diff --git a/.github/workflows/require-design-files.yml b/.github/workflows/require-design-files.yml new file mode 100644 index 0000000..112b673 --- /dev/null +++ b/.github/workflows/require-design-files.yml @@ -0,0 +1,164 @@ +name: Validate PR designs + +on: + pull_request: + types: [opened, synchronize, reopened, ready_for_review] + paths: + - "designs/**" + +permissions: + contents: read + +jobs: + validate: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + with: + fetch-depth: 0 + + - name: Validate required design files + shell: bash + run: | + set -euo pipefail + + BASE_REF="origin/${{ github.base_ref }}" + HEAD_SHA="${{ github.sha }}" + git fetch origin "${{ github.base_ref }}" --no-tags --prune + + techs=(sky130hd asap7 nangate45) + + # Collect changed file paths for A/M (and treat R* as changed using new path field). + mapfile -t changed_paths < <( + git diff --name-status "${BASE_REF}...${HEAD_SHA}" \ + | awk ' + $1=="A" || $1=="M" {print $2} + $1 ~ /^R/ {print $3} + ' + ) + + relevant_paths=() + for p in "${changed_paths[@]}"; do + if [[ "$p" =~ ^designs/src/[^/]+/ ]] || [[ "$p" =~ ^designs/[^/]+/[^/]+/ ]]; then + relevant_paths+=("$p") + fi + done + + if (( ${#relevant_paths[@]} == 0 )); then + echo "No changes to designs/src// or designs///. Nothing to validate." + exit 0 + fi + + declare -A touched_src_design=() # key: + declare -A touched_tech_design=() # key: / + + for p in "${changed_paths[@]}"; do + if [[ "$p" =~ ^designs/src/([^/]+)/ ]]; then + touched_src_design["${BASH_REMATCH[1]}"]=1 + continue + fi + + if [[ "$p" =~ ^designs/([^/]+)/([^/]+)/ ]]; then + t="${BASH_REMATCH[1]}" + d="${BASH_REMATCH[2]}" + for allowed in "${techs[@]}"; do + if [[ "$t" == "$allowed" ]]; then + touched_tech_design["$t/$d"]=1 + break + fi + done + fi + done + + echo "Design's with new or updated designs/src/ files:" + if (( ${#touched_src_design[@]} == 0 )); then + echo " - (none)" + else + for d in "${!touched_src_design[@]}"; do echo " - $d"; done + fi + + echo "Design's with new/updated designs// files:" + if (( ${#touched_tech_design[@]} == 0 )); then + echo " - (none)" + else + for td in "${!touched_tech_design[@]}"; do echo " - $td"; done + fi + + # REQUIRED files relative to designs/src// + required_src=( + "file:verilog.mk" + "file:LICENSE" + "dir:dev" + ) + + # REQUIRED files relative to designs/// + # Both config.mk and constraint.sdc are checked recursively (see below), + # so this list is intentionally empty but kept for future flat-check additions. + required_tech=() + + missing=0 + + # Enforce src rules ONLY for src designs touched by PR + for d in "${!touched_src_design[@]}"; do + src_root="designs/src/$d" + + # Require the directory itself + if [[ ! -d "$src_root" ]]; then + echo "::error file=designs/src::$src_root/ is required (touched by PR) but is missing." + missing=1 + continue + fi + + # Require files inside it + for req in "${required_src[@]}"; do + kind="${req%%:*}" + path="${req#*:}" + + if [[ "$kind" == "file" ]]; then + if [[ ! -f "$src_root/$path" ]]; then + echo "::error file=$src_root/$path::Missing required file: $src_root/$path" + missing=1 + fi + elif [[ "$kind" == "dir" ]]; then + if [[ ! -d "$src_root/$path" ]]; then + echo "::error file=$src_root/$path::Missing required directory: $src_root/$path/" + missing=1 + fi + fi + done + done + + # Enforce tech rules ONLY for tech/design trees touched by PR + for td in "${!touched_tech_design[@]}"; do + t="${td%%/*}" + d="${td#*/}" + tech_root="designs/$t/$d" + + if [[ ! -d "$tech_root" ]]; then + echo "::error file=designs/$t::$tech_root/ is touched by PR but directory is missing." + missing=1 + continue + fi + + # Check required files recursively — each may live directly in / or in any subdir. + for req_file in config.mk constraint.sdc; do + if ! find "$tech_root" -name "$req_file" -type f -print -quit | grep -q .; then + echo "::error file=$tech_root::Missing required file: $req_file (expected anywhere under $tech_root/)" + missing=1 + fi + done + + for rel in "${required_tech[@]}"; do + if [[ ! -f "$tech_root/$rel" ]]; then + echo "::error file=$tech_root/$rel::Missing required file: $tech_root/$rel" + missing=1 + fi + done + done + + if (( missing )); then + echo "Validation failed." + exit 1 + fi + + echo "Validation passed." \ No newline at end of file diff --git a/.gitignore b/.gitignore index 53c287f..a7b06d3 100644 --- a/.gitignore +++ b/.gitignore @@ -8,4 +8,17 @@ objects .dev* .venv sv2v -**/dev/liteeth_builds \ No newline at end of file +**/dev/liteeth_builds +**/srecord/ +**/bazel +**/sv2v*/ +**/python-*/ +**/systemc-*/ +**/perl-*/ +**/_build*/ +**/openssl*/ +**/_installed/ +**/_tarballs/ +**/*.log +**/packages/ +**/generated/ \ No newline at end of file diff --git a/.gitmodules b/.gitmodules index 0985f06..8ed0af6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,15 +7,19 @@ [submodule "designs/src/minimax/dev/repo"] path = designs/src/minimax/dev/repo url = https://github.com/gsmecher/minimax.git -[submodule "designs/src/NyuziProcessor/dev/repo"] - path = designs/src/NyuziProcessor/dev/repo - url = https://github.com/jbush001/NyuziProcessor.git [submodule "designs/src/liteeth/dev/liteeth"] path = designs/src/liteeth/dev/repo url = https://github.com/enjoy-digital/liteeth.git [submodule "designs/src/cnn/dev/repo"] path = designs/src/cnn/dev/repo url = https://github.com/NNgen/nngen +[submodule "designs/src/NVDLA/dev/repo"] + path = designs/src/NVDLA/dev/repo + url = https://github.com/nvdla/hw.git + branch = nv_small +[submodule "designs/src/coralnpu/dev/repo"] + path = designs/src/coralnpu/dev/repo + url = https://github.com/google-coral/coralnpu.git [submodule "designs/src/gemmini/dev/repo"] path = designs/src/gemmini/dev/repo url = https://github.com/ucb-bar/gemmini.git @@ -25,3 +29,9 @@ [submodule "designs/src/sha3/dev/repo"] path = designs/src/sha3/dev/repo url = https://github.com/ucb-bar/sha3 +[submodule "FakeRAM"] + path = FakeRAM + url = https://github.com/VLSIDA/bsg_fakeram.git +[submodule "designs/src/vortex/dev/repo"] + path = designs/src/vortex/dev/repo + url = https://github.com/vortexgpgpu/vortex.git diff --git a/FakeRAM b/FakeRAM new file mode 160000 index 0000000..fae05c0 --- /dev/null +++ b/FakeRAM @@ -0,0 +1 @@ +Subproject commit fae05c0c94051441a3d4457cae8db6aaa97f5207 diff --git a/Makefile b/Makefile index 69467f2..1bf742a 100644 --- a/Makefile +++ b/Makefile @@ -1,70 +1,35 @@ ### Comprehensive Design List (nangate45, sky130hd, asap7) ### -# -# DESIGN_CONFIG=./designs/nangate45/lfsr_prbs_gen/config.mk +# # DESIGN_CONFIG=./designs/nangate45/minimax/config.mk # DESIGN_CONFIG=./designs/nangate45/NyuziProcessor/config.mk # -# DESIGN_CONFIG=./designs/sky130hd/lfsr_prbs_gen/config.mk # DESIGN_CONFIG=./designs/sky130hd/minimax/config.mk # +# DESIGN_CONFIG=./designs/asap7/sha3/config.mk +# DESIGN_CONFIG=./designs/asap7/gemmini/config.mk +# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_a/config.mk +# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_c/config.mk +# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_m/config.mk +# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_o/config.mk +# DESIGN_CONFIG=./designs/asap7/NVDLA/NVDLA_partition_p/config.mk +# DESIGN_CONFIG=./designs/asap7/coralnpu/config.mk # DESIGN_CONFIG=./designs/asap7/minimax/config.mk -# DESIGN_CONFIG=./designs/asap7/lfsr_prbs_gen/config.mk # DESIGN_CONFIG=./designs/asap7/NyuziProcessor/config.mk # DESIGN_CONFIG=./designs/asap7/gemmini/config.mk # DESIGN_CONFIG=./designs/asap7/bp_processor/bp_quad/config.mk -DESIGN_CONFIG ?= ./designs/nangate45/lfsr_prbs_gen/config.mk +DESIGN_CONFIG ?= ./designs/asap7/sha3/config.mk + -include OpenROAD-flow-scripts/flow/Makefile -# Designs with RAM macros use FakeRAM (LEF generated for pins, no internal logic) -# Check if calling "dev" with an ORFS command or by itself. -DEV_RUN_TAG?=x -.PHONY: dev -ifeq ($(firstword $(MAKECMDGOALS)),dev) -DEV_RUN_TAG:=$(shell date +%s%N)$(shell bash -c "echo $$RANDOM") -ifneq ($(lastword $(MAKECMDGOALS)),dev) -dev: ;@: -else -$(info Starting dev run) -dev: .dev-run-$(DESIGN_NAME)-$(DEV_RUN_TAG) -endif -endif -export DEV_RUN_TAG +.PHONY: update_rtl +update_rtl: + @$(MAKE) DO_UPDATE=1 do-update -.PHONY: do-dev-setup -do-dev-setup: +.PHONY: do-update +do-update: git submodule init $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/repo git submodule update $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/repo - # Check if a setup.sh script exists for the current design @if [ -f "$(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/setup.sh" ]; then \ bash $(BENCH_DESIGN_HOME)/src/$(DEV_DESIGN_HOME)/setup.sh; \ fi - -# .dev-suite-run flag is necessary because ORFS makefile unsets all vars for recursion -.DELETE_ON_ERROR: -.dev-run%: - # Change Design Nickname to avoid conflict between default and dev designs - : > $@ - $(MAKE) do-dev-setup - @if [ ! -f "$(RESULTS_DIR)/1_synth.v" ]; then \ - $(MAKE) finish; \ - elif [ ! -f "$(RESULTS_DIR)/2_floorplan.odb" ]; then \ - $(MAKE) do-floorplan do-place do-cts do-route do-finish; \ - elif [ ! -f "$(RESULTS_DIR)/3_place.odb" ]; then \ - $(MAKE) do-place do-cts do-route do-finish; \ - elif [ ! -f "$(RESULTS_DIR)/4_cts.odb" ]; then \ - $(MAKE) do-cts do-route do-finish; \ - elif [ ! -f "$(RESULTS_DIR)/5_route.odb" ]; then \ - $(MAKE) do-route do-finish; \ - else \ - $(MAKE) do-finish; \ - fi - rm -f $@ - -.PHONY: clean_design - -# DEV_SRC can be used to clean up any dev-dependent source files -clean_design: - rm -rf $(DEV_SRC) - -clean_all: clean_design - + @echo "Successfully updated Verilog RTL!" diff --git a/OpenROAD-flow-scripts b/OpenROAD-flow-scripts index f53fbce..9a13bc5 160000 --- a/OpenROAD-flow-scripts +++ b/OpenROAD-flow-scripts @@ -1 +1 @@ -Subproject commit f53fbce71af0e7965b3fa76396ff6d3e8121b6bb +Subproject commit 9a13bc5678e9a5dbe451bbb6a8007083968b8c66 diff --git a/designs/asap7/NVDLA/partition_a/config.mk b/designs/asap7/NVDLA/partition_a/config.mk new file mode 100644 index 0000000..75bdf03 --- /dev/null +++ b/designs/asap7/NVDLA/partition_a/config.mk @@ -0,0 +1,24 @@ +export DESIGN_NAME = NV_NVDLA_partition_a +export PLATFORM = asap7 +export DESIGN_NICKNAME = NVDLA +export DESIGN_RESULTS_NAME = NVDLA_partition_a + +-include $(BENCH_DESIGN_HOME)/src/NVDLA/verilog.mk + +export SYNTH_HIERARCHICAL = 1 + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/NVDLA/partition_a/constraint.sdc + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_256x16_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_272x16_1r1w.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_256x16_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_272x16_1r1w.lib + +export CORE_UTILIZATION = 55 + +export PLACE_DENSITY_LB_ADDON = 0.2 + +export MACRO_PLACE_HALO = 5 5 + +export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_a/constraint.sdc b/designs/asap7/NVDLA/partition_a/constraint.sdc new file mode 100644 index 0000000..7c23d67 --- /dev/null +++ b/designs/asap7/NVDLA/partition_a/constraint.sdc @@ -0,0 +1,40 @@ +# =================================================================== +# Using Contents of File: syn/cons/NV_NVDLA_partition_c.sdc +# NVDLA Open Source Project +# +# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the +# NVDLA Open Hardware License; see the "LICENSE.txt" file that came +# with this distribution for more information. +# =================================================================== +current_design NV_NVDLA_partition_a + +set clk_name nvdla_core_clk +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period 1500 -waveform {0 750} $clk_port +set_clock_transition -rise -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -rise -max 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -max 0.1 [get_clocks {nvdla_core_clk}] + + + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr 1500 * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr 1500 * $clk_io_pct] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] +set_ideal_network [get_ports test_mode] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_c/config.mk b/designs/asap7/NVDLA/partition_c/config.mk new file mode 100644 index 0000000..3505b0d --- /dev/null +++ b/designs/asap7/NVDLA/partition_c/config.mk @@ -0,0 +1,30 @@ +export DESIGN_NAME = NV_NVDLA_partition_c +export PLATFORM = asap7 +export DESIGN_NICKNAME = NVDLA +export DESIGN_RESULTS_NAME = NVDLA_partition_c + +-include $(BENCH_DESIGN_HOME)/src/NVDLA/verilog.mk + +export SYNTH_HIERARCHICAL = 1 + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/NVDLA/partition_c/constraint.sdc + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_64x16_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_6x128_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_66x8_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_11x128_1r1w.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_64x16_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_6x128_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_66x8_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_11x128_1r1w.lib + +export CORE_UTILIZATION = 50 + +export PLACE_DENSITY_LB_ADDON = 0.25 + +export MACRO_PLACE_HALO = 2 2 + +export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_c/constraint.sdc b/designs/asap7/NVDLA/partition_c/constraint.sdc new file mode 100644 index 0000000..2c092e7 --- /dev/null +++ b/designs/asap7/NVDLA/partition_c/constraint.sdc @@ -0,0 +1,51 @@ +# =================================================================== +# Using Contents of File: syn/cons/NV_NVDLA_partition_c.sdc +# NVDLA Open Source Project +# +# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the +# NVDLA Open Hardware License; see the "LICENSE.txt" file that came +# with this distribution for more information. +# =================================================================== + +current_design NV_NVDLA_partition_c + +set clk_name nvdla_core_clk +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period 1500 -waveform {0 750} $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr 1500 * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr 1500 * $clk_io_pct] -clock $clk_name [all_outputs] + +set_clock_transition -rise -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -rise -max 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -max 0.1 [get_clocks {nvdla_core_clk}] + +set_ideal_network [get_ports {global_clk_ovr_on}] +set_ideal_network [get_ports {test_mode}] +set_ideal_network [get_ports {direct_reset_}] +set_ideal_network [get_ports {dla_reset_rstn}] +set_ideal_network [get_ports {nvdla_core_clk}] +set_ideal_network [get_ports {nvdla_clk_ovr_on}] +set_ideal_network [get_ports {tmc2slcg_disable_clock_gating}] +set_ideal_network [get_ports {pwrbus_ram_pd*}] + +set_false_path -to [get_pin */RESETN] +set_false_path -to [get_pin */SETN] +set_ideal_network [get_ports {global_clk_ovr_on}] +set_ideal_network [get_ports {test_mode}] +set_ideal_network [get_ports {direct_reset_}] +set_ideal_network [get_ports {dla_reset_rstn}] +set_ideal_network [get_ports {nvdla_core_clk}] +set_ideal_network [get_ports {nvdla_clk_ovr_on}] +set_ideal_network [get_ports {tmc2slcg_disable_clock_gating}] +set_ideal_network [get_ports {pwrbus_ram_pd*}] + +set_max_fanout 128 [current_design] + +set_wire_load_mode enclosed diff --git a/designs/asap7/NVDLA/partition_m/config.mk b/designs/asap7/NVDLA/partition_m/config.mk new file mode 100644 index 0000000..94d0493 --- /dev/null +++ b/designs/asap7/NVDLA/partition_m/config.mk @@ -0,0 +1,18 @@ +export DESIGN_NAME = NV_NVDLA_partition_m +export PLATFORM = asap7 +export DESIGN_NICKNAME = NVDLA +export DESIGN_RESULTS_NAME = NVDLA_partition_m + +-include $(BENCH_DESIGN_HOME)/src/NVDLA/verilog.mk + +export SYNTH_HIERARCHICAL = 1 + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/NVDLA/partition_m/constraint.sdc + +export CORE_UTILIZATION = 55 + +export PLACE_DENSITY_LB_ADDON = 0.2 + +export MACRO_PLACE_HALO = 5 5 + +export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_m/constraint.sdc b/designs/asap7/NVDLA/partition_m/constraint.sdc new file mode 100644 index 0000000..669974c --- /dev/null +++ b/designs/asap7/NVDLA/partition_m/constraint.sdc @@ -0,0 +1,39 @@ +# =================================================================== +# Using Contents of File: syn/cons/NV_NVDLA_partition_m.sdc +# NVDLA Open Source Project +# +# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the +# NVDLA Open Hardware License; see the "LICENSE.txt" file that came +# with this distribution for more information. +# =================================================================== +current_design NV_NVDLA_partition_m + +set clk_name nvdla_core_clk +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period 1500 -waveform {0 750} $clk_port +set_clock_transition -rise -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -rise -max 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -max 0.1 [get_clocks {nvdla_core_clk}] + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr 1500 * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr 1500 * $clk_io_pct] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] +set_ideal_network [get_ports test_mode] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] +set_false_path -to [get_pin */RESETN] +set_false_path -to [get_pin */SETN] \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_o/config.mk b/designs/asap7/NVDLA/partition_o/config.mk new file mode 100644 index 0000000..245bc50 --- /dev/null +++ b/designs/asap7/NVDLA/partition_o/config.mk @@ -0,0 +1,38 @@ +export DESIGN_NAME = NV_NVDLA_partition_o +export PLATFORM = asap7 +export DESIGN_NICKNAME = NVDLA +export DESIGN_RESULTS_NAME = NVDLA_partition_o + +-include $(BENCH_DESIGN_HOME)/src/NVDLA/verilog.mk + +export SYNTH_HIERARCHICAL = 1 + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/NVDLA/partition_o/constraint.sdc + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_18x128_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_8x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_4x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_7x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_66x64_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_15x80_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_22x60_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_32x128_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_9x80_1r1w.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_18x128_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_8x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_4x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_7x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_66x64_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_15x80_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_22x60_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_32x128_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_9x80_1r1w.lib + +export CORE_UTILIZATION = 45 + +export PLACE_DENSITY_LB_ADDON = 0.15 + +export MACRO_PLACE_HALO = 7 7 + +export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_o/constraint.sdc b/designs/asap7/NVDLA/partition_o/constraint.sdc new file mode 100644 index 0000000..4c1f41a --- /dev/null +++ b/designs/asap7/NVDLA/partition_o/constraint.sdc @@ -0,0 +1,48 @@ +# =================================================================== +# Using Contents of File: syn/cons/NV_NVDLA_partition_o.sdc +# NVDLA Open Source Project +# +# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the +# NVDLA Open Hardware License; see the "LICENSE.txt" file that came +# with this distribution for more information. +# =================================================================== +current_design NV_NVDLA_partition_o + +set clk_name nvdla_core_clk +set clk_falcon_name nvdla_falcon_clk +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] +set clk_falcon_port [get_ports $clk_falcon_name] + +create_clock -name $clk_name -period 2000 -waveform {0 1000} $clk_port +set_clock_transition -rise -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -rise -max 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -max 0.1 [get_clocks {nvdla_core_clk}] + +create_clock -name $clk_falcon_name -period 2500 -waveform {0 1250} $clk_falcon_port +set_clock_transition -rise -min 0.1 [get_clocks {nvdla_falcon_clk}] +set_clock_transition -rise -max 0.1 [get_clocks {nvdla_falcon_clk}] +set_clock_transition -fall -min 0.1 [get_clocks {nvdla_falcon_clk}] +set_clock_transition -fall -max 0.1 [get_clocks {nvdla_falcon_clk}] + + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] "^($clk_port|$clk_falcon_port)$"] + +set_input_delay [expr 2000 * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr 2000 * $clk_io_pct] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports test_mode] +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network [get_nets nvdla_core_rstn] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_clocks nvdla_core_clk] -to [get_clocks nvdla_falcon_clk] +set_false_path -from [get_clocks nvdla_falcon_clk] -to [get_clocks nvdla_core_clk] \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_p/config.mk b/designs/asap7/NVDLA/partition_p/config.mk new file mode 100644 index 0000000..3d0e78a --- /dev/null +++ b/designs/asap7/NVDLA/partition_p/config.mk @@ -0,0 +1,28 @@ +export DESIGN_NAME = NV_NVDLA_partition_p +export PLATFORM = asap7 +export DESIGN_NICKNAME = NVDLA +export DESIGN_RESULTS_NAME = NVDLA_partition_p + +-include $(BENCH_DESIGN_HOME)/src/NVDLA/verilog.mk + +export SYNTH_HIERARCHICAL = 1 + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/NVDLA/partition_p/constraint.sdc + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_16x160_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_65x160_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_14x80_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_66x80_1r1w.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_16x160_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_65x160_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_14x80_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_66x80_1r1w.lib + +export CORE_UTILIZATION = 45 + +export PLACE_DENSITY_LB_ADDON = 0.25 + +export MACRO_PLACE_HALO = 5 5 + +export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NVDLA/partition_p/constraint.sdc b/designs/asap7/NVDLA/partition_p/constraint.sdc new file mode 100644 index 0000000..db2906a --- /dev/null +++ b/designs/asap7/NVDLA/partition_p/constraint.sdc @@ -0,0 +1,39 @@ +# =================================================================== +# Using contents of File: syn/cons/NV_NVDLA_partition_p.sdc +# NVDLA Open Source Project +# +# Copyright (c) 2016 – 2017 NVIDIA Corporation. Licensed under the +# NVDLA Open Hardware License; see the "LICENSE.txt" file that came +# with this distribution for more information. +# =================================================================== +current_design NV_NVDLA_partition_p + +set clk_name nvdla_core_clk +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period 1500 -waveform {0 750} $clk_port +set_clock_transition -rise -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -rise -max 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -min 0.1 [get_clocks {nvdla_core_clk}] +set_clock_transition -fall -max 0.1 [get_clocks {nvdla_core_clk}] + + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr 1500 * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr 1500 * $clk_io_pct] -clock $clk_name [all_outputs] + +set_ideal_network [get_ports direct_reset_] +set_ideal_network [get_ports dla_reset_rstn] +set_ideal_network -no_propagate [get_nets nvdla_core_rstn] +set_ideal_network [get_ports test_mode] + +set_false_path -from [get_ports direct_reset_] +set_false_path -from [get_ports dla_reset_rstn] +set_false_path -from [get_ports test_mode] +set_false_path -from [get_ports pwrbus_ram_pd*] +set_false_path -from [get_ports tmc2slcg_disable_clock_gating] +set_false_path -from [get_ports global_clk_ovr_on] +set_false_path -from [get_ports nvdla_clk_ovr_on] \ No newline at end of file diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_10x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_10x64_1r1w.lef new file mode 100644 index 0000000..f0fb2cf --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_10x64_1r1w.lef @@ -0,0 +1,397 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_10x64_1r1w + FOREIGN fakeram_10x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 11.551 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.476 0.072 1.500 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 1.476 9.643 1.500 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END w0_wd_in[9] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 11.497 0.225 11.551 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 11.497 1.125 11.551 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 11.497 2.025 11.551 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 11.497 2.925 11.551 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 11.497 3.825 11.551 ; + END + END r0_rd_out[9] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.276 0.072 6.300 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.676 9.643 2.700 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 3.876 9.643 3.900 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 5.076 9.643 5.100 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.276 9.643 6.300 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.476 9.643 7.500 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.676 9.643 8.700 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 11.497 4.725 11.551 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 11.497 5.625 11.551 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 11.497 6.525 11.551 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 11.497 7.425 11.551 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 11.497 8.325 11.551 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 11.551 ; + LAYER M2 ; + RECT 0 0 9.643 11.551 ; + LAYER M3 ; + RECT 0 0 9.643 11.551 ; + LAYER M4 ; + RECT 0 0 9.643 11.551 ; + END +END fakeram_10x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_116x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_116x64_1r1w.lef new file mode 100644 index 0000000..944b84f --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_116x64_1r1w.lef @@ -0,0 +1,2329 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_116x64_1r1w + FOREIGN fakeram_116x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 34.954 BY 20.423 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.804 0.072 0.828 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.332 0.072 1.356 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.916 0.072 2.940 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.084 0.072 6.108 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.140 0.072 7.164 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.252 0.072 9.276 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.308 0.072 10.332 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.892 0.072 11.916 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.420 0.072 12.444 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.476 0.072 13.500 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 0.276 34.954 0.300 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 0.804 34.954 0.828 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 1.332 34.954 1.356 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 1.860 34.954 1.884 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 2.388 34.954 2.412 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 2.916 34.954 2.940 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 3.444 34.954 3.468 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 3.972 34.954 3.996 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 4.500 34.954 4.524 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 5.028 34.954 5.052 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 5.556 34.954 5.580 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 6.084 34.954 6.108 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 6.612 34.954 6.636 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 7.140 34.954 7.164 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 7.668 34.954 7.692 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 8.196 34.954 8.220 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 8.724 34.954 8.748 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 9.252 34.954 9.276 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 9.780 34.954 9.804 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 10.308 34.954 10.332 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 10.836 34.954 10.860 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 11.364 34.954 11.388 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 11.892 34.954 11.916 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 12.420 34.954 12.444 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 12.948 34.954 12.972 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 13.476 34.954 13.500 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 14.004 34.954 14.028 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 14.532 34.954 14.556 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 15.060 34.954 15.084 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[115] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 20.369 0.225 20.423 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 20.369 0.765 20.423 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 20.369 1.305 20.423 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 20.369 1.845 20.423 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 20.369 2.385 20.423 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 20.369 2.925 20.423 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 20.369 3.465 20.423 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 20.369 4.005 20.423 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 20.369 4.545 20.423 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 20.369 5.085 20.423 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 20.369 5.625 20.423 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 20.369 6.165 20.423 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 20.369 6.705 20.423 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 20.369 7.245 20.423 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 20.369 7.785 20.423 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 20.369 8.325 20.423 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 20.369 8.865 20.423 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 20.369 9.405 20.423 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 20.369 9.945 20.423 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 20.369 10.485 20.423 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 20.369 11.025 20.423 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 20.369 11.565 20.423 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 20.369 12.105 20.423 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 20.369 12.645 20.423 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 20.369 13.185 20.423 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 20.369 13.725 20.423 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 20.369 14.265 20.423 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 20.369 14.805 20.423 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 20.369 15.345 20.423 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 20.369 15.885 20.423 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 20.369 16.425 20.423 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 20.369 16.965 20.423 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 20.369 17.505 20.423 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 20.369 18.045 20.423 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 20.369 18.585 20.423 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 20.369 19.125 20.423 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 20.369 19.665 20.423 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 20.369 20.205 20.423 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 20.369 20.745 20.423 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 20.369 21.285 20.423 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 20.369 21.825 20.423 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 20.369 22.365 20.423 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 20.369 22.905 20.423 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 20.369 23.445 20.423 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 20.369 23.985 20.423 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 20.369 24.525 20.423 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 20.369 25.065 20.423 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 20.369 25.605 20.423 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 20.369 26.145 20.423 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 20.369 26.685 20.423 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 20.369 27.225 20.423 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 20.369 27.765 20.423 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 20.369 28.305 20.423 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 20.369 28.845 20.423 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 20.369 29.385 20.423 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 20.369 29.925 20.423 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 20.369 30.465 20.423 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 20.369 31.005 20.423 ; + END + END r0_rd_out[115] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.588 0.072 15.612 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.644 0.072 16.668 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 15.588 34.954 15.612 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 16.116 34.954 16.140 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 16.644 34.954 16.668 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.700 0.072 17.724 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.228 0.072 18.252 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 17.172 34.954 17.196 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 17.700 34.954 17.724 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 34.882 18.228 34.954 18.252 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 20.369 31.545 20.423 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 20.369 32.085 20.423 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 20.369 32.625 20.423 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 20.369 33.165 20.423 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 20.369 33.705 20.423 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 34.738 0.336 ; + RECT 0.216 1.008 34.738 1.104 ; + RECT 0.216 1.776 34.738 1.872 ; + RECT 0.216 2.544 34.738 2.640 ; + RECT 0.216 3.312 34.738 3.408 ; + RECT 0.216 4.080 34.738 4.176 ; + RECT 0.216 4.848 34.738 4.944 ; + RECT 0.216 5.616 34.738 5.712 ; + RECT 0.216 6.384 34.738 6.480 ; + RECT 0.216 7.152 34.738 7.248 ; + RECT 0.216 7.920 34.738 8.016 ; + RECT 0.216 8.688 34.738 8.784 ; + RECT 0.216 9.456 34.738 9.552 ; + RECT 0.216 10.224 34.738 10.320 ; + RECT 0.216 10.992 34.738 11.088 ; + RECT 0.216 11.760 34.738 11.856 ; + RECT 0.216 12.528 34.738 12.624 ; + RECT 0.216 13.296 34.738 13.392 ; + RECT 0.216 14.064 34.738 14.160 ; + RECT 0.216 14.832 34.738 14.928 ; + RECT 0.216 15.600 34.738 15.696 ; + RECT 0.216 16.368 34.738 16.464 ; + RECT 0.216 17.136 34.738 17.232 ; + RECT 0.216 17.904 34.738 18.000 ; + RECT 0.216 18.672 34.738 18.768 ; + RECT 0.216 19.440 34.738 19.536 ; + RECT 0.216 20.208 34.738 20.304 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 34.738 0.336 ; + RECT 0.216 1.008 34.738 1.104 ; + RECT 0.216 1.776 34.738 1.872 ; + RECT 0.216 2.544 34.738 2.640 ; + RECT 0.216 3.312 34.738 3.408 ; + RECT 0.216 4.080 34.738 4.176 ; + RECT 0.216 4.848 34.738 4.944 ; + RECT 0.216 5.616 34.738 5.712 ; + RECT 0.216 6.384 34.738 6.480 ; + RECT 0.216 7.152 34.738 7.248 ; + RECT 0.216 7.920 34.738 8.016 ; + RECT 0.216 8.688 34.738 8.784 ; + RECT 0.216 9.456 34.738 9.552 ; + RECT 0.216 10.224 34.738 10.320 ; + RECT 0.216 10.992 34.738 11.088 ; + RECT 0.216 11.760 34.738 11.856 ; + RECT 0.216 12.528 34.738 12.624 ; + RECT 0.216 13.296 34.738 13.392 ; + RECT 0.216 14.064 34.738 14.160 ; + RECT 0.216 14.832 34.738 14.928 ; + RECT 0.216 15.600 34.738 15.696 ; + RECT 0.216 16.368 34.738 16.464 ; + RECT 0.216 17.136 34.738 17.232 ; + RECT 0.216 17.904 34.738 18.000 ; + RECT 0.216 18.672 34.738 18.768 ; + RECT 0.216 19.440 34.738 19.536 ; + RECT 0.216 20.208 34.738 20.304 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 34.954 20.423 ; + LAYER M2 ; + RECT 0 0 34.954 20.423 ; + LAYER M3 ; + RECT 0 0 34.954 20.423 ; + LAYER M4 ; + RECT 0 0 34.954 20.423 ; + END +END fakeram_116x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_11x128_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_11x128_1r1w.lef new file mode 100644 index 0000000..efd6b3a --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_11x128_1r1w.lef @@ -0,0 +1,461 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_11x128_1r1w + FOREIGN fakeram_11x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 22.348 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.436 9.643 2.460 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.596 9.643 4.620 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.963 0.000 0.981 0.054 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 0.000 1.737 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.475 0.000 2.493 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[10] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.499 0.000 5.517 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.011 0.000 7.029 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 22.294 0.225 22.348 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.035 22.294 1.053 22.348 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.863 22.294 1.881 22.348 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.691 22.294 2.709 22.348 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.519 22.294 3.537 22.348 ; + END + END r0_rd_out[10] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.756 9.643 6.780 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.916 9.643 8.940 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.076 9.643 11.100 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 13.236 9.643 13.260 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 15.396 9.643 15.420 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 17.556 9.643 17.580 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 22.294 4.365 22.348 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.175 22.294 5.193 22.348 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.003 22.294 6.021 22.348 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 22.294 6.849 22.348 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.659 22.294 7.677 22.348 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 22.348 ; + LAYER M2 ; + RECT 0 0 9.643 22.348 ; + LAYER M3 ; + RECT 0 0 9.643 22.348 ; + LAYER M4 ; + RECT 0 0 9.643 22.348 ; + END +END fakeram_11x128_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_11x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_11x256_1r1w.lef new file mode 100644 index 0000000..5798cb9 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_11x256_1r1w.lef @@ -0,0 +1,535 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_11x256_1r1w + FOREIGN fakeram_11x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 43.776 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.164 9.643 4.188 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.052 9.643 8.076 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.963 0.000 0.981 0.054 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 0.000 1.737 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.475 0.000 2.493 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[10] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.499 0.000 5.517 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.011 0.000 7.029 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 43.722 0.225 43.776 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.035 43.722 1.053 43.776 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.863 43.722 1.881 43.776 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.691 43.722 2.709 43.776 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.519 43.722 3.537 43.776 ; + END + END r0_rd_out[10] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.940 9.643 11.964 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 15.828 9.643 15.852 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 19.716 9.643 19.740 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 23.604 9.643 23.628 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.268 0.072 35.292 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 27.492 9.643 27.516 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 31.380 9.643 31.404 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 35.268 9.643 35.292 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 39.156 9.643 39.180 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 43.722 4.365 43.776 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.175 43.722 5.193 43.776 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.003 43.722 6.021 43.776 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 43.722 6.849 43.776 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.659 43.722 7.677 43.776 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 43.776 ; + LAYER M2 ; + RECT 0 0 9.643 43.776 ; + LAYER M3 ; + RECT 0 0 9.643 43.776 ; + LAYER M4 ; + RECT 0 0 9.643 43.776 ; + END +END fakeram_11x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_144x160_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_144x160_1r1w.lef new file mode 100644 index 0000000..82a14c1 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_144x160_1r1w.lef @@ -0,0 +1,2917 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_144x160_1r1w + FOREIGN fakeram_144x160_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 43.391 BY 38.837 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 0.276 43.391 0.300 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 1.140 43.391 1.164 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 2.004 43.391 2.028 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 2.868 43.391 2.892 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 3.732 43.391 3.756 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 4.596 43.391 4.620 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 5.460 43.391 5.484 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 6.324 43.391 6.348 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 7.188 43.391 7.212 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 8.052 43.391 8.076 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 8.916 43.391 8.940 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 9.780 43.391 9.804 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 10.644 43.391 10.668 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 11.508 43.391 11.532 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 12.372 43.391 12.396 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 13.236 43.391 13.260 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 14.100 43.391 14.124 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 14.964 43.391 14.988 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 15.828 43.391 15.852 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 16.692 43.391 16.716 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 17.556 43.391 17.580 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 18.420 43.391 18.444 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 19.284 43.391 19.308 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 20.148 43.391 20.172 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 21.012 43.391 21.036 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 21.876 43.391 21.900 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 22.740 43.391 22.764 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 23.604 43.391 23.628 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 24.468 43.391 24.492 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 25.332 43.391 25.356 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 26.196 43.391 26.220 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 27.060 43.391 27.084 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 27.924 43.391 27.948 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 28.788 43.391 28.812 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 29.652 43.391 29.676 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 30.516 43.391 30.540 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[143] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 38.783 0.225 38.837 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 38.783 0.765 38.837 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 38.783 1.305 38.837 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 38.783 1.845 38.837 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 38.783 2.385 38.837 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 38.783 2.925 38.837 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 38.783 3.465 38.837 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 38.783 4.005 38.837 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 38.783 4.545 38.837 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 38.783 5.085 38.837 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 38.783 5.625 38.837 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 38.783 6.165 38.837 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 38.783 6.705 38.837 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 38.783 7.245 38.837 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 38.783 7.785 38.837 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 38.783 8.325 38.837 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 38.783 8.865 38.837 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 38.783 9.405 38.837 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 38.783 9.945 38.837 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 38.783 10.485 38.837 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 38.783 11.025 38.837 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 38.783 11.565 38.837 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 38.783 12.105 38.837 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 38.783 12.645 38.837 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 38.783 13.185 38.837 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 38.783 13.725 38.837 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 38.783 14.265 38.837 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 38.783 14.805 38.837 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 38.783 15.345 38.837 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 38.783 15.885 38.837 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 38.783 16.425 38.837 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 38.783 16.965 38.837 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 38.783 17.505 38.837 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 38.783 18.045 38.837 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 38.783 18.585 38.837 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 38.783 19.125 38.837 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 38.783 19.665 38.837 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 38.783 20.205 38.837 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 38.783 20.745 38.837 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 38.783 21.285 38.837 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 38.783 21.825 38.837 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 38.783 22.365 38.837 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 38.783 22.905 38.837 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 38.783 23.445 38.837 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 38.783 23.985 38.837 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 38.783 24.525 38.837 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 38.783 25.065 38.837 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 38.783 25.605 38.837 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 38.783 26.145 38.837 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 38.783 26.685 38.837 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 38.783 27.225 38.837 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 38.783 27.765 38.837 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 38.783 28.305 38.837 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 38.783 28.845 38.837 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 38.783 29.385 38.837 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 38.783 29.925 38.837 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 38.783 30.465 38.837 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 38.783 31.005 38.837 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 38.783 31.545 38.837 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 38.783 32.085 38.837 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 38.783 32.625 38.837 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 38.783 33.165 38.837 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 38.783 33.705 38.837 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 38.783 34.245 38.837 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 38.783 34.785 38.837 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 38.783 35.325 38.837 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 38.783 35.865 38.837 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 38.783 36.405 38.837 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 38.783 36.945 38.837 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 38.783 37.485 38.837 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 38.783 38.025 38.837 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 38.783 38.565 38.837 ; + END + END r0_rd_out[143] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 31.380 43.391 31.404 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 32.244 43.391 32.268 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 33.108 43.391 33.132 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 33.972 43.391 33.996 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 34.836 43.391 34.860 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 35.700 43.391 35.724 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 36.564 43.391 36.588 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 43.319 37.428 43.391 37.452 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 38.783 39.105 38.837 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 38.783 39.645 38.837 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 38.783 40.185 38.837 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 38.783 40.725 38.837 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 38.783 41.265 38.837 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 43.175 0.336 ; + RECT 0.216 1.008 43.175 1.104 ; + RECT 0.216 1.776 43.175 1.872 ; + RECT 0.216 2.544 43.175 2.640 ; + RECT 0.216 3.312 43.175 3.408 ; + RECT 0.216 4.080 43.175 4.176 ; + RECT 0.216 4.848 43.175 4.944 ; + RECT 0.216 5.616 43.175 5.712 ; + RECT 0.216 6.384 43.175 6.480 ; + RECT 0.216 7.152 43.175 7.248 ; + RECT 0.216 7.920 43.175 8.016 ; + RECT 0.216 8.688 43.175 8.784 ; + RECT 0.216 9.456 43.175 9.552 ; + RECT 0.216 10.224 43.175 10.320 ; + RECT 0.216 10.992 43.175 11.088 ; + RECT 0.216 11.760 43.175 11.856 ; + RECT 0.216 12.528 43.175 12.624 ; + RECT 0.216 13.296 43.175 13.392 ; + RECT 0.216 14.064 43.175 14.160 ; + RECT 0.216 14.832 43.175 14.928 ; + RECT 0.216 15.600 43.175 15.696 ; + RECT 0.216 16.368 43.175 16.464 ; + RECT 0.216 17.136 43.175 17.232 ; + RECT 0.216 17.904 43.175 18.000 ; + RECT 0.216 18.672 43.175 18.768 ; + RECT 0.216 19.440 43.175 19.536 ; + RECT 0.216 20.208 43.175 20.304 ; + RECT 0.216 20.976 43.175 21.072 ; + RECT 0.216 21.744 43.175 21.840 ; + RECT 0.216 22.512 43.175 22.608 ; + RECT 0.216 23.280 43.175 23.376 ; + RECT 0.216 24.048 43.175 24.144 ; + RECT 0.216 24.816 43.175 24.912 ; + RECT 0.216 25.584 43.175 25.680 ; + RECT 0.216 26.352 43.175 26.448 ; + RECT 0.216 27.120 43.175 27.216 ; + RECT 0.216 27.888 43.175 27.984 ; + RECT 0.216 28.656 43.175 28.752 ; + RECT 0.216 29.424 43.175 29.520 ; + RECT 0.216 30.192 43.175 30.288 ; + RECT 0.216 30.960 43.175 31.056 ; + RECT 0.216 31.728 43.175 31.824 ; + RECT 0.216 32.496 43.175 32.592 ; + RECT 0.216 33.264 43.175 33.360 ; + RECT 0.216 34.032 43.175 34.128 ; + RECT 0.216 34.800 43.175 34.896 ; + RECT 0.216 35.568 43.175 35.664 ; + RECT 0.216 36.336 43.175 36.432 ; + RECT 0.216 37.104 43.175 37.200 ; + RECT 0.216 37.872 43.175 37.968 ; + RECT 0.216 38.640 43.175 38.736 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 43.175 0.336 ; + RECT 0.216 1.008 43.175 1.104 ; + RECT 0.216 1.776 43.175 1.872 ; + RECT 0.216 2.544 43.175 2.640 ; + RECT 0.216 3.312 43.175 3.408 ; + RECT 0.216 4.080 43.175 4.176 ; + RECT 0.216 4.848 43.175 4.944 ; + RECT 0.216 5.616 43.175 5.712 ; + RECT 0.216 6.384 43.175 6.480 ; + RECT 0.216 7.152 43.175 7.248 ; + RECT 0.216 7.920 43.175 8.016 ; + RECT 0.216 8.688 43.175 8.784 ; + RECT 0.216 9.456 43.175 9.552 ; + RECT 0.216 10.224 43.175 10.320 ; + RECT 0.216 10.992 43.175 11.088 ; + RECT 0.216 11.760 43.175 11.856 ; + RECT 0.216 12.528 43.175 12.624 ; + RECT 0.216 13.296 43.175 13.392 ; + RECT 0.216 14.064 43.175 14.160 ; + RECT 0.216 14.832 43.175 14.928 ; + RECT 0.216 15.600 43.175 15.696 ; + RECT 0.216 16.368 43.175 16.464 ; + RECT 0.216 17.136 43.175 17.232 ; + RECT 0.216 17.904 43.175 18.000 ; + RECT 0.216 18.672 43.175 18.768 ; + RECT 0.216 19.440 43.175 19.536 ; + RECT 0.216 20.208 43.175 20.304 ; + RECT 0.216 20.976 43.175 21.072 ; + RECT 0.216 21.744 43.175 21.840 ; + RECT 0.216 22.512 43.175 22.608 ; + RECT 0.216 23.280 43.175 23.376 ; + RECT 0.216 24.048 43.175 24.144 ; + RECT 0.216 24.816 43.175 24.912 ; + RECT 0.216 25.584 43.175 25.680 ; + RECT 0.216 26.352 43.175 26.448 ; + RECT 0.216 27.120 43.175 27.216 ; + RECT 0.216 27.888 43.175 27.984 ; + RECT 0.216 28.656 43.175 28.752 ; + RECT 0.216 29.424 43.175 29.520 ; + RECT 0.216 30.192 43.175 30.288 ; + RECT 0.216 30.960 43.175 31.056 ; + RECT 0.216 31.728 43.175 31.824 ; + RECT 0.216 32.496 43.175 32.592 ; + RECT 0.216 33.264 43.175 33.360 ; + RECT 0.216 34.032 43.175 34.128 ; + RECT 0.216 34.800 43.175 34.896 ; + RECT 0.216 35.568 43.175 35.664 ; + RECT 0.216 36.336 43.175 36.432 ; + RECT 0.216 37.104 43.175 37.200 ; + RECT 0.216 37.872 43.175 37.968 ; + RECT 0.216 38.640 43.175 38.736 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 43.391 38.837 ; + LAYER M2 ; + RECT 0 0 43.391 38.837 ; + LAYER M3 ; + RECT 0 0 43.391 38.837 ; + LAYER M4 ; + RECT 0 0 43.391 38.837 ; + END +END fakeram_144x160_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_144x248_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_144x248_1r1w.lef new file mode 100644 index 0000000..95f22a9 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_144x248_1r1w.lef @@ -0,0 +1,1643 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_144x248_1r1w + FOREIGN fakeram_144x248_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 21.696 BY 47.542 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.052 0.072 2.076 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.828 0.072 3.852 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.380 0.072 7.404 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.156 0.072 9.180 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.484 0.072 14.508 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.812 0.072 19.836 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.364 0.072 23.388 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.140 0.072 25.164 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.916 0.072 26.940 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.692 0.072 28.716 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.468 0.072 30.492 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 0.276 21.696 0.300 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 2.052 21.696 2.076 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 3.828 21.696 3.852 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 5.604 21.696 5.628 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 7.380 21.696 7.404 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 9.156 21.696 9.180 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 10.932 21.696 10.956 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 12.708 21.696 12.732 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 14.484 21.696 14.508 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 16.260 21.696 16.284 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 18.036 21.696 18.060 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 19.812 21.696 19.836 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 21.588 21.696 21.612 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 23.364 21.696 23.388 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 25.140 21.696 25.164 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 26.916 21.696 26.940 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 28.692 21.696 28.716 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 30.468 21.696 30.492 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[71] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 47.488 0.225 47.542 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 47.488 0.729 47.542 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 47.488 1.233 47.542 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 47.488 1.737 47.542 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 47.488 2.241 47.542 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 47.488 2.745 47.542 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 47.488 3.249 47.542 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 47.488 3.753 47.542 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 47.488 4.257 47.542 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 47.488 4.761 47.542 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 47.488 5.265 47.542 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 47.488 5.769 47.542 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 47.488 6.273 47.542 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 47.488 6.777 47.542 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 47.488 7.281 47.542 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 47.488 7.785 47.542 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 47.488 8.289 47.542 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 47.488 8.793 47.542 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 47.488 9.297 47.542 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 47.488 9.801 47.542 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 47.488 10.305 47.542 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 47.488 10.809 47.542 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 47.488 11.313 47.542 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 47.488 11.817 47.542 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 47.488 12.321 47.542 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 47.488 12.825 47.542 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 47.488 13.329 47.542 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 47.488 13.833 47.542 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 47.488 14.337 47.542 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 47.488 14.841 47.542 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 47.488 15.345 47.542 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 47.488 15.849 47.542 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 47.488 16.353 47.542 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 47.488 16.857 47.542 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 47.488 17.361 47.542 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 47.488 17.865 47.542 ; + END + END r0_rd_out[71] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.020 0.072 34.044 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.796 0.072 35.820 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 32.244 21.696 32.268 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 34.020 21.696 34.044 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 35.796 21.696 35.820 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 37.572 21.696 37.596 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.348 0.072 39.372 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.124 0.072 41.148 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.900 0.072 42.924 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.676 0.072 44.700 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 39.348 21.696 39.372 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 41.124 21.696 41.148 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 42.900 21.696 42.924 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 44.676 21.696 44.700 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 47.488 18.369 47.542 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 47.488 18.873 47.542 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 47.488 19.377 47.542 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 47.488 19.881 47.542 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 47.488 20.385 47.542 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 21.480 0.336 ; + RECT 0.216 1.008 21.480 1.104 ; + RECT 0.216 1.776 21.480 1.872 ; + RECT 0.216 2.544 21.480 2.640 ; + RECT 0.216 3.312 21.480 3.408 ; + RECT 0.216 4.080 21.480 4.176 ; + RECT 0.216 4.848 21.480 4.944 ; + RECT 0.216 5.616 21.480 5.712 ; + RECT 0.216 6.384 21.480 6.480 ; + RECT 0.216 7.152 21.480 7.248 ; + RECT 0.216 7.920 21.480 8.016 ; + RECT 0.216 8.688 21.480 8.784 ; + RECT 0.216 9.456 21.480 9.552 ; + RECT 0.216 10.224 21.480 10.320 ; + RECT 0.216 10.992 21.480 11.088 ; + RECT 0.216 11.760 21.480 11.856 ; + RECT 0.216 12.528 21.480 12.624 ; + RECT 0.216 13.296 21.480 13.392 ; + RECT 0.216 14.064 21.480 14.160 ; + RECT 0.216 14.832 21.480 14.928 ; + RECT 0.216 15.600 21.480 15.696 ; + RECT 0.216 16.368 21.480 16.464 ; + RECT 0.216 17.136 21.480 17.232 ; + RECT 0.216 17.904 21.480 18.000 ; + RECT 0.216 18.672 21.480 18.768 ; + RECT 0.216 19.440 21.480 19.536 ; + RECT 0.216 20.208 21.480 20.304 ; + RECT 0.216 20.976 21.480 21.072 ; + RECT 0.216 21.744 21.480 21.840 ; + RECT 0.216 22.512 21.480 22.608 ; + RECT 0.216 23.280 21.480 23.376 ; + RECT 0.216 24.048 21.480 24.144 ; + RECT 0.216 24.816 21.480 24.912 ; + RECT 0.216 25.584 21.480 25.680 ; + RECT 0.216 26.352 21.480 26.448 ; + RECT 0.216 27.120 21.480 27.216 ; + RECT 0.216 27.888 21.480 27.984 ; + RECT 0.216 28.656 21.480 28.752 ; + RECT 0.216 29.424 21.480 29.520 ; + RECT 0.216 30.192 21.480 30.288 ; + RECT 0.216 30.960 21.480 31.056 ; + RECT 0.216 31.728 21.480 31.824 ; + RECT 0.216 32.496 21.480 32.592 ; + RECT 0.216 33.264 21.480 33.360 ; + RECT 0.216 34.032 21.480 34.128 ; + RECT 0.216 34.800 21.480 34.896 ; + RECT 0.216 35.568 21.480 35.664 ; + RECT 0.216 36.336 21.480 36.432 ; + RECT 0.216 37.104 21.480 37.200 ; + RECT 0.216 37.872 21.480 37.968 ; + RECT 0.216 38.640 21.480 38.736 ; + RECT 0.216 39.408 21.480 39.504 ; + RECT 0.216 40.176 21.480 40.272 ; + RECT 0.216 40.944 21.480 41.040 ; + RECT 0.216 41.712 21.480 41.808 ; + RECT 0.216 42.480 21.480 42.576 ; + RECT 0.216 43.248 21.480 43.344 ; + RECT 0.216 44.016 21.480 44.112 ; + RECT 0.216 44.784 21.480 44.880 ; + RECT 0.216 45.552 21.480 45.648 ; + RECT 0.216 46.320 21.480 46.416 ; + RECT 0.216 47.088 21.480 47.184 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 21.480 0.336 ; + RECT 0.216 1.008 21.480 1.104 ; + RECT 0.216 1.776 21.480 1.872 ; + RECT 0.216 2.544 21.480 2.640 ; + RECT 0.216 3.312 21.480 3.408 ; + RECT 0.216 4.080 21.480 4.176 ; + RECT 0.216 4.848 21.480 4.944 ; + RECT 0.216 5.616 21.480 5.712 ; + RECT 0.216 6.384 21.480 6.480 ; + RECT 0.216 7.152 21.480 7.248 ; + RECT 0.216 7.920 21.480 8.016 ; + RECT 0.216 8.688 21.480 8.784 ; + RECT 0.216 9.456 21.480 9.552 ; + RECT 0.216 10.224 21.480 10.320 ; + RECT 0.216 10.992 21.480 11.088 ; + RECT 0.216 11.760 21.480 11.856 ; + RECT 0.216 12.528 21.480 12.624 ; + RECT 0.216 13.296 21.480 13.392 ; + RECT 0.216 14.064 21.480 14.160 ; + RECT 0.216 14.832 21.480 14.928 ; + RECT 0.216 15.600 21.480 15.696 ; + RECT 0.216 16.368 21.480 16.464 ; + RECT 0.216 17.136 21.480 17.232 ; + RECT 0.216 17.904 21.480 18.000 ; + RECT 0.216 18.672 21.480 18.768 ; + RECT 0.216 19.440 21.480 19.536 ; + RECT 0.216 20.208 21.480 20.304 ; + RECT 0.216 20.976 21.480 21.072 ; + RECT 0.216 21.744 21.480 21.840 ; + RECT 0.216 22.512 21.480 22.608 ; + RECT 0.216 23.280 21.480 23.376 ; + RECT 0.216 24.048 21.480 24.144 ; + RECT 0.216 24.816 21.480 24.912 ; + RECT 0.216 25.584 21.480 25.680 ; + RECT 0.216 26.352 21.480 26.448 ; + RECT 0.216 27.120 21.480 27.216 ; + RECT 0.216 27.888 21.480 27.984 ; + RECT 0.216 28.656 21.480 28.752 ; + RECT 0.216 29.424 21.480 29.520 ; + RECT 0.216 30.192 21.480 30.288 ; + RECT 0.216 30.960 21.480 31.056 ; + RECT 0.216 31.728 21.480 31.824 ; + RECT 0.216 32.496 21.480 32.592 ; + RECT 0.216 33.264 21.480 33.360 ; + RECT 0.216 34.032 21.480 34.128 ; + RECT 0.216 34.800 21.480 34.896 ; + RECT 0.216 35.568 21.480 35.664 ; + RECT 0.216 36.336 21.480 36.432 ; + RECT 0.216 37.104 21.480 37.200 ; + RECT 0.216 37.872 21.480 37.968 ; + RECT 0.216 38.640 21.480 38.736 ; + RECT 0.216 39.408 21.480 39.504 ; + RECT 0.216 40.176 21.480 40.272 ; + RECT 0.216 40.944 21.480 41.040 ; + RECT 0.216 41.712 21.480 41.808 ; + RECT 0.216 42.480 21.480 42.576 ; + RECT 0.216 43.248 21.480 43.344 ; + RECT 0.216 44.016 21.480 44.112 ; + RECT 0.216 44.784 21.480 44.880 ; + RECT 0.216 45.552 21.480 45.648 ; + RECT 0.216 46.320 21.480 46.416 ; + RECT 0.216 47.088 21.480 47.184 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 21.696 47.542 ; + LAYER M2 ; + RECT 0 0 21.696 47.542 ; + LAYER M3 ; + RECT 0 0 21.696 47.542 ; + LAYER M4 ; + RECT 0 0 21.696 47.542 ; + END +END fakeram_144x248_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_144x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_144x256_1r1w.lef new file mode 100644 index 0000000..1457918 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_144x256_1r1w.lef @@ -0,0 +1,1647 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_144x256_1r1w + FOREIGN fakeram_144x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 21.696 BY 48.881 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.100 0.072 2.124 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.340 0.072 20.364 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.988 0.072 24.012 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.812 0.072 25.836 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.460 0.072 29.484 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.284 0.072 31.308 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 0.276 21.696 0.300 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 2.100 21.696 2.124 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 3.924 21.696 3.948 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 5.748 21.696 5.772 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 7.572 21.696 7.596 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 9.396 21.696 9.420 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 11.220 21.696 11.244 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 13.044 21.696 13.068 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 14.868 21.696 14.892 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 16.692 21.696 16.716 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 18.516 21.696 18.540 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 20.340 21.696 20.364 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 22.164 21.696 22.188 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 23.988 21.696 24.012 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 25.812 21.696 25.836 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 27.636 21.696 27.660 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 29.460 21.696 29.484 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 31.284 21.696 31.308 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[71] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 48.827 0.225 48.881 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 48.827 0.729 48.881 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 48.827 1.233 48.881 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 48.827 1.737 48.881 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 48.827 2.241 48.881 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 48.827 2.745 48.881 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 48.827 3.249 48.881 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 48.827 3.753 48.881 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 48.827 4.257 48.881 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 48.827 4.761 48.881 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 48.827 5.265 48.881 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 48.827 5.769 48.881 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 48.827 6.273 48.881 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 48.827 6.777 48.881 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 48.827 7.281 48.881 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 48.827 7.785 48.881 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 48.827 8.289 48.881 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 48.827 8.793 48.881 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 48.827 9.297 48.881 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 48.827 9.801 48.881 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 48.827 10.305 48.881 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 48.827 10.809 48.881 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 48.827 11.313 48.881 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 48.827 11.817 48.881 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 48.827 12.321 48.881 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 48.827 12.825 48.881 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 48.827 13.329 48.881 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 48.827 13.833 48.881 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 48.827 14.337 48.881 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 48.827 14.841 48.881 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 48.827 15.345 48.881 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 48.827 15.849 48.881 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 48.827 16.353 48.881 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 48.827 16.857 48.881 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 48.827 17.361 48.881 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 48.827 17.865 48.881 ; + END + END r0_rd_out[71] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.932 0.072 34.956 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.756 0.072 36.780 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 33.108 21.696 33.132 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 34.932 21.696 34.956 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 36.756 21.696 36.780 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 38.580 21.696 38.604 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.404 0.072 40.428 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.228 0.072 42.252 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.052 0.072 44.076 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.876 0.072 45.900 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 40.404 21.696 40.428 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 42.228 21.696 42.252 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 44.052 21.696 44.076 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 45.876 21.696 45.900 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 48.827 18.369 48.881 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 48.827 18.873 48.881 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 48.827 19.377 48.881 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 48.827 19.881 48.881 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 48.827 20.385 48.881 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 21.480 0.336 ; + RECT 0.216 1.008 21.480 1.104 ; + RECT 0.216 1.776 21.480 1.872 ; + RECT 0.216 2.544 21.480 2.640 ; + RECT 0.216 3.312 21.480 3.408 ; + RECT 0.216 4.080 21.480 4.176 ; + RECT 0.216 4.848 21.480 4.944 ; + RECT 0.216 5.616 21.480 5.712 ; + RECT 0.216 6.384 21.480 6.480 ; + RECT 0.216 7.152 21.480 7.248 ; + RECT 0.216 7.920 21.480 8.016 ; + RECT 0.216 8.688 21.480 8.784 ; + RECT 0.216 9.456 21.480 9.552 ; + RECT 0.216 10.224 21.480 10.320 ; + RECT 0.216 10.992 21.480 11.088 ; + RECT 0.216 11.760 21.480 11.856 ; + RECT 0.216 12.528 21.480 12.624 ; + RECT 0.216 13.296 21.480 13.392 ; + RECT 0.216 14.064 21.480 14.160 ; + RECT 0.216 14.832 21.480 14.928 ; + RECT 0.216 15.600 21.480 15.696 ; + RECT 0.216 16.368 21.480 16.464 ; + RECT 0.216 17.136 21.480 17.232 ; + RECT 0.216 17.904 21.480 18.000 ; + RECT 0.216 18.672 21.480 18.768 ; + RECT 0.216 19.440 21.480 19.536 ; + RECT 0.216 20.208 21.480 20.304 ; + RECT 0.216 20.976 21.480 21.072 ; + RECT 0.216 21.744 21.480 21.840 ; + RECT 0.216 22.512 21.480 22.608 ; + RECT 0.216 23.280 21.480 23.376 ; + RECT 0.216 24.048 21.480 24.144 ; + RECT 0.216 24.816 21.480 24.912 ; + RECT 0.216 25.584 21.480 25.680 ; + RECT 0.216 26.352 21.480 26.448 ; + RECT 0.216 27.120 21.480 27.216 ; + RECT 0.216 27.888 21.480 27.984 ; + RECT 0.216 28.656 21.480 28.752 ; + RECT 0.216 29.424 21.480 29.520 ; + RECT 0.216 30.192 21.480 30.288 ; + RECT 0.216 30.960 21.480 31.056 ; + RECT 0.216 31.728 21.480 31.824 ; + RECT 0.216 32.496 21.480 32.592 ; + RECT 0.216 33.264 21.480 33.360 ; + RECT 0.216 34.032 21.480 34.128 ; + RECT 0.216 34.800 21.480 34.896 ; + RECT 0.216 35.568 21.480 35.664 ; + RECT 0.216 36.336 21.480 36.432 ; + RECT 0.216 37.104 21.480 37.200 ; + RECT 0.216 37.872 21.480 37.968 ; + RECT 0.216 38.640 21.480 38.736 ; + RECT 0.216 39.408 21.480 39.504 ; + RECT 0.216 40.176 21.480 40.272 ; + RECT 0.216 40.944 21.480 41.040 ; + RECT 0.216 41.712 21.480 41.808 ; + RECT 0.216 42.480 21.480 42.576 ; + RECT 0.216 43.248 21.480 43.344 ; + RECT 0.216 44.016 21.480 44.112 ; + RECT 0.216 44.784 21.480 44.880 ; + RECT 0.216 45.552 21.480 45.648 ; + RECT 0.216 46.320 21.480 46.416 ; + RECT 0.216 47.088 21.480 47.184 ; + RECT 0.216 47.856 21.480 47.952 ; + RECT 0.216 48.624 21.480 48.720 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 21.480 0.336 ; + RECT 0.216 1.008 21.480 1.104 ; + RECT 0.216 1.776 21.480 1.872 ; + RECT 0.216 2.544 21.480 2.640 ; + RECT 0.216 3.312 21.480 3.408 ; + RECT 0.216 4.080 21.480 4.176 ; + RECT 0.216 4.848 21.480 4.944 ; + RECT 0.216 5.616 21.480 5.712 ; + RECT 0.216 6.384 21.480 6.480 ; + RECT 0.216 7.152 21.480 7.248 ; + RECT 0.216 7.920 21.480 8.016 ; + RECT 0.216 8.688 21.480 8.784 ; + RECT 0.216 9.456 21.480 9.552 ; + RECT 0.216 10.224 21.480 10.320 ; + RECT 0.216 10.992 21.480 11.088 ; + RECT 0.216 11.760 21.480 11.856 ; + RECT 0.216 12.528 21.480 12.624 ; + RECT 0.216 13.296 21.480 13.392 ; + RECT 0.216 14.064 21.480 14.160 ; + RECT 0.216 14.832 21.480 14.928 ; + RECT 0.216 15.600 21.480 15.696 ; + RECT 0.216 16.368 21.480 16.464 ; + RECT 0.216 17.136 21.480 17.232 ; + RECT 0.216 17.904 21.480 18.000 ; + RECT 0.216 18.672 21.480 18.768 ; + RECT 0.216 19.440 21.480 19.536 ; + RECT 0.216 20.208 21.480 20.304 ; + RECT 0.216 20.976 21.480 21.072 ; + RECT 0.216 21.744 21.480 21.840 ; + RECT 0.216 22.512 21.480 22.608 ; + RECT 0.216 23.280 21.480 23.376 ; + RECT 0.216 24.048 21.480 24.144 ; + RECT 0.216 24.816 21.480 24.912 ; + RECT 0.216 25.584 21.480 25.680 ; + RECT 0.216 26.352 21.480 26.448 ; + RECT 0.216 27.120 21.480 27.216 ; + RECT 0.216 27.888 21.480 27.984 ; + RECT 0.216 28.656 21.480 28.752 ; + RECT 0.216 29.424 21.480 29.520 ; + RECT 0.216 30.192 21.480 30.288 ; + RECT 0.216 30.960 21.480 31.056 ; + RECT 0.216 31.728 21.480 31.824 ; + RECT 0.216 32.496 21.480 32.592 ; + RECT 0.216 33.264 21.480 33.360 ; + RECT 0.216 34.032 21.480 34.128 ; + RECT 0.216 34.800 21.480 34.896 ; + RECT 0.216 35.568 21.480 35.664 ; + RECT 0.216 36.336 21.480 36.432 ; + RECT 0.216 37.104 21.480 37.200 ; + RECT 0.216 37.872 21.480 37.968 ; + RECT 0.216 38.640 21.480 38.736 ; + RECT 0.216 39.408 21.480 39.504 ; + RECT 0.216 40.176 21.480 40.272 ; + RECT 0.216 40.944 21.480 41.040 ; + RECT 0.216 41.712 21.480 41.808 ; + RECT 0.216 42.480 21.480 42.576 ; + RECT 0.216 43.248 21.480 43.344 ; + RECT 0.216 44.016 21.480 44.112 ; + RECT 0.216 44.784 21.480 44.880 ; + RECT 0.216 45.552 21.480 45.648 ; + RECT 0.216 46.320 21.480 46.416 ; + RECT 0.216 47.088 21.480 47.184 ; + RECT 0.216 47.856 21.480 47.952 ; + RECT 0.216 48.624 21.480 48.720 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 21.696 48.881 ; + LAYER M2 ; + RECT 0 0 21.696 48.881 ; + LAYER M3 ; + RECT 0 0 21.696 48.881 ; + LAYER M4 ; + RECT 0 0 21.696 48.881 ; + END +END fakeram_144x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_14x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_14x80_1r1w.lef new file mode 100644 index 0000000..f05c284 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_14x80_1r1w.lef @@ -0,0 +1,495 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_14x80_1r1w + FOREIGN fakeram_14x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 14.564 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.524 0.072 1.548 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 1.524 9.643 1.548 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.772 9.643 2.796 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.855 0.000 0.873 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 0.000 1.521 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.151 0.000 2.169 0.054 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 0.000 4.113 0.054 ; + END + END w0_wd_in[13] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.039 0.000 6.057 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.335 0.000 7.353 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.631 0.000 8.649 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 14.510 0.225 14.564 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.963 14.510 0.981 14.564 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 14.510 1.737 14.564 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.475 14.510 2.493 14.564 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 14.510 3.249 14.564 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 14.510 4.005 14.564 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 14.510 4.761 14.564 ; + END + END r0_rd_out[13] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.020 9.643 4.044 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 5.268 9.643 5.292 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.516 9.643 6.540 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.764 9.643 7.788 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.012 9.643 9.036 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 10.260 9.643 10.284 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.499 14.510 5.517 14.564 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 14.510 6.273 14.564 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.011 14.510 7.029 14.564 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 14.510 7.785 14.564 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.523 14.510 8.541 14.564 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 14.564 ; + LAYER M2 ; + RECT 0 0 9.643 14.564 ; + LAYER M3 ; + RECT 0 0 9.643 14.564 ; + LAYER M4 ; + RECT 0 0 9.643 14.564 ; + END +END fakeram_14x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_15x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_15x80_1r1w.lef new file mode 100644 index 0000000..9c9965d --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_15x80_1r1w.lef @@ -0,0 +1,513 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_15x80_1r1w + FOREIGN fakeram_15x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 14.648 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.524 0.072 1.548 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 1.524 9.643 1.548 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.772 9.643 2.796 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.020 9.643 4.044 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END w0_wd_in[14] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 14.594 0.225 14.648 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.891 14.594 0.909 14.648 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.575 14.594 1.593 14.648 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.259 14.594 2.277 14.648 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.943 14.594 2.961 14.648 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 14.594 3.645 14.648 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.311 14.594 4.329 14.648 ; + END + END r0_rd_out[14] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 5.268 9.643 5.292 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.516 9.643 6.540 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.764 9.643 7.788 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.012 9.643 9.036 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 10.260 9.643 10.284 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.508 9.643 11.532 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.995 14.594 5.013 14.648 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 14.594 5.697 14.648 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.363 14.594 6.381 14.648 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 14.594 7.065 14.648 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.731 14.594 7.749 14.648 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 14.648 ; + LAYER M2 ; + RECT 0 0 9.643 14.648 ; + LAYER M3 ; + RECT 0 0 9.643 14.648 ; + LAYER M4 ; + RECT 0 0 9.643 14.648 ; + END +END fakeram_15x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_160x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_160x64_1r1w.lef new file mode 100644 index 0000000..9eb2029 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_160x64_1r1w.lef @@ -0,0 +1,3129 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_160x64_1r1w + FOREIGN fakeram_160x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 48.212 BY 24.106 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 0.276 48.212 0.300 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 0.756 48.212 0.780 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 1.236 48.212 1.260 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 1.716 48.212 1.740 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 2.196 48.212 2.220 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 2.676 48.212 2.700 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 3.156 48.212 3.180 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 3.636 48.212 3.660 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 4.116 48.212 4.140 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 4.596 48.212 4.620 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 5.076 48.212 5.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 5.556 48.212 5.580 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 6.036 48.212 6.060 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 6.516 48.212 6.540 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 6.996 48.212 7.020 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 7.476 48.212 7.500 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 7.956 48.212 7.980 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 8.436 48.212 8.460 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 8.916 48.212 8.940 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 9.396 48.212 9.420 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 9.876 48.212 9.900 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 10.356 48.212 10.380 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 10.836 48.212 10.860 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 11.316 48.212 11.340 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 11.796 48.212 11.820 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 12.276 48.212 12.300 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 12.756 48.212 12.780 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 13.236 48.212 13.260 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 13.716 48.212 13.740 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 14.196 48.212 14.220 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 14.676 48.212 14.700 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 15.156 48.212 15.180 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 15.636 48.212 15.660 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 16.116 48.212 16.140 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 16.596 48.212 16.620 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 17.076 48.212 17.100 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 17.556 48.212 17.580 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 18.036 48.212 18.060 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 18.516 48.212 18.540 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 18.996 48.212 19.020 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[159] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 24.052 0.225 24.106 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 24.052 0.765 24.106 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 24.052 1.305 24.106 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 24.052 1.845 24.106 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 24.052 2.385 24.106 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 24.052 2.925 24.106 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 24.052 3.465 24.106 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 24.052 4.005 24.106 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 24.052 4.545 24.106 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 24.052 5.085 24.106 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 24.052 5.625 24.106 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 24.052 6.165 24.106 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 24.052 6.705 24.106 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 24.052 7.245 24.106 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 24.052 7.785 24.106 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 24.052 8.325 24.106 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 24.052 8.865 24.106 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 24.052 9.405 24.106 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 24.052 9.945 24.106 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 24.052 10.485 24.106 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 24.052 11.025 24.106 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 24.052 11.565 24.106 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 24.052 12.105 24.106 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 24.052 12.645 24.106 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 24.052 13.185 24.106 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 24.052 13.725 24.106 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 24.052 14.265 24.106 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 24.052 14.805 24.106 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 24.052 15.345 24.106 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 24.052 15.885 24.106 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 24.052 16.425 24.106 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 24.052 16.965 24.106 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 24.052 17.505 24.106 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 24.052 18.045 24.106 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 24.052 18.585 24.106 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 24.052 19.125 24.106 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 24.052 19.665 24.106 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 24.052 20.205 24.106 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 24.052 20.745 24.106 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 24.052 21.285 24.106 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 24.052 21.825 24.106 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 24.052 22.365 24.106 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 24.052 22.905 24.106 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 24.052 23.445 24.106 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 24.052 23.985 24.106 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 24.052 24.525 24.106 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 24.052 25.065 24.106 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 24.052 25.605 24.106 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 24.052 26.145 24.106 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 24.052 26.685 24.106 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 24.052 27.225 24.106 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 24.052 27.765 24.106 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 24.052 28.305 24.106 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 24.052 28.845 24.106 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 24.052 29.385 24.106 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 24.052 29.925 24.106 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 24.052 30.465 24.106 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 24.052 31.005 24.106 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 24.052 31.545 24.106 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 24.052 32.085 24.106 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 24.052 32.625 24.106 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 24.052 33.165 24.106 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 24.052 33.705 24.106 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 24.052 34.245 24.106 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 24.052 34.785 24.106 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 24.052 35.325 24.106 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 24.052 35.865 24.106 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 24.052 36.405 24.106 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 24.052 36.945 24.106 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 24.052 37.485 24.106 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 24.052 38.025 24.106 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 24.052 38.565 24.106 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 24.052 39.105 24.106 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 24.052 39.645 24.106 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 24.052 40.185 24.106 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 24.052 40.725 24.106 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 24.052 41.265 24.106 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 24.052 41.805 24.106 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 24.052 42.345 24.106 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 24.052 42.885 24.106 ; + END + END r0_rd_out[159] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 19.476 48.212 19.500 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 19.956 48.212 19.980 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 20.436 48.212 20.460 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 20.916 48.212 20.940 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 21.396 48.212 21.420 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 48.140 21.876 48.212 21.900 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 24.052 43.425 24.106 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 24.052 43.965 24.106 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 24.052 44.505 24.106 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 24.052 45.045 24.106 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 24.052 45.585 24.106 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 47.996 0.336 ; + RECT 0.216 1.008 47.996 1.104 ; + RECT 0.216 1.776 47.996 1.872 ; + RECT 0.216 2.544 47.996 2.640 ; + RECT 0.216 3.312 47.996 3.408 ; + RECT 0.216 4.080 47.996 4.176 ; + RECT 0.216 4.848 47.996 4.944 ; + RECT 0.216 5.616 47.996 5.712 ; + RECT 0.216 6.384 47.996 6.480 ; + RECT 0.216 7.152 47.996 7.248 ; + RECT 0.216 7.920 47.996 8.016 ; + RECT 0.216 8.688 47.996 8.784 ; + RECT 0.216 9.456 47.996 9.552 ; + RECT 0.216 10.224 47.996 10.320 ; + RECT 0.216 10.992 47.996 11.088 ; + RECT 0.216 11.760 47.996 11.856 ; + RECT 0.216 12.528 47.996 12.624 ; + RECT 0.216 13.296 47.996 13.392 ; + RECT 0.216 14.064 47.996 14.160 ; + RECT 0.216 14.832 47.996 14.928 ; + RECT 0.216 15.600 47.996 15.696 ; + RECT 0.216 16.368 47.996 16.464 ; + RECT 0.216 17.136 47.996 17.232 ; + RECT 0.216 17.904 47.996 18.000 ; + RECT 0.216 18.672 47.996 18.768 ; + RECT 0.216 19.440 47.996 19.536 ; + RECT 0.216 20.208 47.996 20.304 ; + RECT 0.216 20.976 47.996 21.072 ; + RECT 0.216 21.744 47.996 21.840 ; + RECT 0.216 22.512 47.996 22.608 ; + RECT 0.216 23.280 47.996 23.376 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 47.996 0.336 ; + RECT 0.216 1.008 47.996 1.104 ; + RECT 0.216 1.776 47.996 1.872 ; + RECT 0.216 2.544 47.996 2.640 ; + RECT 0.216 3.312 47.996 3.408 ; + RECT 0.216 4.080 47.996 4.176 ; + RECT 0.216 4.848 47.996 4.944 ; + RECT 0.216 5.616 47.996 5.712 ; + RECT 0.216 6.384 47.996 6.480 ; + RECT 0.216 7.152 47.996 7.248 ; + RECT 0.216 7.920 47.996 8.016 ; + RECT 0.216 8.688 47.996 8.784 ; + RECT 0.216 9.456 47.996 9.552 ; + RECT 0.216 10.224 47.996 10.320 ; + RECT 0.216 10.992 47.996 11.088 ; + RECT 0.216 11.760 47.996 11.856 ; + RECT 0.216 12.528 47.996 12.624 ; + RECT 0.216 13.296 47.996 13.392 ; + RECT 0.216 14.064 47.996 14.160 ; + RECT 0.216 14.832 47.996 14.928 ; + RECT 0.216 15.600 47.996 15.696 ; + RECT 0.216 16.368 47.996 16.464 ; + RECT 0.216 17.136 47.996 17.232 ; + RECT 0.216 17.904 47.996 18.000 ; + RECT 0.216 18.672 47.996 18.768 ; + RECT 0.216 19.440 47.996 19.536 ; + RECT 0.216 20.208 47.996 20.304 ; + RECT 0.216 20.976 47.996 21.072 ; + RECT 0.216 21.744 47.996 21.840 ; + RECT 0.216 22.512 47.996 22.608 ; + RECT 0.216 23.280 47.996 23.376 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 48.212 24.106 ; + LAYER M2 ; + RECT 0 0 48.212 24.106 ; + LAYER M3 ; + RECT 0 0 48.212 24.106 ; + LAYER M4 ; + RECT 0 0 48.212 24.106 ; + END +END fakeram_160x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_168x60_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_168x60_1r1w.lef new file mode 100644 index 0000000..edff8ac --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_168x60_1r1w.lef @@ -0,0 +1,3273 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_168x60_1r1w + FOREIGN fakeram_168x60_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 50.622 BY 24.106 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 0.276 50.622 0.300 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 0.756 50.622 0.780 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 1.236 50.622 1.260 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 1.716 50.622 1.740 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 2.196 50.622 2.220 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 2.676 50.622 2.700 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 3.156 50.622 3.180 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 3.636 50.622 3.660 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 4.116 50.622 4.140 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 4.596 50.622 4.620 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 5.076 50.622 5.100 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 5.556 50.622 5.580 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 6.036 50.622 6.060 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 6.516 50.622 6.540 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 6.996 50.622 7.020 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 7.476 50.622 7.500 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 7.956 50.622 7.980 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 8.436 50.622 8.460 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 8.916 50.622 8.940 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 9.396 50.622 9.420 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 9.876 50.622 9.900 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 10.356 50.622 10.380 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 10.836 50.622 10.860 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 11.316 50.622 11.340 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 11.796 50.622 11.820 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 12.276 50.622 12.300 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 12.756 50.622 12.780 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 13.236 50.622 13.260 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 13.716 50.622 13.740 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 14.196 50.622 14.220 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 14.676 50.622 14.700 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 15.156 50.622 15.180 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 15.636 50.622 15.660 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 16.116 50.622 16.140 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 16.596 50.622 16.620 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 17.076 50.622 17.100 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 17.556 50.622 17.580 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 18.036 50.622 18.060 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 18.516 50.622 18.540 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 18.996 50.622 19.020 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 19.476 50.622 19.500 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 19.956 50.622 19.980 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[167] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 24.052 0.225 24.106 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 24.052 0.765 24.106 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 24.052 1.305 24.106 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 24.052 1.845 24.106 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 24.052 2.385 24.106 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 24.052 2.925 24.106 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 24.052 3.465 24.106 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 24.052 4.005 24.106 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 24.052 4.545 24.106 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 24.052 5.085 24.106 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 24.052 5.625 24.106 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 24.052 6.165 24.106 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 24.052 6.705 24.106 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 24.052 7.245 24.106 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 24.052 7.785 24.106 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 24.052 8.325 24.106 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 24.052 8.865 24.106 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 24.052 9.405 24.106 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 24.052 9.945 24.106 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 24.052 10.485 24.106 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 24.052 11.025 24.106 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 24.052 11.565 24.106 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 24.052 12.105 24.106 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 24.052 12.645 24.106 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 24.052 13.185 24.106 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 24.052 13.725 24.106 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 24.052 14.265 24.106 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 24.052 14.805 24.106 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 24.052 15.345 24.106 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 24.052 15.885 24.106 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 24.052 16.425 24.106 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 24.052 16.965 24.106 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 24.052 17.505 24.106 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 24.052 18.045 24.106 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 24.052 18.585 24.106 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 24.052 19.125 24.106 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 24.052 19.665 24.106 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 24.052 20.205 24.106 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 24.052 20.745 24.106 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 24.052 21.285 24.106 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 24.052 21.825 24.106 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 24.052 22.365 24.106 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 24.052 22.905 24.106 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 24.052 23.445 24.106 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 24.052 23.985 24.106 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 24.052 24.525 24.106 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 24.052 25.065 24.106 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 24.052 25.605 24.106 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 24.052 26.145 24.106 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 24.052 26.685 24.106 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 24.052 27.225 24.106 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 24.052 27.765 24.106 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 24.052 28.305 24.106 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 24.052 28.845 24.106 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 24.052 29.385 24.106 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 24.052 29.925 24.106 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 24.052 30.465 24.106 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 24.052 31.005 24.106 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 24.052 31.545 24.106 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 24.052 32.085 24.106 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 24.052 32.625 24.106 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 24.052 33.165 24.106 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 24.052 33.705 24.106 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 24.052 34.245 24.106 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 24.052 34.785 24.106 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 24.052 35.325 24.106 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 24.052 35.865 24.106 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 24.052 36.405 24.106 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 24.052 36.945 24.106 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 24.052 37.485 24.106 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 24.052 38.025 24.106 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 24.052 38.565 24.106 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 24.052 39.105 24.106 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 24.052 39.645 24.106 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 24.052 40.185 24.106 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 24.052 40.725 24.106 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 24.052 41.265 24.106 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 24.052 41.805 24.106 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 24.052 42.345 24.106 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 24.052 42.885 24.106 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 24.052 43.425 24.106 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 24.052 43.965 24.106 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 24.052 44.505 24.106 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 24.052 45.045 24.106 ; + END + END r0_rd_out[167] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 20.436 50.622 20.460 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 20.916 50.622 20.940 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 21.396 50.622 21.420 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 21.876 50.622 21.900 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 22.356 50.622 22.380 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 50.550 22.836 50.622 22.860 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 24.052 45.585 24.106 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 24.052 46.125 24.106 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 24.052 46.665 24.106 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 24.052 47.205 24.106 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 24.052 47.745 24.106 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 50.406 0.336 ; + RECT 0.216 1.008 50.406 1.104 ; + RECT 0.216 1.776 50.406 1.872 ; + RECT 0.216 2.544 50.406 2.640 ; + RECT 0.216 3.312 50.406 3.408 ; + RECT 0.216 4.080 50.406 4.176 ; + RECT 0.216 4.848 50.406 4.944 ; + RECT 0.216 5.616 50.406 5.712 ; + RECT 0.216 6.384 50.406 6.480 ; + RECT 0.216 7.152 50.406 7.248 ; + RECT 0.216 7.920 50.406 8.016 ; + RECT 0.216 8.688 50.406 8.784 ; + RECT 0.216 9.456 50.406 9.552 ; + RECT 0.216 10.224 50.406 10.320 ; + RECT 0.216 10.992 50.406 11.088 ; + RECT 0.216 11.760 50.406 11.856 ; + RECT 0.216 12.528 50.406 12.624 ; + RECT 0.216 13.296 50.406 13.392 ; + RECT 0.216 14.064 50.406 14.160 ; + RECT 0.216 14.832 50.406 14.928 ; + RECT 0.216 15.600 50.406 15.696 ; + RECT 0.216 16.368 50.406 16.464 ; + RECT 0.216 17.136 50.406 17.232 ; + RECT 0.216 17.904 50.406 18.000 ; + RECT 0.216 18.672 50.406 18.768 ; + RECT 0.216 19.440 50.406 19.536 ; + RECT 0.216 20.208 50.406 20.304 ; + RECT 0.216 20.976 50.406 21.072 ; + RECT 0.216 21.744 50.406 21.840 ; + RECT 0.216 22.512 50.406 22.608 ; + RECT 0.216 23.280 50.406 23.376 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 50.406 0.336 ; + RECT 0.216 1.008 50.406 1.104 ; + RECT 0.216 1.776 50.406 1.872 ; + RECT 0.216 2.544 50.406 2.640 ; + RECT 0.216 3.312 50.406 3.408 ; + RECT 0.216 4.080 50.406 4.176 ; + RECT 0.216 4.848 50.406 4.944 ; + RECT 0.216 5.616 50.406 5.712 ; + RECT 0.216 6.384 50.406 6.480 ; + RECT 0.216 7.152 50.406 7.248 ; + RECT 0.216 7.920 50.406 8.016 ; + RECT 0.216 8.688 50.406 8.784 ; + RECT 0.216 9.456 50.406 9.552 ; + RECT 0.216 10.224 50.406 10.320 ; + RECT 0.216 10.992 50.406 11.088 ; + RECT 0.216 11.760 50.406 11.856 ; + RECT 0.216 12.528 50.406 12.624 ; + RECT 0.216 13.296 50.406 13.392 ; + RECT 0.216 14.064 50.406 14.160 ; + RECT 0.216 14.832 50.406 14.928 ; + RECT 0.216 15.600 50.406 15.696 ; + RECT 0.216 16.368 50.406 16.464 ; + RECT 0.216 17.136 50.406 17.232 ; + RECT 0.216 17.904 50.406 18.000 ; + RECT 0.216 18.672 50.406 18.768 ; + RECT 0.216 19.440 50.406 19.536 ; + RECT 0.216 20.208 50.406 20.304 ; + RECT 0.216 20.976 50.406 21.072 ; + RECT 0.216 21.744 50.406 21.840 ; + RECT 0.216 22.512 50.406 22.608 ; + RECT 0.216 23.280 50.406 23.376 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 50.622 24.106 ; + LAYER M2 ; + RECT 0 0 50.622 24.106 ; + LAYER M3 ; + RECT 0 0 50.622 24.106 ; + LAYER M4 ; + RECT 0 0 50.622 24.106 ; + END +END fakeram_168x60_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_16x160_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_16x160_1r1w.lef new file mode 100644 index 0000000..a093346 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_16x160_1r1w.lef @@ -0,0 +1,585 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_16x160_1r1w + FOREIGN fakeram_16x160_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 28.124 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.532 0.072 2.556 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.788 0.072 4.812 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.532 9.643 2.556 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.788 9.643 4.812 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.044 9.643 7.068 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END w0_wd_in[15] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 28.070 0.225 28.124 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.891 28.070 0.909 28.124 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.575 28.070 1.593 28.124 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.259 28.070 2.277 28.124 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.943 28.070 2.961 28.124 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 28.070 3.645 28.124 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.311 28.070 4.329 28.124 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.995 28.070 5.013 28.124 ; + END + END r0_rd_out[15] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.300 0.072 9.324 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.556 0.072 11.580 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.300 9.643 9.324 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.556 9.643 11.580 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 13.812 9.643 13.836 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 16.068 9.643 16.092 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.324 0.072 18.348 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.092 0.072 25.116 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 18.324 9.643 18.348 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 20.580 9.643 20.604 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 22.836 9.643 22.860 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 25.092 9.643 25.116 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 28.070 5.697 28.124 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.363 28.070 6.381 28.124 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 28.070 7.065 28.124 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.731 28.070 7.749 28.124 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 28.070 8.433 28.124 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 28.124 ; + LAYER M2 ; + RECT 0 0 9.643 28.124 ; + LAYER M3 ; + RECT 0 0 9.643 28.124 ; + LAYER M4 ; + RECT 0 0 9.643 28.124 ; + END +END fakeram_16x160_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_16x32_1r1w.lef similarity index 69% rename from designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef rename to designs/asap7/NVDLA/sram/lef/fakeram_16x32_1r1w.lef index 4641970..b26f478 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef +++ b/designs/asap7/NVDLA/sram/lef/fakeram_16x32_1r1w.lef @@ -1,9 +1,9 @@ VERSION 5.7 ; BUSBITCHARS "[]" ; -MACRO fakeram_16x52_1r1w - FOREIGN fakeram_16x52_1r1w 0 0 ; +MACRO fakeram_16x32_1r1w + FOREIGN fakeram_16x32_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 8.295 BY 5.184 ; + SIZE 9.643 BY 9.643 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -11,7 +11,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 0.276 0.072 0.300 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +20,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.708 0.024 0.732 ; + RECT 0.000 1.236 0.072 1.260 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.140 0.024 1.164 ; + RECT 0.000 2.196 0.072 2.220 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.572 0.024 1.596 ; + RECT 0.000 3.156 0.072 3.180 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 0.276 8.295 0.300 ; + RECT 9.571 0.276 9.643 0.300 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 0.708 8.295 0.732 ; + RECT 9.571 1.236 9.643 1.260 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 1.140 8.295 1.164 ; + RECT 9.571 2.196 9.643 2.220 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 1.572 8.295 1.596 ; + RECT 9.571 3.156 9.643 3.180 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +92,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.675 0.000 0.693 0.018 ; + RECT 0.747 0.000 0.765 0.054 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +101,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.018 ; + RECT 1.287 0.000 1.305 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +110,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.018 ; + RECT 1.827 0.000 1.845 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +119,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.018 ; + RECT 2.367 0.000 2.385 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +128,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.018 ; + RECT 2.907 0.000 2.925 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +137,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.018 ; + RECT 3.447 0.000 3.465 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +146,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.018 ; + RECT 3.987 0.000 4.005 0.054 ; END END w0_wd_in[15] PIN r0_rd_out[0] @@ -155,7 +155,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.951 0.000 3.969 0.018 ; + RECT 4.527 0.000 4.545 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -164,7 +164,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 5.067 0.000 5.085 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -173,7 +173,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.018 ; + RECT 5.607 0.000 5.625 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -182,7 +182,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.018 ; + RECT 6.147 0.000 6.165 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -191,7 +191,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.823 0.000 5.841 0.018 ; + RECT 6.687 0.000 6.705 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -200,7 +200,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.291 0.000 6.309 0.018 ; + RECT 7.227 0.000 7.245 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -209,7 +209,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 7.767 0.000 7.785 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -218,7 +218,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 0.000 7.245 0.018 ; + RECT 8.307 0.000 8.325 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -227,7 +227,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 5.166 0.225 5.184 ; + RECT 0.207 9.589 0.225 9.643 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -236,7 +236,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.783 5.166 0.801 5.184 ; + RECT 0.891 9.589 0.909 9.643 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -245,7 +245,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.359 5.166 1.377 5.184 ; + RECT 1.575 9.589 1.593 9.643 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -254,7 +254,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.935 5.166 1.953 5.184 ; + RECT 2.259 9.589 2.277 9.643 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -263,7 +263,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.511 5.166 2.529 5.184 ; + RECT 2.943 9.589 2.961 9.643 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -272,7 +272,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.087 5.166 3.105 5.184 ; + RECT 3.627 9.589 3.645 9.643 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -281,7 +281,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.663 5.166 3.681 5.184 ; + RECT 4.311 9.589 4.329 9.643 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -290,7 +290,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.239 5.166 4.257 5.184 ; + RECT 4.995 9.589 5.013 9.643 ; END END r0_rd_out[15] PIN w0_addr_in[0] @@ -299,7 +299,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.004 0.024 2.028 ; + RECT 0.000 4.116 0.072 4.140 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -308,7 +308,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.436 0.024 2.460 ; + RECT 0.000 5.076 0.072 5.100 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -317,7 +317,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.868 0.024 2.892 ; + RECT 0.000 6.036 0.072 6.060 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -326,7 +326,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 2.004 8.295 2.028 ; + RECT 9.571 4.116 9.643 4.140 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -335,25 +335,16 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 2.436 8.295 2.460 ; + RECT 9.571 5.076 9.643 5.100 ; END END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 8.271 2.868 8.295 2.892 ; - END - END w0_addr_in[5] PIN r0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.300 0.024 3.324 ; + RECT 0.000 6.996 0.072 7.020 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -362,7 +353,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 7.956 0.072 7.980 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -371,7 +362,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.164 0.024 4.188 ; + RECT 0.000 8.916 0.072 8.940 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -380,7 +371,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 3.300 8.295 3.324 ; + RECT 9.571 6.036 9.643 6.060 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -389,25 +380,16 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 8.271 3.732 8.295 3.756 ; + RECT 9.571 6.996 9.643 7.020 ; END END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 8.271 4.164 8.295 4.188 ; - END - END r0_addr_in[5] PIN w0_we_in DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.815 5.166 4.833 5.184 ; + RECT 5.679 9.589 5.697 9.643 ; END END w0_we_in PIN w0_ce_in @@ -416,7 +398,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 5.166 5.409 5.184 ; + RECT 6.363 9.589 6.381 9.643 ; END END w0_ce_in PIN w0_clk @@ -425,7 +407,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.967 5.166 5.985 5.184 ; + RECT 7.047 9.589 7.065 9.643 ; END END w0_clk PIN r0_ce_in @@ -434,7 +416,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.543 5.166 6.561 5.184 ; + RECT 7.731 9.589 7.749 9.643 ; END END r0_ce_in PIN r0_clk @@ -443,7 +425,7 @@ MACRO fakeram_16x52_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.119 5.166 7.137 5.184 ; + RECT 8.415 9.589 8.433 9.643 ; END END r0_clk PIN VSS @@ -451,13 +433,19 @@ MACRO fakeram_16x52_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 8.187 0.288 ; - RECT 0.108 0.960 8.187 1.056 ; - RECT 0.108 1.728 8.187 1.824 ; - RECT 0.108 2.496 8.187 2.592 ; - RECT 0.108 3.264 8.187 3.360 ; - RECT 0.108 4.032 8.187 4.128 ; - RECT 0.108 4.800 8.187 4.896 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; END END VSS PIN VDD @@ -465,25 +453,31 @@ MACRO fakeram_16x52_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 8.187 0.288 ; - RECT 0.108 0.960 8.187 1.056 ; - RECT 0.108 1.728 8.187 1.824 ; - RECT 0.108 2.496 8.187 2.592 ; - RECT 0.108 3.264 8.187 3.360 ; - RECT 0.108 4.032 8.187 4.128 ; - RECT 0.108 4.800 8.187 4.896 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; END END VDD OBS LAYER M1 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 9.643 9.643 ; LAYER M2 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 9.643 9.643 ; LAYER M3 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 9.643 9.643 ; LAYER M4 ; - RECT 0 0 8.295 5.184 ; + RECT 0 0 9.643 9.643 ; END -END fakeram_16x52_1r1w +END fakeram_16x32_1r1w END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_16x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_16x80_1r1w.lef new file mode 100644 index 0000000..d61b77c --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_16x80_1r1w.lef @@ -0,0 +1,531 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_16x80_1r1w + FOREIGN fakeram_16x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 14.732 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.524 0.072 1.548 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 1.524 9.643 1.548 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.772 9.643 2.796 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.020 9.643 4.044 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END w0_wd_in[15] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 14.678 0.225 14.732 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.891 14.678 0.909 14.732 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.575 14.678 1.593 14.732 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.259 14.678 2.277 14.732 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.943 14.678 2.961 14.732 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 14.678 3.645 14.732 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.311 14.678 4.329 14.732 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.995 14.678 5.013 14.732 ; + END + END r0_rd_out[15] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 5.268 9.643 5.292 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.516 9.643 6.540 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.764 9.643 7.788 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.012 9.643 9.036 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 10.260 9.643 10.284 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.508 9.643 11.532 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 14.678 5.697 14.732 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.363 14.678 6.381 14.732 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 14.678 7.065 14.732 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.731 14.678 7.749 14.732 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 14.678 8.433 14.732 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 14.732 ; + LAYER M2 ; + RECT 0 0 9.643 14.732 ; + LAYER M3 ; + RECT 0 0 9.643 14.732 ; + LAYER M4 ; + RECT 0 0 9.643 14.732 ; + END +END fakeram_16x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_18x128_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_18x128_1r1w.lef new file mode 100644 index 0000000..aa35800 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_18x128_1r1w.lef @@ -0,0 +1,589 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_18x128_1r1w + FOREIGN fakeram_18x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 22.934 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.100 0.072 2.124 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.100 9.643 2.124 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 3.924 9.643 3.948 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 5.748 9.643 5.772 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 0.000 0.729 0.054 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 0.000 1.233 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 0.000 1.737 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 0.000 3.753 0.054 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[17] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 0.000 5.769 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 0.000 6.777 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 0.000 7.281 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 0.000 8.793 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 22.880 0.225 22.934 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.855 22.880 0.873 22.934 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 22.880 1.521 22.934 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.151 22.880 2.169 22.934 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 22.880 2.817 22.934 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 22.880 3.465 22.934 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 22.880 4.113 22.934 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 22.880 4.761 22.934 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 22.880 5.409 22.934 ; + END + END r0_rd_out[17] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.572 9.643 7.596 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.396 9.643 9.420 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.220 9.643 11.244 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.340 0.072 20.364 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 13.044 9.643 13.068 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 14.868 9.643 14.892 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 16.692 9.643 16.716 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.039 22.880 6.057 22.934 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 22.880 6.705 22.934 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.335 22.880 7.353 22.934 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 22.880 8.001 22.934 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.631 22.880 8.649 22.934 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 22.934 ; + LAYER M2 ; + RECT 0 0 9.643 22.934 ; + LAYER M3 ; + RECT 0 0 9.643 22.934 ; + LAYER M4 ; + RECT 0 0 9.643 22.934 ; + END +END fakeram_18x128_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_18x64_1r1w.lef similarity index 68% rename from designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef rename to designs/asap7/NVDLA/sram/lef/fakeram_18x64_1r1w.lef index 4431806..bb59db0 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef +++ b/designs/asap7/NVDLA/sram/lef/fakeram_18x64_1r1w.lef @@ -1,9 +1,9 @@ VERSION 5.7 ; BUSBITCHARS "[]" ; -MACRO fakeram_20x64_1r1w - FOREIGN fakeram_20x64_1r1w 0 0 ; +MACRO fakeram_18x64_1r1w + FOREIGN fakeram_18x64_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 10.368 BY 5.184 ; + SIZE 9.643 BY 12.221 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -11,7 +11,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 0.276 0.072 0.300 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +20,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.660 0.024 0.684 ; + RECT 0.000 1.284 0.072 1.308 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.044 0.024 1.068 ; + RECT 0.000 2.292 0.072 2.316 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; + RECT 0.000 3.300 0.072 3.324 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.812 0.024 1.836 ; + RECT 0.000 4.308 0.072 4.332 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.276 10.368 0.300 ; + RECT 9.571 0.276 9.643 0.300 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.660 10.368 0.684 ; + RECT 9.571 1.284 9.643 1.308 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.044 10.368 1.068 ; + RECT 9.571 2.292 9.643 2.316 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,16 +83,16 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.428 10.368 1.452 ; + RECT 9.571 3.300 9.643 3.324 ; END END w0_wd_in[8] PIN w0_wd_in[9] - DIRECTION INPUT ; + DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M4 ; - RECT 10.344 1.812 10.368 1.836 ; + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +101,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + RECT 0.711 0.000 0.729 0.054 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +110,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.675 0.000 0.693 0.018 ; + RECT 1.215 0.000 1.233 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +119,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.018 ; + RECT 1.719 0.000 1.737 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +128,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.018 ; + RECT 2.223 0.000 2.241 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +137,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.018 ; + RECT 2.727 0.000 2.745 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +146,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.018 ; + RECT 3.231 0.000 3.249 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +155,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.018 ; + RECT 3.735 0.000 3.753 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,34 +164,16 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.018 ; + RECT 4.239 0.000 4.257 0.054 ; END END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.951 0.000 3.969 0.018 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; - END - END w0_wd_in[19] PIN r0_rd_out[0] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.018 ; + RECT 4.743 0.000 4.761 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -200,7 +182,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.018 ; + RECT 5.247 0.000 5.265 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -209,7 +191,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.823 0.000 5.841 0.018 ; + RECT 5.751 0.000 5.769 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -218,7 +200,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.291 0.000 6.309 0.018 ; + RECT 6.255 0.000 6.273 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -227,7 +209,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 6.759 0.000 6.777 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -236,7 +218,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 0.000 7.245 0.018 ; + RECT 7.263 0.000 7.281 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -245,7 +227,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.695 0.000 7.713 0.018 ; + RECT 7.767 0.000 7.785 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -254,7 +236,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.163 0.000 8.181 0.018 ; + RECT 8.271 0.000 8.289 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -263,7 +245,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 0.000 8.649 0.018 ; + RECT 8.775 0.000 8.793 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -272,7 +254,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.099 0.000 9.117 0.018 ; + RECT 0.207 12.167 0.225 12.221 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -281,7 +263,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 5.166 0.225 5.184 ; + RECT 0.855 12.167 0.873 12.221 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -290,7 +272,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.855 5.166 0.873 5.184 ; + RECT 1.503 12.167 1.521 12.221 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -299,7 +281,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.503 5.166 1.521 5.184 ; + RECT 2.151 12.167 2.169 12.221 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -308,7 +290,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.151 5.166 2.169 5.184 ; + RECT 2.799 12.167 2.817 12.221 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -317,7 +299,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.799 5.166 2.817 5.184 ; + RECT 3.447 12.167 3.465 12.221 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -326,7 +308,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 5.166 3.465 5.184 ; + RECT 4.095 12.167 4.113 12.221 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -335,7 +317,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.095 5.166 4.113 5.184 ; + RECT 4.743 12.167 4.761 12.221 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -344,34 +326,16 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 5.166 4.761 5.184 ; + RECT 5.391 12.167 5.409 12.221 ; END END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.391 5.166 5.409 5.184 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.039 5.166 6.057 5.184 ; - END - END r0_rd_out[19] PIN w0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.196 0.024 2.220 ; + RECT 0.000 5.316 0.072 5.340 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -380,7 +344,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; + RECT 0.000 6.324 0.072 6.348 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -389,7 +353,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.964 0.024 2.988 ; + RECT 0.000 7.332 0.072 7.356 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -398,7 +362,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.196 10.368 2.220 ; + RECT 9.571 4.308 9.643 4.332 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -407,7 +371,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.580 10.368 2.604 ; + RECT 9.571 5.316 9.643 5.340 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -416,7 +380,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.964 10.368 2.988 ; + RECT 9.571 6.324 9.643 6.348 ; END END w0_addr_in[5] PIN r0_addr_in[0] @@ -425,7 +389,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.348 0.024 3.372 ; + RECT 0.000 8.340 0.072 8.364 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -434,7 +398,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; + RECT 0.000 9.348 0.072 9.372 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -443,7 +407,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.116 0.024 4.140 ; + RECT 0.000 10.356 0.072 10.380 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -452,7 +416,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.348 10.368 3.372 ; + RECT 9.571 7.332 9.643 7.356 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -461,7 +425,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 3.732 10.368 3.756 ; + RECT 9.571 8.340 9.643 8.364 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -470,7 +434,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 4.116 10.368 4.140 ; + RECT 9.571 9.348 9.643 9.372 ; END END r0_addr_in[5] PIN w0_we_in @@ -479,7 +443,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 5.166 6.705 5.184 ; + RECT 6.039 12.167 6.057 12.221 ; END END w0_we_in PIN w0_ce_in @@ -488,7 +452,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 5.166 7.353 5.184 ; + RECT 6.687 12.167 6.705 12.221 ; END END w0_ce_in PIN w0_clk @@ -497,7 +461,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.983 5.166 8.001 5.184 ; + RECT 7.335 12.167 7.353 12.221 ; END END w0_clk PIN r0_ce_in @@ -506,7 +470,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 5.166 8.649 5.184 ; + RECT 7.983 12.167 8.001 12.221 ; END END r0_ce_in PIN r0_clk @@ -515,7 +479,7 @@ MACRO fakeram_20x64_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 5.166 9.297 5.184 ; + RECT 8.631 12.167 8.649 12.221 ; END END r0_clk PIN VSS @@ -523,13 +487,22 @@ MACRO fakeram_20x64_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; END END VSS PIN VDD @@ -537,25 +510,34 @@ MACRO fakeram_20x64_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; END END VDD OBS LAYER M1 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 12.221 ; LAYER M2 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 12.221 ; LAYER M3 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 12.221 ; LAYER M4 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 12.221 ; END -END fakeram_20x64_1r1w +END fakeram_18x64_1r1w END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_192x32_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_192x32_1r1w.lef new file mode 100644 index 0000000..a51ddab --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_192x32_1r1w.lef @@ -0,0 +1,3681 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_192x32_1r1w + FOREIGN fakeram_192x32_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 57.854 BY 21.428 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.412 0.072 11.436 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.180 0.072 12.204 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.564 0.072 12.588 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.332 0.072 13.356 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.484 0.072 14.508 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.020 0.072 16.044 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.788 0.072 16.812 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.324 0.072 18.348 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 0.276 57.854 0.300 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 0.660 57.854 0.684 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 1.044 57.854 1.068 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 1.428 57.854 1.452 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 1.812 57.854 1.836 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 2.196 57.854 2.220 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 2.580 57.854 2.604 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 2.964 57.854 2.988 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 3.348 57.854 3.372 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 3.732 57.854 3.756 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 4.116 57.854 4.140 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 4.500 57.854 4.524 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 4.884 57.854 4.908 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 5.268 57.854 5.292 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 5.652 57.854 5.676 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 6.036 57.854 6.060 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 6.420 57.854 6.444 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 6.804 57.854 6.828 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 7.188 57.854 7.212 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 7.572 57.854 7.596 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 7.956 57.854 7.980 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 8.340 57.854 8.364 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 8.724 57.854 8.748 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 9.108 57.854 9.132 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 9.492 57.854 9.516 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 9.876 57.854 9.900 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 10.260 57.854 10.284 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 10.644 57.854 10.668 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 11.028 57.854 11.052 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 11.412 57.854 11.436 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 11.796 57.854 11.820 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 12.180 57.854 12.204 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 12.564 57.854 12.588 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 12.948 57.854 12.972 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 13.332 57.854 13.356 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 13.716 57.854 13.740 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 14.100 57.854 14.124 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 14.484 57.854 14.508 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 14.868 57.854 14.892 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 15.252 57.854 15.276 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 15.636 57.854 15.660 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 16.020 57.854 16.044 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 16.404 57.854 16.428 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 16.788 57.854 16.812 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 17.172 57.854 17.196 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 17.556 57.854 17.580 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 17.940 57.854 17.964 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 18.324 57.854 18.348 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[191] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 21.374 0.225 21.428 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 21.374 0.765 21.428 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 21.374 1.305 21.428 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 21.374 1.845 21.428 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 21.374 2.385 21.428 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 21.374 2.925 21.428 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 21.374 3.465 21.428 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 21.374 4.005 21.428 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 21.374 4.545 21.428 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 21.374 5.085 21.428 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 21.374 5.625 21.428 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 21.374 6.165 21.428 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 21.374 6.705 21.428 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 21.374 7.245 21.428 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 21.374 7.785 21.428 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 21.374 8.325 21.428 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 21.374 8.865 21.428 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 21.374 9.405 21.428 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 21.374 9.945 21.428 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 21.374 10.485 21.428 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 21.374 11.025 21.428 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 21.374 11.565 21.428 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 21.374 12.105 21.428 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 21.374 12.645 21.428 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 21.374 13.185 21.428 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 21.374 13.725 21.428 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 21.374 14.265 21.428 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 21.374 14.805 21.428 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 21.374 15.345 21.428 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 21.374 15.885 21.428 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 21.374 16.425 21.428 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 21.374 16.965 21.428 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 21.374 17.505 21.428 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 21.374 18.045 21.428 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 21.374 18.585 21.428 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 21.374 19.125 21.428 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 21.374 19.665 21.428 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 21.374 20.205 21.428 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 21.374 20.745 21.428 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 21.374 21.285 21.428 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 21.374 21.825 21.428 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 21.374 22.365 21.428 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 21.374 22.905 21.428 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 21.374 23.445 21.428 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 21.374 23.985 21.428 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 21.374 24.525 21.428 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 21.374 25.065 21.428 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 21.374 25.605 21.428 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 21.374 26.145 21.428 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 21.374 26.685 21.428 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 21.374 27.225 21.428 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 21.374 27.765 21.428 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 21.374 28.305 21.428 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 21.374 28.845 21.428 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 21.374 29.385 21.428 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 21.374 29.925 21.428 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 21.374 30.465 21.428 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 21.374 31.005 21.428 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 21.374 31.545 21.428 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 21.374 32.085 21.428 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 21.374 32.625 21.428 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 21.374 33.165 21.428 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 21.374 33.705 21.428 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 21.374 34.245 21.428 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 21.374 34.785 21.428 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 21.374 35.325 21.428 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 21.374 35.865 21.428 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 21.374 36.405 21.428 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 21.374 36.945 21.428 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 21.374 37.485 21.428 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 21.374 38.025 21.428 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 21.374 38.565 21.428 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 21.374 39.105 21.428 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 21.374 39.645 21.428 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 21.374 40.185 21.428 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 21.374 40.725 21.428 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 21.374 41.265 21.428 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 21.374 41.805 21.428 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 21.374 42.345 21.428 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 21.374 42.885 21.428 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 21.374 43.425 21.428 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 21.374 43.965 21.428 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 21.374 44.505 21.428 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 21.374 45.045 21.428 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 21.374 45.585 21.428 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 21.374 46.125 21.428 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 21.374 46.665 21.428 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 21.374 47.205 21.428 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 21.374 47.745 21.428 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 21.374 48.285 21.428 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 21.374 48.825 21.428 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 21.374 49.365 21.428 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 21.374 49.905 21.428 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 21.374 50.445 21.428 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 21.374 50.985 21.428 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 21.374 51.525 21.428 ; + END + END r0_rd_out[191] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 18.708 57.854 18.732 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 19.092 57.854 19.116 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.244 0.072 20.268 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.628 0.072 20.652 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 19.476 57.854 19.500 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 57.782 19.860 57.854 19.884 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 21.374 52.065 21.428 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 21.374 52.605 21.428 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 21.374 53.145 21.428 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 21.374 53.685 21.428 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 21.374 54.225 21.428 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 57.638 0.336 ; + RECT 0.216 1.008 57.638 1.104 ; + RECT 0.216 1.776 57.638 1.872 ; + RECT 0.216 2.544 57.638 2.640 ; + RECT 0.216 3.312 57.638 3.408 ; + RECT 0.216 4.080 57.638 4.176 ; + RECT 0.216 4.848 57.638 4.944 ; + RECT 0.216 5.616 57.638 5.712 ; + RECT 0.216 6.384 57.638 6.480 ; + RECT 0.216 7.152 57.638 7.248 ; + RECT 0.216 7.920 57.638 8.016 ; + RECT 0.216 8.688 57.638 8.784 ; + RECT 0.216 9.456 57.638 9.552 ; + RECT 0.216 10.224 57.638 10.320 ; + RECT 0.216 10.992 57.638 11.088 ; + RECT 0.216 11.760 57.638 11.856 ; + RECT 0.216 12.528 57.638 12.624 ; + RECT 0.216 13.296 57.638 13.392 ; + RECT 0.216 14.064 57.638 14.160 ; + RECT 0.216 14.832 57.638 14.928 ; + RECT 0.216 15.600 57.638 15.696 ; + RECT 0.216 16.368 57.638 16.464 ; + RECT 0.216 17.136 57.638 17.232 ; + RECT 0.216 17.904 57.638 18.000 ; + RECT 0.216 18.672 57.638 18.768 ; + RECT 0.216 19.440 57.638 19.536 ; + RECT 0.216 20.208 57.638 20.304 ; + RECT 0.216 20.976 57.638 21.072 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 57.638 0.336 ; + RECT 0.216 1.008 57.638 1.104 ; + RECT 0.216 1.776 57.638 1.872 ; + RECT 0.216 2.544 57.638 2.640 ; + RECT 0.216 3.312 57.638 3.408 ; + RECT 0.216 4.080 57.638 4.176 ; + RECT 0.216 4.848 57.638 4.944 ; + RECT 0.216 5.616 57.638 5.712 ; + RECT 0.216 6.384 57.638 6.480 ; + RECT 0.216 7.152 57.638 7.248 ; + RECT 0.216 7.920 57.638 8.016 ; + RECT 0.216 8.688 57.638 8.784 ; + RECT 0.216 9.456 57.638 9.552 ; + RECT 0.216 10.224 57.638 10.320 ; + RECT 0.216 10.992 57.638 11.088 ; + RECT 0.216 11.760 57.638 11.856 ; + RECT 0.216 12.528 57.638 12.624 ; + RECT 0.216 13.296 57.638 13.392 ; + RECT 0.216 14.064 57.638 14.160 ; + RECT 0.216 14.832 57.638 14.928 ; + RECT 0.216 15.600 57.638 15.696 ; + RECT 0.216 16.368 57.638 16.464 ; + RECT 0.216 17.136 57.638 17.232 ; + RECT 0.216 17.904 57.638 18.000 ; + RECT 0.216 18.672 57.638 18.768 ; + RECT 0.216 19.440 57.638 19.536 ; + RECT 0.216 20.208 57.638 20.304 ; + RECT 0.216 20.976 57.638 21.072 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 57.854 21.428 ; + LAYER M2 ; + RECT 0 0 57.854 21.428 ; + LAYER M3 ; + RECT 0 0 57.854 21.428 ; + LAYER M4 ; + RECT 0 0 57.854 21.428 ; + END +END fakeram_192x32_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_224x32_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_224x32_1r1w.lef new file mode 100644 index 0000000..542715d --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_224x32_1r1w.lef @@ -0,0 +1,4263 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_224x32_1r1w + FOREIGN fakeram_224x32_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 67.496 BY 24.106 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.412 0.072 11.436 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.180 0.072 12.204 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.564 0.072 12.588 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.332 0.072 13.356 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.484 0.072 14.508 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.020 0.072 16.044 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.788 0.072 16.812 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.324 0.072 18.348 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.244 0.072 20.268 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.628 0.072 20.652 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 0.276 67.496 0.300 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 0.660 67.496 0.684 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 1.044 67.496 1.068 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 1.428 67.496 1.452 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 1.812 67.496 1.836 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 2.196 67.496 2.220 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 2.580 67.496 2.604 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 2.964 67.496 2.988 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 3.348 67.496 3.372 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 3.732 67.496 3.756 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 4.116 67.496 4.140 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 4.500 67.496 4.524 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 4.884 67.496 4.908 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 5.268 67.496 5.292 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 5.652 67.496 5.676 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 6.036 67.496 6.060 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 6.420 67.496 6.444 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 6.804 67.496 6.828 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 7.188 67.496 7.212 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 7.572 67.496 7.596 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 7.956 67.496 7.980 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 8.340 67.496 8.364 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 8.724 67.496 8.748 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 9.108 67.496 9.132 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 9.492 67.496 9.516 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 9.876 67.496 9.900 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 10.260 67.496 10.284 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 10.644 67.496 10.668 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 11.028 67.496 11.052 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 11.412 67.496 11.436 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 11.796 67.496 11.820 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 12.180 67.496 12.204 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 12.564 67.496 12.588 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 12.948 67.496 12.972 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 13.332 67.496 13.356 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 13.716 67.496 13.740 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 14.100 67.496 14.124 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 14.484 67.496 14.508 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 14.868 67.496 14.892 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 15.252 67.496 15.276 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 15.636 67.496 15.660 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 16.020 67.496 16.044 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 16.404 67.496 16.428 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 16.788 67.496 16.812 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 17.172 67.496 17.196 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 17.556 67.496 17.580 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 17.940 67.496 17.964 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 18.324 67.496 18.348 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 18.708 67.496 18.732 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 19.092 67.496 19.116 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 19.476 67.496 19.500 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 19.860 67.496 19.884 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 20.244 67.496 20.268 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 20.628 67.496 20.652 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 21.012 67.496 21.036 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 21.396 67.496 21.420 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[223] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 24.052 0.225 24.106 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 24.052 0.765 24.106 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 24.052 1.305 24.106 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 24.052 1.845 24.106 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 24.052 2.385 24.106 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 24.052 2.925 24.106 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 24.052 3.465 24.106 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 24.052 4.005 24.106 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 24.052 4.545 24.106 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 24.052 5.085 24.106 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 24.052 5.625 24.106 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 24.052 6.165 24.106 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 24.052 6.705 24.106 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 24.052 7.245 24.106 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 24.052 7.785 24.106 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 24.052 8.325 24.106 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 24.052 8.865 24.106 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 24.052 9.405 24.106 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 24.052 9.945 24.106 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 24.052 10.485 24.106 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 24.052 11.025 24.106 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 24.052 11.565 24.106 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 24.052 12.105 24.106 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 24.052 12.645 24.106 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 24.052 13.185 24.106 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 24.052 13.725 24.106 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 24.052 14.265 24.106 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 24.052 14.805 24.106 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 24.052 15.345 24.106 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 24.052 15.885 24.106 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 24.052 16.425 24.106 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 24.052 16.965 24.106 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 24.052 17.505 24.106 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 24.052 18.045 24.106 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 24.052 18.585 24.106 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 24.052 19.125 24.106 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 24.052 19.665 24.106 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 24.052 20.205 24.106 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 24.052 20.745 24.106 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 24.052 21.285 24.106 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 24.052 21.825 24.106 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 24.052 22.365 24.106 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 24.052 22.905 24.106 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 24.052 23.445 24.106 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 24.052 23.985 24.106 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 24.052 24.525 24.106 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 24.052 25.065 24.106 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 24.052 25.605 24.106 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 24.052 26.145 24.106 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 24.052 26.685 24.106 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 24.052 27.225 24.106 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 24.052 27.765 24.106 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 24.052 28.305 24.106 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 24.052 28.845 24.106 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 24.052 29.385 24.106 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 24.052 29.925 24.106 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 24.052 30.465 24.106 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 24.052 31.005 24.106 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 24.052 31.545 24.106 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 24.052 32.085 24.106 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 24.052 32.625 24.106 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 24.052 33.165 24.106 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 24.052 33.705 24.106 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 24.052 34.245 24.106 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 24.052 34.785 24.106 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 24.052 35.325 24.106 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 24.052 35.865 24.106 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 24.052 36.405 24.106 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 24.052 36.945 24.106 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 24.052 37.485 24.106 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 24.052 38.025 24.106 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 24.052 38.565 24.106 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 24.052 39.105 24.106 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 24.052 39.645 24.106 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 24.052 40.185 24.106 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 24.052 40.725 24.106 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 24.052 41.265 24.106 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 24.052 41.805 24.106 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 24.052 42.345 24.106 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 24.052 42.885 24.106 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 24.052 43.425 24.106 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 24.052 43.965 24.106 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 24.052 44.505 24.106 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 24.052 45.045 24.106 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 24.052 45.585 24.106 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 24.052 46.125 24.106 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 24.052 46.665 24.106 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 24.052 47.205 24.106 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 24.052 47.745 24.106 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 24.052 48.285 24.106 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 24.052 48.825 24.106 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 24.052 49.365 24.106 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 24.052 49.905 24.106 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 24.052 50.445 24.106 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 24.052 50.985 24.106 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 24.052 51.525 24.106 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 24.052 52.065 24.106 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 24.052 52.605 24.106 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 24.052 53.145 24.106 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 24.052 53.685 24.106 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 24.052 54.225 24.106 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 24.052 54.765 24.106 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 24.052 55.305 24.106 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 24.052 55.845 24.106 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 24.052 56.385 24.106 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 24.052 56.925 24.106 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 24.052 57.465 24.106 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 24.052 58.005 24.106 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 24.052 58.545 24.106 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 24.052 59.085 24.106 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 24.052 59.625 24.106 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 24.052 60.165 24.106 ; + END + END r0_rd_out[223] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.548 0.072 22.572 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 21.780 67.496 21.804 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 22.164 67.496 22.188 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.932 0.072 22.956 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.700 0.072 23.724 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 22.548 67.496 22.572 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 22.932 67.496 22.956 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 24.052 60.705 24.106 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 24.052 61.245 24.106 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 24.052 61.785 24.106 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 24.052 62.325 24.106 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 24.052 62.865 24.106 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.280 0.336 ; + RECT 0.216 1.008 67.280 1.104 ; + RECT 0.216 1.776 67.280 1.872 ; + RECT 0.216 2.544 67.280 2.640 ; + RECT 0.216 3.312 67.280 3.408 ; + RECT 0.216 4.080 67.280 4.176 ; + RECT 0.216 4.848 67.280 4.944 ; + RECT 0.216 5.616 67.280 5.712 ; + RECT 0.216 6.384 67.280 6.480 ; + RECT 0.216 7.152 67.280 7.248 ; + RECT 0.216 7.920 67.280 8.016 ; + RECT 0.216 8.688 67.280 8.784 ; + RECT 0.216 9.456 67.280 9.552 ; + RECT 0.216 10.224 67.280 10.320 ; + RECT 0.216 10.992 67.280 11.088 ; + RECT 0.216 11.760 67.280 11.856 ; + RECT 0.216 12.528 67.280 12.624 ; + RECT 0.216 13.296 67.280 13.392 ; + RECT 0.216 14.064 67.280 14.160 ; + RECT 0.216 14.832 67.280 14.928 ; + RECT 0.216 15.600 67.280 15.696 ; + RECT 0.216 16.368 67.280 16.464 ; + RECT 0.216 17.136 67.280 17.232 ; + RECT 0.216 17.904 67.280 18.000 ; + RECT 0.216 18.672 67.280 18.768 ; + RECT 0.216 19.440 67.280 19.536 ; + RECT 0.216 20.208 67.280 20.304 ; + RECT 0.216 20.976 67.280 21.072 ; + RECT 0.216 21.744 67.280 21.840 ; + RECT 0.216 22.512 67.280 22.608 ; + RECT 0.216 23.280 67.280 23.376 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.280 0.336 ; + RECT 0.216 1.008 67.280 1.104 ; + RECT 0.216 1.776 67.280 1.872 ; + RECT 0.216 2.544 67.280 2.640 ; + RECT 0.216 3.312 67.280 3.408 ; + RECT 0.216 4.080 67.280 4.176 ; + RECT 0.216 4.848 67.280 4.944 ; + RECT 0.216 5.616 67.280 5.712 ; + RECT 0.216 6.384 67.280 6.480 ; + RECT 0.216 7.152 67.280 7.248 ; + RECT 0.216 7.920 67.280 8.016 ; + RECT 0.216 8.688 67.280 8.784 ; + RECT 0.216 9.456 67.280 9.552 ; + RECT 0.216 10.224 67.280 10.320 ; + RECT 0.216 10.992 67.280 11.088 ; + RECT 0.216 11.760 67.280 11.856 ; + RECT 0.216 12.528 67.280 12.624 ; + RECT 0.216 13.296 67.280 13.392 ; + RECT 0.216 14.064 67.280 14.160 ; + RECT 0.216 14.832 67.280 14.928 ; + RECT 0.216 15.600 67.280 15.696 ; + RECT 0.216 16.368 67.280 16.464 ; + RECT 0.216 17.136 67.280 17.232 ; + RECT 0.216 17.904 67.280 18.000 ; + RECT 0.216 18.672 67.280 18.768 ; + RECT 0.216 19.440 67.280 19.536 ; + RECT 0.216 20.208 67.280 20.304 ; + RECT 0.216 20.976 67.280 21.072 ; + RECT 0.216 21.744 67.280 21.840 ; + RECT 0.216 22.512 67.280 22.608 ; + RECT 0.216 23.280 67.280 23.376 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 67.496 24.106 ; + LAYER M2 ; + RECT 0 0 67.496 24.106 ; + LAYER M3 ; + RECT 0 0 67.496 24.106 ; + LAYER M4 ; + RECT 0 0 67.496 24.106 ; + END +END fakeram_224x32_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_224x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_224x64_1r1w.lef new file mode 100644 index 0000000..1028500 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_224x64_1r1w.lef @@ -0,0 +1,4295 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_224x64_1r1w + FOREIGN fakeram_224x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 67.496 BY 29.463 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 0.276 67.496 0.300 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 0.708 67.496 0.732 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 1.140 67.496 1.164 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 1.572 67.496 1.596 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 2.004 67.496 2.028 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 2.436 67.496 2.460 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 2.868 67.496 2.892 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 3.300 67.496 3.324 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 3.732 67.496 3.756 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 4.164 67.496 4.188 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 4.596 67.496 4.620 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 5.028 67.496 5.052 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 5.460 67.496 5.484 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 5.892 67.496 5.916 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 6.324 67.496 6.348 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 6.756 67.496 6.780 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 7.188 67.496 7.212 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 7.620 67.496 7.644 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 8.052 67.496 8.076 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 8.484 67.496 8.508 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 8.916 67.496 8.940 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 9.348 67.496 9.372 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 9.780 67.496 9.804 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 10.212 67.496 10.236 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 10.644 67.496 10.668 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 11.076 67.496 11.100 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 11.508 67.496 11.532 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 11.940 67.496 11.964 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 12.372 67.496 12.396 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 12.804 67.496 12.828 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 13.236 67.496 13.260 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 13.668 67.496 13.692 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 14.100 67.496 14.124 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 14.532 67.496 14.556 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 14.964 67.496 14.988 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 15.396 67.496 15.420 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 15.828 67.496 15.852 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 16.260 67.496 16.284 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 16.692 67.496 16.716 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 17.124 67.496 17.148 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 17.556 67.496 17.580 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 17.988 67.496 18.012 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 18.420 67.496 18.444 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 18.852 67.496 18.876 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 19.284 67.496 19.308 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 19.716 67.496 19.740 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 20.148 67.496 20.172 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 20.580 67.496 20.604 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 21.012 67.496 21.036 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 21.444 67.496 21.468 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 21.876 67.496 21.900 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 22.308 67.496 22.332 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 22.740 67.496 22.764 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 23.172 67.496 23.196 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 23.604 67.496 23.628 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 24.036 67.496 24.060 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[223] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 29.409 0.225 29.463 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 29.409 0.765 29.463 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 29.409 1.305 29.463 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 29.409 1.845 29.463 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 29.409 2.385 29.463 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 29.409 2.925 29.463 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 29.409 3.465 29.463 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 29.409 4.005 29.463 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 29.409 4.545 29.463 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 29.409 5.085 29.463 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 29.409 5.625 29.463 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 29.409 6.165 29.463 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 29.409 6.705 29.463 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 29.409 7.245 29.463 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 29.409 7.785 29.463 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 29.409 8.325 29.463 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 29.409 8.865 29.463 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 29.409 9.405 29.463 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 29.409 9.945 29.463 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 29.409 10.485 29.463 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 29.409 11.025 29.463 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 29.409 11.565 29.463 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 29.409 12.105 29.463 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 29.409 12.645 29.463 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 29.409 13.185 29.463 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 29.409 13.725 29.463 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 29.409 14.265 29.463 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 29.409 14.805 29.463 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 29.409 15.345 29.463 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 29.409 15.885 29.463 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 29.409 16.425 29.463 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 29.409 16.965 29.463 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 29.409 17.505 29.463 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 29.409 18.045 29.463 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 29.409 18.585 29.463 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 29.409 19.125 29.463 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 29.409 19.665 29.463 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 29.409 20.205 29.463 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 29.409 20.745 29.463 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 29.409 21.285 29.463 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 29.409 21.825 29.463 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 29.409 22.365 29.463 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 29.409 22.905 29.463 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 29.409 23.445 29.463 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 29.409 23.985 29.463 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 29.409 24.525 29.463 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 29.409 25.065 29.463 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 29.409 25.605 29.463 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 29.409 26.145 29.463 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 29.409 26.685 29.463 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 29.409 27.225 29.463 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 29.409 27.765 29.463 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 29.409 28.305 29.463 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 29.409 28.845 29.463 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 29.409 29.385 29.463 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 29.409 29.925 29.463 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 29.409 30.465 29.463 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 29.409 31.005 29.463 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 29.409 31.545 29.463 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 29.409 32.085 29.463 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 29.409 32.625 29.463 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 29.409 33.165 29.463 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 29.409 33.705 29.463 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 29.409 34.245 29.463 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 29.409 34.785 29.463 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 29.409 35.325 29.463 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 29.409 35.865 29.463 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 29.409 36.405 29.463 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 29.409 36.945 29.463 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 29.409 37.485 29.463 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 29.409 38.025 29.463 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 29.409 38.565 29.463 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 29.409 39.105 29.463 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 29.409 39.645 29.463 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 29.409 40.185 29.463 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 29.409 40.725 29.463 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 29.409 41.265 29.463 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 29.409 41.805 29.463 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 29.409 42.345 29.463 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 29.409 42.885 29.463 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 29.409 43.425 29.463 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 29.409 43.965 29.463 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 29.409 44.505 29.463 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 29.409 45.045 29.463 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 29.409 45.585 29.463 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 29.409 46.125 29.463 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 29.409 46.665 29.463 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 29.409 47.205 29.463 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 29.409 47.745 29.463 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 29.409 48.285 29.463 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 29.409 48.825 29.463 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 29.409 49.365 29.463 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 29.409 49.905 29.463 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 29.409 50.445 29.463 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 29.409 50.985 29.463 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 29.409 51.525 29.463 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 29.409 52.065 29.463 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 29.409 52.605 29.463 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 29.409 53.145 29.463 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 29.409 53.685 29.463 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 29.409 54.225 29.463 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 29.409 54.765 29.463 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 29.409 55.305 29.463 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 29.409 55.845 29.463 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 29.409 56.385 29.463 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 29.409 56.925 29.463 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 29.409 57.465 29.463 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 29.409 58.005 29.463 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 29.409 58.545 29.463 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 29.409 59.085 29.463 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 29.409 59.625 29.463 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 29.409 60.165 29.463 ; + END + END r0_rd_out[223] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 24.468 67.496 24.492 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 24.900 67.496 24.924 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 25.332 67.496 25.356 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 25.764 67.496 25.788 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 26.196 67.496 26.220 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 67.424 26.628 67.496 26.652 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 29.409 60.705 29.463 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 29.409 61.245 29.463 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 29.409 61.785 29.463 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 29.409 62.325 29.463 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 29.409 62.865 29.463 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.280 0.336 ; + RECT 0.216 1.008 67.280 1.104 ; + RECT 0.216 1.776 67.280 1.872 ; + RECT 0.216 2.544 67.280 2.640 ; + RECT 0.216 3.312 67.280 3.408 ; + RECT 0.216 4.080 67.280 4.176 ; + RECT 0.216 4.848 67.280 4.944 ; + RECT 0.216 5.616 67.280 5.712 ; + RECT 0.216 6.384 67.280 6.480 ; + RECT 0.216 7.152 67.280 7.248 ; + RECT 0.216 7.920 67.280 8.016 ; + RECT 0.216 8.688 67.280 8.784 ; + RECT 0.216 9.456 67.280 9.552 ; + RECT 0.216 10.224 67.280 10.320 ; + RECT 0.216 10.992 67.280 11.088 ; + RECT 0.216 11.760 67.280 11.856 ; + RECT 0.216 12.528 67.280 12.624 ; + RECT 0.216 13.296 67.280 13.392 ; + RECT 0.216 14.064 67.280 14.160 ; + RECT 0.216 14.832 67.280 14.928 ; + RECT 0.216 15.600 67.280 15.696 ; + RECT 0.216 16.368 67.280 16.464 ; + RECT 0.216 17.136 67.280 17.232 ; + RECT 0.216 17.904 67.280 18.000 ; + RECT 0.216 18.672 67.280 18.768 ; + RECT 0.216 19.440 67.280 19.536 ; + RECT 0.216 20.208 67.280 20.304 ; + RECT 0.216 20.976 67.280 21.072 ; + RECT 0.216 21.744 67.280 21.840 ; + RECT 0.216 22.512 67.280 22.608 ; + RECT 0.216 23.280 67.280 23.376 ; + RECT 0.216 24.048 67.280 24.144 ; + RECT 0.216 24.816 67.280 24.912 ; + RECT 0.216 25.584 67.280 25.680 ; + RECT 0.216 26.352 67.280 26.448 ; + RECT 0.216 27.120 67.280 27.216 ; + RECT 0.216 27.888 67.280 27.984 ; + RECT 0.216 28.656 67.280 28.752 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.280 0.336 ; + RECT 0.216 1.008 67.280 1.104 ; + RECT 0.216 1.776 67.280 1.872 ; + RECT 0.216 2.544 67.280 2.640 ; + RECT 0.216 3.312 67.280 3.408 ; + RECT 0.216 4.080 67.280 4.176 ; + RECT 0.216 4.848 67.280 4.944 ; + RECT 0.216 5.616 67.280 5.712 ; + RECT 0.216 6.384 67.280 6.480 ; + RECT 0.216 7.152 67.280 7.248 ; + RECT 0.216 7.920 67.280 8.016 ; + RECT 0.216 8.688 67.280 8.784 ; + RECT 0.216 9.456 67.280 9.552 ; + RECT 0.216 10.224 67.280 10.320 ; + RECT 0.216 10.992 67.280 11.088 ; + RECT 0.216 11.760 67.280 11.856 ; + RECT 0.216 12.528 67.280 12.624 ; + RECT 0.216 13.296 67.280 13.392 ; + RECT 0.216 14.064 67.280 14.160 ; + RECT 0.216 14.832 67.280 14.928 ; + RECT 0.216 15.600 67.280 15.696 ; + RECT 0.216 16.368 67.280 16.464 ; + RECT 0.216 17.136 67.280 17.232 ; + RECT 0.216 17.904 67.280 18.000 ; + RECT 0.216 18.672 67.280 18.768 ; + RECT 0.216 19.440 67.280 19.536 ; + RECT 0.216 20.208 67.280 20.304 ; + RECT 0.216 20.976 67.280 21.072 ; + RECT 0.216 21.744 67.280 21.840 ; + RECT 0.216 22.512 67.280 22.608 ; + RECT 0.216 23.280 67.280 23.376 ; + RECT 0.216 24.048 67.280 24.144 ; + RECT 0.216 24.816 67.280 24.912 ; + RECT 0.216 25.584 67.280 25.680 ; + RECT 0.216 26.352 67.280 26.448 ; + RECT 0.216 27.120 67.280 27.216 ; + RECT 0.216 27.888 67.280 27.984 ; + RECT 0.216 28.656 67.280 28.752 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 67.496 29.463 ; + LAYER M2 ; + RECT 0 0 67.496 29.463 ; + LAYER M3 ; + RECT 0 0 67.496 29.463 ; + LAYER M4 ; + RECT 0 0 67.496 29.463 ; + END +END fakeram_224x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_226x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_226x64_1r1w.lef new file mode 100644 index 0000000..f1be651 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_226x64_1r1w.lef @@ -0,0 +1,4333 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_226x64_1r1w + FOREIGN fakeram_226x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 68.099 BY 29.630 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 0.276 68.099 0.300 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 0.708 68.099 0.732 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 1.140 68.099 1.164 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 1.572 68.099 1.596 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 2.004 68.099 2.028 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 2.436 68.099 2.460 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 2.868 68.099 2.892 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 3.300 68.099 3.324 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 3.732 68.099 3.756 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 4.164 68.099 4.188 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 4.596 68.099 4.620 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 5.028 68.099 5.052 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 5.460 68.099 5.484 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 5.892 68.099 5.916 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 6.324 68.099 6.348 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 6.756 68.099 6.780 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 7.188 68.099 7.212 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 7.620 68.099 7.644 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 8.052 68.099 8.076 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 8.484 68.099 8.508 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 8.916 68.099 8.940 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 9.348 68.099 9.372 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 9.780 68.099 9.804 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 10.212 68.099 10.236 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 10.644 68.099 10.668 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 11.076 68.099 11.100 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 11.508 68.099 11.532 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 11.940 68.099 11.964 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 12.372 68.099 12.396 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 12.804 68.099 12.828 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 13.236 68.099 13.260 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 13.668 68.099 13.692 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 14.100 68.099 14.124 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 14.532 68.099 14.556 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 14.964 68.099 14.988 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 15.396 68.099 15.420 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 15.828 68.099 15.852 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 16.260 68.099 16.284 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 16.692 68.099 16.716 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 17.124 68.099 17.148 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 17.556 68.099 17.580 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 17.988 68.099 18.012 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 18.420 68.099 18.444 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 18.852 68.099 18.876 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 19.284 68.099 19.308 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 19.716 68.099 19.740 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 20.148 68.099 20.172 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 20.580 68.099 20.604 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 21.012 68.099 21.036 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 21.444 68.099 21.468 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 21.876 68.099 21.900 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 22.308 68.099 22.332 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 22.740 68.099 22.764 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 23.172 68.099 23.196 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 23.604 68.099 23.628 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 24.036 68.099 24.060 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[225] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 29.576 0.225 29.630 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 29.576 0.765 29.630 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 29.576 1.305 29.630 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 29.576 1.845 29.630 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 29.576 2.385 29.630 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 29.576 2.925 29.630 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 29.576 3.465 29.630 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 29.576 4.005 29.630 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 29.576 4.545 29.630 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 29.576 5.085 29.630 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 29.576 5.625 29.630 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 29.576 6.165 29.630 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 29.576 6.705 29.630 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 29.576 7.245 29.630 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 29.576 7.785 29.630 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 29.576 8.325 29.630 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 29.576 8.865 29.630 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 29.576 9.405 29.630 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 29.576 9.945 29.630 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 29.576 10.485 29.630 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 29.576 11.025 29.630 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 29.576 11.565 29.630 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 29.576 12.105 29.630 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 29.576 12.645 29.630 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 29.576 13.185 29.630 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 29.576 13.725 29.630 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 29.576 14.265 29.630 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 29.576 14.805 29.630 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 29.576 15.345 29.630 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 29.576 15.885 29.630 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 29.576 16.425 29.630 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 29.576 16.965 29.630 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 29.576 17.505 29.630 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 29.576 18.045 29.630 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 29.576 18.585 29.630 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 29.576 19.125 29.630 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 29.576 19.665 29.630 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 29.576 20.205 29.630 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 29.576 20.745 29.630 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 29.576 21.285 29.630 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 29.576 21.825 29.630 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 29.576 22.365 29.630 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 29.576 22.905 29.630 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 29.576 23.445 29.630 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 29.576 23.985 29.630 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 29.576 24.525 29.630 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 29.576 25.065 29.630 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 29.576 25.605 29.630 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 29.576 26.145 29.630 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 29.576 26.685 29.630 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 29.576 27.225 29.630 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 29.576 27.765 29.630 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 29.576 28.305 29.630 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 29.576 28.845 29.630 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 29.576 29.385 29.630 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 29.576 29.925 29.630 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 29.576 30.465 29.630 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 29.576 31.005 29.630 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 29.576 31.545 29.630 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 29.576 32.085 29.630 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 29.576 32.625 29.630 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 29.576 33.165 29.630 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 29.576 33.705 29.630 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 29.576 34.245 29.630 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 29.576 34.785 29.630 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 29.576 35.325 29.630 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 29.576 35.865 29.630 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 29.576 36.405 29.630 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 29.576 36.945 29.630 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 29.576 37.485 29.630 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 29.576 38.025 29.630 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 29.576 38.565 29.630 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 29.576 39.105 29.630 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 29.576 39.645 29.630 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 29.576 40.185 29.630 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 29.576 40.725 29.630 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 29.576 41.265 29.630 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 29.576 41.805 29.630 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 29.576 42.345 29.630 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 29.576 42.885 29.630 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 29.576 43.425 29.630 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 29.576 43.965 29.630 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 29.576 44.505 29.630 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 29.576 45.045 29.630 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 29.576 45.585 29.630 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 29.576 46.125 29.630 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 29.576 46.665 29.630 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 29.576 47.205 29.630 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 29.576 47.745 29.630 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 29.576 48.285 29.630 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 29.576 48.825 29.630 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 29.576 49.365 29.630 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 29.576 49.905 29.630 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 29.576 50.445 29.630 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 29.576 50.985 29.630 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 29.576 51.525 29.630 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 29.576 52.065 29.630 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 29.576 52.605 29.630 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 29.576 53.145 29.630 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 29.576 53.685 29.630 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 29.576 54.225 29.630 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 29.576 54.765 29.630 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 29.576 55.305 29.630 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 29.576 55.845 29.630 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 29.576 56.385 29.630 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 29.576 56.925 29.630 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 29.576 57.465 29.630 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 29.576 58.005 29.630 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 29.576 58.545 29.630 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 29.576 59.085 29.630 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 29.576 59.625 29.630 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 29.576 60.165 29.630 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 29.576 60.705 29.630 ; + END + END r0_rd_out[225] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 24.468 68.099 24.492 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 24.900 68.099 24.924 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 25.332 68.099 25.356 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 25.764 68.099 25.788 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 26.196 68.099 26.220 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 26.628 68.099 26.652 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 29.576 61.245 29.630 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 29.576 61.785 29.630 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 29.576 62.325 29.630 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 29.576 62.865 29.630 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 29.576 63.405 29.630 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.883 0.336 ; + RECT 0.216 1.008 67.883 1.104 ; + RECT 0.216 1.776 67.883 1.872 ; + RECT 0.216 2.544 67.883 2.640 ; + RECT 0.216 3.312 67.883 3.408 ; + RECT 0.216 4.080 67.883 4.176 ; + RECT 0.216 4.848 67.883 4.944 ; + RECT 0.216 5.616 67.883 5.712 ; + RECT 0.216 6.384 67.883 6.480 ; + RECT 0.216 7.152 67.883 7.248 ; + RECT 0.216 7.920 67.883 8.016 ; + RECT 0.216 8.688 67.883 8.784 ; + RECT 0.216 9.456 67.883 9.552 ; + RECT 0.216 10.224 67.883 10.320 ; + RECT 0.216 10.992 67.883 11.088 ; + RECT 0.216 11.760 67.883 11.856 ; + RECT 0.216 12.528 67.883 12.624 ; + RECT 0.216 13.296 67.883 13.392 ; + RECT 0.216 14.064 67.883 14.160 ; + RECT 0.216 14.832 67.883 14.928 ; + RECT 0.216 15.600 67.883 15.696 ; + RECT 0.216 16.368 67.883 16.464 ; + RECT 0.216 17.136 67.883 17.232 ; + RECT 0.216 17.904 67.883 18.000 ; + RECT 0.216 18.672 67.883 18.768 ; + RECT 0.216 19.440 67.883 19.536 ; + RECT 0.216 20.208 67.883 20.304 ; + RECT 0.216 20.976 67.883 21.072 ; + RECT 0.216 21.744 67.883 21.840 ; + RECT 0.216 22.512 67.883 22.608 ; + RECT 0.216 23.280 67.883 23.376 ; + RECT 0.216 24.048 67.883 24.144 ; + RECT 0.216 24.816 67.883 24.912 ; + RECT 0.216 25.584 67.883 25.680 ; + RECT 0.216 26.352 67.883 26.448 ; + RECT 0.216 27.120 67.883 27.216 ; + RECT 0.216 27.888 67.883 27.984 ; + RECT 0.216 28.656 67.883 28.752 ; + RECT 0.216 29.424 67.883 29.520 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.883 0.336 ; + RECT 0.216 1.008 67.883 1.104 ; + RECT 0.216 1.776 67.883 1.872 ; + RECT 0.216 2.544 67.883 2.640 ; + RECT 0.216 3.312 67.883 3.408 ; + RECT 0.216 4.080 67.883 4.176 ; + RECT 0.216 4.848 67.883 4.944 ; + RECT 0.216 5.616 67.883 5.712 ; + RECT 0.216 6.384 67.883 6.480 ; + RECT 0.216 7.152 67.883 7.248 ; + RECT 0.216 7.920 67.883 8.016 ; + RECT 0.216 8.688 67.883 8.784 ; + RECT 0.216 9.456 67.883 9.552 ; + RECT 0.216 10.224 67.883 10.320 ; + RECT 0.216 10.992 67.883 11.088 ; + RECT 0.216 11.760 67.883 11.856 ; + RECT 0.216 12.528 67.883 12.624 ; + RECT 0.216 13.296 67.883 13.392 ; + RECT 0.216 14.064 67.883 14.160 ; + RECT 0.216 14.832 67.883 14.928 ; + RECT 0.216 15.600 67.883 15.696 ; + RECT 0.216 16.368 67.883 16.464 ; + RECT 0.216 17.136 67.883 17.232 ; + RECT 0.216 17.904 67.883 18.000 ; + RECT 0.216 18.672 67.883 18.768 ; + RECT 0.216 19.440 67.883 19.536 ; + RECT 0.216 20.208 67.883 20.304 ; + RECT 0.216 20.976 67.883 21.072 ; + RECT 0.216 21.744 67.883 21.840 ; + RECT 0.216 22.512 67.883 22.608 ; + RECT 0.216 23.280 67.883 23.376 ; + RECT 0.216 24.048 67.883 24.144 ; + RECT 0.216 24.816 67.883 24.912 ; + RECT 0.216 25.584 67.883 25.680 ; + RECT 0.216 26.352 67.883 26.448 ; + RECT 0.216 27.120 67.883 27.216 ; + RECT 0.216 27.888 67.883 27.984 ; + RECT 0.216 28.656 67.883 28.752 ; + RECT 0.216 29.424 67.883 29.520 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 68.099 29.630 ; + LAYER M2 ; + RECT 0 0 68.099 29.630 ; + LAYER M3 ; + RECT 0 0 68.099 29.630 ; + LAYER M4 ; + RECT 0 0 68.099 29.630 ; + END +END fakeram_226x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_226x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_226x80_1r1w.lef new file mode 100644 index 0000000..de4c5c1 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_226x80_1r1w.lef @@ -0,0 +1,4357 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_226x80_1r1w + FOREIGN fakeram_226x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 68.099 BY 32.309 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.276 0.072 24.300 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.236 0.072 25.260 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.716 0.072 25.740 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.676 0.072 26.700 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.156 0.072 27.180 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 0.276 68.099 0.300 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 0.756 68.099 0.780 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 1.236 68.099 1.260 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 1.716 68.099 1.740 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 2.196 68.099 2.220 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 2.676 68.099 2.700 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 3.156 68.099 3.180 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 3.636 68.099 3.660 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 4.116 68.099 4.140 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 4.596 68.099 4.620 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 5.076 68.099 5.100 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 5.556 68.099 5.580 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 6.036 68.099 6.060 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 6.516 68.099 6.540 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 6.996 68.099 7.020 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 7.476 68.099 7.500 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 7.956 68.099 7.980 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 8.436 68.099 8.460 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 8.916 68.099 8.940 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 9.396 68.099 9.420 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 9.876 68.099 9.900 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 10.356 68.099 10.380 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 10.836 68.099 10.860 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 11.316 68.099 11.340 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 11.796 68.099 11.820 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 12.276 68.099 12.300 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 12.756 68.099 12.780 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 13.236 68.099 13.260 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 13.716 68.099 13.740 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 14.196 68.099 14.220 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 14.676 68.099 14.700 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 15.156 68.099 15.180 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 15.636 68.099 15.660 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 16.116 68.099 16.140 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 16.596 68.099 16.620 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 17.076 68.099 17.100 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 17.556 68.099 17.580 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 18.036 68.099 18.060 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 18.516 68.099 18.540 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 18.996 68.099 19.020 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 19.476 68.099 19.500 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 19.956 68.099 19.980 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 20.436 68.099 20.460 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 20.916 68.099 20.940 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 21.396 68.099 21.420 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 21.876 68.099 21.900 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 22.356 68.099 22.380 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 22.836 68.099 22.860 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 23.316 68.099 23.340 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 23.796 68.099 23.820 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 24.276 68.099 24.300 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 24.756 68.099 24.780 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 25.236 68.099 25.260 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 25.716 68.099 25.740 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 26.196 68.099 26.220 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 26.676 68.099 26.700 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[225] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 32.255 0.225 32.309 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 32.255 0.765 32.309 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 32.255 1.305 32.309 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 32.255 1.845 32.309 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 32.255 2.385 32.309 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 32.255 2.925 32.309 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 32.255 3.465 32.309 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 32.255 4.005 32.309 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 32.255 4.545 32.309 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 32.255 5.085 32.309 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 32.255 5.625 32.309 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 32.255 6.165 32.309 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 32.255 6.705 32.309 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 32.255 7.245 32.309 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 32.255 7.785 32.309 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 32.255 8.325 32.309 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 32.255 8.865 32.309 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 32.255 9.405 32.309 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 32.255 9.945 32.309 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 32.255 10.485 32.309 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 32.255 11.025 32.309 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 32.255 11.565 32.309 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 32.255 12.105 32.309 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 32.255 12.645 32.309 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 32.255 13.185 32.309 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 32.255 13.725 32.309 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 32.255 14.265 32.309 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 32.255 14.805 32.309 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 32.255 15.345 32.309 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 32.255 15.885 32.309 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 32.255 16.425 32.309 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 32.255 16.965 32.309 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 32.255 17.505 32.309 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 32.255 18.045 32.309 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 32.255 18.585 32.309 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 32.255 19.125 32.309 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 32.255 19.665 32.309 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 32.255 20.205 32.309 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 32.255 20.745 32.309 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 32.255 21.285 32.309 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 32.255 21.825 32.309 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 32.255 22.365 32.309 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 32.255 22.905 32.309 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 32.255 23.445 32.309 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 32.255 23.985 32.309 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 32.255 24.525 32.309 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 32.255 25.065 32.309 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 32.255 25.605 32.309 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 32.255 26.145 32.309 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 32.255 26.685 32.309 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 32.255 27.225 32.309 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 32.255 27.765 32.309 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 32.255 28.305 32.309 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 32.255 28.845 32.309 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 32.255 29.385 32.309 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 32.255 29.925 32.309 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 32.255 30.465 32.309 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 32.255 31.005 32.309 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 32.255 31.545 32.309 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 32.255 32.085 32.309 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 32.255 32.625 32.309 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 32.255 33.165 32.309 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 32.255 33.705 32.309 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 32.255 34.245 32.309 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 32.255 34.785 32.309 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 32.255 35.325 32.309 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 32.255 35.865 32.309 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 32.255 36.405 32.309 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 32.255 36.945 32.309 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 32.255 37.485 32.309 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 32.255 38.025 32.309 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 32.255 38.565 32.309 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 32.255 39.105 32.309 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 32.255 39.645 32.309 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 32.255 40.185 32.309 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 32.255 40.725 32.309 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 32.255 41.265 32.309 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 32.255 41.805 32.309 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 32.255 42.345 32.309 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 32.255 42.885 32.309 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 32.255 43.425 32.309 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 32.255 43.965 32.309 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 32.255 44.505 32.309 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 32.255 45.045 32.309 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 32.255 45.585 32.309 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 32.255 46.125 32.309 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 32.255 46.665 32.309 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 32.255 47.205 32.309 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 32.255 47.745 32.309 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 32.255 48.285 32.309 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 32.255 48.825 32.309 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 32.255 49.365 32.309 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 32.255 49.905 32.309 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 32.255 50.445 32.309 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 32.255 50.985 32.309 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 32.255 51.525 32.309 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 32.255 52.065 32.309 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 32.255 52.605 32.309 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 32.255 53.145 32.309 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 32.255 53.685 32.309 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 32.255 54.225 32.309 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 32.255 54.765 32.309 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 32.255 55.305 32.309 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 32.255 55.845 32.309 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 32.255 56.385 32.309 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 32.255 56.925 32.309 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 32.255 57.465 32.309 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 32.255 58.005 32.309 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 32.255 58.545 32.309 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 32.255 59.085 32.309 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 32.255 59.625 32.309 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 32.255 60.165 32.309 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 32.255 60.705 32.309 ; + END + END r0_rd_out[225] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.116 0.072 28.140 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.596 0.072 28.620 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 27.156 68.099 27.180 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 27.636 68.099 27.660 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 28.116 68.099 28.140 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.556 0.072 29.580 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.036 0.072 30.060 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.996 0.072 31.020 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 28.596 68.099 28.620 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 29.076 68.099 29.100 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 68.027 29.556 68.099 29.580 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 32.255 61.245 32.309 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 32.255 61.785 32.309 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 32.255 62.325 32.309 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 32.255 62.865 32.309 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 32.255 63.405 32.309 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.883 0.336 ; + RECT 0.216 1.008 67.883 1.104 ; + RECT 0.216 1.776 67.883 1.872 ; + RECT 0.216 2.544 67.883 2.640 ; + RECT 0.216 3.312 67.883 3.408 ; + RECT 0.216 4.080 67.883 4.176 ; + RECT 0.216 4.848 67.883 4.944 ; + RECT 0.216 5.616 67.883 5.712 ; + RECT 0.216 6.384 67.883 6.480 ; + RECT 0.216 7.152 67.883 7.248 ; + RECT 0.216 7.920 67.883 8.016 ; + RECT 0.216 8.688 67.883 8.784 ; + RECT 0.216 9.456 67.883 9.552 ; + RECT 0.216 10.224 67.883 10.320 ; + RECT 0.216 10.992 67.883 11.088 ; + RECT 0.216 11.760 67.883 11.856 ; + RECT 0.216 12.528 67.883 12.624 ; + RECT 0.216 13.296 67.883 13.392 ; + RECT 0.216 14.064 67.883 14.160 ; + RECT 0.216 14.832 67.883 14.928 ; + RECT 0.216 15.600 67.883 15.696 ; + RECT 0.216 16.368 67.883 16.464 ; + RECT 0.216 17.136 67.883 17.232 ; + RECT 0.216 17.904 67.883 18.000 ; + RECT 0.216 18.672 67.883 18.768 ; + RECT 0.216 19.440 67.883 19.536 ; + RECT 0.216 20.208 67.883 20.304 ; + RECT 0.216 20.976 67.883 21.072 ; + RECT 0.216 21.744 67.883 21.840 ; + RECT 0.216 22.512 67.883 22.608 ; + RECT 0.216 23.280 67.883 23.376 ; + RECT 0.216 24.048 67.883 24.144 ; + RECT 0.216 24.816 67.883 24.912 ; + RECT 0.216 25.584 67.883 25.680 ; + RECT 0.216 26.352 67.883 26.448 ; + RECT 0.216 27.120 67.883 27.216 ; + RECT 0.216 27.888 67.883 27.984 ; + RECT 0.216 28.656 67.883 28.752 ; + RECT 0.216 29.424 67.883 29.520 ; + RECT 0.216 30.192 67.883 30.288 ; + RECT 0.216 30.960 67.883 31.056 ; + RECT 0.216 31.728 67.883 31.824 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 67.883 0.336 ; + RECT 0.216 1.008 67.883 1.104 ; + RECT 0.216 1.776 67.883 1.872 ; + RECT 0.216 2.544 67.883 2.640 ; + RECT 0.216 3.312 67.883 3.408 ; + RECT 0.216 4.080 67.883 4.176 ; + RECT 0.216 4.848 67.883 4.944 ; + RECT 0.216 5.616 67.883 5.712 ; + RECT 0.216 6.384 67.883 6.480 ; + RECT 0.216 7.152 67.883 7.248 ; + RECT 0.216 7.920 67.883 8.016 ; + RECT 0.216 8.688 67.883 8.784 ; + RECT 0.216 9.456 67.883 9.552 ; + RECT 0.216 10.224 67.883 10.320 ; + RECT 0.216 10.992 67.883 11.088 ; + RECT 0.216 11.760 67.883 11.856 ; + RECT 0.216 12.528 67.883 12.624 ; + RECT 0.216 13.296 67.883 13.392 ; + RECT 0.216 14.064 67.883 14.160 ; + RECT 0.216 14.832 67.883 14.928 ; + RECT 0.216 15.600 67.883 15.696 ; + RECT 0.216 16.368 67.883 16.464 ; + RECT 0.216 17.136 67.883 17.232 ; + RECT 0.216 17.904 67.883 18.000 ; + RECT 0.216 18.672 67.883 18.768 ; + RECT 0.216 19.440 67.883 19.536 ; + RECT 0.216 20.208 67.883 20.304 ; + RECT 0.216 20.976 67.883 21.072 ; + RECT 0.216 21.744 67.883 21.840 ; + RECT 0.216 22.512 67.883 22.608 ; + RECT 0.216 23.280 67.883 23.376 ; + RECT 0.216 24.048 67.883 24.144 ; + RECT 0.216 24.816 67.883 24.912 ; + RECT 0.216 25.584 67.883 25.680 ; + RECT 0.216 26.352 67.883 26.448 ; + RECT 0.216 27.120 67.883 27.216 ; + RECT 0.216 27.888 67.883 27.984 ; + RECT 0.216 28.656 67.883 28.752 ; + RECT 0.216 29.424 67.883 29.520 ; + RECT 0.216 30.192 67.883 30.288 ; + RECT 0.216 30.960 67.883 31.056 ; + RECT 0.216 31.728 67.883 31.824 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 68.099 32.309 ; + LAYER M2 ; + RECT 0 0 68.099 32.309 ; + LAYER M3 ; + RECT 0 0 68.099 32.309 ; + LAYER M4 ; + RECT 0 0 68.099 32.309 ; + END +END fakeram_226x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_22x60_1r1w.lef similarity index 62% rename from designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef rename to designs/asap7/NVDLA/sram/lef/fakeram_22x60_1r1w.lef index 70786c2..4fb595d 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef +++ b/designs/asap7/NVDLA/sram/lef/fakeram_22x60_1r1w.lef @@ -1,9 +1,9 @@ VERSION 5.7 ; BUSBITCHARS "[]" ; -MACRO fakeram_18x256_1r1w - FOREIGN fakeram_18x256_1r1w 0 0 ; +MACRO fakeram_22x60_1r1w + FOREIGN fakeram_22x60_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 9.332 BY 20.736 ; + SIZE 9.643 BY 11.886 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -11,7 +11,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 0.276 0.072 0.300 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +20,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.812 0.024 1.836 ; + RECT 0.000 1.188 0.072 1.212 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.348 0.024 3.372 ; + RECT 0.000 2.100 0.072 2.124 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.884 0.024 4.908 ; + RECT 0.000 3.012 0.072 3.036 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.420 0.024 6.444 ; + RECT 0.000 3.924 0.072 3.948 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 0.276 9.332 0.300 ; + RECT 0.000 4.836 0.072 4.860 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 1.812 9.332 1.836 ; + RECT 9.571 0.276 9.643 0.300 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 3.348 9.332 3.372 ; + RECT 9.571 1.188 9.643 1.212 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,25 +83,25 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 4.884 9.332 4.908 ; + RECT 9.571 2.100 9.643 2.124 ; END END w0_wd_in[8] PIN w0_wd_in[9] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + LAYER M4 ; + RECT 9.571 3.012 9.643 3.036 ; END END w0_wd_in[9] PIN w0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.675 0.000 0.693 0.018 ; + LAYER M4 ; + RECT 9.571 3.924 9.643 3.948 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +110,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.143 0.000 1.161 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +119,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.611 0.000 1.629 0.018 ; + RECT 0.603 0.000 0.621 0.054 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +128,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.079 0.000 2.097 0.018 ; + RECT 0.999 0.000 1.017 0.054 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +137,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.547 0.000 2.565 0.018 ; + RECT 1.395 0.000 1.413 0.054 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,7 +146,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.015 0.000 3.033 0.018 ; + RECT 1.791 0.000 1.809 0.054 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +155,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.483 0.000 3.501 0.018 ; + RECT 2.187 0.000 2.205 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,16 +164,52 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.951 0.000 3.969 0.018 ; + RECT 2.583 0.000 2.601 0.054 ; END END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.979 0.000 2.997 0.054 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.771 0.000 3.789 0.054 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 0.000 4.185 0.054 ; + END + END w0_wd_in[21] PIN r0_rd_out[0] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 4.563 0.000 4.581 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -182,7 +218,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 0.000 4.905 0.018 ; + RECT 4.959 0.000 4.977 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -191,7 +227,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 0.000 5.373 0.018 ; + RECT 5.355 0.000 5.373 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -200,7 +236,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.823 0.000 5.841 0.018 ; + RECT 5.751 0.000 5.769 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -209,7 +245,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.291 0.000 6.309 0.018 ; + RECT 6.147 0.000 6.165 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -218,7 +254,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; + RECT 6.543 0.000 6.561 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -227,7 +263,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.227 0.000 7.245 0.018 ; + RECT 6.939 0.000 6.957 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -236,7 +272,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.695 0.000 7.713 0.018 ; + RECT 7.335 0.000 7.353 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -245,7 +281,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.163 0.000 8.181 0.018 ; + RECT 7.731 0.000 7.749 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -254,7 +290,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 20.718 0.225 20.736 ; + RECT 8.127 0.000 8.145 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -263,7 +299,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.819 20.718 0.837 20.736 ; + RECT 8.523 0.000 8.541 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -272,7 +308,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.431 20.718 1.449 20.736 ; + RECT 0.207 11.832 0.225 11.886 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -281,7 +317,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.043 20.718 2.061 20.736 ; + RECT 0.747 11.832 0.765 11.886 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -290,7 +326,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.655 20.718 2.673 20.736 ; + RECT 1.287 11.832 1.305 11.886 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -299,7 +335,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.267 20.718 3.285 20.736 ; + RECT 1.827 11.832 1.845 11.886 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -308,7 +344,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.879 20.718 3.897 20.736 ; + RECT 2.367 11.832 2.385 11.886 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -317,7 +353,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.491 20.718 4.509 20.736 ; + RECT 2.907 11.832 2.925 11.886 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -326,16 +362,52 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.103 20.718 5.121 20.736 ; + RECT 3.447 11.832 3.465 11.886 ; END END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 11.832 4.005 11.886 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 11.832 4.545 11.886 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 11.832 5.085 11.886 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 11.832 5.625 11.886 ; + END + END r0_rd_out[21] PIN w0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.956 0.024 7.980 ; + RECT 0.000 5.748 0.072 5.772 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -344,7 +416,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 9.492 0.024 9.516 ; + RECT 0.000 6.660 0.072 6.684 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -353,7 +425,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 11.028 0.024 11.052 ; + RECT 0.000 7.572 0.072 7.596 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -362,7 +434,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 12.564 0.024 12.588 ; + RECT 9.571 4.836 9.643 4.860 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -371,7 +443,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 6.420 9.332 6.444 ; + RECT 9.571 5.748 9.643 5.772 ; END END w0_addr_in[4] PIN w0_addr_in[5] @@ -380,34 +452,16 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 7.956 9.332 7.980 ; + RECT 9.571 6.660 9.643 6.684 ; END END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 9.308 9.492 9.332 9.516 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 9.308 11.028 9.332 11.052 ; - END - END w0_addr_in[7] PIN r0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 14.100 0.024 14.124 ; + RECT 0.000 8.484 0.072 8.508 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -416,7 +470,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 15.636 0.024 15.660 ; + RECT 0.000 9.396 0.072 9.420 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -425,7 +479,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 17.172 0.024 17.196 ; + RECT 0.000 10.308 0.072 10.332 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -434,7 +488,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 18.708 0.024 18.732 ; + RECT 9.571 7.572 9.643 7.596 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -443,7 +497,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 12.564 9.332 12.588 ; + RECT 9.571 8.484 9.643 8.508 ; END END r0_addr_in[4] PIN r0_addr_in[5] @@ -452,34 +506,16 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 9.308 14.100 9.332 14.124 ; + RECT 9.571 9.396 9.643 9.420 ; END END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 9.308 15.636 9.332 15.660 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 9.308 17.172 9.332 17.196 ; - END - END r0_addr_in[7] PIN w0_we_in DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.715 20.718 5.733 20.736 ; + RECT 6.147 11.832 6.165 11.886 ; END END w0_we_in PIN w0_ce_in @@ -488,7 +524,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.327 20.718 6.345 20.736 ; + RECT 6.687 11.832 6.705 11.886 ; END END w0_ce_in PIN w0_clk @@ -497,7 +533,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.939 20.718 6.957 20.736 ; + RECT 7.227 11.832 7.245 11.886 ; END END w0_clk PIN r0_ce_in @@ -506,7 +542,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.551 20.718 7.569 20.736 ; + RECT 7.767 11.832 7.785 11.886 ; END END r0_ce_in PIN r0_clk @@ -515,7 +551,7 @@ MACRO fakeram_18x256_1r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.163 20.718 8.181 20.736 ; + RECT 8.307 11.832 8.325 11.886 ; END END r0_clk PIN VSS @@ -523,33 +559,22 @@ MACRO fakeram_18x256_1r1w USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 9.224 0.288 ; - RECT 0.108 0.960 9.224 1.056 ; - RECT 0.108 1.728 9.224 1.824 ; - RECT 0.108 2.496 9.224 2.592 ; - RECT 0.108 3.264 9.224 3.360 ; - RECT 0.108 4.032 9.224 4.128 ; - RECT 0.108 4.800 9.224 4.896 ; - RECT 0.108 5.568 9.224 5.664 ; - RECT 0.108 6.336 9.224 6.432 ; - RECT 0.108 7.104 9.224 7.200 ; - RECT 0.108 7.872 9.224 7.968 ; - RECT 0.108 8.640 9.224 8.736 ; - RECT 0.108 9.408 9.224 9.504 ; - RECT 0.108 10.176 9.224 10.272 ; - RECT 0.108 10.944 9.224 11.040 ; - RECT 0.108 11.712 9.224 11.808 ; - RECT 0.108 12.480 9.224 12.576 ; - RECT 0.108 13.248 9.224 13.344 ; - RECT 0.108 14.016 9.224 14.112 ; - RECT 0.108 14.784 9.224 14.880 ; - RECT 0.108 15.552 9.224 15.648 ; - RECT 0.108 16.320 9.224 16.416 ; - RECT 0.108 17.088 9.224 17.184 ; - RECT 0.108 17.856 9.224 17.952 ; - RECT 0.108 18.624 9.224 18.720 ; - RECT 0.108 19.392 9.224 19.488 ; - RECT 0.108 20.160 9.224 20.256 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; END END VSS PIN VDD @@ -557,45 +582,34 @@ MACRO fakeram_18x256_1r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 9.224 0.288 ; - RECT 0.108 0.960 9.224 1.056 ; - RECT 0.108 1.728 9.224 1.824 ; - RECT 0.108 2.496 9.224 2.592 ; - RECT 0.108 3.264 9.224 3.360 ; - RECT 0.108 4.032 9.224 4.128 ; - RECT 0.108 4.800 9.224 4.896 ; - RECT 0.108 5.568 9.224 5.664 ; - RECT 0.108 6.336 9.224 6.432 ; - RECT 0.108 7.104 9.224 7.200 ; - RECT 0.108 7.872 9.224 7.968 ; - RECT 0.108 8.640 9.224 8.736 ; - RECT 0.108 9.408 9.224 9.504 ; - RECT 0.108 10.176 9.224 10.272 ; - RECT 0.108 10.944 9.224 11.040 ; - RECT 0.108 11.712 9.224 11.808 ; - RECT 0.108 12.480 9.224 12.576 ; - RECT 0.108 13.248 9.224 13.344 ; - RECT 0.108 14.016 9.224 14.112 ; - RECT 0.108 14.784 9.224 14.880 ; - RECT 0.108 15.552 9.224 15.648 ; - RECT 0.108 16.320 9.224 16.416 ; - RECT 0.108 17.088 9.224 17.184 ; - RECT 0.108 17.856 9.224 17.952 ; - RECT 0.108 18.624 9.224 18.720 ; - RECT 0.108 19.392 9.224 19.488 ; - RECT 0.108 20.160 9.224 20.256 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; END END VDD OBS LAYER M1 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 9.643 11.886 ; LAYER M2 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 9.643 11.886 ; LAYER M3 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 9.643 11.886 ; LAYER M4 ; - RECT 0 0 9.332 20.736 ; + RECT 0 0 9.643 11.886 ; END -END fakeram_18x256_1r1w +END fakeram_22x60_1r1w END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_256x128_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_256x128_1r1w.lef new file mode 100644 index 0000000..b2c2d2e --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_256x128_1r1w.lef @@ -0,0 +1,4925 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_256x128_1r1w + FOREIGN fakeram_256x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 77.138 BY 42.855 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.276 77.138 0.300 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.852 77.138 0.876 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.428 77.138 1.452 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.004 77.138 2.028 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.580 77.138 2.604 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.156 77.138 3.180 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.732 77.138 3.756 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.308 77.138 4.332 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.884 77.138 4.908 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.460 77.138 5.484 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.036 77.138 6.060 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.612 77.138 6.636 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.188 77.138 7.212 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.764 77.138 7.788 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.340 77.138 8.364 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.916 77.138 8.940 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.492 77.138 9.516 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.068 77.138 10.092 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.644 77.138 10.668 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.220 77.138 11.244 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.796 77.138 11.820 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.372 77.138 12.396 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.948 77.138 12.972 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.524 77.138 13.548 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.100 77.138 14.124 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.676 77.138 14.700 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.252 77.138 15.276 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.828 77.138 15.852 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.404 77.138 16.428 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.980 77.138 17.004 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.556 77.138 17.580 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.132 77.138 18.156 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.708 77.138 18.732 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.284 77.138 19.308 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.860 77.138 19.884 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.436 77.138 20.460 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.012 77.138 21.036 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.588 77.138 21.612 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.164 77.138 22.188 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.740 77.138 22.764 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 23.316 77.138 23.340 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 23.892 77.138 23.916 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 24.468 77.138 24.492 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 25.044 77.138 25.068 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 25.620 77.138 25.644 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 26.196 77.138 26.220 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 26.772 77.138 26.796 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 27.348 77.138 27.372 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 27.924 77.138 27.948 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 28.500 77.138 28.524 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 29.076 77.138 29.100 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 29.652 77.138 29.676 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 30.228 77.138 30.252 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 30.804 77.138 30.828 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 31.380 77.138 31.404 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 31.956 77.138 31.980 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 32.532 77.138 32.556 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 33.108 77.138 33.132 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 33.684 77.138 33.708 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 34.260 77.138 34.284 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 34.836 77.138 34.860 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 35.412 77.138 35.436 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 35.988 77.138 36.012 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 36.564 77.138 36.588 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[255] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 42.801 0.225 42.855 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 42.801 0.801 42.855 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 42.801 1.377 42.855 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 42.801 1.953 42.855 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 42.801 2.529 42.855 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 42.801 3.105 42.855 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 42.801 3.681 42.855 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 42.801 4.257 42.855 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 42.801 4.833 42.855 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 42.801 5.409 42.855 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 42.801 5.985 42.855 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 42.801 6.561 42.855 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 42.801 7.137 42.855 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 42.801 7.713 42.855 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 42.801 8.289 42.855 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 42.801 8.865 42.855 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 42.801 9.441 42.855 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 42.801 10.017 42.855 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 42.801 10.593 42.855 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 42.801 11.169 42.855 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 42.801 11.745 42.855 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 42.801 12.321 42.855 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 42.801 12.897 42.855 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 42.801 13.473 42.855 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 42.801 14.049 42.855 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 42.801 14.625 42.855 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 42.801 15.201 42.855 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 42.801 15.777 42.855 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 42.801 16.353 42.855 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 42.801 16.929 42.855 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 42.801 17.505 42.855 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 42.801 18.081 42.855 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 42.801 18.657 42.855 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 42.801 19.233 42.855 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 42.801 19.809 42.855 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 42.801 20.385 42.855 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 42.801 20.961 42.855 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 42.801 21.537 42.855 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 42.801 22.113 42.855 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 42.801 22.689 42.855 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 42.801 23.265 42.855 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 42.801 23.841 42.855 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 42.801 24.417 42.855 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 42.801 24.993 42.855 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 42.801 25.569 42.855 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 42.801 26.145 42.855 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 42.801 26.721 42.855 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 42.801 27.297 42.855 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 42.801 27.873 42.855 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 42.801 28.449 42.855 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 42.801 29.025 42.855 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 42.801 29.601 42.855 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 42.801 30.177 42.855 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 42.801 30.753 42.855 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 42.801 31.329 42.855 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 42.801 31.905 42.855 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 42.801 32.481 42.855 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 42.801 33.057 42.855 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 42.801 33.633 42.855 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 42.801 34.209 42.855 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 42.801 34.785 42.855 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 42.801 35.361 42.855 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 42.801 35.937 42.855 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 42.801 36.513 42.855 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 42.801 37.089 42.855 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 42.801 37.665 42.855 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 42.801 38.241 42.855 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 42.801 38.817 42.855 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 42.801 39.393 42.855 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 42.801 39.969 42.855 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 42.801 40.545 42.855 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 42.801 41.121 42.855 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 42.801 41.697 42.855 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 42.801 42.273 42.855 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 42.801 42.849 42.855 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 42.801 43.425 42.855 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 42.801 44.001 42.855 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 42.801 44.577 42.855 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 42.801 45.153 42.855 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 42.801 45.729 42.855 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 42.801 46.305 42.855 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 42.801 46.881 42.855 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 42.801 47.457 42.855 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 42.801 48.033 42.855 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 42.801 48.609 42.855 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 42.801 49.185 42.855 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 42.801 49.761 42.855 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 42.801 50.337 42.855 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 42.801 50.913 42.855 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 42.801 51.489 42.855 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 42.801 52.065 42.855 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 42.801 52.641 42.855 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 42.801 53.217 42.855 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 42.801 53.793 42.855 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 42.801 54.369 42.855 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 42.801 54.945 42.855 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 42.801 55.521 42.855 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 42.801 56.097 42.855 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 42.801 56.673 42.855 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 42.801 57.249 42.855 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 42.801 57.825 42.855 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 42.801 58.401 42.855 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 42.801 58.977 42.855 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 42.801 59.553 42.855 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 42.801 60.129 42.855 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 42.801 60.705 42.855 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 42.801 61.281 42.855 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 42.801 61.857 42.855 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 42.801 62.433 42.855 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 42.801 63.009 42.855 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 42.801 63.585 42.855 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 42.801 64.161 42.855 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 42.801 64.737 42.855 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 42.801 65.313 42.855 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 42.801 65.889 42.855 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 42.801 66.465 42.855 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 42.801 67.041 42.855 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 42.801 67.617 42.855 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 42.801 68.193 42.855 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 42.801 68.769 42.855 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 42.801 69.345 42.855 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 42.801 69.921 42.855 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 42.801 70.497 42.855 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 42.801 71.073 42.855 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 42.801 71.649 42.855 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 42.801 72.225 42.855 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 42.801 72.801 42.855 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 42.801 73.377 42.855 ; + END + END r0_rd_out[255] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.868 0.072 38.892 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 37.140 77.138 37.164 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 37.716 77.138 37.740 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 38.292 77.138 38.316 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.172 0.072 41.196 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 38.868 77.138 38.892 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 39.444 77.138 39.468 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 40.020 77.138 40.044 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 42.801 73.953 42.855 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 42.801 74.529 42.855 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 42.801 75.105 42.855 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 42.801 75.681 42.855 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 42.801 76.257 42.855 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + RECT 0.216 24.048 76.922 24.144 ; + RECT 0.216 24.816 76.922 24.912 ; + RECT 0.216 25.584 76.922 25.680 ; + RECT 0.216 26.352 76.922 26.448 ; + RECT 0.216 27.120 76.922 27.216 ; + RECT 0.216 27.888 76.922 27.984 ; + RECT 0.216 28.656 76.922 28.752 ; + RECT 0.216 29.424 76.922 29.520 ; + RECT 0.216 30.192 76.922 30.288 ; + RECT 0.216 30.960 76.922 31.056 ; + RECT 0.216 31.728 76.922 31.824 ; + RECT 0.216 32.496 76.922 32.592 ; + RECT 0.216 33.264 76.922 33.360 ; + RECT 0.216 34.032 76.922 34.128 ; + RECT 0.216 34.800 76.922 34.896 ; + RECT 0.216 35.568 76.922 35.664 ; + RECT 0.216 36.336 76.922 36.432 ; + RECT 0.216 37.104 76.922 37.200 ; + RECT 0.216 37.872 76.922 37.968 ; + RECT 0.216 38.640 76.922 38.736 ; + RECT 0.216 39.408 76.922 39.504 ; + RECT 0.216 40.176 76.922 40.272 ; + RECT 0.216 40.944 76.922 41.040 ; + RECT 0.216 41.712 76.922 41.808 ; + RECT 0.216 42.480 76.922 42.576 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + RECT 0.216 24.048 76.922 24.144 ; + RECT 0.216 24.816 76.922 24.912 ; + RECT 0.216 25.584 76.922 25.680 ; + RECT 0.216 26.352 76.922 26.448 ; + RECT 0.216 27.120 76.922 27.216 ; + RECT 0.216 27.888 76.922 27.984 ; + RECT 0.216 28.656 76.922 28.752 ; + RECT 0.216 29.424 76.922 29.520 ; + RECT 0.216 30.192 76.922 30.288 ; + RECT 0.216 30.960 76.922 31.056 ; + RECT 0.216 31.728 76.922 31.824 ; + RECT 0.216 32.496 76.922 32.592 ; + RECT 0.216 33.264 76.922 33.360 ; + RECT 0.216 34.032 76.922 34.128 ; + RECT 0.216 34.800 76.922 34.896 ; + RECT 0.216 35.568 76.922 35.664 ; + RECT 0.216 36.336 76.922 36.432 ; + RECT 0.216 37.104 76.922 37.200 ; + RECT 0.216 37.872 76.922 37.968 ; + RECT 0.216 38.640 76.922 38.736 ; + RECT 0.216 39.408 76.922 39.504 ; + RECT 0.216 40.176 76.922 40.272 ; + RECT 0.216 40.944 76.922 41.040 ; + RECT 0.216 41.712 76.922 41.808 ; + RECT 0.216 42.480 76.922 42.576 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 77.138 42.855 ; + LAYER M2 ; + RECT 0 0 77.138 42.855 ; + LAYER M3 ; + RECT 0 0 77.138 42.855 ; + LAYER M4 ; + RECT 0 0 77.138 42.855 ; + END +END fakeram_256x128_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_256x16_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_256x16_1r1w.lef new file mode 100644 index 0000000..7eb613e --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_256x16_1r1w.lef @@ -0,0 +1,4821 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_256x16_1r1w + FOREIGN fakeram_256x16_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 77.138 BY 24.106 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.276 77.138 0.300 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.612 77.138 0.636 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.948 77.138 0.972 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.284 77.138 1.308 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.620 77.138 1.644 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.956 77.138 1.980 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.292 77.138 2.316 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.628 77.138 2.652 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.964 77.138 2.988 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.300 77.138 3.324 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.636 77.138 3.660 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.972 77.138 3.996 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.308 77.138 4.332 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.644 77.138 4.668 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.980 77.138 5.004 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.316 77.138 5.340 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.652 77.138 5.676 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.988 77.138 6.012 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.324 77.138 6.348 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.660 77.138 6.684 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.996 77.138 7.020 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.332 77.138 7.356 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.668 77.138 7.692 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.004 77.138 8.028 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.340 77.138 8.364 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.676 77.138 8.700 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.012 77.138 9.036 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.348 77.138 9.372 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.684 77.138 9.708 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.020 77.138 10.044 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.356 77.138 10.380 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.692 77.138 10.716 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.028 77.138 11.052 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.364 77.138 11.388 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.700 77.138 11.724 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.036 77.138 12.060 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.372 77.138 12.396 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.708 77.138 12.732 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.044 77.138 13.068 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.380 77.138 13.404 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.716 77.138 13.740 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.052 77.138 14.076 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.388 77.138 14.412 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.724 77.138 14.748 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.060 77.138 15.084 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.396 77.138 15.420 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.732 77.138 15.756 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.068 77.138 16.092 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.404 77.138 16.428 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.740 77.138 16.764 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.076 77.138 17.100 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.412 77.138 17.436 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.748 77.138 17.772 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.084 77.138 18.108 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.420 77.138 18.444 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.756 77.138 18.780 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.092 77.138 19.116 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.428 77.138 19.452 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.764 77.138 19.788 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.100 77.138 20.124 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.436 77.138 20.460 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.772 77.138 20.796 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.108 77.138 21.132 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.444 77.138 21.468 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[255] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 24.052 0.225 24.106 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 24.052 0.801 24.106 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 24.052 1.377 24.106 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 24.052 1.953 24.106 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 24.052 2.529 24.106 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 24.052 3.105 24.106 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 24.052 3.681 24.106 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 24.052 4.257 24.106 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 24.052 4.833 24.106 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 24.052 5.409 24.106 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 24.052 5.985 24.106 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 24.052 6.561 24.106 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 24.052 7.137 24.106 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 24.052 7.713 24.106 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 24.052 8.289 24.106 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 24.052 8.865 24.106 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 24.052 9.441 24.106 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 24.052 10.017 24.106 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 24.052 10.593 24.106 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 24.052 11.169 24.106 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 24.052 11.745 24.106 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 24.052 12.321 24.106 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 24.052 12.897 24.106 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 24.052 13.473 24.106 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 24.052 14.049 24.106 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 24.052 14.625 24.106 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 24.052 15.201 24.106 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 24.052 15.777 24.106 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 24.052 16.353 24.106 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 24.052 16.929 24.106 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 24.052 17.505 24.106 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 24.052 18.081 24.106 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 24.052 18.657 24.106 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 24.052 19.233 24.106 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 24.052 19.809 24.106 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 24.052 20.385 24.106 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 24.052 20.961 24.106 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 24.052 21.537 24.106 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 24.052 22.113 24.106 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 24.052 22.689 24.106 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 24.052 23.265 24.106 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 24.052 23.841 24.106 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 24.052 24.417 24.106 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 24.052 24.993 24.106 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 24.052 25.569 24.106 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 24.052 26.145 24.106 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 24.052 26.721 24.106 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 24.052 27.297 24.106 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 24.052 27.873 24.106 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 24.052 28.449 24.106 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 24.052 29.025 24.106 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 24.052 29.601 24.106 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 24.052 30.177 24.106 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 24.052 30.753 24.106 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 24.052 31.329 24.106 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 24.052 31.905 24.106 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 24.052 32.481 24.106 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 24.052 33.057 24.106 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 24.052 33.633 24.106 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 24.052 34.209 24.106 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 24.052 34.785 24.106 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 24.052 35.361 24.106 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 24.052 35.937 24.106 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 24.052 36.513 24.106 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 24.052 37.089 24.106 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 24.052 37.665 24.106 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 24.052 38.241 24.106 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 24.052 38.817 24.106 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 24.052 39.393 24.106 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 24.052 39.969 24.106 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 24.052 40.545 24.106 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 24.052 41.121 24.106 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 24.052 41.697 24.106 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 24.052 42.273 24.106 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 24.052 42.849 24.106 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 24.052 43.425 24.106 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 24.052 44.001 24.106 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 24.052 44.577 24.106 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 24.052 45.153 24.106 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 24.052 45.729 24.106 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 24.052 46.305 24.106 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 24.052 46.881 24.106 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 24.052 47.457 24.106 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 24.052 48.033 24.106 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 24.052 48.609 24.106 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 24.052 49.185 24.106 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 24.052 49.761 24.106 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 24.052 50.337 24.106 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 24.052 50.913 24.106 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 24.052 51.489 24.106 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 24.052 52.065 24.106 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 24.052 52.641 24.106 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 24.052 53.217 24.106 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 24.052 53.793 24.106 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 24.052 54.369 24.106 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 24.052 54.945 24.106 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 24.052 55.521 24.106 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 24.052 56.097 24.106 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 24.052 56.673 24.106 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 24.052 57.249 24.106 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 24.052 57.825 24.106 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 24.052 58.401 24.106 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 24.052 58.977 24.106 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 24.052 59.553 24.106 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 24.052 60.129 24.106 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 24.052 60.705 24.106 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 24.052 61.281 24.106 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 24.052 61.857 24.106 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 24.052 62.433 24.106 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 24.052 63.009 24.106 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 24.052 63.585 24.106 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 24.052 64.161 24.106 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 24.052 64.737 24.106 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 24.052 65.313 24.106 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 24.052 65.889 24.106 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 24.052 66.465 24.106 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 24.052 67.041 24.106 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 24.052 67.617 24.106 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 24.052 68.193 24.106 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 24.052 68.769 24.106 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 24.052 69.345 24.106 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 24.052 69.921 24.106 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 24.052 70.497 24.106 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 24.052 71.073 24.106 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 24.052 71.649 24.106 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 24.052 72.225 24.106 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 24.052 72.801 24.106 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 24.052 73.377 24.106 ; + END + END r0_rd_out[255] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.780 77.138 21.804 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.116 77.138 22.140 ; + END + END w0_addr_in[3] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.452 77.138 22.476 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.788 77.138 22.812 ; + END + END r0_addr_in[3] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 24.052 73.953 24.106 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 24.052 74.529 24.106 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 24.052 75.105 24.106 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 24.052 75.681 24.106 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 24.052 76.257 24.106 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 77.138 24.106 ; + LAYER M2 ; + RECT 0 0 77.138 24.106 ; + LAYER M3 ; + RECT 0 0 77.138 24.106 ; + LAYER M4 ; + RECT 0 0 77.138 24.106 ; + END +END fakeram_256x16_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_256x32_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_256x32_1r1w.lef new file mode 100644 index 0000000..20b5bca --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_256x32_1r1w.lef @@ -0,0 +1,4847 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_256x32_1r1w + FOREIGN fakeram_256x32_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 77.138 BY 26.785 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.276 77.138 0.300 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.612 77.138 0.636 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.948 77.138 0.972 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.284 77.138 1.308 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.620 77.138 1.644 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.956 77.138 1.980 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.292 77.138 2.316 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.628 77.138 2.652 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.964 77.138 2.988 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.300 77.138 3.324 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.636 77.138 3.660 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.972 77.138 3.996 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.308 77.138 4.332 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.644 77.138 4.668 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.980 77.138 5.004 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.316 77.138 5.340 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.652 77.138 5.676 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.988 77.138 6.012 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.324 77.138 6.348 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.660 77.138 6.684 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.996 77.138 7.020 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.332 77.138 7.356 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.668 77.138 7.692 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.004 77.138 8.028 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.340 77.138 8.364 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.676 77.138 8.700 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.012 77.138 9.036 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.348 77.138 9.372 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.684 77.138 9.708 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.020 77.138 10.044 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.356 77.138 10.380 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.692 77.138 10.716 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.028 77.138 11.052 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.364 77.138 11.388 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.700 77.138 11.724 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.036 77.138 12.060 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.372 77.138 12.396 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.708 77.138 12.732 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.044 77.138 13.068 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.380 77.138 13.404 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.716 77.138 13.740 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.052 77.138 14.076 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.388 77.138 14.412 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.724 77.138 14.748 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.060 77.138 15.084 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.396 77.138 15.420 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.732 77.138 15.756 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.068 77.138 16.092 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.404 77.138 16.428 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.740 77.138 16.764 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.076 77.138 17.100 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.412 77.138 17.436 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.748 77.138 17.772 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.084 77.138 18.108 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.420 77.138 18.444 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.756 77.138 18.780 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.092 77.138 19.116 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.428 77.138 19.452 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.764 77.138 19.788 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.100 77.138 20.124 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.436 77.138 20.460 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.772 77.138 20.796 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.108 77.138 21.132 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.444 77.138 21.468 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[255] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 26.731 0.225 26.785 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 26.731 0.801 26.785 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 26.731 1.377 26.785 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 26.731 1.953 26.785 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 26.731 2.529 26.785 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 26.731 3.105 26.785 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 26.731 3.681 26.785 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 26.731 4.257 26.785 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 26.731 4.833 26.785 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 26.731 5.409 26.785 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 26.731 5.985 26.785 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 26.731 6.561 26.785 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 26.731 7.137 26.785 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 26.731 7.713 26.785 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 26.731 8.289 26.785 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 26.731 8.865 26.785 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 26.731 9.441 26.785 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 26.731 10.017 26.785 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 26.731 10.593 26.785 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 26.731 11.169 26.785 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 26.731 11.745 26.785 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 26.731 12.321 26.785 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 26.731 12.897 26.785 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 26.731 13.473 26.785 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 26.731 14.049 26.785 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 26.731 14.625 26.785 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 26.731 15.201 26.785 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 26.731 15.777 26.785 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 26.731 16.353 26.785 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 26.731 16.929 26.785 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 26.731 17.505 26.785 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 26.731 18.081 26.785 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 26.731 18.657 26.785 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 26.731 19.233 26.785 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 26.731 19.809 26.785 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 26.731 20.385 26.785 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 26.731 20.961 26.785 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 26.731 21.537 26.785 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 26.731 22.113 26.785 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 26.731 22.689 26.785 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 26.731 23.265 26.785 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 26.731 23.841 26.785 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 26.731 24.417 26.785 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 26.731 24.993 26.785 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 26.731 25.569 26.785 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 26.731 26.145 26.785 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 26.731 26.721 26.785 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 26.731 27.297 26.785 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 26.731 27.873 26.785 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 26.731 28.449 26.785 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 26.731 29.025 26.785 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 26.731 29.601 26.785 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 26.731 30.177 26.785 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 26.731 30.753 26.785 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 26.731 31.329 26.785 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 26.731 31.905 26.785 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 26.731 32.481 26.785 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 26.731 33.057 26.785 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 26.731 33.633 26.785 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 26.731 34.209 26.785 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 26.731 34.785 26.785 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 26.731 35.361 26.785 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 26.731 35.937 26.785 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 26.731 36.513 26.785 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 26.731 37.089 26.785 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 26.731 37.665 26.785 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 26.731 38.241 26.785 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 26.731 38.817 26.785 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 26.731 39.393 26.785 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 26.731 39.969 26.785 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 26.731 40.545 26.785 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 26.731 41.121 26.785 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 26.731 41.697 26.785 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 26.731 42.273 26.785 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 26.731 42.849 26.785 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 26.731 43.425 26.785 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 26.731 44.001 26.785 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 26.731 44.577 26.785 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 26.731 45.153 26.785 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 26.731 45.729 26.785 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 26.731 46.305 26.785 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 26.731 46.881 26.785 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 26.731 47.457 26.785 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 26.731 48.033 26.785 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 26.731 48.609 26.785 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 26.731 49.185 26.785 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 26.731 49.761 26.785 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 26.731 50.337 26.785 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 26.731 50.913 26.785 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 26.731 51.489 26.785 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 26.731 52.065 26.785 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 26.731 52.641 26.785 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 26.731 53.217 26.785 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 26.731 53.793 26.785 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 26.731 54.369 26.785 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 26.731 54.945 26.785 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 26.731 55.521 26.785 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 26.731 56.097 26.785 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 26.731 56.673 26.785 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 26.731 57.249 26.785 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 26.731 57.825 26.785 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 26.731 58.401 26.785 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 26.731 58.977 26.785 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 26.731 59.553 26.785 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 26.731 60.129 26.785 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 26.731 60.705 26.785 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 26.731 61.281 26.785 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 26.731 61.857 26.785 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 26.731 62.433 26.785 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 26.731 63.009 26.785 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 26.731 63.585 26.785 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 26.731 64.161 26.785 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 26.731 64.737 26.785 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 26.731 65.313 26.785 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 26.731 65.889 26.785 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 26.731 66.465 26.785 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 26.731 67.041 26.785 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 26.731 67.617 26.785 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 26.731 68.193 26.785 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 26.731 68.769 26.785 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 26.731 69.345 26.785 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 26.731 69.921 26.785 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 26.731 70.497 26.785 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 26.731 71.073 26.785 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 26.731 71.649 26.785 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 26.731 72.225 26.785 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 26.731 72.801 26.785 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 26.731 73.377 26.785 ; + END + END r0_rd_out[255] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.780 77.138 21.804 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.116 77.138 22.140 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.452 77.138 22.476 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.788 77.138 22.812 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 26.731 73.953 26.785 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 26.731 74.529 26.785 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 26.731 75.105 26.785 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 26.731 75.681 26.785 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 26.731 76.257 26.785 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + RECT 0.216 24.048 76.922 24.144 ; + RECT 0.216 24.816 76.922 24.912 ; + RECT 0.216 25.584 76.922 25.680 ; + RECT 0.216 26.352 76.922 26.448 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + RECT 0.216 24.048 76.922 24.144 ; + RECT 0.216 24.816 76.922 24.912 ; + RECT 0.216 25.584 76.922 25.680 ; + RECT 0.216 26.352 76.922 26.448 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 77.138 26.785 ; + LAYER M2 ; + RECT 0 0 77.138 26.785 ; + LAYER M3 ; + RECT 0 0 77.138 26.785 ; + LAYER M4 ; + RECT 0 0 77.138 26.785 ; + END +END fakeram_256x32_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_256x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_256x80_1r1w.lef new file mode 100644 index 0000000..877e412 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_256x80_1r1w.lef @@ -0,0 +1,4903 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_256x80_1r1w + FOREIGN fakeram_256x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 77.138 BY 34.820 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.276 0.072 24.300 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.236 0.072 25.260 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.716 0.072 25.740 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.676 0.072 26.700 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.156 0.072 27.180 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.116 0.072 28.140 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.596 0.072 28.620 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.556 0.072 29.580 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.036 0.072 30.060 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.276 77.138 0.300 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 0.756 77.138 0.780 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.236 77.138 1.260 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 1.716 77.138 1.740 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.196 77.138 2.220 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 2.676 77.138 2.700 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.156 77.138 3.180 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 3.636 77.138 3.660 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.116 77.138 4.140 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 4.596 77.138 4.620 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.076 77.138 5.100 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 5.556 77.138 5.580 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.036 77.138 6.060 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.516 77.138 6.540 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 6.996 77.138 7.020 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.476 77.138 7.500 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 7.956 77.138 7.980 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.436 77.138 8.460 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 8.916 77.138 8.940 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.396 77.138 9.420 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 9.876 77.138 9.900 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.356 77.138 10.380 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 10.836 77.138 10.860 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.316 77.138 11.340 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 11.796 77.138 11.820 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.276 77.138 12.300 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 12.756 77.138 12.780 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.236 77.138 13.260 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 13.716 77.138 13.740 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.196 77.138 14.220 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 14.676 77.138 14.700 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.156 77.138 15.180 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 15.636 77.138 15.660 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.116 77.138 16.140 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 16.596 77.138 16.620 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.076 77.138 17.100 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 17.556 77.138 17.580 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.036 77.138 18.060 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.516 77.138 18.540 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 18.996 77.138 19.020 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.476 77.138 19.500 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 19.956 77.138 19.980 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.436 77.138 20.460 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 20.916 77.138 20.940 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.396 77.138 21.420 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 21.876 77.138 21.900 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.356 77.138 22.380 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 22.836 77.138 22.860 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 23.316 77.138 23.340 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 23.796 77.138 23.820 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 24.276 77.138 24.300 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 24.756 77.138 24.780 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 25.236 77.138 25.260 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 25.716 77.138 25.740 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 26.196 77.138 26.220 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 26.676 77.138 26.700 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 27.156 77.138 27.180 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 27.636 77.138 27.660 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 28.116 77.138 28.140 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 28.596 77.138 28.620 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 29.076 77.138 29.100 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 29.556 77.138 29.580 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 30.036 77.138 30.060 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 30.516 77.138 30.540 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[255] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 34.766 0.225 34.820 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 34.766 0.801 34.820 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 34.766 1.377 34.820 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 34.766 1.953 34.820 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 34.766 2.529 34.820 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 34.766 3.105 34.820 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 34.766 3.681 34.820 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 34.766 4.257 34.820 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 34.766 4.833 34.820 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 34.766 5.409 34.820 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 34.766 5.985 34.820 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 34.766 6.561 34.820 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 34.766 7.137 34.820 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 34.766 7.713 34.820 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 34.766 8.289 34.820 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 34.766 8.865 34.820 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 34.766 9.441 34.820 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 34.766 10.017 34.820 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 34.766 10.593 34.820 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 34.766 11.169 34.820 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 34.766 11.745 34.820 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 34.766 12.321 34.820 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 34.766 12.897 34.820 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 34.766 13.473 34.820 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 34.766 14.049 34.820 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 34.766 14.625 34.820 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 34.766 15.201 34.820 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 34.766 15.777 34.820 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 34.766 16.353 34.820 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 34.766 16.929 34.820 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 34.766 17.505 34.820 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 34.766 18.081 34.820 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 34.766 18.657 34.820 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 34.766 19.233 34.820 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 34.766 19.809 34.820 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 34.766 20.385 34.820 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 34.766 20.961 34.820 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 34.766 21.537 34.820 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 34.766 22.113 34.820 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 34.766 22.689 34.820 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 34.766 23.265 34.820 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 34.766 23.841 34.820 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 34.766 24.417 34.820 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 34.766 24.993 34.820 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 34.766 25.569 34.820 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 34.766 26.145 34.820 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 34.766 26.721 34.820 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 34.766 27.297 34.820 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 34.766 27.873 34.820 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 34.766 28.449 34.820 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 34.766 29.025 34.820 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 34.766 29.601 34.820 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 34.766 30.177 34.820 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 34.766 30.753 34.820 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 34.766 31.329 34.820 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 34.766 31.905 34.820 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 34.766 32.481 34.820 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 34.766 33.057 34.820 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 34.766 33.633 34.820 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 34.766 34.209 34.820 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 34.766 34.785 34.820 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 34.766 35.361 34.820 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 34.766 35.937 34.820 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 34.766 36.513 34.820 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 34.766 37.089 34.820 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 34.766 37.665 34.820 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 34.766 38.241 34.820 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 34.766 38.817 34.820 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 34.766 39.393 34.820 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 34.766 39.969 34.820 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 34.766 40.545 34.820 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 34.766 41.121 34.820 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 34.766 41.697 34.820 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 34.766 42.273 34.820 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 34.766 42.849 34.820 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 34.766 43.425 34.820 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 34.766 44.001 34.820 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 34.766 44.577 34.820 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 34.766 45.153 34.820 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 34.766 45.729 34.820 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 34.766 46.305 34.820 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 34.766 46.881 34.820 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 34.766 47.457 34.820 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 34.766 48.033 34.820 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 34.766 48.609 34.820 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 34.766 49.185 34.820 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 34.766 49.761 34.820 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 34.766 50.337 34.820 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 34.766 50.913 34.820 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 34.766 51.489 34.820 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 34.766 52.065 34.820 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 34.766 52.641 34.820 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 34.766 53.217 34.820 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 34.766 53.793 34.820 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 34.766 54.369 34.820 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 34.766 54.945 34.820 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 34.766 55.521 34.820 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 34.766 56.097 34.820 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 34.766 56.673 34.820 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 34.766 57.249 34.820 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 34.766 57.825 34.820 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 34.766 58.401 34.820 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 34.766 58.977 34.820 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 34.766 59.553 34.820 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 34.766 60.129 34.820 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 34.766 60.705 34.820 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 34.766 61.281 34.820 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 34.766 61.857 34.820 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 34.766 62.433 34.820 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 34.766 63.009 34.820 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 34.766 63.585 34.820 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 34.766 64.161 34.820 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 34.766 64.737 34.820 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 34.766 65.313 34.820 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 34.766 65.889 34.820 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 34.766 66.465 34.820 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 34.766 67.041 34.820 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 34.766 67.617 34.820 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 34.766 68.193 34.820 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 34.766 68.769 34.820 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 34.766 69.345 34.820 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 34.766 69.921 34.820 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 34.766 70.497 34.820 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 34.766 71.073 34.820 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 34.766 71.649 34.820 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 34.766 72.225 34.820 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 34.766 72.801 34.820 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 34.766 73.377 34.820 ; + END + END r0_rd_out[255] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.996 0.072 31.020 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.476 0.072 31.500 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.436 0.072 32.460 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 30.996 77.138 31.020 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 31.476 77.138 31.500 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 31.956 77.138 31.980 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.916 0.072 32.940 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.876 0.072 33.900 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.356 0.072 34.380 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 32.436 77.138 32.460 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 32.916 77.138 32.940 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 77.066 33.396 77.138 33.420 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 34.766 73.953 34.820 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 34.766 74.529 34.820 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 34.766 75.105 34.820 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 34.766 75.681 34.820 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 34.766 76.257 34.820 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + RECT 0.216 24.048 76.922 24.144 ; + RECT 0.216 24.816 76.922 24.912 ; + RECT 0.216 25.584 76.922 25.680 ; + RECT 0.216 26.352 76.922 26.448 ; + RECT 0.216 27.120 76.922 27.216 ; + RECT 0.216 27.888 76.922 27.984 ; + RECT 0.216 28.656 76.922 28.752 ; + RECT 0.216 29.424 76.922 29.520 ; + RECT 0.216 30.192 76.922 30.288 ; + RECT 0.216 30.960 76.922 31.056 ; + RECT 0.216 31.728 76.922 31.824 ; + RECT 0.216 32.496 76.922 32.592 ; + RECT 0.216 33.264 76.922 33.360 ; + RECT 0.216 34.032 76.922 34.128 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 76.922 0.336 ; + RECT 0.216 1.008 76.922 1.104 ; + RECT 0.216 1.776 76.922 1.872 ; + RECT 0.216 2.544 76.922 2.640 ; + RECT 0.216 3.312 76.922 3.408 ; + RECT 0.216 4.080 76.922 4.176 ; + RECT 0.216 4.848 76.922 4.944 ; + RECT 0.216 5.616 76.922 5.712 ; + RECT 0.216 6.384 76.922 6.480 ; + RECT 0.216 7.152 76.922 7.248 ; + RECT 0.216 7.920 76.922 8.016 ; + RECT 0.216 8.688 76.922 8.784 ; + RECT 0.216 9.456 76.922 9.552 ; + RECT 0.216 10.224 76.922 10.320 ; + RECT 0.216 10.992 76.922 11.088 ; + RECT 0.216 11.760 76.922 11.856 ; + RECT 0.216 12.528 76.922 12.624 ; + RECT 0.216 13.296 76.922 13.392 ; + RECT 0.216 14.064 76.922 14.160 ; + RECT 0.216 14.832 76.922 14.928 ; + RECT 0.216 15.600 76.922 15.696 ; + RECT 0.216 16.368 76.922 16.464 ; + RECT 0.216 17.136 76.922 17.232 ; + RECT 0.216 17.904 76.922 18.000 ; + RECT 0.216 18.672 76.922 18.768 ; + RECT 0.216 19.440 76.922 19.536 ; + RECT 0.216 20.208 76.922 20.304 ; + RECT 0.216 20.976 76.922 21.072 ; + RECT 0.216 21.744 76.922 21.840 ; + RECT 0.216 22.512 76.922 22.608 ; + RECT 0.216 23.280 76.922 23.376 ; + RECT 0.216 24.048 76.922 24.144 ; + RECT 0.216 24.816 76.922 24.912 ; + RECT 0.216 25.584 76.922 25.680 ; + RECT 0.216 26.352 76.922 26.448 ; + RECT 0.216 27.120 76.922 27.216 ; + RECT 0.216 27.888 76.922 27.984 ; + RECT 0.216 28.656 76.922 28.752 ; + RECT 0.216 29.424 76.922 29.520 ; + RECT 0.216 30.192 76.922 30.288 ; + RECT 0.216 30.960 76.922 31.056 ; + RECT 0.216 31.728 76.922 31.824 ; + RECT 0.216 32.496 76.922 32.592 ; + RECT 0.216 33.264 76.922 33.360 ; + RECT 0.216 34.032 76.922 34.128 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 77.138 34.820 ; + LAYER M2 ; + RECT 0 0 77.138 34.820 ; + LAYER M3 ; + RECT 0 0 77.138 34.820 ; + LAYER M4 ; + RECT 0 0 77.138 34.820 ; + END +END fakeram_256x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_272x16_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_272x16_1r1w.lef new file mode 100644 index 0000000..6b61311 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_272x16_1r1w.lef @@ -0,0 +1,5113 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_272x16_1r1w + FOREIGN fakeram_272x16_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 81.960 BY 25.445 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 0.276 81.960 0.300 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 0.612 81.960 0.636 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 0.948 81.960 0.972 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 1.284 81.960 1.308 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 1.620 81.960 1.644 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 1.956 81.960 1.980 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 2.292 81.960 2.316 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 2.628 81.960 2.652 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 2.964 81.960 2.988 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 3.300 81.960 3.324 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 3.636 81.960 3.660 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 3.972 81.960 3.996 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 4.308 81.960 4.332 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 4.644 81.960 4.668 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 4.980 81.960 5.004 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 5.316 81.960 5.340 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 5.652 81.960 5.676 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 5.988 81.960 6.012 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 6.324 81.960 6.348 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 6.660 81.960 6.684 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 6.996 81.960 7.020 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 7.332 81.960 7.356 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 7.668 81.960 7.692 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 8.004 81.960 8.028 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 8.340 81.960 8.364 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 8.676 81.960 8.700 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 9.012 81.960 9.036 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 9.348 81.960 9.372 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 9.684 81.960 9.708 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 10.020 81.960 10.044 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 10.356 81.960 10.380 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 10.692 81.960 10.716 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 11.028 81.960 11.052 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 11.364 81.960 11.388 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 11.700 81.960 11.724 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 12.036 81.960 12.060 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 12.372 81.960 12.396 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 12.708 81.960 12.732 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 13.044 81.960 13.068 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 13.380 81.960 13.404 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 13.716 81.960 13.740 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 14.052 81.960 14.076 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 14.388 81.960 14.412 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 14.724 81.960 14.748 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 15.060 81.960 15.084 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 15.396 81.960 15.420 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 15.732 81.960 15.756 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 16.068 81.960 16.092 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 16.404 81.960 16.428 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 16.740 81.960 16.764 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 17.076 81.960 17.100 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 17.412 81.960 17.436 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 17.748 81.960 17.772 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 18.084 81.960 18.108 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 18.420 81.960 18.444 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 18.756 81.960 18.780 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 19.092 81.960 19.116 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 19.428 81.960 19.452 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 19.764 81.960 19.788 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 20.100 81.960 20.124 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 20.436 81.960 20.460 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 20.772 81.960 20.796 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 21.108 81.960 21.132 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 21.444 81.960 21.468 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 21.780 81.960 21.804 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 22.116 81.960 22.140 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 22.452 81.960 22.476 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 22.788 81.960 22.812 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[271] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 25.391 0.225 25.445 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 25.391 0.801 25.445 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 25.391 1.377 25.445 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 25.391 1.953 25.445 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 25.391 2.529 25.445 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 25.391 3.105 25.445 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 25.391 3.681 25.445 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 25.391 4.257 25.445 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 25.391 4.833 25.445 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 25.391 5.409 25.445 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 25.391 5.985 25.445 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 25.391 6.561 25.445 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 25.391 7.137 25.445 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 25.391 7.713 25.445 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 25.391 8.289 25.445 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 25.391 8.865 25.445 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 25.391 9.441 25.445 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 25.391 10.017 25.445 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 25.391 10.593 25.445 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 25.391 11.169 25.445 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 25.391 11.745 25.445 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 25.391 12.321 25.445 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 25.391 12.897 25.445 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 25.391 13.473 25.445 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 25.391 14.049 25.445 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 25.391 14.625 25.445 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 25.391 15.201 25.445 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 25.391 15.777 25.445 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 25.391 16.353 25.445 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 25.391 16.929 25.445 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 25.391 17.505 25.445 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 25.391 18.081 25.445 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 25.391 18.657 25.445 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 25.391 19.233 25.445 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 25.391 19.809 25.445 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 25.391 20.385 25.445 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 25.391 20.961 25.445 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 25.391 21.537 25.445 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 25.391 22.113 25.445 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 25.391 22.689 25.445 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 25.391 23.265 25.445 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 25.391 23.841 25.445 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 25.391 24.417 25.445 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 25.391 24.993 25.445 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 25.391 25.569 25.445 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 25.391 26.145 25.445 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 25.391 26.721 25.445 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 25.391 27.297 25.445 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 25.391 27.873 25.445 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 25.391 28.449 25.445 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 25.391 29.025 25.445 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 25.391 29.601 25.445 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 25.391 30.177 25.445 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 25.391 30.753 25.445 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 25.391 31.329 25.445 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 25.391 31.905 25.445 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 25.391 32.481 25.445 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 25.391 33.057 25.445 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 25.391 33.633 25.445 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 25.391 34.209 25.445 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 25.391 34.785 25.445 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 25.391 35.361 25.445 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 25.391 35.937 25.445 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 25.391 36.513 25.445 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 25.391 37.089 25.445 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 25.391 37.665 25.445 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 25.391 38.241 25.445 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 25.391 38.817 25.445 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 25.391 39.393 25.445 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 25.391 39.969 25.445 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 25.391 40.545 25.445 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 25.391 41.121 25.445 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 25.391 41.697 25.445 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 25.391 42.273 25.445 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 25.391 42.849 25.445 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 25.391 43.425 25.445 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 25.391 44.001 25.445 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 25.391 44.577 25.445 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 25.391 45.153 25.445 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 25.391 45.729 25.445 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 25.391 46.305 25.445 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 25.391 46.881 25.445 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 25.391 47.457 25.445 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 25.391 48.033 25.445 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 25.391 48.609 25.445 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 25.391 49.185 25.445 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 25.391 49.761 25.445 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 25.391 50.337 25.445 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 25.391 50.913 25.445 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 25.391 51.489 25.445 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 25.391 52.065 25.445 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 25.391 52.641 25.445 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 25.391 53.217 25.445 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 25.391 53.793 25.445 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 25.391 54.369 25.445 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 25.391 54.945 25.445 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 25.391 55.521 25.445 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 25.391 56.097 25.445 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 25.391 56.673 25.445 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 25.391 57.249 25.445 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 25.391 57.825 25.445 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 25.391 58.401 25.445 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 25.391 58.977 25.445 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 25.391 59.553 25.445 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 25.391 60.129 25.445 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 25.391 60.705 25.445 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 25.391 61.281 25.445 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 25.391 61.857 25.445 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 25.391 62.433 25.445 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 25.391 63.009 25.445 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 25.391 63.585 25.445 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 25.391 64.161 25.445 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 25.391 64.737 25.445 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 25.391 65.313 25.445 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 25.391 65.889 25.445 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 25.391 66.465 25.445 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 25.391 67.041 25.445 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 25.391 67.617 25.445 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 25.391 68.193 25.445 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 25.391 68.769 25.445 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 25.391 69.345 25.445 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 25.391 69.921 25.445 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 25.391 70.497 25.445 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 25.391 71.073 25.445 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 25.391 71.649 25.445 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 25.391 72.225 25.445 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 25.391 72.801 25.445 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 25.391 73.377 25.445 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 25.391 73.953 25.445 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 25.391 74.529 25.445 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 25.391 75.105 25.445 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 25.391 75.681 25.445 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 25.391 76.257 25.445 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 25.391 76.833 25.445 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 25.391 77.409 25.445 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 25.391 77.985 25.445 ; + END + END r0_rd_out[271] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 23.124 81.960 23.148 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 23.460 81.960 23.484 ; + END + END w0_addr_in[3] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.132 0.072 24.156 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 23.796 81.960 23.820 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 24.132 81.960 24.156 ; + END + END r0_addr_in[3] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 25.391 78.561 25.445 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 25.391 79.137 25.445 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 25.391 79.713 25.445 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 25.391 80.289 25.445 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 25.391 80.865 25.445 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 81.744 0.336 ; + RECT 0.216 1.008 81.744 1.104 ; + RECT 0.216 1.776 81.744 1.872 ; + RECT 0.216 2.544 81.744 2.640 ; + RECT 0.216 3.312 81.744 3.408 ; + RECT 0.216 4.080 81.744 4.176 ; + RECT 0.216 4.848 81.744 4.944 ; + RECT 0.216 5.616 81.744 5.712 ; + RECT 0.216 6.384 81.744 6.480 ; + RECT 0.216 7.152 81.744 7.248 ; + RECT 0.216 7.920 81.744 8.016 ; + RECT 0.216 8.688 81.744 8.784 ; + RECT 0.216 9.456 81.744 9.552 ; + RECT 0.216 10.224 81.744 10.320 ; + RECT 0.216 10.992 81.744 11.088 ; + RECT 0.216 11.760 81.744 11.856 ; + RECT 0.216 12.528 81.744 12.624 ; + RECT 0.216 13.296 81.744 13.392 ; + RECT 0.216 14.064 81.744 14.160 ; + RECT 0.216 14.832 81.744 14.928 ; + RECT 0.216 15.600 81.744 15.696 ; + RECT 0.216 16.368 81.744 16.464 ; + RECT 0.216 17.136 81.744 17.232 ; + RECT 0.216 17.904 81.744 18.000 ; + RECT 0.216 18.672 81.744 18.768 ; + RECT 0.216 19.440 81.744 19.536 ; + RECT 0.216 20.208 81.744 20.304 ; + RECT 0.216 20.976 81.744 21.072 ; + RECT 0.216 21.744 81.744 21.840 ; + RECT 0.216 22.512 81.744 22.608 ; + RECT 0.216 23.280 81.744 23.376 ; + RECT 0.216 24.048 81.744 24.144 ; + RECT 0.216 24.816 81.744 24.912 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 81.744 0.336 ; + RECT 0.216 1.008 81.744 1.104 ; + RECT 0.216 1.776 81.744 1.872 ; + RECT 0.216 2.544 81.744 2.640 ; + RECT 0.216 3.312 81.744 3.408 ; + RECT 0.216 4.080 81.744 4.176 ; + RECT 0.216 4.848 81.744 4.944 ; + RECT 0.216 5.616 81.744 5.712 ; + RECT 0.216 6.384 81.744 6.480 ; + RECT 0.216 7.152 81.744 7.248 ; + RECT 0.216 7.920 81.744 8.016 ; + RECT 0.216 8.688 81.744 8.784 ; + RECT 0.216 9.456 81.744 9.552 ; + RECT 0.216 10.224 81.744 10.320 ; + RECT 0.216 10.992 81.744 11.088 ; + RECT 0.216 11.760 81.744 11.856 ; + RECT 0.216 12.528 81.744 12.624 ; + RECT 0.216 13.296 81.744 13.392 ; + RECT 0.216 14.064 81.744 14.160 ; + RECT 0.216 14.832 81.744 14.928 ; + RECT 0.216 15.600 81.744 15.696 ; + RECT 0.216 16.368 81.744 16.464 ; + RECT 0.216 17.136 81.744 17.232 ; + RECT 0.216 17.904 81.744 18.000 ; + RECT 0.216 18.672 81.744 18.768 ; + RECT 0.216 19.440 81.744 19.536 ; + RECT 0.216 20.208 81.744 20.304 ; + RECT 0.216 20.976 81.744 21.072 ; + RECT 0.216 21.744 81.744 21.840 ; + RECT 0.216 22.512 81.744 22.608 ; + RECT 0.216 23.280 81.744 23.376 ; + RECT 0.216 24.048 81.744 24.144 ; + RECT 0.216 24.816 81.744 24.912 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 81.960 25.445 ; + LAYER M2 ; + RECT 0 0 81.960 25.445 ; + LAYER M3 ; + RECT 0 0 81.960 25.445 ; + LAYER M4 ; + RECT 0 0 81.960 25.445 ; + END +END fakeram_272x16_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_272x32_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_272x32_1r1w.lef new file mode 100644 index 0000000..c3fdc56 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_272x32_1r1w.lef @@ -0,0 +1,5139 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_272x32_1r1w + FOREIGN fakeram_272x32_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 81.960 BY 28.124 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 0.276 81.960 0.300 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 0.612 81.960 0.636 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 0.948 81.960 0.972 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 1.284 81.960 1.308 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 1.620 81.960 1.644 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 1.956 81.960 1.980 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 2.292 81.960 2.316 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 2.628 81.960 2.652 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 2.964 81.960 2.988 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 3.300 81.960 3.324 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 3.636 81.960 3.660 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 3.972 81.960 3.996 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 4.308 81.960 4.332 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 4.644 81.960 4.668 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 4.980 81.960 5.004 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 5.316 81.960 5.340 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 5.652 81.960 5.676 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 5.988 81.960 6.012 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 6.324 81.960 6.348 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 6.660 81.960 6.684 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 6.996 81.960 7.020 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 7.332 81.960 7.356 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 7.668 81.960 7.692 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 8.004 81.960 8.028 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 8.340 81.960 8.364 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 8.676 81.960 8.700 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 9.012 81.960 9.036 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 9.348 81.960 9.372 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 9.684 81.960 9.708 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 10.020 81.960 10.044 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 10.356 81.960 10.380 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 10.692 81.960 10.716 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 11.028 81.960 11.052 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 11.364 81.960 11.388 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 11.700 81.960 11.724 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 12.036 81.960 12.060 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 12.372 81.960 12.396 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 12.708 81.960 12.732 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 13.044 81.960 13.068 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 13.380 81.960 13.404 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 13.716 81.960 13.740 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 14.052 81.960 14.076 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 14.388 81.960 14.412 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 14.724 81.960 14.748 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 15.060 81.960 15.084 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 15.396 81.960 15.420 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 15.732 81.960 15.756 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 16.068 81.960 16.092 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 16.404 81.960 16.428 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 16.740 81.960 16.764 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 17.076 81.960 17.100 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 17.412 81.960 17.436 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 17.748 81.960 17.772 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 18.084 81.960 18.108 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 18.420 81.960 18.444 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 18.756 81.960 18.780 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 19.092 81.960 19.116 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 19.428 81.960 19.452 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 19.764 81.960 19.788 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 20.100 81.960 20.124 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 20.436 81.960 20.460 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 20.772 81.960 20.796 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 21.108 81.960 21.132 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 21.444 81.960 21.468 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 21.780 81.960 21.804 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 22.116 81.960 22.140 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 22.452 81.960 22.476 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 22.788 81.960 22.812 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[271] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 28.070 0.225 28.124 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 28.070 0.801 28.124 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 28.070 1.377 28.124 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 28.070 1.953 28.124 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 28.070 2.529 28.124 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 28.070 3.105 28.124 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 28.070 3.681 28.124 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 28.070 4.257 28.124 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 28.070 4.833 28.124 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 28.070 5.409 28.124 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 28.070 5.985 28.124 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 28.070 6.561 28.124 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 28.070 7.137 28.124 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 28.070 7.713 28.124 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 28.070 8.289 28.124 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 28.070 8.865 28.124 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 28.070 9.441 28.124 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 28.070 10.017 28.124 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 28.070 10.593 28.124 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 28.070 11.169 28.124 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 28.070 11.745 28.124 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 28.070 12.321 28.124 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 28.070 12.897 28.124 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 28.070 13.473 28.124 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 28.070 14.049 28.124 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 28.070 14.625 28.124 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 28.070 15.201 28.124 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 28.070 15.777 28.124 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 28.070 16.353 28.124 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 28.070 16.929 28.124 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 28.070 17.505 28.124 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 28.070 18.081 28.124 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 28.070 18.657 28.124 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 28.070 19.233 28.124 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 28.070 19.809 28.124 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 28.070 20.385 28.124 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 28.070 20.961 28.124 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 28.070 21.537 28.124 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 28.070 22.113 28.124 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 28.070 22.689 28.124 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 28.070 23.265 28.124 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 28.070 23.841 28.124 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 28.070 24.417 28.124 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 28.070 24.993 28.124 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 28.070 25.569 28.124 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 28.070 26.145 28.124 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 28.070 26.721 28.124 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 28.070 27.297 28.124 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 28.070 27.873 28.124 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 28.070 28.449 28.124 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 28.070 29.025 28.124 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 28.070 29.601 28.124 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 28.070 30.177 28.124 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 28.070 30.753 28.124 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 28.070 31.329 28.124 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 28.070 31.905 28.124 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 28.070 32.481 28.124 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 28.070 33.057 28.124 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 28.070 33.633 28.124 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 28.070 34.209 28.124 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 28.070 34.785 28.124 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 28.070 35.361 28.124 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 28.070 35.937 28.124 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 28.070 36.513 28.124 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 28.070 37.089 28.124 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 28.070 37.665 28.124 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 28.070 38.241 28.124 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 28.070 38.817 28.124 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 28.070 39.393 28.124 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 28.070 39.969 28.124 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 28.070 40.545 28.124 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 28.070 41.121 28.124 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 28.070 41.697 28.124 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 28.070 42.273 28.124 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 28.070 42.849 28.124 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 28.070 43.425 28.124 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 28.070 44.001 28.124 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 28.070 44.577 28.124 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 28.070 45.153 28.124 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 28.070 45.729 28.124 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 28.070 46.305 28.124 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 28.070 46.881 28.124 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 28.070 47.457 28.124 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 28.070 48.033 28.124 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 28.070 48.609 28.124 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 28.070 49.185 28.124 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 28.070 49.761 28.124 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 28.070 50.337 28.124 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 28.070 50.913 28.124 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 28.070 51.489 28.124 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 28.070 52.065 28.124 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 28.070 52.641 28.124 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 28.070 53.217 28.124 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 28.070 53.793 28.124 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 28.070 54.369 28.124 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 28.070 54.945 28.124 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 28.070 55.521 28.124 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 28.070 56.097 28.124 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 28.070 56.673 28.124 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 28.070 57.249 28.124 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 28.070 57.825 28.124 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 28.070 58.401 28.124 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 28.070 58.977 28.124 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 28.070 59.553 28.124 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 28.070 60.129 28.124 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 28.070 60.705 28.124 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 28.070 61.281 28.124 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 28.070 61.857 28.124 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 28.070 62.433 28.124 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 28.070 63.009 28.124 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 28.070 63.585 28.124 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 28.070 64.161 28.124 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 28.070 64.737 28.124 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 28.070 65.313 28.124 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 28.070 65.889 28.124 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 28.070 66.465 28.124 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 28.070 67.041 28.124 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 28.070 67.617 28.124 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 28.070 68.193 28.124 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 28.070 68.769 28.124 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 28.070 69.345 28.124 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 28.070 69.921 28.124 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 28.070 70.497 28.124 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 28.070 71.073 28.124 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 28.070 71.649 28.124 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 28.070 72.225 28.124 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 28.070 72.801 28.124 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 28.070 73.377 28.124 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 28.070 73.953 28.124 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 28.070 74.529 28.124 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 28.070 75.105 28.124 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 28.070 75.681 28.124 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 28.070 76.257 28.124 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 28.070 76.833 28.124 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 28.070 77.409 28.124 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 28.070 77.985 28.124 ; + END + END r0_rd_out[271] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 23.124 81.960 23.148 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 23.460 81.960 23.484 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.132 0.072 24.156 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.804 0.072 24.828 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 23.796 81.960 23.820 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 81.888 24.132 81.960 24.156 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 28.070 78.561 28.124 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 28.070 79.137 28.124 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 28.070 79.713 28.124 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 28.070 80.289 28.124 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 28.070 80.865 28.124 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 81.744 0.336 ; + RECT 0.216 1.008 81.744 1.104 ; + RECT 0.216 1.776 81.744 1.872 ; + RECT 0.216 2.544 81.744 2.640 ; + RECT 0.216 3.312 81.744 3.408 ; + RECT 0.216 4.080 81.744 4.176 ; + RECT 0.216 4.848 81.744 4.944 ; + RECT 0.216 5.616 81.744 5.712 ; + RECT 0.216 6.384 81.744 6.480 ; + RECT 0.216 7.152 81.744 7.248 ; + RECT 0.216 7.920 81.744 8.016 ; + RECT 0.216 8.688 81.744 8.784 ; + RECT 0.216 9.456 81.744 9.552 ; + RECT 0.216 10.224 81.744 10.320 ; + RECT 0.216 10.992 81.744 11.088 ; + RECT 0.216 11.760 81.744 11.856 ; + RECT 0.216 12.528 81.744 12.624 ; + RECT 0.216 13.296 81.744 13.392 ; + RECT 0.216 14.064 81.744 14.160 ; + RECT 0.216 14.832 81.744 14.928 ; + RECT 0.216 15.600 81.744 15.696 ; + RECT 0.216 16.368 81.744 16.464 ; + RECT 0.216 17.136 81.744 17.232 ; + RECT 0.216 17.904 81.744 18.000 ; + RECT 0.216 18.672 81.744 18.768 ; + RECT 0.216 19.440 81.744 19.536 ; + RECT 0.216 20.208 81.744 20.304 ; + RECT 0.216 20.976 81.744 21.072 ; + RECT 0.216 21.744 81.744 21.840 ; + RECT 0.216 22.512 81.744 22.608 ; + RECT 0.216 23.280 81.744 23.376 ; + RECT 0.216 24.048 81.744 24.144 ; + RECT 0.216 24.816 81.744 24.912 ; + RECT 0.216 25.584 81.744 25.680 ; + RECT 0.216 26.352 81.744 26.448 ; + RECT 0.216 27.120 81.744 27.216 ; + RECT 0.216 27.888 81.744 27.984 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 81.744 0.336 ; + RECT 0.216 1.008 81.744 1.104 ; + RECT 0.216 1.776 81.744 1.872 ; + RECT 0.216 2.544 81.744 2.640 ; + RECT 0.216 3.312 81.744 3.408 ; + RECT 0.216 4.080 81.744 4.176 ; + RECT 0.216 4.848 81.744 4.944 ; + RECT 0.216 5.616 81.744 5.712 ; + RECT 0.216 6.384 81.744 6.480 ; + RECT 0.216 7.152 81.744 7.248 ; + RECT 0.216 7.920 81.744 8.016 ; + RECT 0.216 8.688 81.744 8.784 ; + RECT 0.216 9.456 81.744 9.552 ; + RECT 0.216 10.224 81.744 10.320 ; + RECT 0.216 10.992 81.744 11.088 ; + RECT 0.216 11.760 81.744 11.856 ; + RECT 0.216 12.528 81.744 12.624 ; + RECT 0.216 13.296 81.744 13.392 ; + RECT 0.216 14.064 81.744 14.160 ; + RECT 0.216 14.832 81.744 14.928 ; + RECT 0.216 15.600 81.744 15.696 ; + RECT 0.216 16.368 81.744 16.464 ; + RECT 0.216 17.136 81.744 17.232 ; + RECT 0.216 17.904 81.744 18.000 ; + RECT 0.216 18.672 81.744 18.768 ; + RECT 0.216 19.440 81.744 19.536 ; + RECT 0.216 20.208 81.744 20.304 ; + RECT 0.216 20.976 81.744 21.072 ; + RECT 0.216 21.744 81.744 21.840 ; + RECT 0.216 22.512 81.744 22.608 ; + RECT 0.216 23.280 81.744 23.376 ; + RECT 0.216 24.048 81.744 24.144 ; + RECT 0.216 24.816 81.744 24.912 ; + RECT 0.216 25.584 81.744 25.680 ; + RECT 0.216 26.352 81.744 26.448 ; + RECT 0.216 27.120 81.744 27.216 ; + RECT 0.216 27.888 81.744 27.984 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 81.960 28.124 ; + LAYER M2 ; + RECT 0 0 81.960 28.124 ; + LAYER M3 ; + RECT 0 0 81.960 28.124 ; + LAYER M4 ; + RECT 0 0 81.960 28.124 ; + END +END fakeram_272x32_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_288x20_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_288x20_1r1w.lef new file mode 100644 index 0000000..41e9643 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_288x20_1r1w.lef @@ -0,0 +1,5425 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_288x20_1r1w + FOREIGN fakeram_288x20_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 86.781 BY 27.454 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.132 0.072 24.156 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.276 86.781 0.300 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.612 86.781 0.636 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.948 86.781 0.972 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.284 86.781 1.308 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.620 86.781 1.644 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.956 86.781 1.980 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.292 86.781 2.316 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.628 86.781 2.652 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.964 86.781 2.988 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.300 86.781 3.324 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.636 86.781 3.660 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.972 86.781 3.996 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.308 86.781 4.332 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.644 86.781 4.668 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.980 86.781 5.004 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.316 86.781 5.340 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.652 86.781 5.676 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.988 86.781 6.012 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.324 86.781 6.348 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.660 86.781 6.684 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.996 86.781 7.020 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.332 86.781 7.356 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.668 86.781 7.692 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.004 86.781 8.028 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.340 86.781 8.364 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.676 86.781 8.700 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.012 86.781 9.036 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.348 86.781 9.372 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.684 86.781 9.708 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.020 86.781 10.044 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.356 86.781 10.380 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.692 86.781 10.716 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.028 86.781 11.052 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.364 86.781 11.388 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.700 86.781 11.724 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.036 86.781 12.060 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.372 86.781 12.396 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.708 86.781 12.732 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.044 86.781 13.068 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.380 86.781 13.404 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.716 86.781 13.740 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.052 86.781 14.076 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.388 86.781 14.412 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.724 86.781 14.748 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.060 86.781 15.084 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.396 86.781 15.420 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.732 86.781 15.756 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.068 86.781 16.092 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.404 86.781 16.428 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.740 86.781 16.764 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.076 86.781 17.100 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.412 86.781 17.436 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.748 86.781 17.772 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.084 86.781 18.108 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.420 86.781 18.444 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.756 86.781 18.780 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.092 86.781 19.116 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.428 86.781 19.452 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.764 86.781 19.788 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.100 86.781 20.124 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.436 86.781 20.460 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.772 86.781 20.796 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.108 86.781 21.132 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.444 86.781 21.468 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.780 86.781 21.804 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.116 86.781 22.140 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.452 86.781 22.476 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.788 86.781 22.812 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.124 86.781 23.148 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.460 86.781 23.484 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.796 86.781 23.820 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.132 86.781 24.156 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[287] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 27.400 0.225 27.454 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 27.400 0.801 27.454 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 27.400 1.377 27.454 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 27.400 1.953 27.454 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 27.400 2.529 27.454 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 27.400 3.105 27.454 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 27.400 3.681 27.454 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 27.400 4.257 27.454 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 27.400 4.833 27.454 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 27.400 5.409 27.454 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 27.400 5.985 27.454 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 27.400 6.561 27.454 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 27.400 7.137 27.454 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 27.400 7.713 27.454 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 27.400 8.289 27.454 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 27.400 8.865 27.454 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 27.400 9.441 27.454 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 27.400 10.017 27.454 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 27.400 10.593 27.454 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 27.400 11.169 27.454 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 27.400 11.745 27.454 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 27.400 12.321 27.454 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 27.400 12.897 27.454 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 27.400 13.473 27.454 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 27.400 14.049 27.454 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 27.400 14.625 27.454 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 27.400 15.201 27.454 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 27.400 15.777 27.454 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 27.400 16.353 27.454 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 27.400 16.929 27.454 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 27.400 17.505 27.454 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 27.400 18.081 27.454 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 27.400 18.657 27.454 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 27.400 19.233 27.454 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 27.400 19.809 27.454 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 27.400 20.385 27.454 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 27.400 20.961 27.454 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 27.400 21.537 27.454 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 27.400 22.113 27.454 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 27.400 22.689 27.454 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 27.400 23.265 27.454 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 27.400 23.841 27.454 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 27.400 24.417 27.454 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 27.400 24.993 27.454 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 27.400 25.569 27.454 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 27.400 26.145 27.454 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 27.400 26.721 27.454 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 27.400 27.297 27.454 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 27.400 27.873 27.454 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 27.400 28.449 27.454 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 27.400 29.025 27.454 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 27.400 29.601 27.454 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 27.400 30.177 27.454 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 27.400 30.753 27.454 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 27.400 31.329 27.454 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 27.400 31.905 27.454 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 27.400 32.481 27.454 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 27.400 33.057 27.454 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 27.400 33.633 27.454 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 27.400 34.209 27.454 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 27.400 34.785 27.454 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 27.400 35.361 27.454 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 27.400 35.937 27.454 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 27.400 36.513 27.454 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 27.400 37.089 27.454 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 27.400 37.665 27.454 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 27.400 38.241 27.454 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 27.400 38.817 27.454 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 27.400 39.393 27.454 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 27.400 39.969 27.454 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 27.400 40.545 27.454 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 27.400 41.121 27.454 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 27.400 41.697 27.454 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 27.400 42.273 27.454 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 27.400 42.849 27.454 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 27.400 43.425 27.454 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 27.400 44.001 27.454 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 27.400 44.577 27.454 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 27.400 45.153 27.454 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 27.400 45.729 27.454 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 27.400 46.305 27.454 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 27.400 46.881 27.454 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 27.400 47.457 27.454 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 27.400 48.033 27.454 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 27.400 48.609 27.454 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 27.400 49.185 27.454 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 27.400 49.761 27.454 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 27.400 50.337 27.454 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 27.400 50.913 27.454 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 27.400 51.489 27.454 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 27.400 52.065 27.454 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 27.400 52.641 27.454 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 27.400 53.217 27.454 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 27.400 53.793 27.454 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 27.400 54.369 27.454 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 27.400 54.945 27.454 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 27.400 55.521 27.454 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 27.400 56.097 27.454 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 27.400 56.673 27.454 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 27.400 57.249 27.454 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 27.400 57.825 27.454 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 27.400 58.401 27.454 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 27.400 58.977 27.454 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 27.400 59.553 27.454 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 27.400 60.129 27.454 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 27.400 60.705 27.454 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 27.400 61.281 27.454 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 27.400 61.857 27.454 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 27.400 62.433 27.454 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 27.400 63.009 27.454 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 27.400 63.585 27.454 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 27.400 64.161 27.454 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 27.400 64.737 27.454 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 27.400 65.313 27.454 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 27.400 65.889 27.454 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 27.400 66.465 27.454 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 27.400 67.041 27.454 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 27.400 67.617 27.454 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 27.400 68.193 27.454 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 27.400 68.769 27.454 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 27.400 69.345 27.454 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 27.400 69.921 27.454 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 27.400 70.497 27.454 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 27.400 71.073 27.454 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 27.400 71.649 27.454 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 27.400 72.225 27.454 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 27.400 72.801 27.454 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 27.400 73.377 27.454 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 27.400 73.953 27.454 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 27.400 74.529 27.454 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 27.400 75.105 27.454 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 27.400 75.681 27.454 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 27.400 76.257 27.454 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 27.400 76.833 27.454 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 27.400 77.409 27.454 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 27.400 77.985 27.454 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 27.400 78.561 27.454 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 27.400 79.137 27.454 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 27.400 79.713 27.454 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 27.400 80.289 27.454 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 27.400 80.865 27.454 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 27.400 81.441 27.454 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 27.400 82.017 27.454 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 27.400 82.593 27.454 ; + END + END r0_rd_out[287] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.804 0.072 24.828 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.140 0.072 25.164 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.468 86.781 24.492 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.804 86.781 24.828 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.812 0.072 25.836 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.148 0.072 26.172 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.140 86.781 25.164 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.476 86.781 25.500 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 27.400 83.169 27.454 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 27.400 83.745 27.454 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 27.400 84.321 27.454 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 27.400 84.897 27.454 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 27.400 85.473 27.454 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 86.781 27.454 ; + LAYER M2 ; + RECT 0 0 86.781 27.454 ; + LAYER M3 ; + RECT 0 0 86.781 27.454 ; + LAYER M4 ; + RECT 0 0 86.781 27.454 ; + END +END fakeram_288x20_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_288x32_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_288x32_1r1w.lef new file mode 100644 index 0000000..e86a48a --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_288x32_1r1w.lef @@ -0,0 +1,5429 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_288x32_1r1w + FOREIGN fakeram_288x32_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 86.781 BY 29.463 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.020 0.072 10.044 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.692 0.072 10.716 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.708 0.072 12.732 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.724 0.072 14.748 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.068 0.072 16.092 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.084 0.072 18.108 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.756 0.072 18.780 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.100 0.072 20.124 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.772 0.072 20.796 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.116 0.072 22.140 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.788 0.072 22.812 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.132 0.072 24.156 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.276 86.781 0.300 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.612 86.781 0.636 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.948 86.781 0.972 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.284 86.781 1.308 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.620 86.781 1.644 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.956 86.781 1.980 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.292 86.781 2.316 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.628 86.781 2.652 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.964 86.781 2.988 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.300 86.781 3.324 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.636 86.781 3.660 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.972 86.781 3.996 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.308 86.781 4.332 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.644 86.781 4.668 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.980 86.781 5.004 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.316 86.781 5.340 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.652 86.781 5.676 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.988 86.781 6.012 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.324 86.781 6.348 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.660 86.781 6.684 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.996 86.781 7.020 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.332 86.781 7.356 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.668 86.781 7.692 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.004 86.781 8.028 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.340 86.781 8.364 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.676 86.781 8.700 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.012 86.781 9.036 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.348 86.781 9.372 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.684 86.781 9.708 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.020 86.781 10.044 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.356 86.781 10.380 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.692 86.781 10.716 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.028 86.781 11.052 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.364 86.781 11.388 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.700 86.781 11.724 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.036 86.781 12.060 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.372 86.781 12.396 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.708 86.781 12.732 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.044 86.781 13.068 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.380 86.781 13.404 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.716 86.781 13.740 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.052 86.781 14.076 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.388 86.781 14.412 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.724 86.781 14.748 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.060 86.781 15.084 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.396 86.781 15.420 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.732 86.781 15.756 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.068 86.781 16.092 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.404 86.781 16.428 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.740 86.781 16.764 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.076 86.781 17.100 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.412 86.781 17.436 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.748 86.781 17.772 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.084 86.781 18.108 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.420 86.781 18.444 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.756 86.781 18.780 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.092 86.781 19.116 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.428 86.781 19.452 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.764 86.781 19.788 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.100 86.781 20.124 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.436 86.781 20.460 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.772 86.781 20.796 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.108 86.781 21.132 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.444 86.781 21.468 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.780 86.781 21.804 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.116 86.781 22.140 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.452 86.781 22.476 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.788 86.781 22.812 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.124 86.781 23.148 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.460 86.781 23.484 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.796 86.781 23.820 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.132 86.781 24.156 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[287] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 29.409 0.225 29.463 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 29.409 0.801 29.463 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 29.409 1.377 29.463 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 29.409 1.953 29.463 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 29.409 2.529 29.463 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 29.409 3.105 29.463 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 29.409 3.681 29.463 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 29.409 4.257 29.463 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 29.409 4.833 29.463 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 29.409 5.409 29.463 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 29.409 5.985 29.463 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 29.409 6.561 29.463 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 29.409 7.137 29.463 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 29.409 7.713 29.463 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 29.409 8.289 29.463 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 29.409 8.865 29.463 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 29.409 9.441 29.463 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 29.409 10.017 29.463 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 29.409 10.593 29.463 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 29.409 11.169 29.463 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 29.409 11.745 29.463 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 29.409 12.321 29.463 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 29.409 12.897 29.463 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 29.409 13.473 29.463 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 29.409 14.049 29.463 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 29.409 14.625 29.463 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 29.409 15.201 29.463 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 29.409 15.777 29.463 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 29.409 16.353 29.463 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 29.409 16.929 29.463 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 29.409 17.505 29.463 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 29.409 18.081 29.463 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 29.409 18.657 29.463 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 29.409 19.233 29.463 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 29.409 19.809 29.463 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 29.409 20.385 29.463 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 29.409 20.961 29.463 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 29.409 21.537 29.463 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 29.409 22.113 29.463 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 29.409 22.689 29.463 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 29.409 23.265 29.463 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 29.409 23.841 29.463 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 29.409 24.417 29.463 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 29.409 24.993 29.463 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 29.409 25.569 29.463 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 29.409 26.145 29.463 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 29.409 26.721 29.463 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 29.409 27.297 29.463 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 29.409 27.873 29.463 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 29.409 28.449 29.463 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 29.409 29.025 29.463 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 29.409 29.601 29.463 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 29.409 30.177 29.463 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 29.409 30.753 29.463 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 29.409 31.329 29.463 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 29.409 31.905 29.463 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 29.409 32.481 29.463 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 29.409 33.057 29.463 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 29.409 33.633 29.463 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 29.409 34.209 29.463 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 29.409 34.785 29.463 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 29.409 35.361 29.463 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 29.409 35.937 29.463 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 29.409 36.513 29.463 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 29.409 37.089 29.463 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 29.409 37.665 29.463 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 29.409 38.241 29.463 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 29.409 38.817 29.463 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 29.409 39.393 29.463 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 29.409 39.969 29.463 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 29.409 40.545 29.463 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 29.409 41.121 29.463 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 29.409 41.697 29.463 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 29.409 42.273 29.463 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 29.409 42.849 29.463 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 29.409 43.425 29.463 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 29.409 44.001 29.463 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 29.409 44.577 29.463 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 29.409 45.153 29.463 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 29.409 45.729 29.463 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 29.409 46.305 29.463 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 29.409 46.881 29.463 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 29.409 47.457 29.463 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 29.409 48.033 29.463 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 29.409 48.609 29.463 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 29.409 49.185 29.463 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 29.409 49.761 29.463 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 29.409 50.337 29.463 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 29.409 50.913 29.463 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 29.409 51.489 29.463 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 29.409 52.065 29.463 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 29.409 52.641 29.463 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 29.409 53.217 29.463 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 29.409 53.793 29.463 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 29.409 54.369 29.463 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 29.409 54.945 29.463 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 29.409 55.521 29.463 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 29.409 56.097 29.463 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 29.409 56.673 29.463 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 29.409 57.249 29.463 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 29.409 57.825 29.463 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 29.409 58.401 29.463 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 29.409 58.977 29.463 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 29.409 59.553 29.463 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 29.409 60.129 29.463 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 29.409 60.705 29.463 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 29.409 61.281 29.463 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 29.409 61.857 29.463 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 29.409 62.433 29.463 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 29.409 63.009 29.463 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 29.409 63.585 29.463 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 29.409 64.161 29.463 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 29.409 64.737 29.463 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 29.409 65.313 29.463 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 29.409 65.889 29.463 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 29.409 66.465 29.463 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 29.409 67.041 29.463 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 29.409 67.617 29.463 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 29.409 68.193 29.463 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 29.409 68.769 29.463 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 29.409 69.345 29.463 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 29.409 69.921 29.463 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 29.409 70.497 29.463 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 29.409 71.073 29.463 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 29.409 71.649 29.463 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 29.409 72.225 29.463 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 29.409 72.801 29.463 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 29.409 73.377 29.463 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 29.409 73.953 29.463 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 29.409 74.529 29.463 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 29.409 75.105 29.463 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 29.409 75.681 29.463 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 29.409 76.257 29.463 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 29.409 76.833 29.463 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 29.409 77.409 29.463 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 29.409 77.985 29.463 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 29.409 78.561 29.463 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 29.409 79.137 29.463 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 29.409 79.713 29.463 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 29.409 80.289 29.463 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 29.409 80.865 29.463 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 29.409 81.441 29.463 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 29.409 82.017 29.463 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 29.409 82.593 29.463 ; + END + END r0_rd_out[287] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.804 0.072 24.828 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.140 0.072 25.164 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.468 86.781 24.492 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.804 86.781 24.828 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.812 0.072 25.836 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.148 0.072 26.172 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.140 86.781 25.164 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.476 86.781 25.500 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 29.409 83.169 29.463 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 29.409 83.745 29.463 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 29.409 84.321 29.463 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 29.409 84.897 29.463 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 29.409 85.473 29.463 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + RECT 0.216 27.888 86.565 27.984 ; + RECT 0.216 28.656 86.565 28.752 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + RECT 0.216 27.888 86.565 27.984 ; + RECT 0.216 28.656 86.565 28.752 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 86.781 29.463 ; + LAYER M2 ; + RECT 0 0 86.781 29.463 ; + LAYER M3 ; + RECT 0 0 86.781 29.463 ; + LAYER M4 ; + RECT 0 0 86.781 29.463 ; + END +END fakeram_288x32_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_288x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_288x64_1r1w.lef new file mode 100644 index 0000000..894a0a7 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_288x64_1r1w.lef @@ -0,0 +1,5461 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_288x64_1r1w + FOREIGN fakeram_288x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 86.781 BY 34.820 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.276 86.781 0.300 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.708 86.781 0.732 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.140 86.781 1.164 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.572 86.781 1.596 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.004 86.781 2.028 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.436 86.781 2.460 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.868 86.781 2.892 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.300 86.781 3.324 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.732 86.781 3.756 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.164 86.781 4.188 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.596 86.781 4.620 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.028 86.781 5.052 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.460 86.781 5.484 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.892 86.781 5.916 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.324 86.781 6.348 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.756 86.781 6.780 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.188 86.781 7.212 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.620 86.781 7.644 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.052 86.781 8.076 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.484 86.781 8.508 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.916 86.781 8.940 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.348 86.781 9.372 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.780 86.781 9.804 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.212 86.781 10.236 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.644 86.781 10.668 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.076 86.781 11.100 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.508 86.781 11.532 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.940 86.781 11.964 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.372 86.781 12.396 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.804 86.781 12.828 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.236 86.781 13.260 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.668 86.781 13.692 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.100 86.781 14.124 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.532 86.781 14.556 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.964 86.781 14.988 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.396 86.781 15.420 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.828 86.781 15.852 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.260 86.781 16.284 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.692 86.781 16.716 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.124 86.781 17.148 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.556 86.781 17.580 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.988 86.781 18.012 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.420 86.781 18.444 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.852 86.781 18.876 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.284 86.781 19.308 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.716 86.781 19.740 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.148 86.781 20.172 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.580 86.781 20.604 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.012 86.781 21.036 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.444 86.781 21.468 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.876 86.781 21.900 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.308 86.781 22.332 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.740 86.781 22.764 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.172 86.781 23.196 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.604 86.781 23.628 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.036 86.781 24.060 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.468 86.781 24.492 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.900 86.781 24.924 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.332 86.781 25.356 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.764 86.781 25.788 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 26.196 86.781 26.220 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 26.628 86.781 26.652 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 27.060 86.781 27.084 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 27.492 86.781 27.516 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 27.924 86.781 27.948 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 28.356 86.781 28.380 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 28.788 86.781 28.812 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 29.220 86.781 29.244 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 29.652 86.781 29.676 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 30.084 86.781 30.108 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 30.516 86.781 30.540 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 30.948 86.781 30.972 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[287] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 34.766 0.225 34.820 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 34.766 0.801 34.820 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 34.766 1.377 34.820 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 34.766 1.953 34.820 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 34.766 2.529 34.820 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 34.766 3.105 34.820 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 34.766 3.681 34.820 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 34.766 4.257 34.820 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 34.766 4.833 34.820 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 34.766 5.409 34.820 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 34.766 5.985 34.820 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 34.766 6.561 34.820 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 34.766 7.137 34.820 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 34.766 7.713 34.820 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 34.766 8.289 34.820 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 34.766 8.865 34.820 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 34.766 9.441 34.820 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 34.766 10.017 34.820 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 34.766 10.593 34.820 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 34.766 11.169 34.820 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 34.766 11.745 34.820 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 34.766 12.321 34.820 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 34.766 12.897 34.820 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 34.766 13.473 34.820 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 34.766 14.049 34.820 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 34.766 14.625 34.820 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 34.766 15.201 34.820 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 34.766 15.777 34.820 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 34.766 16.353 34.820 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 34.766 16.929 34.820 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 34.766 17.505 34.820 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 34.766 18.081 34.820 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 34.766 18.657 34.820 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 34.766 19.233 34.820 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 34.766 19.809 34.820 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 34.766 20.385 34.820 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 34.766 20.961 34.820 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 34.766 21.537 34.820 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 34.766 22.113 34.820 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 34.766 22.689 34.820 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 34.766 23.265 34.820 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 34.766 23.841 34.820 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 34.766 24.417 34.820 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 34.766 24.993 34.820 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 34.766 25.569 34.820 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 34.766 26.145 34.820 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 34.766 26.721 34.820 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 34.766 27.297 34.820 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 34.766 27.873 34.820 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 34.766 28.449 34.820 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 34.766 29.025 34.820 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 34.766 29.601 34.820 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 34.766 30.177 34.820 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 34.766 30.753 34.820 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 34.766 31.329 34.820 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 34.766 31.905 34.820 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 34.766 32.481 34.820 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 34.766 33.057 34.820 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 34.766 33.633 34.820 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 34.766 34.209 34.820 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 34.766 34.785 34.820 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 34.766 35.361 34.820 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 34.766 35.937 34.820 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 34.766 36.513 34.820 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 34.766 37.089 34.820 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 34.766 37.665 34.820 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 34.766 38.241 34.820 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 34.766 38.817 34.820 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 34.766 39.393 34.820 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 34.766 39.969 34.820 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 34.766 40.545 34.820 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 34.766 41.121 34.820 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 34.766 41.697 34.820 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 34.766 42.273 34.820 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 34.766 42.849 34.820 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 34.766 43.425 34.820 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 34.766 44.001 34.820 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 34.766 44.577 34.820 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 34.766 45.153 34.820 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 34.766 45.729 34.820 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 34.766 46.305 34.820 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 34.766 46.881 34.820 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 34.766 47.457 34.820 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 34.766 48.033 34.820 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 34.766 48.609 34.820 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 34.766 49.185 34.820 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 34.766 49.761 34.820 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 34.766 50.337 34.820 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 34.766 50.913 34.820 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 34.766 51.489 34.820 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 34.766 52.065 34.820 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 34.766 52.641 34.820 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 34.766 53.217 34.820 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 34.766 53.793 34.820 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 34.766 54.369 34.820 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 34.766 54.945 34.820 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 34.766 55.521 34.820 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 34.766 56.097 34.820 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 34.766 56.673 34.820 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 34.766 57.249 34.820 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 34.766 57.825 34.820 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 34.766 58.401 34.820 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 34.766 58.977 34.820 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 34.766 59.553 34.820 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 34.766 60.129 34.820 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 34.766 60.705 34.820 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 34.766 61.281 34.820 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 34.766 61.857 34.820 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 34.766 62.433 34.820 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 34.766 63.009 34.820 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 34.766 63.585 34.820 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 34.766 64.161 34.820 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 34.766 64.737 34.820 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 34.766 65.313 34.820 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 34.766 65.889 34.820 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 34.766 66.465 34.820 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 34.766 67.041 34.820 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 34.766 67.617 34.820 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 34.766 68.193 34.820 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 34.766 68.769 34.820 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 34.766 69.345 34.820 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 34.766 69.921 34.820 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 34.766 70.497 34.820 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 34.766 71.073 34.820 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 34.766 71.649 34.820 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 34.766 72.225 34.820 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 34.766 72.801 34.820 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 34.766 73.377 34.820 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 34.766 73.953 34.820 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 34.766 74.529 34.820 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 34.766 75.105 34.820 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 34.766 75.681 34.820 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 34.766 76.257 34.820 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 34.766 76.833 34.820 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 34.766 77.409 34.820 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 34.766 77.985 34.820 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 34.766 78.561 34.820 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 34.766 79.137 34.820 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 34.766 79.713 34.820 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 34.766 80.289 34.820 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 34.766 80.865 34.820 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 34.766 81.441 34.820 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 34.766 82.017 34.820 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 34.766 82.593 34.820 ; + END + END r0_rd_out[287] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 31.380 86.781 31.404 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 31.812 86.781 31.836 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 32.244 86.781 32.268 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 32.676 86.781 32.700 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 33.108 86.781 33.132 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 33.540 86.781 33.564 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 34.766 83.169 34.820 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 34.766 83.745 34.820 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 34.766 84.321 34.820 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 34.766 84.897 34.820 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 34.766 85.473 34.820 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + RECT 0.216 27.888 86.565 27.984 ; + RECT 0.216 28.656 86.565 28.752 ; + RECT 0.216 29.424 86.565 29.520 ; + RECT 0.216 30.192 86.565 30.288 ; + RECT 0.216 30.960 86.565 31.056 ; + RECT 0.216 31.728 86.565 31.824 ; + RECT 0.216 32.496 86.565 32.592 ; + RECT 0.216 33.264 86.565 33.360 ; + RECT 0.216 34.032 86.565 34.128 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + RECT 0.216 27.888 86.565 27.984 ; + RECT 0.216 28.656 86.565 28.752 ; + RECT 0.216 29.424 86.565 29.520 ; + RECT 0.216 30.192 86.565 30.288 ; + RECT 0.216 30.960 86.565 31.056 ; + RECT 0.216 31.728 86.565 31.824 ; + RECT 0.216 32.496 86.565 32.592 ; + RECT 0.216 33.264 86.565 33.360 ; + RECT 0.216 34.032 86.565 34.128 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 86.781 34.820 ; + LAYER M2 ; + RECT 0 0 86.781 34.820 ; + LAYER M3 ; + RECT 0 0 86.781 34.820 ; + LAYER M4 ; + RECT 0 0 86.781 34.820 ; + END +END fakeram_288x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_288x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_288x80_1r1w.lef new file mode 100644 index 0000000..37b472d --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_288x80_1r1w.lef @@ -0,0 +1,5487 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_288x80_1r1w + FOREIGN fakeram_288x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 86.781 BY 37.498 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.276 86.781 0.300 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 0.708 86.781 0.732 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.140 86.781 1.164 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 1.572 86.781 1.596 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.004 86.781 2.028 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.436 86.781 2.460 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 2.868 86.781 2.892 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.300 86.781 3.324 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 3.732 86.781 3.756 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.164 86.781 4.188 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 4.596 86.781 4.620 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.028 86.781 5.052 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.460 86.781 5.484 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 5.892 86.781 5.916 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.324 86.781 6.348 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 6.756 86.781 6.780 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.188 86.781 7.212 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 7.620 86.781 7.644 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.052 86.781 8.076 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.484 86.781 8.508 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 8.916 86.781 8.940 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.348 86.781 9.372 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 9.780 86.781 9.804 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.212 86.781 10.236 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 10.644 86.781 10.668 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.076 86.781 11.100 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.508 86.781 11.532 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 11.940 86.781 11.964 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.372 86.781 12.396 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 12.804 86.781 12.828 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.236 86.781 13.260 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 13.668 86.781 13.692 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.100 86.781 14.124 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.532 86.781 14.556 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 14.964 86.781 14.988 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.396 86.781 15.420 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 15.828 86.781 15.852 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.260 86.781 16.284 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 16.692 86.781 16.716 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.124 86.781 17.148 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.556 86.781 17.580 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 17.988 86.781 18.012 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.420 86.781 18.444 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 18.852 86.781 18.876 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.284 86.781 19.308 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 19.716 86.781 19.740 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.148 86.781 20.172 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 20.580 86.781 20.604 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.012 86.781 21.036 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.444 86.781 21.468 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 21.876 86.781 21.900 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.308 86.781 22.332 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 22.740 86.781 22.764 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.172 86.781 23.196 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 23.604 86.781 23.628 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.036 86.781 24.060 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.468 86.781 24.492 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 24.900 86.781 24.924 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.332 86.781 25.356 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 25.764 86.781 25.788 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 26.196 86.781 26.220 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 26.628 86.781 26.652 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 27.060 86.781 27.084 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 27.492 86.781 27.516 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 27.924 86.781 27.948 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 28.356 86.781 28.380 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 28.788 86.781 28.812 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 29.220 86.781 29.244 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 29.652 86.781 29.676 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 30.084 86.781 30.108 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 30.516 86.781 30.540 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 30.948 86.781 30.972 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[287] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 37.444 0.225 37.498 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 37.444 0.801 37.498 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 37.444 1.377 37.498 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 37.444 1.953 37.498 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 37.444 2.529 37.498 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 37.444 3.105 37.498 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 37.444 3.681 37.498 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 37.444 4.257 37.498 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 37.444 4.833 37.498 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 37.444 5.409 37.498 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 37.444 5.985 37.498 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 37.444 6.561 37.498 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 37.444 7.137 37.498 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 37.444 7.713 37.498 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 37.444 8.289 37.498 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 37.444 8.865 37.498 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 37.444 9.441 37.498 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 37.444 10.017 37.498 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 37.444 10.593 37.498 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 37.444 11.169 37.498 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 37.444 11.745 37.498 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 37.444 12.321 37.498 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 37.444 12.897 37.498 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 37.444 13.473 37.498 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 37.444 14.049 37.498 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 37.444 14.625 37.498 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 37.444 15.201 37.498 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 37.444 15.777 37.498 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 37.444 16.353 37.498 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 37.444 16.929 37.498 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 37.444 17.505 37.498 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 37.444 18.081 37.498 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 37.444 18.657 37.498 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 37.444 19.233 37.498 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 37.444 19.809 37.498 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 37.444 20.385 37.498 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 37.444 20.961 37.498 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 37.444 21.537 37.498 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 37.444 22.113 37.498 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 37.444 22.689 37.498 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 37.444 23.265 37.498 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 37.444 23.841 37.498 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 37.444 24.417 37.498 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 37.444 24.993 37.498 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 37.444 25.569 37.498 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 37.444 26.145 37.498 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 37.444 26.721 37.498 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 37.444 27.297 37.498 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 37.444 27.873 37.498 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 37.444 28.449 37.498 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 37.444 29.025 37.498 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 37.444 29.601 37.498 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 37.444 30.177 37.498 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 37.444 30.753 37.498 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 37.444 31.329 37.498 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 37.444 31.905 37.498 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 37.444 32.481 37.498 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 37.444 33.057 37.498 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 37.444 33.633 37.498 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 37.444 34.209 37.498 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 37.444 34.785 37.498 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 37.444 35.361 37.498 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 37.444 35.937 37.498 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 37.444 36.513 37.498 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 37.444 37.089 37.498 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 37.444 37.665 37.498 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 37.444 38.241 37.498 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 37.444 38.817 37.498 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 37.444 39.393 37.498 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 37.444 39.969 37.498 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 37.444 40.545 37.498 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 37.444 41.121 37.498 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 37.444 41.697 37.498 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 37.444 42.273 37.498 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 37.444 42.849 37.498 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 37.444 43.425 37.498 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 37.444 44.001 37.498 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 37.444 44.577 37.498 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 37.444 45.153 37.498 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 37.444 45.729 37.498 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 37.444 46.305 37.498 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 37.444 46.881 37.498 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 37.444 47.457 37.498 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 37.444 48.033 37.498 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 37.444 48.609 37.498 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 37.444 49.185 37.498 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 37.444 49.761 37.498 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 37.444 50.337 37.498 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 37.444 50.913 37.498 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 37.444 51.489 37.498 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 37.444 52.065 37.498 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 37.444 52.641 37.498 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 37.444 53.217 37.498 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 37.444 53.793 37.498 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 37.444 54.369 37.498 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 37.444 54.945 37.498 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 37.444 55.521 37.498 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 37.444 56.097 37.498 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 37.444 56.673 37.498 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 37.444 57.249 37.498 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 37.444 57.825 37.498 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 37.444 58.401 37.498 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 37.444 58.977 37.498 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 37.444 59.553 37.498 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 37.444 60.129 37.498 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 37.444 60.705 37.498 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 37.444 61.281 37.498 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 37.444 61.857 37.498 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 37.444 62.433 37.498 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 37.444 63.009 37.498 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 37.444 63.585 37.498 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 37.444 64.161 37.498 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 37.444 64.737 37.498 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 37.444 65.313 37.498 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 37.444 65.889 37.498 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 37.444 66.465 37.498 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 37.444 67.041 37.498 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 37.444 67.617 37.498 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 37.444 68.193 37.498 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 37.444 68.769 37.498 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 37.444 69.345 37.498 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 37.444 69.921 37.498 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 37.444 70.497 37.498 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 37.444 71.073 37.498 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 37.444 71.649 37.498 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 37.444 72.225 37.498 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 37.444 72.801 37.498 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 37.444 73.377 37.498 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 37.444 73.953 37.498 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 37.444 74.529 37.498 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 37.444 75.105 37.498 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 37.444 75.681 37.498 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 37.444 76.257 37.498 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 37.444 76.833 37.498 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 37.444 77.409 37.498 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 37.444 77.985 37.498 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 37.444 78.561 37.498 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 37.444 79.137 37.498 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 37.444 79.713 37.498 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 37.444 80.289 37.498 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 37.444 80.865 37.498 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 37.444 81.441 37.498 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 37.444 82.017 37.498 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 37.444 82.593 37.498 ; + END + END r0_rd_out[287] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 31.380 86.781 31.404 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 31.812 86.781 31.836 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 32.244 86.781 32.268 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.404 0.072 34.428 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 32.676 86.781 32.700 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 33.108 86.781 33.132 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 86.709 33.540 86.781 33.564 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 37.444 83.169 37.498 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 37.444 83.745 37.498 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 37.444 84.321 37.498 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 37.444 84.897 37.498 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 37.444 85.473 37.498 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + RECT 0.216 27.888 86.565 27.984 ; + RECT 0.216 28.656 86.565 28.752 ; + RECT 0.216 29.424 86.565 29.520 ; + RECT 0.216 30.192 86.565 30.288 ; + RECT 0.216 30.960 86.565 31.056 ; + RECT 0.216 31.728 86.565 31.824 ; + RECT 0.216 32.496 86.565 32.592 ; + RECT 0.216 33.264 86.565 33.360 ; + RECT 0.216 34.032 86.565 34.128 ; + RECT 0.216 34.800 86.565 34.896 ; + RECT 0.216 35.568 86.565 35.664 ; + RECT 0.216 36.336 86.565 36.432 ; + RECT 0.216 37.104 86.565 37.200 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 86.565 0.336 ; + RECT 0.216 1.008 86.565 1.104 ; + RECT 0.216 1.776 86.565 1.872 ; + RECT 0.216 2.544 86.565 2.640 ; + RECT 0.216 3.312 86.565 3.408 ; + RECT 0.216 4.080 86.565 4.176 ; + RECT 0.216 4.848 86.565 4.944 ; + RECT 0.216 5.616 86.565 5.712 ; + RECT 0.216 6.384 86.565 6.480 ; + RECT 0.216 7.152 86.565 7.248 ; + RECT 0.216 7.920 86.565 8.016 ; + RECT 0.216 8.688 86.565 8.784 ; + RECT 0.216 9.456 86.565 9.552 ; + RECT 0.216 10.224 86.565 10.320 ; + RECT 0.216 10.992 86.565 11.088 ; + RECT 0.216 11.760 86.565 11.856 ; + RECT 0.216 12.528 86.565 12.624 ; + RECT 0.216 13.296 86.565 13.392 ; + RECT 0.216 14.064 86.565 14.160 ; + RECT 0.216 14.832 86.565 14.928 ; + RECT 0.216 15.600 86.565 15.696 ; + RECT 0.216 16.368 86.565 16.464 ; + RECT 0.216 17.136 86.565 17.232 ; + RECT 0.216 17.904 86.565 18.000 ; + RECT 0.216 18.672 86.565 18.768 ; + RECT 0.216 19.440 86.565 19.536 ; + RECT 0.216 20.208 86.565 20.304 ; + RECT 0.216 20.976 86.565 21.072 ; + RECT 0.216 21.744 86.565 21.840 ; + RECT 0.216 22.512 86.565 22.608 ; + RECT 0.216 23.280 86.565 23.376 ; + RECT 0.216 24.048 86.565 24.144 ; + RECT 0.216 24.816 86.565 24.912 ; + RECT 0.216 25.584 86.565 25.680 ; + RECT 0.216 26.352 86.565 26.448 ; + RECT 0.216 27.120 86.565 27.216 ; + RECT 0.216 27.888 86.565 27.984 ; + RECT 0.216 28.656 86.565 28.752 ; + RECT 0.216 29.424 86.565 29.520 ; + RECT 0.216 30.192 86.565 30.288 ; + RECT 0.216 30.960 86.565 31.056 ; + RECT 0.216 31.728 86.565 31.824 ; + RECT 0.216 32.496 86.565 32.592 ; + RECT 0.216 33.264 86.565 33.360 ; + RECT 0.216 34.032 86.565 34.128 ; + RECT 0.216 34.800 86.565 34.896 ; + RECT 0.216 35.568 86.565 35.664 ; + RECT 0.216 36.336 86.565 36.432 ; + RECT 0.216 37.104 86.565 37.200 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 86.781 37.498 ; + LAYER M2 ; + RECT 0 0 86.781 37.498 ; + LAYER M3 ; + RECT 0 0 86.781 37.498 ; + LAYER M4 ; + RECT 0 0 86.781 37.498 ; + END +END fakeram_288x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_32x128_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_32x128_1r1w.lef new file mode 100644 index 0000000..22129ce --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_32x128_1r1w.lef @@ -0,0 +1,843 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_32x128_1r1w + FOREIGN fakeram_32x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 24.106 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 1.812 9.643 1.836 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 3.348 9.643 3.372 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.884 9.643 4.908 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.420 9.643 6.444 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.956 9.643 7.980 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.492 9.643 9.516 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 11.028 9.643 11.052 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.459 0.000 0.477 0.054 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 0.000 0.729 0.054 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.963 0.000 0.981 0.054 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 0.000 1.233 0.054 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 0.000 1.485 0.054 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 0.000 1.737 0.054 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.971 0.000 1.989 0.054 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.475 0.000 2.493 0.054 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.979 0.000 2.997 0.054 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.483 0.000 3.501 0.054 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 0.000 3.753 0.054 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END w0_wd_in[31] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.491 0.000 4.509 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.995 0.000 5.013 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.499 0.000 5.517 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 0.000 5.769 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.003 0.000 6.021 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 0.000 6.777 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.011 0.000 7.029 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 0.000 7.281 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.515 0.000 7.533 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.019 0.000 8.037 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 24.052 0.225 24.106 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 24.052 0.657 24.106 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 24.052 1.089 24.106 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 24.052 1.521 24.106 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 24.052 1.953 24.106 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 24.052 2.385 24.106 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 24.052 2.817 24.106 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 24.052 3.249 24.106 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 24.052 3.681 24.106 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 24.052 4.113 24.106 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 24.052 4.545 24.106 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 24.052 4.977 24.106 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 24.052 5.409 24.106 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.823 24.052 5.841 24.106 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 24.052 6.273 24.106 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 24.052 6.705 24.106 ; + END + END r0_rd_out[31] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.564 0.072 12.588 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 12.564 9.643 12.588 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 14.100 9.643 14.124 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 15.636 9.643 15.660 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.244 0.072 20.268 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 17.172 9.643 17.196 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 18.708 9.643 18.732 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 20.244 9.643 20.268 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 24.052 7.137 24.106 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.551 24.052 7.569 24.106 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 24.052 8.001 24.106 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 24.052 8.433 24.106 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 24.052 8.865 24.106 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 24.106 ; + LAYER M2 ; + RECT 0 0 9.643 24.106 ; + LAYER M3 ; + RECT 0 0 9.643 24.106 ; + LAYER M4 ; + RECT 0 0 9.643 24.106 ; + END +END fakeram_32x128_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_32x32_1r1w.lef similarity index 63% rename from designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef rename to designs/asap7/NVDLA/sram/lef/fakeram_32x32_1r1w.lef index 06ae066..b8b1c6a 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef +++ b/designs/asap7/NVDLA/sram/lef/fakeram_32x32_1r1w.lef @@ -1,9 +1,9 @@ VERSION 5.7 ; BUSBITCHARS "[]" ; -MACRO fakeram_20x64_2r1w - FOREIGN fakeram_20x64_2r1w 0 0 ; +MACRO fakeram_32x32_1r1w + FOREIGN fakeram_32x32_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 10.368 BY 5.184 ; + SIZE 9.643 BY 9.643 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -11,7 +11,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 0.276 0.072 0.300 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +20,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.564 0.024 0.588 ; + RECT 0.000 0.948 0.072 0.972 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.852 0.024 0.876 ; + RECT 0.000 1.620 0.072 1.644 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.140 0.024 1.164 ; + RECT 0.000 2.292 0.072 2.316 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; + RECT 0.000 2.964 0.072 2.988 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.276 10.368 0.300 ; + RECT 0.000 3.636 0.072 3.660 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.564 10.368 0.588 ; + RECT 0.000 4.308 0.072 4.332 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 0.852 10.368 0.876 ; + RECT 0.000 4.980 0.072 5.004 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.140 10.368 1.164 ; + RECT 9.571 0.276 9.643 0.300 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,61 +92,61 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.428 10.368 1.452 ; + RECT 9.571 0.948 9.643 0.972 ; END END w0_wd_in[9] PIN w0_wd_in[10] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + LAYER M4 ; + RECT 9.571 1.620 9.643 1.644 ; END END w0_wd_in[10] PIN w0_wd_in[11] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.531 0.000 0.549 0.018 ; + LAYER M4 ; + RECT 9.571 2.292 9.643 2.316 ; END END w0_wd_in[11] PIN w0_wd_in[12] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.855 0.000 0.873 0.018 ; + LAYER M4 ; + RECT 9.571 2.964 9.643 2.988 ; END END w0_wd_in[12] PIN w0_wd_in[13] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 1.179 0.000 1.197 0.018 ; + LAYER M4 ; + RECT 9.571 3.636 9.643 3.660 ; END END w0_wd_in[13] PIN w0_wd_in[14] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 1.503 0.000 1.521 0.018 ; + LAYER M4 ; + RECT 9.571 4.308 9.643 4.332 ; END END w0_wd_in[14] PIN w0_wd_in[15] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 1.827 0.000 1.845 0.018 ; + LAYER M4 ; + RECT 9.571 4.980 9.643 5.004 ; END END w0_wd_in[15] PIN w0_wd_in[16] @@ -155,7 +155,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.151 0.000 2.169 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END END w0_wd_in[16] PIN w0_wd_in[17] @@ -164,7 +164,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.475 0.000 2.493 0.018 ; + RECT 0.459 0.000 0.477 0.054 ; END END w0_wd_in[17] PIN w0_wd_in[18] @@ -173,7 +173,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.799 0.000 2.817 0.018 ; + RECT 0.711 0.000 0.729 0.054 ; END END w0_wd_in[18] PIN w0_wd_in[19] @@ -182,376 +182,412 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.123 0.000 3.141 0.018 ; + RECT 0.963 0.000 0.981 0.054 ; END END w0_wd_in[19] - PIN r0_rd_out[0] + PIN w0_wd_in[20] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 0.000 3.465 0.018 ; + RECT 1.215 0.000 1.233 0.054 ; END - END r0_rd_out[0] - PIN r0_rd_out[1] + END w0_wd_in[20] + PIN w0_wd_in[21] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 0.000 3.789 0.018 ; + RECT 1.467 0.000 1.485 0.054 ; END - END r0_rd_out[1] - PIN r0_rd_out[2] + END w0_wd_in[21] + PIN w0_wd_in[22] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.095 0.000 4.113 0.018 ; + RECT 1.719 0.000 1.737 0.054 ; END - END r0_rd_out[2] - PIN r0_rd_out[3] + END w0_wd_in[22] + PIN w0_wd_in[23] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + RECT 1.971 0.000 1.989 0.054 ; END - END r0_rd_out[3] - PIN r0_rd_out[4] + END w0_wd_in[23] + PIN w0_wd_in[24] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; + RECT 2.223 0.000 2.241 0.054 ; END - END r0_rd_out[4] - PIN r0_rd_out[5] + END w0_wd_in[24] + PIN w0_wd_in[25] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.067 0.000 5.085 0.018 ; + RECT 2.475 0.000 2.493 0.054 ; END - END r0_rd_out[5] - PIN r0_rd_out[6] + END w0_wd_in[25] + PIN w0_wd_in[26] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 0.000 5.409 0.018 ; + RECT 2.727 0.000 2.745 0.054 ; END - END r0_rd_out[6] - PIN r0_rd_out[7] + END w0_wd_in[26] + PIN w0_wd_in[27] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.715 0.000 5.733 0.018 ; + RECT 2.979 0.000 2.997 0.054 ; END - END r0_rd_out[7] - PIN r0_rd_out[8] + END w0_wd_in[27] + PIN w0_wd_in[28] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.039 0.000 6.057 0.018 ; + RECT 3.231 0.000 3.249 0.054 ; END - END r0_rd_out[8] - PIN r0_rd_out[9] + END w0_wd_in[28] + PIN w0_wd_in[29] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.363 0.000 6.381 0.018 ; + RECT 3.483 0.000 3.501 0.054 ; END - END r0_rd_out[9] - PIN r0_rd_out[10] + END w0_wd_in[29] + PIN w0_wd_in[30] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 5.166 0.225 5.184 ; + RECT 3.735 0.000 3.753 0.054 ; END - END r0_rd_out[10] - PIN r0_rd_out[11] + END w0_wd_in[30] + PIN w0_wd_in[31] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.567 5.166 0.585 5.184 ; + RECT 3.987 0.000 4.005 0.054 ; END - END r0_rd_out[11] - PIN r0_rd_out[12] + END w0_wd_in[31] + PIN r0_rd_out[0] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.927 5.166 0.945 5.184 ; + RECT 4.239 0.000 4.257 0.054 ; END - END r0_rd_out[12] - PIN r0_rd_out[13] + END r0_rd_out[0] + PIN r0_rd_out[1] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.287 5.166 1.305 5.184 ; + RECT 4.491 0.000 4.509 0.054 ; END - END r0_rd_out[13] - PIN r0_rd_out[14] + END r0_rd_out[1] + PIN r0_rd_out[2] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.647 5.166 1.665 5.184 ; + RECT 4.743 0.000 4.761 0.054 ; END - END r0_rd_out[14] - PIN r0_rd_out[15] + END r0_rd_out[2] + PIN r0_rd_out[3] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.007 5.166 2.025 5.184 ; + RECT 4.995 0.000 5.013 0.054 ; END - END r0_rd_out[15] - PIN r0_rd_out[16] + END r0_rd_out[3] + PIN r0_rd_out[4] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.367 5.166 2.385 5.184 ; + RECT 5.247 0.000 5.265 0.054 ; END - END r0_rd_out[16] - PIN r0_rd_out[17] + END r0_rd_out[4] + PIN r0_rd_out[5] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.727 5.166 2.745 5.184 ; + RECT 5.499 0.000 5.517 0.054 ; END - END r0_rd_out[17] - PIN r0_rd_out[18] + END r0_rd_out[5] + PIN r0_rd_out[6] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.087 5.166 3.105 5.184 ; + RECT 5.751 0.000 5.769 0.054 ; END - END r0_rd_out[18] - PIN r0_rd_out[19] + END r0_rd_out[6] + PIN r0_rd_out[7] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.447 5.166 3.465 5.184 ; + RECT 6.003 0.000 6.021 0.054 ; END - END r0_rd_out[19] - PIN r1_rd_out[0] + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 0.000 6.705 0.018 ; + RECT 6.759 0.000 6.777 0.054 ; END - END r1_rd_out[0] - PIN r1_rd_out[1] + END r0_rd_out[10] + PIN r0_rd_out[11] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.011 0.000 7.029 0.018 ; + RECT 7.011 0.000 7.029 0.054 ; END - END r1_rd_out[1] - PIN r1_rd_out[2] + END r0_rd_out[11] + PIN r0_rd_out[12] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 0.000 7.353 0.018 ; + RECT 7.263 0.000 7.281 0.054 ; END - END r1_rd_out[2] - PIN r1_rd_out[3] + END r0_rd_out[12] + PIN r0_rd_out[13] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.659 0.000 7.677 0.018 ; + RECT 7.515 0.000 7.533 0.054 ; END - END r1_rd_out[3] - PIN r1_rd_out[4] + END r0_rd_out[13] + PIN r0_rd_out[14] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.983 0.000 8.001 0.018 ; + RECT 7.767 0.000 7.785 0.054 ; END - END r1_rd_out[4] - PIN r1_rd_out[5] + END r0_rd_out[14] + PIN r0_rd_out[15] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.307 0.000 8.325 0.018 ; + RECT 8.019 0.000 8.037 0.054 ; END - END r1_rd_out[5] - PIN r1_rd_out[6] + END r0_rd_out[15] + PIN r0_rd_out[16] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 0.000 8.649 0.018 ; + RECT 0.207 9.589 0.225 9.643 ; END - END r1_rd_out[6] - PIN r1_rd_out[7] + END r0_rd_out[16] + PIN r0_rd_out[17] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.955 0.000 8.973 0.018 ; + RECT 0.639 9.589 0.657 9.643 ; END - END r1_rd_out[7] - PIN r1_rd_out[8] + END r0_rd_out[17] + PIN r0_rd_out[18] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; + RECT 1.071 9.589 1.089 9.643 ; END - END r1_rd_out[8] - PIN r1_rd_out[9] + END r0_rd_out[18] + PIN r0_rd_out[19] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.603 0.000 9.621 0.018 ; + RECT 1.503 9.589 1.521 9.643 ; END - END r1_rd_out[9] - PIN r1_rd_out[10] + END r0_rd_out[19] + PIN r0_rd_out[20] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.807 5.166 3.825 5.184 ; + RECT 1.935 9.589 1.953 9.643 ; END - END r1_rd_out[10] - PIN r1_rd_out[11] + END r0_rd_out[20] + PIN r0_rd_out[21] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 5.166 4.185 5.184 ; + RECT 2.367 9.589 2.385 9.643 ; END - END r1_rd_out[11] - PIN r1_rd_out[12] + END r0_rd_out[21] + PIN r0_rd_out[22] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.527 5.166 4.545 5.184 ; + RECT 2.799 9.589 2.817 9.643 ; END - END r1_rd_out[12] - PIN r1_rd_out[13] + END r0_rd_out[22] + PIN r0_rd_out[23] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.887 5.166 4.905 5.184 ; + RECT 3.231 9.589 3.249 9.643 ; END - END r1_rd_out[13] - PIN r1_rd_out[14] + END r0_rd_out[23] + PIN r0_rd_out[24] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.247 5.166 5.265 5.184 ; + RECT 3.663 9.589 3.681 9.643 ; END - END r1_rd_out[14] - PIN r1_rd_out[15] + END r0_rd_out[24] + PIN r0_rd_out[25] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.607 5.166 5.625 5.184 ; + RECT 4.095 9.589 4.113 9.643 ; END - END r1_rd_out[15] - PIN r1_rd_out[16] + END r0_rd_out[25] + PIN r0_rd_out[26] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.967 5.166 5.985 5.184 ; + RECT 4.527 9.589 4.545 9.643 ; END - END r1_rd_out[16] - PIN r1_rd_out[17] + END r0_rd_out[26] + PIN r0_rd_out[27] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.327 5.166 6.345 5.184 ; + RECT 4.959 9.589 4.977 9.643 ; END - END r1_rd_out[17] - PIN r1_rd_out[18] + END r0_rd_out[27] + PIN r0_rd_out[28] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 5.166 6.705 5.184 ; + RECT 5.391 9.589 5.409 9.643 ; END - END r1_rd_out[18] - PIN r1_rd_out[19] + END r0_rd_out[28] + PIN r0_rd_out[29] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.047 5.166 7.065 5.184 ; + RECT 5.823 9.589 5.841 9.643 ; END - END r1_rd_out[19] + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 9.589 6.273 9.643 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 9.589 6.705 9.643 ; + END + END r0_rd_out[31] PIN w0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.716 0.024 1.740 ; + RECT 0.000 5.652 0.072 5.676 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -560,7 +596,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.004 0.024 2.028 ; + RECT 0.000 6.324 0.072 6.348 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -569,7 +605,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.292 0.024 2.316 ; + RECT 0.000 6.996 0.072 7.020 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -578,7 +614,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 1.716 10.368 1.740 ; + RECT 9.571 5.652 9.643 5.676 ; END END w0_addr_in[3] PIN w0_addr_in[4] @@ -587,25 +623,16 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.004 10.368 2.028 ; + RECT 9.571 6.324 9.643 6.348 ; END END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 10.344 2.292 10.368 2.316 ; - END - END w0_addr_in[5] PIN r0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; + RECT 0.000 7.668 0.072 7.692 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -614,7 +641,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.868 0.024 2.892 ; + RECT 0.000 8.340 0.072 8.364 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -623,7 +650,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.156 0.024 3.180 ; + RECT 0.000 9.012 0.072 9.036 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -632,7 +659,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.580 10.368 2.604 ; + RECT 9.571 6.996 9.643 7.020 ; END END r0_addr_in[3] PIN r0_addr_in[4] @@ -641,79 +668,16 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 10.344 2.868 10.368 2.892 ; + RECT 9.571 7.668 9.643 7.692 ; END END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 10.344 3.156 10.368 3.180 ; - END - END r0_addr_in[5] - PIN r1_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.444 0.024 3.468 ; - END - END r1_addr_in[0] - PIN r1_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; - END - END r1_addr_in[1] - PIN r1_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.020 0.024 4.044 ; - END - END r1_addr_in[2] - PIN r1_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 10.344 3.444 10.368 3.468 ; - END - END r1_addr_in[3] - PIN r1_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 10.344 3.732 10.368 3.756 ; - END - END r1_addr_in[4] - PIN r1_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 10.344 4.020 10.368 4.044 ; - END - END r1_addr_in[5] PIN w0_we_in DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.407 5.166 7.425 5.184 ; + RECT 7.119 9.589 7.137 9.643 ; END END w0_we_in PIN w0_ce_in @@ -722,7 +686,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.767 5.166 7.785 5.184 ; + RECT 7.551 9.589 7.569 9.643 ; END END w0_ce_in PIN w0_clk @@ -731,7 +695,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.127 5.166 8.145 5.184 ; + RECT 7.983 9.589 8.001 9.643 ; END END w0_clk PIN r0_ce_in @@ -740,7 +704,7 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.487 5.166 8.505 5.184 ; + RECT 8.415 9.589 8.433 9.643 ; END END r0_ce_in PIN r0_clk @@ -749,39 +713,27 @@ MACRO fakeram_20x64_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.847 5.166 8.865 5.184 ; + RECT 8.847 9.589 8.865 9.643 ; END END r0_clk - PIN r1_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.207 5.166 9.225 5.184 ; - END - END r1_ce_in - PIN r1_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.567 5.166 9.585 5.184 ; - END - END r1_clk PIN VSS DIRECTION INOUT ; USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; END END VSS PIN VDD @@ -789,25 +741,31 @@ MACRO fakeram_20x64_2r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 10.260 0.288 ; - RECT 0.108 0.960 10.260 1.056 ; - RECT 0.108 1.728 10.260 1.824 ; - RECT 0.108 2.496 10.260 2.592 ; - RECT 0.108 3.264 10.260 3.360 ; - RECT 0.108 4.032 10.260 4.128 ; - RECT 0.108 4.800 10.260 4.896 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; END END VDD OBS LAYER M1 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 9.643 ; LAYER M2 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 9.643 ; LAYER M3 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 9.643 ; LAYER M4 ; - RECT 0 0 10.368 5.184 ; + RECT 0 0 9.643 9.643 ; END -END fakeram_20x64_2r1w +END fakeram_32x32_1r1w END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_40x512_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_40x512_1r1w.lef new file mode 100644 index 0000000..03c96fb --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_40x512_1r1w.lef @@ -0,0 +1,1193 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_40x512_1r1w + FOREIGN fakeram_40x512_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 12.053 BY 89.057 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.748 0.072 41.772 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 0.276 12.053 0.300 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 4.884 12.053 4.908 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 9.492 12.053 9.516 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 14.100 12.053 14.124 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 18.708 12.053 18.732 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 23.316 12.053 23.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 27.924 12.053 27.948 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 32.532 12.053 32.556 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 37.140 12.053 37.164 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 41.748 12.053 41.772 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[39] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 89.003 0.225 89.057 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 89.003 0.657 89.057 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 89.003 1.089 89.057 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 89.003 1.521 89.057 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 89.003 1.953 89.057 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 89.003 2.385 89.057 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 89.003 2.817 89.057 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 89.003 3.249 89.057 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 89.003 3.681 89.057 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 89.003 4.113 89.057 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 89.003 4.545 89.057 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 89.003 4.977 89.057 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 89.003 5.409 89.057 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.823 89.003 5.841 89.057 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 89.003 6.273 89.057 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 89.003 6.705 89.057 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 89.003 7.137 89.057 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.551 89.003 7.569 89.057 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 89.003 8.001 89.057 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 89.003 8.433 89.057 ; + END + END r0_rd_out[39] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.356 0.072 46.380 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.964 0.072 50.988 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.572 0.072 55.596 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.180 0.072 60.204 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.788 0.072 64.812 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 46.356 12.053 46.380 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 50.964 12.053 50.988 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 55.572 12.053 55.596 ; + END + END w0_addr_in[7] + PIN w0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 60.180 12.053 60.204 ; + END + END w0_addr_in[8] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.396 0.072 69.420 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.004 0.072 74.028 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.612 0.072 78.636 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.220 0.072 83.244 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.828 0.072 87.852 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 64.788 12.053 64.812 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 69.396 12.053 69.420 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 74.004 12.053 74.028 ; + END + END r0_addr_in[7] + PIN r0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 11.981 78.612 12.053 78.636 ; + END + END r0_addr_in[8] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 89.003 8.865 89.057 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 89.003 9.297 89.057 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 89.003 9.729 89.057 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.143 89.003 10.161 89.057 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 89.003 10.593 89.057 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 11.837 0.336 ; + RECT 0.216 1.008 11.837 1.104 ; + RECT 0.216 1.776 11.837 1.872 ; + RECT 0.216 2.544 11.837 2.640 ; + RECT 0.216 3.312 11.837 3.408 ; + RECT 0.216 4.080 11.837 4.176 ; + RECT 0.216 4.848 11.837 4.944 ; + RECT 0.216 5.616 11.837 5.712 ; + RECT 0.216 6.384 11.837 6.480 ; + RECT 0.216 7.152 11.837 7.248 ; + RECT 0.216 7.920 11.837 8.016 ; + RECT 0.216 8.688 11.837 8.784 ; + RECT 0.216 9.456 11.837 9.552 ; + RECT 0.216 10.224 11.837 10.320 ; + RECT 0.216 10.992 11.837 11.088 ; + RECT 0.216 11.760 11.837 11.856 ; + RECT 0.216 12.528 11.837 12.624 ; + RECT 0.216 13.296 11.837 13.392 ; + RECT 0.216 14.064 11.837 14.160 ; + RECT 0.216 14.832 11.837 14.928 ; + RECT 0.216 15.600 11.837 15.696 ; + RECT 0.216 16.368 11.837 16.464 ; + RECT 0.216 17.136 11.837 17.232 ; + RECT 0.216 17.904 11.837 18.000 ; + RECT 0.216 18.672 11.837 18.768 ; + RECT 0.216 19.440 11.837 19.536 ; + RECT 0.216 20.208 11.837 20.304 ; + RECT 0.216 20.976 11.837 21.072 ; + RECT 0.216 21.744 11.837 21.840 ; + RECT 0.216 22.512 11.837 22.608 ; + RECT 0.216 23.280 11.837 23.376 ; + RECT 0.216 24.048 11.837 24.144 ; + RECT 0.216 24.816 11.837 24.912 ; + RECT 0.216 25.584 11.837 25.680 ; + RECT 0.216 26.352 11.837 26.448 ; + RECT 0.216 27.120 11.837 27.216 ; + RECT 0.216 27.888 11.837 27.984 ; + RECT 0.216 28.656 11.837 28.752 ; + RECT 0.216 29.424 11.837 29.520 ; + RECT 0.216 30.192 11.837 30.288 ; + RECT 0.216 30.960 11.837 31.056 ; + RECT 0.216 31.728 11.837 31.824 ; + RECT 0.216 32.496 11.837 32.592 ; + RECT 0.216 33.264 11.837 33.360 ; + RECT 0.216 34.032 11.837 34.128 ; + RECT 0.216 34.800 11.837 34.896 ; + RECT 0.216 35.568 11.837 35.664 ; + RECT 0.216 36.336 11.837 36.432 ; + RECT 0.216 37.104 11.837 37.200 ; + RECT 0.216 37.872 11.837 37.968 ; + RECT 0.216 38.640 11.837 38.736 ; + RECT 0.216 39.408 11.837 39.504 ; + RECT 0.216 40.176 11.837 40.272 ; + RECT 0.216 40.944 11.837 41.040 ; + RECT 0.216 41.712 11.837 41.808 ; + RECT 0.216 42.480 11.837 42.576 ; + RECT 0.216 43.248 11.837 43.344 ; + RECT 0.216 44.016 11.837 44.112 ; + RECT 0.216 44.784 11.837 44.880 ; + RECT 0.216 45.552 11.837 45.648 ; + RECT 0.216 46.320 11.837 46.416 ; + RECT 0.216 47.088 11.837 47.184 ; + RECT 0.216 47.856 11.837 47.952 ; + RECT 0.216 48.624 11.837 48.720 ; + RECT 0.216 49.392 11.837 49.488 ; + RECT 0.216 50.160 11.837 50.256 ; + RECT 0.216 50.928 11.837 51.024 ; + RECT 0.216 51.696 11.837 51.792 ; + RECT 0.216 52.464 11.837 52.560 ; + RECT 0.216 53.232 11.837 53.328 ; + RECT 0.216 54.000 11.837 54.096 ; + RECT 0.216 54.768 11.837 54.864 ; + RECT 0.216 55.536 11.837 55.632 ; + RECT 0.216 56.304 11.837 56.400 ; + RECT 0.216 57.072 11.837 57.168 ; + RECT 0.216 57.840 11.837 57.936 ; + RECT 0.216 58.608 11.837 58.704 ; + RECT 0.216 59.376 11.837 59.472 ; + RECT 0.216 60.144 11.837 60.240 ; + RECT 0.216 60.912 11.837 61.008 ; + RECT 0.216 61.680 11.837 61.776 ; + RECT 0.216 62.448 11.837 62.544 ; + RECT 0.216 63.216 11.837 63.312 ; + RECT 0.216 63.984 11.837 64.080 ; + RECT 0.216 64.752 11.837 64.848 ; + RECT 0.216 65.520 11.837 65.616 ; + RECT 0.216 66.288 11.837 66.384 ; + RECT 0.216 67.056 11.837 67.152 ; + RECT 0.216 67.824 11.837 67.920 ; + RECT 0.216 68.592 11.837 68.688 ; + RECT 0.216 69.360 11.837 69.456 ; + RECT 0.216 70.128 11.837 70.224 ; + RECT 0.216 70.896 11.837 70.992 ; + RECT 0.216 71.664 11.837 71.760 ; + RECT 0.216 72.432 11.837 72.528 ; + RECT 0.216 73.200 11.837 73.296 ; + RECT 0.216 73.968 11.837 74.064 ; + RECT 0.216 74.736 11.837 74.832 ; + RECT 0.216 75.504 11.837 75.600 ; + RECT 0.216 76.272 11.837 76.368 ; + RECT 0.216 77.040 11.837 77.136 ; + RECT 0.216 77.808 11.837 77.904 ; + RECT 0.216 78.576 11.837 78.672 ; + RECT 0.216 79.344 11.837 79.440 ; + RECT 0.216 80.112 11.837 80.208 ; + RECT 0.216 80.880 11.837 80.976 ; + RECT 0.216 81.648 11.837 81.744 ; + RECT 0.216 82.416 11.837 82.512 ; + RECT 0.216 83.184 11.837 83.280 ; + RECT 0.216 83.952 11.837 84.048 ; + RECT 0.216 84.720 11.837 84.816 ; + RECT 0.216 85.488 11.837 85.584 ; + RECT 0.216 86.256 11.837 86.352 ; + RECT 0.216 87.024 11.837 87.120 ; + RECT 0.216 87.792 11.837 87.888 ; + RECT 0.216 88.560 11.837 88.656 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 11.837 0.336 ; + RECT 0.216 1.008 11.837 1.104 ; + RECT 0.216 1.776 11.837 1.872 ; + RECT 0.216 2.544 11.837 2.640 ; + RECT 0.216 3.312 11.837 3.408 ; + RECT 0.216 4.080 11.837 4.176 ; + RECT 0.216 4.848 11.837 4.944 ; + RECT 0.216 5.616 11.837 5.712 ; + RECT 0.216 6.384 11.837 6.480 ; + RECT 0.216 7.152 11.837 7.248 ; + RECT 0.216 7.920 11.837 8.016 ; + RECT 0.216 8.688 11.837 8.784 ; + RECT 0.216 9.456 11.837 9.552 ; + RECT 0.216 10.224 11.837 10.320 ; + RECT 0.216 10.992 11.837 11.088 ; + RECT 0.216 11.760 11.837 11.856 ; + RECT 0.216 12.528 11.837 12.624 ; + RECT 0.216 13.296 11.837 13.392 ; + RECT 0.216 14.064 11.837 14.160 ; + RECT 0.216 14.832 11.837 14.928 ; + RECT 0.216 15.600 11.837 15.696 ; + RECT 0.216 16.368 11.837 16.464 ; + RECT 0.216 17.136 11.837 17.232 ; + RECT 0.216 17.904 11.837 18.000 ; + RECT 0.216 18.672 11.837 18.768 ; + RECT 0.216 19.440 11.837 19.536 ; + RECT 0.216 20.208 11.837 20.304 ; + RECT 0.216 20.976 11.837 21.072 ; + RECT 0.216 21.744 11.837 21.840 ; + RECT 0.216 22.512 11.837 22.608 ; + RECT 0.216 23.280 11.837 23.376 ; + RECT 0.216 24.048 11.837 24.144 ; + RECT 0.216 24.816 11.837 24.912 ; + RECT 0.216 25.584 11.837 25.680 ; + RECT 0.216 26.352 11.837 26.448 ; + RECT 0.216 27.120 11.837 27.216 ; + RECT 0.216 27.888 11.837 27.984 ; + RECT 0.216 28.656 11.837 28.752 ; + RECT 0.216 29.424 11.837 29.520 ; + RECT 0.216 30.192 11.837 30.288 ; + RECT 0.216 30.960 11.837 31.056 ; + RECT 0.216 31.728 11.837 31.824 ; + RECT 0.216 32.496 11.837 32.592 ; + RECT 0.216 33.264 11.837 33.360 ; + RECT 0.216 34.032 11.837 34.128 ; + RECT 0.216 34.800 11.837 34.896 ; + RECT 0.216 35.568 11.837 35.664 ; + RECT 0.216 36.336 11.837 36.432 ; + RECT 0.216 37.104 11.837 37.200 ; + RECT 0.216 37.872 11.837 37.968 ; + RECT 0.216 38.640 11.837 38.736 ; + RECT 0.216 39.408 11.837 39.504 ; + RECT 0.216 40.176 11.837 40.272 ; + RECT 0.216 40.944 11.837 41.040 ; + RECT 0.216 41.712 11.837 41.808 ; + RECT 0.216 42.480 11.837 42.576 ; + RECT 0.216 43.248 11.837 43.344 ; + RECT 0.216 44.016 11.837 44.112 ; + RECT 0.216 44.784 11.837 44.880 ; + RECT 0.216 45.552 11.837 45.648 ; + RECT 0.216 46.320 11.837 46.416 ; + RECT 0.216 47.088 11.837 47.184 ; + RECT 0.216 47.856 11.837 47.952 ; + RECT 0.216 48.624 11.837 48.720 ; + RECT 0.216 49.392 11.837 49.488 ; + RECT 0.216 50.160 11.837 50.256 ; + RECT 0.216 50.928 11.837 51.024 ; + RECT 0.216 51.696 11.837 51.792 ; + RECT 0.216 52.464 11.837 52.560 ; + RECT 0.216 53.232 11.837 53.328 ; + RECT 0.216 54.000 11.837 54.096 ; + RECT 0.216 54.768 11.837 54.864 ; + RECT 0.216 55.536 11.837 55.632 ; + RECT 0.216 56.304 11.837 56.400 ; + RECT 0.216 57.072 11.837 57.168 ; + RECT 0.216 57.840 11.837 57.936 ; + RECT 0.216 58.608 11.837 58.704 ; + RECT 0.216 59.376 11.837 59.472 ; + RECT 0.216 60.144 11.837 60.240 ; + RECT 0.216 60.912 11.837 61.008 ; + RECT 0.216 61.680 11.837 61.776 ; + RECT 0.216 62.448 11.837 62.544 ; + RECT 0.216 63.216 11.837 63.312 ; + RECT 0.216 63.984 11.837 64.080 ; + RECT 0.216 64.752 11.837 64.848 ; + RECT 0.216 65.520 11.837 65.616 ; + RECT 0.216 66.288 11.837 66.384 ; + RECT 0.216 67.056 11.837 67.152 ; + RECT 0.216 67.824 11.837 67.920 ; + RECT 0.216 68.592 11.837 68.688 ; + RECT 0.216 69.360 11.837 69.456 ; + RECT 0.216 70.128 11.837 70.224 ; + RECT 0.216 70.896 11.837 70.992 ; + RECT 0.216 71.664 11.837 71.760 ; + RECT 0.216 72.432 11.837 72.528 ; + RECT 0.216 73.200 11.837 73.296 ; + RECT 0.216 73.968 11.837 74.064 ; + RECT 0.216 74.736 11.837 74.832 ; + RECT 0.216 75.504 11.837 75.600 ; + RECT 0.216 76.272 11.837 76.368 ; + RECT 0.216 77.040 11.837 77.136 ; + RECT 0.216 77.808 11.837 77.904 ; + RECT 0.216 78.576 11.837 78.672 ; + RECT 0.216 79.344 11.837 79.440 ; + RECT 0.216 80.112 11.837 80.208 ; + RECT 0.216 80.880 11.837 80.976 ; + RECT 0.216 81.648 11.837 81.744 ; + RECT 0.216 82.416 11.837 82.512 ; + RECT 0.216 83.184 11.837 83.280 ; + RECT 0.216 83.952 11.837 84.048 ; + RECT 0.216 84.720 11.837 84.816 ; + RECT 0.216 85.488 11.837 85.584 ; + RECT 0.216 86.256 11.837 86.352 ; + RECT 0.216 87.024 11.837 87.120 ; + RECT 0.216 87.792 11.837 87.888 ; + RECT 0.216 88.560 11.837 88.656 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 12.053 89.057 ; + LAYER M2 ; + RECT 0 0 12.053 89.057 ; + LAYER M3 ; + RECT 0 0 12.053 89.057 ; + LAYER M4 ; + RECT 0 0 12.053 89.057 ; + END +END fakeram_40x512_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_4x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_4x256_1r1w.lef new file mode 100644 index 0000000..8c6f523 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_4x256_1r1w.lef @@ -0,0 +1,407 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_4x256_1r1w + FOREIGN fakeram_4x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 43.190 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.475 0.000 2.493 0.054 ; + END + END w0_wd_in[3] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.011 0.000 7.029 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 43.136 0.225 43.190 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 43.136 1.521 43.190 ; + END + END r0_rd_out[3] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.980 9.643 5.004 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.684 9.643 9.708 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 14.388 9.643 14.412 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 19.092 9.643 19.116 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.204 0.072 33.228 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.908 0.072 37.932 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 23.796 9.643 23.820 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 28.500 9.643 28.524 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 33.204 9.643 33.228 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 37.908 9.643 37.932 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 43.136 2.817 43.190 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 43.136 4.113 43.190 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 43.136 5.409 43.190 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 43.136 6.705 43.190 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 43.136 8.001 43.190 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 43.190 ; + LAYER M2 ; + RECT 0 0 9.643 43.190 ; + LAYER M3 ; + RECT 0 0 9.643 43.190 ; + LAYER M4 ; + RECT 0 0 9.643 43.190 ; + END +END fakeram_4x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_64x128_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_64x128_1r1w.lef new file mode 100644 index 0000000..b575aa1 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_64x128_1r1w.lef @@ -0,0 +1,1427 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x128_1r1w + FOREIGN fakeram_64x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.285 BY 26.785 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.380 0.072 1.404 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.484 0.072 2.508 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.796 0.072 5.820 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.420 0.072 12.444 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.628 0.072 14.652 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 0.276 19.285 0.300 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 1.380 19.285 1.404 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 2.484 19.285 2.508 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 3.588 19.285 3.612 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 4.692 19.285 4.716 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 5.796 19.285 5.820 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 6.900 19.285 6.924 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 8.004 19.285 8.028 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 9.108 19.285 9.132 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 10.212 19.285 10.236 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 11.316 19.285 11.340 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 12.420 19.285 12.444 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 13.524 19.285 13.548 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 14.628 19.285 14.652 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 15.732 19.285 15.756 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 16.836 19.285 16.860 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[63] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 26.731 0.225 26.785 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 26.731 0.729 26.785 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 26.731 1.233 26.785 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 26.731 1.737 26.785 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 26.731 2.241 26.785 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 26.731 2.745 26.785 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 26.731 3.249 26.785 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 26.731 3.753 26.785 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 26.731 4.257 26.785 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 26.731 4.761 26.785 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 26.731 5.265 26.785 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 26.731 5.769 26.785 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 26.731 6.273 26.785 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 26.731 6.777 26.785 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 26.731 7.281 26.785 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 26.731 7.785 26.785 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 26.731 8.289 26.785 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 26.731 8.793 26.785 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 26.731 9.297 26.785 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 26.731 9.801 26.785 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 26.731 10.305 26.785 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 26.731 10.809 26.785 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 26.731 11.313 26.785 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 26.731 11.817 26.785 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 26.731 12.321 26.785 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 26.731 12.825 26.785 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 26.731 13.329 26.785 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 26.731 13.833 26.785 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 26.731 14.337 26.785 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 26.731 14.841 26.785 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 26.731 15.345 26.785 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 26.731 15.849 26.785 ; + END + END r0_rd_out[63] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.044 0.072 19.068 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.252 0.072 21.276 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 17.940 19.285 17.964 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 19.044 19.285 19.068 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 20.148 19.285 20.172 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.564 0.072 24.588 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.668 0.072 25.692 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 21.252 19.285 21.276 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 22.356 19.285 22.380 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 23.460 19.285 23.484 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 26.731 16.353 26.785 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 26.731 16.857 26.785 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 26.731 17.361 26.785 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 26.731 17.865 26.785 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 26.731 18.369 26.785 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + RECT 0.216 16.368 19.069 16.464 ; + RECT 0.216 17.136 19.069 17.232 ; + RECT 0.216 17.904 19.069 18.000 ; + RECT 0.216 18.672 19.069 18.768 ; + RECT 0.216 19.440 19.069 19.536 ; + RECT 0.216 20.208 19.069 20.304 ; + RECT 0.216 20.976 19.069 21.072 ; + RECT 0.216 21.744 19.069 21.840 ; + RECT 0.216 22.512 19.069 22.608 ; + RECT 0.216 23.280 19.069 23.376 ; + RECT 0.216 24.048 19.069 24.144 ; + RECT 0.216 24.816 19.069 24.912 ; + RECT 0.216 25.584 19.069 25.680 ; + RECT 0.216 26.352 19.069 26.448 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + RECT 0.216 16.368 19.069 16.464 ; + RECT 0.216 17.136 19.069 17.232 ; + RECT 0.216 17.904 19.069 18.000 ; + RECT 0.216 18.672 19.069 18.768 ; + RECT 0.216 19.440 19.069 19.536 ; + RECT 0.216 20.208 19.069 20.304 ; + RECT 0.216 20.976 19.069 21.072 ; + RECT 0.216 21.744 19.069 21.840 ; + RECT 0.216 22.512 19.069 22.608 ; + RECT 0.216 23.280 19.069 23.376 ; + RECT 0.216 24.048 19.069 24.144 ; + RECT 0.216 24.816 19.069 24.912 ; + RECT 0.216 25.584 19.069 25.680 ; + RECT 0.216 26.352 19.069 26.448 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.285 26.785 ; + LAYER M2 ; + RECT 0 0 19.285 26.785 ; + LAYER M3 ; + RECT 0 0 19.285 26.785 ; + LAYER M4 ; + RECT 0 0 19.285 26.785 ; + END +END fakeram_64x128_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_64x16_1r1w.lef similarity index 58% rename from designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef rename to designs/asap7/NVDLA/sram/lef/fakeram_64x16_1r1w.lef index 9dd70c8..89d5a41 100644 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef +++ b/designs/asap7/NVDLA/sram/lef/fakeram_64x16_1r1w.lef @@ -1,9 +1,9 @@ VERSION 5.7 ; BUSBITCHARS "[]" ; -MACRO fakeram_32x128_2r1w - FOREIGN fakeram_32x128_2r1w 0 0 ; +MACRO fakeram_64x16_1r1w + FOREIGN fakeram_64x16_1r1w 0 0 ; SYMMETRY X Y R90 ; - SIZE 16.589 BY 10.368 ; + SIZE 19.285 BY 9.643 ; CLASS BLOCK ; PIN w0_wd_in[0] DIRECTION INPUT ; @@ -11,7 +11,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; + RECT 0.000 0.276 0.072 0.300 ; END END w0_wd_in[0] PIN w0_wd_in[1] @@ -20,7 +20,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 0.756 0.024 0.780 ; + RECT 0.000 0.708 0.072 0.732 ; END END w0_wd_in[1] PIN w0_wd_in[2] @@ -29,7 +29,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.236 0.024 1.260 ; + RECT 0.000 1.140 0.072 1.164 ; END END w0_wd_in[2] PIN w0_wd_in[3] @@ -38,7 +38,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 1.716 0.024 1.740 ; + RECT 0.000 1.572 0.072 1.596 ; END END w0_wd_in[3] PIN w0_wd_in[4] @@ -47,7 +47,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.196 0.024 2.220 ; + RECT 0.000 2.004 0.072 2.028 ; END END w0_wd_in[4] PIN w0_wd_in[5] @@ -56,7 +56,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 2.676 0.024 2.700 ; + RECT 0.000 2.436 0.072 2.460 ; END END w0_wd_in[5] PIN w0_wd_in[6] @@ -65,7 +65,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.156 0.024 3.180 ; + RECT 0.000 2.868 0.072 2.892 ; END END w0_wd_in[6] PIN w0_wd_in[7] @@ -74,7 +74,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 3.636 0.024 3.660 ; + RECT 0.000 3.300 0.072 3.324 ; END END w0_wd_in[7] PIN w0_wd_in[8] @@ -83,7 +83,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 0.276 16.589 0.300 ; + RECT 0.000 3.732 0.072 3.756 ; END END w0_wd_in[8] PIN w0_wd_in[9] @@ -92,7 +92,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 0.756 16.589 0.780 ; + RECT 0.000 4.164 0.072 4.188 ; END END w0_wd_in[9] PIN w0_wd_in[10] @@ -101,7 +101,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 1.236 16.589 1.260 ; + RECT 0.000 4.596 0.072 4.620 ; END END w0_wd_in[10] PIN w0_wd_in[11] @@ -110,7 +110,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 1.716 16.589 1.740 ; + RECT 0.000 5.028 0.072 5.052 ; END END w0_wd_in[11] PIN w0_wd_in[12] @@ -119,7 +119,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 2.196 16.589 2.220 ; + RECT 0.000 5.460 0.072 5.484 ; END END w0_wd_in[12] PIN w0_wd_in[13] @@ -128,7 +128,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 2.676 16.589 2.700 ; + RECT 0.000 5.892 0.072 5.916 ; END END w0_wd_in[13] PIN w0_wd_in[14] @@ -137,7 +137,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 3.156 16.589 3.180 ; + RECT 0.000 6.324 0.072 6.348 ; END END w0_wd_in[14] PIN w0_wd_in[15] @@ -146,160 +146,448 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 16.565 3.636 16.589 3.660 ; + RECT 0.000 6.756 0.072 6.780 ; END END w0_wd_in[15] PIN w0_wd_in[16] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; + LAYER M4 ; + RECT 19.213 0.276 19.285 0.300 ; END END w0_wd_in[16] PIN w0_wd_in[17] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.531 0.000 0.549 0.018 ; + LAYER M4 ; + RECT 19.213 0.708 19.285 0.732 ; END END w0_wd_in[17] PIN w0_wd_in[18] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 0.855 0.000 0.873 0.018 ; + LAYER M4 ; + RECT 19.213 1.140 19.285 1.164 ; END END w0_wd_in[18] PIN w0_wd_in[19] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 1.179 0.000 1.197 0.018 ; + LAYER M4 ; + RECT 19.213 1.572 19.285 1.596 ; END END w0_wd_in[19] PIN w0_wd_in[20] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 1.503 0.000 1.521 0.018 ; + LAYER M4 ; + RECT 19.213 2.004 19.285 2.028 ; END END w0_wd_in[20] PIN w0_wd_in[21] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 1.827 0.000 1.845 0.018 ; + LAYER M4 ; + RECT 19.213 2.436 19.285 2.460 ; END END w0_wd_in[21] PIN w0_wd_in[22] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 2.151 0.000 2.169 0.018 ; + LAYER M4 ; + RECT 19.213 2.868 19.285 2.892 ; END END w0_wd_in[22] PIN w0_wd_in[23] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 2.475 0.000 2.493 0.018 ; + LAYER M4 ; + RECT 19.213 3.300 19.285 3.324 ; END END w0_wd_in[23] PIN w0_wd_in[24] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 2.799 0.000 2.817 0.018 ; + LAYER M4 ; + RECT 19.213 3.732 19.285 3.756 ; END END w0_wd_in[24] PIN w0_wd_in[25] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 3.123 0.000 3.141 0.018 ; + LAYER M4 ; + RECT 19.213 4.164 19.285 4.188 ; END END w0_wd_in[25] PIN w0_wd_in[26] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 3.447 0.000 3.465 0.018 ; + LAYER M4 ; + RECT 19.213 4.596 19.285 4.620 ; END END w0_wd_in[26] PIN w0_wd_in[27] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 3.771 0.000 3.789 0.018 ; + LAYER M4 ; + RECT 19.213 5.028 19.285 5.052 ; END END w0_wd_in[27] PIN w0_wd_in[28] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 4.095 0.000 4.113 0.018 ; + LAYER M4 ; + RECT 19.213 5.460 19.285 5.484 ; END END w0_wd_in[28] PIN w0_wd_in[29] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 4.419 0.000 4.437 0.018 ; + LAYER M4 ; + RECT 19.213 5.892 19.285 5.916 ; END END w0_wd_in[29] PIN w0_wd_in[30] - DIRECTION OUTPUT ; + DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT - LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; + LAYER M4 ; + RECT 19.213 6.324 19.285 6.348 ; END END w0_wd_in[30] PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 6.756 19.285 6.780 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.067 0.000 5.085 0.018 ; + RECT 0.207 0.000 0.225 0.054 ; END - END w0_wd_in[31] + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[63] PIN r0_rd_out[0] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.391 0.000 5.409 0.018 ; + RECT 9.423 0.000 9.441 0.054 ; END END r0_rd_out[0] PIN r0_rd_out[1] @@ -308,7 +596,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.715 0.000 5.733 0.018 ; + RECT 9.711 0.000 9.729 0.054 ; END END r0_rd_out[1] PIN r0_rd_out[2] @@ -317,7 +605,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.039 0.000 6.057 0.018 ; + RECT 9.999 0.000 10.017 0.054 ; END END r0_rd_out[2] PIN r0_rd_out[3] @@ -326,7 +614,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.363 0.000 6.381 0.018 ; + RECT 10.287 0.000 10.305 0.054 ; END END r0_rd_out[3] PIN r0_rd_out[4] @@ -335,7 +623,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.687 0.000 6.705 0.018 ; + RECT 10.575 0.000 10.593 0.054 ; END END r0_rd_out[4] PIN r0_rd_out[5] @@ -344,7 +632,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.011 0.000 7.029 0.018 ; + RECT 10.863 0.000 10.881 0.054 ; END END r0_rd_out[5] PIN r0_rd_out[6] @@ -353,7 +641,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 0.000 7.353 0.018 ; + RECT 11.151 0.000 11.169 0.054 ; END END r0_rd_out[6] PIN r0_rd_out[7] @@ -362,7 +650,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.659 0.000 7.677 0.018 ; + RECT 11.439 0.000 11.457 0.054 ; END END r0_rd_out[7] PIN r0_rd_out[8] @@ -371,7 +659,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.983 0.000 8.001 0.018 ; + RECT 11.727 0.000 11.745 0.054 ; END END r0_rd_out[8] PIN r0_rd_out[9] @@ -380,7 +668,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.307 0.000 8.325 0.018 ; + RECT 12.015 0.000 12.033 0.054 ; END END r0_rd_out[9] PIN r0_rd_out[10] @@ -389,7 +677,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.631 0.000 8.649 0.018 ; + RECT 12.303 0.000 12.321 0.054 ; END END r0_rd_out[10] PIN r0_rd_out[11] @@ -398,7 +686,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.955 0.000 8.973 0.018 ; + RECT 12.591 0.000 12.609 0.054 ; END END r0_rd_out[11] PIN r0_rd_out[12] @@ -407,7 +695,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; + RECT 12.879 0.000 12.897 0.054 ; END END r0_rd_out[12] PIN r0_rd_out[13] @@ -416,7 +704,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.603 0.000 9.621 0.018 ; + RECT 13.167 0.000 13.185 0.054 ; END END r0_rd_out[13] PIN r0_rd_out[14] @@ -425,7 +713,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.927 0.000 9.945 0.018 ; + RECT 13.455 0.000 13.473 0.054 ; END END r0_rd_out[14] PIN r0_rd_out[15] @@ -434,7 +722,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.251 0.000 10.269 0.018 ; + RECT 13.743 0.000 13.761 0.054 ; END END r0_rd_out[15] PIN r0_rd_out[16] @@ -443,7 +731,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.207 10.350 0.225 10.368 ; + RECT 14.031 0.000 14.049 0.054 ; END END r0_rd_out[16] PIN r0_rd_out[17] @@ -452,7 +740,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.603 10.350 0.621 10.368 ; + RECT 14.319 0.000 14.337 0.054 ; END END r0_rd_out[17] PIN r0_rd_out[18] @@ -461,7 +749,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 0.999 10.350 1.017 10.368 ; + RECT 14.607 0.000 14.625 0.054 ; END END r0_rd_out[18] PIN r0_rd_out[19] @@ -470,7 +758,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.395 10.350 1.413 10.368 ; + RECT 14.895 0.000 14.913 0.054 ; END END r0_rd_out[19] PIN r0_rd_out[20] @@ -479,7 +767,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 1.791 10.350 1.809 10.368 ; + RECT 15.183 0.000 15.201 0.054 ; END END r0_rd_out[20] PIN r0_rd_out[21] @@ -488,7 +776,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.187 10.350 2.205 10.368 ; + RECT 15.471 0.000 15.489 0.054 ; END END r0_rd_out[21] PIN r0_rd_out[22] @@ -497,7 +785,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.583 10.350 2.601 10.368 ; + RECT 15.759 0.000 15.777 0.054 ; END END r0_rd_out[22] PIN r0_rd_out[23] @@ -506,7 +794,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 2.979 10.350 2.997 10.368 ; + RECT 16.047 0.000 16.065 0.054 ; END END r0_rd_out[23] PIN r0_rd_out[24] @@ -515,7 +803,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.375 10.350 3.393 10.368 ; + RECT 16.335 0.000 16.353 0.054 ; END END r0_rd_out[24] PIN r0_rd_out[25] @@ -524,7 +812,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 3.771 10.350 3.789 10.368 ; + RECT 16.623 0.000 16.641 0.054 ; END END r0_rd_out[25] PIN r0_rd_out[26] @@ -533,7 +821,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.167 10.350 4.185 10.368 ; + RECT 16.911 0.000 16.929 0.054 ; END END r0_rd_out[26] PIN r0_rd_out[27] @@ -542,7 +830,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.563 10.350 4.581 10.368 ; + RECT 17.199 0.000 17.217 0.054 ; END END r0_rd_out[27] PIN r0_rd_out[28] @@ -551,7 +839,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 4.959 10.350 4.977 10.368 ; + RECT 17.487 0.000 17.505 0.054 ; END END r0_rd_out[28] PIN r0_rd_out[29] @@ -560,7 +848,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.355 10.350 5.373 10.368 ; + RECT 17.775 0.000 17.793 0.054 ; END END r0_rd_out[29] PIN r0_rd_out[30] @@ -569,7 +857,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 5.751 10.350 5.769 10.368 ; + RECT 18.063 0.000 18.081 0.054 ; END END r0_rd_out[30] PIN r0_rd_out[31] @@ -578,304 +866,304 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.147 10.350 6.165 10.368 ; + RECT 18.351 0.000 18.369 0.054 ; END END r0_rd_out[31] - PIN r1_rd_out[0] + PIN r0_rd_out[32] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.575 0.000 10.593 0.018 ; + RECT 0.207 9.589 0.225 9.643 ; END - END r1_rd_out[0] - PIN r1_rd_out[1] + END r0_rd_out[32] + PIN r0_rd_out[33] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.899 0.000 10.917 0.018 ; + RECT 0.711 9.589 0.729 9.643 ; END - END r1_rd_out[1] - PIN r1_rd_out[2] + END r0_rd_out[33] + PIN r0_rd_out[34] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.223 0.000 11.241 0.018 ; + RECT 1.215 9.589 1.233 9.643 ; END - END r1_rd_out[2] - PIN r1_rd_out[3] + END r0_rd_out[34] + PIN r0_rd_out[35] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.547 0.000 11.565 0.018 ; + RECT 1.719 9.589 1.737 9.643 ; END - END r1_rd_out[3] - PIN r1_rd_out[4] + END r0_rd_out[35] + PIN r0_rd_out[36] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.871 0.000 11.889 0.018 ; + RECT 2.223 9.589 2.241 9.643 ; END - END r1_rd_out[4] - PIN r1_rd_out[5] + END r0_rd_out[36] + PIN r0_rd_out[37] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.195 0.000 12.213 0.018 ; + RECT 2.727 9.589 2.745 9.643 ; END - END r1_rd_out[5] - PIN r1_rd_out[6] + END r0_rd_out[37] + PIN r0_rd_out[38] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.519 0.000 12.537 0.018 ; + RECT 3.231 9.589 3.249 9.643 ; END - END r1_rd_out[6] - PIN r1_rd_out[7] + END r0_rd_out[38] + PIN r0_rd_out[39] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.843 0.000 12.861 0.018 ; + RECT 3.735 9.589 3.753 9.643 ; END - END r1_rd_out[7] - PIN r1_rd_out[8] + END r0_rd_out[39] + PIN r0_rd_out[40] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.167 0.000 13.185 0.018 ; + RECT 4.239 9.589 4.257 9.643 ; END - END r1_rd_out[8] - PIN r1_rd_out[9] + END r0_rd_out[40] + PIN r0_rd_out[41] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.491 0.000 13.509 0.018 ; + RECT 4.743 9.589 4.761 9.643 ; END - END r1_rd_out[9] - PIN r1_rd_out[10] + END r0_rd_out[41] + PIN r0_rd_out[42] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.815 0.000 13.833 0.018 ; + RECT 5.247 9.589 5.265 9.643 ; END - END r1_rd_out[10] - PIN r1_rd_out[11] + END r0_rd_out[42] + PIN r0_rd_out[43] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.139 0.000 14.157 0.018 ; + RECT 5.751 9.589 5.769 9.643 ; END - END r1_rd_out[11] - PIN r1_rd_out[12] + END r0_rd_out[43] + PIN r0_rd_out[44] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.463 0.000 14.481 0.018 ; + RECT 6.255 9.589 6.273 9.643 ; END - END r1_rd_out[12] - PIN r1_rd_out[13] + END r0_rd_out[44] + PIN r0_rd_out[45] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.787 0.000 14.805 0.018 ; + RECT 6.759 9.589 6.777 9.643 ; END - END r1_rd_out[13] - PIN r1_rd_out[14] + END r0_rd_out[45] + PIN r0_rd_out[46] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.111 0.000 15.129 0.018 ; + RECT 7.263 9.589 7.281 9.643 ; END - END r1_rd_out[14] - PIN r1_rd_out[15] + END r0_rd_out[46] + PIN r0_rd_out[47] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 15.435 0.000 15.453 0.018 ; + RECT 7.767 9.589 7.785 9.643 ; END - END r1_rd_out[15] - PIN r1_rd_out[16] + END r0_rd_out[47] + PIN r0_rd_out[48] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.543 10.350 6.561 10.368 ; + RECT 8.271 9.589 8.289 9.643 ; END - END r1_rd_out[16] - PIN r1_rd_out[17] + END r0_rd_out[48] + PIN r0_rd_out[49] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 6.939 10.350 6.957 10.368 ; + RECT 8.775 9.589 8.793 9.643 ; END - END r1_rd_out[17] - PIN r1_rd_out[18] + END r0_rd_out[49] + PIN r0_rd_out[50] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.335 10.350 7.353 10.368 ; + RECT 9.279 9.589 9.297 9.643 ; END - END r1_rd_out[18] - PIN r1_rd_out[19] + END r0_rd_out[50] + PIN r0_rd_out[51] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 7.731 10.350 7.749 10.368 ; + RECT 9.783 9.589 9.801 9.643 ; END - END r1_rd_out[19] - PIN r1_rd_out[20] + END r0_rd_out[51] + PIN r0_rd_out[52] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.127 10.350 8.145 10.368 ; + RECT 10.287 9.589 10.305 9.643 ; END - END r1_rd_out[20] - PIN r1_rd_out[21] + END r0_rd_out[52] + PIN r0_rd_out[53] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.523 10.350 8.541 10.368 ; + RECT 10.791 9.589 10.809 9.643 ; END - END r1_rd_out[21] - PIN r1_rd_out[22] + END r0_rd_out[53] + PIN r0_rd_out[54] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 8.919 10.350 8.937 10.368 ; + RECT 11.295 9.589 11.313 9.643 ; END - END r1_rd_out[22] - PIN r1_rd_out[23] + END r0_rd_out[54] + PIN r0_rd_out[55] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.315 10.350 9.333 10.368 ; + RECT 11.799 9.589 11.817 9.643 ; END - END r1_rd_out[23] - PIN r1_rd_out[24] + END r0_rd_out[55] + PIN r0_rd_out[56] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 9.711 10.350 9.729 10.368 ; + RECT 12.303 9.589 12.321 9.643 ; END - END r1_rd_out[24] - PIN r1_rd_out[25] + END r0_rd_out[56] + PIN r0_rd_out[57] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.107 10.350 10.125 10.368 ; + RECT 12.807 9.589 12.825 9.643 ; END - END r1_rd_out[25] - PIN r1_rd_out[26] + END r0_rd_out[57] + PIN r0_rd_out[58] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.503 10.350 10.521 10.368 ; + RECT 13.311 9.589 13.329 9.643 ; END - END r1_rd_out[26] - PIN r1_rd_out[27] + END r0_rd_out[58] + PIN r0_rd_out[59] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 10.899 10.350 10.917 10.368 ; + RECT 13.815 9.589 13.833 9.643 ; END - END r1_rd_out[27] - PIN r1_rd_out[28] + END r0_rd_out[59] + PIN r0_rd_out[60] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.295 10.350 11.313 10.368 ; + RECT 14.319 9.589 14.337 9.643 ; END - END r1_rd_out[28] - PIN r1_rd_out[29] + END r0_rd_out[60] + PIN r0_rd_out[61] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 11.691 10.350 11.709 10.368 ; + RECT 14.823 9.589 14.841 9.643 ; END - END r1_rd_out[29] - PIN r1_rd_out[30] + END r0_rd_out[61] + PIN r0_rd_out[62] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.087 10.350 12.105 10.368 ; + RECT 15.327 9.589 15.345 9.643 ; END - END r1_rd_out[30] - PIN r1_rd_out[31] + END r0_rd_out[62] + PIN r0_rd_out[63] DIRECTION OUTPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.483 10.350 12.501 10.368 ; + RECT 15.831 9.589 15.849 9.643 ; END - END r1_rd_out[31] + END r0_rd_out[63] PIN w0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.116 0.024 4.140 ; + RECT 0.000 7.188 0.072 7.212 ; END END w0_addr_in[0] PIN w0_addr_in[1] @@ -884,7 +1172,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 4.596 0.024 4.620 ; + RECT 0.000 7.620 0.072 7.644 ; END END w0_addr_in[1] PIN w0_addr_in[2] @@ -893,7 +1181,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.076 0.024 5.100 ; + RECT 19.213 7.188 19.285 7.212 ; END END w0_addr_in[2] PIN w0_addr_in[3] @@ -902,43 +1190,16 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 5.556 0.024 5.580 ; + RECT 19.213 7.620 19.285 7.644 ; END END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 4.116 16.589 4.140 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 4.596 16.589 4.620 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 5.076 16.589 5.100 ; - END - END w0_addr_in[6] PIN r0_addr_in[0] DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.036 0.024 6.060 ; + RECT 0.000 8.052 0.072 8.076 ; END END r0_addr_in[0] PIN r0_addr_in[1] @@ -947,7 +1208,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.516 0.024 6.540 ; + RECT 0.000 8.484 0.072 8.508 ; END END r0_addr_in[1] PIN r0_addr_in[2] @@ -956,7 +1217,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 6.996 0.024 7.020 ; + RECT 19.213 8.052 19.285 8.076 ; END END r0_addr_in[2] PIN r0_addr_in[3] @@ -965,106 +1226,16 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M4 ; - RECT 0.000 7.476 0.024 7.500 ; + RECT 19.213 8.484 19.285 8.508 ; END END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 5.556 16.589 5.580 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 6.036 16.589 6.060 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 6.516 16.589 6.540 ; - END - END r0_addr_in[6] - PIN r1_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.956 0.024 7.980 ; - END - END r1_addr_in[0] - PIN r1_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.436 0.024 8.460 ; - END - END r1_addr_in[1] - PIN r1_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.916 0.024 8.940 ; - END - END r1_addr_in[2] - PIN r1_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.396 0.024 9.420 ; - END - END r1_addr_in[3] - PIN r1_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 6.996 16.589 7.020 ; - END - END r1_addr_in[4] - PIN r1_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 7.476 16.589 7.500 ; - END - END r1_addr_in[5] - PIN r1_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 16.565 7.956 16.589 7.980 ; - END - END r1_addr_in[6] PIN w0_we_in DIRECTION INPUT ; USE SIGNAL ; SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 12.879 10.350 12.897 10.368 ; + RECT 16.335 9.589 16.353 9.643 ; END END w0_we_in PIN w0_ce_in @@ -1073,7 +1244,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.275 10.350 13.293 10.368 ; + RECT 16.839 9.589 16.857 9.643 ; END END w0_ce_in PIN w0_clk @@ -1082,7 +1253,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 13.671 10.350 13.689 10.368 ; + RECT 17.343 9.589 17.361 9.643 ; END END w0_clk PIN r0_ce_in @@ -1091,7 +1262,7 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.067 10.350 14.085 10.368 ; + RECT 17.847 9.589 17.865 9.643 ; END END r0_ce_in PIN r0_clk @@ -1100,45 +1271,27 @@ MACRO fakeram_32x128_2r1w SHAPE ABUTMENT ; PORT LAYER M3 ; - RECT 14.463 10.350 14.481 10.368 ; + RECT 18.351 9.589 18.369 9.643 ; END END r0_clk - PIN r1_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.859 10.350 14.877 10.368 ; - END - END r1_ce_in - PIN r1_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.255 10.350 15.273 10.368 ; - END - END r1_clk PIN VSS DIRECTION INOUT ; USE GROUND ; PORT LAYER M4 ; - RECT 0.108 0.192 16.481 0.288 ; - RECT 0.108 0.960 16.481 1.056 ; - RECT 0.108 1.728 16.481 1.824 ; - RECT 0.108 2.496 16.481 2.592 ; - RECT 0.108 3.264 16.481 3.360 ; - RECT 0.108 4.032 16.481 4.128 ; - RECT 0.108 4.800 16.481 4.896 ; - RECT 0.108 5.568 16.481 5.664 ; - RECT 0.108 6.336 16.481 6.432 ; - RECT 0.108 7.104 16.481 7.200 ; - RECT 0.108 7.872 16.481 7.968 ; - RECT 0.108 8.640 16.481 8.736 ; - RECT 0.108 9.408 16.481 9.504 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; END END VSS PIN VDD @@ -1146,31 +1299,31 @@ MACRO fakeram_32x128_2r1w USE POWER ; PORT LAYER M4 ; - RECT 0.108 0.192 16.481 0.288 ; - RECT 0.108 0.960 16.481 1.056 ; - RECT 0.108 1.728 16.481 1.824 ; - RECT 0.108 2.496 16.481 2.592 ; - RECT 0.108 3.264 16.481 3.360 ; - RECT 0.108 4.032 16.481 4.128 ; - RECT 0.108 4.800 16.481 4.896 ; - RECT 0.108 5.568 16.481 5.664 ; - RECT 0.108 6.336 16.481 6.432 ; - RECT 0.108 7.104 16.481 7.200 ; - RECT 0.108 7.872 16.481 7.968 ; - RECT 0.108 8.640 16.481 8.736 ; - RECT 0.108 9.408 16.481 9.504 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; END END VDD OBS LAYER M1 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 19.285 9.643 ; LAYER M2 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 19.285 9.643 ; LAYER M3 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 19.285 9.643 ; LAYER M4 ; - RECT 0 0 16.589 10.368 ; + RECT 0 0 19.285 9.643 ; END -END fakeram_32x128_2r1w +END fakeram_64x16_1r1w END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_64x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_64x256_1r1w.lef new file mode 100644 index 0000000..8963c26 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_64x256_1r1w.lef @@ -0,0 +1,1501 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x256_1r1w + FOREIGN fakeram_64x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.285 BY 48.212 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.244 0.072 2.268 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.212 0.072 4.236 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.148 0.072 8.172 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.116 0.072 10.140 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.052 0.072 14.076 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.020 0.072 16.044 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.924 0.072 21.948 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.860 0.072 25.884 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.828 0.072 27.852 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.796 0.072 29.820 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 0.276 19.285 0.300 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 2.244 19.285 2.268 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 4.212 19.285 4.236 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 6.180 19.285 6.204 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 8.148 19.285 8.172 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 10.116 19.285 10.140 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 12.084 19.285 12.108 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 14.052 19.285 14.076 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 16.020 19.285 16.044 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 17.988 19.285 18.012 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 19.956 19.285 19.980 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 21.924 19.285 21.948 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 23.892 19.285 23.916 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 25.860 19.285 25.884 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 27.828 19.285 27.852 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 29.796 19.285 29.820 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[63] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 48.158 0.225 48.212 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 48.158 0.729 48.212 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 48.158 1.233 48.212 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 48.158 1.737 48.212 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 48.158 2.241 48.212 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 48.158 2.745 48.212 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 48.158 3.249 48.212 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 48.158 3.753 48.212 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 48.158 4.257 48.212 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 48.158 4.761 48.212 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 48.158 5.265 48.212 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 48.158 5.769 48.212 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 48.158 6.273 48.212 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 48.158 6.777 48.212 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 48.158 7.281 48.212 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 48.158 7.785 48.212 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 48.158 8.289 48.212 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 48.158 8.793 48.212 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 48.158 9.297 48.212 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 48.158 9.801 48.212 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 48.158 10.305 48.212 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 48.158 10.809 48.212 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 48.158 11.313 48.212 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 48.158 11.817 48.212 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 48.158 12.321 48.212 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 48.158 12.825 48.212 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 48.158 13.329 48.212 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 48.158 13.833 48.212 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 48.158 14.337 48.212 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 48.158 14.841 48.212 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 48.158 15.345 48.212 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 48.158 15.849 48.212 ; + END + END r0_rd_out[63] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.764 0.072 31.788 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.732 0.072 33.756 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.668 0.072 37.692 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 31.764 19.285 31.788 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 33.732 19.285 33.756 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 35.700 19.285 35.724 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 37.668 19.285 37.692 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.636 0.072 39.660 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.604 0.072 41.628 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.572 0.072 43.596 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.540 0.072 45.564 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 39.636 19.285 39.660 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 41.604 19.285 41.628 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 43.572 19.285 43.596 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 45.540 19.285 45.564 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 48.158 16.353 48.212 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 48.158 16.857 48.212 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 48.158 17.361 48.212 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 48.158 17.865 48.212 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 48.158 18.369 48.212 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + RECT 0.216 16.368 19.069 16.464 ; + RECT 0.216 17.136 19.069 17.232 ; + RECT 0.216 17.904 19.069 18.000 ; + RECT 0.216 18.672 19.069 18.768 ; + RECT 0.216 19.440 19.069 19.536 ; + RECT 0.216 20.208 19.069 20.304 ; + RECT 0.216 20.976 19.069 21.072 ; + RECT 0.216 21.744 19.069 21.840 ; + RECT 0.216 22.512 19.069 22.608 ; + RECT 0.216 23.280 19.069 23.376 ; + RECT 0.216 24.048 19.069 24.144 ; + RECT 0.216 24.816 19.069 24.912 ; + RECT 0.216 25.584 19.069 25.680 ; + RECT 0.216 26.352 19.069 26.448 ; + RECT 0.216 27.120 19.069 27.216 ; + RECT 0.216 27.888 19.069 27.984 ; + RECT 0.216 28.656 19.069 28.752 ; + RECT 0.216 29.424 19.069 29.520 ; + RECT 0.216 30.192 19.069 30.288 ; + RECT 0.216 30.960 19.069 31.056 ; + RECT 0.216 31.728 19.069 31.824 ; + RECT 0.216 32.496 19.069 32.592 ; + RECT 0.216 33.264 19.069 33.360 ; + RECT 0.216 34.032 19.069 34.128 ; + RECT 0.216 34.800 19.069 34.896 ; + RECT 0.216 35.568 19.069 35.664 ; + RECT 0.216 36.336 19.069 36.432 ; + RECT 0.216 37.104 19.069 37.200 ; + RECT 0.216 37.872 19.069 37.968 ; + RECT 0.216 38.640 19.069 38.736 ; + RECT 0.216 39.408 19.069 39.504 ; + RECT 0.216 40.176 19.069 40.272 ; + RECT 0.216 40.944 19.069 41.040 ; + RECT 0.216 41.712 19.069 41.808 ; + RECT 0.216 42.480 19.069 42.576 ; + RECT 0.216 43.248 19.069 43.344 ; + RECT 0.216 44.016 19.069 44.112 ; + RECT 0.216 44.784 19.069 44.880 ; + RECT 0.216 45.552 19.069 45.648 ; + RECT 0.216 46.320 19.069 46.416 ; + RECT 0.216 47.088 19.069 47.184 ; + RECT 0.216 47.856 19.069 47.952 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + RECT 0.216 16.368 19.069 16.464 ; + RECT 0.216 17.136 19.069 17.232 ; + RECT 0.216 17.904 19.069 18.000 ; + RECT 0.216 18.672 19.069 18.768 ; + RECT 0.216 19.440 19.069 19.536 ; + RECT 0.216 20.208 19.069 20.304 ; + RECT 0.216 20.976 19.069 21.072 ; + RECT 0.216 21.744 19.069 21.840 ; + RECT 0.216 22.512 19.069 22.608 ; + RECT 0.216 23.280 19.069 23.376 ; + RECT 0.216 24.048 19.069 24.144 ; + RECT 0.216 24.816 19.069 24.912 ; + RECT 0.216 25.584 19.069 25.680 ; + RECT 0.216 26.352 19.069 26.448 ; + RECT 0.216 27.120 19.069 27.216 ; + RECT 0.216 27.888 19.069 27.984 ; + RECT 0.216 28.656 19.069 28.752 ; + RECT 0.216 29.424 19.069 29.520 ; + RECT 0.216 30.192 19.069 30.288 ; + RECT 0.216 30.960 19.069 31.056 ; + RECT 0.216 31.728 19.069 31.824 ; + RECT 0.216 32.496 19.069 32.592 ; + RECT 0.216 33.264 19.069 33.360 ; + RECT 0.216 34.032 19.069 34.128 ; + RECT 0.216 34.800 19.069 34.896 ; + RECT 0.216 35.568 19.069 35.664 ; + RECT 0.216 36.336 19.069 36.432 ; + RECT 0.216 37.104 19.069 37.200 ; + RECT 0.216 37.872 19.069 37.968 ; + RECT 0.216 38.640 19.069 38.736 ; + RECT 0.216 39.408 19.069 39.504 ; + RECT 0.216 40.176 19.069 40.272 ; + RECT 0.216 40.944 19.069 41.040 ; + RECT 0.216 41.712 19.069 41.808 ; + RECT 0.216 42.480 19.069 42.576 ; + RECT 0.216 43.248 19.069 43.344 ; + RECT 0.216 44.016 19.069 44.112 ; + RECT 0.216 44.784 19.069 44.880 ; + RECT 0.216 45.552 19.069 45.648 ; + RECT 0.216 46.320 19.069 46.416 ; + RECT 0.216 47.088 19.069 47.184 ; + RECT 0.216 47.856 19.069 47.952 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.285 48.212 ; + LAYER M2 ; + RECT 0 0 19.285 48.212 ; + LAYER M3 ; + RECT 0 0 19.285 48.212 ; + LAYER M4 ; + RECT 0 0 19.285 48.212 ; + END +END fakeram_64x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_64x512_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_64x512_1r1w.lef new file mode 100644 index 0000000..6e43b05 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_64x512_1r1w.lef @@ -0,0 +1,1631 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x512_1r1w + FOREIGN fakeram_64x512_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.285 BY 91.066 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.876 0.072 39.900 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.476 0.072 43.500 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.076 0.072 47.100 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.676 0.072 50.700 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.276 0.072 54.300 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 0.276 19.285 0.300 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 3.876 19.285 3.900 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 7.476 19.285 7.500 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 11.076 19.285 11.100 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 14.676 19.285 14.700 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 18.276 19.285 18.300 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 21.876 19.285 21.900 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 25.476 19.285 25.500 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 29.076 19.285 29.100 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 32.676 19.285 32.700 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 36.276 19.285 36.300 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 39.876 19.285 39.900 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 43.476 19.285 43.500 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 47.076 19.285 47.100 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 50.676 19.285 50.700 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 54.276 19.285 54.300 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[63] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 91.012 0.225 91.066 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 91.012 0.729 91.066 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 91.012 1.233 91.066 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 91.012 1.737 91.066 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 91.012 2.241 91.066 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 91.012 2.745 91.066 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 91.012 3.249 91.066 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 91.012 3.753 91.066 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 91.012 4.257 91.066 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 91.012 4.761 91.066 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 91.012 5.265 91.066 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 91.012 5.769 91.066 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 91.012 6.273 91.066 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 91.012 6.777 91.066 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 91.012 7.281 91.066 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 91.012 7.785 91.066 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 91.012 8.289 91.066 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 91.012 8.793 91.066 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 91.012 9.297 91.066 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 91.012 9.801 91.066 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 91.012 10.305 91.066 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 91.012 10.809 91.066 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 91.012 11.313 91.066 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 91.012 11.817 91.066 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 91.012 12.321 91.066 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 91.012 12.825 91.066 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 91.012 13.329 91.066 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 91.012 13.833 91.066 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 91.012 14.337 91.066 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 91.012 14.841 91.066 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 91.012 15.345 91.066 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 91.012 15.849 91.066 ; + END + END r0_rd_out[63] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.876 0.072 57.900 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.476 0.072 61.500 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.076 0.072 65.100 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.676 0.072 68.700 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.276 0.072 72.300 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 57.876 19.285 57.900 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 61.476 19.285 61.500 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 65.076 19.285 65.100 ; + END + END w0_addr_in[7] + PIN w0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 68.676 19.285 68.700 ; + END + END w0_addr_in[8] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.876 0.072 75.900 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.476 0.072 79.500 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.076 0.072 83.100 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.676 0.072 86.700 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.276 0.072 90.300 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 72.276 19.285 72.300 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 75.876 19.285 75.900 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 79.476 19.285 79.500 ; + END + END r0_addr_in[7] + PIN r0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 83.076 19.285 83.100 ; + END + END r0_addr_in[8] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 91.012 16.353 91.066 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 91.012 16.857 91.066 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 91.012 17.361 91.066 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 91.012 17.865 91.066 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 91.012 18.369 91.066 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + RECT 0.216 16.368 19.069 16.464 ; + RECT 0.216 17.136 19.069 17.232 ; + RECT 0.216 17.904 19.069 18.000 ; + RECT 0.216 18.672 19.069 18.768 ; + RECT 0.216 19.440 19.069 19.536 ; + RECT 0.216 20.208 19.069 20.304 ; + RECT 0.216 20.976 19.069 21.072 ; + RECT 0.216 21.744 19.069 21.840 ; + RECT 0.216 22.512 19.069 22.608 ; + RECT 0.216 23.280 19.069 23.376 ; + RECT 0.216 24.048 19.069 24.144 ; + RECT 0.216 24.816 19.069 24.912 ; + RECT 0.216 25.584 19.069 25.680 ; + RECT 0.216 26.352 19.069 26.448 ; + RECT 0.216 27.120 19.069 27.216 ; + RECT 0.216 27.888 19.069 27.984 ; + RECT 0.216 28.656 19.069 28.752 ; + RECT 0.216 29.424 19.069 29.520 ; + RECT 0.216 30.192 19.069 30.288 ; + RECT 0.216 30.960 19.069 31.056 ; + RECT 0.216 31.728 19.069 31.824 ; + RECT 0.216 32.496 19.069 32.592 ; + RECT 0.216 33.264 19.069 33.360 ; + RECT 0.216 34.032 19.069 34.128 ; + RECT 0.216 34.800 19.069 34.896 ; + RECT 0.216 35.568 19.069 35.664 ; + RECT 0.216 36.336 19.069 36.432 ; + RECT 0.216 37.104 19.069 37.200 ; + RECT 0.216 37.872 19.069 37.968 ; + RECT 0.216 38.640 19.069 38.736 ; + RECT 0.216 39.408 19.069 39.504 ; + RECT 0.216 40.176 19.069 40.272 ; + RECT 0.216 40.944 19.069 41.040 ; + RECT 0.216 41.712 19.069 41.808 ; + RECT 0.216 42.480 19.069 42.576 ; + RECT 0.216 43.248 19.069 43.344 ; + RECT 0.216 44.016 19.069 44.112 ; + RECT 0.216 44.784 19.069 44.880 ; + RECT 0.216 45.552 19.069 45.648 ; + RECT 0.216 46.320 19.069 46.416 ; + RECT 0.216 47.088 19.069 47.184 ; + RECT 0.216 47.856 19.069 47.952 ; + RECT 0.216 48.624 19.069 48.720 ; + RECT 0.216 49.392 19.069 49.488 ; + RECT 0.216 50.160 19.069 50.256 ; + RECT 0.216 50.928 19.069 51.024 ; + RECT 0.216 51.696 19.069 51.792 ; + RECT 0.216 52.464 19.069 52.560 ; + RECT 0.216 53.232 19.069 53.328 ; + RECT 0.216 54.000 19.069 54.096 ; + RECT 0.216 54.768 19.069 54.864 ; + RECT 0.216 55.536 19.069 55.632 ; + RECT 0.216 56.304 19.069 56.400 ; + RECT 0.216 57.072 19.069 57.168 ; + RECT 0.216 57.840 19.069 57.936 ; + RECT 0.216 58.608 19.069 58.704 ; + RECT 0.216 59.376 19.069 59.472 ; + RECT 0.216 60.144 19.069 60.240 ; + RECT 0.216 60.912 19.069 61.008 ; + RECT 0.216 61.680 19.069 61.776 ; + RECT 0.216 62.448 19.069 62.544 ; + RECT 0.216 63.216 19.069 63.312 ; + RECT 0.216 63.984 19.069 64.080 ; + RECT 0.216 64.752 19.069 64.848 ; + RECT 0.216 65.520 19.069 65.616 ; + RECT 0.216 66.288 19.069 66.384 ; + RECT 0.216 67.056 19.069 67.152 ; + RECT 0.216 67.824 19.069 67.920 ; + RECT 0.216 68.592 19.069 68.688 ; + RECT 0.216 69.360 19.069 69.456 ; + RECT 0.216 70.128 19.069 70.224 ; + RECT 0.216 70.896 19.069 70.992 ; + RECT 0.216 71.664 19.069 71.760 ; + RECT 0.216 72.432 19.069 72.528 ; + RECT 0.216 73.200 19.069 73.296 ; + RECT 0.216 73.968 19.069 74.064 ; + RECT 0.216 74.736 19.069 74.832 ; + RECT 0.216 75.504 19.069 75.600 ; + RECT 0.216 76.272 19.069 76.368 ; + RECT 0.216 77.040 19.069 77.136 ; + RECT 0.216 77.808 19.069 77.904 ; + RECT 0.216 78.576 19.069 78.672 ; + RECT 0.216 79.344 19.069 79.440 ; + RECT 0.216 80.112 19.069 80.208 ; + RECT 0.216 80.880 19.069 80.976 ; + RECT 0.216 81.648 19.069 81.744 ; + RECT 0.216 82.416 19.069 82.512 ; + RECT 0.216 83.184 19.069 83.280 ; + RECT 0.216 83.952 19.069 84.048 ; + RECT 0.216 84.720 19.069 84.816 ; + RECT 0.216 85.488 19.069 85.584 ; + RECT 0.216 86.256 19.069 86.352 ; + RECT 0.216 87.024 19.069 87.120 ; + RECT 0.216 87.792 19.069 87.888 ; + RECT 0.216 88.560 19.069 88.656 ; + RECT 0.216 89.328 19.069 89.424 ; + RECT 0.216 90.096 19.069 90.192 ; + RECT 0.216 90.864 19.069 90.960 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + RECT 0.216 16.368 19.069 16.464 ; + RECT 0.216 17.136 19.069 17.232 ; + RECT 0.216 17.904 19.069 18.000 ; + RECT 0.216 18.672 19.069 18.768 ; + RECT 0.216 19.440 19.069 19.536 ; + RECT 0.216 20.208 19.069 20.304 ; + RECT 0.216 20.976 19.069 21.072 ; + RECT 0.216 21.744 19.069 21.840 ; + RECT 0.216 22.512 19.069 22.608 ; + RECT 0.216 23.280 19.069 23.376 ; + RECT 0.216 24.048 19.069 24.144 ; + RECT 0.216 24.816 19.069 24.912 ; + RECT 0.216 25.584 19.069 25.680 ; + RECT 0.216 26.352 19.069 26.448 ; + RECT 0.216 27.120 19.069 27.216 ; + RECT 0.216 27.888 19.069 27.984 ; + RECT 0.216 28.656 19.069 28.752 ; + RECT 0.216 29.424 19.069 29.520 ; + RECT 0.216 30.192 19.069 30.288 ; + RECT 0.216 30.960 19.069 31.056 ; + RECT 0.216 31.728 19.069 31.824 ; + RECT 0.216 32.496 19.069 32.592 ; + RECT 0.216 33.264 19.069 33.360 ; + RECT 0.216 34.032 19.069 34.128 ; + RECT 0.216 34.800 19.069 34.896 ; + RECT 0.216 35.568 19.069 35.664 ; + RECT 0.216 36.336 19.069 36.432 ; + RECT 0.216 37.104 19.069 37.200 ; + RECT 0.216 37.872 19.069 37.968 ; + RECT 0.216 38.640 19.069 38.736 ; + RECT 0.216 39.408 19.069 39.504 ; + RECT 0.216 40.176 19.069 40.272 ; + RECT 0.216 40.944 19.069 41.040 ; + RECT 0.216 41.712 19.069 41.808 ; + RECT 0.216 42.480 19.069 42.576 ; + RECT 0.216 43.248 19.069 43.344 ; + RECT 0.216 44.016 19.069 44.112 ; + RECT 0.216 44.784 19.069 44.880 ; + RECT 0.216 45.552 19.069 45.648 ; + RECT 0.216 46.320 19.069 46.416 ; + RECT 0.216 47.088 19.069 47.184 ; + RECT 0.216 47.856 19.069 47.952 ; + RECT 0.216 48.624 19.069 48.720 ; + RECT 0.216 49.392 19.069 49.488 ; + RECT 0.216 50.160 19.069 50.256 ; + RECT 0.216 50.928 19.069 51.024 ; + RECT 0.216 51.696 19.069 51.792 ; + RECT 0.216 52.464 19.069 52.560 ; + RECT 0.216 53.232 19.069 53.328 ; + RECT 0.216 54.000 19.069 54.096 ; + RECT 0.216 54.768 19.069 54.864 ; + RECT 0.216 55.536 19.069 55.632 ; + RECT 0.216 56.304 19.069 56.400 ; + RECT 0.216 57.072 19.069 57.168 ; + RECT 0.216 57.840 19.069 57.936 ; + RECT 0.216 58.608 19.069 58.704 ; + RECT 0.216 59.376 19.069 59.472 ; + RECT 0.216 60.144 19.069 60.240 ; + RECT 0.216 60.912 19.069 61.008 ; + RECT 0.216 61.680 19.069 61.776 ; + RECT 0.216 62.448 19.069 62.544 ; + RECT 0.216 63.216 19.069 63.312 ; + RECT 0.216 63.984 19.069 64.080 ; + RECT 0.216 64.752 19.069 64.848 ; + RECT 0.216 65.520 19.069 65.616 ; + RECT 0.216 66.288 19.069 66.384 ; + RECT 0.216 67.056 19.069 67.152 ; + RECT 0.216 67.824 19.069 67.920 ; + RECT 0.216 68.592 19.069 68.688 ; + RECT 0.216 69.360 19.069 69.456 ; + RECT 0.216 70.128 19.069 70.224 ; + RECT 0.216 70.896 19.069 70.992 ; + RECT 0.216 71.664 19.069 71.760 ; + RECT 0.216 72.432 19.069 72.528 ; + RECT 0.216 73.200 19.069 73.296 ; + RECT 0.216 73.968 19.069 74.064 ; + RECT 0.216 74.736 19.069 74.832 ; + RECT 0.216 75.504 19.069 75.600 ; + RECT 0.216 76.272 19.069 76.368 ; + RECT 0.216 77.040 19.069 77.136 ; + RECT 0.216 77.808 19.069 77.904 ; + RECT 0.216 78.576 19.069 78.672 ; + RECT 0.216 79.344 19.069 79.440 ; + RECT 0.216 80.112 19.069 80.208 ; + RECT 0.216 80.880 19.069 80.976 ; + RECT 0.216 81.648 19.069 81.744 ; + RECT 0.216 82.416 19.069 82.512 ; + RECT 0.216 83.184 19.069 83.280 ; + RECT 0.216 83.952 19.069 84.048 ; + RECT 0.216 84.720 19.069 84.816 ; + RECT 0.216 85.488 19.069 85.584 ; + RECT 0.216 86.256 19.069 86.352 ; + RECT 0.216 87.024 19.069 87.120 ; + RECT 0.216 87.792 19.069 87.888 ; + RECT 0.216 88.560 19.069 88.656 ; + RECT 0.216 89.328 19.069 89.424 ; + RECT 0.216 90.096 19.069 90.192 ; + RECT 0.216 90.864 19.069 90.960 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.285 91.066 ; + LAYER M2 ; + RECT 0 0 19.285 91.066 ; + LAYER M3 ; + RECT 0 0 19.285 91.066 ; + LAYER M4 ; + RECT 0 0 19.285 91.066 ; + END +END fakeram_64x512_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_64x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_64x64_1r1w.lef new file mode 100644 index 0000000..44ad596 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_64x64_1r1w.lef @@ -0,0 +1,1381 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_64x64_1r1w + FOREIGN fakeram_64x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.285 BY 16.071 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 0.276 19.285 0.300 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 0.948 19.285 0.972 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 1.620 19.285 1.644 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 2.292 19.285 2.316 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 2.964 19.285 2.988 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 3.636 19.285 3.660 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 4.308 19.285 4.332 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 4.980 19.285 5.004 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 5.652 19.285 5.676 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 6.324 19.285 6.348 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 6.996 19.285 7.020 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 7.668 19.285 7.692 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 8.340 19.285 8.364 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 9.012 19.285 9.036 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 9.684 19.285 9.708 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 10.356 19.285 10.380 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[63] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 16.017 0.225 16.071 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 16.017 0.729 16.071 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 16.017 1.233 16.071 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 16.017 1.737 16.071 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 16.017 2.241 16.071 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 16.017 2.745 16.071 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 16.017 3.249 16.071 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 16.017 3.753 16.071 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 16.017 4.257 16.071 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 16.017 4.761 16.071 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 16.017 5.265 16.071 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 16.017 5.769 16.071 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 16.017 6.273 16.071 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 16.017 6.777 16.071 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 16.017 7.281 16.071 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 16.017 7.785 16.071 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 16.017 8.289 16.071 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 16.017 8.793 16.071 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 16.017 9.297 16.071 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 16.017 9.801 16.071 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 16.017 10.305 16.071 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 16.017 10.809 16.071 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 16.017 11.313 16.071 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 16.017 11.817 16.071 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 16.017 12.321 16.071 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 16.017 12.825 16.071 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 16.017 13.329 16.071 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 16.017 13.833 16.071 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 16.017 14.337 16.071 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 16.017 14.841 16.071 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 16.017 15.345 16.071 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 16.017 15.849 16.071 ; + END + END r0_rd_out[63] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 11.028 19.285 11.052 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 11.700 19.285 11.724 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 12.372 19.285 12.396 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 13.044 19.285 13.068 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 13.716 19.285 13.740 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.213 14.388 19.285 14.412 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 16.017 16.353 16.071 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 16.017 16.857 16.071 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 16.017 17.361 16.071 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 16.017 17.865 16.071 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 16.017 18.369 16.071 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.069 0.336 ; + RECT 0.216 1.008 19.069 1.104 ; + RECT 0.216 1.776 19.069 1.872 ; + RECT 0.216 2.544 19.069 2.640 ; + RECT 0.216 3.312 19.069 3.408 ; + RECT 0.216 4.080 19.069 4.176 ; + RECT 0.216 4.848 19.069 4.944 ; + RECT 0.216 5.616 19.069 5.712 ; + RECT 0.216 6.384 19.069 6.480 ; + RECT 0.216 7.152 19.069 7.248 ; + RECT 0.216 7.920 19.069 8.016 ; + RECT 0.216 8.688 19.069 8.784 ; + RECT 0.216 9.456 19.069 9.552 ; + RECT 0.216 10.224 19.069 10.320 ; + RECT 0.216 10.992 19.069 11.088 ; + RECT 0.216 11.760 19.069 11.856 ; + RECT 0.216 12.528 19.069 12.624 ; + RECT 0.216 13.296 19.069 13.392 ; + RECT 0.216 14.064 19.069 14.160 ; + RECT 0.216 14.832 19.069 14.928 ; + RECT 0.216 15.600 19.069 15.696 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.285 16.071 ; + LAYER M2 ; + RECT 0 0 19.285 16.071 ; + LAYER M3 ; + RECT 0 0 19.285 16.071 ; + LAYER M4 ; + RECT 0 0 19.285 16.071 ; + END +END fakeram_64x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_65x160_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_65x160_1r1w.lef new file mode 100644 index 0000000..6ee4721 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_65x160_1r1w.lef @@ -0,0 +1,1477 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_65x160_1r1w + FOREIGN fakeram_65x160_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.586 BY 32.225 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.524 0.072 1.548 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.500 0.072 16.524 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.244 0.072 20.268 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 0.276 19.586 0.300 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 1.524 19.586 1.548 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 2.772 19.586 2.796 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 4.020 19.586 4.044 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 5.268 19.586 5.292 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 6.516 19.586 6.540 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 7.764 19.586 7.788 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 9.012 19.586 9.036 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 10.260 19.586 10.284 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 11.508 19.586 11.532 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 12.756 19.586 12.780 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 14.004 19.586 14.028 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 15.252 19.586 15.276 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 16.500 19.586 16.524 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 17.748 19.586 17.772 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 18.996 19.586 19.020 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[64] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 32.171 0.225 32.225 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.675 32.171 0.693 32.225 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.143 32.171 1.161 32.225 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.611 32.171 1.629 32.225 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.079 32.171 2.097 32.225 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 32.171 2.565 32.225 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.015 32.171 3.033 32.225 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.483 32.171 3.501 32.225 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 32.171 3.969 32.225 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.419 32.171 4.437 32.225 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 32.171 4.905 32.225 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.355 32.171 5.373 32.225 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.823 32.171 5.841 32.225 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.291 32.171 6.309 32.225 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 32.171 6.777 32.225 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 32.171 7.245 32.225 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 32.171 7.713 32.225 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.163 32.171 8.181 32.225 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.631 32.171 8.649 32.225 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.099 32.171 9.117 32.225 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 32.171 9.585 32.225 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.035 32.171 10.053 32.225 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.503 32.171 10.521 32.225 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.971 32.171 10.989 32.225 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 32.171 11.457 32.225 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 32.171 11.925 32.225 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.375 32.171 12.393 32.225 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.843 32.171 12.861 32.225 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 32.171 13.329 32.225 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.779 32.171 13.797 32.225 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 32.171 14.265 32.225 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.715 32.171 14.733 32.225 ; + END + END r0_rd_out[64] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.492 0.072 21.516 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.988 0.072 24.012 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.236 0.072 25.260 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 20.244 19.586 20.268 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 21.492 19.586 21.516 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 22.740 19.586 22.764 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 23.988 19.586 24.012 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.732 0.072 27.756 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.980 0.072 29.004 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 25.236 19.586 25.260 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 26.484 19.586 26.508 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 27.732 19.586 27.756 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.514 28.980 19.586 29.004 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 32.171 15.201 32.225 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.651 32.171 15.669 32.225 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.119 32.171 16.137 32.225 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 32.171 16.605 32.225 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.055 32.171 17.073 32.225 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.370 0.336 ; + RECT 0.216 1.008 19.370 1.104 ; + RECT 0.216 1.776 19.370 1.872 ; + RECT 0.216 2.544 19.370 2.640 ; + RECT 0.216 3.312 19.370 3.408 ; + RECT 0.216 4.080 19.370 4.176 ; + RECT 0.216 4.848 19.370 4.944 ; + RECT 0.216 5.616 19.370 5.712 ; + RECT 0.216 6.384 19.370 6.480 ; + RECT 0.216 7.152 19.370 7.248 ; + RECT 0.216 7.920 19.370 8.016 ; + RECT 0.216 8.688 19.370 8.784 ; + RECT 0.216 9.456 19.370 9.552 ; + RECT 0.216 10.224 19.370 10.320 ; + RECT 0.216 10.992 19.370 11.088 ; + RECT 0.216 11.760 19.370 11.856 ; + RECT 0.216 12.528 19.370 12.624 ; + RECT 0.216 13.296 19.370 13.392 ; + RECT 0.216 14.064 19.370 14.160 ; + RECT 0.216 14.832 19.370 14.928 ; + RECT 0.216 15.600 19.370 15.696 ; + RECT 0.216 16.368 19.370 16.464 ; + RECT 0.216 17.136 19.370 17.232 ; + RECT 0.216 17.904 19.370 18.000 ; + RECT 0.216 18.672 19.370 18.768 ; + RECT 0.216 19.440 19.370 19.536 ; + RECT 0.216 20.208 19.370 20.304 ; + RECT 0.216 20.976 19.370 21.072 ; + RECT 0.216 21.744 19.370 21.840 ; + RECT 0.216 22.512 19.370 22.608 ; + RECT 0.216 23.280 19.370 23.376 ; + RECT 0.216 24.048 19.370 24.144 ; + RECT 0.216 24.816 19.370 24.912 ; + RECT 0.216 25.584 19.370 25.680 ; + RECT 0.216 26.352 19.370 26.448 ; + RECT 0.216 27.120 19.370 27.216 ; + RECT 0.216 27.888 19.370 27.984 ; + RECT 0.216 28.656 19.370 28.752 ; + RECT 0.216 29.424 19.370 29.520 ; + RECT 0.216 30.192 19.370 30.288 ; + RECT 0.216 30.960 19.370 31.056 ; + RECT 0.216 31.728 19.370 31.824 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.370 0.336 ; + RECT 0.216 1.008 19.370 1.104 ; + RECT 0.216 1.776 19.370 1.872 ; + RECT 0.216 2.544 19.370 2.640 ; + RECT 0.216 3.312 19.370 3.408 ; + RECT 0.216 4.080 19.370 4.176 ; + RECT 0.216 4.848 19.370 4.944 ; + RECT 0.216 5.616 19.370 5.712 ; + RECT 0.216 6.384 19.370 6.480 ; + RECT 0.216 7.152 19.370 7.248 ; + RECT 0.216 7.920 19.370 8.016 ; + RECT 0.216 8.688 19.370 8.784 ; + RECT 0.216 9.456 19.370 9.552 ; + RECT 0.216 10.224 19.370 10.320 ; + RECT 0.216 10.992 19.370 11.088 ; + RECT 0.216 11.760 19.370 11.856 ; + RECT 0.216 12.528 19.370 12.624 ; + RECT 0.216 13.296 19.370 13.392 ; + RECT 0.216 14.064 19.370 14.160 ; + RECT 0.216 14.832 19.370 14.928 ; + RECT 0.216 15.600 19.370 15.696 ; + RECT 0.216 16.368 19.370 16.464 ; + RECT 0.216 17.136 19.370 17.232 ; + RECT 0.216 17.904 19.370 18.000 ; + RECT 0.216 18.672 19.370 18.768 ; + RECT 0.216 19.440 19.370 19.536 ; + RECT 0.216 20.208 19.370 20.304 ; + RECT 0.216 20.976 19.370 21.072 ; + RECT 0.216 21.744 19.370 21.840 ; + RECT 0.216 22.512 19.370 22.608 ; + RECT 0.216 23.280 19.370 23.376 ; + RECT 0.216 24.048 19.370 24.144 ; + RECT 0.216 24.816 19.370 24.912 ; + RECT 0.216 25.584 19.370 25.680 ; + RECT 0.216 26.352 19.370 26.448 ; + RECT 0.216 27.120 19.370 27.216 ; + RECT 0.216 27.888 19.370 27.984 ; + RECT 0.216 28.656 19.370 28.752 ; + RECT 0.216 29.424 19.370 29.520 ; + RECT 0.216 30.192 19.370 30.288 ; + RECT 0.216 30.960 19.370 31.056 ; + RECT 0.216 31.728 19.370 31.824 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.586 32.225 ; + LAYER M2 ; + RECT 0 0 19.586 32.225 ; + LAYER M3 ; + RECT 0 0 19.586 32.225 ; + LAYER M4 ; + RECT 0 0 19.586 32.225 ; + END +END fakeram_65x160_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_66x64_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_66x64_1r1w.lef new file mode 100644 index 0000000..9c7f925 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_66x64_1r1w.lef @@ -0,0 +1,1417 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_66x64_1r1w + FOREIGN fakeram_66x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.888 BY 16.238 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 0.276 19.888 0.300 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 0.948 19.888 0.972 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 1.620 19.888 1.644 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 2.292 19.888 2.316 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 2.964 19.888 2.988 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 3.636 19.888 3.660 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 4.308 19.888 4.332 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 4.980 19.888 5.004 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 5.652 19.888 5.676 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 6.324 19.888 6.348 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 6.996 19.888 7.020 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 7.668 19.888 7.692 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 8.340 19.888 8.364 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 9.012 19.888 9.036 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 9.684 19.888 9.708 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 10.356 19.888 10.380 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[65] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 16.184 0.225 16.238 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 16.184 0.729 16.238 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 16.184 1.233 16.238 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 16.184 1.737 16.238 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 16.184 2.241 16.238 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 16.184 2.745 16.238 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 16.184 3.249 16.238 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 16.184 3.753 16.238 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 16.184 4.257 16.238 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 16.184 4.761 16.238 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 16.184 5.265 16.238 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 16.184 5.769 16.238 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 16.184 6.273 16.238 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 16.184 6.777 16.238 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 16.184 7.281 16.238 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 16.184 7.785 16.238 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 16.184 8.289 16.238 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 16.184 8.793 16.238 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 16.184 9.297 16.238 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 16.184 9.801 16.238 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 16.184 10.305 16.238 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 16.184 10.809 16.238 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 16.184 11.313 16.238 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 16.184 11.817 16.238 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 16.184 12.321 16.238 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 16.184 12.825 16.238 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 16.184 13.329 16.238 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 16.184 13.833 16.238 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 16.184 14.337 16.238 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 16.184 14.841 16.238 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 16.184 15.345 16.238 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 16.184 15.849 16.238 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 16.184 16.353 16.238 ; + END + END r0_rd_out[65] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 11.028 19.888 11.052 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 11.700 19.888 11.724 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 12.372 19.888 12.396 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 13.044 19.888 13.068 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 13.716 19.888 13.740 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 14.388 19.888 14.412 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 16.184 16.857 16.238 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 16.184 17.361 16.238 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 16.184 17.865 16.238 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 16.184 18.369 16.238 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 16.184 18.873 16.238 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.672 0.336 ; + RECT 0.216 1.008 19.672 1.104 ; + RECT 0.216 1.776 19.672 1.872 ; + RECT 0.216 2.544 19.672 2.640 ; + RECT 0.216 3.312 19.672 3.408 ; + RECT 0.216 4.080 19.672 4.176 ; + RECT 0.216 4.848 19.672 4.944 ; + RECT 0.216 5.616 19.672 5.712 ; + RECT 0.216 6.384 19.672 6.480 ; + RECT 0.216 7.152 19.672 7.248 ; + RECT 0.216 7.920 19.672 8.016 ; + RECT 0.216 8.688 19.672 8.784 ; + RECT 0.216 9.456 19.672 9.552 ; + RECT 0.216 10.224 19.672 10.320 ; + RECT 0.216 10.992 19.672 11.088 ; + RECT 0.216 11.760 19.672 11.856 ; + RECT 0.216 12.528 19.672 12.624 ; + RECT 0.216 13.296 19.672 13.392 ; + RECT 0.216 14.064 19.672 14.160 ; + RECT 0.216 14.832 19.672 14.928 ; + RECT 0.216 15.600 19.672 15.696 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.672 0.336 ; + RECT 0.216 1.008 19.672 1.104 ; + RECT 0.216 1.776 19.672 1.872 ; + RECT 0.216 2.544 19.672 2.640 ; + RECT 0.216 3.312 19.672 3.408 ; + RECT 0.216 4.080 19.672 4.176 ; + RECT 0.216 4.848 19.672 4.944 ; + RECT 0.216 5.616 19.672 5.712 ; + RECT 0.216 6.384 19.672 6.480 ; + RECT 0.216 7.152 19.672 7.248 ; + RECT 0.216 7.920 19.672 8.016 ; + RECT 0.216 8.688 19.672 8.784 ; + RECT 0.216 9.456 19.672 9.552 ; + RECT 0.216 10.224 19.672 10.320 ; + RECT 0.216 10.992 19.672 11.088 ; + RECT 0.216 11.760 19.672 11.856 ; + RECT 0.216 12.528 19.672 12.624 ; + RECT 0.216 13.296 19.672 13.392 ; + RECT 0.216 14.064 19.672 14.160 ; + RECT 0.216 14.832 19.672 14.928 ; + RECT 0.216 15.600 19.672 15.696 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.888 16.238 ; + LAYER M2 ; + RECT 0 0 19.888 16.238 ; + LAYER M3 ; + RECT 0 0 19.888 16.238 ; + LAYER M4 ; + RECT 0 0 19.888 16.238 ; + END +END fakeram_66x64_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_66x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_66x80_1r1w.lef new file mode 100644 index 0000000..5c59a35 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_66x80_1r1w.lef @@ -0,0 +1,1443 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_66x80_1r1w + FOREIGN fakeram_66x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.888 BY 18.917 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 0.276 19.888 0.300 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 0.996 19.888 1.020 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 1.716 19.888 1.740 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 2.436 19.888 2.460 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 3.156 19.888 3.180 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 3.876 19.888 3.900 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 4.596 19.888 4.620 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 5.316 19.888 5.340 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 6.036 19.888 6.060 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 6.756 19.888 6.780 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 7.476 19.888 7.500 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 8.196 19.888 8.220 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 8.916 19.888 8.940 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 9.636 19.888 9.660 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 10.356 19.888 10.380 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 11.076 19.888 11.100 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[65] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 18.863 0.225 18.917 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 18.863 0.729 18.917 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 18.863 1.233 18.917 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 18.863 1.737 18.917 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 18.863 2.241 18.917 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 18.863 2.745 18.917 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 18.863 3.249 18.917 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 18.863 3.753 18.917 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 18.863 4.257 18.917 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 18.863 4.761 18.917 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 18.863 5.265 18.917 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 18.863 5.769 18.917 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 18.863 6.273 18.917 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 18.863 6.777 18.917 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 18.863 7.281 18.917 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 18.863 7.785 18.917 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 18.863 8.289 18.917 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 18.863 8.793 18.917 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 18.863 9.297 18.917 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 18.863 9.801 18.917 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 18.863 10.305 18.917 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 18.863 10.809 18.917 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 18.863 11.313 18.917 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 18.863 11.817 18.917 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 18.863 12.321 18.917 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 18.863 12.825 18.917 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 18.863 13.329 18.917 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 18.863 13.833 18.917 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 18.863 14.337 18.917 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 18.863 14.841 18.917 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 18.863 15.345 18.917 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 18.863 15.849 18.917 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 18.863 16.353 18.917 ; + END + END r0_rd_out[65] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 11.796 19.888 11.820 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 12.516 19.888 12.540 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 13.236 19.888 13.260 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 13.956 19.888 13.980 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 14.676 19.888 14.700 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 15.396 19.888 15.420 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 18.863 16.857 18.917 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 18.863 17.361 18.917 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 18.863 17.865 18.917 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 18.863 18.369 18.917 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 18.863 18.873 18.917 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.672 0.336 ; + RECT 0.216 1.008 19.672 1.104 ; + RECT 0.216 1.776 19.672 1.872 ; + RECT 0.216 2.544 19.672 2.640 ; + RECT 0.216 3.312 19.672 3.408 ; + RECT 0.216 4.080 19.672 4.176 ; + RECT 0.216 4.848 19.672 4.944 ; + RECT 0.216 5.616 19.672 5.712 ; + RECT 0.216 6.384 19.672 6.480 ; + RECT 0.216 7.152 19.672 7.248 ; + RECT 0.216 7.920 19.672 8.016 ; + RECT 0.216 8.688 19.672 8.784 ; + RECT 0.216 9.456 19.672 9.552 ; + RECT 0.216 10.224 19.672 10.320 ; + RECT 0.216 10.992 19.672 11.088 ; + RECT 0.216 11.760 19.672 11.856 ; + RECT 0.216 12.528 19.672 12.624 ; + RECT 0.216 13.296 19.672 13.392 ; + RECT 0.216 14.064 19.672 14.160 ; + RECT 0.216 14.832 19.672 14.928 ; + RECT 0.216 15.600 19.672 15.696 ; + RECT 0.216 16.368 19.672 16.464 ; + RECT 0.216 17.136 19.672 17.232 ; + RECT 0.216 17.904 19.672 18.000 ; + RECT 0.216 18.672 19.672 18.768 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.672 0.336 ; + RECT 0.216 1.008 19.672 1.104 ; + RECT 0.216 1.776 19.672 1.872 ; + RECT 0.216 2.544 19.672 2.640 ; + RECT 0.216 3.312 19.672 3.408 ; + RECT 0.216 4.080 19.672 4.176 ; + RECT 0.216 4.848 19.672 4.944 ; + RECT 0.216 5.616 19.672 5.712 ; + RECT 0.216 6.384 19.672 6.480 ; + RECT 0.216 7.152 19.672 7.248 ; + RECT 0.216 7.920 19.672 8.016 ; + RECT 0.216 8.688 19.672 8.784 ; + RECT 0.216 9.456 19.672 9.552 ; + RECT 0.216 10.224 19.672 10.320 ; + RECT 0.216 10.992 19.672 11.088 ; + RECT 0.216 11.760 19.672 11.856 ; + RECT 0.216 12.528 19.672 12.624 ; + RECT 0.216 13.296 19.672 13.392 ; + RECT 0.216 14.064 19.672 14.160 ; + RECT 0.216 14.832 19.672 14.928 ; + RECT 0.216 15.600 19.672 15.696 ; + RECT 0.216 16.368 19.672 16.464 ; + RECT 0.216 17.136 19.672 17.232 ; + RECT 0.216 17.904 19.672 18.000 ; + RECT 0.216 18.672 19.672 18.768 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.888 18.917 ; + LAYER M2 ; + RECT 0 0 19.888 18.917 ; + LAYER M3 ; + RECT 0 0 19.888 18.917 ; + LAYER M4 ; + RECT 0 0 19.888 18.917 ; + END +END fakeram_66x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_66x8_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_66x8_1r1w.lef new file mode 100644 index 0000000..434f9af --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_66x8_1r1w.lef @@ -0,0 +1,1347 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_66x8_1r1w + FOREIGN fakeram_66x8_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 19.888 BY 9.643 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 0.276 19.888 0.300 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 0.708 19.888 0.732 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 1.140 19.888 1.164 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 1.572 19.888 1.596 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 2.004 19.888 2.028 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 2.436 19.888 2.460 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 2.868 19.888 2.892 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 3.300 19.888 3.324 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 3.732 19.888 3.756 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 4.164 19.888 4.188 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 4.596 19.888 4.620 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 5.028 19.888 5.052 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 5.460 19.888 5.484 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 5.892 19.888 5.916 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 6.324 19.888 6.348 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 6.756 19.888 6.780 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[65] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 9.589 0.225 9.643 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 9.589 0.729 9.643 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 9.589 1.233 9.643 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 9.589 1.737 9.643 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 9.589 2.241 9.643 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 9.589 2.745 9.643 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 9.589 3.249 9.643 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 9.589 3.753 9.643 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 9.589 4.257 9.643 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 9.589 4.761 9.643 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 9.589 5.265 9.643 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 9.589 5.769 9.643 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 9.589 6.273 9.643 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 9.589 6.777 9.643 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 9.589 7.281 9.643 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 9.589 7.785 9.643 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 9.589 8.289 9.643 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 9.589 8.793 9.643 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 9.589 9.297 9.643 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 9.589 9.801 9.643 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 9.589 10.305 9.643 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 9.589 10.809 9.643 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 9.589 11.313 9.643 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 9.589 11.817 9.643 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 9.589 12.321 9.643 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 9.589 12.825 9.643 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 9.589 13.329 9.643 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 9.589 13.833 9.643 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 9.589 14.337 9.643 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 9.589 14.841 9.643 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 9.589 15.345 9.643 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 9.589 15.849 9.643 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 9.589 16.353 9.643 ; + END + END r0_rd_out[65] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 7.188 19.888 7.212 ; + END + END w0_addr_in[2] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 19.816 7.620 19.888 7.644 ; + END + END r0_addr_in[2] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 9.589 16.857 9.643 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 9.589 17.361 9.643 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 9.589 17.865 9.643 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 9.589 18.369 9.643 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 9.589 18.873 9.643 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.672 0.336 ; + RECT 0.216 1.008 19.672 1.104 ; + RECT 0.216 1.776 19.672 1.872 ; + RECT 0.216 2.544 19.672 2.640 ; + RECT 0.216 3.312 19.672 3.408 ; + RECT 0.216 4.080 19.672 4.176 ; + RECT 0.216 4.848 19.672 4.944 ; + RECT 0.216 5.616 19.672 5.712 ; + RECT 0.216 6.384 19.672 6.480 ; + RECT 0.216 7.152 19.672 7.248 ; + RECT 0.216 7.920 19.672 8.016 ; + RECT 0.216 8.688 19.672 8.784 ; + RECT 0.216 9.456 19.672 9.552 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 19.672 0.336 ; + RECT 0.216 1.008 19.672 1.104 ; + RECT 0.216 1.776 19.672 1.872 ; + RECT 0.216 2.544 19.672 2.640 ; + RECT 0.216 3.312 19.672 3.408 ; + RECT 0.216 4.080 19.672 4.176 ; + RECT 0.216 4.848 19.672 4.944 ; + RECT 0.216 5.616 19.672 5.712 ; + RECT 0.216 6.384 19.672 6.480 ; + RECT 0.216 7.152 19.672 7.248 ; + RECT 0.216 7.920 19.672 8.016 ; + RECT 0.216 8.688 19.672 8.784 ; + RECT 0.216 9.456 19.672 9.552 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 19.888 9.643 ; + LAYER M2 ; + RECT 0 0 19.888 9.643 ; + LAYER M3 ; + RECT 0 0 19.888 9.643 ; + LAYER M4 ; + RECT 0 0 19.888 9.643 ; + END +END fakeram_66x8_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_6x128_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_6x128_1r1w.lef new file mode 100644 index 0000000..4b64d73 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_6x128_1r1w.lef @@ -0,0 +1,371 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_6x128_1r1w + FOREIGN fakeram_6x128_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 21.930 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 0.000 1.737 0.054 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[5] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 0.000 4.761 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 21.876 0.225 21.930 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.323 21.876 1.341 21.930 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.439 21.876 2.457 21.930 ; + END + END r0_rd_out[5] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.036 0.072 12.060 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.628 9.643 2.652 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.980 9.643 5.004 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 7.332 9.643 7.356 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.740 0.072 16.764 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.684 9.643 9.708 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 12.036 9.643 12.060 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 14.388 9.643 14.412 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.555 21.876 3.573 21.930 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.671 21.876 4.689 21.930 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 21.876 5.805 21.930 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.903 21.876 6.921 21.930 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.019 21.876 8.037 21.930 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 21.930 ; + LAYER M2 ; + RECT 0 0 9.643 21.930 ; + LAYER M3 ; + RECT 0 0 9.643 21.930 ; + LAYER M4 ; + RECT 0 0 9.643 21.930 ; + END +END fakeram_6x128_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_72x512_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_72x512_1r1w.lef new file mode 100644 index 0000000..7dbf8f3 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_72x512_1r1w.lef @@ -0,0 +1,1121 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_72x512_1r1w + FOREIGN fakeram_72x512_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 10.848 BY 88.723 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.124 0.072 5.148 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.972 0.072 9.996 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.668 0.072 19.692 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.516 0.072 24.540 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.212 0.072 34.236 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.060 0.072 39.084 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 0.276 10.848 0.300 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 5.124 10.848 5.148 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 9.972 10.848 9.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 14.820 10.848 14.844 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 19.668 10.848 19.692 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 24.516 10.848 24.540 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 29.364 10.848 29.388 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 34.212 10.848 34.236 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 39.060 10.848 39.084 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[35] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 88.669 0.225 88.723 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 88.669 0.657 88.723 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 88.669 1.089 88.723 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 88.669 1.521 88.723 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 88.669 1.953 88.723 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 88.669 2.385 88.723 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 88.669 2.817 88.723 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 88.669 3.249 88.723 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 88.669 3.681 88.723 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 88.669 4.113 88.723 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 88.669 4.545 88.723 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 88.669 4.977 88.723 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 88.669 5.409 88.723 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.823 88.669 5.841 88.723 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 88.669 6.273 88.723 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 88.669 6.705 88.723 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 88.669 7.137 88.723 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.551 88.669 7.569 88.723 ; + END + END r0_rd_out[35] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.908 0.072 43.932 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.756 0.072 48.780 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.604 0.072 53.628 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.452 0.072 58.476 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.300 0.072 63.324 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 43.908 10.848 43.932 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 48.756 10.848 48.780 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 53.604 10.848 53.628 ; + END + END w0_addr_in[7] + PIN w0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 58.452 10.848 58.476 ; + END + END w0_addr_in[8] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.148 0.072 68.172 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.996 0.072 73.020 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.844 0.072 77.868 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.692 0.072 82.716 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.540 0.072 87.564 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 63.300 10.848 63.324 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 68.148 10.848 68.172 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 72.996 10.848 73.020 ; + END + END r0_addr_in[7] + PIN r0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.776 77.844 10.848 77.868 ; + END + END r0_addr_in[8] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 88.669 8.001 88.723 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 88.669 8.433 88.723 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 88.669 8.865 88.723 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 88.669 9.297 88.723 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 88.669 9.729 88.723 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 10.632 0.336 ; + RECT 0.216 1.008 10.632 1.104 ; + RECT 0.216 1.776 10.632 1.872 ; + RECT 0.216 2.544 10.632 2.640 ; + RECT 0.216 3.312 10.632 3.408 ; + RECT 0.216 4.080 10.632 4.176 ; + RECT 0.216 4.848 10.632 4.944 ; + RECT 0.216 5.616 10.632 5.712 ; + RECT 0.216 6.384 10.632 6.480 ; + RECT 0.216 7.152 10.632 7.248 ; + RECT 0.216 7.920 10.632 8.016 ; + RECT 0.216 8.688 10.632 8.784 ; + RECT 0.216 9.456 10.632 9.552 ; + RECT 0.216 10.224 10.632 10.320 ; + RECT 0.216 10.992 10.632 11.088 ; + RECT 0.216 11.760 10.632 11.856 ; + RECT 0.216 12.528 10.632 12.624 ; + RECT 0.216 13.296 10.632 13.392 ; + RECT 0.216 14.064 10.632 14.160 ; + RECT 0.216 14.832 10.632 14.928 ; + RECT 0.216 15.600 10.632 15.696 ; + RECT 0.216 16.368 10.632 16.464 ; + RECT 0.216 17.136 10.632 17.232 ; + RECT 0.216 17.904 10.632 18.000 ; + RECT 0.216 18.672 10.632 18.768 ; + RECT 0.216 19.440 10.632 19.536 ; + RECT 0.216 20.208 10.632 20.304 ; + RECT 0.216 20.976 10.632 21.072 ; + RECT 0.216 21.744 10.632 21.840 ; + RECT 0.216 22.512 10.632 22.608 ; + RECT 0.216 23.280 10.632 23.376 ; + RECT 0.216 24.048 10.632 24.144 ; + RECT 0.216 24.816 10.632 24.912 ; + RECT 0.216 25.584 10.632 25.680 ; + RECT 0.216 26.352 10.632 26.448 ; + RECT 0.216 27.120 10.632 27.216 ; + RECT 0.216 27.888 10.632 27.984 ; + RECT 0.216 28.656 10.632 28.752 ; + RECT 0.216 29.424 10.632 29.520 ; + RECT 0.216 30.192 10.632 30.288 ; + RECT 0.216 30.960 10.632 31.056 ; + RECT 0.216 31.728 10.632 31.824 ; + RECT 0.216 32.496 10.632 32.592 ; + RECT 0.216 33.264 10.632 33.360 ; + RECT 0.216 34.032 10.632 34.128 ; + RECT 0.216 34.800 10.632 34.896 ; + RECT 0.216 35.568 10.632 35.664 ; + RECT 0.216 36.336 10.632 36.432 ; + RECT 0.216 37.104 10.632 37.200 ; + RECT 0.216 37.872 10.632 37.968 ; + RECT 0.216 38.640 10.632 38.736 ; + RECT 0.216 39.408 10.632 39.504 ; + RECT 0.216 40.176 10.632 40.272 ; + RECT 0.216 40.944 10.632 41.040 ; + RECT 0.216 41.712 10.632 41.808 ; + RECT 0.216 42.480 10.632 42.576 ; + RECT 0.216 43.248 10.632 43.344 ; + RECT 0.216 44.016 10.632 44.112 ; + RECT 0.216 44.784 10.632 44.880 ; + RECT 0.216 45.552 10.632 45.648 ; + RECT 0.216 46.320 10.632 46.416 ; + RECT 0.216 47.088 10.632 47.184 ; + RECT 0.216 47.856 10.632 47.952 ; + RECT 0.216 48.624 10.632 48.720 ; + RECT 0.216 49.392 10.632 49.488 ; + RECT 0.216 50.160 10.632 50.256 ; + RECT 0.216 50.928 10.632 51.024 ; + RECT 0.216 51.696 10.632 51.792 ; + RECT 0.216 52.464 10.632 52.560 ; + RECT 0.216 53.232 10.632 53.328 ; + RECT 0.216 54.000 10.632 54.096 ; + RECT 0.216 54.768 10.632 54.864 ; + RECT 0.216 55.536 10.632 55.632 ; + RECT 0.216 56.304 10.632 56.400 ; + RECT 0.216 57.072 10.632 57.168 ; + RECT 0.216 57.840 10.632 57.936 ; + RECT 0.216 58.608 10.632 58.704 ; + RECT 0.216 59.376 10.632 59.472 ; + RECT 0.216 60.144 10.632 60.240 ; + RECT 0.216 60.912 10.632 61.008 ; + RECT 0.216 61.680 10.632 61.776 ; + RECT 0.216 62.448 10.632 62.544 ; + RECT 0.216 63.216 10.632 63.312 ; + RECT 0.216 63.984 10.632 64.080 ; + RECT 0.216 64.752 10.632 64.848 ; + RECT 0.216 65.520 10.632 65.616 ; + RECT 0.216 66.288 10.632 66.384 ; + RECT 0.216 67.056 10.632 67.152 ; + RECT 0.216 67.824 10.632 67.920 ; + RECT 0.216 68.592 10.632 68.688 ; + RECT 0.216 69.360 10.632 69.456 ; + RECT 0.216 70.128 10.632 70.224 ; + RECT 0.216 70.896 10.632 70.992 ; + RECT 0.216 71.664 10.632 71.760 ; + RECT 0.216 72.432 10.632 72.528 ; + RECT 0.216 73.200 10.632 73.296 ; + RECT 0.216 73.968 10.632 74.064 ; + RECT 0.216 74.736 10.632 74.832 ; + RECT 0.216 75.504 10.632 75.600 ; + RECT 0.216 76.272 10.632 76.368 ; + RECT 0.216 77.040 10.632 77.136 ; + RECT 0.216 77.808 10.632 77.904 ; + RECT 0.216 78.576 10.632 78.672 ; + RECT 0.216 79.344 10.632 79.440 ; + RECT 0.216 80.112 10.632 80.208 ; + RECT 0.216 80.880 10.632 80.976 ; + RECT 0.216 81.648 10.632 81.744 ; + RECT 0.216 82.416 10.632 82.512 ; + RECT 0.216 83.184 10.632 83.280 ; + RECT 0.216 83.952 10.632 84.048 ; + RECT 0.216 84.720 10.632 84.816 ; + RECT 0.216 85.488 10.632 85.584 ; + RECT 0.216 86.256 10.632 86.352 ; + RECT 0.216 87.024 10.632 87.120 ; + RECT 0.216 87.792 10.632 87.888 ; + RECT 0.216 88.560 10.632 88.656 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 10.632 0.336 ; + RECT 0.216 1.008 10.632 1.104 ; + RECT 0.216 1.776 10.632 1.872 ; + RECT 0.216 2.544 10.632 2.640 ; + RECT 0.216 3.312 10.632 3.408 ; + RECT 0.216 4.080 10.632 4.176 ; + RECT 0.216 4.848 10.632 4.944 ; + RECT 0.216 5.616 10.632 5.712 ; + RECT 0.216 6.384 10.632 6.480 ; + RECT 0.216 7.152 10.632 7.248 ; + RECT 0.216 7.920 10.632 8.016 ; + RECT 0.216 8.688 10.632 8.784 ; + RECT 0.216 9.456 10.632 9.552 ; + RECT 0.216 10.224 10.632 10.320 ; + RECT 0.216 10.992 10.632 11.088 ; + RECT 0.216 11.760 10.632 11.856 ; + RECT 0.216 12.528 10.632 12.624 ; + RECT 0.216 13.296 10.632 13.392 ; + RECT 0.216 14.064 10.632 14.160 ; + RECT 0.216 14.832 10.632 14.928 ; + RECT 0.216 15.600 10.632 15.696 ; + RECT 0.216 16.368 10.632 16.464 ; + RECT 0.216 17.136 10.632 17.232 ; + RECT 0.216 17.904 10.632 18.000 ; + RECT 0.216 18.672 10.632 18.768 ; + RECT 0.216 19.440 10.632 19.536 ; + RECT 0.216 20.208 10.632 20.304 ; + RECT 0.216 20.976 10.632 21.072 ; + RECT 0.216 21.744 10.632 21.840 ; + RECT 0.216 22.512 10.632 22.608 ; + RECT 0.216 23.280 10.632 23.376 ; + RECT 0.216 24.048 10.632 24.144 ; + RECT 0.216 24.816 10.632 24.912 ; + RECT 0.216 25.584 10.632 25.680 ; + RECT 0.216 26.352 10.632 26.448 ; + RECT 0.216 27.120 10.632 27.216 ; + RECT 0.216 27.888 10.632 27.984 ; + RECT 0.216 28.656 10.632 28.752 ; + RECT 0.216 29.424 10.632 29.520 ; + RECT 0.216 30.192 10.632 30.288 ; + RECT 0.216 30.960 10.632 31.056 ; + RECT 0.216 31.728 10.632 31.824 ; + RECT 0.216 32.496 10.632 32.592 ; + RECT 0.216 33.264 10.632 33.360 ; + RECT 0.216 34.032 10.632 34.128 ; + RECT 0.216 34.800 10.632 34.896 ; + RECT 0.216 35.568 10.632 35.664 ; + RECT 0.216 36.336 10.632 36.432 ; + RECT 0.216 37.104 10.632 37.200 ; + RECT 0.216 37.872 10.632 37.968 ; + RECT 0.216 38.640 10.632 38.736 ; + RECT 0.216 39.408 10.632 39.504 ; + RECT 0.216 40.176 10.632 40.272 ; + RECT 0.216 40.944 10.632 41.040 ; + RECT 0.216 41.712 10.632 41.808 ; + RECT 0.216 42.480 10.632 42.576 ; + RECT 0.216 43.248 10.632 43.344 ; + RECT 0.216 44.016 10.632 44.112 ; + RECT 0.216 44.784 10.632 44.880 ; + RECT 0.216 45.552 10.632 45.648 ; + RECT 0.216 46.320 10.632 46.416 ; + RECT 0.216 47.088 10.632 47.184 ; + RECT 0.216 47.856 10.632 47.952 ; + RECT 0.216 48.624 10.632 48.720 ; + RECT 0.216 49.392 10.632 49.488 ; + RECT 0.216 50.160 10.632 50.256 ; + RECT 0.216 50.928 10.632 51.024 ; + RECT 0.216 51.696 10.632 51.792 ; + RECT 0.216 52.464 10.632 52.560 ; + RECT 0.216 53.232 10.632 53.328 ; + RECT 0.216 54.000 10.632 54.096 ; + RECT 0.216 54.768 10.632 54.864 ; + RECT 0.216 55.536 10.632 55.632 ; + RECT 0.216 56.304 10.632 56.400 ; + RECT 0.216 57.072 10.632 57.168 ; + RECT 0.216 57.840 10.632 57.936 ; + RECT 0.216 58.608 10.632 58.704 ; + RECT 0.216 59.376 10.632 59.472 ; + RECT 0.216 60.144 10.632 60.240 ; + RECT 0.216 60.912 10.632 61.008 ; + RECT 0.216 61.680 10.632 61.776 ; + RECT 0.216 62.448 10.632 62.544 ; + RECT 0.216 63.216 10.632 63.312 ; + RECT 0.216 63.984 10.632 64.080 ; + RECT 0.216 64.752 10.632 64.848 ; + RECT 0.216 65.520 10.632 65.616 ; + RECT 0.216 66.288 10.632 66.384 ; + RECT 0.216 67.056 10.632 67.152 ; + RECT 0.216 67.824 10.632 67.920 ; + RECT 0.216 68.592 10.632 68.688 ; + RECT 0.216 69.360 10.632 69.456 ; + RECT 0.216 70.128 10.632 70.224 ; + RECT 0.216 70.896 10.632 70.992 ; + RECT 0.216 71.664 10.632 71.760 ; + RECT 0.216 72.432 10.632 72.528 ; + RECT 0.216 73.200 10.632 73.296 ; + RECT 0.216 73.968 10.632 74.064 ; + RECT 0.216 74.736 10.632 74.832 ; + RECT 0.216 75.504 10.632 75.600 ; + RECT 0.216 76.272 10.632 76.368 ; + RECT 0.216 77.040 10.632 77.136 ; + RECT 0.216 77.808 10.632 77.904 ; + RECT 0.216 78.576 10.632 78.672 ; + RECT 0.216 79.344 10.632 79.440 ; + RECT 0.216 80.112 10.632 80.208 ; + RECT 0.216 80.880 10.632 80.976 ; + RECT 0.216 81.648 10.632 81.744 ; + RECT 0.216 82.416 10.632 82.512 ; + RECT 0.216 83.184 10.632 83.280 ; + RECT 0.216 83.952 10.632 84.048 ; + RECT 0.216 84.720 10.632 84.816 ; + RECT 0.216 85.488 10.632 85.584 ; + RECT 0.216 86.256 10.632 86.352 ; + RECT 0.216 87.024 10.632 87.120 ; + RECT 0.216 87.792 10.632 87.888 ; + RECT 0.216 88.560 10.632 88.656 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 10.848 88.723 ; + LAYER M2 ; + RECT 0 0 10.848 88.723 ; + LAYER M3 ; + RECT 0 0 10.848 88.723 ; + LAYER M4 ; + RECT 0 0 10.848 88.723 ; + END +END fakeram_72x512_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_72x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_72x80_1r1w.lef new file mode 100644 index 0000000..7df092a --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_72x80_1r1w.lef @@ -0,0 +1,1551 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_72x80_1r1w + FOREIGN fakeram_72x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 21.696 BY 19.419 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 0.276 21.696 0.300 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 0.996 21.696 1.020 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 1.716 21.696 1.740 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 2.436 21.696 2.460 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 3.156 21.696 3.180 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 3.876 21.696 3.900 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 4.596 21.696 4.620 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 5.316 21.696 5.340 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 6.036 21.696 6.060 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 6.756 21.696 6.780 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 7.476 21.696 7.500 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 8.196 21.696 8.220 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 8.916 21.696 8.940 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 9.636 21.696 9.660 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 10.356 21.696 10.380 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 11.076 21.696 11.100 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 11.796 21.696 11.820 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 12.516 21.696 12.540 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[71] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 19.365 0.225 19.419 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 19.365 0.729 19.419 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 19.365 1.233 19.419 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 19.365 1.737 19.419 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 19.365 2.241 19.419 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 19.365 2.745 19.419 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 19.365 3.249 19.419 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 19.365 3.753 19.419 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 19.365 4.257 19.419 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 19.365 4.761 19.419 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 19.365 5.265 19.419 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 19.365 5.769 19.419 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 19.365 6.273 19.419 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 19.365 6.777 19.419 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 19.365 7.281 19.419 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 19.365 7.785 19.419 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 19.365 8.289 19.419 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 19.365 8.793 19.419 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 19.365 9.297 19.419 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 19.365 9.801 19.419 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 19.365 10.305 19.419 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 19.365 10.809 19.419 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 19.365 11.313 19.419 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 19.365 11.817 19.419 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 19.365 12.321 19.419 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 19.365 12.825 19.419 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 19.365 13.329 19.419 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 19.365 13.833 19.419 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 19.365 14.337 19.419 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 19.365 14.841 19.419 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 19.365 15.345 19.419 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 19.365 15.849 19.419 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 19.365 16.353 19.419 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 19.365 16.857 19.419 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 19.365 17.361 19.419 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 19.365 17.865 19.419 ; + END + END r0_rd_out[71] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 13.236 21.696 13.260 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 13.956 21.696 13.980 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 14.676 21.696 14.700 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 15.396 21.696 15.420 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 16.116 21.696 16.140 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 21.624 16.836 21.696 16.860 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 19.365 18.369 19.419 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 19.365 18.873 19.419 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 19.365 19.377 19.419 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 19.365 19.881 19.419 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 19.365 20.385 19.419 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 21.480 0.336 ; + RECT 0.216 1.008 21.480 1.104 ; + RECT 0.216 1.776 21.480 1.872 ; + RECT 0.216 2.544 21.480 2.640 ; + RECT 0.216 3.312 21.480 3.408 ; + RECT 0.216 4.080 21.480 4.176 ; + RECT 0.216 4.848 21.480 4.944 ; + RECT 0.216 5.616 21.480 5.712 ; + RECT 0.216 6.384 21.480 6.480 ; + RECT 0.216 7.152 21.480 7.248 ; + RECT 0.216 7.920 21.480 8.016 ; + RECT 0.216 8.688 21.480 8.784 ; + RECT 0.216 9.456 21.480 9.552 ; + RECT 0.216 10.224 21.480 10.320 ; + RECT 0.216 10.992 21.480 11.088 ; + RECT 0.216 11.760 21.480 11.856 ; + RECT 0.216 12.528 21.480 12.624 ; + RECT 0.216 13.296 21.480 13.392 ; + RECT 0.216 14.064 21.480 14.160 ; + RECT 0.216 14.832 21.480 14.928 ; + RECT 0.216 15.600 21.480 15.696 ; + RECT 0.216 16.368 21.480 16.464 ; + RECT 0.216 17.136 21.480 17.232 ; + RECT 0.216 17.904 21.480 18.000 ; + RECT 0.216 18.672 21.480 18.768 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 21.480 0.336 ; + RECT 0.216 1.008 21.480 1.104 ; + RECT 0.216 1.776 21.480 1.872 ; + RECT 0.216 2.544 21.480 2.640 ; + RECT 0.216 3.312 21.480 3.408 ; + RECT 0.216 4.080 21.480 4.176 ; + RECT 0.216 4.848 21.480 4.944 ; + RECT 0.216 5.616 21.480 5.712 ; + RECT 0.216 6.384 21.480 6.480 ; + RECT 0.216 7.152 21.480 7.248 ; + RECT 0.216 7.920 21.480 8.016 ; + RECT 0.216 8.688 21.480 8.784 ; + RECT 0.216 9.456 21.480 9.552 ; + RECT 0.216 10.224 21.480 10.320 ; + RECT 0.216 10.992 21.480 11.088 ; + RECT 0.216 11.760 21.480 11.856 ; + RECT 0.216 12.528 21.480 12.624 ; + RECT 0.216 13.296 21.480 13.392 ; + RECT 0.216 14.064 21.480 14.160 ; + RECT 0.216 14.832 21.480 14.928 ; + RECT 0.216 15.600 21.480 15.696 ; + RECT 0.216 16.368 21.480 16.464 ; + RECT 0.216 17.136 21.480 17.232 ; + RECT 0.216 17.904 21.480 18.000 ; + RECT 0.216 18.672 21.480 18.768 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 21.696 19.419 ; + LAYER M2 ; + RECT 0 0 21.696 19.419 ; + LAYER M3 ; + RECT 0 0 21.696 19.419 ; + LAYER M4 ; + RECT 0 0 21.696 19.419 ; + END +END fakeram_72x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_7x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_7x256_1r1w.lef new file mode 100644 index 0000000..5b7e952 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_7x256_1r1w.lef @@ -0,0 +1,463 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_7x256_1r1w + FOREIGN fakeram_7x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 43.441 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.548 0.072 4.572 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.548 9.643 4.572 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.323 0.000 1.341 0.054 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.439 0.000 2.457 0.054 ; + END + END w0_wd_in[6] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.555 0.000 3.573 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.671 0.000 4.689 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.903 0.000 6.921 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 43.387 0.225 43.441 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 43.387 1.233 43.441 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 43.387 2.241 43.441 ; + END + END r0_rd_out[6] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.820 0.072 8.844 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.364 0.072 17.388 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.636 0.072 21.660 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.820 9.643 8.844 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 13.092 9.643 13.116 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 17.364 9.643 17.388 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 21.636 9.643 21.660 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.180 0.072 30.204 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.452 0.072 34.476 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.724 0.072 38.748 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 25.908 9.643 25.932 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 30.180 9.643 30.204 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 34.452 9.643 34.476 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 38.724 9.643 38.748 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 43.387 3.249 43.441 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 43.387 4.257 43.441 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 43.387 5.265 43.441 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 43.387 6.273 43.441 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 43.387 7.281 43.441 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 43.441 ; + LAYER M2 ; + RECT 0 0 9.643 43.441 ; + LAYER M3 ; + RECT 0 0 9.643 43.441 ; + LAYER M4 ; + RECT 0 0 9.643 43.441 ; + END +END fakeram_7x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_80x20_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_80x20_1r1w.lef new file mode 100644 index 0000000..4b92d3e --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_80x20_1r1w.lef @@ -0,0 +1,1635 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_80x20_1r1w + FOREIGN fakeram_80x20_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 24.106 BY 10.045 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.612 0.072 0.636 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.956 0.072 1.980 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.628 0.072 2.652 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.972 0.072 3.996 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.644 0.072 4.668 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.988 0.072 6.012 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.660 0.072 6.684 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 0.276 24.106 0.300 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 0.612 24.106 0.636 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 0.948 24.106 0.972 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 1.284 24.106 1.308 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 1.620 24.106 1.644 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 1.956 24.106 1.980 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 2.292 24.106 2.316 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 2.628 24.106 2.652 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 2.964 24.106 2.988 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 3.300 24.106 3.324 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 3.636 24.106 3.660 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 3.972 24.106 3.996 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 4.308 24.106 4.332 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 4.644 24.106 4.668 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 4.980 24.106 5.004 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 5.316 24.106 5.340 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 5.652 24.106 5.676 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 5.988 24.106 6.012 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 6.324 24.106 6.348 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 6.660 24.106 6.684 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[79] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 9.991 0.225 10.045 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 9.991 0.729 10.045 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 9.991 1.233 10.045 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 9.991 1.737 10.045 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 9.991 2.241 10.045 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 9.991 2.745 10.045 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 9.991 3.249 10.045 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 9.991 3.753 10.045 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 9.991 4.257 10.045 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 9.991 4.761 10.045 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 9.991 5.265 10.045 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 9.991 5.769 10.045 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 9.991 6.273 10.045 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 9.991 6.777 10.045 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 9.991 7.281 10.045 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 9.991 7.785 10.045 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 9.991 8.289 10.045 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 9.991 8.793 10.045 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 9.991 9.297 10.045 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 9.991 9.801 10.045 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 9.991 10.305 10.045 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 9.991 10.809 10.045 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 9.991 11.313 10.045 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 9.991 11.817 10.045 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 9.991 12.321 10.045 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 9.991 12.825 10.045 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 9.991 13.329 10.045 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 9.991 13.833 10.045 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 9.991 14.337 10.045 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 9.991 14.841 10.045 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 9.991 15.345 10.045 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 9.991 15.849 10.045 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 9.991 16.353 10.045 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 9.991 16.857 10.045 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 9.991 17.361 10.045 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 9.991 17.865 10.045 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 9.991 18.369 10.045 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 9.991 18.873 10.045 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 9.991 19.377 10.045 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 9.991 19.881 10.045 ; + END + END r0_rd_out[79] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 6.996 24.106 7.020 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 7.332 24.106 7.356 ; + END + END w0_addr_in[4] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.676 0.072 8.700 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 7.668 24.106 7.692 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 8.004 24.106 8.028 ; + END + END r0_addr_in[4] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 9.991 20.385 10.045 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.871 9.991 20.889 10.045 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.375 9.991 21.393 10.045 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.879 9.991 21.897 10.045 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 9.991 22.401 10.045 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 23.890 0.336 ; + RECT 0.216 1.008 23.890 1.104 ; + RECT 0.216 1.776 23.890 1.872 ; + RECT 0.216 2.544 23.890 2.640 ; + RECT 0.216 3.312 23.890 3.408 ; + RECT 0.216 4.080 23.890 4.176 ; + RECT 0.216 4.848 23.890 4.944 ; + RECT 0.216 5.616 23.890 5.712 ; + RECT 0.216 6.384 23.890 6.480 ; + RECT 0.216 7.152 23.890 7.248 ; + RECT 0.216 7.920 23.890 8.016 ; + RECT 0.216 8.688 23.890 8.784 ; + RECT 0.216 9.456 23.890 9.552 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 23.890 0.336 ; + RECT 0.216 1.008 23.890 1.104 ; + RECT 0.216 1.776 23.890 1.872 ; + RECT 0.216 2.544 23.890 2.640 ; + RECT 0.216 3.312 23.890 3.408 ; + RECT 0.216 4.080 23.890 4.176 ; + RECT 0.216 4.848 23.890 4.944 ; + RECT 0.216 5.616 23.890 5.712 ; + RECT 0.216 6.384 23.890 6.480 ; + RECT 0.216 7.152 23.890 7.248 ; + RECT 0.216 7.920 23.890 8.016 ; + RECT 0.216 8.688 23.890 8.784 ; + RECT 0.216 9.456 23.890 9.552 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 24.106 10.045 ; + LAYER M2 ; + RECT 0 0 24.106 10.045 ; + LAYER M3 ; + RECT 0 0 24.106 10.045 ; + LAYER M4 ; + RECT 0 0 24.106 10.045 ; + END +END fakeram_80x20_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_80x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_80x256_1r1w.lef new file mode 100644 index 0000000..7bb6823 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_80x256_1r1w.lef @@ -0,0 +1,1793 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_80x256_1r1w + FOREIGN fakeram_80x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 24.106 BY 49.551 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 0.276 24.106 0.300 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 2.004 24.106 2.028 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 3.732 24.106 3.756 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 5.460 24.106 5.484 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 7.188 24.106 7.212 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 8.916 24.106 8.940 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 10.644 24.106 10.668 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 12.372 24.106 12.396 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 14.100 24.106 14.124 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 15.828 24.106 15.852 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 17.556 24.106 17.580 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 19.284 24.106 19.308 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 21.012 24.106 21.036 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 22.740 24.106 22.764 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 24.468 24.106 24.492 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 26.196 24.106 26.220 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 27.924 24.106 27.948 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 29.652 24.106 29.676 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 31.380 24.106 31.404 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 33.108 24.106 33.132 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[79] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 49.497 0.225 49.551 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 49.497 0.729 49.551 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 49.497 1.233 49.551 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 49.497 1.737 49.551 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 49.497 2.241 49.551 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 49.497 2.745 49.551 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 49.497 3.249 49.551 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 49.497 3.753 49.551 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 49.497 4.257 49.551 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 49.497 4.761 49.551 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 49.497 5.265 49.551 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 49.497 5.769 49.551 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 49.497 6.273 49.551 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 49.497 6.777 49.551 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 49.497 7.281 49.551 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 49.497 7.785 49.551 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 49.497 8.289 49.551 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 49.497 8.793 49.551 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 49.497 9.297 49.551 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 49.497 9.801 49.551 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 49.497 10.305 49.551 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 49.497 10.809 49.551 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 49.497 11.313 49.551 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 49.497 11.817 49.551 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 49.497 12.321 49.551 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 49.497 12.825 49.551 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 49.497 13.329 49.551 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 49.497 13.833 49.551 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 49.497 14.337 49.551 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 49.497 14.841 49.551 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 49.497 15.345 49.551 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 49.497 15.849 49.551 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 49.497 16.353 49.551 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 49.497 16.857 49.551 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 49.497 17.361 49.551 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 49.497 17.865 49.551 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 49.497 18.369 49.551 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 49.497 18.873 49.551 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 49.497 19.377 49.551 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 49.497 19.881 49.551 ; + END + END r0_rd_out[79] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 34.836 24.106 34.860 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 36.564 24.106 36.588 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 38.292 24.106 38.316 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 40.020 24.106 40.044 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.748 0.072 41.772 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.476 0.072 43.500 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.204 0.072 45.228 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.932 0.072 46.956 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 41.748 24.106 41.772 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 43.476 24.106 43.500 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 45.204 24.106 45.228 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.034 46.932 24.106 46.956 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 49.497 20.385 49.551 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.871 49.497 20.889 49.551 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.375 49.497 21.393 49.551 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.879 49.497 21.897 49.551 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 49.497 22.401 49.551 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 23.890 0.336 ; + RECT 0.216 1.008 23.890 1.104 ; + RECT 0.216 1.776 23.890 1.872 ; + RECT 0.216 2.544 23.890 2.640 ; + RECT 0.216 3.312 23.890 3.408 ; + RECT 0.216 4.080 23.890 4.176 ; + RECT 0.216 4.848 23.890 4.944 ; + RECT 0.216 5.616 23.890 5.712 ; + RECT 0.216 6.384 23.890 6.480 ; + RECT 0.216 7.152 23.890 7.248 ; + RECT 0.216 7.920 23.890 8.016 ; + RECT 0.216 8.688 23.890 8.784 ; + RECT 0.216 9.456 23.890 9.552 ; + RECT 0.216 10.224 23.890 10.320 ; + RECT 0.216 10.992 23.890 11.088 ; + RECT 0.216 11.760 23.890 11.856 ; + RECT 0.216 12.528 23.890 12.624 ; + RECT 0.216 13.296 23.890 13.392 ; + RECT 0.216 14.064 23.890 14.160 ; + RECT 0.216 14.832 23.890 14.928 ; + RECT 0.216 15.600 23.890 15.696 ; + RECT 0.216 16.368 23.890 16.464 ; + RECT 0.216 17.136 23.890 17.232 ; + RECT 0.216 17.904 23.890 18.000 ; + RECT 0.216 18.672 23.890 18.768 ; + RECT 0.216 19.440 23.890 19.536 ; + RECT 0.216 20.208 23.890 20.304 ; + RECT 0.216 20.976 23.890 21.072 ; + RECT 0.216 21.744 23.890 21.840 ; + RECT 0.216 22.512 23.890 22.608 ; + RECT 0.216 23.280 23.890 23.376 ; + RECT 0.216 24.048 23.890 24.144 ; + RECT 0.216 24.816 23.890 24.912 ; + RECT 0.216 25.584 23.890 25.680 ; + RECT 0.216 26.352 23.890 26.448 ; + RECT 0.216 27.120 23.890 27.216 ; + RECT 0.216 27.888 23.890 27.984 ; + RECT 0.216 28.656 23.890 28.752 ; + RECT 0.216 29.424 23.890 29.520 ; + RECT 0.216 30.192 23.890 30.288 ; + RECT 0.216 30.960 23.890 31.056 ; + RECT 0.216 31.728 23.890 31.824 ; + RECT 0.216 32.496 23.890 32.592 ; + RECT 0.216 33.264 23.890 33.360 ; + RECT 0.216 34.032 23.890 34.128 ; + RECT 0.216 34.800 23.890 34.896 ; + RECT 0.216 35.568 23.890 35.664 ; + RECT 0.216 36.336 23.890 36.432 ; + RECT 0.216 37.104 23.890 37.200 ; + RECT 0.216 37.872 23.890 37.968 ; + RECT 0.216 38.640 23.890 38.736 ; + RECT 0.216 39.408 23.890 39.504 ; + RECT 0.216 40.176 23.890 40.272 ; + RECT 0.216 40.944 23.890 41.040 ; + RECT 0.216 41.712 23.890 41.808 ; + RECT 0.216 42.480 23.890 42.576 ; + RECT 0.216 43.248 23.890 43.344 ; + RECT 0.216 44.016 23.890 44.112 ; + RECT 0.216 44.784 23.890 44.880 ; + RECT 0.216 45.552 23.890 45.648 ; + RECT 0.216 46.320 23.890 46.416 ; + RECT 0.216 47.088 23.890 47.184 ; + RECT 0.216 47.856 23.890 47.952 ; + RECT 0.216 48.624 23.890 48.720 ; + RECT 0.216 49.392 23.890 49.488 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 23.890 0.336 ; + RECT 0.216 1.008 23.890 1.104 ; + RECT 0.216 1.776 23.890 1.872 ; + RECT 0.216 2.544 23.890 2.640 ; + RECT 0.216 3.312 23.890 3.408 ; + RECT 0.216 4.080 23.890 4.176 ; + RECT 0.216 4.848 23.890 4.944 ; + RECT 0.216 5.616 23.890 5.712 ; + RECT 0.216 6.384 23.890 6.480 ; + RECT 0.216 7.152 23.890 7.248 ; + RECT 0.216 7.920 23.890 8.016 ; + RECT 0.216 8.688 23.890 8.784 ; + RECT 0.216 9.456 23.890 9.552 ; + RECT 0.216 10.224 23.890 10.320 ; + RECT 0.216 10.992 23.890 11.088 ; + RECT 0.216 11.760 23.890 11.856 ; + RECT 0.216 12.528 23.890 12.624 ; + RECT 0.216 13.296 23.890 13.392 ; + RECT 0.216 14.064 23.890 14.160 ; + RECT 0.216 14.832 23.890 14.928 ; + RECT 0.216 15.600 23.890 15.696 ; + RECT 0.216 16.368 23.890 16.464 ; + RECT 0.216 17.136 23.890 17.232 ; + RECT 0.216 17.904 23.890 18.000 ; + RECT 0.216 18.672 23.890 18.768 ; + RECT 0.216 19.440 23.890 19.536 ; + RECT 0.216 20.208 23.890 20.304 ; + RECT 0.216 20.976 23.890 21.072 ; + RECT 0.216 21.744 23.890 21.840 ; + RECT 0.216 22.512 23.890 22.608 ; + RECT 0.216 23.280 23.890 23.376 ; + RECT 0.216 24.048 23.890 24.144 ; + RECT 0.216 24.816 23.890 24.912 ; + RECT 0.216 25.584 23.890 25.680 ; + RECT 0.216 26.352 23.890 26.448 ; + RECT 0.216 27.120 23.890 27.216 ; + RECT 0.216 27.888 23.890 27.984 ; + RECT 0.216 28.656 23.890 28.752 ; + RECT 0.216 29.424 23.890 29.520 ; + RECT 0.216 30.192 23.890 30.288 ; + RECT 0.216 30.960 23.890 31.056 ; + RECT 0.216 31.728 23.890 31.824 ; + RECT 0.216 32.496 23.890 32.592 ; + RECT 0.216 33.264 23.890 33.360 ; + RECT 0.216 34.032 23.890 34.128 ; + RECT 0.216 34.800 23.890 34.896 ; + RECT 0.216 35.568 23.890 35.664 ; + RECT 0.216 36.336 23.890 36.432 ; + RECT 0.216 37.104 23.890 37.200 ; + RECT 0.216 37.872 23.890 37.968 ; + RECT 0.216 38.640 23.890 38.736 ; + RECT 0.216 39.408 23.890 39.504 ; + RECT 0.216 40.176 23.890 40.272 ; + RECT 0.216 40.944 23.890 41.040 ; + RECT 0.216 41.712 23.890 41.808 ; + RECT 0.216 42.480 23.890 42.576 ; + RECT 0.216 43.248 23.890 43.344 ; + RECT 0.216 44.016 23.890 44.112 ; + RECT 0.216 44.784 23.890 44.880 ; + RECT 0.216 45.552 23.890 45.648 ; + RECT 0.216 46.320 23.890 46.416 ; + RECT 0.216 47.088 23.890 47.184 ; + RECT 0.216 47.856 23.890 47.952 ; + RECT 0.216 48.624 23.890 48.720 ; + RECT 0.216 49.392 23.890 49.488 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 24.106 49.551 ; + LAYER M2 ; + RECT 0 0 24.106 49.551 ; + LAYER M3 ; + RECT 0 0 24.106 49.551 ; + LAYER M4 ; + RECT 0 0 24.106 49.551 ; + END +END fakeram_80x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_82x160_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_82x160_1r1w.lef new file mode 100644 index 0000000..1ac7593 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_82x160_1r1w.lef @@ -0,0 +1,1787 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_82x160_1r1w + FOREIGN fakeram_82x160_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 24.709 BY 33.648 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.380 0.072 1.404 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.484 0.072 2.508 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.796 0.072 5.820 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.004 0.072 8.028 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.420 0.072 12.444 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.628 0.072 14.652 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.044 0.072 19.068 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.252 0.072 21.276 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 0.276 24.709 0.300 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 1.380 24.709 1.404 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 2.484 24.709 2.508 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 3.588 24.709 3.612 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 4.692 24.709 4.716 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 5.796 24.709 5.820 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 6.900 24.709 6.924 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 8.004 24.709 8.028 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 9.108 24.709 9.132 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 10.212 24.709 10.236 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 11.316 24.709 11.340 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 12.420 24.709 12.444 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 13.524 24.709 13.548 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 14.628 24.709 14.652 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 15.732 24.709 15.756 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 16.836 24.709 16.860 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 17.940 24.709 17.964 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 19.044 24.709 19.068 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 20.148 24.709 20.172 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 21.252 24.709 21.276 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[81] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 33.594 0.225 33.648 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 33.594 0.729 33.648 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 33.594 1.233 33.648 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 33.594 1.737 33.648 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 33.594 2.241 33.648 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 33.594 2.745 33.648 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 33.594 3.249 33.648 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 33.594 3.753 33.648 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 33.594 4.257 33.648 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 33.594 4.761 33.648 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 33.594 5.265 33.648 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 33.594 5.769 33.648 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 33.594 6.273 33.648 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 33.594 6.777 33.648 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 33.594 7.281 33.648 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 33.594 7.785 33.648 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 33.594 8.289 33.648 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 33.594 8.793 33.648 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 33.594 9.297 33.648 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 33.594 9.801 33.648 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 33.594 10.305 33.648 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 33.594 10.809 33.648 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 33.594 11.313 33.648 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 33.594 11.817 33.648 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 33.594 12.321 33.648 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 33.594 12.825 33.648 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 33.594 13.329 33.648 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 33.594 13.833 33.648 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 33.594 14.337 33.648 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 33.594 14.841 33.648 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 33.594 15.345 33.648 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 33.594 15.849 33.648 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 33.594 16.353 33.648 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 33.594 16.857 33.648 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 33.594 17.361 33.648 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 33.594 17.865 33.648 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 33.594 18.369 33.648 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 33.594 18.873 33.648 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 33.594 19.377 33.648 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 33.594 19.881 33.648 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 33.594 20.385 33.648 ; + END + END r0_rd_out[81] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.564 0.072 24.588 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.668 0.072 25.692 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 22.356 24.709 22.380 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 23.460 24.709 23.484 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 24.564 24.709 24.588 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 25.668 24.709 25.692 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.876 0.072 27.900 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.980 0.072 29.004 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.188 0.072 31.212 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 26.772 24.709 26.796 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 27.876 24.709 27.900 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 28.980 24.709 29.004 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 30.084 24.709 30.108 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.871 33.594 20.889 33.648 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.375 33.594 21.393 33.648 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.879 33.594 21.897 33.648 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 33.594 22.401 33.648 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 33.594 22.905 33.648 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 24.493 0.336 ; + RECT 0.216 1.008 24.493 1.104 ; + RECT 0.216 1.776 24.493 1.872 ; + RECT 0.216 2.544 24.493 2.640 ; + RECT 0.216 3.312 24.493 3.408 ; + RECT 0.216 4.080 24.493 4.176 ; + RECT 0.216 4.848 24.493 4.944 ; + RECT 0.216 5.616 24.493 5.712 ; + RECT 0.216 6.384 24.493 6.480 ; + RECT 0.216 7.152 24.493 7.248 ; + RECT 0.216 7.920 24.493 8.016 ; + RECT 0.216 8.688 24.493 8.784 ; + RECT 0.216 9.456 24.493 9.552 ; + RECT 0.216 10.224 24.493 10.320 ; + RECT 0.216 10.992 24.493 11.088 ; + RECT 0.216 11.760 24.493 11.856 ; + RECT 0.216 12.528 24.493 12.624 ; + RECT 0.216 13.296 24.493 13.392 ; + RECT 0.216 14.064 24.493 14.160 ; + RECT 0.216 14.832 24.493 14.928 ; + RECT 0.216 15.600 24.493 15.696 ; + RECT 0.216 16.368 24.493 16.464 ; + RECT 0.216 17.136 24.493 17.232 ; + RECT 0.216 17.904 24.493 18.000 ; + RECT 0.216 18.672 24.493 18.768 ; + RECT 0.216 19.440 24.493 19.536 ; + RECT 0.216 20.208 24.493 20.304 ; + RECT 0.216 20.976 24.493 21.072 ; + RECT 0.216 21.744 24.493 21.840 ; + RECT 0.216 22.512 24.493 22.608 ; + RECT 0.216 23.280 24.493 23.376 ; + RECT 0.216 24.048 24.493 24.144 ; + RECT 0.216 24.816 24.493 24.912 ; + RECT 0.216 25.584 24.493 25.680 ; + RECT 0.216 26.352 24.493 26.448 ; + RECT 0.216 27.120 24.493 27.216 ; + RECT 0.216 27.888 24.493 27.984 ; + RECT 0.216 28.656 24.493 28.752 ; + RECT 0.216 29.424 24.493 29.520 ; + RECT 0.216 30.192 24.493 30.288 ; + RECT 0.216 30.960 24.493 31.056 ; + RECT 0.216 31.728 24.493 31.824 ; + RECT 0.216 32.496 24.493 32.592 ; + RECT 0.216 33.264 24.493 33.360 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 24.493 0.336 ; + RECT 0.216 1.008 24.493 1.104 ; + RECT 0.216 1.776 24.493 1.872 ; + RECT 0.216 2.544 24.493 2.640 ; + RECT 0.216 3.312 24.493 3.408 ; + RECT 0.216 4.080 24.493 4.176 ; + RECT 0.216 4.848 24.493 4.944 ; + RECT 0.216 5.616 24.493 5.712 ; + RECT 0.216 6.384 24.493 6.480 ; + RECT 0.216 7.152 24.493 7.248 ; + RECT 0.216 7.920 24.493 8.016 ; + RECT 0.216 8.688 24.493 8.784 ; + RECT 0.216 9.456 24.493 9.552 ; + RECT 0.216 10.224 24.493 10.320 ; + RECT 0.216 10.992 24.493 11.088 ; + RECT 0.216 11.760 24.493 11.856 ; + RECT 0.216 12.528 24.493 12.624 ; + RECT 0.216 13.296 24.493 13.392 ; + RECT 0.216 14.064 24.493 14.160 ; + RECT 0.216 14.832 24.493 14.928 ; + RECT 0.216 15.600 24.493 15.696 ; + RECT 0.216 16.368 24.493 16.464 ; + RECT 0.216 17.136 24.493 17.232 ; + RECT 0.216 17.904 24.493 18.000 ; + RECT 0.216 18.672 24.493 18.768 ; + RECT 0.216 19.440 24.493 19.536 ; + RECT 0.216 20.208 24.493 20.304 ; + RECT 0.216 20.976 24.493 21.072 ; + RECT 0.216 21.744 24.493 21.840 ; + RECT 0.216 22.512 24.493 22.608 ; + RECT 0.216 23.280 24.493 23.376 ; + RECT 0.216 24.048 24.493 24.144 ; + RECT 0.216 24.816 24.493 24.912 ; + RECT 0.216 25.584 24.493 25.680 ; + RECT 0.216 26.352 24.493 26.448 ; + RECT 0.216 27.120 24.493 27.216 ; + RECT 0.216 27.888 24.493 27.984 ; + RECT 0.216 28.656 24.493 28.752 ; + RECT 0.216 29.424 24.493 29.520 ; + RECT 0.216 30.192 24.493 30.288 ; + RECT 0.216 30.960 24.493 31.056 ; + RECT 0.216 31.728 24.493 31.824 ; + RECT 0.216 32.496 24.493 32.592 ; + RECT 0.216 33.264 24.493 33.360 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 24.709 33.648 ; + LAYER M2 ; + RECT 0 0 24.709 33.648 ; + LAYER M3 ; + RECT 0 0 24.709 33.648 ; + LAYER M4 ; + RECT 0 0 24.709 33.648 ; + END +END fakeram_82x160_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_82x248_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_82x248_1r1w.lef new file mode 100644 index 0000000..d288940 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_82x248_1r1w.lef @@ -0,0 +1,1825 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_82x248_1r1w + FOREIGN fakeram_82x248_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 24.709 BY 48.379 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.908 0.072 1.932 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.540 0.072 3.564 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.332 0.072 13.356 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.228 0.072 18.252 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.492 0.072 21.516 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.388 0.072 26.412 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.020 0.072 28.044 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.284 0.072 31.308 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.916 0.072 32.940 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 0.276 24.709 0.300 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 1.908 24.709 1.932 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 3.540 24.709 3.564 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 5.172 24.709 5.196 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 6.804 24.709 6.828 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 8.436 24.709 8.460 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 10.068 24.709 10.092 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 11.700 24.709 11.724 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 13.332 24.709 13.356 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 14.964 24.709 14.988 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 16.596 24.709 16.620 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 18.228 24.709 18.252 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 19.860 24.709 19.884 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 21.492 24.709 21.516 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 23.124 24.709 23.148 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 24.756 24.709 24.780 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 26.388 24.709 26.412 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 28.020 24.709 28.044 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 29.652 24.709 29.676 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 31.284 24.709 31.308 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[81] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 48.325 0.225 48.379 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.711 48.325 0.729 48.379 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 48.325 1.233 48.379 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.719 48.325 1.737 48.379 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 48.325 2.241 48.379 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 48.325 2.745 48.379 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 48.325 3.249 48.379 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.735 48.325 3.753 48.379 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 48.325 4.257 48.379 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.743 48.325 4.761 48.379 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 48.325 5.265 48.379 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.751 48.325 5.769 48.379 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 48.325 6.273 48.379 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.759 48.325 6.777 48.379 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 48.325 7.281 48.379 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 48.325 7.785 48.379 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 48.325 8.289 48.379 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.775 48.325 8.793 48.379 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.279 48.325 9.297 48.379 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.783 48.325 9.801 48.379 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 48.325 10.305 48.379 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.791 48.325 10.809 48.379 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.295 48.325 11.313 48.379 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.799 48.325 11.817 48.379 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 48.325 12.321 48.379 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 48.325 12.825 48.379 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.311 48.325 13.329 48.379 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.815 48.325 13.833 48.379 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 48.325 14.337 48.379 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.823 48.325 14.841 48.379 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 48.325 15.345 48.379 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.831 48.325 15.849 48.379 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 48.325 16.353 48.379 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.839 48.325 16.857 48.379 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.343 48.325 17.361 48.379 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 48.325 17.865 48.379 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 48.325 18.369 48.379 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.855 48.325 18.873 48.379 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.359 48.325 19.377 48.379 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.863 48.325 19.881 48.379 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 48.325 20.385 48.379 ; + END + END r0_rd_out[81] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.180 0.072 36.204 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.812 0.072 37.836 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 32.916 24.709 32.940 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 34.548 24.709 34.572 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 36.180 24.709 36.204 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 37.812 24.709 37.836 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.076 0.072 41.100 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.708 0.072 42.732 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.340 0.072 44.364 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.972 0.072 45.996 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 39.444 24.709 39.468 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 41.076 24.709 41.100 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 42.708 24.709 42.732 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 24.637 44.340 24.709 44.364 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.871 48.325 20.889 48.379 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.375 48.325 21.393 48.379 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.879 48.325 21.897 48.379 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 48.325 22.401 48.379 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 48.325 22.905 48.379 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 24.493 0.336 ; + RECT 0.216 1.008 24.493 1.104 ; + RECT 0.216 1.776 24.493 1.872 ; + RECT 0.216 2.544 24.493 2.640 ; + RECT 0.216 3.312 24.493 3.408 ; + RECT 0.216 4.080 24.493 4.176 ; + RECT 0.216 4.848 24.493 4.944 ; + RECT 0.216 5.616 24.493 5.712 ; + RECT 0.216 6.384 24.493 6.480 ; + RECT 0.216 7.152 24.493 7.248 ; + RECT 0.216 7.920 24.493 8.016 ; + RECT 0.216 8.688 24.493 8.784 ; + RECT 0.216 9.456 24.493 9.552 ; + RECT 0.216 10.224 24.493 10.320 ; + RECT 0.216 10.992 24.493 11.088 ; + RECT 0.216 11.760 24.493 11.856 ; + RECT 0.216 12.528 24.493 12.624 ; + RECT 0.216 13.296 24.493 13.392 ; + RECT 0.216 14.064 24.493 14.160 ; + RECT 0.216 14.832 24.493 14.928 ; + RECT 0.216 15.600 24.493 15.696 ; + RECT 0.216 16.368 24.493 16.464 ; + RECT 0.216 17.136 24.493 17.232 ; + RECT 0.216 17.904 24.493 18.000 ; + RECT 0.216 18.672 24.493 18.768 ; + RECT 0.216 19.440 24.493 19.536 ; + RECT 0.216 20.208 24.493 20.304 ; + RECT 0.216 20.976 24.493 21.072 ; + RECT 0.216 21.744 24.493 21.840 ; + RECT 0.216 22.512 24.493 22.608 ; + RECT 0.216 23.280 24.493 23.376 ; + RECT 0.216 24.048 24.493 24.144 ; + RECT 0.216 24.816 24.493 24.912 ; + RECT 0.216 25.584 24.493 25.680 ; + RECT 0.216 26.352 24.493 26.448 ; + RECT 0.216 27.120 24.493 27.216 ; + RECT 0.216 27.888 24.493 27.984 ; + RECT 0.216 28.656 24.493 28.752 ; + RECT 0.216 29.424 24.493 29.520 ; + RECT 0.216 30.192 24.493 30.288 ; + RECT 0.216 30.960 24.493 31.056 ; + RECT 0.216 31.728 24.493 31.824 ; + RECT 0.216 32.496 24.493 32.592 ; + RECT 0.216 33.264 24.493 33.360 ; + RECT 0.216 34.032 24.493 34.128 ; + RECT 0.216 34.800 24.493 34.896 ; + RECT 0.216 35.568 24.493 35.664 ; + RECT 0.216 36.336 24.493 36.432 ; + RECT 0.216 37.104 24.493 37.200 ; + RECT 0.216 37.872 24.493 37.968 ; + RECT 0.216 38.640 24.493 38.736 ; + RECT 0.216 39.408 24.493 39.504 ; + RECT 0.216 40.176 24.493 40.272 ; + RECT 0.216 40.944 24.493 41.040 ; + RECT 0.216 41.712 24.493 41.808 ; + RECT 0.216 42.480 24.493 42.576 ; + RECT 0.216 43.248 24.493 43.344 ; + RECT 0.216 44.016 24.493 44.112 ; + RECT 0.216 44.784 24.493 44.880 ; + RECT 0.216 45.552 24.493 45.648 ; + RECT 0.216 46.320 24.493 46.416 ; + RECT 0.216 47.088 24.493 47.184 ; + RECT 0.216 47.856 24.493 47.952 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 24.493 0.336 ; + RECT 0.216 1.008 24.493 1.104 ; + RECT 0.216 1.776 24.493 1.872 ; + RECT 0.216 2.544 24.493 2.640 ; + RECT 0.216 3.312 24.493 3.408 ; + RECT 0.216 4.080 24.493 4.176 ; + RECT 0.216 4.848 24.493 4.944 ; + RECT 0.216 5.616 24.493 5.712 ; + RECT 0.216 6.384 24.493 6.480 ; + RECT 0.216 7.152 24.493 7.248 ; + RECT 0.216 7.920 24.493 8.016 ; + RECT 0.216 8.688 24.493 8.784 ; + RECT 0.216 9.456 24.493 9.552 ; + RECT 0.216 10.224 24.493 10.320 ; + RECT 0.216 10.992 24.493 11.088 ; + RECT 0.216 11.760 24.493 11.856 ; + RECT 0.216 12.528 24.493 12.624 ; + RECT 0.216 13.296 24.493 13.392 ; + RECT 0.216 14.064 24.493 14.160 ; + RECT 0.216 14.832 24.493 14.928 ; + RECT 0.216 15.600 24.493 15.696 ; + RECT 0.216 16.368 24.493 16.464 ; + RECT 0.216 17.136 24.493 17.232 ; + RECT 0.216 17.904 24.493 18.000 ; + RECT 0.216 18.672 24.493 18.768 ; + RECT 0.216 19.440 24.493 19.536 ; + RECT 0.216 20.208 24.493 20.304 ; + RECT 0.216 20.976 24.493 21.072 ; + RECT 0.216 21.744 24.493 21.840 ; + RECT 0.216 22.512 24.493 22.608 ; + RECT 0.216 23.280 24.493 23.376 ; + RECT 0.216 24.048 24.493 24.144 ; + RECT 0.216 24.816 24.493 24.912 ; + RECT 0.216 25.584 24.493 25.680 ; + RECT 0.216 26.352 24.493 26.448 ; + RECT 0.216 27.120 24.493 27.216 ; + RECT 0.216 27.888 24.493 27.984 ; + RECT 0.216 28.656 24.493 28.752 ; + RECT 0.216 29.424 24.493 29.520 ; + RECT 0.216 30.192 24.493 30.288 ; + RECT 0.216 30.960 24.493 31.056 ; + RECT 0.216 31.728 24.493 31.824 ; + RECT 0.216 32.496 24.493 32.592 ; + RECT 0.216 33.264 24.493 33.360 ; + RECT 0.216 34.032 24.493 34.128 ; + RECT 0.216 34.800 24.493 34.896 ; + RECT 0.216 35.568 24.493 35.664 ; + RECT 0.216 36.336 24.493 36.432 ; + RECT 0.216 37.104 24.493 37.200 ; + RECT 0.216 37.872 24.493 37.968 ; + RECT 0.216 38.640 24.493 38.736 ; + RECT 0.216 39.408 24.493 39.504 ; + RECT 0.216 40.176 24.493 40.272 ; + RECT 0.216 40.944 24.493 41.040 ; + RECT 0.216 41.712 24.493 41.808 ; + RECT 0.216 42.480 24.493 42.576 ; + RECT 0.216 43.248 24.493 43.344 ; + RECT 0.216 44.016 24.493 44.112 ; + RECT 0.216 44.784 24.493 44.880 ; + RECT 0.216 45.552 24.493 45.648 ; + RECT 0.216 46.320 24.493 46.416 ; + RECT 0.216 47.088 24.493 47.184 ; + RECT 0.216 47.856 24.493 47.952 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 24.709 48.379 ; + LAYER M2 ; + RECT 0 0 24.709 48.379 ; + LAYER M3 ; + RECT 0 0 24.709 48.379 ; + LAYER M4 ; + RECT 0 0 24.709 48.379 ; + END +END fakeram_82x248_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_8x256_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_8x256_1r1w.lef new file mode 100644 index 0000000..f07377b --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_8x256_1r1w.lef @@ -0,0 +1,481 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_8x256_1r1w + FOREIGN fakeram_8x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 43.524 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.548 0.072 4.572 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.548 9.643 4.572 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.323 0.000 1.341 0.054 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.439 0.000 2.457 0.054 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.555 0.000 3.573 0.054 ; + END + END w0_wd_in[7] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.671 0.000 4.689 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.903 0.000 6.921 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.019 0.000 8.037 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 43.470 0.225 43.524 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 43.470 1.233 43.524 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 43.470 2.241 43.524 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 43.470 3.249 43.524 ; + END + END r0_rd_out[7] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.820 0.072 8.844 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.364 0.072 17.388 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.636 0.072 21.660 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.820 9.643 8.844 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 13.092 9.643 13.116 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 17.364 9.643 17.388 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 21.636 9.643 21.660 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.180 0.072 30.204 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.452 0.072 34.476 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.724 0.072 38.748 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 25.908 9.643 25.932 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 30.180 9.643 30.204 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 34.452 9.643 34.476 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 38.724 9.643 38.748 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 43.470 4.257 43.524 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 43.470 5.265 43.524 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 43.470 6.273 43.524 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 43.470 7.281 43.524 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 43.470 8.289 43.524 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 43.524 ; + LAYER M2 ; + RECT 0 0 9.643 43.524 ; + LAYER M3 ; + RECT 0 0 9.643 43.524 ; + LAYER M4 ; + RECT 0 0 9.643 43.524 ; + END +END fakeram_8x256_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_8x512_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_8x512_1r1w.lef new file mode 100644 index 0000000..ce1f902 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_8x512_1r1w.lef @@ -0,0 +1,611 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_8x512_1r1w + FOREIGN fakeram_8x512_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 86.379 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.052 9.643 8.076 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.323 0.000 1.341 0.054 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.439 0.000 2.457 0.054 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.555 0.000 3.573 0.054 ; + END + END w0_wd_in[7] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.671 0.000 4.689 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.903 0.000 6.921 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.019 0.000 8.037 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 86.325 0.225 86.379 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 86.325 1.233 86.379 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 86.325 2.241 86.379 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 86.325 3.249 86.379 ; + END + END r0_rd_out[7] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.932 0.072 46.956 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 15.828 9.643 15.852 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 23.604 9.643 23.628 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 31.380 9.643 31.404 ; + END + END w0_addr_in[7] + PIN w0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 39.156 9.643 39.180 ; + END + END w0_addr_in[8] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.708 0.072 54.732 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.484 0.072 62.508 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.260 0.072 70.284 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.036 0.072 78.060 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.812 0.072 85.836 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 46.932 9.643 46.956 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 54.708 9.643 54.732 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 62.484 9.643 62.508 ; + END + END r0_addr_in[7] + PIN r0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 70.260 9.643 70.284 ; + END + END r0_addr_in[8] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 86.325 4.257 86.379 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 86.325 5.265 86.379 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 86.325 6.273 86.379 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.263 86.325 7.281 86.379 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 86.325 8.289 86.379 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + RECT 0.216 44.016 9.427 44.112 ; + RECT 0.216 44.784 9.427 44.880 ; + RECT 0.216 45.552 9.427 45.648 ; + RECT 0.216 46.320 9.427 46.416 ; + RECT 0.216 47.088 9.427 47.184 ; + RECT 0.216 47.856 9.427 47.952 ; + RECT 0.216 48.624 9.427 48.720 ; + RECT 0.216 49.392 9.427 49.488 ; + RECT 0.216 50.160 9.427 50.256 ; + RECT 0.216 50.928 9.427 51.024 ; + RECT 0.216 51.696 9.427 51.792 ; + RECT 0.216 52.464 9.427 52.560 ; + RECT 0.216 53.232 9.427 53.328 ; + RECT 0.216 54.000 9.427 54.096 ; + RECT 0.216 54.768 9.427 54.864 ; + RECT 0.216 55.536 9.427 55.632 ; + RECT 0.216 56.304 9.427 56.400 ; + RECT 0.216 57.072 9.427 57.168 ; + RECT 0.216 57.840 9.427 57.936 ; + RECT 0.216 58.608 9.427 58.704 ; + RECT 0.216 59.376 9.427 59.472 ; + RECT 0.216 60.144 9.427 60.240 ; + RECT 0.216 60.912 9.427 61.008 ; + RECT 0.216 61.680 9.427 61.776 ; + RECT 0.216 62.448 9.427 62.544 ; + RECT 0.216 63.216 9.427 63.312 ; + RECT 0.216 63.984 9.427 64.080 ; + RECT 0.216 64.752 9.427 64.848 ; + RECT 0.216 65.520 9.427 65.616 ; + RECT 0.216 66.288 9.427 66.384 ; + RECT 0.216 67.056 9.427 67.152 ; + RECT 0.216 67.824 9.427 67.920 ; + RECT 0.216 68.592 9.427 68.688 ; + RECT 0.216 69.360 9.427 69.456 ; + RECT 0.216 70.128 9.427 70.224 ; + RECT 0.216 70.896 9.427 70.992 ; + RECT 0.216 71.664 9.427 71.760 ; + RECT 0.216 72.432 9.427 72.528 ; + RECT 0.216 73.200 9.427 73.296 ; + RECT 0.216 73.968 9.427 74.064 ; + RECT 0.216 74.736 9.427 74.832 ; + RECT 0.216 75.504 9.427 75.600 ; + RECT 0.216 76.272 9.427 76.368 ; + RECT 0.216 77.040 9.427 77.136 ; + RECT 0.216 77.808 9.427 77.904 ; + RECT 0.216 78.576 9.427 78.672 ; + RECT 0.216 79.344 9.427 79.440 ; + RECT 0.216 80.112 9.427 80.208 ; + RECT 0.216 80.880 9.427 80.976 ; + RECT 0.216 81.648 9.427 81.744 ; + RECT 0.216 82.416 9.427 82.512 ; + RECT 0.216 83.184 9.427 83.280 ; + RECT 0.216 83.952 9.427 84.048 ; + RECT 0.216 84.720 9.427 84.816 ; + RECT 0.216 85.488 9.427 85.584 ; + RECT 0.216 86.256 9.427 86.352 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + RECT 0.216 14.064 9.427 14.160 ; + RECT 0.216 14.832 9.427 14.928 ; + RECT 0.216 15.600 9.427 15.696 ; + RECT 0.216 16.368 9.427 16.464 ; + RECT 0.216 17.136 9.427 17.232 ; + RECT 0.216 17.904 9.427 18.000 ; + RECT 0.216 18.672 9.427 18.768 ; + RECT 0.216 19.440 9.427 19.536 ; + RECT 0.216 20.208 9.427 20.304 ; + RECT 0.216 20.976 9.427 21.072 ; + RECT 0.216 21.744 9.427 21.840 ; + RECT 0.216 22.512 9.427 22.608 ; + RECT 0.216 23.280 9.427 23.376 ; + RECT 0.216 24.048 9.427 24.144 ; + RECT 0.216 24.816 9.427 24.912 ; + RECT 0.216 25.584 9.427 25.680 ; + RECT 0.216 26.352 9.427 26.448 ; + RECT 0.216 27.120 9.427 27.216 ; + RECT 0.216 27.888 9.427 27.984 ; + RECT 0.216 28.656 9.427 28.752 ; + RECT 0.216 29.424 9.427 29.520 ; + RECT 0.216 30.192 9.427 30.288 ; + RECT 0.216 30.960 9.427 31.056 ; + RECT 0.216 31.728 9.427 31.824 ; + RECT 0.216 32.496 9.427 32.592 ; + RECT 0.216 33.264 9.427 33.360 ; + RECT 0.216 34.032 9.427 34.128 ; + RECT 0.216 34.800 9.427 34.896 ; + RECT 0.216 35.568 9.427 35.664 ; + RECT 0.216 36.336 9.427 36.432 ; + RECT 0.216 37.104 9.427 37.200 ; + RECT 0.216 37.872 9.427 37.968 ; + RECT 0.216 38.640 9.427 38.736 ; + RECT 0.216 39.408 9.427 39.504 ; + RECT 0.216 40.176 9.427 40.272 ; + RECT 0.216 40.944 9.427 41.040 ; + RECT 0.216 41.712 9.427 41.808 ; + RECT 0.216 42.480 9.427 42.576 ; + RECT 0.216 43.248 9.427 43.344 ; + RECT 0.216 44.016 9.427 44.112 ; + RECT 0.216 44.784 9.427 44.880 ; + RECT 0.216 45.552 9.427 45.648 ; + RECT 0.216 46.320 9.427 46.416 ; + RECT 0.216 47.088 9.427 47.184 ; + RECT 0.216 47.856 9.427 47.952 ; + RECT 0.216 48.624 9.427 48.720 ; + RECT 0.216 49.392 9.427 49.488 ; + RECT 0.216 50.160 9.427 50.256 ; + RECT 0.216 50.928 9.427 51.024 ; + RECT 0.216 51.696 9.427 51.792 ; + RECT 0.216 52.464 9.427 52.560 ; + RECT 0.216 53.232 9.427 53.328 ; + RECT 0.216 54.000 9.427 54.096 ; + RECT 0.216 54.768 9.427 54.864 ; + RECT 0.216 55.536 9.427 55.632 ; + RECT 0.216 56.304 9.427 56.400 ; + RECT 0.216 57.072 9.427 57.168 ; + RECT 0.216 57.840 9.427 57.936 ; + RECT 0.216 58.608 9.427 58.704 ; + RECT 0.216 59.376 9.427 59.472 ; + RECT 0.216 60.144 9.427 60.240 ; + RECT 0.216 60.912 9.427 61.008 ; + RECT 0.216 61.680 9.427 61.776 ; + RECT 0.216 62.448 9.427 62.544 ; + RECT 0.216 63.216 9.427 63.312 ; + RECT 0.216 63.984 9.427 64.080 ; + RECT 0.216 64.752 9.427 64.848 ; + RECT 0.216 65.520 9.427 65.616 ; + RECT 0.216 66.288 9.427 66.384 ; + RECT 0.216 67.056 9.427 67.152 ; + RECT 0.216 67.824 9.427 67.920 ; + RECT 0.216 68.592 9.427 68.688 ; + RECT 0.216 69.360 9.427 69.456 ; + RECT 0.216 70.128 9.427 70.224 ; + RECT 0.216 70.896 9.427 70.992 ; + RECT 0.216 71.664 9.427 71.760 ; + RECT 0.216 72.432 9.427 72.528 ; + RECT 0.216 73.200 9.427 73.296 ; + RECT 0.216 73.968 9.427 74.064 ; + RECT 0.216 74.736 9.427 74.832 ; + RECT 0.216 75.504 9.427 75.600 ; + RECT 0.216 76.272 9.427 76.368 ; + RECT 0.216 77.040 9.427 77.136 ; + RECT 0.216 77.808 9.427 77.904 ; + RECT 0.216 78.576 9.427 78.672 ; + RECT 0.216 79.344 9.427 79.440 ; + RECT 0.216 80.112 9.427 80.208 ; + RECT 0.216 80.880 9.427 80.976 ; + RECT 0.216 81.648 9.427 81.744 ; + RECT 0.216 82.416 9.427 82.512 ; + RECT 0.216 83.184 9.427 83.280 ; + RECT 0.216 83.952 9.427 84.048 ; + RECT 0.216 84.720 9.427 84.816 ; + RECT 0.216 85.488 9.427 85.584 ; + RECT 0.216 86.256 9.427 86.352 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 86.379 ; + LAYER M2 ; + RECT 0 0 9.643 86.379 ; + LAYER M3 ; + RECT 0 0 9.643 86.379 ; + LAYER M4 ; + RECT 0 0 9.643 86.379 ; + END +END fakeram_8x512_1r1w + +END LIBRARY diff --git a/designs/asap7/NVDLA/sram/lef/fakeram_9x80_1r1w.lef b/designs/asap7/NVDLA/sram/lef/fakeram_9x80_1r1w.lef new file mode 100644 index 0000000..95b5374 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lef/fakeram_9x80_1r1w.lef @@ -0,0 +1,403 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_9x80_1r1w + FOREIGN fakeram_9x80_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 9.643 BY 14.146 ; + CLASS BLOCK ; + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 0.276 9.643 0.300 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 1.620 9.643 1.644 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END w0_wd_in[8] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 14.092 0.225 14.146 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 14.092 1.125 14.146 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 14.092 2.025 14.146 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 14.092 2.925 14.146 ; + END + END r0_rd_out[8] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 2.964 9.643 2.988 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 4.308 9.643 4.332 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 5.652 9.643 5.676 ; + END + END w0_addr_in[6] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 6.996 9.643 7.020 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 8.340 9.643 8.364 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 9.571 9.684 9.643 9.708 ; + END + END r0_addr_in[6] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 14.092 3.825 14.146 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 14.092 4.725 14.146 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 14.092 5.625 14.146 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 14.092 6.525 14.146 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 14.092 7.425 14.146 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.427 0.336 ; + RECT 0.216 1.008 9.427 1.104 ; + RECT 0.216 1.776 9.427 1.872 ; + RECT 0.216 2.544 9.427 2.640 ; + RECT 0.216 3.312 9.427 3.408 ; + RECT 0.216 4.080 9.427 4.176 ; + RECT 0.216 4.848 9.427 4.944 ; + RECT 0.216 5.616 9.427 5.712 ; + RECT 0.216 6.384 9.427 6.480 ; + RECT 0.216 7.152 9.427 7.248 ; + RECT 0.216 7.920 9.427 8.016 ; + RECT 0.216 8.688 9.427 8.784 ; + RECT 0.216 9.456 9.427 9.552 ; + RECT 0.216 10.224 9.427 10.320 ; + RECT 0.216 10.992 9.427 11.088 ; + RECT 0.216 11.760 9.427 11.856 ; + RECT 0.216 12.528 9.427 12.624 ; + RECT 0.216 13.296 9.427 13.392 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 9.643 14.146 ; + LAYER M2 ; + RECT 0 0 9.643 14.146 ; + LAYER M3 ; + RECT 0 0 9.643 14.146 ; + LAYER M4 ; + RECT 0 0 9.643 14.146 ; + END +END fakeram_9x80_1r1w + +END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_10x64_1r1w.lib similarity index 77% rename from designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib rename to designs/asap7/NVDLA/sram/lib/fakeram_10x64_1r1w.lib index f5e4960..3fd2059 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib +++ b/designs/asap7/NVDLA/sram/lib/fakeram_10x64_1r1w.lib @@ -1,8 +1,8 @@ -library(fakeram_20x64_1r1w) { +library(fakeram_10x64_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-03-01 01:35:00Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -46,40 +46,40 @@ library(fakeram_20x64_1r1w) { output_threshold_pct_rise : 50.000; - lu_table_template(fakeram_20x64_1r1w_mem_out_delay_template) { + lu_table_template(fakeram_10x64_1r1w_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - lu_table_template(fakeram_20x64_1r1w_mem_out_slew_template) { + lu_table_template(fakeram_10x64_1r1w_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } - lu_table_template(fakeram_20x64_1r1w_constraint_template) { + lu_table_template(fakeram_10x64_1r1w_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - power_lut_template(fakeram_20x64_1r1w_energy_template_clkslew) { + power_lut_template(fakeram_10x64_1r1w_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } - power_lut_template(fakeram_20x64_1r1w_energy_template_sigslew) { + power_lut_template(fakeram_10x64_1r1w_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); - type (fakeram_20x64_1r1w_DATA) { + type (fakeram_10x64_1r1w_DATA) { base_type : array ; data_type : bit ; - bit_width : 20; - bit_from : 19; + bit_width : 10; + bit_from : 9; bit_to : 0 ; downto : true ; } - type (fakeram_20x64_1r1w_ADDRESS) { + type (fakeram_10x64_1r1w_ADDRESS) { base_type : array ; data_type : bit ; bit_width : 6; @@ -87,13 +87,13 @@ library(fakeram_20x64_1r1w) { bit_to : 0 ; downto : true ; } -cell(fakeram_20x64_1r1w) { - area : 53.748; +cell(fakeram_10x64_1r1w) { + area : 111.386; interface_timing : true; memory() { type : ram; address_width : 6; - word_width : 20; + word_width : 10; } pin(r0_clk) { direction : input; @@ -101,11 +101,11 @@ cell(fakeram_20x64_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_clkslew) { + rise_power(fakeram_10x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_20x64_1r1w_energy_template_clkslew) { + fall_power(fakeram_10x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -118,11 +118,11 @@ cell(fakeram_20x64_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_clkslew) { + rise_power(fakeram_10x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_20x64_1r1w_energy_template_clkslew) { + fall_power(fakeram_10x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -130,7 +130,7 @@ cell(fakeram_20x64_1r1w) { } bus(r0_rd_out) { - bus_type : fakeram_20x64_1r1w_DATA; + bus_type : fakeram_10x64_1r1w_DATA; direction : output; max_capacitance : 0.500; memory_read() { @@ -140,7 +140,7 @@ cell(fakeram_20x64_1r1w) { related_pin : "r0_clk" ; timing_type : rising_edge; timing_sense : non_unate; - cell_rise(fakeram_20x64_1r1w_mem_out_delay_template) { + cell_rise(fakeram_10x64_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -148,7 +148,7 @@ cell(fakeram_20x64_1r1w) { "0.218, 0.218" \ ) } - cell_fall(fakeram_20x64_1r1w_mem_out_delay_template) { + cell_fall(fakeram_10x64_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -156,11 +156,11 @@ cell(fakeram_20x64_1r1w) { "0.218, 0.218" \ ) } - rise_transition(fakeram_20x64_1r1w_mem_out_slew_template) { + rise_transition(fakeram_10x64_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } - fall_transition(fakeram_20x64_1r1w_mem_out_slew_template) { + fall_transition(fakeram_10x64_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } @@ -172,7 +172,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -180,7 +180,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -192,7 +192,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -200,7 +200,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -210,11 +210,11 @@ cell(fakeram_20x64_1r1w) { } } internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -226,7 +226,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -234,7 +234,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -246,7 +246,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -254,7 +254,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -264,11 +264,11 @@ cell(fakeram_20x64_1r1w) { } } internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -280,7 +280,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -288,7 +288,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -300,7 +300,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -308,7 +308,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -318,18 +318,18 @@ cell(fakeram_20x64_1r1w) { } } internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_wd_in) { - bus_type : fakeram_20x64_1r1w_DATA; + bus_type : fakeram_10x64_1r1w_DATA; memory_write() { address : w0_addr_in; clocked_on : "w0_clk"; @@ -339,7 +339,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -347,7 +347,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -359,7 +359,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -367,7 +367,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -378,35 +378,35 @@ cell(fakeram_20x64_1r1w) { } internal_power(){ when : "(! (w0_we_in) )"; - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } internal_power(){ when : "(w0_we_in)"; - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(r0_addr_in) { - bus_type : fakeram_20x64_1r1w_ADDRESS; + bus_type : fakeram_10x64_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -414,7 +414,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -426,7 +426,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -434,7 +434,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -444,24 +444,24 @@ cell(fakeram_20x64_1r1w) { } } internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_addr_in) { - bus_type : fakeram_20x64_1r1w_ADDRESS; + bus_type : fakeram_10x64_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -469,7 +469,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -481,7 +481,7 @@ cell(fakeram_20x64_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { + rise_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -489,7 +489,7 @@ cell(fakeram_20x64_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { + fall_constraint(fakeram_10x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -499,11 +499,11 @@ cell(fakeram_20x64_1r1w) { } } internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { + rise_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { + fall_power(fakeram_10x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_116x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_116x64_1r1w.lib new file mode 100644 index 0000000..5bc88fc --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_116x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_116x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_116x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_116x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_116x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_116x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_116x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_116x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 116; + bit_from : 115; + bit_to : 0 ; + downto : true ; + } + type (fakeram_116x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_116x64_1r1w) { + area : 713.866; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 116; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_116x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_116x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_116x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_116x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_116x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_116x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_116x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_116x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_116x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_116x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_116x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_116x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_11x128_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_11x128_1r1w.lib new file mode 100644 index 0000000..f72c724 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_11x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_11x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_11x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_11x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_11x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_11x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_11x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_11x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 11; + bit_from : 10; + bit_to : 0 ; + downto : true ; + } + type (fakeram_11x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_11x128_1r1w) { + area : 215.502; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 11; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_11x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_11x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_11x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_11x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_11x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_11x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_11x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_11x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_11x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_11x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_11x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_11x256_1r1w.lib similarity index 77% rename from designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib rename to designs/asap7/NVDLA/sram/lib/fakeram_11x256_1r1w.lib index c7caac0..242e7bd 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib +++ b/designs/asap7/NVDLA/sram/lib/fakeram_11x256_1r1w.lib @@ -1,8 +1,8 @@ -library(fakeram_18x256_1r1w) { +library(fakeram_11x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-03-01 01:35:00Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -46,40 +46,40 @@ library(fakeram_18x256_1r1w) { output_threshold_pct_rise : 50.000; - lu_table_template(fakeram_18x256_1r1w_mem_out_delay_template) { + lu_table_template(fakeram_11x256_1r1w_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - lu_table_template(fakeram_18x256_1r1w_mem_out_slew_template) { + lu_table_template(fakeram_11x256_1r1w_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } - lu_table_template(fakeram_18x256_1r1w_constraint_template) { + lu_table_template(fakeram_11x256_1r1w_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - power_lut_template(fakeram_18x256_1r1w_energy_template_clkslew) { + power_lut_template(fakeram_11x256_1r1w_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } - power_lut_template(fakeram_18x256_1r1w_energy_template_sigslew) { + power_lut_template(fakeram_11x256_1r1w_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); - type (fakeram_18x256_1r1w_DATA) { + type (fakeram_11x256_1r1w_DATA) { base_type : array ; data_type : bit ; - bit_width : 18; - bit_from : 17; + bit_width : 11; + bit_from : 10; bit_to : 0 ; downto : true ; } - type (fakeram_18x256_1r1w_ADDRESS) { + type (fakeram_11x256_1r1w_ADDRESS) { base_type : array ; data_type : bit ; bit_width : 8; @@ -87,13 +87,13 @@ library(fakeram_18x256_1r1w) { bit_to : 0 ; downto : true ; } -cell(fakeram_18x256_1r1w) { - area : 193.508; +cell(fakeram_11x256_1r1w) { + area : 422.132; interface_timing : true; memory() { type : ram; address_width : 8; - word_width : 18; + word_width : 11; } pin(r0_clk) { direction : input; @@ -101,11 +101,11 @@ cell(fakeram_18x256_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_clkslew) { + rise_power(fakeram_11x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_18x256_1r1w_energy_template_clkslew) { + fall_power(fakeram_11x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -118,11 +118,11 @@ cell(fakeram_18x256_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_clkslew) { + rise_power(fakeram_11x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_18x256_1r1w_energy_template_clkslew) { + fall_power(fakeram_11x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -130,7 +130,7 @@ cell(fakeram_18x256_1r1w) { } bus(r0_rd_out) { - bus_type : fakeram_18x256_1r1w_DATA; + bus_type : fakeram_11x256_1r1w_DATA; direction : output; max_capacitance : 0.500; memory_read() { @@ -140,7 +140,7 @@ cell(fakeram_18x256_1r1w) { related_pin : "r0_clk" ; timing_type : rising_edge; timing_sense : non_unate; - cell_rise(fakeram_18x256_1r1w_mem_out_delay_template) { + cell_rise(fakeram_11x256_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -148,7 +148,7 @@ cell(fakeram_18x256_1r1w) { "0.218, 0.218" \ ) } - cell_fall(fakeram_18x256_1r1w_mem_out_delay_template) { + cell_fall(fakeram_11x256_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -156,11 +156,11 @@ cell(fakeram_18x256_1r1w) { "0.218, 0.218" \ ) } - rise_transition(fakeram_18x256_1r1w_mem_out_slew_template) { + rise_transition(fakeram_11x256_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } - fall_transition(fakeram_18x256_1r1w_mem_out_slew_template) { + fall_transition(fakeram_11x256_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } @@ -172,7 +172,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -180,7 +180,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -192,7 +192,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -200,7 +200,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -210,11 +210,11 @@ cell(fakeram_18x256_1r1w) { } } internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -226,7 +226,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -234,7 +234,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -246,7 +246,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -254,7 +254,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -264,11 +264,11 @@ cell(fakeram_18x256_1r1w) { } } internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -280,7 +280,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -288,7 +288,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -300,7 +300,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -308,7 +308,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -318,18 +318,18 @@ cell(fakeram_18x256_1r1w) { } } internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_wd_in) { - bus_type : fakeram_18x256_1r1w_DATA; + bus_type : fakeram_11x256_1r1w_DATA; memory_write() { address : w0_addr_in; clocked_on : "w0_clk"; @@ -339,7 +339,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -347,7 +347,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -359,7 +359,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -367,7 +367,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -378,35 +378,35 @@ cell(fakeram_18x256_1r1w) { } internal_power(){ when : "(! (w0_we_in) )"; - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } internal_power(){ when : "(w0_we_in)"; - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(r0_addr_in) { - bus_type : fakeram_18x256_1r1w_ADDRESS; + bus_type : fakeram_11x256_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -414,7 +414,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -426,7 +426,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -434,7 +434,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -444,24 +444,24 @@ cell(fakeram_18x256_1r1w) { } } internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_addr_in) { - bus_type : fakeram_18x256_1r1w_ADDRESS; + bus_type : fakeram_11x256_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -469,7 +469,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -481,7 +481,7 @@ cell(fakeram_18x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { + rise_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -489,7 +489,7 @@ cell(fakeram_18x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { + fall_constraint(fakeram_11x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -499,11 +499,11 @@ cell(fakeram_18x256_1r1w) { } } internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_11x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_144x160_1r1w.lib similarity index 77% rename from designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib rename to designs/asap7/NVDLA/sram/lib/fakeram_144x160_1r1w.lib index 34c181b..8b7c782 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib +++ b/designs/asap7/NVDLA/sram/lib/fakeram_144x160_1r1w.lib @@ -1,8 +1,8 @@ -library(fakeram_512x256_1r1w) { +library(fakeram_144x160_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-03-01 01:35:00Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -46,40 +46,40 @@ library(fakeram_512x256_1r1w) { output_threshold_pct_rise : 50.000; - lu_table_template(fakeram_512x256_1r1w_mem_out_delay_template) { + lu_table_template(fakeram_144x160_1r1w_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - lu_table_template(fakeram_512x256_1r1w_mem_out_slew_template) { + lu_table_template(fakeram_144x160_1r1w_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } - lu_table_template(fakeram_512x256_1r1w_constraint_template) { + lu_table_template(fakeram_144x160_1r1w_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - power_lut_template(fakeram_512x256_1r1w_energy_template_clkslew) { + power_lut_template(fakeram_144x160_1r1w_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } - power_lut_template(fakeram_512x256_1r1w_energy_template_sigslew) { + power_lut_template(fakeram_144x160_1r1w_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); - type (fakeram_512x256_1r1w_DATA) { + type (fakeram_144x160_1r1w_DATA) { base_type : array ; data_type : bit ; - bit_width : 512; - bit_from : 511; + bit_width : 144; + bit_from : 143; bit_to : 0 ; downto : true ; } - type (fakeram_512x256_1r1w_ADDRESS) { + type (fakeram_144x160_1r1w_ADDRESS) { base_type : array ; data_type : bit ; bit_width : 8; @@ -87,13 +87,13 @@ library(fakeram_512x256_1r1w) { bit_to : 0 ; downto : true ; } -cell(fakeram_512x256_1r1w) { - area : 5503.791; +cell(fakeram_144x160_1r1w) { + area : 1685.176; interface_timing : true; memory() { type : ram; address_width : 8; - word_width : 512; + word_width : 144; } pin(r0_clk) { direction : input; @@ -101,11 +101,11 @@ cell(fakeram_512x256_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_clkslew) { + rise_power(fakeram_144x160_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_512x256_1r1w_energy_template_clkslew) { + fall_power(fakeram_144x160_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -118,11 +118,11 @@ cell(fakeram_512x256_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_clkslew) { + rise_power(fakeram_144x160_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_512x256_1r1w_energy_template_clkslew) { + fall_power(fakeram_144x160_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -130,7 +130,7 @@ cell(fakeram_512x256_1r1w) { } bus(r0_rd_out) { - bus_type : fakeram_512x256_1r1w_DATA; + bus_type : fakeram_144x160_1r1w_DATA; direction : output; max_capacitance : 0.500; memory_read() { @@ -140,7 +140,7 @@ cell(fakeram_512x256_1r1w) { related_pin : "r0_clk" ; timing_type : rising_edge; timing_sense : non_unate; - cell_rise(fakeram_512x256_1r1w_mem_out_delay_template) { + cell_rise(fakeram_144x160_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -148,7 +148,7 @@ cell(fakeram_512x256_1r1w) { "0.218, 0.218" \ ) } - cell_fall(fakeram_512x256_1r1w_mem_out_delay_template) { + cell_fall(fakeram_144x160_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -156,11 +156,11 @@ cell(fakeram_512x256_1r1w) { "0.218, 0.218" \ ) } - rise_transition(fakeram_512x256_1r1w_mem_out_slew_template) { + rise_transition(fakeram_144x160_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } - fall_transition(fakeram_512x256_1r1w_mem_out_slew_template) { + fall_transition(fakeram_144x160_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } @@ -172,7 +172,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -180,7 +180,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -192,7 +192,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -200,7 +200,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -210,11 +210,11 @@ cell(fakeram_512x256_1r1w) { } } internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -226,7 +226,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -234,7 +234,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -246,7 +246,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -254,7 +254,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -264,11 +264,11 @@ cell(fakeram_512x256_1r1w) { } } internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -280,7 +280,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -288,7 +288,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -300,7 +300,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -308,7 +308,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -318,18 +318,18 @@ cell(fakeram_512x256_1r1w) { } } internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_wd_in) { - bus_type : fakeram_512x256_1r1w_DATA; + bus_type : fakeram_144x160_1r1w_DATA; memory_write() { address : w0_addr_in; clocked_on : "w0_clk"; @@ -339,7 +339,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -347,7 +347,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -359,7 +359,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -367,7 +367,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -378,35 +378,35 @@ cell(fakeram_512x256_1r1w) { } internal_power(){ when : "(! (w0_we_in) )"; - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } internal_power(){ when : "(w0_we_in)"; - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(r0_addr_in) { - bus_type : fakeram_512x256_1r1w_ADDRESS; + bus_type : fakeram_144x160_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -414,7 +414,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -426,7 +426,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -434,7 +434,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -444,24 +444,24 @@ cell(fakeram_512x256_1r1w) { } } internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_addr_in) { - bus_type : fakeram_512x256_1r1w_ADDRESS; + bus_type : fakeram_144x160_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -469,7 +469,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -481,7 +481,7 @@ cell(fakeram_512x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { + rise_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -489,7 +489,7 @@ cell(fakeram_512x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { + fall_constraint(fakeram_144x160_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -499,11 +499,11 @@ cell(fakeram_512x256_1r1w) { } } internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_144x160_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_144x248_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_144x248_1r1w.lib new file mode 100644 index 0000000..50b38fd --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_144x248_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_144x248_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_144x248_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_144x248_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_144x248_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_144x248_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_144x248_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_144x248_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 72; + bit_from : 71; + bit_to : 0 ; + downto : true ; + } + type (fakeram_144x248_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_144x248_1r1w) { + area : 1031.471; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 72; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_144x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_144x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_144x248_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_144x248_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_144x248_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_144x248_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_144x248_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_144x248_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_144x248_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_144x248_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_144x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_144x256_1r1w.lib new file mode 100644 index 0000000..b829dee --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_144x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_144x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_144x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_144x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_144x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_144x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_144x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_144x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 72; + bit_from : 71; + bit_to : 0 ; + downto : true ; + } + type (fakeram_144x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_144x256_1r1w) { + area : 1060.522; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 72; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_144x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_144x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_144x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_144x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_144x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_144x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_144x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_144x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_144x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_144x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_144x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_144x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_14x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_14x80_1r1w.lib new file mode 100644 index 0000000..1fcd071 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_14x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_14x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_14x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_14x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_14x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_14x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_14x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_14x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 14; + bit_from : 13; + bit_to : 0 ; + downto : true ; + } + type (fakeram_14x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_14x80_1r1w) { + area : 140.441; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 14; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_14x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_14x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_14x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_14x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_14x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_14x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_14x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_14x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_14x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_14x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_14x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_15x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_15x80_1r1w.lib new file mode 100644 index 0000000..04476a8 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_15x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_15x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_15x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_15x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_15x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_15x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_15x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_15x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 15; + bit_from : 14; + bit_to : 0 ; + downto : true ; + } + type (fakeram_15x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_15x80_1r1w) { + area : 141.251; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 15; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_15x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_15x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_15x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_15x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_15x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_15x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_15x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_15x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_15x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_15x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_15x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_160x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_160x64_1r1w.lib new file mode 100644 index 0000000..ec76091 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_160x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_160x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_160x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_160x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_160x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_160x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_160x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_160x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 160; + bit_from : 159; + bit_to : 0 ; + downto : true ; + } + type (fakeram_160x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_160x64_1r1w) { + area : 1162.198; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 160; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_160x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_160x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_160x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_160x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_160x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_160x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_160x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_160x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_160x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_160x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_160x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_160x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_168x60_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_168x60_1r1w.lib new file mode 100644 index 0000000..656bfd8 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_168x60_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_168x60_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_168x60_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_168x60_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_168x60_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_168x60_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_168x60_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_168x60_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 168; + bit_from : 167; + bit_to : 0 ; + downto : true ; + } + type (fakeram_168x60_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_168x60_1r1w) { + area : 1220.294; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 168; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_168x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_168x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_168x60_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_168x60_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_168x60_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_168x60_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_168x60_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_168x60_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_168x60_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_168x60_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_168x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_168x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_16x160_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_16x160_1r1w.lib new file mode 100644 index 0000000..2e92df5 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_16x160_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_16x160_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_16x160_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_16x160_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_16x160_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_16x160_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_16x160_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_16x160_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 16; + bit_from : 15; + bit_to : 0 ; + downto : true ; + } + type (fakeram_16x160_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_16x160_1r1w) { + area : 271.200; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 16; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_16x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_16x160_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_16x160_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_16x160_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_16x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_16x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_16x160_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_16x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_16x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_16x32_1r1w.lib similarity index 77% rename from designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib rename to designs/asap7/NVDLA/sram/lib/fakeram_16x32_1r1w.lib index b35bc37..39ccb1f 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib +++ b/designs/asap7/NVDLA/sram/lib/fakeram_16x32_1r1w.lib @@ -1,8 +1,8 @@ -library(fakeram_16x52_1r1w) { +library(fakeram_16x32_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-03-01 01:35:00Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -46,32 +46,32 @@ library(fakeram_16x52_1r1w) { output_threshold_pct_rise : 50.000; - lu_table_template(fakeram_16x52_1r1w_mem_out_delay_template) { + lu_table_template(fakeram_16x32_1r1w_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - lu_table_template(fakeram_16x52_1r1w_mem_out_slew_template) { + lu_table_template(fakeram_16x32_1r1w_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } - lu_table_template(fakeram_16x52_1r1w_constraint_template) { + lu_table_template(fakeram_16x32_1r1w_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - power_lut_template(fakeram_16x52_1r1w_energy_template_clkslew) { + power_lut_template(fakeram_16x32_1r1w_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } - power_lut_template(fakeram_16x52_1r1w_energy_template_sigslew) { + power_lut_template(fakeram_16x32_1r1w_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); - type (fakeram_16x52_1r1w_DATA) { + type (fakeram_16x32_1r1w_DATA) { base_type : array ; data_type : bit ; bit_width : 16; @@ -79,20 +79,20 @@ library(fakeram_16x52_1r1w) { bit_to : 0 ; downto : true ; } - type (fakeram_16x52_1r1w_ADDRESS) { + type (fakeram_16x32_1r1w_ADDRESS) { base_type : array ; data_type : bit ; - bit_width : 6; - bit_from : 5; + bit_width : 5; + bit_from : 4; bit_to : 0 ; downto : true ; } -cell(fakeram_16x52_1r1w) { - area : 43.006; +cell(fakeram_16x32_1r1w) { + area : 92.987; interface_timing : true; memory() { type : ram; - address_width : 6; + address_width : 5; word_width : 16; } pin(r0_clk) { @@ -101,11 +101,11 @@ cell(fakeram_16x52_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_clkslew) { + rise_power(fakeram_16x32_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_16x52_1r1w_energy_template_clkslew) { + fall_power(fakeram_16x32_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -118,11 +118,11 @@ cell(fakeram_16x52_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_clkslew) { + rise_power(fakeram_16x32_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_16x52_1r1w_energy_template_clkslew) { + fall_power(fakeram_16x32_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -130,7 +130,7 @@ cell(fakeram_16x52_1r1w) { } bus(r0_rd_out) { - bus_type : fakeram_16x52_1r1w_DATA; + bus_type : fakeram_16x32_1r1w_DATA; direction : output; max_capacitance : 0.500; memory_read() { @@ -140,7 +140,7 @@ cell(fakeram_16x52_1r1w) { related_pin : "r0_clk" ; timing_type : rising_edge; timing_sense : non_unate; - cell_rise(fakeram_16x52_1r1w_mem_out_delay_template) { + cell_rise(fakeram_16x32_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -148,7 +148,7 @@ cell(fakeram_16x52_1r1w) { "0.218, 0.218" \ ) } - cell_fall(fakeram_16x52_1r1w_mem_out_delay_template) { + cell_fall(fakeram_16x32_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -156,11 +156,11 @@ cell(fakeram_16x52_1r1w) { "0.218, 0.218" \ ) } - rise_transition(fakeram_16x52_1r1w_mem_out_slew_template) { + rise_transition(fakeram_16x32_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } - fall_transition(fakeram_16x52_1r1w_mem_out_slew_template) { + fall_transition(fakeram_16x32_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } @@ -172,7 +172,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -180,7 +180,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -192,7 +192,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -200,7 +200,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -210,11 +210,11 @@ cell(fakeram_16x52_1r1w) { } } internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -226,7 +226,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -234,7 +234,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -246,7 +246,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -254,7 +254,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -264,11 +264,11 @@ cell(fakeram_16x52_1r1w) { } } internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -280,7 +280,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -288,7 +288,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -300,7 +300,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -308,7 +308,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -318,18 +318,18 @@ cell(fakeram_16x52_1r1w) { } } internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_wd_in) { - bus_type : fakeram_16x52_1r1w_DATA; + bus_type : fakeram_16x32_1r1w_DATA; memory_write() { address : w0_addr_in; clocked_on : "w0_clk"; @@ -339,7 +339,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -347,7 +347,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -359,7 +359,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -367,7 +367,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -378,35 +378,35 @@ cell(fakeram_16x52_1r1w) { } internal_power(){ when : "(! (w0_we_in) )"; - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } internal_power(){ when : "(w0_we_in)"; - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(r0_addr_in) { - bus_type : fakeram_16x52_1r1w_ADDRESS; + bus_type : fakeram_16x32_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -414,7 +414,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -426,7 +426,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -434,7 +434,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -444,24 +444,24 @@ cell(fakeram_16x52_1r1w) { } } internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_addr_in) { - bus_type : fakeram_16x52_1r1w_ADDRESS; + bus_type : fakeram_16x32_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -469,7 +469,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -481,7 +481,7 @@ cell(fakeram_16x52_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { + rise_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -489,7 +489,7 @@ cell(fakeram_16x52_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { + fall_constraint(fakeram_16x32_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -499,11 +499,11 @@ cell(fakeram_16x52_1r1w) { } } internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { + rise_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { + fall_power(fakeram_16x32_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_16x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_16x80_1r1w.lib new file mode 100644 index 0000000..befcac3 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_16x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_16x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_16x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_16x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_16x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_16x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_16x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_16x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 16; + bit_from : 15; + bit_to : 0 ; + downto : true ; + } + type (fakeram_16x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_16x80_1r1w) { + area : 142.061; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 16; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_16x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_16x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_16x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_16x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_16x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_16x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_16x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_16x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_16x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_16x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_16x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_16x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_18x128_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_18x128_1r1w.lib new file mode 100644 index 0000000..aec71d7 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_18x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_18x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_18x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_18x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_18x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_18x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_18x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_18x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 18; + bit_from : 17; + bit_to : 0 ; + downto : true ; + } + type (fakeram_18x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_18x128_1r1w) { + area : 221.153; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 18; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_18x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_18x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_18x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_18x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_18x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_18x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_18x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_18x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_18x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_18x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_18x64_1r1w.lib new file mode 100644 index 0000000..4f5ad49 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_18x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_18x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_18x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_18x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_18x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_18x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_18x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_18x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 18; + bit_from : 17; + bit_to : 0 ; + downto : true ; + } + type (fakeram_18x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_18x64_1r1w) { + area : 117.847; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 18; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_18x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_18x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_18x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_18x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_18x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_18x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_18x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_18x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_18x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_18x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_18x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_18x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_192x32_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_192x32_1r1w.lib new file mode 100644 index 0000000..25fc8d2 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_192x32_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_192x32_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_192x32_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_192x32_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_192x32_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_192x32_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_192x32_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_192x32_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 192; + bit_from : 191; + bit_to : 0 ; + downto : true ; + } + type (fakeram_192x32_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_192x32_1r1w) { + area : 1239.696; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 192; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_192x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_192x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_192x32_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_192x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_192x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_192x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_192x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_192x32_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_192x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_192x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_224x32_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_224x32_1r1w.lib new file mode 100644 index 0000000..4a12d86 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_224x32_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_224x32_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_224x32_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_224x32_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_224x32_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_224x32_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_224x32_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_224x32_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 224; + bit_from : 223; + bit_to : 0 ; + downto : true ; + } + type (fakeram_224x32_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_224x32_1r1w) { + area : 1627.059; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 224; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_224x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_224x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_224x32_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_224x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_224x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_224x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_224x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_224x32_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_224x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_224x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_224x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_224x64_1r1w.lib new file mode 100644 index 0000000..3b5d54d --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_224x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_224x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_224x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_224x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_224x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_224x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_224x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_224x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 224; + bit_from : 223; + bit_to : 0 ; + downto : true ; + } + type (fakeram_224x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_224x64_1r1w) { + area : 1988.635; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 224; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_224x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_224x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_224x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_224x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_224x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_224x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_224x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_224x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_224x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_224x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_224x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_224x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_226x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_226x64_1r1w.lib new file mode 100644 index 0000000..44403a1 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_226x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_226x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_226x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_226x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_226x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_226x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_226x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_226x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 226; + bit_from : 225; + bit_to : 0 ; + downto : true ; + } + type (fakeram_226x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_226x64_1r1w) { + area : 2017.773; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 226; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_226x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_226x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_226x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_226x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_226x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_226x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_226x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_226x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_226x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_226x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_226x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_226x80_1r1w.lib new file mode 100644 index 0000000..31a37ef --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_226x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_226x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_226x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_226x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_226x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_226x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_226x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_226x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 226; + bit_from : 225; + bit_to : 0 ; + downto : true ; + } + type (fakeram_226x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_226x80_1r1w) { + area : 2200.211; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 226; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_226x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_226x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_226x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_226x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_226x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_226x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_226x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_226x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_226x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_226x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_226x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_226x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_22x60_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_22x60_1r1w.lib new file mode 100644 index 0000000..4100c64 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_22x60_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_22x60_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_22x60_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_22x60_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_22x60_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_22x60_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_22x60_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_22x60_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 22; + bit_from : 21; + bit_to : 0 ; + downto : true ; + } + type (fakeram_22x60_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_22x60_1r1w) { + area : 114.617; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 22; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_22x60_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_22x60_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_22x60_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_22x60_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_22x60_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_22x60_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_22x60_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_22x60_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_22x60_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_22x60_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_22x60_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_256x128_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_256x128_1r1w.lib new file mode 100644 index 0000000..cc8c4eb --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_256x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_256x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_256x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_256x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_256x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_256x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_256x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_256x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram_256x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_256x128_1r1w) { + area : 3305.749; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 256; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_256x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_256x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_256x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_256x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_256x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_256x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_256x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_256x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_256x16_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_256x16_1r1w.lib new file mode 100644 index 0000000..3630594 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_256x16_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_256x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_256x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_256x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_256x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_256x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_256x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_256x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram_256x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_256x16_1r1w) { + area : 1859.489; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 256; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_256x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_256x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_256x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_256x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_256x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_256x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_256x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_256x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_256x32_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_256x32_1r1w.lib new file mode 100644 index 0000000..84cf6e5 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_256x32_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_256x32_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_256x32_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_256x32_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_256x32_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_256x32_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_256x32_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_256x32_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram_256x32_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_256x32_1r1w) { + area : 2066.141; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 256; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_256x32_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_256x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_256x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_256x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_256x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_256x32_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_256x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_256x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_256x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_256x80_1r1w.lib new file mode 100644 index 0000000..57ac2c1 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_256x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_256x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_256x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_256x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_256x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_256x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_256x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_256x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } + type (fakeram_256x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_256x80_1r1w) { + area : 2685.945; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 256; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_256x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_256x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_256x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_256x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_256x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_256x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_256x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_256x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_256x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_256x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_256x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_272x16_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_272x16_1r1w.lib new file mode 100644 index 0000000..c031531 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_272x16_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_272x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_272x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_272x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_272x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_272x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_272x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_272x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 272; + bit_from : 271; + bit_to : 0 ; + downto : true ; + } + type (fakeram_272x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_272x16_1r1w) { + area : 2085.472; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 272; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_272x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_272x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_272x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_272x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_272x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_272x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_272x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_272x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_272x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_272x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_272x32_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_272x32_1r1w.lib new file mode 100644 index 0000000..d2cade3 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_272x32_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_272x32_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_272x32_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_272x32_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_272x32_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_272x32_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_272x32_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_272x32_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 272; + bit_from : 271; + bit_to : 0 ; + downto : true ; + } + type (fakeram_272x32_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_272x32_1r1w) { + area : 2305.043; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 272; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_272x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_272x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_272x32_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_272x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_272x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_272x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_272x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_272x32_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_272x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_272x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_272x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_272x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_288x20_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_288x20_1r1w.lib new file mode 100644 index 0000000..943ddb0 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_288x20_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_288x20_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_288x20_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_288x20_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_288x20_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_288x20_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_288x20_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_288x20_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 288; + bit_from : 287; + bit_to : 0 ; + downto : true ; + } + type (fakeram_288x20_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_288x20_1r1w) { + area : 2382.486; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 288; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_288x20_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_288x20_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_288x20_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_288x20_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_288x20_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_288x20_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_288x20_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_288x20_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_288x32_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_288x32_1r1w.lib new file mode 100644 index 0000000..4d1c57b --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_288x32_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_288x32_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_288x32_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_288x32_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_288x32_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_288x32_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_288x32_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_288x32_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 288; + bit_from : 287; + bit_to : 0 ; + downto : true ; + } + type (fakeram_288x32_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_288x32_1r1w) { + area : 2556.829; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 288; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_288x32_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_288x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_288x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_288x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_288x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_288x32_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_288x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_288x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_288x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_288x64_1r1w.lib new file mode 100644 index 0000000..ac362e6 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_288x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_288x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_288x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_288x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_288x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_288x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_288x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_288x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 288; + bit_from : 287; + bit_to : 0 ; + downto : true ; + } + type (fakeram_288x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_288x64_1r1w) { + area : 3021.714; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 288; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_288x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_288x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_288x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_288x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_288x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_288x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_288x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_288x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_288x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_288x80_1r1w.lib new file mode 100644 index 0000000..190cee6 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_288x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_288x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_288x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_288x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_288x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_288x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_288x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_288x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 288; + bit_from : 287; + bit_to : 0 ; + downto : true ; + } + type (fakeram_288x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_288x80_1r1w) { + area : 3254.114; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 288; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_288x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_288x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_288x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_288x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_288x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_288x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_288x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_288x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_288x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_288x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_288x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_32x128_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_32x128_1r1w.lib new file mode 100644 index 0000000..57526da --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_32x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_32x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-02 20:40:55Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_32x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_32x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_32x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_32x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_32x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_32x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_32x128_1r1w) { + area : 232.454; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 32; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_32x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_32x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_32x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_32x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_32x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_32x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_32x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_32x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_32x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_32x32_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_32x32_1r1w.lib new file mode 100644 index 0000000..f59b19e --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_32x32_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_32x32_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_32x32_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_32x32_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_32x32_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_32x32_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_32x32_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_32x32_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x32_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_32x32_1r1w) { + area : 92.987; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 32; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_32x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_32x32_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_32x32_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_32x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_32x32_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_32x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_32x32_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_32x32_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_32x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_32x32_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x32_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x32_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_40x512_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_40x512_1r1w.lib new file mode 100644 index 0000000..ea7558b --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_40x512_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_40x512_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_40x512_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_40x512_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_40x512_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_40x512_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_40x512_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_40x512_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 40; + bit_from : 39; + bit_to : 0 ; + downto : true ; + } + type (fakeram_40x512_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_40x512_1r1w) { + area : 1073.404; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 40; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_40x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_40x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_40x512_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_40x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_40x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_40x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_40x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_40x512_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_40x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_40x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_40x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_40x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_4x256_1r1w.lib similarity index 77% rename from designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib rename to designs/asap7/NVDLA/sram/lib/fakeram_4x256_1r1w.lib index c4214cb..4710bcb 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib +++ b/designs/asap7/NVDLA/sram/lib/fakeram_4x256_1r1w.lib @@ -1,8 +1,8 @@ -library(fakeram_1x256_1r1w) { +library(fakeram_4x256_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-03-01 01:35:00Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -46,40 +46,40 @@ library(fakeram_1x256_1r1w) { output_threshold_pct_rise : 50.000; - lu_table_template(fakeram_1x256_1r1w_mem_out_delay_template) { + lu_table_template(fakeram_4x256_1r1w_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - lu_table_template(fakeram_1x256_1r1w_mem_out_slew_template) { + lu_table_template(fakeram_4x256_1r1w_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } - lu_table_template(fakeram_1x256_1r1w_constraint_template) { + lu_table_template(fakeram_4x256_1r1w_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - power_lut_template(fakeram_1x256_1r1w_energy_template_clkslew) { + power_lut_template(fakeram_4x256_1r1w_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } - power_lut_template(fakeram_1x256_1r1w_energy_template_sigslew) { + power_lut_template(fakeram_4x256_1r1w_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); - type (fakeram_1x256_1r1w_DATA) { + type (fakeram_4x256_1r1w_DATA) { base_type : array ; data_type : bit ; - bit_width : 1; - bit_from : 0; + bit_width : 4; + bit_from : 3; bit_to : 0 ; downto : true ; } - type (fakeram_1x256_1r1w_ADDRESS) { + type (fakeram_4x256_1r1w_ADDRESS) { base_type : array ; data_type : bit ; bit_width : 8; @@ -87,13 +87,13 @@ library(fakeram_1x256_1r1w) { bit_to : 0 ; downto : true ; } -cell(fakeram_1x256_1r1w) { - area : 10.783; +cell(fakeram_4x256_1r1w) { + area : 416.481; interface_timing : true; memory() { type : ram; address_width : 8; - word_width : 1; + word_width : 4; } pin(r0_clk) { direction : input; @@ -101,11 +101,11 @@ cell(fakeram_1x256_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_clkslew) { + rise_power(fakeram_4x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_1x256_1r1w_energy_template_clkslew) { + fall_power(fakeram_4x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -118,11 +118,11 @@ cell(fakeram_1x256_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_clkslew) { + rise_power(fakeram_4x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_1x256_1r1w_energy_template_clkslew) { + fall_power(fakeram_4x256_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -130,7 +130,7 @@ cell(fakeram_1x256_1r1w) { } bus(r0_rd_out) { - bus_type : fakeram_1x256_1r1w_DATA; + bus_type : fakeram_4x256_1r1w_DATA; direction : output; max_capacitance : 0.500; memory_read() { @@ -140,7 +140,7 @@ cell(fakeram_1x256_1r1w) { related_pin : "r0_clk" ; timing_type : rising_edge; timing_sense : non_unate; - cell_rise(fakeram_1x256_1r1w_mem_out_delay_template) { + cell_rise(fakeram_4x256_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -148,7 +148,7 @@ cell(fakeram_1x256_1r1w) { "0.218, 0.218" \ ) } - cell_fall(fakeram_1x256_1r1w_mem_out_delay_template) { + cell_fall(fakeram_4x256_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -156,11 +156,11 @@ cell(fakeram_1x256_1r1w) { "0.218, 0.218" \ ) } - rise_transition(fakeram_1x256_1r1w_mem_out_slew_template) { + rise_transition(fakeram_4x256_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } - fall_transition(fakeram_1x256_1r1w_mem_out_slew_template) { + fall_transition(fakeram_4x256_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } @@ -172,7 +172,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -180,7 +180,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -192,7 +192,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -200,7 +200,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -210,11 +210,11 @@ cell(fakeram_1x256_1r1w) { } } internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -226,7 +226,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -234,7 +234,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -246,7 +246,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -254,7 +254,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -264,11 +264,11 @@ cell(fakeram_1x256_1r1w) { } } internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -280,7 +280,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -288,7 +288,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -300,7 +300,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -308,7 +308,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -318,18 +318,18 @@ cell(fakeram_1x256_1r1w) { } } internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_wd_in) { - bus_type : fakeram_1x256_1r1w_DATA; + bus_type : fakeram_4x256_1r1w_DATA; memory_write() { address : w0_addr_in; clocked_on : "w0_clk"; @@ -339,7 +339,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -347,7 +347,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -359,7 +359,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -367,7 +367,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -378,35 +378,35 @@ cell(fakeram_1x256_1r1w) { } internal_power(){ when : "(! (w0_we_in) )"; - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } internal_power(){ when : "(w0_we_in)"; - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(r0_addr_in) { - bus_type : fakeram_1x256_1r1w_ADDRESS; + bus_type : fakeram_4x256_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -414,7 +414,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -426,7 +426,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -434,7 +434,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -444,24 +444,24 @@ cell(fakeram_1x256_1r1w) { } } internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_addr_in) { - bus_type : fakeram_1x256_1r1w_ADDRESS; + bus_type : fakeram_4x256_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -469,7 +469,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -481,7 +481,7 @@ cell(fakeram_1x256_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { + rise_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -489,7 +489,7 @@ cell(fakeram_1x256_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { + fall_constraint(fakeram_4x256_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -499,11 +499,11 @@ cell(fakeram_1x256_1r1w) { } } internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { + rise_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { + fall_power(fakeram_4x256_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_64x128_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_64x128_1r1w.lib new file mode 100644 index 0000000..cae70b6 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_64x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_64x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x128_1r1w) { + area : 516.549; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 64; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_64x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_64x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_64x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_64x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_64x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_64x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_64x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_64x16_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_64x16_1r1w.lib new file mode 100644 index 0000000..08593ed --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_64x16_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_64x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x16_1r1w) { + area : 185.965; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 64; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_64x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_64x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_64x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_64x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_64x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_64x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_64x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_64x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_64x256_1r1w.lib new file mode 100644 index 0000000..5be81e3 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_64x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_64x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x256_1r1w) { + area : 929.768; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 64; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_64x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_64x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_64x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_64x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_64x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_64x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_64x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_64x512_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_64x512_1r1w.lib new file mode 100644 index 0000000..9c993f8 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_64x512_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_64x512_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x512_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x512_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x512_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x512_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x512_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x512_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x512_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x512_1r1w) { + area : 1756.208; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 64; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_64x512_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_64x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_64x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_64x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_64x512_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_64x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_64x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_64x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_64x64_1r1w.lib new file mode 100644 index 0000000..046bc42 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_64x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_64x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_64x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_64x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_64x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_64x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_64x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_64x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } + type (fakeram_64x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_64x64_1r1w) { + area : 309.929; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 64; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_64x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_64x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_64x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_64x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_64x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_64x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_64x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_64x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_64x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_64x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_64x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_65x160_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_65x160_1r1w.lib new file mode 100644 index 0000000..dc9f6df --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_65x160_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_65x160_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_65x160_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_65x160_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_65x160_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_65x160_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_65x160_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_65x160_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 65; + bit_from : 64; + bit_to : 0 ; + downto : true ; + } + type (fakeram_65x160_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_65x160_1r1w) { + area : 631.159; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 65; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_65x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_65x160_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_65x160_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_65x160_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_65x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_65x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_65x160_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_65x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_65x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_65x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_65x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_66x64_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_66x64_1r1w.lib new file mode 100644 index 0000000..65807c5 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_66x64_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_66x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_66x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_66x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_66x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_66x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_66x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_66x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 66; + bit_from : 65; + bit_to : 0 ; + downto : true ; + } + type (fakeram_66x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_66x64_1r1w) { + area : 322.941; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 66; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_66x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_66x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_66x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_66x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_66x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_66x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_66x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_66x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_66x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_66x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_66x80_1r1w.lib new file mode 100644 index 0000000..7a953fe --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_66x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_66x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_66x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_66x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_66x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_66x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_66x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_66x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 66; + bit_from : 65; + bit_to : 0 ; + downto : true ; + } + type (fakeram_66x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_66x80_1r1w) { + area : 376.221; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 66; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_66x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_66x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_66x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_66x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_66x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_66x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_66x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_66x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_66x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_66x8_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_66x8_1r1w.lib new file mode 100644 index 0000000..1dc0eec --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_66x8_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_66x8_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_66x8_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_66x8_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_66x8_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_66x8_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_66x8_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_66x8_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 66; + bit_from : 65; + bit_to : 0 ; + downto : true ; + } + type (fakeram_66x8_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 3; + bit_from : 2; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_66x8_1r1w) { + area : 191.780; + interface_timing : true; + memory() { + type : ram; + address_width : 3; + word_width : 66; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_66x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_66x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_66x8_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_66x8_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_66x8_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_66x8_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_66x8_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_66x8_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_66x8_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_66x8_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_66x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_66x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_6x128_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_6x128_1r1w.lib new file mode 100644 index 0000000..5988464 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_6x128_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_6x128_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_6x128_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_6x128_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_6x128_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_6x128_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_6x128_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_6x128_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_6x128_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_6x128_1r1w) { + area : 211.471; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 6; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_6x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_6x128_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_6x128_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_6x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_6x128_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_6x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_6x128_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_6x128_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_6x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_6x128_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_6x128_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_6x128_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_72x512_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_72x512_1r1w.lib new file mode 100644 index 0000000..f884d81 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_72x512_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_72x512_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_72x512_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_72x512_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_72x512_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_72x512_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_72x512_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_72x512_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 36; + bit_from : 35; + bit_to : 0 ; + downto : true ; + } + type (fakeram_72x512_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_72x512_1r1w) { + area : 962.467; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 36; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_72x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_72x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_72x512_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_72x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_72x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_72x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_72x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_72x512_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_72x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_72x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_72x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_72x80_1r1w.lib new file mode 100644 index 0000000..86c7194 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_72x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_72x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_72x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_72x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_72x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_72x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_72x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_72x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 72; + bit_from : 71; + bit_to : 0 ; + downto : true ; + } + type (fakeram_72x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_72x80_1r1w) { + area : 421.315; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 72; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_72x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_72x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_72x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_72x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_72x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_72x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_72x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_72x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_72x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_72x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_72x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_72x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_7x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_7x256_1r1w.lib new file mode 100644 index 0000000..66e6384 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_7x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_7x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_7x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_7x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_7x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_7x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_7x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_7x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } + type (fakeram_7x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_7x256_1r1w) { + area : 418.902; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 7; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_7x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_7x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_7x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_7x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_7x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_7x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_7x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_7x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_7x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_7x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_7x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_80x20_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_80x20_1r1w.lib new file mode 100644 index 0000000..16ab10d --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_80x20_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_80x20_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_80x20_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_80x20_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_80x20_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_80x20_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_80x20_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_80x20_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 80; + bit_from : 79; + bit_to : 0 ; + downto : true ; + } + type (fakeram_80x20_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 5; + bit_from : 4; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_80x20_1r1w) { + area : 242.145; + interface_timing : true; + memory() { + type : ram; + address_width : 5; + word_width : 80; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_80x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_80x20_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_80x20_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_80x20_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_80x20_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_80x20_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_80x20_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_80x20_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_80x20_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_80x20_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x20_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x20_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_80x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_80x256_1r1w.lib new file mode 100644 index 0000000..54ed50e --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_80x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_80x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_80x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_80x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_80x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_80x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_80x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_80x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 80; + bit_from : 79; + bit_to : 0 ; + downto : true ; + } + type (fakeram_80x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_80x256_1r1w) { + area : 1194.476; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 80; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_80x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_80x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_80x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_80x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_80x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_80x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_80x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_80x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_80x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_80x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_80x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_80x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_82x160_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_82x160_1r1w.lib new file mode 100644 index 0000000..dcdc048 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_82x160_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_82x160_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_82x160_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_82x160_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_82x160_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_82x160_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_82x160_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_82x160_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 82; + bit_from : 81; + bit_to : 0 ; + downto : true ; + } + type (fakeram_82x160_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_82x160_1r1w) { + area : 831.408; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 82; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_82x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_82x160_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_82x160_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_82x160_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_82x160_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_82x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_82x160_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_82x160_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_82x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_82x160_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x160_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x160_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_82x248_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_82x248_1r1w.lib new file mode 100644 index 0000000..13ba4a6 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_82x248_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_82x248_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_82x248_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_82x248_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_82x248_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_82x248_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_82x248_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_82x248_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 82; + bit_from : 81; + bit_to : 0 ; + downto : true ; + } + type (fakeram_82x248_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_82x248_1r1w) { + area : 1195.397; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 82; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_82x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_82x248_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_82x248_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_82x248_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_82x248_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_82x248_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_82x248_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_82x248_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_82x248_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_82x248_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_82x248_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_82x248_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_8x256_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_8x256_1r1w.lib new file mode 100644 index 0000000..6e416a6 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_8x256_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_8x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_8x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_8x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_8x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_8x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_8x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_8x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_8x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_8x256_1r1w) { + area : 419.702; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 8; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_8x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_8x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_8x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_8x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_8x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_8x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_8x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_8x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_8x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_8x512_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_8x512_1r1w.lib new file mode 100644 index 0000000..90a9e0c --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_8x512_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_8x512_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_8x512_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_8x512_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_8x512_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_8x512_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_8x512_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_8x512_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_8x512_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_8x512_1r1w) { + area : 832.953; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 8; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_8x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_8x512_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_8x512_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_8x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_8x512_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_8x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_8x512_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_8x512_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_8x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_8x512_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_8x512_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_8x512_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NVDLA/sram/lib/fakeram_9x80_1r1w.lib b/designs/asap7/NVDLA/sram/lib/fakeram_9x80_1r1w.lib new file mode 100644 index 0000000..eb3e777 --- /dev/null +++ b/designs/asap7/NVDLA/sram/lib/fakeram_9x80_1r1w.lib @@ -0,0 +1,515 @@ +library(fakeram_9x80_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-01 01:35:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_9x80_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_9x80_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_9x80_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_9x80_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_9x80_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_9x80_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } + type (fakeram_9x80_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_9x80_1r1w) { + area : 136.410; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 9; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_9x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_9x80_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_9x80_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_9x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_9x80_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_9x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_9x80_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_9x80_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_9x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_9x80_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_9x80_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_9x80_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NyuziProcessor/config.mk b/designs/asap7/NyuziProcessor/config.mk deleted file mode 100644 index 3b151bb..0000000 --- a/designs/asap7/NyuziProcessor/config.mk +++ /dev/null @@ -1,37 +0,0 @@ -export DESIGN_NAME = NyuziProcessor -export PLATFORM = asap7 - --include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk - -export SYNTH_HIERARCHICAL = 1 - -export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_1x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_16x52_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_18x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_2r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_32x128_2r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x2048_1r1w.lef - -export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_1x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_16x52_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_18x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_2r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_32x128_2r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x2048_1r1w.lib - -export ABC_AREA = 1 - -export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export CORE_AREA = 5 5 655 655 -export DIE_AREA = 0 0 660 660 - -export PLACE_DENSITY_LB_ADDON = 0.15 - -export MACRO_PLACE_HALO = 5 5 - -export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/NyuziProcessor/constraint.sdc b/designs/asap7/NyuziProcessor/constraint.sdc deleted file mode 100644 index 1f25d2c..0000000 --- a/designs/asap7/NyuziProcessor/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design NyuziProcessor - -set clk_name clk -set clk_port_name clk -set clk_period 2400 -set clk_io_pct 0.15 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef deleted file mode 100644 index ccfafef..0000000 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef +++ /dev/null @@ -1,295 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_1x256_1r1w - FOREIGN fakeram_1x256_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 5.184 BY 20.736 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; - END - END w0_wd_in[0] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; - END - END r0_rd_out[0] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.484 0.024 2.508 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.692 0.024 4.716 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.900 0.024 6.924 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.108 0.024 9.132 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 0.276 5.184 0.300 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 2.484 5.184 2.508 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 4.692 5.184 4.716 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 6.900 5.184 6.924 ; - END - END w0_addr_in[7] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.316 0.024 11.340 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.524 0.024 13.548 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.732 0.024 15.756 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.940 0.024 17.964 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 9.108 5.184 9.132 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 11.316 5.184 11.340 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 13.524 5.184 13.548 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 5.160 15.732 5.184 15.756 ; - END - END r0_addr_in[7] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.207 20.718 0.225 20.736 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.963 20.718 0.981 20.736 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.719 20.718 1.737 20.736 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.475 20.718 2.493 20.736 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.231 20.718 3.249 20.736 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER M4 ; - RECT 0.108 0.192 5.076 0.288 ; - RECT 0.108 0.960 5.076 1.056 ; - RECT 0.108 1.728 5.076 1.824 ; - RECT 0.108 2.496 5.076 2.592 ; - RECT 0.108 3.264 5.076 3.360 ; - RECT 0.108 4.032 5.076 4.128 ; - RECT 0.108 4.800 5.076 4.896 ; - RECT 0.108 5.568 5.076 5.664 ; - RECT 0.108 6.336 5.076 6.432 ; - RECT 0.108 7.104 5.076 7.200 ; - RECT 0.108 7.872 5.076 7.968 ; - RECT 0.108 8.640 5.076 8.736 ; - RECT 0.108 9.408 5.076 9.504 ; - RECT 0.108 10.176 5.076 10.272 ; - RECT 0.108 10.944 5.076 11.040 ; - RECT 0.108 11.712 5.076 11.808 ; - RECT 0.108 12.480 5.076 12.576 ; - RECT 0.108 13.248 5.076 13.344 ; - RECT 0.108 14.016 5.076 14.112 ; - RECT 0.108 14.784 5.076 14.880 ; - RECT 0.108 15.552 5.076 15.648 ; - RECT 0.108 16.320 5.076 16.416 ; - RECT 0.108 17.088 5.076 17.184 ; - RECT 0.108 17.856 5.076 17.952 ; - RECT 0.108 18.624 5.076 18.720 ; - RECT 0.108 19.392 5.076 19.488 ; - RECT 0.108 20.160 5.076 20.256 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M4 ; - RECT 0.108 0.192 5.076 0.288 ; - RECT 0.108 0.960 5.076 1.056 ; - RECT 0.108 1.728 5.076 1.824 ; - RECT 0.108 2.496 5.076 2.592 ; - RECT 0.108 3.264 5.076 3.360 ; - RECT 0.108 4.032 5.076 4.128 ; - RECT 0.108 4.800 5.076 4.896 ; - RECT 0.108 5.568 5.076 5.664 ; - RECT 0.108 6.336 5.076 6.432 ; - RECT 0.108 7.104 5.076 7.200 ; - RECT 0.108 7.872 5.076 7.968 ; - RECT 0.108 8.640 5.076 8.736 ; - RECT 0.108 9.408 5.076 9.504 ; - RECT 0.108 10.176 5.076 10.272 ; - RECT 0.108 10.944 5.076 11.040 ; - RECT 0.108 11.712 5.076 11.808 ; - RECT 0.108 12.480 5.076 12.576 ; - RECT 0.108 13.248 5.076 13.344 ; - RECT 0.108 14.016 5.076 14.112 ; - RECT 0.108 14.784 5.076 14.880 ; - RECT 0.108 15.552 5.076 15.648 ; - RECT 0.108 16.320 5.076 16.416 ; - RECT 0.108 17.088 5.076 17.184 ; - RECT 0.108 17.856 5.076 17.952 ; - RECT 0.108 18.624 5.076 18.720 ; - RECT 0.108 19.392 5.076 19.488 ; - RECT 0.108 20.160 5.076 20.256 ; - END - END VDD - OBS - LAYER M1 ; - RECT 0 0 5.184 20.736 ; - LAYER M2 ; - RECT 0 0 5.184 20.736 ; - LAYER M3 ; - RECT 0 0 5.184 20.736 ; - LAYER M4 ; - RECT 0 0 5.184 20.736 ; - END -END fakeram_1x256_1r1w - -END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef deleted file mode 100644 index 1a00c4b..0000000 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef +++ /dev/null @@ -1,9925 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_512x2048_1r1w - FOREIGN fakeram_512x2048_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 265.421 BY 165.888 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.884 0.024 4.908 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.036 0.024 6.060 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.188 0.024 7.212 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.340 0.024 8.364 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.492 0.024 9.516 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.644 0.024 10.668 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.796 0.024 11.820 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.948 0.024 12.972 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.100 0.024 14.124 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.252 0.024 15.276 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.404 0.024 16.428 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.556 0.024 17.580 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.708 0.024 18.732 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 19.860 0.024 19.884 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 21.012 0.024 21.036 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 22.164 0.024 22.188 ; - END - END w0_wd_in[19] - PIN w0_wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 23.316 0.024 23.340 ; - END - END w0_wd_in[20] - PIN w0_wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 24.468 0.024 24.492 ; - END - END w0_wd_in[21] - PIN w0_wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 25.620 0.024 25.644 ; - END - END w0_wd_in[22] - PIN w0_wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 26.772 0.024 26.796 ; - END - END w0_wd_in[23] - PIN w0_wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 27.924 0.024 27.948 ; - END - END w0_wd_in[24] - PIN w0_wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 29.076 0.024 29.100 ; - END - END w0_wd_in[25] - PIN w0_wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 30.228 0.024 30.252 ; - END - END w0_wd_in[26] - PIN w0_wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 31.380 0.024 31.404 ; - END - END w0_wd_in[27] - PIN w0_wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 32.532 0.024 32.556 ; - END - END w0_wd_in[28] - PIN w0_wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 33.684 0.024 33.708 ; - END - END w0_wd_in[29] - PIN w0_wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 34.836 0.024 34.860 ; - END - END w0_wd_in[30] - PIN w0_wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 35.988 0.024 36.012 ; - END - END w0_wd_in[31] - PIN w0_wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 37.140 0.024 37.164 ; - END - END w0_wd_in[32] - PIN w0_wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 38.292 0.024 38.316 ; - END - END w0_wd_in[33] - PIN w0_wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 39.444 0.024 39.468 ; - END - END w0_wd_in[34] - PIN w0_wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 40.596 0.024 40.620 ; - END - END w0_wd_in[35] - PIN w0_wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 41.748 0.024 41.772 ; - END - END w0_wd_in[36] - PIN w0_wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 42.900 0.024 42.924 ; - END - END w0_wd_in[37] - PIN w0_wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 44.052 0.024 44.076 ; - END - END w0_wd_in[38] - PIN w0_wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 45.204 0.024 45.228 ; - END - END w0_wd_in[39] - PIN w0_wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 46.356 0.024 46.380 ; - END - END w0_wd_in[40] - PIN w0_wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 47.508 0.024 47.532 ; - END - END w0_wd_in[41] - PIN w0_wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 48.660 0.024 48.684 ; - END - END w0_wd_in[42] - PIN w0_wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 49.812 0.024 49.836 ; - END - END w0_wd_in[43] - PIN w0_wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 50.964 0.024 50.988 ; - END - END w0_wd_in[44] - PIN w0_wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 52.116 0.024 52.140 ; - END - END w0_wd_in[45] - PIN w0_wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 53.268 0.024 53.292 ; - END - END w0_wd_in[46] - PIN w0_wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 54.420 0.024 54.444 ; - END - END w0_wd_in[47] - PIN w0_wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 55.572 0.024 55.596 ; - END - END w0_wd_in[48] - PIN w0_wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 56.724 0.024 56.748 ; - END - END w0_wd_in[49] - PIN w0_wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 57.876 0.024 57.900 ; - END - END w0_wd_in[50] - PIN w0_wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 59.028 0.024 59.052 ; - END - END w0_wd_in[51] - PIN w0_wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 60.180 0.024 60.204 ; - END - END w0_wd_in[52] - PIN w0_wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 61.332 0.024 61.356 ; - END - END w0_wd_in[53] - PIN w0_wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 62.484 0.024 62.508 ; - END - END w0_wd_in[54] - PIN w0_wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 63.636 0.024 63.660 ; - END - END w0_wd_in[55] - PIN w0_wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 64.788 0.024 64.812 ; - END - END w0_wd_in[56] - PIN w0_wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 65.940 0.024 65.964 ; - END - END w0_wd_in[57] - PIN w0_wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 67.092 0.024 67.116 ; - END - END w0_wd_in[58] - PIN w0_wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 68.244 0.024 68.268 ; - END - END w0_wd_in[59] - PIN w0_wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 69.396 0.024 69.420 ; - END - END w0_wd_in[60] - PIN w0_wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 70.548 0.024 70.572 ; - END - END w0_wd_in[61] - PIN w0_wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 71.700 0.024 71.724 ; - END - END w0_wd_in[62] - PIN w0_wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 72.852 0.024 72.876 ; - END - END w0_wd_in[63] - PIN w0_wd_in[64] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 74.004 0.024 74.028 ; - END - END w0_wd_in[64] - PIN w0_wd_in[65] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 75.156 0.024 75.180 ; - END - END w0_wd_in[65] - PIN w0_wd_in[66] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 76.308 0.024 76.332 ; - END - END w0_wd_in[66] - PIN w0_wd_in[67] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 77.460 0.024 77.484 ; - END - END w0_wd_in[67] - PIN w0_wd_in[68] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 78.612 0.024 78.636 ; - END - END w0_wd_in[68] - PIN w0_wd_in[69] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 79.764 0.024 79.788 ; - END - END w0_wd_in[69] - PIN w0_wd_in[70] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 80.916 0.024 80.940 ; - END - END w0_wd_in[70] - PIN w0_wd_in[71] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 82.068 0.024 82.092 ; - END - END w0_wd_in[71] - PIN w0_wd_in[72] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 83.220 0.024 83.244 ; - END - END w0_wd_in[72] - PIN w0_wd_in[73] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 84.372 0.024 84.396 ; - END - END w0_wd_in[73] - PIN w0_wd_in[74] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 85.524 0.024 85.548 ; - END - END w0_wd_in[74] - PIN w0_wd_in[75] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 86.676 0.024 86.700 ; - END - END w0_wd_in[75] - PIN w0_wd_in[76] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 87.828 0.024 87.852 ; - END - END w0_wd_in[76] - PIN w0_wd_in[77] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 88.980 0.024 89.004 ; - END - END w0_wd_in[77] - PIN w0_wd_in[78] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 90.132 0.024 90.156 ; - END - END w0_wd_in[78] - PIN w0_wd_in[79] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 91.284 0.024 91.308 ; - END - END w0_wd_in[79] - PIN w0_wd_in[80] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 92.436 0.024 92.460 ; - END - END w0_wd_in[80] - PIN w0_wd_in[81] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 93.588 0.024 93.612 ; - END - END w0_wd_in[81] - PIN w0_wd_in[82] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 94.740 0.024 94.764 ; - END - END w0_wd_in[82] - PIN w0_wd_in[83] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 95.892 0.024 95.916 ; - END - END w0_wd_in[83] - PIN w0_wd_in[84] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 97.044 0.024 97.068 ; - END - END w0_wd_in[84] - PIN w0_wd_in[85] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 98.196 0.024 98.220 ; - END - END w0_wd_in[85] - PIN w0_wd_in[86] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 99.348 0.024 99.372 ; - END - END w0_wd_in[86] - PIN w0_wd_in[87] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 100.500 0.024 100.524 ; - END - END w0_wd_in[87] - PIN w0_wd_in[88] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 101.652 0.024 101.676 ; - END - END w0_wd_in[88] - PIN w0_wd_in[89] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 102.804 0.024 102.828 ; - END - END w0_wd_in[89] - PIN w0_wd_in[90] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 103.956 0.024 103.980 ; - END - END w0_wd_in[90] - PIN w0_wd_in[91] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 105.108 0.024 105.132 ; - END - END w0_wd_in[91] - PIN w0_wd_in[92] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 106.260 0.024 106.284 ; - END - END w0_wd_in[92] - PIN w0_wd_in[93] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 107.412 0.024 107.436 ; - END - END w0_wd_in[93] - PIN w0_wd_in[94] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 108.564 0.024 108.588 ; - END - END w0_wd_in[94] - PIN w0_wd_in[95] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 109.716 0.024 109.740 ; - END - END w0_wd_in[95] - PIN w0_wd_in[96] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 110.868 0.024 110.892 ; - END - END w0_wd_in[96] - PIN w0_wd_in[97] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 112.020 0.024 112.044 ; - END - END w0_wd_in[97] - PIN w0_wd_in[98] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 113.172 0.024 113.196 ; - END - END w0_wd_in[98] - PIN w0_wd_in[99] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 114.324 0.024 114.348 ; - END - END w0_wd_in[99] - PIN w0_wd_in[100] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 115.476 0.024 115.500 ; - END - END w0_wd_in[100] - PIN w0_wd_in[101] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 116.628 0.024 116.652 ; - END - END w0_wd_in[101] - PIN w0_wd_in[102] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 117.780 0.024 117.804 ; - END - END w0_wd_in[102] - PIN w0_wd_in[103] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 118.932 0.024 118.956 ; - END - END w0_wd_in[103] - PIN w0_wd_in[104] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 120.084 0.024 120.108 ; - END - END w0_wd_in[104] - PIN w0_wd_in[105] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 121.236 0.024 121.260 ; - END - END w0_wd_in[105] - PIN w0_wd_in[106] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 122.388 0.024 122.412 ; - END - END w0_wd_in[106] - PIN w0_wd_in[107] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 123.540 0.024 123.564 ; - END - END w0_wd_in[107] - PIN w0_wd_in[108] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 124.692 0.024 124.716 ; - END - END w0_wd_in[108] - PIN w0_wd_in[109] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 125.844 0.024 125.868 ; - END - END w0_wd_in[109] - PIN w0_wd_in[110] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 126.996 0.024 127.020 ; - END - END w0_wd_in[110] - PIN w0_wd_in[111] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 128.148 0.024 128.172 ; - END - END w0_wd_in[111] - PIN w0_wd_in[112] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 129.300 0.024 129.324 ; - END - END w0_wd_in[112] - PIN w0_wd_in[113] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 130.452 0.024 130.476 ; - END - END w0_wd_in[113] - PIN w0_wd_in[114] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 131.604 0.024 131.628 ; - END - END w0_wd_in[114] - PIN w0_wd_in[115] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 132.756 0.024 132.780 ; - END - END w0_wd_in[115] - PIN w0_wd_in[116] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 133.908 0.024 133.932 ; - END - END w0_wd_in[116] - PIN w0_wd_in[117] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 135.060 0.024 135.084 ; - END - END w0_wd_in[117] - PIN w0_wd_in[118] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 136.212 0.024 136.236 ; - END - END w0_wd_in[118] - PIN w0_wd_in[119] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 137.364 0.024 137.388 ; - END - END w0_wd_in[119] - PIN w0_wd_in[120] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 138.516 0.024 138.540 ; - END - END w0_wd_in[120] - PIN w0_wd_in[121] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 139.668 0.024 139.692 ; - END - END w0_wd_in[121] - PIN w0_wd_in[122] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 140.820 0.024 140.844 ; - END - END w0_wd_in[122] - PIN w0_wd_in[123] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 141.972 0.024 141.996 ; - END - END w0_wd_in[123] - PIN w0_wd_in[124] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 143.124 0.024 143.148 ; - END - END w0_wd_in[124] - PIN w0_wd_in[125] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 144.276 0.024 144.300 ; - END - END w0_wd_in[125] - PIN w0_wd_in[126] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 145.428 0.024 145.452 ; - END - END w0_wd_in[126] - PIN w0_wd_in[127] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 146.580 0.024 146.604 ; - END - END w0_wd_in[127] - PIN w0_wd_in[128] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.276 265.421 0.300 ; - END - END w0_wd_in[128] - PIN w0_wd_in[129] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.428 265.421 1.452 ; - END - END w0_wd_in[129] - PIN w0_wd_in[130] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.580 265.421 2.604 ; - END - END w0_wd_in[130] - PIN w0_wd_in[131] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.732 265.421 3.756 ; - END - END w0_wd_in[131] - PIN w0_wd_in[132] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.884 265.421 4.908 ; - END - END w0_wd_in[132] - PIN w0_wd_in[133] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.036 265.421 6.060 ; - END - END w0_wd_in[133] - PIN w0_wd_in[134] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.188 265.421 7.212 ; - END - END w0_wd_in[134] - PIN w0_wd_in[135] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.340 265.421 8.364 ; - END - END w0_wd_in[135] - PIN w0_wd_in[136] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.492 265.421 9.516 ; - END - END w0_wd_in[136] - PIN w0_wd_in[137] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.644 265.421 10.668 ; - END - END w0_wd_in[137] - PIN w0_wd_in[138] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.796 265.421 11.820 ; - END - END w0_wd_in[138] - PIN w0_wd_in[139] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.948 265.421 12.972 ; - END - END w0_wd_in[139] - PIN w0_wd_in[140] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.100 265.421 14.124 ; - END - END w0_wd_in[140] - PIN w0_wd_in[141] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.252 265.421 15.276 ; - END - END w0_wd_in[141] - PIN w0_wd_in[142] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.404 265.421 16.428 ; - END - END w0_wd_in[142] - PIN w0_wd_in[143] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.556 265.421 17.580 ; - END - END w0_wd_in[143] - PIN w0_wd_in[144] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.708 265.421 18.732 ; - END - END w0_wd_in[144] - PIN w0_wd_in[145] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 19.860 265.421 19.884 ; - END - END w0_wd_in[145] - PIN w0_wd_in[146] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 21.012 265.421 21.036 ; - END - END w0_wd_in[146] - PIN w0_wd_in[147] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 22.164 265.421 22.188 ; - END - END w0_wd_in[147] - PIN w0_wd_in[148] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 23.316 265.421 23.340 ; - END - END w0_wd_in[148] - PIN w0_wd_in[149] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 24.468 265.421 24.492 ; - END - END w0_wd_in[149] - PIN w0_wd_in[150] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 25.620 265.421 25.644 ; - END - END w0_wd_in[150] - PIN w0_wd_in[151] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 26.772 265.421 26.796 ; - END - END w0_wd_in[151] - PIN w0_wd_in[152] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 27.924 265.421 27.948 ; - END - END w0_wd_in[152] - PIN w0_wd_in[153] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 29.076 265.421 29.100 ; - END - END w0_wd_in[153] - PIN w0_wd_in[154] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 30.228 265.421 30.252 ; - END - END w0_wd_in[154] - PIN w0_wd_in[155] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 31.380 265.421 31.404 ; - END - END w0_wd_in[155] - PIN w0_wd_in[156] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 32.532 265.421 32.556 ; - END - END w0_wd_in[156] - PIN w0_wd_in[157] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 33.684 265.421 33.708 ; - END - END w0_wd_in[157] - PIN w0_wd_in[158] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 34.836 265.421 34.860 ; - END - END w0_wd_in[158] - PIN w0_wd_in[159] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 35.988 265.421 36.012 ; - END - END w0_wd_in[159] - PIN w0_wd_in[160] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 37.140 265.421 37.164 ; - END - END w0_wd_in[160] - PIN w0_wd_in[161] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 38.292 265.421 38.316 ; - END - END w0_wd_in[161] - PIN w0_wd_in[162] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 39.444 265.421 39.468 ; - END - END w0_wd_in[162] - PIN w0_wd_in[163] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 40.596 265.421 40.620 ; - END - END w0_wd_in[163] - PIN w0_wd_in[164] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 41.748 265.421 41.772 ; - END - END w0_wd_in[164] - PIN w0_wd_in[165] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 42.900 265.421 42.924 ; - END - END w0_wd_in[165] - PIN w0_wd_in[166] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 44.052 265.421 44.076 ; - END - END w0_wd_in[166] - PIN w0_wd_in[167] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 45.204 265.421 45.228 ; - END - END w0_wd_in[167] - PIN w0_wd_in[168] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 46.356 265.421 46.380 ; - END - END w0_wd_in[168] - PIN w0_wd_in[169] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 47.508 265.421 47.532 ; - END - END w0_wd_in[169] - PIN w0_wd_in[170] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 48.660 265.421 48.684 ; - END - END w0_wd_in[170] - PIN w0_wd_in[171] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 49.812 265.421 49.836 ; - END - END w0_wd_in[171] - PIN w0_wd_in[172] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 50.964 265.421 50.988 ; - END - END w0_wd_in[172] - PIN w0_wd_in[173] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 52.116 265.421 52.140 ; - END - END w0_wd_in[173] - PIN w0_wd_in[174] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 53.268 265.421 53.292 ; - END - END w0_wd_in[174] - PIN w0_wd_in[175] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 54.420 265.421 54.444 ; - END - END w0_wd_in[175] - PIN w0_wd_in[176] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 55.572 265.421 55.596 ; - END - END w0_wd_in[176] - PIN w0_wd_in[177] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 56.724 265.421 56.748 ; - END - END w0_wd_in[177] - PIN w0_wd_in[178] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 57.876 265.421 57.900 ; - END - END w0_wd_in[178] - PIN w0_wd_in[179] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 59.028 265.421 59.052 ; - END - END w0_wd_in[179] - PIN w0_wd_in[180] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 60.180 265.421 60.204 ; - END - END w0_wd_in[180] - PIN w0_wd_in[181] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 61.332 265.421 61.356 ; - END - END w0_wd_in[181] - PIN w0_wd_in[182] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 62.484 265.421 62.508 ; - END - END w0_wd_in[182] - PIN w0_wd_in[183] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 63.636 265.421 63.660 ; - END - END w0_wd_in[183] - PIN w0_wd_in[184] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 64.788 265.421 64.812 ; - END - END w0_wd_in[184] - PIN w0_wd_in[185] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 65.940 265.421 65.964 ; - END - END w0_wd_in[185] - PIN w0_wd_in[186] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 67.092 265.421 67.116 ; - END - END w0_wd_in[186] - PIN w0_wd_in[187] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 68.244 265.421 68.268 ; - END - END w0_wd_in[187] - PIN w0_wd_in[188] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 69.396 265.421 69.420 ; - END - END w0_wd_in[188] - PIN w0_wd_in[189] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 70.548 265.421 70.572 ; - END - END w0_wd_in[189] - PIN w0_wd_in[190] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 71.700 265.421 71.724 ; - END - END w0_wd_in[190] - PIN w0_wd_in[191] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 72.852 265.421 72.876 ; - END - END w0_wd_in[191] - PIN w0_wd_in[192] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 74.004 265.421 74.028 ; - END - END w0_wd_in[192] - PIN w0_wd_in[193] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 75.156 265.421 75.180 ; - END - END w0_wd_in[193] - PIN w0_wd_in[194] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 76.308 265.421 76.332 ; - END - END w0_wd_in[194] - PIN w0_wd_in[195] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 77.460 265.421 77.484 ; - END - END w0_wd_in[195] - PIN w0_wd_in[196] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 78.612 265.421 78.636 ; - END - END w0_wd_in[196] - PIN w0_wd_in[197] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 79.764 265.421 79.788 ; - END - END w0_wd_in[197] - PIN w0_wd_in[198] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 80.916 265.421 80.940 ; - END - END w0_wd_in[198] - PIN w0_wd_in[199] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 82.068 265.421 82.092 ; - END - END w0_wd_in[199] - PIN w0_wd_in[200] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 83.220 265.421 83.244 ; - END - END w0_wd_in[200] - PIN w0_wd_in[201] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 84.372 265.421 84.396 ; - END - END w0_wd_in[201] - PIN w0_wd_in[202] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 85.524 265.421 85.548 ; - END - END w0_wd_in[202] - PIN w0_wd_in[203] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 86.676 265.421 86.700 ; - END - END w0_wd_in[203] - PIN w0_wd_in[204] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 87.828 265.421 87.852 ; - END - END w0_wd_in[204] - PIN w0_wd_in[205] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 88.980 265.421 89.004 ; - END - END w0_wd_in[205] - PIN w0_wd_in[206] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 90.132 265.421 90.156 ; - END - END w0_wd_in[206] - PIN w0_wd_in[207] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 91.284 265.421 91.308 ; - END - END w0_wd_in[207] - PIN w0_wd_in[208] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 92.436 265.421 92.460 ; - END - END w0_wd_in[208] - PIN w0_wd_in[209] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 93.588 265.421 93.612 ; - END - END w0_wd_in[209] - PIN w0_wd_in[210] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 94.740 265.421 94.764 ; - END - END w0_wd_in[210] - PIN w0_wd_in[211] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 95.892 265.421 95.916 ; - END - END w0_wd_in[211] - PIN w0_wd_in[212] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 97.044 265.421 97.068 ; - END - END w0_wd_in[212] - PIN w0_wd_in[213] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 98.196 265.421 98.220 ; - END - END w0_wd_in[213] - PIN w0_wd_in[214] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 99.348 265.421 99.372 ; - END - END w0_wd_in[214] - PIN w0_wd_in[215] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 100.500 265.421 100.524 ; - END - END w0_wd_in[215] - PIN w0_wd_in[216] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 101.652 265.421 101.676 ; - END - END w0_wd_in[216] - PIN w0_wd_in[217] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 102.804 265.421 102.828 ; - END - END w0_wd_in[217] - PIN w0_wd_in[218] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 103.956 265.421 103.980 ; - END - END w0_wd_in[218] - PIN w0_wd_in[219] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 105.108 265.421 105.132 ; - END - END w0_wd_in[219] - PIN w0_wd_in[220] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 106.260 265.421 106.284 ; - END - END w0_wd_in[220] - PIN w0_wd_in[221] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 107.412 265.421 107.436 ; - END - END w0_wd_in[221] - PIN w0_wd_in[222] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 108.564 265.421 108.588 ; - END - END w0_wd_in[222] - PIN w0_wd_in[223] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 109.716 265.421 109.740 ; - END - END w0_wd_in[223] - PIN w0_wd_in[224] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 110.868 265.421 110.892 ; - END - END w0_wd_in[224] - PIN w0_wd_in[225] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 112.020 265.421 112.044 ; - END - END w0_wd_in[225] - PIN w0_wd_in[226] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 113.172 265.421 113.196 ; - END - END w0_wd_in[226] - PIN w0_wd_in[227] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 114.324 265.421 114.348 ; - END - END w0_wd_in[227] - PIN w0_wd_in[228] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 115.476 265.421 115.500 ; - END - END w0_wd_in[228] - PIN w0_wd_in[229] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 116.628 265.421 116.652 ; - END - END w0_wd_in[229] - PIN w0_wd_in[230] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 117.780 265.421 117.804 ; - END - END w0_wd_in[230] - PIN w0_wd_in[231] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 118.932 265.421 118.956 ; - END - END w0_wd_in[231] - PIN w0_wd_in[232] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 120.084 265.421 120.108 ; - END - END w0_wd_in[232] - PIN w0_wd_in[233] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 121.236 265.421 121.260 ; - END - END w0_wd_in[233] - PIN w0_wd_in[234] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 122.388 265.421 122.412 ; - END - END w0_wd_in[234] - PIN w0_wd_in[235] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 123.540 265.421 123.564 ; - END - END w0_wd_in[235] - PIN w0_wd_in[236] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 124.692 265.421 124.716 ; - END - END w0_wd_in[236] - PIN w0_wd_in[237] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 125.844 265.421 125.868 ; - END - END w0_wd_in[237] - PIN w0_wd_in[238] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 126.996 265.421 127.020 ; - END - END w0_wd_in[238] - PIN w0_wd_in[239] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 128.148 265.421 128.172 ; - END - END w0_wd_in[239] - PIN w0_wd_in[240] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 129.300 265.421 129.324 ; - END - END w0_wd_in[240] - PIN w0_wd_in[241] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 130.452 265.421 130.476 ; - END - END w0_wd_in[241] - PIN w0_wd_in[242] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 131.604 265.421 131.628 ; - END - END w0_wd_in[242] - PIN w0_wd_in[243] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 132.756 265.421 132.780 ; - END - END w0_wd_in[243] - PIN w0_wd_in[244] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 133.908 265.421 133.932 ; - END - END w0_wd_in[244] - PIN w0_wd_in[245] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 135.060 265.421 135.084 ; - END - END w0_wd_in[245] - PIN w0_wd_in[246] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 136.212 265.421 136.236 ; - END - END w0_wd_in[246] - PIN w0_wd_in[247] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 137.364 265.421 137.388 ; - END - END w0_wd_in[247] - PIN w0_wd_in[248] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 138.516 265.421 138.540 ; - END - END w0_wd_in[248] - PIN w0_wd_in[249] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 139.668 265.421 139.692 ; - END - END w0_wd_in[249] - PIN w0_wd_in[250] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 140.820 265.421 140.844 ; - END - END w0_wd_in[250] - PIN w0_wd_in[251] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 141.972 265.421 141.996 ; - END - END w0_wd_in[251] - PIN w0_wd_in[252] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 143.124 265.421 143.148 ; - END - END w0_wd_in[252] - PIN w0_wd_in[253] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 144.276 265.421 144.300 ; - END - END w0_wd_in[253] - PIN w0_wd_in[254] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 145.428 265.421 145.452 ; - END - END w0_wd_in[254] - PIN w0_wd_in[255] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 146.580 265.421 146.604 ; - END - END w0_wd_in[255] - PIN w0_wd_in[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; - END - END w0_wd_in[256] - PIN w0_wd_in[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.711 0.000 0.729 0.018 ; - END - END w0_wd_in[257] - PIN w0_wd_in[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.215 0.000 1.233 0.018 ; - END - END w0_wd_in[258] - PIN w0_wd_in[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.719 0.000 1.737 0.018 ; - END - END w0_wd_in[259] - PIN w0_wd_in[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.223 0.000 2.241 0.018 ; - END - END w0_wd_in[260] - PIN w0_wd_in[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.727 0.000 2.745 0.018 ; - END - END w0_wd_in[261] - PIN w0_wd_in[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.231 0.000 3.249 0.018 ; - END - END w0_wd_in[262] - PIN w0_wd_in[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.735 0.000 3.753 0.018 ; - END - END w0_wd_in[263] - PIN w0_wd_in[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.239 0.000 4.257 0.018 ; - END - END w0_wd_in[264] - PIN w0_wd_in[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; - END - END w0_wd_in[265] - PIN w0_wd_in[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.247 0.000 5.265 0.018 ; - END - END w0_wd_in[266] - PIN w0_wd_in[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.751 0.000 5.769 0.018 ; - END - END w0_wd_in[267] - PIN w0_wd_in[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.255 0.000 6.273 0.018 ; - END - END w0_wd_in[268] - PIN w0_wd_in[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; - END - END w0_wd_in[269] - PIN w0_wd_in[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 7.263 0.000 7.281 0.018 ; - END - END w0_wd_in[270] - PIN w0_wd_in[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 7.767 0.000 7.785 0.018 ; - END - END w0_wd_in[271] - PIN w0_wd_in[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 8.271 0.000 8.289 0.018 ; - END - END w0_wd_in[272] - PIN w0_wd_in[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 8.775 0.000 8.793 0.018 ; - END - END w0_wd_in[273] - PIN w0_wd_in[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; - END - END w0_wd_in[274] - PIN w0_wd_in[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.783 0.000 9.801 0.018 ; - END - END w0_wd_in[275] - PIN w0_wd_in[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 10.287 0.000 10.305 0.018 ; - END - END w0_wd_in[276] - PIN w0_wd_in[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 10.791 0.000 10.809 0.018 ; - END - END w0_wd_in[277] - PIN w0_wd_in[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 11.295 0.000 11.313 0.018 ; - END - END w0_wd_in[278] - PIN w0_wd_in[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 11.799 0.000 11.817 0.018 ; - END - END w0_wd_in[279] - PIN w0_wd_in[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 12.303 0.000 12.321 0.018 ; - END - END w0_wd_in[280] - PIN w0_wd_in[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 12.807 0.000 12.825 0.018 ; - END - END w0_wd_in[281] - PIN w0_wd_in[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 13.311 0.000 13.329 0.018 ; - END - END w0_wd_in[282] - PIN w0_wd_in[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 13.815 0.000 13.833 0.018 ; - END - END w0_wd_in[283] - PIN w0_wd_in[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.319 0.000 14.337 0.018 ; - END - END w0_wd_in[284] - PIN w0_wd_in[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.823 0.000 14.841 0.018 ; - END - END w0_wd_in[285] - PIN w0_wd_in[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.327 0.000 15.345 0.018 ; - END - END w0_wd_in[286] - PIN w0_wd_in[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.831 0.000 15.849 0.018 ; - END - END w0_wd_in[287] - PIN w0_wd_in[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 16.335 0.000 16.353 0.018 ; - END - END w0_wd_in[288] - PIN w0_wd_in[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 16.839 0.000 16.857 0.018 ; - END - END w0_wd_in[289] - PIN w0_wd_in[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 17.343 0.000 17.361 0.018 ; - END - END w0_wd_in[290] - PIN w0_wd_in[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 17.847 0.000 17.865 0.018 ; - END - END w0_wd_in[291] - PIN w0_wd_in[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 18.351 0.000 18.369 0.018 ; - END - END w0_wd_in[292] - PIN w0_wd_in[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 18.855 0.000 18.873 0.018 ; - END - END w0_wd_in[293] - PIN w0_wd_in[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 19.359 0.000 19.377 0.018 ; - END - END w0_wd_in[294] - PIN w0_wd_in[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 19.863 0.000 19.881 0.018 ; - END - END w0_wd_in[295] - PIN w0_wd_in[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 20.367 0.000 20.385 0.018 ; - END - END w0_wd_in[296] - PIN w0_wd_in[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 20.871 0.000 20.889 0.018 ; - END - END w0_wd_in[297] - PIN w0_wd_in[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 21.375 0.000 21.393 0.018 ; - END - END w0_wd_in[298] - PIN w0_wd_in[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 21.879 0.000 21.897 0.018 ; - END - END w0_wd_in[299] - PIN w0_wd_in[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 22.383 0.000 22.401 0.018 ; - END - END w0_wd_in[300] - PIN w0_wd_in[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 22.887 0.000 22.905 0.018 ; - END - END w0_wd_in[301] - PIN w0_wd_in[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 23.391 0.000 23.409 0.018 ; - END - END w0_wd_in[302] - PIN w0_wd_in[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 23.895 0.000 23.913 0.018 ; - END - END w0_wd_in[303] - PIN w0_wd_in[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 24.399 0.000 24.417 0.018 ; - END - END w0_wd_in[304] - PIN w0_wd_in[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 24.903 0.000 24.921 0.018 ; - END - END w0_wd_in[305] - PIN w0_wd_in[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 25.407 0.000 25.425 0.018 ; - END - END w0_wd_in[306] - PIN w0_wd_in[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 25.911 0.000 25.929 0.018 ; - END - END w0_wd_in[307] - PIN w0_wd_in[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 26.415 0.000 26.433 0.018 ; - END - END w0_wd_in[308] - PIN w0_wd_in[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 26.919 0.000 26.937 0.018 ; - END - END w0_wd_in[309] - PIN w0_wd_in[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 27.423 0.000 27.441 0.018 ; - END - END w0_wd_in[310] - PIN w0_wd_in[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 27.927 0.000 27.945 0.018 ; - END - END w0_wd_in[311] - PIN w0_wd_in[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 28.431 0.000 28.449 0.018 ; - END - END w0_wd_in[312] - PIN w0_wd_in[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 28.935 0.000 28.953 0.018 ; - END - END w0_wd_in[313] - PIN w0_wd_in[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 29.439 0.000 29.457 0.018 ; - END - END w0_wd_in[314] - PIN w0_wd_in[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 29.943 0.000 29.961 0.018 ; - END - END w0_wd_in[315] - PIN w0_wd_in[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 30.447 0.000 30.465 0.018 ; - END - END w0_wd_in[316] - PIN w0_wd_in[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 30.951 0.000 30.969 0.018 ; - END - END w0_wd_in[317] - PIN w0_wd_in[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 31.455 0.000 31.473 0.018 ; - END - END w0_wd_in[318] - PIN w0_wd_in[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 31.959 0.000 31.977 0.018 ; - END - END w0_wd_in[319] - PIN w0_wd_in[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 32.463 0.000 32.481 0.018 ; - END - END w0_wd_in[320] - PIN w0_wd_in[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 32.967 0.000 32.985 0.018 ; - END - END w0_wd_in[321] - PIN w0_wd_in[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 33.471 0.000 33.489 0.018 ; - END - END w0_wd_in[322] - PIN w0_wd_in[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 33.975 0.000 33.993 0.018 ; - END - END w0_wd_in[323] - PIN w0_wd_in[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 34.479 0.000 34.497 0.018 ; - END - END w0_wd_in[324] - PIN w0_wd_in[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 34.983 0.000 35.001 0.018 ; - END - END w0_wd_in[325] - PIN w0_wd_in[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 35.487 0.000 35.505 0.018 ; - END - END w0_wd_in[326] - PIN w0_wd_in[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 35.991 0.000 36.009 0.018 ; - END - END w0_wd_in[327] - PIN w0_wd_in[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 36.495 0.000 36.513 0.018 ; - END - END w0_wd_in[328] - PIN w0_wd_in[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 36.999 0.000 37.017 0.018 ; - END - END w0_wd_in[329] - PIN w0_wd_in[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 37.503 0.000 37.521 0.018 ; - END - END w0_wd_in[330] - PIN w0_wd_in[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 38.007 0.000 38.025 0.018 ; - END - END w0_wd_in[331] - PIN w0_wd_in[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 38.511 0.000 38.529 0.018 ; - END - END w0_wd_in[332] - PIN w0_wd_in[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 39.015 0.000 39.033 0.018 ; - END - END w0_wd_in[333] - PIN w0_wd_in[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 39.519 0.000 39.537 0.018 ; - END - END w0_wd_in[334] - PIN w0_wd_in[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 40.023 0.000 40.041 0.018 ; - END - END w0_wd_in[335] - PIN w0_wd_in[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 40.527 0.000 40.545 0.018 ; - END - END w0_wd_in[336] - PIN w0_wd_in[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 41.031 0.000 41.049 0.018 ; - END - END w0_wd_in[337] - PIN w0_wd_in[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 41.535 0.000 41.553 0.018 ; - END - END w0_wd_in[338] - PIN w0_wd_in[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 42.039 0.000 42.057 0.018 ; - END - END w0_wd_in[339] - PIN w0_wd_in[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 42.543 0.000 42.561 0.018 ; - END - END w0_wd_in[340] - PIN w0_wd_in[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 43.047 0.000 43.065 0.018 ; - END - END w0_wd_in[341] - PIN w0_wd_in[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 43.551 0.000 43.569 0.018 ; - END - END w0_wd_in[342] - PIN w0_wd_in[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 44.055 0.000 44.073 0.018 ; - END - END w0_wd_in[343] - PIN w0_wd_in[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 44.559 0.000 44.577 0.018 ; - END - END w0_wd_in[344] - PIN w0_wd_in[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 45.063 0.000 45.081 0.018 ; - END - END w0_wd_in[345] - PIN w0_wd_in[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 45.567 0.000 45.585 0.018 ; - END - END w0_wd_in[346] - PIN w0_wd_in[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 46.071 0.000 46.089 0.018 ; - END - END w0_wd_in[347] - PIN w0_wd_in[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 46.575 0.000 46.593 0.018 ; - END - END w0_wd_in[348] - PIN w0_wd_in[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 47.079 0.000 47.097 0.018 ; - END - END w0_wd_in[349] - PIN w0_wd_in[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 47.583 0.000 47.601 0.018 ; - END - END w0_wd_in[350] - PIN w0_wd_in[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 48.087 0.000 48.105 0.018 ; - END - END w0_wd_in[351] - PIN w0_wd_in[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 48.591 0.000 48.609 0.018 ; - END - END w0_wd_in[352] - PIN w0_wd_in[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 49.095 0.000 49.113 0.018 ; - END - END w0_wd_in[353] - PIN w0_wd_in[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 49.599 0.000 49.617 0.018 ; - END - END w0_wd_in[354] - PIN w0_wd_in[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 50.103 0.000 50.121 0.018 ; - END - END w0_wd_in[355] - PIN w0_wd_in[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 50.607 0.000 50.625 0.018 ; - END - END w0_wd_in[356] - PIN w0_wd_in[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 51.111 0.000 51.129 0.018 ; - END - END w0_wd_in[357] - PIN w0_wd_in[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 51.615 0.000 51.633 0.018 ; - END - END w0_wd_in[358] - PIN w0_wd_in[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 52.119 0.000 52.137 0.018 ; - END - END w0_wd_in[359] - PIN w0_wd_in[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 52.623 0.000 52.641 0.018 ; - END - END w0_wd_in[360] - PIN w0_wd_in[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 53.127 0.000 53.145 0.018 ; - END - END w0_wd_in[361] - PIN w0_wd_in[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 53.631 0.000 53.649 0.018 ; - END - END w0_wd_in[362] - PIN w0_wd_in[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 54.135 0.000 54.153 0.018 ; - END - END w0_wd_in[363] - PIN w0_wd_in[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 54.639 0.000 54.657 0.018 ; - END - END w0_wd_in[364] - PIN w0_wd_in[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 55.143 0.000 55.161 0.018 ; - END - END w0_wd_in[365] - PIN w0_wd_in[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 55.647 0.000 55.665 0.018 ; - END - END w0_wd_in[366] - PIN w0_wd_in[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 56.151 0.000 56.169 0.018 ; - END - END w0_wd_in[367] - PIN w0_wd_in[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 56.655 0.000 56.673 0.018 ; - END - END w0_wd_in[368] - PIN w0_wd_in[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 57.159 0.000 57.177 0.018 ; - END - END w0_wd_in[369] - PIN w0_wd_in[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 57.663 0.000 57.681 0.018 ; - END - END w0_wd_in[370] - PIN w0_wd_in[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 58.167 0.000 58.185 0.018 ; - END - END w0_wd_in[371] - PIN w0_wd_in[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 58.671 0.000 58.689 0.018 ; - END - END w0_wd_in[372] - PIN w0_wd_in[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 59.175 0.000 59.193 0.018 ; - END - END w0_wd_in[373] - PIN w0_wd_in[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 59.679 0.000 59.697 0.018 ; - END - END w0_wd_in[374] - PIN w0_wd_in[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 60.183 0.000 60.201 0.018 ; - END - END w0_wd_in[375] - PIN w0_wd_in[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 60.687 0.000 60.705 0.018 ; - END - END w0_wd_in[376] - PIN w0_wd_in[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 61.191 0.000 61.209 0.018 ; - END - END w0_wd_in[377] - PIN w0_wd_in[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 61.695 0.000 61.713 0.018 ; - END - END w0_wd_in[378] - PIN w0_wd_in[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 62.199 0.000 62.217 0.018 ; - END - END w0_wd_in[379] - PIN w0_wd_in[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 62.703 0.000 62.721 0.018 ; - END - END w0_wd_in[380] - PIN w0_wd_in[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 63.207 0.000 63.225 0.018 ; - END - END w0_wd_in[381] - PIN w0_wd_in[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 63.711 0.000 63.729 0.018 ; - END - END w0_wd_in[382] - PIN w0_wd_in[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 64.215 0.000 64.233 0.018 ; - END - END w0_wd_in[383] - PIN w0_wd_in[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 64.719 0.000 64.737 0.018 ; - END - END w0_wd_in[384] - PIN w0_wd_in[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 65.223 0.000 65.241 0.018 ; - END - END w0_wd_in[385] - PIN w0_wd_in[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 65.727 0.000 65.745 0.018 ; - END - END w0_wd_in[386] - PIN w0_wd_in[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 66.231 0.000 66.249 0.018 ; - END - END w0_wd_in[387] - PIN w0_wd_in[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 66.735 0.000 66.753 0.018 ; - END - END w0_wd_in[388] - PIN w0_wd_in[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 67.239 0.000 67.257 0.018 ; - END - END w0_wd_in[389] - PIN w0_wd_in[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 67.743 0.000 67.761 0.018 ; - END - END w0_wd_in[390] - PIN w0_wd_in[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 68.247 0.000 68.265 0.018 ; - END - END w0_wd_in[391] - PIN w0_wd_in[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 68.751 0.000 68.769 0.018 ; - END - END w0_wd_in[392] - PIN w0_wd_in[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 69.255 0.000 69.273 0.018 ; - END - END w0_wd_in[393] - PIN w0_wd_in[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 69.759 0.000 69.777 0.018 ; - END - END w0_wd_in[394] - PIN w0_wd_in[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 70.263 0.000 70.281 0.018 ; - END - END w0_wd_in[395] - PIN w0_wd_in[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 70.767 0.000 70.785 0.018 ; - END - END w0_wd_in[396] - PIN w0_wd_in[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 71.271 0.000 71.289 0.018 ; - END - END w0_wd_in[397] - PIN w0_wd_in[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 71.775 0.000 71.793 0.018 ; - END - END w0_wd_in[398] - PIN w0_wd_in[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 72.279 0.000 72.297 0.018 ; - END - END w0_wd_in[399] - PIN w0_wd_in[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 72.783 0.000 72.801 0.018 ; - END - END w0_wd_in[400] - PIN w0_wd_in[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 73.287 0.000 73.305 0.018 ; - END - END w0_wd_in[401] - PIN w0_wd_in[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 73.791 0.000 73.809 0.018 ; - END - END w0_wd_in[402] - PIN w0_wd_in[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 74.295 0.000 74.313 0.018 ; - END - END w0_wd_in[403] - PIN w0_wd_in[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 74.799 0.000 74.817 0.018 ; - END - END w0_wd_in[404] - PIN w0_wd_in[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 75.303 0.000 75.321 0.018 ; - END - END w0_wd_in[405] - PIN w0_wd_in[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 75.807 0.000 75.825 0.018 ; - END - END w0_wd_in[406] - PIN w0_wd_in[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 76.311 0.000 76.329 0.018 ; - END - END w0_wd_in[407] - PIN w0_wd_in[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 76.815 0.000 76.833 0.018 ; - END - END w0_wd_in[408] - PIN w0_wd_in[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 77.319 0.000 77.337 0.018 ; - END - END w0_wd_in[409] - PIN w0_wd_in[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 77.823 0.000 77.841 0.018 ; - END - END w0_wd_in[410] - PIN w0_wd_in[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 78.327 0.000 78.345 0.018 ; - END - END w0_wd_in[411] - PIN w0_wd_in[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 78.831 0.000 78.849 0.018 ; - END - END w0_wd_in[412] - PIN w0_wd_in[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 79.335 0.000 79.353 0.018 ; - END - END w0_wd_in[413] - PIN w0_wd_in[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 79.839 0.000 79.857 0.018 ; - END - END w0_wd_in[414] - PIN w0_wd_in[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 80.343 0.000 80.361 0.018 ; - END - END w0_wd_in[415] - PIN w0_wd_in[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 80.847 0.000 80.865 0.018 ; - END - END w0_wd_in[416] - PIN w0_wd_in[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 81.351 0.000 81.369 0.018 ; - END - END w0_wd_in[417] - PIN w0_wd_in[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 81.855 0.000 81.873 0.018 ; - END - END w0_wd_in[418] - PIN w0_wd_in[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 82.359 0.000 82.377 0.018 ; - END - END w0_wd_in[419] - PIN w0_wd_in[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 82.863 0.000 82.881 0.018 ; - END - END w0_wd_in[420] - PIN w0_wd_in[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 83.367 0.000 83.385 0.018 ; - END - END w0_wd_in[421] - PIN w0_wd_in[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 83.871 0.000 83.889 0.018 ; - END - END w0_wd_in[422] - PIN w0_wd_in[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 84.375 0.000 84.393 0.018 ; - END - END w0_wd_in[423] - PIN w0_wd_in[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 84.879 0.000 84.897 0.018 ; - END - END w0_wd_in[424] - PIN w0_wd_in[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 85.383 0.000 85.401 0.018 ; - END - END w0_wd_in[425] - PIN w0_wd_in[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 85.887 0.000 85.905 0.018 ; - END - END w0_wd_in[426] - PIN w0_wd_in[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 86.391 0.000 86.409 0.018 ; - END - END w0_wd_in[427] - PIN w0_wd_in[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 86.895 0.000 86.913 0.018 ; - END - END w0_wd_in[428] - PIN w0_wd_in[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 87.399 0.000 87.417 0.018 ; - END - END w0_wd_in[429] - PIN w0_wd_in[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 87.903 0.000 87.921 0.018 ; - END - END w0_wd_in[430] - PIN w0_wd_in[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 88.407 0.000 88.425 0.018 ; - END - END w0_wd_in[431] - PIN w0_wd_in[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 88.911 0.000 88.929 0.018 ; - END - END w0_wd_in[432] - PIN w0_wd_in[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 89.415 0.000 89.433 0.018 ; - END - END w0_wd_in[433] - PIN w0_wd_in[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 89.919 0.000 89.937 0.018 ; - END - END w0_wd_in[434] - PIN w0_wd_in[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 90.423 0.000 90.441 0.018 ; - END - END w0_wd_in[435] - PIN w0_wd_in[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 90.927 0.000 90.945 0.018 ; - END - END w0_wd_in[436] - PIN w0_wd_in[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 91.431 0.000 91.449 0.018 ; - END - END w0_wd_in[437] - PIN w0_wd_in[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 91.935 0.000 91.953 0.018 ; - END - END w0_wd_in[438] - PIN w0_wd_in[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 92.439 0.000 92.457 0.018 ; - END - END w0_wd_in[439] - PIN w0_wd_in[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 92.943 0.000 92.961 0.018 ; - END - END w0_wd_in[440] - PIN w0_wd_in[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 93.447 0.000 93.465 0.018 ; - END - END w0_wd_in[441] - PIN w0_wd_in[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 93.951 0.000 93.969 0.018 ; - END - END w0_wd_in[442] - PIN w0_wd_in[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 94.455 0.000 94.473 0.018 ; - END - END w0_wd_in[443] - PIN w0_wd_in[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 94.959 0.000 94.977 0.018 ; - END - END w0_wd_in[444] - PIN w0_wd_in[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 95.463 0.000 95.481 0.018 ; - END - END w0_wd_in[445] - PIN w0_wd_in[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 95.967 0.000 95.985 0.018 ; - END - END w0_wd_in[446] - PIN w0_wd_in[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 96.471 0.000 96.489 0.018 ; - END - END w0_wd_in[447] - PIN w0_wd_in[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 96.975 0.000 96.993 0.018 ; - END - END w0_wd_in[448] - PIN w0_wd_in[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 97.479 0.000 97.497 0.018 ; - END - END w0_wd_in[449] - PIN w0_wd_in[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 97.983 0.000 98.001 0.018 ; - END - END w0_wd_in[450] - PIN w0_wd_in[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 98.487 0.000 98.505 0.018 ; - END - END w0_wd_in[451] - PIN w0_wd_in[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 98.991 0.000 99.009 0.018 ; - END - END w0_wd_in[452] - PIN w0_wd_in[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 99.495 0.000 99.513 0.018 ; - END - END w0_wd_in[453] - PIN w0_wd_in[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 99.999 0.000 100.017 0.018 ; - END - END w0_wd_in[454] - PIN w0_wd_in[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 100.503 0.000 100.521 0.018 ; - END - END w0_wd_in[455] - PIN w0_wd_in[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 101.007 0.000 101.025 0.018 ; - END - END w0_wd_in[456] - PIN w0_wd_in[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 101.511 0.000 101.529 0.018 ; - END - END w0_wd_in[457] - PIN w0_wd_in[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 102.015 0.000 102.033 0.018 ; - END - END w0_wd_in[458] - PIN w0_wd_in[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 102.519 0.000 102.537 0.018 ; - END - END w0_wd_in[459] - PIN w0_wd_in[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 103.023 0.000 103.041 0.018 ; - END - END w0_wd_in[460] - PIN w0_wd_in[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 103.527 0.000 103.545 0.018 ; - END - END w0_wd_in[461] - PIN w0_wd_in[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 104.031 0.000 104.049 0.018 ; - END - END w0_wd_in[462] - PIN w0_wd_in[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 104.535 0.000 104.553 0.018 ; - END - END w0_wd_in[463] - PIN w0_wd_in[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 105.039 0.000 105.057 0.018 ; - END - END w0_wd_in[464] - PIN w0_wd_in[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 105.543 0.000 105.561 0.018 ; - END - END w0_wd_in[465] - PIN w0_wd_in[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 106.047 0.000 106.065 0.018 ; - END - END w0_wd_in[466] - PIN w0_wd_in[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 106.551 0.000 106.569 0.018 ; - END - END w0_wd_in[467] - PIN w0_wd_in[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 107.055 0.000 107.073 0.018 ; - END - END w0_wd_in[468] - PIN w0_wd_in[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 107.559 0.000 107.577 0.018 ; - END - END w0_wd_in[469] - PIN w0_wd_in[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 108.063 0.000 108.081 0.018 ; - END - END w0_wd_in[470] - PIN w0_wd_in[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 108.567 0.000 108.585 0.018 ; - END - END w0_wd_in[471] - PIN w0_wd_in[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 109.071 0.000 109.089 0.018 ; - END - END w0_wd_in[472] - PIN w0_wd_in[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 109.575 0.000 109.593 0.018 ; - END - END w0_wd_in[473] - PIN w0_wd_in[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 110.079 0.000 110.097 0.018 ; - END - END w0_wd_in[474] - PIN w0_wd_in[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 110.583 0.000 110.601 0.018 ; - END - END w0_wd_in[475] - PIN w0_wd_in[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 111.087 0.000 111.105 0.018 ; - END - END w0_wd_in[476] - PIN w0_wd_in[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 111.591 0.000 111.609 0.018 ; - END - END w0_wd_in[477] - PIN w0_wd_in[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 112.095 0.000 112.113 0.018 ; - END - END w0_wd_in[478] - PIN w0_wd_in[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 112.599 0.000 112.617 0.018 ; - END - END w0_wd_in[479] - PIN w0_wd_in[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 113.103 0.000 113.121 0.018 ; - END - END w0_wd_in[480] - PIN w0_wd_in[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 113.607 0.000 113.625 0.018 ; - END - END w0_wd_in[481] - PIN w0_wd_in[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 114.111 0.000 114.129 0.018 ; - END - END w0_wd_in[482] - PIN w0_wd_in[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 114.615 0.000 114.633 0.018 ; - END - END w0_wd_in[483] - PIN w0_wd_in[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 115.119 0.000 115.137 0.018 ; - END - END w0_wd_in[484] - PIN w0_wd_in[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 115.623 0.000 115.641 0.018 ; - END - END w0_wd_in[485] - PIN w0_wd_in[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 116.127 0.000 116.145 0.018 ; - END - END w0_wd_in[486] - PIN w0_wd_in[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 116.631 0.000 116.649 0.018 ; - END - END w0_wd_in[487] - PIN w0_wd_in[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 117.135 0.000 117.153 0.018 ; - END - END w0_wd_in[488] - PIN w0_wd_in[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 117.639 0.000 117.657 0.018 ; - END - END w0_wd_in[489] - PIN w0_wd_in[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 118.143 0.000 118.161 0.018 ; - END - END w0_wd_in[490] - PIN w0_wd_in[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 118.647 0.000 118.665 0.018 ; - END - END w0_wd_in[491] - PIN w0_wd_in[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 119.151 0.000 119.169 0.018 ; - END - END w0_wd_in[492] - PIN w0_wd_in[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 119.655 0.000 119.673 0.018 ; - END - END w0_wd_in[493] - PIN w0_wd_in[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 120.159 0.000 120.177 0.018 ; - END - END w0_wd_in[494] - PIN w0_wd_in[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 120.663 0.000 120.681 0.018 ; - END - END w0_wd_in[495] - PIN w0_wd_in[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 121.167 0.000 121.185 0.018 ; - END - END w0_wd_in[496] - PIN w0_wd_in[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 121.671 0.000 121.689 0.018 ; - END - END w0_wd_in[497] - PIN w0_wd_in[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 122.175 0.000 122.193 0.018 ; - END - END w0_wd_in[498] - PIN w0_wd_in[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 122.679 0.000 122.697 0.018 ; - END - END w0_wd_in[499] - PIN w0_wd_in[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 123.183 0.000 123.201 0.018 ; - END - END w0_wd_in[500] - PIN w0_wd_in[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 123.687 0.000 123.705 0.018 ; - END - END w0_wd_in[501] - PIN w0_wd_in[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 124.191 0.000 124.209 0.018 ; - END - END w0_wd_in[502] - PIN w0_wd_in[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 124.695 0.000 124.713 0.018 ; - END - END w0_wd_in[503] - PIN w0_wd_in[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 125.199 0.000 125.217 0.018 ; - END - END w0_wd_in[504] - PIN w0_wd_in[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 125.703 0.000 125.721 0.018 ; - END - END w0_wd_in[505] - PIN w0_wd_in[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 126.207 0.000 126.225 0.018 ; - END - END w0_wd_in[506] - PIN w0_wd_in[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 126.711 0.000 126.729 0.018 ; - END - END w0_wd_in[507] - PIN w0_wd_in[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 127.215 0.000 127.233 0.018 ; - END - END w0_wd_in[508] - PIN w0_wd_in[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 127.719 0.000 127.737 0.018 ; - END - END w0_wd_in[509] - PIN w0_wd_in[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 128.223 0.000 128.241 0.018 ; - END - END w0_wd_in[510] - PIN w0_wd_in[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 128.727 0.000 128.745 0.018 ; - END - END w0_wd_in[511] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 129.231 0.000 129.249 0.018 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 129.735 0.000 129.753 0.018 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 130.239 0.000 130.257 0.018 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 130.743 0.000 130.761 0.018 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 131.247 0.000 131.265 0.018 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 131.751 0.000 131.769 0.018 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 132.255 0.000 132.273 0.018 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 132.759 0.000 132.777 0.018 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 133.263 0.000 133.281 0.018 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 133.767 0.000 133.785 0.018 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 134.271 0.000 134.289 0.018 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 134.775 0.000 134.793 0.018 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 135.279 0.000 135.297 0.018 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 135.783 0.000 135.801 0.018 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 136.287 0.000 136.305 0.018 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 136.791 0.000 136.809 0.018 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 137.295 0.000 137.313 0.018 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 137.799 0.000 137.817 0.018 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 138.303 0.000 138.321 0.018 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 138.807 0.000 138.825 0.018 ; - END - END r0_rd_out[19] - PIN r0_rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 139.311 0.000 139.329 0.018 ; - END - END r0_rd_out[20] - PIN r0_rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 139.815 0.000 139.833 0.018 ; - END - END r0_rd_out[21] - PIN r0_rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 140.319 0.000 140.337 0.018 ; - END - END r0_rd_out[22] - PIN r0_rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 140.823 0.000 140.841 0.018 ; - END - END r0_rd_out[23] - PIN r0_rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 141.327 0.000 141.345 0.018 ; - END - END r0_rd_out[24] - PIN r0_rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 141.831 0.000 141.849 0.018 ; - END - END r0_rd_out[25] - PIN r0_rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 142.335 0.000 142.353 0.018 ; - END - END r0_rd_out[26] - PIN r0_rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 142.839 0.000 142.857 0.018 ; - END - END r0_rd_out[27] - PIN r0_rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 143.343 0.000 143.361 0.018 ; - END - END r0_rd_out[28] - PIN r0_rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 143.847 0.000 143.865 0.018 ; - END - END r0_rd_out[29] - PIN r0_rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 144.351 0.000 144.369 0.018 ; - END - END r0_rd_out[30] - PIN r0_rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 144.855 0.000 144.873 0.018 ; - END - END r0_rd_out[31] - PIN r0_rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 145.359 0.000 145.377 0.018 ; - END - END r0_rd_out[32] - PIN r0_rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 145.863 0.000 145.881 0.018 ; - END - END r0_rd_out[33] - PIN r0_rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 146.367 0.000 146.385 0.018 ; - END - END r0_rd_out[34] - PIN r0_rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 146.871 0.000 146.889 0.018 ; - END - END r0_rd_out[35] - PIN r0_rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 147.375 0.000 147.393 0.018 ; - END - END r0_rd_out[36] - PIN r0_rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 147.879 0.000 147.897 0.018 ; - END - END r0_rd_out[37] - PIN r0_rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 148.383 0.000 148.401 0.018 ; - END - END r0_rd_out[38] - PIN r0_rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 148.887 0.000 148.905 0.018 ; - END - END r0_rd_out[39] - PIN r0_rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 149.391 0.000 149.409 0.018 ; - END - END r0_rd_out[40] - PIN r0_rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 149.895 0.000 149.913 0.018 ; - END - END r0_rd_out[41] - PIN r0_rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 150.399 0.000 150.417 0.018 ; - END - END r0_rd_out[42] - PIN r0_rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 150.903 0.000 150.921 0.018 ; - END - END r0_rd_out[43] - PIN r0_rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 151.407 0.000 151.425 0.018 ; - END - END r0_rd_out[44] - PIN r0_rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 151.911 0.000 151.929 0.018 ; - END - END r0_rd_out[45] - PIN r0_rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 152.415 0.000 152.433 0.018 ; - END - END r0_rd_out[46] - PIN r0_rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 152.919 0.000 152.937 0.018 ; - END - END r0_rd_out[47] - PIN r0_rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 153.423 0.000 153.441 0.018 ; - END - END r0_rd_out[48] - PIN r0_rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 153.927 0.000 153.945 0.018 ; - END - END r0_rd_out[49] - PIN r0_rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 154.431 0.000 154.449 0.018 ; - END - END r0_rd_out[50] - PIN r0_rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 154.935 0.000 154.953 0.018 ; - END - END r0_rd_out[51] - PIN r0_rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 155.439 0.000 155.457 0.018 ; - END - END r0_rd_out[52] - PIN r0_rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 155.943 0.000 155.961 0.018 ; - END - END r0_rd_out[53] - PIN r0_rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 156.447 0.000 156.465 0.018 ; - END - END r0_rd_out[54] - PIN r0_rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 156.951 0.000 156.969 0.018 ; - END - END r0_rd_out[55] - PIN r0_rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 157.455 0.000 157.473 0.018 ; - END - END r0_rd_out[56] - PIN r0_rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 157.959 0.000 157.977 0.018 ; - END - END r0_rd_out[57] - PIN r0_rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 158.463 0.000 158.481 0.018 ; - END - END r0_rd_out[58] - PIN r0_rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 158.967 0.000 158.985 0.018 ; - END - END r0_rd_out[59] - PIN r0_rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 159.471 0.000 159.489 0.018 ; - END - END r0_rd_out[60] - PIN r0_rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 159.975 0.000 159.993 0.018 ; - END - END r0_rd_out[61] - PIN r0_rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 160.479 0.000 160.497 0.018 ; - END - END r0_rd_out[62] - PIN r0_rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 160.983 0.000 161.001 0.018 ; - END - END r0_rd_out[63] - PIN r0_rd_out[64] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 161.487 0.000 161.505 0.018 ; - END - END r0_rd_out[64] - PIN r0_rd_out[65] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 161.991 0.000 162.009 0.018 ; - END - END r0_rd_out[65] - PIN r0_rd_out[66] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 162.495 0.000 162.513 0.018 ; - END - END r0_rd_out[66] - PIN r0_rd_out[67] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 162.999 0.000 163.017 0.018 ; - END - END r0_rd_out[67] - PIN r0_rd_out[68] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 163.503 0.000 163.521 0.018 ; - END - END r0_rd_out[68] - PIN r0_rd_out[69] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 164.007 0.000 164.025 0.018 ; - END - END r0_rd_out[69] - PIN r0_rd_out[70] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 164.511 0.000 164.529 0.018 ; - END - END r0_rd_out[70] - PIN r0_rd_out[71] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 165.015 0.000 165.033 0.018 ; - END - END r0_rd_out[71] - PIN r0_rd_out[72] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 165.519 0.000 165.537 0.018 ; - END - END r0_rd_out[72] - PIN r0_rd_out[73] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 166.023 0.000 166.041 0.018 ; - END - END r0_rd_out[73] - PIN r0_rd_out[74] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 166.527 0.000 166.545 0.018 ; - END - END r0_rd_out[74] - PIN r0_rd_out[75] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 167.031 0.000 167.049 0.018 ; - END - END r0_rd_out[75] - PIN r0_rd_out[76] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 167.535 0.000 167.553 0.018 ; - END - END r0_rd_out[76] - PIN r0_rd_out[77] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 168.039 0.000 168.057 0.018 ; - END - END r0_rd_out[77] - PIN r0_rd_out[78] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 168.543 0.000 168.561 0.018 ; - END - END r0_rd_out[78] - PIN r0_rd_out[79] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 169.047 0.000 169.065 0.018 ; - END - END r0_rd_out[79] - PIN r0_rd_out[80] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 169.551 0.000 169.569 0.018 ; - END - END r0_rd_out[80] - PIN r0_rd_out[81] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 170.055 0.000 170.073 0.018 ; - END - END r0_rd_out[81] - PIN r0_rd_out[82] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 170.559 0.000 170.577 0.018 ; - END - END r0_rd_out[82] - PIN r0_rd_out[83] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 171.063 0.000 171.081 0.018 ; - END - END r0_rd_out[83] - PIN r0_rd_out[84] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 171.567 0.000 171.585 0.018 ; - END - END r0_rd_out[84] - PIN r0_rd_out[85] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 172.071 0.000 172.089 0.018 ; - END - END r0_rd_out[85] - PIN r0_rd_out[86] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 172.575 0.000 172.593 0.018 ; - END - END r0_rd_out[86] - PIN r0_rd_out[87] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 173.079 0.000 173.097 0.018 ; - END - END r0_rd_out[87] - PIN r0_rd_out[88] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 173.583 0.000 173.601 0.018 ; - END - END r0_rd_out[88] - PIN r0_rd_out[89] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 174.087 0.000 174.105 0.018 ; - END - END r0_rd_out[89] - PIN r0_rd_out[90] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 174.591 0.000 174.609 0.018 ; - END - END r0_rd_out[90] - PIN r0_rd_out[91] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 175.095 0.000 175.113 0.018 ; - END - END r0_rd_out[91] - PIN r0_rd_out[92] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 175.599 0.000 175.617 0.018 ; - END - END r0_rd_out[92] - PIN r0_rd_out[93] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 176.103 0.000 176.121 0.018 ; - END - END r0_rd_out[93] - PIN r0_rd_out[94] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 176.607 0.000 176.625 0.018 ; - END - END r0_rd_out[94] - PIN r0_rd_out[95] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 177.111 0.000 177.129 0.018 ; - END - END r0_rd_out[95] - PIN r0_rd_out[96] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 177.615 0.000 177.633 0.018 ; - END - END r0_rd_out[96] - PIN r0_rd_out[97] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 178.119 0.000 178.137 0.018 ; - END - END r0_rd_out[97] - PIN r0_rd_out[98] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 178.623 0.000 178.641 0.018 ; - END - END r0_rd_out[98] - PIN r0_rd_out[99] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 179.127 0.000 179.145 0.018 ; - END - END r0_rd_out[99] - PIN r0_rd_out[100] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 179.631 0.000 179.649 0.018 ; - END - END r0_rd_out[100] - PIN r0_rd_out[101] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 180.135 0.000 180.153 0.018 ; - END - END r0_rd_out[101] - PIN r0_rd_out[102] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 180.639 0.000 180.657 0.018 ; - END - END r0_rd_out[102] - PIN r0_rd_out[103] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 181.143 0.000 181.161 0.018 ; - END - END r0_rd_out[103] - PIN r0_rd_out[104] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 181.647 0.000 181.665 0.018 ; - END - END r0_rd_out[104] - PIN r0_rd_out[105] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 182.151 0.000 182.169 0.018 ; - END - END r0_rd_out[105] - PIN r0_rd_out[106] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 182.655 0.000 182.673 0.018 ; - END - END r0_rd_out[106] - PIN r0_rd_out[107] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 183.159 0.000 183.177 0.018 ; - END - END r0_rd_out[107] - PIN r0_rd_out[108] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 183.663 0.000 183.681 0.018 ; - END - END r0_rd_out[108] - PIN r0_rd_out[109] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 184.167 0.000 184.185 0.018 ; - END - END r0_rd_out[109] - PIN r0_rd_out[110] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 184.671 0.000 184.689 0.018 ; - END - END r0_rd_out[110] - PIN r0_rd_out[111] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 185.175 0.000 185.193 0.018 ; - END - END r0_rd_out[111] - PIN r0_rd_out[112] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 185.679 0.000 185.697 0.018 ; - END - END r0_rd_out[112] - PIN r0_rd_out[113] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 186.183 0.000 186.201 0.018 ; - END - END r0_rd_out[113] - PIN r0_rd_out[114] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 186.687 0.000 186.705 0.018 ; - END - END r0_rd_out[114] - PIN r0_rd_out[115] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 187.191 0.000 187.209 0.018 ; - END - END r0_rd_out[115] - PIN r0_rd_out[116] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 187.695 0.000 187.713 0.018 ; - END - END r0_rd_out[116] - PIN r0_rd_out[117] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 188.199 0.000 188.217 0.018 ; - END - END r0_rd_out[117] - PIN r0_rd_out[118] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 188.703 0.000 188.721 0.018 ; - END - END r0_rd_out[118] - PIN r0_rd_out[119] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 189.207 0.000 189.225 0.018 ; - END - END r0_rd_out[119] - PIN r0_rd_out[120] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 189.711 0.000 189.729 0.018 ; - END - END r0_rd_out[120] - PIN r0_rd_out[121] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 190.215 0.000 190.233 0.018 ; - END - END r0_rd_out[121] - PIN r0_rd_out[122] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 190.719 0.000 190.737 0.018 ; - END - END r0_rd_out[122] - PIN r0_rd_out[123] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 191.223 0.000 191.241 0.018 ; - END - END r0_rd_out[123] - PIN r0_rd_out[124] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 191.727 0.000 191.745 0.018 ; - END - END r0_rd_out[124] - PIN r0_rd_out[125] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 192.231 0.000 192.249 0.018 ; - END - END r0_rd_out[125] - PIN r0_rd_out[126] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 192.735 0.000 192.753 0.018 ; - END - END r0_rd_out[126] - PIN r0_rd_out[127] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 193.239 0.000 193.257 0.018 ; - END - END r0_rd_out[127] - PIN r0_rd_out[128] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 193.743 0.000 193.761 0.018 ; - END - END r0_rd_out[128] - PIN r0_rd_out[129] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 194.247 0.000 194.265 0.018 ; - END - END r0_rd_out[129] - PIN r0_rd_out[130] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 194.751 0.000 194.769 0.018 ; - END - END r0_rd_out[130] - PIN r0_rd_out[131] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 195.255 0.000 195.273 0.018 ; - END - END r0_rd_out[131] - PIN r0_rd_out[132] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 195.759 0.000 195.777 0.018 ; - END - END r0_rd_out[132] - PIN r0_rd_out[133] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 196.263 0.000 196.281 0.018 ; - END - END r0_rd_out[133] - PIN r0_rd_out[134] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 196.767 0.000 196.785 0.018 ; - END - END r0_rd_out[134] - PIN r0_rd_out[135] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 197.271 0.000 197.289 0.018 ; - END - END r0_rd_out[135] - PIN r0_rd_out[136] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 197.775 0.000 197.793 0.018 ; - END - END r0_rd_out[136] - PIN r0_rd_out[137] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 198.279 0.000 198.297 0.018 ; - END - END r0_rd_out[137] - PIN r0_rd_out[138] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 198.783 0.000 198.801 0.018 ; - END - END r0_rd_out[138] - PIN r0_rd_out[139] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 199.287 0.000 199.305 0.018 ; - END - END r0_rd_out[139] - PIN r0_rd_out[140] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 199.791 0.000 199.809 0.018 ; - END - END r0_rd_out[140] - PIN r0_rd_out[141] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 200.295 0.000 200.313 0.018 ; - END - END r0_rd_out[141] - PIN r0_rd_out[142] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 200.799 0.000 200.817 0.018 ; - END - END r0_rd_out[142] - PIN r0_rd_out[143] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 201.303 0.000 201.321 0.018 ; - END - END r0_rd_out[143] - PIN r0_rd_out[144] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 201.807 0.000 201.825 0.018 ; - END - END r0_rd_out[144] - PIN r0_rd_out[145] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 202.311 0.000 202.329 0.018 ; - END - END r0_rd_out[145] - PIN r0_rd_out[146] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 202.815 0.000 202.833 0.018 ; - END - END r0_rd_out[146] - PIN r0_rd_out[147] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 203.319 0.000 203.337 0.018 ; - END - END r0_rd_out[147] - PIN r0_rd_out[148] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 203.823 0.000 203.841 0.018 ; - END - END r0_rd_out[148] - PIN r0_rd_out[149] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 204.327 0.000 204.345 0.018 ; - END - END r0_rd_out[149] - PIN r0_rd_out[150] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 204.831 0.000 204.849 0.018 ; - END - END r0_rd_out[150] - PIN r0_rd_out[151] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 205.335 0.000 205.353 0.018 ; - END - END r0_rd_out[151] - PIN r0_rd_out[152] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 205.839 0.000 205.857 0.018 ; - END - END r0_rd_out[152] - PIN r0_rd_out[153] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 206.343 0.000 206.361 0.018 ; - END - END r0_rd_out[153] - PIN r0_rd_out[154] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 206.847 0.000 206.865 0.018 ; - END - END r0_rd_out[154] - PIN r0_rd_out[155] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 207.351 0.000 207.369 0.018 ; - END - END r0_rd_out[155] - PIN r0_rd_out[156] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 207.855 0.000 207.873 0.018 ; - END - END r0_rd_out[156] - PIN r0_rd_out[157] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 208.359 0.000 208.377 0.018 ; - END - END r0_rd_out[157] - PIN r0_rd_out[158] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 208.863 0.000 208.881 0.018 ; - END - END r0_rd_out[158] - PIN r0_rd_out[159] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 209.367 0.000 209.385 0.018 ; - END - END r0_rd_out[159] - PIN r0_rd_out[160] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 209.871 0.000 209.889 0.018 ; - END - END r0_rd_out[160] - PIN r0_rd_out[161] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 210.375 0.000 210.393 0.018 ; - END - END r0_rd_out[161] - PIN r0_rd_out[162] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 210.879 0.000 210.897 0.018 ; - END - END r0_rd_out[162] - PIN r0_rd_out[163] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 211.383 0.000 211.401 0.018 ; - END - END r0_rd_out[163] - PIN r0_rd_out[164] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 211.887 0.000 211.905 0.018 ; - END - END r0_rd_out[164] - PIN r0_rd_out[165] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 212.391 0.000 212.409 0.018 ; - END - END r0_rd_out[165] - PIN r0_rd_out[166] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 212.895 0.000 212.913 0.018 ; - END - END r0_rd_out[166] - PIN r0_rd_out[167] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 213.399 0.000 213.417 0.018 ; - END - END r0_rd_out[167] - PIN r0_rd_out[168] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 213.903 0.000 213.921 0.018 ; - END - END r0_rd_out[168] - PIN r0_rd_out[169] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 214.407 0.000 214.425 0.018 ; - END - END r0_rd_out[169] - PIN r0_rd_out[170] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 214.911 0.000 214.929 0.018 ; - END - END r0_rd_out[170] - PIN r0_rd_out[171] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 215.415 0.000 215.433 0.018 ; - END - END r0_rd_out[171] - PIN r0_rd_out[172] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 215.919 0.000 215.937 0.018 ; - END - END r0_rd_out[172] - PIN r0_rd_out[173] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 216.423 0.000 216.441 0.018 ; - END - END r0_rd_out[173] - PIN r0_rd_out[174] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 216.927 0.000 216.945 0.018 ; - END - END r0_rd_out[174] - PIN r0_rd_out[175] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 217.431 0.000 217.449 0.018 ; - END - END r0_rd_out[175] - PIN r0_rd_out[176] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 217.935 0.000 217.953 0.018 ; - END - END r0_rd_out[176] - PIN r0_rd_out[177] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 218.439 0.000 218.457 0.018 ; - END - END r0_rd_out[177] - PIN r0_rd_out[178] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 218.943 0.000 218.961 0.018 ; - END - END r0_rd_out[178] - PIN r0_rd_out[179] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 219.447 0.000 219.465 0.018 ; - END - END r0_rd_out[179] - PIN r0_rd_out[180] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 219.951 0.000 219.969 0.018 ; - END - END r0_rd_out[180] - PIN r0_rd_out[181] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 220.455 0.000 220.473 0.018 ; - END - END r0_rd_out[181] - PIN r0_rd_out[182] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 220.959 0.000 220.977 0.018 ; - END - END r0_rd_out[182] - PIN r0_rd_out[183] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 221.463 0.000 221.481 0.018 ; - END - END r0_rd_out[183] - PIN r0_rd_out[184] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 221.967 0.000 221.985 0.018 ; - END - END r0_rd_out[184] - PIN r0_rd_out[185] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 222.471 0.000 222.489 0.018 ; - END - END r0_rd_out[185] - PIN r0_rd_out[186] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 222.975 0.000 222.993 0.018 ; - END - END r0_rd_out[186] - PIN r0_rd_out[187] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 223.479 0.000 223.497 0.018 ; - END - END r0_rd_out[187] - PIN r0_rd_out[188] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 223.983 0.000 224.001 0.018 ; - END - END r0_rd_out[188] - PIN r0_rd_out[189] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 224.487 0.000 224.505 0.018 ; - END - END r0_rd_out[189] - PIN r0_rd_out[190] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 224.991 0.000 225.009 0.018 ; - END - END r0_rd_out[190] - PIN r0_rd_out[191] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 225.495 0.000 225.513 0.018 ; - END - END r0_rd_out[191] - PIN r0_rd_out[192] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 225.999 0.000 226.017 0.018 ; - END - END r0_rd_out[192] - PIN r0_rd_out[193] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 226.503 0.000 226.521 0.018 ; - END - END r0_rd_out[193] - PIN r0_rd_out[194] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 227.007 0.000 227.025 0.018 ; - END - END r0_rd_out[194] - PIN r0_rd_out[195] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 227.511 0.000 227.529 0.018 ; - END - END r0_rd_out[195] - PIN r0_rd_out[196] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 228.015 0.000 228.033 0.018 ; - END - END r0_rd_out[196] - PIN r0_rd_out[197] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 228.519 0.000 228.537 0.018 ; - END - END r0_rd_out[197] - PIN r0_rd_out[198] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 229.023 0.000 229.041 0.018 ; - END - END r0_rd_out[198] - PIN r0_rd_out[199] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 229.527 0.000 229.545 0.018 ; - END - END r0_rd_out[199] - PIN r0_rd_out[200] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 230.031 0.000 230.049 0.018 ; - END - END r0_rd_out[200] - PIN r0_rd_out[201] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 230.535 0.000 230.553 0.018 ; - END - END r0_rd_out[201] - PIN r0_rd_out[202] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 231.039 0.000 231.057 0.018 ; - END - END r0_rd_out[202] - PIN r0_rd_out[203] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 231.543 0.000 231.561 0.018 ; - END - END r0_rd_out[203] - PIN r0_rd_out[204] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 232.047 0.000 232.065 0.018 ; - END - END r0_rd_out[204] - PIN r0_rd_out[205] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 232.551 0.000 232.569 0.018 ; - END - END r0_rd_out[205] - PIN r0_rd_out[206] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 233.055 0.000 233.073 0.018 ; - END - END r0_rd_out[206] - PIN r0_rd_out[207] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 233.559 0.000 233.577 0.018 ; - END - END r0_rd_out[207] - PIN r0_rd_out[208] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 234.063 0.000 234.081 0.018 ; - END - END r0_rd_out[208] - PIN r0_rd_out[209] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 234.567 0.000 234.585 0.018 ; - END - END r0_rd_out[209] - PIN r0_rd_out[210] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 235.071 0.000 235.089 0.018 ; - END - END r0_rd_out[210] - PIN r0_rd_out[211] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 235.575 0.000 235.593 0.018 ; - END - END r0_rd_out[211] - PIN r0_rd_out[212] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 236.079 0.000 236.097 0.018 ; - END - END r0_rd_out[212] - PIN r0_rd_out[213] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 236.583 0.000 236.601 0.018 ; - END - END r0_rd_out[213] - PIN r0_rd_out[214] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 237.087 0.000 237.105 0.018 ; - END - END r0_rd_out[214] - PIN r0_rd_out[215] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 237.591 0.000 237.609 0.018 ; - END - END r0_rd_out[215] - PIN r0_rd_out[216] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 238.095 0.000 238.113 0.018 ; - END - END r0_rd_out[216] - PIN r0_rd_out[217] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 238.599 0.000 238.617 0.018 ; - END - END r0_rd_out[217] - PIN r0_rd_out[218] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 239.103 0.000 239.121 0.018 ; - END - END r0_rd_out[218] - PIN r0_rd_out[219] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 239.607 0.000 239.625 0.018 ; - END - END r0_rd_out[219] - PIN r0_rd_out[220] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 240.111 0.000 240.129 0.018 ; - END - END r0_rd_out[220] - PIN r0_rd_out[221] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 240.615 0.000 240.633 0.018 ; - END - END r0_rd_out[221] - PIN r0_rd_out[222] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 241.119 0.000 241.137 0.018 ; - END - END r0_rd_out[222] - PIN r0_rd_out[223] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 241.623 0.000 241.641 0.018 ; - END - END r0_rd_out[223] - PIN r0_rd_out[224] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 242.127 0.000 242.145 0.018 ; - END - END r0_rd_out[224] - PIN r0_rd_out[225] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 242.631 0.000 242.649 0.018 ; - END - END r0_rd_out[225] - PIN r0_rd_out[226] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 243.135 0.000 243.153 0.018 ; - END - END r0_rd_out[226] - PIN r0_rd_out[227] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 243.639 0.000 243.657 0.018 ; - END - END r0_rd_out[227] - PIN r0_rd_out[228] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 244.143 0.000 244.161 0.018 ; - END - END r0_rd_out[228] - PIN r0_rd_out[229] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 244.647 0.000 244.665 0.018 ; - END - END r0_rd_out[229] - PIN r0_rd_out[230] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 245.151 0.000 245.169 0.018 ; - END - END r0_rd_out[230] - PIN r0_rd_out[231] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 245.655 0.000 245.673 0.018 ; - END - END r0_rd_out[231] - PIN r0_rd_out[232] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 246.159 0.000 246.177 0.018 ; - END - END r0_rd_out[232] - PIN r0_rd_out[233] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 246.663 0.000 246.681 0.018 ; - END - END r0_rd_out[233] - PIN r0_rd_out[234] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 247.167 0.000 247.185 0.018 ; - END - END r0_rd_out[234] - PIN r0_rd_out[235] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 247.671 0.000 247.689 0.018 ; - END - END r0_rd_out[235] - PIN r0_rd_out[236] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 248.175 0.000 248.193 0.018 ; - END - END r0_rd_out[236] - PIN r0_rd_out[237] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 248.679 0.000 248.697 0.018 ; - END - END r0_rd_out[237] - PIN r0_rd_out[238] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 249.183 0.000 249.201 0.018 ; - END - END r0_rd_out[238] - PIN r0_rd_out[239] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 249.687 0.000 249.705 0.018 ; - END - END r0_rd_out[239] - PIN r0_rd_out[240] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 250.191 0.000 250.209 0.018 ; - END - END r0_rd_out[240] - PIN r0_rd_out[241] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 250.695 0.000 250.713 0.018 ; - END - END r0_rd_out[241] - PIN r0_rd_out[242] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 251.199 0.000 251.217 0.018 ; - END - END r0_rd_out[242] - PIN r0_rd_out[243] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 251.703 0.000 251.721 0.018 ; - END - END r0_rd_out[243] - PIN r0_rd_out[244] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 252.207 0.000 252.225 0.018 ; - END - END r0_rd_out[244] - PIN r0_rd_out[245] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 252.711 0.000 252.729 0.018 ; - END - END r0_rd_out[245] - PIN r0_rd_out[246] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 253.215 0.000 253.233 0.018 ; - END - END r0_rd_out[246] - PIN r0_rd_out[247] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 253.719 0.000 253.737 0.018 ; - END - END r0_rd_out[247] - PIN r0_rd_out[248] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 254.223 0.000 254.241 0.018 ; - END - END r0_rd_out[248] - PIN r0_rd_out[249] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 254.727 0.000 254.745 0.018 ; - END - END r0_rd_out[249] - PIN r0_rd_out[250] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 255.231 0.000 255.249 0.018 ; - END - END r0_rd_out[250] - PIN r0_rd_out[251] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 255.735 0.000 255.753 0.018 ; - END - END r0_rd_out[251] - PIN r0_rd_out[252] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 256.239 0.000 256.257 0.018 ; - END - END r0_rd_out[252] - PIN r0_rd_out[253] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 256.743 0.000 256.761 0.018 ; - END - END r0_rd_out[253] - PIN r0_rd_out[254] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 257.247 0.000 257.265 0.018 ; - END - END r0_rd_out[254] - PIN r0_rd_out[255] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 257.751 0.000 257.769 0.018 ; - END - END r0_rd_out[255] - PIN r0_rd_out[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.207 165.870 0.225 165.888 ; - END - END r0_rd_out[256] - PIN r0_rd_out[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.215 165.870 1.233 165.888 ; - END - END r0_rd_out[257] - PIN r0_rd_out[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.223 165.870 2.241 165.888 ; - END - END r0_rd_out[258] - PIN r0_rd_out[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.231 165.870 3.249 165.888 ; - END - END r0_rd_out[259] - PIN r0_rd_out[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.239 165.870 4.257 165.888 ; - END - END r0_rd_out[260] - PIN r0_rd_out[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.247 165.870 5.265 165.888 ; - END - END r0_rd_out[261] - PIN r0_rd_out[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.255 165.870 6.273 165.888 ; - END - END r0_rd_out[262] - PIN r0_rd_out[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 7.263 165.870 7.281 165.888 ; - END - END r0_rd_out[263] - PIN r0_rd_out[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 8.271 165.870 8.289 165.888 ; - END - END r0_rd_out[264] - PIN r0_rd_out[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.279 165.870 9.297 165.888 ; - END - END r0_rd_out[265] - PIN r0_rd_out[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 10.287 165.870 10.305 165.888 ; - END - END r0_rd_out[266] - PIN r0_rd_out[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 11.295 165.870 11.313 165.888 ; - END - END r0_rd_out[267] - PIN r0_rd_out[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 12.303 165.870 12.321 165.888 ; - END - END r0_rd_out[268] - PIN r0_rd_out[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 13.311 165.870 13.329 165.888 ; - END - END r0_rd_out[269] - PIN r0_rd_out[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.319 165.870 14.337 165.888 ; - END - END r0_rd_out[270] - PIN r0_rd_out[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.327 165.870 15.345 165.888 ; - END - END r0_rd_out[271] - PIN r0_rd_out[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 16.335 165.870 16.353 165.888 ; - END - END r0_rd_out[272] - PIN r0_rd_out[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 17.343 165.870 17.361 165.888 ; - END - END r0_rd_out[273] - PIN r0_rd_out[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 18.351 165.870 18.369 165.888 ; - END - END r0_rd_out[274] - PIN r0_rd_out[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 19.359 165.870 19.377 165.888 ; - END - END r0_rd_out[275] - PIN r0_rd_out[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 20.367 165.870 20.385 165.888 ; - END - END r0_rd_out[276] - PIN r0_rd_out[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 21.375 165.870 21.393 165.888 ; - END - END r0_rd_out[277] - PIN r0_rd_out[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 22.383 165.870 22.401 165.888 ; - END - END r0_rd_out[278] - PIN r0_rd_out[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 23.391 165.870 23.409 165.888 ; - END - END r0_rd_out[279] - PIN r0_rd_out[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 24.399 165.870 24.417 165.888 ; - END - END r0_rd_out[280] - PIN r0_rd_out[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 25.407 165.870 25.425 165.888 ; - END - END r0_rd_out[281] - PIN r0_rd_out[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 26.415 165.870 26.433 165.888 ; - END - END r0_rd_out[282] - PIN r0_rd_out[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 27.423 165.870 27.441 165.888 ; - END - END r0_rd_out[283] - PIN r0_rd_out[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 28.431 165.870 28.449 165.888 ; - END - END r0_rd_out[284] - PIN r0_rd_out[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 29.439 165.870 29.457 165.888 ; - END - END r0_rd_out[285] - PIN r0_rd_out[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 30.447 165.870 30.465 165.888 ; - END - END r0_rd_out[286] - PIN r0_rd_out[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 31.455 165.870 31.473 165.888 ; - END - END r0_rd_out[287] - PIN r0_rd_out[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 32.463 165.870 32.481 165.888 ; - END - END r0_rd_out[288] - PIN r0_rd_out[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 33.471 165.870 33.489 165.888 ; - END - END r0_rd_out[289] - PIN r0_rd_out[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 34.479 165.870 34.497 165.888 ; - END - END r0_rd_out[290] - PIN r0_rd_out[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 35.487 165.870 35.505 165.888 ; - END - END r0_rd_out[291] - PIN r0_rd_out[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 36.495 165.870 36.513 165.888 ; - END - END r0_rd_out[292] - PIN r0_rd_out[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 37.503 165.870 37.521 165.888 ; - END - END r0_rd_out[293] - PIN r0_rd_out[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 38.511 165.870 38.529 165.888 ; - END - END r0_rd_out[294] - PIN r0_rd_out[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 39.519 165.870 39.537 165.888 ; - END - END r0_rd_out[295] - PIN r0_rd_out[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 40.527 165.870 40.545 165.888 ; - END - END r0_rd_out[296] - PIN r0_rd_out[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 41.535 165.870 41.553 165.888 ; - END - END r0_rd_out[297] - PIN r0_rd_out[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 42.543 165.870 42.561 165.888 ; - END - END r0_rd_out[298] - PIN r0_rd_out[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 43.551 165.870 43.569 165.888 ; - END - END r0_rd_out[299] - PIN r0_rd_out[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 44.559 165.870 44.577 165.888 ; - END - END r0_rd_out[300] - PIN r0_rd_out[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 45.567 165.870 45.585 165.888 ; - END - END r0_rd_out[301] - PIN r0_rd_out[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 46.575 165.870 46.593 165.888 ; - END - END r0_rd_out[302] - PIN r0_rd_out[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 47.583 165.870 47.601 165.888 ; - END - END r0_rd_out[303] - PIN r0_rd_out[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 48.591 165.870 48.609 165.888 ; - END - END r0_rd_out[304] - PIN r0_rd_out[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 49.599 165.870 49.617 165.888 ; - END - END r0_rd_out[305] - PIN r0_rd_out[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 50.607 165.870 50.625 165.888 ; - END - END r0_rd_out[306] - PIN r0_rd_out[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 51.615 165.870 51.633 165.888 ; - END - END r0_rd_out[307] - PIN r0_rd_out[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 52.623 165.870 52.641 165.888 ; - END - END r0_rd_out[308] - PIN r0_rd_out[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 53.631 165.870 53.649 165.888 ; - END - END r0_rd_out[309] - PIN r0_rd_out[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 54.639 165.870 54.657 165.888 ; - END - END r0_rd_out[310] - PIN r0_rd_out[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 55.647 165.870 55.665 165.888 ; - END - END r0_rd_out[311] - PIN r0_rd_out[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 56.655 165.870 56.673 165.888 ; - END - END r0_rd_out[312] - PIN r0_rd_out[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 57.663 165.870 57.681 165.888 ; - END - END r0_rd_out[313] - PIN r0_rd_out[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 58.671 165.870 58.689 165.888 ; - END - END r0_rd_out[314] - PIN r0_rd_out[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 59.679 165.870 59.697 165.888 ; - END - END r0_rd_out[315] - PIN r0_rd_out[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 60.687 165.870 60.705 165.888 ; - END - END r0_rd_out[316] - PIN r0_rd_out[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 61.695 165.870 61.713 165.888 ; - END - END r0_rd_out[317] - PIN r0_rd_out[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 62.703 165.870 62.721 165.888 ; - END - END r0_rd_out[318] - PIN r0_rd_out[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 63.711 165.870 63.729 165.888 ; - END - END r0_rd_out[319] - PIN r0_rd_out[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 64.719 165.870 64.737 165.888 ; - END - END r0_rd_out[320] - PIN r0_rd_out[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 65.727 165.870 65.745 165.888 ; - END - END r0_rd_out[321] - PIN r0_rd_out[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 66.735 165.870 66.753 165.888 ; - END - END r0_rd_out[322] - PIN r0_rd_out[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 67.743 165.870 67.761 165.888 ; - END - END r0_rd_out[323] - PIN r0_rd_out[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 68.751 165.870 68.769 165.888 ; - END - END r0_rd_out[324] - PIN r0_rd_out[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 69.759 165.870 69.777 165.888 ; - END - END r0_rd_out[325] - PIN r0_rd_out[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 70.767 165.870 70.785 165.888 ; - END - END r0_rd_out[326] - PIN r0_rd_out[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 71.775 165.870 71.793 165.888 ; - END - END r0_rd_out[327] - PIN r0_rd_out[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 72.783 165.870 72.801 165.888 ; - END - END r0_rd_out[328] - PIN r0_rd_out[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 73.791 165.870 73.809 165.888 ; - END - END r0_rd_out[329] - PIN r0_rd_out[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 74.799 165.870 74.817 165.888 ; - END - END r0_rd_out[330] - PIN r0_rd_out[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 75.807 165.870 75.825 165.888 ; - END - END r0_rd_out[331] - PIN r0_rd_out[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 76.815 165.870 76.833 165.888 ; - END - END r0_rd_out[332] - PIN r0_rd_out[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 77.823 165.870 77.841 165.888 ; - END - END r0_rd_out[333] - PIN r0_rd_out[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 78.831 165.870 78.849 165.888 ; - END - END r0_rd_out[334] - PIN r0_rd_out[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 79.839 165.870 79.857 165.888 ; - END - END r0_rd_out[335] - PIN r0_rd_out[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 80.847 165.870 80.865 165.888 ; - END - END r0_rd_out[336] - PIN r0_rd_out[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 81.855 165.870 81.873 165.888 ; - END - END r0_rd_out[337] - PIN r0_rd_out[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 82.863 165.870 82.881 165.888 ; - END - END r0_rd_out[338] - PIN r0_rd_out[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 83.871 165.870 83.889 165.888 ; - END - END r0_rd_out[339] - PIN r0_rd_out[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 84.879 165.870 84.897 165.888 ; - END - END r0_rd_out[340] - PIN r0_rd_out[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 85.887 165.870 85.905 165.888 ; - END - END r0_rd_out[341] - PIN r0_rd_out[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 86.895 165.870 86.913 165.888 ; - END - END r0_rd_out[342] - PIN r0_rd_out[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 87.903 165.870 87.921 165.888 ; - END - END r0_rd_out[343] - PIN r0_rd_out[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 88.911 165.870 88.929 165.888 ; - END - END r0_rd_out[344] - PIN r0_rd_out[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 89.919 165.870 89.937 165.888 ; - END - END r0_rd_out[345] - PIN r0_rd_out[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 90.927 165.870 90.945 165.888 ; - END - END r0_rd_out[346] - PIN r0_rd_out[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 91.935 165.870 91.953 165.888 ; - END - END r0_rd_out[347] - PIN r0_rd_out[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 92.943 165.870 92.961 165.888 ; - END - END r0_rd_out[348] - PIN r0_rd_out[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 93.951 165.870 93.969 165.888 ; - END - END r0_rd_out[349] - PIN r0_rd_out[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 94.959 165.870 94.977 165.888 ; - END - END r0_rd_out[350] - PIN r0_rd_out[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 95.967 165.870 95.985 165.888 ; - END - END r0_rd_out[351] - PIN r0_rd_out[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 96.975 165.870 96.993 165.888 ; - END - END r0_rd_out[352] - PIN r0_rd_out[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 97.983 165.870 98.001 165.888 ; - END - END r0_rd_out[353] - PIN r0_rd_out[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 98.991 165.870 99.009 165.888 ; - END - END r0_rd_out[354] - PIN r0_rd_out[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 99.999 165.870 100.017 165.888 ; - END - END r0_rd_out[355] - PIN r0_rd_out[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 101.007 165.870 101.025 165.888 ; - END - END r0_rd_out[356] - PIN r0_rd_out[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 102.015 165.870 102.033 165.888 ; - END - END r0_rd_out[357] - PIN r0_rd_out[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 103.023 165.870 103.041 165.888 ; - END - END r0_rd_out[358] - PIN r0_rd_out[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 104.031 165.870 104.049 165.888 ; - END - END r0_rd_out[359] - PIN r0_rd_out[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 105.039 165.870 105.057 165.888 ; - END - END r0_rd_out[360] - PIN r0_rd_out[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 106.047 165.870 106.065 165.888 ; - END - END r0_rd_out[361] - PIN r0_rd_out[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 107.055 165.870 107.073 165.888 ; - END - END r0_rd_out[362] - PIN r0_rd_out[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 108.063 165.870 108.081 165.888 ; - END - END r0_rd_out[363] - PIN r0_rd_out[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 109.071 165.870 109.089 165.888 ; - END - END r0_rd_out[364] - PIN r0_rd_out[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 110.079 165.870 110.097 165.888 ; - END - END r0_rd_out[365] - PIN r0_rd_out[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 111.087 165.870 111.105 165.888 ; - END - END r0_rd_out[366] - PIN r0_rd_out[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 112.095 165.870 112.113 165.888 ; - END - END r0_rd_out[367] - PIN r0_rd_out[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 113.103 165.870 113.121 165.888 ; - END - END r0_rd_out[368] - PIN r0_rd_out[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 114.111 165.870 114.129 165.888 ; - END - END r0_rd_out[369] - PIN r0_rd_out[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 115.119 165.870 115.137 165.888 ; - END - END r0_rd_out[370] - PIN r0_rd_out[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 116.127 165.870 116.145 165.888 ; - END - END r0_rd_out[371] - PIN r0_rd_out[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 117.135 165.870 117.153 165.888 ; - END - END r0_rd_out[372] - PIN r0_rd_out[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 118.143 165.870 118.161 165.888 ; - END - END r0_rd_out[373] - PIN r0_rd_out[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 119.151 165.870 119.169 165.888 ; - END - END r0_rd_out[374] - PIN r0_rd_out[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 120.159 165.870 120.177 165.888 ; - END - END r0_rd_out[375] - PIN r0_rd_out[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 121.167 165.870 121.185 165.888 ; - END - END r0_rd_out[376] - PIN r0_rd_out[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 122.175 165.870 122.193 165.888 ; - END - END r0_rd_out[377] - PIN r0_rd_out[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 123.183 165.870 123.201 165.888 ; - END - END r0_rd_out[378] - PIN r0_rd_out[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 124.191 165.870 124.209 165.888 ; - END - END r0_rd_out[379] - PIN r0_rd_out[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 125.199 165.870 125.217 165.888 ; - END - END r0_rd_out[380] - PIN r0_rd_out[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 126.207 165.870 126.225 165.888 ; - END - END r0_rd_out[381] - PIN r0_rd_out[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 127.215 165.870 127.233 165.888 ; - END - END r0_rd_out[382] - PIN r0_rd_out[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 128.223 165.870 128.241 165.888 ; - END - END r0_rd_out[383] - PIN r0_rd_out[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 129.231 165.870 129.249 165.888 ; - END - END r0_rd_out[384] - PIN r0_rd_out[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 130.239 165.870 130.257 165.888 ; - END - END r0_rd_out[385] - PIN r0_rd_out[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 131.247 165.870 131.265 165.888 ; - END - END r0_rd_out[386] - PIN r0_rd_out[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 132.255 165.870 132.273 165.888 ; - END - END r0_rd_out[387] - PIN r0_rd_out[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 133.263 165.870 133.281 165.888 ; - END - END r0_rd_out[388] - PIN r0_rd_out[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 134.271 165.870 134.289 165.888 ; - END - END r0_rd_out[389] - PIN r0_rd_out[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 135.279 165.870 135.297 165.888 ; - END - END r0_rd_out[390] - PIN r0_rd_out[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 136.287 165.870 136.305 165.888 ; - END - END r0_rd_out[391] - PIN r0_rd_out[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 137.295 165.870 137.313 165.888 ; - END - END r0_rd_out[392] - PIN r0_rd_out[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 138.303 165.870 138.321 165.888 ; - END - END r0_rd_out[393] - PIN r0_rd_out[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 139.311 165.870 139.329 165.888 ; - END - END r0_rd_out[394] - PIN r0_rd_out[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 140.319 165.870 140.337 165.888 ; - END - END r0_rd_out[395] - PIN r0_rd_out[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 141.327 165.870 141.345 165.888 ; - END - END r0_rd_out[396] - PIN r0_rd_out[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 142.335 165.870 142.353 165.888 ; - END - END r0_rd_out[397] - PIN r0_rd_out[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 143.343 165.870 143.361 165.888 ; - END - END r0_rd_out[398] - PIN r0_rd_out[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 144.351 165.870 144.369 165.888 ; - END - END r0_rd_out[399] - PIN r0_rd_out[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 145.359 165.870 145.377 165.888 ; - END - END r0_rd_out[400] - PIN r0_rd_out[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 146.367 165.870 146.385 165.888 ; - END - END r0_rd_out[401] - PIN r0_rd_out[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 147.375 165.870 147.393 165.888 ; - END - END r0_rd_out[402] - PIN r0_rd_out[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 148.383 165.870 148.401 165.888 ; - END - END r0_rd_out[403] - PIN r0_rd_out[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 149.391 165.870 149.409 165.888 ; - END - END r0_rd_out[404] - PIN r0_rd_out[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 150.399 165.870 150.417 165.888 ; - END - END r0_rd_out[405] - PIN r0_rd_out[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 151.407 165.870 151.425 165.888 ; - END - END r0_rd_out[406] - PIN r0_rd_out[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 152.415 165.870 152.433 165.888 ; - END - END r0_rd_out[407] - PIN r0_rd_out[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 153.423 165.870 153.441 165.888 ; - END - END r0_rd_out[408] - PIN r0_rd_out[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 154.431 165.870 154.449 165.888 ; - END - END r0_rd_out[409] - PIN r0_rd_out[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 155.439 165.870 155.457 165.888 ; - END - END r0_rd_out[410] - PIN r0_rd_out[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 156.447 165.870 156.465 165.888 ; - END - END r0_rd_out[411] - PIN r0_rd_out[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 157.455 165.870 157.473 165.888 ; - END - END r0_rd_out[412] - PIN r0_rd_out[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 158.463 165.870 158.481 165.888 ; - END - END r0_rd_out[413] - PIN r0_rd_out[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 159.471 165.870 159.489 165.888 ; - END - END r0_rd_out[414] - PIN r0_rd_out[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 160.479 165.870 160.497 165.888 ; - END - END r0_rd_out[415] - PIN r0_rd_out[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 161.487 165.870 161.505 165.888 ; - END - END r0_rd_out[416] - PIN r0_rd_out[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 162.495 165.870 162.513 165.888 ; - END - END r0_rd_out[417] - PIN r0_rd_out[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 163.503 165.870 163.521 165.888 ; - END - END r0_rd_out[418] - PIN r0_rd_out[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 164.511 165.870 164.529 165.888 ; - END - END r0_rd_out[419] - PIN r0_rd_out[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 165.519 165.870 165.537 165.888 ; - END - END r0_rd_out[420] - PIN r0_rd_out[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 166.527 165.870 166.545 165.888 ; - END - END r0_rd_out[421] - PIN r0_rd_out[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 167.535 165.870 167.553 165.888 ; - END - END r0_rd_out[422] - PIN r0_rd_out[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 168.543 165.870 168.561 165.888 ; - END - END r0_rd_out[423] - PIN r0_rd_out[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 169.551 165.870 169.569 165.888 ; - END - END r0_rd_out[424] - PIN r0_rd_out[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 170.559 165.870 170.577 165.888 ; - END - END r0_rd_out[425] - PIN r0_rd_out[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 171.567 165.870 171.585 165.888 ; - END - END r0_rd_out[426] - PIN r0_rd_out[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 172.575 165.870 172.593 165.888 ; - END - END r0_rd_out[427] - PIN r0_rd_out[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 173.583 165.870 173.601 165.888 ; - END - END r0_rd_out[428] - PIN r0_rd_out[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 174.591 165.870 174.609 165.888 ; - END - END r0_rd_out[429] - PIN r0_rd_out[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 175.599 165.870 175.617 165.888 ; - END - END r0_rd_out[430] - PIN r0_rd_out[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 176.607 165.870 176.625 165.888 ; - END - END r0_rd_out[431] - PIN r0_rd_out[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 177.615 165.870 177.633 165.888 ; - END - END r0_rd_out[432] - PIN r0_rd_out[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 178.623 165.870 178.641 165.888 ; - END - END r0_rd_out[433] - PIN r0_rd_out[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 179.631 165.870 179.649 165.888 ; - END - END r0_rd_out[434] - PIN r0_rd_out[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 180.639 165.870 180.657 165.888 ; - END - END r0_rd_out[435] - PIN r0_rd_out[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 181.647 165.870 181.665 165.888 ; - END - END r0_rd_out[436] - PIN r0_rd_out[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 182.655 165.870 182.673 165.888 ; - END - END r0_rd_out[437] - PIN r0_rd_out[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 183.663 165.870 183.681 165.888 ; - END - END r0_rd_out[438] - PIN r0_rd_out[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 184.671 165.870 184.689 165.888 ; - END - END r0_rd_out[439] - PIN r0_rd_out[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 185.679 165.870 185.697 165.888 ; - END - END r0_rd_out[440] - PIN r0_rd_out[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 186.687 165.870 186.705 165.888 ; - END - END r0_rd_out[441] - PIN r0_rd_out[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 187.695 165.870 187.713 165.888 ; - END - END r0_rd_out[442] - PIN r0_rd_out[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 188.703 165.870 188.721 165.888 ; - END - END r0_rd_out[443] - PIN r0_rd_out[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 189.711 165.870 189.729 165.888 ; - END - END r0_rd_out[444] - PIN r0_rd_out[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 190.719 165.870 190.737 165.888 ; - END - END r0_rd_out[445] - PIN r0_rd_out[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 191.727 165.870 191.745 165.888 ; - END - END r0_rd_out[446] - PIN r0_rd_out[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 192.735 165.870 192.753 165.888 ; - END - END r0_rd_out[447] - PIN r0_rd_out[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 193.743 165.870 193.761 165.888 ; - END - END r0_rd_out[448] - PIN r0_rd_out[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 194.751 165.870 194.769 165.888 ; - END - END r0_rd_out[449] - PIN r0_rd_out[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 195.759 165.870 195.777 165.888 ; - END - END r0_rd_out[450] - PIN r0_rd_out[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 196.767 165.870 196.785 165.888 ; - END - END r0_rd_out[451] - PIN r0_rd_out[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 197.775 165.870 197.793 165.888 ; - END - END r0_rd_out[452] - PIN r0_rd_out[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 198.783 165.870 198.801 165.888 ; - END - END r0_rd_out[453] - PIN r0_rd_out[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 199.791 165.870 199.809 165.888 ; - END - END r0_rd_out[454] - PIN r0_rd_out[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 200.799 165.870 200.817 165.888 ; - END - END r0_rd_out[455] - PIN r0_rd_out[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 201.807 165.870 201.825 165.888 ; - END - END r0_rd_out[456] - PIN r0_rd_out[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 202.815 165.870 202.833 165.888 ; - END - END r0_rd_out[457] - PIN r0_rd_out[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 203.823 165.870 203.841 165.888 ; - END - END r0_rd_out[458] - PIN r0_rd_out[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 204.831 165.870 204.849 165.888 ; - END - END r0_rd_out[459] - PIN r0_rd_out[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 205.839 165.870 205.857 165.888 ; - END - END r0_rd_out[460] - PIN r0_rd_out[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 206.847 165.870 206.865 165.888 ; - END - END r0_rd_out[461] - PIN r0_rd_out[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 207.855 165.870 207.873 165.888 ; - END - END r0_rd_out[462] - PIN r0_rd_out[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 208.863 165.870 208.881 165.888 ; - END - END r0_rd_out[463] - PIN r0_rd_out[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 209.871 165.870 209.889 165.888 ; - END - END r0_rd_out[464] - PIN r0_rd_out[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 210.879 165.870 210.897 165.888 ; - END - END r0_rd_out[465] - PIN r0_rd_out[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 211.887 165.870 211.905 165.888 ; - END - END r0_rd_out[466] - PIN r0_rd_out[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 212.895 165.870 212.913 165.888 ; - END - END r0_rd_out[467] - PIN r0_rd_out[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 213.903 165.870 213.921 165.888 ; - END - END r0_rd_out[468] - PIN r0_rd_out[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 214.911 165.870 214.929 165.888 ; - END - END r0_rd_out[469] - PIN r0_rd_out[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 215.919 165.870 215.937 165.888 ; - END - END r0_rd_out[470] - PIN r0_rd_out[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 216.927 165.870 216.945 165.888 ; - END - END r0_rd_out[471] - PIN r0_rd_out[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 217.935 165.870 217.953 165.888 ; - END - END r0_rd_out[472] - PIN r0_rd_out[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 218.943 165.870 218.961 165.888 ; - END - END r0_rd_out[473] - PIN r0_rd_out[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 219.951 165.870 219.969 165.888 ; - END - END r0_rd_out[474] - PIN r0_rd_out[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 220.959 165.870 220.977 165.888 ; - END - END r0_rd_out[475] - PIN r0_rd_out[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 221.967 165.870 221.985 165.888 ; - END - END r0_rd_out[476] - PIN r0_rd_out[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 222.975 165.870 222.993 165.888 ; - END - END r0_rd_out[477] - PIN r0_rd_out[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 223.983 165.870 224.001 165.888 ; - END - END r0_rd_out[478] - PIN r0_rd_out[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 224.991 165.870 225.009 165.888 ; - END - END r0_rd_out[479] - PIN r0_rd_out[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 225.999 165.870 226.017 165.888 ; - END - END r0_rd_out[480] - PIN r0_rd_out[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 227.007 165.870 227.025 165.888 ; - END - END r0_rd_out[481] - PIN r0_rd_out[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 228.015 165.870 228.033 165.888 ; - END - END r0_rd_out[482] - PIN r0_rd_out[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 229.023 165.870 229.041 165.888 ; - END - END r0_rd_out[483] - PIN r0_rd_out[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 230.031 165.870 230.049 165.888 ; - END - END r0_rd_out[484] - PIN r0_rd_out[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 231.039 165.870 231.057 165.888 ; - END - END r0_rd_out[485] - PIN r0_rd_out[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 232.047 165.870 232.065 165.888 ; - END - END r0_rd_out[486] - PIN r0_rd_out[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 233.055 165.870 233.073 165.888 ; - END - END r0_rd_out[487] - PIN r0_rd_out[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 234.063 165.870 234.081 165.888 ; - END - END r0_rd_out[488] - PIN r0_rd_out[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 235.071 165.870 235.089 165.888 ; - END - END r0_rd_out[489] - PIN r0_rd_out[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 236.079 165.870 236.097 165.888 ; - END - END r0_rd_out[490] - PIN r0_rd_out[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 237.087 165.870 237.105 165.888 ; - END - END r0_rd_out[491] - PIN r0_rd_out[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 238.095 165.870 238.113 165.888 ; - END - END r0_rd_out[492] - PIN r0_rd_out[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 239.103 165.870 239.121 165.888 ; - END - END r0_rd_out[493] - PIN r0_rd_out[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 240.111 165.870 240.129 165.888 ; - END - END r0_rd_out[494] - PIN r0_rd_out[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 241.119 165.870 241.137 165.888 ; - END - END r0_rd_out[495] - PIN r0_rd_out[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 242.127 165.870 242.145 165.888 ; - END - END r0_rd_out[496] - PIN r0_rd_out[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 243.135 165.870 243.153 165.888 ; - END - END r0_rd_out[497] - PIN r0_rd_out[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 244.143 165.870 244.161 165.888 ; - END - END r0_rd_out[498] - PIN r0_rd_out[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 245.151 165.870 245.169 165.888 ; - END - END r0_rd_out[499] - PIN r0_rd_out[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 246.159 165.870 246.177 165.888 ; - END - END r0_rd_out[500] - PIN r0_rd_out[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 247.167 165.870 247.185 165.888 ; - END - END r0_rd_out[501] - PIN r0_rd_out[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 248.175 165.870 248.193 165.888 ; - END - END r0_rd_out[502] - PIN r0_rd_out[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 249.183 165.870 249.201 165.888 ; - END - END r0_rd_out[503] - PIN r0_rd_out[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 250.191 165.870 250.209 165.888 ; - END - END r0_rd_out[504] - PIN r0_rd_out[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 251.199 165.870 251.217 165.888 ; - END - END r0_rd_out[505] - PIN r0_rd_out[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 252.207 165.870 252.225 165.888 ; - END - END r0_rd_out[506] - PIN r0_rd_out[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 253.215 165.870 253.233 165.888 ; - END - END r0_rd_out[507] - PIN r0_rd_out[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 254.223 165.870 254.241 165.888 ; - END - END r0_rd_out[508] - PIN r0_rd_out[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 255.231 165.870 255.249 165.888 ; - END - END r0_rd_out[509] - PIN r0_rd_out[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 256.239 165.870 256.257 165.888 ; - END - END r0_rd_out[510] - PIN r0_rd_out[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 257.247 165.870 257.265 165.888 ; - END - END r0_rd_out[511] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 147.732 0.024 147.756 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 148.884 0.024 148.908 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 150.036 0.024 150.060 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 151.188 0.024 151.212 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 152.340 0.024 152.364 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 153.492 0.024 153.516 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 147.732 265.421 147.756 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 148.884 265.421 148.908 ; - END - END w0_addr_in[7] - PIN w0_addr_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 150.036 265.421 150.060 ; - END - END w0_addr_in[8] - PIN w0_addr_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 151.188 265.421 151.212 ; - END - END w0_addr_in[9] - PIN w0_addr_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 152.340 265.421 152.364 ; - END - END w0_addr_in[10] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 154.644 0.024 154.668 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 155.796 0.024 155.820 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 156.948 0.024 156.972 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 158.100 0.024 158.124 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 159.252 0.024 159.276 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 160.404 0.024 160.428 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 153.492 265.421 153.516 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 154.644 265.421 154.668 ; - END - END r0_addr_in[7] - PIN r0_addr_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 155.796 265.421 155.820 ; - END - END r0_addr_in[8] - PIN r0_addr_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 156.948 265.421 156.972 ; - END - END r0_addr_in[9] - PIN r0_addr_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 158.100 265.421 158.124 ; - END - END r0_addr_in[10] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 258.255 165.870 258.273 165.888 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 259.263 165.870 259.281 165.888 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 260.271 165.870 260.289 165.888 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 261.279 165.870 261.297 165.888 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 262.287 165.870 262.305 165.888 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; - RECT 0.108 20.928 265.313 21.024 ; - RECT 0.108 21.696 265.313 21.792 ; - RECT 0.108 22.464 265.313 22.560 ; - RECT 0.108 23.232 265.313 23.328 ; - RECT 0.108 24.000 265.313 24.096 ; - RECT 0.108 24.768 265.313 24.864 ; - RECT 0.108 25.536 265.313 25.632 ; - RECT 0.108 26.304 265.313 26.400 ; - RECT 0.108 27.072 265.313 27.168 ; - RECT 0.108 27.840 265.313 27.936 ; - RECT 0.108 28.608 265.313 28.704 ; - RECT 0.108 29.376 265.313 29.472 ; - RECT 0.108 30.144 265.313 30.240 ; - RECT 0.108 30.912 265.313 31.008 ; - RECT 0.108 31.680 265.313 31.776 ; - RECT 0.108 32.448 265.313 32.544 ; - RECT 0.108 33.216 265.313 33.312 ; - RECT 0.108 33.984 265.313 34.080 ; - RECT 0.108 34.752 265.313 34.848 ; - RECT 0.108 35.520 265.313 35.616 ; - RECT 0.108 36.288 265.313 36.384 ; - RECT 0.108 37.056 265.313 37.152 ; - RECT 0.108 37.824 265.313 37.920 ; - RECT 0.108 38.592 265.313 38.688 ; - RECT 0.108 39.360 265.313 39.456 ; - RECT 0.108 40.128 265.313 40.224 ; - RECT 0.108 40.896 265.313 40.992 ; - RECT 0.108 41.664 265.313 41.760 ; - RECT 0.108 42.432 265.313 42.528 ; - RECT 0.108 43.200 265.313 43.296 ; - RECT 0.108 43.968 265.313 44.064 ; - RECT 0.108 44.736 265.313 44.832 ; - RECT 0.108 45.504 265.313 45.600 ; - RECT 0.108 46.272 265.313 46.368 ; - RECT 0.108 47.040 265.313 47.136 ; - RECT 0.108 47.808 265.313 47.904 ; - RECT 0.108 48.576 265.313 48.672 ; - RECT 0.108 49.344 265.313 49.440 ; - RECT 0.108 50.112 265.313 50.208 ; - RECT 0.108 50.880 265.313 50.976 ; - RECT 0.108 51.648 265.313 51.744 ; - RECT 0.108 52.416 265.313 52.512 ; - RECT 0.108 53.184 265.313 53.280 ; - RECT 0.108 53.952 265.313 54.048 ; - RECT 0.108 54.720 265.313 54.816 ; - RECT 0.108 55.488 265.313 55.584 ; - RECT 0.108 56.256 265.313 56.352 ; - RECT 0.108 57.024 265.313 57.120 ; - RECT 0.108 57.792 265.313 57.888 ; - RECT 0.108 58.560 265.313 58.656 ; - RECT 0.108 59.328 265.313 59.424 ; - RECT 0.108 60.096 265.313 60.192 ; - RECT 0.108 60.864 265.313 60.960 ; - RECT 0.108 61.632 265.313 61.728 ; - RECT 0.108 62.400 265.313 62.496 ; - RECT 0.108 63.168 265.313 63.264 ; - RECT 0.108 63.936 265.313 64.032 ; - RECT 0.108 64.704 265.313 64.800 ; - RECT 0.108 65.472 265.313 65.568 ; - RECT 0.108 66.240 265.313 66.336 ; - RECT 0.108 67.008 265.313 67.104 ; - RECT 0.108 67.776 265.313 67.872 ; - RECT 0.108 68.544 265.313 68.640 ; - RECT 0.108 69.312 265.313 69.408 ; - RECT 0.108 70.080 265.313 70.176 ; - RECT 0.108 70.848 265.313 70.944 ; - RECT 0.108 71.616 265.313 71.712 ; - RECT 0.108 72.384 265.313 72.480 ; - RECT 0.108 73.152 265.313 73.248 ; - RECT 0.108 73.920 265.313 74.016 ; - RECT 0.108 74.688 265.313 74.784 ; - RECT 0.108 75.456 265.313 75.552 ; - RECT 0.108 76.224 265.313 76.320 ; - RECT 0.108 76.992 265.313 77.088 ; - RECT 0.108 77.760 265.313 77.856 ; - RECT 0.108 78.528 265.313 78.624 ; - RECT 0.108 79.296 265.313 79.392 ; - RECT 0.108 80.064 265.313 80.160 ; - RECT 0.108 80.832 265.313 80.928 ; - RECT 0.108 81.600 265.313 81.696 ; - RECT 0.108 82.368 265.313 82.464 ; - RECT 0.108 83.136 265.313 83.232 ; - RECT 0.108 83.904 265.313 84.000 ; - RECT 0.108 84.672 265.313 84.768 ; - RECT 0.108 85.440 265.313 85.536 ; - RECT 0.108 86.208 265.313 86.304 ; - RECT 0.108 86.976 265.313 87.072 ; - RECT 0.108 87.744 265.313 87.840 ; - RECT 0.108 88.512 265.313 88.608 ; - RECT 0.108 89.280 265.313 89.376 ; - RECT 0.108 90.048 265.313 90.144 ; - RECT 0.108 90.816 265.313 90.912 ; - RECT 0.108 91.584 265.313 91.680 ; - RECT 0.108 92.352 265.313 92.448 ; - RECT 0.108 93.120 265.313 93.216 ; - RECT 0.108 93.888 265.313 93.984 ; - RECT 0.108 94.656 265.313 94.752 ; - RECT 0.108 95.424 265.313 95.520 ; - RECT 0.108 96.192 265.313 96.288 ; - RECT 0.108 96.960 265.313 97.056 ; - RECT 0.108 97.728 265.313 97.824 ; - RECT 0.108 98.496 265.313 98.592 ; - RECT 0.108 99.264 265.313 99.360 ; - RECT 0.108 100.032 265.313 100.128 ; - RECT 0.108 100.800 265.313 100.896 ; - RECT 0.108 101.568 265.313 101.664 ; - RECT 0.108 102.336 265.313 102.432 ; - RECT 0.108 103.104 265.313 103.200 ; - RECT 0.108 103.872 265.313 103.968 ; - RECT 0.108 104.640 265.313 104.736 ; - RECT 0.108 105.408 265.313 105.504 ; - RECT 0.108 106.176 265.313 106.272 ; - RECT 0.108 106.944 265.313 107.040 ; - RECT 0.108 107.712 265.313 107.808 ; - RECT 0.108 108.480 265.313 108.576 ; - RECT 0.108 109.248 265.313 109.344 ; - RECT 0.108 110.016 265.313 110.112 ; - RECT 0.108 110.784 265.313 110.880 ; - RECT 0.108 111.552 265.313 111.648 ; - RECT 0.108 112.320 265.313 112.416 ; - RECT 0.108 113.088 265.313 113.184 ; - RECT 0.108 113.856 265.313 113.952 ; - RECT 0.108 114.624 265.313 114.720 ; - RECT 0.108 115.392 265.313 115.488 ; - RECT 0.108 116.160 265.313 116.256 ; - RECT 0.108 116.928 265.313 117.024 ; - RECT 0.108 117.696 265.313 117.792 ; - RECT 0.108 118.464 265.313 118.560 ; - RECT 0.108 119.232 265.313 119.328 ; - RECT 0.108 120.000 265.313 120.096 ; - RECT 0.108 120.768 265.313 120.864 ; - RECT 0.108 121.536 265.313 121.632 ; - RECT 0.108 122.304 265.313 122.400 ; - RECT 0.108 123.072 265.313 123.168 ; - RECT 0.108 123.840 265.313 123.936 ; - RECT 0.108 124.608 265.313 124.704 ; - RECT 0.108 125.376 265.313 125.472 ; - RECT 0.108 126.144 265.313 126.240 ; - RECT 0.108 126.912 265.313 127.008 ; - RECT 0.108 127.680 265.313 127.776 ; - RECT 0.108 128.448 265.313 128.544 ; - RECT 0.108 129.216 265.313 129.312 ; - RECT 0.108 129.984 265.313 130.080 ; - RECT 0.108 130.752 265.313 130.848 ; - RECT 0.108 131.520 265.313 131.616 ; - RECT 0.108 132.288 265.313 132.384 ; - RECT 0.108 133.056 265.313 133.152 ; - RECT 0.108 133.824 265.313 133.920 ; - RECT 0.108 134.592 265.313 134.688 ; - RECT 0.108 135.360 265.313 135.456 ; - RECT 0.108 136.128 265.313 136.224 ; - RECT 0.108 136.896 265.313 136.992 ; - RECT 0.108 137.664 265.313 137.760 ; - RECT 0.108 138.432 265.313 138.528 ; - RECT 0.108 139.200 265.313 139.296 ; - RECT 0.108 139.968 265.313 140.064 ; - RECT 0.108 140.736 265.313 140.832 ; - RECT 0.108 141.504 265.313 141.600 ; - RECT 0.108 142.272 265.313 142.368 ; - RECT 0.108 143.040 265.313 143.136 ; - RECT 0.108 143.808 265.313 143.904 ; - RECT 0.108 144.576 265.313 144.672 ; - RECT 0.108 145.344 265.313 145.440 ; - RECT 0.108 146.112 265.313 146.208 ; - RECT 0.108 146.880 265.313 146.976 ; - RECT 0.108 147.648 265.313 147.744 ; - RECT 0.108 148.416 265.313 148.512 ; - RECT 0.108 149.184 265.313 149.280 ; - RECT 0.108 149.952 265.313 150.048 ; - RECT 0.108 150.720 265.313 150.816 ; - RECT 0.108 151.488 265.313 151.584 ; - RECT 0.108 152.256 265.313 152.352 ; - RECT 0.108 153.024 265.313 153.120 ; - RECT 0.108 153.792 265.313 153.888 ; - RECT 0.108 154.560 265.313 154.656 ; - RECT 0.108 155.328 265.313 155.424 ; - RECT 0.108 156.096 265.313 156.192 ; - RECT 0.108 156.864 265.313 156.960 ; - RECT 0.108 157.632 265.313 157.728 ; - RECT 0.108 158.400 265.313 158.496 ; - RECT 0.108 159.168 265.313 159.264 ; - RECT 0.108 159.936 265.313 160.032 ; - RECT 0.108 160.704 265.313 160.800 ; - RECT 0.108 161.472 265.313 161.568 ; - RECT 0.108 162.240 265.313 162.336 ; - RECT 0.108 163.008 265.313 163.104 ; - RECT 0.108 163.776 265.313 163.872 ; - RECT 0.108 164.544 265.313 164.640 ; - RECT 0.108 165.312 265.313 165.408 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; - RECT 0.108 20.928 265.313 21.024 ; - RECT 0.108 21.696 265.313 21.792 ; - RECT 0.108 22.464 265.313 22.560 ; - RECT 0.108 23.232 265.313 23.328 ; - RECT 0.108 24.000 265.313 24.096 ; - RECT 0.108 24.768 265.313 24.864 ; - RECT 0.108 25.536 265.313 25.632 ; - RECT 0.108 26.304 265.313 26.400 ; - RECT 0.108 27.072 265.313 27.168 ; - RECT 0.108 27.840 265.313 27.936 ; - RECT 0.108 28.608 265.313 28.704 ; - RECT 0.108 29.376 265.313 29.472 ; - RECT 0.108 30.144 265.313 30.240 ; - RECT 0.108 30.912 265.313 31.008 ; - RECT 0.108 31.680 265.313 31.776 ; - RECT 0.108 32.448 265.313 32.544 ; - RECT 0.108 33.216 265.313 33.312 ; - RECT 0.108 33.984 265.313 34.080 ; - RECT 0.108 34.752 265.313 34.848 ; - RECT 0.108 35.520 265.313 35.616 ; - RECT 0.108 36.288 265.313 36.384 ; - RECT 0.108 37.056 265.313 37.152 ; - RECT 0.108 37.824 265.313 37.920 ; - RECT 0.108 38.592 265.313 38.688 ; - RECT 0.108 39.360 265.313 39.456 ; - RECT 0.108 40.128 265.313 40.224 ; - RECT 0.108 40.896 265.313 40.992 ; - RECT 0.108 41.664 265.313 41.760 ; - RECT 0.108 42.432 265.313 42.528 ; - RECT 0.108 43.200 265.313 43.296 ; - RECT 0.108 43.968 265.313 44.064 ; - RECT 0.108 44.736 265.313 44.832 ; - RECT 0.108 45.504 265.313 45.600 ; - RECT 0.108 46.272 265.313 46.368 ; - RECT 0.108 47.040 265.313 47.136 ; - RECT 0.108 47.808 265.313 47.904 ; - RECT 0.108 48.576 265.313 48.672 ; - RECT 0.108 49.344 265.313 49.440 ; - RECT 0.108 50.112 265.313 50.208 ; - RECT 0.108 50.880 265.313 50.976 ; - RECT 0.108 51.648 265.313 51.744 ; - RECT 0.108 52.416 265.313 52.512 ; - RECT 0.108 53.184 265.313 53.280 ; - RECT 0.108 53.952 265.313 54.048 ; - RECT 0.108 54.720 265.313 54.816 ; - RECT 0.108 55.488 265.313 55.584 ; - RECT 0.108 56.256 265.313 56.352 ; - RECT 0.108 57.024 265.313 57.120 ; - RECT 0.108 57.792 265.313 57.888 ; - RECT 0.108 58.560 265.313 58.656 ; - RECT 0.108 59.328 265.313 59.424 ; - RECT 0.108 60.096 265.313 60.192 ; - RECT 0.108 60.864 265.313 60.960 ; - RECT 0.108 61.632 265.313 61.728 ; - RECT 0.108 62.400 265.313 62.496 ; - RECT 0.108 63.168 265.313 63.264 ; - RECT 0.108 63.936 265.313 64.032 ; - RECT 0.108 64.704 265.313 64.800 ; - RECT 0.108 65.472 265.313 65.568 ; - RECT 0.108 66.240 265.313 66.336 ; - RECT 0.108 67.008 265.313 67.104 ; - RECT 0.108 67.776 265.313 67.872 ; - RECT 0.108 68.544 265.313 68.640 ; - RECT 0.108 69.312 265.313 69.408 ; - RECT 0.108 70.080 265.313 70.176 ; - RECT 0.108 70.848 265.313 70.944 ; - RECT 0.108 71.616 265.313 71.712 ; - RECT 0.108 72.384 265.313 72.480 ; - RECT 0.108 73.152 265.313 73.248 ; - RECT 0.108 73.920 265.313 74.016 ; - RECT 0.108 74.688 265.313 74.784 ; - RECT 0.108 75.456 265.313 75.552 ; - RECT 0.108 76.224 265.313 76.320 ; - RECT 0.108 76.992 265.313 77.088 ; - RECT 0.108 77.760 265.313 77.856 ; - RECT 0.108 78.528 265.313 78.624 ; - RECT 0.108 79.296 265.313 79.392 ; - RECT 0.108 80.064 265.313 80.160 ; - RECT 0.108 80.832 265.313 80.928 ; - RECT 0.108 81.600 265.313 81.696 ; - RECT 0.108 82.368 265.313 82.464 ; - RECT 0.108 83.136 265.313 83.232 ; - RECT 0.108 83.904 265.313 84.000 ; - RECT 0.108 84.672 265.313 84.768 ; - RECT 0.108 85.440 265.313 85.536 ; - RECT 0.108 86.208 265.313 86.304 ; - RECT 0.108 86.976 265.313 87.072 ; - RECT 0.108 87.744 265.313 87.840 ; - RECT 0.108 88.512 265.313 88.608 ; - RECT 0.108 89.280 265.313 89.376 ; - RECT 0.108 90.048 265.313 90.144 ; - RECT 0.108 90.816 265.313 90.912 ; - RECT 0.108 91.584 265.313 91.680 ; - RECT 0.108 92.352 265.313 92.448 ; - RECT 0.108 93.120 265.313 93.216 ; - RECT 0.108 93.888 265.313 93.984 ; - RECT 0.108 94.656 265.313 94.752 ; - RECT 0.108 95.424 265.313 95.520 ; - RECT 0.108 96.192 265.313 96.288 ; - RECT 0.108 96.960 265.313 97.056 ; - RECT 0.108 97.728 265.313 97.824 ; - RECT 0.108 98.496 265.313 98.592 ; - RECT 0.108 99.264 265.313 99.360 ; - RECT 0.108 100.032 265.313 100.128 ; - RECT 0.108 100.800 265.313 100.896 ; - RECT 0.108 101.568 265.313 101.664 ; - RECT 0.108 102.336 265.313 102.432 ; - RECT 0.108 103.104 265.313 103.200 ; - RECT 0.108 103.872 265.313 103.968 ; - RECT 0.108 104.640 265.313 104.736 ; - RECT 0.108 105.408 265.313 105.504 ; - RECT 0.108 106.176 265.313 106.272 ; - RECT 0.108 106.944 265.313 107.040 ; - RECT 0.108 107.712 265.313 107.808 ; - RECT 0.108 108.480 265.313 108.576 ; - RECT 0.108 109.248 265.313 109.344 ; - RECT 0.108 110.016 265.313 110.112 ; - RECT 0.108 110.784 265.313 110.880 ; - RECT 0.108 111.552 265.313 111.648 ; - RECT 0.108 112.320 265.313 112.416 ; - RECT 0.108 113.088 265.313 113.184 ; - RECT 0.108 113.856 265.313 113.952 ; - RECT 0.108 114.624 265.313 114.720 ; - RECT 0.108 115.392 265.313 115.488 ; - RECT 0.108 116.160 265.313 116.256 ; - RECT 0.108 116.928 265.313 117.024 ; - RECT 0.108 117.696 265.313 117.792 ; - RECT 0.108 118.464 265.313 118.560 ; - RECT 0.108 119.232 265.313 119.328 ; - RECT 0.108 120.000 265.313 120.096 ; - RECT 0.108 120.768 265.313 120.864 ; - RECT 0.108 121.536 265.313 121.632 ; - RECT 0.108 122.304 265.313 122.400 ; - RECT 0.108 123.072 265.313 123.168 ; - RECT 0.108 123.840 265.313 123.936 ; - RECT 0.108 124.608 265.313 124.704 ; - RECT 0.108 125.376 265.313 125.472 ; - RECT 0.108 126.144 265.313 126.240 ; - RECT 0.108 126.912 265.313 127.008 ; - RECT 0.108 127.680 265.313 127.776 ; - RECT 0.108 128.448 265.313 128.544 ; - RECT 0.108 129.216 265.313 129.312 ; - RECT 0.108 129.984 265.313 130.080 ; - RECT 0.108 130.752 265.313 130.848 ; - RECT 0.108 131.520 265.313 131.616 ; - RECT 0.108 132.288 265.313 132.384 ; - RECT 0.108 133.056 265.313 133.152 ; - RECT 0.108 133.824 265.313 133.920 ; - RECT 0.108 134.592 265.313 134.688 ; - RECT 0.108 135.360 265.313 135.456 ; - RECT 0.108 136.128 265.313 136.224 ; - RECT 0.108 136.896 265.313 136.992 ; - RECT 0.108 137.664 265.313 137.760 ; - RECT 0.108 138.432 265.313 138.528 ; - RECT 0.108 139.200 265.313 139.296 ; - RECT 0.108 139.968 265.313 140.064 ; - RECT 0.108 140.736 265.313 140.832 ; - RECT 0.108 141.504 265.313 141.600 ; - RECT 0.108 142.272 265.313 142.368 ; - RECT 0.108 143.040 265.313 143.136 ; - RECT 0.108 143.808 265.313 143.904 ; - RECT 0.108 144.576 265.313 144.672 ; - RECT 0.108 145.344 265.313 145.440 ; - RECT 0.108 146.112 265.313 146.208 ; - RECT 0.108 146.880 265.313 146.976 ; - RECT 0.108 147.648 265.313 147.744 ; - RECT 0.108 148.416 265.313 148.512 ; - RECT 0.108 149.184 265.313 149.280 ; - RECT 0.108 149.952 265.313 150.048 ; - RECT 0.108 150.720 265.313 150.816 ; - RECT 0.108 151.488 265.313 151.584 ; - RECT 0.108 152.256 265.313 152.352 ; - RECT 0.108 153.024 265.313 153.120 ; - RECT 0.108 153.792 265.313 153.888 ; - RECT 0.108 154.560 265.313 154.656 ; - RECT 0.108 155.328 265.313 155.424 ; - RECT 0.108 156.096 265.313 156.192 ; - RECT 0.108 156.864 265.313 156.960 ; - RECT 0.108 157.632 265.313 157.728 ; - RECT 0.108 158.400 265.313 158.496 ; - RECT 0.108 159.168 265.313 159.264 ; - RECT 0.108 159.936 265.313 160.032 ; - RECT 0.108 160.704 265.313 160.800 ; - RECT 0.108 161.472 265.313 161.568 ; - RECT 0.108 162.240 265.313 162.336 ; - RECT 0.108 163.008 265.313 163.104 ; - RECT 0.108 163.776 265.313 163.872 ; - RECT 0.108 164.544 265.313 164.640 ; - RECT 0.108 165.312 265.313 165.408 ; - END - END VDD - OBS - LAYER M1 ; - RECT 0 0 265.421 165.888 ; - LAYER M2 ; - RECT 0 0 265.421 165.888 ; - LAYER M3 ; - RECT 0 0 265.421 165.888 ; - LAYER M4 ; - RECT 0 0 265.421 165.888 ; - END -END fakeram_512x2048_1r1w - -END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef b/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef deleted file mode 100644 index 93f4233..0000000 --- a/designs/asap7/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef +++ /dev/null @@ -1,9493 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_512x256_1r1w - FOREIGN fakeram_512x256_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 265.421 BY 20.736 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.276 0.024 0.300 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.420 0.024 0.444 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.564 0.024 0.588 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.708 0.024 0.732 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.852 0.024 0.876 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 0.996 0.024 1.020 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.140 0.024 1.164 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.284 0.024 1.308 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.428 0.024 1.452 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.572 0.024 1.596 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.716 0.024 1.740 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 1.860 0.024 1.884 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.004 0.024 2.028 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.148 0.024 2.172 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.292 0.024 2.316 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.436 0.024 2.460 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.580 0.024 2.604 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.724 0.024 2.748 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 2.868 0.024 2.892 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.012 0.024 3.036 ; - END - END w0_wd_in[19] - PIN w0_wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.156 0.024 3.180 ; - END - END w0_wd_in[20] - PIN w0_wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.300 0.024 3.324 ; - END - END w0_wd_in[21] - PIN w0_wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.444 0.024 3.468 ; - END - END w0_wd_in[22] - PIN w0_wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.588 0.024 3.612 ; - END - END w0_wd_in[23] - PIN w0_wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.732 0.024 3.756 ; - END - END w0_wd_in[24] - PIN w0_wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 3.876 0.024 3.900 ; - END - END w0_wd_in[25] - PIN w0_wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.020 0.024 4.044 ; - END - END w0_wd_in[26] - PIN w0_wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.164 0.024 4.188 ; - END - END w0_wd_in[27] - PIN w0_wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.308 0.024 4.332 ; - END - END w0_wd_in[28] - PIN w0_wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.452 0.024 4.476 ; - END - END w0_wd_in[29] - PIN w0_wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.596 0.024 4.620 ; - END - END w0_wd_in[30] - PIN w0_wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.740 0.024 4.764 ; - END - END w0_wd_in[31] - PIN w0_wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 4.884 0.024 4.908 ; - END - END w0_wd_in[32] - PIN w0_wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.028 0.024 5.052 ; - END - END w0_wd_in[33] - PIN w0_wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.172 0.024 5.196 ; - END - END w0_wd_in[34] - PIN w0_wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.316 0.024 5.340 ; - END - END w0_wd_in[35] - PIN w0_wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.460 0.024 5.484 ; - END - END w0_wd_in[36] - PIN w0_wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.604 0.024 5.628 ; - END - END w0_wd_in[37] - PIN w0_wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.748 0.024 5.772 ; - END - END w0_wd_in[38] - PIN w0_wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 5.892 0.024 5.916 ; - END - END w0_wd_in[39] - PIN w0_wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.036 0.024 6.060 ; - END - END w0_wd_in[40] - PIN w0_wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.180 0.024 6.204 ; - END - END w0_wd_in[41] - PIN w0_wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.324 0.024 6.348 ; - END - END w0_wd_in[42] - PIN w0_wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.468 0.024 6.492 ; - END - END w0_wd_in[43] - PIN w0_wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.612 0.024 6.636 ; - END - END w0_wd_in[44] - PIN w0_wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.756 0.024 6.780 ; - END - END w0_wd_in[45] - PIN w0_wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 6.900 0.024 6.924 ; - END - END w0_wd_in[46] - PIN w0_wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.044 0.024 7.068 ; - END - END w0_wd_in[47] - PIN w0_wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.188 0.024 7.212 ; - END - END w0_wd_in[48] - PIN w0_wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.332 0.024 7.356 ; - END - END w0_wd_in[49] - PIN w0_wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.476 0.024 7.500 ; - END - END w0_wd_in[50] - PIN w0_wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.620 0.024 7.644 ; - END - END w0_wd_in[51] - PIN w0_wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.764 0.024 7.788 ; - END - END w0_wd_in[52] - PIN w0_wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 7.908 0.024 7.932 ; - END - END w0_wd_in[53] - PIN w0_wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.052 0.024 8.076 ; - END - END w0_wd_in[54] - PIN w0_wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.196 0.024 8.220 ; - END - END w0_wd_in[55] - PIN w0_wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.340 0.024 8.364 ; - END - END w0_wd_in[56] - PIN w0_wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.484 0.024 8.508 ; - END - END w0_wd_in[57] - PIN w0_wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.628 0.024 8.652 ; - END - END w0_wd_in[58] - PIN w0_wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.772 0.024 8.796 ; - END - END w0_wd_in[59] - PIN w0_wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 8.916 0.024 8.940 ; - END - END w0_wd_in[60] - PIN w0_wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.060 0.024 9.084 ; - END - END w0_wd_in[61] - PIN w0_wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.204 0.024 9.228 ; - END - END w0_wd_in[62] - PIN w0_wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.348 0.024 9.372 ; - END - END w0_wd_in[63] - PIN w0_wd_in[64] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.492 0.024 9.516 ; - END - END w0_wd_in[64] - PIN w0_wd_in[65] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.636 0.024 9.660 ; - END - END w0_wd_in[65] - PIN w0_wd_in[66] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.780 0.024 9.804 ; - END - END w0_wd_in[66] - PIN w0_wd_in[67] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 9.924 0.024 9.948 ; - END - END w0_wd_in[67] - PIN w0_wd_in[68] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.068 0.024 10.092 ; - END - END w0_wd_in[68] - PIN w0_wd_in[69] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.212 0.024 10.236 ; - END - END w0_wd_in[69] - PIN w0_wd_in[70] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.356 0.024 10.380 ; - END - END w0_wd_in[70] - PIN w0_wd_in[71] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.500 0.024 10.524 ; - END - END w0_wd_in[71] - PIN w0_wd_in[72] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.644 0.024 10.668 ; - END - END w0_wd_in[72] - PIN w0_wd_in[73] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.788 0.024 10.812 ; - END - END w0_wd_in[73] - PIN w0_wd_in[74] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 10.932 0.024 10.956 ; - END - END w0_wd_in[74] - PIN w0_wd_in[75] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.076 0.024 11.100 ; - END - END w0_wd_in[75] - PIN w0_wd_in[76] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.220 0.024 11.244 ; - END - END w0_wd_in[76] - PIN w0_wd_in[77] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.364 0.024 11.388 ; - END - END w0_wd_in[77] - PIN w0_wd_in[78] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.508 0.024 11.532 ; - END - END w0_wd_in[78] - PIN w0_wd_in[79] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.652 0.024 11.676 ; - END - END w0_wd_in[79] - PIN w0_wd_in[80] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.796 0.024 11.820 ; - END - END w0_wd_in[80] - PIN w0_wd_in[81] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 11.940 0.024 11.964 ; - END - END w0_wd_in[81] - PIN w0_wd_in[82] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.084 0.024 12.108 ; - END - END w0_wd_in[82] - PIN w0_wd_in[83] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.228 0.024 12.252 ; - END - END w0_wd_in[83] - PIN w0_wd_in[84] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.372 0.024 12.396 ; - END - END w0_wd_in[84] - PIN w0_wd_in[85] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.516 0.024 12.540 ; - END - END w0_wd_in[85] - PIN w0_wd_in[86] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.660 0.024 12.684 ; - END - END w0_wd_in[86] - PIN w0_wd_in[87] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.804 0.024 12.828 ; - END - END w0_wd_in[87] - PIN w0_wd_in[88] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 12.948 0.024 12.972 ; - END - END w0_wd_in[88] - PIN w0_wd_in[89] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.092 0.024 13.116 ; - END - END w0_wd_in[89] - PIN w0_wd_in[90] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.236 0.024 13.260 ; - END - END w0_wd_in[90] - PIN w0_wd_in[91] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.380 0.024 13.404 ; - END - END w0_wd_in[91] - PIN w0_wd_in[92] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.524 0.024 13.548 ; - END - END w0_wd_in[92] - PIN w0_wd_in[93] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.668 0.024 13.692 ; - END - END w0_wd_in[93] - PIN w0_wd_in[94] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.812 0.024 13.836 ; - END - END w0_wd_in[94] - PIN w0_wd_in[95] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 13.956 0.024 13.980 ; - END - END w0_wd_in[95] - PIN w0_wd_in[96] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.100 0.024 14.124 ; - END - END w0_wd_in[96] - PIN w0_wd_in[97] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.244 0.024 14.268 ; - END - END w0_wd_in[97] - PIN w0_wd_in[98] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.388 0.024 14.412 ; - END - END w0_wd_in[98] - PIN w0_wd_in[99] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.532 0.024 14.556 ; - END - END w0_wd_in[99] - PIN w0_wd_in[100] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.676 0.024 14.700 ; - END - END w0_wd_in[100] - PIN w0_wd_in[101] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.820 0.024 14.844 ; - END - END w0_wd_in[101] - PIN w0_wd_in[102] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 14.964 0.024 14.988 ; - END - END w0_wd_in[102] - PIN w0_wd_in[103] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.108 0.024 15.132 ; - END - END w0_wd_in[103] - PIN w0_wd_in[104] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.252 0.024 15.276 ; - END - END w0_wd_in[104] - PIN w0_wd_in[105] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.396 0.024 15.420 ; - END - END w0_wd_in[105] - PIN w0_wd_in[106] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.540 0.024 15.564 ; - END - END w0_wd_in[106] - PIN w0_wd_in[107] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.684 0.024 15.708 ; - END - END w0_wd_in[107] - PIN w0_wd_in[108] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.828 0.024 15.852 ; - END - END w0_wd_in[108] - PIN w0_wd_in[109] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 15.972 0.024 15.996 ; - END - END w0_wd_in[109] - PIN w0_wd_in[110] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.116 0.024 16.140 ; - END - END w0_wd_in[110] - PIN w0_wd_in[111] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.260 0.024 16.284 ; - END - END w0_wd_in[111] - PIN w0_wd_in[112] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.404 0.024 16.428 ; - END - END w0_wd_in[112] - PIN w0_wd_in[113] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.548 0.024 16.572 ; - END - END w0_wd_in[113] - PIN w0_wd_in[114] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.692 0.024 16.716 ; - END - END w0_wd_in[114] - PIN w0_wd_in[115] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.836 0.024 16.860 ; - END - END w0_wd_in[115] - PIN w0_wd_in[116] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 16.980 0.024 17.004 ; - END - END w0_wd_in[116] - PIN w0_wd_in[117] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.124 0.024 17.148 ; - END - END w0_wd_in[117] - PIN w0_wd_in[118] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.268 0.024 17.292 ; - END - END w0_wd_in[118] - PIN w0_wd_in[119] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.412 0.024 17.436 ; - END - END w0_wd_in[119] - PIN w0_wd_in[120] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.556 0.024 17.580 ; - END - END w0_wd_in[120] - PIN w0_wd_in[121] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.700 0.024 17.724 ; - END - END w0_wd_in[121] - PIN w0_wd_in[122] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.844 0.024 17.868 ; - END - END w0_wd_in[122] - PIN w0_wd_in[123] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 17.988 0.024 18.012 ; - END - END w0_wd_in[123] - PIN w0_wd_in[124] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.132 0.024 18.156 ; - END - END w0_wd_in[124] - PIN w0_wd_in[125] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.276 0.024 18.300 ; - END - END w0_wd_in[125] - PIN w0_wd_in[126] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.420 0.024 18.444 ; - END - END w0_wd_in[126] - PIN w0_wd_in[127] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.564 0.024 18.588 ; - END - END w0_wd_in[127] - PIN w0_wd_in[128] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.276 265.421 0.300 ; - END - END w0_wd_in[128] - PIN w0_wd_in[129] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.420 265.421 0.444 ; - END - END w0_wd_in[129] - PIN w0_wd_in[130] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.564 265.421 0.588 ; - END - END w0_wd_in[130] - PIN w0_wd_in[131] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.708 265.421 0.732 ; - END - END w0_wd_in[131] - PIN w0_wd_in[132] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.852 265.421 0.876 ; - END - END w0_wd_in[132] - PIN w0_wd_in[133] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 0.996 265.421 1.020 ; - END - END w0_wd_in[133] - PIN w0_wd_in[134] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.140 265.421 1.164 ; - END - END w0_wd_in[134] - PIN w0_wd_in[135] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.284 265.421 1.308 ; - END - END w0_wd_in[135] - PIN w0_wd_in[136] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.428 265.421 1.452 ; - END - END w0_wd_in[136] - PIN w0_wd_in[137] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.572 265.421 1.596 ; - END - END w0_wd_in[137] - PIN w0_wd_in[138] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.716 265.421 1.740 ; - END - END w0_wd_in[138] - PIN w0_wd_in[139] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 1.860 265.421 1.884 ; - END - END w0_wd_in[139] - PIN w0_wd_in[140] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.004 265.421 2.028 ; - END - END w0_wd_in[140] - PIN w0_wd_in[141] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.148 265.421 2.172 ; - END - END w0_wd_in[141] - PIN w0_wd_in[142] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.292 265.421 2.316 ; - END - END w0_wd_in[142] - PIN w0_wd_in[143] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.436 265.421 2.460 ; - END - END w0_wd_in[143] - PIN w0_wd_in[144] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.580 265.421 2.604 ; - END - END w0_wd_in[144] - PIN w0_wd_in[145] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.724 265.421 2.748 ; - END - END w0_wd_in[145] - PIN w0_wd_in[146] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 2.868 265.421 2.892 ; - END - END w0_wd_in[146] - PIN w0_wd_in[147] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.012 265.421 3.036 ; - END - END w0_wd_in[147] - PIN w0_wd_in[148] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.156 265.421 3.180 ; - END - END w0_wd_in[148] - PIN w0_wd_in[149] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.300 265.421 3.324 ; - END - END w0_wd_in[149] - PIN w0_wd_in[150] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.444 265.421 3.468 ; - END - END w0_wd_in[150] - PIN w0_wd_in[151] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.588 265.421 3.612 ; - END - END w0_wd_in[151] - PIN w0_wd_in[152] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.732 265.421 3.756 ; - END - END w0_wd_in[152] - PIN w0_wd_in[153] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 3.876 265.421 3.900 ; - END - END w0_wd_in[153] - PIN w0_wd_in[154] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.020 265.421 4.044 ; - END - END w0_wd_in[154] - PIN w0_wd_in[155] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.164 265.421 4.188 ; - END - END w0_wd_in[155] - PIN w0_wd_in[156] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.308 265.421 4.332 ; - END - END w0_wd_in[156] - PIN w0_wd_in[157] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.452 265.421 4.476 ; - END - END w0_wd_in[157] - PIN w0_wd_in[158] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.596 265.421 4.620 ; - END - END w0_wd_in[158] - PIN w0_wd_in[159] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.740 265.421 4.764 ; - END - END w0_wd_in[159] - PIN w0_wd_in[160] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 4.884 265.421 4.908 ; - END - END w0_wd_in[160] - PIN w0_wd_in[161] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.028 265.421 5.052 ; - END - END w0_wd_in[161] - PIN w0_wd_in[162] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.172 265.421 5.196 ; - END - END w0_wd_in[162] - PIN w0_wd_in[163] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.316 265.421 5.340 ; - END - END w0_wd_in[163] - PIN w0_wd_in[164] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.460 265.421 5.484 ; - END - END w0_wd_in[164] - PIN w0_wd_in[165] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.604 265.421 5.628 ; - END - END w0_wd_in[165] - PIN w0_wd_in[166] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.748 265.421 5.772 ; - END - END w0_wd_in[166] - PIN w0_wd_in[167] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 5.892 265.421 5.916 ; - END - END w0_wd_in[167] - PIN w0_wd_in[168] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.036 265.421 6.060 ; - END - END w0_wd_in[168] - PIN w0_wd_in[169] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.180 265.421 6.204 ; - END - END w0_wd_in[169] - PIN w0_wd_in[170] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.324 265.421 6.348 ; - END - END w0_wd_in[170] - PIN w0_wd_in[171] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.468 265.421 6.492 ; - END - END w0_wd_in[171] - PIN w0_wd_in[172] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.612 265.421 6.636 ; - END - END w0_wd_in[172] - PIN w0_wd_in[173] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.756 265.421 6.780 ; - END - END w0_wd_in[173] - PIN w0_wd_in[174] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 6.900 265.421 6.924 ; - END - END w0_wd_in[174] - PIN w0_wd_in[175] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.044 265.421 7.068 ; - END - END w0_wd_in[175] - PIN w0_wd_in[176] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.188 265.421 7.212 ; - END - END w0_wd_in[176] - PIN w0_wd_in[177] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.332 265.421 7.356 ; - END - END w0_wd_in[177] - PIN w0_wd_in[178] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.476 265.421 7.500 ; - END - END w0_wd_in[178] - PIN w0_wd_in[179] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.620 265.421 7.644 ; - END - END w0_wd_in[179] - PIN w0_wd_in[180] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.764 265.421 7.788 ; - END - END w0_wd_in[180] - PIN w0_wd_in[181] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 7.908 265.421 7.932 ; - END - END w0_wd_in[181] - PIN w0_wd_in[182] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.052 265.421 8.076 ; - END - END w0_wd_in[182] - PIN w0_wd_in[183] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.196 265.421 8.220 ; - END - END w0_wd_in[183] - PIN w0_wd_in[184] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.340 265.421 8.364 ; - END - END w0_wd_in[184] - PIN w0_wd_in[185] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.484 265.421 8.508 ; - END - END w0_wd_in[185] - PIN w0_wd_in[186] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.628 265.421 8.652 ; - END - END w0_wd_in[186] - PIN w0_wd_in[187] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.772 265.421 8.796 ; - END - END w0_wd_in[187] - PIN w0_wd_in[188] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 8.916 265.421 8.940 ; - END - END w0_wd_in[188] - PIN w0_wd_in[189] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.060 265.421 9.084 ; - END - END w0_wd_in[189] - PIN w0_wd_in[190] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.204 265.421 9.228 ; - END - END w0_wd_in[190] - PIN w0_wd_in[191] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.348 265.421 9.372 ; - END - END w0_wd_in[191] - PIN w0_wd_in[192] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.492 265.421 9.516 ; - END - END w0_wd_in[192] - PIN w0_wd_in[193] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.636 265.421 9.660 ; - END - END w0_wd_in[193] - PIN w0_wd_in[194] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.780 265.421 9.804 ; - END - END w0_wd_in[194] - PIN w0_wd_in[195] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 9.924 265.421 9.948 ; - END - END w0_wd_in[195] - PIN w0_wd_in[196] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.068 265.421 10.092 ; - END - END w0_wd_in[196] - PIN w0_wd_in[197] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.212 265.421 10.236 ; - END - END w0_wd_in[197] - PIN w0_wd_in[198] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.356 265.421 10.380 ; - END - END w0_wd_in[198] - PIN w0_wd_in[199] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.500 265.421 10.524 ; - END - END w0_wd_in[199] - PIN w0_wd_in[200] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.644 265.421 10.668 ; - END - END w0_wd_in[200] - PIN w0_wd_in[201] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.788 265.421 10.812 ; - END - END w0_wd_in[201] - PIN w0_wd_in[202] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 10.932 265.421 10.956 ; - END - END w0_wd_in[202] - PIN w0_wd_in[203] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.076 265.421 11.100 ; - END - END w0_wd_in[203] - PIN w0_wd_in[204] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.220 265.421 11.244 ; - END - END w0_wd_in[204] - PIN w0_wd_in[205] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.364 265.421 11.388 ; - END - END w0_wd_in[205] - PIN w0_wd_in[206] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.508 265.421 11.532 ; - END - END w0_wd_in[206] - PIN w0_wd_in[207] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.652 265.421 11.676 ; - END - END w0_wd_in[207] - PIN w0_wd_in[208] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.796 265.421 11.820 ; - END - END w0_wd_in[208] - PIN w0_wd_in[209] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 11.940 265.421 11.964 ; - END - END w0_wd_in[209] - PIN w0_wd_in[210] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.084 265.421 12.108 ; - END - END w0_wd_in[210] - PIN w0_wd_in[211] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.228 265.421 12.252 ; - END - END w0_wd_in[211] - PIN w0_wd_in[212] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.372 265.421 12.396 ; - END - END w0_wd_in[212] - PIN w0_wd_in[213] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.516 265.421 12.540 ; - END - END w0_wd_in[213] - PIN w0_wd_in[214] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.660 265.421 12.684 ; - END - END w0_wd_in[214] - PIN w0_wd_in[215] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.804 265.421 12.828 ; - END - END w0_wd_in[215] - PIN w0_wd_in[216] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 12.948 265.421 12.972 ; - END - END w0_wd_in[216] - PIN w0_wd_in[217] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.092 265.421 13.116 ; - END - END w0_wd_in[217] - PIN w0_wd_in[218] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.236 265.421 13.260 ; - END - END w0_wd_in[218] - PIN w0_wd_in[219] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.380 265.421 13.404 ; - END - END w0_wd_in[219] - PIN w0_wd_in[220] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.524 265.421 13.548 ; - END - END w0_wd_in[220] - PIN w0_wd_in[221] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.668 265.421 13.692 ; - END - END w0_wd_in[221] - PIN w0_wd_in[222] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.812 265.421 13.836 ; - END - END w0_wd_in[222] - PIN w0_wd_in[223] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 13.956 265.421 13.980 ; - END - END w0_wd_in[223] - PIN w0_wd_in[224] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.100 265.421 14.124 ; - END - END w0_wd_in[224] - PIN w0_wd_in[225] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.244 265.421 14.268 ; - END - END w0_wd_in[225] - PIN w0_wd_in[226] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.388 265.421 14.412 ; - END - END w0_wd_in[226] - PIN w0_wd_in[227] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.532 265.421 14.556 ; - END - END w0_wd_in[227] - PIN w0_wd_in[228] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.676 265.421 14.700 ; - END - END w0_wd_in[228] - PIN w0_wd_in[229] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.820 265.421 14.844 ; - END - END w0_wd_in[229] - PIN w0_wd_in[230] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 14.964 265.421 14.988 ; - END - END w0_wd_in[230] - PIN w0_wd_in[231] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.108 265.421 15.132 ; - END - END w0_wd_in[231] - PIN w0_wd_in[232] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.252 265.421 15.276 ; - END - END w0_wd_in[232] - PIN w0_wd_in[233] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.396 265.421 15.420 ; - END - END w0_wd_in[233] - PIN w0_wd_in[234] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.540 265.421 15.564 ; - END - END w0_wd_in[234] - PIN w0_wd_in[235] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.684 265.421 15.708 ; - END - END w0_wd_in[235] - PIN w0_wd_in[236] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.828 265.421 15.852 ; - END - END w0_wd_in[236] - PIN w0_wd_in[237] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 15.972 265.421 15.996 ; - END - END w0_wd_in[237] - PIN w0_wd_in[238] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.116 265.421 16.140 ; - END - END w0_wd_in[238] - PIN w0_wd_in[239] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.260 265.421 16.284 ; - END - END w0_wd_in[239] - PIN w0_wd_in[240] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.404 265.421 16.428 ; - END - END w0_wd_in[240] - PIN w0_wd_in[241] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.548 265.421 16.572 ; - END - END w0_wd_in[241] - PIN w0_wd_in[242] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.692 265.421 16.716 ; - END - END w0_wd_in[242] - PIN w0_wd_in[243] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.836 265.421 16.860 ; - END - END w0_wd_in[243] - PIN w0_wd_in[244] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 16.980 265.421 17.004 ; - END - END w0_wd_in[244] - PIN w0_wd_in[245] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.124 265.421 17.148 ; - END - END w0_wd_in[245] - PIN w0_wd_in[246] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.268 265.421 17.292 ; - END - END w0_wd_in[246] - PIN w0_wd_in[247] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.412 265.421 17.436 ; - END - END w0_wd_in[247] - PIN w0_wd_in[248] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.556 265.421 17.580 ; - END - END w0_wd_in[248] - PIN w0_wd_in[249] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.700 265.421 17.724 ; - END - END w0_wd_in[249] - PIN w0_wd_in[250] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.844 265.421 17.868 ; - END - END w0_wd_in[250] - PIN w0_wd_in[251] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 17.988 265.421 18.012 ; - END - END w0_wd_in[251] - PIN w0_wd_in[252] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.132 265.421 18.156 ; - END - END w0_wd_in[252] - PIN w0_wd_in[253] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.276 265.421 18.300 ; - END - END w0_wd_in[253] - PIN w0_wd_in[254] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.420 265.421 18.444 ; - END - END w0_wd_in[254] - PIN w0_wd_in[255] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.564 265.421 18.588 ; - END - END w0_wd_in[255] - PIN w0_wd_in[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.207 0.000 0.225 0.018 ; - END - END w0_wd_in[256] - PIN w0_wd_in[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.711 0.000 0.729 0.018 ; - END - END w0_wd_in[257] - PIN w0_wd_in[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.215 0.000 1.233 0.018 ; - END - END w0_wd_in[258] - PIN w0_wd_in[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.719 0.000 1.737 0.018 ; - END - END w0_wd_in[259] - PIN w0_wd_in[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.223 0.000 2.241 0.018 ; - END - END w0_wd_in[260] - PIN w0_wd_in[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.727 0.000 2.745 0.018 ; - END - END w0_wd_in[261] - PIN w0_wd_in[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.231 0.000 3.249 0.018 ; - END - END w0_wd_in[262] - PIN w0_wd_in[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.735 0.000 3.753 0.018 ; - END - END w0_wd_in[263] - PIN w0_wd_in[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.239 0.000 4.257 0.018 ; - END - END w0_wd_in[264] - PIN w0_wd_in[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.743 0.000 4.761 0.018 ; - END - END w0_wd_in[265] - PIN w0_wd_in[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.247 0.000 5.265 0.018 ; - END - END w0_wd_in[266] - PIN w0_wd_in[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.751 0.000 5.769 0.018 ; - END - END w0_wd_in[267] - PIN w0_wd_in[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.255 0.000 6.273 0.018 ; - END - END w0_wd_in[268] - PIN w0_wd_in[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.759 0.000 6.777 0.018 ; - END - END w0_wd_in[269] - PIN w0_wd_in[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 7.263 0.000 7.281 0.018 ; - END - END w0_wd_in[270] - PIN w0_wd_in[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 7.767 0.000 7.785 0.018 ; - END - END w0_wd_in[271] - PIN w0_wd_in[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 8.271 0.000 8.289 0.018 ; - END - END w0_wd_in[272] - PIN w0_wd_in[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 8.775 0.000 8.793 0.018 ; - END - END w0_wd_in[273] - PIN w0_wd_in[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.279 0.000 9.297 0.018 ; - END - END w0_wd_in[274] - PIN w0_wd_in[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.783 0.000 9.801 0.018 ; - END - END w0_wd_in[275] - PIN w0_wd_in[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 10.287 0.000 10.305 0.018 ; - END - END w0_wd_in[276] - PIN w0_wd_in[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 10.791 0.000 10.809 0.018 ; - END - END w0_wd_in[277] - PIN w0_wd_in[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 11.295 0.000 11.313 0.018 ; - END - END w0_wd_in[278] - PIN w0_wd_in[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 11.799 0.000 11.817 0.018 ; - END - END w0_wd_in[279] - PIN w0_wd_in[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 12.303 0.000 12.321 0.018 ; - END - END w0_wd_in[280] - PIN w0_wd_in[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 12.807 0.000 12.825 0.018 ; - END - END w0_wd_in[281] - PIN w0_wd_in[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 13.311 0.000 13.329 0.018 ; - END - END w0_wd_in[282] - PIN w0_wd_in[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 13.815 0.000 13.833 0.018 ; - END - END w0_wd_in[283] - PIN w0_wd_in[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.319 0.000 14.337 0.018 ; - END - END w0_wd_in[284] - PIN w0_wd_in[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.823 0.000 14.841 0.018 ; - END - END w0_wd_in[285] - PIN w0_wd_in[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.327 0.000 15.345 0.018 ; - END - END w0_wd_in[286] - PIN w0_wd_in[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.831 0.000 15.849 0.018 ; - END - END w0_wd_in[287] - PIN w0_wd_in[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 16.335 0.000 16.353 0.018 ; - END - END w0_wd_in[288] - PIN w0_wd_in[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 16.839 0.000 16.857 0.018 ; - END - END w0_wd_in[289] - PIN w0_wd_in[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 17.343 0.000 17.361 0.018 ; - END - END w0_wd_in[290] - PIN w0_wd_in[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 17.847 0.000 17.865 0.018 ; - END - END w0_wd_in[291] - PIN w0_wd_in[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 18.351 0.000 18.369 0.018 ; - END - END w0_wd_in[292] - PIN w0_wd_in[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 18.855 0.000 18.873 0.018 ; - END - END w0_wd_in[293] - PIN w0_wd_in[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 19.359 0.000 19.377 0.018 ; - END - END w0_wd_in[294] - PIN w0_wd_in[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 19.863 0.000 19.881 0.018 ; - END - END w0_wd_in[295] - PIN w0_wd_in[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 20.367 0.000 20.385 0.018 ; - END - END w0_wd_in[296] - PIN w0_wd_in[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 20.871 0.000 20.889 0.018 ; - END - END w0_wd_in[297] - PIN w0_wd_in[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 21.375 0.000 21.393 0.018 ; - END - END w0_wd_in[298] - PIN w0_wd_in[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 21.879 0.000 21.897 0.018 ; - END - END w0_wd_in[299] - PIN w0_wd_in[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 22.383 0.000 22.401 0.018 ; - END - END w0_wd_in[300] - PIN w0_wd_in[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 22.887 0.000 22.905 0.018 ; - END - END w0_wd_in[301] - PIN w0_wd_in[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 23.391 0.000 23.409 0.018 ; - END - END w0_wd_in[302] - PIN w0_wd_in[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 23.895 0.000 23.913 0.018 ; - END - END w0_wd_in[303] - PIN w0_wd_in[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 24.399 0.000 24.417 0.018 ; - END - END w0_wd_in[304] - PIN w0_wd_in[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 24.903 0.000 24.921 0.018 ; - END - END w0_wd_in[305] - PIN w0_wd_in[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 25.407 0.000 25.425 0.018 ; - END - END w0_wd_in[306] - PIN w0_wd_in[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 25.911 0.000 25.929 0.018 ; - END - END w0_wd_in[307] - PIN w0_wd_in[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 26.415 0.000 26.433 0.018 ; - END - END w0_wd_in[308] - PIN w0_wd_in[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 26.919 0.000 26.937 0.018 ; - END - END w0_wd_in[309] - PIN w0_wd_in[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 27.423 0.000 27.441 0.018 ; - END - END w0_wd_in[310] - PIN w0_wd_in[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 27.927 0.000 27.945 0.018 ; - END - END w0_wd_in[311] - PIN w0_wd_in[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 28.431 0.000 28.449 0.018 ; - END - END w0_wd_in[312] - PIN w0_wd_in[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 28.935 0.000 28.953 0.018 ; - END - END w0_wd_in[313] - PIN w0_wd_in[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 29.439 0.000 29.457 0.018 ; - END - END w0_wd_in[314] - PIN w0_wd_in[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 29.943 0.000 29.961 0.018 ; - END - END w0_wd_in[315] - PIN w0_wd_in[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 30.447 0.000 30.465 0.018 ; - END - END w0_wd_in[316] - PIN w0_wd_in[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 30.951 0.000 30.969 0.018 ; - END - END w0_wd_in[317] - PIN w0_wd_in[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 31.455 0.000 31.473 0.018 ; - END - END w0_wd_in[318] - PIN w0_wd_in[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 31.959 0.000 31.977 0.018 ; - END - END w0_wd_in[319] - PIN w0_wd_in[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 32.463 0.000 32.481 0.018 ; - END - END w0_wd_in[320] - PIN w0_wd_in[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 32.967 0.000 32.985 0.018 ; - END - END w0_wd_in[321] - PIN w0_wd_in[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 33.471 0.000 33.489 0.018 ; - END - END w0_wd_in[322] - PIN w0_wd_in[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 33.975 0.000 33.993 0.018 ; - END - END w0_wd_in[323] - PIN w0_wd_in[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 34.479 0.000 34.497 0.018 ; - END - END w0_wd_in[324] - PIN w0_wd_in[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 34.983 0.000 35.001 0.018 ; - END - END w0_wd_in[325] - PIN w0_wd_in[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 35.487 0.000 35.505 0.018 ; - END - END w0_wd_in[326] - PIN w0_wd_in[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 35.991 0.000 36.009 0.018 ; - END - END w0_wd_in[327] - PIN w0_wd_in[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 36.495 0.000 36.513 0.018 ; - END - END w0_wd_in[328] - PIN w0_wd_in[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 36.999 0.000 37.017 0.018 ; - END - END w0_wd_in[329] - PIN w0_wd_in[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 37.503 0.000 37.521 0.018 ; - END - END w0_wd_in[330] - PIN w0_wd_in[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 38.007 0.000 38.025 0.018 ; - END - END w0_wd_in[331] - PIN w0_wd_in[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 38.511 0.000 38.529 0.018 ; - END - END w0_wd_in[332] - PIN w0_wd_in[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 39.015 0.000 39.033 0.018 ; - END - END w0_wd_in[333] - PIN w0_wd_in[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 39.519 0.000 39.537 0.018 ; - END - END w0_wd_in[334] - PIN w0_wd_in[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 40.023 0.000 40.041 0.018 ; - END - END w0_wd_in[335] - PIN w0_wd_in[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 40.527 0.000 40.545 0.018 ; - END - END w0_wd_in[336] - PIN w0_wd_in[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 41.031 0.000 41.049 0.018 ; - END - END w0_wd_in[337] - PIN w0_wd_in[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 41.535 0.000 41.553 0.018 ; - END - END w0_wd_in[338] - PIN w0_wd_in[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 42.039 0.000 42.057 0.018 ; - END - END w0_wd_in[339] - PIN w0_wd_in[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 42.543 0.000 42.561 0.018 ; - END - END w0_wd_in[340] - PIN w0_wd_in[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 43.047 0.000 43.065 0.018 ; - END - END w0_wd_in[341] - PIN w0_wd_in[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 43.551 0.000 43.569 0.018 ; - END - END w0_wd_in[342] - PIN w0_wd_in[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 44.055 0.000 44.073 0.018 ; - END - END w0_wd_in[343] - PIN w0_wd_in[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 44.559 0.000 44.577 0.018 ; - END - END w0_wd_in[344] - PIN w0_wd_in[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 45.063 0.000 45.081 0.018 ; - END - END w0_wd_in[345] - PIN w0_wd_in[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 45.567 0.000 45.585 0.018 ; - END - END w0_wd_in[346] - PIN w0_wd_in[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 46.071 0.000 46.089 0.018 ; - END - END w0_wd_in[347] - PIN w0_wd_in[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 46.575 0.000 46.593 0.018 ; - END - END w0_wd_in[348] - PIN w0_wd_in[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 47.079 0.000 47.097 0.018 ; - END - END w0_wd_in[349] - PIN w0_wd_in[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 47.583 0.000 47.601 0.018 ; - END - END w0_wd_in[350] - PIN w0_wd_in[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 48.087 0.000 48.105 0.018 ; - END - END w0_wd_in[351] - PIN w0_wd_in[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 48.591 0.000 48.609 0.018 ; - END - END w0_wd_in[352] - PIN w0_wd_in[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 49.095 0.000 49.113 0.018 ; - END - END w0_wd_in[353] - PIN w0_wd_in[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 49.599 0.000 49.617 0.018 ; - END - END w0_wd_in[354] - PIN w0_wd_in[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 50.103 0.000 50.121 0.018 ; - END - END w0_wd_in[355] - PIN w0_wd_in[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 50.607 0.000 50.625 0.018 ; - END - END w0_wd_in[356] - PIN w0_wd_in[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 51.111 0.000 51.129 0.018 ; - END - END w0_wd_in[357] - PIN w0_wd_in[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 51.615 0.000 51.633 0.018 ; - END - END w0_wd_in[358] - PIN w0_wd_in[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 52.119 0.000 52.137 0.018 ; - END - END w0_wd_in[359] - PIN w0_wd_in[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 52.623 0.000 52.641 0.018 ; - END - END w0_wd_in[360] - PIN w0_wd_in[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 53.127 0.000 53.145 0.018 ; - END - END w0_wd_in[361] - PIN w0_wd_in[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 53.631 0.000 53.649 0.018 ; - END - END w0_wd_in[362] - PIN w0_wd_in[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 54.135 0.000 54.153 0.018 ; - END - END w0_wd_in[363] - PIN w0_wd_in[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 54.639 0.000 54.657 0.018 ; - END - END w0_wd_in[364] - PIN w0_wd_in[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 55.143 0.000 55.161 0.018 ; - END - END w0_wd_in[365] - PIN w0_wd_in[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 55.647 0.000 55.665 0.018 ; - END - END w0_wd_in[366] - PIN w0_wd_in[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 56.151 0.000 56.169 0.018 ; - END - END w0_wd_in[367] - PIN w0_wd_in[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 56.655 0.000 56.673 0.018 ; - END - END w0_wd_in[368] - PIN w0_wd_in[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 57.159 0.000 57.177 0.018 ; - END - END w0_wd_in[369] - PIN w0_wd_in[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 57.663 0.000 57.681 0.018 ; - END - END w0_wd_in[370] - PIN w0_wd_in[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 58.167 0.000 58.185 0.018 ; - END - END w0_wd_in[371] - PIN w0_wd_in[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 58.671 0.000 58.689 0.018 ; - END - END w0_wd_in[372] - PIN w0_wd_in[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 59.175 0.000 59.193 0.018 ; - END - END w0_wd_in[373] - PIN w0_wd_in[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 59.679 0.000 59.697 0.018 ; - END - END w0_wd_in[374] - PIN w0_wd_in[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 60.183 0.000 60.201 0.018 ; - END - END w0_wd_in[375] - PIN w0_wd_in[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 60.687 0.000 60.705 0.018 ; - END - END w0_wd_in[376] - PIN w0_wd_in[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 61.191 0.000 61.209 0.018 ; - END - END w0_wd_in[377] - PIN w0_wd_in[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 61.695 0.000 61.713 0.018 ; - END - END w0_wd_in[378] - PIN w0_wd_in[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 62.199 0.000 62.217 0.018 ; - END - END w0_wd_in[379] - PIN w0_wd_in[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 62.703 0.000 62.721 0.018 ; - END - END w0_wd_in[380] - PIN w0_wd_in[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 63.207 0.000 63.225 0.018 ; - END - END w0_wd_in[381] - PIN w0_wd_in[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 63.711 0.000 63.729 0.018 ; - END - END w0_wd_in[382] - PIN w0_wd_in[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 64.215 0.000 64.233 0.018 ; - END - END w0_wd_in[383] - PIN w0_wd_in[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 64.719 0.000 64.737 0.018 ; - END - END w0_wd_in[384] - PIN w0_wd_in[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 65.223 0.000 65.241 0.018 ; - END - END w0_wd_in[385] - PIN w0_wd_in[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 65.727 0.000 65.745 0.018 ; - END - END w0_wd_in[386] - PIN w0_wd_in[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 66.231 0.000 66.249 0.018 ; - END - END w0_wd_in[387] - PIN w0_wd_in[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 66.735 0.000 66.753 0.018 ; - END - END w0_wd_in[388] - PIN w0_wd_in[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 67.239 0.000 67.257 0.018 ; - END - END w0_wd_in[389] - PIN w0_wd_in[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 67.743 0.000 67.761 0.018 ; - END - END w0_wd_in[390] - PIN w0_wd_in[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 68.247 0.000 68.265 0.018 ; - END - END w0_wd_in[391] - PIN w0_wd_in[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 68.751 0.000 68.769 0.018 ; - END - END w0_wd_in[392] - PIN w0_wd_in[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 69.255 0.000 69.273 0.018 ; - END - END w0_wd_in[393] - PIN w0_wd_in[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 69.759 0.000 69.777 0.018 ; - END - END w0_wd_in[394] - PIN w0_wd_in[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 70.263 0.000 70.281 0.018 ; - END - END w0_wd_in[395] - PIN w0_wd_in[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 70.767 0.000 70.785 0.018 ; - END - END w0_wd_in[396] - PIN w0_wd_in[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 71.271 0.000 71.289 0.018 ; - END - END w0_wd_in[397] - PIN w0_wd_in[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 71.775 0.000 71.793 0.018 ; - END - END w0_wd_in[398] - PIN w0_wd_in[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 72.279 0.000 72.297 0.018 ; - END - END w0_wd_in[399] - PIN w0_wd_in[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 72.783 0.000 72.801 0.018 ; - END - END w0_wd_in[400] - PIN w0_wd_in[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 73.287 0.000 73.305 0.018 ; - END - END w0_wd_in[401] - PIN w0_wd_in[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 73.791 0.000 73.809 0.018 ; - END - END w0_wd_in[402] - PIN w0_wd_in[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 74.295 0.000 74.313 0.018 ; - END - END w0_wd_in[403] - PIN w0_wd_in[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 74.799 0.000 74.817 0.018 ; - END - END w0_wd_in[404] - PIN w0_wd_in[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 75.303 0.000 75.321 0.018 ; - END - END w0_wd_in[405] - PIN w0_wd_in[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 75.807 0.000 75.825 0.018 ; - END - END w0_wd_in[406] - PIN w0_wd_in[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 76.311 0.000 76.329 0.018 ; - END - END w0_wd_in[407] - PIN w0_wd_in[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 76.815 0.000 76.833 0.018 ; - END - END w0_wd_in[408] - PIN w0_wd_in[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 77.319 0.000 77.337 0.018 ; - END - END w0_wd_in[409] - PIN w0_wd_in[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 77.823 0.000 77.841 0.018 ; - END - END w0_wd_in[410] - PIN w0_wd_in[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 78.327 0.000 78.345 0.018 ; - END - END w0_wd_in[411] - PIN w0_wd_in[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 78.831 0.000 78.849 0.018 ; - END - END w0_wd_in[412] - PIN w0_wd_in[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 79.335 0.000 79.353 0.018 ; - END - END w0_wd_in[413] - PIN w0_wd_in[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 79.839 0.000 79.857 0.018 ; - END - END w0_wd_in[414] - PIN w0_wd_in[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 80.343 0.000 80.361 0.018 ; - END - END w0_wd_in[415] - PIN w0_wd_in[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 80.847 0.000 80.865 0.018 ; - END - END w0_wd_in[416] - PIN w0_wd_in[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 81.351 0.000 81.369 0.018 ; - END - END w0_wd_in[417] - PIN w0_wd_in[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 81.855 0.000 81.873 0.018 ; - END - END w0_wd_in[418] - PIN w0_wd_in[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 82.359 0.000 82.377 0.018 ; - END - END w0_wd_in[419] - PIN w0_wd_in[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 82.863 0.000 82.881 0.018 ; - END - END w0_wd_in[420] - PIN w0_wd_in[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 83.367 0.000 83.385 0.018 ; - END - END w0_wd_in[421] - PIN w0_wd_in[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 83.871 0.000 83.889 0.018 ; - END - END w0_wd_in[422] - PIN w0_wd_in[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 84.375 0.000 84.393 0.018 ; - END - END w0_wd_in[423] - PIN w0_wd_in[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 84.879 0.000 84.897 0.018 ; - END - END w0_wd_in[424] - PIN w0_wd_in[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 85.383 0.000 85.401 0.018 ; - END - END w0_wd_in[425] - PIN w0_wd_in[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 85.887 0.000 85.905 0.018 ; - END - END w0_wd_in[426] - PIN w0_wd_in[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 86.391 0.000 86.409 0.018 ; - END - END w0_wd_in[427] - PIN w0_wd_in[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 86.895 0.000 86.913 0.018 ; - END - END w0_wd_in[428] - PIN w0_wd_in[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 87.399 0.000 87.417 0.018 ; - END - END w0_wd_in[429] - PIN w0_wd_in[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 87.903 0.000 87.921 0.018 ; - END - END w0_wd_in[430] - PIN w0_wd_in[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 88.407 0.000 88.425 0.018 ; - END - END w0_wd_in[431] - PIN w0_wd_in[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 88.911 0.000 88.929 0.018 ; - END - END w0_wd_in[432] - PIN w0_wd_in[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 89.415 0.000 89.433 0.018 ; - END - END w0_wd_in[433] - PIN w0_wd_in[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 89.919 0.000 89.937 0.018 ; - END - END w0_wd_in[434] - PIN w0_wd_in[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 90.423 0.000 90.441 0.018 ; - END - END w0_wd_in[435] - PIN w0_wd_in[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 90.927 0.000 90.945 0.018 ; - END - END w0_wd_in[436] - PIN w0_wd_in[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 91.431 0.000 91.449 0.018 ; - END - END w0_wd_in[437] - PIN w0_wd_in[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 91.935 0.000 91.953 0.018 ; - END - END w0_wd_in[438] - PIN w0_wd_in[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 92.439 0.000 92.457 0.018 ; - END - END w0_wd_in[439] - PIN w0_wd_in[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 92.943 0.000 92.961 0.018 ; - END - END w0_wd_in[440] - PIN w0_wd_in[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 93.447 0.000 93.465 0.018 ; - END - END w0_wd_in[441] - PIN w0_wd_in[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 93.951 0.000 93.969 0.018 ; - END - END w0_wd_in[442] - PIN w0_wd_in[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 94.455 0.000 94.473 0.018 ; - END - END w0_wd_in[443] - PIN w0_wd_in[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 94.959 0.000 94.977 0.018 ; - END - END w0_wd_in[444] - PIN w0_wd_in[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 95.463 0.000 95.481 0.018 ; - END - END w0_wd_in[445] - PIN w0_wd_in[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 95.967 0.000 95.985 0.018 ; - END - END w0_wd_in[446] - PIN w0_wd_in[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 96.471 0.000 96.489 0.018 ; - END - END w0_wd_in[447] - PIN w0_wd_in[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 96.975 0.000 96.993 0.018 ; - END - END w0_wd_in[448] - PIN w0_wd_in[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 97.479 0.000 97.497 0.018 ; - END - END w0_wd_in[449] - PIN w0_wd_in[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 97.983 0.000 98.001 0.018 ; - END - END w0_wd_in[450] - PIN w0_wd_in[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 98.487 0.000 98.505 0.018 ; - END - END w0_wd_in[451] - PIN w0_wd_in[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 98.991 0.000 99.009 0.018 ; - END - END w0_wd_in[452] - PIN w0_wd_in[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 99.495 0.000 99.513 0.018 ; - END - END w0_wd_in[453] - PIN w0_wd_in[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 99.999 0.000 100.017 0.018 ; - END - END w0_wd_in[454] - PIN w0_wd_in[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 100.503 0.000 100.521 0.018 ; - END - END w0_wd_in[455] - PIN w0_wd_in[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 101.007 0.000 101.025 0.018 ; - END - END w0_wd_in[456] - PIN w0_wd_in[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 101.511 0.000 101.529 0.018 ; - END - END w0_wd_in[457] - PIN w0_wd_in[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 102.015 0.000 102.033 0.018 ; - END - END w0_wd_in[458] - PIN w0_wd_in[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 102.519 0.000 102.537 0.018 ; - END - END w0_wd_in[459] - PIN w0_wd_in[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 103.023 0.000 103.041 0.018 ; - END - END w0_wd_in[460] - PIN w0_wd_in[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 103.527 0.000 103.545 0.018 ; - END - END w0_wd_in[461] - PIN w0_wd_in[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 104.031 0.000 104.049 0.018 ; - END - END w0_wd_in[462] - PIN w0_wd_in[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 104.535 0.000 104.553 0.018 ; - END - END w0_wd_in[463] - PIN w0_wd_in[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 105.039 0.000 105.057 0.018 ; - END - END w0_wd_in[464] - PIN w0_wd_in[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 105.543 0.000 105.561 0.018 ; - END - END w0_wd_in[465] - PIN w0_wd_in[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 106.047 0.000 106.065 0.018 ; - END - END w0_wd_in[466] - PIN w0_wd_in[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 106.551 0.000 106.569 0.018 ; - END - END w0_wd_in[467] - PIN w0_wd_in[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 107.055 0.000 107.073 0.018 ; - END - END w0_wd_in[468] - PIN w0_wd_in[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 107.559 0.000 107.577 0.018 ; - END - END w0_wd_in[469] - PIN w0_wd_in[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 108.063 0.000 108.081 0.018 ; - END - END w0_wd_in[470] - PIN w0_wd_in[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 108.567 0.000 108.585 0.018 ; - END - END w0_wd_in[471] - PIN w0_wd_in[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 109.071 0.000 109.089 0.018 ; - END - END w0_wd_in[472] - PIN w0_wd_in[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 109.575 0.000 109.593 0.018 ; - END - END w0_wd_in[473] - PIN w0_wd_in[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 110.079 0.000 110.097 0.018 ; - END - END w0_wd_in[474] - PIN w0_wd_in[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 110.583 0.000 110.601 0.018 ; - END - END w0_wd_in[475] - PIN w0_wd_in[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 111.087 0.000 111.105 0.018 ; - END - END w0_wd_in[476] - PIN w0_wd_in[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 111.591 0.000 111.609 0.018 ; - END - END w0_wd_in[477] - PIN w0_wd_in[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 112.095 0.000 112.113 0.018 ; - END - END w0_wd_in[478] - PIN w0_wd_in[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 112.599 0.000 112.617 0.018 ; - END - END w0_wd_in[479] - PIN w0_wd_in[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 113.103 0.000 113.121 0.018 ; - END - END w0_wd_in[480] - PIN w0_wd_in[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 113.607 0.000 113.625 0.018 ; - END - END w0_wd_in[481] - PIN w0_wd_in[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 114.111 0.000 114.129 0.018 ; - END - END w0_wd_in[482] - PIN w0_wd_in[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 114.615 0.000 114.633 0.018 ; - END - END w0_wd_in[483] - PIN w0_wd_in[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 115.119 0.000 115.137 0.018 ; - END - END w0_wd_in[484] - PIN w0_wd_in[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 115.623 0.000 115.641 0.018 ; - END - END w0_wd_in[485] - PIN w0_wd_in[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 116.127 0.000 116.145 0.018 ; - END - END w0_wd_in[486] - PIN w0_wd_in[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 116.631 0.000 116.649 0.018 ; - END - END w0_wd_in[487] - PIN w0_wd_in[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 117.135 0.000 117.153 0.018 ; - END - END w0_wd_in[488] - PIN w0_wd_in[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 117.639 0.000 117.657 0.018 ; - END - END w0_wd_in[489] - PIN w0_wd_in[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 118.143 0.000 118.161 0.018 ; - END - END w0_wd_in[490] - PIN w0_wd_in[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 118.647 0.000 118.665 0.018 ; - END - END w0_wd_in[491] - PIN w0_wd_in[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 119.151 0.000 119.169 0.018 ; - END - END w0_wd_in[492] - PIN w0_wd_in[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 119.655 0.000 119.673 0.018 ; - END - END w0_wd_in[493] - PIN w0_wd_in[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 120.159 0.000 120.177 0.018 ; - END - END w0_wd_in[494] - PIN w0_wd_in[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 120.663 0.000 120.681 0.018 ; - END - END w0_wd_in[495] - PIN w0_wd_in[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 121.167 0.000 121.185 0.018 ; - END - END w0_wd_in[496] - PIN w0_wd_in[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 121.671 0.000 121.689 0.018 ; - END - END w0_wd_in[497] - PIN w0_wd_in[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 122.175 0.000 122.193 0.018 ; - END - END w0_wd_in[498] - PIN w0_wd_in[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 122.679 0.000 122.697 0.018 ; - END - END w0_wd_in[499] - PIN w0_wd_in[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 123.183 0.000 123.201 0.018 ; - END - END w0_wd_in[500] - PIN w0_wd_in[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 123.687 0.000 123.705 0.018 ; - END - END w0_wd_in[501] - PIN w0_wd_in[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 124.191 0.000 124.209 0.018 ; - END - END w0_wd_in[502] - PIN w0_wd_in[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 124.695 0.000 124.713 0.018 ; - END - END w0_wd_in[503] - PIN w0_wd_in[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 125.199 0.000 125.217 0.018 ; - END - END w0_wd_in[504] - PIN w0_wd_in[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 125.703 0.000 125.721 0.018 ; - END - END w0_wd_in[505] - PIN w0_wd_in[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 126.207 0.000 126.225 0.018 ; - END - END w0_wd_in[506] - PIN w0_wd_in[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 126.711 0.000 126.729 0.018 ; - END - END w0_wd_in[507] - PIN w0_wd_in[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 127.215 0.000 127.233 0.018 ; - END - END w0_wd_in[508] - PIN w0_wd_in[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 127.719 0.000 127.737 0.018 ; - END - END w0_wd_in[509] - PIN w0_wd_in[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 128.223 0.000 128.241 0.018 ; - END - END w0_wd_in[510] - PIN w0_wd_in[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 128.727 0.000 128.745 0.018 ; - END - END w0_wd_in[511] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 129.231 0.000 129.249 0.018 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 129.735 0.000 129.753 0.018 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 130.239 0.000 130.257 0.018 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 130.743 0.000 130.761 0.018 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 131.247 0.000 131.265 0.018 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 131.751 0.000 131.769 0.018 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 132.255 0.000 132.273 0.018 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 132.759 0.000 132.777 0.018 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 133.263 0.000 133.281 0.018 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 133.767 0.000 133.785 0.018 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 134.271 0.000 134.289 0.018 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 134.775 0.000 134.793 0.018 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 135.279 0.000 135.297 0.018 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 135.783 0.000 135.801 0.018 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 136.287 0.000 136.305 0.018 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 136.791 0.000 136.809 0.018 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 137.295 0.000 137.313 0.018 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 137.799 0.000 137.817 0.018 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 138.303 0.000 138.321 0.018 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 138.807 0.000 138.825 0.018 ; - END - END r0_rd_out[19] - PIN r0_rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 139.311 0.000 139.329 0.018 ; - END - END r0_rd_out[20] - PIN r0_rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 139.815 0.000 139.833 0.018 ; - END - END r0_rd_out[21] - PIN r0_rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 140.319 0.000 140.337 0.018 ; - END - END r0_rd_out[22] - PIN r0_rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 140.823 0.000 140.841 0.018 ; - END - END r0_rd_out[23] - PIN r0_rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 141.327 0.000 141.345 0.018 ; - END - END r0_rd_out[24] - PIN r0_rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 141.831 0.000 141.849 0.018 ; - END - END r0_rd_out[25] - PIN r0_rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 142.335 0.000 142.353 0.018 ; - END - END r0_rd_out[26] - PIN r0_rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 142.839 0.000 142.857 0.018 ; - END - END r0_rd_out[27] - PIN r0_rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 143.343 0.000 143.361 0.018 ; - END - END r0_rd_out[28] - PIN r0_rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 143.847 0.000 143.865 0.018 ; - END - END r0_rd_out[29] - PIN r0_rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 144.351 0.000 144.369 0.018 ; - END - END r0_rd_out[30] - PIN r0_rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 144.855 0.000 144.873 0.018 ; - END - END r0_rd_out[31] - PIN r0_rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 145.359 0.000 145.377 0.018 ; - END - END r0_rd_out[32] - PIN r0_rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 145.863 0.000 145.881 0.018 ; - END - END r0_rd_out[33] - PIN r0_rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 146.367 0.000 146.385 0.018 ; - END - END r0_rd_out[34] - PIN r0_rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 146.871 0.000 146.889 0.018 ; - END - END r0_rd_out[35] - PIN r0_rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 147.375 0.000 147.393 0.018 ; - END - END r0_rd_out[36] - PIN r0_rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 147.879 0.000 147.897 0.018 ; - END - END r0_rd_out[37] - PIN r0_rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 148.383 0.000 148.401 0.018 ; - END - END r0_rd_out[38] - PIN r0_rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 148.887 0.000 148.905 0.018 ; - END - END r0_rd_out[39] - PIN r0_rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 149.391 0.000 149.409 0.018 ; - END - END r0_rd_out[40] - PIN r0_rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 149.895 0.000 149.913 0.018 ; - END - END r0_rd_out[41] - PIN r0_rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 150.399 0.000 150.417 0.018 ; - END - END r0_rd_out[42] - PIN r0_rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 150.903 0.000 150.921 0.018 ; - END - END r0_rd_out[43] - PIN r0_rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 151.407 0.000 151.425 0.018 ; - END - END r0_rd_out[44] - PIN r0_rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 151.911 0.000 151.929 0.018 ; - END - END r0_rd_out[45] - PIN r0_rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 152.415 0.000 152.433 0.018 ; - END - END r0_rd_out[46] - PIN r0_rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 152.919 0.000 152.937 0.018 ; - END - END r0_rd_out[47] - PIN r0_rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 153.423 0.000 153.441 0.018 ; - END - END r0_rd_out[48] - PIN r0_rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 153.927 0.000 153.945 0.018 ; - END - END r0_rd_out[49] - PIN r0_rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 154.431 0.000 154.449 0.018 ; - END - END r0_rd_out[50] - PIN r0_rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 154.935 0.000 154.953 0.018 ; - END - END r0_rd_out[51] - PIN r0_rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 155.439 0.000 155.457 0.018 ; - END - END r0_rd_out[52] - PIN r0_rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 155.943 0.000 155.961 0.018 ; - END - END r0_rd_out[53] - PIN r0_rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 156.447 0.000 156.465 0.018 ; - END - END r0_rd_out[54] - PIN r0_rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 156.951 0.000 156.969 0.018 ; - END - END r0_rd_out[55] - PIN r0_rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 157.455 0.000 157.473 0.018 ; - END - END r0_rd_out[56] - PIN r0_rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 157.959 0.000 157.977 0.018 ; - END - END r0_rd_out[57] - PIN r0_rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 158.463 0.000 158.481 0.018 ; - END - END r0_rd_out[58] - PIN r0_rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 158.967 0.000 158.985 0.018 ; - END - END r0_rd_out[59] - PIN r0_rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 159.471 0.000 159.489 0.018 ; - END - END r0_rd_out[60] - PIN r0_rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 159.975 0.000 159.993 0.018 ; - END - END r0_rd_out[61] - PIN r0_rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 160.479 0.000 160.497 0.018 ; - END - END r0_rd_out[62] - PIN r0_rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 160.983 0.000 161.001 0.018 ; - END - END r0_rd_out[63] - PIN r0_rd_out[64] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 161.487 0.000 161.505 0.018 ; - END - END r0_rd_out[64] - PIN r0_rd_out[65] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 161.991 0.000 162.009 0.018 ; - END - END r0_rd_out[65] - PIN r0_rd_out[66] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 162.495 0.000 162.513 0.018 ; - END - END r0_rd_out[66] - PIN r0_rd_out[67] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 162.999 0.000 163.017 0.018 ; - END - END r0_rd_out[67] - PIN r0_rd_out[68] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 163.503 0.000 163.521 0.018 ; - END - END r0_rd_out[68] - PIN r0_rd_out[69] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 164.007 0.000 164.025 0.018 ; - END - END r0_rd_out[69] - PIN r0_rd_out[70] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 164.511 0.000 164.529 0.018 ; - END - END r0_rd_out[70] - PIN r0_rd_out[71] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 165.015 0.000 165.033 0.018 ; - END - END r0_rd_out[71] - PIN r0_rd_out[72] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 165.519 0.000 165.537 0.018 ; - END - END r0_rd_out[72] - PIN r0_rd_out[73] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 166.023 0.000 166.041 0.018 ; - END - END r0_rd_out[73] - PIN r0_rd_out[74] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 166.527 0.000 166.545 0.018 ; - END - END r0_rd_out[74] - PIN r0_rd_out[75] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 167.031 0.000 167.049 0.018 ; - END - END r0_rd_out[75] - PIN r0_rd_out[76] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 167.535 0.000 167.553 0.018 ; - END - END r0_rd_out[76] - PIN r0_rd_out[77] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 168.039 0.000 168.057 0.018 ; - END - END r0_rd_out[77] - PIN r0_rd_out[78] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 168.543 0.000 168.561 0.018 ; - END - END r0_rd_out[78] - PIN r0_rd_out[79] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 169.047 0.000 169.065 0.018 ; - END - END r0_rd_out[79] - PIN r0_rd_out[80] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 169.551 0.000 169.569 0.018 ; - END - END r0_rd_out[80] - PIN r0_rd_out[81] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 170.055 0.000 170.073 0.018 ; - END - END r0_rd_out[81] - PIN r0_rd_out[82] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 170.559 0.000 170.577 0.018 ; - END - END r0_rd_out[82] - PIN r0_rd_out[83] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 171.063 0.000 171.081 0.018 ; - END - END r0_rd_out[83] - PIN r0_rd_out[84] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 171.567 0.000 171.585 0.018 ; - END - END r0_rd_out[84] - PIN r0_rd_out[85] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 172.071 0.000 172.089 0.018 ; - END - END r0_rd_out[85] - PIN r0_rd_out[86] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 172.575 0.000 172.593 0.018 ; - END - END r0_rd_out[86] - PIN r0_rd_out[87] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 173.079 0.000 173.097 0.018 ; - END - END r0_rd_out[87] - PIN r0_rd_out[88] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 173.583 0.000 173.601 0.018 ; - END - END r0_rd_out[88] - PIN r0_rd_out[89] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 174.087 0.000 174.105 0.018 ; - END - END r0_rd_out[89] - PIN r0_rd_out[90] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 174.591 0.000 174.609 0.018 ; - END - END r0_rd_out[90] - PIN r0_rd_out[91] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 175.095 0.000 175.113 0.018 ; - END - END r0_rd_out[91] - PIN r0_rd_out[92] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 175.599 0.000 175.617 0.018 ; - END - END r0_rd_out[92] - PIN r0_rd_out[93] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 176.103 0.000 176.121 0.018 ; - END - END r0_rd_out[93] - PIN r0_rd_out[94] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 176.607 0.000 176.625 0.018 ; - END - END r0_rd_out[94] - PIN r0_rd_out[95] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 177.111 0.000 177.129 0.018 ; - END - END r0_rd_out[95] - PIN r0_rd_out[96] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 177.615 0.000 177.633 0.018 ; - END - END r0_rd_out[96] - PIN r0_rd_out[97] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 178.119 0.000 178.137 0.018 ; - END - END r0_rd_out[97] - PIN r0_rd_out[98] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 178.623 0.000 178.641 0.018 ; - END - END r0_rd_out[98] - PIN r0_rd_out[99] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 179.127 0.000 179.145 0.018 ; - END - END r0_rd_out[99] - PIN r0_rd_out[100] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 179.631 0.000 179.649 0.018 ; - END - END r0_rd_out[100] - PIN r0_rd_out[101] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 180.135 0.000 180.153 0.018 ; - END - END r0_rd_out[101] - PIN r0_rd_out[102] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 180.639 0.000 180.657 0.018 ; - END - END r0_rd_out[102] - PIN r0_rd_out[103] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 181.143 0.000 181.161 0.018 ; - END - END r0_rd_out[103] - PIN r0_rd_out[104] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 181.647 0.000 181.665 0.018 ; - END - END r0_rd_out[104] - PIN r0_rd_out[105] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 182.151 0.000 182.169 0.018 ; - END - END r0_rd_out[105] - PIN r0_rd_out[106] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 182.655 0.000 182.673 0.018 ; - END - END r0_rd_out[106] - PIN r0_rd_out[107] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 183.159 0.000 183.177 0.018 ; - END - END r0_rd_out[107] - PIN r0_rd_out[108] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 183.663 0.000 183.681 0.018 ; - END - END r0_rd_out[108] - PIN r0_rd_out[109] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 184.167 0.000 184.185 0.018 ; - END - END r0_rd_out[109] - PIN r0_rd_out[110] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 184.671 0.000 184.689 0.018 ; - END - END r0_rd_out[110] - PIN r0_rd_out[111] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 185.175 0.000 185.193 0.018 ; - END - END r0_rd_out[111] - PIN r0_rd_out[112] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 185.679 0.000 185.697 0.018 ; - END - END r0_rd_out[112] - PIN r0_rd_out[113] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 186.183 0.000 186.201 0.018 ; - END - END r0_rd_out[113] - PIN r0_rd_out[114] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 186.687 0.000 186.705 0.018 ; - END - END r0_rd_out[114] - PIN r0_rd_out[115] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 187.191 0.000 187.209 0.018 ; - END - END r0_rd_out[115] - PIN r0_rd_out[116] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 187.695 0.000 187.713 0.018 ; - END - END r0_rd_out[116] - PIN r0_rd_out[117] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 188.199 0.000 188.217 0.018 ; - END - END r0_rd_out[117] - PIN r0_rd_out[118] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 188.703 0.000 188.721 0.018 ; - END - END r0_rd_out[118] - PIN r0_rd_out[119] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 189.207 0.000 189.225 0.018 ; - END - END r0_rd_out[119] - PIN r0_rd_out[120] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 189.711 0.000 189.729 0.018 ; - END - END r0_rd_out[120] - PIN r0_rd_out[121] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 190.215 0.000 190.233 0.018 ; - END - END r0_rd_out[121] - PIN r0_rd_out[122] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 190.719 0.000 190.737 0.018 ; - END - END r0_rd_out[122] - PIN r0_rd_out[123] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 191.223 0.000 191.241 0.018 ; - END - END r0_rd_out[123] - PIN r0_rd_out[124] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 191.727 0.000 191.745 0.018 ; - END - END r0_rd_out[124] - PIN r0_rd_out[125] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 192.231 0.000 192.249 0.018 ; - END - END r0_rd_out[125] - PIN r0_rd_out[126] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 192.735 0.000 192.753 0.018 ; - END - END r0_rd_out[126] - PIN r0_rd_out[127] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 193.239 0.000 193.257 0.018 ; - END - END r0_rd_out[127] - PIN r0_rd_out[128] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 193.743 0.000 193.761 0.018 ; - END - END r0_rd_out[128] - PIN r0_rd_out[129] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 194.247 0.000 194.265 0.018 ; - END - END r0_rd_out[129] - PIN r0_rd_out[130] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 194.751 0.000 194.769 0.018 ; - END - END r0_rd_out[130] - PIN r0_rd_out[131] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 195.255 0.000 195.273 0.018 ; - END - END r0_rd_out[131] - PIN r0_rd_out[132] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 195.759 0.000 195.777 0.018 ; - END - END r0_rd_out[132] - PIN r0_rd_out[133] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 196.263 0.000 196.281 0.018 ; - END - END r0_rd_out[133] - PIN r0_rd_out[134] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 196.767 0.000 196.785 0.018 ; - END - END r0_rd_out[134] - PIN r0_rd_out[135] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 197.271 0.000 197.289 0.018 ; - END - END r0_rd_out[135] - PIN r0_rd_out[136] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 197.775 0.000 197.793 0.018 ; - END - END r0_rd_out[136] - PIN r0_rd_out[137] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 198.279 0.000 198.297 0.018 ; - END - END r0_rd_out[137] - PIN r0_rd_out[138] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 198.783 0.000 198.801 0.018 ; - END - END r0_rd_out[138] - PIN r0_rd_out[139] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 199.287 0.000 199.305 0.018 ; - END - END r0_rd_out[139] - PIN r0_rd_out[140] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 199.791 0.000 199.809 0.018 ; - END - END r0_rd_out[140] - PIN r0_rd_out[141] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 200.295 0.000 200.313 0.018 ; - END - END r0_rd_out[141] - PIN r0_rd_out[142] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 200.799 0.000 200.817 0.018 ; - END - END r0_rd_out[142] - PIN r0_rd_out[143] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 201.303 0.000 201.321 0.018 ; - END - END r0_rd_out[143] - PIN r0_rd_out[144] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 201.807 0.000 201.825 0.018 ; - END - END r0_rd_out[144] - PIN r0_rd_out[145] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 202.311 0.000 202.329 0.018 ; - END - END r0_rd_out[145] - PIN r0_rd_out[146] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 202.815 0.000 202.833 0.018 ; - END - END r0_rd_out[146] - PIN r0_rd_out[147] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 203.319 0.000 203.337 0.018 ; - END - END r0_rd_out[147] - PIN r0_rd_out[148] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 203.823 0.000 203.841 0.018 ; - END - END r0_rd_out[148] - PIN r0_rd_out[149] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 204.327 0.000 204.345 0.018 ; - END - END r0_rd_out[149] - PIN r0_rd_out[150] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 204.831 0.000 204.849 0.018 ; - END - END r0_rd_out[150] - PIN r0_rd_out[151] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 205.335 0.000 205.353 0.018 ; - END - END r0_rd_out[151] - PIN r0_rd_out[152] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 205.839 0.000 205.857 0.018 ; - END - END r0_rd_out[152] - PIN r0_rd_out[153] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 206.343 0.000 206.361 0.018 ; - END - END r0_rd_out[153] - PIN r0_rd_out[154] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 206.847 0.000 206.865 0.018 ; - END - END r0_rd_out[154] - PIN r0_rd_out[155] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 207.351 0.000 207.369 0.018 ; - END - END r0_rd_out[155] - PIN r0_rd_out[156] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 207.855 0.000 207.873 0.018 ; - END - END r0_rd_out[156] - PIN r0_rd_out[157] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 208.359 0.000 208.377 0.018 ; - END - END r0_rd_out[157] - PIN r0_rd_out[158] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 208.863 0.000 208.881 0.018 ; - END - END r0_rd_out[158] - PIN r0_rd_out[159] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 209.367 0.000 209.385 0.018 ; - END - END r0_rd_out[159] - PIN r0_rd_out[160] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 209.871 0.000 209.889 0.018 ; - END - END r0_rd_out[160] - PIN r0_rd_out[161] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 210.375 0.000 210.393 0.018 ; - END - END r0_rd_out[161] - PIN r0_rd_out[162] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 210.879 0.000 210.897 0.018 ; - END - END r0_rd_out[162] - PIN r0_rd_out[163] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 211.383 0.000 211.401 0.018 ; - END - END r0_rd_out[163] - PIN r0_rd_out[164] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 211.887 0.000 211.905 0.018 ; - END - END r0_rd_out[164] - PIN r0_rd_out[165] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 212.391 0.000 212.409 0.018 ; - END - END r0_rd_out[165] - PIN r0_rd_out[166] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 212.895 0.000 212.913 0.018 ; - END - END r0_rd_out[166] - PIN r0_rd_out[167] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 213.399 0.000 213.417 0.018 ; - END - END r0_rd_out[167] - PIN r0_rd_out[168] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 213.903 0.000 213.921 0.018 ; - END - END r0_rd_out[168] - PIN r0_rd_out[169] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 214.407 0.000 214.425 0.018 ; - END - END r0_rd_out[169] - PIN r0_rd_out[170] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 214.911 0.000 214.929 0.018 ; - END - END r0_rd_out[170] - PIN r0_rd_out[171] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 215.415 0.000 215.433 0.018 ; - END - END r0_rd_out[171] - PIN r0_rd_out[172] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 215.919 0.000 215.937 0.018 ; - END - END r0_rd_out[172] - PIN r0_rd_out[173] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 216.423 0.000 216.441 0.018 ; - END - END r0_rd_out[173] - PIN r0_rd_out[174] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 216.927 0.000 216.945 0.018 ; - END - END r0_rd_out[174] - PIN r0_rd_out[175] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 217.431 0.000 217.449 0.018 ; - END - END r0_rd_out[175] - PIN r0_rd_out[176] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 217.935 0.000 217.953 0.018 ; - END - END r0_rd_out[176] - PIN r0_rd_out[177] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 218.439 0.000 218.457 0.018 ; - END - END r0_rd_out[177] - PIN r0_rd_out[178] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 218.943 0.000 218.961 0.018 ; - END - END r0_rd_out[178] - PIN r0_rd_out[179] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 219.447 0.000 219.465 0.018 ; - END - END r0_rd_out[179] - PIN r0_rd_out[180] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 219.951 0.000 219.969 0.018 ; - END - END r0_rd_out[180] - PIN r0_rd_out[181] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 220.455 0.000 220.473 0.018 ; - END - END r0_rd_out[181] - PIN r0_rd_out[182] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 220.959 0.000 220.977 0.018 ; - END - END r0_rd_out[182] - PIN r0_rd_out[183] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 221.463 0.000 221.481 0.018 ; - END - END r0_rd_out[183] - PIN r0_rd_out[184] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 221.967 0.000 221.985 0.018 ; - END - END r0_rd_out[184] - PIN r0_rd_out[185] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 222.471 0.000 222.489 0.018 ; - END - END r0_rd_out[185] - PIN r0_rd_out[186] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 222.975 0.000 222.993 0.018 ; - END - END r0_rd_out[186] - PIN r0_rd_out[187] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 223.479 0.000 223.497 0.018 ; - END - END r0_rd_out[187] - PIN r0_rd_out[188] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 223.983 0.000 224.001 0.018 ; - END - END r0_rd_out[188] - PIN r0_rd_out[189] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 224.487 0.000 224.505 0.018 ; - END - END r0_rd_out[189] - PIN r0_rd_out[190] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 224.991 0.000 225.009 0.018 ; - END - END r0_rd_out[190] - PIN r0_rd_out[191] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 225.495 0.000 225.513 0.018 ; - END - END r0_rd_out[191] - PIN r0_rd_out[192] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 225.999 0.000 226.017 0.018 ; - END - END r0_rd_out[192] - PIN r0_rd_out[193] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 226.503 0.000 226.521 0.018 ; - END - END r0_rd_out[193] - PIN r0_rd_out[194] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 227.007 0.000 227.025 0.018 ; - END - END r0_rd_out[194] - PIN r0_rd_out[195] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 227.511 0.000 227.529 0.018 ; - END - END r0_rd_out[195] - PIN r0_rd_out[196] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 228.015 0.000 228.033 0.018 ; - END - END r0_rd_out[196] - PIN r0_rd_out[197] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 228.519 0.000 228.537 0.018 ; - END - END r0_rd_out[197] - PIN r0_rd_out[198] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 229.023 0.000 229.041 0.018 ; - END - END r0_rd_out[198] - PIN r0_rd_out[199] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 229.527 0.000 229.545 0.018 ; - END - END r0_rd_out[199] - PIN r0_rd_out[200] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 230.031 0.000 230.049 0.018 ; - END - END r0_rd_out[200] - PIN r0_rd_out[201] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 230.535 0.000 230.553 0.018 ; - END - END r0_rd_out[201] - PIN r0_rd_out[202] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 231.039 0.000 231.057 0.018 ; - END - END r0_rd_out[202] - PIN r0_rd_out[203] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 231.543 0.000 231.561 0.018 ; - END - END r0_rd_out[203] - PIN r0_rd_out[204] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 232.047 0.000 232.065 0.018 ; - END - END r0_rd_out[204] - PIN r0_rd_out[205] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 232.551 0.000 232.569 0.018 ; - END - END r0_rd_out[205] - PIN r0_rd_out[206] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 233.055 0.000 233.073 0.018 ; - END - END r0_rd_out[206] - PIN r0_rd_out[207] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 233.559 0.000 233.577 0.018 ; - END - END r0_rd_out[207] - PIN r0_rd_out[208] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 234.063 0.000 234.081 0.018 ; - END - END r0_rd_out[208] - PIN r0_rd_out[209] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 234.567 0.000 234.585 0.018 ; - END - END r0_rd_out[209] - PIN r0_rd_out[210] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 235.071 0.000 235.089 0.018 ; - END - END r0_rd_out[210] - PIN r0_rd_out[211] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 235.575 0.000 235.593 0.018 ; - END - END r0_rd_out[211] - PIN r0_rd_out[212] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 236.079 0.000 236.097 0.018 ; - END - END r0_rd_out[212] - PIN r0_rd_out[213] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 236.583 0.000 236.601 0.018 ; - END - END r0_rd_out[213] - PIN r0_rd_out[214] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 237.087 0.000 237.105 0.018 ; - END - END r0_rd_out[214] - PIN r0_rd_out[215] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 237.591 0.000 237.609 0.018 ; - END - END r0_rd_out[215] - PIN r0_rd_out[216] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 238.095 0.000 238.113 0.018 ; - END - END r0_rd_out[216] - PIN r0_rd_out[217] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 238.599 0.000 238.617 0.018 ; - END - END r0_rd_out[217] - PIN r0_rd_out[218] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 239.103 0.000 239.121 0.018 ; - END - END r0_rd_out[218] - PIN r0_rd_out[219] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 239.607 0.000 239.625 0.018 ; - END - END r0_rd_out[219] - PIN r0_rd_out[220] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 240.111 0.000 240.129 0.018 ; - END - END r0_rd_out[220] - PIN r0_rd_out[221] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 240.615 0.000 240.633 0.018 ; - END - END r0_rd_out[221] - PIN r0_rd_out[222] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 241.119 0.000 241.137 0.018 ; - END - END r0_rd_out[222] - PIN r0_rd_out[223] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 241.623 0.000 241.641 0.018 ; - END - END r0_rd_out[223] - PIN r0_rd_out[224] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 242.127 0.000 242.145 0.018 ; - END - END r0_rd_out[224] - PIN r0_rd_out[225] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 242.631 0.000 242.649 0.018 ; - END - END r0_rd_out[225] - PIN r0_rd_out[226] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 243.135 0.000 243.153 0.018 ; - END - END r0_rd_out[226] - PIN r0_rd_out[227] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 243.639 0.000 243.657 0.018 ; - END - END r0_rd_out[227] - PIN r0_rd_out[228] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 244.143 0.000 244.161 0.018 ; - END - END r0_rd_out[228] - PIN r0_rd_out[229] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 244.647 0.000 244.665 0.018 ; - END - END r0_rd_out[229] - PIN r0_rd_out[230] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 245.151 0.000 245.169 0.018 ; - END - END r0_rd_out[230] - PIN r0_rd_out[231] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 245.655 0.000 245.673 0.018 ; - END - END r0_rd_out[231] - PIN r0_rd_out[232] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 246.159 0.000 246.177 0.018 ; - END - END r0_rd_out[232] - PIN r0_rd_out[233] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 246.663 0.000 246.681 0.018 ; - END - END r0_rd_out[233] - PIN r0_rd_out[234] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 247.167 0.000 247.185 0.018 ; - END - END r0_rd_out[234] - PIN r0_rd_out[235] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 247.671 0.000 247.689 0.018 ; - END - END r0_rd_out[235] - PIN r0_rd_out[236] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 248.175 0.000 248.193 0.018 ; - END - END r0_rd_out[236] - PIN r0_rd_out[237] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 248.679 0.000 248.697 0.018 ; - END - END r0_rd_out[237] - PIN r0_rd_out[238] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 249.183 0.000 249.201 0.018 ; - END - END r0_rd_out[238] - PIN r0_rd_out[239] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 249.687 0.000 249.705 0.018 ; - END - END r0_rd_out[239] - PIN r0_rd_out[240] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 250.191 0.000 250.209 0.018 ; - END - END r0_rd_out[240] - PIN r0_rd_out[241] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 250.695 0.000 250.713 0.018 ; - END - END r0_rd_out[241] - PIN r0_rd_out[242] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 251.199 0.000 251.217 0.018 ; - END - END r0_rd_out[242] - PIN r0_rd_out[243] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 251.703 0.000 251.721 0.018 ; - END - END r0_rd_out[243] - PIN r0_rd_out[244] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 252.207 0.000 252.225 0.018 ; - END - END r0_rd_out[244] - PIN r0_rd_out[245] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 252.711 0.000 252.729 0.018 ; - END - END r0_rd_out[245] - PIN r0_rd_out[246] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 253.215 0.000 253.233 0.018 ; - END - END r0_rd_out[246] - PIN r0_rd_out[247] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 253.719 0.000 253.737 0.018 ; - END - END r0_rd_out[247] - PIN r0_rd_out[248] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 254.223 0.000 254.241 0.018 ; - END - END r0_rd_out[248] - PIN r0_rd_out[249] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 254.727 0.000 254.745 0.018 ; - END - END r0_rd_out[249] - PIN r0_rd_out[250] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 255.231 0.000 255.249 0.018 ; - END - END r0_rd_out[250] - PIN r0_rd_out[251] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 255.735 0.000 255.753 0.018 ; - END - END r0_rd_out[251] - PIN r0_rd_out[252] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 256.239 0.000 256.257 0.018 ; - END - END r0_rd_out[252] - PIN r0_rd_out[253] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 256.743 0.000 256.761 0.018 ; - END - END r0_rd_out[253] - PIN r0_rd_out[254] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 257.247 0.000 257.265 0.018 ; - END - END r0_rd_out[254] - PIN r0_rd_out[255] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 257.751 0.000 257.769 0.018 ; - END - END r0_rd_out[255] - PIN r0_rd_out[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 0.207 20.718 0.225 20.736 ; - END - END r0_rd_out[256] - PIN r0_rd_out[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 1.215 20.718 1.233 20.736 ; - END - END r0_rd_out[257] - PIN r0_rd_out[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 2.223 20.718 2.241 20.736 ; - END - END r0_rd_out[258] - PIN r0_rd_out[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 3.231 20.718 3.249 20.736 ; - END - END r0_rd_out[259] - PIN r0_rd_out[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 4.239 20.718 4.257 20.736 ; - END - END r0_rd_out[260] - PIN r0_rd_out[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 5.247 20.718 5.265 20.736 ; - END - END r0_rd_out[261] - PIN r0_rd_out[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 6.255 20.718 6.273 20.736 ; - END - END r0_rd_out[262] - PIN r0_rd_out[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 7.263 20.718 7.281 20.736 ; - END - END r0_rd_out[263] - PIN r0_rd_out[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 8.271 20.718 8.289 20.736 ; - END - END r0_rd_out[264] - PIN r0_rd_out[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 9.279 20.718 9.297 20.736 ; - END - END r0_rd_out[265] - PIN r0_rd_out[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 10.287 20.718 10.305 20.736 ; - END - END r0_rd_out[266] - PIN r0_rd_out[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 11.295 20.718 11.313 20.736 ; - END - END r0_rd_out[267] - PIN r0_rd_out[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 12.303 20.718 12.321 20.736 ; - END - END r0_rd_out[268] - PIN r0_rd_out[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 13.311 20.718 13.329 20.736 ; - END - END r0_rd_out[269] - PIN r0_rd_out[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 14.319 20.718 14.337 20.736 ; - END - END r0_rd_out[270] - PIN r0_rd_out[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 15.327 20.718 15.345 20.736 ; - END - END r0_rd_out[271] - PIN r0_rd_out[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 16.335 20.718 16.353 20.736 ; - END - END r0_rd_out[272] - PIN r0_rd_out[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 17.343 20.718 17.361 20.736 ; - END - END r0_rd_out[273] - PIN r0_rd_out[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 18.351 20.718 18.369 20.736 ; - END - END r0_rd_out[274] - PIN r0_rd_out[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 19.359 20.718 19.377 20.736 ; - END - END r0_rd_out[275] - PIN r0_rd_out[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 20.367 20.718 20.385 20.736 ; - END - END r0_rd_out[276] - PIN r0_rd_out[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 21.375 20.718 21.393 20.736 ; - END - END r0_rd_out[277] - PIN r0_rd_out[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 22.383 20.718 22.401 20.736 ; - END - END r0_rd_out[278] - PIN r0_rd_out[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 23.391 20.718 23.409 20.736 ; - END - END r0_rd_out[279] - PIN r0_rd_out[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 24.399 20.718 24.417 20.736 ; - END - END r0_rd_out[280] - PIN r0_rd_out[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 25.407 20.718 25.425 20.736 ; - END - END r0_rd_out[281] - PIN r0_rd_out[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 26.415 20.718 26.433 20.736 ; - END - END r0_rd_out[282] - PIN r0_rd_out[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 27.423 20.718 27.441 20.736 ; - END - END r0_rd_out[283] - PIN r0_rd_out[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 28.431 20.718 28.449 20.736 ; - END - END r0_rd_out[284] - PIN r0_rd_out[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 29.439 20.718 29.457 20.736 ; - END - END r0_rd_out[285] - PIN r0_rd_out[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 30.447 20.718 30.465 20.736 ; - END - END r0_rd_out[286] - PIN r0_rd_out[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 31.455 20.718 31.473 20.736 ; - END - END r0_rd_out[287] - PIN r0_rd_out[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 32.463 20.718 32.481 20.736 ; - END - END r0_rd_out[288] - PIN r0_rd_out[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 33.471 20.718 33.489 20.736 ; - END - END r0_rd_out[289] - PIN r0_rd_out[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 34.479 20.718 34.497 20.736 ; - END - END r0_rd_out[290] - PIN r0_rd_out[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 35.487 20.718 35.505 20.736 ; - END - END r0_rd_out[291] - PIN r0_rd_out[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 36.495 20.718 36.513 20.736 ; - END - END r0_rd_out[292] - PIN r0_rd_out[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 37.503 20.718 37.521 20.736 ; - END - END r0_rd_out[293] - PIN r0_rd_out[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 38.511 20.718 38.529 20.736 ; - END - END r0_rd_out[294] - PIN r0_rd_out[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 39.519 20.718 39.537 20.736 ; - END - END r0_rd_out[295] - PIN r0_rd_out[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 40.527 20.718 40.545 20.736 ; - END - END r0_rd_out[296] - PIN r0_rd_out[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 41.535 20.718 41.553 20.736 ; - END - END r0_rd_out[297] - PIN r0_rd_out[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 42.543 20.718 42.561 20.736 ; - END - END r0_rd_out[298] - PIN r0_rd_out[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 43.551 20.718 43.569 20.736 ; - END - END r0_rd_out[299] - PIN r0_rd_out[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 44.559 20.718 44.577 20.736 ; - END - END r0_rd_out[300] - PIN r0_rd_out[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 45.567 20.718 45.585 20.736 ; - END - END r0_rd_out[301] - PIN r0_rd_out[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 46.575 20.718 46.593 20.736 ; - END - END r0_rd_out[302] - PIN r0_rd_out[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 47.583 20.718 47.601 20.736 ; - END - END r0_rd_out[303] - PIN r0_rd_out[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 48.591 20.718 48.609 20.736 ; - END - END r0_rd_out[304] - PIN r0_rd_out[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 49.599 20.718 49.617 20.736 ; - END - END r0_rd_out[305] - PIN r0_rd_out[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 50.607 20.718 50.625 20.736 ; - END - END r0_rd_out[306] - PIN r0_rd_out[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 51.615 20.718 51.633 20.736 ; - END - END r0_rd_out[307] - PIN r0_rd_out[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 52.623 20.718 52.641 20.736 ; - END - END r0_rd_out[308] - PIN r0_rd_out[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 53.631 20.718 53.649 20.736 ; - END - END r0_rd_out[309] - PIN r0_rd_out[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 54.639 20.718 54.657 20.736 ; - END - END r0_rd_out[310] - PIN r0_rd_out[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 55.647 20.718 55.665 20.736 ; - END - END r0_rd_out[311] - PIN r0_rd_out[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 56.655 20.718 56.673 20.736 ; - END - END r0_rd_out[312] - PIN r0_rd_out[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 57.663 20.718 57.681 20.736 ; - END - END r0_rd_out[313] - PIN r0_rd_out[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 58.671 20.718 58.689 20.736 ; - END - END r0_rd_out[314] - PIN r0_rd_out[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 59.679 20.718 59.697 20.736 ; - END - END r0_rd_out[315] - PIN r0_rd_out[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 60.687 20.718 60.705 20.736 ; - END - END r0_rd_out[316] - PIN r0_rd_out[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 61.695 20.718 61.713 20.736 ; - END - END r0_rd_out[317] - PIN r0_rd_out[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 62.703 20.718 62.721 20.736 ; - END - END r0_rd_out[318] - PIN r0_rd_out[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 63.711 20.718 63.729 20.736 ; - END - END r0_rd_out[319] - PIN r0_rd_out[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 64.719 20.718 64.737 20.736 ; - END - END r0_rd_out[320] - PIN r0_rd_out[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 65.727 20.718 65.745 20.736 ; - END - END r0_rd_out[321] - PIN r0_rd_out[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 66.735 20.718 66.753 20.736 ; - END - END r0_rd_out[322] - PIN r0_rd_out[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 67.743 20.718 67.761 20.736 ; - END - END r0_rd_out[323] - PIN r0_rd_out[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 68.751 20.718 68.769 20.736 ; - END - END r0_rd_out[324] - PIN r0_rd_out[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 69.759 20.718 69.777 20.736 ; - END - END r0_rd_out[325] - PIN r0_rd_out[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 70.767 20.718 70.785 20.736 ; - END - END r0_rd_out[326] - PIN r0_rd_out[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 71.775 20.718 71.793 20.736 ; - END - END r0_rd_out[327] - PIN r0_rd_out[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 72.783 20.718 72.801 20.736 ; - END - END r0_rd_out[328] - PIN r0_rd_out[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 73.791 20.718 73.809 20.736 ; - END - END r0_rd_out[329] - PIN r0_rd_out[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 74.799 20.718 74.817 20.736 ; - END - END r0_rd_out[330] - PIN r0_rd_out[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 75.807 20.718 75.825 20.736 ; - END - END r0_rd_out[331] - PIN r0_rd_out[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 76.815 20.718 76.833 20.736 ; - END - END r0_rd_out[332] - PIN r0_rd_out[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 77.823 20.718 77.841 20.736 ; - END - END r0_rd_out[333] - PIN r0_rd_out[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 78.831 20.718 78.849 20.736 ; - END - END r0_rd_out[334] - PIN r0_rd_out[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 79.839 20.718 79.857 20.736 ; - END - END r0_rd_out[335] - PIN r0_rd_out[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 80.847 20.718 80.865 20.736 ; - END - END r0_rd_out[336] - PIN r0_rd_out[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 81.855 20.718 81.873 20.736 ; - END - END r0_rd_out[337] - PIN r0_rd_out[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 82.863 20.718 82.881 20.736 ; - END - END r0_rd_out[338] - PIN r0_rd_out[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 83.871 20.718 83.889 20.736 ; - END - END r0_rd_out[339] - PIN r0_rd_out[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 84.879 20.718 84.897 20.736 ; - END - END r0_rd_out[340] - PIN r0_rd_out[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 85.887 20.718 85.905 20.736 ; - END - END r0_rd_out[341] - PIN r0_rd_out[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 86.895 20.718 86.913 20.736 ; - END - END r0_rd_out[342] - PIN r0_rd_out[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 87.903 20.718 87.921 20.736 ; - END - END r0_rd_out[343] - PIN r0_rd_out[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 88.911 20.718 88.929 20.736 ; - END - END r0_rd_out[344] - PIN r0_rd_out[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 89.919 20.718 89.937 20.736 ; - END - END r0_rd_out[345] - PIN r0_rd_out[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 90.927 20.718 90.945 20.736 ; - END - END r0_rd_out[346] - PIN r0_rd_out[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 91.935 20.718 91.953 20.736 ; - END - END r0_rd_out[347] - PIN r0_rd_out[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 92.943 20.718 92.961 20.736 ; - END - END r0_rd_out[348] - PIN r0_rd_out[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 93.951 20.718 93.969 20.736 ; - END - END r0_rd_out[349] - PIN r0_rd_out[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 94.959 20.718 94.977 20.736 ; - END - END r0_rd_out[350] - PIN r0_rd_out[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 95.967 20.718 95.985 20.736 ; - END - END r0_rd_out[351] - PIN r0_rd_out[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 96.975 20.718 96.993 20.736 ; - END - END r0_rd_out[352] - PIN r0_rd_out[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 97.983 20.718 98.001 20.736 ; - END - END r0_rd_out[353] - PIN r0_rd_out[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 98.991 20.718 99.009 20.736 ; - END - END r0_rd_out[354] - PIN r0_rd_out[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 99.999 20.718 100.017 20.736 ; - END - END r0_rd_out[355] - PIN r0_rd_out[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 101.007 20.718 101.025 20.736 ; - END - END r0_rd_out[356] - PIN r0_rd_out[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 102.015 20.718 102.033 20.736 ; - END - END r0_rd_out[357] - PIN r0_rd_out[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 103.023 20.718 103.041 20.736 ; - END - END r0_rd_out[358] - PIN r0_rd_out[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 104.031 20.718 104.049 20.736 ; - END - END r0_rd_out[359] - PIN r0_rd_out[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 105.039 20.718 105.057 20.736 ; - END - END r0_rd_out[360] - PIN r0_rd_out[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 106.047 20.718 106.065 20.736 ; - END - END r0_rd_out[361] - PIN r0_rd_out[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 107.055 20.718 107.073 20.736 ; - END - END r0_rd_out[362] - PIN r0_rd_out[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 108.063 20.718 108.081 20.736 ; - END - END r0_rd_out[363] - PIN r0_rd_out[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 109.071 20.718 109.089 20.736 ; - END - END r0_rd_out[364] - PIN r0_rd_out[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 110.079 20.718 110.097 20.736 ; - END - END r0_rd_out[365] - PIN r0_rd_out[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 111.087 20.718 111.105 20.736 ; - END - END r0_rd_out[366] - PIN r0_rd_out[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 112.095 20.718 112.113 20.736 ; - END - END r0_rd_out[367] - PIN r0_rd_out[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 113.103 20.718 113.121 20.736 ; - END - END r0_rd_out[368] - PIN r0_rd_out[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 114.111 20.718 114.129 20.736 ; - END - END r0_rd_out[369] - PIN r0_rd_out[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 115.119 20.718 115.137 20.736 ; - END - END r0_rd_out[370] - PIN r0_rd_out[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 116.127 20.718 116.145 20.736 ; - END - END r0_rd_out[371] - PIN r0_rd_out[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 117.135 20.718 117.153 20.736 ; - END - END r0_rd_out[372] - PIN r0_rd_out[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 118.143 20.718 118.161 20.736 ; - END - END r0_rd_out[373] - PIN r0_rd_out[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 119.151 20.718 119.169 20.736 ; - END - END r0_rd_out[374] - PIN r0_rd_out[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 120.159 20.718 120.177 20.736 ; - END - END r0_rd_out[375] - PIN r0_rd_out[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 121.167 20.718 121.185 20.736 ; - END - END r0_rd_out[376] - PIN r0_rd_out[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 122.175 20.718 122.193 20.736 ; - END - END r0_rd_out[377] - PIN r0_rd_out[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 123.183 20.718 123.201 20.736 ; - END - END r0_rd_out[378] - PIN r0_rd_out[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 124.191 20.718 124.209 20.736 ; - END - END r0_rd_out[379] - PIN r0_rd_out[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 125.199 20.718 125.217 20.736 ; - END - END r0_rd_out[380] - PIN r0_rd_out[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 126.207 20.718 126.225 20.736 ; - END - END r0_rd_out[381] - PIN r0_rd_out[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 127.215 20.718 127.233 20.736 ; - END - END r0_rd_out[382] - PIN r0_rd_out[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 128.223 20.718 128.241 20.736 ; - END - END r0_rd_out[383] - PIN r0_rd_out[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 129.231 20.718 129.249 20.736 ; - END - END r0_rd_out[384] - PIN r0_rd_out[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 130.239 20.718 130.257 20.736 ; - END - END r0_rd_out[385] - PIN r0_rd_out[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 131.247 20.718 131.265 20.736 ; - END - END r0_rd_out[386] - PIN r0_rd_out[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 132.255 20.718 132.273 20.736 ; - END - END r0_rd_out[387] - PIN r0_rd_out[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 133.263 20.718 133.281 20.736 ; - END - END r0_rd_out[388] - PIN r0_rd_out[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 134.271 20.718 134.289 20.736 ; - END - END r0_rd_out[389] - PIN r0_rd_out[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 135.279 20.718 135.297 20.736 ; - END - END r0_rd_out[390] - PIN r0_rd_out[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 136.287 20.718 136.305 20.736 ; - END - END r0_rd_out[391] - PIN r0_rd_out[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 137.295 20.718 137.313 20.736 ; - END - END r0_rd_out[392] - PIN r0_rd_out[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 138.303 20.718 138.321 20.736 ; - END - END r0_rd_out[393] - PIN r0_rd_out[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 139.311 20.718 139.329 20.736 ; - END - END r0_rd_out[394] - PIN r0_rd_out[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 140.319 20.718 140.337 20.736 ; - END - END r0_rd_out[395] - PIN r0_rd_out[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 141.327 20.718 141.345 20.736 ; - END - END r0_rd_out[396] - PIN r0_rd_out[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 142.335 20.718 142.353 20.736 ; - END - END r0_rd_out[397] - PIN r0_rd_out[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 143.343 20.718 143.361 20.736 ; - END - END r0_rd_out[398] - PIN r0_rd_out[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 144.351 20.718 144.369 20.736 ; - END - END r0_rd_out[399] - PIN r0_rd_out[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 145.359 20.718 145.377 20.736 ; - END - END r0_rd_out[400] - PIN r0_rd_out[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 146.367 20.718 146.385 20.736 ; - END - END r0_rd_out[401] - PIN r0_rd_out[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 147.375 20.718 147.393 20.736 ; - END - END r0_rd_out[402] - PIN r0_rd_out[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 148.383 20.718 148.401 20.736 ; - END - END r0_rd_out[403] - PIN r0_rd_out[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 149.391 20.718 149.409 20.736 ; - END - END r0_rd_out[404] - PIN r0_rd_out[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 150.399 20.718 150.417 20.736 ; - END - END r0_rd_out[405] - PIN r0_rd_out[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 151.407 20.718 151.425 20.736 ; - END - END r0_rd_out[406] - PIN r0_rd_out[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 152.415 20.718 152.433 20.736 ; - END - END r0_rd_out[407] - PIN r0_rd_out[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 153.423 20.718 153.441 20.736 ; - END - END r0_rd_out[408] - PIN r0_rd_out[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 154.431 20.718 154.449 20.736 ; - END - END r0_rd_out[409] - PIN r0_rd_out[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 155.439 20.718 155.457 20.736 ; - END - END r0_rd_out[410] - PIN r0_rd_out[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 156.447 20.718 156.465 20.736 ; - END - END r0_rd_out[411] - PIN r0_rd_out[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 157.455 20.718 157.473 20.736 ; - END - END r0_rd_out[412] - PIN r0_rd_out[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 158.463 20.718 158.481 20.736 ; - END - END r0_rd_out[413] - PIN r0_rd_out[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 159.471 20.718 159.489 20.736 ; - END - END r0_rd_out[414] - PIN r0_rd_out[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 160.479 20.718 160.497 20.736 ; - END - END r0_rd_out[415] - PIN r0_rd_out[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 161.487 20.718 161.505 20.736 ; - END - END r0_rd_out[416] - PIN r0_rd_out[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 162.495 20.718 162.513 20.736 ; - END - END r0_rd_out[417] - PIN r0_rd_out[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 163.503 20.718 163.521 20.736 ; - END - END r0_rd_out[418] - PIN r0_rd_out[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 164.511 20.718 164.529 20.736 ; - END - END r0_rd_out[419] - PIN r0_rd_out[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 165.519 20.718 165.537 20.736 ; - END - END r0_rd_out[420] - PIN r0_rd_out[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 166.527 20.718 166.545 20.736 ; - END - END r0_rd_out[421] - PIN r0_rd_out[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 167.535 20.718 167.553 20.736 ; - END - END r0_rd_out[422] - PIN r0_rd_out[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 168.543 20.718 168.561 20.736 ; - END - END r0_rd_out[423] - PIN r0_rd_out[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 169.551 20.718 169.569 20.736 ; - END - END r0_rd_out[424] - PIN r0_rd_out[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 170.559 20.718 170.577 20.736 ; - END - END r0_rd_out[425] - PIN r0_rd_out[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 171.567 20.718 171.585 20.736 ; - END - END r0_rd_out[426] - PIN r0_rd_out[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 172.575 20.718 172.593 20.736 ; - END - END r0_rd_out[427] - PIN r0_rd_out[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 173.583 20.718 173.601 20.736 ; - END - END r0_rd_out[428] - PIN r0_rd_out[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 174.591 20.718 174.609 20.736 ; - END - END r0_rd_out[429] - PIN r0_rd_out[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 175.599 20.718 175.617 20.736 ; - END - END r0_rd_out[430] - PIN r0_rd_out[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 176.607 20.718 176.625 20.736 ; - END - END r0_rd_out[431] - PIN r0_rd_out[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 177.615 20.718 177.633 20.736 ; - END - END r0_rd_out[432] - PIN r0_rd_out[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 178.623 20.718 178.641 20.736 ; - END - END r0_rd_out[433] - PIN r0_rd_out[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 179.631 20.718 179.649 20.736 ; - END - END r0_rd_out[434] - PIN r0_rd_out[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 180.639 20.718 180.657 20.736 ; - END - END r0_rd_out[435] - PIN r0_rd_out[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 181.647 20.718 181.665 20.736 ; - END - END r0_rd_out[436] - PIN r0_rd_out[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 182.655 20.718 182.673 20.736 ; - END - END r0_rd_out[437] - PIN r0_rd_out[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 183.663 20.718 183.681 20.736 ; - END - END r0_rd_out[438] - PIN r0_rd_out[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 184.671 20.718 184.689 20.736 ; - END - END r0_rd_out[439] - PIN r0_rd_out[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 185.679 20.718 185.697 20.736 ; - END - END r0_rd_out[440] - PIN r0_rd_out[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 186.687 20.718 186.705 20.736 ; - END - END r0_rd_out[441] - PIN r0_rd_out[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 187.695 20.718 187.713 20.736 ; - END - END r0_rd_out[442] - PIN r0_rd_out[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 188.703 20.718 188.721 20.736 ; - END - END r0_rd_out[443] - PIN r0_rd_out[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 189.711 20.718 189.729 20.736 ; - END - END r0_rd_out[444] - PIN r0_rd_out[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 190.719 20.718 190.737 20.736 ; - END - END r0_rd_out[445] - PIN r0_rd_out[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 191.727 20.718 191.745 20.736 ; - END - END r0_rd_out[446] - PIN r0_rd_out[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 192.735 20.718 192.753 20.736 ; - END - END r0_rd_out[447] - PIN r0_rd_out[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 193.743 20.718 193.761 20.736 ; - END - END r0_rd_out[448] - PIN r0_rd_out[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 194.751 20.718 194.769 20.736 ; - END - END r0_rd_out[449] - PIN r0_rd_out[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 195.759 20.718 195.777 20.736 ; - END - END r0_rd_out[450] - PIN r0_rd_out[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 196.767 20.718 196.785 20.736 ; - END - END r0_rd_out[451] - PIN r0_rd_out[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 197.775 20.718 197.793 20.736 ; - END - END r0_rd_out[452] - PIN r0_rd_out[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 198.783 20.718 198.801 20.736 ; - END - END r0_rd_out[453] - PIN r0_rd_out[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 199.791 20.718 199.809 20.736 ; - END - END r0_rd_out[454] - PIN r0_rd_out[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 200.799 20.718 200.817 20.736 ; - END - END r0_rd_out[455] - PIN r0_rd_out[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 201.807 20.718 201.825 20.736 ; - END - END r0_rd_out[456] - PIN r0_rd_out[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 202.815 20.718 202.833 20.736 ; - END - END r0_rd_out[457] - PIN r0_rd_out[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 203.823 20.718 203.841 20.736 ; - END - END r0_rd_out[458] - PIN r0_rd_out[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 204.831 20.718 204.849 20.736 ; - END - END r0_rd_out[459] - PIN r0_rd_out[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 205.839 20.718 205.857 20.736 ; - END - END r0_rd_out[460] - PIN r0_rd_out[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 206.847 20.718 206.865 20.736 ; - END - END r0_rd_out[461] - PIN r0_rd_out[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 207.855 20.718 207.873 20.736 ; - END - END r0_rd_out[462] - PIN r0_rd_out[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 208.863 20.718 208.881 20.736 ; - END - END r0_rd_out[463] - PIN r0_rd_out[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 209.871 20.718 209.889 20.736 ; - END - END r0_rd_out[464] - PIN r0_rd_out[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 210.879 20.718 210.897 20.736 ; - END - END r0_rd_out[465] - PIN r0_rd_out[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 211.887 20.718 211.905 20.736 ; - END - END r0_rd_out[466] - PIN r0_rd_out[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 212.895 20.718 212.913 20.736 ; - END - END r0_rd_out[467] - PIN r0_rd_out[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 213.903 20.718 213.921 20.736 ; - END - END r0_rd_out[468] - PIN r0_rd_out[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 214.911 20.718 214.929 20.736 ; - END - END r0_rd_out[469] - PIN r0_rd_out[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 215.919 20.718 215.937 20.736 ; - END - END r0_rd_out[470] - PIN r0_rd_out[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 216.927 20.718 216.945 20.736 ; - END - END r0_rd_out[471] - PIN r0_rd_out[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 217.935 20.718 217.953 20.736 ; - END - END r0_rd_out[472] - PIN r0_rd_out[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 218.943 20.718 218.961 20.736 ; - END - END r0_rd_out[473] - PIN r0_rd_out[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 219.951 20.718 219.969 20.736 ; - END - END r0_rd_out[474] - PIN r0_rd_out[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 220.959 20.718 220.977 20.736 ; - END - END r0_rd_out[475] - PIN r0_rd_out[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 221.967 20.718 221.985 20.736 ; - END - END r0_rd_out[476] - PIN r0_rd_out[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 222.975 20.718 222.993 20.736 ; - END - END r0_rd_out[477] - PIN r0_rd_out[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 223.983 20.718 224.001 20.736 ; - END - END r0_rd_out[478] - PIN r0_rd_out[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 224.991 20.718 225.009 20.736 ; - END - END r0_rd_out[479] - PIN r0_rd_out[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 225.999 20.718 226.017 20.736 ; - END - END r0_rd_out[480] - PIN r0_rd_out[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 227.007 20.718 227.025 20.736 ; - END - END r0_rd_out[481] - PIN r0_rd_out[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 228.015 20.718 228.033 20.736 ; - END - END r0_rd_out[482] - PIN r0_rd_out[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 229.023 20.718 229.041 20.736 ; - END - END r0_rd_out[483] - PIN r0_rd_out[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 230.031 20.718 230.049 20.736 ; - END - END r0_rd_out[484] - PIN r0_rd_out[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 231.039 20.718 231.057 20.736 ; - END - END r0_rd_out[485] - PIN r0_rd_out[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 232.047 20.718 232.065 20.736 ; - END - END r0_rd_out[486] - PIN r0_rd_out[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 233.055 20.718 233.073 20.736 ; - END - END r0_rd_out[487] - PIN r0_rd_out[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 234.063 20.718 234.081 20.736 ; - END - END r0_rd_out[488] - PIN r0_rd_out[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 235.071 20.718 235.089 20.736 ; - END - END r0_rd_out[489] - PIN r0_rd_out[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 236.079 20.718 236.097 20.736 ; - END - END r0_rd_out[490] - PIN r0_rd_out[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 237.087 20.718 237.105 20.736 ; - END - END r0_rd_out[491] - PIN r0_rd_out[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 238.095 20.718 238.113 20.736 ; - END - END r0_rd_out[492] - PIN r0_rd_out[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 239.103 20.718 239.121 20.736 ; - END - END r0_rd_out[493] - PIN r0_rd_out[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 240.111 20.718 240.129 20.736 ; - END - END r0_rd_out[494] - PIN r0_rd_out[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 241.119 20.718 241.137 20.736 ; - END - END r0_rd_out[495] - PIN r0_rd_out[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 242.127 20.718 242.145 20.736 ; - END - END r0_rd_out[496] - PIN r0_rd_out[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 243.135 20.718 243.153 20.736 ; - END - END r0_rd_out[497] - PIN r0_rd_out[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 244.143 20.718 244.161 20.736 ; - END - END r0_rd_out[498] - PIN r0_rd_out[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 245.151 20.718 245.169 20.736 ; - END - END r0_rd_out[499] - PIN r0_rd_out[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 246.159 20.718 246.177 20.736 ; - END - END r0_rd_out[500] - PIN r0_rd_out[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 247.167 20.718 247.185 20.736 ; - END - END r0_rd_out[501] - PIN r0_rd_out[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 248.175 20.718 248.193 20.736 ; - END - END r0_rd_out[502] - PIN r0_rd_out[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 249.183 20.718 249.201 20.736 ; - END - END r0_rd_out[503] - PIN r0_rd_out[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 250.191 20.718 250.209 20.736 ; - END - END r0_rd_out[504] - PIN r0_rd_out[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 251.199 20.718 251.217 20.736 ; - END - END r0_rd_out[505] - PIN r0_rd_out[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 252.207 20.718 252.225 20.736 ; - END - END r0_rd_out[506] - PIN r0_rd_out[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 253.215 20.718 253.233 20.736 ; - END - END r0_rd_out[507] - PIN r0_rd_out[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 254.223 20.718 254.241 20.736 ; - END - END r0_rd_out[508] - PIN r0_rd_out[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 255.231 20.718 255.249 20.736 ; - END - END r0_rd_out[509] - PIN r0_rd_out[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 256.239 20.718 256.257 20.736 ; - END - END r0_rd_out[510] - PIN r0_rd_out[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 257.247 20.718 257.265 20.736 ; - END - END r0_rd_out[511] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.708 0.024 18.732 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.852 0.024 18.876 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 18.996 0.024 19.020 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 19.140 0.024 19.164 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.708 265.421 18.732 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.852 265.421 18.876 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 18.996 265.421 19.020 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 19.140 265.421 19.164 ; - END - END w0_addr_in[7] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 19.284 0.024 19.308 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 19.428 0.024 19.452 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 19.572 0.024 19.596 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 0.000 19.716 0.024 19.740 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 19.284 265.421 19.308 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 19.428 265.421 19.452 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 19.572 265.421 19.596 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M4 ; - RECT 265.397 19.716 265.421 19.740 ; - END - END r0_addr_in[7] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 258.255 20.718 258.273 20.736 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 259.263 20.718 259.281 20.736 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 260.271 20.718 260.289 20.736 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 261.279 20.718 261.297 20.736 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER M3 ; - RECT 262.287 20.718 262.305 20.736 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER M4 ; - RECT 0.108 0.192 265.313 0.288 ; - RECT 0.108 0.960 265.313 1.056 ; - RECT 0.108 1.728 265.313 1.824 ; - RECT 0.108 2.496 265.313 2.592 ; - RECT 0.108 3.264 265.313 3.360 ; - RECT 0.108 4.032 265.313 4.128 ; - RECT 0.108 4.800 265.313 4.896 ; - RECT 0.108 5.568 265.313 5.664 ; - RECT 0.108 6.336 265.313 6.432 ; - RECT 0.108 7.104 265.313 7.200 ; - RECT 0.108 7.872 265.313 7.968 ; - RECT 0.108 8.640 265.313 8.736 ; - RECT 0.108 9.408 265.313 9.504 ; - RECT 0.108 10.176 265.313 10.272 ; - RECT 0.108 10.944 265.313 11.040 ; - RECT 0.108 11.712 265.313 11.808 ; - RECT 0.108 12.480 265.313 12.576 ; - RECT 0.108 13.248 265.313 13.344 ; - RECT 0.108 14.016 265.313 14.112 ; - RECT 0.108 14.784 265.313 14.880 ; - RECT 0.108 15.552 265.313 15.648 ; - RECT 0.108 16.320 265.313 16.416 ; - RECT 0.108 17.088 265.313 17.184 ; - RECT 0.108 17.856 265.313 17.952 ; - RECT 0.108 18.624 265.313 18.720 ; - RECT 0.108 19.392 265.313 19.488 ; - RECT 0.108 20.160 265.313 20.256 ; - END - END VDD - OBS - LAYER M1 ; - RECT 0 0 265.421 20.736 ; - LAYER M2 ; - RECT 0 0 265.421 20.736 ; - LAYER M3 ; - RECT 0 0 265.421 20.736 ; - LAYER M4 ; - RECT 0 0 265.421 20.736 ; - END -END fakeram_512x256_1r1w - -END LIBRARY diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib deleted file mode 100644 index bf05bb6..0000000 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib +++ /dev/null @@ -1,678 +0,0 @@ -library(fakeram_20x64_2r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-02 18:11:03Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 0.7; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 0.7; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_20x64_2r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_20x64_2r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_20x64_2r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_20x64_2r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_20x64_2r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_20x64_2r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 20; - bit_from : 19; - bit_to : 0 ; - downto : true ; - } - type (fakeram_20x64_2r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 6; - bit_from : 5; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_20x64_2r1w) { - area : 53.748; - interface_timing : true; - memory() { - type : ram; - address_width : 6; - word_width : 20; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.157 ; - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - fall_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - } - } - - pin(r1_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.157 ; - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - fall_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.157 ; - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - fall_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_20x64_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - cell_fall(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - rise_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - bus(r1_rd_out) { - bus_type : fakeram_20x64_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r1_addr_in; - } - timing() { - related_pin : "r1_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - cell_fall(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - rise_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - pin(r1_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_20x64_2r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_20x64_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(r1_addr_in) { - bus_type : fakeram_20x64_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_20x64_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - cell_leakage_power : 128.900; -} - -} diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib b/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib deleted file mode 100644 index b5577c5..0000000 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib +++ /dev/null @@ -1,678 +0,0 @@ -library(fakeram_32x128_2r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-02 18:11:03Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 0.7; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 0.7; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_32x128_2r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_32x128_2r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_32x128_2r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_32x128_2r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_32x128_2r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_32x128_2r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 32; - bit_from : 31; - bit_to : 0 ; - downto : true ; - } - type (fakeram_32x128_2r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 7; - bit_from : 6; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_32x128_2r1w) { - area : 172.005; - interface_timing : true; - memory() { - type : ram; - address_width : 7; - word_width : 32; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.157 ; - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - fall_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - } - } - - pin(r1_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.157 ; - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - fall_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.157 ; - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - fall_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.345, 1.345") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_32x128_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - cell_fall(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - rise_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - bus(r1_rd_out) { - bus_type : fakeram_32x128_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r1_addr_in; - } - timing() { - related_pin : "r1_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - cell_fall(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.218, 0.218", \ - "0.218, 0.218" \ - ) - } - rise_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - pin(r1_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_32x128_2r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_32x128_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(r1_addr_in) { - bus_type : fakeram_32x128_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_32x128_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.013, 0.013") - } - } - } - cell_leakage_power : 128.900; -} - -} diff --git a/designs/asap7/coralnpu/config.mk b/designs/asap7/coralnpu/config.mk new file mode 100644 index 0000000..e77888d --- /dev/null +++ b/designs/asap7/coralnpu/config.mk @@ -0,0 +1,17 @@ +export DESIGN_NAME = CoreMiniAxi +export PLATFORM = asap7 +export DESIGN_NICKNAME = coralnpu +export DESIGN_RESULTS_NAME = coralnpu + +-include $(BENCH_DESIGN_HOME)/src/coralnpu/verilog.mk + +export SYNTH_HIERARCHICAL = 1 + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/coralnpu/constraint.sdc + +export CORE_UTILIZATION = 50 +export PLACE_DENSITY_LB_ADDON = 0.20 + +export MACRO_PLACE_HALO = 6 6 + +export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/asap7/coralnpu/constraint.sdc b/designs/asap7/coralnpu/constraint.sdc new file mode 100644 index 0000000..9e74ca9 --- /dev/null +++ b/designs/asap7/coralnpu/constraint.sdc @@ -0,0 +1,19 @@ +current_design CoreMiniAxi + +set clk_name io_aclk +set clk_port_name io_aclk +set clk_period 3000 +set clk_io_pct 0.2 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] +set non_clock_outputs [lsearch -inline -all -not -exact [all_outputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] + +set_false_path -from [get_ports io_aresetn] +set_false_path -from [get_ports reset] \ No newline at end of file diff --git a/designs/asap7/coralnpu/sram/lef/fakeram_2048x128_1rw.lef b/designs/asap7/coralnpu/sram/lef/fakeram_2048x128_1rw.lef new file mode 100644 index 0000000..8ab8c52 --- /dev/null +++ b/designs/asap7/coralnpu/sram/lef/fakeram_2048x128_1rw.lef @@ -0,0 +1,55758 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_2048x128_1rw + FOREIGN fakeram_2048x128_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 416.048 BY 130.015 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.372 0.072 0.396 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.468 0.072 0.492 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.332 0.072 1.356 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.524 0.072 1.548 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.908 0.072 1.932 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.100 0.072 2.124 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.484 0.072 2.508 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.060 0.072 3.084 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.252 0.072 3.276 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.540 0.072 3.564 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.828 0.072 3.852 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.212 0.072 4.236 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.404 0.072 4.428 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.788 0.072 4.812 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.364 0.072 5.388 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.844 0.072 5.868 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.940 0.072 5.964 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.132 0.072 6.156 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.228 0.072 6.252 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END rw0_wmask_in[63] + PIN rw0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END rw0_wmask_in[64] + PIN rw0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END rw0_wmask_in[65] + PIN rw0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END rw0_wmask_in[66] + PIN rw0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.708 0.072 6.732 ; + END + END rw0_wmask_in[67] + PIN rw0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END rw0_wmask_in[68] + PIN rw0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END rw0_wmask_in[69] + PIN rw0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END rw0_wmask_in[70] + PIN rw0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.092 0.072 7.116 ; + END + END rw0_wmask_in[71] + PIN rw0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END rw0_wmask_in[72] + PIN rw0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.284 0.072 7.308 ; + END + END rw0_wmask_in[73] + PIN rw0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.380 0.072 7.404 ; + END + END rw0_wmask_in[74] + PIN rw0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END rw0_wmask_in[75] + PIN rw0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END rw0_wmask_in[76] + PIN rw0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END rw0_wmask_in[77] + PIN rw0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END rw0_wmask_in[78] + PIN rw0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.860 0.072 7.884 ; + END + END rw0_wmask_in[79] + PIN rw0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END rw0_wmask_in[80] + PIN rw0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END rw0_wmask_in[81] + PIN rw0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.148 0.072 8.172 ; + END + END rw0_wmask_in[82] + PIN rw0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.244 0.072 8.268 ; + END + END rw0_wmask_in[83] + PIN rw0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END rw0_wmask_in[84] + PIN rw0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END rw0_wmask_in[85] + PIN rw0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.532 0.072 8.556 ; + END + END rw0_wmask_in[86] + PIN rw0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END rw0_wmask_in[87] + PIN rw0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END rw0_wmask_in[88] + PIN rw0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.820 0.072 8.844 ; + END + END rw0_wmask_in[89] + PIN rw0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END rw0_wmask_in[90] + PIN rw0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END rw0_wmask_in[91] + PIN rw0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END rw0_wmask_in[92] + PIN rw0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END rw0_wmask_in[93] + PIN rw0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.300 0.072 9.324 ; + END + END rw0_wmask_in[94] + PIN rw0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END rw0_wmask_in[95] + PIN rw0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END rw0_wmask_in[96] + PIN rw0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.588 0.072 9.612 ; + END + END rw0_wmask_in[97] + PIN rw0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END rw0_wmask_in[98] + PIN rw0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END rw0_wmask_in[99] + PIN rw0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END rw0_wmask_in[100] + PIN rw0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.972 0.072 9.996 ; + END + END rw0_wmask_in[101] + PIN rw0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END rw0_wmask_in[102] + PIN rw0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.164 0.072 10.188 ; + END + END rw0_wmask_in[103] + PIN rw0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END rw0_wmask_in[104] + PIN rw0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END rw0_wmask_in[105] + PIN rw0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.452 0.072 10.476 ; + END + END rw0_wmask_in[106] + PIN rw0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.548 0.072 10.572 ; + END + END rw0_wmask_in[107] + PIN rw0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END rw0_wmask_in[108] + PIN rw0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.740 0.072 10.764 ; + END + END rw0_wmask_in[109] + PIN rw0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END rw0_wmask_in[110] + PIN rw0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END rw0_wmask_in[111] + PIN rw0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END rw0_wmask_in[112] + PIN rw0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.124 0.072 11.148 ; + END + END rw0_wmask_in[113] + PIN rw0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END rw0_wmask_in[114] + PIN rw0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END rw0_wmask_in[115] + PIN rw0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.412 0.072 11.436 ; + END + END rw0_wmask_in[116] + PIN rw0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END rw0_wmask_in[117] + PIN rw0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.604 0.072 11.628 ; + END + END rw0_wmask_in[118] + PIN rw0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END rw0_wmask_in[119] + PIN rw0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END rw0_wmask_in[120] + PIN rw0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.892 0.072 11.916 ; + END + END rw0_wmask_in[121] + PIN rw0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.988 0.072 12.012 ; + END + END rw0_wmask_in[122] + PIN rw0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END rw0_wmask_in[123] + PIN rw0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.180 0.072 12.204 ; + END + END rw0_wmask_in[124] + PIN rw0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END rw0_wmask_in[125] + PIN rw0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END rw0_wmask_in[126] + PIN rw0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.468 0.072 12.492 ; + END + END rw0_wmask_in[127] + PIN rw0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.564 0.072 12.588 ; + END + END rw0_wmask_in[128] + PIN rw0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END rw0_wmask_in[129] + PIN rw0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END rw0_wmask_in[130] + PIN rw0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.852 0.072 12.876 ; + END + END rw0_wmask_in[131] + PIN rw0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END rw0_wmask_in[132] + PIN rw0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END rw0_wmask_in[133] + PIN rw0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.140 0.072 13.164 ; + END + END rw0_wmask_in[134] + PIN rw0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END rw0_wmask_in[135] + PIN rw0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.332 0.072 13.356 ; + END + END rw0_wmask_in[136] + PIN rw0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.428 0.072 13.452 ; + END + END rw0_wmask_in[137] + PIN rw0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END rw0_wmask_in[138] + PIN rw0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.620 0.072 13.644 ; + END + END rw0_wmask_in[139] + PIN rw0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END rw0_wmask_in[140] + PIN rw0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END rw0_wmask_in[141] + PIN rw0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.908 0.072 13.932 ; + END + END rw0_wmask_in[142] + PIN rw0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END rw0_wmask_in[143] + PIN rw0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END rw0_wmask_in[144] + PIN rw0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END rw0_wmask_in[145] + PIN rw0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.292 0.072 14.316 ; + END + END rw0_wmask_in[146] + PIN rw0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END rw0_wmask_in[147] + PIN rw0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.484 0.072 14.508 ; + END + END rw0_wmask_in[148] + PIN rw0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.580 0.072 14.604 ; + END + END rw0_wmask_in[149] + PIN rw0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END rw0_wmask_in[150] + PIN rw0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.772 0.072 14.796 ; + END + END rw0_wmask_in[151] + PIN rw0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END rw0_wmask_in[152] + PIN rw0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END rw0_wmask_in[153] + PIN rw0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END rw0_wmask_in[154] + PIN rw0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END rw0_wmask_in[155] + PIN rw0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END rw0_wmask_in[156] + PIN rw0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.348 0.072 15.372 ; + END + END rw0_wmask_in[157] + PIN rw0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.444 0.072 15.468 ; + END + END rw0_wmask_in[158] + PIN rw0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END rw0_wmask_in[159] + PIN rw0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END rw0_wmask_in[160] + PIN rw0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END rw0_wmask_in[161] + PIN rw0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END rw0_wmask_in[162] + PIN rw0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.924 0.072 15.948 ; + END + END rw0_wmask_in[163] + PIN rw0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.020 0.072 16.044 ; + END + END rw0_wmask_in[164] + PIN rw0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END rw0_wmask_in[165] + PIN rw0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.212 0.072 16.236 ; + END + END rw0_wmask_in[166] + PIN rw0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.308 0.072 16.332 ; + END + END rw0_wmask_in[167] + PIN rw0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END rw0_wmask_in[168] + PIN rw0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.500 0.072 16.524 ; + END + END rw0_wmask_in[169] + PIN rw0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END rw0_wmask_in[170] + PIN rw0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END rw0_wmask_in[171] + PIN rw0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.788 0.072 16.812 ; + END + END rw0_wmask_in[172] + PIN rw0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.884 0.072 16.908 ; + END + END rw0_wmask_in[173] + PIN rw0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END rw0_wmask_in[174] + PIN rw0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END rw0_wmask_in[175] + PIN rw0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END rw0_wmask_in[176] + PIN rw0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END rw0_wmask_in[177] + PIN rw0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.364 0.072 17.388 ; + END + END rw0_wmask_in[178] + PIN rw0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.460 0.072 17.484 ; + END + END rw0_wmask_in[179] + PIN rw0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END rw0_wmask_in[180] + PIN rw0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.652 0.072 17.676 ; + END + END rw0_wmask_in[181] + PIN rw0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END rw0_wmask_in[182] + PIN rw0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END rw0_wmask_in[183] + PIN rw0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END rw0_wmask_in[184] + PIN rw0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END rw0_wmask_in[185] + PIN rw0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END rw0_wmask_in[186] + PIN rw0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.228 0.072 18.252 ; + END + END rw0_wmask_in[187] + PIN rw0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.324 0.072 18.348 ; + END + END rw0_wmask_in[188] + PIN rw0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END rw0_wmask_in[189] + PIN rw0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END rw0_wmask_in[190] + PIN rw0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.612 0.072 18.636 ; + END + END rw0_wmask_in[191] + PIN rw0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END rw0_wmask_in[192] + PIN rw0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.804 0.072 18.828 ; + END + END rw0_wmask_in[193] + PIN rw0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.900 0.072 18.924 ; + END + END rw0_wmask_in[194] + PIN rw0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END rw0_wmask_in[195] + PIN rw0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END rw0_wmask_in[196] + PIN rw0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.188 0.072 19.212 ; + END + END rw0_wmask_in[197] + PIN rw0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END rw0_wmask_in[198] + PIN rw0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.380 0.072 19.404 ; + END + END rw0_wmask_in[199] + PIN rw0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END rw0_wmask_in[200] + PIN rw0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END rw0_wmask_in[201] + PIN rw0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.668 0.072 19.692 ; + END + END rw0_wmask_in[202] + PIN rw0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END rw0_wmask_in[203] + PIN rw0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END rw0_wmask_in[204] + PIN rw0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END rw0_wmask_in[205] + PIN rw0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.052 0.072 20.076 ; + END + END rw0_wmask_in[206] + PIN rw0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END rw0_wmask_in[207] + PIN rw0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.244 0.072 20.268 ; + END + END rw0_wmask_in[208] + PIN rw0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.340 0.072 20.364 ; + END + END rw0_wmask_in[209] + PIN rw0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END rw0_wmask_in[210] + PIN rw0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.532 0.072 20.556 ; + END + END rw0_wmask_in[211] + PIN rw0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.628 0.072 20.652 ; + END + END rw0_wmask_in[212] + PIN rw0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END rw0_wmask_in[213] + PIN rw0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.820 0.072 20.844 ; + END + END rw0_wmask_in[214] + PIN rw0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END rw0_wmask_in[215] + PIN rw0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END rw0_wmask_in[216] + PIN rw0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END rw0_wmask_in[217] + PIN rw0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.204 0.072 21.228 ; + END + END rw0_wmask_in[218] + PIN rw0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END rw0_wmask_in[219] + PIN rw0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END rw0_wmask_in[220] + PIN rw0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.492 0.072 21.516 ; + END + END rw0_wmask_in[221] + PIN rw0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END rw0_wmask_in[222] + PIN rw0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.684 0.072 21.708 ; + END + END rw0_wmask_in[223] + PIN rw0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END rw0_wmask_in[224] + PIN rw0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END rw0_wmask_in[225] + PIN rw0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.972 0.072 21.996 ; + END + END rw0_wmask_in[226] + PIN rw0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.068 0.072 22.092 ; + END + END rw0_wmask_in[227] + PIN rw0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END rw0_wmask_in[228] + PIN rw0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.260 0.072 22.284 ; + END + END rw0_wmask_in[229] + PIN rw0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END rw0_wmask_in[230] + PIN rw0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END rw0_wmask_in[231] + PIN rw0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.548 0.072 22.572 ; + END + END rw0_wmask_in[232] + PIN rw0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.644 0.072 22.668 ; + END + END rw0_wmask_in[233] + PIN rw0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END rw0_wmask_in[234] + PIN rw0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END rw0_wmask_in[235] + PIN rw0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.932 0.072 22.956 ; + END + END rw0_wmask_in[236] + PIN rw0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END rw0_wmask_in[237] + PIN rw0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END rw0_wmask_in[238] + PIN rw0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.220 0.072 23.244 ; + END + END rw0_wmask_in[239] + PIN rw0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END rw0_wmask_in[240] + PIN rw0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.412 0.072 23.436 ; + END + END rw0_wmask_in[241] + PIN rw0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.508 0.072 23.532 ; + END + END rw0_wmask_in[242] + PIN rw0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END rw0_wmask_in[243] + PIN rw0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.700 0.072 23.724 ; + END + END rw0_wmask_in[244] + PIN rw0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END rw0_wmask_in[245] + PIN rw0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END rw0_wmask_in[246] + PIN rw0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.988 0.072 24.012 ; + END + END rw0_wmask_in[247] + PIN rw0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.084 0.072 24.108 ; + END + END rw0_wmask_in[248] + PIN rw0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END rw0_wmask_in[249] + PIN rw0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.276 0.072 24.300 ; + END + END rw0_wmask_in[250] + PIN rw0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.372 0.072 24.396 ; + END + END rw0_wmask_in[251] + PIN rw0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END rw0_wmask_in[252] + PIN rw0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.564 0.072 24.588 ; + END + END rw0_wmask_in[253] + PIN rw0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.660 0.072 24.684 ; + END + END rw0_wmask_in[254] + PIN rw0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END rw0_wmask_in[255] + PIN rw0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.852 0.072 24.876 ; + END + END rw0_wmask_in[256] + PIN rw0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.948 0.072 24.972 ; + END + END rw0_wmask_in[257] + PIN rw0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END rw0_wmask_in[258] + PIN rw0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.140 0.072 25.164 ; + END + END rw0_wmask_in[259] + PIN rw0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.236 0.072 25.260 ; + END + END rw0_wmask_in[260] + PIN rw0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END rw0_wmask_in[261] + PIN rw0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.428 0.072 25.452 ; + END + END rw0_wmask_in[262] + PIN rw0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.524 0.072 25.548 ; + END + END rw0_wmask_in[263] + PIN rw0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END rw0_wmask_in[264] + PIN rw0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.716 0.072 25.740 ; + END + END rw0_wmask_in[265] + PIN rw0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.812 0.072 25.836 ; + END + END rw0_wmask_in[266] + PIN rw0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END rw0_wmask_in[267] + PIN rw0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.004 0.072 26.028 ; + END + END rw0_wmask_in[268] + PIN rw0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.100 0.072 26.124 ; + END + END rw0_wmask_in[269] + PIN rw0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END rw0_wmask_in[270] + PIN rw0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.292 0.072 26.316 ; + END + END rw0_wmask_in[271] + PIN rw0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.388 0.072 26.412 ; + END + END rw0_wmask_in[272] + PIN rw0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END rw0_wmask_in[273] + PIN rw0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.580 0.072 26.604 ; + END + END rw0_wmask_in[274] + PIN rw0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.676 0.072 26.700 ; + END + END rw0_wmask_in[275] + PIN rw0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END rw0_wmask_in[276] + PIN rw0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.868 0.072 26.892 ; + END + END rw0_wmask_in[277] + PIN rw0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.964 0.072 26.988 ; + END + END rw0_wmask_in[278] + PIN rw0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END rw0_wmask_in[279] + PIN rw0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.156 0.072 27.180 ; + END + END rw0_wmask_in[280] + PIN rw0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.252 0.072 27.276 ; + END + END rw0_wmask_in[281] + PIN rw0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END rw0_wmask_in[282] + PIN rw0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.444 0.072 27.468 ; + END + END rw0_wmask_in[283] + PIN rw0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.540 0.072 27.564 ; + END + END rw0_wmask_in[284] + PIN rw0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END rw0_wmask_in[285] + PIN rw0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.732 0.072 27.756 ; + END + END rw0_wmask_in[286] + PIN rw0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.828 0.072 27.852 ; + END + END rw0_wmask_in[287] + PIN rw0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END rw0_wmask_in[288] + PIN rw0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.020 0.072 28.044 ; + END + END rw0_wmask_in[289] + PIN rw0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.116 0.072 28.140 ; + END + END rw0_wmask_in[290] + PIN rw0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.212 0.072 28.236 ; + END + END rw0_wmask_in[291] + PIN rw0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.308 0.072 28.332 ; + END + END rw0_wmask_in[292] + PIN rw0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.404 0.072 28.428 ; + END + END rw0_wmask_in[293] + PIN rw0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END rw0_wmask_in[294] + PIN rw0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.596 0.072 28.620 ; + END + END rw0_wmask_in[295] + PIN rw0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.692 0.072 28.716 ; + END + END rw0_wmask_in[296] + PIN rw0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END rw0_wmask_in[297] + PIN rw0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.884 0.072 28.908 ; + END + END rw0_wmask_in[298] + PIN rw0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.980 0.072 29.004 ; + END + END rw0_wmask_in[299] + PIN rw0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END rw0_wmask_in[300] + PIN rw0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.172 0.072 29.196 ; + END + END rw0_wmask_in[301] + PIN rw0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.268 0.072 29.292 ; + END + END rw0_wmask_in[302] + PIN rw0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END rw0_wmask_in[303] + PIN rw0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.460 0.072 29.484 ; + END + END rw0_wmask_in[304] + PIN rw0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.556 0.072 29.580 ; + END + END rw0_wmask_in[305] + PIN rw0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END rw0_wmask_in[306] + PIN rw0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.748 0.072 29.772 ; + END + END rw0_wmask_in[307] + PIN rw0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.844 0.072 29.868 ; + END + END rw0_wmask_in[308] + PIN rw0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.940 0.072 29.964 ; + END + END rw0_wmask_in[309] + PIN rw0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.036 0.072 30.060 ; + END + END rw0_wmask_in[310] + PIN rw0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.132 0.072 30.156 ; + END + END rw0_wmask_in[311] + PIN rw0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END rw0_wmask_in[312] + PIN rw0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.324 0.072 30.348 ; + END + END rw0_wmask_in[313] + PIN rw0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.420 0.072 30.444 ; + END + END rw0_wmask_in[314] + PIN rw0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END rw0_wmask_in[315] + PIN rw0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.612 0.072 30.636 ; + END + END rw0_wmask_in[316] + PIN rw0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.708 0.072 30.732 ; + END + END rw0_wmask_in[317] + PIN rw0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END rw0_wmask_in[318] + PIN rw0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.900 0.072 30.924 ; + END + END rw0_wmask_in[319] + PIN rw0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.996 0.072 31.020 ; + END + END rw0_wmask_in[320] + PIN rw0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.092 0.072 31.116 ; + END + END rw0_wmask_in[321] + PIN rw0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.188 0.072 31.212 ; + END + END rw0_wmask_in[322] + PIN rw0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.284 0.072 31.308 ; + END + END rw0_wmask_in[323] + PIN rw0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END rw0_wmask_in[324] + PIN rw0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.476 0.072 31.500 ; + END + END rw0_wmask_in[325] + PIN rw0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.572 0.072 31.596 ; + END + END rw0_wmask_in[326] + PIN rw0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.668 0.072 31.692 ; + END + END rw0_wmask_in[327] + PIN rw0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.764 0.072 31.788 ; + END + END rw0_wmask_in[328] + PIN rw0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.860 0.072 31.884 ; + END + END rw0_wmask_in[329] + PIN rw0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END rw0_wmask_in[330] + PIN rw0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.052 0.072 32.076 ; + END + END rw0_wmask_in[331] + PIN rw0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.148 0.072 32.172 ; + END + END rw0_wmask_in[332] + PIN rw0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END rw0_wmask_in[333] + PIN rw0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.340 0.072 32.364 ; + END + END rw0_wmask_in[334] + PIN rw0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.436 0.072 32.460 ; + END + END rw0_wmask_in[335] + PIN rw0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END rw0_wmask_in[336] + PIN rw0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.628 0.072 32.652 ; + END + END rw0_wmask_in[337] + PIN rw0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.724 0.072 32.748 ; + END + END rw0_wmask_in[338] + PIN rw0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.820 0.072 32.844 ; + END + END rw0_wmask_in[339] + PIN rw0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.916 0.072 32.940 ; + END + END rw0_wmask_in[340] + PIN rw0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.012 0.072 33.036 ; + END + END rw0_wmask_in[341] + PIN rw0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END rw0_wmask_in[342] + PIN rw0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.204 0.072 33.228 ; + END + END rw0_wmask_in[343] + PIN rw0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.300 0.072 33.324 ; + END + END rw0_wmask_in[344] + PIN rw0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END rw0_wmask_in[345] + PIN rw0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.492 0.072 33.516 ; + END + END rw0_wmask_in[346] + PIN rw0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.588 0.072 33.612 ; + END + END rw0_wmask_in[347] + PIN rw0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END rw0_wmask_in[348] + PIN rw0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.780 0.072 33.804 ; + END + END rw0_wmask_in[349] + PIN rw0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.876 0.072 33.900 ; + END + END rw0_wmask_in[350] + PIN rw0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END rw0_wmask_in[351] + PIN rw0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.068 0.072 34.092 ; + END + END rw0_wmask_in[352] + PIN rw0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.164 0.072 34.188 ; + END + END rw0_wmask_in[353] + PIN rw0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END rw0_wmask_in[354] + PIN rw0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.356 0.072 34.380 ; + END + END rw0_wmask_in[355] + PIN rw0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.452 0.072 34.476 ; + END + END rw0_wmask_in[356] + PIN rw0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END rw0_wmask_in[357] + PIN rw0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.644 0.072 34.668 ; + END + END rw0_wmask_in[358] + PIN rw0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.740 0.072 34.764 ; + END + END rw0_wmask_in[359] + PIN rw0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END rw0_wmask_in[360] + PIN rw0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.932 0.072 34.956 ; + END + END rw0_wmask_in[361] + PIN rw0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.028 0.072 35.052 ; + END + END rw0_wmask_in[362] + PIN rw0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.124 0.072 35.148 ; + END + END rw0_wmask_in[363] + PIN rw0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.220 0.072 35.244 ; + END + END rw0_wmask_in[364] + PIN rw0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.316 0.072 35.340 ; + END + END rw0_wmask_in[365] + PIN rw0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END rw0_wmask_in[366] + PIN rw0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.508 0.072 35.532 ; + END + END rw0_wmask_in[367] + PIN rw0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.604 0.072 35.628 ; + END + END rw0_wmask_in[368] + PIN rw0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END rw0_wmask_in[369] + PIN rw0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.796 0.072 35.820 ; + END + END rw0_wmask_in[370] + PIN rw0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.892 0.072 35.916 ; + END + END rw0_wmask_in[371] + PIN rw0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END rw0_wmask_in[372] + PIN rw0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.084 0.072 36.108 ; + END + END rw0_wmask_in[373] + PIN rw0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.180 0.072 36.204 ; + END + END rw0_wmask_in[374] + PIN rw0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END rw0_wmask_in[375] + PIN rw0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.372 0.072 36.396 ; + END + END rw0_wmask_in[376] + PIN rw0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.468 0.072 36.492 ; + END + END rw0_wmask_in[377] + PIN rw0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END rw0_wmask_in[378] + PIN rw0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.660 0.072 36.684 ; + END + END rw0_wmask_in[379] + PIN rw0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.756 0.072 36.780 ; + END + END rw0_wmask_in[380] + PIN rw0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.852 0.072 36.876 ; + END + END rw0_wmask_in[381] + PIN rw0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.948 0.072 36.972 ; + END + END rw0_wmask_in[382] + PIN rw0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.044 0.072 37.068 ; + END + END rw0_wmask_in[383] + PIN rw0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END rw0_wmask_in[384] + PIN rw0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.236 0.072 37.260 ; + END + END rw0_wmask_in[385] + PIN rw0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.332 0.072 37.356 ; + END + END rw0_wmask_in[386] + PIN rw0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END rw0_wmask_in[387] + PIN rw0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.524 0.072 37.548 ; + END + END rw0_wmask_in[388] + PIN rw0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.620 0.072 37.644 ; + END + END rw0_wmask_in[389] + PIN rw0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END rw0_wmask_in[390] + PIN rw0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.812 0.072 37.836 ; + END + END rw0_wmask_in[391] + PIN rw0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.908 0.072 37.932 ; + END + END rw0_wmask_in[392] + PIN rw0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.004 0.072 38.028 ; + END + END rw0_wmask_in[393] + PIN rw0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.100 0.072 38.124 ; + END + END rw0_wmask_in[394] + PIN rw0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.196 0.072 38.220 ; + END + END rw0_wmask_in[395] + PIN rw0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END rw0_wmask_in[396] + PIN rw0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.388 0.072 38.412 ; + END + END rw0_wmask_in[397] + PIN rw0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.484 0.072 38.508 ; + END + END rw0_wmask_in[398] + PIN rw0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END rw0_wmask_in[399] + PIN rw0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.676 0.072 38.700 ; + END + END rw0_wmask_in[400] + PIN rw0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.772 0.072 38.796 ; + END + END rw0_wmask_in[401] + PIN rw0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.868 0.072 38.892 ; + END + END rw0_wmask_in[402] + PIN rw0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.964 0.072 38.988 ; + END + END rw0_wmask_in[403] + PIN rw0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.060 0.072 39.084 ; + END + END rw0_wmask_in[404] + PIN rw0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END rw0_wmask_in[405] + PIN rw0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.252 0.072 39.276 ; + END + END rw0_wmask_in[406] + PIN rw0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.348 0.072 39.372 ; + END + END rw0_wmask_in[407] + PIN rw0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END rw0_wmask_in[408] + PIN rw0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.540 0.072 39.564 ; + END + END rw0_wmask_in[409] + PIN rw0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.636 0.072 39.660 ; + END + END rw0_wmask_in[410] + PIN rw0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.732 0.072 39.756 ; + END + END rw0_wmask_in[411] + PIN rw0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.828 0.072 39.852 ; + END + END rw0_wmask_in[412] + PIN rw0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.924 0.072 39.948 ; + END + END rw0_wmask_in[413] + PIN rw0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END rw0_wmask_in[414] + PIN rw0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.116 0.072 40.140 ; + END + END rw0_wmask_in[415] + PIN rw0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.212 0.072 40.236 ; + END + END rw0_wmask_in[416] + PIN rw0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.308 0.072 40.332 ; + END + END rw0_wmask_in[417] + PIN rw0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.404 0.072 40.428 ; + END + END rw0_wmask_in[418] + PIN rw0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.500 0.072 40.524 ; + END + END rw0_wmask_in[419] + PIN rw0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END rw0_wmask_in[420] + PIN rw0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.692 0.072 40.716 ; + END + END rw0_wmask_in[421] + PIN rw0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.788 0.072 40.812 ; + END + END rw0_wmask_in[422] + PIN rw0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.884 0.072 40.908 ; + END + END rw0_wmask_in[423] + PIN rw0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.980 0.072 41.004 ; + END + END rw0_wmask_in[424] + PIN rw0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.076 0.072 41.100 ; + END + END rw0_wmask_in[425] + PIN rw0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.172 0.072 41.196 ; + END + END rw0_wmask_in[426] + PIN rw0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.268 0.072 41.292 ; + END + END rw0_wmask_in[427] + PIN rw0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.364 0.072 41.388 ; + END + END rw0_wmask_in[428] + PIN rw0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.460 0.072 41.484 ; + END + END rw0_wmask_in[429] + PIN rw0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.556 0.072 41.580 ; + END + END rw0_wmask_in[430] + PIN rw0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.652 0.072 41.676 ; + END + END rw0_wmask_in[431] + PIN rw0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.748 0.072 41.772 ; + END + END rw0_wmask_in[432] + PIN rw0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.844 0.072 41.868 ; + END + END rw0_wmask_in[433] + PIN rw0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.940 0.072 41.964 ; + END + END rw0_wmask_in[434] + PIN rw0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.036 0.072 42.060 ; + END + END rw0_wmask_in[435] + PIN rw0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.132 0.072 42.156 ; + END + END rw0_wmask_in[436] + PIN rw0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.228 0.072 42.252 ; + END + END rw0_wmask_in[437] + PIN rw0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.324 0.072 42.348 ; + END + END rw0_wmask_in[438] + PIN rw0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.420 0.072 42.444 ; + END + END rw0_wmask_in[439] + PIN rw0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.516 0.072 42.540 ; + END + END rw0_wmask_in[440] + PIN rw0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.612 0.072 42.636 ; + END + END rw0_wmask_in[441] + PIN rw0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.708 0.072 42.732 ; + END + END rw0_wmask_in[442] + PIN rw0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.804 0.072 42.828 ; + END + END rw0_wmask_in[443] + PIN rw0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.900 0.072 42.924 ; + END + END rw0_wmask_in[444] + PIN rw0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.996 0.072 43.020 ; + END + END rw0_wmask_in[445] + PIN rw0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.092 0.072 43.116 ; + END + END rw0_wmask_in[446] + PIN rw0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.188 0.072 43.212 ; + END + END rw0_wmask_in[447] + PIN rw0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.284 0.072 43.308 ; + END + END rw0_wmask_in[448] + PIN rw0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.380 0.072 43.404 ; + END + END rw0_wmask_in[449] + PIN rw0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.476 0.072 43.500 ; + END + END rw0_wmask_in[450] + PIN rw0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.572 0.072 43.596 ; + END + END rw0_wmask_in[451] + PIN rw0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.668 0.072 43.692 ; + END + END rw0_wmask_in[452] + PIN rw0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.764 0.072 43.788 ; + END + END rw0_wmask_in[453] + PIN rw0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.860 0.072 43.884 ; + END + END rw0_wmask_in[454] + PIN rw0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.956 0.072 43.980 ; + END + END rw0_wmask_in[455] + PIN rw0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.052 0.072 44.076 ; + END + END rw0_wmask_in[456] + PIN rw0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.148 0.072 44.172 ; + END + END rw0_wmask_in[457] + PIN rw0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.244 0.072 44.268 ; + END + END rw0_wmask_in[458] + PIN rw0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.340 0.072 44.364 ; + END + END rw0_wmask_in[459] + PIN rw0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.436 0.072 44.460 ; + END + END rw0_wmask_in[460] + PIN rw0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.532 0.072 44.556 ; + END + END rw0_wmask_in[461] + PIN rw0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.628 0.072 44.652 ; + END + END rw0_wmask_in[462] + PIN rw0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.724 0.072 44.748 ; + END + END rw0_wmask_in[463] + PIN rw0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.820 0.072 44.844 ; + END + END rw0_wmask_in[464] + PIN rw0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.916 0.072 44.940 ; + END + END rw0_wmask_in[465] + PIN rw0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.012 0.072 45.036 ; + END + END rw0_wmask_in[466] + PIN rw0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.108 0.072 45.132 ; + END + END rw0_wmask_in[467] + PIN rw0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.204 0.072 45.228 ; + END + END rw0_wmask_in[468] + PIN rw0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.300 0.072 45.324 ; + END + END rw0_wmask_in[469] + PIN rw0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.396 0.072 45.420 ; + END + END rw0_wmask_in[470] + PIN rw0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.492 0.072 45.516 ; + END + END rw0_wmask_in[471] + PIN rw0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.588 0.072 45.612 ; + END + END rw0_wmask_in[472] + PIN rw0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.684 0.072 45.708 ; + END + END rw0_wmask_in[473] + PIN rw0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.780 0.072 45.804 ; + END + END rw0_wmask_in[474] + PIN rw0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.876 0.072 45.900 ; + END + END rw0_wmask_in[475] + PIN rw0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.972 0.072 45.996 ; + END + END rw0_wmask_in[476] + PIN rw0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.068 0.072 46.092 ; + END + END rw0_wmask_in[477] + PIN rw0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.164 0.072 46.188 ; + END + END rw0_wmask_in[478] + PIN rw0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.260 0.072 46.284 ; + END + END rw0_wmask_in[479] + PIN rw0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.356 0.072 46.380 ; + END + END rw0_wmask_in[480] + PIN rw0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.452 0.072 46.476 ; + END + END rw0_wmask_in[481] + PIN rw0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.548 0.072 46.572 ; + END + END rw0_wmask_in[482] + PIN rw0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.644 0.072 46.668 ; + END + END rw0_wmask_in[483] + PIN rw0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.740 0.072 46.764 ; + END + END rw0_wmask_in[484] + PIN rw0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.836 0.072 46.860 ; + END + END rw0_wmask_in[485] + PIN rw0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.932 0.072 46.956 ; + END + END rw0_wmask_in[486] + PIN rw0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.028 0.072 47.052 ; + END + END rw0_wmask_in[487] + PIN rw0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.124 0.072 47.148 ; + END + END rw0_wmask_in[488] + PIN rw0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.220 0.072 47.244 ; + END + END rw0_wmask_in[489] + PIN rw0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.316 0.072 47.340 ; + END + END rw0_wmask_in[490] + PIN rw0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.412 0.072 47.436 ; + END + END rw0_wmask_in[491] + PIN rw0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.508 0.072 47.532 ; + END + END rw0_wmask_in[492] + PIN rw0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.604 0.072 47.628 ; + END + END rw0_wmask_in[493] + PIN rw0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.700 0.072 47.724 ; + END + END rw0_wmask_in[494] + PIN rw0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.796 0.072 47.820 ; + END + END rw0_wmask_in[495] + PIN rw0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.892 0.072 47.916 ; + END + END rw0_wmask_in[496] + PIN rw0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.988 0.072 48.012 ; + END + END rw0_wmask_in[497] + PIN rw0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.084 0.072 48.108 ; + END + END rw0_wmask_in[498] + PIN rw0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.180 0.072 48.204 ; + END + END rw0_wmask_in[499] + PIN rw0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.276 0.072 48.300 ; + END + END rw0_wmask_in[500] + PIN rw0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.372 0.072 48.396 ; + END + END rw0_wmask_in[501] + PIN rw0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.468 0.072 48.492 ; + END + END rw0_wmask_in[502] + PIN rw0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.564 0.072 48.588 ; + END + END rw0_wmask_in[503] + PIN rw0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.660 0.072 48.684 ; + END + END rw0_wmask_in[504] + PIN rw0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.756 0.072 48.780 ; + END + END rw0_wmask_in[505] + PIN rw0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.852 0.072 48.876 ; + END + END rw0_wmask_in[506] + PIN rw0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.948 0.072 48.972 ; + END + END rw0_wmask_in[507] + PIN rw0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.044 0.072 49.068 ; + END + END rw0_wmask_in[508] + PIN rw0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.140 0.072 49.164 ; + END + END rw0_wmask_in[509] + PIN rw0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.236 0.072 49.260 ; + END + END rw0_wmask_in[510] + PIN rw0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.332 0.072 49.356 ; + END + END rw0_wmask_in[511] + PIN rw0_wmask_in[512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.276 416.048 0.300 ; + END + END rw0_wmask_in[512] + PIN rw0_wmask_in[513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.372 416.048 0.396 ; + END + END rw0_wmask_in[513] + PIN rw0_wmask_in[514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.468 416.048 0.492 ; + END + END rw0_wmask_in[514] + PIN rw0_wmask_in[515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.564 416.048 0.588 ; + END + END rw0_wmask_in[515] + PIN rw0_wmask_in[516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.660 416.048 0.684 ; + END + END rw0_wmask_in[516] + PIN rw0_wmask_in[517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.756 416.048 0.780 ; + END + END rw0_wmask_in[517] + PIN rw0_wmask_in[518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.852 416.048 0.876 ; + END + END rw0_wmask_in[518] + PIN rw0_wmask_in[519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 0.948 416.048 0.972 ; + END + END rw0_wmask_in[519] + PIN rw0_wmask_in[520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.044 416.048 1.068 ; + END + END rw0_wmask_in[520] + PIN rw0_wmask_in[521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.140 416.048 1.164 ; + END + END rw0_wmask_in[521] + PIN rw0_wmask_in[522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.236 416.048 1.260 ; + END + END rw0_wmask_in[522] + PIN rw0_wmask_in[523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.332 416.048 1.356 ; + END + END rw0_wmask_in[523] + PIN rw0_wmask_in[524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.428 416.048 1.452 ; + END + END rw0_wmask_in[524] + PIN rw0_wmask_in[525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.524 416.048 1.548 ; + END + END rw0_wmask_in[525] + PIN rw0_wmask_in[526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.620 416.048 1.644 ; + END + END rw0_wmask_in[526] + PIN rw0_wmask_in[527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.716 416.048 1.740 ; + END + END rw0_wmask_in[527] + PIN rw0_wmask_in[528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.812 416.048 1.836 ; + END + END rw0_wmask_in[528] + PIN rw0_wmask_in[529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 1.908 416.048 1.932 ; + END + END rw0_wmask_in[529] + PIN rw0_wmask_in[530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.004 416.048 2.028 ; + END + END rw0_wmask_in[530] + PIN rw0_wmask_in[531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.100 416.048 2.124 ; + END + END rw0_wmask_in[531] + PIN rw0_wmask_in[532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.196 416.048 2.220 ; + END + END rw0_wmask_in[532] + PIN rw0_wmask_in[533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.292 416.048 2.316 ; + END + END rw0_wmask_in[533] + PIN rw0_wmask_in[534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.388 416.048 2.412 ; + END + END rw0_wmask_in[534] + PIN rw0_wmask_in[535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.484 416.048 2.508 ; + END + END rw0_wmask_in[535] + PIN rw0_wmask_in[536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.580 416.048 2.604 ; + END + END rw0_wmask_in[536] + PIN rw0_wmask_in[537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.676 416.048 2.700 ; + END + END rw0_wmask_in[537] + PIN rw0_wmask_in[538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.772 416.048 2.796 ; + END + END rw0_wmask_in[538] + PIN rw0_wmask_in[539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.868 416.048 2.892 ; + END + END rw0_wmask_in[539] + PIN rw0_wmask_in[540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 2.964 416.048 2.988 ; + END + END rw0_wmask_in[540] + PIN rw0_wmask_in[541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.060 416.048 3.084 ; + END + END rw0_wmask_in[541] + PIN rw0_wmask_in[542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.156 416.048 3.180 ; + END + END rw0_wmask_in[542] + PIN rw0_wmask_in[543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.252 416.048 3.276 ; + END + END rw0_wmask_in[543] + PIN rw0_wmask_in[544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.348 416.048 3.372 ; + END + END rw0_wmask_in[544] + PIN rw0_wmask_in[545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.444 416.048 3.468 ; + END + END rw0_wmask_in[545] + PIN rw0_wmask_in[546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.540 416.048 3.564 ; + END + END rw0_wmask_in[546] + PIN rw0_wmask_in[547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.636 416.048 3.660 ; + END + END rw0_wmask_in[547] + PIN rw0_wmask_in[548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.732 416.048 3.756 ; + END + END rw0_wmask_in[548] + PIN rw0_wmask_in[549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.828 416.048 3.852 ; + END + END rw0_wmask_in[549] + PIN rw0_wmask_in[550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 3.924 416.048 3.948 ; + END + END rw0_wmask_in[550] + PIN rw0_wmask_in[551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.020 416.048 4.044 ; + END + END rw0_wmask_in[551] + PIN rw0_wmask_in[552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.116 416.048 4.140 ; + END + END rw0_wmask_in[552] + PIN rw0_wmask_in[553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.212 416.048 4.236 ; + END + END rw0_wmask_in[553] + PIN rw0_wmask_in[554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.308 416.048 4.332 ; + END + END rw0_wmask_in[554] + PIN rw0_wmask_in[555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.404 416.048 4.428 ; + END + END rw0_wmask_in[555] + PIN rw0_wmask_in[556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.500 416.048 4.524 ; + END + END rw0_wmask_in[556] + PIN rw0_wmask_in[557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.596 416.048 4.620 ; + END + END rw0_wmask_in[557] + PIN rw0_wmask_in[558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.692 416.048 4.716 ; + END + END rw0_wmask_in[558] + PIN rw0_wmask_in[559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.788 416.048 4.812 ; + END + END rw0_wmask_in[559] + PIN rw0_wmask_in[560] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.884 416.048 4.908 ; + END + END rw0_wmask_in[560] + PIN rw0_wmask_in[561] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 4.980 416.048 5.004 ; + END + END rw0_wmask_in[561] + PIN rw0_wmask_in[562] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.076 416.048 5.100 ; + END + END rw0_wmask_in[562] + PIN rw0_wmask_in[563] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.172 416.048 5.196 ; + END + END rw0_wmask_in[563] + PIN rw0_wmask_in[564] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.268 416.048 5.292 ; + END + END rw0_wmask_in[564] + PIN rw0_wmask_in[565] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.364 416.048 5.388 ; + END + END rw0_wmask_in[565] + PIN rw0_wmask_in[566] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.460 416.048 5.484 ; + END + END rw0_wmask_in[566] + PIN rw0_wmask_in[567] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.556 416.048 5.580 ; + END + END rw0_wmask_in[567] + PIN rw0_wmask_in[568] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.652 416.048 5.676 ; + END + END rw0_wmask_in[568] + PIN rw0_wmask_in[569] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.748 416.048 5.772 ; + END + END rw0_wmask_in[569] + PIN rw0_wmask_in[570] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.844 416.048 5.868 ; + END + END rw0_wmask_in[570] + PIN rw0_wmask_in[571] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 5.940 416.048 5.964 ; + END + END rw0_wmask_in[571] + PIN rw0_wmask_in[572] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.036 416.048 6.060 ; + END + END rw0_wmask_in[572] + PIN rw0_wmask_in[573] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.132 416.048 6.156 ; + END + END rw0_wmask_in[573] + PIN rw0_wmask_in[574] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.228 416.048 6.252 ; + END + END rw0_wmask_in[574] + PIN rw0_wmask_in[575] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.324 416.048 6.348 ; + END + END rw0_wmask_in[575] + PIN rw0_wmask_in[576] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.420 416.048 6.444 ; + END + END rw0_wmask_in[576] + PIN rw0_wmask_in[577] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.516 416.048 6.540 ; + END + END rw0_wmask_in[577] + PIN rw0_wmask_in[578] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.612 416.048 6.636 ; + END + END rw0_wmask_in[578] + PIN rw0_wmask_in[579] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.708 416.048 6.732 ; + END + END rw0_wmask_in[579] + PIN rw0_wmask_in[580] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.804 416.048 6.828 ; + END + END rw0_wmask_in[580] + PIN rw0_wmask_in[581] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.900 416.048 6.924 ; + END + END rw0_wmask_in[581] + PIN rw0_wmask_in[582] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 6.996 416.048 7.020 ; + END + END rw0_wmask_in[582] + PIN rw0_wmask_in[583] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.092 416.048 7.116 ; + END + END rw0_wmask_in[583] + PIN rw0_wmask_in[584] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.188 416.048 7.212 ; + END + END rw0_wmask_in[584] + PIN rw0_wmask_in[585] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.284 416.048 7.308 ; + END + END rw0_wmask_in[585] + PIN rw0_wmask_in[586] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.380 416.048 7.404 ; + END + END rw0_wmask_in[586] + PIN rw0_wmask_in[587] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.476 416.048 7.500 ; + END + END rw0_wmask_in[587] + PIN rw0_wmask_in[588] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.572 416.048 7.596 ; + END + END rw0_wmask_in[588] + PIN rw0_wmask_in[589] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.668 416.048 7.692 ; + END + END rw0_wmask_in[589] + PIN rw0_wmask_in[590] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.764 416.048 7.788 ; + END + END rw0_wmask_in[590] + PIN rw0_wmask_in[591] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.860 416.048 7.884 ; + END + END rw0_wmask_in[591] + PIN rw0_wmask_in[592] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 7.956 416.048 7.980 ; + END + END rw0_wmask_in[592] + PIN rw0_wmask_in[593] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.052 416.048 8.076 ; + END + END rw0_wmask_in[593] + PIN rw0_wmask_in[594] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.148 416.048 8.172 ; + END + END rw0_wmask_in[594] + PIN rw0_wmask_in[595] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.244 416.048 8.268 ; + END + END rw0_wmask_in[595] + PIN rw0_wmask_in[596] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.340 416.048 8.364 ; + END + END rw0_wmask_in[596] + PIN rw0_wmask_in[597] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.436 416.048 8.460 ; + END + END rw0_wmask_in[597] + PIN rw0_wmask_in[598] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.532 416.048 8.556 ; + END + END rw0_wmask_in[598] + PIN rw0_wmask_in[599] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.628 416.048 8.652 ; + END + END rw0_wmask_in[599] + PIN rw0_wmask_in[600] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.724 416.048 8.748 ; + END + END rw0_wmask_in[600] + PIN rw0_wmask_in[601] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.820 416.048 8.844 ; + END + END rw0_wmask_in[601] + PIN rw0_wmask_in[602] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 8.916 416.048 8.940 ; + END + END rw0_wmask_in[602] + PIN rw0_wmask_in[603] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.012 416.048 9.036 ; + END + END rw0_wmask_in[603] + PIN rw0_wmask_in[604] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.108 416.048 9.132 ; + END + END rw0_wmask_in[604] + PIN rw0_wmask_in[605] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.204 416.048 9.228 ; + END + END rw0_wmask_in[605] + PIN rw0_wmask_in[606] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.300 416.048 9.324 ; + END + END rw0_wmask_in[606] + PIN rw0_wmask_in[607] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.396 416.048 9.420 ; + END + END rw0_wmask_in[607] + PIN rw0_wmask_in[608] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.492 416.048 9.516 ; + END + END rw0_wmask_in[608] + PIN rw0_wmask_in[609] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.588 416.048 9.612 ; + END + END rw0_wmask_in[609] + PIN rw0_wmask_in[610] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.684 416.048 9.708 ; + END + END rw0_wmask_in[610] + PIN rw0_wmask_in[611] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.780 416.048 9.804 ; + END + END rw0_wmask_in[611] + PIN rw0_wmask_in[612] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.876 416.048 9.900 ; + END + END rw0_wmask_in[612] + PIN rw0_wmask_in[613] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 9.972 416.048 9.996 ; + END + END rw0_wmask_in[613] + PIN rw0_wmask_in[614] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.068 416.048 10.092 ; + END + END rw0_wmask_in[614] + PIN rw0_wmask_in[615] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.164 416.048 10.188 ; + END + END rw0_wmask_in[615] + PIN rw0_wmask_in[616] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.260 416.048 10.284 ; + END + END rw0_wmask_in[616] + PIN rw0_wmask_in[617] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.356 416.048 10.380 ; + END + END rw0_wmask_in[617] + PIN rw0_wmask_in[618] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.452 416.048 10.476 ; + END + END rw0_wmask_in[618] + PIN rw0_wmask_in[619] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.548 416.048 10.572 ; + END + END rw0_wmask_in[619] + PIN rw0_wmask_in[620] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.644 416.048 10.668 ; + END + END rw0_wmask_in[620] + PIN rw0_wmask_in[621] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.740 416.048 10.764 ; + END + END rw0_wmask_in[621] + PIN rw0_wmask_in[622] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.836 416.048 10.860 ; + END + END rw0_wmask_in[622] + PIN rw0_wmask_in[623] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 10.932 416.048 10.956 ; + END + END rw0_wmask_in[623] + PIN rw0_wmask_in[624] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.028 416.048 11.052 ; + END + END rw0_wmask_in[624] + PIN rw0_wmask_in[625] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.124 416.048 11.148 ; + END + END rw0_wmask_in[625] + PIN rw0_wmask_in[626] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.220 416.048 11.244 ; + END + END rw0_wmask_in[626] + PIN rw0_wmask_in[627] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.316 416.048 11.340 ; + END + END rw0_wmask_in[627] + PIN rw0_wmask_in[628] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.412 416.048 11.436 ; + END + END rw0_wmask_in[628] + PIN rw0_wmask_in[629] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.508 416.048 11.532 ; + END + END rw0_wmask_in[629] + PIN rw0_wmask_in[630] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.604 416.048 11.628 ; + END + END rw0_wmask_in[630] + PIN rw0_wmask_in[631] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.700 416.048 11.724 ; + END + END rw0_wmask_in[631] + PIN rw0_wmask_in[632] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.796 416.048 11.820 ; + END + END rw0_wmask_in[632] + PIN rw0_wmask_in[633] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.892 416.048 11.916 ; + END + END rw0_wmask_in[633] + PIN rw0_wmask_in[634] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 11.988 416.048 12.012 ; + END + END rw0_wmask_in[634] + PIN rw0_wmask_in[635] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.084 416.048 12.108 ; + END + END rw0_wmask_in[635] + PIN rw0_wmask_in[636] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.180 416.048 12.204 ; + END + END rw0_wmask_in[636] + PIN rw0_wmask_in[637] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.276 416.048 12.300 ; + END + END rw0_wmask_in[637] + PIN rw0_wmask_in[638] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.372 416.048 12.396 ; + END + END rw0_wmask_in[638] + PIN rw0_wmask_in[639] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.468 416.048 12.492 ; + END + END rw0_wmask_in[639] + PIN rw0_wmask_in[640] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.564 416.048 12.588 ; + END + END rw0_wmask_in[640] + PIN rw0_wmask_in[641] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.660 416.048 12.684 ; + END + END rw0_wmask_in[641] + PIN rw0_wmask_in[642] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.756 416.048 12.780 ; + END + END rw0_wmask_in[642] + PIN rw0_wmask_in[643] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.852 416.048 12.876 ; + END + END rw0_wmask_in[643] + PIN rw0_wmask_in[644] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 12.948 416.048 12.972 ; + END + END rw0_wmask_in[644] + PIN rw0_wmask_in[645] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.044 416.048 13.068 ; + END + END rw0_wmask_in[645] + PIN rw0_wmask_in[646] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.140 416.048 13.164 ; + END + END rw0_wmask_in[646] + PIN rw0_wmask_in[647] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.236 416.048 13.260 ; + END + END rw0_wmask_in[647] + PIN rw0_wmask_in[648] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.332 416.048 13.356 ; + END + END rw0_wmask_in[648] + PIN rw0_wmask_in[649] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.428 416.048 13.452 ; + END + END rw0_wmask_in[649] + PIN rw0_wmask_in[650] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.524 416.048 13.548 ; + END + END rw0_wmask_in[650] + PIN rw0_wmask_in[651] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.620 416.048 13.644 ; + END + END rw0_wmask_in[651] + PIN rw0_wmask_in[652] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.716 416.048 13.740 ; + END + END rw0_wmask_in[652] + PIN rw0_wmask_in[653] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.812 416.048 13.836 ; + END + END rw0_wmask_in[653] + PIN rw0_wmask_in[654] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 13.908 416.048 13.932 ; + END + END rw0_wmask_in[654] + PIN rw0_wmask_in[655] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.004 416.048 14.028 ; + END + END rw0_wmask_in[655] + PIN rw0_wmask_in[656] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.100 416.048 14.124 ; + END + END rw0_wmask_in[656] + PIN rw0_wmask_in[657] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.196 416.048 14.220 ; + END + END rw0_wmask_in[657] + PIN rw0_wmask_in[658] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.292 416.048 14.316 ; + END + END rw0_wmask_in[658] + PIN rw0_wmask_in[659] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.388 416.048 14.412 ; + END + END rw0_wmask_in[659] + PIN rw0_wmask_in[660] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.484 416.048 14.508 ; + END + END rw0_wmask_in[660] + PIN rw0_wmask_in[661] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.580 416.048 14.604 ; + END + END rw0_wmask_in[661] + PIN rw0_wmask_in[662] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.676 416.048 14.700 ; + END + END rw0_wmask_in[662] + PIN rw0_wmask_in[663] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.772 416.048 14.796 ; + END + END rw0_wmask_in[663] + PIN rw0_wmask_in[664] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.868 416.048 14.892 ; + END + END rw0_wmask_in[664] + PIN rw0_wmask_in[665] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 14.964 416.048 14.988 ; + END + END rw0_wmask_in[665] + PIN rw0_wmask_in[666] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.060 416.048 15.084 ; + END + END rw0_wmask_in[666] + PIN rw0_wmask_in[667] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.156 416.048 15.180 ; + END + END rw0_wmask_in[667] + PIN rw0_wmask_in[668] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.252 416.048 15.276 ; + END + END rw0_wmask_in[668] + PIN rw0_wmask_in[669] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.348 416.048 15.372 ; + END + END rw0_wmask_in[669] + PIN rw0_wmask_in[670] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.444 416.048 15.468 ; + END + END rw0_wmask_in[670] + PIN rw0_wmask_in[671] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.540 416.048 15.564 ; + END + END rw0_wmask_in[671] + PIN rw0_wmask_in[672] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.636 416.048 15.660 ; + END + END rw0_wmask_in[672] + PIN rw0_wmask_in[673] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.732 416.048 15.756 ; + END + END rw0_wmask_in[673] + PIN rw0_wmask_in[674] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.828 416.048 15.852 ; + END + END rw0_wmask_in[674] + PIN rw0_wmask_in[675] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 15.924 416.048 15.948 ; + END + END rw0_wmask_in[675] + PIN rw0_wmask_in[676] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.020 416.048 16.044 ; + END + END rw0_wmask_in[676] + PIN rw0_wmask_in[677] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.116 416.048 16.140 ; + END + END rw0_wmask_in[677] + PIN rw0_wmask_in[678] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.212 416.048 16.236 ; + END + END rw0_wmask_in[678] + PIN rw0_wmask_in[679] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.308 416.048 16.332 ; + END + END rw0_wmask_in[679] + PIN rw0_wmask_in[680] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.404 416.048 16.428 ; + END + END rw0_wmask_in[680] + PIN rw0_wmask_in[681] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.500 416.048 16.524 ; + END + END rw0_wmask_in[681] + PIN rw0_wmask_in[682] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.596 416.048 16.620 ; + END + END rw0_wmask_in[682] + PIN rw0_wmask_in[683] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.692 416.048 16.716 ; + END + END rw0_wmask_in[683] + PIN rw0_wmask_in[684] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.788 416.048 16.812 ; + END + END rw0_wmask_in[684] + PIN rw0_wmask_in[685] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.884 416.048 16.908 ; + END + END rw0_wmask_in[685] + PIN rw0_wmask_in[686] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 16.980 416.048 17.004 ; + END + END rw0_wmask_in[686] + PIN rw0_wmask_in[687] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.076 416.048 17.100 ; + END + END rw0_wmask_in[687] + PIN rw0_wmask_in[688] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.172 416.048 17.196 ; + END + END rw0_wmask_in[688] + PIN rw0_wmask_in[689] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.268 416.048 17.292 ; + END + END rw0_wmask_in[689] + PIN rw0_wmask_in[690] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.364 416.048 17.388 ; + END + END rw0_wmask_in[690] + PIN rw0_wmask_in[691] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.460 416.048 17.484 ; + END + END rw0_wmask_in[691] + PIN rw0_wmask_in[692] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.556 416.048 17.580 ; + END + END rw0_wmask_in[692] + PIN rw0_wmask_in[693] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.652 416.048 17.676 ; + END + END rw0_wmask_in[693] + PIN rw0_wmask_in[694] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.748 416.048 17.772 ; + END + END rw0_wmask_in[694] + PIN rw0_wmask_in[695] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.844 416.048 17.868 ; + END + END rw0_wmask_in[695] + PIN rw0_wmask_in[696] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 17.940 416.048 17.964 ; + END + END rw0_wmask_in[696] + PIN rw0_wmask_in[697] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.036 416.048 18.060 ; + END + END rw0_wmask_in[697] + PIN rw0_wmask_in[698] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.132 416.048 18.156 ; + END + END rw0_wmask_in[698] + PIN rw0_wmask_in[699] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.228 416.048 18.252 ; + END + END rw0_wmask_in[699] + PIN rw0_wmask_in[700] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.324 416.048 18.348 ; + END + END rw0_wmask_in[700] + PIN rw0_wmask_in[701] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.420 416.048 18.444 ; + END + END rw0_wmask_in[701] + PIN rw0_wmask_in[702] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.516 416.048 18.540 ; + END + END rw0_wmask_in[702] + PIN rw0_wmask_in[703] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.612 416.048 18.636 ; + END + END rw0_wmask_in[703] + PIN rw0_wmask_in[704] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.708 416.048 18.732 ; + END + END rw0_wmask_in[704] + PIN rw0_wmask_in[705] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.804 416.048 18.828 ; + END + END rw0_wmask_in[705] + PIN rw0_wmask_in[706] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.900 416.048 18.924 ; + END + END rw0_wmask_in[706] + PIN rw0_wmask_in[707] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 18.996 416.048 19.020 ; + END + END rw0_wmask_in[707] + PIN rw0_wmask_in[708] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.092 416.048 19.116 ; + END + END rw0_wmask_in[708] + PIN rw0_wmask_in[709] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.188 416.048 19.212 ; + END + END rw0_wmask_in[709] + PIN rw0_wmask_in[710] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.284 416.048 19.308 ; + END + END rw0_wmask_in[710] + PIN rw0_wmask_in[711] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.380 416.048 19.404 ; + END + END rw0_wmask_in[711] + PIN rw0_wmask_in[712] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.476 416.048 19.500 ; + END + END rw0_wmask_in[712] + PIN rw0_wmask_in[713] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.572 416.048 19.596 ; + END + END rw0_wmask_in[713] + PIN rw0_wmask_in[714] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.668 416.048 19.692 ; + END + END rw0_wmask_in[714] + PIN rw0_wmask_in[715] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.764 416.048 19.788 ; + END + END rw0_wmask_in[715] + PIN rw0_wmask_in[716] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.860 416.048 19.884 ; + END + END rw0_wmask_in[716] + PIN rw0_wmask_in[717] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 19.956 416.048 19.980 ; + END + END rw0_wmask_in[717] + PIN rw0_wmask_in[718] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.052 416.048 20.076 ; + END + END rw0_wmask_in[718] + PIN rw0_wmask_in[719] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.148 416.048 20.172 ; + END + END rw0_wmask_in[719] + PIN rw0_wmask_in[720] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.244 416.048 20.268 ; + END + END rw0_wmask_in[720] + PIN rw0_wmask_in[721] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.340 416.048 20.364 ; + END + END rw0_wmask_in[721] + PIN rw0_wmask_in[722] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.436 416.048 20.460 ; + END + END rw0_wmask_in[722] + PIN rw0_wmask_in[723] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.532 416.048 20.556 ; + END + END rw0_wmask_in[723] + PIN rw0_wmask_in[724] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.628 416.048 20.652 ; + END + END rw0_wmask_in[724] + PIN rw0_wmask_in[725] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.724 416.048 20.748 ; + END + END rw0_wmask_in[725] + PIN rw0_wmask_in[726] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.820 416.048 20.844 ; + END + END rw0_wmask_in[726] + PIN rw0_wmask_in[727] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 20.916 416.048 20.940 ; + END + END rw0_wmask_in[727] + PIN rw0_wmask_in[728] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.012 416.048 21.036 ; + END + END rw0_wmask_in[728] + PIN rw0_wmask_in[729] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.108 416.048 21.132 ; + END + END rw0_wmask_in[729] + PIN rw0_wmask_in[730] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.204 416.048 21.228 ; + END + END rw0_wmask_in[730] + PIN rw0_wmask_in[731] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.300 416.048 21.324 ; + END + END rw0_wmask_in[731] + PIN rw0_wmask_in[732] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.396 416.048 21.420 ; + END + END rw0_wmask_in[732] + PIN rw0_wmask_in[733] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.492 416.048 21.516 ; + END + END rw0_wmask_in[733] + PIN rw0_wmask_in[734] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.588 416.048 21.612 ; + END + END rw0_wmask_in[734] + PIN rw0_wmask_in[735] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.684 416.048 21.708 ; + END + END rw0_wmask_in[735] + PIN rw0_wmask_in[736] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.780 416.048 21.804 ; + END + END rw0_wmask_in[736] + PIN rw0_wmask_in[737] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.876 416.048 21.900 ; + END + END rw0_wmask_in[737] + PIN rw0_wmask_in[738] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 21.972 416.048 21.996 ; + END + END rw0_wmask_in[738] + PIN rw0_wmask_in[739] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.068 416.048 22.092 ; + END + END rw0_wmask_in[739] + PIN rw0_wmask_in[740] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.164 416.048 22.188 ; + END + END rw0_wmask_in[740] + PIN rw0_wmask_in[741] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.260 416.048 22.284 ; + END + END rw0_wmask_in[741] + PIN rw0_wmask_in[742] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.356 416.048 22.380 ; + END + END rw0_wmask_in[742] + PIN rw0_wmask_in[743] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.452 416.048 22.476 ; + END + END rw0_wmask_in[743] + PIN rw0_wmask_in[744] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.548 416.048 22.572 ; + END + END rw0_wmask_in[744] + PIN rw0_wmask_in[745] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.644 416.048 22.668 ; + END + END rw0_wmask_in[745] + PIN rw0_wmask_in[746] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.740 416.048 22.764 ; + END + END rw0_wmask_in[746] + PIN rw0_wmask_in[747] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.836 416.048 22.860 ; + END + END rw0_wmask_in[747] + PIN rw0_wmask_in[748] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 22.932 416.048 22.956 ; + END + END rw0_wmask_in[748] + PIN rw0_wmask_in[749] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.028 416.048 23.052 ; + END + END rw0_wmask_in[749] + PIN rw0_wmask_in[750] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.124 416.048 23.148 ; + END + END rw0_wmask_in[750] + PIN rw0_wmask_in[751] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.220 416.048 23.244 ; + END + END rw0_wmask_in[751] + PIN rw0_wmask_in[752] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.316 416.048 23.340 ; + END + END rw0_wmask_in[752] + PIN rw0_wmask_in[753] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.412 416.048 23.436 ; + END + END rw0_wmask_in[753] + PIN rw0_wmask_in[754] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.508 416.048 23.532 ; + END + END rw0_wmask_in[754] + PIN rw0_wmask_in[755] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.604 416.048 23.628 ; + END + END rw0_wmask_in[755] + PIN rw0_wmask_in[756] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.700 416.048 23.724 ; + END + END rw0_wmask_in[756] + PIN rw0_wmask_in[757] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.796 416.048 23.820 ; + END + END rw0_wmask_in[757] + PIN rw0_wmask_in[758] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.892 416.048 23.916 ; + END + END rw0_wmask_in[758] + PIN rw0_wmask_in[759] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 23.988 416.048 24.012 ; + END + END rw0_wmask_in[759] + PIN rw0_wmask_in[760] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.084 416.048 24.108 ; + END + END rw0_wmask_in[760] + PIN rw0_wmask_in[761] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.180 416.048 24.204 ; + END + END rw0_wmask_in[761] + PIN rw0_wmask_in[762] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.276 416.048 24.300 ; + END + END rw0_wmask_in[762] + PIN rw0_wmask_in[763] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.372 416.048 24.396 ; + END + END rw0_wmask_in[763] + PIN rw0_wmask_in[764] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.468 416.048 24.492 ; + END + END rw0_wmask_in[764] + PIN rw0_wmask_in[765] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.564 416.048 24.588 ; + END + END rw0_wmask_in[765] + PIN rw0_wmask_in[766] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.660 416.048 24.684 ; + END + END rw0_wmask_in[766] + PIN rw0_wmask_in[767] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.756 416.048 24.780 ; + END + END rw0_wmask_in[767] + PIN rw0_wmask_in[768] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.852 416.048 24.876 ; + END + END rw0_wmask_in[768] + PIN rw0_wmask_in[769] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 24.948 416.048 24.972 ; + END + END rw0_wmask_in[769] + PIN rw0_wmask_in[770] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.044 416.048 25.068 ; + END + END rw0_wmask_in[770] + PIN rw0_wmask_in[771] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.140 416.048 25.164 ; + END + END rw0_wmask_in[771] + PIN rw0_wmask_in[772] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.236 416.048 25.260 ; + END + END rw0_wmask_in[772] + PIN rw0_wmask_in[773] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.332 416.048 25.356 ; + END + END rw0_wmask_in[773] + PIN rw0_wmask_in[774] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.428 416.048 25.452 ; + END + END rw0_wmask_in[774] + PIN rw0_wmask_in[775] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.524 416.048 25.548 ; + END + END rw0_wmask_in[775] + PIN rw0_wmask_in[776] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.620 416.048 25.644 ; + END + END rw0_wmask_in[776] + PIN rw0_wmask_in[777] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.716 416.048 25.740 ; + END + END rw0_wmask_in[777] + PIN rw0_wmask_in[778] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.812 416.048 25.836 ; + END + END rw0_wmask_in[778] + PIN rw0_wmask_in[779] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 25.908 416.048 25.932 ; + END + END rw0_wmask_in[779] + PIN rw0_wmask_in[780] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.004 416.048 26.028 ; + END + END rw0_wmask_in[780] + PIN rw0_wmask_in[781] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.100 416.048 26.124 ; + END + END rw0_wmask_in[781] + PIN rw0_wmask_in[782] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.196 416.048 26.220 ; + END + END rw0_wmask_in[782] + PIN rw0_wmask_in[783] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.292 416.048 26.316 ; + END + END rw0_wmask_in[783] + PIN rw0_wmask_in[784] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.388 416.048 26.412 ; + END + END rw0_wmask_in[784] + PIN rw0_wmask_in[785] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.484 416.048 26.508 ; + END + END rw0_wmask_in[785] + PIN rw0_wmask_in[786] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.580 416.048 26.604 ; + END + END rw0_wmask_in[786] + PIN rw0_wmask_in[787] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.676 416.048 26.700 ; + END + END rw0_wmask_in[787] + PIN rw0_wmask_in[788] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.772 416.048 26.796 ; + END + END rw0_wmask_in[788] + PIN rw0_wmask_in[789] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.868 416.048 26.892 ; + END + END rw0_wmask_in[789] + PIN rw0_wmask_in[790] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 26.964 416.048 26.988 ; + END + END rw0_wmask_in[790] + PIN rw0_wmask_in[791] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.060 416.048 27.084 ; + END + END rw0_wmask_in[791] + PIN rw0_wmask_in[792] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.156 416.048 27.180 ; + END + END rw0_wmask_in[792] + PIN rw0_wmask_in[793] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.252 416.048 27.276 ; + END + END rw0_wmask_in[793] + PIN rw0_wmask_in[794] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.348 416.048 27.372 ; + END + END rw0_wmask_in[794] + PIN rw0_wmask_in[795] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.444 416.048 27.468 ; + END + END rw0_wmask_in[795] + PIN rw0_wmask_in[796] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.540 416.048 27.564 ; + END + END rw0_wmask_in[796] + PIN rw0_wmask_in[797] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.636 416.048 27.660 ; + END + END rw0_wmask_in[797] + PIN rw0_wmask_in[798] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.732 416.048 27.756 ; + END + END rw0_wmask_in[798] + PIN rw0_wmask_in[799] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.828 416.048 27.852 ; + END + END rw0_wmask_in[799] + PIN rw0_wmask_in[800] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 27.924 416.048 27.948 ; + END + END rw0_wmask_in[800] + PIN rw0_wmask_in[801] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.020 416.048 28.044 ; + END + END rw0_wmask_in[801] + PIN rw0_wmask_in[802] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.116 416.048 28.140 ; + END + END rw0_wmask_in[802] + PIN rw0_wmask_in[803] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.212 416.048 28.236 ; + END + END rw0_wmask_in[803] + PIN rw0_wmask_in[804] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.308 416.048 28.332 ; + END + END rw0_wmask_in[804] + PIN rw0_wmask_in[805] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.404 416.048 28.428 ; + END + END rw0_wmask_in[805] + PIN rw0_wmask_in[806] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.500 416.048 28.524 ; + END + END rw0_wmask_in[806] + PIN rw0_wmask_in[807] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.596 416.048 28.620 ; + END + END rw0_wmask_in[807] + PIN rw0_wmask_in[808] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.692 416.048 28.716 ; + END + END rw0_wmask_in[808] + PIN rw0_wmask_in[809] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.788 416.048 28.812 ; + END + END rw0_wmask_in[809] + PIN rw0_wmask_in[810] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.884 416.048 28.908 ; + END + END rw0_wmask_in[810] + PIN rw0_wmask_in[811] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 28.980 416.048 29.004 ; + END + END rw0_wmask_in[811] + PIN rw0_wmask_in[812] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.076 416.048 29.100 ; + END + END rw0_wmask_in[812] + PIN rw0_wmask_in[813] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.172 416.048 29.196 ; + END + END rw0_wmask_in[813] + PIN rw0_wmask_in[814] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.268 416.048 29.292 ; + END + END rw0_wmask_in[814] + PIN rw0_wmask_in[815] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.364 416.048 29.388 ; + END + END rw0_wmask_in[815] + PIN rw0_wmask_in[816] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.460 416.048 29.484 ; + END + END rw0_wmask_in[816] + PIN rw0_wmask_in[817] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.556 416.048 29.580 ; + END + END rw0_wmask_in[817] + PIN rw0_wmask_in[818] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.652 416.048 29.676 ; + END + END rw0_wmask_in[818] + PIN rw0_wmask_in[819] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.748 416.048 29.772 ; + END + END rw0_wmask_in[819] + PIN rw0_wmask_in[820] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.844 416.048 29.868 ; + END + END rw0_wmask_in[820] + PIN rw0_wmask_in[821] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 29.940 416.048 29.964 ; + END + END rw0_wmask_in[821] + PIN rw0_wmask_in[822] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.036 416.048 30.060 ; + END + END rw0_wmask_in[822] + PIN rw0_wmask_in[823] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.132 416.048 30.156 ; + END + END rw0_wmask_in[823] + PIN rw0_wmask_in[824] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.228 416.048 30.252 ; + END + END rw0_wmask_in[824] + PIN rw0_wmask_in[825] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.324 416.048 30.348 ; + END + END rw0_wmask_in[825] + PIN rw0_wmask_in[826] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.420 416.048 30.444 ; + END + END rw0_wmask_in[826] + PIN rw0_wmask_in[827] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.516 416.048 30.540 ; + END + END rw0_wmask_in[827] + PIN rw0_wmask_in[828] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.612 416.048 30.636 ; + END + END rw0_wmask_in[828] + PIN rw0_wmask_in[829] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.708 416.048 30.732 ; + END + END rw0_wmask_in[829] + PIN rw0_wmask_in[830] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.804 416.048 30.828 ; + END + END rw0_wmask_in[830] + PIN rw0_wmask_in[831] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.900 416.048 30.924 ; + END + END rw0_wmask_in[831] + PIN rw0_wmask_in[832] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 30.996 416.048 31.020 ; + END + END rw0_wmask_in[832] + PIN rw0_wmask_in[833] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.092 416.048 31.116 ; + END + END rw0_wmask_in[833] + PIN rw0_wmask_in[834] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.188 416.048 31.212 ; + END + END rw0_wmask_in[834] + PIN rw0_wmask_in[835] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.284 416.048 31.308 ; + END + END rw0_wmask_in[835] + PIN rw0_wmask_in[836] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.380 416.048 31.404 ; + END + END rw0_wmask_in[836] + PIN rw0_wmask_in[837] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.476 416.048 31.500 ; + END + END rw0_wmask_in[837] + PIN rw0_wmask_in[838] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.572 416.048 31.596 ; + END + END rw0_wmask_in[838] + PIN rw0_wmask_in[839] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.668 416.048 31.692 ; + END + END rw0_wmask_in[839] + PIN rw0_wmask_in[840] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.764 416.048 31.788 ; + END + END rw0_wmask_in[840] + PIN rw0_wmask_in[841] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.860 416.048 31.884 ; + END + END rw0_wmask_in[841] + PIN rw0_wmask_in[842] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 31.956 416.048 31.980 ; + END + END rw0_wmask_in[842] + PIN rw0_wmask_in[843] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.052 416.048 32.076 ; + END + END rw0_wmask_in[843] + PIN rw0_wmask_in[844] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.148 416.048 32.172 ; + END + END rw0_wmask_in[844] + PIN rw0_wmask_in[845] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.244 416.048 32.268 ; + END + END rw0_wmask_in[845] + PIN rw0_wmask_in[846] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.340 416.048 32.364 ; + END + END rw0_wmask_in[846] + PIN rw0_wmask_in[847] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.436 416.048 32.460 ; + END + END rw0_wmask_in[847] + PIN rw0_wmask_in[848] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.532 416.048 32.556 ; + END + END rw0_wmask_in[848] + PIN rw0_wmask_in[849] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.628 416.048 32.652 ; + END + END rw0_wmask_in[849] + PIN rw0_wmask_in[850] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.724 416.048 32.748 ; + END + END rw0_wmask_in[850] + PIN rw0_wmask_in[851] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.820 416.048 32.844 ; + END + END rw0_wmask_in[851] + PIN rw0_wmask_in[852] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 32.916 416.048 32.940 ; + END + END rw0_wmask_in[852] + PIN rw0_wmask_in[853] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.012 416.048 33.036 ; + END + END rw0_wmask_in[853] + PIN rw0_wmask_in[854] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.108 416.048 33.132 ; + END + END rw0_wmask_in[854] + PIN rw0_wmask_in[855] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.204 416.048 33.228 ; + END + END rw0_wmask_in[855] + PIN rw0_wmask_in[856] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.300 416.048 33.324 ; + END + END rw0_wmask_in[856] + PIN rw0_wmask_in[857] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.396 416.048 33.420 ; + END + END rw0_wmask_in[857] + PIN rw0_wmask_in[858] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.492 416.048 33.516 ; + END + END rw0_wmask_in[858] + PIN rw0_wmask_in[859] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.588 416.048 33.612 ; + END + END rw0_wmask_in[859] + PIN rw0_wmask_in[860] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.684 416.048 33.708 ; + END + END rw0_wmask_in[860] + PIN rw0_wmask_in[861] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.780 416.048 33.804 ; + END + END rw0_wmask_in[861] + PIN rw0_wmask_in[862] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.876 416.048 33.900 ; + END + END rw0_wmask_in[862] + PIN rw0_wmask_in[863] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 33.972 416.048 33.996 ; + END + END rw0_wmask_in[863] + PIN rw0_wmask_in[864] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.068 416.048 34.092 ; + END + END rw0_wmask_in[864] + PIN rw0_wmask_in[865] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.164 416.048 34.188 ; + END + END rw0_wmask_in[865] + PIN rw0_wmask_in[866] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.260 416.048 34.284 ; + END + END rw0_wmask_in[866] + PIN rw0_wmask_in[867] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.356 416.048 34.380 ; + END + END rw0_wmask_in[867] + PIN rw0_wmask_in[868] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.452 416.048 34.476 ; + END + END rw0_wmask_in[868] + PIN rw0_wmask_in[869] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.548 416.048 34.572 ; + END + END rw0_wmask_in[869] + PIN rw0_wmask_in[870] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.644 416.048 34.668 ; + END + END rw0_wmask_in[870] + PIN rw0_wmask_in[871] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.740 416.048 34.764 ; + END + END rw0_wmask_in[871] + PIN rw0_wmask_in[872] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.836 416.048 34.860 ; + END + END rw0_wmask_in[872] + PIN rw0_wmask_in[873] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 34.932 416.048 34.956 ; + END + END rw0_wmask_in[873] + PIN rw0_wmask_in[874] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.028 416.048 35.052 ; + END + END rw0_wmask_in[874] + PIN rw0_wmask_in[875] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.124 416.048 35.148 ; + END + END rw0_wmask_in[875] + PIN rw0_wmask_in[876] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.220 416.048 35.244 ; + END + END rw0_wmask_in[876] + PIN rw0_wmask_in[877] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.316 416.048 35.340 ; + END + END rw0_wmask_in[877] + PIN rw0_wmask_in[878] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.412 416.048 35.436 ; + END + END rw0_wmask_in[878] + PIN rw0_wmask_in[879] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.508 416.048 35.532 ; + END + END rw0_wmask_in[879] + PIN rw0_wmask_in[880] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.604 416.048 35.628 ; + END + END rw0_wmask_in[880] + PIN rw0_wmask_in[881] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.700 416.048 35.724 ; + END + END rw0_wmask_in[881] + PIN rw0_wmask_in[882] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.796 416.048 35.820 ; + END + END rw0_wmask_in[882] + PIN rw0_wmask_in[883] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.892 416.048 35.916 ; + END + END rw0_wmask_in[883] + PIN rw0_wmask_in[884] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 35.988 416.048 36.012 ; + END + END rw0_wmask_in[884] + PIN rw0_wmask_in[885] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.084 416.048 36.108 ; + END + END rw0_wmask_in[885] + PIN rw0_wmask_in[886] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.180 416.048 36.204 ; + END + END rw0_wmask_in[886] + PIN rw0_wmask_in[887] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.276 416.048 36.300 ; + END + END rw0_wmask_in[887] + PIN rw0_wmask_in[888] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.372 416.048 36.396 ; + END + END rw0_wmask_in[888] + PIN rw0_wmask_in[889] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.468 416.048 36.492 ; + END + END rw0_wmask_in[889] + PIN rw0_wmask_in[890] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.564 416.048 36.588 ; + END + END rw0_wmask_in[890] + PIN rw0_wmask_in[891] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.660 416.048 36.684 ; + END + END rw0_wmask_in[891] + PIN rw0_wmask_in[892] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.756 416.048 36.780 ; + END + END rw0_wmask_in[892] + PIN rw0_wmask_in[893] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.852 416.048 36.876 ; + END + END rw0_wmask_in[893] + PIN rw0_wmask_in[894] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 36.948 416.048 36.972 ; + END + END rw0_wmask_in[894] + PIN rw0_wmask_in[895] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.044 416.048 37.068 ; + END + END rw0_wmask_in[895] + PIN rw0_wmask_in[896] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.140 416.048 37.164 ; + END + END rw0_wmask_in[896] + PIN rw0_wmask_in[897] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.236 416.048 37.260 ; + END + END rw0_wmask_in[897] + PIN rw0_wmask_in[898] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.332 416.048 37.356 ; + END + END rw0_wmask_in[898] + PIN rw0_wmask_in[899] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.428 416.048 37.452 ; + END + END rw0_wmask_in[899] + PIN rw0_wmask_in[900] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.524 416.048 37.548 ; + END + END rw0_wmask_in[900] + PIN rw0_wmask_in[901] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.620 416.048 37.644 ; + END + END rw0_wmask_in[901] + PIN rw0_wmask_in[902] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.716 416.048 37.740 ; + END + END rw0_wmask_in[902] + PIN rw0_wmask_in[903] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.812 416.048 37.836 ; + END + END rw0_wmask_in[903] + PIN rw0_wmask_in[904] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 37.908 416.048 37.932 ; + END + END rw0_wmask_in[904] + PIN rw0_wmask_in[905] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.004 416.048 38.028 ; + END + END rw0_wmask_in[905] + PIN rw0_wmask_in[906] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.100 416.048 38.124 ; + END + END rw0_wmask_in[906] + PIN rw0_wmask_in[907] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.196 416.048 38.220 ; + END + END rw0_wmask_in[907] + PIN rw0_wmask_in[908] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.292 416.048 38.316 ; + END + END rw0_wmask_in[908] + PIN rw0_wmask_in[909] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.388 416.048 38.412 ; + END + END rw0_wmask_in[909] + PIN rw0_wmask_in[910] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.484 416.048 38.508 ; + END + END rw0_wmask_in[910] + PIN rw0_wmask_in[911] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.580 416.048 38.604 ; + END + END rw0_wmask_in[911] + PIN rw0_wmask_in[912] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.676 416.048 38.700 ; + END + END rw0_wmask_in[912] + PIN rw0_wmask_in[913] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.772 416.048 38.796 ; + END + END rw0_wmask_in[913] + PIN rw0_wmask_in[914] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.868 416.048 38.892 ; + END + END rw0_wmask_in[914] + PIN rw0_wmask_in[915] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 38.964 416.048 38.988 ; + END + END rw0_wmask_in[915] + PIN rw0_wmask_in[916] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.060 416.048 39.084 ; + END + END rw0_wmask_in[916] + PIN rw0_wmask_in[917] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.156 416.048 39.180 ; + END + END rw0_wmask_in[917] + PIN rw0_wmask_in[918] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.252 416.048 39.276 ; + END + END rw0_wmask_in[918] + PIN rw0_wmask_in[919] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.348 416.048 39.372 ; + END + END rw0_wmask_in[919] + PIN rw0_wmask_in[920] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.444 416.048 39.468 ; + END + END rw0_wmask_in[920] + PIN rw0_wmask_in[921] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.540 416.048 39.564 ; + END + END rw0_wmask_in[921] + PIN rw0_wmask_in[922] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.636 416.048 39.660 ; + END + END rw0_wmask_in[922] + PIN rw0_wmask_in[923] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.732 416.048 39.756 ; + END + END rw0_wmask_in[923] + PIN rw0_wmask_in[924] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.828 416.048 39.852 ; + END + END rw0_wmask_in[924] + PIN rw0_wmask_in[925] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 39.924 416.048 39.948 ; + END + END rw0_wmask_in[925] + PIN rw0_wmask_in[926] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.020 416.048 40.044 ; + END + END rw0_wmask_in[926] + PIN rw0_wmask_in[927] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.116 416.048 40.140 ; + END + END rw0_wmask_in[927] + PIN rw0_wmask_in[928] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.212 416.048 40.236 ; + END + END rw0_wmask_in[928] + PIN rw0_wmask_in[929] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.308 416.048 40.332 ; + END + END rw0_wmask_in[929] + PIN rw0_wmask_in[930] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.404 416.048 40.428 ; + END + END rw0_wmask_in[930] + PIN rw0_wmask_in[931] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.500 416.048 40.524 ; + END + END rw0_wmask_in[931] + PIN rw0_wmask_in[932] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.596 416.048 40.620 ; + END + END rw0_wmask_in[932] + PIN rw0_wmask_in[933] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.692 416.048 40.716 ; + END + END rw0_wmask_in[933] + PIN rw0_wmask_in[934] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.788 416.048 40.812 ; + END + END rw0_wmask_in[934] + PIN rw0_wmask_in[935] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.884 416.048 40.908 ; + END + END rw0_wmask_in[935] + PIN rw0_wmask_in[936] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 40.980 416.048 41.004 ; + END + END rw0_wmask_in[936] + PIN rw0_wmask_in[937] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.076 416.048 41.100 ; + END + END rw0_wmask_in[937] + PIN rw0_wmask_in[938] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.172 416.048 41.196 ; + END + END rw0_wmask_in[938] + PIN rw0_wmask_in[939] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.268 416.048 41.292 ; + END + END rw0_wmask_in[939] + PIN rw0_wmask_in[940] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.364 416.048 41.388 ; + END + END rw0_wmask_in[940] + PIN rw0_wmask_in[941] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.460 416.048 41.484 ; + END + END rw0_wmask_in[941] + PIN rw0_wmask_in[942] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.556 416.048 41.580 ; + END + END rw0_wmask_in[942] + PIN rw0_wmask_in[943] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.652 416.048 41.676 ; + END + END rw0_wmask_in[943] + PIN rw0_wmask_in[944] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.748 416.048 41.772 ; + END + END rw0_wmask_in[944] + PIN rw0_wmask_in[945] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.844 416.048 41.868 ; + END + END rw0_wmask_in[945] + PIN rw0_wmask_in[946] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 41.940 416.048 41.964 ; + END + END rw0_wmask_in[946] + PIN rw0_wmask_in[947] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.036 416.048 42.060 ; + END + END rw0_wmask_in[947] + PIN rw0_wmask_in[948] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.132 416.048 42.156 ; + END + END rw0_wmask_in[948] + PIN rw0_wmask_in[949] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.228 416.048 42.252 ; + END + END rw0_wmask_in[949] + PIN rw0_wmask_in[950] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.324 416.048 42.348 ; + END + END rw0_wmask_in[950] + PIN rw0_wmask_in[951] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.420 416.048 42.444 ; + END + END rw0_wmask_in[951] + PIN rw0_wmask_in[952] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.516 416.048 42.540 ; + END + END rw0_wmask_in[952] + PIN rw0_wmask_in[953] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.612 416.048 42.636 ; + END + END rw0_wmask_in[953] + PIN rw0_wmask_in[954] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.708 416.048 42.732 ; + END + END rw0_wmask_in[954] + PIN rw0_wmask_in[955] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.804 416.048 42.828 ; + END + END rw0_wmask_in[955] + PIN rw0_wmask_in[956] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.900 416.048 42.924 ; + END + END rw0_wmask_in[956] + PIN rw0_wmask_in[957] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 42.996 416.048 43.020 ; + END + END rw0_wmask_in[957] + PIN rw0_wmask_in[958] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.092 416.048 43.116 ; + END + END rw0_wmask_in[958] + PIN rw0_wmask_in[959] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.188 416.048 43.212 ; + END + END rw0_wmask_in[959] + PIN rw0_wmask_in[960] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.284 416.048 43.308 ; + END + END rw0_wmask_in[960] + PIN rw0_wmask_in[961] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.380 416.048 43.404 ; + END + END rw0_wmask_in[961] + PIN rw0_wmask_in[962] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.476 416.048 43.500 ; + END + END rw0_wmask_in[962] + PIN rw0_wmask_in[963] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.572 416.048 43.596 ; + END + END rw0_wmask_in[963] + PIN rw0_wmask_in[964] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.668 416.048 43.692 ; + END + END rw0_wmask_in[964] + PIN rw0_wmask_in[965] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.764 416.048 43.788 ; + END + END rw0_wmask_in[965] + PIN rw0_wmask_in[966] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.860 416.048 43.884 ; + END + END rw0_wmask_in[966] + PIN rw0_wmask_in[967] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 43.956 416.048 43.980 ; + END + END rw0_wmask_in[967] + PIN rw0_wmask_in[968] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.052 416.048 44.076 ; + END + END rw0_wmask_in[968] + PIN rw0_wmask_in[969] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.148 416.048 44.172 ; + END + END rw0_wmask_in[969] + PIN rw0_wmask_in[970] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.244 416.048 44.268 ; + END + END rw0_wmask_in[970] + PIN rw0_wmask_in[971] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.340 416.048 44.364 ; + END + END rw0_wmask_in[971] + PIN rw0_wmask_in[972] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.436 416.048 44.460 ; + END + END rw0_wmask_in[972] + PIN rw0_wmask_in[973] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.532 416.048 44.556 ; + END + END rw0_wmask_in[973] + PIN rw0_wmask_in[974] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.628 416.048 44.652 ; + END + END rw0_wmask_in[974] + PIN rw0_wmask_in[975] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.724 416.048 44.748 ; + END + END rw0_wmask_in[975] + PIN rw0_wmask_in[976] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.820 416.048 44.844 ; + END + END rw0_wmask_in[976] + PIN rw0_wmask_in[977] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 44.916 416.048 44.940 ; + END + END rw0_wmask_in[977] + PIN rw0_wmask_in[978] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.012 416.048 45.036 ; + END + END rw0_wmask_in[978] + PIN rw0_wmask_in[979] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.108 416.048 45.132 ; + END + END rw0_wmask_in[979] + PIN rw0_wmask_in[980] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.204 416.048 45.228 ; + END + END rw0_wmask_in[980] + PIN rw0_wmask_in[981] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.300 416.048 45.324 ; + END + END rw0_wmask_in[981] + PIN rw0_wmask_in[982] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.396 416.048 45.420 ; + END + END rw0_wmask_in[982] + PIN rw0_wmask_in[983] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.492 416.048 45.516 ; + END + END rw0_wmask_in[983] + PIN rw0_wmask_in[984] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.588 416.048 45.612 ; + END + END rw0_wmask_in[984] + PIN rw0_wmask_in[985] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.684 416.048 45.708 ; + END + END rw0_wmask_in[985] + PIN rw0_wmask_in[986] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.780 416.048 45.804 ; + END + END rw0_wmask_in[986] + PIN rw0_wmask_in[987] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.876 416.048 45.900 ; + END + END rw0_wmask_in[987] + PIN rw0_wmask_in[988] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 45.972 416.048 45.996 ; + END + END rw0_wmask_in[988] + PIN rw0_wmask_in[989] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.068 416.048 46.092 ; + END + END rw0_wmask_in[989] + PIN rw0_wmask_in[990] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.164 416.048 46.188 ; + END + END rw0_wmask_in[990] + PIN rw0_wmask_in[991] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.260 416.048 46.284 ; + END + END rw0_wmask_in[991] + PIN rw0_wmask_in[992] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.356 416.048 46.380 ; + END + END rw0_wmask_in[992] + PIN rw0_wmask_in[993] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.452 416.048 46.476 ; + END + END rw0_wmask_in[993] + PIN rw0_wmask_in[994] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.548 416.048 46.572 ; + END + END rw0_wmask_in[994] + PIN rw0_wmask_in[995] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.644 416.048 46.668 ; + END + END rw0_wmask_in[995] + PIN rw0_wmask_in[996] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.740 416.048 46.764 ; + END + END rw0_wmask_in[996] + PIN rw0_wmask_in[997] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.836 416.048 46.860 ; + END + END rw0_wmask_in[997] + PIN rw0_wmask_in[998] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 46.932 416.048 46.956 ; + END + END rw0_wmask_in[998] + PIN rw0_wmask_in[999] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.028 416.048 47.052 ; + END + END rw0_wmask_in[999] + PIN rw0_wmask_in[1000] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.124 416.048 47.148 ; + END + END rw0_wmask_in[1000] + PIN rw0_wmask_in[1001] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.220 416.048 47.244 ; + END + END rw0_wmask_in[1001] + PIN rw0_wmask_in[1002] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.316 416.048 47.340 ; + END + END rw0_wmask_in[1002] + PIN rw0_wmask_in[1003] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.412 416.048 47.436 ; + END + END rw0_wmask_in[1003] + PIN rw0_wmask_in[1004] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.508 416.048 47.532 ; + END + END rw0_wmask_in[1004] + PIN rw0_wmask_in[1005] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.604 416.048 47.628 ; + END + END rw0_wmask_in[1005] + PIN rw0_wmask_in[1006] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.700 416.048 47.724 ; + END + END rw0_wmask_in[1006] + PIN rw0_wmask_in[1007] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.796 416.048 47.820 ; + END + END rw0_wmask_in[1007] + PIN rw0_wmask_in[1008] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.892 416.048 47.916 ; + END + END rw0_wmask_in[1008] + PIN rw0_wmask_in[1009] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 47.988 416.048 48.012 ; + END + END rw0_wmask_in[1009] + PIN rw0_wmask_in[1010] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.084 416.048 48.108 ; + END + END rw0_wmask_in[1010] + PIN rw0_wmask_in[1011] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.180 416.048 48.204 ; + END + END rw0_wmask_in[1011] + PIN rw0_wmask_in[1012] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.276 416.048 48.300 ; + END + END rw0_wmask_in[1012] + PIN rw0_wmask_in[1013] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.372 416.048 48.396 ; + END + END rw0_wmask_in[1013] + PIN rw0_wmask_in[1014] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.468 416.048 48.492 ; + END + END rw0_wmask_in[1014] + PIN rw0_wmask_in[1015] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.564 416.048 48.588 ; + END + END rw0_wmask_in[1015] + PIN rw0_wmask_in[1016] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.660 416.048 48.684 ; + END + END rw0_wmask_in[1016] + PIN rw0_wmask_in[1017] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.756 416.048 48.780 ; + END + END rw0_wmask_in[1017] + PIN rw0_wmask_in[1018] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.852 416.048 48.876 ; + END + END rw0_wmask_in[1018] + PIN rw0_wmask_in[1019] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 48.948 416.048 48.972 ; + END + END rw0_wmask_in[1019] + PIN rw0_wmask_in[1020] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.044 416.048 49.068 ; + END + END rw0_wmask_in[1020] + PIN rw0_wmask_in[1021] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.140 416.048 49.164 ; + END + END rw0_wmask_in[1021] + PIN rw0_wmask_in[1022] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.236 416.048 49.260 ; + END + END rw0_wmask_in[1022] + PIN rw0_wmask_in[1023] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.332 416.048 49.356 ; + END + END rw0_wmask_in[1023] + PIN rw0_wmask_in[1024] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 129.961 0.225 130.015 ; + END + END rw0_wmask_in[1024] + PIN rw0_wmask_in[1025] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 129.961 0.405 130.015 ; + END + END rw0_wmask_in[1025] + PIN rw0_wmask_in[1026] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 129.961 0.585 130.015 ; + END + END rw0_wmask_in[1026] + PIN rw0_wmask_in[1027] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 129.961 0.765 130.015 ; + END + END rw0_wmask_in[1027] + PIN rw0_wmask_in[1028] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 129.961 0.945 130.015 ; + END + END rw0_wmask_in[1028] + PIN rw0_wmask_in[1029] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 129.961 1.125 130.015 ; + END + END rw0_wmask_in[1029] + PIN rw0_wmask_in[1030] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 129.961 1.305 130.015 ; + END + END rw0_wmask_in[1030] + PIN rw0_wmask_in[1031] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 129.961 1.485 130.015 ; + END + END rw0_wmask_in[1031] + PIN rw0_wmask_in[1032] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 129.961 1.665 130.015 ; + END + END rw0_wmask_in[1032] + PIN rw0_wmask_in[1033] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 129.961 1.845 130.015 ; + END + END rw0_wmask_in[1033] + PIN rw0_wmask_in[1034] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 129.961 2.025 130.015 ; + END + END rw0_wmask_in[1034] + PIN rw0_wmask_in[1035] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 129.961 2.205 130.015 ; + END + END rw0_wmask_in[1035] + PIN rw0_wmask_in[1036] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 129.961 2.385 130.015 ; + END + END rw0_wmask_in[1036] + PIN rw0_wmask_in[1037] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 129.961 2.565 130.015 ; + END + END rw0_wmask_in[1037] + PIN rw0_wmask_in[1038] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 129.961 2.745 130.015 ; + END + END rw0_wmask_in[1038] + PIN rw0_wmask_in[1039] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 129.961 2.925 130.015 ; + END + END rw0_wmask_in[1039] + PIN rw0_wmask_in[1040] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 129.961 3.105 130.015 ; + END + END rw0_wmask_in[1040] + PIN rw0_wmask_in[1041] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 129.961 3.285 130.015 ; + END + END rw0_wmask_in[1041] + PIN rw0_wmask_in[1042] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 129.961 3.465 130.015 ; + END + END rw0_wmask_in[1042] + PIN rw0_wmask_in[1043] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 129.961 3.645 130.015 ; + END + END rw0_wmask_in[1043] + PIN rw0_wmask_in[1044] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 129.961 3.825 130.015 ; + END + END rw0_wmask_in[1044] + PIN rw0_wmask_in[1045] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 129.961 4.005 130.015 ; + END + END rw0_wmask_in[1045] + PIN rw0_wmask_in[1046] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 129.961 4.185 130.015 ; + END + END rw0_wmask_in[1046] + PIN rw0_wmask_in[1047] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 129.961 4.365 130.015 ; + END + END rw0_wmask_in[1047] + PIN rw0_wmask_in[1048] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 129.961 4.545 130.015 ; + END + END rw0_wmask_in[1048] + PIN rw0_wmask_in[1049] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 129.961 4.725 130.015 ; + END + END rw0_wmask_in[1049] + PIN rw0_wmask_in[1050] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 129.961 4.905 130.015 ; + END + END rw0_wmask_in[1050] + PIN rw0_wmask_in[1051] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 129.961 5.085 130.015 ; + END + END rw0_wmask_in[1051] + PIN rw0_wmask_in[1052] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 129.961 5.265 130.015 ; + END + END rw0_wmask_in[1052] + PIN rw0_wmask_in[1053] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 129.961 5.445 130.015 ; + END + END rw0_wmask_in[1053] + PIN rw0_wmask_in[1054] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 129.961 5.625 130.015 ; + END + END rw0_wmask_in[1054] + PIN rw0_wmask_in[1055] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 129.961 5.805 130.015 ; + END + END rw0_wmask_in[1055] + PIN rw0_wmask_in[1056] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 129.961 5.985 130.015 ; + END + END rw0_wmask_in[1056] + PIN rw0_wmask_in[1057] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 129.961 6.165 130.015 ; + END + END rw0_wmask_in[1057] + PIN rw0_wmask_in[1058] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 129.961 6.345 130.015 ; + END + END rw0_wmask_in[1058] + PIN rw0_wmask_in[1059] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 129.961 6.525 130.015 ; + END + END rw0_wmask_in[1059] + PIN rw0_wmask_in[1060] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 129.961 6.705 130.015 ; + END + END rw0_wmask_in[1060] + PIN rw0_wmask_in[1061] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 129.961 6.885 130.015 ; + END + END rw0_wmask_in[1061] + PIN rw0_wmask_in[1062] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 129.961 7.065 130.015 ; + END + END rw0_wmask_in[1062] + PIN rw0_wmask_in[1063] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 129.961 7.245 130.015 ; + END + END rw0_wmask_in[1063] + PIN rw0_wmask_in[1064] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 129.961 7.425 130.015 ; + END + END rw0_wmask_in[1064] + PIN rw0_wmask_in[1065] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 129.961 7.605 130.015 ; + END + END rw0_wmask_in[1065] + PIN rw0_wmask_in[1066] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 129.961 7.785 130.015 ; + END + END rw0_wmask_in[1066] + PIN rw0_wmask_in[1067] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 129.961 7.965 130.015 ; + END + END rw0_wmask_in[1067] + PIN rw0_wmask_in[1068] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 129.961 8.145 130.015 ; + END + END rw0_wmask_in[1068] + PIN rw0_wmask_in[1069] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 129.961 8.325 130.015 ; + END + END rw0_wmask_in[1069] + PIN rw0_wmask_in[1070] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 129.961 8.505 130.015 ; + END + END rw0_wmask_in[1070] + PIN rw0_wmask_in[1071] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 129.961 8.685 130.015 ; + END + END rw0_wmask_in[1071] + PIN rw0_wmask_in[1072] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 129.961 8.865 130.015 ; + END + END rw0_wmask_in[1072] + PIN rw0_wmask_in[1073] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 129.961 9.045 130.015 ; + END + END rw0_wmask_in[1073] + PIN rw0_wmask_in[1074] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 129.961 9.225 130.015 ; + END + END rw0_wmask_in[1074] + PIN rw0_wmask_in[1075] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 129.961 9.405 130.015 ; + END + END rw0_wmask_in[1075] + PIN rw0_wmask_in[1076] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 129.961 9.585 130.015 ; + END + END rw0_wmask_in[1076] + PIN rw0_wmask_in[1077] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 129.961 9.765 130.015 ; + END + END rw0_wmask_in[1077] + PIN rw0_wmask_in[1078] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 129.961 9.945 130.015 ; + END + END rw0_wmask_in[1078] + PIN rw0_wmask_in[1079] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 129.961 10.125 130.015 ; + END + END rw0_wmask_in[1079] + PIN rw0_wmask_in[1080] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 129.961 10.305 130.015 ; + END + END rw0_wmask_in[1080] + PIN rw0_wmask_in[1081] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 129.961 10.485 130.015 ; + END + END rw0_wmask_in[1081] + PIN rw0_wmask_in[1082] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 129.961 10.665 130.015 ; + END + END rw0_wmask_in[1082] + PIN rw0_wmask_in[1083] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 129.961 10.845 130.015 ; + END + END rw0_wmask_in[1083] + PIN rw0_wmask_in[1084] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 129.961 11.025 130.015 ; + END + END rw0_wmask_in[1084] + PIN rw0_wmask_in[1085] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 129.961 11.205 130.015 ; + END + END rw0_wmask_in[1085] + PIN rw0_wmask_in[1086] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 129.961 11.385 130.015 ; + END + END rw0_wmask_in[1086] + PIN rw0_wmask_in[1087] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 129.961 11.565 130.015 ; + END + END rw0_wmask_in[1087] + PIN rw0_wmask_in[1088] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 129.961 11.745 130.015 ; + END + END rw0_wmask_in[1088] + PIN rw0_wmask_in[1089] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 129.961 11.925 130.015 ; + END + END rw0_wmask_in[1089] + PIN rw0_wmask_in[1090] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 129.961 12.105 130.015 ; + END + END rw0_wmask_in[1090] + PIN rw0_wmask_in[1091] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 129.961 12.285 130.015 ; + END + END rw0_wmask_in[1091] + PIN rw0_wmask_in[1092] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 129.961 12.465 130.015 ; + END + END rw0_wmask_in[1092] + PIN rw0_wmask_in[1093] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 129.961 12.645 130.015 ; + END + END rw0_wmask_in[1093] + PIN rw0_wmask_in[1094] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 129.961 12.825 130.015 ; + END + END rw0_wmask_in[1094] + PIN rw0_wmask_in[1095] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 129.961 13.005 130.015 ; + END + END rw0_wmask_in[1095] + PIN rw0_wmask_in[1096] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 129.961 13.185 130.015 ; + END + END rw0_wmask_in[1096] + PIN rw0_wmask_in[1097] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 129.961 13.365 130.015 ; + END + END rw0_wmask_in[1097] + PIN rw0_wmask_in[1098] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 129.961 13.545 130.015 ; + END + END rw0_wmask_in[1098] + PIN rw0_wmask_in[1099] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 129.961 13.725 130.015 ; + END + END rw0_wmask_in[1099] + PIN rw0_wmask_in[1100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 129.961 13.905 130.015 ; + END + END rw0_wmask_in[1100] + PIN rw0_wmask_in[1101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 129.961 14.085 130.015 ; + END + END rw0_wmask_in[1101] + PIN rw0_wmask_in[1102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 129.961 14.265 130.015 ; + END + END rw0_wmask_in[1102] + PIN rw0_wmask_in[1103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 129.961 14.445 130.015 ; + END + END rw0_wmask_in[1103] + PIN rw0_wmask_in[1104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 129.961 14.625 130.015 ; + END + END rw0_wmask_in[1104] + PIN rw0_wmask_in[1105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 129.961 14.805 130.015 ; + END + END rw0_wmask_in[1105] + PIN rw0_wmask_in[1106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 129.961 14.985 130.015 ; + END + END rw0_wmask_in[1106] + PIN rw0_wmask_in[1107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 129.961 15.165 130.015 ; + END + END rw0_wmask_in[1107] + PIN rw0_wmask_in[1108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 129.961 15.345 130.015 ; + END + END rw0_wmask_in[1108] + PIN rw0_wmask_in[1109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 129.961 15.525 130.015 ; + END + END rw0_wmask_in[1109] + PIN rw0_wmask_in[1110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 129.961 15.705 130.015 ; + END + END rw0_wmask_in[1110] + PIN rw0_wmask_in[1111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 129.961 15.885 130.015 ; + END + END rw0_wmask_in[1111] + PIN rw0_wmask_in[1112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 129.961 16.065 130.015 ; + END + END rw0_wmask_in[1112] + PIN rw0_wmask_in[1113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 129.961 16.245 130.015 ; + END + END rw0_wmask_in[1113] + PIN rw0_wmask_in[1114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 129.961 16.425 130.015 ; + END + END rw0_wmask_in[1114] + PIN rw0_wmask_in[1115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 129.961 16.605 130.015 ; + END + END rw0_wmask_in[1115] + PIN rw0_wmask_in[1116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 129.961 16.785 130.015 ; + END + END rw0_wmask_in[1116] + PIN rw0_wmask_in[1117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 129.961 16.965 130.015 ; + END + END rw0_wmask_in[1117] + PIN rw0_wmask_in[1118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 129.961 17.145 130.015 ; + END + END rw0_wmask_in[1118] + PIN rw0_wmask_in[1119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 129.961 17.325 130.015 ; + END + END rw0_wmask_in[1119] + PIN rw0_wmask_in[1120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 129.961 17.505 130.015 ; + END + END rw0_wmask_in[1120] + PIN rw0_wmask_in[1121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 129.961 17.685 130.015 ; + END + END rw0_wmask_in[1121] + PIN rw0_wmask_in[1122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 129.961 17.865 130.015 ; + END + END rw0_wmask_in[1122] + PIN rw0_wmask_in[1123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 129.961 18.045 130.015 ; + END + END rw0_wmask_in[1123] + PIN rw0_wmask_in[1124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 129.961 18.225 130.015 ; + END + END rw0_wmask_in[1124] + PIN rw0_wmask_in[1125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 129.961 18.405 130.015 ; + END + END rw0_wmask_in[1125] + PIN rw0_wmask_in[1126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 129.961 18.585 130.015 ; + END + END rw0_wmask_in[1126] + PIN rw0_wmask_in[1127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 129.961 18.765 130.015 ; + END + END rw0_wmask_in[1127] + PIN rw0_wmask_in[1128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 129.961 18.945 130.015 ; + END + END rw0_wmask_in[1128] + PIN rw0_wmask_in[1129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 129.961 19.125 130.015 ; + END + END rw0_wmask_in[1129] + PIN rw0_wmask_in[1130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 129.961 19.305 130.015 ; + END + END rw0_wmask_in[1130] + PIN rw0_wmask_in[1131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 129.961 19.485 130.015 ; + END + END rw0_wmask_in[1131] + PIN rw0_wmask_in[1132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 129.961 19.665 130.015 ; + END + END rw0_wmask_in[1132] + PIN rw0_wmask_in[1133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 129.961 19.845 130.015 ; + END + END rw0_wmask_in[1133] + PIN rw0_wmask_in[1134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 129.961 20.025 130.015 ; + END + END rw0_wmask_in[1134] + PIN rw0_wmask_in[1135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 129.961 20.205 130.015 ; + END + END rw0_wmask_in[1135] + PIN rw0_wmask_in[1136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 129.961 20.385 130.015 ; + END + END rw0_wmask_in[1136] + PIN rw0_wmask_in[1137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 129.961 20.565 130.015 ; + END + END rw0_wmask_in[1137] + PIN rw0_wmask_in[1138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 129.961 20.745 130.015 ; + END + END rw0_wmask_in[1138] + PIN rw0_wmask_in[1139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 129.961 20.925 130.015 ; + END + END rw0_wmask_in[1139] + PIN rw0_wmask_in[1140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 129.961 21.105 130.015 ; + END + END rw0_wmask_in[1140] + PIN rw0_wmask_in[1141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 129.961 21.285 130.015 ; + END + END rw0_wmask_in[1141] + PIN rw0_wmask_in[1142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 129.961 21.465 130.015 ; + END + END rw0_wmask_in[1142] + PIN rw0_wmask_in[1143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 129.961 21.645 130.015 ; + END + END rw0_wmask_in[1143] + PIN rw0_wmask_in[1144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 129.961 21.825 130.015 ; + END + END rw0_wmask_in[1144] + PIN rw0_wmask_in[1145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 129.961 22.005 130.015 ; + END + END rw0_wmask_in[1145] + PIN rw0_wmask_in[1146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 129.961 22.185 130.015 ; + END + END rw0_wmask_in[1146] + PIN rw0_wmask_in[1147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 129.961 22.365 130.015 ; + END + END rw0_wmask_in[1147] + PIN rw0_wmask_in[1148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 129.961 22.545 130.015 ; + END + END rw0_wmask_in[1148] + PIN rw0_wmask_in[1149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 129.961 22.725 130.015 ; + END + END rw0_wmask_in[1149] + PIN rw0_wmask_in[1150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 129.961 22.905 130.015 ; + END + END rw0_wmask_in[1150] + PIN rw0_wmask_in[1151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 129.961 23.085 130.015 ; + END + END rw0_wmask_in[1151] + PIN rw0_wmask_in[1152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 129.961 23.265 130.015 ; + END + END rw0_wmask_in[1152] + PIN rw0_wmask_in[1153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 129.961 23.445 130.015 ; + END + END rw0_wmask_in[1153] + PIN rw0_wmask_in[1154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 129.961 23.625 130.015 ; + END + END rw0_wmask_in[1154] + PIN rw0_wmask_in[1155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.787 129.961 23.805 130.015 ; + END + END rw0_wmask_in[1155] + PIN rw0_wmask_in[1156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 129.961 23.985 130.015 ; + END + END rw0_wmask_in[1156] + PIN rw0_wmask_in[1157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.147 129.961 24.165 130.015 ; + END + END rw0_wmask_in[1157] + PIN rw0_wmask_in[1158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.327 129.961 24.345 130.015 ; + END + END rw0_wmask_in[1158] + PIN rw0_wmask_in[1159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 129.961 24.525 130.015 ; + END + END rw0_wmask_in[1159] + PIN rw0_wmask_in[1160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 129.961 24.705 130.015 ; + END + END rw0_wmask_in[1160] + PIN rw0_wmask_in[1161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.867 129.961 24.885 130.015 ; + END + END rw0_wmask_in[1161] + PIN rw0_wmask_in[1162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 129.961 25.065 130.015 ; + END + END rw0_wmask_in[1162] + PIN rw0_wmask_in[1163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.227 129.961 25.245 130.015 ; + END + END rw0_wmask_in[1163] + PIN rw0_wmask_in[1164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.407 129.961 25.425 130.015 ; + END + END rw0_wmask_in[1164] + PIN rw0_wmask_in[1165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 129.961 25.605 130.015 ; + END + END rw0_wmask_in[1165] + PIN rw0_wmask_in[1166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.767 129.961 25.785 130.015 ; + END + END rw0_wmask_in[1166] + PIN rw0_wmask_in[1167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.947 129.961 25.965 130.015 ; + END + END rw0_wmask_in[1167] + PIN rw0_wmask_in[1168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 129.961 26.145 130.015 ; + END + END rw0_wmask_in[1168] + PIN rw0_wmask_in[1169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.307 129.961 26.325 130.015 ; + END + END rw0_wmask_in[1169] + PIN rw0_wmask_in[1170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.487 129.961 26.505 130.015 ; + END + END rw0_wmask_in[1170] + PIN rw0_wmask_in[1171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 129.961 26.685 130.015 ; + END + END rw0_wmask_in[1171] + PIN rw0_wmask_in[1172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.847 129.961 26.865 130.015 ; + END + END rw0_wmask_in[1172] + PIN rw0_wmask_in[1173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.027 129.961 27.045 130.015 ; + END + END rw0_wmask_in[1173] + PIN rw0_wmask_in[1174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 129.961 27.225 130.015 ; + END + END rw0_wmask_in[1174] + PIN rw0_wmask_in[1175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.387 129.961 27.405 130.015 ; + END + END rw0_wmask_in[1175] + PIN rw0_wmask_in[1176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 129.961 27.585 130.015 ; + END + END rw0_wmask_in[1176] + PIN rw0_wmask_in[1177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 129.961 27.765 130.015 ; + END + END rw0_wmask_in[1177] + PIN rw0_wmask_in[1178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.927 129.961 27.945 130.015 ; + END + END rw0_wmask_in[1178] + PIN rw0_wmask_in[1179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.107 129.961 28.125 130.015 ; + END + END rw0_wmask_in[1179] + PIN rw0_wmask_in[1180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 129.961 28.305 130.015 ; + END + END rw0_wmask_in[1180] + PIN rw0_wmask_in[1181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.467 129.961 28.485 130.015 ; + END + END rw0_wmask_in[1181] + PIN rw0_wmask_in[1182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.647 129.961 28.665 130.015 ; + END + END rw0_wmask_in[1182] + PIN rw0_wmask_in[1183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 129.961 28.845 130.015 ; + END + END rw0_wmask_in[1183] + PIN rw0_wmask_in[1184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 129.961 29.025 130.015 ; + END + END rw0_wmask_in[1184] + PIN rw0_wmask_in[1185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.187 129.961 29.205 130.015 ; + END + END rw0_wmask_in[1185] + PIN rw0_wmask_in[1186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 129.961 29.385 130.015 ; + END + END rw0_wmask_in[1186] + PIN rw0_wmask_in[1187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.547 129.961 29.565 130.015 ; + END + END rw0_wmask_in[1187] + PIN rw0_wmask_in[1188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.727 129.961 29.745 130.015 ; + END + END rw0_wmask_in[1188] + PIN rw0_wmask_in[1189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 129.961 29.925 130.015 ; + END + END rw0_wmask_in[1189] + PIN rw0_wmask_in[1190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.087 129.961 30.105 130.015 ; + END + END rw0_wmask_in[1190] + PIN rw0_wmask_in[1191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.267 129.961 30.285 130.015 ; + END + END rw0_wmask_in[1191] + PIN rw0_wmask_in[1192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 129.961 30.465 130.015 ; + END + END rw0_wmask_in[1192] + PIN rw0_wmask_in[1193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.627 129.961 30.645 130.015 ; + END + END rw0_wmask_in[1193] + PIN rw0_wmask_in[1194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.807 129.961 30.825 130.015 ; + END + END rw0_wmask_in[1194] + PIN rw0_wmask_in[1195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 129.961 31.005 130.015 ; + END + END rw0_wmask_in[1195] + PIN rw0_wmask_in[1196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.167 129.961 31.185 130.015 ; + END + END rw0_wmask_in[1196] + PIN rw0_wmask_in[1197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.347 129.961 31.365 130.015 ; + END + END rw0_wmask_in[1197] + PIN rw0_wmask_in[1198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 129.961 31.545 130.015 ; + END + END rw0_wmask_in[1198] + PIN rw0_wmask_in[1199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.707 129.961 31.725 130.015 ; + END + END rw0_wmask_in[1199] + PIN rw0_wmask_in[1200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 129.961 31.905 130.015 ; + END + END rw0_wmask_in[1200] + PIN rw0_wmask_in[1201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 129.961 32.085 130.015 ; + END + END rw0_wmask_in[1201] + PIN rw0_wmask_in[1202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.247 129.961 32.265 130.015 ; + END + END rw0_wmask_in[1202] + PIN rw0_wmask_in[1203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.427 129.961 32.445 130.015 ; + END + END rw0_wmask_in[1203] + PIN rw0_wmask_in[1204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 129.961 32.625 130.015 ; + END + END rw0_wmask_in[1204] + PIN rw0_wmask_in[1205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.787 129.961 32.805 130.015 ; + END + END rw0_wmask_in[1205] + PIN rw0_wmask_in[1206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.967 129.961 32.985 130.015 ; + END + END rw0_wmask_in[1206] + PIN rw0_wmask_in[1207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 129.961 33.165 130.015 ; + END + END rw0_wmask_in[1207] + PIN rw0_wmask_in[1208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 129.961 33.345 130.015 ; + END + END rw0_wmask_in[1208] + PIN rw0_wmask_in[1209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.507 129.961 33.525 130.015 ; + END + END rw0_wmask_in[1209] + PIN rw0_wmask_in[1210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 129.961 33.705 130.015 ; + END + END rw0_wmask_in[1210] + PIN rw0_wmask_in[1211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.867 129.961 33.885 130.015 ; + END + END rw0_wmask_in[1211] + PIN rw0_wmask_in[1212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.047 129.961 34.065 130.015 ; + END + END rw0_wmask_in[1212] + PIN rw0_wmask_in[1213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 129.961 34.245 130.015 ; + END + END rw0_wmask_in[1213] + PIN rw0_wmask_in[1214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.407 129.961 34.425 130.015 ; + END + END rw0_wmask_in[1214] + PIN rw0_wmask_in[1215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.587 129.961 34.605 130.015 ; + END + END rw0_wmask_in[1215] + PIN rw0_wmask_in[1216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 129.961 34.785 130.015 ; + END + END rw0_wmask_in[1216] + PIN rw0_wmask_in[1217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.947 129.961 34.965 130.015 ; + END + END rw0_wmask_in[1217] + PIN rw0_wmask_in[1218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.127 129.961 35.145 130.015 ; + END + END rw0_wmask_in[1218] + PIN rw0_wmask_in[1219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 129.961 35.325 130.015 ; + END + END rw0_wmask_in[1219] + PIN rw0_wmask_in[1220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.487 129.961 35.505 130.015 ; + END + END rw0_wmask_in[1220] + PIN rw0_wmask_in[1221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.667 129.961 35.685 130.015 ; + END + END rw0_wmask_in[1221] + PIN rw0_wmask_in[1222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 129.961 35.865 130.015 ; + END + END rw0_wmask_in[1222] + PIN rw0_wmask_in[1223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.027 129.961 36.045 130.015 ; + END + END rw0_wmask_in[1223] + PIN rw0_wmask_in[1224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 129.961 36.225 130.015 ; + END + END rw0_wmask_in[1224] + PIN rw0_wmask_in[1225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 129.961 36.405 130.015 ; + END + END rw0_wmask_in[1225] + PIN rw0_wmask_in[1226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.567 129.961 36.585 130.015 ; + END + END rw0_wmask_in[1226] + PIN rw0_wmask_in[1227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.747 129.961 36.765 130.015 ; + END + END rw0_wmask_in[1227] + PIN rw0_wmask_in[1228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 129.961 36.945 130.015 ; + END + END rw0_wmask_in[1228] + PIN rw0_wmask_in[1229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.107 129.961 37.125 130.015 ; + END + END rw0_wmask_in[1229] + PIN rw0_wmask_in[1230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.287 129.961 37.305 130.015 ; + END + END rw0_wmask_in[1230] + PIN rw0_wmask_in[1231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 129.961 37.485 130.015 ; + END + END rw0_wmask_in[1231] + PIN rw0_wmask_in[1232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 129.961 37.665 130.015 ; + END + END rw0_wmask_in[1232] + PIN rw0_wmask_in[1233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.827 129.961 37.845 130.015 ; + END + END rw0_wmask_in[1233] + PIN rw0_wmask_in[1234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 129.961 38.025 130.015 ; + END + END rw0_wmask_in[1234] + PIN rw0_wmask_in[1235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.187 129.961 38.205 130.015 ; + END + END rw0_wmask_in[1235] + PIN rw0_wmask_in[1236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.367 129.961 38.385 130.015 ; + END + END rw0_wmask_in[1236] + PIN rw0_wmask_in[1237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 129.961 38.565 130.015 ; + END + END rw0_wmask_in[1237] + PIN rw0_wmask_in[1238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.727 129.961 38.745 130.015 ; + END + END rw0_wmask_in[1238] + PIN rw0_wmask_in[1239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.907 129.961 38.925 130.015 ; + END + END rw0_wmask_in[1239] + PIN rw0_wmask_in[1240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 129.961 39.105 130.015 ; + END + END rw0_wmask_in[1240] + PIN rw0_wmask_in[1241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.267 129.961 39.285 130.015 ; + END + END rw0_wmask_in[1241] + PIN rw0_wmask_in[1242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.447 129.961 39.465 130.015 ; + END + END rw0_wmask_in[1242] + PIN rw0_wmask_in[1243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 129.961 39.645 130.015 ; + END + END rw0_wmask_in[1243] + PIN rw0_wmask_in[1244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.807 129.961 39.825 130.015 ; + END + END rw0_wmask_in[1244] + PIN rw0_wmask_in[1245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.987 129.961 40.005 130.015 ; + END + END rw0_wmask_in[1245] + PIN rw0_wmask_in[1246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 129.961 40.185 130.015 ; + END + END rw0_wmask_in[1246] + PIN rw0_wmask_in[1247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.347 129.961 40.365 130.015 ; + END + END rw0_wmask_in[1247] + PIN rw0_wmask_in[1248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 129.961 40.545 130.015 ; + END + END rw0_wmask_in[1248] + PIN rw0_wmask_in[1249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 129.961 40.725 130.015 ; + END + END rw0_wmask_in[1249] + PIN rw0_wmask_in[1250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.887 129.961 40.905 130.015 ; + END + END rw0_wmask_in[1250] + PIN rw0_wmask_in[1251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.067 129.961 41.085 130.015 ; + END + END rw0_wmask_in[1251] + PIN rw0_wmask_in[1252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 129.961 41.265 130.015 ; + END + END rw0_wmask_in[1252] + PIN rw0_wmask_in[1253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.427 129.961 41.445 130.015 ; + END + END rw0_wmask_in[1253] + PIN rw0_wmask_in[1254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.607 129.961 41.625 130.015 ; + END + END rw0_wmask_in[1254] + PIN rw0_wmask_in[1255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 129.961 41.805 130.015 ; + END + END rw0_wmask_in[1255] + PIN rw0_wmask_in[1256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 129.961 41.985 130.015 ; + END + END rw0_wmask_in[1256] + PIN rw0_wmask_in[1257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.147 129.961 42.165 130.015 ; + END + END rw0_wmask_in[1257] + PIN rw0_wmask_in[1258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 129.961 42.345 130.015 ; + END + END rw0_wmask_in[1258] + PIN rw0_wmask_in[1259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.507 129.961 42.525 130.015 ; + END + END rw0_wmask_in[1259] + PIN rw0_wmask_in[1260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.687 129.961 42.705 130.015 ; + END + END rw0_wmask_in[1260] + PIN rw0_wmask_in[1261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 129.961 42.885 130.015 ; + END + END rw0_wmask_in[1261] + PIN rw0_wmask_in[1262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.047 129.961 43.065 130.015 ; + END + END rw0_wmask_in[1262] + PIN rw0_wmask_in[1263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.227 129.961 43.245 130.015 ; + END + END rw0_wmask_in[1263] + PIN rw0_wmask_in[1264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 129.961 43.425 130.015 ; + END + END rw0_wmask_in[1264] + PIN rw0_wmask_in[1265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.587 129.961 43.605 130.015 ; + END + END rw0_wmask_in[1265] + PIN rw0_wmask_in[1266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.767 129.961 43.785 130.015 ; + END + END rw0_wmask_in[1266] + PIN rw0_wmask_in[1267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 129.961 43.965 130.015 ; + END + END rw0_wmask_in[1267] + PIN rw0_wmask_in[1268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.127 129.961 44.145 130.015 ; + END + END rw0_wmask_in[1268] + PIN rw0_wmask_in[1269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.307 129.961 44.325 130.015 ; + END + END rw0_wmask_in[1269] + PIN rw0_wmask_in[1270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 129.961 44.505 130.015 ; + END + END rw0_wmask_in[1270] + PIN rw0_wmask_in[1271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.667 129.961 44.685 130.015 ; + END + END rw0_wmask_in[1271] + PIN rw0_wmask_in[1272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 129.961 44.865 130.015 ; + END + END rw0_wmask_in[1272] + PIN rw0_wmask_in[1273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 129.961 45.045 130.015 ; + END + END rw0_wmask_in[1273] + PIN rw0_wmask_in[1274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.207 129.961 45.225 130.015 ; + END + END rw0_wmask_in[1274] + PIN rw0_wmask_in[1275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.387 129.961 45.405 130.015 ; + END + END rw0_wmask_in[1275] + PIN rw0_wmask_in[1276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 129.961 45.585 130.015 ; + END + END rw0_wmask_in[1276] + PIN rw0_wmask_in[1277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.747 129.961 45.765 130.015 ; + END + END rw0_wmask_in[1277] + PIN rw0_wmask_in[1278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.927 129.961 45.945 130.015 ; + END + END rw0_wmask_in[1278] + PIN rw0_wmask_in[1279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 129.961 46.125 130.015 ; + END + END rw0_wmask_in[1279] + PIN rw0_wmask_in[1280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 129.961 46.305 130.015 ; + END + END rw0_wmask_in[1280] + PIN rw0_wmask_in[1281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.467 129.961 46.485 130.015 ; + END + END rw0_wmask_in[1281] + PIN rw0_wmask_in[1282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 129.961 46.665 130.015 ; + END + END rw0_wmask_in[1282] + PIN rw0_wmask_in[1283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.827 129.961 46.845 130.015 ; + END + END rw0_wmask_in[1283] + PIN rw0_wmask_in[1284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.007 129.961 47.025 130.015 ; + END + END rw0_wmask_in[1284] + PIN rw0_wmask_in[1285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 129.961 47.205 130.015 ; + END + END rw0_wmask_in[1285] + PIN rw0_wmask_in[1286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.367 129.961 47.385 130.015 ; + END + END rw0_wmask_in[1286] + PIN rw0_wmask_in[1287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.547 129.961 47.565 130.015 ; + END + END rw0_wmask_in[1287] + PIN rw0_wmask_in[1288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 129.961 47.745 130.015 ; + END + END rw0_wmask_in[1288] + PIN rw0_wmask_in[1289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.907 129.961 47.925 130.015 ; + END + END rw0_wmask_in[1289] + PIN rw0_wmask_in[1290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.087 129.961 48.105 130.015 ; + END + END rw0_wmask_in[1290] + PIN rw0_wmask_in[1291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 129.961 48.285 130.015 ; + END + END rw0_wmask_in[1291] + PIN rw0_wmask_in[1292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.447 129.961 48.465 130.015 ; + END + END rw0_wmask_in[1292] + PIN rw0_wmask_in[1293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.627 129.961 48.645 130.015 ; + END + END rw0_wmask_in[1293] + PIN rw0_wmask_in[1294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 129.961 48.825 130.015 ; + END + END rw0_wmask_in[1294] + PIN rw0_wmask_in[1295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.987 129.961 49.005 130.015 ; + END + END rw0_wmask_in[1295] + PIN rw0_wmask_in[1296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 129.961 49.185 130.015 ; + END + END rw0_wmask_in[1296] + PIN rw0_wmask_in[1297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 129.961 49.365 130.015 ; + END + END rw0_wmask_in[1297] + PIN rw0_wmask_in[1298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.527 129.961 49.545 130.015 ; + END + END rw0_wmask_in[1298] + PIN rw0_wmask_in[1299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.707 129.961 49.725 130.015 ; + END + END rw0_wmask_in[1299] + PIN rw0_wmask_in[1300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 129.961 49.905 130.015 ; + END + END rw0_wmask_in[1300] + PIN rw0_wmask_in[1301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.067 129.961 50.085 130.015 ; + END + END rw0_wmask_in[1301] + PIN rw0_wmask_in[1302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.247 129.961 50.265 130.015 ; + END + END rw0_wmask_in[1302] + PIN rw0_wmask_in[1303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 129.961 50.445 130.015 ; + END + END rw0_wmask_in[1303] + PIN rw0_wmask_in[1304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 129.961 50.625 130.015 ; + END + END rw0_wmask_in[1304] + PIN rw0_wmask_in[1305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.787 129.961 50.805 130.015 ; + END + END rw0_wmask_in[1305] + PIN rw0_wmask_in[1306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 129.961 50.985 130.015 ; + END + END rw0_wmask_in[1306] + PIN rw0_wmask_in[1307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.147 129.961 51.165 130.015 ; + END + END rw0_wmask_in[1307] + PIN rw0_wmask_in[1308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.327 129.961 51.345 130.015 ; + END + END rw0_wmask_in[1308] + PIN rw0_wmask_in[1309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 129.961 51.525 130.015 ; + END + END rw0_wmask_in[1309] + PIN rw0_wmask_in[1310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.687 129.961 51.705 130.015 ; + END + END rw0_wmask_in[1310] + PIN rw0_wmask_in[1311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.867 129.961 51.885 130.015 ; + END + END rw0_wmask_in[1311] + PIN rw0_wmask_in[1312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 129.961 52.065 130.015 ; + END + END rw0_wmask_in[1312] + PIN rw0_wmask_in[1313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.227 129.961 52.245 130.015 ; + END + END rw0_wmask_in[1313] + PIN rw0_wmask_in[1314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.407 129.961 52.425 130.015 ; + END + END rw0_wmask_in[1314] + PIN rw0_wmask_in[1315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 129.961 52.605 130.015 ; + END + END rw0_wmask_in[1315] + PIN rw0_wmask_in[1316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.767 129.961 52.785 130.015 ; + END + END rw0_wmask_in[1316] + PIN rw0_wmask_in[1317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.947 129.961 52.965 130.015 ; + END + END rw0_wmask_in[1317] + PIN rw0_wmask_in[1318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 129.961 53.145 130.015 ; + END + END rw0_wmask_in[1318] + PIN rw0_wmask_in[1319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.307 129.961 53.325 130.015 ; + END + END rw0_wmask_in[1319] + PIN rw0_wmask_in[1320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 129.961 53.505 130.015 ; + END + END rw0_wmask_in[1320] + PIN rw0_wmask_in[1321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 129.961 53.685 130.015 ; + END + END rw0_wmask_in[1321] + PIN rw0_wmask_in[1322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.847 129.961 53.865 130.015 ; + END + END rw0_wmask_in[1322] + PIN rw0_wmask_in[1323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.027 129.961 54.045 130.015 ; + END + END rw0_wmask_in[1323] + PIN rw0_wmask_in[1324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 129.961 54.225 130.015 ; + END + END rw0_wmask_in[1324] + PIN rw0_wmask_in[1325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.387 129.961 54.405 130.015 ; + END + END rw0_wmask_in[1325] + PIN rw0_wmask_in[1326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.567 129.961 54.585 130.015 ; + END + END rw0_wmask_in[1326] + PIN rw0_wmask_in[1327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 129.961 54.765 130.015 ; + END + END rw0_wmask_in[1327] + PIN rw0_wmask_in[1328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 129.961 54.945 130.015 ; + END + END rw0_wmask_in[1328] + PIN rw0_wmask_in[1329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.107 129.961 55.125 130.015 ; + END + END rw0_wmask_in[1329] + PIN rw0_wmask_in[1330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 129.961 55.305 130.015 ; + END + END rw0_wmask_in[1330] + PIN rw0_wmask_in[1331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.467 129.961 55.485 130.015 ; + END + END rw0_wmask_in[1331] + PIN rw0_wmask_in[1332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.647 129.961 55.665 130.015 ; + END + END rw0_wmask_in[1332] + PIN rw0_wmask_in[1333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 129.961 55.845 130.015 ; + END + END rw0_wmask_in[1333] + PIN rw0_wmask_in[1334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.007 129.961 56.025 130.015 ; + END + END rw0_wmask_in[1334] + PIN rw0_wmask_in[1335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.187 129.961 56.205 130.015 ; + END + END rw0_wmask_in[1335] + PIN rw0_wmask_in[1336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 129.961 56.385 130.015 ; + END + END rw0_wmask_in[1336] + PIN rw0_wmask_in[1337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.547 129.961 56.565 130.015 ; + END + END rw0_wmask_in[1337] + PIN rw0_wmask_in[1338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.727 129.961 56.745 130.015 ; + END + END rw0_wmask_in[1338] + PIN rw0_wmask_in[1339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 129.961 56.925 130.015 ; + END + END rw0_wmask_in[1339] + PIN rw0_wmask_in[1340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.087 129.961 57.105 130.015 ; + END + END rw0_wmask_in[1340] + PIN rw0_wmask_in[1341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.267 129.961 57.285 130.015 ; + END + END rw0_wmask_in[1341] + PIN rw0_wmask_in[1342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 129.961 57.465 130.015 ; + END + END rw0_wmask_in[1342] + PIN rw0_wmask_in[1343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.627 129.961 57.645 130.015 ; + END + END rw0_wmask_in[1343] + PIN rw0_wmask_in[1344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 129.961 57.825 130.015 ; + END + END rw0_wmask_in[1344] + PIN rw0_wmask_in[1345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 129.961 58.005 130.015 ; + END + END rw0_wmask_in[1345] + PIN rw0_wmask_in[1346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.167 129.961 58.185 130.015 ; + END + END rw0_wmask_in[1346] + PIN rw0_wmask_in[1347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.347 129.961 58.365 130.015 ; + END + END rw0_wmask_in[1347] + PIN rw0_wmask_in[1348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 129.961 58.545 130.015 ; + END + END rw0_wmask_in[1348] + PIN rw0_wmask_in[1349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.707 129.961 58.725 130.015 ; + END + END rw0_wmask_in[1349] + PIN rw0_wmask_in[1350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.887 129.961 58.905 130.015 ; + END + END rw0_wmask_in[1350] + PIN rw0_wmask_in[1351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 129.961 59.085 130.015 ; + END + END rw0_wmask_in[1351] + PIN rw0_wmask_in[1352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 129.961 59.265 130.015 ; + END + END rw0_wmask_in[1352] + PIN rw0_wmask_in[1353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.427 129.961 59.445 130.015 ; + END + END rw0_wmask_in[1353] + PIN rw0_wmask_in[1354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 129.961 59.625 130.015 ; + END + END rw0_wmask_in[1354] + PIN rw0_wmask_in[1355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.787 129.961 59.805 130.015 ; + END + END rw0_wmask_in[1355] + PIN rw0_wmask_in[1356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.967 129.961 59.985 130.015 ; + END + END rw0_wmask_in[1356] + PIN rw0_wmask_in[1357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 129.961 60.165 130.015 ; + END + END rw0_wmask_in[1357] + PIN rw0_wmask_in[1358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.327 129.961 60.345 130.015 ; + END + END rw0_wmask_in[1358] + PIN rw0_wmask_in[1359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.507 129.961 60.525 130.015 ; + END + END rw0_wmask_in[1359] + PIN rw0_wmask_in[1360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 129.961 60.705 130.015 ; + END + END rw0_wmask_in[1360] + PIN rw0_wmask_in[1361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.867 129.961 60.885 130.015 ; + END + END rw0_wmask_in[1361] + PIN rw0_wmask_in[1362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.047 129.961 61.065 130.015 ; + END + END rw0_wmask_in[1362] + PIN rw0_wmask_in[1363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 129.961 61.245 130.015 ; + END + END rw0_wmask_in[1363] + PIN rw0_wmask_in[1364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.407 129.961 61.425 130.015 ; + END + END rw0_wmask_in[1364] + PIN rw0_wmask_in[1365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.587 129.961 61.605 130.015 ; + END + END rw0_wmask_in[1365] + PIN rw0_wmask_in[1366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 129.961 61.785 130.015 ; + END + END rw0_wmask_in[1366] + PIN rw0_wmask_in[1367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.947 129.961 61.965 130.015 ; + END + END rw0_wmask_in[1367] + PIN rw0_wmask_in[1368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 129.961 62.145 130.015 ; + END + END rw0_wmask_in[1368] + PIN rw0_wmask_in[1369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 129.961 62.325 130.015 ; + END + END rw0_wmask_in[1369] + PIN rw0_wmask_in[1370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.487 129.961 62.505 130.015 ; + END + END rw0_wmask_in[1370] + PIN rw0_wmask_in[1371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.667 129.961 62.685 130.015 ; + END + END rw0_wmask_in[1371] + PIN rw0_wmask_in[1372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 129.961 62.865 130.015 ; + END + END rw0_wmask_in[1372] + PIN rw0_wmask_in[1373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.027 129.961 63.045 130.015 ; + END + END rw0_wmask_in[1373] + PIN rw0_wmask_in[1374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.207 129.961 63.225 130.015 ; + END + END rw0_wmask_in[1374] + PIN rw0_wmask_in[1375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 129.961 63.405 130.015 ; + END + END rw0_wmask_in[1375] + PIN rw0_wmask_in[1376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 129.961 63.585 130.015 ; + END + END rw0_wmask_in[1376] + PIN rw0_wmask_in[1377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.747 129.961 63.765 130.015 ; + END + END rw0_wmask_in[1377] + PIN rw0_wmask_in[1378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.927 129.961 63.945 130.015 ; + END + END rw0_wmask_in[1378] + PIN rw0_wmask_in[1379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.107 129.961 64.125 130.015 ; + END + END rw0_wmask_in[1379] + PIN rw0_wmask_in[1380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.287 129.961 64.305 130.015 ; + END + END rw0_wmask_in[1380] + PIN rw0_wmask_in[1381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.467 129.961 64.485 130.015 ; + END + END rw0_wmask_in[1381] + PIN rw0_wmask_in[1382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.647 129.961 64.665 130.015 ; + END + END rw0_wmask_in[1382] + PIN rw0_wmask_in[1383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.827 129.961 64.845 130.015 ; + END + END rw0_wmask_in[1383] + PIN rw0_wmask_in[1384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 129.961 65.025 130.015 ; + END + END rw0_wmask_in[1384] + PIN rw0_wmask_in[1385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.187 129.961 65.205 130.015 ; + END + END rw0_wmask_in[1385] + PIN rw0_wmask_in[1386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.367 129.961 65.385 130.015 ; + END + END rw0_wmask_in[1386] + PIN rw0_wmask_in[1387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.547 129.961 65.565 130.015 ; + END + END rw0_wmask_in[1387] + PIN rw0_wmask_in[1388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.727 129.961 65.745 130.015 ; + END + END rw0_wmask_in[1388] + PIN rw0_wmask_in[1389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.907 129.961 65.925 130.015 ; + END + END rw0_wmask_in[1389] + PIN rw0_wmask_in[1390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.087 129.961 66.105 130.015 ; + END + END rw0_wmask_in[1390] + PIN rw0_wmask_in[1391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.267 129.961 66.285 130.015 ; + END + END rw0_wmask_in[1391] + PIN rw0_wmask_in[1392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 129.961 66.465 130.015 ; + END + END rw0_wmask_in[1392] + PIN rw0_wmask_in[1393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.627 129.961 66.645 130.015 ; + END + END rw0_wmask_in[1393] + PIN rw0_wmask_in[1394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.807 129.961 66.825 130.015 ; + END + END rw0_wmask_in[1394] + PIN rw0_wmask_in[1395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.987 129.961 67.005 130.015 ; + END + END rw0_wmask_in[1395] + PIN rw0_wmask_in[1396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.167 129.961 67.185 130.015 ; + END + END rw0_wmask_in[1396] + PIN rw0_wmask_in[1397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.347 129.961 67.365 130.015 ; + END + END rw0_wmask_in[1397] + PIN rw0_wmask_in[1398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.527 129.961 67.545 130.015 ; + END + END rw0_wmask_in[1398] + PIN rw0_wmask_in[1399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.707 129.961 67.725 130.015 ; + END + END rw0_wmask_in[1399] + PIN rw0_wmask_in[1400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 129.961 67.905 130.015 ; + END + END rw0_wmask_in[1400] + PIN rw0_wmask_in[1401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.067 129.961 68.085 130.015 ; + END + END rw0_wmask_in[1401] + PIN rw0_wmask_in[1402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.247 129.961 68.265 130.015 ; + END + END rw0_wmask_in[1402] + PIN rw0_wmask_in[1403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.427 129.961 68.445 130.015 ; + END + END rw0_wmask_in[1403] + PIN rw0_wmask_in[1404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.607 129.961 68.625 130.015 ; + END + END rw0_wmask_in[1404] + PIN rw0_wmask_in[1405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.787 129.961 68.805 130.015 ; + END + END rw0_wmask_in[1405] + PIN rw0_wmask_in[1406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.967 129.961 68.985 130.015 ; + END + END rw0_wmask_in[1406] + PIN rw0_wmask_in[1407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.147 129.961 69.165 130.015 ; + END + END rw0_wmask_in[1407] + PIN rw0_wmask_in[1408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 129.961 69.345 130.015 ; + END + END rw0_wmask_in[1408] + PIN rw0_wmask_in[1409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.507 129.961 69.525 130.015 ; + END + END rw0_wmask_in[1409] + PIN rw0_wmask_in[1410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.687 129.961 69.705 130.015 ; + END + END rw0_wmask_in[1410] + PIN rw0_wmask_in[1411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.867 129.961 69.885 130.015 ; + END + END rw0_wmask_in[1411] + PIN rw0_wmask_in[1412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.047 129.961 70.065 130.015 ; + END + END rw0_wmask_in[1412] + PIN rw0_wmask_in[1413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.227 129.961 70.245 130.015 ; + END + END rw0_wmask_in[1413] + PIN rw0_wmask_in[1414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.407 129.961 70.425 130.015 ; + END + END rw0_wmask_in[1414] + PIN rw0_wmask_in[1415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.587 129.961 70.605 130.015 ; + END + END rw0_wmask_in[1415] + PIN rw0_wmask_in[1416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 129.961 70.785 130.015 ; + END + END rw0_wmask_in[1416] + PIN rw0_wmask_in[1417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.947 129.961 70.965 130.015 ; + END + END rw0_wmask_in[1417] + PIN rw0_wmask_in[1418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.127 129.961 71.145 130.015 ; + END + END rw0_wmask_in[1418] + PIN rw0_wmask_in[1419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.307 129.961 71.325 130.015 ; + END + END rw0_wmask_in[1419] + PIN rw0_wmask_in[1420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.487 129.961 71.505 130.015 ; + END + END rw0_wmask_in[1420] + PIN rw0_wmask_in[1421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.667 129.961 71.685 130.015 ; + END + END rw0_wmask_in[1421] + PIN rw0_wmask_in[1422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.847 129.961 71.865 130.015 ; + END + END rw0_wmask_in[1422] + PIN rw0_wmask_in[1423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.027 129.961 72.045 130.015 ; + END + END rw0_wmask_in[1423] + PIN rw0_wmask_in[1424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 129.961 72.225 130.015 ; + END + END rw0_wmask_in[1424] + PIN rw0_wmask_in[1425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.387 129.961 72.405 130.015 ; + END + END rw0_wmask_in[1425] + PIN rw0_wmask_in[1426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.567 129.961 72.585 130.015 ; + END + END rw0_wmask_in[1426] + PIN rw0_wmask_in[1427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.747 129.961 72.765 130.015 ; + END + END rw0_wmask_in[1427] + PIN rw0_wmask_in[1428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.927 129.961 72.945 130.015 ; + END + END rw0_wmask_in[1428] + PIN rw0_wmask_in[1429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.107 129.961 73.125 130.015 ; + END + END rw0_wmask_in[1429] + PIN rw0_wmask_in[1430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.287 129.961 73.305 130.015 ; + END + END rw0_wmask_in[1430] + PIN rw0_wmask_in[1431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.467 129.961 73.485 130.015 ; + END + END rw0_wmask_in[1431] + PIN rw0_wmask_in[1432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 129.961 73.665 130.015 ; + END + END rw0_wmask_in[1432] + PIN rw0_wmask_in[1433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.827 129.961 73.845 130.015 ; + END + END rw0_wmask_in[1433] + PIN rw0_wmask_in[1434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.007 129.961 74.025 130.015 ; + END + END rw0_wmask_in[1434] + PIN rw0_wmask_in[1435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.187 129.961 74.205 130.015 ; + END + END rw0_wmask_in[1435] + PIN rw0_wmask_in[1436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.367 129.961 74.385 130.015 ; + END + END rw0_wmask_in[1436] + PIN rw0_wmask_in[1437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.547 129.961 74.565 130.015 ; + END + END rw0_wmask_in[1437] + PIN rw0_wmask_in[1438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.727 129.961 74.745 130.015 ; + END + END rw0_wmask_in[1438] + PIN rw0_wmask_in[1439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.907 129.961 74.925 130.015 ; + END + END rw0_wmask_in[1439] + PIN rw0_wmask_in[1440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 129.961 75.105 130.015 ; + END + END rw0_wmask_in[1440] + PIN rw0_wmask_in[1441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.267 129.961 75.285 130.015 ; + END + END rw0_wmask_in[1441] + PIN rw0_wmask_in[1442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.447 129.961 75.465 130.015 ; + END + END rw0_wmask_in[1442] + PIN rw0_wmask_in[1443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.627 129.961 75.645 130.015 ; + END + END rw0_wmask_in[1443] + PIN rw0_wmask_in[1444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.807 129.961 75.825 130.015 ; + END + END rw0_wmask_in[1444] + PIN rw0_wmask_in[1445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.987 129.961 76.005 130.015 ; + END + END rw0_wmask_in[1445] + PIN rw0_wmask_in[1446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.167 129.961 76.185 130.015 ; + END + END rw0_wmask_in[1446] + PIN rw0_wmask_in[1447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.347 129.961 76.365 130.015 ; + END + END rw0_wmask_in[1447] + PIN rw0_wmask_in[1448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 129.961 76.545 130.015 ; + END + END rw0_wmask_in[1448] + PIN rw0_wmask_in[1449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.707 129.961 76.725 130.015 ; + END + END rw0_wmask_in[1449] + PIN rw0_wmask_in[1450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.887 129.961 76.905 130.015 ; + END + END rw0_wmask_in[1450] + PIN rw0_wmask_in[1451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.067 129.961 77.085 130.015 ; + END + END rw0_wmask_in[1451] + PIN rw0_wmask_in[1452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.247 129.961 77.265 130.015 ; + END + END rw0_wmask_in[1452] + PIN rw0_wmask_in[1453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.427 129.961 77.445 130.015 ; + END + END rw0_wmask_in[1453] + PIN rw0_wmask_in[1454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.607 129.961 77.625 130.015 ; + END + END rw0_wmask_in[1454] + PIN rw0_wmask_in[1455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.787 129.961 77.805 130.015 ; + END + END rw0_wmask_in[1455] + PIN rw0_wmask_in[1456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 129.961 77.985 130.015 ; + END + END rw0_wmask_in[1456] + PIN rw0_wmask_in[1457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.147 129.961 78.165 130.015 ; + END + END rw0_wmask_in[1457] + PIN rw0_wmask_in[1458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.327 129.961 78.345 130.015 ; + END + END rw0_wmask_in[1458] + PIN rw0_wmask_in[1459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.507 129.961 78.525 130.015 ; + END + END rw0_wmask_in[1459] + PIN rw0_wmask_in[1460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.687 129.961 78.705 130.015 ; + END + END rw0_wmask_in[1460] + PIN rw0_wmask_in[1461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.867 129.961 78.885 130.015 ; + END + END rw0_wmask_in[1461] + PIN rw0_wmask_in[1462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.047 129.961 79.065 130.015 ; + END + END rw0_wmask_in[1462] + PIN rw0_wmask_in[1463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.227 129.961 79.245 130.015 ; + END + END rw0_wmask_in[1463] + PIN rw0_wmask_in[1464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 129.961 79.425 130.015 ; + END + END rw0_wmask_in[1464] + PIN rw0_wmask_in[1465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.587 129.961 79.605 130.015 ; + END + END rw0_wmask_in[1465] + PIN rw0_wmask_in[1466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.767 129.961 79.785 130.015 ; + END + END rw0_wmask_in[1466] + PIN rw0_wmask_in[1467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.947 129.961 79.965 130.015 ; + END + END rw0_wmask_in[1467] + PIN rw0_wmask_in[1468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.127 129.961 80.145 130.015 ; + END + END rw0_wmask_in[1468] + PIN rw0_wmask_in[1469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.307 129.961 80.325 130.015 ; + END + END rw0_wmask_in[1469] + PIN rw0_wmask_in[1470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.487 129.961 80.505 130.015 ; + END + END rw0_wmask_in[1470] + PIN rw0_wmask_in[1471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.667 129.961 80.685 130.015 ; + END + END rw0_wmask_in[1471] + PIN rw0_wmask_in[1472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 129.961 80.865 130.015 ; + END + END rw0_wmask_in[1472] + PIN rw0_wmask_in[1473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.027 129.961 81.045 130.015 ; + END + END rw0_wmask_in[1473] + PIN rw0_wmask_in[1474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.207 129.961 81.225 130.015 ; + END + END rw0_wmask_in[1474] + PIN rw0_wmask_in[1475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.387 129.961 81.405 130.015 ; + END + END rw0_wmask_in[1475] + PIN rw0_wmask_in[1476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.567 129.961 81.585 130.015 ; + END + END rw0_wmask_in[1476] + PIN rw0_wmask_in[1477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.747 129.961 81.765 130.015 ; + END + END rw0_wmask_in[1477] + PIN rw0_wmask_in[1478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.927 129.961 81.945 130.015 ; + END + END rw0_wmask_in[1478] + PIN rw0_wmask_in[1479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.107 129.961 82.125 130.015 ; + END + END rw0_wmask_in[1479] + PIN rw0_wmask_in[1480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 129.961 82.305 130.015 ; + END + END rw0_wmask_in[1480] + PIN rw0_wmask_in[1481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.467 129.961 82.485 130.015 ; + END + END rw0_wmask_in[1481] + PIN rw0_wmask_in[1482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.647 129.961 82.665 130.015 ; + END + END rw0_wmask_in[1482] + PIN rw0_wmask_in[1483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.827 129.961 82.845 130.015 ; + END + END rw0_wmask_in[1483] + PIN rw0_wmask_in[1484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.007 129.961 83.025 130.015 ; + END + END rw0_wmask_in[1484] + PIN rw0_wmask_in[1485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.187 129.961 83.205 130.015 ; + END + END rw0_wmask_in[1485] + PIN rw0_wmask_in[1486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.367 129.961 83.385 130.015 ; + END + END rw0_wmask_in[1486] + PIN rw0_wmask_in[1487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.547 129.961 83.565 130.015 ; + END + END rw0_wmask_in[1487] + PIN rw0_wmask_in[1488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 129.961 83.745 130.015 ; + END + END rw0_wmask_in[1488] + PIN rw0_wmask_in[1489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.907 129.961 83.925 130.015 ; + END + END rw0_wmask_in[1489] + PIN rw0_wmask_in[1490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.087 129.961 84.105 130.015 ; + END + END rw0_wmask_in[1490] + PIN rw0_wmask_in[1491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.267 129.961 84.285 130.015 ; + END + END rw0_wmask_in[1491] + PIN rw0_wmask_in[1492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.447 129.961 84.465 130.015 ; + END + END rw0_wmask_in[1492] + PIN rw0_wmask_in[1493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.627 129.961 84.645 130.015 ; + END + END rw0_wmask_in[1493] + PIN rw0_wmask_in[1494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.807 129.961 84.825 130.015 ; + END + END rw0_wmask_in[1494] + PIN rw0_wmask_in[1495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.987 129.961 85.005 130.015 ; + END + END rw0_wmask_in[1495] + PIN rw0_wmask_in[1496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 129.961 85.185 130.015 ; + END + END rw0_wmask_in[1496] + PIN rw0_wmask_in[1497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.347 129.961 85.365 130.015 ; + END + END rw0_wmask_in[1497] + PIN rw0_wmask_in[1498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.527 129.961 85.545 130.015 ; + END + END rw0_wmask_in[1498] + PIN rw0_wmask_in[1499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.707 129.961 85.725 130.015 ; + END + END rw0_wmask_in[1499] + PIN rw0_wmask_in[1500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.887 129.961 85.905 130.015 ; + END + END rw0_wmask_in[1500] + PIN rw0_wmask_in[1501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.067 129.961 86.085 130.015 ; + END + END rw0_wmask_in[1501] + PIN rw0_wmask_in[1502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.247 129.961 86.265 130.015 ; + END + END rw0_wmask_in[1502] + PIN rw0_wmask_in[1503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.427 129.961 86.445 130.015 ; + END + END rw0_wmask_in[1503] + PIN rw0_wmask_in[1504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 129.961 86.625 130.015 ; + END + END rw0_wmask_in[1504] + PIN rw0_wmask_in[1505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.787 129.961 86.805 130.015 ; + END + END rw0_wmask_in[1505] + PIN rw0_wmask_in[1506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.967 129.961 86.985 130.015 ; + END + END rw0_wmask_in[1506] + PIN rw0_wmask_in[1507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.147 129.961 87.165 130.015 ; + END + END rw0_wmask_in[1507] + PIN rw0_wmask_in[1508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.327 129.961 87.345 130.015 ; + END + END rw0_wmask_in[1508] + PIN rw0_wmask_in[1509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.507 129.961 87.525 130.015 ; + END + END rw0_wmask_in[1509] + PIN rw0_wmask_in[1510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.687 129.961 87.705 130.015 ; + END + END rw0_wmask_in[1510] + PIN rw0_wmask_in[1511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.867 129.961 87.885 130.015 ; + END + END rw0_wmask_in[1511] + PIN rw0_wmask_in[1512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 129.961 88.065 130.015 ; + END + END rw0_wmask_in[1512] + PIN rw0_wmask_in[1513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.227 129.961 88.245 130.015 ; + END + END rw0_wmask_in[1513] + PIN rw0_wmask_in[1514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.407 129.961 88.425 130.015 ; + END + END rw0_wmask_in[1514] + PIN rw0_wmask_in[1515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.587 129.961 88.605 130.015 ; + END + END rw0_wmask_in[1515] + PIN rw0_wmask_in[1516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.767 129.961 88.785 130.015 ; + END + END rw0_wmask_in[1516] + PIN rw0_wmask_in[1517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.947 129.961 88.965 130.015 ; + END + END rw0_wmask_in[1517] + PIN rw0_wmask_in[1518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.127 129.961 89.145 130.015 ; + END + END rw0_wmask_in[1518] + PIN rw0_wmask_in[1519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.307 129.961 89.325 130.015 ; + END + END rw0_wmask_in[1519] + PIN rw0_wmask_in[1520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 129.961 89.505 130.015 ; + END + END rw0_wmask_in[1520] + PIN rw0_wmask_in[1521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.667 129.961 89.685 130.015 ; + END + END rw0_wmask_in[1521] + PIN rw0_wmask_in[1522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.847 129.961 89.865 130.015 ; + END + END rw0_wmask_in[1522] + PIN rw0_wmask_in[1523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.027 129.961 90.045 130.015 ; + END + END rw0_wmask_in[1523] + PIN rw0_wmask_in[1524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.207 129.961 90.225 130.015 ; + END + END rw0_wmask_in[1524] + PIN rw0_wmask_in[1525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.387 129.961 90.405 130.015 ; + END + END rw0_wmask_in[1525] + PIN rw0_wmask_in[1526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.567 129.961 90.585 130.015 ; + END + END rw0_wmask_in[1526] + PIN rw0_wmask_in[1527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.747 129.961 90.765 130.015 ; + END + END rw0_wmask_in[1527] + PIN rw0_wmask_in[1528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 129.961 90.945 130.015 ; + END + END rw0_wmask_in[1528] + PIN rw0_wmask_in[1529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.107 129.961 91.125 130.015 ; + END + END rw0_wmask_in[1529] + PIN rw0_wmask_in[1530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.287 129.961 91.305 130.015 ; + END + END rw0_wmask_in[1530] + PIN rw0_wmask_in[1531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.467 129.961 91.485 130.015 ; + END + END rw0_wmask_in[1531] + PIN rw0_wmask_in[1532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.647 129.961 91.665 130.015 ; + END + END rw0_wmask_in[1532] + PIN rw0_wmask_in[1533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.827 129.961 91.845 130.015 ; + END + END rw0_wmask_in[1533] + PIN rw0_wmask_in[1534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.007 129.961 92.025 130.015 ; + END + END rw0_wmask_in[1534] + PIN rw0_wmask_in[1535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.187 129.961 92.205 130.015 ; + END + END rw0_wmask_in[1535] + PIN rw0_wmask_in[1536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 129.961 92.385 130.015 ; + END + END rw0_wmask_in[1536] + PIN rw0_wmask_in[1537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.547 129.961 92.565 130.015 ; + END + END rw0_wmask_in[1537] + PIN rw0_wmask_in[1538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.727 129.961 92.745 130.015 ; + END + END rw0_wmask_in[1538] + PIN rw0_wmask_in[1539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.907 129.961 92.925 130.015 ; + END + END rw0_wmask_in[1539] + PIN rw0_wmask_in[1540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.087 129.961 93.105 130.015 ; + END + END rw0_wmask_in[1540] + PIN rw0_wmask_in[1541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.267 129.961 93.285 130.015 ; + END + END rw0_wmask_in[1541] + PIN rw0_wmask_in[1542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.447 129.961 93.465 130.015 ; + END + END rw0_wmask_in[1542] + PIN rw0_wmask_in[1543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.627 129.961 93.645 130.015 ; + END + END rw0_wmask_in[1543] + PIN rw0_wmask_in[1544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 129.961 93.825 130.015 ; + END + END rw0_wmask_in[1544] + PIN rw0_wmask_in[1545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.987 129.961 94.005 130.015 ; + END + END rw0_wmask_in[1545] + PIN rw0_wmask_in[1546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.167 129.961 94.185 130.015 ; + END + END rw0_wmask_in[1546] + PIN rw0_wmask_in[1547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.347 129.961 94.365 130.015 ; + END + END rw0_wmask_in[1547] + PIN rw0_wmask_in[1548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.527 129.961 94.545 130.015 ; + END + END rw0_wmask_in[1548] + PIN rw0_wmask_in[1549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.707 129.961 94.725 130.015 ; + END + END rw0_wmask_in[1549] + PIN rw0_wmask_in[1550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.887 129.961 94.905 130.015 ; + END + END rw0_wmask_in[1550] + PIN rw0_wmask_in[1551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.067 129.961 95.085 130.015 ; + END + END rw0_wmask_in[1551] + PIN rw0_wmask_in[1552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 129.961 95.265 130.015 ; + END + END rw0_wmask_in[1552] + PIN rw0_wmask_in[1553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.427 129.961 95.445 130.015 ; + END + END rw0_wmask_in[1553] + PIN rw0_wmask_in[1554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.607 129.961 95.625 130.015 ; + END + END rw0_wmask_in[1554] + PIN rw0_wmask_in[1555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.787 129.961 95.805 130.015 ; + END + END rw0_wmask_in[1555] + PIN rw0_wmask_in[1556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.967 129.961 95.985 130.015 ; + END + END rw0_wmask_in[1556] + PIN rw0_wmask_in[1557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.147 129.961 96.165 130.015 ; + END + END rw0_wmask_in[1557] + PIN rw0_wmask_in[1558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.327 129.961 96.345 130.015 ; + END + END rw0_wmask_in[1558] + PIN rw0_wmask_in[1559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.507 129.961 96.525 130.015 ; + END + END rw0_wmask_in[1559] + PIN rw0_wmask_in[1560] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 129.961 96.705 130.015 ; + END + END rw0_wmask_in[1560] + PIN rw0_wmask_in[1561] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.867 129.961 96.885 130.015 ; + END + END rw0_wmask_in[1561] + PIN rw0_wmask_in[1562] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.047 129.961 97.065 130.015 ; + END + END rw0_wmask_in[1562] + PIN rw0_wmask_in[1563] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.227 129.961 97.245 130.015 ; + END + END rw0_wmask_in[1563] + PIN rw0_wmask_in[1564] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.407 129.961 97.425 130.015 ; + END + END rw0_wmask_in[1564] + PIN rw0_wmask_in[1565] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.587 129.961 97.605 130.015 ; + END + END rw0_wmask_in[1565] + PIN rw0_wmask_in[1566] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.767 129.961 97.785 130.015 ; + END + END rw0_wmask_in[1566] + PIN rw0_wmask_in[1567] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.947 129.961 97.965 130.015 ; + END + END rw0_wmask_in[1567] + PIN rw0_wmask_in[1568] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 129.961 98.145 130.015 ; + END + END rw0_wmask_in[1568] + PIN rw0_wmask_in[1569] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.307 129.961 98.325 130.015 ; + END + END rw0_wmask_in[1569] + PIN rw0_wmask_in[1570] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.487 129.961 98.505 130.015 ; + END + END rw0_wmask_in[1570] + PIN rw0_wmask_in[1571] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.667 129.961 98.685 130.015 ; + END + END rw0_wmask_in[1571] + PIN rw0_wmask_in[1572] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.847 129.961 98.865 130.015 ; + END + END rw0_wmask_in[1572] + PIN rw0_wmask_in[1573] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.027 129.961 99.045 130.015 ; + END + END rw0_wmask_in[1573] + PIN rw0_wmask_in[1574] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.207 129.961 99.225 130.015 ; + END + END rw0_wmask_in[1574] + PIN rw0_wmask_in[1575] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.387 129.961 99.405 130.015 ; + END + END rw0_wmask_in[1575] + PIN rw0_wmask_in[1576] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 129.961 99.585 130.015 ; + END + END rw0_wmask_in[1576] + PIN rw0_wmask_in[1577] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.747 129.961 99.765 130.015 ; + END + END rw0_wmask_in[1577] + PIN rw0_wmask_in[1578] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.927 129.961 99.945 130.015 ; + END + END rw0_wmask_in[1578] + PIN rw0_wmask_in[1579] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.107 129.961 100.125 130.015 ; + END + END rw0_wmask_in[1579] + PIN rw0_wmask_in[1580] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.287 129.961 100.305 130.015 ; + END + END rw0_wmask_in[1580] + PIN rw0_wmask_in[1581] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.467 129.961 100.485 130.015 ; + END + END rw0_wmask_in[1581] + PIN rw0_wmask_in[1582] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.647 129.961 100.665 130.015 ; + END + END rw0_wmask_in[1582] + PIN rw0_wmask_in[1583] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.827 129.961 100.845 130.015 ; + END + END rw0_wmask_in[1583] + PIN rw0_wmask_in[1584] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 129.961 101.025 130.015 ; + END + END rw0_wmask_in[1584] + PIN rw0_wmask_in[1585] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.187 129.961 101.205 130.015 ; + END + END rw0_wmask_in[1585] + PIN rw0_wmask_in[1586] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.367 129.961 101.385 130.015 ; + END + END rw0_wmask_in[1586] + PIN rw0_wmask_in[1587] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.547 129.961 101.565 130.015 ; + END + END rw0_wmask_in[1587] + PIN rw0_wmask_in[1588] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.727 129.961 101.745 130.015 ; + END + END rw0_wmask_in[1588] + PIN rw0_wmask_in[1589] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.907 129.961 101.925 130.015 ; + END + END rw0_wmask_in[1589] + PIN rw0_wmask_in[1590] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.087 129.961 102.105 130.015 ; + END + END rw0_wmask_in[1590] + PIN rw0_wmask_in[1591] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.267 129.961 102.285 130.015 ; + END + END rw0_wmask_in[1591] + PIN rw0_wmask_in[1592] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 129.961 102.465 130.015 ; + END + END rw0_wmask_in[1592] + PIN rw0_wmask_in[1593] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.627 129.961 102.645 130.015 ; + END + END rw0_wmask_in[1593] + PIN rw0_wmask_in[1594] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.807 129.961 102.825 130.015 ; + END + END rw0_wmask_in[1594] + PIN rw0_wmask_in[1595] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.987 129.961 103.005 130.015 ; + END + END rw0_wmask_in[1595] + PIN rw0_wmask_in[1596] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.167 129.961 103.185 130.015 ; + END + END rw0_wmask_in[1596] + PIN rw0_wmask_in[1597] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.347 129.961 103.365 130.015 ; + END + END rw0_wmask_in[1597] + PIN rw0_wmask_in[1598] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.527 129.961 103.545 130.015 ; + END + END rw0_wmask_in[1598] + PIN rw0_wmask_in[1599] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.707 129.961 103.725 130.015 ; + END + END rw0_wmask_in[1599] + PIN rw0_wmask_in[1600] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 129.961 103.905 130.015 ; + END + END rw0_wmask_in[1600] + PIN rw0_wmask_in[1601] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.067 129.961 104.085 130.015 ; + END + END rw0_wmask_in[1601] + PIN rw0_wmask_in[1602] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.247 129.961 104.265 130.015 ; + END + END rw0_wmask_in[1602] + PIN rw0_wmask_in[1603] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.427 129.961 104.445 130.015 ; + END + END rw0_wmask_in[1603] + PIN rw0_wmask_in[1604] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.607 129.961 104.625 130.015 ; + END + END rw0_wmask_in[1604] + PIN rw0_wmask_in[1605] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.787 129.961 104.805 130.015 ; + END + END rw0_wmask_in[1605] + PIN rw0_wmask_in[1606] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.967 129.961 104.985 130.015 ; + END + END rw0_wmask_in[1606] + PIN rw0_wmask_in[1607] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.147 129.961 105.165 130.015 ; + END + END rw0_wmask_in[1607] + PIN rw0_wmask_in[1608] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 129.961 105.345 130.015 ; + END + END rw0_wmask_in[1608] + PIN rw0_wmask_in[1609] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.507 129.961 105.525 130.015 ; + END + END rw0_wmask_in[1609] + PIN rw0_wmask_in[1610] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.687 129.961 105.705 130.015 ; + END + END rw0_wmask_in[1610] + PIN rw0_wmask_in[1611] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.867 129.961 105.885 130.015 ; + END + END rw0_wmask_in[1611] + PIN rw0_wmask_in[1612] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.047 129.961 106.065 130.015 ; + END + END rw0_wmask_in[1612] + PIN rw0_wmask_in[1613] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.227 129.961 106.245 130.015 ; + END + END rw0_wmask_in[1613] + PIN rw0_wmask_in[1614] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.407 129.961 106.425 130.015 ; + END + END rw0_wmask_in[1614] + PIN rw0_wmask_in[1615] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.587 129.961 106.605 130.015 ; + END + END rw0_wmask_in[1615] + PIN rw0_wmask_in[1616] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 129.961 106.785 130.015 ; + END + END rw0_wmask_in[1616] + PIN rw0_wmask_in[1617] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.947 129.961 106.965 130.015 ; + END + END rw0_wmask_in[1617] + PIN rw0_wmask_in[1618] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.127 129.961 107.145 130.015 ; + END + END rw0_wmask_in[1618] + PIN rw0_wmask_in[1619] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.307 129.961 107.325 130.015 ; + END + END rw0_wmask_in[1619] + PIN rw0_wmask_in[1620] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.487 129.961 107.505 130.015 ; + END + END rw0_wmask_in[1620] + PIN rw0_wmask_in[1621] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.667 129.961 107.685 130.015 ; + END + END rw0_wmask_in[1621] + PIN rw0_wmask_in[1622] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.847 129.961 107.865 130.015 ; + END + END rw0_wmask_in[1622] + PIN rw0_wmask_in[1623] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.027 129.961 108.045 130.015 ; + END + END rw0_wmask_in[1623] + PIN rw0_wmask_in[1624] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 129.961 108.225 130.015 ; + END + END rw0_wmask_in[1624] + PIN rw0_wmask_in[1625] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.387 129.961 108.405 130.015 ; + END + END rw0_wmask_in[1625] + PIN rw0_wmask_in[1626] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.567 129.961 108.585 130.015 ; + END + END rw0_wmask_in[1626] + PIN rw0_wmask_in[1627] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.747 129.961 108.765 130.015 ; + END + END rw0_wmask_in[1627] + PIN rw0_wmask_in[1628] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.927 129.961 108.945 130.015 ; + END + END rw0_wmask_in[1628] + PIN rw0_wmask_in[1629] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.107 129.961 109.125 130.015 ; + END + END rw0_wmask_in[1629] + PIN rw0_wmask_in[1630] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.287 129.961 109.305 130.015 ; + END + END rw0_wmask_in[1630] + PIN rw0_wmask_in[1631] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.467 129.961 109.485 130.015 ; + END + END rw0_wmask_in[1631] + PIN rw0_wmask_in[1632] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 129.961 109.665 130.015 ; + END + END rw0_wmask_in[1632] + PIN rw0_wmask_in[1633] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.827 129.961 109.845 130.015 ; + END + END rw0_wmask_in[1633] + PIN rw0_wmask_in[1634] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.007 129.961 110.025 130.015 ; + END + END rw0_wmask_in[1634] + PIN rw0_wmask_in[1635] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.187 129.961 110.205 130.015 ; + END + END rw0_wmask_in[1635] + PIN rw0_wmask_in[1636] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.367 129.961 110.385 130.015 ; + END + END rw0_wmask_in[1636] + PIN rw0_wmask_in[1637] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.547 129.961 110.565 130.015 ; + END + END rw0_wmask_in[1637] + PIN rw0_wmask_in[1638] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.727 129.961 110.745 130.015 ; + END + END rw0_wmask_in[1638] + PIN rw0_wmask_in[1639] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.907 129.961 110.925 130.015 ; + END + END rw0_wmask_in[1639] + PIN rw0_wmask_in[1640] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 129.961 111.105 130.015 ; + END + END rw0_wmask_in[1640] + PIN rw0_wmask_in[1641] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.267 129.961 111.285 130.015 ; + END + END rw0_wmask_in[1641] + PIN rw0_wmask_in[1642] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.447 129.961 111.465 130.015 ; + END + END rw0_wmask_in[1642] + PIN rw0_wmask_in[1643] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.627 129.961 111.645 130.015 ; + END + END rw0_wmask_in[1643] + PIN rw0_wmask_in[1644] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.807 129.961 111.825 130.015 ; + END + END rw0_wmask_in[1644] + PIN rw0_wmask_in[1645] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.987 129.961 112.005 130.015 ; + END + END rw0_wmask_in[1645] + PIN rw0_wmask_in[1646] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.167 129.961 112.185 130.015 ; + END + END rw0_wmask_in[1646] + PIN rw0_wmask_in[1647] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.347 129.961 112.365 130.015 ; + END + END rw0_wmask_in[1647] + PIN rw0_wmask_in[1648] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 129.961 112.545 130.015 ; + END + END rw0_wmask_in[1648] + PIN rw0_wmask_in[1649] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.707 129.961 112.725 130.015 ; + END + END rw0_wmask_in[1649] + PIN rw0_wmask_in[1650] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.887 129.961 112.905 130.015 ; + END + END rw0_wmask_in[1650] + PIN rw0_wmask_in[1651] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.067 129.961 113.085 130.015 ; + END + END rw0_wmask_in[1651] + PIN rw0_wmask_in[1652] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.247 129.961 113.265 130.015 ; + END + END rw0_wmask_in[1652] + PIN rw0_wmask_in[1653] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.427 129.961 113.445 130.015 ; + END + END rw0_wmask_in[1653] + PIN rw0_wmask_in[1654] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.607 129.961 113.625 130.015 ; + END + END rw0_wmask_in[1654] + PIN rw0_wmask_in[1655] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.787 129.961 113.805 130.015 ; + END + END rw0_wmask_in[1655] + PIN rw0_wmask_in[1656] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 129.961 113.985 130.015 ; + END + END rw0_wmask_in[1656] + PIN rw0_wmask_in[1657] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.147 129.961 114.165 130.015 ; + END + END rw0_wmask_in[1657] + PIN rw0_wmask_in[1658] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.327 129.961 114.345 130.015 ; + END + END rw0_wmask_in[1658] + PIN rw0_wmask_in[1659] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.507 129.961 114.525 130.015 ; + END + END rw0_wmask_in[1659] + PIN rw0_wmask_in[1660] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.687 129.961 114.705 130.015 ; + END + END rw0_wmask_in[1660] + PIN rw0_wmask_in[1661] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.867 129.961 114.885 130.015 ; + END + END rw0_wmask_in[1661] + PIN rw0_wmask_in[1662] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.047 129.961 115.065 130.015 ; + END + END rw0_wmask_in[1662] + PIN rw0_wmask_in[1663] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.227 129.961 115.245 130.015 ; + END + END rw0_wmask_in[1663] + PIN rw0_wmask_in[1664] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 129.961 115.425 130.015 ; + END + END rw0_wmask_in[1664] + PIN rw0_wmask_in[1665] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.587 129.961 115.605 130.015 ; + END + END rw0_wmask_in[1665] + PIN rw0_wmask_in[1666] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.767 129.961 115.785 130.015 ; + END + END rw0_wmask_in[1666] + PIN rw0_wmask_in[1667] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.947 129.961 115.965 130.015 ; + END + END rw0_wmask_in[1667] + PIN rw0_wmask_in[1668] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.127 129.961 116.145 130.015 ; + END + END rw0_wmask_in[1668] + PIN rw0_wmask_in[1669] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.307 129.961 116.325 130.015 ; + END + END rw0_wmask_in[1669] + PIN rw0_wmask_in[1670] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.487 129.961 116.505 130.015 ; + END + END rw0_wmask_in[1670] + PIN rw0_wmask_in[1671] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.667 129.961 116.685 130.015 ; + END + END rw0_wmask_in[1671] + PIN rw0_wmask_in[1672] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 129.961 116.865 130.015 ; + END + END rw0_wmask_in[1672] + PIN rw0_wmask_in[1673] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.027 129.961 117.045 130.015 ; + END + END rw0_wmask_in[1673] + PIN rw0_wmask_in[1674] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.207 129.961 117.225 130.015 ; + END + END rw0_wmask_in[1674] + PIN rw0_wmask_in[1675] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.387 129.961 117.405 130.015 ; + END + END rw0_wmask_in[1675] + PIN rw0_wmask_in[1676] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.567 129.961 117.585 130.015 ; + END + END rw0_wmask_in[1676] + PIN rw0_wmask_in[1677] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.747 129.961 117.765 130.015 ; + END + END rw0_wmask_in[1677] + PIN rw0_wmask_in[1678] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.927 129.961 117.945 130.015 ; + END + END rw0_wmask_in[1678] + PIN rw0_wmask_in[1679] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.107 129.961 118.125 130.015 ; + END + END rw0_wmask_in[1679] + PIN rw0_wmask_in[1680] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 129.961 118.305 130.015 ; + END + END rw0_wmask_in[1680] + PIN rw0_wmask_in[1681] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.467 129.961 118.485 130.015 ; + END + END rw0_wmask_in[1681] + PIN rw0_wmask_in[1682] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.647 129.961 118.665 130.015 ; + END + END rw0_wmask_in[1682] + PIN rw0_wmask_in[1683] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.827 129.961 118.845 130.015 ; + END + END rw0_wmask_in[1683] + PIN rw0_wmask_in[1684] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.007 129.961 119.025 130.015 ; + END + END rw0_wmask_in[1684] + PIN rw0_wmask_in[1685] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.187 129.961 119.205 130.015 ; + END + END rw0_wmask_in[1685] + PIN rw0_wmask_in[1686] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.367 129.961 119.385 130.015 ; + END + END rw0_wmask_in[1686] + PIN rw0_wmask_in[1687] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.547 129.961 119.565 130.015 ; + END + END rw0_wmask_in[1687] + PIN rw0_wmask_in[1688] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 129.961 119.745 130.015 ; + END + END rw0_wmask_in[1688] + PIN rw0_wmask_in[1689] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.907 129.961 119.925 130.015 ; + END + END rw0_wmask_in[1689] + PIN rw0_wmask_in[1690] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.087 129.961 120.105 130.015 ; + END + END rw0_wmask_in[1690] + PIN rw0_wmask_in[1691] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.267 129.961 120.285 130.015 ; + END + END rw0_wmask_in[1691] + PIN rw0_wmask_in[1692] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.447 129.961 120.465 130.015 ; + END + END rw0_wmask_in[1692] + PIN rw0_wmask_in[1693] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.627 129.961 120.645 130.015 ; + END + END rw0_wmask_in[1693] + PIN rw0_wmask_in[1694] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.807 129.961 120.825 130.015 ; + END + END rw0_wmask_in[1694] + PIN rw0_wmask_in[1695] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.987 129.961 121.005 130.015 ; + END + END rw0_wmask_in[1695] + PIN rw0_wmask_in[1696] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 129.961 121.185 130.015 ; + END + END rw0_wmask_in[1696] + PIN rw0_wmask_in[1697] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.347 129.961 121.365 130.015 ; + END + END rw0_wmask_in[1697] + PIN rw0_wmask_in[1698] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.527 129.961 121.545 130.015 ; + END + END rw0_wmask_in[1698] + PIN rw0_wmask_in[1699] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.707 129.961 121.725 130.015 ; + END + END rw0_wmask_in[1699] + PIN rw0_wmask_in[1700] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.887 129.961 121.905 130.015 ; + END + END rw0_wmask_in[1700] + PIN rw0_wmask_in[1701] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.067 129.961 122.085 130.015 ; + END + END rw0_wmask_in[1701] + PIN rw0_wmask_in[1702] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.247 129.961 122.265 130.015 ; + END + END rw0_wmask_in[1702] + PIN rw0_wmask_in[1703] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.427 129.961 122.445 130.015 ; + END + END rw0_wmask_in[1703] + PIN rw0_wmask_in[1704] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 129.961 122.625 130.015 ; + END + END rw0_wmask_in[1704] + PIN rw0_wmask_in[1705] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.787 129.961 122.805 130.015 ; + END + END rw0_wmask_in[1705] + PIN rw0_wmask_in[1706] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.967 129.961 122.985 130.015 ; + END + END rw0_wmask_in[1706] + PIN rw0_wmask_in[1707] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.147 129.961 123.165 130.015 ; + END + END rw0_wmask_in[1707] + PIN rw0_wmask_in[1708] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.327 129.961 123.345 130.015 ; + END + END rw0_wmask_in[1708] + PIN rw0_wmask_in[1709] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.507 129.961 123.525 130.015 ; + END + END rw0_wmask_in[1709] + PIN rw0_wmask_in[1710] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.687 129.961 123.705 130.015 ; + END + END rw0_wmask_in[1710] + PIN rw0_wmask_in[1711] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.867 129.961 123.885 130.015 ; + END + END rw0_wmask_in[1711] + PIN rw0_wmask_in[1712] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 129.961 124.065 130.015 ; + END + END rw0_wmask_in[1712] + PIN rw0_wmask_in[1713] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.227 129.961 124.245 130.015 ; + END + END rw0_wmask_in[1713] + PIN rw0_wmask_in[1714] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.407 129.961 124.425 130.015 ; + END + END rw0_wmask_in[1714] + PIN rw0_wmask_in[1715] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.587 129.961 124.605 130.015 ; + END + END rw0_wmask_in[1715] + PIN rw0_wmask_in[1716] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.767 129.961 124.785 130.015 ; + END + END rw0_wmask_in[1716] + PIN rw0_wmask_in[1717] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.947 129.961 124.965 130.015 ; + END + END rw0_wmask_in[1717] + PIN rw0_wmask_in[1718] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.127 129.961 125.145 130.015 ; + END + END rw0_wmask_in[1718] + PIN rw0_wmask_in[1719] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.307 129.961 125.325 130.015 ; + END + END rw0_wmask_in[1719] + PIN rw0_wmask_in[1720] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 129.961 125.505 130.015 ; + END + END rw0_wmask_in[1720] + PIN rw0_wmask_in[1721] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.667 129.961 125.685 130.015 ; + END + END rw0_wmask_in[1721] + PIN rw0_wmask_in[1722] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.847 129.961 125.865 130.015 ; + END + END rw0_wmask_in[1722] + PIN rw0_wmask_in[1723] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.027 129.961 126.045 130.015 ; + END + END rw0_wmask_in[1723] + PIN rw0_wmask_in[1724] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.207 129.961 126.225 130.015 ; + END + END rw0_wmask_in[1724] + PIN rw0_wmask_in[1725] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.387 129.961 126.405 130.015 ; + END + END rw0_wmask_in[1725] + PIN rw0_wmask_in[1726] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.567 129.961 126.585 130.015 ; + END + END rw0_wmask_in[1726] + PIN rw0_wmask_in[1727] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.747 129.961 126.765 130.015 ; + END + END rw0_wmask_in[1727] + PIN rw0_wmask_in[1728] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 129.961 126.945 130.015 ; + END + END rw0_wmask_in[1728] + PIN rw0_wmask_in[1729] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.107 129.961 127.125 130.015 ; + END + END rw0_wmask_in[1729] + PIN rw0_wmask_in[1730] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.287 129.961 127.305 130.015 ; + END + END rw0_wmask_in[1730] + PIN rw0_wmask_in[1731] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.467 129.961 127.485 130.015 ; + END + END rw0_wmask_in[1731] + PIN rw0_wmask_in[1732] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.647 129.961 127.665 130.015 ; + END + END rw0_wmask_in[1732] + PIN rw0_wmask_in[1733] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.827 129.961 127.845 130.015 ; + END + END rw0_wmask_in[1733] + PIN rw0_wmask_in[1734] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.007 129.961 128.025 130.015 ; + END + END rw0_wmask_in[1734] + PIN rw0_wmask_in[1735] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.187 129.961 128.205 130.015 ; + END + END rw0_wmask_in[1735] + PIN rw0_wmask_in[1736] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 129.961 128.385 130.015 ; + END + END rw0_wmask_in[1736] + PIN rw0_wmask_in[1737] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.547 129.961 128.565 130.015 ; + END + END rw0_wmask_in[1737] + PIN rw0_wmask_in[1738] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.727 129.961 128.745 130.015 ; + END + END rw0_wmask_in[1738] + PIN rw0_wmask_in[1739] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.907 129.961 128.925 130.015 ; + END + END rw0_wmask_in[1739] + PIN rw0_wmask_in[1740] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.087 129.961 129.105 130.015 ; + END + END rw0_wmask_in[1740] + PIN rw0_wmask_in[1741] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.267 129.961 129.285 130.015 ; + END + END rw0_wmask_in[1741] + PIN rw0_wmask_in[1742] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.447 129.961 129.465 130.015 ; + END + END rw0_wmask_in[1742] + PIN rw0_wmask_in[1743] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.627 129.961 129.645 130.015 ; + END + END rw0_wmask_in[1743] + PIN rw0_wmask_in[1744] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 129.961 129.825 130.015 ; + END + END rw0_wmask_in[1744] + PIN rw0_wmask_in[1745] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.987 129.961 130.005 130.015 ; + END + END rw0_wmask_in[1745] + PIN rw0_wmask_in[1746] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.167 129.961 130.185 130.015 ; + END + END rw0_wmask_in[1746] + PIN rw0_wmask_in[1747] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.347 129.961 130.365 130.015 ; + END + END rw0_wmask_in[1747] + PIN rw0_wmask_in[1748] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.527 129.961 130.545 130.015 ; + END + END rw0_wmask_in[1748] + PIN rw0_wmask_in[1749] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.707 129.961 130.725 130.015 ; + END + END rw0_wmask_in[1749] + PIN rw0_wmask_in[1750] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.887 129.961 130.905 130.015 ; + END + END rw0_wmask_in[1750] + PIN rw0_wmask_in[1751] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.067 129.961 131.085 130.015 ; + END + END rw0_wmask_in[1751] + PIN rw0_wmask_in[1752] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 129.961 131.265 130.015 ; + END + END rw0_wmask_in[1752] + PIN rw0_wmask_in[1753] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.427 129.961 131.445 130.015 ; + END + END rw0_wmask_in[1753] + PIN rw0_wmask_in[1754] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.607 129.961 131.625 130.015 ; + END + END rw0_wmask_in[1754] + PIN rw0_wmask_in[1755] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.787 129.961 131.805 130.015 ; + END + END rw0_wmask_in[1755] + PIN rw0_wmask_in[1756] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.967 129.961 131.985 130.015 ; + END + END rw0_wmask_in[1756] + PIN rw0_wmask_in[1757] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.147 129.961 132.165 130.015 ; + END + END rw0_wmask_in[1757] + PIN rw0_wmask_in[1758] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.327 129.961 132.345 130.015 ; + END + END rw0_wmask_in[1758] + PIN rw0_wmask_in[1759] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.507 129.961 132.525 130.015 ; + END + END rw0_wmask_in[1759] + PIN rw0_wmask_in[1760] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 129.961 132.705 130.015 ; + END + END rw0_wmask_in[1760] + PIN rw0_wmask_in[1761] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.867 129.961 132.885 130.015 ; + END + END rw0_wmask_in[1761] + PIN rw0_wmask_in[1762] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.047 129.961 133.065 130.015 ; + END + END rw0_wmask_in[1762] + PIN rw0_wmask_in[1763] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.227 129.961 133.245 130.015 ; + END + END rw0_wmask_in[1763] + PIN rw0_wmask_in[1764] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.407 129.961 133.425 130.015 ; + END + END rw0_wmask_in[1764] + PIN rw0_wmask_in[1765] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.587 129.961 133.605 130.015 ; + END + END rw0_wmask_in[1765] + PIN rw0_wmask_in[1766] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.767 129.961 133.785 130.015 ; + END + END rw0_wmask_in[1766] + PIN rw0_wmask_in[1767] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.947 129.961 133.965 130.015 ; + END + END rw0_wmask_in[1767] + PIN rw0_wmask_in[1768] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 129.961 134.145 130.015 ; + END + END rw0_wmask_in[1768] + PIN rw0_wmask_in[1769] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.307 129.961 134.325 130.015 ; + END + END rw0_wmask_in[1769] + PIN rw0_wmask_in[1770] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.487 129.961 134.505 130.015 ; + END + END rw0_wmask_in[1770] + PIN rw0_wmask_in[1771] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.667 129.961 134.685 130.015 ; + END + END rw0_wmask_in[1771] + PIN rw0_wmask_in[1772] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.847 129.961 134.865 130.015 ; + END + END rw0_wmask_in[1772] + PIN rw0_wmask_in[1773] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.027 129.961 135.045 130.015 ; + END + END rw0_wmask_in[1773] + PIN rw0_wmask_in[1774] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.207 129.961 135.225 130.015 ; + END + END rw0_wmask_in[1774] + PIN rw0_wmask_in[1775] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.387 129.961 135.405 130.015 ; + END + END rw0_wmask_in[1775] + PIN rw0_wmask_in[1776] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 129.961 135.585 130.015 ; + END + END rw0_wmask_in[1776] + PIN rw0_wmask_in[1777] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.747 129.961 135.765 130.015 ; + END + END rw0_wmask_in[1777] + PIN rw0_wmask_in[1778] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.927 129.961 135.945 130.015 ; + END + END rw0_wmask_in[1778] + PIN rw0_wmask_in[1779] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.107 129.961 136.125 130.015 ; + END + END rw0_wmask_in[1779] + PIN rw0_wmask_in[1780] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.287 129.961 136.305 130.015 ; + END + END rw0_wmask_in[1780] + PIN rw0_wmask_in[1781] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.467 129.961 136.485 130.015 ; + END + END rw0_wmask_in[1781] + PIN rw0_wmask_in[1782] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.647 129.961 136.665 130.015 ; + END + END rw0_wmask_in[1782] + PIN rw0_wmask_in[1783] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.827 129.961 136.845 130.015 ; + END + END rw0_wmask_in[1783] + PIN rw0_wmask_in[1784] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 129.961 137.025 130.015 ; + END + END rw0_wmask_in[1784] + PIN rw0_wmask_in[1785] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.187 129.961 137.205 130.015 ; + END + END rw0_wmask_in[1785] + PIN rw0_wmask_in[1786] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.367 129.961 137.385 130.015 ; + END + END rw0_wmask_in[1786] + PIN rw0_wmask_in[1787] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.547 129.961 137.565 130.015 ; + END + END rw0_wmask_in[1787] + PIN rw0_wmask_in[1788] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.727 129.961 137.745 130.015 ; + END + END rw0_wmask_in[1788] + PIN rw0_wmask_in[1789] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.907 129.961 137.925 130.015 ; + END + END rw0_wmask_in[1789] + PIN rw0_wmask_in[1790] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.087 129.961 138.105 130.015 ; + END + END rw0_wmask_in[1790] + PIN rw0_wmask_in[1791] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.267 129.961 138.285 130.015 ; + END + END rw0_wmask_in[1791] + PIN rw0_wmask_in[1792] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 129.961 138.465 130.015 ; + END + END rw0_wmask_in[1792] + PIN rw0_wmask_in[1793] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.627 129.961 138.645 130.015 ; + END + END rw0_wmask_in[1793] + PIN rw0_wmask_in[1794] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.807 129.961 138.825 130.015 ; + END + END rw0_wmask_in[1794] + PIN rw0_wmask_in[1795] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.987 129.961 139.005 130.015 ; + END + END rw0_wmask_in[1795] + PIN rw0_wmask_in[1796] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.167 129.961 139.185 130.015 ; + END + END rw0_wmask_in[1796] + PIN rw0_wmask_in[1797] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.347 129.961 139.365 130.015 ; + END + END rw0_wmask_in[1797] + PIN rw0_wmask_in[1798] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.527 129.961 139.545 130.015 ; + END + END rw0_wmask_in[1798] + PIN rw0_wmask_in[1799] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.707 129.961 139.725 130.015 ; + END + END rw0_wmask_in[1799] + PIN rw0_wmask_in[1800] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 129.961 139.905 130.015 ; + END + END rw0_wmask_in[1800] + PIN rw0_wmask_in[1801] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.067 129.961 140.085 130.015 ; + END + END rw0_wmask_in[1801] + PIN rw0_wmask_in[1802] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.247 129.961 140.265 130.015 ; + END + END rw0_wmask_in[1802] + PIN rw0_wmask_in[1803] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.427 129.961 140.445 130.015 ; + END + END rw0_wmask_in[1803] + PIN rw0_wmask_in[1804] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.607 129.961 140.625 130.015 ; + END + END rw0_wmask_in[1804] + PIN rw0_wmask_in[1805] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.787 129.961 140.805 130.015 ; + END + END rw0_wmask_in[1805] + PIN rw0_wmask_in[1806] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.967 129.961 140.985 130.015 ; + END + END rw0_wmask_in[1806] + PIN rw0_wmask_in[1807] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.147 129.961 141.165 130.015 ; + END + END rw0_wmask_in[1807] + PIN rw0_wmask_in[1808] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 129.961 141.345 130.015 ; + END + END rw0_wmask_in[1808] + PIN rw0_wmask_in[1809] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.507 129.961 141.525 130.015 ; + END + END rw0_wmask_in[1809] + PIN rw0_wmask_in[1810] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.687 129.961 141.705 130.015 ; + END + END rw0_wmask_in[1810] + PIN rw0_wmask_in[1811] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.867 129.961 141.885 130.015 ; + END + END rw0_wmask_in[1811] + PIN rw0_wmask_in[1812] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.047 129.961 142.065 130.015 ; + END + END rw0_wmask_in[1812] + PIN rw0_wmask_in[1813] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.227 129.961 142.245 130.015 ; + END + END rw0_wmask_in[1813] + PIN rw0_wmask_in[1814] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.407 129.961 142.425 130.015 ; + END + END rw0_wmask_in[1814] + PIN rw0_wmask_in[1815] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.587 129.961 142.605 130.015 ; + END + END rw0_wmask_in[1815] + PIN rw0_wmask_in[1816] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 129.961 142.785 130.015 ; + END + END rw0_wmask_in[1816] + PIN rw0_wmask_in[1817] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.947 129.961 142.965 130.015 ; + END + END rw0_wmask_in[1817] + PIN rw0_wmask_in[1818] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.127 129.961 143.145 130.015 ; + END + END rw0_wmask_in[1818] + PIN rw0_wmask_in[1819] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.307 129.961 143.325 130.015 ; + END + END rw0_wmask_in[1819] + PIN rw0_wmask_in[1820] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.487 129.961 143.505 130.015 ; + END + END rw0_wmask_in[1820] + PIN rw0_wmask_in[1821] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.667 129.961 143.685 130.015 ; + END + END rw0_wmask_in[1821] + PIN rw0_wmask_in[1822] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.847 129.961 143.865 130.015 ; + END + END rw0_wmask_in[1822] + PIN rw0_wmask_in[1823] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.027 129.961 144.045 130.015 ; + END + END rw0_wmask_in[1823] + PIN rw0_wmask_in[1824] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 129.961 144.225 130.015 ; + END + END rw0_wmask_in[1824] + PIN rw0_wmask_in[1825] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.387 129.961 144.405 130.015 ; + END + END rw0_wmask_in[1825] + PIN rw0_wmask_in[1826] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.567 129.961 144.585 130.015 ; + END + END rw0_wmask_in[1826] + PIN rw0_wmask_in[1827] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.747 129.961 144.765 130.015 ; + END + END rw0_wmask_in[1827] + PIN rw0_wmask_in[1828] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.927 129.961 144.945 130.015 ; + END + END rw0_wmask_in[1828] + PIN rw0_wmask_in[1829] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.107 129.961 145.125 130.015 ; + END + END rw0_wmask_in[1829] + PIN rw0_wmask_in[1830] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.287 129.961 145.305 130.015 ; + END + END rw0_wmask_in[1830] + PIN rw0_wmask_in[1831] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.467 129.961 145.485 130.015 ; + END + END rw0_wmask_in[1831] + PIN rw0_wmask_in[1832] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 129.961 145.665 130.015 ; + END + END rw0_wmask_in[1832] + PIN rw0_wmask_in[1833] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.827 129.961 145.845 130.015 ; + END + END rw0_wmask_in[1833] + PIN rw0_wmask_in[1834] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.007 129.961 146.025 130.015 ; + END + END rw0_wmask_in[1834] + PIN rw0_wmask_in[1835] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.187 129.961 146.205 130.015 ; + END + END rw0_wmask_in[1835] + PIN rw0_wmask_in[1836] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.367 129.961 146.385 130.015 ; + END + END rw0_wmask_in[1836] + PIN rw0_wmask_in[1837] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.547 129.961 146.565 130.015 ; + END + END rw0_wmask_in[1837] + PIN rw0_wmask_in[1838] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.727 129.961 146.745 130.015 ; + END + END rw0_wmask_in[1838] + PIN rw0_wmask_in[1839] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.907 129.961 146.925 130.015 ; + END + END rw0_wmask_in[1839] + PIN rw0_wmask_in[1840] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 129.961 147.105 130.015 ; + END + END rw0_wmask_in[1840] + PIN rw0_wmask_in[1841] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.267 129.961 147.285 130.015 ; + END + END rw0_wmask_in[1841] + PIN rw0_wmask_in[1842] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.447 129.961 147.465 130.015 ; + END + END rw0_wmask_in[1842] + PIN rw0_wmask_in[1843] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.627 129.961 147.645 130.015 ; + END + END rw0_wmask_in[1843] + PIN rw0_wmask_in[1844] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.807 129.961 147.825 130.015 ; + END + END rw0_wmask_in[1844] + PIN rw0_wmask_in[1845] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.987 129.961 148.005 130.015 ; + END + END rw0_wmask_in[1845] + PIN rw0_wmask_in[1846] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.167 129.961 148.185 130.015 ; + END + END rw0_wmask_in[1846] + PIN rw0_wmask_in[1847] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.347 129.961 148.365 130.015 ; + END + END rw0_wmask_in[1847] + PIN rw0_wmask_in[1848] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 129.961 148.545 130.015 ; + END + END rw0_wmask_in[1848] + PIN rw0_wmask_in[1849] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.707 129.961 148.725 130.015 ; + END + END rw0_wmask_in[1849] + PIN rw0_wmask_in[1850] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.887 129.961 148.905 130.015 ; + END + END rw0_wmask_in[1850] + PIN rw0_wmask_in[1851] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.067 129.961 149.085 130.015 ; + END + END rw0_wmask_in[1851] + PIN rw0_wmask_in[1852] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.247 129.961 149.265 130.015 ; + END + END rw0_wmask_in[1852] + PIN rw0_wmask_in[1853] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.427 129.961 149.445 130.015 ; + END + END rw0_wmask_in[1853] + PIN rw0_wmask_in[1854] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.607 129.961 149.625 130.015 ; + END + END rw0_wmask_in[1854] + PIN rw0_wmask_in[1855] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.787 129.961 149.805 130.015 ; + END + END rw0_wmask_in[1855] + PIN rw0_wmask_in[1856] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 129.961 149.985 130.015 ; + END + END rw0_wmask_in[1856] + PIN rw0_wmask_in[1857] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.147 129.961 150.165 130.015 ; + END + END rw0_wmask_in[1857] + PIN rw0_wmask_in[1858] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.327 129.961 150.345 130.015 ; + END + END rw0_wmask_in[1858] + PIN rw0_wmask_in[1859] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.507 129.961 150.525 130.015 ; + END + END rw0_wmask_in[1859] + PIN rw0_wmask_in[1860] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.687 129.961 150.705 130.015 ; + END + END rw0_wmask_in[1860] + PIN rw0_wmask_in[1861] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.867 129.961 150.885 130.015 ; + END + END rw0_wmask_in[1861] + PIN rw0_wmask_in[1862] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.047 129.961 151.065 130.015 ; + END + END rw0_wmask_in[1862] + PIN rw0_wmask_in[1863] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.227 129.961 151.245 130.015 ; + END + END rw0_wmask_in[1863] + PIN rw0_wmask_in[1864] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 129.961 151.425 130.015 ; + END + END rw0_wmask_in[1864] + PIN rw0_wmask_in[1865] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.587 129.961 151.605 130.015 ; + END + END rw0_wmask_in[1865] + PIN rw0_wmask_in[1866] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.767 129.961 151.785 130.015 ; + END + END rw0_wmask_in[1866] + PIN rw0_wmask_in[1867] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.947 129.961 151.965 130.015 ; + END + END rw0_wmask_in[1867] + PIN rw0_wmask_in[1868] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.127 129.961 152.145 130.015 ; + END + END rw0_wmask_in[1868] + PIN rw0_wmask_in[1869] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.307 129.961 152.325 130.015 ; + END + END rw0_wmask_in[1869] + PIN rw0_wmask_in[1870] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.487 129.961 152.505 130.015 ; + END + END rw0_wmask_in[1870] + PIN rw0_wmask_in[1871] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.667 129.961 152.685 130.015 ; + END + END rw0_wmask_in[1871] + PIN rw0_wmask_in[1872] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 129.961 152.865 130.015 ; + END + END rw0_wmask_in[1872] + PIN rw0_wmask_in[1873] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.027 129.961 153.045 130.015 ; + END + END rw0_wmask_in[1873] + PIN rw0_wmask_in[1874] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.207 129.961 153.225 130.015 ; + END + END rw0_wmask_in[1874] + PIN rw0_wmask_in[1875] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.387 129.961 153.405 130.015 ; + END + END rw0_wmask_in[1875] + PIN rw0_wmask_in[1876] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.567 129.961 153.585 130.015 ; + END + END rw0_wmask_in[1876] + PIN rw0_wmask_in[1877] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.747 129.961 153.765 130.015 ; + END + END rw0_wmask_in[1877] + PIN rw0_wmask_in[1878] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.927 129.961 153.945 130.015 ; + END + END rw0_wmask_in[1878] + PIN rw0_wmask_in[1879] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.107 129.961 154.125 130.015 ; + END + END rw0_wmask_in[1879] + PIN rw0_wmask_in[1880] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 129.961 154.305 130.015 ; + END + END rw0_wmask_in[1880] + PIN rw0_wmask_in[1881] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.467 129.961 154.485 130.015 ; + END + END rw0_wmask_in[1881] + PIN rw0_wmask_in[1882] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.647 129.961 154.665 130.015 ; + END + END rw0_wmask_in[1882] + PIN rw0_wmask_in[1883] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.827 129.961 154.845 130.015 ; + END + END rw0_wmask_in[1883] + PIN rw0_wmask_in[1884] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.007 129.961 155.025 130.015 ; + END + END rw0_wmask_in[1884] + PIN rw0_wmask_in[1885] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.187 129.961 155.205 130.015 ; + END + END rw0_wmask_in[1885] + PIN rw0_wmask_in[1886] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.367 129.961 155.385 130.015 ; + END + END rw0_wmask_in[1886] + PIN rw0_wmask_in[1887] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.547 129.961 155.565 130.015 ; + END + END rw0_wmask_in[1887] + PIN rw0_wmask_in[1888] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 129.961 155.745 130.015 ; + END + END rw0_wmask_in[1888] + PIN rw0_wmask_in[1889] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.907 129.961 155.925 130.015 ; + END + END rw0_wmask_in[1889] + PIN rw0_wmask_in[1890] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.087 129.961 156.105 130.015 ; + END + END rw0_wmask_in[1890] + PIN rw0_wmask_in[1891] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.267 129.961 156.285 130.015 ; + END + END rw0_wmask_in[1891] + PIN rw0_wmask_in[1892] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.447 129.961 156.465 130.015 ; + END + END rw0_wmask_in[1892] + PIN rw0_wmask_in[1893] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.627 129.961 156.645 130.015 ; + END + END rw0_wmask_in[1893] + PIN rw0_wmask_in[1894] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.807 129.961 156.825 130.015 ; + END + END rw0_wmask_in[1894] + PIN rw0_wmask_in[1895] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.987 129.961 157.005 130.015 ; + END + END rw0_wmask_in[1895] + PIN rw0_wmask_in[1896] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 129.961 157.185 130.015 ; + END + END rw0_wmask_in[1896] + PIN rw0_wmask_in[1897] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.347 129.961 157.365 130.015 ; + END + END rw0_wmask_in[1897] + PIN rw0_wmask_in[1898] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.527 129.961 157.545 130.015 ; + END + END rw0_wmask_in[1898] + PIN rw0_wmask_in[1899] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.707 129.961 157.725 130.015 ; + END + END rw0_wmask_in[1899] + PIN rw0_wmask_in[1900] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.887 129.961 157.905 130.015 ; + END + END rw0_wmask_in[1900] + PIN rw0_wmask_in[1901] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.067 129.961 158.085 130.015 ; + END + END rw0_wmask_in[1901] + PIN rw0_wmask_in[1902] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.247 129.961 158.265 130.015 ; + END + END rw0_wmask_in[1902] + PIN rw0_wmask_in[1903] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.427 129.961 158.445 130.015 ; + END + END rw0_wmask_in[1903] + PIN rw0_wmask_in[1904] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 129.961 158.625 130.015 ; + END + END rw0_wmask_in[1904] + PIN rw0_wmask_in[1905] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.787 129.961 158.805 130.015 ; + END + END rw0_wmask_in[1905] + PIN rw0_wmask_in[1906] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.967 129.961 158.985 130.015 ; + END + END rw0_wmask_in[1906] + PIN rw0_wmask_in[1907] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.147 129.961 159.165 130.015 ; + END + END rw0_wmask_in[1907] + PIN rw0_wmask_in[1908] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.327 129.961 159.345 130.015 ; + END + END rw0_wmask_in[1908] + PIN rw0_wmask_in[1909] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.507 129.961 159.525 130.015 ; + END + END rw0_wmask_in[1909] + PIN rw0_wmask_in[1910] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.687 129.961 159.705 130.015 ; + END + END rw0_wmask_in[1910] + PIN rw0_wmask_in[1911] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.867 129.961 159.885 130.015 ; + END + END rw0_wmask_in[1911] + PIN rw0_wmask_in[1912] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 129.961 160.065 130.015 ; + END + END rw0_wmask_in[1912] + PIN rw0_wmask_in[1913] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.227 129.961 160.245 130.015 ; + END + END rw0_wmask_in[1913] + PIN rw0_wmask_in[1914] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.407 129.961 160.425 130.015 ; + END + END rw0_wmask_in[1914] + PIN rw0_wmask_in[1915] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.587 129.961 160.605 130.015 ; + END + END rw0_wmask_in[1915] + PIN rw0_wmask_in[1916] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.767 129.961 160.785 130.015 ; + END + END rw0_wmask_in[1916] + PIN rw0_wmask_in[1917] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.947 129.961 160.965 130.015 ; + END + END rw0_wmask_in[1917] + PIN rw0_wmask_in[1918] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.127 129.961 161.145 130.015 ; + END + END rw0_wmask_in[1918] + PIN rw0_wmask_in[1919] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.307 129.961 161.325 130.015 ; + END + END rw0_wmask_in[1919] + PIN rw0_wmask_in[1920] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 129.961 161.505 130.015 ; + END + END rw0_wmask_in[1920] + PIN rw0_wmask_in[1921] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.667 129.961 161.685 130.015 ; + END + END rw0_wmask_in[1921] + PIN rw0_wmask_in[1922] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.847 129.961 161.865 130.015 ; + END + END rw0_wmask_in[1922] + PIN rw0_wmask_in[1923] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.027 129.961 162.045 130.015 ; + END + END rw0_wmask_in[1923] + PIN rw0_wmask_in[1924] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.207 129.961 162.225 130.015 ; + END + END rw0_wmask_in[1924] + PIN rw0_wmask_in[1925] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.387 129.961 162.405 130.015 ; + END + END rw0_wmask_in[1925] + PIN rw0_wmask_in[1926] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.567 129.961 162.585 130.015 ; + END + END rw0_wmask_in[1926] + PIN rw0_wmask_in[1927] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.747 129.961 162.765 130.015 ; + END + END rw0_wmask_in[1927] + PIN rw0_wmask_in[1928] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 129.961 162.945 130.015 ; + END + END rw0_wmask_in[1928] + PIN rw0_wmask_in[1929] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.107 129.961 163.125 130.015 ; + END + END rw0_wmask_in[1929] + PIN rw0_wmask_in[1930] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.287 129.961 163.305 130.015 ; + END + END rw0_wmask_in[1930] + PIN rw0_wmask_in[1931] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.467 129.961 163.485 130.015 ; + END + END rw0_wmask_in[1931] + PIN rw0_wmask_in[1932] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.647 129.961 163.665 130.015 ; + END + END rw0_wmask_in[1932] + PIN rw0_wmask_in[1933] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.827 129.961 163.845 130.015 ; + END + END rw0_wmask_in[1933] + PIN rw0_wmask_in[1934] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.007 129.961 164.025 130.015 ; + END + END rw0_wmask_in[1934] + PIN rw0_wmask_in[1935] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.187 129.961 164.205 130.015 ; + END + END rw0_wmask_in[1935] + PIN rw0_wmask_in[1936] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 129.961 164.385 130.015 ; + END + END rw0_wmask_in[1936] + PIN rw0_wmask_in[1937] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.547 129.961 164.565 130.015 ; + END + END rw0_wmask_in[1937] + PIN rw0_wmask_in[1938] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.727 129.961 164.745 130.015 ; + END + END rw0_wmask_in[1938] + PIN rw0_wmask_in[1939] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.907 129.961 164.925 130.015 ; + END + END rw0_wmask_in[1939] + PIN rw0_wmask_in[1940] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.087 129.961 165.105 130.015 ; + END + END rw0_wmask_in[1940] + PIN rw0_wmask_in[1941] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.267 129.961 165.285 130.015 ; + END + END rw0_wmask_in[1941] + PIN rw0_wmask_in[1942] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.447 129.961 165.465 130.015 ; + END + END rw0_wmask_in[1942] + PIN rw0_wmask_in[1943] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.627 129.961 165.645 130.015 ; + END + END rw0_wmask_in[1943] + PIN rw0_wmask_in[1944] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 129.961 165.825 130.015 ; + END + END rw0_wmask_in[1944] + PIN rw0_wmask_in[1945] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.987 129.961 166.005 130.015 ; + END + END rw0_wmask_in[1945] + PIN rw0_wmask_in[1946] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.167 129.961 166.185 130.015 ; + END + END rw0_wmask_in[1946] + PIN rw0_wmask_in[1947] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.347 129.961 166.365 130.015 ; + END + END rw0_wmask_in[1947] + PIN rw0_wmask_in[1948] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.527 129.961 166.545 130.015 ; + END + END rw0_wmask_in[1948] + PIN rw0_wmask_in[1949] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.707 129.961 166.725 130.015 ; + END + END rw0_wmask_in[1949] + PIN rw0_wmask_in[1950] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.887 129.961 166.905 130.015 ; + END + END rw0_wmask_in[1950] + PIN rw0_wmask_in[1951] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.067 129.961 167.085 130.015 ; + END + END rw0_wmask_in[1951] + PIN rw0_wmask_in[1952] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 129.961 167.265 130.015 ; + END + END rw0_wmask_in[1952] + PIN rw0_wmask_in[1953] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.427 129.961 167.445 130.015 ; + END + END rw0_wmask_in[1953] + PIN rw0_wmask_in[1954] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.607 129.961 167.625 130.015 ; + END + END rw0_wmask_in[1954] + PIN rw0_wmask_in[1955] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.787 129.961 167.805 130.015 ; + END + END rw0_wmask_in[1955] + PIN rw0_wmask_in[1956] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.967 129.961 167.985 130.015 ; + END + END rw0_wmask_in[1956] + PIN rw0_wmask_in[1957] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.147 129.961 168.165 130.015 ; + END + END rw0_wmask_in[1957] + PIN rw0_wmask_in[1958] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.327 129.961 168.345 130.015 ; + END + END rw0_wmask_in[1958] + PIN rw0_wmask_in[1959] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.507 129.961 168.525 130.015 ; + END + END rw0_wmask_in[1959] + PIN rw0_wmask_in[1960] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 129.961 168.705 130.015 ; + END + END rw0_wmask_in[1960] + PIN rw0_wmask_in[1961] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.867 129.961 168.885 130.015 ; + END + END rw0_wmask_in[1961] + PIN rw0_wmask_in[1962] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.047 129.961 169.065 130.015 ; + END + END rw0_wmask_in[1962] + PIN rw0_wmask_in[1963] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.227 129.961 169.245 130.015 ; + END + END rw0_wmask_in[1963] + PIN rw0_wmask_in[1964] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.407 129.961 169.425 130.015 ; + END + END rw0_wmask_in[1964] + PIN rw0_wmask_in[1965] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.587 129.961 169.605 130.015 ; + END + END rw0_wmask_in[1965] + PIN rw0_wmask_in[1966] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.767 129.961 169.785 130.015 ; + END + END rw0_wmask_in[1966] + PIN rw0_wmask_in[1967] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.947 129.961 169.965 130.015 ; + END + END rw0_wmask_in[1967] + PIN rw0_wmask_in[1968] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 129.961 170.145 130.015 ; + END + END rw0_wmask_in[1968] + PIN rw0_wmask_in[1969] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.307 129.961 170.325 130.015 ; + END + END rw0_wmask_in[1969] + PIN rw0_wmask_in[1970] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.487 129.961 170.505 130.015 ; + END + END rw0_wmask_in[1970] + PIN rw0_wmask_in[1971] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.667 129.961 170.685 130.015 ; + END + END rw0_wmask_in[1971] + PIN rw0_wmask_in[1972] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.847 129.961 170.865 130.015 ; + END + END rw0_wmask_in[1972] + PIN rw0_wmask_in[1973] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.027 129.961 171.045 130.015 ; + END + END rw0_wmask_in[1973] + PIN rw0_wmask_in[1974] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.207 129.961 171.225 130.015 ; + END + END rw0_wmask_in[1974] + PIN rw0_wmask_in[1975] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.387 129.961 171.405 130.015 ; + END + END rw0_wmask_in[1975] + PIN rw0_wmask_in[1976] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 129.961 171.585 130.015 ; + END + END rw0_wmask_in[1976] + PIN rw0_wmask_in[1977] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.747 129.961 171.765 130.015 ; + END + END rw0_wmask_in[1977] + PIN rw0_wmask_in[1978] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.927 129.961 171.945 130.015 ; + END + END rw0_wmask_in[1978] + PIN rw0_wmask_in[1979] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.107 129.961 172.125 130.015 ; + END + END rw0_wmask_in[1979] + PIN rw0_wmask_in[1980] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.287 129.961 172.305 130.015 ; + END + END rw0_wmask_in[1980] + PIN rw0_wmask_in[1981] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.467 129.961 172.485 130.015 ; + END + END rw0_wmask_in[1981] + PIN rw0_wmask_in[1982] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.647 129.961 172.665 130.015 ; + END + END rw0_wmask_in[1982] + PIN rw0_wmask_in[1983] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.827 129.961 172.845 130.015 ; + END + END rw0_wmask_in[1983] + PIN rw0_wmask_in[1984] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.007 129.961 173.025 130.015 ; + END + END rw0_wmask_in[1984] + PIN rw0_wmask_in[1985] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.187 129.961 173.205 130.015 ; + END + END rw0_wmask_in[1985] + PIN rw0_wmask_in[1986] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.367 129.961 173.385 130.015 ; + END + END rw0_wmask_in[1986] + PIN rw0_wmask_in[1987] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.547 129.961 173.565 130.015 ; + END + END rw0_wmask_in[1987] + PIN rw0_wmask_in[1988] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.727 129.961 173.745 130.015 ; + END + END rw0_wmask_in[1988] + PIN rw0_wmask_in[1989] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.907 129.961 173.925 130.015 ; + END + END rw0_wmask_in[1989] + PIN rw0_wmask_in[1990] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.087 129.961 174.105 130.015 ; + END + END rw0_wmask_in[1990] + PIN rw0_wmask_in[1991] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.267 129.961 174.285 130.015 ; + END + END rw0_wmask_in[1991] + PIN rw0_wmask_in[1992] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.447 129.961 174.465 130.015 ; + END + END rw0_wmask_in[1992] + PIN rw0_wmask_in[1993] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.627 129.961 174.645 130.015 ; + END + END rw0_wmask_in[1993] + PIN rw0_wmask_in[1994] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.807 129.961 174.825 130.015 ; + END + END rw0_wmask_in[1994] + PIN rw0_wmask_in[1995] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.987 129.961 175.005 130.015 ; + END + END rw0_wmask_in[1995] + PIN rw0_wmask_in[1996] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.167 129.961 175.185 130.015 ; + END + END rw0_wmask_in[1996] + PIN rw0_wmask_in[1997] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.347 129.961 175.365 130.015 ; + END + END rw0_wmask_in[1997] + PIN rw0_wmask_in[1998] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.527 129.961 175.545 130.015 ; + END + END rw0_wmask_in[1998] + PIN rw0_wmask_in[1999] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.707 129.961 175.725 130.015 ; + END + END rw0_wmask_in[1999] + PIN rw0_wmask_in[2000] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.887 129.961 175.905 130.015 ; + END + END rw0_wmask_in[2000] + PIN rw0_wmask_in[2001] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.067 129.961 176.085 130.015 ; + END + END rw0_wmask_in[2001] + PIN rw0_wmask_in[2002] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.247 129.961 176.265 130.015 ; + END + END rw0_wmask_in[2002] + PIN rw0_wmask_in[2003] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.427 129.961 176.445 130.015 ; + END + END rw0_wmask_in[2003] + PIN rw0_wmask_in[2004] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.607 129.961 176.625 130.015 ; + END + END rw0_wmask_in[2004] + PIN rw0_wmask_in[2005] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.787 129.961 176.805 130.015 ; + END + END rw0_wmask_in[2005] + PIN rw0_wmask_in[2006] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.967 129.961 176.985 130.015 ; + END + END rw0_wmask_in[2006] + PIN rw0_wmask_in[2007] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.147 129.961 177.165 130.015 ; + END + END rw0_wmask_in[2007] + PIN rw0_wmask_in[2008] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.327 129.961 177.345 130.015 ; + END + END rw0_wmask_in[2008] + PIN rw0_wmask_in[2009] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.507 129.961 177.525 130.015 ; + END + END rw0_wmask_in[2009] + PIN rw0_wmask_in[2010] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.687 129.961 177.705 130.015 ; + END + END rw0_wmask_in[2010] + PIN rw0_wmask_in[2011] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.867 129.961 177.885 130.015 ; + END + END rw0_wmask_in[2011] + PIN rw0_wmask_in[2012] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.047 129.961 178.065 130.015 ; + END + END rw0_wmask_in[2012] + PIN rw0_wmask_in[2013] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.227 129.961 178.245 130.015 ; + END + END rw0_wmask_in[2013] + PIN rw0_wmask_in[2014] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.407 129.961 178.425 130.015 ; + END + END rw0_wmask_in[2014] + PIN rw0_wmask_in[2015] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.587 129.961 178.605 130.015 ; + END + END rw0_wmask_in[2015] + PIN rw0_wmask_in[2016] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.767 129.961 178.785 130.015 ; + END + END rw0_wmask_in[2016] + PIN rw0_wmask_in[2017] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.947 129.961 178.965 130.015 ; + END + END rw0_wmask_in[2017] + PIN rw0_wmask_in[2018] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.127 129.961 179.145 130.015 ; + END + END rw0_wmask_in[2018] + PIN rw0_wmask_in[2019] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.307 129.961 179.325 130.015 ; + END + END rw0_wmask_in[2019] + PIN rw0_wmask_in[2020] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.487 129.961 179.505 130.015 ; + END + END rw0_wmask_in[2020] + PIN rw0_wmask_in[2021] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.667 129.961 179.685 130.015 ; + END + END rw0_wmask_in[2021] + PIN rw0_wmask_in[2022] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.847 129.961 179.865 130.015 ; + END + END rw0_wmask_in[2022] + PIN rw0_wmask_in[2023] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.027 129.961 180.045 130.015 ; + END + END rw0_wmask_in[2023] + PIN rw0_wmask_in[2024] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.207 129.961 180.225 130.015 ; + END + END rw0_wmask_in[2024] + PIN rw0_wmask_in[2025] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.387 129.961 180.405 130.015 ; + END + END rw0_wmask_in[2025] + PIN rw0_wmask_in[2026] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.567 129.961 180.585 130.015 ; + END + END rw0_wmask_in[2026] + PIN rw0_wmask_in[2027] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.747 129.961 180.765 130.015 ; + END + END rw0_wmask_in[2027] + PIN rw0_wmask_in[2028] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.927 129.961 180.945 130.015 ; + END + END rw0_wmask_in[2028] + PIN rw0_wmask_in[2029] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.107 129.961 181.125 130.015 ; + END + END rw0_wmask_in[2029] + PIN rw0_wmask_in[2030] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.287 129.961 181.305 130.015 ; + END + END rw0_wmask_in[2030] + PIN rw0_wmask_in[2031] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.467 129.961 181.485 130.015 ; + END + END rw0_wmask_in[2031] + PIN rw0_wmask_in[2032] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.647 129.961 181.665 130.015 ; + END + END rw0_wmask_in[2032] + PIN rw0_wmask_in[2033] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.827 129.961 181.845 130.015 ; + END + END rw0_wmask_in[2033] + PIN rw0_wmask_in[2034] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.007 129.961 182.025 130.015 ; + END + END rw0_wmask_in[2034] + PIN rw0_wmask_in[2035] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.187 129.961 182.205 130.015 ; + END + END rw0_wmask_in[2035] + PIN rw0_wmask_in[2036] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.367 129.961 182.385 130.015 ; + END + END rw0_wmask_in[2036] + PIN rw0_wmask_in[2037] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.547 129.961 182.565 130.015 ; + END + END rw0_wmask_in[2037] + PIN rw0_wmask_in[2038] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.727 129.961 182.745 130.015 ; + END + END rw0_wmask_in[2038] + PIN rw0_wmask_in[2039] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.907 129.961 182.925 130.015 ; + END + END rw0_wmask_in[2039] + PIN rw0_wmask_in[2040] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.087 129.961 183.105 130.015 ; + END + END rw0_wmask_in[2040] + PIN rw0_wmask_in[2041] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.267 129.961 183.285 130.015 ; + END + END rw0_wmask_in[2041] + PIN rw0_wmask_in[2042] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.447 129.961 183.465 130.015 ; + END + END rw0_wmask_in[2042] + PIN rw0_wmask_in[2043] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.627 129.961 183.645 130.015 ; + END + END rw0_wmask_in[2043] + PIN rw0_wmask_in[2044] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.807 129.961 183.825 130.015 ; + END + END rw0_wmask_in[2044] + PIN rw0_wmask_in[2045] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.987 129.961 184.005 130.015 ; + END + END rw0_wmask_in[2045] + PIN rw0_wmask_in[2046] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.167 129.961 184.185 130.015 ; + END + END rw0_wmask_in[2046] + PIN rw0_wmask_in[2047] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.347 129.961 184.365 130.015 ; + END + END rw0_wmask_in[2047] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.428 0.072 49.452 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.524 0.072 49.548 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.620 0.072 49.644 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.716 0.072 49.740 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.812 0.072 49.836 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.908 0.072 49.932 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.004 0.072 50.028 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.100 0.072 50.124 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.196 0.072 50.220 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.292 0.072 50.316 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.388 0.072 50.412 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.484 0.072 50.508 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.580 0.072 50.604 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.676 0.072 50.700 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.772 0.072 50.796 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.868 0.072 50.892 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.964 0.072 50.988 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.060 0.072 51.084 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.156 0.072 51.180 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.252 0.072 51.276 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.348 0.072 51.372 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.444 0.072 51.468 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.540 0.072 51.564 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.636 0.072 51.660 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.732 0.072 51.756 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.828 0.072 51.852 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.924 0.072 51.948 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.020 0.072 52.044 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.116 0.072 52.140 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.212 0.072 52.236 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.308 0.072 52.332 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.404 0.072 52.428 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.500 0.072 52.524 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.596 0.072 52.620 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.692 0.072 52.716 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.788 0.072 52.812 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.884 0.072 52.908 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.980 0.072 53.004 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.076 0.072 53.100 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.172 0.072 53.196 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.268 0.072 53.292 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.364 0.072 53.388 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.460 0.072 53.484 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.556 0.072 53.580 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.652 0.072 53.676 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.748 0.072 53.772 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.844 0.072 53.868 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.940 0.072 53.964 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.036 0.072 54.060 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.132 0.072 54.156 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.228 0.072 54.252 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.324 0.072 54.348 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.420 0.072 54.444 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.516 0.072 54.540 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.612 0.072 54.636 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.708 0.072 54.732 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.804 0.072 54.828 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.900 0.072 54.924 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.996 0.072 55.020 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.092 0.072 55.116 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.188 0.072 55.212 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.284 0.072 55.308 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.380 0.072 55.404 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.476 0.072 55.500 ; + END + END rw0_wd_in[63] + PIN rw0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.572 0.072 55.596 ; + END + END rw0_wd_in[64] + PIN rw0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.668 0.072 55.692 ; + END + END rw0_wd_in[65] + PIN rw0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.764 0.072 55.788 ; + END + END rw0_wd_in[66] + PIN rw0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.860 0.072 55.884 ; + END + END rw0_wd_in[67] + PIN rw0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.956 0.072 55.980 ; + END + END rw0_wd_in[68] + PIN rw0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.052 0.072 56.076 ; + END + END rw0_wd_in[69] + PIN rw0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.148 0.072 56.172 ; + END + END rw0_wd_in[70] + PIN rw0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.244 0.072 56.268 ; + END + END rw0_wd_in[71] + PIN rw0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.340 0.072 56.364 ; + END + END rw0_wd_in[72] + PIN rw0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.436 0.072 56.460 ; + END + END rw0_wd_in[73] + PIN rw0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.532 0.072 56.556 ; + END + END rw0_wd_in[74] + PIN rw0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.628 0.072 56.652 ; + END + END rw0_wd_in[75] + PIN rw0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.724 0.072 56.748 ; + END + END rw0_wd_in[76] + PIN rw0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.820 0.072 56.844 ; + END + END rw0_wd_in[77] + PIN rw0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.916 0.072 56.940 ; + END + END rw0_wd_in[78] + PIN rw0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.012 0.072 57.036 ; + END + END rw0_wd_in[79] + PIN rw0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.108 0.072 57.132 ; + END + END rw0_wd_in[80] + PIN rw0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.204 0.072 57.228 ; + END + END rw0_wd_in[81] + PIN rw0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.300 0.072 57.324 ; + END + END rw0_wd_in[82] + PIN rw0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.396 0.072 57.420 ; + END + END rw0_wd_in[83] + PIN rw0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.492 0.072 57.516 ; + END + END rw0_wd_in[84] + PIN rw0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.588 0.072 57.612 ; + END + END rw0_wd_in[85] + PIN rw0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.684 0.072 57.708 ; + END + END rw0_wd_in[86] + PIN rw0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.780 0.072 57.804 ; + END + END rw0_wd_in[87] + PIN rw0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.876 0.072 57.900 ; + END + END rw0_wd_in[88] + PIN rw0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.972 0.072 57.996 ; + END + END rw0_wd_in[89] + PIN rw0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.068 0.072 58.092 ; + END + END rw0_wd_in[90] + PIN rw0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.164 0.072 58.188 ; + END + END rw0_wd_in[91] + PIN rw0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.260 0.072 58.284 ; + END + END rw0_wd_in[92] + PIN rw0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.356 0.072 58.380 ; + END + END rw0_wd_in[93] + PIN rw0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.452 0.072 58.476 ; + END + END rw0_wd_in[94] + PIN rw0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.548 0.072 58.572 ; + END + END rw0_wd_in[95] + PIN rw0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.644 0.072 58.668 ; + END + END rw0_wd_in[96] + PIN rw0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.740 0.072 58.764 ; + END + END rw0_wd_in[97] + PIN rw0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.836 0.072 58.860 ; + END + END rw0_wd_in[98] + PIN rw0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.932 0.072 58.956 ; + END + END rw0_wd_in[99] + PIN rw0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.028 0.072 59.052 ; + END + END rw0_wd_in[100] + PIN rw0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.124 0.072 59.148 ; + END + END rw0_wd_in[101] + PIN rw0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.220 0.072 59.244 ; + END + END rw0_wd_in[102] + PIN rw0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.316 0.072 59.340 ; + END + END rw0_wd_in[103] + PIN rw0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.412 0.072 59.436 ; + END + END rw0_wd_in[104] + PIN rw0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.508 0.072 59.532 ; + END + END rw0_wd_in[105] + PIN rw0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.604 0.072 59.628 ; + END + END rw0_wd_in[106] + PIN rw0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.700 0.072 59.724 ; + END + END rw0_wd_in[107] + PIN rw0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.796 0.072 59.820 ; + END + END rw0_wd_in[108] + PIN rw0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.892 0.072 59.916 ; + END + END rw0_wd_in[109] + PIN rw0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.988 0.072 60.012 ; + END + END rw0_wd_in[110] + PIN rw0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.084 0.072 60.108 ; + END + END rw0_wd_in[111] + PIN rw0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.180 0.072 60.204 ; + END + END rw0_wd_in[112] + PIN rw0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.276 0.072 60.300 ; + END + END rw0_wd_in[113] + PIN rw0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.372 0.072 60.396 ; + END + END rw0_wd_in[114] + PIN rw0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.468 0.072 60.492 ; + END + END rw0_wd_in[115] + PIN rw0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.564 0.072 60.588 ; + END + END rw0_wd_in[116] + PIN rw0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.660 0.072 60.684 ; + END + END rw0_wd_in[117] + PIN rw0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.756 0.072 60.780 ; + END + END rw0_wd_in[118] + PIN rw0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.852 0.072 60.876 ; + END + END rw0_wd_in[119] + PIN rw0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.948 0.072 60.972 ; + END + END rw0_wd_in[120] + PIN rw0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.044 0.072 61.068 ; + END + END rw0_wd_in[121] + PIN rw0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.140 0.072 61.164 ; + END + END rw0_wd_in[122] + PIN rw0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.236 0.072 61.260 ; + END + END rw0_wd_in[123] + PIN rw0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.332 0.072 61.356 ; + END + END rw0_wd_in[124] + PIN rw0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.428 0.072 61.452 ; + END + END rw0_wd_in[125] + PIN rw0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.524 0.072 61.548 ; + END + END rw0_wd_in[126] + PIN rw0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.620 0.072 61.644 ; + END + END rw0_wd_in[127] + PIN rw0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.716 0.072 61.740 ; + END + END rw0_wd_in[128] + PIN rw0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.812 0.072 61.836 ; + END + END rw0_wd_in[129] + PIN rw0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.908 0.072 61.932 ; + END + END rw0_wd_in[130] + PIN rw0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.004 0.072 62.028 ; + END + END rw0_wd_in[131] + PIN rw0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.100 0.072 62.124 ; + END + END rw0_wd_in[132] + PIN rw0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.196 0.072 62.220 ; + END + END rw0_wd_in[133] + PIN rw0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.292 0.072 62.316 ; + END + END rw0_wd_in[134] + PIN rw0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.388 0.072 62.412 ; + END + END rw0_wd_in[135] + PIN rw0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.484 0.072 62.508 ; + END + END rw0_wd_in[136] + PIN rw0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.580 0.072 62.604 ; + END + END rw0_wd_in[137] + PIN rw0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.676 0.072 62.700 ; + END + END rw0_wd_in[138] + PIN rw0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.772 0.072 62.796 ; + END + END rw0_wd_in[139] + PIN rw0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.868 0.072 62.892 ; + END + END rw0_wd_in[140] + PIN rw0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.964 0.072 62.988 ; + END + END rw0_wd_in[141] + PIN rw0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.060 0.072 63.084 ; + END + END rw0_wd_in[142] + PIN rw0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.156 0.072 63.180 ; + END + END rw0_wd_in[143] + PIN rw0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.252 0.072 63.276 ; + END + END rw0_wd_in[144] + PIN rw0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.348 0.072 63.372 ; + END + END rw0_wd_in[145] + PIN rw0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.444 0.072 63.468 ; + END + END rw0_wd_in[146] + PIN rw0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.540 0.072 63.564 ; + END + END rw0_wd_in[147] + PIN rw0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.636 0.072 63.660 ; + END + END rw0_wd_in[148] + PIN rw0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.732 0.072 63.756 ; + END + END rw0_wd_in[149] + PIN rw0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.828 0.072 63.852 ; + END + END rw0_wd_in[150] + PIN rw0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.924 0.072 63.948 ; + END + END rw0_wd_in[151] + PIN rw0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.020 0.072 64.044 ; + END + END rw0_wd_in[152] + PIN rw0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.116 0.072 64.140 ; + END + END rw0_wd_in[153] + PIN rw0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.212 0.072 64.236 ; + END + END rw0_wd_in[154] + PIN rw0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.308 0.072 64.332 ; + END + END rw0_wd_in[155] + PIN rw0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.404 0.072 64.428 ; + END + END rw0_wd_in[156] + PIN rw0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.500 0.072 64.524 ; + END + END rw0_wd_in[157] + PIN rw0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.596 0.072 64.620 ; + END + END rw0_wd_in[158] + PIN rw0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.692 0.072 64.716 ; + END + END rw0_wd_in[159] + PIN rw0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.788 0.072 64.812 ; + END + END rw0_wd_in[160] + PIN rw0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.884 0.072 64.908 ; + END + END rw0_wd_in[161] + PIN rw0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.980 0.072 65.004 ; + END + END rw0_wd_in[162] + PIN rw0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.076 0.072 65.100 ; + END + END rw0_wd_in[163] + PIN rw0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.172 0.072 65.196 ; + END + END rw0_wd_in[164] + PIN rw0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.268 0.072 65.292 ; + END + END rw0_wd_in[165] + PIN rw0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.364 0.072 65.388 ; + END + END rw0_wd_in[166] + PIN rw0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.460 0.072 65.484 ; + END + END rw0_wd_in[167] + PIN rw0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.556 0.072 65.580 ; + END + END rw0_wd_in[168] + PIN rw0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.652 0.072 65.676 ; + END + END rw0_wd_in[169] + PIN rw0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.748 0.072 65.772 ; + END + END rw0_wd_in[170] + PIN rw0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.844 0.072 65.868 ; + END + END rw0_wd_in[171] + PIN rw0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.940 0.072 65.964 ; + END + END rw0_wd_in[172] + PIN rw0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.036 0.072 66.060 ; + END + END rw0_wd_in[173] + PIN rw0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.132 0.072 66.156 ; + END + END rw0_wd_in[174] + PIN rw0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.228 0.072 66.252 ; + END + END rw0_wd_in[175] + PIN rw0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.324 0.072 66.348 ; + END + END rw0_wd_in[176] + PIN rw0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.420 0.072 66.444 ; + END + END rw0_wd_in[177] + PIN rw0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.516 0.072 66.540 ; + END + END rw0_wd_in[178] + PIN rw0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.612 0.072 66.636 ; + END + END rw0_wd_in[179] + PIN rw0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.708 0.072 66.732 ; + END + END rw0_wd_in[180] + PIN rw0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.804 0.072 66.828 ; + END + END rw0_wd_in[181] + PIN rw0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.900 0.072 66.924 ; + END + END rw0_wd_in[182] + PIN rw0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.996 0.072 67.020 ; + END + END rw0_wd_in[183] + PIN rw0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.092 0.072 67.116 ; + END + END rw0_wd_in[184] + PIN rw0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.188 0.072 67.212 ; + END + END rw0_wd_in[185] + PIN rw0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.284 0.072 67.308 ; + END + END rw0_wd_in[186] + PIN rw0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.380 0.072 67.404 ; + END + END rw0_wd_in[187] + PIN rw0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.476 0.072 67.500 ; + END + END rw0_wd_in[188] + PIN rw0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.572 0.072 67.596 ; + END + END rw0_wd_in[189] + PIN rw0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.668 0.072 67.692 ; + END + END rw0_wd_in[190] + PIN rw0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.764 0.072 67.788 ; + END + END rw0_wd_in[191] + PIN rw0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.860 0.072 67.884 ; + END + END rw0_wd_in[192] + PIN rw0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.956 0.072 67.980 ; + END + END rw0_wd_in[193] + PIN rw0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.052 0.072 68.076 ; + END + END rw0_wd_in[194] + PIN rw0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.148 0.072 68.172 ; + END + END rw0_wd_in[195] + PIN rw0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.244 0.072 68.268 ; + END + END rw0_wd_in[196] + PIN rw0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.340 0.072 68.364 ; + END + END rw0_wd_in[197] + PIN rw0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.436 0.072 68.460 ; + END + END rw0_wd_in[198] + PIN rw0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.532 0.072 68.556 ; + END + END rw0_wd_in[199] + PIN rw0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.628 0.072 68.652 ; + END + END rw0_wd_in[200] + PIN rw0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.724 0.072 68.748 ; + END + END rw0_wd_in[201] + PIN rw0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.820 0.072 68.844 ; + END + END rw0_wd_in[202] + PIN rw0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.916 0.072 68.940 ; + END + END rw0_wd_in[203] + PIN rw0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.012 0.072 69.036 ; + END + END rw0_wd_in[204] + PIN rw0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.108 0.072 69.132 ; + END + END rw0_wd_in[205] + PIN rw0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.204 0.072 69.228 ; + END + END rw0_wd_in[206] + PIN rw0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.300 0.072 69.324 ; + END + END rw0_wd_in[207] + PIN rw0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.396 0.072 69.420 ; + END + END rw0_wd_in[208] + PIN rw0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.492 0.072 69.516 ; + END + END rw0_wd_in[209] + PIN rw0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.588 0.072 69.612 ; + END + END rw0_wd_in[210] + PIN rw0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.684 0.072 69.708 ; + END + END rw0_wd_in[211] + PIN rw0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.780 0.072 69.804 ; + END + END rw0_wd_in[212] + PIN rw0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.876 0.072 69.900 ; + END + END rw0_wd_in[213] + PIN rw0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.972 0.072 69.996 ; + END + END rw0_wd_in[214] + PIN rw0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.068 0.072 70.092 ; + END + END rw0_wd_in[215] + PIN rw0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.164 0.072 70.188 ; + END + END rw0_wd_in[216] + PIN rw0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.260 0.072 70.284 ; + END + END rw0_wd_in[217] + PIN rw0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.356 0.072 70.380 ; + END + END rw0_wd_in[218] + PIN rw0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.452 0.072 70.476 ; + END + END rw0_wd_in[219] + PIN rw0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.548 0.072 70.572 ; + END + END rw0_wd_in[220] + PIN rw0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.644 0.072 70.668 ; + END + END rw0_wd_in[221] + PIN rw0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.740 0.072 70.764 ; + END + END rw0_wd_in[222] + PIN rw0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.836 0.072 70.860 ; + END + END rw0_wd_in[223] + PIN rw0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.932 0.072 70.956 ; + END + END rw0_wd_in[224] + PIN rw0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.028 0.072 71.052 ; + END + END rw0_wd_in[225] + PIN rw0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.124 0.072 71.148 ; + END + END rw0_wd_in[226] + PIN rw0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.220 0.072 71.244 ; + END + END rw0_wd_in[227] + PIN rw0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.316 0.072 71.340 ; + END + END rw0_wd_in[228] + PIN rw0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.412 0.072 71.436 ; + END + END rw0_wd_in[229] + PIN rw0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.508 0.072 71.532 ; + END + END rw0_wd_in[230] + PIN rw0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.604 0.072 71.628 ; + END + END rw0_wd_in[231] + PIN rw0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.700 0.072 71.724 ; + END + END rw0_wd_in[232] + PIN rw0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.796 0.072 71.820 ; + END + END rw0_wd_in[233] + PIN rw0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.892 0.072 71.916 ; + END + END rw0_wd_in[234] + PIN rw0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.988 0.072 72.012 ; + END + END rw0_wd_in[235] + PIN rw0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.084 0.072 72.108 ; + END + END rw0_wd_in[236] + PIN rw0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.180 0.072 72.204 ; + END + END rw0_wd_in[237] + PIN rw0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.276 0.072 72.300 ; + END + END rw0_wd_in[238] + PIN rw0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.372 0.072 72.396 ; + END + END rw0_wd_in[239] + PIN rw0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.468 0.072 72.492 ; + END + END rw0_wd_in[240] + PIN rw0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.564 0.072 72.588 ; + END + END rw0_wd_in[241] + PIN rw0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.660 0.072 72.684 ; + END + END rw0_wd_in[242] + PIN rw0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.756 0.072 72.780 ; + END + END rw0_wd_in[243] + PIN rw0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.852 0.072 72.876 ; + END + END rw0_wd_in[244] + PIN rw0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.948 0.072 72.972 ; + END + END rw0_wd_in[245] + PIN rw0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.044 0.072 73.068 ; + END + END rw0_wd_in[246] + PIN rw0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.140 0.072 73.164 ; + END + END rw0_wd_in[247] + PIN rw0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.236 0.072 73.260 ; + END + END rw0_wd_in[248] + PIN rw0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.332 0.072 73.356 ; + END + END rw0_wd_in[249] + PIN rw0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.428 0.072 73.452 ; + END + END rw0_wd_in[250] + PIN rw0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.524 0.072 73.548 ; + END + END rw0_wd_in[251] + PIN rw0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.620 0.072 73.644 ; + END + END rw0_wd_in[252] + PIN rw0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.716 0.072 73.740 ; + END + END rw0_wd_in[253] + PIN rw0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.812 0.072 73.836 ; + END + END rw0_wd_in[254] + PIN rw0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.908 0.072 73.932 ; + END + END rw0_wd_in[255] + PIN rw0_wd_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.004 0.072 74.028 ; + END + END rw0_wd_in[256] + PIN rw0_wd_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.100 0.072 74.124 ; + END + END rw0_wd_in[257] + PIN rw0_wd_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.196 0.072 74.220 ; + END + END rw0_wd_in[258] + PIN rw0_wd_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.292 0.072 74.316 ; + END + END rw0_wd_in[259] + PIN rw0_wd_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.388 0.072 74.412 ; + END + END rw0_wd_in[260] + PIN rw0_wd_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.484 0.072 74.508 ; + END + END rw0_wd_in[261] + PIN rw0_wd_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.580 0.072 74.604 ; + END + END rw0_wd_in[262] + PIN rw0_wd_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.676 0.072 74.700 ; + END + END rw0_wd_in[263] + PIN rw0_wd_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.772 0.072 74.796 ; + END + END rw0_wd_in[264] + PIN rw0_wd_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.868 0.072 74.892 ; + END + END rw0_wd_in[265] + PIN rw0_wd_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 74.964 0.072 74.988 ; + END + END rw0_wd_in[266] + PIN rw0_wd_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.060 0.072 75.084 ; + END + END rw0_wd_in[267] + PIN rw0_wd_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.156 0.072 75.180 ; + END + END rw0_wd_in[268] + PIN rw0_wd_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.252 0.072 75.276 ; + END + END rw0_wd_in[269] + PIN rw0_wd_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.348 0.072 75.372 ; + END + END rw0_wd_in[270] + PIN rw0_wd_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.444 0.072 75.468 ; + END + END rw0_wd_in[271] + PIN rw0_wd_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.540 0.072 75.564 ; + END + END rw0_wd_in[272] + PIN rw0_wd_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.636 0.072 75.660 ; + END + END rw0_wd_in[273] + PIN rw0_wd_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.732 0.072 75.756 ; + END + END rw0_wd_in[274] + PIN rw0_wd_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.828 0.072 75.852 ; + END + END rw0_wd_in[275] + PIN rw0_wd_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 75.924 0.072 75.948 ; + END + END rw0_wd_in[276] + PIN rw0_wd_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.020 0.072 76.044 ; + END + END rw0_wd_in[277] + PIN rw0_wd_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.116 0.072 76.140 ; + END + END rw0_wd_in[278] + PIN rw0_wd_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.212 0.072 76.236 ; + END + END rw0_wd_in[279] + PIN rw0_wd_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.308 0.072 76.332 ; + END + END rw0_wd_in[280] + PIN rw0_wd_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.404 0.072 76.428 ; + END + END rw0_wd_in[281] + PIN rw0_wd_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.500 0.072 76.524 ; + END + END rw0_wd_in[282] + PIN rw0_wd_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.596 0.072 76.620 ; + END + END rw0_wd_in[283] + PIN rw0_wd_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.692 0.072 76.716 ; + END + END rw0_wd_in[284] + PIN rw0_wd_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.788 0.072 76.812 ; + END + END rw0_wd_in[285] + PIN rw0_wd_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.884 0.072 76.908 ; + END + END rw0_wd_in[286] + PIN rw0_wd_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 76.980 0.072 77.004 ; + END + END rw0_wd_in[287] + PIN rw0_wd_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.076 0.072 77.100 ; + END + END rw0_wd_in[288] + PIN rw0_wd_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.172 0.072 77.196 ; + END + END rw0_wd_in[289] + PIN rw0_wd_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.268 0.072 77.292 ; + END + END rw0_wd_in[290] + PIN rw0_wd_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.364 0.072 77.388 ; + END + END rw0_wd_in[291] + PIN rw0_wd_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.460 0.072 77.484 ; + END + END rw0_wd_in[292] + PIN rw0_wd_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.556 0.072 77.580 ; + END + END rw0_wd_in[293] + PIN rw0_wd_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.652 0.072 77.676 ; + END + END rw0_wd_in[294] + PIN rw0_wd_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.748 0.072 77.772 ; + END + END rw0_wd_in[295] + PIN rw0_wd_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.844 0.072 77.868 ; + END + END rw0_wd_in[296] + PIN rw0_wd_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.940 0.072 77.964 ; + END + END rw0_wd_in[297] + PIN rw0_wd_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.036 0.072 78.060 ; + END + END rw0_wd_in[298] + PIN rw0_wd_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.132 0.072 78.156 ; + END + END rw0_wd_in[299] + PIN rw0_wd_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.228 0.072 78.252 ; + END + END rw0_wd_in[300] + PIN rw0_wd_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.324 0.072 78.348 ; + END + END rw0_wd_in[301] + PIN rw0_wd_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.420 0.072 78.444 ; + END + END rw0_wd_in[302] + PIN rw0_wd_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.516 0.072 78.540 ; + END + END rw0_wd_in[303] + PIN rw0_wd_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.612 0.072 78.636 ; + END + END rw0_wd_in[304] + PIN rw0_wd_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.708 0.072 78.732 ; + END + END rw0_wd_in[305] + PIN rw0_wd_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.804 0.072 78.828 ; + END + END rw0_wd_in[306] + PIN rw0_wd_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.900 0.072 78.924 ; + END + END rw0_wd_in[307] + PIN rw0_wd_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.996 0.072 79.020 ; + END + END rw0_wd_in[308] + PIN rw0_wd_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.092 0.072 79.116 ; + END + END rw0_wd_in[309] + PIN rw0_wd_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.188 0.072 79.212 ; + END + END rw0_wd_in[310] + PIN rw0_wd_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.284 0.072 79.308 ; + END + END rw0_wd_in[311] + PIN rw0_wd_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.380 0.072 79.404 ; + END + END rw0_wd_in[312] + PIN rw0_wd_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.476 0.072 79.500 ; + END + END rw0_wd_in[313] + PIN rw0_wd_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.572 0.072 79.596 ; + END + END rw0_wd_in[314] + PIN rw0_wd_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.668 0.072 79.692 ; + END + END rw0_wd_in[315] + PIN rw0_wd_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.764 0.072 79.788 ; + END + END rw0_wd_in[316] + PIN rw0_wd_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.860 0.072 79.884 ; + END + END rw0_wd_in[317] + PIN rw0_wd_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.956 0.072 79.980 ; + END + END rw0_wd_in[318] + PIN rw0_wd_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.052 0.072 80.076 ; + END + END rw0_wd_in[319] + PIN rw0_wd_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.148 0.072 80.172 ; + END + END rw0_wd_in[320] + PIN rw0_wd_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.244 0.072 80.268 ; + END + END rw0_wd_in[321] + PIN rw0_wd_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.340 0.072 80.364 ; + END + END rw0_wd_in[322] + PIN rw0_wd_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.436 0.072 80.460 ; + END + END rw0_wd_in[323] + PIN rw0_wd_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.532 0.072 80.556 ; + END + END rw0_wd_in[324] + PIN rw0_wd_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.628 0.072 80.652 ; + END + END rw0_wd_in[325] + PIN rw0_wd_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.724 0.072 80.748 ; + END + END rw0_wd_in[326] + PIN rw0_wd_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.820 0.072 80.844 ; + END + END rw0_wd_in[327] + PIN rw0_wd_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.916 0.072 80.940 ; + END + END rw0_wd_in[328] + PIN rw0_wd_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.012 0.072 81.036 ; + END + END rw0_wd_in[329] + PIN rw0_wd_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.108 0.072 81.132 ; + END + END rw0_wd_in[330] + PIN rw0_wd_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.204 0.072 81.228 ; + END + END rw0_wd_in[331] + PIN rw0_wd_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.300 0.072 81.324 ; + END + END rw0_wd_in[332] + PIN rw0_wd_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.396 0.072 81.420 ; + END + END rw0_wd_in[333] + PIN rw0_wd_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.492 0.072 81.516 ; + END + END rw0_wd_in[334] + PIN rw0_wd_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.588 0.072 81.612 ; + END + END rw0_wd_in[335] + PIN rw0_wd_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.684 0.072 81.708 ; + END + END rw0_wd_in[336] + PIN rw0_wd_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.780 0.072 81.804 ; + END + END rw0_wd_in[337] + PIN rw0_wd_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.876 0.072 81.900 ; + END + END rw0_wd_in[338] + PIN rw0_wd_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.972 0.072 81.996 ; + END + END rw0_wd_in[339] + PIN rw0_wd_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.068 0.072 82.092 ; + END + END rw0_wd_in[340] + PIN rw0_wd_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.164 0.072 82.188 ; + END + END rw0_wd_in[341] + PIN rw0_wd_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.260 0.072 82.284 ; + END + END rw0_wd_in[342] + PIN rw0_wd_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.356 0.072 82.380 ; + END + END rw0_wd_in[343] + PIN rw0_wd_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.452 0.072 82.476 ; + END + END rw0_wd_in[344] + PIN rw0_wd_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.548 0.072 82.572 ; + END + END rw0_wd_in[345] + PIN rw0_wd_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.644 0.072 82.668 ; + END + END rw0_wd_in[346] + PIN rw0_wd_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.740 0.072 82.764 ; + END + END rw0_wd_in[347] + PIN rw0_wd_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.836 0.072 82.860 ; + END + END rw0_wd_in[348] + PIN rw0_wd_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.932 0.072 82.956 ; + END + END rw0_wd_in[349] + PIN rw0_wd_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.028 0.072 83.052 ; + END + END rw0_wd_in[350] + PIN rw0_wd_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.124 0.072 83.148 ; + END + END rw0_wd_in[351] + PIN rw0_wd_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.220 0.072 83.244 ; + END + END rw0_wd_in[352] + PIN rw0_wd_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.316 0.072 83.340 ; + END + END rw0_wd_in[353] + PIN rw0_wd_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.412 0.072 83.436 ; + END + END rw0_wd_in[354] + PIN rw0_wd_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.508 0.072 83.532 ; + END + END rw0_wd_in[355] + PIN rw0_wd_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.604 0.072 83.628 ; + END + END rw0_wd_in[356] + PIN rw0_wd_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.700 0.072 83.724 ; + END + END rw0_wd_in[357] + PIN rw0_wd_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.796 0.072 83.820 ; + END + END rw0_wd_in[358] + PIN rw0_wd_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.892 0.072 83.916 ; + END + END rw0_wd_in[359] + PIN rw0_wd_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.988 0.072 84.012 ; + END + END rw0_wd_in[360] + PIN rw0_wd_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.084 0.072 84.108 ; + END + END rw0_wd_in[361] + PIN rw0_wd_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.180 0.072 84.204 ; + END + END rw0_wd_in[362] + PIN rw0_wd_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.276 0.072 84.300 ; + END + END rw0_wd_in[363] + PIN rw0_wd_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.372 0.072 84.396 ; + END + END rw0_wd_in[364] + PIN rw0_wd_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.468 0.072 84.492 ; + END + END rw0_wd_in[365] + PIN rw0_wd_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.564 0.072 84.588 ; + END + END rw0_wd_in[366] + PIN rw0_wd_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.660 0.072 84.684 ; + END + END rw0_wd_in[367] + PIN rw0_wd_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.756 0.072 84.780 ; + END + END rw0_wd_in[368] + PIN rw0_wd_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.852 0.072 84.876 ; + END + END rw0_wd_in[369] + PIN rw0_wd_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.948 0.072 84.972 ; + END + END rw0_wd_in[370] + PIN rw0_wd_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.044 0.072 85.068 ; + END + END rw0_wd_in[371] + PIN rw0_wd_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.140 0.072 85.164 ; + END + END rw0_wd_in[372] + PIN rw0_wd_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.236 0.072 85.260 ; + END + END rw0_wd_in[373] + PIN rw0_wd_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.332 0.072 85.356 ; + END + END rw0_wd_in[374] + PIN rw0_wd_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.428 0.072 85.452 ; + END + END rw0_wd_in[375] + PIN rw0_wd_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.524 0.072 85.548 ; + END + END rw0_wd_in[376] + PIN rw0_wd_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.620 0.072 85.644 ; + END + END rw0_wd_in[377] + PIN rw0_wd_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.716 0.072 85.740 ; + END + END rw0_wd_in[378] + PIN rw0_wd_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.812 0.072 85.836 ; + END + END rw0_wd_in[379] + PIN rw0_wd_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.908 0.072 85.932 ; + END + END rw0_wd_in[380] + PIN rw0_wd_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.004 0.072 86.028 ; + END + END rw0_wd_in[381] + PIN rw0_wd_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.100 0.072 86.124 ; + END + END rw0_wd_in[382] + PIN rw0_wd_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.196 0.072 86.220 ; + END + END rw0_wd_in[383] + PIN rw0_wd_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.292 0.072 86.316 ; + END + END rw0_wd_in[384] + PIN rw0_wd_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.388 0.072 86.412 ; + END + END rw0_wd_in[385] + PIN rw0_wd_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.484 0.072 86.508 ; + END + END rw0_wd_in[386] + PIN rw0_wd_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.580 0.072 86.604 ; + END + END rw0_wd_in[387] + PIN rw0_wd_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.676 0.072 86.700 ; + END + END rw0_wd_in[388] + PIN rw0_wd_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.772 0.072 86.796 ; + END + END rw0_wd_in[389] + PIN rw0_wd_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.868 0.072 86.892 ; + END + END rw0_wd_in[390] + PIN rw0_wd_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.964 0.072 86.988 ; + END + END rw0_wd_in[391] + PIN rw0_wd_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.060 0.072 87.084 ; + END + END rw0_wd_in[392] + PIN rw0_wd_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.156 0.072 87.180 ; + END + END rw0_wd_in[393] + PIN rw0_wd_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.252 0.072 87.276 ; + END + END rw0_wd_in[394] + PIN rw0_wd_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.348 0.072 87.372 ; + END + END rw0_wd_in[395] + PIN rw0_wd_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.444 0.072 87.468 ; + END + END rw0_wd_in[396] + PIN rw0_wd_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.540 0.072 87.564 ; + END + END rw0_wd_in[397] + PIN rw0_wd_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.636 0.072 87.660 ; + END + END rw0_wd_in[398] + PIN rw0_wd_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.732 0.072 87.756 ; + END + END rw0_wd_in[399] + PIN rw0_wd_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.828 0.072 87.852 ; + END + END rw0_wd_in[400] + PIN rw0_wd_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.924 0.072 87.948 ; + END + END rw0_wd_in[401] + PIN rw0_wd_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.020 0.072 88.044 ; + END + END rw0_wd_in[402] + PIN rw0_wd_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.116 0.072 88.140 ; + END + END rw0_wd_in[403] + PIN rw0_wd_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.212 0.072 88.236 ; + END + END rw0_wd_in[404] + PIN rw0_wd_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.308 0.072 88.332 ; + END + END rw0_wd_in[405] + PIN rw0_wd_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.404 0.072 88.428 ; + END + END rw0_wd_in[406] + PIN rw0_wd_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.500 0.072 88.524 ; + END + END rw0_wd_in[407] + PIN rw0_wd_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.596 0.072 88.620 ; + END + END rw0_wd_in[408] + PIN rw0_wd_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.692 0.072 88.716 ; + END + END rw0_wd_in[409] + PIN rw0_wd_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.788 0.072 88.812 ; + END + END rw0_wd_in[410] + PIN rw0_wd_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.884 0.072 88.908 ; + END + END rw0_wd_in[411] + PIN rw0_wd_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.980 0.072 89.004 ; + END + END rw0_wd_in[412] + PIN rw0_wd_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.076 0.072 89.100 ; + END + END rw0_wd_in[413] + PIN rw0_wd_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.172 0.072 89.196 ; + END + END rw0_wd_in[414] + PIN rw0_wd_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.268 0.072 89.292 ; + END + END rw0_wd_in[415] + PIN rw0_wd_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.364 0.072 89.388 ; + END + END rw0_wd_in[416] + PIN rw0_wd_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.460 0.072 89.484 ; + END + END rw0_wd_in[417] + PIN rw0_wd_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.556 0.072 89.580 ; + END + END rw0_wd_in[418] + PIN rw0_wd_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.652 0.072 89.676 ; + END + END rw0_wd_in[419] + PIN rw0_wd_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.748 0.072 89.772 ; + END + END rw0_wd_in[420] + PIN rw0_wd_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.844 0.072 89.868 ; + END + END rw0_wd_in[421] + PIN rw0_wd_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.940 0.072 89.964 ; + END + END rw0_wd_in[422] + PIN rw0_wd_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.036 0.072 90.060 ; + END + END rw0_wd_in[423] + PIN rw0_wd_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.132 0.072 90.156 ; + END + END rw0_wd_in[424] + PIN rw0_wd_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.228 0.072 90.252 ; + END + END rw0_wd_in[425] + PIN rw0_wd_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.324 0.072 90.348 ; + END + END rw0_wd_in[426] + PIN rw0_wd_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.420 0.072 90.444 ; + END + END rw0_wd_in[427] + PIN rw0_wd_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.516 0.072 90.540 ; + END + END rw0_wd_in[428] + PIN rw0_wd_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.612 0.072 90.636 ; + END + END rw0_wd_in[429] + PIN rw0_wd_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.708 0.072 90.732 ; + END + END rw0_wd_in[430] + PIN rw0_wd_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.804 0.072 90.828 ; + END + END rw0_wd_in[431] + PIN rw0_wd_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.900 0.072 90.924 ; + END + END rw0_wd_in[432] + PIN rw0_wd_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.996 0.072 91.020 ; + END + END rw0_wd_in[433] + PIN rw0_wd_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.092 0.072 91.116 ; + END + END rw0_wd_in[434] + PIN rw0_wd_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.188 0.072 91.212 ; + END + END rw0_wd_in[435] + PIN rw0_wd_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.284 0.072 91.308 ; + END + END rw0_wd_in[436] + PIN rw0_wd_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.380 0.072 91.404 ; + END + END rw0_wd_in[437] + PIN rw0_wd_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.476 0.072 91.500 ; + END + END rw0_wd_in[438] + PIN rw0_wd_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.572 0.072 91.596 ; + END + END rw0_wd_in[439] + PIN rw0_wd_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.668 0.072 91.692 ; + END + END rw0_wd_in[440] + PIN rw0_wd_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.764 0.072 91.788 ; + END + END rw0_wd_in[441] + PIN rw0_wd_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.860 0.072 91.884 ; + END + END rw0_wd_in[442] + PIN rw0_wd_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.956 0.072 91.980 ; + END + END rw0_wd_in[443] + PIN rw0_wd_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.052 0.072 92.076 ; + END + END rw0_wd_in[444] + PIN rw0_wd_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.148 0.072 92.172 ; + END + END rw0_wd_in[445] + PIN rw0_wd_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.244 0.072 92.268 ; + END + END rw0_wd_in[446] + PIN rw0_wd_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.340 0.072 92.364 ; + END + END rw0_wd_in[447] + PIN rw0_wd_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.436 0.072 92.460 ; + END + END rw0_wd_in[448] + PIN rw0_wd_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.532 0.072 92.556 ; + END + END rw0_wd_in[449] + PIN rw0_wd_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.628 0.072 92.652 ; + END + END rw0_wd_in[450] + PIN rw0_wd_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.724 0.072 92.748 ; + END + END rw0_wd_in[451] + PIN rw0_wd_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.820 0.072 92.844 ; + END + END rw0_wd_in[452] + PIN rw0_wd_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.916 0.072 92.940 ; + END + END rw0_wd_in[453] + PIN rw0_wd_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.012 0.072 93.036 ; + END + END rw0_wd_in[454] + PIN rw0_wd_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.108 0.072 93.132 ; + END + END rw0_wd_in[455] + PIN rw0_wd_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.204 0.072 93.228 ; + END + END rw0_wd_in[456] + PIN rw0_wd_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.300 0.072 93.324 ; + END + END rw0_wd_in[457] + PIN rw0_wd_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.396 0.072 93.420 ; + END + END rw0_wd_in[458] + PIN rw0_wd_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.492 0.072 93.516 ; + END + END rw0_wd_in[459] + PIN rw0_wd_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.588 0.072 93.612 ; + END + END rw0_wd_in[460] + PIN rw0_wd_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.684 0.072 93.708 ; + END + END rw0_wd_in[461] + PIN rw0_wd_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.780 0.072 93.804 ; + END + END rw0_wd_in[462] + PIN rw0_wd_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.876 0.072 93.900 ; + END + END rw0_wd_in[463] + PIN rw0_wd_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.972 0.072 93.996 ; + END + END rw0_wd_in[464] + PIN rw0_wd_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.068 0.072 94.092 ; + END + END rw0_wd_in[465] + PIN rw0_wd_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.164 0.072 94.188 ; + END + END rw0_wd_in[466] + PIN rw0_wd_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.260 0.072 94.284 ; + END + END rw0_wd_in[467] + PIN rw0_wd_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.356 0.072 94.380 ; + END + END rw0_wd_in[468] + PIN rw0_wd_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.452 0.072 94.476 ; + END + END rw0_wd_in[469] + PIN rw0_wd_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.548 0.072 94.572 ; + END + END rw0_wd_in[470] + PIN rw0_wd_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.644 0.072 94.668 ; + END + END rw0_wd_in[471] + PIN rw0_wd_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.740 0.072 94.764 ; + END + END rw0_wd_in[472] + PIN rw0_wd_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.836 0.072 94.860 ; + END + END rw0_wd_in[473] + PIN rw0_wd_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.932 0.072 94.956 ; + END + END rw0_wd_in[474] + PIN rw0_wd_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.028 0.072 95.052 ; + END + END rw0_wd_in[475] + PIN rw0_wd_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.124 0.072 95.148 ; + END + END rw0_wd_in[476] + PIN rw0_wd_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.220 0.072 95.244 ; + END + END rw0_wd_in[477] + PIN rw0_wd_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.316 0.072 95.340 ; + END + END rw0_wd_in[478] + PIN rw0_wd_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.412 0.072 95.436 ; + END + END rw0_wd_in[479] + PIN rw0_wd_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.508 0.072 95.532 ; + END + END rw0_wd_in[480] + PIN rw0_wd_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.604 0.072 95.628 ; + END + END rw0_wd_in[481] + PIN rw0_wd_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.700 0.072 95.724 ; + END + END rw0_wd_in[482] + PIN rw0_wd_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.796 0.072 95.820 ; + END + END rw0_wd_in[483] + PIN rw0_wd_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.892 0.072 95.916 ; + END + END rw0_wd_in[484] + PIN rw0_wd_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.988 0.072 96.012 ; + END + END rw0_wd_in[485] + PIN rw0_wd_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.084 0.072 96.108 ; + END + END rw0_wd_in[486] + PIN rw0_wd_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.180 0.072 96.204 ; + END + END rw0_wd_in[487] + PIN rw0_wd_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.276 0.072 96.300 ; + END + END rw0_wd_in[488] + PIN rw0_wd_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.372 0.072 96.396 ; + END + END rw0_wd_in[489] + PIN rw0_wd_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.468 0.072 96.492 ; + END + END rw0_wd_in[490] + PIN rw0_wd_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.564 0.072 96.588 ; + END + END rw0_wd_in[491] + PIN rw0_wd_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.660 0.072 96.684 ; + END + END rw0_wd_in[492] + PIN rw0_wd_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.756 0.072 96.780 ; + END + END rw0_wd_in[493] + PIN rw0_wd_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.852 0.072 96.876 ; + END + END rw0_wd_in[494] + PIN rw0_wd_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.948 0.072 96.972 ; + END + END rw0_wd_in[495] + PIN rw0_wd_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.044 0.072 97.068 ; + END + END rw0_wd_in[496] + PIN rw0_wd_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.140 0.072 97.164 ; + END + END rw0_wd_in[497] + PIN rw0_wd_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.236 0.072 97.260 ; + END + END rw0_wd_in[498] + PIN rw0_wd_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.332 0.072 97.356 ; + END + END rw0_wd_in[499] + PIN rw0_wd_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.428 0.072 97.452 ; + END + END rw0_wd_in[500] + PIN rw0_wd_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.524 0.072 97.548 ; + END + END rw0_wd_in[501] + PIN rw0_wd_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.620 0.072 97.644 ; + END + END rw0_wd_in[502] + PIN rw0_wd_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.716 0.072 97.740 ; + END + END rw0_wd_in[503] + PIN rw0_wd_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.812 0.072 97.836 ; + END + END rw0_wd_in[504] + PIN rw0_wd_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.908 0.072 97.932 ; + END + END rw0_wd_in[505] + PIN rw0_wd_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.004 0.072 98.028 ; + END + END rw0_wd_in[506] + PIN rw0_wd_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.100 0.072 98.124 ; + END + END rw0_wd_in[507] + PIN rw0_wd_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.196 0.072 98.220 ; + END + END rw0_wd_in[508] + PIN rw0_wd_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.292 0.072 98.316 ; + END + END rw0_wd_in[509] + PIN rw0_wd_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.388 0.072 98.412 ; + END + END rw0_wd_in[510] + PIN rw0_wd_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.484 0.072 98.508 ; + END + END rw0_wd_in[511] + PIN rw0_wd_in[512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.428 416.048 49.452 ; + END + END rw0_wd_in[512] + PIN rw0_wd_in[513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.524 416.048 49.548 ; + END + END rw0_wd_in[513] + PIN rw0_wd_in[514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.620 416.048 49.644 ; + END + END rw0_wd_in[514] + PIN rw0_wd_in[515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.716 416.048 49.740 ; + END + END rw0_wd_in[515] + PIN rw0_wd_in[516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.812 416.048 49.836 ; + END + END rw0_wd_in[516] + PIN rw0_wd_in[517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 49.908 416.048 49.932 ; + END + END rw0_wd_in[517] + PIN rw0_wd_in[518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.004 416.048 50.028 ; + END + END rw0_wd_in[518] + PIN rw0_wd_in[519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.100 416.048 50.124 ; + END + END rw0_wd_in[519] + PIN rw0_wd_in[520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.196 416.048 50.220 ; + END + END rw0_wd_in[520] + PIN rw0_wd_in[521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.292 416.048 50.316 ; + END + END rw0_wd_in[521] + PIN rw0_wd_in[522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.388 416.048 50.412 ; + END + END rw0_wd_in[522] + PIN rw0_wd_in[523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.484 416.048 50.508 ; + END + END rw0_wd_in[523] + PIN rw0_wd_in[524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.580 416.048 50.604 ; + END + END rw0_wd_in[524] + PIN rw0_wd_in[525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.676 416.048 50.700 ; + END + END rw0_wd_in[525] + PIN rw0_wd_in[526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.772 416.048 50.796 ; + END + END rw0_wd_in[526] + PIN rw0_wd_in[527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.868 416.048 50.892 ; + END + END rw0_wd_in[527] + PIN rw0_wd_in[528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 50.964 416.048 50.988 ; + END + END rw0_wd_in[528] + PIN rw0_wd_in[529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.060 416.048 51.084 ; + END + END rw0_wd_in[529] + PIN rw0_wd_in[530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.156 416.048 51.180 ; + END + END rw0_wd_in[530] + PIN rw0_wd_in[531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.252 416.048 51.276 ; + END + END rw0_wd_in[531] + PIN rw0_wd_in[532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.348 416.048 51.372 ; + END + END rw0_wd_in[532] + PIN rw0_wd_in[533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.444 416.048 51.468 ; + END + END rw0_wd_in[533] + PIN rw0_wd_in[534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.540 416.048 51.564 ; + END + END rw0_wd_in[534] + PIN rw0_wd_in[535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.636 416.048 51.660 ; + END + END rw0_wd_in[535] + PIN rw0_wd_in[536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.732 416.048 51.756 ; + END + END rw0_wd_in[536] + PIN rw0_wd_in[537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.828 416.048 51.852 ; + END + END rw0_wd_in[537] + PIN rw0_wd_in[538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 51.924 416.048 51.948 ; + END + END rw0_wd_in[538] + PIN rw0_wd_in[539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.020 416.048 52.044 ; + END + END rw0_wd_in[539] + PIN rw0_wd_in[540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.116 416.048 52.140 ; + END + END rw0_wd_in[540] + PIN rw0_wd_in[541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.212 416.048 52.236 ; + END + END rw0_wd_in[541] + PIN rw0_wd_in[542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.308 416.048 52.332 ; + END + END rw0_wd_in[542] + PIN rw0_wd_in[543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.404 416.048 52.428 ; + END + END rw0_wd_in[543] + PIN rw0_wd_in[544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.500 416.048 52.524 ; + END + END rw0_wd_in[544] + PIN rw0_wd_in[545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.596 416.048 52.620 ; + END + END rw0_wd_in[545] + PIN rw0_wd_in[546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.692 416.048 52.716 ; + END + END rw0_wd_in[546] + PIN rw0_wd_in[547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.788 416.048 52.812 ; + END + END rw0_wd_in[547] + PIN rw0_wd_in[548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.884 416.048 52.908 ; + END + END rw0_wd_in[548] + PIN rw0_wd_in[549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 52.980 416.048 53.004 ; + END + END rw0_wd_in[549] + PIN rw0_wd_in[550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.076 416.048 53.100 ; + END + END rw0_wd_in[550] + PIN rw0_wd_in[551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.172 416.048 53.196 ; + END + END rw0_wd_in[551] + PIN rw0_wd_in[552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.268 416.048 53.292 ; + END + END rw0_wd_in[552] + PIN rw0_wd_in[553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.364 416.048 53.388 ; + END + END rw0_wd_in[553] + PIN rw0_wd_in[554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.460 416.048 53.484 ; + END + END rw0_wd_in[554] + PIN rw0_wd_in[555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.556 416.048 53.580 ; + END + END rw0_wd_in[555] + PIN rw0_wd_in[556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.652 416.048 53.676 ; + END + END rw0_wd_in[556] + PIN rw0_wd_in[557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.748 416.048 53.772 ; + END + END rw0_wd_in[557] + PIN rw0_wd_in[558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.844 416.048 53.868 ; + END + END rw0_wd_in[558] + PIN rw0_wd_in[559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 53.940 416.048 53.964 ; + END + END rw0_wd_in[559] + PIN rw0_wd_in[560] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.036 416.048 54.060 ; + END + END rw0_wd_in[560] + PIN rw0_wd_in[561] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.132 416.048 54.156 ; + END + END rw0_wd_in[561] + PIN rw0_wd_in[562] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.228 416.048 54.252 ; + END + END rw0_wd_in[562] + PIN rw0_wd_in[563] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.324 416.048 54.348 ; + END + END rw0_wd_in[563] + PIN rw0_wd_in[564] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.420 416.048 54.444 ; + END + END rw0_wd_in[564] + PIN rw0_wd_in[565] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.516 416.048 54.540 ; + END + END rw0_wd_in[565] + PIN rw0_wd_in[566] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.612 416.048 54.636 ; + END + END rw0_wd_in[566] + PIN rw0_wd_in[567] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.708 416.048 54.732 ; + END + END rw0_wd_in[567] + PIN rw0_wd_in[568] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.804 416.048 54.828 ; + END + END rw0_wd_in[568] + PIN rw0_wd_in[569] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.900 416.048 54.924 ; + END + END rw0_wd_in[569] + PIN rw0_wd_in[570] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 54.996 416.048 55.020 ; + END + END rw0_wd_in[570] + PIN rw0_wd_in[571] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.092 416.048 55.116 ; + END + END rw0_wd_in[571] + PIN rw0_wd_in[572] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.188 416.048 55.212 ; + END + END rw0_wd_in[572] + PIN rw0_wd_in[573] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.284 416.048 55.308 ; + END + END rw0_wd_in[573] + PIN rw0_wd_in[574] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.380 416.048 55.404 ; + END + END rw0_wd_in[574] + PIN rw0_wd_in[575] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.476 416.048 55.500 ; + END + END rw0_wd_in[575] + PIN rw0_wd_in[576] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.572 416.048 55.596 ; + END + END rw0_wd_in[576] + PIN rw0_wd_in[577] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.668 416.048 55.692 ; + END + END rw0_wd_in[577] + PIN rw0_wd_in[578] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.764 416.048 55.788 ; + END + END rw0_wd_in[578] + PIN rw0_wd_in[579] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.860 416.048 55.884 ; + END + END rw0_wd_in[579] + PIN rw0_wd_in[580] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 55.956 416.048 55.980 ; + END + END rw0_wd_in[580] + PIN rw0_wd_in[581] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.052 416.048 56.076 ; + END + END rw0_wd_in[581] + PIN rw0_wd_in[582] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.148 416.048 56.172 ; + END + END rw0_wd_in[582] + PIN rw0_wd_in[583] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.244 416.048 56.268 ; + END + END rw0_wd_in[583] + PIN rw0_wd_in[584] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.340 416.048 56.364 ; + END + END rw0_wd_in[584] + PIN rw0_wd_in[585] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.436 416.048 56.460 ; + END + END rw0_wd_in[585] + PIN rw0_wd_in[586] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.532 416.048 56.556 ; + END + END rw0_wd_in[586] + PIN rw0_wd_in[587] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.628 416.048 56.652 ; + END + END rw0_wd_in[587] + PIN rw0_wd_in[588] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.724 416.048 56.748 ; + END + END rw0_wd_in[588] + PIN rw0_wd_in[589] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.820 416.048 56.844 ; + END + END rw0_wd_in[589] + PIN rw0_wd_in[590] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 56.916 416.048 56.940 ; + END + END rw0_wd_in[590] + PIN rw0_wd_in[591] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.012 416.048 57.036 ; + END + END rw0_wd_in[591] + PIN rw0_wd_in[592] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.108 416.048 57.132 ; + END + END rw0_wd_in[592] + PIN rw0_wd_in[593] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.204 416.048 57.228 ; + END + END rw0_wd_in[593] + PIN rw0_wd_in[594] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.300 416.048 57.324 ; + END + END rw0_wd_in[594] + PIN rw0_wd_in[595] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.396 416.048 57.420 ; + END + END rw0_wd_in[595] + PIN rw0_wd_in[596] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.492 416.048 57.516 ; + END + END rw0_wd_in[596] + PIN rw0_wd_in[597] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.588 416.048 57.612 ; + END + END rw0_wd_in[597] + PIN rw0_wd_in[598] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.684 416.048 57.708 ; + END + END rw0_wd_in[598] + PIN rw0_wd_in[599] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.780 416.048 57.804 ; + END + END rw0_wd_in[599] + PIN rw0_wd_in[600] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.876 416.048 57.900 ; + END + END rw0_wd_in[600] + PIN rw0_wd_in[601] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 57.972 416.048 57.996 ; + END + END rw0_wd_in[601] + PIN rw0_wd_in[602] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.068 416.048 58.092 ; + END + END rw0_wd_in[602] + PIN rw0_wd_in[603] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.164 416.048 58.188 ; + END + END rw0_wd_in[603] + PIN rw0_wd_in[604] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.260 416.048 58.284 ; + END + END rw0_wd_in[604] + PIN rw0_wd_in[605] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.356 416.048 58.380 ; + END + END rw0_wd_in[605] + PIN rw0_wd_in[606] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.452 416.048 58.476 ; + END + END rw0_wd_in[606] + PIN rw0_wd_in[607] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.548 416.048 58.572 ; + END + END rw0_wd_in[607] + PIN rw0_wd_in[608] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.644 416.048 58.668 ; + END + END rw0_wd_in[608] + PIN rw0_wd_in[609] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.740 416.048 58.764 ; + END + END rw0_wd_in[609] + PIN rw0_wd_in[610] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.836 416.048 58.860 ; + END + END rw0_wd_in[610] + PIN rw0_wd_in[611] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 58.932 416.048 58.956 ; + END + END rw0_wd_in[611] + PIN rw0_wd_in[612] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.028 416.048 59.052 ; + END + END rw0_wd_in[612] + PIN rw0_wd_in[613] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.124 416.048 59.148 ; + END + END rw0_wd_in[613] + PIN rw0_wd_in[614] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.220 416.048 59.244 ; + END + END rw0_wd_in[614] + PIN rw0_wd_in[615] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.316 416.048 59.340 ; + END + END rw0_wd_in[615] + PIN rw0_wd_in[616] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.412 416.048 59.436 ; + END + END rw0_wd_in[616] + PIN rw0_wd_in[617] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.508 416.048 59.532 ; + END + END rw0_wd_in[617] + PIN rw0_wd_in[618] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.604 416.048 59.628 ; + END + END rw0_wd_in[618] + PIN rw0_wd_in[619] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.700 416.048 59.724 ; + END + END rw0_wd_in[619] + PIN rw0_wd_in[620] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.796 416.048 59.820 ; + END + END rw0_wd_in[620] + PIN rw0_wd_in[621] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.892 416.048 59.916 ; + END + END rw0_wd_in[621] + PIN rw0_wd_in[622] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 59.988 416.048 60.012 ; + END + END rw0_wd_in[622] + PIN rw0_wd_in[623] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.084 416.048 60.108 ; + END + END rw0_wd_in[623] + PIN rw0_wd_in[624] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.180 416.048 60.204 ; + END + END rw0_wd_in[624] + PIN rw0_wd_in[625] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.276 416.048 60.300 ; + END + END rw0_wd_in[625] + PIN rw0_wd_in[626] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.372 416.048 60.396 ; + END + END rw0_wd_in[626] + PIN rw0_wd_in[627] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.468 416.048 60.492 ; + END + END rw0_wd_in[627] + PIN rw0_wd_in[628] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.564 416.048 60.588 ; + END + END rw0_wd_in[628] + PIN rw0_wd_in[629] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.660 416.048 60.684 ; + END + END rw0_wd_in[629] + PIN rw0_wd_in[630] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.756 416.048 60.780 ; + END + END rw0_wd_in[630] + PIN rw0_wd_in[631] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.852 416.048 60.876 ; + END + END rw0_wd_in[631] + PIN rw0_wd_in[632] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 60.948 416.048 60.972 ; + END + END rw0_wd_in[632] + PIN rw0_wd_in[633] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.044 416.048 61.068 ; + END + END rw0_wd_in[633] + PIN rw0_wd_in[634] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.140 416.048 61.164 ; + END + END rw0_wd_in[634] + PIN rw0_wd_in[635] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.236 416.048 61.260 ; + END + END rw0_wd_in[635] + PIN rw0_wd_in[636] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.332 416.048 61.356 ; + END + END rw0_wd_in[636] + PIN rw0_wd_in[637] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.428 416.048 61.452 ; + END + END rw0_wd_in[637] + PIN rw0_wd_in[638] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.524 416.048 61.548 ; + END + END rw0_wd_in[638] + PIN rw0_wd_in[639] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.620 416.048 61.644 ; + END + END rw0_wd_in[639] + PIN rw0_wd_in[640] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.716 416.048 61.740 ; + END + END rw0_wd_in[640] + PIN rw0_wd_in[641] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.812 416.048 61.836 ; + END + END rw0_wd_in[641] + PIN rw0_wd_in[642] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 61.908 416.048 61.932 ; + END + END rw0_wd_in[642] + PIN rw0_wd_in[643] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.004 416.048 62.028 ; + END + END rw0_wd_in[643] + PIN rw0_wd_in[644] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.100 416.048 62.124 ; + END + END rw0_wd_in[644] + PIN rw0_wd_in[645] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.196 416.048 62.220 ; + END + END rw0_wd_in[645] + PIN rw0_wd_in[646] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.292 416.048 62.316 ; + END + END rw0_wd_in[646] + PIN rw0_wd_in[647] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.388 416.048 62.412 ; + END + END rw0_wd_in[647] + PIN rw0_wd_in[648] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.484 416.048 62.508 ; + END + END rw0_wd_in[648] + PIN rw0_wd_in[649] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.580 416.048 62.604 ; + END + END rw0_wd_in[649] + PIN rw0_wd_in[650] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.676 416.048 62.700 ; + END + END rw0_wd_in[650] + PIN rw0_wd_in[651] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.772 416.048 62.796 ; + END + END rw0_wd_in[651] + PIN rw0_wd_in[652] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.868 416.048 62.892 ; + END + END rw0_wd_in[652] + PIN rw0_wd_in[653] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 62.964 416.048 62.988 ; + END + END rw0_wd_in[653] + PIN rw0_wd_in[654] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.060 416.048 63.084 ; + END + END rw0_wd_in[654] + PIN rw0_wd_in[655] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.156 416.048 63.180 ; + END + END rw0_wd_in[655] + PIN rw0_wd_in[656] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.252 416.048 63.276 ; + END + END rw0_wd_in[656] + PIN rw0_wd_in[657] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.348 416.048 63.372 ; + END + END rw0_wd_in[657] + PIN rw0_wd_in[658] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.444 416.048 63.468 ; + END + END rw0_wd_in[658] + PIN rw0_wd_in[659] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.540 416.048 63.564 ; + END + END rw0_wd_in[659] + PIN rw0_wd_in[660] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.636 416.048 63.660 ; + END + END rw0_wd_in[660] + PIN rw0_wd_in[661] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.732 416.048 63.756 ; + END + END rw0_wd_in[661] + PIN rw0_wd_in[662] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.828 416.048 63.852 ; + END + END rw0_wd_in[662] + PIN rw0_wd_in[663] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 63.924 416.048 63.948 ; + END + END rw0_wd_in[663] + PIN rw0_wd_in[664] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.020 416.048 64.044 ; + END + END rw0_wd_in[664] + PIN rw0_wd_in[665] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.116 416.048 64.140 ; + END + END rw0_wd_in[665] + PIN rw0_wd_in[666] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.212 416.048 64.236 ; + END + END rw0_wd_in[666] + PIN rw0_wd_in[667] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.308 416.048 64.332 ; + END + END rw0_wd_in[667] + PIN rw0_wd_in[668] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.404 416.048 64.428 ; + END + END rw0_wd_in[668] + PIN rw0_wd_in[669] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.500 416.048 64.524 ; + END + END rw0_wd_in[669] + PIN rw0_wd_in[670] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.596 416.048 64.620 ; + END + END rw0_wd_in[670] + PIN rw0_wd_in[671] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.692 416.048 64.716 ; + END + END rw0_wd_in[671] + PIN rw0_wd_in[672] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.788 416.048 64.812 ; + END + END rw0_wd_in[672] + PIN rw0_wd_in[673] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.884 416.048 64.908 ; + END + END rw0_wd_in[673] + PIN rw0_wd_in[674] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 64.980 416.048 65.004 ; + END + END rw0_wd_in[674] + PIN rw0_wd_in[675] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.076 416.048 65.100 ; + END + END rw0_wd_in[675] + PIN rw0_wd_in[676] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.172 416.048 65.196 ; + END + END rw0_wd_in[676] + PIN rw0_wd_in[677] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.268 416.048 65.292 ; + END + END rw0_wd_in[677] + PIN rw0_wd_in[678] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.364 416.048 65.388 ; + END + END rw0_wd_in[678] + PIN rw0_wd_in[679] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.460 416.048 65.484 ; + END + END rw0_wd_in[679] + PIN rw0_wd_in[680] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.556 416.048 65.580 ; + END + END rw0_wd_in[680] + PIN rw0_wd_in[681] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.652 416.048 65.676 ; + END + END rw0_wd_in[681] + PIN rw0_wd_in[682] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.748 416.048 65.772 ; + END + END rw0_wd_in[682] + PIN rw0_wd_in[683] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.844 416.048 65.868 ; + END + END rw0_wd_in[683] + PIN rw0_wd_in[684] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 65.940 416.048 65.964 ; + END + END rw0_wd_in[684] + PIN rw0_wd_in[685] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.036 416.048 66.060 ; + END + END rw0_wd_in[685] + PIN rw0_wd_in[686] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.132 416.048 66.156 ; + END + END rw0_wd_in[686] + PIN rw0_wd_in[687] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.228 416.048 66.252 ; + END + END rw0_wd_in[687] + PIN rw0_wd_in[688] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.324 416.048 66.348 ; + END + END rw0_wd_in[688] + PIN rw0_wd_in[689] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.420 416.048 66.444 ; + END + END rw0_wd_in[689] + PIN rw0_wd_in[690] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.516 416.048 66.540 ; + END + END rw0_wd_in[690] + PIN rw0_wd_in[691] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.612 416.048 66.636 ; + END + END rw0_wd_in[691] + PIN rw0_wd_in[692] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.708 416.048 66.732 ; + END + END rw0_wd_in[692] + PIN rw0_wd_in[693] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.804 416.048 66.828 ; + END + END rw0_wd_in[693] + PIN rw0_wd_in[694] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.900 416.048 66.924 ; + END + END rw0_wd_in[694] + PIN rw0_wd_in[695] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 66.996 416.048 67.020 ; + END + END rw0_wd_in[695] + PIN rw0_wd_in[696] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.092 416.048 67.116 ; + END + END rw0_wd_in[696] + PIN rw0_wd_in[697] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.188 416.048 67.212 ; + END + END rw0_wd_in[697] + PIN rw0_wd_in[698] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.284 416.048 67.308 ; + END + END rw0_wd_in[698] + PIN rw0_wd_in[699] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.380 416.048 67.404 ; + END + END rw0_wd_in[699] + PIN rw0_wd_in[700] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.476 416.048 67.500 ; + END + END rw0_wd_in[700] + PIN rw0_wd_in[701] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.572 416.048 67.596 ; + END + END rw0_wd_in[701] + PIN rw0_wd_in[702] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.668 416.048 67.692 ; + END + END rw0_wd_in[702] + PIN rw0_wd_in[703] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.764 416.048 67.788 ; + END + END rw0_wd_in[703] + PIN rw0_wd_in[704] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.860 416.048 67.884 ; + END + END rw0_wd_in[704] + PIN rw0_wd_in[705] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 67.956 416.048 67.980 ; + END + END rw0_wd_in[705] + PIN rw0_wd_in[706] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.052 416.048 68.076 ; + END + END rw0_wd_in[706] + PIN rw0_wd_in[707] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.148 416.048 68.172 ; + END + END rw0_wd_in[707] + PIN rw0_wd_in[708] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.244 416.048 68.268 ; + END + END rw0_wd_in[708] + PIN rw0_wd_in[709] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.340 416.048 68.364 ; + END + END rw0_wd_in[709] + PIN rw0_wd_in[710] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.436 416.048 68.460 ; + END + END rw0_wd_in[710] + PIN rw0_wd_in[711] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.532 416.048 68.556 ; + END + END rw0_wd_in[711] + PIN rw0_wd_in[712] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.628 416.048 68.652 ; + END + END rw0_wd_in[712] + PIN rw0_wd_in[713] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.724 416.048 68.748 ; + END + END rw0_wd_in[713] + PIN rw0_wd_in[714] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.820 416.048 68.844 ; + END + END rw0_wd_in[714] + PIN rw0_wd_in[715] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 68.916 416.048 68.940 ; + END + END rw0_wd_in[715] + PIN rw0_wd_in[716] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.012 416.048 69.036 ; + END + END rw0_wd_in[716] + PIN rw0_wd_in[717] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.108 416.048 69.132 ; + END + END rw0_wd_in[717] + PIN rw0_wd_in[718] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.204 416.048 69.228 ; + END + END rw0_wd_in[718] + PIN rw0_wd_in[719] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.300 416.048 69.324 ; + END + END rw0_wd_in[719] + PIN rw0_wd_in[720] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.396 416.048 69.420 ; + END + END rw0_wd_in[720] + PIN rw0_wd_in[721] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.492 416.048 69.516 ; + END + END rw0_wd_in[721] + PIN rw0_wd_in[722] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.588 416.048 69.612 ; + END + END rw0_wd_in[722] + PIN rw0_wd_in[723] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.684 416.048 69.708 ; + END + END rw0_wd_in[723] + PIN rw0_wd_in[724] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.780 416.048 69.804 ; + END + END rw0_wd_in[724] + PIN rw0_wd_in[725] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.876 416.048 69.900 ; + END + END rw0_wd_in[725] + PIN rw0_wd_in[726] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 69.972 416.048 69.996 ; + END + END rw0_wd_in[726] + PIN rw0_wd_in[727] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.068 416.048 70.092 ; + END + END rw0_wd_in[727] + PIN rw0_wd_in[728] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.164 416.048 70.188 ; + END + END rw0_wd_in[728] + PIN rw0_wd_in[729] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.260 416.048 70.284 ; + END + END rw0_wd_in[729] + PIN rw0_wd_in[730] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.356 416.048 70.380 ; + END + END rw0_wd_in[730] + PIN rw0_wd_in[731] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.452 416.048 70.476 ; + END + END rw0_wd_in[731] + PIN rw0_wd_in[732] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.548 416.048 70.572 ; + END + END rw0_wd_in[732] + PIN rw0_wd_in[733] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.644 416.048 70.668 ; + END + END rw0_wd_in[733] + PIN rw0_wd_in[734] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.740 416.048 70.764 ; + END + END rw0_wd_in[734] + PIN rw0_wd_in[735] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.836 416.048 70.860 ; + END + END rw0_wd_in[735] + PIN rw0_wd_in[736] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 70.932 416.048 70.956 ; + END + END rw0_wd_in[736] + PIN rw0_wd_in[737] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.028 416.048 71.052 ; + END + END rw0_wd_in[737] + PIN rw0_wd_in[738] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.124 416.048 71.148 ; + END + END rw0_wd_in[738] + PIN rw0_wd_in[739] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.220 416.048 71.244 ; + END + END rw0_wd_in[739] + PIN rw0_wd_in[740] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.316 416.048 71.340 ; + END + END rw0_wd_in[740] + PIN rw0_wd_in[741] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.412 416.048 71.436 ; + END + END rw0_wd_in[741] + PIN rw0_wd_in[742] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.508 416.048 71.532 ; + END + END rw0_wd_in[742] + PIN rw0_wd_in[743] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.604 416.048 71.628 ; + END + END rw0_wd_in[743] + PIN rw0_wd_in[744] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.700 416.048 71.724 ; + END + END rw0_wd_in[744] + PIN rw0_wd_in[745] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.796 416.048 71.820 ; + END + END rw0_wd_in[745] + PIN rw0_wd_in[746] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.892 416.048 71.916 ; + END + END rw0_wd_in[746] + PIN rw0_wd_in[747] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 71.988 416.048 72.012 ; + END + END rw0_wd_in[747] + PIN rw0_wd_in[748] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.084 416.048 72.108 ; + END + END rw0_wd_in[748] + PIN rw0_wd_in[749] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.180 416.048 72.204 ; + END + END rw0_wd_in[749] + PIN rw0_wd_in[750] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.276 416.048 72.300 ; + END + END rw0_wd_in[750] + PIN rw0_wd_in[751] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.372 416.048 72.396 ; + END + END rw0_wd_in[751] + PIN rw0_wd_in[752] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.468 416.048 72.492 ; + END + END rw0_wd_in[752] + PIN rw0_wd_in[753] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.564 416.048 72.588 ; + END + END rw0_wd_in[753] + PIN rw0_wd_in[754] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.660 416.048 72.684 ; + END + END rw0_wd_in[754] + PIN rw0_wd_in[755] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.756 416.048 72.780 ; + END + END rw0_wd_in[755] + PIN rw0_wd_in[756] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.852 416.048 72.876 ; + END + END rw0_wd_in[756] + PIN rw0_wd_in[757] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 72.948 416.048 72.972 ; + END + END rw0_wd_in[757] + PIN rw0_wd_in[758] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.044 416.048 73.068 ; + END + END rw0_wd_in[758] + PIN rw0_wd_in[759] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.140 416.048 73.164 ; + END + END rw0_wd_in[759] + PIN rw0_wd_in[760] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.236 416.048 73.260 ; + END + END rw0_wd_in[760] + PIN rw0_wd_in[761] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.332 416.048 73.356 ; + END + END rw0_wd_in[761] + PIN rw0_wd_in[762] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.428 416.048 73.452 ; + END + END rw0_wd_in[762] + PIN rw0_wd_in[763] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.524 416.048 73.548 ; + END + END rw0_wd_in[763] + PIN rw0_wd_in[764] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.620 416.048 73.644 ; + END + END rw0_wd_in[764] + PIN rw0_wd_in[765] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.716 416.048 73.740 ; + END + END rw0_wd_in[765] + PIN rw0_wd_in[766] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.812 416.048 73.836 ; + END + END rw0_wd_in[766] + PIN rw0_wd_in[767] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 73.908 416.048 73.932 ; + END + END rw0_wd_in[767] + PIN rw0_wd_in[768] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.004 416.048 74.028 ; + END + END rw0_wd_in[768] + PIN rw0_wd_in[769] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.100 416.048 74.124 ; + END + END rw0_wd_in[769] + PIN rw0_wd_in[770] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.196 416.048 74.220 ; + END + END rw0_wd_in[770] + PIN rw0_wd_in[771] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.292 416.048 74.316 ; + END + END rw0_wd_in[771] + PIN rw0_wd_in[772] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.388 416.048 74.412 ; + END + END rw0_wd_in[772] + PIN rw0_wd_in[773] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.484 416.048 74.508 ; + END + END rw0_wd_in[773] + PIN rw0_wd_in[774] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.580 416.048 74.604 ; + END + END rw0_wd_in[774] + PIN rw0_wd_in[775] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.676 416.048 74.700 ; + END + END rw0_wd_in[775] + PIN rw0_wd_in[776] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.772 416.048 74.796 ; + END + END rw0_wd_in[776] + PIN rw0_wd_in[777] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.868 416.048 74.892 ; + END + END rw0_wd_in[777] + PIN rw0_wd_in[778] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 74.964 416.048 74.988 ; + END + END rw0_wd_in[778] + PIN rw0_wd_in[779] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.060 416.048 75.084 ; + END + END rw0_wd_in[779] + PIN rw0_wd_in[780] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.156 416.048 75.180 ; + END + END rw0_wd_in[780] + PIN rw0_wd_in[781] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.252 416.048 75.276 ; + END + END rw0_wd_in[781] + PIN rw0_wd_in[782] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.348 416.048 75.372 ; + END + END rw0_wd_in[782] + PIN rw0_wd_in[783] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.444 416.048 75.468 ; + END + END rw0_wd_in[783] + PIN rw0_wd_in[784] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.540 416.048 75.564 ; + END + END rw0_wd_in[784] + PIN rw0_wd_in[785] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.636 416.048 75.660 ; + END + END rw0_wd_in[785] + PIN rw0_wd_in[786] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.732 416.048 75.756 ; + END + END rw0_wd_in[786] + PIN rw0_wd_in[787] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.828 416.048 75.852 ; + END + END rw0_wd_in[787] + PIN rw0_wd_in[788] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 75.924 416.048 75.948 ; + END + END rw0_wd_in[788] + PIN rw0_wd_in[789] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.020 416.048 76.044 ; + END + END rw0_wd_in[789] + PIN rw0_wd_in[790] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.116 416.048 76.140 ; + END + END rw0_wd_in[790] + PIN rw0_wd_in[791] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.212 416.048 76.236 ; + END + END rw0_wd_in[791] + PIN rw0_wd_in[792] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.308 416.048 76.332 ; + END + END rw0_wd_in[792] + PIN rw0_wd_in[793] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.404 416.048 76.428 ; + END + END rw0_wd_in[793] + PIN rw0_wd_in[794] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.500 416.048 76.524 ; + END + END rw0_wd_in[794] + PIN rw0_wd_in[795] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.596 416.048 76.620 ; + END + END rw0_wd_in[795] + PIN rw0_wd_in[796] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.692 416.048 76.716 ; + END + END rw0_wd_in[796] + PIN rw0_wd_in[797] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.788 416.048 76.812 ; + END + END rw0_wd_in[797] + PIN rw0_wd_in[798] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.884 416.048 76.908 ; + END + END rw0_wd_in[798] + PIN rw0_wd_in[799] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 76.980 416.048 77.004 ; + END + END rw0_wd_in[799] + PIN rw0_wd_in[800] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.076 416.048 77.100 ; + END + END rw0_wd_in[800] + PIN rw0_wd_in[801] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.172 416.048 77.196 ; + END + END rw0_wd_in[801] + PIN rw0_wd_in[802] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.268 416.048 77.292 ; + END + END rw0_wd_in[802] + PIN rw0_wd_in[803] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.364 416.048 77.388 ; + END + END rw0_wd_in[803] + PIN rw0_wd_in[804] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.460 416.048 77.484 ; + END + END rw0_wd_in[804] + PIN rw0_wd_in[805] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.556 416.048 77.580 ; + END + END rw0_wd_in[805] + PIN rw0_wd_in[806] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.652 416.048 77.676 ; + END + END rw0_wd_in[806] + PIN rw0_wd_in[807] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.748 416.048 77.772 ; + END + END rw0_wd_in[807] + PIN rw0_wd_in[808] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.844 416.048 77.868 ; + END + END rw0_wd_in[808] + PIN rw0_wd_in[809] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 77.940 416.048 77.964 ; + END + END rw0_wd_in[809] + PIN rw0_wd_in[810] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.036 416.048 78.060 ; + END + END rw0_wd_in[810] + PIN rw0_wd_in[811] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.132 416.048 78.156 ; + END + END rw0_wd_in[811] + PIN rw0_wd_in[812] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.228 416.048 78.252 ; + END + END rw0_wd_in[812] + PIN rw0_wd_in[813] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.324 416.048 78.348 ; + END + END rw0_wd_in[813] + PIN rw0_wd_in[814] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.420 416.048 78.444 ; + END + END rw0_wd_in[814] + PIN rw0_wd_in[815] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.516 416.048 78.540 ; + END + END rw0_wd_in[815] + PIN rw0_wd_in[816] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.612 416.048 78.636 ; + END + END rw0_wd_in[816] + PIN rw0_wd_in[817] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.708 416.048 78.732 ; + END + END rw0_wd_in[817] + PIN rw0_wd_in[818] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.804 416.048 78.828 ; + END + END rw0_wd_in[818] + PIN rw0_wd_in[819] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.900 416.048 78.924 ; + END + END rw0_wd_in[819] + PIN rw0_wd_in[820] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 78.996 416.048 79.020 ; + END + END rw0_wd_in[820] + PIN rw0_wd_in[821] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.092 416.048 79.116 ; + END + END rw0_wd_in[821] + PIN rw0_wd_in[822] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.188 416.048 79.212 ; + END + END rw0_wd_in[822] + PIN rw0_wd_in[823] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.284 416.048 79.308 ; + END + END rw0_wd_in[823] + PIN rw0_wd_in[824] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.380 416.048 79.404 ; + END + END rw0_wd_in[824] + PIN rw0_wd_in[825] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.476 416.048 79.500 ; + END + END rw0_wd_in[825] + PIN rw0_wd_in[826] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.572 416.048 79.596 ; + END + END rw0_wd_in[826] + PIN rw0_wd_in[827] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.668 416.048 79.692 ; + END + END rw0_wd_in[827] + PIN rw0_wd_in[828] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.764 416.048 79.788 ; + END + END rw0_wd_in[828] + PIN rw0_wd_in[829] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.860 416.048 79.884 ; + END + END rw0_wd_in[829] + PIN rw0_wd_in[830] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 79.956 416.048 79.980 ; + END + END rw0_wd_in[830] + PIN rw0_wd_in[831] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.052 416.048 80.076 ; + END + END rw0_wd_in[831] + PIN rw0_wd_in[832] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.148 416.048 80.172 ; + END + END rw0_wd_in[832] + PIN rw0_wd_in[833] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.244 416.048 80.268 ; + END + END rw0_wd_in[833] + PIN rw0_wd_in[834] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.340 416.048 80.364 ; + END + END rw0_wd_in[834] + PIN rw0_wd_in[835] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.436 416.048 80.460 ; + END + END rw0_wd_in[835] + PIN rw0_wd_in[836] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.532 416.048 80.556 ; + END + END rw0_wd_in[836] + PIN rw0_wd_in[837] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.628 416.048 80.652 ; + END + END rw0_wd_in[837] + PIN rw0_wd_in[838] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.724 416.048 80.748 ; + END + END rw0_wd_in[838] + PIN rw0_wd_in[839] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.820 416.048 80.844 ; + END + END rw0_wd_in[839] + PIN rw0_wd_in[840] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 80.916 416.048 80.940 ; + END + END rw0_wd_in[840] + PIN rw0_wd_in[841] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.012 416.048 81.036 ; + END + END rw0_wd_in[841] + PIN rw0_wd_in[842] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.108 416.048 81.132 ; + END + END rw0_wd_in[842] + PIN rw0_wd_in[843] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.204 416.048 81.228 ; + END + END rw0_wd_in[843] + PIN rw0_wd_in[844] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.300 416.048 81.324 ; + END + END rw0_wd_in[844] + PIN rw0_wd_in[845] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.396 416.048 81.420 ; + END + END rw0_wd_in[845] + PIN rw0_wd_in[846] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.492 416.048 81.516 ; + END + END rw0_wd_in[846] + PIN rw0_wd_in[847] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.588 416.048 81.612 ; + END + END rw0_wd_in[847] + PIN rw0_wd_in[848] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.684 416.048 81.708 ; + END + END rw0_wd_in[848] + PIN rw0_wd_in[849] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.780 416.048 81.804 ; + END + END rw0_wd_in[849] + PIN rw0_wd_in[850] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.876 416.048 81.900 ; + END + END rw0_wd_in[850] + PIN rw0_wd_in[851] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 81.972 416.048 81.996 ; + END + END rw0_wd_in[851] + PIN rw0_wd_in[852] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.068 416.048 82.092 ; + END + END rw0_wd_in[852] + PIN rw0_wd_in[853] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.164 416.048 82.188 ; + END + END rw0_wd_in[853] + PIN rw0_wd_in[854] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.260 416.048 82.284 ; + END + END rw0_wd_in[854] + PIN rw0_wd_in[855] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.356 416.048 82.380 ; + END + END rw0_wd_in[855] + PIN rw0_wd_in[856] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.452 416.048 82.476 ; + END + END rw0_wd_in[856] + PIN rw0_wd_in[857] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.548 416.048 82.572 ; + END + END rw0_wd_in[857] + PIN rw0_wd_in[858] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.644 416.048 82.668 ; + END + END rw0_wd_in[858] + PIN rw0_wd_in[859] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.740 416.048 82.764 ; + END + END rw0_wd_in[859] + PIN rw0_wd_in[860] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.836 416.048 82.860 ; + END + END rw0_wd_in[860] + PIN rw0_wd_in[861] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 82.932 416.048 82.956 ; + END + END rw0_wd_in[861] + PIN rw0_wd_in[862] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.028 416.048 83.052 ; + END + END rw0_wd_in[862] + PIN rw0_wd_in[863] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.124 416.048 83.148 ; + END + END rw0_wd_in[863] + PIN rw0_wd_in[864] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.220 416.048 83.244 ; + END + END rw0_wd_in[864] + PIN rw0_wd_in[865] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.316 416.048 83.340 ; + END + END rw0_wd_in[865] + PIN rw0_wd_in[866] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.412 416.048 83.436 ; + END + END rw0_wd_in[866] + PIN rw0_wd_in[867] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.508 416.048 83.532 ; + END + END rw0_wd_in[867] + PIN rw0_wd_in[868] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.604 416.048 83.628 ; + END + END rw0_wd_in[868] + PIN rw0_wd_in[869] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.700 416.048 83.724 ; + END + END rw0_wd_in[869] + PIN rw0_wd_in[870] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.796 416.048 83.820 ; + END + END rw0_wd_in[870] + PIN rw0_wd_in[871] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.892 416.048 83.916 ; + END + END rw0_wd_in[871] + PIN rw0_wd_in[872] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 83.988 416.048 84.012 ; + END + END rw0_wd_in[872] + PIN rw0_wd_in[873] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.084 416.048 84.108 ; + END + END rw0_wd_in[873] + PIN rw0_wd_in[874] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.180 416.048 84.204 ; + END + END rw0_wd_in[874] + PIN rw0_wd_in[875] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.276 416.048 84.300 ; + END + END rw0_wd_in[875] + PIN rw0_wd_in[876] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.372 416.048 84.396 ; + END + END rw0_wd_in[876] + PIN rw0_wd_in[877] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.468 416.048 84.492 ; + END + END rw0_wd_in[877] + PIN rw0_wd_in[878] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.564 416.048 84.588 ; + END + END rw0_wd_in[878] + PIN rw0_wd_in[879] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.660 416.048 84.684 ; + END + END rw0_wd_in[879] + PIN rw0_wd_in[880] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.756 416.048 84.780 ; + END + END rw0_wd_in[880] + PIN rw0_wd_in[881] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.852 416.048 84.876 ; + END + END rw0_wd_in[881] + PIN rw0_wd_in[882] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 84.948 416.048 84.972 ; + END + END rw0_wd_in[882] + PIN rw0_wd_in[883] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.044 416.048 85.068 ; + END + END rw0_wd_in[883] + PIN rw0_wd_in[884] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.140 416.048 85.164 ; + END + END rw0_wd_in[884] + PIN rw0_wd_in[885] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.236 416.048 85.260 ; + END + END rw0_wd_in[885] + PIN rw0_wd_in[886] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.332 416.048 85.356 ; + END + END rw0_wd_in[886] + PIN rw0_wd_in[887] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.428 416.048 85.452 ; + END + END rw0_wd_in[887] + PIN rw0_wd_in[888] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.524 416.048 85.548 ; + END + END rw0_wd_in[888] + PIN rw0_wd_in[889] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.620 416.048 85.644 ; + END + END rw0_wd_in[889] + PIN rw0_wd_in[890] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.716 416.048 85.740 ; + END + END rw0_wd_in[890] + PIN rw0_wd_in[891] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.812 416.048 85.836 ; + END + END rw0_wd_in[891] + PIN rw0_wd_in[892] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 85.908 416.048 85.932 ; + END + END rw0_wd_in[892] + PIN rw0_wd_in[893] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.004 416.048 86.028 ; + END + END rw0_wd_in[893] + PIN rw0_wd_in[894] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.100 416.048 86.124 ; + END + END rw0_wd_in[894] + PIN rw0_wd_in[895] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.196 416.048 86.220 ; + END + END rw0_wd_in[895] + PIN rw0_wd_in[896] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.292 416.048 86.316 ; + END + END rw0_wd_in[896] + PIN rw0_wd_in[897] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.388 416.048 86.412 ; + END + END rw0_wd_in[897] + PIN rw0_wd_in[898] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.484 416.048 86.508 ; + END + END rw0_wd_in[898] + PIN rw0_wd_in[899] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.580 416.048 86.604 ; + END + END rw0_wd_in[899] + PIN rw0_wd_in[900] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.676 416.048 86.700 ; + END + END rw0_wd_in[900] + PIN rw0_wd_in[901] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.772 416.048 86.796 ; + END + END rw0_wd_in[901] + PIN rw0_wd_in[902] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.868 416.048 86.892 ; + END + END rw0_wd_in[902] + PIN rw0_wd_in[903] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 86.964 416.048 86.988 ; + END + END rw0_wd_in[903] + PIN rw0_wd_in[904] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.060 416.048 87.084 ; + END + END rw0_wd_in[904] + PIN rw0_wd_in[905] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.156 416.048 87.180 ; + END + END rw0_wd_in[905] + PIN rw0_wd_in[906] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.252 416.048 87.276 ; + END + END rw0_wd_in[906] + PIN rw0_wd_in[907] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.348 416.048 87.372 ; + END + END rw0_wd_in[907] + PIN rw0_wd_in[908] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.444 416.048 87.468 ; + END + END rw0_wd_in[908] + PIN rw0_wd_in[909] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.540 416.048 87.564 ; + END + END rw0_wd_in[909] + PIN rw0_wd_in[910] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.636 416.048 87.660 ; + END + END rw0_wd_in[910] + PIN rw0_wd_in[911] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.732 416.048 87.756 ; + END + END rw0_wd_in[911] + PIN rw0_wd_in[912] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.828 416.048 87.852 ; + END + END rw0_wd_in[912] + PIN rw0_wd_in[913] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 87.924 416.048 87.948 ; + END + END rw0_wd_in[913] + PIN rw0_wd_in[914] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.020 416.048 88.044 ; + END + END rw0_wd_in[914] + PIN rw0_wd_in[915] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.116 416.048 88.140 ; + END + END rw0_wd_in[915] + PIN rw0_wd_in[916] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.212 416.048 88.236 ; + END + END rw0_wd_in[916] + PIN rw0_wd_in[917] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.308 416.048 88.332 ; + END + END rw0_wd_in[917] + PIN rw0_wd_in[918] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.404 416.048 88.428 ; + END + END rw0_wd_in[918] + PIN rw0_wd_in[919] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.500 416.048 88.524 ; + END + END rw0_wd_in[919] + PIN rw0_wd_in[920] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.596 416.048 88.620 ; + END + END rw0_wd_in[920] + PIN rw0_wd_in[921] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.692 416.048 88.716 ; + END + END rw0_wd_in[921] + PIN rw0_wd_in[922] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.788 416.048 88.812 ; + END + END rw0_wd_in[922] + PIN rw0_wd_in[923] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.884 416.048 88.908 ; + END + END rw0_wd_in[923] + PIN rw0_wd_in[924] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 88.980 416.048 89.004 ; + END + END rw0_wd_in[924] + PIN rw0_wd_in[925] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.076 416.048 89.100 ; + END + END rw0_wd_in[925] + PIN rw0_wd_in[926] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.172 416.048 89.196 ; + END + END rw0_wd_in[926] + PIN rw0_wd_in[927] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.268 416.048 89.292 ; + END + END rw0_wd_in[927] + PIN rw0_wd_in[928] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.364 416.048 89.388 ; + END + END rw0_wd_in[928] + PIN rw0_wd_in[929] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.460 416.048 89.484 ; + END + END rw0_wd_in[929] + PIN rw0_wd_in[930] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.556 416.048 89.580 ; + END + END rw0_wd_in[930] + PIN rw0_wd_in[931] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.652 416.048 89.676 ; + END + END rw0_wd_in[931] + PIN rw0_wd_in[932] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.748 416.048 89.772 ; + END + END rw0_wd_in[932] + PIN rw0_wd_in[933] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.844 416.048 89.868 ; + END + END rw0_wd_in[933] + PIN rw0_wd_in[934] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 89.940 416.048 89.964 ; + END + END rw0_wd_in[934] + PIN rw0_wd_in[935] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.036 416.048 90.060 ; + END + END rw0_wd_in[935] + PIN rw0_wd_in[936] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.132 416.048 90.156 ; + END + END rw0_wd_in[936] + PIN rw0_wd_in[937] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.228 416.048 90.252 ; + END + END rw0_wd_in[937] + PIN rw0_wd_in[938] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.324 416.048 90.348 ; + END + END rw0_wd_in[938] + PIN rw0_wd_in[939] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.420 416.048 90.444 ; + END + END rw0_wd_in[939] + PIN rw0_wd_in[940] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.516 416.048 90.540 ; + END + END rw0_wd_in[940] + PIN rw0_wd_in[941] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.612 416.048 90.636 ; + END + END rw0_wd_in[941] + PIN rw0_wd_in[942] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.708 416.048 90.732 ; + END + END rw0_wd_in[942] + PIN rw0_wd_in[943] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.804 416.048 90.828 ; + END + END rw0_wd_in[943] + PIN rw0_wd_in[944] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.900 416.048 90.924 ; + END + END rw0_wd_in[944] + PIN rw0_wd_in[945] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 90.996 416.048 91.020 ; + END + END rw0_wd_in[945] + PIN rw0_wd_in[946] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.092 416.048 91.116 ; + END + END rw0_wd_in[946] + PIN rw0_wd_in[947] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.188 416.048 91.212 ; + END + END rw0_wd_in[947] + PIN rw0_wd_in[948] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.284 416.048 91.308 ; + END + END rw0_wd_in[948] + PIN rw0_wd_in[949] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.380 416.048 91.404 ; + END + END rw0_wd_in[949] + PIN rw0_wd_in[950] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.476 416.048 91.500 ; + END + END rw0_wd_in[950] + PIN rw0_wd_in[951] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.572 416.048 91.596 ; + END + END rw0_wd_in[951] + PIN rw0_wd_in[952] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.668 416.048 91.692 ; + END + END rw0_wd_in[952] + PIN rw0_wd_in[953] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.764 416.048 91.788 ; + END + END rw0_wd_in[953] + PIN rw0_wd_in[954] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.860 416.048 91.884 ; + END + END rw0_wd_in[954] + PIN rw0_wd_in[955] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 91.956 416.048 91.980 ; + END + END rw0_wd_in[955] + PIN rw0_wd_in[956] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.052 416.048 92.076 ; + END + END rw0_wd_in[956] + PIN rw0_wd_in[957] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.148 416.048 92.172 ; + END + END rw0_wd_in[957] + PIN rw0_wd_in[958] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.244 416.048 92.268 ; + END + END rw0_wd_in[958] + PIN rw0_wd_in[959] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.340 416.048 92.364 ; + END + END rw0_wd_in[959] + PIN rw0_wd_in[960] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.436 416.048 92.460 ; + END + END rw0_wd_in[960] + PIN rw0_wd_in[961] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.532 416.048 92.556 ; + END + END rw0_wd_in[961] + PIN rw0_wd_in[962] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.628 416.048 92.652 ; + END + END rw0_wd_in[962] + PIN rw0_wd_in[963] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.724 416.048 92.748 ; + END + END rw0_wd_in[963] + PIN rw0_wd_in[964] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.820 416.048 92.844 ; + END + END rw0_wd_in[964] + PIN rw0_wd_in[965] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 92.916 416.048 92.940 ; + END + END rw0_wd_in[965] + PIN rw0_wd_in[966] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.012 416.048 93.036 ; + END + END rw0_wd_in[966] + PIN rw0_wd_in[967] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.108 416.048 93.132 ; + END + END rw0_wd_in[967] + PIN rw0_wd_in[968] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.204 416.048 93.228 ; + END + END rw0_wd_in[968] + PIN rw0_wd_in[969] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.300 416.048 93.324 ; + END + END rw0_wd_in[969] + PIN rw0_wd_in[970] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.396 416.048 93.420 ; + END + END rw0_wd_in[970] + PIN rw0_wd_in[971] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.492 416.048 93.516 ; + END + END rw0_wd_in[971] + PIN rw0_wd_in[972] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.588 416.048 93.612 ; + END + END rw0_wd_in[972] + PIN rw0_wd_in[973] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.684 416.048 93.708 ; + END + END rw0_wd_in[973] + PIN rw0_wd_in[974] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.780 416.048 93.804 ; + END + END rw0_wd_in[974] + PIN rw0_wd_in[975] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.876 416.048 93.900 ; + END + END rw0_wd_in[975] + PIN rw0_wd_in[976] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 93.972 416.048 93.996 ; + END + END rw0_wd_in[976] + PIN rw0_wd_in[977] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.068 416.048 94.092 ; + END + END rw0_wd_in[977] + PIN rw0_wd_in[978] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.164 416.048 94.188 ; + END + END rw0_wd_in[978] + PIN rw0_wd_in[979] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.260 416.048 94.284 ; + END + END rw0_wd_in[979] + PIN rw0_wd_in[980] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.356 416.048 94.380 ; + END + END rw0_wd_in[980] + PIN rw0_wd_in[981] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.452 416.048 94.476 ; + END + END rw0_wd_in[981] + PIN rw0_wd_in[982] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.548 416.048 94.572 ; + END + END rw0_wd_in[982] + PIN rw0_wd_in[983] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.644 416.048 94.668 ; + END + END rw0_wd_in[983] + PIN rw0_wd_in[984] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.740 416.048 94.764 ; + END + END rw0_wd_in[984] + PIN rw0_wd_in[985] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.836 416.048 94.860 ; + END + END rw0_wd_in[985] + PIN rw0_wd_in[986] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 94.932 416.048 94.956 ; + END + END rw0_wd_in[986] + PIN rw0_wd_in[987] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.028 416.048 95.052 ; + END + END rw0_wd_in[987] + PIN rw0_wd_in[988] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.124 416.048 95.148 ; + END + END rw0_wd_in[988] + PIN rw0_wd_in[989] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.220 416.048 95.244 ; + END + END rw0_wd_in[989] + PIN rw0_wd_in[990] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.316 416.048 95.340 ; + END + END rw0_wd_in[990] + PIN rw0_wd_in[991] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.412 416.048 95.436 ; + END + END rw0_wd_in[991] + PIN rw0_wd_in[992] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.508 416.048 95.532 ; + END + END rw0_wd_in[992] + PIN rw0_wd_in[993] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.604 416.048 95.628 ; + END + END rw0_wd_in[993] + PIN rw0_wd_in[994] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.700 416.048 95.724 ; + END + END rw0_wd_in[994] + PIN rw0_wd_in[995] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.796 416.048 95.820 ; + END + END rw0_wd_in[995] + PIN rw0_wd_in[996] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.892 416.048 95.916 ; + END + END rw0_wd_in[996] + PIN rw0_wd_in[997] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 95.988 416.048 96.012 ; + END + END rw0_wd_in[997] + PIN rw0_wd_in[998] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.084 416.048 96.108 ; + END + END rw0_wd_in[998] + PIN rw0_wd_in[999] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.180 416.048 96.204 ; + END + END rw0_wd_in[999] + PIN rw0_wd_in[1000] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.276 416.048 96.300 ; + END + END rw0_wd_in[1000] + PIN rw0_wd_in[1001] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.372 416.048 96.396 ; + END + END rw0_wd_in[1001] + PIN rw0_wd_in[1002] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.468 416.048 96.492 ; + END + END rw0_wd_in[1002] + PIN rw0_wd_in[1003] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.564 416.048 96.588 ; + END + END rw0_wd_in[1003] + PIN rw0_wd_in[1004] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.660 416.048 96.684 ; + END + END rw0_wd_in[1004] + PIN rw0_wd_in[1005] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.756 416.048 96.780 ; + END + END rw0_wd_in[1005] + PIN rw0_wd_in[1006] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.852 416.048 96.876 ; + END + END rw0_wd_in[1006] + PIN rw0_wd_in[1007] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 96.948 416.048 96.972 ; + END + END rw0_wd_in[1007] + PIN rw0_wd_in[1008] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.044 416.048 97.068 ; + END + END rw0_wd_in[1008] + PIN rw0_wd_in[1009] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.140 416.048 97.164 ; + END + END rw0_wd_in[1009] + PIN rw0_wd_in[1010] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.236 416.048 97.260 ; + END + END rw0_wd_in[1010] + PIN rw0_wd_in[1011] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.332 416.048 97.356 ; + END + END rw0_wd_in[1011] + PIN rw0_wd_in[1012] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.428 416.048 97.452 ; + END + END rw0_wd_in[1012] + PIN rw0_wd_in[1013] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.524 416.048 97.548 ; + END + END rw0_wd_in[1013] + PIN rw0_wd_in[1014] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.620 416.048 97.644 ; + END + END rw0_wd_in[1014] + PIN rw0_wd_in[1015] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.716 416.048 97.740 ; + END + END rw0_wd_in[1015] + PIN rw0_wd_in[1016] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.812 416.048 97.836 ; + END + END rw0_wd_in[1016] + PIN rw0_wd_in[1017] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 97.908 416.048 97.932 ; + END + END rw0_wd_in[1017] + PIN rw0_wd_in[1018] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.004 416.048 98.028 ; + END + END rw0_wd_in[1018] + PIN rw0_wd_in[1019] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.100 416.048 98.124 ; + END + END rw0_wd_in[1019] + PIN rw0_wd_in[1020] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.196 416.048 98.220 ; + END + END rw0_wd_in[1020] + PIN rw0_wd_in[1021] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.292 416.048 98.316 ; + END + END rw0_wd_in[1021] + PIN rw0_wd_in[1022] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.388 416.048 98.412 ; + END + END rw0_wd_in[1022] + PIN rw0_wd_in[1023] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.484 416.048 98.508 ; + END + END rw0_wd_in[1023] + PIN rw0_wd_in[1024] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END rw0_wd_in[1024] + PIN rw0_wd_in[1025] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 0.000 0.405 0.054 ; + END + END rw0_wd_in[1025] + PIN rw0_wd_in[1026] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 0.000 0.585 0.054 ; + END + END rw0_wd_in[1026] + PIN rw0_wd_in[1027] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END rw0_wd_in[1027] + PIN rw0_wd_in[1028] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 0.000 0.945 0.054 ; + END + END rw0_wd_in[1028] + PIN rw0_wd_in[1029] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END rw0_wd_in[1029] + PIN rw0_wd_in[1030] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END rw0_wd_in[1030] + PIN rw0_wd_in[1031] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 0.000 1.485 0.054 ; + END + END rw0_wd_in[1031] + PIN rw0_wd_in[1032] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END rw0_wd_in[1032] + PIN rw0_wd_in[1033] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END rw0_wd_in[1033] + PIN rw0_wd_in[1034] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END rw0_wd_in[1034] + PIN rw0_wd_in[1035] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 0.000 2.205 0.054 ; + END + END rw0_wd_in[1035] + PIN rw0_wd_in[1036] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END rw0_wd_in[1036] + PIN rw0_wd_in[1037] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 0.000 2.565 0.054 ; + END + END rw0_wd_in[1037] + PIN rw0_wd_in[1038] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END rw0_wd_in[1038] + PIN rw0_wd_in[1039] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END rw0_wd_in[1039] + PIN rw0_wd_in[1040] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END rw0_wd_in[1040] + PIN rw0_wd_in[1041] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 0.000 3.285 0.054 ; + END + END rw0_wd_in[1041] + PIN rw0_wd_in[1042] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END rw0_wd_in[1042] + PIN rw0_wd_in[1043] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 0.000 3.645 0.054 ; + END + END rw0_wd_in[1043] + PIN rw0_wd_in[1044] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END rw0_wd_in[1044] + PIN rw0_wd_in[1045] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END rw0_wd_in[1045] + PIN rw0_wd_in[1046] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 0.000 4.185 0.054 ; + END + END rw0_wd_in[1046] + PIN rw0_wd_in[1047] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 0.000 4.365 0.054 ; + END + END rw0_wd_in[1047] + PIN rw0_wd_in[1048] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END rw0_wd_in[1048] + PIN rw0_wd_in[1049] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END rw0_wd_in[1049] + PIN rw0_wd_in[1050] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 0.000 4.905 0.054 ; + END + END rw0_wd_in[1050] + PIN rw0_wd_in[1051] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END rw0_wd_in[1051] + PIN rw0_wd_in[1052] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END rw0_wd_in[1052] + PIN rw0_wd_in[1053] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 0.000 5.445 0.054 ; + END + END rw0_wd_in[1053] + PIN rw0_wd_in[1054] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END rw0_wd_in[1054] + PIN rw0_wd_in[1055] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END rw0_wd_in[1055] + PIN rw0_wd_in[1056] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END rw0_wd_in[1056] + PIN rw0_wd_in[1057] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END rw0_wd_in[1057] + PIN rw0_wd_in[1058] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 0.000 6.345 0.054 ; + END + END rw0_wd_in[1058] + PIN rw0_wd_in[1059] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END rw0_wd_in[1059] + PIN rw0_wd_in[1060] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END rw0_wd_in[1060] + PIN rw0_wd_in[1061] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 0.000 6.885 0.054 ; + END + END rw0_wd_in[1061] + PIN rw0_wd_in[1062] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 0.000 7.065 0.054 ; + END + END rw0_wd_in[1062] + PIN rw0_wd_in[1063] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END rw0_wd_in[1063] + PIN rw0_wd_in[1064] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END rw0_wd_in[1064] + PIN rw0_wd_in[1065] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 0.000 7.605 0.054 ; + END + END rw0_wd_in[1065] + PIN rw0_wd_in[1066] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END rw0_wd_in[1066] + PIN rw0_wd_in[1067] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 0.000 7.965 0.054 ; + END + END rw0_wd_in[1067] + PIN rw0_wd_in[1068] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 0.000 8.145 0.054 ; + END + END rw0_wd_in[1068] + PIN rw0_wd_in[1069] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END rw0_wd_in[1069] + PIN rw0_wd_in[1070] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 0.000 8.505 0.054 ; + END + END rw0_wd_in[1070] + PIN rw0_wd_in[1071] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 0.000 8.685 0.054 ; + END + END rw0_wd_in[1071] + PIN rw0_wd_in[1072] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END rw0_wd_in[1072] + PIN rw0_wd_in[1073] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 0.000 9.045 0.054 ; + END + END rw0_wd_in[1073] + PIN rw0_wd_in[1074] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 0.000 9.225 0.054 ; + END + END rw0_wd_in[1074] + PIN rw0_wd_in[1075] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 0.000 9.405 0.054 ; + END + END rw0_wd_in[1075] + PIN rw0_wd_in[1076] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 0.000 9.585 0.054 ; + END + END rw0_wd_in[1076] + PIN rw0_wd_in[1077] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 0.000 9.765 0.054 ; + END + END rw0_wd_in[1077] + PIN rw0_wd_in[1078] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 0.000 9.945 0.054 ; + END + END rw0_wd_in[1078] + PIN rw0_wd_in[1079] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 0.000 10.125 0.054 ; + END + END rw0_wd_in[1079] + PIN rw0_wd_in[1080] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END rw0_wd_in[1080] + PIN rw0_wd_in[1081] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 0.000 10.485 0.054 ; + END + END rw0_wd_in[1081] + PIN rw0_wd_in[1082] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 0.000 10.665 0.054 ; + END + END rw0_wd_in[1082] + PIN rw0_wd_in[1083] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 0.000 10.845 0.054 ; + END + END rw0_wd_in[1083] + PIN rw0_wd_in[1084] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 0.000 11.025 0.054 ; + END + END rw0_wd_in[1084] + PIN rw0_wd_in[1085] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 0.000 11.205 0.054 ; + END + END rw0_wd_in[1085] + PIN rw0_wd_in[1086] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 0.000 11.385 0.054 ; + END + END rw0_wd_in[1086] + PIN rw0_wd_in[1087] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 0.000 11.565 0.054 ; + END + END rw0_wd_in[1087] + PIN rw0_wd_in[1088] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END rw0_wd_in[1088] + PIN rw0_wd_in[1089] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 0.000 11.925 0.054 ; + END + END rw0_wd_in[1089] + PIN rw0_wd_in[1090] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 0.000 12.105 0.054 ; + END + END rw0_wd_in[1090] + PIN rw0_wd_in[1091] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 0.000 12.285 0.054 ; + END + END rw0_wd_in[1091] + PIN rw0_wd_in[1092] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 0.000 12.465 0.054 ; + END + END rw0_wd_in[1092] + PIN rw0_wd_in[1093] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 0.000 12.645 0.054 ; + END + END rw0_wd_in[1093] + PIN rw0_wd_in[1094] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 0.000 12.825 0.054 ; + END + END rw0_wd_in[1094] + PIN rw0_wd_in[1095] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 0.000 13.005 0.054 ; + END + END rw0_wd_in[1095] + PIN rw0_wd_in[1096] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END rw0_wd_in[1096] + PIN rw0_wd_in[1097] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 0.000 13.365 0.054 ; + END + END rw0_wd_in[1097] + PIN rw0_wd_in[1098] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 0.000 13.545 0.054 ; + END + END rw0_wd_in[1098] + PIN rw0_wd_in[1099] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 0.000 13.725 0.054 ; + END + END rw0_wd_in[1099] + PIN rw0_wd_in[1100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 0.000 13.905 0.054 ; + END + END rw0_wd_in[1100] + PIN rw0_wd_in[1101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 0.000 14.085 0.054 ; + END + END rw0_wd_in[1101] + PIN rw0_wd_in[1102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 0.000 14.265 0.054 ; + END + END rw0_wd_in[1102] + PIN rw0_wd_in[1103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 0.000 14.445 0.054 ; + END + END rw0_wd_in[1103] + PIN rw0_wd_in[1104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END rw0_wd_in[1104] + PIN rw0_wd_in[1105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 0.000 14.805 0.054 ; + END + END rw0_wd_in[1105] + PIN rw0_wd_in[1106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 0.000 14.985 0.054 ; + END + END rw0_wd_in[1106] + PIN rw0_wd_in[1107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 0.000 15.165 0.054 ; + END + END rw0_wd_in[1107] + PIN rw0_wd_in[1108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 0.000 15.345 0.054 ; + END + END rw0_wd_in[1108] + PIN rw0_wd_in[1109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 0.000 15.525 0.054 ; + END + END rw0_wd_in[1109] + PIN rw0_wd_in[1110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 0.000 15.705 0.054 ; + END + END rw0_wd_in[1110] + PIN rw0_wd_in[1111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 0.000 15.885 0.054 ; + END + END rw0_wd_in[1111] + PIN rw0_wd_in[1112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END rw0_wd_in[1112] + PIN rw0_wd_in[1113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 0.000 16.245 0.054 ; + END + END rw0_wd_in[1113] + PIN rw0_wd_in[1114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 0.000 16.425 0.054 ; + END + END rw0_wd_in[1114] + PIN rw0_wd_in[1115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 0.000 16.605 0.054 ; + END + END rw0_wd_in[1115] + PIN rw0_wd_in[1116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 0.000 16.785 0.054 ; + END + END rw0_wd_in[1116] + PIN rw0_wd_in[1117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 0.000 16.965 0.054 ; + END + END rw0_wd_in[1117] + PIN rw0_wd_in[1118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 0.000 17.145 0.054 ; + END + END rw0_wd_in[1118] + PIN rw0_wd_in[1119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 0.000 17.325 0.054 ; + END + END rw0_wd_in[1119] + PIN rw0_wd_in[1120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END rw0_wd_in[1120] + PIN rw0_wd_in[1121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 0.000 17.685 0.054 ; + END + END rw0_wd_in[1121] + PIN rw0_wd_in[1122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 0.000 17.865 0.054 ; + END + END rw0_wd_in[1122] + PIN rw0_wd_in[1123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 0.000 18.045 0.054 ; + END + END rw0_wd_in[1123] + PIN rw0_wd_in[1124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 0.000 18.225 0.054 ; + END + END rw0_wd_in[1124] + PIN rw0_wd_in[1125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 0.000 18.405 0.054 ; + END + END rw0_wd_in[1125] + PIN rw0_wd_in[1126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 0.000 18.585 0.054 ; + END + END rw0_wd_in[1126] + PIN rw0_wd_in[1127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 0.000 18.765 0.054 ; + END + END rw0_wd_in[1127] + PIN rw0_wd_in[1128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END rw0_wd_in[1128] + PIN rw0_wd_in[1129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 0.000 19.125 0.054 ; + END + END rw0_wd_in[1129] + PIN rw0_wd_in[1130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 0.000 19.305 0.054 ; + END + END rw0_wd_in[1130] + PIN rw0_wd_in[1131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 0.000 19.485 0.054 ; + END + END rw0_wd_in[1131] + PIN rw0_wd_in[1132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 0.000 19.665 0.054 ; + END + END rw0_wd_in[1132] + PIN rw0_wd_in[1133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 0.000 19.845 0.054 ; + END + END rw0_wd_in[1133] + PIN rw0_wd_in[1134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 0.000 20.025 0.054 ; + END + END rw0_wd_in[1134] + PIN rw0_wd_in[1135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 0.000 20.205 0.054 ; + END + END rw0_wd_in[1135] + PIN rw0_wd_in[1136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END rw0_wd_in[1136] + PIN rw0_wd_in[1137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 0.000 20.565 0.054 ; + END + END rw0_wd_in[1137] + PIN rw0_wd_in[1138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 0.000 20.745 0.054 ; + END + END rw0_wd_in[1138] + PIN rw0_wd_in[1139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 0.000 20.925 0.054 ; + END + END rw0_wd_in[1139] + PIN rw0_wd_in[1140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 0.000 21.105 0.054 ; + END + END rw0_wd_in[1140] + PIN rw0_wd_in[1141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 0.000 21.285 0.054 ; + END + END rw0_wd_in[1141] + PIN rw0_wd_in[1142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 0.000 21.465 0.054 ; + END + END rw0_wd_in[1142] + PIN rw0_wd_in[1143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 0.000 21.645 0.054 ; + END + END rw0_wd_in[1143] + PIN rw0_wd_in[1144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END rw0_wd_in[1144] + PIN rw0_wd_in[1145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 0.000 22.005 0.054 ; + END + END rw0_wd_in[1145] + PIN rw0_wd_in[1146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 0.000 22.185 0.054 ; + END + END rw0_wd_in[1146] + PIN rw0_wd_in[1147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 0.000 22.365 0.054 ; + END + END rw0_wd_in[1147] + PIN rw0_wd_in[1148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 0.000 22.545 0.054 ; + END + END rw0_wd_in[1148] + PIN rw0_wd_in[1149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 0.000 22.725 0.054 ; + END + END rw0_wd_in[1149] + PIN rw0_wd_in[1150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 0.000 22.905 0.054 ; + END + END rw0_wd_in[1150] + PIN rw0_wd_in[1151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 0.000 23.085 0.054 ; + END + END rw0_wd_in[1151] + PIN rw0_wd_in[1152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END rw0_wd_in[1152] + PIN rw0_wd_in[1153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 0.000 23.445 0.054 ; + END + END rw0_wd_in[1153] + PIN rw0_wd_in[1154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 0.000 23.625 0.054 ; + END + END rw0_wd_in[1154] + PIN rw0_wd_in[1155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.787 0.000 23.805 0.054 ; + END + END rw0_wd_in[1155] + PIN rw0_wd_in[1156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 0.000 23.985 0.054 ; + END + END rw0_wd_in[1156] + PIN rw0_wd_in[1157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.147 0.000 24.165 0.054 ; + END + END rw0_wd_in[1157] + PIN rw0_wd_in[1158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.327 0.000 24.345 0.054 ; + END + END rw0_wd_in[1158] + PIN rw0_wd_in[1159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 0.000 24.525 0.054 ; + END + END rw0_wd_in[1159] + PIN rw0_wd_in[1160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END rw0_wd_in[1160] + PIN rw0_wd_in[1161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.867 0.000 24.885 0.054 ; + END + END rw0_wd_in[1161] + PIN rw0_wd_in[1162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 0.000 25.065 0.054 ; + END + END rw0_wd_in[1162] + PIN rw0_wd_in[1163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.227 0.000 25.245 0.054 ; + END + END rw0_wd_in[1163] + PIN rw0_wd_in[1164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.407 0.000 25.425 0.054 ; + END + END rw0_wd_in[1164] + PIN rw0_wd_in[1165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 0.000 25.605 0.054 ; + END + END rw0_wd_in[1165] + PIN rw0_wd_in[1166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.767 0.000 25.785 0.054 ; + END + END rw0_wd_in[1166] + PIN rw0_wd_in[1167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.947 0.000 25.965 0.054 ; + END + END rw0_wd_in[1167] + PIN rw0_wd_in[1168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END rw0_wd_in[1168] + PIN rw0_wd_in[1169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.307 0.000 26.325 0.054 ; + END + END rw0_wd_in[1169] + PIN rw0_wd_in[1170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.487 0.000 26.505 0.054 ; + END + END rw0_wd_in[1170] + PIN rw0_wd_in[1171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 0.000 26.685 0.054 ; + END + END rw0_wd_in[1171] + PIN rw0_wd_in[1172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.847 0.000 26.865 0.054 ; + END + END rw0_wd_in[1172] + PIN rw0_wd_in[1173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.027 0.000 27.045 0.054 ; + END + END rw0_wd_in[1173] + PIN rw0_wd_in[1174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 0.000 27.225 0.054 ; + END + END rw0_wd_in[1174] + PIN rw0_wd_in[1175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.387 0.000 27.405 0.054 ; + END + END rw0_wd_in[1175] + PIN rw0_wd_in[1176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END rw0_wd_in[1176] + PIN rw0_wd_in[1177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 0.000 27.765 0.054 ; + END + END rw0_wd_in[1177] + PIN rw0_wd_in[1178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.927 0.000 27.945 0.054 ; + END + END rw0_wd_in[1178] + PIN rw0_wd_in[1179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.107 0.000 28.125 0.054 ; + END + END rw0_wd_in[1179] + PIN rw0_wd_in[1180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 0.000 28.305 0.054 ; + END + END rw0_wd_in[1180] + PIN rw0_wd_in[1181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.467 0.000 28.485 0.054 ; + END + END rw0_wd_in[1181] + PIN rw0_wd_in[1182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.647 0.000 28.665 0.054 ; + END + END rw0_wd_in[1182] + PIN rw0_wd_in[1183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 0.000 28.845 0.054 ; + END + END rw0_wd_in[1183] + PIN rw0_wd_in[1184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END rw0_wd_in[1184] + PIN rw0_wd_in[1185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.187 0.000 29.205 0.054 ; + END + END rw0_wd_in[1185] + PIN rw0_wd_in[1186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 0.000 29.385 0.054 ; + END + END rw0_wd_in[1186] + PIN rw0_wd_in[1187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.547 0.000 29.565 0.054 ; + END + END rw0_wd_in[1187] + PIN rw0_wd_in[1188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.727 0.000 29.745 0.054 ; + END + END rw0_wd_in[1188] + PIN rw0_wd_in[1189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 0.000 29.925 0.054 ; + END + END rw0_wd_in[1189] + PIN rw0_wd_in[1190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.087 0.000 30.105 0.054 ; + END + END rw0_wd_in[1190] + PIN rw0_wd_in[1191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.267 0.000 30.285 0.054 ; + END + END rw0_wd_in[1191] + PIN rw0_wd_in[1192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END rw0_wd_in[1192] + PIN rw0_wd_in[1193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.627 0.000 30.645 0.054 ; + END + END rw0_wd_in[1193] + PIN rw0_wd_in[1194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.807 0.000 30.825 0.054 ; + END + END rw0_wd_in[1194] + PIN rw0_wd_in[1195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 0.000 31.005 0.054 ; + END + END rw0_wd_in[1195] + PIN rw0_wd_in[1196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.167 0.000 31.185 0.054 ; + END + END rw0_wd_in[1196] + PIN rw0_wd_in[1197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.347 0.000 31.365 0.054 ; + END + END rw0_wd_in[1197] + PIN rw0_wd_in[1198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 0.000 31.545 0.054 ; + END + END rw0_wd_in[1198] + PIN rw0_wd_in[1199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.707 0.000 31.725 0.054 ; + END + END rw0_wd_in[1199] + PIN rw0_wd_in[1200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END rw0_wd_in[1200] + PIN rw0_wd_in[1201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 0.000 32.085 0.054 ; + END + END rw0_wd_in[1201] + PIN rw0_wd_in[1202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.247 0.000 32.265 0.054 ; + END + END rw0_wd_in[1202] + PIN rw0_wd_in[1203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.427 0.000 32.445 0.054 ; + END + END rw0_wd_in[1203] + PIN rw0_wd_in[1204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 0.000 32.625 0.054 ; + END + END rw0_wd_in[1204] + PIN rw0_wd_in[1205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.787 0.000 32.805 0.054 ; + END + END rw0_wd_in[1205] + PIN rw0_wd_in[1206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.967 0.000 32.985 0.054 ; + END + END rw0_wd_in[1206] + PIN rw0_wd_in[1207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 0.000 33.165 0.054 ; + END + END rw0_wd_in[1207] + PIN rw0_wd_in[1208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END rw0_wd_in[1208] + PIN rw0_wd_in[1209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.507 0.000 33.525 0.054 ; + END + END rw0_wd_in[1209] + PIN rw0_wd_in[1210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 0.000 33.705 0.054 ; + END + END rw0_wd_in[1210] + PIN rw0_wd_in[1211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.867 0.000 33.885 0.054 ; + END + END rw0_wd_in[1211] + PIN rw0_wd_in[1212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.047 0.000 34.065 0.054 ; + END + END rw0_wd_in[1212] + PIN rw0_wd_in[1213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 0.000 34.245 0.054 ; + END + END rw0_wd_in[1213] + PIN rw0_wd_in[1214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.407 0.000 34.425 0.054 ; + END + END rw0_wd_in[1214] + PIN rw0_wd_in[1215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.587 0.000 34.605 0.054 ; + END + END rw0_wd_in[1215] + PIN rw0_wd_in[1216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END rw0_wd_in[1216] + PIN rw0_wd_in[1217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.947 0.000 34.965 0.054 ; + END + END rw0_wd_in[1217] + PIN rw0_wd_in[1218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.127 0.000 35.145 0.054 ; + END + END rw0_wd_in[1218] + PIN rw0_wd_in[1219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 0.000 35.325 0.054 ; + END + END rw0_wd_in[1219] + PIN rw0_wd_in[1220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.487 0.000 35.505 0.054 ; + END + END rw0_wd_in[1220] + PIN rw0_wd_in[1221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.667 0.000 35.685 0.054 ; + END + END rw0_wd_in[1221] + PIN rw0_wd_in[1222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 0.000 35.865 0.054 ; + END + END rw0_wd_in[1222] + PIN rw0_wd_in[1223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.027 0.000 36.045 0.054 ; + END + END rw0_wd_in[1223] + PIN rw0_wd_in[1224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END rw0_wd_in[1224] + PIN rw0_wd_in[1225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 0.000 36.405 0.054 ; + END + END rw0_wd_in[1225] + PIN rw0_wd_in[1226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.567 0.000 36.585 0.054 ; + END + END rw0_wd_in[1226] + PIN rw0_wd_in[1227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.747 0.000 36.765 0.054 ; + END + END rw0_wd_in[1227] + PIN rw0_wd_in[1228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 0.000 36.945 0.054 ; + END + END rw0_wd_in[1228] + PIN rw0_wd_in[1229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.107 0.000 37.125 0.054 ; + END + END rw0_wd_in[1229] + PIN rw0_wd_in[1230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.287 0.000 37.305 0.054 ; + END + END rw0_wd_in[1230] + PIN rw0_wd_in[1231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 0.000 37.485 0.054 ; + END + END rw0_wd_in[1231] + PIN rw0_wd_in[1232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END rw0_wd_in[1232] + PIN rw0_wd_in[1233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.827 0.000 37.845 0.054 ; + END + END rw0_wd_in[1233] + PIN rw0_wd_in[1234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 0.000 38.025 0.054 ; + END + END rw0_wd_in[1234] + PIN rw0_wd_in[1235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.187 0.000 38.205 0.054 ; + END + END rw0_wd_in[1235] + PIN rw0_wd_in[1236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.367 0.000 38.385 0.054 ; + END + END rw0_wd_in[1236] + PIN rw0_wd_in[1237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 0.000 38.565 0.054 ; + END + END rw0_wd_in[1237] + PIN rw0_wd_in[1238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.727 0.000 38.745 0.054 ; + END + END rw0_wd_in[1238] + PIN rw0_wd_in[1239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.907 0.000 38.925 0.054 ; + END + END rw0_wd_in[1239] + PIN rw0_wd_in[1240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END rw0_wd_in[1240] + PIN rw0_wd_in[1241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.267 0.000 39.285 0.054 ; + END + END rw0_wd_in[1241] + PIN rw0_wd_in[1242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.447 0.000 39.465 0.054 ; + END + END rw0_wd_in[1242] + PIN rw0_wd_in[1243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 0.000 39.645 0.054 ; + END + END rw0_wd_in[1243] + PIN rw0_wd_in[1244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.807 0.000 39.825 0.054 ; + END + END rw0_wd_in[1244] + PIN rw0_wd_in[1245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.987 0.000 40.005 0.054 ; + END + END rw0_wd_in[1245] + PIN rw0_wd_in[1246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 0.000 40.185 0.054 ; + END + END rw0_wd_in[1246] + PIN rw0_wd_in[1247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.347 0.000 40.365 0.054 ; + END + END rw0_wd_in[1247] + PIN rw0_wd_in[1248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END rw0_wd_in[1248] + PIN rw0_wd_in[1249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 0.000 40.725 0.054 ; + END + END rw0_wd_in[1249] + PIN rw0_wd_in[1250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.887 0.000 40.905 0.054 ; + END + END rw0_wd_in[1250] + PIN rw0_wd_in[1251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.067 0.000 41.085 0.054 ; + END + END rw0_wd_in[1251] + PIN rw0_wd_in[1252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 0.000 41.265 0.054 ; + END + END rw0_wd_in[1252] + PIN rw0_wd_in[1253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.427 0.000 41.445 0.054 ; + END + END rw0_wd_in[1253] + PIN rw0_wd_in[1254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.607 0.000 41.625 0.054 ; + END + END rw0_wd_in[1254] + PIN rw0_wd_in[1255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 0.000 41.805 0.054 ; + END + END rw0_wd_in[1255] + PIN rw0_wd_in[1256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END rw0_wd_in[1256] + PIN rw0_wd_in[1257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.147 0.000 42.165 0.054 ; + END + END rw0_wd_in[1257] + PIN rw0_wd_in[1258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 0.000 42.345 0.054 ; + END + END rw0_wd_in[1258] + PIN rw0_wd_in[1259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.507 0.000 42.525 0.054 ; + END + END rw0_wd_in[1259] + PIN rw0_wd_in[1260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.687 0.000 42.705 0.054 ; + END + END rw0_wd_in[1260] + PIN rw0_wd_in[1261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 0.000 42.885 0.054 ; + END + END rw0_wd_in[1261] + PIN rw0_wd_in[1262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.047 0.000 43.065 0.054 ; + END + END rw0_wd_in[1262] + PIN rw0_wd_in[1263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.227 0.000 43.245 0.054 ; + END + END rw0_wd_in[1263] + PIN rw0_wd_in[1264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END rw0_wd_in[1264] + PIN rw0_wd_in[1265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.587 0.000 43.605 0.054 ; + END + END rw0_wd_in[1265] + PIN rw0_wd_in[1266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.767 0.000 43.785 0.054 ; + END + END rw0_wd_in[1266] + PIN rw0_wd_in[1267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 0.000 43.965 0.054 ; + END + END rw0_wd_in[1267] + PIN rw0_wd_in[1268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.127 0.000 44.145 0.054 ; + END + END rw0_wd_in[1268] + PIN rw0_wd_in[1269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.307 0.000 44.325 0.054 ; + END + END rw0_wd_in[1269] + PIN rw0_wd_in[1270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 0.000 44.505 0.054 ; + END + END rw0_wd_in[1270] + PIN rw0_wd_in[1271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.667 0.000 44.685 0.054 ; + END + END rw0_wd_in[1271] + PIN rw0_wd_in[1272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END rw0_wd_in[1272] + PIN rw0_wd_in[1273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 0.000 45.045 0.054 ; + END + END rw0_wd_in[1273] + PIN rw0_wd_in[1274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.207 0.000 45.225 0.054 ; + END + END rw0_wd_in[1274] + PIN rw0_wd_in[1275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.387 0.000 45.405 0.054 ; + END + END rw0_wd_in[1275] + PIN rw0_wd_in[1276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 0.000 45.585 0.054 ; + END + END rw0_wd_in[1276] + PIN rw0_wd_in[1277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.747 0.000 45.765 0.054 ; + END + END rw0_wd_in[1277] + PIN rw0_wd_in[1278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.927 0.000 45.945 0.054 ; + END + END rw0_wd_in[1278] + PIN rw0_wd_in[1279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 0.000 46.125 0.054 ; + END + END rw0_wd_in[1279] + PIN rw0_wd_in[1280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END rw0_wd_in[1280] + PIN rw0_wd_in[1281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.467 0.000 46.485 0.054 ; + END + END rw0_wd_in[1281] + PIN rw0_wd_in[1282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 0.000 46.665 0.054 ; + END + END rw0_wd_in[1282] + PIN rw0_wd_in[1283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.827 0.000 46.845 0.054 ; + END + END rw0_wd_in[1283] + PIN rw0_wd_in[1284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.007 0.000 47.025 0.054 ; + END + END rw0_wd_in[1284] + PIN rw0_wd_in[1285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 0.000 47.205 0.054 ; + END + END rw0_wd_in[1285] + PIN rw0_wd_in[1286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.367 0.000 47.385 0.054 ; + END + END rw0_wd_in[1286] + PIN rw0_wd_in[1287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.547 0.000 47.565 0.054 ; + END + END rw0_wd_in[1287] + PIN rw0_wd_in[1288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END rw0_wd_in[1288] + PIN rw0_wd_in[1289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.907 0.000 47.925 0.054 ; + END + END rw0_wd_in[1289] + PIN rw0_wd_in[1290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.087 0.000 48.105 0.054 ; + END + END rw0_wd_in[1290] + PIN rw0_wd_in[1291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 0.000 48.285 0.054 ; + END + END rw0_wd_in[1291] + PIN rw0_wd_in[1292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.447 0.000 48.465 0.054 ; + END + END rw0_wd_in[1292] + PIN rw0_wd_in[1293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.627 0.000 48.645 0.054 ; + END + END rw0_wd_in[1293] + PIN rw0_wd_in[1294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 0.000 48.825 0.054 ; + END + END rw0_wd_in[1294] + PIN rw0_wd_in[1295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.987 0.000 49.005 0.054 ; + END + END rw0_wd_in[1295] + PIN rw0_wd_in[1296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END rw0_wd_in[1296] + PIN rw0_wd_in[1297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 0.000 49.365 0.054 ; + END + END rw0_wd_in[1297] + PIN rw0_wd_in[1298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.527 0.000 49.545 0.054 ; + END + END rw0_wd_in[1298] + PIN rw0_wd_in[1299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.707 0.000 49.725 0.054 ; + END + END rw0_wd_in[1299] + PIN rw0_wd_in[1300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 0.000 49.905 0.054 ; + END + END rw0_wd_in[1300] + PIN rw0_wd_in[1301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.067 0.000 50.085 0.054 ; + END + END rw0_wd_in[1301] + PIN rw0_wd_in[1302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.247 0.000 50.265 0.054 ; + END + END rw0_wd_in[1302] + PIN rw0_wd_in[1303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 0.000 50.445 0.054 ; + END + END rw0_wd_in[1303] + PIN rw0_wd_in[1304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END rw0_wd_in[1304] + PIN rw0_wd_in[1305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.787 0.000 50.805 0.054 ; + END + END rw0_wd_in[1305] + PIN rw0_wd_in[1306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 0.000 50.985 0.054 ; + END + END rw0_wd_in[1306] + PIN rw0_wd_in[1307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.147 0.000 51.165 0.054 ; + END + END rw0_wd_in[1307] + PIN rw0_wd_in[1308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.327 0.000 51.345 0.054 ; + END + END rw0_wd_in[1308] + PIN rw0_wd_in[1309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 0.000 51.525 0.054 ; + END + END rw0_wd_in[1309] + PIN rw0_wd_in[1310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.687 0.000 51.705 0.054 ; + END + END rw0_wd_in[1310] + PIN rw0_wd_in[1311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.867 0.000 51.885 0.054 ; + END + END rw0_wd_in[1311] + PIN rw0_wd_in[1312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END rw0_wd_in[1312] + PIN rw0_wd_in[1313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.227 0.000 52.245 0.054 ; + END + END rw0_wd_in[1313] + PIN rw0_wd_in[1314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.407 0.000 52.425 0.054 ; + END + END rw0_wd_in[1314] + PIN rw0_wd_in[1315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 0.000 52.605 0.054 ; + END + END rw0_wd_in[1315] + PIN rw0_wd_in[1316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.767 0.000 52.785 0.054 ; + END + END rw0_wd_in[1316] + PIN rw0_wd_in[1317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.947 0.000 52.965 0.054 ; + END + END rw0_wd_in[1317] + PIN rw0_wd_in[1318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 0.000 53.145 0.054 ; + END + END rw0_wd_in[1318] + PIN rw0_wd_in[1319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.307 0.000 53.325 0.054 ; + END + END rw0_wd_in[1319] + PIN rw0_wd_in[1320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END rw0_wd_in[1320] + PIN rw0_wd_in[1321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 0.000 53.685 0.054 ; + END + END rw0_wd_in[1321] + PIN rw0_wd_in[1322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.847 0.000 53.865 0.054 ; + END + END rw0_wd_in[1322] + PIN rw0_wd_in[1323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.027 0.000 54.045 0.054 ; + END + END rw0_wd_in[1323] + PIN rw0_wd_in[1324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 0.000 54.225 0.054 ; + END + END rw0_wd_in[1324] + PIN rw0_wd_in[1325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.387 0.000 54.405 0.054 ; + END + END rw0_wd_in[1325] + PIN rw0_wd_in[1326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.567 0.000 54.585 0.054 ; + END + END rw0_wd_in[1326] + PIN rw0_wd_in[1327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 0.000 54.765 0.054 ; + END + END rw0_wd_in[1327] + PIN rw0_wd_in[1328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END rw0_wd_in[1328] + PIN rw0_wd_in[1329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.107 0.000 55.125 0.054 ; + END + END rw0_wd_in[1329] + PIN rw0_wd_in[1330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 0.000 55.305 0.054 ; + END + END rw0_wd_in[1330] + PIN rw0_wd_in[1331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.467 0.000 55.485 0.054 ; + END + END rw0_wd_in[1331] + PIN rw0_wd_in[1332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.647 0.000 55.665 0.054 ; + END + END rw0_wd_in[1332] + PIN rw0_wd_in[1333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 0.000 55.845 0.054 ; + END + END rw0_wd_in[1333] + PIN rw0_wd_in[1334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.007 0.000 56.025 0.054 ; + END + END rw0_wd_in[1334] + PIN rw0_wd_in[1335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.187 0.000 56.205 0.054 ; + END + END rw0_wd_in[1335] + PIN rw0_wd_in[1336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END rw0_wd_in[1336] + PIN rw0_wd_in[1337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.547 0.000 56.565 0.054 ; + END + END rw0_wd_in[1337] + PIN rw0_wd_in[1338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.727 0.000 56.745 0.054 ; + END + END rw0_wd_in[1338] + PIN rw0_wd_in[1339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 0.000 56.925 0.054 ; + END + END rw0_wd_in[1339] + PIN rw0_wd_in[1340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.087 0.000 57.105 0.054 ; + END + END rw0_wd_in[1340] + PIN rw0_wd_in[1341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.267 0.000 57.285 0.054 ; + END + END rw0_wd_in[1341] + PIN rw0_wd_in[1342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 0.000 57.465 0.054 ; + END + END rw0_wd_in[1342] + PIN rw0_wd_in[1343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.627 0.000 57.645 0.054 ; + END + END rw0_wd_in[1343] + PIN rw0_wd_in[1344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END rw0_wd_in[1344] + PIN rw0_wd_in[1345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 0.000 58.005 0.054 ; + END + END rw0_wd_in[1345] + PIN rw0_wd_in[1346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.167 0.000 58.185 0.054 ; + END + END rw0_wd_in[1346] + PIN rw0_wd_in[1347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.347 0.000 58.365 0.054 ; + END + END rw0_wd_in[1347] + PIN rw0_wd_in[1348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 0.000 58.545 0.054 ; + END + END rw0_wd_in[1348] + PIN rw0_wd_in[1349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.707 0.000 58.725 0.054 ; + END + END rw0_wd_in[1349] + PIN rw0_wd_in[1350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.887 0.000 58.905 0.054 ; + END + END rw0_wd_in[1350] + PIN rw0_wd_in[1351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 0.000 59.085 0.054 ; + END + END rw0_wd_in[1351] + PIN rw0_wd_in[1352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END rw0_wd_in[1352] + PIN rw0_wd_in[1353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.427 0.000 59.445 0.054 ; + END + END rw0_wd_in[1353] + PIN rw0_wd_in[1354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 0.000 59.625 0.054 ; + END + END rw0_wd_in[1354] + PIN rw0_wd_in[1355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.787 0.000 59.805 0.054 ; + END + END rw0_wd_in[1355] + PIN rw0_wd_in[1356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.967 0.000 59.985 0.054 ; + END + END rw0_wd_in[1356] + PIN rw0_wd_in[1357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 0.000 60.165 0.054 ; + END + END rw0_wd_in[1357] + PIN rw0_wd_in[1358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.327 0.000 60.345 0.054 ; + END + END rw0_wd_in[1358] + PIN rw0_wd_in[1359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.507 0.000 60.525 0.054 ; + END + END rw0_wd_in[1359] + PIN rw0_wd_in[1360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END rw0_wd_in[1360] + PIN rw0_wd_in[1361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.867 0.000 60.885 0.054 ; + END + END rw0_wd_in[1361] + PIN rw0_wd_in[1362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.047 0.000 61.065 0.054 ; + END + END rw0_wd_in[1362] + PIN rw0_wd_in[1363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 0.000 61.245 0.054 ; + END + END rw0_wd_in[1363] + PIN rw0_wd_in[1364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.407 0.000 61.425 0.054 ; + END + END rw0_wd_in[1364] + PIN rw0_wd_in[1365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.587 0.000 61.605 0.054 ; + END + END rw0_wd_in[1365] + PIN rw0_wd_in[1366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 0.000 61.785 0.054 ; + END + END rw0_wd_in[1366] + PIN rw0_wd_in[1367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.947 0.000 61.965 0.054 ; + END + END rw0_wd_in[1367] + PIN rw0_wd_in[1368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END rw0_wd_in[1368] + PIN rw0_wd_in[1369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 0.000 62.325 0.054 ; + END + END rw0_wd_in[1369] + PIN rw0_wd_in[1370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.487 0.000 62.505 0.054 ; + END + END rw0_wd_in[1370] + PIN rw0_wd_in[1371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.667 0.000 62.685 0.054 ; + END + END rw0_wd_in[1371] + PIN rw0_wd_in[1372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 0.000 62.865 0.054 ; + END + END rw0_wd_in[1372] + PIN rw0_wd_in[1373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.027 0.000 63.045 0.054 ; + END + END rw0_wd_in[1373] + PIN rw0_wd_in[1374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.207 0.000 63.225 0.054 ; + END + END rw0_wd_in[1374] + PIN rw0_wd_in[1375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 0.000 63.405 0.054 ; + END + END rw0_wd_in[1375] + PIN rw0_wd_in[1376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END rw0_wd_in[1376] + PIN rw0_wd_in[1377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.747 0.000 63.765 0.054 ; + END + END rw0_wd_in[1377] + PIN rw0_wd_in[1378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.927 0.000 63.945 0.054 ; + END + END rw0_wd_in[1378] + PIN rw0_wd_in[1379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.107 0.000 64.125 0.054 ; + END + END rw0_wd_in[1379] + PIN rw0_wd_in[1380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.287 0.000 64.305 0.054 ; + END + END rw0_wd_in[1380] + PIN rw0_wd_in[1381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.467 0.000 64.485 0.054 ; + END + END rw0_wd_in[1381] + PIN rw0_wd_in[1382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.647 0.000 64.665 0.054 ; + END + END rw0_wd_in[1382] + PIN rw0_wd_in[1383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.827 0.000 64.845 0.054 ; + END + END rw0_wd_in[1383] + PIN rw0_wd_in[1384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END rw0_wd_in[1384] + PIN rw0_wd_in[1385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.187 0.000 65.205 0.054 ; + END + END rw0_wd_in[1385] + PIN rw0_wd_in[1386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.367 0.000 65.385 0.054 ; + END + END rw0_wd_in[1386] + PIN rw0_wd_in[1387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.547 0.000 65.565 0.054 ; + END + END rw0_wd_in[1387] + PIN rw0_wd_in[1388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.727 0.000 65.745 0.054 ; + END + END rw0_wd_in[1388] + PIN rw0_wd_in[1389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.907 0.000 65.925 0.054 ; + END + END rw0_wd_in[1389] + PIN rw0_wd_in[1390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.087 0.000 66.105 0.054 ; + END + END rw0_wd_in[1390] + PIN rw0_wd_in[1391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.267 0.000 66.285 0.054 ; + END + END rw0_wd_in[1391] + PIN rw0_wd_in[1392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END rw0_wd_in[1392] + PIN rw0_wd_in[1393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.627 0.000 66.645 0.054 ; + END + END rw0_wd_in[1393] + PIN rw0_wd_in[1394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.807 0.000 66.825 0.054 ; + END + END rw0_wd_in[1394] + PIN rw0_wd_in[1395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.987 0.000 67.005 0.054 ; + END + END rw0_wd_in[1395] + PIN rw0_wd_in[1396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.167 0.000 67.185 0.054 ; + END + END rw0_wd_in[1396] + PIN rw0_wd_in[1397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.347 0.000 67.365 0.054 ; + END + END rw0_wd_in[1397] + PIN rw0_wd_in[1398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.527 0.000 67.545 0.054 ; + END + END rw0_wd_in[1398] + PIN rw0_wd_in[1399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.707 0.000 67.725 0.054 ; + END + END rw0_wd_in[1399] + PIN rw0_wd_in[1400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END rw0_wd_in[1400] + PIN rw0_wd_in[1401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.067 0.000 68.085 0.054 ; + END + END rw0_wd_in[1401] + PIN rw0_wd_in[1402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.247 0.000 68.265 0.054 ; + END + END rw0_wd_in[1402] + PIN rw0_wd_in[1403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.427 0.000 68.445 0.054 ; + END + END rw0_wd_in[1403] + PIN rw0_wd_in[1404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.607 0.000 68.625 0.054 ; + END + END rw0_wd_in[1404] + PIN rw0_wd_in[1405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.787 0.000 68.805 0.054 ; + END + END rw0_wd_in[1405] + PIN rw0_wd_in[1406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.967 0.000 68.985 0.054 ; + END + END rw0_wd_in[1406] + PIN rw0_wd_in[1407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.147 0.000 69.165 0.054 ; + END + END rw0_wd_in[1407] + PIN rw0_wd_in[1408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END rw0_wd_in[1408] + PIN rw0_wd_in[1409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.507 0.000 69.525 0.054 ; + END + END rw0_wd_in[1409] + PIN rw0_wd_in[1410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.687 0.000 69.705 0.054 ; + END + END rw0_wd_in[1410] + PIN rw0_wd_in[1411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.867 0.000 69.885 0.054 ; + END + END rw0_wd_in[1411] + PIN rw0_wd_in[1412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.047 0.000 70.065 0.054 ; + END + END rw0_wd_in[1412] + PIN rw0_wd_in[1413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.227 0.000 70.245 0.054 ; + END + END rw0_wd_in[1413] + PIN rw0_wd_in[1414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.407 0.000 70.425 0.054 ; + END + END rw0_wd_in[1414] + PIN rw0_wd_in[1415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.587 0.000 70.605 0.054 ; + END + END rw0_wd_in[1415] + PIN rw0_wd_in[1416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END rw0_wd_in[1416] + PIN rw0_wd_in[1417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.947 0.000 70.965 0.054 ; + END + END rw0_wd_in[1417] + PIN rw0_wd_in[1418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.127 0.000 71.145 0.054 ; + END + END rw0_wd_in[1418] + PIN rw0_wd_in[1419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.307 0.000 71.325 0.054 ; + END + END rw0_wd_in[1419] + PIN rw0_wd_in[1420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.487 0.000 71.505 0.054 ; + END + END rw0_wd_in[1420] + PIN rw0_wd_in[1421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.667 0.000 71.685 0.054 ; + END + END rw0_wd_in[1421] + PIN rw0_wd_in[1422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.847 0.000 71.865 0.054 ; + END + END rw0_wd_in[1422] + PIN rw0_wd_in[1423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.027 0.000 72.045 0.054 ; + END + END rw0_wd_in[1423] + PIN rw0_wd_in[1424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END rw0_wd_in[1424] + PIN rw0_wd_in[1425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.387 0.000 72.405 0.054 ; + END + END rw0_wd_in[1425] + PIN rw0_wd_in[1426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.567 0.000 72.585 0.054 ; + END + END rw0_wd_in[1426] + PIN rw0_wd_in[1427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.747 0.000 72.765 0.054 ; + END + END rw0_wd_in[1427] + PIN rw0_wd_in[1428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.927 0.000 72.945 0.054 ; + END + END rw0_wd_in[1428] + PIN rw0_wd_in[1429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.107 0.000 73.125 0.054 ; + END + END rw0_wd_in[1429] + PIN rw0_wd_in[1430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.287 0.000 73.305 0.054 ; + END + END rw0_wd_in[1430] + PIN rw0_wd_in[1431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.467 0.000 73.485 0.054 ; + END + END rw0_wd_in[1431] + PIN rw0_wd_in[1432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END rw0_wd_in[1432] + PIN rw0_wd_in[1433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.827 0.000 73.845 0.054 ; + END + END rw0_wd_in[1433] + PIN rw0_wd_in[1434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.007 0.000 74.025 0.054 ; + END + END rw0_wd_in[1434] + PIN rw0_wd_in[1435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.187 0.000 74.205 0.054 ; + END + END rw0_wd_in[1435] + PIN rw0_wd_in[1436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.367 0.000 74.385 0.054 ; + END + END rw0_wd_in[1436] + PIN rw0_wd_in[1437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.547 0.000 74.565 0.054 ; + END + END rw0_wd_in[1437] + PIN rw0_wd_in[1438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.727 0.000 74.745 0.054 ; + END + END rw0_wd_in[1438] + PIN rw0_wd_in[1439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.907 0.000 74.925 0.054 ; + END + END rw0_wd_in[1439] + PIN rw0_wd_in[1440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END rw0_wd_in[1440] + PIN rw0_wd_in[1441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.267 0.000 75.285 0.054 ; + END + END rw0_wd_in[1441] + PIN rw0_wd_in[1442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.447 0.000 75.465 0.054 ; + END + END rw0_wd_in[1442] + PIN rw0_wd_in[1443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.627 0.000 75.645 0.054 ; + END + END rw0_wd_in[1443] + PIN rw0_wd_in[1444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.807 0.000 75.825 0.054 ; + END + END rw0_wd_in[1444] + PIN rw0_wd_in[1445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.987 0.000 76.005 0.054 ; + END + END rw0_wd_in[1445] + PIN rw0_wd_in[1446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.167 0.000 76.185 0.054 ; + END + END rw0_wd_in[1446] + PIN rw0_wd_in[1447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.347 0.000 76.365 0.054 ; + END + END rw0_wd_in[1447] + PIN rw0_wd_in[1448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END rw0_wd_in[1448] + PIN rw0_wd_in[1449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.707 0.000 76.725 0.054 ; + END + END rw0_wd_in[1449] + PIN rw0_wd_in[1450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.887 0.000 76.905 0.054 ; + END + END rw0_wd_in[1450] + PIN rw0_wd_in[1451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.067 0.000 77.085 0.054 ; + END + END rw0_wd_in[1451] + PIN rw0_wd_in[1452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.247 0.000 77.265 0.054 ; + END + END rw0_wd_in[1452] + PIN rw0_wd_in[1453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.427 0.000 77.445 0.054 ; + END + END rw0_wd_in[1453] + PIN rw0_wd_in[1454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.607 0.000 77.625 0.054 ; + END + END rw0_wd_in[1454] + PIN rw0_wd_in[1455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.787 0.000 77.805 0.054 ; + END + END rw0_wd_in[1455] + PIN rw0_wd_in[1456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END rw0_wd_in[1456] + PIN rw0_wd_in[1457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.147 0.000 78.165 0.054 ; + END + END rw0_wd_in[1457] + PIN rw0_wd_in[1458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.327 0.000 78.345 0.054 ; + END + END rw0_wd_in[1458] + PIN rw0_wd_in[1459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.507 0.000 78.525 0.054 ; + END + END rw0_wd_in[1459] + PIN rw0_wd_in[1460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.687 0.000 78.705 0.054 ; + END + END rw0_wd_in[1460] + PIN rw0_wd_in[1461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.867 0.000 78.885 0.054 ; + END + END rw0_wd_in[1461] + PIN rw0_wd_in[1462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.047 0.000 79.065 0.054 ; + END + END rw0_wd_in[1462] + PIN rw0_wd_in[1463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.227 0.000 79.245 0.054 ; + END + END rw0_wd_in[1463] + PIN rw0_wd_in[1464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END rw0_wd_in[1464] + PIN rw0_wd_in[1465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.587 0.000 79.605 0.054 ; + END + END rw0_wd_in[1465] + PIN rw0_wd_in[1466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.767 0.000 79.785 0.054 ; + END + END rw0_wd_in[1466] + PIN rw0_wd_in[1467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.947 0.000 79.965 0.054 ; + END + END rw0_wd_in[1467] + PIN rw0_wd_in[1468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.127 0.000 80.145 0.054 ; + END + END rw0_wd_in[1468] + PIN rw0_wd_in[1469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.307 0.000 80.325 0.054 ; + END + END rw0_wd_in[1469] + PIN rw0_wd_in[1470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.487 0.000 80.505 0.054 ; + END + END rw0_wd_in[1470] + PIN rw0_wd_in[1471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.667 0.000 80.685 0.054 ; + END + END rw0_wd_in[1471] + PIN rw0_wd_in[1472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END rw0_wd_in[1472] + PIN rw0_wd_in[1473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.027 0.000 81.045 0.054 ; + END + END rw0_wd_in[1473] + PIN rw0_wd_in[1474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.207 0.000 81.225 0.054 ; + END + END rw0_wd_in[1474] + PIN rw0_wd_in[1475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.387 0.000 81.405 0.054 ; + END + END rw0_wd_in[1475] + PIN rw0_wd_in[1476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.567 0.000 81.585 0.054 ; + END + END rw0_wd_in[1476] + PIN rw0_wd_in[1477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.747 0.000 81.765 0.054 ; + END + END rw0_wd_in[1477] + PIN rw0_wd_in[1478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.927 0.000 81.945 0.054 ; + END + END rw0_wd_in[1478] + PIN rw0_wd_in[1479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.107 0.000 82.125 0.054 ; + END + END rw0_wd_in[1479] + PIN rw0_wd_in[1480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END rw0_wd_in[1480] + PIN rw0_wd_in[1481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.467 0.000 82.485 0.054 ; + END + END rw0_wd_in[1481] + PIN rw0_wd_in[1482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.647 0.000 82.665 0.054 ; + END + END rw0_wd_in[1482] + PIN rw0_wd_in[1483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.827 0.000 82.845 0.054 ; + END + END rw0_wd_in[1483] + PIN rw0_wd_in[1484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.007 0.000 83.025 0.054 ; + END + END rw0_wd_in[1484] + PIN rw0_wd_in[1485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.187 0.000 83.205 0.054 ; + END + END rw0_wd_in[1485] + PIN rw0_wd_in[1486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.367 0.000 83.385 0.054 ; + END + END rw0_wd_in[1486] + PIN rw0_wd_in[1487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.547 0.000 83.565 0.054 ; + END + END rw0_wd_in[1487] + PIN rw0_wd_in[1488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END rw0_wd_in[1488] + PIN rw0_wd_in[1489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.907 0.000 83.925 0.054 ; + END + END rw0_wd_in[1489] + PIN rw0_wd_in[1490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.087 0.000 84.105 0.054 ; + END + END rw0_wd_in[1490] + PIN rw0_wd_in[1491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.267 0.000 84.285 0.054 ; + END + END rw0_wd_in[1491] + PIN rw0_wd_in[1492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.447 0.000 84.465 0.054 ; + END + END rw0_wd_in[1492] + PIN rw0_wd_in[1493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.627 0.000 84.645 0.054 ; + END + END rw0_wd_in[1493] + PIN rw0_wd_in[1494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.807 0.000 84.825 0.054 ; + END + END rw0_wd_in[1494] + PIN rw0_wd_in[1495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.987 0.000 85.005 0.054 ; + END + END rw0_wd_in[1495] + PIN rw0_wd_in[1496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END rw0_wd_in[1496] + PIN rw0_wd_in[1497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.347 0.000 85.365 0.054 ; + END + END rw0_wd_in[1497] + PIN rw0_wd_in[1498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.527 0.000 85.545 0.054 ; + END + END rw0_wd_in[1498] + PIN rw0_wd_in[1499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.707 0.000 85.725 0.054 ; + END + END rw0_wd_in[1499] + PIN rw0_wd_in[1500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.887 0.000 85.905 0.054 ; + END + END rw0_wd_in[1500] + PIN rw0_wd_in[1501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.067 0.000 86.085 0.054 ; + END + END rw0_wd_in[1501] + PIN rw0_wd_in[1502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.247 0.000 86.265 0.054 ; + END + END rw0_wd_in[1502] + PIN rw0_wd_in[1503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.427 0.000 86.445 0.054 ; + END + END rw0_wd_in[1503] + PIN rw0_wd_in[1504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END rw0_wd_in[1504] + PIN rw0_wd_in[1505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.787 0.000 86.805 0.054 ; + END + END rw0_wd_in[1505] + PIN rw0_wd_in[1506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.967 0.000 86.985 0.054 ; + END + END rw0_wd_in[1506] + PIN rw0_wd_in[1507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.147 0.000 87.165 0.054 ; + END + END rw0_wd_in[1507] + PIN rw0_wd_in[1508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.327 0.000 87.345 0.054 ; + END + END rw0_wd_in[1508] + PIN rw0_wd_in[1509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.507 0.000 87.525 0.054 ; + END + END rw0_wd_in[1509] + PIN rw0_wd_in[1510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.687 0.000 87.705 0.054 ; + END + END rw0_wd_in[1510] + PIN rw0_wd_in[1511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.867 0.000 87.885 0.054 ; + END + END rw0_wd_in[1511] + PIN rw0_wd_in[1512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END rw0_wd_in[1512] + PIN rw0_wd_in[1513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.227 0.000 88.245 0.054 ; + END + END rw0_wd_in[1513] + PIN rw0_wd_in[1514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.407 0.000 88.425 0.054 ; + END + END rw0_wd_in[1514] + PIN rw0_wd_in[1515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.587 0.000 88.605 0.054 ; + END + END rw0_wd_in[1515] + PIN rw0_wd_in[1516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.767 0.000 88.785 0.054 ; + END + END rw0_wd_in[1516] + PIN rw0_wd_in[1517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.947 0.000 88.965 0.054 ; + END + END rw0_wd_in[1517] + PIN rw0_wd_in[1518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.127 0.000 89.145 0.054 ; + END + END rw0_wd_in[1518] + PIN rw0_wd_in[1519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.307 0.000 89.325 0.054 ; + END + END rw0_wd_in[1519] + PIN rw0_wd_in[1520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END rw0_wd_in[1520] + PIN rw0_wd_in[1521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.667 0.000 89.685 0.054 ; + END + END rw0_wd_in[1521] + PIN rw0_wd_in[1522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.847 0.000 89.865 0.054 ; + END + END rw0_wd_in[1522] + PIN rw0_wd_in[1523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.027 0.000 90.045 0.054 ; + END + END rw0_wd_in[1523] + PIN rw0_wd_in[1524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.207 0.000 90.225 0.054 ; + END + END rw0_wd_in[1524] + PIN rw0_wd_in[1525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.387 0.000 90.405 0.054 ; + END + END rw0_wd_in[1525] + PIN rw0_wd_in[1526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.567 0.000 90.585 0.054 ; + END + END rw0_wd_in[1526] + PIN rw0_wd_in[1527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.747 0.000 90.765 0.054 ; + END + END rw0_wd_in[1527] + PIN rw0_wd_in[1528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END rw0_wd_in[1528] + PIN rw0_wd_in[1529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.107 0.000 91.125 0.054 ; + END + END rw0_wd_in[1529] + PIN rw0_wd_in[1530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.287 0.000 91.305 0.054 ; + END + END rw0_wd_in[1530] + PIN rw0_wd_in[1531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.467 0.000 91.485 0.054 ; + END + END rw0_wd_in[1531] + PIN rw0_wd_in[1532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.647 0.000 91.665 0.054 ; + END + END rw0_wd_in[1532] + PIN rw0_wd_in[1533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.827 0.000 91.845 0.054 ; + END + END rw0_wd_in[1533] + PIN rw0_wd_in[1534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.007 0.000 92.025 0.054 ; + END + END rw0_wd_in[1534] + PIN rw0_wd_in[1535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.187 0.000 92.205 0.054 ; + END + END rw0_wd_in[1535] + PIN rw0_wd_in[1536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 0.000 92.385 0.054 ; + END + END rw0_wd_in[1536] + PIN rw0_wd_in[1537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.547 0.000 92.565 0.054 ; + END + END rw0_wd_in[1537] + PIN rw0_wd_in[1538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.727 0.000 92.745 0.054 ; + END + END rw0_wd_in[1538] + PIN rw0_wd_in[1539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.907 0.000 92.925 0.054 ; + END + END rw0_wd_in[1539] + PIN rw0_wd_in[1540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.087 0.000 93.105 0.054 ; + END + END rw0_wd_in[1540] + PIN rw0_wd_in[1541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.267 0.000 93.285 0.054 ; + END + END rw0_wd_in[1541] + PIN rw0_wd_in[1542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.447 0.000 93.465 0.054 ; + END + END rw0_wd_in[1542] + PIN rw0_wd_in[1543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.627 0.000 93.645 0.054 ; + END + END rw0_wd_in[1543] + PIN rw0_wd_in[1544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 0.000 93.825 0.054 ; + END + END rw0_wd_in[1544] + PIN rw0_wd_in[1545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.987 0.000 94.005 0.054 ; + END + END rw0_wd_in[1545] + PIN rw0_wd_in[1546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.167 0.000 94.185 0.054 ; + END + END rw0_wd_in[1546] + PIN rw0_wd_in[1547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.347 0.000 94.365 0.054 ; + END + END rw0_wd_in[1547] + PIN rw0_wd_in[1548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.527 0.000 94.545 0.054 ; + END + END rw0_wd_in[1548] + PIN rw0_wd_in[1549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.707 0.000 94.725 0.054 ; + END + END rw0_wd_in[1549] + PIN rw0_wd_in[1550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.887 0.000 94.905 0.054 ; + END + END rw0_wd_in[1550] + PIN rw0_wd_in[1551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.067 0.000 95.085 0.054 ; + END + END rw0_wd_in[1551] + PIN rw0_wd_in[1552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 0.000 95.265 0.054 ; + END + END rw0_wd_in[1552] + PIN rw0_wd_in[1553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.427 0.000 95.445 0.054 ; + END + END rw0_wd_in[1553] + PIN rw0_wd_in[1554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.607 0.000 95.625 0.054 ; + END + END rw0_wd_in[1554] + PIN rw0_wd_in[1555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.787 0.000 95.805 0.054 ; + END + END rw0_wd_in[1555] + PIN rw0_wd_in[1556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.967 0.000 95.985 0.054 ; + END + END rw0_wd_in[1556] + PIN rw0_wd_in[1557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.147 0.000 96.165 0.054 ; + END + END rw0_wd_in[1557] + PIN rw0_wd_in[1558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.327 0.000 96.345 0.054 ; + END + END rw0_wd_in[1558] + PIN rw0_wd_in[1559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.507 0.000 96.525 0.054 ; + END + END rw0_wd_in[1559] + PIN rw0_wd_in[1560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 0.000 96.705 0.054 ; + END + END rw0_wd_in[1560] + PIN rw0_wd_in[1561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.867 0.000 96.885 0.054 ; + END + END rw0_wd_in[1561] + PIN rw0_wd_in[1562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.047 0.000 97.065 0.054 ; + END + END rw0_wd_in[1562] + PIN rw0_wd_in[1563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.227 0.000 97.245 0.054 ; + END + END rw0_wd_in[1563] + PIN rw0_wd_in[1564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.407 0.000 97.425 0.054 ; + END + END rw0_wd_in[1564] + PIN rw0_wd_in[1565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.587 0.000 97.605 0.054 ; + END + END rw0_wd_in[1565] + PIN rw0_wd_in[1566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.767 0.000 97.785 0.054 ; + END + END rw0_wd_in[1566] + PIN rw0_wd_in[1567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.947 0.000 97.965 0.054 ; + END + END rw0_wd_in[1567] + PIN rw0_wd_in[1568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 0.000 98.145 0.054 ; + END + END rw0_wd_in[1568] + PIN rw0_wd_in[1569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.307 0.000 98.325 0.054 ; + END + END rw0_wd_in[1569] + PIN rw0_wd_in[1570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.487 0.000 98.505 0.054 ; + END + END rw0_wd_in[1570] + PIN rw0_wd_in[1571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.667 0.000 98.685 0.054 ; + END + END rw0_wd_in[1571] + PIN rw0_wd_in[1572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.847 0.000 98.865 0.054 ; + END + END rw0_wd_in[1572] + PIN rw0_wd_in[1573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.027 0.000 99.045 0.054 ; + END + END rw0_wd_in[1573] + PIN rw0_wd_in[1574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.207 0.000 99.225 0.054 ; + END + END rw0_wd_in[1574] + PIN rw0_wd_in[1575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.387 0.000 99.405 0.054 ; + END + END rw0_wd_in[1575] + PIN rw0_wd_in[1576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 0.000 99.585 0.054 ; + END + END rw0_wd_in[1576] + PIN rw0_wd_in[1577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.747 0.000 99.765 0.054 ; + END + END rw0_wd_in[1577] + PIN rw0_wd_in[1578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.927 0.000 99.945 0.054 ; + END + END rw0_wd_in[1578] + PIN rw0_wd_in[1579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.107 0.000 100.125 0.054 ; + END + END rw0_wd_in[1579] + PIN rw0_wd_in[1580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.287 0.000 100.305 0.054 ; + END + END rw0_wd_in[1580] + PIN rw0_wd_in[1581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.467 0.000 100.485 0.054 ; + END + END rw0_wd_in[1581] + PIN rw0_wd_in[1582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.647 0.000 100.665 0.054 ; + END + END rw0_wd_in[1582] + PIN rw0_wd_in[1583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.827 0.000 100.845 0.054 ; + END + END rw0_wd_in[1583] + PIN rw0_wd_in[1584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 0.000 101.025 0.054 ; + END + END rw0_wd_in[1584] + PIN rw0_wd_in[1585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.187 0.000 101.205 0.054 ; + END + END rw0_wd_in[1585] + PIN rw0_wd_in[1586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.367 0.000 101.385 0.054 ; + END + END rw0_wd_in[1586] + PIN rw0_wd_in[1587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.547 0.000 101.565 0.054 ; + END + END rw0_wd_in[1587] + PIN rw0_wd_in[1588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.727 0.000 101.745 0.054 ; + END + END rw0_wd_in[1588] + PIN rw0_wd_in[1589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.907 0.000 101.925 0.054 ; + END + END rw0_wd_in[1589] + PIN rw0_wd_in[1590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.087 0.000 102.105 0.054 ; + END + END rw0_wd_in[1590] + PIN rw0_wd_in[1591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.267 0.000 102.285 0.054 ; + END + END rw0_wd_in[1591] + PIN rw0_wd_in[1592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 0.000 102.465 0.054 ; + END + END rw0_wd_in[1592] + PIN rw0_wd_in[1593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.627 0.000 102.645 0.054 ; + END + END rw0_wd_in[1593] + PIN rw0_wd_in[1594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.807 0.000 102.825 0.054 ; + END + END rw0_wd_in[1594] + PIN rw0_wd_in[1595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.987 0.000 103.005 0.054 ; + END + END rw0_wd_in[1595] + PIN rw0_wd_in[1596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.167 0.000 103.185 0.054 ; + END + END rw0_wd_in[1596] + PIN rw0_wd_in[1597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.347 0.000 103.365 0.054 ; + END + END rw0_wd_in[1597] + PIN rw0_wd_in[1598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.527 0.000 103.545 0.054 ; + END + END rw0_wd_in[1598] + PIN rw0_wd_in[1599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.707 0.000 103.725 0.054 ; + END + END rw0_wd_in[1599] + PIN rw0_wd_in[1600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 0.000 103.905 0.054 ; + END + END rw0_wd_in[1600] + PIN rw0_wd_in[1601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.067 0.000 104.085 0.054 ; + END + END rw0_wd_in[1601] + PIN rw0_wd_in[1602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.247 0.000 104.265 0.054 ; + END + END rw0_wd_in[1602] + PIN rw0_wd_in[1603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.427 0.000 104.445 0.054 ; + END + END rw0_wd_in[1603] + PIN rw0_wd_in[1604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.607 0.000 104.625 0.054 ; + END + END rw0_wd_in[1604] + PIN rw0_wd_in[1605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.787 0.000 104.805 0.054 ; + END + END rw0_wd_in[1605] + PIN rw0_wd_in[1606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.967 0.000 104.985 0.054 ; + END + END rw0_wd_in[1606] + PIN rw0_wd_in[1607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.147 0.000 105.165 0.054 ; + END + END rw0_wd_in[1607] + PIN rw0_wd_in[1608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 0.000 105.345 0.054 ; + END + END rw0_wd_in[1608] + PIN rw0_wd_in[1609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.507 0.000 105.525 0.054 ; + END + END rw0_wd_in[1609] + PIN rw0_wd_in[1610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.687 0.000 105.705 0.054 ; + END + END rw0_wd_in[1610] + PIN rw0_wd_in[1611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.867 0.000 105.885 0.054 ; + END + END rw0_wd_in[1611] + PIN rw0_wd_in[1612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.047 0.000 106.065 0.054 ; + END + END rw0_wd_in[1612] + PIN rw0_wd_in[1613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.227 0.000 106.245 0.054 ; + END + END rw0_wd_in[1613] + PIN rw0_wd_in[1614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.407 0.000 106.425 0.054 ; + END + END rw0_wd_in[1614] + PIN rw0_wd_in[1615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.587 0.000 106.605 0.054 ; + END + END rw0_wd_in[1615] + PIN rw0_wd_in[1616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 0.000 106.785 0.054 ; + END + END rw0_wd_in[1616] + PIN rw0_wd_in[1617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.947 0.000 106.965 0.054 ; + END + END rw0_wd_in[1617] + PIN rw0_wd_in[1618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.127 0.000 107.145 0.054 ; + END + END rw0_wd_in[1618] + PIN rw0_wd_in[1619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.307 0.000 107.325 0.054 ; + END + END rw0_wd_in[1619] + PIN rw0_wd_in[1620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.487 0.000 107.505 0.054 ; + END + END rw0_wd_in[1620] + PIN rw0_wd_in[1621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.667 0.000 107.685 0.054 ; + END + END rw0_wd_in[1621] + PIN rw0_wd_in[1622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.847 0.000 107.865 0.054 ; + END + END rw0_wd_in[1622] + PIN rw0_wd_in[1623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.027 0.000 108.045 0.054 ; + END + END rw0_wd_in[1623] + PIN rw0_wd_in[1624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 0.000 108.225 0.054 ; + END + END rw0_wd_in[1624] + PIN rw0_wd_in[1625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.387 0.000 108.405 0.054 ; + END + END rw0_wd_in[1625] + PIN rw0_wd_in[1626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.567 0.000 108.585 0.054 ; + END + END rw0_wd_in[1626] + PIN rw0_wd_in[1627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.747 0.000 108.765 0.054 ; + END + END rw0_wd_in[1627] + PIN rw0_wd_in[1628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.927 0.000 108.945 0.054 ; + END + END rw0_wd_in[1628] + PIN rw0_wd_in[1629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.107 0.000 109.125 0.054 ; + END + END rw0_wd_in[1629] + PIN rw0_wd_in[1630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.287 0.000 109.305 0.054 ; + END + END rw0_wd_in[1630] + PIN rw0_wd_in[1631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.467 0.000 109.485 0.054 ; + END + END rw0_wd_in[1631] + PIN rw0_wd_in[1632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 0.000 109.665 0.054 ; + END + END rw0_wd_in[1632] + PIN rw0_wd_in[1633] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.827 0.000 109.845 0.054 ; + END + END rw0_wd_in[1633] + PIN rw0_wd_in[1634] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.007 0.000 110.025 0.054 ; + END + END rw0_wd_in[1634] + PIN rw0_wd_in[1635] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.187 0.000 110.205 0.054 ; + END + END rw0_wd_in[1635] + PIN rw0_wd_in[1636] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.367 0.000 110.385 0.054 ; + END + END rw0_wd_in[1636] + PIN rw0_wd_in[1637] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.547 0.000 110.565 0.054 ; + END + END rw0_wd_in[1637] + PIN rw0_wd_in[1638] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.727 0.000 110.745 0.054 ; + END + END rw0_wd_in[1638] + PIN rw0_wd_in[1639] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.907 0.000 110.925 0.054 ; + END + END rw0_wd_in[1639] + PIN rw0_wd_in[1640] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 0.000 111.105 0.054 ; + END + END rw0_wd_in[1640] + PIN rw0_wd_in[1641] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.267 0.000 111.285 0.054 ; + END + END rw0_wd_in[1641] + PIN rw0_wd_in[1642] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.447 0.000 111.465 0.054 ; + END + END rw0_wd_in[1642] + PIN rw0_wd_in[1643] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.627 0.000 111.645 0.054 ; + END + END rw0_wd_in[1643] + PIN rw0_wd_in[1644] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.807 0.000 111.825 0.054 ; + END + END rw0_wd_in[1644] + PIN rw0_wd_in[1645] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.987 0.000 112.005 0.054 ; + END + END rw0_wd_in[1645] + PIN rw0_wd_in[1646] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.167 0.000 112.185 0.054 ; + END + END rw0_wd_in[1646] + PIN rw0_wd_in[1647] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.347 0.000 112.365 0.054 ; + END + END rw0_wd_in[1647] + PIN rw0_wd_in[1648] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 0.000 112.545 0.054 ; + END + END rw0_wd_in[1648] + PIN rw0_wd_in[1649] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.707 0.000 112.725 0.054 ; + END + END rw0_wd_in[1649] + PIN rw0_wd_in[1650] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.887 0.000 112.905 0.054 ; + END + END rw0_wd_in[1650] + PIN rw0_wd_in[1651] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.067 0.000 113.085 0.054 ; + END + END rw0_wd_in[1651] + PIN rw0_wd_in[1652] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.247 0.000 113.265 0.054 ; + END + END rw0_wd_in[1652] + PIN rw0_wd_in[1653] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.427 0.000 113.445 0.054 ; + END + END rw0_wd_in[1653] + PIN rw0_wd_in[1654] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.607 0.000 113.625 0.054 ; + END + END rw0_wd_in[1654] + PIN rw0_wd_in[1655] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.787 0.000 113.805 0.054 ; + END + END rw0_wd_in[1655] + PIN rw0_wd_in[1656] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 0.000 113.985 0.054 ; + END + END rw0_wd_in[1656] + PIN rw0_wd_in[1657] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.147 0.000 114.165 0.054 ; + END + END rw0_wd_in[1657] + PIN rw0_wd_in[1658] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.327 0.000 114.345 0.054 ; + END + END rw0_wd_in[1658] + PIN rw0_wd_in[1659] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.507 0.000 114.525 0.054 ; + END + END rw0_wd_in[1659] + PIN rw0_wd_in[1660] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.687 0.000 114.705 0.054 ; + END + END rw0_wd_in[1660] + PIN rw0_wd_in[1661] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.867 0.000 114.885 0.054 ; + END + END rw0_wd_in[1661] + PIN rw0_wd_in[1662] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.047 0.000 115.065 0.054 ; + END + END rw0_wd_in[1662] + PIN rw0_wd_in[1663] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.227 0.000 115.245 0.054 ; + END + END rw0_wd_in[1663] + PIN rw0_wd_in[1664] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 0.000 115.425 0.054 ; + END + END rw0_wd_in[1664] + PIN rw0_wd_in[1665] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.587 0.000 115.605 0.054 ; + END + END rw0_wd_in[1665] + PIN rw0_wd_in[1666] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.767 0.000 115.785 0.054 ; + END + END rw0_wd_in[1666] + PIN rw0_wd_in[1667] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.947 0.000 115.965 0.054 ; + END + END rw0_wd_in[1667] + PIN rw0_wd_in[1668] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.127 0.000 116.145 0.054 ; + END + END rw0_wd_in[1668] + PIN rw0_wd_in[1669] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.307 0.000 116.325 0.054 ; + END + END rw0_wd_in[1669] + PIN rw0_wd_in[1670] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.487 0.000 116.505 0.054 ; + END + END rw0_wd_in[1670] + PIN rw0_wd_in[1671] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.667 0.000 116.685 0.054 ; + END + END rw0_wd_in[1671] + PIN rw0_wd_in[1672] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 0.000 116.865 0.054 ; + END + END rw0_wd_in[1672] + PIN rw0_wd_in[1673] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.027 0.000 117.045 0.054 ; + END + END rw0_wd_in[1673] + PIN rw0_wd_in[1674] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.207 0.000 117.225 0.054 ; + END + END rw0_wd_in[1674] + PIN rw0_wd_in[1675] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.387 0.000 117.405 0.054 ; + END + END rw0_wd_in[1675] + PIN rw0_wd_in[1676] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.567 0.000 117.585 0.054 ; + END + END rw0_wd_in[1676] + PIN rw0_wd_in[1677] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.747 0.000 117.765 0.054 ; + END + END rw0_wd_in[1677] + PIN rw0_wd_in[1678] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.927 0.000 117.945 0.054 ; + END + END rw0_wd_in[1678] + PIN rw0_wd_in[1679] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.107 0.000 118.125 0.054 ; + END + END rw0_wd_in[1679] + PIN rw0_wd_in[1680] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 0.000 118.305 0.054 ; + END + END rw0_wd_in[1680] + PIN rw0_wd_in[1681] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.467 0.000 118.485 0.054 ; + END + END rw0_wd_in[1681] + PIN rw0_wd_in[1682] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.647 0.000 118.665 0.054 ; + END + END rw0_wd_in[1682] + PIN rw0_wd_in[1683] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.827 0.000 118.845 0.054 ; + END + END rw0_wd_in[1683] + PIN rw0_wd_in[1684] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.007 0.000 119.025 0.054 ; + END + END rw0_wd_in[1684] + PIN rw0_wd_in[1685] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.187 0.000 119.205 0.054 ; + END + END rw0_wd_in[1685] + PIN rw0_wd_in[1686] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.367 0.000 119.385 0.054 ; + END + END rw0_wd_in[1686] + PIN rw0_wd_in[1687] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.547 0.000 119.565 0.054 ; + END + END rw0_wd_in[1687] + PIN rw0_wd_in[1688] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 0.000 119.745 0.054 ; + END + END rw0_wd_in[1688] + PIN rw0_wd_in[1689] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.907 0.000 119.925 0.054 ; + END + END rw0_wd_in[1689] + PIN rw0_wd_in[1690] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.087 0.000 120.105 0.054 ; + END + END rw0_wd_in[1690] + PIN rw0_wd_in[1691] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.267 0.000 120.285 0.054 ; + END + END rw0_wd_in[1691] + PIN rw0_wd_in[1692] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.447 0.000 120.465 0.054 ; + END + END rw0_wd_in[1692] + PIN rw0_wd_in[1693] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.627 0.000 120.645 0.054 ; + END + END rw0_wd_in[1693] + PIN rw0_wd_in[1694] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.807 0.000 120.825 0.054 ; + END + END rw0_wd_in[1694] + PIN rw0_wd_in[1695] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.987 0.000 121.005 0.054 ; + END + END rw0_wd_in[1695] + PIN rw0_wd_in[1696] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 0.000 121.185 0.054 ; + END + END rw0_wd_in[1696] + PIN rw0_wd_in[1697] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.347 0.000 121.365 0.054 ; + END + END rw0_wd_in[1697] + PIN rw0_wd_in[1698] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.527 0.000 121.545 0.054 ; + END + END rw0_wd_in[1698] + PIN rw0_wd_in[1699] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.707 0.000 121.725 0.054 ; + END + END rw0_wd_in[1699] + PIN rw0_wd_in[1700] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.887 0.000 121.905 0.054 ; + END + END rw0_wd_in[1700] + PIN rw0_wd_in[1701] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.067 0.000 122.085 0.054 ; + END + END rw0_wd_in[1701] + PIN rw0_wd_in[1702] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.247 0.000 122.265 0.054 ; + END + END rw0_wd_in[1702] + PIN rw0_wd_in[1703] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.427 0.000 122.445 0.054 ; + END + END rw0_wd_in[1703] + PIN rw0_wd_in[1704] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 0.000 122.625 0.054 ; + END + END rw0_wd_in[1704] + PIN rw0_wd_in[1705] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.787 0.000 122.805 0.054 ; + END + END rw0_wd_in[1705] + PIN rw0_wd_in[1706] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.967 0.000 122.985 0.054 ; + END + END rw0_wd_in[1706] + PIN rw0_wd_in[1707] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.147 0.000 123.165 0.054 ; + END + END rw0_wd_in[1707] + PIN rw0_wd_in[1708] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.327 0.000 123.345 0.054 ; + END + END rw0_wd_in[1708] + PIN rw0_wd_in[1709] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.507 0.000 123.525 0.054 ; + END + END rw0_wd_in[1709] + PIN rw0_wd_in[1710] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.687 0.000 123.705 0.054 ; + END + END rw0_wd_in[1710] + PIN rw0_wd_in[1711] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.867 0.000 123.885 0.054 ; + END + END rw0_wd_in[1711] + PIN rw0_wd_in[1712] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 0.000 124.065 0.054 ; + END + END rw0_wd_in[1712] + PIN rw0_wd_in[1713] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.227 0.000 124.245 0.054 ; + END + END rw0_wd_in[1713] + PIN rw0_wd_in[1714] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.407 0.000 124.425 0.054 ; + END + END rw0_wd_in[1714] + PIN rw0_wd_in[1715] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.587 0.000 124.605 0.054 ; + END + END rw0_wd_in[1715] + PIN rw0_wd_in[1716] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.767 0.000 124.785 0.054 ; + END + END rw0_wd_in[1716] + PIN rw0_wd_in[1717] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.947 0.000 124.965 0.054 ; + END + END rw0_wd_in[1717] + PIN rw0_wd_in[1718] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.127 0.000 125.145 0.054 ; + END + END rw0_wd_in[1718] + PIN rw0_wd_in[1719] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.307 0.000 125.325 0.054 ; + END + END rw0_wd_in[1719] + PIN rw0_wd_in[1720] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 0.000 125.505 0.054 ; + END + END rw0_wd_in[1720] + PIN rw0_wd_in[1721] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.667 0.000 125.685 0.054 ; + END + END rw0_wd_in[1721] + PIN rw0_wd_in[1722] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.847 0.000 125.865 0.054 ; + END + END rw0_wd_in[1722] + PIN rw0_wd_in[1723] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.027 0.000 126.045 0.054 ; + END + END rw0_wd_in[1723] + PIN rw0_wd_in[1724] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.207 0.000 126.225 0.054 ; + END + END rw0_wd_in[1724] + PIN rw0_wd_in[1725] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.387 0.000 126.405 0.054 ; + END + END rw0_wd_in[1725] + PIN rw0_wd_in[1726] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.567 0.000 126.585 0.054 ; + END + END rw0_wd_in[1726] + PIN rw0_wd_in[1727] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.747 0.000 126.765 0.054 ; + END + END rw0_wd_in[1727] + PIN rw0_wd_in[1728] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 0.000 126.945 0.054 ; + END + END rw0_wd_in[1728] + PIN rw0_wd_in[1729] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.107 0.000 127.125 0.054 ; + END + END rw0_wd_in[1729] + PIN rw0_wd_in[1730] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.287 0.000 127.305 0.054 ; + END + END rw0_wd_in[1730] + PIN rw0_wd_in[1731] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.467 0.000 127.485 0.054 ; + END + END rw0_wd_in[1731] + PIN rw0_wd_in[1732] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.647 0.000 127.665 0.054 ; + END + END rw0_wd_in[1732] + PIN rw0_wd_in[1733] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.827 0.000 127.845 0.054 ; + END + END rw0_wd_in[1733] + PIN rw0_wd_in[1734] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.007 0.000 128.025 0.054 ; + END + END rw0_wd_in[1734] + PIN rw0_wd_in[1735] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.187 0.000 128.205 0.054 ; + END + END rw0_wd_in[1735] + PIN rw0_wd_in[1736] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 0.000 128.385 0.054 ; + END + END rw0_wd_in[1736] + PIN rw0_wd_in[1737] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.547 0.000 128.565 0.054 ; + END + END rw0_wd_in[1737] + PIN rw0_wd_in[1738] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.727 0.000 128.745 0.054 ; + END + END rw0_wd_in[1738] + PIN rw0_wd_in[1739] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.907 0.000 128.925 0.054 ; + END + END rw0_wd_in[1739] + PIN rw0_wd_in[1740] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.087 0.000 129.105 0.054 ; + END + END rw0_wd_in[1740] + PIN rw0_wd_in[1741] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.267 0.000 129.285 0.054 ; + END + END rw0_wd_in[1741] + PIN rw0_wd_in[1742] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.447 0.000 129.465 0.054 ; + END + END rw0_wd_in[1742] + PIN rw0_wd_in[1743] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.627 0.000 129.645 0.054 ; + END + END rw0_wd_in[1743] + PIN rw0_wd_in[1744] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 0.000 129.825 0.054 ; + END + END rw0_wd_in[1744] + PIN rw0_wd_in[1745] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.987 0.000 130.005 0.054 ; + END + END rw0_wd_in[1745] + PIN rw0_wd_in[1746] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.167 0.000 130.185 0.054 ; + END + END rw0_wd_in[1746] + PIN rw0_wd_in[1747] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.347 0.000 130.365 0.054 ; + END + END rw0_wd_in[1747] + PIN rw0_wd_in[1748] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.527 0.000 130.545 0.054 ; + END + END rw0_wd_in[1748] + PIN rw0_wd_in[1749] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.707 0.000 130.725 0.054 ; + END + END rw0_wd_in[1749] + PIN rw0_wd_in[1750] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.887 0.000 130.905 0.054 ; + END + END rw0_wd_in[1750] + PIN rw0_wd_in[1751] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.067 0.000 131.085 0.054 ; + END + END rw0_wd_in[1751] + PIN rw0_wd_in[1752] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 0.000 131.265 0.054 ; + END + END rw0_wd_in[1752] + PIN rw0_wd_in[1753] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.427 0.000 131.445 0.054 ; + END + END rw0_wd_in[1753] + PIN rw0_wd_in[1754] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.607 0.000 131.625 0.054 ; + END + END rw0_wd_in[1754] + PIN rw0_wd_in[1755] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.787 0.000 131.805 0.054 ; + END + END rw0_wd_in[1755] + PIN rw0_wd_in[1756] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.967 0.000 131.985 0.054 ; + END + END rw0_wd_in[1756] + PIN rw0_wd_in[1757] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.147 0.000 132.165 0.054 ; + END + END rw0_wd_in[1757] + PIN rw0_wd_in[1758] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.327 0.000 132.345 0.054 ; + END + END rw0_wd_in[1758] + PIN rw0_wd_in[1759] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.507 0.000 132.525 0.054 ; + END + END rw0_wd_in[1759] + PIN rw0_wd_in[1760] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 0.000 132.705 0.054 ; + END + END rw0_wd_in[1760] + PIN rw0_wd_in[1761] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.867 0.000 132.885 0.054 ; + END + END rw0_wd_in[1761] + PIN rw0_wd_in[1762] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.047 0.000 133.065 0.054 ; + END + END rw0_wd_in[1762] + PIN rw0_wd_in[1763] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.227 0.000 133.245 0.054 ; + END + END rw0_wd_in[1763] + PIN rw0_wd_in[1764] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.407 0.000 133.425 0.054 ; + END + END rw0_wd_in[1764] + PIN rw0_wd_in[1765] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.587 0.000 133.605 0.054 ; + END + END rw0_wd_in[1765] + PIN rw0_wd_in[1766] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.767 0.000 133.785 0.054 ; + END + END rw0_wd_in[1766] + PIN rw0_wd_in[1767] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.947 0.000 133.965 0.054 ; + END + END rw0_wd_in[1767] + PIN rw0_wd_in[1768] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 0.000 134.145 0.054 ; + END + END rw0_wd_in[1768] + PIN rw0_wd_in[1769] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.307 0.000 134.325 0.054 ; + END + END rw0_wd_in[1769] + PIN rw0_wd_in[1770] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.487 0.000 134.505 0.054 ; + END + END rw0_wd_in[1770] + PIN rw0_wd_in[1771] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.667 0.000 134.685 0.054 ; + END + END rw0_wd_in[1771] + PIN rw0_wd_in[1772] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.847 0.000 134.865 0.054 ; + END + END rw0_wd_in[1772] + PIN rw0_wd_in[1773] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.027 0.000 135.045 0.054 ; + END + END rw0_wd_in[1773] + PIN rw0_wd_in[1774] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.207 0.000 135.225 0.054 ; + END + END rw0_wd_in[1774] + PIN rw0_wd_in[1775] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.387 0.000 135.405 0.054 ; + END + END rw0_wd_in[1775] + PIN rw0_wd_in[1776] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 0.000 135.585 0.054 ; + END + END rw0_wd_in[1776] + PIN rw0_wd_in[1777] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.747 0.000 135.765 0.054 ; + END + END rw0_wd_in[1777] + PIN rw0_wd_in[1778] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.927 0.000 135.945 0.054 ; + END + END rw0_wd_in[1778] + PIN rw0_wd_in[1779] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.107 0.000 136.125 0.054 ; + END + END rw0_wd_in[1779] + PIN rw0_wd_in[1780] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.287 0.000 136.305 0.054 ; + END + END rw0_wd_in[1780] + PIN rw0_wd_in[1781] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.467 0.000 136.485 0.054 ; + END + END rw0_wd_in[1781] + PIN rw0_wd_in[1782] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.647 0.000 136.665 0.054 ; + END + END rw0_wd_in[1782] + PIN rw0_wd_in[1783] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.827 0.000 136.845 0.054 ; + END + END rw0_wd_in[1783] + PIN rw0_wd_in[1784] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 0.000 137.025 0.054 ; + END + END rw0_wd_in[1784] + PIN rw0_wd_in[1785] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.187 0.000 137.205 0.054 ; + END + END rw0_wd_in[1785] + PIN rw0_wd_in[1786] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.367 0.000 137.385 0.054 ; + END + END rw0_wd_in[1786] + PIN rw0_wd_in[1787] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.547 0.000 137.565 0.054 ; + END + END rw0_wd_in[1787] + PIN rw0_wd_in[1788] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.727 0.000 137.745 0.054 ; + END + END rw0_wd_in[1788] + PIN rw0_wd_in[1789] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.907 0.000 137.925 0.054 ; + END + END rw0_wd_in[1789] + PIN rw0_wd_in[1790] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.087 0.000 138.105 0.054 ; + END + END rw0_wd_in[1790] + PIN rw0_wd_in[1791] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.267 0.000 138.285 0.054 ; + END + END rw0_wd_in[1791] + PIN rw0_wd_in[1792] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 0.000 138.465 0.054 ; + END + END rw0_wd_in[1792] + PIN rw0_wd_in[1793] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.627 0.000 138.645 0.054 ; + END + END rw0_wd_in[1793] + PIN rw0_wd_in[1794] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.807 0.000 138.825 0.054 ; + END + END rw0_wd_in[1794] + PIN rw0_wd_in[1795] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.987 0.000 139.005 0.054 ; + END + END rw0_wd_in[1795] + PIN rw0_wd_in[1796] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.167 0.000 139.185 0.054 ; + END + END rw0_wd_in[1796] + PIN rw0_wd_in[1797] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.347 0.000 139.365 0.054 ; + END + END rw0_wd_in[1797] + PIN rw0_wd_in[1798] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.527 0.000 139.545 0.054 ; + END + END rw0_wd_in[1798] + PIN rw0_wd_in[1799] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.707 0.000 139.725 0.054 ; + END + END rw0_wd_in[1799] + PIN rw0_wd_in[1800] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 0.000 139.905 0.054 ; + END + END rw0_wd_in[1800] + PIN rw0_wd_in[1801] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.067 0.000 140.085 0.054 ; + END + END rw0_wd_in[1801] + PIN rw0_wd_in[1802] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.247 0.000 140.265 0.054 ; + END + END rw0_wd_in[1802] + PIN rw0_wd_in[1803] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.427 0.000 140.445 0.054 ; + END + END rw0_wd_in[1803] + PIN rw0_wd_in[1804] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.607 0.000 140.625 0.054 ; + END + END rw0_wd_in[1804] + PIN rw0_wd_in[1805] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.787 0.000 140.805 0.054 ; + END + END rw0_wd_in[1805] + PIN rw0_wd_in[1806] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.967 0.000 140.985 0.054 ; + END + END rw0_wd_in[1806] + PIN rw0_wd_in[1807] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.147 0.000 141.165 0.054 ; + END + END rw0_wd_in[1807] + PIN rw0_wd_in[1808] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 0.000 141.345 0.054 ; + END + END rw0_wd_in[1808] + PIN rw0_wd_in[1809] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.507 0.000 141.525 0.054 ; + END + END rw0_wd_in[1809] + PIN rw0_wd_in[1810] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.687 0.000 141.705 0.054 ; + END + END rw0_wd_in[1810] + PIN rw0_wd_in[1811] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.867 0.000 141.885 0.054 ; + END + END rw0_wd_in[1811] + PIN rw0_wd_in[1812] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.047 0.000 142.065 0.054 ; + END + END rw0_wd_in[1812] + PIN rw0_wd_in[1813] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.227 0.000 142.245 0.054 ; + END + END rw0_wd_in[1813] + PIN rw0_wd_in[1814] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.407 0.000 142.425 0.054 ; + END + END rw0_wd_in[1814] + PIN rw0_wd_in[1815] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.587 0.000 142.605 0.054 ; + END + END rw0_wd_in[1815] + PIN rw0_wd_in[1816] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 0.000 142.785 0.054 ; + END + END rw0_wd_in[1816] + PIN rw0_wd_in[1817] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.947 0.000 142.965 0.054 ; + END + END rw0_wd_in[1817] + PIN rw0_wd_in[1818] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.127 0.000 143.145 0.054 ; + END + END rw0_wd_in[1818] + PIN rw0_wd_in[1819] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.307 0.000 143.325 0.054 ; + END + END rw0_wd_in[1819] + PIN rw0_wd_in[1820] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.487 0.000 143.505 0.054 ; + END + END rw0_wd_in[1820] + PIN rw0_wd_in[1821] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.667 0.000 143.685 0.054 ; + END + END rw0_wd_in[1821] + PIN rw0_wd_in[1822] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.847 0.000 143.865 0.054 ; + END + END rw0_wd_in[1822] + PIN rw0_wd_in[1823] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.027 0.000 144.045 0.054 ; + END + END rw0_wd_in[1823] + PIN rw0_wd_in[1824] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 0.000 144.225 0.054 ; + END + END rw0_wd_in[1824] + PIN rw0_wd_in[1825] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.387 0.000 144.405 0.054 ; + END + END rw0_wd_in[1825] + PIN rw0_wd_in[1826] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.567 0.000 144.585 0.054 ; + END + END rw0_wd_in[1826] + PIN rw0_wd_in[1827] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.747 0.000 144.765 0.054 ; + END + END rw0_wd_in[1827] + PIN rw0_wd_in[1828] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.927 0.000 144.945 0.054 ; + END + END rw0_wd_in[1828] + PIN rw0_wd_in[1829] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.107 0.000 145.125 0.054 ; + END + END rw0_wd_in[1829] + PIN rw0_wd_in[1830] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.287 0.000 145.305 0.054 ; + END + END rw0_wd_in[1830] + PIN rw0_wd_in[1831] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.467 0.000 145.485 0.054 ; + END + END rw0_wd_in[1831] + PIN rw0_wd_in[1832] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 0.000 145.665 0.054 ; + END + END rw0_wd_in[1832] + PIN rw0_wd_in[1833] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.827 0.000 145.845 0.054 ; + END + END rw0_wd_in[1833] + PIN rw0_wd_in[1834] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.007 0.000 146.025 0.054 ; + END + END rw0_wd_in[1834] + PIN rw0_wd_in[1835] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.187 0.000 146.205 0.054 ; + END + END rw0_wd_in[1835] + PIN rw0_wd_in[1836] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.367 0.000 146.385 0.054 ; + END + END rw0_wd_in[1836] + PIN rw0_wd_in[1837] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.547 0.000 146.565 0.054 ; + END + END rw0_wd_in[1837] + PIN rw0_wd_in[1838] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.727 0.000 146.745 0.054 ; + END + END rw0_wd_in[1838] + PIN rw0_wd_in[1839] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.907 0.000 146.925 0.054 ; + END + END rw0_wd_in[1839] + PIN rw0_wd_in[1840] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 0.000 147.105 0.054 ; + END + END rw0_wd_in[1840] + PIN rw0_wd_in[1841] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.267 0.000 147.285 0.054 ; + END + END rw0_wd_in[1841] + PIN rw0_wd_in[1842] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.447 0.000 147.465 0.054 ; + END + END rw0_wd_in[1842] + PIN rw0_wd_in[1843] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.627 0.000 147.645 0.054 ; + END + END rw0_wd_in[1843] + PIN rw0_wd_in[1844] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.807 0.000 147.825 0.054 ; + END + END rw0_wd_in[1844] + PIN rw0_wd_in[1845] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.987 0.000 148.005 0.054 ; + END + END rw0_wd_in[1845] + PIN rw0_wd_in[1846] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.167 0.000 148.185 0.054 ; + END + END rw0_wd_in[1846] + PIN rw0_wd_in[1847] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.347 0.000 148.365 0.054 ; + END + END rw0_wd_in[1847] + PIN rw0_wd_in[1848] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 0.000 148.545 0.054 ; + END + END rw0_wd_in[1848] + PIN rw0_wd_in[1849] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.707 0.000 148.725 0.054 ; + END + END rw0_wd_in[1849] + PIN rw0_wd_in[1850] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.887 0.000 148.905 0.054 ; + END + END rw0_wd_in[1850] + PIN rw0_wd_in[1851] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.067 0.000 149.085 0.054 ; + END + END rw0_wd_in[1851] + PIN rw0_wd_in[1852] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.247 0.000 149.265 0.054 ; + END + END rw0_wd_in[1852] + PIN rw0_wd_in[1853] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.427 0.000 149.445 0.054 ; + END + END rw0_wd_in[1853] + PIN rw0_wd_in[1854] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.607 0.000 149.625 0.054 ; + END + END rw0_wd_in[1854] + PIN rw0_wd_in[1855] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.787 0.000 149.805 0.054 ; + END + END rw0_wd_in[1855] + PIN rw0_wd_in[1856] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 0.000 149.985 0.054 ; + END + END rw0_wd_in[1856] + PIN rw0_wd_in[1857] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.147 0.000 150.165 0.054 ; + END + END rw0_wd_in[1857] + PIN rw0_wd_in[1858] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.327 0.000 150.345 0.054 ; + END + END rw0_wd_in[1858] + PIN rw0_wd_in[1859] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.507 0.000 150.525 0.054 ; + END + END rw0_wd_in[1859] + PIN rw0_wd_in[1860] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.687 0.000 150.705 0.054 ; + END + END rw0_wd_in[1860] + PIN rw0_wd_in[1861] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.867 0.000 150.885 0.054 ; + END + END rw0_wd_in[1861] + PIN rw0_wd_in[1862] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.047 0.000 151.065 0.054 ; + END + END rw0_wd_in[1862] + PIN rw0_wd_in[1863] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.227 0.000 151.245 0.054 ; + END + END rw0_wd_in[1863] + PIN rw0_wd_in[1864] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 0.000 151.425 0.054 ; + END + END rw0_wd_in[1864] + PIN rw0_wd_in[1865] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.587 0.000 151.605 0.054 ; + END + END rw0_wd_in[1865] + PIN rw0_wd_in[1866] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.767 0.000 151.785 0.054 ; + END + END rw0_wd_in[1866] + PIN rw0_wd_in[1867] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.947 0.000 151.965 0.054 ; + END + END rw0_wd_in[1867] + PIN rw0_wd_in[1868] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.127 0.000 152.145 0.054 ; + END + END rw0_wd_in[1868] + PIN rw0_wd_in[1869] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.307 0.000 152.325 0.054 ; + END + END rw0_wd_in[1869] + PIN rw0_wd_in[1870] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.487 0.000 152.505 0.054 ; + END + END rw0_wd_in[1870] + PIN rw0_wd_in[1871] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.667 0.000 152.685 0.054 ; + END + END rw0_wd_in[1871] + PIN rw0_wd_in[1872] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 0.000 152.865 0.054 ; + END + END rw0_wd_in[1872] + PIN rw0_wd_in[1873] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.027 0.000 153.045 0.054 ; + END + END rw0_wd_in[1873] + PIN rw0_wd_in[1874] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.207 0.000 153.225 0.054 ; + END + END rw0_wd_in[1874] + PIN rw0_wd_in[1875] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.387 0.000 153.405 0.054 ; + END + END rw0_wd_in[1875] + PIN rw0_wd_in[1876] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.567 0.000 153.585 0.054 ; + END + END rw0_wd_in[1876] + PIN rw0_wd_in[1877] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.747 0.000 153.765 0.054 ; + END + END rw0_wd_in[1877] + PIN rw0_wd_in[1878] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.927 0.000 153.945 0.054 ; + END + END rw0_wd_in[1878] + PIN rw0_wd_in[1879] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.107 0.000 154.125 0.054 ; + END + END rw0_wd_in[1879] + PIN rw0_wd_in[1880] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 0.000 154.305 0.054 ; + END + END rw0_wd_in[1880] + PIN rw0_wd_in[1881] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.467 0.000 154.485 0.054 ; + END + END rw0_wd_in[1881] + PIN rw0_wd_in[1882] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.647 0.000 154.665 0.054 ; + END + END rw0_wd_in[1882] + PIN rw0_wd_in[1883] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.827 0.000 154.845 0.054 ; + END + END rw0_wd_in[1883] + PIN rw0_wd_in[1884] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.007 0.000 155.025 0.054 ; + END + END rw0_wd_in[1884] + PIN rw0_wd_in[1885] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.187 0.000 155.205 0.054 ; + END + END rw0_wd_in[1885] + PIN rw0_wd_in[1886] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.367 0.000 155.385 0.054 ; + END + END rw0_wd_in[1886] + PIN rw0_wd_in[1887] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.547 0.000 155.565 0.054 ; + END + END rw0_wd_in[1887] + PIN rw0_wd_in[1888] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 0.000 155.745 0.054 ; + END + END rw0_wd_in[1888] + PIN rw0_wd_in[1889] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.907 0.000 155.925 0.054 ; + END + END rw0_wd_in[1889] + PIN rw0_wd_in[1890] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.087 0.000 156.105 0.054 ; + END + END rw0_wd_in[1890] + PIN rw0_wd_in[1891] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.267 0.000 156.285 0.054 ; + END + END rw0_wd_in[1891] + PIN rw0_wd_in[1892] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.447 0.000 156.465 0.054 ; + END + END rw0_wd_in[1892] + PIN rw0_wd_in[1893] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.627 0.000 156.645 0.054 ; + END + END rw0_wd_in[1893] + PIN rw0_wd_in[1894] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.807 0.000 156.825 0.054 ; + END + END rw0_wd_in[1894] + PIN rw0_wd_in[1895] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.987 0.000 157.005 0.054 ; + END + END rw0_wd_in[1895] + PIN rw0_wd_in[1896] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 0.000 157.185 0.054 ; + END + END rw0_wd_in[1896] + PIN rw0_wd_in[1897] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.347 0.000 157.365 0.054 ; + END + END rw0_wd_in[1897] + PIN rw0_wd_in[1898] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.527 0.000 157.545 0.054 ; + END + END rw0_wd_in[1898] + PIN rw0_wd_in[1899] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.707 0.000 157.725 0.054 ; + END + END rw0_wd_in[1899] + PIN rw0_wd_in[1900] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.887 0.000 157.905 0.054 ; + END + END rw0_wd_in[1900] + PIN rw0_wd_in[1901] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.067 0.000 158.085 0.054 ; + END + END rw0_wd_in[1901] + PIN rw0_wd_in[1902] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.247 0.000 158.265 0.054 ; + END + END rw0_wd_in[1902] + PIN rw0_wd_in[1903] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.427 0.000 158.445 0.054 ; + END + END rw0_wd_in[1903] + PIN rw0_wd_in[1904] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 0.000 158.625 0.054 ; + END + END rw0_wd_in[1904] + PIN rw0_wd_in[1905] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.787 0.000 158.805 0.054 ; + END + END rw0_wd_in[1905] + PIN rw0_wd_in[1906] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.967 0.000 158.985 0.054 ; + END + END rw0_wd_in[1906] + PIN rw0_wd_in[1907] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.147 0.000 159.165 0.054 ; + END + END rw0_wd_in[1907] + PIN rw0_wd_in[1908] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.327 0.000 159.345 0.054 ; + END + END rw0_wd_in[1908] + PIN rw0_wd_in[1909] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.507 0.000 159.525 0.054 ; + END + END rw0_wd_in[1909] + PIN rw0_wd_in[1910] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.687 0.000 159.705 0.054 ; + END + END rw0_wd_in[1910] + PIN rw0_wd_in[1911] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.867 0.000 159.885 0.054 ; + END + END rw0_wd_in[1911] + PIN rw0_wd_in[1912] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 0.000 160.065 0.054 ; + END + END rw0_wd_in[1912] + PIN rw0_wd_in[1913] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.227 0.000 160.245 0.054 ; + END + END rw0_wd_in[1913] + PIN rw0_wd_in[1914] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.407 0.000 160.425 0.054 ; + END + END rw0_wd_in[1914] + PIN rw0_wd_in[1915] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.587 0.000 160.605 0.054 ; + END + END rw0_wd_in[1915] + PIN rw0_wd_in[1916] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.767 0.000 160.785 0.054 ; + END + END rw0_wd_in[1916] + PIN rw0_wd_in[1917] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.947 0.000 160.965 0.054 ; + END + END rw0_wd_in[1917] + PIN rw0_wd_in[1918] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.127 0.000 161.145 0.054 ; + END + END rw0_wd_in[1918] + PIN rw0_wd_in[1919] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.307 0.000 161.325 0.054 ; + END + END rw0_wd_in[1919] + PIN rw0_wd_in[1920] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 0.000 161.505 0.054 ; + END + END rw0_wd_in[1920] + PIN rw0_wd_in[1921] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.667 0.000 161.685 0.054 ; + END + END rw0_wd_in[1921] + PIN rw0_wd_in[1922] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.847 0.000 161.865 0.054 ; + END + END rw0_wd_in[1922] + PIN rw0_wd_in[1923] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.027 0.000 162.045 0.054 ; + END + END rw0_wd_in[1923] + PIN rw0_wd_in[1924] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.207 0.000 162.225 0.054 ; + END + END rw0_wd_in[1924] + PIN rw0_wd_in[1925] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.387 0.000 162.405 0.054 ; + END + END rw0_wd_in[1925] + PIN rw0_wd_in[1926] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.567 0.000 162.585 0.054 ; + END + END rw0_wd_in[1926] + PIN rw0_wd_in[1927] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.747 0.000 162.765 0.054 ; + END + END rw0_wd_in[1927] + PIN rw0_wd_in[1928] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 0.000 162.945 0.054 ; + END + END rw0_wd_in[1928] + PIN rw0_wd_in[1929] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.107 0.000 163.125 0.054 ; + END + END rw0_wd_in[1929] + PIN rw0_wd_in[1930] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.287 0.000 163.305 0.054 ; + END + END rw0_wd_in[1930] + PIN rw0_wd_in[1931] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.467 0.000 163.485 0.054 ; + END + END rw0_wd_in[1931] + PIN rw0_wd_in[1932] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.647 0.000 163.665 0.054 ; + END + END rw0_wd_in[1932] + PIN rw0_wd_in[1933] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.827 0.000 163.845 0.054 ; + END + END rw0_wd_in[1933] + PIN rw0_wd_in[1934] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.007 0.000 164.025 0.054 ; + END + END rw0_wd_in[1934] + PIN rw0_wd_in[1935] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.187 0.000 164.205 0.054 ; + END + END rw0_wd_in[1935] + PIN rw0_wd_in[1936] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 0.000 164.385 0.054 ; + END + END rw0_wd_in[1936] + PIN rw0_wd_in[1937] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.547 0.000 164.565 0.054 ; + END + END rw0_wd_in[1937] + PIN rw0_wd_in[1938] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.727 0.000 164.745 0.054 ; + END + END rw0_wd_in[1938] + PIN rw0_wd_in[1939] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.907 0.000 164.925 0.054 ; + END + END rw0_wd_in[1939] + PIN rw0_wd_in[1940] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.087 0.000 165.105 0.054 ; + END + END rw0_wd_in[1940] + PIN rw0_wd_in[1941] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.267 0.000 165.285 0.054 ; + END + END rw0_wd_in[1941] + PIN rw0_wd_in[1942] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.447 0.000 165.465 0.054 ; + END + END rw0_wd_in[1942] + PIN rw0_wd_in[1943] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.627 0.000 165.645 0.054 ; + END + END rw0_wd_in[1943] + PIN rw0_wd_in[1944] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 0.000 165.825 0.054 ; + END + END rw0_wd_in[1944] + PIN rw0_wd_in[1945] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.987 0.000 166.005 0.054 ; + END + END rw0_wd_in[1945] + PIN rw0_wd_in[1946] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.167 0.000 166.185 0.054 ; + END + END rw0_wd_in[1946] + PIN rw0_wd_in[1947] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.347 0.000 166.365 0.054 ; + END + END rw0_wd_in[1947] + PIN rw0_wd_in[1948] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.527 0.000 166.545 0.054 ; + END + END rw0_wd_in[1948] + PIN rw0_wd_in[1949] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.707 0.000 166.725 0.054 ; + END + END rw0_wd_in[1949] + PIN rw0_wd_in[1950] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.887 0.000 166.905 0.054 ; + END + END rw0_wd_in[1950] + PIN rw0_wd_in[1951] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.067 0.000 167.085 0.054 ; + END + END rw0_wd_in[1951] + PIN rw0_wd_in[1952] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 0.000 167.265 0.054 ; + END + END rw0_wd_in[1952] + PIN rw0_wd_in[1953] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.427 0.000 167.445 0.054 ; + END + END rw0_wd_in[1953] + PIN rw0_wd_in[1954] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.607 0.000 167.625 0.054 ; + END + END rw0_wd_in[1954] + PIN rw0_wd_in[1955] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.787 0.000 167.805 0.054 ; + END + END rw0_wd_in[1955] + PIN rw0_wd_in[1956] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.967 0.000 167.985 0.054 ; + END + END rw0_wd_in[1956] + PIN rw0_wd_in[1957] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.147 0.000 168.165 0.054 ; + END + END rw0_wd_in[1957] + PIN rw0_wd_in[1958] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.327 0.000 168.345 0.054 ; + END + END rw0_wd_in[1958] + PIN rw0_wd_in[1959] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.507 0.000 168.525 0.054 ; + END + END rw0_wd_in[1959] + PIN rw0_wd_in[1960] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 0.000 168.705 0.054 ; + END + END rw0_wd_in[1960] + PIN rw0_wd_in[1961] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.867 0.000 168.885 0.054 ; + END + END rw0_wd_in[1961] + PIN rw0_wd_in[1962] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.047 0.000 169.065 0.054 ; + END + END rw0_wd_in[1962] + PIN rw0_wd_in[1963] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.227 0.000 169.245 0.054 ; + END + END rw0_wd_in[1963] + PIN rw0_wd_in[1964] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.407 0.000 169.425 0.054 ; + END + END rw0_wd_in[1964] + PIN rw0_wd_in[1965] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.587 0.000 169.605 0.054 ; + END + END rw0_wd_in[1965] + PIN rw0_wd_in[1966] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.767 0.000 169.785 0.054 ; + END + END rw0_wd_in[1966] + PIN rw0_wd_in[1967] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.947 0.000 169.965 0.054 ; + END + END rw0_wd_in[1967] + PIN rw0_wd_in[1968] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 0.000 170.145 0.054 ; + END + END rw0_wd_in[1968] + PIN rw0_wd_in[1969] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.307 0.000 170.325 0.054 ; + END + END rw0_wd_in[1969] + PIN rw0_wd_in[1970] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.487 0.000 170.505 0.054 ; + END + END rw0_wd_in[1970] + PIN rw0_wd_in[1971] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.667 0.000 170.685 0.054 ; + END + END rw0_wd_in[1971] + PIN rw0_wd_in[1972] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.847 0.000 170.865 0.054 ; + END + END rw0_wd_in[1972] + PIN rw0_wd_in[1973] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.027 0.000 171.045 0.054 ; + END + END rw0_wd_in[1973] + PIN rw0_wd_in[1974] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.207 0.000 171.225 0.054 ; + END + END rw0_wd_in[1974] + PIN rw0_wd_in[1975] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.387 0.000 171.405 0.054 ; + END + END rw0_wd_in[1975] + PIN rw0_wd_in[1976] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 0.000 171.585 0.054 ; + END + END rw0_wd_in[1976] + PIN rw0_wd_in[1977] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.747 0.000 171.765 0.054 ; + END + END rw0_wd_in[1977] + PIN rw0_wd_in[1978] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.927 0.000 171.945 0.054 ; + END + END rw0_wd_in[1978] + PIN rw0_wd_in[1979] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.107 0.000 172.125 0.054 ; + END + END rw0_wd_in[1979] + PIN rw0_wd_in[1980] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.287 0.000 172.305 0.054 ; + END + END rw0_wd_in[1980] + PIN rw0_wd_in[1981] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.467 0.000 172.485 0.054 ; + END + END rw0_wd_in[1981] + PIN rw0_wd_in[1982] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.647 0.000 172.665 0.054 ; + END + END rw0_wd_in[1982] + PIN rw0_wd_in[1983] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.827 0.000 172.845 0.054 ; + END + END rw0_wd_in[1983] + PIN rw0_wd_in[1984] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.007 0.000 173.025 0.054 ; + END + END rw0_wd_in[1984] + PIN rw0_wd_in[1985] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.187 0.000 173.205 0.054 ; + END + END rw0_wd_in[1985] + PIN rw0_wd_in[1986] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.367 0.000 173.385 0.054 ; + END + END rw0_wd_in[1986] + PIN rw0_wd_in[1987] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.547 0.000 173.565 0.054 ; + END + END rw0_wd_in[1987] + PIN rw0_wd_in[1988] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.727 0.000 173.745 0.054 ; + END + END rw0_wd_in[1988] + PIN rw0_wd_in[1989] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.907 0.000 173.925 0.054 ; + END + END rw0_wd_in[1989] + PIN rw0_wd_in[1990] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.087 0.000 174.105 0.054 ; + END + END rw0_wd_in[1990] + PIN rw0_wd_in[1991] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.267 0.000 174.285 0.054 ; + END + END rw0_wd_in[1991] + PIN rw0_wd_in[1992] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.447 0.000 174.465 0.054 ; + END + END rw0_wd_in[1992] + PIN rw0_wd_in[1993] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.627 0.000 174.645 0.054 ; + END + END rw0_wd_in[1993] + PIN rw0_wd_in[1994] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.807 0.000 174.825 0.054 ; + END + END rw0_wd_in[1994] + PIN rw0_wd_in[1995] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.987 0.000 175.005 0.054 ; + END + END rw0_wd_in[1995] + PIN rw0_wd_in[1996] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.167 0.000 175.185 0.054 ; + END + END rw0_wd_in[1996] + PIN rw0_wd_in[1997] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.347 0.000 175.365 0.054 ; + END + END rw0_wd_in[1997] + PIN rw0_wd_in[1998] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.527 0.000 175.545 0.054 ; + END + END rw0_wd_in[1998] + PIN rw0_wd_in[1999] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.707 0.000 175.725 0.054 ; + END + END rw0_wd_in[1999] + PIN rw0_wd_in[2000] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.887 0.000 175.905 0.054 ; + END + END rw0_wd_in[2000] + PIN rw0_wd_in[2001] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.067 0.000 176.085 0.054 ; + END + END rw0_wd_in[2001] + PIN rw0_wd_in[2002] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.247 0.000 176.265 0.054 ; + END + END rw0_wd_in[2002] + PIN rw0_wd_in[2003] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.427 0.000 176.445 0.054 ; + END + END rw0_wd_in[2003] + PIN rw0_wd_in[2004] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.607 0.000 176.625 0.054 ; + END + END rw0_wd_in[2004] + PIN rw0_wd_in[2005] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.787 0.000 176.805 0.054 ; + END + END rw0_wd_in[2005] + PIN rw0_wd_in[2006] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.967 0.000 176.985 0.054 ; + END + END rw0_wd_in[2006] + PIN rw0_wd_in[2007] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.147 0.000 177.165 0.054 ; + END + END rw0_wd_in[2007] + PIN rw0_wd_in[2008] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.327 0.000 177.345 0.054 ; + END + END rw0_wd_in[2008] + PIN rw0_wd_in[2009] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.507 0.000 177.525 0.054 ; + END + END rw0_wd_in[2009] + PIN rw0_wd_in[2010] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.687 0.000 177.705 0.054 ; + END + END rw0_wd_in[2010] + PIN rw0_wd_in[2011] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.867 0.000 177.885 0.054 ; + END + END rw0_wd_in[2011] + PIN rw0_wd_in[2012] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.047 0.000 178.065 0.054 ; + END + END rw0_wd_in[2012] + PIN rw0_wd_in[2013] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.227 0.000 178.245 0.054 ; + END + END rw0_wd_in[2013] + PIN rw0_wd_in[2014] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.407 0.000 178.425 0.054 ; + END + END rw0_wd_in[2014] + PIN rw0_wd_in[2015] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.587 0.000 178.605 0.054 ; + END + END rw0_wd_in[2015] + PIN rw0_wd_in[2016] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.767 0.000 178.785 0.054 ; + END + END rw0_wd_in[2016] + PIN rw0_wd_in[2017] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.947 0.000 178.965 0.054 ; + END + END rw0_wd_in[2017] + PIN rw0_wd_in[2018] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.127 0.000 179.145 0.054 ; + END + END rw0_wd_in[2018] + PIN rw0_wd_in[2019] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.307 0.000 179.325 0.054 ; + END + END rw0_wd_in[2019] + PIN rw0_wd_in[2020] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.487 0.000 179.505 0.054 ; + END + END rw0_wd_in[2020] + PIN rw0_wd_in[2021] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.667 0.000 179.685 0.054 ; + END + END rw0_wd_in[2021] + PIN rw0_wd_in[2022] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.847 0.000 179.865 0.054 ; + END + END rw0_wd_in[2022] + PIN rw0_wd_in[2023] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.027 0.000 180.045 0.054 ; + END + END rw0_wd_in[2023] + PIN rw0_wd_in[2024] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.207 0.000 180.225 0.054 ; + END + END rw0_wd_in[2024] + PIN rw0_wd_in[2025] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.387 0.000 180.405 0.054 ; + END + END rw0_wd_in[2025] + PIN rw0_wd_in[2026] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.567 0.000 180.585 0.054 ; + END + END rw0_wd_in[2026] + PIN rw0_wd_in[2027] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.747 0.000 180.765 0.054 ; + END + END rw0_wd_in[2027] + PIN rw0_wd_in[2028] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.927 0.000 180.945 0.054 ; + END + END rw0_wd_in[2028] + PIN rw0_wd_in[2029] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.107 0.000 181.125 0.054 ; + END + END rw0_wd_in[2029] + PIN rw0_wd_in[2030] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.287 0.000 181.305 0.054 ; + END + END rw0_wd_in[2030] + PIN rw0_wd_in[2031] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.467 0.000 181.485 0.054 ; + END + END rw0_wd_in[2031] + PIN rw0_wd_in[2032] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.647 0.000 181.665 0.054 ; + END + END rw0_wd_in[2032] + PIN rw0_wd_in[2033] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.827 0.000 181.845 0.054 ; + END + END rw0_wd_in[2033] + PIN rw0_wd_in[2034] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.007 0.000 182.025 0.054 ; + END + END rw0_wd_in[2034] + PIN rw0_wd_in[2035] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.187 0.000 182.205 0.054 ; + END + END rw0_wd_in[2035] + PIN rw0_wd_in[2036] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.367 0.000 182.385 0.054 ; + END + END rw0_wd_in[2036] + PIN rw0_wd_in[2037] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.547 0.000 182.565 0.054 ; + END + END rw0_wd_in[2037] + PIN rw0_wd_in[2038] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.727 0.000 182.745 0.054 ; + END + END rw0_wd_in[2038] + PIN rw0_wd_in[2039] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.907 0.000 182.925 0.054 ; + END + END rw0_wd_in[2039] + PIN rw0_wd_in[2040] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.087 0.000 183.105 0.054 ; + END + END rw0_wd_in[2040] + PIN rw0_wd_in[2041] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.267 0.000 183.285 0.054 ; + END + END rw0_wd_in[2041] + PIN rw0_wd_in[2042] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.447 0.000 183.465 0.054 ; + END + END rw0_wd_in[2042] + PIN rw0_wd_in[2043] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.627 0.000 183.645 0.054 ; + END + END rw0_wd_in[2043] + PIN rw0_wd_in[2044] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.807 0.000 183.825 0.054 ; + END + END rw0_wd_in[2044] + PIN rw0_wd_in[2045] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.987 0.000 184.005 0.054 ; + END + END rw0_wd_in[2045] + PIN rw0_wd_in[2046] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.167 0.000 184.185 0.054 ; + END + END rw0_wd_in[2046] + PIN rw0_wd_in[2047] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.347 0.000 184.365 0.054 ; + END + END rw0_wd_in[2047] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.527 0.000 184.545 0.054 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.707 0.000 184.725 0.054 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.887 0.000 184.905 0.054 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.067 0.000 185.085 0.054 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.247 0.000 185.265 0.054 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.427 0.000 185.445 0.054 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.607 0.000 185.625 0.054 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.787 0.000 185.805 0.054 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.967 0.000 185.985 0.054 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.147 0.000 186.165 0.054 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.327 0.000 186.345 0.054 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.507 0.000 186.525 0.054 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.687 0.000 186.705 0.054 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.867 0.000 186.885 0.054 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.047 0.000 187.065 0.054 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.227 0.000 187.245 0.054 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.407 0.000 187.425 0.054 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.587 0.000 187.605 0.054 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.767 0.000 187.785 0.054 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.947 0.000 187.965 0.054 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.127 0.000 188.145 0.054 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.307 0.000 188.325 0.054 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.487 0.000 188.505 0.054 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.667 0.000 188.685 0.054 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.847 0.000 188.865 0.054 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.027 0.000 189.045 0.054 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.207 0.000 189.225 0.054 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.387 0.000 189.405 0.054 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.567 0.000 189.585 0.054 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.747 0.000 189.765 0.054 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.927 0.000 189.945 0.054 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.107 0.000 190.125 0.054 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.287 0.000 190.305 0.054 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.467 0.000 190.485 0.054 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.647 0.000 190.665 0.054 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.827 0.000 190.845 0.054 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.007 0.000 191.025 0.054 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.187 0.000 191.205 0.054 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.367 0.000 191.385 0.054 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.547 0.000 191.565 0.054 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.727 0.000 191.745 0.054 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.907 0.000 191.925 0.054 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.087 0.000 192.105 0.054 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.267 0.000 192.285 0.054 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.447 0.000 192.465 0.054 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.627 0.000 192.645 0.054 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.807 0.000 192.825 0.054 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.987 0.000 193.005 0.054 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.167 0.000 193.185 0.054 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.347 0.000 193.365 0.054 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.527 0.000 193.545 0.054 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.707 0.000 193.725 0.054 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.887 0.000 193.905 0.054 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.067 0.000 194.085 0.054 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.247 0.000 194.265 0.054 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.427 0.000 194.445 0.054 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.607 0.000 194.625 0.054 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.787 0.000 194.805 0.054 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.967 0.000 194.985 0.054 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.147 0.000 195.165 0.054 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.327 0.000 195.345 0.054 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.507 0.000 195.525 0.054 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.687 0.000 195.705 0.054 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.867 0.000 195.885 0.054 ; + END + END rw0_rd_out[63] + PIN rw0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.047 0.000 196.065 0.054 ; + END + END rw0_rd_out[64] + PIN rw0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.227 0.000 196.245 0.054 ; + END + END rw0_rd_out[65] + PIN rw0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.407 0.000 196.425 0.054 ; + END + END rw0_rd_out[66] + PIN rw0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.587 0.000 196.605 0.054 ; + END + END rw0_rd_out[67] + PIN rw0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.767 0.000 196.785 0.054 ; + END + END rw0_rd_out[68] + PIN rw0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.947 0.000 196.965 0.054 ; + END + END rw0_rd_out[69] + PIN rw0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.127 0.000 197.145 0.054 ; + END + END rw0_rd_out[70] + PIN rw0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.307 0.000 197.325 0.054 ; + END + END rw0_rd_out[71] + PIN rw0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.487 0.000 197.505 0.054 ; + END + END rw0_rd_out[72] + PIN rw0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.667 0.000 197.685 0.054 ; + END + END rw0_rd_out[73] + PIN rw0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.847 0.000 197.865 0.054 ; + END + END rw0_rd_out[74] + PIN rw0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.027 0.000 198.045 0.054 ; + END + END rw0_rd_out[75] + PIN rw0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.207 0.000 198.225 0.054 ; + END + END rw0_rd_out[76] + PIN rw0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.387 0.000 198.405 0.054 ; + END + END rw0_rd_out[77] + PIN rw0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.567 0.000 198.585 0.054 ; + END + END rw0_rd_out[78] + PIN rw0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.747 0.000 198.765 0.054 ; + END + END rw0_rd_out[79] + PIN rw0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.927 0.000 198.945 0.054 ; + END + END rw0_rd_out[80] + PIN rw0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.107 0.000 199.125 0.054 ; + END + END rw0_rd_out[81] + PIN rw0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.287 0.000 199.305 0.054 ; + END + END rw0_rd_out[82] + PIN rw0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.467 0.000 199.485 0.054 ; + END + END rw0_rd_out[83] + PIN rw0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.647 0.000 199.665 0.054 ; + END + END rw0_rd_out[84] + PIN rw0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.827 0.000 199.845 0.054 ; + END + END rw0_rd_out[85] + PIN rw0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.007 0.000 200.025 0.054 ; + END + END rw0_rd_out[86] + PIN rw0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.187 0.000 200.205 0.054 ; + END + END rw0_rd_out[87] + PIN rw0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.367 0.000 200.385 0.054 ; + END + END rw0_rd_out[88] + PIN rw0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.547 0.000 200.565 0.054 ; + END + END rw0_rd_out[89] + PIN rw0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.727 0.000 200.745 0.054 ; + END + END rw0_rd_out[90] + PIN rw0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.907 0.000 200.925 0.054 ; + END + END rw0_rd_out[91] + PIN rw0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.087 0.000 201.105 0.054 ; + END + END rw0_rd_out[92] + PIN rw0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.267 0.000 201.285 0.054 ; + END + END rw0_rd_out[93] + PIN rw0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.447 0.000 201.465 0.054 ; + END + END rw0_rd_out[94] + PIN rw0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.627 0.000 201.645 0.054 ; + END + END rw0_rd_out[95] + PIN rw0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.807 0.000 201.825 0.054 ; + END + END rw0_rd_out[96] + PIN rw0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.987 0.000 202.005 0.054 ; + END + END rw0_rd_out[97] + PIN rw0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.167 0.000 202.185 0.054 ; + END + END rw0_rd_out[98] + PIN rw0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.347 0.000 202.365 0.054 ; + END + END rw0_rd_out[99] + PIN rw0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.527 0.000 202.545 0.054 ; + END + END rw0_rd_out[100] + PIN rw0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.707 0.000 202.725 0.054 ; + END + END rw0_rd_out[101] + PIN rw0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.887 0.000 202.905 0.054 ; + END + END rw0_rd_out[102] + PIN rw0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.067 0.000 203.085 0.054 ; + END + END rw0_rd_out[103] + PIN rw0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.247 0.000 203.265 0.054 ; + END + END rw0_rd_out[104] + PIN rw0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.427 0.000 203.445 0.054 ; + END + END rw0_rd_out[105] + PIN rw0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.607 0.000 203.625 0.054 ; + END + END rw0_rd_out[106] + PIN rw0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.787 0.000 203.805 0.054 ; + END + END rw0_rd_out[107] + PIN rw0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.967 0.000 203.985 0.054 ; + END + END rw0_rd_out[108] + PIN rw0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.147 0.000 204.165 0.054 ; + END + END rw0_rd_out[109] + PIN rw0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.327 0.000 204.345 0.054 ; + END + END rw0_rd_out[110] + PIN rw0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.507 0.000 204.525 0.054 ; + END + END rw0_rd_out[111] + PIN rw0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.687 0.000 204.705 0.054 ; + END + END rw0_rd_out[112] + PIN rw0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.867 0.000 204.885 0.054 ; + END + END rw0_rd_out[113] + PIN rw0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.047 0.000 205.065 0.054 ; + END + END rw0_rd_out[114] + PIN rw0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.227 0.000 205.245 0.054 ; + END + END rw0_rd_out[115] + PIN rw0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.407 0.000 205.425 0.054 ; + END + END rw0_rd_out[116] + PIN rw0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.587 0.000 205.605 0.054 ; + END + END rw0_rd_out[117] + PIN rw0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.767 0.000 205.785 0.054 ; + END + END rw0_rd_out[118] + PIN rw0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.947 0.000 205.965 0.054 ; + END + END rw0_rd_out[119] + PIN rw0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.127 0.000 206.145 0.054 ; + END + END rw0_rd_out[120] + PIN rw0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.307 0.000 206.325 0.054 ; + END + END rw0_rd_out[121] + PIN rw0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.487 0.000 206.505 0.054 ; + END + END rw0_rd_out[122] + PIN rw0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.667 0.000 206.685 0.054 ; + END + END rw0_rd_out[123] + PIN rw0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.847 0.000 206.865 0.054 ; + END + END rw0_rd_out[124] + PIN rw0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.027 0.000 207.045 0.054 ; + END + END rw0_rd_out[125] + PIN rw0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.207 0.000 207.225 0.054 ; + END + END rw0_rd_out[126] + PIN rw0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.387 0.000 207.405 0.054 ; + END + END rw0_rd_out[127] + PIN rw0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.567 0.000 207.585 0.054 ; + END + END rw0_rd_out[128] + PIN rw0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.747 0.000 207.765 0.054 ; + END + END rw0_rd_out[129] + PIN rw0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.927 0.000 207.945 0.054 ; + END + END rw0_rd_out[130] + PIN rw0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.107 0.000 208.125 0.054 ; + END + END rw0_rd_out[131] + PIN rw0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.287 0.000 208.305 0.054 ; + END + END rw0_rd_out[132] + PIN rw0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.467 0.000 208.485 0.054 ; + END + END rw0_rd_out[133] + PIN rw0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.647 0.000 208.665 0.054 ; + END + END rw0_rd_out[134] + PIN rw0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.827 0.000 208.845 0.054 ; + END + END rw0_rd_out[135] + PIN rw0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.007 0.000 209.025 0.054 ; + END + END rw0_rd_out[136] + PIN rw0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.187 0.000 209.205 0.054 ; + END + END rw0_rd_out[137] + PIN rw0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.367 0.000 209.385 0.054 ; + END + END rw0_rd_out[138] + PIN rw0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.547 0.000 209.565 0.054 ; + END + END rw0_rd_out[139] + PIN rw0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.727 0.000 209.745 0.054 ; + END + END rw0_rd_out[140] + PIN rw0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.907 0.000 209.925 0.054 ; + END + END rw0_rd_out[141] + PIN rw0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.087 0.000 210.105 0.054 ; + END + END rw0_rd_out[142] + PIN rw0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.267 0.000 210.285 0.054 ; + END + END rw0_rd_out[143] + PIN rw0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.447 0.000 210.465 0.054 ; + END + END rw0_rd_out[144] + PIN rw0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.627 0.000 210.645 0.054 ; + END + END rw0_rd_out[145] + PIN rw0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.807 0.000 210.825 0.054 ; + END + END rw0_rd_out[146] + PIN rw0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.987 0.000 211.005 0.054 ; + END + END rw0_rd_out[147] + PIN rw0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.167 0.000 211.185 0.054 ; + END + END rw0_rd_out[148] + PIN rw0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.347 0.000 211.365 0.054 ; + END + END rw0_rd_out[149] + PIN rw0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.527 0.000 211.545 0.054 ; + END + END rw0_rd_out[150] + PIN rw0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.707 0.000 211.725 0.054 ; + END + END rw0_rd_out[151] + PIN rw0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.887 0.000 211.905 0.054 ; + END + END rw0_rd_out[152] + PIN rw0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.067 0.000 212.085 0.054 ; + END + END rw0_rd_out[153] + PIN rw0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.247 0.000 212.265 0.054 ; + END + END rw0_rd_out[154] + PIN rw0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.427 0.000 212.445 0.054 ; + END + END rw0_rd_out[155] + PIN rw0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.607 0.000 212.625 0.054 ; + END + END rw0_rd_out[156] + PIN rw0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.787 0.000 212.805 0.054 ; + END + END rw0_rd_out[157] + PIN rw0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.967 0.000 212.985 0.054 ; + END + END rw0_rd_out[158] + PIN rw0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.147 0.000 213.165 0.054 ; + END + END rw0_rd_out[159] + PIN rw0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.327 0.000 213.345 0.054 ; + END + END rw0_rd_out[160] + PIN rw0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.507 0.000 213.525 0.054 ; + END + END rw0_rd_out[161] + PIN rw0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.687 0.000 213.705 0.054 ; + END + END rw0_rd_out[162] + PIN rw0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.867 0.000 213.885 0.054 ; + END + END rw0_rd_out[163] + PIN rw0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.047 0.000 214.065 0.054 ; + END + END rw0_rd_out[164] + PIN rw0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.227 0.000 214.245 0.054 ; + END + END rw0_rd_out[165] + PIN rw0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.407 0.000 214.425 0.054 ; + END + END rw0_rd_out[166] + PIN rw0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.587 0.000 214.605 0.054 ; + END + END rw0_rd_out[167] + PIN rw0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.767 0.000 214.785 0.054 ; + END + END rw0_rd_out[168] + PIN rw0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.947 0.000 214.965 0.054 ; + END + END rw0_rd_out[169] + PIN rw0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.127 0.000 215.145 0.054 ; + END + END rw0_rd_out[170] + PIN rw0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.307 0.000 215.325 0.054 ; + END + END rw0_rd_out[171] + PIN rw0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.487 0.000 215.505 0.054 ; + END + END rw0_rd_out[172] + PIN rw0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.667 0.000 215.685 0.054 ; + END + END rw0_rd_out[173] + PIN rw0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.847 0.000 215.865 0.054 ; + END + END rw0_rd_out[174] + PIN rw0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.027 0.000 216.045 0.054 ; + END + END rw0_rd_out[175] + PIN rw0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.207 0.000 216.225 0.054 ; + END + END rw0_rd_out[176] + PIN rw0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.387 0.000 216.405 0.054 ; + END + END rw0_rd_out[177] + PIN rw0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.567 0.000 216.585 0.054 ; + END + END rw0_rd_out[178] + PIN rw0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.747 0.000 216.765 0.054 ; + END + END rw0_rd_out[179] + PIN rw0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.927 0.000 216.945 0.054 ; + END + END rw0_rd_out[180] + PIN rw0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.107 0.000 217.125 0.054 ; + END + END rw0_rd_out[181] + PIN rw0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.287 0.000 217.305 0.054 ; + END + END rw0_rd_out[182] + PIN rw0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.467 0.000 217.485 0.054 ; + END + END rw0_rd_out[183] + PIN rw0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.647 0.000 217.665 0.054 ; + END + END rw0_rd_out[184] + PIN rw0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.827 0.000 217.845 0.054 ; + END + END rw0_rd_out[185] + PIN rw0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.007 0.000 218.025 0.054 ; + END + END rw0_rd_out[186] + PIN rw0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.187 0.000 218.205 0.054 ; + END + END rw0_rd_out[187] + PIN rw0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.367 0.000 218.385 0.054 ; + END + END rw0_rd_out[188] + PIN rw0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.547 0.000 218.565 0.054 ; + END + END rw0_rd_out[189] + PIN rw0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.727 0.000 218.745 0.054 ; + END + END rw0_rd_out[190] + PIN rw0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.907 0.000 218.925 0.054 ; + END + END rw0_rd_out[191] + PIN rw0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.087 0.000 219.105 0.054 ; + END + END rw0_rd_out[192] + PIN rw0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.267 0.000 219.285 0.054 ; + END + END rw0_rd_out[193] + PIN rw0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.447 0.000 219.465 0.054 ; + END + END rw0_rd_out[194] + PIN rw0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.627 0.000 219.645 0.054 ; + END + END rw0_rd_out[195] + PIN rw0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.807 0.000 219.825 0.054 ; + END + END rw0_rd_out[196] + PIN rw0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.987 0.000 220.005 0.054 ; + END + END rw0_rd_out[197] + PIN rw0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.167 0.000 220.185 0.054 ; + END + END rw0_rd_out[198] + PIN rw0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.347 0.000 220.365 0.054 ; + END + END rw0_rd_out[199] + PIN rw0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.527 0.000 220.545 0.054 ; + END + END rw0_rd_out[200] + PIN rw0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.707 0.000 220.725 0.054 ; + END + END rw0_rd_out[201] + PIN rw0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.887 0.000 220.905 0.054 ; + END + END rw0_rd_out[202] + PIN rw0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.067 0.000 221.085 0.054 ; + END + END rw0_rd_out[203] + PIN rw0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.247 0.000 221.265 0.054 ; + END + END rw0_rd_out[204] + PIN rw0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.427 0.000 221.445 0.054 ; + END + END rw0_rd_out[205] + PIN rw0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.607 0.000 221.625 0.054 ; + END + END rw0_rd_out[206] + PIN rw0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.787 0.000 221.805 0.054 ; + END + END rw0_rd_out[207] + PIN rw0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.967 0.000 221.985 0.054 ; + END + END rw0_rd_out[208] + PIN rw0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.147 0.000 222.165 0.054 ; + END + END rw0_rd_out[209] + PIN rw0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.327 0.000 222.345 0.054 ; + END + END rw0_rd_out[210] + PIN rw0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.507 0.000 222.525 0.054 ; + END + END rw0_rd_out[211] + PIN rw0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.687 0.000 222.705 0.054 ; + END + END rw0_rd_out[212] + PIN rw0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.867 0.000 222.885 0.054 ; + END + END rw0_rd_out[213] + PIN rw0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.047 0.000 223.065 0.054 ; + END + END rw0_rd_out[214] + PIN rw0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.227 0.000 223.245 0.054 ; + END + END rw0_rd_out[215] + PIN rw0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.407 0.000 223.425 0.054 ; + END + END rw0_rd_out[216] + PIN rw0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.587 0.000 223.605 0.054 ; + END + END rw0_rd_out[217] + PIN rw0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.767 0.000 223.785 0.054 ; + END + END rw0_rd_out[218] + PIN rw0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.947 0.000 223.965 0.054 ; + END + END rw0_rd_out[219] + PIN rw0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.127 0.000 224.145 0.054 ; + END + END rw0_rd_out[220] + PIN rw0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.307 0.000 224.325 0.054 ; + END + END rw0_rd_out[221] + PIN rw0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.487 0.000 224.505 0.054 ; + END + END rw0_rd_out[222] + PIN rw0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.667 0.000 224.685 0.054 ; + END + END rw0_rd_out[223] + PIN rw0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.847 0.000 224.865 0.054 ; + END + END rw0_rd_out[224] + PIN rw0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.027 0.000 225.045 0.054 ; + END + END rw0_rd_out[225] + PIN rw0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.207 0.000 225.225 0.054 ; + END + END rw0_rd_out[226] + PIN rw0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.387 0.000 225.405 0.054 ; + END + END rw0_rd_out[227] + PIN rw0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.567 0.000 225.585 0.054 ; + END + END rw0_rd_out[228] + PIN rw0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.747 0.000 225.765 0.054 ; + END + END rw0_rd_out[229] + PIN rw0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.927 0.000 225.945 0.054 ; + END + END rw0_rd_out[230] + PIN rw0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.107 0.000 226.125 0.054 ; + END + END rw0_rd_out[231] + PIN rw0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.287 0.000 226.305 0.054 ; + END + END rw0_rd_out[232] + PIN rw0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.467 0.000 226.485 0.054 ; + END + END rw0_rd_out[233] + PIN rw0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.647 0.000 226.665 0.054 ; + END + END rw0_rd_out[234] + PIN rw0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.827 0.000 226.845 0.054 ; + END + END rw0_rd_out[235] + PIN rw0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.007 0.000 227.025 0.054 ; + END + END rw0_rd_out[236] + PIN rw0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.187 0.000 227.205 0.054 ; + END + END rw0_rd_out[237] + PIN rw0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.367 0.000 227.385 0.054 ; + END + END rw0_rd_out[238] + PIN rw0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.547 0.000 227.565 0.054 ; + END + END rw0_rd_out[239] + PIN rw0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.727 0.000 227.745 0.054 ; + END + END rw0_rd_out[240] + PIN rw0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.907 0.000 227.925 0.054 ; + END + END rw0_rd_out[241] + PIN rw0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.087 0.000 228.105 0.054 ; + END + END rw0_rd_out[242] + PIN rw0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.267 0.000 228.285 0.054 ; + END + END rw0_rd_out[243] + PIN rw0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.447 0.000 228.465 0.054 ; + END + END rw0_rd_out[244] + PIN rw0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.627 0.000 228.645 0.054 ; + END + END rw0_rd_out[245] + PIN rw0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.807 0.000 228.825 0.054 ; + END + END rw0_rd_out[246] + PIN rw0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.987 0.000 229.005 0.054 ; + END + END rw0_rd_out[247] + PIN rw0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.167 0.000 229.185 0.054 ; + END + END rw0_rd_out[248] + PIN rw0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.347 0.000 229.365 0.054 ; + END + END rw0_rd_out[249] + PIN rw0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.527 0.000 229.545 0.054 ; + END + END rw0_rd_out[250] + PIN rw0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.707 0.000 229.725 0.054 ; + END + END rw0_rd_out[251] + PIN rw0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.887 0.000 229.905 0.054 ; + END + END rw0_rd_out[252] + PIN rw0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.067 0.000 230.085 0.054 ; + END + END rw0_rd_out[253] + PIN rw0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.247 0.000 230.265 0.054 ; + END + END rw0_rd_out[254] + PIN rw0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.427 0.000 230.445 0.054 ; + END + END rw0_rd_out[255] + PIN rw0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.607 0.000 230.625 0.054 ; + END + END rw0_rd_out[256] + PIN rw0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.787 0.000 230.805 0.054 ; + END + END rw0_rd_out[257] + PIN rw0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.967 0.000 230.985 0.054 ; + END + END rw0_rd_out[258] + PIN rw0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.147 0.000 231.165 0.054 ; + END + END rw0_rd_out[259] + PIN rw0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.327 0.000 231.345 0.054 ; + END + END rw0_rd_out[260] + PIN rw0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.507 0.000 231.525 0.054 ; + END + END rw0_rd_out[261] + PIN rw0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.687 0.000 231.705 0.054 ; + END + END rw0_rd_out[262] + PIN rw0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.867 0.000 231.885 0.054 ; + END + END rw0_rd_out[263] + PIN rw0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.047 0.000 232.065 0.054 ; + END + END rw0_rd_out[264] + PIN rw0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.227 0.000 232.245 0.054 ; + END + END rw0_rd_out[265] + PIN rw0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.407 0.000 232.425 0.054 ; + END + END rw0_rd_out[266] + PIN rw0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.587 0.000 232.605 0.054 ; + END + END rw0_rd_out[267] + PIN rw0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.767 0.000 232.785 0.054 ; + END + END rw0_rd_out[268] + PIN rw0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.947 0.000 232.965 0.054 ; + END + END rw0_rd_out[269] + PIN rw0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.127 0.000 233.145 0.054 ; + END + END rw0_rd_out[270] + PIN rw0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.307 0.000 233.325 0.054 ; + END + END rw0_rd_out[271] + PIN rw0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.487 0.000 233.505 0.054 ; + END + END rw0_rd_out[272] + PIN rw0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.667 0.000 233.685 0.054 ; + END + END rw0_rd_out[273] + PIN rw0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.847 0.000 233.865 0.054 ; + END + END rw0_rd_out[274] + PIN rw0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.027 0.000 234.045 0.054 ; + END + END rw0_rd_out[275] + PIN rw0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.207 0.000 234.225 0.054 ; + END + END rw0_rd_out[276] + PIN rw0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.387 0.000 234.405 0.054 ; + END + END rw0_rd_out[277] + PIN rw0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.567 0.000 234.585 0.054 ; + END + END rw0_rd_out[278] + PIN rw0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.747 0.000 234.765 0.054 ; + END + END rw0_rd_out[279] + PIN rw0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.927 0.000 234.945 0.054 ; + END + END rw0_rd_out[280] + PIN rw0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.107 0.000 235.125 0.054 ; + END + END rw0_rd_out[281] + PIN rw0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.287 0.000 235.305 0.054 ; + END + END rw0_rd_out[282] + PIN rw0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.467 0.000 235.485 0.054 ; + END + END rw0_rd_out[283] + PIN rw0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.647 0.000 235.665 0.054 ; + END + END rw0_rd_out[284] + PIN rw0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.827 0.000 235.845 0.054 ; + END + END rw0_rd_out[285] + PIN rw0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.007 0.000 236.025 0.054 ; + END + END rw0_rd_out[286] + PIN rw0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.187 0.000 236.205 0.054 ; + END + END rw0_rd_out[287] + PIN rw0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.367 0.000 236.385 0.054 ; + END + END rw0_rd_out[288] + PIN rw0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.547 0.000 236.565 0.054 ; + END + END rw0_rd_out[289] + PIN rw0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.727 0.000 236.745 0.054 ; + END + END rw0_rd_out[290] + PIN rw0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.907 0.000 236.925 0.054 ; + END + END rw0_rd_out[291] + PIN rw0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.087 0.000 237.105 0.054 ; + END + END rw0_rd_out[292] + PIN rw0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.267 0.000 237.285 0.054 ; + END + END rw0_rd_out[293] + PIN rw0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.447 0.000 237.465 0.054 ; + END + END rw0_rd_out[294] + PIN rw0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.627 0.000 237.645 0.054 ; + END + END rw0_rd_out[295] + PIN rw0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.807 0.000 237.825 0.054 ; + END + END rw0_rd_out[296] + PIN rw0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.987 0.000 238.005 0.054 ; + END + END rw0_rd_out[297] + PIN rw0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.167 0.000 238.185 0.054 ; + END + END rw0_rd_out[298] + PIN rw0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.347 0.000 238.365 0.054 ; + END + END rw0_rd_out[299] + PIN rw0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.527 0.000 238.545 0.054 ; + END + END rw0_rd_out[300] + PIN rw0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.707 0.000 238.725 0.054 ; + END + END rw0_rd_out[301] + PIN rw0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.887 0.000 238.905 0.054 ; + END + END rw0_rd_out[302] + PIN rw0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.067 0.000 239.085 0.054 ; + END + END rw0_rd_out[303] + PIN rw0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.247 0.000 239.265 0.054 ; + END + END rw0_rd_out[304] + PIN rw0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.427 0.000 239.445 0.054 ; + END + END rw0_rd_out[305] + PIN rw0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.607 0.000 239.625 0.054 ; + END + END rw0_rd_out[306] + PIN rw0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.787 0.000 239.805 0.054 ; + END + END rw0_rd_out[307] + PIN rw0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.967 0.000 239.985 0.054 ; + END + END rw0_rd_out[308] + PIN rw0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.147 0.000 240.165 0.054 ; + END + END rw0_rd_out[309] + PIN rw0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.327 0.000 240.345 0.054 ; + END + END rw0_rd_out[310] + PIN rw0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.507 0.000 240.525 0.054 ; + END + END rw0_rd_out[311] + PIN rw0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.687 0.000 240.705 0.054 ; + END + END rw0_rd_out[312] + PIN rw0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.867 0.000 240.885 0.054 ; + END + END rw0_rd_out[313] + PIN rw0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.047 0.000 241.065 0.054 ; + END + END rw0_rd_out[314] + PIN rw0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.227 0.000 241.245 0.054 ; + END + END rw0_rd_out[315] + PIN rw0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.407 0.000 241.425 0.054 ; + END + END rw0_rd_out[316] + PIN rw0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.587 0.000 241.605 0.054 ; + END + END rw0_rd_out[317] + PIN rw0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.767 0.000 241.785 0.054 ; + END + END rw0_rd_out[318] + PIN rw0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.947 0.000 241.965 0.054 ; + END + END rw0_rd_out[319] + PIN rw0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.127 0.000 242.145 0.054 ; + END + END rw0_rd_out[320] + PIN rw0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.307 0.000 242.325 0.054 ; + END + END rw0_rd_out[321] + PIN rw0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.487 0.000 242.505 0.054 ; + END + END rw0_rd_out[322] + PIN rw0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.667 0.000 242.685 0.054 ; + END + END rw0_rd_out[323] + PIN rw0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.847 0.000 242.865 0.054 ; + END + END rw0_rd_out[324] + PIN rw0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.027 0.000 243.045 0.054 ; + END + END rw0_rd_out[325] + PIN rw0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.207 0.000 243.225 0.054 ; + END + END rw0_rd_out[326] + PIN rw0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.387 0.000 243.405 0.054 ; + END + END rw0_rd_out[327] + PIN rw0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.567 0.000 243.585 0.054 ; + END + END rw0_rd_out[328] + PIN rw0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.747 0.000 243.765 0.054 ; + END + END rw0_rd_out[329] + PIN rw0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.927 0.000 243.945 0.054 ; + END + END rw0_rd_out[330] + PIN rw0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.107 0.000 244.125 0.054 ; + END + END rw0_rd_out[331] + PIN rw0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.287 0.000 244.305 0.054 ; + END + END rw0_rd_out[332] + PIN rw0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.467 0.000 244.485 0.054 ; + END + END rw0_rd_out[333] + PIN rw0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.647 0.000 244.665 0.054 ; + END + END rw0_rd_out[334] + PIN rw0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.827 0.000 244.845 0.054 ; + END + END rw0_rd_out[335] + PIN rw0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.007 0.000 245.025 0.054 ; + END + END rw0_rd_out[336] + PIN rw0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.187 0.000 245.205 0.054 ; + END + END rw0_rd_out[337] + PIN rw0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.367 0.000 245.385 0.054 ; + END + END rw0_rd_out[338] + PIN rw0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.547 0.000 245.565 0.054 ; + END + END rw0_rd_out[339] + PIN rw0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.727 0.000 245.745 0.054 ; + END + END rw0_rd_out[340] + PIN rw0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.907 0.000 245.925 0.054 ; + END + END rw0_rd_out[341] + PIN rw0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.087 0.000 246.105 0.054 ; + END + END rw0_rd_out[342] + PIN rw0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.267 0.000 246.285 0.054 ; + END + END rw0_rd_out[343] + PIN rw0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.447 0.000 246.465 0.054 ; + END + END rw0_rd_out[344] + PIN rw0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.627 0.000 246.645 0.054 ; + END + END rw0_rd_out[345] + PIN rw0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.807 0.000 246.825 0.054 ; + END + END rw0_rd_out[346] + PIN rw0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.987 0.000 247.005 0.054 ; + END + END rw0_rd_out[347] + PIN rw0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.167 0.000 247.185 0.054 ; + END + END rw0_rd_out[348] + PIN rw0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.347 0.000 247.365 0.054 ; + END + END rw0_rd_out[349] + PIN rw0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.527 0.000 247.545 0.054 ; + END + END rw0_rd_out[350] + PIN rw0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.707 0.000 247.725 0.054 ; + END + END rw0_rd_out[351] + PIN rw0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.887 0.000 247.905 0.054 ; + END + END rw0_rd_out[352] + PIN rw0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.067 0.000 248.085 0.054 ; + END + END rw0_rd_out[353] + PIN rw0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.247 0.000 248.265 0.054 ; + END + END rw0_rd_out[354] + PIN rw0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.427 0.000 248.445 0.054 ; + END + END rw0_rd_out[355] + PIN rw0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.607 0.000 248.625 0.054 ; + END + END rw0_rd_out[356] + PIN rw0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.787 0.000 248.805 0.054 ; + END + END rw0_rd_out[357] + PIN rw0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.967 0.000 248.985 0.054 ; + END + END rw0_rd_out[358] + PIN rw0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.147 0.000 249.165 0.054 ; + END + END rw0_rd_out[359] + PIN rw0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.327 0.000 249.345 0.054 ; + END + END rw0_rd_out[360] + PIN rw0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.507 0.000 249.525 0.054 ; + END + END rw0_rd_out[361] + PIN rw0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.687 0.000 249.705 0.054 ; + END + END rw0_rd_out[362] + PIN rw0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.867 0.000 249.885 0.054 ; + END + END rw0_rd_out[363] + PIN rw0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.047 0.000 250.065 0.054 ; + END + END rw0_rd_out[364] + PIN rw0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.227 0.000 250.245 0.054 ; + END + END rw0_rd_out[365] + PIN rw0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.407 0.000 250.425 0.054 ; + END + END rw0_rd_out[366] + PIN rw0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.587 0.000 250.605 0.054 ; + END + END rw0_rd_out[367] + PIN rw0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.767 0.000 250.785 0.054 ; + END + END rw0_rd_out[368] + PIN rw0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.947 0.000 250.965 0.054 ; + END + END rw0_rd_out[369] + PIN rw0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.127 0.000 251.145 0.054 ; + END + END rw0_rd_out[370] + PIN rw0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.307 0.000 251.325 0.054 ; + END + END rw0_rd_out[371] + PIN rw0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.487 0.000 251.505 0.054 ; + END + END rw0_rd_out[372] + PIN rw0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.667 0.000 251.685 0.054 ; + END + END rw0_rd_out[373] + PIN rw0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.847 0.000 251.865 0.054 ; + END + END rw0_rd_out[374] + PIN rw0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.027 0.000 252.045 0.054 ; + END + END rw0_rd_out[375] + PIN rw0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.207 0.000 252.225 0.054 ; + END + END rw0_rd_out[376] + PIN rw0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.387 0.000 252.405 0.054 ; + END + END rw0_rd_out[377] + PIN rw0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.567 0.000 252.585 0.054 ; + END + END rw0_rd_out[378] + PIN rw0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.747 0.000 252.765 0.054 ; + END + END rw0_rd_out[379] + PIN rw0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.927 0.000 252.945 0.054 ; + END + END rw0_rd_out[380] + PIN rw0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.107 0.000 253.125 0.054 ; + END + END rw0_rd_out[381] + PIN rw0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.287 0.000 253.305 0.054 ; + END + END rw0_rd_out[382] + PIN rw0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.467 0.000 253.485 0.054 ; + END + END rw0_rd_out[383] + PIN rw0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.647 0.000 253.665 0.054 ; + END + END rw0_rd_out[384] + PIN rw0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.827 0.000 253.845 0.054 ; + END + END rw0_rd_out[385] + PIN rw0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.007 0.000 254.025 0.054 ; + END + END rw0_rd_out[386] + PIN rw0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.187 0.000 254.205 0.054 ; + END + END rw0_rd_out[387] + PIN rw0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.367 0.000 254.385 0.054 ; + END + END rw0_rd_out[388] + PIN rw0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.547 0.000 254.565 0.054 ; + END + END rw0_rd_out[389] + PIN rw0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.727 0.000 254.745 0.054 ; + END + END rw0_rd_out[390] + PIN rw0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.907 0.000 254.925 0.054 ; + END + END rw0_rd_out[391] + PIN rw0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.087 0.000 255.105 0.054 ; + END + END rw0_rd_out[392] + PIN rw0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.267 0.000 255.285 0.054 ; + END + END rw0_rd_out[393] + PIN rw0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.447 0.000 255.465 0.054 ; + END + END rw0_rd_out[394] + PIN rw0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.627 0.000 255.645 0.054 ; + END + END rw0_rd_out[395] + PIN rw0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.807 0.000 255.825 0.054 ; + END + END rw0_rd_out[396] + PIN rw0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.987 0.000 256.005 0.054 ; + END + END rw0_rd_out[397] + PIN rw0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.167 0.000 256.185 0.054 ; + END + END rw0_rd_out[398] + PIN rw0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.347 0.000 256.365 0.054 ; + END + END rw0_rd_out[399] + PIN rw0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.527 0.000 256.545 0.054 ; + END + END rw0_rd_out[400] + PIN rw0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.707 0.000 256.725 0.054 ; + END + END rw0_rd_out[401] + PIN rw0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.887 0.000 256.905 0.054 ; + END + END rw0_rd_out[402] + PIN rw0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.067 0.000 257.085 0.054 ; + END + END rw0_rd_out[403] + PIN rw0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.247 0.000 257.265 0.054 ; + END + END rw0_rd_out[404] + PIN rw0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.427 0.000 257.445 0.054 ; + END + END rw0_rd_out[405] + PIN rw0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.607 0.000 257.625 0.054 ; + END + END rw0_rd_out[406] + PIN rw0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.787 0.000 257.805 0.054 ; + END + END rw0_rd_out[407] + PIN rw0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.967 0.000 257.985 0.054 ; + END + END rw0_rd_out[408] + PIN rw0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.147 0.000 258.165 0.054 ; + END + END rw0_rd_out[409] + PIN rw0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.327 0.000 258.345 0.054 ; + END + END rw0_rd_out[410] + PIN rw0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.507 0.000 258.525 0.054 ; + END + END rw0_rd_out[411] + PIN rw0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.687 0.000 258.705 0.054 ; + END + END rw0_rd_out[412] + PIN rw0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.867 0.000 258.885 0.054 ; + END + END rw0_rd_out[413] + PIN rw0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.047 0.000 259.065 0.054 ; + END + END rw0_rd_out[414] + PIN rw0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.227 0.000 259.245 0.054 ; + END + END rw0_rd_out[415] + PIN rw0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.407 0.000 259.425 0.054 ; + END + END rw0_rd_out[416] + PIN rw0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.587 0.000 259.605 0.054 ; + END + END rw0_rd_out[417] + PIN rw0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.767 0.000 259.785 0.054 ; + END + END rw0_rd_out[418] + PIN rw0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.947 0.000 259.965 0.054 ; + END + END rw0_rd_out[419] + PIN rw0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.127 0.000 260.145 0.054 ; + END + END rw0_rd_out[420] + PIN rw0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.307 0.000 260.325 0.054 ; + END + END rw0_rd_out[421] + PIN rw0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.487 0.000 260.505 0.054 ; + END + END rw0_rd_out[422] + PIN rw0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.667 0.000 260.685 0.054 ; + END + END rw0_rd_out[423] + PIN rw0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.847 0.000 260.865 0.054 ; + END + END rw0_rd_out[424] + PIN rw0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.027 0.000 261.045 0.054 ; + END + END rw0_rd_out[425] + PIN rw0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.207 0.000 261.225 0.054 ; + END + END rw0_rd_out[426] + PIN rw0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.387 0.000 261.405 0.054 ; + END + END rw0_rd_out[427] + PIN rw0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.567 0.000 261.585 0.054 ; + END + END rw0_rd_out[428] + PIN rw0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.747 0.000 261.765 0.054 ; + END + END rw0_rd_out[429] + PIN rw0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.927 0.000 261.945 0.054 ; + END + END rw0_rd_out[430] + PIN rw0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.107 0.000 262.125 0.054 ; + END + END rw0_rd_out[431] + PIN rw0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.287 0.000 262.305 0.054 ; + END + END rw0_rd_out[432] + PIN rw0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.467 0.000 262.485 0.054 ; + END + END rw0_rd_out[433] + PIN rw0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.647 0.000 262.665 0.054 ; + END + END rw0_rd_out[434] + PIN rw0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.827 0.000 262.845 0.054 ; + END + END rw0_rd_out[435] + PIN rw0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.007 0.000 263.025 0.054 ; + END + END rw0_rd_out[436] + PIN rw0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.187 0.000 263.205 0.054 ; + END + END rw0_rd_out[437] + PIN rw0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.367 0.000 263.385 0.054 ; + END + END rw0_rd_out[438] + PIN rw0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.547 0.000 263.565 0.054 ; + END + END rw0_rd_out[439] + PIN rw0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.727 0.000 263.745 0.054 ; + END + END rw0_rd_out[440] + PIN rw0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.907 0.000 263.925 0.054 ; + END + END rw0_rd_out[441] + PIN rw0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.087 0.000 264.105 0.054 ; + END + END rw0_rd_out[442] + PIN rw0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.267 0.000 264.285 0.054 ; + END + END rw0_rd_out[443] + PIN rw0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.447 0.000 264.465 0.054 ; + END + END rw0_rd_out[444] + PIN rw0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.627 0.000 264.645 0.054 ; + END + END rw0_rd_out[445] + PIN rw0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.807 0.000 264.825 0.054 ; + END + END rw0_rd_out[446] + PIN rw0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.987 0.000 265.005 0.054 ; + END + END rw0_rd_out[447] + PIN rw0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.167 0.000 265.185 0.054 ; + END + END rw0_rd_out[448] + PIN rw0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.347 0.000 265.365 0.054 ; + END + END rw0_rd_out[449] + PIN rw0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.527 0.000 265.545 0.054 ; + END + END rw0_rd_out[450] + PIN rw0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.707 0.000 265.725 0.054 ; + END + END rw0_rd_out[451] + PIN rw0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.887 0.000 265.905 0.054 ; + END + END rw0_rd_out[452] + PIN rw0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.067 0.000 266.085 0.054 ; + END + END rw0_rd_out[453] + PIN rw0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.247 0.000 266.265 0.054 ; + END + END rw0_rd_out[454] + PIN rw0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.427 0.000 266.445 0.054 ; + END + END rw0_rd_out[455] + PIN rw0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.607 0.000 266.625 0.054 ; + END + END rw0_rd_out[456] + PIN rw0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.787 0.000 266.805 0.054 ; + END + END rw0_rd_out[457] + PIN rw0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.967 0.000 266.985 0.054 ; + END + END rw0_rd_out[458] + PIN rw0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.147 0.000 267.165 0.054 ; + END + END rw0_rd_out[459] + PIN rw0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.327 0.000 267.345 0.054 ; + END + END rw0_rd_out[460] + PIN rw0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.507 0.000 267.525 0.054 ; + END + END rw0_rd_out[461] + PIN rw0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.687 0.000 267.705 0.054 ; + END + END rw0_rd_out[462] + PIN rw0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.867 0.000 267.885 0.054 ; + END + END rw0_rd_out[463] + PIN rw0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.047 0.000 268.065 0.054 ; + END + END rw0_rd_out[464] + PIN rw0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.227 0.000 268.245 0.054 ; + END + END rw0_rd_out[465] + PIN rw0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.407 0.000 268.425 0.054 ; + END + END rw0_rd_out[466] + PIN rw0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.587 0.000 268.605 0.054 ; + END + END rw0_rd_out[467] + PIN rw0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.767 0.000 268.785 0.054 ; + END + END rw0_rd_out[468] + PIN rw0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.947 0.000 268.965 0.054 ; + END + END rw0_rd_out[469] + PIN rw0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.127 0.000 269.145 0.054 ; + END + END rw0_rd_out[470] + PIN rw0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.307 0.000 269.325 0.054 ; + END + END rw0_rd_out[471] + PIN rw0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.487 0.000 269.505 0.054 ; + END + END rw0_rd_out[472] + PIN rw0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.667 0.000 269.685 0.054 ; + END + END rw0_rd_out[473] + PIN rw0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.847 0.000 269.865 0.054 ; + END + END rw0_rd_out[474] + PIN rw0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.027 0.000 270.045 0.054 ; + END + END rw0_rd_out[475] + PIN rw0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.207 0.000 270.225 0.054 ; + END + END rw0_rd_out[476] + PIN rw0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.387 0.000 270.405 0.054 ; + END + END rw0_rd_out[477] + PIN rw0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.567 0.000 270.585 0.054 ; + END + END rw0_rd_out[478] + PIN rw0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.747 0.000 270.765 0.054 ; + END + END rw0_rd_out[479] + PIN rw0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.927 0.000 270.945 0.054 ; + END + END rw0_rd_out[480] + PIN rw0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.107 0.000 271.125 0.054 ; + END + END rw0_rd_out[481] + PIN rw0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.287 0.000 271.305 0.054 ; + END + END rw0_rd_out[482] + PIN rw0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.467 0.000 271.485 0.054 ; + END + END rw0_rd_out[483] + PIN rw0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.647 0.000 271.665 0.054 ; + END + END rw0_rd_out[484] + PIN rw0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.827 0.000 271.845 0.054 ; + END + END rw0_rd_out[485] + PIN rw0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.007 0.000 272.025 0.054 ; + END + END rw0_rd_out[486] + PIN rw0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.187 0.000 272.205 0.054 ; + END + END rw0_rd_out[487] + PIN rw0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.367 0.000 272.385 0.054 ; + END + END rw0_rd_out[488] + PIN rw0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.547 0.000 272.565 0.054 ; + END + END rw0_rd_out[489] + PIN rw0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.727 0.000 272.745 0.054 ; + END + END rw0_rd_out[490] + PIN rw0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.907 0.000 272.925 0.054 ; + END + END rw0_rd_out[491] + PIN rw0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.087 0.000 273.105 0.054 ; + END + END rw0_rd_out[492] + PIN rw0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.267 0.000 273.285 0.054 ; + END + END rw0_rd_out[493] + PIN rw0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.447 0.000 273.465 0.054 ; + END + END rw0_rd_out[494] + PIN rw0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.627 0.000 273.645 0.054 ; + END + END rw0_rd_out[495] + PIN rw0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.807 0.000 273.825 0.054 ; + END + END rw0_rd_out[496] + PIN rw0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.987 0.000 274.005 0.054 ; + END + END rw0_rd_out[497] + PIN rw0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.167 0.000 274.185 0.054 ; + END + END rw0_rd_out[498] + PIN rw0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.347 0.000 274.365 0.054 ; + END + END rw0_rd_out[499] + PIN rw0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.527 0.000 274.545 0.054 ; + END + END rw0_rd_out[500] + PIN rw0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.707 0.000 274.725 0.054 ; + END + END rw0_rd_out[501] + PIN rw0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.887 0.000 274.905 0.054 ; + END + END rw0_rd_out[502] + PIN rw0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.067 0.000 275.085 0.054 ; + END + END rw0_rd_out[503] + PIN rw0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.247 0.000 275.265 0.054 ; + END + END rw0_rd_out[504] + PIN rw0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.427 0.000 275.445 0.054 ; + END + END rw0_rd_out[505] + PIN rw0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.607 0.000 275.625 0.054 ; + END + END rw0_rd_out[506] + PIN rw0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.787 0.000 275.805 0.054 ; + END + END rw0_rd_out[507] + PIN rw0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.967 0.000 275.985 0.054 ; + END + END rw0_rd_out[508] + PIN rw0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.147 0.000 276.165 0.054 ; + END + END rw0_rd_out[509] + PIN rw0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.327 0.000 276.345 0.054 ; + END + END rw0_rd_out[510] + PIN rw0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.507 0.000 276.525 0.054 ; + END + END rw0_rd_out[511] + PIN rw0_rd_out[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.687 0.000 276.705 0.054 ; + END + END rw0_rd_out[512] + PIN rw0_rd_out[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.867 0.000 276.885 0.054 ; + END + END rw0_rd_out[513] + PIN rw0_rd_out[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.047 0.000 277.065 0.054 ; + END + END rw0_rd_out[514] + PIN rw0_rd_out[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.227 0.000 277.245 0.054 ; + END + END rw0_rd_out[515] + PIN rw0_rd_out[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.407 0.000 277.425 0.054 ; + END + END rw0_rd_out[516] + PIN rw0_rd_out[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.587 0.000 277.605 0.054 ; + END + END rw0_rd_out[517] + PIN rw0_rd_out[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.767 0.000 277.785 0.054 ; + END + END rw0_rd_out[518] + PIN rw0_rd_out[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.947 0.000 277.965 0.054 ; + END + END rw0_rd_out[519] + PIN rw0_rd_out[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.127 0.000 278.145 0.054 ; + END + END rw0_rd_out[520] + PIN rw0_rd_out[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.307 0.000 278.325 0.054 ; + END + END rw0_rd_out[521] + PIN rw0_rd_out[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.487 0.000 278.505 0.054 ; + END + END rw0_rd_out[522] + PIN rw0_rd_out[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.667 0.000 278.685 0.054 ; + END + END rw0_rd_out[523] + PIN rw0_rd_out[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.847 0.000 278.865 0.054 ; + END + END rw0_rd_out[524] + PIN rw0_rd_out[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.027 0.000 279.045 0.054 ; + END + END rw0_rd_out[525] + PIN rw0_rd_out[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.207 0.000 279.225 0.054 ; + END + END rw0_rd_out[526] + PIN rw0_rd_out[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.387 0.000 279.405 0.054 ; + END + END rw0_rd_out[527] + PIN rw0_rd_out[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.567 0.000 279.585 0.054 ; + END + END rw0_rd_out[528] + PIN rw0_rd_out[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.747 0.000 279.765 0.054 ; + END + END rw0_rd_out[529] + PIN rw0_rd_out[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.927 0.000 279.945 0.054 ; + END + END rw0_rd_out[530] + PIN rw0_rd_out[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.107 0.000 280.125 0.054 ; + END + END rw0_rd_out[531] + PIN rw0_rd_out[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.287 0.000 280.305 0.054 ; + END + END rw0_rd_out[532] + PIN rw0_rd_out[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.467 0.000 280.485 0.054 ; + END + END rw0_rd_out[533] + PIN rw0_rd_out[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.647 0.000 280.665 0.054 ; + END + END rw0_rd_out[534] + PIN rw0_rd_out[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.827 0.000 280.845 0.054 ; + END + END rw0_rd_out[535] + PIN rw0_rd_out[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.007 0.000 281.025 0.054 ; + END + END rw0_rd_out[536] + PIN rw0_rd_out[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.187 0.000 281.205 0.054 ; + END + END rw0_rd_out[537] + PIN rw0_rd_out[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.367 0.000 281.385 0.054 ; + END + END rw0_rd_out[538] + PIN rw0_rd_out[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.547 0.000 281.565 0.054 ; + END + END rw0_rd_out[539] + PIN rw0_rd_out[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.727 0.000 281.745 0.054 ; + END + END rw0_rd_out[540] + PIN rw0_rd_out[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.907 0.000 281.925 0.054 ; + END + END rw0_rd_out[541] + PIN rw0_rd_out[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.087 0.000 282.105 0.054 ; + END + END rw0_rd_out[542] + PIN rw0_rd_out[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.267 0.000 282.285 0.054 ; + END + END rw0_rd_out[543] + PIN rw0_rd_out[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.447 0.000 282.465 0.054 ; + END + END rw0_rd_out[544] + PIN rw0_rd_out[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.627 0.000 282.645 0.054 ; + END + END rw0_rd_out[545] + PIN rw0_rd_out[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.807 0.000 282.825 0.054 ; + END + END rw0_rd_out[546] + PIN rw0_rd_out[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.987 0.000 283.005 0.054 ; + END + END rw0_rd_out[547] + PIN rw0_rd_out[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.167 0.000 283.185 0.054 ; + END + END rw0_rd_out[548] + PIN rw0_rd_out[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.347 0.000 283.365 0.054 ; + END + END rw0_rd_out[549] + PIN rw0_rd_out[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.527 0.000 283.545 0.054 ; + END + END rw0_rd_out[550] + PIN rw0_rd_out[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.707 0.000 283.725 0.054 ; + END + END rw0_rd_out[551] + PIN rw0_rd_out[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.887 0.000 283.905 0.054 ; + END + END rw0_rd_out[552] + PIN rw0_rd_out[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.067 0.000 284.085 0.054 ; + END + END rw0_rd_out[553] + PIN rw0_rd_out[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.247 0.000 284.265 0.054 ; + END + END rw0_rd_out[554] + PIN rw0_rd_out[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.427 0.000 284.445 0.054 ; + END + END rw0_rd_out[555] + PIN rw0_rd_out[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.607 0.000 284.625 0.054 ; + END + END rw0_rd_out[556] + PIN rw0_rd_out[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.787 0.000 284.805 0.054 ; + END + END rw0_rd_out[557] + PIN rw0_rd_out[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.967 0.000 284.985 0.054 ; + END + END rw0_rd_out[558] + PIN rw0_rd_out[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.147 0.000 285.165 0.054 ; + END + END rw0_rd_out[559] + PIN rw0_rd_out[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.327 0.000 285.345 0.054 ; + END + END rw0_rd_out[560] + PIN rw0_rd_out[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.507 0.000 285.525 0.054 ; + END + END rw0_rd_out[561] + PIN rw0_rd_out[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.687 0.000 285.705 0.054 ; + END + END rw0_rd_out[562] + PIN rw0_rd_out[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.867 0.000 285.885 0.054 ; + END + END rw0_rd_out[563] + PIN rw0_rd_out[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.047 0.000 286.065 0.054 ; + END + END rw0_rd_out[564] + PIN rw0_rd_out[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.227 0.000 286.245 0.054 ; + END + END rw0_rd_out[565] + PIN rw0_rd_out[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.407 0.000 286.425 0.054 ; + END + END rw0_rd_out[566] + PIN rw0_rd_out[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.587 0.000 286.605 0.054 ; + END + END rw0_rd_out[567] + PIN rw0_rd_out[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.767 0.000 286.785 0.054 ; + END + END rw0_rd_out[568] + PIN rw0_rd_out[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.947 0.000 286.965 0.054 ; + END + END rw0_rd_out[569] + PIN rw0_rd_out[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.127 0.000 287.145 0.054 ; + END + END rw0_rd_out[570] + PIN rw0_rd_out[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.307 0.000 287.325 0.054 ; + END + END rw0_rd_out[571] + PIN rw0_rd_out[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.487 0.000 287.505 0.054 ; + END + END rw0_rd_out[572] + PIN rw0_rd_out[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.667 0.000 287.685 0.054 ; + END + END rw0_rd_out[573] + PIN rw0_rd_out[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.847 0.000 287.865 0.054 ; + END + END rw0_rd_out[574] + PIN rw0_rd_out[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.027 0.000 288.045 0.054 ; + END + END rw0_rd_out[575] + PIN rw0_rd_out[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.207 0.000 288.225 0.054 ; + END + END rw0_rd_out[576] + PIN rw0_rd_out[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.387 0.000 288.405 0.054 ; + END + END rw0_rd_out[577] + PIN rw0_rd_out[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.567 0.000 288.585 0.054 ; + END + END rw0_rd_out[578] + PIN rw0_rd_out[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.747 0.000 288.765 0.054 ; + END + END rw0_rd_out[579] + PIN rw0_rd_out[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.927 0.000 288.945 0.054 ; + END + END rw0_rd_out[580] + PIN rw0_rd_out[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.107 0.000 289.125 0.054 ; + END + END rw0_rd_out[581] + PIN rw0_rd_out[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.287 0.000 289.305 0.054 ; + END + END rw0_rd_out[582] + PIN rw0_rd_out[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.467 0.000 289.485 0.054 ; + END + END rw0_rd_out[583] + PIN rw0_rd_out[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.647 0.000 289.665 0.054 ; + END + END rw0_rd_out[584] + PIN rw0_rd_out[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.827 0.000 289.845 0.054 ; + END + END rw0_rd_out[585] + PIN rw0_rd_out[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.007 0.000 290.025 0.054 ; + END + END rw0_rd_out[586] + PIN rw0_rd_out[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.187 0.000 290.205 0.054 ; + END + END rw0_rd_out[587] + PIN rw0_rd_out[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.367 0.000 290.385 0.054 ; + END + END rw0_rd_out[588] + PIN rw0_rd_out[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.547 0.000 290.565 0.054 ; + END + END rw0_rd_out[589] + PIN rw0_rd_out[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.727 0.000 290.745 0.054 ; + END + END rw0_rd_out[590] + PIN rw0_rd_out[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.907 0.000 290.925 0.054 ; + END + END rw0_rd_out[591] + PIN rw0_rd_out[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.087 0.000 291.105 0.054 ; + END + END rw0_rd_out[592] + PIN rw0_rd_out[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.267 0.000 291.285 0.054 ; + END + END rw0_rd_out[593] + PIN rw0_rd_out[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.447 0.000 291.465 0.054 ; + END + END rw0_rd_out[594] + PIN rw0_rd_out[595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.627 0.000 291.645 0.054 ; + END + END rw0_rd_out[595] + PIN rw0_rd_out[596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.807 0.000 291.825 0.054 ; + END + END rw0_rd_out[596] + PIN rw0_rd_out[597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.987 0.000 292.005 0.054 ; + END + END rw0_rd_out[597] + PIN rw0_rd_out[598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.167 0.000 292.185 0.054 ; + END + END rw0_rd_out[598] + PIN rw0_rd_out[599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.347 0.000 292.365 0.054 ; + END + END rw0_rd_out[599] + PIN rw0_rd_out[600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.527 0.000 292.545 0.054 ; + END + END rw0_rd_out[600] + PIN rw0_rd_out[601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.707 0.000 292.725 0.054 ; + END + END rw0_rd_out[601] + PIN rw0_rd_out[602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.887 0.000 292.905 0.054 ; + END + END rw0_rd_out[602] + PIN rw0_rd_out[603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.067 0.000 293.085 0.054 ; + END + END rw0_rd_out[603] + PIN rw0_rd_out[604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.247 0.000 293.265 0.054 ; + END + END rw0_rd_out[604] + PIN rw0_rd_out[605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.427 0.000 293.445 0.054 ; + END + END rw0_rd_out[605] + PIN rw0_rd_out[606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.607 0.000 293.625 0.054 ; + END + END rw0_rd_out[606] + PIN rw0_rd_out[607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.787 0.000 293.805 0.054 ; + END + END rw0_rd_out[607] + PIN rw0_rd_out[608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.967 0.000 293.985 0.054 ; + END + END rw0_rd_out[608] + PIN rw0_rd_out[609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.147 0.000 294.165 0.054 ; + END + END rw0_rd_out[609] + PIN rw0_rd_out[610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.327 0.000 294.345 0.054 ; + END + END rw0_rd_out[610] + PIN rw0_rd_out[611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.507 0.000 294.525 0.054 ; + END + END rw0_rd_out[611] + PIN rw0_rd_out[612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.687 0.000 294.705 0.054 ; + END + END rw0_rd_out[612] + PIN rw0_rd_out[613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.867 0.000 294.885 0.054 ; + END + END rw0_rd_out[613] + PIN rw0_rd_out[614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.047 0.000 295.065 0.054 ; + END + END rw0_rd_out[614] + PIN rw0_rd_out[615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.227 0.000 295.245 0.054 ; + END + END rw0_rd_out[615] + PIN rw0_rd_out[616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.407 0.000 295.425 0.054 ; + END + END rw0_rd_out[616] + PIN rw0_rd_out[617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.587 0.000 295.605 0.054 ; + END + END rw0_rd_out[617] + PIN rw0_rd_out[618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.767 0.000 295.785 0.054 ; + END + END rw0_rd_out[618] + PIN rw0_rd_out[619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.947 0.000 295.965 0.054 ; + END + END rw0_rd_out[619] + PIN rw0_rd_out[620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.127 0.000 296.145 0.054 ; + END + END rw0_rd_out[620] + PIN rw0_rd_out[621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.307 0.000 296.325 0.054 ; + END + END rw0_rd_out[621] + PIN rw0_rd_out[622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.487 0.000 296.505 0.054 ; + END + END rw0_rd_out[622] + PIN rw0_rd_out[623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.667 0.000 296.685 0.054 ; + END + END rw0_rd_out[623] + PIN rw0_rd_out[624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.847 0.000 296.865 0.054 ; + END + END rw0_rd_out[624] + PIN rw0_rd_out[625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.027 0.000 297.045 0.054 ; + END + END rw0_rd_out[625] + PIN rw0_rd_out[626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.207 0.000 297.225 0.054 ; + END + END rw0_rd_out[626] + PIN rw0_rd_out[627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.387 0.000 297.405 0.054 ; + END + END rw0_rd_out[627] + PIN rw0_rd_out[628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.567 0.000 297.585 0.054 ; + END + END rw0_rd_out[628] + PIN rw0_rd_out[629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.747 0.000 297.765 0.054 ; + END + END rw0_rd_out[629] + PIN rw0_rd_out[630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.927 0.000 297.945 0.054 ; + END + END rw0_rd_out[630] + PIN rw0_rd_out[631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.107 0.000 298.125 0.054 ; + END + END rw0_rd_out[631] + PIN rw0_rd_out[632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.287 0.000 298.305 0.054 ; + END + END rw0_rd_out[632] + PIN rw0_rd_out[633] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.467 0.000 298.485 0.054 ; + END + END rw0_rd_out[633] + PIN rw0_rd_out[634] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.647 0.000 298.665 0.054 ; + END + END rw0_rd_out[634] + PIN rw0_rd_out[635] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.827 0.000 298.845 0.054 ; + END + END rw0_rd_out[635] + PIN rw0_rd_out[636] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.007 0.000 299.025 0.054 ; + END + END rw0_rd_out[636] + PIN rw0_rd_out[637] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.187 0.000 299.205 0.054 ; + END + END rw0_rd_out[637] + PIN rw0_rd_out[638] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.367 0.000 299.385 0.054 ; + END + END rw0_rd_out[638] + PIN rw0_rd_out[639] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.547 0.000 299.565 0.054 ; + END + END rw0_rd_out[639] + PIN rw0_rd_out[640] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.727 0.000 299.745 0.054 ; + END + END rw0_rd_out[640] + PIN rw0_rd_out[641] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.907 0.000 299.925 0.054 ; + END + END rw0_rd_out[641] + PIN rw0_rd_out[642] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.087 0.000 300.105 0.054 ; + END + END rw0_rd_out[642] + PIN rw0_rd_out[643] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.267 0.000 300.285 0.054 ; + END + END rw0_rd_out[643] + PIN rw0_rd_out[644] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.447 0.000 300.465 0.054 ; + END + END rw0_rd_out[644] + PIN rw0_rd_out[645] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.627 0.000 300.645 0.054 ; + END + END rw0_rd_out[645] + PIN rw0_rd_out[646] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.807 0.000 300.825 0.054 ; + END + END rw0_rd_out[646] + PIN rw0_rd_out[647] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.987 0.000 301.005 0.054 ; + END + END rw0_rd_out[647] + PIN rw0_rd_out[648] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.167 0.000 301.185 0.054 ; + END + END rw0_rd_out[648] + PIN rw0_rd_out[649] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.347 0.000 301.365 0.054 ; + END + END rw0_rd_out[649] + PIN rw0_rd_out[650] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.527 0.000 301.545 0.054 ; + END + END rw0_rd_out[650] + PIN rw0_rd_out[651] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.707 0.000 301.725 0.054 ; + END + END rw0_rd_out[651] + PIN rw0_rd_out[652] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.887 0.000 301.905 0.054 ; + END + END rw0_rd_out[652] + PIN rw0_rd_out[653] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.067 0.000 302.085 0.054 ; + END + END rw0_rd_out[653] + PIN rw0_rd_out[654] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.247 0.000 302.265 0.054 ; + END + END rw0_rd_out[654] + PIN rw0_rd_out[655] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.427 0.000 302.445 0.054 ; + END + END rw0_rd_out[655] + PIN rw0_rd_out[656] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.607 0.000 302.625 0.054 ; + END + END rw0_rd_out[656] + PIN rw0_rd_out[657] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.787 0.000 302.805 0.054 ; + END + END rw0_rd_out[657] + PIN rw0_rd_out[658] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.967 0.000 302.985 0.054 ; + END + END rw0_rd_out[658] + PIN rw0_rd_out[659] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.147 0.000 303.165 0.054 ; + END + END rw0_rd_out[659] + PIN rw0_rd_out[660] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.327 0.000 303.345 0.054 ; + END + END rw0_rd_out[660] + PIN rw0_rd_out[661] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.507 0.000 303.525 0.054 ; + END + END rw0_rd_out[661] + PIN rw0_rd_out[662] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.687 0.000 303.705 0.054 ; + END + END rw0_rd_out[662] + PIN rw0_rd_out[663] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.867 0.000 303.885 0.054 ; + END + END rw0_rd_out[663] + PIN rw0_rd_out[664] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.047 0.000 304.065 0.054 ; + END + END rw0_rd_out[664] + PIN rw0_rd_out[665] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.227 0.000 304.245 0.054 ; + END + END rw0_rd_out[665] + PIN rw0_rd_out[666] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.407 0.000 304.425 0.054 ; + END + END rw0_rd_out[666] + PIN rw0_rd_out[667] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.587 0.000 304.605 0.054 ; + END + END rw0_rd_out[667] + PIN rw0_rd_out[668] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.767 0.000 304.785 0.054 ; + END + END rw0_rd_out[668] + PIN rw0_rd_out[669] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.947 0.000 304.965 0.054 ; + END + END rw0_rd_out[669] + PIN rw0_rd_out[670] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.127 0.000 305.145 0.054 ; + END + END rw0_rd_out[670] + PIN rw0_rd_out[671] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.307 0.000 305.325 0.054 ; + END + END rw0_rd_out[671] + PIN rw0_rd_out[672] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.487 0.000 305.505 0.054 ; + END + END rw0_rd_out[672] + PIN rw0_rd_out[673] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.667 0.000 305.685 0.054 ; + END + END rw0_rd_out[673] + PIN rw0_rd_out[674] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.847 0.000 305.865 0.054 ; + END + END rw0_rd_out[674] + PIN rw0_rd_out[675] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.027 0.000 306.045 0.054 ; + END + END rw0_rd_out[675] + PIN rw0_rd_out[676] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.207 0.000 306.225 0.054 ; + END + END rw0_rd_out[676] + PIN rw0_rd_out[677] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.387 0.000 306.405 0.054 ; + END + END rw0_rd_out[677] + PIN rw0_rd_out[678] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.567 0.000 306.585 0.054 ; + END + END rw0_rd_out[678] + PIN rw0_rd_out[679] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.747 0.000 306.765 0.054 ; + END + END rw0_rd_out[679] + PIN rw0_rd_out[680] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.927 0.000 306.945 0.054 ; + END + END rw0_rd_out[680] + PIN rw0_rd_out[681] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.107 0.000 307.125 0.054 ; + END + END rw0_rd_out[681] + PIN rw0_rd_out[682] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.287 0.000 307.305 0.054 ; + END + END rw0_rd_out[682] + PIN rw0_rd_out[683] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.467 0.000 307.485 0.054 ; + END + END rw0_rd_out[683] + PIN rw0_rd_out[684] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.647 0.000 307.665 0.054 ; + END + END rw0_rd_out[684] + PIN rw0_rd_out[685] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.827 0.000 307.845 0.054 ; + END + END rw0_rd_out[685] + PIN rw0_rd_out[686] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.007 0.000 308.025 0.054 ; + END + END rw0_rd_out[686] + PIN rw0_rd_out[687] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.187 0.000 308.205 0.054 ; + END + END rw0_rd_out[687] + PIN rw0_rd_out[688] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.367 0.000 308.385 0.054 ; + END + END rw0_rd_out[688] + PIN rw0_rd_out[689] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.547 0.000 308.565 0.054 ; + END + END rw0_rd_out[689] + PIN rw0_rd_out[690] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.727 0.000 308.745 0.054 ; + END + END rw0_rd_out[690] + PIN rw0_rd_out[691] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.907 0.000 308.925 0.054 ; + END + END rw0_rd_out[691] + PIN rw0_rd_out[692] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.087 0.000 309.105 0.054 ; + END + END rw0_rd_out[692] + PIN rw0_rd_out[693] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.267 0.000 309.285 0.054 ; + END + END rw0_rd_out[693] + PIN rw0_rd_out[694] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.447 0.000 309.465 0.054 ; + END + END rw0_rd_out[694] + PIN rw0_rd_out[695] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.627 0.000 309.645 0.054 ; + END + END rw0_rd_out[695] + PIN rw0_rd_out[696] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.807 0.000 309.825 0.054 ; + END + END rw0_rd_out[696] + PIN rw0_rd_out[697] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.987 0.000 310.005 0.054 ; + END + END rw0_rd_out[697] + PIN rw0_rd_out[698] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.167 0.000 310.185 0.054 ; + END + END rw0_rd_out[698] + PIN rw0_rd_out[699] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.347 0.000 310.365 0.054 ; + END + END rw0_rd_out[699] + PIN rw0_rd_out[700] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.527 0.000 310.545 0.054 ; + END + END rw0_rd_out[700] + PIN rw0_rd_out[701] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.707 0.000 310.725 0.054 ; + END + END rw0_rd_out[701] + PIN rw0_rd_out[702] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.887 0.000 310.905 0.054 ; + END + END rw0_rd_out[702] + PIN rw0_rd_out[703] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.067 0.000 311.085 0.054 ; + END + END rw0_rd_out[703] + PIN rw0_rd_out[704] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.247 0.000 311.265 0.054 ; + END + END rw0_rd_out[704] + PIN rw0_rd_out[705] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.427 0.000 311.445 0.054 ; + END + END rw0_rd_out[705] + PIN rw0_rd_out[706] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.607 0.000 311.625 0.054 ; + END + END rw0_rd_out[706] + PIN rw0_rd_out[707] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.787 0.000 311.805 0.054 ; + END + END rw0_rd_out[707] + PIN rw0_rd_out[708] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.967 0.000 311.985 0.054 ; + END + END rw0_rd_out[708] + PIN rw0_rd_out[709] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.147 0.000 312.165 0.054 ; + END + END rw0_rd_out[709] + PIN rw0_rd_out[710] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.327 0.000 312.345 0.054 ; + END + END rw0_rd_out[710] + PIN rw0_rd_out[711] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.507 0.000 312.525 0.054 ; + END + END rw0_rd_out[711] + PIN rw0_rd_out[712] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.687 0.000 312.705 0.054 ; + END + END rw0_rd_out[712] + PIN rw0_rd_out[713] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.867 0.000 312.885 0.054 ; + END + END rw0_rd_out[713] + PIN rw0_rd_out[714] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.047 0.000 313.065 0.054 ; + END + END rw0_rd_out[714] + PIN rw0_rd_out[715] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.227 0.000 313.245 0.054 ; + END + END rw0_rd_out[715] + PIN rw0_rd_out[716] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.407 0.000 313.425 0.054 ; + END + END rw0_rd_out[716] + PIN rw0_rd_out[717] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.587 0.000 313.605 0.054 ; + END + END rw0_rd_out[717] + PIN rw0_rd_out[718] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.767 0.000 313.785 0.054 ; + END + END rw0_rd_out[718] + PIN rw0_rd_out[719] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.947 0.000 313.965 0.054 ; + END + END rw0_rd_out[719] + PIN rw0_rd_out[720] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.127 0.000 314.145 0.054 ; + END + END rw0_rd_out[720] + PIN rw0_rd_out[721] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.307 0.000 314.325 0.054 ; + END + END rw0_rd_out[721] + PIN rw0_rd_out[722] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.487 0.000 314.505 0.054 ; + END + END rw0_rd_out[722] + PIN rw0_rd_out[723] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.667 0.000 314.685 0.054 ; + END + END rw0_rd_out[723] + PIN rw0_rd_out[724] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.847 0.000 314.865 0.054 ; + END + END rw0_rd_out[724] + PIN rw0_rd_out[725] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.027 0.000 315.045 0.054 ; + END + END rw0_rd_out[725] + PIN rw0_rd_out[726] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.207 0.000 315.225 0.054 ; + END + END rw0_rd_out[726] + PIN rw0_rd_out[727] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.387 0.000 315.405 0.054 ; + END + END rw0_rd_out[727] + PIN rw0_rd_out[728] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.567 0.000 315.585 0.054 ; + END + END rw0_rd_out[728] + PIN rw0_rd_out[729] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.747 0.000 315.765 0.054 ; + END + END rw0_rd_out[729] + PIN rw0_rd_out[730] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.927 0.000 315.945 0.054 ; + END + END rw0_rd_out[730] + PIN rw0_rd_out[731] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.107 0.000 316.125 0.054 ; + END + END rw0_rd_out[731] + PIN rw0_rd_out[732] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.287 0.000 316.305 0.054 ; + END + END rw0_rd_out[732] + PIN rw0_rd_out[733] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.467 0.000 316.485 0.054 ; + END + END rw0_rd_out[733] + PIN rw0_rd_out[734] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.647 0.000 316.665 0.054 ; + END + END rw0_rd_out[734] + PIN rw0_rd_out[735] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.827 0.000 316.845 0.054 ; + END + END rw0_rd_out[735] + PIN rw0_rd_out[736] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.007 0.000 317.025 0.054 ; + END + END rw0_rd_out[736] + PIN rw0_rd_out[737] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.187 0.000 317.205 0.054 ; + END + END rw0_rd_out[737] + PIN rw0_rd_out[738] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.367 0.000 317.385 0.054 ; + END + END rw0_rd_out[738] + PIN rw0_rd_out[739] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.547 0.000 317.565 0.054 ; + END + END rw0_rd_out[739] + PIN rw0_rd_out[740] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.727 0.000 317.745 0.054 ; + END + END rw0_rd_out[740] + PIN rw0_rd_out[741] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.907 0.000 317.925 0.054 ; + END + END rw0_rd_out[741] + PIN rw0_rd_out[742] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.087 0.000 318.105 0.054 ; + END + END rw0_rd_out[742] + PIN rw0_rd_out[743] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.267 0.000 318.285 0.054 ; + END + END rw0_rd_out[743] + PIN rw0_rd_out[744] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.447 0.000 318.465 0.054 ; + END + END rw0_rd_out[744] + PIN rw0_rd_out[745] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.627 0.000 318.645 0.054 ; + END + END rw0_rd_out[745] + PIN rw0_rd_out[746] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.807 0.000 318.825 0.054 ; + END + END rw0_rd_out[746] + PIN rw0_rd_out[747] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.987 0.000 319.005 0.054 ; + END + END rw0_rd_out[747] + PIN rw0_rd_out[748] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.167 0.000 319.185 0.054 ; + END + END rw0_rd_out[748] + PIN rw0_rd_out[749] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.347 0.000 319.365 0.054 ; + END + END rw0_rd_out[749] + PIN rw0_rd_out[750] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.527 0.000 319.545 0.054 ; + END + END rw0_rd_out[750] + PIN rw0_rd_out[751] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.707 0.000 319.725 0.054 ; + END + END rw0_rd_out[751] + PIN rw0_rd_out[752] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.887 0.000 319.905 0.054 ; + END + END rw0_rd_out[752] + PIN rw0_rd_out[753] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.067 0.000 320.085 0.054 ; + END + END rw0_rd_out[753] + PIN rw0_rd_out[754] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.247 0.000 320.265 0.054 ; + END + END rw0_rd_out[754] + PIN rw0_rd_out[755] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.427 0.000 320.445 0.054 ; + END + END rw0_rd_out[755] + PIN rw0_rd_out[756] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.607 0.000 320.625 0.054 ; + END + END rw0_rd_out[756] + PIN rw0_rd_out[757] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.787 0.000 320.805 0.054 ; + END + END rw0_rd_out[757] + PIN rw0_rd_out[758] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.967 0.000 320.985 0.054 ; + END + END rw0_rd_out[758] + PIN rw0_rd_out[759] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.147 0.000 321.165 0.054 ; + END + END rw0_rd_out[759] + PIN rw0_rd_out[760] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.327 0.000 321.345 0.054 ; + END + END rw0_rd_out[760] + PIN rw0_rd_out[761] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.507 0.000 321.525 0.054 ; + END + END rw0_rd_out[761] + PIN rw0_rd_out[762] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.687 0.000 321.705 0.054 ; + END + END rw0_rd_out[762] + PIN rw0_rd_out[763] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.867 0.000 321.885 0.054 ; + END + END rw0_rd_out[763] + PIN rw0_rd_out[764] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.047 0.000 322.065 0.054 ; + END + END rw0_rd_out[764] + PIN rw0_rd_out[765] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.227 0.000 322.245 0.054 ; + END + END rw0_rd_out[765] + PIN rw0_rd_out[766] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.407 0.000 322.425 0.054 ; + END + END rw0_rd_out[766] + PIN rw0_rd_out[767] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.587 0.000 322.605 0.054 ; + END + END rw0_rd_out[767] + PIN rw0_rd_out[768] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.767 0.000 322.785 0.054 ; + END + END rw0_rd_out[768] + PIN rw0_rd_out[769] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.947 0.000 322.965 0.054 ; + END + END rw0_rd_out[769] + PIN rw0_rd_out[770] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.127 0.000 323.145 0.054 ; + END + END rw0_rd_out[770] + PIN rw0_rd_out[771] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.307 0.000 323.325 0.054 ; + END + END rw0_rd_out[771] + PIN rw0_rd_out[772] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.487 0.000 323.505 0.054 ; + END + END rw0_rd_out[772] + PIN rw0_rd_out[773] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.667 0.000 323.685 0.054 ; + END + END rw0_rd_out[773] + PIN rw0_rd_out[774] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.847 0.000 323.865 0.054 ; + END + END rw0_rd_out[774] + PIN rw0_rd_out[775] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.027 0.000 324.045 0.054 ; + END + END rw0_rd_out[775] + PIN rw0_rd_out[776] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.207 0.000 324.225 0.054 ; + END + END rw0_rd_out[776] + PIN rw0_rd_out[777] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.387 0.000 324.405 0.054 ; + END + END rw0_rd_out[777] + PIN rw0_rd_out[778] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.567 0.000 324.585 0.054 ; + END + END rw0_rd_out[778] + PIN rw0_rd_out[779] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.747 0.000 324.765 0.054 ; + END + END rw0_rd_out[779] + PIN rw0_rd_out[780] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.927 0.000 324.945 0.054 ; + END + END rw0_rd_out[780] + PIN rw0_rd_out[781] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.107 0.000 325.125 0.054 ; + END + END rw0_rd_out[781] + PIN rw0_rd_out[782] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.287 0.000 325.305 0.054 ; + END + END rw0_rd_out[782] + PIN rw0_rd_out[783] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.467 0.000 325.485 0.054 ; + END + END rw0_rd_out[783] + PIN rw0_rd_out[784] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.647 0.000 325.665 0.054 ; + END + END rw0_rd_out[784] + PIN rw0_rd_out[785] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.827 0.000 325.845 0.054 ; + END + END rw0_rd_out[785] + PIN rw0_rd_out[786] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.007 0.000 326.025 0.054 ; + END + END rw0_rd_out[786] + PIN rw0_rd_out[787] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.187 0.000 326.205 0.054 ; + END + END rw0_rd_out[787] + PIN rw0_rd_out[788] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.367 0.000 326.385 0.054 ; + END + END rw0_rd_out[788] + PIN rw0_rd_out[789] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.547 0.000 326.565 0.054 ; + END + END rw0_rd_out[789] + PIN rw0_rd_out[790] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.727 0.000 326.745 0.054 ; + END + END rw0_rd_out[790] + PIN rw0_rd_out[791] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.907 0.000 326.925 0.054 ; + END + END rw0_rd_out[791] + PIN rw0_rd_out[792] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.087 0.000 327.105 0.054 ; + END + END rw0_rd_out[792] + PIN rw0_rd_out[793] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.267 0.000 327.285 0.054 ; + END + END rw0_rd_out[793] + PIN rw0_rd_out[794] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.447 0.000 327.465 0.054 ; + END + END rw0_rd_out[794] + PIN rw0_rd_out[795] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.627 0.000 327.645 0.054 ; + END + END rw0_rd_out[795] + PIN rw0_rd_out[796] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.807 0.000 327.825 0.054 ; + END + END rw0_rd_out[796] + PIN rw0_rd_out[797] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.987 0.000 328.005 0.054 ; + END + END rw0_rd_out[797] + PIN rw0_rd_out[798] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.167 0.000 328.185 0.054 ; + END + END rw0_rd_out[798] + PIN rw0_rd_out[799] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.347 0.000 328.365 0.054 ; + END + END rw0_rd_out[799] + PIN rw0_rd_out[800] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.527 0.000 328.545 0.054 ; + END + END rw0_rd_out[800] + PIN rw0_rd_out[801] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.707 0.000 328.725 0.054 ; + END + END rw0_rd_out[801] + PIN rw0_rd_out[802] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.887 0.000 328.905 0.054 ; + END + END rw0_rd_out[802] + PIN rw0_rd_out[803] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.067 0.000 329.085 0.054 ; + END + END rw0_rd_out[803] + PIN rw0_rd_out[804] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.247 0.000 329.265 0.054 ; + END + END rw0_rd_out[804] + PIN rw0_rd_out[805] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.427 0.000 329.445 0.054 ; + END + END rw0_rd_out[805] + PIN rw0_rd_out[806] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.607 0.000 329.625 0.054 ; + END + END rw0_rd_out[806] + PIN rw0_rd_out[807] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.787 0.000 329.805 0.054 ; + END + END rw0_rd_out[807] + PIN rw0_rd_out[808] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.967 0.000 329.985 0.054 ; + END + END rw0_rd_out[808] + PIN rw0_rd_out[809] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.147 0.000 330.165 0.054 ; + END + END rw0_rd_out[809] + PIN rw0_rd_out[810] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.327 0.000 330.345 0.054 ; + END + END rw0_rd_out[810] + PIN rw0_rd_out[811] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.507 0.000 330.525 0.054 ; + END + END rw0_rd_out[811] + PIN rw0_rd_out[812] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.687 0.000 330.705 0.054 ; + END + END rw0_rd_out[812] + PIN rw0_rd_out[813] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.867 0.000 330.885 0.054 ; + END + END rw0_rd_out[813] + PIN rw0_rd_out[814] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.047 0.000 331.065 0.054 ; + END + END rw0_rd_out[814] + PIN rw0_rd_out[815] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.227 0.000 331.245 0.054 ; + END + END rw0_rd_out[815] + PIN rw0_rd_out[816] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.407 0.000 331.425 0.054 ; + END + END rw0_rd_out[816] + PIN rw0_rd_out[817] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.587 0.000 331.605 0.054 ; + END + END rw0_rd_out[817] + PIN rw0_rd_out[818] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.767 0.000 331.785 0.054 ; + END + END rw0_rd_out[818] + PIN rw0_rd_out[819] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.947 0.000 331.965 0.054 ; + END + END rw0_rd_out[819] + PIN rw0_rd_out[820] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.127 0.000 332.145 0.054 ; + END + END rw0_rd_out[820] + PIN rw0_rd_out[821] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.307 0.000 332.325 0.054 ; + END + END rw0_rd_out[821] + PIN rw0_rd_out[822] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.487 0.000 332.505 0.054 ; + END + END rw0_rd_out[822] + PIN rw0_rd_out[823] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.667 0.000 332.685 0.054 ; + END + END rw0_rd_out[823] + PIN rw0_rd_out[824] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.847 0.000 332.865 0.054 ; + END + END rw0_rd_out[824] + PIN rw0_rd_out[825] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.027 0.000 333.045 0.054 ; + END + END rw0_rd_out[825] + PIN rw0_rd_out[826] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.207 0.000 333.225 0.054 ; + END + END rw0_rd_out[826] + PIN rw0_rd_out[827] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.387 0.000 333.405 0.054 ; + END + END rw0_rd_out[827] + PIN rw0_rd_out[828] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.567 0.000 333.585 0.054 ; + END + END rw0_rd_out[828] + PIN rw0_rd_out[829] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.747 0.000 333.765 0.054 ; + END + END rw0_rd_out[829] + PIN rw0_rd_out[830] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.927 0.000 333.945 0.054 ; + END + END rw0_rd_out[830] + PIN rw0_rd_out[831] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.107 0.000 334.125 0.054 ; + END + END rw0_rd_out[831] + PIN rw0_rd_out[832] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.287 0.000 334.305 0.054 ; + END + END rw0_rd_out[832] + PIN rw0_rd_out[833] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.467 0.000 334.485 0.054 ; + END + END rw0_rd_out[833] + PIN rw0_rd_out[834] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.647 0.000 334.665 0.054 ; + END + END rw0_rd_out[834] + PIN rw0_rd_out[835] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.827 0.000 334.845 0.054 ; + END + END rw0_rd_out[835] + PIN rw0_rd_out[836] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.007 0.000 335.025 0.054 ; + END + END rw0_rd_out[836] + PIN rw0_rd_out[837] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.187 0.000 335.205 0.054 ; + END + END rw0_rd_out[837] + PIN rw0_rd_out[838] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.367 0.000 335.385 0.054 ; + END + END rw0_rd_out[838] + PIN rw0_rd_out[839] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.547 0.000 335.565 0.054 ; + END + END rw0_rd_out[839] + PIN rw0_rd_out[840] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.727 0.000 335.745 0.054 ; + END + END rw0_rd_out[840] + PIN rw0_rd_out[841] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.907 0.000 335.925 0.054 ; + END + END rw0_rd_out[841] + PIN rw0_rd_out[842] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.087 0.000 336.105 0.054 ; + END + END rw0_rd_out[842] + PIN rw0_rd_out[843] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.267 0.000 336.285 0.054 ; + END + END rw0_rd_out[843] + PIN rw0_rd_out[844] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.447 0.000 336.465 0.054 ; + END + END rw0_rd_out[844] + PIN rw0_rd_out[845] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.627 0.000 336.645 0.054 ; + END + END rw0_rd_out[845] + PIN rw0_rd_out[846] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.807 0.000 336.825 0.054 ; + END + END rw0_rd_out[846] + PIN rw0_rd_out[847] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.987 0.000 337.005 0.054 ; + END + END rw0_rd_out[847] + PIN rw0_rd_out[848] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.167 0.000 337.185 0.054 ; + END + END rw0_rd_out[848] + PIN rw0_rd_out[849] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.347 0.000 337.365 0.054 ; + END + END rw0_rd_out[849] + PIN rw0_rd_out[850] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.527 0.000 337.545 0.054 ; + END + END rw0_rd_out[850] + PIN rw0_rd_out[851] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.707 0.000 337.725 0.054 ; + END + END rw0_rd_out[851] + PIN rw0_rd_out[852] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.887 0.000 337.905 0.054 ; + END + END rw0_rd_out[852] + PIN rw0_rd_out[853] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.067 0.000 338.085 0.054 ; + END + END rw0_rd_out[853] + PIN rw0_rd_out[854] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.247 0.000 338.265 0.054 ; + END + END rw0_rd_out[854] + PIN rw0_rd_out[855] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.427 0.000 338.445 0.054 ; + END + END rw0_rd_out[855] + PIN rw0_rd_out[856] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.607 0.000 338.625 0.054 ; + END + END rw0_rd_out[856] + PIN rw0_rd_out[857] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.787 0.000 338.805 0.054 ; + END + END rw0_rd_out[857] + PIN rw0_rd_out[858] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.967 0.000 338.985 0.054 ; + END + END rw0_rd_out[858] + PIN rw0_rd_out[859] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.147 0.000 339.165 0.054 ; + END + END rw0_rd_out[859] + PIN rw0_rd_out[860] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.327 0.000 339.345 0.054 ; + END + END rw0_rd_out[860] + PIN rw0_rd_out[861] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.507 0.000 339.525 0.054 ; + END + END rw0_rd_out[861] + PIN rw0_rd_out[862] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.687 0.000 339.705 0.054 ; + END + END rw0_rd_out[862] + PIN rw0_rd_out[863] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.867 0.000 339.885 0.054 ; + END + END rw0_rd_out[863] + PIN rw0_rd_out[864] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.047 0.000 340.065 0.054 ; + END + END rw0_rd_out[864] + PIN rw0_rd_out[865] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.227 0.000 340.245 0.054 ; + END + END rw0_rd_out[865] + PIN rw0_rd_out[866] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.407 0.000 340.425 0.054 ; + END + END rw0_rd_out[866] + PIN rw0_rd_out[867] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.587 0.000 340.605 0.054 ; + END + END rw0_rd_out[867] + PIN rw0_rd_out[868] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.767 0.000 340.785 0.054 ; + END + END rw0_rd_out[868] + PIN rw0_rd_out[869] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.947 0.000 340.965 0.054 ; + END + END rw0_rd_out[869] + PIN rw0_rd_out[870] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.127 0.000 341.145 0.054 ; + END + END rw0_rd_out[870] + PIN rw0_rd_out[871] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.307 0.000 341.325 0.054 ; + END + END rw0_rd_out[871] + PIN rw0_rd_out[872] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.487 0.000 341.505 0.054 ; + END + END rw0_rd_out[872] + PIN rw0_rd_out[873] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.667 0.000 341.685 0.054 ; + END + END rw0_rd_out[873] + PIN rw0_rd_out[874] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.847 0.000 341.865 0.054 ; + END + END rw0_rd_out[874] + PIN rw0_rd_out[875] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.027 0.000 342.045 0.054 ; + END + END rw0_rd_out[875] + PIN rw0_rd_out[876] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.207 0.000 342.225 0.054 ; + END + END rw0_rd_out[876] + PIN rw0_rd_out[877] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.387 0.000 342.405 0.054 ; + END + END rw0_rd_out[877] + PIN rw0_rd_out[878] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.567 0.000 342.585 0.054 ; + END + END rw0_rd_out[878] + PIN rw0_rd_out[879] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.747 0.000 342.765 0.054 ; + END + END rw0_rd_out[879] + PIN rw0_rd_out[880] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.927 0.000 342.945 0.054 ; + END + END rw0_rd_out[880] + PIN rw0_rd_out[881] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.107 0.000 343.125 0.054 ; + END + END rw0_rd_out[881] + PIN rw0_rd_out[882] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.287 0.000 343.305 0.054 ; + END + END rw0_rd_out[882] + PIN rw0_rd_out[883] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.467 0.000 343.485 0.054 ; + END + END rw0_rd_out[883] + PIN rw0_rd_out[884] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.647 0.000 343.665 0.054 ; + END + END rw0_rd_out[884] + PIN rw0_rd_out[885] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.827 0.000 343.845 0.054 ; + END + END rw0_rd_out[885] + PIN rw0_rd_out[886] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.007 0.000 344.025 0.054 ; + END + END rw0_rd_out[886] + PIN rw0_rd_out[887] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.187 0.000 344.205 0.054 ; + END + END rw0_rd_out[887] + PIN rw0_rd_out[888] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.367 0.000 344.385 0.054 ; + END + END rw0_rd_out[888] + PIN rw0_rd_out[889] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.547 0.000 344.565 0.054 ; + END + END rw0_rd_out[889] + PIN rw0_rd_out[890] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.727 0.000 344.745 0.054 ; + END + END rw0_rd_out[890] + PIN rw0_rd_out[891] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.907 0.000 344.925 0.054 ; + END + END rw0_rd_out[891] + PIN rw0_rd_out[892] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.087 0.000 345.105 0.054 ; + END + END rw0_rd_out[892] + PIN rw0_rd_out[893] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.267 0.000 345.285 0.054 ; + END + END rw0_rd_out[893] + PIN rw0_rd_out[894] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.447 0.000 345.465 0.054 ; + END + END rw0_rd_out[894] + PIN rw0_rd_out[895] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.627 0.000 345.645 0.054 ; + END + END rw0_rd_out[895] + PIN rw0_rd_out[896] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.807 0.000 345.825 0.054 ; + END + END rw0_rd_out[896] + PIN rw0_rd_out[897] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.987 0.000 346.005 0.054 ; + END + END rw0_rd_out[897] + PIN rw0_rd_out[898] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.167 0.000 346.185 0.054 ; + END + END rw0_rd_out[898] + PIN rw0_rd_out[899] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.347 0.000 346.365 0.054 ; + END + END rw0_rd_out[899] + PIN rw0_rd_out[900] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.527 0.000 346.545 0.054 ; + END + END rw0_rd_out[900] + PIN rw0_rd_out[901] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.707 0.000 346.725 0.054 ; + END + END rw0_rd_out[901] + PIN rw0_rd_out[902] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.887 0.000 346.905 0.054 ; + END + END rw0_rd_out[902] + PIN rw0_rd_out[903] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.067 0.000 347.085 0.054 ; + END + END rw0_rd_out[903] + PIN rw0_rd_out[904] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.247 0.000 347.265 0.054 ; + END + END rw0_rd_out[904] + PIN rw0_rd_out[905] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.427 0.000 347.445 0.054 ; + END + END rw0_rd_out[905] + PIN rw0_rd_out[906] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.607 0.000 347.625 0.054 ; + END + END rw0_rd_out[906] + PIN rw0_rd_out[907] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.787 0.000 347.805 0.054 ; + END + END rw0_rd_out[907] + PIN rw0_rd_out[908] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.967 0.000 347.985 0.054 ; + END + END rw0_rd_out[908] + PIN rw0_rd_out[909] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.147 0.000 348.165 0.054 ; + END + END rw0_rd_out[909] + PIN rw0_rd_out[910] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.327 0.000 348.345 0.054 ; + END + END rw0_rd_out[910] + PIN rw0_rd_out[911] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.507 0.000 348.525 0.054 ; + END + END rw0_rd_out[911] + PIN rw0_rd_out[912] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.687 0.000 348.705 0.054 ; + END + END rw0_rd_out[912] + PIN rw0_rd_out[913] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.867 0.000 348.885 0.054 ; + END + END rw0_rd_out[913] + PIN rw0_rd_out[914] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.047 0.000 349.065 0.054 ; + END + END rw0_rd_out[914] + PIN rw0_rd_out[915] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.227 0.000 349.245 0.054 ; + END + END rw0_rd_out[915] + PIN rw0_rd_out[916] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.407 0.000 349.425 0.054 ; + END + END rw0_rd_out[916] + PIN rw0_rd_out[917] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.587 0.000 349.605 0.054 ; + END + END rw0_rd_out[917] + PIN rw0_rd_out[918] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.767 0.000 349.785 0.054 ; + END + END rw0_rd_out[918] + PIN rw0_rd_out[919] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.947 0.000 349.965 0.054 ; + END + END rw0_rd_out[919] + PIN rw0_rd_out[920] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.127 0.000 350.145 0.054 ; + END + END rw0_rd_out[920] + PIN rw0_rd_out[921] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.307 0.000 350.325 0.054 ; + END + END rw0_rd_out[921] + PIN rw0_rd_out[922] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.487 0.000 350.505 0.054 ; + END + END rw0_rd_out[922] + PIN rw0_rd_out[923] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.667 0.000 350.685 0.054 ; + END + END rw0_rd_out[923] + PIN rw0_rd_out[924] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.847 0.000 350.865 0.054 ; + END + END rw0_rd_out[924] + PIN rw0_rd_out[925] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.027 0.000 351.045 0.054 ; + END + END rw0_rd_out[925] + PIN rw0_rd_out[926] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.207 0.000 351.225 0.054 ; + END + END rw0_rd_out[926] + PIN rw0_rd_out[927] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.387 0.000 351.405 0.054 ; + END + END rw0_rd_out[927] + PIN rw0_rd_out[928] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.567 0.000 351.585 0.054 ; + END + END rw0_rd_out[928] + PIN rw0_rd_out[929] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.747 0.000 351.765 0.054 ; + END + END rw0_rd_out[929] + PIN rw0_rd_out[930] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.927 0.000 351.945 0.054 ; + END + END rw0_rd_out[930] + PIN rw0_rd_out[931] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.107 0.000 352.125 0.054 ; + END + END rw0_rd_out[931] + PIN rw0_rd_out[932] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.287 0.000 352.305 0.054 ; + END + END rw0_rd_out[932] + PIN rw0_rd_out[933] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.467 0.000 352.485 0.054 ; + END + END rw0_rd_out[933] + PIN rw0_rd_out[934] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.647 0.000 352.665 0.054 ; + END + END rw0_rd_out[934] + PIN rw0_rd_out[935] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.827 0.000 352.845 0.054 ; + END + END rw0_rd_out[935] + PIN rw0_rd_out[936] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.007 0.000 353.025 0.054 ; + END + END rw0_rd_out[936] + PIN rw0_rd_out[937] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.187 0.000 353.205 0.054 ; + END + END rw0_rd_out[937] + PIN rw0_rd_out[938] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.367 0.000 353.385 0.054 ; + END + END rw0_rd_out[938] + PIN rw0_rd_out[939] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.547 0.000 353.565 0.054 ; + END + END rw0_rd_out[939] + PIN rw0_rd_out[940] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.727 0.000 353.745 0.054 ; + END + END rw0_rd_out[940] + PIN rw0_rd_out[941] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.907 0.000 353.925 0.054 ; + END + END rw0_rd_out[941] + PIN rw0_rd_out[942] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.087 0.000 354.105 0.054 ; + END + END rw0_rd_out[942] + PIN rw0_rd_out[943] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.267 0.000 354.285 0.054 ; + END + END rw0_rd_out[943] + PIN rw0_rd_out[944] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.447 0.000 354.465 0.054 ; + END + END rw0_rd_out[944] + PIN rw0_rd_out[945] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.627 0.000 354.645 0.054 ; + END + END rw0_rd_out[945] + PIN rw0_rd_out[946] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.807 0.000 354.825 0.054 ; + END + END rw0_rd_out[946] + PIN rw0_rd_out[947] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.987 0.000 355.005 0.054 ; + END + END rw0_rd_out[947] + PIN rw0_rd_out[948] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.167 0.000 355.185 0.054 ; + END + END rw0_rd_out[948] + PIN rw0_rd_out[949] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.347 0.000 355.365 0.054 ; + END + END rw0_rd_out[949] + PIN rw0_rd_out[950] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.527 0.000 355.545 0.054 ; + END + END rw0_rd_out[950] + PIN rw0_rd_out[951] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.707 0.000 355.725 0.054 ; + END + END rw0_rd_out[951] + PIN rw0_rd_out[952] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.887 0.000 355.905 0.054 ; + END + END rw0_rd_out[952] + PIN rw0_rd_out[953] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.067 0.000 356.085 0.054 ; + END + END rw0_rd_out[953] + PIN rw0_rd_out[954] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.247 0.000 356.265 0.054 ; + END + END rw0_rd_out[954] + PIN rw0_rd_out[955] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.427 0.000 356.445 0.054 ; + END + END rw0_rd_out[955] + PIN rw0_rd_out[956] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.607 0.000 356.625 0.054 ; + END + END rw0_rd_out[956] + PIN rw0_rd_out[957] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.787 0.000 356.805 0.054 ; + END + END rw0_rd_out[957] + PIN rw0_rd_out[958] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.967 0.000 356.985 0.054 ; + END + END rw0_rd_out[958] + PIN rw0_rd_out[959] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.147 0.000 357.165 0.054 ; + END + END rw0_rd_out[959] + PIN rw0_rd_out[960] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.327 0.000 357.345 0.054 ; + END + END rw0_rd_out[960] + PIN rw0_rd_out[961] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.507 0.000 357.525 0.054 ; + END + END rw0_rd_out[961] + PIN rw0_rd_out[962] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.687 0.000 357.705 0.054 ; + END + END rw0_rd_out[962] + PIN rw0_rd_out[963] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.867 0.000 357.885 0.054 ; + END + END rw0_rd_out[963] + PIN rw0_rd_out[964] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.047 0.000 358.065 0.054 ; + END + END rw0_rd_out[964] + PIN rw0_rd_out[965] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.227 0.000 358.245 0.054 ; + END + END rw0_rd_out[965] + PIN rw0_rd_out[966] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.407 0.000 358.425 0.054 ; + END + END rw0_rd_out[966] + PIN rw0_rd_out[967] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.587 0.000 358.605 0.054 ; + END + END rw0_rd_out[967] + PIN rw0_rd_out[968] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.767 0.000 358.785 0.054 ; + END + END rw0_rd_out[968] + PIN rw0_rd_out[969] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.947 0.000 358.965 0.054 ; + END + END rw0_rd_out[969] + PIN rw0_rd_out[970] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.127 0.000 359.145 0.054 ; + END + END rw0_rd_out[970] + PIN rw0_rd_out[971] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.307 0.000 359.325 0.054 ; + END + END rw0_rd_out[971] + PIN rw0_rd_out[972] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.487 0.000 359.505 0.054 ; + END + END rw0_rd_out[972] + PIN rw0_rd_out[973] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.667 0.000 359.685 0.054 ; + END + END rw0_rd_out[973] + PIN rw0_rd_out[974] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.847 0.000 359.865 0.054 ; + END + END rw0_rd_out[974] + PIN rw0_rd_out[975] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.027 0.000 360.045 0.054 ; + END + END rw0_rd_out[975] + PIN rw0_rd_out[976] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.207 0.000 360.225 0.054 ; + END + END rw0_rd_out[976] + PIN rw0_rd_out[977] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.387 0.000 360.405 0.054 ; + END + END rw0_rd_out[977] + PIN rw0_rd_out[978] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.567 0.000 360.585 0.054 ; + END + END rw0_rd_out[978] + PIN rw0_rd_out[979] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.747 0.000 360.765 0.054 ; + END + END rw0_rd_out[979] + PIN rw0_rd_out[980] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.927 0.000 360.945 0.054 ; + END + END rw0_rd_out[980] + PIN rw0_rd_out[981] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.107 0.000 361.125 0.054 ; + END + END rw0_rd_out[981] + PIN rw0_rd_out[982] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.287 0.000 361.305 0.054 ; + END + END rw0_rd_out[982] + PIN rw0_rd_out[983] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.467 0.000 361.485 0.054 ; + END + END rw0_rd_out[983] + PIN rw0_rd_out[984] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.647 0.000 361.665 0.054 ; + END + END rw0_rd_out[984] + PIN rw0_rd_out[985] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.827 0.000 361.845 0.054 ; + END + END rw0_rd_out[985] + PIN rw0_rd_out[986] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.007 0.000 362.025 0.054 ; + END + END rw0_rd_out[986] + PIN rw0_rd_out[987] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.187 0.000 362.205 0.054 ; + END + END rw0_rd_out[987] + PIN rw0_rd_out[988] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.367 0.000 362.385 0.054 ; + END + END rw0_rd_out[988] + PIN rw0_rd_out[989] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.547 0.000 362.565 0.054 ; + END + END rw0_rd_out[989] + PIN rw0_rd_out[990] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.727 0.000 362.745 0.054 ; + END + END rw0_rd_out[990] + PIN rw0_rd_out[991] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.907 0.000 362.925 0.054 ; + END + END rw0_rd_out[991] + PIN rw0_rd_out[992] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.087 0.000 363.105 0.054 ; + END + END rw0_rd_out[992] + PIN rw0_rd_out[993] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.267 0.000 363.285 0.054 ; + END + END rw0_rd_out[993] + PIN rw0_rd_out[994] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.447 0.000 363.465 0.054 ; + END + END rw0_rd_out[994] + PIN rw0_rd_out[995] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.627 0.000 363.645 0.054 ; + END + END rw0_rd_out[995] + PIN rw0_rd_out[996] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.807 0.000 363.825 0.054 ; + END + END rw0_rd_out[996] + PIN rw0_rd_out[997] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.987 0.000 364.005 0.054 ; + END + END rw0_rd_out[997] + PIN rw0_rd_out[998] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.167 0.000 364.185 0.054 ; + END + END rw0_rd_out[998] + PIN rw0_rd_out[999] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.347 0.000 364.365 0.054 ; + END + END rw0_rd_out[999] + PIN rw0_rd_out[1000] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.527 0.000 364.545 0.054 ; + END + END rw0_rd_out[1000] + PIN rw0_rd_out[1001] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.707 0.000 364.725 0.054 ; + END + END rw0_rd_out[1001] + PIN rw0_rd_out[1002] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.887 0.000 364.905 0.054 ; + END + END rw0_rd_out[1002] + PIN rw0_rd_out[1003] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.067 0.000 365.085 0.054 ; + END + END rw0_rd_out[1003] + PIN rw0_rd_out[1004] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.247 0.000 365.265 0.054 ; + END + END rw0_rd_out[1004] + PIN rw0_rd_out[1005] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.427 0.000 365.445 0.054 ; + END + END rw0_rd_out[1005] + PIN rw0_rd_out[1006] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.607 0.000 365.625 0.054 ; + END + END rw0_rd_out[1006] + PIN rw0_rd_out[1007] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.787 0.000 365.805 0.054 ; + END + END rw0_rd_out[1007] + PIN rw0_rd_out[1008] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.967 0.000 365.985 0.054 ; + END + END rw0_rd_out[1008] + PIN rw0_rd_out[1009] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.147 0.000 366.165 0.054 ; + END + END rw0_rd_out[1009] + PIN rw0_rd_out[1010] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.327 0.000 366.345 0.054 ; + END + END rw0_rd_out[1010] + PIN rw0_rd_out[1011] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.507 0.000 366.525 0.054 ; + END + END rw0_rd_out[1011] + PIN rw0_rd_out[1012] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.687 0.000 366.705 0.054 ; + END + END rw0_rd_out[1012] + PIN rw0_rd_out[1013] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.867 0.000 366.885 0.054 ; + END + END rw0_rd_out[1013] + PIN rw0_rd_out[1014] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.047 0.000 367.065 0.054 ; + END + END rw0_rd_out[1014] + PIN rw0_rd_out[1015] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.227 0.000 367.245 0.054 ; + END + END rw0_rd_out[1015] + PIN rw0_rd_out[1016] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.407 0.000 367.425 0.054 ; + END + END rw0_rd_out[1016] + PIN rw0_rd_out[1017] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.587 0.000 367.605 0.054 ; + END + END rw0_rd_out[1017] + PIN rw0_rd_out[1018] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.767 0.000 367.785 0.054 ; + END + END rw0_rd_out[1018] + PIN rw0_rd_out[1019] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.947 0.000 367.965 0.054 ; + END + END rw0_rd_out[1019] + PIN rw0_rd_out[1020] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.127 0.000 368.145 0.054 ; + END + END rw0_rd_out[1020] + PIN rw0_rd_out[1021] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.307 0.000 368.325 0.054 ; + END + END rw0_rd_out[1021] + PIN rw0_rd_out[1022] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.487 0.000 368.505 0.054 ; + END + END rw0_rd_out[1022] + PIN rw0_rd_out[1023] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.667 0.000 368.685 0.054 ; + END + END rw0_rd_out[1023] + PIN rw0_rd_out[1024] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.527 129.961 184.545 130.015 ; + END + END rw0_rd_out[1024] + PIN rw0_rd_out[1025] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.707 129.961 184.725 130.015 ; + END + END rw0_rd_out[1025] + PIN rw0_rd_out[1026] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.887 129.961 184.905 130.015 ; + END + END rw0_rd_out[1026] + PIN rw0_rd_out[1027] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.067 129.961 185.085 130.015 ; + END + END rw0_rd_out[1027] + PIN rw0_rd_out[1028] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.247 129.961 185.265 130.015 ; + END + END rw0_rd_out[1028] + PIN rw0_rd_out[1029] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.427 129.961 185.445 130.015 ; + END + END rw0_rd_out[1029] + PIN rw0_rd_out[1030] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.607 129.961 185.625 130.015 ; + END + END rw0_rd_out[1030] + PIN rw0_rd_out[1031] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.787 129.961 185.805 130.015 ; + END + END rw0_rd_out[1031] + PIN rw0_rd_out[1032] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.967 129.961 185.985 130.015 ; + END + END rw0_rd_out[1032] + PIN rw0_rd_out[1033] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.147 129.961 186.165 130.015 ; + END + END rw0_rd_out[1033] + PIN rw0_rd_out[1034] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.327 129.961 186.345 130.015 ; + END + END rw0_rd_out[1034] + PIN rw0_rd_out[1035] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.507 129.961 186.525 130.015 ; + END + END rw0_rd_out[1035] + PIN rw0_rd_out[1036] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.687 129.961 186.705 130.015 ; + END + END rw0_rd_out[1036] + PIN rw0_rd_out[1037] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.867 129.961 186.885 130.015 ; + END + END rw0_rd_out[1037] + PIN rw0_rd_out[1038] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.047 129.961 187.065 130.015 ; + END + END rw0_rd_out[1038] + PIN rw0_rd_out[1039] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.227 129.961 187.245 130.015 ; + END + END rw0_rd_out[1039] + PIN rw0_rd_out[1040] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.407 129.961 187.425 130.015 ; + END + END rw0_rd_out[1040] + PIN rw0_rd_out[1041] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.587 129.961 187.605 130.015 ; + END + END rw0_rd_out[1041] + PIN rw0_rd_out[1042] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.767 129.961 187.785 130.015 ; + END + END rw0_rd_out[1042] + PIN rw0_rd_out[1043] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.947 129.961 187.965 130.015 ; + END + END rw0_rd_out[1043] + PIN rw0_rd_out[1044] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.127 129.961 188.145 130.015 ; + END + END rw0_rd_out[1044] + PIN rw0_rd_out[1045] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.307 129.961 188.325 130.015 ; + END + END rw0_rd_out[1045] + PIN rw0_rd_out[1046] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.487 129.961 188.505 130.015 ; + END + END rw0_rd_out[1046] + PIN rw0_rd_out[1047] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.667 129.961 188.685 130.015 ; + END + END rw0_rd_out[1047] + PIN rw0_rd_out[1048] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.847 129.961 188.865 130.015 ; + END + END rw0_rd_out[1048] + PIN rw0_rd_out[1049] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.027 129.961 189.045 130.015 ; + END + END rw0_rd_out[1049] + PIN rw0_rd_out[1050] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.207 129.961 189.225 130.015 ; + END + END rw0_rd_out[1050] + PIN rw0_rd_out[1051] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.387 129.961 189.405 130.015 ; + END + END rw0_rd_out[1051] + PIN rw0_rd_out[1052] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.567 129.961 189.585 130.015 ; + END + END rw0_rd_out[1052] + PIN rw0_rd_out[1053] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.747 129.961 189.765 130.015 ; + END + END rw0_rd_out[1053] + PIN rw0_rd_out[1054] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.927 129.961 189.945 130.015 ; + END + END rw0_rd_out[1054] + PIN rw0_rd_out[1055] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.107 129.961 190.125 130.015 ; + END + END rw0_rd_out[1055] + PIN rw0_rd_out[1056] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.287 129.961 190.305 130.015 ; + END + END rw0_rd_out[1056] + PIN rw0_rd_out[1057] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.467 129.961 190.485 130.015 ; + END + END rw0_rd_out[1057] + PIN rw0_rd_out[1058] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.647 129.961 190.665 130.015 ; + END + END rw0_rd_out[1058] + PIN rw0_rd_out[1059] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 190.827 129.961 190.845 130.015 ; + END + END rw0_rd_out[1059] + PIN rw0_rd_out[1060] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.007 129.961 191.025 130.015 ; + END + END rw0_rd_out[1060] + PIN rw0_rd_out[1061] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.187 129.961 191.205 130.015 ; + END + END rw0_rd_out[1061] + PIN rw0_rd_out[1062] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.367 129.961 191.385 130.015 ; + END + END rw0_rd_out[1062] + PIN rw0_rd_out[1063] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.547 129.961 191.565 130.015 ; + END + END rw0_rd_out[1063] + PIN rw0_rd_out[1064] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.727 129.961 191.745 130.015 ; + END + END rw0_rd_out[1064] + PIN rw0_rd_out[1065] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 191.907 129.961 191.925 130.015 ; + END + END rw0_rd_out[1065] + PIN rw0_rd_out[1066] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.087 129.961 192.105 130.015 ; + END + END rw0_rd_out[1066] + PIN rw0_rd_out[1067] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.267 129.961 192.285 130.015 ; + END + END rw0_rd_out[1067] + PIN rw0_rd_out[1068] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.447 129.961 192.465 130.015 ; + END + END rw0_rd_out[1068] + PIN rw0_rd_out[1069] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.627 129.961 192.645 130.015 ; + END + END rw0_rd_out[1069] + PIN rw0_rd_out[1070] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.807 129.961 192.825 130.015 ; + END + END rw0_rd_out[1070] + PIN rw0_rd_out[1071] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 192.987 129.961 193.005 130.015 ; + END + END rw0_rd_out[1071] + PIN rw0_rd_out[1072] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.167 129.961 193.185 130.015 ; + END + END rw0_rd_out[1072] + PIN rw0_rd_out[1073] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.347 129.961 193.365 130.015 ; + END + END rw0_rd_out[1073] + PIN rw0_rd_out[1074] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.527 129.961 193.545 130.015 ; + END + END rw0_rd_out[1074] + PIN rw0_rd_out[1075] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.707 129.961 193.725 130.015 ; + END + END rw0_rd_out[1075] + PIN rw0_rd_out[1076] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 193.887 129.961 193.905 130.015 ; + END + END rw0_rd_out[1076] + PIN rw0_rd_out[1077] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.067 129.961 194.085 130.015 ; + END + END rw0_rd_out[1077] + PIN rw0_rd_out[1078] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.247 129.961 194.265 130.015 ; + END + END rw0_rd_out[1078] + PIN rw0_rd_out[1079] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.427 129.961 194.445 130.015 ; + END + END rw0_rd_out[1079] + PIN rw0_rd_out[1080] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.607 129.961 194.625 130.015 ; + END + END rw0_rd_out[1080] + PIN rw0_rd_out[1081] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.787 129.961 194.805 130.015 ; + END + END rw0_rd_out[1081] + PIN rw0_rd_out[1082] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 194.967 129.961 194.985 130.015 ; + END + END rw0_rd_out[1082] + PIN rw0_rd_out[1083] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.147 129.961 195.165 130.015 ; + END + END rw0_rd_out[1083] + PIN rw0_rd_out[1084] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.327 129.961 195.345 130.015 ; + END + END rw0_rd_out[1084] + PIN rw0_rd_out[1085] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.507 129.961 195.525 130.015 ; + END + END rw0_rd_out[1085] + PIN rw0_rd_out[1086] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.687 129.961 195.705 130.015 ; + END + END rw0_rd_out[1086] + PIN rw0_rd_out[1087] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 195.867 129.961 195.885 130.015 ; + END + END rw0_rd_out[1087] + PIN rw0_rd_out[1088] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.047 129.961 196.065 130.015 ; + END + END rw0_rd_out[1088] + PIN rw0_rd_out[1089] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.227 129.961 196.245 130.015 ; + END + END rw0_rd_out[1089] + PIN rw0_rd_out[1090] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.407 129.961 196.425 130.015 ; + END + END rw0_rd_out[1090] + PIN rw0_rd_out[1091] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.587 129.961 196.605 130.015 ; + END + END rw0_rd_out[1091] + PIN rw0_rd_out[1092] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.767 129.961 196.785 130.015 ; + END + END rw0_rd_out[1092] + PIN rw0_rd_out[1093] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 196.947 129.961 196.965 130.015 ; + END + END rw0_rd_out[1093] + PIN rw0_rd_out[1094] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.127 129.961 197.145 130.015 ; + END + END rw0_rd_out[1094] + PIN rw0_rd_out[1095] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.307 129.961 197.325 130.015 ; + END + END rw0_rd_out[1095] + PIN rw0_rd_out[1096] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.487 129.961 197.505 130.015 ; + END + END rw0_rd_out[1096] + PIN rw0_rd_out[1097] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.667 129.961 197.685 130.015 ; + END + END rw0_rd_out[1097] + PIN rw0_rd_out[1098] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 197.847 129.961 197.865 130.015 ; + END + END rw0_rd_out[1098] + PIN rw0_rd_out[1099] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.027 129.961 198.045 130.015 ; + END + END rw0_rd_out[1099] + PIN rw0_rd_out[1100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.207 129.961 198.225 130.015 ; + END + END rw0_rd_out[1100] + PIN rw0_rd_out[1101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.387 129.961 198.405 130.015 ; + END + END rw0_rd_out[1101] + PIN rw0_rd_out[1102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.567 129.961 198.585 130.015 ; + END + END rw0_rd_out[1102] + PIN rw0_rd_out[1103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.747 129.961 198.765 130.015 ; + END + END rw0_rd_out[1103] + PIN rw0_rd_out[1104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 198.927 129.961 198.945 130.015 ; + END + END rw0_rd_out[1104] + PIN rw0_rd_out[1105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.107 129.961 199.125 130.015 ; + END + END rw0_rd_out[1105] + PIN rw0_rd_out[1106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.287 129.961 199.305 130.015 ; + END + END rw0_rd_out[1106] + PIN rw0_rd_out[1107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.467 129.961 199.485 130.015 ; + END + END rw0_rd_out[1107] + PIN rw0_rd_out[1108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.647 129.961 199.665 130.015 ; + END + END rw0_rd_out[1108] + PIN rw0_rd_out[1109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 199.827 129.961 199.845 130.015 ; + END + END rw0_rd_out[1109] + PIN rw0_rd_out[1110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.007 129.961 200.025 130.015 ; + END + END rw0_rd_out[1110] + PIN rw0_rd_out[1111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.187 129.961 200.205 130.015 ; + END + END rw0_rd_out[1111] + PIN rw0_rd_out[1112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.367 129.961 200.385 130.015 ; + END + END rw0_rd_out[1112] + PIN rw0_rd_out[1113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.547 129.961 200.565 130.015 ; + END + END rw0_rd_out[1113] + PIN rw0_rd_out[1114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.727 129.961 200.745 130.015 ; + END + END rw0_rd_out[1114] + PIN rw0_rd_out[1115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 200.907 129.961 200.925 130.015 ; + END + END rw0_rd_out[1115] + PIN rw0_rd_out[1116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.087 129.961 201.105 130.015 ; + END + END rw0_rd_out[1116] + PIN rw0_rd_out[1117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.267 129.961 201.285 130.015 ; + END + END rw0_rd_out[1117] + PIN rw0_rd_out[1118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.447 129.961 201.465 130.015 ; + END + END rw0_rd_out[1118] + PIN rw0_rd_out[1119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.627 129.961 201.645 130.015 ; + END + END rw0_rd_out[1119] + PIN rw0_rd_out[1120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.807 129.961 201.825 130.015 ; + END + END rw0_rd_out[1120] + PIN rw0_rd_out[1121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 201.987 129.961 202.005 130.015 ; + END + END rw0_rd_out[1121] + PIN rw0_rd_out[1122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.167 129.961 202.185 130.015 ; + END + END rw0_rd_out[1122] + PIN rw0_rd_out[1123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.347 129.961 202.365 130.015 ; + END + END rw0_rd_out[1123] + PIN rw0_rd_out[1124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.527 129.961 202.545 130.015 ; + END + END rw0_rd_out[1124] + PIN rw0_rd_out[1125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.707 129.961 202.725 130.015 ; + END + END rw0_rd_out[1125] + PIN rw0_rd_out[1126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 202.887 129.961 202.905 130.015 ; + END + END rw0_rd_out[1126] + PIN rw0_rd_out[1127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.067 129.961 203.085 130.015 ; + END + END rw0_rd_out[1127] + PIN rw0_rd_out[1128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.247 129.961 203.265 130.015 ; + END + END rw0_rd_out[1128] + PIN rw0_rd_out[1129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.427 129.961 203.445 130.015 ; + END + END rw0_rd_out[1129] + PIN rw0_rd_out[1130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.607 129.961 203.625 130.015 ; + END + END rw0_rd_out[1130] + PIN rw0_rd_out[1131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.787 129.961 203.805 130.015 ; + END + END rw0_rd_out[1131] + PIN rw0_rd_out[1132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 203.967 129.961 203.985 130.015 ; + END + END rw0_rd_out[1132] + PIN rw0_rd_out[1133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.147 129.961 204.165 130.015 ; + END + END rw0_rd_out[1133] + PIN rw0_rd_out[1134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.327 129.961 204.345 130.015 ; + END + END rw0_rd_out[1134] + PIN rw0_rd_out[1135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.507 129.961 204.525 130.015 ; + END + END rw0_rd_out[1135] + PIN rw0_rd_out[1136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.687 129.961 204.705 130.015 ; + END + END rw0_rd_out[1136] + PIN rw0_rd_out[1137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 204.867 129.961 204.885 130.015 ; + END + END rw0_rd_out[1137] + PIN rw0_rd_out[1138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.047 129.961 205.065 130.015 ; + END + END rw0_rd_out[1138] + PIN rw0_rd_out[1139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.227 129.961 205.245 130.015 ; + END + END rw0_rd_out[1139] + PIN rw0_rd_out[1140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.407 129.961 205.425 130.015 ; + END + END rw0_rd_out[1140] + PIN rw0_rd_out[1141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.587 129.961 205.605 130.015 ; + END + END rw0_rd_out[1141] + PIN rw0_rd_out[1142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.767 129.961 205.785 130.015 ; + END + END rw0_rd_out[1142] + PIN rw0_rd_out[1143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 205.947 129.961 205.965 130.015 ; + END + END rw0_rd_out[1143] + PIN rw0_rd_out[1144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.127 129.961 206.145 130.015 ; + END + END rw0_rd_out[1144] + PIN rw0_rd_out[1145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.307 129.961 206.325 130.015 ; + END + END rw0_rd_out[1145] + PIN rw0_rd_out[1146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.487 129.961 206.505 130.015 ; + END + END rw0_rd_out[1146] + PIN rw0_rd_out[1147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.667 129.961 206.685 130.015 ; + END + END rw0_rd_out[1147] + PIN rw0_rd_out[1148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 206.847 129.961 206.865 130.015 ; + END + END rw0_rd_out[1148] + PIN rw0_rd_out[1149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.027 129.961 207.045 130.015 ; + END + END rw0_rd_out[1149] + PIN rw0_rd_out[1150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.207 129.961 207.225 130.015 ; + END + END rw0_rd_out[1150] + PIN rw0_rd_out[1151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.387 129.961 207.405 130.015 ; + END + END rw0_rd_out[1151] + PIN rw0_rd_out[1152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.567 129.961 207.585 130.015 ; + END + END rw0_rd_out[1152] + PIN rw0_rd_out[1153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.747 129.961 207.765 130.015 ; + END + END rw0_rd_out[1153] + PIN rw0_rd_out[1154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 207.927 129.961 207.945 130.015 ; + END + END rw0_rd_out[1154] + PIN rw0_rd_out[1155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.107 129.961 208.125 130.015 ; + END + END rw0_rd_out[1155] + PIN rw0_rd_out[1156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.287 129.961 208.305 130.015 ; + END + END rw0_rd_out[1156] + PIN rw0_rd_out[1157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.467 129.961 208.485 130.015 ; + END + END rw0_rd_out[1157] + PIN rw0_rd_out[1158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.647 129.961 208.665 130.015 ; + END + END rw0_rd_out[1158] + PIN rw0_rd_out[1159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 208.827 129.961 208.845 130.015 ; + END + END rw0_rd_out[1159] + PIN rw0_rd_out[1160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.007 129.961 209.025 130.015 ; + END + END rw0_rd_out[1160] + PIN rw0_rd_out[1161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.187 129.961 209.205 130.015 ; + END + END rw0_rd_out[1161] + PIN rw0_rd_out[1162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.367 129.961 209.385 130.015 ; + END + END rw0_rd_out[1162] + PIN rw0_rd_out[1163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.547 129.961 209.565 130.015 ; + END + END rw0_rd_out[1163] + PIN rw0_rd_out[1164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.727 129.961 209.745 130.015 ; + END + END rw0_rd_out[1164] + PIN rw0_rd_out[1165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 209.907 129.961 209.925 130.015 ; + END + END rw0_rd_out[1165] + PIN rw0_rd_out[1166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.087 129.961 210.105 130.015 ; + END + END rw0_rd_out[1166] + PIN rw0_rd_out[1167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.267 129.961 210.285 130.015 ; + END + END rw0_rd_out[1167] + PIN rw0_rd_out[1168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.447 129.961 210.465 130.015 ; + END + END rw0_rd_out[1168] + PIN rw0_rd_out[1169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.627 129.961 210.645 130.015 ; + END + END rw0_rd_out[1169] + PIN rw0_rd_out[1170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.807 129.961 210.825 130.015 ; + END + END rw0_rd_out[1170] + PIN rw0_rd_out[1171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 210.987 129.961 211.005 130.015 ; + END + END rw0_rd_out[1171] + PIN rw0_rd_out[1172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.167 129.961 211.185 130.015 ; + END + END rw0_rd_out[1172] + PIN rw0_rd_out[1173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.347 129.961 211.365 130.015 ; + END + END rw0_rd_out[1173] + PIN rw0_rd_out[1174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.527 129.961 211.545 130.015 ; + END + END rw0_rd_out[1174] + PIN rw0_rd_out[1175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.707 129.961 211.725 130.015 ; + END + END rw0_rd_out[1175] + PIN rw0_rd_out[1176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 211.887 129.961 211.905 130.015 ; + END + END rw0_rd_out[1176] + PIN rw0_rd_out[1177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.067 129.961 212.085 130.015 ; + END + END rw0_rd_out[1177] + PIN rw0_rd_out[1178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.247 129.961 212.265 130.015 ; + END + END rw0_rd_out[1178] + PIN rw0_rd_out[1179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.427 129.961 212.445 130.015 ; + END + END rw0_rd_out[1179] + PIN rw0_rd_out[1180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.607 129.961 212.625 130.015 ; + END + END rw0_rd_out[1180] + PIN rw0_rd_out[1181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.787 129.961 212.805 130.015 ; + END + END rw0_rd_out[1181] + PIN rw0_rd_out[1182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 212.967 129.961 212.985 130.015 ; + END + END rw0_rd_out[1182] + PIN rw0_rd_out[1183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.147 129.961 213.165 130.015 ; + END + END rw0_rd_out[1183] + PIN rw0_rd_out[1184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.327 129.961 213.345 130.015 ; + END + END rw0_rd_out[1184] + PIN rw0_rd_out[1185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.507 129.961 213.525 130.015 ; + END + END rw0_rd_out[1185] + PIN rw0_rd_out[1186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.687 129.961 213.705 130.015 ; + END + END rw0_rd_out[1186] + PIN rw0_rd_out[1187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 213.867 129.961 213.885 130.015 ; + END + END rw0_rd_out[1187] + PIN rw0_rd_out[1188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.047 129.961 214.065 130.015 ; + END + END rw0_rd_out[1188] + PIN rw0_rd_out[1189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.227 129.961 214.245 130.015 ; + END + END rw0_rd_out[1189] + PIN rw0_rd_out[1190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.407 129.961 214.425 130.015 ; + END + END rw0_rd_out[1190] + PIN rw0_rd_out[1191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.587 129.961 214.605 130.015 ; + END + END rw0_rd_out[1191] + PIN rw0_rd_out[1192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.767 129.961 214.785 130.015 ; + END + END rw0_rd_out[1192] + PIN rw0_rd_out[1193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 214.947 129.961 214.965 130.015 ; + END + END rw0_rd_out[1193] + PIN rw0_rd_out[1194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.127 129.961 215.145 130.015 ; + END + END rw0_rd_out[1194] + PIN rw0_rd_out[1195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.307 129.961 215.325 130.015 ; + END + END rw0_rd_out[1195] + PIN rw0_rd_out[1196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.487 129.961 215.505 130.015 ; + END + END rw0_rd_out[1196] + PIN rw0_rd_out[1197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.667 129.961 215.685 130.015 ; + END + END rw0_rd_out[1197] + PIN rw0_rd_out[1198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 215.847 129.961 215.865 130.015 ; + END + END rw0_rd_out[1198] + PIN rw0_rd_out[1199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.027 129.961 216.045 130.015 ; + END + END rw0_rd_out[1199] + PIN rw0_rd_out[1200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.207 129.961 216.225 130.015 ; + END + END rw0_rd_out[1200] + PIN rw0_rd_out[1201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.387 129.961 216.405 130.015 ; + END + END rw0_rd_out[1201] + PIN rw0_rd_out[1202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.567 129.961 216.585 130.015 ; + END + END rw0_rd_out[1202] + PIN rw0_rd_out[1203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.747 129.961 216.765 130.015 ; + END + END rw0_rd_out[1203] + PIN rw0_rd_out[1204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 216.927 129.961 216.945 130.015 ; + END + END rw0_rd_out[1204] + PIN rw0_rd_out[1205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.107 129.961 217.125 130.015 ; + END + END rw0_rd_out[1205] + PIN rw0_rd_out[1206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.287 129.961 217.305 130.015 ; + END + END rw0_rd_out[1206] + PIN rw0_rd_out[1207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.467 129.961 217.485 130.015 ; + END + END rw0_rd_out[1207] + PIN rw0_rd_out[1208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.647 129.961 217.665 130.015 ; + END + END rw0_rd_out[1208] + PIN rw0_rd_out[1209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 217.827 129.961 217.845 130.015 ; + END + END rw0_rd_out[1209] + PIN rw0_rd_out[1210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.007 129.961 218.025 130.015 ; + END + END rw0_rd_out[1210] + PIN rw0_rd_out[1211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.187 129.961 218.205 130.015 ; + END + END rw0_rd_out[1211] + PIN rw0_rd_out[1212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.367 129.961 218.385 130.015 ; + END + END rw0_rd_out[1212] + PIN rw0_rd_out[1213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.547 129.961 218.565 130.015 ; + END + END rw0_rd_out[1213] + PIN rw0_rd_out[1214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.727 129.961 218.745 130.015 ; + END + END rw0_rd_out[1214] + PIN rw0_rd_out[1215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 218.907 129.961 218.925 130.015 ; + END + END rw0_rd_out[1215] + PIN rw0_rd_out[1216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.087 129.961 219.105 130.015 ; + END + END rw0_rd_out[1216] + PIN rw0_rd_out[1217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.267 129.961 219.285 130.015 ; + END + END rw0_rd_out[1217] + PIN rw0_rd_out[1218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.447 129.961 219.465 130.015 ; + END + END rw0_rd_out[1218] + PIN rw0_rd_out[1219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.627 129.961 219.645 130.015 ; + END + END rw0_rd_out[1219] + PIN rw0_rd_out[1220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.807 129.961 219.825 130.015 ; + END + END rw0_rd_out[1220] + PIN rw0_rd_out[1221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 219.987 129.961 220.005 130.015 ; + END + END rw0_rd_out[1221] + PIN rw0_rd_out[1222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.167 129.961 220.185 130.015 ; + END + END rw0_rd_out[1222] + PIN rw0_rd_out[1223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.347 129.961 220.365 130.015 ; + END + END rw0_rd_out[1223] + PIN rw0_rd_out[1224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.527 129.961 220.545 130.015 ; + END + END rw0_rd_out[1224] + PIN rw0_rd_out[1225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.707 129.961 220.725 130.015 ; + END + END rw0_rd_out[1225] + PIN rw0_rd_out[1226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 220.887 129.961 220.905 130.015 ; + END + END rw0_rd_out[1226] + PIN rw0_rd_out[1227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.067 129.961 221.085 130.015 ; + END + END rw0_rd_out[1227] + PIN rw0_rd_out[1228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.247 129.961 221.265 130.015 ; + END + END rw0_rd_out[1228] + PIN rw0_rd_out[1229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.427 129.961 221.445 130.015 ; + END + END rw0_rd_out[1229] + PIN rw0_rd_out[1230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.607 129.961 221.625 130.015 ; + END + END rw0_rd_out[1230] + PIN rw0_rd_out[1231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.787 129.961 221.805 130.015 ; + END + END rw0_rd_out[1231] + PIN rw0_rd_out[1232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 221.967 129.961 221.985 130.015 ; + END + END rw0_rd_out[1232] + PIN rw0_rd_out[1233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.147 129.961 222.165 130.015 ; + END + END rw0_rd_out[1233] + PIN rw0_rd_out[1234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.327 129.961 222.345 130.015 ; + END + END rw0_rd_out[1234] + PIN rw0_rd_out[1235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.507 129.961 222.525 130.015 ; + END + END rw0_rd_out[1235] + PIN rw0_rd_out[1236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.687 129.961 222.705 130.015 ; + END + END rw0_rd_out[1236] + PIN rw0_rd_out[1237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 222.867 129.961 222.885 130.015 ; + END + END rw0_rd_out[1237] + PIN rw0_rd_out[1238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.047 129.961 223.065 130.015 ; + END + END rw0_rd_out[1238] + PIN rw0_rd_out[1239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.227 129.961 223.245 130.015 ; + END + END rw0_rd_out[1239] + PIN rw0_rd_out[1240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.407 129.961 223.425 130.015 ; + END + END rw0_rd_out[1240] + PIN rw0_rd_out[1241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.587 129.961 223.605 130.015 ; + END + END rw0_rd_out[1241] + PIN rw0_rd_out[1242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.767 129.961 223.785 130.015 ; + END + END rw0_rd_out[1242] + PIN rw0_rd_out[1243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 223.947 129.961 223.965 130.015 ; + END + END rw0_rd_out[1243] + PIN rw0_rd_out[1244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.127 129.961 224.145 130.015 ; + END + END rw0_rd_out[1244] + PIN rw0_rd_out[1245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.307 129.961 224.325 130.015 ; + END + END rw0_rd_out[1245] + PIN rw0_rd_out[1246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.487 129.961 224.505 130.015 ; + END + END rw0_rd_out[1246] + PIN rw0_rd_out[1247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.667 129.961 224.685 130.015 ; + END + END rw0_rd_out[1247] + PIN rw0_rd_out[1248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 224.847 129.961 224.865 130.015 ; + END + END rw0_rd_out[1248] + PIN rw0_rd_out[1249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.027 129.961 225.045 130.015 ; + END + END rw0_rd_out[1249] + PIN rw0_rd_out[1250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.207 129.961 225.225 130.015 ; + END + END rw0_rd_out[1250] + PIN rw0_rd_out[1251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.387 129.961 225.405 130.015 ; + END + END rw0_rd_out[1251] + PIN rw0_rd_out[1252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.567 129.961 225.585 130.015 ; + END + END rw0_rd_out[1252] + PIN rw0_rd_out[1253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.747 129.961 225.765 130.015 ; + END + END rw0_rd_out[1253] + PIN rw0_rd_out[1254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 225.927 129.961 225.945 130.015 ; + END + END rw0_rd_out[1254] + PIN rw0_rd_out[1255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.107 129.961 226.125 130.015 ; + END + END rw0_rd_out[1255] + PIN rw0_rd_out[1256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.287 129.961 226.305 130.015 ; + END + END rw0_rd_out[1256] + PIN rw0_rd_out[1257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.467 129.961 226.485 130.015 ; + END + END rw0_rd_out[1257] + PIN rw0_rd_out[1258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.647 129.961 226.665 130.015 ; + END + END rw0_rd_out[1258] + PIN rw0_rd_out[1259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 226.827 129.961 226.845 130.015 ; + END + END rw0_rd_out[1259] + PIN rw0_rd_out[1260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.007 129.961 227.025 130.015 ; + END + END rw0_rd_out[1260] + PIN rw0_rd_out[1261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.187 129.961 227.205 130.015 ; + END + END rw0_rd_out[1261] + PIN rw0_rd_out[1262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.367 129.961 227.385 130.015 ; + END + END rw0_rd_out[1262] + PIN rw0_rd_out[1263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.547 129.961 227.565 130.015 ; + END + END rw0_rd_out[1263] + PIN rw0_rd_out[1264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.727 129.961 227.745 130.015 ; + END + END rw0_rd_out[1264] + PIN rw0_rd_out[1265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 227.907 129.961 227.925 130.015 ; + END + END rw0_rd_out[1265] + PIN rw0_rd_out[1266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.087 129.961 228.105 130.015 ; + END + END rw0_rd_out[1266] + PIN rw0_rd_out[1267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.267 129.961 228.285 130.015 ; + END + END rw0_rd_out[1267] + PIN rw0_rd_out[1268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.447 129.961 228.465 130.015 ; + END + END rw0_rd_out[1268] + PIN rw0_rd_out[1269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.627 129.961 228.645 130.015 ; + END + END rw0_rd_out[1269] + PIN rw0_rd_out[1270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.807 129.961 228.825 130.015 ; + END + END rw0_rd_out[1270] + PIN rw0_rd_out[1271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 228.987 129.961 229.005 130.015 ; + END + END rw0_rd_out[1271] + PIN rw0_rd_out[1272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.167 129.961 229.185 130.015 ; + END + END rw0_rd_out[1272] + PIN rw0_rd_out[1273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.347 129.961 229.365 130.015 ; + END + END rw0_rd_out[1273] + PIN rw0_rd_out[1274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.527 129.961 229.545 130.015 ; + END + END rw0_rd_out[1274] + PIN rw0_rd_out[1275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.707 129.961 229.725 130.015 ; + END + END rw0_rd_out[1275] + PIN rw0_rd_out[1276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 229.887 129.961 229.905 130.015 ; + END + END rw0_rd_out[1276] + PIN rw0_rd_out[1277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.067 129.961 230.085 130.015 ; + END + END rw0_rd_out[1277] + PIN rw0_rd_out[1278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.247 129.961 230.265 130.015 ; + END + END rw0_rd_out[1278] + PIN rw0_rd_out[1279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.427 129.961 230.445 130.015 ; + END + END rw0_rd_out[1279] + PIN rw0_rd_out[1280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.607 129.961 230.625 130.015 ; + END + END rw0_rd_out[1280] + PIN rw0_rd_out[1281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.787 129.961 230.805 130.015 ; + END + END rw0_rd_out[1281] + PIN rw0_rd_out[1282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 230.967 129.961 230.985 130.015 ; + END + END rw0_rd_out[1282] + PIN rw0_rd_out[1283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.147 129.961 231.165 130.015 ; + END + END rw0_rd_out[1283] + PIN rw0_rd_out[1284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.327 129.961 231.345 130.015 ; + END + END rw0_rd_out[1284] + PIN rw0_rd_out[1285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.507 129.961 231.525 130.015 ; + END + END rw0_rd_out[1285] + PIN rw0_rd_out[1286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.687 129.961 231.705 130.015 ; + END + END rw0_rd_out[1286] + PIN rw0_rd_out[1287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 231.867 129.961 231.885 130.015 ; + END + END rw0_rd_out[1287] + PIN rw0_rd_out[1288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.047 129.961 232.065 130.015 ; + END + END rw0_rd_out[1288] + PIN rw0_rd_out[1289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.227 129.961 232.245 130.015 ; + END + END rw0_rd_out[1289] + PIN rw0_rd_out[1290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.407 129.961 232.425 130.015 ; + END + END rw0_rd_out[1290] + PIN rw0_rd_out[1291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.587 129.961 232.605 130.015 ; + END + END rw0_rd_out[1291] + PIN rw0_rd_out[1292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.767 129.961 232.785 130.015 ; + END + END rw0_rd_out[1292] + PIN rw0_rd_out[1293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 232.947 129.961 232.965 130.015 ; + END + END rw0_rd_out[1293] + PIN rw0_rd_out[1294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.127 129.961 233.145 130.015 ; + END + END rw0_rd_out[1294] + PIN rw0_rd_out[1295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.307 129.961 233.325 130.015 ; + END + END rw0_rd_out[1295] + PIN rw0_rd_out[1296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.487 129.961 233.505 130.015 ; + END + END rw0_rd_out[1296] + PIN rw0_rd_out[1297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.667 129.961 233.685 130.015 ; + END + END rw0_rd_out[1297] + PIN rw0_rd_out[1298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 233.847 129.961 233.865 130.015 ; + END + END rw0_rd_out[1298] + PIN rw0_rd_out[1299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.027 129.961 234.045 130.015 ; + END + END rw0_rd_out[1299] + PIN rw0_rd_out[1300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.207 129.961 234.225 130.015 ; + END + END rw0_rd_out[1300] + PIN rw0_rd_out[1301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.387 129.961 234.405 130.015 ; + END + END rw0_rd_out[1301] + PIN rw0_rd_out[1302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.567 129.961 234.585 130.015 ; + END + END rw0_rd_out[1302] + PIN rw0_rd_out[1303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.747 129.961 234.765 130.015 ; + END + END rw0_rd_out[1303] + PIN rw0_rd_out[1304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 234.927 129.961 234.945 130.015 ; + END + END rw0_rd_out[1304] + PIN rw0_rd_out[1305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.107 129.961 235.125 130.015 ; + END + END rw0_rd_out[1305] + PIN rw0_rd_out[1306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.287 129.961 235.305 130.015 ; + END + END rw0_rd_out[1306] + PIN rw0_rd_out[1307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.467 129.961 235.485 130.015 ; + END + END rw0_rd_out[1307] + PIN rw0_rd_out[1308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.647 129.961 235.665 130.015 ; + END + END rw0_rd_out[1308] + PIN rw0_rd_out[1309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 235.827 129.961 235.845 130.015 ; + END + END rw0_rd_out[1309] + PIN rw0_rd_out[1310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.007 129.961 236.025 130.015 ; + END + END rw0_rd_out[1310] + PIN rw0_rd_out[1311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.187 129.961 236.205 130.015 ; + END + END rw0_rd_out[1311] + PIN rw0_rd_out[1312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.367 129.961 236.385 130.015 ; + END + END rw0_rd_out[1312] + PIN rw0_rd_out[1313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.547 129.961 236.565 130.015 ; + END + END rw0_rd_out[1313] + PIN rw0_rd_out[1314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.727 129.961 236.745 130.015 ; + END + END rw0_rd_out[1314] + PIN rw0_rd_out[1315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 236.907 129.961 236.925 130.015 ; + END + END rw0_rd_out[1315] + PIN rw0_rd_out[1316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.087 129.961 237.105 130.015 ; + END + END rw0_rd_out[1316] + PIN rw0_rd_out[1317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.267 129.961 237.285 130.015 ; + END + END rw0_rd_out[1317] + PIN rw0_rd_out[1318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.447 129.961 237.465 130.015 ; + END + END rw0_rd_out[1318] + PIN rw0_rd_out[1319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.627 129.961 237.645 130.015 ; + END + END rw0_rd_out[1319] + PIN rw0_rd_out[1320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.807 129.961 237.825 130.015 ; + END + END rw0_rd_out[1320] + PIN rw0_rd_out[1321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 237.987 129.961 238.005 130.015 ; + END + END rw0_rd_out[1321] + PIN rw0_rd_out[1322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.167 129.961 238.185 130.015 ; + END + END rw0_rd_out[1322] + PIN rw0_rd_out[1323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.347 129.961 238.365 130.015 ; + END + END rw0_rd_out[1323] + PIN rw0_rd_out[1324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.527 129.961 238.545 130.015 ; + END + END rw0_rd_out[1324] + PIN rw0_rd_out[1325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.707 129.961 238.725 130.015 ; + END + END rw0_rd_out[1325] + PIN rw0_rd_out[1326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 238.887 129.961 238.905 130.015 ; + END + END rw0_rd_out[1326] + PIN rw0_rd_out[1327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.067 129.961 239.085 130.015 ; + END + END rw0_rd_out[1327] + PIN rw0_rd_out[1328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.247 129.961 239.265 130.015 ; + END + END rw0_rd_out[1328] + PIN rw0_rd_out[1329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.427 129.961 239.445 130.015 ; + END + END rw0_rd_out[1329] + PIN rw0_rd_out[1330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.607 129.961 239.625 130.015 ; + END + END rw0_rd_out[1330] + PIN rw0_rd_out[1331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.787 129.961 239.805 130.015 ; + END + END rw0_rd_out[1331] + PIN rw0_rd_out[1332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 239.967 129.961 239.985 130.015 ; + END + END rw0_rd_out[1332] + PIN rw0_rd_out[1333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.147 129.961 240.165 130.015 ; + END + END rw0_rd_out[1333] + PIN rw0_rd_out[1334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.327 129.961 240.345 130.015 ; + END + END rw0_rd_out[1334] + PIN rw0_rd_out[1335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.507 129.961 240.525 130.015 ; + END + END rw0_rd_out[1335] + PIN rw0_rd_out[1336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.687 129.961 240.705 130.015 ; + END + END rw0_rd_out[1336] + PIN rw0_rd_out[1337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 240.867 129.961 240.885 130.015 ; + END + END rw0_rd_out[1337] + PIN rw0_rd_out[1338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.047 129.961 241.065 130.015 ; + END + END rw0_rd_out[1338] + PIN rw0_rd_out[1339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.227 129.961 241.245 130.015 ; + END + END rw0_rd_out[1339] + PIN rw0_rd_out[1340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.407 129.961 241.425 130.015 ; + END + END rw0_rd_out[1340] + PIN rw0_rd_out[1341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.587 129.961 241.605 130.015 ; + END + END rw0_rd_out[1341] + PIN rw0_rd_out[1342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.767 129.961 241.785 130.015 ; + END + END rw0_rd_out[1342] + PIN rw0_rd_out[1343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 241.947 129.961 241.965 130.015 ; + END + END rw0_rd_out[1343] + PIN rw0_rd_out[1344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.127 129.961 242.145 130.015 ; + END + END rw0_rd_out[1344] + PIN rw0_rd_out[1345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.307 129.961 242.325 130.015 ; + END + END rw0_rd_out[1345] + PIN rw0_rd_out[1346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.487 129.961 242.505 130.015 ; + END + END rw0_rd_out[1346] + PIN rw0_rd_out[1347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.667 129.961 242.685 130.015 ; + END + END rw0_rd_out[1347] + PIN rw0_rd_out[1348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 242.847 129.961 242.865 130.015 ; + END + END rw0_rd_out[1348] + PIN rw0_rd_out[1349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.027 129.961 243.045 130.015 ; + END + END rw0_rd_out[1349] + PIN rw0_rd_out[1350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.207 129.961 243.225 130.015 ; + END + END rw0_rd_out[1350] + PIN rw0_rd_out[1351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.387 129.961 243.405 130.015 ; + END + END rw0_rd_out[1351] + PIN rw0_rd_out[1352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.567 129.961 243.585 130.015 ; + END + END rw0_rd_out[1352] + PIN rw0_rd_out[1353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.747 129.961 243.765 130.015 ; + END + END rw0_rd_out[1353] + PIN rw0_rd_out[1354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 243.927 129.961 243.945 130.015 ; + END + END rw0_rd_out[1354] + PIN rw0_rd_out[1355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.107 129.961 244.125 130.015 ; + END + END rw0_rd_out[1355] + PIN rw0_rd_out[1356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.287 129.961 244.305 130.015 ; + END + END rw0_rd_out[1356] + PIN rw0_rd_out[1357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.467 129.961 244.485 130.015 ; + END + END rw0_rd_out[1357] + PIN rw0_rd_out[1358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.647 129.961 244.665 130.015 ; + END + END rw0_rd_out[1358] + PIN rw0_rd_out[1359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 244.827 129.961 244.845 130.015 ; + END + END rw0_rd_out[1359] + PIN rw0_rd_out[1360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.007 129.961 245.025 130.015 ; + END + END rw0_rd_out[1360] + PIN rw0_rd_out[1361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.187 129.961 245.205 130.015 ; + END + END rw0_rd_out[1361] + PIN rw0_rd_out[1362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.367 129.961 245.385 130.015 ; + END + END rw0_rd_out[1362] + PIN rw0_rd_out[1363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.547 129.961 245.565 130.015 ; + END + END rw0_rd_out[1363] + PIN rw0_rd_out[1364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.727 129.961 245.745 130.015 ; + END + END rw0_rd_out[1364] + PIN rw0_rd_out[1365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 245.907 129.961 245.925 130.015 ; + END + END rw0_rd_out[1365] + PIN rw0_rd_out[1366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.087 129.961 246.105 130.015 ; + END + END rw0_rd_out[1366] + PIN rw0_rd_out[1367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.267 129.961 246.285 130.015 ; + END + END rw0_rd_out[1367] + PIN rw0_rd_out[1368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.447 129.961 246.465 130.015 ; + END + END rw0_rd_out[1368] + PIN rw0_rd_out[1369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.627 129.961 246.645 130.015 ; + END + END rw0_rd_out[1369] + PIN rw0_rd_out[1370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.807 129.961 246.825 130.015 ; + END + END rw0_rd_out[1370] + PIN rw0_rd_out[1371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 246.987 129.961 247.005 130.015 ; + END + END rw0_rd_out[1371] + PIN rw0_rd_out[1372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.167 129.961 247.185 130.015 ; + END + END rw0_rd_out[1372] + PIN rw0_rd_out[1373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.347 129.961 247.365 130.015 ; + END + END rw0_rd_out[1373] + PIN rw0_rd_out[1374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.527 129.961 247.545 130.015 ; + END + END rw0_rd_out[1374] + PIN rw0_rd_out[1375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.707 129.961 247.725 130.015 ; + END + END rw0_rd_out[1375] + PIN rw0_rd_out[1376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 247.887 129.961 247.905 130.015 ; + END + END rw0_rd_out[1376] + PIN rw0_rd_out[1377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.067 129.961 248.085 130.015 ; + END + END rw0_rd_out[1377] + PIN rw0_rd_out[1378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.247 129.961 248.265 130.015 ; + END + END rw0_rd_out[1378] + PIN rw0_rd_out[1379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.427 129.961 248.445 130.015 ; + END + END rw0_rd_out[1379] + PIN rw0_rd_out[1380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.607 129.961 248.625 130.015 ; + END + END rw0_rd_out[1380] + PIN rw0_rd_out[1381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.787 129.961 248.805 130.015 ; + END + END rw0_rd_out[1381] + PIN rw0_rd_out[1382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 248.967 129.961 248.985 130.015 ; + END + END rw0_rd_out[1382] + PIN rw0_rd_out[1383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.147 129.961 249.165 130.015 ; + END + END rw0_rd_out[1383] + PIN rw0_rd_out[1384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.327 129.961 249.345 130.015 ; + END + END rw0_rd_out[1384] + PIN rw0_rd_out[1385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.507 129.961 249.525 130.015 ; + END + END rw0_rd_out[1385] + PIN rw0_rd_out[1386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.687 129.961 249.705 130.015 ; + END + END rw0_rd_out[1386] + PIN rw0_rd_out[1387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 249.867 129.961 249.885 130.015 ; + END + END rw0_rd_out[1387] + PIN rw0_rd_out[1388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.047 129.961 250.065 130.015 ; + END + END rw0_rd_out[1388] + PIN rw0_rd_out[1389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.227 129.961 250.245 130.015 ; + END + END rw0_rd_out[1389] + PIN rw0_rd_out[1390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.407 129.961 250.425 130.015 ; + END + END rw0_rd_out[1390] + PIN rw0_rd_out[1391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.587 129.961 250.605 130.015 ; + END + END rw0_rd_out[1391] + PIN rw0_rd_out[1392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.767 129.961 250.785 130.015 ; + END + END rw0_rd_out[1392] + PIN rw0_rd_out[1393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 250.947 129.961 250.965 130.015 ; + END + END rw0_rd_out[1393] + PIN rw0_rd_out[1394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.127 129.961 251.145 130.015 ; + END + END rw0_rd_out[1394] + PIN rw0_rd_out[1395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.307 129.961 251.325 130.015 ; + END + END rw0_rd_out[1395] + PIN rw0_rd_out[1396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.487 129.961 251.505 130.015 ; + END + END rw0_rd_out[1396] + PIN rw0_rd_out[1397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.667 129.961 251.685 130.015 ; + END + END rw0_rd_out[1397] + PIN rw0_rd_out[1398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 251.847 129.961 251.865 130.015 ; + END + END rw0_rd_out[1398] + PIN rw0_rd_out[1399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.027 129.961 252.045 130.015 ; + END + END rw0_rd_out[1399] + PIN rw0_rd_out[1400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.207 129.961 252.225 130.015 ; + END + END rw0_rd_out[1400] + PIN rw0_rd_out[1401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.387 129.961 252.405 130.015 ; + END + END rw0_rd_out[1401] + PIN rw0_rd_out[1402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.567 129.961 252.585 130.015 ; + END + END rw0_rd_out[1402] + PIN rw0_rd_out[1403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.747 129.961 252.765 130.015 ; + END + END rw0_rd_out[1403] + PIN rw0_rd_out[1404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 252.927 129.961 252.945 130.015 ; + END + END rw0_rd_out[1404] + PIN rw0_rd_out[1405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.107 129.961 253.125 130.015 ; + END + END rw0_rd_out[1405] + PIN rw0_rd_out[1406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.287 129.961 253.305 130.015 ; + END + END rw0_rd_out[1406] + PIN rw0_rd_out[1407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.467 129.961 253.485 130.015 ; + END + END rw0_rd_out[1407] + PIN rw0_rd_out[1408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.647 129.961 253.665 130.015 ; + END + END rw0_rd_out[1408] + PIN rw0_rd_out[1409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 253.827 129.961 253.845 130.015 ; + END + END rw0_rd_out[1409] + PIN rw0_rd_out[1410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.007 129.961 254.025 130.015 ; + END + END rw0_rd_out[1410] + PIN rw0_rd_out[1411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.187 129.961 254.205 130.015 ; + END + END rw0_rd_out[1411] + PIN rw0_rd_out[1412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.367 129.961 254.385 130.015 ; + END + END rw0_rd_out[1412] + PIN rw0_rd_out[1413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.547 129.961 254.565 130.015 ; + END + END rw0_rd_out[1413] + PIN rw0_rd_out[1414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.727 129.961 254.745 130.015 ; + END + END rw0_rd_out[1414] + PIN rw0_rd_out[1415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 254.907 129.961 254.925 130.015 ; + END + END rw0_rd_out[1415] + PIN rw0_rd_out[1416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.087 129.961 255.105 130.015 ; + END + END rw0_rd_out[1416] + PIN rw0_rd_out[1417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.267 129.961 255.285 130.015 ; + END + END rw0_rd_out[1417] + PIN rw0_rd_out[1418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.447 129.961 255.465 130.015 ; + END + END rw0_rd_out[1418] + PIN rw0_rd_out[1419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.627 129.961 255.645 130.015 ; + END + END rw0_rd_out[1419] + PIN rw0_rd_out[1420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.807 129.961 255.825 130.015 ; + END + END rw0_rd_out[1420] + PIN rw0_rd_out[1421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 255.987 129.961 256.005 130.015 ; + END + END rw0_rd_out[1421] + PIN rw0_rd_out[1422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.167 129.961 256.185 130.015 ; + END + END rw0_rd_out[1422] + PIN rw0_rd_out[1423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.347 129.961 256.365 130.015 ; + END + END rw0_rd_out[1423] + PIN rw0_rd_out[1424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.527 129.961 256.545 130.015 ; + END + END rw0_rd_out[1424] + PIN rw0_rd_out[1425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.707 129.961 256.725 130.015 ; + END + END rw0_rd_out[1425] + PIN rw0_rd_out[1426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 256.887 129.961 256.905 130.015 ; + END + END rw0_rd_out[1426] + PIN rw0_rd_out[1427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.067 129.961 257.085 130.015 ; + END + END rw0_rd_out[1427] + PIN rw0_rd_out[1428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.247 129.961 257.265 130.015 ; + END + END rw0_rd_out[1428] + PIN rw0_rd_out[1429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.427 129.961 257.445 130.015 ; + END + END rw0_rd_out[1429] + PIN rw0_rd_out[1430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.607 129.961 257.625 130.015 ; + END + END rw0_rd_out[1430] + PIN rw0_rd_out[1431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.787 129.961 257.805 130.015 ; + END + END rw0_rd_out[1431] + PIN rw0_rd_out[1432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 257.967 129.961 257.985 130.015 ; + END + END rw0_rd_out[1432] + PIN rw0_rd_out[1433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.147 129.961 258.165 130.015 ; + END + END rw0_rd_out[1433] + PIN rw0_rd_out[1434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.327 129.961 258.345 130.015 ; + END + END rw0_rd_out[1434] + PIN rw0_rd_out[1435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.507 129.961 258.525 130.015 ; + END + END rw0_rd_out[1435] + PIN rw0_rd_out[1436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.687 129.961 258.705 130.015 ; + END + END rw0_rd_out[1436] + PIN rw0_rd_out[1437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 258.867 129.961 258.885 130.015 ; + END + END rw0_rd_out[1437] + PIN rw0_rd_out[1438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.047 129.961 259.065 130.015 ; + END + END rw0_rd_out[1438] + PIN rw0_rd_out[1439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.227 129.961 259.245 130.015 ; + END + END rw0_rd_out[1439] + PIN rw0_rd_out[1440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.407 129.961 259.425 130.015 ; + END + END rw0_rd_out[1440] + PIN rw0_rd_out[1441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.587 129.961 259.605 130.015 ; + END + END rw0_rd_out[1441] + PIN rw0_rd_out[1442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.767 129.961 259.785 130.015 ; + END + END rw0_rd_out[1442] + PIN rw0_rd_out[1443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 259.947 129.961 259.965 130.015 ; + END + END rw0_rd_out[1443] + PIN rw0_rd_out[1444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.127 129.961 260.145 130.015 ; + END + END rw0_rd_out[1444] + PIN rw0_rd_out[1445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.307 129.961 260.325 130.015 ; + END + END rw0_rd_out[1445] + PIN rw0_rd_out[1446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.487 129.961 260.505 130.015 ; + END + END rw0_rd_out[1446] + PIN rw0_rd_out[1447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.667 129.961 260.685 130.015 ; + END + END rw0_rd_out[1447] + PIN rw0_rd_out[1448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 260.847 129.961 260.865 130.015 ; + END + END rw0_rd_out[1448] + PIN rw0_rd_out[1449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.027 129.961 261.045 130.015 ; + END + END rw0_rd_out[1449] + PIN rw0_rd_out[1450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.207 129.961 261.225 130.015 ; + END + END rw0_rd_out[1450] + PIN rw0_rd_out[1451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.387 129.961 261.405 130.015 ; + END + END rw0_rd_out[1451] + PIN rw0_rd_out[1452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.567 129.961 261.585 130.015 ; + END + END rw0_rd_out[1452] + PIN rw0_rd_out[1453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.747 129.961 261.765 130.015 ; + END + END rw0_rd_out[1453] + PIN rw0_rd_out[1454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 261.927 129.961 261.945 130.015 ; + END + END rw0_rd_out[1454] + PIN rw0_rd_out[1455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.107 129.961 262.125 130.015 ; + END + END rw0_rd_out[1455] + PIN rw0_rd_out[1456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.287 129.961 262.305 130.015 ; + END + END rw0_rd_out[1456] + PIN rw0_rd_out[1457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.467 129.961 262.485 130.015 ; + END + END rw0_rd_out[1457] + PIN rw0_rd_out[1458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.647 129.961 262.665 130.015 ; + END + END rw0_rd_out[1458] + PIN rw0_rd_out[1459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 262.827 129.961 262.845 130.015 ; + END + END rw0_rd_out[1459] + PIN rw0_rd_out[1460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.007 129.961 263.025 130.015 ; + END + END rw0_rd_out[1460] + PIN rw0_rd_out[1461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.187 129.961 263.205 130.015 ; + END + END rw0_rd_out[1461] + PIN rw0_rd_out[1462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.367 129.961 263.385 130.015 ; + END + END rw0_rd_out[1462] + PIN rw0_rd_out[1463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.547 129.961 263.565 130.015 ; + END + END rw0_rd_out[1463] + PIN rw0_rd_out[1464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.727 129.961 263.745 130.015 ; + END + END rw0_rd_out[1464] + PIN rw0_rd_out[1465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 263.907 129.961 263.925 130.015 ; + END + END rw0_rd_out[1465] + PIN rw0_rd_out[1466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.087 129.961 264.105 130.015 ; + END + END rw0_rd_out[1466] + PIN rw0_rd_out[1467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.267 129.961 264.285 130.015 ; + END + END rw0_rd_out[1467] + PIN rw0_rd_out[1468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.447 129.961 264.465 130.015 ; + END + END rw0_rd_out[1468] + PIN rw0_rd_out[1469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.627 129.961 264.645 130.015 ; + END + END rw0_rd_out[1469] + PIN rw0_rd_out[1470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.807 129.961 264.825 130.015 ; + END + END rw0_rd_out[1470] + PIN rw0_rd_out[1471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 264.987 129.961 265.005 130.015 ; + END + END rw0_rd_out[1471] + PIN rw0_rd_out[1472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.167 129.961 265.185 130.015 ; + END + END rw0_rd_out[1472] + PIN rw0_rd_out[1473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.347 129.961 265.365 130.015 ; + END + END rw0_rd_out[1473] + PIN rw0_rd_out[1474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.527 129.961 265.545 130.015 ; + END + END rw0_rd_out[1474] + PIN rw0_rd_out[1475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.707 129.961 265.725 130.015 ; + END + END rw0_rd_out[1475] + PIN rw0_rd_out[1476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 265.887 129.961 265.905 130.015 ; + END + END rw0_rd_out[1476] + PIN rw0_rd_out[1477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.067 129.961 266.085 130.015 ; + END + END rw0_rd_out[1477] + PIN rw0_rd_out[1478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.247 129.961 266.265 130.015 ; + END + END rw0_rd_out[1478] + PIN rw0_rd_out[1479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.427 129.961 266.445 130.015 ; + END + END rw0_rd_out[1479] + PIN rw0_rd_out[1480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.607 129.961 266.625 130.015 ; + END + END rw0_rd_out[1480] + PIN rw0_rd_out[1481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.787 129.961 266.805 130.015 ; + END + END rw0_rd_out[1481] + PIN rw0_rd_out[1482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 266.967 129.961 266.985 130.015 ; + END + END rw0_rd_out[1482] + PIN rw0_rd_out[1483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.147 129.961 267.165 130.015 ; + END + END rw0_rd_out[1483] + PIN rw0_rd_out[1484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.327 129.961 267.345 130.015 ; + END + END rw0_rd_out[1484] + PIN rw0_rd_out[1485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.507 129.961 267.525 130.015 ; + END + END rw0_rd_out[1485] + PIN rw0_rd_out[1486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.687 129.961 267.705 130.015 ; + END + END rw0_rd_out[1486] + PIN rw0_rd_out[1487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 267.867 129.961 267.885 130.015 ; + END + END rw0_rd_out[1487] + PIN rw0_rd_out[1488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.047 129.961 268.065 130.015 ; + END + END rw0_rd_out[1488] + PIN rw0_rd_out[1489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.227 129.961 268.245 130.015 ; + END + END rw0_rd_out[1489] + PIN rw0_rd_out[1490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.407 129.961 268.425 130.015 ; + END + END rw0_rd_out[1490] + PIN rw0_rd_out[1491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.587 129.961 268.605 130.015 ; + END + END rw0_rd_out[1491] + PIN rw0_rd_out[1492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.767 129.961 268.785 130.015 ; + END + END rw0_rd_out[1492] + PIN rw0_rd_out[1493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 268.947 129.961 268.965 130.015 ; + END + END rw0_rd_out[1493] + PIN rw0_rd_out[1494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.127 129.961 269.145 130.015 ; + END + END rw0_rd_out[1494] + PIN rw0_rd_out[1495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.307 129.961 269.325 130.015 ; + END + END rw0_rd_out[1495] + PIN rw0_rd_out[1496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.487 129.961 269.505 130.015 ; + END + END rw0_rd_out[1496] + PIN rw0_rd_out[1497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.667 129.961 269.685 130.015 ; + END + END rw0_rd_out[1497] + PIN rw0_rd_out[1498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 269.847 129.961 269.865 130.015 ; + END + END rw0_rd_out[1498] + PIN rw0_rd_out[1499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.027 129.961 270.045 130.015 ; + END + END rw0_rd_out[1499] + PIN rw0_rd_out[1500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.207 129.961 270.225 130.015 ; + END + END rw0_rd_out[1500] + PIN rw0_rd_out[1501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.387 129.961 270.405 130.015 ; + END + END rw0_rd_out[1501] + PIN rw0_rd_out[1502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.567 129.961 270.585 130.015 ; + END + END rw0_rd_out[1502] + PIN rw0_rd_out[1503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.747 129.961 270.765 130.015 ; + END + END rw0_rd_out[1503] + PIN rw0_rd_out[1504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 270.927 129.961 270.945 130.015 ; + END + END rw0_rd_out[1504] + PIN rw0_rd_out[1505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.107 129.961 271.125 130.015 ; + END + END rw0_rd_out[1505] + PIN rw0_rd_out[1506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.287 129.961 271.305 130.015 ; + END + END rw0_rd_out[1506] + PIN rw0_rd_out[1507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.467 129.961 271.485 130.015 ; + END + END rw0_rd_out[1507] + PIN rw0_rd_out[1508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.647 129.961 271.665 130.015 ; + END + END rw0_rd_out[1508] + PIN rw0_rd_out[1509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 271.827 129.961 271.845 130.015 ; + END + END rw0_rd_out[1509] + PIN rw0_rd_out[1510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.007 129.961 272.025 130.015 ; + END + END rw0_rd_out[1510] + PIN rw0_rd_out[1511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.187 129.961 272.205 130.015 ; + END + END rw0_rd_out[1511] + PIN rw0_rd_out[1512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.367 129.961 272.385 130.015 ; + END + END rw0_rd_out[1512] + PIN rw0_rd_out[1513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.547 129.961 272.565 130.015 ; + END + END rw0_rd_out[1513] + PIN rw0_rd_out[1514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.727 129.961 272.745 130.015 ; + END + END rw0_rd_out[1514] + PIN rw0_rd_out[1515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 272.907 129.961 272.925 130.015 ; + END + END rw0_rd_out[1515] + PIN rw0_rd_out[1516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.087 129.961 273.105 130.015 ; + END + END rw0_rd_out[1516] + PIN rw0_rd_out[1517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.267 129.961 273.285 130.015 ; + END + END rw0_rd_out[1517] + PIN rw0_rd_out[1518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.447 129.961 273.465 130.015 ; + END + END rw0_rd_out[1518] + PIN rw0_rd_out[1519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.627 129.961 273.645 130.015 ; + END + END rw0_rd_out[1519] + PIN rw0_rd_out[1520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.807 129.961 273.825 130.015 ; + END + END rw0_rd_out[1520] + PIN rw0_rd_out[1521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 273.987 129.961 274.005 130.015 ; + END + END rw0_rd_out[1521] + PIN rw0_rd_out[1522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.167 129.961 274.185 130.015 ; + END + END rw0_rd_out[1522] + PIN rw0_rd_out[1523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.347 129.961 274.365 130.015 ; + END + END rw0_rd_out[1523] + PIN rw0_rd_out[1524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.527 129.961 274.545 130.015 ; + END + END rw0_rd_out[1524] + PIN rw0_rd_out[1525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.707 129.961 274.725 130.015 ; + END + END rw0_rd_out[1525] + PIN rw0_rd_out[1526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 274.887 129.961 274.905 130.015 ; + END + END rw0_rd_out[1526] + PIN rw0_rd_out[1527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.067 129.961 275.085 130.015 ; + END + END rw0_rd_out[1527] + PIN rw0_rd_out[1528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.247 129.961 275.265 130.015 ; + END + END rw0_rd_out[1528] + PIN rw0_rd_out[1529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.427 129.961 275.445 130.015 ; + END + END rw0_rd_out[1529] + PIN rw0_rd_out[1530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.607 129.961 275.625 130.015 ; + END + END rw0_rd_out[1530] + PIN rw0_rd_out[1531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.787 129.961 275.805 130.015 ; + END + END rw0_rd_out[1531] + PIN rw0_rd_out[1532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 275.967 129.961 275.985 130.015 ; + END + END rw0_rd_out[1532] + PIN rw0_rd_out[1533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.147 129.961 276.165 130.015 ; + END + END rw0_rd_out[1533] + PIN rw0_rd_out[1534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.327 129.961 276.345 130.015 ; + END + END rw0_rd_out[1534] + PIN rw0_rd_out[1535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.507 129.961 276.525 130.015 ; + END + END rw0_rd_out[1535] + PIN rw0_rd_out[1536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.687 129.961 276.705 130.015 ; + END + END rw0_rd_out[1536] + PIN rw0_rd_out[1537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 276.867 129.961 276.885 130.015 ; + END + END rw0_rd_out[1537] + PIN rw0_rd_out[1538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.047 129.961 277.065 130.015 ; + END + END rw0_rd_out[1538] + PIN rw0_rd_out[1539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.227 129.961 277.245 130.015 ; + END + END rw0_rd_out[1539] + PIN rw0_rd_out[1540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.407 129.961 277.425 130.015 ; + END + END rw0_rd_out[1540] + PIN rw0_rd_out[1541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.587 129.961 277.605 130.015 ; + END + END rw0_rd_out[1541] + PIN rw0_rd_out[1542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.767 129.961 277.785 130.015 ; + END + END rw0_rd_out[1542] + PIN rw0_rd_out[1543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 277.947 129.961 277.965 130.015 ; + END + END rw0_rd_out[1543] + PIN rw0_rd_out[1544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.127 129.961 278.145 130.015 ; + END + END rw0_rd_out[1544] + PIN rw0_rd_out[1545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.307 129.961 278.325 130.015 ; + END + END rw0_rd_out[1545] + PIN rw0_rd_out[1546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.487 129.961 278.505 130.015 ; + END + END rw0_rd_out[1546] + PIN rw0_rd_out[1547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.667 129.961 278.685 130.015 ; + END + END rw0_rd_out[1547] + PIN rw0_rd_out[1548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 278.847 129.961 278.865 130.015 ; + END + END rw0_rd_out[1548] + PIN rw0_rd_out[1549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.027 129.961 279.045 130.015 ; + END + END rw0_rd_out[1549] + PIN rw0_rd_out[1550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.207 129.961 279.225 130.015 ; + END + END rw0_rd_out[1550] + PIN rw0_rd_out[1551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.387 129.961 279.405 130.015 ; + END + END rw0_rd_out[1551] + PIN rw0_rd_out[1552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.567 129.961 279.585 130.015 ; + END + END rw0_rd_out[1552] + PIN rw0_rd_out[1553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.747 129.961 279.765 130.015 ; + END + END rw0_rd_out[1553] + PIN rw0_rd_out[1554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 279.927 129.961 279.945 130.015 ; + END + END rw0_rd_out[1554] + PIN rw0_rd_out[1555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.107 129.961 280.125 130.015 ; + END + END rw0_rd_out[1555] + PIN rw0_rd_out[1556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.287 129.961 280.305 130.015 ; + END + END rw0_rd_out[1556] + PIN rw0_rd_out[1557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.467 129.961 280.485 130.015 ; + END + END rw0_rd_out[1557] + PIN rw0_rd_out[1558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.647 129.961 280.665 130.015 ; + END + END rw0_rd_out[1558] + PIN rw0_rd_out[1559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 280.827 129.961 280.845 130.015 ; + END + END rw0_rd_out[1559] + PIN rw0_rd_out[1560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.007 129.961 281.025 130.015 ; + END + END rw0_rd_out[1560] + PIN rw0_rd_out[1561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.187 129.961 281.205 130.015 ; + END + END rw0_rd_out[1561] + PIN rw0_rd_out[1562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.367 129.961 281.385 130.015 ; + END + END rw0_rd_out[1562] + PIN rw0_rd_out[1563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.547 129.961 281.565 130.015 ; + END + END rw0_rd_out[1563] + PIN rw0_rd_out[1564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.727 129.961 281.745 130.015 ; + END + END rw0_rd_out[1564] + PIN rw0_rd_out[1565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 281.907 129.961 281.925 130.015 ; + END + END rw0_rd_out[1565] + PIN rw0_rd_out[1566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.087 129.961 282.105 130.015 ; + END + END rw0_rd_out[1566] + PIN rw0_rd_out[1567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.267 129.961 282.285 130.015 ; + END + END rw0_rd_out[1567] + PIN rw0_rd_out[1568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.447 129.961 282.465 130.015 ; + END + END rw0_rd_out[1568] + PIN rw0_rd_out[1569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.627 129.961 282.645 130.015 ; + END + END rw0_rd_out[1569] + PIN rw0_rd_out[1570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.807 129.961 282.825 130.015 ; + END + END rw0_rd_out[1570] + PIN rw0_rd_out[1571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 282.987 129.961 283.005 130.015 ; + END + END rw0_rd_out[1571] + PIN rw0_rd_out[1572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.167 129.961 283.185 130.015 ; + END + END rw0_rd_out[1572] + PIN rw0_rd_out[1573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.347 129.961 283.365 130.015 ; + END + END rw0_rd_out[1573] + PIN rw0_rd_out[1574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.527 129.961 283.545 130.015 ; + END + END rw0_rd_out[1574] + PIN rw0_rd_out[1575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.707 129.961 283.725 130.015 ; + END + END rw0_rd_out[1575] + PIN rw0_rd_out[1576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 283.887 129.961 283.905 130.015 ; + END + END rw0_rd_out[1576] + PIN rw0_rd_out[1577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.067 129.961 284.085 130.015 ; + END + END rw0_rd_out[1577] + PIN rw0_rd_out[1578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.247 129.961 284.265 130.015 ; + END + END rw0_rd_out[1578] + PIN rw0_rd_out[1579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.427 129.961 284.445 130.015 ; + END + END rw0_rd_out[1579] + PIN rw0_rd_out[1580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.607 129.961 284.625 130.015 ; + END + END rw0_rd_out[1580] + PIN rw0_rd_out[1581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.787 129.961 284.805 130.015 ; + END + END rw0_rd_out[1581] + PIN rw0_rd_out[1582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 284.967 129.961 284.985 130.015 ; + END + END rw0_rd_out[1582] + PIN rw0_rd_out[1583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.147 129.961 285.165 130.015 ; + END + END rw0_rd_out[1583] + PIN rw0_rd_out[1584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.327 129.961 285.345 130.015 ; + END + END rw0_rd_out[1584] + PIN rw0_rd_out[1585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.507 129.961 285.525 130.015 ; + END + END rw0_rd_out[1585] + PIN rw0_rd_out[1586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.687 129.961 285.705 130.015 ; + END + END rw0_rd_out[1586] + PIN rw0_rd_out[1587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 285.867 129.961 285.885 130.015 ; + END + END rw0_rd_out[1587] + PIN rw0_rd_out[1588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.047 129.961 286.065 130.015 ; + END + END rw0_rd_out[1588] + PIN rw0_rd_out[1589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.227 129.961 286.245 130.015 ; + END + END rw0_rd_out[1589] + PIN rw0_rd_out[1590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.407 129.961 286.425 130.015 ; + END + END rw0_rd_out[1590] + PIN rw0_rd_out[1591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.587 129.961 286.605 130.015 ; + END + END rw0_rd_out[1591] + PIN rw0_rd_out[1592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.767 129.961 286.785 130.015 ; + END + END rw0_rd_out[1592] + PIN rw0_rd_out[1593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 286.947 129.961 286.965 130.015 ; + END + END rw0_rd_out[1593] + PIN rw0_rd_out[1594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.127 129.961 287.145 130.015 ; + END + END rw0_rd_out[1594] + PIN rw0_rd_out[1595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.307 129.961 287.325 130.015 ; + END + END rw0_rd_out[1595] + PIN rw0_rd_out[1596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.487 129.961 287.505 130.015 ; + END + END rw0_rd_out[1596] + PIN rw0_rd_out[1597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.667 129.961 287.685 130.015 ; + END + END rw0_rd_out[1597] + PIN rw0_rd_out[1598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 287.847 129.961 287.865 130.015 ; + END + END rw0_rd_out[1598] + PIN rw0_rd_out[1599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.027 129.961 288.045 130.015 ; + END + END rw0_rd_out[1599] + PIN rw0_rd_out[1600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.207 129.961 288.225 130.015 ; + END + END rw0_rd_out[1600] + PIN rw0_rd_out[1601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.387 129.961 288.405 130.015 ; + END + END rw0_rd_out[1601] + PIN rw0_rd_out[1602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.567 129.961 288.585 130.015 ; + END + END rw0_rd_out[1602] + PIN rw0_rd_out[1603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.747 129.961 288.765 130.015 ; + END + END rw0_rd_out[1603] + PIN rw0_rd_out[1604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 288.927 129.961 288.945 130.015 ; + END + END rw0_rd_out[1604] + PIN rw0_rd_out[1605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.107 129.961 289.125 130.015 ; + END + END rw0_rd_out[1605] + PIN rw0_rd_out[1606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.287 129.961 289.305 130.015 ; + END + END rw0_rd_out[1606] + PIN rw0_rd_out[1607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.467 129.961 289.485 130.015 ; + END + END rw0_rd_out[1607] + PIN rw0_rd_out[1608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.647 129.961 289.665 130.015 ; + END + END rw0_rd_out[1608] + PIN rw0_rd_out[1609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 289.827 129.961 289.845 130.015 ; + END + END rw0_rd_out[1609] + PIN rw0_rd_out[1610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.007 129.961 290.025 130.015 ; + END + END rw0_rd_out[1610] + PIN rw0_rd_out[1611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.187 129.961 290.205 130.015 ; + END + END rw0_rd_out[1611] + PIN rw0_rd_out[1612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.367 129.961 290.385 130.015 ; + END + END rw0_rd_out[1612] + PIN rw0_rd_out[1613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.547 129.961 290.565 130.015 ; + END + END rw0_rd_out[1613] + PIN rw0_rd_out[1614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.727 129.961 290.745 130.015 ; + END + END rw0_rd_out[1614] + PIN rw0_rd_out[1615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 290.907 129.961 290.925 130.015 ; + END + END rw0_rd_out[1615] + PIN rw0_rd_out[1616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.087 129.961 291.105 130.015 ; + END + END rw0_rd_out[1616] + PIN rw0_rd_out[1617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.267 129.961 291.285 130.015 ; + END + END rw0_rd_out[1617] + PIN rw0_rd_out[1618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.447 129.961 291.465 130.015 ; + END + END rw0_rd_out[1618] + PIN rw0_rd_out[1619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.627 129.961 291.645 130.015 ; + END + END rw0_rd_out[1619] + PIN rw0_rd_out[1620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.807 129.961 291.825 130.015 ; + END + END rw0_rd_out[1620] + PIN rw0_rd_out[1621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 291.987 129.961 292.005 130.015 ; + END + END rw0_rd_out[1621] + PIN rw0_rd_out[1622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.167 129.961 292.185 130.015 ; + END + END rw0_rd_out[1622] + PIN rw0_rd_out[1623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.347 129.961 292.365 130.015 ; + END + END rw0_rd_out[1623] + PIN rw0_rd_out[1624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.527 129.961 292.545 130.015 ; + END + END rw0_rd_out[1624] + PIN rw0_rd_out[1625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.707 129.961 292.725 130.015 ; + END + END rw0_rd_out[1625] + PIN rw0_rd_out[1626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 292.887 129.961 292.905 130.015 ; + END + END rw0_rd_out[1626] + PIN rw0_rd_out[1627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.067 129.961 293.085 130.015 ; + END + END rw0_rd_out[1627] + PIN rw0_rd_out[1628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.247 129.961 293.265 130.015 ; + END + END rw0_rd_out[1628] + PIN rw0_rd_out[1629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.427 129.961 293.445 130.015 ; + END + END rw0_rd_out[1629] + PIN rw0_rd_out[1630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.607 129.961 293.625 130.015 ; + END + END rw0_rd_out[1630] + PIN rw0_rd_out[1631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.787 129.961 293.805 130.015 ; + END + END rw0_rd_out[1631] + PIN rw0_rd_out[1632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 293.967 129.961 293.985 130.015 ; + END + END rw0_rd_out[1632] + PIN rw0_rd_out[1633] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.147 129.961 294.165 130.015 ; + END + END rw0_rd_out[1633] + PIN rw0_rd_out[1634] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.327 129.961 294.345 130.015 ; + END + END rw0_rd_out[1634] + PIN rw0_rd_out[1635] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.507 129.961 294.525 130.015 ; + END + END rw0_rd_out[1635] + PIN rw0_rd_out[1636] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.687 129.961 294.705 130.015 ; + END + END rw0_rd_out[1636] + PIN rw0_rd_out[1637] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 294.867 129.961 294.885 130.015 ; + END + END rw0_rd_out[1637] + PIN rw0_rd_out[1638] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.047 129.961 295.065 130.015 ; + END + END rw0_rd_out[1638] + PIN rw0_rd_out[1639] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.227 129.961 295.245 130.015 ; + END + END rw0_rd_out[1639] + PIN rw0_rd_out[1640] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.407 129.961 295.425 130.015 ; + END + END rw0_rd_out[1640] + PIN rw0_rd_out[1641] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.587 129.961 295.605 130.015 ; + END + END rw0_rd_out[1641] + PIN rw0_rd_out[1642] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.767 129.961 295.785 130.015 ; + END + END rw0_rd_out[1642] + PIN rw0_rd_out[1643] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 295.947 129.961 295.965 130.015 ; + END + END rw0_rd_out[1643] + PIN rw0_rd_out[1644] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.127 129.961 296.145 130.015 ; + END + END rw0_rd_out[1644] + PIN rw0_rd_out[1645] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.307 129.961 296.325 130.015 ; + END + END rw0_rd_out[1645] + PIN rw0_rd_out[1646] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.487 129.961 296.505 130.015 ; + END + END rw0_rd_out[1646] + PIN rw0_rd_out[1647] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.667 129.961 296.685 130.015 ; + END + END rw0_rd_out[1647] + PIN rw0_rd_out[1648] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 296.847 129.961 296.865 130.015 ; + END + END rw0_rd_out[1648] + PIN rw0_rd_out[1649] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.027 129.961 297.045 130.015 ; + END + END rw0_rd_out[1649] + PIN rw0_rd_out[1650] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.207 129.961 297.225 130.015 ; + END + END rw0_rd_out[1650] + PIN rw0_rd_out[1651] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.387 129.961 297.405 130.015 ; + END + END rw0_rd_out[1651] + PIN rw0_rd_out[1652] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.567 129.961 297.585 130.015 ; + END + END rw0_rd_out[1652] + PIN rw0_rd_out[1653] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.747 129.961 297.765 130.015 ; + END + END rw0_rd_out[1653] + PIN rw0_rd_out[1654] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 297.927 129.961 297.945 130.015 ; + END + END rw0_rd_out[1654] + PIN rw0_rd_out[1655] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.107 129.961 298.125 130.015 ; + END + END rw0_rd_out[1655] + PIN rw0_rd_out[1656] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.287 129.961 298.305 130.015 ; + END + END rw0_rd_out[1656] + PIN rw0_rd_out[1657] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.467 129.961 298.485 130.015 ; + END + END rw0_rd_out[1657] + PIN rw0_rd_out[1658] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.647 129.961 298.665 130.015 ; + END + END rw0_rd_out[1658] + PIN rw0_rd_out[1659] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 298.827 129.961 298.845 130.015 ; + END + END rw0_rd_out[1659] + PIN rw0_rd_out[1660] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.007 129.961 299.025 130.015 ; + END + END rw0_rd_out[1660] + PIN rw0_rd_out[1661] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.187 129.961 299.205 130.015 ; + END + END rw0_rd_out[1661] + PIN rw0_rd_out[1662] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.367 129.961 299.385 130.015 ; + END + END rw0_rd_out[1662] + PIN rw0_rd_out[1663] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.547 129.961 299.565 130.015 ; + END + END rw0_rd_out[1663] + PIN rw0_rd_out[1664] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.727 129.961 299.745 130.015 ; + END + END rw0_rd_out[1664] + PIN rw0_rd_out[1665] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 299.907 129.961 299.925 130.015 ; + END + END rw0_rd_out[1665] + PIN rw0_rd_out[1666] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.087 129.961 300.105 130.015 ; + END + END rw0_rd_out[1666] + PIN rw0_rd_out[1667] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.267 129.961 300.285 130.015 ; + END + END rw0_rd_out[1667] + PIN rw0_rd_out[1668] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.447 129.961 300.465 130.015 ; + END + END rw0_rd_out[1668] + PIN rw0_rd_out[1669] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.627 129.961 300.645 130.015 ; + END + END rw0_rd_out[1669] + PIN rw0_rd_out[1670] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.807 129.961 300.825 130.015 ; + END + END rw0_rd_out[1670] + PIN rw0_rd_out[1671] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 300.987 129.961 301.005 130.015 ; + END + END rw0_rd_out[1671] + PIN rw0_rd_out[1672] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.167 129.961 301.185 130.015 ; + END + END rw0_rd_out[1672] + PIN rw0_rd_out[1673] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.347 129.961 301.365 130.015 ; + END + END rw0_rd_out[1673] + PIN rw0_rd_out[1674] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.527 129.961 301.545 130.015 ; + END + END rw0_rd_out[1674] + PIN rw0_rd_out[1675] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.707 129.961 301.725 130.015 ; + END + END rw0_rd_out[1675] + PIN rw0_rd_out[1676] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 301.887 129.961 301.905 130.015 ; + END + END rw0_rd_out[1676] + PIN rw0_rd_out[1677] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.067 129.961 302.085 130.015 ; + END + END rw0_rd_out[1677] + PIN rw0_rd_out[1678] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.247 129.961 302.265 130.015 ; + END + END rw0_rd_out[1678] + PIN rw0_rd_out[1679] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.427 129.961 302.445 130.015 ; + END + END rw0_rd_out[1679] + PIN rw0_rd_out[1680] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.607 129.961 302.625 130.015 ; + END + END rw0_rd_out[1680] + PIN rw0_rd_out[1681] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.787 129.961 302.805 130.015 ; + END + END rw0_rd_out[1681] + PIN rw0_rd_out[1682] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 302.967 129.961 302.985 130.015 ; + END + END rw0_rd_out[1682] + PIN rw0_rd_out[1683] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.147 129.961 303.165 130.015 ; + END + END rw0_rd_out[1683] + PIN rw0_rd_out[1684] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.327 129.961 303.345 130.015 ; + END + END rw0_rd_out[1684] + PIN rw0_rd_out[1685] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.507 129.961 303.525 130.015 ; + END + END rw0_rd_out[1685] + PIN rw0_rd_out[1686] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.687 129.961 303.705 130.015 ; + END + END rw0_rd_out[1686] + PIN rw0_rd_out[1687] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 303.867 129.961 303.885 130.015 ; + END + END rw0_rd_out[1687] + PIN rw0_rd_out[1688] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.047 129.961 304.065 130.015 ; + END + END rw0_rd_out[1688] + PIN rw0_rd_out[1689] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.227 129.961 304.245 130.015 ; + END + END rw0_rd_out[1689] + PIN rw0_rd_out[1690] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.407 129.961 304.425 130.015 ; + END + END rw0_rd_out[1690] + PIN rw0_rd_out[1691] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.587 129.961 304.605 130.015 ; + END + END rw0_rd_out[1691] + PIN rw0_rd_out[1692] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.767 129.961 304.785 130.015 ; + END + END rw0_rd_out[1692] + PIN rw0_rd_out[1693] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 304.947 129.961 304.965 130.015 ; + END + END rw0_rd_out[1693] + PIN rw0_rd_out[1694] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.127 129.961 305.145 130.015 ; + END + END rw0_rd_out[1694] + PIN rw0_rd_out[1695] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.307 129.961 305.325 130.015 ; + END + END rw0_rd_out[1695] + PIN rw0_rd_out[1696] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.487 129.961 305.505 130.015 ; + END + END rw0_rd_out[1696] + PIN rw0_rd_out[1697] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.667 129.961 305.685 130.015 ; + END + END rw0_rd_out[1697] + PIN rw0_rd_out[1698] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 305.847 129.961 305.865 130.015 ; + END + END rw0_rd_out[1698] + PIN rw0_rd_out[1699] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.027 129.961 306.045 130.015 ; + END + END rw0_rd_out[1699] + PIN rw0_rd_out[1700] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.207 129.961 306.225 130.015 ; + END + END rw0_rd_out[1700] + PIN rw0_rd_out[1701] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.387 129.961 306.405 130.015 ; + END + END rw0_rd_out[1701] + PIN rw0_rd_out[1702] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.567 129.961 306.585 130.015 ; + END + END rw0_rd_out[1702] + PIN rw0_rd_out[1703] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.747 129.961 306.765 130.015 ; + END + END rw0_rd_out[1703] + PIN rw0_rd_out[1704] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 306.927 129.961 306.945 130.015 ; + END + END rw0_rd_out[1704] + PIN rw0_rd_out[1705] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.107 129.961 307.125 130.015 ; + END + END rw0_rd_out[1705] + PIN rw0_rd_out[1706] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.287 129.961 307.305 130.015 ; + END + END rw0_rd_out[1706] + PIN rw0_rd_out[1707] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.467 129.961 307.485 130.015 ; + END + END rw0_rd_out[1707] + PIN rw0_rd_out[1708] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.647 129.961 307.665 130.015 ; + END + END rw0_rd_out[1708] + PIN rw0_rd_out[1709] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 307.827 129.961 307.845 130.015 ; + END + END rw0_rd_out[1709] + PIN rw0_rd_out[1710] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.007 129.961 308.025 130.015 ; + END + END rw0_rd_out[1710] + PIN rw0_rd_out[1711] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.187 129.961 308.205 130.015 ; + END + END rw0_rd_out[1711] + PIN rw0_rd_out[1712] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.367 129.961 308.385 130.015 ; + END + END rw0_rd_out[1712] + PIN rw0_rd_out[1713] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.547 129.961 308.565 130.015 ; + END + END rw0_rd_out[1713] + PIN rw0_rd_out[1714] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.727 129.961 308.745 130.015 ; + END + END rw0_rd_out[1714] + PIN rw0_rd_out[1715] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 308.907 129.961 308.925 130.015 ; + END + END rw0_rd_out[1715] + PIN rw0_rd_out[1716] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.087 129.961 309.105 130.015 ; + END + END rw0_rd_out[1716] + PIN rw0_rd_out[1717] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.267 129.961 309.285 130.015 ; + END + END rw0_rd_out[1717] + PIN rw0_rd_out[1718] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.447 129.961 309.465 130.015 ; + END + END rw0_rd_out[1718] + PIN rw0_rd_out[1719] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.627 129.961 309.645 130.015 ; + END + END rw0_rd_out[1719] + PIN rw0_rd_out[1720] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.807 129.961 309.825 130.015 ; + END + END rw0_rd_out[1720] + PIN rw0_rd_out[1721] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 309.987 129.961 310.005 130.015 ; + END + END rw0_rd_out[1721] + PIN rw0_rd_out[1722] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.167 129.961 310.185 130.015 ; + END + END rw0_rd_out[1722] + PIN rw0_rd_out[1723] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.347 129.961 310.365 130.015 ; + END + END rw0_rd_out[1723] + PIN rw0_rd_out[1724] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.527 129.961 310.545 130.015 ; + END + END rw0_rd_out[1724] + PIN rw0_rd_out[1725] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.707 129.961 310.725 130.015 ; + END + END rw0_rd_out[1725] + PIN rw0_rd_out[1726] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 310.887 129.961 310.905 130.015 ; + END + END rw0_rd_out[1726] + PIN rw0_rd_out[1727] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.067 129.961 311.085 130.015 ; + END + END rw0_rd_out[1727] + PIN rw0_rd_out[1728] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.247 129.961 311.265 130.015 ; + END + END rw0_rd_out[1728] + PIN rw0_rd_out[1729] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.427 129.961 311.445 130.015 ; + END + END rw0_rd_out[1729] + PIN rw0_rd_out[1730] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.607 129.961 311.625 130.015 ; + END + END rw0_rd_out[1730] + PIN rw0_rd_out[1731] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.787 129.961 311.805 130.015 ; + END + END rw0_rd_out[1731] + PIN rw0_rd_out[1732] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 311.967 129.961 311.985 130.015 ; + END + END rw0_rd_out[1732] + PIN rw0_rd_out[1733] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.147 129.961 312.165 130.015 ; + END + END rw0_rd_out[1733] + PIN rw0_rd_out[1734] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.327 129.961 312.345 130.015 ; + END + END rw0_rd_out[1734] + PIN rw0_rd_out[1735] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.507 129.961 312.525 130.015 ; + END + END rw0_rd_out[1735] + PIN rw0_rd_out[1736] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.687 129.961 312.705 130.015 ; + END + END rw0_rd_out[1736] + PIN rw0_rd_out[1737] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 312.867 129.961 312.885 130.015 ; + END + END rw0_rd_out[1737] + PIN rw0_rd_out[1738] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.047 129.961 313.065 130.015 ; + END + END rw0_rd_out[1738] + PIN rw0_rd_out[1739] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.227 129.961 313.245 130.015 ; + END + END rw0_rd_out[1739] + PIN rw0_rd_out[1740] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.407 129.961 313.425 130.015 ; + END + END rw0_rd_out[1740] + PIN rw0_rd_out[1741] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.587 129.961 313.605 130.015 ; + END + END rw0_rd_out[1741] + PIN rw0_rd_out[1742] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.767 129.961 313.785 130.015 ; + END + END rw0_rd_out[1742] + PIN rw0_rd_out[1743] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 313.947 129.961 313.965 130.015 ; + END + END rw0_rd_out[1743] + PIN rw0_rd_out[1744] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.127 129.961 314.145 130.015 ; + END + END rw0_rd_out[1744] + PIN rw0_rd_out[1745] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.307 129.961 314.325 130.015 ; + END + END rw0_rd_out[1745] + PIN rw0_rd_out[1746] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.487 129.961 314.505 130.015 ; + END + END rw0_rd_out[1746] + PIN rw0_rd_out[1747] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.667 129.961 314.685 130.015 ; + END + END rw0_rd_out[1747] + PIN rw0_rd_out[1748] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 314.847 129.961 314.865 130.015 ; + END + END rw0_rd_out[1748] + PIN rw0_rd_out[1749] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.027 129.961 315.045 130.015 ; + END + END rw0_rd_out[1749] + PIN rw0_rd_out[1750] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.207 129.961 315.225 130.015 ; + END + END rw0_rd_out[1750] + PIN rw0_rd_out[1751] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.387 129.961 315.405 130.015 ; + END + END rw0_rd_out[1751] + PIN rw0_rd_out[1752] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.567 129.961 315.585 130.015 ; + END + END rw0_rd_out[1752] + PIN rw0_rd_out[1753] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.747 129.961 315.765 130.015 ; + END + END rw0_rd_out[1753] + PIN rw0_rd_out[1754] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 315.927 129.961 315.945 130.015 ; + END + END rw0_rd_out[1754] + PIN rw0_rd_out[1755] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.107 129.961 316.125 130.015 ; + END + END rw0_rd_out[1755] + PIN rw0_rd_out[1756] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.287 129.961 316.305 130.015 ; + END + END rw0_rd_out[1756] + PIN rw0_rd_out[1757] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.467 129.961 316.485 130.015 ; + END + END rw0_rd_out[1757] + PIN rw0_rd_out[1758] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.647 129.961 316.665 130.015 ; + END + END rw0_rd_out[1758] + PIN rw0_rd_out[1759] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 316.827 129.961 316.845 130.015 ; + END + END rw0_rd_out[1759] + PIN rw0_rd_out[1760] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.007 129.961 317.025 130.015 ; + END + END rw0_rd_out[1760] + PIN rw0_rd_out[1761] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.187 129.961 317.205 130.015 ; + END + END rw0_rd_out[1761] + PIN rw0_rd_out[1762] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.367 129.961 317.385 130.015 ; + END + END rw0_rd_out[1762] + PIN rw0_rd_out[1763] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.547 129.961 317.565 130.015 ; + END + END rw0_rd_out[1763] + PIN rw0_rd_out[1764] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.727 129.961 317.745 130.015 ; + END + END rw0_rd_out[1764] + PIN rw0_rd_out[1765] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 317.907 129.961 317.925 130.015 ; + END + END rw0_rd_out[1765] + PIN rw0_rd_out[1766] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.087 129.961 318.105 130.015 ; + END + END rw0_rd_out[1766] + PIN rw0_rd_out[1767] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.267 129.961 318.285 130.015 ; + END + END rw0_rd_out[1767] + PIN rw0_rd_out[1768] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.447 129.961 318.465 130.015 ; + END + END rw0_rd_out[1768] + PIN rw0_rd_out[1769] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.627 129.961 318.645 130.015 ; + END + END rw0_rd_out[1769] + PIN rw0_rd_out[1770] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.807 129.961 318.825 130.015 ; + END + END rw0_rd_out[1770] + PIN rw0_rd_out[1771] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 318.987 129.961 319.005 130.015 ; + END + END rw0_rd_out[1771] + PIN rw0_rd_out[1772] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.167 129.961 319.185 130.015 ; + END + END rw0_rd_out[1772] + PIN rw0_rd_out[1773] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.347 129.961 319.365 130.015 ; + END + END rw0_rd_out[1773] + PIN rw0_rd_out[1774] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.527 129.961 319.545 130.015 ; + END + END rw0_rd_out[1774] + PIN rw0_rd_out[1775] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.707 129.961 319.725 130.015 ; + END + END rw0_rd_out[1775] + PIN rw0_rd_out[1776] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 319.887 129.961 319.905 130.015 ; + END + END rw0_rd_out[1776] + PIN rw0_rd_out[1777] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.067 129.961 320.085 130.015 ; + END + END rw0_rd_out[1777] + PIN rw0_rd_out[1778] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.247 129.961 320.265 130.015 ; + END + END rw0_rd_out[1778] + PIN rw0_rd_out[1779] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.427 129.961 320.445 130.015 ; + END + END rw0_rd_out[1779] + PIN rw0_rd_out[1780] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.607 129.961 320.625 130.015 ; + END + END rw0_rd_out[1780] + PIN rw0_rd_out[1781] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.787 129.961 320.805 130.015 ; + END + END rw0_rd_out[1781] + PIN rw0_rd_out[1782] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 320.967 129.961 320.985 130.015 ; + END + END rw0_rd_out[1782] + PIN rw0_rd_out[1783] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.147 129.961 321.165 130.015 ; + END + END rw0_rd_out[1783] + PIN rw0_rd_out[1784] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.327 129.961 321.345 130.015 ; + END + END rw0_rd_out[1784] + PIN rw0_rd_out[1785] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.507 129.961 321.525 130.015 ; + END + END rw0_rd_out[1785] + PIN rw0_rd_out[1786] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.687 129.961 321.705 130.015 ; + END + END rw0_rd_out[1786] + PIN rw0_rd_out[1787] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 321.867 129.961 321.885 130.015 ; + END + END rw0_rd_out[1787] + PIN rw0_rd_out[1788] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.047 129.961 322.065 130.015 ; + END + END rw0_rd_out[1788] + PIN rw0_rd_out[1789] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.227 129.961 322.245 130.015 ; + END + END rw0_rd_out[1789] + PIN rw0_rd_out[1790] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.407 129.961 322.425 130.015 ; + END + END rw0_rd_out[1790] + PIN rw0_rd_out[1791] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.587 129.961 322.605 130.015 ; + END + END rw0_rd_out[1791] + PIN rw0_rd_out[1792] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.767 129.961 322.785 130.015 ; + END + END rw0_rd_out[1792] + PIN rw0_rd_out[1793] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 322.947 129.961 322.965 130.015 ; + END + END rw0_rd_out[1793] + PIN rw0_rd_out[1794] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.127 129.961 323.145 130.015 ; + END + END rw0_rd_out[1794] + PIN rw0_rd_out[1795] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.307 129.961 323.325 130.015 ; + END + END rw0_rd_out[1795] + PIN rw0_rd_out[1796] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.487 129.961 323.505 130.015 ; + END + END rw0_rd_out[1796] + PIN rw0_rd_out[1797] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.667 129.961 323.685 130.015 ; + END + END rw0_rd_out[1797] + PIN rw0_rd_out[1798] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 323.847 129.961 323.865 130.015 ; + END + END rw0_rd_out[1798] + PIN rw0_rd_out[1799] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.027 129.961 324.045 130.015 ; + END + END rw0_rd_out[1799] + PIN rw0_rd_out[1800] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.207 129.961 324.225 130.015 ; + END + END rw0_rd_out[1800] + PIN rw0_rd_out[1801] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.387 129.961 324.405 130.015 ; + END + END rw0_rd_out[1801] + PIN rw0_rd_out[1802] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.567 129.961 324.585 130.015 ; + END + END rw0_rd_out[1802] + PIN rw0_rd_out[1803] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.747 129.961 324.765 130.015 ; + END + END rw0_rd_out[1803] + PIN rw0_rd_out[1804] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 324.927 129.961 324.945 130.015 ; + END + END rw0_rd_out[1804] + PIN rw0_rd_out[1805] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.107 129.961 325.125 130.015 ; + END + END rw0_rd_out[1805] + PIN rw0_rd_out[1806] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.287 129.961 325.305 130.015 ; + END + END rw0_rd_out[1806] + PIN rw0_rd_out[1807] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.467 129.961 325.485 130.015 ; + END + END rw0_rd_out[1807] + PIN rw0_rd_out[1808] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.647 129.961 325.665 130.015 ; + END + END rw0_rd_out[1808] + PIN rw0_rd_out[1809] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 325.827 129.961 325.845 130.015 ; + END + END rw0_rd_out[1809] + PIN rw0_rd_out[1810] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.007 129.961 326.025 130.015 ; + END + END rw0_rd_out[1810] + PIN rw0_rd_out[1811] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.187 129.961 326.205 130.015 ; + END + END rw0_rd_out[1811] + PIN rw0_rd_out[1812] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.367 129.961 326.385 130.015 ; + END + END rw0_rd_out[1812] + PIN rw0_rd_out[1813] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.547 129.961 326.565 130.015 ; + END + END rw0_rd_out[1813] + PIN rw0_rd_out[1814] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.727 129.961 326.745 130.015 ; + END + END rw0_rd_out[1814] + PIN rw0_rd_out[1815] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 326.907 129.961 326.925 130.015 ; + END + END rw0_rd_out[1815] + PIN rw0_rd_out[1816] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.087 129.961 327.105 130.015 ; + END + END rw0_rd_out[1816] + PIN rw0_rd_out[1817] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.267 129.961 327.285 130.015 ; + END + END rw0_rd_out[1817] + PIN rw0_rd_out[1818] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.447 129.961 327.465 130.015 ; + END + END rw0_rd_out[1818] + PIN rw0_rd_out[1819] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.627 129.961 327.645 130.015 ; + END + END rw0_rd_out[1819] + PIN rw0_rd_out[1820] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.807 129.961 327.825 130.015 ; + END + END rw0_rd_out[1820] + PIN rw0_rd_out[1821] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 327.987 129.961 328.005 130.015 ; + END + END rw0_rd_out[1821] + PIN rw0_rd_out[1822] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.167 129.961 328.185 130.015 ; + END + END rw0_rd_out[1822] + PIN rw0_rd_out[1823] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.347 129.961 328.365 130.015 ; + END + END rw0_rd_out[1823] + PIN rw0_rd_out[1824] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.527 129.961 328.545 130.015 ; + END + END rw0_rd_out[1824] + PIN rw0_rd_out[1825] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.707 129.961 328.725 130.015 ; + END + END rw0_rd_out[1825] + PIN rw0_rd_out[1826] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 328.887 129.961 328.905 130.015 ; + END + END rw0_rd_out[1826] + PIN rw0_rd_out[1827] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.067 129.961 329.085 130.015 ; + END + END rw0_rd_out[1827] + PIN rw0_rd_out[1828] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.247 129.961 329.265 130.015 ; + END + END rw0_rd_out[1828] + PIN rw0_rd_out[1829] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.427 129.961 329.445 130.015 ; + END + END rw0_rd_out[1829] + PIN rw0_rd_out[1830] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.607 129.961 329.625 130.015 ; + END + END rw0_rd_out[1830] + PIN rw0_rd_out[1831] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.787 129.961 329.805 130.015 ; + END + END rw0_rd_out[1831] + PIN rw0_rd_out[1832] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 329.967 129.961 329.985 130.015 ; + END + END rw0_rd_out[1832] + PIN rw0_rd_out[1833] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.147 129.961 330.165 130.015 ; + END + END rw0_rd_out[1833] + PIN rw0_rd_out[1834] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.327 129.961 330.345 130.015 ; + END + END rw0_rd_out[1834] + PIN rw0_rd_out[1835] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.507 129.961 330.525 130.015 ; + END + END rw0_rd_out[1835] + PIN rw0_rd_out[1836] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.687 129.961 330.705 130.015 ; + END + END rw0_rd_out[1836] + PIN rw0_rd_out[1837] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 330.867 129.961 330.885 130.015 ; + END + END rw0_rd_out[1837] + PIN rw0_rd_out[1838] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.047 129.961 331.065 130.015 ; + END + END rw0_rd_out[1838] + PIN rw0_rd_out[1839] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.227 129.961 331.245 130.015 ; + END + END rw0_rd_out[1839] + PIN rw0_rd_out[1840] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.407 129.961 331.425 130.015 ; + END + END rw0_rd_out[1840] + PIN rw0_rd_out[1841] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.587 129.961 331.605 130.015 ; + END + END rw0_rd_out[1841] + PIN rw0_rd_out[1842] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.767 129.961 331.785 130.015 ; + END + END rw0_rd_out[1842] + PIN rw0_rd_out[1843] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 331.947 129.961 331.965 130.015 ; + END + END rw0_rd_out[1843] + PIN rw0_rd_out[1844] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.127 129.961 332.145 130.015 ; + END + END rw0_rd_out[1844] + PIN rw0_rd_out[1845] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.307 129.961 332.325 130.015 ; + END + END rw0_rd_out[1845] + PIN rw0_rd_out[1846] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.487 129.961 332.505 130.015 ; + END + END rw0_rd_out[1846] + PIN rw0_rd_out[1847] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.667 129.961 332.685 130.015 ; + END + END rw0_rd_out[1847] + PIN rw0_rd_out[1848] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 332.847 129.961 332.865 130.015 ; + END + END rw0_rd_out[1848] + PIN rw0_rd_out[1849] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.027 129.961 333.045 130.015 ; + END + END rw0_rd_out[1849] + PIN rw0_rd_out[1850] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.207 129.961 333.225 130.015 ; + END + END rw0_rd_out[1850] + PIN rw0_rd_out[1851] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.387 129.961 333.405 130.015 ; + END + END rw0_rd_out[1851] + PIN rw0_rd_out[1852] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.567 129.961 333.585 130.015 ; + END + END rw0_rd_out[1852] + PIN rw0_rd_out[1853] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.747 129.961 333.765 130.015 ; + END + END rw0_rd_out[1853] + PIN rw0_rd_out[1854] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 333.927 129.961 333.945 130.015 ; + END + END rw0_rd_out[1854] + PIN rw0_rd_out[1855] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.107 129.961 334.125 130.015 ; + END + END rw0_rd_out[1855] + PIN rw0_rd_out[1856] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.287 129.961 334.305 130.015 ; + END + END rw0_rd_out[1856] + PIN rw0_rd_out[1857] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.467 129.961 334.485 130.015 ; + END + END rw0_rd_out[1857] + PIN rw0_rd_out[1858] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.647 129.961 334.665 130.015 ; + END + END rw0_rd_out[1858] + PIN rw0_rd_out[1859] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 334.827 129.961 334.845 130.015 ; + END + END rw0_rd_out[1859] + PIN rw0_rd_out[1860] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.007 129.961 335.025 130.015 ; + END + END rw0_rd_out[1860] + PIN rw0_rd_out[1861] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.187 129.961 335.205 130.015 ; + END + END rw0_rd_out[1861] + PIN rw0_rd_out[1862] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.367 129.961 335.385 130.015 ; + END + END rw0_rd_out[1862] + PIN rw0_rd_out[1863] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.547 129.961 335.565 130.015 ; + END + END rw0_rd_out[1863] + PIN rw0_rd_out[1864] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.727 129.961 335.745 130.015 ; + END + END rw0_rd_out[1864] + PIN rw0_rd_out[1865] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 335.907 129.961 335.925 130.015 ; + END + END rw0_rd_out[1865] + PIN rw0_rd_out[1866] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.087 129.961 336.105 130.015 ; + END + END rw0_rd_out[1866] + PIN rw0_rd_out[1867] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.267 129.961 336.285 130.015 ; + END + END rw0_rd_out[1867] + PIN rw0_rd_out[1868] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.447 129.961 336.465 130.015 ; + END + END rw0_rd_out[1868] + PIN rw0_rd_out[1869] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.627 129.961 336.645 130.015 ; + END + END rw0_rd_out[1869] + PIN rw0_rd_out[1870] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.807 129.961 336.825 130.015 ; + END + END rw0_rd_out[1870] + PIN rw0_rd_out[1871] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 336.987 129.961 337.005 130.015 ; + END + END rw0_rd_out[1871] + PIN rw0_rd_out[1872] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.167 129.961 337.185 130.015 ; + END + END rw0_rd_out[1872] + PIN rw0_rd_out[1873] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.347 129.961 337.365 130.015 ; + END + END rw0_rd_out[1873] + PIN rw0_rd_out[1874] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.527 129.961 337.545 130.015 ; + END + END rw0_rd_out[1874] + PIN rw0_rd_out[1875] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.707 129.961 337.725 130.015 ; + END + END rw0_rd_out[1875] + PIN rw0_rd_out[1876] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 337.887 129.961 337.905 130.015 ; + END + END rw0_rd_out[1876] + PIN rw0_rd_out[1877] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.067 129.961 338.085 130.015 ; + END + END rw0_rd_out[1877] + PIN rw0_rd_out[1878] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.247 129.961 338.265 130.015 ; + END + END rw0_rd_out[1878] + PIN rw0_rd_out[1879] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.427 129.961 338.445 130.015 ; + END + END rw0_rd_out[1879] + PIN rw0_rd_out[1880] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.607 129.961 338.625 130.015 ; + END + END rw0_rd_out[1880] + PIN rw0_rd_out[1881] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.787 129.961 338.805 130.015 ; + END + END rw0_rd_out[1881] + PIN rw0_rd_out[1882] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 338.967 129.961 338.985 130.015 ; + END + END rw0_rd_out[1882] + PIN rw0_rd_out[1883] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.147 129.961 339.165 130.015 ; + END + END rw0_rd_out[1883] + PIN rw0_rd_out[1884] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.327 129.961 339.345 130.015 ; + END + END rw0_rd_out[1884] + PIN rw0_rd_out[1885] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.507 129.961 339.525 130.015 ; + END + END rw0_rd_out[1885] + PIN rw0_rd_out[1886] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.687 129.961 339.705 130.015 ; + END + END rw0_rd_out[1886] + PIN rw0_rd_out[1887] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 339.867 129.961 339.885 130.015 ; + END + END rw0_rd_out[1887] + PIN rw0_rd_out[1888] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.047 129.961 340.065 130.015 ; + END + END rw0_rd_out[1888] + PIN rw0_rd_out[1889] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.227 129.961 340.245 130.015 ; + END + END rw0_rd_out[1889] + PIN rw0_rd_out[1890] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.407 129.961 340.425 130.015 ; + END + END rw0_rd_out[1890] + PIN rw0_rd_out[1891] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.587 129.961 340.605 130.015 ; + END + END rw0_rd_out[1891] + PIN rw0_rd_out[1892] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.767 129.961 340.785 130.015 ; + END + END rw0_rd_out[1892] + PIN rw0_rd_out[1893] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 340.947 129.961 340.965 130.015 ; + END + END rw0_rd_out[1893] + PIN rw0_rd_out[1894] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.127 129.961 341.145 130.015 ; + END + END rw0_rd_out[1894] + PIN rw0_rd_out[1895] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.307 129.961 341.325 130.015 ; + END + END rw0_rd_out[1895] + PIN rw0_rd_out[1896] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.487 129.961 341.505 130.015 ; + END + END rw0_rd_out[1896] + PIN rw0_rd_out[1897] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.667 129.961 341.685 130.015 ; + END + END rw0_rd_out[1897] + PIN rw0_rd_out[1898] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 341.847 129.961 341.865 130.015 ; + END + END rw0_rd_out[1898] + PIN rw0_rd_out[1899] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.027 129.961 342.045 130.015 ; + END + END rw0_rd_out[1899] + PIN rw0_rd_out[1900] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.207 129.961 342.225 130.015 ; + END + END rw0_rd_out[1900] + PIN rw0_rd_out[1901] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.387 129.961 342.405 130.015 ; + END + END rw0_rd_out[1901] + PIN rw0_rd_out[1902] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.567 129.961 342.585 130.015 ; + END + END rw0_rd_out[1902] + PIN rw0_rd_out[1903] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.747 129.961 342.765 130.015 ; + END + END rw0_rd_out[1903] + PIN rw0_rd_out[1904] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 342.927 129.961 342.945 130.015 ; + END + END rw0_rd_out[1904] + PIN rw0_rd_out[1905] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.107 129.961 343.125 130.015 ; + END + END rw0_rd_out[1905] + PIN rw0_rd_out[1906] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.287 129.961 343.305 130.015 ; + END + END rw0_rd_out[1906] + PIN rw0_rd_out[1907] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.467 129.961 343.485 130.015 ; + END + END rw0_rd_out[1907] + PIN rw0_rd_out[1908] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.647 129.961 343.665 130.015 ; + END + END rw0_rd_out[1908] + PIN rw0_rd_out[1909] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 343.827 129.961 343.845 130.015 ; + END + END rw0_rd_out[1909] + PIN rw0_rd_out[1910] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.007 129.961 344.025 130.015 ; + END + END rw0_rd_out[1910] + PIN rw0_rd_out[1911] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.187 129.961 344.205 130.015 ; + END + END rw0_rd_out[1911] + PIN rw0_rd_out[1912] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.367 129.961 344.385 130.015 ; + END + END rw0_rd_out[1912] + PIN rw0_rd_out[1913] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.547 129.961 344.565 130.015 ; + END + END rw0_rd_out[1913] + PIN rw0_rd_out[1914] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.727 129.961 344.745 130.015 ; + END + END rw0_rd_out[1914] + PIN rw0_rd_out[1915] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 344.907 129.961 344.925 130.015 ; + END + END rw0_rd_out[1915] + PIN rw0_rd_out[1916] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.087 129.961 345.105 130.015 ; + END + END rw0_rd_out[1916] + PIN rw0_rd_out[1917] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.267 129.961 345.285 130.015 ; + END + END rw0_rd_out[1917] + PIN rw0_rd_out[1918] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.447 129.961 345.465 130.015 ; + END + END rw0_rd_out[1918] + PIN rw0_rd_out[1919] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.627 129.961 345.645 130.015 ; + END + END rw0_rd_out[1919] + PIN rw0_rd_out[1920] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.807 129.961 345.825 130.015 ; + END + END rw0_rd_out[1920] + PIN rw0_rd_out[1921] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 345.987 129.961 346.005 130.015 ; + END + END rw0_rd_out[1921] + PIN rw0_rd_out[1922] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.167 129.961 346.185 130.015 ; + END + END rw0_rd_out[1922] + PIN rw0_rd_out[1923] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.347 129.961 346.365 130.015 ; + END + END rw0_rd_out[1923] + PIN rw0_rd_out[1924] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.527 129.961 346.545 130.015 ; + END + END rw0_rd_out[1924] + PIN rw0_rd_out[1925] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.707 129.961 346.725 130.015 ; + END + END rw0_rd_out[1925] + PIN rw0_rd_out[1926] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 346.887 129.961 346.905 130.015 ; + END + END rw0_rd_out[1926] + PIN rw0_rd_out[1927] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.067 129.961 347.085 130.015 ; + END + END rw0_rd_out[1927] + PIN rw0_rd_out[1928] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.247 129.961 347.265 130.015 ; + END + END rw0_rd_out[1928] + PIN rw0_rd_out[1929] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.427 129.961 347.445 130.015 ; + END + END rw0_rd_out[1929] + PIN rw0_rd_out[1930] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.607 129.961 347.625 130.015 ; + END + END rw0_rd_out[1930] + PIN rw0_rd_out[1931] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.787 129.961 347.805 130.015 ; + END + END rw0_rd_out[1931] + PIN rw0_rd_out[1932] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 347.967 129.961 347.985 130.015 ; + END + END rw0_rd_out[1932] + PIN rw0_rd_out[1933] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.147 129.961 348.165 130.015 ; + END + END rw0_rd_out[1933] + PIN rw0_rd_out[1934] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.327 129.961 348.345 130.015 ; + END + END rw0_rd_out[1934] + PIN rw0_rd_out[1935] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.507 129.961 348.525 130.015 ; + END + END rw0_rd_out[1935] + PIN rw0_rd_out[1936] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.687 129.961 348.705 130.015 ; + END + END rw0_rd_out[1936] + PIN rw0_rd_out[1937] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 348.867 129.961 348.885 130.015 ; + END + END rw0_rd_out[1937] + PIN rw0_rd_out[1938] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.047 129.961 349.065 130.015 ; + END + END rw0_rd_out[1938] + PIN rw0_rd_out[1939] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.227 129.961 349.245 130.015 ; + END + END rw0_rd_out[1939] + PIN rw0_rd_out[1940] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.407 129.961 349.425 130.015 ; + END + END rw0_rd_out[1940] + PIN rw0_rd_out[1941] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.587 129.961 349.605 130.015 ; + END + END rw0_rd_out[1941] + PIN rw0_rd_out[1942] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.767 129.961 349.785 130.015 ; + END + END rw0_rd_out[1942] + PIN rw0_rd_out[1943] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 349.947 129.961 349.965 130.015 ; + END + END rw0_rd_out[1943] + PIN rw0_rd_out[1944] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.127 129.961 350.145 130.015 ; + END + END rw0_rd_out[1944] + PIN rw0_rd_out[1945] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.307 129.961 350.325 130.015 ; + END + END rw0_rd_out[1945] + PIN rw0_rd_out[1946] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.487 129.961 350.505 130.015 ; + END + END rw0_rd_out[1946] + PIN rw0_rd_out[1947] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.667 129.961 350.685 130.015 ; + END + END rw0_rd_out[1947] + PIN rw0_rd_out[1948] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 350.847 129.961 350.865 130.015 ; + END + END rw0_rd_out[1948] + PIN rw0_rd_out[1949] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.027 129.961 351.045 130.015 ; + END + END rw0_rd_out[1949] + PIN rw0_rd_out[1950] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.207 129.961 351.225 130.015 ; + END + END rw0_rd_out[1950] + PIN rw0_rd_out[1951] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.387 129.961 351.405 130.015 ; + END + END rw0_rd_out[1951] + PIN rw0_rd_out[1952] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.567 129.961 351.585 130.015 ; + END + END rw0_rd_out[1952] + PIN rw0_rd_out[1953] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.747 129.961 351.765 130.015 ; + END + END rw0_rd_out[1953] + PIN rw0_rd_out[1954] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 351.927 129.961 351.945 130.015 ; + END + END rw0_rd_out[1954] + PIN rw0_rd_out[1955] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.107 129.961 352.125 130.015 ; + END + END rw0_rd_out[1955] + PIN rw0_rd_out[1956] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.287 129.961 352.305 130.015 ; + END + END rw0_rd_out[1956] + PIN rw0_rd_out[1957] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.467 129.961 352.485 130.015 ; + END + END rw0_rd_out[1957] + PIN rw0_rd_out[1958] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.647 129.961 352.665 130.015 ; + END + END rw0_rd_out[1958] + PIN rw0_rd_out[1959] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 352.827 129.961 352.845 130.015 ; + END + END rw0_rd_out[1959] + PIN rw0_rd_out[1960] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.007 129.961 353.025 130.015 ; + END + END rw0_rd_out[1960] + PIN rw0_rd_out[1961] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.187 129.961 353.205 130.015 ; + END + END rw0_rd_out[1961] + PIN rw0_rd_out[1962] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.367 129.961 353.385 130.015 ; + END + END rw0_rd_out[1962] + PIN rw0_rd_out[1963] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.547 129.961 353.565 130.015 ; + END + END rw0_rd_out[1963] + PIN rw0_rd_out[1964] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.727 129.961 353.745 130.015 ; + END + END rw0_rd_out[1964] + PIN rw0_rd_out[1965] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 353.907 129.961 353.925 130.015 ; + END + END rw0_rd_out[1965] + PIN rw0_rd_out[1966] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.087 129.961 354.105 130.015 ; + END + END rw0_rd_out[1966] + PIN rw0_rd_out[1967] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.267 129.961 354.285 130.015 ; + END + END rw0_rd_out[1967] + PIN rw0_rd_out[1968] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.447 129.961 354.465 130.015 ; + END + END rw0_rd_out[1968] + PIN rw0_rd_out[1969] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.627 129.961 354.645 130.015 ; + END + END rw0_rd_out[1969] + PIN rw0_rd_out[1970] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.807 129.961 354.825 130.015 ; + END + END rw0_rd_out[1970] + PIN rw0_rd_out[1971] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 354.987 129.961 355.005 130.015 ; + END + END rw0_rd_out[1971] + PIN rw0_rd_out[1972] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.167 129.961 355.185 130.015 ; + END + END rw0_rd_out[1972] + PIN rw0_rd_out[1973] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.347 129.961 355.365 130.015 ; + END + END rw0_rd_out[1973] + PIN rw0_rd_out[1974] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.527 129.961 355.545 130.015 ; + END + END rw0_rd_out[1974] + PIN rw0_rd_out[1975] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.707 129.961 355.725 130.015 ; + END + END rw0_rd_out[1975] + PIN rw0_rd_out[1976] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 355.887 129.961 355.905 130.015 ; + END + END rw0_rd_out[1976] + PIN rw0_rd_out[1977] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.067 129.961 356.085 130.015 ; + END + END rw0_rd_out[1977] + PIN rw0_rd_out[1978] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.247 129.961 356.265 130.015 ; + END + END rw0_rd_out[1978] + PIN rw0_rd_out[1979] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.427 129.961 356.445 130.015 ; + END + END rw0_rd_out[1979] + PIN rw0_rd_out[1980] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.607 129.961 356.625 130.015 ; + END + END rw0_rd_out[1980] + PIN rw0_rd_out[1981] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.787 129.961 356.805 130.015 ; + END + END rw0_rd_out[1981] + PIN rw0_rd_out[1982] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 356.967 129.961 356.985 130.015 ; + END + END rw0_rd_out[1982] + PIN rw0_rd_out[1983] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.147 129.961 357.165 130.015 ; + END + END rw0_rd_out[1983] + PIN rw0_rd_out[1984] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.327 129.961 357.345 130.015 ; + END + END rw0_rd_out[1984] + PIN rw0_rd_out[1985] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.507 129.961 357.525 130.015 ; + END + END rw0_rd_out[1985] + PIN rw0_rd_out[1986] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.687 129.961 357.705 130.015 ; + END + END rw0_rd_out[1986] + PIN rw0_rd_out[1987] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 357.867 129.961 357.885 130.015 ; + END + END rw0_rd_out[1987] + PIN rw0_rd_out[1988] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.047 129.961 358.065 130.015 ; + END + END rw0_rd_out[1988] + PIN rw0_rd_out[1989] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.227 129.961 358.245 130.015 ; + END + END rw0_rd_out[1989] + PIN rw0_rd_out[1990] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.407 129.961 358.425 130.015 ; + END + END rw0_rd_out[1990] + PIN rw0_rd_out[1991] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.587 129.961 358.605 130.015 ; + END + END rw0_rd_out[1991] + PIN rw0_rd_out[1992] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.767 129.961 358.785 130.015 ; + END + END rw0_rd_out[1992] + PIN rw0_rd_out[1993] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 358.947 129.961 358.965 130.015 ; + END + END rw0_rd_out[1993] + PIN rw0_rd_out[1994] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.127 129.961 359.145 130.015 ; + END + END rw0_rd_out[1994] + PIN rw0_rd_out[1995] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.307 129.961 359.325 130.015 ; + END + END rw0_rd_out[1995] + PIN rw0_rd_out[1996] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.487 129.961 359.505 130.015 ; + END + END rw0_rd_out[1996] + PIN rw0_rd_out[1997] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.667 129.961 359.685 130.015 ; + END + END rw0_rd_out[1997] + PIN rw0_rd_out[1998] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 359.847 129.961 359.865 130.015 ; + END + END rw0_rd_out[1998] + PIN rw0_rd_out[1999] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.027 129.961 360.045 130.015 ; + END + END rw0_rd_out[1999] + PIN rw0_rd_out[2000] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.207 129.961 360.225 130.015 ; + END + END rw0_rd_out[2000] + PIN rw0_rd_out[2001] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.387 129.961 360.405 130.015 ; + END + END rw0_rd_out[2001] + PIN rw0_rd_out[2002] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.567 129.961 360.585 130.015 ; + END + END rw0_rd_out[2002] + PIN rw0_rd_out[2003] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.747 129.961 360.765 130.015 ; + END + END rw0_rd_out[2003] + PIN rw0_rd_out[2004] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 360.927 129.961 360.945 130.015 ; + END + END rw0_rd_out[2004] + PIN rw0_rd_out[2005] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.107 129.961 361.125 130.015 ; + END + END rw0_rd_out[2005] + PIN rw0_rd_out[2006] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.287 129.961 361.305 130.015 ; + END + END rw0_rd_out[2006] + PIN rw0_rd_out[2007] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.467 129.961 361.485 130.015 ; + END + END rw0_rd_out[2007] + PIN rw0_rd_out[2008] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.647 129.961 361.665 130.015 ; + END + END rw0_rd_out[2008] + PIN rw0_rd_out[2009] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 361.827 129.961 361.845 130.015 ; + END + END rw0_rd_out[2009] + PIN rw0_rd_out[2010] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.007 129.961 362.025 130.015 ; + END + END rw0_rd_out[2010] + PIN rw0_rd_out[2011] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.187 129.961 362.205 130.015 ; + END + END rw0_rd_out[2011] + PIN rw0_rd_out[2012] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.367 129.961 362.385 130.015 ; + END + END rw0_rd_out[2012] + PIN rw0_rd_out[2013] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.547 129.961 362.565 130.015 ; + END + END rw0_rd_out[2013] + PIN rw0_rd_out[2014] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.727 129.961 362.745 130.015 ; + END + END rw0_rd_out[2014] + PIN rw0_rd_out[2015] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 362.907 129.961 362.925 130.015 ; + END + END rw0_rd_out[2015] + PIN rw0_rd_out[2016] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.087 129.961 363.105 130.015 ; + END + END rw0_rd_out[2016] + PIN rw0_rd_out[2017] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.267 129.961 363.285 130.015 ; + END + END rw0_rd_out[2017] + PIN rw0_rd_out[2018] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.447 129.961 363.465 130.015 ; + END + END rw0_rd_out[2018] + PIN rw0_rd_out[2019] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.627 129.961 363.645 130.015 ; + END + END rw0_rd_out[2019] + PIN rw0_rd_out[2020] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.807 129.961 363.825 130.015 ; + END + END rw0_rd_out[2020] + PIN rw0_rd_out[2021] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 363.987 129.961 364.005 130.015 ; + END + END rw0_rd_out[2021] + PIN rw0_rd_out[2022] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.167 129.961 364.185 130.015 ; + END + END rw0_rd_out[2022] + PIN rw0_rd_out[2023] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.347 129.961 364.365 130.015 ; + END + END rw0_rd_out[2023] + PIN rw0_rd_out[2024] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.527 129.961 364.545 130.015 ; + END + END rw0_rd_out[2024] + PIN rw0_rd_out[2025] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.707 129.961 364.725 130.015 ; + END + END rw0_rd_out[2025] + PIN rw0_rd_out[2026] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 364.887 129.961 364.905 130.015 ; + END + END rw0_rd_out[2026] + PIN rw0_rd_out[2027] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.067 129.961 365.085 130.015 ; + END + END rw0_rd_out[2027] + PIN rw0_rd_out[2028] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.247 129.961 365.265 130.015 ; + END + END rw0_rd_out[2028] + PIN rw0_rd_out[2029] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.427 129.961 365.445 130.015 ; + END + END rw0_rd_out[2029] + PIN rw0_rd_out[2030] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.607 129.961 365.625 130.015 ; + END + END rw0_rd_out[2030] + PIN rw0_rd_out[2031] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.787 129.961 365.805 130.015 ; + END + END rw0_rd_out[2031] + PIN rw0_rd_out[2032] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 365.967 129.961 365.985 130.015 ; + END + END rw0_rd_out[2032] + PIN rw0_rd_out[2033] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.147 129.961 366.165 130.015 ; + END + END rw0_rd_out[2033] + PIN rw0_rd_out[2034] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.327 129.961 366.345 130.015 ; + END + END rw0_rd_out[2034] + PIN rw0_rd_out[2035] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.507 129.961 366.525 130.015 ; + END + END rw0_rd_out[2035] + PIN rw0_rd_out[2036] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.687 129.961 366.705 130.015 ; + END + END rw0_rd_out[2036] + PIN rw0_rd_out[2037] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 366.867 129.961 366.885 130.015 ; + END + END rw0_rd_out[2037] + PIN rw0_rd_out[2038] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.047 129.961 367.065 130.015 ; + END + END rw0_rd_out[2038] + PIN rw0_rd_out[2039] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.227 129.961 367.245 130.015 ; + END + END rw0_rd_out[2039] + PIN rw0_rd_out[2040] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.407 129.961 367.425 130.015 ; + END + END rw0_rd_out[2040] + PIN rw0_rd_out[2041] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.587 129.961 367.605 130.015 ; + END + END rw0_rd_out[2041] + PIN rw0_rd_out[2042] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.767 129.961 367.785 130.015 ; + END + END rw0_rd_out[2042] + PIN rw0_rd_out[2043] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 367.947 129.961 367.965 130.015 ; + END + END rw0_rd_out[2043] + PIN rw0_rd_out[2044] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.127 129.961 368.145 130.015 ; + END + END rw0_rd_out[2044] + PIN rw0_rd_out[2045] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.307 129.961 368.325 130.015 ; + END + END rw0_rd_out[2045] + PIN rw0_rd_out[2046] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.487 129.961 368.505 130.015 ; + END + END rw0_rd_out[2046] + PIN rw0_rd_out[2047] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.667 129.961 368.685 130.015 ; + END + END rw0_rd_out[2047] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.580 0.072 98.604 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.676 0.072 98.700 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.772 0.072 98.796 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.868 0.072 98.892 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.580 416.048 98.604 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.676 416.048 98.700 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 415.976 98.772 416.048 98.796 ; + END + END rw0_addr_in[6] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 368.847 129.961 368.865 130.015 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 369.027 129.961 369.045 130.015 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 369.207 129.961 369.225 130.015 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 415.832 0.336 ; + RECT 0.216 1.008 415.832 1.104 ; + RECT 0.216 1.776 415.832 1.872 ; + RECT 0.216 2.544 415.832 2.640 ; + RECT 0.216 3.312 415.832 3.408 ; + RECT 0.216 4.080 415.832 4.176 ; + RECT 0.216 4.848 415.832 4.944 ; + RECT 0.216 5.616 415.832 5.712 ; + RECT 0.216 6.384 415.832 6.480 ; + RECT 0.216 7.152 415.832 7.248 ; + RECT 0.216 7.920 415.832 8.016 ; + RECT 0.216 8.688 415.832 8.784 ; + RECT 0.216 9.456 415.832 9.552 ; + RECT 0.216 10.224 415.832 10.320 ; + RECT 0.216 10.992 415.832 11.088 ; + RECT 0.216 11.760 415.832 11.856 ; + RECT 0.216 12.528 415.832 12.624 ; + RECT 0.216 13.296 415.832 13.392 ; + RECT 0.216 14.064 415.832 14.160 ; + RECT 0.216 14.832 415.832 14.928 ; + RECT 0.216 15.600 415.832 15.696 ; + RECT 0.216 16.368 415.832 16.464 ; + RECT 0.216 17.136 415.832 17.232 ; + RECT 0.216 17.904 415.832 18.000 ; + RECT 0.216 18.672 415.832 18.768 ; + RECT 0.216 19.440 415.832 19.536 ; + RECT 0.216 20.208 415.832 20.304 ; + RECT 0.216 20.976 415.832 21.072 ; + RECT 0.216 21.744 415.832 21.840 ; + RECT 0.216 22.512 415.832 22.608 ; + RECT 0.216 23.280 415.832 23.376 ; + RECT 0.216 24.048 415.832 24.144 ; + RECT 0.216 24.816 415.832 24.912 ; + RECT 0.216 25.584 415.832 25.680 ; + RECT 0.216 26.352 415.832 26.448 ; + RECT 0.216 27.120 415.832 27.216 ; + RECT 0.216 27.888 415.832 27.984 ; + RECT 0.216 28.656 415.832 28.752 ; + RECT 0.216 29.424 415.832 29.520 ; + RECT 0.216 30.192 415.832 30.288 ; + RECT 0.216 30.960 415.832 31.056 ; + RECT 0.216 31.728 415.832 31.824 ; + RECT 0.216 32.496 415.832 32.592 ; + RECT 0.216 33.264 415.832 33.360 ; + RECT 0.216 34.032 415.832 34.128 ; + RECT 0.216 34.800 415.832 34.896 ; + RECT 0.216 35.568 415.832 35.664 ; + RECT 0.216 36.336 415.832 36.432 ; + RECT 0.216 37.104 415.832 37.200 ; + RECT 0.216 37.872 415.832 37.968 ; + RECT 0.216 38.640 415.832 38.736 ; + RECT 0.216 39.408 415.832 39.504 ; + RECT 0.216 40.176 415.832 40.272 ; + RECT 0.216 40.944 415.832 41.040 ; + RECT 0.216 41.712 415.832 41.808 ; + RECT 0.216 42.480 415.832 42.576 ; + RECT 0.216 43.248 415.832 43.344 ; + RECT 0.216 44.016 415.832 44.112 ; + RECT 0.216 44.784 415.832 44.880 ; + RECT 0.216 45.552 415.832 45.648 ; + RECT 0.216 46.320 415.832 46.416 ; + RECT 0.216 47.088 415.832 47.184 ; + RECT 0.216 47.856 415.832 47.952 ; + RECT 0.216 48.624 415.832 48.720 ; + RECT 0.216 49.392 415.832 49.488 ; + RECT 0.216 50.160 415.832 50.256 ; + RECT 0.216 50.928 415.832 51.024 ; + RECT 0.216 51.696 415.832 51.792 ; + RECT 0.216 52.464 415.832 52.560 ; + RECT 0.216 53.232 415.832 53.328 ; + RECT 0.216 54.000 415.832 54.096 ; + RECT 0.216 54.768 415.832 54.864 ; + RECT 0.216 55.536 415.832 55.632 ; + RECT 0.216 56.304 415.832 56.400 ; + RECT 0.216 57.072 415.832 57.168 ; + RECT 0.216 57.840 415.832 57.936 ; + RECT 0.216 58.608 415.832 58.704 ; + RECT 0.216 59.376 415.832 59.472 ; + RECT 0.216 60.144 415.832 60.240 ; + RECT 0.216 60.912 415.832 61.008 ; + RECT 0.216 61.680 415.832 61.776 ; + RECT 0.216 62.448 415.832 62.544 ; + RECT 0.216 63.216 415.832 63.312 ; + RECT 0.216 63.984 415.832 64.080 ; + RECT 0.216 64.752 415.832 64.848 ; + RECT 0.216 65.520 415.832 65.616 ; + RECT 0.216 66.288 415.832 66.384 ; + RECT 0.216 67.056 415.832 67.152 ; + RECT 0.216 67.824 415.832 67.920 ; + RECT 0.216 68.592 415.832 68.688 ; + RECT 0.216 69.360 415.832 69.456 ; + RECT 0.216 70.128 415.832 70.224 ; + RECT 0.216 70.896 415.832 70.992 ; + RECT 0.216 71.664 415.832 71.760 ; + RECT 0.216 72.432 415.832 72.528 ; + RECT 0.216 73.200 415.832 73.296 ; + RECT 0.216 73.968 415.832 74.064 ; + RECT 0.216 74.736 415.832 74.832 ; + RECT 0.216 75.504 415.832 75.600 ; + RECT 0.216 76.272 415.832 76.368 ; + RECT 0.216 77.040 415.832 77.136 ; + RECT 0.216 77.808 415.832 77.904 ; + RECT 0.216 78.576 415.832 78.672 ; + RECT 0.216 79.344 415.832 79.440 ; + RECT 0.216 80.112 415.832 80.208 ; + RECT 0.216 80.880 415.832 80.976 ; + RECT 0.216 81.648 415.832 81.744 ; + RECT 0.216 82.416 415.832 82.512 ; + RECT 0.216 83.184 415.832 83.280 ; + RECT 0.216 83.952 415.832 84.048 ; + RECT 0.216 84.720 415.832 84.816 ; + RECT 0.216 85.488 415.832 85.584 ; + RECT 0.216 86.256 415.832 86.352 ; + RECT 0.216 87.024 415.832 87.120 ; + RECT 0.216 87.792 415.832 87.888 ; + RECT 0.216 88.560 415.832 88.656 ; + RECT 0.216 89.328 415.832 89.424 ; + RECT 0.216 90.096 415.832 90.192 ; + RECT 0.216 90.864 415.832 90.960 ; + RECT 0.216 91.632 415.832 91.728 ; + RECT 0.216 92.400 415.832 92.496 ; + RECT 0.216 93.168 415.832 93.264 ; + RECT 0.216 93.936 415.832 94.032 ; + RECT 0.216 94.704 415.832 94.800 ; + RECT 0.216 95.472 415.832 95.568 ; + RECT 0.216 96.240 415.832 96.336 ; + RECT 0.216 97.008 415.832 97.104 ; + RECT 0.216 97.776 415.832 97.872 ; + RECT 0.216 98.544 415.832 98.640 ; + RECT 0.216 99.312 415.832 99.408 ; + RECT 0.216 100.080 415.832 100.176 ; + RECT 0.216 100.848 415.832 100.944 ; + RECT 0.216 101.616 415.832 101.712 ; + RECT 0.216 102.384 415.832 102.480 ; + RECT 0.216 103.152 415.832 103.248 ; + RECT 0.216 103.920 415.832 104.016 ; + RECT 0.216 104.688 415.832 104.784 ; + RECT 0.216 105.456 415.832 105.552 ; + RECT 0.216 106.224 415.832 106.320 ; + RECT 0.216 106.992 415.832 107.088 ; + RECT 0.216 107.760 415.832 107.856 ; + RECT 0.216 108.528 415.832 108.624 ; + RECT 0.216 109.296 415.832 109.392 ; + RECT 0.216 110.064 415.832 110.160 ; + RECT 0.216 110.832 415.832 110.928 ; + RECT 0.216 111.600 415.832 111.696 ; + RECT 0.216 112.368 415.832 112.464 ; + RECT 0.216 113.136 415.832 113.232 ; + RECT 0.216 113.904 415.832 114.000 ; + RECT 0.216 114.672 415.832 114.768 ; + RECT 0.216 115.440 415.832 115.536 ; + RECT 0.216 116.208 415.832 116.304 ; + RECT 0.216 116.976 415.832 117.072 ; + RECT 0.216 117.744 415.832 117.840 ; + RECT 0.216 118.512 415.832 118.608 ; + RECT 0.216 119.280 415.832 119.376 ; + RECT 0.216 120.048 415.832 120.144 ; + RECT 0.216 120.816 415.832 120.912 ; + RECT 0.216 121.584 415.832 121.680 ; + RECT 0.216 122.352 415.832 122.448 ; + RECT 0.216 123.120 415.832 123.216 ; + RECT 0.216 123.888 415.832 123.984 ; + RECT 0.216 124.656 415.832 124.752 ; + RECT 0.216 125.424 415.832 125.520 ; + RECT 0.216 126.192 415.832 126.288 ; + RECT 0.216 126.960 415.832 127.056 ; + RECT 0.216 127.728 415.832 127.824 ; + RECT 0.216 128.496 415.832 128.592 ; + RECT 0.216 129.264 415.832 129.360 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 415.832 0.336 ; + RECT 0.216 1.008 415.832 1.104 ; + RECT 0.216 1.776 415.832 1.872 ; + RECT 0.216 2.544 415.832 2.640 ; + RECT 0.216 3.312 415.832 3.408 ; + RECT 0.216 4.080 415.832 4.176 ; + RECT 0.216 4.848 415.832 4.944 ; + RECT 0.216 5.616 415.832 5.712 ; + RECT 0.216 6.384 415.832 6.480 ; + RECT 0.216 7.152 415.832 7.248 ; + RECT 0.216 7.920 415.832 8.016 ; + RECT 0.216 8.688 415.832 8.784 ; + RECT 0.216 9.456 415.832 9.552 ; + RECT 0.216 10.224 415.832 10.320 ; + RECT 0.216 10.992 415.832 11.088 ; + RECT 0.216 11.760 415.832 11.856 ; + RECT 0.216 12.528 415.832 12.624 ; + RECT 0.216 13.296 415.832 13.392 ; + RECT 0.216 14.064 415.832 14.160 ; + RECT 0.216 14.832 415.832 14.928 ; + RECT 0.216 15.600 415.832 15.696 ; + RECT 0.216 16.368 415.832 16.464 ; + RECT 0.216 17.136 415.832 17.232 ; + RECT 0.216 17.904 415.832 18.000 ; + RECT 0.216 18.672 415.832 18.768 ; + RECT 0.216 19.440 415.832 19.536 ; + RECT 0.216 20.208 415.832 20.304 ; + RECT 0.216 20.976 415.832 21.072 ; + RECT 0.216 21.744 415.832 21.840 ; + RECT 0.216 22.512 415.832 22.608 ; + RECT 0.216 23.280 415.832 23.376 ; + RECT 0.216 24.048 415.832 24.144 ; + RECT 0.216 24.816 415.832 24.912 ; + RECT 0.216 25.584 415.832 25.680 ; + RECT 0.216 26.352 415.832 26.448 ; + RECT 0.216 27.120 415.832 27.216 ; + RECT 0.216 27.888 415.832 27.984 ; + RECT 0.216 28.656 415.832 28.752 ; + RECT 0.216 29.424 415.832 29.520 ; + RECT 0.216 30.192 415.832 30.288 ; + RECT 0.216 30.960 415.832 31.056 ; + RECT 0.216 31.728 415.832 31.824 ; + RECT 0.216 32.496 415.832 32.592 ; + RECT 0.216 33.264 415.832 33.360 ; + RECT 0.216 34.032 415.832 34.128 ; + RECT 0.216 34.800 415.832 34.896 ; + RECT 0.216 35.568 415.832 35.664 ; + RECT 0.216 36.336 415.832 36.432 ; + RECT 0.216 37.104 415.832 37.200 ; + RECT 0.216 37.872 415.832 37.968 ; + RECT 0.216 38.640 415.832 38.736 ; + RECT 0.216 39.408 415.832 39.504 ; + RECT 0.216 40.176 415.832 40.272 ; + RECT 0.216 40.944 415.832 41.040 ; + RECT 0.216 41.712 415.832 41.808 ; + RECT 0.216 42.480 415.832 42.576 ; + RECT 0.216 43.248 415.832 43.344 ; + RECT 0.216 44.016 415.832 44.112 ; + RECT 0.216 44.784 415.832 44.880 ; + RECT 0.216 45.552 415.832 45.648 ; + RECT 0.216 46.320 415.832 46.416 ; + RECT 0.216 47.088 415.832 47.184 ; + RECT 0.216 47.856 415.832 47.952 ; + RECT 0.216 48.624 415.832 48.720 ; + RECT 0.216 49.392 415.832 49.488 ; + RECT 0.216 50.160 415.832 50.256 ; + RECT 0.216 50.928 415.832 51.024 ; + RECT 0.216 51.696 415.832 51.792 ; + RECT 0.216 52.464 415.832 52.560 ; + RECT 0.216 53.232 415.832 53.328 ; + RECT 0.216 54.000 415.832 54.096 ; + RECT 0.216 54.768 415.832 54.864 ; + RECT 0.216 55.536 415.832 55.632 ; + RECT 0.216 56.304 415.832 56.400 ; + RECT 0.216 57.072 415.832 57.168 ; + RECT 0.216 57.840 415.832 57.936 ; + RECT 0.216 58.608 415.832 58.704 ; + RECT 0.216 59.376 415.832 59.472 ; + RECT 0.216 60.144 415.832 60.240 ; + RECT 0.216 60.912 415.832 61.008 ; + RECT 0.216 61.680 415.832 61.776 ; + RECT 0.216 62.448 415.832 62.544 ; + RECT 0.216 63.216 415.832 63.312 ; + RECT 0.216 63.984 415.832 64.080 ; + RECT 0.216 64.752 415.832 64.848 ; + RECT 0.216 65.520 415.832 65.616 ; + RECT 0.216 66.288 415.832 66.384 ; + RECT 0.216 67.056 415.832 67.152 ; + RECT 0.216 67.824 415.832 67.920 ; + RECT 0.216 68.592 415.832 68.688 ; + RECT 0.216 69.360 415.832 69.456 ; + RECT 0.216 70.128 415.832 70.224 ; + RECT 0.216 70.896 415.832 70.992 ; + RECT 0.216 71.664 415.832 71.760 ; + RECT 0.216 72.432 415.832 72.528 ; + RECT 0.216 73.200 415.832 73.296 ; + RECT 0.216 73.968 415.832 74.064 ; + RECT 0.216 74.736 415.832 74.832 ; + RECT 0.216 75.504 415.832 75.600 ; + RECT 0.216 76.272 415.832 76.368 ; + RECT 0.216 77.040 415.832 77.136 ; + RECT 0.216 77.808 415.832 77.904 ; + RECT 0.216 78.576 415.832 78.672 ; + RECT 0.216 79.344 415.832 79.440 ; + RECT 0.216 80.112 415.832 80.208 ; + RECT 0.216 80.880 415.832 80.976 ; + RECT 0.216 81.648 415.832 81.744 ; + RECT 0.216 82.416 415.832 82.512 ; + RECT 0.216 83.184 415.832 83.280 ; + RECT 0.216 83.952 415.832 84.048 ; + RECT 0.216 84.720 415.832 84.816 ; + RECT 0.216 85.488 415.832 85.584 ; + RECT 0.216 86.256 415.832 86.352 ; + RECT 0.216 87.024 415.832 87.120 ; + RECT 0.216 87.792 415.832 87.888 ; + RECT 0.216 88.560 415.832 88.656 ; + RECT 0.216 89.328 415.832 89.424 ; + RECT 0.216 90.096 415.832 90.192 ; + RECT 0.216 90.864 415.832 90.960 ; + RECT 0.216 91.632 415.832 91.728 ; + RECT 0.216 92.400 415.832 92.496 ; + RECT 0.216 93.168 415.832 93.264 ; + RECT 0.216 93.936 415.832 94.032 ; + RECT 0.216 94.704 415.832 94.800 ; + RECT 0.216 95.472 415.832 95.568 ; + RECT 0.216 96.240 415.832 96.336 ; + RECT 0.216 97.008 415.832 97.104 ; + RECT 0.216 97.776 415.832 97.872 ; + RECT 0.216 98.544 415.832 98.640 ; + RECT 0.216 99.312 415.832 99.408 ; + RECT 0.216 100.080 415.832 100.176 ; + RECT 0.216 100.848 415.832 100.944 ; + RECT 0.216 101.616 415.832 101.712 ; + RECT 0.216 102.384 415.832 102.480 ; + RECT 0.216 103.152 415.832 103.248 ; + RECT 0.216 103.920 415.832 104.016 ; + RECT 0.216 104.688 415.832 104.784 ; + RECT 0.216 105.456 415.832 105.552 ; + RECT 0.216 106.224 415.832 106.320 ; + RECT 0.216 106.992 415.832 107.088 ; + RECT 0.216 107.760 415.832 107.856 ; + RECT 0.216 108.528 415.832 108.624 ; + RECT 0.216 109.296 415.832 109.392 ; + RECT 0.216 110.064 415.832 110.160 ; + RECT 0.216 110.832 415.832 110.928 ; + RECT 0.216 111.600 415.832 111.696 ; + RECT 0.216 112.368 415.832 112.464 ; + RECT 0.216 113.136 415.832 113.232 ; + RECT 0.216 113.904 415.832 114.000 ; + RECT 0.216 114.672 415.832 114.768 ; + RECT 0.216 115.440 415.832 115.536 ; + RECT 0.216 116.208 415.832 116.304 ; + RECT 0.216 116.976 415.832 117.072 ; + RECT 0.216 117.744 415.832 117.840 ; + RECT 0.216 118.512 415.832 118.608 ; + RECT 0.216 119.280 415.832 119.376 ; + RECT 0.216 120.048 415.832 120.144 ; + RECT 0.216 120.816 415.832 120.912 ; + RECT 0.216 121.584 415.832 121.680 ; + RECT 0.216 122.352 415.832 122.448 ; + RECT 0.216 123.120 415.832 123.216 ; + RECT 0.216 123.888 415.832 123.984 ; + RECT 0.216 124.656 415.832 124.752 ; + RECT 0.216 125.424 415.832 125.520 ; + RECT 0.216 126.192 415.832 126.288 ; + RECT 0.216 126.960 415.832 127.056 ; + RECT 0.216 127.728 415.832 127.824 ; + RECT 0.216 128.496 415.832 128.592 ; + RECT 0.216 129.264 415.832 129.360 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 416.048 130.015 ; + LAYER M2 ; + RECT 0 0 416.048 130.015 ; + LAYER M3 ; + RECT 0 0 416.048 130.015 ; + LAYER M4 ; + RECT 0 0 416.048 130.015 ; + END +END fakeram_2048x128_1rw + +END LIBRARY diff --git a/designs/asap7/coralnpu/sram/lef/fakeram_512x128_1rw.lef b/designs/asap7/coralnpu/sram/lef/fakeram_512x128_1rw.lef new file mode 100644 index 0000000..94c2bc2 --- /dev/null +++ b/designs/asap7/coralnpu/sram/lef/fakeram_512x128_1rw.lef @@ -0,0 +1,14060 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_512x128_1rw + FOREIGN fakeram_512x128_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 104.012 BY 43.339 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.420 0.072 0.444 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.148 0.072 2.172 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.012 0.072 3.036 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.452 0.072 4.476 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.468 0.072 6.492 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.908 0.072 7.932 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.772 0.072 8.796 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.060 0.072 9.084 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END rw0_wmask_in[63] + PIN rw0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END rw0_wmask_in[64] + PIN rw0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END rw0_wmask_in[65] + PIN rw0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END rw0_wmask_in[66] + PIN rw0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.924 0.072 9.948 ; + END + END rw0_wmask_in[67] + PIN rw0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END rw0_wmask_in[68] + PIN rw0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END rw0_wmask_in[69] + PIN rw0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END rw0_wmask_in[70] + PIN rw0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.500 0.072 10.524 ; + END + END rw0_wmask_in[71] + PIN rw0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END rw0_wmask_in[72] + PIN rw0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.788 0.072 10.812 ; + END + END rw0_wmask_in[73] + PIN rw0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END rw0_wmask_in[74] + PIN rw0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END rw0_wmask_in[75] + PIN rw0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END rw0_wmask_in[76] + PIN rw0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END rw0_wmask_in[77] + PIN rw0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END rw0_wmask_in[78] + PIN rw0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.652 0.072 11.676 ; + END + END rw0_wmask_in[79] + PIN rw0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END rw0_wmask_in[80] + PIN rw0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END rw0_wmask_in[81] + PIN rw0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END rw0_wmask_in[82] + PIN rw0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.228 0.072 12.252 ; + END + END rw0_wmask_in[83] + PIN rw0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END rw0_wmask_in[84] + PIN rw0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END rw0_wmask_in[85] + PIN rw0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END rw0_wmask_in[86] + PIN rw0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END rw0_wmask_in[87] + PIN rw0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END rw0_wmask_in[88] + PIN rw0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END rw0_wmask_in[89] + PIN rw0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END rw0_wmask_in[90] + PIN rw0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END rw0_wmask_in[91] + PIN rw0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END rw0_wmask_in[92] + PIN rw0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END rw0_wmask_in[93] + PIN rw0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END rw0_wmask_in[94] + PIN rw0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END rw0_wmask_in[95] + PIN rw0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END rw0_wmask_in[96] + PIN rw0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.244 0.072 14.268 ; + END + END rw0_wmask_in[97] + PIN rw0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END rw0_wmask_in[98] + PIN rw0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END rw0_wmask_in[99] + PIN rw0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END rw0_wmask_in[100] + PIN rw0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END rw0_wmask_in[101] + PIN rw0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END rw0_wmask_in[102] + PIN rw0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.108 0.072 15.132 ; + END + END rw0_wmask_in[103] + PIN rw0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END rw0_wmask_in[104] + PIN rw0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END rw0_wmask_in[105] + PIN rw0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END rw0_wmask_in[106] + PIN rw0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.684 0.072 15.708 ; + END + END rw0_wmask_in[107] + PIN rw0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END rw0_wmask_in[108] + PIN rw0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.972 0.072 15.996 ; + END + END rw0_wmask_in[109] + PIN rw0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END rw0_wmask_in[110] + PIN rw0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END rw0_wmask_in[111] + PIN rw0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END rw0_wmask_in[112] + PIN rw0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.548 0.072 16.572 ; + END + END rw0_wmask_in[113] + PIN rw0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END rw0_wmask_in[114] + PIN rw0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END rw0_wmask_in[115] + PIN rw0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END rw0_wmask_in[116] + PIN rw0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END rw0_wmask_in[117] + PIN rw0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END rw0_wmask_in[118] + PIN rw0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END rw0_wmask_in[119] + PIN rw0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END rw0_wmask_in[120] + PIN rw0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.700 0.072 17.724 ; + END + END rw0_wmask_in[121] + PIN rw0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END rw0_wmask_in[122] + PIN rw0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END rw0_wmask_in[123] + PIN rw0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END rw0_wmask_in[124] + PIN rw0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END rw0_wmask_in[125] + PIN rw0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END rw0_wmask_in[126] + PIN rw0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.564 0.072 18.588 ; + END + END rw0_wmask_in[127] + PIN rw0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.276 104.012 0.300 ; + END + END rw0_wmask_in[128] + PIN rw0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.420 104.012 0.444 ; + END + END rw0_wmask_in[129] + PIN rw0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.564 104.012 0.588 ; + END + END rw0_wmask_in[130] + PIN rw0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.708 104.012 0.732 ; + END + END rw0_wmask_in[131] + PIN rw0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.852 104.012 0.876 ; + END + END rw0_wmask_in[132] + PIN rw0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.996 104.012 1.020 ; + END + END rw0_wmask_in[133] + PIN rw0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.140 104.012 1.164 ; + END + END rw0_wmask_in[134] + PIN rw0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.284 104.012 1.308 ; + END + END rw0_wmask_in[135] + PIN rw0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.428 104.012 1.452 ; + END + END rw0_wmask_in[136] + PIN rw0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.572 104.012 1.596 ; + END + END rw0_wmask_in[137] + PIN rw0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.716 104.012 1.740 ; + END + END rw0_wmask_in[138] + PIN rw0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.860 104.012 1.884 ; + END + END rw0_wmask_in[139] + PIN rw0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.004 104.012 2.028 ; + END + END rw0_wmask_in[140] + PIN rw0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.148 104.012 2.172 ; + END + END rw0_wmask_in[141] + PIN rw0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.292 104.012 2.316 ; + END + END rw0_wmask_in[142] + PIN rw0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.436 104.012 2.460 ; + END + END rw0_wmask_in[143] + PIN rw0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.580 104.012 2.604 ; + END + END rw0_wmask_in[144] + PIN rw0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.724 104.012 2.748 ; + END + END rw0_wmask_in[145] + PIN rw0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.868 104.012 2.892 ; + END + END rw0_wmask_in[146] + PIN rw0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.012 104.012 3.036 ; + END + END rw0_wmask_in[147] + PIN rw0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.156 104.012 3.180 ; + END + END rw0_wmask_in[148] + PIN rw0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.300 104.012 3.324 ; + END + END rw0_wmask_in[149] + PIN rw0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.444 104.012 3.468 ; + END + END rw0_wmask_in[150] + PIN rw0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.588 104.012 3.612 ; + END + END rw0_wmask_in[151] + PIN rw0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.732 104.012 3.756 ; + END + END rw0_wmask_in[152] + PIN rw0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.876 104.012 3.900 ; + END + END rw0_wmask_in[153] + PIN rw0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.020 104.012 4.044 ; + END + END rw0_wmask_in[154] + PIN rw0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.164 104.012 4.188 ; + END + END rw0_wmask_in[155] + PIN rw0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.308 104.012 4.332 ; + END + END rw0_wmask_in[156] + PIN rw0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.452 104.012 4.476 ; + END + END rw0_wmask_in[157] + PIN rw0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.596 104.012 4.620 ; + END + END rw0_wmask_in[158] + PIN rw0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.740 104.012 4.764 ; + END + END rw0_wmask_in[159] + PIN rw0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.884 104.012 4.908 ; + END + END rw0_wmask_in[160] + PIN rw0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.028 104.012 5.052 ; + END + END rw0_wmask_in[161] + PIN rw0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.172 104.012 5.196 ; + END + END rw0_wmask_in[162] + PIN rw0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.316 104.012 5.340 ; + END + END rw0_wmask_in[163] + PIN rw0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.460 104.012 5.484 ; + END + END rw0_wmask_in[164] + PIN rw0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.604 104.012 5.628 ; + END + END rw0_wmask_in[165] + PIN rw0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.748 104.012 5.772 ; + END + END rw0_wmask_in[166] + PIN rw0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.892 104.012 5.916 ; + END + END rw0_wmask_in[167] + PIN rw0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.036 104.012 6.060 ; + END + END rw0_wmask_in[168] + PIN rw0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.180 104.012 6.204 ; + END + END rw0_wmask_in[169] + PIN rw0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.324 104.012 6.348 ; + END + END rw0_wmask_in[170] + PIN rw0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.468 104.012 6.492 ; + END + END rw0_wmask_in[171] + PIN rw0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.612 104.012 6.636 ; + END + END rw0_wmask_in[172] + PIN rw0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.756 104.012 6.780 ; + END + END rw0_wmask_in[173] + PIN rw0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.900 104.012 6.924 ; + END + END rw0_wmask_in[174] + PIN rw0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.044 104.012 7.068 ; + END + END rw0_wmask_in[175] + PIN rw0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.188 104.012 7.212 ; + END + END rw0_wmask_in[176] + PIN rw0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.332 104.012 7.356 ; + END + END rw0_wmask_in[177] + PIN rw0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.476 104.012 7.500 ; + END + END rw0_wmask_in[178] + PIN rw0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.620 104.012 7.644 ; + END + END rw0_wmask_in[179] + PIN rw0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.764 104.012 7.788 ; + END + END rw0_wmask_in[180] + PIN rw0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.908 104.012 7.932 ; + END + END rw0_wmask_in[181] + PIN rw0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.052 104.012 8.076 ; + END + END rw0_wmask_in[182] + PIN rw0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.196 104.012 8.220 ; + END + END rw0_wmask_in[183] + PIN rw0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.340 104.012 8.364 ; + END + END rw0_wmask_in[184] + PIN rw0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.484 104.012 8.508 ; + END + END rw0_wmask_in[185] + PIN rw0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.628 104.012 8.652 ; + END + END rw0_wmask_in[186] + PIN rw0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.772 104.012 8.796 ; + END + END rw0_wmask_in[187] + PIN rw0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.916 104.012 8.940 ; + END + END rw0_wmask_in[188] + PIN rw0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.060 104.012 9.084 ; + END + END rw0_wmask_in[189] + PIN rw0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.204 104.012 9.228 ; + END + END rw0_wmask_in[190] + PIN rw0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.348 104.012 9.372 ; + END + END rw0_wmask_in[191] + PIN rw0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.492 104.012 9.516 ; + END + END rw0_wmask_in[192] + PIN rw0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.636 104.012 9.660 ; + END + END rw0_wmask_in[193] + PIN rw0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.780 104.012 9.804 ; + END + END rw0_wmask_in[194] + PIN rw0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.924 104.012 9.948 ; + END + END rw0_wmask_in[195] + PIN rw0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.068 104.012 10.092 ; + END + END rw0_wmask_in[196] + PIN rw0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.212 104.012 10.236 ; + END + END rw0_wmask_in[197] + PIN rw0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.356 104.012 10.380 ; + END + END rw0_wmask_in[198] + PIN rw0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.500 104.012 10.524 ; + END + END rw0_wmask_in[199] + PIN rw0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.644 104.012 10.668 ; + END + END rw0_wmask_in[200] + PIN rw0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.788 104.012 10.812 ; + END + END rw0_wmask_in[201] + PIN rw0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.932 104.012 10.956 ; + END + END rw0_wmask_in[202] + PIN rw0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.076 104.012 11.100 ; + END + END rw0_wmask_in[203] + PIN rw0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.220 104.012 11.244 ; + END + END rw0_wmask_in[204] + PIN rw0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.364 104.012 11.388 ; + END + END rw0_wmask_in[205] + PIN rw0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.508 104.012 11.532 ; + END + END rw0_wmask_in[206] + PIN rw0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.652 104.012 11.676 ; + END + END rw0_wmask_in[207] + PIN rw0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.796 104.012 11.820 ; + END + END rw0_wmask_in[208] + PIN rw0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.940 104.012 11.964 ; + END + END rw0_wmask_in[209] + PIN rw0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.084 104.012 12.108 ; + END + END rw0_wmask_in[210] + PIN rw0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.228 104.012 12.252 ; + END + END rw0_wmask_in[211] + PIN rw0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.372 104.012 12.396 ; + END + END rw0_wmask_in[212] + PIN rw0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.516 104.012 12.540 ; + END + END rw0_wmask_in[213] + PIN rw0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.660 104.012 12.684 ; + END + END rw0_wmask_in[214] + PIN rw0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.804 104.012 12.828 ; + END + END rw0_wmask_in[215] + PIN rw0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.948 104.012 12.972 ; + END + END rw0_wmask_in[216] + PIN rw0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.092 104.012 13.116 ; + END + END rw0_wmask_in[217] + PIN rw0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.236 104.012 13.260 ; + END + END rw0_wmask_in[218] + PIN rw0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.380 104.012 13.404 ; + END + END rw0_wmask_in[219] + PIN rw0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.524 104.012 13.548 ; + END + END rw0_wmask_in[220] + PIN rw0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.668 104.012 13.692 ; + END + END rw0_wmask_in[221] + PIN rw0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.812 104.012 13.836 ; + END + END rw0_wmask_in[222] + PIN rw0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.956 104.012 13.980 ; + END + END rw0_wmask_in[223] + PIN rw0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.100 104.012 14.124 ; + END + END rw0_wmask_in[224] + PIN rw0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.244 104.012 14.268 ; + END + END rw0_wmask_in[225] + PIN rw0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.388 104.012 14.412 ; + END + END rw0_wmask_in[226] + PIN rw0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.532 104.012 14.556 ; + END + END rw0_wmask_in[227] + PIN rw0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.676 104.012 14.700 ; + END + END rw0_wmask_in[228] + PIN rw0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.820 104.012 14.844 ; + END + END rw0_wmask_in[229] + PIN rw0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.964 104.012 14.988 ; + END + END rw0_wmask_in[230] + PIN rw0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.108 104.012 15.132 ; + END + END rw0_wmask_in[231] + PIN rw0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.252 104.012 15.276 ; + END + END rw0_wmask_in[232] + PIN rw0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.396 104.012 15.420 ; + END + END rw0_wmask_in[233] + PIN rw0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.540 104.012 15.564 ; + END + END rw0_wmask_in[234] + PIN rw0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.684 104.012 15.708 ; + END + END rw0_wmask_in[235] + PIN rw0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.828 104.012 15.852 ; + END + END rw0_wmask_in[236] + PIN rw0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.972 104.012 15.996 ; + END + END rw0_wmask_in[237] + PIN rw0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.116 104.012 16.140 ; + END + END rw0_wmask_in[238] + PIN rw0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.260 104.012 16.284 ; + END + END rw0_wmask_in[239] + PIN rw0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.404 104.012 16.428 ; + END + END rw0_wmask_in[240] + PIN rw0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.548 104.012 16.572 ; + END + END rw0_wmask_in[241] + PIN rw0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.692 104.012 16.716 ; + END + END rw0_wmask_in[242] + PIN rw0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.836 104.012 16.860 ; + END + END rw0_wmask_in[243] + PIN rw0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.980 104.012 17.004 ; + END + END rw0_wmask_in[244] + PIN rw0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.124 104.012 17.148 ; + END + END rw0_wmask_in[245] + PIN rw0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.268 104.012 17.292 ; + END + END rw0_wmask_in[246] + PIN rw0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.412 104.012 17.436 ; + END + END rw0_wmask_in[247] + PIN rw0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.556 104.012 17.580 ; + END + END rw0_wmask_in[248] + PIN rw0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.700 104.012 17.724 ; + END + END rw0_wmask_in[249] + PIN rw0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.844 104.012 17.868 ; + END + END rw0_wmask_in[250] + PIN rw0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.988 104.012 18.012 ; + END + END rw0_wmask_in[251] + PIN rw0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.132 104.012 18.156 ; + END + END rw0_wmask_in[252] + PIN rw0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.276 104.012 18.300 ; + END + END rw0_wmask_in[253] + PIN rw0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.420 104.012 18.444 ; + END + END rw0_wmask_in[254] + PIN rw0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.564 104.012 18.588 ; + END + END rw0_wmask_in[255] + PIN rw0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 43.285 0.225 43.339 ; + END + END rw0_wmask_in[256] + PIN rw0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 43.285 0.405 43.339 ; + END + END rw0_wmask_in[257] + PIN rw0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 43.285 0.585 43.339 ; + END + END rw0_wmask_in[258] + PIN rw0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 43.285 0.765 43.339 ; + END + END rw0_wmask_in[259] + PIN rw0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 43.285 0.945 43.339 ; + END + END rw0_wmask_in[260] + PIN rw0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 43.285 1.125 43.339 ; + END + END rw0_wmask_in[261] + PIN rw0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 43.285 1.305 43.339 ; + END + END rw0_wmask_in[262] + PIN rw0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 43.285 1.485 43.339 ; + END + END rw0_wmask_in[263] + PIN rw0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 43.285 1.665 43.339 ; + END + END rw0_wmask_in[264] + PIN rw0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 43.285 1.845 43.339 ; + END + END rw0_wmask_in[265] + PIN rw0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 43.285 2.025 43.339 ; + END + END rw0_wmask_in[266] + PIN rw0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 43.285 2.205 43.339 ; + END + END rw0_wmask_in[267] + PIN rw0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 43.285 2.385 43.339 ; + END + END rw0_wmask_in[268] + PIN rw0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 43.285 2.565 43.339 ; + END + END rw0_wmask_in[269] + PIN rw0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 43.285 2.745 43.339 ; + END + END rw0_wmask_in[270] + PIN rw0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 43.285 2.925 43.339 ; + END + END rw0_wmask_in[271] + PIN rw0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 43.285 3.105 43.339 ; + END + END rw0_wmask_in[272] + PIN rw0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 43.285 3.285 43.339 ; + END + END rw0_wmask_in[273] + PIN rw0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 43.285 3.465 43.339 ; + END + END rw0_wmask_in[274] + PIN rw0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 43.285 3.645 43.339 ; + END + END rw0_wmask_in[275] + PIN rw0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 43.285 3.825 43.339 ; + END + END rw0_wmask_in[276] + PIN rw0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 43.285 4.005 43.339 ; + END + END rw0_wmask_in[277] + PIN rw0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 43.285 4.185 43.339 ; + END + END rw0_wmask_in[278] + PIN rw0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 43.285 4.365 43.339 ; + END + END rw0_wmask_in[279] + PIN rw0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 43.285 4.545 43.339 ; + END + END rw0_wmask_in[280] + PIN rw0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 43.285 4.725 43.339 ; + END + END rw0_wmask_in[281] + PIN rw0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 43.285 4.905 43.339 ; + END + END rw0_wmask_in[282] + PIN rw0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 43.285 5.085 43.339 ; + END + END rw0_wmask_in[283] + PIN rw0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 43.285 5.265 43.339 ; + END + END rw0_wmask_in[284] + PIN rw0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 43.285 5.445 43.339 ; + END + END rw0_wmask_in[285] + PIN rw0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 43.285 5.625 43.339 ; + END + END rw0_wmask_in[286] + PIN rw0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 43.285 5.805 43.339 ; + END + END rw0_wmask_in[287] + PIN rw0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 43.285 5.985 43.339 ; + END + END rw0_wmask_in[288] + PIN rw0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 43.285 6.165 43.339 ; + END + END rw0_wmask_in[289] + PIN rw0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 43.285 6.345 43.339 ; + END + END rw0_wmask_in[290] + PIN rw0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 43.285 6.525 43.339 ; + END + END rw0_wmask_in[291] + PIN rw0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 43.285 6.705 43.339 ; + END + END rw0_wmask_in[292] + PIN rw0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 43.285 6.885 43.339 ; + END + END rw0_wmask_in[293] + PIN rw0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 43.285 7.065 43.339 ; + END + END rw0_wmask_in[294] + PIN rw0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 43.285 7.245 43.339 ; + END + END rw0_wmask_in[295] + PIN rw0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 43.285 7.425 43.339 ; + END + END rw0_wmask_in[296] + PIN rw0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 43.285 7.605 43.339 ; + END + END rw0_wmask_in[297] + PIN rw0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 43.285 7.785 43.339 ; + END + END rw0_wmask_in[298] + PIN rw0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 43.285 7.965 43.339 ; + END + END rw0_wmask_in[299] + PIN rw0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 43.285 8.145 43.339 ; + END + END rw0_wmask_in[300] + PIN rw0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 43.285 8.325 43.339 ; + END + END rw0_wmask_in[301] + PIN rw0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 43.285 8.505 43.339 ; + END + END rw0_wmask_in[302] + PIN rw0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 43.285 8.685 43.339 ; + END + END rw0_wmask_in[303] + PIN rw0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 43.285 8.865 43.339 ; + END + END rw0_wmask_in[304] + PIN rw0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 43.285 9.045 43.339 ; + END + END rw0_wmask_in[305] + PIN rw0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 43.285 9.225 43.339 ; + END + END rw0_wmask_in[306] + PIN rw0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 43.285 9.405 43.339 ; + END + END rw0_wmask_in[307] + PIN rw0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 43.285 9.585 43.339 ; + END + END rw0_wmask_in[308] + PIN rw0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 43.285 9.765 43.339 ; + END + END rw0_wmask_in[309] + PIN rw0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 43.285 9.945 43.339 ; + END + END rw0_wmask_in[310] + PIN rw0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 43.285 10.125 43.339 ; + END + END rw0_wmask_in[311] + PIN rw0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 43.285 10.305 43.339 ; + END + END rw0_wmask_in[312] + PIN rw0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 43.285 10.485 43.339 ; + END + END rw0_wmask_in[313] + PIN rw0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 43.285 10.665 43.339 ; + END + END rw0_wmask_in[314] + PIN rw0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 43.285 10.845 43.339 ; + END + END rw0_wmask_in[315] + PIN rw0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 43.285 11.025 43.339 ; + END + END rw0_wmask_in[316] + PIN rw0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 43.285 11.205 43.339 ; + END + END rw0_wmask_in[317] + PIN rw0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 43.285 11.385 43.339 ; + END + END rw0_wmask_in[318] + PIN rw0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 43.285 11.565 43.339 ; + END + END rw0_wmask_in[319] + PIN rw0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 43.285 11.745 43.339 ; + END + END rw0_wmask_in[320] + PIN rw0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 43.285 11.925 43.339 ; + END + END rw0_wmask_in[321] + PIN rw0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 43.285 12.105 43.339 ; + END + END rw0_wmask_in[322] + PIN rw0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 43.285 12.285 43.339 ; + END + END rw0_wmask_in[323] + PIN rw0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 43.285 12.465 43.339 ; + END + END rw0_wmask_in[324] + PIN rw0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 43.285 12.645 43.339 ; + END + END rw0_wmask_in[325] + PIN rw0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 43.285 12.825 43.339 ; + END + END rw0_wmask_in[326] + PIN rw0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 43.285 13.005 43.339 ; + END + END rw0_wmask_in[327] + PIN rw0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 43.285 13.185 43.339 ; + END + END rw0_wmask_in[328] + PIN rw0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 43.285 13.365 43.339 ; + END + END rw0_wmask_in[329] + PIN rw0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 43.285 13.545 43.339 ; + END + END rw0_wmask_in[330] + PIN rw0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 43.285 13.725 43.339 ; + END + END rw0_wmask_in[331] + PIN rw0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 43.285 13.905 43.339 ; + END + END rw0_wmask_in[332] + PIN rw0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 43.285 14.085 43.339 ; + END + END rw0_wmask_in[333] + PIN rw0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 43.285 14.265 43.339 ; + END + END rw0_wmask_in[334] + PIN rw0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 43.285 14.445 43.339 ; + END + END rw0_wmask_in[335] + PIN rw0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 43.285 14.625 43.339 ; + END + END rw0_wmask_in[336] + PIN rw0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 43.285 14.805 43.339 ; + END + END rw0_wmask_in[337] + PIN rw0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 43.285 14.985 43.339 ; + END + END rw0_wmask_in[338] + PIN rw0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 43.285 15.165 43.339 ; + END + END rw0_wmask_in[339] + PIN rw0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 43.285 15.345 43.339 ; + END + END rw0_wmask_in[340] + PIN rw0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 43.285 15.525 43.339 ; + END + END rw0_wmask_in[341] + PIN rw0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 43.285 15.705 43.339 ; + END + END rw0_wmask_in[342] + PIN rw0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 43.285 15.885 43.339 ; + END + END rw0_wmask_in[343] + PIN rw0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 43.285 16.065 43.339 ; + END + END rw0_wmask_in[344] + PIN rw0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 43.285 16.245 43.339 ; + END + END rw0_wmask_in[345] + PIN rw0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 43.285 16.425 43.339 ; + END + END rw0_wmask_in[346] + PIN rw0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 43.285 16.605 43.339 ; + END + END rw0_wmask_in[347] + PIN rw0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 43.285 16.785 43.339 ; + END + END rw0_wmask_in[348] + PIN rw0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 43.285 16.965 43.339 ; + END + END rw0_wmask_in[349] + PIN rw0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 43.285 17.145 43.339 ; + END + END rw0_wmask_in[350] + PIN rw0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 43.285 17.325 43.339 ; + END + END rw0_wmask_in[351] + PIN rw0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 43.285 17.505 43.339 ; + END + END rw0_wmask_in[352] + PIN rw0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 43.285 17.685 43.339 ; + END + END rw0_wmask_in[353] + PIN rw0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 43.285 17.865 43.339 ; + END + END rw0_wmask_in[354] + PIN rw0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 43.285 18.045 43.339 ; + END + END rw0_wmask_in[355] + PIN rw0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 43.285 18.225 43.339 ; + END + END rw0_wmask_in[356] + PIN rw0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 43.285 18.405 43.339 ; + END + END rw0_wmask_in[357] + PIN rw0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 43.285 18.585 43.339 ; + END + END rw0_wmask_in[358] + PIN rw0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 43.285 18.765 43.339 ; + END + END rw0_wmask_in[359] + PIN rw0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 43.285 18.945 43.339 ; + END + END rw0_wmask_in[360] + PIN rw0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 43.285 19.125 43.339 ; + END + END rw0_wmask_in[361] + PIN rw0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 43.285 19.305 43.339 ; + END + END rw0_wmask_in[362] + PIN rw0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 43.285 19.485 43.339 ; + END + END rw0_wmask_in[363] + PIN rw0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 43.285 19.665 43.339 ; + END + END rw0_wmask_in[364] + PIN rw0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 43.285 19.845 43.339 ; + END + END rw0_wmask_in[365] + PIN rw0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 43.285 20.025 43.339 ; + END + END rw0_wmask_in[366] + PIN rw0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 43.285 20.205 43.339 ; + END + END rw0_wmask_in[367] + PIN rw0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 43.285 20.385 43.339 ; + END + END rw0_wmask_in[368] + PIN rw0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 43.285 20.565 43.339 ; + END + END rw0_wmask_in[369] + PIN rw0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 43.285 20.745 43.339 ; + END + END rw0_wmask_in[370] + PIN rw0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 43.285 20.925 43.339 ; + END + END rw0_wmask_in[371] + PIN rw0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 43.285 21.105 43.339 ; + END + END rw0_wmask_in[372] + PIN rw0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 43.285 21.285 43.339 ; + END + END rw0_wmask_in[373] + PIN rw0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 43.285 21.465 43.339 ; + END + END rw0_wmask_in[374] + PIN rw0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 43.285 21.645 43.339 ; + END + END rw0_wmask_in[375] + PIN rw0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 43.285 21.825 43.339 ; + END + END rw0_wmask_in[376] + PIN rw0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 43.285 22.005 43.339 ; + END + END rw0_wmask_in[377] + PIN rw0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 43.285 22.185 43.339 ; + END + END rw0_wmask_in[378] + PIN rw0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 43.285 22.365 43.339 ; + END + END rw0_wmask_in[379] + PIN rw0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 43.285 22.545 43.339 ; + END + END rw0_wmask_in[380] + PIN rw0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 43.285 22.725 43.339 ; + END + END rw0_wmask_in[381] + PIN rw0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 43.285 22.905 43.339 ; + END + END rw0_wmask_in[382] + PIN rw0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 43.285 23.085 43.339 ; + END + END rw0_wmask_in[383] + PIN rw0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 43.285 23.265 43.339 ; + END + END rw0_wmask_in[384] + PIN rw0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 43.285 23.445 43.339 ; + END + END rw0_wmask_in[385] + PIN rw0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 43.285 23.625 43.339 ; + END + END rw0_wmask_in[386] + PIN rw0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.787 43.285 23.805 43.339 ; + END + END rw0_wmask_in[387] + PIN rw0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 43.285 23.985 43.339 ; + END + END rw0_wmask_in[388] + PIN rw0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.147 43.285 24.165 43.339 ; + END + END rw0_wmask_in[389] + PIN rw0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.327 43.285 24.345 43.339 ; + END + END rw0_wmask_in[390] + PIN rw0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 43.285 24.525 43.339 ; + END + END rw0_wmask_in[391] + PIN rw0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 43.285 24.705 43.339 ; + END + END rw0_wmask_in[392] + PIN rw0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.867 43.285 24.885 43.339 ; + END + END rw0_wmask_in[393] + PIN rw0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 43.285 25.065 43.339 ; + END + END rw0_wmask_in[394] + PIN rw0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.227 43.285 25.245 43.339 ; + END + END rw0_wmask_in[395] + PIN rw0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.407 43.285 25.425 43.339 ; + END + END rw0_wmask_in[396] + PIN rw0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 43.285 25.605 43.339 ; + END + END rw0_wmask_in[397] + PIN rw0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.767 43.285 25.785 43.339 ; + END + END rw0_wmask_in[398] + PIN rw0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.947 43.285 25.965 43.339 ; + END + END rw0_wmask_in[399] + PIN rw0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 43.285 26.145 43.339 ; + END + END rw0_wmask_in[400] + PIN rw0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.307 43.285 26.325 43.339 ; + END + END rw0_wmask_in[401] + PIN rw0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.487 43.285 26.505 43.339 ; + END + END rw0_wmask_in[402] + PIN rw0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 43.285 26.685 43.339 ; + END + END rw0_wmask_in[403] + PIN rw0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.847 43.285 26.865 43.339 ; + END + END rw0_wmask_in[404] + PIN rw0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.027 43.285 27.045 43.339 ; + END + END rw0_wmask_in[405] + PIN rw0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 43.285 27.225 43.339 ; + END + END rw0_wmask_in[406] + PIN rw0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.387 43.285 27.405 43.339 ; + END + END rw0_wmask_in[407] + PIN rw0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 43.285 27.585 43.339 ; + END + END rw0_wmask_in[408] + PIN rw0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 43.285 27.765 43.339 ; + END + END rw0_wmask_in[409] + PIN rw0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.927 43.285 27.945 43.339 ; + END + END rw0_wmask_in[410] + PIN rw0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.107 43.285 28.125 43.339 ; + END + END rw0_wmask_in[411] + PIN rw0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 43.285 28.305 43.339 ; + END + END rw0_wmask_in[412] + PIN rw0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.467 43.285 28.485 43.339 ; + END + END rw0_wmask_in[413] + PIN rw0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.647 43.285 28.665 43.339 ; + END + END rw0_wmask_in[414] + PIN rw0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 43.285 28.845 43.339 ; + END + END rw0_wmask_in[415] + PIN rw0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 43.285 29.025 43.339 ; + END + END rw0_wmask_in[416] + PIN rw0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.187 43.285 29.205 43.339 ; + END + END rw0_wmask_in[417] + PIN rw0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 43.285 29.385 43.339 ; + END + END rw0_wmask_in[418] + PIN rw0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.547 43.285 29.565 43.339 ; + END + END rw0_wmask_in[419] + PIN rw0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.727 43.285 29.745 43.339 ; + END + END rw0_wmask_in[420] + PIN rw0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 43.285 29.925 43.339 ; + END + END rw0_wmask_in[421] + PIN rw0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.087 43.285 30.105 43.339 ; + END + END rw0_wmask_in[422] + PIN rw0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.267 43.285 30.285 43.339 ; + END + END rw0_wmask_in[423] + PIN rw0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 43.285 30.465 43.339 ; + END + END rw0_wmask_in[424] + PIN rw0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.627 43.285 30.645 43.339 ; + END + END rw0_wmask_in[425] + PIN rw0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.807 43.285 30.825 43.339 ; + END + END rw0_wmask_in[426] + PIN rw0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 43.285 31.005 43.339 ; + END + END rw0_wmask_in[427] + PIN rw0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.167 43.285 31.185 43.339 ; + END + END rw0_wmask_in[428] + PIN rw0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.347 43.285 31.365 43.339 ; + END + END rw0_wmask_in[429] + PIN rw0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 43.285 31.545 43.339 ; + END + END rw0_wmask_in[430] + PIN rw0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.707 43.285 31.725 43.339 ; + END + END rw0_wmask_in[431] + PIN rw0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 43.285 31.905 43.339 ; + END + END rw0_wmask_in[432] + PIN rw0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 43.285 32.085 43.339 ; + END + END rw0_wmask_in[433] + PIN rw0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.247 43.285 32.265 43.339 ; + END + END rw0_wmask_in[434] + PIN rw0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.427 43.285 32.445 43.339 ; + END + END rw0_wmask_in[435] + PIN rw0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 43.285 32.625 43.339 ; + END + END rw0_wmask_in[436] + PIN rw0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.787 43.285 32.805 43.339 ; + END + END rw0_wmask_in[437] + PIN rw0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.967 43.285 32.985 43.339 ; + END + END rw0_wmask_in[438] + PIN rw0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 43.285 33.165 43.339 ; + END + END rw0_wmask_in[439] + PIN rw0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 43.285 33.345 43.339 ; + END + END rw0_wmask_in[440] + PIN rw0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.507 43.285 33.525 43.339 ; + END + END rw0_wmask_in[441] + PIN rw0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 43.285 33.705 43.339 ; + END + END rw0_wmask_in[442] + PIN rw0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.867 43.285 33.885 43.339 ; + END + END rw0_wmask_in[443] + PIN rw0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.047 43.285 34.065 43.339 ; + END + END rw0_wmask_in[444] + PIN rw0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 43.285 34.245 43.339 ; + END + END rw0_wmask_in[445] + PIN rw0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.407 43.285 34.425 43.339 ; + END + END rw0_wmask_in[446] + PIN rw0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.587 43.285 34.605 43.339 ; + END + END rw0_wmask_in[447] + PIN rw0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 43.285 34.785 43.339 ; + END + END rw0_wmask_in[448] + PIN rw0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.947 43.285 34.965 43.339 ; + END + END rw0_wmask_in[449] + PIN rw0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.127 43.285 35.145 43.339 ; + END + END rw0_wmask_in[450] + PIN rw0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 43.285 35.325 43.339 ; + END + END rw0_wmask_in[451] + PIN rw0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.487 43.285 35.505 43.339 ; + END + END rw0_wmask_in[452] + PIN rw0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.667 43.285 35.685 43.339 ; + END + END rw0_wmask_in[453] + PIN rw0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 43.285 35.865 43.339 ; + END + END rw0_wmask_in[454] + PIN rw0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.027 43.285 36.045 43.339 ; + END + END rw0_wmask_in[455] + PIN rw0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 43.285 36.225 43.339 ; + END + END rw0_wmask_in[456] + PIN rw0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 43.285 36.405 43.339 ; + END + END rw0_wmask_in[457] + PIN rw0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.567 43.285 36.585 43.339 ; + END + END rw0_wmask_in[458] + PIN rw0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.747 43.285 36.765 43.339 ; + END + END rw0_wmask_in[459] + PIN rw0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 43.285 36.945 43.339 ; + END + END rw0_wmask_in[460] + PIN rw0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.107 43.285 37.125 43.339 ; + END + END rw0_wmask_in[461] + PIN rw0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.287 43.285 37.305 43.339 ; + END + END rw0_wmask_in[462] + PIN rw0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 43.285 37.485 43.339 ; + END + END rw0_wmask_in[463] + PIN rw0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 43.285 37.665 43.339 ; + END + END rw0_wmask_in[464] + PIN rw0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.827 43.285 37.845 43.339 ; + END + END rw0_wmask_in[465] + PIN rw0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 43.285 38.025 43.339 ; + END + END rw0_wmask_in[466] + PIN rw0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.187 43.285 38.205 43.339 ; + END + END rw0_wmask_in[467] + PIN rw0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.367 43.285 38.385 43.339 ; + END + END rw0_wmask_in[468] + PIN rw0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 43.285 38.565 43.339 ; + END + END rw0_wmask_in[469] + PIN rw0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.727 43.285 38.745 43.339 ; + END + END rw0_wmask_in[470] + PIN rw0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.907 43.285 38.925 43.339 ; + END + END rw0_wmask_in[471] + PIN rw0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 43.285 39.105 43.339 ; + END + END rw0_wmask_in[472] + PIN rw0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.267 43.285 39.285 43.339 ; + END + END rw0_wmask_in[473] + PIN rw0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.447 43.285 39.465 43.339 ; + END + END rw0_wmask_in[474] + PIN rw0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 43.285 39.645 43.339 ; + END + END rw0_wmask_in[475] + PIN rw0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.807 43.285 39.825 43.339 ; + END + END rw0_wmask_in[476] + PIN rw0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.987 43.285 40.005 43.339 ; + END + END rw0_wmask_in[477] + PIN rw0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 43.285 40.185 43.339 ; + END + END rw0_wmask_in[478] + PIN rw0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.347 43.285 40.365 43.339 ; + END + END rw0_wmask_in[479] + PIN rw0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 43.285 40.545 43.339 ; + END + END rw0_wmask_in[480] + PIN rw0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 43.285 40.725 43.339 ; + END + END rw0_wmask_in[481] + PIN rw0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.887 43.285 40.905 43.339 ; + END + END rw0_wmask_in[482] + PIN rw0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.067 43.285 41.085 43.339 ; + END + END rw0_wmask_in[483] + PIN rw0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 43.285 41.265 43.339 ; + END + END rw0_wmask_in[484] + PIN rw0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.427 43.285 41.445 43.339 ; + END + END rw0_wmask_in[485] + PIN rw0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.607 43.285 41.625 43.339 ; + END + END rw0_wmask_in[486] + PIN rw0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 43.285 41.805 43.339 ; + END + END rw0_wmask_in[487] + PIN rw0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 43.285 41.985 43.339 ; + END + END rw0_wmask_in[488] + PIN rw0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.147 43.285 42.165 43.339 ; + END + END rw0_wmask_in[489] + PIN rw0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 43.285 42.345 43.339 ; + END + END rw0_wmask_in[490] + PIN rw0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.507 43.285 42.525 43.339 ; + END + END rw0_wmask_in[491] + PIN rw0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.687 43.285 42.705 43.339 ; + END + END rw0_wmask_in[492] + PIN rw0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 43.285 42.885 43.339 ; + END + END rw0_wmask_in[493] + PIN rw0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.047 43.285 43.065 43.339 ; + END + END rw0_wmask_in[494] + PIN rw0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.227 43.285 43.245 43.339 ; + END + END rw0_wmask_in[495] + PIN rw0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 43.285 43.425 43.339 ; + END + END rw0_wmask_in[496] + PIN rw0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.587 43.285 43.605 43.339 ; + END + END rw0_wmask_in[497] + PIN rw0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.767 43.285 43.785 43.339 ; + END + END rw0_wmask_in[498] + PIN rw0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 43.285 43.965 43.339 ; + END + END rw0_wmask_in[499] + PIN rw0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.127 43.285 44.145 43.339 ; + END + END rw0_wmask_in[500] + PIN rw0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.307 43.285 44.325 43.339 ; + END + END rw0_wmask_in[501] + PIN rw0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 43.285 44.505 43.339 ; + END + END rw0_wmask_in[502] + PIN rw0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.667 43.285 44.685 43.339 ; + END + END rw0_wmask_in[503] + PIN rw0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 43.285 44.865 43.339 ; + END + END rw0_wmask_in[504] + PIN rw0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 43.285 45.045 43.339 ; + END + END rw0_wmask_in[505] + PIN rw0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.207 43.285 45.225 43.339 ; + END + END rw0_wmask_in[506] + PIN rw0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.387 43.285 45.405 43.339 ; + END + END rw0_wmask_in[507] + PIN rw0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 43.285 45.585 43.339 ; + END + END rw0_wmask_in[508] + PIN rw0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.747 43.285 45.765 43.339 ; + END + END rw0_wmask_in[509] + PIN rw0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.927 43.285 45.945 43.339 ; + END + END rw0_wmask_in[510] + PIN rw0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 43.285 46.125 43.339 ; + END + END rw0_wmask_in[511] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.140 0.072 19.164 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.004 0.072 20.028 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.292 0.072 20.316 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.868 0.072 20.892 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.156 0.072 21.180 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.732 0.072 21.756 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.020 0.072 22.044 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.596 0.072 22.620 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.884 0.072 22.908 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.748 0.072 23.772 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.324 0.072 24.348 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.612 0.072 24.636 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.188 0.072 25.212 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.052 0.072 26.076 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.340 0.072 26.364 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.916 0.072 26.940 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.204 0.072 27.228 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.780 0.072 27.804 ; + END + END rw0_wd_in[63] + PIN rw0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END rw0_wd_in[64] + PIN rw0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.068 0.072 28.092 ; + END + END rw0_wd_in[65] + PIN rw0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.212 0.072 28.236 ; + END + END rw0_wd_in[66] + PIN rw0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END rw0_wd_in[67] + PIN rw0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END rw0_wd_in[68] + PIN rw0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.644 0.072 28.668 ; + END + END rw0_wd_in[69] + PIN rw0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END rw0_wd_in[70] + PIN rw0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.932 0.072 28.956 ; + END + END rw0_wd_in[71] + PIN rw0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END rw0_wd_in[72] + PIN rw0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END rw0_wd_in[73] + PIN rw0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END rw0_wd_in[74] + PIN rw0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.508 0.072 29.532 ; + END + END rw0_wd_in[75] + PIN rw0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END rw0_wd_in[76] + PIN rw0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.796 0.072 29.820 ; + END + END rw0_wd_in[77] + PIN rw0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.940 0.072 29.964 ; + END + END rw0_wd_in[78] + PIN rw0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END rw0_wd_in[79] + PIN rw0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END rw0_wd_in[80] + PIN rw0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.372 0.072 30.396 ; + END + END rw0_wd_in[81] + PIN rw0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END rw0_wd_in[82] + PIN rw0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.660 0.072 30.684 ; + END + END rw0_wd_in[83] + PIN rw0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END rw0_wd_in[84] + PIN rw0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END rw0_wd_in[85] + PIN rw0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.092 0.072 31.116 ; + END + END rw0_wd_in[86] + PIN rw0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.236 0.072 31.260 ; + END + END rw0_wd_in[87] + PIN rw0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END rw0_wd_in[88] + PIN rw0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END rw0_wd_in[89] + PIN rw0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.668 0.072 31.692 ; + END + END rw0_wd_in[90] + PIN rw0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END rw0_wd_in[91] + PIN rw0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END rw0_wd_in[92] + PIN rw0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.100 0.072 32.124 ; + END + END rw0_wd_in[93] + PIN rw0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END rw0_wd_in[94] + PIN rw0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.388 0.072 32.412 ; + END + END rw0_wd_in[95] + PIN rw0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END rw0_wd_in[96] + PIN rw0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END rw0_wd_in[97] + PIN rw0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.820 0.072 32.844 ; + END + END rw0_wd_in[98] + PIN rw0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.964 0.072 32.988 ; + END + END rw0_wd_in[99] + PIN rw0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END rw0_wd_in[100] + PIN rw0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.252 0.072 33.276 ; + END + END rw0_wd_in[101] + PIN rw0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END rw0_wd_in[102] + PIN rw0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END rw0_wd_in[103] + PIN rw0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END rw0_wd_in[104] + PIN rw0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.828 0.072 33.852 ; + END + END rw0_wd_in[105] + PIN rw0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END rw0_wd_in[106] + PIN rw0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.116 0.072 34.140 ; + END + END rw0_wd_in[107] + PIN rw0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END rw0_wd_in[108] + PIN rw0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.404 0.072 34.428 ; + END + END rw0_wd_in[109] + PIN rw0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END rw0_wd_in[110] + PIN rw0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.692 0.072 34.716 ; + END + END rw0_wd_in[111] + PIN rw0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END rw0_wd_in[112] + PIN rw0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.980 0.072 35.004 ; + END + END rw0_wd_in[113] + PIN rw0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.124 0.072 35.148 ; + END + END rw0_wd_in[114] + PIN rw0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.268 0.072 35.292 ; + END + END rw0_wd_in[115] + PIN rw0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END rw0_wd_in[116] + PIN rw0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.556 0.072 35.580 ; + END + END rw0_wd_in[117] + PIN rw0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END rw0_wd_in[118] + PIN rw0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.844 0.072 35.868 ; + END + END rw0_wd_in[119] + PIN rw0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END rw0_wd_in[120] + PIN rw0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.132 0.072 36.156 ; + END + END rw0_wd_in[121] + PIN rw0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END rw0_wd_in[122] + PIN rw0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.420 0.072 36.444 ; + END + END rw0_wd_in[123] + PIN rw0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END rw0_wd_in[124] + PIN rw0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.708 0.072 36.732 ; + END + END rw0_wd_in[125] + PIN rw0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.852 0.072 36.876 ; + END + END rw0_wd_in[126] + PIN rw0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.996 0.072 37.020 ; + END + END rw0_wd_in[127] + PIN rw0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.708 104.012 18.732 ; + END + END rw0_wd_in[128] + PIN rw0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.852 104.012 18.876 ; + END + END rw0_wd_in[129] + PIN rw0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.996 104.012 19.020 ; + END + END rw0_wd_in[130] + PIN rw0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.140 104.012 19.164 ; + END + END rw0_wd_in[131] + PIN rw0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.284 104.012 19.308 ; + END + END rw0_wd_in[132] + PIN rw0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.428 104.012 19.452 ; + END + END rw0_wd_in[133] + PIN rw0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.572 104.012 19.596 ; + END + END rw0_wd_in[134] + PIN rw0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.716 104.012 19.740 ; + END + END rw0_wd_in[135] + PIN rw0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.860 104.012 19.884 ; + END + END rw0_wd_in[136] + PIN rw0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.004 104.012 20.028 ; + END + END rw0_wd_in[137] + PIN rw0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.148 104.012 20.172 ; + END + END rw0_wd_in[138] + PIN rw0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.292 104.012 20.316 ; + END + END rw0_wd_in[139] + PIN rw0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.436 104.012 20.460 ; + END + END rw0_wd_in[140] + PIN rw0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.580 104.012 20.604 ; + END + END rw0_wd_in[141] + PIN rw0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.724 104.012 20.748 ; + END + END rw0_wd_in[142] + PIN rw0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.868 104.012 20.892 ; + END + END rw0_wd_in[143] + PIN rw0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.012 104.012 21.036 ; + END + END rw0_wd_in[144] + PIN rw0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.156 104.012 21.180 ; + END + END rw0_wd_in[145] + PIN rw0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.300 104.012 21.324 ; + END + END rw0_wd_in[146] + PIN rw0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.444 104.012 21.468 ; + END + END rw0_wd_in[147] + PIN rw0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.588 104.012 21.612 ; + END + END rw0_wd_in[148] + PIN rw0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.732 104.012 21.756 ; + END + END rw0_wd_in[149] + PIN rw0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.876 104.012 21.900 ; + END + END rw0_wd_in[150] + PIN rw0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.020 104.012 22.044 ; + END + END rw0_wd_in[151] + PIN rw0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.164 104.012 22.188 ; + END + END rw0_wd_in[152] + PIN rw0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.308 104.012 22.332 ; + END + END rw0_wd_in[153] + PIN rw0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.452 104.012 22.476 ; + END + END rw0_wd_in[154] + PIN rw0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.596 104.012 22.620 ; + END + END rw0_wd_in[155] + PIN rw0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.740 104.012 22.764 ; + END + END rw0_wd_in[156] + PIN rw0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.884 104.012 22.908 ; + END + END rw0_wd_in[157] + PIN rw0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.028 104.012 23.052 ; + END + END rw0_wd_in[158] + PIN rw0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.172 104.012 23.196 ; + END + END rw0_wd_in[159] + PIN rw0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.316 104.012 23.340 ; + END + END rw0_wd_in[160] + PIN rw0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.460 104.012 23.484 ; + END + END rw0_wd_in[161] + PIN rw0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.604 104.012 23.628 ; + END + END rw0_wd_in[162] + PIN rw0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.748 104.012 23.772 ; + END + END rw0_wd_in[163] + PIN rw0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.892 104.012 23.916 ; + END + END rw0_wd_in[164] + PIN rw0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.036 104.012 24.060 ; + END + END rw0_wd_in[165] + PIN rw0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.180 104.012 24.204 ; + END + END rw0_wd_in[166] + PIN rw0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.324 104.012 24.348 ; + END + END rw0_wd_in[167] + PIN rw0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.468 104.012 24.492 ; + END + END rw0_wd_in[168] + PIN rw0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.612 104.012 24.636 ; + END + END rw0_wd_in[169] + PIN rw0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.756 104.012 24.780 ; + END + END rw0_wd_in[170] + PIN rw0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.900 104.012 24.924 ; + END + END rw0_wd_in[171] + PIN rw0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.044 104.012 25.068 ; + END + END rw0_wd_in[172] + PIN rw0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.188 104.012 25.212 ; + END + END rw0_wd_in[173] + PIN rw0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.332 104.012 25.356 ; + END + END rw0_wd_in[174] + PIN rw0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.476 104.012 25.500 ; + END + END rw0_wd_in[175] + PIN rw0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.620 104.012 25.644 ; + END + END rw0_wd_in[176] + PIN rw0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.764 104.012 25.788 ; + END + END rw0_wd_in[177] + PIN rw0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.908 104.012 25.932 ; + END + END rw0_wd_in[178] + PIN rw0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.052 104.012 26.076 ; + END + END rw0_wd_in[179] + PIN rw0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.196 104.012 26.220 ; + END + END rw0_wd_in[180] + PIN rw0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.340 104.012 26.364 ; + END + END rw0_wd_in[181] + PIN rw0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.484 104.012 26.508 ; + END + END rw0_wd_in[182] + PIN rw0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.628 104.012 26.652 ; + END + END rw0_wd_in[183] + PIN rw0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.772 104.012 26.796 ; + END + END rw0_wd_in[184] + PIN rw0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 26.916 104.012 26.940 ; + END + END rw0_wd_in[185] + PIN rw0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.060 104.012 27.084 ; + END + END rw0_wd_in[186] + PIN rw0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.204 104.012 27.228 ; + END + END rw0_wd_in[187] + PIN rw0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.348 104.012 27.372 ; + END + END rw0_wd_in[188] + PIN rw0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.492 104.012 27.516 ; + END + END rw0_wd_in[189] + PIN rw0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.636 104.012 27.660 ; + END + END rw0_wd_in[190] + PIN rw0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.780 104.012 27.804 ; + END + END rw0_wd_in[191] + PIN rw0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 27.924 104.012 27.948 ; + END + END rw0_wd_in[192] + PIN rw0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.068 104.012 28.092 ; + END + END rw0_wd_in[193] + PIN rw0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.212 104.012 28.236 ; + END + END rw0_wd_in[194] + PIN rw0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.356 104.012 28.380 ; + END + END rw0_wd_in[195] + PIN rw0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.500 104.012 28.524 ; + END + END rw0_wd_in[196] + PIN rw0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.644 104.012 28.668 ; + END + END rw0_wd_in[197] + PIN rw0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.788 104.012 28.812 ; + END + END rw0_wd_in[198] + PIN rw0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 28.932 104.012 28.956 ; + END + END rw0_wd_in[199] + PIN rw0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.076 104.012 29.100 ; + END + END rw0_wd_in[200] + PIN rw0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.220 104.012 29.244 ; + END + END rw0_wd_in[201] + PIN rw0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.364 104.012 29.388 ; + END + END rw0_wd_in[202] + PIN rw0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.508 104.012 29.532 ; + END + END rw0_wd_in[203] + PIN rw0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.652 104.012 29.676 ; + END + END rw0_wd_in[204] + PIN rw0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.796 104.012 29.820 ; + END + END rw0_wd_in[205] + PIN rw0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 29.940 104.012 29.964 ; + END + END rw0_wd_in[206] + PIN rw0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.084 104.012 30.108 ; + END + END rw0_wd_in[207] + PIN rw0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.228 104.012 30.252 ; + END + END rw0_wd_in[208] + PIN rw0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.372 104.012 30.396 ; + END + END rw0_wd_in[209] + PIN rw0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.516 104.012 30.540 ; + END + END rw0_wd_in[210] + PIN rw0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.660 104.012 30.684 ; + END + END rw0_wd_in[211] + PIN rw0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.804 104.012 30.828 ; + END + END rw0_wd_in[212] + PIN rw0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 30.948 104.012 30.972 ; + END + END rw0_wd_in[213] + PIN rw0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.092 104.012 31.116 ; + END + END rw0_wd_in[214] + PIN rw0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.236 104.012 31.260 ; + END + END rw0_wd_in[215] + PIN rw0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.380 104.012 31.404 ; + END + END rw0_wd_in[216] + PIN rw0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.524 104.012 31.548 ; + END + END rw0_wd_in[217] + PIN rw0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.668 104.012 31.692 ; + END + END rw0_wd_in[218] + PIN rw0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.812 104.012 31.836 ; + END + END rw0_wd_in[219] + PIN rw0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 31.956 104.012 31.980 ; + END + END rw0_wd_in[220] + PIN rw0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.100 104.012 32.124 ; + END + END rw0_wd_in[221] + PIN rw0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.244 104.012 32.268 ; + END + END rw0_wd_in[222] + PIN rw0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.388 104.012 32.412 ; + END + END rw0_wd_in[223] + PIN rw0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.532 104.012 32.556 ; + END + END rw0_wd_in[224] + PIN rw0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.676 104.012 32.700 ; + END + END rw0_wd_in[225] + PIN rw0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.820 104.012 32.844 ; + END + END rw0_wd_in[226] + PIN rw0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 32.964 104.012 32.988 ; + END + END rw0_wd_in[227] + PIN rw0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.108 104.012 33.132 ; + END + END rw0_wd_in[228] + PIN rw0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.252 104.012 33.276 ; + END + END rw0_wd_in[229] + PIN rw0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.396 104.012 33.420 ; + END + END rw0_wd_in[230] + PIN rw0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.540 104.012 33.564 ; + END + END rw0_wd_in[231] + PIN rw0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.684 104.012 33.708 ; + END + END rw0_wd_in[232] + PIN rw0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.828 104.012 33.852 ; + END + END rw0_wd_in[233] + PIN rw0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 33.972 104.012 33.996 ; + END + END rw0_wd_in[234] + PIN rw0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.116 104.012 34.140 ; + END + END rw0_wd_in[235] + PIN rw0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.260 104.012 34.284 ; + END + END rw0_wd_in[236] + PIN rw0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.404 104.012 34.428 ; + END + END rw0_wd_in[237] + PIN rw0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.548 104.012 34.572 ; + END + END rw0_wd_in[238] + PIN rw0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.692 104.012 34.716 ; + END + END rw0_wd_in[239] + PIN rw0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.836 104.012 34.860 ; + END + END rw0_wd_in[240] + PIN rw0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 34.980 104.012 35.004 ; + END + END rw0_wd_in[241] + PIN rw0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.124 104.012 35.148 ; + END + END rw0_wd_in[242] + PIN rw0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.268 104.012 35.292 ; + END + END rw0_wd_in[243] + PIN rw0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.412 104.012 35.436 ; + END + END rw0_wd_in[244] + PIN rw0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.556 104.012 35.580 ; + END + END rw0_wd_in[245] + PIN rw0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.700 104.012 35.724 ; + END + END rw0_wd_in[246] + PIN rw0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.844 104.012 35.868 ; + END + END rw0_wd_in[247] + PIN rw0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 35.988 104.012 36.012 ; + END + END rw0_wd_in[248] + PIN rw0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.132 104.012 36.156 ; + END + END rw0_wd_in[249] + PIN rw0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.276 104.012 36.300 ; + END + END rw0_wd_in[250] + PIN rw0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.420 104.012 36.444 ; + END + END rw0_wd_in[251] + PIN rw0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.564 104.012 36.588 ; + END + END rw0_wd_in[252] + PIN rw0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.708 104.012 36.732 ; + END + END rw0_wd_in[253] + PIN rw0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.852 104.012 36.876 ; + END + END rw0_wd_in[254] + PIN rw0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 36.996 104.012 37.020 ; + END + END rw0_wd_in[255] + PIN rw0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END rw0_wd_in[256] + PIN rw0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 0.000 0.405 0.054 ; + END + END rw0_wd_in[257] + PIN rw0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 0.000 0.585 0.054 ; + END + END rw0_wd_in[258] + PIN rw0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END rw0_wd_in[259] + PIN rw0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 0.000 0.945 0.054 ; + END + END rw0_wd_in[260] + PIN rw0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END rw0_wd_in[261] + PIN rw0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END rw0_wd_in[262] + PIN rw0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 0.000 1.485 0.054 ; + END + END rw0_wd_in[263] + PIN rw0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END rw0_wd_in[264] + PIN rw0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END rw0_wd_in[265] + PIN rw0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END rw0_wd_in[266] + PIN rw0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 0.000 2.205 0.054 ; + END + END rw0_wd_in[267] + PIN rw0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END rw0_wd_in[268] + PIN rw0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 0.000 2.565 0.054 ; + END + END rw0_wd_in[269] + PIN rw0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END rw0_wd_in[270] + PIN rw0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END rw0_wd_in[271] + PIN rw0_wd_in[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END rw0_wd_in[272] + PIN rw0_wd_in[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 0.000 3.285 0.054 ; + END + END rw0_wd_in[273] + PIN rw0_wd_in[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END rw0_wd_in[274] + PIN rw0_wd_in[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 0.000 3.645 0.054 ; + END + END rw0_wd_in[275] + PIN rw0_wd_in[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END rw0_wd_in[276] + PIN rw0_wd_in[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END rw0_wd_in[277] + PIN rw0_wd_in[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 0.000 4.185 0.054 ; + END + END rw0_wd_in[278] + PIN rw0_wd_in[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 0.000 4.365 0.054 ; + END + END rw0_wd_in[279] + PIN rw0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END rw0_wd_in[280] + PIN rw0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END rw0_wd_in[281] + PIN rw0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 0.000 4.905 0.054 ; + END + END rw0_wd_in[282] + PIN rw0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END rw0_wd_in[283] + PIN rw0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END rw0_wd_in[284] + PIN rw0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 0.000 5.445 0.054 ; + END + END rw0_wd_in[285] + PIN rw0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END rw0_wd_in[286] + PIN rw0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END rw0_wd_in[287] + PIN rw0_wd_in[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END rw0_wd_in[288] + PIN rw0_wd_in[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END rw0_wd_in[289] + PIN rw0_wd_in[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 0.000 6.345 0.054 ; + END + END rw0_wd_in[290] + PIN rw0_wd_in[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END rw0_wd_in[291] + PIN rw0_wd_in[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END rw0_wd_in[292] + PIN rw0_wd_in[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 0.000 6.885 0.054 ; + END + END rw0_wd_in[293] + PIN rw0_wd_in[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 0.000 7.065 0.054 ; + END + END rw0_wd_in[294] + PIN rw0_wd_in[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END rw0_wd_in[295] + PIN rw0_wd_in[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END rw0_wd_in[296] + PIN rw0_wd_in[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 0.000 7.605 0.054 ; + END + END rw0_wd_in[297] + PIN rw0_wd_in[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END rw0_wd_in[298] + PIN rw0_wd_in[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 0.000 7.965 0.054 ; + END + END rw0_wd_in[299] + PIN rw0_wd_in[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 0.000 8.145 0.054 ; + END + END rw0_wd_in[300] + PIN rw0_wd_in[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END rw0_wd_in[301] + PIN rw0_wd_in[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 0.000 8.505 0.054 ; + END + END rw0_wd_in[302] + PIN rw0_wd_in[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 0.000 8.685 0.054 ; + END + END rw0_wd_in[303] + PIN rw0_wd_in[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END rw0_wd_in[304] + PIN rw0_wd_in[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 0.000 9.045 0.054 ; + END + END rw0_wd_in[305] + PIN rw0_wd_in[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 0.000 9.225 0.054 ; + END + END rw0_wd_in[306] + PIN rw0_wd_in[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 0.000 9.405 0.054 ; + END + END rw0_wd_in[307] + PIN rw0_wd_in[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 0.000 9.585 0.054 ; + END + END rw0_wd_in[308] + PIN rw0_wd_in[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 0.000 9.765 0.054 ; + END + END rw0_wd_in[309] + PIN rw0_wd_in[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 0.000 9.945 0.054 ; + END + END rw0_wd_in[310] + PIN rw0_wd_in[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 0.000 10.125 0.054 ; + END + END rw0_wd_in[311] + PIN rw0_wd_in[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END rw0_wd_in[312] + PIN rw0_wd_in[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 0.000 10.485 0.054 ; + END + END rw0_wd_in[313] + PIN rw0_wd_in[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 0.000 10.665 0.054 ; + END + END rw0_wd_in[314] + PIN rw0_wd_in[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 0.000 10.845 0.054 ; + END + END rw0_wd_in[315] + PIN rw0_wd_in[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 0.000 11.025 0.054 ; + END + END rw0_wd_in[316] + PIN rw0_wd_in[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 0.000 11.205 0.054 ; + END + END rw0_wd_in[317] + PIN rw0_wd_in[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 0.000 11.385 0.054 ; + END + END rw0_wd_in[318] + PIN rw0_wd_in[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 0.000 11.565 0.054 ; + END + END rw0_wd_in[319] + PIN rw0_wd_in[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END rw0_wd_in[320] + PIN rw0_wd_in[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 0.000 11.925 0.054 ; + END + END rw0_wd_in[321] + PIN rw0_wd_in[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 0.000 12.105 0.054 ; + END + END rw0_wd_in[322] + PIN rw0_wd_in[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 0.000 12.285 0.054 ; + END + END rw0_wd_in[323] + PIN rw0_wd_in[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 0.000 12.465 0.054 ; + END + END rw0_wd_in[324] + PIN rw0_wd_in[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 0.000 12.645 0.054 ; + END + END rw0_wd_in[325] + PIN rw0_wd_in[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 0.000 12.825 0.054 ; + END + END rw0_wd_in[326] + PIN rw0_wd_in[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 0.000 13.005 0.054 ; + END + END rw0_wd_in[327] + PIN rw0_wd_in[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END rw0_wd_in[328] + PIN rw0_wd_in[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 0.000 13.365 0.054 ; + END + END rw0_wd_in[329] + PIN rw0_wd_in[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 0.000 13.545 0.054 ; + END + END rw0_wd_in[330] + PIN rw0_wd_in[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 0.000 13.725 0.054 ; + END + END rw0_wd_in[331] + PIN rw0_wd_in[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 0.000 13.905 0.054 ; + END + END rw0_wd_in[332] + PIN rw0_wd_in[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 0.000 14.085 0.054 ; + END + END rw0_wd_in[333] + PIN rw0_wd_in[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 0.000 14.265 0.054 ; + END + END rw0_wd_in[334] + PIN rw0_wd_in[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 0.000 14.445 0.054 ; + END + END rw0_wd_in[335] + PIN rw0_wd_in[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END rw0_wd_in[336] + PIN rw0_wd_in[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 0.000 14.805 0.054 ; + END + END rw0_wd_in[337] + PIN rw0_wd_in[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 0.000 14.985 0.054 ; + END + END rw0_wd_in[338] + PIN rw0_wd_in[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 0.000 15.165 0.054 ; + END + END rw0_wd_in[339] + PIN rw0_wd_in[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 0.000 15.345 0.054 ; + END + END rw0_wd_in[340] + PIN rw0_wd_in[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 0.000 15.525 0.054 ; + END + END rw0_wd_in[341] + PIN rw0_wd_in[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 0.000 15.705 0.054 ; + END + END rw0_wd_in[342] + PIN rw0_wd_in[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 0.000 15.885 0.054 ; + END + END rw0_wd_in[343] + PIN rw0_wd_in[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END rw0_wd_in[344] + PIN rw0_wd_in[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 0.000 16.245 0.054 ; + END + END rw0_wd_in[345] + PIN rw0_wd_in[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 0.000 16.425 0.054 ; + END + END rw0_wd_in[346] + PIN rw0_wd_in[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 0.000 16.605 0.054 ; + END + END rw0_wd_in[347] + PIN rw0_wd_in[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 0.000 16.785 0.054 ; + END + END rw0_wd_in[348] + PIN rw0_wd_in[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 0.000 16.965 0.054 ; + END + END rw0_wd_in[349] + PIN rw0_wd_in[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 0.000 17.145 0.054 ; + END + END rw0_wd_in[350] + PIN rw0_wd_in[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 0.000 17.325 0.054 ; + END + END rw0_wd_in[351] + PIN rw0_wd_in[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END rw0_wd_in[352] + PIN rw0_wd_in[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 0.000 17.685 0.054 ; + END + END rw0_wd_in[353] + PIN rw0_wd_in[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 0.000 17.865 0.054 ; + END + END rw0_wd_in[354] + PIN rw0_wd_in[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 0.000 18.045 0.054 ; + END + END rw0_wd_in[355] + PIN rw0_wd_in[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 0.000 18.225 0.054 ; + END + END rw0_wd_in[356] + PIN rw0_wd_in[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 0.000 18.405 0.054 ; + END + END rw0_wd_in[357] + PIN rw0_wd_in[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 0.000 18.585 0.054 ; + END + END rw0_wd_in[358] + PIN rw0_wd_in[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 0.000 18.765 0.054 ; + END + END rw0_wd_in[359] + PIN rw0_wd_in[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END rw0_wd_in[360] + PIN rw0_wd_in[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 0.000 19.125 0.054 ; + END + END rw0_wd_in[361] + PIN rw0_wd_in[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 0.000 19.305 0.054 ; + END + END rw0_wd_in[362] + PIN rw0_wd_in[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 0.000 19.485 0.054 ; + END + END rw0_wd_in[363] + PIN rw0_wd_in[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 0.000 19.665 0.054 ; + END + END rw0_wd_in[364] + PIN rw0_wd_in[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 0.000 19.845 0.054 ; + END + END rw0_wd_in[365] + PIN rw0_wd_in[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 0.000 20.025 0.054 ; + END + END rw0_wd_in[366] + PIN rw0_wd_in[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 0.000 20.205 0.054 ; + END + END rw0_wd_in[367] + PIN rw0_wd_in[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END rw0_wd_in[368] + PIN rw0_wd_in[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 0.000 20.565 0.054 ; + END + END rw0_wd_in[369] + PIN rw0_wd_in[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 0.000 20.745 0.054 ; + END + END rw0_wd_in[370] + PIN rw0_wd_in[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 0.000 20.925 0.054 ; + END + END rw0_wd_in[371] + PIN rw0_wd_in[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 0.000 21.105 0.054 ; + END + END rw0_wd_in[372] + PIN rw0_wd_in[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 0.000 21.285 0.054 ; + END + END rw0_wd_in[373] + PIN rw0_wd_in[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 0.000 21.465 0.054 ; + END + END rw0_wd_in[374] + PIN rw0_wd_in[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 0.000 21.645 0.054 ; + END + END rw0_wd_in[375] + PIN rw0_wd_in[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END rw0_wd_in[376] + PIN rw0_wd_in[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 0.000 22.005 0.054 ; + END + END rw0_wd_in[377] + PIN rw0_wd_in[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 0.000 22.185 0.054 ; + END + END rw0_wd_in[378] + PIN rw0_wd_in[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 0.000 22.365 0.054 ; + END + END rw0_wd_in[379] + PIN rw0_wd_in[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 0.000 22.545 0.054 ; + END + END rw0_wd_in[380] + PIN rw0_wd_in[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 0.000 22.725 0.054 ; + END + END rw0_wd_in[381] + PIN rw0_wd_in[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 0.000 22.905 0.054 ; + END + END rw0_wd_in[382] + PIN rw0_wd_in[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 0.000 23.085 0.054 ; + END + END rw0_wd_in[383] + PIN rw0_wd_in[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END rw0_wd_in[384] + PIN rw0_wd_in[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 0.000 23.445 0.054 ; + END + END rw0_wd_in[385] + PIN rw0_wd_in[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 0.000 23.625 0.054 ; + END + END rw0_wd_in[386] + PIN rw0_wd_in[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.787 0.000 23.805 0.054 ; + END + END rw0_wd_in[387] + PIN rw0_wd_in[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 0.000 23.985 0.054 ; + END + END rw0_wd_in[388] + PIN rw0_wd_in[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.147 0.000 24.165 0.054 ; + END + END rw0_wd_in[389] + PIN rw0_wd_in[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.327 0.000 24.345 0.054 ; + END + END rw0_wd_in[390] + PIN rw0_wd_in[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 0.000 24.525 0.054 ; + END + END rw0_wd_in[391] + PIN rw0_wd_in[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END rw0_wd_in[392] + PIN rw0_wd_in[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.867 0.000 24.885 0.054 ; + END + END rw0_wd_in[393] + PIN rw0_wd_in[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 0.000 25.065 0.054 ; + END + END rw0_wd_in[394] + PIN rw0_wd_in[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.227 0.000 25.245 0.054 ; + END + END rw0_wd_in[395] + PIN rw0_wd_in[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.407 0.000 25.425 0.054 ; + END + END rw0_wd_in[396] + PIN rw0_wd_in[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 0.000 25.605 0.054 ; + END + END rw0_wd_in[397] + PIN rw0_wd_in[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.767 0.000 25.785 0.054 ; + END + END rw0_wd_in[398] + PIN rw0_wd_in[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.947 0.000 25.965 0.054 ; + END + END rw0_wd_in[399] + PIN rw0_wd_in[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END rw0_wd_in[400] + PIN rw0_wd_in[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.307 0.000 26.325 0.054 ; + END + END rw0_wd_in[401] + PIN rw0_wd_in[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.487 0.000 26.505 0.054 ; + END + END rw0_wd_in[402] + PIN rw0_wd_in[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 0.000 26.685 0.054 ; + END + END rw0_wd_in[403] + PIN rw0_wd_in[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.847 0.000 26.865 0.054 ; + END + END rw0_wd_in[404] + PIN rw0_wd_in[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.027 0.000 27.045 0.054 ; + END + END rw0_wd_in[405] + PIN rw0_wd_in[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 0.000 27.225 0.054 ; + END + END rw0_wd_in[406] + PIN rw0_wd_in[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.387 0.000 27.405 0.054 ; + END + END rw0_wd_in[407] + PIN rw0_wd_in[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END rw0_wd_in[408] + PIN rw0_wd_in[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 0.000 27.765 0.054 ; + END + END rw0_wd_in[409] + PIN rw0_wd_in[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.927 0.000 27.945 0.054 ; + END + END rw0_wd_in[410] + PIN rw0_wd_in[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.107 0.000 28.125 0.054 ; + END + END rw0_wd_in[411] + PIN rw0_wd_in[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 0.000 28.305 0.054 ; + END + END rw0_wd_in[412] + PIN rw0_wd_in[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.467 0.000 28.485 0.054 ; + END + END rw0_wd_in[413] + PIN rw0_wd_in[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.647 0.000 28.665 0.054 ; + END + END rw0_wd_in[414] + PIN rw0_wd_in[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 0.000 28.845 0.054 ; + END + END rw0_wd_in[415] + PIN rw0_wd_in[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END rw0_wd_in[416] + PIN rw0_wd_in[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.187 0.000 29.205 0.054 ; + END + END rw0_wd_in[417] + PIN rw0_wd_in[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 0.000 29.385 0.054 ; + END + END rw0_wd_in[418] + PIN rw0_wd_in[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.547 0.000 29.565 0.054 ; + END + END rw0_wd_in[419] + PIN rw0_wd_in[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.727 0.000 29.745 0.054 ; + END + END rw0_wd_in[420] + PIN rw0_wd_in[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 0.000 29.925 0.054 ; + END + END rw0_wd_in[421] + PIN rw0_wd_in[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.087 0.000 30.105 0.054 ; + END + END rw0_wd_in[422] + PIN rw0_wd_in[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.267 0.000 30.285 0.054 ; + END + END rw0_wd_in[423] + PIN rw0_wd_in[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END rw0_wd_in[424] + PIN rw0_wd_in[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.627 0.000 30.645 0.054 ; + END + END rw0_wd_in[425] + PIN rw0_wd_in[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.807 0.000 30.825 0.054 ; + END + END rw0_wd_in[426] + PIN rw0_wd_in[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 0.000 31.005 0.054 ; + END + END rw0_wd_in[427] + PIN rw0_wd_in[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.167 0.000 31.185 0.054 ; + END + END rw0_wd_in[428] + PIN rw0_wd_in[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.347 0.000 31.365 0.054 ; + END + END rw0_wd_in[429] + PIN rw0_wd_in[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 0.000 31.545 0.054 ; + END + END rw0_wd_in[430] + PIN rw0_wd_in[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.707 0.000 31.725 0.054 ; + END + END rw0_wd_in[431] + PIN rw0_wd_in[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END rw0_wd_in[432] + PIN rw0_wd_in[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 0.000 32.085 0.054 ; + END + END rw0_wd_in[433] + PIN rw0_wd_in[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.247 0.000 32.265 0.054 ; + END + END rw0_wd_in[434] + PIN rw0_wd_in[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.427 0.000 32.445 0.054 ; + END + END rw0_wd_in[435] + PIN rw0_wd_in[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 0.000 32.625 0.054 ; + END + END rw0_wd_in[436] + PIN rw0_wd_in[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.787 0.000 32.805 0.054 ; + END + END rw0_wd_in[437] + PIN rw0_wd_in[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.967 0.000 32.985 0.054 ; + END + END rw0_wd_in[438] + PIN rw0_wd_in[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 0.000 33.165 0.054 ; + END + END rw0_wd_in[439] + PIN rw0_wd_in[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END rw0_wd_in[440] + PIN rw0_wd_in[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.507 0.000 33.525 0.054 ; + END + END rw0_wd_in[441] + PIN rw0_wd_in[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 0.000 33.705 0.054 ; + END + END rw0_wd_in[442] + PIN rw0_wd_in[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.867 0.000 33.885 0.054 ; + END + END rw0_wd_in[443] + PIN rw0_wd_in[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.047 0.000 34.065 0.054 ; + END + END rw0_wd_in[444] + PIN rw0_wd_in[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 0.000 34.245 0.054 ; + END + END rw0_wd_in[445] + PIN rw0_wd_in[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.407 0.000 34.425 0.054 ; + END + END rw0_wd_in[446] + PIN rw0_wd_in[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.587 0.000 34.605 0.054 ; + END + END rw0_wd_in[447] + PIN rw0_wd_in[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END rw0_wd_in[448] + PIN rw0_wd_in[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.947 0.000 34.965 0.054 ; + END + END rw0_wd_in[449] + PIN rw0_wd_in[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.127 0.000 35.145 0.054 ; + END + END rw0_wd_in[450] + PIN rw0_wd_in[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 0.000 35.325 0.054 ; + END + END rw0_wd_in[451] + PIN rw0_wd_in[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.487 0.000 35.505 0.054 ; + END + END rw0_wd_in[452] + PIN rw0_wd_in[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.667 0.000 35.685 0.054 ; + END + END rw0_wd_in[453] + PIN rw0_wd_in[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 0.000 35.865 0.054 ; + END + END rw0_wd_in[454] + PIN rw0_wd_in[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.027 0.000 36.045 0.054 ; + END + END rw0_wd_in[455] + PIN rw0_wd_in[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END rw0_wd_in[456] + PIN rw0_wd_in[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 0.000 36.405 0.054 ; + END + END rw0_wd_in[457] + PIN rw0_wd_in[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.567 0.000 36.585 0.054 ; + END + END rw0_wd_in[458] + PIN rw0_wd_in[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.747 0.000 36.765 0.054 ; + END + END rw0_wd_in[459] + PIN rw0_wd_in[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 0.000 36.945 0.054 ; + END + END rw0_wd_in[460] + PIN rw0_wd_in[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.107 0.000 37.125 0.054 ; + END + END rw0_wd_in[461] + PIN rw0_wd_in[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.287 0.000 37.305 0.054 ; + END + END rw0_wd_in[462] + PIN rw0_wd_in[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 0.000 37.485 0.054 ; + END + END rw0_wd_in[463] + PIN rw0_wd_in[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END rw0_wd_in[464] + PIN rw0_wd_in[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.827 0.000 37.845 0.054 ; + END + END rw0_wd_in[465] + PIN rw0_wd_in[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 0.000 38.025 0.054 ; + END + END rw0_wd_in[466] + PIN rw0_wd_in[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.187 0.000 38.205 0.054 ; + END + END rw0_wd_in[467] + PIN rw0_wd_in[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.367 0.000 38.385 0.054 ; + END + END rw0_wd_in[468] + PIN rw0_wd_in[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 0.000 38.565 0.054 ; + END + END rw0_wd_in[469] + PIN rw0_wd_in[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.727 0.000 38.745 0.054 ; + END + END rw0_wd_in[470] + PIN rw0_wd_in[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.907 0.000 38.925 0.054 ; + END + END rw0_wd_in[471] + PIN rw0_wd_in[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END rw0_wd_in[472] + PIN rw0_wd_in[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.267 0.000 39.285 0.054 ; + END + END rw0_wd_in[473] + PIN rw0_wd_in[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.447 0.000 39.465 0.054 ; + END + END rw0_wd_in[474] + PIN rw0_wd_in[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 0.000 39.645 0.054 ; + END + END rw0_wd_in[475] + PIN rw0_wd_in[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.807 0.000 39.825 0.054 ; + END + END rw0_wd_in[476] + PIN rw0_wd_in[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.987 0.000 40.005 0.054 ; + END + END rw0_wd_in[477] + PIN rw0_wd_in[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 0.000 40.185 0.054 ; + END + END rw0_wd_in[478] + PIN rw0_wd_in[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.347 0.000 40.365 0.054 ; + END + END rw0_wd_in[479] + PIN rw0_wd_in[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END rw0_wd_in[480] + PIN rw0_wd_in[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 0.000 40.725 0.054 ; + END + END rw0_wd_in[481] + PIN rw0_wd_in[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.887 0.000 40.905 0.054 ; + END + END rw0_wd_in[482] + PIN rw0_wd_in[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.067 0.000 41.085 0.054 ; + END + END rw0_wd_in[483] + PIN rw0_wd_in[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 0.000 41.265 0.054 ; + END + END rw0_wd_in[484] + PIN rw0_wd_in[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.427 0.000 41.445 0.054 ; + END + END rw0_wd_in[485] + PIN rw0_wd_in[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.607 0.000 41.625 0.054 ; + END + END rw0_wd_in[486] + PIN rw0_wd_in[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 0.000 41.805 0.054 ; + END + END rw0_wd_in[487] + PIN rw0_wd_in[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END rw0_wd_in[488] + PIN rw0_wd_in[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.147 0.000 42.165 0.054 ; + END + END rw0_wd_in[489] + PIN rw0_wd_in[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 0.000 42.345 0.054 ; + END + END rw0_wd_in[490] + PIN rw0_wd_in[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.507 0.000 42.525 0.054 ; + END + END rw0_wd_in[491] + PIN rw0_wd_in[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.687 0.000 42.705 0.054 ; + END + END rw0_wd_in[492] + PIN rw0_wd_in[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 0.000 42.885 0.054 ; + END + END rw0_wd_in[493] + PIN rw0_wd_in[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.047 0.000 43.065 0.054 ; + END + END rw0_wd_in[494] + PIN rw0_wd_in[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.227 0.000 43.245 0.054 ; + END + END rw0_wd_in[495] + PIN rw0_wd_in[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END rw0_wd_in[496] + PIN rw0_wd_in[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.587 0.000 43.605 0.054 ; + END + END rw0_wd_in[497] + PIN rw0_wd_in[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.767 0.000 43.785 0.054 ; + END + END rw0_wd_in[498] + PIN rw0_wd_in[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 0.000 43.965 0.054 ; + END + END rw0_wd_in[499] + PIN rw0_wd_in[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.127 0.000 44.145 0.054 ; + END + END rw0_wd_in[500] + PIN rw0_wd_in[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.307 0.000 44.325 0.054 ; + END + END rw0_wd_in[501] + PIN rw0_wd_in[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 0.000 44.505 0.054 ; + END + END rw0_wd_in[502] + PIN rw0_wd_in[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.667 0.000 44.685 0.054 ; + END + END rw0_wd_in[503] + PIN rw0_wd_in[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END rw0_wd_in[504] + PIN rw0_wd_in[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 0.000 45.045 0.054 ; + END + END rw0_wd_in[505] + PIN rw0_wd_in[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.207 0.000 45.225 0.054 ; + END + END rw0_wd_in[506] + PIN rw0_wd_in[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.387 0.000 45.405 0.054 ; + END + END rw0_wd_in[507] + PIN rw0_wd_in[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 0.000 45.585 0.054 ; + END + END rw0_wd_in[508] + PIN rw0_wd_in[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.747 0.000 45.765 0.054 ; + END + END rw0_wd_in[509] + PIN rw0_wd_in[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.927 0.000 45.945 0.054 ; + END + END rw0_wd_in[510] + PIN rw0_wd_in[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 0.000 46.125 0.054 ; + END + END rw0_wd_in[511] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.467 0.000 46.485 0.054 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 0.000 46.665 0.054 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.827 0.000 46.845 0.054 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.007 0.000 47.025 0.054 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 0.000 47.205 0.054 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.367 0.000 47.385 0.054 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.547 0.000 47.565 0.054 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.907 0.000 47.925 0.054 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.087 0.000 48.105 0.054 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 0.000 48.285 0.054 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.447 0.000 48.465 0.054 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.627 0.000 48.645 0.054 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 0.000 48.825 0.054 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.987 0.000 49.005 0.054 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 0.000 49.365 0.054 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.527 0.000 49.545 0.054 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.707 0.000 49.725 0.054 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 0.000 49.905 0.054 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.067 0.000 50.085 0.054 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.247 0.000 50.265 0.054 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 0.000 50.445 0.054 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.787 0.000 50.805 0.054 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 0.000 50.985 0.054 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.147 0.000 51.165 0.054 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.327 0.000 51.345 0.054 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 0.000 51.525 0.054 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.687 0.000 51.705 0.054 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.867 0.000 51.885 0.054 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.227 0.000 52.245 0.054 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.407 0.000 52.425 0.054 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 0.000 52.605 0.054 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.767 0.000 52.785 0.054 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.947 0.000 52.965 0.054 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 0.000 53.145 0.054 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.307 0.000 53.325 0.054 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 0.000 53.685 0.054 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.847 0.000 53.865 0.054 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.027 0.000 54.045 0.054 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 0.000 54.225 0.054 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.387 0.000 54.405 0.054 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.567 0.000 54.585 0.054 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 0.000 54.765 0.054 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.107 0.000 55.125 0.054 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 0.000 55.305 0.054 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.467 0.000 55.485 0.054 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.647 0.000 55.665 0.054 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 0.000 55.845 0.054 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.007 0.000 56.025 0.054 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.187 0.000 56.205 0.054 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.547 0.000 56.565 0.054 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.727 0.000 56.745 0.054 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 0.000 56.925 0.054 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.087 0.000 57.105 0.054 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.267 0.000 57.285 0.054 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 0.000 57.465 0.054 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.627 0.000 57.645 0.054 ; + END + END rw0_rd_out[63] + PIN rw0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END rw0_rd_out[64] + PIN rw0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 0.000 58.005 0.054 ; + END + END rw0_rd_out[65] + PIN rw0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.167 0.000 58.185 0.054 ; + END + END rw0_rd_out[66] + PIN rw0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.347 0.000 58.365 0.054 ; + END + END rw0_rd_out[67] + PIN rw0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 0.000 58.545 0.054 ; + END + END rw0_rd_out[68] + PIN rw0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.707 0.000 58.725 0.054 ; + END + END rw0_rd_out[69] + PIN rw0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.887 0.000 58.905 0.054 ; + END + END rw0_rd_out[70] + PIN rw0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 0.000 59.085 0.054 ; + END + END rw0_rd_out[71] + PIN rw0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END rw0_rd_out[72] + PIN rw0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.427 0.000 59.445 0.054 ; + END + END rw0_rd_out[73] + PIN rw0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 0.000 59.625 0.054 ; + END + END rw0_rd_out[74] + PIN rw0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.787 0.000 59.805 0.054 ; + END + END rw0_rd_out[75] + PIN rw0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.967 0.000 59.985 0.054 ; + END + END rw0_rd_out[76] + PIN rw0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 0.000 60.165 0.054 ; + END + END rw0_rd_out[77] + PIN rw0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.327 0.000 60.345 0.054 ; + END + END rw0_rd_out[78] + PIN rw0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.507 0.000 60.525 0.054 ; + END + END rw0_rd_out[79] + PIN rw0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END rw0_rd_out[80] + PIN rw0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.867 0.000 60.885 0.054 ; + END + END rw0_rd_out[81] + PIN rw0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.047 0.000 61.065 0.054 ; + END + END rw0_rd_out[82] + PIN rw0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 0.000 61.245 0.054 ; + END + END rw0_rd_out[83] + PIN rw0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.407 0.000 61.425 0.054 ; + END + END rw0_rd_out[84] + PIN rw0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.587 0.000 61.605 0.054 ; + END + END rw0_rd_out[85] + PIN rw0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 0.000 61.785 0.054 ; + END + END rw0_rd_out[86] + PIN rw0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.947 0.000 61.965 0.054 ; + END + END rw0_rd_out[87] + PIN rw0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END rw0_rd_out[88] + PIN rw0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 0.000 62.325 0.054 ; + END + END rw0_rd_out[89] + PIN rw0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.487 0.000 62.505 0.054 ; + END + END rw0_rd_out[90] + PIN rw0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.667 0.000 62.685 0.054 ; + END + END rw0_rd_out[91] + PIN rw0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 0.000 62.865 0.054 ; + END + END rw0_rd_out[92] + PIN rw0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.027 0.000 63.045 0.054 ; + END + END rw0_rd_out[93] + PIN rw0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.207 0.000 63.225 0.054 ; + END + END rw0_rd_out[94] + PIN rw0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 0.000 63.405 0.054 ; + END + END rw0_rd_out[95] + PIN rw0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END rw0_rd_out[96] + PIN rw0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.747 0.000 63.765 0.054 ; + END + END rw0_rd_out[97] + PIN rw0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.927 0.000 63.945 0.054 ; + END + END rw0_rd_out[98] + PIN rw0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.107 0.000 64.125 0.054 ; + END + END rw0_rd_out[99] + PIN rw0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.287 0.000 64.305 0.054 ; + END + END rw0_rd_out[100] + PIN rw0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.467 0.000 64.485 0.054 ; + END + END rw0_rd_out[101] + PIN rw0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.647 0.000 64.665 0.054 ; + END + END rw0_rd_out[102] + PIN rw0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.827 0.000 64.845 0.054 ; + END + END rw0_rd_out[103] + PIN rw0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END rw0_rd_out[104] + PIN rw0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.187 0.000 65.205 0.054 ; + END + END rw0_rd_out[105] + PIN rw0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.367 0.000 65.385 0.054 ; + END + END rw0_rd_out[106] + PIN rw0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.547 0.000 65.565 0.054 ; + END + END rw0_rd_out[107] + PIN rw0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.727 0.000 65.745 0.054 ; + END + END rw0_rd_out[108] + PIN rw0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.907 0.000 65.925 0.054 ; + END + END rw0_rd_out[109] + PIN rw0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.087 0.000 66.105 0.054 ; + END + END rw0_rd_out[110] + PIN rw0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.267 0.000 66.285 0.054 ; + END + END rw0_rd_out[111] + PIN rw0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END rw0_rd_out[112] + PIN rw0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.627 0.000 66.645 0.054 ; + END + END rw0_rd_out[113] + PIN rw0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.807 0.000 66.825 0.054 ; + END + END rw0_rd_out[114] + PIN rw0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.987 0.000 67.005 0.054 ; + END + END rw0_rd_out[115] + PIN rw0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.167 0.000 67.185 0.054 ; + END + END rw0_rd_out[116] + PIN rw0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.347 0.000 67.365 0.054 ; + END + END rw0_rd_out[117] + PIN rw0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.527 0.000 67.545 0.054 ; + END + END rw0_rd_out[118] + PIN rw0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.707 0.000 67.725 0.054 ; + END + END rw0_rd_out[119] + PIN rw0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END rw0_rd_out[120] + PIN rw0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.067 0.000 68.085 0.054 ; + END + END rw0_rd_out[121] + PIN rw0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.247 0.000 68.265 0.054 ; + END + END rw0_rd_out[122] + PIN rw0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.427 0.000 68.445 0.054 ; + END + END rw0_rd_out[123] + PIN rw0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.607 0.000 68.625 0.054 ; + END + END rw0_rd_out[124] + PIN rw0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.787 0.000 68.805 0.054 ; + END + END rw0_rd_out[125] + PIN rw0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.967 0.000 68.985 0.054 ; + END + END rw0_rd_out[126] + PIN rw0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.147 0.000 69.165 0.054 ; + END + END rw0_rd_out[127] + PIN rw0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END rw0_rd_out[128] + PIN rw0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.507 0.000 69.525 0.054 ; + END + END rw0_rd_out[129] + PIN rw0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.687 0.000 69.705 0.054 ; + END + END rw0_rd_out[130] + PIN rw0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.867 0.000 69.885 0.054 ; + END + END rw0_rd_out[131] + PIN rw0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.047 0.000 70.065 0.054 ; + END + END rw0_rd_out[132] + PIN rw0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.227 0.000 70.245 0.054 ; + END + END rw0_rd_out[133] + PIN rw0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.407 0.000 70.425 0.054 ; + END + END rw0_rd_out[134] + PIN rw0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.587 0.000 70.605 0.054 ; + END + END rw0_rd_out[135] + PIN rw0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END rw0_rd_out[136] + PIN rw0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.947 0.000 70.965 0.054 ; + END + END rw0_rd_out[137] + PIN rw0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.127 0.000 71.145 0.054 ; + END + END rw0_rd_out[138] + PIN rw0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.307 0.000 71.325 0.054 ; + END + END rw0_rd_out[139] + PIN rw0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.487 0.000 71.505 0.054 ; + END + END rw0_rd_out[140] + PIN rw0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.667 0.000 71.685 0.054 ; + END + END rw0_rd_out[141] + PIN rw0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.847 0.000 71.865 0.054 ; + END + END rw0_rd_out[142] + PIN rw0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.027 0.000 72.045 0.054 ; + END + END rw0_rd_out[143] + PIN rw0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END rw0_rd_out[144] + PIN rw0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.387 0.000 72.405 0.054 ; + END + END rw0_rd_out[145] + PIN rw0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.567 0.000 72.585 0.054 ; + END + END rw0_rd_out[146] + PIN rw0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.747 0.000 72.765 0.054 ; + END + END rw0_rd_out[147] + PIN rw0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.927 0.000 72.945 0.054 ; + END + END rw0_rd_out[148] + PIN rw0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.107 0.000 73.125 0.054 ; + END + END rw0_rd_out[149] + PIN rw0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.287 0.000 73.305 0.054 ; + END + END rw0_rd_out[150] + PIN rw0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.467 0.000 73.485 0.054 ; + END + END rw0_rd_out[151] + PIN rw0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END rw0_rd_out[152] + PIN rw0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.827 0.000 73.845 0.054 ; + END + END rw0_rd_out[153] + PIN rw0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.007 0.000 74.025 0.054 ; + END + END rw0_rd_out[154] + PIN rw0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.187 0.000 74.205 0.054 ; + END + END rw0_rd_out[155] + PIN rw0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.367 0.000 74.385 0.054 ; + END + END rw0_rd_out[156] + PIN rw0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.547 0.000 74.565 0.054 ; + END + END rw0_rd_out[157] + PIN rw0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.727 0.000 74.745 0.054 ; + END + END rw0_rd_out[158] + PIN rw0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.907 0.000 74.925 0.054 ; + END + END rw0_rd_out[159] + PIN rw0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END rw0_rd_out[160] + PIN rw0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.267 0.000 75.285 0.054 ; + END + END rw0_rd_out[161] + PIN rw0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.447 0.000 75.465 0.054 ; + END + END rw0_rd_out[162] + PIN rw0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.627 0.000 75.645 0.054 ; + END + END rw0_rd_out[163] + PIN rw0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.807 0.000 75.825 0.054 ; + END + END rw0_rd_out[164] + PIN rw0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.987 0.000 76.005 0.054 ; + END + END rw0_rd_out[165] + PIN rw0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.167 0.000 76.185 0.054 ; + END + END rw0_rd_out[166] + PIN rw0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.347 0.000 76.365 0.054 ; + END + END rw0_rd_out[167] + PIN rw0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END rw0_rd_out[168] + PIN rw0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.707 0.000 76.725 0.054 ; + END + END rw0_rd_out[169] + PIN rw0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.887 0.000 76.905 0.054 ; + END + END rw0_rd_out[170] + PIN rw0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.067 0.000 77.085 0.054 ; + END + END rw0_rd_out[171] + PIN rw0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.247 0.000 77.265 0.054 ; + END + END rw0_rd_out[172] + PIN rw0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.427 0.000 77.445 0.054 ; + END + END rw0_rd_out[173] + PIN rw0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.607 0.000 77.625 0.054 ; + END + END rw0_rd_out[174] + PIN rw0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.787 0.000 77.805 0.054 ; + END + END rw0_rd_out[175] + PIN rw0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END rw0_rd_out[176] + PIN rw0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.147 0.000 78.165 0.054 ; + END + END rw0_rd_out[177] + PIN rw0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.327 0.000 78.345 0.054 ; + END + END rw0_rd_out[178] + PIN rw0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.507 0.000 78.525 0.054 ; + END + END rw0_rd_out[179] + PIN rw0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.687 0.000 78.705 0.054 ; + END + END rw0_rd_out[180] + PIN rw0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.867 0.000 78.885 0.054 ; + END + END rw0_rd_out[181] + PIN rw0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.047 0.000 79.065 0.054 ; + END + END rw0_rd_out[182] + PIN rw0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.227 0.000 79.245 0.054 ; + END + END rw0_rd_out[183] + PIN rw0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END rw0_rd_out[184] + PIN rw0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.587 0.000 79.605 0.054 ; + END + END rw0_rd_out[185] + PIN rw0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.767 0.000 79.785 0.054 ; + END + END rw0_rd_out[186] + PIN rw0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.947 0.000 79.965 0.054 ; + END + END rw0_rd_out[187] + PIN rw0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.127 0.000 80.145 0.054 ; + END + END rw0_rd_out[188] + PIN rw0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.307 0.000 80.325 0.054 ; + END + END rw0_rd_out[189] + PIN rw0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.487 0.000 80.505 0.054 ; + END + END rw0_rd_out[190] + PIN rw0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.667 0.000 80.685 0.054 ; + END + END rw0_rd_out[191] + PIN rw0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END rw0_rd_out[192] + PIN rw0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.027 0.000 81.045 0.054 ; + END + END rw0_rd_out[193] + PIN rw0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.207 0.000 81.225 0.054 ; + END + END rw0_rd_out[194] + PIN rw0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.387 0.000 81.405 0.054 ; + END + END rw0_rd_out[195] + PIN rw0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.567 0.000 81.585 0.054 ; + END + END rw0_rd_out[196] + PIN rw0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.747 0.000 81.765 0.054 ; + END + END rw0_rd_out[197] + PIN rw0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.927 0.000 81.945 0.054 ; + END + END rw0_rd_out[198] + PIN rw0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.107 0.000 82.125 0.054 ; + END + END rw0_rd_out[199] + PIN rw0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END rw0_rd_out[200] + PIN rw0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.467 0.000 82.485 0.054 ; + END + END rw0_rd_out[201] + PIN rw0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.647 0.000 82.665 0.054 ; + END + END rw0_rd_out[202] + PIN rw0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.827 0.000 82.845 0.054 ; + END + END rw0_rd_out[203] + PIN rw0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.007 0.000 83.025 0.054 ; + END + END rw0_rd_out[204] + PIN rw0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.187 0.000 83.205 0.054 ; + END + END rw0_rd_out[205] + PIN rw0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.367 0.000 83.385 0.054 ; + END + END rw0_rd_out[206] + PIN rw0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.547 0.000 83.565 0.054 ; + END + END rw0_rd_out[207] + PIN rw0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END rw0_rd_out[208] + PIN rw0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.907 0.000 83.925 0.054 ; + END + END rw0_rd_out[209] + PIN rw0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.087 0.000 84.105 0.054 ; + END + END rw0_rd_out[210] + PIN rw0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.267 0.000 84.285 0.054 ; + END + END rw0_rd_out[211] + PIN rw0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.447 0.000 84.465 0.054 ; + END + END rw0_rd_out[212] + PIN rw0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.627 0.000 84.645 0.054 ; + END + END rw0_rd_out[213] + PIN rw0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.807 0.000 84.825 0.054 ; + END + END rw0_rd_out[214] + PIN rw0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.987 0.000 85.005 0.054 ; + END + END rw0_rd_out[215] + PIN rw0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END rw0_rd_out[216] + PIN rw0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.347 0.000 85.365 0.054 ; + END + END rw0_rd_out[217] + PIN rw0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.527 0.000 85.545 0.054 ; + END + END rw0_rd_out[218] + PIN rw0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.707 0.000 85.725 0.054 ; + END + END rw0_rd_out[219] + PIN rw0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.887 0.000 85.905 0.054 ; + END + END rw0_rd_out[220] + PIN rw0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.067 0.000 86.085 0.054 ; + END + END rw0_rd_out[221] + PIN rw0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.247 0.000 86.265 0.054 ; + END + END rw0_rd_out[222] + PIN rw0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.427 0.000 86.445 0.054 ; + END + END rw0_rd_out[223] + PIN rw0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END rw0_rd_out[224] + PIN rw0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.787 0.000 86.805 0.054 ; + END + END rw0_rd_out[225] + PIN rw0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.967 0.000 86.985 0.054 ; + END + END rw0_rd_out[226] + PIN rw0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.147 0.000 87.165 0.054 ; + END + END rw0_rd_out[227] + PIN rw0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.327 0.000 87.345 0.054 ; + END + END rw0_rd_out[228] + PIN rw0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.507 0.000 87.525 0.054 ; + END + END rw0_rd_out[229] + PIN rw0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.687 0.000 87.705 0.054 ; + END + END rw0_rd_out[230] + PIN rw0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.867 0.000 87.885 0.054 ; + END + END rw0_rd_out[231] + PIN rw0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END rw0_rd_out[232] + PIN rw0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.227 0.000 88.245 0.054 ; + END + END rw0_rd_out[233] + PIN rw0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.407 0.000 88.425 0.054 ; + END + END rw0_rd_out[234] + PIN rw0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.587 0.000 88.605 0.054 ; + END + END rw0_rd_out[235] + PIN rw0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.767 0.000 88.785 0.054 ; + END + END rw0_rd_out[236] + PIN rw0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.947 0.000 88.965 0.054 ; + END + END rw0_rd_out[237] + PIN rw0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.127 0.000 89.145 0.054 ; + END + END rw0_rd_out[238] + PIN rw0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.307 0.000 89.325 0.054 ; + END + END rw0_rd_out[239] + PIN rw0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END rw0_rd_out[240] + PIN rw0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.667 0.000 89.685 0.054 ; + END + END rw0_rd_out[241] + PIN rw0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.847 0.000 89.865 0.054 ; + END + END rw0_rd_out[242] + PIN rw0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.027 0.000 90.045 0.054 ; + END + END rw0_rd_out[243] + PIN rw0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.207 0.000 90.225 0.054 ; + END + END rw0_rd_out[244] + PIN rw0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.387 0.000 90.405 0.054 ; + END + END rw0_rd_out[245] + PIN rw0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.567 0.000 90.585 0.054 ; + END + END rw0_rd_out[246] + PIN rw0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.747 0.000 90.765 0.054 ; + END + END rw0_rd_out[247] + PIN rw0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END rw0_rd_out[248] + PIN rw0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.107 0.000 91.125 0.054 ; + END + END rw0_rd_out[249] + PIN rw0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.287 0.000 91.305 0.054 ; + END + END rw0_rd_out[250] + PIN rw0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.467 0.000 91.485 0.054 ; + END + END rw0_rd_out[251] + PIN rw0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.647 0.000 91.665 0.054 ; + END + END rw0_rd_out[252] + PIN rw0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.827 0.000 91.845 0.054 ; + END + END rw0_rd_out[253] + PIN rw0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.007 0.000 92.025 0.054 ; + END + END rw0_rd_out[254] + PIN rw0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.187 0.000 92.205 0.054 ; + END + END rw0_rd_out[255] + PIN rw0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 43.285 46.305 43.339 ; + END + END rw0_rd_out[256] + PIN rw0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.467 43.285 46.485 43.339 ; + END + END rw0_rd_out[257] + PIN rw0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 43.285 46.665 43.339 ; + END + END rw0_rd_out[258] + PIN rw0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.827 43.285 46.845 43.339 ; + END + END rw0_rd_out[259] + PIN rw0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.007 43.285 47.025 43.339 ; + END + END rw0_rd_out[260] + PIN rw0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 43.285 47.205 43.339 ; + END + END rw0_rd_out[261] + PIN rw0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.367 43.285 47.385 43.339 ; + END + END rw0_rd_out[262] + PIN rw0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.547 43.285 47.565 43.339 ; + END + END rw0_rd_out[263] + PIN rw0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 43.285 47.745 43.339 ; + END + END rw0_rd_out[264] + PIN rw0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.907 43.285 47.925 43.339 ; + END + END rw0_rd_out[265] + PIN rw0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.087 43.285 48.105 43.339 ; + END + END rw0_rd_out[266] + PIN rw0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 43.285 48.285 43.339 ; + END + END rw0_rd_out[267] + PIN rw0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.447 43.285 48.465 43.339 ; + END + END rw0_rd_out[268] + PIN rw0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.627 43.285 48.645 43.339 ; + END + END rw0_rd_out[269] + PIN rw0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 43.285 48.825 43.339 ; + END + END rw0_rd_out[270] + PIN rw0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.987 43.285 49.005 43.339 ; + END + END rw0_rd_out[271] + PIN rw0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 43.285 49.185 43.339 ; + END + END rw0_rd_out[272] + PIN rw0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 43.285 49.365 43.339 ; + END + END rw0_rd_out[273] + PIN rw0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.527 43.285 49.545 43.339 ; + END + END rw0_rd_out[274] + PIN rw0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.707 43.285 49.725 43.339 ; + END + END rw0_rd_out[275] + PIN rw0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 43.285 49.905 43.339 ; + END + END rw0_rd_out[276] + PIN rw0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.067 43.285 50.085 43.339 ; + END + END rw0_rd_out[277] + PIN rw0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.247 43.285 50.265 43.339 ; + END + END rw0_rd_out[278] + PIN rw0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 43.285 50.445 43.339 ; + END + END rw0_rd_out[279] + PIN rw0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 43.285 50.625 43.339 ; + END + END rw0_rd_out[280] + PIN rw0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.787 43.285 50.805 43.339 ; + END + END rw0_rd_out[281] + PIN rw0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 43.285 50.985 43.339 ; + END + END rw0_rd_out[282] + PIN rw0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.147 43.285 51.165 43.339 ; + END + END rw0_rd_out[283] + PIN rw0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.327 43.285 51.345 43.339 ; + END + END rw0_rd_out[284] + PIN rw0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 43.285 51.525 43.339 ; + END + END rw0_rd_out[285] + PIN rw0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.687 43.285 51.705 43.339 ; + END + END rw0_rd_out[286] + PIN rw0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.867 43.285 51.885 43.339 ; + END + END rw0_rd_out[287] + PIN rw0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 43.285 52.065 43.339 ; + END + END rw0_rd_out[288] + PIN rw0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.227 43.285 52.245 43.339 ; + END + END rw0_rd_out[289] + PIN rw0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.407 43.285 52.425 43.339 ; + END + END rw0_rd_out[290] + PIN rw0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 43.285 52.605 43.339 ; + END + END rw0_rd_out[291] + PIN rw0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.767 43.285 52.785 43.339 ; + END + END rw0_rd_out[292] + PIN rw0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.947 43.285 52.965 43.339 ; + END + END rw0_rd_out[293] + PIN rw0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 43.285 53.145 43.339 ; + END + END rw0_rd_out[294] + PIN rw0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.307 43.285 53.325 43.339 ; + END + END rw0_rd_out[295] + PIN rw0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 43.285 53.505 43.339 ; + END + END rw0_rd_out[296] + PIN rw0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 43.285 53.685 43.339 ; + END + END rw0_rd_out[297] + PIN rw0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.847 43.285 53.865 43.339 ; + END + END rw0_rd_out[298] + PIN rw0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.027 43.285 54.045 43.339 ; + END + END rw0_rd_out[299] + PIN rw0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 43.285 54.225 43.339 ; + END + END rw0_rd_out[300] + PIN rw0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.387 43.285 54.405 43.339 ; + END + END rw0_rd_out[301] + PIN rw0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.567 43.285 54.585 43.339 ; + END + END rw0_rd_out[302] + PIN rw0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 43.285 54.765 43.339 ; + END + END rw0_rd_out[303] + PIN rw0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 43.285 54.945 43.339 ; + END + END rw0_rd_out[304] + PIN rw0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.107 43.285 55.125 43.339 ; + END + END rw0_rd_out[305] + PIN rw0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 43.285 55.305 43.339 ; + END + END rw0_rd_out[306] + PIN rw0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.467 43.285 55.485 43.339 ; + END + END rw0_rd_out[307] + PIN rw0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.647 43.285 55.665 43.339 ; + END + END rw0_rd_out[308] + PIN rw0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 43.285 55.845 43.339 ; + END + END rw0_rd_out[309] + PIN rw0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.007 43.285 56.025 43.339 ; + END + END rw0_rd_out[310] + PIN rw0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.187 43.285 56.205 43.339 ; + END + END rw0_rd_out[311] + PIN rw0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 43.285 56.385 43.339 ; + END + END rw0_rd_out[312] + PIN rw0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.547 43.285 56.565 43.339 ; + END + END rw0_rd_out[313] + PIN rw0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.727 43.285 56.745 43.339 ; + END + END rw0_rd_out[314] + PIN rw0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 43.285 56.925 43.339 ; + END + END rw0_rd_out[315] + PIN rw0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.087 43.285 57.105 43.339 ; + END + END rw0_rd_out[316] + PIN rw0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.267 43.285 57.285 43.339 ; + END + END rw0_rd_out[317] + PIN rw0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 43.285 57.465 43.339 ; + END + END rw0_rd_out[318] + PIN rw0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.627 43.285 57.645 43.339 ; + END + END rw0_rd_out[319] + PIN rw0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 43.285 57.825 43.339 ; + END + END rw0_rd_out[320] + PIN rw0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 43.285 58.005 43.339 ; + END + END rw0_rd_out[321] + PIN rw0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.167 43.285 58.185 43.339 ; + END + END rw0_rd_out[322] + PIN rw0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.347 43.285 58.365 43.339 ; + END + END rw0_rd_out[323] + PIN rw0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 43.285 58.545 43.339 ; + END + END rw0_rd_out[324] + PIN rw0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.707 43.285 58.725 43.339 ; + END + END rw0_rd_out[325] + PIN rw0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.887 43.285 58.905 43.339 ; + END + END rw0_rd_out[326] + PIN rw0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 43.285 59.085 43.339 ; + END + END rw0_rd_out[327] + PIN rw0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 43.285 59.265 43.339 ; + END + END rw0_rd_out[328] + PIN rw0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.427 43.285 59.445 43.339 ; + END + END rw0_rd_out[329] + PIN rw0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 43.285 59.625 43.339 ; + END + END rw0_rd_out[330] + PIN rw0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.787 43.285 59.805 43.339 ; + END + END rw0_rd_out[331] + PIN rw0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.967 43.285 59.985 43.339 ; + END + END rw0_rd_out[332] + PIN rw0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 43.285 60.165 43.339 ; + END + END rw0_rd_out[333] + PIN rw0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.327 43.285 60.345 43.339 ; + END + END rw0_rd_out[334] + PIN rw0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.507 43.285 60.525 43.339 ; + END + END rw0_rd_out[335] + PIN rw0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 43.285 60.705 43.339 ; + END + END rw0_rd_out[336] + PIN rw0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.867 43.285 60.885 43.339 ; + END + END rw0_rd_out[337] + PIN rw0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.047 43.285 61.065 43.339 ; + END + END rw0_rd_out[338] + PIN rw0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 43.285 61.245 43.339 ; + END + END rw0_rd_out[339] + PIN rw0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.407 43.285 61.425 43.339 ; + END + END rw0_rd_out[340] + PIN rw0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.587 43.285 61.605 43.339 ; + END + END rw0_rd_out[341] + PIN rw0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 43.285 61.785 43.339 ; + END + END rw0_rd_out[342] + PIN rw0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.947 43.285 61.965 43.339 ; + END + END rw0_rd_out[343] + PIN rw0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 43.285 62.145 43.339 ; + END + END rw0_rd_out[344] + PIN rw0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 43.285 62.325 43.339 ; + END + END rw0_rd_out[345] + PIN rw0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.487 43.285 62.505 43.339 ; + END + END rw0_rd_out[346] + PIN rw0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.667 43.285 62.685 43.339 ; + END + END rw0_rd_out[347] + PIN rw0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 43.285 62.865 43.339 ; + END + END rw0_rd_out[348] + PIN rw0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.027 43.285 63.045 43.339 ; + END + END rw0_rd_out[349] + PIN rw0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.207 43.285 63.225 43.339 ; + END + END rw0_rd_out[350] + PIN rw0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 43.285 63.405 43.339 ; + END + END rw0_rd_out[351] + PIN rw0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 43.285 63.585 43.339 ; + END + END rw0_rd_out[352] + PIN rw0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.747 43.285 63.765 43.339 ; + END + END rw0_rd_out[353] + PIN rw0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.927 43.285 63.945 43.339 ; + END + END rw0_rd_out[354] + PIN rw0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.107 43.285 64.125 43.339 ; + END + END rw0_rd_out[355] + PIN rw0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.287 43.285 64.305 43.339 ; + END + END rw0_rd_out[356] + PIN rw0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.467 43.285 64.485 43.339 ; + END + END rw0_rd_out[357] + PIN rw0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.647 43.285 64.665 43.339 ; + END + END rw0_rd_out[358] + PIN rw0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.827 43.285 64.845 43.339 ; + END + END rw0_rd_out[359] + PIN rw0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 43.285 65.025 43.339 ; + END + END rw0_rd_out[360] + PIN rw0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.187 43.285 65.205 43.339 ; + END + END rw0_rd_out[361] + PIN rw0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.367 43.285 65.385 43.339 ; + END + END rw0_rd_out[362] + PIN rw0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.547 43.285 65.565 43.339 ; + END + END rw0_rd_out[363] + PIN rw0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.727 43.285 65.745 43.339 ; + END + END rw0_rd_out[364] + PIN rw0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.907 43.285 65.925 43.339 ; + END + END rw0_rd_out[365] + PIN rw0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.087 43.285 66.105 43.339 ; + END + END rw0_rd_out[366] + PIN rw0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.267 43.285 66.285 43.339 ; + END + END rw0_rd_out[367] + PIN rw0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 43.285 66.465 43.339 ; + END + END rw0_rd_out[368] + PIN rw0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.627 43.285 66.645 43.339 ; + END + END rw0_rd_out[369] + PIN rw0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.807 43.285 66.825 43.339 ; + END + END rw0_rd_out[370] + PIN rw0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.987 43.285 67.005 43.339 ; + END + END rw0_rd_out[371] + PIN rw0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.167 43.285 67.185 43.339 ; + END + END rw0_rd_out[372] + PIN rw0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.347 43.285 67.365 43.339 ; + END + END rw0_rd_out[373] + PIN rw0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.527 43.285 67.545 43.339 ; + END + END rw0_rd_out[374] + PIN rw0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.707 43.285 67.725 43.339 ; + END + END rw0_rd_out[375] + PIN rw0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 43.285 67.905 43.339 ; + END + END rw0_rd_out[376] + PIN rw0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.067 43.285 68.085 43.339 ; + END + END rw0_rd_out[377] + PIN rw0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.247 43.285 68.265 43.339 ; + END + END rw0_rd_out[378] + PIN rw0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.427 43.285 68.445 43.339 ; + END + END rw0_rd_out[379] + PIN rw0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.607 43.285 68.625 43.339 ; + END + END rw0_rd_out[380] + PIN rw0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.787 43.285 68.805 43.339 ; + END + END rw0_rd_out[381] + PIN rw0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.967 43.285 68.985 43.339 ; + END + END rw0_rd_out[382] + PIN rw0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.147 43.285 69.165 43.339 ; + END + END rw0_rd_out[383] + PIN rw0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 43.285 69.345 43.339 ; + END + END rw0_rd_out[384] + PIN rw0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.507 43.285 69.525 43.339 ; + END + END rw0_rd_out[385] + PIN rw0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.687 43.285 69.705 43.339 ; + END + END rw0_rd_out[386] + PIN rw0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.867 43.285 69.885 43.339 ; + END + END rw0_rd_out[387] + PIN rw0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.047 43.285 70.065 43.339 ; + END + END rw0_rd_out[388] + PIN rw0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.227 43.285 70.245 43.339 ; + END + END rw0_rd_out[389] + PIN rw0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.407 43.285 70.425 43.339 ; + END + END rw0_rd_out[390] + PIN rw0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.587 43.285 70.605 43.339 ; + END + END rw0_rd_out[391] + PIN rw0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 43.285 70.785 43.339 ; + END + END rw0_rd_out[392] + PIN rw0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.947 43.285 70.965 43.339 ; + END + END rw0_rd_out[393] + PIN rw0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.127 43.285 71.145 43.339 ; + END + END rw0_rd_out[394] + PIN rw0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.307 43.285 71.325 43.339 ; + END + END rw0_rd_out[395] + PIN rw0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.487 43.285 71.505 43.339 ; + END + END rw0_rd_out[396] + PIN rw0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.667 43.285 71.685 43.339 ; + END + END rw0_rd_out[397] + PIN rw0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.847 43.285 71.865 43.339 ; + END + END rw0_rd_out[398] + PIN rw0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.027 43.285 72.045 43.339 ; + END + END rw0_rd_out[399] + PIN rw0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 43.285 72.225 43.339 ; + END + END rw0_rd_out[400] + PIN rw0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.387 43.285 72.405 43.339 ; + END + END rw0_rd_out[401] + PIN rw0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.567 43.285 72.585 43.339 ; + END + END rw0_rd_out[402] + PIN rw0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.747 43.285 72.765 43.339 ; + END + END rw0_rd_out[403] + PIN rw0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.927 43.285 72.945 43.339 ; + END + END rw0_rd_out[404] + PIN rw0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.107 43.285 73.125 43.339 ; + END + END rw0_rd_out[405] + PIN rw0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.287 43.285 73.305 43.339 ; + END + END rw0_rd_out[406] + PIN rw0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.467 43.285 73.485 43.339 ; + END + END rw0_rd_out[407] + PIN rw0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 43.285 73.665 43.339 ; + END + END rw0_rd_out[408] + PIN rw0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.827 43.285 73.845 43.339 ; + END + END rw0_rd_out[409] + PIN rw0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.007 43.285 74.025 43.339 ; + END + END rw0_rd_out[410] + PIN rw0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.187 43.285 74.205 43.339 ; + END + END rw0_rd_out[411] + PIN rw0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.367 43.285 74.385 43.339 ; + END + END rw0_rd_out[412] + PIN rw0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.547 43.285 74.565 43.339 ; + END + END rw0_rd_out[413] + PIN rw0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.727 43.285 74.745 43.339 ; + END + END rw0_rd_out[414] + PIN rw0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.907 43.285 74.925 43.339 ; + END + END rw0_rd_out[415] + PIN rw0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 43.285 75.105 43.339 ; + END + END rw0_rd_out[416] + PIN rw0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.267 43.285 75.285 43.339 ; + END + END rw0_rd_out[417] + PIN rw0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.447 43.285 75.465 43.339 ; + END + END rw0_rd_out[418] + PIN rw0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.627 43.285 75.645 43.339 ; + END + END rw0_rd_out[419] + PIN rw0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.807 43.285 75.825 43.339 ; + END + END rw0_rd_out[420] + PIN rw0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.987 43.285 76.005 43.339 ; + END + END rw0_rd_out[421] + PIN rw0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.167 43.285 76.185 43.339 ; + END + END rw0_rd_out[422] + PIN rw0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.347 43.285 76.365 43.339 ; + END + END rw0_rd_out[423] + PIN rw0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 43.285 76.545 43.339 ; + END + END rw0_rd_out[424] + PIN rw0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.707 43.285 76.725 43.339 ; + END + END rw0_rd_out[425] + PIN rw0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.887 43.285 76.905 43.339 ; + END + END rw0_rd_out[426] + PIN rw0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.067 43.285 77.085 43.339 ; + END + END rw0_rd_out[427] + PIN rw0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.247 43.285 77.265 43.339 ; + END + END rw0_rd_out[428] + PIN rw0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.427 43.285 77.445 43.339 ; + END + END rw0_rd_out[429] + PIN rw0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.607 43.285 77.625 43.339 ; + END + END rw0_rd_out[430] + PIN rw0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.787 43.285 77.805 43.339 ; + END + END rw0_rd_out[431] + PIN rw0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 43.285 77.985 43.339 ; + END + END rw0_rd_out[432] + PIN rw0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.147 43.285 78.165 43.339 ; + END + END rw0_rd_out[433] + PIN rw0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.327 43.285 78.345 43.339 ; + END + END rw0_rd_out[434] + PIN rw0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.507 43.285 78.525 43.339 ; + END + END rw0_rd_out[435] + PIN rw0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.687 43.285 78.705 43.339 ; + END + END rw0_rd_out[436] + PIN rw0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.867 43.285 78.885 43.339 ; + END + END rw0_rd_out[437] + PIN rw0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.047 43.285 79.065 43.339 ; + END + END rw0_rd_out[438] + PIN rw0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.227 43.285 79.245 43.339 ; + END + END rw0_rd_out[439] + PIN rw0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 43.285 79.425 43.339 ; + END + END rw0_rd_out[440] + PIN rw0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.587 43.285 79.605 43.339 ; + END + END rw0_rd_out[441] + PIN rw0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.767 43.285 79.785 43.339 ; + END + END rw0_rd_out[442] + PIN rw0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.947 43.285 79.965 43.339 ; + END + END rw0_rd_out[443] + PIN rw0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.127 43.285 80.145 43.339 ; + END + END rw0_rd_out[444] + PIN rw0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.307 43.285 80.325 43.339 ; + END + END rw0_rd_out[445] + PIN rw0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.487 43.285 80.505 43.339 ; + END + END rw0_rd_out[446] + PIN rw0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.667 43.285 80.685 43.339 ; + END + END rw0_rd_out[447] + PIN rw0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 43.285 80.865 43.339 ; + END + END rw0_rd_out[448] + PIN rw0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.027 43.285 81.045 43.339 ; + END + END rw0_rd_out[449] + PIN rw0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.207 43.285 81.225 43.339 ; + END + END rw0_rd_out[450] + PIN rw0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.387 43.285 81.405 43.339 ; + END + END rw0_rd_out[451] + PIN rw0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.567 43.285 81.585 43.339 ; + END + END rw0_rd_out[452] + PIN rw0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.747 43.285 81.765 43.339 ; + END + END rw0_rd_out[453] + PIN rw0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.927 43.285 81.945 43.339 ; + END + END rw0_rd_out[454] + PIN rw0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.107 43.285 82.125 43.339 ; + END + END rw0_rd_out[455] + PIN rw0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 43.285 82.305 43.339 ; + END + END rw0_rd_out[456] + PIN rw0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.467 43.285 82.485 43.339 ; + END + END rw0_rd_out[457] + PIN rw0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.647 43.285 82.665 43.339 ; + END + END rw0_rd_out[458] + PIN rw0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.827 43.285 82.845 43.339 ; + END + END rw0_rd_out[459] + PIN rw0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.007 43.285 83.025 43.339 ; + END + END rw0_rd_out[460] + PIN rw0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.187 43.285 83.205 43.339 ; + END + END rw0_rd_out[461] + PIN rw0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.367 43.285 83.385 43.339 ; + END + END rw0_rd_out[462] + PIN rw0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.547 43.285 83.565 43.339 ; + END + END rw0_rd_out[463] + PIN rw0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 43.285 83.745 43.339 ; + END + END rw0_rd_out[464] + PIN rw0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.907 43.285 83.925 43.339 ; + END + END rw0_rd_out[465] + PIN rw0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.087 43.285 84.105 43.339 ; + END + END rw0_rd_out[466] + PIN rw0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.267 43.285 84.285 43.339 ; + END + END rw0_rd_out[467] + PIN rw0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.447 43.285 84.465 43.339 ; + END + END rw0_rd_out[468] + PIN rw0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.627 43.285 84.645 43.339 ; + END + END rw0_rd_out[469] + PIN rw0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.807 43.285 84.825 43.339 ; + END + END rw0_rd_out[470] + PIN rw0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.987 43.285 85.005 43.339 ; + END + END rw0_rd_out[471] + PIN rw0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 43.285 85.185 43.339 ; + END + END rw0_rd_out[472] + PIN rw0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.347 43.285 85.365 43.339 ; + END + END rw0_rd_out[473] + PIN rw0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.527 43.285 85.545 43.339 ; + END + END rw0_rd_out[474] + PIN rw0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.707 43.285 85.725 43.339 ; + END + END rw0_rd_out[475] + PIN rw0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.887 43.285 85.905 43.339 ; + END + END rw0_rd_out[476] + PIN rw0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.067 43.285 86.085 43.339 ; + END + END rw0_rd_out[477] + PIN rw0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.247 43.285 86.265 43.339 ; + END + END rw0_rd_out[478] + PIN rw0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.427 43.285 86.445 43.339 ; + END + END rw0_rd_out[479] + PIN rw0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 43.285 86.625 43.339 ; + END + END rw0_rd_out[480] + PIN rw0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.787 43.285 86.805 43.339 ; + END + END rw0_rd_out[481] + PIN rw0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.967 43.285 86.985 43.339 ; + END + END rw0_rd_out[482] + PIN rw0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.147 43.285 87.165 43.339 ; + END + END rw0_rd_out[483] + PIN rw0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.327 43.285 87.345 43.339 ; + END + END rw0_rd_out[484] + PIN rw0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.507 43.285 87.525 43.339 ; + END + END rw0_rd_out[485] + PIN rw0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.687 43.285 87.705 43.339 ; + END + END rw0_rd_out[486] + PIN rw0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.867 43.285 87.885 43.339 ; + END + END rw0_rd_out[487] + PIN rw0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 43.285 88.065 43.339 ; + END + END rw0_rd_out[488] + PIN rw0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.227 43.285 88.245 43.339 ; + END + END rw0_rd_out[489] + PIN rw0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.407 43.285 88.425 43.339 ; + END + END rw0_rd_out[490] + PIN rw0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.587 43.285 88.605 43.339 ; + END + END rw0_rd_out[491] + PIN rw0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.767 43.285 88.785 43.339 ; + END + END rw0_rd_out[492] + PIN rw0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.947 43.285 88.965 43.339 ; + END + END rw0_rd_out[493] + PIN rw0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.127 43.285 89.145 43.339 ; + END + END rw0_rd_out[494] + PIN rw0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.307 43.285 89.325 43.339 ; + END + END rw0_rd_out[495] + PIN rw0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 43.285 89.505 43.339 ; + END + END rw0_rd_out[496] + PIN rw0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.667 43.285 89.685 43.339 ; + END + END rw0_rd_out[497] + PIN rw0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.847 43.285 89.865 43.339 ; + END + END rw0_rd_out[498] + PIN rw0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.027 43.285 90.045 43.339 ; + END + END rw0_rd_out[499] + PIN rw0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.207 43.285 90.225 43.339 ; + END + END rw0_rd_out[500] + PIN rw0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.387 43.285 90.405 43.339 ; + END + END rw0_rd_out[501] + PIN rw0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.567 43.285 90.585 43.339 ; + END + END rw0_rd_out[502] + PIN rw0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.747 43.285 90.765 43.339 ; + END + END rw0_rd_out[503] + PIN rw0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 43.285 90.945 43.339 ; + END + END rw0_rd_out[504] + PIN rw0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.107 43.285 91.125 43.339 ; + END + END rw0_rd_out[505] + PIN rw0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.287 43.285 91.305 43.339 ; + END + END rw0_rd_out[506] + PIN rw0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.467 43.285 91.485 43.339 ; + END + END rw0_rd_out[507] + PIN rw0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.647 43.285 91.665 43.339 ; + END + END rw0_rd_out[508] + PIN rw0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.827 43.285 91.845 43.339 ; + END + END rw0_rd_out[509] + PIN rw0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.007 43.285 92.025 43.339 ; + END + END rw0_rd_out[510] + PIN rw0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.187 43.285 92.205 43.339 ; + END + END rw0_rd_out[511] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.284 0.072 37.308 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 37.140 104.012 37.164 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 37.284 104.012 37.308 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 37.428 104.012 37.452 ; + END + END rw0_addr_in[6] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 43.285 92.385 43.339 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.547 43.285 92.565 43.339 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.727 43.285 92.745 43.339 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 103.796 0.336 ; + RECT 0.216 1.008 103.796 1.104 ; + RECT 0.216 1.776 103.796 1.872 ; + RECT 0.216 2.544 103.796 2.640 ; + RECT 0.216 3.312 103.796 3.408 ; + RECT 0.216 4.080 103.796 4.176 ; + RECT 0.216 4.848 103.796 4.944 ; + RECT 0.216 5.616 103.796 5.712 ; + RECT 0.216 6.384 103.796 6.480 ; + RECT 0.216 7.152 103.796 7.248 ; + RECT 0.216 7.920 103.796 8.016 ; + RECT 0.216 8.688 103.796 8.784 ; + RECT 0.216 9.456 103.796 9.552 ; + RECT 0.216 10.224 103.796 10.320 ; + RECT 0.216 10.992 103.796 11.088 ; + RECT 0.216 11.760 103.796 11.856 ; + RECT 0.216 12.528 103.796 12.624 ; + RECT 0.216 13.296 103.796 13.392 ; + RECT 0.216 14.064 103.796 14.160 ; + RECT 0.216 14.832 103.796 14.928 ; + RECT 0.216 15.600 103.796 15.696 ; + RECT 0.216 16.368 103.796 16.464 ; + RECT 0.216 17.136 103.796 17.232 ; + RECT 0.216 17.904 103.796 18.000 ; + RECT 0.216 18.672 103.796 18.768 ; + RECT 0.216 19.440 103.796 19.536 ; + RECT 0.216 20.208 103.796 20.304 ; + RECT 0.216 20.976 103.796 21.072 ; + RECT 0.216 21.744 103.796 21.840 ; + RECT 0.216 22.512 103.796 22.608 ; + RECT 0.216 23.280 103.796 23.376 ; + RECT 0.216 24.048 103.796 24.144 ; + RECT 0.216 24.816 103.796 24.912 ; + RECT 0.216 25.584 103.796 25.680 ; + RECT 0.216 26.352 103.796 26.448 ; + RECT 0.216 27.120 103.796 27.216 ; + RECT 0.216 27.888 103.796 27.984 ; + RECT 0.216 28.656 103.796 28.752 ; + RECT 0.216 29.424 103.796 29.520 ; + RECT 0.216 30.192 103.796 30.288 ; + RECT 0.216 30.960 103.796 31.056 ; + RECT 0.216 31.728 103.796 31.824 ; + RECT 0.216 32.496 103.796 32.592 ; + RECT 0.216 33.264 103.796 33.360 ; + RECT 0.216 34.032 103.796 34.128 ; + RECT 0.216 34.800 103.796 34.896 ; + RECT 0.216 35.568 103.796 35.664 ; + RECT 0.216 36.336 103.796 36.432 ; + RECT 0.216 37.104 103.796 37.200 ; + RECT 0.216 37.872 103.796 37.968 ; + RECT 0.216 38.640 103.796 38.736 ; + RECT 0.216 39.408 103.796 39.504 ; + RECT 0.216 40.176 103.796 40.272 ; + RECT 0.216 40.944 103.796 41.040 ; + RECT 0.216 41.712 103.796 41.808 ; + RECT 0.216 42.480 103.796 42.576 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 103.796 0.336 ; + RECT 0.216 1.008 103.796 1.104 ; + RECT 0.216 1.776 103.796 1.872 ; + RECT 0.216 2.544 103.796 2.640 ; + RECT 0.216 3.312 103.796 3.408 ; + RECT 0.216 4.080 103.796 4.176 ; + RECT 0.216 4.848 103.796 4.944 ; + RECT 0.216 5.616 103.796 5.712 ; + RECT 0.216 6.384 103.796 6.480 ; + RECT 0.216 7.152 103.796 7.248 ; + RECT 0.216 7.920 103.796 8.016 ; + RECT 0.216 8.688 103.796 8.784 ; + RECT 0.216 9.456 103.796 9.552 ; + RECT 0.216 10.224 103.796 10.320 ; + RECT 0.216 10.992 103.796 11.088 ; + RECT 0.216 11.760 103.796 11.856 ; + RECT 0.216 12.528 103.796 12.624 ; + RECT 0.216 13.296 103.796 13.392 ; + RECT 0.216 14.064 103.796 14.160 ; + RECT 0.216 14.832 103.796 14.928 ; + RECT 0.216 15.600 103.796 15.696 ; + RECT 0.216 16.368 103.796 16.464 ; + RECT 0.216 17.136 103.796 17.232 ; + RECT 0.216 17.904 103.796 18.000 ; + RECT 0.216 18.672 103.796 18.768 ; + RECT 0.216 19.440 103.796 19.536 ; + RECT 0.216 20.208 103.796 20.304 ; + RECT 0.216 20.976 103.796 21.072 ; + RECT 0.216 21.744 103.796 21.840 ; + RECT 0.216 22.512 103.796 22.608 ; + RECT 0.216 23.280 103.796 23.376 ; + RECT 0.216 24.048 103.796 24.144 ; + RECT 0.216 24.816 103.796 24.912 ; + RECT 0.216 25.584 103.796 25.680 ; + RECT 0.216 26.352 103.796 26.448 ; + RECT 0.216 27.120 103.796 27.216 ; + RECT 0.216 27.888 103.796 27.984 ; + RECT 0.216 28.656 103.796 28.752 ; + RECT 0.216 29.424 103.796 29.520 ; + RECT 0.216 30.192 103.796 30.288 ; + RECT 0.216 30.960 103.796 31.056 ; + RECT 0.216 31.728 103.796 31.824 ; + RECT 0.216 32.496 103.796 32.592 ; + RECT 0.216 33.264 103.796 33.360 ; + RECT 0.216 34.032 103.796 34.128 ; + RECT 0.216 34.800 103.796 34.896 ; + RECT 0.216 35.568 103.796 35.664 ; + RECT 0.216 36.336 103.796 36.432 ; + RECT 0.216 37.104 103.796 37.200 ; + RECT 0.216 37.872 103.796 37.968 ; + RECT 0.216 38.640 103.796 38.736 ; + RECT 0.216 39.408 103.796 39.504 ; + RECT 0.216 40.176 103.796 40.272 ; + RECT 0.216 40.944 103.796 41.040 ; + RECT 0.216 41.712 103.796 41.808 ; + RECT 0.216 42.480 103.796 42.576 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 104.012 43.339 ; + LAYER M2 ; + RECT 0 0 104.012 43.339 ; + LAYER M3 ; + RECT 0 0 104.012 43.339 ; + LAYER M4 ; + RECT 0 0 104.012 43.339 ; + END +END fakeram_512x128_1rw + +END LIBRARY diff --git a/designs/asap7/coralnpu/sram/lef/fakeram_595x8_1r1w.lef b/designs/asap7/coralnpu/sram/lef/fakeram_595x8_1r1w.lef new file mode 100644 index 0000000..e2bbd50 --- /dev/null +++ b/designs/asap7/coralnpu/sram/lef/fakeram_595x8_1r1w.lef @@ -0,0 +1,16300 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_595x8_1r1w + FOREIGN fakeram_595x8_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 189.696 BY 53.048 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.420 0.072 0.444 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.148 0.072 2.172 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.012 0.072 3.036 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.452 0.072 4.476 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.468 0.072 6.492 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.908 0.072 7.932 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.772 0.072 8.796 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.060 0.072 9.084 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.924 0.072 9.948 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.500 0.072 10.524 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.788 0.072 10.812 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.652 0.072 11.676 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.228 0.072 12.252 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.244 0.072 14.268 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.108 0.072 15.132 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.684 0.072 15.708 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.972 0.072 15.996 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.548 0.072 16.572 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.700 0.072 17.724 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.564 0.072 18.588 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.140 0.072 19.164 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.004 0.072 20.028 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.292 0.072 20.316 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.868 0.072 20.892 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.156 0.072 21.180 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 0.276 189.696 0.300 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 0.420 189.696 0.444 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 0.564 189.696 0.588 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 0.708 189.696 0.732 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 0.852 189.696 0.876 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 0.996 189.696 1.020 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 1.140 189.696 1.164 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 1.284 189.696 1.308 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 1.428 189.696 1.452 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 1.572 189.696 1.596 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 1.716 189.696 1.740 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 1.860 189.696 1.884 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.004 189.696 2.028 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.148 189.696 2.172 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.292 189.696 2.316 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.436 189.696 2.460 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.580 189.696 2.604 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.724 189.696 2.748 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 2.868 189.696 2.892 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.012 189.696 3.036 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.156 189.696 3.180 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.300 189.696 3.324 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.444 189.696 3.468 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.588 189.696 3.612 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.732 189.696 3.756 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 3.876 189.696 3.900 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.020 189.696 4.044 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.164 189.696 4.188 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.308 189.696 4.332 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.452 189.696 4.476 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.596 189.696 4.620 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.740 189.696 4.764 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 4.884 189.696 4.908 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.028 189.696 5.052 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.172 189.696 5.196 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.316 189.696 5.340 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.460 189.696 5.484 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.604 189.696 5.628 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.748 189.696 5.772 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 5.892 189.696 5.916 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.036 189.696 6.060 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.180 189.696 6.204 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.324 189.696 6.348 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.468 189.696 6.492 ; + END + END w0_wmask_in[192] + PIN w0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.612 189.696 6.636 ; + END + END w0_wmask_in[193] + PIN w0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.756 189.696 6.780 ; + END + END w0_wmask_in[194] + PIN w0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 6.900 189.696 6.924 ; + END + END w0_wmask_in[195] + PIN w0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.044 189.696 7.068 ; + END + END w0_wmask_in[196] + PIN w0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.188 189.696 7.212 ; + END + END w0_wmask_in[197] + PIN w0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.332 189.696 7.356 ; + END + END w0_wmask_in[198] + PIN w0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.476 189.696 7.500 ; + END + END w0_wmask_in[199] + PIN w0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.620 189.696 7.644 ; + END + END w0_wmask_in[200] + PIN w0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.764 189.696 7.788 ; + END + END w0_wmask_in[201] + PIN w0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 7.908 189.696 7.932 ; + END + END w0_wmask_in[202] + PIN w0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.052 189.696 8.076 ; + END + END w0_wmask_in[203] + PIN w0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.196 189.696 8.220 ; + END + END w0_wmask_in[204] + PIN w0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.340 189.696 8.364 ; + END + END w0_wmask_in[205] + PIN w0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.484 189.696 8.508 ; + END + END w0_wmask_in[206] + PIN w0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.628 189.696 8.652 ; + END + END w0_wmask_in[207] + PIN w0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.772 189.696 8.796 ; + END + END w0_wmask_in[208] + PIN w0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 8.916 189.696 8.940 ; + END + END w0_wmask_in[209] + PIN w0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.060 189.696 9.084 ; + END + END w0_wmask_in[210] + PIN w0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.204 189.696 9.228 ; + END + END w0_wmask_in[211] + PIN w0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.348 189.696 9.372 ; + END + END w0_wmask_in[212] + PIN w0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.492 189.696 9.516 ; + END + END w0_wmask_in[213] + PIN w0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.636 189.696 9.660 ; + END + END w0_wmask_in[214] + PIN w0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.780 189.696 9.804 ; + END + END w0_wmask_in[215] + PIN w0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 9.924 189.696 9.948 ; + END + END w0_wmask_in[216] + PIN w0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.068 189.696 10.092 ; + END + END w0_wmask_in[217] + PIN w0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.212 189.696 10.236 ; + END + END w0_wmask_in[218] + PIN w0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.356 189.696 10.380 ; + END + END w0_wmask_in[219] + PIN w0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.500 189.696 10.524 ; + END + END w0_wmask_in[220] + PIN w0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.644 189.696 10.668 ; + END + END w0_wmask_in[221] + PIN w0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.788 189.696 10.812 ; + END + END w0_wmask_in[222] + PIN w0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 10.932 189.696 10.956 ; + END + END w0_wmask_in[223] + PIN w0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.076 189.696 11.100 ; + END + END w0_wmask_in[224] + PIN w0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.220 189.696 11.244 ; + END + END w0_wmask_in[225] + PIN w0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.364 189.696 11.388 ; + END + END w0_wmask_in[226] + PIN w0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.508 189.696 11.532 ; + END + END w0_wmask_in[227] + PIN w0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.652 189.696 11.676 ; + END + END w0_wmask_in[228] + PIN w0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.796 189.696 11.820 ; + END + END w0_wmask_in[229] + PIN w0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 11.940 189.696 11.964 ; + END + END w0_wmask_in[230] + PIN w0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.084 189.696 12.108 ; + END + END w0_wmask_in[231] + PIN w0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.228 189.696 12.252 ; + END + END w0_wmask_in[232] + PIN w0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.372 189.696 12.396 ; + END + END w0_wmask_in[233] + PIN w0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.516 189.696 12.540 ; + END + END w0_wmask_in[234] + PIN w0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.660 189.696 12.684 ; + END + END w0_wmask_in[235] + PIN w0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.804 189.696 12.828 ; + END + END w0_wmask_in[236] + PIN w0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 12.948 189.696 12.972 ; + END + END w0_wmask_in[237] + PIN w0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.092 189.696 13.116 ; + END + END w0_wmask_in[238] + PIN w0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.236 189.696 13.260 ; + END + END w0_wmask_in[239] + PIN w0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.380 189.696 13.404 ; + END + END w0_wmask_in[240] + PIN w0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.524 189.696 13.548 ; + END + END w0_wmask_in[241] + PIN w0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.668 189.696 13.692 ; + END + END w0_wmask_in[242] + PIN w0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.812 189.696 13.836 ; + END + END w0_wmask_in[243] + PIN w0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 13.956 189.696 13.980 ; + END + END w0_wmask_in[244] + PIN w0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.100 189.696 14.124 ; + END + END w0_wmask_in[245] + PIN w0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.244 189.696 14.268 ; + END + END w0_wmask_in[246] + PIN w0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.388 189.696 14.412 ; + END + END w0_wmask_in[247] + PIN w0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.532 189.696 14.556 ; + END + END w0_wmask_in[248] + PIN w0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.676 189.696 14.700 ; + END + END w0_wmask_in[249] + PIN w0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.820 189.696 14.844 ; + END + END w0_wmask_in[250] + PIN w0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 14.964 189.696 14.988 ; + END + END w0_wmask_in[251] + PIN w0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.108 189.696 15.132 ; + END + END w0_wmask_in[252] + PIN w0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.252 189.696 15.276 ; + END + END w0_wmask_in[253] + PIN w0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.396 189.696 15.420 ; + END + END w0_wmask_in[254] + PIN w0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.540 189.696 15.564 ; + END + END w0_wmask_in[255] + PIN w0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.684 189.696 15.708 ; + END + END w0_wmask_in[256] + PIN w0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.828 189.696 15.852 ; + END + END w0_wmask_in[257] + PIN w0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 15.972 189.696 15.996 ; + END + END w0_wmask_in[258] + PIN w0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.116 189.696 16.140 ; + END + END w0_wmask_in[259] + PIN w0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.260 189.696 16.284 ; + END + END w0_wmask_in[260] + PIN w0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.404 189.696 16.428 ; + END + END w0_wmask_in[261] + PIN w0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.548 189.696 16.572 ; + END + END w0_wmask_in[262] + PIN w0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.692 189.696 16.716 ; + END + END w0_wmask_in[263] + PIN w0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.836 189.696 16.860 ; + END + END w0_wmask_in[264] + PIN w0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 16.980 189.696 17.004 ; + END + END w0_wmask_in[265] + PIN w0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.124 189.696 17.148 ; + END + END w0_wmask_in[266] + PIN w0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.268 189.696 17.292 ; + END + END w0_wmask_in[267] + PIN w0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.412 189.696 17.436 ; + END + END w0_wmask_in[268] + PIN w0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.556 189.696 17.580 ; + END + END w0_wmask_in[269] + PIN w0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.700 189.696 17.724 ; + END + END w0_wmask_in[270] + PIN w0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.844 189.696 17.868 ; + END + END w0_wmask_in[271] + PIN w0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 17.988 189.696 18.012 ; + END + END w0_wmask_in[272] + PIN w0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.132 189.696 18.156 ; + END + END w0_wmask_in[273] + PIN w0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.276 189.696 18.300 ; + END + END w0_wmask_in[274] + PIN w0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.420 189.696 18.444 ; + END + END w0_wmask_in[275] + PIN w0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.564 189.696 18.588 ; + END + END w0_wmask_in[276] + PIN w0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.708 189.696 18.732 ; + END + END w0_wmask_in[277] + PIN w0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.852 189.696 18.876 ; + END + END w0_wmask_in[278] + PIN w0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 18.996 189.696 19.020 ; + END + END w0_wmask_in[279] + PIN w0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 19.140 189.696 19.164 ; + END + END w0_wmask_in[280] + PIN w0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 19.284 189.696 19.308 ; + END + END w0_wmask_in[281] + PIN w0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 19.428 189.696 19.452 ; + END + END w0_wmask_in[282] + PIN w0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 19.572 189.696 19.596 ; + END + END w0_wmask_in[283] + PIN w0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 19.716 189.696 19.740 ; + END + END w0_wmask_in[284] + PIN w0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 19.860 189.696 19.884 ; + END + END w0_wmask_in[285] + PIN w0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.004 189.696 20.028 ; + END + END w0_wmask_in[286] + PIN w0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.148 189.696 20.172 ; + END + END w0_wmask_in[287] + PIN w0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.292 189.696 20.316 ; + END + END w0_wmask_in[288] + PIN w0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.436 189.696 20.460 ; + END + END w0_wmask_in[289] + PIN w0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.580 189.696 20.604 ; + END + END w0_wmask_in[290] + PIN w0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.724 189.696 20.748 ; + END + END w0_wmask_in[291] + PIN w0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 20.868 189.696 20.892 ; + END + END w0_wmask_in[292] + PIN w0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.012 189.696 21.036 ; + END + END w0_wmask_in[293] + PIN w0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.156 189.696 21.180 ; + END + END w0_wmask_in[294] + PIN w0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.300 189.696 21.324 ; + END + END w0_wmask_in[295] + PIN w0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.444 189.696 21.468 ; + END + END w0_wmask_in[296] + PIN w0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.588 189.696 21.612 ; + END + END w0_wmask_in[297] + PIN w0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 52.994 0.225 53.048 ; + END + END w0_wmask_in[298] + PIN w0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 52.994 0.513 53.048 ; + END + END w0_wmask_in[299] + PIN w0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 52.994 0.801 53.048 ; + END + END w0_wmask_in[300] + PIN w0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 52.994 1.089 53.048 ; + END + END w0_wmask_in[301] + PIN w0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 52.994 1.377 53.048 ; + END + END w0_wmask_in[302] + PIN w0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 52.994 1.665 53.048 ; + END + END w0_wmask_in[303] + PIN w0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 52.994 1.953 53.048 ; + END + END w0_wmask_in[304] + PIN w0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 52.994 2.241 53.048 ; + END + END w0_wmask_in[305] + PIN w0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 52.994 2.529 53.048 ; + END + END w0_wmask_in[306] + PIN w0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 52.994 2.817 53.048 ; + END + END w0_wmask_in[307] + PIN w0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 52.994 3.105 53.048 ; + END + END w0_wmask_in[308] + PIN w0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 52.994 3.393 53.048 ; + END + END w0_wmask_in[309] + PIN w0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 52.994 3.681 53.048 ; + END + END w0_wmask_in[310] + PIN w0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 52.994 3.969 53.048 ; + END + END w0_wmask_in[311] + PIN w0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 52.994 4.257 53.048 ; + END + END w0_wmask_in[312] + PIN w0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 52.994 4.545 53.048 ; + END + END w0_wmask_in[313] + PIN w0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 52.994 4.833 53.048 ; + END + END w0_wmask_in[314] + PIN w0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 52.994 5.121 53.048 ; + END + END w0_wmask_in[315] + PIN w0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 52.994 5.409 53.048 ; + END + END w0_wmask_in[316] + PIN w0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 52.994 5.697 53.048 ; + END + END w0_wmask_in[317] + PIN w0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 52.994 5.985 53.048 ; + END + END w0_wmask_in[318] + PIN w0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 52.994 6.273 53.048 ; + END + END w0_wmask_in[319] + PIN w0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 52.994 6.561 53.048 ; + END + END w0_wmask_in[320] + PIN w0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 52.994 6.849 53.048 ; + END + END w0_wmask_in[321] + PIN w0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 52.994 7.137 53.048 ; + END + END w0_wmask_in[322] + PIN w0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 52.994 7.425 53.048 ; + END + END w0_wmask_in[323] + PIN w0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 52.994 7.713 53.048 ; + END + END w0_wmask_in[324] + PIN w0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 52.994 8.001 53.048 ; + END + END w0_wmask_in[325] + PIN w0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 52.994 8.289 53.048 ; + END + END w0_wmask_in[326] + PIN w0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 52.994 8.577 53.048 ; + END + END w0_wmask_in[327] + PIN w0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 52.994 8.865 53.048 ; + END + END w0_wmask_in[328] + PIN w0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 52.994 9.153 53.048 ; + END + END w0_wmask_in[329] + PIN w0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 52.994 9.441 53.048 ; + END + END w0_wmask_in[330] + PIN w0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 52.994 9.729 53.048 ; + END + END w0_wmask_in[331] + PIN w0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 52.994 10.017 53.048 ; + END + END w0_wmask_in[332] + PIN w0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 52.994 10.305 53.048 ; + END + END w0_wmask_in[333] + PIN w0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 52.994 10.593 53.048 ; + END + END w0_wmask_in[334] + PIN w0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 52.994 10.881 53.048 ; + END + END w0_wmask_in[335] + PIN w0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 52.994 11.169 53.048 ; + END + END w0_wmask_in[336] + PIN w0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 52.994 11.457 53.048 ; + END + END w0_wmask_in[337] + PIN w0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 52.994 11.745 53.048 ; + END + END w0_wmask_in[338] + PIN w0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 52.994 12.033 53.048 ; + END + END w0_wmask_in[339] + PIN w0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 52.994 12.321 53.048 ; + END + END w0_wmask_in[340] + PIN w0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 52.994 12.609 53.048 ; + END + END w0_wmask_in[341] + PIN w0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 52.994 12.897 53.048 ; + END + END w0_wmask_in[342] + PIN w0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 52.994 13.185 53.048 ; + END + END w0_wmask_in[343] + PIN w0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 52.994 13.473 53.048 ; + END + END w0_wmask_in[344] + PIN w0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 52.994 13.761 53.048 ; + END + END w0_wmask_in[345] + PIN w0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 52.994 14.049 53.048 ; + END + END w0_wmask_in[346] + PIN w0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 52.994 14.337 53.048 ; + END + END w0_wmask_in[347] + PIN w0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 52.994 14.625 53.048 ; + END + END w0_wmask_in[348] + PIN w0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 52.994 14.913 53.048 ; + END + END w0_wmask_in[349] + PIN w0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 52.994 15.201 53.048 ; + END + END w0_wmask_in[350] + PIN w0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 52.994 15.489 53.048 ; + END + END w0_wmask_in[351] + PIN w0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 52.994 15.777 53.048 ; + END + END w0_wmask_in[352] + PIN w0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 52.994 16.065 53.048 ; + END + END w0_wmask_in[353] + PIN w0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 52.994 16.353 53.048 ; + END + END w0_wmask_in[354] + PIN w0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 52.994 16.641 53.048 ; + END + END w0_wmask_in[355] + PIN w0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 52.994 16.929 53.048 ; + END + END w0_wmask_in[356] + PIN w0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 52.994 17.217 53.048 ; + END + END w0_wmask_in[357] + PIN w0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 52.994 17.505 53.048 ; + END + END w0_wmask_in[358] + PIN w0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 52.994 17.793 53.048 ; + END + END w0_wmask_in[359] + PIN w0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 52.994 18.081 53.048 ; + END + END w0_wmask_in[360] + PIN w0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 52.994 18.369 53.048 ; + END + END w0_wmask_in[361] + PIN w0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 52.994 18.657 53.048 ; + END + END w0_wmask_in[362] + PIN w0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 52.994 18.945 53.048 ; + END + END w0_wmask_in[363] + PIN w0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 52.994 19.233 53.048 ; + END + END w0_wmask_in[364] + PIN w0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 52.994 19.521 53.048 ; + END + END w0_wmask_in[365] + PIN w0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 52.994 19.809 53.048 ; + END + END w0_wmask_in[366] + PIN w0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 52.994 20.097 53.048 ; + END + END w0_wmask_in[367] + PIN w0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 52.994 20.385 53.048 ; + END + END w0_wmask_in[368] + PIN w0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 52.994 20.673 53.048 ; + END + END w0_wmask_in[369] + PIN w0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 52.994 20.961 53.048 ; + END + END w0_wmask_in[370] + PIN w0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 52.994 21.249 53.048 ; + END + END w0_wmask_in[371] + PIN w0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 52.994 21.537 53.048 ; + END + END w0_wmask_in[372] + PIN w0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 52.994 21.825 53.048 ; + END + END w0_wmask_in[373] + PIN w0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 52.994 22.113 53.048 ; + END + END w0_wmask_in[374] + PIN w0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 52.994 22.401 53.048 ; + END + END w0_wmask_in[375] + PIN w0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 52.994 22.689 53.048 ; + END + END w0_wmask_in[376] + PIN w0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 52.994 22.977 53.048 ; + END + END w0_wmask_in[377] + PIN w0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 52.994 23.265 53.048 ; + END + END w0_wmask_in[378] + PIN w0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 52.994 23.553 53.048 ; + END + END w0_wmask_in[379] + PIN w0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 52.994 23.841 53.048 ; + END + END w0_wmask_in[380] + PIN w0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 52.994 24.129 53.048 ; + END + END w0_wmask_in[381] + PIN w0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 52.994 24.417 53.048 ; + END + END w0_wmask_in[382] + PIN w0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 52.994 24.705 53.048 ; + END + END w0_wmask_in[383] + PIN w0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 52.994 24.993 53.048 ; + END + END w0_wmask_in[384] + PIN w0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 52.994 25.281 53.048 ; + END + END w0_wmask_in[385] + PIN w0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 52.994 25.569 53.048 ; + END + END w0_wmask_in[386] + PIN w0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 52.994 25.857 53.048 ; + END + END w0_wmask_in[387] + PIN w0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 52.994 26.145 53.048 ; + END + END w0_wmask_in[388] + PIN w0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 52.994 26.433 53.048 ; + END + END w0_wmask_in[389] + PIN w0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 52.994 26.721 53.048 ; + END + END w0_wmask_in[390] + PIN w0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 52.994 27.009 53.048 ; + END + END w0_wmask_in[391] + PIN w0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 52.994 27.297 53.048 ; + END + END w0_wmask_in[392] + PIN w0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 52.994 27.585 53.048 ; + END + END w0_wmask_in[393] + PIN w0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 52.994 27.873 53.048 ; + END + END w0_wmask_in[394] + PIN w0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 52.994 28.161 53.048 ; + END + END w0_wmask_in[395] + PIN w0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 52.994 28.449 53.048 ; + END + END w0_wmask_in[396] + PIN w0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 52.994 28.737 53.048 ; + END + END w0_wmask_in[397] + PIN w0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 52.994 29.025 53.048 ; + END + END w0_wmask_in[398] + PIN w0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 52.994 29.313 53.048 ; + END + END w0_wmask_in[399] + PIN w0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 52.994 29.601 53.048 ; + END + END w0_wmask_in[400] + PIN w0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 52.994 29.889 53.048 ; + END + END w0_wmask_in[401] + PIN w0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 52.994 30.177 53.048 ; + END + END w0_wmask_in[402] + PIN w0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 52.994 30.465 53.048 ; + END + END w0_wmask_in[403] + PIN w0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 52.994 30.753 53.048 ; + END + END w0_wmask_in[404] + PIN w0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 52.994 31.041 53.048 ; + END + END w0_wmask_in[405] + PIN w0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 52.994 31.329 53.048 ; + END + END w0_wmask_in[406] + PIN w0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 52.994 31.617 53.048 ; + END + END w0_wmask_in[407] + PIN w0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 52.994 31.905 53.048 ; + END + END w0_wmask_in[408] + PIN w0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 52.994 32.193 53.048 ; + END + END w0_wmask_in[409] + PIN w0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 52.994 32.481 53.048 ; + END + END w0_wmask_in[410] + PIN w0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 52.994 32.769 53.048 ; + END + END w0_wmask_in[411] + PIN w0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 52.994 33.057 53.048 ; + END + END w0_wmask_in[412] + PIN w0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 52.994 33.345 53.048 ; + END + END w0_wmask_in[413] + PIN w0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 52.994 33.633 53.048 ; + END + END w0_wmask_in[414] + PIN w0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 52.994 33.921 53.048 ; + END + END w0_wmask_in[415] + PIN w0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 52.994 34.209 53.048 ; + END + END w0_wmask_in[416] + PIN w0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 52.994 34.497 53.048 ; + END + END w0_wmask_in[417] + PIN w0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 52.994 34.785 53.048 ; + END + END w0_wmask_in[418] + PIN w0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 52.994 35.073 53.048 ; + END + END w0_wmask_in[419] + PIN w0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 52.994 35.361 53.048 ; + END + END w0_wmask_in[420] + PIN w0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 52.994 35.649 53.048 ; + END + END w0_wmask_in[421] + PIN w0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 52.994 35.937 53.048 ; + END + END w0_wmask_in[422] + PIN w0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 52.994 36.225 53.048 ; + END + END w0_wmask_in[423] + PIN w0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 52.994 36.513 53.048 ; + END + END w0_wmask_in[424] + PIN w0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 52.994 36.801 53.048 ; + END + END w0_wmask_in[425] + PIN w0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 52.994 37.089 53.048 ; + END + END w0_wmask_in[426] + PIN w0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 52.994 37.377 53.048 ; + END + END w0_wmask_in[427] + PIN w0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 52.994 37.665 53.048 ; + END + END w0_wmask_in[428] + PIN w0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 52.994 37.953 53.048 ; + END + END w0_wmask_in[429] + PIN w0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 52.994 38.241 53.048 ; + END + END w0_wmask_in[430] + PIN w0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 52.994 38.529 53.048 ; + END + END w0_wmask_in[431] + PIN w0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 52.994 38.817 53.048 ; + END + END w0_wmask_in[432] + PIN w0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 52.994 39.105 53.048 ; + END + END w0_wmask_in[433] + PIN w0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 52.994 39.393 53.048 ; + END + END w0_wmask_in[434] + PIN w0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 52.994 39.681 53.048 ; + END + END w0_wmask_in[435] + PIN w0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 52.994 39.969 53.048 ; + END + END w0_wmask_in[436] + PIN w0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 52.994 40.257 53.048 ; + END + END w0_wmask_in[437] + PIN w0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 52.994 40.545 53.048 ; + END + END w0_wmask_in[438] + PIN w0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 52.994 40.833 53.048 ; + END + END w0_wmask_in[439] + PIN w0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 52.994 41.121 53.048 ; + END + END w0_wmask_in[440] + PIN w0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 52.994 41.409 53.048 ; + END + END w0_wmask_in[441] + PIN w0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 52.994 41.697 53.048 ; + END + END w0_wmask_in[442] + PIN w0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 52.994 41.985 53.048 ; + END + END w0_wmask_in[443] + PIN w0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 52.994 42.273 53.048 ; + END + END w0_wmask_in[444] + PIN w0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 52.994 42.561 53.048 ; + END + END w0_wmask_in[445] + PIN w0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 52.994 42.849 53.048 ; + END + END w0_wmask_in[446] + PIN w0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 52.994 43.137 53.048 ; + END + END w0_wmask_in[447] + PIN w0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 52.994 43.425 53.048 ; + END + END w0_wmask_in[448] + PIN w0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 52.994 43.713 53.048 ; + END + END w0_wmask_in[449] + PIN w0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 52.994 44.001 53.048 ; + END + END w0_wmask_in[450] + PIN w0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 52.994 44.289 53.048 ; + END + END w0_wmask_in[451] + PIN w0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 52.994 44.577 53.048 ; + END + END w0_wmask_in[452] + PIN w0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 52.994 44.865 53.048 ; + END + END w0_wmask_in[453] + PIN w0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 52.994 45.153 53.048 ; + END + END w0_wmask_in[454] + PIN w0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 52.994 45.441 53.048 ; + END + END w0_wmask_in[455] + PIN w0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 52.994 45.729 53.048 ; + END + END w0_wmask_in[456] + PIN w0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 52.994 46.017 53.048 ; + END + END w0_wmask_in[457] + PIN w0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 52.994 46.305 53.048 ; + END + END w0_wmask_in[458] + PIN w0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 52.994 46.593 53.048 ; + END + END w0_wmask_in[459] + PIN w0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 52.994 46.881 53.048 ; + END + END w0_wmask_in[460] + PIN w0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 52.994 47.169 53.048 ; + END + END w0_wmask_in[461] + PIN w0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 52.994 47.457 53.048 ; + END + END w0_wmask_in[462] + PIN w0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 52.994 47.745 53.048 ; + END + END w0_wmask_in[463] + PIN w0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 52.994 48.033 53.048 ; + END + END w0_wmask_in[464] + PIN w0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 52.994 48.321 53.048 ; + END + END w0_wmask_in[465] + PIN w0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 52.994 48.609 53.048 ; + END + END w0_wmask_in[466] + PIN w0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 52.994 48.897 53.048 ; + END + END w0_wmask_in[467] + PIN w0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 52.994 49.185 53.048 ; + END + END w0_wmask_in[468] + PIN w0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 52.994 49.473 53.048 ; + END + END w0_wmask_in[469] + PIN w0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 52.994 49.761 53.048 ; + END + END w0_wmask_in[470] + PIN w0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 52.994 50.049 53.048 ; + END + END w0_wmask_in[471] + PIN w0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 52.994 50.337 53.048 ; + END + END w0_wmask_in[472] + PIN w0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 52.994 50.625 53.048 ; + END + END w0_wmask_in[473] + PIN w0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 52.994 50.913 53.048 ; + END + END w0_wmask_in[474] + PIN w0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 52.994 51.201 53.048 ; + END + END w0_wmask_in[475] + PIN w0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 52.994 51.489 53.048 ; + END + END w0_wmask_in[476] + PIN w0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 52.994 51.777 53.048 ; + END + END w0_wmask_in[477] + PIN w0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 52.994 52.065 53.048 ; + END + END w0_wmask_in[478] + PIN w0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 52.994 52.353 53.048 ; + END + END w0_wmask_in[479] + PIN w0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 52.994 52.641 53.048 ; + END + END w0_wmask_in[480] + PIN w0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 52.994 52.929 53.048 ; + END + END w0_wmask_in[481] + PIN w0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 52.994 53.217 53.048 ; + END + END w0_wmask_in[482] + PIN w0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 52.994 53.505 53.048 ; + END + END w0_wmask_in[483] + PIN w0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 52.994 53.793 53.048 ; + END + END w0_wmask_in[484] + PIN w0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 52.994 54.081 53.048 ; + END + END w0_wmask_in[485] + PIN w0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 52.994 54.369 53.048 ; + END + END w0_wmask_in[486] + PIN w0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 52.994 54.657 53.048 ; + END + END w0_wmask_in[487] + PIN w0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 52.994 54.945 53.048 ; + END + END w0_wmask_in[488] + PIN w0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 52.994 55.233 53.048 ; + END + END w0_wmask_in[489] + PIN w0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 52.994 55.521 53.048 ; + END + END w0_wmask_in[490] + PIN w0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 52.994 55.809 53.048 ; + END + END w0_wmask_in[491] + PIN w0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 52.994 56.097 53.048 ; + END + END w0_wmask_in[492] + PIN w0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 52.994 56.385 53.048 ; + END + END w0_wmask_in[493] + PIN w0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 52.994 56.673 53.048 ; + END + END w0_wmask_in[494] + PIN w0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 52.994 56.961 53.048 ; + END + END w0_wmask_in[495] + PIN w0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 52.994 57.249 53.048 ; + END + END w0_wmask_in[496] + PIN w0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 52.994 57.537 53.048 ; + END + END w0_wmask_in[497] + PIN w0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 52.994 57.825 53.048 ; + END + END w0_wmask_in[498] + PIN w0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 52.994 58.113 53.048 ; + END + END w0_wmask_in[499] + PIN w0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 52.994 58.401 53.048 ; + END + END w0_wmask_in[500] + PIN w0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 52.994 58.689 53.048 ; + END + END w0_wmask_in[501] + PIN w0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 52.994 58.977 53.048 ; + END + END w0_wmask_in[502] + PIN w0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 52.994 59.265 53.048 ; + END + END w0_wmask_in[503] + PIN w0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 52.994 59.553 53.048 ; + END + END w0_wmask_in[504] + PIN w0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 52.994 59.841 53.048 ; + END + END w0_wmask_in[505] + PIN w0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 52.994 60.129 53.048 ; + END + END w0_wmask_in[506] + PIN w0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 52.994 60.417 53.048 ; + END + END w0_wmask_in[507] + PIN w0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 52.994 60.705 53.048 ; + END + END w0_wmask_in[508] + PIN w0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 52.994 60.993 53.048 ; + END + END w0_wmask_in[509] + PIN w0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 52.994 61.281 53.048 ; + END + END w0_wmask_in[510] + PIN w0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 52.994 61.569 53.048 ; + END + END w0_wmask_in[511] + PIN w0_wmask_in[512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 52.994 61.857 53.048 ; + END + END w0_wmask_in[512] + PIN w0_wmask_in[513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 52.994 62.145 53.048 ; + END + END w0_wmask_in[513] + PIN w0_wmask_in[514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 52.994 62.433 53.048 ; + END + END w0_wmask_in[514] + PIN w0_wmask_in[515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 52.994 62.721 53.048 ; + END + END w0_wmask_in[515] + PIN w0_wmask_in[516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 52.994 63.009 53.048 ; + END + END w0_wmask_in[516] + PIN w0_wmask_in[517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 52.994 63.297 53.048 ; + END + END w0_wmask_in[517] + PIN w0_wmask_in[518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 52.994 63.585 53.048 ; + END + END w0_wmask_in[518] + PIN w0_wmask_in[519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 52.994 63.873 53.048 ; + END + END w0_wmask_in[519] + PIN w0_wmask_in[520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 52.994 64.161 53.048 ; + END + END w0_wmask_in[520] + PIN w0_wmask_in[521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 52.994 64.449 53.048 ; + END + END w0_wmask_in[521] + PIN w0_wmask_in[522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 52.994 64.737 53.048 ; + END + END w0_wmask_in[522] + PIN w0_wmask_in[523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 52.994 65.025 53.048 ; + END + END w0_wmask_in[523] + PIN w0_wmask_in[524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 52.994 65.313 53.048 ; + END + END w0_wmask_in[524] + PIN w0_wmask_in[525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 52.994 65.601 53.048 ; + END + END w0_wmask_in[525] + PIN w0_wmask_in[526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 52.994 65.889 53.048 ; + END + END w0_wmask_in[526] + PIN w0_wmask_in[527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 52.994 66.177 53.048 ; + END + END w0_wmask_in[527] + PIN w0_wmask_in[528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 52.994 66.465 53.048 ; + END + END w0_wmask_in[528] + PIN w0_wmask_in[529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 52.994 66.753 53.048 ; + END + END w0_wmask_in[529] + PIN w0_wmask_in[530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 52.994 67.041 53.048 ; + END + END w0_wmask_in[530] + PIN w0_wmask_in[531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 52.994 67.329 53.048 ; + END + END w0_wmask_in[531] + PIN w0_wmask_in[532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 52.994 67.617 53.048 ; + END + END w0_wmask_in[532] + PIN w0_wmask_in[533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 52.994 67.905 53.048 ; + END + END w0_wmask_in[533] + PIN w0_wmask_in[534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 52.994 68.193 53.048 ; + END + END w0_wmask_in[534] + PIN w0_wmask_in[535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 52.994 68.481 53.048 ; + END + END w0_wmask_in[535] + PIN w0_wmask_in[536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 52.994 68.769 53.048 ; + END + END w0_wmask_in[536] + PIN w0_wmask_in[537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 52.994 69.057 53.048 ; + END + END w0_wmask_in[537] + PIN w0_wmask_in[538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 52.994 69.345 53.048 ; + END + END w0_wmask_in[538] + PIN w0_wmask_in[539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 52.994 69.633 53.048 ; + END + END w0_wmask_in[539] + PIN w0_wmask_in[540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 52.994 69.921 53.048 ; + END + END w0_wmask_in[540] + PIN w0_wmask_in[541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 52.994 70.209 53.048 ; + END + END w0_wmask_in[541] + PIN w0_wmask_in[542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 52.994 70.497 53.048 ; + END + END w0_wmask_in[542] + PIN w0_wmask_in[543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 52.994 70.785 53.048 ; + END + END w0_wmask_in[543] + PIN w0_wmask_in[544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 52.994 71.073 53.048 ; + END + END w0_wmask_in[544] + PIN w0_wmask_in[545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 52.994 71.361 53.048 ; + END + END w0_wmask_in[545] + PIN w0_wmask_in[546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 52.994 71.649 53.048 ; + END + END w0_wmask_in[546] + PIN w0_wmask_in[547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 52.994 71.937 53.048 ; + END + END w0_wmask_in[547] + PIN w0_wmask_in[548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 52.994 72.225 53.048 ; + END + END w0_wmask_in[548] + PIN w0_wmask_in[549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 52.994 72.513 53.048 ; + END + END w0_wmask_in[549] + PIN w0_wmask_in[550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 52.994 72.801 53.048 ; + END + END w0_wmask_in[550] + PIN w0_wmask_in[551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 52.994 73.089 53.048 ; + END + END w0_wmask_in[551] + PIN w0_wmask_in[552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 52.994 73.377 53.048 ; + END + END w0_wmask_in[552] + PIN w0_wmask_in[553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 52.994 73.665 53.048 ; + END + END w0_wmask_in[553] + PIN w0_wmask_in[554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 52.994 73.953 53.048 ; + END + END w0_wmask_in[554] + PIN w0_wmask_in[555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 52.994 74.241 53.048 ; + END + END w0_wmask_in[555] + PIN w0_wmask_in[556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 52.994 74.529 53.048 ; + END + END w0_wmask_in[556] + PIN w0_wmask_in[557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 52.994 74.817 53.048 ; + END + END w0_wmask_in[557] + PIN w0_wmask_in[558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 52.994 75.105 53.048 ; + END + END w0_wmask_in[558] + PIN w0_wmask_in[559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 52.994 75.393 53.048 ; + END + END w0_wmask_in[559] + PIN w0_wmask_in[560] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 52.994 75.681 53.048 ; + END + END w0_wmask_in[560] + PIN w0_wmask_in[561] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 52.994 75.969 53.048 ; + END + END w0_wmask_in[561] + PIN w0_wmask_in[562] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 52.994 76.257 53.048 ; + END + END w0_wmask_in[562] + PIN w0_wmask_in[563] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 52.994 76.545 53.048 ; + END + END w0_wmask_in[563] + PIN w0_wmask_in[564] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 52.994 76.833 53.048 ; + END + END w0_wmask_in[564] + PIN w0_wmask_in[565] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 52.994 77.121 53.048 ; + END + END w0_wmask_in[565] + PIN w0_wmask_in[566] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 52.994 77.409 53.048 ; + END + END w0_wmask_in[566] + PIN w0_wmask_in[567] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 52.994 77.697 53.048 ; + END + END w0_wmask_in[567] + PIN w0_wmask_in[568] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 52.994 77.985 53.048 ; + END + END w0_wmask_in[568] + PIN w0_wmask_in[569] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 52.994 78.273 53.048 ; + END + END w0_wmask_in[569] + PIN w0_wmask_in[570] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 52.994 78.561 53.048 ; + END + END w0_wmask_in[570] + PIN w0_wmask_in[571] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 52.994 78.849 53.048 ; + END + END w0_wmask_in[571] + PIN w0_wmask_in[572] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 52.994 79.137 53.048 ; + END + END w0_wmask_in[572] + PIN w0_wmask_in[573] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 52.994 79.425 53.048 ; + END + END w0_wmask_in[573] + PIN w0_wmask_in[574] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 52.994 79.713 53.048 ; + END + END w0_wmask_in[574] + PIN w0_wmask_in[575] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 52.994 80.001 53.048 ; + END + END w0_wmask_in[575] + PIN w0_wmask_in[576] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 52.994 80.289 53.048 ; + END + END w0_wmask_in[576] + PIN w0_wmask_in[577] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 52.994 80.577 53.048 ; + END + END w0_wmask_in[577] + PIN w0_wmask_in[578] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 52.994 80.865 53.048 ; + END + END w0_wmask_in[578] + PIN w0_wmask_in[579] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 52.994 81.153 53.048 ; + END + END w0_wmask_in[579] + PIN w0_wmask_in[580] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 52.994 81.441 53.048 ; + END + END w0_wmask_in[580] + PIN w0_wmask_in[581] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 52.994 81.729 53.048 ; + END + END w0_wmask_in[581] + PIN w0_wmask_in[582] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 52.994 82.017 53.048 ; + END + END w0_wmask_in[582] + PIN w0_wmask_in[583] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 52.994 82.305 53.048 ; + END + END w0_wmask_in[583] + PIN w0_wmask_in[584] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 52.994 82.593 53.048 ; + END + END w0_wmask_in[584] + PIN w0_wmask_in[585] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 52.994 82.881 53.048 ; + END + END w0_wmask_in[585] + PIN w0_wmask_in[586] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 52.994 83.169 53.048 ; + END + END w0_wmask_in[586] + PIN w0_wmask_in[587] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 52.994 83.457 53.048 ; + END + END w0_wmask_in[587] + PIN w0_wmask_in[588] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 52.994 83.745 53.048 ; + END + END w0_wmask_in[588] + PIN w0_wmask_in[589] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 52.994 84.033 53.048 ; + END + END w0_wmask_in[589] + PIN w0_wmask_in[590] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 52.994 84.321 53.048 ; + END + END w0_wmask_in[590] + PIN w0_wmask_in[591] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 52.994 84.609 53.048 ; + END + END w0_wmask_in[591] + PIN w0_wmask_in[592] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 52.994 84.897 53.048 ; + END + END w0_wmask_in[592] + PIN w0_wmask_in[593] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 52.994 85.185 53.048 ; + END + END w0_wmask_in[593] + PIN w0_wmask_in[594] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 52.994 85.473 53.048 ; + END + END w0_wmask_in[594] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.732 0.072 21.756 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.020 0.072 22.044 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.596 0.072 22.620 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.884 0.072 22.908 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.748 0.072 23.772 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.324 0.072 24.348 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.612 0.072 24.636 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.188 0.072 25.212 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.052 0.072 26.076 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.340 0.072 26.364 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.916 0.072 26.940 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.204 0.072 27.228 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.780 0.072 27.804 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.068 0.072 28.092 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.212 0.072 28.236 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.644 0.072 28.668 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.932 0.072 28.956 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.508 0.072 29.532 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.796 0.072 29.820 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.940 0.072 29.964 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.372 0.072 30.396 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.660 0.072 30.684 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.092 0.072 31.116 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.236 0.072 31.260 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.668 0.072 31.692 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.100 0.072 32.124 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.388 0.072 32.412 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.820 0.072 32.844 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.964 0.072 32.988 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.252 0.072 33.276 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.828 0.072 33.852 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.116 0.072 34.140 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.404 0.072 34.428 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.692 0.072 34.716 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.980 0.072 35.004 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.124 0.072 35.148 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.268 0.072 35.292 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.556 0.072 35.580 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.844 0.072 35.868 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.132 0.072 36.156 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.420 0.072 36.444 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.708 0.072 36.732 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.852 0.072 36.876 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.996 0.072 37.020 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.284 0.072 37.308 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.860 0.072 37.884 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.004 0.072 38.028 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.148 0.072 38.172 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.436 0.072 38.460 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.724 0.072 38.748 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.868 0.072 38.892 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.012 0.072 39.036 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.300 0.072 39.324 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.588 0.072 39.612 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.732 0.072 39.756 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.876 0.072 39.900 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.164 0.072 40.188 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.308 0.072 40.332 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.452 0.072 40.476 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.740 0.072 40.764 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.884 0.072 40.908 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.028 0.072 41.052 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.172 0.072 41.196 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.316 0.072 41.340 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.460 0.072 41.484 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.604 0.072 41.628 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.748 0.072 41.772 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.892 0.072 41.916 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.036 0.072 42.060 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.180 0.072 42.204 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.324 0.072 42.348 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.468 0.072 42.492 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.612 0.072 42.636 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.756 0.072 42.780 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.900 0.072 42.924 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.044 0.072 43.068 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.732 189.696 21.756 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 21.876 189.696 21.900 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.020 189.696 22.044 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.164 189.696 22.188 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.308 189.696 22.332 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.452 189.696 22.476 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.596 189.696 22.620 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.740 189.696 22.764 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 22.884 189.696 22.908 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.028 189.696 23.052 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.172 189.696 23.196 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.316 189.696 23.340 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.460 189.696 23.484 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.604 189.696 23.628 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.748 189.696 23.772 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 23.892 189.696 23.916 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.036 189.696 24.060 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.180 189.696 24.204 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.324 189.696 24.348 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.468 189.696 24.492 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.612 189.696 24.636 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.756 189.696 24.780 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 24.900 189.696 24.924 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.044 189.696 25.068 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.188 189.696 25.212 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.332 189.696 25.356 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.476 189.696 25.500 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.620 189.696 25.644 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.764 189.696 25.788 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 25.908 189.696 25.932 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.052 189.696 26.076 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.196 189.696 26.220 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.340 189.696 26.364 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.484 189.696 26.508 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.628 189.696 26.652 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.772 189.696 26.796 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 26.916 189.696 26.940 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.060 189.696 27.084 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.204 189.696 27.228 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.348 189.696 27.372 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.492 189.696 27.516 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.636 189.696 27.660 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.780 189.696 27.804 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 27.924 189.696 27.948 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.068 189.696 28.092 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.212 189.696 28.236 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.356 189.696 28.380 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.500 189.696 28.524 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.644 189.696 28.668 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.788 189.696 28.812 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 28.932 189.696 28.956 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.076 189.696 29.100 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.220 189.696 29.244 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.364 189.696 29.388 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.508 189.696 29.532 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.652 189.696 29.676 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.796 189.696 29.820 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 29.940 189.696 29.964 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.084 189.696 30.108 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.228 189.696 30.252 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.372 189.696 30.396 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.516 189.696 30.540 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.660 189.696 30.684 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.804 189.696 30.828 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 30.948 189.696 30.972 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.092 189.696 31.116 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.236 189.696 31.260 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.380 189.696 31.404 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.524 189.696 31.548 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.668 189.696 31.692 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.812 189.696 31.836 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 31.956 189.696 31.980 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.100 189.696 32.124 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.244 189.696 32.268 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.388 189.696 32.412 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.532 189.696 32.556 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.676 189.696 32.700 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.820 189.696 32.844 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 32.964 189.696 32.988 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.108 189.696 33.132 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.252 189.696 33.276 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.396 189.696 33.420 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.540 189.696 33.564 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.684 189.696 33.708 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.828 189.696 33.852 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 33.972 189.696 33.996 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.116 189.696 34.140 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.260 189.696 34.284 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.404 189.696 34.428 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.548 189.696 34.572 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.692 189.696 34.716 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.836 189.696 34.860 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 34.980 189.696 35.004 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.124 189.696 35.148 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.268 189.696 35.292 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.412 189.696 35.436 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.556 189.696 35.580 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.700 189.696 35.724 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.844 189.696 35.868 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 35.988 189.696 36.012 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.132 189.696 36.156 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.276 189.696 36.300 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.420 189.696 36.444 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.564 189.696 36.588 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.708 189.696 36.732 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.852 189.696 36.876 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 36.996 189.696 37.020 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 37.140 189.696 37.164 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 37.284 189.696 37.308 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 37.428 189.696 37.452 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 37.572 189.696 37.596 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 37.716 189.696 37.740 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 37.860 189.696 37.884 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.004 189.696 38.028 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.148 189.696 38.172 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.292 189.696 38.316 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.436 189.696 38.460 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.580 189.696 38.604 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.724 189.696 38.748 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 38.868 189.696 38.892 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.012 189.696 39.036 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.156 189.696 39.180 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.300 189.696 39.324 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.444 189.696 39.468 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.588 189.696 39.612 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.732 189.696 39.756 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 39.876 189.696 39.900 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.020 189.696 40.044 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.164 189.696 40.188 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.308 189.696 40.332 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.452 189.696 40.476 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.596 189.696 40.620 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.740 189.696 40.764 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 40.884 189.696 40.908 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.028 189.696 41.052 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.172 189.696 41.196 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.316 189.696 41.340 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.460 189.696 41.484 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.604 189.696 41.628 ; + END + END w0_wd_in[287] + PIN w0_wd_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.748 189.696 41.772 ; + END + END w0_wd_in[288] + PIN w0_wd_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 41.892 189.696 41.916 ; + END + END w0_wd_in[289] + PIN w0_wd_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.036 189.696 42.060 ; + END + END w0_wd_in[290] + PIN w0_wd_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.180 189.696 42.204 ; + END + END w0_wd_in[291] + PIN w0_wd_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.324 189.696 42.348 ; + END + END w0_wd_in[292] + PIN w0_wd_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.468 189.696 42.492 ; + END + END w0_wd_in[293] + PIN w0_wd_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.612 189.696 42.636 ; + END + END w0_wd_in[294] + PIN w0_wd_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.756 189.696 42.780 ; + END + END w0_wd_in[295] + PIN w0_wd_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 42.900 189.696 42.924 ; + END + END w0_wd_in[296] + PIN w0_wd_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 189.624 43.044 189.696 43.068 ; + END + END w0_wd_in[297] + PIN w0_wd_in[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[298] + PIN w0_wd_in[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[299] + PIN w0_wd_in[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[300] + PIN w0_wd_in[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[301] + PIN w0_wd_in[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[302] + PIN w0_wd_in[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[303] + PIN w0_wd_in[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[304] + PIN w0_wd_in[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[305] + PIN w0_wd_in[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[306] + PIN w0_wd_in[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[307] + PIN w0_wd_in[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[308] + PIN w0_wd_in[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[309] + PIN w0_wd_in[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[310] + PIN w0_wd_in[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[311] + PIN w0_wd_in[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[312] + PIN w0_wd_in[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[313] + PIN w0_wd_in[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[314] + PIN w0_wd_in[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[315] + PIN w0_wd_in[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[316] + PIN w0_wd_in[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[317] + PIN w0_wd_in[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[318] + PIN w0_wd_in[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[319] + PIN w0_wd_in[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[320] + PIN w0_wd_in[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[321] + PIN w0_wd_in[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[322] + PIN w0_wd_in[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[323] + PIN w0_wd_in[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[324] + PIN w0_wd_in[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[325] + PIN w0_wd_in[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[326] + PIN w0_wd_in[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[327] + PIN w0_wd_in[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[328] + PIN w0_wd_in[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[329] + PIN w0_wd_in[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[330] + PIN w0_wd_in[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[331] + PIN w0_wd_in[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[332] + PIN w0_wd_in[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[333] + PIN w0_wd_in[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[334] + PIN w0_wd_in[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[335] + PIN w0_wd_in[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[336] + PIN w0_wd_in[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[337] + PIN w0_wd_in[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[338] + PIN w0_wd_in[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[339] + PIN w0_wd_in[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[340] + PIN w0_wd_in[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[341] + PIN w0_wd_in[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[342] + PIN w0_wd_in[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[343] + PIN w0_wd_in[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[344] + PIN w0_wd_in[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[345] + PIN w0_wd_in[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[346] + PIN w0_wd_in[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[347] + PIN w0_wd_in[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[348] + PIN w0_wd_in[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[349] + PIN w0_wd_in[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[350] + PIN w0_wd_in[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[351] + PIN w0_wd_in[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[352] + PIN w0_wd_in[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[353] + PIN w0_wd_in[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[354] + PIN w0_wd_in[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[355] + PIN w0_wd_in[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[356] + PIN w0_wd_in[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[357] + PIN w0_wd_in[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[358] + PIN w0_wd_in[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[359] + PIN w0_wd_in[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[360] + PIN w0_wd_in[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[361] + PIN w0_wd_in[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[362] + PIN w0_wd_in[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[363] + PIN w0_wd_in[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[364] + PIN w0_wd_in[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[365] + PIN w0_wd_in[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[366] + PIN w0_wd_in[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[367] + PIN w0_wd_in[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[368] + PIN w0_wd_in[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[369] + PIN w0_wd_in[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[370] + PIN w0_wd_in[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[371] + PIN w0_wd_in[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[372] + PIN w0_wd_in[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[373] + PIN w0_wd_in[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[374] + PIN w0_wd_in[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[375] + PIN w0_wd_in[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[376] + PIN w0_wd_in[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[377] + PIN w0_wd_in[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[378] + PIN w0_wd_in[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[379] + PIN w0_wd_in[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[380] + PIN w0_wd_in[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[381] + PIN w0_wd_in[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[382] + PIN w0_wd_in[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[383] + PIN w0_wd_in[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[384] + PIN w0_wd_in[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[385] + PIN w0_wd_in[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[386] + PIN w0_wd_in[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[387] + PIN w0_wd_in[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[388] + PIN w0_wd_in[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[389] + PIN w0_wd_in[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[390] + PIN w0_wd_in[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[391] + PIN w0_wd_in[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[392] + PIN w0_wd_in[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[393] + PIN w0_wd_in[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[394] + PIN w0_wd_in[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[395] + PIN w0_wd_in[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[396] + PIN w0_wd_in[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[397] + PIN w0_wd_in[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[398] + PIN w0_wd_in[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[399] + PIN w0_wd_in[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[400] + PIN w0_wd_in[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[401] + PIN w0_wd_in[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[402] + PIN w0_wd_in[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[403] + PIN w0_wd_in[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[404] + PIN w0_wd_in[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[405] + PIN w0_wd_in[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[406] + PIN w0_wd_in[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[407] + PIN w0_wd_in[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[408] + PIN w0_wd_in[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[409] + PIN w0_wd_in[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[410] + PIN w0_wd_in[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[411] + PIN w0_wd_in[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[412] + PIN w0_wd_in[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[413] + PIN w0_wd_in[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[414] + PIN w0_wd_in[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[415] + PIN w0_wd_in[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[416] + PIN w0_wd_in[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[417] + PIN w0_wd_in[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[418] + PIN w0_wd_in[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[419] + PIN w0_wd_in[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[420] + PIN w0_wd_in[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[421] + PIN w0_wd_in[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[422] + PIN w0_wd_in[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[423] + PIN w0_wd_in[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[424] + PIN w0_wd_in[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[425] + PIN w0_wd_in[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[426] + PIN w0_wd_in[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[427] + PIN w0_wd_in[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[428] + PIN w0_wd_in[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[429] + PIN w0_wd_in[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[430] + PIN w0_wd_in[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[431] + PIN w0_wd_in[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[432] + PIN w0_wd_in[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[433] + PIN w0_wd_in[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[434] + PIN w0_wd_in[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[435] + PIN w0_wd_in[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[436] + PIN w0_wd_in[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[437] + PIN w0_wd_in[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[438] + PIN w0_wd_in[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[439] + PIN w0_wd_in[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[440] + PIN w0_wd_in[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[441] + PIN w0_wd_in[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END w0_wd_in[442] + PIN w0_wd_in[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END w0_wd_in[443] + PIN w0_wd_in[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END w0_wd_in[444] + PIN w0_wd_in[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END w0_wd_in[445] + PIN w0_wd_in[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END w0_wd_in[446] + PIN w0_wd_in[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END w0_wd_in[447] + PIN w0_wd_in[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END w0_wd_in[448] + PIN w0_wd_in[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END w0_wd_in[449] + PIN w0_wd_in[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END w0_wd_in[450] + PIN w0_wd_in[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END w0_wd_in[451] + PIN w0_wd_in[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END w0_wd_in[452] + PIN w0_wd_in[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END w0_wd_in[453] + PIN w0_wd_in[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END w0_wd_in[454] + PIN w0_wd_in[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END w0_wd_in[455] + PIN w0_wd_in[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END w0_wd_in[456] + PIN w0_wd_in[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END w0_wd_in[457] + PIN w0_wd_in[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END w0_wd_in[458] + PIN w0_wd_in[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END w0_wd_in[459] + PIN w0_wd_in[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END w0_wd_in[460] + PIN w0_wd_in[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END w0_wd_in[461] + PIN w0_wd_in[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END w0_wd_in[462] + PIN w0_wd_in[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END w0_wd_in[463] + PIN w0_wd_in[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END w0_wd_in[464] + PIN w0_wd_in[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END w0_wd_in[465] + PIN w0_wd_in[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END w0_wd_in[466] + PIN w0_wd_in[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END w0_wd_in[467] + PIN w0_wd_in[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END w0_wd_in[468] + PIN w0_wd_in[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END w0_wd_in[469] + PIN w0_wd_in[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END w0_wd_in[470] + PIN w0_wd_in[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END w0_wd_in[471] + PIN w0_wd_in[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END w0_wd_in[472] + PIN w0_wd_in[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END w0_wd_in[473] + PIN w0_wd_in[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END w0_wd_in[474] + PIN w0_wd_in[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END w0_wd_in[475] + PIN w0_wd_in[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END w0_wd_in[476] + PIN w0_wd_in[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END w0_wd_in[477] + PIN w0_wd_in[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END w0_wd_in[478] + PIN w0_wd_in[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END w0_wd_in[479] + PIN w0_wd_in[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END w0_wd_in[480] + PIN w0_wd_in[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END w0_wd_in[481] + PIN w0_wd_in[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END w0_wd_in[482] + PIN w0_wd_in[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END w0_wd_in[483] + PIN w0_wd_in[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END w0_wd_in[484] + PIN w0_wd_in[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END w0_wd_in[485] + PIN w0_wd_in[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END w0_wd_in[486] + PIN w0_wd_in[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END w0_wd_in[487] + PIN w0_wd_in[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END w0_wd_in[488] + PIN w0_wd_in[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END w0_wd_in[489] + PIN w0_wd_in[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END w0_wd_in[490] + PIN w0_wd_in[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END w0_wd_in[491] + PIN w0_wd_in[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END w0_wd_in[492] + PIN w0_wd_in[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END w0_wd_in[493] + PIN w0_wd_in[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END w0_wd_in[494] + PIN w0_wd_in[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END w0_wd_in[495] + PIN w0_wd_in[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END w0_wd_in[496] + PIN w0_wd_in[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END w0_wd_in[497] + PIN w0_wd_in[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END w0_wd_in[498] + PIN w0_wd_in[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END w0_wd_in[499] + PIN w0_wd_in[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END w0_wd_in[500] + PIN w0_wd_in[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END w0_wd_in[501] + PIN w0_wd_in[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END w0_wd_in[502] + PIN w0_wd_in[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END w0_wd_in[503] + PIN w0_wd_in[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END w0_wd_in[504] + PIN w0_wd_in[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END w0_wd_in[505] + PIN w0_wd_in[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END w0_wd_in[506] + PIN w0_wd_in[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END w0_wd_in[507] + PIN w0_wd_in[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END w0_wd_in[508] + PIN w0_wd_in[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END w0_wd_in[509] + PIN w0_wd_in[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END w0_wd_in[510] + PIN w0_wd_in[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END w0_wd_in[511] + PIN w0_wd_in[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END w0_wd_in[512] + PIN w0_wd_in[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END w0_wd_in[513] + PIN w0_wd_in[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END w0_wd_in[514] + PIN w0_wd_in[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END w0_wd_in[515] + PIN w0_wd_in[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END w0_wd_in[516] + PIN w0_wd_in[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END w0_wd_in[517] + PIN w0_wd_in[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END w0_wd_in[518] + PIN w0_wd_in[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END w0_wd_in[519] + PIN w0_wd_in[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END w0_wd_in[520] + PIN w0_wd_in[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END w0_wd_in[521] + PIN w0_wd_in[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END w0_wd_in[522] + PIN w0_wd_in[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END w0_wd_in[523] + PIN w0_wd_in[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END w0_wd_in[524] + PIN w0_wd_in[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END w0_wd_in[525] + PIN w0_wd_in[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END w0_wd_in[526] + PIN w0_wd_in[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END w0_wd_in[527] + PIN w0_wd_in[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END w0_wd_in[528] + PIN w0_wd_in[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END w0_wd_in[529] + PIN w0_wd_in[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END w0_wd_in[530] + PIN w0_wd_in[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END w0_wd_in[531] + PIN w0_wd_in[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END w0_wd_in[532] + PIN w0_wd_in[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END w0_wd_in[533] + PIN w0_wd_in[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END w0_wd_in[534] + PIN w0_wd_in[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END w0_wd_in[535] + PIN w0_wd_in[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END w0_wd_in[536] + PIN w0_wd_in[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END w0_wd_in[537] + PIN w0_wd_in[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END w0_wd_in[538] + PIN w0_wd_in[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END w0_wd_in[539] + PIN w0_wd_in[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END w0_wd_in[540] + PIN w0_wd_in[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END w0_wd_in[541] + PIN w0_wd_in[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END w0_wd_in[542] + PIN w0_wd_in[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END w0_wd_in[543] + PIN w0_wd_in[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END w0_wd_in[544] + PIN w0_wd_in[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END w0_wd_in[545] + PIN w0_wd_in[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END w0_wd_in[546] + PIN w0_wd_in[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END w0_wd_in[547] + PIN w0_wd_in[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END w0_wd_in[548] + PIN w0_wd_in[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END w0_wd_in[549] + PIN w0_wd_in[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END w0_wd_in[550] + PIN w0_wd_in[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END w0_wd_in[551] + PIN w0_wd_in[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END w0_wd_in[552] + PIN w0_wd_in[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END w0_wd_in[553] + PIN w0_wd_in[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END w0_wd_in[554] + PIN w0_wd_in[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END w0_wd_in[555] + PIN w0_wd_in[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END w0_wd_in[556] + PIN w0_wd_in[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END w0_wd_in[557] + PIN w0_wd_in[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END w0_wd_in[558] + PIN w0_wd_in[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END w0_wd_in[559] + PIN w0_wd_in[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END w0_wd_in[560] + PIN w0_wd_in[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END w0_wd_in[561] + PIN w0_wd_in[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END w0_wd_in[562] + PIN w0_wd_in[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END w0_wd_in[563] + PIN w0_wd_in[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END w0_wd_in[564] + PIN w0_wd_in[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END w0_wd_in[565] + PIN w0_wd_in[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END w0_wd_in[566] + PIN w0_wd_in[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END w0_wd_in[567] + PIN w0_wd_in[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END w0_wd_in[568] + PIN w0_wd_in[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END w0_wd_in[569] + PIN w0_wd_in[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END w0_wd_in[570] + PIN w0_wd_in[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END w0_wd_in[571] + PIN w0_wd_in[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END w0_wd_in[572] + PIN w0_wd_in[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END w0_wd_in[573] + PIN w0_wd_in[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END w0_wd_in[574] + PIN w0_wd_in[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END w0_wd_in[575] + PIN w0_wd_in[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END w0_wd_in[576] + PIN w0_wd_in[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END w0_wd_in[577] + PIN w0_wd_in[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END w0_wd_in[578] + PIN w0_wd_in[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END w0_wd_in[579] + PIN w0_wd_in[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END w0_wd_in[580] + PIN w0_wd_in[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END w0_wd_in[581] + PIN w0_wd_in[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END w0_wd_in[582] + PIN w0_wd_in[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END w0_wd_in[583] + PIN w0_wd_in[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END w0_wd_in[584] + PIN w0_wd_in[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END w0_wd_in[585] + PIN w0_wd_in[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 0.000 83.169 0.054 ; + END + END w0_wd_in[586] + PIN w0_wd_in[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 0.000 83.457 0.054 ; + END + END w0_wd_in[587] + PIN w0_wd_in[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END w0_wd_in[588] + PIN w0_wd_in[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 0.000 84.033 0.054 ; + END + END w0_wd_in[589] + PIN w0_wd_in[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 0.000 84.321 0.054 ; + END + END w0_wd_in[590] + PIN w0_wd_in[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 0.000 84.609 0.054 ; + END + END w0_wd_in[591] + PIN w0_wd_in[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 0.000 84.897 0.054 ; + END + END w0_wd_in[592] + PIN w0_wd_in[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END w0_wd_in[593] + PIN w0_wd_in[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 0.000 85.473 0.054 ; + END + END w0_wd_in[594] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 0.000 85.761 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 0.000 86.049 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 0.000 86.337 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 0.000 86.913 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 0.000 87.201 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 0.000 87.489 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 0.000 87.777 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 0.000 88.353 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 0.000 88.641 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 0.000 88.929 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 0.000 89.217 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 0.000 89.793 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 0.000 90.081 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 0.000 90.369 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 0.000 90.657 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 0.000 91.233 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 0.000 91.521 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 0.000 91.809 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 0.000 92.097 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 0.000 92.385 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 0.000 92.673 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 0.000 92.961 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 0.000 93.249 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 0.000 93.537 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 0.000 93.825 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 0.000 94.113 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 0.000 94.401 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 0.000 94.689 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 0.000 94.977 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 0.000 95.265 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 0.000 95.553 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 0.000 95.841 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 0.000 96.129 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 0.000 96.417 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 0.000 96.705 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 0.000 96.993 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 0.000 97.281 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 0.000 97.569 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 0.000 97.857 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 0.000 98.145 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 0.000 98.433 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 0.000 98.721 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 0.000 99.009 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 0.000 99.297 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 0.000 99.585 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 0.000 99.873 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 0.000 100.161 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 0.000 100.449 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 0.000 100.737 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 0.000 101.025 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 0.000 101.313 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 0.000 101.601 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 0.000 101.889 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 0.000 102.177 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 0.000 102.465 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 0.000 102.753 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 0.000 103.041 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 0.000 103.329 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 0.000 103.617 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 0.000 103.905 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 0.000 104.193 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 0.000 104.481 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 0.000 104.769 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 0.000 105.057 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 0.000 105.345 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 0.000 105.633 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 0.000 105.921 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 0.000 106.209 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 0.000 106.497 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 0.000 106.785 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 0.000 107.073 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 0.000 107.361 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 0.000 107.649 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 0.000 107.937 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 0.000 108.225 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 0.000 108.513 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 0.000 108.801 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 0.000 109.089 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 0.000 109.377 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 0.000 109.665 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 0.000 109.953 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 0.000 110.241 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 0.000 110.529 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 0.000 110.817 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 0.000 111.105 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 0.000 111.393 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 0.000 111.681 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 0.000 111.969 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 0.000 112.257 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 0.000 112.545 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 0.000 112.833 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 0.000 113.121 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 0.000 113.409 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 0.000 113.697 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 0.000 113.985 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 0.000 114.273 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 0.000 114.561 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 0.000 114.849 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 0.000 115.137 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 0.000 115.425 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 0.000 115.713 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 0.000 116.001 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 0.000 116.289 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 0.000 116.577 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 0.000 116.865 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 0.000 117.153 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 0.000 117.441 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 0.000 117.729 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 0.000 118.017 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 0.000 118.305 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 0.000 118.593 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 0.000 118.881 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 0.000 119.169 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 0.000 119.457 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 0.000 119.745 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 0.000 120.033 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 0.000 120.321 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 0.000 120.609 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 0.000 120.897 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 0.000 121.185 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 0.000 121.473 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 0.000 121.761 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 0.000 122.049 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 0.000 122.337 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 0.000 122.625 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 0.000 122.913 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 0.000 123.201 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 0.000 123.489 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 0.000 123.777 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 0.000 124.065 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 0.000 124.353 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 0.000 124.641 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 0.000 124.929 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 0.000 125.217 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 0.000 125.505 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 0.000 125.793 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 0.000 126.081 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 0.000 126.369 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 0.000 126.657 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 0.000 126.945 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 0.000 127.233 0.054 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 0.000 127.521 0.054 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 0.000 127.809 0.054 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 0.000 128.097 0.054 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 0.000 128.385 0.054 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 0.000 128.673 0.054 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 0.000 128.961 0.054 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 0.000 129.249 0.054 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 0.000 129.537 0.054 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 0.000 129.825 0.054 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 0.000 130.113 0.054 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 0.000 130.401 0.054 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 0.000 130.689 0.054 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 0.000 130.977 0.054 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 0.000 131.265 0.054 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 0.000 131.553 0.054 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 0.000 131.841 0.054 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 0.000 132.129 0.054 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 0.000 132.417 0.054 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 0.000 132.705 0.054 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 0.000 132.993 0.054 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 0.000 133.281 0.054 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 0.000 133.569 0.054 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 0.000 133.857 0.054 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 0.000 134.145 0.054 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 0.000 134.433 0.054 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 0.000 134.721 0.054 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 0.000 135.009 0.054 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 0.000 135.297 0.054 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 0.000 135.585 0.054 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 0.000 135.873 0.054 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 0.000 136.161 0.054 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 0.000 136.449 0.054 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 0.000 136.737 0.054 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 0.000 137.025 0.054 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 0.000 137.313 0.054 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 0.000 137.601 0.054 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 0.000 137.889 0.054 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 0.000 138.177 0.054 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 0.000 138.465 0.054 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 0.000 138.753 0.054 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 0.000 139.041 0.054 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 0.000 139.329 0.054 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 0.000 139.617 0.054 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 0.000 139.905 0.054 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 0.000 140.193 0.054 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 0.000 140.481 0.054 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 0.000 140.769 0.054 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 0.000 141.057 0.054 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 0.000 141.345 0.054 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 0.000 141.633 0.054 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 0.000 141.921 0.054 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 0.000 142.209 0.054 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 0.000 142.497 0.054 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 0.000 142.785 0.054 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 0.000 143.073 0.054 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 0.000 143.361 0.054 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 0.000 143.649 0.054 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 0.000 143.937 0.054 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 0.000 144.225 0.054 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 0.000 144.513 0.054 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 0.000 144.801 0.054 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 0.000 145.089 0.054 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 0.000 145.377 0.054 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 0.000 145.665 0.054 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 0.000 145.953 0.054 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 0.000 146.241 0.054 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 0.000 146.529 0.054 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 0.000 146.817 0.054 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 0.000 147.105 0.054 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 0.000 147.393 0.054 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 0.000 147.681 0.054 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 0.000 147.969 0.054 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 0.000 148.257 0.054 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 0.000 148.545 0.054 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 0.000 148.833 0.054 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 0.000 149.121 0.054 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 0.000 149.409 0.054 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 0.000 149.697 0.054 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 0.000 149.985 0.054 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 0.000 150.273 0.054 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 0.000 150.561 0.054 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 0.000 150.849 0.054 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 0.000 151.137 0.054 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 0.000 151.425 0.054 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 0.000 151.713 0.054 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 0.000 152.001 0.054 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 0.000 152.289 0.054 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 0.000 152.577 0.054 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 0.000 152.865 0.054 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 0.000 153.153 0.054 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 0.000 153.441 0.054 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 0.000 153.729 0.054 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 0.000 154.017 0.054 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 0.000 154.305 0.054 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 0.000 154.593 0.054 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 0.000 154.881 0.054 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 0.000 155.169 0.054 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 0.000 155.457 0.054 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 0.000 155.745 0.054 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 0.000 156.033 0.054 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 0.000 156.321 0.054 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 0.000 156.609 0.054 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 0.000 156.897 0.054 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 0.000 157.185 0.054 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 0.000 157.473 0.054 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 0.000 157.761 0.054 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 0.000 158.049 0.054 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 0.000 158.337 0.054 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 0.000 158.625 0.054 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 0.000 158.913 0.054 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 0.000 159.201 0.054 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 0.000 159.489 0.054 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 0.000 159.777 0.054 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 0.000 160.065 0.054 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 0.000 160.353 0.054 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 0.000 160.641 0.054 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 0.000 160.929 0.054 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 0.000 161.217 0.054 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 0.000 161.505 0.054 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 0.000 161.793 0.054 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 0.000 162.081 0.054 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 0.000 162.369 0.054 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 0.000 162.657 0.054 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 0.000 162.945 0.054 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.215 0.000 163.233 0.054 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.503 0.000 163.521 0.054 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.791 0.000 163.809 0.054 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.079 0.000 164.097 0.054 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 0.000 164.385 0.054 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.655 0.000 164.673 0.054 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.943 0.000 164.961 0.054 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.231 0.000 165.249 0.054 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.519 0.000 165.537 0.054 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 0.000 165.825 0.054 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.095 0.000 166.113 0.054 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.383 0.000 166.401 0.054 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.671 0.000 166.689 0.054 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.959 0.000 166.977 0.054 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 0.000 167.265 0.054 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.535 0.000 167.553 0.054 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.823 0.000 167.841 0.054 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.111 0.000 168.129 0.054 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.399 0.000 168.417 0.054 ; + END + END r0_rd_out[287] + PIN r0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 0.000 168.705 0.054 ; + END + END r0_rd_out[288] + PIN r0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.975 0.000 168.993 0.054 ; + END + END r0_rd_out[289] + PIN r0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.263 0.000 169.281 0.054 ; + END + END r0_rd_out[290] + PIN r0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.551 0.000 169.569 0.054 ; + END + END r0_rd_out[291] + PIN r0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.839 0.000 169.857 0.054 ; + END + END r0_rd_out[292] + PIN r0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 0.000 170.145 0.054 ; + END + END r0_rd_out[293] + PIN r0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.415 0.000 170.433 0.054 ; + END + END r0_rd_out[294] + PIN r0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.703 0.000 170.721 0.054 ; + END + END r0_rd_out[295] + PIN r0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.991 0.000 171.009 0.054 ; + END + END r0_rd_out[296] + PIN r0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.279 0.000 171.297 0.054 ; + END + END r0_rd_out[297] + PIN r0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 52.994 85.761 53.048 ; + END + END r0_rd_out[298] + PIN r0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 52.994 86.049 53.048 ; + END + END r0_rd_out[299] + PIN r0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 52.994 86.337 53.048 ; + END + END r0_rd_out[300] + PIN r0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 52.994 86.625 53.048 ; + END + END r0_rd_out[301] + PIN r0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 52.994 86.913 53.048 ; + END + END r0_rd_out[302] + PIN r0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 52.994 87.201 53.048 ; + END + END r0_rd_out[303] + PIN r0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 52.994 87.489 53.048 ; + END + END r0_rd_out[304] + PIN r0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 52.994 87.777 53.048 ; + END + END r0_rd_out[305] + PIN r0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 52.994 88.065 53.048 ; + END + END r0_rd_out[306] + PIN r0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 52.994 88.353 53.048 ; + END + END r0_rd_out[307] + PIN r0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 52.994 88.641 53.048 ; + END + END r0_rd_out[308] + PIN r0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 52.994 88.929 53.048 ; + END + END r0_rd_out[309] + PIN r0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 52.994 89.217 53.048 ; + END + END r0_rd_out[310] + PIN r0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 52.994 89.505 53.048 ; + END + END r0_rd_out[311] + PIN r0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 52.994 89.793 53.048 ; + END + END r0_rd_out[312] + PIN r0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 52.994 90.081 53.048 ; + END + END r0_rd_out[313] + PIN r0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 52.994 90.369 53.048 ; + END + END r0_rd_out[314] + PIN r0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 52.994 90.657 53.048 ; + END + END r0_rd_out[315] + PIN r0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 52.994 90.945 53.048 ; + END + END r0_rd_out[316] + PIN r0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 52.994 91.233 53.048 ; + END + END r0_rd_out[317] + PIN r0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 52.994 91.521 53.048 ; + END + END r0_rd_out[318] + PIN r0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 52.994 91.809 53.048 ; + END + END r0_rd_out[319] + PIN r0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 52.994 92.097 53.048 ; + END + END r0_rd_out[320] + PIN r0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 52.994 92.385 53.048 ; + END + END r0_rd_out[321] + PIN r0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 52.994 92.673 53.048 ; + END + END r0_rd_out[322] + PIN r0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 52.994 92.961 53.048 ; + END + END r0_rd_out[323] + PIN r0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 52.994 93.249 53.048 ; + END + END r0_rd_out[324] + PIN r0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 52.994 93.537 53.048 ; + END + END r0_rd_out[325] + PIN r0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 52.994 93.825 53.048 ; + END + END r0_rd_out[326] + PIN r0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 52.994 94.113 53.048 ; + END + END r0_rd_out[327] + PIN r0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 52.994 94.401 53.048 ; + END + END r0_rd_out[328] + PIN r0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 52.994 94.689 53.048 ; + END + END r0_rd_out[329] + PIN r0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 52.994 94.977 53.048 ; + END + END r0_rd_out[330] + PIN r0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 52.994 95.265 53.048 ; + END + END r0_rd_out[331] + PIN r0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 52.994 95.553 53.048 ; + END + END r0_rd_out[332] + PIN r0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 52.994 95.841 53.048 ; + END + END r0_rd_out[333] + PIN r0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 52.994 96.129 53.048 ; + END + END r0_rd_out[334] + PIN r0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 52.994 96.417 53.048 ; + END + END r0_rd_out[335] + PIN r0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 52.994 96.705 53.048 ; + END + END r0_rd_out[336] + PIN r0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 52.994 96.993 53.048 ; + END + END r0_rd_out[337] + PIN r0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 52.994 97.281 53.048 ; + END + END r0_rd_out[338] + PIN r0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 52.994 97.569 53.048 ; + END + END r0_rd_out[339] + PIN r0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 52.994 97.857 53.048 ; + END + END r0_rd_out[340] + PIN r0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 52.994 98.145 53.048 ; + END + END r0_rd_out[341] + PIN r0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 52.994 98.433 53.048 ; + END + END r0_rd_out[342] + PIN r0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 52.994 98.721 53.048 ; + END + END r0_rd_out[343] + PIN r0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 52.994 99.009 53.048 ; + END + END r0_rd_out[344] + PIN r0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 52.994 99.297 53.048 ; + END + END r0_rd_out[345] + PIN r0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 52.994 99.585 53.048 ; + END + END r0_rd_out[346] + PIN r0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 52.994 99.873 53.048 ; + END + END r0_rd_out[347] + PIN r0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 52.994 100.161 53.048 ; + END + END r0_rd_out[348] + PIN r0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 52.994 100.449 53.048 ; + END + END r0_rd_out[349] + PIN r0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 52.994 100.737 53.048 ; + END + END r0_rd_out[350] + PIN r0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 52.994 101.025 53.048 ; + END + END r0_rd_out[351] + PIN r0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 52.994 101.313 53.048 ; + END + END r0_rd_out[352] + PIN r0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 52.994 101.601 53.048 ; + END + END r0_rd_out[353] + PIN r0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 52.994 101.889 53.048 ; + END + END r0_rd_out[354] + PIN r0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 52.994 102.177 53.048 ; + END + END r0_rd_out[355] + PIN r0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 52.994 102.465 53.048 ; + END + END r0_rd_out[356] + PIN r0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 52.994 102.753 53.048 ; + END + END r0_rd_out[357] + PIN r0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 52.994 103.041 53.048 ; + END + END r0_rd_out[358] + PIN r0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 52.994 103.329 53.048 ; + END + END r0_rd_out[359] + PIN r0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 52.994 103.617 53.048 ; + END + END r0_rd_out[360] + PIN r0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 52.994 103.905 53.048 ; + END + END r0_rd_out[361] + PIN r0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 52.994 104.193 53.048 ; + END + END r0_rd_out[362] + PIN r0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 52.994 104.481 53.048 ; + END + END r0_rd_out[363] + PIN r0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 52.994 104.769 53.048 ; + END + END r0_rd_out[364] + PIN r0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 52.994 105.057 53.048 ; + END + END r0_rd_out[365] + PIN r0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 52.994 105.345 53.048 ; + END + END r0_rd_out[366] + PIN r0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 52.994 105.633 53.048 ; + END + END r0_rd_out[367] + PIN r0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 52.994 105.921 53.048 ; + END + END r0_rd_out[368] + PIN r0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 52.994 106.209 53.048 ; + END + END r0_rd_out[369] + PIN r0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 52.994 106.497 53.048 ; + END + END r0_rd_out[370] + PIN r0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 52.994 106.785 53.048 ; + END + END r0_rd_out[371] + PIN r0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 52.994 107.073 53.048 ; + END + END r0_rd_out[372] + PIN r0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 52.994 107.361 53.048 ; + END + END r0_rd_out[373] + PIN r0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 52.994 107.649 53.048 ; + END + END r0_rd_out[374] + PIN r0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 52.994 107.937 53.048 ; + END + END r0_rd_out[375] + PIN r0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 52.994 108.225 53.048 ; + END + END r0_rd_out[376] + PIN r0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 52.994 108.513 53.048 ; + END + END r0_rd_out[377] + PIN r0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 52.994 108.801 53.048 ; + END + END r0_rd_out[378] + PIN r0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 52.994 109.089 53.048 ; + END + END r0_rd_out[379] + PIN r0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 52.994 109.377 53.048 ; + END + END r0_rd_out[380] + PIN r0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 52.994 109.665 53.048 ; + END + END r0_rd_out[381] + PIN r0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 52.994 109.953 53.048 ; + END + END r0_rd_out[382] + PIN r0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 52.994 110.241 53.048 ; + END + END r0_rd_out[383] + PIN r0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 52.994 110.529 53.048 ; + END + END r0_rd_out[384] + PIN r0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 52.994 110.817 53.048 ; + END + END r0_rd_out[385] + PIN r0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 52.994 111.105 53.048 ; + END + END r0_rd_out[386] + PIN r0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 52.994 111.393 53.048 ; + END + END r0_rd_out[387] + PIN r0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 52.994 111.681 53.048 ; + END + END r0_rd_out[388] + PIN r0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 52.994 111.969 53.048 ; + END + END r0_rd_out[389] + PIN r0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 52.994 112.257 53.048 ; + END + END r0_rd_out[390] + PIN r0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 52.994 112.545 53.048 ; + END + END r0_rd_out[391] + PIN r0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 52.994 112.833 53.048 ; + END + END r0_rd_out[392] + PIN r0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 52.994 113.121 53.048 ; + END + END r0_rd_out[393] + PIN r0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 52.994 113.409 53.048 ; + END + END r0_rd_out[394] + PIN r0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 52.994 113.697 53.048 ; + END + END r0_rd_out[395] + PIN r0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 52.994 113.985 53.048 ; + END + END r0_rd_out[396] + PIN r0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 52.994 114.273 53.048 ; + END + END r0_rd_out[397] + PIN r0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 52.994 114.561 53.048 ; + END + END r0_rd_out[398] + PIN r0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 52.994 114.849 53.048 ; + END + END r0_rd_out[399] + PIN r0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 52.994 115.137 53.048 ; + END + END r0_rd_out[400] + PIN r0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 52.994 115.425 53.048 ; + END + END r0_rd_out[401] + PIN r0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 52.994 115.713 53.048 ; + END + END r0_rd_out[402] + PIN r0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 52.994 116.001 53.048 ; + END + END r0_rd_out[403] + PIN r0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 52.994 116.289 53.048 ; + END + END r0_rd_out[404] + PIN r0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 52.994 116.577 53.048 ; + END + END r0_rd_out[405] + PIN r0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 52.994 116.865 53.048 ; + END + END r0_rd_out[406] + PIN r0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 52.994 117.153 53.048 ; + END + END r0_rd_out[407] + PIN r0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 52.994 117.441 53.048 ; + END + END r0_rd_out[408] + PIN r0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 52.994 117.729 53.048 ; + END + END r0_rd_out[409] + PIN r0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 52.994 118.017 53.048 ; + END + END r0_rd_out[410] + PIN r0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 52.994 118.305 53.048 ; + END + END r0_rd_out[411] + PIN r0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 52.994 118.593 53.048 ; + END + END r0_rd_out[412] + PIN r0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 52.994 118.881 53.048 ; + END + END r0_rd_out[413] + PIN r0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 52.994 119.169 53.048 ; + END + END r0_rd_out[414] + PIN r0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 52.994 119.457 53.048 ; + END + END r0_rd_out[415] + PIN r0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 52.994 119.745 53.048 ; + END + END r0_rd_out[416] + PIN r0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 52.994 120.033 53.048 ; + END + END r0_rd_out[417] + PIN r0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 52.994 120.321 53.048 ; + END + END r0_rd_out[418] + PIN r0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 52.994 120.609 53.048 ; + END + END r0_rd_out[419] + PIN r0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 52.994 120.897 53.048 ; + END + END r0_rd_out[420] + PIN r0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 52.994 121.185 53.048 ; + END + END r0_rd_out[421] + PIN r0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 52.994 121.473 53.048 ; + END + END r0_rd_out[422] + PIN r0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 52.994 121.761 53.048 ; + END + END r0_rd_out[423] + PIN r0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 52.994 122.049 53.048 ; + END + END r0_rd_out[424] + PIN r0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 52.994 122.337 53.048 ; + END + END r0_rd_out[425] + PIN r0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 52.994 122.625 53.048 ; + END + END r0_rd_out[426] + PIN r0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 52.994 122.913 53.048 ; + END + END r0_rd_out[427] + PIN r0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 52.994 123.201 53.048 ; + END + END r0_rd_out[428] + PIN r0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 52.994 123.489 53.048 ; + END + END r0_rd_out[429] + PIN r0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 52.994 123.777 53.048 ; + END + END r0_rd_out[430] + PIN r0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 52.994 124.065 53.048 ; + END + END r0_rd_out[431] + PIN r0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 52.994 124.353 53.048 ; + END + END r0_rd_out[432] + PIN r0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 52.994 124.641 53.048 ; + END + END r0_rd_out[433] + PIN r0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 52.994 124.929 53.048 ; + END + END r0_rd_out[434] + PIN r0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 52.994 125.217 53.048 ; + END + END r0_rd_out[435] + PIN r0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 52.994 125.505 53.048 ; + END + END r0_rd_out[436] + PIN r0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 52.994 125.793 53.048 ; + END + END r0_rd_out[437] + PIN r0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 52.994 126.081 53.048 ; + END + END r0_rd_out[438] + PIN r0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 52.994 126.369 53.048 ; + END + END r0_rd_out[439] + PIN r0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 52.994 126.657 53.048 ; + END + END r0_rd_out[440] + PIN r0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 52.994 126.945 53.048 ; + END + END r0_rd_out[441] + PIN r0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 52.994 127.233 53.048 ; + END + END r0_rd_out[442] + PIN r0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 52.994 127.521 53.048 ; + END + END r0_rd_out[443] + PIN r0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 52.994 127.809 53.048 ; + END + END r0_rd_out[444] + PIN r0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 52.994 128.097 53.048 ; + END + END r0_rd_out[445] + PIN r0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 52.994 128.385 53.048 ; + END + END r0_rd_out[446] + PIN r0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 52.994 128.673 53.048 ; + END + END r0_rd_out[447] + PIN r0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 52.994 128.961 53.048 ; + END + END r0_rd_out[448] + PIN r0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 52.994 129.249 53.048 ; + END + END r0_rd_out[449] + PIN r0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 52.994 129.537 53.048 ; + END + END r0_rd_out[450] + PIN r0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 52.994 129.825 53.048 ; + END + END r0_rd_out[451] + PIN r0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 52.994 130.113 53.048 ; + END + END r0_rd_out[452] + PIN r0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 52.994 130.401 53.048 ; + END + END r0_rd_out[453] + PIN r0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 52.994 130.689 53.048 ; + END + END r0_rd_out[454] + PIN r0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 52.994 130.977 53.048 ; + END + END r0_rd_out[455] + PIN r0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 52.994 131.265 53.048 ; + END + END r0_rd_out[456] + PIN r0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 52.994 131.553 53.048 ; + END + END r0_rd_out[457] + PIN r0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 52.994 131.841 53.048 ; + END + END r0_rd_out[458] + PIN r0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 52.994 132.129 53.048 ; + END + END r0_rd_out[459] + PIN r0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 52.994 132.417 53.048 ; + END + END r0_rd_out[460] + PIN r0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 52.994 132.705 53.048 ; + END + END r0_rd_out[461] + PIN r0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 52.994 132.993 53.048 ; + END + END r0_rd_out[462] + PIN r0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 52.994 133.281 53.048 ; + END + END r0_rd_out[463] + PIN r0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 52.994 133.569 53.048 ; + END + END r0_rd_out[464] + PIN r0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 52.994 133.857 53.048 ; + END + END r0_rd_out[465] + PIN r0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 52.994 134.145 53.048 ; + END + END r0_rd_out[466] + PIN r0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 52.994 134.433 53.048 ; + END + END r0_rd_out[467] + PIN r0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 52.994 134.721 53.048 ; + END + END r0_rd_out[468] + PIN r0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 52.994 135.009 53.048 ; + END + END r0_rd_out[469] + PIN r0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 52.994 135.297 53.048 ; + END + END r0_rd_out[470] + PIN r0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 52.994 135.585 53.048 ; + END + END r0_rd_out[471] + PIN r0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 52.994 135.873 53.048 ; + END + END r0_rd_out[472] + PIN r0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 52.994 136.161 53.048 ; + END + END r0_rd_out[473] + PIN r0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 52.994 136.449 53.048 ; + END + END r0_rd_out[474] + PIN r0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 52.994 136.737 53.048 ; + END + END r0_rd_out[475] + PIN r0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 52.994 137.025 53.048 ; + END + END r0_rd_out[476] + PIN r0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 52.994 137.313 53.048 ; + END + END r0_rd_out[477] + PIN r0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 52.994 137.601 53.048 ; + END + END r0_rd_out[478] + PIN r0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 52.994 137.889 53.048 ; + END + END r0_rd_out[479] + PIN r0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 52.994 138.177 53.048 ; + END + END r0_rd_out[480] + PIN r0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 52.994 138.465 53.048 ; + END + END r0_rd_out[481] + PIN r0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 52.994 138.753 53.048 ; + END + END r0_rd_out[482] + PIN r0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 52.994 139.041 53.048 ; + END + END r0_rd_out[483] + PIN r0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 52.994 139.329 53.048 ; + END + END r0_rd_out[484] + PIN r0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 52.994 139.617 53.048 ; + END + END r0_rd_out[485] + PIN r0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 52.994 139.905 53.048 ; + END + END r0_rd_out[486] + PIN r0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 52.994 140.193 53.048 ; + END + END r0_rd_out[487] + PIN r0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 52.994 140.481 53.048 ; + END + END r0_rd_out[488] + PIN r0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 52.994 140.769 53.048 ; + END + END r0_rd_out[489] + PIN r0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 52.994 141.057 53.048 ; + END + END r0_rd_out[490] + PIN r0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 52.994 141.345 53.048 ; + END + END r0_rd_out[491] + PIN r0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 52.994 141.633 53.048 ; + END + END r0_rd_out[492] + PIN r0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 52.994 141.921 53.048 ; + END + END r0_rd_out[493] + PIN r0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 52.994 142.209 53.048 ; + END + END r0_rd_out[494] + PIN r0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 52.994 142.497 53.048 ; + END + END r0_rd_out[495] + PIN r0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 52.994 142.785 53.048 ; + END + END r0_rd_out[496] + PIN r0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 52.994 143.073 53.048 ; + END + END r0_rd_out[497] + PIN r0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 52.994 143.361 53.048 ; + END + END r0_rd_out[498] + PIN r0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 52.994 143.649 53.048 ; + END + END r0_rd_out[499] + PIN r0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 52.994 143.937 53.048 ; + END + END r0_rd_out[500] + PIN r0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 52.994 144.225 53.048 ; + END + END r0_rd_out[501] + PIN r0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 52.994 144.513 53.048 ; + END + END r0_rd_out[502] + PIN r0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 52.994 144.801 53.048 ; + END + END r0_rd_out[503] + PIN r0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 52.994 145.089 53.048 ; + END + END r0_rd_out[504] + PIN r0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 52.994 145.377 53.048 ; + END + END r0_rd_out[505] + PIN r0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 52.994 145.665 53.048 ; + END + END r0_rd_out[506] + PIN r0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 52.994 145.953 53.048 ; + END + END r0_rd_out[507] + PIN r0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 52.994 146.241 53.048 ; + END + END r0_rd_out[508] + PIN r0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 52.994 146.529 53.048 ; + END + END r0_rd_out[509] + PIN r0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 52.994 146.817 53.048 ; + END + END r0_rd_out[510] + PIN r0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 52.994 147.105 53.048 ; + END + END r0_rd_out[511] + PIN r0_rd_out[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 52.994 147.393 53.048 ; + END + END r0_rd_out[512] + PIN r0_rd_out[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 52.994 147.681 53.048 ; + END + END r0_rd_out[513] + PIN r0_rd_out[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 52.994 147.969 53.048 ; + END + END r0_rd_out[514] + PIN r0_rd_out[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 52.994 148.257 53.048 ; + END + END r0_rd_out[515] + PIN r0_rd_out[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 52.994 148.545 53.048 ; + END + END r0_rd_out[516] + PIN r0_rd_out[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 52.994 148.833 53.048 ; + END + END r0_rd_out[517] + PIN r0_rd_out[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 52.994 149.121 53.048 ; + END + END r0_rd_out[518] + PIN r0_rd_out[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 52.994 149.409 53.048 ; + END + END r0_rd_out[519] + PIN r0_rd_out[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 52.994 149.697 53.048 ; + END + END r0_rd_out[520] + PIN r0_rd_out[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 52.994 149.985 53.048 ; + END + END r0_rd_out[521] + PIN r0_rd_out[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 52.994 150.273 53.048 ; + END + END r0_rd_out[522] + PIN r0_rd_out[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 52.994 150.561 53.048 ; + END + END r0_rd_out[523] + PIN r0_rd_out[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 52.994 150.849 53.048 ; + END + END r0_rd_out[524] + PIN r0_rd_out[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 52.994 151.137 53.048 ; + END + END r0_rd_out[525] + PIN r0_rd_out[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 52.994 151.425 53.048 ; + END + END r0_rd_out[526] + PIN r0_rd_out[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 52.994 151.713 53.048 ; + END + END r0_rd_out[527] + PIN r0_rd_out[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 52.994 152.001 53.048 ; + END + END r0_rd_out[528] + PIN r0_rd_out[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 52.994 152.289 53.048 ; + END + END r0_rd_out[529] + PIN r0_rd_out[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 52.994 152.577 53.048 ; + END + END r0_rd_out[530] + PIN r0_rd_out[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 52.994 152.865 53.048 ; + END + END r0_rd_out[531] + PIN r0_rd_out[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 52.994 153.153 53.048 ; + END + END r0_rd_out[532] + PIN r0_rd_out[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 52.994 153.441 53.048 ; + END + END r0_rd_out[533] + PIN r0_rd_out[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 52.994 153.729 53.048 ; + END + END r0_rd_out[534] + PIN r0_rd_out[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 52.994 154.017 53.048 ; + END + END r0_rd_out[535] + PIN r0_rd_out[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 52.994 154.305 53.048 ; + END + END r0_rd_out[536] + PIN r0_rd_out[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 52.994 154.593 53.048 ; + END + END r0_rd_out[537] + PIN r0_rd_out[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 52.994 154.881 53.048 ; + END + END r0_rd_out[538] + PIN r0_rd_out[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 52.994 155.169 53.048 ; + END + END r0_rd_out[539] + PIN r0_rd_out[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 52.994 155.457 53.048 ; + END + END r0_rd_out[540] + PIN r0_rd_out[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 52.994 155.745 53.048 ; + END + END r0_rd_out[541] + PIN r0_rd_out[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 52.994 156.033 53.048 ; + END + END r0_rd_out[542] + PIN r0_rd_out[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 52.994 156.321 53.048 ; + END + END r0_rd_out[543] + PIN r0_rd_out[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 52.994 156.609 53.048 ; + END + END r0_rd_out[544] + PIN r0_rd_out[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 52.994 156.897 53.048 ; + END + END r0_rd_out[545] + PIN r0_rd_out[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 52.994 157.185 53.048 ; + END + END r0_rd_out[546] + PIN r0_rd_out[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 52.994 157.473 53.048 ; + END + END r0_rd_out[547] + PIN r0_rd_out[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 52.994 157.761 53.048 ; + END + END r0_rd_out[548] + PIN r0_rd_out[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 52.994 158.049 53.048 ; + END + END r0_rd_out[549] + PIN r0_rd_out[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 52.994 158.337 53.048 ; + END + END r0_rd_out[550] + PIN r0_rd_out[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 52.994 158.625 53.048 ; + END + END r0_rd_out[551] + PIN r0_rd_out[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 52.994 158.913 53.048 ; + END + END r0_rd_out[552] + PIN r0_rd_out[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 52.994 159.201 53.048 ; + END + END r0_rd_out[553] + PIN r0_rd_out[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 52.994 159.489 53.048 ; + END + END r0_rd_out[554] + PIN r0_rd_out[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 52.994 159.777 53.048 ; + END + END r0_rd_out[555] + PIN r0_rd_out[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 52.994 160.065 53.048 ; + END + END r0_rd_out[556] + PIN r0_rd_out[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 52.994 160.353 53.048 ; + END + END r0_rd_out[557] + PIN r0_rd_out[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 52.994 160.641 53.048 ; + END + END r0_rd_out[558] + PIN r0_rd_out[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 52.994 160.929 53.048 ; + END + END r0_rd_out[559] + PIN r0_rd_out[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 52.994 161.217 53.048 ; + END + END r0_rd_out[560] + PIN r0_rd_out[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 52.994 161.505 53.048 ; + END + END r0_rd_out[561] + PIN r0_rd_out[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 52.994 161.793 53.048 ; + END + END r0_rd_out[562] + PIN r0_rd_out[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 52.994 162.081 53.048 ; + END + END r0_rd_out[563] + PIN r0_rd_out[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 52.994 162.369 53.048 ; + END + END r0_rd_out[564] + PIN r0_rd_out[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 52.994 162.657 53.048 ; + END + END r0_rd_out[565] + PIN r0_rd_out[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 52.994 162.945 53.048 ; + END + END r0_rd_out[566] + PIN r0_rd_out[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.215 52.994 163.233 53.048 ; + END + END r0_rd_out[567] + PIN r0_rd_out[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.503 52.994 163.521 53.048 ; + END + END r0_rd_out[568] + PIN r0_rd_out[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.791 52.994 163.809 53.048 ; + END + END r0_rd_out[569] + PIN r0_rd_out[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.079 52.994 164.097 53.048 ; + END + END r0_rd_out[570] + PIN r0_rd_out[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 52.994 164.385 53.048 ; + END + END r0_rd_out[571] + PIN r0_rd_out[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.655 52.994 164.673 53.048 ; + END + END r0_rd_out[572] + PIN r0_rd_out[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.943 52.994 164.961 53.048 ; + END + END r0_rd_out[573] + PIN r0_rd_out[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.231 52.994 165.249 53.048 ; + END + END r0_rd_out[574] + PIN r0_rd_out[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.519 52.994 165.537 53.048 ; + END + END r0_rd_out[575] + PIN r0_rd_out[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 52.994 165.825 53.048 ; + END + END r0_rd_out[576] + PIN r0_rd_out[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.095 52.994 166.113 53.048 ; + END + END r0_rd_out[577] + PIN r0_rd_out[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.383 52.994 166.401 53.048 ; + END + END r0_rd_out[578] + PIN r0_rd_out[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.671 52.994 166.689 53.048 ; + END + END r0_rd_out[579] + PIN r0_rd_out[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.959 52.994 166.977 53.048 ; + END + END r0_rd_out[580] + PIN r0_rd_out[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 52.994 167.265 53.048 ; + END + END r0_rd_out[581] + PIN r0_rd_out[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.535 52.994 167.553 53.048 ; + END + END r0_rd_out[582] + PIN r0_rd_out[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.823 52.994 167.841 53.048 ; + END + END r0_rd_out[583] + PIN r0_rd_out[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.111 52.994 168.129 53.048 ; + END + END r0_rd_out[584] + PIN r0_rd_out[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.399 52.994 168.417 53.048 ; + END + END r0_rd_out[585] + PIN r0_rd_out[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 52.994 168.705 53.048 ; + END + END r0_rd_out[586] + PIN r0_rd_out[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.975 52.994 168.993 53.048 ; + END + END r0_rd_out[587] + PIN r0_rd_out[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.263 52.994 169.281 53.048 ; + END + END r0_rd_out[588] + PIN r0_rd_out[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.551 52.994 169.569 53.048 ; + END + END r0_rd_out[589] + PIN r0_rd_out[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.839 52.994 169.857 53.048 ; + END + END r0_rd_out[590] + PIN r0_rd_out[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 52.994 170.145 53.048 ; + END + END r0_rd_out[591] + PIN r0_rd_out[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.415 52.994 170.433 53.048 ; + END + END r0_rd_out[592] + PIN r0_rd_out[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.703 52.994 170.721 53.048 ; + END + END r0_rd_out[593] + PIN r0_rd_out[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.991 52.994 171.009 53.048 ; + END + END r0_rd_out[594] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.188 0.072 43.212 ; + END + END w0_addr_in[0] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.332 0.072 43.356 ; + END + END r0_addr_in[0] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.279 52.994 171.297 53.048 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 52.994 171.585 53.048 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.855 52.994 171.873 53.048 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.143 52.994 172.161 53.048 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.431 52.994 172.449 53.048 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 189.480 0.336 ; + RECT 0.216 1.008 189.480 1.104 ; + RECT 0.216 1.776 189.480 1.872 ; + RECT 0.216 2.544 189.480 2.640 ; + RECT 0.216 3.312 189.480 3.408 ; + RECT 0.216 4.080 189.480 4.176 ; + RECT 0.216 4.848 189.480 4.944 ; + RECT 0.216 5.616 189.480 5.712 ; + RECT 0.216 6.384 189.480 6.480 ; + RECT 0.216 7.152 189.480 7.248 ; + RECT 0.216 7.920 189.480 8.016 ; + RECT 0.216 8.688 189.480 8.784 ; + RECT 0.216 9.456 189.480 9.552 ; + RECT 0.216 10.224 189.480 10.320 ; + RECT 0.216 10.992 189.480 11.088 ; + RECT 0.216 11.760 189.480 11.856 ; + RECT 0.216 12.528 189.480 12.624 ; + RECT 0.216 13.296 189.480 13.392 ; + RECT 0.216 14.064 189.480 14.160 ; + RECT 0.216 14.832 189.480 14.928 ; + RECT 0.216 15.600 189.480 15.696 ; + RECT 0.216 16.368 189.480 16.464 ; + RECT 0.216 17.136 189.480 17.232 ; + RECT 0.216 17.904 189.480 18.000 ; + RECT 0.216 18.672 189.480 18.768 ; + RECT 0.216 19.440 189.480 19.536 ; + RECT 0.216 20.208 189.480 20.304 ; + RECT 0.216 20.976 189.480 21.072 ; + RECT 0.216 21.744 189.480 21.840 ; + RECT 0.216 22.512 189.480 22.608 ; + RECT 0.216 23.280 189.480 23.376 ; + RECT 0.216 24.048 189.480 24.144 ; + RECT 0.216 24.816 189.480 24.912 ; + RECT 0.216 25.584 189.480 25.680 ; + RECT 0.216 26.352 189.480 26.448 ; + RECT 0.216 27.120 189.480 27.216 ; + RECT 0.216 27.888 189.480 27.984 ; + RECT 0.216 28.656 189.480 28.752 ; + RECT 0.216 29.424 189.480 29.520 ; + RECT 0.216 30.192 189.480 30.288 ; + RECT 0.216 30.960 189.480 31.056 ; + RECT 0.216 31.728 189.480 31.824 ; + RECT 0.216 32.496 189.480 32.592 ; + RECT 0.216 33.264 189.480 33.360 ; + RECT 0.216 34.032 189.480 34.128 ; + RECT 0.216 34.800 189.480 34.896 ; + RECT 0.216 35.568 189.480 35.664 ; + RECT 0.216 36.336 189.480 36.432 ; + RECT 0.216 37.104 189.480 37.200 ; + RECT 0.216 37.872 189.480 37.968 ; + RECT 0.216 38.640 189.480 38.736 ; + RECT 0.216 39.408 189.480 39.504 ; + RECT 0.216 40.176 189.480 40.272 ; + RECT 0.216 40.944 189.480 41.040 ; + RECT 0.216 41.712 189.480 41.808 ; + RECT 0.216 42.480 189.480 42.576 ; + RECT 0.216 43.248 189.480 43.344 ; + RECT 0.216 44.016 189.480 44.112 ; + RECT 0.216 44.784 189.480 44.880 ; + RECT 0.216 45.552 189.480 45.648 ; + RECT 0.216 46.320 189.480 46.416 ; + RECT 0.216 47.088 189.480 47.184 ; + RECT 0.216 47.856 189.480 47.952 ; + RECT 0.216 48.624 189.480 48.720 ; + RECT 0.216 49.392 189.480 49.488 ; + RECT 0.216 50.160 189.480 50.256 ; + RECT 0.216 50.928 189.480 51.024 ; + RECT 0.216 51.696 189.480 51.792 ; + RECT 0.216 52.464 189.480 52.560 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 189.480 0.336 ; + RECT 0.216 1.008 189.480 1.104 ; + RECT 0.216 1.776 189.480 1.872 ; + RECT 0.216 2.544 189.480 2.640 ; + RECT 0.216 3.312 189.480 3.408 ; + RECT 0.216 4.080 189.480 4.176 ; + RECT 0.216 4.848 189.480 4.944 ; + RECT 0.216 5.616 189.480 5.712 ; + RECT 0.216 6.384 189.480 6.480 ; + RECT 0.216 7.152 189.480 7.248 ; + RECT 0.216 7.920 189.480 8.016 ; + RECT 0.216 8.688 189.480 8.784 ; + RECT 0.216 9.456 189.480 9.552 ; + RECT 0.216 10.224 189.480 10.320 ; + RECT 0.216 10.992 189.480 11.088 ; + RECT 0.216 11.760 189.480 11.856 ; + RECT 0.216 12.528 189.480 12.624 ; + RECT 0.216 13.296 189.480 13.392 ; + RECT 0.216 14.064 189.480 14.160 ; + RECT 0.216 14.832 189.480 14.928 ; + RECT 0.216 15.600 189.480 15.696 ; + RECT 0.216 16.368 189.480 16.464 ; + RECT 0.216 17.136 189.480 17.232 ; + RECT 0.216 17.904 189.480 18.000 ; + RECT 0.216 18.672 189.480 18.768 ; + RECT 0.216 19.440 189.480 19.536 ; + RECT 0.216 20.208 189.480 20.304 ; + RECT 0.216 20.976 189.480 21.072 ; + RECT 0.216 21.744 189.480 21.840 ; + RECT 0.216 22.512 189.480 22.608 ; + RECT 0.216 23.280 189.480 23.376 ; + RECT 0.216 24.048 189.480 24.144 ; + RECT 0.216 24.816 189.480 24.912 ; + RECT 0.216 25.584 189.480 25.680 ; + RECT 0.216 26.352 189.480 26.448 ; + RECT 0.216 27.120 189.480 27.216 ; + RECT 0.216 27.888 189.480 27.984 ; + RECT 0.216 28.656 189.480 28.752 ; + RECT 0.216 29.424 189.480 29.520 ; + RECT 0.216 30.192 189.480 30.288 ; + RECT 0.216 30.960 189.480 31.056 ; + RECT 0.216 31.728 189.480 31.824 ; + RECT 0.216 32.496 189.480 32.592 ; + RECT 0.216 33.264 189.480 33.360 ; + RECT 0.216 34.032 189.480 34.128 ; + RECT 0.216 34.800 189.480 34.896 ; + RECT 0.216 35.568 189.480 35.664 ; + RECT 0.216 36.336 189.480 36.432 ; + RECT 0.216 37.104 189.480 37.200 ; + RECT 0.216 37.872 189.480 37.968 ; + RECT 0.216 38.640 189.480 38.736 ; + RECT 0.216 39.408 189.480 39.504 ; + RECT 0.216 40.176 189.480 40.272 ; + RECT 0.216 40.944 189.480 41.040 ; + RECT 0.216 41.712 189.480 41.808 ; + RECT 0.216 42.480 189.480 42.576 ; + RECT 0.216 43.248 189.480 43.344 ; + RECT 0.216 44.016 189.480 44.112 ; + RECT 0.216 44.784 189.480 44.880 ; + RECT 0.216 45.552 189.480 45.648 ; + RECT 0.216 46.320 189.480 46.416 ; + RECT 0.216 47.088 189.480 47.184 ; + RECT 0.216 47.856 189.480 47.952 ; + RECT 0.216 48.624 189.480 48.720 ; + RECT 0.216 49.392 189.480 49.488 ; + RECT 0.216 50.160 189.480 50.256 ; + RECT 0.216 50.928 189.480 51.024 ; + RECT 0.216 51.696 189.480 51.792 ; + RECT 0.216 52.464 189.480 52.560 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 189.696 53.048 ; + LAYER M2 ; + RECT 0 0 189.696 53.048 ; + LAYER M3 ; + RECT 0 0 189.696 53.048 ; + LAYER M4 ; + RECT 0 0 189.696 53.048 ; + END +END fakeram_595x8_1r1w + +END LIBRARY diff --git a/designs/asap7/coralnpu/sram/lef/fakeram_633x8_1r1w.lef b/designs/asap7/coralnpu/sram/lef/fakeram_633x8_1r1w.lef new file mode 100644 index 0000000..2ce088e --- /dev/null +++ b/designs/asap7/coralnpu/sram/lef/fakeram_633x8_1r1w.lef @@ -0,0 +1,17336 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_633x8_1r1w + FOREIGN fakeram_633x8_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 201.811 BY 56.413 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.420 0.072 0.444 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.148 0.072 2.172 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.012 0.072 3.036 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.452 0.072 4.476 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.468 0.072 6.492 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.908 0.072 7.932 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.772 0.072 8.796 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.060 0.072 9.084 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.924 0.072 9.948 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.500 0.072 10.524 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.788 0.072 10.812 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.652 0.072 11.676 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.228 0.072 12.252 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.244 0.072 14.268 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.108 0.072 15.132 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.684 0.072 15.708 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.972 0.072 15.996 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.548 0.072 16.572 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.700 0.072 17.724 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.564 0.072 18.588 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.140 0.072 19.164 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.004 0.072 20.028 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.292 0.072 20.316 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.868 0.072 20.892 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.156 0.072 21.180 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.732 0.072 21.756 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.020 0.072 22.044 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.596 0.072 22.620 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.884 0.072 22.908 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 0.276 201.811 0.300 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 0.420 201.811 0.444 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 0.564 201.811 0.588 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 0.708 201.811 0.732 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 0.852 201.811 0.876 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 0.996 201.811 1.020 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 1.140 201.811 1.164 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 1.284 201.811 1.308 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 1.428 201.811 1.452 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 1.572 201.811 1.596 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 1.716 201.811 1.740 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 1.860 201.811 1.884 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.004 201.811 2.028 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.148 201.811 2.172 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.292 201.811 2.316 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.436 201.811 2.460 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.580 201.811 2.604 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.724 201.811 2.748 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 2.868 201.811 2.892 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.012 201.811 3.036 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.156 201.811 3.180 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.300 201.811 3.324 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.444 201.811 3.468 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.588 201.811 3.612 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.732 201.811 3.756 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 3.876 201.811 3.900 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.020 201.811 4.044 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.164 201.811 4.188 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.308 201.811 4.332 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.452 201.811 4.476 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.596 201.811 4.620 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.740 201.811 4.764 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 4.884 201.811 4.908 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.028 201.811 5.052 ; + END + END w0_wmask_in[192] + PIN w0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.172 201.811 5.196 ; + END + END w0_wmask_in[193] + PIN w0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.316 201.811 5.340 ; + END + END w0_wmask_in[194] + PIN w0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.460 201.811 5.484 ; + END + END w0_wmask_in[195] + PIN w0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.604 201.811 5.628 ; + END + END w0_wmask_in[196] + PIN w0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.748 201.811 5.772 ; + END + END w0_wmask_in[197] + PIN w0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 5.892 201.811 5.916 ; + END + END w0_wmask_in[198] + PIN w0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.036 201.811 6.060 ; + END + END w0_wmask_in[199] + PIN w0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.180 201.811 6.204 ; + END + END w0_wmask_in[200] + PIN w0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.324 201.811 6.348 ; + END + END w0_wmask_in[201] + PIN w0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.468 201.811 6.492 ; + END + END w0_wmask_in[202] + PIN w0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.612 201.811 6.636 ; + END + END w0_wmask_in[203] + PIN w0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.756 201.811 6.780 ; + END + END w0_wmask_in[204] + PIN w0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 6.900 201.811 6.924 ; + END + END w0_wmask_in[205] + PIN w0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.044 201.811 7.068 ; + END + END w0_wmask_in[206] + PIN w0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.188 201.811 7.212 ; + END + END w0_wmask_in[207] + PIN w0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.332 201.811 7.356 ; + END + END w0_wmask_in[208] + PIN w0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.476 201.811 7.500 ; + END + END w0_wmask_in[209] + PIN w0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.620 201.811 7.644 ; + END + END w0_wmask_in[210] + PIN w0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.764 201.811 7.788 ; + END + END w0_wmask_in[211] + PIN w0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 7.908 201.811 7.932 ; + END + END w0_wmask_in[212] + PIN w0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.052 201.811 8.076 ; + END + END w0_wmask_in[213] + PIN w0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.196 201.811 8.220 ; + END + END w0_wmask_in[214] + PIN w0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.340 201.811 8.364 ; + END + END w0_wmask_in[215] + PIN w0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.484 201.811 8.508 ; + END + END w0_wmask_in[216] + PIN w0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.628 201.811 8.652 ; + END + END w0_wmask_in[217] + PIN w0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.772 201.811 8.796 ; + END + END w0_wmask_in[218] + PIN w0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 8.916 201.811 8.940 ; + END + END w0_wmask_in[219] + PIN w0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.060 201.811 9.084 ; + END + END w0_wmask_in[220] + PIN w0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.204 201.811 9.228 ; + END + END w0_wmask_in[221] + PIN w0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.348 201.811 9.372 ; + END + END w0_wmask_in[222] + PIN w0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.492 201.811 9.516 ; + END + END w0_wmask_in[223] + PIN w0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.636 201.811 9.660 ; + END + END w0_wmask_in[224] + PIN w0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.780 201.811 9.804 ; + END + END w0_wmask_in[225] + PIN w0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 9.924 201.811 9.948 ; + END + END w0_wmask_in[226] + PIN w0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.068 201.811 10.092 ; + END + END w0_wmask_in[227] + PIN w0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.212 201.811 10.236 ; + END + END w0_wmask_in[228] + PIN w0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.356 201.811 10.380 ; + END + END w0_wmask_in[229] + PIN w0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.500 201.811 10.524 ; + END + END w0_wmask_in[230] + PIN w0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.644 201.811 10.668 ; + END + END w0_wmask_in[231] + PIN w0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.788 201.811 10.812 ; + END + END w0_wmask_in[232] + PIN w0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 10.932 201.811 10.956 ; + END + END w0_wmask_in[233] + PIN w0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.076 201.811 11.100 ; + END + END w0_wmask_in[234] + PIN w0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.220 201.811 11.244 ; + END + END w0_wmask_in[235] + PIN w0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.364 201.811 11.388 ; + END + END w0_wmask_in[236] + PIN w0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.508 201.811 11.532 ; + END + END w0_wmask_in[237] + PIN w0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.652 201.811 11.676 ; + END + END w0_wmask_in[238] + PIN w0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.796 201.811 11.820 ; + END + END w0_wmask_in[239] + PIN w0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 11.940 201.811 11.964 ; + END + END w0_wmask_in[240] + PIN w0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.084 201.811 12.108 ; + END + END w0_wmask_in[241] + PIN w0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.228 201.811 12.252 ; + END + END w0_wmask_in[242] + PIN w0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.372 201.811 12.396 ; + END + END w0_wmask_in[243] + PIN w0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.516 201.811 12.540 ; + END + END w0_wmask_in[244] + PIN w0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.660 201.811 12.684 ; + END + END w0_wmask_in[245] + PIN w0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.804 201.811 12.828 ; + END + END w0_wmask_in[246] + PIN w0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 12.948 201.811 12.972 ; + END + END w0_wmask_in[247] + PIN w0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.092 201.811 13.116 ; + END + END w0_wmask_in[248] + PIN w0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.236 201.811 13.260 ; + END + END w0_wmask_in[249] + PIN w0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.380 201.811 13.404 ; + END + END w0_wmask_in[250] + PIN w0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.524 201.811 13.548 ; + END + END w0_wmask_in[251] + PIN w0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.668 201.811 13.692 ; + END + END w0_wmask_in[252] + PIN w0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.812 201.811 13.836 ; + END + END w0_wmask_in[253] + PIN w0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 13.956 201.811 13.980 ; + END + END w0_wmask_in[254] + PIN w0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.100 201.811 14.124 ; + END + END w0_wmask_in[255] + PIN w0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.244 201.811 14.268 ; + END + END w0_wmask_in[256] + PIN w0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.388 201.811 14.412 ; + END + END w0_wmask_in[257] + PIN w0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.532 201.811 14.556 ; + END + END w0_wmask_in[258] + PIN w0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.676 201.811 14.700 ; + END + END w0_wmask_in[259] + PIN w0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.820 201.811 14.844 ; + END + END w0_wmask_in[260] + PIN w0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 14.964 201.811 14.988 ; + END + END w0_wmask_in[261] + PIN w0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.108 201.811 15.132 ; + END + END w0_wmask_in[262] + PIN w0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.252 201.811 15.276 ; + END + END w0_wmask_in[263] + PIN w0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.396 201.811 15.420 ; + END + END w0_wmask_in[264] + PIN w0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.540 201.811 15.564 ; + END + END w0_wmask_in[265] + PIN w0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.684 201.811 15.708 ; + END + END w0_wmask_in[266] + PIN w0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.828 201.811 15.852 ; + END + END w0_wmask_in[267] + PIN w0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 15.972 201.811 15.996 ; + END + END w0_wmask_in[268] + PIN w0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.116 201.811 16.140 ; + END + END w0_wmask_in[269] + PIN w0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.260 201.811 16.284 ; + END + END w0_wmask_in[270] + PIN w0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.404 201.811 16.428 ; + END + END w0_wmask_in[271] + PIN w0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.548 201.811 16.572 ; + END + END w0_wmask_in[272] + PIN w0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.692 201.811 16.716 ; + END + END w0_wmask_in[273] + PIN w0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.836 201.811 16.860 ; + END + END w0_wmask_in[274] + PIN w0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 16.980 201.811 17.004 ; + END + END w0_wmask_in[275] + PIN w0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.124 201.811 17.148 ; + END + END w0_wmask_in[276] + PIN w0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.268 201.811 17.292 ; + END + END w0_wmask_in[277] + PIN w0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.412 201.811 17.436 ; + END + END w0_wmask_in[278] + PIN w0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.556 201.811 17.580 ; + END + END w0_wmask_in[279] + PIN w0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.700 201.811 17.724 ; + END + END w0_wmask_in[280] + PIN w0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.844 201.811 17.868 ; + END + END w0_wmask_in[281] + PIN w0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 17.988 201.811 18.012 ; + END + END w0_wmask_in[282] + PIN w0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.132 201.811 18.156 ; + END + END w0_wmask_in[283] + PIN w0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.276 201.811 18.300 ; + END + END w0_wmask_in[284] + PIN w0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.420 201.811 18.444 ; + END + END w0_wmask_in[285] + PIN w0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.564 201.811 18.588 ; + END + END w0_wmask_in[286] + PIN w0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.708 201.811 18.732 ; + END + END w0_wmask_in[287] + PIN w0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.852 201.811 18.876 ; + END + END w0_wmask_in[288] + PIN w0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 18.996 201.811 19.020 ; + END + END w0_wmask_in[289] + PIN w0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 19.140 201.811 19.164 ; + END + END w0_wmask_in[290] + PIN w0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 19.284 201.811 19.308 ; + END + END w0_wmask_in[291] + PIN w0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 19.428 201.811 19.452 ; + END + END w0_wmask_in[292] + PIN w0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 19.572 201.811 19.596 ; + END + END w0_wmask_in[293] + PIN w0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 19.716 201.811 19.740 ; + END + END w0_wmask_in[294] + PIN w0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 19.860 201.811 19.884 ; + END + END w0_wmask_in[295] + PIN w0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.004 201.811 20.028 ; + END + END w0_wmask_in[296] + PIN w0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.148 201.811 20.172 ; + END + END w0_wmask_in[297] + PIN w0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.292 201.811 20.316 ; + END + END w0_wmask_in[298] + PIN w0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.436 201.811 20.460 ; + END + END w0_wmask_in[299] + PIN w0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.580 201.811 20.604 ; + END + END w0_wmask_in[300] + PIN w0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.724 201.811 20.748 ; + END + END w0_wmask_in[301] + PIN w0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 20.868 201.811 20.892 ; + END + END w0_wmask_in[302] + PIN w0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.012 201.811 21.036 ; + END + END w0_wmask_in[303] + PIN w0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.156 201.811 21.180 ; + END + END w0_wmask_in[304] + PIN w0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.300 201.811 21.324 ; + END + END w0_wmask_in[305] + PIN w0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.444 201.811 21.468 ; + END + END w0_wmask_in[306] + PIN w0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.588 201.811 21.612 ; + END + END w0_wmask_in[307] + PIN w0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.732 201.811 21.756 ; + END + END w0_wmask_in[308] + PIN w0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 21.876 201.811 21.900 ; + END + END w0_wmask_in[309] + PIN w0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.020 201.811 22.044 ; + END + END w0_wmask_in[310] + PIN w0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.164 201.811 22.188 ; + END + END w0_wmask_in[311] + PIN w0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.308 201.811 22.332 ; + END + END w0_wmask_in[312] + PIN w0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.452 201.811 22.476 ; + END + END w0_wmask_in[313] + PIN w0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.596 201.811 22.620 ; + END + END w0_wmask_in[314] + PIN w0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.740 201.811 22.764 ; + END + END w0_wmask_in[315] + PIN w0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 22.884 201.811 22.908 ; + END + END w0_wmask_in[316] + PIN w0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 56.359 0.225 56.413 ; + END + END w0_wmask_in[317] + PIN w0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 56.359 0.513 56.413 ; + END + END w0_wmask_in[318] + PIN w0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 56.359 0.801 56.413 ; + END + END w0_wmask_in[319] + PIN w0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 56.359 1.089 56.413 ; + END + END w0_wmask_in[320] + PIN w0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 56.359 1.377 56.413 ; + END + END w0_wmask_in[321] + PIN w0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 56.359 1.665 56.413 ; + END + END w0_wmask_in[322] + PIN w0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 56.359 1.953 56.413 ; + END + END w0_wmask_in[323] + PIN w0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 56.359 2.241 56.413 ; + END + END w0_wmask_in[324] + PIN w0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 56.359 2.529 56.413 ; + END + END w0_wmask_in[325] + PIN w0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 56.359 2.817 56.413 ; + END + END w0_wmask_in[326] + PIN w0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 56.359 3.105 56.413 ; + END + END w0_wmask_in[327] + PIN w0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 56.359 3.393 56.413 ; + END + END w0_wmask_in[328] + PIN w0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 56.359 3.681 56.413 ; + END + END w0_wmask_in[329] + PIN w0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 56.359 3.969 56.413 ; + END + END w0_wmask_in[330] + PIN w0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 56.359 4.257 56.413 ; + END + END w0_wmask_in[331] + PIN w0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 56.359 4.545 56.413 ; + END + END w0_wmask_in[332] + PIN w0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 56.359 4.833 56.413 ; + END + END w0_wmask_in[333] + PIN w0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 56.359 5.121 56.413 ; + END + END w0_wmask_in[334] + PIN w0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 56.359 5.409 56.413 ; + END + END w0_wmask_in[335] + PIN w0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 56.359 5.697 56.413 ; + END + END w0_wmask_in[336] + PIN w0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 56.359 5.985 56.413 ; + END + END w0_wmask_in[337] + PIN w0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 56.359 6.273 56.413 ; + END + END w0_wmask_in[338] + PIN w0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 56.359 6.561 56.413 ; + END + END w0_wmask_in[339] + PIN w0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 56.359 6.849 56.413 ; + END + END w0_wmask_in[340] + PIN w0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 56.359 7.137 56.413 ; + END + END w0_wmask_in[341] + PIN w0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 56.359 7.425 56.413 ; + END + END w0_wmask_in[342] + PIN w0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 56.359 7.713 56.413 ; + END + END w0_wmask_in[343] + PIN w0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 56.359 8.001 56.413 ; + END + END w0_wmask_in[344] + PIN w0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 56.359 8.289 56.413 ; + END + END w0_wmask_in[345] + PIN w0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 56.359 8.577 56.413 ; + END + END w0_wmask_in[346] + PIN w0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 56.359 8.865 56.413 ; + END + END w0_wmask_in[347] + PIN w0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 56.359 9.153 56.413 ; + END + END w0_wmask_in[348] + PIN w0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 56.359 9.441 56.413 ; + END + END w0_wmask_in[349] + PIN w0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 56.359 9.729 56.413 ; + END + END w0_wmask_in[350] + PIN w0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 56.359 10.017 56.413 ; + END + END w0_wmask_in[351] + PIN w0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 56.359 10.305 56.413 ; + END + END w0_wmask_in[352] + PIN w0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 56.359 10.593 56.413 ; + END + END w0_wmask_in[353] + PIN w0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 56.359 10.881 56.413 ; + END + END w0_wmask_in[354] + PIN w0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 56.359 11.169 56.413 ; + END + END w0_wmask_in[355] + PIN w0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 56.359 11.457 56.413 ; + END + END w0_wmask_in[356] + PIN w0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 56.359 11.745 56.413 ; + END + END w0_wmask_in[357] + PIN w0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 56.359 12.033 56.413 ; + END + END w0_wmask_in[358] + PIN w0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 56.359 12.321 56.413 ; + END + END w0_wmask_in[359] + PIN w0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 56.359 12.609 56.413 ; + END + END w0_wmask_in[360] + PIN w0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 56.359 12.897 56.413 ; + END + END w0_wmask_in[361] + PIN w0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 56.359 13.185 56.413 ; + END + END w0_wmask_in[362] + PIN w0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 56.359 13.473 56.413 ; + END + END w0_wmask_in[363] + PIN w0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 56.359 13.761 56.413 ; + END + END w0_wmask_in[364] + PIN w0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 56.359 14.049 56.413 ; + END + END w0_wmask_in[365] + PIN w0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 56.359 14.337 56.413 ; + END + END w0_wmask_in[366] + PIN w0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 56.359 14.625 56.413 ; + END + END w0_wmask_in[367] + PIN w0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 56.359 14.913 56.413 ; + END + END w0_wmask_in[368] + PIN w0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 56.359 15.201 56.413 ; + END + END w0_wmask_in[369] + PIN w0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 56.359 15.489 56.413 ; + END + END w0_wmask_in[370] + PIN w0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 56.359 15.777 56.413 ; + END + END w0_wmask_in[371] + PIN w0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 56.359 16.065 56.413 ; + END + END w0_wmask_in[372] + PIN w0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 56.359 16.353 56.413 ; + END + END w0_wmask_in[373] + PIN w0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 56.359 16.641 56.413 ; + END + END w0_wmask_in[374] + PIN w0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 56.359 16.929 56.413 ; + END + END w0_wmask_in[375] + PIN w0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 56.359 17.217 56.413 ; + END + END w0_wmask_in[376] + PIN w0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 56.359 17.505 56.413 ; + END + END w0_wmask_in[377] + PIN w0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 56.359 17.793 56.413 ; + END + END w0_wmask_in[378] + PIN w0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 56.359 18.081 56.413 ; + END + END w0_wmask_in[379] + PIN w0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 56.359 18.369 56.413 ; + END + END w0_wmask_in[380] + PIN w0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 56.359 18.657 56.413 ; + END + END w0_wmask_in[381] + PIN w0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 56.359 18.945 56.413 ; + END + END w0_wmask_in[382] + PIN w0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 56.359 19.233 56.413 ; + END + END w0_wmask_in[383] + PIN w0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 56.359 19.521 56.413 ; + END + END w0_wmask_in[384] + PIN w0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 56.359 19.809 56.413 ; + END + END w0_wmask_in[385] + PIN w0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 56.359 20.097 56.413 ; + END + END w0_wmask_in[386] + PIN w0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 56.359 20.385 56.413 ; + END + END w0_wmask_in[387] + PIN w0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 56.359 20.673 56.413 ; + END + END w0_wmask_in[388] + PIN w0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 56.359 20.961 56.413 ; + END + END w0_wmask_in[389] + PIN w0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 56.359 21.249 56.413 ; + END + END w0_wmask_in[390] + PIN w0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 56.359 21.537 56.413 ; + END + END w0_wmask_in[391] + PIN w0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 56.359 21.825 56.413 ; + END + END w0_wmask_in[392] + PIN w0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 56.359 22.113 56.413 ; + END + END w0_wmask_in[393] + PIN w0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 56.359 22.401 56.413 ; + END + END w0_wmask_in[394] + PIN w0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 56.359 22.689 56.413 ; + END + END w0_wmask_in[395] + PIN w0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 56.359 22.977 56.413 ; + END + END w0_wmask_in[396] + PIN w0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 56.359 23.265 56.413 ; + END + END w0_wmask_in[397] + PIN w0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 56.359 23.553 56.413 ; + END + END w0_wmask_in[398] + PIN w0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 56.359 23.841 56.413 ; + END + END w0_wmask_in[399] + PIN w0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 56.359 24.129 56.413 ; + END + END w0_wmask_in[400] + PIN w0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 56.359 24.417 56.413 ; + END + END w0_wmask_in[401] + PIN w0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 56.359 24.705 56.413 ; + END + END w0_wmask_in[402] + PIN w0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 56.359 24.993 56.413 ; + END + END w0_wmask_in[403] + PIN w0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 56.359 25.281 56.413 ; + END + END w0_wmask_in[404] + PIN w0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 56.359 25.569 56.413 ; + END + END w0_wmask_in[405] + PIN w0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 56.359 25.857 56.413 ; + END + END w0_wmask_in[406] + PIN w0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 56.359 26.145 56.413 ; + END + END w0_wmask_in[407] + PIN w0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 56.359 26.433 56.413 ; + END + END w0_wmask_in[408] + PIN w0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 56.359 26.721 56.413 ; + END + END w0_wmask_in[409] + PIN w0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 56.359 27.009 56.413 ; + END + END w0_wmask_in[410] + PIN w0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 56.359 27.297 56.413 ; + END + END w0_wmask_in[411] + PIN w0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 56.359 27.585 56.413 ; + END + END w0_wmask_in[412] + PIN w0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 56.359 27.873 56.413 ; + END + END w0_wmask_in[413] + PIN w0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 56.359 28.161 56.413 ; + END + END w0_wmask_in[414] + PIN w0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 56.359 28.449 56.413 ; + END + END w0_wmask_in[415] + PIN w0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 56.359 28.737 56.413 ; + END + END w0_wmask_in[416] + PIN w0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 56.359 29.025 56.413 ; + END + END w0_wmask_in[417] + PIN w0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 56.359 29.313 56.413 ; + END + END w0_wmask_in[418] + PIN w0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 56.359 29.601 56.413 ; + END + END w0_wmask_in[419] + PIN w0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 56.359 29.889 56.413 ; + END + END w0_wmask_in[420] + PIN w0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 56.359 30.177 56.413 ; + END + END w0_wmask_in[421] + PIN w0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 56.359 30.465 56.413 ; + END + END w0_wmask_in[422] + PIN w0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 56.359 30.753 56.413 ; + END + END w0_wmask_in[423] + PIN w0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 56.359 31.041 56.413 ; + END + END w0_wmask_in[424] + PIN w0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 56.359 31.329 56.413 ; + END + END w0_wmask_in[425] + PIN w0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 56.359 31.617 56.413 ; + END + END w0_wmask_in[426] + PIN w0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 56.359 31.905 56.413 ; + END + END w0_wmask_in[427] + PIN w0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 56.359 32.193 56.413 ; + END + END w0_wmask_in[428] + PIN w0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 56.359 32.481 56.413 ; + END + END w0_wmask_in[429] + PIN w0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 56.359 32.769 56.413 ; + END + END w0_wmask_in[430] + PIN w0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 56.359 33.057 56.413 ; + END + END w0_wmask_in[431] + PIN w0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 56.359 33.345 56.413 ; + END + END w0_wmask_in[432] + PIN w0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 56.359 33.633 56.413 ; + END + END w0_wmask_in[433] + PIN w0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 56.359 33.921 56.413 ; + END + END w0_wmask_in[434] + PIN w0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 56.359 34.209 56.413 ; + END + END w0_wmask_in[435] + PIN w0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 56.359 34.497 56.413 ; + END + END w0_wmask_in[436] + PIN w0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 56.359 34.785 56.413 ; + END + END w0_wmask_in[437] + PIN w0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 56.359 35.073 56.413 ; + END + END w0_wmask_in[438] + PIN w0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 56.359 35.361 56.413 ; + END + END w0_wmask_in[439] + PIN w0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 56.359 35.649 56.413 ; + END + END w0_wmask_in[440] + PIN w0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 56.359 35.937 56.413 ; + END + END w0_wmask_in[441] + PIN w0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 56.359 36.225 56.413 ; + END + END w0_wmask_in[442] + PIN w0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 56.359 36.513 56.413 ; + END + END w0_wmask_in[443] + PIN w0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 56.359 36.801 56.413 ; + END + END w0_wmask_in[444] + PIN w0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 56.359 37.089 56.413 ; + END + END w0_wmask_in[445] + PIN w0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 56.359 37.377 56.413 ; + END + END w0_wmask_in[446] + PIN w0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 56.359 37.665 56.413 ; + END + END w0_wmask_in[447] + PIN w0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 56.359 37.953 56.413 ; + END + END w0_wmask_in[448] + PIN w0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 56.359 38.241 56.413 ; + END + END w0_wmask_in[449] + PIN w0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 56.359 38.529 56.413 ; + END + END w0_wmask_in[450] + PIN w0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 56.359 38.817 56.413 ; + END + END w0_wmask_in[451] + PIN w0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 56.359 39.105 56.413 ; + END + END w0_wmask_in[452] + PIN w0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 56.359 39.393 56.413 ; + END + END w0_wmask_in[453] + PIN w0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 56.359 39.681 56.413 ; + END + END w0_wmask_in[454] + PIN w0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 56.359 39.969 56.413 ; + END + END w0_wmask_in[455] + PIN w0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 56.359 40.257 56.413 ; + END + END w0_wmask_in[456] + PIN w0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 56.359 40.545 56.413 ; + END + END w0_wmask_in[457] + PIN w0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 56.359 40.833 56.413 ; + END + END w0_wmask_in[458] + PIN w0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 56.359 41.121 56.413 ; + END + END w0_wmask_in[459] + PIN w0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 56.359 41.409 56.413 ; + END + END w0_wmask_in[460] + PIN w0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 56.359 41.697 56.413 ; + END + END w0_wmask_in[461] + PIN w0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 56.359 41.985 56.413 ; + END + END w0_wmask_in[462] + PIN w0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 56.359 42.273 56.413 ; + END + END w0_wmask_in[463] + PIN w0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 56.359 42.561 56.413 ; + END + END w0_wmask_in[464] + PIN w0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 56.359 42.849 56.413 ; + END + END w0_wmask_in[465] + PIN w0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 56.359 43.137 56.413 ; + END + END w0_wmask_in[466] + PIN w0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 56.359 43.425 56.413 ; + END + END w0_wmask_in[467] + PIN w0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 56.359 43.713 56.413 ; + END + END w0_wmask_in[468] + PIN w0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 56.359 44.001 56.413 ; + END + END w0_wmask_in[469] + PIN w0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 56.359 44.289 56.413 ; + END + END w0_wmask_in[470] + PIN w0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 56.359 44.577 56.413 ; + END + END w0_wmask_in[471] + PIN w0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 56.359 44.865 56.413 ; + END + END w0_wmask_in[472] + PIN w0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 56.359 45.153 56.413 ; + END + END w0_wmask_in[473] + PIN w0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 56.359 45.441 56.413 ; + END + END w0_wmask_in[474] + PIN w0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 56.359 45.729 56.413 ; + END + END w0_wmask_in[475] + PIN w0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 56.359 46.017 56.413 ; + END + END w0_wmask_in[476] + PIN w0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 56.359 46.305 56.413 ; + END + END w0_wmask_in[477] + PIN w0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 56.359 46.593 56.413 ; + END + END w0_wmask_in[478] + PIN w0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 56.359 46.881 56.413 ; + END + END w0_wmask_in[479] + PIN w0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 56.359 47.169 56.413 ; + END + END w0_wmask_in[480] + PIN w0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 56.359 47.457 56.413 ; + END + END w0_wmask_in[481] + PIN w0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 56.359 47.745 56.413 ; + END + END w0_wmask_in[482] + PIN w0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 56.359 48.033 56.413 ; + END + END w0_wmask_in[483] + PIN w0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 56.359 48.321 56.413 ; + END + END w0_wmask_in[484] + PIN w0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 56.359 48.609 56.413 ; + END + END w0_wmask_in[485] + PIN w0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 56.359 48.897 56.413 ; + END + END w0_wmask_in[486] + PIN w0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 56.359 49.185 56.413 ; + END + END w0_wmask_in[487] + PIN w0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 56.359 49.473 56.413 ; + END + END w0_wmask_in[488] + PIN w0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 56.359 49.761 56.413 ; + END + END w0_wmask_in[489] + PIN w0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 56.359 50.049 56.413 ; + END + END w0_wmask_in[490] + PIN w0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 56.359 50.337 56.413 ; + END + END w0_wmask_in[491] + PIN w0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 56.359 50.625 56.413 ; + END + END w0_wmask_in[492] + PIN w0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 56.359 50.913 56.413 ; + END + END w0_wmask_in[493] + PIN w0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 56.359 51.201 56.413 ; + END + END w0_wmask_in[494] + PIN w0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 56.359 51.489 56.413 ; + END + END w0_wmask_in[495] + PIN w0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 56.359 51.777 56.413 ; + END + END w0_wmask_in[496] + PIN w0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 56.359 52.065 56.413 ; + END + END w0_wmask_in[497] + PIN w0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 56.359 52.353 56.413 ; + END + END w0_wmask_in[498] + PIN w0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 56.359 52.641 56.413 ; + END + END w0_wmask_in[499] + PIN w0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 56.359 52.929 56.413 ; + END + END w0_wmask_in[500] + PIN w0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 56.359 53.217 56.413 ; + END + END w0_wmask_in[501] + PIN w0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 56.359 53.505 56.413 ; + END + END w0_wmask_in[502] + PIN w0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 56.359 53.793 56.413 ; + END + END w0_wmask_in[503] + PIN w0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 56.359 54.081 56.413 ; + END + END w0_wmask_in[504] + PIN w0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 56.359 54.369 56.413 ; + END + END w0_wmask_in[505] + PIN w0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 56.359 54.657 56.413 ; + END + END w0_wmask_in[506] + PIN w0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 56.359 54.945 56.413 ; + END + END w0_wmask_in[507] + PIN w0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 56.359 55.233 56.413 ; + END + END w0_wmask_in[508] + PIN w0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 56.359 55.521 56.413 ; + END + END w0_wmask_in[509] + PIN w0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 56.359 55.809 56.413 ; + END + END w0_wmask_in[510] + PIN w0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 56.359 56.097 56.413 ; + END + END w0_wmask_in[511] + PIN w0_wmask_in[512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 56.359 56.385 56.413 ; + END + END w0_wmask_in[512] + PIN w0_wmask_in[513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 56.359 56.673 56.413 ; + END + END w0_wmask_in[513] + PIN w0_wmask_in[514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 56.359 56.961 56.413 ; + END + END w0_wmask_in[514] + PIN w0_wmask_in[515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 56.359 57.249 56.413 ; + END + END w0_wmask_in[515] + PIN w0_wmask_in[516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 56.359 57.537 56.413 ; + END + END w0_wmask_in[516] + PIN w0_wmask_in[517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 56.359 57.825 56.413 ; + END + END w0_wmask_in[517] + PIN w0_wmask_in[518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 56.359 58.113 56.413 ; + END + END w0_wmask_in[518] + PIN w0_wmask_in[519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 56.359 58.401 56.413 ; + END + END w0_wmask_in[519] + PIN w0_wmask_in[520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 56.359 58.689 56.413 ; + END + END w0_wmask_in[520] + PIN w0_wmask_in[521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 56.359 58.977 56.413 ; + END + END w0_wmask_in[521] + PIN w0_wmask_in[522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 56.359 59.265 56.413 ; + END + END w0_wmask_in[522] + PIN w0_wmask_in[523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 56.359 59.553 56.413 ; + END + END w0_wmask_in[523] + PIN w0_wmask_in[524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 56.359 59.841 56.413 ; + END + END w0_wmask_in[524] + PIN w0_wmask_in[525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 56.359 60.129 56.413 ; + END + END w0_wmask_in[525] + PIN w0_wmask_in[526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 56.359 60.417 56.413 ; + END + END w0_wmask_in[526] + PIN w0_wmask_in[527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 56.359 60.705 56.413 ; + END + END w0_wmask_in[527] + PIN w0_wmask_in[528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 56.359 60.993 56.413 ; + END + END w0_wmask_in[528] + PIN w0_wmask_in[529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 56.359 61.281 56.413 ; + END + END w0_wmask_in[529] + PIN w0_wmask_in[530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 56.359 61.569 56.413 ; + END + END w0_wmask_in[530] + PIN w0_wmask_in[531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 56.359 61.857 56.413 ; + END + END w0_wmask_in[531] + PIN w0_wmask_in[532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 56.359 62.145 56.413 ; + END + END w0_wmask_in[532] + PIN w0_wmask_in[533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 56.359 62.433 56.413 ; + END + END w0_wmask_in[533] + PIN w0_wmask_in[534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 56.359 62.721 56.413 ; + END + END w0_wmask_in[534] + PIN w0_wmask_in[535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 56.359 63.009 56.413 ; + END + END w0_wmask_in[535] + PIN w0_wmask_in[536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 56.359 63.297 56.413 ; + END + END w0_wmask_in[536] + PIN w0_wmask_in[537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 56.359 63.585 56.413 ; + END + END w0_wmask_in[537] + PIN w0_wmask_in[538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 56.359 63.873 56.413 ; + END + END w0_wmask_in[538] + PIN w0_wmask_in[539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 56.359 64.161 56.413 ; + END + END w0_wmask_in[539] + PIN w0_wmask_in[540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 56.359 64.449 56.413 ; + END + END w0_wmask_in[540] + PIN w0_wmask_in[541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 56.359 64.737 56.413 ; + END + END w0_wmask_in[541] + PIN w0_wmask_in[542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 56.359 65.025 56.413 ; + END + END w0_wmask_in[542] + PIN w0_wmask_in[543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 56.359 65.313 56.413 ; + END + END w0_wmask_in[543] + PIN w0_wmask_in[544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 56.359 65.601 56.413 ; + END + END w0_wmask_in[544] + PIN w0_wmask_in[545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 56.359 65.889 56.413 ; + END + END w0_wmask_in[545] + PIN w0_wmask_in[546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 56.359 66.177 56.413 ; + END + END w0_wmask_in[546] + PIN w0_wmask_in[547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 56.359 66.465 56.413 ; + END + END w0_wmask_in[547] + PIN w0_wmask_in[548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 56.359 66.753 56.413 ; + END + END w0_wmask_in[548] + PIN w0_wmask_in[549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 56.359 67.041 56.413 ; + END + END w0_wmask_in[549] + PIN w0_wmask_in[550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 56.359 67.329 56.413 ; + END + END w0_wmask_in[550] + PIN w0_wmask_in[551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 56.359 67.617 56.413 ; + END + END w0_wmask_in[551] + PIN w0_wmask_in[552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 56.359 67.905 56.413 ; + END + END w0_wmask_in[552] + PIN w0_wmask_in[553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 56.359 68.193 56.413 ; + END + END w0_wmask_in[553] + PIN w0_wmask_in[554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 56.359 68.481 56.413 ; + END + END w0_wmask_in[554] + PIN w0_wmask_in[555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 56.359 68.769 56.413 ; + END + END w0_wmask_in[555] + PIN w0_wmask_in[556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 56.359 69.057 56.413 ; + END + END w0_wmask_in[556] + PIN w0_wmask_in[557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 56.359 69.345 56.413 ; + END + END w0_wmask_in[557] + PIN w0_wmask_in[558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 56.359 69.633 56.413 ; + END + END w0_wmask_in[558] + PIN w0_wmask_in[559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 56.359 69.921 56.413 ; + END + END w0_wmask_in[559] + PIN w0_wmask_in[560] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 56.359 70.209 56.413 ; + END + END w0_wmask_in[560] + PIN w0_wmask_in[561] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 56.359 70.497 56.413 ; + END + END w0_wmask_in[561] + PIN w0_wmask_in[562] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 56.359 70.785 56.413 ; + END + END w0_wmask_in[562] + PIN w0_wmask_in[563] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 56.359 71.073 56.413 ; + END + END w0_wmask_in[563] + PIN w0_wmask_in[564] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 56.359 71.361 56.413 ; + END + END w0_wmask_in[564] + PIN w0_wmask_in[565] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 56.359 71.649 56.413 ; + END + END w0_wmask_in[565] + PIN w0_wmask_in[566] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 56.359 71.937 56.413 ; + END + END w0_wmask_in[566] + PIN w0_wmask_in[567] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 56.359 72.225 56.413 ; + END + END w0_wmask_in[567] + PIN w0_wmask_in[568] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 56.359 72.513 56.413 ; + END + END w0_wmask_in[568] + PIN w0_wmask_in[569] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 56.359 72.801 56.413 ; + END + END w0_wmask_in[569] + PIN w0_wmask_in[570] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 56.359 73.089 56.413 ; + END + END w0_wmask_in[570] + PIN w0_wmask_in[571] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 56.359 73.377 56.413 ; + END + END w0_wmask_in[571] + PIN w0_wmask_in[572] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 56.359 73.665 56.413 ; + END + END w0_wmask_in[572] + PIN w0_wmask_in[573] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 56.359 73.953 56.413 ; + END + END w0_wmask_in[573] + PIN w0_wmask_in[574] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 56.359 74.241 56.413 ; + END + END w0_wmask_in[574] + PIN w0_wmask_in[575] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 56.359 74.529 56.413 ; + END + END w0_wmask_in[575] + PIN w0_wmask_in[576] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 56.359 74.817 56.413 ; + END + END w0_wmask_in[576] + PIN w0_wmask_in[577] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 56.359 75.105 56.413 ; + END + END w0_wmask_in[577] + PIN w0_wmask_in[578] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 56.359 75.393 56.413 ; + END + END w0_wmask_in[578] + PIN w0_wmask_in[579] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 56.359 75.681 56.413 ; + END + END w0_wmask_in[579] + PIN w0_wmask_in[580] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 56.359 75.969 56.413 ; + END + END w0_wmask_in[580] + PIN w0_wmask_in[581] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 56.359 76.257 56.413 ; + END + END w0_wmask_in[581] + PIN w0_wmask_in[582] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 56.359 76.545 56.413 ; + END + END w0_wmask_in[582] + PIN w0_wmask_in[583] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 56.359 76.833 56.413 ; + END + END w0_wmask_in[583] + PIN w0_wmask_in[584] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 56.359 77.121 56.413 ; + END + END w0_wmask_in[584] + PIN w0_wmask_in[585] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 56.359 77.409 56.413 ; + END + END w0_wmask_in[585] + PIN w0_wmask_in[586] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 56.359 77.697 56.413 ; + END + END w0_wmask_in[586] + PIN w0_wmask_in[587] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 56.359 77.985 56.413 ; + END + END w0_wmask_in[587] + PIN w0_wmask_in[588] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 56.359 78.273 56.413 ; + END + END w0_wmask_in[588] + PIN w0_wmask_in[589] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 56.359 78.561 56.413 ; + END + END w0_wmask_in[589] + PIN w0_wmask_in[590] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 56.359 78.849 56.413 ; + END + END w0_wmask_in[590] + PIN w0_wmask_in[591] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 56.359 79.137 56.413 ; + END + END w0_wmask_in[591] + PIN w0_wmask_in[592] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 56.359 79.425 56.413 ; + END + END w0_wmask_in[592] + PIN w0_wmask_in[593] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 56.359 79.713 56.413 ; + END + END w0_wmask_in[593] + PIN w0_wmask_in[594] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 56.359 80.001 56.413 ; + END + END w0_wmask_in[594] + PIN w0_wmask_in[595] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 56.359 80.289 56.413 ; + END + END w0_wmask_in[595] + PIN w0_wmask_in[596] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 56.359 80.577 56.413 ; + END + END w0_wmask_in[596] + PIN w0_wmask_in[597] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 56.359 80.865 56.413 ; + END + END w0_wmask_in[597] + PIN w0_wmask_in[598] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 56.359 81.153 56.413 ; + END + END w0_wmask_in[598] + PIN w0_wmask_in[599] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 56.359 81.441 56.413 ; + END + END w0_wmask_in[599] + PIN w0_wmask_in[600] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 56.359 81.729 56.413 ; + END + END w0_wmask_in[600] + PIN w0_wmask_in[601] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 56.359 82.017 56.413 ; + END + END w0_wmask_in[601] + PIN w0_wmask_in[602] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 56.359 82.305 56.413 ; + END + END w0_wmask_in[602] + PIN w0_wmask_in[603] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 56.359 82.593 56.413 ; + END + END w0_wmask_in[603] + PIN w0_wmask_in[604] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 56.359 82.881 56.413 ; + END + END w0_wmask_in[604] + PIN w0_wmask_in[605] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 56.359 83.169 56.413 ; + END + END w0_wmask_in[605] + PIN w0_wmask_in[606] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 56.359 83.457 56.413 ; + END + END w0_wmask_in[606] + PIN w0_wmask_in[607] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 56.359 83.745 56.413 ; + END + END w0_wmask_in[607] + PIN w0_wmask_in[608] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 56.359 84.033 56.413 ; + END + END w0_wmask_in[608] + PIN w0_wmask_in[609] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 56.359 84.321 56.413 ; + END + END w0_wmask_in[609] + PIN w0_wmask_in[610] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 56.359 84.609 56.413 ; + END + END w0_wmask_in[610] + PIN w0_wmask_in[611] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 56.359 84.897 56.413 ; + END + END w0_wmask_in[611] + PIN w0_wmask_in[612] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 56.359 85.185 56.413 ; + END + END w0_wmask_in[612] + PIN w0_wmask_in[613] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 56.359 85.473 56.413 ; + END + END w0_wmask_in[613] + PIN w0_wmask_in[614] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 56.359 85.761 56.413 ; + END + END w0_wmask_in[614] + PIN w0_wmask_in[615] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 56.359 86.049 56.413 ; + END + END w0_wmask_in[615] + PIN w0_wmask_in[616] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 56.359 86.337 56.413 ; + END + END w0_wmask_in[616] + PIN w0_wmask_in[617] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 56.359 86.625 56.413 ; + END + END w0_wmask_in[617] + PIN w0_wmask_in[618] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 56.359 86.913 56.413 ; + END + END w0_wmask_in[618] + PIN w0_wmask_in[619] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 56.359 87.201 56.413 ; + END + END w0_wmask_in[619] + PIN w0_wmask_in[620] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 56.359 87.489 56.413 ; + END + END w0_wmask_in[620] + PIN w0_wmask_in[621] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 56.359 87.777 56.413 ; + END + END w0_wmask_in[621] + PIN w0_wmask_in[622] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 56.359 88.065 56.413 ; + END + END w0_wmask_in[622] + PIN w0_wmask_in[623] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 56.359 88.353 56.413 ; + END + END w0_wmask_in[623] + PIN w0_wmask_in[624] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 56.359 88.641 56.413 ; + END + END w0_wmask_in[624] + PIN w0_wmask_in[625] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 56.359 88.929 56.413 ; + END + END w0_wmask_in[625] + PIN w0_wmask_in[626] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 56.359 89.217 56.413 ; + END + END w0_wmask_in[626] + PIN w0_wmask_in[627] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 56.359 89.505 56.413 ; + END + END w0_wmask_in[627] + PIN w0_wmask_in[628] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 56.359 89.793 56.413 ; + END + END w0_wmask_in[628] + PIN w0_wmask_in[629] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 56.359 90.081 56.413 ; + END + END w0_wmask_in[629] + PIN w0_wmask_in[630] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 56.359 90.369 56.413 ; + END + END w0_wmask_in[630] + PIN w0_wmask_in[631] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 56.359 90.657 56.413 ; + END + END w0_wmask_in[631] + PIN w0_wmask_in[632] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 56.359 90.945 56.413 ; + END + END w0_wmask_in[632] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.748 0.072 23.772 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.324 0.072 24.348 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.612 0.072 24.636 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.188 0.072 25.212 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.052 0.072 26.076 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.340 0.072 26.364 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.916 0.072 26.940 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.204 0.072 27.228 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.780 0.072 27.804 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.068 0.072 28.092 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.212 0.072 28.236 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.644 0.072 28.668 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.932 0.072 28.956 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.508 0.072 29.532 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.796 0.072 29.820 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.940 0.072 29.964 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.372 0.072 30.396 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.660 0.072 30.684 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.092 0.072 31.116 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.236 0.072 31.260 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.668 0.072 31.692 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.100 0.072 32.124 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.388 0.072 32.412 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.820 0.072 32.844 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.964 0.072 32.988 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.252 0.072 33.276 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.828 0.072 33.852 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.116 0.072 34.140 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.404 0.072 34.428 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.692 0.072 34.716 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.980 0.072 35.004 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.124 0.072 35.148 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.268 0.072 35.292 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.556 0.072 35.580 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.844 0.072 35.868 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.132 0.072 36.156 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.420 0.072 36.444 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.708 0.072 36.732 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.852 0.072 36.876 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.996 0.072 37.020 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.284 0.072 37.308 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.860 0.072 37.884 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.004 0.072 38.028 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.148 0.072 38.172 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.436 0.072 38.460 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.724 0.072 38.748 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.868 0.072 38.892 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.012 0.072 39.036 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.300 0.072 39.324 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.588 0.072 39.612 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.732 0.072 39.756 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.876 0.072 39.900 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.164 0.072 40.188 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.308 0.072 40.332 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.452 0.072 40.476 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.740 0.072 40.764 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.884 0.072 40.908 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.028 0.072 41.052 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.172 0.072 41.196 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.316 0.072 41.340 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.460 0.072 41.484 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.604 0.072 41.628 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.748 0.072 41.772 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.892 0.072 41.916 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.036 0.072 42.060 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.180 0.072 42.204 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.324 0.072 42.348 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.468 0.072 42.492 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.612 0.072 42.636 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.756 0.072 42.780 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.900 0.072 42.924 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.044 0.072 43.068 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.188 0.072 43.212 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.332 0.072 43.356 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.476 0.072 43.500 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.620 0.072 43.644 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.764 0.072 43.788 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.908 0.072 43.932 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.052 0.072 44.076 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.196 0.072 44.220 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.340 0.072 44.364 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.484 0.072 44.508 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.628 0.072 44.652 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.772 0.072 44.796 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.916 0.072 44.940 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.060 0.072 45.084 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.204 0.072 45.228 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.348 0.072 45.372 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.492 0.072 45.516 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.636 0.072 45.660 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.780 0.072 45.804 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.924 0.072 45.948 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.028 201.811 23.052 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.172 201.811 23.196 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.316 201.811 23.340 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.460 201.811 23.484 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.604 201.811 23.628 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.748 201.811 23.772 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 23.892 201.811 23.916 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.036 201.811 24.060 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.180 201.811 24.204 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.324 201.811 24.348 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.468 201.811 24.492 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.612 201.811 24.636 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.756 201.811 24.780 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 24.900 201.811 24.924 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.044 201.811 25.068 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.188 201.811 25.212 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.332 201.811 25.356 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.476 201.811 25.500 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.620 201.811 25.644 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.764 201.811 25.788 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 25.908 201.811 25.932 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.052 201.811 26.076 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.196 201.811 26.220 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.340 201.811 26.364 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.484 201.811 26.508 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.628 201.811 26.652 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.772 201.811 26.796 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 26.916 201.811 26.940 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.060 201.811 27.084 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.204 201.811 27.228 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.348 201.811 27.372 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.492 201.811 27.516 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.636 201.811 27.660 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.780 201.811 27.804 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 27.924 201.811 27.948 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.068 201.811 28.092 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.212 201.811 28.236 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.356 201.811 28.380 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.500 201.811 28.524 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.644 201.811 28.668 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.788 201.811 28.812 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 28.932 201.811 28.956 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.076 201.811 29.100 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.220 201.811 29.244 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.364 201.811 29.388 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.508 201.811 29.532 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.652 201.811 29.676 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.796 201.811 29.820 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 29.940 201.811 29.964 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.084 201.811 30.108 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.228 201.811 30.252 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.372 201.811 30.396 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.516 201.811 30.540 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.660 201.811 30.684 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.804 201.811 30.828 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 30.948 201.811 30.972 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.092 201.811 31.116 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.236 201.811 31.260 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.380 201.811 31.404 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.524 201.811 31.548 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.668 201.811 31.692 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.812 201.811 31.836 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 31.956 201.811 31.980 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.100 201.811 32.124 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.244 201.811 32.268 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.388 201.811 32.412 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.532 201.811 32.556 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.676 201.811 32.700 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.820 201.811 32.844 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 32.964 201.811 32.988 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.108 201.811 33.132 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.252 201.811 33.276 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.396 201.811 33.420 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.540 201.811 33.564 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.684 201.811 33.708 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.828 201.811 33.852 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 33.972 201.811 33.996 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.116 201.811 34.140 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.260 201.811 34.284 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.404 201.811 34.428 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.548 201.811 34.572 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.692 201.811 34.716 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.836 201.811 34.860 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 34.980 201.811 35.004 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.124 201.811 35.148 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.268 201.811 35.292 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.412 201.811 35.436 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.556 201.811 35.580 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.700 201.811 35.724 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.844 201.811 35.868 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 35.988 201.811 36.012 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.132 201.811 36.156 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.276 201.811 36.300 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.420 201.811 36.444 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.564 201.811 36.588 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.708 201.811 36.732 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.852 201.811 36.876 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 36.996 201.811 37.020 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 37.140 201.811 37.164 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 37.284 201.811 37.308 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 37.428 201.811 37.452 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 37.572 201.811 37.596 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 37.716 201.811 37.740 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 37.860 201.811 37.884 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.004 201.811 38.028 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.148 201.811 38.172 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.292 201.811 38.316 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.436 201.811 38.460 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.580 201.811 38.604 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.724 201.811 38.748 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 38.868 201.811 38.892 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.012 201.811 39.036 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.156 201.811 39.180 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.300 201.811 39.324 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.444 201.811 39.468 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.588 201.811 39.612 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.732 201.811 39.756 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 39.876 201.811 39.900 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.020 201.811 40.044 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.164 201.811 40.188 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.308 201.811 40.332 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.452 201.811 40.476 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.596 201.811 40.620 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.740 201.811 40.764 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 40.884 201.811 40.908 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.028 201.811 41.052 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.172 201.811 41.196 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.316 201.811 41.340 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.460 201.811 41.484 ; + END + END w0_wd_in[287] + PIN w0_wd_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.604 201.811 41.628 ; + END + END w0_wd_in[288] + PIN w0_wd_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.748 201.811 41.772 ; + END + END w0_wd_in[289] + PIN w0_wd_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 41.892 201.811 41.916 ; + END + END w0_wd_in[290] + PIN w0_wd_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.036 201.811 42.060 ; + END + END w0_wd_in[291] + PIN w0_wd_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.180 201.811 42.204 ; + END + END w0_wd_in[292] + PIN w0_wd_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.324 201.811 42.348 ; + END + END w0_wd_in[293] + PIN w0_wd_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.468 201.811 42.492 ; + END + END w0_wd_in[294] + PIN w0_wd_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.612 201.811 42.636 ; + END + END w0_wd_in[295] + PIN w0_wd_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.756 201.811 42.780 ; + END + END w0_wd_in[296] + PIN w0_wd_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 42.900 201.811 42.924 ; + END + END w0_wd_in[297] + PIN w0_wd_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.044 201.811 43.068 ; + END + END w0_wd_in[298] + PIN w0_wd_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.188 201.811 43.212 ; + END + END w0_wd_in[299] + PIN w0_wd_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.332 201.811 43.356 ; + END + END w0_wd_in[300] + PIN w0_wd_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.476 201.811 43.500 ; + END + END w0_wd_in[301] + PIN w0_wd_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.620 201.811 43.644 ; + END + END w0_wd_in[302] + PIN w0_wd_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.764 201.811 43.788 ; + END + END w0_wd_in[303] + PIN w0_wd_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 43.908 201.811 43.932 ; + END + END w0_wd_in[304] + PIN w0_wd_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.052 201.811 44.076 ; + END + END w0_wd_in[305] + PIN w0_wd_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.196 201.811 44.220 ; + END + END w0_wd_in[306] + PIN w0_wd_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.340 201.811 44.364 ; + END + END w0_wd_in[307] + PIN w0_wd_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.484 201.811 44.508 ; + END + END w0_wd_in[308] + PIN w0_wd_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.628 201.811 44.652 ; + END + END w0_wd_in[309] + PIN w0_wd_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.772 201.811 44.796 ; + END + END w0_wd_in[310] + PIN w0_wd_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 44.916 201.811 44.940 ; + END + END w0_wd_in[311] + PIN w0_wd_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 45.060 201.811 45.084 ; + END + END w0_wd_in[312] + PIN w0_wd_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 45.204 201.811 45.228 ; + END + END w0_wd_in[313] + PIN w0_wd_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 45.348 201.811 45.372 ; + END + END w0_wd_in[314] + PIN w0_wd_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 45.492 201.811 45.516 ; + END + END w0_wd_in[315] + PIN w0_wd_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 201.739 45.636 201.811 45.660 ; + END + END w0_wd_in[316] + PIN w0_wd_in[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[317] + PIN w0_wd_in[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[318] + PIN w0_wd_in[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[319] + PIN w0_wd_in[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[320] + PIN w0_wd_in[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[321] + PIN w0_wd_in[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[322] + PIN w0_wd_in[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[323] + PIN w0_wd_in[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[324] + PIN w0_wd_in[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[325] + PIN w0_wd_in[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[326] + PIN w0_wd_in[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[327] + PIN w0_wd_in[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[328] + PIN w0_wd_in[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[329] + PIN w0_wd_in[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[330] + PIN w0_wd_in[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[331] + PIN w0_wd_in[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[332] + PIN w0_wd_in[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[333] + PIN w0_wd_in[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[334] + PIN w0_wd_in[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[335] + PIN w0_wd_in[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[336] + PIN w0_wd_in[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[337] + PIN w0_wd_in[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[338] + PIN w0_wd_in[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[339] + PIN w0_wd_in[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[340] + PIN w0_wd_in[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[341] + PIN w0_wd_in[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[342] + PIN w0_wd_in[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[343] + PIN w0_wd_in[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[344] + PIN w0_wd_in[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[345] + PIN w0_wd_in[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[346] + PIN w0_wd_in[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[347] + PIN w0_wd_in[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[348] + PIN w0_wd_in[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[349] + PIN w0_wd_in[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[350] + PIN w0_wd_in[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[351] + PIN w0_wd_in[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[352] + PIN w0_wd_in[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[353] + PIN w0_wd_in[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[354] + PIN w0_wd_in[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[355] + PIN w0_wd_in[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[356] + PIN w0_wd_in[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[357] + PIN w0_wd_in[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[358] + PIN w0_wd_in[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[359] + PIN w0_wd_in[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[360] + PIN w0_wd_in[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[361] + PIN w0_wd_in[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[362] + PIN w0_wd_in[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[363] + PIN w0_wd_in[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[364] + PIN w0_wd_in[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[365] + PIN w0_wd_in[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[366] + PIN w0_wd_in[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[367] + PIN w0_wd_in[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[368] + PIN w0_wd_in[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[369] + PIN w0_wd_in[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[370] + PIN w0_wd_in[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[371] + PIN w0_wd_in[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[372] + PIN w0_wd_in[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[373] + PIN w0_wd_in[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[374] + PIN w0_wd_in[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[375] + PIN w0_wd_in[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[376] + PIN w0_wd_in[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[377] + PIN w0_wd_in[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[378] + PIN w0_wd_in[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[379] + PIN w0_wd_in[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[380] + PIN w0_wd_in[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[381] + PIN w0_wd_in[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[382] + PIN w0_wd_in[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[383] + PIN w0_wd_in[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[384] + PIN w0_wd_in[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[385] + PIN w0_wd_in[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[386] + PIN w0_wd_in[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[387] + PIN w0_wd_in[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[388] + PIN w0_wd_in[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[389] + PIN w0_wd_in[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[390] + PIN w0_wd_in[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[391] + PIN w0_wd_in[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[392] + PIN w0_wd_in[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[393] + PIN w0_wd_in[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[394] + PIN w0_wd_in[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[395] + PIN w0_wd_in[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[396] + PIN w0_wd_in[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[397] + PIN w0_wd_in[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[398] + PIN w0_wd_in[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[399] + PIN w0_wd_in[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[400] + PIN w0_wd_in[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[401] + PIN w0_wd_in[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[402] + PIN w0_wd_in[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[403] + PIN w0_wd_in[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[404] + PIN w0_wd_in[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[405] + PIN w0_wd_in[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[406] + PIN w0_wd_in[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[407] + PIN w0_wd_in[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[408] + PIN w0_wd_in[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[409] + PIN w0_wd_in[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[410] + PIN w0_wd_in[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[411] + PIN w0_wd_in[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[412] + PIN w0_wd_in[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[413] + PIN w0_wd_in[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[414] + PIN w0_wd_in[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[415] + PIN w0_wd_in[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[416] + PIN w0_wd_in[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[417] + PIN w0_wd_in[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[418] + PIN w0_wd_in[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[419] + PIN w0_wd_in[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[420] + PIN w0_wd_in[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[421] + PIN w0_wd_in[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[422] + PIN w0_wd_in[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[423] + PIN w0_wd_in[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[424] + PIN w0_wd_in[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[425] + PIN w0_wd_in[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[426] + PIN w0_wd_in[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[427] + PIN w0_wd_in[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[428] + PIN w0_wd_in[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[429] + PIN w0_wd_in[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[430] + PIN w0_wd_in[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[431] + PIN w0_wd_in[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[432] + PIN w0_wd_in[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[433] + PIN w0_wd_in[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[434] + PIN w0_wd_in[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[435] + PIN w0_wd_in[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[436] + PIN w0_wd_in[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[437] + PIN w0_wd_in[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[438] + PIN w0_wd_in[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[439] + PIN w0_wd_in[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[440] + PIN w0_wd_in[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[441] + PIN w0_wd_in[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[442] + PIN w0_wd_in[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[443] + PIN w0_wd_in[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[444] + PIN w0_wd_in[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[445] + PIN w0_wd_in[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[446] + PIN w0_wd_in[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[447] + PIN w0_wd_in[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[448] + PIN w0_wd_in[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[449] + PIN w0_wd_in[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[450] + PIN w0_wd_in[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[451] + PIN w0_wd_in[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[452] + PIN w0_wd_in[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[453] + PIN w0_wd_in[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[454] + PIN w0_wd_in[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[455] + PIN w0_wd_in[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[456] + PIN w0_wd_in[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[457] + PIN w0_wd_in[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[458] + PIN w0_wd_in[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[459] + PIN w0_wd_in[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[460] + PIN w0_wd_in[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END w0_wd_in[461] + PIN w0_wd_in[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END w0_wd_in[462] + PIN w0_wd_in[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END w0_wd_in[463] + PIN w0_wd_in[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END w0_wd_in[464] + PIN w0_wd_in[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END w0_wd_in[465] + PIN w0_wd_in[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END w0_wd_in[466] + PIN w0_wd_in[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END w0_wd_in[467] + PIN w0_wd_in[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END w0_wd_in[468] + PIN w0_wd_in[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END w0_wd_in[469] + PIN w0_wd_in[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END w0_wd_in[470] + PIN w0_wd_in[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END w0_wd_in[471] + PIN w0_wd_in[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END w0_wd_in[472] + PIN w0_wd_in[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END w0_wd_in[473] + PIN w0_wd_in[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END w0_wd_in[474] + PIN w0_wd_in[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END w0_wd_in[475] + PIN w0_wd_in[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END w0_wd_in[476] + PIN w0_wd_in[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END w0_wd_in[477] + PIN w0_wd_in[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END w0_wd_in[478] + PIN w0_wd_in[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END w0_wd_in[479] + PIN w0_wd_in[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END w0_wd_in[480] + PIN w0_wd_in[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END w0_wd_in[481] + PIN w0_wd_in[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END w0_wd_in[482] + PIN w0_wd_in[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END w0_wd_in[483] + PIN w0_wd_in[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END w0_wd_in[484] + PIN w0_wd_in[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END w0_wd_in[485] + PIN w0_wd_in[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END w0_wd_in[486] + PIN w0_wd_in[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END w0_wd_in[487] + PIN w0_wd_in[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END w0_wd_in[488] + PIN w0_wd_in[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END w0_wd_in[489] + PIN w0_wd_in[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END w0_wd_in[490] + PIN w0_wd_in[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END w0_wd_in[491] + PIN w0_wd_in[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END w0_wd_in[492] + PIN w0_wd_in[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END w0_wd_in[493] + PIN w0_wd_in[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END w0_wd_in[494] + PIN w0_wd_in[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END w0_wd_in[495] + PIN w0_wd_in[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END w0_wd_in[496] + PIN w0_wd_in[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END w0_wd_in[497] + PIN w0_wd_in[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END w0_wd_in[498] + PIN w0_wd_in[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END w0_wd_in[499] + PIN w0_wd_in[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END w0_wd_in[500] + PIN w0_wd_in[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END w0_wd_in[501] + PIN w0_wd_in[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END w0_wd_in[502] + PIN w0_wd_in[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END w0_wd_in[503] + PIN w0_wd_in[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END w0_wd_in[504] + PIN w0_wd_in[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END w0_wd_in[505] + PIN w0_wd_in[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END w0_wd_in[506] + PIN w0_wd_in[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END w0_wd_in[507] + PIN w0_wd_in[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END w0_wd_in[508] + PIN w0_wd_in[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END w0_wd_in[509] + PIN w0_wd_in[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END w0_wd_in[510] + PIN w0_wd_in[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END w0_wd_in[511] + PIN w0_wd_in[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END w0_wd_in[512] + PIN w0_wd_in[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END w0_wd_in[513] + PIN w0_wd_in[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END w0_wd_in[514] + PIN w0_wd_in[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END w0_wd_in[515] + PIN w0_wd_in[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END w0_wd_in[516] + PIN w0_wd_in[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END w0_wd_in[517] + PIN w0_wd_in[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END w0_wd_in[518] + PIN w0_wd_in[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END w0_wd_in[519] + PIN w0_wd_in[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END w0_wd_in[520] + PIN w0_wd_in[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END w0_wd_in[521] + PIN w0_wd_in[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END w0_wd_in[522] + PIN w0_wd_in[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END w0_wd_in[523] + PIN w0_wd_in[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END w0_wd_in[524] + PIN w0_wd_in[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END w0_wd_in[525] + PIN w0_wd_in[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END w0_wd_in[526] + PIN w0_wd_in[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END w0_wd_in[527] + PIN w0_wd_in[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END w0_wd_in[528] + PIN w0_wd_in[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END w0_wd_in[529] + PIN w0_wd_in[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END w0_wd_in[530] + PIN w0_wd_in[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END w0_wd_in[531] + PIN w0_wd_in[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END w0_wd_in[532] + PIN w0_wd_in[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END w0_wd_in[533] + PIN w0_wd_in[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END w0_wd_in[534] + PIN w0_wd_in[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END w0_wd_in[535] + PIN w0_wd_in[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END w0_wd_in[536] + PIN w0_wd_in[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END w0_wd_in[537] + PIN w0_wd_in[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END w0_wd_in[538] + PIN w0_wd_in[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END w0_wd_in[539] + PIN w0_wd_in[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END w0_wd_in[540] + PIN w0_wd_in[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END w0_wd_in[541] + PIN w0_wd_in[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END w0_wd_in[542] + PIN w0_wd_in[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END w0_wd_in[543] + PIN w0_wd_in[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END w0_wd_in[544] + PIN w0_wd_in[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END w0_wd_in[545] + PIN w0_wd_in[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END w0_wd_in[546] + PIN w0_wd_in[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END w0_wd_in[547] + PIN w0_wd_in[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END w0_wd_in[548] + PIN w0_wd_in[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END w0_wd_in[549] + PIN w0_wd_in[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END w0_wd_in[550] + PIN w0_wd_in[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END w0_wd_in[551] + PIN w0_wd_in[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END w0_wd_in[552] + PIN w0_wd_in[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END w0_wd_in[553] + PIN w0_wd_in[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END w0_wd_in[554] + PIN w0_wd_in[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END w0_wd_in[555] + PIN w0_wd_in[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END w0_wd_in[556] + PIN w0_wd_in[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END w0_wd_in[557] + PIN w0_wd_in[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END w0_wd_in[558] + PIN w0_wd_in[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END w0_wd_in[559] + PIN w0_wd_in[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END w0_wd_in[560] + PIN w0_wd_in[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END w0_wd_in[561] + PIN w0_wd_in[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END w0_wd_in[562] + PIN w0_wd_in[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END w0_wd_in[563] + PIN w0_wd_in[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END w0_wd_in[564] + PIN w0_wd_in[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END w0_wd_in[565] + PIN w0_wd_in[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END w0_wd_in[566] + PIN w0_wd_in[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END w0_wd_in[567] + PIN w0_wd_in[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END w0_wd_in[568] + PIN w0_wd_in[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END w0_wd_in[569] + PIN w0_wd_in[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END w0_wd_in[570] + PIN w0_wd_in[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END w0_wd_in[571] + PIN w0_wd_in[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END w0_wd_in[572] + PIN w0_wd_in[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END w0_wd_in[573] + PIN w0_wd_in[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END w0_wd_in[574] + PIN w0_wd_in[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END w0_wd_in[575] + PIN w0_wd_in[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END w0_wd_in[576] + PIN w0_wd_in[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END w0_wd_in[577] + PIN w0_wd_in[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END w0_wd_in[578] + PIN w0_wd_in[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END w0_wd_in[579] + PIN w0_wd_in[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END w0_wd_in[580] + PIN w0_wd_in[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END w0_wd_in[581] + PIN w0_wd_in[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END w0_wd_in[582] + PIN w0_wd_in[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END w0_wd_in[583] + PIN w0_wd_in[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END w0_wd_in[584] + PIN w0_wd_in[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END w0_wd_in[585] + PIN w0_wd_in[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END w0_wd_in[586] + PIN w0_wd_in[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END w0_wd_in[587] + PIN w0_wd_in[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END w0_wd_in[588] + PIN w0_wd_in[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END w0_wd_in[589] + PIN w0_wd_in[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END w0_wd_in[590] + PIN w0_wd_in[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END w0_wd_in[591] + PIN w0_wd_in[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END w0_wd_in[592] + PIN w0_wd_in[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END w0_wd_in[593] + PIN w0_wd_in[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END w0_wd_in[594] + PIN w0_wd_in[595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END w0_wd_in[595] + PIN w0_wd_in[596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END w0_wd_in[596] + PIN w0_wd_in[597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END w0_wd_in[597] + PIN w0_wd_in[598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END w0_wd_in[598] + PIN w0_wd_in[599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END w0_wd_in[599] + PIN w0_wd_in[600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END w0_wd_in[600] + PIN w0_wd_in[601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END w0_wd_in[601] + PIN w0_wd_in[602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END w0_wd_in[602] + PIN w0_wd_in[603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END w0_wd_in[603] + PIN w0_wd_in[604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END w0_wd_in[604] + PIN w0_wd_in[605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 0.000 83.169 0.054 ; + END + END w0_wd_in[605] + PIN w0_wd_in[606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 0.000 83.457 0.054 ; + END + END w0_wd_in[606] + PIN w0_wd_in[607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END w0_wd_in[607] + PIN w0_wd_in[608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 0.000 84.033 0.054 ; + END + END w0_wd_in[608] + PIN w0_wd_in[609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 0.000 84.321 0.054 ; + END + END w0_wd_in[609] + PIN w0_wd_in[610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 0.000 84.609 0.054 ; + END + END w0_wd_in[610] + PIN w0_wd_in[611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 0.000 84.897 0.054 ; + END + END w0_wd_in[611] + PIN w0_wd_in[612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END w0_wd_in[612] + PIN w0_wd_in[613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 0.000 85.473 0.054 ; + END + END w0_wd_in[613] + PIN w0_wd_in[614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 0.000 85.761 0.054 ; + END + END w0_wd_in[614] + PIN w0_wd_in[615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 0.000 86.049 0.054 ; + END + END w0_wd_in[615] + PIN w0_wd_in[616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 0.000 86.337 0.054 ; + END + END w0_wd_in[616] + PIN w0_wd_in[617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END w0_wd_in[617] + PIN w0_wd_in[618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 0.000 86.913 0.054 ; + END + END w0_wd_in[618] + PIN w0_wd_in[619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 0.000 87.201 0.054 ; + END + END w0_wd_in[619] + PIN w0_wd_in[620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 0.000 87.489 0.054 ; + END + END w0_wd_in[620] + PIN w0_wd_in[621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 0.000 87.777 0.054 ; + END + END w0_wd_in[621] + PIN w0_wd_in[622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END w0_wd_in[622] + PIN w0_wd_in[623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 0.000 88.353 0.054 ; + END + END w0_wd_in[623] + PIN w0_wd_in[624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 0.000 88.641 0.054 ; + END + END w0_wd_in[624] + PIN w0_wd_in[625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 0.000 88.929 0.054 ; + END + END w0_wd_in[625] + PIN w0_wd_in[626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 0.000 89.217 0.054 ; + END + END w0_wd_in[626] + PIN w0_wd_in[627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END w0_wd_in[627] + PIN w0_wd_in[628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 0.000 89.793 0.054 ; + END + END w0_wd_in[628] + PIN w0_wd_in[629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 0.000 90.081 0.054 ; + END + END w0_wd_in[629] + PIN w0_wd_in[630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 0.000 90.369 0.054 ; + END + END w0_wd_in[630] + PIN w0_wd_in[631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 0.000 90.657 0.054 ; + END + END w0_wd_in[631] + PIN w0_wd_in[632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END w0_wd_in[632] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 0.000 91.233 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 0.000 91.521 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 0.000 91.809 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 0.000 92.097 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 0.000 92.385 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 0.000 92.673 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 0.000 92.961 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 0.000 93.249 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 0.000 93.537 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 0.000 93.825 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 0.000 94.113 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 0.000 94.401 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 0.000 94.689 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 0.000 94.977 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 0.000 95.265 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 0.000 95.553 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 0.000 95.841 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 0.000 96.129 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 0.000 96.417 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 0.000 96.705 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 0.000 96.993 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 0.000 97.281 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 0.000 97.569 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 0.000 97.857 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 0.000 98.145 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 0.000 98.433 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 0.000 98.721 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 0.000 99.009 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 0.000 99.297 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 0.000 99.585 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 0.000 99.873 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 0.000 100.161 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 0.000 100.449 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 0.000 100.737 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 0.000 101.025 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 0.000 101.313 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 0.000 101.601 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 0.000 101.889 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 0.000 102.177 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 0.000 102.465 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 0.000 102.753 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 0.000 103.041 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 0.000 103.329 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 0.000 103.617 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 0.000 103.905 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 0.000 104.193 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 0.000 104.481 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 0.000 104.769 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 0.000 105.057 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 0.000 105.345 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 0.000 105.633 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 0.000 105.921 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 0.000 106.209 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 0.000 106.497 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 0.000 106.785 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 0.000 107.073 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 0.000 107.361 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 0.000 107.649 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 0.000 107.937 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 0.000 108.225 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 0.000 108.513 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 0.000 108.801 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 0.000 109.089 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 0.000 109.377 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 0.000 109.665 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 0.000 109.953 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 0.000 110.241 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 0.000 110.529 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 0.000 110.817 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 0.000 111.105 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 0.000 111.393 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 0.000 111.681 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 0.000 111.969 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 0.000 112.257 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 0.000 112.545 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 0.000 112.833 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 0.000 113.121 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 0.000 113.409 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 0.000 113.697 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 0.000 113.985 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 0.000 114.273 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 0.000 114.561 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 0.000 114.849 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 0.000 115.137 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 0.000 115.425 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 0.000 115.713 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 0.000 116.001 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 0.000 116.289 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 0.000 116.577 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 0.000 116.865 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 0.000 117.153 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 0.000 117.441 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 0.000 117.729 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 0.000 118.017 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 0.000 118.305 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 0.000 118.593 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 0.000 118.881 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 0.000 119.169 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 0.000 119.457 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 0.000 119.745 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 0.000 120.033 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 0.000 120.321 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 0.000 120.609 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 0.000 120.897 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 0.000 121.185 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 0.000 121.473 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 0.000 121.761 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 0.000 122.049 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 0.000 122.337 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 0.000 122.625 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 0.000 122.913 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 0.000 123.201 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 0.000 123.489 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 0.000 123.777 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 0.000 124.065 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 0.000 124.353 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 0.000 124.641 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 0.000 124.929 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 0.000 125.217 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 0.000 125.505 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 0.000 125.793 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 0.000 126.081 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 0.000 126.369 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 0.000 126.657 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 0.000 126.945 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 0.000 127.233 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 0.000 127.521 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 0.000 127.809 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 0.000 128.097 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 0.000 128.385 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 0.000 128.673 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 0.000 128.961 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 0.000 129.249 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 0.000 129.537 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 0.000 129.825 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 0.000 130.113 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 0.000 130.401 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 0.000 130.689 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 0.000 130.977 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 0.000 131.265 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 0.000 131.553 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 0.000 131.841 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 0.000 132.129 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 0.000 132.417 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 0.000 132.705 0.054 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 0.000 132.993 0.054 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 0.000 133.281 0.054 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 0.000 133.569 0.054 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 0.000 133.857 0.054 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 0.000 134.145 0.054 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 0.000 134.433 0.054 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 0.000 134.721 0.054 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 0.000 135.009 0.054 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 0.000 135.297 0.054 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 0.000 135.585 0.054 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 0.000 135.873 0.054 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 0.000 136.161 0.054 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 0.000 136.449 0.054 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 0.000 136.737 0.054 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 0.000 137.025 0.054 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 0.000 137.313 0.054 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 0.000 137.601 0.054 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 0.000 137.889 0.054 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 0.000 138.177 0.054 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 0.000 138.465 0.054 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 0.000 138.753 0.054 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 0.000 139.041 0.054 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 0.000 139.329 0.054 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 0.000 139.617 0.054 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 0.000 139.905 0.054 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 0.000 140.193 0.054 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 0.000 140.481 0.054 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 0.000 140.769 0.054 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 0.000 141.057 0.054 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 0.000 141.345 0.054 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 0.000 141.633 0.054 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 0.000 141.921 0.054 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 0.000 142.209 0.054 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 0.000 142.497 0.054 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 0.000 142.785 0.054 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 0.000 143.073 0.054 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 0.000 143.361 0.054 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 0.000 143.649 0.054 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 0.000 143.937 0.054 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 0.000 144.225 0.054 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 0.000 144.513 0.054 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 0.000 144.801 0.054 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 0.000 145.089 0.054 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 0.000 145.377 0.054 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 0.000 145.665 0.054 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 0.000 145.953 0.054 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 0.000 146.241 0.054 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 0.000 146.529 0.054 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 0.000 146.817 0.054 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 0.000 147.105 0.054 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 0.000 147.393 0.054 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 0.000 147.681 0.054 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 0.000 147.969 0.054 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 0.000 148.257 0.054 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 0.000 148.545 0.054 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 0.000 148.833 0.054 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 0.000 149.121 0.054 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 0.000 149.409 0.054 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 0.000 149.697 0.054 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 0.000 149.985 0.054 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 0.000 150.273 0.054 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 0.000 150.561 0.054 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 0.000 150.849 0.054 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 0.000 151.137 0.054 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 0.000 151.425 0.054 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 0.000 151.713 0.054 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 0.000 152.001 0.054 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 0.000 152.289 0.054 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 0.000 152.577 0.054 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 0.000 152.865 0.054 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 0.000 153.153 0.054 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 0.000 153.441 0.054 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 0.000 153.729 0.054 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 0.000 154.017 0.054 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 0.000 154.305 0.054 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 0.000 154.593 0.054 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 0.000 154.881 0.054 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 0.000 155.169 0.054 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 0.000 155.457 0.054 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 0.000 155.745 0.054 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 0.000 156.033 0.054 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 0.000 156.321 0.054 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 0.000 156.609 0.054 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 0.000 156.897 0.054 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 0.000 157.185 0.054 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 0.000 157.473 0.054 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 0.000 157.761 0.054 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 0.000 158.049 0.054 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 0.000 158.337 0.054 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 0.000 158.625 0.054 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 0.000 158.913 0.054 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 0.000 159.201 0.054 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 0.000 159.489 0.054 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 0.000 159.777 0.054 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 0.000 160.065 0.054 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 0.000 160.353 0.054 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 0.000 160.641 0.054 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 0.000 160.929 0.054 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 0.000 161.217 0.054 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 0.000 161.505 0.054 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 0.000 161.793 0.054 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 0.000 162.081 0.054 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 0.000 162.369 0.054 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 0.000 162.657 0.054 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 0.000 162.945 0.054 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.215 0.000 163.233 0.054 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.503 0.000 163.521 0.054 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.791 0.000 163.809 0.054 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.079 0.000 164.097 0.054 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 0.000 164.385 0.054 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.655 0.000 164.673 0.054 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.943 0.000 164.961 0.054 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.231 0.000 165.249 0.054 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.519 0.000 165.537 0.054 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 0.000 165.825 0.054 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.095 0.000 166.113 0.054 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.383 0.000 166.401 0.054 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.671 0.000 166.689 0.054 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.959 0.000 166.977 0.054 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 0.000 167.265 0.054 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.535 0.000 167.553 0.054 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.823 0.000 167.841 0.054 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.111 0.000 168.129 0.054 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.399 0.000 168.417 0.054 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 0.000 168.705 0.054 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.975 0.000 168.993 0.054 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.263 0.000 169.281 0.054 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.551 0.000 169.569 0.054 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.839 0.000 169.857 0.054 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 0.000 170.145 0.054 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.415 0.000 170.433 0.054 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.703 0.000 170.721 0.054 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.991 0.000 171.009 0.054 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.279 0.000 171.297 0.054 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 0.000 171.585 0.054 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.855 0.000 171.873 0.054 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.143 0.000 172.161 0.054 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.431 0.000 172.449 0.054 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.719 0.000 172.737 0.054 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.007 0.000 173.025 0.054 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.295 0.000 173.313 0.054 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.583 0.000 173.601 0.054 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.871 0.000 173.889 0.054 ; + END + END r0_rd_out[287] + PIN r0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.159 0.000 174.177 0.054 ; + END + END r0_rd_out[288] + PIN r0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.447 0.000 174.465 0.054 ; + END + END r0_rd_out[289] + PIN r0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.735 0.000 174.753 0.054 ; + END + END r0_rd_out[290] + PIN r0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.023 0.000 175.041 0.054 ; + END + END r0_rd_out[291] + PIN r0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.311 0.000 175.329 0.054 ; + END + END r0_rd_out[292] + PIN r0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.599 0.000 175.617 0.054 ; + END + END r0_rd_out[293] + PIN r0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.887 0.000 175.905 0.054 ; + END + END r0_rd_out[294] + PIN r0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.175 0.000 176.193 0.054 ; + END + END r0_rd_out[295] + PIN r0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.463 0.000 176.481 0.054 ; + END + END r0_rd_out[296] + PIN r0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.751 0.000 176.769 0.054 ; + END + END r0_rd_out[297] + PIN r0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.039 0.000 177.057 0.054 ; + END + END r0_rd_out[298] + PIN r0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.327 0.000 177.345 0.054 ; + END + END r0_rd_out[299] + PIN r0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.615 0.000 177.633 0.054 ; + END + END r0_rd_out[300] + PIN r0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.903 0.000 177.921 0.054 ; + END + END r0_rd_out[301] + PIN r0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.191 0.000 178.209 0.054 ; + END + END r0_rd_out[302] + PIN r0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.479 0.000 178.497 0.054 ; + END + END r0_rd_out[303] + PIN r0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.767 0.000 178.785 0.054 ; + END + END r0_rd_out[304] + PIN r0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.055 0.000 179.073 0.054 ; + END + END r0_rd_out[305] + PIN r0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.343 0.000 179.361 0.054 ; + END + END r0_rd_out[306] + PIN r0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.631 0.000 179.649 0.054 ; + END + END r0_rd_out[307] + PIN r0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.919 0.000 179.937 0.054 ; + END + END r0_rd_out[308] + PIN r0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.207 0.000 180.225 0.054 ; + END + END r0_rd_out[309] + PIN r0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.495 0.000 180.513 0.054 ; + END + END r0_rd_out[310] + PIN r0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.783 0.000 180.801 0.054 ; + END + END r0_rd_out[311] + PIN r0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.071 0.000 181.089 0.054 ; + END + END r0_rd_out[312] + PIN r0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.359 0.000 181.377 0.054 ; + END + END r0_rd_out[313] + PIN r0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.647 0.000 181.665 0.054 ; + END + END r0_rd_out[314] + PIN r0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.935 0.000 181.953 0.054 ; + END + END r0_rd_out[315] + PIN r0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.223 0.000 182.241 0.054 ; + END + END r0_rd_out[316] + PIN r0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 56.359 91.233 56.413 ; + END + END r0_rd_out[317] + PIN r0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 56.359 91.521 56.413 ; + END + END r0_rd_out[318] + PIN r0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 56.359 91.809 56.413 ; + END + END r0_rd_out[319] + PIN r0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 56.359 92.097 56.413 ; + END + END r0_rd_out[320] + PIN r0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 56.359 92.385 56.413 ; + END + END r0_rd_out[321] + PIN r0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 56.359 92.673 56.413 ; + END + END r0_rd_out[322] + PIN r0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 56.359 92.961 56.413 ; + END + END r0_rd_out[323] + PIN r0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 56.359 93.249 56.413 ; + END + END r0_rd_out[324] + PIN r0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 56.359 93.537 56.413 ; + END + END r0_rd_out[325] + PIN r0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 56.359 93.825 56.413 ; + END + END r0_rd_out[326] + PIN r0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 56.359 94.113 56.413 ; + END + END r0_rd_out[327] + PIN r0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 56.359 94.401 56.413 ; + END + END r0_rd_out[328] + PIN r0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 56.359 94.689 56.413 ; + END + END r0_rd_out[329] + PIN r0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 56.359 94.977 56.413 ; + END + END r0_rd_out[330] + PIN r0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 56.359 95.265 56.413 ; + END + END r0_rd_out[331] + PIN r0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 56.359 95.553 56.413 ; + END + END r0_rd_out[332] + PIN r0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 56.359 95.841 56.413 ; + END + END r0_rd_out[333] + PIN r0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 56.359 96.129 56.413 ; + END + END r0_rd_out[334] + PIN r0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 56.359 96.417 56.413 ; + END + END r0_rd_out[335] + PIN r0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 56.359 96.705 56.413 ; + END + END r0_rd_out[336] + PIN r0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 56.359 96.993 56.413 ; + END + END r0_rd_out[337] + PIN r0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 56.359 97.281 56.413 ; + END + END r0_rd_out[338] + PIN r0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 56.359 97.569 56.413 ; + END + END r0_rd_out[339] + PIN r0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 56.359 97.857 56.413 ; + END + END r0_rd_out[340] + PIN r0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 56.359 98.145 56.413 ; + END + END r0_rd_out[341] + PIN r0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 56.359 98.433 56.413 ; + END + END r0_rd_out[342] + PIN r0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 56.359 98.721 56.413 ; + END + END r0_rd_out[343] + PIN r0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 56.359 99.009 56.413 ; + END + END r0_rd_out[344] + PIN r0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 56.359 99.297 56.413 ; + END + END r0_rd_out[345] + PIN r0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 56.359 99.585 56.413 ; + END + END r0_rd_out[346] + PIN r0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 56.359 99.873 56.413 ; + END + END r0_rd_out[347] + PIN r0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 56.359 100.161 56.413 ; + END + END r0_rd_out[348] + PIN r0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 56.359 100.449 56.413 ; + END + END r0_rd_out[349] + PIN r0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 56.359 100.737 56.413 ; + END + END r0_rd_out[350] + PIN r0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 56.359 101.025 56.413 ; + END + END r0_rd_out[351] + PIN r0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 56.359 101.313 56.413 ; + END + END r0_rd_out[352] + PIN r0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 56.359 101.601 56.413 ; + END + END r0_rd_out[353] + PIN r0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 56.359 101.889 56.413 ; + END + END r0_rd_out[354] + PIN r0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 56.359 102.177 56.413 ; + END + END r0_rd_out[355] + PIN r0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 56.359 102.465 56.413 ; + END + END r0_rd_out[356] + PIN r0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 56.359 102.753 56.413 ; + END + END r0_rd_out[357] + PIN r0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 56.359 103.041 56.413 ; + END + END r0_rd_out[358] + PIN r0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 56.359 103.329 56.413 ; + END + END r0_rd_out[359] + PIN r0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 56.359 103.617 56.413 ; + END + END r0_rd_out[360] + PIN r0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 56.359 103.905 56.413 ; + END + END r0_rd_out[361] + PIN r0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 56.359 104.193 56.413 ; + END + END r0_rd_out[362] + PIN r0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 56.359 104.481 56.413 ; + END + END r0_rd_out[363] + PIN r0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 56.359 104.769 56.413 ; + END + END r0_rd_out[364] + PIN r0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 56.359 105.057 56.413 ; + END + END r0_rd_out[365] + PIN r0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 56.359 105.345 56.413 ; + END + END r0_rd_out[366] + PIN r0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 56.359 105.633 56.413 ; + END + END r0_rd_out[367] + PIN r0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 56.359 105.921 56.413 ; + END + END r0_rd_out[368] + PIN r0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 56.359 106.209 56.413 ; + END + END r0_rd_out[369] + PIN r0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 56.359 106.497 56.413 ; + END + END r0_rd_out[370] + PIN r0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 56.359 106.785 56.413 ; + END + END r0_rd_out[371] + PIN r0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 56.359 107.073 56.413 ; + END + END r0_rd_out[372] + PIN r0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 56.359 107.361 56.413 ; + END + END r0_rd_out[373] + PIN r0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 56.359 107.649 56.413 ; + END + END r0_rd_out[374] + PIN r0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 56.359 107.937 56.413 ; + END + END r0_rd_out[375] + PIN r0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 56.359 108.225 56.413 ; + END + END r0_rd_out[376] + PIN r0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 56.359 108.513 56.413 ; + END + END r0_rd_out[377] + PIN r0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 56.359 108.801 56.413 ; + END + END r0_rd_out[378] + PIN r0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 56.359 109.089 56.413 ; + END + END r0_rd_out[379] + PIN r0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 56.359 109.377 56.413 ; + END + END r0_rd_out[380] + PIN r0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 56.359 109.665 56.413 ; + END + END r0_rd_out[381] + PIN r0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 56.359 109.953 56.413 ; + END + END r0_rd_out[382] + PIN r0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 56.359 110.241 56.413 ; + END + END r0_rd_out[383] + PIN r0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 56.359 110.529 56.413 ; + END + END r0_rd_out[384] + PIN r0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 56.359 110.817 56.413 ; + END + END r0_rd_out[385] + PIN r0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 56.359 111.105 56.413 ; + END + END r0_rd_out[386] + PIN r0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 56.359 111.393 56.413 ; + END + END r0_rd_out[387] + PIN r0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 56.359 111.681 56.413 ; + END + END r0_rd_out[388] + PIN r0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 56.359 111.969 56.413 ; + END + END r0_rd_out[389] + PIN r0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 56.359 112.257 56.413 ; + END + END r0_rd_out[390] + PIN r0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 56.359 112.545 56.413 ; + END + END r0_rd_out[391] + PIN r0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 56.359 112.833 56.413 ; + END + END r0_rd_out[392] + PIN r0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 56.359 113.121 56.413 ; + END + END r0_rd_out[393] + PIN r0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 56.359 113.409 56.413 ; + END + END r0_rd_out[394] + PIN r0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 56.359 113.697 56.413 ; + END + END r0_rd_out[395] + PIN r0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 56.359 113.985 56.413 ; + END + END r0_rd_out[396] + PIN r0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 56.359 114.273 56.413 ; + END + END r0_rd_out[397] + PIN r0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 56.359 114.561 56.413 ; + END + END r0_rd_out[398] + PIN r0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 56.359 114.849 56.413 ; + END + END r0_rd_out[399] + PIN r0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 56.359 115.137 56.413 ; + END + END r0_rd_out[400] + PIN r0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 56.359 115.425 56.413 ; + END + END r0_rd_out[401] + PIN r0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 56.359 115.713 56.413 ; + END + END r0_rd_out[402] + PIN r0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 56.359 116.001 56.413 ; + END + END r0_rd_out[403] + PIN r0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 56.359 116.289 56.413 ; + END + END r0_rd_out[404] + PIN r0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 56.359 116.577 56.413 ; + END + END r0_rd_out[405] + PIN r0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 56.359 116.865 56.413 ; + END + END r0_rd_out[406] + PIN r0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 56.359 117.153 56.413 ; + END + END r0_rd_out[407] + PIN r0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 56.359 117.441 56.413 ; + END + END r0_rd_out[408] + PIN r0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 56.359 117.729 56.413 ; + END + END r0_rd_out[409] + PIN r0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 56.359 118.017 56.413 ; + END + END r0_rd_out[410] + PIN r0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 56.359 118.305 56.413 ; + END + END r0_rd_out[411] + PIN r0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 56.359 118.593 56.413 ; + END + END r0_rd_out[412] + PIN r0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 56.359 118.881 56.413 ; + END + END r0_rd_out[413] + PIN r0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 56.359 119.169 56.413 ; + END + END r0_rd_out[414] + PIN r0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 56.359 119.457 56.413 ; + END + END r0_rd_out[415] + PIN r0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 56.359 119.745 56.413 ; + END + END r0_rd_out[416] + PIN r0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 56.359 120.033 56.413 ; + END + END r0_rd_out[417] + PIN r0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 56.359 120.321 56.413 ; + END + END r0_rd_out[418] + PIN r0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 56.359 120.609 56.413 ; + END + END r0_rd_out[419] + PIN r0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 56.359 120.897 56.413 ; + END + END r0_rd_out[420] + PIN r0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 56.359 121.185 56.413 ; + END + END r0_rd_out[421] + PIN r0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 56.359 121.473 56.413 ; + END + END r0_rd_out[422] + PIN r0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 56.359 121.761 56.413 ; + END + END r0_rd_out[423] + PIN r0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 56.359 122.049 56.413 ; + END + END r0_rd_out[424] + PIN r0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 56.359 122.337 56.413 ; + END + END r0_rd_out[425] + PIN r0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 56.359 122.625 56.413 ; + END + END r0_rd_out[426] + PIN r0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 56.359 122.913 56.413 ; + END + END r0_rd_out[427] + PIN r0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 56.359 123.201 56.413 ; + END + END r0_rd_out[428] + PIN r0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 56.359 123.489 56.413 ; + END + END r0_rd_out[429] + PIN r0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 56.359 123.777 56.413 ; + END + END r0_rd_out[430] + PIN r0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 56.359 124.065 56.413 ; + END + END r0_rd_out[431] + PIN r0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 56.359 124.353 56.413 ; + END + END r0_rd_out[432] + PIN r0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 56.359 124.641 56.413 ; + END + END r0_rd_out[433] + PIN r0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 56.359 124.929 56.413 ; + END + END r0_rd_out[434] + PIN r0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 56.359 125.217 56.413 ; + END + END r0_rd_out[435] + PIN r0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 56.359 125.505 56.413 ; + END + END r0_rd_out[436] + PIN r0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 56.359 125.793 56.413 ; + END + END r0_rd_out[437] + PIN r0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 56.359 126.081 56.413 ; + END + END r0_rd_out[438] + PIN r0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 56.359 126.369 56.413 ; + END + END r0_rd_out[439] + PIN r0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 56.359 126.657 56.413 ; + END + END r0_rd_out[440] + PIN r0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 56.359 126.945 56.413 ; + END + END r0_rd_out[441] + PIN r0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 56.359 127.233 56.413 ; + END + END r0_rd_out[442] + PIN r0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 56.359 127.521 56.413 ; + END + END r0_rd_out[443] + PIN r0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 56.359 127.809 56.413 ; + END + END r0_rd_out[444] + PIN r0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 56.359 128.097 56.413 ; + END + END r0_rd_out[445] + PIN r0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 56.359 128.385 56.413 ; + END + END r0_rd_out[446] + PIN r0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 56.359 128.673 56.413 ; + END + END r0_rd_out[447] + PIN r0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 56.359 128.961 56.413 ; + END + END r0_rd_out[448] + PIN r0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 56.359 129.249 56.413 ; + END + END r0_rd_out[449] + PIN r0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 56.359 129.537 56.413 ; + END + END r0_rd_out[450] + PIN r0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 56.359 129.825 56.413 ; + END + END r0_rd_out[451] + PIN r0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 56.359 130.113 56.413 ; + END + END r0_rd_out[452] + PIN r0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 56.359 130.401 56.413 ; + END + END r0_rd_out[453] + PIN r0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 56.359 130.689 56.413 ; + END + END r0_rd_out[454] + PIN r0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 56.359 130.977 56.413 ; + END + END r0_rd_out[455] + PIN r0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 56.359 131.265 56.413 ; + END + END r0_rd_out[456] + PIN r0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 56.359 131.553 56.413 ; + END + END r0_rd_out[457] + PIN r0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 56.359 131.841 56.413 ; + END + END r0_rd_out[458] + PIN r0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 56.359 132.129 56.413 ; + END + END r0_rd_out[459] + PIN r0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 56.359 132.417 56.413 ; + END + END r0_rd_out[460] + PIN r0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 56.359 132.705 56.413 ; + END + END r0_rd_out[461] + PIN r0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 56.359 132.993 56.413 ; + END + END r0_rd_out[462] + PIN r0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 56.359 133.281 56.413 ; + END + END r0_rd_out[463] + PIN r0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 56.359 133.569 56.413 ; + END + END r0_rd_out[464] + PIN r0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 56.359 133.857 56.413 ; + END + END r0_rd_out[465] + PIN r0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 56.359 134.145 56.413 ; + END + END r0_rd_out[466] + PIN r0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 56.359 134.433 56.413 ; + END + END r0_rd_out[467] + PIN r0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 56.359 134.721 56.413 ; + END + END r0_rd_out[468] + PIN r0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 56.359 135.009 56.413 ; + END + END r0_rd_out[469] + PIN r0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 56.359 135.297 56.413 ; + END + END r0_rd_out[470] + PIN r0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 56.359 135.585 56.413 ; + END + END r0_rd_out[471] + PIN r0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 56.359 135.873 56.413 ; + END + END r0_rd_out[472] + PIN r0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 56.359 136.161 56.413 ; + END + END r0_rd_out[473] + PIN r0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 56.359 136.449 56.413 ; + END + END r0_rd_out[474] + PIN r0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 56.359 136.737 56.413 ; + END + END r0_rd_out[475] + PIN r0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 56.359 137.025 56.413 ; + END + END r0_rd_out[476] + PIN r0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 56.359 137.313 56.413 ; + END + END r0_rd_out[477] + PIN r0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 56.359 137.601 56.413 ; + END + END r0_rd_out[478] + PIN r0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 56.359 137.889 56.413 ; + END + END r0_rd_out[479] + PIN r0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 56.359 138.177 56.413 ; + END + END r0_rd_out[480] + PIN r0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 56.359 138.465 56.413 ; + END + END r0_rd_out[481] + PIN r0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 56.359 138.753 56.413 ; + END + END r0_rd_out[482] + PIN r0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 56.359 139.041 56.413 ; + END + END r0_rd_out[483] + PIN r0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 56.359 139.329 56.413 ; + END + END r0_rd_out[484] + PIN r0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 56.359 139.617 56.413 ; + END + END r0_rd_out[485] + PIN r0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 56.359 139.905 56.413 ; + END + END r0_rd_out[486] + PIN r0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 56.359 140.193 56.413 ; + END + END r0_rd_out[487] + PIN r0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 56.359 140.481 56.413 ; + END + END r0_rd_out[488] + PIN r0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 56.359 140.769 56.413 ; + END + END r0_rd_out[489] + PIN r0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 56.359 141.057 56.413 ; + END + END r0_rd_out[490] + PIN r0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 56.359 141.345 56.413 ; + END + END r0_rd_out[491] + PIN r0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 56.359 141.633 56.413 ; + END + END r0_rd_out[492] + PIN r0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 56.359 141.921 56.413 ; + END + END r0_rd_out[493] + PIN r0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 56.359 142.209 56.413 ; + END + END r0_rd_out[494] + PIN r0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 56.359 142.497 56.413 ; + END + END r0_rd_out[495] + PIN r0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 56.359 142.785 56.413 ; + END + END r0_rd_out[496] + PIN r0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 56.359 143.073 56.413 ; + END + END r0_rd_out[497] + PIN r0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 56.359 143.361 56.413 ; + END + END r0_rd_out[498] + PIN r0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 56.359 143.649 56.413 ; + END + END r0_rd_out[499] + PIN r0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 56.359 143.937 56.413 ; + END + END r0_rd_out[500] + PIN r0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 56.359 144.225 56.413 ; + END + END r0_rd_out[501] + PIN r0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 56.359 144.513 56.413 ; + END + END r0_rd_out[502] + PIN r0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 56.359 144.801 56.413 ; + END + END r0_rd_out[503] + PIN r0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 56.359 145.089 56.413 ; + END + END r0_rd_out[504] + PIN r0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 56.359 145.377 56.413 ; + END + END r0_rd_out[505] + PIN r0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 56.359 145.665 56.413 ; + END + END r0_rd_out[506] + PIN r0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 56.359 145.953 56.413 ; + END + END r0_rd_out[507] + PIN r0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 56.359 146.241 56.413 ; + END + END r0_rd_out[508] + PIN r0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 56.359 146.529 56.413 ; + END + END r0_rd_out[509] + PIN r0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 56.359 146.817 56.413 ; + END + END r0_rd_out[510] + PIN r0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 56.359 147.105 56.413 ; + END + END r0_rd_out[511] + PIN r0_rd_out[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 56.359 147.393 56.413 ; + END + END r0_rd_out[512] + PIN r0_rd_out[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 56.359 147.681 56.413 ; + END + END r0_rd_out[513] + PIN r0_rd_out[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 56.359 147.969 56.413 ; + END + END r0_rd_out[514] + PIN r0_rd_out[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 56.359 148.257 56.413 ; + END + END r0_rd_out[515] + PIN r0_rd_out[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 56.359 148.545 56.413 ; + END + END r0_rd_out[516] + PIN r0_rd_out[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 56.359 148.833 56.413 ; + END + END r0_rd_out[517] + PIN r0_rd_out[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 56.359 149.121 56.413 ; + END + END r0_rd_out[518] + PIN r0_rd_out[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 56.359 149.409 56.413 ; + END + END r0_rd_out[519] + PIN r0_rd_out[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 56.359 149.697 56.413 ; + END + END r0_rd_out[520] + PIN r0_rd_out[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 56.359 149.985 56.413 ; + END + END r0_rd_out[521] + PIN r0_rd_out[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 56.359 150.273 56.413 ; + END + END r0_rd_out[522] + PIN r0_rd_out[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 56.359 150.561 56.413 ; + END + END r0_rd_out[523] + PIN r0_rd_out[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 56.359 150.849 56.413 ; + END + END r0_rd_out[524] + PIN r0_rd_out[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 56.359 151.137 56.413 ; + END + END r0_rd_out[525] + PIN r0_rd_out[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 56.359 151.425 56.413 ; + END + END r0_rd_out[526] + PIN r0_rd_out[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 56.359 151.713 56.413 ; + END + END r0_rd_out[527] + PIN r0_rd_out[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 56.359 152.001 56.413 ; + END + END r0_rd_out[528] + PIN r0_rd_out[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 56.359 152.289 56.413 ; + END + END r0_rd_out[529] + PIN r0_rd_out[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 56.359 152.577 56.413 ; + END + END r0_rd_out[530] + PIN r0_rd_out[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 56.359 152.865 56.413 ; + END + END r0_rd_out[531] + PIN r0_rd_out[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 56.359 153.153 56.413 ; + END + END r0_rd_out[532] + PIN r0_rd_out[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 56.359 153.441 56.413 ; + END + END r0_rd_out[533] + PIN r0_rd_out[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 56.359 153.729 56.413 ; + END + END r0_rd_out[534] + PIN r0_rd_out[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 56.359 154.017 56.413 ; + END + END r0_rd_out[535] + PIN r0_rd_out[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 56.359 154.305 56.413 ; + END + END r0_rd_out[536] + PIN r0_rd_out[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 56.359 154.593 56.413 ; + END + END r0_rd_out[537] + PIN r0_rd_out[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 56.359 154.881 56.413 ; + END + END r0_rd_out[538] + PIN r0_rd_out[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 56.359 155.169 56.413 ; + END + END r0_rd_out[539] + PIN r0_rd_out[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 56.359 155.457 56.413 ; + END + END r0_rd_out[540] + PIN r0_rd_out[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 56.359 155.745 56.413 ; + END + END r0_rd_out[541] + PIN r0_rd_out[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 56.359 156.033 56.413 ; + END + END r0_rd_out[542] + PIN r0_rd_out[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 56.359 156.321 56.413 ; + END + END r0_rd_out[543] + PIN r0_rd_out[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 56.359 156.609 56.413 ; + END + END r0_rd_out[544] + PIN r0_rd_out[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 56.359 156.897 56.413 ; + END + END r0_rd_out[545] + PIN r0_rd_out[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 56.359 157.185 56.413 ; + END + END r0_rd_out[546] + PIN r0_rd_out[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 56.359 157.473 56.413 ; + END + END r0_rd_out[547] + PIN r0_rd_out[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 56.359 157.761 56.413 ; + END + END r0_rd_out[548] + PIN r0_rd_out[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 56.359 158.049 56.413 ; + END + END r0_rd_out[549] + PIN r0_rd_out[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 56.359 158.337 56.413 ; + END + END r0_rd_out[550] + PIN r0_rd_out[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 56.359 158.625 56.413 ; + END + END r0_rd_out[551] + PIN r0_rd_out[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 56.359 158.913 56.413 ; + END + END r0_rd_out[552] + PIN r0_rd_out[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 56.359 159.201 56.413 ; + END + END r0_rd_out[553] + PIN r0_rd_out[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 56.359 159.489 56.413 ; + END + END r0_rd_out[554] + PIN r0_rd_out[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 56.359 159.777 56.413 ; + END + END r0_rd_out[555] + PIN r0_rd_out[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 56.359 160.065 56.413 ; + END + END r0_rd_out[556] + PIN r0_rd_out[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 56.359 160.353 56.413 ; + END + END r0_rd_out[557] + PIN r0_rd_out[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 56.359 160.641 56.413 ; + END + END r0_rd_out[558] + PIN r0_rd_out[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 56.359 160.929 56.413 ; + END + END r0_rd_out[559] + PIN r0_rd_out[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 56.359 161.217 56.413 ; + END + END r0_rd_out[560] + PIN r0_rd_out[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 56.359 161.505 56.413 ; + END + END r0_rd_out[561] + PIN r0_rd_out[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 56.359 161.793 56.413 ; + END + END r0_rd_out[562] + PIN r0_rd_out[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 56.359 162.081 56.413 ; + END + END r0_rd_out[563] + PIN r0_rd_out[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 56.359 162.369 56.413 ; + END + END r0_rd_out[564] + PIN r0_rd_out[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 56.359 162.657 56.413 ; + END + END r0_rd_out[565] + PIN r0_rd_out[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 56.359 162.945 56.413 ; + END + END r0_rd_out[566] + PIN r0_rd_out[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.215 56.359 163.233 56.413 ; + END + END r0_rd_out[567] + PIN r0_rd_out[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.503 56.359 163.521 56.413 ; + END + END r0_rd_out[568] + PIN r0_rd_out[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.791 56.359 163.809 56.413 ; + END + END r0_rd_out[569] + PIN r0_rd_out[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.079 56.359 164.097 56.413 ; + END + END r0_rd_out[570] + PIN r0_rd_out[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 56.359 164.385 56.413 ; + END + END r0_rd_out[571] + PIN r0_rd_out[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.655 56.359 164.673 56.413 ; + END + END r0_rd_out[572] + PIN r0_rd_out[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.943 56.359 164.961 56.413 ; + END + END r0_rd_out[573] + PIN r0_rd_out[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.231 56.359 165.249 56.413 ; + END + END r0_rd_out[574] + PIN r0_rd_out[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.519 56.359 165.537 56.413 ; + END + END r0_rd_out[575] + PIN r0_rd_out[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 56.359 165.825 56.413 ; + END + END r0_rd_out[576] + PIN r0_rd_out[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.095 56.359 166.113 56.413 ; + END + END r0_rd_out[577] + PIN r0_rd_out[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.383 56.359 166.401 56.413 ; + END + END r0_rd_out[578] + PIN r0_rd_out[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.671 56.359 166.689 56.413 ; + END + END r0_rd_out[579] + PIN r0_rd_out[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.959 56.359 166.977 56.413 ; + END + END r0_rd_out[580] + PIN r0_rd_out[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 56.359 167.265 56.413 ; + END + END r0_rd_out[581] + PIN r0_rd_out[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.535 56.359 167.553 56.413 ; + END + END r0_rd_out[582] + PIN r0_rd_out[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.823 56.359 167.841 56.413 ; + END + END r0_rd_out[583] + PIN r0_rd_out[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.111 56.359 168.129 56.413 ; + END + END r0_rd_out[584] + PIN r0_rd_out[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.399 56.359 168.417 56.413 ; + END + END r0_rd_out[585] + PIN r0_rd_out[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 56.359 168.705 56.413 ; + END + END r0_rd_out[586] + PIN r0_rd_out[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.975 56.359 168.993 56.413 ; + END + END r0_rd_out[587] + PIN r0_rd_out[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.263 56.359 169.281 56.413 ; + END + END r0_rd_out[588] + PIN r0_rd_out[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.551 56.359 169.569 56.413 ; + END + END r0_rd_out[589] + PIN r0_rd_out[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.839 56.359 169.857 56.413 ; + END + END r0_rd_out[590] + PIN r0_rd_out[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 56.359 170.145 56.413 ; + END + END r0_rd_out[591] + PIN r0_rd_out[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.415 56.359 170.433 56.413 ; + END + END r0_rd_out[592] + PIN r0_rd_out[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.703 56.359 170.721 56.413 ; + END + END r0_rd_out[593] + PIN r0_rd_out[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.991 56.359 171.009 56.413 ; + END + END r0_rd_out[594] + PIN r0_rd_out[595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.279 56.359 171.297 56.413 ; + END + END r0_rd_out[595] + PIN r0_rd_out[596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 56.359 171.585 56.413 ; + END + END r0_rd_out[596] + PIN r0_rd_out[597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.855 56.359 171.873 56.413 ; + END + END r0_rd_out[597] + PIN r0_rd_out[598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.143 56.359 172.161 56.413 ; + END + END r0_rd_out[598] + PIN r0_rd_out[599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.431 56.359 172.449 56.413 ; + END + END r0_rd_out[599] + PIN r0_rd_out[600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.719 56.359 172.737 56.413 ; + END + END r0_rd_out[600] + PIN r0_rd_out[601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.007 56.359 173.025 56.413 ; + END + END r0_rd_out[601] + PIN r0_rd_out[602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.295 56.359 173.313 56.413 ; + END + END r0_rd_out[602] + PIN r0_rd_out[603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.583 56.359 173.601 56.413 ; + END + END r0_rd_out[603] + PIN r0_rd_out[604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.871 56.359 173.889 56.413 ; + END + END r0_rd_out[604] + PIN r0_rd_out[605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.159 56.359 174.177 56.413 ; + END + END r0_rd_out[605] + PIN r0_rd_out[606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.447 56.359 174.465 56.413 ; + END + END r0_rd_out[606] + PIN r0_rd_out[607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.735 56.359 174.753 56.413 ; + END + END r0_rd_out[607] + PIN r0_rd_out[608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.023 56.359 175.041 56.413 ; + END + END r0_rd_out[608] + PIN r0_rd_out[609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.311 56.359 175.329 56.413 ; + END + END r0_rd_out[609] + PIN r0_rd_out[610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.599 56.359 175.617 56.413 ; + END + END r0_rd_out[610] + PIN r0_rd_out[611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.887 56.359 175.905 56.413 ; + END + END r0_rd_out[611] + PIN r0_rd_out[612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.175 56.359 176.193 56.413 ; + END + END r0_rd_out[612] + PIN r0_rd_out[613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.463 56.359 176.481 56.413 ; + END + END r0_rd_out[613] + PIN r0_rd_out[614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.751 56.359 176.769 56.413 ; + END + END r0_rd_out[614] + PIN r0_rd_out[615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.039 56.359 177.057 56.413 ; + END + END r0_rd_out[615] + PIN r0_rd_out[616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.327 56.359 177.345 56.413 ; + END + END r0_rd_out[616] + PIN r0_rd_out[617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.615 56.359 177.633 56.413 ; + END + END r0_rd_out[617] + PIN r0_rd_out[618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.903 56.359 177.921 56.413 ; + END + END r0_rd_out[618] + PIN r0_rd_out[619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.191 56.359 178.209 56.413 ; + END + END r0_rd_out[619] + PIN r0_rd_out[620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.479 56.359 178.497 56.413 ; + END + END r0_rd_out[620] + PIN r0_rd_out[621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.767 56.359 178.785 56.413 ; + END + END r0_rd_out[621] + PIN r0_rd_out[622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.055 56.359 179.073 56.413 ; + END + END r0_rd_out[622] + PIN r0_rd_out[623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.343 56.359 179.361 56.413 ; + END + END r0_rd_out[623] + PIN r0_rd_out[624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.631 56.359 179.649 56.413 ; + END + END r0_rd_out[624] + PIN r0_rd_out[625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.919 56.359 179.937 56.413 ; + END + END r0_rd_out[625] + PIN r0_rd_out[626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.207 56.359 180.225 56.413 ; + END + END r0_rd_out[626] + PIN r0_rd_out[627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.495 56.359 180.513 56.413 ; + END + END r0_rd_out[627] + PIN r0_rd_out[628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.783 56.359 180.801 56.413 ; + END + END r0_rd_out[628] + PIN r0_rd_out[629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.071 56.359 181.089 56.413 ; + END + END r0_rd_out[629] + PIN r0_rd_out[630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.359 56.359 181.377 56.413 ; + END + END r0_rd_out[630] + PIN r0_rd_out[631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.647 56.359 181.665 56.413 ; + END + END r0_rd_out[631] + PIN r0_rd_out[632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.935 56.359 181.953 56.413 ; + END + END r0_rd_out[632] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.068 0.072 46.092 ; + END + END w0_addr_in[0] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.212 0.072 46.236 ; + END + END r0_addr_in[0] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.223 56.359 182.241 56.413 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.511 56.359 182.529 56.413 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.799 56.359 182.817 56.413 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.087 56.359 183.105 56.413 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.375 56.359 183.393 56.413 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 201.595 0.336 ; + RECT 0.216 1.008 201.595 1.104 ; + RECT 0.216 1.776 201.595 1.872 ; + RECT 0.216 2.544 201.595 2.640 ; + RECT 0.216 3.312 201.595 3.408 ; + RECT 0.216 4.080 201.595 4.176 ; + RECT 0.216 4.848 201.595 4.944 ; + RECT 0.216 5.616 201.595 5.712 ; + RECT 0.216 6.384 201.595 6.480 ; + RECT 0.216 7.152 201.595 7.248 ; + RECT 0.216 7.920 201.595 8.016 ; + RECT 0.216 8.688 201.595 8.784 ; + RECT 0.216 9.456 201.595 9.552 ; + RECT 0.216 10.224 201.595 10.320 ; + RECT 0.216 10.992 201.595 11.088 ; + RECT 0.216 11.760 201.595 11.856 ; + RECT 0.216 12.528 201.595 12.624 ; + RECT 0.216 13.296 201.595 13.392 ; + RECT 0.216 14.064 201.595 14.160 ; + RECT 0.216 14.832 201.595 14.928 ; + RECT 0.216 15.600 201.595 15.696 ; + RECT 0.216 16.368 201.595 16.464 ; + RECT 0.216 17.136 201.595 17.232 ; + RECT 0.216 17.904 201.595 18.000 ; + RECT 0.216 18.672 201.595 18.768 ; + RECT 0.216 19.440 201.595 19.536 ; + RECT 0.216 20.208 201.595 20.304 ; + RECT 0.216 20.976 201.595 21.072 ; + RECT 0.216 21.744 201.595 21.840 ; + RECT 0.216 22.512 201.595 22.608 ; + RECT 0.216 23.280 201.595 23.376 ; + RECT 0.216 24.048 201.595 24.144 ; + RECT 0.216 24.816 201.595 24.912 ; + RECT 0.216 25.584 201.595 25.680 ; + RECT 0.216 26.352 201.595 26.448 ; + RECT 0.216 27.120 201.595 27.216 ; + RECT 0.216 27.888 201.595 27.984 ; + RECT 0.216 28.656 201.595 28.752 ; + RECT 0.216 29.424 201.595 29.520 ; + RECT 0.216 30.192 201.595 30.288 ; + RECT 0.216 30.960 201.595 31.056 ; + RECT 0.216 31.728 201.595 31.824 ; + RECT 0.216 32.496 201.595 32.592 ; + RECT 0.216 33.264 201.595 33.360 ; + RECT 0.216 34.032 201.595 34.128 ; + RECT 0.216 34.800 201.595 34.896 ; + RECT 0.216 35.568 201.595 35.664 ; + RECT 0.216 36.336 201.595 36.432 ; + RECT 0.216 37.104 201.595 37.200 ; + RECT 0.216 37.872 201.595 37.968 ; + RECT 0.216 38.640 201.595 38.736 ; + RECT 0.216 39.408 201.595 39.504 ; + RECT 0.216 40.176 201.595 40.272 ; + RECT 0.216 40.944 201.595 41.040 ; + RECT 0.216 41.712 201.595 41.808 ; + RECT 0.216 42.480 201.595 42.576 ; + RECT 0.216 43.248 201.595 43.344 ; + RECT 0.216 44.016 201.595 44.112 ; + RECT 0.216 44.784 201.595 44.880 ; + RECT 0.216 45.552 201.595 45.648 ; + RECT 0.216 46.320 201.595 46.416 ; + RECT 0.216 47.088 201.595 47.184 ; + RECT 0.216 47.856 201.595 47.952 ; + RECT 0.216 48.624 201.595 48.720 ; + RECT 0.216 49.392 201.595 49.488 ; + RECT 0.216 50.160 201.595 50.256 ; + RECT 0.216 50.928 201.595 51.024 ; + RECT 0.216 51.696 201.595 51.792 ; + RECT 0.216 52.464 201.595 52.560 ; + RECT 0.216 53.232 201.595 53.328 ; + RECT 0.216 54.000 201.595 54.096 ; + RECT 0.216 54.768 201.595 54.864 ; + RECT 0.216 55.536 201.595 55.632 ; + RECT 0.216 56.304 201.595 56.400 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 201.595 0.336 ; + RECT 0.216 1.008 201.595 1.104 ; + RECT 0.216 1.776 201.595 1.872 ; + RECT 0.216 2.544 201.595 2.640 ; + RECT 0.216 3.312 201.595 3.408 ; + RECT 0.216 4.080 201.595 4.176 ; + RECT 0.216 4.848 201.595 4.944 ; + RECT 0.216 5.616 201.595 5.712 ; + RECT 0.216 6.384 201.595 6.480 ; + RECT 0.216 7.152 201.595 7.248 ; + RECT 0.216 7.920 201.595 8.016 ; + RECT 0.216 8.688 201.595 8.784 ; + RECT 0.216 9.456 201.595 9.552 ; + RECT 0.216 10.224 201.595 10.320 ; + RECT 0.216 10.992 201.595 11.088 ; + RECT 0.216 11.760 201.595 11.856 ; + RECT 0.216 12.528 201.595 12.624 ; + RECT 0.216 13.296 201.595 13.392 ; + RECT 0.216 14.064 201.595 14.160 ; + RECT 0.216 14.832 201.595 14.928 ; + RECT 0.216 15.600 201.595 15.696 ; + RECT 0.216 16.368 201.595 16.464 ; + RECT 0.216 17.136 201.595 17.232 ; + RECT 0.216 17.904 201.595 18.000 ; + RECT 0.216 18.672 201.595 18.768 ; + RECT 0.216 19.440 201.595 19.536 ; + RECT 0.216 20.208 201.595 20.304 ; + RECT 0.216 20.976 201.595 21.072 ; + RECT 0.216 21.744 201.595 21.840 ; + RECT 0.216 22.512 201.595 22.608 ; + RECT 0.216 23.280 201.595 23.376 ; + RECT 0.216 24.048 201.595 24.144 ; + RECT 0.216 24.816 201.595 24.912 ; + RECT 0.216 25.584 201.595 25.680 ; + RECT 0.216 26.352 201.595 26.448 ; + RECT 0.216 27.120 201.595 27.216 ; + RECT 0.216 27.888 201.595 27.984 ; + RECT 0.216 28.656 201.595 28.752 ; + RECT 0.216 29.424 201.595 29.520 ; + RECT 0.216 30.192 201.595 30.288 ; + RECT 0.216 30.960 201.595 31.056 ; + RECT 0.216 31.728 201.595 31.824 ; + RECT 0.216 32.496 201.595 32.592 ; + RECT 0.216 33.264 201.595 33.360 ; + RECT 0.216 34.032 201.595 34.128 ; + RECT 0.216 34.800 201.595 34.896 ; + RECT 0.216 35.568 201.595 35.664 ; + RECT 0.216 36.336 201.595 36.432 ; + RECT 0.216 37.104 201.595 37.200 ; + RECT 0.216 37.872 201.595 37.968 ; + RECT 0.216 38.640 201.595 38.736 ; + RECT 0.216 39.408 201.595 39.504 ; + RECT 0.216 40.176 201.595 40.272 ; + RECT 0.216 40.944 201.595 41.040 ; + RECT 0.216 41.712 201.595 41.808 ; + RECT 0.216 42.480 201.595 42.576 ; + RECT 0.216 43.248 201.595 43.344 ; + RECT 0.216 44.016 201.595 44.112 ; + RECT 0.216 44.784 201.595 44.880 ; + RECT 0.216 45.552 201.595 45.648 ; + RECT 0.216 46.320 201.595 46.416 ; + RECT 0.216 47.088 201.595 47.184 ; + RECT 0.216 47.856 201.595 47.952 ; + RECT 0.216 48.624 201.595 48.720 ; + RECT 0.216 49.392 201.595 49.488 ; + RECT 0.216 50.160 201.595 50.256 ; + RECT 0.216 50.928 201.595 51.024 ; + RECT 0.216 51.696 201.595 51.792 ; + RECT 0.216 52.464 201.595 52.560 ; + RECT 0.216 53.232 201.595 53.328 ; + RECT 0.216 54.000 201.595 54.096 ; + RECT 0.216 54.768 201.595 54.864 ; + RECT 0.216 55.536 201.595 55.632 ; + RECT 0.216 56.304 201.595 56.400 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 201.811 56.413 ; + LAYER M2 ; + RECT 0 0 201.811 56.413 ; + LAYER M3 ; + RECT 0 0 201.811 56.413 ; + LAYER M4 ; + RECT 0 0 201.811 56.413 ; + END +END fakeram_633x8_1r1w + +END LIBRARY diff --git a/designs/asap7/coralnpu/sram/lib/fakeram_2048x128_1rw.lib b/designs/asap7/coralnpu/sram/lib/fakeram_2048x128_1rw.lib new file mode 100644 index 0000000..3ef0363 --- /dev/null +++ b/designs/asap7/coralnpu/sram/lib/fakeram_2048x128_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_2048x128_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-01-25 23:59:45Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_2048x128_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_2048x128_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_2048x128_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_2048x128_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_2048x128_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_2048x128_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 2048; + bit_from : 2047; + bit_to : 0 ; + downto : true ; + } + type (fakeram_2048x128_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } + type (fakeram_2048x128_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 256; + bit_from : 255; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_2048x128_1rw) { + area : 54092.481; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 2048; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_2048x128_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_2048x128_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_2048x128_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_2048x128_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_2048x128_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_2048x128_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_2048x128_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_2048x128_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_2048x128_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_2048x128_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/coralnpu/sram/lib/fakeram_512x128_1rw.lib b/designs/asap7/coralnpu/sram/lib/fakeram_512x128_1rw.lib new file mode 100644 index 0000000..f350bfd --- /dev/null +++ b/designs/asap7/coralnpu/sram/lib/fakeram_512x128_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_512x128_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-01-25 23:59:45Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_512x128_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_512x128_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_512x128_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_512x128_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_512x128_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_512x128_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 512; + bit_from : 511; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x128_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 7; + bit_from : 6; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x128_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_512x128_1rw) { + area : 4507.776; + interface_timing : true; + memory() { + type : ram; + address_width : 7; + word_width : 512; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_512x128_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_512x128_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_512x128_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_512x128_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_512x128_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_512x128_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_512x128_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_512x128_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_512x128_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_512x128_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/coralnpu/sram/lib/fakeram_595x8_1r1w.lib b/designs/asap7/coralnpu/sram/lib/fakeram_595x8_1r1w.lib new file mode 100644 index 0000000..10520db --- /dev/null +++ b/designs/asap7/coralnpu/sram/lib/fakeram_595x8_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_595x8_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-01-03 23:16:16Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_595x8_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_595x8_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_595x8_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_595x8_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_595x8_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_595x8_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 595; + bit_from : 594; + bit_to : 0 ; + downto : true ; + } + type (fakeram_595x8_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 1; + bit_from : 0; + bit_to : 0 ; + downto : true ; + } + type (fakeram_595x8_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 74; + bit_from : 73; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_595x8_1r1w) { + area : 10062.993; + interface_timing : true; + memory() { + type : ram; + address_width : 1; + word_width : 595; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_595x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_595x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_595x8_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_595x8_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_595x8_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_595x8_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_595x8_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_595x8_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_595x8_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_595x8_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_595x8_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_595x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_595x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/coralnpu/sram/lib/fakeram_633x8_1r1w.lib b/designs/asap7/coralnpu/sram/lib/fakeram_633x8_1r1w.lib new file mode 100644 index 0000000..d2235d9 --- /dev/null +++ b/designs/asap7/coralnpu/sram/lib/fakeram_633x8_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_633x8_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-01-03 23:16:16Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_633x8_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_633x8_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_633x8_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_633x8_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_633x8_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_633x8_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 633; + bit_from : 632; + bit_to : 0 ; + downto : true ; + } + type (fakeram_633x8_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 1; + bit_from : 0; + bit_to : 0 ; + downto : true ; + } + type (fakeram_633x8_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 79; + bit_from : 78; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_633x8_1r1w) { + area : 11384.764; + interface_timing : true; + memory() { + type : ram; + address_width : 1; + word_width : 633; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_633x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_633x8_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_633x8_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_633x8_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_633x8_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_633x8_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_633x8_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_633x8_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_633x8_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_633x8_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_633x8_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_633x8_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_633x8_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/minimax/config.mk b/designs/asap7/minimax/config.mk index c8f89e6..197c876 100644 --- a/designs/asap7/minimax/config.mk +++ b/designs/asap7/minimax/config.mk @@ -1,4 +1,5 @@ export DESIGN_NAME = minimax + export PLATFORM = asap7 # This could be a wildcard diff --git a/designs/asap7/minimax/constraint.sdc b/designs/asap7/minimax/constraint.sdc index fa2f900..9c4a387 100644 --- a/designs/asap7/minimax/constraint.sdc +++ b/designs/asap7/minimax/constraint.sdc @@ -1,7 +1,7 @@ current_design minimax set clk_name clk -set clk_period 400 +set clk_period 850 set clk_io_pct 0.2 set clk_port [get_ports $clk_name] diff --git a/designs/asap7/vortex/config.mk b/designs/asap7/vortex/config.mk new file mode 100644 index 0000000..e4b9e91 --- /dev/null +++ b/designs/asap7/vortex/config.mk @@ -0,0 +1,44 @@ +export DESIGN_NAME = Vortex +export PLATFORM = asap7 +export DESIGN_NICKNAME = vortex +export DESIGN_RESULTS_NAME = vortex + +-include $(BENCH_DESIGN_HOME)/src/vortex/verilog.mk + +export SYNTH_HIERARCHICAL = 0 + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_32x1024_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_128x64_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_193x16_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_512x64_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_21x256_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_128x256_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_85x16_1r1w.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lef/fakeram_192x16_1r1w.lef + + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_32x1024_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_128x64_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_193x16_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_512x64_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_21x256_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_128x256_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_85x16_1r1w.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sram/lib/fakeram_192x16_1r1w.lib + +export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export CORE_UTILIZATION = 50 + +export MACRO_PLACE_HALO = 5 5 + +export PLACE_DENSITY_LB_ADDON = 0.46 + +export TNS_END_PERCENT = 100 + +export IO_CONSTRAINTS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/vortex/io.tcl + +# FOOTPRINT_TCL causes io_placement.tcl to skip place_pins (which would +# reorder our manually-placed pins). Pins are placed by IO_CONSTRAINTS +# during the floorplan step using place_pin (singular). +export FOOTPRINT_TCL = $(BENCH_DESIGN_HOME)/$(PLATFORM)/vortex/io.tcl \ No newline at end of file diff --git a/designs/asap7/vortex/constraint.sdc b/designs/asap7/vortex/constraint.sdc new file mode 100644 index 0000000..3de52c0 --- /dev/null +++ b/designs/asap7/vortex/constraint.sdc @@ -0,0 +1,34 @@ +current_design Vortex + +set clk_name clk +set clk_port_name clk +set clk_period 1100 +set clk_io_pct 0.1 + +set clk_port [get_ports $clk_name] + +create_clock -name $clk_name -period $clk_period $clk_port + +set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] + +set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs +set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] + +set_false_path -from [get_ports reset] +set_false_path -from [get_ports dcr_wr_valid] +set_false_path -from [get_ports dcr_wr_addr] +set_false_path -from [get_ports dcr_wr_data] + +# ── Fanout limiting ──────────────────────────────────────────────────────── +# DESIGN-WIDE max fanout. Without this, only clk/reset were constrained +# and synthesis was free to leave internal nets with 400+ sinks unbuffered. +# This forces synthesis (ABC) and repair_design to insert buffer trees on +# high-fanout decoded signals in the commit arbiter, cache banks, etc. +set_max_fanout 32 [current_design] + +set non_clock_inputs [all_inputs -no_clocks] +set_input_delay 10 -clock $clk_name $non_clock_inputs +set_output_delay 10 -clock $clk_name [all_outputs] + +set_driving_cell -lib_cell DFFHQNx2_ASAP7_75t_R -pin QN $non_clock_inputs +set_load [expr 4.0 * 0.683716] [all_outputs] \ No newline at end of file diff --git a/designs/asap7/vortex/io.tcl b/designs/asap7/vortex/io.tcl new file mode 100644 index 0000000..ffefaee --- /dev/null +++ b/designs/asap7/vortex/io.tcl @@ -0,0 +1,179 @@ +# io.tcl — Explicit pin placement for Vortex on ASAP7 +# +# Uses place_pin (not set_io_pin_constraint) for deterministic placement. +# Pins are evenly distributed and snapped to metal tracks. +# +# Edge assignment based on data flow: +# Right : mem_req_* (output request bus to external memory) +# Left : mem_rsp_* (input response bus from external memory) +# Top : clk, reset +# Bottom: dcr_*, busy (low-bandwidth config/status) + +# ── Die dimensions ── +lassign [ord::get_die_area] die_lx die_ly die_ux die_uy +puts "INFO(io.tcl): Die area: ($die_lx, $die_ly) to ($die_ux, $die_uy)" + +# ── ASAP7 track parameters (from make_tracks.tcl) ── +# M4 (horizontal): pins on left/right edges, spaced along y +# M5 (vertical): pins on top/bottom edges, spaced along x +set m4_y_offset 0.012 +set m4_y_pitch 0.048 +set m5_x_offset 0.012 +set m5_x_pitch 0.048 + +# ── Helper: collect and sort port names matching a glob ── +proc get_port_list {pattern} { + set pins {} + foreach p [get_ports -quiet $pattern] { + lappend pins [get_property $p name] + } + return [lsort $pins] +} + +# ── Snap to nearest track ── +proc snap_track {val offset pitch} { + set n [expr {round(($val - $offset) / $pitch)}] + return [expr {$offset + $n * $pitch}] +} + +# ── Place pins evenly along an edge with track snapping ── +proc place_edge {edge layer pins} { + upvar die_lx lx die_ly ly die_ux ux die_uy uy + upvar m4_y_offset m4yo m4_y_pitch m4yp + upvar m5_x_offset m5xo m5_x_pitch m5xp + + set n [llength $pins] + if {$n == 0} return + + switch $edge { + left { + set margin 2.0 + set lo [expr {$ly + $margin}] + set hi [expr {$uy - $margin}] + for {set i 0} {$i < $n} {incr i} { + set frac [expr {($i + 0.5) / double($n)}] + set raw_y [expr {$lo + $frac * ($hi - $lo)}] + set y [snap_track $raw_y $m4yo $m4yp] + place_pin -pin_name [lindex $pins $i] -layer $layer \ + -location [list $lx $y] -force_to_die_boundary + } + } + right { + set margin 2.0 + set lo [expr {$ly + $margin}] + set hi [expr {$uy - $margin}] + for {set i 0} {$i < $n} {incr i} { + set frac [expr {($i + 0.5) / double($n)}] + set raw_y [expr {$lo + $frac * ($hi - $lo)}] + set y [snap_track $raw_y $m4yo $m4yp] + place_pin -pin_name [lindex $pins $i] -layer $layer \ + -location [list $ux $y] -force_to_die_boundary + } + } + top { + set margin 2.0 + set lo [expr {$lx + $margin}] + set hi [expr {$ux - $margin}] + for {set i 0} {$i < $n} {incr i} { + set frac [expr {($i + 0.5) / double($n)}] + set raw_x [expr {$lo + $frac * ($hi - $lo)}] + set x [snap_track $raw_x $m5xo $m5xp] + place_pin -pin_name [lindex $pins $i] -layer $layer \ + -location [list $x $uy] -force_to_die_boundary + } + } + bottom { + set margin 2.0 + set lo [expr {$lx + $margin}] + set hi [expr {$ux - $margin}] + for {set i 0} {$i < $n} {incr i} { + set frac [expr {($i + 0.5) / double($n)}] + set raw_x [expr {$lo + $frac * ($hi - $lo)}] + set x [snap_track $raw_x $m5xo $m5xp] + place_pin -pin_name [lindex $pins $i] -layer $layer \ + -location [list $x $ly] -force_to_die_boundary + } + } + } +} + +# ══════════════════════════════════════════════════════════════════════════ +# Assemble pin lists per edge +# ══════════════════════════════════════════════════════════════════════════ + +# ── RIGHT edge: memory request bus (outputs + ready input) ── +# Group by signal type so related bits are physically adjacent +set right_pins [concat \ + [get_port_list "mem_req_valid*"] \ + [get_port_list "mem_req_rw*"] \ + [get_port_list "mem_req_ready*"] \ + [get_port_list "mem_req_addr*"] \ + [get_port_list "mem_req_byteen*"] \ + [get_port_list "mem_req_data*"] \ + [get_port_list "mem_req_tag*"] \ +] + +# ── LEFT edge: memory response bus (inputs + ready output) ── +set left_pins [concat \ + [get_port_list "mem_rsp_valid*"] \ + [get_port_list "mem_rsp_ready*"] \ + [get_port_list "mem_rsp_data*"] \ + [get_port_list "mem_rsp_tag*"] \ +] + +# ── TOP edge: clock and reset ── +set top_pins {clk reset} + +# ── BOTTOM edge: DCR config + busy status ── +set bottom_pins [concat \ + [get_port_list "dcr_wr_valid*"] \ + [get_port_list "dcr_wr_addr*"] \ + [get_port_list "dcr_wr_data*"] \ + [get_port_list "busy*"] \ +] + +# ══════════════════════════════════════════════════════════════════════════ +# Verify all signal pins are accounted for (exclude VDD/VSS) +# ══════════════════════════════════════════════════════════════════════════ +set all_placed [concat $left_pins $right_pins $top_pins $bottom_pins] +set all_ports [get_port_list "*"] + +set signal_ports {} +foreach p $all_ports { + if {$p ne "VDD" && $p ne "VSS"} { + lappend signal_ports $p + } +} + +set placed_count [llength $all_placed] +set total_count [llength $signal_ports] + +if {$placed_count != $total_count} { + puts "WARNING(io.tcl): $placed_count pins assigned but $total_count signal ports exist!" + set placed_set [lsort -unique $all_placed] + foreach p $signal_ports { + if {[lsearch -exact $placed_set $p] < 0} { + puts " UNASSIGNED: $p" + } + } +} else { + puts "INFO(io.tcl): All $total_count signal pins assigned to edges." +} + +# ══════════════════════════════════════════════════════════════════════════ +# Place all pins +# ══════════════════════════════════════════════════════════════════════════ +puts "INFO(io.tcl): Placing [llength $left_pins] pins on LEFT edge (M4)" +place_edge left M4 $left_pins + +puts "INFO(io.tcl): Placing [llength $right_pins] pins on RIGHT edge (M4)" +place_edge right M4 $right_pins + +puts "INFO(io.tcl): Placing [llength $top_pins] pins on TOP edge (M5)" +place_edge top M5 $top_pins + +puts "INFO(io.tcl): Placing [llength $bottom_pins] pins on BOTTOM edge (M5)" +place_edge bottom M5 $bottom_pins + +set total_placed [expr {[llength $left_pins] + [llength $right_pins] + [llength $top_pins] + [llength $bottom_pins]}] +puts "INFO(io.tcl): Total pins placed: $total_placed" \ No newline at end of file diff --git a/designs/asap7/vortex/sram/lef/fakeram_128x256_1rw.lef b/designs/asap7/vortex/sram/lef/fakeram_128x256_1rw.lef new file mode 100644 index 0000000..06305e6 --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_128x256_1rw.lef @@ -0,0 +1,3683 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_128x256_1rw + FOREIGN fakeram_128x256_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 26.003 BY 36.116 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 0.276 26.003 0.300 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 0.756 26.003 0.780 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 1.236 26.003 1.260 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 1.716 26.003 1.740 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 2.196 26.003 2.220 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 2.676 26.003 2.700 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 3.156 26.003 3.180 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 3.636 26.003 3.660 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 4.116 26.003 4.140 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 4.596 26.003 4.620 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 5.076 26.003 5.100 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 5.556 26.003 5.580 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 6.036 26.003 6.060 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 6.516 26.003 6.540 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 6.996 26.003 7.020 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 7.476 26.003 7.500 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 7.956 26.003 7.980 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 8.436 26.003 8.460 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 8.916 26.003 8.940 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 9.396 26.003 9.420 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 9.876 26.003 9.900 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 10.356 26.003 10.380 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 10.836 26.003 10.860 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 11.316 26.003 11.340 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 11.796 26.003 11.820 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 12.276 26.003 12.300 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 12.756 26.003 12.780 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 13.236 26.003 13.260 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 13.716 26.003 13.740 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 14.196 26.003 14.220 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 14.676 26.003 14.700 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 15.156 26.003 15.180 ; + END + END rw0_wmask_in[63] + PIN rw0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 36.062 0.225 36.116 ; + END + END rw0_wmask_in[64] + PIN rw0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 36.062 0.405 36.116 ; + END + END rw0_wmask_in[65] + PIN rw0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 36.062 0.585 36.116 ; + END + END rw0_wmask_in[66] + PIN rw0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 36.062 0.765 36.116 ; + END + END rw0_wmask_in[67] + PIN rw0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 36.062 0.945 36.116 ; + END + END rw0_wmask_in[68] + PIN rw0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 36.062 1.125 36.116 ; + END + END rw0_wmask_in[69] + PIN rw0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 36.062 1.305 36.116 ; + END + END rw0_wmask_in[70] + PIN rw0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 36.062 1.485 36.116 ; + END + END rw0_wmask_in[71] + PIN rw0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 36.062 1.665 36.116 ; + END + END rw0_wmask_in[72] + PIN rw0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 36.062 1.845 36.116 ; + END + END rw0_wmask_in[73] + PIN rw0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 36.062 2.025 36.116 ; + END + END rw0_wmask_in[74] + PIN rw0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 36.062 2.205 36.116 ; + END + END rw0_wmask_in[75] + PIN rw0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 36.062 2.385 36.116 ; + END + END rw0_wmask_in[76] + PIN rw0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 36.062 2.565 36.116 ; + END + END rw0_wmask_in[77] + PIN rw0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 36.062 2.745 36.116 ; + END + END rw0_wmask_in[78] + PIN rw0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 36.062 2.925 36.116 ; + END + END rw0_wmask_in[79] + PIN rw0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 36.062 3.105 36.116 ; + END + END rw0_wmask_in[80] + PIN rw0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 36.062 3.285 36.116 ; + END + END rw0_wmask_in[81] + PIN rw0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 36.062 3.465 36.116 ; + END + END rw0_wmask_in[82] + PIN rw0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 36.062 3.645 36.116 ; + END + END rw0_wmask_in[83] + PIN rw0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 36.062 3.825 36.116 ; + END + END rw0_wmask_in[84] + PIN rw0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 36.062 4.005 36.116 ; + END + END rw0_wmask_in[85] + PIN rw0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 36.062 4.185 36.116 ; + END + END rw0_wmask_in[86] + PIN rw0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 36.062 4.365 36.116 ; + END + END rw0_wmask_in[87] + PIN rw0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 36.062 4.545 36.116 ; + END + END rw0_wmask_in[88] + PIN rw0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 36.062 4.725 36.116 ; + END + END rw0_wmask_in[89] + PIN rw0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 36.062 4.905 36.116 ; + END + END rw0_wmask_in[90] + PIN rw0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 36.062 5.085 36.116 ; + END + END rw0_wmask_in[91] + PIN rw0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 36.062 5.265 36.116 ; + END + END rw0_wmask_in[92] + PIN rw0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 36.062 5.445 36.116 ; + END + END rw0_wmask_in[93] + PIN rw0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 36.062 5.625 36.116 ; + END + END rw0_wmask_in[94] + PIN rw0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 36.062 5.805 36.116 ; + END + END rw0_wmask_in[95] + PIN rw0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 36.062 5.985 36.116 ; + END + END rw0_wmask_in[96] + PIN rw0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 36.062 6.165 36.116 ; + END + END rw0_wmask_in[97] + PIN rw0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 36.062 6.345 36.116 ; + END + END rw0_wmask_in[98] + PIN rw0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 36.062 6.525 36.116 ; + END + END rw0_wmask_in[99] + PIN rw0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 36.062 6.705 36.116 ; + END + END rw0_wmask_in[100] + PIN rw0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 36.062 6.885 36.116 ; + END + END rw0_wmask_in[101] + PIN rw0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 36.062 7.065 36.116 ; + END + END rw0_wmask_in[102] + PIN rw0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 36.062 7.245 36.116 ; + END + END rw0_wmask_in[103] + PIN rw0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 36.062 7.425 36.116 ; + END + END rw0_wmask_in[104] + PIN rw0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 36.062 7.605 36.116 ; + END + END rw0_wmask_in[105] + PIN rw0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 36.062 7.785 36.116 ; + END + END rw0_wmask_in[106] + PIN rw0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 36.062 7.965 36.116 ; + END + END rw0_wmask_in[107] + PIN rw0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 36.062 8.145 36.116 ; + END + END rw0_wmask_in[108] + PIN rw0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 36.062 8.325 36.116 ; + END + END rw0_wmask_in[109] + PIN rw0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 36.062 8.505 36.116 ; + END + END rw0_wmask_in[110] + PIN rw0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 36.062 8.685 36.116 ; + END + END rw0_wmask_in[111] + PIN rw0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 36.062 8.865 36.116 ; + END + END rw0_wmask_in[112] + PIN rw0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 36.062 9.045 36.116 ; + END + END rw0_wmask_in[113] + PIN rw0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 36.062 9.225 36.116 ; + END + END rw0_wmask_in[114] + PIN rw0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 36.062 9.405 36.116 ; + END + END rw0_wmask_in[115] + PIN rw0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 36.062 9.585 36.116 ; + END + END rw0_wmask_in[116] + PIN rw0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 36.062 9.765 36.116 ; + END + END rw0_wmask_in[117] + PIN rw0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 36.062 9.945 36.116 ; + END + END rw0_wmask_in[118] + PIN rw0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 36.062 10.125 36.116 ; + END + END rw0_wmask_in[119] + PIN rw0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 36.062 10.305 36.116 ; + END + END rw0_wmask_in[120] + PIN rw0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 36.062 10.485 36.116 ; + END + END rw0_wmask_in[121] + PIN rw0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 36.062 10.665 36.116 ; + END + END rw0_wmask_in[122] + PIN rw0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 36.062 10.845 36.116 ; + END + END rw0_wmask_in[123] + PIN rw0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 36.062 11.025 36.116 ; + END + END rw0_wmask_in[124] + PIN rw0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 36.062 11.205 36.116 ; + END + END rw0_wmask_in[125] + PIN rw0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 36.062 11.385 36.116 ; + END + END rw0_wmask_in[126] + PIN rw0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 36.062 11.565 36.116 ; + END + END rw0_wmask_in[127] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.276 0.072 24.300 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.236 0.072 25.260 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.716 0.072 25.740 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.676 0.072 26.700 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.156 0.072 27.180 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.116 0.072 28.140 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.596 0.072 28.620 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.556 0.072 29.580 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.036 0.072 30.060 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 15.636 26.003 15.660 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 16.116 26.003 16.140 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 16.596 26.003 16.620 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 17.076 26.003 17.100 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 17.556 26.003 17.580 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 18.036 26.003 18.060 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 18.516 26.003 18.540 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 18.996 26.003 19.020 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 19.476 26.003 19.500 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 19.956 26.003 19.980 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 20.436 26.003 20.460 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 20.916 26.003 20.940 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 21.396 26.003 21.420 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 21.876 26.003 21.900 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 22.356 26.003 22.380 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 22.836 26.003 22.860 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 23.316 26.003 23.340 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 23.796 26.003 23.820 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 24.276 26.003 24.300 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 24.756 26.003 24.780 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 25.236 26.003 25.260 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 25.716 26.003 25.740 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 26.196 26.003 26.220 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 26.676 26.003 26.700 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 27.156 26.003 27.180 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 27.636 26.003 27.660 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 28.116 26.003 28.140 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 28.596 26.003 28.620 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 29.076 26.003 29.100 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 29.556 26.003 29.580 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 30.036 26.003 30.060 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 30.516 26.003 30.540 ; + END + END rw0_wd_in[63] + PIN rw0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END rw0_wd_in[64] + PIN rw0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 0.000 0.405 0.054 ; + END + END rw0_wd_in[65] + PIN rw0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 0.000 0.585 0.054 ; + END + END rw0_wd_in[66] + PIN rw0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END rw0_wd_in[67] + PIN rw0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 0.000 0.945 0.054 ; + END + END rw0_wd_in[68] + PIN rw0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END rw0_wd_in[69] + PIN rw0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END rw0_wd_in[70] + PIN rw0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 0.000 1.485 0.054 ; + END + END rw0_wd_in[71] + PIN rw0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END rw0_wd_in[72] + PIN rw0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END rw0_wd_in[73] + PIN rw0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END rw0_wd_in[74] + PIN rw0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 0.000 2.205 0.054 ; + END + END rw0_wd_in[75] + PIN rw0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END rw0_wd_in[76] + PIN rw0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 0.000 2.565 0.054 ; + END + END rw0_wd_in[77] + PIN rw0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END rw0_wd_in[78] + PIN rw0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END rw0_wd_in[79] + PIN rw0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END rw0_wd_in[80] + PIN rw0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 0.000 3.285 0.054 ; + END + END rw0_wd_in[81] + PIN rw0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END rw0_wd_in[82] + PIN rw0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 0.000 3.645 0.054 ; + END + END rw0_wd_in[83] + PIN rw0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END rw0_wd_in[84] + PIN rw0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END rw0_wd_in[85] + PIN rw0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 0.000 4.185 0.054 ; + END + END rw0_wd_in[86] + PIN rw0_wd_in[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 0.000 4.365 0.054 ; + END + END rw0_wd_in[87] + PIN rw0_wd_in[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END rw0_wd_in[88] + PIN rw0_wd_in[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END rw0_wd_in[89] + PIN rw0_wd_in[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 0.000 4.905 0.054 ; + END + END rw0_wd_in[90] + PIN rw0_wd_in[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END rw0_wd_in[91] + PIN rw0_wd_in[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END rw0_wd_in[92] + PIN rw0_wd_in[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 0.000 5.445 0.054 ; + END + END rw0_wd_in[93] + PIN rw0_wd_in[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END rw0_wd_in[94] + PIN rw0_wd_in[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END rw0_wd_in[95] + PIN rw0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END rw0_wd_in[96] + PIN rw0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END rw0_wd_in[97] + PIN rw0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 0.000 6.345 0.054 ; + END + END rw0_wd_in[98] + PIN rw0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END rw0_wd_in[99] + PIN rw0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END rw0_wd_in[100] + PIN rw0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 0.000 6.885 0.054 ; + END + END rw0_wd_in[101] + PIN rw0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 0.000 7.065 0.054 ; + END + END rw0_wd_in[102] + PIN rw0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END rw0_wd_in[103] + PIN rw0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END rw0_wd_in[104] + PIN rw0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 0.000 7.605 0.054 ; + END + END rw0_wd_in[105] + PIN rw0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END rw0_wd_in[106] + PIN rw0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 0.000 7.965 0.054 ; + END + END rw0_wd_in[107] + PIN rw0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 0.000 8.145 0.054 ; + END + END rw0_wd_in[108] + PIN rw0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END rw0_wd_in[109] + PIN rw0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 0.000 8.505 0.054 ; + END + END rw0_wd_in[110] + PIN rw0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 0.000 8.685 0.054 ; + END + END rw0_wd_in[111] + PIN rw0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END rw0_wd_in[112] + PIN rw0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 0.000 9.045 0.054 ; + END + END rw0_wd_in[113] + PIN rw0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 0.000 9.225 0.054 ; + END + END rw0_wd_in[114] + PIN rw0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 0.000 9.405 0.054 ; + END + END rw0_wd_in[115] + PIN rw0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 0.000 9.585 0.054 ; + END + END rw0_wd_in[116] + PIN rw0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 0.000 9.765 0.054 ; + END + END rw0_wd_in[117] + PIN rw0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 0.000 9.945 0.054 ; + END + END rw0_wd_in[118] + PIN rw0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 0.000 10.125 0.054 ; + END + END rw0_wd_in[119] + PIN rw0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END rw0_wd_in[120] + PIN rw0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 0.000 10.485 0.054 ; + END + END rw0_wd_in[121] + PIN rw0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 0.000 10.665 0.054 ; + END + END rw0_wd_in[122] + PIN rw0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 0.000 10.845 0.054 ; + END + END rw0_wd_in[123] + PIN rw0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 0.000 11.025 0.054 ; + END + END rw0_wd_in[124] + PIN rw0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 0.000 11.205 0.054 ; + END + END rw0_wd_in[125] + PIN rw0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 0.000 11.385 0.054 ; + END + END rw0_wd_in[126] + PIN rw0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 0.000 11.565 0.054 ; + END + END rw0_wd_in[127] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 0.000 11.925 0.054 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 0.000 12.105 0.054 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 0.000 12.285 0.054 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 0.000 12.465 0.054 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 0.000 12.645 0.054 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 0.000 12.825 0.054 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 0.000 13.005 0.054 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 0.000 13.365 0.054 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 0.000 13.545 0.054 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 0.000 13.725 0.054 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 0.000 13.905 0.054 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 0.000 14.085 0.054 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 0.000 14.265 0.054 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 0.000 14.445 0.054 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 0.000 14.805 0.054 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 0.000 14.985 0.054 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 0.000 15.165 0.054 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 0.000 15.345 0.054 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 0.000 15.525 0.054 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 0.000 15.705 0.054 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 0.000 15.885 0.054 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 0.000 16.245 0.054 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 0.000 16.425 0.054 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 0.000 16.605 0.054 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 0.000 16.785 0.054 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 0.000 16.965 0.054 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 0.000 17.145 0.054 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 0.000 17.325 0.054 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 0.000 17.685 0.054 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 0.000 17.865 0.054 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 0.000 18.045 0.054 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 0.000 18.225 0.054 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 0.000 18.405 0.054 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 0.000 18.585 0.054 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 0.000 18.765 0.054 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 0.000 19.125 0.054 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 0.000 19.305 0.054 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 0.000 19.485 0.054 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 0.000 19.665 0.054 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 0.000 19.845 0.054 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 0.000 20.025 0.054 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 0.000 20.205 0.054 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 0.000 20.565 0.054 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 0.000 20.745 0.054 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 0.000 20.925 0.054 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 0.000 21.105 0.054 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 0.000 21.285 0.054 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 0.000 21.465 0.054 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 0.000 21.645 0.054 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 0.000 22.005 0.054 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 0.000 22.185 0.054 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 0.000 22.365 0.054 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 0.000 22.545 0.054 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 0.000 22.725 0.054 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 0.000 22.905 0.054 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 0.000 23.085 0.054 ; + END + END rw0_rd_out[63] + PIN rw0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 36.062 11.745 36.116 ; + END + END rw0_rd_out[64] + PIN rw0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 36.062 11.925 36.116 ; + END + END rw0_rd_out[65] + PIN rw0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 36.062 12.105 36.116 ; + END + END rw0_rd_out[66] + PIN rw0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 36.062 12.285 36.116 ; + END + END rw0_rd_out[67] + PIN rw0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 36.062 12.465 36.116 ; + END + END rw0_rd_out[68] + PIN rw0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 36.062 12.645 36.116 ; + END + END rw0_rd_out[69] + PIN rw0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 36.062 12.825 36.116 ; + END + END rw0_rd_out[70] + PIN rw0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 36.062 13.005 36.116 ; + END + END rw0_rd_out[71] + PIN rw0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 36.062 13.185 36.116 ; + END + END rw0_rd_out[72] + PIN rw0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 36.062 13.365 36.116 ; + END + END rw0_rd_out[73] + PIN rw0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 36.062 13.545 36.116 ; + END + END rw0_rd_out[74] + PIN rw0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 36.062 13.725 36.116 ; + END + END rw0_rd_out[75] + PIN rw0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 36.062 13.905 36.116 ; + END + END rw0_rd_out[76] + PIN rw0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 36.062 14.085 36.116 ; + END + END rw0_rd_out[77] + PIN rw0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 36.062 14.265 36.116 ; + END + END rw0_rd_out[78] + PIN rw0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 36.062 14.445 36.116 ; + END + END rw0_rd_out[79] + PIN rw0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 36.062 14.625 36.116 ; + END + END rw0_rd_out[80] + PIN rw0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 36.062 14.805 36.116 ; + END + END rw0_rd_out[81] + PIN rw0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 36.062 14.985 36.116 ; + END + END rw0_rd_out[82] + PIN rw0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 36.062 15.165 36.116 ; + END + END rw0_rd_out[83] + PIN rw0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 36.062 15.345 36.116 ; + END + END rw0_rd_out[84] + PIN rw0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 36.062 15.525 36.116 ; + END + END rw0_rd_out[85] + PIN rw0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 36.062 15.705 36.116 ; + END + END rw0_rd_out[86] + PIN rw0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 36.062 15.885 36.116 ; + END + END rw0_rd_out[87] + PIN rw0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 36.062 16.065 36.116 ; + END + END rw0_rd_out[88] + PIN rw0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 36.062 16.245 36.116 ; + END + END rw0_rd_out[89] + PIN rw0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 36.062 16.425 36.116 ; + END + END rw0_rd_out[90] + PIN rw0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 36.062 16.605 36.116 ; + END + END rw0_rd_out[91] + PIN rw0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 36.062 16.785 36.116 ; + END + END rw0_rd_out[92] + PIN rw0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 36.062 16.965 36.116 ; + END + END rw0_rd_out[93] + PIN rw0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 36.062 17.145 36.116 ; + END + END rw0_rd_out[94] + PIN rw0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 36.062 17.325 36.116 ; + END + END rw0_rd_out[95] + PIN rw0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 36.062 17.505 36.116 ; + END + END rw0_rd_out[96] + PIN rw0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 36.062 17.685 36.116 ; + END + END rw0_rd_out[97] + PIN rw0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 36.062 17.865 36.116 ; + END + END rw0_rd_out[98] + PIN rw0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 36.062 18.045 36.116 ; + END + END rw0_rd_out[99] + PIN rw0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 36.062 18.225 36.116 ; + END + END rw0_rd_out[100] + PIN rw0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 36.062 18.405 36.116 ; + END + END rw0_rd_out[101] + PIN rw0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 36.062 18.585 36.116 ; + END + END rw0_rd_out[102] + PIN rw0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 36.062 18.765 36.116 ; + END + END rw0_rd_out[103] + PIN rw0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 36.062 18.945 36.116 ; + END + END rw0_rd_out[104] + PIN rw0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 36.062 19.125 36.116 ; + END + END rw0_rd_out[105] + PIN rw0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 36.062 19.305 36.116 ; + END + END rw0_rd_out[106] + PIN rw0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 36.062 19.485 36.116 ; + END + END rw0_rd_out[107] + PIN rw0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 36.062 19.665 36.116 ; + END + END rw0_rd_out[108] + PIN rw0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 36.062 19.845 36.116 ; + END + END rw0_rd_out[109] + PIN rw0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 36.062 20.025 36.116 ; + END + END rw0_rd_out[110] + PIN rw0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 36.062 20.205 36.116 ; + END + END rw0_rd_out[111] + PIN rw0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 36.062 20.385 36.116 ; + END + END rw0_rd_out[112] + PIN rw0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 36.062 20.565 36.116 ; + END + END rw0_rd_out[113] + PIN rw0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 36.062 20.745 36.116 ; + END + END rw0_rd_out[114] + PIN rw0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 36.062 20.925 36.116 ; + END + END rw0_rd_out[115] + PIN rw0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 36.062 21.105 36.116 ; + END + END rw0_rd_out[116] + PIN rw0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 36.062 21.285 36.116 ; + END + END rw0_rd_out[117] + PIN rw0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 36.062 21.465 36.116 ; + END + END rw0_rd_out[118] + PIN rw0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 36.062 21.645 36.116 ; + END + END rw0_rd_out[119] + PIN rw0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 36.062 21.825 36.116 ; + END + END rw0_rd_out[120] + PIN rw0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 36.062 22.005 36.116 ; + END + END rw0_rd_out[121] + PIN rw0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 36.062 22.185 36.116 ; + END + END rw0_rd_out[122] + PIN rw0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 36.062 22.365 36.116 ; + END + END rw0_rd_out[123] + PIN rw0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 36.062 22.545 36.116 ; + END + END rw0_rd_out[124] + PIN rw0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 36.062 22.725 36.116 ; + END + END rw0_rd_out[125] + PIN rw0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 36.062 22.905 36.116 ; + END + END rw0_rd_out[126] + PIN rw0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 36.062 23.085 36.116 ; + END + END rw0_rd_out[127] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.996 0.072 31.020 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.476 0.072 31.500 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.436 0.072 32.460 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 30.996 26.003 31.020 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 31.476 26.003 31.500 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 31.956 26.003 31.980 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 25.931 32.436 26.003 32.460 ; + END + END rw0_addr_in[7] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 36.062 23.265 36.116 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 36.062 23.445 36.116 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 36.062 23.625 36.116 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 25.787 0.336 ; + RECT 0.216 1.008 25.787 1.104 ; + RECT 0.216 1.776 25.787 1.872 ; + RECT 0.216 2.544 25.787 2.640 ; + RECT 0.216 3.312 25.787 3.408 ; + RECT 0.216 4.080 25.787 4.176 ; + RECT 0.216 4.848 25.787 4.944 ; + RECT 0.216 5.616 25.787 5.712 ; + RECT 0.216 6.384 25.787 6.480 ; + RECT 0.216 7.152 25.787 7.248 ; + RECT 0.216 7.920 25.787 8.016 ; + RECT 0.216 8.688 25.787 8.784 ; + RECT 0.216 9.456 25.787 9.552 ; + RECT 0.216 10.224 25.787 10.320 ; + RECT 0.216 10.992 25.787 11.088 ; + RECT 0.216 11.760 25.787 11.856 ; + RECT 0.216 12.528 25.787 12.624 ; + RECT 0.216 13.296 25.787 13.392 ; + RECT 0.216 14.064 25.787 14.160 ; + RECT 0.216 14.832 25.787 14.928 ; + RECT 0.216 15.600 25.787 15.696 ; + RECT 0.216 16.368 25.787 16.464 ; + RECT 0.216 17.136 25.787 17.232 ; + RECT 0.216 17.904 25.787 18.000 ; + RECT 0.216 18.672 25.787 18.768 ; + RECT 0.216 19.440 25.787 19.536 ; + RECT 0.216 20.208 25.787 20.304 ; + RECT 0.216 20.976 25.787 21.072 ; + RECT 0.216 21.744 25.787 21.840 ; + RECT 0.216 22.512 25.787 22.608 ; + RECT 0.216 23.280 25.787 23.376 ; + RECT 0.216 24.048 25.787 24.144 ; + RECT 0.216 24.816 25.787 24.912 ; + RECT 0.216 25.584 25.787 25.680 ; + RECT 0.216 26.352 25.787 26.448 ; + RECT 0.216 27.120 25.787 27.216 ; + RECT 0.216 27.888 25.787 27.984 ; + RECT 0.216 28.656 25.787 28.752 ; + RECT 0.216 29.424 25.787 29.520 ; + RECT 0.216 30.192 25.787 30.288 ; + RECT 0.216 30.960 25.787 31.056 ; + RECT 0.216 31.728 25.787 31.824 ; + RECT 0.216 32.496 25.787 32.592 ; + RECT 0.216 33.264 25.787 33.360 ; + RECT 0.216 34.032 25.787 34.128 ; + RECT 0.216 34.800 25.787 34.896 ; + RECT 0.216 35.568 25.787 35.664 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 25.787 0.336 ; + RECT 0.216 1.008 25.787 1.104 ; + RECT 0.216 1.776 25.787 1.872 ; + RECT 0.216 2.544 25.787 2.640 ; + RECT 0.216 3.312 25.787 3.408 ; + RECT 0.216 4.080 25.787 4.176 ; + RECT 0.216 4.848 25.787 4.944 ; + RECT 0.216 5.616 25.787 5.712 ; + RECT 0.216 6.384 25.787 6.480 ; + RECT 0.216 7.152 25.787 7.248 ; + RECT 0.216 7.920 25.787 8.016 ; + RECT 0.216 8.688 25.787 8.784 ; + RECT 0.216 9.456 25.787 9.552 ; + RECT 0.216 10.224 25.787 10.320 ; + RECT 0.216 10.992 25.787 11.088 ; + RECT 0.216 11.760 25.787 11.856 ; + RECT 0.216 12.528 25.787 12.624 ; + RECT 0.216 13.296 25.787 13.392 ; + RECT 0.216 14.064 25.787 14.160 ; + RECT 0.216 14.832 25.787 14.928 ; + RECT 0.216 15.600 25.787 15.696 ; + RECT 0.216 16.368 25.787 16.464 ; + RECT 0.216 17.136 25.787 17.232 ; + RECT 0.216 17.904 25.787 18.000 ; + RECT 0.216 18.672 25.787 18.768 ; + RECT 0.216 19.440 25.787 19.536 ; + RECT 0.216 20.208 25.787 20.304 ; + RECT 0.216 20.976 25.787 21.072 ; + RECT 0.216 21.744 25.787 21.840 ; + RECT 0.216 22.512 25.787 22.608 ; + RECT 0.216 23.280 25.787 23.376 ; + RECT 0.216 24.048 25.787 24.144 ; + RECT 0.216 24.816 25.787 24.912 ; + RECT 0.216 25.584 25.787 25.680 ; + RECT 0.216 26.352 25.787 26.448 ; + RECT 0.216 27.120 25.787 27.216 ; + RECT 0.216 27.888 25.787 27.984 ; + RECT 0.216 28.656 25.787 28.752 ; + RECT 0.216 29.424 25.787 29.520 ; + RECT 0.216 30.192 25.787 30.288 ; + RECT 0.216 30.960 25.787 31.056 ; + RECT 0.216 31.728 25.787 31.824 ; + RECT 0.216 32.496 25.787 32.592 ; + RECT 0.216 33.264 25.787 33.360 ; + RECT 0.216 34.032 25.787 34.128 ; + RECT 0.216 34.800 25.787 34.896 ; + RECT 0.216 35.568 25.787 35.664 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 26.003 36.116 ; + LAYER M2 ; + RECT 0 0 26.003 36.116 ; + LAYER M3 ; + RECT 0 0 26.003 36.116 ; + LAYER M4 ; + RECT 0 0 26.003 36.116 ; + END +END fakeram_128x256_1rw + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_128x64_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_128x64_1r1w.lef new file mode 100644 index 0000000..f78a2ab --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_128x64_1r1w.lef @@ -0,0 +1,3703 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_128x64_1r1w + FOREIGN fakeram_128x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 40.809 BY 22.672 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 0.276 40.809 0.300 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 0.564 40.809 0.588 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 0.852 40.809 0.876 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 1.140 40.809 1.164 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 1.428 40.809 1.452 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 1.716 40.809 1.740 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 2.004 40.809 2.028 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 2.292 40.809 2.316 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 2.580 40.809 2.604 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 2.868 40.809 2.892 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 3.156 40.809 3.180 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 3.444 40.809 3.468 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 3.732 40.809 3.756 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 4.020 40.809 4.044 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 4.308 40.809 4.332 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 4.596 40.809 4.620 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 4.884 40.809 4.908 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 5.172 40.809 5.196 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 5.460 40.809 5.484 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 5.748 40.809 5.772 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 6.036 40.809 6.060 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 6.324 40.809 6.348 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 6.612 40.809 6.636 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 6.900 40.809 6.924 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 7.188 40.809 7.212 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 7.476 40.809 7.500 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 7.764 40.809 7.788 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 8.052 40.809 8.076 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 8.340 40.809 8.364 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 8.628 40.809 8.652 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 8.916 40.809 8.940 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 9.204 40.809 9.228 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 22.618 0.225 22.672 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 22.618 0.513 22.672 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 22.618 0.801 22.672 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 22.618 1.089 22.672 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 22.618 1.377 22.672 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 22.618 1.665 22.672 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 22.618 1.953 22.672 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 22.618 2.241 22.672 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 22.618 2.529 22.672 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 22.618 2.817 22.672 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 22.618 3.105 22.672 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 22.618 3.393 22.672 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 22.618 3.681 22.672 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 22.618 3.969 22.672 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 22.618 4.257 22.672 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 22.618 4.545 22.672 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 22.618 4.833 22.672 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 22.618 5.121 22.672 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 22.618 5.409 22.672 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 22.618 5.697 22.672 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 22.618 5.985 22.672 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 22.618 6.273 22.672 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 22.618 6.561 22.672 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 22.618 6.849 22.672 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 22.618 7.137 22.672 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 22.618 7.425 22.672 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 22.618 7.713 22.672 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 22.618 8.001 22.672 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 22.618 8.289 22.672 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 22.618 8.577 22.672 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 22.618 8.865 22.672 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 22.618 9.153 22.672 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 22.618 9.441 22.672 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 22.618 9.729 22.672 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 22.618 10.017 22.672 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 22.618 10.305 22.672 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 22.618 10.593 22.672 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 22.618 10.881 22.672 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 22.618 11.169 22.672 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 22.618 11.457 22.672 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 22.618 11.745 22.672 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 22.618 12.033 22.672 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 22.618 12.321 22.672 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 22.618 12.609 22.672 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 22.618 12.897 22.672 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 22.618 13.185 22.672 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 22.618 13.473 22.672 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 22.618 13.761 22.672 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 22.618 14.049 22.672 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 22.618 14.337 22.672 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 22.618 14.625 22.672 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 22.618 14.913 22.672 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 22.618 15.201 22.672 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 22.618 15.489 22.672 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 22.618 15.777 22.672 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 22.618 16.065 22.672 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 22.618 16.353 22.672 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 22.618 16.641 22.672 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 22.618 16.929 22.672 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 22.618 17.217 22.672 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 22.618 17.505 22.672 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 22.618 17.793 22.672 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 22.618 18.081 22.672 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 22.618 18.369 22.672 ; + END + END w0_wmask_in[127] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 9.492 40.809 9.516 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 9.780 40.809 9.804 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 10.068 40.809 10.092 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 10.356 40.809 10.380 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 10.644 40.809 10.668 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 10.932 40.809 10.956 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 11.220 40.809 11.244 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 11.508 40.809 11.532 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 11.796 40.809 11.820 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 12.084 40.809 12.108 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 12.372 40.809 12.396 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 12.660 40.809 12.684 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 12.948 40.809 12.972 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 13.236 40.809 13.260 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 13.524 40.809 13.548 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 13.812 40.809 13.836 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 14.100 40.809 14.124 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 14.388 40.809 14.412 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 14.676 40.809 14.700 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 14.964 40.809 14.988 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 15.252 40.809 15.276 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 15.540 40.809 15.564 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 15.828 40.809 15.852 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 16.116 40.809 16.140 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 16.404 40.809 16.428 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 16.692 40.809 16.716 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 16.980 40.809 17.004 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 17.268 40.809 17.292 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 17.556 40.809 17.580 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 17.844 40.809 17.868 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 18.132 40.809 18.156 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 18.420 40.809 18.444 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[127] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 22.618 18.657 22.672 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 22.618 18.945 22.672 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 22.618 19.233 22.672 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 22.618 19.521 22.672 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 22.618 19.809 22.672 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 22.618 20.097 22.672 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 22.618 20.385 22.672 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 22.618 20.673 22.672 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 22.618 20.961 22.672 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 22.618 21.249 22.672 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 22.618 21.537 22.672 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 22.618 21.825 22.672 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 22.618 22.113 22.672 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 22.618 22.401 22.672 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 22.618 22.689 22.672 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 22.618 22.977 22.672 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 22.618 23.265 22.672 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 22.618 23.553 22.672 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 22.618 23.841 22.672 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 22.618 24.129 22.672 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 22.618 24.417 22.672 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 22.618 24.705 22.672 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 22.618 24.993 22.672 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 22.618 25.281 22.672 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 22.618 25.569 22.672 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 22.618 25.857 22.672 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 22.618 26.145 22.672 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 22.618 26.433 22.672 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 22.618 26.721 22.672 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 22.618 27.009 22.672 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 22.618 27.297 22.672 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 22.618 27.585 22.672 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 22.618 27.873 22.672 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 22.618 28.161 22.672 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 22.618 28.449 22.672 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 22.618 28.737 22.672 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 22.618 29.025 22.672 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 22.618 29.313 22.672 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 22.618 29.601 22.672 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 22.618 29.889 22.672 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 22.618 30.177 22.672 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 22.618 30.465 22.672 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 22.618 30.753 22.672 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 22.618 31.041 22.672 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 22.618 31.329 22.672 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 22.618 31.617 22.672 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 22.618 31.905 22.672 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 22.618 32.193 22.672 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 22.618 32.481 22.672 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 22.618 32.769 22.672 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 22.618 33.057 22.672 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 22.618 33.345 22.672 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 22.618 33.633 22.672 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 22.618 33.921 22.672 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 22.618 34.209 22.672 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 22.618 34.497 22.672 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 22.618 34.785 22.672 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 22.618 35.073 22.672 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 22.618 35.361 22.672 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 22.618 35.649 22.672 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 22.618 35.937 22.672 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 22.618 36.225 22.672 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 22.618 36.513 22.672 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 22.618 36.801 22.672 ; + END + END r0_rd_out[127] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 18.708 40.809 18.732 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 18.996 40.809 19.020 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 19.284 40.809 19.308 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 19.572 40.809 19.596 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 19.860 40.809 19.884 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 40.737 20.148 40.809 20.172 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 22.618 37.089 22.672 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 22.618 37.377 22.672 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 22.618 37.665 22.672 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 22.618 37.953 22.672 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 22.618 38.241 22.672 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 40.593 0.336 ; + RECT 0.216 1.008 40.593 1.104 ; + RECT 0.216 1.776 40.593 1.872 ; + RECT 0.216 2.544 40.593 2.640 ; + RECT 0.216 3.312 40.593 3.408 ; + RECT 0.216 4.080 40.593 4.176 ; + RECT 0.216 4.848 40.593 4.944 ; + RECT 0.216 5.616 40.593 5.712 ; + RECT 0.216 6.384 40.593 6.480 ; + RECT 0.216 7.152 40.593 7.248 ; + RECT 0.216 7.920 40.593 8.016 ; + RECT 0.216 8.688 40.593 8.784 ; + RECT 0.216 9.456 40.593 9.552 ; + RECT 0.216 10.224 40.593 10.320 ; + RECT 0.216 10.992 40.593 11.088 ; + RECT 0.216 11.760 40.593 11.856 ; + RECT 0.216 12.528 40.593 12.624 ; + RECT 0.216 13.296 40.593 13.392 ; + RECT 0.216 14.064 40.593 14.160 ; + RECT 0.216 14.832 40.593 14.928 ; + RECT 0.216 15.600 40.593 15.696 ; + RECT 0.216 16.368 40.593 16.464 ; + RECT 0.216 17.136 40.593 17.232 ; + RECT 0.216 17.904 40.593 18.000 ; + RECT 0.216 18.672 40.593 18.768 ; + RECT 0.216 19.440 40.593 19.536 ; + RECT 0.216 20.208 40.593 20.304 ; + RECT 0.216 20.976 40.593 21.072 ; + RECT 0.216 21.744 40.593 21.840 ; + RECT 0.216 22.512 40.593 22.608 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 40.593 0.336 ; + RECT 0.216 1.008 40.593 1.104 ; + RECT 0.216 1.776 40.593 1.872 ; + RECT 0.216 2.544 40.593 2.640 ; + RECT 0.216 3.312 40.593 3.408 ; + RECT 0.216 4.080 40.593 4.176 ; + RECT 0.216 4.848 40.593 4.944 ; + RECT 0.216 5.616 40.593 5.712 ; + RECT 0.216 6.384 40.593 6.480 ; + RECT 0.216 7.152 40.593 7.248 ; + RECT 0.216 7.920 40.593 8.016 ; + RECT 0.216 8.688 40.593 8.784 ; + RECT 0.216 9.456 40.593 9.552 ; + RECT 0.216 10.224 40.593 10.320 ; + RECT 0.216 10.992 40.593 11.088 ; + RECT 0.216 11.760 40.593 11.856 ; + RECT 0.216 12.528 40.593 12.624 ; + RECT 0.216 13.296 40.593 13.392 ; + RECT 0.216 14.064 40.593 14.160 ; + RECT 0.216 14.832 40.593 14.928 ; + RECT 0.216 15.600 40.593 15.696 ; + RECT 0.216 16.368 40.593 16.464 ; + RECT 0.216 17.136 40.593 17.232 ; + RECT 0.216 17.904 40.593 18.000 ; + RECT 0.216 18.672 40.593 18.768 ; + RECT 0.216 19.440 40.593 19.536 ; + RECT 0.216 20.208 40.593 20.304 ; + RECT 0.216 20.976 40.593 21.072 ; + RECT 0.216 21.744 40.593 21.840 ; + RECT 0.216 22.512 40.593 22.608 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 40.809 22.672 ; + LAYER M2 ; + RECT 0 0 40.809 22.672 ; + LAYER M3 ; + RECT 0 0 40.809 22.672 ; + LAYER M4 ; + RECT 0 0 40.809 22.672 ; + END +END fakeram_128x64_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_192x16_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_192x16_1r1w.lef new file mode 100644 index 0000000..d11932d --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_192x16_1r1w.lef @@ -0,0 +1,5387 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_192x16_1r1w + FOREIGN fakeram_192x16_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 61.213 BY 19.838 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.468 0.072 0.492 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.540 0.072 3.564 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.844 0.072 5.868 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.228 0.072 6.252 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.380 0.072 7.404 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.148 0.072 8.172 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.532 0.072 8.556 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.300 0.072 9.324 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 0.276 61.213 0.300 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 0.468 61.213 0.492 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 0.660 61.213 0.684 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 0.852 61.213 0.876 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 1.044 61.213 1.068 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 1.236 61.213 1.260 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 1.428 61.213 1.452 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 1.620 61.213 1.644 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 1.812 61.213 1.836 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 2.004 61.213 2.028 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 2.196 61.213 2.220 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 2.388 61.213 2.412 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 2.580 61.213 2.604 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 2.772 61.213 2.796 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 2.964 61.213 2.988 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 3.156 61.213 3.180 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 3.348 61.213 3.372 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 3.540 61.213 3.564 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 3.732 61.213 3.756 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 3.924 61.213 3.948 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 4.116 61.213 4.140 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 4.308 61.213 4.332 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 4.500 61.213 4.524 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 4.692 61.213 4.716 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 4.884 61.213 4.908 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 5.076 61.213 5.100 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 5.268 61.213 5.292 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 5.460 61.213 5.484 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 5.652 61.213 5.676 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 5.844 61.213 5.868 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 6.036 61.213 6.060 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 6.228 61.213 6.252 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 6.420 61.213 6.444 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 6.612 61.213 6.636 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 6.804 61.213 6.828 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 6.996 61.213 7.020 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 7.188 61.213 7.212 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 7.380 61.213 7.404 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 7.572 61.213 7.596 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 7.764 61.213 7.788 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 7.956 61.213 7.980 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 8.148 61.213 8.172 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 8.340 61.213 8.364 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 8.532 61.213 8.556 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 8.724 61.213 8.748 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 8.916 61.213 8.940 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 9.108 61.213 9.132 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 9.300 61.213 9.324 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 19.784 0.225 19.838 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 19.784 0.513 19.838 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 19.784 0.801 19.838 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 19.784 1.089 19.838 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 19.784 1.377 19.838 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 19.784 1.665 19.838 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 19.784 1.953 19.838 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 19.784 2.241 19.838 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 19.784 2.529 19.838 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 19.784 2.817 19.838 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 19.784 3.105 19.838 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 19.784 3.393 19.838 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 19.784 3.681 19.838 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 19.784 3.969 19.838 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 19.784 4.257 19.838 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 19.784 4.545 19.838 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 19.784 4.833 19.838 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 19.784 5.121 19.838 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 19.784 5.409 19.838 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 19.784 5.697 19.838 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 19.784 5.985 19.838 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 19.784 6.273 19.838 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 19.784 6.561 19.838 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 19.784 6.849 19.838 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 19.784 7.137 19.838 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 19.784 7.425 19.838 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 19.784 7.713 19.838 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 19.784 8.001 19.838 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 19.784 8.289 19.838 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 19.784 8.577 19.838 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 19.784 8.865 19.838 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 19.784 9.153 19.838 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 19.784 9.441 19.838 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 19.784 9.729 19.838 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 19.784 10.017 19.838 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 19.784 10.305 19.838 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 19.784 10.593 19.838 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 19.784 10.881 19.838 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 19.784 11.169 19.838 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 19.784 11.457 19.838 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 19.784 11.745 19.838 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 19.784 12.033 19.838 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 19.784 12.321 19.838 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 19.784 12.609 19.838 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 19.784 12.897 19.838 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 19.784 13.185 19.838 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 19.784 13.473 19.838 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 19.784 13.761 19.838 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 19.784 14.049 19.838 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 19.784 14.337 19.838 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 19.784 14.625 19.838 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 19.784 14.913 19.838 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 19.784 15.201 19.838 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 19.784 15.489 19.838 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 19.784 15.777 19.838 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 19.784 16.065 19.838 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 19.784 16.353 19.838 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 19.784 16.641 19.838 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 19.784 16.929 19.838 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 19.784 17.217 19.838 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 19.784 17.505 19.838 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 19.784 17.793 19.838 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 19.784 18.081 19.838 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 19.784 18.369 19.838 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 19.784 18.657 19.838 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 19.784 18.945 19.838 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 19.784 19.233 19.838 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 19.784 19.521 19.838 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 19.784 19.809 19.838 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 19.784 20.097 19.838 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 19.784 20.385 19.838 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 19.784 20.673 19.838 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 19.784 20.961 19.838 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 19.784 21.249 19.838 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 19.784 21.537 19.838 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 19.784 21.825 19.838 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 19.784 22.113 19.838 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 19.784 22.401 19.838 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 19.784 22.689 19.838 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 19.784 22.977 19.838 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 19.784 23.265 19.838 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 19.784 23.553 19.838 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 19.784 23.841 19.838 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 19.784 24.129 19.838 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 19.784 24.417 19.838 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 19.784 24.705 19.838 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 19.784 24.993 19.838 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 19.784 25.281 19.838 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 19.784 25.569 19.838 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 19.784 25.857 19.838 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 19.784 26.145 19.838 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 19.784 26.433 19.838 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 19.784 26.721 19.838 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 19.784 27.009 19.838 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 19.784 27.297 19.838 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 19.784 27.585 19.838 ; + END + END w0_wmask_in[191] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.452 0.072 10.476 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.412 0.072 11.436 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.604 0.072 11.628 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.988 0.072 12.012 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.180 0.072 12.204 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.564 0.072 12.588 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.140 0.072 13.164 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.332 0.072 13.356 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.908 0.072 13.932 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.292 0.072 14.316 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.484 0.072 14.508 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.444 0.072 15.468 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.020 0.072 16.044 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.212 0.072 16.236 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.788 0.072 16.812 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.364 0.072 17.388 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.324 0.072 18.348 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 9.492 61.213 9.516 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 9.684 61.213 9.708 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 9.876 61.213 9.900 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 10.068 61.213 10.092 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 10.260 61.213 10.284 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 10.452 61.213 10.476 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 10.644 61.213 10.668 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 10.836 61.213 10.860 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 11.028 61.213 11.052 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 11.220 61.213 11.244 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 11.412 61.213 11.436 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 11.604 61.213 11.628 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 11.796 61.213 11.820 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 11.988 61.213 12.012 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 12.180 61.213 12.204 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 12.372 61.213 12.396 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 12.564 61.213 12.588 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 12.756 61.213 12.780 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 12.948 61.213 12.972 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 13.140 61.213 13.164 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 13.332 61.213 13.356 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 13.524 61.213 13.548 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 13.716 61.213 13.740 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 13.908 61.213 13.932 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 14.100 61.213 14.124 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 14.292 61.213 14.316 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 14.484 61.213 14.508 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 14.676 61.213 14.700 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 14.868 61.213 14.892 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 15.060 61.213 15.084 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 15.252 61.213 15.276 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 15.444 61.213 15.468 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 15.636 61.213 15.660 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 15.828 61.213 15.852 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 16.020 61.213 16.044 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 16.212 61.213 16.236 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 16.404 61.213 16.428 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 16.596 61.213 16.620 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 16.788 61.213 16.812 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 16.980 61.213 17.004 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 17.172 61.213 17.196 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 17.364 61.213 17.388 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 17.556 61.213 17.580 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 17.748 61.213 17.772 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 17.940 61.213 17.964 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 18.132 61.213 18.156 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 18.324 61.213 18.348 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 18.516 61.213 18.540 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[191] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 19.784 27.873 19.838 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 19.784 28.161 19.838 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 19.784 28.449 19.838 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 19.784 28.737 19.838 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 19.784 29.025 19.838 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 19.784 29.313 19.838 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 19.784 29.601 19.838 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 19.784 29.889 19.838 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 19.784 30.177 19.838 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 19.784 30.465 19.838 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 19.784 30.753 19.838 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 19.784 31.041 19.838 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 19.784 31.329 19.838 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 19.784 31.617 19.838 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 19.784 31.905 19.838 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 19.784 32.193 19.838 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 19.784 32.481 19.838 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 19.784 32.769 19.838 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 19.784 33.057 19.838 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 19.784 33.345 19.838 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 19.784 33.633 19.838 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 19.784 33.921 19.838 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 19.784 34.209 19.838 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 19.784 34.497 19.838 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 19.784 34.785 19.838 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 19.784 35.073 19.838 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 19.784 35.361 19.838 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 19.784 35.649 19.838 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 19.784 35.937 19.838 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 19.784 36.225 19.838 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 19.784 36.513 19.838 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 19.784 36.801 19.838 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 19.784 37.089 19.838 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 19.784 37.377 19.838 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 19.784 37.665 19.838 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 19.784 37.953 19.838 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 19.784 38.241 19.838 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 19.784 38.529 19.838 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 19.784 38.817 19.838 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 19.784 39.105 19.838 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 19.784 39.393 19.838 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 19.784 39.681 19.838 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 19.784 39.969 19.838 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 19.784 40.257 19.838 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 19.784 40.545 19.838 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 19.784 40.833 19.838 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 19.784 41.121 19.838 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 19.784 41.409 19.838 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 19.784 41.697 19.838 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 19.784 41.985 19.838 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 19.784 42.273 19.838 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 19.784 42.561 19.838 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 19.784 42.849 19.838 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 19.784 43.137 19.838 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 19.784 43.425 19.838 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 19.784 43.713 19.838 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 19.784 44.001 19.838 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 19.784 44.289 19.838 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 19.784 44.577 19.838 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 19.784 44.865 19.838 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 19.784 45.153 19.838 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 19.784 45.441 19.838 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 19.784 45.729 19.838 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 19.784 46.017 19.838 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 19.784 46.305 19.838 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 19.784 46.593 19.838 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 19.784 46.881 19.838 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 19.784 47.169 19.838 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 19.784 47.457 19.838 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 19.784 47.745 19.838 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 19.784 48.033 19.838 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 19.784 48.321 19.838 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 19.784 48.609 19.838 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 19.784 48.897 19.838 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 19.784 49.185 19.838 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 19.784 49.473 19.838 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 19.784 49.761 19.838 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 19.784 50.049 19.838 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 19.784 50.337 19.838 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 19.784 50.625 19.838 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 19.784 50.913 19.838 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 19.784 51.201 19.838 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 19.784 51.489 19.838 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 19.784 51.777 19.838 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 19.784 52.065 19.838 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 19.784 52.353 19.838 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 19.784 52.641 19.838 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 19.784 52.929 19.838 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 19.784 53.217 19.838 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 19.784 53.505 19.838 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 19.784 53.793 19.838 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 19.784 54.081 19.838 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 19.784 54.369 19.838 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 19.784 54.657 19.838 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 19.784 54.945 19.838 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 19.784 55.233 19.838 ; + END + END r0_rd_out[191] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.900 0.072 18.924 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 18.708 61.213 18.732 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 18.900 61.213 18.924 ; + END + END w0_addr_in[3] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 19.092 61.213 19.116 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.141 19.284 61.213 19.308 ; + END + END r0_addr_in[3] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 19.784 55.521 19.838 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 19.784 55.809 19.838 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 19.784 56.097 19.838 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 19.784 56.385 19.838 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 19.784 56.673 19.838 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 60.997 0.336 ; + RECT 0.216 1.008 60.997 1.104 ; + RECT 0.216 1.776 60.997 1.872 ; + RECT 0.216 2.544 60.997 2.640 ; + RECT 0.216 3.312 60.997 3.408 ; + RECT 0.216 4.080 60.997 4.176 ; + RECT 0.216 4.848 60.997 4.944 ; + RECT 0.216 5.616 60.997 5.712 ; + RECT 0.216 6.384 60.997 6.480 ; + RECT 0.216 7.152 60.997 7.248 ; + RECT 0.216 7.920 60.997 8.016 ; + RECT 0.216 8.688 60.997 8.784 ; + RECT 0.216 9.456 60.997 9.552 ; + RECT 0.216 10.224 60.997 10.320 ; + RECT 0.216 10.992 60.997 11.088 ; + RECT 0.216 11.760 60.997 11.856 ; + RECT 0.216 12.528 60.997 12.624 ; + RECT 0.216 13.296 60.997 13.392 ; + RECT 0.216 14.064 60.997 14.160 ; + RECT 0.216 14.832 60.997 14.928 ; + RECT 0.216 15.600 60.997 15.696 ; + RECT 0.216 16.368 60.997 16.464 ; + RECT 0.216 17.136 60.997 17.232 ; + RECT 0.216 17.904 60.997 18.000 ; + RECT 0.216 18.672 60.997 18.768 ; + RECT 0.216 19.440 60.997 19.536 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 60.997 0.336 ; + RECT 0.216 1.008 60.997 1.104 ; + RECT 0.216 1.776 60.997 1.872 ; + RECT 0.216 2.544 60.997 2.640 ; + RECT 0.216 3.312 60.997 3.408 ; + RECT 0.216 4.080 60.997 4.176 ; + RECT 0.216 4.848 60.997 4.944 ; + RECT 0.216 5.616 60.997 5.712 ; + RECT 0.216 6.384 60.997 6.480 ; + RECT 0.216 7.152 60.997 7.248 ; + RECT 0.216 7.920 60.997 8.016 ; + RECT 0.216 8.688 60.997 8.784 ; + RECT 0.216 9.456 60.997 9.552 ; + RECT 0.216 10.224 60.997 10.320 ; + RECT 0.216 10.992 60.997 11.088 ; + RECT 0.216 11.760 60.997 11.856 ; + RECT 0.216 12.528 60.997 12.624 ; + RECT 0.216 13.296 60.997 13.392 ; + RECT 0.216 14.064 60.997 14.160 ; + RECT 0.216 14.832 60.997 14.928 ; + RECT 0.216 15.600 60.997 15.696 ; + RECT 0.216 16.368 60.997 16.464 ; + RECT 0.216 17.136 60.997 17.232 ; + RECT 0.216 17.904 60.997 18.000 ; + RECT 0.216 18.672 60.997 18.768 ; + RECT 0.216 19.440 60.997 19.536 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 61.213 19.838 ; + LAYER M2 ; + RECT 0 0 61.213 19.838 ; + LAYER M3 ; + RECT 0 0 61.213 19.838 ; + LAYER M4 ; + RECT 0 0 61.213 19.838 ; + END +END fakeram_192x16_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_193x16_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_193x16_1r1w.lef new file mode 100644 index 0000000..40a62f8 --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_193x16_1r1w.lef @@ -0,0 +1,5414 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_193x16_1r1w + FOREIGN fakeram_193x16_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 61.532 BY 19.927 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.420 0.072 0.444 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.148 0.072 2.172 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.012 0.072 3.036 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.452 0.072 4.476 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.468 0.072 6.492 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 0.276 61.532 0.300 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 0.420 61.532 0.444 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 0.564 61.532 0.588 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 0.708 61.532 0.732 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 0.852 61.532 0.876 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 0.996 61.532 1.020 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 1.140 61.532 1.164 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 1.284 61.532 1.308 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 1.428 61.532 1.452 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 1.572 61.532 1.596 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 1.716 61.532 1.740 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 1.860 61.532 1.884 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.004 61.532 2.028 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.148 61.532 2.172 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.292 61.532 2.316 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.436 61.532 2.460 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.580 61.532 2.604 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.724 61.532 2.748 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 2.868 61.532 2.892 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.012 61.532 3.036 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.156 61.532 3.180 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.300 61.532 3.324 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.444 61.532 3.468 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.588 61.532 3.612 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.732 61.532 3.756 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 3.876 61.532 3.900 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.020 61.532 4.044 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.164 61.532 4.188 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.308 61.532 4.332 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.452 61.532 4.476 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.596 61.532 4.620 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.740 61.532 4.764 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 4.884 61.532 4.908 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.028 61.532 5.052 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.172 61.532 5.196 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.316 61.532 5.340 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.460 61.532 5.484 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.604 61.532 5.628 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.748 61.532 5.772 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 5.892 61.532 5.916 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.036 61.532 6.060 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.180 61.532 6.204 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.324 61.532 6.348 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.468 61.532 6.492 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.612 61.532 6.636 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.756 61.532 6.780 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 6.900 61.532 6.924 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.044 61.532 7.068 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 19.873 0.225 19.927 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 19.873 0.513 19.927 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 19.873 0.801 19.927 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 19.873 1.089 19.927 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 19.873 1.377 19.927 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 19.873 1.665 19.927 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 19.873 1.953 19.927 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 19.873 2.241 19.927 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 19.873 2.529 19.927 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 19.873 2.817 19.927 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 19.873 3.105 19.927 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 19.873 3.393 19.927 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 19.873 3.681 19.927 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 19.873 3.969 19.927 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 19.873 4.257 19.927 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 19.873 4.545 19.927 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 19.873 4.833 19.927 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 19.873 5.121 19.927 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 19.873 5.409 19.927 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 19.873 5.697 19.927 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 19.873 5.985 19.927 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 19.873 6.273 19.927 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 19.873 6.561 19.927 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 19.873 6.849 19.927 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 19.873 7.137 19.927 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 19.873 7.425 19.927 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 19.873 7.713 19.927 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 19.873 8.001 19.927 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 19.873 8.289 19.927 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 19.873 8.577 19.927 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 19.873 8.865 19.927 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 19.873 9.153 19.927 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 19.873 9.441 19.927 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 19.873 9.729 19.927 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 19.873 10.017 19.927 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 19.873 10.305 19.927 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 19.873 10.593 19.927 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 19.873 10.881 19.927 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 19.873 11.169 19.927 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 19.873 11.457 19.927 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 19.873 11.745 19.927 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 19.873 12.033 19.927 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 19.873 12.321 19.927 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 19.873 12.609 19.927 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 19.873 12.897 19.927 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 19.873 13.185 19.927 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 19.873 13.473 19.927 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 19.873 13.761 19.927 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 19.873 14.049 19.927 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 19.873 14.337 19.927 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 19.873 14.625 19.927 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 19.873 14.913 19.927 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 19.873 15.201 19.927 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 19.873 15.489 19.927 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 19.873 15.777 19.927 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 19.873 16.065 19.927 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 19.873 16.353 19.927 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 19.873 16.641 19.927 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 19.873 16.929 19.927 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 19.873 17.217 19.927 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 19.873 17.505 19.927 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 19.873 17.793 19.927 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 19.873 18.081 19.927 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 19.873 18.369 19.927 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 19.873 18.657 19.927 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 19.873 18.945 19.927 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 19.873 19.233 19.927 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 19.873 19.521 19.927 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 19.873 19.809 19.927 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 19.873 20.097 19.927 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 19.873 20.385 19.927 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 19.873 20.673 19.927 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 19.873 20.961 19.927 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 19.873 21.249 19.927 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 19.873 21.537 19.927 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 19.873 21.825 19.927 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 19.873 22.113 19.927 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 19.873 22.401 19.927 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 19.873 22.689 19.927 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 19.873 22.977 19.927 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 19.873 23.265 19.927 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 19.873 23.553 19.927 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 19.873 23.841 19.927 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 19.873 24.129 19.927 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 19.873 24.417 19.927 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 19.873 24.705 19.927 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 19.873 24.993 19.927 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 19.873 25.281 19.927 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 19.873 25.569 19.927 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 19.873 25.857 19.927 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 19.873 26.145 19.927 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 19.873 26.433 19.927 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 19.873 26.721 19.927 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 19.873 27.009 19.927 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 19.873 27.297 19.927 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 19.873 27.585 19.927 ; + END + END w0_wmask_in[192] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.908 0.072 7.932 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.772 0.072 8.796 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.060 0.072 9.084 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.924 0.072 9.948 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.500 0.072 10.524 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.788 0.072 10.812 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.652 0.072 11.676 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.228 0.072 12.252 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.244 0.072 14.268 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.188 61.532 7.212 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.332 61.532 7.356 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.476 61.532 7.500 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.620 61.532 7.644 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.764 61.532 7.788 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 7.908 61.532 7.932 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.052 61.532 8.076 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.196 61.532 8.220 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.340 61.532 8.364 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.484 61.532 8.508 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.628 61.532 8.652 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.772 61.532 8.796 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 8.916 61.532 8.940 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.060 61.532 9.084 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.204 61.532 9.228 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.348 61.532 9.372 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.492 61.532 9.516 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.636 61.532 9.660 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.780 61.532 9.804 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 9.924 61.532 9.948 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.068 61.532 10.092 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.212 61.532 10.236 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.356 61.532 10.380 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.500 61.532 10.524 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.644 61.532 10.668 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.788 61.532 10.812 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 10.932 61.532 10.956 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.076 61.532 11.100 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.220 61.532 11.244 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.364 61.532 11.388 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.508 61.532 11.532 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.652 61.532 11.676 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.796 61.532 11.820 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 11.940 61.532 11.964 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.084 61.532 12.108 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.228 61.532 12.252 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.372 61.532 12.396 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.516 61.532 12.540 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.660 61.532 12.684 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.804 61.532 12.828 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 12.948 61.532 12.972 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.092 61.532 13.116 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.236 61.532 13.260 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.380 61.532 13.404 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.524 61.532 13.548 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.668 61.532 13.692 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.812 61.532 13.836 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 13.956 61.532 13.980 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[192] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 19.873 27.873 19.927 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 19.873 28.161 19.927 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 19.873 28.449 19.927 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 19.873 28.737 19.927 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 19.873 29.025 19.927 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 19.873 29.313 19.927 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 19.873 29.601 19.927 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 19.873 29.889 19.927 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 19.873 30.177 19.927 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 19.873 30.465 19.927 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 19.873 30.753 19.927 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 19.873 31.041 19.927 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 19.873 31.329 19.927 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 19.873 31.617 19.927 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 19.873 31.905 19.927 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 19.873 32.193 19.927 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 19.873 32.481 19.927 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 19.873 32.769 19.927 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 19.873 33.057 19.927 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 19.873 33.345 19.927 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 19.873 33.633 19.927 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 19.873 33.921 19.927 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 19.873 34.209 19.927 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 19.873 34.497 19.927 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 19.873 34.785 19.927 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 19.873 35.073 19.927 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 19.873 35.361 19.927 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 19.873 35.649 19.927 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 19.873 35.937 19.927 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 19.873 36.225 19.927 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 19.873 36.513 19.927 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 19.873 36.801 19.927 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 19.873 37.089 19.927 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 19.873 37.377 19.927 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 19.873 37.665 19.927 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 19.873 37.953 19.927 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 19.873 38.241 19.927 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 19.873 38.529 19.927 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 19.873 38.817 19.927 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 19.873 39.105 19.927 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 19.873 39.393 19.927 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 19.873 39.681 19.927 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 19.873 39.969 19.927 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 19.873 40.257 19.927 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 19.873 40.545 19.927 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 19.873 40.833 19.927 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 19.873 41.121 19.927 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 19.873 41.409 19.927 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 19.873 41.697 19.927 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 19.873 41.985 19.927 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 19.873 42.273 19.927 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 19.873 42.561 19.927 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 19.873 42.849 19.927 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 19.873 43.137 19.927 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 19.873 43.425 19.927 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 19.873 43.713 19.927 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 19.873 44.001 19.927 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 19.873 44.289 19.927 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 19.873 44.577 19.927 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 19.873 44.865 19.927 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 19.873 45.153 19.927 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 19.873 45.441 19.927 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 19.873 45.729 19.927 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 19.873 46.017 19.927 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 19.873 46.305 19.927 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 19.873 46.593 19.927 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 19.873 46.881 19.927 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 19.873 47.169 19.927 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 19.873 47.457 19.927 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 19.873 47.745 19.927 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 19.873 48.033 19.927 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 19.873 48.321 19.927 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 19.873 48.609 19.927 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 19.873 48.897 19.927 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 19.873 49.185 19.927 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 19.873 49.473 19.927 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 19.873 49.761 19.927 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 19.873 50.049 19.927 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 19.873 50.337 19.927 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 19.873 50.625 19.927 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 19.873 50.913 19.927 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 19.873 51.201 19.927 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 19.873 51.489 19.927 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 19.873 51.777 19.927 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 19.873 52.065 19.927 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 19.873 52.353 19.927 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 19.873 52.641 19.927 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 19.873 52.929 19.927 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 19.873 53.217 19.927 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 19.873 53.505 19.927 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 19.873 53.793 19.927 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 19.873 54.081 19.927 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 19.873 54.369 19.927 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 19.873 54.657 19.927 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 19.873 54.945 19.927 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 19.873 55.233 19.927 ; + END + END r0_rd_out[192] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 14.100 61.532 14.124 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 14.244 61.532 14.268 ; + END + END w0_addr_in[3] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 14.388 61.532 14.412 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 61.460 14.532 61.532 14.556 ; + END + END r0_addr_in[3] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 19.873 55.521 19.927 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 19.873 55.809 19.927 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 19.873 56.097 19.927 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 19.873 56.385 19.927 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 19.873 56.673 19.927 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 61.316 0.336 ; + RECT 0.216 1.008 61.316 1.104 ; + RECT 0.216 1.776 61.316 1.872 ; + RECT 0.216 2.544 61.316 2.640 ; + RECT 0.216 3.312 61.316 3.408 ; + RECT 0.216 4.080 61.316 4.176 ; + RECT 0.216 4.848 61.316 4.944 ; + RECT 0.216 5.616 61.316 5.712 ; + RECT 0.216 6.384 61.316 6.480 ; + RECT 0.216 7.152 61.316 7.248 ; + RECT 0.216 7.920 61.316 8.016 ; + RECT 0.216 8.688 61.316 8.784 ; + RECT 0.216 9.456 61.316 9.552 ; + RECT 0.216 10.224 61.316 10.320 ; + RECT 0.216 10.992 61.316 11.088 ; + RECT 0.216 11.760 61.316 11.856 ; + RECT 0.216 12.528 61.316 12.624 ; + RECT 0.216 13.296 61.316 13.392 ; + RECT 0.216 14.064 61.316 14.160 ; + RECT 0.216 14.832 61.316 14.928 ; + RECT 0.216 15.600 61.316 15.696 ; + RECT 0.216 16.368 61.316 16.464 ; + RECT 0.216 17.136 61.316 17.232 ; + RECT 0.216 17.904 61.316 18.000 ; + RECT 0.216 18.672 61.316 18.768 ; + RECT 0.216 19.440 61.316 19.536 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 61.316 0.336 ; + RECT 0.216 1.008 61.316 1.104 ; + RECT 0.216 1.776 61.316 1.872 ; + RECT 0.216 2.544 61.316 2.640 ; + RECT 0.216 3.312 61.316 3.408 ; + RECT 0.216 4.080 61.316 4.176 ; + RECT 0.216 4.848 61.316 4.944 ; + RECT 0.216 5.616 61.316 5.712 ; + RECT 0.216 6.384 61.316 6.480 ; + RECT 0.216 7.152 61.316 7.248 ; + RECT 0.216 7.920 61.316 8.016 ; + RECT 0.216 8.688 61.316 8.784 ; + RECT 0.216 9.456 61.316 9.552 ; + RECT 0.216 10.224 61.316 10.320 ; + RECT 0.216 10.992 61.316 11.088 ; + RECT 0.216 11.760 61.316 11.856 ; + RECT 0.216 12.528 61.316 12.624 ; + RECT 0.216 13.296 61.316 13.392 ; + RECT 0.216 14.064 61.316 14.160 ; + RECT 0.216 14.832 61.316 14.928 ; + RECT 0.216 15.600 61.316 15.696 ; + RECT 0.216 16.368 61.316 16.464 ; + RECT 0.216 17.136 61.316 17.232 ; + RECT 0.216 17.904 61.316 18.000 ; + RECT 0.216 18.672 61.316 18.768 ; + RECT 0.216 19.440 61.316 19.536 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 61.532 19.927 ; + LAYER M2 ; + RECT 0 0 61.532 19.927 ; + LAYER M3 ; + RECT 0 0 61.532 19.927 ; + LAYER M4 ; + RECT 0 0 61.532 19.927 ; + END +END fakeram_193x16_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_21x256_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_21x256_1r1w.lef new file mode 100644 index 0000000..a5bfa5d --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_21x256_1r1w.lef @@ -0,0 +1,914 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_21x256_1r1w + FOREIGN fakeram_21x256_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 10.203 BY 47.203 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.724 10.203 2.748 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 5.172 10.203 5.196 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 7.620 10.203 7.644 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 10.068 10.203 10.092 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 47.149 0.225 47.203 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 47.149 0.585 47.203 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 47.149 0.945 47.203 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 47.149 1.305 47.203 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 47.149 1.665 47.203 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 47.149 2.025 47.203 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 47.149 2.385 47.203 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 47.149 2.745 47.203 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 47.149 3.105 47.203 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 47.149 3.465 47.203 ; + END + END w0_wmask_in[20] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.204 0.072 27.228 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 12.516 10.203 12.540 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 14.964 10.203 14.988 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 17.412 10.203 17.436 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 19.860 10.203 19.884 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 22.308 10.203 22.332 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 0.000 0.657 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 0.000 1.521 0.054 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 0.000 4.113 0.054 ; + END + END w0_wd_in[20] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 0.000 4.977 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.823 0.000 5.841 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.551 0.000 7.569 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 0.000 8.433 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 47.149 3.825 47.203 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 47.149 4.185 47.203 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 47.149 4.545 47.203 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 47.149 4.905 47.203 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 47.149 5.265 47.203 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 47.149 5.625 47.203 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 47.149 5.985 47.203 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 47.149 6.345 47.203 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 47.149 6.705 47.203 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 47.149 7.065 47.203 ; + END + END r0_rd_out[20] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.100 0.072 32.124 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.996 0.072 37.020 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 24.756 10.203 24.780 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 27.204 10.203 27.228 ; + END + END w0_addr_in[5] + PIN w0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 29.652 10.203 29.676 ; + END + END w0_addr_in[6] + PIN w0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 32.100 10.203 32.124 ; + END + END w0_addr_in[7] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.892 0.072 41.916 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.340 0.072 44.364 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.788 0.072 46.812 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 34.548 10.203 34.572 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 36.996 10.203 37.020 ; + END + END r0_addr_in[5] + PIN r0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 39.444 10.203 39.468 ; + END + END r0_addr_in[6] + PIN r0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 41.892 10.203 41.916 ; + END + END r0_addr_in[7] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 47.149 7.425 47.203 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 47.149 7.785 47.203 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 47.149 8.145 47.203 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 47.149 8.505 47.203 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 47.149 8.865 47.203 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; + RECT 0.216 45.552 9.987 45.648 ; + RECT 0.216 46.320 9.987 46.416 ; + RECT 0.216 47.088 9.987 47.184 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + RECT 0.216 13.296 9.987 13.392 ; + RECT 0.216 14.064 9.987 14.160 ; + RECT 0.216 14.832 9.987 14.928 ; + RECT 0.216 15.600 9.987 15.696 ; + RECT 0.216 16.368 9.987 16.464 ; + RECT 0.216 17.136 9.987 17.232 ; + RECT 0.216 17.904 9.987 18.000 ; + RECT 0.216 18.672 9.987 18.768 ; + RECT 0.216 19.440 9.987 19.536 ; + RECT 0.216 20.208 9.987 20.304 ; + RECT 0.216 20.976 9.987 21.072 ; + RECT 0.216 21.744 9.987 21.840 ; + RECT 0.216 22.512 9.987 22.608 ; + RECT 0.216 23.280 9.987 23.376 ; + RECT 0.216 24.048 9.987 24.144 ; + RECT 0.216 24.816 9.987 24.912 ; + RECT 0.216 25.584 9.987 25.680 ; + RECT 0.216 26.352 9.987 26.448 ; + RECT 0.216 27.120 9.987 27.216 ; + RECT 0.216 27.888 9.987 27.984 ; + RECT 0.216 28.656 9.987 28.752 ; + RECT 0.216 29.424 9.987 29.520 ; + RECT 0.216 30.192 9.987 30.288 ; + RECT 0.216 30.960 9.987 31.056 ; + RECT 0.216 31.728 9.987 31.824 ; + RECT 0.216 32.496 9.987 32.592 ; + RECT 0.216 33.264 9.987 33.360 ; + RECT 0.216 34.032 9.987 34.128 ; + RECT 0.216 34.800 9.987 34.896 ; + RECT 0.216 35.568 9.987 35.664 ; + RECT 0.216 36.336 9.987 36.432 ; + RECT 0.216 37.104 9.987 37.200 ; + RECT 0.216 37.872 9.987 37.968 ; + RECT 0.216 38.640 9.987 38.736 ; + RECT 0.216 39.408 9.987 39.504 ; + RECT 0.216 40.176 9.987 40.272 ; + RECT 0.216 40.944 9.987 41.040 ; + RECT 0.216 41.712 9.987 41.808 ; + RECT 0.216 42.480 9.987 42.576 ; + RECT 0.216 43.248 9.987 43.344 ; + RECT 0.216 44.016 9.987 44.112 ; + RECT 0.216 44.784 9.987 44.880 ; + RECT 0.216 45.552 9.987 45.648 ; + RECT 0.216 46.320 9.987 46.416 ; + RECT 0.216 47.088 9.987 47.184 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 10.203 47.203 ; + LAYER M2 ; + RECT 0 0 10.203 47.203 ; + LAYER M3 ; + RECT 0 0 10.203 47.203 ; + LAYER M4 ; + RECT 0 0 10.203 47.203 ; + END +END fakeram_21x256_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_21x64_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_21x64_1r1w.lef new file mode 100644 index 0000000..7f44dfb --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_21x64_1r1w.lef @@ -0,0 +1,788 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_21x64_1r1w + FOREIGN fakeram_21x64_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 10.203 BY 13.196 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.276 10.203 0.300 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 0.996 10.203 1.020 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 1.716 10.203 1.740 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 2.436 10.203 2.460 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 3.156 10.203 3.180 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 13.142 0.225 13.196 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 13.142 0.585 13.196 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 13.142 0.945 13.196 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 13.142 1.305 13.196 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 13.142 1.665 13.196 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 13.142 2.025 13.196 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 13.142 2.385 13.196 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 13.142 2.745 13.196 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 13.142 3.105 13.196 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 13.142 3.465 13.196 ; + END + END w0_wmask_in[20] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 3.876 10.203 3.900 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 4.596 10.203 4.620 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 5.316 10.203 5.340 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 6.036 10.203 6.060 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 6.756 10.203 6.780 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 0.000 0.657 0.054 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 0.000 1.521 0.054 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 0.000 3.249 0.054 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 0.000 4.113 0.054 ; + END + END w0_wd_in[20] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 0.000 4.977 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.823 0.000 5.841 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.551 0.000 7.569 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.415 0.000 8.433 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 13.142 3.825 13.196 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 13.142 4.185 13.196 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 13.142 4.545 13.196 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 13.142 4.905 13.196 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 13.142 5.265 13.196 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 13.142 5.625 13.196 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 13.142 5.985 13.196 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 13.142 6.345 13.196 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 13.142 6.705 13.196 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 13.142 7.065 13.196 ; + END + END r0_rd_out[20] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 7.476 10.203 7.500 ; + END + END w0_addr_in[3] + PIN w0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 8.196 10.203 8.220 ; + END + END w0_addr_in[4] + PIN w0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 8.916 10.203 8.940 ; + END + END w0_addr_in[5] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 9.636 10.203 9.660 ; + END + END r0_addr_in[3] + PIN r0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 10.356 10.203 10.380 ; + END + END r0_addr_in[4] + PIN r0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 10.131 11.076 10.203 11.100 ; + END + END r0_addr_in[5] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 13.142 7.425 13.196 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 13.142 7.785 13.196 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 13.142 8.145 13.196 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 13.142 8.505 13.196 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 13.142 8.865 13.196 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 9.987 0.336 ; + RECT 0.216 1.008 9.987 1.104 ; + RECT 0.216 1.776 9.987 1.872 ; + RECT 0.216 2.544 9.987 2.640 ; + RECT 0.216 3.312 9.987 3.408 ; + RECT 0.216 4.080 9.987 4.176 ; + RECT 0.216 4.848 9.987 4.944 ; + RECT 0.216 5.616 9.987 5.712 ; + RECT 0.216 6.384 9.987 6.480 ; + RECT 0.216 7.152 9.987 7.248 ; + RECT 0.216 7.920 9.987 8.016 ; + RECT 0.216 8.688 9.987 8.784 ; + RECT 0.216 9.456 9.987 9.552 ; + RECT 0.216 10.224 9.987 10.320 ; + RECT 0.216 10.992 9.987 11.088 ; + RECT 0.216 11.760 9.987 11.856 ; + RECT 0.216 12.528 9.987 12.624 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 10.203 13.196 ; + LAYER M2 ; + RECT 0 0 10.203 13.196 ; + LAYER M3 ; + RECT 0 0 10.203 13.196 ; + LAYER M4 ; + RECT 0 0 10.203 13.196 ; + END +END fakeram_21x64_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_32x1024_1rw.lef b/designs/asap7/vortex/sram/lef/fakeram_32x1024_1rw.lef new file mode 100644 index 0000000..64f58fa --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_32x1024_1rw.lef @@ -0,0 +1,1321 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_32x1024_1rw + FOREIGN fakeram_32x1024_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 6.501 BY 117.375 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.796 0.072 5.820 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.876 0.072 27.900 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.916 0.072 38.940 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 0.276 6.501 0.300 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 5.796 6.501 5.820 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 11.316 6.501 11.340 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 16.836 6.501 16.860 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 22.356 6.501 22.380 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 27.876 6.501 27.900 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 33.396 6.501 33.420 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 38.916 6.501 38.940 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 117.321 0.225 117.375 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.351 117.321 0.369 117.375 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 117.321 0.513 117.375 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.639 117.321 0.657 117.375 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 117.321 0.801 117.375 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 117.321 0.945 117.375 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 117.321 1.089 117.375 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.215 117.321 1.233 117.375 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 117.321 1.377 117.375 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.503 117.321 1.521 117.375 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 117.321 1.665 117.375 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.791 117.321 1.809 117.375 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 117.321 1.953 117.375 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.079 117.321 2.097 117.375 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 117.321 2.241 117.375 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 117.321 2.385 117.375 ; + END + END rw0_wmask_in[31] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.436 0.072 44.460 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.956 0.072 49.980 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.476 0.072 55.500 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.996 0.072 61.020 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.516 0.072 66.540 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.036 0.072 72.060 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.556 0.072 77.580 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.076 0.072 83.100 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 44.436 6.501 44.460 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 49.956 6.501 49.980 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 55.476 6.501 55.500 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 60.996 6.501 61.020 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 66.516 6.501 66.540 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 72.036 6.501 72.060 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 77.556 6.501 77.580 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 83.076 6.501 83.100 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 0.000 0.405 0.054 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 0.000 0.585 0.054 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 0.000 0.945 0.054 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 0.000 1.485 0.054 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 0.000 2.205 0.054 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 0.000 2.565 0.054 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END rw0_wd_in[31] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 0.000 3.285 0.054 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 0.000 3.645 0.054 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 0.000 4.185 0.054 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 0.000 4.365 0.054 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 0.000 4.905 0.054 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 0.000 5.445 0.054 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 117.321 2.529 117.375 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.655 117.321 2.673 117.375 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 117.321 2.817 117.375 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.943 117.321 2.961 117.375 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 117.321 3.105 117.375 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.231 117.321 3.249 117.375 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 117.321 3.393 117.375 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.519 117.321 3.537 117.375 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 117.321 3.681 117.375 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 117.321 3.825 117.375 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 117.321 3.969 117.375 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.095 117.321 4.113 117.375 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 117.321 4.257 117.375 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.383 117.321 4.401 117.375 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 117.321 4.545 117.375 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.671 117.321 4.689 117.375 ; + END + END rw0_rd_out[31] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.596 0.072 88.620 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.116 0.072 94.140 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 99.636 0.072 99.660 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 105.156 0.072 105.180 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 110.676 0.072 110.700 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 88.596 6.501 88.620 ; + END + END rw0_addr_in[5] + PIN rw0_addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 94.116 6.501 94.140 ; + END + END rw0_addr_in[6] + PIN rw0_addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 99.636 6.501 99.660 ; + END + END rw0_addr_in[7] + PIN rw0_addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 105.156 6.501 105.180 ; + END + END rw0_addr_in[8] + PIN rw0_addr_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 6.429 110.676 6.501 110.700 ; + END + END rw0_addr_in[9] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 117.321 4.833 117.375 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.959 117.321 4.977 117.375 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 117.321 5.121 117.375 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 6.285 0.336 ; + RECT 0.216 1.008 6.285 1.104 ; + RECT 0.216 1.776 6.285 1.872 ; + RECT 0.216 2.544 6.285 2.640 ; + RECT 0.216 3.312 6.285 3.408 ; + RECT 0.216 4.080 6.285 4.176 ; + RECT 0.216 4.848 6.285 4.944 ; + RECT 0.216 5.616 6.285 5.712 ; + RECT 0.216 6.384 6.285 6.480 ; + RECT 0.216 7.152 6.285 7.248 ; + RECT 0.216 7.920 6.285 8.016 ; + RECT 0.216 8.688 6.285 8.784 ; + RECT 0.216 9.456 6.285 9.552 ; + RECT 0.216 10.224 6.285 10.320 ; + RECT 0.216 10.992 6.285 11.088 ; + RECT 0.216 11.760 6.285 11.856 ; + RECT 0.216 12.528 6.285 12.624 ; + RECT 0.216 13.296 6.285 13.392 ; + RECT 0.216 14.064 6.285 14.160 ; + RECT 0.216 14.832 6.285 14.928 ; + RECT 0.216 15.600 6.285 15.696 ; + RECT 0.216 16.368 6.285 16.464 ; + RECT 0.216 17.136 6.285 17.232 ; + RECT 0.216 17.904 6.285 18.000 ; + RECT 0.216 18.672 6.285 18.768 ; + RECT 0.216 19.440 6.285 19.536 ; + RECT 0.216 20.208 6.285 20.304 ; + RECT 0.216 20.976 6.285 21.072 ; + RECT 0.216 21.744 6.285 21.840 ; + RECT 0.216 22.512 6.285 22.608 ; + RECT 0.216 23.280 6.285 23.376 ; + RECT 0.216 24.048 6.285 24.144 ; + RECT 0.216 24.816 6.285 24.912 ; + RECT 0.216 25.584 6.285 25.680 ; + RECT 0.216 26.352 6.285 26.448 ; + RECT 0.216 27.120 6.285 27.216 ; + RECT 0.216 27.888 6.285 27.984 ; + RECT 0.216 28.656 6.285 28.752 ; + RECT 0.216 29.424 6.285 29.520 ; + RECT 0.216 30.192 6.285 30.288 ; + RECT 0.216 30.960 6.285 31.056 ; + RECT 0.216 31.728 6.285 31.824 ; + RECT 0.216 32.496 6.285 32.592 ; + RECT 0.216 33.264 6.285 33.360 ; + RECT 0.216 34.032 6.285 34.128 ; + RECT 0.216 34.800 6.285 34.896 ; + RECT 0.216 35.568 6.285 35.664 ; + RECT 0.216 36.336 6.285 36.432 ; + RECT 0.216 37.104 6.285 37.200 ; + RECT 0.216 37.872 6.285 37.968 ; + RECT 0.216 38.640 6.285 38.736 ; + RECT 0.216 39.408 6.285 39.504 ; + RECT 0.216 40.176 6.285 40.272 ; + RECT 0.216 40.944 6.285 41.040 ; + RECT 0.216 41.712 6.285 41.808 ; + RECT 0.216 42.480 6.285 42.576 ; + RECT 0.216 43.248 6.285 43.344 ; + RECT 0.216 44.016 6.285 44.112 ; + RECT 0.216 44.784 6.285 44.880 ; + RECT 0.216 45.552 6.285 45.648 ; + RECT 0.216 46.320 6.285 46.416 ; + RECT 0.216 47.088 6.285 47.184 ; + RECT 0.216 47.856 6.285 47.952 ; + RECT 0.216 48.624 6.285 48.720 ; + RECT 0.216 49.392 6.285 49.488 ; + RECT 0.216 50.160 6.285 50.256 ; + RECT 0.216 50.928 6.285 51.024 ; + RECT 0.216 51.696 6.285 51.792 ; + RECT 0.216 52.464 6.285 52.560 ; + RECT 0.216 53.232 6.285 53.328 ; + RECT 0.216 54.000 6.285 54.096 ; + RECT 0.216 54.768 6.285 54.864 ; + RECT 0.216 55.536 6.285 55.632 ; + RECT 0.216 56.304 6.285 56.400 ; + RECT 0.216 57.072 6.285 57.168 ; + RECT 0.216 57.840 6.285 57.936 ; + RECT 0.216 58.608 6.285 58.704 ; + RECT 0.216 59.376 6.285 59.472 ; + RECT 0.216 60.144 6.285 60.240 ; + RECT 0.216 60.912 6.285 61.008 ; + RECT 0.216 61.680 6.285 61.776 ; + RECT 0.216 62.448 6.285 62.544 ; + RECT 0.216 63.216 6.285 63.312 ; + RECT 0.216 63.984 6.285 64.080 ; + RECT 0.216 64.752 6.285 64.848 ; + RECT 0.216 65.520 6.285 65.616 ; + RECT 0.216 66.288 6.285 66.384 ; + RECT 0.216 67.056 6.285 67.152 ; + RECT 0.216 67.824 6.285 67.920 ; + RECT 0.216 68.592 6.285 68.688 ; + RECT 0.216 69.360 6.285 69.456 ; + RECT 0.216 70.128 6.285 70.224 ; + RECT 0.216 70.896 6.285 70.992 ; + RECT 0.216 71.664 6.285 71.760 ; + RECT 0.216 72.432 6.285 72.528 ; + RECT 0.216 73.200 6.285 73.296 ; + RECT 0.216 73.968 6.285 74.064 ; + RECT 0.216 74.736 6.285 74.832 ; + RECT 0.216 75.504 6.285 75.600 ; + RECT 0.216 76.272 6.285 76.368 ; + RECT 0.216 77.040 6.285 77.136 ; + RECT 0.216 77.808 6.285 77.904 ; + RECT 0.216 78.576 6.285 78.672 ; + RECT 0.216 79.344 6.285 79.440 ; + RECT 0.216 80.112 6.285 80.208 ; + RECT 0.216 80.880 6.285 80.976 ; + RECT 0.216 81.648 6.285 81.744 ; + RECT 0.216 82.416 6.285 82.512 ; + RECT 0.216 83.184 6.285 83.280 ; + RECT 0.216 83.952 6.285 84.048 ; + RECT 0.216 84.720 6.285 84.816 ; + RECT 0.216 85.488 6.285 85.584 ; + RECT 0.216 86.256 6.285 86.352 ; + RECT 0.216 87.024 6.285 87.120 ; + RECT 0.216 87.792 6.285 87.888 ; + RECT 0.216 88.560 6.285 88.656 ; + RECT 0.216 89.328 6.285 89.424 ; + RECT 0.216 90.096 6.285 90.192 ; + RECT 0.216 90.864 6.285 90.960 ; + RECT 0.216 91.632 6.285 91.728 ; + RECT 0.216 92.400 6.285 92.496 ; + RECT 0.216 93.168 6.285 93.264 ; + RECT 0.216 93.936 6.285 94.032 ; + RECT 0.216 94.704 6.285 94.800 ; + RECT 0.216 95.472 6.285 95.568 ; + RECT 0.216 96.240 6.285 96.336 ; + RECT 0.216 97.008 6.285 97.104 ; + RECT 0.216 97.776 6.285 97.872 ; + RECT 0.216 98.544 6.285 98.640 ; + RECT 0.216 99.312 6.285 99.408 ; + RECT 0.216 100.080 6.285 100.176 ; + RECT 0.216 100.848 6.285 100.944 ; + RECT 0.216 101.616 6.285 101.712 ; + RECT 0.216 102.384 6.285 102.480 ; + RECT 0.216 103.152 6.285 103.248 ; + RECT 0.216 103.920 6.285 104.016 ; + RECT 0.216 104.688 6.285 104.784 ; + RECT 0.216 105.456 6.285 105.552 ; + RECT 0.216 106.224 6.285 106.320 ; + RECT 0.216 106.992 6.285 107.088 ; + RECT 0.216 107.760 6.285 107.856 ; + RECT 0.216 108.528 6.285 108.624 ; + RECT 0.216 109.296 6.285 109.392 ; + RECT 0.216 110.064 6.285 110.160 ; + RECT 0.216 110.832 6.285 110.928 ; + RECT 0.216 111.600 6.285 111.696 ; + RECT 0.216 112.368 6.285 112.464 ; + RECT 0.216 113.136 6.285 113.232 ; + RECT 0.216 113.904 6.285 114.000 ; + RECT 0.216 114.672 6.285 114.768 ; + RECT 0.216 115.440 6.285 115.536 ; + RECT 0.216 116.208 6.285 116.304 ; + RECT 0.216 116.976 6.285 117.072 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 6.285 0.336 ; + RECT 0.216 1.008 6.285 1.104 ; + RECT 0.216 1.776 6.285 1.872 ; + RECT 0.216 2.544 6.285 2.640 ; + RECT 0.216 3.312 6.285 3.408 ; + RECT 0.216 4.080 6.285 4.176 ; + RECT 0.216 4.848 6.285 4.944 ; + RECT 0.216 5.616 6.285 5.712 ; + RECT 0.216 6.384 6.285 6.480 ; + RECT 0.216 7.152 6.285 7.248 ; + RECT 0.216 7.920 6.285 8.016 ; + RECT 0.216 8.688 6.285 8.784 ; + RECT 0.216 9.456 6.285 9.552 ; + RECT 0.216 10.224 6.285 10.320 ; + RECT 0.216 10.992 6.285 11.088 ; + RECT 0.216 11.760 6.285 11.856 ; + RECT 0.216 12.528 6.285 12.624 ; + RECT 0.216 13.296 6.285 13.392 ; + RECT 0.216 14.064 6.285 14.160 ; + RECT 0.216 14.832 6.285 14.928 ; + RECT 0.216 15.600 6.285 15.696 ; + RECT 0.216 16.368 6.285 16.464 ; + RECT 0.216 17.136 6.285 17.232 ; + RECT 0.216 17.904 6.285 18.000 ; + RECT 0.216 18.672 6.285 18.768 ; + RECT 0.216 19.440 6.285 19.536 ; + RECT 0.216 20.208 6.285 20.304 ; + RECT 0.216 20.976 6.285 21.072 ; + RECT 0.216 21.744 6.285 21.840 ; + RECT 0.216 22.512 6.285 22.608 ; + RECT 0.216 23.280 6.285 23.376 ; + RECT 0.216 24.048 6.285 24.144 ; + RECT 0.216 24.816 6.285 24.912 ; + RECT 0.216 25.584 6.285 25.680 ; + RECT 0.216 26.352 6.285 26.448 ; + RECT 0.216 27.120 6.285 27.216 ; + RECT 0.216 27.888 6.285 27.984 ; + RECT 0.216 28.656 6.285 28.752 ; + RECT 0.216 29.424 6.285 29.520 ; + RECT 0.216 30.192 6.285 30.288 ; + RECT 0.216 30.960 6.285 31.056 ; + RECT 0.216 31.728 6.285 31.824 ; + RECT 0.216 32.496 6.285 32.592 ; + RECT 0.216 33.264 6.285 33.360 ; + RECT 0.216 34.032 6.285 34.128 ; + RECT 0.216 34.800 6.285 34.896 ; + RECT 0.216 35.568 6.285 35.664 ; + RECT 0.216 36.336 6.285 36.432 ; + RECT 0.216 37.104 6.285 37.200 ; + RECT 0.216 37.872 6.285 37.968 ; + RECT 0.216 38.640 6.285 38.736 ; + RECT 0.216 39.408 6.285 39.504 ; + RECT 0.216 40.176 6.285 40.272 ; + RECT 0.216 40.944 6.285 41.040 ; + RECT 0.216 41.712 6.285 41.808 ; + RECT 0.216 42.480 6.285 42.576 ; + RECT 0.216 43.248 6.285 43.344 ; + RECT 0.216 44.016 6.285 44.112 ; + RECT 0.216 44.784 6.285 44.880 ; + RECT 0.216 45.552 6.285 45.648 ; + RECT 0.216 46.320 6.285 46.416 ; + RECT 0.216 47.088 6.285 47.184 ; + RECT 0.216 47.856 6.285 47.952 ; + RECT 0.216 48.624 6.285 48.720 ; + RECT 0.216 49.392 6.285 49.488 ; + RECT 0.216 50.160 6.285 50.256 ; + RECT 0.216 50.928 6.285 51.024 ; + RECT 0.216 51.696 6.285 51.792 ; + RECT 0.216 52.464 6.285 52.560 ; + RECT 0.216 53.232 6.285 53.328 ; + RECT 0.216 54.000 6.285 54.096 ; + RECT 0.216 54.768 6.285 54.864 ; + RECT 0.216 55.536 6.285 55.632 ; + RECT 0.216 56.304 6.285 56.400 ; + RECT 0.216 57.072 6.285 57.168 ; + RECT 0.216 57.840 6.285 57.936 ; + RECT 0.216 58.608 6.285 58.704 ; + RECT 0.216 59.376 6.285 59.472 ; + RECT 0.216 60.144 6.285 60.240 ; + RECT 0.216 60.912 6.285 61.008 ; + RECT 0.216 61.680 6.285 61.776 ; + RECT 0.216 62.448 6.285 62.544 ; + RECT 0.216 63.216 6.285 63.312 ; + RECT 0.216 63.984 6.285 64.080 ; + RECT 0.216 64.752 6.285 64.848 ; + RECT 0.216 65.520 6.285 65.616 ; + RECT 0.216 66.288 6.285 66.384 ; + RECT 0.216 67.056 6.285 67.152 ; + RECT 0.216 67.824 6.285 67.920 ; + RECT 0.216 68.592 6.285 68.688 ; + RECT 0.216 69.360 6.285 69.456 ; + RECT 0.216 70.128 6.285 70.224 ; + RECT 0.216 70.896 6.285 70.992 ; + RECT 0.216 71.664 6.285 71.760 ; + RECT 0.216 72.432 6.285 72.528 ; + RECT 0.216 73.200 6.285 73.296 ; + RECT 0.216 73.968 6.285 74.064 ; + RECT 0.216 74.736 6.285 74.832 ; + RECT 0.216 75.504 6.285 75.600 ; + RECT 0.216 76.272 6.285 76.368 ; + RECT 0.216 77.040 6.285 77.136 ; + RECT 0.216 77.808 6.285 77.904 ; + RECT 0.216 78.576 6.285 78.672 ; + RECT 0.216 79.344 6.285 79.440 ; + RECT 0.216 80.112 6.285 80.208 ; + RECT 0.216 80.880 6.285 80.976 ; + RECT 0.216 81.648 6.285 81.744 ; + RECT 0.216 82.416 6.285 82.512 ; + RECT 0.216 83.184 6.285 83.280 ; + RECT 0.216 83.952 6.285 84.048 ; + RECT 0.216 84.720 6.285 84.816 ; + RECT 0.216 85.488 6.285 85.584 ; + RECT 0.216 86.256 6.285 86.352 ; + RECT 0.216 87.024 6.285 87.120 ; + RECT 0.216 87.792 6.285 87.888 ; + RECT 0.216 88.560 6.285 88.656 ; + RECT 0.216 89.328 6.285 89.424 ; + RECT 0.216 90.096 6.285 90.192 ; + RECT 0.216 90.864 6.285 90.960 ; + RECT 0.216 91.632 6.285 91.728 ; + RECT 0.216 92.400 6.285 92.496 ; + RECT 0.216 93.168 6.285 93.264 ; + RECT 0.216 93.936 6.285 94.032 ; + RECT 0.216 94.704 6.285 94.800 ; + RECT 0.216 95.472 6.285 95.568 ; + RECT 0.216 96.240 6.285 96.336 ; + RECT 0.216 97.008 6.285 97.104 ; + RECT 0.216 97.776 6.285 97.872 ; + RECT 0.216 98.544 6.285 98.640 ; + RECT 0.216 99.312 6.285 99.408 ; + RECT 0.216 100.080 6.285 100.176 ; + RECT 0.216 100.848 6.285 100.944 ; + RECT 0.216 101.616 6.285 101.712 ; + RECT 0.216 102.384 6.285 102.480 ; + RECT 0.216 103.152 6.285 103.248 ; + RECT 0.216 103.920 6.285 104.016 ; + RECT 0.216 104.688 6.285 104.784 ; + RECT 0.216 105.456 6.285 105.552 ; + RECT 0.216 106.224 6.285 106.320 ; + RECT 0.216 106.992 6.285 107.088 ; + RECT 0.216 107.760 6.285 107.856 ; + RECT 0.216 108.528 6.285 108.624 ; + RECT 0.216 109.296 6.285 109.392 ; + RECT 0.216 110.064 6.285 110.160 ; + RECT 0.216 110.832 6.285 110.928 ; + RECT 0.216 111.600 6.285 111.696 ; + RECT 0.216 112.368 6.285 112.464 ; + RECT 0.216 113.136 6.285 113.232 ; + RECT 0.216 113.904 6.285 114.000 ; + RECT 0.216 114.672 6.285 114.768 ; + RECT 0.216 115.440 6.285 115.536 ; + RECT 0.216 116.208 6.285 116.304 ; + RECT 0.216 116.976 6.285 117.072 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 6.501 117.375 ; + LAYER M2 ; + RECT 0 0 6.501 117.375 ; + LAYER M3 ; + RECT 0 0 6.501 117.375 ; + LAYER M4 ; + RECT 0 0 6.501 117.375 ; + END +END fakeram_32x1024_1rw + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_512x64_1rw.lef b/designs/asap7/vortex/sram/lef/fakeram_512x64_1rw.lef new file mode 100644 index 0000000..1a36f90 --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_512x64_1rw.lef @@ -0,0 +1,14033 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_512x64_1rw + FOREIGN fakeram_512x64_1rw 0 0 ; + SYMMETRY X Y R90 ; + SIZE 104.012 BY 36.116 ; + CLASS BLOCK ; + PIN rw0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END rw0_wmask_in[0] + PIN rw0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.372 0.072 0.396 ; + END + END rw0_wmask_in[1] + PIN rw0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.468 0.072 0.492 ; + END + END rw0_wmask_in[2] + PIN rw0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END rw0_wmask_in[3] + PIN rw0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END rw0_wmask_in[4] + PIN rw0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.756 0.072 0.780 ; + END + END rw0_wmask_in[5] + PIN rw0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END rw0_wmask_in[6] + PIN rw0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.948 0.072 0.972 ; + END + END rw0_wmask_in[7] + PIN rw0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END rw0_wmask_in[8] + PIN rw0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END rw0_wmask_in[9] + PIN rw0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END rw0_wmask_in[10] + PIN rw0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.332 0.072 1.356 ; + END + END rw0_wmask_in[11] + PIN rw0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END rw0_wmask_in[12] + PIN rw0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.524 0.072 1.548 ; + END + END rw0_wmask_in[13] + PIN rw0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END rw0_wmask_in[14] + PIN rw0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END rw0_wmask_in[15] + PIN rw0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END rw0_wmask_in[16] + PIN rw0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.908 0.072 1.932 ; + END + END rw0_wmask_in[17] + PIN rw0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END rw0_wmask_in[18] + PIN rw0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.100 0.072 2.124 ; + END + END rw0_wmask_in[19] + PIN rw0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END rw0_wmask_in[20] + PIN rw0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END rw0_wmask_in[21] + PIN rw0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END rw0_wmask_in[22] + PIN rw0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.484 0.072 2.508 ; + END + END rw0_wmask_in[23] + PIN rw0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END rw0_wmask_in[24] + PIN rw0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.676 0.072 2.700 ; + END + END rw0_wmask_in[25] + PIN rw0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END rw0_wmask_in[26] + PIN rw0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END rw0_wmask_in[27] + PIN rw0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END rw0_wmask_in[28] + PIN rw0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.060 0.072 3.084 ; + END + END rw0_wmask_in[29] + PIN rw0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END rw0_wmask_in[30] + PIN rw0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.252 0.072 3.276 ; + END + END rw0_wmask_in[31] + PIN rw0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END rw0_wmask_in[32] + PIN rw0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END rw0_wmask_in[33] + PIN rw0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.540 0.072 3.564 ; + END + END rw0_wmask_in[34] + PIN rw0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.636 0.072 3.660 ; + END + END rw0_wmask_in[35] + PIN rw0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END rw0_wmask_in[36] + PIN rw0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.828 0.072 3.852 ; + END + END rw0_wmask_in[37] + PIN rw0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END rw0_wmask_in[38] + PIN rw0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END rw0_wmask_in[39] + PIN rw0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END rw0_wmask_in[40] + PIN rw0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.212 0.072 4.236 ; + END + END rw0_wmask_in[41] + PIN rw0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END rw0_wmask_in[42] + PIN rw0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.404 0.072 4.428 ; + END + END rw0_wmask_in[43] + PIN rw0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END rw0_wmask_in[44] + PIN rw0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END rw0_wmask_in[45] + PIN rw0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END rw0_wmask_in[46] + PIN rw0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.788 0.072 4.812 ; + END + END rw0_wmask_in[47] + PIN rw0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END rw0_wmask_in[48] + PIN rw0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.980 0.072 5.004 ; + END + END rw0_wmask_in[49] + PIN rw0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END rw0_wmask_in[50] + PIN rw0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END rw0_wmask_in[51] + PIN rw0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END rw0_wmask_in[52] + PIN rw0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.364 0.072 5.388 ; + END + END rw0_wmask_in[53] + PIN rw0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END rw0_wmask_in[54] + PIN rw0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.556 0.072 5.580 ; + END + END rw0_wmask_in[55] + PIN rw0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END rw0_wmask_in[56] + PIN rw0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END rw0_wmask_in[57] + PIN rw0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.844 0.072 5.868 ; + END + END rw0_wmask_in[58] + PIN rw0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.940 0.072 5.964 ; + END + END rw0_wmask_in[59] + PIN rw0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END rw0_wmask_in[60] + PIN rw0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.132 0.072 6.156 ; + END + END rw0_wmask_in[61] + PIN rw0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.228 0.072 6.252 ; + END + END rw0_wmask_in[62] + PIN rw0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END rw0_wmask_in[63] + PIN rw0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END rw0_wmask_in[64] + PIN rw0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.516 0.072 6.540 ; + END + END rw0_wmask_in[65] + PIN rw0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END rw0_wmask_in[66] + PIN rw0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.708 0.072 6.732 ; + END + END rw0_wmask_in[67] + PIN rw0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END rw0_wmask_in[68] + PIN rw0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END rw0_wmask_in[69] + PIN rw0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END rw0_wmask_in[70] + PIN rw0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.092 0.072 7.116 ; + END + END rw0_wmask_in[71] + PIN rw0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END rw0_wmask_in[72] + PIN rw0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.284 0.072 7.308 ; + END + END rw0_wmask_in[73] + PIN rw0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.380 0.072 7.404 ; + END + END rw0_wmask_in[74] + PIN rw0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END rw0_wmask_in[75] + PIN rw0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END rw0_wmask_in[76] + PIN rw0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.668 0.072 7.692 ; + END + END rw0_wmask_in[77] + PIN rw0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END rw0_wmask_in[78] + PIN rw0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.860 0.072 7.884 ; + END + END rw0_wmask_in[79] + PIN rw0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END rw0_wmask_in[80] + PIN rw0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END rw0_wmask_in[81] + PIN rw0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.148 0.072 8.172 ; + END + END rw0_wmask_in[82] + PIN rw0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.244 0.072 8.268 ; + END + END rw0_wmask_in[83] + PIN rw0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END rw0_wmask_in[84] + PIN rw0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.436 0.072 8.460 ; + END + END rw0_wmask_in[85] + PIN rw0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.532 0.072 8.556 ; + END + END rw0_wmask_in[86] + PIN rw0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END rw0_wmask_in[87] + PIN rw0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END rw0_wmask_in[88] + PIN rw0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.820 0.072 8.844 ; + END + END rw0_wmask_in[89] + PIN rw0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END rw0_wmask_in[90] + PIN rw0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.012 0.072 9.036 ; + END + END rw0_wmask_in[91] + PIN rw0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END rw0_wmask_in[92] + PIN rw0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END rw0_wmask_in[93] + PIN rw0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.300 0.072 9.324 ; + END + END rw0_wmask_in[94] + PIN rw0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.396 0.072 9.420 ; + END + END rw0_wmask_in[95] + PIN rw0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END rw0_wmask_in[96] + PIN rw0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.588 0.072 9.612 ; + END + END rw0_wmask_in[97] + PIN rw0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.684 0.072 9.708 ; + END + END rw0_wmask_in[98] + PIN rw0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END rw0_wmask_in[99] + PIN rw0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.876 0.072 9.900 ; + END + END rw0_wmask_in[100] + PIN rw0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.972 0.072 9.996 ; + END + END rw0_wmask_in[101] + PIN rw0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END rw0_wmask_in[102] + PIN rw0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.164 0.072 10.188 ; + END + END rw0_wmask_in[103] + PIN rw0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.260 0.072 10.284 ; + END + END rw0_wmask_in[104] + PIN rw0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END rw0_wmask_in[105] + PIN rw0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.452 0.072 10.476 ; + END + END rw0_wmask_in[106] + PIN rw0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.548 0.072 10.572 ; + END + END rw0_wmask_in[107] + PIN rw0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END rw0_wmask_in[108] + PIN rw0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.740 0.072 10.764 ; + END + END rw0_wmask_in[109] + PIN rw0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.836 0.072 10.860 ; + END + END rw0_wmask_in[110] + PIN rw0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END rw0_wmask_in[111] + PIN rw0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.028 0.072 11.052 ; + END + END rw0_wmask_in[112] + PIN rw0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.124 0.072 11.148 ; + END + END rw0_wmask_in[113] + PIN rw0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END rw0_wmask_in[114] + PIN rw0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.316 0.072 11.340 ; + END + END rw0_wmask_in[115] + PIN rw0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.412 0.072 11.436 ; + END + END rw0_wmask_in[116] + PIN rw0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END rw0_wmask_in[117] + PIN rw0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.604 0.072 11.628 ; + END + END rw0_wmask_in[118] + PIN rw0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.700 0.072 11.724 ; + END + END rw0_wmask_in[119] + PIN rw0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END rw0_wmask_in[120] + PIN rw0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.892 0.072 11.916 ; + END + END rw0_wmask_in[121] + PIN rw0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.988 0.072 12.012 ; + END + END rw0_wmask_in[122] + PIN rw0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END rw0_wmask_in[123] + PIN rw0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.180 0.072 12.204 ; + END + END rw0_wmask_in[124] + PIN rw0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.276 0.072 12.300 ; + END + END rw0_wmask_in[125] + PIN rw0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END rw0_wmask_in[126] + PIN rw0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.468 0.072 12.492 ; + END + END rw0_wmask_in[127] + PIN rw0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.276 104.012 0.300 ; + END + END rw0_wmask_in[128] + PIN rw0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.372 104.012 0.396 ; + END + END rw0_wmask_in[129] + PIN rw0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.468 104.012 0.492 ; + END + END rw0_wmask_in[130] + PIN rw0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.564 104.012 0.588 ; + END + END rw0_wmask_in[131] + PIN rw0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.660 104.012 0.684 ; + END + END rw0_wmask_in[132] + PIN rw0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.756 104.012 0.780 ; + END + END rw0_wmask_in[133] + PIN rw0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.852 104.012 0.876 ; + END + END rw0_wmask_in[134] + PIN rw0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 0.948 104.012 0.972 ; + END + END rw0_wmask_in[135] + PIN rw0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.044 104.012 1.068 ; + END + END rw0_wmask_in[136] + PIN rw0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.140 104.012 1.164 ; + END + END rw0_wmask_in[137] + PIN rw0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.236 104.012 1.260 ; + END + END rw0_wmask_in[138] + PIN rw0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.332 104.012 1.356 ; + END + END rw0_wmask_in[139] + PIN rw0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.428 104.012 1.452 ; + END + END rw0_wmask_in[140] + PIN rw0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.524 104.012 1.548 ; + END + END rw0_wmask_in[141] + PIN rw0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.620 104.012 1.644 ; + END + END rw0_wmask_in[142] + PIN rw0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.716 104.012 1.740 ; + END + END rw0_wmask_in[143] + PIN rw0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.812 104.012 1.836 ; + END + END rw0_wmask_in[144] + PIN rw0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 1.908 104.012 1.932 ; + END + END rw0_wmask_in[145] + PIN rw0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.004 104.012 2.028 ; + END + END rw0_wmask_in[146] + PIN rw0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.100 104.012 2.124 ; + END + END rw0_wmask_in[147] + PIN rw0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.196 104.012 2.220 ; + END + END rw0_wmask_in[148] + PIN rw0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.292 104.012 2.316 ; + END + END rw0_wmask_in[149] + PIN rw0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.388 104.012 2.412 ; + END + END rw0_wmask_in[150] + PIN rw0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.484 104.012 2.508 ; + END + END rw0_wmask_in[151] + PIN rw0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.580 104.012 2.604 ; + END + END rw0_wmask_in[152] + PIN rw0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.676 104.012 2.700 ; + END + END rw0_wmask_in[153] + PIN rw0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.772 104.012 2.796 ; + END + END rw0_wmask_in[154] + PIN rw0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.868 104.012 2.892 ; + END + END rw0_wmask_in[155] + PIN rw0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 2.964 104.012 2.988 ; + END + END rw0_wmask_in[156] + PIN rw0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.060 104.012 3.084 ; + END + END rw0_wmask_in[157] + PIN rw0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.156 104.012 3.180 ; + END + END rw0_wmask_in[158] + PIN rw0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.252 104.012 3.276 ; + END + END rw0_wmask_in[159] + PIN rw0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.348 104.012 3.372 ; + END + END rw0_wmask_in[160] + PIN rw0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.444 104.012 3.468 ; + END + END rw0_wmask_in[161] + PIN rw0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.540 104.012 3.564 ; + END + END rw0_wmask_in[162] + PIN rw0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.636 104.012 3.660 ; + END + END rw0_wmask_in[163] + PIN rw0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.732 104.012 3.756 ; + END + END rw0_wmask_in[164] + PIN rw0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.828 104.012 3.852 ; + END + END rw0_wmask_in[165] + PIN rw0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 3.924 104.012 3.948 ; + END + END rw0_wmask_in[166] + PIN rw0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.020 104.012 4.044 ; + END + END rw0_wmask_in[167] + PIN rw0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.116 104.012 4.140 ; + END + END rw0_wmask_in[168] + PIN rw0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.212 104.012 4.236 ; + END + END rw0_wmask_in[169] + PIN rw0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.308 104.012 4.332 ; + END + END rw0_wmask_in[170] + PIN rw0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.404 104.012 4.428 ; + END + END rw0_wmask_in[171] + PIN rw0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.500 104.012 4.524 ; + END + END rw0_wmask_in[172] + PIN rw0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.596 104.012 4.620 ; + END + END rw0_wmask_in[173] + PIN rw0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.692 104.012 4.716 ; + END + END rw0_wmask_in[174] + PIN rw0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.788 104.012 4.812 ; + END + END rw0_wmask_in[175] + PIN rw0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.884 104.012 4.908 ; + END + END rw0_wmask_in[176] + PIN rw0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 4.980 104.012 5.004 ; + END + END rw0_wmask_in[177] + PIN rw0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.076 104.012 5.100 ; + END + END rw0_wmask_in[178] + PIN rw0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.172 104.012 5.196 ; + END + END rw0_wmask_in[179] + PIN rw0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.268 104.012 5.292 ; + END + END rw0_wmask_in[180] + PIN rw0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.364 104.012 5.388 ; + END + END rw0_wmask_in[181] + PIN rw0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.460 104.012 5.484 ; + END + END rw0_wmask_in[182] + PIN rw0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.556 104.012 5.580 ; + END + END rw0_wmask_in[183] + PIN rw0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.652 104.012 5.676 ; + END + END rw0_wmask_in[184] + PIN rw0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.748 104.012 5.772 ; + END + END rw0_wmask_in[185] + PIN rw0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.844 104.012 5.868 ; + END + END rw0_wmask_in[186] + PIN rw0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 5.940 104.012 5.964 ; + END + END rw0_wmask_in[187] + PIN rw0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.036 104.012 6.060 ; + END + END rw0_wmask_in[188] + PIN rw0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.132 104.012 6.156 ; + END + END rw0_wmask_in[189] + PIN rw0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.228 104.012 6.252 ; + END + END rw0_wmask_in[190] + PIN rw0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.324 104.012 6.348 ; + END + END rw0_wmask_in[191] + PIN rw0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.420 104.012 6.444 ; + END + END rw0_wmask_in[192] + PIN rw0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.516 104.012 6.540 ; + END + END rw0_wmask_in[193] + PIN rw0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.612 104.012 6.636 ; + END + END rw0_wmask_in[194] + PIN rw0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.708 104.012 6.732 ; + END + END rw0_wmask_in[195] + PIN rw0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.804 104.012 6.828 ; + END + END rw0_wmask_in[196] + PIN rw0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.900 104.012 6.924 ; + END + END rw0_wmask_in[197] + PIN rw0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 6.996 104.012 7.020 ; + END + END rw0_wmask_in[198] + PIN rw0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.092 104.012 7.116 ; + END + END rw0_wmask_in[199] + PIN rw0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.188 104.012 7.212 ; + END + END rw0_wmask_in[200] + PIN rw0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.284 104.012 7.308 ; + END + END rw0_wmask_in[201] + PIN rw0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.380 104.012 7.404 ; + END + END rw0_wmask_in[202] + PIN rw0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.476 104.012 7.500 ; + END + END rw0_wmask_in[203] + PIN rw0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.572 104.012 7.596 ; + END + END rw0_wmask_in[204] + PIN rw0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.668 104.012 7.692 ; + END + END rw0_wmask_in[205] + PIN rw0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.764 104.012 7.788 ; + END + END rw0_wmask_in[206] + PIN rw0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.860 104.012 7.884 ; + END + END rw0_wmask_in[207] + PIN rw0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 7.956 104.012 7.980 ; + END + END rw0_wmask_in[208] + PIN rw0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.052 104.012 8.076 ; + END + END rw0_wmask_in[209] + PIN rw0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.148 104.012 8.172 ; + END + END rw0_wmask_in[210] + PIN rw0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.244 104.012 8.268 ; + END + END rw0_wmask_in[211] + PIN rw0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.340 104.012 8.364 ; + END + END rw0_wmask_in[212] + PIN rw0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.436 104.012 8.460 ; + END + END rw0_wmask_in[213] + PIN rw0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.532 104.012 8.556 ; + END + END rw0_wmask_in[214] + PIN rw0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.628 104.012 8.652 ; + END + END rw0_wmask_in[215] + PIN rw0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.724 104.012 8.748 ; + END + END rw0_wmask_in[216] + PIN rw0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.820 104.012 8.844 ; + END + END rw0_wmask_in[217] + PIN rw0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 8.916 104.012 8.940 ; + END + END rw0_wmask_in[218] + PIN rw0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.012 104.012 9.036 ; + END + END rw0_wmask_in[219] + PIN rw0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.108 104.012 9.132 ; + END + END rw0_wmask_in[220] + PIN rw0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.204 104.012 9.228 ; + END + END rw0_wmask_in[221] + PIN rw0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.300 104.012 9.324 ; + END + END rw0_wmask_in[222] + PIN rw0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.396 104.012 9.420 ; + END + END rw0_wmask_in[223] + PIN rw0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.492 104.012 9.516 ; + END + END rw0_wmask_in[224] + PIN rw0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.588 104.012 9.612 ; + END + END rw0_wmask_in[225] + PIN rw0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.684 104.012 9.708 ; + END + END rw0_wmask_in[226] + PIN rw0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.780 104.012 9.804 ; + END + END rw0_wmask_in[227] + PIN rw0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.876 104.012 9.900 ; + END + END rw0_wmask_in[228] + PIN rw0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 9.972 104.012 9.996 ; + END + END rw0_wmask_in[229] + PIN rw0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.068 104.012 10.092 ; + END + END rw0_wmask_in[230] + PIN rw0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.164 104.012 10.188 ; + END + END rw0_wmask_in[231] + PIN rw0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.260 104.012 10.284 ; + END + END rw0_wmask_in[232] + PIN rw0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.356 104.012 10.380 ; + END + END rw0_wmask_in[233] + PIN rw0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.452 104.012 10.476 ; + END + END rw0_wmask_in[234] + PIN rw0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.548 104.012 10.572 ; + END + END rw0_wmask_in[235] + PIN rw0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.644 104.012 10.668 ; + END + END rw0_wmask_in[236] + PIN rw0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.740 104.012 10.764 ; + END + END rw0_wmask_in[237] + PIN rw0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.836 104.012 10.860 ; + END + END rw0_wmask_in[238] + PIN rw0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 10.932 104.012 10.956 ; + END + END rw0_wmask_in[239] + PIN rw0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.028 104.012 11.052 ; + END + END rw0_wmask_in[240] + PIN rw0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.124 104.012 11.148 ; + END + END rw0_wmask_in[241] + PIN rw0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.220 104.012 11.244 ; + END + END rw0_wmask_in[242] + PIN rw0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.316 104.012 11.340 ; + END + END rw0_wmask_in[243] + PIN rw0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.412 104.012 11.436 ; + END + END rw0_wmask_in[244] + PIN rw0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.508 104.012 11.532 ; + END + END rw0_wmask_in[245] + PIN rw0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.604 104.012 11.628 ; + END + END rw0_wmask_in[246] + PIN rw0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.700 104.012 11.724 ; + END + END rw0_wmask_in[247] + PIN rw0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.796 104.012 11.820 ; + END + END rw0_wmask_in[248] + PIN rw0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.892 104.012 11.916 ; + END + END rw0_wmask_in[249] + PIN rw0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 11.988 104.012 12.012 ; + END + END rw0_wmask_in[250] + PIN rw0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.084 104.012 12.108 ; + END + END rw0_wmask_in[251] + PIN rw0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.180 104.012 12.204 ; + END + END rw0_wmask_in[252] + PIN rw0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.276 104.012 12.300 ; + END + END rw0_wmask_in[253] + PIN rw0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.372 104.012 12.396 ; + END + END rw0_wmask_in[254] + PIN rw0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.468 104.012 12.492 ; + END + END rw0_wmask_in[255] + PIN rw0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 36.062 0.225 36.116 ; + END + END rw0_wmask_in[256] + PIN rw0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 36.062 0.405 36.116 ; + END + END rw0_wmask_in[257] + PIN rw0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 36.062 0.585 36.116 ; + END + END rw0_wmask_in[258] + PIN rw0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 36.062 0.765 36.116 ; + END + END rw0_wmask_in[259] + PIN rw0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 36.062 0.945 36.116 ; + END + END rw0_wmask_in[260] + PIN rw0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 36.062 1.125 36.116 ; + END + END rw0_wmask_in[261] + PIN rw0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 36.062 1.305 36.116 ; + END + END rw0_wmask_in[262] + PIN rw0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 36.062 1.485 36.116 ; + END + END rw0_wmask_in[263] + PIN rw0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 36.062 1.665 36.116 ; + END + END rw0_wmask_in[264] + PIN rw0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 36.062 1.845 36.116 ; + END + END rw0_wmask_in[265] + PIN rw0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 36.062 2.025 36.116 ; + END + END rw0_wmask_in[266] + PIN rw0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 36.062 2.205 36.116 ; + END + END rw0_wmask_in[267] + PIN rw0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 36.062 2.385 36.116 ; + END + END rw0_wmask_in[268] + PIN rw0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 36.062 2.565 36.116 ; + END + END rw0_wmask_in[269] + PIN rw0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 36.062 2.745 36.116 ; + END + END rw0_wmask_in[270] + PIN rw0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 36.062 2.925 36.116 ; + END + END rw0_wmask_in[271] + PIN rw0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 36.062 3.105 36.116 ; + END + END rw0_wmask_in[272] + PIN rw0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 36.062 3.285 36.116 ; + END + END rw0_wmask_in[273] + PIN rw0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 36.062 3.465 36.116 ; + END + END rw0_wmask_in[274] + PIN rw0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 36.062 3.645 36.116 ; + END + END rw0_wmask_in[275] + PIN rw0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 36.062 3.825 36.116 ; + END + END rw0_wmask_in[276] + PIN rw0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 36.062 4.005 36.116 ; + END + END rw0_wmask_in[277] + PIN rw0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 36.062 4.185 36.116 ; + END + END rw0_wmask_in[278] + PIN rw0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 36.062 4.365 36.116 ; + END + END rw0_wmask_in[279] + PIN rw0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 36.062 4.545 36.116 ; + END + END rw0_wmask_in[280] + PIN rw0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 36.062 4.725 36.116 ; + END + END rw0_wmask_in[281] + PIN rw0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 36.062 4.905 36.116 ; + END + END rw0_wmask_in[282] + PIN rw0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 36.062 5.085 36.116 ; + END + END rw0_wmask_in[283] + PIN rw0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 36.062 5.265 36.116 ; + END + END rw0_wmask_in[284] + PIN rw0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 36.062 5.445 36.116 ; + END + END rw0_wmask_in[285] + PIN rw0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 36.062 5.625 36.116 ; + END + END rw0_wmask_in[286] + PIN rw0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 36.062 5.805 36.116 ; + END + END rw0_wmask_in[287] + PIN rw0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 36.062 5.985 36.116 ; + END + END rw0_wmask_in[288] + PIN rw0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 36.062 6.165 36.116 ; + END + END rw0_wmask_in[289] + PIN rw0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 36.062 6.345 36.116 ; + END + END rw0_wmask_in[290] + PIN rw0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 36.062 6.525 36.116 ; + END + END rw0_wmask_in[291] + PIN rw0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 36.062 6.705 36.116 ; + END + END rw0_wmask_in[292] + PIN rw0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 36.062 6.885 36.116 ; + END + END rw0_wmask_in[293] + PIN rw0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 36.062 7.065 36.116 ; + END + END rw0_wmask_in[294] + PIN rw0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 36.062 7.245 36.116 ; + END + END rw0_wmask_in[295] + PIN rw0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 36.062 7.425 36.116 ; + END + END rw0_wmask_in[296] + PIN rw0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 36.062 7.605 36.116 ; + END + END rw0_wmask_in[297] + PIN rw0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 36.062 7.785 36.116 ; + END + END rw0_wmask_in[298] + PIN rw0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 36.062 7.965 36.116 ; + END + END rw0_wmask_in[299] + PIN rw0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 36.062 8.145 36.116 ; + END + END rw0_wmask_in[300] + PIN rw0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 36.062 8.325 36.116 ; + END + END rw0_wmask_in[301] + PIN rw0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 36.062 8.505 36.116 ; + END + END rw0_wmask_in[302] + PIN rw0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 36.062 8.685 36.116 ; + END + END rw0_wmask_in[303] + PIN rw0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 36.062 8.865 36.116 ; + END + END rw0_wmask_in[304] + PIN rw0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 36.062 9.045 36.116 ; + END + END rw0_wmask_in[305] + PIN rw0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 36.062 9.225 36.116 ; + END + END rw0_wmask_in[306] + PIN rw0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 36.062 9.405 36.116 ; + END + END rw0_wmask_in[307] + PIN rw0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 36.062 9.585 36.116 ; + END + END rw0_wmask_in[308] + PIN rw0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 36.062 9.765 36.116 ; + END + END rw0_wmask_in[309] + PIN rw0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 36.062 9.945 36.116 ; + END + END rw0_wmask_in[310] + PIN rw0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 36.062 10.125 36.116 ; + END + END rw0_wmask_in[311] + PIN rw0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 36.062 10.305 36.116 ; + END + END rw0_wmask_in[312] + PIN rw0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 36.062 10.485 36.116 ; + END + END rw0_wmask_in[313] + PIN rw0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 36.062 10.665 36.116 ; + END + END rw0_wmask_in[314] + PIN rw0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 36.062 10.845 36.116 ; + END + END rw0_wmask_in[315] + PIN rw0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 36.062 11.025 36.116 ; + END + END rw0_wmask_in[316] + PIN rw0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 36.062 11.205 36.116 ; + END + END rw0_wmask_in[317] + PIN rw0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 36.062 11.385 36.116 ; + END + END rw0_wmask_in[318] + PIN rw0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 36.062 11.565 36.116 ; + END + END rw0_wmask_in[319] + PIN rw0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 36.062 11.745 36.116 ; + END + END rw0_wmask_in[320] + PIN rw0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 36.062 11.925 36.116 ; + END + END rw0_wmask_in[321] + PIN rw0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 36.062 12.105 36.116 ; + END + END rw0_wmask_in[322] + PIN rw0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 36.062 12.285 36.116 ; + END + END rw0_wmask_in[323] + PIN rw0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 36.062 12.465 36.116 ; + END + END rw0_wmask_in[324] + PIN rw0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 36.062 12.645 36.116 ; + END + END rw0_wmask_in[325] + PIN rw0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 36.062 12.825 36.116 ; + END + END rw0_wmask_in[326] + PIN rw0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 36.062 13.005 36.116 ; + END + END rw0_wmask_in[327] + PIN rw0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 36.062 13.185 36.116 ; + END + END rw0_wmask_in[328] + PIN rw0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 36.062 13.365 36.116 ; + END + END rw0_wmask_in[329] + PIN rw0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 36.062 13.545 36.116 ; + END + END rw0_wmask_in[330] + PIN rw0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 36.062 13.725 36.116 ; + END + END rw0_wmask_in[331] + PIN rw0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 36.062 13.905 36.116 ; + END + END rw0_wmask_in[332] + PIN rw0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 36.062 14.085 36.116 ; + END + END rw0_wmask_in[333] + PIN rw0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 36.062 14.265 36.116 ; + END + END rw0_wmask_in[334] + PIN rw0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 36.062 14.445 36.116 ; + END + END rw0_wmask_in[335] + PIN rw0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 36.062 14.625 36.116 ; + END + END rw0_wmask_in[336] + PIN rw0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 36.062 14.805 36.116 ; + END + END rw0_wmask_in[337] + PIN rw0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 36.062 14.985 36.116 ; + END + END rw0_wmask_in[338] + PIN rw0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 36.062 15.165 36.116 ; + END + END rw0_wmask_in[339] + PIN rw0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 36.062 15.345 36.116 ; + END + END rw0_wmask_in[340] + PIN rw0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 36.062 15.525 36.116 ; + END + END rw0_wmask_in[341] + PIN rw0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 36.062 15.705 36.116 ; + END + END rw0_wmask_in[342] + PIN rw0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 36.062 15.885 36.116 ; + END + END rw0_wmask_in[343] + PIN rw0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 36.062 16.065 36.116 ; + END + END rw0_wmask_in[344] + PIN rw0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 36.062 16.245 36.116 ; + END + END rw0_wmask_in[345] + PIN rw0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 36.062 16.425 36.116 ; + END + END rw0_wmask_in[346] + PIN rw0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 36.062 16.605 36.116 ; + END + END rw0_wmask_in[347] + PIN rw0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 36.062 16.785 36.116 ; + END + END rw0_wmask_in[348] + PIN rw0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 36.062 16.965 36.116 ; + END + END rw0_wmask_in[349] + PIN rw0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 36.062 17.145 36.116 ; + END + END rw0_wmask_in[350] + PIN rw0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 36.062 17.325 36.116 ; + END + END rw0_wmask_in[351] + PIN rw0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 36.062 17.505 36.116 ; + END + END rw0_wmask_in[352] + PIN rw0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 36.062 17.685 36.116 ; + END + END rw0_wmask_in[353] + PIN rw0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 36.062 17.865 36.116 ; + END + END rw0_wmask_in[354] + PIN rw0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 36.062 18.045 36.116 ; + END + END rw0_wmask_in[355] + PIN rw0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 36.062 18.225 36.116 ; + END + END rw0_wmask_in[356] + PIN rw0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 36.062 18.405 36.116 ; + END + END rw0_wmask_in[357] + PIN rw0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 36.062 18.585 36.116 ; + END + END rw0_wmask_in[358] + PIN rw0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 36.062 18.765 36.116 ; + END + END rw0_wmask_in[359] + PIN rw0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 36.062 18.945 36.116 ; + END + END rw0_wmask_in[360] + PIN rw0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 36.062 19.125 36.116 ; + END + END rw0_wmask_in[361] + PIN rw0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 36.062 19.305 36.116 ; + END + END rw0_wmask_in[362] + PIN rw0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 36.062 19.485 36.116 ; + END + END rw0_wmask_in[363] + PIN rw0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 36.062 19.665 36.116 ; + END + END rw0_wmask_in[364] + PIN rw0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 36.062 19.845 36.116 ; + END + END rw0_wmask_in[365] + PIN rw0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 36.062 20.025 36.116 ; + END + END rw0_wmask_in[366] + PIN rw0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 36.062 20.205 36.116 ; + END + END rw0_wmask_in[367] + PIN rw0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 36.062 20.385 36.116 ; + END + END rw0_wmask_in[368] + PIN rw0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 36.062 20.565 36.116 ; + END + END rw0_wmask_in[369] + PIN rw0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 36.062 20.745 36.116 ; + END + END rw0_wmask_in[370] + PIN rw0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 36.062 20.925 36.116 ; + END + END rw0_wmask_in[371] + PIN rw0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 36.062 21.105 36.116 ; + END + END rw0_wmask_in[372] + PIN rw0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 36.062 21.285 36.116 ; + END + END rw0_wmask_in[373] + PIN rw0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 36.062 21.465 36.116 ; + END + END rw0_wmask_in[374] + PIN rw0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 36.062 21.645 36.116 ; + END + END rw0_wmask_in[375] + PIN rw0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 36.062 21.825 36.116 ; + END + END rw0_wmask_in[376] + PIN rw0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 36.062 22.005 36.116 ; + END + END rw0_wmask_in[377] + PIN rw0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 36.062 22.185 36.116 ; + END + END rw0_wmask_in[378] + PIN rw0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 36.062 22.365 36.116 ; + END + END rw0_wmask_in[379] + PIN rw0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 36.062 22.545 36.116 ; + END + END rw0_wmask_in[380] + PIN rw0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 36.062 22.725 36.116 ; + END + END rw0_wmask_in[381] + PIN rw0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 36.062 22.905 36.116 ; + END + END rw0_wmask_in[382] + PIN rw0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 36.062 23.085 36.116 ; + END + END rw0_wmask_in[383] + PIN rw0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 36.062 23.265 36.116 ; + END + END rw0_wmask_in[384] + PIN rw0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 36.062 23.445 36.116 ; + END + END rw0_wmask_in[385] + PIN rw0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 36.062 23.625 36.116 ; + END + END rw0_wmask_in[386] + PIN rw0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.787 36.062 23.805 36.116 ; + END + END rw0_wmask_in[387] + PIN rw0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 36.062 23.985 36.116 ; + END + END rw0_wmask_in[388] + PIN rw0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.147 36.062 24.165 36.116 ; + END + END rw0_wmask_in[389] + PIN rw0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.327 36.062 24.345 36.116 ; + END + END rw0_wmask_in[390] + PIN rw0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 36.062 24.525 36.116 ; + END + END rw0_wmask_in[391] + PIN rw0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 36.062 24.705 36.116 ; + END + END rw0_wmask_in[392] + PIN rw0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.867 36.062 24.885 36.116 ; + END + END rw0_wmask_in[393] + PIN rw0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 36.062 25.065 36.116 ; + END + END rw0_wmask_in[394] + PIN rw0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.227 36.062 25.245 36.116 ; + END + END rw0_wmask_in[395] + PIN rw0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.407 36.062 25.425 36.116 ; + END + END rw0_wmask_in[396] + PIN rw0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 36.062 25.605 36.116 ; + END + END rw0_wmask_in[397] + PIN rw0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.767 36.062 25.785 36.116 ; + END + END rw0_wmask_in[398] + PIN rw0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.947 36.062 25.965 36.116 ; + END + END rw0_wmask_in[399] + PIN rw0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 36.062 26.145 36.116 ; + END + END rw0_wmask_in[400] + PIN rw0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.307 36.062 26.325 36.116 ; + END + END rw0_wmask_in[401] + PIN rw0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.487 36.062 26.505 36.116 ; + END + END rw0_wmask_in[402] + PIN rw0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 36.062 26.685 36.116 ; + END + END rw0_wmask_in[403] + PIN rw0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.847 36.062 26.865 36.116 ; + END + END rw0_wmask_in[404] + PIN rw0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.027 36.062 27.045 36.116 ; + END + END rw0_wmask_in[405] + PIN rw0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 36.062 27.225 36.116 ; + END + END rw0_wmask_in[406] + PIN rw0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.387 36.062 27.405 36.116 ; + END + END rw0_wmask_in[407] + PIN rw0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 36.062 27.585 36.116 ; + END + END rw0_wmask_in[408] + PIN rw0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 36.062 27.765 36.116 ; + END + END rw0_wmask_in[409] + PIN rw0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.927 36.062 27.945 36.116 ; + END + END rw0_wmask_in[410] + PIN rw0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.107 36.062 28.125 36.116 ; + END + END rw0_wmask_in[411] + PIN rw0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 36.062 28.305 36.116 ; + END + END rw0_wmask_in[412] + PIN rw0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.467 36.062 28.485 36.116 ; + END + END rw0_wmask_in[413] + PIN rw0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.647 36.062 28.665 36.116 ; + END + END rw0_wmask_in[414] + PIN rw0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 36.062 28.845 36.116 ; + END + END rw0_wmask_in[415] + PIN rw0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 36.062 29.025 36.116 ; + END + END rw0_wmask_in[416] + PIN rw0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.187 36.062 29.205 36.116 ; + END + END rw0_wmask_in[417] + PIN rw0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 36.062 29.385 36.116 ; + END + END rw0_wmask_in[418] + PIN rw0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.547 36.062 29.565 36.116 ; + END + END rw0_wmask_in[419] + PIN rw0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.727 36.062 29.745 36.116 ; + END + END rw0_wmask_in[420] + PIN rw0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 36.062 29.925 36.116 ; + END + END rw0_wmask_in[421] + PIN rw0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.087 36.062 30.105 36.116 ; + END + END rw0_wmask_in[422] + PIN rw0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.267 36.062 30.285 36.116 ; + END + END rw0_wmask_in[423] + PIN rw0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 36.062 30.465 36.116 ; + END + END rw0_wmask_in[424] + PIN rw0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.627 36.062 30.645 36.116 ; + END + END rw0_wmask_in[425] + PIN rw0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.807 36.062 30.825 36.116 ; + END + END rw0_wmask_in[426] + PIN rw0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 36.062 31.005 36.116 ; + END + END rw0_wmask_in[427] + PIN rw0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.167 36.062 31.185 36.116 ; + END + END rw0_wmask_in[428] + PIN rw0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.347 36.062 31.365 36.116 ; + END + END rw0_wmask_in[429] + PIN rw0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 36.062 31.545 36.116 ; + END + END rw0_wmask_in[430] + PIN rw0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.707 36.062 31.725 36.116 ; + END + END rw0_wmask_in[431] + PIN rw0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 36.062 31.905 36.116 ; + END + END rw0_wmask_in[432] + PIN rw0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 36.062 32.085 36.116 ; + END + END rw0_wmask_in[433] + PIN rw0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.247 36.062 32.265 36.116 ; + END + END rw0_wmask_in[434] + PIN rw0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.427 36.062 32.445 36.116 ; + END + END rw0_wmask_in[435] + PIN rw0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 36.062 32.625 36.116 ; + END + END rw0_wmask_in[436] + PIN rw0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.787 36.062 32.805 36.116 ; + END + END rw0_wmask_in[437] + PIN rw0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.967 36.062 32.985 36.116 ; + END + END rw0_wmask_in[438] + PIN rw0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 36.062 33.165 36.116 ; + END + END rw0_wmask_in[439] + PIN rw0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 36.062 33.345 36.116 ; + END + END rw0_wmask_in[440] + PIN rw0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.507 36.062 33.525 36.116 ; + END + END rw0_wmask_in[441] + PIN rw0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 36.062 33.705 36.116 ; + END + END rw0_wmask_in[442] + PIN rw0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.867 36.062 33.885 36.116 ; + END + END rw0_wmask_in[443] + PIN rw0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.047 36.062 34.065 36.116 ; + END + END rw0_wmask_in[444] + PIN rw0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 36.062 34.245 36.116 ; + END + END rw0_wmask_in[445] + PIN rw0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.407 36.062 34.425 36.116 ; + END + END rw0_wmask_in[446] + PIN rw0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.587 36.062 34.605 36.116 ; + END + END rw0_wmask_in[447] + PIN rw0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 36.062 34.785 36.116 ; + END + END rw0_wmask_in[448] + PIN rw0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.947 36.062 34.965 36.116 ; + END + END rw0_wmask_in[449] + PIN rw0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.127 36.062 35.145 36.116 ; + END + END rw0_wmask_in[450] + PIN rw0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 36.062 35.325 36.116 ; + END + END rw0_wmask_in[451] + PIN rw0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.487 36.062 35.505 36.116 ; + END + END rw0_wmask_in[452] + PIN rw0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.667 36.062 35.685 36.116 ; + END + END rw0_wmask_in[453] + PIN rw0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 36.062 35.865 36.116 ; + END + END rw0_wmask_in[454] + PIN rw0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.027 36.062 36.045 36.116 ; + END + END rw0_wmask_in[455] + PIN rw0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 36.062 36.225 36.116 ; + END + END rw0_wmask_in[456] + PIN rw0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 36.062 36.405 36.116 ; + END + END rw0_wmask_in[457] + PIN rw0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.567 36.062 36.585 36.116 ; + END + END rw0_wmask_in[458] + PIN rw0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.747 36.062 36.765 36.116 ; + END + END rw0_wmask_in[459] + PIN rw0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 36.062 36.945 36.116 ; + END + END rw0_wmask_in[460] + PIN rw0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.107 36.062 37.125 36.116 ; + END + END rw0_wmask_in[461] + PIN rw0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.287 36.062 37.305 36.116 ; + END + END rw0_wmask_in[462] + PIN rw0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 36.062 37.485 36.116 ; + END + END rw0_wmask_in[463] + PIN rw0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 36.062 37.665 36.116 ; + END + END rw0_wmask_in[464] + PIN rw0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.827 36.062 37.845 36.116 ; + END + END rw0_wmask_in[465] + PIN rw0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 36.062 38.025 36.116 ; + END + END rw0_wmask_in[466] + PIN rw0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.187 36.062 38.205 36.116 ; + END + END rw0_wmask_in[467] + PIN rw0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.367 36.062 38.385 36.116 ; + END + END rw0_wmask_in[468] + PIN rw0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 36.062 38.565 36.116 ; + END + END rw0_wmask_in[469] + PIN rw0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.727 36.062 38.745 36.116 ; + END + END rw0_wmask_in[470] + PIN rw0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.907 36.062 38.925 36.116 ; + END + END rw0_wmask_in[471] + PIN rw0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 36.062 39.105 36.116 ; + END + END rw0_wmask_in[472] + PIN rw0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.267 36.062 39.285 36.116 ; + END + END rw0_wmask_in[473] + PIN rw0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.447 36.062 39.465 36.116 ; + END + END rw0_wmask_in[474] + PIN rw0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 36.062 39.645 36.116 ; + END + END rw0_wmask_in[475] + PIN rw0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.807 36.062 39.825 36.116 ; + END + END rw0_wmask_in[476] + PIN rw0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.987 36.062 40.005 36.116 ; + END + END rw0_wmask_in[477] + PIN rw0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 36.062 40.185 36.116 ; + END + END rw0_wmask_in[478] + PIN rw0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.347 36.062 40.365 36.116 ; + END + END rw0_wmask_in[479] + PIN rw0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 36.062 40.545 36.116 ; + END + END rw0_wmask_in[480] + PIN rw0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 36.062 40.725 36.116 ; + END + END rw0_wmask_in[481] + PIN rw0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.887 36.062 40.905 36.116 ; + END + END rw0_wmask_in[482] + PIN rw0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.067 36.062 41.085 36.116 ; + END + END rw0_wmask_in[483] + PIN rw0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 36.062 41.265 36.116 ; + END + END rw0_wmask_in[484] + PIN rw0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.427 36.062 41.445 36.116 ; + END + END rw0_wmask_in[485] + PIN rw0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.607 36.062 41.625 36.116 ; + END + END rw0_wmask_in[486] + PIN rw0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 36.062 41.805 36.116 ; + END + END rw0_wmask_in[487] + PIN rw0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 36.062 41.985 36.116 ; + END + END rw0_wmask_in[488] + PIN rw0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.147 36.062 42.165 36.116 ; + END + END rw0_wmask_in[489] + PIN rw0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 36.062 42.345 36.116 ; + END + END rw0_wmask_in[490] + PIN rw0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.507 36.062 42.525 36.116 ; + END + END rw0_wmask_in[491] + PIN rw0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.687 36.062 42.705 36.116 ; + END + END rw0_wmask_in[492] + PIN rw0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 36.062 42.885 36.116 ; + END + END rw0_wmask_in[493] + PIN rw0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.047 36.062 43.065 36.116 ; + END + END rw0_wmask_in[494] + PIN rw0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.227 36.062 43.245 36.116 ; + END + END rw0_wmask_in[495] + PIN rw0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 36.062 43.425 36.116 ; + END + END rw0_wmask_in[496] + PIN rw0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.587 36.062 43.605 36.116 ; + END + END rw0_wmask_in[497] + PIN rw0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.767 36.062 43.785 36.116 ; + END + END rw0_wmask_in[498] + PIN rw0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 36.062 43.965 36.116 ; + END + END rw0_wmask_in[499] + PIN rw0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.127 36.062 44.145 36.116 ; + END + END rw0_wmask_in[500] + PIN rw0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.307 36.062 44.325 36.116 ; + END + END rw0_wmask_in[501] + PIN rw0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 36.062 44.505 36.116 ; + END + END rw0_wmask_in[502] + PIN rw0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.667 36.062 44.685 36.116 ; + END + END rw0_wmask_in[503] + PIN rw0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 36.062 44.865 36.116 ; + END + END rw0_wmask_in[504] + PIN rw0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 36.062 45.045 36.116 ; + END + END rw0_wmask_in[505] + PIN rw0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.207 36.062 45.225 36.116 ; + END + END rw0_wmask_in[506] + PIN rw0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.387 36.062 45.405 36.116 ; + END + END rw0_wmask_in[507] + PIN rw0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 36.062 45.585 36.116 ; + END + END rw0_wmask_in[508] + PIN rw0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.747 36.062 45.765 36.116 ; + END + END rw0_wmask_in[509] + PIN rw0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.927 36.062 45.945 36.116 ; + END + END rw0_wmask_in[510] + PIN rw0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 36.062 46.125 36.116 ; + END + END rw0_wmask_in[511] + PIN rw0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.564 0.072 12.588 ; + END + END rw0_wd_in[0] + PIN rw0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END rw0_wd_in[1] + PIN rw0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.756 0.072 12.780 ; + END + END rw0_wd_in[2] + PIN rw0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.852 0.072 12.876 ; + END + END rw0_wd_in[3] + PIN rw0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END rw0_wd_in[4] + PIN rw0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.044 0.072 13.068 ; + END + END rw0_wd_in[5] + PIN rw0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.140 0.072 13.164 ; + END + END rw0_wd_in[6] + PIN rw0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END rw0_wd_in[7] + PIN rw0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.332 0.072 13.356 ; + END + END rw0_wd_in[8] + PIN rw0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.428 0.072 13.452 ; + END + END rw0_wd_in[9] + PIN rw0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END rw0_wd_in[10] + PIN rw0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.620 0.072 13.644 ; + END + END rw0_wd_in[11] + PIN rw0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.716 0.072 13.740 ; + END + END rw0_wd_in[12] + PIN rw0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END rw0_wd_in[13] + PIN rw0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.908 0.072 13.932 ; + END + END rw0_wd_in[14] + PIN rw0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.004 0.072 14.028 ; + END + END rw0_wd_in[15] + PIN rw0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END rw0_wd_in[16] + PIN rw0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.196 0.072 14.220 ; + END + END rw0_wd_in[17] + PIN rw0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.292 0.072 14.316 ; + END + END rw0_wd_in[18] + PIN rw0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END rw0_wd_in[19] + PIN rw0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.484 0.072 14.508 ; + END + END rw0_wd_in[20] + PIN rw0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.580 0.072 14.604 ; + END + END rw0_wd_in[21] + PIN rw0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END rw0_wd_in[22] + PIN rw0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.772 0.072 14.796 ; + END + END rw0_wd_in[23] + PIN rw0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.868 0.072 14.892 ; + END + END rw0_wd_in[24] + PIN rw0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END rw0_wd_in[25] + PIN rw0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.060 0.072 15.084 ; + END + END rw0_wd_in[26] + PIN rw0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.156 0.072 15.180 ; + END + END rw0_wd_in[27] + PIN rw0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END rw0_wd_in[28] + PIN rw0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.348 0.072 15.372 ; + END + END rw0_wd_in[29] + PIN rw0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.444 0.072 15.468 ; + END + END rw0_wd_in[30] + PIN rw0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END rw0_wd_in[31] + PIN rw0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.636 0.072 15.660 ; + END + END rw0_wd_in[32] + PIN rw0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.732 0.072 15.756 ; + END + END rw0_wd_in[33] + PIN rw0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END rw0_wd_in[34] + PIN rw0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.924 0.072 15.948 ; + END + END rw0_wd_in[35] + PIN rw0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.020 0.072 16.044 ; + END + END rw0_wd_in[36] + PIN rw0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END rw0_wd_in[37] + PIN rw0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.212 0.072 16.236 ; + END + END rw0_wd_in[38] + PIN rw0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.308 0.072 16.332 ; + END + END rw0_wd_in[39] + PIN rw0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END rw0_wd_in[40] + PIN rw0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.500 0.072 16.524 ; + END + END rw0_wd_in[41] + PIN rw0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.596 0.072 16.620 ; + END + END rw0_wd_in[42] + PIN rw0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END rw0_wd_in[43] + PIN rw0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.788 0.072 16.812 ; + END + END rw0_wd_in[44] + PIN rw0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.884 0.072 16.908 ; + END + END rw0_wd_in[45] + PIN rw0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END rw0_wd_in[46] + PIN rw0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.076 0.072 17.100 ; + END + END rw0_wd_in[47] + PIN rw0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.172 0.072 17.196 ; + END + END rw0_wd_in[48] + PIN rw0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END rw0_wd_in[49] + PIN rw0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.364 0.072 17.388 ; + END + END rw0_wd_in[50] + PIN rw0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.460 0.072 17.484 ; + END + END rw0_wd_in[51] + PIN rw0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END rw0_wd_in[52] + PIN rw0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.652 0.072 17.676 ; + END + END rw0_wd_in[53] + PIN rw0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.748 0.072 17.772 ; + END + END rw0_wd_in[54] + PIN rw0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END rw0_wd_in[55] + PIN rw0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.940 0.072 17.964 ; + END + END rw0_wd_in[56] + PIN rw0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.036 0.072 18.060 ; + END + END rw0_wd_in[57] + PIN rw0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END rw0_wd_in[58] + PIN rw0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.228 0.072 18.252 ; + END + END rw0_wd_in[59] + PIN rw0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.324 0.072 18.348 ; + END + END rw0_wd_in[60] + PIN rw0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END rw0_wd_in[61] + PIN rw0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.516 0.072 18.540 ; + END + END rw0_wd_in[62] + PIN rw0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.612 0.072 18.636 ; + END + END rw0_wd_in[63] + PIN rw0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END rw0_wd_in[64] + PIN rw0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.804 0.072 18.828 ; + END + END rw0_wd_in[65] + PIN rw0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.900 0.072 18.924 ; + END + END rw0_wd_in[66] + PIN rw0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END rw0_wd_in[67] + PIN rw0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.092 0.072 19.116 ; + END + END rw0_wd_in[68] + PIN rw0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.188 0.072 19.212 ; + END + END rw0_wd_in[69] + PIN rw0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END rw0_wd_in[70] + PIN rw0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.380 0.072 19.404 ; + END + END rw0_wd_in[71] + PIN rw0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.476 0.072 19.500 ; + END + END rw0_wd_in[72] + PIN rw0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END rw0_wd_in[73] + PIN rw0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.668 0.072 19.692 ; + END + END rw0_wd_in[74] + PIN rw0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.764 0.072 19.788 ; + END + END rw0_wd_in[75] + PIN rw0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END rw0_wd_in[76] + PIN rw0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.956 0.072 19.980 ; + END + END rw0_wd_in[77] + PIN rw0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.052 0.072 20.076 ; + END + END rw0_wd_in[78] + PIN rw0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END rw0_wd_in[79] + PIN rw0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.244 0.072 20.268 ; + END + END rw0_wd_in[80] + PIN rw0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.340 0.072 20.364 ; + END + END rw0_wd_in[81] + PIN rw0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END rw0_wd_in[82] + PIN rw0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.532 0.072 20.556 ; + END + END rw0_wd_in[83] + PIN rw0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.628 0.072 20.652 ; + END + END rw0_wd_in[84] + PIN rw0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END rw0_wd_in[85] + PIN rw0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.820 0.072 20.844 ; + END + END rw0_wd_in[86] + PIN rw0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.916 0.072 20.940 ; + END + END rw0_wd_in[87] + PIN rw0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END rw0_wd_in[88] + PIN rw0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.108 0.072 21.132 ; + END + END rw0_wd_in[89] + PIN rw0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.204 0.072 21.228 ; + END + END rw0_wd_in[90] + PIN rw0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END rw0_wd_in[91] + PIN rw0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.396 0.072 21.420 ; + END + END rw0_wd_in[92] + PIN rw0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.492 0.072 21.516 ; + END + END rw0_wd_in[93] + PIN rw0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END rw0_wd_in[94] + PIN rw0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.684 0.072 21.708 ; + END + END rw0_wd_in[95] + PIN rw0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.780 0.072 21.804 ; + END + END rw0_wd_in[96] + PIN rw0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END rw0_wd_in[97] + PIN rw0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.972 0.072 21.996 ; + END + END rw0_wd_in[98] + PIN rw0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.068 0.072 22.092 ; + END + END rw0_wd_in[99] + PIN rw0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END rw0_wd_in[100] + PIN rw0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.260 0.072 22.284 ; + END + END rw0_wd_in[101] + PIN rw0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.356 0.072 22.380 ; + END + END rw0_wd_in[102] + PIN rw0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END rw0_wd_in[103] + PIN rw0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.548 0.072 22.572 ; + END + END rw0_wd_in[104] + PIN rw0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.644 0.072 22.668 ; + END + END rw0_wd_in[105] + PIN rw0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END rw0_wd_in[106] + PIN rw0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.836 0.072 22.860 ; + END + END rw0_wd_in[107] + PIN rw0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.932 0.072 22.956 ; + END + END rw0_wd_in[108] + PIN rw0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END rw0_wd_in[109] + PIN rw0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.124 0.072 23.148 ; + END + END rw0_wd_in[110] + PIN rw0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.220 0.072 23.244 ; + END + END rw0_wd_in[111] + PIN rw0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END rw0_wd_in[112] + PIN rw0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.412 0.072 23.436 ; + END + END rw0_wd_in[113] + PIN rw0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.508 0.072 23.532 ; + END + END rw0_wd_in[114] + PIN rw0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END rw0_wd_in[115] + PIN rw0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.700 0.072 23.724 ; + END + END rw0_wd_in[116] + PIN rw0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.796 0.072 23.820 ; + END + END rw0_wd_in[117] + PIN rw0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END rw0_wd_in[118] + PIN rw0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.988 0.072 24.012 ; + END + END rw0_wd_in[119] + PIN rw0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.084 0.072 24.108 ; + END + END rw0_wd_in[120] + PIN rw0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END rw0_wd_in[121] + PIN rw0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.276 0.072 24.300 ; + END + END rw0_wd_in[122] + PIN rw0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.372 0.072 24.396 ; + END + END rw0_wd_in[123] + PIN rw0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END rw0_wd_in[124] + PIN rw0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.564 0.072 24.588 ; + END + END rw0_wd_in[125] + PIN rw0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.660 0.072 24.684 ; + END + END rw0_wd_in[126] + PIN rw0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END rw0_wd_in[127] + PIN rw0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.564 104.012 12.588 ; + END + END rw0_wd_in[128] + PIN rw0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.660 104.012 12.684 ; + END + END rw0_wd_in[129] + PIN rw0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.756 104.012 12.780 ; + END + END rw0_wd_in[130] + PIN rw0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.852 104.012 12.876 ; + END + END rw0_wd_in[131] + PIN rw0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 12.948 104.012 12.972 ; + END + END rw0_wd_in[132] + PIN rw0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.044 104.012 13.068 ; + END + END rw0_wd_in[133] + PIN rw0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.140 104.012 13.164 ; + END + END rw0_wd_in[134] + PIN rw0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.236 104.012 13.260 ; + END + END rw0_wd_in[135] + PIN rw0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.332 104.012 13.356 ; + END + END rw0_wd_in[136] + PIN rw0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.428 104.012 13.452 ; + END + END rw0_wd_in[137] + PIN rw0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.524 104.012 13.548 ; + END + END rw0_wd_in[138] + PIN rw0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.620 104.012 13.644 ; + END + END rw0_wd_in[139] + PIN rw0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.716 104.012 13.740 ; + END + END rw0_wd_in[140] + PIN rw0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.812 104.012 13.836 ; + END + END rw0_wd_in[141] + PIN rw0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 13.908 104.012 13.932 ; + END + END rw0_wd_in[142] + PIN rw0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.004 104.012 14.028 ; + END + END rw0_wd_in[143] + PIN rw0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.100 104.012 14.124 ; + END + END rw0_wd_in[144] + PIN rw0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.196 104.012 14.220 ; + END + END rw0_wd_in[145] + PIN rw0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.292 104.012 14.316 ; + END + END rw0_wd_in[146] + PIN rw0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.388 104.012 14.412 ; + END + END rw0_wd_in[147] + PIN rw0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.484 104.012 14.508 ; + END + END rw0_wd_in[148] + PIN rw0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.580 104.012 14.604 ; + END + END rw0_wd_in[149] + PIN rw0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.676 104.012 14.700 ; + END + END rw0_wd_in[150] + PIN rw0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.772 104.012 14.796 ; + END + END rw0_wd_in[151] + PIN rw0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.868 104.012 14.892 ; + END + END rw0_wd_in[152] + PIN rw0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 14.964 104.012 14.988 ; + END + END rw0_wd_in[153] + PIN rw0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.060 104.012 15.084 ; + END + END rw0_wd_in[154] + PIN rw0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.156 104.012 15.180 ; + END + END rw0_wd_in[155] + PIN rw0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.252 104.012 15.276 ; + END + END rw0_wd_in[156] + PIN rw0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.348 104.012 15.372 ; + END + END rw0_wd_in[157] + PIN rw0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.444 104.012 15.468 ; + END + END rw0_wd_in[158] + PIN rw0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.540 104.012 15.564 ; + END + END rw0_wd_in[159] + PIN rw0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.636 104.012 15.660 ; + END + END rw0_wd_in[160] + PIN rw0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.732 104.012 15.756 ; + END + END rw0_wd_in[161] + PIN rw0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.828 104.012 15.852 ; + END + END rw0_wd_in[162] + PIN rw0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 15.924 104.012 15.948 ; + END + END rw0_wd_in[163] + PIN rw0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.020 104.012 16.044 ; + END + END rw0_wd_in[164] + PIN rw0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.116 104.012 16.140 ; + END + END rw0_wd_in[165] + PIN rw0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.212 104.012 16.236 ; + END + END rw0_wd_in[166] + PIN rw0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.308 104.012 16.332 ; + END + END rw0_wd_in[167] + PIN rw0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.404 104.012 16.428 ; + END + END rw0_wd_in[168] + PIN rw0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.500 104.012 16.524 ; + END + END rw0_wd_in[169] + PIN rw0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.596 104.012 16.620 ; + END + END rw0_wd_in[170] + PIN rw0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.692 104.012 16.716 ; + END + END rw0_wd_in[171] + PIN rw0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.788 104.012 16.812 ; + END + END rw0_wd_in[172] + PIN rw0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.884 104.012 16.908 ; + END + END rw0_wd_in[173] + PIN rw0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 16.980 104.012 17.004 ; + END + END rw0_wd_in[174] + PIN rw0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.076 104.012 17.100 ; + END + END rw0_wd_in[175] + PIN rw0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.172 104.012 17.196 ; + END + END rw0_wd_in[176] + PIN rw0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.268 104.012 17.292 ; + END + END rw0_wd_in[177] + PIN rw0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.364 104.012 17.388 ; + END + END rw0_wd_in[178] + PIN rw0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.460 104.012 17.484 ; + END + END rw0_wd_in[179] + PIN rw0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.556 104.012 17.580 ; + END + END rw0_wd_in[180] + PIN rw0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.652 104.012 17.676 ; + END + END rw0_wd_in[181] + PIN rw0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.748 104.012 17.772 ; + END + END rw0_wd_in[182] + PIN rw0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.844 104.012 17.868 ; + END + END rw0_wd_in[183] + PIN rw0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 17.940 104.012 17.964 ; + END + END rw0_wd_in[184] + PIN rw0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.036 104.012 18.060 ; + END + END rw0_wd_in[185] + PIN rw0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.132 104.012 18.156 ; + END + END rw0_wd_in[186] + PIN rw0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.228 104.012 18.252 ; + END + END rw0_wd_in[187] + PIN rw0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.324 104.012 18.348 ; + END + END rw0_wd_in[188] + PIN rw0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.420 104.012 18.444 ; + END + END rw0_wd_in[189] + PIN rw0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.516 104.012 18.540 ; + END + END rw0_wd_in[190] + PIN rw0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.612 104.012 18.636 ; + END + END rw0_wd_in[191] + PIN rw0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.708 104.012 18.732 ; + END + END rw0_wd_in[192] + PIN rw0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.804 104.012 18.828 ; + END + END rw0_wd_in[193] + PIN rw0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.900 104.012 18.924 ; + END + END rw0_wd_in[194] + PIN rw0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 18.996 104.012 19.020 ; + END + END rw0_wd_in[195] + PIN rw0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.092 104.012 19.116 ; + END + END rw0_wd_in[196] + PIN rw0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.188 104.012 19.212 ; + END + END rw0_wd_in[197] + PIN rw0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.284 104.012 19.308 ; + END + END rw0_wd_in[198] + PIN rw0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.380 104.012 19.404 ; + END + END rw0_wd_in[199] + PIN rw0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.476 104.012 19.500 ; + END + END rw0_wd_in[200] + PIN rw0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.572 104.012 19.596 ; + END + END rw0_wd_in[201] + PIN rw0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.668 104.012 19.692 ; + END + END rw0_wd_in[202] + PIN rw0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.764 104.012 19.788 ; + END + END rw0_wd_in[203] + PIN rw0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.860 104.012 19.884 ; + END + END rw0_wd_in[204] + PIN rw0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 19.956 104.012 19.980 ; + END + END rw0_wd_in[205] + PIN rw0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.052 104.012 20.076 ; + END + END rw0_wd_in[206] + PIN rw0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.148 104.012 20.172 ; + END + END rw0_wd_in[207] + PIN rw0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.244 104.012 20.268 ; + END + END rw0_wd_in[208] + PIN rw0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.340 104.012 20.364 ; + END + END rw0_wd_in[209] + PIN rw0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.436 104.012 20.460 ; + END + END rw0_wd_in[210] + PIN rw0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.532 104.012 20.556 ; + END + END rw0_wd_in[211] + PIN rw0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.628 104.012 20.652 ; + END + END rw0_wd_in[212] + PIN rw0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.724 104.012 20.748 ; + END + END rw0_wd_in[213] + PIN rw0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.820 104.012 20.844 ; + END + END rw0_wd_in[214] + PIN rw0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 20.916 104.012 20.940 ; + END + END rw0_wd_in[215] + PIN rw0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.012 104.012 21.036 ; + END + END rw0_wd_in[216] + PIN rw0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.108 104.012 21.132 ; + END + END rw0_wd_in[217] + PIN rw0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.204 104.012 21.228 ; + END + END rw0_wd_in[218] + PIN rw0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.300 104.012 21.324 ; + END + END rw0_wd_in[219] + PIN rw0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.396 104.012 21.420 ; + END + END rw0_wd_in[220] + PIN rw0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.492 104.012 21.516 ; + END + END rw0_wd_in[221] + PIN rw0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.588 104.012 21.612 ; + END + END rw0_wd_in[222] + PIN rw0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.684 104.012 21.708 ; + END + END rw0_wd_in[223] + PIN rw0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.780 104.012 21.804 ; + END + END rw0_wd_in[224] + PIN rw0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.876 104.012 21.900 ; + END + END rw0_wd_in[225] + PIN rw0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 21.972 104.012 21.996 ; + END + END rw0_wd_in[226] + PIN rw0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.068 104.012 22.092 ; + END + END rw0_wd_in[227] + PIN rw0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.164 104.012 22.188 ; + END + END rw0_wd_in[228] + PIN rw0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.260 104.012 22.284 ; + END + END rw0_wd_in[229] + PIN rw0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.356 104.012 22.380 ; + END + END rw0_wd_in[230] + PIN rw0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.452 104.012 22.476 ; + END + END rw0_wd_in[231] + PIN rw0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.548 104.012 22.572 ; + END + END rw0_wd_in[232] + PIN rw0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.644 104.012 22.668 ; + END + END rw0_wd_in[233] + PIN rw0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.740 104.012 22.764 ; + END + END rw0_wd_in[234] + PIN rw0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.836 104.012 22.860 ; + END + END rw0_wd_in[235] + PIN rw0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 22.932 104.012 22.956 ; + END + END rw0_wd_in[236] + PIN rw0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.028 104.012 23.052 ; + END + END rw0_wd_in[237] + PIN rw0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.124 104.012 23.148 ; + END + END rw0_wd_in[238] + PIN rw0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.220 104.012 23.244 ; + END + END rw0_wd_in[239] + PIN rw0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.316 104.012 23.340 ; + END + END rw0_wd_in[240] + PIN rw0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.412 104.012 23.436 ; + END + END rw0_wd_in[241] + PIN rw0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.508 104.012 23.532 ; + END + END rw0_wd_in[242] + PIN rw0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.604 104.012 23.628 ; + END + END rw0_wd_in[243] + PIN rw0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.700 104.012 23.724 ; + END + END rw0_wd_in[244] + PIN rw0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.796 104.012 23.820 ; + END + END rw0_wd_in[245] + PIN rw0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.892 104.012 23.916 ; + END + END rw0_wd_in[246] + PIN rw0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 23.988 104.012 24.012 ; + END + END rw0_wd_in[247] + PIN rw0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.084 104.012 24.108 ; + END + END rw0_wd_in[248] + PIN rw0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.180 104.012 24.204 ; + END + END rw0_wd_in[249] + PIN rw0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.276 104.012 24.300 ; + END + END rw0_wd_in[250] + PIN rw0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.372 104.012 24.396 ; + END + END rw0_wd_in[251] + PIN rw0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.468 104.012 24.492 ; + END + END rw0_wd_in[252] + PIN rw0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.564 104.012 24.588 ; + END + END rw0_wd_in[253] + PIN rw0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.660 104.012 24.684 ; + END + END rw0_wd_in[254] + PIN rw0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.756 104.012 24.780 ; + END + END rw0_wd_in[255] + PIN rw0_wd_in[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END rw0_wd_in[256] + PIN rw0_wd_in[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.387 0.000 0.405 0.054 ; + END + END rw0_wd_in[257] + PIN rw0_wd_in[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.567 0.000 0.585 0.054 ; + END + END rw0_wd_in[258] + PIN rw0_wd_in[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.747 0.000 0.765 0.054 ; + END + END rw0_wd_in[259] + PIN rw0_wd_in[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.927 0.000 0.945 0.054 ; + END + END rw0_wd_in[260] + PIN rw0_wd_in[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.107 0.000 1.125 0.054 ; + END + END rw0_wd_in[261] + PIN rw0_wd_in[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.287 0.000 1.305 0.054 ; + END + END rw0_wd_in[262] + PIN rw0_wd_in[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.467 0.000 1.485 0.054 ; + END + END rw0_wd_in[263] + PIN rw0_wd_in[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END rw0_wd_in[264] + PIN rw0_wd_in[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.827 0.000 1.845 0.054 ; + END + END rw0_wd_in[265] + PIN rw0_wd_in[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.007 0.000 2.025 0.054 ; + END + END rw0_wd_in[266] + PIN rw0_wd_in[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.187 0.000 2.205 0.054 ; + END + END rw0_wd_in[267] + PIN rw0_wd_in[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.367 0.000 2.385 0.054 ; + END + END rw0_wd_in[268] + PIN rw0_wd_in[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.547 0.000 2.565 0.054 ; + END + END rw0_wd_in[269] + PIN rw0_wd_in[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.727 0.000 2.745 0.054 ; + END + END rw0_wd_in[270] + PIN rw0_wd_in[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.907 0.000 2.925 0.054 ; + END + END rw0_wd_in[271] + PIN rw0_wd_in[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END rw0_wd_in[272] + PIN rw0_wd_in[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.267 0.000 3.285 0.054 ; + END + END rw0_wd_in[273] + PIN rw0_wd_in[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.447 0.000 3.465 0.054 ; + END + END rw0_wd_in[274] + PIN rw0_wd_in[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.627 0.000 3.645 0.054 ; + END + END rw0_wd_in[275] + PIN rw0_wd_in[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.807 0.000 3.825 0.054 ; + END + END rw0_wd_in[276] + PIN rw0_wd_in[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.987 0.000 4.005 0.054 ; + END + END rw0_wd_in[277] + PIN rw0_wd_in[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.167 0.000 4.185 0.054 ; + END + END rw0_wd_in[278] + PIN rw0_wd_in[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.347 0.000 4.365 0.054 ; + END + END rw0_wd_in[279] + PIN rw0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END rw0_wd_in[280] + PIN rw0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.707 0.000 4.725 0.054 ; + END + END rw0_wd_in[281] + PIN rw0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.887 0.000 4.905 0.054 ; + END + END rw0_wd_in[282] + PIN rw0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.067 0.000 5.085 0.054 ; + END + END rw0_wd_in[283] + PIN rw0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.247 0.000 5.265 0.054 ; + END + END rw0_wd_in[284] + PIN rw0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.427 0.000 5.445 0.054 ; + END + END rw0_wd_in[285] + PIN rw0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.607 0.000 5.625 0.054 ; + END + END rw0_wd_in[286] + PIN rw0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.787 0.000 5.805 0.054 ; + END + END rw0_wd_in[287] + PIN rw0_wd_in[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END rw0_wd_in[288] + PIN rw0_wd_in[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.147 0.000 6.165 0.054 ; + END + END rw0_wd_in[289] + PIN rw0_wd_in[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.327 0.000 6.345 0.054 ; + END + END rw0_wd_in[290] + PIN rw0_wd_in[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.507 0.000 6.525 0.054 ; + END + END rw0_wd_in[291] + PIN rw0_wd_in[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.687 0.000 6.705 0.054 ; + END + END rw0_wd_in[292] + PIN rw0_wd_in[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.867 0.000 6.885 0.054 ; + END + END rw0_wd_in[293] + PIN rw0_wd_in[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.047 0.000 7.065 0.054 ; + END + END rw0_wd_in[294] + PIN rw0_wd_in[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.227 0.000 7.245 0.054 ; + END + END rw0_wd_in[295] + PIN rw0_wd_in[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END rw0_wd_in[296] + PIN rw0_wd_in[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.587 0.000 7.605 0.054 ; + END + END rw0_wd_in[297] + PIN rw0_wd_in[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.767 0.000 7.785 0.054 ; + END + END rw0_wd_in[298] + PIN rw0_wd_in[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.947 0.000 7.965 0.054 ; + END + END rw0_wd_in[299] + PIN rw0_wd_in[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.127 0.000 8.145 0.054 ; + END + END rw0_wd_in[300] + PIN rw0_wd_in[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.307 0.000 8.325 0.054 ; + END + END rw0_wd_in[301] + PIN rw0_wd_in[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.487 0.000 8.505 0.054 ; + END + END rw0_wd_in[302] + PIN rw0_wd_in[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.667 0.000 8.685 0.054 ; + END + END rw0_wd_in[303] + PIN rw0_wd_in[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END rw0_wd_in[304] + PIN rw0_wd_in[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.027 0.000 9.045 0.054 ; + END + END rw0_wd_in[305] + PIN rw0_wd_in[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.207 0.000 9.225 0.054 ; + END + END rw0_wd_in[306] + PIN rw0_wd_in[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.387 0.000 9.405 0.054 ; + END + END rw0_wd_in[307] + PIN rw0_wd_in[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.567 0.000 9.585 0.054 ; + END + END rw0_wd_in[308] + PIN rw0_wd_in[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.747 0.000 9.765 0.054 ; + END + END rw0_wd_in[309] + PIN rw0_wd_in[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.927 0.000 9.945 0.054 ; + END + END rw0_wd_in[310] + PIN rw0_wd_in[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.107 0.000 10.125 0.054 ; + END + END rw0_wd_in[311] + PIN rw0_wd_in[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END rw0_wd_in[312] + PIN rw0_wd_in[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.467 0.000 10.485 0.054 ; + END + END rw0_wd_in[313] + PIN rw0_wd_in[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.647 0.000 10.665 0.054 ; + END + END rw0_wd_in[314] + PIN rw0_wd_in[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.827 0.000 10.845 0.054 ; + END + END rw0_wd_in[315] + PIN rw0_wd_in[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.007 0.000 11.025 0.054 ; + END + END rw0_wd_in[316] + PIN rw0_wd_in[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.187 0.000 11.205 0.054 ; + END + END rw0_wd_in[317] + PIN rw0_wd_in[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.367 0.000 11.385 0.054 ; + END + END rw0_wd_in[318] + PIN rw0_wd_in[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.547 0.000 11.565 0.054 ; + END + END rw0_wd_in[319] + PIN rw0_wd_in[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END rw0_wd_in[320] + PIN rw0_wd_in[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.907 0.000 11.925 0.054 ; + END + END rw0_wd_in[321] + PIN rw0_wd_in[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.087 0.000 12.105 0.054 ; + END + END rw0_wd_in[322] + PIN rw0_wd_in[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.267 0.000 12.285 0.054 ; + END + END rw0_wd_in[323] + PIN rw0_wd_in[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.447 0.000 12.465 0.054 ; + END + END rw0_wd_in[324] + PIN rw0_wd_in[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.627 0.000 12.645 0.054 ; + END + END rw0_wd_in[325] + PIN rw0_wd_in[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.807 0.000 12.825 0.054 ; + END + END rw0_wd_in[326] + PIN rw0_wd_in[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.987 0.000 13.005 0.054 ; + END + END rw0_wd_in[327] + PIN rw0_wd_in[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END rw0_wd_in[328] + PIN rw0_wd_in[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.347 0.000 13.365 0.054 ; + END + END rw0_wd_in[329] + PIN rw0_wd_in[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.527 0.000 13.545 0.054 ; + END + END rw0_wd_in[330] + PIN rw0_wd_in[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.707 0.000 13.725 0.054 ; + END + END rw0_wd_in[331] + PIN rw0_wd_in[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.887 0.000 13.905 0.054 ; + END + END rw0_wd_in[332] + PIN rw0_wd_in[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.067 0.000 14.085 0.054 ; + END + END rw0_wd_in[333] + PIN rw0_wd_in[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.247 0.000 14.265 0.054 ; + END + END rw0_wd_in[334] + PIN rw0_wd_in[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.427 0.000 14.445 0.054 ; + END + END rw0_wd_in[335] + PIN rw0_wd_in[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END rw0_wd_in[336] + PIN rw0_wd_in[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.787 0.000 14.805 0.054 ; + END + END rw0_wd_in[337] + PIN rw0_wd_in[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.967 0.000 14.985 0.054 ; + END + END rw0_wd_in[338] + PIN rw0_wd_in[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.147 0.000 15.165 0.054 ; + END + END rw0_wd_in[339] + PIN rw0_wd_in[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.327 0.000 15.345 0.054 ; + END + END rw0_wd_in[340] + PIN rw0_wd_in[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.507 0.000 15.525 0.054 ; + END + END rw0_wd_in[341] + PIN rw0_wd_in[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.687 0.000 15.705 0.054 ; + END + END rw0_wd_in[342] + PIN rw0_wd_in[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.867 0.000 15.885 0.054 ; + END + END rw0_wd_in[343] + PIN rw0_wd_in[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END rw0_wd_in[344] + PIN rw0_wd_in[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.227 0.000 16.245 0.054 ; + END + END rw0_wd_in[345] + PIN rw0_wd_in[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.407 0.000 16.425 0.054 ; + END + END rw0_wd_in[346] + PIN rw0_wd_in[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.587 0.000 16.605 0.054 ; + END + END rw0_wd_in[347] + PIN rw0_wd_in[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.767 0.000 16.785 0.054 ; + END + END rw0_wd_in[348] + PIN rw0_wd_in[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.947 0.000 16.965 0.054 ; + END + END rw0_wd_in[349] + PIN rw0_wd_in[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.127 0.000 17.145 0.054 ; + END + END rw0_wd_in[350] + PIN rw0_wd_in[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.307 0.000 17.325 0.054 ; + END + END rw0_wd_in[351] + PIN rw0_wd_in[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END rw0_wd_in[352] + PIN rw0_wd_in[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.667 0.000 17.685 0.054 ; + END + END rw0_wd_in[353] + PIN rw0_wd_in[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.847 0.000 17.865 0.054 ; + END + END rw0_wd_in[354] + PIN rw0_wd_in[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.027 0.000 18.045 0.054 ; + END + END rw0_wd_in[355] + PIN rw0_wd_in[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.207 0.000 18.225 0.054 ; + END + END rw0_wd_in[356] + PIN rw0_wd_in[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.387 0.000 18.405 0.054 ; + END + END rw0_wd_in[357] + PIN rw0_wd_in[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.567 0.000 18.585 0.054 ; + END + END rw0_wd_in[358] + PIN rw0_wd_in[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.747 0.000 18.765 0.054 ; + END + END rw0_wd_in[359] + PIN rw0_wd_in[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END rw0_wd_in[360] + PIN rw0_wd_in[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.107 0.000 19.125 0.054 ; + END + END rw0_wd_in[361] + PIN rw0_wd_in[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.287 0.000 19.305 0.054 ; + END + END rw0_wd_in[362] + PIN rw0_wd_in[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.467 0.000 19.485 0.054 ; + END + END rw0_wd_in[363] + PIN rw0_wd_in[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.647 0.000 19.665 0.054 ; + END + END rw0_wd_in[364] + PIN rw0_wd_in[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.827 0.000 19.845 0.054 ; + END + END rw0_wd_in[365] + PIN rw0_wd_in[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.007 0.000 20.025 0.054 ; + END + END rw0_wd_in[366] + PIN rw0_wd_in[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.187 0.000 20.205 0.054 ; + END + END rw0_wd_in[367] + PIN rw0_wd_in[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END rw0_wd_in[368] + PIN rw0_wd_in[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.547 0.000 20.565 0.054 ; + END + END rw0_wd_in[369] + PIN rw0_wd_in[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.727 0.000 20.745 0.054 ; + END + END rw0_wd_in[370] + PIN rw0_wd_in[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.907 0.000 20.925 0.054 ; + END + END rw0_wd_in[371] + PIN rw0_wd_in[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.087 0.000 21.105 0.054 ; + END + END rw0_wd_in[372] + PIN rw0_wd_in[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.267 0.000 21.285 0.054 ; + END + END rw0_wd_in[373] + PIN rw0_wd_in[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.447 0.000 21.465 0.054 ; + END + END rw0_wd_in[374] + PIN rw0_wd_in[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.627 0.000 21.645 0.054 ; + END + END rw0_wd_in[375] + PIN rw0_wd_in[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END rw0_wd_in[376] + PIN rw0_wd_in[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.987 0.000 22.005 0.054 ; + END + END rw0_wd_in[377] + PIN rw0_wd_in[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.167 0.000 22.185 0.054 ; + END + END rw0_wd_in[378] + PIN rw0_wd_in[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.347 0.000 22.365 0.054 ; + END + END rw0_wd_in[379] + PIN rw0_wd_in[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.527 0.000 22.545 0.054 ; + END + END rw0_wd_in[380] + PIN rw0_wd_in[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.707 0.000 22.725 0.054 ; + END + END rw0_wd_in[381] + PIN rw0_wd_in[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.887 0.000 22.905 0.054 ; + END + END rw0_wd_in[382] + PIN rw0_wd_in[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.067 0.000 23.085 0.054 ; + END + END rw0_wd_in[383] + PIN rw0_wd_in[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END rw0_wd_in[384] + PIN rw0_wd_in[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.427 0.000 23.445 0.054 ; + END + END rw0_wd_in[385] + PIN rw0_wd_in[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.607 0.000 23.625 0.054 ; + END + END rw0_wd_in[386] + PIN rw0_wd_in[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.787 0.000 23.805 0.054 ; + END + END rw0_wd_in[387] + PIN rw0_wd_in[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.967 0.000 23.985 0.054 ; + END + END rw0_wd_in[388] + PIN rw0_wd_in[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.147 0.000 24.165 0.054 ; + END + END rw0_wd_in[389] + PIN rw0_wd_in[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.327 0.000 24.345 0.054 ; + END + END rw0_wd_in[390] + PIN rw0_wd_in[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.507 0.000 24.525 0.054 ; + END + END rw0_wd_in[391] + PIN rw0_wd_in[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END rw0_wd_in[392] + PIN rw0_wd_in[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.867 0.000 24.885 0.054 ; + END + END rw0_wd_in[393] + PIN rw0_wd_in[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.047 0.000 25.065 0.054 ; + END + END rw0_wd_in[394] + PIN rw0_wd_in[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.227 0.000 25.245 0.054 ; + END + END rw0_wd_in[395] + PIN rw0_wd_in[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.407 0.000 25.425 0.054 ; + END + END rw0_wd_in[396] + PIN rw0_wd_in[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.587 0.000 25.605 0.054 ; + END + END rw0_wd_in[397] + PIN rw0_wd_in[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.767 0.000 25.785 0.054 ; + END + END rw0_wd_in[398] + PIN rw0_wd_in[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.947 0.000 25.965 0.054 ; + END + END rw0_wd_in[399] + PIN rw0_wd_in[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END rw0_wd_in[400] + PIN rw0_wd_in[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.307 0.000 26.325 0.054 ; + END + END rw0_wd_in[401] + PIN rw0_wd_in[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.487 0.000 26.505 0.054 ; + END + END rw0_wd_in[402] + PIN rw0_wd_in[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.667 0.000 26.685 0.054 ; + END + END rw0_wd_in[403] + PIN rw0_wd_in[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.847 0.000 26.865 0.054 ; + END + END rw0_wd_in[404] + PIN rw0_wd_in[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.027 0.000 27.045 0.054 ; + END + END rw0_wd_in[405] + PIN rw0_wd_in[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.207 0.000 27.225 0.054 ; + END + END rw0_wd_in[406] + PIN rw0_wd_in[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.387 0.000 27.405 0.054 ; + END + END rw0_wd_in[407] + PIN rw0_wd_in[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END rw0_wd_in[408] + PIN rw0_wd_in[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.747 0.000 27.765 0.054 ; + END + END rw0_wd_in[409] + PIN rw0_wd_in[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.927 0.000 27.945 0.054 ; + END + END rw0_wd_in[410] + PIN rw0_wd_in[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.107 0.000 28.125 0.054 ; + END + END rw0_wd_in[411] + PIN rw0_wd_in[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.287 0.000 28.305 0.054 ; + END + END rw0_wd_in[412] + PIN rw0_wd_in[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.467 0.000 28.485 0.054 ; + END + END rw0_wd_in[413] + PIN rw0_wd_in[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.647 0.000 28.665 0.054 ; + END + END rw0_wd_in[414] + PIN rw0_wd_in[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.827 0.000 28.845 0.054 ; + END + END rw0_wd_in[415] + PIN rw0_wd_in[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END rw0_wd_in[416] + PIN rw0_wd_in[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.187 0.000 29.205 0.054 ; + END + END rw0_wd_in[417] + PIN rw0_wd_in[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.367 0.000 29.385 0.054 ; + END + END rw0_wd_in[418] + PIN rw0_wd_in[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.547 0.000 29.565 0.054 ; + END + END rw0_wd_in[419] + PIN rw0_wd_in[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.727 0.000 29.745 0.054 ; + END + END rw0_wd_in[420] + PIN rw0_wd_in[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.907 0.000 29.925 0.054 ; + END + END rw0_wd_in[421] + PIN rw0_wd_in[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.087 0.000 30.105 0.054 ; + END + END rw0_wd_in[422] + PIN rw0_wd_in[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.267 0.000 30.285 0.054 ; + END + END rw0_wd_in[423] + PIN rw0_wd_in[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END rw0_wd_in[424] + PIN rw0_wd_in[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.627 0.000 30.645 0.054 ; + END + END rw0_wd_in[425] + PIN rw0_wd_in[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.807 0.000 30.825 0.054 ; + END + END rw0_wd_in[426] + PIN rw0_wd_in[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.987 0.000 31.005 0.054 ; + END + END rw0_wd_in[427] + PIN rw0_wd_in[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.167 0.000 31.185 0.054 ; + END + END rw0_wd_in[428] + PIN rw0_wd_in[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.347 0.000 31.365 0.054 ; + END + END rw0_wd_in[429] + PIN rw0_wd_in[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.527 0.000 31.545 0.054 ; + END + END rw0_wd_in[430] + PIN rw0_wd_in[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.707 0.000 31.725 0.054 ; + END + END rw0_wd_in[431] + PIN rw0_wd_in[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END rw0_wd_in[432] + PIN rw0_wd_in[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.067 0.000 32.085 0.054 ; + END + END rw0_wd_in[433] + PIN rw0_wd_in[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.247 0.000 32.265 0.054 ; + END + END rw0_wd_in[434] + PIN rw0_wd_in[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.427 0.000 32.445 0.054 ; + END + END rw0_wd_in[435] + PIN rw0_wd_in[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.607 0.000 32.625 0.054 ; + END + END rw0_wd_in[436] + PIN rw0_wd_in[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.787 0.000 32.805 0.054 ; + END + END rw0_wd_in[437] + PIN rw0_wd_in[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.967 0.000 32.985 0.054 ; + END + END rw0_wd_in[438] + PIN rw0_wd_in[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.147 0.000 33.165 0.054 ; + END + END rw0_wd_in[439] + PIN rw0_wd_in[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END rw0_wd_in[440] + PIN rw0_wd_in[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.507 0.000 33.525 0.054 ; + END + END rw0_wd_in[441] + PIN rw0_wd_in[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.687 0.000 33.705 0.054 ; + END + END rw0_wd_in[442] + PIN rw0_wd_in[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.867 0.000 33.885 0.054 ; + END + END rw0_wd_in[443] + PIN rw0_wd_in[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.047 0.000 34.065 0.054 ; + END + END rw0_wd_in[444] + PIN rw0_wd_in[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.227 0.000 34.245 0.054 ; + END + END rw0_wd_in[445] + PIN rw0_wd_in[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.407 0.000 34.425 0.054 ; + END + END rw0_wd_in[446] + PIN rw0_wd_in[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.587 0.000 34.605 0.054 ; + END + END rw0_wd_in[447] + PIN rw0_wd_in[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END rw0_wd_in[448] + PIN rw0_wd_in[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.947 0.000 34.965 0.054 ; + END + END rw0_wd_in[449] + PIN rw0_wd_in[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.127 0.000 35.145 0.054 ; + END + END rw0_wd_in[450] + PIN rw0_wd_in[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.307 0.000 35.325 0.054 ; + END + END rw0_wd_in[451] + PIN rw0_wd_in[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.487 0.000 35.505 0.054 ; + END + END rw0_wd_in[452] + PIN rw0_wd_in[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.667 0.000 35.685 0.054 ; + END + END rw0_wd_in[453] + PIN rw0_wd_in[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.847 0.000 35.865 0.054 ; + END + END rw0_wd_in[454] + PIN rw0_wd_in[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.027 0.000 36.045 0.054 ; + END + END rw0_wd_in[455] + PIN rw0_wd_in[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END rw0_wd_in[456] + PIN rw0_wd_in[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.387 0.000 36.405 0.054 ; + END + END rw0_wd_in[457] + PIN rw0_wd_in[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.567 0.000 36.585 0.054 ; + END + END rw0_wd_in[458] + PIN rw0_wd_in[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.747 0.000 36.765 0.054 ; + END + END rw0_wd_in[459] + PIN rw0_wd_in[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.927 0.000 36.945 0.054 ; + END + END rw0_wd_in[460] + PIN rw0_wd_in[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.107 0.000 37.125 0.054 ; + END + END rw0_wd_in[461] + PIN rw0_wd_in[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.287 0.000 37.305 0.054 ; + END + END rw0_wd_in[462] + PIN rw0_wd_in[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.467 0.000 37.485 0.054 ; + END + END rw0_wd_in[463] + PIN rw0_wd_in[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END rw0_wd_in[464] + PIN rw0_wd_in[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.827 0.000 37.845 0.054 ; + END + END rw0_wd_in[465] + PIN rw0_wd_in[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.007 0.000 38.025 0.054 ; + END + END rw0_wd_in[466] + PIN rw0_wd_in[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.187 0.000 38.205 0.054 ; + END + END rw0_wd_in[467] + PIN rw0_wd_in[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.367 0.000 38.385 0.054 ; + END + END rw0_wd_in[468] + PIN rw0_wd_in[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.547 0.000 38.565 0.054 ; + END + END rw0_wd_in[469] + PIN rw0_wd_in[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.727 0.000 38.745 0.054 ; + END + END rw0_wd_in[470] + PIN rw0_wd_in[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.907 0.000 38.925 0.054 ; + END + END rw0_wd_in[471] + PIN rw0_wd_in[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END rw0_wd_in[472] + PIN rw0_wd_in[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.267 0.000 39.285 0.054 ; + END + END rw0_wd_in[473] + PIN rw0_wd_in[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.447 0.000 39.465 0.054 ; + END + END rw0_wd_in[474] + PIN rw0_wd_in[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.627 0.000 39.645 0.054 ; + END + END rw0_wd_in[475] + PIN rw0_wd_in[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.807 0.000 39.825 0.054 ; + END + END rw0_wd_in[476] + PIN rw0_wd_in[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.987 0.000 40.005 0.054 ; + END + END rw0_wd_in[477] + PIN rw0_wd_in[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.167 0.000 40.185 0.054 ; + END + END rw0_wd_in[478] + PIN rw0_wd_in[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.347 0.000 40.365 0.054 ; + END + END rw0_wd_in[479] + PIN rw0_wd_in[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END rw0_wd_in[480] + PIN rw0_wd_in[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.707 0.000 40.725 0.054 ; + END + END rw0_wd_in[481] + PIN rw0_wd_in[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.887 0.000 40.905 0.054 ; + END + END rw0_wd_in[482] + PIN rw0_wd_in[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.067 0.000 41.085 0.054 ; + END + END rw0_wd_in[483] + PIN rw0_wd_in[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.247 0.000 41.265 0.054 ; + END + END rw0_wd_in[484] + PIN rw0_wd_in[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.427 0.000 41.445 0.054 ; + END + END rw0_wd_in[485] + PIN rw0_wd_in[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.607 0.000 41.625 0.054 ; + END + END rw0_wd_in[486] + PIN rw0_wd_in[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.787 0.000 41.805 0.054 ; + END + END rw0_wd_in[487] + PIN rw0_wd_in[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END rw0_wd_in[488] + PIN rw0_wd_in[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.147 0.000 42.165 0.054 ; + END + END rw0_wd_in[489] + PIN rw0_wd_in[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.327 0.000 42.345 0.054 ; + END + END rw0_wd_in[490] + PIN rw0_wd_in[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.507 0.000 42.525 0.054 ; + END + END rw0_wd_in[491] + PIN rw0_wd_in[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.687 0.000 42.705 0.054 ; + END + END rw0_wd_in[492] + PIN rw0_wd_in[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.867 0.000 42.885 0.054 ; + END + END rw0_wd_in[493] + PIN rw0_wd_in[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.047 0.000 43.065 0.054 ; + END + END rw0_wd_in[494] + PIN rw0_wd_in[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.227 0.000 43.245 0.054 ; + END + END rw0_wd_in[495] + PIN rw0_wd_in[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END rw0_wd_in[496] + PIN rw0_wd_in[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.587 0.000 43.605 0.054 ; + END + END rw0_wd_in[497] + PIN rw0_wd_in[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.767 0.000 43.785 0.054 ; + END + END rw0_wd_in[498] + PIN rw0_wd_in[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.947 0.000 43.965 0.054 ; + END + END rw0_wd_in[499] + PIN rw0_wd_in[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.127 0.000 44.145 0.054 ; + END + END rw0_wd_in[500] + PIN rw0_wd_in[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.307 0.000 44.325 0.054 ; + END + END rw0_wd_in[501] + PIN rw0_wd_in[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.487 0.000 44.505 0.054 ; + END + END rw0_wd_in[502] + PIN rw0_wd_in[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.667 0.000 44.685 0.054 ; + END + END rw0_wd_in[503] + PIN rw0_wd_in[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END rw0_wd_in[504] + PIN rw0_wd_in[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.027 0.000 45.045 0.054 ; + END + END rw0_wd_in[505] + PIN rw0_wd_in[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.207 0.000 45.225 0.054 ; + END + END rw0_wd_in[506] + PIN rw0_wd_in[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.387 0.000 45.405 0.054 ; + END + END rw0_wd_in[507] + PIN rw0_wd_in[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.567 0.000 45.585 0.054 ; + END + END rw0_wd_in[508] + PIN rw0_wd_in[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.747 0.000 45.765 0.054 ; + END + END rw0_wd_in[509] + PIN rw0_wd_in[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.927 0.000 45.945 0.054 ; + END + END rw0_wd_in[510] + PIN rw0_wd_in[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.107 0.000 46.125 0.054 ; + END + END rw0_wd_in[511] + PIN rw0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END rw0_rd_out[0] + PIN rw0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.467 0.000 46.485 0.054 ; + END + END rw0_rd_out[1] + PIN rw0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 0.000 46.665 0.054 ; + END + END rw0_rd_out[2] + PIN rw0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.827 0.000 46.845 0.054 ; + END + END rw0_rd_out[3] + PIN rw0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.007 0.000 47.025 0.054 ; + END + END rw0_rd_out[4] + PIN rw0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 0.000 47.205 0.054 ; + END + END rw0_rd_out[5] + PIN rw0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.367 0.000 47.385 0.054 ; + END + END rw0_rd_out[6] + PIN rw0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.547 0.000 47.565 0.054 ; + END + END rw0_rd_out[7] + PIN rw0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END rw0_rd_out[8] + PIN rw0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.907 0.000 47.925 0.054 ; + END + END rw0_rd_out[9] + PIN rw0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.087 0.000 48.105 0.054 ; + END + END rw0_rd_out[10] + PIN rw0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 0.000 48.285 0.054 ; + END + END rw0_rd_out[11] + PIN rw0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.447 0.000 48.465 0.054 ; + END + END rw0_rd_out[12] + PIN rw0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.627 0.000 48.645 0.054 ; + END + END rw0_rd_out[13] + PIN rw0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 0.000 48.825 0.054 ; + END + END rw0_rd_out[14] + PIN rw0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.987 0.000 49.005 0.054 ; + END + END rw0_rd_out[15] + PIN rw0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END rw0_rd_out[16] + PIN rw0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 0.000 49.365 0.054 ; + END + END rw0_rd_out[17] + PIN rw0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.527 0.000 49.545 0.054 ; + END + END rw0_rd_out[18] + PIN rw0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.707 0.000 49.725 0.054 ; + END + END rw0_rd_out[19] + PIN rw0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 0.000 49.905 0.054 ; + END + END rw0_rd_out[20] + PIN rw0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.067 0.000 50.085 0.054 ; + END + END rw0_rd_out[21] + PIN rw0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.247 0.000 50.265 0.054 ; + END + END rw0_rd_out[22] + PIN rw0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 0.000 50.445 0.054 ; + END + END rw0_rd_out[23] + PIN rw0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END rw0_rd_out[24] + PIN rw0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.787 0.000 50.805 0.054 ; + END + END rw0_rd_out[25] + PIN rw0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 0.000 50.985 0.054 ; + END + END rw0_rd_out[26] + PIN rw0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.147 0.000 51.165 0.054 ; + END + END rw0_rd_out[27] + PIN rw0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.327 0.000 51.345 0.054 ; + END + END rw0_rd_out[28] + PIN rw0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 0.000 51.525 0.054 ; + END + END rw0_rd_out[29] + PIN rw0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.687 0.000 51.705 0.054 ; + END + END rw0_rd_out[30] + PIN rw0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.867 0.000 51.885 0.054 ; + END + END rw0_rd_out[31] + PIN rw0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END rw0_rd_out[32] + PIN rw0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.227 0.000 52.245 0.054 ; + END + END rw0_rd_out[33] + PIN rw0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.407 0.000 52.425 0.054 ; + END + END rw0_rd_out[34] + PIN rw0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 0.000 52.605 0.054 ; + END + END rw0_rd_out[35] + PIN rw0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.767 0.000 52.785 0.054 ; + END + END rw0_rd_out[36] + PIN rw0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.947 0.000 52.965 0.054 ; + END + END rw0_rd_out[37] + PIN rw0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 0.000 53.145 0.054 ; + END + END rw0_rd_out[38] + PIN rw0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.307 0.000 53.325 0.054 ; + END + END rw0_rd_out[39] + PIN rw0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END rw0_rd_out[40] + PIN rw0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 0.000 53.685 0.054 ; + END + END rw0_rd_out[41] + PIN rw0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.847 0.000 53.865 0.054 ; + END + END rw0_rd_out[42] + PIN rw0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.027 0.000 54.045 0.054 ; + END + END rw0_rd_out[43] + PIN rw0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 0.000 54.225 0.054 ; + END + END rw0_rd_out[44] + PIN rw0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.387 0.000 54.405 0.054 ; + END + END rw0_rd_out[45] + PIN rw0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.567 0.000 54.585 0.054 ; + END + END rw0_rd_out[46] + PIN rw0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 0.000 54.765 0.054 ; + END + END rw0_rd_out[47] + PIN rw0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END rw0_rd_out[48] + PIN rw0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.107 0.000 55.125 0.054 ; + END + END rw0_rd_out[49] + PIN rw0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 0.000 55.305 0.054 ; + END + END rw0_rd_out[50] + PIN rw0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.467 0.000 55.485 0.054 ; + END + END rw0_rd_out[51] + PIN rw0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.647 0.000 55.665 0.054 ; + END + END rw0_rd_out[52] + PIN rw0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 0.000 55.845 0.054 ; + END + END rw0_rd_out[53] + PIN rw0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.007 0.000 56.025 0.054 ; + END + END rw0_rd_out[54] + PIN rw0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.187 0.000 56.205 0.054 ; + END + END rw0_rd_out[55] + PIN rw0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END rw0_rd_out[56] + PIN rw0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.547 0.000 56.565 0.054 ; + END + END rw0_rd_out[57] + PIN rw0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.727 0.000 56.745 0.054 ; + END + END rw0_rd_out[58] + PIN rw0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 0.000 56.925 0.054 ; + END + END rw0_rd_out[59] + PIN rw0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.087 0.000 57.105 0.054 ; + END + END rw0_rd_out[60] + PIN rw0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.267 0.000 57.285 0.054 ; + END + END rw0_rd_out[61] + PIN rw0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 0.000 57.465 0.054 ; + END + END rw0_rd_out[62] + PIN rw0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.627 0.000 57.645 0.054 ; + END + END rw0_rd_out[63] + PIN rw0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END rw0_rd_out[64] + PIN rw0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 0.000 58.005 0.054 ; + END + END rw0_rd_out[65] + PIN rw0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.167 0.000 58.185 0.054 ; + END + END rw0_rd_out[66] + PIN rw0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.347 0.000 58.365 0.054 ; + END + END rw0_rd_out[67] + PIN rw0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 0.000 58.545 0.054 ; + END + END rw0_rd_out[68] + PIN rw0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.707 0.000 58.725 0.054 ; + END + END rw0_rd_out[69] + PIN rw0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.887 0.000 58.905 0.054 ; + END + END rw0_rd_out[70] + PIN rw0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 0.000 59.085 0.054 ; + END + END rw0_rd_out[71] + PIN rw0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END rw0_rd_out[72] + PIN rw0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.427 0.000 59.445 0.054 ; + END + END rw0_rd_out[73] + PIN rw0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 0.000 59.625 0.054 ; + END + END rw0_rd_out[74] + PIN rw0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.787 0.000 59.805 0.054 ; + END + END rw0_rd_out[75] + PIN rw0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.967 0.000 59.985 0.054 ; + END + END rw0_rd_out[76] + PIN rw0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 0.000 60.165 0.054 ; + END + END rw0_rd_out[77] + PIN rw0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.327 0.000 60.345 0.054 ; + END + END rw0_rd_out[78] + PIN rw0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.507 0.000 60.525 0.054 ; + END + END rw0_rd_out[79] + PIN rw0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END rw0_rd_out[80] + PIN rw0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.867 0.000 60.885 0.054 ; + END + END rw0_rd_out[81] + PIN rw0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.047 0.000 61.065 0.054 ; + END + END rw0_rd_out[82] + PIN rw0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 0.000 61.245 0.054 ; + END + END rw0_rd_out[83] + PIN rw0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.407 0.000 61.425 0.054 ; + END + END rw0_rd_out[84] + PIN rw0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.587 0.000 61.605 0.054 ; + END + END rw0_rd_out[85] + PIN rw0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 0.000 61.785 0.054 ; + END + END rw0_rd_out[86] + PIN rw0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.947 0.000 61.965 0.054 ; + END + END rw0_rd_out[87] + PIN rw0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END rw0_rd_out[88] + PIN rw0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 0.000 62.325 0.054 ; + END + END rw0_rd_out[89] + PIN rw0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.487 0.000 62.505 0.054 ; + END + END rw0_rd_out[90] + PIN rw0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.667 0.000 62.685 0.054 ; + END + END rw0_rd_out[91] + PIN rw0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 0.000 62.865 0.054 ; + END + END rw0_rd_out[92] + PIN rw0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.027 0.000 63.045 0.054 ; + END + END rw0_rd_out[93] + PIN rw0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.207 0.000 63.225 0.054 ; + END + END rw0_rd_out[94] + PIN rw0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 0.000 63.405 0.054 ; + END + END rw0_rd_out[95] + PIN rw0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END rw0_rd_out[96] + PIN rw0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.747 0.000 63.765 0.054 ; + END + END rw0_rd_out[97] + PIN rw0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.927 0.000 63.945 0.054 ; + END + END rw0_rd_out[98] + PIN rw0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.107 0.000 64.125 0.054 ; + END + END rw0_rd_out[99] + PIN rw0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.287 0.000 64.305 0.054 ; + END + END rw0_rd_out[100] + PIN rw0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.467 0.000 64.485 0.054 ; + END + END rw0_rd_out[101] + PIN rw0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.647 0.000 64.665 0.054 ; + END + END rw0_rd_out[102] + PIN rw0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.827 0.000 64.845 0.054 ; + END + END rw0_rd_out[103] + PIN rw0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END rw0_rd_out[104] + PIN rw0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.187 0.000 65.205 0.054 ; + END + END rw0_rd_out[105] + PIN rw0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.367 0.000 65.385 0.054 ; + END + END rw0_rd_out[106] + PIN rw0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.547 0.000 65.565 0.054 ; + END + END rw0_rd_out[107] + PIN rw0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.727 0.000 65.745 0.054 ; + END + END rw0_rd_out[108] + PIN rw0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.907 0.000 65.925 0.054 ; + END + END rw0_rd_out[109] + PIN rw0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.087 0.000 66.105 0.054 ; + END + END rw0_rd_out[110] + PIN rw0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.267 0.000 66.285 0.054 ; + END + END rw0_rd_out[111] + PIN rw0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END rw0_rd_out[112] + PIN rw0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.627 0.000 66.645 0.054 ; + END + END rw0_rd_out[113] + PIN rw0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.807 0.000 66.825 0.054 ; + END + END rw0_rd_out[114] + PIN rw0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.987 0.000 67.005 0.054 ; + END + END rw0_rd_out[115] + PIN rw0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.167 0.000 67.185 0.054 ; + END + END rw0_rd_out[116] + PIN rw0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.347 0.000 67.365 0.054 ; + END + END rw0_rd_out[117] + PIN rw0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.527 0.000 67.545 0.054 ; + END + END rw0_rd_out[118] + PIN rw0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.707 0.000 67.725 0.054 ; + END + END rw0_rd_out[119] + PIN rw0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END rw0_rd_out[120] + PIN rw0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.067 0.000 68.085 0.054 ; + END + END rw0_rd_out[121] + PIN rw0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.247 0.000 68.265 0.054 ; + END + END rw0_rd_out[122] + PIN rw0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.427 0.000 68.445 0.054 ; + END + END rw0_rd_out[123] + PIN rw0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.607 0.000 68.625 0.054 ; + END + END rw0_rd_out[124] + PIN rw0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.787 0.000 68.805 0.054 ; + END + END rw0_rd_out[125] + PIN rw0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.967 0.000 68.985 0.054 ; + END + END rw0_rd_out[126] + PIN rw0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.147 0.000 69.165 0.054 ; + END + END rw0_rd_out[127] + PIN rw0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END rw0_rd_out[128] + PIN rw0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.507 0.000 69.525 0.054 ; + END + END rw0_rd_out[129] + PIN rw0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.687 0.000 69.705 0.054 ; + END + END rw0_rd_out[130] + PIN rw0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.867 0.000 69.885 0.054 ; + END + END rw0_rd_out[131] + PIN rw0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.047 0.000 70.065 0.054 ; + END + END rw0_rd_out[132] + PIN rw0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.227 0.000 70.245 0.054 ; + END + END rw0_rd_out[133] + PIN rw0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.407 0.000 70.425 0.054 ; + END + END rw0_rd_out[134] + PIN rw0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.587 0.000 70.605 0.054 ; + END + END rw0_rd_out[135] + PIN rw0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END rw0_rd_out[136] + PIN rw0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.947 0.000 70.965 0.054 ; + END + END rw0_rd_out[137] + PIN rw0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.127 0.000 71.145 0.054 ; + END + END rw0_rd_out[138] + PIN rw0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.307 0.000 71.325 0.054 ; + END + END rw0_rd_out[139] + PIN rw0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.487 0.000 71.505 0.054 ; + END + END rw0_rd_out[140] + PIN rw0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.667 0.000 71.685 0.054 ; + END + END rw0_rd_out[141] + PIN rw0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.847 0.000 71.865 0.054 ; + END + END rw0_rd_out[142] + PIN rw0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.027 0.000 72.045 0.054 ; + END + END rw0_rd_out[143] + PIN rw0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END rw0_rd_out[144] + PIN rw0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.387 0.000 72.405 0.054 ; + END + END rw0_rd_out[145] + PIN rw0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.567 0.000 72.585 0.054 ; + END + END rw0_rd_out[146] + PIN rw0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.747 0.000 72.765 0.054 ; + END + END rw0_rd_out[147] + PIN rw0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.927 0.000 72.945 0.054 ; + END + END rw0_rd_out[148] + PIN rw0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.107 0.000 73.125 0.054 ; + END + END rw0_rd_out[149] + PIN rw0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.287 0.000 73.305 0.054 ; + END + END rw0_rd_out[150] + PIN rw0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.467 0.000 73.485 0.054 ; + END + END rw0_rd_out[151] + PIN rw0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END rw0_rd_out[152] + PIN rw0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.827 0.000 73.845 0.054 ; + END + END rw0_rd_out[153] + PIN rw0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.007 0.000 74.025 0.054 ; + END + END rw0_rd_out[154] + PIN rw0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.187 0.000 74.205 0.054 ; + END + END rw0_rd_out[155] + PIN rw0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.367 0.000 74.385 0.054 ; + END + END rw0_rd_out[156] + PIN rw0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.547 0.000 74.565 0.054 ; + END + END rw0_rd_out[157] + PIN rw0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.727 0.000 74.745 0.054 ; + END + END rw0_rd_out[158] + PIN rw0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.907 0.000 74.925 0.054 ; + END + END rw0_rd_out[159] + PIN rw0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END rw0_rd_out[160] + PIN rw0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.267 0.000 75.285 0.054 ; + END + END rw0_rd_out[161] + PIN rw0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.447 0.000 75.465 0.054 ; + END + END rw0_rd_out[162] + PIN rw0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.627 0.000 75.645 0.054 ; + END + END rw0_rd_out[163] + PIN rw0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.807 0.000 75.825 0.054 ; + END + END rw0_rd_out[164] + PIN rw0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.987 0.000 76.005 0.054 ; + END + END rw0_rd_out[165] + PIN rw0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.167 0.000 76.185 0.054 ; + END + END rw0_rd_out[166] + PIN rw0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.347 0.000 76.365 0.054 ; + END + END rw0_rd_out[167] + PIN rw0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END rw0_rd_out[168] + PIN rw0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.707 0.000 76.725 0.054 ; + END + END rw0_rd_out[169] + PIN rw0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.887 0.000 76.905 0.054 ; + END + END rw0_rd_out[170] + PIN rw0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.067 0.000 77.085 0.054 ; + END + END rw0_rd_out[171] + PIN rw0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.247 0.000 77.265 0.054 ; + END + END rw0_rd_out[172] + PIN rw0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.427 0.000 77.445 0.054 ; + END + END rw0_rd_out[173] + PIN rw0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.607 0.000 77.625 0.054 ; + END + END rw0_rd_out[174] + PIN rw0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.787 0.000 77.805 0.054 ; + END + END rw0_rd_out[175] + PIN rw0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END rw0_rd_out[176] + PIN rw0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.147 0.000 78.165 0.054 ; + END + END rw0_rd_out[177] + PIN rw0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.327 0.000 78.345 0.054 ; + END + END rw0_rd_out[178] + PIN rw0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.507 0.000 78.525 0.054 ; + END + END rw0_rd_out[179] + PIN rw0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.687 0.000 78.705 0.054 ; + END + END rw0_rd_out[180] + PIN rw0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.867 0.000 78.885 0.054 ; + END + END rw0_rd_out[181] + PIN rw0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.047 0.000 79.065 0.054 ; + END + END rw0_rd_out[182] + PIN rw0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.227 0.000 79.245 0.054 ; + END + END rw0_rd_out[183] + PIN rw0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END rw0_rd_out[184] + PIN rw0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.587 0.000 79.605 0.054 ; + END + END rw0_rd_out[185] + PIN rw0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.767 0.000 79.785 0.054 ; + END + END rw0_rd_out[186] + PIN rw0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.947 0.000 79.965 0.054 ; + END + END rw0_rd_out[187] + PIN rw0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.127 0.000 80.145 0.054 ; + END + END rw0_rd_out[188] + PIN rw0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.307 0.000 80.325 0.054 ; + END + END rw0_rd_out[189] + PIN rw0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.487 0.000 80.505 0.054 ; + END + END rw0_rd_out[190] + PIN rw0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.667 0.000 80.685 0.054 ; + END + END rw0_rd_out[191] + PIN rw0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END rw0_rd_out[192] + PIN rw0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.027 0.000 81.045 0.054 ; + END + END rw0_rd_out[193] + PIN rw0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.207 0.000 81.225 0.054 ; + END + END rw0_rd_out[194] + PIN rw0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.387 0.000 81.405 0.054 ; + END + END rw0_rd_out[195] + PIN rw0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.567 0.000 81.585 0.054 ; + END + END rw0_rd_out[196] + PIN rw0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.747 0.000 81.765 0.054 ; + END + END rw0_rd_out[197] + PIN rw0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.927 0.000 81.945 0.054 ; + END + END rw0_rd_out[198] + PIN rw0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.107 0.000 82.125 0.054 ; + END + END rw0_rd_out[199] + PIN rw0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END rw0_rd_out[200] + PIN rw0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.467 0.000 82.485 0.054 ; + END + END rw0_rd_out[201] + PIN rw0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.647 0.000 82.665 0.054 ; + END + END rw0_rd_out[202] + PIN rw0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.827 0.000 82.845 0.054 ; + END + END rw0_rd_out[203] + PIN rw0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.007 0.000 83.025 0.054 ; + END + END rw0_rd_out[204] + PIN rw0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.187 0.000 83.205 0.054 ; + END + END rw0_rd_out[205] + PIN rw0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.367 0.000 83.385 0.054 ; + END + END rw0_rd_out[206] + PIN rw0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.547 0.000 83.565 0.054 ; + END + END rw0_rd_out[207] + PIN rw0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END rw0_rd_out[208] + PIN rw0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.907 0.000 83.925 0.054 ; + END + END rw0_rd_out[209] + PIN rw0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.087 0.000 84.105 0.054 ; + END + END rw0_rd_out[210] + PIN rw0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.267 0.000 84.285 0.054 ; + END + END rw0_rd_out[211] + PIN rw0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.447 0.000 84.465 0.054 ; + END + END rw0_rd_out[212] + PIN rw0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.627 0.000 84.645 0.054 ; + END + END rw0_rd_out[213] + PIN rw0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.807 0.000 84.825 0.054 ; + END + END rw0_rd_out[214] + PIN rw0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.987 0.000 85.005 0.054 ; + END + END rw0_rd_out[215] + PIN rw0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END rw0_rd_out[216] + PIN rw0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.347 0.000 85.365 0.054 ; + END + END rw0_rd_out[217] + PIN rw0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.527 0.000 85.545 0.054 ; + END + END rw0_rd_out[218] + PIN rw0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.707 0.000 85.725 0.054 ; + END + END rw0_rd_out[219] + PIN rw0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.887 0.000 85.905 0.054 ; + END + END rw0_rd_out[220] + PIN rw0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.067 0.000 86.085 0.054 ; + END + END rw0_rd_out[221] + PIN rw0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.247 0.000 86.265 0.054 ; + END + END rw0_rd_out[222] + PIN rw0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.427 0.000 86.445 0.054 ; + END + END rw0_rd_out[223] + PIN rw0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END rw0_rd_out[224] + PIN rw0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.787 0.000 86.805 0.054 ; + END + END rw0_rd_out[225] + PIN rw0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.967 0.000 86.985 0.054 ; + END + END rw0_rd_out[226] + PIN rw0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.147 0.000 87.165 0.054 ; + END + END rw0_rd_out[227] + PIN rw0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.327 0.000 87.345 0.054 ; + END + END rw0_rd_out[228] + PIN rw0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.507 0.000 87.525 0.054 ; + END + END rw0_rd_out[229] + PIN rw0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.687 0.000 87.705 0.054 ; + END + END rw0_rd_out[230] + PIN rw0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.867 0.000 87.885 0.054 ; + END + END rw0_rd_out[231] + PIN rw0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END rw0_rd_out[232] + PIN rw0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.227 0.000 88.245 0.054 ; + END + END rw0_rd_out[233] + PIN rw0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.407 0.000 88.425 0.054 ; + END + END rw0_rd_out[234] + PIN rw0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.587 0.000 88.605 0.054 ; + END + END rw0_rd_out[235] + PIN rw0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.767 0.000 88.785 0.054 ; + END + END rw0_rd_out[236] + PIN rw0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.947 0.000 88.965 0.054 ; + END + END rw0_rd_out[237] + PIN rw0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.127 0.000 89.145 0.054 ; + END + END rw0_rd_out[238] + PIN rw0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.307 0.000 89.325 0.054 ; + END + END rw0_rd_out[239] + PIN rw0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END rw0_rd_out[240] + PIN rw0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.667 0.000 89.685 0.054 ; + END + END rw0_rd_out[241] + PIN rw0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.847 0.000 89.865 0.054 ; + END + END rw0_rd_out[242] + PIN rw0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.027 0.000 90.045 0.054 ; + END + END rw0_rd_out[243] + PIN rw0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.207 0.000 90.225 0.054 ; + END + END rw0_rd_out[244] + PIN rw0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.387 0.000 90.405 0.054 ; + END + END rw0_rd_out[245] + PIN rw0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.567 0.000 90.585 0.054 ; + END + END rw0_rd_out[246] + PIN rw0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.747 0.000 90.765 0.054 ; + END + END rw0_rd_out[247] + PIN rw0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END rw0_rd_out[248] + PIN rw0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.107 0.000 91.125 0.054 ; + END + END rw0_rd_out[249] + PIN rw0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.287 0.000 91.305 0.054 ; + END + END rw0_rd_out[250] + PIN rw0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.467 0.000 91.485 0.054 ; + END + END rw0_rd_out[251] + PIN rw0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.647 0.000 91.665 0.054 ; + END + END rw0_rd_out[252] + PIN rw0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.827 0.000 91.845 0.054 ; + END + END rw0_rd_out[253] + PIN rw0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.007 0.000 92.025 0.054 ; + END + END rw0_rd_out[254] + PIN rw0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.187 0.000 92.205 0.054 ; + END + END rw0_rd_out[255] + PIN rw0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 36.062 46.305 36.116 ; + END + END rw0_rd_out[256] + PIN rw0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.467 36.062 46.485 36.116 ; + END + END rw0_rd_out[257] + PIN rw0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.647 36.062 46.665 36.116 ; + END + END rw0_rd_out[258] + PIN rw0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.827 36.062 46.845 36.116 ; + END + END rw0_rd_out[259] + PIN rw0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.007 36.062 47.025 36.116 ; + END + END rw0_rd_out[260] + PIN rw0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.187 36.062 47.205 36.116 ; + END + END rw0_rd_out[261] + PIN rw0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.367 36.062 47.385 36.116 ; + END + END rw0_rd_out[262] + PIN rw0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.547 36.062 47.565 36.116 ; + END + END rw0_rd_out[263] + PIN rw0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 36.062 47.745 36.116 ; + END + END rw0_rd_out[264] + PIN rw0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.907 36.062 47.925 36.116 ; + END + END rw0_rd_out[265] + PIN rw0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.087 36.062 48.105 36.116 ; + END + END rw0_rd_out[266] + PIN rw0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.267 36.062 48.285 36.116 ; + END + END rw0_rd_out[267] + PIN rw0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.447 36.062 48.465 36.116 ; + END + END rw0_rd_out[268] + PIN rw0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.627 36.062 48.645 36.116 ; + END + END rw0_rd_out[269] + PIN rw0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.807 36.062 48.825 36.116 ; + END + END rw0_rd_out[270] + PIN rw0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.987 36.062 49.005 36.116 ; + END + END rw0_rd_out[271] + PIN rw0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 36.062 49.185 36.116 ; + END + END rw0_rd_out[272] + PIN rw0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.347 36.062 49.365 36.116 ; + END + END rw0_rd_out[273] + PIN rw0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.527 36.062 49.545 36.116 ; + END + END rw0_rd_out[274] + PIN rw0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.707 36.062 49.725 36.116 ; + END + END rw0_rd_out[275] + PIN rw0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.887 36.062 49.905 36.116 ; + END + END rw0_rd_out[276] + PIN rw0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.067 36.062 50.085 36.116 ; + END + END rw0_rd_out[277] + PIN rw0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.247 36.062 50.265 36.116 ; + END + END rw0_rd_out[278] + PIN rw0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.427 36.062 50.445 36.116 ; + END + END rw0_rd_out[279] + PIN rw0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 36.062 50.625 36.116 ; + END + END rw0_rd_out[280] + PIN rw0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.787 36.062 50.805 36.116 ; + END + END rw0_rd_out[281] + PIN rw0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.967 36.062 50.985 36.116 ; + END + END rw0_rd_out[282] + PIN rw0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.147 36.062 51.165 36.116 ; + END + END rw0_rd_out[283] + PIN rw0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.327 36.062 51.345 36.116 ; + END + END rw0_rd_out[284] + PIN rw0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.507 36.062 51.525 36.116 ; + END + END rw0_rd_out[285] + PIN rw0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.687 36.062 51.705 36.116 ; + END + END rw0_rd_out[286] + PIN rw0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.867 36.062 51.885 36.116 ; + END + END rw0_rd_out[287] + PIN rw0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 36.062 52.065 36.116 ; + END + END rw0_rd_out[288] + PIN rw0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.227 36.062 52.245 36.116 ; + END + END rw0_rd_out[289] + PIN rw0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.407 36.062 52.425 36.116 ; + END + END rw0_rd_out[290] + PIN rw0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.587 36.062 52.605 36.116 ; + END + END rw0_rd_out[291] + PIN rw0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.767 36.062 52.785 36.116 ; + END + END rw0_rd_out[292] + PIN rw0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.947 36.062 52.965 36.116 ; + END + END rw0_rd_out[293] + PIN rw0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.127 36.062 53.145 36.116 ; + END + END rw0_rd_out[294] + PIN rw0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.307 36.062 53.325 36.116 ; + END + END rw0_rd_out[295] + PIN rw0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 36.062 53.505 36.116 ; + END + END rw0_rd_out[296] + PIN rw0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.667 36.062 53.685 36.116 ; + END + END rw0_rd_out[297] + PIN rw0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.847 36.062 53.865 36.116 ; + END + END rw0_rd_out[298] + PIN rw0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.027 36.062 54.045 36.116 ; + END + END rw0_rd_out[299] + PIN rw0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.207 36.062 54.225 36.116 ; + END + END rw0_rd_out[300] + PIN rw0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.387 36.062 54.405 36.116 ; + END + END rw0_rd_out[301] + PIN rw0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.567 36.062 54.585 36.116 ; + END + END rw0_rd_out[302] + PIN rw0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.747 36.062 54.765 36.116 ; + END + END rw0_rd_out[303] + PIN rw0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 36.062 54.945 36.116 ; + END + END rw0_rd_out[304] + PIN rw0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.107 36.062 55.125 36.116 ; + END + END rw0_rd_out[305] + PIN rw0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.287 36.062 55.305 36.116 ; + END + END rw0_rd_out[306] + PIN rw0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.467 36.062 55.485 36.116 ; + END + END rw0_rd_out[307] + PIN rw0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.647 36.062 55.665 36.116 ; + END + END rw0_rd_out[308] + PIN rw0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.827 36.062 55.845 36.116 ; + END + END rw0_rd_out[309] + PIN rw0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.007 36.062 56.025 36.116 ; + END + END rw0_rd_out[310] + PIN rw0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.187 36.062 56.205 36.116 ; + END + END rw0_rd_out[311] + PIN rw0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 36.062 56.385 36.116 ; + END + END rw0_rd_out[312] + PIN rw0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.547 36.062 56.565 36.116 ; + END + END rw0_rd_out[313] + PIN rw0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.727 36.062 56.745 36.116 ; + END + END rw0_rd_out[314] + PIN rw0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.907 36.062 56.925 36.116 ; + END + END rw0_rd_out[315] + PIN rw0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.087 36.062 57.105 36.116 ; + END + END rw0_rd_out[316] + PIN rw0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.267 36.062 57.285 36.116 ; + END + END rw0_rd_out[317] + PIN rw0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.447 36.062 57.465 36.116 ; + END + END rw0_rd_out[318] + PIN rw0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.627 36.062 57.645 36.116 ; + END + END rw0_rd_out[319] + PIN rw0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 36.062 57.825 36.116 ; + END + END rw0_rd_out[320] + PIN rw0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.987 36.062 58.005 36.116 ; + END + END rw0_rd_out[321] + PIN rw0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.167 36.062 58.185 36.116 ; + END + END rw0_rd_out[322] + PIN rw0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.347 36.062 58.365 36.116 ; + END + END rw0_rd_out[323] + PIN rw0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.527 36.062 58.545 36.116 ; + END + END rw0_rd_out[324] + PIN rw0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.707 36.062 58.725 36.116 ; + END + END rw0_rd_out[325] + PIN rw0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.887 36.062 58.905 36.116 ; + END + END rw0_rd_out[326] + PIN rw0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.067 36.062 59.085 36.116 ; + END + END rw0_rd_out[327] + PIN rw0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 36.062 59.265 36.116 ; + END + END rw0_rd_out[328] + PIN rw0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.427 36.062 59.445 36.116 ; + END + END rw0_rd_out[329] + PIN rw0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.607 36.062 59.625 36.116 ; + END + END rw0_rd_out[330] + PIN rw0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.787 36.062 59.805 36.116 ; + END + END rw0_rd_out[331] + PIN rw0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.967 36.062 59.985 36.116 ; + END + END rw0_rd_out[332] + PIN rw0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.147 36.062 60.165 36.116 ; + END + END rw0_rd_out[333] + PIN rw0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.327 36.062 60.345 36.116 ; + END + END rw0_rd_out[334] + PIN rw0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.507 36.062 60.525 36.116 ; + END + END rw0_rd_out[335] + PIN rw0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 36.062 60.705 36.116 ; + END + END rw0_rd_out[336] + PIN rw0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.867 36.062 60.885 36.116 ; + END + END rw0_rd_out[337] + PIN rw0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.047 36.062 61.065 36.116 ; + END + END rw0_rd_out[338] + PIN rw0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.227 36.062 61.245 36.116 ; + END + END rw0_rd_out[339] + PIN rw0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.407 36.062 61.425 36.116 ; + END + END rw0_rd_out[340] + PIN rw0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.587 36.062 61.605 36.116 ; + END + END rw0_rd_out[341] + PIN rw0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.767 36.062 61.785 36.116 ; + END + END rw0_rd_out[342] + PIN rw0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.947 36.062 61.965 36.116 ; + END + END rw0_rd_out[343] + PIN rw0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 36.062 62.145 36.116 ; + END + END rw0_rd_out[344] + PIN rw0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.307 36.062 62.325 36.116 ; + END + END rw0_rd_out[345] + PIN rw0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.487 36.062 62.505 36.116 ; + END + END rw0_rd_out[346] + PIN rw0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.667 36.062 62.685 36.116 ; + END + END rw0_rd_out[347] + PIN rw0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.847 36.062 62.865 36.116 ; + END + END rw0_rd_out[348] + PIN rw0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.027 36.062 63.045 36.116 ; + END + END rw0_rd_out[349] + PIN rw0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.207 36.062 63.225 36.116 ; + END + END rw0_rd_out[350] + PIN rw0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.387 36.062 63.405 36.116 ; + END + END rw0_rd_out[351] + PIN rw0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 36.062 63.585 36.116 ; + END + END rw0_rd_out[352] + PIN rw0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.747 36.062 63.765 36.116 ; + END + END rw0_rd_out[353] + PIN rw0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.927 36.062 63.945 36.116 ; + END + END rw0_rd_out[354] + PIN rw0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.107 36.062 64.125 36.116 ; + END + END rw0_rd_out[355] + PIN rw0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.287 36.062 64.305 36.116 ; + END + END rw0_rd_out[356] + PIN rw0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.467 36.062 64.485 36.116 ; + END + END rw0_rd_out[357] + PIN rw0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.647 36.062 64.665 36.116 ; + END + END rw0_rd_out[358] + PIN rw0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.827 36.062 64.845 36.116 ; + END + END rw0_rd_out[359] + PIN rw0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 36.062 65.025 36.116 ; + END + END rw0_rd_out[360] + PIN rw0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.187 36.062 65.205 36.116 ; + END + END rw0_rd_out[361] + PIN rw0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.367 36.062 65.385 36.116 ; + END + END rw0_rd_out[362] + PIN rw0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.547 36.062 65.565 36.116 ; + END + END rw0_rd_out[363] + PIN rw0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.727 36.062 65.745 36.116 ; + END + END rw0_rd_out[364] + PIN rw0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.907 36.062 65.925 36.116 ; + END + END rw0_rd_out[365] + PIN rw0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.087 36.062 66.105 36.116 ; + END + END rw0_rd_out[366] + PIN rw0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.267 36.062 66.285 36.116 ; + END + END rw0_rd_out[367] + PIN rw0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 36.062 66.465 36.116 ; + END + END rw0_rd_out[368] + PIN rw0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.627 36.062 66.645 36.116 ; + END + END rw0_rd_out[369] + PIN rw0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.807 36.062 66.825 36.116 ; + END + END rw0_rd_out[370] + PIN rw0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.987 36.062 67.005 36.116 ; + END + END rw0_rd_out[371] + PIN rw0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.167 36.062 67.185 36.116 ; + END + END rw0_rd_out[372] + PIN rw0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.347 36.062 67.365 36.116 ; + END + END rw0_rd_out[373] + PIN rw0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.527 36.062 67.545 36.116 ; + END + END rw0_rd_out[374] + PIN rw0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.707 36.062 67.725 36.116 ; + END + END rw0_rd_out[375] + PIN rw0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 36.062 67.905 36.116 ; + END + END rw0_rd_out[376] + PIN rw0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.067 36.062 68.085 36.116 ; + END + END rw0_rd_out[377] + PIN rw0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.247 36.062 68.265 36.116 ; + END + END rw0_rd_out[378] + PIN rw0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.427 36.062 68.445 36.116 ; + END + END rw0_rd_out[379] + PIN rw0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.607 36.062 68.625 36.116 ; + END + END rw0_rd_out[380] + PIN rw0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.787 36.062 68.805 36.116 ; + END + END rw0_rd_out[381] + PIN rw0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.967 36.062 68.985 36.116 ; + END + END rw0_rd_out[382] + PIN rw0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.147 36.062 69.165 36.116 ; + END + END rw0_rd_out[383] + PIN rw0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 36.062 69.345 36.116 ; + END + END rw0_rd_out[384] + PIN rw0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.507 36.062 69.525 36.116 ; + END + END rw0_rd_out[385] + PIN rw0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.687 36.062 69.705 36.116 ; + END + END rw0_rd_out[386] + PIN rw0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.867 36.062 69.885 36.116 ; + END + END rw0_rd_out[387] + PIN rw0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.047 36.062 70.065 36.116 ; + END + END rw0_rd_out[388] + PIN rw0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.227 36.062 70.245 36.116 ; + END + END rw0_rd_out[389] + PIN rw0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.407 36.062 70.425 36.116 ; + END + END rw0_rd_out[390] + PIN rw0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.587 36.062 70.605 36.116 ; + END + END rw0_rd_out[391] + PIN rw0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 36.062 70.785 36.116 ; + END + END rw0_rd_out[392] + PIN rw0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.947 36.062 70.965 36.116 ; + END + END rw0_rd_out[393] + PIN rw0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.127 36.062 71.145 36.116 ; + END + END rw0_rd_out[394] + PIN rw0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.307 36.062 71.325 36.116 ; + END + END rw0_rd_out[395] + PIN rw0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.487 36.062 71.505 36.116 ; + END + END rw0_rd_out[396] + PIN rw0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.667 36.062 71.685 36.116 ; + END + END rw0_rd_out[397] + PIN rw0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.847 36.062 71.865 36.116 ; + END + END rw0_rd_out[398] + PIN rw0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.027 36.062 72.045 36.116 ; + END + END rw0_rd_out[399] + PIN rw0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 36.062 72.225 36.116 ; + END + END rw0_rd_out[400] + PIN rw0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.387 36.062 72.405 36.116 ; + END + END rw0_rd_out[401] + PIN rw0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.567 36.062 72.585 36.116 ; + END + END rw0_rd_out[402] + PIN rw0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.747 36.062 72.765 36.116 ; + END + END rw0_rd_out[403] + PIN rw0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.927 36.062 72.945 36.116 ; + END + END rw0_rd_out[404] + PIN rw0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.107 36.062 73.125 36.116 ; + END + END rw0_rd_out[405] + PIN rw0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.287 36.062 73.305 36.116 ; + END + END rw0_rd_out[406] + PIN rw0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.467 36.062 73.485 36.116 ; + END + END rw0_rd_out[407] + PIN rw0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 36.062 73.665 36.116 ; + END + END rw0_rd_out[408] + PIN rw0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.827 36.062 73.845 36.116 ; + END + END rw0_rd_out[409] + PIN rw0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.007 36.062 74.025 36.116 ; + END + END rw0_rd_out[410] + PIN rw0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.187 36.062 74.205 36.116 ; + END + END rw0_rd_out[411] + PIN rw0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.367 36.062 74.385 36.116 ; + END + END rw0_rd_out[412] + PIN rw0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.547 36.062 74.565 36.116 ; + END + END rw0_rd_out[413] + PIN rw0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.727 36.062 74.745 36.116 ; + END + END rw0_rd_out[414] + PIN rw0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.907 36.062 74.925 36.116 ; + END + END rw0_rd_out[415] + PIN rw0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 36.062 75.105 36.116 ; + END + END rw0_rd_out[416] + PIN rw0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.267 36.062 75.285 36.116 ; + END + END rw0_rd_out[417] + PIN rw0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.447 36.062 75.465 36.116 ; + END + END rw0_rd_out[418] + PIN rw0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.627 36.062 75.645 36.116 ; + END + END rw0_rd_out[419] + PIN rw0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.807 36.062 75.825 36.116 ; + END + END rw0_rd_out[420] + PIN rw0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.987 36.062 76.005 36.116 ; + END + END rw0_rd_out[421] + PIN rw0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.167 36.062 76.185 36.116 ; + END + END rw0_rd_out[422] + PIN rw0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.347 36.062 76.365 36.116 ; + END + END rw0_rd_out[423] + PIN rw0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 36.062 76.545 36.116 ; + END + END rw0_rd_out[424] + PIN rw0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.707 36.062 76.725 36.116 ; + END + END rw0_rd_out[425] + PIN rw0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.887 36.062 76.905 36.116 ; + END + END rw0_rd_out[426] + PIN rw0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.067 36.062 77.085 36.116 ; + END + END rw0_rd_out[427] + PIN rw0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.247 36.062 77.265 36.116 ; + END + END rw0_rd_out[428] + PIN rw0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.427 36.062 77.445 36.116 ; + END + END rw0_rd_out[429] + PIN rw0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.607 36.062 77.625 36.116 ; + END + END rw0_rd_out[430] + PIN rw0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.787 36.062 77.805 36.116 ; + END + END rw0_rd_out[431] + PIN rw0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 36.062 77.985 36.116 ; + END + END rw0_rd_out[432] + PIN rw0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.147 36.062 78.165 36.116 ; + END + END rw0_rd_out[433] + PIN rw0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.327 36.062 78.345 36.116 ; + END + END rw0_rd_out[434] + PIN rw0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.507 36.062 78.525 36.116 ; + END + END rw0_rd_out[435] + PIN rw0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.687 36.062 78.705 36.116 ; + END + END rw0_rd_out[436] + PIN rw0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.867 36.062 78.885 36.116 ; + END + END rw0_rd_out[437] + PIN rw0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.047 36.062 79.065 36.116 ; + END + END rw0_rd_out[438] + PIN rw0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.227 36.062 79.245 36.116 ; + END + END rw0_rd_out[439] + PIN rw0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 36.062 79.425 36.116 ; + END + END rw0_rd_out[440] + PIN rw0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.587 36.062 79.605 36.116 ; + END + END rw0_rd_out[441] + PIN rw0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.767 36.062 79.785 36.116 ; + END + END rw0_rd_out[442] + PIN rw0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.947 36.062 79.965 36.116 ; + END + END rw0_rd_out[443] + PIN rw0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.127 36.062 80.145 36.116 ; + END + END rw0_rd_out[444] + PIN rw0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.307 36.062 80.325 36.116 ; + END + END rw0_rd_out[445] + PIN rw0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.487 36.062 80.505 36.116 ; + END + END rw0_rd_out[446] + PIN rw0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.667 36.062 80.685 36.116 ; + END + END rw0_rd_out[447] + PIN rw0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 36.062 80.865 36.116 ; + END + END rw0_rd_out[448] + PIN rw0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.027 36.062 81.045 36.116 ; + END + END rw0_rd_out[449] + PIN rw0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.207 36.062 81.225 36.116 ; + END + END rw0_rd_out[450] + PIN rw0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.387 36.062 81.405 36.116 ; + END + END rw0_rd_out[451] + PIN rw0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.567 36.062 81.585 36.116 ; + END + END rw0_rd_out[452] + PIN rw0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.747 36.062 81.765 36.116 ; + END + END rw0_rd_out[453] + PIN rw0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.927 36.062 81.945 36.116 ; + END + END rw0_rd_out[454] + PIN rw0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.107 36.062 82.125 36.116 ; + END + END rw0_rd_out[455] + PIN rw0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 36.062 82.305 36.116 ; + END + END rw0_rd_out[456] + PIN rw0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.467 36.062 82.485 36.116 ; + END + END rw0_rd_out[457] + PIN rw0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.647 36.062 82.665 36.116 ; + END + END rw0_rd_out[458] + PIN rw0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.827 36.062 82.845 36.116 ; + END + END rw0_rd_out[459] + PIN rw0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.007 36.062 83.025 36.116 ; + END + END rw0_rd_out[460] + PIN rw0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.187 36.062 83.205 36.116 ; + END + END rw0_rd_out[461] + PIN rw0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.367 36.062 83.385 36.116 ; + END + END rw0_rd_out[462] + PIN rw0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.547 36.062 83.565 36.116 ; + END + END rw0_rd_out[463] + PIN rw0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 36.062 83.745 36.116 ; + END + END rw0_rd_out[464] + PIN rw0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.907 36.062 83.925 36.116 ; + END + END rw0_rd_out[465] + PIN rw0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.087 36.062 84.105 36.116 ; + END + END rw0_rd_out[466] + PIN rw0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.267 36.062 84.285 36.116 ; + END + END rw0_rd_out[467] + PIN rw0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.447 36.062 84.465 36.116 ; + END + END rw0_rd_out[468] + PIN rw0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.627 36.062 84.645 36.116 ; + END + END rw0_rd_out[469] + PIN rw0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.807 36.062 84.825 36.116 ; + END + END rw0_rd_out[470] + PIN rw0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.987 36.062 85.005 36.116 ; + END + END rw0_rd_out[471] + PIN rw0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 36.062 85.185 36.116 ; + END + END rw0_rd_out[472] + PIN rw0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.347 36.062 85.365 36.116 ; + END + END rw0_rd_out[473] + PIN rw0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.527 36.062 85.545 36.116 ; + END + END rw0_rd_out[474] + PIN rw0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.707 36.062 85.725 36.116 ; + END + END rw0_rd_out[475] + PIN rw0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.887 36.062 85.905 36.116 ; + END + END rw0_rd_out[476] + PIN rw0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.067 36.062 86.085 36.116 ; + END + END rw0_rd_out[477] + PIN rw0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.247 36.062 86.265 36.116 ; + END + END rw0_rd_out[478] + PIN rw0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.427 36.062 86.445 36.116 ; + END + END rw0_rd_out[479] + PIN rw0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 36.062 86.625 36.116 ; + END + END rw0_rd_out[480] + PIN rw0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.787 36.062 86.805 36.116 ; + END + END rw0_rd_out[481] + PIN rw0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.967 36.062 86.985 36.116 ; + END + END rw0_rd_out[482] + PIN rw0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.147 36.062 87.165 36.116 ; + END + END rw0_rd_out[483] + PIN rw0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.327 36.062 87.345 36.116 ; + END + END rw0_rd_out[484] + PIN rw0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.507 36.062 87.525 36.116 ; + END + END rw0_rd_out[485] + PIN rw0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.687 36.062 87.705 36.116 ; + END + END rw0_rd_out[486] + PIN rw0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.867 36.062 87.885 36.116 ; + END + END rw0_rd_out[487] + PIN rw0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 36.062 88.065 36.116 ; + END + END rw0_rd_out[488] + PIN rw0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.227 36.062 88.245 36.116 ; + END + END rw0_rd_out[489] + PIN rw0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.407 36.062 88.425 36.116 ; + END + END rw0_rd_out[490] + PIN rw0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.587 36.062 88.605 36.116 ; + END + END rw0_rd_out[491] + PIN rw0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.767 36.062 88.785 36.116 ; + END + END rw0_rd_out[492] + PIN rw0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.947 36.062 88.965 36.116 ; + END + END rw0_rd_out[493] + PIN rw0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.127 36.062 89.145 36.116 ; + END + END rw0_rd_out[494] + PIN rw0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.307 36.062 89.325 36.116 ; + END + END rw0_rd_out[495] + PIN rw0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 36.062 89.505 36.116 ; + END + END rw0_rd_out[496] + PIN rw0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.667 36.062 89.685 36.116 ; + END + END rw0_rd_out[497] + PIN rw0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.847 36.062 89.865 36.116 ; + END + END rw0_rd_out[498] + PIN rw0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.027 36.062 90.045 36.116 ; + END + END rw0_rd_out[499] + PIN rw0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.207 36.062 90.225 36.116 ; + END + END rw0_rd_out[500] + PIN rw0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.387 36.062 90.405 36.116 ; + END + END rw0_rd_out[501] + PIN rw0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.567 36.062 90.585 36.116 ; + END + END rw0_rd_out[502] + PIN rw0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.747 36.062 90.765 36.116 ; + END + END rw0_rd_out[503] + PIN rw0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 36.062 90.945 36.116 ; + END + END rw0_rd_out[504] + PIN rw0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.107 36.062 91.125 36.116 ; + END + END rw0_rd_out[505] + PIN rw0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.287 36.062 91.305 36.116 ; + END + END rw0_rd_out[506] + PIN rw0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.467 36.062 91.485 36.116 ; + END + END rw0_rd_out[507] + PIN rw0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.647 36.062 91.665 36.116 ; + END + END rw0_rd_out[508] + PIN rw0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.827 36.062 91.845 36.116 ; + END + END rw0_rd_out[509] + PIN rw0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.007 36.062 92.025 36.116 ; + END + END rw0_rd_out[510] + PIN rw0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.187 36.062 92.205 36.116 ; + END + END rw0_rd_out[511] + PIN rw0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.852 0.072 24.876 ; + END + END rw0_addr_in[0] + PIN rw0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.948 0.072 24.972 ; + END + END rw0_addr_in[1] + PIN rw0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END rw0_addr_in[2] + PIN rw0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.852 104.012 24.876 ; + END + END rw0_addr_in[3] + PIN rw0_addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 24.948 104.012 24.972 ; + END + END rw0_addr_in[4] + PIN rw0_addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 103.940 25.044 104.012 25.068 ; + END + END rw0_addr_in[5] + PIN rw0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 36.062 92.385 36.116 ; + END + END rw0_we_in + PIN rw0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.547 36.062 92.565 36.116 ; + END + END rw0_ce_in + PIN rw0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.727 36.062 92.745 36.116 ; + END + END rw0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 103.796 0.336 ; + RECT 0.216 1.008 103.796 1.104 ; + RECT 0.216 1.776 103.796 1.872 ; + RECT 0.216 2.544 103.796 2.640 ; + RECT 0.216 3.312 103.796 3.408 ; + RECT 0.216 4.080 103.796 4.176 ; + RECT 0.216 4.848 103.796 4.944 ; + RECT 0.216 5.616 103.796 5.712 ; + RECT 0.216 6.384 103.796 6.480 ; + RECT 0.216 7.152 103.796 7.248 ; + RECT 0.216 7.920 103.796 8.016 ; + RECT 0.216 8.688 103.796 8.784 ; + RECT 0.216 9.456 103.796 9.552 ; + RECT 0.216 10.224 103.796 10.320 ; + RECT 0.216 10.992 103.796 11.088 ; + RECT 0.216 11.760 103.796 11.856 ; + RECT 0.216 12.528 103.796 12.624 ; + RECT 0.216 13.296 103.796 13.392 ; + RECT 0.216 14.064 103.796 14.160 ; + RECT 0.216 14.832 103.796 14.928 ; + RECT 0.216 15.600 103.796 15.696 ; + RECT 0.216 16.368 103.796 16.464 ; + RECT 0.216 17.136 103.796 17.232 ; + RECT 0.216 17.904 103.796 18.000 ; + RECT 0.216 18.672 103.796 18.768 ; + RECT 0.216 19.440 103.796 19.536 ; + RECT 0.216 20.208 103.796 20.304 ; + RECT 0.216 20.976 103.796 21.072 ; + RECT 0.216 21.744 103.796 21.840 ; + RECT 0.216 22.512 103.796 22.608 ; + RECT 0.216 23.280 103.796 23.376 ; + RECT 0.216 24.048 103.796 24.144 ; + RECT 0.216 24.816 103.796 24.912 ; + RECT 0.216 25.584 103.796 25.680 ; + RECT 0.216 26.352 103.796 26.448 ; + RECT 0.216 27.120 103.796 27.216 ; + RECT 0.216 27.888 103.796 27.984 ; + RECT 0.216 28.656 103.796 28.752 ; + RECT 0.216 29.424 103.796 29.520 ; + RECT 0.216 30.192 103.796 30.288 ; + RECT 0.216 30.960 103.796 31.056 ; + RECT 0.216 31.728 103.796 31.824 ; + RECT 0.216 32.496 103.796 32.592 ; + RECT 0.216 33.264 103.796 33.360 ; + RECT 0.216 34.032 103.796 34.128 ; + RECT 0.216 34.800 103.796 34.896 ; + RECT 0.216 35.568 103.796 35.664 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 103.796 0.336 ; + RECT 0.216 1.008 103.796 1.104 ; + RECT 0.216 1.776 103.796 1.872 ; + RECT 0.216 2.544 103.796 2.640 ; + RECT 0.216 3.312 103.796 3.408 ; + RECT 0.216 4.080 103.796 4.176 ; + RECT 0.216 4.848 103.796 4.944 ; + RECT 0.216 5.616 103.796 5.712 ; + RECT 0.216 6.384 103.796 6.480 ; + RECT 0.216 7.152 103.796 7.248 ; + RECT 0.216 7.920 103.796 8.016 ; + RECT 0.216 8.688 103.796 8.784 ; + RECT 0.216 9.456 103.796 9.552 ; + RECT 0.216 10.224 103.796 10.320 ; + RECT 0.216 10.992 103.796 11.088 ; + RECT 0.216 11.760 103.796 11.856 ; + RECT 0.216 12.528 103.796 12.624 ; + RECT 0.216 13.296 103.796 13.392 ; + RECT 0.216 14.064 103.796 14.160 ; + RECT 0.216 14.832 103.796 14.928 ; + RECT 0.216 15.600 103.796 15.696 ; + RECT 0.216 16.368 103.796 16.464 ; + RECT 0.216 17.136 103.796 17.232 ; + RECT 0.216 17.904 103.796 18.000 ; + RECT 0.216 18.672 103.796 18.768 ; + RECT 0.216 19.440 103.796 19.536 ; + RECT 0.216 20.208 103.796 20.304 ; + RECT 0.216 20.976 103.796 21.072 ; + RECT 0.216 21.744 103.796 21.840 ; + RECT 0.216 22.512 103.796 22.608 ; + RECT 0.216 23.280 103.796 23.376 ; + RECT 0.216 24.048 103.796 24.144 ; + RECT 0.216 24.816 103.796 24.912 ; + RECT 0.216 25.584 103.796 25.680 ; + RECT 0.216 26.352 103.796 26.448 ; + RECT 0.216 27.120 103.796 27.216 ; + RECT 0.216 27.888 103.796 27.984 ; + RECT 0.216 28.656 103.796 28.752 ; + RECT 0.216 29.424 103.796 29.520 ; + RECT 0.216 30.192 103.796 30.288 ; + RECT 0.216 30.960 103.796 31.056 ; + RECT 0.216 31.728 103.796 31.824 ; + RECT 0.216 32.496 103.796 32.592 ; + RECT 0.216 33.264 103.796 33.360 ; + RECT 0.216 34.032 103.796 34.128 ; + RECT 0.216 34.800 103.796 34.896 ; + RECT 0.216 35.568 103.796 35.664 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 104.012 36.116 ; + LAYER M2 ; + RECT 0 0 104.012 36.116 ; + LAYER M3 ; + RECT 0 0 104.012 36.116 ; + LAYER M4 ; + RECT 0 0 104.012 36.116 ; + END +END fakeram_512x64_1rw + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_560x4_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_560x4_1r1w.lef new file mode 100644 index 0000000..3ea7893 --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_560x4_1r1w.lef @@ -0,0 +1,15367 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_560x4_1r1w + FOREIGN fakeram_560x4_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 178.537 BY 50.303 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.420 0.072 0.444 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.148 0.072 2.172 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.012 0.072 3.036 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.452 0.072 4.476 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.468 0.072 6.492 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.908 0.072 7.932 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.772 0.072 8.796 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.060 0.072 9.084 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.924 0.072 9.948 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.500 0.072 10.524 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.788 0.072 10.812 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.652 0.072 11.676 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.228 0.072 12.252 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.244 0.072 14.268 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.108 0.072 15.132 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.684 0.072 15.708 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.972 0.072 15.996 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.548 0.072 16.572 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.700 0.072 17.724 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.564 0.072 18.588 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.140 0.072 19.164 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.004 0.072 20.028 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.292 0.072 20.316 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 0.276 178.537 0.300 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 0.420 178.537 0.444 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 0.564 178.537 0.588 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 0.708 178.537 0.732 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 0.852 178.537 0.876 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 0.996 178.537 1.020 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 1.140 178.537 1.164 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 1.284 178.537 1.308 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 1.428 178.537 1.452 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 1.572 178.537 1.596 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 1.716 178.537 1.740 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 1.860 178.537 1.884 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.004 178.537 2.028 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.148 178.537 2.172 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.292 178.537 2.316 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.436 178.537 2.460 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.580 178.537 2.604 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.724 178.537 2.748 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 2.868 178.537 2.892 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.012 178.537 3.036 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.156 178.537 3.180 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.300 178.537 3.324 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.444 178.537 3.468 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.588 178.537 3.612 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.732 178.537 3.756 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 3.876 178.537 3.900 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.020 178.537 4.044 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.164 178.537 4.188 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.308 178.537 4.332 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.452 178.537 4.476 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.596 178.537 4.620 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.740 178.537 4.764 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 4.884 178.537 4.908 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.028 178.537 5.052 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.172 178.537 5.196 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.316 178.537 5.340 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.460 178.537 5.484 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.604 178.537 5.628 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.748 178.537 5.772 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 5.892 178.537 5.916 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.036 178.537 6.060 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.180 178.537 6.204 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.324 178.537 6.348 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.468 178.537 6.492 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.612 178.537 6.636 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.756 178.537 6.780 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 6.900 178.537 6.924 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.044 178.537 7.068 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.188 178.537 7.212 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.332 178.537 7.356 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.476 178.537 7.500 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.620 178.537 7.644 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.764 178.537 7.788 ; + END + END w0_wmask_in[192] + PIN w0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 7.908 178.537 7.932 ; + END + END w0_wmask_in[193] + PIN w0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.052 178.537 8.076 ; + END + END w0_wmask_in[194] + PIN w0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.196 178.537 8.220 ; + END + END w0_wmask_in[195] + PIN w0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.340 178.537 8.364 ; + END + END w0_wmask_in[196] + PIN w0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.484 178.537 8.508 ; + END + END w0_wmask_in[197] + PIN w0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.628 178.537 8.652 ; + END + END w0_wmask_in[198] + PIN w0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.772 178.537 8.796 ; + END + END w0_wmask_in[199] + PIN w0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 8.916 178.537 8.940 ; + END + END w0_wmask_in[200] + PIN w0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.060 178.537 9.084 ; + END + END w0_wmask_in[201] + PIN w0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.204 178.537 9.228 ; + END + END w0_wmask_in[202] + PIN w0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.348 178.537 9.372 ; + END + END w0_wmask_in[203] + PIN w0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.492 178.537 9.516 ; + END + END w0_wmask_in[204] + PIN w0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.636 178.537 9.660 ; + END + END w0_wmask_in[205] + PIN w0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.780 178.537 9.804 ; + END + END w0_wmask_in[206] + PIN w0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 9.924 178.537 9.948 ; + END + END w0_wmask_in[207] + PIN w0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.068 178.537 10.092 ; + END + END w0_wmask_in[208] + PIN w0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.212 178.537 10.236 ; + END + END w0_wmask_in[209] + PIN w0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.356 178.537 10.380 ; + END + END w0_wmask_in[210] + PIN w0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.500 178.537 10.524 ; + END + END w0_wmask_in[211] + PIN w0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.644 178.537 10.668 ; + END + END w0_wmask_in[212] + PIN w0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.788 178.537 10.812 ; + END + END w0_wmask_in[213] + PIN w0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 10.932 178.537 10.956 ; + END + END w0_wmask_in[214] + PIN w0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.076 178.537 11.100 ; + END + END w0_wmask_in[215] + PIN w0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.220 178.537 11.244 ; + END + END w0_wmask_in[216] + PIN w0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.364 178.537 11.388 ; + END + END w0_wmask_in[217] + PIN w0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.508 178.537 11.532 ; + END + END w0_wmask_in[218] + PIN w0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.652 178.537 11.676 ; + END + END w0_wmask_in[219] + PIN w0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.796 178.537 11.820 ; + END + END w0_wmask_in[220] + PIN w0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 11.940 178.537 11.964 ; + END + END w0_wmask_in[221] + PIN w0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.084 178.537 12.108 ; + END + END w0_wmask_in[222] + PIN w0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.228 178.537 12.252 ; + END + END w0_wmask_in[223] + PIN w0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.372 178.537 12.396 ; + END + END w0_wmask_in[224] + PIN w0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.516 178.537 12.540 ; + END + END w0_wmask_in[225] + PIN w0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.660 178.537 12.684 ; + END + END w0_wmask_in[226] + PIN w0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.804 178.537 12.828 ; + END + END w0_wmask_in[227] + PIN w0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 12.948 178.537 12.972 ; + END + END w0_wmask_in[228] + PIN w0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.092 178.537 13.116 ; + END + END w0_wmask_in[229] + PIN w0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.236 178.537 13.260 ; + END + END w0_wmask_in[230] + PIN w0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.380 178.537 13.404 ; + END + END w0_wmask_in[231] + PIN w0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.524 178.537 13.548 ; + END + END w0_wmask_in[232] + PIN w0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.668 178.537 13.692 ; + END + END w0_wmask_in[233] + PIN w0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.812 178.537 13.836 ; + END + END w0_wmask_in[234] + PIN w0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 13.956 178.537 13.980 ; + END + END w0_wmask_in[235] + PIN w0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.100 178.537 14.124 ; + END + END w0_wmask_in[236] + PIN w0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.244 178.537 14.268 ; + END + END w0_wmask_in[237] + PIN w0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.388 178.537 14.412 ; + END + END w0_wmask_in[238] + PIN w0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.532 178.537 14.556 ; + END + END w0_wmask_in[239] + PIN w0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.676 178.537 14.700 ; + END + END w0_wmask_in[240] + PIN w0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.820 178.537 14.844 ; + END + END w0_wmask_in[241] + PIN w0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 14.964 178.537 14.988 ; + END + END w0_wmask_in[242] + PIN w0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.108 178.537 15.132 ; + END + END w0_wmask_in[243] + PIN w0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.252 178.537 15.276 ; + END + END w0_wmask_in[244] + PIN w0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.396 178.537 15.420 ; + END + END w0_wmask_in[245] + PIN w0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.540 178.537 15.564 ; + END + END w0_wmask_in[246] + PIN w0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.684 178.537 15.708 ; + END + END w0_wmask_in[247] + PIN w0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.828 178.537 15.852 ; + END + END w0_wmask_in[248] + PIN w0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 15.972 178.537 15.996 ; + END + END w0_wmask_in[249] + PIN w0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.116 178.537 16.140 ; + END + END w0_wmask_in[250] + PIN w0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.260 178.537 16.284 ; + END + END w0_wmask_in[251] + PIN w0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.404 178.537 16.428 ; + END + END w0_wmask_in[252] + PIN w0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.548 178.537 16.572 ; + END + END w0_wmask_in[253] + PIN w0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.692 178.537 16.716 ; + END + END w0_wmask_in[254] + PIN w0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.836 178.537 16.860 ; + END + END w0_wmask_in[255] + PIN w0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 16.980 178.537 17.004 ; + END + END w0_wmask_in[256] + PIN w0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.124 178.537 17.148 ; + END + END w0_wmask_in[257] + PIN w0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.268 178.537 17.292 ; + END + END w0_wmask_in[258] + PIN w0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.412 178.537 17.436 ; + END + END w0_wmask_in[259] + PIN w0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.556 178.537 17.580 ; + END + END w0_wmask_in[260] + PIN w0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.700 178.537 17.724 ; + END + END w0_wmask_in[261] + PIN w0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.844 178.537 17.868 ; + END + END w0_wmask_in[262] + PIN w0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 17.988 178.537 18.012 ; + END + END w0_wmask_in[263] + PIN w0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.132 178.537 18.156 ; + END + END w0_wmask_in[264] + PIN w0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.276 178.537 18.300 ; + END + END w0_wmask_in[265] + PIN w0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.420 178.537 18.444 ; + END + END w0_wmask_in[266] + PIN w0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.564 178.537 18.588 ; + END + END w0_wmask_in[267] + PIN w0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.708 178.537 18.732 ; + END + END w0_wmask_in[268] + PIN w0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.852 178.537 18.876 ; + END + END w0_wmask_in[269] + PIN w0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 18.996 178.537 19.020 ; + END + END w0_wmask_in[270] + PIN w0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 19.140 178.537 19.164 ; + END + END w0_wmask_in[271] + PIN w0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 19.284 178.537 19.308 ; + END + END w0_wmask_in[272] + PIN w0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 19.428 178.537 19.452 ; + END + END w0_wmask_in[273] + PIN w0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 19.572 178.537 19.596 ; + END + END w0_wmask_in[274] + PIN w0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 19.716 178.537 19.740 ; + END + END w0_wmask_in[275] + PIN w0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 19.860 178.537 19.884 ; + END + END w0_wmask_in[276] + PIN w0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.004 178.537 20.028 ; + END + END w0_wmask_in[277] + PIN w0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.148 178.537 20.172 ; + END + END w0_wmask_in[278] + PIN w0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.292 178.537 20.316 ; + END + END w0_wmask_in[279] + PIN w0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 50.249 0.225 50.303 ; + END + END w0_wmask_in[280] + PIN w0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 50.249 0.513 50.303 ; + END + END w0_wmask_in[281] + PIN w0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 50.249 0.801 50.303 ; + END + END w0_wmask_in[282] + PIN w0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 50.249 1.089 50.303 ; + END + END w0_wmask_in[283] + PIN w0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 50.249 1.377 50.303 ; + END + END w0_wmask_in[284] + PIN w0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 50.249 1.665 50.303 ; + END + END w0_wmask_in[285] + PIN w0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 50.249 1.953 50.303 ; + END + END w0_wmask_in[286] + PIN w0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 50.249 2.241 50.303 ; + END + END w0_wmask_in[287] + PIN w0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 50.249 2.529 50.303 ; + END + END w0_wmask_in[288] + PIN w0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 50.249 2.817 50.303 ; + END + END w0_wmask_in[289] + PIN w0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 50.249 3.105 50.303 ; + END + END w0_wmask_in[290] + PIN w0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 50.249 3.393 50.303 ; + END + END w0_wmask_in[291] + PIN w0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 50.249 3.681 50.303 ; + END + END w0_wmask_in[292] + PIN w0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 50.249 3.969 50.303 ; + END + END w0_wmask_in[293] + PIN w0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 50.249 4.257 50.303 ; + END + END w0_wmask_in[294] + PIN w0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 50.249 4.545 50.303 ; + END + END w0_wmask_in[295] + PIN w0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 50.249 4.833 50.303 ; + END + END w0_wmask_in[296] + PIN w0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 50.249 5.121 50.303 ; + END + END w0_wmask_in[297] + PIN w0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 50.249 5.409 50.303 ; + END + END w0_wmask_in[298] + PIN w0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 50.249 5.697 50.303 ; + END + END w0_wmask_in[299] + PIN w0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 50.249 5.985 50.303 ; + END + END w0_wmask_in[300] + PIN w0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 50.249 6.273 50.303 ; + END + END w0_wmask_in[301] + PIN w0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 50.249 6.561 50.303 ; + END + END w0_wmask_in[302] + PIN w0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 50.249 6.849 50.303 ; + END + END w0_wmask_in[303] + PIN w0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 50.249 7.137 50.303 ; + END + END w0_wmask_in[304] + PIN w0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 50.249 7.425 50.303 ; + END + END w0_wmask_in[305] + PIN w0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 50.249 7.713 50.303 ; + END + END w0_wmask_in[306] + PIN w0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 50.249 8.001 50.303 ; + END + END w0_wmask_in[307] + PIN w0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 50.249 8.289 50.303 ; + END + END w0_wmask_in[308] + PIN w0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 50.249 8.577 50.303 ; + END + END w0_wmask_in[309] + PIN w0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 50.249 8.865 50.303 ; + END + END w0_wmask_in[310] + PIN w0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 50.249 9.153 50.303 ; + END + END w0_wmask_in[311] + PIN w0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 50.249 9.441 50.303 ; + END + END w0_wmask_in[312] + PIN w0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 50.249 9.729 50.303 ; + END + END w0_wmask_in[313] + PIN w0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 50.249 10.017 50.303 ; + END + END w0_wmask_in[314] + PIN w0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 50.249 10.305 50.303 ; + END + END w0_wmask_in[315] + PIN w0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 50.249 10.593 50.303 ; + END + END w0_wmask_in[316] + PIN w0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 50.249 10.881 50.303 ; + END + END w0_wmask_in[317] + PIN w0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 50.249 11.169 50.303 ; + END + END w0_wmask_in[318] + PIN w0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 50.249 11.457 50.303 ; + END + END w0_wmask_in[319] + PIN w0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 50.249 11.745 50.303 ; + END + END w0_wmask_in[320] + PIN w0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 50.249 12.033 50.303 ; + END + END w0_wmask_in[321] + PIN w0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 50.249 12.321 50.303 ; + END + END w0_wmask_in[322] + PIN w0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 50.249 12.609 50.303 ; + END + END w0_wmask_in[323] + PIN w0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 50.249 12.897 50.303 ; + END + END w0_wmask_in[324] + PIN w0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 50.249 13.185 50.303 ; + END + END w0_wmask_in[325] + PIN w0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 50.249 13.473 50.303 ; + END + END w0_wmask_in[326] + PIN w0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 50.249 13.761 50.303 ; + END + END w0_wmask_in[327] + PIN w0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 50.249 14.049 50.303 ; + END + END w0_wmask_in[328] + PIN w0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 50.249 14.337 50.303 ; + END + END w0_wmask_in[329] + PIN w0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 50.249 14.625 50.303 ; + END + END w0_wmask_in[330] + PIN w0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 50.249 14.913 50.303 ; + END + END w0_wmask_in[331] + PIN w0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 50.249 15.201 50.303 ; + END + END w0_wmask_in[332] + PIN w0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 50.249 15.489 50.303 ; + END + END w0_wmask_in[333] + PIN w0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 50.249 15.777 50.303 ; + END + END w0_wmask_in[334] + PIN w0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 50.249 16.065 50.303 ; + END + END w0_wmask_in[335] + PIN w0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 50.249 16.353 50.303 ; + END + END w0_wmask_in[336] + PIN w0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 50.249 16.641 50.303 ; + END + END w0_wmask_in[337] + PIN w0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 50.249 16.929 50.303 ; + END + END w0_wmask_in[338] + PIN w0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 50.249 17.217 50.303 ; + END + END w0_wmask_in[339] + PIN w0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 50.249 17.505 50.303 ; + END + END w0_wmask_in[340] + PIN w0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 50.249 17.793 50.303 ; + END + END w0_wmask_in[341] + PIN w0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 50.249 18.081 50.303 ; + END + END w0_wmask_in[342] + PIN w0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 50.249 18.369 50.303 ; + END + END w0_wmask_in[343] + PIN w0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 50.249 18.657 50.303 ; + END + END w0_wmask_in[344] + PIN w0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 50.249 18.945 50.303 ; + END + END w0_wmask_in[345] + PIN w0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 50.249 19.233 50.303 ; + END + END w0_wmask_in[346] + PIN w0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 50.249 19.521 50.303 ; + END + END w0_wmask_in[347] + PIN w0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 50.249 19.809 50.303 ; + END + END w0_wmask_in[348] + PIN w0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 50.249 20.097 50.303 ; + END + END w0_wmask_in[349] + PIN w0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 50.249 20.385 50.303 ; + END + END w0_wmask_in[350] + PIN w0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 50.249 20.673 50.303 ; + END + END w0_wmask_in[351] + PIN w0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 50.249 20.961 50.303 ; + END + END w0_wmask_in[352] + PIN w0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 50.249 21.249 50.303 ; + END + END w0_wmask_in[353] + PIN w0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 50.249 21.537 50.303 ; + END + END w0_wmask_in[354] + PIN w0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 50.249 21.825 50.303 ; + END + END w0_wmask_in[355] + PIN w0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 50.249 22.113 50.303 ; + END + END w0_wmask_in[356] + PIN w0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 50.249 22.401 50.303 ; + END + END w0_wmask_in[357] + PIN w0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 50.249 22.689 50.303 ; + END + END w0_wmask_in[358] + PIN w0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 50.249 22.977 50.303 ; + END + END w0_wmask_in[359] + PIN w0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 50.249 23.265 50.303 ; + END + END w0_wmask_in[360] + PIN w0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 50.249 23.553 50.303 ; + END + END w0_wmask_in[361] + PIN w0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 50.249 23.841 50.303 ; + END + END w0_wmask_in[362] + PIN w0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 50.249 24.129 50.303 ; + END + END w0_wmask_in[363] + PIN w0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 50.249 24.417 50.303 ; + END + END w0_wmask_in[364] + PIN w0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 50.249 24.705 50.303 ; + END + END w0_wmask_in[365] + PIN w0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 50.249 24.993 50.303 ; + END + END w0_wmask_in[366] + PIN w0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 50.249 25.281 50.303 ; + END + END w0_wmask_in[367] + PIN w0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 50.249 25.569 50.303 ; + END + END w0_wmask_in[368] + PIN w0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 50.249 25.857 50.303 ; + END + END w0_wmask_in[369] + PIN w0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 50.249 26.145 50.303 ; + END + END w0_wmask_in[370] + PIN w0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 50.249 26.433 50.303 ; + END + END w0_wmask_in[371] + PIN w0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 50.249 26.721 50.303 ; + END + END w0_wmask_in[372] + PIN w0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 50.249 27.009 50.303 ; + END + END w0_wmask_in[373] + PIN w0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 50.249 27.297 50.303 ; + END + END w0_wmask_in[374] + PIN w0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 50.249 27.585 50.303 ; + END + END w0_wmask_in[375] + PIN w0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 50.249 27.873 50.303 ; + END + END w0_wmask_in[376] + PIN w0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 50.249 28.161 50.303 ; + END + END w0_wmask_in[377] + PIN w0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 50.249 28.449 50.303 ; + END + END w0_wmask_in[378] + PIN w0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 50.249 28.737 50.303 ; + END + END w0_wmask_in[379] + PIN w0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 50.249 29.025 50.303 ; + END + END w0_wmask_in[380] + PIN w0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 50.249 29.313 50.303 ; + END + END w0_wmask_in[381] + PIN w0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 50.249 29.601 50.303 ; + END + END w0_wmask_in[382] + PIN w0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 50.249 29.889 50.303 ; + END + END w0_wmask_in[383] + PIN w0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 50.249 30.177 50.303 ; + END + END w0_wmask_in[384] + PIN w0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 50.249 30.465 50.303 ; + END + END w0_wmask_in[385] + PIN w0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 50.249 30.753 50.303 ; + END + END w0_wmask_in[386] + PIN w0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 50.249 31.041 50.303 ; + END + END w0_wmask_in[387] + PIN w0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 50.249 31.329 50.303 ; + END + END w0_wmask_in[388] + PIN w0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 50.249 31.617 50.303 ; + END + END w0_wmask_in[389] + PIN w0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 50.249 31.905 50.303 ; + END + END w0_wmask_in[390] + PIN w0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 50.249 32.193 50.303 ; + END + END w0_wmask_in[391] + PIN w0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 50.249 32.481 50.303 ; + END + END w0_wmask_in[392] + PIN w0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 50.249 32.769 50.303 ; + END + END w0_wmask_in[393] + PIN w0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 50.249 33.057 50.303 ; + END + END w0_wmask_in[394] + PIN w0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 50.249 33.345 50.303 ; + END + END w0_wmask_in[395] + PIN w0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 50.249 33.633 50.303 ; + END + END w0_wmask_in[396] + PIN w0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 50.249 33.921 50.303 ; + END + END w0_wmask_in[397] + PIN w0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 50.249 34.209 50.303 ; + END + END w0_wmask_in[398] + PIN w0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 50.249 34.497 50.303 ; + END + END w0_wmask_in[399] + PIN w0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 50.249 34.785 50.303 ; + END + END w0_wmask_in[400] + PIN w0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 50.249 35.073 50.303 ; + END + END w0_wmask_in[401] + PIN w0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 50.249 35.361 50.303 ; + END + END w0_wmask_in[402] + PIN w0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 50.249 35.649 50.303 ; + END + END w0_wmask_in[403] + PIN w0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 50.249 35.937 50.303 ; + END + END w0_wmask_in[404] + PIN w0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 50.249 36.225 50.303 ; + END + END w0_wmask_in[405] + PIN w0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 50.249 36.513 50.303 ; + END + END w0_wmask_in[406] + PIN w0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 50.249 36.801 50.303 ; + END + END w0_wmask_in[407] + PIN w0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 50.249 37.089 50.303 ; + END + END w0_wmask_in[408] + PIN w0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 50.249 37.377 50.303 ; + END + END w0_wmask_in[409] + PIN w0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 50.249 37.665 50.303 ; + END + END w0_wmask_in[410] + PIN w0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 50.249 37.953 50.303 ; + END + END w0_wmask_in[411] + PIN w0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 50.249 38.241 50.303 ; + END + END w0_wmask_in[412] + PIN w0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 50.249 38.529 50.303 ; + END + END w0_wmask_in[413] + PIN w0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 50.249 38.817 50.303 ; + END + END w0_wmask_in[414] + PIN w0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 50.249 39.105 50.303 ; + END + END w0_wmask_in[415] + PIN w0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 50.249 39.393 50.303 ; + END + END w0_wmask_in[416] + PIN w0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 50.249 39.681 50.303 ; + END + END w0_wmask_in[417] + PIN w0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 50.249 39.969 50.303 ; + END + END w0_wmask_in[418] + PIN w0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 50.249 40.257 50.303 ; + END + END w0_wmask_in[419] + PIN w0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 50.249 40.545 50.303 ; + END + END w0_wmask_in[420] + PIN w0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 50.249 40.833 50.303 ; + END + END w0_wmask_in[421] + PIN w0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 50.249 41.121 50.303 ; + END + END w0_wmask_in[422] + PIN w0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 50.249 41.409 50.303 ; + END + END w0_wmask_in[423] + PIN w0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 50.249 41.697 50.303 ; + END + END w0_wmask_in[424] + PIN w0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 50.249 41.985 50.303 ; + END + END w0_wmask_in[425] + PIN w0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 50.249 42.273 50.303 ; + END + END w0_wmask_in[426] + PIN w0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 50.249 42.561 50.303 ; + END + END w0_wmask_in[427] + PIN w0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 50.249 42.849 50.303 ; + END + END w0_wmask_in[428] + PIN w0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 50.249 43.137 50.303 ; + END + END w0_wmask_in[429] + PIN w0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 50.249 43.425 50.303 ; + END + END w0_wmask_in[430] + PIN w0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 50.249 43.713 50.303 ; + END + END w0_wmask_in[431] + PIN w0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 50.249 44.001 50.303 ; + END + END w0_wmask_in[432] + PIN w0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 50.249 44.289 50.303 ; + END + END w0_wmask_in[433] + PIN w0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 50.249 44.577 50.303 ; + END + END w0_wmask_in[434] + PIN w0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 50.249 44.865 50.303 ; + END + END w0_wmask_in[435] + PIN w0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 50.249 45.153 50.303 ; + END + END w0_wmask_in[436] + PIN w0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 50.249 45.441 50.303 ; + END + END w0_wmask_in[437] + PIN w0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 50.249 45.729 50.303 ; + END + END w0_wmask_in[438] + PIN w0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 50.249 46.017 50.303 ; + END + END w0_wmask_in[439] + PIN w0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 50.249 46.305 50.303 ; + END + END w0_wmask_in[440] + PIN w0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 50.249 46.593 50.303 ; + END + END w0_wmask_in[441] + PIN w0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 50.249 46.881 50.303 ; + END + END w0_wmask_in[442] + PIN w0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 50.249 47.169 50.303 ; + END + END w0_wmask_in[443] + PIN w0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 50.249 47.457 50.303 ; + END + END w0_wmask_in[444] + PIN w0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 50.249 47.745 50.303 ; + END + END w0_wmask_in[445] + PIN w0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 50.249 48.033 50.303 ; + END + END w0_wmask_in[446] + PIN w0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 50.249 48.321 50.303 ; + END + END w0_wmask_in[447] + PIN w0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 50.249 48.609 50.303 ; + END + END w0_wmask_in[448] + PIN w0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 50.249 48.897 50.303 ; + END + END w0_wmask_in[449] + PIN w0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 50.249 49.185 50.303 ; + END + END w0_wmask_in[450] + PIN w0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 50.249 49.473 50.303 ; + END + END w0_wmask_in[451] + PIN w0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 50.249 49.761 50.303 ; + END + END w0_wmask_in[452] + PIN w0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 50.249 50.049 50.303 ; + END + END w0_wmask_in[453] + PIN w0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 50.249 50.337 50.303 ; + END + END w0_wmask_in[454] + PIN w0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 50.249 50.625 50.303 ; + END + END w0_wmask_in[455] + PIN w0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 50.249 50.913 50.303 ; + END + END w0_wmask_in[456] + PIN w0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 50.249 51.201 50.303 ; + END + END w0_wmask_in[457] + PIN w0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 50.249 51.489 50.303 ; + END + END w0_wmask_in[458] + PIN w0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 50.249 51.777 50.303 ; + END + END w0_wmask_in[459] + PIN w0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 50.249 52.065 50.303 ; + END + END w0_wmask_in[460] + PIN w0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 50.249 52.353 50.303 ; + END + END w0_wmask_in[461] + PIN w0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 50.249 52.641 50.303 ; + END + END w0_wmask_in[462] + PIN w0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 50.249 52.929 50.303 ; + END + END w0_wmask_in[463] + PIN w0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 50.249 53.217 50.303 ; + END + END w0_wmask_in[464] + PIN w0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 50.249 53.505 50.303 ; + END + END w0_wmask_in[465] + PIN w0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 50.249 53.793 50.303 ; + END + END w0_wmask_in[466] + PIN w0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 50.249 54.081 50.303 ; + END + END w0_wmask_in[467] + PIN w0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 50.249 54.369 50.303 ; + END + END w0_wmask_in[468] + PIN w0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 50.249 54.657 50.303 ; + END + END w0_wmask_in[469] + PIN w0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 50.249 54.945 50.303 ; + END + END w0_wmask_in[470] + PIN w0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 50.249 55.233 50.303 ; + END + END w0_wmask_in[471] + PIN w0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 50.249 55.521 50.303 ; + END + END w0_wmask_in[472] + PIN w0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 50.249 55.809 50.303 ; + END + END w0_wmask_in[473] + PIN w0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 50.249 56.097 50.303 ; + END + END w0_wmask_in[474] + PIN w0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 50.249 56.385 50.303 ; + END + END w0_wmask_in[475] + PIN w0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 50.249 56.673 50.303 ; + END + END w0_wmask_in[476] + PIN w0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 50.249 56.961 50.303 ; + END + END w0_wmask_in[477] + PIN w0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 50.249 57.249 50.303 ; + END + END w0_wmask_in[478] + PIN w0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 50.249 57.537 50.303 ; + END + END w0_wmask_in[479] + PIN w0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 50.249 57.825 50.303 ; + END + END w0_wmask_in[480] + PIN w0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 50.249 58.113 50.303 ; + END + END w0_wmask_in[481] + PIN w0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 50.249 58.401 50.303 ; + END + END w0_wmask_in[482] + PIN w0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 50.249 58.689 50.303 ; + END + END w0_wmask_in[483] + PIN w0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 50.249 58.977 50.303 ; + END + END w0_wmask_in[484] + PIN w0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 50.249 59.265 50.303 ; + END + END w0_wmask_in[485] + PIN w0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 50.249 59.553 50.303 ; + END + END w0_wmask_in[486] + PIN w0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 50.249 59.841 50.303 ; + END + END w0_wmask_in[487] + PIN w0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 50.249 60.129 50.303 ; + END + END w0_wmask_in[488] + PIN w0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 50.249 60.417 50.303 ; + END + END w0_wmask_in[489] + PIN w0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 50.249 60.705 50.303 ; + END + END w0_wmask_in[490] + PIN w0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 50.249 60.993 50.303 ; + END + END w0_wmask_in[491] + PIN w0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 50.249 61.281 50.303 ; + END + END w0_wmask_in[492] + PIN w0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 50.249 61.569 50.303 ; + END + END w0_wmask_in[493] + PIN w0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 50.249 61.857 50.303 ; + END + END w0_wmask_in[494] + PIN w0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 50.249 62.145 50.303 ; + END + END w0_wmask_in[495] + PIN w0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 50.249 62.433 50.303 ; + END + END w0_wmask_in[496] + PIN w0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 50.249 62.721 50.303 ; + END + END w0_wmask_in[497] + PIN w0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 50.249 63.009 50.303 ; + END + END w0_wmask_in[498] + PIN w0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 50.249 63.297 50.303 ; + END + END w0_wmask_in[499] + PIN w0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 50.249 63.585 50.303 ; + END + END w0_wmask_in[500] + PIN w0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 50.249 63.873 50.303 ; + END + END w0_wmask_in[501] + PIN w0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 50.249 64.161 50.303 ; + END + END w0_wmask_in[502] + PIN w0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 50.249 64.449 50.303 ; + END + END w0_wmask_in[503] + PIN w0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 50.249 64.737 50.303 ; + END + END w0_wmask_in[504] + PIN w0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 50.249 65.025 50.303 ; + END + END w0_wmask_in[505] + PIN w0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 50.249 65.313 50.303 ; + END + END w0_wmask_in[506] + PIN w0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 50.249 65.601 50.303 ; + END + END w0_wmask_in[507] + PIN w0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 50.249 65.889 50.303 ; + END + END w0_wmask_in[508] + PIN w0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 50.249 66.177 50.303 ; + END + END w0_wmask_in[509] + PIN w0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 50.249 66.465 50.303 ; + END + END w0_wmask_in[510] + PIN w0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 50.249 66.753 50.303 ; + END + END w0_wmask_in[511] + PIN w0_wmask_in[512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 50.249 67.041 50.303 ; + END + END w0_wmask_in[512] + PIN w0_wmask_in[513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 50.249 67.329 50.303 ; + END + END w0_wmask_in[513] + PIN w0_wmask_in[514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 50.249 67.617 50.303 ; + END + END w0_wmask_in[514] + PIN w0_wmask_in[515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 50.249 67.905 50.303 ; + END + END w0_wmask_in[515] + PIN w0_wmask_in[516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 50.249 68.193 50.303 ; + END + END w0_wmask_in[516] + PIN w0_wmask_in[517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 50.249 68.481 50.303 ; + END + END w0_wmask_in[517] + PIN w0_wmask_in[518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 50.249 68.769 50.303 ; + END + END w0_wmask_in[518] + PIN w0_wmask_in[519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 50.249 69.057 50.303 ; + END + END w0_wmask_in[519] + PIN w0_wmask_in[520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 50.249 69.345 50.303 ; + END + END w0_wmask_in[520] + PIN w0_wmask_in[521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 50.249 69.633 50.303 ; + END + END w0_wmask_in[521] + PIN w0_wmask_in[522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 50.249 69.921 50.303 ; + END + END w0_wmask_in[522] + PIN w0_wmask_in[523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 50.249 70.209 50.303 ; + END + END w0_wmask_in[523] + PIN w0_wmask_in[524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 50.249 70.497 50.303 ; + END + END w0_wmask_in[524] + PIN w0_wmask_in[525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 50.249 70.785 50.303 ; + END + END w0_wmask_in[525] + PIN w0_wmask_in[526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 50.249 71.073 50.303 ; + END + END w0_wmask_in[526] + PIN w0_wmask_in[527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 50.249 71.361 50.303 ; + END + END w0_wmask_in[527] + PIN w0_wmask_in[528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 50.249 71.649 50.303 ; + END + END w0_wmask_in[528] + PIN w0_wmask_in[529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 50.249 71.937 50.303 ; + END + END w0_wmask_in[529] + PIN w0_wmask_in[530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 50.249 72.225 50.303 ; + END + END w0_wmask_in[530] + PIN w0_wmask_in[531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 50.249 72.513 50.303 ; + END + END w0_wmask_in[531] + PIN w0_wmask_in[532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 50.249 72.801 50.303 ; + END + END w0_wmask_in[532] + PIN w0_wmask_in[533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 50.249 73.089 50.303 ; + END + END w0_wmask_in[533] + PIN w0_wmask_in[534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 50.249 73.377 50.303 ; + END + END w0_wmask_in[534] + PIN w0_wmask_in[535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 50.249 73.665 50.303 ; + END + END w0_wmask_in[535] + PIN w0_wmask_in[536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 50.249 73.953 50.303 ; + END + END w0_wmask_in[536] + PIN w0_wmask_in[537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 50.249 74.241 50.303 ; + END + END w0_wmask_in[537] + PIN w0_wmask_in[538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 50.249 74.529 50.303 ; + END + END w0_wmask_in[538] + PIN w0_wmask_in[539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 50.249 74.817 50.303 ; + END + END w0_wmask_in[539] + PIN w0_wmask_in[540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 50.249 75.105 50.303 ; + END + END w0_wmask_in[540] + PIN w0_wmask_in[541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 50.249 75.393 50.303 ; + END + END w0_wmask_in[541] + PIN w0_wmask_in[542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 50.249 75.681 50.303 ; + END + END w0_wmask_in[542] + PIN w0_wmask_in[543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 50.249 75.969 50.303 ; + END + END w0_wmask_in[543] + PIN w0_wmask_in[544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 50.249 76.257 50.303 ; + END + END w0_wmask_in[544] + PIN w0_wmask_in[545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 50.249 76.545 50.303 ; + END + END w0_wmask_in[545] + PIN w0_wmask_in[546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 50.249 76.833 50.303 ; + END + END w0_wmask_in[546] + PIN w0_wmask_in[547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 50.249 77.121 50.303 ; + END + END w0_wmask_in[547] + PIN w0_wmask_in[548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 50.249 77.409 50.303 ; + END + END w0_wmask_in[548] + PIN w0_wmask_in[549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 50.249 77.697 50.303 ; + END + END w0_wmask_in[549] + PIN w0_wmask_in[550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 50.249 77.985 50.303 ; + END + END w0_wmask_in[550] + PIN w0_wmask_in[551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 50.249 78.273 50.303 ; + END + END w0_wmask_in[551] + PIN w0_wmask_in[552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 50.249 78.561 50.303 ; + END + END w0_wmask_in[552] + PIN w0_wmask_in[553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 50.249 78.849 50.303 ; + END + END w0_wmask_in[553] + PIN w0_wmask_in[554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 50.249 79.137 50.303 ; + END + END w0_wmask_in[554] + PIN w0_wmask_in[555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 50.249 79.425 50.303 ; + END + END w0_wmask_in[555] + PIN w0_wmask_in[556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 50.249 79.713 50.303 ; + END + END w0_wmask_in[556] + PIN w0_wmask_in[557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 50.249 80.001 50.303 ; + END + END w0_wmask_in[557] + PIN w0_wmask_in[558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 50.249 80.289 50.303 ; + END + END w0_wmask_in[558] + PIN w0_wmask_in[559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 50.249 80.577 50.303 ; + END + END w0_wmask_in[559] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.868 0.072 20.892 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.156 0.072 21.180 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.732 0.072 21.756 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.020 0.072 22.044 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.596 0.072 22.620 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.884 0.072 22.908 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.748 0.072 23.772 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.324 0.072 24.348 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.612 0.072 24.636 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.188 0.072 25.212 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.052 0.072 26.076 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.340 0.072 26.364 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.916 0.072 26.940 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.204 0.072 27.228 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.780 0.072 27.804 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.068 0.072 28.092 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.212 0.072 28.236 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.644 0.072 28.668 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.932 0.072 28.956 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.508 0.072 29.532 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.796 0.072 29.820 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.940 0.072 29.964 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.372 0.072 30.396 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.660 0.072 30.684 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.092 0.072 31.116 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.236 0.072 31.260 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.668 0.072 31.692 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.100 0.072 32.124 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.388 0.072 32.412 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.820 0.072 32.844 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.964 0.072 32.988 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.252 0.072 33.276 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.828 0.072 33.852 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.116 0.072 34.140 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.404 0.072 34.428 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.692 0.072 34.716 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.980 0.072 35.004 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.124 0.072 35.148 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.268 0.072 35.292 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.556 0.072 35.580 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.844 0.072 35.868 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.132 0.072 36.156 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.420 0.072 36.444 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.708 0.072 36.732 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.852 0.072 36.876 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.996 0.072 37.020 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.284 0.072 37.308 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.860 0.072 37.884 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.004 0.072 38.028 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.148 0.072 38.172 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.436 0.072 38.460 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.724 0.072 38.748 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.868 0.072 38.892 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.012 0.072 39.036 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.300 0.072 39.324 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.588 0.072 39.612 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.732 0.072 39.756 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.876 0.072 39.900 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.164 0.072 40.188 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.308 0.072 40.332 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.452 0.072 40.476 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.436 178.537 20.460 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.580 178.537 20.604 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.724 178.537 20.748 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 20.868 178.537 20.892 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.012 178.537 21.036 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.156 178.537 21.180 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.300 178.537 21.324 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.444 178.537 21.468 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.588 178.537 21.612 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.732 178.537 21.756 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 21.876 178.537 21.900 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.020 178.537 22.044 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.164 178.537 22.188 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.308 178.537 22.332 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.452 178.537 22.476 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.596 178.537 22.620 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.740 178.537 22.764 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 22.884 178.537 22.908 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.028 178.537 23.052 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.172 178.537 23.196 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.316 178.537 23.340 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.460 178.537 23.484 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.604 178.537 23.628 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.748 178.537 23.772 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 23.892 178.537 23.916 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.036 178.537 24.060 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.180 178.537 24.204 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.324 178.537 24.348 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.468 178.537 24.492 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.612 178.537 24.636 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.756 178.537 24.780 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 24.900 178.537 24.924 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.044 178.537 25.068 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.188 178.537 25.212 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.332 178.537 25.356 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.476 178.537 25.500 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.620 178.537 25.644 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.764 178.537 25.788 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 25.908 178.537 25.932 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.052 178.537 26.076 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.196 178.537 26.220 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.340 178.537 26.364 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.484 178.537 26.508 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.628 178.537 26.652 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.772 178.537 26.796 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 26.916 178.537 26.940 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.060 178.537 27.084 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.204 178.537 27.228 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.348 178.537 27.372 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.492 178.537 27.516 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.636 178.537 27.660 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.780 178.537 27.804 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 27.924 178.537 27.948 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.068 178.537 28.092 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.212 178.537 28.236 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.356 178.537 28.380 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.500 178.537 28.524 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.644 178.537 28.668 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.788 178.537 28.812 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 28.932 178.537 28.956 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.076 178.537 29.100 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.220 178.537 29.244 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.364 178.537 29.388 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.508 178.537 29.532 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.652 178.537 29.676 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.796 178.537 29.820 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 29.940 178.537 29.964 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.084 178.537 30.108 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.228 178.537 30.252 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.372 178.537 30.396 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.516 178.537 30.540 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.660 178.537 30.684 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.804 178.537 30.828 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 30.948 178.537 30.972 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.092 178.537 31.116 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.236 178.537 31.260 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.380 178.537 31.404 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.524 178.537 31.548 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.668 178.537 31.692 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.812 178.537 31.836 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 31.956 178.537 31.980 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.100 178.537 32.124 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.244 178.537 32.268 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.388 178.537 32.412 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.532 178.537 32.556 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.676 178.537 32.700 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.820 178.537 32.844 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 32.964 178.537 32.988 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.108 178.537 33.132 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.252 178.537 33.276 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.396 178.537 33.420 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.540 178.537 33.564 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.684 178.537 33.708 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.828 178.537 33.852 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 33.972 178.537 33.996 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.116 178.537 34.140 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.260 178.537 34.284 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.404 178.537 34.428 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.548 178.537 34.572 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.692 178.537 34.716 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.836 178.537 34.860 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 34.980 178.537 35.004 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.124 178.537 35.148 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.268 178.537 35.292 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.412 178.537 35.436 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.556 178.537 35.580 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.700 178.537 35.724 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.844 178.537 35.868 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 35.988 178.537 36.012 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.132 178.537 36.156 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.276 178.537 36.300 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.420 178.537 36.444 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.564 178.537 36.588 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.708 178.537 36.732 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.852 178.537 36.876 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 36.996 178.537 37.020 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 37.140 178.537 37.164 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 37.284 178.537 37.308 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 37.428 178.537 37.452 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 37.572 178.537 37.596 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 37.716 178.537 37.740 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 37.860 178.537 37.884 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.004 178.537 38.028 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.148 178.537 38.172 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.292 178.537 38.316 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.436 178.537 38.460 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.580 178.537 38.604 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.724 178.537 38.748 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 38.868 178.537 38.892 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.012 178.537 39.036 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.156 178.537 39.180 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.300 178.537 39.324 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.444 178.537 39.468 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.588 178.537 39.612 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.732 178.537 39.756 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 39.876 178.537 39.900 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 40.020 178.537 40.044 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 40.164 178.537 40.188 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 40.308 178.537 40.332 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 40.452 178.537 40.476 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[287] + PIN w0_wd_in[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[288] + PIN w0_wd_in[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[289] + PIN w0_wd_in[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[290] + PIN w0_wd_in[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[291] + PIN w0_wd_in[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[292] + PIN w0_wd_in[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[293] + PIN w0_wd_in[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[294] + PIN w0_wd_in[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[295] + PIN w0_wd_in[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[296] + PIN w0_wd_in[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[297] + PIN w0_wd_in[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[298] + PIN w0_wd_in[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[299] + PIN w0_wd_in[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[300] + PIN w0_wd_in[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[301] + PIN w0_wd_in[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[302] + PIN w0_wd_in[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[303] + PIN w0_wd_in[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[304] + PIN w0_wd_in[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[305] + PIN w0_wd_in[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[306] + PIN w0_wd_in[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[307] + PIN w0_wd_in[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[308] + PIN w0_wd_in[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[309] + PIN w0_wd_in[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[310] + PIN w0_wd_in[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[311] + PIN w0_wd_in[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[312] + PIN w0_wd_in[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[313] + PIN w0_wd_in[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[314] + PIN w0_wd_in[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[315] + PIN w0_wd_in[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[316] + PIN w0_wd_in[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[317] + PIN w0_wd_in[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[318] + PIN w0_wd_in[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[319] + PIN w0_wd_in[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[320] + PIN w0_wd_in[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[321] + PIN w0_wd_in[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[322] + PIN w0_wd_in[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[323] + PIN w0_wd_in[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[324] + PIN w0_wd_in[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[325] + PIN w0_wd_in[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[326] + PIN w0_wd_in[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[327] + PIN w0_wd_in[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[328] + PIN w0_wd_in[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[329] + PIN w0_wd_in[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[330] + PIN w0_wd_in[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[331] + PIN w0_wd_in[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[332] + PIN w0_wd_in[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[333] + PIN w0_wd_in[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[334] + PIN w0_wd_in[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[335] + PIN w0_wd_in[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[336] + PIN w0_wd_in[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[337] + PIN w0_wd_in[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[338] + PIN w0_wd_in[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[339] + PIN w0_wd_in[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[340] + PIN w0_wd_in[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[341] + PIN w0_wd_in[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[342] + PIN w0_wd_in[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[343] + PIN w0_wd_in[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[344] + PIN w0_wd_in[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[345] + PIN w0_wd_in[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[346] + PIN w0_wd_in[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[347] + PIN w0_wd_in[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[348] + PIN w0_wd_in[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[349] + PIN w0_wd_in[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[350] + PIN w0_wd_in[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[351] + PIN w0_wd_in[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[352] + PIN w0_wd_in[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[353] + PIN w0_wd_in[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[354] + PIN w0_wd_in[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[355] + PIN w0_wd_in[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[356] + PIN w0_wd_in[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[357] + PIN w0_wd_in[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[358] + PIN w0_wd_in[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[359] + PIN w0_wd_in[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[360] + PIN w0_wd_in[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[361] + PIN w0_wd_in[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[362] + PIN w0_wd_in[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[363] + PIN w0_wd_in[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[364] + PIN w0_wd_in[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[365] + PIN w0_wd_in[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[366] + PIN w0_wd_in[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[367] + PIN w0_wd_in[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[368] + PIN w0_wd_in[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[369] + PIN w0_wd_in[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[370] + PIN w0_wd_in[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[371] + PIN w0_wd_in[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[372] + PIN w0_wd_in[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[373] + PIN w0_wd_in[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[374] + PIN w0_wd_in[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[375] + PIN w0_wd_in[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[376] + PIN w0_wd_in[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[377] + PIN w0_wd_in[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[378] + PIN w0_wd_in[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[379] + PIN w0_wd_in[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[380] + PIN w0_wd_in[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[381] + PIN w0_wd_in[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[382] + PIN w0_wd_in[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[383] + PIN w0_wd_in[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[384] + PIN w0_wd_in[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[385] + PIN w0_wd_in[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[386] + PIN w0_wd_in[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[387] + PIN w0_wd_in[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[388] + PIN w0_wd_in[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[389] + PIN w0_wd_in[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[390] + PIN w0_wd_in[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[391] + PIN w0_wd_in[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[392] + PIN w0_wd_in[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[393] + PIN w0_wd_in[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[394] + PIN w0_wd_in[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[395] + PIN w0_wd_in[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[396] + PIN w0_wd_in[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[397] + PIN w0_wd_in[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[398] + PIN w0_wd_in[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[399] + PIN w0_wd_in[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[400] + PIN w0_wd_in[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[401] + PIN w0_wd_in[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[402] + PIN w0_wd_in[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[403] + PIN w0_wd_in[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[404] + PIN w0_wd_in[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[405] + PIN w0_wd_in[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[406] + PIN w0_wd_in[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[407] + PIN w0_wd_in[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[408] + PIN w0_wd_in[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[409] + PIN w0_wd_in[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[410] + PIN w0_wd_in[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[411] + PIN w0_wd_in[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[412] + PIN w0_wd_in[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[413] + PIN w0_wd_in[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[414] + PIN w0_wd_in[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[415] + PIN w0_wd_in[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[416] + PIN w0_wd_in[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[417] + PIN w0_wd_in[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[418] + PIN w0_wd_in[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[419] + PIN w0_wd_in[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[420] + PIN w0_wd_in[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[421] + PIN w0_wd_in[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[422] + PIN w0_wd_in[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[423] + PIN w0_wd_in[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END w0_wd_in[424] + PIN w0_wd_in[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END w0_wd_in[425] + PIN w0_wd_in[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END w0_wd_in[426] + PIN w0_wd_in[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END w0_wd_in[427] + PIN w0_wd_in[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END w0_wd_in[428] + PIN w0_wd_in[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END w0_wd_in[429] + PIN w0_wd_in[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END w0_wd_in[430] + PIN w0_wd_in[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END w0_wd_in[431] + PIN w0_wd_in[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END w0_wd_in[432] + PIN w0_wd_in[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END w0_wd_in[433] + PIN w0_wd_in[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END w0_wd_in[434] + PIN w0_wd_in[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END w0_wd_in[435] + PIN w0_wd_in[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END w0_wd_in[436] + PIN w0_wd_in[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END w0_wd_in[437] + PIN w0_wd_in[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END w0_wd_in[438] + PIN w0_wd_in[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END w0_wd_in[439] + PIN w0_wd_in[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END w0_wd_in[440] + PIN w0_wd_in[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END w0_wd_in[441] + PIN w0_wd_in[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END w0_wd_in[442] + PIN w0_wd_in[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END w0_wd_in[443] + PIN w0_wd_in[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END w0_wd_in[444] + PIN w0_wd_in[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END w0_wd_in[445] + PIN w0_wd_in[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END w0_wd_in[446] + PIN w0_wd_in[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END w0_wd_in[447] + PIN w0_wd_in[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END w0_wd_in[448] + PIN w0_wd_in[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END w0_wd_in[449] + PIN w0_wd_in[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END w0_wd_in[450] + PIN w0_wd_in[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END w0_wd_in[451] + PIN w0_wd_in[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END w0_wd_in[452] + PIN w0_wd_in[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END w0_wd_in[453] + PIN w0_wd_in[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END w0_wd_in[454] + PIN w0_wd_in[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END w0_wd_in[455] + PIN w0_wd_in[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END w0_wd_in[456] + PIN w0_wd_in[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END w0_wd_in[457] + PIN w0_wd_in[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END w0_wd_in[458] + PIN w0_wd_in[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END w0_wd_in[459] + PIN w0_wd_in[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END w0_wd_in[460] + PIN w0_wd_in[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END w0_wd_in[461] + PIN w0_wd_in[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END w0_wd_in[462] + PIN w0_wd_in[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END w0_wd_in[463] + PIN w0_wd_in[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END w0_wd_in[464] + PIN w0_wd_in[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END w0_wd_in[465] + PIN w0_wd_in[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END w0_wd_in[466] + PIN w0_wd_in[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END w0_wd_in[467] + PIN w0_wd_in[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END w0_wd_in[468] + PIN w0_wd_in[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END w0_wd_in[469] + PIN w0_wd_in[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END w0_wd_in[470] + PIN w0_wd_in[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END w0_wd_in[471] + PIN w0_wd_in[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END w0_wd_in[472] + PIN w0_wd_in[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END w0_wd_in[473] + PIN w0_wd_in[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END w0_wd_in[474] + PIN w0_wd_in[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END w0_wd_in[475] + PIN w0_wd_in[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END w0_wd_in[476] + PIN w0_wd_in[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END w0_wd_in[477] + PIN w0_wd_in[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END w0_wd_in[478] + PIN w0_wd_in[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END w0_wd_in[479] + PIN w0_wd_in[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END w0_wd_in[480] + PIN w0_wd_in[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END w0_wd_in[481] + PIN w0_wd_in[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END w0_wd_in[482] + PIN w0_wd_in[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END w0_wd_in[483] + PIN w0_wd_in[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END w0_wd_in[484] + PIN w0_wd_in[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END w0_wd_in[485] + PIN w0_wd_in[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END w0_wd_in[486] + PIN w0_wd_in[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END w0_wd_in[487] + PIN w0_wd_in[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END w0_wd_in[488] + PIN w0_wd_in[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END w0_wd_in[489] + PIN w0_wd_in[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END w0_wd_in[490] + PIN w0_wd_in[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END w0_wd_in[491] + PIN w0_wd_in[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END w0_wd_in[492] + PIN w0_wd_in[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END w0_wd_in[493] + PIN w0_wd_in[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END w0_wd_in[494] + PIN w0_wd_in[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END w0_wd_in[495] + PIN w0_wd_in[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END w0_wd_in[496] + PIN w0_wd_in[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END w0_wd_in[497] + PIN w0_wd_in[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END w0_wd_in[498] + PIN w0_wd_in[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END w0_wd_in[499] + PIN w0_wd_in[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END w0_wd_in[500] + PIN w0_wd_in[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END w0_wd_in[501] + PIN w0_wd_in[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END w0_wd_in[502] + PIN w0_wd_in[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END w0_wd_in[503] + PIN w0_wd_in[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END w0_wd_in[504] + PIN w0_wd_in[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END w0_wd_in[505] + PIN w0_wd_in[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END w0_wd_in[506] + PIN w0_wd_in[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END w0_wd_in[507] + PIN w0_wd_in[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END w0_wd_in[508] + PIN w0_wd_in[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END w0_wd_in[509] + PIN w0_wd_in[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END w0_wd_in[510] + PIN w0_wd_in[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END w0_wd_in[511] + PIN w0_wd_in[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END w0_wd_in[512] + PIN w0_wd_in[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END w0_wd_in[513] + PIN w0_wd_in[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END w0_wd_in[514] + PIN w0_wd_in[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END w0_wd_in[515] + PIN w0_wd_in[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END w0_wd_in[516] + PIN w0_wd_in[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END w0_wd_in[517] + PIN w0_wd_in[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END w0_wd_in[518] + PIN w0_wd_in[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END w0_wd_in[519] + PIN w0_wd_in[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END w0_wd_in[520] + PIN w0_wd_in[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END w0_wd_in[521] + PIN w0_wd_in[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END w0_wd_in[522] + PIN w0_wd_in[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END w0_wd_in[523] + PIN w0_wd_in[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END w0_wd_in[524] + PIN w0_wd_in[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END w0_wd_in[525] + PIN w0_wd_in[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END w0_wd_in[526] + PIN w0_wd_in[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END w0_wd_in[527] + PIN w0_wd_in[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END w0_wd_in[528] + PIN w0_wd_in[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END w0_wd_in[529] + PIN w0_wd_in[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END w0_wd_in[530] + PIN w0_wd_in[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END w0_wd_in[531] + PIN w0_wd_in[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END w0_wd_in[532] + PIN w0_wd_in[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END w0_wd_in[533] + PIN w0_wd_in[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END w0_wd_in[534] + PIN w0_wd_in[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END w0_wd_in[535] + PIN w0_wd_in[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END w0_wd_in[536] + PIN w0_wd_in[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END w0_wd_in[537] + PIN w0_wd_in[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END w0_wd_in[538] + PIN w0_wd_in[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END w0_wd_in[539] + PIN w0_wd_in[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END w0_wd_in[540] + PIN w0_wd_in[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END w0_wd_in[541] + PIN w0_wd_in[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END w0_wd_in[542] + PIN w0_wd_in[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END w0_wd_in[543] + PIN w0_wd_in[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END w0_wd_in[544] + PIN w0_wd_in[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END w0_wd_in[545] + PIN w0_wd_in[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END w0_wd_in[546] + PIN w0_wd_in[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END w0_wd_in[547] + PIN w0_wd_in[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END w0_wd_in[548] + PIN w0_wd_in[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END w0_wd_in[549] + PIN w0_wd_in[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END w0_wd_in[550] + PIN w0_wd_in[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END w0_wd_in[551] + PIN w0_wd_in[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END w0_wd_in[552] + PIN w0_wd_in[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END w0_wd_in[553] + PIN w0_wd_in[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END w0_wd_in[554] + PIN w0_wd_in[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END w0_wd_in[555] + PIN w0_wd_in[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END w0_wd_in[556] + PIN w0_wd_in[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END w0_wd_in[557] + PIN w0_wd_in[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END w0_wd_in[558] + PIN w0_wd_in[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END w0_wd_in[559] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 0.000 83.169 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 0.000 83.457 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 0.000 84.033 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 0.000 84.321 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 0.000 84.609 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 0.000 84.897 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 0.000 85.473 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 0.000 85.761 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 0.000 86.049 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 0.000 86.337 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 0.000 86.913 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 0.000 87.201 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 0.000 87.489 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 0.000 87.777 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 0.000 88.353 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 0.000 88.641 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 0.000 88.929 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 0.000 89.217 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 0.000 89.793 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 0.000 90.081 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 0.000 90.369 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 0.000 90.657 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 0.000 91.233 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 0.000 91.521 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 0.000 91.809 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 0.000 92.097 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 0.000 92.385 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 0.000 92.673 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 0.000 92.961 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 0.000 93.249 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 0.000 93.537 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 0.000 93.825 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 0.000 94.113 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 0.000 94.401 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 0.000 94.689 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 0.000 94.977 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 0.000 95.265 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 0.000 95.553 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 0.000 95.841 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 0.000 96.129 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 0.000 96.417 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 0.000 96.705 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 0.000 96.993 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 0.000 97.281 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 0.000 97.569 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 0.000 97.857 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 0.000 98.145 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 0.000 98.433 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 0.000 98.721 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 0.000 99.009 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 0.000 99.297 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 0.000 99.585 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 0.000 99.873 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 0.000 100.161 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 0.000 100.449 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 0.000 100.737 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 0.000 101.025 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 0.000 101.313 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 0.000 101.601 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 0.000 101.889 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 0.000 102.177 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 0.000 102.465 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 0.000 102.753 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 0.000 103.041 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 0.000 103.329 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 0.000 103.617 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 0.000 103.905 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 0.000 104.193 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 0.000 104.481 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 0.000 104.769 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 0.000 105.057 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 0.000 105.345 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 0.000 105.633 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 0.000 105.921 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 0.000 106.209 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 0.000 106.497 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 0.000 106.785 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 0.000 107.073 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 0.000 107.361 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 0.000 107.649 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 0.000 107.937 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 0.000 108.225 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 0.000 108.513 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 0.000 108.801 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 0.000 109.089 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 0.000 109.377 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 0.000 109.665 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 0.000 109.953 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 0.000 110.241 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 0.000 110.529 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 0.000 110.817 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 0.000 111.105 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 0.000 111.393 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 0.000 111.681 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 0.000 111.969 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 0.000 112.257 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 0.000 112.545 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 0.000 112.833 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 0.000 113.121 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 0.000 113.409 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 0.000 113.697 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 0.000 113.985 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 0.000 114.273 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 0.000 114.561 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 0.000 114.849 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 0.000 115.137 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 0.000 115.425 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 0.000 115.713 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 0.000 116.001 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 0.000 116.289 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 0.000 116.577 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 0.000 116.865 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 0.000 117.153 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 0.000 117.441 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 0.000 117.729 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 0.000 118.017 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 0.000 118.305 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 0.000 118.593 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 0.000 118.881 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 0.000 119.169 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 0.000 119.457 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 0.000 119.745 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 0.000 120.033 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 0.000 120.321 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 0.000 120.609 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 0.000 120.897 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 0.000 121.185 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 0.000 121.473 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 0.000 121.761 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 0.000 122.049 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 0.000 122.337 0.054 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 0.000 122.625 0.054 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 0.000 122.913 0.054 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 0.000 123.201 0.054 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 0.000 123.489 0.054 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 0.000 123.777 0.054 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 0.000 124.065 0.054 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 0.000 124.353 0.054 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 0.000 124.641 0.054 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 0.000 124.929 0.054 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 0.000 125.217 0.054 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 0.000 125.505 0.054 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 0.000 125.793 0.054 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 0.000 126.081 0.054 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 0.000 126.369 0.054 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 0.000 126.657 0.054 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 0.000 126.945 0.054 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 0.000 127.233 0.054 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 0.000 127.521 0.054 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 0.000 127.809 0.054 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 0.000 128.097 0.054 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 0.000 128.385 0.054 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 0.000 128.673 0.054 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 0.000 128.961 0.054 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 0.000 129.249 0.054 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 0.000 129.537 0.054 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 0.000 129.825 0.054 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 0.000 130.113 0.054 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 0.000 130.401 0.054 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 0.000 130.689 0.054 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 0.000 130.977 0.054 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 0.000 131.265 0.054 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 0.000 131.553 0.054 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 0.000 131.841 0.054 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 0.000 132.129 0.054 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 0.000 132.417 0.054 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 0.000 132.705 0.054 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 0.000 132.993 0.054 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 0.000 133.281 0.054 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 0.000 133.569 0.054 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 0.000 133.857 0.054 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 0.000 134.145 0.054 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 0.000 134.433 0.054 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 0.000 134.721 0.054 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 0.000 135.009 0.054 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 0.000 135.297 0.054 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 0.000 135.585 0.054 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 0.000 135.873 0.054 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 0.000 136.161 0.054 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 0.000 136.449 0.054 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 0.000 136.737 0.054 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 0.000 137.025 0.054 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 0.000 137.313 0.054 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 0.000 137.601 0.054 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 0.000 137.889 0.054 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 0.000 138.177 0.054 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 0.000 138.465 0.054 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 0.000 138.753 0.054 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 0.000 139.041 0.054 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 0.000 139.329 0.054 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 0.000 139.617 0.054 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 0.000 139.905 0.054 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 0.000 140.193 0.054 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 0.000 140.481 0.054 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 0.000 140.769 0.054 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 0.000 141.057 0.054 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 0.000 141.345 0.054 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 0.000 141.633 0.054 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 0.000 141.921 0.054 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 0.000 142.209 0.054 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 0.000 142.497 0.054 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 0.000 142.785 0.054 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 0.000 143.073 0.054 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 0.000 143.361 0.054 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 0.000 143.649 0.054 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 0.000 143.937 0.054 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 0.000 144.225 0.054 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 0.000 144.513 0.054 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 0.000 144.801 0.054 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 0.000 145.089 0.054 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 0.000 145.377 0.054 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 0.000 145.665 0.054 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 0.000 145.953 0.054 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 0.000 146.241 0.054 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 0.000 146.529 0.054 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 0.000 146.817 0.054 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 0.000 147.105 0.054 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 0.000 147.393 0.054 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 0.000 147.681 0.054 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 0.000 147.969 0.054 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 0.000 148.257 0.054 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 0.000 148.545 0.054 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 0.000 148.833 0.054 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 0.000 149.121 0.054 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 0.000 149.409 0.054 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 0.000 149.697 0.054 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 0.000 149.985 0.054 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 0.000 150.273 0.054 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 0.000 150.561 0.054 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 0.000 150.849 0.054 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 0.000 151.137 0.054 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 0.000 151.425 0.054 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 0.000 151.713 0.054 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 0.000 152.001 0.054 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 0.000 152.289 0.054 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 0.000 152.577 0.054 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 0.000 152.865 0.054 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 0.000 153.153 0.054 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 0.000 153.441 0.054 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 0.000 153.729 0.054 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 0.000 154.017 0.054 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 0.000 154.305 0.054 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 0.000 154.593 0.054 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 0.000 154.881 0.054 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 0.000 155.169 0.054 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 0.000 155.457 0.054 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 0.000 155.745 0.054 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 0.000 156.033 0.054 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 0.000 156.321 0.054 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 0.000 156.609 0.054 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 0.000 156.897 0.054 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 0.000 157.185 0.054 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 0.000 157.473 0.054 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 0.000 157.761 0.054 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 0.000 158.049 0.054 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 0.000 158.337 0.054 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 0.000 158.625 0.054 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 0.000 158.913 0.054 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 0.000 159.201 0.054 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 0.000 159.489 0.054 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 0.000 159.777 0.054 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 0.000 160.065 0.054 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 0.000 160.353 0.054 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 0.000 160.641 0.054 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 0.000 160.929 0.054 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 0.000 161.217 0.054 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 50.249 80.865 50.303 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 50.249 81.153 50.303 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 50.249 81.441 50.303 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 50.249 81.729 50.303 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 50.249 82.017 50.303 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 50.249 82.305 50.303 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 50.249 82.593 50.303 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 50.249 82.881 50.303 ; + END + END r0_rd_out[287] + PIN r0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 50.249 83.169 50.303 ; + END + END r0_rd_out[288] + PIN r0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 50.249 83.457 50.303 ; + END + END r0_rd_out[289] + PIN r0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 50.249 83.745 50.303 ; + END + END r0_rd_out[290] + PIN r0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 50.249 84.033 50.303 ; + END + END r0_rd_out[291] + PIN r0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 50.249 84.321 50.303 ; + END + END r0_rd_out[292] + PIN r0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 50.249 84.609 50.303 ; + END + END r0_rd_out[293] + PIN r0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 50.249 84.897 50.303 ; + END + END r0_rd_out[294] + PIN r0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 50.249 85.185 50.303 ; + END + END r0_rd_out[295] + PIN r0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 50.249 85.473 50.303 ; + END + END r0_rd_out[296] + PIN r0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 50.249 85.761 50.303 ; + END + END r0_rd_out[297] + PIN r0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 50.249 86.049 50.303 ; + END + END r0_rd_out[298] + PIN r0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 50.249 86.337 50.303 ; + END + END r0_rd_out[299] + PIN r0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 50.249 86.625 50.303 ; + END + END r0_rd_out[300] + PIN r0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 50.249 86.913 50.303 ; + END + END r0_rd_out[301] + PIN r0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 50.249 87.201 50.303 ; + END + END r0_rd_out[302] + PIN r0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 50.249 87.489 50.303 ; + END + END r0_rd_out[303] + PIN r0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 50.249 87.777 50.303 ; + END + END r0_rd_out[304] + PIN r0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 50.249 88.065 50.303 ; + END + END r0_rd_out[305] + PIN r0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 50.249 88.353 50.303 ; + END + END r0_rd_out[306] + PIN r0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 50.249 88.641 50.303 ; + END + END r0_rd_out[307] + PIN r0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 50.249 88.929 50.303 ; + END + END r0_rd_out[308] + PIN r0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 50.249 89.217 50.303 ; + END + END r0_rd_out[309] + PIN r0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 50.249 89.505 50.303 ; + END + END r0_rd_out[310] + PIN r0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 50.249 89.793 50.303 ; + END + END r0_rd_out[311] + PIN r0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 50.249 90.081 50.303 ; + END + END r0_rd_out[312] + PIN r0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 50.249 90.369 50.303 ; + END + END r0_rd_out[313] + PIN r0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 50.249 90.657 50.303 ; + END + END r0_rd_out[314] + PIN r0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 50.249 90.945 50.303 ; + END + END r0_rd_out[315] + PIN r0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 50.249 91.233 50.303 ; + END + END r0_rd_out[316] + PIN r0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 50.249 91.521 50.303 ; + END + END r0_rd_out[317] + PIN r0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 50.249 91.809 50.303 ; + END + END r0_rd_out[318] + PIN r0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 50.249 92.097 50.303 ; + END + END r0_rd_out[319] + PIN r0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 50.249 92.385 50.303 ; + END + END r0_rd_out[320] + PIN r0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 50.249 92.673 50.303 ; + END + END r0_rd_out[321] + PIN r0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 50.249 92.961 50.303 ; + END + END r0_rd_out[322] + PIN r0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 50.249 93.249 50.303 ; + END + END r0_rd_out[323] + PIN r0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 50.249 93.537 50.303 ; + END + END r0_rd_out[324] + PIN r0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 50.249 93.825 50.303 ; + END + END r0_rd_out[325] + PIN r0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 50.249 94.113 50.303 ; + END + END r0_rd_out[326] + PIN r0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 50.249 94.401 50.303 ; + END + END r0_rd_out[327] + PIN r0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 50.249 94.689 50.303 ; + END + END r0_rd_out[328] + PIN r0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 50.249 94.977 50.303 ; + END + END r0_rd_out[329] + PIN r0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 50.249 95.265 50.303 ; + END + END r0_rd_out[330] + PIN r0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 50.249 95.553 50.303 ; + END + END r0_rd_out[331] + PIN r0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 50.249 95.841 50.303 ; + END + END r0_rd_out[332] + PIN r0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 50.249 96.129 50.303 ; + END + END r0_rd_out[333] + PIN r0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 50.249 96.417 50.303 ; + END + END r0_rd_out[334] + PIN r0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 50.249 96.705 50.303 ; + END + END r0_rd_out[335] + PIN r0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 50.249 96.993 50.303 ; + END + END r0_rd_out[336] + PIN r0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 50.249 97.281 50.303 ; + END + END r0_rd_out[337] + PIN r0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 50.249 97.569 50.303 ; + END + END r0_rd_out[338] + PIN r0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 50.249 97.857 50.303 ; + END + END r0_rd_out[339] + PIN r0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 50.249 98.145 50.303 ; + END + END r0_rd_out[340] + PIN r0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 50.249 98.433 50.303 ; + END + END r0_rd_out[341] + PIN r0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 50.249 98.721 50.303 ; + END + END r0_rd_out[342] + PIN r0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 50.249 99.009 50.303 ; + END + END r0_rd_out[343] + PIN r0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 50.249 99.297 50.303 ; + END + END r0_rd_out[344] + PIN r0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 50.249 99.585 50.303 ; + END + END r0_rd_out[345] + PIN r0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 50.249 99.873 50.303 ; + END + END r0_rd_out[346] + PIN r0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 50.249 100.161 50.303 ; + END + END r0_rd_out[347] + PIN r0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 50.249 100.449 50.303 ; + END + END r0_rd_out[348] + PIN r0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 50.249 100.737 50.303 ; + END + END r0_rd_out[349] + PIN r0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 50.249 101.025 50.303 ; + END + END r0_rd_out[350] + PIN r0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 50.249 101.313 50.303 ; + END + END r0_rd_out[351] + PIN r0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 50.249 101.601 50.303 ; + END + END r0_rd_out[352] + PIN r0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 50.249 101.889 50.303 ; + END + END r0_rd_out[353] + PIN r0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 50.249 102.177 50.303 ; + END + END r0_rd_out[354] + PIN r0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 50.249 102.465 50.303 ; + END + END r0_rd_out[355] + PIN r0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 50.249 102.753 50.303 ; + END + END r0_rd_out[356] + PIN r0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 50.249 103.041 50.303 ; + END + END r0_rd_out[357] + PIN r0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 50.249 103.329 50.303 ; + END + END r0_rd_out[358] + PIN r0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 50.249 103.617 50.303 ; + END + END r0_rd_out[359] + PIN r0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 50.249 103.905 50.303 ; + END + END r0_rd_out[360] + PIN r0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 50.249 104.193 50.303 ; + END + END r0_rd_out[361] + PIN r0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 50.249 104.481 50.303 ; + END + END r0_rd_out[362] + PIN r0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 50.249 104.769 50.303 ; + END + END r0_rd_out[363] + PIN r0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 50.249 105.057 50.303 ; + END + END r0_rd_out[364] + PIN r0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 50.249 105.345 50.303 ; + END + END r0_rd_out[365] + PIN r0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 50.249 105.633 50.303 ; + END + END r0_rd_out[366] + PIN r0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 50.249 105.921 50.303 ; + END + END r0_rd_out[367] + PIN r0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 50.249 106.209 50.303 ; + END + END r0_rd_out[368] + PIN r0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 50.249 106.497 50.303 ; + END + END r0_rd_out[369] + PIN r0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 50.249 106.785 50.303 ; + END + END r0_rd_out[370] + PIN r0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 50.249 107.073 50.303 ; + END + END r0_rd_out[371] + PIN r0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 50.249 107.361 50.303 ; + END + END r0_rd_out[372] + PIN r0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 50.249 107.649 50.303 ; + END + END r0_rd_out[373] + PIN r0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 50.249 107.937 50.303 ; + END + END r0_rd_out[374] + PIN r0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 50.249 108.225 50.303 ; + END + END r0_rd_out[375] + PIN r0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 50.249 108.513 50.303 ; + END + END r0_rd_out[376] + PIN r0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 50.249 108.801 50.303 ; + END + END r0_rd_out[377] + PIN r0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 50.249 109.089 50.303 ; + END + END r0_rd_out[378] + PIN r0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 50.249 109.377 50.303 ; + END + END r0_rd_out[379] + PIN r0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 50.249 109.665 50.303 ; + END + END r0_rd_out[380] + PIN r0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 50.249 109.953 50.303 ; + END + END r0_rd_out[381] + PIN r0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 50.249 110.241 50.303 ; + END + END r0_rd_out[382] + PIN r0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 50.249 110.529 50.303 ; + END + END r0_rd_out[383] + PIN r0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 50.249 110.817 50.303 ; + END + END r0_rd_out[384] + PIN r0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 50.249 111.105 50.303 ; + END + END r0_rd_out[385] + PIN r0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 50.249 111.393 50.303 ; + END + END r0_rd_out[386] + PIN r0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 50.249 111.681 50.303 ; + END + END r0_rd_out[387] + PIN r0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 50.249 111.969 50.303 ; + END + END r0_rd_out[388] + PIN r0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 50.249 112.257 50.303 ; + END + END r0_rd_out[389] + PIN r0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 50.249 112.545 50.303 ; + END + END r0_rd_out[390] + PIN r0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 50.249 112.833 50.303 ; + END + END r0_rd_out[391] + PIN r0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 50.249 113.121 50.303 ; + END + END r0_rd_out[392] + PIN r0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 50.249 113.409 50.303 ; + END + END r0_rd_out[393] + PIN r0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 50.249 113.697 50.303 ; + END + END r0_rd_out[394] + PIN r0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 50.249 113.985 50.303 ; + END + END r0_rd_out[395] + PIN r0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 50.249 114.273 50.303 ; + END + END r0_rd_out[396] + PIN r0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 50.249 114.561 50.303 ; + END + END r0_rd_out[397] + PIN r0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 50.249 114.849 50.303 ; + END + END r0_rd_out[398] + PIN r0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 50.249 115.137 50.303 ; + END + END r0_rd_out[399] + PIN r0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 50.249 115.425 50.303 ; + END + END r0_rd_out[400] + PIN r0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 50.249 115.713 50.303 ; + END + END r0_rd_out[401] + PIN r0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 50.249 116.001 50.303 ; + END + END r0_rd_out[402] + PIN r0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 50.249 116.289 50.303 ; + END + END r0_rd_out[403] + PIN r0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 50.249 116.577 50.303 ; + END + END r0_rd_out[404] + PIN r0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 50.249 116.865 50.303 ; + END + END r0_rd_out[405] + PIN r0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 50.249 117.153 50.303 ; + END + END r0_rd_out[406] + PIN r0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 50.249 117.441 50.303 ; + END + END r0_rd_out[407] + PIN r0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 50.249 117.729 50.303 ; + END + END r0_rd_out[408] + PIN r0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 50.249 118.017 50.303 ; + END + END r0_rd_out[409] + PIN r0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 50.249 118.305 50.303 ; + END + END r0_rd_out[410] + PIN r0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 50.249 118.593 50.303 ; + END + END r0_rd_out[411] + PIN r0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 50.249 118.881 50.303 ; + END + END r0_rd_out[412] + PIN r0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 50.249 119.169 50.303 ; + END + END r0_rd_out[413] + PIN r0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 50.249 119.457 50.303 ; + END + END r0_rd_out[414] + PIN r0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 50.249 119.745 50.303 ; + END + END r0_rd_out[415] + PIN r0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 50.249 120.033 50.303 ; + END + END r0_rd_out[416] + PIN r0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 50.249 120.321 50.303 ; + END + END r0_rd_out[417] + PIN r0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 50.249 120.609 50.303 ; + END + END r0_rd_out[418] + PIN r0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 50.249 120.897 50.303 ; + END + END r0_rd_out[419] + PIN r0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 50.249 121.185 50.303 ; + END + END r0_rd_out[420] + PIN r0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 50.249 121.473 50.303 ; + END + END r0_rd_out[421] + PIN r0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 50.249 121.761 50.303 ; + END + END r0_rd_out[422] + PIN r0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 50.249 122.049 50.303 ; + END + END r0_rd_out[423] + PIN r0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 50.249 122.337 50.303 ; + END + END r0_rd_out[424] + PIN r0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 50.249 122.625 50.303 ; + END + END r0_rd_out[425] + PIN r0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 50.249 122.913 50.303 ; + END + END r0_rd_out[426] + PIN r0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 50.249 123.201 50.303 ; + END + END r0_rd_out[427] + PIN r0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 50.249 123.489 50.303 ; + END + END r0_rd_out[428] + PIN r0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 50.249 123.777 50.303 ; + END + END r0_rd_out[429] + PIN r0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 50.249 124.065 50.303 ; + END + END r0_rd_out[430] + PIN r0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 50.249 124.353 50.303 ; + END + END r0_rd_out[431] + PIN r0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 50.249 124.641 50.303 ; + END + END r0_rd_out[432] + PIN r0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 50.249 124.929 50.303 ; + END + END r0_rd_out[433] + PIN r0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 50.249 125.217 50.303 ; + END + END r0_rd_out[434] + PIN r0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 50.249 125.505 50.303 ; + END + END r0_rd_out[435] + PIN r0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 50.249 125.793 50.303 ; + END + END r0_rd_out[436] + PIN r0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 50.249 126.081 50.303 ; + END + END r0_rd_out[437] + PIN r0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 50.249 126.369 50.303 ; + END + END r0_rd_out[438] + PIN r0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 50.249 126.657 50.303 ; + END + END r0_rd_out[439] + PIN r0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 50.249 126.945 50.303 ; + END + END r0_rd_out[440] + PIN r0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 50.249 127.233 50.303 ; + END + END r0_rd_out[441] + PIN r0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 50.249 127.521 50.303 ; + END + END r0_rd_out[442] + PIN r0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 50.249 127.809 50.303 ; + END + END r0_rd_out[443] + PIN r0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 50.249 128.097 50.303 ; + END + END r0_rd_out[444] + PIN r0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 50.249 128.385 50.303 ; + END + END r0_rd_out[445] + PIN r0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 50.249 128.673 50.303 ; + END + END r0_rd_out[446] + PIN r0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 50.249 128.961 50.303 ; + END + END r0_rd_out[447] + PIN r0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 50.249 129.249 50.303 ; + END + END r0_rd_out[448] + PIN r0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 50.249 129.537 50.303 ; + END + END r0_rd_out[449] + PIN r0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 50.249 129.825 50.303 ; + END + END r0_rd_out[450] + PIN r0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 50.249 130.113 50.303 ; + END + END r0_rd_out[451] + PIN r0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 50.249 130.401 50.303 ; + END + END r0_rd_out[452] + PIN r0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 50.249 130.689 50.303 ; + END + END r0_rd_out[453] + PIN r0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 50.249 130.977 50.303 ; + END + END r0_rd_out[454] + PIN r0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 50.249 131.265 50.303 ; + END + END r0_rd_out[455] + PIN r0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 50.249 131.553 50.303 ; + END + END r0_rd_out[456] + PIN r0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 50.249 131.841 50.303 ; + END + END r0_rd_out[457] + PIN r0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 50.249 132.129 50.303 ; + END + END r0_rd_out[458] + PIN r0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 50.249 132.417 50.303 ; + END + END r0_rd_out[459] + PIN r0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 50.249 132.705 50.303 ; + END + END r0_rd_out[460] + PIN r0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 50.249 132.993 50.303 ; + END + END r0_rd_out[461] + PIN r0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 50.249 133.281 50.303 ; + END + END r0_rd_out[462] + PIN r0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 50.249 133.569 50.303 ; + END + END r0_rd_out[463] + PIN r0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 50.249 133.857 50.303 ; + END + END r0_rd_out[464] + PIN r0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 50.249 134.145 50.303 ; + END + END r0_rd_out[465] + PIN r0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 50.249 134.433 50.303 ; + END + END r0_rd_out[466] + PIN r0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 50.249 134.721 50.303 ; + END + END r0_rd_out[467] + PIN r0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 50.249 135.009 50.303 ; + END + END r0_rd_out[468] + PIN r0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 50.249 135.297 50.303 ; + END + END r0_rd_out[469] + PIN r0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 50.249 135.585 50.303 ; + END + END r0_rd_out[470] + PIN r0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 50.249 135.873 50.303 ; + END + END r0_rd_out[471] + PIN r0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 50.249 136.161 50.303 ; + END + END r0_rd_out[472] + PIN r0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 50.249 136.449 50.303 ; + END + END r0_rd_out[473] + PIN r0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 50.249 136.737 50.303 ; + END + END r0_rd_out[474] + PIN r0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 50.249 137.025 50.303 ; + END + END r0_rd_out[475] + PIN r0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 50.249 137.313 50.303 ; + END + END r0_rd_out[476] + PIN r0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 50.249 137.601 50.303 ; + END + END r0_rd_out[477] + PIN r0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 50.249 137.889 50.303 ; + END + END r0_rd_out[478] + PIN r0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 50.249 138.177 50.303 ; + END + END r0_rd_out[479] + PIN r0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 50.249 138.465 50.303 ; + END + END r0_rd_out[480] + PIN r0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 50.249 138.753 50.303 ; + END + END r0_rd_out[481] + PIN r0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 50.249 139.041 50.303 ; + END + END r0_rd_out[482] + PIN r0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 50.249 139.329 50.303 ; + END + END r0_rd_out[483] + PIN r0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 50.249 139.617 50.303 ; + END + END r0_rd_out[484] + PIN r0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 50.249 139.905 50.303 ; + END + END r0_rd_out[485] + PIN r0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 50.249 140.193 50.303 ; + END + END r0_rd_out[486] + PIN r0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 50.249 140.481 50.303 ; + END + END r0_rd_out[487] + PIN r0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 50.249 140.769 50.303 ; + END + END r0_rd_out[488] + PIN r0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 50.249 141.057 50.303 ; + END + END r0_rd_out[489] + PIN r0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 50.249 141.345 50.303 ; + END + END r0_rd_out[490] + PIN r0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 50.249 141.633 50.303 ; + END + END r0_rd_out[491] + PIN r0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 50.249 141.921 50.303 ; + END + END r0_rd_out[492] + PIN r0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 50.249 142.209 50.303 ; + END + END r0_rd_out[493] + PIN r0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 50.249 142.497 50.303 ; + END + END r0_rd_out[494] + PIN r0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 50.249 142.785 50.303 ; + END + END r0_rd_out[495] + PIN r0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 50.249 143.073 50.303 ; + END + END r0_rd_out[496] + PIN r0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 50.249 143.361 50.303 ; + END + END r0_rd_out[497] + PIN r0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 50.249 143.649 50.303 ; + END + END r0_rd_out[498] + PIN r0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 50.249 143.937 50.303 ; + END + END r0_rd_out[499] + PIN r0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 50.249 144.225 50.303 ; + END + END r0_rd_out[500] + PIN r0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 50.249 144.513 50.303 ; + END + END r0_rd_out[501] + PIN r0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 50.249 144.801 50.303 ; + END + END r0_rd_out[502] + PIN r0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 50.249 145.089 50.303 ; + END + END r0_rd_out[503] + PIN r0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 50.249 145.377 50.303 ; + END + END r0_rd_out[504] + PIN r0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 50.249 145.665 50.303 ; + END + END r0_rd_out[505] + PIN r0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 50.249 145.953 50.303 ; + END + END r0_rd_out[506] + PIN r0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 50.249 146.241 50.303 ; + END + END r0_rd_out[507] + PIN r0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 50.249 146.529 50.303 ; + END + END r0_rd_out[508] + PIN r0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 50.249 146.817 50.303 ; + END + END r0_rd_out[509] + PIN r0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 50.249 147.105 50.303 ; + END + END r0_rd_out[510] + PIN r0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 50.249 147.393 50.303 ; + END + END r0_rd_out[511] + PIN r0_rd_out[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 50.249 147.681 50.303 ; + END + END r0_rd_out[512] + PIN r0_rd_out[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 50.249 147.969 50.303 ; + END + END r0_rd_out[513] + PIN r0_rd_out[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 50.249 148.257 50.303 ; + END + END r0_rd_out[514] + PIN r0_rd_out[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 50.249 148.545 50.303 ; + END + END r0_rd_out[515] + PIN r0_rd_out[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 50.249 148.833 50.303 ; + END + END r0_rd_out[516] + PIN r0_rd_out[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 50.249 149.121 50.303 ; + END + END r0_rd_out[517] + PIN r0_rd_out[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 50.249 149.409 50.303 ; + END + END r0_rd_out[518] + PIN r0_rd_out[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 50.249 149.697 50.303 ; + END + END r0_rd_out[519] + PIN r0_rd_out[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 50.249 149.985 50.303 ; + END + END r0_rd_out[520] + PIN r0_rd_out[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 50.249 150.273 50.303 ; + END + END r0_rd_out[521] + PIN r0_rd_out[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 50.249 150.561 50.303 ; + END + END r0_rd_out[522] + PIN r0_rd_out[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 50.249 150.849 50.303 ; + END + END r0_rd_out[523] + PIN r0_rd_out[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 50.249 151.137 50.303 ; + END + END r0_rd_out[524] + PIN r0_rd_out[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 50.249 151.425 50.303 ; + END + END r0_rd_out[525] + PIN r0_rd_out[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 50.249 151.713 50.303 ; + END + END r0_rd_out[526] + PIN r0_rd_out[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 50.249 152.001 50.303 ; + END + END r0_rd_out[527] + PIN r0_rd_out[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 50.249 152.289 50.303 ; + END + END r0_rd_out[528] + PIN r0_rd_out[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 50.249 152.577 50.303 ; + END + END r0_rd_out[529] + PIN r0_rd_out[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 50.249 152.865 50.303 ; + END + END r0_rd_out[530] + PIN r0_rd_out[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 50.249 153.153 50.303 ; + END + END r0_rd_out[531] + PIN r0_rd_out[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 50.249 153.441 50.303 ; + END + END r0_rd_out[532] + PIN r0_rd_out[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 50.249 153.729 50.303 ; + END + END r0_rd_out[533] + PIN r0_rd_out[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 50.249 154.017 50.303 ; + END + END r0_rd_out[534] + PIN r0_rd_out[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 50.249 154.305 50.303 ; + END + END r0_rd_out[535] + PIN r0_rd_out[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 50.249 154.593 50.303 ; + END + END r0_rd_out[536] + PIN r0_rd_out[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 50.249 154.881 50.303 ; + END + END r0_rd_out[537] + PIN r0_rd_out[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 50.249 155.169 50.303 ; + END + END r0_rd_out[538] + PIN r0_rd_out[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 50.249 155.457 50.303 ; + END + END r0_rd_out[539] + PIN r0_rd_out[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 50.249 155.745 50.303 ; + END + END r0_rd_out[540] + PIN r0_rd_out[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 50.249 156.033 50.303 ; + END + END r0_rd_out[541] + PIN r0_rd_out[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 50.249 156.321 50.303 ; + END + END r0_rd_out[542] + PIN r0_rd_out[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 50.249 156.609 50.303 ; + END + END r0_rd_out[543] + PIN r0_rd_out[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 50.249 156.897 50.303 ; + END + END r0_rd_out[544] + PIN r0_rd_out[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 50.249 157.185 50.303 ; + END + END r0_rd_out[545] + PIN r0_rd_out[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 50.249 157.473 50.303 ; + END + END r0_rd_out[546] + PIN r0_rd_out[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 50.249 157.761 50.303 ; + END + END r0_rd_out[547] + PIN r0_rd_out[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 50.249 158.049 50.303 ; + END + END r0_rd_out[548] + PIN r0_rd_out[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 50.249 158.337 50.303 ; + END + END r0_rd_out[549] + PIN r0_rd_out[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 50.249 158.625 50.303 ; + END + END r0_rd_out[550] + PIN r0_rd_out[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 50.249 158.913 50.303 ; + END + END r0_rd_out[551] + PIN r0_rd_out[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 50.249 159.201 50.303 ; + END + END r0_rd_out[552] + PIN r0_rd_out[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 50.249 159.489 50.303 ; + END + END r0_rd_out[553] + PIN r0_rd_out[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 50.249 159.777 50.303 ; + END + END r0_rd_out[554] + PIN r0_rd_out[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 50.249 160.065 50.303 ; + END + END r0_rd_out[555] + PIN r0_rd_out[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 50.249 160.353 50.303 ; + END + END r0_rd_out[556] + PIN r0_rd_out[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 50.249 160.641 50.303 ; + END + END r0_rd_out[557] + PIN r0_rd_out[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 50.249 160.929 50.303 ; + END + END r0_rd_out[558] + PIN r0_rd_out[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 50.249 161.217 50.303 ; + END + END r0_rd_out[559] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 40.596 178.537 40.620 ; + END + END w0_addr_in[1] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.740 0.072 40.764 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 178.465 40.740 178.537 40.764 ; + END + END r0_addr_in[1] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 50.249 161.505 50.303 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 50.249 161.793 50.303 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 50.249 162.081 50.303 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 50.249 162.369 50.303 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 50.249 162.657 50.303 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 178.321 0.336 ; + RECT 0.216 1.008 178.321 1.104 ; + RECT 0.216 1.776 178.321 1.872 ; + RECT 0.216 2.544 178.321 2.640 ; + RECT 0.216 3.312 178.321 3.408 ; + RECT 0.216 4.080 178.321 4.176 ; + RECT 0.216 4.848 178.321 4.944 ; + RECT 0.216 5.616 178.321 5.712 ; + RECT 0.216 6.384 178.321 6.480 ; + RECT 0.216 7.152 178.321 7.248 ; + RECT 0.216 7.920 178.321 8.016 ; + RECT 0.216 8.688 178.321 8.784 ; + RECT 0.216 9.456 178.321 9.552 ; + RECT 0.216 10.224 178.321 10.320 ; + RECT 0.216 10.992 178.321 11.088 ; + RECT 0.216 11.760 178.321 11.856 ; + RECT 0.216 12.528 178.321 12.624 ; + RECT 0.216 13.296 178.321 13.392 ; + RECT 0.216 14.064 178.321 14.160 ; + RECT 0.216 14.832 178.321 14.928 ; + RECT 0.216 15.600 178.321 15.696 ; + RECT 0.216 16.368 178.321 16.464 ; + RECT 0.216 17.136 178.321 17.232 ; + RECT 0.216 17.904 178.321 18.000 ; + RECT 0.216 18.672 178.321 18.768 ; + RECT 0.216 19.440 178.321 19.536 ; + RECT 0.216 20.208 178.321 20.304 ; + RECT 0.216 20.976 178.321 21.072 ; + RECT 0.216 21.744 178.321 21.840 ; + RECT 0.216 22.512 178.321 22.608 ; + RECT 0.216 23.280 178.321 23.376 ; + RECT 0.216 24.048 178.321 24.144 ; + RECT 0.216 24.816 178.321 24.912 ; + RECT 0.216 25.584 178.321 25.680 ; + RECT 0.216 26.352 178.321 26.448 ; + RECT 0.216 27.120 178.321 27.216 ; + RECT 0.216 27.888 178.321 27.984 ; + RECT 0.216 28.656 178.321 28.752 ; + RECT 0.216 29.424 178.321 29.520 ; + RECT 0.216 30.192 178.321 30.288 ; + RECT 0.216 30.960 178.321 31.056 ; + RECT 0.216 31.728 178.321 31.824 ; + RECT 0.216 32.496 178.321 32.592 ; + RECT 0.216 33.264 178.321 33.360 ; + RECT 0.216 34.032 178.321 34.128 ; + RECT 0.216 34.800 178.321 34.896 ; + RECT 0.216 35.568 178.321 35.664 ; + RECT 0.216 36.336 178.321 36.432 ; + RECT 0.216 37.104 178.321 37.200 ; + RECT 0.216 37.872 178.321 37.968 ; + RECT 0.216 38.640 178.321 38.736 ; + RECT 0.216 39.408 178.321 39.504 ; + RECT 0.216 40.176 178.321 40.272 ; + RECT 0.216 40.944 178.321 41.040 ; + RECT 0.216 41.712 178.321 41.808 ; + RECT 0.216 42.480 178.321 42.576 ; + RECT 0.216 43.248 178.321 43.344 ; + RECT 0.216 44.016 178.321 44.112 ; + RECT 0.216 44.784 178.321 44.880 ; + RECT 0.216 45.552 178.321 45.648 ; + RECT 0.216 46.320 178.321 46.416 ; + RECT 0.216 47.088 178.321 47.184 ; + RECT 0.216 47.856 178.321 47.952 ; + RECT 0.216 48.624 178.321 48.720 ; + RECT 0.216 49.392 178.321 49.488 ; + RECT 0.216 50.160 178.321 50.256 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 178.321 0.336 ; + RECT 0.216 1.008 178.321 1.104 ; + RECT 0.216 1.776 178.321 1.872 ; + RECT 0.216 2.544 178.321 2.640 ; + RECT 0.216 3.312 178.321 3.408 ; + RECT 0.216 4.080 178.321 4.176 ; + RECT 0.216 4.848 178.321 4.944 ; + RECT 0.216 5.616 178.321 5.712 ; + RECT 0.216 6.384 178.321 6.480 ; + RECT 0.216 7.152 178.321 7.248 ; + RECT 0.216 7.920 178.321 8.016 ; + RECT 0.216 8.688 178.321 8.784 ; + RECT 0.216 9.456 178.321 9.552 ; + RECT 0.216 10.224 178.321 10.320 ; + RECT 0.216 10.992 178.321 11.088 ; + RECT 0.216 11.760 178.321 11.856 ; + RECT 0.216 12.528 178.321 12.624 ; + RECT 0.216 13.296 178.321 13.392 ; + RECT 0.216 14.064 178.321 14.160 ; + RECT 0.216 14.832 178.321 14.928 ; + RECT 0.216 15.600 178.321 15.696 ; + RECT 0.216 16.368 178.321 16.464 ; + RECT 0.216 17.136 178.321 17.232 ; + RECT 0.216 17.904 178.321 18.000 ; + RECT 0.216 18.672 178.321 18.768 ; + RECT 0.216 19.440 178.321 19.536 ; + RECT 0.216 20.208 178.321 20.304 ; + RECT 0.216 20.976 178.321 21.072 ; + RECT 0.216 21.744 178.321 21.840 ; + RECT 0.216 22.512 178.321 22.608 ; + RECT 0.216 23.280 178.321 23.376 ; + RECT 0.216 24.048 178.321 24.144 ; + RECT 0.216 24.816 178.321 24.912 ; + RECT 0.216 25.584 178.321 25.680 ; + RECT 0.216 26.352 178.321 26.448 ; + RECT 0.216 27.120 178.321 27.216 ; + RECT 0.216 27.888 178.321 27.984 ; + RECT 0.216 28.656 178.321 28.752 ; + RECT 0.216 29.424 178.321 29.520 ; + RECT 0.216 30.192 178.321 30.288 ; + RECT 0.216 30.960 178.321 31.056 ; + RECT 0.216 31.728 178.321 31.824 ; + RECT 0.216 32.496 178.321 32.592 ; + RECT 0.216 33.264 178.321 33.360 ; + RECT 0.216 34.032 178.321 34.128 ; + RECT 0.216 34.800 178.321 34.896 ; + RECT 0.216 35.568 178.321 35.664 ; + RECT 0.216 36.336 178.321 36.432 ; + RECT 0.216 37.104 178.321 37.200 ; + RECT 0.216 37.872 178.321 37.968 ; + RECT 0.216 38.640 178.321 38.736 ; + RECT 0.216 39.408 178.321 39.504 ; + RECT 0.216 40.176 178.321 40.272 ; + RECT 0.216 40.944 178.321 41.040 ; + RECT 0.216 41.712 178.321 41.808 ; + RECT 0.216 42.480 178.321 42.576 ; + RECT 0.216 43.248 178.321 43.344 ; + RECT 0.216 44.016 178.321 44.112 ; + RECT 0.216 44.784 178.321 44.880 ; + RECT 0.216 45.552 178.321 45.648 ; + RECT 0.216 46.320 178.321 46.416 ; + RECT 0.216 47.088 178.321 47.184 ; + RECT 0.216 47.856 178.321 47.952 ; + RECT 0.216 48.624 178.321 48.720 ; + RECT 0.216 49.392 178.321 49.488 ; + RECT 0.216 50.160 178.321 50.256 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 178.537 50.303 ; + LAYER M2 ; + RECT 0 0 178.537 50.303 ; + LAYER M3 ; + RECT 0 0 178.537 50.303 ; + LAYER M4 ; + RECT 0 0 178.537 50.303 ; + END +END fakeram_560x4_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_654x4_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_654x4_1r1w.lef new file mode 100644 index 0000000..c57dbf1 --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_654x4_1r1w.lef @@ -0,0 +1,17925 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_654x4_1r1w + FOREIGN fakeram_654x4_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 208.506 BY 58.627 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.420 0.072 0.444 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.564 0.072 0.588 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.708 0.072 0.732 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.996 0.072 1.020 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.140 0.072 1.164 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.284 0.072 1.308 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.572 0.072 1.596 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.716 0.072 1.740 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.860 0.072 1.884 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.148 0.072 2.172 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.292 0.072 2.316 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.436 0.072 2.460 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.724 0.072 2.748 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.868 0.072 2.892 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.012 0.072 3.036 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.300 0.072 3.324 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.444 0.072 3.468 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.588 0.072 3.612 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.876 0.072 3.900 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.020 0.072 4.044 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.164 0.072 4.188 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.452 0.072 4.476 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.596 0.072 4.620 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.740 0.072 4.764 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.028 0.072 5.052 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.172 0.072 5.196 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.316 0.072 5.340 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.604 0.072 5.628 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.748 0.072 5.772 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.892 0.072 5.916 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.180 0.072 6.204 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.324 0.072 6.348 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.468 0.072 6.492 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.756 0.072 6.780 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.900 0.072 6.924 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.044 0.072 7.068 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.332 0.072 7.356 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.476 0.072 7.500 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.620 0.072 7.644 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.908 0.072 7.932 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.052 0.072 8.076 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.196 0.072 8.220 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.484 0.072 8.508 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.628 0.072 8.652 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.772 0.072 8.796 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.060 0.072 9.084 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.204 0.072 9.228 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.348 0.072 9.372 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.492 0.072 9.516 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.636 0.072 9.660 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.780 0.072 9.804 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.924 0.072 9.948 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.068 0.072 10.092 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.212 0.072 10.236 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.356 0.072 10.380 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.500 0.072 10.524 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.644 0.072 10.668 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.788 0.072 10.812 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.932 0.072 10.956 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.076 0.072 11.100 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.220 0.072 11.244 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.364 0.072 11.388 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.508 0.072 11.532 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.652 0.072 11.676 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.796 0.072 11.820 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.940 0.072 11.964 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.084 0.072 12.108 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.228 0.072 12.252 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.372 0.072 12.396 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.516 0.072 12.540 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.660 0.072 12.684 ; + END + END w0_wmask_in[86] + PIN w0_wmask_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.804 0.072 12.828 ; + END + END w0_wmask_in[87] + PIN w0_wmask_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.948 0.072 12.972 ; + END + END w0_wmask_in[88] + PIN w0_wmask_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.092 0.072 13.116 ; + END + END w0_wmask_in[89] + PIN w0_wmask_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.236 0.072 13.260 ; + END + END w0_wmask_in[90] + PIN w0_wmask_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.380 0.072 13.404 ; + END + END w0_wmask_in[91] + PIN w0_wmask_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.524 0.072 13.548 ; + END + END w0_wmask_in[92] + PIN w0_wmask_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.668 0.072 13.692 ; + END + END w0_wmask_in[93] + PIN w0_wmask_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.812 0.072 13.836 ; + END + END w0_wmask_in[94] + PIN w0_wmask_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.956 0.072 13.980 ; + END + END w0_wmask_in[95] + PIN w0_wmask_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.100 0.072 14.124 ; + END + END w0_wmask_in[96] + PIN w0_wmask_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.244 0.072 14.268 ; + END + END w0_wmask_in[97] + PIN w0_wmask_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.388 0.072 14.412 ; + END + END w0_wmask_in[98] + PIN w0_wmask_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.532 0.072 14.556 ; + END + END w0_wmask_in[99] + PIN w0_wmask_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.676 0.072 14.700 ; + END + END w0_wmask_in[100] + PIN w0_wmask_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.820 0.072 14.844 ; + END + END w0_wmask_in[101] + PIN w0_wmask_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.964 0.072 14.988 ; + END + END w0_wmask_in[102] + PIN w0_wmask_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.108 0.072 15.132 ; + END + END w0_wmask_in[103] + PIN w0_wmask_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.252 0.072 15.276 ; + END + END w0_wmask_in[104] + PIN w0_wmask_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.396 0.072 15.420 ; + END + END w0_wmask_in[105] + PIN w0_wmask_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.540 0.072 15.564 ; + END + END w0_wmask_in[106] + PIN w0_wmask_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.684 0.072 15.708 ; + END + END w0_wmask_in[107] + PIN w0_wmask_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.828 0.072 15.852 ; + END + END w0_wmask_in[108] + PIN w0_wmask_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.972 0.072 15.996 ; + END + END w0_wmask_in[109] + PIN w0_wmask_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.116 0.072 16.140 ; + END + END w0_wmask_in[110] + PIN w0_wmask_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.260 0.072 16.284 ; + END + END w0_wmask_in[111] + PIN w0_wmask_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.404 0.072 16.428 ; + END + END w0_wmask_in[112] + PIN w0_wmask_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.548 0.072 16.572 ; + END + END w0_wmask_in[113] + PIN w0_wmask_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.692 0.072 16.716 ; + END + END w0_wmask_in[114] + PIN w0_wmask_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.836 0.072 16.860 ; + END + END w0_wmask_in[115] + PIN w0_wmask_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.980 0.072 17.004 ; + END + END w0_wmask_in[116] + PIN w0_wmask_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.124 0.072 17.148 ; + END + END w0_wmask_in[117] + PIN w0_wmask_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.268 0.072 17.292 ; + END + END w0_wmask_in[118] + PIN w0_wmask_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.412 0.072 17.436 ; + END + END w0_wmask_in[119] + PIN w0_wmask_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.556 0.072 17.580 ; + END + END w0_wmask_in[120] + PIN w0_wmask_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.700 0.072 17.724 ; + END + END w0_wmask_in[121] + PIN w0_wmask_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.844 0.072 17.868 ; + END + END w0_wmask_in[122] + PIN w0_wmask_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.988 0.072 18.012 ; + END + END w0_wmask_in[123] + PIN w0_wmask_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.132 0.072 18.156 ; + END + END w0_wmask_in[124] + PIN w0_wmask_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.276 0.072 18.300 ; + END + END w0_wmask_in[125] + PIN w0_wmask_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.420 0.072 18.444 ; + END + END w0_wmask_in[126] + PIN w0_wmask_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.564 0.072 18.588 ; + END + END w0_wmask_in[127] + PIN w0_wmask_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.708 0.072 18.732 ; + END + END w0_wmask_in[128] + PIN w0_wmask_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.852 0.072 18.876 ; + END + END w0_wmask_in[129] + PIN w0_wmask_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.996 0.072 19.020 ; + END + END w0_wmask_in[130] + PIN w0_wmask_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.140 0.072 19.164 ; + END + END w0_wmask_in[131] + PIN w0_wmask_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.284 0.072 19.308 ; + END + END w0_wmask_in[132] + PIN w0_wmask_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.428 0.072 19.452 ; + END + END w0_wmask_in[133] + PIN w0_wmask_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.572 0.072 19.596 ; + END + END w0_wmask_in[134] + PIN w0_wmask_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.716 0.072 19.740 ; + END + END w0_wmask_in[135] + PIN w0_wmask_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.860 0.072 19.884 ; + END + END w0_wmask_in[136] + PIN w0_wmask_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.004 0.072 20.028 ; + END + END w0_wmask_in[137] + PIN w0_wmask_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.148 0.072 20.172 ; + END + END w0_wmask_in[138] + PIN w0_wmask_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.292 0.072 20.316 ; + END + END w0_wmask_in[139] + PIN w0_wmask_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.436 0.072 20.460 ; + END + END w0_wmask_in[140] + PIN w0_wmask_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.580 0.072 20.604 ; + END + END w0_wmask_in[141] + PIN w0_wmask_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.724 0.072 20.748 ; + END + END w0_wmask_in[142] + PIN w0_wmask_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.868 0.072 20.892 ; + END + END w0_wmask_in[143] + PIN w0_wmask_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.012 0.072 21.036 ; + END + END w0_wmask_in[144] + PIN w0_wmask_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.156 0.072 21.180 ; + END + END w0_wmask_in[145] + PIN w0_wmask_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.300 0.072 21.324 ; + END + END w0_wmask_in[146] + PIN w0_wmask_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.444 0.072 21.468 ; + END + END w0_wmask_in[147] + PIN w0_wmask_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.588 0.072 21.612 ; + END + END w0_wmask_in[148] + PIN w0_wmask_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.732 0.072 21.756 ; + END + END w0_wmask_in[149] + PIN w0_wmask_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.876 0.072 21.900 ; + END + END w0_wmask_in[150] + PIN w0_wmask_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.020 0.072 22.044 ; + END + END w0_wmask_in[151] + PIN w0_wmask_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.164 0.072 22.188 ; + END + END w0_wmask_in[152] + PIN w0_wmask_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.308 0.072 22.332 ; + END + END w0_wmask_in[153] + PIN w0_wmask_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.452 0.072 22.476 ; + END + END w0_wmask_in[154] + PIN w0_wmask_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.596 0.072 22.620 ; + END + END w0_wmask_in[155] + PIN w0_wmask_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.740 0.072 22.764 ; + END + END w0_wmask_in[156] + PIN w0_wmask_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.884 0.072 22.908 ; + END + END w0_wmask_in[157] + PIN w0_wmask_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.028 0.072 23.052 ; + END + END w0_wmask_in[158] + PIN w0_wmask_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.172 0.072 23.196 ; + END + END w0_wmask_in[159] + PIN w0_wmask_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.316 0.072 23.340 ; + END + END w0_wmask_in[160] + PIN w0_wmask_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.460 0.072 23.484 ; + END + END w0_wmask_in[161] + PIN w0_wmask_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.604 0.072 23.628 ; + END + END w0_wmask_in[162] + PIN w0_wmask_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.748 0.072 23.772 ; + END + END w0_wmask_in[163] + PIN w0_wmask_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 0.276 208.506 0.300 ; + END + END w0_wmask_in[164] + PIN w0_wmask_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 0.420 208.506 0.444 ; + END + END w0_wmask_in[165] + PIN w0_wmask_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 0.564 208.506 0.588 ; + END + END w0_wmask_in[166] + PIN w0_wmask_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 0.708 208.506 0.732 ; + END + END w0_wmask_in[167] + PIN w0_wmask_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 0.852 208.506 0.876 ; + END + END w0_wmask_in[168] + PIN w0_wmask_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 0.996 208.506 1.020 ; + END + END w0_wmask_in[169] + PIN w0_wmask_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 1.140 208.506 1.164 ; + END + END w0_wmask_in[170] + PIN w0_wmask_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 1.284 208.506 1.308 ; + END + END w0_wmask_in[171] + PIN w0_wmask_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 1.428 208.506 1.452 ; + END + END w0_wmask_in[172] + PIN w0_wmask_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 1.572 208.506 1.596 ; + END + END w0_wmask_in[173] + PIN w0_wmask_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 1.716 208.506 1.740 ; + END + END w0_wmask_in[174] + PIN w0_wmask_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 1.860 208.506 1.884 ; + END + END w0_wmask_in[175] + PIN w0_wmask_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.004 208.506 2.028 ; + END + END w0_wmask_in[176] + PIN w0_wmask_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.148 208.506 2.172 ; + END + END w0_wmask_in[177] + PIN w0_wmask_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.292 208.506 2.316 ; + END + END w0_wmask_in[178] + PIN w0_wmask_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.436 208.506 2.460 ; + END + END w0_wmask_in[179] + PIN w0_wmask_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.580 208.506 2.604 ; + END + END w0_wmask_in[180] + PIN w0_wmask_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.724 208.506 2.748 ; + END + END w0_wmask_in[181] + PIN w0_wmask_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 2.868 208.506 2.892 ; + END + END w0_wmask_in[182] + PIN w0_wmask_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.012 208.506 3.036 ; + END + END w0_wmask_in[183] + PIN w0_wmask_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.156 208.506 3.180 ; + END + END w0_wmask_in[184] + PIN w0_wmask_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.300 208.506 3.324 ; + END + END w0_wmask_in[185] + PIN w0_wmask_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.444 208.506 3.468 ; + END + END w0_wmask_in[186] + PIN w0_wmask_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.588 208.506 3.612 ; + END + END w0_wmask_in[187] + PIN w0_wmask_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.732 208.506 3.756 ; + END + END w0_wmask_in[188] + PIN w0_wmask_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 3.876 208.506 3.900 ; + END + END w0_wmask_in[189] + PIN w0_wmask_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.020 208.506 4.044 ; + END + END w0_wmask_in[190] + PIN w0_wmask_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.164 208.506 4.188 ; + END + END w0_wmask_in[191] + PIN w0_wmask_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.308 208.506 4.332 ; + END + END w0_wmask_in[192] + PIN w0_wmask_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.452 208.506 4.476 ; + END + END w0_wmask_in[193] + PIN w0_wmask_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.596 208.506 4.620 ; + END + END w0_wmask_in[194] + PIN w0_wmask_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.740 208.506 4.764 ; + END + END w0_wmask_in[195] + PIN w0_wmask_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 4.884 208.506 4.908 ; + END + END w0_wmask_in[196] + PIN w0_wmask_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.028 208.506 5.052 ; + END + END w0_wmask_in[197] + PIN w0_wmask_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.172 208.506 5.196 ; + END + END w0_wmask_in[198] + PIN w0_wmask_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.316 208.506 5.340 ; + END + END w0_wmask_in[199] + PIN w0_wmask_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.460 208.506 5.484 ; + END + END w0_wmask_in[200] + PIN w0_wmask_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.604 208.506 5.628 ; + END + END w0_wmask_in[201] + PIN w0_wmask_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.748 208.506 5.772 ; + END + END w0_wmask_in[202] + PIN w0_wmask_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 5.892 208.506 5.916 ; + END + END w0_wmask_in[203] + PIN w0_wmask_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.036 208.506 6.060 ; + END + END w0_wmask_in[204] + PIN w0_wmask_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.180 208.506 6.204 ; + END + END w0_wmask_in[205] + PIN w0_wmask_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.324 208.506 6.348 ; + END + END w0_wmask_in[206] + PIN w0_wmask_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.468 208.506 6.492 ; + END + END w0_wmask_in[207] + PIN w0_wmask_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.612 208.506 6.636 ; + END + END w0_wmask_in[208] + PIN w0_wmask_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.756 208.506 6.780 ; + END + END w0_wmask_in[209] + PIN w0_wmask_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 6.900 208.506 6.924 ; + END + END w0_wmask_in[210] + PIN w0_wmask_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.044 208.506 7.068 ; + END + END w0_wmask_in[211] + PIN w0_wmask_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.188 208.506 7.212 ; + END + END w0_wmask_in[212] + PIN w0_wmask_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.332 208.506 7.356 ; + END + END w0_wmask_in[213] + PIN w0_wmask_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.476 208.506 7.500 ; + END + END w0_wmask_in[214] + PIN w0_wmask_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.620 208.506 7.644 ; + END + END w0_wmask_in[215] + PIN w0_wmask_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.764 208.506 7.788 ; + END + END w0_wmask_in[216] + PIN w0_wmask_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 7.908 208.506 7.932 ; + END + END w0_wmask_in[217] + PIN w0_wmask_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.052 208.506 8.076 ; + END + END w0_wmask_in[218] + PIN w0_wmask_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.196 208.506 8.220 ; + END + END w0_wmask_in[219] + PIN w0_wmask_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.340 208.506 8.364 ; + END + END w0_wmask_in[220] + PIN w0_wmask_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.484 208.506 8.508 ; + END + END w0_wmask_in[221] + PIN w0_wmask_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.628 208.506 8.652 ; + END + END w0_wmask_in[222] + PIN w0_wmask_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.772 208.506 8.796 ; + END + END w0_wmask_in[223] + PIN w0_wmask_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 8.916 208.506 8.940 ; + END + END w0_wmask_in[224] + PIN w0_wmask_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.060 208.506 9.084 ; + END + END w0_wmask_in[225] + PIN w0_wmask_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.204 208.506 9.228 ; + END + END w0_wmask_in[226] + PIN w0_wmask_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.348 208.506 9.372 ; + END + END w0_wmask_in[227] + PIN w0_wmask_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.492 208.506 9.516 ; + END + END w0_wmask_in[228] + PIN w0_wmask_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.636 208.506 9.660 ; + END + END w0_wmask_in[229] + PIN w0_wmask_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.780 208.506 9.804 ; + END + END w0_wmask_in[230] + PIN w0_wmask_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 9.924 208.506 9.948 ; + END + END w0_wmask_in[231] + PIN w0_wmask_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.068 208.506 10.092 ; + END + END w0_wmask_in[232] + PIN w0_wmask_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.212 208.506 10.236 ; + END + END w0_wmask_in[233] + PIN w0_wmask_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.356 208.506 10.380 ; + END + END w0_wmask_in[234] + PIN w0_wmask_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.500 208.506 10.524 ; + END + END w0_wmask_in[235] + PIN w0_wmask_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.644 208.506 10.668 ; + END + END w0_wmask_in[236] + PIN w0_wmask_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.788 208.506 10.812 ; + END + END w0_wmask_in[237] + PIN w0_wmask_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 10.932 208.506 10.956 ; + END + END w0_wmask_in[238] + PIN w0_wmask_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.076 208.506 11.100 ; + END + END w0_wmask_in[239] + PIN w0_wmask_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.220 208.506 11.244 ; + END + END w0_wmask_in[240] + PIN w0_wmask_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.364 208.506 11.388 ; + END + END w0_wmask_in[241] + PIN w0_wmask_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.508 208.506 11.532 ; + END + END w0_wmask_in[242] + PIN w0_wmask_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.652 208.506 11.676 ; + END + END w0_wmask_in[243] + PIN w0_wmask_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.796 208.506 11.820 ; + END + END w0_wmask_in[244] + PIN w0_wmask_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 11.940 208.506 11.964 ; + END + END w0_wmask_in[245] + PIN w0_wmask_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.084 208.506 12.108 ; + END + END w0_wmask_in[246] + PIN w0_wmask_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.228 208.506 12.252 ; + END + END w0_wmask_in[247] + PIN w0_wmask_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.372 208.506 12.396 ; + END + END w0_wmask_in[248] + PIN w0_wmask_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.516 208.506 12.540 ; + END + END w0_wmask_in[249] + PIN w0_wmask_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.660 208.506 12.684 ; + END + END w0_wmask_in[250] + PIN w0_wmask_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.804 208.506 12.828 ; + END + END w0_wmask_in[251] + PIN w0_wmask_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 12.948 208.506 12.972 ; + END + END w0_wmask_in[252] + PIN w0_wmask_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.092 208.506 13.116 ; + END + END w0_wmask_in[253] + PIN w0_wmask_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.236 208.506 13.260 ; + END + END w0_wmask_in[254] + PIN w0_wmask_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.380 208.506 13.404 ; + END + END w0_wmask_in[255] + PIN w0_wmask_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.524 208.506 13.548 ; + END + END w0_wmask_in[256] + PIN w0_wmask_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.668 208.506 13.692 ; + END + END w0_wmask_in[257] + PIN w0_wmask_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.812 208.506 13.836 ; + END + END w0_wmask_in[258] + PIN w0_wmask_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 13.956 208.506 13.980 ; + END + END w0_wmask_in[259] + PIN w0_wmask_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.100 208.506 14.124 ; + END + END w0_wmask_in[260] + PIN w0_wmask_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.244 208.506 14.268 ; + END + END w0_wmask_in[261] + PIN w0_wmask_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.388 208.506 14.412 ; + END + END w0_wmask_in[262] + PIN w0_wmask_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.532 208.506 14.556 ; + END + END w0_wmask_in[263] + PIN w0_wmask_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.676 208.506 14.700 ; + END + END w0_wmask_in[264] + PIN w0_wmask_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.820 208.506 14.844 ; + END + END w0_wmask_in[265] + PIN w0_wmask_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 14.964 208.506 14.988 ; + END + END w0_wmask_in[266] + PIN w0_wmask_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.108 208.506 15.132 ; + END + END w0_wmask_in[267] + PIN w0_wmask_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.252 208.506 15.276 ; + END + END w0_wmask_in[268] + PIN w0_wmask_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.396 208.506 15.420 ; + END + END w0_wmask_in[269] + PIN w0_wmask_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.540 208.506 15.564 ; + END + END w0_wmask_in[270] + PIN w0_wmask_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.684 208.506 15.708 ; + END + END w0_wmask_in[271] + PIN w0_wmask_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.828 208.506 15.852 ; + END + END w0_wmask_in[272] + PIN w0_wmask_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 15.972 208.506 15.996 ; + END + END w0_wmask_in[273] + PIN w0_wmask_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.116 208.506 16.140 ; + END + END w0_wmask_in[274] + PIN w0_wmask_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.260 208.506 16.284 ; + END + END w0_wmask_in[275] + PIN w0_wmask_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.404 208.506 16.428 ; + END + END w0_wmask_in[276] + PIN w0_wmask_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.548 208.506 16.572 ; + END + END w0_wmask_in[277] + PIN w0_wmask_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.692 208.506 16.716 ; + END + END w0_wmask_in[278] + PIN w0_wmask_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.836 208.506 16.860 ; + END + END w0_wmask_in[279] + PIN w0_wmask_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 16.980 208.506 17.004 ; + END + END w0_wmask_in[280] + PIN w0_wmask_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.124 208.506 17.148 ; + END + END w0_wmask_in[281] + PIN w0_wmask_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.268 208.506 17.292 ; + END + END w0_wmask_in[282] + PIN w0_wmask_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.412 208.506 17.436 ; + END + END w0_wmask_in[283] + PIN w0_wmask_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.556 208.506 17.580 ; + END + END w0_wmask_in[284] + PIN w0_wmask_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.700 208.506 17.724 ; + END + END w0_wmask_in[285] + PIN w0_wmask_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.844 208.506 17.868 ; + END + END w0_wmask_in[286] + PIN w0_wmask_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 17.988 208.506 18.012 ; + END + END w0_wmask_in[287] + PIN w0_wmask_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.132 208.506 18.156 ; + END + END w0_wmask_in[288] + PIN w0_wmask_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.276 208.506 18.300 ; + END + END w0_wmask_in[289] + PIN w0_wmask_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.420 208.506 18.444 ; + END + END w0_wmask_in[290] + PIN w0_wmask_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.564 208.506 18.588 ; + END + END w0_wmask_in[291] + PIN w0_wmask_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.708 208.506 18.732 ; + END + END w0_wmask_in[292] + PIN w0_wmask_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.852 208.506 18.876 ; + END + END w0_wmask_in[293] + PIN w0_wmask_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 18.996 208.506 19.020 ; + END + END w0_wmask_in[294] + PIN w0_wmask_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 19.140 208.506 19.164 ; + END + END w0_wmask_in[295] + PIN w0_wmask_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 19.284 208.506 19.308 ; + END + END w0_wmask_in[296] + PIN w0_wmask_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 19.428 208.506 19.452 ; + END + END w0_wmask_in[297] + PIN w0_wmask_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 19.572 208.506 19.596 ; + END + END w0_wmask_in[298] + PIN w0_wmask_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 19.716 208.506 19.740 ; + END + END w0_wmask_in[299] + PIN w0_wmask_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 19.860 208.506 19.884 ; + END + END w0_wmask_in[300] + PIN w0_wmask_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.004 208.506 20.028 ; + END + END w0_wmask_in[301] + PIN w0_wmask_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.148 208.506 20.172 ; + END + END w0_wmask_in[302] + PIN w0_wmask_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.292 208.506 20.316 ; + END + END w0_wmask_in[303] + PIN w0_wmask_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.436 208.506 20.460 ; + END + END w0_wmask_in[304] + PIN w0_wmask_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.580 208.506 20.604 ; + END + END w0_wmask_in[305] + PIN w0_wmask_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.724 208.506 20.748 ; + END + END w0_wmask_in[306] + PIN w0_wmask_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 20.868 208.506 20.892 ; + END + END w0_wmask_in[307] + PIN w0_wmask_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.012 208.506 21.036 ; + END + END w0_wmask_in[308] + PIN w0_wmask_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.156 208.506 21.180 ; + END + END w0_wmask_in[309] + PIN w0_wmask_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.300 208.506 21.324 ; + END + END w0_wmask_in[310] + PIN w0_wmask_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.444 208.506 21.468 ; + END + END w0_wmask_in[311] + PIN w0_wmask_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.588 208.506 21.612 ; + END + END w0_wmask_in[312] + PIN w0_wmask_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.732 208.506 21.756 ; + END + END w0_wmask_in[313] + PIN w0_wmask_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 21.876 208.506 21.900 ; + END + END w0_wmask_in[314] + PIN w0_wmask_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.020 208.506 22.044 ; + END + END w0_wmask_in[315] + PIN w0_wmask_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.164 208.506 22.188 ; + END + END w0_wmask_in[316] + PIN w0_wmask_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.308 208.506 22.332 ; + END + END w0_wmask_in[317] + PIN w0_wmask_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.452 208.506 22.476 ; + END + END w0_wmask_in[318] + PIN w0_wmask_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.596 208.506 22.620 ; + END + END w0_wmask_in[319] + PIN w0_wmask_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.740 208.506 22.764 ; + END + END w0_wmask_in[320] + PIN w0_wmask_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 22.884 208.506 22.908 ; + END + END w0_wmask_in[321] + PIN w0_wmask_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.028 208.506 23.052 ; + END + END w0_wmask_in[322] + PIN w0_wmask_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.172 208.506 23.196 ; + END + END w0_wmask_in[323] + PIN w0_wmask_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.316 208.506 23.340 ; + END + END w0_wmask_in[324] + PIN w0_wmask_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.460 208.506 23.484 ; + END + END w0_wmask_in[325] + PIN w0_wmask_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.604 208.506 23.628 ; + END + END w0_wmask_in[326] + PIN w0_wmask_in[327] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 58.573 0.225 58.627 ; + END + END w0_wmask_in[327] + PIN w0_wmask_in[328] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 58.573 0.513 58.627 ; + END + END w0_wmask_in[328] + PIN w0_wmask_in[329] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 58.573 0.801 58.627 ; + END + END w0_wmask_in[329] + PIN w0_wmask_in[330] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 58.573 1.089 58.627 ; + END + END w0_wmask_in[330] + PIN w0_wmask_in[331] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 58.573 1.377 58.627 ; + END + END w0_wmask_in[331] + PIN w0_wmask_in[332] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 58.573 1.665 58.627 ; + END + END w0_wmask_in[332] + PIN w0_wmask_in[333] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 58.573 1.953 58.627 ; + END + END w0_wmask_in[333] + PIN w0_wmask_in[334] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 58.573 2.241 58.627 ; + END + END w0_wmask_in[334] + PIN w0_wmask_in[335] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 58.573 2.529 58.627 ; + END + END w0_wmask_in[335] + PIN w0_wmask_in[336] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 58.573 2.817 58.627 ; + END + END w0_wmask_in[336] + PIN w0_wmask_in[337] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 58.573 3.105 58.627 ; + END + END w0_wmask_in[337] + PIN w0_wmask_in[338] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 58.573 3.393 58.627 ; + END + END w0_wmask_in[338] + PIN w0_wmask_in[339] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 58.573 3.681 58.627 ; + END + END w0_wmask_in[339] + PIN w0_wmask_in[340] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 58.573 3.969 58.627 ; + END + END w0_wmask_in[340] + PIN w0_wmask_in[341] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 58.573 4.257 58.627 ; + END + END w0_wmask_in[341] + PIN w0_wmask_in[342] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 58.573 4.545 58.627 ; + END + END w0_wmask_in[342] + PIN w0_wmask_in[343] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 58.573 4.833 58.627 ; + END + END w0_wmask_in[343] + PIN w0_wmask_in[344] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 58.573 5.121 58.627 ; + END + END w0_wmask_in[344] + PIN w0_wmask_in[345] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 58.573 5.409 58.627 ; + END + END w0_wmask_in[345] + PIN w0_wmask_in[346] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 58.573 5.697 58.627 ; + END + END w0_wmask_in[346] + PIN w0_wmask_in[347] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 58.573 5.985 58.627 ; + END + END w0_wmask_in[347] + PIN w0_wmask_in[348] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 58.573 6.273 58.627 ; + END + END w0_wmask_in[348] + PIN w0_wmask_in[349] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 58.573 6.561 58.627 ; + END + END w0_wmask_in[349] + PIN w0_wmask_in[350] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 58.573 6.849 58.627 ; + END + END w0_wmask_in[350] + PIN w0_wmask_in[351] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 58.573 7.137 58.627 ; + END + END w0_wmask_in[351] + PIN w0_wmask_in[352] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 58.573 7.425 58.627 ; + END + END w0_wmask_in[352] + PIN w0_wmask_in[353] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 58.573 7.713 58.627 ; + END + END w0_wmask_in[353] + PIN w0_wmask_in[354] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 58.573 8.001 58.627 ; + END + END w0_wmask_in[354] + PIN w0_wmask_in[355] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 58.573 8.289 58.627 ; + END + END w0_wmask_in[355] + PIN w0_wmask_in[356] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 58.573 8.577 58.627 ; + END + END w0_wmask_in[356] + PIN w0_wmask_in[357] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 58.573 8.865 58.627 ; + END + END w0_wmask_in[357] + PIN w0_wmask_in[358] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 58.573 9.153 58.627 ; + END + END w0_wmask_in[358] + PIN w0_wmask_in[359] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 58.573 9.441 58.627 ; + END + END w0_wmask_in[359] + PIN w0_wmask_in[360] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 58.573 9.729 58.627 ; + END + END w0_wmask_in[360] + PIN w0_wmask_in[361] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 58.573 10.017 58.627 ; + END + END w0_wmask_in[361] + PIN w0_wmask_in[362] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 58.573 10.305 58.627 ; + END + END w0_wmask_in[362] + PIN w0_wmask_in[363] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 58.573 10.593 58.627 ; + END + END w0_wmask_in[363] + PIN w0_wmask_in[364] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 58.573 10.881 58.627 ; + END + END w0_wmask_in[364] + PIN w0_wmask_in[365] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 58.573 11.169 58.627 ; + END + END w0_wmask_in[365] + PIN w0_wmask_in[366] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 58.573 11.457 58.627 ; + END + END w0_wmask_in[366] + PIN w0_wmask_in[367] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 58.573 11.745 58.627 ; + END + END w0_wmask_in[367] + PIN w0_wmask_in[368] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 58.573 12.033 58.627 ; + END + END w0_wmask_in[368] + PIN w0_wmask_in[369] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 58.573 12.321 58.627 ; + END + END w0_wmask_in[369] + PIN w0_wmask_in[370] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 58.573 12.609 58.627 ; + END + END w0_wmask_in[370] + PIN w0_wmask_in[371] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 58.573 12.897 58.627 ; + END + END w0_wmask_in[371] + PIN w0_wmask_in[372] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 58.573 13.185 58.627 ; + END + END w0_wmask_in[372] + PIN w0_wmask_in[373] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 58.573 13.473 58.627 ; + END + END w0_wmask_in[373] + PIN w0_wmask_in[374] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 58.573 13.761 58.627 ; + END + END w0_wmask_in[374] + PIN w0_wmask_in[375] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 58.573 14.049 58.627 ; + END + END w0_wmask_in[375] + PIN w0_wmask_in[376] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 58.573 14.337 58.627 ; + END + END w0_wmask_in[376] + PIN w0_wmask_in[377] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 58.573 14.625 58.627 ; + END + END w0_wmask_in[377] + PIN w0_wmask_in[378] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 58.573 14.913 58.627 ; + END + END w0_wmask_in[378] + PIN w0_wmask_in[379] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 58.573 15.201 58.627 ; + END + END w0_wmask_in[379] + PIN w0_wmask_in[380] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 58.573 15.489 58.627 ; + END + END w0_wmask_in[380] + PIN w0_wmask_in[381] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 58.573 15.777 58.627 ; + END + END w0_wmask_in[381] + PIN w0_wmask_in[382] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 58.573 16.065 58.627 ; + END + END w0_wmask_in[382] + PIN w0_wmask_in[383] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 58.573 16.353 58.627 ; + END + END w0_wmask_in[383] + PIN w0_wmask_in[384] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 58.573 16.641 58.627 ; + END + END w0_wmask_in[384] + PIN w0_wmask_in[385] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 58.573 16.929 58.627 ; + END + END w0_wmask_in[385] + PIN w0_wmask_in[386] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 58.573 17.217 58.627 ; + END + END w0_wmask_in[386] + PIN w0_wmask_in[387] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 58.573 17.505 58.627 ; + END + END w0_wmask_in[387] + PIN w0_wmask_in[388] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 58.573 17.793 58.627 ; + END + END w0_wmask_in[388] + PIN w0_wmask_in[389] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 58.573 18.081 58.627 ; + END + END w0_wmask_in[389] + PIN w0_wmask_in[390] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 58.573 18.369 58.627 ; + END + END w0_wmask_in[390] + PIN w0_wmask_in[391] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 58.573 18.657 58.627 ; + END + END w0_wmask_in[391] + PIN w0_wmask_in[392] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 58.573 18.945 58.627 ; + END + END w0_wmask_in[392] + PIN w0_wmask_in[393] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 58.573 19.233 58.627 ; + END + END w0_wmask_in[393] + PIN w0_wmask_in[394] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 58.573 19.521 58.627 ; + END + END w0_wmask_in[394] + PIN w0_wmask_in[395] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 58.573 19.809 58.627 ; + END + END w0_wmask_in[395] + PIN w0_wmask_in[396] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 58.573 20.097 58.627 ; + END + END w0_wmask_in[396] + PIN w0_wmask_in[397] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 58.573 20.385 58.627 ; + END + END w0_wmask_in[397] + PIN w0_wmask_in[398] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 58.573 20.673 58.627 ; + END + END w0_wmask_in[398] + PIN w0_wmask_in[399] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 58.573 20.961 58.627 ; + END + END w0_wmask_in[399] + PIN w0_wmask_in[400] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 58.573 21.249 58.627 ; + END + END w0_wmask_in[400] + PIN w0_wmask_in[401] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 58.573 21.537 58.627 ; + END + END w0_wmask_in[401] + PIN w0_wmask_in[402] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 58.573 21.825 58.627 ; + END + END w0_wmask_in[402] + PIN w0_wmask_in[403] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 58.573 22.113 58.627 ; + END + END w0_wmask_in[403] + PIN w0_wmask_in[404] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 58.573 22.401 58.627 ; + END + END w0_wmask_in[404] + PIN w0_wmask_in[405] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 58.573 22.689 58.627 ; + END + END w0_wmask_in[405] + PIN w0_wmask_in[406] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 58.573 22.977 58.627 ; + END + END w0_wmask_in[406] + PIN w0_wmask_in[407] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 58.573 23.265 58.627 ; + END + END w0_wmask_in[407] + PIN w0_wmask_in[408] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 58.573 23.553 58.627 ; + END + END w0_wmask_in[408] + PIN w0_wmask_in[409] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 58.573 23.841 58.627 ; + END + END w0_wmask_in[409] + PIN w0_wmask_in[410] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 58.573 24.129 58.627 ; + END + END w0_wmask_in[410] + PIN w0_wmask_in[411] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 58.573 24.417 58.627 ; + END + END w0_wmask_in[411] + PIN w0_wmask_in[412] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 58.573 24.705 58.627 ; + END + END w0_wmask_in[412] + PIN w0_wmask_in[413] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 58.573 24.993 58.627 ; + END + END w0_wmask_in[413] + PIN w0_wmask_in[414] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 58.573 25.281 58.627 ; + END + END w0_wmask_in[414] + PIN w0_wmask_in[415] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 58.573 25.569 58.627 ; + END + END w0_wmask_in[415] + PIN w0_wmask_in[416] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 58.573 25.857 58.627 ; + END + END w0_wmask_in[416] + PIN w0_wmask_in[417] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 58.573 26.145 58.627 ; + END + END w0_wmask_in[417] + PIN w0_wmask_in[418] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 58.573 26.433 58.627 ; + END + END w0_wmask_in[418] + PIN w0_wmask_in[419] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 58.573 26.721 58.627 ; + END + END w0_wmask_in[419] + PIN w0_wmask_in[420] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 58.573 27.009 58.627 ; + END + END w0_wmask_in[420] + PIN w0_wmask_in[421] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 58.573 27.297 58.627 ; + END + END w0_wmask_in[421] + PIN w0_wmask_in[422] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 58.573 27.585 58.627 ; + END + END w0_wmask_in[422] + PIN w0_wmask_in[423] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 58.573 27.873 58.627 ; + END + END w0_wmask_in[423] + PIN w0_wmask_in[424] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 58.573 28.161 58.627 ; + END + END w0_wmask_in[424] + PIN w0_wmask_in[425] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 58.573 28.449 58.627 ; + END + END w0_wmask_in[425] + PIN w0_wmask_in[426] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 58.573 28.737 58.627 ; + END + END w0_wmask_in[426] + PIN w0_wmask_in[427] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 58.573 29.025 58.627 ; + END + END w0_wmask_in[427] + PIN w0_wmask_in[428] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 58.573 29.313 58.627 ; + END + END w0_wmask_in[428] + PIN w0_wmask_in[429] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 58.573 29.601 58.627 ; + END + END w0_wmask_in[429] + PIN w0_wmask_in[430] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 58.573 29.889 58.627 ; + END + END w0_wmask_in[430] + PIN w0_wmask_in[431] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 58.573 30.177 58.627 ; + END + END w0_wmask_in[431] + PIN w0_wmask_in[432] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 58.573 30.465 58.627 ; + END + END w0_wmask_in[432] + PIN w0_wmask_in[433] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 58.573 30.753 58.627 ; + END + END w0_wmask_in[433] + PIN w0_wmask_in[434] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 58.573 31.041 58.627 ; + END + END w0_wmask_in[434] + PIN w0_wmask_in[435] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 58.573 31.329 58.627 ; + END + END w0_wmask_in[435] + PIN w0_wmask_in[436] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 58.573 31.617 58.627 ; + END + END w0_wmask_in[436] + PIN w0_wmask_in[437] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 58.573 31.905 58.627 ; + END + END w0_wmask_in[437] + PIN w0_wmask_in[438] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 58.573 32.193 58.627 ; + END + END w0_wmask_in[438] + PIN w0_wmask_in[439] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 58.573 32.481 58.627 ; + END + END w0_wmask_in[439] + PIN w0_wmask_in[440] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 58.573 32.769 58.627 ; + END + END w0_wmask_in[440] + PIN w0_wmask_in[441] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 58.573 33.057 58.627 ; + END + END w0_wmask_in[441] + PIN w0_wmask_in[442] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 58.573 33.345 58.627 ; + END + END w0_wmask_in[442] + PIN w0_wmask_in[443] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 58.573 33.633 58.627 ; + END + END w0_wmask_in[443] + PIN w0_wmask_in[444] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 58.573 33.921 58.627 ; + END + END w0_wmask_in[444] + PIN w0_wmask_in[445] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 58.573 34.209 58.627 ; + END + END w0_wmask_in[445] + PIN w0_wmask_in[446] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 58.573 34.497 58.627 ; + END + END w0_wmask_in[446] + PIN w0_wmask_in[447] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 58.573 34.785 58.627 ; + END + END w0_wmask_in[447] + PIN w0_wmask_in[448] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 58.573 35.073 58.627 ; + END + END w0_wmask_in[448] + PIN w0_wmask_in[449] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 58.573 35.361 58.627 ; + END + END w0_wmask_in[449] + PIN w0_wmask_in[450] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 58.573 35.649 58.627 ; + END + END w0_wmask_in[450] + PIN w0_wmask_in[451] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 58.573 35.937 58.627 ; + END + END w0_wmask_in[451] + PIN w0_wmask_in[452] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 58.573 36.225 58.627 ; + END + END w0_wmask_in[452] + PIN w0_wmask_in[453] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 58.573 36.513 58.627 ; + END + END w0_wmask_in[453] + PIN w0_wmask_in[454] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 58.573 36.801 58.627 ; + END + END w0_wmask_in[454] + PIN w0_wmask_in[455] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 58.573 37.089 58.627 ; + END + END w0_wmask_in[455] + PIN w0_wmask_in[456] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 58.573 37.377 58.627 ; + END + END w0_wmask_in[456] + PIN w0_wmask_in[457] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 58.573 37.665 58.627 ; + END + END w0_wmask_in[457] + PIN w0_wmask_in[458] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 58.573 37.953 58.627 ; + END + END w0_wmask_in[458] + PIN w0_wmask_in[459] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 58.573 38.241 58.627 ; + END + END w0_wmask_in[459] + PIN w0_wmask_in[460] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 58.573 38.529 58.627 ; + END + END w0_wmask_in[460] + PIN w0_wmask_in[461] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 58.573 38.817 58.627 ; + END + END w0_wmask_in[461] + PIN w0_wmask_in[462] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 58.573 39.105 58.627 ; + END + END w0_wmask_in[462] + PIN w0_wmask_in[463] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 58.573 39.393 58.627 ; + END + END w0_wmask_in[463] + PIN w0_wmask_in[464] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 58.573 39.681 58.627 ; + END + END w0_wmask_in[464] + PIN w0_wmask_in[465] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 58.573 39.969 58.627 ; + END + END w0_wmask_in[465] + PIN w0_wmask_in[466] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 58.573 40.257 58.627 ; + END + END w0_wmask_in[466] + PIN w0_wmask_in[467] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 58.573 40.545 58.627 ; + END + END w0_wmask_in[467] + PIN w0_wmask_in[468] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 58.573 40.833 58.627 ; + END + END w0_wmask_in[468] + PIN w0_wmask_in[469] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 58.573 41.121 58.627 ; + END + END w0_wmask_in[469] + PIN w0_wmask_in[470] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 58.573 41.409 58.627 ; + END + END w0_wmask_in[470] + PIN w0_wmask_in[471] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 58.573 41.697 58.627 ; + END + END w0_wmask_in[471] + PIN w0_wmask_in[472] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 58.573 41.985 58.627 ; + END + END w0_wmask_in[472] + PIN w0_wmask_in[473] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 58.573 42.273 58.627 ; + END + END w0_wmask_in[473] + PIN w0_wmask_in[474] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 58.573 42.561 58.627 ; + END + END w0_wmask_in[474] + PIN w0_wmask_in[475] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 58.573 42.849 58.627 ; + END + END w0_wmask_in[475] + PIN w0_wmask_in[476] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 58.573 43.137 58.627 ; + END + END w0_wmask_in[476] + PIN w0_wmask_in[477] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 58.573 43.425 58.627 ; + END + END w0_wmask_in[477] + PIN w0_wmask_in[478] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 58.573 43.713 58.627 ; + END + END w0_wmask_in[478] + PIN w0_wmask_in[479] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 58.573 44.001 58.627 ; + END + END w0_wmask_in[479] + PIN w0_wmask_in[480] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 58.573 44.289 58.627 ; + END + END w0_wmask_in[480] + PIN w0_wmask_in[481] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 58.573 44.577 58.627 ; + END + END w0_wmask_in[481] + PIN w0_wmask_in[482] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 58.573 44.865 58.627 ; + END + END w0_wmask_in[482] + PIN w0_wmask_in[483] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 58.573 45.153 58.627 ; + END + END w0_wmask_in[483] + PIN w0_wmask_in[484] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 58.573 45.441 58.627 ; + END + END w0_wmask_in[484] + PIN w0_wmask_in[485] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 58.573 45.729 58.627 ; + END + END w0_wmask_in[485] + PIN w0_wmask_in[486] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 58.573 46.017 58.627 ; + END + END w0_wmask_in[486] + PIN w0_wmask_in[487] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 58.573 46.305 58.627 ; + END + END w0_wmask_in[487] + PIN w0_wmask_in[488] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 58.573 46.593 58.627 ; + END + END w0_wmask_in[488] + PIN w0_wmask_in[489] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 58.573 46.881 58.627 ; + END + END w0_wmask_in[489] + PIN w0_wmask_in[490] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 58.573 47.169 58.627 ; + END + END w0_wmask_in[490] + PIN w0_wmask_in[491] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 58.573 47.457 58.627 ; + END + END w0_wmask_in[491] + PIN w0_wmask_in[492] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 58.573 47.745 58.627 ; + END + END w0_wmask_in[492] + PIN w0_wmask_in[493] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 58.573 48.033 58.627 ; + END + END w0_wmask_in[493] + PIN w0_wmask_in[494] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 58.573 48.321 58.627 ; + END + END w0_wmask_in[494] + PIN w0_wmask_in[495] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 58.573 48.609 58.627 ; + END + END w0_wmask_in[495] + PIN w0_wmask_in[496] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 58.573 48.897 58.627 ; + END + END w0_wmask_in[496] + PIN w0_wmask_in[497] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 58.573 49.185 58.627 ; + END + END w0_wmask_in[497] + PIN w0_wmask_in[498] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 58.573 49.473 58.627 ; + END + END w0_wmask_in[498] + PIN w0_wmask_in[499] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 58.573 49.761 58.627 ; + END + END w0_wmask_in[499] + PIN w0_wmask_in[500] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 58.573 50.049 58.627 ; + END + END w0_wmask_in[500] + PIN w0_wmask_in[501] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 58.573 50.337 58.627 ; + END + END w0_wmask_in[501] + PIN w0_wmask_in[502] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 58.573 50.625 58.627 ; + END + END w0_wmask_in[502] + PIN w0_wmask_in[503] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 58.573 50.913 58.627 ; + END + END w0_wmask_in[503] + PIN w0_wmask_in[504] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 58.573 51.201 58.627 ; + END + END w0_wmask_in[504] + PIN w0_wmask_in[505] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 58.573 51.489 58.627 ; + END + END w0_wmask_in[505] + PIN w0_wmask_in[506] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 58.573 51.777 58.627 ; + END + END w0_wmask_in[506] + PIN w0_wmask_in[507] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 58.573 52.065 58.627 ; + END + END w0_wmask_in[507] + PIN w0_wmask_in[508] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 58.573 52.353 58.627 ; + END + END w0_wmask_in[508] + PIN w0_wmask_in[509] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 58.573 52.641 58.627 ; + END + END w0_wmask_in[509] + PIN w0_wmask_in[510] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 58.573 52.929 58.627 ; + END + END w0_wmask_in[510] + PIN w0_wmask_in[511] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 58.573 53.217 58.627 ; + END + END w0_wmask_in[511] + PIN w0_wmask_in[512] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 58.573 53.505 58.627 ; + END + END w0_wmask_in[512] + PIN w0_wmask_in[513] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 58.573 53.793 58.627 ; + END + END w0_wmask_in[513] + PIN w0_wmask_in[514] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 58.573 54.081 58.627 ; + END + END w0_wmask_in[514] + PIN w0_wmask_in[515] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 58.573 54.369 58.627 ; + END + END w0_wmask_in[515] + PIN w0_wmask_in[516] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 58.573 54.657 58.627 ; + END + END w0_wmask_in[516] + PIN w0_wmask_in[517] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 58.573 54.945 58.627 ; + END + END w0_wmask_in[517] + PIN w0_wmask_in[518] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 58.573 55.233 58.627 ; + END + END w0_wmask_in[518] + PIN w0_wmask_in[519] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 58.573 55.521 58.627 ; + END + END w0_wmask_in[519] + PIN w0_wmask_in[520] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 58.573 55.809 58.627 ; + END + END w0_wmask_in[520] + PIN w0_wmask_in[521] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 58.573 56.097 58.627 ; + END + END w0_wmask_in[521] + PIN w0_wmask_in[522] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 58.573 56.385 58.627 ; + END + END w0_wmask_in[522] + PIN w0_wmask_in[523] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 58.573 56.673 58.627 ; + END + END w0_wmask_in[523] + PIN w0_wmask_in[524] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 58.573 56.961 58.627 ; + END + END w0_wmask_in[524] + PIN w0_wmask_in[525] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 58.573 57.249 58.627 ; + END + END w0_wmask_in[525] + PIN w0_wmask_in[526] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 58.573 57.537 58.627 ; + END + END w0_wmask_in[526] + PIN w0_wmask_in[527] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 58.573 57.825 58.627 ; + END + END w0_wmask_in[527] + PIN w0_wmask_in[528] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 58.573 58.113 58.627 ; + END + END w0_wmask_in[528] + PIN w0_wmask_in[529] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 58.573 58.401 58.627 ; + END + END w0_wmask_in[529] + PIN w0_wmask_in[530] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 58.573 58.689 58.627 ; + END + END w0_wmask_in[530] + PIN w0_wmask_in[531] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 58.573 58.977 58.627 ; + END + END w0_wmask_in[531] + PIN w0_wmask_in[532] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 58.573 59.265 58.627 ; + END + END w0_wmask_in[532] + PIN w0_wmask_in[533] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 58.573 59.553 58.627 ; + END + END w0_wmask_in[533] + PIN w0_wmask_in[534] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 58.573 59.841 58.627 ; + END + END w0_wmask_in[534] + PIN w0_wmask_in[535] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 58.573 60.129 58.627 ; + END + END w0_wmask_in[535] + PIN w0_wmask_in[536] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 58.573 60.417 58.627 ; + END + END w0_wmask_in[536] + PIN w0_wmask_in[537] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 58.573 60.705 58.627 ; + END + END w0_wmask_in[537] + PIN w0_wmask_in[538] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 58.573 60.993 58.627 ; + END + END w0_wmask_in[538] + PIN w0_wmask_in[539] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 58.573 61.281 58.627 ; + END + END w0_wmask_in[539] + PIN w0_wmask_in[540] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 58.573 61.569 58.627 ; + END + END w0_wmask_in[540] + PIN w0_wmask_in[541] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 58.573 61.857 58.627 ; + END + END w0_wmask_in[541] + PIN w0_wmask_in[542] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 58.573 62.145 58.627 ; + END + END w0_wmask_in[542] + PIN w0_wmask_in[543] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 58.573 62.433 58.627 ; + END + END w0_wmask_in[543] + PIN w0_wmask_in[544] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 58.573 62.721 58.627 ; + END + END w0_wmask_in[544] + PIN w0_wmask_in[545] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 58.573 63.009 58.627 ; + END + END w0_wmask_in[545] + PIN w0_wmask_in[546] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 58.573 63.297 58.627 ; + END + END w0_wmask_in[546] + PIN w0_wmask_in[547] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 58.573 63.585 58.627 ; + END + END w0_wmask_in[547] + PIN w0_wmask_in[548] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 58.573 63.873 58.627 ; + END + END w0_wmask_in[548] + PIN w0_wmask_in[549] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 58.573 64.161 58.627 ; + END + END w0_wmask_in[549] + PIN w0_wmask_in[550] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 58.573 64.449 58.627 ; + END + END w0_wmask_in[550] + PIN w0_wmask_in[551] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 58.573 64.737 58.627 ; + END + END w0_wmask_in[551] + PIN w0_wmask_in[552] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 58.573 65.025 58.627 ; + END + END w0_wmask_in[552] + PIN w0_wmask_in[553] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 58.573 65.313 58.627 ; + END + END w0_wmask_in[553] + PIN w0_wmask_in[554] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 58.573 65.601 58.627 ; + END + END w0_wmask_in[554] + PIN w0_wmask_in[555] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 58.573 65.889 58.627 ; + END + END w0_wmask_in[555] + PIN w0_wmask_in[556] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 58.573 66.177 58.627 ; + END + END w0_wmask_in[556] + PIN w0_wmask_in[557] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 58.573 66.465 58.627 ; + END + END w0_wmask_in[557] + PIN w0_wmask_in[558] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 58.573 66.753 58.627 ; + END + END w0_wmask_in[558] + PIN w0_wmask_in[559] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 58.573 67.041 58.627 ; + END + END w0_wmask_in[559] + PIN w0_wmask_in[560] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 58.573 67.329 58.627 ; + END + END w0_wmask_in[560] + PIN w0_wmask_in[561] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 58.573 67.617 58.627 ; + END + END w0_wmask_in[561] + PIN w0_wmask_in[562] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 58.573 67.905 58.627 ; + END + END w0_wmask_in[562] + PIN w0_wmask_in[563] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 58.573 68.193 58.627 ; + END + END w0_wmask_in[563] + PIN w0_wmask_in[564] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 58.573 68.481 58.627 ; + END + END w0_wmask_in[564] + PIN w0_wmask_in[565] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 58.573 68.769 58.627 ; + END + END w0_wmask_in[565] + PIN w0_wmask_in[566] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 58.573 69.057 58.627 ; + END + END w0_wmask_in[566] + PIN w0_wmask_in[567] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 58.573 69.345 58.627 ; + END + END w0_wmask_in[567] + PIN w0_wmask_in[568] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 58.573 69.633 58.627 ; + END + END w0_wmask_in[568] + PIN w0_wmask_in[569] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 58.573 69.921 58.627 ; + END + END w0_wmask_in[569] + PIN w0_wmask_in[570] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 58.573 70.209 58.627 ; + END + END w0_wmask_in[570] + PIN w0_wmask_in[571] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 58.573 70.497 58.627 ; + END + END w0_wmask_in[571] + PIN w0_wmask_in[572] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 58.573 70.785 58.627 ; + END + END w0_wmask_in[572] + PIN w0_wmask_in[573] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 58.573 71.073 58.627 ; + END + END w0_wmask_in[573] + PIN w0_wmask_in[574] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 58.573 71.361 58.627 ; + END + END w0_wmask_in[574] + PIN w0_wmask_in[575] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 58.573 71.649 58.627 ; + END + END w0_wmask_in[575] + PIN w0_wmask_in[576] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 58.573 71.937 58.627 ; + END + END w0_wmask_in[576] + PIN w0_wmask_in[577] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 58.573 72.225 58.627 ; + END + END w0_wmask_in[577] + PIN w0_wmask_in[578] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 58.573 72.513 58.627 ; + END + END w0_wmask_in[578] + PIN w0_wmask_in[579] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 58.573 72.801 58.627 ; + END + END w0_wmask_in[579] + PIN w0_wmask_in[580] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 58.573 73.089 58.627 ; + END + END w0_wmask_in[580] + PIN w0_wmask_in[581] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 58.573 73.377 58.627 ; + END + END w0_wmask_in[581] + PIN w0_wmask_in[582] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 58.573 73.665 58.627 ; + END + END w0_wmask_in[582] + PIN w0_wmask_in[583] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 58.573 73.953 58.627 ; + END + END w0_wmask_in[583] + PIN w0_wmask_in[584] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 58.573 74.241 58.627 ; + END + END w0_wmask_in[584] + PIN w0_wmask_in[585] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 58.573 74.529 58.627 ; + END + END w0_wmask_in[585] + PIN w0_wmask_in[586] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 58.573 74.817 58.627 ; + END + END w0_wmask_in[586] + PIN w0_wmask_in[587] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 58.573 75.105 58.627 ; + END + END w0_wmask_in[587] + PIN w0_wmask_in[588] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 58.573 75.393 58.627 ; + END + END w0_wmask_in[588] + PIN w0_wmask_in[589] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 58.573 75.681 58.627 ; + END + END w0_wmask_in[589] + PIN w0_wmask_in[590] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 58.573 75.969 58.627 ; + END + END w0_wmask_in[590] + PIN w0_wmask_in[591] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 58.573 76.257 58.627 ; + END + END w0_wmask_in[591] + PIN w0_wmask_in[592] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 58.573 76.545 58.627 ; + END + END w0_wmask_in[592] + PIN w0_wmask_in[593] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 58.573 76.833 58.627 ; + END + END w0_wmask_in[593] + PIN w0_wmask_in[594] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 58.573 77.121 58.627 ; + END + END w0_wmask_in[594] + PIN w0_wmask_in[595] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 58.573 77.409 58.627 ; + END + END w0_wmask_in[595] + PIN w0_wmask_in[596] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 58.573 77.697 58.627 ; + END + END w0_wmask_in[596] + PIN w0_wmask_in[597] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 58.573 77.985 58.627 ; + END + END w0_wmask_in[597] + PIN w0_wmask_in[598] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 58.573 78.273 58.627 ; + END + END w0_wmask_in[598] + PIN w0_wmask_in[599] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 58.573 78.561 58.627 ; + END + END w0_wmask_in[599] + PIN w0_wmask_in[600] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 58.573 78.849 58.627 ; + END + END w0_wmask_in[600] + PIN w0_wmask_in[601] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 58.573 79.137 58.627 ; + END + END w0_wmask_in[601] + PIN w0_wmask_in[602] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 58.573 79.425 58.627 ; + END + END w0_wmask_in[602] + PIN w0_wmask_in[603] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 58.573 79.713 58.627 ; + END + END w0_wmask_in[603] + PIN w0_wmask_in[604] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 58.573 80.001 58.627 ; + END + END w0_wmask_in[604] + PIN w0_wmask_in[605] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 58.573 80.289 58.627 ; + END + END w0_wmask_in[605] + PIN w0_wmask_in[606] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 58.573 80.577 58.627 ; + END + END w0_wmask_in[606] + PIN w0_wmask_in[607] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 58.573 80.865 58.627 ; + END + END w0_wmask_in[607] + PIN w0_wmask_in[608] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 58.573 81.153 58.627 ; + END + END w0_wmask_in[608] + PIN w0_wmask_in[609] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 58.573 81.441 58.627 ; + END + END w0_wmask_in[609] + PIN w0_wmask_in[610] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 58.573 81.729 58.627 ; + END + END w0_wmask_in[610] + PIN w0_wmask_in[611] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 58.573 82.017 58.627 ; + END + END w0_wmask_in[611] + PIN w0_wmask_in[612] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 58.573 82.305 58.627 ; + END + END w0_wmask_in[612] + PIN w0_wmask_in[613] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 58.573 82.593 58.627 ; + END + END w0_wmask_in[613] + PIN w0_wmask_in[614] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 58.573 82.881 58.627 ; + END + END w0_wmask_in[614] + PIN w0_wmask_in[615] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 58.573 83.169 58.627 ; + END + END w0_wmask_in[615] + PIN w0_wmask_in[616] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 58.573 83.457 58.627 ; + END + END w0_wmask_in[616] + PIN w0_wmask_in[617] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 58.573 83.745 58.627 ; + END + END w0_wmask_in[617] + PIN w0_wmask_in[618] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 58.573 84.033 58.627 ; + END + END w0_wmask_in[618] + PIN w0_wmask_in[619] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 58.573 84.321 58.627 ; + END + END w0_wmask_in[619] + PIN w0_wmask_in[620] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 58.573 84.609 58.627 ; + END + END w0_wmask_in[620] + PIN w0_wmask_in[621] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 58.573 84.897 58.627 ; + END + END w0_wmask_in[621] + PIN w0_wmask_in[622] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 58.573 85.185 58.627 ; + END + END w0_wmask_in[622] + PIN w0_wmask_in[623] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 58.573 85.473 58.627 ; + END + END w0_wmask_in[623] + PIN w0_wmask_in[624] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 58.573 85.761 58.627 ; + END + END w0_wmask_in[624] + PIN w0_wmask_in[625] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 58.573 86.049 58.627 ; + END + END w0_wmask_in[625] + PIN w0_wmask_in[626] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 58.573 86.337 58.627 ; + END + END w0_wmask_in[626] + PIN w0_wmask_in[627] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 58.573 86.625 58.627 ; + END + END w0_wmask_in[627] + PIN w0_wmask_in[628] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 58.573 86.913 58.627 ; + END + END w0_wmask_in[628] + PIN w0_wmask_in[629] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 58.573 87.201 58.627 ; + END + END w0_wmask_in[629] + PIN w0_wmask_in[630] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 58.573 87.489 58.627 ; + END + END w0_wmask_in[630] + PIN w0_wmask_in[631] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 58.573 87.777 58.627 ; + END + END w0_wmask_in[631] + PIN w0_wmask_in[632] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 58.573 88.065 58.627 ; + END + END w0_wmask_in[632] + PIN w0_wmask_in[633] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 58.573 88.353 58.627 ; + END + END w0_wmask_in[633] + PIN w0_wmask_in[634] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 58.573 88.641 58.627 ; + END + END w0_wmask_in[634] + PIN w0_wmask_in[635] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 58.573 88.929 58.627 ; + END + END w0_wmask_in[635] + PIN w0_wmask_in[636] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 58.573 89.217 58.627 ; + END + END w0_wmask_in[636] + PIN w0_wmask_in[637] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 58.573 89.505 58.627 ; + END + END w0_wmask_in[637] + PIN w0_wmask_in[638] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 58.573 89.793 58.627 ; + END + END w0_wmask_in[638] + PIN w0_wmask_in[639] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 58.573 90.081 58.627 ; + END + END w0_wmask_in[639] + PIN w0_wmask_in[640] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 58.573 90.369 58.627 ; + END + END w0_wmask_in[640] + PIN w0_wmask_in[641] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 58.573 90.657 58.627 ; + END + END w0_wmask_in[641] + PIN w0_wmask_in[642] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 58.573 90.945 58.627 ; + END + END w0_wmask_in[642] + PIN w0_wmask_in[643] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 58.573 91.233 58.627 ; + END + END w0_wmask_in[643] + PIN w0_wmask_in[644] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 58.573 91.521 58.627 ; + END + END w0_wmask_in[644] + PIN w0_wmask_in[645] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 58.573 91.809 58.627 ; + END + END w0_wmask_in[645] + PIN w0_wmask_in[646] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 58.573 92.097 58.627 ; + END + END w0_wmask_in[646] + PIN w0_wmask_in[647] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 58.573 92.385 58.627 ; + END + END w0_wmask_in[647] + PIN w0_wmask_in[648] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 58.573 92.673 58.627 ; + END + END w0_wmask_in[648] + PIN w0_wmask_in[649] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 58.573 92.961 58.627 ; + END + END w0_wmask_in[649] + PIN w0_wmask_in[650] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 58.573 93.249 58.627 ; + END + END w0_wmask_in[650] + PIN w0_wmask_in[651] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 58.573 93.537 58.627 ; + END + END w0_wmask_in[651] + PIN w0_wmask_in[652] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 58.573 93.825 58.627 ; + END + END w0_wmask_in[652] + PIN w0_wmask_in[653] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 58.573 94.113 58.627 ; + END + END w0_wmask_in[653] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.892 0.072 23.916 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.036 0.072 24.060 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.180 0.072 24.204 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.324 0.072 24.348 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.468 0.072 24.492 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.612 0.072 24.636 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.756 0.072 24.780 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.900 0.072 24.924 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.044 0.072 25.068 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.188 0.072 25.212 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.332 0.072 25.356 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.476 0.072 25.500 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.620 0.072 25.644 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.764 0.072 25.788 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.908 0.072 25.932 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.052 0.072 26.076 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.196 0.072 26.220 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.340 0.072 26.364 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.484 0.072 26.508 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.628 0.072 26.652 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.772 0.072 26.796 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.916 0.072 26.940 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.060 0.072 27.084 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.204 0.072 27.228 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.348 0.072 27.372 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.492 0.072 27.516 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.636 0.072 27.660 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.780 0.072 27.804 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.924 0.072 27.948 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.068 0.072 28.092 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.212 0.072 28.236 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.356 0.072 28.380 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.500 0.072 28.524 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.644 0.072 28.668 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.788 0.072 28.812 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.932 0.072 28.956 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.076 0.072 29.100 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.220 0.072 29.244 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.364 0.072 29.388 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.508 0.072 29.532 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.652 0.072 29.676 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.796 0.072 29.820 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.940 0.072 29.964 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.084 0.072 30.108 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.228 0.072 30.252 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.372 0.072 30.396 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.516 0.072 30.540 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.660 0.072 30.684 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.804 0.072 30.828 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.948 0.072 30.972 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.092 0.072 31.116 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.236 0.072 31.260 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.380 0.072 31.404 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.524 0.072 31.548 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.668 0.072 31.692 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.812 0.072 31.836 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.956 0.072 31.980 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.100 0.072 32.124 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.244 0.072 32.268 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.388 0.072 32.412 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.532 0.072 32.556 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.676 0.072 32.700 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.820 0.072 32.844 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.964 0.072 32.988 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.108 0.072 33.132 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.252 0.072 33.276 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.396 0.072 33.420 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.540 0.072 33.564 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.684 0.072 33.708 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.828 0.072 33.852 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.972 0.072 33.996 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.116 0.072 34.140 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.260 0.072 34.284 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.404 0.072 34.428 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.548 0.072 34.572 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.692 0.072 34.716 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.836 0.072 34.860 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.980 0.072 35.004 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.124 0.072 35.148 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.268 0.072 35.292 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.412 0.072 35.436 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.556 0.072 35.580 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.700 0.072 35.724 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.844 0.072 35.868 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.988 0.072 36.012 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.132 0.072 36.156 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.276 0.072 36.300 ; + END + END w0_wd_in[86] + PIN w0_wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.420 0.072 36.444 ; + END + END w0_wd_in[87] + PIN w0_wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.564 0.072 36.588 ; + END + END w0_wd_in[88] + PIN w0_wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.708 0.072 36.732 ; + END + END w0_wd_in[89] + PIN w0_wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.852 0.072 36.876 ; + END + END w0_wd_in[90] + PIN w0_wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.996 0.072 37.020 ; + END + END w0_wd_in[91] + PIN w0_wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.140 0.072 37.164 ; + END + END w0_wd_in[92] + PIN w0_wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.284 0.072 37.308 ; + END + END w0_wd_in[93] + PIN w0_wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.428 0.072 37.452 ; + END + END w0_wd_in[94] + PIN w0_wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.572 0.072 37.596 ; + END + END w0_wd_in[95] + PIN w0_wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.716 0.072 37.740 ; + END + END w0_wd_in[96] + PIN w0_wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.860 0.072 37.884 ; + END + END w0_wd_in[97] + PIN w0_wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.004 0.072 38.028 ; + END + END w0_wd_in[98] + PIN w0_wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.148 0.072 38.172 ; + END + END w0_wd_in[99] + PIN w0_wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.292 0.072 38.316 ; + END + END w0_wd_in[100] + PIN w0_wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.436 0.072 38.460 ; + END + END w0_wd_in[101] + PIN w0_wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.580 0.072 38.604 ; + END + END w0_wd_in[102] + PIN w0_wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.724 0.072 38.748 ; + END + END w0_wd_in[103] + PIN w0_wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.868 0.072 38.892 ; + END + END w0_wd_in[104] + PIN w0_wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.012 0.072 39.036 ; + END + END w0_wd_in[105] + PIN w0_wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.156 0.072 39.180 ; + END + END w0_wd_in[106] + PIN w0_wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.300 0.072 39.324 ; + END + END w0_wd_in[107] + PIN w0_wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.444 0.072 39.468 ; + END + END w0_wd_in[108] + PIN w0_wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.588 0.072 39.612 ; + END + END w0_wd_in[109] + PIN w0_wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.732 0.072 39.756 ; + END + END w0_wd_in[110] + PIN w0_wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.876 0.072 39.900 ; + END + END w0_wd_in[111] + PIN w0_wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.020 0.072 40.044 ; + END + END w0_wd_in[112] + PIN w0_wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.164 0.072 40.188 ; + END + END w0_wd_in[113] + PIN w0_wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.308 0.072 40.332 ; + END + END w0_wd_in[114] + PIN w0_wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.452 0.072 40.476 ; + END + END w0_wd_in[115] + PIN w0_wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.596 0.072 40.620 ; + END + END w0_wd_in[116] + PIN w0_wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.740 0.072 40.764 ; + END + END w0_wd_in[117] + PIN w0_wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.884 0.072 40.908 ; + END + END w0_wd_in[118] + PIN w0_wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.028 0.072 41.052 ; + END + END w0_wd_in[119] + PIN w0_wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.172 0.072 41.196 ; + END + END w0_wd_in[120] + PIN w0_wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.316 0.072 41.340 ; + END + END w0_wd_in[121] + PIN w0_wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.460 0.072 41.484 ; + END + END w0_wd_in[122] + PIN w0_wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.604 0.072 41.628 ; + END + END w0_wd_in[123] + PIN w0_wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.748 0.072 41.772 ; + END + END w0_wd_in[124] + PIN w0_wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.892 0.072 41.916 ; + END + END w0_wd_in[125] + PIN w0_wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.036 0.072 42.060 ; + END + END w0_wd_in[126] + PIN w0_wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.180 0.072 42.204 ; + END + END w0_wd_in[127] + PIN w0_wd_in[128] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.324 0.072 42.348 ; + END + END w0_wd_in[128] + PIN w0_wd_in[129] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.468 0.072 42.492 ; + END + END w0_wd_in[129] + PIN w0_wd_in[130] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.612 0.072 42.636 ; + END + END w0_wd_in[130] + PIN w0_wd_in[131] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.756 0.072 42.780 ; + END + END w0_wd_in[131] + PIN w0_wd_in[132] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.900 0.072 42.924 ; + END + END w0_wd_in[132] + PIN w0_wd_in[133] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.044 0.072 43.068 ; + END + END w0_wd_in[133] + PIN w0_wd_in[134] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.188 0.072 43.212 ; + END + END w0_wd_in[134] + PIN w0_wd_in[135] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.332 0.072 43.356 ; + END + END w0_wd_in[135] + PIN w0_wd_in[136] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.476 0.072 43.500 ; + END + END w0_wd_in[136] + PIN w0_wd_in[137] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.620 0.072 43.644 ; + END + END w0_wd_in[137] + PIN w0_wd_in[138] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.764 0.072 43.788 ; + END + END w0_wd_in[138] + PIN w0_wd_in[139] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.908 0.072 43.932 ; + END + END w0_wd_in[139] + PIN w0_wd_in[140] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.052 0.072 44.076 ; + END + END w0_wd_in[140] + PIN w0_wd_in[141] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.196 0.072 44.220 ; + END + END w0_wd_in[141] + PIN w0_wd_in[142] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.340 0.072 44.364 ; + END + END w0_wd_in[142] + PIN w0_wd_in[143] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.484 0.072 44.508 ; + END + END w0_wd_in[143] + PIN w0_wd_in[144] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.628 0.072 44.652 ; + END + END w0_wd_in[144] + PIN w0_wd_in[145] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.772 0.072 44.796 ; + END + END w0_wd_in[145] + PIN w0_wd_in[146] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.916 0.072 44.940 ; + END + END w0_wd_in[146] + PIN w0_wd_in[147] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.060 0.072 45.084 ; + END + END w0_wd_in[147] + PIN w0_wd_in[148] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.204 0.072 45.228 ; + END + END w0_wd_in[148] + PIN w0_wd_in[149] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.348 0.072 45.372 ; + END + END w0_wd_in[149] + PIN w0_wd_in[150] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.492 0.072 45.516 ; + END + END w0_wd_in[150] + PIN w0_wd_in[151] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.636 0.072 45.660 ; + END + END w0_wd_in[151] + PIN w0_wd_in[152] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.780 0.072 45.804 ; + END + END w0_wd_in[152] + PIN w0_wd_in[153] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.924 0.072 45.948 ; + END + END w0_wd_in[153] + PIN w0_wd_in[154] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.068 0.072 46.092 ; + END + END w0_wd_in[154] + PIN w0_wd_in[155] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.212 0.072 46.236 ; + END + END w0_wd_in[155] + PIN w0_wd_in[156] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.356 0.072 46.380 ; + END + END w0_wd_in[156] + PIN w0_wd_in[157] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.500 0.072 46.524 ; + END + END w0_wd_in[157] + PIN w0_wd_in[158] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.644 0.072 46.668 ; + END + END w0_wd_in[158] + PIN w0_wd_in[159] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.788 0.072 46.812 ; + END + END w0_wd_in[159] + PIN w0_wd_in[160] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.932 0.072 46.956 ; + END + END w0_wd_in[160] + PIN w0_wd_in[161] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.076 0.072 47.100 ; + END + END w0_wd_in[161] + PIN w0_wd_in[162] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.220 0.072 47.244 ; + END + END w0_wd_in[162] + PIN w0_wd_in[163] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.364 0.072 47.388 ; + END + END w0_wd_in[163] + PIN w0_wd_in[164] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.748 208.506 23.772 ; + END + END w0_wd_in[164] + PIN w0_wd_in[165] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 23.892 208.506 23.916 ; + END + END w0_wd_in[165] + PIN w0_wd_in[166] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.036 208.506 24.060 ; + END + END w0_wd_in[166] + PIN w0_wd_in[167] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.180 208.506 24.204 ; + END + END w0_wd_in[167] + PIN w0_wd_in[168] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.324 208.506 24.348 ; + END + END w0_wd_in[168] + PIN w0_wd_in[169] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.468 208.506 24.492 ; + END + END w0_wd_in[169] + PIN w0_wd_in[170] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.612 208.506 24.636 ; + END + END w0_wd_in[170] + PIN w0_wd_in[171] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.756 208.506 24.780 ; + END + END w0_wd_in[171] + PIN w0_wd_in[172] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 24.900 208.506 24.924 ; + END + END w0_wd_in[172] + PIN w0_wd_in[173] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.044 208.506 25.068 ; + END + END w0_wd_in[173] + PIN w0_wd_in[174] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.188 208.506 25.212 ; + END + END w0_wd_in[174] + PIN w0_wd_in[175] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.332 208.506 25.356 ; + END + END w0_wd_in[175] + PIN w0_wd_in[176] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.476 208.506 25.500 ; + END + END w0_wd_in[176] + PIN w0_wd_in[177] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.620 208.506 25.644 ; + END + END w0_wd_in[177] + PIN w0_wd_in[178] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.764 208.506 25.788 ; + END + END w0_wd_in[178] + PIN w0_wd_in[179] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 25.908 208.506 25.932 ; + END + END w0_wd_in[179] + PIN w0_wd_in[180] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.052 208.506 26.076 ; + END + END w0_wd_in[180] + PIN w0_wd_in[181] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.196 208.506 26.220 ; + END + END w0_wd_in[181] + PIN w0_wd_in[182] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.340 208.506 26.364 ; + END + END w0_wd_in[182] + PIN w0_wd_in[183] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.484 208.506 26.508 ; + END + END w0_wd_in[183] + PIN w0_wd_in[184] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.628 208.506 26.652 ; + END + END w0_wd_in[184] + PIN w0_wd_in[185] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.772 208.506 26.796 ; + END + END w0_wd_in[185] + PIN w0_wd_in[186] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 26.916 208.506 26.940 ; + END + END w0_wd_in[186] + PIN w0_wd_in[187] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.060 208.506 27.084 ; + END + END w0_wd_in[187] + PIN w0_wd_in[188] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.204 208.506 27.228 ; + END + END w0_wd_in[188] + PIN w0_wd_in[189] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.348 208.506 27.372 ; + END + END w0_wd_in[189] + PIN w0_wd_in[190] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.492 208.506 27.516 ; + END + END w0_wd_in[190] + PIN w0_wd_in[191] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.636 208.506 27.660 ; + END + END w0_wd_in[191] + PIN w0_wd_in[192] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.780 208.506 27.804 ; + END + END w0_wd_in[192] + PIN w0_wd_in[193] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 27.924 208.506 27.948 ; + END + END w0_wd_in[193] + PIN w0_wd_in[194] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.068 208.506 28.092 ; + END + END w0_wd_in[194] + PIN w0_wd_in[195] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.212 208.506 28.236 ; + END + END w0_wd_in[195] + PIN w0_wd_in[196] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.356 208.506 28.380 ; + END + END w0_wd_in[196] + PIN w0_wd_in[197] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.500 208.506 28.524 ; + END + END w0_wd_in[197] + PIN w0_wd_in[198] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.644 208.506 28.668 ; + END + END w0_wd_in[198] + PIN w0_wd_in[199] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.788 208.506 28.812 ; + END + END w0_wd_in[199] + PIN w0_wd_in[200] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 28.932 208.506 28.956 ; + END + END w0_wd_in[200] + PIN w0_wd_in[201] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.076 208.506 29.100 ; + END + END w0_wd_in[201] + PIN w0_wd_in[202] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.220 208.506 29.244 ; + END + END w0_wd_in[202] + PIN w0_wd_in[203] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.364 208.506 29.388 ; + END + END w0_wd_in[203] + PIN w0_wd_in[204] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.508 208.506 29.532 ; + END + END w0_wd_in[204] + PIN w0_wd_in[205] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.652 208.506 29.676 ; + END + END w0_wd_in[205] + PIN w0_wd_in[206] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.796 208.506 29.820 ; + END + END w0_wd_in[206] + PIN w0_wd_in[207] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 29.940 208.506 29.964 ; + END + END w0_wd_in[207] + PIN w0_wd_in[208] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.084 208.506 30.108 ; + END + END w0_wd_in[208] + PIN w0_wd_in[209] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.228 208.506 30.252 ; + END + END w0_wd_in[209] + PIN w0_wd_in[210] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.372 208.506 30.396 ; + END + END w0_wd_in[210] + PIN w0_wd_in[211] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.516 208.506 30.540 ; + END + END w0_wd_in[211] + PIN w0_wd_in[212] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.660 208.506 30.684 ; + END + END w0_wd_in[212] + PIN w0_wd_in[213] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.804 208.506 30.828 ; + END + END w0_wd_in[213] + PIN w0_wd_in[214] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 30.948 208.506 30.972 ; + END + END w0_wd_in[214] + PIN w0_wd_in[215] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.092 208.506 31.116 ; + END + END w0_wd_in[215] + PIN w0_wd_in[216] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.236 208.506 31.260 ; + END + END w0_wd_in[216] + PIN w0_wd_in[217] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.380 208.506 31.404 ; + END + END w0_wd_in[217] + PIN w0_wd_in[218] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.524 208.506 31.548 ; + END + END w0_wd_in[218] + PIN w0_wd_in[219] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.668 208.506 31.692 ; + END + END w0_wd_in[219] + PIN w0_wd_in[220] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.812 208.506 31.836 ; + END + END w0_wd_in[220] + PIN w0_wd_in[221] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 31.956 208.506 31.980 ; + END + END w0_wd_in[221] + PIN w0_wd_in[222] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.100 208.506 32.124 ; + END + END w0_wd_in[222] + PIN w0_wd_in[223] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.244 208.506 32.268 ; + END + END w0_wd_in[223] + PIN w0_wd_in[224] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.388 208.506 32.412 ; + END + END w0_wd_in[224] + PIN w0_wd_in[225] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.532 208.506 32.556 ; + END + END w0_wd_in[225] + PIN w0_wd_in[226] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.676 208.506 32.700 ; + END + END w0_wd_in[226] + PIN w0_wd_in[227] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.820 208.506 32.844 ; + END + END w0_wd_in[227] + PIN w0_wd_in[228] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 32.964 208.506 32.988 ; + END + END w0_wd_in[228] + PIN w0_wd_in[229] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.108 208.506 33.132 ; + END + END w0_wd_in[229] + PIN w0_wd_in[230] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.252 208.506 33.276 ; + END + END w0_wd_in[230] + PIN w0_wd_in[231] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.396 208.506 33.420 ; + END + END w0_wd_in[231] + PIN w0_wd_in[232] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.540 208.506 33.564 ; + END + END w0_wd_in[232] + PIN w0_wd_in[233] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.684 208.506 33.708 ; + END + END w0_wd_in[233] + PIN w0_wd_in[234] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.828 208.506 33.852 ; + END + END w0_wd_in[234] + PIN w0_wd_in[235] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 33.972 208.506 33.996 ; + END + END w0_wd_in[235] + PIN w0_wd_in[236] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.116 208.506 34.140 ; + END + END w0_wd_in[236] + PIN w0_wd_in[237] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.260 208.506 34.284 ; + END + END w0_wd_in[237] + PIN w0_wd_in[238] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.404 208.506 34.428 ; + END + END w0_wd_in[238] + PIN w0_wd_in[239] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.548 208.506 34.572 ; + END + END w0_wd_in[239] + PIN w0_wd_in[240] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.692 208.506 34.716 ; + END + END w0_wd_in[240] + PIN w0_wd_in[241] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.836 208.506 34.860 ; + END + END w0_wd_in[241] + PIN w0_wd_in[242] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 34.980 208.506 35.004 ; + END + END w0_wd_in[242] + PIN w0_wd_in[243] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.124 208.506 35.148 ; + END + END w0_wd_in[243] + PIN w0_wd_in[244] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.268 208.506 35.292 ; + END + END w0_wd_in[244] + PIN w0_wd_in[245] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.412 208.506 35.436 ; + END + END w0_wd_in[245] + PIN w0_wd_in[246] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.556 208.506 35.580 ; + END + END w0_wd_in[246] + PIN w0_wd_in[247] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.700 208.506 35.724 ; + END + END w0_wd_in[247] + PIN w0_wd_in[248] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.844 208.506 35.868 ; + END + END w0_wd_in[248] + PIN w0_wd_in[249] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 35.988 208.506 36.012 ; + END + END w0_wd_in[249] + PIN w0_wd_in[250] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.132 208.506 36.156 ; + END + END w0_wd_in[250] + PIN w0_wd_in[251] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.276 208.506 36.300 ; + END + END w0_wd_in[251] + PIN w0_wd_in[252] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.420 208.506 36.444 ; + END + END w0_wd_in[252] + PIN w0_wd_in[253] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.564 208.506 36.588 ; + END + END w0_wd_in[253] + PIN w0_wd_in[254] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.708 208.506 36.732 ; + END + END w0_wd_in[254] + PIN w0_wd_in[255] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.852 208.506 36.876 ; + END + END w0_wd_in[255] + PIN w0_wd_in[256] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 36.996 208.506 37.020 ; + END + END w0_wd_in[256] + PIN w0_wd_in[257] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 37.140 208.506 37.164 ; + END + END w0_wd_in[257] + PIN w0_wd_in[258] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 37.284 208.506 37.308 ; + END + END w0_wd_in[258] + PIN w0_wd_in[259] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 37.428 208.506 37.452 ; + END + END w0_wd_in[259] + PIN w0_wd_in[260] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 37.572 208.506 37.596 ; + END + END w0_wd_in[260] + PIN w0_wd_in[261] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 37.716 208.506 37.740 ; + END + END w0_wd_in[261] + PIN w0_wd_in[262] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 37.860 208.506 37.884 ; + END + END w0_wd_in[262] + PIN w0_wd_in[263] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.004 208.506 38.028 ; + END + END w0_wd_in[263] + PIN w0_wd_in[264] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.148 208.506 38.172 ; + END + END w0_wd_in[264] + PIN w0_wd_in[265] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.292 208.506 38.316 ; + END + END w0_wd_in[265] + PIN w0_wd_in[266] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.436 208.506 38.460 ; + END + END w0_wd_in[266] + PIN w0_wd_in[267] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.580 208.506 38.604 ; + END + END w0_wd_in[267] + PIN w0_wd_in[268] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.724 208.506 38.748 ; + END + END w0_wd_in[268] + PIN w0_wd_in[269] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 38.868 208.506 38.892 ; + END + END w0_wd_in[269] + PIN w0_wd_in[270] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.012 208.506 39.036 ; + END + END w0_wd_in[270] + PIN w0_wd_in[271] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.156 208.506 39.180 ; + END + END w0_wd_in[271] + PIN w0_wd_in[272] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.300 208.506 39.324 ; + END + END w0_wd_in[272] + PIN w0_wd_in[273] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.444 208.506 39.468 ; + END + END w0_wd_in[273] + PIN w0_wd_in[274] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.588 208.506 39.612 ; + END + END w0_wd_in[274] + PIN w0_wd_in[275] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.732 208.506 39.756 ; + END + END w0_wd_in[275] + PIN w0_wd_in[276] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 39.876 208.506 39.900 ; + END + END w0_wd_in[276] + PIN w0_wd_in[277] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.020 208.506 40.044 ; + END + END w0_wd_in[277] + PIN w0_wd_in[278] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.164 208.506 40.188 ; + END + END w0_wd_in[278] + PIN w0_wd_in[279] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.308 208.506 40.332 ; + END + END w0_wd_in[279] + PIN w0_wd_in[280] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.452 208.506 40.476 ; + END + END w0_wd_in[280] + PIN w0_wd_in[281] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.596 208.506 40.620 ; + END + END w0_wd_in[281] + PIN w0_wd_in[282] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.740 208.506 40.764 ; + END + END w0_wd_in[282] + PIN w0_wd_in[283] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 40.884 208.506 40.908 ; + END + END w0_wd_in[283] + PIN w0_wd_in[284] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.028 208.506 41.052 ; + END + END w0_wd_in[284] + PIN w0_wd_in[285] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.172 208.506 41.196 ; + END + END w0_wd_in[285] + PIN w0_wd_in[286] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.316 208.506 41.340 ; + END + END w0_wd_in[286] + PIN w0_wd_in[287] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.460 208.506 41.484 ; + END + END w0_wd_in[287] + PIN w0_wd_in[288] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.604 208.506 41.628 ; + END + END w0_wd_in[288] + PIN w0_wd_in[289] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.748 208.506 41.772 ; + END + END w0_wd_in[289] + PIN w0_wd_in[290] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 41.892 208.506 41.916 ; + END + END w0_wd_in[290] + PIN w0_wd_in[291] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.036 208.506 42.060 ; + END + END w0_wd_in[291] + PIN w0_wd_in[292] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.180 208.506 42.204 ; + END + END w0_wd_in[292] + PIN w0_wd_in[293] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.324 208.506 42.348 ; + END + END w0_wd_in[293] + PIN w0_wd_in[294] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.468 208.506 42.492 ; + END + END w0_wd_in[294] + PIN w0_wd_in[295] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.612 208.506 42.636 ; + END + END w0_wd_in[295] + PIN w0_wd_in[296] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.756 208.506 42.780 ; + END + END w0_wd_in[296] + PIN w0_wd_in[297] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 42.900 208.506 42.924 ; + END + END w0_wd_in[297] + PIN w0_wd_in[298] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.044 208.506 43.068 ; + END + END w0_wd_in[298] + PIN w0_wd_in[299] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.188 208.506 43.212 ; + END + END w0_wd_in[299] + PIN w0_wd_in[300] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.332 208.506 43.356 ; + END + END w0_wd_in[300] + PIN w0_wd_in[301] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.476 208.506 43.500 ; + END + END w0_wd_in[301] + PIN w0_wd_in[302] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.620 208.506 43.644 ; + END + END w0_wd_in[302] + PIN w0_wd_in[303] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.764 208.506 43.788 ; + END + END w0_wd_in[303] + PIN w0_wd_in[304] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 43.908 208.506 43.932 ; + END + END w0_wd_in[304] + PIN w0_wd_in[305] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.052 208.506 44.076 ; + END + END w0_wd_in[305] + PIN w0_wd_in[306] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.196 208.506 44.220 ; + END + END w0_wd_in[306] + PIN w0_wd_in[307] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.340 208.506 44.364 ; + END + END w0_wd_in[307] + PIN w0_wd_in[308] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.484 208.506 44.508 ; + END + END w0_wd_in[308] + PIN w0_wd_in[309] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.628 208.506 44.652 ; + END + END w0_wd_in[309] + PIN w0_wd_in[310] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.772 208.506 44.796 ; + END + END w0_wd_in[310] + PIN w0_wd_in[311] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 44.916 208.506 44.940 ; + END + END w0_wd_in[311] + PIN w0_wd_in[312] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.060 208.506 45.084 ; + END + END w0_wd_in[312] + PIN w0_wd_in[313] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.204 208.506 45.228 ; + END + END w0_wd_in[313] + PIN w0_wd_in[314] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.348 208.506 45.372 ; + END + END w0_wd_in[314] + PIN w0_wd_in[315] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.492 208.506 45.516 ; + END + END w0_wd_in[315] + PIN w0_wd_in[316] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.636 208.506 45.660 ; + END + END w0_wd_in[316] + PIN w0_wd_in[317] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.780 208.506 45.804 ; + END + END w0_wd_in[317] + PIN w0_wd_in[318] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 45.924 208.506 45.948 ; + END + END w0_wd_in[318] + PIN w0_wd_in[319] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.068 208.506 46.092 ; + END + END w0_wd_in[319] + PIN w0_wd_in[320] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.212 208.506 46.236 ; + END + END w0_wd_in[320] + PIN w0_wd_in[321] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.356 208.506 46.380 ; + END + END w0_wd_in[321] + PIN w0_wd_in[322] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.500 208.506 46.524 ; + END + END w0_wd_in[322] + PIN w0_wd_in[323] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.644 208.506 46.668 ; + END + END w0_wd_in[323] + PIN w0_wd_in[324] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.788 208.506 46.812 ; + END + END w0_wd_in[324] + PIN w0_wd_in[325] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 46.932 208.506 46.956 ; + END + END w0_wd_in[325] + PIN w0_wd_in[326] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 47.076 208.506 47.100 ; + END + END w0_wd_in[326] + PIN w0_wd_in[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[327] + PIN w0_wd_in[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[328] + PIN w0_wd_in[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[329] + PIN w0_wd_in[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[330] + PIN w0_wd_in[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[331] + PIN w0_wd_in[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[332] + PIN w0_wd_in[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[333] + PIN w0_wd_in[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[334] + PIN w0_wd_in[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[335] + PIN w0_wd_in[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[336] + PIN w0_wd_in[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[337] + PIN w0_wd_in[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[338] + PIN w0_wd_in[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[339] + PIN w0_wd_in[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[340] + PIN w0_wd_in[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[341] + PIN w0_wd_in[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[342] + PIN w0_wd_in[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[343] + PIN w0_wd_in[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[344] + PIN w0_wd_in[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[345] + PIN w0_wd_in[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[346] + PIN w0_wd_in[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[347] + PIN w0_wd_in[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[348] + PIN w0_wd_in[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[349] + PIN w0_wd_in[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[350] + PIN w0_wd_in[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[351] + PIN w0_wd_in[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[352] + PIN w0_wd_in[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[353] + PIN w0_wd_in[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[354] + PIN w0_wd_in[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[355] + PIN w0_wd_in[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[356] + PIN w0_wd_in[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[357] + PIN w0_wd_in[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[358] + PIN w0_wd_in[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[359] + PIN w0_wd_in[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[360] + PIN w0_wd_in[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[361] + PIN w0_wd_in[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[362] + PIN w0_wd_in[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[363] + PIN w0_wd_in[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[364] + PIN w0_wd_in[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[365] + PIN w0_wd_in[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[366] + PIN w0_wd_in[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[367] + PIN w0_wd_in[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[368] + PIN w0_wd_in[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[369] + PIN w0_wd_in[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END w0_wd_in[370] + PIN w0_wd_in[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END w0_wd_in[371] + PIN w0_wd_in[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END w0_wd_in[372] + PIN w0_wd_in[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END w0_wd_in[373] + PIN w0_wd_in[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END w0_wd_in[374] + PIN w0_wd_in[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END w0_wd_in[375] + PIN w0_wd_in[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END w0_wd_in[376] + PIN w0_wd_in[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END w0_wd_in[377] + PIN w0_wd_in[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END w0_wd_in[378] + PIN w0_wd_in[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END w0_wd_in[379] + PIN w0_wd_in[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END w0_wd_in[380] + PIN w0_wd_in[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END w0_wd_in[381] + PIN w0_wd_in[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END w0_wd_in[382] + PIN w0_wd_in[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END w0_wd_in[383] + PIN w0_wd_in[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END w0_wd_in[384] + PIN w0_wd_in[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END w0_wd_in[385] + PIN w0_wd_in[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END w0_wd_in[386] + PIN w0_wd_in[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END w0_wd_in[387] + PIN w0_wd_in[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END w0_wd_in[388] + PIN w0_wd_in[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END w0_wd_in[389] + PIN w0_wd_in[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END w0_wd_in[390] + PIN w0_wd_in[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END w0_wd_in[391] + PIN w0_wd_in[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END w0_wd_in[392] + PIN w0_wd_in[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END w0_wd_in[393] + PIN w0_wd_in[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END w0_wd_in[394] + PIN w0_wd_in[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END w0_wd_in[395] + PIN w0_wd_in[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END w0_wd_in[396] + PIN w0_wd_in[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END w0_wd_in[397] + PIN w0_wd_in[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END w0_wd_in[398] + PIN w0_wd_in[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END w0_wd_in[399] + PIN w0_wd_in[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END w0_wd_in[400] + PIN w0_wd_in[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END w0_wd_in[401] + PIN w0_wd_in[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END w0_wd_in[402] + PIN w0_wd_in[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END w0_wd_in[403] + PIN w0_wd_in[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END w0_wd_in[404] + PIN w0_wd_in[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END w0_wd_in[405] + PIN w0_wd_in[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END w0_wd_in[406] + PIN w0_wd_in[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END w0_wd_in[407] + PIN w0_wd_in[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END w0_wd_in[408] + PIN w0_wd_in[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END w0_wd_in[409] + PIN w0_wd_in[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END w0_wd_in[410] + PIN w0_wd_in[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END w0_wd_in[411] + PIN w0_wd_in[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END w0_wd_in[412] + PIN w0_wd_in[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END w0_wd_in[413] + PIN w0_wd_in[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 0.000 25.281 0.054 ; + END + END w0_wd_in[414] + PIN w0_wd_in[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 0.000 25.569 0.054 ; + END + END w0_wd_in[415] + PIN w0_wd_in[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 0.000 25.857 0.054 ; + END + END w0_wd_in[416] + PIN w0_wd_in[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 0.000 26.145 0.054 ; + END + END w0_wd_in[417] + PIN w0_wd_in[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.415 0.000 26.433 0.054 ; + END + END w0_wd_in[418] + PIN w0_wd_in[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.703 0.000 26.721 0.054 ; + END + END w0_wd_in[419] + PIN w0_wd_in[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.991 0.000 27.009 0.054 ; + END + END w0_wd_in[420] + PIN w0_wd_in[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.279 0.000 27.297 0.054 ; + END + END w0_wd_in[421] + PIN w0_wd_in[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.567 0.000 27.585 0.054 ; + END + END w0_wd_in[422] + PIN w0_wd_in[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 27.855 0.000 27.873 0.054 ; + END + END w0_wd_in[423] + PIN w0_wd_in[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.143 0.000 28.161 0.054 ; + END + END w0_wd_in[424] + PIN w0_wd_in[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.431 0.000 28.449 0.054 ; + END + END w0_wd_in[425] + PIN w0_wd_in[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 28.719 0.000 28.737 0.054 ; + END + END w0_wd_in[426] + PIN w0_wd_in[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.007 0.000 29.025 0.054 ; + END + END w0_wd_in[427] + PIN w0_wd_in[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.295 0.000 29.313 0.054 ; + END + END w0_wd_in[428] + PIN w0_wd_in[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.583 0.000 29.601 0.054 ; + END + END w0_wd_in[429] + PIN w0_wd_in[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 29.871 0.000 29.889 0.054 ; + END + END w0_wd_in[430] + PIN w0_wd_in[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.159 0.000 30.177 0.054 ; + END + END w0_wd_in[431] + PIN w0_wd_in[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.447 0.000 30.465 0.054 ; + END + END w0_wd_in[432] + PIN w0_wd_in[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 30.735 0.000 30.753 0.054 ; + END + END w0_wd_in[433] + PIN w0_wd_in[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.023 0.000 31.041 0.054 ; + END + END w0_wd_in[434] + PIN w0_wd_in[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.311 0.000 31.329 0.054 ; + END + END w0_wd_in[435] + PIN w0_wd_in[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.599 0.000 31.617 0.054 ; + END + END w0_wd_in[436] + PIN w0_wd_in[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 31.887 0.000 31.905 0.054 ; + END + END w0_wd_in[437] + PIN w0_wd_in[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.175 0.000 32.193 0.054 ; + END + END w0_wd_in[438] + PIN w0_wd_in[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.463 0.000 32.481 0.054 ; + END + END w0_wd_in[439] + PIN w0_wd_in[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 32.751 0.000 32.769 0.054 ; + END + END w0_wd_in[440] + PIN w0_wd_in[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.039 0.000 33.057 0.054 ; + END + END w0_wd_in[441] + PIN w0_wd_in[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.327 0.000 33.345 0.054 ; + END + END w0_wd_in[442] + PIN w0_wd_in[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.615 0.000 33.633 0.054 ; + END + END w0_wd_in[443] + PIN w0_wd_in[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 33.903 0.000 33.921 0.054 ; + END + END w0_wd_in[444] + PIN w0_wd_in[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.191 0.000 34.209 0.054 ; + END + END w0_wd_in[445] + PIN w0_wd_in[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.479 0.000 34.497 0.054 ; + END + END w0_wd_in[446] + PIN w0_wd_in[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 34.767 0.000 34.785 0.054 ; + END + END w0_wd_in[447] + PIN w0_wd_in[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.055 0.000 35.073 0.054 ; + END + END w0_wd_in[448] + PIN w0_wd_in[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.343 0.000 35.361 0.054 ; + END + END w0_wd_in[449] + PIN w0_wd_in[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.631 0.000 35.649 0.054 ; + END + END w0_wd_in[450] + PIN w0_wd_in[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 35.919 0.000 35.937 0.054 ; + END + END w0_wd_in[451] + PIN w0_wd_in[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.207 0.000 36.225 0.054 ; + END + END w0_wd_in[452] + PIN w0_wd_in[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.495 0.000 36.513 0.054 ; + END + END w0_wd_in[453] + PIN w0_wd_in[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 36.783 0.000 36.801 0.054 ; + END + END w0_wd_in[454] + PIN w0_wd_in[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.071 0.000 37.089 0.054 ; + END + END w0_wd_in[455] + PIN w0_wd_in[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.359 0.000 37.377 0.054 ; + END + END w0_wd_in[456] + PIN w0_wd_in[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.647 0.000 37.665 0.054 ; + END + END w0_wd_in[457] + PIN w0_wd_in[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 37.935 0.000 37.953 0.054 ; + END + END w0_wd_in[458] + PIN w0_wd_in[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.223 0.000 38.241 0.054 ; + END + END w0_wd_in[459] + PIN w0_wd_in[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.511 0.000 38.529 0.054 ; + END + END w0_wd_in[460] + PIN w0_wd_in[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 38.799 0.000 38.817 0.054 ; + END + END w0_wd_in[461] + PIN w0_wd_in[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.087 0.000 39.105 0.054 ; + END + END w0_wd_in[462] + PIN w0_wd_in[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.375 0.000 39.393 0.054 ; + END + END w0_wd_in[463] + PIN w0_wd_in[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.663 0.000 39.681 0.054 ; + END + END w0_wd_in[464] + PIN w0_wd_in[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 39.951 0.000 39.969 0.054 ; + END + END w0_wd_in[465] + PIN w0_wd_in[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.239 0.000 40.257 0.054 ; + END + END w0_wd_in[466] + PIN w0_wd_in[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.527 0.000 40.545 0.054 ; + END + END w0_wd_in[467] + PIN w0_wd_in[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 40.815 0.000 40.833 0.054 ; + END + END w0_wd_in[468] + PIN w0_wd_in[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.103 0.000 41.121 0.054 ; + END + END w0_wd_in[469] + PIN w0_wd_in[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.391 0.000 41.409 0.054 ; + END + END w0_wd_in[470] + PIN w0_wd_in[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.679 0.000 41.697 0.054 ; + END + END w0_wd_in[471] + PIN w0_wd_in[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 41.967 0.000 41.985 0.054 ; + END + END w0_wd_in[472] + PIN w0_wd_in[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.255 0.000 42.273 0.054 ; + END + END w0_wd_in[473] + PIN w0_wd_in[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.543 0.000 42.561 0.054 ; + END + END w0_wd_in[474] + PIN w0_wd_in[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 42.831 0.000 42.849 0.054 ; + END + END w0_wd_in[475] + PIN w0_wd_in[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.119 0.000 43.137 0.054 ; + END + END w0_wd_in[476] + PIN w0_wd_in[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.407 0.000 43.425 0.054 ; + END + END w0_wd_in[477] + PIN w0_wd_in[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.695 0.000 43.713 0.054 ; + END + END w0_wd_in[478] + PIN w0_wd_in[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 43.983 0.000 44.001 0.054 ; + END + END w0_wd_in[479] + PIN w0_wd_in[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.271 0.000 44.289 0.054 ; + END + END w0_wd_in[480] + PIN w0_wd_in[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.559 0.000 44.577 0.054 ; + END + END w0_wd_in[481] + PIN w0_wd_in[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 44.847 0.000 44.865 0.054 ; + END + END w0_wd_in[482] + PIN w0_wd_in[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.135 0.000 45.153 0.054 ; + END + END w0_wd_in[483] + PIN w0_wd_in[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.423 0.000 45.441 0.054 ; + END + END w0_wd_in[484] + PIN w0_wd_in[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.711 0.000 45.729 0.054 ; + END + END w0_wd_in[485] + PIN w0_wd_in[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 45.999 0.000 46.017 0.054 ; + END + END w0_wd_in[486] + PIN w0_wd_in[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.287 0.000 46.305 0.054 ; + END + END w0_wd_in[487] + PIN w0_wd_in[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.575 0.000 46.593 0.054 ; + END + END w0_wd_in[488] + PIN w0_wd_in[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 46.863 0.000 46.881 0.054 ; + END + END w0_wd_in[489] + PIN w0_wd_in[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.151 0.000 47.169 0.054 ; + END + END w0_wd_in[490] + PIN w0_wd_in[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.439 0.000 47.457 0.054 ; + END + END w0_wd_in[491] + PIN w0_wd_in[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 47.727 0.000 47.745 0.054 ; + END + END w0_wd_in[492] + PIN w0_wd_in[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.015 0.000 48.033 0.054 ; + END + END w0_wd_in[493] + PIN w0_wd_in[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.303 0.000 48.321 0.054 ; + END + END w0_wd_in[494] + PIN w0_wd_in[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.591 0.000 48.609 0.054 ; + END + END w0_wd_in[495] + PIN w0_wd_in[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 48.879 0.000 48.897 0.054 ; + END + END w0_wd_in[496] + PIN w0_wd_in[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.167 0.000 49.185 0.054 ; + END + END w0_wd_in[497] + PIN w0_wd_in[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.455 0.000 49.473 0.054 ; + END + END w0_wd_in[498] + PIN w0_wd_in[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 49.743 0.000 49.761 0.054 ; + END + END w0_wd_in[499] + PIN w0_wd_in[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.031 0.000 50.049 0.054 ; + END + END w0_wd_in[500] + PIN w0_wd_in[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.319 0.000 50.337 0.054 ; + END + END w0_wd_in[501] + PIN w0_wd_in[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.607 0.000 50.625 0.054 ; + END + END w0_wd_in[502] + PIN w0_wd_in[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 50.895 0.000 50.913 0.054 ; + END + END w0_wd_in[503] + PIN w0_wd_in[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.183 0.000 51.201 0.054 ; + END + END w0_wd_in[504] + PIN w0_wd_in[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.471 0.000 51.489 0.054 ; + END + END w0_wd_in[505] + PIN w0_wd_in[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 51.759 0.000 51.777 0.054 ; + END + END w0_wd_in[506] + PIN w0_wd_in[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.047 0.000 52.065 0.054 ; + END + END w0_wd_in[507] + PIN w0_wd_in[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.335 0.000 52.353 0.054 ; + END + END w0_wd_in[508] + PIN w0_wd_in[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.623 0.000 52.641 0.054 ; + END + END w0_wd_in[509] + PIN w0_wd_in[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 52.911 0.000 52.929 0.054 ; + END + END w0_wd_in[510] + PIN w0_wd_in[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.199 0.000 53.217 0.054 ; + END + END w0_wd_in[511] + PIN w0_wd_in[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.487 0.000 53.505 0.054 ; + END + END w0_wd_in[512] + PIN w0_wd_in[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 53.775 0.000 53.793 0.054 ; + END + END w0_wd_in[513] + PIN w0_wd_in[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.063 0.000 54.081 0.054 ; + END + END w0_wd_in[514] + PIN w0_wd_in[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.351 0.000 54.369 0.054 ; + END + END w0_wd_in[515] + PIN w0_wd_in[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.639 0.000 54.657 0.054 ; + END + END w0_wd_in[516] + PIN w0_wd_in[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 54.927 0.000 54.945 0.054 ; + END + END w0_wd_in[517] + PIN w0_wd_in[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.215 0.000 55.233 0.054 ; + END + END w0_wd_in[518] + PIN w0_wd_in[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.503 0.000 55.521 0.054 ; + END + END w0_wd_in[519] + PIN w0_wd_in[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 55.791 0.000 55.809 0.054 ; + END + END w0_wd_in[520] + PIN w0_wd_in[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.079 0.000 56.097 0.054 ; + END + END w0_wd_in[521] + PIN w0_wd_in[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.367 0.000 56.385 0.054 ; + END + END w0_wd_in[522] + PIN w0_wd_in[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.655 0.000 56.673 0.054 ; + END + END w0_wd_in[523] + PIN w0_wd_in[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 56.943 0.000 56.961 0.054 ; + END + END w0_wd_in[524] + PIN w0_wd_in[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.231 0.000 57.249 0.054 ; + END + END w0_wd_in[525] + PIN w0_wd_in[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.519 0.000 57.537 0.054 ; + END + END w0_wd_in[526] + PIN w0_wd_in[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 57.807 0.000 57.825 0.054 ; + END + END w0_wd_in[527] + PIN w0_wd_in[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.095 0.000 58.113 0.054 ; + END + END w0_wd_in[528] + PIN w0_wd_in[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.383 0.000 58.401 0.054 ; + END + END w0_wd_in[529] + PIN w0_wd_in[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.671 0.000 58.689 0.054 ; + END + END w0_wd_in[530] + PIN w0_wd_in[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 58.959 0.000 58.977 0.054 ; + END + END w0_wd_in[531] + PIN w0_wd_in[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.247 0.000 59.265 0.054 ; + END + END w0_wd_in[532] + PIN w0_wd_in[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.535 0.000 59.553 0.054 ; + END + END w0_wd_in[533] + PIN w0_wd_in[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 59.823 0.000 59.841 0.054 ; + END + END w0_wd_in[534] + PIN w0_wd_in[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.111 0.000 60.129 0.054 ; + END + END w0_wd_in[535] + PIN w0_wd_in[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.399 0.000 60.417 0.054 ; + END + END w0_wd_in[536] + PIN w0_wd_in[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.687 0.000 60.705 0.054 ; + END + END w0_wd_in[537] + PIN w0_wd_in[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 60.975 0.000 60.993 0.054 ; + END + END w0_wd_in[538] + PIN w0_wd_in[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.263 0.000 61.281 0.054 ; + END + END w0_wd_in[539] + PIN w0_wd_in[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.551 0.000 61.569 0.054 ; + END + END w0_wd_in[540] + PIN w0_wd_in[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 61.839 0.000 61.857 0.054 ; + END + END w0_wd_in[541] + PIN w0_wd_in[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.127 0.000 62.145 0.054 ; + END + END w0_wd_in[542] + PIN w0_wd_in[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.415 0.000 62.433 0.054 ; + END + END w0_wd_in[543] + PIN w0_wd_in[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.703 0.000 62.721 0.054 ; + END + END w0_wd_in[544] + PIN w0_wd_in[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 62.991 0.000 63.009 0.054 ; + END + END w0_wd_in[545] + PIN w0_wd_in[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.279 0.000 63.297 0.054 ; + END + END w0_wd_in[546] + PIN w0_wd_in[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.567 0.000 63.585 0.054 ; + END + END w0_wd_in[547] + PIN w0_wd_in[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 63.855 0.000 63.873 0.054 ; + END + END w0_wd_in[548] + PIN w0_wd_in[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.143 0.000 64.161 0.054 ; + END + END w0_wd_in[549] + PIN w0_wd_in[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.431 0.000 64.449 0.054 ; + END + END w0_wd_in[550] + PIN w0_wd_in[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 64.719 0.000 64.737 0.054 ; + END + END w0_wd_in[551] + PIN w0_wd_in[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.007 0.000 65.025 0.054 ; + END + END w0_wd_in[552] + PIN w0_wd_in[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.295 0.000 65.313 0.054 ; + END + END w0_wd_in[553] + PIN w0_wd_in[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.583 0.000 65.601 0.054 ; + END + END w0_wd_in[554] + PIN w0_wd_in[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 65.871 0.000 65.889 0.054 ; + END + END w0_wd_in[555] + PIN w0_wd_in[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.159 0.000 66.177 0.054 ; + END + END w0_wd_in[556] + PIN w0_wd_in[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.447 0.000 66.465 0.054 ; + END + END w0_wd_in[557] + PIN w0_wd_in[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 66.735 0.000 66.753 0.054 ; + END + END w0_wd_in[558] + PIN w0_wd_in[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.023 0.000 67.041 0.054 ; + END + END w0_wd_in[559] + PIN w0_wd_in[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.311 0.000 67.329 0.054 ; + END + END w0_wd_in[560] + PIN w0_wd_in[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.599 0.000 67.617 0.054 ; + END + END w0_wd_in[561] + PIN w0_wd_in[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 67.887 0.000 67.905 0.054 ; + END + END w0_wd_in[562] + PIN w0_wd_in[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.175 0.000 68.193 0.054 ; + END + END w0_wd_in[563] + PIN w0_wd_in[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.463 0.000 68.481 0.054 ; + END + END w0_wd_in[564] + PIN w0_wd_in[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 68.751 0.000 68.769 0.054 ; + END + END w0_wd_in[565] + PIN w0_wd_in[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.039 0.000 69.057 0.054 ; + END + END w0_wd_in[566] + PIN w0_wd_in[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.327 0.000 69.345 0.054 ; + END + END w0_wd_in[567] + PIN w0_wd_in[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.615 0.000 69.633 0.054 ; + END + END w0_wd_in[568] + PIN w0_wd_in[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 69.903 0.000 69.921 0.054 ; + END + END w0_wd_in[569] + PIN w0_wd_in[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.191 0.000 70.209 0.054 ; + END + END w0_wd_in[570] + PIN w0_wd_in[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.479 0.000 70.497 0.054 ; + END + END w0_wd_in[571] + PIN w0_wd_in[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 70.767 0.000 70.785 0.054 ; + END + END w0_wd_in[572] + PIN w0_wd_in[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.055 0.000 71.073 0.054 ; + END + END w0_wd_in[573] + PIN w0_wd_in[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.343 0.000 71.361 0.054 ; + END + END w0_wd_in[574] + PIN w0_wd_in[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.631 0.000 71.649 0.054 ; + END + END w0_wd_in[575] + PIN w0_wd_in[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 71.919 0.000 71.937 0.054 ; + END + END w0_wd_in[576] + PIN w0_wd_in[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.207 0.000 72.225 0.054 ; + END + END w0_wd_in[577] + PIN w0_wd_in[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.495 0.000 72.513 0.054 ; + END + END w0_wd_in[578] + PIN w0_wd_in[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 72.783 0.000 72.801 0.054 ; + END + END w0_wd_in[579] + PIN w0_wd_in[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.071 0.000 73.089 0.054 ; + END + END w0_wd_in[580] + PIN w0_wd_in[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.359 0.000 73.377 0.054 ; + END + END w0_wd_in[581] + PIN w0_wd_in[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.647 0.000 73.665 0.054 ; + END + END w0_wd_in[582] + PIN w0_wd_in[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 73.935 0.000 73.953 0.054 ; + END + END w0_wd_in[583] + PIN w0_wd_in[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.223 0.000 74.241 0.054 ; + END + END w0_wd_in[584] + PIN w0_wd_in[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.511 0.000 74.529 0.054 ; + END + END w0_wd_in[585] + PIN w0_wd_in[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 74.799 0.000 74.817 0.054 ; + END + END w0_wd_in[586] + PIN w0_wd_in[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.087 0.000 75.105 0.054 ; + END + END w0_wd_in[587] + PIN w0_wd_in[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.375 0.000 75.393 0.054 ; + END + END w0_wd_in[588] + PIN w0_wd_in[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.663 0.000 75.681 0.054 ; + END + END w0_wd_in[589] + PIN w0_wd_in[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 75.951 0.000 75.969 0.054 ; + END + END w0_wd_in[590] + PIN w0_wd_in[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.239 0.000 76.257 0.054 ; + END + END w0_wd_in[591] + PIN w0_wd_in[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.527 0.000 76.545 0.054 ; + END + END w0_wd_in[592] + PIN w0_wd_in[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 76.815 0.000 76.833 0.054 ; + END + END w0_wd_in[593] + PIN w0_wd_in[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.103 0.000 77.121 0.054 ; + END + END w0_wd_in[594] + PIN w0_wd_in[595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.391 0.000 77.409 0.054 ; + END + END w0_wd_in[595] + PIN w0_wd_in[596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.679 0.000 77.697 0.054 ; + END + END w0_wd_in[596] + PIN w0_wd_in[597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 77.967 0.000 77.985 0.054 ; + END + END w0_wd_in[597] + PIN w0_wd_in[598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.255 0.000 78.273 0.054 ; + END + END w0_wd_in[598] + PIN w0_wd_in[599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.543 0.000 78.561 0.054 ; + END + END w0_wd_in[599] + PIN w0_wd_in[600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 78.831 0.000 78.849 0.054 ; + END + END w0_wd_in[600] + PIN w0_wd_in[601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.119 0.000 79.137 0.054 ; + END + END w0_wd_in[601] + PIN w0_wd_in[602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.407 0.000 79.425 0.054 ; + END + END w0_wd_in[602] + PIN w0_wd_in[603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.695 0.000 79.713 0.054 ; + END + END w0_wd_in[603] + PIN w0_wd_in[604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 79.983 0.000 80.001 0.054 ; + END + END w0_wd_in[604] + PIN w0_wd_in[605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.271 0.000 80.289 0.054 ; + END + END w0_wd_in[605] + PIN w0_wd_in[606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.559 0.000 80.577 0.054 ; + END + END w0_wd_in[606] + PIN w0_wd_in[607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 80.847 0.000 80.865 0.054 ; + END + END w0_wd_in[607] + PIN w0_wd_in[608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.135 0.000 81.153 0.054 ; + END + END w0_wd_in[608] + PIN w0_wd_in[609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.423 0.000 81.441 0.054 ; + END + END w0_wd_in[609] + PIN w0_wd_in[610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.711 0.000 81.729 0.054 ; + END + END w0_wd_in[610] + PIN w0_wd_in[611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 81.999 0.000 82.017 0.054 ; + END + END w0_wd_in[611] + PIN w0_wd_in[612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.287 0.000 82.305 0.054 ; + END + END w0_wd_in[612] + PIN w0_wd_in[613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.575 0.000 82.593 0.054 ; + END + END w0_wd_in[613] + PIN w0_wd_in[614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 82.863 0.000 82.881 0.054 ; + END + END w0_wd_in[614] + PIN w0_wd_in[615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.151 0.000 83.169 0.054 ; + END + END w0_wd_in[615] + PIN w0_wd_in[616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.439 0.000 83.457 0.054 ; + END + END w0_wd_in[616] + PIN w0_wd_in[617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 83.727 0.000 83.745 0.054 ; + END + END w0_wd_in[617] + PIN w0_wd_in[618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.015 0.000 84.033 0.054 ; + END + END w0_wd_in[618] + PIN w0_wd_in[619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.303 0.000 84.321 0.054 ; + END + END w0_wd_in[619] + PIN w0_wd_in[620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.591 0.000 84.609 0.054 ; + END + END w0_wd_in[620] + PIN w0_wd_in[621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 84.879 0.000 84.897 0.054 ; + END + END w0_wd_in[621] + PIN w0_wd_in[622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.167 0.000 85.185 0.054 ; + END + END w0_wd_in[622] + PIN w0_wd_in[623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.455 0.000 85.473 0.054 ; + END + END w0_wd_in[623] + PIN w0_wd_in[624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 85.743 0.000 85.761 0.054 ; + END + END w0_wd_in[624] + PIN w0_wd_in[625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.031 0.000 86.049 0.054 ; + END + END w0_wd_in[625] + PIN w0_wd_in[626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.319 0.000 86.337 0.054 ; + END + END w0_wd_in[626] + PIN w0_wd_in[627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.607 0.000 86.625 0.054 ; + END + END w0_wd_in[627] + PIN w0_wd_in[628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 86.895 0.000 86.913 0.054 ; + END + END w0_wd_in[628] + PIN w0_wd_in[629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.183 0.000 87.201 0.054 ; + END + END w0_wd_in[629] + PIN w0_wd_in[630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.471 0.000 87.489 0.054 ; + END + END w0_wd_in[630] + PIN w0_wd_in[631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 87.759 0.000 87.777 0.054 ; + END + END w0_wd_in[631] + PIN w0_wd_in[632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.047 0.000 88.065 0.054 ; + END + END w0_wd_in[632] + PIN w0_wd_in[633] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.335 0.000 88.353 0.054 ; + END + END w0_wd_in[633] + PIN w0_wd_in[634] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.623 0.000 88.641 0.054 ; + END + END w0_wd_in[634] + PIN w0_wd_in[635] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 88.911 0.000 88.929 0.054 ; + END + END w0_wd_in[635] + PIN w0_wd_in[636] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.199 0.000 89.217 0.054 ; + END + END w0_wd_in[636] + PIN w0_wd_in[637] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.487 0.000 89.505 0.054 ; + END + END w0_wd_in[637] + PIN w0_wd_in[638] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 89.775 0.000 89.793 0.054 ; + END + END w0_wd_in[638] + PIN w0_wd_in[639] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.063 0.000 90.081 0.054 ; + END + END w0_wd_in[639] + PIN w0_wd_in[640] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.351 0.000 90.369 0.054 ; + END + END w0_wd_in[640] + PIN w0_wd_in[641] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.639 0.000 90.657 0.054 ; + END + END w0_wd_in[641] + PIN w0_wd_in[642] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 90.927 0.000 90.945 0.054 ; + END + END w0_wd_in[642] + PIN w0_wd_in[643] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.215 0.000 91.233 0.054 ; + END + END w0_wd_in[643] + PIN w0_wd_in[644] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.503 0.000 91.521 0.054 ; + END + END w0_wd_in[644] + PIN w0_wd_in[645] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 91.791 0.000 91.809 0.054 ; + END + END w0_wd_in[645] + PIN w0_wd_in[646] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.079 0.000 92.097 0.054 ; + END + END w0_wd_in[646] + PIN w0_wd_in[647] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.367 0.000 92.385 0.054 ; + END + END w0_wd_in[647] + PIN w0_wd_in[648] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.655 0.000 92.673 0.054 ; + END + END w0_wd_in[648] + PIN w0_wd_in[649] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 92.943 0.000 92.961 0.054 ; + END + END w0_wd_in[649] + PIN w0_wd_in[650] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.231 0.000 93.249 0.054 ; + END + END w0_wd_in[650] + PIN w0_wd_in[651] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.519 0.000 93.537 0.054 ; + END + END w0_wd_in[651] + PIN w0_wd_in[652] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 93.807 0.000 93.825 0.054 ; + END + END w0_wd_in[652] + PIN w0_wd_in[653] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.095 0.000 94.113 0.054 ; + END + END w0_wd_in[653] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 0.000 94.401 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 0.000 94.689 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 0.000 94.977 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 0.000 95.265 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 0.000 95.553 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 0.000 95.841 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 0.000 96.129 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 0.000 96.417 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 0.000 96.705 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 0.000 96.993 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 0.000 97.281 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 0.000 97.569 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 0.000 97.857 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 0.000 98.145 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 0.000 98.433 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 0.000 98.721 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 0.000 99.009 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 0.000 99.297 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 0.000 99.585 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 0.000 99.873 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 0.000 100.161 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 0.000 100.449 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 0.000 100.737 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 0.000 101.025 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 0.000 101.313 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 0.000 101.601 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 0.000 101.889 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 0.000 102.177 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 0.000 102.465 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 0.000 102.753 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 0.000 103.041 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 0.000 103.329 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 0.000 103.617 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 0.000 103.905 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 0.000 104.193 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 0.000 104.481 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 0.000 104.769 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 0.000 105.057 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 0.000 105.345 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 0.000 105.633 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 0.000 105.921 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 0.000 106.209 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 0.000 106.497 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 0.000 106.785 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 0.000 107.073 0.054 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 0.000 107.361 0.054 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 0.000 107.649 0.054 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 0.000 107.937 0.054 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 0.000 108.225 0.054 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 0.000 108.513 0.054 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 0.000 108.801 0.054 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 0.000 109.089 0.054 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 0.000 109.377 0.054 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 0.000 109.665 0.054 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 0.000 109.953 0.054 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 0.000 110.241 0.054 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 0.000 110.529 0.054 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 0.000 110.817 0.054 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 0.000 111.105 0.054 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 0.000 111.393 0.054 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 0.000 111.681 0.054 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 0.000 111.969 0.054 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 0.000 112.257 0.054 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 0.000 112.545 0.054 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 0.000 112.833 0.054 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 0.000 113.121 0.054 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 0.000 113.409 0.054 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 0.000 113.697 0.054 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 0.000 113.985 0.054 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 0.000 114.273 0.054 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 0.000 114.561 0.054 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 0.000 114.849 0.054 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 0.000 115.137 0.054 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 0.000 115.425 0.054 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 0.000 115.713 0.054 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 0.000 116.001 0.054 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 0.000 116.289 0.054 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 0.000 116.577 0.054 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 0.000 116.865 0.054 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 0.000 117.153 0.054 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 0.000 117.441 0.054 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 0.000 117.729 0.054 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 0.000 118.017 0.054 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 0.000 118.305 0.054 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 0.000 118.593 0.054 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 0.000 118.881 0.054 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 0.000 119.169 0.054 ; + END + END r0_rd_out[86] + PIN r0_rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 0.000 119.457 0.054 ; + END + END r0_rd_out[87] + PIN r0_rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 0.000 119.745 0.054 ; + END + END r0_rd_out[88] + PIN r0_rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 0.000 120.033 0.054 ; + END + END r0_rd_out[89] + PIN r0_rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 0.000 120.321 0.054 ; + END + END r0_rd_out[90] + PIN r0_rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 0.000 120.609 0.054 ; + END + END r0_rd_out[91] + PIN r0_rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 0.000 120.897 0.054 ; + END + END r0_rd_out[92] + PIN r0_rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 0.000 121.185 0.054 ; + END + END r0_rd_out[93] + PIN r0_rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 0.000 121.473 0.054 ; + END + END r0_rd_out[94] + PIN r0_rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 0.000 121.761 0.054 ; + END + END r0_rd_out[95] + PIN r0_rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 0.000 122.049 0.054 ; + END + END r0_rd_out[96] + PIN r0_rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 0.000 122.337 0.054 ; + END + END r0_rd_out[97] + PIN r0_rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 0.000 122.625 0.054 ; + END + END r0_rd_out[98] + PIN r0_rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 0.000 122.913 0.054 ; + END + END r0_rd_out[99] + PIN r0_rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 0.000 123.201 0.054 ; + END + END r0_rd_out[100] + PIN r0_rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 0.000 123.489 0.054 ; + END + END r0_rd_out[101] + PIN r0_rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 0.000 123.777 0.054 ; + END + END r0_rd_out[102] + PIN r0_rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 0.000 124.065 0.054 ; + END + END r0_rd_out[103] + PIN r0_rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 0.000 124.353 0.054 ; + END + END r0_rd_out[104] + PIN r0_rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 0.000 124.641 0.054 ; + END + END r0_rd_out[105] + PIN r0_rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 0.000 124.929 0.054 ; + END + END r0_rd_out[106] + PIN r0_rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 0.000 125.217 0.054 ; + END + END r0_rd_out[107] + PIN r0_rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 0.000 125.505 0.054 ; + END + END r0_rd_out[108] + PIN r0_rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 0.000 125.793 0.054 ; + END + END r0_rd_out[109] + PIN r0_rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 0.000 126.081 0.054 ; + END + END r0_rd_out[110] + PIN r0_rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 0.000 126.369 0.054 ; + END + END r0_rd_out[111] + PIN r0_rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 0.000 126.657 0.054 ; + END + END r0_rd_out[112] + PIN r0_rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 0.000 126.945 0.054 ; + END + END r0_rd_out[113] + PIN r0_rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 0.000 127.233 0.054 ; + END + END r0_rd_out[114] + PIN r0_rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 0.000 127.521 0.054 ; + END + END r0_rd_out[115] + PIN r0_rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 0.000 127.809 0.054 ; + END + END r0_rd_out[116] + PIN r0_rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 0.000 128.097 0.054 ; + END + END r0_rd_out[117] + PIN r0_rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 0.000 128.385 0.054 ; + END + END r0_rd_out[118] + PIN r0_rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 0.000 128.673 0.054 ; + END + END r0_rd_out[119] + PIN r0_rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 0.000 128.961 0.054 ; + END + END r0_rd_out[120] + PIN r0_rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 0.000 129.249 0.054 ; + END + END r0_rd_out[121] + PIN r0_rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 0.000 129.537 0.054 ; + END + END r0_rd_out[122] + PIN r0_rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 0.000 129.825 0.054 ; + END + END r0_rd_out[123] + PIN r0_rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 0.000 130.113 0.054 ; + END + END r0_rd_out[124] + PIN r0_rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 0.000 130.401 0.054 ; + END + END r0_rd_out[125] + PIN r0_rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 0.000 130.689 0.054 ; + END + END r0_rd_out[126] + PIN r0_rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 0.000 130.977 0.054 ; + END + END r0_rd_out[127] + PIN r0_rd_out[128] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 0.000 131.265 0.054 ; + END + END r0_rd_out[128] + PIN r0_rd_out[129] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 0.000 131.553 0.054 ; + END + END r0_rd_out[129] + PIN r0_rd_out[130] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 0.000 131.841 0.054 ; + END + END r0_rd_out[130] + PIN r0_rd_out[131] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 0.000 132.129 0.054 ; + END + END r0_rd_out[131] + PIN r0_rd_out[132] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 0.000 132.417 0.054 ; + END + END r0_rd_out[132] + PIN r0_rd_out[133] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 0.000 132.705 0.054 ; + END + END r0_rd_out[133] + PIN r0_rd_out[134] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 0.000 132.993 0.054 ; + END + END r0_rd_out[134] + PIN r0_rd_out[135] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 0.000 133.281 0.054 ; + END + END r0_rd_out[135] + PIN r0_rd_out[136] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 0.000 133.569 0.054 ; + END + END r0_rd_out[136] + PIN r0_rd_out[137] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 0.000 133.857 0.054 ; + END + END r0_rd_out[137] + PIN r0_rd_out[138] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 0.000 134.145 0.054 ; + END + END r0_rd_out[138] + PIN r0_rd_out[139] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 0.000 134.433 0.054 ; + END + END r0_rd_out[139] + PIN r0_rd_out[140] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 0.000 134.721 0.054 ; + END + END r0_rd_out[140] + PIN r0_rd_out[141] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 0.000 135.009 0.054 ; + END + END r0_rd_out[141] + PIN r0_rd_out[142] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 0.000 135.297 0.054 ; + END + END r0_rd_out[142] + PIN r0_rd_out[143] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 0.000 135.585 0.054 ; + END + END r0_rd_out[143] + PIN r0_rd_out[144] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 0.000 135.873 0.054 ; + END + END r0_rd_out[144] + PIN r0_rd_out[145] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 0.000 136.161 0.054 ; + END + END r0_rd_out[145] + PIN r0_rd_out[146] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 0.000 136.449 0.054 ; + END + END r0_rd_out[146] + PIN r0_rd_out[147] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 0.000 136.737 0.054 ; + END + END r0_rd_out[147] + PIN r0_rd_out[148] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 0.000 137.025 0.054 ; + END + END r0_rd_out[148] + PIN r0_rd_out[149] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 0.000 137.313 0.054 ; + END + END r0_rd_out[149] + PIN r0_rd_out[150] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 0.000 137.601 0.054 ; + END + END r0_rd_out[150] + PIN r0_rd_out[151] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 0.000 137.889 0.054 ; + END + END r0_rd_out[151] + PIN r0_rd_out[152] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 0.000 138.177 0.054 ; + END + END r0_rd_out[152] + PIN r0_rd_out[153] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 0.000 138.465 0.054 ; + END + END r0_rd_out[153] + PIN r0_rd_out[154] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 0.000 138.753 0.054 ; + END + END r0_rd_out[154] + PIN r0_rd_out[155] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 0.000 139.041 0.054 ; + END + END r0_rd_out[155] + PIN r0_rd_out[156] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 0.000 139.329 0.054 ; + END + END r0_rd_out[156] + PIN r0_rd_out[157] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 0.000 139.617 0.054 ; + END + END r0_rd_out[157] + PIN r0_rd_out[158] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 0.000 139.905 0.054 ; + END + END r0_rd_out[158] + PIN r0_rd_out[159] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 0.000 140.193 0.054 ; + END + END r0_rd_out[159] + PIN r0_rd_out[160] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 0.000 140.481 0.054 ; + END + END r0_rd_out[160] + PIN r0_rd_out[161] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 0.000 140.769 0.054 ; + END + END r0_rd_out[161] + PIN r0_rd_out[162] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 0.000 141.057 0.054 ; + END + END r0_rd_out[162] + PIN r0_rd_out[163] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 0.000 141.345 0.054 ; + END + END r0_rd_out[163] + PIN r0_rd_out[164] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 0.000 141.633 0.054 ; + END + END r0_rd_out[164] + PIN r0_rd_out[165] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 0.000 141.921 0.054 ; + END + END r0_rd_out[165] + PIN r0_rd_out[166] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 0.000 142.209 0.054 ; + END + END r0_rd_out[166] + PIN r0_rd_out[167] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 0.000 142.497 0.054 ; + END + END r0_rd_out[167] + PIN r0_rd_out[168] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 0.000 142.785 0.054 ; + END + END r0_rd_out[168] + PIN r0_rd_out[169] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 0.000 143.073 0.054 ; + END + END r0_rd_out[169] + PIN r0_rd_out[170] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 0.000 143.361 0.054 ; + END + END r0_rd_out[170] + PIN r0_rd_out[171] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 0.000 143.649 0.054 ; + END + END r0_rd_out[171] + PIN r0_rd_out[172] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 0.000 143.937 0.054 ; + END + END r0_rd_out[172] + PIN r0_rd_out[173] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 0.000 144.225 0.054 ; + END + END r0_rd_out[173] + PIN r0_rd_out[174] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 0.000 144.513 0.054 ; + END + END r0_rd_out[174] + PIN r0_rd_out[175] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 0.000 144.801 0.054 ; + END + END r0_rd_out[175] + PIN r0_rd_out[176] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 0.000 145.089 0.054 ; + END + END r0_rd_out[176] + PIN r0_rd_out[177] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 0.000 145.377 0.054 ; + END + END r0_rd_out[177] + PIN r0_rd_out[178] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 0.000 145.665 0.054 ; + END + END r0_rd_out[178] + PIN r0_rd_out[179] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 0.000 145.953 0.054 ; + END + END r0_rd_out[179] + PIN r0_rd_out[180] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 0.000 146.241 0.054 ; + END + END r0_rd_out[180] + PIN r0_rd_out[181] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 0.000 146.529 0.054 ; + END + END r0_rd_out[181] + PIN r0_rd_out[182] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 0.000 146.817 0.054 ; + END + END r0_rd_out[182] + PIN r0_rd_out[183] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 0.000 147.105 0.054 ; + END + END r0_rd_out[183] + PIN r0_rd_out[184] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 0.000 147.393 0.054 ; + END + END r0_rd_out[184] + PIN r0_rd_out[185] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 0.000 147.681 0.054 ; + END + END r0_rd_out[185] + PIN r0_rd_out[186] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 0.000 147.969 0.054 ; + END + END r0_rd_out[186] + PIN r0_rd_out[187] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 0.000 148.257 0.054 ; + END + END r0_rd_out[187] + PIN r0_rd_out[188] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 0.000 148.545 0.054 ; + END + END r0_rd_out[188] + PIN r0_rd_out[189] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 0.000 148.833 0.054 ; + END + END r0_rd_out[189] + PIN r0_rd_out[190] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 0.000 149.121 0.054 ; + END + END r0_rd_out[190] + PIN r0_rd_out[191] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 0.000 149.409 0.054 ; + END + END r0_rd_out[191] + PIN r0_rd_out[192] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 0.000 149.697 0.054 ; + END + END r0_rd_out[192] + PIN r0_rd_out[193] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 0.000 149.985 0.054 ; + END + END r0_rd_out[193] + PIN r0_rd_out[194] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 0.000 150.273 0.054 ; + END + END r0_rd_out[194] + PIN r0_rd_out[195] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 0.000 150.561 0.054 ; + END + END r0_rd_out[195] + PIN r0_rd_out[196] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 0.000 150.849 0.054 ; + END + END r0_rd_out[196] + PIN r0_rd_out[197] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 0.000 151.137 0.054 ; + END + END r0_rd_out[197] + PIN r0_rd_out[198] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 0.000 151.425 0.054 ; + END + END r0_rd_out[198] + PIN r0_rd_out[199] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 0.000 151.713 0.054 ; + END + END r0_rd_out[199] + PIN r0_rd_out[200] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 0.000 152.001 0.054 ; + END + END r0_rd_out[200] + PIN r0_rd_out[201] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 0.000 152.289 0.054 ; + END + END r0_rd_out[201] + PIN r0_rd_out[202] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 0.000 152.577 0.054 ; + END + END r0_rd_out[202] + PIN r0_rd_out[203] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 0.000 152.865 0.054 ; + END + END r0_rd_out[203] + PIN r0_rd_out[204] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 0.000 153.153 0.054 ; + END + END r0_rd_out[204] + PIN r0_rd_out[205] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 0.000 153.441 0.054 ; + END + END r0_rd_out[205] + PIN r0_rd_out[206] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 0.000 153.729 0.054 ; + END + END r0_rd_out[206] + PIN r0_rd_out[207] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 0.000 154.017 0.054 ; + END + END r0_rd_out[207] + PIN r0_rd_out[208] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 0.000 154.305 0.054 ; + END + END r0_rd_out[208] + PIN r0_rd_out[209] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 0.000 154.593 0.054 ; + END + END r0_rd_out[209] + PIN r0_rd_out[210] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 0.000 154.881 0.054 ; + END + END r0_rd_out[210] + PIN r0_rd_out[211] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 0.000 155.169 0.054 ; + END + END r0_rd_out[211] + PIN r0_rd_out[212] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 0.000 155.457 0.054 ; + END + END r0_rd_out[212] + PIN r0_rd_out[213] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 0.000 155.745 0.054 ; + END + END r0_rd_out[213] + PIN r0_rd_out[214] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 0.000 156.033 0.054 ; + END + END r0_rd_out[214] + PIN r0_rd_out[215] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 0.000 156.321 0.054 ; + END + END r0_rd_out[215] + PIN r0_rd_out[216] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 0.000 156.609 0.054 ; + END + END r0_rd_out[216] + PIN r0_rd_out[217] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 0.000 156.897 0.054 ; + END + END r0_rd_out[217] + PIN r0_rd_out[218] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 0.000 157.185 0.054 ; + END + END r0_rd_out[218] + PIN r0_rd_out[219] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 0.000 157.473 0.054 ; + END + END r0_rd_out[219] + PIN r0_rd_out[220] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 0.000 157.761 0.054 ; + END + END r0_rd_out[220] + PIN r0_rd_out[221] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 0.000 158.049 0.054 ; + END + END r0_rd_out[221] + PIN r0_rd_out[222] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 0.000 158.337 0.054 ; + END + END r0_rd_out[222] + PIN r0_rd_out[223] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 0.000 158.625 0.054 ; + END + END r0_rd_out[223] + PIN r0_rd_out[224] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 0.000 158.913 0.054 ; + END + END r0_rd_out[224] + PIN r0_rd_out[225] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 0.000 159.201 0.054 ; + END + END r0_rd_out[225] + PIN r0_rd_out[226] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 0.000 159.489 0.054 ; + END + END r0_rd_out[226] + PIN r0_rd_out[227] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 0.000 159.777 0.054 ; + END + END r0_rd_out[227] + PIN r0_rd_out[228] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 0.000 160.065 0.054 ; + END + END r0_rd_out[228] + PIN r0_rd_out[229] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 0.000 160.353 0.054 ; + END + END r0_rd_out[229] + PIN r0_rd_out[230] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 0.000 160.641 0.054 ; + END + END r0_rd_out[230] + PIN r0_rd_out[231] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 0.000 160.929 0.054 ; + END + END r0_rd_out[231] + PIN r0_rd_out[232] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 0.000 161.217 0.054 ; + END + END r0_rd_out[232] + PIN r0_rd_out[233] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 0.000 161.505 0.054 ; + END + END r0_rd_out[233] + PIN r0_rd_out[234] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 0.000 161.793 0.054 ; + END + END r0_rd_out[234] + PIN r0_rd_out[235] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 0.000 162.081 0.054 ; + END + END r0_rd_out[235] + PIN r0_rd_out[236] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 0.000 162.369 0.054 ; + END + END r0_rd_out[236] + PIN r0_rd_out[237] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 0.000 162.657 0.054 ; + END + END r0_rd_out[237] + PIN r0_rd_out[238] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 0.000 162.945 0.054 ; + END + END r0_rd_out[238] + PIN r0_rd_out[239] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.215 0.000 163.233 0.054 ; + END + END r0_rd_out[239] + PIN r0_rd_out[240] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.503 0.000 163.521 0.054 ; + END + END r0_rd_out[240] + PIN r0_rd_out[241] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.791 0.000 163.809 0.054 ; + END + END r0_rd_out[241] + PIN r0_rd_out[242] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.079 0.000 164.097 0.054 ; + END + END r0_rd_out[242] + PIN r0_rd_out[243] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 0.000 164.385 0.054 ; + END + END r0_rd_out[243] + PIN r0_rd_out[244] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.655 0.000 164.673 0.054 ; + END + END r0_rd_out[244] + PIN r0_rd_out[245] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.943 0.000 164.961 0.054 ; + END + END r0_rd_out[245] + PIN r0_rd_out[246] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.231 0.000 165.249 0.054 ; + END + END r0_rd_out[246] + PIN r0_rd_out[247] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.519 0.000 165.537 0.054 ; + END + END r0_rd_out[247] + PIN r0_rd_out[248] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 0.000 165.825 0.054 ; + END + END r0_rd_out[248] + PIN r0_rd_out[249] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.095 0.000 166.113 0.054 ; + END + END r0_rd_out[249] + PIN r0_rd_out[250] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.383 0.000 166.401 0.054 ; + END + END r0_rd_out[250] + PIN r0_rd_out[251] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.671 0.000 166.689 0.054 ; + END + END r0_rd_out[251] + PIN r0_rd_out[252] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.959 0.000 166.977 0.054 ; + END + END r0_rd_out[252] + PIN r0_rd_out[253] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 0.000 167.265 0.054 ; + END + END r0_rd_out[253] + PIN r0_rd_out[254] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.535 0.000 167.553 0.054 ; + END + END r0_rd_out[254] + PIN r0_rd_out[255] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.823 0.000 167.841 0.054 ; + END + END r0_rd_out[255] + PIN r0_rd_out[256] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.111 0.000 168.129 0.054 ; + END + END r0_rd_out[256] + PIN r0_rd_out[257] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.399 0.000 168.417 0.054 ; + END + END r0_rd_out[257] + PIN r0_rd_out[258] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 0.000 168.705 0.054 ; + END + END r0_rd_out[258] + PIN r0_rd_out[259] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.975 0.000 168.993 0.054 ; + END + END r0_rd_out[259] + PIN r0_rd_out[260] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.263 0.000 169.281 0.054 ; + END + END r0_rd_out[260] + PIN r0_rd_out[261] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.551 0.000 169.569 0.054 ; + END + END r0_rd_out[261] + PIN r0_rd_out[262] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.839 0.000 169.857 0.054 ; + END + END r0_rd_out[262] + PIN r0_rd_out[263] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 0.000 170.145 0.054 ; + END + END r0_rd_out[263] + PIN r0_rd_out[264] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.415 0.000 170.433 0.054 ; + END + END r0_rd_out[264] + PIN r0_rd_out[265] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.703 0.000 170.721 0.054 ; + END + END r0_rd_out[265] + PIN r0_rd_out[266] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.991 0.000 171.009 0.054 ; + END + END r0_rd_out[266] + PIN r0_rd_out[267] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.279 0.000 171.297 0.054 ; + END + END r0_rd_out[267] + PIN r0_rd_out[268] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 0.000 171.585 0.054 ; + END + END r0_rd_out[268] + PIN r0_rd_out[269] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.855 0.000 171.873 0.054 ; + END + END r0_rd_out[269] + PIN r0_rd_out[270] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.143 0.000 172.161 0.054 ; + END + END r0_rd_out[270] + PIN r0_rd_out[271] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.431 0.000 172.449 0.054 ; + END + END r0_rd_out[271] + PIN r0_rd_out[272] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.719 0.000 172.737 0.054 ; + END + END r0_rd_out[272] + PIN r0_rd_out[273] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.007 0.000 173.025 0.054 ; + END + END r0_rd_out[273] + PIN r0_rd_out[274] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.295 0.000 173.313 0.054 ; + END + END r0_rd_out[274] + PIN r0_rd_out[275] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.583 0.000 173.601 0.054 ; + END + END r0_rd_out[275] + PIN r0_rd_out[276] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.871 0.000 173.889 0.054 ; + END + END r0_rd_out[276] + PIN r0_rd_out[277] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.159 0.000 174.177 0.054 ; + END + END r0_rd_out[277] + PIN r0_rd_out[278] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.447 0.000 174.465 0.054 ; + END + END r0_rd_out[278] + PIN r0_rd_out[279] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.735 0.000 174.753 0.054 ; + END + END r0_rd_out[279] + PIN r0_rd_out[280] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.023 0.000 175.041 0.054 ; + END + END r0_rd_out[280] + PIN r0_rd_out[281] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.311 0.000 175.329 0.054 ; + END + END r0_rd_out[281] + PIN r0_rd_out[282] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.599 0.000 175.617 0.054 ; + END + END r0_rd_out[282] + PIN r0_rd_out[283] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.887 0.000 175.905 0.054 ; + END + END r0_rd_out[283] + PIN r0_rd_out[284] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.175 0.000 176.193 0.054 ; + END + END r0_rd_out[284] + PIN r0_rd_out[285] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.463 0.000 176.481 0.054 ; + END + END r0_rd_out[285] + PIN r0_rd_out[286] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.751 0.000 176.769 0.054 ; + END + END r0_rd_out[286] + PIN r0_rd_out[287] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.039 0.000 177.057 0.054 ; + END + END r0_rd_out[287] + PIN r0_rd_out[288] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.327 0.000 177.345 0.054 ; + END + END r0_rd_out[288] + PIN r0_rd_out[289] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.615 0.000 177.633 0.054 ; + END + END r0_rd_out[289] + PIN r0_rd_out[290] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.903 0.000 177.921 0.054 ; + END + END r0_rd_out[290] + PIN r0_rd_out[291] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.191 0.000 178.209 0.054 ; + END + END r0_rd_out[291] + PIN r0_rd_out[292] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.479 0.000 178.497 0.054 ; + END + END r0_rd_out[292] + PIN r0_rd_out[293] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.767 0.000 178.785 0.054 ; + END + END r0_rd_out[293] + PIN r0_rd_out[294] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.055 0.000 179.073 0.054 ; + END + END r0_rd_out[294] + PIN r0_rd_out[295] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.343 0.000 179.361 0.054 ; + END + END r0_rd_out[295] + PIN r0_rd_out[296] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.631 0.000 179.649 0.054 ; + END + END r0_rd_out[296] + PIN r0_rd_out[297] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.919 0.000 179.937 0.054 ; + END + END r0_rd_out[297] + PIN r0_rd_out[298] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.207 0.000 180.225 0.054 ; + END + END r0_rd_out[298] + PIN r0_rd_out[299] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.495 0.000 180.513 0.054 ; + END + END r0_rd_out[299] + PIN r0_rd_out[300] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.783 0.000 180.801 0.054 ; + END + END r0_rd_out[300] + PIN r0_rd_out[301] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.071 0.000 181.089 0.054 ; + END + END r0_rd_out[301] + PIN r0_rd_out[302] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.359 0.000 181.377 0.054 ; + END + END r0_rd_out[302] + PIN r0_rd_out[303] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.647 0.000 181.665 0.054 ; + END + END r0_rd_out[303] + PIN r0_rd_out[304] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.935 0.000 181.953 0.054 ; + END + END r0_rd_out[304] + PIN r0_rd_out[305] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.223 0.000 182.241 0.054 ; + END + END r0_rd_out[305] + PIN r0_rd_out[306] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.511 0.000 182.529 0.054 ; + END + END r0_rd_out[306] + PIN r0_rd_out[307] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.799 0.000 182.817 0.054 ; + END + END r0_rd_out[307] + PIN r0_rd_out[308] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.087 0.000 183.105 0.054 ; + END + END r0_rd_out[308] + PIN r0_rd_out[309] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.375 0.000 183.393 0.054 ; + END + END r0_rd_out[309] + PIN r0_rd_out[310] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.663 0.000 183.681 0.054 ; + END + END r0_rd_out[310] + PIN r0_rd_out[311] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.951 0.000 183.969 0.054 ; + END + END r0_rd_out[311] + PIN r0_rd_out[312] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.239 0.000 184.257 0.054 ; + END + END r0_rd_out[312] + PIN r0_rd_out[313] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.527 0.000 184.545 0.054 ; + END + END r0_rd_out[313] + PIN r0_rd_out[314] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.815 0.000 184.833 0.054 ; + END + END r0_rd_out[314] + PIN r0_rd_out[315] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.103 0.000 185.121 0.054 ; + END + END r0_rd_out[315] + PIN r0_rd_out[316] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.391 0.000 185.409 0.054 ; + END + END r0_rd_out[316] + PIN r0_rd_out[317] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.679 0.000 185.697 0.054 ; + END + END r0_rd_out[317] + PIN r0_rd_out[318] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.967 0.000 185.985 0.054 ; + END + END r0_rd_out[318] + PIN r0_rd_out[319] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.255 0.000 186.273 0.054 ; + END + END r0_rd_out[319] + PIN r0_rd_out[320] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.543 0.000 186.561 0.054 ; + END + END r0_rd_out[320] + PIN r0_rd_out[321] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.831 0.000 186.849 0.054 ; + END + END r0_rd_out[321] + PIN r0_rd_out[322] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.119 0.000 187.137 0.054 ; + END + END r0_rd_out[322] + PIN r0_rd_out[323] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.407 0.000 187.425 0.054 ; + END + END r0_rd_out[323] + PIN r0_rd_out[324] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.695 0.000 187.713 0.054 ; + END + END r0_rd_out[324] + PIN r0_rd_out[325] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.983 0.000 188.001 0.054 ; + END + END r0_rd_out[325] + PIN r0_rd_out[326] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.271 0.000 188.289 0.054 ; + END + END r0_rd_out[326] + PIN r0_rd_out[327] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.383 58.573 94.401 58.627 ; + END + END r0_rd_out[327] + PIN r0_rd_out[328] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.671 58.573 94.689 58.627 ; + END + END r0_rd_out[328] + PIN r0_rd_out[329] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 94.959 58.573 94.977 58.627 ; + END + END r0_rd_out[329] + PIN r0_rd_out[330] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.247 58.573 95.265 58.627 ; + END + END r0_rd_out[330] + PIN r0_rd_out[331] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.535 58.573 95.553 58.627 ; + END + END r0_rd_out[331] + PIN r0_rd_out[332] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 95.823 58.573 95.841 58.627 ; + END + END r0_rd_out[332] + PIN r0_rd_out[333] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.111 58.573 96.129 58.627 ; + END + END r0_rd_out[333] + PIN r0_rd_out[334] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.399 58.573 96.417 58.627 ; + END + END r0_rd_out[334] + PIN r0_rd_out[335] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.687 58.573 96.705 58.627 ; + END + END r0_rd_out[335] + PIN r0_rd_out[336] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 96.975 58.573 96.993 58.627 ; + END + END r0_rd_out[336] + PIN r0_rd_out[337] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.263 58.573 97.281 58.627 ; + END + END r0_rd_out[337] + PIN r0_rd_out[338] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.551 58.573 97.569 58.627 ; + END + END r0_rd_out[338] + PIN r0_rd_out[339] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 97.839 58.573 97.857 58.627 ; + END + END r0_rd_out[339] + PIN r0_rd_out[340] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.127 58.573 98.145 58.627 ; + END + END r0_rd_out[340] + PIN r0_rd_out[341] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.415 58.573 98.433 58.627 ; + END + END r0_rd_out[341] + PIN r0_rd_out[342] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.703 58.573 98.721 58.627 ; + END + END r0_rd_out[342] + PIN r0_rd_out[343] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 98.991 58.573 99.009 58.627 ; + END + END r0_rd_out[343] + PIN r0_rd_out[344] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.279 58.573 99.297 58.627 ; + END + END r0_rd_out[344] + PIN r0_rd_out[345] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.567 58.573 99.585 58.627 ; + END + END r0_rd_out[345] + PIN r0_rd_out[346] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 99.855 58.573 99.873 58.627 ; + END + END r0_rd_out[346] + PIN r0_rd_out[347] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.143 58.573 100.161 58.627 ; + END + END r0_rd_out[347] + PIN r0_rd_out[348] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.431 58.573 100.449 58.627 ; + END + END r0_rd_out[348] + PIN r0_rd_out[349] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 100.719 58.573 100.737 58.627 ; + END + END r0_rd_out[349] + PIN r0_rd_out[350] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.007 58.573 101.025 58.627 ; + END + END r0_rd_out[350] + PIN r0_rd_out[351] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.295 58.573 101.313 58.627 ; + END + END r0_rd_out[351] + PIN r0_rd_out[352] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.583 58.573 101.601 58.627 ; + END + END r0_rd_out[352] + PIN r0_rd_out[353] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 101.871 58.573 101.889 58.627 ; + END + END r0_rd_out[353] + PIN r0_rd_out[354] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.159 58.573 102.177 58.627 ; + END + END r0_rd_out[354] + PIN r0_rd_out[355] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.447 58.573 102.465 58.627 ; + END + END r0_rd_out[355] + PIN r0_rd_out[356] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 102.735 58.573 102.753 58.627 ; + END + END r0_rd_out[356] + PIN r0_rd_out[357] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.023 58.573 103.041 58.627 ; + END + END r0_rd_out[357] + PIN r0_rd_out[358] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.311 58.573 103.329 58.627 ; + END + END r0_rd_out[358] + PIN r0_rd_out[359] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.599 58.573 103.617 58.627 ; + END + END r0_rd_out[359] + PIN r0_rd_out[360] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 103.887 58.573 103.905 58.627 ; + END + END r0_rd_out[360] + PIN r0_rd_out[361] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.175 58.573 104.193 58.627 ; + END + END r0_rd_out[361] + PIN r0_rd_out[362] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.463 58.573 104.481 58.627 ; + END + END r0_rd_out[362] + PIN r0_rd_out[363] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 104.751 58.573 104.769 58.627 ; + END + END r0_rd_out[363] + PIN r0_rd_out[364] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.039 58.573 105.057 58.627 ; + END + END r0_rd_out[364] + PIN r0_rd_out[365] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.327 58.573 105.345 58.627 ; + END + END r0_rd_out[365] + PIN r0_rd_out[366] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.615 58.573 105.633 58.627 ; + END + END r0_rd_out[366] + PIN r0_rd_out[367] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 105.903 58.573 105.921 58.627 ; + END + END r0_rd_out[367] + PIN r0_rd_out[368] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.191 58.573 106.209 58.627 ; + END + END r0_rd_out[368] + PIN r0_rd_out[369] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.479 58.573 106.497 58.627 ; + END + END r0_rd_out[369] + PIN r0_rd_out[370] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 106.767 58.573 106.785 58.627 ; + END + END r0_rd_out[370] + PIN r0_rd_out[371] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.055 58.573 107.073 58.627 ; + END + END r0_rd_out[371] + PIN r0_rd_out[372] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.343 58.573 107.361 58.627 ; + END + END r0_rd_out[372] + PIN r0_rd_out[373] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.631 58.573 107.649 58.627 ; + END + END r0_rd_out[373] + PIN r0_rd_out[374] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 107.919 58.573 107.937 58.627 ; + END + END r0_rd_out[374] + PIN r0_rd_out[375] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.207 58.573 108.225 58.627 ; + END + END r0_rd_out[375] + PIN r0_rd_out[376] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.495 58.573 108.513 58.627 ; + END + END r0_rd_out[376] + PIN r0_rd_out[377] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 108.783 58.573 108.801 58.627 ; + END + END r0_rd_out[377] + PIN r0_rd_out[378] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.071 58.573 109.089 58.627 ; + END + END r0_rd_out[378] + PIN r0_rd_out[379] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.359 58.573 109.377 58.627 ; + END + END r0_rd_out[379] + PIN r0_rd_out[380] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.647 58.573 109.665 58.627 ; + END + END r0_rd_out[380] + PIN r0_rd_out[381] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 109.935 58.573 109.953 58.627 ; + END + END r0_rd_out[381] + PIN r0_rd_out[382] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.223 58.573 110.241 58.627 ; + END + END r0_rd_out[382] + PIN r0_rd_out[383] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.511 58.573 110.529 58.627 ; + END + END r0_rd_out[383] + PIN r0_rd_out[384] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 110.799 58.573 110.817 58.627 ; + END + END r0_rd_out[384] + PIN r0_rd_out[385] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.087 58.573 111.105 58.627 ; + END + END r0_rd_out[385] + PIN r0_rd_out[386] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.375 58.573 111.393 58.627 ; + END + END r0_rd_out[386] + PIN r0_rd_out[387] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.663 58.573 111.681 58.627 ; + END + END r0_rd_out[387] + PIN r0_rd_out[388] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 111.951 58.573 111.969 58.627 ; + END + END r0_rd_out[388] + PIN r0_rd_out[389] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.239 58.573 112.257 58.627 ; + END + END r0_rd_out[389] + PIN r0_rd_out[390] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.527 58.573 112.545 58.627 ; + END + END r0_rd_out[390] + PIN r0_rd_out[391] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 112.815 58.573 112.833 58.627 ; + END + END r0_rd_out[391] + PIN r0_rd_out[392] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.103 58.573 113.121 58.627 ; + END + END r0_rd_out[392] + PIN r0_rd_out[393] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.391 58.573 113.409 58.627 ; + END + END r0_rd_out[393] + PIN r0_rd_out[394] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.679 58.573 113.697 58.627 ; + END + END r0_rd_out[394] + PIN r0_rd_out[395] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 113.967 58.573 113.985 58.627 ; + END + END r0_rd_out[395] + PIN r0_rd_out[396] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.255 58.573 114.273 58.627 ; + END + END r0_rd_out[396] + PIN r0_rd_out[397] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.543 58.573 114.561 58.627 ; + END + END r0_rd_out[397] + PIN r0_rd_out[398] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 114.831 58.573 114.849 58.627 ; + END + END r0_rd_out[398] + PIN r0_rd_out[399] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.119 58.573 115.137 58.627 ; + END + END r0_rd_out[399] + PIN r0_rd_out[400] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.407 58.573 115.425 58.627 ; + END + END r0_rd_out[400] + PIN r0_rd_out[401] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.695 58.573 115.713 58.627 ; + END + END r0_rd_out[401] + PIN r0_rd_out[402] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 115.983 58.573 116.001 58.627 ; + END + END r0_rd_out[402] + PIN r0_rd_out[403] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.271 58.573 116.289 58.627 ; + END + END r0_rd_out[403] + PIN r0_rd_out[404] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.559 58.573 116.577 58.627 ; + END + END r0_rd_out[404] + PIN r0_rd_out[405] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 116.847 58.573 116.865 58.627 ; + END + END r0_rd_out[405] + PIN r0_rd_out[406] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.135 58.573 117.153 58.627 ; + END + END r0_rd_out[406] + PIN r0_rd_out[407] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.423 58.573 117.441 58.627 ; + END + END r0_rd_out[407] + PIN r0_rd_out[408] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.711 58.573 117.729 58.627 ; + END + END r0_rd_out[408] + PIN r0_rd_out[409] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 117.999 58.573 118.017 58.627 ; + END + END r0_rd_out[409] + PIN r0_rd_out[410] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.287 58.573 118.305 58.627 ; + END + END r0_rd_out[410] + PIN r0_rd_out[411] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.575 58.573 118.593 58.627 ; + END + END r0_rd_out[411] + PIN r0_rd_out[412] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 118.863 58.573 118.881 58.627 ; + END + END r0_rd_out[412] + PIN r0_rd_out[413] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.151 58.573 119.169 58.627 ; + END + END r0_rd_out[413] + PIN r0_rd_out[414] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.439 58.573 119.457 58.627 ; + END + END r0_rd_out[414] + PIN r0_rd_out[415] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 119.727 58.573 119.745 58.627 ; + END + END r0_rd_out[415] + PIN r0_rd_out[416] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.015 58.573 120.033 58.627 ; + END + END r0_rd_out[416] + PIN r0_rd_out[417] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.303 58.573 120.321 58.627 ; + END + END r0_rd_out[417] + PIN r0_rd_out[418] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.591 58.573 120.609 58.627 ; + END + END r0_rd_out[418] + PIN r0_rd_out[419] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 120.879 58.573 120.897 58.627 ; + END + END r0_rd_out[419] + PIN r0_rd_out[420] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.167 58.573 121.185 58.627 ; + END + END r0_rd_out[420] + PIN r0_rd_out[421] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.455 58.573 121.473 58.627 ; + END + END r0_rd_out[421] + PIN r0_rd_out[422] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 121.743 58.573 121.761 58.627 ; + END + END r0_rd_out[422] + PIN r0_rd_out[423] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.031 58.573 122.049 58.627 ; + END + END r0_rd_out[423] + PIN r0_rd_out[424] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.319 58.573 122.337 58.627 ; + END + END r0_rd_out[424] + PIN r0_rd_out[425] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.607 58.573 122.625 58.627 ; + END + END r0_rd_out[425] + PIN r0_rd_out[426] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 122.895 58.573 122.913 58.627 ; + END + END r0_rd_out[426] + PIN r0_rd_out[427] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.183 58.573 123.201 58.627 ; + END + END r0_rd_out[427] + PIN r0_rd_out[428] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.471 58.573 123.489 58.627 ; + END + END r0_rd_out[428] + PIN r0_rd_out[429] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 123.759 58.573 123.777 58.627 ; + END + END r0_rd_out[429] + PIN r0_rd_out[430] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.047 58.573 124.065 58.627 ; + END + END r0_rd_out[430] + PIN r0_rd_out[431] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.335 58.573 124.353 58.627 ; + END + END r0_rd_out[431] + PIN r0_rd_out[432] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.623 58.573 124.641 58.627 ; + END + END r0_rd_out[432] + PIN r0_rd_out[433] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 124.911 58.573 124.929 58.627 ; + END + END r0_rd_out[433] + PIN r0_rd_out[434] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.199 58.573 125.217 58.627 ; + END + END r0_rd_out[434] + PIN r0_rd_out[435] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.487 58.573 125.505 58.627 ; + END + END r0_rd_out[435] + PIN r0_rd_out[436] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 125.775 58.573 125.793 58.627 ; + END + END r0_rd_out[436] + PIN r0_rd_out[437] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.063 58.573 126.081 58.627 ; + END + END r0_rd_out[437] + PIN r0_rd_out[438] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.351 58.573 126.369 58.627 ; + END + END r0_rd_out[438] + PIN r0_rd_out[439] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.639 58.573 126.657 58.627 ; + END + END r0_rd_out[439] + PIN r0_rd_out[440] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 126.927 58.573 126.945 58.627 ; + END + END r0_rd_out[440] + PIN r0_rd_out[441] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.215 58.573 127.233 58.627 ; + END + END r0_rd_out[441] + PIN r0_rd_out[442] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.503 58.573 127.521 58.627 ; + END + END r0_rd_out[442] + PIN r0_rd_out[443] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 127.791 58.573 127.809 58.627 ; + END + END r0_rd_out[443] + PIN r0_rd_out[444] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.079 58.573 128.097 58.627 ; + END + END r0_rd_out[444] + PIN r0_rd_out[445] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.367 58.573 128.385 58.627 ; + END + END r0_rd_out[445] + PIN r0_rd_out[446] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.655 58.573 128.673 58.627 ; + END + END r0_rd_out[446] + PIN r0_rd_out[447] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 128.943 58.573 128.961 58.627 ; + END + END r0_rd_out[447] + PIN r0_rd_out[448] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.231 58.573 129.249 58.627 ; + END + END r0_rd_out[448] + PIN r0_rd_out[449] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.519 58.573 129.537 58.627 ; + END + END r0_rd_out[449] + PIN r0_rd_out[450] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 129.807 58.573 129.825 58.627 ; + END + END r0_rd_out[450] + PIN r0_rd_out[451] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.095 58.573 130.113 58.627 ; + END + END r0_rd_out[451] + PIN r0_rd_out[452] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.383 58.573 130.401 58.627 ; + END + END r0_rd_out[452] + PIN r0_rd_out[453] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.671 58.573 130.689 58.627 ; + END + END r0_rd_out[453] + PIN r0_rd_out[454] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 130.959 58.573 130.977 58.627 ; + END + END r0_rd_out[454] + PIN r0_rd_out[455] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.247 58.573 131.265 58.627 ; + END + END r0_rd_out[455] + PIN r0_rd_out[456] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.535 58.573 131.553 58.627 ; + END + END r0_rd_out[456] + PIN r0_rd_out[457] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 131.823 58.573 131.841 58.627 ; + END + END r0_rd_out[457] + PIN r0_rd_out[458] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.111 58.573 132.129 58.627 ; + END + END r0_rd_out[458] + PIN r0_rd_out[459] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.399 58.573 132.417 58.627 ; + END + END r0_rd_out[459] + PIN r0_rd_out[460] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.687 58.573 132.705 58.627 ; + END + END r0_rd_out[460] + PIN r0_rd_out[461] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 132.975 58.573 132.993 58.627 ; + END + END r0_rd_out[461] + PIN r0_rd_out[462] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.263 58.573 133.281 58.627 ; + END + END r0_rd_out[462] + PIN r0_rd_out[463] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.551 58.573 133.569 58.627 ; + END + END r0_rd_out[463] + PIN r0_rd_out[464] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 133.839 58.573 133.857 58.627 ; + END + END r0_rd_out[464] + PIN r0_rd_out[465] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.127 58.573 134.145 58.627 ; + END + END r0_rd_out[465] + PIN r0_rd_out[466] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.415 58.573 134.433 58.627 ; + END + END r0_rd_out[466] + PIN r0_rd_out[467] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.703 58.573 134.721 58.627 ; + END + END r0_rd_out[467] + PIN r0_rd_out[468] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 134.991 58.573 135.009 58.627 ; + END + END r0_rd_out[468] + PIN r0_rd_out[469] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.279 58.573 135.297 58.627 ; + END + END r0_rd_out[469] + PIN r0_rd_out[470] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.567 58.573 135.585 58.627 ; + END + END r0_rd_out[470] + PIN r0_rd_out[471] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 135.855 58.573 135.873 58.627 ; + END + END r0_rd_out[471] + PIN r0_rd_out[472] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.143 58.573 136.161 58.627 ; + END + END r0_rd_out[472] + PIN r0_rd_out[473] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.431 58.573 136.449 58.627 ; + END + END r0_rd_out[473] + PIN r0_rd_out[474] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 136.719 58.573 136.737 58.627 ; + END + END r0_rd_out[474] + PIN r0_rd_out[475] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.007 58.573 137.025 58.627 ; + END + END r0_rd_out[475] + PIN r0_rd_out[476] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.295 58.573 137.313 58.627 ; + END + END r0_rd_out[476] + PIN r0_rd_out[477] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.583 58.573 137.601 58.627 ; + END + END r0_rd_out[477] + PIN r0_rd_out[478] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 137.871 58.573 137.889 58.627 ; + END + END r0_rd_out[478] + PIN r0_rd_out[479] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.159 58.573 138.177 58.627 ; + END + END r0_rd_out[479] + PIN r0_rd_out[480] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.447 58.573 138.465 58.627 ; + END + END r0_rd_out[480] + PIN r0_rd_out[481] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 138.735 58.573 138.753 58.627 ; + END + END r0_rd_out[481] + PIN r0_rd_out[482] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.023 58.573 139.041 58.627 ; + END + END r0_rd_out[482] + PIN r0_rd_out[483] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.311 58.573 139.329 58.627 ; + END + END r0_rd_out[483] + PIN r0_rd_out[484] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.599 58.573 139.617 58.627 ; + END + END r0_rd_out[484] + PIN r0_rd_out[485] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 139.887 58.573 139.905 58.627 ; + END + END r0_rd_out[485] + PIN r0_rd_out[486] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.175 58.573 140.193 58.627 ; + END + END r0_rd_out[486] + PIN r0_rd_out[487] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.463 58.573 140.481 58.627 ; + END + END r0_rd_out[487] + PIN r0_rd_out[488] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 140.751 58.573 140.769 58.627 ; + END + END r0_rd_out[488] + PIN r0_rd_out[489] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.039 58.573 141.057 58.627 ; + END + END r0_rd_out[489] + PIN r0_rd_out[490] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.327 58.573 141.345 58.627 ; + END + END r0_rd_out[490] + PIN r0_rd_out[491] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.615 58.573 141.633 58.627 ; + END + END r0_rd_out[491] + PIN r0_rd_out[492] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 141.903 58.573 141.921 58.627 ; + END + END r0_rd_out[492] + PIN r0_rd_out[493] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.191 58.573 142.209 58.627 ; + END + END r0_rd_out[493] + PIN r0_rd_out[494] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.479 58.573 142.497 58.627 ; + END + END r0_rd_out[494] + PIN r0_rd_out[495] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 142.767 58.573 142.785 58.627 ; + END + END r0_rd_out[495] + PIN r0_rd_out[496] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.055 58.573 143.073 58.627 ; + END + END r0_rd_out[496] + PIN r0_rd_out[497] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.343 58.573 143.361 58.627 ; + END + END r0_rd_out[497] + PIN r0_rd_out[498] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.631 58.573 143.649 58.627 ; + END + END r0_rd_out[498] + PIN r0_rd_out[499] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 143.919 58.573 143.937 58.627 ; + END + END r0_rd_out[499] + PIN r0_rd_out[500] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.207 58.573 144.225 58.627 ; + END + END r0_rd_out[500] + PIN r0_rd_out[501] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.495 58.573 144.513 58.627 ; + END + END r0_rd_out[501] + PIN r0_rd_out[502] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 144.783 58.573 144.801 58.627 ; + END + END r0_rd_out[502] + PIN r0_rd_out[503] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.071 58.573 145.089 58.627 ; + END + END r0_rd_out[503] + PIN r0_rd_out[504] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.359 58.573 145.377 58.627 ; + END + END r0_rd_out[504] + PIN r0_rd_out[505] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.647 58.573 145.665 58.627 ; + END + END r0_rd_out[505] + PIN r0_rd_out[506] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 145.935 58.573 145.953 58.627 ; + END + END r0_rd_out[506] + PIN r0_rd_out[507] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.223 58.573 146.241 58.627 ; + END + END r0_rd_out[507] + PIN r0_rd_out[508] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.511 58.573 146.529 58.627 ; + END + END r0_rd_out[508] + PIN r0_rd_out[509] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 146.799 58.573 146.817 58.627 ; + END + END r0_rd_out[509] + PIN r0_rd_out[510] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.087 58.573 147.105 58.627 ; + END + END r0_rd_out[510] + PIN r0_rd_out[511] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.375 58.573 147.393 58.627 ; + END + END r0_rd_out[511] + PIN r0_rd_out[512] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.663 58.573 147.681 58.627 ; + END + END r0_rd_out[512] + PIN r0_rd_out[513] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 147.951 58.573 147.969 58.627 ; + END + END r0_rd_out[513] + PIN r0_rd_out[514] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.239 58.573 148.257 58.627 ; + END + END r0_rd_out[514] + PIN r0_rd_out[515] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.527 58.573 148.545 58.627 ; + END + END r0_rd_out[515] + PIN r0_rd_out[516] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 148.815 58.573 148.833 58.627 ; + END + END r0_rd_out[516] + PIN r0_rd_out[517] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.103 58.573 149.121 58.627 ; + END + END r0_rd_out[517] + PIN r0_rd_out[518] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.391 58.573 149.409 58.627 ; + END + END r0_rd_out[518] + PIN r0_rd_out[519] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.679 58.573 149.697 58.627 ; + END + END r0_rd_out[519] + PIN r0_rd_out[520] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 149.967 58.573 149.985 58.627 ; + END + END r0_rd_out[520] + PIN r0_rd_out[521] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.255 58.573 150.273 58.627 ; + END + END r0_rd_out[521] + PIN r0_rd_out[522] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.543 58.573 150.561 58.627 ; + END + END r0_rd_out[522] + PIN r0_rd_out[523] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 150.831 58.573 150.849 58.627 ; + END + END r0_rd_out[523] + PIN r0_rd_out[524] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.119 58.573 151.137 58.627 ; + END + END r0_rd_out[524] + PIN r0_rd_out[525] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.407 58.573 151.425 58.627 ; + END + END r0_rd_out[525] + PIN r0_rd_out[526] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.695 58.573 151.713 58.627 ; + END + END r0_rd_out[526] + PIN r0_rd_out[527] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 151.983 58.573 152.001 58.627 ; + END + END r0_rd_out[527] + PIN r0_rd_out[528] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.271 58.573 152.289 58.627 ; + END + END r0_rd_out[528] + PIN r0_rd_out[529] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.559 58.573 152.577 58.627 ; + END + END r0_rd_out[529] + PIN r0_rd_out[530] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 152.847 58.573 152.865 58.627 ; + END + END r0_rd_out[530] + PIN r0_rd_out[531] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.135 58.573 153.153 58.627 ; + END + END r0_rd_out[531] + PIN r0_rd_out[532] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.423 58.573 153.441 58.627 ; + END + END r0_rd_out[532] + PIN r0_rd_out[533] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.711 58.573 153.729 58.627 ; + END + END r0_rd_out[533] + PIN r0_rd_out[534] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 153.999 58.573 154.017 58.627 ; + END + END r0_rd_out[534] + PIN r0_rd_out[535] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.287 58.573 154.305 58.627 ; + END + END r0_rd_out[535] + PIN r0_rd_out[536] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.575 58.573 154.593 58.627 ; + END + END r0_rd_out[536] + PIN r0_rd_out[537] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 154.863 58.573 154.881 58.627 ; + END + END r0_rd_out[537] + PIN r0_rd_out[538] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.151 58.573 155.169 58.627 ; + END + END r0_rd_out[538] + PIN r0_rd_out[539] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.439 58.573 155.457 58.627 ; + END + END r0_rd_out[539] + PIN r0_rd_out[540] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 155.727 58.573 155.745 58.627 ; + END + END r0_rd_out[540] + PIN r0_rd_out[541] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.015 58.573 156.033 58.627 ; + END + END r0_rd_out[541] + PIN r0_rd_out[542] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.303 58.573 156.321 58.627 ; + END + END r0_rd_out[542] + PIN r0_rd_out[543] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.591 58.573 156.609 58.627 ; + END + END r0_rd_out[543] + PIN r0_rd_out[544] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 156.879 58.573 156.897 58.627 ; + END + END r0_rd_out[544] + PIN r0_rd_out[545] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.167 58.573 157.185 58.627 ; + END + END r0_rd_out[545] + PIN r0_rd_out[546] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.455 58.573 157.473 58.627 ; + END + END r0_rd_out[546] + PIN r0_rd_out[547] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 157.743 58.573 157.761 58.627 ; + END + END r0_rd_out[547] + PIN r0_rd_out[548] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.031 58.573 158.049 58.627 ; + END + END r0_rd_out[548] + PIN r0_rd_out[549] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.319 58.573 158.337 58.627 ; + END + END r0_rd_out[549] + PIN r0_rd_out[550] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.607 58.573 158.625 58.627 ; + END + END r0_rd_out[550] + PIN r0_rd_out[551] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 158.895 58.573 158.913 58.627 ; + END + END r0_rd_out[551] + PIN r0_rd_out[552] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.183 58.573 159.201 58.627 ; + END + END r0_rd_out[552] + PIN r0_rd_out[553] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.471 58.573 159.489 58.627 ; + END + END r0_rd_out[553] + PIN r0_rd_out[554] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 159.759 58.573 159.777 58.627 ; + END + END r0_rd_out[554] + PIN r0_rd_out[555] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.047 58.573 160.065 58.627 ; + END + END r0_rd_out[555] + PIN r0_rd_out[556] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.335 58.573 160.353 58.627 ; + END + END r0_rd_out[556] + PIN r0_rd_out[557] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.623 58.573 160.641 58.627 ; + END + END r0_rd_out[557] + PIN r0_rd_out[558] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 160.911 58.573 160.929 58.627 ; + END + END r0_rd_out[558] + PIN r0_rd_out[559] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.199 58.573 161.217 58.627 ; + END + END r0_rd_out[559] + PIN r0_rd_out[560] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.487 58.573 161.505 58.627 ; + END + END r0_rd_out[560] + PIN r0_rd_out[561] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 161.775 58.573 161.793 58.627 ; + END + END r0_rd_out[561] + PIN r0_rd_out[562] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.063 58.573 162.081 58.627 ; + END + END r0_rd_out[562] + PIN r0_rd_out[563] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.351 58.573 162.369 58.627 ; + END + END r0_rd_out[563] + PIN r0_rd_out[564] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.639 58.573 162.657 58.627 ; + END + END r0_rd_out[564] + PIN r0_rd_out[565] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 162.927 58.573 162.945 58.627 ; + END + END r0_rd_out[565] + PIN r0_rd_out[566] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.215 58.573 163.233 58.627 ; + END + END r0_rd_out[566] + PIN r0_rd_out[567] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.503 58.573 163.521 58.627 ; + END + END r0_rd_out[567] + PIN r0_rd_out[568] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 163.791 58.573 163.809 58.627 ; + END + END r0_rd_out[568] + PIN r0_rd_out[569] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.079 58.573 164.097 58.627 ; + END + END r0_rd_out[569] + PIN r0_rd_out[570] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.367 58.573 164.385 58.627 ; + END + END r0_rd_out[570] + PIN r0_rd_out[571] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.655 58.573 164.673 58.627 ; + END + END r0_rd_out[571] + PIN r0_rd_out[572] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 164.943 58.573 164.961 58.627 ; + END + END r0_rd_out[572] + PIN r0_rd_out[573] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.231 58.573 165.249 58.627 ; + END + END r0_rd_out[573] + PIN r0_rd_out[574] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.519 58.573 165.537 58.627 ; + END + END r0_rd_out[574] + PIN r0_rd_out[575] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 165.807 58.573 165.825 58.627 ; + END + END r0_rd_out[575] + PIN r0_rd_out[576] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.095 58.573 166.113 58.627 ; + END + END r0_rd_out[576] + PIN r0_rd_out[577] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.383 58.573 166.401 58.627 ; + END + END r0_rd_out[577] + PIN r0_rd_out[578] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.671 58.573 166.689 58.627 ; + END + END r0_rd_out[578] + PIN r0_rd_out[579] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 166.959 58.573 166.977 58.627 ; + END + END r0_rd_out[579] + PIN r0_rd_out[580] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.247 58.573 167.265 58.627 ; + END + END r0_rd_out[580] + PIN r0_rd_out[581] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.535 58.573 167.553 58.627 ; + END + END r0_rd_out[581] + PIN r0_rd_out[582] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 167.823 58.573 167.841 58.627 ; + END + END r0_rd_out[582] + PIN r0_rd_out[583] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.111 58.573 168.129 58.627 ; + END + END r0_rd_out[583] + PIN r0_rd_out[584] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.399 58.573 168.417 58.627 ; + END + END r0_rd_out[584] + PIN r0_rd_out[585] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.687 58.573 168.705 58.627 ; + END + END r0_rd_out[585] + PIN r0_rd_out[586] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 168.975 58.573 168.993 58.627 ; + END + END r0_rd_out[586] + PIN r0_rd_out[587] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.263 58.573 169.281 58.627 ; + END + END r0_rd_out[587] + PIN r0_rd_out[588] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.551 58.573 169.569 58.627 ; + END + END r0_rd_out[588] + PIN r0_rd_out[589] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 169.839 58.573 169.857 58.627 ; + END + END r0_rd_out[589] + PIN r0_rd_out[590] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.127 58.573 170.145 58.627 ; + END + END r0_rd_out[590] + PIN r0_rd_out[591] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.415 58.573 170.433 58.627 ; + END + END r0_rd_out[591] + PIN r0_rd_out[592] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.703 58.573 170.721 58.627 ; + END + END r0_rd_out[592] + PIN r0_rd_out[593] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 170.991 58.573 171.009 58.627 ; + END + END r0_rd_out[593] + PIN r0_rd_out[594] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.279 58.573 171.297 58.627 ; + END + END r0_rd_out[594] + PIN r0_rd_out[595] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.567 58.573 171.585 58.627 ; + END + END r0_rd_out[595] + PIN r0_rd_out[596] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 171.855 58.573 171.873 58.627 ; + END + END r0_rd_out[596] + PIN r0_rd_out[597] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.143 58.573 172.161 58.627 ; + END + END r0_rd_out[597] + PIN r0_rd_out[598] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.431 58.573 172.449 58.627 ; + END + END r0_rd_out[598] + PIN r0_rd_out[599] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 172.719 58.573 172.737 58.627 ; + END + END r0_rd_out[599] + PIN r0_rd_out[600] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.007 58.573 173.025 58.627 ; + END + END r0_rd_out[600] + PIN r0_rd_out[601] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.295 58.573 173.313 58.627 ; + END + END r0_rd_out[601] + PIN r0_rd_out[602] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.583 58.573 173.601 58.627 ; + END + END r0_rd_out[602] + PIN r0_rd_out[603] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 173.871 58.573 173.889 58.627 ; + END + END r0_rd_out[603] + PIN r0_rd_out[604] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.159 58.573 174.177 58.627 ; + END + END r0_rd_out[604] + PIN r0_rd_out[605] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.447 58.573 174.465 58.627 ; + END + END r0_rd_out[605] + PIN r0_rd_out[606] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 174.735 58.573 174.753 58.627 ; + END + END r0_rd_out[606] + PIN r0_rd_out[607] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.023 58.573 175.041 58.627 ; + END + END r0_rd_out[607] + PIN r0_rd_out[608] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.311 58.573 175.329 58.627 ; + END + END r0_rd_out[608] + PIN r0_rd_out[609] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.599 58.573 175.617 58.627 ; + END + END r0_rd_out[609] + PIN r0_rd_out[610] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 175.887 58.573 175.905 58.627 ; + END + END r0_rd_out[610] + PIN r0_rd_out[611] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.175 58.573 176.193 58.627 ; + END + END r0_rd_out[611] + PIN r0_rd_out[612] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.463 58.573 176.481 58.627 ; + END + END r0_rd_out[612] + PIN r0_rd_out[613] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 176.751 58.573 176.769 58.627 ; + END + END r0_rd_out[613] + PIN r0_rd_out[614] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.039 58.573 177.057 58.627 ; + END + END r0_rd_out[614] + PIN r0_rd_out[615] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.327 58.573 177.345 58.627 ; + END + END r0_rd_out[615] + PIN r0_rd_out[616] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.615 58.573 177.633 58.627 ; + END + END r0_rd_out[616] + PIN r0_rd_out[617] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 177.903 58.573 177.921 58.627 ; + END + END r0_rd_out[617] + PIN r0_rd_out[618] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.191 58.573 178.209 58.627 ; + END + END r0_rd_out[618] + PIN r0_rd_out[619] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.479 58.573 178.497 58.627 ; + END + END r0_rd_out[619] + PIN r0_rd_out[620] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 178.767 58.573 178.785 58.627 ; + END + END r0_rd_out[620] + PIN r0_rd_out[621] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.055 58.573 179.073 58.627 ; + END + END r0_rd_out[621] + PIN r0_rd_out[622] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.343 58.573 179.361 58.627 ; + END + END r0_rd_out[622] + PIN r0_rd_out[623] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.631 58.573 179.649 58.627 ; + END + END r0_rd_out[623] + PIN r0_rd_out[624] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 179.919 58.573 179.937 58.627 ; + END + END r0_rd_out[624] + PIN r0_rd_out[625] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.207 58.573 180.225 58.627 ; + END + END r0_rd_out[625] + PIN r0_rd_out[626] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.495 58.573 180.513 58.627 ; + END + END r0_rd_out[626] + PIN r0_rd_out[627] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 180.783 58.573 180.801 58.627 ; + END + END r0_rd_out[627] + PIN r0_rd_out[628] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.071 58.573 181.089 58.627 ; + END + END r0_rd_out[628] + PIN r0_rd_out[629] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.359 58.573 181.377 58.627 ; + END + END r0_rd_out[629] + PIN r0_rd_out[630] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.647 58.573 181.665 58.627 ; + END + END r0_rd_out[630] + PIN r0_rd_out[631] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 181.935 58.573 181.953 58.627 ; + END + END r0_rd_out[631] + PIN r0_rd_out[632] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.223 58.573 182.241 58.627 ; + END + END r0_rd_out[632] + PIN r0_rd_out[633] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.511 58.573 182.529 58.627 ; + END + END r0_rd_out[633] + PIN r0_rd_out[634] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 182.799 58.573 182.817 58.627 ; + END + END r0_rd_out[634] + PIN r0_rd_out[635] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.087 58.573 183.105 58.627 ; + END + END r0_rd_out[635] + PIN r0_rd_out[636] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.375 58.573 183.393 58.627 ; + END + END r0_rd_out[636] + PIN r0_rd_out[637] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.663 58.573 183.681 58.627 ; + END + END r0_rd_out[637] + PIN r0_rd_out[638] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 183.951 58.573 183.969 58.627 ; + END + END r0_rd_out[638] + PIN r0_rd_out[639] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.239 58.573 184.257 58.627 ; + END + END r0_rd_out[639] + PIN r0_rd_out[640] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.527 58.573 184.545 58.627 ; + END + END r0_rd_out[640] + PIN r0_rd_out[641] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 184.815 58.573 184.833 58.627 ; + END + END r0_rd_out[641] + PIN r0_rd_out[642] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.103 58.573 185.121 58.627 ; + END + END r0_rd_out[642] + PIN r0_rd_out[643] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.391 58.573 185.409 58.627 ; + END + END r0_rd_out[643] + PIN r0_rd_out[644] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.679 58.573 185.697 58.627 ; + END + END r0_rd_out[644] + PIN r0_rd_out[645] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 185.967 58.573 185.985 58.627 ; + END + END r0_rd_out[645] + PIN r0_rd_out[646] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.255 58.573 186.273 58.627 ; + END + END r0_rd_out[646] + PIN r0_rd_out[647] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.543 58.573 186.561 58.627 ; + END + END r0_rd_out[647] + PIN r0_rd_out[648] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 186.831 58.573 186.849 58.627 ; + END + END r0_rd_out[648] + PIN r0_rd_out[649] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.119 58.573 187.137 58.627 ; + END + END r0_rd_out[649] + PIN r0_rd_out[650] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.407 58.573 187.425 58.627 ; + END + END r0_rd_out[650] + PIN r0_rd_out[651] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.695 58.573 187.713 58.627 ; + END + END r0_rd_out[651] + PIN r0_rd_out[652] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 187.983 58.573 188.001 58.627 ; + END + END r0_rd_out[652] + PIN r0_rd_out[653] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.271 58.573 188.289 58.627 ; + END + END r0_rd_out[653] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.508 0.072 47.532 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 47.220 208.506 47.244 ; + END + END w0_addr_in[1] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.652 0.072 47.676 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 208.434 47.364 208.506 47.388 ; + END + END r0_addr_in[1] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.559 58.573 188.577 58.627 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 188.847 58.573 188.865 58.627 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.135 58.573 189.153 58.627 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.423 58.573 189.441 58.627 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 189.711 58.573 189.729 58.627 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 208.290 0.336 ; + RECT 0.216 1.008 208.290 1.104 ; + RECT 0.216 1.776 208.290 1.872 ; + RECT 0.216 2.544 208.290 2.640 ; + RECT 0.216 3.312 208.290 3.408 ; + RECT 0.216 4.080 208.290 4.176 ; + RECT 0.216 4.848 208.290 4.944 ; + RECT 0.216 5.616 208.290 5.712 ; + RECT 0.216 6.384 208.290 6.480 ; + RECT 0.216 7.152 208.290 7.248 ; + RECT 0.216 7.920 208.290 8.016 ; + RECT 0.216 8.688 208.290 8.784 ; + RECT 0.216 9.456 208.290 9.552 ; + RECT 0.216 10.224 208.290 10.320 ; + RECT 0.216 10.992 208.290 11.088 ; + RECT 0.216 11.760 208.290 11.856 ; + RECT 0.216 12.528 208.290 12.624 ; + RECT 0.216 13.296 208.290 13.392 ; + RECT 0.216 14.064 208.290 14.160 ; + RECT 0.216 14.832 208.290 14.928 ; + RECT 0.216 15.600 208.290 15.696 ; + RECT 0.216 16.368 208.290 16.464 ; + RECT 0.216 17.136 208.290 17.232 ; + RECT 0.216 17.904 208.290 18.000 ; + RECT 0.216 18.672 208.290 18.768 ; + RECT 0.216 19.440 208.290 19.536 ; + RECT 0.216 20.208 208.290 20.304 ; + RECT 0.216 20.976 208.290 21.072 ; + RECT 0.216 21.744 208.290 21.840 ; + RECT 0.216 22.512 208.290 22.608 ; + RECT 0.216 23.280 208.290 23.376 ; + RECT 0.216 24.048 208.290 24.144 ; + RECT 0.216 24.816 208.290 24.912 ; + RECT 0.216 25.584 208.290 25.680 ; + RECT 0.216 26.352 208.290 26.448 ; + RECT 0.216 27.120 208.290 27.216 ; + RECT 0.216 27.888 208.290 27.984 ; + RECT 0.216 28.656 208.290 28.752 ; + RECT 0.216 29.424 208.290 29.520 ; + RECT 0.216 30.192 208.290 30.288 ; + RECT 0.216 30.960 208.290 31.056 ; + RECT 0.216 31.728 208.290 31.824 ; + RECT 0.216 32.496 208.290 32.592 ; + RECT 0.216 33.264 208.290 33.360 ; + RECT 0.216 34.032 208.290 34.128 ; + RECT 0.216 34.800 208.290 34.896 ; + RECT 0.216 35.568 208.290 35.664 ; + RECT 0.216 36.336 208.290 36.432 ; + RECT 0.216 37.104 208.290 37.200 ; + RECT 0.216 37.872 208.290 37.968 ; + RECT 0.216 38.640 208.290 38.736 ; + RECT 0.216 39.408 208.290 39.504 ; + RECT 0.216 40.176 208.290 40.272 ; + RECT 0.216 40.944 208.290 41.040 ; + RECT 0.216 41.712 208.290 41.808 ; + RECT 0.216 42.480 208.290 42.576 ; + RECT 0.216 43.248 208.290 43.344 ; + RECT 0.216 44.016 208.290 44.112 ; + RECT 0.216 44.784 208.290 44.880 ; + RECT 0.216 45.552 208.290 45.648 ; + RECT 0.216 46.320 208.290 46.416 ; + RECT 0.216 47.088 208.290 47.184 ; + RECT 0.216 47.856 208.290 47.952 ; + RECT 0.216 48.624 208.290 48.720 ; + RECT 0.216 49.392 208.290 49.488 ; + RECT 0.216 50.160 208.290 50.256 ; + RECT 0.216 50.928 208.290 51.024 ; + RECT 0.216 51.696 208.290 51.792 ; + RECT 0.216 52.464 208.290 52.560 ; + RECT 0.216 53.232 208.290 53.328 ; + RECT 0.216 54.000 208.290 54.096 ; + RECT 0.216 54.768 208.290 54.864 ; + RECT 0.216 55.536 208.290 55.632 ; + RECT 0.216 56.304 208.290 56.400 ; + RECT 0.216 57.072 208.290 57.168 ; + RECT 0.216 57.840 208.290 57.936 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 208.290 0.336 ; + RECT 0.216 1.008 208.290 1.104 ; + RECT 0.216 1.776 208.290 1.872 ; + RECT 0.216 2.544 208.290 2.640 ; + RECT 0.216 3.312 208.290 3.408 ; + RECT 0.216 4.080 208.290 4.176 ; + RECT 0.216 4.848 208.290 4.944 ; + RECT 0.216 5.616 208.290 5.712 ; + RECT 0.216 6.384 208.290 6.480 ; + RECT 0.216 7.152 208.290 7.248 ; + RECT 0.216 7.920 208.290 8.016 ; + RECT 0.216 8.688 208.290 8.784 ; + RECT 0.216 9.456 208.290 9.552 ; + RECT 0.216 10.224 208.290 10.320 ; + RECT 0.216 10.992 208.290 11.088 ; + RECT 0.216 11.760 208.290 11.856 ; + RECT 0.216 12.528 208.290 12.624 ; + RECT 0.216 13.296 208.290 13.392 ; + RECT 0.216 14.064 208.290 14.160 ; + RECT 0.216 14.832 208.290 14.928 ; + RECT 0.216 15.600 208.290 15.696 ; + RECT 0.216 16.368 208.290 16.464 ; + RECT 0.216 17.136 208.290 17.232 ; + RECT 0.216 17.904 208.290 18.000 ; + RECT 0.216 18.672 208.290 18.768 ; + RECT 0.216 19.440 208.290 19.536 ; + RECT 0.216 20.208 208.290 20.304 ; + RECT 0.216 20.976 208.290 21.072 ; + RECT 0.216 21.744 208.290 21.840 ; + RECT 0.216 22.512 208.290 22.608 ; + RECT 0.216 23.280 208.290 23.376 ; + RECT 0.216 24.048 208.290 24.144 ; + RECT 0.216 24.816 208.290 24.912 ; + RECT 0.216 25.584 208.290 25.680 ; + RECT 0.216 26.352 208.290 26.448 ; + RECT 0.216 27.120 208.290 27.216 ; + RECT 0.216 27.888 208.290 27.984 ; + RECT 0.216 28.656 208.290 28.752 ; + RECT 0.216 29.424 208.290 29.520 ; + RECT 0.216 30.192 208.290 30.288 ; + RECT 0.216 30.960 208.290 31.056 ; + RECT 0.216 31.728 208.290 31.824 ; + RECT 0.216 32.496 208.290 32.592 ; + RECT 0.216 33.264 208.290 33.360 ; + RECT 0.216 34.032 208.290 34.128 ; + RECT 0.216 34.800 208.290 34.896 ; + RECT 0.216 35.568 208.290 35.664 ; + RECT 0.216 36.336 208.290 36.432 ; + RECT 0.216 37.104 208.290 37.200 ; + RECT 0.216 37.872 208.290 37.968 ; + RECT 0.216 38.640 208.290 38.736 ; + RECT 0.216 39.408 208.290 39.504 ; + RECT 0.216 40.176 208.290 40.272 ; + RECT 0.216 40.944 208.290 41.040 ; + RECT 0.216 41.712 208.290 41.808 ; + RECT 0.216 42.480 208.290 42.576 ; + RECT 0.216 43.248 208.290 43.344 ; + RECT 0.216 44.016 208.290 44.112 ; + RECT 0.216 44.784 208.290 44.880 ; + RECT 0.216 45.552 208.290 45.648 ; + RECT 0.216 46.320 208.290 46.416 ; + RECT 0.216 47.088 208.290 47.184 ; + RECT 0.216 47.856 208.290 47.952 ; + RECT 0.216 48.624 208.290 48.720 ; + RECT 0.216 49.392 208.290 49.488 ; + RECT 0.216 50.160 208.290 50.256 ; + RECT 0.216 50.928 208.290 51.024 ; + RECT 0.216 51.696 208.290 51.792 ; + RECT 0.216 52.464 208.290 52.560 ; + RECT 0.216 53.232 208.290 53.328 ; + RECT 0.216 54.000 208.290 54.096 ; + RECT 0.216 54.768 208.290 54.864 ; + RECT 0.216 55.536 208.290 55.632 ; + RECT 0.216 56.304 208.290 56.400 ; + RECT 0.216 57.072 208.290 57.168 ; + RECT 0.216 57.840 208.290 57.936 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 208.506 58.627 ; + LAYER M2 ; + RECT 0 0 208.506 58.627 ; + LAYER M3 ; + RECT 0 0 208.506 58.627 ; + LAYER M4 ; + RECT 0 0 208.506 58.627 ; + END +END fakeram_654x4_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_85x16_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_85x16_1r1w.lef new file mode 100644 index 0000000..6a3b9dc --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_85x16_1r1w.lef @@ -0,0 +1,2474 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_85x16_1r1w + FOREIGN fakeram_85x16_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 27.100 BY 10.362 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.468 0.072 0.492 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.540 0.072 3.564 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 0.276 27.100 0.300 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 0.468 27.100 0.492 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 0.660 27.100 0.684 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 0.852 27.100 0.876 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 1.044 27.100 1.068 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 1.236 27.100 1.260 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 1.428 27.100 1.452 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 1.620 27.100 1.644 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 1.812 27.100 1.836 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 2.004 27.100 2.028 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 2.196 27.100 2.220 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 2.388 27.100 2.412 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 2.580 27.100 2.604 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 2.772 27.100 2.796 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 2.964 27.100 2.988 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 3.156 27.100 3.180 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 3.348 27.100 3.372 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 3.540 27.100 3.564 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 3.732 27.100 3.756 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 3.924 27.100 3.948 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 4.116 27.100 4.140 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 10.308 0.225 10.362 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 10.308 0.513 10.362 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 10.308 0.801 10.362 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 10.308 1.089 10.362 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 10.308 1.377 10.362 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 10.308 1.665 10.362 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 10.308 1.953 10.362 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 10.308 2.241 10.362 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 10.308 2.529 10.362 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 10.308 2.817 10.362 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 10.308 3.105 10.362 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 10.308 3.393 10.362 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 10.308 3.681 10.362 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 10.308 3.969 10.362 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 10.308 4.257 10.362 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 10.308 4.545 10.362 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 10.308 4.833 10.362 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 10.308 5.121 10.362 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 10.308 5.409 10.362 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 10.308 5.697 10.362 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 10.308 5.985 10.362 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 10.308 6.273 10.362 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 10.308 6.561 10.362 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 10.308 6.849 10.362 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 10.308 7.137 10.362 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 10.308 7.425 10.362 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 10.308 7.713 10.362 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 10.308 8.001 10.362 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 10.308 8.289 10.362 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 10.308 8.577 10.362 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 10.308 8.865 10.362 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 10.308 9.153 10.362 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 10.308 9.441 10.362 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 10.308 9.729 10.362 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 10.308 10.017 10.362 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 10.308 10.305 10.362 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 10.308 10.593 10.362 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 10.308 10.881 10.362 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 10.308 11.169 10.362 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 10.308 11.457 10.362 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 10.308 11.745 10.362 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 10.308 12.033 10.362 ; + END + END w0_wmask_in[84] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.844 0.072 5.868 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.228 0.072 6.252 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.380 0.072 7.404 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.148 0.072 8.172 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.532 0.072 8.556 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 4.308 27.100 4.332 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 4.500 27.100 4.524 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 4.692 27.100 4.716 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 4.884 27.100 4.908 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 5.076 27.100 5.100 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 5.268 27.100 5.292 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 5.460 27.100 5.484 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 5.652 27.100 5.676 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 5.844 27.100 5.868 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 6.036 27.100 6.060 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 6.228 27.100 6.252 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 6.420 27.100 6.444 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 6.612 27.100 6.636 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 6.804 27.100 6.828 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 6.996 27.100 7.020 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 7.188 27.100 7.212 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 7.380 27.100 7.404 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 7.572 27.100 7.596 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 7.764 27.100 7.788 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 7.956 27.100 7.980 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 8.148 27.100 8.172 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[84] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 10.308 12.321 10.362 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 10.308 12.609 10.362 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 10.308 12.897 10.362 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 10.308 13.185 10.362 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 10.308 13.473 10.362 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 10.308 13.761 10.362 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 10.308 14.049 10.362 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 10.308 14.337 10.362 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 10.308 14.625 10.362 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 10.308 14.913 10.362 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 10.308 15.201 10.362 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 10.308 15.489 10.362 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 10.308 15.777 10.362 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 10.308 16.065 10.362 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 10.308 16.353 10.362 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 10.308 16.641 10.362 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 10.308 16.929 10.362 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 10.308 17.217 10.362 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 10.308 17.505 10.362 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 10.308 17.793 10.362 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 10.308 18.081 10.362 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 10.308 18.369 10.362 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 10.308 18.657 10.362 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 10.308 18.945 10.362 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 10.308 19.233 10.362 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 10.308 19.521 10.362 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 10.308 19.809 10.362 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 10.308 20.097 10.362 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 10.308 20.385 10.362 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 10.308 20.673 10.362 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 10.308 20.961 10.362 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 10.308 21.249 10.362 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 10.308 21.537 10.362 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 10.308 21.825 10.362 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 10.308 22.113 10.362 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 10.308 22.401 10.362 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 10.308 22.689 10.362 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 10.308 22.977 10.362 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 10.308 23.265 10.362 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 10.308 23.553 10.362 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 10.308 23.841 10.362 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 10.308 24.129 10.362 ; + END + END r0_rd_out[84] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 8.340 27.100 8.364 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 8.532 27.100 8.556 ; + END + END w0_addr_in[3] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.300 0.072 9.324 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 8.724 27.100 8.748 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.028 8.916 27.100 8.940 ; + END + END r0_addr_in[3] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 10.308 24.417 10.362 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 10.308 24.705 10.362 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 10.308 24.993 10.362 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 10.308 25.281 10.362 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 10.308 25.569 10.362 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 26.884 0.336 ; + RECT 0.216 1.008 26.884 1.104 ; + RECT 0.216 1.776 26.884 1.872 ; + RECT 0.216 2.544 26.884 2.640 ; + RECT 0.216 3.312 26.884 3.408 ; + RECT 0.216 4.080 26.884 4.176 ; + RECT 0.216 4.848 26.884 4.944 ; + RECT 0.216 5.616 26.884 5.712 ; + RECT 0.216 6.384 26.884 6.480 ; + RECT 0.216 7.152 26.884 7.248 ; + RECT 0.216 7.920 26.884 8.016 ; + RECT 0.216 8.688 26.884 8.784 ; + RECT 0.216 9.456 26.884 9.552 ; + RECT 0.216 10.224 26.884 10.320 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 26.884 0.336 ; + RECT 0.216 1.008 26.884 1.104 ; + RECT 0.216 1.776 26.884 1.872 ; + RECT 0.216 2.544 26.884 2.640 ; + RECT 0.216 3.312 26.884 3.408 ; + RECT 0.216 4.080 26.884 4.176 ; + RECT 0.216 4.848 26.884 4.944 ; + RECT 0.216 5.616 26.884 5.712 ; + RECT 0.216 6.384 26.884 6.480 ; + RECT 0.216 7.152 26.884 7.248 ; + RECT 0.216 7.920 26.884 8.016 ; + RECT 0.216 8.688 26.884 8.784 ; + RECT 0.216 9.456 26.884 9.552 ; + RECT 0.216 10.224 26.884 10.320 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 27.100 10.362 ; + LAYER M2 ; + RECT 0 0 27.100 10.362 ; + LAYER M3 ; + RECT 0 0 27.100 10.362 ; + LAYER M4 ; + RECT 0 0 27.100 10.362 ; + END +END fakeram_85x16_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lef/fakeram_87x16_1r1w.lef b/designs/asap7/vortex/sram/lef/fakeram_87x16_1r1w.lef new file mode 100644 index 0000000..4944d7e --- /dev/null +++ b/designs/asap7/vortex/sram/lef/fakeram_87x16_1r1w.lef @@ -0,0 +1,2528 @@ +VERSION 5.7 ; +BUSBITCHARS "[]" ; +MACRO fakeram_87x16_1r1w + FOREIGN fakeram_87x16_1r1w 0 0 ; + SYMMETRY X Y R90 ; + SIZE 27.737 BY 10.539 ; + CLASS BLOCK ; + PIN w0_wmask_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.276 0.072 0.300 ; + END + END w0_wmask_in[0] + PIN w0_wmask_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.468 0.072 0.492 ; + END + END w0_wmask_in[1] + PIN w0_wmask_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.660 0.072 0.684 ; + END + END w0_wmask_in[2] + PIN w0_wmask_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.852 0.072 0.876 ; + END + END w0_wmask_in[3] + PIN w0_wmask_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.044 0.072 1.068 ; + END + END w0_wmask_in[4] + PIN w0_wmask_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.236 0.072 1.260 ; + END + END w0_wmask_in[5] + PIN w0_wmask_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.428 0.072 1.452 ; + END + END w0_wmask_in[6] + PIN w0_wmask_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.620 0.072 1.644 ; + END + END w0_wmask_in[7] + PIN w0_wmask_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.812 0.072 1.836 ; + END + END w0_wmask_in[8] + PIN w0_wmask_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.004 0.072 2.028 ; + END + END w0_wmask_in[9] + PIN w0_wmask_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.196 0.072 2.220 ; + END + END w0_wmask_in[10] + PIN w0_wmask_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.388 0.072 2.412 ; + END + END w0_wmask_in[11] + PIN w0_wmask_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.580 0.072 2.604 ; + END + END w0_wmask_in[12] + PIN w0_wmask_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.772 0.072 2.796 ; + END + END w0_wmask_in[13] + PIN w0_wmask_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.964 0.072 2.988 ; + END + END w0_wmask_in[14] + PIN w0_wmask_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.156 0.072 3.180 ; + END + END w0_wmask_in[15] + PIN w0_wmask_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.348 0.072 3.372 ; + END + END w0_wmask_in[16] + PIN w0_wmask_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.540 0.072 3.564 ; + END + END w0_wmask_in[17] + PIN w0_wmask_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.732 0.072 3.756 ; + END + END w0_wmask_in[18] + PIN w0_wmask_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.924 0.072 3.948 ; + END + END w0_wmask_in[19] + PIN w0_wmask_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.116 0.072 4.140 ; + END + END w0_wmask_in[20] + PIN w0_wmask_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.308 0.072 4.332 ; + END + END w0_wmask_in[21] + PIN w0_wmask_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 0.276 27.737 0.300 ; + END + END w0_wmask_in[22] + PIN w0_wmask_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 0.468 27.737 0.492 ; + END + END w0_wmask_in[23] + PIN w0_wmask_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 0.660 27.737 0.684 ; + END + END w0_wmask_in[24] + PIN w0_wmask_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 0.852 27.737 0.876 ; + END + END w0_wmask_in[25] + PIN w0_wmask_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 1.044 27.737 1.068 ; + END + END w0_wmask_in[26] + PIN w0_wmask_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 1.236 27.737 1.260 ; + END + END w0_wmask_in[27] + PIN w0_wmask_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 1.428 27.737 1.452 ; + END + END w0_wmask_in[28] + PIN w0_wmask_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 1.620 27.737 1.644 ; + END + END w0_wmask_in[29] + PIN w0_wmask_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 1.812 27.737 1.836 ; + END + END w0_wmask_in[30] + PIN w0_wmask_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 2.004 27.737 2.028 ; + END + END w0_wmask_in[31] + PIN w0_wmask_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 2.196 27.737 2.220 ; + END + END w0_wmask_in[32] + PIN w0_wmask_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 2.388 27.737 2.412 ; + END + END w0_wmask_in[33] + PIN w0_wmask_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 2.580 27.737 2.604 ; + END + END w0_wmask_in[34] + PIN w0_wmask_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 2.772 27.737 2.796 ; + END + END w0_wmask_in[35] + PIN w0_wmask_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 2.964 27.737 2.988 ; + END + END w0_wmask_in[36] + PIN w0_wmask_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 3.156 27.737 3.180 ; + END + END w0_wmask_in[37] + PIN w0_wmask_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 3.348 27.737 3.372 ; + END + END w0_wmask_in[38] + PIN w0_wmask_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 3.540 27.737 3.564 ; + END + END w0_wmask_in[39] + PIN w0_wmask_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 3.732 27.737 3.756 ; + END + END w0_wmask_in[40] + PIN w0_wmask_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 3.924 27.737 3.948 ; + END + END w0_wmask_in[41] + PIN w0_wmask_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 4.116 27.737 4.140 ; + END + END w0_wmask_in[42] + PIN w0_wmask_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 4.308 27.737 4.332 ; + END + END w0_wmask_in[43] + PIN w0_wmask_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 10.485 0.225 10.539 ; + END + END w0_wmask_in[44] + PIN w0_wmask_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 10.485 0.513 10.539 ; + END + END w0_wmask_in[45] + PIN w0_wmask_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 10.485 0.801 10.539 ; + END + END w0_wmask_in[46] + PIN w0_wmask_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 10.485 1.089 10.539 ; + END + END w0_wmask_in[47] + PIN w0_wmask_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 10.485 1.377 10.539 ; + END + END w0_wmask_in[48] + PIN w0_wmask_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 10.485 1.665 10.539 ; + END + END w0_wmask_in[49] + PIN w0_wmask_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 10.485 1.953 10.539 ; + END + END w0_wmask_in[50] + PIN w0_wmask_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 10.485 2.241 10.539 ; + END + END w0_wmask_in[51] + PIN w0_wmask_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 10.485 2.529 10.539 ; + END + END w0_wmask_in[52] + PIN w0_wmask_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 10.485 2.817 10.539 ; + END + END w0_wmask_in[53] + PIN w0_wmask_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 10.485 3.105 10.539 ; + END + END w0_wmask_in[54] + PIN w0_wmask_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 10.485 3.393 10.539 ; + END + END w0_wmask_in[55] + PIN w0_wmask_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 10.485 3.681 10.539 ; + END + END w0_wmask_in[56] + PIN w0_wmask_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 10.485 3.969 10.539 ; + END + END w0_wmask_in[57] + PIN w0_wmask_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 10.485 4.257 10.539 ; + END + END w0_wmask_in[58] + PIN w0_wmask_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 10.485 4.545 10.539 ; + END + END w0_wmask_in[59] + PIN w0_wmask_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 10.485 4.833 10.539 ; + END + END w0_wmask_in[60] + PIN w0_wmask_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 10.485 5.121 10.539 ; + END + END w0_wmask_in[61] + PIN w0_wmask_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 10.485 5.409 10.539 ; + END + END w0_wmask_in[62] + PIN w0_wmask_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 10.485 5.697 10.539 ; + END + END w0_wmask_in[63] + PIN w0_wmask_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 10.485 5.985 10.539 ; + END + END w0_wmask_in[64] + PIN w0_wmask_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 10.485 6.273 10.539 ; + END + END w0_wmask_in[65] + PIN w0_wmask_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 10.485 6.561 10.539 ; + END + END w0_wmask_in[66] + PIN w0_wmask_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 10.485 6.849 10.539 ; + END + END w0_wmask_in[67] + PIN w0_wmask_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 10.485 7.137 10.539 ; + END + END w0_wmask_in[68] + PIN w0_wmask_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 10.485 7.425 10.539 ; + END + END w0_wmask_in[69] + PIN w0_wmask_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 10.485 7.713 10.539 ; + END + END w0_wmask_in[70] + PIN w0_wmask_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 10.485 8.001 10.539 ; + END + END w0_wmask_in[71] + PIN w0_wmask_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 10.485 8.289 10.539 ; + END + END w0_wmask_in[72] + PIN w0_wmask_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 10.485 8.577 10.539 ; + END + END w0_wmask_in[73] + PIN w0_wmask_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 10.485 8.865 10.539 ; + END + END w0_wmask_in[74] + PIN w0_wmask_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 10.485 9.153 10.539 ; + END + END w0_wmask_in[75] + PIN w0_wmask_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 10.485 9.441 10.539 ; + END + END w0_wmask_in[76] + PIN w0_wmask_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 10.485 9.729 10.539 ; + END + END w0_wmask_in[77] + PIN w0_wmask_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 10.485 10.017 10.539 ; + END + END w0_wmask_in[78] + PIN w0_wmask_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 10.485 10.305 10.539 ; + END + END w0_wmask_in[79] + PIN w0_wmask_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 10.485 10.593 10.539 ; + END + END w0_wmask_in[80] + PIN w0_wmask_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 10.485 10.881 10.539 ; + END + END w0_wmask_in[81] + PIN w0_wmask_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 10.485 11.169 10.539 ; + END + END w0_wmask_in[82] + PIN w0_wmask_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 10.485 11.457 10.539 ; + END + END w0_wmask_in[83] + PIN w0_wmask_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 10.485 11.745 10.539 ; + END + END w0_wmask_in[84] + PIN w0_wmask_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 10.485 12.033 10.539 ; + END + END w0_wmask_in[85] + PIN w0_wmask_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 10.485 12.321 10.539 ; + END + END w0_wmask_in[86] + PIN w0_wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.500 0.072 4.524 ; + END + END w0_wd_in[0] + PIN w0_wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.692 0.072 4.716 ; + END + END w0_wd_in[1] + PIN w0_wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.884 0.072 4.908 ; + END + END w0_wd_in[2] + PIN w0_wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.076 0.072 5.100 ; + END + END w0_wd_in[3] + PIN w0_wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.268 0.072 5.292 ; + END + END w0_wd_in[4] + PIN w0_wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.460 0.072 5.484 ; + END + END w0_wd_in[5] + PIN w0_wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.652 0.072 5.676 ; + END + END w0_wd_in[6] + PIN w0_wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.844 0.072 5.868 ; + END + END w0_wd_in[7] + PIN w0_wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.036 0.072 6.060 ; + END + END w0_wd_in[8] + PIN w0_wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.228 0.072 6.252 ; + END + END w0_wd_in[9] + PIN w0_wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.420 0.072 6.444 ; + END + END w0_wd_in[10] + PIN w0_wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.612 0.072 6.636 ; + END + END w0_wd_in[11] + PIN w0_wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.804 0.072 6.828 ; + END + END w0_wd_in[12] + PIN w0_wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.996 0.072 7.020 ; + END + END w0_wd_in[13] + PIN w0_wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.188 0.072 7.212 ; + END + END w0_wd_in[14] + PIN w0_wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.380 0.072 7.404 ; + END + END w0_wd_in[15] + PIN w0_wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.572 0.072 7.596 ; + END + END w0_wd_in[16] + PIN w0_wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.764 0.072 7.788 ; + END + END w0_wd_in[17] + PIN w0_wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.956 0.072 7.980 ; + END + END w0_wd_in[18] + PIN w0_wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.148 0.072 8.172 ; + END + END w0_wd_in[19] + PIN w0_wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.340 0.072 8.364 ; + END + END w0_wd_in[20] + PIN w0_wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.532 0.072 8.556 ; + END + END w0_wd_in[21] + PIN w0_wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 4.500 27.737 4.524 ; + END + END w0_wd_in[22] + PIN w0_wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 4.692 27.737 4.716 ; + END + END w0_wd_in[23] + PIN w0_wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 4.884 27.737 4.908 ; + END + END w0_wd_in[24] + PIN w0_wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 5.076 27.737 5.100 ; + END + END w0_wd_in[25] + PIN w0_wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 5.268 27.737 5.292 ; + END + END w0_wd_in[26] + PIN w0_wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 5.460 27.737 5.484 ; + END + END w0_wd_in[27] + PIN w0_wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 5.652 27.737 5.676 ; + END + END w0_wd_in[28] + PIN w0_wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 5.844 27.737 5.868 ; + END + END w0_wd_in[29] + PIN w0_wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 6.036 27.737 6.060 ; + END + END w0_wd_in[30] + PIN w0_wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 6.228 27.737 6.252 ; + END + END w0_wd_in[31] + PIN w0_wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 6.420 27.737 6.444 ; + END + END w0_wd_in[32] + PIN w0_wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 6.612 27.737 6.636 ; + END + END w0_wd_in[33] + PIN w0_wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 6.804 27.737 6.828 ; + END + END w0_wd_in[34] + PIN w0_wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 6.996 27.737 7.020 ; + END + END w0_wd_in[35] + PIN w0_wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 7.188 27.737 7.212 ; + END + END w0_wd_in[36] + PIN w0_wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 7.380 27.737 7.404 ; + END + END w0_wd_in[37] + PIN w0_wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 7.572 27.737 7.596 ; + END + END w0_wd_in[38] + PIN w0_wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 7.764 27.737 7.788 ; + END + END w0_wd_in[39] + PIN w0_wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 7.956 27.737 7.980 ; + END + END w0_wd_in[40] + PIN w0_wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 8.148 27.737 8.172 ; + END + END w0_wd_in[41] + PIN w0_wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 8.340 27.737 8.364 ; + END + END w0_wd_in[42] + PIN w0_wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 8.532 27.737 8.556 ; + END + END w0_wd_in[43] + PIN w0_wd_in[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.207 0.000 0.225 0.054 ; + END + END w0_wd_in[44] + PIN w0_wd_in[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.495 0.000 0.513 0.054 ; + END + END w0_wd_in[45] + PIN w0_wd_in[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 0.783 0.000 0.801 0.054 ; + END + END w0_wd_in[46] + PIN w0_wd_in[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.071 0.000 1.089 0.054 ; + END + END w0_wd_in[47] + PIN w0_wd_in[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.359 0.000 1.377 0.054 ; + END + END w0_wd_in[48] + PIN w0_wd_in[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.647 0.000 1.665 0.054 ; + END + END w0_wd_in[49] + PIN w0_wd_in[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 1.935 0.000 1.953 0.054 ; + END + END w0_wd_in[50] + PIN w0_wd_in[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.223 0.000 2.241 0.054 ; + END + END w0_wd_in[51] + PIN w0_wd_in[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.511 0.000 2.529 0.054 ; + END + END w0_wd_in[52] + PIN w0_wd_in[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 2.799 0.000 2.817 0.054 ; + END + END w0_wd_in[53] + PIN w0_wd_in[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.087 0.000 3.105 0.054 ; + END + END w0_wd_in[54] + PIN w0_wd_in[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.375 0.000 3.393 0.054 ; + END + END w0_wd_in[55] + PIN w0_wd_in[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.663 0.000 3.681 0.054 ; + END + END w0_wd_in[56] + PIN w0_wd_in[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 3.951 0.000 3.969 0.054 ; + END + END w0_wd_in[57] + PIN w0_wd_in[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.239 0.000 4.257 0.054 ; + END + END w0_wd_in[58] + PIN w0_wd_in[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.527 0.000 4.545 0.054 ; + END + END w0_wd_in[59] + PIN w0_wd_in[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 4.815 0.000 4.833 0.054 ; + END + END w0_wd_in[60] + PIN w0_wd_in[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.103 0.000 5.121 0.054 ; + END + END w0_wd_in[61] + PIN w0_wd_in[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.391 0.000 5.409 0.054 ; + END + END w0_wd_in[62] + PIN w0_wd_in[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.679 0.000 5.697 0.054 ; + END + END w0_wd_in[63] + PIN w0_wd_in[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 5.967 0.000 5.985 0.054 ; + END + END w0_wd_in[64] + PIN w0_wd_in[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.255 0.000 6.273 0.054 ; + END + END w0_wd_in[65] + PIN w0_wd_in[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.543 0.000 6.561 0.054 ; + END + END w0_wd_in[66] + PIN w0_wd_in[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 6.831 0.000 6.849 0.054 ; + END + END w0_wd_in[67] + PIN w0_wd_in[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.119 0.000 7.137 0.054 ; + END + END w0_wd_in[68] + PIN w0_wd_in[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.407 0.000 7.425 0.054 ; + END + END w0_wd_in[69] + PIN w0_wd_in[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.695 0.000 7.713 0.054 ; + END + END w0_wd_in[70] + PIN w0_wd_in[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 7.983 0.000 8.001 0.054 ; + END + END w0_wd_in[71] + PIN w0_wd_in[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.271 0.000 8.289 0.054 ; + END + END w0_wd_in[72] + PIN w0_wd_in[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.559 0.000 8.577 0.054 ; + END + END w0_wd_in[73] + PIN w0_wd_in[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 8.847 0.000 8.865 0.054 ; + END + END w0_wd_in[74] + PIN w0_wd_in[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.135 0.000 9.153 0.054 ; + END + END w0_wd_in[75] + PIN w0_wd_in[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.423 0.000 9.441 0.054 ; + END + END w0_wd_in[76] + PIN w0_wd_in[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.711 0.000 9.729 0.054 ; + END + END w0_wd_in[77] + PIN w0_wd_in[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 9.999 0.000 10.017 0.054 ; + END + END w0_wd_in[78] + PIN w0_wd_in[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.287 0.000 10.305 0.054 ; + END + END w0_wd_in[79] + PIN w0_wd_in[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.575 0.000 10.593 0.054 ; + END + END w0_wd_in[80] + PIN w0_wd_in[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 10.863 0.000 10.881 0.054 ; + END + END w0_wd_in[81] + PIN w0_wd_in[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.151 0.000 11.169 0.054 ; + END + END w0_wd_in[82] + PIN w0_wd_in[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.439 0.000 11.457 0.054 ; + END + END w0_wd_in[83] + PIN w0_wd_in[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 11.727 0.000 11.745 0.054 ; + END + END w0_wd_in[84] + PIN w0_wd_in[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.015 0.000 12.033 0.054 ; + END + END w0_wd_in[85] + PIN w0_wd_in[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.303 0.000 12.321 0.054 ; + END + END w0_wd_in[86] + PIN r0_rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 0.000 12.609 0.054 ; + END + END r0_rd_out[0] + PIN r0_rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 0.000 12.897 0.054 ; + END + END r0_rd_out[1] + PIN r0_rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 0.000 13.185 0.054 ; + END + END r0_rd_out[2] + PIN r0_rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 0.000 13.473 0.054 ; + END + END r0_rd_out[3] + PIN r0_rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 0.000 13.761 0.054 ; + END + END r0_rd_out[4] + PIN r0_rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 0.000 14.049 0.054 ; + END + END r0_rd_out[5] + PIN r0_rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 0.000 14.337 0.054 ; + END + END r0_rd_out[6] + PIN r0_rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 0.000 14.625 0.054 ; + END + END r0_rd_out[7] + PIN r0_rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 0.000 14.913 0.054 ; + END + END r0_rd_out[8] + PIN r0_rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 0.000 15.201 0.054 ; + END + END r0_rd_out[9] + PIN r0_rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 0.000 15.489 0.054 ; + END + END r0_rd_out[10] + PIN r0_rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 0.000 15.777 0.054 ; + END + END r0_rd_out[11] + PIN r0_rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 0.000 16.065 0.054 ; + END + END r0_rd_out[12] + PIN r0_rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 0.000 16.353 0.054 ; + END + END r0_rd_out[13] + PIN r0_rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 0.000 16.641 0.054 ; + END + END r0_rd_out[14] + PIN r0_rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 0.000 16.929 0.054 ; + END + END r0_rd_out[15] + PIN r0_rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 0.000 17.217 0.054 ; + END + END r0_rd_out[16] + PIN r0_rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 0.000 17.505 0.054 ; + END + END r0_rd_out[17] + PIN r0_rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 0.000 17.793 0.054 ; + END + END r0_rd_out[18] + PIN r0_rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 0.000 18.081 0.054 ; + END + END r0_rd_out[19] + PIN r0_rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 0.000 18.369 0.054 ; + END + END r0_rd_out[20] + PIN r0_rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 0.000 18.657 0.054 ; + END + END r0_rd_out[21] + PIN r0_rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 0.000 18.945 0.054 ; + END + END r0_rd_out[22] + PIN r0_rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 0.000 19.233 0.054 ; + END + END r0_rd_out[23] + PIN r0_rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 0.000 19.521 0.054 ; + END + END r0_rd_out[24] + PIN r0_rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 0.000 19.809 0.054 ; + END + END r0_rd_out[25] + PIN r0_rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 0.000 20.097 0.054 ; + END + END r0_rd_out[26] + PIN r0_rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 0.000 20.385 0.054 ; + END + END r0_rd_out[27] + PIN r0_rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 0.000 20.673 0.054 ; + END + END r0_rd_out[28] + PIN r0_rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 0.000 20.961 0.054 ; + END + END r0_rd_out[29] + PIN r0_rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 0.000 21.249 0.054 ; + END + END r0_rd_out[30] + PIN r0_rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 0.000 21.537 0.054 ; + END + END r0_rd_out[31] + PIN r0_rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 0.000 21.825 0.054 ; + END + END r0_rd_out[32] + PIN r0_rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 0.000 22.113 0.054 ; + END + END r0_rd_out[33] + PIN r0_rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 0.000 22.401 0.054 ; + END + END r0_rd_out[34] + PIN r0_rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 0.000 22.689 0.054 ; + END + END r0_rd_out[35] + PIN r0_rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 0.000 22.977 0.054 ; + END + END r0_rd_out[36] + PIN r0_rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 0.000 23.265 0.054 ; + END + END r0_rd_out[37] + PIN r0_rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 0.000 23.553 0.054 ; + END + END r0_rd_out[38] + PIN r0_rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 0.000 23.841 0.054 ; + END + END r0_rd_out[39] + PIN r0_rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 0.000 24.129 0.054 ; + END + END r0_rd_out[40] + PIN r0_rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 0.000 24.417 0.054 ; + END + END r0_rd_out[41] + PIN r0_rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 0.000 24.705 0.054 ; + END + END r0_rd_out[42] + PIN r0_rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 0.000 24.993 0.054 ; + END + END r0_rd_out[43] + PIN r0_rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.591 10.485 12.609 10.539 ; + END + END r0_rd_out[44] + PIN r0_rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 12.879 10.485 12.897 10.539 ; + END + END r0_rd_out[45] + PIN r0_rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.167 10.485 13.185 10.539 ; + END + END r0_rd_out[46] + PIN r0_rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.455 10.485 13.473 10.539 ; + END + END r0_rd_out[47] + PIN r0_rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 13.743 10.485 13.761 10.539 ; + END + END r0_rd_out[48] + PIN r0_rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.031 10.485 14.049 10.539 ; + END + END r0_rd_out[49] + PIN r0_rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.319 10.485 14.337 10.539 ; + END + END r0_rd_out[50] + PIN r0_rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.607 10.485 14.625 10.539 ; + END + END r0_rd_out[51] + PIN r0_rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 14.895 10.485 14.913 10.539 ; + END + END r0_rd_out[52] + PIN r0_rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.183 10.485 15.201 10.539 ; + END + END r0_rd_out[53] + PIN r0_rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.471 10.485 15.489 10.539 ; + END + END r0_rd_out[54] + PIN r0_rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 15.759 10.485 15.777 10.539 ; + END + END r0_rd_out[55] + PIN r0_rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.047 10.485 16.065 10.539 ; + END + END r0_rd_out[56] + PIN r0_rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.335 10.485 16.353 10.539 ; + END + END r0_rd_out[57] + PIN r0_rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.623 10.485 16.641 10.539 ; + END + END r0_rd_out[58] + PIN r0_rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 16.911 10.485 16.929 10.539 ; + END + END r0_rd_out[59] + PIN r0_rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.199 10.485 17.217 10.539 ; + END + END r0_rd_out[60] + PIN r0_rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.487 10.485 17.505 10.539 ; + END + END r0_rd_out[61] + PIN r0_rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 17.775 10.485 17.793 10.539 ; + END + END r0_rd_out[62] + PIN r0_rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.063 10.485 18.081 10.539 ; + END + END r0_rd_out[63] + PIN r0_rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.351 10.485 18.369 10.539 ; + END + END r0_rd_out[64] + PIN r0_rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.639 10.485 18.657 10.539 ; + END + END r0_rd_out[65] + PIN r0_rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 18.927 10.485 18.945 10.539 ; + END + END r0_rd_out[66] + PIN r0_rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.215 10.485 19.233 10.539 ; + END + END r0_rd_out[67] + PIN r0_rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.503 10.485 19.521 10.539 ; + END + END r0_rd_out[68] + PIN r0_rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 19.791 10.485 19.809 10.539 ; + END + END r0_rd_out[69] + PIN r0_rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.079 10.485 20.097 10.539 ; + END + END r0_rd_out[70] + PIN r0_rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.367 10.485 20.385 10.539 ; + END + END r0_rd_out[71] + PIN r0_rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.655 10.485 20.673 10.539 ; + END + END r0_rd_out[72] + PIN r0_rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 20.943 10.485 20.961 10.539 ; + END + END r0_rd_out[73] + PIN r0_rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.231 10.485 21.249 10.539 ; + END + END r0_rd_out[74] + PIN r0_rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.519 10.485 21.537 10.539 ; + END + END r0_rd_out[75] + PIN r0_rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 21.807 10.485 21.825 10.539 ; + END + END r0_rd_out[76] + PIN r0_rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.095 10.485 22.113 10.539 ; + END + END r0_rd_out[77] + PIN r0_rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.383 10.485 22.401 10.539 ; + END + END r0_rd_out[78] + PIN r0_rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.671 10.485 22.689 10.539 ; + END + END r0_rd_out[79] + PIN r0_rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 22.959 10.485 22.977 10.539 ; + END + END r0_rd_out[80] + PIN r0_rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.247 10.485 23.265 10.539 ; + END + END r0_rd_out[81] + PIN r0_rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.535 10.485 23.553 10.539 ; + END + END r0_rd_out[82] + PIN r0_rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 23.823 10.485 23.841 10.539 ; + END + END r0_rd_out[83] + PIN r0_rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.111 10.485 24.129 10.539 ; + END + END r0_rd_out[84] + PIN r0_rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.399 10.485 24.417 10.539 ; + END + END r0_rd_out[85] + PIN r0_rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.687 10.485 24.705 10.539 ; + END + END r0_rd_out[86] + PIN w0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.724 0.072 8.748 ; + END + END w0_addr_in[0] + PIN w0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.916 0.072 8.940 ; + END + END w0_addr_in[1] + PIN w0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 8.724 27.737 8.748 ; + END + END w0_addr_in[2] + PIN w0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 8.916 27.737 8.940 ; + END + END w0_addr_in[3] + PIN r0_addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.108 0.072 9.132 ; + END + END r0_addr_in[0] + PIN r0_addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.300 0.072 9.324 ; + END + END r0_addr_in[1] + PIN r0_addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 9.108 27.737 9.132 ; + END + END r0_addr_in[2] + PIN r0_addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 27.665 9.300 27.737 9.324 ; + END + END r0_addr_in[3] + PIN w0_we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 24.975 10.485 24.993 10.539 ; + END + END w0_we_in + PIN w0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.263 10.485 25.281 10.539 ; + END + END w0_ce_in + PIN w0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.551 10.485 25.569 10.539 ; + END + END w0_clk + PIN r0_ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 25.839 10.485 25.857 10.539 ; + END + END r0_ce_in + PIN r0_clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M3 ; + RECT 26.127 10.485 26.145 10.539 ; + END + END r0_clk + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.216 0.240 27.521 0.336 ; + RECT 0.216 1.008 27.521 1.104 ; + RECT 0.216 1.776 27.521 1.872 ; + RECT 0.216 2.544 27.521 2.640 ; + RECT 0.216 3.312 27.521 3.408 ; + RECT 0.216 4.080 27.521 4.176 ; + RECT 0.216 4.848 27.521 4.944 ; + RECT 0.216 5.616 27.521 5.712 ; + RECT 0.216 6.384 27.521 6.480 ; + RECT 0.216 7.152 27.521 7.248 ; + RECT 0.216 7.920 27.521 8.016 ; + RECT 0.216 8.688 27.521 8.784 ; + RECT 0.216 9.456 27.521 9.552 ; + RECT 0.216 10.224 27.521 10.320 ; + END + END VSS + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.216 0.240 27.521 0.336 ; + RECT 0.216 1.008 27.521 1.104 ; + RECT 0.216 1.776 27.521 1.872 ; + RECT 0.216 2.544 27.521 2.640 ; + RECT 0.216 3.312 27.521 3.408 ; + RECT 0.216 4.080 27.521 4.176 ; + RECT 0.216 4.848 27.521 4.944 ; + RECT 0.216 5.616 27.521 5.712 ; + RECT 0.216 6.384 27.521 6.480 ; + RECT 0.216 7.152 27.521 7.248 ; + RECT 0.216 7.920 27.521 8.016 ; + RECT 0.216 8.688 27.521 8.784 ; + RECT 0.216 9.456 27.521 9.552 ; + RECT 0.216 10.224 27.521 10.320 ; + END + END VDD + OBS + LAYER M1 ; + RECT 0 0 27.737 10.539 ; + LAYER M2 ; + RECT 0 0 27.737 10.539 ; + LAYER M3 ; + RECT 0 0 27.737 10.539 ; + LAYER M4 ; + RECT 0 0 27.737 10.539 ; + END +END fakeram_87x16_1r1w + +END LIBRARY diff --git a/designs/asap7/vortex/sram/lib/fakeram_128x256_1rw.lib b/designs/asap7/vortex/sram/lib/fakeram_128x256_1rw.lib new file mode 100644 index 0000000..f712ac8 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_128x256_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_128x256_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-15 03:44:17Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_128x256_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_128x256_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_128x256_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_128x256_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_128x256_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_128x256_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 128; + bit_from : 127; + bit_to : 0 ; + downto : true ; + } + type (fakeram_128x256_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_128x256_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 16; + bit_from : 15; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_128x256_1rw) { + area : 939.124; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 128; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_128x256_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_128x256_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_128x256_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_128x256_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_128x256_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_128x256_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_128x256_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_128x256_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_128x256_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_128x256_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x256_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x256_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_128x64_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_128x64_1r1w.lib new file mode 100644 index 0000000..311195e --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_128x64_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_128x64_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:49:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_128x64_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_128x64_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_128x64_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_128x64_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_128x64_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_128x64_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 128; + bit_from : 127; + bit_to : 0 ; + downto : true ; + } + type (fakeram_128x64_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_128x64_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 16; + bit_from : 15; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_128x64_1r1w) { + area : 925.222; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 128; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_128x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_128x64_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_128x64_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_128x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_128x64_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_128x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_128x64_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_128x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_128x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_128x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_128x64_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_128x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_128x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_192x16_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_192x16_1r1w.lib new file mode 100644 index 0000000..52cd363 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_192x16_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_192x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-15 03:44:17Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_192x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_192x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_192x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_192x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_192x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_192x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 192; + bit_from : 191; + bit_to : 0 ; + downto : true ; + } + type (fakeram_192x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } + type (fakeram_192x16_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 24; + bit_from : 23; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_192x16_1r1w) { + area : 1214.343; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 192; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_192x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_192x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_192x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_192x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_192x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_192x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_192x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_192x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_192x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_192x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_192x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_192x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_192x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_193x16_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_193x16_1r1w.lib new file mode 100644 index 0000000..3a28246 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_193x16_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_193x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:49:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_193x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_193x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_193x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_193x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_193x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_193x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 193; + bit_from : 192; + bit_to : 0 ; + downto : true ; + } + type (fakeram_193x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } + type (fakeram_193x16_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 24; + bit_from : 23; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_193x16_1r1w) { + area : 1226.148; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 193; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_193x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_193x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_193x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_193x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_193x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_193x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_193x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_193x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_193x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_193x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_193x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_193x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_193x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_21x256_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_21x256_1r1w.lib new file mode 100644 index 0000000..bd7239c --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_21x256_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_21x256_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-15 03:44:17Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_21x256_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_21x256_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_21x256_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_21x256_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_21x256_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_21x256_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 21; + bit_from : 20; + bit_to : 0 ; + downto : true ; + } + type (fakeram_21x256_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 8; + bit_from : 7; + bit_to : 0 ; + downto : true ; + } + type (fakeram_21x256_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_21x256_1r1w) { + area : 481.612; + interface_timing : true; + memory() { + type : ram; + address_width : 8; + word_width : 21; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_21x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_21x256_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_21x256_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_21x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_21x256_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_21x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_21x256_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_21x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_21x256_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_21x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_21x256_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x256_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x256_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_21x64_1r1w.lib similarity index 65% rename from designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib rename to designs/asap7/vortex/sram/lib/fakeram_21x64_1r1w.lib index 2caeb2d..a20a940 100644 --- a/designs/asap7/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib +++ b/designs/asap7/vortex/sram/lib/fakeram_21x64_1r1w.lib @@ -1,8 +1,8 @@ -library(fakeram_512x2048_1r1w) { +library(fakeram_21x64_1r1w) { technology (cmos); delay_model : table_lookup; revision : 1.0; - date : "2025-10-02 18:11:03Z"; + date : "2026-03-11 04:49:00Z"; comment : "SRAM"; time_unit : "1ns"; voltage_unit : "1V"; @@ -46,54 +46,62 @@ library(fakeram_512x2048_1r1w) { output_threshold_pct_rise : 50.000; - lu_table_template(fakeram_512x2048_1r1w_mem_out_delay_template) { + lu_table_template(fakeram_21x64_1r1w_mem_out_delay_template) { variable_1 : input_net_transition; variable_2 : total_output_net_capacitance; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - lu_table_template(fakeram_512x2048_1r1w_mem_out_slew_template) { + lu_table_template(fakeram_21x64_1r1w_mem_out_slew_template) { variable_1 : total_output_net_capacitance; index_1 ("1000, 1001"); } - lu_table_template(fakeram_512x2048_1r1w_constraint_template) { + lu_table_template(fakeram_21x64_1r1w_constraint_template) { variable_1 : related_pin_transition; variable_2 : constrained_pin_transition; index_1 ("1000, 1001"); index_2 ("1000, 1001"); } - power_lut_template(fakeram_512x2048_1r1w_energy_template_clkslew) { + power_lut_template(fakeram_21x64_1r1w_energy_template_clkslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } - power_lut_template(fakeram_512x2048_1r1w_energy_template_sigslew) { + power_lut_template(fakeram_21x64_1r1w_energy_template_sigslew) { variable_1 : input_transition_time; index_1 ("1000, 1001"); } library_features(report_delay_calculation); - type (fakeram_512x2048_1r1w_DATA) { + type (fakeram_21x64_1r1w_DATA) { base_type : array ; data_type : bit ; - bit_width : 512; - bit_from : 511; + bit_width : 21; + bit_from : 20; bit_to : 0 ; downto : true ; } - type (fakeram_512x2048_1r1w_ADDRESS) { + type (fakeram_21x64_1r1w_ADDRESS) { base_type : array ; data_type : bit ; - bit_width : 11; - bit_from : 10; + bit_width : 6; + bit_from : 5; bit_to : 0 ; downto : true ; } -cell(fakeram_512x2048_1r1w) { - area : 44030.325; + type (fakeram_21x64_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_21x64_1r1w) { + area : 134.639; interface_timing : true; memory() { type : ram; - address_width : 11; - word_width : 512; + address_width : 6; + word_width : 21; } pin(r0_clk) { direction : input; @@ -101,11 +109,11 @@ cell(fakeram_512x2048_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_clkslew) { + rise_power(fakeram_21x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_512x2048_1r1w_energy_template_clkslew) { + fall_power(fakeram_21x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -118,11 +126,11 @@ cell(fakeram_512x2048_1r1w) { clock : true; min_period : 0.157 ; internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_clkslew) { + rise_power(fakeram_21x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } - fall_power(fakeram_512x2048_1r1w_energy_template_clkslew) { + fall_power(fakeram_21x64_1r1w_energy_template_clkslew) { index_1 ("0.009, 0.227"); values ("1.345, 1.345") } @@ -130,7 +138,7 @@ cell(fakeram_512x2048_1r1w) { } bus(r0_rd_out) { - bus_type : fakeram_512x2048_1r1w_DATA; + bus_type : fakeram_21x64_1r1w_DATA; direction : output; max_capacitance : 0.500; memory_read() { @@ -140,7 +148,7 @@ cell(fakeram_512x2048_1r1w) { related_pin : "r0_clk" ; timing_type : rising_edge; timing_sense : non_unate; - cell_rise(fakeram_512x2048_1r1w_mem_out_delay_template) { + cell_rise(fakeram_21x64_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -148,7 +156,7 @@ cell(fakeram_512x2048_1r1w) { "0.218, 0.218" \ ) } - cell_fall(fakeram_512x2048_1r1w_mem_out_delay_template) { + cell_fall(fakeram_21x64_1r1w_mem_out_delay_template) { index_1 ("0.009, 0.227"); index_2 ("0.005, 0.500"); values ( \ @@ -156,11 +164,11 @@ cell(fakeram_512x2048_1r1w) { "0.218, 0.218" \ ) } - rise_transition(fakeram_512x2048_1r1w_mem_out_slew_template) { + rise_transition(fakeram_21x64_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } - fall_transition(fakeram_512x2048_1r1w_mem_out_slew_template) { + fall_transition(fakeram_21x64_1r1w_mem_out_slew_template) { index_1 ("0.005, 0.500"); values ("0.009, 0.227") } @@ -172,7 +180,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -180,7 +188,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -192,7 +200,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -200,7 +208,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -210,11 +218,11 @@ cell(fakeram_512x2048_1r1w) { } } internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -226,7 +234,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -234,7 +242,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -246,7 +254,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -254,7 +262,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -264,11 +272,11 @@ cell(fakeram_512x2048_1r1w) { } } internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } @@ -280,7 +288,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -288,7 +296,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -300,7 +308,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -308,7 +316,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -318,18 +326,89 @@ cell(fakeram_512x2048_1r1w) { } } internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_wd_in) { - bus_type : fakeram_512x2048_1r1w_DATA; + bus_type : fakeram_21x64_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_21x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_21x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_21x64_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_21x64_1r1w_DATA; memory_write() { address : w0_addr_in; clocked_on : "w0_clk"; @@ -339,7 +418,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -347,7 +426,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -359,7 +438,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -367,7 +446,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -378,35 +457,35 @@ cell(fakeram_512x2048_1r1w) { } internal_power(){ when : "(! (w0_we_in) )"; - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } internal_power(){ when : "(w0_we_in)"; - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(r0_addr_in) { - bus_type : fakeram_512x2048_1r1w_ADDRESS; + bus_type : fakeram_21x64_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : r0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -414,7 +493,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -426,7 +505,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : r0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -434,7 +513,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -444,24 +523,24 @@ cell(fakeram_512x2048_1r1w) { } } internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } } } bus(w0_addr_in) { - bus_type : fakeram_512x2048_1r1w_ADDRESS; + bus_type : fakeram_21x64_1r1w_ADDRESS; direction : input; capacitance : 0.005; timing() { related_pin : w0_clk; timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -469,7 +548,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -481,7 +560,7 @@ cell(fakeram_512x2048_1r1w) { timing() { related_pin : w0_clk; timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { + rise_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -489,7 +568,7 @@ cell(fakeram_512x2048_1r1w) { "0.050, 0.050" \ ) } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { + fall_constraint(fakeram_21x64_1r1w_constraint_template) { index_1 ("0.009, 0.227"); index_2 ("0.009, 0.227"); values ( \ @@ -499,11 +578,11 @@ cell(fakeram_512x2048_1r1w) { } } internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + rise_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { + fall_power(fakeram_21x64_1r1w_energy_template_sigslew) { index_1 ("0.009, 0.227"); values ("0.013, 0.013") } diff --git a/designs/asap7/vortex/sram/lib/fakeram_32x1024_1rw.lib b/designs/asap7/vortex/sram/lib/fakeram_32x1024_1rw.lib new file mode 100644 index 0000000..4e8cd51 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_32x1024_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_32x1024_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:59:32Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_32x1024_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_32x1024_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_32x1024_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_32x1024_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_32x1024_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_32x1024_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 32; + bit_from : 31; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x1024_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 10; + bit_from : 9; + bit_to : 0 ; + downto : true ; + } + type (fakeram_32x1024_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_32x1024_1rw) { + area : 763.055; + interface_timing : true; + memory() { + type : ram; + address_width : 10; + word_width : 32; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_32x1024_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_32x1024_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_32x1024_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_32x1024_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_32x1024_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_32x1024_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_32x1024_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_32x1024_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_32x1024_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_32x1024_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_32x1024_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_32x1024_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_512x64_1rw.lib b/designs/asap7/vortex/sram/lib/fakeram_512x64_1rw.lib new file mode 100644 index 0000000..4959708 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_512x64_1rw.lib @@ -0,0 +1,468 @@ +library(fakeram_512x64_1rw) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:59:32Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_512x64_1rw_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_512x64_1rw_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_512x64_1rw_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_512x64_1rw_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_512x64_1rw_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_512x64_1rw_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 512; + bit_from : 511; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x64_1rw_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 6; + bit_from : 5; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x64_1rw_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 64; + bit_from : 63; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_512x64_1rw) { + area : 3756.497; + interface_timing : true; + memory() { + type : ram; + address_width : 6; + word_width : 512; + } + pin(rw0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_512x64_1rw_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rw0_rd_out) { + bus_type : fakeram_512x64_1rw_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "rw0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_512x64_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_512x64_1rw_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_512x64_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_512x64_1rw_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(rw0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(rw0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_addr_in) { + bus_type : fakeram_512x64_1rw_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wd_in) { + bus_type : fakeram_512x64_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(rw0_wmask_in) { + bus_type : fakeram_512x64_1rw_DATA; + memory_write() { + address : rw0_addr_in; + clocked_on : "rw0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : rw0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : rw0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x64_1rw_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (rw0_we_in) )"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(rw0_we_in)"; + rise_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x64_1rw_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_560x4_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_560x4_1r1w.lib new file mode 100644 index 0000000..0fc290c --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_560x4_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_560x4_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:49:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_560x4_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_560x4_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_560x4_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_560x4_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_560x4_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_560x4_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 560; + bit_from : 559; + bit_to : 0 ; + downto : true ; + } + type (fakeram_560x4_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } + type (fakeram_560x4_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 70; + bit_from : 69; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_560x4_1r1w) { + area : 8980.947; + interface_timing : true; + memory() { + type : ram; + address_width : 2; + word_width : 560; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_560x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_560x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_560x4_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_560x4_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_560x4_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_560x4_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_560x4_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_560x4_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_560x4_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_560x4_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_560x4_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_560x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_560x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_654x4_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_654x4_1r1w.lib new file mode 100644 index 0000000..b933c95 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_654x4_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_654x4_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:49:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_654x4_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_654x4_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_654x4_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_654x4_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_654x4_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_654x4_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 654; + bit_from : 653; + bit_to : 0 ; + downto : true ; + } + type (fakeram_654x4_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 2; + bit_from : 1; + bit_to : 0 ; + downto : true ; + } + type (fakeram_654x4_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 81; + bit_from : 80; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_654x4_1r1w) { + area : 12224.081; + interface_timing : true; + memory() { + type : ram; + address_width : 2; + word_width : 654; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_654x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_654x4_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_654x4_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_654x4_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_654x4_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_654x4_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_654x4_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_654x4_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_654x4_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_654x4_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_654x4_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_654x4_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_654x4_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_85x16_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_85x16_1r1w.lib new file mode 100644 index 0000000..b96d3c9 --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_85x16_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_85x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-15 03:44:17Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_85x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_85x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_85x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_85x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_85x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_85x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 85; + bit_from : 84; + bit_to : 0 ; + downto : true ; + } + type (fakeram_85x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } + type (fakeram_85x16_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 10; + bit_from : 9; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_85x16_1r1w) { + area : 280.810; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 85; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_85x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_85x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_85x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_85x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_85x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_85x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_85x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_85x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_85x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_85x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_85x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_85x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_85x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/asap7/vortex/sram/lib/fakeram_87x16_1r1w.lib b/designs/asap7/vortex/sram/lib/fakeram_87x16_1r1w.lib new file mode 100644 index 0000000..882162a --- /dev/null +++ b/designs/asap7/vortex/sram/lib/fakeram_87x16_1r1w.lib @@ -0,0 +1,594 @@ +library(fakeram_87x16_1r1w) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-03-11 04:59:32Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_87x16_1r1w_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_87x16_1r1w_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_87x16_1r1w_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_87x16_1r1w_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_87x16_1r1w_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_87x16_1r1w_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 87; + bit_from : 86; + bit_to : 0 ; + downto : true ; + } + type (fakeram_87x16_1r1w_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3; + bit_to : 0 ; + downto : true ; + } + type (fakeram_87x16_1r1w_WMASK) { + base_type : array ; + data_type : bit ; + bit_width : 10; + bit_from : 9; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_87x16_1r1w) { + area : 292.320; + interface_timing : true; + memory() { + type : ram; + address_width : 4; + word_width : 87; + } + pin(r0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_87x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + pin(w0_clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_87x16_1r1w_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(r0_rd_out) { + bus_type : fakeram_87x16_1r1w_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : r0_addr_in; + } + timing() { + related_pin : "r0_clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_87x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_87x16_1r1w_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_87x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_87x16_1r1w_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(w0_we_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(r0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(w0_ce_in) { + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wd_in) { + bus_type : fakeram_87x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_wmask_in) { + bus_type : fakeram_87x16_1r1w_DATA; + memory_write() { + address : w0_addr_in; + clocked_on : "w0_clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (w0_we_in) )"; + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(w0_we_in)"; + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(r0_addr_in) { + bus_type : fakeram_87x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : r0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : r0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(w0_addr_in) { + bus_type : fakeram_87x16_1r1w_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : w0_clk; + timing_type : setup_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : w0_clk; + timing_type : hold_rising ; + rise_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_87x16_1r1w_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_87x16_1r1w_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/designs/nangate45/NyuziProcessor/config.mk b/designs/nangate45/NyuziProcessor/config.mk deleted file mode 100644 index 7c984cf..0000000 --- a/designs/nangate45/NyuziProcessor/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -export DESIGN_NAME = NyuziProcessor -export PLATFORM = nangate45 -# Used to specify design-specific src files to clean - --include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk - -export SYNTH_HIERARCHICAL = 1 - -export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_1x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_16x52_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_18x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_20x64_2r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_32x128_2r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x256_1r1w.lef \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lef/fakeram_512x2048_1r1w.lef - - -export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_1x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_16x52_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_18x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_20x64_2r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_32x128_2r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x256_1r1w.lib \ - $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/sram/lib/fakeram_512x2048_1r1w.lib - -export ABC_AREA = 1 - -export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export CORE_UTILIZATION = 49 - -export PLACE_DENSITY_LB_ADDON = 0.1 - -export MACRO_PLACE_HALO = 40 40 - -export TNS_END_PERCENT = 100 - -export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl \ No newline at end of file diff --git a/designs/nangate45/NyuziProcessor/constraint.sdc b/designs/nangate45/NyuziProcessor/constraint.sdc deleted file mode 100644 index 589a57e..0000000 --- a/designs/nangate45/NyuziProcessor/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design NyuziProcessor - -set clk_name clk -set clk_port_name clk -set clk_period 4.5 -set clk_io_pct 0.25 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/nangate45/NyuziProcessor/fastroute.tcl b/designs/nangate45/NyuziProcessor/fastroute.tcl deleted file mode 100644 index 35e3028..0000000 --- a/designs/nangate45/NyuziProcessor/fastroute.tcl +++ /dev/null @@ -1,5 +0,0 @@ -set_global_routing_layer_adjustment metal2-metal3 0.35 -set_global_routing_layer_adjustment metal4-metal5 0.15 -set_global_routing_layer_adjustment metal6-$::env(MAX_ROUTING_LAYER) 0.25 - -set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef deleted file mode 100644 index 0aeab9f..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_16x52_1r1w.lef +++ /dev/null @@ -1,543 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_16x52_1r1w - FOREIGN fakeram_16x52_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 74.860 BY 56.000 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 6.125 0.140 6.195 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 11.445 0.140 11.515 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 16.765 0.140 16.835 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 0.805 74.860 0.875 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 6.125 74.860 6.195 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 11.445 74.860 11.515 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 16.765 74.860 16.835 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 5.475 0.000 5.545 0.140 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 9.845 0.000 9.915 0.140 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 14.215 0.000 14.285 0.140 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 18.585 0.000 18.655 0.140 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.955 0.000 23.025 0.140 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 27.325 0.000 27.395 0.140 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.695 0.000 31.765 0.140 ; - END - END w0_wd_in[15] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 36.065 0.000 36.135 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 40.435 0.000 40.505 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 44.805 0.000 44.875 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 49.175 0.000 49.245 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 53.545 0.000 53.615 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 57.915 0.000 57.985 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 62.285 0.000 62.355 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 66.655 0.000 66.725 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 55.860 1.175 56.000 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 6.615 55.860 6.685 56.000 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 12.125 55.860 12.195 56.000 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 17.635 55.860 17.705 56.000 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 23.145 55.860 23.215 56.000 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 28.655 55.860 28.725 56.000 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 34.165 55.860 34.235 56.000 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 39.675 55.860 39.745 56.000 ; - END - END r0_rd_out[15] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 22.085 0.140 22.155 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 27.405 0.140 27.475 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 32.725 0.140 32.795 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 22.085 74.860 22.155 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 27.405 74.860 27.475 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 32.725 74.860 32.795 ; - END - END w0_addr_in[5] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 38.045 0.140 38.115 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 43.365 0.140 43.435 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 48.685 0.140 48.755 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 38.045 74.860 38.115 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 43.365 74.860 43.435 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 74.720 48.685 74.860 48.755 ; - END - END r0_addr_in[5] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 45.185 55.860 45.255 56.000 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 50.695 55.860 50.765 56.000 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 56.205 55.860 56.275 56.000 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 61.715 55.860 61.785 56.000 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.225 55.860 67.295 56.000 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 55.300 ; - RECT 2.670 0.700 2.950 55.300 ; - RECT 4.910 0.700 5.190 55.300 ; - RECT 7.150 0.700 7.430 55.300 ; - RECT 9.390 0.700 9.670 55.300 ; - RECT 11.630 0.700 11.910 55.300 ; - RECT 13.870 0.700 14.150 55.300 ; - RECT 16.110 0.700 16.390 55.300 ; - RECT 18.350 0.700 18.630 55.300 ; - RECT 20.590 0.700 20.870 55.300 ; - RECT 22.830 0.700 23.110 55.300 ; - RECT 25.070 0.700 25.350 55.300 ; - RECT 27.310 0.700 27.590 55.300 ; - RECT 29.550 0.700 29.830 55.300 ; - RECT 31.790 0.700 32.070 55.300 ; - RECT 34.030 0.700 34.310 55.300 ; - RECT 36.270 0.700 36.550 55.300 ; - RECT 38.510 0.700 38.790 55.300 ; - RECT 40.750 0.700 41.030 55.300 ; - RECT 42.990 0.700 43.270 55.300 ; - RECT 45.230 0.700 45.510 55.300 ; - RECT 47.470 0.700 47.750 55.300 ; - RECT 49.710 0.700 49.990 55.300 ; - RECT 51.950 0.700 52.230 55.300 ; - RECT 54.190 0.700 54.470 55.300 ; - RECT 56.430 0.700 56.710 55.300 ; - RECT 58.670 0.700 58.950 55.300 ; - RECT 60.910 0.700 61.190 55.300 ; - RECT 63.150 0.700 63.430 55.300 ; - RECT 65.390 0.700 65.670 55.300 ; - RECT 67.630 0.700 67.910 55.300 ; - RECT 69.870 0.700 70.150 55.300 ; - RECT 72.110 0.700 72.390 55.300 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 55.300 ; - RECT 2.670 0.700 2.950 55.300 ; - RECT 4.910 0.700 5.190 55.300 ; - RECT 7.150 0.700 7.430 55.300 ; - RECT 9.390 0.700 9.670 55.300 ; - RECT 11.630 0.700 11.910 55.300 ; - RECT 13.870 0.700 14.150 55.300 ; - RECT 16.110 0.700 16.390 55.300 ; - RECT 18.350 0.700 18.630 55.300 ; - RECT 20.590 0.700 20.870 55.300 ; - RECT 22.830 0.700 23.110 55.300 ; - RECT 25.070 0.700 25.350 55.300 ; - RECT 27.310 0.700 27.590 55.300 ; - RECT 29.550 0.700 29.830 55.300 ; - RECT 31.790 0.700 32.070 55.300 ; - RECT 34.030 0.700 34.310 55.300 ; - RECT 36.270 0.700 36.550 55.300 ; - RECT 38.510 0.700 38.790 55.300 ; - RECT 40.750 0.700 41.030 55.300 ; - RECT 42.990 0.700 43.270 55.300 ; - RECT 45.230 0.700 45.510 55.300 ; - RECT 47.470 0.700 47.750 55.300 ; - RECT 49.710 0.700 49.990 55.300 ; - RECT 51.950 0.700 52.230 55.300 ; - RECT 54.190 0.700 54.470 55.300 ; - RECT 56.430 0.700 56.710 55.300 ; - RECT 58.670 0.700 58.950 55.300 ; - RECT 60.910 0.700 61.190 55.300 ; - RECT 63.150 0.700 63.430 55.300 ; - RECT 65.390 0.700 65.670 55.300 ; - RECT 67.630 0.700 67.910 55.300 ; - RECT 69.870 0.700 70.150 55.300 ; - RECT 72.110 0.700 72.390 55.300 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 74.860 56.000 ; - LAYER metal2 ; - RECT 0 0 74.860 56.000 ; - LAYER metal3 ; - RECT 0 0 74.860 56.000 ; - LAYER metal4 ; - RECT 0 0 74.860 56.000 ; - LAYER OVERLAP ; - RECT 0 0 74.860 56.000 ; - END -END fakeram_16x52_1r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef deleted file mode 100644 index f1aa5b9..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_18x256_1r1w.lef +++ /dev/null @@ -1,619 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_18x256_1r1w - FOREIGN fakeram_18x256_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 78.660 BY 229.600 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 18.305 0.140 18.375 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 35.805 0.140 35.875 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 53.305 0.140 53.375 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 70.805 0.140 70.875 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 0.805 78.660 0.875 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 18.305 78.660 18.375 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 35.805 78.660 35.875 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 53.305 78.660 53.375 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 5.285 0.000 5.355 0.140 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 9.465 0.000 9.535 0.140 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 13.645 0.000 13.715 0.140 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 17.825 0.000 17.895 0.140 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.005 0.000 22.075 0.140 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 26.185 0.000 26.255 0.140 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 30.365 0.000 30.435 0.140 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 34.545 0.000 34.615 0.140 ; - END - END w0_wd_in[17] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 38.725 0.000 38.795 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 42.905 0.000 42.975 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 47.085 0.000 47.155 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 51.265 0.000 51.335 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.445 0.000 55.515 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 59.625 0.000 59.695 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 63.805 0.000 63.875 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.985 0.000 68.055 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 72.165 0.000 72.235 0.140 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 229.460 1.175 229.600 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 6.425 229.460 6.495 229.600 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 11.745 229.460 11.815 229.600 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 17.065 229.460 17.135 229.600 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.385 229.460 22.455 229.600 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 27.705 229.460 27.775 229.600 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 33.025 229.460 33.095 229.600 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 38.345 229.460 38.415 229.600 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.665 229.460 43.735 229.600 ; - END - END r0_rd_out[17] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 88.305 0.140 88.375 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 105.805 0.140 105.875 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 123.305 0.140 123.375 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 140.805 0.140 140.875 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 70.805 78.660 70.875 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 88.305 78.660 88.375 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 105.805 78.660 105.875 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 123.305 78.660 123.375 ; - END - END w0_addr_in[7] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 158.305 0.140 158.375 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 175.805 0.140 175.875 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 193.305 0.140 193.375 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 210.805 0.140 210.875 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 140.805 78.660 140.875 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 158.305 78.660 158.375 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 175.805 78.660 175.875 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 78.520 193.305 78.660 193.375 ; - END - END r0_addr_in[7] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.985 229.460 49.055 229.600 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 54.305 229.460 54.375 229.600 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 59.625 229.460 59.695 229.600 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 64.945 229.460 65.015 229.600 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 70.265 229.460 70.335 229.600 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 228.900 ; - RECT 2.670 0.700 2.950 228.900 ; - RECT 4.910 0.700 5.190 228.900 ; - RECT 7.150 0.700 7.430 228.900 ; - RECT 9.390 0.700 9.670 228.900 ; - RECT 11.630 0.700 11.910 228.900 ; - RECT 13.870 0.700 14.150 228.900 ; - RECT 16.110 0.700 16.390 228.900 ; - RECT 18.350 0.700 18.630 228.900 ; - RECT 20.590 0.700 20.870 228.900 ; - RECT 22.830 0.700 23.110 228.900 ; - RECT 25.070 0.700 25.350 228.900 ; - RECT 27.310 0.700 27.590 228.900 ; - RECT 29.550 0.700 29.830 228.900 ; - RECT 31.790 0.700 32.070 228.900 ; - RECT 34.030 0.700 34.310 228.900 ; - RECT 36.270 0.700 36.550 228.900 ; - RECT 38.510 0.700 38.790 228.900 ; - RECT 40.750 0.700 41.030 228.900 ; - RECT 42.990 0.700 43.270 228.900 ; - RECT 45.230 0.700 45.510 228.900 ; - RECT 47.470 0.700 47.750 228.900 ; - RECT 49.710 0.700 49.990 228.900 ; - RECT 51.950 0.700 52.230 228.900 ; - RECT 54.190 0.700 54.470 228.900 ; - RECT 56.430 0.700 56.710 228.900 ; - RECT 58.670 0.700 58.950 228.900 ; - RECT 60.910 0.700 61.190 228.900 ; - RECT 63.150 0.700 63.430 228.900 ; - RECT 65.390 0.700 65.670 228.900 ; - RECT 67.630 0.700 67.910 228.900 ; - RECT 69.870 0.700 70.150 228.900 ; - RECT 72.110 0.700 72.390 228.900 ; - RECT 74.350 0.700 74.630 228.900 ; - RECT 76.590 0.700 76.870 228.900 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 228.900 ; - RECT 2.670 0.700 2.950 228.900 ; - RECT 4.910 0.700 5.190 228.900 ; - RECT 7.150 0.700 7.430 228.900 ; - RECT 9.390 0.700 9.670 228.900 ; - RECT 11.630 0.700 11.910 228.900 ; - RECT 13.870 0.700 14.150 228.900 ; - RECT 16.110 0.700 16.390 228.900 ; - RECT 18.350 0.700 18.630 228.900 ; - RECT 20.590 0.700 20.870 228.900 ; - RECT 22.830 0.700 23.110 228.900 ; - RECT 25.070 0.700 25.350 228.900 ; - RECT 27.310 0.700 27.590 228.900 ; - RECT 29.550 0.700 29.830 228.900 ; - RECT 31.790 0.700 32.070 228.900 ; - RECT 34.030 0.700 34.310 228.900 ; - RECT 36.270 0.700 36.550 228.900 ; - RECT 38.510 0.700 38.790 228.900 ; - RECT 40.750 0.700 41.030 228.900 ; - RECT 42.990 0.700 43.270 228.900 ; - RECT 45.230 0.700 45.510 228.900 ; - RECT 47.470 0.700 47.750 228.900 ; - RECT 49.710 0.700 49.990 228.900 ; - RECT 51.950 0.700 52.230 228.900 ; - RECT 54.190 0.700 54.470 228.900 ; - RECT 56.430 0.700 56.710 228.900 ; - RECT 58.670 0.700 58.950 228.900 ; - RECT 60.910 0.700 61.190 228.900 ; - RECT 63.150 0.700 63.430 228.900 ; - RECT 65.390 0.700 65.670 228.900 ; - RECT 67.630 0.700 67.910 228.900 ; - RECT 69.870 0.700 70.150 228.900 ; - RECT 72.110 0.700 72.390 228.900 ; - RECT 74.350 0.700 74.630 228.900 ; - RECT 76.590 0.700 76.870 228.900 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 78.660 229.600 ; - LAYER metal2 ; - RECT 0 0 78.660 229.600 ; - LAYER metal3 ; - RECT 0 0 78.660 229.600 ; - LAYER metal4 ; - RECT 0 0 78.660 229.600 ; - LAYER OVERLAP ; - RECT 0 0 78.660 229.600 ; - END -END fakeram_18x256_1r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef deleted file mode 100644 index e752b4f..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_1x256_1r1w.lef +++ /dev/null @@ -1,359 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_1x256_1r1w - FOREIGN fakeram_1x256_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 130.910 BY 163.800 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END r0_rd_out[0] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 18.725 0.140 18.795 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 36.645 0.140 36.715 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 54.565 0.140 54.635 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 72.485 0.140 72.555 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 0.805 130.910 0.875 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 18.725 130.910 18.795 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 36.645 130.910 36.715 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 54.565 130.910 54.635 ; - END - END w0_addr_in[7] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 90.405 0.140 90.475 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 108.325 0.140 108.395 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 126.245 0.140 126.315 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 144.165 0.140 144.235 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 72.485 130.910 72.555 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 90.405 130.910 90.475 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 108.325 130.910 108.395 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 130.770 126.245 130.910 126.315 ; - END - END r0_addr_in[7] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 163.660 1.175 163.800 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.385 163.660 22.455 163.800 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.665 163.660 43.735 163.800 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 64.945 163.660 65.015 163.800 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.225 163.660 86.295 163.800 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 163.100 ; - RECT 2.670 0.700 2.950 163.100 ; - RECT 4.910 0.700 5.190 163.100 ; - RECT 7.150 0.700 7.430 163.100 ; - RECT 9.390 0.700 9.670 163.100 ; - RECT 11.630 0.700 11.910 163.100 ; - RECT 13.870 0.700 14.150 163.100 ; - RECT 16.110 0.700 16.390 163.100 ; - RECT 18.350 0.700 18.630 163.100 ; - RECT 20.590 0.700 20.870 163.100 ; - RECT 22.830 0.700 23.110 163.100 ; - RECT 25.070 0.700 25.350 163.100 ; - RECT 27.310 0.700 27.590 163.100 ; - RECT 29.550 0.700 29.830 163.100 ; - RECT 31.790 0.700 32.070 163.100 ; - RECT 34.030 0.700 34.310 163.100 ; - RECT 36.270 0.700 36.550 163.100 ; - RECT 38.510 0.700 38.790 163.100 ; - RECT 40.750 0.700 41.030 163.100 ; - RECT 42.990 0.700 43.270 163.100 ; - RECT 45.230 0.700 45.510 163.100 ; - RECT 47.470 0.700 47.750 163.100 ; - RECT 49.710 0.700 49.990 163.100 ; - RECT 51.950 0.700 52.230 163.100 ; - RECT 54.190 0.700 54.470 163.100 ; - RECT 56.430 0.700 56.710 163.100 ; - RECT 58.670 0.700 58.950 163.100 ; - RECT 60.910 0.700 61.190 163.100 ; - RECT 63.150 0.700 63.430 163.100 ; - RECT 65.390 0.700 65.670 163.100 ; - RECT 67.630 0.700 67.910 163.100 ; - RECT 69.870 0.700 70.150 163.100 ; - RECT 72.110 0.700 72.390 163.100 ; - RECT 74.350 0.700 74.630 163.100 ; - RECT 76.590 0.700 76.870 163.100 ; - RECT 78.830 0.700 79.110 163.100 ; - RECT 81.070 0.700 81.350 163.100 ; - RECT 83.310 0.700 83.590 163.100 ; - RECT 85.550 0.700 85.830 163.100 ; - RECT 87.790 0.700 88.070 163.100 ; - RECT 90.030 0.700 90.310 163.100 ; - RECT 92.270 0.700 92.550 163.100 ; - RECT 94.510 0.700 94.790 163.100 ; - RECT 96.750 0.700 97.030 163.100 ; - RECT 98.990 0.700 99.270 163.100 ; - RECT 101.230 0.700 101.510 163.100 ; - RECT 103.470 0.700 103.750 163.100 ; - RECT 105.710 0.700 105.990 163.100 ; - RECT 107.950 0.700 108.230 163.100 ; - RECT 110.190 0.700 110.470 163.100 ; - RECT 112.430 0.700 112.710 163.100 ; - RECT 114.670 0.700 114.950 163.100 ; - RECT 116.910 0.700 117.190 163.100 ; - RECT 119.150 0.700 119.430 163.100 ; - RECT 121.390 0.700 121.670 163.100 ; - RECT 123.630 0.700 123.910 163.100 ; - RECT 125.870 0.700 126.150 163.100 ; - RECT 128.110 0.700 128.390 163.100 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 163.100 ; - RECT 2.670 0.700 2.950 163.100 ; - RECT 4.910 0.700 5.190 163.100 ; - RECT 7.150 0.700 7.430 163.100 ; - RECT 9.390 0.700 9.670 163.100 ; - RECT 11.630 0.700 11.910 163.100 ; - RECT 13.870 0.700 14.150 163.100 ; - RECT 16.110 0.700 16.390 163.100 ; - RECT 18.350 0.700 18.630 163.100 ; - RECT 20.590 0.700 20.870 163.100 ; - RECT 22.830 0.700 23.110 163.100 ; - RECT 25.070 0.700 25.350 163.100 ; - RECT 27.310 0.700 27.590 163.100 ; - RECT 29.550 0.700 29.830 163.100 ; - RECT 31.790 0.700 32.070 163.100 ; - RECT 34.030 0.700 34.310 163.100 ; - RECT 36.270 0.700 36.550 163.100 ; - RECT 38.510 0.700 38.790 163.100 ; - RECT 40.750 0.700 41.030 163.100 ; - RECT 42.990 0.700 43.270 163.100 ; - RECT 45.230 0.700 45.510 163.100 ; - RECT 47.470 0.700 47.750 163.100 ; - RECT 49.710 0.700 49.990 163.100 ; - RECT 51.950 0.700 52.230 163.100 ; - RECT 54.190 0.700 54.470 163.100 ; - RECT 56.430 0.700 56.710 163.100 ; - RECT 58.670 0.700 58.950 163.100 ; - RECT 60.910 0.700 61.190 163.100 ; - RECT 63.150 0.700 63.430 163.100 ; - RECT 65.390 0.700 65.670 163.100 ; - RECT 67.630 0.700 67.910 163.100 ; - RECT 69.870 0.700 70.150 163.100 ; - RECT 72.110 0.700 72.390 163.100 ; - RECT 74.350 0.700 74.630 163.100 ; - RECT 76.590 0.700 76.870 163.100 ; - RECT 78.830 0.700 79.110 163.100 ; - RECT 81.070 0.700 81.350 163.100 ; - RECT 83.310 0.700 83.590 163.100 ; - RECT 85.550 0.700 85.830 163.100 ; - RECT 87.790 0.700 88.070 163.100 ; - RECT 90.030 0.700 90.310 163.100 ; - RECT 92.270 0.700 92.550 163.100 ; - RECT 94.510 0.700 94.790 163.100 ; - RECT 96.750 0.700 97.030 163.100 ; - RECT 98.990 0.700 99.270 163.100 ; - RECT 101.230 0.700 101.510 163.100 ; - RECT 103.470 0.700 103.750 163.100 ; - RECT 105.710 0.700 105.990 163.100 ; - RECT 107.950 0.700 108.230 163.100 ; - RECT 110.190 0.700 110.470 163.100 ; - RECT 112.430 0.700 112.710 163.100 ; - RECT 114.670 0.700 114.950 163.100 ; - RECT 116.910 0.700 117.190 163.100 ; - RECT 119.150 0.700 119.430 163.100 ; - RECT 121.390 0.700 121.670 163.100 ; - RECT 123.630 0.700 123.910 163.100 ; - RECT 125.870 0.700 126.150 163.100 ; - RECT 128.110 0.700 128.390 163.100 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 130.910 163.800 ; - LAYER metal2 ; - RECT 0 0 130.910 163.800 ; - LAYER metal3 ; - RECT 0 0 130.910 163.800 ; - LAYER metal4 ; - RECT 0 0 130.910 163.800 ; - LAYER OVERLAP ; - RECT 0 0 130.910 163.800 ; - END -END fakeram_1x256_1r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef deleted file mode 100644 index 51041ca..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_20x64_1r1w.lef +++ /dev/null @@ -1,617 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_20x64_1r1w - FOREIGN fakeram_20x64_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 76.950 BY 63.000 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 6.265 0.140 6.335 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 11.725 0.140 11.795 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 17.185 0.140 17.255 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 22.645 0.140 22.715 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 0.805 76.950 0.875 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 6.265 76.950 6.335 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 11.725 76.950 11.795 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 17.185 76.950 17.255 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 22.645 76.950 22.715 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 4.715 0.000 4.785 0.140 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 8.325 0.000 8.395 0.140 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 11.935 0.000 12.005 0.140 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 15.545 0.000 15.615 0.140 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 19.155 0.000 19.225 0.140 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.765 0.000 22.835 0.140 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 26.375 0.000 26.445 0.140 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 29.985 0.000 30.055 0.140 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 33.595 0.000 33.665 0.140 ; - END - END w0_wd_in[19] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.205 0.000 37.275 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 40.815 0.000 40.885 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 44.425 0.000 44.495 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.035 0.000 48.105 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 51.645 0.000 51.715 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.255 0.000 55.325 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 58.865 0.000 58.935 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 62.475 0.000 62.545 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 66.085 0.000 66.155 0.140 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 69.695 0.000 69.765 0.140 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 62.860 1.175 63.000 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 6.045 62.860 6.115 63.000 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.985 62.860 11.055 63.000 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 15.925 62.860 15.995 63.000 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 20.865 62.860 20.935 63.000 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.805 62.860 25.875 63.000 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 30.745 62.860 30.815 63.000 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 35.685 62.860 35.755 63.000 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 40.625 62.860 40.695 63.000 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 45.565 62.860 45.635 63.000 ; - END - END r0_rd_out[19] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 28.105 0.140 28.175 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 33.565 0.140 33.635 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 39.025 0.140 39.095 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 28.105 76.950 28.175 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 33.565 76.950 33.635 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 39.025 76.950 39.095 ; - END - END w0_addr_in[5] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 44.485 0.140 44.555 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 49.945 0.140 50.015 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 55.405 0.140 55.475 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 44.485 76.950 44.555 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 49.945 76.950 50.015 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 76.810 55.405 76.950 55.475 ; - END - END r0_addr_in[5] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 50.505 62.860 50.575 63.000 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.445 62.860 55.515 63.000 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 60.385 62.860 60.455 63.000 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 65.325 62.860 65.395 63.000 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 70.265 62.860 70.335 63.000 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 62.300 ; - RECT 2.670 0.700 2.950 62.300 ; - RECT 4.910 0.700 5.190 62.300 ; - RECT 7.150 0.700 7.430 62.300 ; - RECT 9.390 0.700 9.670 62.300 ; - RECT 11.630 0.700 11.910 62.300 ; - RECT 13.870 0.700 14.150 62.300 ; - RECT 16.110 0.700 16.390 62.300 ; - RECT 18.350 0.700 18.630 62.300 ; - RECT 20.590 0.700 20.870 62.300 ; - RECT 22.830 0.700 23.110 62.300 ; - RECT 25.070 0.700 25.350 62.300 ; - RECT 27.310 0.700 27.590 62.300 ; - RECT 29.550 0.700 29.830 62.300 ; - RECT 31.790 0.700 32.070 62.300 ; - RECT 34.030 0.700 34.310 62.300 ; - RECT 36.270 0.700 36.550 62.300 ; - RECT 38.510 0.700 38.790 62.300 ; - RECT 40.750 0.700 41.030 62.300 ; - RECT 42.990 0.700 43.270 62.300 ; - RECT 45.230 0.700 45.510 62.300 ; - RECT 47.470 0.700 47.750 62.300 ; - RECT 49.710 0.700 49.990 62.300 ; - RECT 51.950 0.700 52.230 62.300 ; - RECT 54.190 0.700 54.470 62.300 ; - RECT 56.430 0.700 56.710 62.300 ; - RECT 58.670 0.700 58.950 62.300 ; - RECT 60.910 0.700 61.190 62.300 ; - RECT 63.150 0.700 63.430 62.300 ; - RECT 65.390 0.700 65.670 62.300 ; - RECT 67.630 0.700 67.910 62.300 ; - RECT 69.870 0.700 70.150 62.300 ; - RECT 72.110 0.700 72.390 62.300 ; - RECT 74.350 0.700 74.630 62.300 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 62.300 ; - RECT 2.670 0.700 2.950 62.300 ; - RECT 4.910 0.700 5.190 62.300 ; - RECT 7.150 0.700 7.430 62.300 ; - RECT 9.390 0.700 9.670 62.300 ; - RECT 11.630 0.700 11.910 62.300 ; - RECT 13.870 0.700 14.150 62.300 ; - RECT 16.110 0.700 16.390 62.300 ; - RECT 18.350 0.700 18.630 62.300 ; - RECT 20.590 0.700 20.870 62.300 ; - RECT 22.830 0.700 23.110 62.300 ; - RECT 25.070 0.700 25.350 62.300 ; - RECT 27.310 0.700 27.590 62.300 ; - RECT 29.550 0.700 29.830 62.300 ; - RECT 31.790 0.700 32.070 62.300 ; - RECT 34.030 0.700 34.310 62.300 ; - RECT 36.270 0.700 36.550 62.300 ; - RECT 38.510 0.700 38.790 62.300 ; - RECT 40.750 0.700 41.030 62.300 ; - RECT 42.990 0.700 43.270 62.300 ; - RECT 45.230 0.700 45.510 62.300 ; - RECT 47.470 0.700 47.750 62.300 ; - RECT 49.710 0.700 49.990 62.300 ; - RECT 51.950 0.700 52.230 62.300 ; - RECT 54.190 0.700 54.470 62.300 ; - RECT 56.430 0.700 56.710 62.300 ; - RECT 58.670 0.700 58.950 62.300 ; - RECT 60.910 0.700 61.190 62.300 ; - RECT 63.150 0.700 63.430 62.300 ; - RECT 65.390 0.700 65.670 62.300 ; - RECT 67.630 0.700 67.910 62.300 ; - RECT 69.870 0.700 70.150 62.300 ; - RECT 72.110 0.700 72.390 62.300 ; - RECT 74.350 0.700 74.630 62.300 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 76.950 63.000 ; - LAYER metal2 ; - RECT 0 0 76.950 63.000 ; - LAYER metal3 ; - RECT 0 0 76.950 63.000 ; - LAYER metal4 ; - RECT 0 0 76.950 63.000 ; - LAYER OVERLAP ; - RECT 0 0 76.950 63.000 ; - END -END fakeram_20x64_1r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef deleted file mode 100644 index dd7f2db..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_20x64_2r1w.lef +++ /dev/null @@ -1,889 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_20x64_2r1w - FOREIGN fakeram_20x64_2r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 98.990 BY 134.400 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 10.185 0.140 10.255 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 19.565 0.140 19.635 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 28.945 0.140 29.015 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 38.325 0.140 38.395 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 0.805 98.990 0.875 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 10.185 98.990 10.255 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 19.565 98.990 19.635 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 28.945 98.990 29.015 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 38.325 98.990 38.395 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 4.145 0.000 4.215 0.140 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 7.185 0.000 7.255 0.140 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.225 0.000 10.295 0.140 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 13.265 0.000 13.335 0.140 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 16.305 0.000 16.375 0.140 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 19.345 0.000 19.415 0.140 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.385 0.000 22.455 0.140 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.425 0.000 25.495 0.140 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 28.465 0.000 28.535 0.140 ; - END - END w0_wd_in[19] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.505 0.000 31.575 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 34.545 0.000 34.615 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.585 0.000 37.655 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 40.625 0.000 40.695 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.665 0.000 43.735 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 46.705 0.000 46.775 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 49.745 0.000 49.815 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 52.785 0.000 52.855 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.825 0.000 55.895 0.140 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 58.865 0.000 58.935 0.140 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 134.260 1.175 134.400 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 4.525 134.260 4.595 134.400 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 7.945 134.260 8.015 134.400 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 11.365 134.260 11.435 134.400 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 14.785 134.260 14.855 134.400 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 18.205 134.260 18.275 134.400 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 21.625 134.260 21.695 134.400 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.045 134.260 25.115 134.400 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 28.465 134.260 28.535 134.400 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.885 134.260 31.955 134.400 ; - END - END r0_rd_out[19] - PIN r1_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 61.905 0.000 61.975 0.140 ; - END - END r1_rd_out[0] - PIN r1_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 64.945 0.000 65.015 0.140 ; - END - END r1_rd_out[1] - PIN r1_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.985 0.000 68.055 0.140 ; - END - END r1_rd_out[2] - PIN r1_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 71.025 0.000 71.095 0.140 ; - END - END r1_rd_out[3] - PIN r1_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 74.065 0.000 74.135 0.140 ; - END - END r1_rd_out[4] - PIN r1_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 77.105 0.000 77.175 0.140 ; - END - END r1_rd_out[5] - PIN r1_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.145 0.000 80.215 0.140 ; - END - END r1_rd_out[6] - PIN r1_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 83.185 0.000 83.255 0.140 ; - END - END r1_rd_out[7] - PIN r1_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.225 0.000 86.295 0.140 ; - END - END r1_rd_out[8] - PIN r1_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 89.265 0.000 89.335 0.140 ; - END - END r1_rd_out[9] - PIN r1_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 35.305 134.260 35.375 134.400 ; - END - END r1_rd_out[10] - PIN r1_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 38.725 134.260 38.795 134.400 ; - END - END r1_rd_out[11] - PIN r1_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 42.145 134.260 42.215 134.400 ; - END - END r1_rd_out[12] - PIN r1_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 45.565 134.260 45.635 134.400 ; - END - END r1_rd_out[13] - PIN r1_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.985 134.260 49.055 134.400 ; - END - END r1_rd_out[14] - PIN r1_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 52.405 134.260 52.475 134.400 ; - END - END r1_rd_out[15] - PIN r1_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.825 134.260 55.895 134.400 ; - END - END r1_rd_out[16] - PIN r1_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 59.245 134.260 59.315 134.400 ; - END - END r1_rd_out[17] - PIN r1_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 62.665 134.260 62.735 134.400 ; - END - END r1_rd_out[18] - PIN r1_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 66.085 134.260 66.155 134.400 ; - END - END r1_rd_out[19] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 47.705 0.140 47.775 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 57.085 0.140 57.155 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 66.465 0.140 66.535 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 47.705 98.990 47.775 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 57.085 98.990 57.155 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 66.465 98.990 66.535 ; - END - END w0_addr_in[5] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 75.845 0.140 75.915 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 85.225 0.140 85.295 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 94.605 0.140 94.675 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 75.845 98.990 75.915 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 85.225 98.990 85.295 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 94.605 98.990 94.675 ; - END - END r0_addr_in[5] - PIN r1_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 103.985 0.140 104.055 ; - END - END r1_addr_in[0] - PIN r1_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 113.365 0.140 113.435 ; - END - END r1_addr_in[1] - PIN r1_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 122.745 0.140 122.815 ; - END - END r1_addr_in[2] - PIN r1_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 103.985 98.990 104.055 ; - END - END r1_addr_in[3] - PIN r1_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 113.365 98.990 113.435 ; - END - END r1_addr_in[4] - PIN r1_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 98.850 122.745 98.990 122.815 ; - END - END r1_addr_in[5] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 69.505 134.260 69.575 134.400 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 72.925 134.260 72.995 134.400 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 76.345 134.260 76.415 134.400 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 79.765 134.260 79.835 134.400 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 83.185 134.260 83.255 134.400 ; - END - END r0_clk - PIN r1_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.605 134.260 86.675 134.400 ; - END - END r1_ce_in - PIN r1_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 90.025 134.260 90.095 134.400 ; - END - END r1_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 133.700 ; - RECT 2.670 0.700 2.950 133.700 ; - RECT 4.910 0.700 5.190 133.700 ; - RECT 7.150 0.700 7.430 133.700 ; - RECT 9.390 0.700 9.670 133.700 ; - RECT 11.630 0.700 11.910 133.700 ; - RECT 13.870 0.700 14.150 133.700 ; - RECT 16.110 0.700 16.390 133.700 ; - RECT 18.350 0.700 18.630 133.700 ; - RECT 20.590 0.700 20.870 133.700 ; - RECT 22.830 0.700 23.110 133.700 ; - RECT 25.070 0.700 25.350 133.700 ; - RECT 27.310 0.700 27.590 133.700 ; - RECT 29.550 0.700 29.830 133.700 ; - RECT 31.790 0.700 32.070 133.700 ; - RECT 34.030 0.700 34.310 133.700 ; - RECT 36.270 0.700 36.550 133.700 ; - RECT 38.510 0.700 38.790 133.700 ; - RECT 40.750 0.700 41.030 133.700 ; - RECT 42.990 0.700 43.270 133.700 ; - RECT 45.230 0.700 45.510 133.700 ; - RECT 47.470 0.700 47.750 133.700 ; - RECT 49.710 0.700 49.990 133.700 ; - RECT 51.950 0.700 52.230 133.700 ; - RECT 54.190 0.700 54.470 133.700 ; - RECT 56.430 0.700 56.710 133.700 ; - RECT 58.670 0.700 58.950 133.700 ; - RECT 60.910 0.700 61.190 133.700 ; - RECT 63.150 0.700 63.430 133.700 ; - RECT 65.390 0.700 65.670 133.700 ; - RECT 67.630 0.700 67.910 133.700 ; - RECT 69.870 0.700 70.150 133.700 ; - RECT 72.110 0.700 72.390 133.700 ; - RECT 74.350 0.700 74.630 133.700 ; - RECT 76.590 0.700 76.870 133.700 ; - RECT 78.830 0.700 79.110 133.700 ; - RECT 81.070 0.700 81.350 133.700 ; - RECT 83.310 0.700 83.590 133.700 ; - RECT 85.550 0.700 85.830 133.700 ; - RECT 87.790 0.700 88.070 133.700 ; - RECT 90.030 0.700 90.310 133.700 ; - RECT 92.270 0.700 92.550 133.700 ; - RECT 94.510 0.700 94.790 133.700 ; - RECT 96.750 0.700 97.030 133.700 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 133.700 ; - RECT 2.670 0.700 2.950 133.700 ; - RECT 4.910 0.700 5.190 133.700 ; - RECT 7.150 0.700 7.430 133.700 ; - RECT 9.390 0.700 9.670 133.700 ; - RECT 11.630 0.700 11.910 133.700 ; - RECT 13.870 0.700 14.150 133.700 ; - RECT 16.110 0.700 16.390 133.700 ; - RECT 18.350 0.700 18.630 133.700 ; - RECT 20.590 0.700 20.870 133.700 ; - RECT 22.830 0.700 23.110 133.700 ; - RECT 25.070 0.700 25.350 133.700 ; - RECT 27.310 0.700 27.590 133.700 ; - RECT 29.550 0.700 29.830 133.700 ; - RECT 31.790 0.700 32.070 133.700 ; - RECT 34.030 0.700 34.310 133.700 ; - RECT 36.270 0.700 36.550 133.700 ; - RECT 38.510 0.700 38.790 133.700 ; - RECT 40.750 0.700 41.030 133.700 ; - RECT 42.990 0.700 43.270 133.700 ; - RECT 45.230 0.700 45.510 133.700 ; - RECT 47.470 0.700 47.750 133.700 ; - RECT 49.710 0.700 49.990 133.700 ; - RECT 51.950 0.700 52.230 133.700 ; - RECT 54.190 0.700 54.470 133.700 ; - RECT 56.430 0.700 56.710 133.700 ; - RECT 58.670 0.700 58.950 133.700 ; - RECT 60.910 0.700 61.190 133.700 ; - RECT 63.150 0.700 63.430 133.700 ; - RECT 65.390 0.700 65.670 133.700 ; - RECT 67.630 0.700 67.910 133.700 ; - RECT 69.870 0.700 70.150 133.700 ; - RECT 72.110 0.700 72.390 133.700 ; - RECT 74.350 0.700 74.630 133.700 ; - RECT 76.590 0.700 76.870 133.700 ; - RECT 78.830 0.700 79.110 133.700 ; - RECT 81.070 0.700 81.350 133.700 ; - RECT 83.310 0.700 83.590 133.700 ; - RECT 85.550 0.700 85.830 133.700 ; - RECT 87.790 0.700 88.070 133.700 ; - RECT 90.030 0.700 90.310 133.700 ; - RECT 92.270 0.700 92.550 133.700 ; - RECT 94.510 0.700 94.790 133.700 ; - RECT 96.750 0.700 97.030 133.700 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 98.990 134.400 ; - LAYER metal2 ; - RECT 0 0 98.990 134.400 ; - LAYER metal3 ; - RECT 0 0 98.990 134.400 ; - LAYER metal4 ; - RECT 0 0 98.990 134.400 ; - LAYER OVERLAP ; - RECT 0 0 98.990 134.400 ; - END -END fakeram_20x64_2r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef deleted file mode 100644 index a8a55c8..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_32x128_2r1w.lef +++ /dev/null @@ -1,1238 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_32x128_2r1w - FOREIGN fakeram_32x128_2r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 96.710 BY 250.600 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 13.825 0.140 13.895 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 26.845 0.140 26.915 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 39.865 0.140 39.935 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 52.885 0.140 52.955 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 65.905 0.140 65.975 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 78.925 0.140 78.995 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 91.945 0.140 92.015 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 0.805 96.710 0.875 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 13.825 96.710 13.895 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 26.845 96.710 26.915 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 39.865 96.710 39.935 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 52.885 96.710 52.955 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 65.905 96.710 65.975 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 78.925 96.710 78.995 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 91.945 96.710 92.015 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 3.005 0.000 3.075 0.140 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 4.905 0.000 4.975 0.140 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 6.805 0.000 6.875 0.140 ; - END - END w0_wd_in[19] - PIN w0_wd_in[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 8.705 0.000 8.775 0.140 ; - END - END w0_wd_in[20] - PIN w0_wd_in[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.605 0.000 10.675 0.140 ; - END - END w0_wd_in[21] - PIN w0_wd_in[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 12.505 0.000 12.575 0.140 ; - END - END w0_wd_in[22] - PIN w0_wd_in[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 14.405 0.000 14.475 0.140 ; - END - END w0_wd_in[23] - PIN w0_wd_in[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 16.305 0.000 16.375 0.140 ; - END - END w0_wd_in[24] - PIN w0_wd_in[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 18.205 0.000 18.275 0.140 ; - END - END w0_wd_in[25] - PIN w0_wd_in[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 20.105 0.000 20.175 0.140 ; - END - END w0_wd_in[26] - PIN w0_wd_in[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.005 0.000 22.075 0.140 ; - END - END w0_wd_in[27] - PIN w0_wd_in[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 23.905 0.000 23.975 0.140 ; - END - END w0_wd_in[28] - PIN w0_wd_in[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.805 0.000 25.875 0.140 ; - END - END w0_wd_in[29] - PIN w0_wd_in[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 27.705 0.000 27.775 0.140 ; - END - END w0_wd_in[30] - PIN w0_wd_in[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 29.605 0.000 29.675 0.140 ; - END - END w0_wd_in[31] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.505 0.000 31.575 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 33.405 0.000 33.475 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 35.305 0.000 35.375 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.205 0.000 37.275 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 39.105 0.000 39.175 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 41.005 0.000 41.075 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 42.905 0.000 42.975 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 44.805 0.000 44.875 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 46.705 0.000 46.775 0.140 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.605 0.000 48.675 0.140 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 50.505 0.000 50.575 0.140 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 52.405 0.000 52.475 0.140 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 54.305 0.000 54.375 0.140 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 56.205 0.000 56.275 0.140 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 58.105 0.000 58.175 0.140 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 60.005 0.000 60.075 0.140 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 250.460 1.175 250.600 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 3.385 250.460 3.455 250.600 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 5.665 250.460 5.735 250.600 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 7.945 250.460 8.015 250.600 ; - END - END r0_rd_out[19] - PIN r0_rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.225 250.460 10.295 250.600 ; - END - END r0_rd_out[20] - PIN r0_rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 12.505 250.460 12.575 250.600 ; - END - END r0_rd_out[21] - PIN r0_rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 14.785 250.460 14.855 250.600 ; - END - END r0_rd_out[22] - PIN r0_rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 17.065 250.460 17.135 250.600 ; - END - END r0_rd_out[23] - PIN r0_rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 19.345 250.460 19.415 250.600 ; - END - END r0_rd_out[24] - PIN r0_rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 21.625 250.460 21.695 250.600 ; - END - END r0_rd_out[25] - PIN r0_rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 23.905 250.460 23.975 250.600 ; - END - END r0_rd_out[26] - PIN r0_rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 26.185 250.460 26.255 250.600 ; - END - END r0_rd_out[27] - PIN r0_rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 28.465 250.460 28.535 250.600 ; - END - END r0_rd_out[28] - PIN r0_rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 30.745 250.460 30.815 250.600 ; - END - END r0_rd_out[29] - PIN r0_rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 33.025 250.460 33.095 250.600 ; - END - END r0_rd_out[30] - PIN r0_rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 35.305 250.460 35.375 250.600 ; - END - END r0_rd_out[31] - PIN r1_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 61.905 0.000 61.975 0.140 ; - END - END r1_rd_out[0] - PIN r1_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 63.805 0.000 63.875 0.140 ; - END - END r1_rd_out[1] - PIN r1_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 65.705 0.000 65.775 0.140 ; - END - END r1_rd_out[2] - PIN r1_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.605 0.000 67.675 0.140 ; - END - END r1_rd_out[3] - PIN r1_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 69.505 0.000 69.575 0.140 ; - END - END r1_rd_out[4] - PIN r1_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 71.405 0.000 71.475 0.140 ; - END - END r1_rd_out[5] - PIN r1_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 73.305 0.000 73.375 0.140 ; - END - END r1_rd_out[6] - PIN r1_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 75.205 0.000 75.275 0.140 ; - END - END r1_rd_out[7] - PIN r1_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 77.105 0.000 77.175 0.140 ; - END - END r1_rd_out[8] - PIN r1_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 79.005 0.000 79.075 0.140 ; - END - END r1_rd_out[9] - PIN r1_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.905 0.000 80.975 0.140 ; - END - END r1_rd_out[10] - PIN r1_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 82.805 0.000 82.875 0.140 ; - END - END r1_rd_out[11] - PIN r1_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 84.705 0.000 84.775 0.140 ; - END - END r1_rd_out[12] - PIN r1_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.605 0.000 86.675 0.140 ; - END - END r1_rd_out[13] - PIN r1_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 88.505 0.000 88.575 0.140 ; - END - END r1_rd_out[14] - PIN r1_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 90.405 0.000 90.475 0.140 ; - END - END r1_rd_out[15] - PIN r1_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.585 250.460 37.655 250.600 ; - END - END r1_rd_out[16] - PIN r1_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 39.865 250.460 39.935 250.600 ; - END - END r1_rd_out[17] - PIN r1_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 42.145 250.460 42.215 250.600 ; - END - END r1_rd_out[18] - PIN r1_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 44.425 250.460 44.495 250.600 ; - END - END r1_rd_out[19] - PIN r1_rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 46.705 250.460 46.775 250.600 ; - END - END r1_rd_out[20] - PIN r1_rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.985 250.460 49.055 250.600 ; - END - END r1_rd_out[21] - PIN r1_rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 51.265 250.460 51.335 250.600 ; - END - END r1_rd_out[22] - PIN r1_rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 53.545 250.460 53.615 250.600 ; - END - END r1_rd_out[23] - PIN r1_rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.825 250.460 55.895 250.600 ; - END - END r1_rd_out[24] - PIN r1_rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 58.105 250.460 58.175 250.600 ; - END - END r1_rd_out[25] - PIN r1_rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 60.385 250.460 60.455 250.600 ; - END - END r1_rd_out[26] - PIN r1_rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 62.665 250.460 62.735 250.600 ; - END - END r1_rd_out[27] - PIN r1_rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 64.945 250.460 65.015 250.600 ; - END - END r1_rd_out[28] - PIN r1_rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.225 250.460 67.295 250.600 ; - END - END r1_rd_out[29] - PIN r1_rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 69.505 250.460 69.575 250.600 ; - END - END r1_rd_out[30] - PIN r1_rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 71.785 250.460 71.855 250.600 ; - END - END r1_rd_out[31] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 104.965 0.140 105.035 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 117.985 0.140 118.055 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 131.005 0.140 131.075 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 144.025 0.140 144.095 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 104.965 96.710 105.035 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 117.985 96.710 118.055 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 131.005 96.710 131.075 ; - END - END w0_addr_in[6] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 157.045 0.140 157.115 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 170.065 0.140 170.135 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 183.085 0.140 183.155 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 196.105 0.140 196.175 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 144.025 96.710 144.095 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 157.045 96.710 157.115 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 170.065 96.710 170.135 ; - END - END r0_addr_in[6] - PIN r1_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 209.125 0.140 209.195 ; - END - END r1_addr_in[0] - PIN r1_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 222.145 0.140 222.215 ; - END - END r1_addr_in[1] - PIN r1_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 235.165 0.140 235.235 ; - END - END r1_addr_in[2] - PIN r1_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 248.185 0.140 248.255 ; - END - END r1_addr_in[3] - PIN r1_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 183.085 96.710 183.155 ; - END - END r1_addr_in[4] - PIN r1_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 196.105 96.710 196.175 ; - END - END r1_addr_in[5] - PIN r1_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 96.570 209.125 96.710 209.195 ; - END - END r1_addr_in[6] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 74.065 250.460 74.135 250.600 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 76.345 250.460 76.415 250.600 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 78.625 250.460 78.695 250.600 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.905 250.460 80.975 250.600 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 83.185 250.460 83.255 250.600 ; - END - END r0_clk - PIN r1_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 85.465 250.460 85.535 250.600 ; - END - END r1_ce_in - PIN r1_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 87.745 250.460 87.815 250.600 ; - END - END r1_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 249.900 ; - RECT 2.670 0.700 2.950 249.900 ; - RECT 4.910 0.700 5.190 249.900 ; - RECT 7.150 0.700 7.430 249.900 ; - RECT 9.390 0.700 9.670 249.900 ; - RECT 11.630 0.700 11.910 249.900 ; - RECT 13.870 0.700 14.150 249.900 ; - RECT 16.110 0.700 16.390 249.900 ; - RECT 18.350 0.700 18.630 249.900 ; - RECT 20.590 0.700 20.870 249.900 ; - RECT 22.830 0.700 23.110 249.900 ; - RECT 25.070 0.700 25.350 249.900 ; - RECT 27.310 0.700 27.590 249.900 ; - RECT 29.550 0.700 29.830 249.900 ; - RECT 31.790 0.700 32.070 249.900 ; - RECT 34.030 0.700 34.310 249.900 ; - RECT 36.270 0.700 36.550 249.900 ; - RECT 38.510 0.700 38.790 249.900 ; - RECT 40.750 0.700 41.030 249.900 ; - RECT 42.990 0.700 43.270 249.900 ; - RECT 45.230 0.700 45.510 249.900 ; - RECT 47.470 0.700 47.750 249.900 ; - RECT 49.710 0.700 49.990 249.900 ; - RECT 51.950 0.700 52.230 249.900 ; - RECT 54.190 0.700 54.470 249.900 ; - RECT 56.430 0.700 56.710 249.900 ; - RECT 58.670 0.700 58.950 249.900 ; - RECT 60.910 0.700 61.190 249.900 ; - RECT 63.150 0.700 63.430 249.900 ; - RECT 65.390 0.700 65.670 249.900 ; - RECT 67.630 0.700 67.910 249.900 ; - RECT 69.870 0.700 70.150 249.900 ; - RECT 72.110 0.700 72.390 249.900 ; - RECT 74.350 0.700 74.630 249.900 ; - RECT 76.590 0.700 76.870 249.900 ; - RECT 78.830 0.700 79.110 249.900 ; - RECT 81.070 0.700 81.350 249.900 ; - RECT 83.310 0.700 83.590 249.900 ; - RECT 85.550 0.700 85.830 249.900 ; - RECT 87.790 0.700 88.070 249.900 ; - RECT 90.030 0.700 90.310 249.900 ; - RECT 92.270 0.700 92.550 249.900 ; - RECT 94.510 0.700 94.790 249.900 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 249.900 ; - RECT 2.670 0.700 2.950 249.900 ; - RECT 4.910 0.700 5.190 249.900 ; - RECT 7.150 0.700 7.430 249.900 ; - RECT 9.390 0.700 9.670 249.900 ; - RECT 11.630 0.700 11.910 249.900 ; - RECT 13.870 0.700 14.150 249.900 ; - RECT 16.110 0.700 16.390 249.900 ; - RECT 18.350 0.700 18.630 249.900 ; - RECT 20.590 0.700 20.870 249.900 ; - RECT 22.830 0.700 23.110 249.900 ; - RECT 25.070 0.700 25.350 249.900 ; - RECT 27.310 0.700 27.590 249.900 ; - RECT 29.550 0.700 29.830 249.900 ; - RECT 31.790 0.700 32.070 249.900 ; - RECT 34.030 0.700 34.310 249.900 ; - RECT 36.270 0.700 36.550 249.900 ; - RECT 38.510 0.700 38.790 249.900 ; - RECT 40.750 0.700 41.030 249.900 ; - RECT 42.990 0.700 43.270 249.900 ; - RECT 45.230 0.700 45.510 249.900 ; - RECT 47.470 0.700 47.750 249.900 ; - RECT 49.710 0.700 49.990 249.900 ; - RECT 51.950 0.700 52.230 249.900 ; - RECT 54.190 0.700 54.470 249.900 ; - RECT 56.430 0.700 56.710 249.900 ; - RECT 58.670 0.700 58.950 249.900 ; - RECT 60.910 0.700 61.190 249.900 ; - RECT 63.150 0.700 63.430 249.900 ; - RECT 65.390 0.700 65.670 249.900 ; - RECT 67.630 0.700 67.910 249.900 ; - RECT 69.870 0.700 70.150 249.900 ; - RECT 72.110 0.700 72.390 249.900 ; - RECT 74.350 0.700 74.630 249.900 ; - RECT 76.590 0.700 76.870 249.900 ; - RECT 78.830 0.700 79.110 249.900 ; - RECT 81.070 0.700 81.350 249.900 ; - RECT 83.310 0.700 83.590 249.900 ; - RECT 85.550 0.700 85.830 249.900 ; - RECT 87.790 0.700 88.070 249.900 ; - RECT 90.030 0.700 90.310 249.900 ; - RECT 92.270 0.700 92.550 249.900 ; - RECT 94.510 0.700 94.790 249.900 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 96.710 250.600 ; - LAYER metal2 ; - RECT 0 0 96.710 250.600 ; - LAYER metal3 ; - RECT 0 0 96.710 250.600 ; - LAYER metal4 ; - RECT 0 0 96.710 250.600 ; - LAYER OVERLAP ; - RECT 0 0 96.710 250.600 ; - END -END fakeram_32x128_2r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef deleted file mode 100644 index 36751ff..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_512x2048_1r1w.lef +++ /dev/null @@ -1,10931 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_512x2048_1r1w - FOREIGN fakeram_512x2048_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 1609.300 BY 1512.000 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 11.585 0.140 11.655 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 22.365 0.140 22.435 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 33.145 0.140 33.215 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 43.925 0.140 43.995 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 54.705 0.140 54.775 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 65.485 0.140 65.555 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 76.265 0.140 76.335 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 87.045 0.140 87.115 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 97.825 0.140 97.895 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 108.605 0.140 108.675 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 119.385 0.140 119.455 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 130.165 0.140 130.235 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 140.945 0.140 141.015 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 151.725 0.140 151.795 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 162.505 0.140 162.575 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 173.285 0.140 173.355 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 184.065 0.140 184.135 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 194.845 0.140 194.915 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 205.625 0.140 205.695 ; - END - END w0_wd_in[19] - PIN w0_wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 216.405 0.140 216.475 ; - END - END w0_wd_in[20] - PIN w0_wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 227.185 0.140 227.255 ; - END - END w0_wd_in[21] - PIN w0_wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 237.965 0.140 238.035 ; - END - END w0_wd_in[22] - PIN w0_wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 248.745 0.140 248.815 ; - END - END w0_wd_in[23] - PIN w0_wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 259.525 0.140 259.595 ; - END - END w0_wd_in[24] - PIN w0_wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 270.305 0.140 270.375 ; - END - END w0_wd_in[25] - PIN w0_wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 281.085 0.140 281.155 ; - END - END w0_wd_in[26] - PIN w0_wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 291.865 0.140 291.935 ; - END - END w0_wd_in[27] - PIN w0_wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 302.645 0.140 302.715 ; - END - END w0_wd_in[28] - PIN w0_wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 313.425 0.140 313.495 ; - END - END w0_wd_in[29] - PIN w0_wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 324.205 0.140 324.275 ; - END - END w0_wd_in[30] - PIN w0_wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 334.985 0.140 335.055 ; - END - END w0_wd_in[31] - PIN w0_wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 345.765 0.140 345.835 ; - END - END w0_wd_in[32] - PIN w0_wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 356.545 0.140 356.615 ; - END - END w0_wd_in[33] - PIN w0_wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 367.325 0.140 367.395 ; - END - END w0_wd_in[34] - PIN w0_wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 378.105 0.140 378.175 ; - END - END w0_wd_in[35] - PIN w0_wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 388.885 0.140 388.955 ; - END - END w0_wd_in[36] - PIN w0_wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 399.665 0.140 399.735 ; - END - END w0_wd_in[37] - PIN w0_wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 410.445 0.140 410.515 ; - END - END w0_wd_in[38] - PIN w0_wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 421.225 0.140 421.295 ; - END - END w0_wd_in[39] - PIN w0_wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 432.005 0.140 432.075 ; - END - END w0_wd_in[40] - PIN w0_wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 442.785 0.140 442.855 ; - END - END w0_wd_in[41] - PIN w0_wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 453.565 0.140 453.635 ; - END - END w0_wd_in[42] - PIN w0_wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 464.345 0.140 464.415 ; - END - END w0_wd_in[43] - PIN w0_wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 475.125 0.140 475.195 ; - END - END w0_wd_in[44] - PIN w0_wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 485.905 0.140 485.975 ; - END - END w0_wd_in[45] - PIN w0_wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 496.685 0.140 496.755 ; - END - END w0_wd_in[46] - PIN w0_wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 507.465 0.140 507.535 ; - END - END w0_wd_in[47] - PIN w0_wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 518.245 0.140 518.315 ; - END - END w0_wd_in[48] - PIN w0_wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 529.025 0.140 529.095 ; - END - END w0_wd_in[49] - PIN w0_wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 539.805 0.140 539.875 ; - END - END w0_wd_in[50] - PIN w0_wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 550.585 0.140 550.655 ; - END - END w0_wd_in[51] - PIN w0_wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 561.365 0.140 561.435 ; - END - END w0_wd_in[52] - PIN w0_wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 572.145 0.140 572.215 ; - END - END w0_wd_in[53] - PIN w0_wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 582.925 0.140 582.995 ; - END - END w0_wd_in[54] - PIN w0_wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 593.705 0.140 593.775 ; - END - END w0_wd_in[55] - PIN w0_wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 604.485 0.140 604.555 ; - END - END w0_wd_in[56] - PIN w0_wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 615.265 0.140 615.335 ; - END - END w0_wd_in[57] - PIN w0_wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 626.045 0.140 626.115 ; - END - END w0_wd_in[58] - PIN w0_wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 636.825 0.140 636.895 ; - END - END w0_wd_in[59] - PIN w0_wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 647.605 0.140 647.675 ; - END - END w0_wd_in[60] - PIN w0_wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 658.385 0.140 658.455 ; - END - END w0_wd_in[61] - PIN w0_wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 669.165 0.140 669.235 ; - END - END w0_wd_in[62] - PIN w0_wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 679.945 0.140 680.015 ; - END - END w0_wd_in[63] - PIN w0_wd_in[64] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 690.725 0.140 690.795 ; - END - END w0_wd_in[64] - PIN w0_wd_in[65] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 701.505 0.140 701.575 ; - END - END w0_wd_in[65] - PIN w0_wd_in[66] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 712.285 0.140 712.355 ; - END - END w0_wd_in[66] - PIN w0_wd_in[67] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 723.065 0.140 723.135 ; - END - END w0_wd_in[67] - PIN w0_wd_in[68] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 733.845 0.140 733.915 ; - END - END w0_wd_in[68] - PIN w0_wd_in[69] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 744.625 0.140 744.695 ; - END - END w0_wd_in[69] - PIN w0_wd_in[70] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 755.405 0.140 755.475 ; - END - END w0_wd_in[70] - PIN w0_wd_in[71] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 766.185 0.140 766.255 ; - END - END w0_wd_in[71] - PIN w0_wd_in[72] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 776.965 0.140 777.035 ; - END - END w0_wd_in[72] - PIN w0_wd_in[73] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 787.745 0.140 787.815 ; - END - END w0_wd_in[73] - PIN w0_wd_in[74] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 798.525 0.140 798.595 ; - END - END w0_wd_in[74] - PIN w0_wd_in[75] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 809.305 0.140 809.375 ; - END - END w0_wd_in[75] - PIN w0_wd_in[76] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 820.085 0.140 820.155 ; - END - END w0_wd_in[76] - PIN w0_wd_in[77] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 830.865 0.140 830.935 ; - END - END w0_wd_in[77] - PIN w0_wd_in[78] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 841.645 0.140 841.715 ; - END - END w0_wd_in[78] - PIN w0_wd_in[79] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 852.425 0.140 852.495 ; - END - END w0_wd_in[79] - PIN w0_wd_in[80] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 863.205 0.140 863.275 ; - END - END w0_wd_in[80] - PIN w0_wd_in[81] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 873.985 0.140 874.055 ; - END - END w0_wd_in[81] - PIN w0_wd_in[82] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 884.765 0.140 884.835 ; - END - END w0_wd_in[82] - PIN w0_wd_in[83] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 895.545 0.140 895.615 ; - END - END w0_wd_in[83] - PIN w0_wd_in[84] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 906.325 0.140 906.395 ; - END - END w0_wd_in[84] - PIN w0_wd_in[85] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 917.105 0.140 917.175 ; - END - END w0_wd_in[85] - PIN w0_wd_in[86] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 927.885 0.140 927.955 ; - END - END w0_wd_in[86] - PIN w0_wd_in[87] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 938.665 0.140 938.735 ; - END - END w0_wd_in[87] - PIN w0_wd_in[88] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 949.445 0.140 949.515 ; - END - END w0_wd_in[88] - PIN w0_wd_in[89] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 960.225 0.140 960.295 ; - END - END w0_wd_in[89] - PIN w0_wd_in[90] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 971.005 0.140 971.075 ; - END - END w0_wd_in[90] - PIN w0_wd_in[91] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 981.785 0.140 981.855 ; - END - END w0_wd_in[91] - PIN w0_wd_in[92] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 992.565 0.140 992.635 ; - END - END w0_wd_in[92] - PIN w0_wd_in[93] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1003.345 0.140 1003.415 ; - END - END w0_wd_in[93] - PIN w0_wd_in[94] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1014.125 0.140 1014.195 ; - END - END w0_wd_in[94] - PIN w0_wd_in[95] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1024.905 0.140 1024.975 ; - END - END w0_wd_in[95] - PIN w0_wd_in[96] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1035.685 0.140 1035.755 ; - END - END w0_wd_in[96] - PIN w0_wd_in[97] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1046.465 0.140 1046.535 ; - END - END w0_wd_in[97] - PIN w0_wd_in[98] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1057.245 0.140 1057.315 ; - END - END w0_wd_in[98] - PIN w0_wd_in[99] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1068.025 0.140 1068.095 ; - END - END w0_wd_in[99] - PIN w0_wd_in[100] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1078.805 0.140 1078.875 ; - END - END w0_wd_in[100] - PIN w0_wd_in[101] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1089.585 0.140 1089.655 ; - END - END w0_wd_in[101] - PIN w0_wd_in[102] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1100.365 0.140 1100.435 ; - END - END w0_wd_in[102] - PIN w0_wd_in[103] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1111.145 0.140 1111.215 ; - END - END w0_wd_in[103] - PIN w0_wd_in[104] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1121.925 0.140 1121.995 ; - END - END w0_wd_in[104] - PIN w0_wd_in[105] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1132.705 0.140 1132.775 ; - END - END w0_wd_in[105] - PIN w0_wd_in[106] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1143.485 0.140 1143.555 ; - END - END w0_wd_in[106] - PIN w0_wd_in[107] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1154.265 0.140 1154.335 ; - END - END w0_wd_in[107] - PIN w0_wd_in[108] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1165.045 0.140 1165.115 ; - END - END w0_wd_in[108] - PIN w0_wd_in[109] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1175.825 0.140 1175.895 ; - END - END w0_wd_in[109] - PIN w0_wd_in[110] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1186.605 0.140 1186.675 ; - END - END w0_wd_in[110] - PIN w0_wd_in[111] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1197.385 0.140 1197.455 ; - END - END w0_wd_in[111] - PIN w0_wd_in[112] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1208.165 0.140 1208.235 ; - END - END w0_wd_in[112] - PIN w0_wd_in[113] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1218.945 0.140 1219.015 ; - END - END w0_wd_in[113] - PIN w0_wd_in[114] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1229.725 0.140 1229.795 ; - END - END w0_wd_in[114] - PIN w0_wd_in[115] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1240.505 0.140 1240.575 ; - END - END w0_wd_in[115] - PIN w0_wd_in[116] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1251.285 0.140 1251.355 ; - END - END w0_wd_in[116] - PIN w0_wd_in[117] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1262.065 0.140 1262.135 ; - END - END w0_wd_in[117] - PIN w0_wd_in[118] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1272.845 0.140 1272.915 ; - END - END w0_wd_in[118] - PIN w0_wd_in[119] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1283.625 0.140 1283.695 ; - END - END w0_wd_in[119] - PIN w0_wd_in[120] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1294.405 0.140 1294.475 ; - END - END w0_wd_in[120] - PIN w0_wd_in[121] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1305.185 0.140 1305.255 ; - END - END w0_wd_in[121] - PIN w0_wd_in[122] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1315.965 0.140 1316.035 ; - END - END w0_wd_in[122] - PIN w0_wd_in[123] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1326.745 0.140 1326.815 ; - END - END w0_wd_in[123] - PIN w0_wd_in[124] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1337.525 0.140 1337.595 ; - END - END w0_wd_in[124] - PIN w0_wd_in[125] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1348.305 0.140 1348.375 ; - END - END w0_wd_in[125] - PIN w0_wd_in[126] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1359.085 0.140 1359.155 ; - END - END w0_wd_in[126] - PIN w0_wd_in[127] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1369.865 0.140 1369.935 ; - END - END w0_wd_in[127] - PIN w0_wd_in[128] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 0.805 1609.300 0.875 ; - END - END w0_wd_in[128] - PIN w0_wd_in[129] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 11.585 1609.300 11.655 ; - END - END w0_wd_in[129] - PIN w0_wd_in[130] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 22.365 1609.300 22.435 ; - END - END w0_wd_in[130] - PIN w0_wd_in[131] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 33.145 1609.300 33.215 ; - END - END w0_wd_in[131] - PIN w0_wd_in[132] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 43.925 1609.300 43.995 ; - END - END w0_wd_in[132] - PIN w0_wd_in[133] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 54.705 1609.300 54.775 ; - END - END w0_wd_in[133] - PIN w0_wd_in[134] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 65.485 1609.300 65.555 ; - END - END w0_wd_in[134] - PIN w0_wd_in[135] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 76.265 1609.300 76.335 ; - END - END w0_wd_in[135] - PIN w0_wd_in[136] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 87.045 1609.300 87.115 ; - END - END w0_wd_in[136] - PIN w0_wd_in[137] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 97.825 1609.300 97.895 ; - END - END w0_wd_in[137] - PIN w0_wd_in[138] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 108.605 1609.300 108.675 ; - END - END w0_wd_in[138] - PIN w0_wd_in[139] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 119.385 1609.300 119.455 ; - END - END w0_wd_in[139] - PIN w0_wd_in[140] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 130.165 1609.300 130.235 ; - END - END w0_wd_in[140] - PIN w0_wd_in[141] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 140.945 1609.300 141.015 ; - END - END w0_wd_in[141] - PIN w0_wd_in[142] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 151.725 1609.300 151.795 ; - END - END w0_wd_in[142] - PIN w0_wd_in[143] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 162.505 1609.300 162.575 ; - END - END w0_wd_in[143] - PIN w0_wd_in[144] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 173.285 1609.300 173.355 ; - END - END w0_wd_in[144] - PIN w0_wd_in[145] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 184.065 1609.300 184.135 ; - END - END w0_wd_in[145] - PIN w0_wd_in[146] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 194.845 1609.300 194.915 ; - END - END w0_wd_in[146] - PIN w0_wd_in[147] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 205.625 1609.300 205.695 ; - END - END w0_wd_in[147] - PIN w0_wd_in[148] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 216.405 1609.300 216.475 ; - END - END w0_wd_in[148] - PIN w0_wd_in[149] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 227.185 1609.300 227.255 ; - END - END w0_wd_in[149] - PIN w0_wd_in[150] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 237.965 1609.300 238.035 ; - END - END w0_wd_in[150] - PIN w0_wd_in[151] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 248.745 1609.300 248.815 ; - END - END w0_wd_in[151] - PIN w0_wd_in[152] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 259.525 1609.300 259.595 ; - END - END w0_wd_in[152] - PIN w0_wd_in[153] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 270.305 1609.300 270.375 ; - END - END w0_wd_in[153] - PIN w0_wd_in[154] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 281.085 1609.300 281.155 ; - END - END w0_wd_in[154] - PIN w0_wd_in[155] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 291.865 1609.300 291.935 ; - END - END w0_wd_in[155] - PIN w0_wd_in[156] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 302.645 1609.300 302.715 ; - END - END w0_wd_in[156] - PIN w0_wd_in[157] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 313.425 1609.300 313.495 ; - END - END w0_wd_in[157] - PIN w0_wd_in[158] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 324.205 1609.300 324.275 ; - END - END w0_wd_in[158] - PIN w0_wd_in[159] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 334.985 1609.300 335.055 ; - END - END w0_wd_in[159] - PIN w0_wd_in[160] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 345.765 1609.300 345.835 ; - END - END w0_wd_in[160] - PIN w0_wd_in[161] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 356.545 1609.300 356.615 ; - END - END w0_wd_in[161] - PIN w0_wd_in[162] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 367.325 1609.300 367.395 ; - END - END w0_wd_in[162] - PIN w0_wd_in[163] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 378.105 1609.300 378.175 ; - END - END w0_wd_in[163] - PIN w0_wd_in[164] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 388.885 1609.300 388.955 ; - END - END w0_wd_in[164] - PIN w0_wd_in[165] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 399.665 1609.300 399.735 ; - END - END w0_wd_in[165] - PIN w0_wd_in[166] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 410.445 1609.300 410.515 ; - END - END w0_wd_in[166] - PIN w0_wd_in[167] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 421.225 1609.300 421.295 ; - END - END w0_wd_in[167] - PIN w0_wd_in[168] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 432.005 1609.300 432.075 ; - END - END w0_wd_in[168] - PIN w0_wd_in[169] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 442.785 1609.300 442.855 ; - END - END w0_wd_in[169] - PIN w0_wd_in[170] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 453.565 1609.300 453.635 ; - END - END w0_wd_in[170] - PIN w0_wd_in[171] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 464.345 1609.300 464.415 ; - END - END w0_wd_in[171] - PIN w0_wd_in[172] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 475.125 1609.300 475.195 ; - END - END w0_wd_in[172] - PIN w0_wd_in[173] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 485.905 1609.300 485.975 ; - END - END w0_wd_in[173] - PIN w0_wd_in[174] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 496.685 1609.300 496.755 ; - END - END w0_wd_in[174] - PIN w0_wd_in[175] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 507.465 1609.300 507.535 ; - END - END w0_wd_in[175] - PIN w0_wd_in[176] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 518.245 1609.300 518.315 ; - END - END w0_wd_in[176] - PIN w0_wd_in[177] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 529.025 1609.300 529.095 ; - END - END w0_wd_in[177] - PIN w0_wd_in[178] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 539.805 1609.300 539.875 ; - END - END w0_wd_in[178] - PIN w0_wd_in[179] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 550.585 1609.300 550.655 ; - END - END w0_wd_in[179] - PIN w0_wd_in[180] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 561.365 1609.300 561.435 ; - END - END w0_wd_in[180] - PIN w0_wd_in[181] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 572.145 1609.300 572.215 ; - END - END w0_wd_in[181] - PIN w0_wd_in[182] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 582.925 1609.300 582.995 ; - END - END w0_wd_in[182] - PIN w0_wd_in[183] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 593.705 1609.300 593.775 ; - END - END w0_wd_in[183] - PIN w0_wd_in[184] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 604.485 1609.300 604.555 ; - END - END w0_wd_in[184] - PIN w0_wd_in[185] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 615.265 1609.300 615.335 ; - END - END w0_wd_in[185] - PIN w0_wd_in[186] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 626.045 1609.300 626.115 ; - END - END w0_wd_in[186] - PIN w0_wd_in[187] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 636.825 1609.300 636.895 ; - END - END w0_wd_in[187] - PIN w0_wd_in[188] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 647.605 1609.300 647.675 ; - END - END w0_wd_in[188] - PIN w0_wd_in[189] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 658.385 1609.300 658.455 ; - END - END w0_wd_in[189] - PIN w0_wd_in[190] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 669.165 1609.300 669.235 ; - END - END w0_wd_in[190] - PIN w0_wd_in[191] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 679.945 1609.300 680.015 ; - END - END w0_wd_in[191] - PIN w0_wd_in[192] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 690.725 1609.300 690.795 ; - END - END w0_wd_in[192] - PIN w0_wd_in[193] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 701.505 1609.300 701.575 ; - END - END w0_wd_in[193] - PIN w0_wd_in[194] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 712.285 1609.300 712.355 ; - END - END w0_wd_in[194] - PIN w0_wd_in[195] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 723.065 1609.300 723.135 ; - END - END w0_wd_in[195] - PIN w0_wd_in[196] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 733.845 1609.300 733.915 ; - END - END w0_wd_in[196] - PIN w0_wd_in[197] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 744.625 1609.300 744.695 ; - END - END w0_wd_in[197] - PIN w0_wd_in[198] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 755.405 1609.300 755.475 ; - END - END w0_wd_in[198] - PIN w0_wd_in[199] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 766.185 1609.300 766.255 ; - END - END w0_wd_in[199] - PIN w0_wd_in[200] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 776.965 1609.300 777.035 ; - END - END w0_wd_in[200] - PIN w0_wd_in[201] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 787.745 1609.300 787.815 ; - END - END w0_wd_in[201] - PIN w0_wd_in[202] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 798.525 1609.300 798.595 ; - END - END w0_wd_in[202] - PIN w0_wd_in[203] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 809.305 1609.300 809.375 ; - END - END w0_wd_in[203] - PIN w0_wd_in[204] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 820.085 1609.300 820.155 ; - END - END w0_wd_in[204] - PIN w0_wd_in[205] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 830.865 1609.300 830.935 ; - END - END w0_wd_in[205] - PIN w0_wd_in[206] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 841.645 1609.300 841.715 ; - END - END w0_wd_in[206] - PIN w0_wd_in[207] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 852.425 1609.300 852.495 ; - END - END w0_wd_in[207] - PIN w0_wd_in[208] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 863.205 1609.300 863.275 ; - END - END w0_wd_in[208] - PIN w0_wd_in[209] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 873.985 1609.300 874.055 ; - END - END w0_wd_in[209] - PIN w0_wd_in[210] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 884.765 1609.300 884.835 ; - END - END w0_wd_in[210] - PIN w0_wd_in[211] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 895.545 1609.300 895.615 ; - END - END w0_wd_in[211] - PIN w0_wd_in[212] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 906.325 1609.300 906.395 ; - END - END w0_wd_in[212] - PIN w0_wd_in[213] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 917.105 1609.300 917.175 ; - END - END w0_wd_in[213] - PIN w0_wd_in[214] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 927.885 1609.300 927.955 ; - END - END w0_wd_in[214] - PIN w0_wd_in[215] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 938.665 1609.300 938.735 ; - END - END w0_wd_in[215] - PIN w0_wd_in[216] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 949.445 1609.300 949.515 ; - END - END w0_wd_in[216] - PIN w0_wd_in[217] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 960.225 1609.300 960.295 ; - END - END w0_wd_in[217] - PIN w0_wd_in[218] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 971.005 1609.300 971.075 ; - END - END w0_wd_in[218] - PIN w0_wd_in[219] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 981.785 1609.300 981.855 ; - END - END w0_wd_in[219] - PIN w0_wd_in[220] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 992.565 1609.300 992.635 ; - END - END w0_wd_in[220] - PIN w0_wd_in[221] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1003.345 1609.300 1003.415 ; - END - END w0_wd_in[221] - PIN w0_wd_in[222] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1014.125 1609.300 1014.195 ; - END - END w0_wd_in[222] - PIN w0_wd_in[223] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1024.905 1609.300 1024.975 ; - END - END w0_wd_in[223] - PIN w0_wd_in[224] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1035.685 1609.300 1035.755 ; - END - END w0_wd_in[224] - PIN w0_wd_in[225] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1046.465 1609.300 1046.535 ; - END - END w0_wd_in[225] - PIN w0_wd_in[226] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1057.245 1609.300 1057.315 ; - END - END w0_wd_in[226] - PIN w0_wd_in[227] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1068.025 1609.300 1068.095 ; - END - END w0_wd_in[227] - PIN w0_wd_in[228] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1078.805 1609.300 1078.875 ; - END - END w0_wd_in[228] - PIN w0_wd_in[229] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1089.585 1609.300 1089.655 ; - END - END w0_wd_in[229] - PIN w0_wd_in[230] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1100.365 1609.300 1100.435 ; - END - END w0_wd_in[230] - PIN w0_wd_in[231] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1111.145 1609.300 1111.215 ; - END - END w0_wd_in[231] - PIN w0_wd_in[232] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1121.925 1609.300 1121.995 ; - END - END w0_wd_in[232] - PIN w0_wd_in[233] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1132.705 1609.300 1132.775 ; - END - END w0_wd_in[233] - PIN w0_wd_in[234] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1143.485 1609.300 1143.555 ; - END - END w0_wd_in[234] - PIN w0_wd_in[235] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1154.265 1609.300 1154.335 ; - END - END w0_wd_in[235] - PIN w0_wd_in[236] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1165.045 1609.300 1165.115 ; - END - END w0_wd_in[236] - PIN w0_wd_in[237] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1175.825 1609.300 1175.895 ; - END - END w0_wd_in[237] - PIN w0_wd_in[238] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1186.605 1609.300 1186.675 ; - END - END w0_wd_in[238] - PIN w0_wd_in[239] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1197.385 1609.300 1197.455 ; - END - END w0_wd_in[239] - PIN w0_wd_in[240] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1208.165 1609.300 1208.235 ; - END - END w0_wd_in[240] - PIN w0_wd_in[241] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1218.945 1609.300 1219.015 ; - END - END w0_wd_in[241] - PIN w0_wd_in[242] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1229.725 1609.300 1229.795 ; - END - END w0_wd_in[242] - PIN w0_wd_in[243] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1240.505 1609.300 1240.575 ; - END - END w0_wd_in[243] - PIN w0_wd_in[244] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1251.285 1609.300 1251.355 ; - END - END w0_wd_in[244] - PIN w0_wd_in[245] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1262.065 1609.300 1262.135 ; - END - END w0_wd_in[245] - PIN w0_wd_in[246] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1272.845 1609.300 1272.915 ; - END - END w0_wd_in[246] - PIN w0_wd_in[247] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1283.625 1609.300 1283.695 ; - END - END w0_wd_in[247] - PIN w0_wd_in[248] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1294.405 1609.300 1294.475 ; - END - END w0_wd_in[248] - PIN w0_wd_in[249] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1305.185 1609.300 1305.255 ; - END - END w0_wd_in[249] - PIN w0_wd_in[250] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1315.965 1609.300 1316.035 ; - END - END w0_wd_in[250] - PIN w0_wd_in[251] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1326.745 1609.300 1326.815 ; - END - END w0_wd_in[251] - PIN w0_wd_in[252] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1337.525 1609.300 1337.595 ; - END - END w0_wd_in[252] - PIN w0_wd_in[253] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1348.305 1609.300 1348.375 ; - END - END w0_wd_in[253] - PIN w0_wd_in[254] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1359.085 1609.300 1359.155 ; - END - END w0_wd_in[254] - PIN w0_wd_in[255] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1369.865 1609.300 1369.935 ; - END - END w0_wd_in[255] - PIN w0_wd_in[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[256] - PIN w0_wd_in[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 4.145 0.000 4.215 0.140 ; - END - END w0_wd_in[257] - PIN w0_wd_in[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 7.185 0.000 7.255 0.140 ; - END - END w0_wd_in[258] - PIN w0_wd_in[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.225 0.000 10.295 0.140 ; - END - END w0_wd_in[259] - PIN w0_wd_in[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 13.265 0.000 13.335 0.140 ; - END - END w0_wd_in[260] - PIN w0_wd_in[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 16.305 0.000 16.375 0.140 ; - END - END w0_wd_in[261] - PIN w0_wd_in[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 19.345 0.000 19.415 0.140 ; - END - END w0_wd_in[262] - PIN w0_wd_in[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.385 0.000 22.455 0.140 ; - END - END w0_wd_in[263] - PIN w0_wd_in[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.425 0.000 25.495 0.140 ; - END - END w0_wd_in[264] - PIN w0_wd_in[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 28.465 0.000 28.535 0.140 ; - END - END w0_wd_in[265] - PIN w0_wd_in[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.505 0.000 31.575 0.140 ; - END - END w0_wd_in[266] - PIN w0_wd_in[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 34.545 0.000 34.615 0.140 ; - END - END w0_wd_in[267] - PIN w0_wd_in[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.585 0.000 37.655 0.140 ; - END - END w0_wd_in[268] - PIN w0_wd_in[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 40.625 0.000 40.695 0.140 ; - END - END w0_wd_in[269] - PIN w0_wd_in[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.665 0.000 43.735 0.140 ; - END - END w0_wd_in[270] - PIN w0_wd_in[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 46.705 0.000 46.775 0.140 ; - END - END w0_wd_in[271] - PIN w0_wd_in[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 49.745 0.000 49.815 0.140 ; - END - END w0_wd_in[272] - PIN w0_wd_in[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 52.785 0.000 52.855 0.140 ; - END - END w0_wd_in[273] - PIN w0_wd_in[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.825 0.000 55.895 0.140 ; - END - END w0_wd_in[274] - PIN w0_wd_in[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 58.865 0.000 58.935 0.140 ; - END - END w0_wd_in[275] - PIN w0_wd_in[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 61.905 0.000 61.975 0.140 ; - END - END w0_wd_in[276] - PIN w0_wd_in[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 64.945 0.000 65.015 0.140 ; - END - END w0_wd_in[277] - PIN w0_wd_in[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.985 0.000 68.055 0.140 ; - END - END w0_wd_in[278] - PIN w0_wd_in[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 71.025 0.000 71.095 0.140 ; - END - END w0_wd_in[279] - PIN w0_wd_in[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 74.065 0.000 74.135 0.140 ; - END - END w0_wd_in[280] - PIN w0_wd_in[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 77.105 0.000 77.175 0.140 ; - END - END w0_wd_in[281] - PIN w0_wd_in[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.145 0.000 80.215 0.140 ; - END - END w0_wd_in[282] - PIN w0_wd_in[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 83.185 0.000 83.255 0.140 ; - END - END w0_wd_in[283] - PIN w0_wd_in[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.225 0.000 86.295 0.140 ; - END - END w0_wd_in[284] - PIN w0_wd_in[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 89.265 0.000 89.335 0.140 ; - END - END w0_wd_in[285] - PIN w0_wd_in[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 92.305 0.000 92.375 0.140 ; - END - END w0_wd_in[286] - PIN w0_wd_in[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 95.345 0.000 95.415 0.140 ; - END - END w0_wd_in[287] - PIN w0_wd_in[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 98.385 0.000 98.455 0.140 ; - END - END w0_wd_in[288] - PIN w0_wd_in[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 101.425 0.000 101.495 0.140 ; - END - END w0_wd_in[289] - PIN w0_wd_in[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 104.465 0.000 104.535 0.140 ; - END - END w0_wd_in[290] - PIN w0_wd_in[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 107.505 0.000 107.575 0.140 ; - END - END w0_wd_in[291] - PIN w0_wd_in[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 110.545 0.000 110.615 0.140 ; - END - END w0_wd_in[292] - PIN w0_wd_in[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 113.585 0.000 113.655 0.140 ; - END - END w0_wd_in[293] - PIN w0_wd_in[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 116.625 0.000 116.695 0.140 ; - END - END w0_wd_in[294] - PIN w0_wd_in[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 119.665 0.000 119.735 0.140 ; - END - END w0_wd_in[295] - PIN w0_wd_in[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 122.705 0.000 122.775 0.140 ; - END - END w0_wd_in[296] - PIN w0_wd_in[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 125.745 0.000 125.815 0.140 ; - END - END w0_wd_in[297] - PIN w0_wd_in[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 128.785 0.000 128.855 0.140 ; - END - END w0_wd_in[298] - PIN w0_wd_in[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 131.825 0.000 131.895 0.140 ; - END - END w0_wd_in[299] - PIN w0_wd_in[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 134.865 0.000 134.935 0.140 ; - END - END w0_wd_in[300] - PIN w0_wd_in[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 137.905 0.000 137.975 0.140 ; - END - END w0_wd_in[301] - PIN w0_wd_in[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 140.945 0.000 141.015 0.140 ; - END - END w0_wd_in[302] - PIN w0_wd_in[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 143.985 0.000 144.055 0.140 ; - END - END w0_wd_in[303] - PIN w0_wd_in[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 147.025 0.000 147.095 0.140 ; - END - END w0_wd_in[304] - PIN w0_wd_in[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 150.065 0.000 150.135 0.140 ; - END - END w0_wd_in[305] - PIN w0_wd_in[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 153.105 0.000 153.175 0.140 ; - END - END w0_wd_in[306] - PIN w0_wd_in[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 156.145 0.000 156.215 0.140 ; - END - END w0_wd_in[307] - PIN w0_wd_in[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 159.185 0.000 159.255 0.140 ; - END - END w0_wd_in[308] - PIN w0_wd_in[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 162.225 0.000 162.295 0.140 ; - END - END w0_wd_in[309] - PIN w0_wd_in[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 165.265 0.000 165.335 0.140 ; - END - END w0_wd_in[310] - PIN w0_wd_in[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 168.305 0.000 168.375 0.140 ; - END - END w0_wd_in[311] - PIN w0_wd_in[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 171.345 0.000 171.415 0.140 ; - END - END w0_wd_in[312] - PIN w0_wd_in[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 174.385 0.000 174.455 0.140 ; - END - END w0_wd_in[313] - PIN w0_wd_in[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 177.425 0.000 177.495 0.140 ; - END - END w0_wd_in[314] - PIN w0_wd_in[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 180.465 0.000 180.535 0.140 ; - END - END w0_wd_in[315] - PIN w0_wd_in[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 183.505 0.000 183.575 0.140 ; - END - END w0_wd_in[316] - PIN w0_wd_in[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 186.545 0.000 186.615 0.140 ; - END - END w0_wd_in[317] - PIN w0_wd_in[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 189.585 0.000 189.655 0.140 ; - END - END w0_wd_in[318] - PIN w0_wd_in[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 192.625 0.000 192.695 0.140 ; - END - END w0_wd_in[319] - PIN w0_wd_in[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 195.665 0.000 195.735 0.140 ; - END - END w0_wd_in[320] - PIN w0_wd_in[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 198.705 0.000 198.775 0.140 ; - END - END w0_wd_in[321] - PIN w0_wd_in[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 201.745 0.000 201.815 0.140 ; - END - END w0_wd_in[322] - PIN w0_wd_in[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 204.785 0.000 204.855 0.140 ; - END - END w0_wd_in[323] - PIN w0_wd_in[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 207.825 0.000 207.895 0.140 ; - END - END w0_wd_in[324] - PIN w0_wd_in[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 210.865 0.000 210.935 0.140 ; - END - END w0_wd_in[325] - PIN w0_wd_in[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 213.905 0.000 213.975 0.140 ; - END - END w0_wd_in[326] - PIN w0_wd_in[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 216.945 0.000 217.015 0.140 ; - END - END w0_wd_in[327] - PIN w0_wd_in[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 219.985 0.000 220.055 0.140 ; - END - END w0_wd_in[328] - PIN w0_wd_in[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 223.025 0.000 223.095 0.140 ; - END - END w0_wd_in[329] - PIN w0_wd_in[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 226.065 0.000 226.135 0.140 ; - END - END w0_wd_in[330] - PIN w0_wd_in[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 229.105 0.000 229.175 0.140 ; - END - END w0_wd_in[331] - PIN w0_wd_in[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 232.145 0.000 232.215 0.140 ; - END - END w0_wd_in[332] - PIN w0_wd_in[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 235.185 0.000 235.255 0.140 ; - END - END w0_wd_in[333] - PIN w0_wd_in[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 238.225 0.000 238.295 0.140 ; - END - END w0_wd_in[334] - PIN w0_wd_in[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 241.265 0.000 241.335 0.140 ; - END - END w0_wd_in[335] - PIN w0_wd_in[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 244.305 0.000 244.375 0.140 ; - END - END w0_wd_in[336] - PIN w0_wd_in[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 247.345 0.000 247.415 0.140 ; - END - END w0_wd_in[337] - PIN w0_wd_in[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 250.385 0.000 250.455 0.140 ; - END - END w0_wd_in[338] - PIN w0_wd_in[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 253.425 0.000 253.495 0.140 ; - END - END w0_wd_in[339] - PIN w0_wd_in[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 256.465 0.000 256.535 0.140 ; - END - END w0_wd_in[340] - PIN w0_wd_in[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 259.505 0.000 259.575 0.140 ; - END - END w0_wd_in[341] - PIN w0_wd_in[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 262.545 0.000 262.615 0.140 ; - END - END w0_wd_in[342] - PIN w0_wd_in[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 265.585 0.000 265.655 0.140 ; - END - END w0_wd_in[343] - PIN w0_wd_in[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 268.625 0.000 268.695 0.140 ; - END - END w0_wd_in[344] - PIN w0_wd_in[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 271.665 0.000 271.735 0.140 ; - END - END w0_wd_in[345] - PIN w0_wd_in[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 274.705 0.000 274.775 0.140 ; - END - END w0_wd_in[346] - PIN w0_wd_in[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 277.745 0.000 277.815 0.140 ; - END - END w0_wd_in[347] - PIN w0_wd_in[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 280.785 0.000 280.855 0.140 ; - END - END w0_wd_in[348] - PIN w0_wd_in[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 283.825 0.000 283.895 0.140 ; - END - END w0_wd_in[349] - PIN w0_wd_in[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 286.865 0.000 286.935 0.140 ; - END - END w0_wd_in[350] - PIN w0_wd_in[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 289.905 0.000 289.975 0.140 ; - END - END w0_wd_in[351] - PIN w0_wd_in[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 292.945 0.000 293.015 0.140 ; - END - END w0_wd_in[352] - PIN w0_wd_in[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 295.985 0.000 296.055 0.140 ; - END - END w0_wd_in[353] - PIN w0_wd_in[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 299.025 0.000 299.095 0.140 ; - END - END w0_wd_in[354] - PIN w0_wd_in[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 302.065 0.000 302.135 0.140 ; - END - END w0_wd_in[355] - PIN w0_wd_in[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 305.105 0.000 305.175 0.140 ; - END - END w0_wd_in[356] - PIN w0_wd_in[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 308.145 0.000 308.215 0.140 ; - END - END w0_wd_in[357] - PIN w0_wd_in[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 311.185 0.000 311.255 0.140 ; - END - END w0_wd_in[358] - PIN w0_wd_in[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 314.225 0.000 314.295 0.140 ; - END - END w0_wd_in[359] - PIN w0_wd_in[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 317.265 0.000 317.335 0.140 ; - END - END w0_wd_in[360] - PIN w0_wd_in[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 320.305 0.000 320.375 0.140 ; - END - END w0_wd_in[361] - PIN w0_wd_in[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 323.345 0.000 323.415 0.140 ; - END - END w0_wd_in[362] - PIN w0_wd_in[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 326.385 0.000 326.455 0.140 ; - END - END w0_wd_in[363] - PIN w0_wd_in[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 329.425 0.000 329.495 0.140 ; - END - END w0_wd_in[364] - PIN w0_wd_in[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 332.465 0.000 332.535 0.140 ; - END - END w0_wd_in[365] - PIN w0_wd_in[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 335.505 0.000 335.575 0.140 ; - END - END w0_wd_in[366] - PIN w0_wd_in[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 338.545 0.000 338.615 0.140 ; - END - END w0_wd_in[367] - PIN w0_wd_in[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 341.585 0.000 341.655 0.140 ; - END - END w0_wd_in[368] - PIN w0_wd_in[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 344.625 0.000 344.695 0.140 ; - END - END w0_wd_in[369] - PIN w0_wd_in[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 347.665 0.000 347.735 0.140 ; - END - END w0_wd_in[370] - PIN w0_wd_in[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 350.705 0.000 350.775 0.140 ; - END - END w0_wd_in[371] - PIN w0_wd_in[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 353.745 0.000 353.815 0.140 ; - END - END w0_wd_in[372] - PIN w0_wd_in[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 356.785 0.000 356.855 0.140 ; - END - END w0_wd_in[373] - PIN w0_wd_in[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 359.825 0.000 359.895 0.140 ; - END - END w0_wd_in[374] - PIN w0_wd_in[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 362.865 0.000 362.935 0.140 ; - END - END w0_wd_in[375] - PIN w0_wd_in[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 365.905 0.000 365.975 0.140 ; - END - END w0_wd_in[376] - PIN w0_wd_in[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 368.945 0.000 369.015 0.140 ; - END - END w0_wd_in[377] - PIN w0_wd_in[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 371.985 0.000 372.055 0.140 ; - END - END w0_wd_in[378] - PIN w0_wd_in[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 375.025 0.000 375.095 0.140 ; - END - END w0_wd_in[379] - PIN w0_wd_in[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 378.065 0.000 378.135 0.140 ; - END - END w0_wd_in[380] - PIN w0_wd_in[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 381.105 0.000 381.175 0.140 ; - END - END w0_wd_in[381] - PIN w0_wd_in[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 384.145 0.000 384.215 0.140 ; - END - END w0_wd_in[382] - PIN w0_wd_in[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 387.185 0.000 387.255 0.140 ; - END - END w0_wd_in[383] - PIN w0_wd_in[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 390.225 0.000 390.295 0.140 ; - END - END w0_wd_in[384] - PIN w0_wd_in[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 393.265 0.000 393.335 0.140 ; - END - END w0_wd_in[385] - PIN w0_wd_in[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 396.305 0.000 396.375 0.140 ; - END - END w0_wd_in[386] - PIN w0_wd_in[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 399.345 0.000 399.415 0.140 ; - END - END w0_wd_in[387] - PIN w0_wd_in[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 402.385 0.000 402.455 0.140 ; - END - END w0_wd_in[388] - PIN w0_wd_in[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 405.425 0.000 405.495 0.140 ; - END - END w0_wd_in[389] - PIN w0_wd_in[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 408.465 0.000 408.535 0.140 ; - END - END w0_wd_in[390] - PIN w0_wd_in[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 411.505 0.000 411.575 0.140 ; - END - END w0_wd_in[391] - PIN w0_wd_in[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 414.545 0.000 414.615 0.140 ; - END - END w0_wd_in[392] - PIN w0_wd_in[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 417.585 0.000 417.655 0.140 ; - END - END w0_wd_in[393] - PIN w0_wd_in[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 420.625 0.000 420.695 0.140 ; - END - END w0_wd_in[394] - PIN w0_wd_in[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 423.665 0.000 423.735 0.140 ; - END - END w0_wd_in[395] - PIN w0_wd_in[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 426.705 0.000 426.775 0.140 ; - END - END w0_wd_in[396] - PIN w0_wd_in[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 429.745 0.000 429.815 0.140 ; - END - END w0_wd_in[397] - PIN w0_wd_in[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 432.785 0.000 432.855 0.140 ; - END - END w0_wd_in[398] - PIN w0_wd_in[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 435.825 0.000 435.895 0.140 ; - END - END w0_wd_in[399] - PIN w0_wd_in[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 438.865 0.000 438.935 0.140 ; - END - END w0_wd_in[400] - PIN w0_wd_in[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 441.905 0.000 441.975 0.140 ; - END - END w0_wd_in[401] - PIN w0_wd_in[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 444.945 0.000 445.015 0.140 ; - END - END w0_wd_in[402] - PIN w0_wd_in[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 447.985 0.000 448.055 0.140 ; - END - END w0_wd_in[403] - PIN w0_wd_in[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 451.025 0.000 451.095 0.140 ; - END - END w0_wd_in[404] - PIN w0_wd_in[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 454.065 0.000 454.135 0.140 ; - END - END w0_wd_in[405] - PIN w0_wd_in[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 457.105 0.000 457.175 0.140 ; - END - END w0_wd_in[406] - PIN w0_wd_in[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 460.145 0.000 460.215 0.140 ; - END - END w0_wd_in[407] - PIN w0_wd_in[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 463.185 0.000 463.255 0.140 ; - END - END w0_wd_in[408] - PIN w0_wd_in[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 466.225 0.000 466.295 0.140 ; - END - END w0_wd_in[409] - PIN w0_wd_in[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 469.265 0.000 469.335 0.140 ; - END - END w0_wd_in[410] - PIN w0_wd_in[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 472.305 0.000 472.375 0.140 ; - END - END w0_wd_in[411] - PIN w0_wd_in[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 475.345 0.000 475.415 0.140 ; - END - END w0_wd_in[412] - PIN w0_wd_in[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 478.385 0.000 478.455 0.140 ; - END - END w0_wd_in[413] - PIN w0_wd_in[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 481.425 0.000 481.495 0.140 ; - END - END w0_wd_in[414] - PIN w0_wd_in[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 484.465 0.000 484.535 0.140 ; - END - END w0_wd_in[415] - PIN w0_wd_in[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 487.505 0.000 487.575 0.140 ; - END - END w0_wd_in[416] - PIN w0_wd_in[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 490.545 0.000 490.615 0.140 ; - END - END w0_wd_in[417] - PIN w0_wd_in[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 493.585 0.000 493.655 0.140 ; - END - END w0_wd_in[418] - PIN w0_wd_in[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 496.625 0.000 496.695 0.140 ; - END - END w0_wd_in[419] - PIN w0_wd_in[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 499.665 0.000 499.735 0.140 ; - END - END w0_wd_in[420] - PIN w0_wd_in[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 502.705 0.000 502.775 0.140 ; - END - END w0_wd_in[421] - PIN w0_wd_in[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 505.745 0.000 505.815 0.140 ; - END - END w0_wd_in[422] - PIN w0_wd_in[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 508.785 0.000 508.855 0.140 ; - END - END w0_wd_in[423] - PIN w0_wd_in[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 511.825 0.000 511.895 0.140 ; - END - END w0_wd_in[424] - PIN w0_wd_in[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 514.865 0.000 514.935 0.140 ; - END - END w0_wd_in[425] - PIN w0_wd_in[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 517.905 0.000 517.975 0.140 ; - END - END w0_wd_in[426] - PIN w0_wd_in[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 520.945 0.000 521.015 0.140 ; - END - END w0_wd_in[427] - PIN w0_wd_in[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 523.985 0.000 524.055 0.140 ; - END - END w0_wd_in[428] - PIN w0_wd_in[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 527.025 0.000 527.095 0.140 ; - END - END w0_wd_in[429] - PIN w0_wd_in[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 530.065 0.000 530.135 0.140 ; - END - END w0_wd_in[430] - PIN w0_wd_in[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 533.105 0.000 533.175 0.140 ; - END - END w0_wd_in[431] - PIN w0_wd_in[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 536.145 0.000 536.215 0.140 ; - END - END w0_wd_in[432] - PIN w0_wd_in[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 539.185 0.000 539.255 0.140 ; - END - END w0_wd_in[433] - PIN w0_wd_in[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 542.225 0.000 542.295 0.140 ; - END - END w0_wd_in[434] - PIN w0_wd_in[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 545.265 0.000 545.335 0.140 ; - END - END w0_wd_in[435] - PIN w0_wd_in[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 548.305 0.000 548.375 0.140 ; - END - END w0_wd_in[436] - PIN w0_wd_in[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 551.345 0.000 551.415 0.140 ; - END - END w0_wd_in[437] - PIN w0_wd_in[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 554.385 0.000 554.455 0.140 ; - END - END w0_wd_in[438] - PIN w0_wd_in[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 557.425 0.000 557.495 0.140 ; - END - END w0_wd_in[439] - PIN w0_wd_in[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 560.465 0.000 560.535 0.140 ; - END - END w0_wd_in[440] - PIN w0_wd_in[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 563.505 0.000 563.575 0.140 ; - END - END w0_wd_in[441] - PIN w0_wd_in[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 566.545 0.000 566.615 0.140 ; - END - END w0_wd_in[442] - PIN w0_wd_in[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 569.585 0.000 569.655 0.140 ; - END - END w0_wd_in[443] - PIN w0_wd_in[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 572.625 0.000 572.695 0.140 ; - END - END w0_wd_in[444] - PIN w0_wd_in[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 575.665 0.000 575.735 0.140 ; - END - END w0_wd_in[445] - PIN w0_wd_in[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 578.705 0.000 578.775 0.140 ; - END - END w0_wd_in[446] - PIN w0_wd_in[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 581.745 0.000 581.815 0.140 ; - END - END w0_wd_in[447] - PIN w0_wd_in[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 584.785 0.000 584.855 0.140 ; - END - END w0_wd_in[448] - PIN w0_wd_in[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 587.825 0.000 587.895 0.140 ; - END - END w0_wd_in[449] - PIN w0_wd_in[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 590.865 0.000 590.935 0.140 ; - END - END w0_wd_in[450] - PIN w0_wd_in[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 593.905 0.000 593.975 0.140 ; - END - END w0_wd_in[451] - PIN w0_wd_in[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 596.945 0.000 597.015 0.140 ; - END - END w0_wd_in[452] - PIN w0_wd_in[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 599.985 0.000 600.055 0.140 ; - END - END w0_wd_in[453] - PIN w0_wd_in[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 603.025 0.000 603.095 0.140 ; - END - END w0_wd_in[454] - PIN w0_wd_in[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 606.065 0.000 606.135 0.140 ; - END - END w0_wd_in[455] - PIN w0_wd_in[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 609.105 0.000 609.175 0.140 ; - END - END w0_wd_in[456] - PIN w0_wd_in[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 612.145 0.000 612.215 0.140 ; - END - END w0_wd_in[457] - PIN w0_wd_in[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 615.185 0.000 615.255 0.140 ; - END - END w0_wd_in[458] - PIN w0_wd_in[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 618.225 0.000 618.295 0.140 ; - END - END w0_wd_in[459] - PIN w0_wd_in[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 621.265 0.000 621.335 0.140 ; - END - END w0_wd_in[460] - PIN w0_wd_in[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 624.305 0.000 624.375 0.140 ; - END - END w0_wd_in[461] - PIN w0_wd_in[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 627.345 0.000 627.415 0.140 ; - END - END w0_wd_in[462] - PIN w0_wd_in[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 630.385 0.000 630.455 0.140 ; - END - END w0_wd_in[463] - PIN w0_wd_in[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 633.425 0.000 633.495 0.140 ; - END - END w0_wd_in[464] - PIN w0_wd_in[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 636.465 0.000 636.535 0.140 ; - END - END w0_wd_in[465] - PIN w0_wd_in[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 639.505 0.000 639.575 0.140 ; - END - END w0_wd_in[466] - PIN w0_wd_in[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 642.545 0.000 642.615 0.140 ; - END - END w0_wd_in[467] - PIN w0_wd_in[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 645.585 0.000 645.655 0.140 ; - END - END w0_wd_in[468] - PIN w0_wd_in[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 648.625 0.000 648.695 0.140 ; - END - END w0_wd_in[469] - PIN w0_wd_in[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 651.665 0.000 651.735 0.140 ; - END - END w0_wd_in[470] - PIN w0_wd_in[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 654.705 0.000 654.775 0.140 ; - END - END w0_wd_in[471] - PIN w0_wd_in[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 657.745 0.000 657.815 0.140 ; - END - END w0_wd_in[472] - PIN w0_wd_in[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 660.785 0.000 660.855 0.140 ; - END - END w0_wd_in[473] - PIN w0_wd_in[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 663.825 0.000 663.895 0.140 ; - END - END w0_wd_in[474] - PIN w0_wd_in[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 666.865 0.000 666.935 0.140 ; - END - END w0_wd_in[475] - PIN w0_wd_in[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 669.905 0.000 669.975 0.140 ; - END - END w0_wd_in[476] - PIN w0_wd_in[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 672.945 0.000 673.015 0.140 ; - END - END w0_wd_in[477] - PIN w0_wd_in[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 675.985 0.000 676.055 0.140 ; - END - END w0_wd_in[478] - PIN w0_wd_in[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 679.025 0.000 679.095 0.140 ; - END - END w0_wd_in[479] - PIN w0_wd_in[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 682.065 0.000 682.135 0.140 ; - END - END w0_wd_in[480] - PIN w0_wd_in[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 685.105 0.000 685.175 0.140 ; - END - END w0_wd_in[481] - PIN w0_wd_in[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 688.145 0.000 688.215 0.140 ; - END - END w0_wd_in[482] - PIN w0_wd_in[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 691.185 0.000 691.255 0.140 ; - END - END w0_wd_in[483] - PIN w0_wd_in[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 694.225 0.000 694.295 0.140 ; - END - END w0_wd_in[484] - PIN w0_wd_in[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 697.265 0.000 697.335 0.140 ; - END - END w0_wd_in[485] - PIN w0_wd_in[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 700.305 0.000 700.375 0.140 ; - END - END w0_wd_in[486] - PIN w0_wd_in[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 703.345 0.000 703.415 0.140 ; - END - END w0_wd_in[487] - PIN w0_wd_in[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 706.385 0.000 706.455 0.140 ; - END - END w0_wd_in[488] - PIN w0_wd_in[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 709.425 0.000 709.495 0.140 ; - END - END w0_wd_in[489] - PIN w0_wd_in[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 712.465 0.000 712.535 0.140 ; - END - END w0_wd_in[490] - PIN w0_wd_in[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 715.505 0.000 715.575 0.140 ; - END - END w0_wd_in[491] - PIN w0_wd_in[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 718.545 0.000 718.615 0.140 ; - END - END w0_wd_in[492] - PIN w0_wd_in[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 721.585 0.000 721.655 0.140 ; - END - END w0_wd_in[493] - PIN w0_wd_in[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 724.625 0.000 724.695 0.140 ; - END - END w0_wd_in[494] - PIN w0_wd_in[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 727.665 0.000 727.735 0.140 ; - END - END w0_wd_in[495] - PIN w0_wd_in[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 730.705 0.000 730.775 0.140 ; - END - END w0_wd_in[496] - PIN w0_wd_in[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 733.745 0.000 733.815 0.140 ; - END - END w0_wd_in[497] - PIN w0_wd_in[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 736.785 0.000 736.855 0.140 ; - END - END w0_wd_in[498] - PIN w0_wd_in[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 739.825 0.000 739.895 0.140 ; - END - END w0_wd_in[499] - PIN w0_wd_in[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 742.865 0.000 742.935 0.140 ; - END - END w0_wd_in[500] - PIN w0_wd_in[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 745.905 0.000 745.975 0.140 ; - END - END w0_wd_in[501] - PIN w0_wd_in[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 748.945 0.000 749.015 0.140 ; - END - END w0_wd_in[502] - PIN w0_wd_in[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 751.985 0.000 752.055 0.140 ; - END - END w0_wd_in[503] - PIN w0_wd_in[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 755.025 0.000 755.095 0.140 ; - END - END w0_wd_in[504] - PIN w0_wd_in[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 758.065 0.000 758.135 0.140 ; - END - END w0_wd_in[505] - PIN w0_wd_in[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 761.105 0.000 761.175 0.140 ; - END - END w0_wd_in[506] - PIN w0_wd_in[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 764.145 0.000 764.215 0.140 ; - END - END w0_wd_in[507] - PIN w0_wd_in[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 767.185 0.000 767.255 0.140 ; - END - END w0_wd_in[508] - PIN w0_wd_in[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 770.225 0.000 770.295 0.140 ; - END - END w0_wd_in[509] - PIN w0_wd_in[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 773.265 0.000 773.335 0.140 ; - END - END w0_wd_in[510] - PIN w0_wd_in[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 776.305 0.000 776.375 0.140 ; - END - END w0_wd_in[511] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 779.345 0.000 779.415 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 782.385 0.000 782.455 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 785.425 0.000 785.495 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 788.465 0.000 788.535 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 791.505 0.000 791.575 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 794.545 0.000 794.615 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 797.585 0.000 797.655 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 800.625 0.000 800.695 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 803.665 0.000 803.735 0.140 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 806.705 0.000 806.775 0.140 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 809.745 0.000 809.815 0.140 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 812.785 0.000 812.855 0.140 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 815.825 0.000 815.895 0.140 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 818.865 0.000 818.935 0.140 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 821.905 0.000 821.975 0.140 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 824.945 0.000 825.015 0.140 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 827.985 0.000 828.055 0.140 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 831.025 0.000 831.095 0.140 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 834.065 0.000 834.135 0.140 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 837.105 0.000 837.175 0.140 ; - END - END r0_rd_out[19] - PIN r0_rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 840.145 0.000 840.215 0.140 ; - END - END r0_rd_out[20] - PIN r0_rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 843.185 0.000 843.255 0.140 ; - END - END r0_rd_out[21] - PIN r0_rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 846.225 0.000 846.295 0.140 ; - END - END r0_rd_out[22] - PIN r0_rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 849.265 0.000 849.335 0.140 ; - END - END r0_rd_out[23] - PIN r0_rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 852.305 0.000 852.375 0.140 ; - END - END r0_rd_out[24] - PIN r0_rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 855.345 0.000 855.415 0.140 ; - END - END r0_rd_out[25] - PIN r0_rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 858.385 0.000 858.455 0.140 ; - END - END r0_rd_out[26] - PIN r0_rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 861.425 0.000 861.495 0.140 ; - END - END r0_rd_out[27] - PIN r0_rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 864.465 0.000 864.535 0.140 ; - END - END r0_rd_out[28] - PIN r0_rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 867.505 0.000 867.575 0.140 ; - END - END r0_rd_out[29] - PIN r0_rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 870.545 0.000 870.615 0.140 ; - END - END r0_rd_out[30] - PIN r0_rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 873.585 0.000 873.655 0.140 ; - END - END r0_rd_out[31] - PIN r0_rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 876.625 0.000 876.695 0.140 ; - END - END r0_rd_out[32] - PIN r0_rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 879.665 0.000 879.735 0.140 ; - END - END r0_rd_out[33] - PIN r0_rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 882.705 0.000 882.775 0.140 ; - END - END r0_rd_out[34] - PIN r0_rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 885.745 0.000 885.815 0.140 ; - END - END r0_rd_out[35] - PIN r0_rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 888.785 0.000 888.855 0.140 ; - END - END r0_rd_out[36] - PIN r0_rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 891.825 0.000 891.895 0.140 ; - END - END r0_rd_out[37] - PIN r0_rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 894.865 0.000 894.935 0.140 ; - END - END r0_rd_out[38] - PIN r0_rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 897.905 0.000 897.975 0.140 ; - END - END r0_rd_out[39] - PIN r0_rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 900.945 0.000 901.015 0.140 ; - END - END r0_rd_out[40] - PIN r0_rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 903.985 0.000 904.055 0.140 ; - END - END r0_rd_out[41] - PIN r0_rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 907.025 0.000 907.095 0.140 ; - END - END r0_rd_out[42] - PIN r0_rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 910.065 0.000 910.135 0.140 ; - END - END r0_rd_out[43] - PIN r0_rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 913.105 0.000 913.175 0.140 ; - END - END r0_rd_out[44] - PIN r0_rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 916.145 0.000 916.215 0.140 ; - END - END r0_rd_out[45] - PIN r0_rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 919.185 0.000 919.255 0.140 ; - END - END r0_rd_out[46] - PIN r0_rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 922.225 0.000 922.295 0.140 ; - END - END r0_rd_out[47] - PIN r0_rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 925.265 0.000 925.335 0.140 ; - END - END r0_rd_out[48] - PIN r0_rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 928.305 0.000 928.375 0.140 ; - END - END r0_rd_out[49] - PIN r0_rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 931.345 0.000 931.415 0.140 ; - END - END r0_rd_out[50] - PIN r0_rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 934.385 0.000 934.455 0.140 ; - END - END r0_rd_out[51] - PIN r0_rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 937.425 0.000 937.495 0.140 ; - END - END r0_rd_out[52] - PIN r0_rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 940.465 0.000 940.535 0.140 ; - END - END r0_rd_out[53] - PIN r0_rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 943.505 0.000 943.575 0.140 ; - END - END r0_rd_out[54] - PIN r0_rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 946.545 0.000 946.615 0.140 ; - END - END r0_rd_out[55] - PIN r0_rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 949.585 0.000 949.655 0.140 ; - END - END r0_rd_out[56] - PIN r0_rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 952.625 0.000 952.695 0.140 ; - END - END r0_rd_out[57] - PIN r0_rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 955.665 0.000 955.735 0.140 ; - END - END r0_rd_out[58] - PIN r0_rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 958.705 0.000 958.775 0.140 ; - END - END r0_rd_out[59] - PIN r0_rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 961.745 0.000 961.815 0.140 ; - END - END r0_rd_out[60] - PIN r0_rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 964.785 0.000 964.855 0.140 ; - END - END r0_rd_out[61] - PIN r0_rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 967.825 0.000 967.895 0.140 ; - END - END r0_rd_out[62] - PIN r0_rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 970.865 0.000 970.935 0.140 ; - END - END r0_rd_out[63] - PIN r0_rd_out[64] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 973.905 0.000 973.975 0.140 ; - END - END r0_rd_out[64] - PIN r0_rd_out[65] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 976.945 0.000 977.015 0.140 ; - END - END r0_rd_out[65] - PIN r0_rd_out[66] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 979.985 0.000 980.055 0.140 ; - END - END r0_rd_out[66] - PIN r0_rd_out[67] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 983.025 0.000 983.095 0.140 ; - END - END r0_rd_out[67] - PIN r0_rd_out[68] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 986.065 0.000 986.135 0.140 ; - END - END r0_rd_out[68] - PIN r0_rd_out[69] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 989.105 0.000 989.175 0.140 ; - END - END r0_rd_out[69] - PIN r0_rd_out[70] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 992.145 0.000 992.215 0.140 ; - END - END r0_rd_out[70] - PIN r0_rd_out[71] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 995.185 0.000 995.255 0.140 ; - END - END r0_rd_out[71] - PIN r0_rd_out[72] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 998.225 0.000 998.295 0.140 ; - END - END r0_rd_out[72] - PIN r0_rd_out[73] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1001.265 0.000 1001.335 0.140 ; - END - END r0_rd_out[73] - PIN r0_rd_out[74] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1004.305 0.000 1004.375 0.140 ; - END - END r0_rd_out[74] - PIN r0_rd_out[75] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1007.345 0.000 1007.415 0.140 ; - END - END r0_rd_out[75] - PIN r0_rd_out[76] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1010.385 0.000 1010.455 0.140 ; - END - END r0_rd_out[76] - PIN r0_rd_out[77] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1013.425 0.000 1013.495 0.140 ; - END - END r0_rd_out[77] - PIN r0_rd_out[78] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1016.465 0.000 1016.535 0.140 ; - END - END r0_rd_out[78] - PIN r0_rd_out[79] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1019.505 0.000 1019.575 0.140 ; - END - END r0_rd_out[79] - PIN r0_rd_out[80] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1022.545 0.000 1022.615 0.140 ; - END - END r0_rd_out[80] - PIN r0_rd_out[81] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1025.585 0.000 1025.655 0.140 ; - END - END r0_rd_out[81] - PIN r0_rd_out[82] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1028.625 0.000 1028.695 0.140 ; - END - END r0_rd_out[82] - PIN r0_rd_out[83] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1031.665 0.000 1031.735 0.140 ; - END - END r0_rd_out[83] - PIN r0_rd_out[84] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1034.705 0.000 1034.775 0.140 ; - END - END r0_rd_out[84] - PIN r0_rd_out[85] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1037.745 0.000 1037.815 0.140 ; - END - END r0_rd_out[85] - PIN r0_rd_out[86] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1040.785 0.000 1040.855 0.140 ; - END - END r0_rd_out[86] - PIN r0_rd_out[87] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1043.825 0.000 1043.895 0.140 ; - END - END r0_rd_out[87] - PIN r0_rd_out[88] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1046.865 0.000 1046.935 0.140 ; - END - END r0_rd_out[88] - PIN r0_rd_out[89] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1049.905 0.000 1049.975 0.140 ; - END - END r0_rd_out[89] - PIN r0_rd_out[90] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1052.945 0.000 1053.015 0.140 ; - END - END r0_rd_out[90] - PIN r0_rd_out[91] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1055.985 0.000 1056.055 0.140 ; - END - END r0_rd_out[91] - PIN r0_rd_out[92] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1059.025 0.000 1059.095 0.140 ; - END - END r0_rd_out[92] - PIN r0_rd_out[93] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1062.065 0.000 1062.135 0.140 ; - END - END r0_rd_out[93] - PIN r0_rd_out[94] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1065.105 0.000 1065.175 0.140 ; - END - END r0_rd_out[94] - PIN r0_rd_out[95] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1068.145 0.000 1068.215 0.140 ; - END - END r0_rd_out[95] - PIN r0_rd_out[96] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1071.185 0.000 1071.255 0.140 ; - END - END r0_rd_out[96] - PIN r0_rd_out[97] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1074.225 0.000 1074.295 0.140 ; - END - END r0_rd_out[97] - PIN r0_rd_out[98] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1077.265 0.000 1077.335 0.140 ; - END - END r0_rd_out[98] - PIN r0_rd_out[99] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1080.305 0.000 1080.375 0.140 ; - END - END r0_rd_out[99] - PIN r0_rd_out[100] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1083.345 0.000 1083.415 0.140 ; - END - END r0_rd_out[100] - PIN r0_rd_out[101] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1086.385 0.000 1086.455 0.140 ; - END - END r0_rd_out[101] - PIN r0_rd_out[102] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1089.425 0.000 1089.495 0.140 ; - END - END r0_rd_out[102] - PIN r0_rd_out[103] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1092.465 0.000 1092.535 0.140 ; - END - END r0_rd_out[103] - PIN r0_rd_out[104] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1095.505 0.000 1095.575 0.140 ; - END - END r0_rd_out[104] - PIN r0_rd_out[105] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1098.545 0.000 1098.615 0.140 ; - END - END r0_rd_out[105] - PIN r0_rd_out[106] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1101.585 0.000 1101.655 0.140 ; - END - END r0_rd_out[106] - PIN r0_rd_out[107] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1104.625 0.000 1104.695 0.140 ; - END - END r0_rd_out[107] - PIN r0_rd_out[108] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1107.665 0.000 1107.735 0.140 ; - END - END r0_rd_out[108] - PIN r0_rd_out[109] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1110.705 0.000 1110.775 0.140 ; - END - END r0_rd_out[109] - PIN r0_rd_out[110] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1113.745 0.000 1113.815 0.140 ; - END - END r0_rd_out[110] - PIN r0_rd_out[111] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1116.785 0.000 1116.855 0.140 ; - END - END r0_rd_out[111] - PIN r0_rd_out[112] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1119.825 0.000 1119.895 0.140 ; - END - END r0_rd_out[112] - PIN r0_rd_out[113] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1122.865 0.000 1122.935 0.140 ; - END - END r0_rd_out[113] - PIN r0_rd_out[114] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1125.905 0.000 1125.975 0.140 ; - END - END r0_rd_out[114] - PIN r0_rd_out[115] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1128.945 0.000 1129.015 0.140 ; - END - END r0_rd_out[115] - PIN r0_rd_out[116] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1131.985 0.000 1132.055 0.140 ; - END - END r0_rd_out[116] - PIN r0_rd_out[117] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1135.025 0.000 1135.095 0.140 ; - END - END r0_rd_out[117] - PIN r0_rd_out[118] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1138.065 0.000 1138.135 0.140 ; - END - END r0_rd_out[118] - PIN r0_rd_out[119] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1141.105 0.000 1141.175 0.140 ; - END - END r0_rd_out[119] - PIN r0_rd_out[120] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1144.145 0.000 1144.215 0.140 ; - END - END r0_rd_out[120] - PIN r0_rd_out[121] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1147.185 0.000 1147.255 0.140 ; - END - END r0_rd_out[121] - PIN r0_rd_out[122] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1150.225 0.000 1150.295 0.140 ; - END - END r0_rd_out[122] - PIN r0_rd_out[123] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1153.265 0.000 1153.335 0.140 ; - END - END r0_rd_out[123] - PIN r0_rd_out[124] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1156.305 0.000 1156.375 0.140 ; - END - END r0_rd_out[124] - PIN r0_rd_out[125] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1159.345 0.000 1159.415 0.140 ; - END - END r0_rd_out[125] - PIN r0_rd_out[126] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1162.385 0.000 1162.455 0.140 ; - END - END r0_rd_out[126] - PIN r0_rd_out[127] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1165.425 0.000 1165.495 0.140 ; - END - END r0_rd_out[127] - PIN r0_rd_out[128] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1168.465 0.000 1168.535 0.140 ; - END - END r0_rd_out[128] - PIN r0_rd_out[129] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1171.505 0.000 1171.575 0.140 ; - END - END r0_rd_out[129] - PIN r0_rd_out[130] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1174.545 0.000 1174.615 0.140 ; - END - END r0_rd_out[130] - PIN r0_rd_out[131] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1177.585 0.000 1177.655 0.140 ; - END - END r0_rd_out[131] - PIN r0_rd_out[132] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1180.625 0.000 1180.695 0.140 ; - END - END r0_rd_out[132] - PIN r0_rd_out[133] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1183.665 0.000 1183.735 0.140 ; - END - END r0_rd_out[133] - PIN r0_rd_out[134] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1186.705 0.000 1186.775 0.140 ; - END - END r0_rd_out[134] - PIN r0_rd_out[135] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1189.745 0.000 1189.815 0.140 ; - END - END r0_rd_out[135] - PIN r0_rd_out[136] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1192.785 0.000 1192.855 0.140 ; - END - END r0_rd_out[136] - PIN r0_rd_out[137] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1195.825 0.000 1195.895 0.140 ; - END - END r0_rd_out[137] - PIN r0_rd_out[138] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1198.865 0.000 1198.935 0.140 ; - END - END r0_rd_out[138] - PIN r0_rd_out[139] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1201.905 0.000 1201.975 0.140 ; - END - END r0_rd_out[139] - PIN r0_rd_out[140] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1204.945 0.000 1205.015 0.140 ; - END - END r0_rd_out[140] - PIN r0_rd_out[141] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1207.985 0.000 1208.055 0.140 ; - END - END r0_rd_out[141] - PIN r0_rd_out[142] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1211.025 0.000 1211.095 0.140 ; - END - END r0_rd_out[142] - PIN r0_rd_out[143] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1214.065 0.000 1214.135 0.140 ; - END - END r0_rd_out[143] - PIN r0_rd_out[144] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1217.105 0.000 1217.175 0.140 ; - END - END r0_rd_out[144] - PIN r0_rd_out[145] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1220.145 0.000 1220.215 0.140 ; - END - END r0_rd_out[145] - PIN r0_rd_out[146] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1223.185 0.000 1223.255 0.140 ; - END - END r0_rd_out[146] - PIN r0_rd_out[147] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1226.225 0.000 1226.295 0.140 ; - END - END r0_rd_out[147] - PIN r0_rd_out[148] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1229.265 0.000 1229.335 0.140 ; - END - END r0_rd_out[148] - PIN r0_rd_out[149] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1232.305 0.000 1232.375 0.140 ; - END - END r0_rd_out[149] - PIN r0_rd_out[150] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1235.345 0.000 1235.415 0.140 ; - END - END r0_rd_out[150] - PIN r0_rd_out[151] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1238.385 0.000 1238.455 0.140 ; - END - END r0_rd_out[151] - PIN r0_rd_out[152] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1241.425 0.000 1241.495 0.140 ; - END - END r0_rd_out[152] - PIN r0_rd_out[153] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1244.465 0.000 1244.535 0.140 ; - END - END r0_rd_out[153] - PIN r0_rd_out[154] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1247.505 0.000 1247.575 0.140 ; - END - END r0_rd_out[154] - PIN r0_rd_out[155] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1250.545 0.000 1250.615 0.140 ; - END - END r0_rd_out[155] - PIN r0_rd_out[156] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1253.585 0.000 1253.655 0.140 ; - END - END r0_rd_out[156] - PIN r0_rd_out[157] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1256.625 0.000 1256.695 0.140 ; - END - END r0_rd_out[157] - PIN r0_rd_out[158] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1259.665 0.000 1259.735 0.140 ; - END - END r0_rd_out[158] - PIN r0_rd_out[159] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1262.705 0.000 1262.775 0.140 ; - END - END r0_rd_out[159] - PIN r0_rd_out[160] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1265.745 0.000 1265.815 0.140 ; - END - END r0_rd_out[160] - PIN r0_rd_out[161] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1268.785 0.000 1268.855 0.140 ; - END - END r0_rd_out[161] - PIN r0_rd_out[162] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1271.825 0.000 1271.895 0.140 ; - END - END r0_rd_out[162] - PIN r0_rd_out[163] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1274.865 0.000 1274.935 0.140 ; - END - END r0_rd_out[163] - PIN r0_rd_out[164] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1277.905 0.000 1277.975 0.140 ; - END - END r0_rd_out[164] - PIN r0_rd_out[165] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1280.945 0.000 1281.015 0.140 ; - END - END r0_rd_out[165] - PIN r0_rd_out[166] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1283.985 0.000 1284.055 0.140 ; - END - END r0_rd_out[166] - PIN r0_rd_out[167] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1287.025 0.000 1287.095 0.140 ; - END - END r0_rd_out[167] - PIN r0_rd_out[168] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1290.065 0.000 1290.135 0.140 ; - END - END r0_rd_out[168] - PIN r0_rd_out[169] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1293.105 0.000 1293.175 0.140 ; - END - END r0_rd_out[169] - PIN r0_rd_out[170] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1296.145 0.000 1296.215 0.140 ; - END - END r0_rd_out[170] - PIN r0_rd_out[171] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1299.185 0.000 1299.255 0.140 ; - END - END r0_rd_out[171] - PIN r0_rd_out[172] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1302.225 0.000 1302.295 0.140 ; - END - END r0_rd_out[172] - PIN r0_rd_out[173] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1305.265 0.000 1305.335 0.140 ; - END - END r0_rd_out[173] - PIN r0_rd_out[174] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1308.305 0.000 1308.375 0.140 ; - END - END r0_rd_out[174] - PIN r0_rd_out[175] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1311.345 0.000 1311.415 0.140 ; - END - END r0_rd_out[175] - PIN r0_rd_out[176] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1314.385 0.000 1314.455 0.140 ; - END - END r0_rd_out[176] - PIN r0_rd_out[177] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1317.425 0.000 1317.495 0.140 ; - END - END r0_rd_out[177] - PIN r0_rd_out[178] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1320.465 0.000 1320.535 0.140 ; - END - END r0_rd_out[178] - PIN r0_rd_out[179] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1323.505 0.000 1323.575 0.140 ; - END - END r0_rd_out[179] - PIN r0_rd_out[180] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1326.545 0.000 1326.615 0.140 ; - END - END r0_rd_out[180] - PIN r0_rd_out[181] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1329.585 0.000 1329.655 0.140 ; - END - END r0_rd_out[181] - PIN r0_rd_out[182] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1332.625 0.000 1332.695 0.140 ; - END - END r0_rd_out[182] - PIN r0_rd_out[183] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1335.665 0.000 1335.735 0.140 ; - END - END r0_rd_out[183] - PIN r0_rd_out[184] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1338.705 0.000 1338.775 0.140 ; - END - END r0_rd_out[184] - PIN r0_rd_out[185] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1341.745 0.000 1341.815 0.140 ; - END - END r0_rd_out[185] - PIN r0_rd_out[186] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1344.785 0.000 1344.855 0.140 ; - END - END r0_rd_out[186] - PIN r0_rd_out[187] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1347.825 0.000 1347.895 0.140 ; - END - END r0_rd_out[187] - PIN r0_rd_out[188] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1350.865 0.000 1350.935 0.140 ; - END - END r0_rd_out[188] - PIN r0_rd_out[189] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1353.905 0.000 1353.975 0.140 ; - END - END r0_rd_out[189] - PIN r0_rd_out[190] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1356.945 0.000 1357.015 0.140 ; - END - END r0_rd_out[190] - PIN r0_rd_out[191] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1359.985 0.000 1360.055 0.140 ; - END - END r0_rd_out[191] - PIN r0_rd_out[192] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1363.025 0.000 1363.095 0.140 ; - END - END r0_rd_out[192] - PIN r0_rd_out[193] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1366.065 0.000 1366.135 0.140 ; - END - END r0_rd_out[193] - PIN r0_rd_out[194] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1369.105 0.000 1369.175 0.140 ; - END - END r0_rd_out[194] - PIN r0_rd_out[195] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1372.145 0.000 1372.215 0.140 ; - END - END r0_rd_out[195] - PIN r0_rd_out[196] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1375.185 0.000 1375.255 0.140 ; - END - END r0_rd_out[196] - PIN r0_rd_out[197] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1378.225 0.000 1378.295 0.140 ; - END - END r0_rd_out[197] - PIN r0_rd_out[198] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1381.265 0.000 1381.335 0.140 ; - END - END r0_rd_out[198] - PIN r0_rd_out[199] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1384.305 0.000 1384.375 0.140 ; - END - END r0_rd_out[199] - PIN r0_rd_out[200] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1387.345 0.000 1387.415 0.140 ; - END - END r0_rd_out[200] - PIN r0_rd_out[201] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1390.385 0.000 1390.455 0.140 ; - END - END r0_rd_out[201] - PIN r0_rd_out[202] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1393.425 0.000 1393.495 0.140 ; - END - END r0_rd_out[202] - PIN r0_rd_out[203] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1396.465 0.000 1396.535 0.140 ; - END - END r0_rd_out[203] - PIN r0_rd_out[204] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1399.505 0.000 1399.575 0.140 ; - END - END r0_rd_out[204] - PIN r0_rd_out[205] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1402.545 0.000 1402.615 0.140 ; - END - END r0_rd_out[205] - PIN r0_rd_out[206] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1405.585 0.000 1405.655 0.140 ; - END - END r0_rd_out[206] - PIN r0_rd_out[207] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1408.625 0.000 1408.695 0.140 ; - END - END r0_rd_out[207] - PIN r0_rd_out[208] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1411.665 0.000 1411.735 0.140 ; - END - END r0_rd_out[208] - PIN r0_rd_out[209] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1414.705 0.000 1414.775 0.140 ; - END - END r0_rd_out[209] - PIN r0_rd_out[210] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1417.745 0.000 1417.815 0.140 ; - END - END r0_rd_out[210] - PIN r0_rd_out[211] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1420.785 0.000 1420.855 0.140 ; - END - END r0_rd_out[211] - PIN r0_rd_out[212] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1423.825 0.000 1423.895 0.140 ; - END - END r0_rd_out[212] - PIN r0_rd_out[213] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1426.865 0.000 1426.935 0.140 ; - END - END r0_rd_out[213] - PIN r0_rd_out[214] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1429.905 0.000 1429.975 0.140 ; - END - END r0_rd_out[214] - PIN r0_rd_out[215] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1432.945 0.000 1433.015 0.140 ; - END - END r0_rd_out[215] - PIN r0_rd_out[216] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1435.985 0.000 1436.055 0.140 ; - END - END r0_rd_out[216] - PIN r0_rd_out[217] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1439.025 0.000 1439.095 0.140 ; - END - END r0_rd_out[217] - PIN r0_rd_out[218] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1442.065 0.000 1442.135 0.140 ; - END - END r0_rd_out[218] - PIN r0_rd_out[219] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1445.105 0.000 1445.175 0.140 ; - END - END r0_rd_out[219] - PIN r0_rd_out[220] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1448.145 0.000 1448.215 0.140 ; - END - END r0_rd_out[220] - PIN r0_rd_out[221] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1451.185 0.000 1451.255 0.140 ; - END - END r0_rd_out[221] - PIN r0_rd_out[222] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1454.225 0.000 1454.295 0.140 ; - END - END r0_rd_out[222] - PIN r0_rd_out[223] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1457.265 0.000 1457.335 0.140 ; - END - END r0_rd_out[223] - PIN r0_rd_out[224] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1460.305 0.000 1460.375 0.140 ; - END - END r0_rd_out[224] - PIN r0_rd_out[225] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1463.345 0.000 1463.415 0.140 ; - END - END r0_rd_out[225] - PIN r0_rd_out[226] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1466.385 0.000 1466.455 0.140 ; - END - END r0_rd_out[226] - PIN r0_rd_out[227] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1469.425 0.000 1469.495 0.140 ; - END - END r0_rd_out[227] - PIN r0_rd_out[228] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1472.465 0.000 1472.535 0.140 ; - END - END r0_rd_out[228] - PIN r0_rd_out[229] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1475.505 0.000 1475.575 0.140 ; - END - END r0_rd_out[229] - PIN r0_rd_out[230] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1478.545 0.000 1478.615 0.140 ; - END - END r0_rd_out[230] - PIN r0_rd_out[231] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1481.585 0.000 1481.655 0.140 ; - END - END r0_rd_out[231] - PIN r0_rd_out[232] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1484.625 0.000 1484.695 0.140 ; - END - END r0_rd_out[232] - PIN r0_rd_out[233] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1487.665 0.000 1487.735 0.140 ; - END - END r0_rd_out[233] - PIN r0_rd_out[234] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1490.705 0.000 1490.775 0.140 ; - END - END r0_rd_out[234] - PIN r0_rd_out[235] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1493.745 0.000 1493.815 0.140 ; - END - END r0_rd_out[235] - PIN r0_rd_out[236] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1496.785 0.000 1496.855 0.140 ; - END - END r0_rd_out[236] - PIN r0_rd_out[237] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1499.825 0.000 1499.895 0.140 ; - END - END r0_rd_out[237] - PIN r0_rd_out[238] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1502.865 0.000 1502.935 0.140 ; - END - END r0_rd_out[238] - PIN r0_rd_out[239] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1505.905 0.000 1505.975 0.140 ; - END - END r0_rd_out[239] - PIN r0_rd_out[240] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1508.945 0.000 1509.015 0.140 ; - END - END r0_rd_out[240] - PIN r0_rd_out[241] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1511.985 0.000 1512.055 0.140 ; - END - END r0_rd_out[241] - PIN r0_rd_out[242] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1515.025 0.000 1515.095 0.140 ; - END - END r0_rd_out[242] - PIN r0_rd_out[243] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1518.065 0.000 1518.135 0.140 ; - END - END r0_rd_out[243] - PIN r0_rd_out[244] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1521.105 0.000 1521.175 0.140 ; - END - END r0_rd_out[244] - PIN r0_rd_out[245] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1524.145 0.000 1524.215 0.140 ; - END - END r0_rd_out[245] - PIN r0_rd_out[246] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1527.185 0.000 1527.255 0.140 ; - END - END r0_rd_out[246] - PIN r0_rd_out[247] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1530.225 0.000 1530.295 0.140 ; - END - END r0_rd_out[247] - PIN r0_rd_out[248] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1533.265 0.000 1533.335 0.140 ; - END - END r0_rd_out[248] - PIN r0_rd_out[249] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1536.305 0.000 1536.375 0.140 ; - END - END r0_rd_out[249] - PIN r0_rd_out[250] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1539.345 0.000 1539.415 0.140 ; - END - END r0_rd_out[250] - PIN r0_rd_out[251] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1542.385 0.000 1542.455 0.140 ; - END - END r0_rd_out[251] - PIN r0_rd_out[252] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1545.425 0.000 1545.495 0.140 ; - END - END r0_rd_out[252] - PIN r0_rd_out[253] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1548.465 0.000 1548.535 0.140 ; - END - END r0_rd_out[253] - PIN r0_rd_out[254] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1551.505 0.000 1551.575 0.140 ; - END - END r0_rd_out[254] - PIN r0_rd_out[255] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1554.545 0.000 1554.615 0.140 ; - END - END r0_rd_out[255] - PIN r0_rd_out[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 1511.860 1.175 1512.000 ; - END - END r0_rd_out[256] - PIN r0_rd_out[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 7.185 1511.860 7.255 1512.000 ; - END - END r0_rd_out[257] - PIN r0_rd_out[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 13.265 1511.860 13.335 1512.000 ; - END - END r0_rd_out[258] - PIN r0_rd_out[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 19.345 1511.860 19.415 1512.000 ; - END - END r0_rd_out[259] - PIN r0_rd_out[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.425 1511.860 25.495 1512.000 ; - END - END r0_rd_out[260] - PIN r0_rd_out[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.505 1511.860 31.575 1512.000 ; - END - END r0_rd_out[261] - PIN r0_rd_out[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.585 1511.860 37.655 1512.000 ; - END - END r0_rd_out[262] - PIN r0_rd_out[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.665 1511.860 43.735 1512.000 ; - END - END r0_rd_out[263] - PIN r0_rd_out[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 49.745 1511.860 49.815 1512.000 ; - END - END r0_rd_out[264] - PIN r0_rd_out[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.825 1511.860 55.895 1512.000 ; - END - END r0_rd_out[265] - PIN r0_rd_out[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 61.905 1511.860 61.975 1512.000 ; - END - END r0_rd_out[266] - PIN r0_rd_out[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.985 1511.860 68.055 1512.000 ; - END - END r0_rd_out[267] - PIN r0_rd_out[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 74.065 1511.860 74.135 1512.000 ; - END - END r0_rd_out[268] - PIN r0_rd_out[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.145 1511.860 80.215 1512.000 ; - END - END r0_rd_out[269] - PIN r0_rd_out[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.225 1511.860 86.295 1512.000 ; - END - END r0_rd_out[270] - PIN r0_rd_out[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 92.305 1511.860 92.375 1512.000 ; - END - END r0_rd_out[271] - PIN r0_rd_out[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 98.385 1511.860 98.455 1512.000 ; - END - END r0_rd_out[272] - PIN r0_rd_out[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 104.465 1511.860 104.535 1512.000 ; - END - END r0_rd_out[273] - PIN r0_rd_out[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 110.545 1511.860 110.615 1512.000 ; - END - END r0_rd_out[274] - PIN r0_rd_out[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 116.625 1511.860 116.695 1512.000 ; - END - END r0_rd_out[275] - PIN r0_rd_out[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 122.705 1511.860 122.775 1512.000 ; - END - END r0_rd_out[276] - PIN r0_rd_out[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 128.785 1511.860 128.855 1512.000 ; - END - END r0_rd_out[277] - PIN r0_rd_out[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 134.865 1511.860 134.935 1512.000 ; - END - END r0_rd_out[278] - PIN r0_rd_out[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 140.945 1511.860 141.015 1512.000 ; - END - END r0_rd_out[279] - PIN r0_rd_out[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 147.025 1511.860 147.095 1512.000 ; - END - END r0_rd_out[280] - PIN r0_rd_out[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 153.105 1511.860 153.175 1512.000 ; - END - END r0_rd_out[281] - PIN r0_rd_out[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 159.185 1511.860 159.255 1512.000 ; - END - END r0_rd_out[282] - PIN r0_rd_out[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 165.265 1511.860 165.335 1512.000 ; - END - END r0_rd_out[283] - PIN r0_rd_out[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 171.345 1511.860 171.415 1512.000 ; - END - END r0_rd_out[284] - PIN r0_rd_out[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 177.425 1511.860 177.495 1512.000 ; - END - END r0_rd_out[285] - PIN r0_rd_out[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 183.505 1511.860 183.575 1512.000 ; - END - END r0_rd_out[286] - PIN r0_rd_out[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 189.585 1511.860 189.655 1512.000 ; - END - END r0_rd_out[287] - PIN r0_rd_out[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 195.665 1511.860 195.735 1512.000 ; - END - END r0_rd_out[288] - PIN r0_rd_out[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 201.745 1511.860 201.815 1512.000 ; - END - END r0_rd_out[289] - PIN r0_rd_out[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 207.825 1511.860 207.895 1512.000 ; - END - END r0_rd_out[290] - PIN r0_rd_out[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 213.905 1511.860 213.975 1512.000 ; - END - END r0_rd_out[291] - PIN r0_rd_out[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 219.985 1511.860 220.055 1512.000 ; - END - END r0_rd_out[292] - PIN r0_rd_out[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 226.065 1511.860 226.135 1512.000 ; - END - END r0_rd_out[293] - PIN r0_rd_out[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 232.145 1511.860 232.215 1512.000 ; - END - END r0_rd_out[294] - PIN r0_rd_out[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 238.225 1511.860 238.295 1512.000 ; - END - END r0_rd_out[295] - PIN r0_rd_out[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 244.305 1511.860 244.375 1512.000 ; - END - END r0_rd_out[296] - PIN r0_rd_out[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 250.385 1511.860 250.455 1512.000 ; - END - END r0_rd_out[297] - PIN r0_rd_out[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 256.465 1511.860 256.535 1512.000 ; - END - END r0_rd_out[298] - PIN r0_rd_out[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 262.545 1511.860 262.615 1512.000 ; - END - END r0_rd_out[299] - PIN r0_rd_out[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 268.625 1511.860 268.695 1512.000 ; - END - END r0_rd_out[300] - PIN r0_rd_out[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 274.705 1511.860 274.775 1512.000 ; - END - END r0_rd_out[301] - PIN r0_rd_out[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 280.785 1511.860 280.855 1512.000 ; - END - END r0_rd_out[302] - PIN r0_rd_out[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 286.865 1511.860 286.935 1512.000 ; - END - END r0_rd_out[303] - PIN r0_rd_out[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 292.945 1511.860 293.015 1512.000 ; - END - END r0_rd_out[304] - PIN r0_rd_out[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 299.025 1511.860 299.095 1512.000 ; - END - END r0_rd_out[305] - PIN r0_rd_out[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 305.105 1511.860 305.175 1512.000 ; - END - END r0_rd_out[306] - PIN r0_rd_out[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 311.185 1511.860 311.255 1512.000 ; - END - END r0_rd_out[307] - PIN r0_rd_out[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 317.265 1511.860 317.335 1512.000 ; - END - END r0_rd_out[308] - PIN r0_rd_out[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 323.345 1511.860 323.415 1512.000 ; - END - END r0_rd_out[309] - PIN r0_rd_out[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 329.425 1511.860 329.495 1512.000 ; - END - END r0_rd_out[310] - PIN r0_rd_out[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 335.505 1511.860 335.575 1512.000 ; - END - END r0_rd_out[311] - PIN r0_rd_out[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 341.585 1511.860 341.655 1512.000 ; - END - END r0_rd_out[312] - PIN r0_rd_out[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 347.665 1511.860 347.735 1512.000 ; - END - END r0_rd_out[313] - PIN r0_rd_out[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 353.745 1511.860 353.815 1512.000 ; - END - END r0_rd_out[314] - PIN r0_rd_out[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 359.825 1511.860 359.895 1512.000 ; - END - END r0_rd_out[315] - PIN r0_rd_out[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 365.905 1511.860 365.975 1512.000 ; - END - END r0_rd_out[316] - PIN r0_rd_out[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 371.985 1511.860 372.055 1512.000 ; - END - END r0_rd_out[317] - PIN r0_rd_out[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 378.065 1511.860 378.135 1512.000 ; - END - END r0_rd_out[318] - PIN r0_rd_out[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 384.145 1511.860 384.215 1512.000 ; - END - END r0_rd_out[319] - PIN r0_rd_out[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 390.225 1511.860 390.295 1512.000 ; - END - END r0_rd_out[320] - PIN r0_rd_out[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 396.305 1511.860 396.375 1512.000 ; - END - END r0_rd_out[321] - PIN r0_rd_out[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 402.385 1511.860 402.455 1512.000 ; - END - END r0_rd_out[322] - PIN r0_rd_out[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 408.465 1511.860 408.535 1512.000 ; - END - END r0_rd_out[323] - PIN r0_rd_out[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 414.545 1511.860 414.615 1512.000 ; - END - END r0_rd_out[324] - PIN r0_rd_out[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 420.625 1511.860 420.695 1512.000 ; - END - END r0_rd_out[325] - PIN r0_rd_out[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 426.705 1511.860 426.775 1512.000 ; - END - END r0_rd_out[326] - PIN r0_rd_out[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 432.785 1511.860 432.855 1512.000 ; - END - END r0_rd_out[327] - PIN r0_rd_out[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 438.865 1511.860 438.935 1512.000 ; - END - END r0_rd_out[328] - PIN r0_rd_out[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 444.945 1511.860 445.015 1512.000 ; - END - END r0_rd_out[329] - PIN r0_rd_out[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 451.025 1511.860 451.095 1512.000 ; - END - END r0_rd_out[330] - PIN r0_rd_out[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 457.105 1511.860 457.175 1512.000 ; - END - END r0_rd_out[331] - PIN r0_rd_out[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 463.185 1511.860 463.255 1512.000 ; - END - END r0_rd_out[332] - PIN r0_rd_out[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 469.265 1511.860 469.335 1512.000 ; - END - END r0_rd_out[333] - PIN r0_rd_out[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 475.345 1511.860 475.415 1512.000 ; - END - END r0_rd_out[334] - PIN r0_rd_out[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 481.425 1511.860 481.495 1512.000 ; - END - END r0_rd_out[335] - PIN r0_rd_out[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 487.505 1511.860 487.575 1512.000 ; - END - END r0_rd_out[336] - PIN r0_rd_out[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 493.585 1511.860 493.655 1512.000 ; - END - END r0_rd_out[337] - PIN r0_rd_out[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 499.665 1511.860 499.735 1512.000 ; - END - END r0_rd_out[338] - PIN r0_rd_out[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 505.745 1511.860 505.815 1512.000 ; - END - END r0_rd_out[339] - PIN r0_rd_out[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 511.825 1511.860 511.895 1512.000 ; - END - END r0_rd_out[340] - PIN r0_rd_out[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 517.905 1511.860 517.975 1512.000 ; - END - END r0_rd_out[341] - PIN r0_rd_out[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 523.985 1511.860 524.055 1512.000 ; - END - END r0_rd_out[342] - PIN r0_rd_out[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 530.065 1511.860 530.135 1512.000 ; - END - END r0_rd_out[343] - PIN r0_rd_out[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 536.145 1511.860 536.215 1512.000 ; - END - END r0_rd_out[344] - PIN r0_rd_out[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 542.225 1511.860 542.295 1512.000 ; - END - END r0_rd_out[345] - PIN r0_rd_out[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 548.305 1511.860 548.375 1512.000 ; - END - END r0_rd_out[346] - PIN r0_rd_out[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 554.385 1511.860 554.455 1512.000 ; - END - END r0_rd_out[347] - PIN r0_rd_out[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 560.465 1511.860 560.535 1512.000 ; - END - END r0_rd_out[348] - PIN r0_rd_out[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 566.545 1511.860 566.615 1512.000 ; - END - END r0_rd_out[349] - PIN r0_rd_out[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 572.625 1511.860 572.695 1512.000 ; - END - END r0_rd_out[350] - PIN r0_rd_out[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 578.705 1511.860 578.775 1512.000 ; - END - END r0_rd_out[351] - PIN r0_rd_out[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 584.785 1511.860 584.855 1512.000 ; - END - END r0_rd_out[352] - PIN r0_rd_out[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 590.865 1511.860 590.935 1512.000 ; - END - END r0_rd_out[353] - PIN r0_rd_out[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 596.945 1511.860 597.015 1512.000 ; - END - END r0_rd_out[354] - PIN r0_rd_out[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 603.025 1511.860 603.095 1512.000 ; - END - END r0_rd_out[355] - PIN r0_rd_out[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 609.105 1511.860 609.175 1512.000 ; - END - END r0_rd_out[356] - PIN r0_rd_out[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 615.185 1511.860 615.255 1512.000 ; - END - END r0_rd_out[357] - PIN r0_rd_out[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 621.265 1511.860 621.335 1512.000 ; - END - END r0_rd_out[358] - PIN r0_rd_out[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 627.345 1511.860 627.415 1512.000 ; - END - END r0_rd_out[359] - PIN r0_rd_out[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 633.425 1511.860 633.495 1512.000 ; - END - END r0_rd_out[360] - PIN r0_rd_out[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 639.505 1511.860 639.575 1512.000 ; - END - END r0_rd_out[361] - PIN r0_rd_out[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 645.585 1511.860 645.655 1512.000 ; - END - END r0_rd_out[362] - PIN r0_rd_out[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 651.665 1511.860 651.735 1512.000 ; - END - END r0_rd_out[363] - PIN r0_rd_out[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 657.745 1511.860 657.815 1512.000 ; - END - END r0_rd_out[364] - PIN r0_rd_out[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 663.825 1511.860 663.895 1512.000 ; - END - END r0_rd_out[365] - PIN r0_rd_out[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 669.905 1511.860 669.975 1512.000 ; - END - END r0_rd_out[366] - PIN r0_rd_out[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 675.985 1511.860 676.055 1512.000 ; - END - END r0_rd_out[367] - PIN r0_rd_out[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 682.065 1511.860 682.135 1512.000 ; - END - END r0_rd_out[368] - PIN r0_rd_out[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 688.145 1511.860 688.215 1512.000 ; - END - END r0_rd_out[369] - PIN r0_rd_out[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 694.225 1511.860 694.295 1512.000 ; - END - END r0_rd_out[370] - PIN r0_rd_out[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 700.305 1511.860 700.375 1512.000 ; - END - END r0_rd_out[371] - PIN r0_rd_out[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 706.385 1511.860 706.455 1512.000 ; - END - END r0_rd_out[372] - PIN r0_rd_out[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 712.465 1511.860 712.535 1512.000 ; - END - END r0_rd_out[373] - PIN r0_rd_out[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 718.545 1511.860 718.615 1512.000 ; - END - END r0_rd_out[374] - PIN r0_rd_out[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 724.625 1511.860 724.695 1512.000 ; - END - END r0_rd_out[375] - PIN r0_rd_out[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 730.705 1511.860 730.775 1512.000 ; - END - END r0_rd_out[376] - PIN r0_rd_out[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 736.785 1511.860 736.855 1512.000 ; - END - END r0_rd_out[377] - PIN r0_rd_out[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 742.865 1511.860 742.935 1512.000 ; - END - END r0_rd_out[378] - PIN r0_rd_out[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 748.945 1511.860 749.015 1512.000 ; - END - END r0_rd_out[379] - PIN r0_rd_out[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 755.025 1511.860 755.095 1512.000 ; - END - END r0_rd_out[380] - PIN r0_rd_out[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 761.105 1511.860 761.175 1512.000 ; - END - END r0_rd_out[381] - PIN r0_rd_out[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 767.185 1511.860 767.255 1512.000 ; - END - END r0_rd_out[382] - PIN r0_rd_out[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 773.265 1511.860 773.335 1512.000 ; - END - END r0_rd_out[383] - PIN r0_rd_out[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 779.345 1511.860 779.415 1512.000 ; - END - END r0_rd_out[384] - PIN r0_rd_out[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 785.425 1511.860 785.495 1512.000 ; - END - END r0_rd_out[385] - PIN r0_rd_out[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 791.505 1511.860 791.575 1512.000 ; - END - END r0_rd_out[386] - PIN r0_rd_out[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 797.585 1511.860 797.655 1512.000 ; - END - END r0_rd_out[387] - PIN r0_rd_out[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 803.665 1511.860 803.735 1512.000 ; - END - END r0_rd_out[388] - PIN r0_rd_out[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 809.745 1511.860 809.815 1512.000 ; - END - END r0_rd_out[389] - PIN r0_rd_out[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 815.825 1511.860 815.895 1512.000 ; - END - END r0_rd_out[390] - PIN r0_rd_out[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 821.905 1511.860 821.975 1512.000 ; - END - END r0_rd_out[391] - PIN r0_rd_out[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 827.985 1511.860 828.055 1512.000 ; - END - END r0_rd_out[392] - PIN r0_rd_out[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 834.065 1511.860 834.135 1512.000 ; - END - END r0_rd_out[393] - PIN r0_rd_out[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 840.145 1511.860 840.215 1512.000 ; - END - END r0_rd_out[394] - PIN r0_rd_out[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 846.225 1511.860 846.295 1512.000 ; - END - END r0_rd_out[395] - PIN r0_rd_out[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 852.305 1511.860 852.375 1512.000 ; - END - END r0_rd_out[396] - PIN r0_rd_out[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 858.385 1511.860 858.455 1512.000 ; - END - END r0_rd_out[397] - PIN r0_rd_out[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 864.465 1511.860 864.535 1512.000 ; - END - END r0_rd_out[398] - PIN r0_rd_out[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 870.545 1511.860 870.615 1512.000 ; - END - END r0_rd_out[399] - PIN r0_rd_out[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 876.625 1511.860 876.695 1512.000 ; - END - END r0_rd_out[400] - PIN r0_rd_out[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 882.705 1511.860 882.775 1512.000 ; - END - END r0_rd_out[401] - PIN r0_rd_out[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 888.785 1511.860 888.855 1512.000 ; - END - END r0_rd_out[402] - PIN r0_rd_out[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 894.865 1511.860 894.935 1512.000 ; - END - END r0_rd_out[403] - PIN r0_rd_out[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 900.945 1511.860 901.015 1512.000 ; - END - END r0_rd_out[404] - PIN r0_rd_out[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 907.025 1511.860 907.095 1512.000 ; - END - END r0_rd_out[405] - PIN r0_rd_out[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 913.105 1511.860 913.175 1512.000 ; - END - END r0_rd_out[406] - PIN r0_rd_out[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 919.185 1511.860 919.255 1512.000 ; - END - END r0_rd_out[407] - PIN r0_rd_out[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 925.265 1511.860 925.335 1512.000 ; - END - END r0_rd_out[408] - PIN r0_rd_out[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 931.345 1511.860 931.415 1512.000 ; - END - END r0_rd_out[409] - PIN r0_rd_out[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 937.425 1511.860 937.495 1512.000 ; - END - END r0_rd_out[410] - PIN r0_rd_out[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 943.505 1511.860 943.575 1512.000 ; - END - END r0_rd_out[411] - PIN r0_rd_out[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 949.585 1511.860 949.655 1512.000 ; - END - END r0_rd_out[412] - PIN r0_rd_out[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 955.665 1511.860 955.735 1512.000 ; - END - END r0_rd_out[413] - PIN r0_rd_out[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 961.745 1511.860 961.815 1512.000 ; - END - END r0_rd_out[414] - PIN r0_rd_out[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 967.825 1511.860 967.895 1512.000 ; - END - END r0_rd_out[415] - PIN r0_rd_out[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 973.905 1511.860 973.975 1512.000 ; - END - END r0_rd_out[416] - PIN r0_rd_out[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 979.985 1511.860 980.055 1512.000 ; - END - END r0_rd_out[417] - PIN r0_rd_out[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 986.065 1511.860 986.135 1512.000 ; - END - END r0_rd_out[418] - PIN r0_rd_out[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 992.145 1511.860 992.215 1512.000 ; - END - END r0_rd_out[419] - PIN r0_rd_out[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 998.225 1511.860 998.295 1512.000 ; - END - END r0_rd_out[420] - PIN r0_rd_out[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1004.305 1511.860 1004.375 1512.000 ; - END - END r0_rd_out[421] - PIN r0_rd_out[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1010.385 1511.860 1010.455 1512.000 ; - END - END r0_rd_out[422] - PIN r0_rd_out[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1016.465 1511.860 1016.535 1512.000 ; - END - END r0_rd_out[423] - PIN r0_rd_out[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1022.545 1511.860 1022.615 1512.000 ; - END - END r0_rd_out[424] - PIN r0_rd_out[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1028.625 1511.860 1028.695 1512.000 ; - END - END r0_rd_out[425] - PIN r0_rd_out[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1034.705 1511.860 1034.775 1512.000 ; - END - END r0_rd_out[426] - PIN r0_rd_out[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1040.785 1511.860 1040.855 1512.000 ; - END - END r0_rd_out[427] - PIN r0_rd_out[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1046.865 1511.860 1046.935 1512.000 ; - END - END r0_rd_out[428] - PIN r0_rd_out[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1052.945 1511.860 1053.015 1512.000 ; - END - END r0_rd_out[429] - PIN r0_rd_out[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1059.025 1511.860 1059.095 1512.000 ; - END - END r0_rd_out[430] - PIN r0_rd_out[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1065.105 1511.860 1065.175 1512.000 ; - END - END r0_rd_out[431] - PIN r0_rd_out[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1071.185 1511.860 1071.255 1512.000 ; - END - END r0_rd_out[432] - PIN r0_rd_out[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1077.265 1511.860 1077.335 1512.000 ; - END - END r0_rd_out[433] - PIN r0_rd_out[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1083.345 1511.860 1083.415 1512.000 ; - END - END r0_rd_out[434] - PIN r0_rd_out[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1089.425 1511.860 1089.495 1512.000 ; - END - END r0_rd_out[435] - PIN r0_rd_out[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1095.505 1511.860 1095.575 1512.000 ; - END - END r0_rd_out[436] - PIN r0_rd_out[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1101.585 1511.860 1101.655 1512.000 ; - END - END r0_rd_out[437] - PIN r0_rd_out[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1107.665 1511.860 1107.735 1512.000 ; - END - END r0_rd_out[438] - PIN r0_rd_out[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1113.745 1511.860 1113.815 1512.000 ; - END - END r0_rd_out[439] - PIN r0_rd_out[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1119.825 1511.860 1119.895 1512.000 ; - END - END r0_rd_out[440] - PIN r0_rd_out[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1125.905 1511.860 1125.975 1512.000 ; - END - END r0_rd_out[441] - PIN r0_rd_out[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1131.985 1511.860 1132.055 1512.000 ; - END - END r0_rd_out[442] - PIN r0_rd_out[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1138.065 1511.860 1138.135 1512.000 ; - END - END r0_rd_out[443] - PIN r0_rd_out[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1144.145 1511.860 1144.215 1512.000 ; - END - END r0_rd_out[444] - PIN r0_rd_out[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1150.225 1511.860 1150.295 1512.000 ; - END - END r0_rd_out[445] - PIN r0_rd_out[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1156.305 1511.860 1156.375 1512.000 ; - END - END r0_rd_out[446] - PIN r0_rd_out[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1162.385 1511.860 1162.455 1512.000 ; - END - END r0_rd_out[447] - PIN r0_rd_out[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1168.465 1511.860 1168.535 1512.000 ; - END - END r0_rd_out[448] - PIN r0_rd_out[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1174.545 1511.860 1174.615 1512.000 ; - END - END r0_rd_out[449] - PIN r0_rd_out[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1180.625 1511.860 1180.695 1512.000 ; - END - END r0_rd_out[450] - PIN r0_rd_out[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1186.705 1511.860 1186.775 1512.000 ; - END - END r0_rd_out[451] - PIN r0_rd_out[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1192.785 1511.860 1192.855 1512.000 ; - END - END r0_rd_out[452] - PIN r0_rd_out[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1198.865 1511.860 1198.935 1512.000 ; - END - END r0_rd_out[453] - PIN r0_rd_out[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1204.945 1511.860 1205.015 1512.000 ; - END - END r0_rd_out[454] - PIN r0_rd_out[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1211.025 1511.860 1211.095 1512.000 ; - END - END r0_rd_out[455] - PIN r0_rd_out[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1217.105 1511.860 1217.175 1512.000 ; - END - END r0_rd_out[456] - PIN r0_rd_out[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1223.185 1511.860 1223.255 1512.000 ; - END - END r0_rd_out[457] - PIN r0_rd_out[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1229.265 1511.860 1229.335 1512.000 ; - END - END r0_rd_out[458] - PIN r0_rd_out[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1235.345 1511.860 1235.415 1512.000 ; - END - END r0_rd_out[459] - PIN r0_rd_out[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1241.425 1511.860 1241.495 1512.000 ; - END - END r0_rd_out[460] - PIN r0_rd_out[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1247.505 1511.860 1247.575 1512.000 ; - END - END r0_rd_out[461] - PIN r0_rd_out[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1253.585 1511.860 1253.655 1512.000 ; - END - END r0_rd_out[462] - PIN r0_rd_out[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1259.665 1511.860 1259.735 1512.000 ; - END - END r0_rd_out[463] - PIN r0_rd_out[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1265.745 1511.860 1265.815 1512.000 ; - END - END r0_rd_out[464] - PIN r0_rd_out[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1271.825 1511.860 1271.895 1512.000 ; - END - END r0_rd_out[465] - PIN r0_rd_out[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1277.905 1511.860 1277.975 1512.000 ; - END - END r0_rd_out[466] - PIN r0_rd_out[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1283.985 1511.860 1284.055 1512.000 ; - END - END r0_rd_out[467] - PIN r0_rd_out[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1290.065 1511.860 1290.135 1512.000 ; - END - END r0_rd_out[468] - PIN r0_rd_out[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1296.145 1511.860 1296.215 1512.000 ; - END - END r0_rd_out[469] - PIN r0_rd_out[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1302.225 1511.860 1302.295 1512.000 ; - END - END r0_rd_out[470] - PIN r0_rd_out[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1308.305 1511.860 1308.375 1512.000 ; - END - END r0_rd_out[471] - PIN r0_rd_out[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1314.385 1511.860 1314.455 1512.000 ; - END - END r0_rd_out[472] - PIN r0_rd_out[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1320.465 1511.860 1320.535 1512.000 ; - END - END r0_rd_out[473] - PIN r0_rd_out[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1326.545 1511.860 1326.615 1512.000 ; - END - END r0_rd_out[474] - PIN r0_rd_out[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1332.625 1511.860 1332.695 1512.000 ; - END - END r0_rd_out[475] - PIN r0_rd_out[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1338.705 1511.860 1338.775 1512.000 ; - END - END r0_rd_out[476] - PIN r0_rd_out[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1344.785 1511.860 1344.855 1512.000 ; - END - END r0_rd_out[477] - PIN r0_rd_out[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1350.865 1511.860 1350.935 1512.000 ; - END - END r0_rd_out[478] - PIN r0_rd_out[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1356.945 1511.860 1357.015 1512.000 ; - END - END r0_rd_out[479] - PIN r0_rd_out[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1363.025 1511.860 1363.095 1512.000 ; - END - END r0_rd_out[480] - PIN r0_rd_out[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1369.105 1511.860 1369.175 1512.000 ; - END - END r0_rd_out[481] - PIN r0_rd_out[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1375.185 1511.860 1375.255 1512.000 ; - END - END r0_rd_out[482] - PIN r0_rd_out[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1381.265 1511.860 1381.335 1512.000 ; - END - END r0_rd_out[483] - PIN r0_rd_out[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1387.345 1511.860 1387.415 1512.000 ; - END - END r0_rd_out[484] - PIN r0_rd_out[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1393.425 1511.860 1393.495 1512.000 ; - END - END r0_rd_out[485] - PIN r0_rd_out[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1399.505 1511.860 1399.575 1512.000 ; - END - END r0_rd_out[486] - PIN r0_rd_out[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1405.585 1511.860 1405.655 1512.000 ; - END - END r0_rd_out[487] - PIN r0_rd_out[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1411.665 1511.860 1411.735 1512.000 ; - END - END r0_rd_out[488] - PIN r0_rd_out[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1417.745 1511.860 1417.815 1512.000 ; - END - END r0_rd_out[489] - PIN r0_rd_out[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1423.825 1511.860 1423.895 1512.000 ; - END - END r0_rd_out[490] - PIN r0_rd_out[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1429.905 1511.860 1429.975 1512.000 ; - END - END r0_rd_out[491] - PIN r0_rd_out[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1435.985 1511.860 1436.055 1512.000 ; - END - END r0_rd_out[492] - PIN r0_rd_out[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1442.065 1511.860 1442.135 1512.000 ; - END - END r0_rd_out[493] - PIN r0_rd_out[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1448.145 1511.860 1448.215 1512.000 ; - END - END r0_rd_out[494] - PIN r0_rd_out[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1454.225 1511.860 1454.295 1512.000 ; - END - END r0_rd_out[495] - PIN r0_rd_out[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1460.305 1511.860 1460.375 1512.000 ; - END - END r0_rd_out[496] - PIN r0_rd_out[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1466.385 1511.860 1466.455 1512.000 ; - END - END r0_rd_out[497] - PIN r0_rd_out[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1472.465 1511.860 1472.535 1512.000 ; - END - END r0_rd_out[498] - PIN r0_rd_out[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1478.545 1511.860 1478.615 1512.000 ; - END - END r0_rd_out[499] - PIN r0_rd_out[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1484.625 1511.860 1484.695 1512.000 ; - END - END r0_rd_out[500] - PIN r0_rd_out[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1490.705 1511.860 1490.775 1512.000 ; - END - END r0_rd_out[501] - PIN r0_rd_out[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1496.785 1511.860 1496.855 1512.000 ; - END - END r0_rd_out[502] - PIN r0_rd_out[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1502.865 1511.860 1502.935 1512.000 ; - END - END r0_rd_out[503] - PIN r0_rd_out[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1508.945 1511.860 1509.015 1512.000 ; - END - END r0_rd_out[504] - PIN r0_rd_out[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1515.025 1511.860 1515.095 1512.000 ; - END - END r0_rd_out[505] - PIN r0_rd_out[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1521.105 1511.860 1521.175 1512.000 ; - END - END r0_rd_out[506] - PIN r0_rd_out[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1527.185 1511.860 1527.255 1512.000 ; - END - END r0_rd_out[507] - PIN r0_rd_out[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1533.265 1511.860 1533.335 1512.000 ; - END - END r0_rd_out[508] - PIN r0_rd_out[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1539.345 1511.860 1539.415 1512.000 ; - END - END r0_rd_out[509] - PIN r0_rd_out[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1545.425 1511.860 1545.495 1512.000 ; - END - END r0_rd_out[510] - PIN r0_rd_out[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1551.505 1511.860 1551.575 1512.000 ; - END - END r0_rd_out[511] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1380.645 0.140 1380.715 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1391.425 0.140 1391.495 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1402.205 0.140 1402.275 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1412.985 0.140 1413.055 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1423.765 0.140 1423.835 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1434.545 0.140 1434.615 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1380.645 1609.300 1380.715 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1391.425 1609.300 1391.495 ; - END - END w0_addr_in[7] - PIN w0_addr_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1402.205 1609.300 1402.275 ; - END - END w0_addr_in[8] - PIN w0_addr_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1412.985 1609.300 1413.055 ; - END - END w0_addr_in[9] - PIN w0_addr_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1423.765 1609.300 1423.835 ; - END - END w0_addr_in[10] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1445.325 0.140 1445.395 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1456.105 0.140 1456.175 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1466.885 0.140 1466.955 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1477.665 0.140 1477.735 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1488.445 0.140 1488.515 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 1499.225 0.140 1499.295 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1434.545 1609.300 1434.615 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1445.325 1609.300 1445.395 ; - END - END r0_addr_in[7] - PIN r0_addr_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1456.105 1609.300 1456.175 ; - END - END r0_addr_in[8] - PIN r0_addr_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1466.885 1609.300 1466.955 ; - END - END r0_addr_in[9] - PIN r0_addr_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 1609.160 1477.665 1609.300 1477.735 ; - END - END r0_addr_in[10] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1557.585 1511.860 1557.655 1512.000 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1563.665 1511.860 1563.735 1512.000 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1569.745 1511.860 1569.815 1512.000 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1575.825 1511.860 1575.895 1512.000 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1581.905 1511.860 1581.975 1512.000 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 1511.300 ; - RECT 2.670 0.700 2.950 1511.300 ; - RECT 4.910 0.700 5.190 1511.300 ; - RECT 7.150 0.700 7.430 1511.300 ; - RECT 9.390 0.700 9.670 1511.300 ; - RECT 11.630 0.700 11.910 1511.300 ; - RECT 13.870 0.700 14.150 1511.300 ; - RECT 16.110 0.700 16.390 1511.300 ; - RECT 18.350 0.700 18.630 1511.300 ; - RECT 20.590 0.700 20.870 1511.300 ; - RECT 22.830 0.700 23.110 1511.300 ; - RECT 25.070 0.700 25.350 1511.300 ; - RECT 27.310 0.700 27.590 1511.300 ; - RECT 29.550 0.700 29.830 1511.300 ; - RECT 31.790 0.700 32.070 1511.300 ; - RECT 34.030 0.700 34.310 1511.300 ; - RECT 36.270 0.700 36.550 1511.300 ; - RECT 38.510 0.700 38.790 1511.300 ; - RECT 40.750 0.700 41.030 1511.300 ; - RECT 42.990 0.700 43.270 1511.300 ; - RECT 45.230 0.700 45.510 1511.300 ; - RECT 47.470 0.700 47.750 1511.300 ; - RECT 49.710 0.700 49.990 1511.300 ; - RECT 51.950 0.700 52.230 1511.300 ; - RECT 54.190 0.700 54.470 1511.300 ; - RECT 56.430 0.700 56.710 1511.300 ; - RECT 58.670 0.700 58.950 1511.300 ; - RECT 60.910 0.700 61.190 1511.300 ; - RECT 63.150 0.700 63.430 1511.300 ; - RECT 65.390 0.700 65.670 1511.300 ; - RECT 67.630 0.700 67.910 1511.300 ; - RECT 69.870 0.700 70.150 1511.300 ; - RECT 72.110 0.700 72.390 1511.300 ; - RECT 74.350 0.700 74.630 1511.300 ; - RECT 76.590 0.700 76.870 1511.300 ; - RECT 78.830 0.700 79.110 1511.300 ; - RECT 81.070 0.700 81.350 1511.300 ; - RECT 83.310 0.700 83.590 1511.300 ; - RECT 85.550 0.700 85.830 1511.300 ; - RECT 87.790 0.700 88.070 1511.300 ; - RECT 90.030 0.700 90.310 1511.300 ; - RECT 92.270 0.700 92.550 1511.300 ; - RECT 94.510 0.700 94.790 1511.300 ; - RECT 96.750 0.700 97.030 1511.300 ; - RECT 98.990 0.700 99.270 1511.300 ; - RECT 101.230 0.700 101.510 1511.300 ; - RECT 103.470 0.700 103.750 1511.300 ; - RECT 105.710 0.700 105.990 1511.300 ; - RECT 107.950 0.700 108.230 1511.300 ; - RECT 110.190 0.700 110.470 1511.300 ; - RECT 112.430 0.700 112.710 1511.300 ; - RECT 114.670 0.700 114.950 1511.300 ; - RECT 116.910 0.700 117.190 1511.300 ; - RECT 119.150 0.700 119.430 1511.300 ; - RECT 121.390 0.700 121.670 1511.300 ; - RECT 123.630 0.700 123.910 1511.300 ; - RECT 125.870 0.700 126.150 1511.300 ; - RECT 128.110 0.700 128.390 1511.300 ; - RECT 130.350 0.700 130.630 1511.300 ; - RECT 132.590 0.700 132.870 1511.300 ; - RECT 134.830 0.700 135.110 1511.300 ; - RECT 137.070 0.700 137.350 1511.300 ; - RECT 139.310 0.700 139.590 1511.300 ; - RECT 141.550 0.700 141.830 1511.300 ; - RECT 143.790 0.700 144.070 1511.300 ; - RECT 146.030 0.700 146.310 1511.300 ; - RECT 148.270 0.700 148.550 1511.300 ; - RECT 150.510 0.700 150.790 1511.300 ; - RECT 152.750 0.700 153.030 1511.300 ; - RECT 154.990 0.700 155.270 1511.300 ; - RECT 157.230 0.700 157.510 1511.300 ; - RECT 159.470 0.700 159.750 1511.300 ; - RECT 161.710 0.700 161.990 1511.300 ; - RECT 163.950 0.700 164.230 1511.300 ; - RECT 166.190 0.700 166.470 1511.300 ; - RECT 168.430 0.700 168.710 1511.300 ; - RECT 170.670 0.700 170.950 1511.300 ; - RECT 172.910 0.700 173.190 1511.300 ; - RECT 175.150 0.700 175.430 1511.300 ; - RECT 177.390 0.700 177.670 1511.300 ; - RECT 179.630 0.700 179.910 1511.300 ; - RECT 181.870 0.700 182.150 1511.300 ; - RECT 184.110 0.700 184.390 1511.300 ; - RECT 186.350 0.700 186.630 1511.300 ; - RECT 188.590 0.700 188.870 1511.300 ; - RECT 190.830 0.700 191.110 1511.300 ; - RECT 193.070 0.700 193.350 1511.300 ; - RECT 195.310 0.700 195.590 1511.300 ; - RECT 197.550 0.700 197.830 1511.300 ; - RECT 199.790 0.700 200.070 1511.300 ; - RECT 202.030 0.700 202.310 1511.300 ; - RECT 204.270 0.700 204.550 1511.300 ; - RECT 206.510 0.700 206.790 1511.300 ; - RECT 208.750 0.700 209.030 1511.300 ; - RECT 210.990 0.700 211.270 1511.300 ; - RECT 213.230 0.700 213.510 1511.300 ; - RECT 215.470 0.700 215.750 1511.300 ; - RECT 217.710 0.700 217.990 1511.300 ; - RECT 219.950 0.700 220.230 1511.300 ; - RECT 222.190 0.700 222.470 1511.300 ; - RECT 224.430 0.700 224.710 1511.300 ; - RECT 226.670 0.700 226.950 1511.300 ; - RECT 228.910 0.700 229.190 1511.300 ; - RECT 231.150 0.700 231.430 1511.300 ; - RECT 233.390 0.700 233.670 1511.300 ; - RECT 235.630 0.700 235.910 1511.300 ; - RECT 237.870 0.700 238.150 1511.300 ; - RECT 240.110 0.700 240.390 1511.300 ; - RECT 242.350 0.700 242.630 1511.300 ; - RECT 244.590 0.700 244.870 1511.300 ; - RECT 246.830 0.700 247.110 1511.300 ; - RECT 249.070 0.700 249.350 1511.300 ; - RECT 251.310 0.700 251.590 1511.300 ; - RECT 253.550 0.700 253.830 1511.300 ; - RECT 255.790 0.700 256.070 1511.300 ; - RECT 258.030 0.700 258.310 1511.300 ; - RECT 260.270 0.700 260.550 1511.300 ; - RECT 262.510 0.700 262.790 1511.300 ; - RECT 264.750 0.700 265.030 1511.300 ; - RECT 266.990 0.700 267.270 1511.300 ; - RECT 269.230 0.700 269.510 1511.300 ; - RECT 271.470 0.700 271.750 1511.300 ; - RECT 273.710 0.700 273.990 1511.300 ; - RECT 275.950 0.700 276.230 1511.300 ; - RECT 278.190 0.700 278.470 1511.300 ; - RECT 280.430 0.700 280.710 1511.300 ; - RECT 282.670 0.700 282.950 1511.300 ; - RECT 284.910 0.700 285.190 1511.300 ; - RECT 287.150 0.700 287.430 1511.300 ; - RECT 289.390 0.700 289.670 1511.300 ; - RECT 291.630 0.700 291.910 1511.300 ; - RECT 293.870 0.700 294.150 1511.300 ; - RECT 296.110 0.700 296.390 1511.300 ; - RECT 298.350 0.700 298.630 1511.300 ; - RECT 300.590 0.700 300.870 1511.300 ; - RECT 302.830 0.700 303.110 1511.300 ; - RECT 305.070 0.700 305.350 1511.300 ; - RECT 307.310 0.700 307.590 1511.300 ; - RECT 309.550 0.700 309.830 1511.300 ; - RECT 311.790 0.700 312.070 1511.300 ; - RECT 314.030 0.700 314.310 1511.300 ; - RECT 316.270 0.700 316.550 1511.300 ; - RECT 318.510 0.700 318.790 1511.300 ; - RECT 320.750 0.700 321.030 1511.300 ; - RECT 322.990 0.700 323.270 1511.300 ; - RECT 325.230 0.700 325.510 1511.300 ; - RECT 327.470 0.700 327.750 1511.300 ; - RECT 329.710 0.700 329.990 1511.300 ; - RECT 331.950 0.700 332.230 1511.300 ; - RECT 334.190 0.700 334.470 1511.300 ; - RECT 336.430 0.700 336.710 1511.300 ; - RECT 338.670 0.700 338.950 1511.300 ; - RECT 340.910 0.700 341.190 1511.300 ; - RECT 343.150 0.700 343.430 1511.300 ; - RECT 345.390 0.700 345.670 1511.300 ; - RECT 347.630 0.700 347.910 1511.300 ; - RECT 349.870 0.700 350.150 1511.300 ; - RECT 352.110 0.700 352.390 1511.300 ; - RECT 354.350 0.700 354.630 1511.300 ; - RECT 356.590 0.700 356.870 1511.300 ; - RECT 358.830 0.700 359.110 1511.300 ; - RECT 361.070 0.700 361.350 1511.300 ; - RECT 363.310 0.700 363.590 1511.300 ; - RECT 365.550 0.700 365.830 1511.300 ; - RECT 367.790 0.700 368.070 1511.300 ; - RECT 370.030 0.700 370.310 1511.300 ; - RECT 372.270 0.700 372.550 1511.300 ; - RECT 374.510 0.700 374.790 1511.300 ; - RECT 376.750 0.700 377.030 1511.300 ; - RECT 378.990 0.700 379.270 1511.300 ; - RECT 381.230 0.700 381.510 1511.300 ; - RECT 383.470 0.700 383.750 1511.300 ; - RECT 385.710 0.700 385.990 1511.300 ; - RECT 387.950 0.700 388.230 1511.300 ; - RECT 390.190 0.700 390.470 1511.300 ; - RECT 392.430 0.700 392.710 1511.300 ; - RECT 394.670 0.700 394.950 1511.300 ; - RECT 396.910 0.700 397.190 1511.300 ; - RECT 399.150 0.700 399.430 1511.300 ; - RECT 401.390 0.700 401.670 1511.300 ; - RECT 403.630 0.700 403.910 1511.300 ; - RECT 405.870 0.700 406.150 1511.300 ; - RECT 408.110 0.700 408.390 1511.300 ; - RECT 410.350 0.700 410.630 1511.300 ; - RECT 412.590 0.700 412.870 1511.300 ; - RECT 414.830 0.700 415.110 1511.300 ; - RECT 417.070 0.700 417.350 1511.300 ; - RECT 419.310 0.700 419.590 1511.300 ; - RECT 421.550 0.700 421.830 1511.300 ; - RECT 423.790 0.700 424.070 1511.300 ; - RECT 426.030 0.700 426.310 1511.300 ; - RECT 428.270 0.700 428.550 1511.300 ; - RECT 430.510 0.700 430.790 1511.300 ; - RECT 432.750 0.700 433.030 1511.300 ; - RECT 434.990 0.700 435.270 1511.300 ; - RECT 437.230 0.700 437.510 1511.300 ; - RECT 439.470 0.700 439.750 1511.300 ; - RECT 441.710 0.700 441.990 1511.300 ; - RECT 443.950 0.700 444.230 1511.300 ; - RECT 446.190 0.700 446.470 1511.300 ; - RECT 448.430 0.700 448.710 1511.300 ; - RECT 450.670 0.700 450.950 1511.300 ; - RECT 452.910 0.700 453.190 1511.300 ; - RECT 455.150 0.700 455.430 1511.300 ; - RECT 457.390 0.700 457.670 1511.300 ; - RECT 459.630 0.700 459.910 1511.300 ; - RECT 461.870 0.700 462.150 1511.300 ; - RECT 464.110 0.700 464.390 1511.300 ; - RECT 466.350 0.700 466.630 1511.300 ; - RECT 468.590 0.700 468.870 1511.300 ; - RECT 470.830 0.700 471.110 1511.300 ; - RECT 473.070 0.700 473.350 1511.300 ; - RECT 475.310 0.700 475.590 1511.300 ; - RECT 477.550 0.700 477.830 1511.300 ; - RECT 479.790 0.700 480.070 1511.300 ; - RECT 482.030 0.700 482.310 1511.300 ; - RECT 484.270 0.700 484.550 1511.300 ; - RECT 486.510 0.700 486.790 1511.300 ; - RECT 488.750 0.700 489.030 1511.300 ; - RECT 490.990 0.700 491.270 1511.300 ; - RECT 493.230 0.700 493.510 1511.300 ; - RECT 495.470 0.700 495.750 1511.300 ; - RECT 497.710 0.700 497.990 1511.300 ; - RECT 499.950 0.700 500.230 1511.300 ; - RECT 502.190 0.700 502.470 1511.300 ; - RECT 504.430 0.700 504.710 1511.300 ; - RECT 506.670 0.700 506.950 1511.300 ; - RECT 508.910 0.700 509.190 1511.300 ; - RECT 511.150 0.700 511.430 1511.300 ; - RECT 513.390 0.700 513.670 1511.300 ; - RECT 515.630 0.700 515.910 1511.300 ; - RECT 517.870 0.700 518.150 1511.300 ; - RECT 520.110 0.700 520.390 1511.300 ; - RECT 522.350 0.700 522.630 1511.300 ; - RECT 524.590 0.700 524.870 1511.300 ; - RECT 526.830 0.700 527.110 1511.300 ; - RECT 529.070 0.700 529.350 1511.300 ; - RECT 531.310 0.700 531.590 1511.300 ; - RECT 533.550 0.700 533.830 1511.300 ; - RECT 535.790 0.700 536.070 1511.300 ; - RECT 538.030 0.700 538.310 1511.300 ; - RECT 540.270 0.700 540.550 1511.300 ; - RECT 542.510 0.700 542.790 1511.300 ; - RECT 544.750 0.700 545.030 1511.300 ; - RECT 546.990 0.700 547.270 1511.300 ; - RECT 549.230 0.700 549.510 1511.300 ; - RECT 551.470 0.700 551.750 1511.300 ; - RECT 553.710 0.700 553.990 1511.300 ; - RECT 555.950 0.700 556.230 1511.300 ; - RECT 558.190 0.700 558.470 1511.300 ; - RECT 560.430 0.700 560.710 1511.300 ; - RECT 562.670 0.700 562.950 1511.300 ; - RECT 564.910 0.700 565.190 1511.300 ; - RECT 567.150 0.700 567.430 1511.300 ; - RECT 569.390 0.700 569.670 1511.300 ; - RECT 571.630 0.700 571.910 1511.300 ; - RECT 573.870 0.700 574.150 1511.300 ; - RECT 576.110 0.700 576.390 1511.300 ; - RECT 578.350 0.700 578.630 1511.300 ; - RECT 580.590 0.700 580.870 1511.300 ; - RECT 582.830 0.700 583.110 1511.300 ; - RECT 585.070 0.700 585.350 1511.300 ; - RECT 587.310 0.700 587.590 1511.300 ; - RECT 589.550 0.700 589.830 1511.300 ; - RECT 591.790 0.700 592.070 1511.300 ; - RECT 594.030 0.700 594.310 1511.300 ; - RECT 596.270 0.700 596.550 1511.300 ; - RECT 598.510 0.700 598.790 1511.300 ; - RECT 600.750 0.700 601.030 1511.300 ; - RECT 602.990 0.700 603.270 1511.300 ; - RECT 605.230 0.700 605.510 1511.300 ; - RECT 607.470 0.700 607.750 1511.300 ; - RECT 609.710 0.700 609.990 1511.300 ; - RECT 611.950 0.700 612.230 1511.300 ; - RECT 614.190 0.700 614.470 1511.300 ; - RECT 616.430 0.700 616.710 1511.300 ; - RECT 618.670 0.700 618.950 1511.300 ; - RECT 620.910 0.700 621.190 1511.300 ; - RECT 623.150 0.700 623.430 1511.300 ; - RECT 625.390 0.700 625.670 1511.300 ; - RECT 627.630 0.700 627.910 1511.300 ; - RECT 629.870 0.700 630.150 1511.300 ; - RECT 632.110 0.700 632.390 1511.300 ; - RECT 634.350 0.700 634.630 1511.300 ; - RECT 636.590 0.700 636.870 1511.300 ; - RECT 638.830 0.700 639.110 1511.300 ; - RECT 641.070 0.700 641.350 1511.300 ; - RECT 643.310 0.700 643.590 1511.300 ; - RECT 645.550 0.700 645.830 1511.300 ; - RECT 647.790 0.700 648.070 1511.300 ; - RECT 650.030 0.700 650.310 1511.300 ; - RECT 652.270 0.700 652.550 1511.300 ; - RECT 654.510 0.700 654.790 1511.300 ; - RECT 656.750 0.700 657.030 1511.300 ; - RECT 658.990 0.700 659.270 1511.300 ; - RECT 661.230 0.700 661.510 1511.300 ; - RECT 663.470 0.700 663.750 1511.300 ; - RECT 665.710 0.700 665.990 1511.300 ; - RECT 667.950 0.700 668.230 1511.300 ; - RECT 670.190 0.700 670.470 1511.300 ; - RECT 672.430 0.700 672.710 1511.300 ; - RECT 674.670 0.700 674.950 1511.300 ; - RECT 676.910 0.700 677.190 1511.300 ; - RECT 679.150 0.700 679.430 1511.300 ; - RECT 681.390 0.700 681.670 1511.300 ; - RECT 683.630 0.700 683.910 1511.300 ; - RECT 685.870 0.700 686.150 1511.300 ; - RECT 688.110 0.700 688.390 1511.300 ; - RECT 690.350 0.700 690.630 1511.300 ; - RECT 692.590 0.700 692.870 1511.300 ; - RECT 694.830 0.700 695.110 1511.300 ; - RECT 697.070 0.700 697.350 1511.300 ; - RECT 699.310 0.700 699.590 1511.300 ; - RECT 701.550 0.700 701.830 1511.300 ; - RECT 703.790 0.700 704.070 1511.300 ; - RECT 706.030 0.700 706.310 1511.300 ; - RECT 708.270 0.700 708.550 1511.300 ; - RECT 710.510 0.700 710.790 1511.300 ; - RECT 712.750 0.700 713.030 1511.300 ; - RECT 714.990 0.700 715.270 1511.300 ; - RECT 717.230 0.700 717.510 1511.300 ; - RECT 719.470 0.700 719.750 1511.300 ; - RECT 721.710 0.700 721.990 1511.300 ; - RECT 723.950 0.700 724.230 1511.300 ; - RECT 726.190 0.700 726.470 1511.300 ; - RECT 728.430 0.700 728.710 1511.300 ; - RECT 730.670 0.700 730.950 1511.300 ; - RECT 732.910 0.700 733.190 1511.300 ; - RECT 735.150 0.700 735.430 1511.300 ; - RECT 737.390 0.700 737.670 1511.300 ; - RECT 739.630 0.700 739.910 1511.300 ; - RECT 741.870 0.700 742.150 1511.300 ; - RECT 744.110 0.700 744.390 1511.300 ; - RECT 746.350 0.700 746.630 1511.300 ; - RECT 748.590 0.700 748.870 1511.300 ; - RECT 750.830 0.700 751.110 1511.300 ; - RECT 753.070 0.700 753.350 1511.300 ; - RECT 755.310 0.700 755.590 1511.300 ; - RECT 757.550 0.700 757.830 1511.300 ; - RECT 759.790 0.700 760.070 1511.300 ; - RECT 762.030 0.700 762.310 1511.300 ; - RECT 764.270 0.700 764.550 1511.300 ; - RECT 766.510 0.700 766.790 1511.300 ; - RECT 768.750 0.700 769.030 1511.300 ; - RECT 770.990 0.700 771.270 1511.300 ; - RECT 773.230 0.700 773.510 1511.300 ; - RECT 775.470 0.700 775.750 1511.300 ; - RECT 777.710 0.700 777.990 1511.300 ; - RECT 779.950 0.700 780.230 1511.300 ; - RECT 782.190 0.700 782.470 1511.300 ; - RECT 784.430 0.700 784.710 1511.300 ; - RECT 786.670 0.700 786.950 1511.300 ; - RECT 788.910 0.700 789.190 1511.300 ; - RECT 791.150 0.700 791.430 1511.300 ; - RECT 793.390 0.700 793.670 1511.300 ; - RECT 795.630 0.700 795.910 1511.300 ; - RECT 797.870 0.700 798.150 1511.300 ; - RECT 800.110 0.700 800.390 1511.300 ; - RECT 802.350 0.700 802.630 1511.300 ; - RECT 804.590 0.700 804.870 1511.300 ; - RECT 806.830 0.700 807.110 1511.300 ; - RECT 809.070 0.700 809.350 1511.300 ; - RECT 811.310 0.700 811.590 1511.300 ; - RECT 813.550 0.700 813.830 1511.300 ; - RECT 815.790 0.700 816.070 1511.300 ; - RECT 818.030 0.700 818.310 1511.300 ; - RECT 820.270 0.700 820.550 1511.300 ; - RECT 822.510 0.700 822.790 1511.300 ; - RECT 824.750 0.700 825.030 1511.300 ; - RECT 826.990 0.700 827.270 1511.300 ; - RECT 829.230 0.700 829.510 1511.300 ; - RECT 831.470 0.700 831.750 1511.300 ; - RECT 833.710 0.700 833.990 1511.300 ; - RECT 835.950 0.700 836.230 1511.300 ; - RECT 838.190 0.700 838.470 1511.300 ; - RECT 840.430 0.700 840.710 1511.300 ; - RECT 842.670 0.700 842.950 1511.300 ; - RECT 844.910 0.700 845.190 1511.300 ; - RECT 847.150 0.700 847.430 1511.300 ; - RECT 849.390 0.700 849.670 1511.300 ; - RECT 851.630 0.700 851.910 1511.300 ; - RECT 853.870 0.700 854.150 1511.300 ; - RECT 856.110 0.700 856.390 1511.300 ; - RECT 858.350 0.700 858.630 1511.300 ; - RECT 860.590 0.700 860.870 1511.300 ; - RECT 862.830 0.700 863.110 1511.300 ; - RECT 865.070 0.700 865.350 1511.300 ; - RECT 867.310 0.700 867.590 1511.300 ; - RECT 869.550 0.700 869.830 1511.300 ; - RECT 871.790 0.700 872.070 1511.300 ; - RECT 874.030 0.700 874.310 1511.300 ; - RECT 876.270 0.700 876.550 1511.300 ; - RECT 878.510 0.700 878.790 1511.300 ; - RECT 880.750 0.700 881.030 1511.300 ; - RECT 882.990 0.700 883.270 1511.300 ; - RECT 885.230 0.700 885.510 1511.300 ; - RECT 887.470 0.700 887.750 1511.300 ; - RECT 889.710 0.700 889.990 1511.300 ; - RECT 891.950 0.700 892.230 1511.300 ; - RECT 894.190 0.700 894.470 1511.300 ; - RECT 896.430 0.700 896.710 1511.300 ; - RECT 898.670 0.700 898.950 1511.300 ; - RECT 900.910 0.700 901.190 1511.300 ; - RECT 903.150 0.700 903.430 1511.300 ; - RECT 905.390 0.700 905.670 1511.300 ; - RECT 907.630 0.700 907.910 1511.300 ; - RECT 909.870 0.700 910.150 1511.300 ; - RECT 912.110 0.700 912.390 1511.300 ; - RECT 914.350 0.700 914.630 1511.300 ; - RECT 916.590 0.700 916.870 1511.300 ; - RECT 918.830 0.700 919.110 1511.300 ; - RECT 921.070 0.700 921.350 1511.300 ; - RECT 923.310 0.700 923.590 1511.300 ; - RECT 925.550 0.700 925.830 1511.300 ; - RECT 927.790 0.700 928.070 1511.300 ; - RECT 930.030 0.700 930.310 1511.300 ; - RECT 932.270 0.700 932.550 1511.300 ; - RECT 934.510 0.700 934.790 1511.300 ; - RECT 936.750 0.700 937.030 1511.300 ; - RECT 938.990 0.700 939.270 1511.300 ; - RECT 941.230 0.700 941.510 1511.300 ; - RECT 943.470 0.700 943.750 1511.300 ; - RECT 945.710 0.700 945.990 1511.300 ; - RECT 947.950 0.700 948.230 1511.300 ; - RECT 950.190 0.700 950.470 1511.300 ; - RECT 952.430 0.700 952.710 1511.300 ; - RECT 954.670 0.700 954.950 1511.300 ; - RECT 956.910 0.700 957.190 1511.300 ; - RECT 959.150 0.700 959.430 1511.300 ; - RECT 961.390 0.700 961.670 1511.300 ; - RECT 963.630 0.700 963.910 1511.300 ; - RECT 965.870 0.700 966.150 1511.300 ; - RECT 968.110 0.700 968.390 1511.300 ; - RECT 970.350 0.700 970.630 1511.300 ; - RECT 972.590 0.700 972.870 1511.300 ; - RECT 974.830 0.700 975.110 1511.300 ; - RECT 977.070 0.700 977.350 1511.300 ; - RECT 979.310 0.700 979.590 1511.300 ; - RECT 981.550 0.700 981.830 1511.300 ; - RECT 983.790 0.700 984.070 1511.300 ; - RECT 986.030 0.700 986.310 1511.300 ; - RECT 988.270 0.700 988.550 1511.300 ; - RECT 990.510 0.700 990.790 1511.300 ; - RECT 992.750 0.700 993.030 1511.300 ; - RECT 994.990 0.700 995.270 1511.300 ; - RECT 997.230 0.700 997.510 1511.300 ; - RECT 999.470 0.700 999.750 1511.300 ; - RECT 1001.710 0.700 1001.990 1511.300 ; - RECT 1003.950 0.700 1004.230 1511.300 ; - RECT 1006.190 0.700 1006.470 1511.300 ; - RECT 1008.430 0.700 1008.710 1511.300 ; - RECT 1010.670 0.700 1010.950 1511.300 ; - RECT 1012.910 0.700 1013.190 1511.300 ; - RECT 1015.150 0.700 1015.430 1511.300 ; - RECT 1017.390 0.700 1017.670 1511.300 ; - RECT 1019.630 0.700 1019.910 1511.300 ; - RECT 1021.870 0.700 1022.150 1511.300 ; - RECT 1024.110 0.700 1024.390 1511.300 ; - RECT 1026.350 0.700 1026.630 1511.300 ; - RECT 1028.590 0.700 1028.870 1511.300 ; - RECT 1030.830 0.700 1031.110 1511.300 ; - RECT 1033.070 0.700 1033.350 1511.300 ; - RECT 1035.310 0.700 1035.590 1511.300 ; - RECT 1037.550 0.700 1037.830 1511.300 ; - RECT 1039.790 0.700 1040.070 1511.300 ; - RECT 1042.030 0.700 1042.310 1511.300 ; - RECT 1044.270 0.700 1044.550 1511.300 ; - RECT 1046.510 0.700 1046.790 1511.300 ; - RECT 1048.750 0.700 1049.030 1511.300 ; - RECT 1050.990 0.700 1051.270 1511.300 ; - RECT 1053.230 0.700 1053.510 1511.300 ; - RECT 1055.470 0.700 1055.750 1511.300 ; - RECT 1057.710 0.700 1057.990 1511.300 ; - RECT 1059.950 0.700 1060.230 1511.300 ; - RECT 1062.190 0.700 1062.470 1511.300 ; - RECT 1064.430 0.700 1064.710 1511.300 ; - RECT 1066.670 0.700 1066.950 1511.300 ; - RECT 1068.910 0.700 1069.190 1511.300 ; - RECT 1071.150 0.700 1071.430 1511.300 ; - RECT 1073.390 0.700 1073.670 1511.300 ; - RECT 1075.630 0.700 1075.910 1511.300 ; - RECT 1077.870 0.700 1078.150 1511.300 ; - RECT 1080.110 0.700 1080.390 1511.300 ; - RECT 1082.350 0.700 1082.630 1511.300 ; - RECT 1084.590 0.700 1084.870 1511.300 ; - RECT 1086.830 0.700 1087.110 1511.300 ; - RECT 1089.070 0.700 1089.350 1511.300 ; - RECT 1091.310 0.700 1091.590 1511.300 ; - RECT 1093.550 0.700 1093.830 1511.300 ; - RECT 1095.790 0.700 1096.070 1511.300 ; - RECT 1098.030 0.700 1098.310 1511.300 ; - RECT 1100.270 0.700 1100.550 1511.300 ; - RECT 1102.510 0.700 1102.790 1511.300 ; - RECT 1104.750 0.700 1105.030 1511.300 ; - RECT 1106.990 0.700 1107.270 1511.300 ; - RECT 1109.230 0.700 1109.510 1511.300 ; - RECT 1111.470 0.700 1111.750 1511.300 ; - RECT 1113.710 0.700 1113.990 1511.300 ; - RECT 1115.950 0.700 1116.230 1511.300 ; - RECT 1118.190 0.700 1118.470 1511.300 ; - RECT 1120.430 0.700 1120.710 1511.300 ; - RECT 1122.670 0.700 1122.950 1511.300 ; - RECT 1124.910 0.700 1125.190 1511.300 ; - RECT 1127.150 0.700 1127.430 1511.300 ; - RECT 1129.390 0.700 1129.670 1511.300 ; - RECT 1131.630 0.700 1131.910 1511.300 ; - RECT 1133.870 0.700 1134.150 1511.300 ; - RECT 1136.110 0.700 1136.390 1511.300 ; - RECT 1138.350 0.700 1138.630 1511.300 ; - RECT 1140.590 0.700 1140.870 1511.300 ; - RECT 1142.830 0.700 1143.110 1511.300 ; - RECT 1145.070 0.700 1145.350 1511.300 ; - RECT 1147.310 0.700 1147.590 1511.300 ; - RECT 1149.550 0.700 1149.830 1511.300 ; - RECT 1151.790 0.700 1152.070 1511.300 ; - RECT 1154.030 0.700 1154.310 1511.300 ; - RECT 1156.270 0.700 1156.550 1511.300 ; - RECT 1158.510 0.700 1158.790 1511.300 ; - RECT 1160.750 0.700 1161.030 1511.300 ; - RECT 1162.990 0.700 1163.270 1511.300 ; - RECT 1165.230 0.700 1165.510 1511.300 ; - RECT 1167.470 0.700 1167.750 1511.300 ; - RECT 1169.710 0.700 1169.990 1511.300 ; - RECT 1171.950 0.700 1172.230 1511.300 ; - RECT 1174.190 0.700 1174.470 1511.300 ; - RECT 1176.430 0.700 1176.710 1511.300 ; - RECT 1178.670 0.700 1178.950 1511.300 ; - RECT 1180.910 0.700 1181.190 1511.300 ; - RECT 1183.150 0.700 1183.430 1511.300 ; - RECT 1185.390 0.700 1185.670 1511.300 ; - RECT 1187.630 0.700 1187.910 1511.300 ; - RECT 1189.870 0.700 1190.150 1511.300 ; - RECT 1192.110 0.700 1192.390 1511.300 ; - RECT 1194.350 0.700 1194.630 1511.300 ; - RECT 1196.590 0.700 1196.870 1511.300 ; - RECT 1198.830 0.700 1199.110 1511.300 ; - RECT 1201.070 0.700 1201.350 1511.300 ; - RECT 1203.310 0.700 1203.590 1511.300 ; - RECT 1205.550 0.700 1205.830 1511.300 ; - RECT 1207.790 0.700 1208.070 1511.300 ; - RECT 1210.030 0.700 1210.310 1511.300 ; - RECT 1212.270 0.700 1212.550 1511.300 ; - RECT 1214.510 0.700 1214.790 1511.300 ; - RECT 1216.750 0.700 1217.030 1511.300 ; - RECT 1218.990 0.700 1219.270 1511.300 ; - RECT 1221.230 0.700 1221.510 1511.300 ; - RECT 1223.470 0.700 1223.750 1511.300 ; - RECT 1225.710 0.700 1225.990 1511.300 ; - RECT 1227.950 0.700 1228.230 1511.300 ; - RECT 1230.190 0.700 1230.470 1511.300 ; - RECT 1232.430 0.700 1232.710 1511.300 ; - RECT 1234.670 0.700 1234.950 1511.300 ; - RECT 1236.910 0.700 1237.190 1511.300 ; - RECT 1239.150 0.700 1239.430 1511.300 ; - RECT 1241.390 0.700 1241.670 1511.300 ; - RECT 1243.630 0.700 1243.910 1511.300 ; - RECT 1245.870 0.700 1246.150 1511.300 ; - RECT 1248.110 0.700 1248.390 1511.300 ; - RECT 1250.350 0.700 1250.630 1511.300 ; - RECT 1252.590 0.700 1252.870 1511.300 ; - RECT 1254.830 0.700 1255.110 1511.300 ; - RECT 1257.070 0.700 1257.350 1511.300 ; - RECT 1259.310 0.700 1259.590 1511.300 ; - RECT 1261.550 0.700 1261.830 1511.300 ; - RECT 1263.790 0.700 1264.070 1511.300 ; - RECT 1266.030 0.700 1266.310 1511.300 ; - RECT 1268.270 0.700 1268.550 1511.300 ; - RECT 1270.510 0.700 1270.790 1511.300 ; - RECT 1272.750 0.700 1273.030 1511.300 ; - RECT 1274.990 0.700 1275.270 1511.300 ; - RECT 1277.230 0.700 1277.510 1511.300 ; - RECT 1279.470 0.700 1279.750 1511.300 ; - RECT 1281.710 0.700 1281.990 1511.300 ; - RECT 1283.950 0.700 1284.230 1511.300 ; - RECT 1286.190 0.700 1286.470 1511.300 ; - RECT 1288.430 0.700 1288.710 1511.300 ; - RECT 1290.670 0.700 1290.950 1511.300 ; - RECT 1292.910 0.700 1293.190 1511.300 ; - RECT 1295.150 0.700 1295.430 1511.300 ; - RECT 1297.390 0.700 1297.670 1511.300 ; - RECT 1299.630 0.700 1299.910 1511.300 ; - RECT 1301.870 0.700 1302.150 1511.300 ; - RECT 1304.110 0.700 1304.390 1511.300 ; - RECT 1306.350 0.700 1306.630 1511.300 ; - RECT 1308.590 0.700 1308.870 1511.300 ; - RECT 1310.830 0.700 1311.110 1511.300 ; - RECT 1313.070 0.700 1313.350 1511.300 ; - RECT 1315.310 0.700 1315.590 1511.300 ; - RECT 1317.550 0.700 1317.830 1511.300 ; - RECT 1319.790 0.700 1320.070 1511.300 ; - RECT 1322.030 0.700 1322.310 1511.300 ; - RECT 1324.270 0.700 1324.550 1511.300 ; - RECT 1326.510 0.700 1326.790 1511.300 ; - RECT 1328.750 0.700 1329.030 1511.300 ; - RECT 1330.990 0.700 1331.270 1511.300 ; - RECT 1333.230 0.700 1333.510 1511.300 ; - RECT 1335.470 0.700 1335.750 1511.300 ; - RECT 1337.710 0.700 1337.990 1511.300 ; - RECT 1339.950 0.700 1340.230 1511.300 ; - RECT 1342.190 0.700 1342.470 1511.300 ; - RECT 1344.430 0.700 1344.710 1511.300 ; - RECT 1346.670 0.700 1346.950 1511.300 ; - RECT 1348.910 0.700 1349.190 1511.300 ; - RECT 1351.150 0.700 1351.430 1511.300 ; - RECT 1353.390 0.700 1353.670 1511.300 ; - RECT 1355.630 0.700 1355.910 1511.300 ; - RECT 1357.870 0.700 1358.150 1511.300 ; - RECT 1360.110 0.700 1360.390 1511.300 ; - RECT 1362.350 0.700 1362.630 1511.300 ; - RECT 1364.590 0.700 1364.870 1511.300 ; - RECT 1366.830 0.700 1367.110 1511.300 ; - RECT 1369.070 0.700 1369.350 1511.300 ; - RECT 1371.310 0.700 1371.590 1511.300 ; - RECT 1373.550 0.700 1373.830 1511.300 ; - RECT 1375.790 0.700 1376.070 1511.300 ; - RECT 1378.030 0.700 1378.310 1511.300 ; - RECT 1380.270 0.700 1380.550 1511.300 ; - RECT 1382.510 0.700 1382.790 1511.300 ; - RECT 1384.750 0.700 1385.030 1511.300 ; - RECT 1386.990 0.700 1387.270 1511.300 ; - RECT 1389.230 0.700 1389.510 1511.300 ; - RECT 1391.470 0.700 1391.750 1511.300 ; - RECT 1393.710 0.700 1393.990 1511.300 ; - RECT 1395.950 0.700 1396.230 1511.300 ; - RECT 1398.190 0.700 1398.470 1511.300 ; - RECT 1400.430 0.700 1400.710 1511.300 ; - RECT 1402.670 0.700 1402.950 1511.300 ; - RECT 1404.910 0.700 1405.190 1511.300 ; - RECT 1407.150 0.700 1407.430 1511.300 ; - RECT 1409.390 0.700 1409.670 1511.300 ; - RECT 1411.630 0.700 1411.910 1511.300 ; - RECT 1413.870 0.700 1414.150 1511.300 ; - RECT 1416.110 0.700 1416.390 1511.300 ; - RECT 1418.350 0.700 1418.630 1511.300 ; - RECT 1420.590 0.700 1420.870 1511.300 ; - RECT 1422.830 0.700 1423.110 1511.300 ; - RECT 1425.070 0.700 1425.350 1511.300 ; - RECT 1427.310 0.700 1427.590 1511.300 ; - RECT 1429.550 0.700 1429.830 1511.300 ; - RECT 1431.790 0.700 1432.070 1511.300 ; - RECT 1434.030 0.700 1434.310 1511.300 ; - RECT 1436.270 0.700 1436.550 1511.300 ; - RECT 1438.510 0.700 1438.790 1511.300 ; - RECT 1440.750 0.700 1441.030 1511.300 ; - RECT 1442.990 0.700 1443.270 1511.300 ; - RECT 1445.230 0.700 1445.510 1511.300 ; - RECT 1447.470 0.700 1447.750 1511.300 ; - RECT 1449.710 0.700 1449.990 1511.300 ; - RECT 1451.950 0.700 1452.230 1511.300 ; - RECT 1454.190 0.700 1454.470 1511.300 ; - RECT 1456.430 0.700 1456.710 1511.300 ; - RECT 1458.670 0.700 1458.950 1511.300 ; - RECT 1460.910 0.700 1461.190 1511.300 ; - RECT 1463.150 0.700 1463.430 1511.300 ; - RECT 1465.390 0.700 1465.670 1511.300 ; - RECT 1467.630 0.700 1467.910 1511.300 ; - RECT 1469.870 0.700 1470.150 1511.300 ; - RECT 1472.110 0.700 1472.390 1511.300 ; - RECT 1474.350 0.700 1474.630 1511.300 ; - RECT 1476.590 0.700 1476.870 1511.300 ; - RECT 1478.830 0.700 1479.110 1511.300 ; - RECT 1481.070 0.700 1481.350 1511.300 ; - RECT 1483.310 0.700 1483.590 1511.300 ; - RECT 1485.550 0.700 1485.830 1511.300 ; - RECT 1487.790 0.700 1488.070 1511.300 ; - RECT 1490.030 0.700 1490.310 1511.300 ; - RECT 1492.270 0.700 1492.550 1511.300 ; - RECT 1494.510 0.700 1494.790 1511.300 ; - RECT 1496.750 0.700 1497.030 1511.300 ; - RECT 1498.990 0.700 1499.270 1511.300 ; - RECT 1501.230 0.700 1501.510 1511.300 ; - RECT 1503.470 0.700 1503.750 1511.300 ; - RECT 1505.710 0.700 1505.990 1511.300 ; - RECT 1507.950 0.700 1508.230 1511.300 ; - RECT 1510.190 0.700 1510.470 1511.300 ; - RECT 1512.430 0.700 1512.710 1511.300 ; - RECT 1514.670 0.700 1514.950 1511.300 ; - RECT 1516.910 0.700 1517.190 1511.300 ; - RECT 1519.150 0.700 1519.430 1511.300 ; - RECT 1521.390 0.700 1521.670 1511.300 ; - RECT 1523.630 0.700 1523.910 1511.300 ; - RECT 1525.870 0.700 1526.150 1511.300 ; - RECT 1528.110 0.700 1528.390 1511.300 ; - RECT 1530.350 0.700 1530.630 1511.300 ; - RECT 1532.590 0.700 1532.870 1511.300 ; - RECT 1534.830 0.700 1535.110 1511.300 ; - RECT 1537.070 0.700 1537.350 1511.300 ; - RECT 1539.310 0.700 1539.590 1511.300 ; - RECT 1541.550 0.700 1541.830 1511.300 ; - RECT 1543.790 0.700 1544.070 1511.300 ; - RECT 1546.030 0.700 1546.310 1511.300 ; - RECT 1548.270 0.700 1548.550 1511.300 ; - RECT 1550.510 0.700 1550.790 1511.300 ; - RECT 1552.750 0.700 1553.030 1511.300 ; - RECT 1554.990 0.700 1555.270 1511.300 ; - RECT 1557.230 0.700 1557.510 1511.300 ; - RECT 1559.470 0.700 1559.750 1511.300 ; - RECT 1561.710 0.700 1561.990 1511.300 ; - RECT 1563.950 0.700 1564.230 1511.300 ; - RECT 1566.190 0.700 1566.470 1511.300 ; - RECT 1568.430 0.700 1568.710 1511.300 ; - RECT 1570.670 0.700 1570.950 1511.300 ; - RECT 1572.910 0.700 1573.190 1511.300 ; - RECT 1575.150 0.700 1575.430 1511.300 ; - RECT 1577.390 0.700 1577.670 1511.300 ; - RECT 1579.630 0.700 1579.910 1511.300 ; - RECT 1581.870 0.700 1582.150 1511.300 ; - RECT 1584.110 0.700 1584.390 1511.300 ; - RECT 1586.350 0.700 1586.630 1511.300 ; - RECT 1588.590 0.700 1588.870 1511.300 ; - RECT 1590.830 0.700 1591.110 1511.300 ; - RECT 1593.070 0.700 1593.350 1511.300 ; - RECT 1595.310 0.700 1595.590 1511.300 ; - RECT 1597.550 0.700 1597.830 1511.300 ; - RECT 1599.790 0.700 1600.070 1511.300 ; - RECT 1602.030 0.700 1602.310 1511.300 ; - RECT 1604.270 0.700 1604.550 1511.300 ; - RECT 1606.510 0.700 1606.790 1511.300 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 1511.300 ; - RECT 2.670 0.700 2.950 1511.300 ; - RECT 4.910 0.700 5.190 1511.300 ; - RECT 7.150 0.700 7.430 1511.300 ; - RECT 9.390 0.700 9.670 1511.300 ; - RECT 11.630 0.700 11.910 1511.300 ; - RECT 13.870 0.700 14.150 1511.300 ; - RECT 16.110 0.700 16.390 1511.300 ; - RECT 18.350 0.700 18.630 1511.300 ; - RECT 20.590 0.700 20.870 1511.300 ; - RECT 22.830 0.700 23.110 1511.300 ; - RECT 25.070 0.700 25.350 1511.300 ; - RECT 27.310 0.700 27.590 1511.300 ; - RECT 29.550 0.700 29.830 1511.300 ; - RECT 31.790 0.700 32.070 1511.300 ; - RECT 34.030 0.700 34.310 1511.300 ; - RECT 36.270 0.700 36.550 1511.300 ; - RECT 38.510 0.700 38.790 1511.300 ; - RECT 40.750 0.700 41.030 1511.300 ; - RECT 42.990 0.700 43.270 1511.300 ; - RECT 45.230 0.700 45.510 1511.300 ; - RECT 47.470 0.700 47.750 1511.300 ; - RECT 49.710 0.700 49.990 1511.300 ; - RECT 51.950 0.700 52.230 1511.300 ; - RECT 54.190 0.700 54.470 1511.300 ; - RECT 56.430 0.700 56.710 1511.300 ; - RECT 58.670 0.700 58.950 1511.300 ; - RECT 60.910 0.700 61.190 1511.300 ; - RECT 63.150 0.700 63.430 1511.300 ; - RECT 65.390 0.700 65.670 1511.300 ; - RECT 67.630 0.700 67.910 1511.300 ; - RECT 69.870 0.700 70.150 1511.300 ; - RECT 72.110 0.700 72.390 1511.300 ; - RECT 74.350 0.700 74.630 1511.300 ; - RECT 76.590 0.700 76.870 1511.300 ; - RECT 78.830 0.700 79.110 1511.300 ; - RECT 81.070 0.700 81.350 1511.300 ; - RECT 83.310 0.700 83.590 1511.300 ; - RECT 85.550 0.700 85.830 1511.300 ; - RECT 87.790 0.700 88.070 1511.300 ; - RECT 90.030 0.700 90.310 1511.300 ; - RECT 92.270 0.700 92.550 1511.300 ; - RECT 94.510 0.700 94.790 1511.300 ; - RECT 96.750 0.700 97.030 1511.300 ; - RECT 98.990 0.700 99.270 1511.300 ; - RECT 101.230 0.700 101.510 1511.300 ; - RECT 103.470 0.700 103.750 1511.300 ; - RECT 105.710 0.700 105.990 1511.300 ; - RECT 107.950 0.700 108.230 1511.300 ; - RECT 110.190 0.700 110.470 1511.300 ; - RECT 112.430 0.700 112.710 1511.300 ; - RECT 114.670 0.700 114.950 1511.300 ; - RECT 116.910 0.700 117.190 1511.300 ; - RECT 119.150 0.700 119.430 1511.300 ; - RECT 121.390 0.700 121.670 1511.300 ; - RECT 123.630 0.700 123.910 1511.300 ; - RECT 125.870 0.700 126.150 1511.300 ; - RECT 128.110 0.700 128.390 1511.300 ; - RECT 130.350 0.700 130.630 1511.300 ; - RECT 132.590 0.700 132.870 1511.300 ; - RECT 134.830 0.700 135.110 1511.300 ; - RECT 137.070 0.700 137.350 1511.300 ; - RECT 139.310 0.700 139.590 1511.300 ; - RECT 141.550 0.700 141.830 1511.300 ; - RECT 143.790 0.700 144.070 1511.300 ; - RECT 146.030 0.700 146.310 1511.300 ; - RECT 148.270 0.700 148.550 1511.300 ; - RECT 150.510 0.700 150.790 1511.300 ; - RECT 152.750 0.700 153.030 1511.300 ; - RECT 154.990 0.700 155.270 1511.300 ; - RECT 157.230 0.700 157.510 1511.300 ; - RECT 159.470 0.700 159.750 1511.300 ; - RECT 161.710 0.700 161.990 1511.300 ; - RECT 163.950 0.700 164.230 1511.300 ; - RECT 166.190 0.700 166.470 1511.300 ; - RECT 168.430 0.700 168.710 1511.300 ; - RECT 170.670 0.700 170.950 1511.300 ; - RECT 172.910 0.700 173.190 1511.300 ; - RECT 175.150 0.700 175.430 1511.300 ; - RECT 177.390 0.700 177.670 1511.300 ; - RECT 179.630 0.700 179.910 1511.300 ; - RECT 181.870 0.700 182.150 1511.300 ; - RECT 184.110 0.700 184.390 1511.300 ; - RECT 186.350 0.700 186.630 1511.300 ; - RECT 188.590 0.700 188.870 1511.300 ; - RECT 190.830 0.700 191.110 1511.300 ; - RECT 193.070 0.700 193.350 1511.300 ; - RECT 195.310 0.700 195.590 1511.300 ; - RECT 197.550 0.700 197.830 1511.300 ; - RECT 199.790 0.700 200.070 1511.300 ; - RECT 202.030 0.700 202.310 1511.300 ; - RECT 204.270 0.700 204.550 1511.300 ; - RECT 206.510 0.700 206.790 1511.300 ; - RECT 208.750 0.700 209.030 1511.300 ; - RECT 210.990 0.700 211.270 1511.300 ; - RECT 213.230 0.700 213.510 1511.300 ; - RECT 215.470 0.700 215.750 1511.300 ; - RECT 217.710 0.700 217.990 1511.300 ; - RECT 219.950 0.700 220.230 1511.300 ; - RECT 222.190 0.700 222.470 1511.300 ; - RECT 224.430 0.700 224.710 1511.300 ; - RECT 226.670 0.700 226.950 1511.300 ; - RECT 228.910 0.700 229.190 1511.300 ; - RECT 231.150 0.700 231.430 1511.300 ; - RECT 233.390 0.700 233.670 1511.300 ; - RECT 235.630 0.700 235.910 1511.300 ; - RECT 237.870 0.700 238.150 1511.300 ; - RECT 240.110 0.700 240.390 1511.300 ; - RECT 242.350 0.700 242.630 1511.300 ; - RECT 244.590 0.700 244.870 1511.300 ; - RECT 246.830 0.700 247.110 1511.300 ; - RECT 249.070 0.700 249.350 1511.300 ; - RECT 251.310 0.700 251.590 1511.300 ; - RECT 253.550 0.700 253.830 1511.300 ; - RECT 255.790 0.700 256.070 1511.300 ; - RECT 258.030 0.700 258.310 1511.300 ; - RECT 260.270 0.700 260.550 1511.300 ; - RECT 262.510 0.700 262.790 1511.300 ; - RECT 264.750 0.700 265.030 1511.300 ; - RECT 266.990 0.700 267.270 1511.300 ; - RECT 269.230 0.700 269.510 1511.300 ; - RECT 271.470 0.700 271.750 1511.300 ; - RECT 273.710 0.700 273.990 1511.300 ; - RECT 275.950 0.700 276.230 1511.300 ; - RECT 278.190 0.700 278.470 1511.300 ; - RECT 280.430 0.700 280.710 1511.300 ; - RECT 282.670 0.700 282.950 1511.300 ; - RECT 284.910 0.700 285.190 1511.300 ; - RECT 287.150 0.700 287.430 1511.300 ; - RECT 289.390 0.700 289.670 1511.300 ; - RECT 291.630 0.700 291.910 1511.300 ; - RECT 293.870 0.700 294.150 1511.300 ; - RECT 296.110 0.700 296.390 1511.300 ; - RECT 298.350 0.700 298.630 1511.300 ; - RECT 300.590 0.700 300.870 1511.300 ; - RECT 302.830 0.700 303.110 1511.300 ; - RECT 305.070 0.700 305.350 1511.300 ; - RECT 307.310 0.700 307.590 1511.300 ; - RECT 309.550 0.700 309.830 1511.300 ; - RECT 311.790 0.700 312.070 1511.300 ; - RECT 314.030 0.700 314.310 1511.300 ; - RECT 316.270 0.700 316.550 1511.300 ; - RECT 318.510 0.700 318.790 1511.300 ; - RECT 320.750 0.700 321.030 1511.300 ; - RECT 322.990 0.700 323.270 1511.300 ; - RECT 325.230 0.700 325.510 1511.300 ; - RECT 327.470 0.700 327.750 1511.300 ; - RECT 329.710 0.700 329.990 1511.300 ; - RECT 331.950 0.700 332.230 1511.300 ; - RECT 334.190 0.700 334.470 1511.300 ; - RECT 336.430 0.700 336.710 1511.300 ; - RECT 338.670 0.700 338.950 1511.300 ; - RECT 340.910 0.700 341.190 1511.300 ; - RECT 343.150 0.700 343.430 1511.300 ; - RECT 345.390 0.700 345.670 1511.300 ; - RECT 347.630 0.700 347.910 1511.300 ; - RECT 349.870 0.700 350.150 1511.300 ; - RECT 352.110 0.700 352.390 1511.300 ; - RECT 354.350 0.700 354.630 1511.300 ; - RECT 356.590 0.700 356.870 1511.300 ; - RECT 358.830 0.700 359.110 1511.300 ; - RECT 361.070 0.700 361.350 1511.300 ; - RECT 363.310 0.700 363.590 1511.300 ; - RECT 365.550 0.700 365.830 1511.300 ; - RECT 367.790 0.700 368.070 1511.300 ; - RECT 370.030 0.700 370.310 1511.300 ; - RECT 372.270 0.700 372.550 1511.300 ; - RECT 374.510 0.700 374.790 1511.300 ; - RECT 376.750 0.700 377.030 1511.300 ; - RECT 378.990 0.700 379.270 1511.300 ; - RECT 381.230 0.700 381.510 1511.300 ; - RECT 383.470 0.700 383.750 1511.300 ; - RECT 385.710 0.700 385.990 1511.300 ; - RECT 387.950 0.700 388.230 1511.300 ; - RECT 390.190 0.700 390.470 1511.300 ; - RECT 392.430 0.700 392.710 1511.300 ; - RECT 394.670 0.700 394.950 1511.300 ; - RECT 396.910 0.700 397.190 1511.300 ; - RECT 399.150 0.700 399.430 1511.300 ; - RECT 401.390 0.700 401.670 1511.300 ; - RECT 403.630 0.700 403.910 1511.300 ; - RECT 405.870 0.700 406.150 1511.300 ; - RECT 408.110 0.700 408.390 1511.300 ; - RECT 410.350 0.700 410.630 1511.300 ; - RECT 412.590 0.700 412.870 1511.300 ; - RECT 414.830 0.700 415.110 1511.300 ; - RECT 417.070 0.700 417.350 1511.300 ; - RECT 419.310 0.700 419.590 1511.300 ; - RECT 421.550 0.700 421.830 1511.300 ; - RECT 423.790 0.700 424.070 1511.300 ; - RECT 426.030 0.700 426.310 1511.300 ; - RECT 428.270 0.700 428.550 1511.300 ; - RECT 430.510 0.700 430.790 1511.300 ; - RECT 432.750 0.700 433.030 1511.300 ; - RECT 434.990 0.700 435.270 1511.300 ; - RECT 437.230 0.700 437.510 1511.300 ; - RECT 439.470 0.700 439.750 1511.300 ; - RECT 441.710 0.700 441.990 1511.300 ; - RECT 443.950 0.700 444.230 1511.300 ; - RECT 446.190 0.700 446.470 1511.300 ; - RECT 448.430 0.700 448.710 1511.300 ; - RECT 450.670 0.700 450.950 1511.300 ; - RECT 452.910 0.700 453.190 1511.300 ; - RECT 455.150 0.700 455.430 1511.300 ; - RECT 457.390 0.700 457.670 1511.300 ; - RECT 459.630 0.700 459.910 1511.300 ; - RECT 461.870 0.700 462.150 1511.300 ; - RECT 464.110 0.700 464.390 1511.300 ; - RECT 466.350 0.700 466.630 1511.300 ; - RECT 468.590 0.700 468.870 1511.300 ; - RECT 470.830 0.700 471.110 1511.300 ; - RECT 473.070 0.700 473.350 1511.300 ; - RECT 475.310 0.700 475.590 1511.300 ; - RECT 477.550 0.700 477.830 1511.300 ; - RECT 479.790 0.700 480.070 1511.300 ; - RECT 482.030 0.700 482.310 1511.300 ; - RECT 484.270 0.700 484.550 1511.300 ; - RECT 486.510 0.700 486.790 1511.300 ; - RECT 488.750 0.700 489.030 1511.300 ; - RECT 490.990 0.700 491.270 1511.300 ; - RECT 493.230 0.700 493.510 1511.300 ; - RECT 495.470 0.700 495.750 1511.300 ; - RECT 497.710 0.700 497.990 1511.300 ; - RECT 499.950 0.700 500.230 1511.300 ; - RECT 502.190 0.700 502.470 1511.300 ; - RECT 504.430 0.700 504.710 1511.300 ; - RECT 506.670 0.700 506.950 1511.300 ; - RECT 508.910 0.700 509.190 1511.300 ; - RECT 511.150 0.700 511.430 1511.300 ; - RECT 513.390 0.700 513.670 1511.300 ; - RECT 515.630 0.700 515.910 1511.300 ; - RECT 517.870 0.700 518.150 1511.300 ; - RECT 520.110 0.700 520.390 1511.300 ; - RECT 522.350 0.700 522.630 1511.300 ; - RECT 524.590 0.700 524.870 1511.300 ; - RECT 526.830 0.700 527.110 1511.300 ; - RECT 529.070 0.700 529.350 1511.300 ; - RECT 531.310 0.700 531.590 1511.300 ; - RECT 533.550 0.700 533.830 1511.300 ; - RECT 535.790 0.700 536.070 1511.300 ; - RECT 538.030 0.700 538.310 1511.300 ; - RECT 540.270 0.700 540.550 1511.300 ; - RECT 542.510 0.700 542.790 1511.300 ; - RECT 544.750 0.700 545.030 1511.300 ; - RECT 546.990 0.700 547.270 1511.300 ; - RECT 549.230 0.700 549.510 1511.300 ; - RECT 551.470 0.700 551.750 1511.300 ; - RECT 553.710 0.700 553.990 1511.300 ; - RECT 555.950 0.700 556.230 1511.300 ; - RECT 558.190 0.700 558.470 1511.300 ; - RECT 560.430 0.700 560.710 1511.300 ; - RECT 562.670 0.700 562.950 1511.300 ; - RECT 564.910 0.700 565.190 1511.300 ; - RECT 567.150 0.700 567.430 1511.300 ; - RECT 569.390 0.700 569.670 1511.300 ; - RECT 571.630 0.700 571.910 1511.300 ; - RECT 573.870 0.700 574.150 1511.300 ; - RECT 576.110 0.700 576.390 1511.300 ; - RECT 578.350 0.700 578.630 1511.300 ; - RECT 580.590 0.700 580.870 1511.300 ; - RECT 582.830 0.700 583.110 1511.300 ; - RECT 585.070 0.700 585.350 1511.300 ; - RECT 587.310 0.700 587.590 1511.300 ; - RECT 589.550 0.700 589.830 1511.300 ; - RECT 591.790 0.700 592.070 1511.300 ; - RECT 594.030 0.700 594.310 1511.300 ; - RECT 596.270 0.700 596.550 1511.300 ; - RECT 598.510 0.700 598.790 1511.300 ; - RECT 600.750 0.700 601.030 1511.300 ; - RECT 602.990 0.700 603.270 1511.300 ; - RECT 605.230 0.700 605.510 1511.300 ; - RECT 607.470 0.700 607.750 1511.300 ; - RECT 609.710 0.700 609.990 1511.300 ; - RECT 611.950 0.700 612.230 1511.300 ; - RECT 614.190 0.700 614.470 1511.300 ; - RECT 616.430 0.700 616.710 1511.300 ; - RECT 618.670 0.700 618.950 1511.300 ; - RECT 620.910 0.700 621.190 1511.300 ; - RECT 623.150 0.700 623.430 1511.300 ; - RECT 625.390 0.700 625.670 1511.300 ; - RECT 627.630 0.700 627.910 1511.300 ; - RECT 629.870 0.700 630.150 1511.300 ; - RECT 632.110 0.700 632.390 1511.300 ; - RECT 634.350 0.700 634.630 1511.300 ; - RECT 636.590 0.700 636.870 1511.300 ; - RECT 638.830 0.700 639.110 1511.300 ; - RECT 641.070 0.700 641.350 1511.300 ; - RECT 643.310 0.700 643.590 1511.300 ; - RECT 645.550 0.700 645.830 1511.300 ; - RECT 647.790 0.700 648.070 1511.300 ; - RECT 650.030 0.700 650.310 1511.300 ; - RECT 652.270 0.700 652.550 1511.300 ; - RECT 654.510 0.700 654.790 1511.300 ; - RECT 656.750 0.700 657.030 1511.300 ; - RECT 658.990 0.700 659.270 1511.300 ; - RECT 661.230 0.700 661.510 1511.300 ; - RECT 663.470 0.700 663.750 1511.300 ; - RECT 665.710 0.700 665.990 1511.300 ; - RECT 667.950 0.700 668.230 1511.300 ; - RECT 670.190 0.700 670.470 1511.300 ; - RECT 672.430 0.700 672.710 1511.300 ; - RECT 674.670 0.700 674.950 1511.300 ; - RECT 676.910 0.700 677.190 1511.300 ; - RECT 679.150 0.700 679.430 1511.300 ; - RECT 681.390 0.700 681.670 1511.300 ; - RECT 683.630 0.700 683.910 1511.300 ; - RECT 685.870 0.700 686.150 1511.300 ; - RECT 688.110 0.700 688.390 1511.300 ; - RECT 690.350 0.700 690.630 1511.300 ; - RECT 692.590 0.700 692.870 1511.300 ; - RECT 694.830 0.700 695.110 1511.300 ; - RECT 697.070 0.700 697.350 1511.300 ; - RECT 699.310 0.700 699.590 1511.300 ; - RECT 701.550 0.700 701.830 1511.300 ; - RECT 703.790 0.700 704.070 1511.300 ; - RECT 706.030 0.700 706.310 1511.300 ; - RECT 708.270 0.700 708.550 1511.300 ; - RECT 710.510 0.700 710.790 1511.300 ; - RECT 712.750 0.700 713.030 1511.300 ; - RECT 714.990 0.700 715.270 1511.300 ; - RECT 717.230 0.700 717.510 1511.300 ; - RECT 719.470 0.700 719.750 1511.300 ; - RECT 721.710 0.700 721.990 1511.300 ; - RECT 723.950 0.700 724.230 1511.300 ; - RECT 726.190 0.700 726.470 1511.300 ; - RECT 728.430 0.700 728.710 1511.300 ; - RECT 730.670 0.700 730.950 1511.300 ; - RECT 732.910 0.700 733.190 1511.300 ; - RECT 735.150 0.700 735.430 1511.300 ; - RECT 737.390 0.700 737.670 1511.300 ; - RECT 739.630 0.700 739.910 1511.300 ; - RECT 741.870 0.700 742.150 1511.300 ; - RECT 744.110 0.700 744.390 1511.300 ; - RECT 746.350 0.700 746.630 1511.300 ; - RECT 748.590 0.700 748.870 1511.300 ; - RECT 750.830 0.700 751.110 1511.300 ; - RECT 753.070 0.700 753.350 1511.300 ; - RECT 755.310 0.700 755.590 1511.300 ; - RECT 757.550 0.700 757.830 1511.300 ; - RECT 759.790 0.700 760.070 1511.300 ; - RECT 762.030 0.700 762.310 1511.300 ; - RECT 764.270 0.700 764.550 1511.300 ; - RECT 766.510 0.700 766.790 1511.300 ; - RECT 768.750 0.700 769.030 1511.300 ; - RECT 770.990 0.700 771.270 1511.300 ; - RECT 773.230 0.700 773.510 1511.300 ; - RECT 775.470 0.700 775.750 1511.300 ; - RECT 777.710 0.700 777.990 1511.300 ; - RECT 779.950 0.700 780.230 1511.300 ; - RECT 782.190 0.700 782.470 1511.300 ; - RECT 784.430 0.700 784.710 1511.300 ; - RECT 786.670 0.700 786.950 1511.300 ; - RECT 788.910 0.700 789.190 1511.300 ; - RECT 791.150 0.700 791.430 1511.300 ; - RECT 793.390 0.700 793.670 1511.300 ; - RECT 795.630 0.700 795.910 1511.300 ; - RECT 797.870 0.700 798.150 1511.300 ; - RECT 800.110 0.700 800.390 1511.300 ; - RECT 802.350 0.700 802.630 1511.300 ; - RECT 804.590 0.700 804.870 1511.300 ; - RECT 806.830 0.700 807.110 1511.300 ; - RECT 809.070 0.700 809.350 1511.300 ; - RECT 811.310 0.700 811.590 1511.300 ; - RECT 813.550 0.700 813.830 1511.300 ; - RECT 815.790 0.700 816.070 1511.300 ; - RECT 818.030 0.700 818.310 1511.300 ; - RECT 820.270 0.700 820.550 1511.300 ; - RECT 822.510 0.700 822.790 1511.300 ; - RECT 824.750 0.700 825.030 1511.300 ; - RECT 826.990 0.700 827.270 1511.300 ; - RECT 829.230 0.700 829.510 1511.300 ; - RECT 831.470 0.700 831.750 1511.300 ; - RECT 833.710 0.700 833.990 1511.300 ; - RECT 835.950 0.700 836.230 1511.300 ; - RECT 838.190 0.700 838.470 1511.300 ; - RECT 840.430 0.700 840.710 1511.300 ; - RECT 842.670 0.700 842.950 1511.300 ; - RECT 844.910 0.700 845.190 1511.300 ; - RECT 847.150 0.700 847.430 1511.300 ; - RECT 849.390 0.700 849.670 1511.300 ; - RECT 851.630 0.700 851.910 1511.300 ; - RECT 853.870 0.700 854.150 1511.300 ; - RECT 856.110 0.700 856.390 1511.300 ; - RECT 858.350 0.700 858.630 1511.300 ; - RECT 860.590 0.700 860.870 1511.300 ; - RECT 862.830 0.700 863.110 1511.300 ; - RECT 865.070 0.700 865.350 1511.300 ; - RECT 867.310 0.700 867.590 1511.300 ; - RECT 869.550 0.700 869.830 1511.300 ; - RECT 871.790 0.700 872.070 1511.300 ; - RECT 874.030 0.700 874.310 1511.300 ; - RECT 876.270 0.700 876.550 1511.300 ; - RECT 878.510 0.700 878.790 1511.300 ; - RECT 880.750 0.700 881.030 1511.300 ; - RECT 882.990 0.700 883.270 1511.300 ; - RECT 885.230 0.700 885.510 1511.300 ; - RECT 887.470 0.700 887.750 1511.300 ; - RECT 889.710 0.700 889.990 1511.300 ; - RECT 891.950 0.700 892.230 1511.300 ; - RECT 894.190 0.700 894.470 1511.300 ; - RECT 896.430 0.700 896.710 1511.300 ; - RECT 898.670 0.700 898.950 1511.300 ; - RECT 900.910 0.700 901.190 1511.300 ; - RECT 903.150 0.700 903.430 1511.300 ; - RECT 905.390 0.700 905.670 1511.300 ; - RECT 907.630 0.700 907.910 1511.300 ; - RECT 909.870 0.700 910.150 1511.300 ; - RECT 912.110 0.700 912.390 1511.300 ; - RECT 914.350 0.700 914.630 1511.300 ; - RECT 916.590 0.700 916.870 1511.300 ; - RECT 918.830 0.700 919.110 1511.300 ; - RECT 921.070 0.700 921.350 1511.300 ; - RECT 923.310 0.700 923.590 1511.300 ; - RECT 925.550 0.700 925.830 1511.300 ; - RECT 927.790 0.700 928.070 1511.300 ; - RECT 930.030 0.700 930.310 1511.300 ; - RECT 932.270 0.700 932.550 1511.300 ; - RECT 934.510 0.700 934.790 1511.300 ; - RECT 936.750 0.700 937.030 1511.300 ; - RECT 938.990 0.700 939.270 1511.300 ; - RECT 941.230 0.700 941.510 1511.300 ; - RECT 943.470 0.700 943.750 1511.300 ; - RECT 945.710 0.700 945.990 1511.300 ; - RECT 947.950 0.700 948.230 1511.300 ; - RECT 950.190 0.700 950.470 1511.300 ; - RECT 952.430 0.700 952.710 1511.300 ; - RECT 954.670 0.700 954.950 1511.300 ; - RECT 956.910 0.700 957.190 1511.300 ; - RECT 959.150 0.700 959.430 1511.300 ; - RECT 961.390 0.700 961.670 1511.300 ; - RECT 963.630 0.700 963.910 1511.300 ; - RECT 965.870 0.700 966.150 1511.300 ; - RECT 968.110 0.700 968.390 1511.300 ; - RECT 970.350 0.700 970.630 1511.300 ; - RECT 972.590 0.700 972.870 1511.300 ; - RECT 974.830 0.700 975.110 1511.300 ; - RECT 977.070 0.700 977.350 1511.300 ; - RECT 979.310 0.700 979.590 1511.300 ; - RECT 981.550 0.700 981.830 1511.300 ; - RECT 983.790 0.700 984.070 1511.300 ; - RECT 986.030 0.700 986.310 1511.300 ; - RECT 988.270 0.700 988.550 1511.300 ; - RECT 990.510 0.700 990.790 1511.300 ; - RECT 992.750 0.700 993.030 1511.300 ; - RECT 994.990 0.700 995.270 1511.300 ; - RECT 997.230 0.700 997.510 1511.300 ; - RECT 999.470 0.700 999.750 1511.300 ; - RECT 1001.710 0.700 1001.990 1511.300 ; - RECT 1003.950 0.700 1004.230 1511.300 ; - RECT 1006.190 0.700 1006.470 1511.300 ; - RECT 1008.430 0.700 1008.710 1511.300 ; - RECT 1010.670 0.700 1010.950 1511.300 ; - RECT 1012.910 0.700 1013.190 1511.300 ; - RECT 1015.150 0.700 1015.430 1511.300 ; - RECT 1017.390 0.700 1017.670 1511.300 ; - RECT 1019.630 0.700 1019.910 1511.300 ; - RECT 1021.870 0.700 1022.150 1511.300 ; - RECT 1024.110 0.700 1024.390 1511.300 ; - RECT 1026.350 0.700 1026.630 1511.300 ; - RECT 1028.590 0.700 1028.870 1511.300 ; - RECT 1030.830 0.700 1031.110 1511.300 ; - RECT 1033.070 0.700 1033.350 1511.300 ; - RECT 1035.310 0.700 1035.590 1511.300 ; - RECT 1037.550 0.700 1037.830 1511.300 ; - RECT 1039.790 0.700 1040.070 1511.300 ; - RECT 1042.030 0.700 1042.310 1511.300 ; - RECT 1044.270 0.700 1044.550 1511.300 ; - RECT 1046.510 0.700 1046.790 1511.300 ; - RECT 1048.750 0.700 1049.030 1511.300 ; - RECT 1050.990 0.700 1051.270 1511.300 ; - RECT 1053.230 0.700 1053.510 1511.300 ; - RECT 1055.470 0.700 1055.750 1511.300 ; - RECT 1057.710 0.700 1057.990 1511.300 ; - RECT 1059.950 0.700 1060.230 1511.300 ; - RECT 1062.190 0.700 1062.470 1511.300 ; - RECT 1064.430 0.700 1064.710 1511.300 ; - RECT 1066.670 0.700 1066.950 1511.300 ; - RECT 1068.910 0.700 1069.190 1511.300 ; - RECT 1071.150 0.700 1071.430 1511.300 ; - RECT 1073.390 0.700 1073.670 1511.300 ; - RECT 1075.630 0.700 1075.910 1511.300 ; - RECT 1077.870 0.700 1078.150 1511.300 ; - RECT 1080.110 0.700 1080.390 1511.300 ; - RECT 1082.350 0.700 1082.630 1511.300 ; - RECT 1084.590 0.700 1084.870 1511.300 ; - RECT 1086.830 0.700 1087.110 1511.300 ; - RECT 1089.070 0.700 1089.350 1511.300 ; - RECT 1091.310 0.700 1091.590 1511.300 ; - RECT 1093.550 0.700 1093.830 1511.300 ; - RECT 1095.790 0.700 1096.070 1511.300 ; - RECT 1098.030 0.700 1098.310 1511.300 ; - RECT 1100.270 0.700 1100.550 1511.300 ; - RECT 1102.510 0.700 1102.790 1511.300 ; - RECT 1104.750 0.700 1105.030 1511.300 ; - RECT 1106.990 0.700 1107.270 1511.300 ; - RECT 1109.230 0.700 1109.510 1511.300 ; - RECT 1111.470 0.700 1111.750 1511.300 ; - RECT 1113.710 0.700 1113.990 1511.300 ; - RECT 1115.950 0.700 1116.230 1511.300 ; - RECT 1118.190 0.700 1118.470 1511.300 ; - RECT 1120.430 0.700 1120.710 1511.300 ; - RECT 1122.670 0.700 1122.950 1511.300 ; - RECT 1124.910 0.700 1125.190 1511.300 ; - RECT 1127.150 0.700 1127.430 1511.300 ; - RECT 1129.390 0.700 1129.670 1511.300 ; - RECT 1131.630 0.700 1131.910 1511.300 ; - RECT 1133.870 0.700 1134.150 1511.300 ; - RECT 1136.110 0.700 1136.390 1511.300 ; - RECT 1138.350 0.700 1138.630 1511.300 ; - RECT 1140.590 0.700 1140.870 1511.300 ; - RECT 1142.830 0.700 1143.110 1511.300 ; - RECT 1145.070 0.700 1145.350 1511.300 ; - RECT 1147.310 0.700 1147.590 1511.300 ; - RECT 1149.550 0.700 1149.830 1511.300 ; - RECT 1151.790 0.700 1152.070 1511.300 ; - RECT 1154.030 0.700 1154.310 1511.300 ; - RECT 1156.270 0.700 1156.550 1511.300 ; - RECT 1158.510 0.700 1158.790 1511.300 ; - RECT 1160.750 0.700 1161.030 1511.300 ; - RECT 1162.990 0.700 1163.270 1511.300 ; - RECT 1165.230 0.700 1165.510 1511.300 ; - RECT 1167.470 0.700 1167.750 1511.300 ; - RECT 1169.710 0.700 1169.990 1511.300 ; - RECT 1171.950 0.700 1172.230 1511.300 ; - RECT 1174.190 0.700 1174.470 1511.300 ; - RECT 1176.430 0.700 1176.710 1511.300 ; - RECT 1178.670 0.700 1178.950 1511.300 ; - RECT 1180.910 0.700 1181.190 1511.300 ; - RECT 1183.150 0.700 1183.430 1511.300 ; - RECT 1185.390 0.700 1185.670 1511.300 ; - RECT 1187.630 0.700 1187.910 1511.300 ; - RECT 1189.870 0.700 1190.150 1511.300 ; - RECT 1192.110 0.700 1192.390 1511.300 ; - RECT 1194.350 0.700 1194.630 1511.300 ; - RECT 1196.590 0.700 1196.870 1511.300 ; - RECT 1198.830 0.700 1199.110 1511.300 ; - RECT 1201.070 0.700 1201.350 1511.300 ; - RECT 1203.310 0.700 1203.590 1511.300 ; - RECT 1205.550 0.700 1205.830 1511.300 ; - RECT 1207.790 0.700 1208.070 1511.300 ; - RECT 1210.030 0.700 1210.310 1511.300 ; - RECT 1212.270 0.700 1212.550 1511.300 ; - RECT 1214.510 0.700 1214.790 1511.300 ; - RECT 1216.750 0.700 1217.030 1511.300 ; - RECT 1218.990 0.700 1219.270 1511.300 ; - RECT 1221.230 0.700 1221.510 1511.300 ; - RECT 1223.470 0.700 1223.750 1511.300 ; - RECT 1225.710 0.700 1225.990 1511.300 ; - RECT 1227.950 0.700 1228.230 1511.300 ; - RECT 1230.190 0.700 1230.470 1511.300 ; - RECT 1232.430 0.700 1232.710 1511.300 ; - RECT 1234.670 0.700 1234.950 1511.300 ; - RECT 1236.910 0.700 1237.190 1511.300 ; - RECT 1239.150 0.700 1239.430 1511.300 ; - RECT 1241.390 0.700 1241.670 1511.300 ; - RECT 1243.630 0.700 1243.910 1511.300 ; - RECT 1245.870 0.700 1246.150 1511.300 ; - RECT 1248.110 0.700 1248.390 1511.300 ; - RECT 1250.350 0.700 1250.630 1511.300 ; - RECT 1252.590 0.700 1252.870 1511.300 ; - RECT 1254.830 0.700 1255.110 1511.300 ; - RECT 1257.070 0.700 1257.350 1511.300 ; - RECT 1259.310 0.700 1259.590 1511.300 ; - RECT 1261.550 0.700 1261.830 1511.300 ; - RECT 1263.790 0.700 1264.070 1511.300 ; - RECT 1266.030 0.700 1266.310 1511.300 ; - RECT 1268.270 0.700 1268.550 1511.300 ; - RECT 1270.510 0.700 1270.790 1511.300 ; - RECT 1272.750 0.700 1273.030 1511.300 ; - RECT 1274.990 0.700 1275.270 1511.300 ; - RECT 1277.230 0.700 1277.510 1511.300 ; - RECT 1279.470 0.700 1279.750 1511.300 ; - RECT 1281.710 0.700 1281.990 1511.300 ; - RECT 1283.950 0.700 1284.230 1511.300 ; - RECT 1286.190 0.700 1286.470 1511.300 ; - RECT 1288.430 0.700 1288.710 1511.300 ; - RECT 1290.670 0.700 1290.950 1511.300 ; - RECT 1292.910 0.700 1293.190 1511.300 ; - RECT 1295.150 0.700 1295.430 1511.300 ; - RECT 1297.390 0.700 1297.670 1511.300 ; - RECT 1299.630 0.700 1299.910 1511.300 ; - RECT 1301.870 0.700 1302.150 1511.300 ; - RECT 1304.110 0.700 1304.390 1511.300 ; - RECT 1306.350 0.700 1306.630 1511.300 ; - RECT 1308.590 0.700 1308.870 1511.300 ; - RECT 1310.830 0.700 1311.110 1511.300 ; - RECT 1313.070 0.700 1313.350 1511.300 ; - RECT 1315.310 0.700 1315.590 1511.300 ; - RECT 1317.550 0.700 1317.830 1511.300 ; - RECT 1319.790 0.700 1320.070 1511.300 ; - RECT 1322.030 0.700 1322.310 1511.300 ; - RECT 1324.270 0.700 1324.550 1511.300 ; - RECT 1326.510 0.700 1326.790 1511.300 ; - RECT 1328.750 0.700 1329.030 1511.300 ; - RECT 1330.990 0.700 1331.270 1511.300 ; - RECT 1333.230 0.700 1333.510 1511.300 ; - RECT 1335.470 0.700 1335.750 1511.300 ; - RECT 1337.710 0.700 1337.990 1511.300 ; - RECT 1339.950 0.700 1340.230 1511.300 ; - RECT 1342.190 0.700 1342.470 1511.300 ; - RECT 1344.430 0.700 1344.710 1511.300 ; - RECT 1346.670 0.700 1346.950 1511.300 ; - RECT 1348.910 0.700 1349.190 1511.300 ; - RECT 1351.150 0.700 1351.430 1511.300 ; - RECT 1353.390 0.700 1353.670 1511.300 ; - RECT 1355.630 0.700 1355.910 1511.300 ; - RECT 1357.870 0.700 1358.150 1511.300 ; - RECT 1360.110 0.700 1360.390 1511.300 ; - RECT 1362.350 0.700 1362.630 1511.300 ; - RECT 1364.590 0.700 1364.870 1511.300 ; - RECT 1366.830 0.700 1367.110 1511.300 ; - RECT 1369.070 0.700 1369.350 1511.300 ; - RECT 1371.310 0.700 1371.590 1511.300 ; - RECT 1373.550 0.700 1373.830 1511.300 ; - RECT 1375.790 0.700 1376.070 1511.300 ; - RECT 1378.030 0.700 1378.310 1511.300 ; - RECT 1380.270 0.700 1380.550 1511.300 ; - RECT 1382.510 0.700 1382.790 1511.300 ; - RECT 1384.750 0.700 1385.030 1511.300 ; - RECT 1386.990 0.700 1387.270 1511.300 ; - RECT 1389.230 0.700 1389.510 1511.300 ; - RECT 1391.470 0.700 1391.750 1511.300 ; - RECT 1393.710 0.700 1393.990 1511.300 ; - RECT 1395.950 0.700 1396.230 1511.300 ; - RECT 1398.190 0.700 1398.470 1511.300 ; - RECT 1400.430 0.700 1400.710 1511.300 ; - RECT 1402.670 0.700 1402.950 1511.300 ; - RECT 1404.910 0.700 1405.190 1511.300 ; - RECT 1407.150 0.700 1407.430 1511.300 ; - RECT 1409.390 0.700 1409.670 1511.300 ; - RECT 1411.630 0.700 1411.910 1511.300 ; - RECT 1413.870 0.700 1414.150 1511.300 ; - RECT 1416.110 0.700 1416.390 1511.300 ; - RECT 1418.350 0.700 1418.630 1511.300 ; - RECT 1420.590 0.700 1420.870 1511.300 ; - RECT 1422.830 0.700 1423.110 1511.300 ; - RECT 1425.070 0.700 1425.350 1511.300 ; - RECT 1427.310 0.700 1427.590 1511.300 ; - RECT 1429.550 0.700 1429.830 1511.300 ; - RECT 1431.790 0.700 1432.070 1511.300 ; - RECT 1434.030 0.700 1434.310 1511.300 ; - RECT 1436.270 0.700 1436.550 1511.300 ; - RECT 1438.510 0.700 1438.790 1511.300 ; - RECT 1440.750 0.700 1441.030 1511.300 ; - RECT 1442.990 0.700 1443.270 1511.300 ; - RECT 1445.230 0.700 1445.510 1511.300 ; - RECT 1447.470 0.700 1447.750 1511.300 ; - RECT 1449.710 0.700 1449.990 1511.300 ; - RECT 1451.950 0.700 1452.230 1511.300 ; - RECT 1454.190 0.700 1454.470 1511.300 ; - RECT 1456.430 0.700 1456.710 1511.300 ; - RECT 1458.670 0.700 1458.950 1511.300 ; - RECT 1460.910 0.700 1461.190 1511.300 ; - RECT 1463.150 0.700 1463.430 1511.300 ; - RECT 1465.390 0.700 1465.670 1511.300 ; - RECT 1467.630 0.700 1467.910 1511.300 ; - RECT 1469.870 0.700 1470.150 1511.300 ; - RECT 1472.110 0.700 1472.390 1511.300 ; - RECT 1474.350 0.700 1474.630 1511.300 ; - RECT 1476.590 0.700 1476.870 1511.300 ; - RECT 1478.830 0.700 1479.110 1511.300 ; - RECT 1481.070 0.700 1481.350 1511.300 ; - RECT 1483.310 0.700 1483.590 1511.300 ; - RECT 1485.550 0.700 1485.830 1511.300 ; - RECT 1487.790 0.700 1488.070 1511.300 ; - RECT 1490.030 0.700 1490.310 1511.300 ; - RECT 1492.270 0.700 1492.550 1511.300 ; - RECT 1494.510 0.700 1494.790 1511.300 ; - RECT 1496.750 0.700 1497.030 1511.300 ; - RECT 1498.990 0.700 1499.270 1511.300 ; - RECT 1501.230 0.700 1501.510 1511.300 ; - RECT 1503.470 0.700 1503.750 1511.300 ; - RECT 1505.710 0.700 1505.990 1511.300 ; - RECT 1507.950 0.700 1508.230 1511.300 ; - RECT 1510.190 0.700 1510.470 1511.300 ; - RECT 1512.430 0.700 1512.710 1511.300 ; - RECT 1514.670 0.700 1514.950 1511.300 ; - RECT 1516.910 0.700 1517.190 1511.300 ; - RECT 1519.150 0.700 1519.430 1511.300 ; - RECT 1521.390 0.700 1521.670 1511.300 ; - RECT 1523.630 0.700 1523.910 1511.300 ; - RECT 1525.870 0.700 1526.150 1511.300 ; - RECT 1528.110 0.700 1528.390 1511.300 ; - RECT 1530.350 0.700 1530.630 1511.300 ; - RECT 1532.590 0.700 1532.870 1511.300 ; - RECT 1534.830 0.700 1535.110 1511.300 ; - RECT 1537.070 0.700 1537.350 1511.300 ; - RECT 1539.310 0.700 1539.590 1511.300 ; - RECT 1541.550 0.700 1541.830 1511.300 ; - RECT 1543.790 0.700 1544.070 1511.300 ; - RECT 1546.030 0.700 1546.310 1511.300 ; - RECT 1548.270 0.700 1548.550 1511.300 ; - RECT 1550.510 0.700 1550.790 1511.300 ; - RECT 1552.750 0.700 1553.030 1511.300 ; - RECT 1554.990 0.700 1555.270 1511.300 ; - RECT 1557.230 0.700 1557.510 1511.300 ; - RECT 1559.470 0.700 1559.750 1511.300 ; - RECT 1561.710 0.700 1561.990 1511.300 ; - RECT 1563.950 0.700 1564.230 1511.300 ; - RECT 1566.190 0.700 1566.470 1511.300 ; - RECT 1568.430 0.700 1568.710 1511.300 ; - RECT 1570.670 0.700 1570.950 1511.300 ; - RECT 1572.910 0.700 1573.190 1511.300 ; - RECT 1575.150 0.700 1575.430 1511.300 ; - RECT 1577.390 0.700 1577.670 1511.300 ; - RECT 1579.630 0.700 1579.910 1511.300 ; - RECT 1581.870 0.700 1582.150 1511.300 ; - RECT 1584.110 0.700 1584.390 1511.300 ; - RECT 1586.350 0.700 1586.630 1511.300 ; - RECT 1588.590 0.700 1588.870 1511.300 ; - RECT 1590.830 0.700 1591.110 1511.300 ; - RECT 1593.070 0.700 1593.350 1511.300 ; - RECT 1595.310 0.700 1595.590 1511.300 ; - RECT 1597.550 0.700 1597.830 1511.300 ; - RECT 1599.790 0.700 1600.070 1511.300 ; - RECT 1602.030 0.700 1602.310 1511.300 ; - RECT 1604.270 0.700 1604.550 1511.300 ; - RECT 1606.510 0.700 1606.790 1511.300 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 1609.300 1512.000 ; - LAYER metal2 ; - RECT 0 0 1609.300 1512.000 ; - LAYER metal3 ; - RECT 0 0 1609.300 1512.000 ; - LAYER metal4 ; - RECT 0 0 1609.300 1512.000 ; - LAYER OVERLAP ; - RECT 0 0 1609.300 1512.000 ; - END -END fakeram_512x2048_1r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef b/designs/nangate45/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef deleted file mode 100644 index dde4eb2..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lef/fakeram_512x256_1r1w.lef +++ /dev/null @@ -1,10057 +0,0 @@ -VERSION 5.7 ; -BUSBITCHARS "[]" ; -MACRO fakeram_512x256_1r1w - FOREIGN fakeram_512x256_1r1w 0 0 ; - SYMMETRY X Y R90 ; - SIZE 689.130 BY 767.200 ; - CLASS BLOCK ; - PIN w0_wd_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 0.805 0.140 0.875 ; - END - END w0_wd_in[0] - PIN w0_wd_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 6.405 0.140 6.475 ; - END - END w0_wd_in[1] - PIN w0_wd_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 12.005 0.140 12.075 ; - END - END w0_wd_in[2] - PIN w0_wd_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 17.605 0.140 17.675 ; - END - END w0_wd_in[3] - PIN w0_wd_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 23.205 0.140 23.275 ; - END - END w0_wd_in[4] - PIN w0_wd_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 28.805 0.140 28.875 ; - END - END w0_wd_in[5] - PIN w0_wd_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 34.405 0.140 34.475 ; - END - END w0_wd_in[6] - PIN w0_wd_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 40.005 0.140 40.075 ; - END - END w0_wd_in[7] - PIN w0_wd_in[8] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 45.605 0.140 45.675 ; - END - END w0_wd_in[8] - PIN w0_wd_in[9] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 51.205 0.140 51.275 ; - END - END w0_wd_in[9] - PIN w0_wd_in[10] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 56.805 0.140 56.875 ; - END - END w0_wd_in[10] - PIN w0_wd_in[11] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 62.405 0.140 62.475 ; - END - END w0_wd_in[11] - PIN w0_wd_in[12] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 68.005 0.140 68.075 ; - END - END w0_wd_in[12] - PIN w0_wd_in[13] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 73.605 0.140 73.675 ; - END - END w0_wd_in[13] - PIN w0_wd_in[14] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 79.205 0.140 79.275 ; - END - END w0_wd_in[14] - PIN w0_wd_in[15] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 84.805 0.140 84.875 ; - END - END w0_wd_in[15] - PIN w0_wd_in[16] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 90.405 0.140 90.475 ; - END - END w0_wd_in[16] - PIN w0_wd_in[17] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 96.005 0.140 96.075 ; - END - END w0_wd_in[17] - PIN w0_wd_in[18] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 101.605 0.140 101.675 ; - END - END w0_wd_in[18] - PIN w0_wd_in[19] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 107.205 0.140 107.275 ; - END - END w0_wd_in[19] - PIN w0_wd_in[20] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 112.805 0.140 112.875 ; - END - END w0_wd_in[20] - PIN w0_wd_in[21] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 118.405 0.140 118.475 ; - END - END w0_wd_in[21] - PIN w0_wd_in[22] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 124.005 0.140 124.075 ; - END - END w0_wd_in[22] - PIN w0_wd_in[23] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 129.605 0.140 129.675 ; - END - END w0_wd_in[23] - PIN w0_wd_in[24] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 135.205 0.140 135.275 ; - END - END w0_wd_in[24] - PIN w0_wd_in[25] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 140.805 0.140 140.875 ; - END - END w0_wd_in[25] - PIN w0_wd_in[26] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 146.405 0.140 146.475 ; - END - END w0_wd_in[26] - PIN w0_wd_in[27] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 152.005 0.140 152.075 ; - END - END w0_wd_in[27] - PIN w0_wd_in[28] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 157.605 0.140 157.675 ; - END - END w0_wd_in[28] - PIN w0_wd_in[29] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 163.205 0.140 163.275 ; - END - END w0_wd_in[29] - PIN w0_wd_in[30] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 168.805 0.140 168.875 ; - END - END w0_wd_in[30] - PIN w0_wd_in[31] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 174.405 0.140 174.475 ; - END - END w0_wd_in[31] - PIN w0_wd_in[32] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 180.005 0.140 180.075 ; - END - END w0_wd_in[32] - PIN w0_wd_in[33] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 185.605 0.140 185.675 ; - END - END w0_wd_in[33] - PIN w0_wd_in[34] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 191.205 0.140 191.275 ; - END - END w0_wd_in[34] - PIN w0_wd_in[35] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 196.805 0.140 196.875 ; - END - END w0_wd_in[35] - PIN w0_wd_in[36] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 202.405 0.140 202.475 ; - END - END w0_wd_in[36] - PIN w0_wd_in[37] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 208.005 0.140 208.075 ; - END - END w0_wd_in[37] - PIN w0_wd_in[38] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 213.605 0.140 213.675 ; - END - END w0_wd_in[38] - PIN w0_wd_in[39] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 219.205 0.140 219.275 ; - END - END w0_wd_in[39] - PIN w0_wd_in[40] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 224.805 0.140 224.875 ; - END - END w0_wd_in[40] - PIN w0_wd_in[41] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 230.405 0.140 230.475 ; - END - END w0_wd_in[41] - PIN w0_wd_in[42] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 236.005 0.140 236.075 ; - END - END w0_wd_in[42] - PIN w0_wd_in[43] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 241.605 0.140 241.675 ; - END - END w0_wd_in[43] - PIN w0_wd_in[44] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 247.205 0.140 247.275 ; - END - END w0_wd_in[44] - PIN w0_wd_in[45] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 252.805 0.140 252.875 ; - END - END w0_wd_in[45] - PIN w0_wd_in[46] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 258.405 0.140 258.475 ; - END - END w0_wd_in[46] - PIN w0_wd_in[47] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 264.005 0.140 264.075 ; - END - END w0_wd_in[47] - PIN w0_wd_in[48] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 269.605 0.140 269.675 ; - END - END w0_wd_in[48] - PIN w0_wd_in[49] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 275.205 0.140 275.275 ; - END - END w0_wd_in[49] - PIN w0_wd_in[50] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 280.805 0.140 280.875 ; - END - END w0_wd_in[50] - PIN w0_wd_in[51] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 286.405 0.140 286.475 ; - END - END w0_wd_in[51] - PIN w0_wd_in[52] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 292.005 0.140 292.075 ; - END - END w0_wd_in[52] - PIN w0_wd_in[53] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 297.605 0.140 297.675 ; - END - END w0_wd_in[53] - PIN w0_wd_in[54] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 303.205 0.140 303.275 ; - END - END w0_wd_in[54] - PIN w0_wd_in[55] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 308.805 0.140 308.875 ; - END - END w0_wd_in[55] - PIN w0_wd_in[56] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 314.405 0.140 314.475 ; - END - END w0_wd_in[56] - PIN w0_wd_in[57] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 320.005 0.140 320.075 ; - END - END w0_wd_in[57] - PIN w0_wd_in[58] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 325.605 0.140 325.675 ; - END - END w0_wd_in[58] - PIN w0_wd_in[59] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 331.205 0.140 331.275 ; - END - END w0_wd_in[59] - PIN w0_wd_in[60] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 336.805 0.140 336.875 ; - END - END w0_wd_in[60] - PIN w0_wd_in[61] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 342.405 0.140 342.475 ; - END - END w0_wd_in[61] - PIN w0_wd_in[62] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 348.005 0.140 348.075 ; - END - END w0_wd_in[62] - PIN w0_wd_in[63] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 353.605 0.140 353.675 ; - END - END w0_wd_in[63] - PIN w0_wd_in[64] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 359.205 0.140 359.275 ; - END - END w0_wd_in[64] - PIN w0_wd_in[65] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 364.805 0.140 364.875 ; - END - END w0_wd_in[65] - PIN w0_wd_in[66] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 370.405 0.140 370.475 ; - END - END w0_wd_in[66] - PIN w0_wd_in[67] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 376.005 0.140 376.075 ; - END - END w0_wd_in[67] - PIN w0_wd_in[68] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 381.605 0.140 381.675 ; - END - END w0_wd_in[68] - PIN w0_wd_in[69] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 387.205 0.140 387.275 ; - END - END w0_wd_in[69] - PIN w0_wd_in[70] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 392.805 0.140 392.875 ; - END - END w0_wd_in[70] - PIN w0_wd_in[71] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 398.405 0.140 398.475 ; - END - END w0_wd_in[71] - PIN w0_wd_in[72] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 404.005 0.140 404.075 ; - END - END w0_wd_in[72] - PIN w0_wd_in[73] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 409.605 0.140 409.675 ; - END - END w0_wd_in[73] - PIN w0_wd_in[74] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 415.205 0.140 415.275 ; - END - END w0_wd_in[74] - PIN w0_wd_in[75] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 420.805 0.140 420.875 ; - END - END w0_wd_in[75] - PIN w0_wd_in[76] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 426.405 0.140 426.475 ; - END - END w0_wd_in[76] - PIN w0_wd_in[77] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 432.005 0.140 432.075 ; - END - END w0_wd_in[77] - PIN w0_wd_in[78] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 437.605 0.140 437.675 ; - END - END w0_wd_in[78] - PIN w0_wd_in[79] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 443.205 0.140 443.275 ; - END - END w0_wd_in[79] - PIN w0_wd_in[80] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 448.805 0.140 448.875 ; - END - END w0_wd_in[80] - PIN w0_wd_in[81] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 454.405 0.140 454.475 ; - END - END w0_wd_in[81] - PIN w0_wd_in[82] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 460.005 0.140 460.075 ; - END - END w0_wd_in[82] - PIN w0_wd_in[83] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 465.605 0.140 465.675 ; - END - END w0_wd_in[83] - PIN w0_wd_in[84] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 471.205 0.140 471.275 ; - END - END w0_wd_in[84] - PIN w0_wd_in[85] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 476.805 0.140 476.875 ; - END - END w0_wd_in[85] - PIN w0_wd_in[86] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 482.405 0.140 482.475 ; - END - END w0_wd_in[86] - PIN w0_wd_in[87] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 488.005 0.140 488.075 ; - END - END w0_wd_in[87] - PIN w0_wd_in[88] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 493.605 0.140 493.675 ; - END - END w0_wd_in[88] - PIN w0_wd_in[89] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 499.205 0.140 499.275 ; - END - END w0_wd_in[89] - PIN w0_wd_in[90] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 504.805 0.140 504.875 ; - END - END w0_wd_in[90] - PIN w0_wd_in[91] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 510.405 0.140 510.475 ; - END - END w0_wd_in[91] - PIN w0_wd_in[92] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 516.005 0.140 516.075 ; - END - END w0_wd_in[92] - PIN w0_wd_in[93] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 521.605 0.140 521.675 ; - END - END w0_wd_in[93] - PIN w0_wd_in[94] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 527.205 0.140 527.275 ; - END - END w0_wd_in[94] - PIN w0_wd_in[95] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 532.805 0.140 532.875 ; - END - END w0_wd_in[95] - PIN w0_wd_in[96] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 538.405 0.140 538.475 ; - END - END w0_wd_in[96] - PIN w0_wd_in[97] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 544.005 0.140 544.075 ; - END - END w0_wd_in[97] - PIN w0_wd_in[98] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 549.605 0.140 549.675 ; - END - END w0_wd_in[98] - PIN w0_wd_in[99] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 555.205 0.140 555.275 ; - END - END w0_wd_in[99] - PIN w0_wd_in[100] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 560.805 0.140 560.875 ; - END - END w0_wd_in[100] - PIN w0_wd_in[101] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 566.405 0.140 566.475 ; - END - END w0_wd_in[101] - PIN w0_wd_in[102] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 572.005 0.140 572.075 ; - END - END w0_wd_in[102] - PIN w0_wd_in[103] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 577.605 0.140 577.675 ; - END - END w0_wd_in[103] - PIN w0_wd_in[104] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 583.205 0.140 583.275 ; - END - END w0_wd_in[104] - PIN w0_wd_in[105] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 588.805 0.140 588.875 ; - END - END w0_wd_in[105] - PIN w0_wd_in[106] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 594.405 0.140 594.475 ; - END - END w0_wd_in[106] - PIN w0_wd_in[107] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 600.005 0.140 600.075 ; - END - END w0_wd_in[107] - PIN w0_wd_in[108] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 605.605 0.140 605.675 ; - END - END w0_wd_in[108] - PIN w0_wd_in[109] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 611.205 0.140 611.275 ; - END - END w0_wd_in[109] - PIN w0_wd_in[110] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 616.805 0.140 616.875 ; - END - END w0_wd_in[110] - PIN w0_wd_in[111] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 622.405 0.140 622.475 ; - END - END w0_wd_in[111] - PIN w0_wd_in[112] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 628.005 0.140 628.075 ; - END - END w0_wd_in[112] - PIN w0_wd_in[113] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 633.605 0.140 633.675 ; - END - END w0_wd_in[113] - PIN w0_wd_in[114] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 639.205 0.140 639.275 ; - END - END w0_wd_in[114] - PIN w0_wd_in[115] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 644.805 0.140 644.875 ; - END - END w0_wd_in[115] - PIN w0_wd_in[116] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 650.405 0.140 650.475 ; - END - END w0_wd_in[116] - PIN w0_wd_in[117] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 656.005 0.140 656.075 ; - END - END w0_wd_in[117] - PIN w0_wd_in[118] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 661.605 0.140 661.675 ; - END - END w0_wd_in[118] - PIN w0_wd_in[119] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 667.205 0.140 667.275 ; - END - END w0_wd_in[119] - PIN w0_wd_in[120] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 672.805 0.140 672.875 ; - END - END w0_wd_in[120] - PIN w0_wd_in[121] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 678.405 0.140 678.475 ; - END - END w0_wd_in[121] - PIN w0_wd_in[122] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 684.005 0.140 684.075 ; - END - END w0_wd_in[122] - PIN w0_wd_in[123] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 689.605 0.140 689.675 ; - END - END w0_wd_in[123] - PIN w0_wd_in[124] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 695.205 0.140 695.275 ; - END - END w0_wd_in[124] - PIN w0_wd_in[125] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 700.805 0.140 700.875 ; - END - END w0_wd_in[125] - PIN w0_wd_in[126] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 706.405 0.140 706.475 ; - END - END w0_wd_in[126] - PIN w0_wd_in[127] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 712.005 0.140 712.075 ; - END - END w0_wd_in[127] - PIN w0_wd_in[128] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 0.805 689.130 0.875 ; - END - END w0_wd_in[128] - PIN w0_wd_in[129] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 6.405 689.130 6.475 ; - END - END w0_wd_in[129] - PIN w0_wd_in[130] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 12.005 689.130 12.075 ; - END - END w0_wd_in[130] - PIN w0_wd_in[131] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 17.605 689.130 17.675 ; - END - END w0_wd_in[131] - PIN w0_wd_in[132] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 23.205 689.130 23.275 ; - END - END w0_wd_in[132] - PIN w0_wd_in[133] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 28.805 689.130 28.875 ; - END - END w0_wd_in[133] - PIN w0_wd_in[134] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 34.405 689.130 34.475 ; - END - END w0_wd_in[134] - PIN w0_wd_in[135] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 40.005 689.130 40.075 ; - END - END w0_wd_in[135] - PIN w0_wd_in[136] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 45.605 689.130 45.675 ; - END - END w0_wd_in[136] - PIN w0_wd_in[137] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 51.205 689.130 51.275 ; - END - END w0_wd_in[137] - PIN w0_wd_in[138] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 56.805 689.130 56.875 ; - END - END w0_wd_in[138] - PIN w0_wd_in[139] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 62.405 689.130 62.475 ; - END - END w0_wd_in[139] - PIN w0_wd_in[140] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 68.005 689.130 68.075 ; - END - END w0_wd_in[140] - PIN w0_wd_in[141] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 73.605 689.130 73.675 ; - END - END w0_wd_in[141] - PIN w0_wd_in[142] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 79.205 689.130 79.275 ; - END - END w0_wd_in[142] - PIN w0_wd_in[143] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 84.805 689.130 84.875 ; - END - END w0_wd_in[143] - PIN w0_wd_in[144] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 90.405 689.130 90.475 ; - END - END w0_wd_in[144] - PIN w0_wd_in[145] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 96.005 689.130 96.075 ; - END - END w0_wd_in[145] - PIN w0_wd_in[146] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 101.605 689.130 101.675 ; - END - END w0_wd_in[146] - PIN w0_wd_in[147] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 107.205 689.130 107.275 ; - END - END w0_wd_in[147] - PIN w0_wd_in[148] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 112.805 689.130 112.875 ; - END - END w0_wd_in[148] - PIN w0_wd_in[149] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 118.405 689.130 118.475 ; - END - END w0_wd_in[149] - PIN w0_wd_in[150] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 124.005 689.130 124.075 ; - END - END w0_wd_in[150] - PIN w0_wd_in[151] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 129.605 689.130 129.675 ; - END - END w0_wd_in[151] - PIN w0_wd_in[152] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 135.205 689.130 135.275 ; - END - END w0_wd_in[152] - PIN w0_wd_in[153] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 140.805 689.130 140.875 ; - END - END w0_wd_in[153] - PIN w0_wd_in[154] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 146.405 689.130 146.475 ; - END - END w0_wd_in[154] - PIN w0_wd_in[155] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 152.005 689.130 152.075 ; - END - END w0_wd_in[155] - PIN w0_wd_in[156] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 157.605 689.130 157.675 ; - END - END w0_wd_in[156] - PIN w0_wd_in[157] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 163.205 689.130 163.275 ; - END - END w0_wd_in[157] - PIN w0_wd_in[158] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 168.805 689.130 168.875 ; - END - END w0_wd_in[158] - PIN w0_wd_in[159] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 174.405 689.130 174.475 ; - END - END w0_wd_in[159] - PIN w0_wd_in[160] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 180.005 689.130 180.075 ; - END - END w0_wd_in[160] - PIN w0_wd_in[161] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 185.605 689.130 185.675 ; - END - END w0_wd_in[161] - PIN w0_wd_in[162] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 191.205 689.130 191.275 ; - END - END w0_wd_in[162] - PIN w0_wd_in[163] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 196.805 689.130 196.875 ; - END - END w0_wd_in[163] - PIN w0_wd_in[164] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 202.405 689.130 202.475 ; - END - END w0_wd_in[164] - PIN w0_wd_in[165] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 208.005 689.130 208.075 ; - END - END w0_wd_in[165] - PIN w0_wd_in[166] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 213.605 689.130 213.675 ; - END - END w0_wd_in[166] - PIN w0_wd_in[167] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 219.205 689.130 219.275 ; - END - END w0_wd_in[167] - PIN w0_wd_in[168] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 224.805 689.130 224.875 ; - END - END w0_wd_in[168] - PIN w0_wd_in[169] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 230.405 689.130 230.475 ; - END - END w0_wd_in[169] - PIN w0_wd_in[170] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 236.005 689.130 236.075 ; - END - END w0_wd_in[170] - PIN w0_wd_in[171] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 241.605 689.130 241.675 ; - END - END w0_wd_in[171] - PIN w0_wd_in[172] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 247.205 689.130 247.275 ; - END - END w0_wd_in[172] - PIN w0_wd_in[173] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 252.805 689.130 252.875 ; - END - END w0_wd_in[173] - PIN w0_wd_in[174] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 258.405 689.130 258.475 ; - END - END w0_wd_in[174] - PIN w0_wd_in[175] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 264.005 689.130 264.075 ; - END - END w0_wd_in[175] - PIN w0_wd_in[176] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 269.605 689.130 269.675 ; - END - END w0_wd_in[176] - PIN w0_wd_in[177] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 275.205 689.130 275.275 ; - END - END w0_wd_in[177] - PIN w0_wd_in[178] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 280.805 689.130 280.875 ; - END - END w0_wd_in[178] - PIN w0_wd_in[179] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 286.405 689.130 286.475 ; - END - END w0_wd_in[179] - PIN w0_wd_in[180] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 292.005 689.130 292.075 ; - END - END w0_wd_in[180] - PIN w0_wd_in[181] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 297.605 689.130 297.675 ; - END - END w0_wd_in[181] - PIN w0_wd_in[182] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 303.205 689.130 303.275 ; - END - END w0_wd_in[182] - PIN w0_wd_in[183] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 308.805 689.130 308.875 ; - END - END w0_wd_in[183] - PIN w0_wd_in[184] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 314.405 689.130 314.475 ; - END - END w0_wd_in[184] - PIN w0_wd_in[185] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 320.005 689.130 320.075 ; - END - END w0_wd_in[185] - PIN w0_wd_in[186] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 325.605 689.130 325.675 ; - END - END w0_wd_in[186] - PIN w0_wd_in[187] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 331.205 689.130 331.275 ; - END - END w0_wd_in[187] - PIN w0_wd_in[188] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 336.805 689.130 336.875 ; - END - END w0_wd_in[188] - PIN w0_wd_in[189] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 342.405 689.130 342.475 ; - END - END w0_wd_in[189] - PIN w0_wd_in[190] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 348.005 689.130 348.075 ; - END - END w0_wd_in[190] - PIN w0_wd_in[191] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 353.605 689.130 353.675 ; - END - END w0_wd_in[191] - PIN w0_wd_in[192] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 359.205 689.130 359.275 ; - END - END w0_wd_in[192] - PIN w0_wd_in[193] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 364.805 689.130 364.875 ; - END - END w0_wd_in[193] - PIN w0_wd_in[194] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 370.405 689.130 370.475 ; - END - END w0_wd_in[194] - PIN w0_wd_in[195] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 376.005 689.130 376.075 ; - END - END w0_wd_in[195] - PIN w0_wd_in[196] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 381.605 689.130 381.675 ; - END - END w0_wd_in[196] - PIN w0_wd_in[197] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 387.205 689.130 387.275 ; - END - END w0_wd_in[197] - PIN w0_wd_in[198] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 392.805 689.130 392.875 ; - END - END w0_wd_in[198] - PIN w0_wd_in[199] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 398.405 689.130 398.475 ; - END - END w0_wd_in[199] - PIN w0_wd_in[200] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 404.005 689.130 404.075 ; - END - END w0_wd_in[200] - PIN w0_wd_in[201] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 409.605 689.130 409.675 ; - END - END w0_wd_in[201] - PIN w0_wd_in[202] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 415.205 689.130 415.275 ; - END - END w0_wd_in[202] - PIN w0_wd_in[203] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 420.805 689.130 420.875 ; - END - END w0_wd_in[203] - PIN w0_wd_in[204] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 426.405 689.130 426.475 ; - END - END w0_wd_in[204] - PIN w0_wd_in[205] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 432.005 689.130 432.075 ; - END - END w0_wd_in[205] - PIN w0_wd_in[206] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 437.605 689.130 437.675 ; - END - END w0_wd_in[206] - PIN w0_wd_in[207] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 443.205 689.130 443.275 ; - END - END w0_wd_in[207] - PIN w0_wd_in[208] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 448.805 689.130 448.875 ; - END - END w0_wd_in[208] - PIN w0_wd_in[209] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 454.405 689.130 454.475 ; - END - END w0_wd_in[209] - PIN w0_wd_in[210] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 460.005 689.130 460.075 ; - END - END w0_wd_in[210] - PIN w0_wd_in[211] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 465.605 689.130 465.675 ; - END - END w0_wd_in[211] - PIN w0_wd_in[212] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 471.205 689.130 471.275 ; - END - END w0_wd_in[212] - PIN w0_wd_in[213] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 476.805 689.130 476.875 ; - END - END w0_wd_in[213] - PIN w0_wd_in[214] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 482.405 689.130 482.475 ; - END - END w0_wd_in[214] - PIN w0_wd_in[215] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 488.005 689.130 488.075 ; - END - END w0_wd_in[215] - PIN w0_wd_in[216] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 493.605 689.130 493.675 ; - END - END w0_wd_in[216] - PIN w0_wd_in[217] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 499.205 689.130 499.275 ; - END - END w0_wd_in[217] - PIN w0_wd_in[218] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 504.805 689.130 504.875 ; - END - END w0_wd_in[218] - PIN w0_wd_in[219] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 510.405 689.130 510.475 ; - END - END w0_wd_in[219] - PIN w0_wd_in[220] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 516.005 689.130 516.075 ; - END - END w0_wd_in[220] - PIN w0_wd_in[221] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 521.605 689.130 521.675 ; - END - END w0_wd_in[221] - PIN w0_wd_in[222] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 527.205 689.130 527.275 ; - END - END w0_wd_in[222] - PIN w0_wd_in[223] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 532.805 689.130 532.875 ; - END - END w0_wd_in[223] - PIN w0_wd_in[224] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 538.405 689.130 538.475 ; - END - END w0_wd_in[224] - PIN w0_wd_in[225] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 544.005 689.130 544.075 ; - END - END w0_wd_in[225] - PIN w0_wd_in[226] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 549.605 689.130 549.675 ; - END - END w0_wd_in[226] - PIN w0_wd_in[227] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 555.205 689.130 555.275 ; - END - END w0_wd_in[227] - PIN w0_wd_in[228] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 560.805 689.130 560.875 ; - END - END w0_wd_in[228] - PIN w0_wd_in[229] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 566.405 689.130 566.475 ; - END - END w0_wd_in[229] - PIN w0_wd_in[230] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 572.005 689.130 572.075 ; - END - END w0_wd_in[230] - PIN w0_wd_in[231] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 577.605 689.130 577.675 ; - END - END w0_wd_in[231] - PIN w0_wd_in[232] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 583.205 689.130 583.275 ; - END - END w0_wd_in[232] - PIN w0_wd_in[233] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 588.805 689.130 588.875 ; - END - END w0_wd_in[233] - PIN w0_wd_in[234] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 594.405 689.130 594.475 ; - END - END w0_wd_in[234] - PIN w0_wd_in[235] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 600.005 689.130 600.075 ; - END - END w0_wd_in[235] - PIN w0_wd_in[236] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 605.605 689.130 605.675 ; - END - END w0_wd_in[236] - PIN w0_wd_in[237] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 611.205 689.130 611.275 ; - END - END w0_wd_in[237] - PIN w0_wd_in[238] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 616.805 689.130 616.875 ; - END - END w0_wd_in[238] - PIN w0_wd_in[239] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 622.405 689.130 622.475 ; - END - END w0_wd_in[239] - PIN w0_wd_in[240] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 628.005 689.130 628.075 ; - END - END w0_wd_in[240] - PIN w0_wd_in[241] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 633.605 689.130 633.675 ; - END - END w0_wd_in[241] - PIN w0_wd_in[242] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 639.205 689.130 639.275 ; - END - END w0_wd_in[242] - PIN w0_wd_in[243] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 644.805 689.130 644.875 ; - END - END w0_wd_in[243] - PIN w0_wd_in[244] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 650.405 689.130 650.475 ; - END - END w0_wd_in[244] - PIN w0_wd_in[245] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 656.005 689.130 656.075 ; - END - END w0_wd_in[245] - PIN w0_wd_in[246] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 661.605 689.130 661.675 ; - END - END w0_wd_in[246] - PIN w0_wd_in[247] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 667.205 689.130 667.275 ; - END - END w0_wd_in[247] - PIN w0_wd_in[248] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 672.805 689.130 672.875 ; - END - END w0_wd_in[248] - PIN w0_wd_in[249] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 678.405 689.130 678.475 ; - END - END w0_wd_in[249] - PIN w0_wd_in[250] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 684.005 689.130 684.075 ; - END - END w0_wd_in[250] - PIN w0_wd_in[251] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 689.605 689.130 689.675 ; - END - END w0_wd_in[251] - PIN w0_wd_in[252] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 695.205 689.130 695.275 ; - END - END w0_wd_in[252] - PIN w0_wd_in[253] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 700.805 689.130 700.875 ; - END - END w0_wd_in[253] - PIN w0_wd_in[254] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 706.405 689.130 706.475 ; - END - END w0_wd_in[254] - PIN w0_wd_in[255] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 712.005 689.130 712.075 ; - END - END w0_wd_in[255] - PIN w0_wd_in[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 0.000 1.175 0.140 ; - END - END w0_wd_in[256] - PIN w0_wd_in[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 2.435 0.000 2.505 0.140 ; - END - END w0_wd_in[257] - PIN w0_wd_in[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 3.765 0.000 3.835 0.140 ; - END - END w0_wd_in[258] - PIN w0_wd_in[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 5.095 0.000 5.165 0.140 ; - END - END w0_wd_in[259] - PIN w0_wd_in[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 6.425 0.000 6.495 0.140 ; - END - END w0_wd_in[260] - PIN w0_wd_in[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 7.755 0.000 7.825 0.140 ; - END - END w0_wd_in[261] - PIN w0_wd_in[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 9.085 0.000 9.155 0.140 ; - END - END w0_wd_in[262] - PIN w0_wd_in[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.415 0.000 10.485 0.140 ; - END - END w0_wd_in[263] - PIN w0_wd_in[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 11.745 0.000 11.815 0.140 ; - END - END w0_wd_in[264] - PIN w0_wd_in[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 13.075 0.000 13.145 0.140 ; - END - END w0_wd_in[265] - PIN w0_wd_in[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 14.405 0.000 14.475 0.140 ; - END - END w0_wd_in[266] - PIN w0_wd_in[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 15.735 0.000 15.805 0.140 ; - END - END w0_wd_in[267] - PIN w0_wd_in[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 17.065 0.000 17.135 0.140 ; - END - END w0_wd_in[268] - PIN w0_wd_in[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 18.395 0.000 18.465 0.140 ; - END - END w0_wd_in[269] - PIN w0_wd_in[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 19.725 0.000 19.795 0.140 ; - END - END w0_wd_in[270] - PIN w0_wd_in[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 21.055 0.000 21.125 0.140 ; - END - END w0_wd_in[271] - PIN w0_wd_in[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 22.385 0.000 22.455 0.140 ; - END - END w0_wd_in[272] - PIN w0_wd_in[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 23.715 0.000 23.785 0.140 ; - END - END w0_wd_in[273] - PIN w0_wd_in[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.045 0.000 25.115 0.140 ; - END - END w0_wd_in[274] - PIN w0_wd_in[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 26.375 0.000 26.445 0.140 ; - END - END w0_wd_in[275] - PIN w0_wd_in[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 27.705 0.000 27.775 0.140 ; - END - END w0_wd_in[276] - PIN w0_wd_in[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 29.035 0.000 29.105 0.140 ; - END - END w0_wd_in[277] - PIN w0_wd_in[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 30.365 0.000 30.435 0.140 ; - END - END w0_wd_in[278] - PIN w0_wd_in[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 31.695 0.000 31.765 0.140 ; - END - END w0_wd_in[279] - PIN w0_wd_in[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 33.025 0.000 33.095 0.140 ; - END - END w0_wd_in[280] - PIN w0_wd_in[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 34.355 0.000 34.425 0.140 ; - END - END w0_wd_in[281] - PIN w0_wd_in[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 35.685 0.000 35.755 0.140 ; - END - END w0_wd_in[282] - PIN w0_wd_in[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 37.015 0.000 37.085 0.140 ; - END - END w0_wd_in[283] - PIN w0_wd_in[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 38.345 0.000 38.415 0.140 ; - END - END w0_wd_in[284] - PIN w0_wd_in[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 39.675 0.000 39.745 0.140 ; - END - END w0_wd_in[285] - PIN w0_wd_in[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 41.005 0.000 41.075 0.140 ; - END - END w0_wd_in[286] - PIN w0_wd_in[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 42.335 0.000 42.405 0.140 ; - END - END w0_wd_in[287] - PIN w0_wd_in[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.665 0.000 43.735 0.140 ; - END - END w0_wd_in[288] - PIN w0_wd_in[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 44.995 0.000 45.065 0.140 ; - END - END w0_wd_in[289] - PIN w0_wd_in[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 46.325 0.000 46.395 0.140 ; - END - END w0_wd_in[290] - PIN w0_wd_in[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 47.655 0.000 47.725 0.140 ; - END - END w0_wd_in[291] - PIN w0_wd_in[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.985 0.000 49.055 0.140 ; - END - END w0_wd_in[292] - PIN w0_wd_in[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 50.315 0.000 50.385 0.140 ; - END - END w0_wd_in[293] - PIN w0_wd_in[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 51.645 0.000 51.715 0.140 ; - END - END w0_wd_in[294] - PIN w0_wd_in[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 52.975 0.000 53.045 0.140 ; - END - END w0_wd_in[295] - PIN w0_wd_in[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 54.305 0.000 54.375 0.140 ; - END - END w0_wd_in[296] - PIN w0_wd_in[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.635 0.000 55.705 0.140 ; - END - END w0_wd_in[297] - PIN w0_wd_in[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 56.965 0.000 57.035 0.140 ; - END - END w0_wd_in[298] - PIN w0_wd_in[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 58.295 0.000 58.365 0.140 ; - END - END w0_wd_in[299] - PIN w0_wd_in[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 59.625 0.000 59.695 0.140 ; - END - END w0_wd_in[300] - PIN w0_wd_in[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 60.955 0.000 61.025 0.140 ; - END - END w0_wd_in[301] - PIN w0_wd_in[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 62.285 0.000 62.355 0.140 ; - END - END w0_wd_in[302] - PIN w0_wd_in[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 63.615 0.000 63.685 0.140 ; - END - END w0_wd_in[303] - PIN w0_wd_in[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 64.945 0.000 65.015 0.140 ; - END - END w0_wd_in[304] - PIN w0_wd_in[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 66.275 0.000 66.345 0.140 ; - END - END w0_wd_in[305] - PIN w0_wd_in[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.605 0.000 67.675 0.140 ; - END - END w0_wd_in[306] - PIN w0_wd_in[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 68.935 0.000 69.005 0.140 ; - END - END w0_wd_in[307] - PIN w0_wd_in[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 70.265 0.000 70.335 0.140 ; - END - END w0_wd_in[308] - PIN w0_wd_in[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 71.595 0.000 71.665 0.140 ; - END - END w0_wd_in[309] - PIN w0_wd_in[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 72.925 0.000 72.995 0.140 ; - END - END w0_wd_in[310] - PIN w0_wd_in[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 74.255 0.000 74.325 0.140 ; - END - END w0_wd_in[311] - PIN w0_wd_in[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 75.585 0.000 75.655 0.140 ; - END - END w0_wd_in[312] - PIN w0_wd_in[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 76.915 0.000 76.985 0.140 ; - END - END w0_wd_in[313] - PIN w0_wd_in[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 78.245 0.000 78.315 0.140 ; - END - END w0_wd_in[314] - PIN w0_wd_in[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 79.575 0.000 79.645 0.140 ; - END - END w0_wd_in[315] - PIN w0_wd_in[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.905 0.000 80.975 0.140 ; - END - END w0_wd_in[316] - PIN w0_wd_in[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 82.235 0.000 82.305 0.140 ; - END - END w0_wd_in[317] - PIN w0_wd_in[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 83.565 0.000 83.635 0.140 ; - END - END w0_wd_in[318] - PIN w0_wd_in[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 84.895 0.000 84.965 0.140 ; - END - END w0_wd_in[319] - PIN w0_wd_in[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 86.225 0.000 86.295 0.140 ; - END - END w0_wd_in[320] - PIN w0_wd_in[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 87.555 0.000 87.625 0.140 ; - END - END w0_wd_in[321] - PIN w0_wd_in[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 88.885 0.000 88.955 0.140 ; - END - END w0_wd_in[322] - PIN w0_wd_in[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 90.215 0.000 90.285 0.140 ; - END - END w0_wd_in[323] - PIN w0_wd_in[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 91.545 0.000 91.615 0.140 ; - END - END w0_wd_in[324] - PIN w0_wd_in[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 92.875 0.000 92.945 0.140 ; - END - END w0_wd_in[325] - PIN w0_wd_in[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 94.205 0.000 94.275 0.140 ; - END - END w0_wd_in[326] - PIN w0_wd_in[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 95.535 0.000 95.605 0.140 ; - END - END w0_wd_in[327] - PIN w0_wd_in[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 96.865 0.000 96.935 0.140 ; - END - END w0_wd_in[328] - PIN w0_wd_in[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 98.195 0.000 98.265 0.140 ; - END - END w0_wd_in[329] - PIN w0_wd_in[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 99.525 0.000 99.595 0.140 ; - END - END w0_wd_in[330] - PIN w0_wd_in[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 100.855 0.000 100.925 0.140 ; - END - END w0_wd_in[331] - PIN w0_wd_in[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 102.185 0.000 102.255 0.140 ; - END - END w0_wd_in[332] - PIN w0_wd_in[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 103.515 0.000 103.585 0.140 ; - END - END w0_wd_in[333] - PIN w0_wd_in[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 104.845 0.000 104.915 0.140 ; - END - END w0_wd_in[334] - PIN w0_wd_in[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 106.175 0.000 106.245 0.140 ; - END - END w0_wd_in[335] - PIN w0_wd_in[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 107.505 0.000 107.575 0.140 ; - END - END w0_wd_in[336] - PIN w0_wd_in[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 108.835 0.000 108.905 0.140 ; - END - END w0_wd_in[337] - PIN w0_wd_in[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 110.165 0.000 110.235 0.140 ; - END - END w0_wd_in[338] - PIN w0_wd_in[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 111.495 0.000 111.565 0.140 ; - END - END w0_wd_in[339] - PIN w0_wd_in[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 112.825 0.000 112.895 0.140 ; - END - END w0_wd_in[340] - PIN w0_wd_in[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 114.155 0.000 114.225 0.140 ; - END - END w0_wd_in[341] - PIN w0_wd_in[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 115.485 0.000 115.555 0.140 ; - END - END w0_wd_in[342] - PIN w0_wd_in[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 116.815 0.000 116.885 0.140 ; - END - END w0_wd_in[343] - PIN w0_wd_in[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 118.145 0.000 118.215 0.140 ; - END - END w0_wd_in[344] - PIN w0_wd_in[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 119.475 0.000 119.545 0.140 ; - END - END w0_wd_in[345] - PIN w0_wd_in[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 120.805 0.000 120.875 0.140 ; - END - END w0_wd_in[346] - PIN w0_wd_in[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 122.135 0.000 122.205 0.140 ; - END - END w0_wd_in[347] - PIN w0_wd_in[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 123.465 0.000 123.535 0.140 ; - END - END w0_wd_in[348] - PIN w0_wd_in[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 124.795 0.000 124.865 0.140 ; - END - END w0_wd_in[349] - PIN w0_wd_in[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 126.125 0.000 126.195 0.140 ; - END - END w0_wd_in[350] - PIN w0_wd_in[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 127.455 0.000 127.525 0.140 ; - END - END w0_wd_in[351] - PIN w0_wd_in[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 128.785 0.000 128.855 0.140 ; - END - END w0_wd_in[352] - PIN w0_wd_in[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 130.115 0.000 130.185 0.140 ; - END - END w0_wd_in[353] - PIN w0_wd_in[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 131.445 0.000 131.515 0.140 ; - END - END w0_wd_in[354] - PIN w0_wd_in[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 132.775 0.000 132.845 0.140 ; - END - END w0_wd_in[355] - PIN w0_wd_in[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 134.105 0.000 134.175 0.140 ; - END - END w0_wd_in[356] - PIN w0_wd_in[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 135.435 0.000 135.505 0.140 ; - END - END w0_wd_in[357] - PIN w0_wd_in[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 136.765 0.000 136.835 0.140 ; - END - END w0_wd_in[358] - PIN w0_wd_in[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 138.095 0.000 138.165 0.140 ; - END - END w0_wd_in[359] - PIN w0_wd_in[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 139.425 0.000 139.495 0.140 ; - END - END w0_wd_in[360] - PIN w0_wd_in[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 140.755 0.000 140.825 0.140 ; - END - END w0_wd_in[361] - PIN w0_wd_in[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 142.085 0.000 142.155 0.140 ; - END - END w0_wd_in[362] - PIN w0_wd_in[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 143.415 0.000 143.485 0.140 ; - END - END w0_wd_in[363] - PIN w0_wd_in[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 144.745 0.000 144.815 0.140 ; - END - END w0_wd_in[364] - PIN w0_wd_in[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 146.075 0.000 146.145 0.140 ; - END - END w0_wd_in[365] - PIN w0_wd_in[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 147.405 0.000 147.475 0.140 ; - END - END w0_wd_in[366] - PIN w0_wd_in[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 148.735 0.000 148.805 0.140 ; - END - END w0_wd_in[367] - PIN w0_wd_in[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 150.065 0.000 150.135 0.140 ; - END - END w0_wd_in[368] - PIN w0_wd_in[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 151.395 0.000 151.465 0.140 ; - END - END w0_wd_in[369] - PIN w0_wd_in[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 152.725 0.000 152.795 0.140 ; - END - END w0_wd_in[370] - PIN w0_wd_in[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 154.055 0.000 154.125 0.140 ; - END - END w0_wd_in[371] - PIN w0_wd_in[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 155.385 0.000 155.455 0.140 ; - END - END w0_wd_in[372] - PIN w0_wd_in[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 156.715 0.000 156.785 0.140 ; - END - END w0_wd_in[373] - PIN w0_wd_in[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 158.045 0.000 158.115 0.140 ; - END - END w0_wd_in[374] - PIN w0_wd_in[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 159.375 0.000 159.445 0.140 ; - END - END w0_wd_in[375] - PIN w0_wd_in[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 160.705 0.000 160.775 0.140 ; - END - END w0_wd_in[376] - PIN w0_wd_in[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 162.035 0.000 162.105 0.140 ; - END - END w0_wd_in[377] - PIN w0_wd_in[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 163.365 0.000 163.435 0.140 ; - END - END w0_wd_in[378] - PIN w0_wd_in[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 164.695 0.000 164.765 0.140 ; - END - END w0_wd_in[379] - PIN w0_wd_in[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 166.025 0.000 166.095 0.140 ; - END - END w0_wd_in[380] - PIN w0_wd_in[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 167.355 0.000 167.425 0.140 ; - END - END w0_wd_in[381] - PIN w0_wd_in[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 168.685 0.000 168.755 0.140 ; - END - END w0_wd_in[382] - PIN w0_wd_in[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 170.015 0.000 170.085 0.140 ; - END - END w0_wd_in[383] - PIN w0_wd_in[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 171.345 0.000 171.415 0.140 ; - END - END w0_wd_in[384] - PIN w0_wd_in[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 172.675 0.000 172.745 0.140 ; - END - END w0_wd_in[385] - PIN w0_wd_in[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 174.005 0.000 174.075 0.140 ; - END - END w0_wd_in[386] - PIN w0_wd_in[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 175.335 0.000 175.405 0.140 ; - END - END w0_wd_in[387] - PIN w0_wd_in[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 176.665 0.000 176.735 0.140 ; - END - END w0_wd_in[388] - PIN w0_wd_in[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 177.995 0.000 178.065 0.140 ; - END - END w0_wd_in[389] - PIN w0_wd_in[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 179.325 0.000 179.395 0.140 ; - END - END w0_wd_in[390] - PIN w0_wd_in[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 180.655 0.000 180.725 0.140 ; - END - END w0_wd_in[391] - PIN w0_wd_in[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 181.985 0.000 182.055 0.140 ; - END - END w0_wd_in[392] - PIN w0_wd_in[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 183.315 0.000 183.385 0.140 ; - END - END w0_wd_in[393] - PIN w0_wd_in[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 184.645 0.000 184.715 0.140 ; - END - END w0_wd_in[394] - PIN w0_wd_in[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 185.975 0.000 186.045 0.140 ; - END - END w0_wd_in[395] - PIN w0_wd_in[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 187.305 0.000 187.375 0.140 ; - END - END w0_wd_in[396] - PIN w0_wd_in[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 188.635 0.000 188.705 0.140 ; - END - END w0_wd_in[397] - PIN w0_wd_in[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 189.965 0.000 190.035 0.140 ; - END - END w0_wd_in[398] - PIN w0_wd_in[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 191.295 0.000 191.365 0.140 ; - END - END w0_wd_in[399] - PIN w0_wd_in[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 192.625 0.000 192.695 0.140 ; - END - END w0_wd_in[400] - PIN w0_wd_in[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 193.955 0.000 194.025 0.140 ; - END - END w0_wd_in[401] - PIN w0_wd_in[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 195.285 0.000 195.355 0.140 ; - END - END w0_wd_in[402] - PIN w0_wd_in[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 196.615 0.000 196.685 0.140 ; - END - END w0_wd_in[403] - PIN w0_wd_in[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 197.945 0.000 198.015 0.140 ; - END - END w0_wd_in[404] - PIN w0_wd_in[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 199.275 0.000 199.345 0.140 ; - END - END w0_wd_in[405] - PIN w0_wd_in[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 200.605 0.000 200.675 0.140 ; - END - END w0_wd_in[406] - PIN w0_wd_in[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 201.935 0.000 202.005 0.140 ; - END - END w0_wd_in[407] - PIN w0_wd_in[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 203.265 0.000 203.335 0.140 ; - END - END w0_wd_in[408] - PIN w0_wd_in[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 204.595 0.000 204.665 0.140 ; - END - END w0_wd_in[409] - PIN w0_wd_in[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 205.925 0.000 205.995 0.140 ; - END - END w0_wd_in[410] - PIN w0_wd_in[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 207.255 0.000 207.325 0.140 ; - END - END w0_wd_in[411] - PIN w0_wd_in[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 208.585 0.000 208.655 0.140 ; - END - END w0_wd_in[412] - PIN w0_wd_in[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 209.915 0.000 209.985 0.140 ; - END - END w0_wd_in[413] - PIN w0_wd_in[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 211.245 0.000 211.315 0.140 ; - END - END w0_wd_in[414] - PIN w0_wd_in[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 212.575 0.000 212.645 0.140 ; - END - END w0_wd_in[415] - PIN w0_wd_in[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 213.905 0.000 213.975 0.140 ; - END - END w0_wd_in[416] - PIN w0_wd_in[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 215.235 0.000 215.305 0.140 ; - END - END w0_wd_in[417] - PIN w0_wd_in[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 216.565 0.000 216.635 0.140 ; - END - END w0_wd_in[418] - PIN w0_wd_in[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 217.895 0.000 217.965 0.140 ; - END - END w0_wd_in[419] - PIN w0_wd_in[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 219.225 0.000 219.295 0.140 ; - END - END w0_wd_in[420] - PIN w0_wd_in[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 220.555 0.000 220.625 0.140 ; - END - END w0_wd_in[421] - PIN w0_wd_in[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 221.885 0.000 221.955 0.140 ; - END - END w0_wd_in[422] - PIN w0_wd_in[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 223.215 0.000 223.285 0.140 ; - END - END w0_wd_in[423] - PIN w0_wd_in[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 224.545 0.000 224.615 0.140 ; - END - END w0_wd_in[424] - PIN w0_wd_in[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 225.875 0.000 225.945 0.140 ; - END - END w0_wd_in[425] - PIN w0_wd_in[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 227.205 0.000 227.275 0.140 ; - END - END w0_wd_in[426] - PIN w0_wd_in[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 228.535 0.000 228.605 0.140 ; - END - END w0_wd_in[427] - PIN w0_wd_in[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 229.865 0.000 229.935 0.140 ; - END - END w0_wd_in[428] - PIN w0_wd_in[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 231.195 0.000 231.265 0.140 ; - END - END w0_wd_in[429] - PIN w0_wd_in[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 232.525 0.000 232.595 0.140 ; - END - END w0_wd_in[430] - PIN w0_wd_in[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 233.855 0.000 233.925 0.140 ; - END - END w0_wd_in[431] - PIN w0_wd_in[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 235.185 0.000 235.255 0.140 ; - END - END w0_wd_in[432] - PIN w0_wd_in[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 236.515 0.000 236.585 0.140 ; - END - END w0_wd_in[433] - PIN w0_wd_in[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 237.845 0.000 237.915 0.140 ; - END - END w0_wd_in[434] - PIN w0_wd_in[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 239.175 0.000 239.245 0.140 ; - END - END w0_wd_in[435] - PIN w0_wd_in[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 240.505 0.000 240.575 0.140 ; - END - END w0_wd_in[436] - PIN w0_wd_in[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 241.835 0.000 241.905 0.140 ; - END - END w0_wd_in[437] - PIN w0_wd_in[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 243.165 0.000 243.235 0.140 ; - END - END w0_wd_in[438] - PIN w0_wd_in[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 244.495 0.000 244.565 0.140 ; - END - END w0_wd_in[439] - PIN w0_wd_in[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 245.825 0.000 245.895 0.140 ; - END - END w0_wd_in[440] - PIN w0_wd_in[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 247.155 0.000 247.225 0.140 ; - END - END w0_wd_in[441] - PIN w0_wd_in[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 248.485 0.000 248.555 0.140 ; - END - END w0_wd_in[442] - PIN w0_wd_in[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 249.815 0.000 249.885 0.140 ; - END - END w0_wd_in[443] - PIN w0_wd_in[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 251.145 0.000 251.215 0.140 ; - END - END w0_wd_in[444] - PIN w0_wd_in[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 252.475 0.000 252.545 0.140 ; - END - END w0_wd_in[445] - PIN w0_wd_in[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 253.805 0.000 253.875 0.140 ; - END - END w0_wd_in[446] - PIN w0_wd_in[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 255.135 0.000 255.205 0.140 ; - END - END w0_wd_in[447] - PIN w0_wd_in[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 256.465 0.000 256.535 0.140 ; - END - END w0_wd_in[448] - PIN w0_wd_in[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 257.795 0.000 257.865 0.140 ; - END - END w0_wd_in[449] - PIN w0_wd_in[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 259.125 0.000 259.195 0.140 ; - END - END w0_wd_in[450] - PIN w0_wd_in[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 260.455 0.000 260.525 0.140 ; - END - END w0_wd_in[451] - PIN w0_wd_in[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 261.785 0.000 261.855 0.140 ; - END - END w0_wd_in[452] - PIN w0_wd_in[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 263.115 0.000 263.185 0.140 ; - END - END w0_wd_in[453] - PIN w0_wd_in[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 264.445 0.000 264.515 0.140 ; - END - END w0_wd_in[454] - PIN w0_wd_in[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 265.775 0.000 265.845 0.140 ; - END - END w0_wd_in[455] - PIN w0_wd_in[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 267.105 0.000 267.175 0.140 ; - END - END w0_wd_in[456] - PIN w0_wd_in[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 268.435 0.000 268.505 0.140 ; - END - END w0_wd_in[457] - PIN w0_wd_in[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 269.765 0.000 269.835 0.140 ; - END - END w0_wd_in[458] - PIN w0_wd_in[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 271.095 0.000 271.165 0.140 ; - END - END w0_wd_in[459] - PIN w0_wd_in[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 272.425 0.000 272.495 0.140 ; - END - END w0_wd_in[460] - PIN w0_wd_in[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 273.755 0.000 273.825 0.140 ; - END - END w0_wd_in[461] - PIN w0_wd_in[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 275.085 0.000 275.155 0.140 ; - END - END w0_wd_in[462] - PIN w0_wd_in[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 276.415 0.000 276.485 0.140 ; - END - END w0_wd_in[463] - PIN w0_wd_in[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 277.745 0.000 277.815 0.140 ; - END - END w0_wd_in[464] - PIN w0_wd_in[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 279.075 0.000 279.145 0.140 ; - END - END w0_wd_in[465] - PIN w0_wd_in[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 280.405 0.000 280.475 0.140 ; - END - END w0_wd_in[466] - PIN w0_wd_in[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 281.735 0.000 281.805 0.140 ; - END - END w0_wd_in[467] - PIN w0_wd_in[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 283.065 0.000 283.135 0.140 ; - END - END w0_wd_in[468] - PIN w0_wd_in[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 284.395 0.000 284.465 0.140 ; - END - END w0_wd_in[469] - PIN w0_wd_in[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 285.725 0.000 285.795 0.140 ; - END - END w0_wd_in[470] - PIN w0_wd_in[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 287.055 0.000 287.125 0.140 ; - END - END w0_wd_in[471] - PIN w0_wd_in[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 288.385 0.000 288.455 0.140 ; - END - END w0_wd_in[472] - PIN w0_wd_in[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 289.715 0.000 289.785 0.140 ; - END - END w0_wd_in[473] - PIN w0_wd_in[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 291.045 0.000 291.115 0.140 ; - END - END w0_wd_in[474] - PIN w0_wd_in[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 292.375 0.000 292.445 0.140 ; - END - END w0_wd_in[475] - PIN w0_wd_in[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 293.705 0.000 293.775 0.140 ; - END - END w0_wd_in[476] - PIN w0_wd_in[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 295.035 0.000 295.105 0.140 ; - END - END w0_wd_in[477] - PIN w0_wd_in[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 296.365 0.000 296.435 0.140 ; - END - END w0_wd_in[478] - PIN w0_wd_in[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 297.695 0.000 297.765 0.140 ; - END - END w0_wd_in[479] - PIN w0_wd_in[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 299.025 0.000 299.095 0.140 ; - END - END w0_wd_in[480] - PIN w0_wd_in[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 300.355 0.000 300.425 0.140 ; - END - END w0_wd_in[481] - PIN w0_wd_in[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 301.685 0.000 301.755 0.140 ; - END - END w0_wd_in[482] - PIN w0_wd_in[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 303.015 0.000 303.085 0.140 ; - END - END w0_wd_in[483] - PIN w0_wd_in[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 304.345 0.000 304.415 0.140 ; - END - END w0_wd_in[484] - PIN w0_wd_in[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 305.675 0.000 305.745 0.140 ; - END - END w0_wd_in[485] - PIN w0_wd_in[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 307.005 0.000 307.075 0.140 ; - END - END w0_wd_in[486] - PIN w0_wd_in[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 308.335 0.000 308.405 0.140 ; - END - END w0_wd_in[487] - PIN w0_wd_in[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 309.665 0.000 309.735 0.140 ; - END - END w0_wd_in[488] - PIN w0_wd_in[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 310.995 0.000 311.065 0.140 ; - END - END w0_wd_in[489] - PIN w0_wd_in[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 312.325 0.000 312.395 0.140 ; - END - END w0_wd_in[490] - PIN w0_wd_in[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 313.655 0.000 313.725 0.140 ; - END - END w0_wd_in[491] - PIN w0_wd_in[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 314.985 0.000 315.055 0.140 ; - END - END w0_wd_in[492] - PIN w0_wd_in[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 316.315 0.000 316.385 0.140 ; - END - END w0_wd_in[493] - PIN w0_wd_in[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 317.645 0.000 317.715 0.140 ; - END - END w0_wd_in[494] - PIN w0_wd_in[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 318.975 0.000 319.045 0.140 ; - END - END w0_wd_in[495] - PIN w0_wd_in[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 320.305 0.000 320.375 0.140 ; - END - END w0_wd_in[496] - PIN w0_wd_in[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 321.635 0.000 321.705 0.140 ; - END - END w0_wd_in[497] - PIN w0_wd_in[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 322.965 0.000 323.035 0.140 ; - END - END w0_wd_in[498] - PIN w0_wd_in[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 324.295 0.000 324.365 0.140 ; - END - END w0_wd_in[499] - PIN w0_wd_in[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 325.625 0.000 325.695 0.140 ; - END - END w0_wd_in[500] - PIN w0_wd_in[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 326.955 0.000 327.025 0.140 ; - END - END w0_wd_in[501] - PIN w0_wd_in[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 328.285 0.000 328.355 0.140 ; - END - END w0_wd_in[502] - PIN w0_wd_in[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 329.615 0.000 329.685 0.140 ; - END - END w0_wd_in[503] - PIN w0_wd_in[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 330.945 0.000 331.015 0.140 ; - END - END w0_wd_in[504] - PIN w0_wd_in[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 332.275 0.000 332.345 0.140 ; - END - END w0_wd_in[505] - PIN w0_wd_in[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 333.605 0.000 333.675 0.140 ; - END - END w0_wd_in[506] - PIN w0_wd_in[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 334.935 0.000 335.005 0.140 ; - END - END w0_wd_in[507] - PIN w0_wd_in[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 336.265 0.000 336.335 0.140 ; - END - END w0_wd_in[508] - PIN w0_wd_in[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 337.595 0.000 337.665 0.140 ; - END - END w0_wd_in[509] - PIN w0_wd_in[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 338.925 0.000 338.995 0.140 ; - END - END w0_wd_in[510] - PIN w0_wd_in[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 340.255 0.000 340.325 0.140 ; - END - END w0_wd_in[511] - PIN r0_rd_out[0] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 341.585 0.000 341.655 0.140 ; - END - END r0_rd_out[0] - PIN r0_rd_out[1] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 342.915 0.000 342.985 0.140 ; - END - END r0_rd_out[1] - PIN r0_rd_out[2] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 344.245 0.000 344.315 0.140 ; - END - END r0_rd_out[2] - PIN r0_rd_out[3] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 345.575 0.000 345.645 0.140 ; - END - END r0_rd_out[3] - PIN r0_rd_out[4] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 346.905 0.000 346.975 0.140 ; - END - END r0_rd_out[4] - PIN r0_rd_out[5] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 348.235 0.000 348.305 0.140 ; - END - END r0_rd_out[5] - PIN r0_rd_out[6] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 349.565 0.000 349.635 0.140 ; - END - END r0_rd_out[6] - PIN r0_rd_out[7] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 350.895 0.000 350.965 0.140 ; - END - END r0_rd_out[7] - PIN r0_rd_out[8] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 352.225 0.000 352.295 0.140 ; - END - END r0_rd_out[8] - PIN r0_rd_out[9] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 353.555 0.000 353.625 0.140 ; - END - END r0_rd_out[9] - PIN r0_rd_out[10] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 354.885 0.000 354.955 0.140 ; - END - END r0_rd_out[10] - PIN r0_rd_out[11] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 356.215 0.000 356.285 0.140 ; - END - END r0_rd_out[11] - PIN r0_rd_out[12] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 357.545 0.000 357.615 0.140 ; - END - END r0_rd_out[12] - PIN r0_rd_out[13] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 358.875 0.000 358.945 0.140 ; - END - END r0_rd_out[13] - PIN r0_rd_out[14] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 360.205 0.000 360.275 0.140 ; - END - END r0_rd_out[14] - PIN r0_rd_out[15] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 361.535 0.000 361.605 0.140 ; - END - END r0_rd_out[15] - PIN r0_rd_out[16] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 362.865 0.000 362.935 0.140 ; - END - END r0_rd_out[16] - PIN r0_rd_out[17] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 364.195 0.000 364.265 0.140 ; - END - END r0_rd_out[17] - PIN r0_rd_out[18] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 365.525 0.000 365.595 0.140 ; - END - END r0_rd_out[18] - PIN r0_rd_out[19] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 366.855 0.000 366.925 0.140 ; - END - END r0_rd_out[19] - PIN r0_rd_out[20] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 368.185 0.000 368.255 0.140 ; - END - END r0_rd_out[20] - PIN r0_rd_out[21] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 369.515 0.000 369.585 0.140 ; - END - END r0_rd_out[21] - PIN r0_rd_out[22] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 370.845 0.000 370.915 0.140 ; - END - END r0_rd_out[22] - PIN r0_rd_out[23] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 372.175 0.000 372.245 0.140 ; - END - END r0_rd_out[23] - PIN r0_rd_out[24] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 373.505 0.000 373.575 0.140 ; - END - END r0_rd_out[24] - PIN r0_rd_out[25] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 374.835 0.000 374.905 0.140 ; - END - END r0_rd_out[25] - PIN r0_rd_out[26] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 376.165 0.000 376.235 0.140 ; - END - END r0_rd_out[26] - PIN r0_rd_out[27] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 377.495 0.000 377.565 0.140 ; - END - END r0_rd_out[27] - PIN r0_rd_out[28] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 378.825 0.000 378.895 0.140 ; - END - END r0_rd_out[28] - PIN r0_rd_out[29] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 380.155 0.000 380.225 0.140 ; - END - END r0_rd_out[29] - PIN r0_rd_out[30] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 381.485 0.000 381.555 0.140 ; - END - END r0_rd_out[30] - PIN r0_rd_out[31] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 382.815 0.000 382.885 0.140 ; - END - END r0_rd_out[31] - PIN r0_rd_out[32] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 384.145 0.000 384.215 0.140 ; - END - END r0_rd_out[32] - PIN r0_rd_out[33] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 385.475 0.000 385.545 0.140 ; - END - END r0_rd_out[33] - PIN r0_rd_out[34] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 386.805 0.000 386.875 0.140 ; - END - END r0_rd_out[34] - PIN r0_rd_out[35] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 388.135 0.000 388.205 0.140 ; - END - END r0_rd_out[35] - PIN r0_rd_out[36] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 389.465 0.000 389.535 0.140 ; - END - END r0_rd_out[36] - PIN r0_rd_out[37] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 390.795 0.000 390.865 0.140 ; - END - END r0_rd_out[37] - PIN r0_rd_out[38] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 392.125 0.000 392.195 0.140 ; - END - END r0_rd_out[38] - PIN r0_rd_out[39] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 393.455 0.000 393.525 0.140 ; - END - END r0_rd_out[39] - PIN r0_rd_out[40] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 394.785 0.000 394.855 0.140 ; - END - END r0_rd_out[40] - PIN r0_rd_out[41] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 396.115 0.000 396.185 0.140 ; - END - END r0_rd_out[41] - PIN r0_rd_out[42] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 397.445 0.000 397.515 0.140 ; - END - END r0_rd_out[42] - PIN r0_rd_out[43] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 398.775 0.000 398.845 0.140 ; - END - END r0_rd_out[43] - PIN r0_rd_out[44] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 400.105 0.000 400.175 0.140 ; - END - END r0_rd_out[44] - PIN r0_rd_out[45] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 401.435 0.000 401.505 0.140 ; - END - END r0_rd_out[45] - PIN r0_rd_out[46] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 402.765 0.000 402.835 0.140 ; - END - END r0_rd_out[46] - PIN r0_rd_out[47] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 404.095 0.000 404.165 0.140 ; - END - END r0_rd_out[47] - PIN r0_rd_out[48] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 405.425 0.000 405.495 0.140 ; - END - END r0_rd_out[48] - PIN r0_rd_out[49] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 406.755 0.000 406.825 0.140 ; - END - END r0_rd_out[49] - PIN r0_rd_out[50] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 408.085 0.000 408.155 0.140 ; - END - END r0_rd_out[50] - PIN r0_rd_out[51] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 409.415 0.000 409.485 0.140 ; - END - END r0_rd_out[51] - PIN r0_rd_out[52] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 410.745 0.000 410.815 0.140 ; - END - END r0_rd_out[52] - PIN r0_rd_out[53] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 412.075 0.000 412.145 0.140 ; - END - END r0_rd_out[53] - PIN r0_rd_out[54] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 413.405 0.000 413.475 0.140 ; - END - END r0_rd_out[54] - PIN r0_rd_out[55] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 414.735 0.000 414.805 0.140 ; - END - END r0_rd_out[55] - PIN r0_rd_out[56] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 416.065 0.000 416.135 0.140 ; - END - END r0_rd_out[56] - PIN r0_rd_out[57] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 417.395 0.000 417.465 0.140 ; - END - END r0_rd_out[57] - PIN r0_rd_out[58] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 418.725 0.000 418.795 0.140 ; - END - END r0_rd_out[58] - PIN r0_rd_out[59] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 420.055 0.000 420.125 0.140 ; - END - END r0_rd_out[59] - PIN r0_rd_out[60] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 421.385 0.000 421.455 0.140 ; - END - END r0_rd_out[60] - PIN r0_rd_out[61] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 422.715 0.000 422.785 0.140 ; - END - END r0_rd_out[61] - PIN r0_rd_out[62] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 424.045 0.000 424.115 0.140 ; - END - END r0_rd_out[62] - PIN r0_rd_out[63] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 425.375 0.000 425.445 0.140 ; - END - END r0_rd_out[63] - PIN r0_rd_out[64] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 426.705 0.000 426.775 0.140 ; - END - END r0_rd_out[64] - PIN r0_rd_out[65] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 428.035 0.000 428.105 0.140 ; - END - END r0_rd_out[65] - PIN r0_rd_out[66] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 429.365 0.000 429.435 0.140 ; - END - END r0_rd_out[66] - PIN r0_rd_out[67] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 430.695 0.000 430.765 0.140 ; - END - END r0_rd_out[67] - PIN r0_rd_out[68] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 432.025 0.000 432.095 0.140 ; - END - END r0_rd_out[68] - PIN r0_rd_out[69] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 433.355 0.000 433.425 0.140 ; - END - END r0_rd_out[69] - PIN r0_rd_out[70] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 434.685 0.000 434.755 0.140 ; - END - END r0_rd_out[70] - PIN r0_rd_out[71] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 436.015 0.000 436.085 0.140 ; - END - END r0_rd_out[71] - PIN r0_rd_out[72] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 437.345 0.000 437.415 0.140 ; - END - END r0_rd_out[72] - PIN r0_rd_out[73] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 438.675 0.000 438.745 0.140 ; - END - END r0_rd_out[73] - PIN r0_rd_out[74] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 440.005 0.000 440.075 0.140 ; - END - END r0_rd_out[74] - PIN r0_rd_out[75] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 441.335 0.000 441.405 0.140 ; - END - END r0_rd_out[75] - PIN r0_rd_out[76] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 442.665 0.000 442.735 0.140 ; - END - END r0_rd_out[76] - PIN r0_rd_out[77] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 443.995 0.000 444.065 0.140 ; - END - END r0_rd_out[77] - PIN r0_rd_out[78] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 445.325 0.000 445.395 0.140 ; - END - END r0_rd_out[78] - PIN r0_rd_out[79] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 446.655 0.000 446.725 0.140 ; - END - END r0_rd_out[79] - PIN r0_rd_out[80] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 447.985 0.000 448.055 0.140 ; - END - END r0_rd_out[80] - PIN r0_rd_out[81] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 449.315 0.000 449.385 0.140 ; - END - END r0_rd_out[81] - PIN r0_rd_out[82] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 450.645 0.000 450.715 0.140 ; - END - END r0_rd_out[82] - PIN r0_rd_out[83] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 451.975 0.000 452.045 0.140 ; - END - END r0_rd_out[83] - PIN r0_rd_out[84] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 453.305 0.000 453.375 0.140 ; - END - END r0_rd_out[84] - PIN r0_rd_out[85] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 454.635 0.000 454.705 0.140 ; - END - END r0_rd_out[85] - PIN r0_rd_out[86] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 455.965 0.000 456.035 0.140 ; - END - END r0_rd_out[86] - PIN r0_rd_out[87] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 457.295 0.000 457.365 0.140 ; - END - END r0_rd_out[87] - PIN r0_rd_out[88] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 458.625 0.000 458.695 0.140 ; - END - END r0_rd_out[88] - PIN r0_rd_out[89] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 459.955 0.000 460.025 0.140 ; - END - END r0_rd_out[89] - PIN r0_rd_out[90] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 461.285 0.000 461.355 0.140 ; - END - END r0_rd_out[90] - PIN r0_rd_out[91] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 462.615 0.000 462.685 0.140 ; - END - END r0_rd_out[91] - PIN r0_rd_out[92] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 463.945 0.000 464.015 0.140 ; - END - END r0_rd_out[92] - PIN r0_rd_out[93] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 465.275 0.000 465.345 0.140 ; - END - END r0_rd_out[93] - PIN r0_rd_out[94] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 466.605 0.000 466.675 0.140 ; - END - END r0_rd_out[94] - PIN r0_rd_out[95] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 467.935 0.000 468.005 0.140 ; - END - END r0_rd_out[95] - PIN r0_rd_out[96] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 469.265 0.000 469.335 0.140 ; - END - END r0_rd_out[96] - PIN r0_rd_out[97] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 470.595 0.000 470.665 0.140 ; - END - END r0_rd_out[97] - PIN r0_rd_out[98] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 471.925 0.000 471.995 0.140 ; - END - END r0_rd_out[98] - PIN r0_rd_out[99] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 473.255 0.000 473.325 0.140 ; - END - END r0_rd_out[99] - PIN r0_rd_out[100] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 474.585 0.000 474.655 0.140 ; - END - END r0_rd_out[100] - PIN r0_rd_out[101] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 475.915 0.000 475.985 0.140 ; - END - END r0_rd_out[101] - PIN r0_rd_out[102] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 477.245 0.000 477.315 0.140 ; - END - END r0_rd_out[102] - PIN r0_rd_out[103] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 478.575 0.000 478.645 0.140 ; - END - END r0_rd_out[103] - PIN r0_rd_out[104] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 479.905 0.000 479.975 0.140 ; - END - END r0_rd_out[104] - PIN r0_rd_out[105] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 481.235 0.000 481.305 0.140 ; - END - END r0_rd_out[105] - PIN r0_rd_out[106] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 482.565 0.000 482.635 0.140 ; - END - END r0_rd_out[106] - PIN r0_rd_out[107] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 483.895 0.000 483.965 0.140 ; - END - END r0_rd_out[107] - PIN r0_rd_out[108] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 485.225 0.000 485.295 0.140 ; - END - END r0_rd_out[108] - PIN r0_rd_out[109] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 486.555 0.000 486.625 0.140 ; - END - END r0_rd_out[109] - PIN r0_rd_out[110] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 487.885 0.000 487.955 0.140 ; - END - END r0_rd_out[110] - PIN r0_rd_out[111] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 489.215 0.000 489.285 0.140 ; - END - END r0_rd_out[111] - PIN r0_rd_out[112] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 490.545 0.000 490.615 0.140 ; - END - END r0_rd_out[112] - PIN r0_rd_out[113] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 491.875 0.000 491.945 0.140 ; - END - END r0_rd_out[113] - PIN r0_rd_out[114] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 493.205 0.000 493.275 0.140 ; - END - END r0_rd_out[114] - PIN r0_rd_out[115] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 494.535 0.000 494.605 0.140 ; - END - END r0_rd_out[115] - PIN r0_rd_out[116] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 495.865 0.000 495.935 0.140 ; - END - END r0_rd_out[116] - PIN r0_rd_out[117] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 497.195 0.000 497.265 0.140 ; - END - END r0_rd_out[117] - PIN r0_rd_out[118] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 498.525 0.000 498.595 0.140 ; - END - END r0_rd_out[118] - PIN r0_rd_out[119] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 499.855 0.000 499.925 0.140 ; - END - END r0_rd_out[119] - PIN r0_rd_out[120] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 501.185 0.000 501.255 0.140 ; - END - END r0_rd_out[120] - PIN r0_rd_out[121] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 502.515 0.000 502.585 0.140 ; - END - END r0_rd_out[121] - PIN r0_rd_out[122] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 503.845 0.000 503.915 0.140 ; - END - END r0_rd_out[122] - PIN r0_rd_out[123] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 505.175 0.000 505.245 0.140 ; - END - END r0_rd_out[123] - PIN r0_rd_out[124] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 506.505 0.000 506.575 0.140 ; - END - END r0_rd_out[124] - PIN r0_rd_out[125] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 507.835 0.000 507.905 0.140 ; - END - END r0_rd_out[125] - PIN r0_rd_out[126] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 509.165 0.000 509.235 0.140 ; - END - END r0_rd_out[126] - PIN r0_rd_out[127] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 510.495 0.000 510.565 0.140 ; - END - END r0_rd_out[127] - PIN r0_rd_out[128] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 511.825 0.000 511.895 0.140 ; - END - END r0_rd_out[128] - PIN r0_rd_out[129] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 513.155 0.000 513.225 0.140 ; - END - END r0_rd_out[129] - PIN r0_rd_out[130] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 514.485 0.000 514.555 0.140 ; - END - END r0_rd_out[130] - PIN r0_rd_out[131] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 515.815 0.000 515.885 0.140 ; - END - END r0_rd_out[131] - PIN r0_rd_out[132] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 517.145 0.000 517.215 0.140 ; - END - END r0_rd_out[132] - PIN r0_rd_out[133] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 518.475 0.000 518.545 0.140 ; - END - END r0_rd_out[133] - PIN r0_rd_out[134] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 519.805 0.000 519.875 0.140 ; - END - END r0_rd_out[134] - PIN r0_rd_out[135] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 521.135 0.000 521.205 0.140 ; - END - END r0_rd_out[135] - PIN r0_rd_out[136] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 522.465 0.000 522.535 0.140 ; - END - END r0_rd_out[136] - PIN r0_rd_out[137] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 523.795 0.000 523.865 0.140 ; - END - END r0_rd_out[137] - PIN r0_rd_out[138] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 525.125 0.000 525.195 0.140 ; - END - END r0_rd_out[138] - PIN r0_rd_out[139] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 526.455 0.000 526.525 0.140 ; - END - END r0_rd_out[139] - PIN r0_rd_out[140] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 527.785 0.000 527.855 0.140 ; - END - END r0_rd_out[140] - PIN r0_rd_out[141] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 529.115 0.000 529.185 0.140 ; - END - END r0_rd_out[141] - PIN r0_rd_out[142] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 530.445 0.000 530.515 0.140 ; - END - END r0_rd_out[142] - PIN r0_rd_out[143] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 531.775 0.000 531.845 0.140 ; - END - END r0_rd_out[143] - PIN r0_rd_out[144] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 533.105 0.000 533.175 0.140 ; - END - END r0_rd_out[144] - PIN r0_rd_out[145] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 534.435 0.000 534.505 0.140 ; - END - END r0_rd_out[145] - PIN r0_rd_out[146] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 535.765 0.000 535.835 0.140 ; - END - END r0_rd_out[146] - PIN r0_rd_out[147] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 537.095 0.000 537.165 0.140 ; - END - END r0_rd_out[147] - PIN r0_rd_out[148] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 538.425 0.000 538.495 0.140 ; - END - END r0_rd_out[148] - PIN r0_rd_out[149] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 539.755 0.000 539.825 0.140 ; - END - END r0_rd_out[149] - PIN r0_rd_out[150] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 541.085 0.000 541.155 0.140 ; - END - END r0_rd_out[150] - PIN r0_rd_out[151] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 542.415 0.000 542.485 0.140 ; - END - END r0_rd_out[151] - PIN r0_rd_out[152] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 543.745 0.000 543.815 0.140 ; - END - END r0_rd_out[152] - PIN r0_rd_out[153] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 545.075 0.000 545.145 0.140 ; - END - END r0_rd_out[153] - PIN r0_rd_out[154] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 546.405 0.000 546.475 0.140 ; - END - END r0_rd_out[154] - PIN r0_rd_out[155] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 547.735 0.000 547.805 0.140 ; - END - END r0_rd_out[155] - PIN r0_rd_out[156] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 549.065 0.000 549.135 0.140 ; - END - END r0_rd_out[156] - PIN r0_rd_out[157] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 550.395 0.000 550.465 0.140 ; - END - END r0_rd_out[157] - PIN r0_rd_out[158] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 551.725 0.000 551.795 0.140 ; - END - END r0_rd_out[158] - PIN r0_rd_out[159] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 553.055 0.000 553.125 0.140 ; - END - END r0_rd_out[159] - PIN r0_rd_out[160] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 554.385 0.000 554.455 0.140 ; - END - END r0_rd_out[160] - PIN r0_rd_out[161] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 555.715 0.000 555.785 0.140 ; - END - END r0_rd_out[161] - PIN r0_rd_out[162] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 557.045 0.000 557.115 0.140 ; - END - END r0_rd_out[162] - PIN r0_rd_out[163] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 558.375 0.000 558.445 0.140 ; - END - END r0_rd_out[163] - PIN r0_rd_out[164] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 559.705 0.000 559.775 0.140 ; - END - END r0_rd_out[164] - PIN r0_rd_out[165] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 561.035 0.000 561.105 0.140 ; - END - END r0_rd_out[165] - PIN r0_rd_out[166] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 562.365 0.000 562.435 0.140 ; - END - END r0_rd_out[166] - PIN r0_rd_out[167] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 563.695 0.000 563.765 0.140 ; - END - END r0_rd_out[167] - PIN r0_rd_out[168] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 565.025 0.000 565.095 0.140 ; - END - END r0_rd_out[168] - PIN r0_rd_out[169] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 566.355 0.000 566.425 0.140 ; - END - END r0_rd_out[169] - PIN r0_rd_out[170] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 567.685 0.000 567.755 0.140 ; - END - END r0_rd_out[170] - PIN r0_rd_out[171] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 569.015 0.000 569.085 0.140 ; - END - END r0_rd_out[171] - PIN r0_rd_out[172] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 570.345 0.000 570.415 0.140 ; - END - END r0_rd_out[172] - PIN r0_rd_out[173] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 571.675 0.000 571.745 0.140 ; - END - END r0_rd_out[173] - PIN r0_rd_out[174] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 573.005 0.000 573.075 0.140 ; - END - END r0_rd_out[174] - PIN r0_rd_out[175] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 574.335 0.000 574.405 0.140 ; - END - END r0_rd_out[175] - PIN r0_rd_out[176] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 575.665 0.000 575.735 0.140 ; - END - END r0_rd_out[176] - PIN r0_rd_out[177] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 576.995 0.000 577.065 0.140 ; - END - END r0_rd_out[177] - PIN r0_rd_out[178] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 578.325 0.000 578.395 0.140 ; - END - END r0_rd_out[178] - PIN r0_rd_out[179] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 579.655 0.000 579.725 0.140 ; - END - END r0_rd_out[179] - PIN r0_rd_out[180] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 580.985 0.000 581.055 0.140 ; - END - END r0_rd_out[180] - PIN r0_rd_out[181] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 582.315 0.000 582.385 0.140 ; - END - END r0_rd_out[181] - PIN r0_rd_out[182] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 583.645 0.000 583.715 0.140 ; - END - END r0_rd_out[182] - PIN r0_rd_out[183] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 584.975 0.000 585.045 0.140 ; - END - END r0_rd_out[183] - PIN r0_rd_out[184] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 586.305 0.000 586.375 0.140 ; - END - END r0_rd_out[184] - PIN r0_rd_out[185] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 587.635 0.000 587.705 0.140 ; - END - END r0_rd_out[185] - PIN r0_rd_out[186] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 588.965 0.000 589.035 0.140 ; - END - END r0_rd_out[186] - PIN r0_rd_out[187] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 590.295 0.000 590.365 0.140 ; - END - END r0_rd_out[187] - PIN r0_rd_out[188] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 591.625 0.000 591.695 0.140 ; - END - END r0_rd_out[188] - PIN r0_rd_out[189] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 592.955 0.000 593.025 0.140 ; - END - END r0_rd_out[189] - PIN r0_rd_out[190] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 594.285 0.000 594.355 0.140 ; - END - END r0_rd_out[190] - PIN r0_rd_out[191] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 595.615 0.000 595.685 0.140 ; - END - END r0_rd_out[191] - PIN r0_rd_out[192] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 596.945 0.000 597.015 0.140 ; - END - END r0_rd_out[192] - PIN r0_rd_out[193] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 598.275 0.000 598.345 0.140 ; - END - END r0_rd_out[193] - PIN r0_rd_out[194] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 599.605 0.000 599.675 0.140 ; - END - END r0_rd_out[194] - PIN r0_rd_out[195] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 600.935 0.000 601.005 0.140 ; - END - END r0_rd_out[195] - PIN r0_rd_out[196] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 602.265 0.000 602.335 0.140 ; - END - END r0_rd_out[196] - PIN r0_rd_out[197] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 603.595 0.000 603.665 0.140 ; - END - END r0_rd_out[197] - PIN r0_rd_out[198] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 604.925 0.000 604.995 0.140 ; - END - END r0_rd_out[198] - PIN r0_rd_out[199] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 606.255 0.000 606.325 0.140 ; - END - END r0_rd_out[199] - PIN r0_rd_out[200] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 607.585 0.000 607.655 0.140 ; - END - END r0_rd_out[200] - PIN r0_rd_out[201] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 608.915 0.000 608.985 0.140 ; - END - END r0_rd_out[201] - PIN r0_rd_out[202] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 610.245 0.000 610.315 0.140 ; - END - END r0_rd_out[202] - PIN r0_rd_out[203] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 611.575 0.000 611.645 0.140 ; - END - END r0_rd_out[203] - PIN r0_rd_out[204] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 612.905 0.000 612.975 0.140 ; - END - END r0_rd_out[204] - PIN r0_rd_out[205] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 614.235 0.000 614.305 0.140 ; - END - END r0_rd_out[205] - PIN r0_rd_out[206] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 615.565 0.000 615.635 0.140 ; - END - END r0_rd_out[206] - PIN r0_rd_out[207] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 616.895 0.000 616.965 0.140 ; - END - END r0_rd_out[207] - PIN r0_rd_out[208] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 618.225 0.000 618.295 0.140 ; - END - END r0_rd_out[208] - PIN r0_rd_out[209] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 619.555 0.000 619.625 0.140 ; - END - END r0_rd_out[209] - PIN r0_rd_out[210] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 620.885 0.000 620.955 0.140 ; - END - END r0_rd_out[210] - PIN r0_rd_out[211] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 622.215 0.000 622.285 0.140 ; - END - END r0_rd_out[211] - PIN r0_rd_out[212] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 623.545 0.000 623.615 0.140 ; - END - END r0_rd_out[212] - PIN r0_rd_out[213] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 624.875 0.000 624.945 0.140 ; - END - END r0_rd_out[213] - PIN r0_rd_out[214] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 626.205 0.000 626.275 0.140 ; - END - END r0_rd_out[214] - PIN r0_rd_out[215] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 627.535 0.000 627.605 0.140 ; - END - END r0_rd_out[215] - PIN r0_rd_out[216] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 628.865 0.000 628.935 0.140 ; - END - END r0_rd_out[216] - PIN r0_rd_out[217] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 630.195 0.000 630.265 0.140 ; - END - END r0_rd_out[217] - PIN r0_rd_out[218] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 631.525 0.000 631.595 0.140 ; - END - END r0_rd_out[218] - PIN r0_rd_out[219] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 632.855 0.000 632.925 0.140 ; - END - END r0_rd_out[219] - PIN r0_rd_out[220] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 634.185 0.000 634.255 0.140 ; - END - END r0_rd_out[220] - PIN r0_rd_out[221] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 635.515 0.000 635.585 0.140 ; - END - END r0_rd_out[221] - PIN r0_rd_out[222] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 636.845 0.000 636.915 0.140 ; - END - END r0_rd_out[222] - PIN r0_rd_out[223] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 638.175 0.000 638.245 0.140 ; - END - END r0_rd_out[223] - PIN r0_rd_out[224] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 639.505 0.000 639.575 0.140 ; - END - END r0_rd_out[224] - PIN r0_rd_out[225] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 640.835 0.000 640.905 0.140 ; - END - END r0_rd_out[225] - PIN r0_rd_out[226] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 642.165 0.000 642.235 0.140 ; - END - END r0_rd_out[226] - PIN r0_rd_out[227] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 643.495 0.000 643.565 0.140 ; - END - END r0_rd_out[227] - PIN r0_rd_out[228] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 644.825 0.000 644.895 0.140 ; - END - END r0_rd_out[228] - PIN r0_rd_out[229] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 646.155 0.000 646.225 0.140 ; - END - END r0_rd_out[229] - PIN r0_rd_out[230] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 647.485 0.000 647.555 0.140 ; - END - END r0_rd_out[230] - PIN r0_rd_out[231] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 648.815 0.000 648.885 0.140 ; - END - END r0_rd_out[231] - PIN r0_rd_out[232] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 650.145 0.000 650.215 0.140 ; - END - END r0_rd_out[232] - PIN r0_rd_out[233] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 651.475 0.000 651.545 0.140 ; - END - END r0_rd_out[233] - PIN r0_rd_out[234] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 652.805 0.000 652.875 0.140 ; - END - END r0_rd_out[234] - PIN r0_rd_out[235] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 654.135 0.000 654.205 0.140 ; - END - END r0_rd_out[235] - PIN r0_rd_out[236] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 655.465 0.000 655.535 0.140 ; - END - END r0_rd_out[236] - PIN r0_rd_out[237] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 656.795 0.000 656.865 0.140 ; - END - END r0_rd_out[237] - PIN r0_rd_out[238] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 658.125 0.000 658.195 0.140 ; - END - END r0_rd_out[238] - PIN r0_rd_out[239] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 659.455 0.000 659.525 0.140 ; - END - END r0_rd_out[239] - PIN r0_rd_out[240] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 660.785 0.000 660.855 0.140 ; - END - END r0_rd_out[240] - PIN r0_rd_out[241] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 662.115 0.000 662.185 0.140 ; - END - END r0_rd_out[241] - PIN r0_rd_out[242] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 663.445 0.000 663.515 0.140 ; - END - END r0_rd_out[242] - PIN r0_rd_out[243] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 664.775 0.000 664.845 0.140 ; - END - END r0_rd_out[243] - PIN r0_rd_out[244] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 666.105 0.000 666.175 0.140 ; - END - END r0_rd_out[244] - PIN r0_rd_out[245] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 667.435 0.000 667.505 0.140 ; - END - END r0_rd_out[245] - PIN r0_rd_out[246] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 668.765 0.000 668.835 0.140 ; - END - END r0_rd_out[246] - PIN r0_rd_out[247] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 670.095 0.000 670.165 0.140 ; - END - END r0_rd_out[247] - PIN r0_rd_out[248] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 671.425 0.000 671.495 0.140 ; - END - END r0_rd_out[248] - PIN r0_rd_out[249] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 672.755 0.000 672.825 0.140 ; - END - END r0_rd_out[249] - PIN r0_rd_out[250] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 674.085 0.000 674.155 0.140 ; - END - END r0_rd_out[250] - PIN r0_rd_out[251] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 675.415 0.000 675.485 0.140 ; - END - END r0_rd_out[251] - PIN r0_rd_out[252] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 676.745 0.000 676.815 0.140 ; - END - END r0_rd_out[252] - PIN r0_rd_out[253] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 678.075 0.000 678.145 0.140 ; - END - END r0_rd_out[253] - PIN r0_rd_out[254] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 679.405 0.000 679.475 0.140 ; - END - END r0_rd_out[254] - PIN r0_rd_out[255] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 680.735 0.000 680.805 0.140 ; - END - END r0_rd_out[255] - PIN r0_rd_out[256] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 1.105 767.060 1.175 767.200 ; - END - END r0_rd_out[256] - PIN r0_rd_out[257] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 3.575 767.060 3.645 767.200 ; - END - END r0_rd_out[257] - PIN r0_rd_out[258] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 6.045 767.060 6.115 767.200 ; - END - END r0_rd_out[258] - PIN r0_rd_out[259] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 8.515 767.060 8.585 767.200 ; - END - END r0_rd_out[259] - PIN r0_rd_out[260] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 10.985 767.060 11.055 767.200 ; - END - END r0_rd_out[260] - PIN r0_rd_out[261] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 13.455 767.060 13.525 767.200 ; - END - END r0_rd_out[261] - PIN r0_rd_out[262] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 15.925 767.060 15.995 767.200 ; - END - END r0_rd_out[262] - PIN r0_rd_out[263] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 18.395 767.060 18.465 767.200 ; - END - END r0_rd_out[263] - PIN r0_rd_out[264] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 20.865 767.060 20.935 767.200 ; - END - END r0_rd_out[264] - PIN r0_rd_out[265] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 23.335 767.060 23.405 767.200 ; - END - END r0_rd_out[265] - PIN r0_rd_out[266] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 25.805 767.060 25.875 767.200 ; - END - END r0_rd_out[266] - PIN r0_rd_out[267] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 28.275 767.060 28.345 767.200 ; - END - END r0_rd_out[267] - PIN r0_rd_out[268] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 30.745 767.060 30.815 767.200 ; - END - END r0_rd_out[268] - PIN r0_rd_out[269] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 33.215 767.060 33.285 767.200 ; - END - END r0_rd_out[269] - PIN r0_rd_out[270] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 35.685 767.060 35.755 767.200 ; - END - END r0_rd_out[270] - PIN r0_rd_out[271] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 38.155 767.060 38.225 767.200 ; - END - END r0_rd_out[271] - PIN r0_rd_out[272] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 40.625 767.060 40.695 767.200 ; - END - END r0_rd_out[272] - PIN r0_rd_out[273] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 43.095 767.060 43.165 767.200 ; - END - END r0_rd_out[273] - PIN r0_rd_out[274] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 45.565 767.060 45.635 767.200 ; - END - END r0_rd_out[274] - PIN r0_rd_out[275] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 48.035 767.060 48.105 767.200 ; - END - END r0_rd_out[275] - PIN r0_rd_out[276] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 50.505 767.060 50.575 767.200 ; - END - END r0_rd_out[276] - PIN r0_rd_out[277] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 52.975 767.060 53.045 767.200 ; - END - END r0_rd_out[277] - PIN r0_rd_out[278] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 55.445 767.060 55.515 767.200 ; - END - END r0_rd_out[278] - PIN r0_rd_out[279] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 57.915 767.060 57.985 767.200 ; - END - END r0_rd_out[279] - PIN r0_rd_out[280] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 60.385 767.060 60.455 767.200 ; - END - END r0_rd_out[280] - PIN r0_rd_out[281] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 62.855 767.060 62.925 767.200 ; - END - END r0_rd_out[281] - PIN r0_rd_out[282] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 65.325 767.060 65.395 767.200 ; - END - END r0_rd_out[282] - PIN r0_rd_out[283] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 67.795 767.060 67.865 767.200 ; - END - END r0_rd_out[283] - PIN r0_rd_out[284] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 70.265 767.060 70.335 767.200 ; - END - END r0_rd_out[284] - PIN r0_rd_out[285] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 72.735 767.060 72.805 767.200 ; - END - END r0_rd_out[285] - PIN r0_rd_out[286] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 75.205 767.060 75.275 767.200 ; - END - END r0_rd_out[286] - PIN r0_rd_out[287] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 77.675 767.060 77.745 767.200 ; - END - END r0_rd_out[287] - PIN r0_rd_out[288] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 80.145 767.060 80.215 767.200 ; - END - END r0_rd_out[288] - PIN r0_rd_out[289] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 82.615 767.060 82.685 767.200 ; - END - END r0_rd_out[289] - PIN r0_rd_out[290] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 85.085 767.060 85.155 767.200 ; - END - END r0_rd_out[290] - PIN r0_rd_out[291] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 87.555 767.060 87.625 767.200 ; - END - END r0_rd_out[291] - PIN r0_rd_out[292] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 90.025 767.060 90.095 767.200 ; - END - END r0_rd_out[292] - PIN r0_rd_out[293] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 92.495 767.060 92.565 767.200 ; - END - END r0_rd_out[293] - PIN r0_rd_out[294] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 94.965 767.060 95.035 767.200 ; - END - END r0_rd_out[294] - PIN r0_rd_out[295] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 97.435 767.060 97.505 767.200 ; - END - END r0_rd_out[295] - PIN r0_rd_out[296] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 99.905 767.060 99.975 767.200 ; - END - END r0_rd_out[296] - PIN r0_rd_out[297] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 102.375 767.060 102.445 767.200 ; - END - END r0_rd_out[297] - PIN r0_rd_out[298] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 104.845 767.060 104.915 767.200 ; - END - END r0_rd_out[298] - PIN r0_rd_out[299] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 107.315 767.060 107.385 767.200 ; - END - END r0_rd_out[299] - PIN r0_rd_out[300] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 109.785 767.060 109.855 767.200 ; - END - END r0_rd_out[300] - PIN r0_rd_out[301] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 112.255 767.060 112.325 767.200 ; - END - END r0_rd_out[301] - PIN r0_rd_out[302] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 114.725 767.060 114.795 767.200 ; - END - END r0_rd_out[302] - PIN r0_rd_out[303] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 117.195 767.060 117.265 767.200 ; - END - END r0_rd_out[303] - PIN r0_rd_out[304] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 119.665 767.060 119.735 767.200 ; - END - END r0_rd_out[304] - PIN r0_rd_out[305] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 122.135 767.060 122.205 767.200 ; - END - END r0_rd_out[305] - PIN r0_rd_out[306] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 124.605 767.060 124.675 767.200 ; - END - END r0_rd_out[306] - PIN r0_rd_out[307] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 127.075 767.060 127.145 767.200 ; - END - END r0_rd_out[307] - PIN r0_rd_out[308] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 129.545 767.060 129.615 767.200 ; - END - END r0_rd_out[308] - PIN r0_rd_out[309] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 132.015 767.060 132.085 767.200 ; - END - END r0_rd_out[309] - PIN r0_rd_out[310] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 134.485 767.060 134.555 767.200 ; - END - END r0_rd_out[310] - PIN r0_rd_out[311] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 136.955 767.060 137.025 767.200 ; - END - END r0_rd_out[311] - PIN r0_rd_out[312] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 139.425 767.060 139.495 767.200 ; - END - END r0_rd_out[312] - PIN r0_rd_out[313] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 141.895 767.060 141.965 767.200 ; - END - END r0_rd_out[313] - PIN r0_rd_out[314] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 144.365 767.060 144.435 767.200 ; - END - END r0_rd_out[314] - PIN r0_rd_out[315] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 146.835 767.060 146.905 767.200 ; - END - END r0_rd_out[315] - PIN r0_rd_out[316] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 149.305 767.060 149.375 767.200 ; - END - END r0_rd_out[316] - PIN r0_rd_out[317] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 151.775 767.060 151.845 767.200 ; - END - END r0_rd_out[317] - PIN r0_rd_out[318] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 154.245 767.060 154.315 767.200 ; - END - END r0_rd_out[318] - PIN r0_rd_out[319] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 156.715 767.060 156.785 767.200 ; - END - END r0_rd_out[319] - PIN r0_rd_out[320] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 159.185 767.060 159.255 767.200 ; - END - END r0_rd_out[320] - PIN r0_rd_out[321] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 161.655 767.060 161.725 767.200 ; - END - END r0_rd_out[321] - PIN r0_rd_out[322] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 164.125 767.060 164.195 767.200 ; - END - END r0_rd_out[322] - PIN r0_rd_out[323] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 166.595 767.060 166.665 767.200 ; - END - END r0_rd_out[323] - PIN r0_rd_out[324] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 169.065 767.060 169.135 767.200 ; - END - END r0_rd_out[324] - PIN r0_rd_out[325] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 171.535 767.060 171.605 767.200 ; - END - END r0_rd_out[325] - PIN r0_rd_out[326] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 174.005 767.060 174.075 767.200 ; - END - END r0_rd_out[326] - PIN r0_rd_out[327] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 176.475 767.060 176.545 767.200 ; - END - END r0_rd_out[327] - PIN r0_rd_out[328] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 178.945 767.060 179.015 767.200 ; - END - END r0_rd_out[328] - PIN r0_rd_out[329] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 181.415 767.060 181.485 767.200 ; - END - END r0_rd_out[329] - PIN r0_rd_out[330] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 183.885 767.060 183.955 767.200 ; - END - END r0_rd_out[330] - PIN r0_rd_out[331] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 186.355 767.060 186.425 767.200 ; - END - END r0_rd_out[331] - PIN r0_rd_out[332] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 188.825 767.060 188.895 767.200 ; - END - END r0_rd_out[332] - PIN r0_rd_out[333] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 191.295 767.060 191.365 767.200 ; - END - END r0_rd_out[333] - PIN r0_rd_out[334] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 193.765 767.060 193.835 767.200 ; - END - END r0_rd_out[334] - PIN r0_rd_out[335] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 196.235 767.060 196.305 767.200 ; - END - END r0_rd_out[335] - PIN r0_rd_out[336] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 198.705 767.060 198.775 767.200 ; - END - END r0_rd_out[336] - PIN r0_rd_out[337] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 201.175 767.060 201.245 767.200 ; - END - END r0_rd_out[337] - PIN r0_rd_out[338] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 203.645 767.060 203.715 767.200 ; - END - END r0_rd_out[338] - PIN r0_rd_out[339] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 206.115 767.060 206.185 767.200 ; - END - END r0_rd_out[339] - PIN r0_rd_out[340] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 208.585 767.060 208.655 767.200 ; - END - END r0_rd_out[340] - PIN r0_rd_out[341] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 211.055 767.060 211.125 767.200 ; - END - END r0_rd_out[341] - PIN r0_rd_out[342] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 213.525 767.060 213.595 767.200 ; - END - END r0_rd_out[342] - PIN r0_rd_out[343] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 215.995 767.060 216.065 767.200 ; - END - END r0_rd_out[343] - PIN r0_rd_out[344] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 218.465 767.060 218.535 767.200 ; - END - END r0_rd_out[344] - PIN r0_rd_out[345] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 220.935 767.060 221.005 767.200 ; - END - END r0_rd_out[345] - PIN r0_rd_out[346] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 223.405 767.060 223.475 767.200 ; - END - END r0_rd_out[346] - PIN r0_rd_out[347] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 225.875 767.060 225.945 767.200 ; - END - END r0_rd_out[347] - PIN r0_rd_out[348] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 228.345 767.060 228.415 767.200 ; - END - END r0_rd_out[348] - PIN r0_rd_out[349] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 230.815 767.060 230.885 767.200 ; - END - END r0_rd_out[349] - PIN r0_rd_out[350] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 233.285 767.060 233.355 767.200 ; - END - END r0_rd_out[350] - PIN r0_rd_out[351] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 235.755 767.060 235.825 767.200 ; - END - END r0_rd_out[351] - PIN r0_rd_out[352] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 238.225 767.060 238.295 767.200 ; - END - END r0_rd_out[352] - PIN r0_rd_out[353] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 240.695 767.060 240.765 767.200 ; - END - END r0_rd_out[353] - PIN r0_rd_out[354] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 243.165 767.060 243.235 767.200 ; - END - END r0_rd_out[354] - PIN r0_rd_out[355] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 245.635 767.060 245.705 767.200 ; - END - END r0_rd_out[355] - PIN r0_rd_out[356] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 248.105 767.060 248.175 767.200 ; - END - END r0_rd_out[356] - PIN r0_rd_out[357] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 250.575 767.060 250.645 767.200 ; - END - END r0_rd_out[357] - PIN r0_rd_out[358] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 253.045 767.060 253.115 767.200 ; - END - END r0_rd_out[358] - PIN r0_rd_out[359] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 255.515 767.060 255.585 767.200 ; - END - END r0_rd_out[359] - PIN r0_rd_out[360] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 257.985 767.060 258.055 767.200 ; - END - END r0_rd_out[360] - PIN r0_rd_out[361] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 260.455 767.060 260.525 767.200 ; - END - END r0_rd_out[361] - PIN r0_rd_out[362] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 262.925 767.060 262.995 767.200 ; - END - END r0_rd_out[362] - PIN r0_rd_out[363] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 265.395 767.060 265.465 767.200 ; - END - END r0_rd_out[363] - PIN r0_rd_out[364] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 267.865 767.060 267.935 767.200 ; - END - END r0_rd_out[364] - PIN r0_rd_out[365] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 270.335 767.060 270.405 767.200 ; - END - END r0_rd_out[365] - PIN r0_rd_out[366] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 272.805 767.060 272.875 767.200 ; - END - END r0_rd_out[366] - PIN r0_rd_out[367] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 275.275 767.060 275.345 767.200 ; - END - END r0_rd_out[367] - PIN r0_rd_out[368] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 277.745 767.060 277.815 767.200 ; - END - END r0_rd_out[368] - PIN r0_rd_out[369] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 280.215 767.060 280.285 767.200 ; - END - END r0_rd_out[369] - PIN r0_rd_out[370] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 282.685 767.060 282.755 767.200 ; - END - END r0_rd_out[370] - PIN r0_rd_out[371] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 285.155 767.060 285.225 767.200 ; - END - END r0_rd_out[371] - PIN r0_rd_out[372] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 287.625 767.060 287.695 767.200 ; - END - END r0_rd_out[372] - PIN r0_rd_out[373] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 290.095 767.060 290.165 767.200 ; - END - END r0_rd_out[373] - PIN r0_rd_out[374] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 292.565 767.060 292.635 767.200 ; - END - END r0_rd_out[374] - PIN r0_rd_out[375] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 295.035 767.060 295.105 767.200 ; - END - END r0_rd_out[375] - PIN r0_rd_out[376] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 297.505 767.060 297.575 767.200 ; - END - END r0_rd_out[376] - PIN r0_rd_out[377] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 299.975 767.060 300.045 767.200 ; - END - END r0_rd_out[377] - PIN r0_rd_out[378] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 302.445 767.060 302.515 767.200 ; - END - END r0_rd_out[378] - PIN r0_rd_out[379] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 304.915 767.060 304.985 767.200 ; - END - END r0_rd_out[379] - PIN r0_rd_out[380] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 307.385 767.060 307.455 767.200 ; - END - END r0_rd_out[380] - PIN r0_rd_out[381] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 309.855 767.060 309.925 767.200 ; - END - END r0_rd_out[381] - PIN r0_rd_out[382] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 312.325 767.060 312.395 767.200 ; - END - END r0_rd_out[382] - PIN r0_rd_out[383] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 314.795 767.060 314.865 767.200 ; - END - END r0_rd_out[383] - PIN r0_rd_out[384] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 317.265 767.060 317.335 767.200 ; - END - END r0_rd_out[384] - PIN r0_rd_out[385] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 319.735 767.060 319.805 767.200 ; - END - END r0_rd_out[385] - PIN r0_rd_out[386] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 322.205 767.060 322.275 767.200 ; - END - END r0_rd_out[386] - PIN r0_rd_out[387] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 324.675 767.060 324.745 767.200 ; - END - END r0_rd_out[387] - PIN r0_rd_out[388] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 327.145 767.060 327.215 767.200 ; - END - END r0_rd_out[388] - PIN r0_rd_out[389] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 329.615 767.060 329.685 767.200 ; - END - END r0_rd_out[389] - PIN r0_rd_out[390] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 332.085 767.060 332.155 767.200 ; - END - END r0_rd_out[390] - PIN r0_rd_out[391] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 334.555 767.060 334.625 767.200 ; - END - END r0_rd_out[391] - PIN r0_rd_out[392] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 337.025 767.060 337.095 767.200 ; - END - END r0_rd_out[392] - PIN r0_rd_out[393] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 339.495 767.060 339.565 767.200 ; - END - END r0_rd_out[393] - PIN r0_rd_out[394] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 341.965 767.060 342.035 767.200 ; - END - END r0_rd_out[394] - PIN r0_rd_out[395] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 344.435 767.060 344.505 767.200 ; - END - END r0_rd_out[395] - PIN r0_rd_out[396] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 346.905 767.060 346.975 767.200 ; - END - END r0_rd_out[396] - PIN r0_rd_out[397] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 349.375 767.060 349.445 767.200 ; - END - END r0_rd_out[397] - PIN r0_rd_out[398] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 351.845 767.060 351.915 767.200 ; - END - END r0_rd_out[398] - PIN r0_rd_out[399] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 354.315 767.060 354.385 767.200 ; - END - END r0_rd_out[399] - PIN r0_rd_out[400] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 356.785 767.060 356.855 767.200 ; - END - END r0_rd_out[400] - PIN r0_rd_out[401] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 359.255 767.060 359.325 767.200 ; - END - END r0_rd_out[401] - PIN r0_rd_out[402] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 361.725 767.060 361.795 767.200 ; - END - END r0_rd_out[402] - PIN r0_rd_out[403] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 364.195 767.060 364.265 767.200 ; - END - END r0_rd_out[403] - PIN r0_rd_out[404] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 366.665 767.060 366.735 767.200 ; - END - END r0_rd_out[404] - PIN r0_rd_out[405] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 369.135 767.060 369.205 767.200 ; - END - END r0_rd_out[405] - PIN r0_rd_out[406] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 371.605 767.060 371.675 767.200 ; - END - END r0_rd_out[406] - PIN r0_rd_out[407] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 374.075 767.060 374.145 767.200 ; - END - END r0_rd_out[407] - PIN r0_rd_out[408] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 376.545 767.060 376.615 767.200 ; - END - END r0_rd_out[408] - PIN r0_rd_out[409] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 379.015 767.060 379.085 767.200 ; - END - END r0_rd_out[409] - PIN r0_rd_out[410] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 381.485 767.060 381.555 767.200 ; - END - END r0_rd_out[410] - PIN r0_rd_out[411] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 383.955 767.060 384.025 767.200 ; - END - END r0_rd_out[411] - PIN r0_rd_out[412] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 386.425 767.060 386.495 767.200 ; - END - END r0_rd_out[412] - PIN r0_rd_out[413] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 388.895 767.060 388.965 767.200 ; - END - END r0_rd_out[413] - PIN r0_rd_out[414] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 391.365 767.060 391.435 767.200 ; - END - END r0_rd_out[414] - PIN r0_rd_out[415] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 393.835 767.060 393.905 767.200 ; - END - END r0_rd_out[415] - PIN r0_rd_out[416] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 396.305 767.060 396.375 767.200 ; - END - END r0_rd_out[416] - PIN r0_rd_out[417] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 398.775 767.060 398.845 767.200 ; - END - END r0_rd_out[417] - PIN r0_rd_out[418] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 401.245 767.060 401.315 767.200 ; - END - END r0_rd_out[418] - PIN r0_rd_out[419] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 403.715 767.060 403.785 767.200 ; - END - END r0_rd_out[419] - PIN r0_rd_out[420] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 406.185 767.060 406.255 767.200 ; - END - END r0_rd_out[420] - PIN r0_rd_out[421] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 408.655 767.060 408.725 767.200 ; - END - END r0_rd_out[421] - PIN r0_rd_out[422] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 411.125 767.060 411.195 767.200 ; - END - END r0_rd_out[422] - PIN r0_rd_out[423] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 413.595 767.060 413.665 767.200 ; - END - END r0_rd_out[423] - PIN r0_rd_out[424] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 416.065 767.060 416.135 767.200 ; - END - END r0_rd_out[424] - PIN r0_rd_out[425] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 418.535 767.060 418.605 767.200 ; - END - END r0_rd_out[425] - PIN r0_rd_out[426] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 421.005 767.060 421.075 767.200 ; - END - END r0_rd_out[426] - PIN r0_rd_out[427] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 423.475 767.060 423.545 767.200 ; - END - END r0_rd_out[427] - PIN r0_rd_out[428] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 425.945 767.060 426.015 767.200 ; - END - END r0_rd_out[428] - PIN r0_rd_out[429] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 428.415 767.060 428.485 767.200 ; - END - END r0_rd_out[429] - PIN r0_rd_out[430] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 430.885 767.060 430.955 767.200 ; - END - END r0_rd_out[430] - PIN r0_rd_out[431] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 433.355 767.060 433.425 767.200 ; - END - END r0_rd_out[431] - PIN r0_rd_out[432] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 435.825 767.060 435.895 767.200 ; - END - END r0_rd_out[432] - PIN r0_rd_out[433] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 438.295 767.060 438.365 767.200 ; - END - END r0_rd_out[433] - PIN r0_rd_out[434] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 440.765 767.060 440.835 767.200 ; - END - END r0_rd_out[434] - PIN r0_rd_out[435] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 443.235 767.060 443.305 767.200 ; - END - END r0_rd_out[435] - PIN r0_rd_out[436] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 445.705 767.060 445.775 767.200 ; - END - END r0_rd_out[436] - PIN r0_rd_out[437] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 448.175 767.060 448.245 767.200 ; - END - END r0_rd_out[437] - PIN r0_rd_out[438] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 450.645 767.060 450.715 767.200 ; - END - END r0_rd_out[438] - PIN r0_rd_out[439] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 453.115 767.060 453.185 767.200 ; - END - END r0_rd_out[439] - PIN r0_rd_out[440] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 455.585 767.060 455.655 767.200 ; - END - END r0_rd_out[440] - PIN r0_rd_out[441] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 458.055 767.060 458.125 767.200 ; - END - END r0_rd_out[441] - PIN r0_rd_out[442] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 460.525 767.060 460.595 767.200 ; - END - END r0_rd_out[442] - PIN r0_rd_out[443] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 462.995 767.060 463.065 767.200 ; - END - END r0_rd_out[443] - PIN r0_rd_out[444] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 465.465 767.060 465.535 767.200 ; - END - END r0_rd_out[444] - PIN r0_rd_out[445] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 467.935 767.060 468.005 767.200 ; - END - END r0_rd_out[445] - PIN r0_rd_out[446] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 470.405 767.060 470.475 767.200 ; - END - END r0_rd_out[446] - PIN r0_rd_out[447] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 472.875 767.060 472.945 767.200 ; - END - END r0_rd_out[447] - PIN r0_rd_out[448] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 475.345 767.060 475.415 767.200 ; - END - END r0_rd_out[448] - PIN r0_rd_out[449] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 477.815 767.060 477.885 767.200 ; - END - END r0_rd_out[449] - PIN r0_rd_out[450] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 480.285 767.060 480.355 767.200 ; - END - END r0_rd_out[450] - PIN r0_rd_out[451] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 482.755 767.060 482.825 767.200 ; - END - END r0_rd_out[451] - PIN r0_rd_out[452] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 485.225 767.060 485.295 767.200 ; - END - END r0_rd_out[452] - PIN r0_rd_out[453] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 487.695 767.060 487.765 767.200 ; - END - END r0_rd_out[453] - PIN r0_rd_out[454] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 490.165 767.060 490.235 767.200 ; - END - END r0_rd_out[454] - PIN r0_rd_out[455] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 492.635 767.060 492.705 767.200 ; - END - END r0_rd_out[455] - PIN r0_rd_out[456] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 495.105 767.060 495.175 767.200 ; - END - END r0_rd_out[456] - PIN r0_rd_out[457] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 497.575 767.060 497.645 767.200 ; - END - END r0_rd_out[457] - PIN r0_rd_out[458] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 500.045 767.060 500.115 767.200 ; - END - END r0_rd_out[458] - PIN r0_rd_out[459] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 502.515 767.060 502.585 767.200 ; - END - END r0_rd_out[459] - PIN r0_rd_out[460] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 504.985 767.060 505.055 767.200 ; - END - END r0_rd_out[460] - PIN r0_rd_out[461] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 507.455 767.060 507.525 767.200 ; - END - END r0_rd_out[461] - PIN r0_rd_out[462] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 509.925 767.060 509.995 767.200 ; - END - END r0_rd_out[462] - PIN r0_rd_out[463] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 512.395 767.060 512.465 767.200 ; - END - END r0_rd_out[463] - PIN r0_rd_out[464] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 514.865 767.060 514.935 767.200 ; - END - END r0_rd_out[464] - PIN r0_rd_out[465] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 517.335 767.060 517.405 767.200 ; - END - END r0_rd_out[465] - PIN r0_rd_out[466] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 519.805 767.060 519.875 767.200 ; - END - END r0_rd_out[466] - PIN r0_rd_out[467] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 522.275 767.060 522.345 767.200 ; - END - END r0_rd_out[467] - PIN r0_rd_out[468] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 524.745 767.060 524.815 767.200 ; - END - END r0_rd_out[468] - PIN r0_rd_out[469] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 527.215 767.060 527.285 767.200 ; - END - END r0_rd_out[469] - PIN r0_rd_out[470] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 529.685 767.060 529.755 767.200 ; - END - END r0_rd_out[470] - PIN r0_rd_out[471] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 532.155 767.060 532.225 767.200 ; - END - END r0_rd_out[471] - PIN r0_rd_out[472] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 534.625 767.060 534.695 767.200 ; - END - END r0_rd_out[472] - PIN r0_rd_out[473] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 537.095 767.060 537.165 767.200 ; - END - END r0_rd_out[473] - PIN r0_rd_out[474] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 539.565 767.060 539.635 767.200 ; - END - END r0_rd_out[474] - PIN r0_rd_out[475] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 542.035 767.060 542.105 767.200 ; - END - END r0_rd_out[475] - PIN r0_rd_out[476] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 544.505 767.060 544.575 767.200 ; - END - END r0_rd_out[476] - PIN r0_rd_out[477] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 546.975 767.060 547.045 767.200 ; - END - END r0_rd_out[477] - PIN r0_rd_out[478] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 549.445 767.060 549.515 767.200 ; - END - END r0_rd_out[478] - PIN r0_rd_out[479] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 551.915 767.060 551.985 767.200 ; - END - END r0_rd_out[479] - PIN r0_rd_out[480] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 554.385 767.060 554.455 767.200 ; - END - END r0_rd_out[480] - PIN r0_rd_out[481] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 556.855 767.060 556.925 767.200 ; - END - END r0_rd_out[481] - PIN r0_rd_out[482] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 559.325 767.060 559.395 767.200 ; - END - END r0_rd_out[482] - PIN r0_rd_out[483] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 561.795 767.060 561.865 767.200 ; - END - END r0_rd_out[483] - PIN r0_rd_out[484] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 564.265 767.060 564.335 767.200 ; - END - END r0_rd_out[484] - PIN r0_rd_out[485] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 566.735 767.060 566.805 767.200 ; - END - END r0_rd_out[485] - PIN r0_rd_out[486] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 569.205 767.060 569.275 767.200 ; - END - END r0_rd_out[486] - PIN r0_rd_out[487] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 571.675 767.060 571.745 767.200 ; - END - END r0_rd_out[487] - PIN r0_rd_out[488] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 574.145 767.060 574.215 767.200 ; - END - END r0_rd_out[488] - PIN r0_rd_out[489] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 576.615 767.060 576.685 767.200 ; - END - END r0_rd_out[489] - PIN r0_rd_out[490] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 579.085 767.060 579.155 767.200 ; - END - END r0_rd_out[490] - PIN r0_rd_out[491] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 581.555 767.060 581.625 767.200 ; - END - END r0_rd_out[491] - PIN r0_rd_out[492] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 584.025 767.060 584.095 767.200 ; - END - END r0_rd_out[492] - PIN r0_rd_out[493] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 586.495 767.060 586.565 767.200 ; - END - END r0_rd_out[493] - PIN r0_rd_out[494] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 588.965 767.060 589.035 767.200 ; - END - END r0_rd_out[494] - PIN r0_rd_out[495] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 591.435 767.060 591.505 767.200 ; - END - END r0_rd_out[495] - PIN r0_rd_out[496] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 593.905 767.060 593.975 767.200 ; - END - END r0_rd_out[496] - PIN r0_rd_out[497] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 596.375 767.060 596.445 767.200 ; - END - END r0_rd_out[497] - PIN r0_rd_out[498] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 598.845 767.060 598.915 767.200 ; - END - END r0_rd_out[498] - PIN r0_rd_out[499] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 601.315 767.060 601.385 767.200 ; - END - END r0_rd_out[499] - PIN r0_rd_out[500] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 603.785 767.060 603.855 767.200 ; - END - END r0_rd_out[500] - PIN r0_rd_out[501] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 606.255 767.060 606.325 767.200 ; - END - END r0_rd_out[501] - PIN r0_rd_out[502] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 608.725 767.060 608.795 767.200 ; - END - END r0_rd_out[502] - PIN r0_rd_out[503] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 611.195 767.060 611.265 767.200 ; - END - END r0_rd_out[503] - PIN r0_rd_out[504] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 613.665 767.060 613.735 767.200 ; - END - END r0_rd_out[504] - PIN r0_rd_out[505] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 616.135 767.060 616.205 767.200 ; - END - END r0_rd_out[505] - PIN r0_rd_out[506] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 618.605 767.060 618.675 767.200 ; - END - END r0_rd_out[506] - PIN r0_rd_out[507] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 621.075 767.060 621.145 767.200 ; - END - END r0_rd_out[507] - PIN r0_rd_out[508] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 623.545 767.060 623.615 767.200 ; - END - END r0_rd_out[508] - PIN r0_rd_out[509] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 626.015 767.060 626.085 767.200 ; - END - END r0_rd_out[509] - PIN r0_rd_out[510] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 628.485 767.060 628.555 767.200 ; - END - END r0_rd_out[510] - PIN r0_rd_out[511] - DIRECTION OUTPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 630.955 767.060 631.025 767.200 ; - END - END r0_rd_out[511] - PIN w0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 717.605 0.140 717.675 ; - END - END w0_addr_in[0] - PIN w0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 723.205 0.140 723.275 ; - END - END w0_addr_in[1] - PIN w0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 728.805 0.140 728.875 ; - END - END w0_addr_in[2] - PIN w0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 734.405 0.140 734.475 ; - END - END w0_addr_in[3] - PIN w0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 717.605 689.130 717.675 ; - END - END w0_addr_in[4] - PIN w0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 723.205 689.130 723.275 ; - END - END w0_addr_in[5] - PIN w0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 728.805 689.130 728.875 ; - END - END w0_addr_in[6] - PIN w0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 734.405 689.130 734.475 ; - END - END w0_addr_in[7] - PIN r0_addr_in[0] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 740.005 0.140 740.075 ; - END - END r0_addr_in[0] - PIN r0_addr_in[1] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 745.605 0.140 745.675 ; - END - END r0_addr_in[1] - PIN r0_addr_in[2] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 751.205 0.140 751.275 ; - END - END r0_addr_in[2] - PIN r0_addr_in[3] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 0.000 756.805 0.140 756.875 ; - END - END r0_addr_in[3] - PIN r0_addr_in[4] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 740.005 689.130 740.075 ; - END - END r0_addr_in[4] - PIN r0_addr_in[5] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 745.605 689.130 745.675 ; - END - END r0_addr_in[5] - PIN r0_addr_in[6] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 751.205 689.130 751.275 ; - END - END r0_addr_in[6] - PIN r0_addr_in[7] - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal3 ; - RECT 688.990 756.805 689.130 756.875 ; - END - END r0_addr_in[7] - PIN w0_we_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 633.425 767.060 633.495 767.200 ; - END - END w0_we_in - PIN w0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 635.895 767.060 635.965 767.200 ; - END - END w0_ce_in - PIN w0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 638.365 767.060 638.435 767.200 ; - END - END w0_clk - PIN r0_ce_in - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 640.835 767.060 640.905 767.200 ; - END - END r0_ce_in - PIN r0_clk - DIRECTION INPUT ; - USE SIGNAL ; - SHAPE ABUTMENT ; - PORT - LAYER metal2 ; - RECT 643.305 767.060 643.375 767.200 ; - END - END r0_clk - PIN VSS - DIRECTION INOUT ; - USE GROUND ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 766.500 ; - RECT 2.670 0.700 2.950 766.500 ; - RECT 4.910 0.700 5.190 766.500 ; - RECT 7.150 0.700 7.430 766.500 ; - RECT 9.390 0.700 9.670 766.500 ; - RECT 11.630 0.700 11.910 766.500 ; - RECT 13.870 0.700 14.150 766.500 ; - RECT 16.110 0.700 16.390 766.500 ; - RECT 18.350 0.700 18.630 766.500 ; - RECT 20.590 0.700 20.870 766.500 ; - RECT 22.830 0.700 23.110 766.500 ; - RECT 25.070 0.700 25.350 766.500 ; - RECT 27.310 0.700 27.590 766.500 ; - RECT 29.550 0.700 29.830 766.500 ; - RECT 31.790 0.700 32.070 766.500 ; - RECT 34.030 0.700 34.310 766.500 ; - RECT 36.270 0.700 36.550 766.500 ; - RECT 38.510 0.700 38.790 766.500 ; - RECT 40.750 0.700 41.030 766.500 ; - RECT 42.990 0.700 43.270 766.500 ; - RECT 45.230 0.700 45.510 766.500 ; - RECT 47.470 0.700 47.750 766.500 ; - RECT 49.710 0.700 49.990 766.500 ; - RECT 51.950 0.700 52.230 766.500 ; - RECT 54.190 0.700 54.470 766.500 ; - RECT 56.430 0.700 56.710 766.500 ; - RECT 58.670 0.700 58.950 766.500 ; - RECT 60.910 0.700 61.190 766.500 ; - RECT 63.150 0.700 63.430 766.500 ; - RECT 65.390 0.700 65.670 766.500 ; - RECT 67.630 0.700 67.910 766.500 ; - RECT 69.870 0.700 70.150 766.500 ; - RECT 72.110 0.700 72.390 766.500 ; - RECT 74.350 0.700 74.630 766.500 ; - RECT 76.590 0.700 76.870 766.500 ; - RECT 78.830 0.700 79.110 766.500 ; - RECT 81.070 0.700 81.350 766.500 ; - RECT 83.310 0.700 83.590 766.500 ; - RECT 85.550 0.700 85.830 766.500 ; - RECT 87.790 0.700 88.070 766.500 ; - RECT 90.030 0.700 90.310 766.500 ; - RECT 92.270 0.700 92.550 766.500 ; - RECT 94.510 0.700 94.790 766.500 ; - RECT 96.750 0.700 97.030 766.500 ; - RECT 98.990 0.700 99.270 766.500 ; - RECT 101.230 0.700 101.510 766.500 ; - RECT 103.470 0.700 103.750 766.500 ; - RECT 105.710 0.700 105.990 766.500 ; - RECT 107.950 0.700 108.230 766.500 ; - RECT 110.190 0.700 110.470 766.500 ; - RECT 112.430 0.700 112.710 766.500 ; - RECT 114.670 0.700 114.950 766.500 ; - RECT 116.910 0.700 117.190 766.500 ; - RECT 119.150 0.700 119.430 766.500 ; - RECT 121.390 0.700 121.670 766.500 ; - RECT 123.630 0.700 123.910 766.500 ; - RECT 125.870 0.700 126.150 766.500 ; - RECT 128.110 0.700 128.390 766.500 ; - RECT 130.350 0.700 130.630 766.500 ; - RECT 132.590 0.700 132.870 766.500 ; - RECT 134.830 0.700 135.110 766.500 ; - RECT 137.070 0.700 137.350 766.500 ; - RECT 139.310 0.700 139.590 766.500 ; - RECT 141.550 0.700 141.830 766.500 ; - RECT 143.790 0.700 144.070 766.500 ; - RECT 146.030 0.700 146.310 766.500 ; - RECT 148.270 0.700 148.550 766.500 ; - RECT 150.510 0.700 150.790 766.500 ; - RECT 152.750 0.700 153.030 766.500 ; - RECT 154.990 0.700 155.270 766.500 ; - RECT 157.230 0.700 157.510 766.500 ; - RECT 159.470 0.700 159.750 766.500 ; - RECT 161.710 0.700 161.990 766.500 ; - RECT 163.950 0.700 164.230 766.500 ; - RECT 166.190 0.700 166.470 766.500 ; - RECT 168.430 0.700 168.710 766.500 ; - RECT 170.670 0.700 170.950 766.500 ; - RECT 172.910 0.700 173.190 766.500 ; - RECT 175.150 0.700 175.430 766.500 ; - RECT 177.390 0.700 177.670 766.500 ; - RECT 179.630 0.700 179.910 766.500 ; - RECT 181.870 0.700 182.150 766.500 ; - RECT 184.110 0.700 184.390 766.500 ; - RECT 186.350 0.700 186.630 766.500 ; - RECT 188.590 0.700 188.870 766.500 ; - RECT 190.830 0.700 191.110 766.500 ; - RECT 193.070 0.700 193.350 766.500 ; - RECT 195.310 0.700 195.590 766.500 ; - RECT 197.550 0.700 197.830 766.500 ; - RECT 199.790 0.700 200.070 766.500 ; - RECT 202.030 0.700 202.310 766.500 ; - RECT 204.270 0.700 204.550 766.500 ; - RECT 206.510 0.700 206.790 766.500 ; - RECT 208.750 0.700 209.030 766.500 ; - RECT 210.990 0.700 211.270 766.500 ; - RECT 213.230 0.700 213.510 766.500 ; - RECT 215.470 0.700 215.750 766.500 ; - RECT 217.710 0.700 217.990 766.500 ; - RECT 219.950 0.700 220.230 766.500 ; - RECT 222.190 0.700 222.470 766.500 ; - RECT 224.430 0.700 224.710 766.500 ; - RECT 226.670 0.700 226.950 766.500 ; - RECT 228.910 0.700 229.190 766.500 ; - RECT 231.150 0.700 231.430 766.500 ; - RECT 233.390 0.700 233.670 766.500 ; - RECT 235.630 0.700 235.910 766.500 ; - RECT 237.870 0.700 238.150 766.500 ; - RECT 240.110 0.700 240.390 766.500 ; - RECT 242.350 0.700 242.630 766.500 ; - RECT 244.590 0.700 244.870 766.500 ; - RECT 246.830 0.700 247.110 766.500 ; - RECT 249.070 0.700 249.350 766.500 ; - RECT 251.310 0.700 251.590 766.500 ; - RECT 253.550 0.700 253.830 766.500 ; - RECT 255.790 0.700 256.070 766.500 ; - RECT 258.030 0.700 258.310 766.500 ; - RECT 260.270 0.700 260.550 766.500 ; - RECT 262.510 0.700 262.790 766.500 ; - RECT 264.750 0.700 265.030 766.500 ; - RECT 266.990 0.700 267.270 766.500 ; - RECT 269.230 0.700 269.510 766.500 ; - RECT 271.470 0.700 271.750 766.500 ; - RECT 273.710 0.700 273.990 766.500 ; - RECT 275.950 0.700 276.230 766.500 ; - RECT 278.190 0.700 278.470 766.500 ; - RECT 280.430 0.700 280.710 766.500 ; - RECT 282.670 0.700 282.950 766.500 ; - RECT 284.910 0.700 285.190 766.500 ; - RECT 287.150 0.700 287.430 766.500 ; - RECT 289.390 0.700 289.670 766.500 ; - RECT 291.630 0.700 291.910 766.500 ; - RECT 293.870 0.700 294.150 766.500 ; - RECT 296.110 0.700 296.390 766.500 ; - RECT 298.350 0.700 298.630 766.500 ; - RECT 300.590 0.700 300.870 766.500 ; - RECT 302.830 0.700 303.110 766.500 ; - RECT 305.070 0.700 305.350 766.500 ; - RECT 307.310 0.700 307.590 766.500 ; - RECT 309.550 0.700 309.830 766.500 ; - RECT 311.790 0.700 312.070 766.500 ; - RECT 314.030 0.700 314.310 766.500 ; - RECT 316.270 0.700 316.550 766.500 ; - RECT 318.510 0.700 318.790 766.500 ; - RECT 320.750 0.700 321.030 766.500 ; - RECT 322.990 0.700 323.270 766.500 ; - RECT 325.230 0.700 325.510 766.500 ; - RECT 327.470 0.700 327.750 766.500 ; - RECT 329.710 0.700 329.990 766.500 ; - RECT 331.950 0.700 332.230 766.500 ; - RECT 334.190 0.700 334.470 766.500 ; - RECT 336.430 0.700 336.710 766.500 ; - RECT 338.670 0.700 338.950 766.500 ; - RECT 340.910 0.700 341.190 766.500 ; - RECT 343.150 0.700 343.430 766.500 ; - RECT 345.390 0.700 345.670 766.500 ; - RECT 347.630 0.700 347.910 766.500 ; - RECT 349.870 0.700 350.150 766.500 ; - RECT 352.110 0.700 352.390 766.500 ; - RECT 354.350 0.700 354.630 766.500 ; - RECT 356.590 0.700 356.870 766.500 ; - RECT 358.830 0.700 359.110 766.500 ; - RECT 361.070 0.700 361.350 766.500 ; - RECT 363.310 0.700 363.590 766.500 ; - RECT 365.550 0.700 365.830 766.500 ; - RECT 367.790 0.700 368.070 766.500 ; - RECT 370.030 0.700 370.310 766.500 ; - RECT 372.270 0.700 372.550 766.500 ; - RECT 374.510 0.700 374.790 766.500 ; - RECT 376.750 0.700 377.030 766.500 ; - RECT 378.990 0.700 379.270 766.500 ; - RECT 381.230 0.700 381.510 766.500 ; - RECT 383.470 0.700 383.750 766.500 ; - RECT 385.710 0.700 385.990 766.500 ; - RECT 387.950 0.700 388.230 766.500 ; - RECT 390.190 0.700 390.470 766.500 ; - RECT 392.430 0.700 392.710 766.500 ; - RECT 394.670 0.700 394.950 766.500 ; - RECT 396.910 0.700 397.190 766.500 ; - RECT 399.150 0.700 399.430 766.500 ; - RECT 401.390 0.700 401.670 766.500 ; - RECT 403.630 0.700 403.910 766.500 ; - RECT 405.870 0.700 406.150 766.500 ; - RECT 408.110 0.700 408.390 766.500 ; - RECT 410.350 0.700 410.630 766.500 ; - RECT 412.590 0.700 412.870 766.500 ; - RECT 414.830 0.700 415.110 766.500 ; - RECT 417.070 0.700 417.350 766.500 ; - RECT 419.310 0.700 419.590 766.500 ; - RECT 421.550 0.700 421.830 766.500 ; - RECT 423.790 0.700 424.070 766.500 ; - RECT 426.030 0.700 426.310 766.500 ; - RECT 428.270 0.700 428.550 766.500 ; - RECT 430.510 0.700 430.790 766.500 ; - RECT 432.750 0.700 433.030 766.500 ; - RECT 434.990 0.700 435.270 766.500 ; - RECT 437.230 0.700 437.510 766.500 ; - RECT 439.470 0.700 439.750 766.500 ; - RECT 441.710 0.700 441.990 766.500 ; - RECT 443.950 0.700 444.230 766.500 ; - RECT 446.190 0.700 446.470 766.500 ; - RECT 448.430 0.700 448.710 766.500 ; - RECT 450.670 0.700 450.950 766.500 ; - RECT 452.910 0.700 453.190 766.500 ; - RECT 455.150 0.700 455.430 766.500 ; - RECT 457.390 0.700 457.670 766.500 ; - RECT 459.630 0.700 459.910 766.500 ; - RECT 461.870 0.700 462.150 766.500 ; - RECT 464.110 0.700 464.390 766.500 ; - RECT 466.350 0.700 466.630 766.500 ; - RECT 468.590 0.700 468.870 766.500 ; - RECT 470.830 0.700 471.110 766.500 ; - RECT 473.070 0.700 473.350 766.500 ; - RECT 475.310 0.700 475.590 766.500 ; - RECT 477.550 0.700 477.830 766.500 ; - RECT 479.790 0.700 480.070 766.500 ; - RECT 482.030 0.700 482.310 766.500 ; - RECT 484.270 0.700 484.550 766.500 ; - RECT 486.510 0.700 486.790 766.500 ; - RECT 488.750 0.700 489.030 766.500 ; - RECT 490.990 0.700 491.270 766.500 ; - RECT 493.230 0.700 493.510 766.500 ; - RECT 495.470 0.700 495.750 766.500 ; - RECT 497.710 0.700 497.990 766.500 ; - RECT 499.950 0.700 500.230 766.500 ; - RECT 502.190 0.700 502.470 766.500 ; - RECT 504.430 0.700 504.710 766.500 ; - RECT 506.670 0.700 506.950 766.500 ; - RECT 508.910 0.700 509.190 766.500 ; - RECT 511.150 0.700 511.430 766.500 ; - RECT 513.390 0.700 513.670 766.500 ; - RECT 515.630 0.700 515.910 766.500 ; - RECT 517.870 0.700 518.150 766.500 ; - RECT 520.110 0.700 520.390 766.500 ; - RECT 522.350 0.700 522.630 766.500 ; - RECT 524.590 0.700 524.870 766.500 ; - RECT 526.830 0.700 527.110 766.500 ; - RECT 529.070 0.700 529.350 766.500 ; - RECT 531.310 0.700 531.590 766.500 ; - RECT 533.550 0.700 533.830 766.500 ; - RECT 535.790 0.700 536.070 766.500 ; - RECT 538.030 0.700 538.310 766.500 ; - RECT 540.270 0.700 540.550 766.500 ; - RECT 542.510 0.700 542.790 766.500 ; - RECT 544.750 0.700 545.030 766.500 ; - RECT 546.990 0.700 547.270 766.500 ; - RECT 549.230 0.700 549.510 766.500 ; - RECT 551.470 0.700 551.750 766.500 ; - RECT 553.710 0.700 553.990 766.500 ; - RECT 555.950 0.700 556.230 766.500 ; - RECT 558.190 0.700 558.470 766.500 ; - RECT 560.430 0.700 560.710 766.500 ; - RECT 562.670 0.700 562.950 766.500 ; - RECT 564.910 0.700 565.190 766.500 ; - RECT 567.150 0.700 567.430 766.500 ; - RECT 569.390 0.700 569.670 766.500 ; - RECT 571.630 0.700 571.910 766.500 ; - RECT 573.870 0.700 574.150 766.500 ; - RECT 576.110 0.700 576.390 766.500 ; - RECT 578.350 0.700 578.630 766.500 ; - RECT 580.590 0.700 580.870 766.500 ; - RECT 582.830 0.700 583.110 766.500 ; - RECT 585.070 0.700 585.350 766.500 ; - RECT 587.310 0.700 587.590 766.500 ; - RECT 589.550 0.700 589.830 766.500 ; - RECT 591.790 0.700 592.070 766.500 ; - RECT 594.030 0.700 594.310 766.500 ; - RECT 596.270 0.700 596.550 766.500 ; - RECT 598.510 0.700 598.790 766.500 ; - RECT 600.750 0.700 601.030 766.500 ; - RECT 602.990 0.700 603.270 766.500 ; - RECT 605.230 0.700 605.510 766.500 ; - RECT 607.470 0.700 607.750 766.500 ; - RECT 609.710 0.700 609.990 766.500 ; - RECT 611.950 0.700 612.230 766.500 ; - RECT 614.190 0.700 614.470 766.500 ; - RECT 616.430 0.700 616.710 766.500 ; - RECT 618.670 0.700 618.950 766.500 ; - RECT 620.910 0.700 621.190 766.500 ; - RECT 623.150 0.700 623.430 766.500 ; - RECT 625.390 0.700 625.670 766.500 ; - RECT 627.630 0.700 627.910 766.500 ; - RECT 629.870 0.700 630.150 766.500 ; - RECT 632.110 0.700 632.390 766.500 ; - RECT 634.350 0.700 634.630 766.500 ; - RECT 636.590 0.700 636.870 766.500 ; - RECT 638.830 0.700 639.110 766.500 ; - RECT 641.070 0.700 641.350 766.500 ; - RECT 643.310 0.700 643.590 766.500 ; - RECT 645.550 0.700 645.830 766.500 ; - RECT 647.790 0.700 648.070 766.500 ; - RECT 650.030 0.700 650.310 766.500 ; - RECT 652.270 0.700 652.550 766.500 ; - RECT 654.510 0.700 654.790 766.500 ; - RECT 656.750 0.700 657.030 766.500 ; - RECT 658.990 0.700 659.270 766.500 ; - RECT 661.230 0.700 661.510 766.500 ; - RECT 663.470 0.700 663.750 766.500 ; - RECT 665.710 0.700 665.990 766.500 ; - RECT 667.950 0.700 668.230 766.500 ; - RECT 670.190 0.700 670.470 766.500 ; - RECT 672.430 0.700 672.710 766.500 ; - RECT 674.670 0.700 674.950 766.500 ; - RECT 676.910 0.700 677.190 766.500 ; - RECT 679.150 0.700 679.430 766.500 ; - RECT 681.390 0.700 681.670 766.500 ; - RECT 683.630 0.700 683.910 766.500 ; - RECT 685.870 0.700 686.150 766.500 ; - RECT 688.110 0.700 688.390 766.500 ; - END - END VSS - PIN VDD - DIRECTION INOUT ; - USE POWER ; - PORT - LAYER metal4 ; - RECT 0.430 0.700 0.710 766.500 ; - RECT 2.670 0.700 2.950 766.500 ; - RECT 4.910 0.700 5.190 766.500 ; - RECT 7.150 0.700 7.430 766.500 ; - RECT 9.390 0.700 9.670 766.500 ; - RECT 11.630 0.700 11.910 766.500 ; - RECT 13.870 0.700 14.150 766.500 ; - RECT 16.110 0.700 16.390 766.500 ; - RECT 18.350 0.700 18.630 766.500 ; - RECT 20.590 0.700 20.870 766.500 ; - RECT 22.830 0.700 23.110 766.500 ; - RECT 25.070 0.700 25.350 766.500 ; - RECT 27.310 0.700 27.590 766.500 ; - RECT 29.550 0.700 29.830 766.500 ; - RECT 31.790 0.700 32.070 766.500 ; - RECT 34.030 0.700 34.310 766.500 ; - RECT 36.270 0.700 36.550 766.500 ; - RECT 38.510 0.700 38.790 766.500 ; - RECT 40.750 0.700 41.030 766.500 ; - RECT 42.990 0.700 43.270 766.500 ; - RECT 45.230 0.700 45.510 766.500 ; - RECT 47.470 0.700 47.750 766.500 ; - RECT 49.710 0.700 49.990 766.500 ; - RECT 51.950 0.700 52.230 766.500 ; - RECT 54.190 0.700 54.470 766.500 ; - RECT 56.430 0.700 56.710 766.500 ; - RECT 58.670 0.700 58.950 766.500 ; - RECT 60.910 0.700 61.190 766.500 ; - RECT 63.150 0.700 63.430 766.500 ; - RECT 65.390 0.700 65.670 766.500 ; - RECT 67.630 0.700 67.910 766.500 ; - RECT 69.870 0.700 70.150 766.500 ; - RECT 72.110 0.700 72.390 766.500 ; - RECT 74.350 0.700 74.630 766.500 ; - RECT 76.590 0.700 76.870 766.500 ; - RECT 78.830 0.700 79.110 766.500 ; - RECT 81.070 0.700 81.350 766.500 ; - RECT 83.310 0.700 83.590 766.500 ; - RECT 85.550 0.700 85.830 766.500 ; - RECT 87.790 0.700 88.070 766.500 ; - RECT 90.030 0.700 90.310 766.500 ; - RECT 92.270 0.700 92.550 766.500 ; - RECT 94.510 0.700 94.790 766.500 ; - RECT 96.750 0.700 97.030 766.500 ; - RECT 98.990 0.700 99.270 766.500 ; - RECT 101.230 0.700 101.510 766.500 ; - RECT 103.470 0.700 103.750 766.500 ; - RECT 105.710 0.700 105.990 766.500 ; - RECT 107.950 0.700 108.230 766.500 ; - RECT 110.190 0.700 110.470 766.500 ; - RECT 112.430 0.700 112.710 766.500 ; - RECT 114.670 0.700 114.950 766.500 ; - RECT 116.910 0.700 117.190 766.500 ; - RECT 119.150 0.700 119.430 766.500 ; - RECT 121.390 0.700 121.670 766.500 ; - RECT 123.630 0.700 123.910 766.500 ; - RECT 125.870 0.700 126.150 766.500 ; - RECT 128.110 0.700 128.390 766.500 ; - RECT 130.350 0.700 130.630 766.500 ; - RECT 132.590 0.700 132.870 766.500 ; - RECT 134.830 0.700 135.110 766.500 ; - RECT 137.070 0.700 137.350 766.500 ; - RECT 139.310 0.700 139.590 766.500 ; - RECT 141.550 0.700 141.830 766.500 ; - RECT 143.790 0.700 144.070 766.500 ; - RECT 146.030 0.700 146.310 766.500 ; - RECT 148.270 0.700 148.550 766.500 ; - RECT 150.510 0.700 150.790 766.500 ; - RECT 152.750 0.700 153.030 766.500 ; - RECT 154.990 0.700 155.270 766.500 ; - RECT 157.230 0.700 157.510 766.500 ; - RECT 159.470 0.700 159.750 766.500 ; - RECT 161.710 0.700 161.990 766.500 ; - RECT 163.950 0.700 164.230 766.500 ; - RECT 166.190 0.700 166.470 766.500 ; - RECT 168.430 0.700 168.710 766.500 ; - RECT 170.670 0.700 170.950 766.500 ; - RECT 172.910 0.700 173.190 766.500 ; - RECT 175.150 0.700 175.430 766.500 ; - RECT 177.390 0.700 177.670 766.500 ; - RECT 179.630 0.700 179.910 766.500 ; - RECT 181.870 0.700 182.150 766.500 ; - RECT 184.110 0.700 184.390 766.500 ; - RECT 186.350 0.700 186.630 766.500 ; - RECT 188.590 0.700 188.870 766.500 ; - RECT 190.830 0.700 191.110 766.500 ; - RECT 193.070 0.700 193.350 766.500 ; - RECT 195.310 0.700 195.590 766.500 ; - RECT 197.550 0.700 197.830 766.500 ; - RECT 199.790 0.700 200.070 766.500 ; - RECT 202.030 0.700 202.310 766.500 ; - RECT 204.270 0.700 204.550 766.500 ; - RECT 206.510 0.700 206.790 766.500 ; - RECT 208.750 0.700 209.030 766.500 ; - RECT 210.990 0.700 211.270 766.500 ; - RECT 213.230 0.700 213.510 766.500 ; - RECT 215.470 0.700 215.750 766.500 ; - RECT 217.710 0.700 217.990 766.500 ; - RECT 219.950 0.700 220.230 766.500 ; - RECT 222.190 0.700 222.470 766.500 ; - RECT 224.430 0.700 224.710 766.500 ; - RECT 226.670 0.700 226.950 766.500 ; - RECT 228.910 0.700 229.190 766.500 ; - RECT 231.150 0.700 231.430 766.500 ; - RECT 233.390 0.700 233.670 766.500 ; - RECT 235.630 0.700 235.910 766.500 ; - RECT 237.870 0.700 238.150 766.500 ; - RECT 240.110 0.700 240.390 766.500 ; - RECT 242.350 0.700 242.630 766.500 ; - RECT 244.590 0.700 244.870 766.500 ; - RECT 246.830 0.700 247.110 766.500 ; - RECT 249.070 0.700 249.350 766.500 ; - RECT 251.310 0.700 251.590 766.500 ; - RECT 253.550 0.700 253.830 766.500 ; - RECT 255.790 0.700 256.070 766.500 ; - RECT 258.030 0.700 258.310 766.500 ; - RECT 260.270 0.700 260.550 766.500 ; - RECT 262.510 0.700 262.790 766.500 ; - RECT 264.750 0.700 265.030 766.500 ; - RECT 266.990 0.700 267.270 766.500 ; - RECT 269.230 0.700 269.510 766.500 ; - RECT 271.470 0.700 271.750 766.500 ; - RECT 273.710 0.700 273.990 766.500 ; - RECT 275.950 0.700 276.230 766.500 ; - RECT 278.190 0.700 278.470 766.500 ; - RECT 280.430 0.700 280.710 766.500 ; - RECT 282.670 0.700 282.950 766.500 ; - RECT 284.910 0.700 285.190 766.500 ; - RECT 287.150 0.700 287.430 766.500 ; - RECT 289.390 0.700 289.670 766.500 ; - RECT 291.630 0.700 291.910 766.500 ; - RECT 293.870 0.700 294.150 766.500 ; - RECT 296.110 0.700 296.390 766.500 ; - RECT 298.350 0.700 298.630 766.500 ; - RECT 300.590 0.700 300.870 766.500 ; - RECT 302.830 0.700 303.110 766.500 ; - RECT 305.070 0.700 305.350 766.500 ; - RECT 307.310 0.700 307.590 766.500 ; - RECT 309.550 0.700 309.830 766.500 ; - RECT 311.790 0.700 312.070 766.500 ; - RECT 314.030 0.700 314.310 766.500 ; - RECT 316.270 0.700 316.550 766.500 ; - RECT 318.510 0.700 318.790 766.500 ; - RECT 320.750 0.700 321.030 766.500 ; - RECT 322.990 0.700 323.270 766.500 ; - RECT 325.230 0.700 325.510 766.500 ; - RECT 327.470 0.700 327.750 766.500 ; - RECT 329.710 0.700 329.990 766.500 ; - RECT 331.950 0.700 332.230 766.500 ; - RECT 334.190 0.700 334.470 766.500 ; - RECT 336.430 0.700 336.710 766.500 ; - RECT 338.670 0.700 338.950 766.500 ; - RECT 340.910 0.700 341.190 766.500 ; - RECT 343.150 0.700 343.430 766.500 ; - RECT 345.390 0.700 345.670 766.500 ; - RECT 347.630 0.700 347.910 766.500 ; - RECT 349.870 0.700 350.150 766.500 ; - RECT 352.110 0.700 352.390 766.500 ; - RECT 354.350 0.700 354.630 766.500 ; - RECT 356.590 0.700 356.870 766.500 ; - RECT 358.830 0.700 359.110 766.500 ; - RECT 361.070 0.700 361.350 766.500 ; - RECT 363.310 0.700 363.590 766.500 ; - RECT 365.550 0.700 365.830 766.500 ; - RECT 367.790 0.700 368.070 766.500 ; - RECT 370.030 0.700 370.310 766.500 ; - RECT 372.270 0.700 372.550 766.500 ; - RECT 374.510 0.700 374.790 766.500 ; - RECT 376.750 0.700 377.030 766.500 ; - RECT 378.990 0.700 379.270 766.500 ; - RECT 381.230 0.700 381.510 766.500 ; - RECT 383.470 0.700 383.750 766.500 ; - RECT 385.710 0.700 385.990 766.500 ; - RECT 387.950 0.700 388.230 766.500 ; - RECT 390.190 0.700 390.470 766.500 ; - RECT 392.430 0.700 392.710 766.500 ; - RECT 394.670 0.700 394.950 766.500 ; - RECT 396.910 0.700 397.190 766.500 ; - RECT 399.150 0.700 399.430 766.500 ; - RECT 401.390 0.700 401.670 766.500 ; - RECT 403.630 0.700 403.910 766.500 ; - RECT 405.870 0.700 406.150 766.500 ; - RECT 408.110 0.700 408.390 766.500 ; - RECT 410.350 0.700 410.630 766.500 ; - RECT 412.590 0.700 412.870 766.500 ; - RECT 414.830 0.700 415.110 766.500 ; - RECT 417.070 0.700 417.350 766.500 ; - RECT 419.310 0.700 419.590 766.500 ; - RECT 421.550 0.700 421.830 766.500 ; - RECT 423.790 0.700 424.070 766.500 ; - RECT 426.030 0.700 426.310 766.500 ; - RECT 428.270 0.700 428.550 766.500 ; - RECT 430.510 0.700 430.790 766.500 ; - RECT 432.750 0.700 433.030 766.500 ; - RECT 434.990 0.700 435.270 766.500 ; - RECT 437.230 0.700 437.510 766.500 ; - RECT 439.470 0.700 439.750 766.500 ; - RECT 441.710 0.700 441.990 766.500 ; - RECT 443.950 0.700 444.230 766.500 ; - RECT 446.190 0.700 446.470 766.500 ; - RECT 448.430 0.700 448.710 766.500 ; - RECT 450.670 0.700 450.950 766.500 ; - RECT 452.910 0.700 453.190 766.500 ; - RECT 455.150 0.700 455.430 766.500 ; - RECT 457.390 0.700 457.670 766.500 ; - RECT 459.630 0.700 459.910 766.500 ; - RECT 461.870 0.700 462.150 766.500 ; - RECT 464.110 0.700 464.390 766.500 ; - RECT 466.350 0.700 466.630 766.500 ; - RECT 468.590 0.700 468.870 766.500 ; - RECT 470.830 0.700 471.110 766.500 ; - RECT 473.070 0.700 473.350 766.500 ; - RECT 475.310 0.700 475.590 766.500 ; - RECT 477.550 0.700 477.830 766.500 ; - RECT 479.790 0.700 480.070 766.500 ; - RECT 482.030 0.700 482.310 766.500 ; - RECT 484.270 0.700 484.550 766.500 ; - RECT 486.510 0.700 486.790 766.500 ; - RECT 488.750 0.700 489.030 766.500 ; - RECT 490.990 0.700 491.270 766.500 ; - RECT 493.230 0.700 493.510 766.500 ; - RECT 495.470 0.700 495.750 766.500 ; - RECT 497.710 0.700 497.990 766.500 ; - RECT 499.950 0.700 500.230 766.500 ; - RECT 502.190 0.700 502.470 766.500 ; - RECT 504.430 0.700 504.710 766.500 ; - RECT 506.670 0.700 506.950 766.500 ; - RECT 508.910 0.700 509.190 766.500 ; - RECT 511.150 0.700 511.430 766.500 ; - RECT 513.390 0.700 513.670 766.500 ; - RECT 515.630 0.700 515.910 766.500 ; - RECT 517.870 0.700 518.150 766.500 ; - RECT 520.110 0.700 520.390 766.500 ; - RECT 522.350 0.700 522.630 766.500 ; - RECT 524.590 0.700 524.870 766.500 ; - RECT 526.830 0.700 527.110 766.500 ; - RECT 529.070 0.700 529.350 766.500 ; - RECT 531.310 0.700 531.590 766.500 ; - RECT 533.550 0.700 533.830 766.500 ; - RECT 535.790 0.700 536.070 766.500 ; - RECT 538.030 0.700 538.310 766.500 ; - RECT 540.270 0.700 540.550 766.500 ; - RECT 542.510 0.700 542.790 766.500 ; - RECT 544.750 0.700 545.030 766.500 ; - RECT 546.990 0.700 547.270 766.500 ; - RECT 549.230 0.700 549.510 766.500 ; - RECT 551.470 0.700 551.750 766.500 ; - RECT 553.710 0.700 553.990 766.500 ; - RECT 555.950 0.700 556.230 766.500 ; - RECT 558.190 0.700 558.470 766.500 ; - RECT 560.430 0.700 560.710 766.500 ; - RECT 562.670 0.700 562.950 766.500 ; - RECT 564.910 0.700 565.190 766.500 ; - RECT 567.150 0.700 567.430 766.500 ; - RECT 569.390 0.700 569.670 766.500 ; - RECT 571.630 0.700 571.910 766.500 ; - RECT 573.870 0.700 574.150 766.500 ; - RECT 576.110 0.700 576.390 766.500 ; - RECT 578.350 0.700 578.630 766.500 ; - RECT 580.590 0.700 580.870 766.500 ; - RECT 582.830 0.700 583.110 766.500 ; - RECT 585.070 0.700 585.350 766.500 ; - RECT 587.310 0.700 587.590 766.500 ; - RECT 589.550 0.700 589.830 766.500 ; - RECT 591.790 0.700 592.070 766.500 ; - RECT 594.030 0.700 594.310 766.500 ; - RECT 596.270 0.700 596.550 766.500 ; - RECT 598.510 0.700 598.790 766.500 ; - RECT 600.750 0.700 601.030 766.500 ; - RECT 602.990 0.700 603.270 766.500 ; - RECT 605.230 0.700 605.510 766.500 ; - RECT 607.470 0.700 607.750 766.500 ; - RECT 609.710 0.700 609.990 766.500 ; - RECT 611.950 0.700 612.230 766.500 ; - RECT 614.190 0.700 614.470 766.500 ; - RECT 616.430 0.700 616.710 766.500 ; - RECT 618.670 0.700 618.950 766.500 ; - RECT 620.910 0.700 621.190 766.500 ; - RECT 623.150 0.700 623.430 766.500 ; - RECT 625.390 0.700 625.670 766.500 ; - RECT 627.630 0.700 627.910 766.500 ; - RECT 629.870 0.700 630.150 766.500 ; - RECT 632.110 0.700 632.390 766.500 ; - RECT 634.350 0.700 634.630 766.500 ; - RECT 636.590 0.700 636.870 766.500 ; - RECT 638.830 0.700 639.110 766.500 ; - RECT 641.070 0.700 641.350 766.500 ; - RECT 643.310 0.700 643.590 766.500 ; - RECT 645.550 0.700 645.830 766.500 ; - RECT 647.790 0.700 648.070 766.500 ; - RECT 650.030 0.700 650.310 766.500 ; - RECT 652.270 0.700 652.550 766.500 ; - RECT 654.510 0.700 654.790 766.500 ; - RECT 656.750 0.700 657.030 766.500 ; - RECT 658.990 0.700 659.270 766.500 ; - RECT 661.230 0.700 661.510 766.500 ; - RECT 663.470 0.700 663.750 766.500 ; - RECT 665.710 0.700 665.990 766.500 ; - RECT 667.950 0.700 668.230 766.500 ; - RECT 670.190 0.700 670.470 766.500 ; - RECT 672.430 0.700 672.710 766.500 ; - RECT 674.670 0.700 674.950 766.500 ; - RECT 676.910 0.700 677.190 766.500 ; - RECT 679.150 0.700 679.430 766.500 ; - RECT 681.390 0.700 681.670 766.500 ; - RECT 683.630 0.700 683.910 766.500 ; - RECT 685.870 0.700 686.150 766.500 ; - RECT 688.110 0.700 688.390 766.500 ; - END - END VDD - OBS - LAYER metal1 ; - RECT 0 0 689.130 767.200 ; - LAYER metal2 ; - RECT 0 0 689.130 767.200 ; - LAYER metal3 ; - RECT 0 0 689.130 767.200 ; - LAYER metal4 ; - RECT 0 0 689.130 767.200 ; - LAYER OVERLAP ; - RECT 0 0 689.130 767.200 ; - END -END fakeram_512x256_1r1w - -END LIBRARY diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib deleted file mode 100644 index 518a35a..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_16x52_1r1w.lib +++ /dev/null @@ -1,515 +0,0 @@ -library(fakeram_16x52_1r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:32Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_16x52_1r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_16x52_1r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_16x52_1r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_16x52_1r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_16x52_1r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_16x52_1r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 16; - bit_from : 15; - bit_to : 0 ; - downto : true ; - } - type (fakeram_16x52_1r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 6; - bit_from : 5; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_16x52_1r1w) { - area : 4192.160; - interface_timing : true; - memory() { - type : ram; - address_width : 6; - word_width : 16; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.188 ; - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.416, 1.416") - } - fall_power(fakeram_16x52_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.416, 1.416") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.188 ; - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.416, 1.416") - } - fall_power(fakeram_16x52_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.416, 1.416") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_16x52_1r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_16x52_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.246, 0.246", \ - "0.246, 0.246" \ - ) - } - cell_fall(fakeram_16x52_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.246, 0.246", \ - "0.246, 0.246" \ - ) - } - rise_transition(fakeram_16x52_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_16x52_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_16x52_1r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_16x52_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_16x52_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_16x52_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - fall_power(fakeram_16x52_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.014, 0.014") - } - } - } - cell_leakage_power : 181.512; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib deleted file mode 100644 index 5f1359a..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_18x256_1r1w.lib +++ /dev/null @@ -1,515 +0,0 @@ -library(fakeram_18x256_1r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:33Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_18x256_1r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_18x256_1r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_18x256_1r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_18x256_1r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_18x256_1r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_18x256_1r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 18; - bit_from : 17; - bit_to : 0 ; - downto : true ; - } - type (fakeram_18x256_1r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_18x256_1r1w) { - area : 18060.336; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 18; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.231 ; - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.231, 3.231") - } - fall_power(fakeram_18x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.231, 3.231") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.231 ; - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.231, 3.231") - } - fall_power(fakeram_18x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.231, 3.231") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_18x256_1r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_18x256_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.288, 0.288", \ - "0.288, 0.288" \ - ) - } - cell_fall(fakeram_18x256_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.288, 0.288", \ - "0.288, 0.288" \ - ) - } - rise_transition(fakeram_18x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_18x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_18x256_1r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_18x256_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_18x256_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_18x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - fall_power(fakeram_18x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.032, 0.032") - } - } - } - cell_leakage_power : 643.248; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib deleted file mode 100644 index 0d035ae..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_1x256_1r1w.lib +++ /dev/null @@ -1,515 +0,0 @@ -library(fakeram_1x256_1r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:32Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_1x256_1r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_1x256_1r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_1x256_1r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_1x256_1r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_1x256_1r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_1x256_1r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 1; - bit_from : 0; - bit_to : 0 ; - downto : true ; - } - type (fakeram_1x256_1r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_1x256_1r1w) { - area : 21443.058; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 1; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.232 ; - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("2.219, 2.219") - } - fall_power(fakeram_1x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("2.219, 2.219") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.232 ; - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("2.219, 2.219") - } - fall_power(fakeram_1x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("2.219, 2.219") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_1x256_1r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_1x256_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.331, 0.331", \ - "0.331, 0.331" \ - ) - } - cell_fall(fakeram_1x256_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.331, 0.331", \ - "0.331, 0.331" \ - ) - } - rise_transition(fakeram_1x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_1x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_1x256_1r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_1x256_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_1x256_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_1x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - fall_power(fakeram_1x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.022, 0.022") - } - } - } - cell_leakage_power : 497.834; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib deleted file mode 100644 index bc6c36f..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_20x64_1r1w.lib +++ /dev/null @@ -1,515 +0,0 @@ -library(fakeram_20x64_1r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:38Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_20x64_1r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_20x64_1r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_20x64_1r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_20x64_1r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_20x64_1r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_20x64_1r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 20; - bit_from : 19; - bit_to : 0 ; - downto : true ; - } - type (fakeram_20x64_1r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 6; - bit_from : 5; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_20x64_1r1w) { - area : 4847.850; - interface_timing : true; - memory() { - type : ram; - address_width : 6; - word_width : 20; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.188 ; - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.677, 1.677") - } - fall_power(fakeram_20x64_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.677, 1.677") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.188 ; - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.677, 1.677") - } - fall_power(fakeram_20x64_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.677, 1.677") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_20x64_1r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_20x64_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.248, 0.248", \ - "0.248, 0.248" \ - ) - } - cell_fall(fakeram_20x64_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.248, 0.248", \ - "0.248, 0.248" \ - ) - } - rise_transition(fakeram_20x64_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_20x64_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_20x64_1r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_20x64_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_20x64_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - fall_power(fakeram_20x64_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.017, 0.017") - } - } - } - cell_leakage_power : 194.910; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib deleted file mode 100644 index 98ef9d0..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_20x64_2r1w.lib +++ /dev/null @@ -1,678 +0,0 @@ -library(fakeram_20x64_2r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:39Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_20x64_2r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_20x64_2r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_20x64_2r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_20x64_2r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_20x64_2r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_20x64_2r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 20; - bit_from : 19; - bit_to : 0 ; - downto : true ; - } - type (fakeram_20x64_2r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 6; - bit_from : 5; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_20x64_2r1w) { - area : 13304.256; - interface_timing : true; - memory() { - type : ram; - address_width : 6; - word_width : 20; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.194 ; - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.922, 1.922") - } - fall_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.922, 1.922") - } - } - } - - pin(r1_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.194 ; - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.922, 1.922") - } - fall_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.922, 1.922") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.194 ; - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.922, 1.922") - } - fall_power(fakeram_20x64_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("1.922, 1.922") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_20x64_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.242, 0.242", \ - "0.242, 0.242" \ - ) - } - cell_fall(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.242, 0.242", \ - "0.242, 0.242" \ - ) - } - rise_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - bus(r1_rd_out) { - bus_type : fakeram_20x64_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r1_addr_in; - } - timing() { - related_pin : "r1_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.242, 0.242", \ - "0.242, 0.242" \ - ) - } - cell_fall(fakeram_20x64_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.242, 0.242", \ - "0.242, 0.242" \ - ) - } - rise_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_20x64_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - pin(r1_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_20x64_2r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_20x64_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - bus(r1_addr_in) { - bus_type : fakeram_20x64_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_20x64_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_20x64_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - fall_power(fakeram_20x64_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.019, 0.019") - } - } - } - cell_leakage_power : 298.917; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib deleted file mode 100644 index 48b1405..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_32x128_2r1w.lib +++ /dev/null @@ -1,678 +0,0 @@ -library(fakeram_32x128_2r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:40Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_32x128_2r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_32x128_2r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_32x128_2r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_32x128_2r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_32x128_2r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_32x128_2r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 32; - bit_from : 31; - bit_to : 0 ; - downto : true ; - } - type (fakeram_32x128_2r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 7; - bit_from : 6; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_32x128_2r1w) { - area : 24235.526; - interface_timing : true; - memory() { - type : ram; - address_width : 7; - word_width : 32; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.222 ; - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.740, 3.740") - } - fall_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.740, 3.740") - } - } - } - - pin(r1_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.222 ; - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.740, 3.740") - } - fall_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.740, 3.740") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.222 ; - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.740, 3.740") - } - fall_power(fakeram_32x128_2r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("3.740, 3.740") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_32x128_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.293, 0.293", \ - "0.293, 0.293" \ - ) - } - cell_fall(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.293, 0.293", \ - "0.293, 0.293" \ - ) - } - rise_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - bus(r1_rd_out) { - bus_type : fakeram_32x128_2r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r1_addr_in; - } - timing() { - related_pin : "r1_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.293, 0.293", \ - "0.293, 0.293" \ - ) - } - cell_fall(fakeram_32x128_2r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.293, 0.293", \ - "0.293, 0.293" \ - ) - } - rise_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_32x128_2r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - pin(r1_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_32x128_2r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_32x128_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - bus(r1_addr_in) { - bus_type : fakeram_32x128_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r1_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r1_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_32x128_2r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_32x128_2r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - fall_power(fakeram_32x128_2r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("0.037, 0.037") - } - } - } - cell_leakage_power : 569.925; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib deleted file mode 100644 index 9eecc3b..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_512x2048_1r1w.lib +++ /dev/null @@ -1,515 +0,0 @@ -library(fakeram_512x2048_1r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:37Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_512x2048_1r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_512x2048_1r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_512x2048_1r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_512x2048_1r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_512x2048_1r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_512x2048_1r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 512; - bit_from : 511; - bit_to : 0 ; - downto : true ; - } - type (fakeram_512x2048_1r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 11; - bit_from : 10; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_512x2048_1r1w) { - area : 2433261.600; - interface_timing : true; - memory() { - type : ram; - address_width : 11; - word_width : 512; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.642 ; - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("460.071, 460.071") - } - fall_power(fakeram_512x2048_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("460.071, 460.071") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.642 ; - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("460.071, 460.071") - } - fall_power(fakeram_512x2048_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("460.071, 460.071") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_512x2048_1r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_512x2048_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "1.367, 1.367", \ - "1.367, 1.367" \ - ) - } - cell_fall(fakeram_512x2048_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "1.367, 1.367", \ - "1.367, 1.367" \ - ) - } - rise_transition(fakeram_512x2048_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_512x2048_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_512x2048_1r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_512x2048_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_512x2048_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x2048_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - fall_power(fakeram_512x2048_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("4.601, 4.601") - } - } - } - cell_leakage_power : 26453.200; -} - -} diff --git a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib b/designs/nangate45/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib deleted file mode 100644 index bbb8102..0000000 --- a/designs/nangate45/NyuziProcessor/sram/lib/fakeram_512x256_1r1w.lib +++ /dev/null @@ -1,515 +0,0 @@ -library(fakeram_512x256_1r1w) { - technology (cmos); - delay_model : table_lookup; - revision : 1.0; - date : "2025-10-10 17:45:34Z"; - comment : "SRAM"; - time_unit : "1ns"; - voltage_unit : "1V"; - current_unit : "1uA"; - leakage_power_unit : "1uW"; - nom_process : 1; - nom_temperature : 25.000; - nom_voltage : 1.1; - capacitive_load_unit (1,pf); - - pulling_resistance_unit : "1kohm"; - - operating_conditions(tt_1.0_25.0) { - process : 1; - temperature : 25.000; - voltage : 1.1; - tree_type : balanced_tree; - } - - /* default attributes */ - default_cell_leakage_power : 0; - default_fanout_load : 1; - default_inout_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_output_pin_cap : 0.0; - default_input_pin_cap : 0.0; - default_max_transition : 0.227; - - default_operating_conditions : tt_1.0_25.0; - default_leakage_power_density : 0.0; - - /* additional header data */ - slew_derate_from_library : 1.000; - slew_lower_threshold_pct_fall : 20.000; - slew_upper_threshold_pct_fall : 80.000; - slew_lower_threshold_pct_rise : 20.000; - slew_upper_threshold_pct_rise : 80.000; - input_threshold_pct_fall : 50.000; - input_threshold_pct_rise : 50.000; - output_threshold_pct_fall : 50.000; - output_threshold_pct_rise : 50.000; - - - lu_table_template(fakeram_512x256_1r1w_mem_out_delay_template) { - variable_1 : input_net_transition; - variable_2 : total_output_net_capacitance; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - lu_table_template(fakeram_512x256_1r1w_mem_out_slew_template) { - variable_1 : total_output_net_capacitance; - index_1 ("1000, 1001"); - } - lu_table_template(fakeram_512x256_1r1w_constraint_template) { - variable_1 : related_pin_transition; - variable_2 : constrained_pin_transition; - index_1 ("1000, 1001"); - index_2 ("1000, 1001"); - } - power_lut_template(fakeram_512x256_1r1w_energy_template_clkslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - power_lut_template(fakeram_512x256_1r1w_energy_template_sigslew) { - variable_1 : input_transition_time; - index_1 ("1000, 1001"); - } - library_features(report_delay_calculation); - type (fakeram_512x256_1r1w_DATA) { - base_type : array ; - data_type : bit ; - bit_width : 512; - bit_from : 511; - bit_to : 0 ; - downto : true ; - } - type (fakeram_512x256_1r1w_ADDRESS) { - base_type : array ; - data_type : bit ; - bit_width : 8; - bit_from : 7; - bit_to : 0 ; - downto : true ; - } -cell(fakeram_512x256_1r1w) { - area : 528700.536; - interface_timing : true; - memory() { - type : ram; - address_width : 8; - word_width : 512; - } - pin(r0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.531 ; - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("124.013, 124.013") - } - fall_power(fakeram_512x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("124.013, 124.013") - } - } - } - - pin(w0_clk) { - direction : input; - capacitance : 0.025; - clock : true; - min_period : 0.531 ; - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("124.013, 124.013") - } - fall_power(fakeram_512x256_1r1w_energy_template_clkslew) { - index_1 ("0.009, 0.227"); - values ("124.013, 124.013") - } - } - } - - bus(r0_rd_out) { - bus_type : fakeram_512x256_1r1w_DATA; - direction : output; - max_capacitance : 0.500; - memory_read() { - address : r0_addr_in; - } - timing() { - related_pin : "r0_clk" ; - timing_type : rising_edge; - timing_sense : non_unate; - cell_rise(fakeram_512x256_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.628, 0.628", \ - "0.628, 0.628" \ - ) - } - cell_fall(fakeram_512x256_1r1w_mem_out_delay_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.005, 0.500"); - values ( \ - "0.628, 0.628", \ - "0.628, 0.628" \ - ) - } - rise_transition(fakeram_512x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - fall_transition(fakeram_512x256_1r1w_mem_out_slew_template) { - index_1 ("0.005, 0.500"); - values ("0.009, 0.227") - } - } - } - pin(w0_we_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - } - pin(r0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - } - pin(w0_ce_in) { - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - } - bus(w0_wd_in) { - bus_type : fakeram_512x256_1r1w_DATA; - memory_write() { - address : w0_addr_in; - clocked_on : "w0_clk"; - } - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - when : "(! (w0_we_in) )"; - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - internal_power(){ - when : "(w0_we_in)"; - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - } - bus(r0_addr_in) { - bus_type : fakeram_512x256_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : r0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : r0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - } - bus(w0_addr_in) { - bus_type : fakeram_512x256_1r1w_ADDRESS; - direction : input; - capacitance : 0.005; - timing() { - related_pin : w0_clk; - timing_type : setup_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - timing() { - related_pin : w0_clk; - timing_type : hold_rising ; - rise_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - fall_constraint(fakeram_512x256_1r1w_constraint_template) { - index_1 ("0.009, 0.227"); - index_2 ("0.009, 0.227"); - values ( \ - "0.050, 0.050", \ - "0.050, 0.050" \ - ) - } - } - internal_power(){ - rise_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - fall_power(fakeram_512x256_1r1w_energy_template_sigslew) { - index_1 ("0.009, 0.227"); - values ("1.240, 1.240") - } - } - } - cell_leakage_power : 6033.320; -} - -} diff --git a/designs/nangate45/lfsr_prbs_gen/config.mk b/designs/nangate45/lfsr_prbs_gen/config.mk deleted file mode 100644 index ea5bb62..0000000 --- a/designs/nangate45/lfsr_prbs_gen/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -export DESIGN_NAME = lfsr_prbs_gen -export PLATFORM = nangate45 - --include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk - -export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export CORE_UTILIZATION = 20 -export PLACE_DENSITY_LB_ADDON = 0.20 -export TNS_END_PERCENT = 100 \ No newline at end of file diff --git a/designs/nangate45/lfsr_prbs_gen/constraint.sdc b/designs/nangate45/lfsr_prbs_gen/constraint.sdc deleted file mode 100644 index 6f7d84f..0000000 --- a/designs/nangate45/lfsr_prbs_gen/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design lfsr_prbs_gen - -set clk_name core_clock -set clk_port_name clk -set clk_period 0.46 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/sky130hd/lfsr_prbs_gen/config.mk b/designs/sky130hd/lfsr_prbs_gen/config.mk deleted file mode 100644 index 6325389..0000000 --- a/designs/sky130hd/lfsr_prbs_gen/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -export DESIGN_NAME = lfsr_prbs_gen -export PLATFORM = sky130hd - --include $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/verilog.mk - -export SDC_FILE = $(BENCH_DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc - -export CORE_UTILIZATION = 40 -export TNS_END_PERCENT = 100 diff --git a/designs/sky130hd/lfsr_prbs_gen/constraint.sdc b/designs/sky130hd/lfsr_prbs_gen/constraint.sdc deleted file mode 100644 index f3ea545..0000000 --- a/designs/sky130hd/lfsr_prbs_gen/constraint.sdc +++ /dev/null @@ -1,15 +0,0 @@ -current_design lfsr_prbs_gen - -set clk_name core_clock -set clk_port_name clk -set clk_period 1.1 -set clk_io_pct 0.2 - -set clk_port [get_ports $clk_port_name] - -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] diff --git a/designs/src/NVDLA/LICENSE b/designs/src/NVDLA/LICENSE new file mode 100644 index 0000000..f4422e6 --- /dev/null +++ b/designs/src/NVDLA/LICENSE @@ -0,0 +1,207 @@ +NVIDIA Open NVDLA License and Agreement v1.0 + +NVIDIA's Deep Learning Accelerator ("NVDLA") is a hardware design that +accelerates inferencing in System-on-a-Chip designs. Subject to the terms +and conditions of this Open NVDLA License and Agreement, NVIDIA offers its +NVDLA design on a royalty-free, open-source basis, promoting the adoption of +deep learning inferencing in third-party designs and IoT devices, and +expanding the overall market for AI. + +By exercising the rights granted hereunder, You accept and agree to be bound +by these terms and conditions. You are granted the rights hereunder in +consideration of Your agreement to these terms and conditions. If You do +not agree to these terms and conditions, do not download or use the NVDLA +Specification. + +If You are agreeing to these terms and conditions on behalf of a legal +entity, You represent that You have the legal authority to bind the legal +entity to these terms and conditions. + +In consideration of the mutual covenants contained herein, You agree as +follows: + +1. DEFINITIONS. + +"NVDLA Specification" shall mean and include the design information, code, +and documentation used in designing a deep learning accelerator or creating +a DLA Product, which may include: HDL, netlists, GDSII files, mask works, +architectural descriptions, interface specifications, microcode, software +source code, documentation source, and configuration files. + +"Contributor" shall mean NVIDIA and any owner of a NVDLA Contribution that +NVIDIA has incorporated within the NVDLA Specification. + +"Derivative Work" shall mean any work that is based on (or derived from) +any portion of the NVDLA Specification. For the purposes of this License, +Derivative Works shall not include works that remain separable from, or +merely link (or bind by name) to the interfaces of, any portion of the NVDLA +Specification and Derivative Works thereof. + +"DLA Product" shall mean a semiconductor chip product or portions thereof +designed or manufactured in accordance with a NVDLA Specification or a +Derivative Work, including any semiconductor chip product embodying a mask +work included in a NVDLA Specification or a Derivative Work. + +"NVDLA" means NVIDIA's Deep Learning Accelerator, a hardware design that +accelerates inferencing in System-on-a-Chip designs. + +"NVDLA Contribution" shall mean any work of authorship, design, or +inventorship that is intentionally submitted to NVIDIA for inclusion in the +NVDLA Specification by a person authorized to submit the contribution on +behalf of the owner. + +"NVDLA Patents" shall mean patents that are necessary to practice the NVDLA +Specification and any Derivative Works. + +"NVDLA Patent Rights" shall mean the right to make, have made, use, sell, +offer for sale, and import patents that are necessary to practice the NVDLA +Specification and any Derivative Works. + +"Other NVDLA Rights" includes copyright, design right (whether registered or +unregistered), semiconductor topography (mask work) rights, and database +rights to the NVDLA Specification and any Derivative Work. For the +avoidance of doubt, Other NVDLA Rights does not include patents or +trademarks. + +"License" and "Agreement" shall mean the terms and conditions for use, +reproduction, and distribution as set forth in this document. + +"You" (or "Your") shall mean an individual or Legal Entity agreeing to the +terms and conditions of this License. + +2. LICENSE TO NVDLA PATENTS. + +Subject to the terms and conditions of this License, NVIDIA and each +Contributor hereby grant to You a perpetual, worldwide, non-exclusive, +no-charge, royalty-free, irrevocable (except as stated in this section) +license under the NVDLA Patents to make, have made, use, offer to sell, +sell, import, and otherwise transfer DLA Products and the NVDLA +Specification, where such license applies only to those patent claims +licensable by such Contributor that are necessarily infringed either by (i) +their Contribution(s) alone or (ii) the combination of their NVDLA +Contribution(s) with the portion of the NVDLA Specification to which such +NVDLA Contribution(s) was submitted. + +If You institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that any portion of the +NVDLA Specification, a NVDLA Contribution incorporated within the NVDLA +Specification, or any portion of a DLA Product directly or contributorily +infringes any patent, then any patent licenses granted to You under this +License and Agreement shall terminate as of the date such litigation is +filed. + +3. LICENSE TO OTHER NVDLA RIGHTS. + +Subject to the terms and conditions of this License, NVIDIA and each +Contributor hereby grant to You a perpetual, worldwide, non-exclusive, +no-charge, royalty-free, irrevocable license under the Other NVDLA Rights to +reproduce, prepare Derivative Works of, publicly display, publicly perform, +sublicense, and distribute the NVDLA Specification and such Derivative +Works, and to commercially exploit any mask works included in the NVDLA +Specification or such Derivative Works. + +4. REDISTRIBUTION. + +You may reproduce and distribute copies of the NVDLA Specification or +Derivative Works thereof in any medium, with or without modifications, +provided that You meet the following conditions: + + 1. You must give any other recipients of the NVDLA Specification or + Derivative Works a copy of this License and Agreement; and + + 2. You must cause any modified files or other portions of the NVDLA + Specification to carry prominent notices stating that You changed such + files or other portions; and + + 3. You must retain, in any Derivative Works that You distribute, all + notices, including copyright, patent, trademark, and attribution + notices, from the NVDLA Specification, excluding those notices that do + not pertain to any part of the Derivative Works; and + + 4. You may add Your own copyright statement to Your modifications and may + provide additional or different license terms and conditions for use, + reproduction, or distribution of Your modifications, or for any such + Derivative Works as a whole, provided Your use, reproduction, and + distribution of the NVDLA Specification otherwise complies with the + conditions stated in this License and Agreement. + +5. SUBMISSION OF NVDLA CONTRIBUTIONS. + +You are not required to submit contributions to the NVDLA Specification, but +you may do so at your discretion. Unless You explicitly state otherwise, +any NVDLA Contribution intentionally submitted by you to NVIDIA for +inclusion in the NVDLA Specification shall be provided under the terms and +conditions of this License and Agreement, without any additional terms or +conditions. NVIDIA is under no obligation to consider, review, or +incorporate any NVDLA Contribution into any version of the NVDLA +Specification + +6. TRADEMARKS. + +This License does not grant permission to use the trade names, trademarks, +service marks, or product names ("Marks") of NVIDIA or any Contributor, +except as required for reasonable and customary use in describing the origin +of the NVDLA Specification. For DLA Products that are compatible with NVDLA +interfaces, NVIDIA and You may mutually agree on certain marketing +activities and branding involving the use of NVIDIA's Marks under separate +agreement and/or supplemental terms. + +7. NO IMPLIED RIGHTS. + +Except for the licenses expressly set forth herein, no other licenses are +granted hereunder whether by implication, estoppel or otherwise. This +License and Agreement provides you with no implied rights or licenses to the +intellectual property of NVIDIA or any Contributor. + +8. DISCLAIMER OF WARRANTY. + +Unless required by applicable law or agreed to in writing, NVIDIA provides +the NVDLA Specification (and each Contributor provides its NVDLA +Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +KIND, either express or implied, including, without limitation, any +warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or +FITNESS FOR A PARTICULAR PURPOSE. + +You are solely responsible for determining the appropriateness of Your use +of NVDLA, the NVDLA Specification, or any DLA Product, and You assume all +associated risks, including but not limited to the risks and costs of damage +to or loss of data, programs or equipment, and unavailability or +interruption of operations. You agree to comply with all regulations and +safety standards applicable to Your use of NVDLA and the NVDLA +Specification. You acknowledge that the NVDLA and NVDLA Specification +provided to You under this Agreement are not intended to be used, without +additional safeguards and/or process technology, to control or operate +machines that can lead to personal injury, death, or severe physical or +environmental damage, and if You make, use, or sell such machines, You agree +to assume all liability therefor and will comply with all applicable +safety-related laws, regulations, and best industry practices. + +9. LIMITATION OF LIABILITY. + +In no event and under no legal theory, whether in tort (including +negligence), contract, or otherwise, shall NVIDIA or any Contributor be +liable to You for damages, including any direct, indirect, special, +incidental, or consequential damages of any character arising as a result of +this License and Agreement, or arising out of the use or inability to use +any DLA Product (including but not limited to damages for loss of goodwill, +work stoppage, computer failure or malfunction, or any and all other +commercial damages or losses). + +10. WAIVER AND INDEMNITY. + +You agree to waive any and all claims against NVIDIA and each Contributor +arising from Your use of NVDLA or the NVDLA Specification. If Your use of +the NVDLA, the NVDLA Specification, or any portion thereof, results in any +liabilities, demands, damages, expenses or losses arising from such use, +including any damages from products based on, or resulting from, Your use of +NVDLA or the NVDLA Specification licensed under this Agreement, You shall +indemnify and hold harmless NVIDIA and each Contributor to the extent +permitted by law. In addition, You agree to defend, indemnify, and hold +NVIDIA and each Contributor harmless from any claim brought by a third party +alleging any defect in the design, manufacture, or any Product which You +make, have made, sell, or distribute pursuant to this Agreement. Your sole +remedy for any such matter shall be the immediate, unilateral termination of +this Agreement. + +END OF OPEN NVDLA LICENSE AND AGREEMENT + diff --git a/designs/src/NVDLA/dev/NV_NVDLA_cfgrom_REPLACE.v b/designs/src/NVDLA/dev/NV_NVDLA_cfgrom_REPLACE.v new file mode 100644 index 0000000..eec8059 --- /dev/null +++ b/designs/src/NVDLA/dev/NV_NVDLA_cfgrom_REPLACE.v @@ -0,0 +1,162 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ + +// File Name: NV_NVDLA_cfgrom.v + +`include "simulate_x_tick.vh" +module NV_NVDLA_cfgrom ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2cfgrom_req_pd + ,csb2cfgrom_req_pvld + ,csb2cfgrom_req_prdy + ,cfgrom2csb_resp_pd + ,cfgrom2csb_resp_valid + ); + +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cfgrom_req_pd; +input csb2cfgrom_req_pvld; +output csb2cfgrom_req_prdy; +output [33:0] cfgrom2csb_resp_pd; +output cfgrom2csb_resp_valid; +///////////////////////////////////////////// +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +reg [33:0] cfgrom2csb_resp_pd; +reg cfgrom2csb_resp_valid; +reg [62:0] req_pd; +reg req_pvld; +// One-cycle pipeline to align response with fakeram read latency +reg reg_rd_en_d1; +reg reg_wr_en_nposted_d1; +//////////////////////////////////////////////////////////////////////// + +fakeram_32x128_1r1w u_NV_NVDLA_CFGROM_rom ( + .r0_clk (nvdla_core_clk) + ,.r0_ce_in (reg_rd_en) + ,.r0_addr_in (reg_offset[8:2]) // 7-bit word address from byte offset + ,.r0_rd_out (reg_rd_data[31:0]) + ,.w0_clk (nvdla_core_clk) + ,.w0_ce_in (1'b1) + ,.w0_we_in (1'b0) // ROM — write port permanently disabled + ,.w0_addr_in (7'b0) + ,.w0_wd_in (32'b0) + ); + +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cfgrom_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cfgrom_req_pvld) == 1'b1) begin + req_pd <= csb2cfgrom_req_pd; + end + end +end + + +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; + +assign csb2cfgrom_req_prdy = 1'b1; + + +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; + + +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; + +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; + +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; + +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; + +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; + +// Delay rd/wr enables by 1 cycle to match fakeram registered output +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_rd_en_d1 <= 1'b0; + reg_wr_en_nposted_d1 <= 1'b0; + end else begin + reg_rd_en_d1 <= reg_rd_en; + reg_wr_en_nposted_d1 <= reg_wr_en & req_nposted; + end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en_d1) + begin + cfgrom2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en_nposted_d1) + begin + cfgrom2csb_resp_pd <= csb_wresp_pd_w; + end + end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom2csb_resp_valid <= 1'b0; + end else begin + cfgrom2csb_resp_valid <= reg_wr_en_nposted_d1 | reg_rd_en_d1; + end +end + + +endmodule \ No newline at end of file diff --git a/designs/src/NVDLA/dev/install/install_jdk11.sh b/designs/src/NVDLA/dev/install/install_jdk11.sh new file mode 100644 index 0000000..e1e1a6b --- /dev/null +++ b/designs/src/NVDLA/dev/install/install_jdk11.sh @@ -0,0 +1,74 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(pwd)" +PKG_ROOT="${ROOT_DIR}/packages" + +NAME="openjdk-11" +PREFIX="${PKG_ROOT}/${NAME}" +TARBALLS="${PKG_ROOT}/_tarballs" +BUILD="${PKG_ROOT}/_build" + +TB_NAME="openjdk-11.0.2_linux-x64_bin.tar.gz" +URL="https://download.java.net/java/GA/jdk11/9/GPL/${TB_NAME}" + +TB="${TARBALLS}/${TB_NAME}" +STAGE="${BUILD}/${NAME}-stage" + +mkdir -p "${TARBALLS}" "${BUILD}" + +# If already installed, exit early based on the actual java binary. +if [[ -x "${PREFIX}/bin/java" ]]; then + echo "[${NAME}] already installed at ${PREFIX}" + echo "Use it via:" + echo " export JAVA_HOME=\"${PREFIX}\"" + echo " export PATH=\"\${JAVA_HOME}/bin:\$PATH\"" + exit 0 +fi + +command -v tar >/dev/null 2>&1 || { echo "ERROR: Missing required command: tar" >&2; exit 1; } +if ! command -v curl >/dev/null 2>&1 && ! command -v wget >/dev/null 2>&1; then + echo "ERROR: Need curl or wget" >&2 + exit 1 +fi + +if [[ ! -f "${TB}" ]]; then + echo "[fetch] downloading: ${URL}" + if command -v curl >/dev/null 2>&1; then + curl -L --fail --retry 3 --retry-delay 2 -o "${TB}" "${URL}" + else + wget -O "${TB}" "${URL}" + fi +else + echo "[fetch] already exists: ${TB}" +fi + +echo "[${NAME}] extracting..." +rm -rf "${STAGE}" +mkdir -p "${STAGE}" +tar -xzf "${TB}" -C "${STAGE}" + +JDK_DIR="$(ls -d "${STAGE}"/jdk-* 2>/dev/null | head -1)" +if [[ -z "${JDK_DIR}" || ! -d "${JDK_DIR}" ]]; then + echo "ERROR: Could not locate extracted JDK directory under ${STAGE}" >&2 + exit 1 +fi + +rm -rf "${PREFIX}" +mv "${JDK_DIR}" "${PREFIX}" +rm -rf "${STAGE}" + +JAVA_BIN="${PREFIX}/bin/java" +JAR_BIN="${PREFIX}/bin/jar" +[[ -x "${JAVA_BIN}" ]] || { echo "ERROR: java binary not found at ${JAVA_BIN}" >&2; exit 1; } +[[ -x "${JAR_BIN}" ]] || { echo "ERROR: jar binary not found at ${JAR_BIN}" >&2; exit 1; } + +echo "[${NAME}] Verifying:" +"${JAVA_BIN}" -version +"${JAR_BIN}" --version + +echo +echo "[${NAME}] installed to ${PREFIX}" +echo "Add to your shell:" +echo " export JAVA_HOME=\"${PREFIX}\"" +echo " export PATH=\"\${JAVA_HOME}/bin:\$PATH\"" \ No newline at end of file diff --git a/designs/src/NVDLA/dev/install/install_openssl.sh b/designs/src/NVDLA/dev/install/install_openssl.sh new file mode 100644 index 0000000..b0da4b0 --- /dev/null +++ b/designs/src/NVDLA/dev/install/install_openssl.sh @@ -0,0 +1,70 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(pwd)" +PKG_ROOT="${ROOT_DIR}/packages" +PREFIX="${PKG_ROOT}/openssl-1.0.2u" +TARBALLS="${PKG_ROOT}/_tarballs" +BUILD="${PKG_ROOT}/_build" +MARKERS="${PKG_ROOT}/_installed" +NAME="openssl-1.0.2u" +JOBS="${JOBS:-$(nproc)}" + +mkdir -p "${PREFIX}" "${TARBALLS}" "${BUILD}" "${MARKERS}" + +die() { echo "ERROR: $*" >&2; exit 1; } +need_cmd() { command -v "$1" >/dev/null 2>&1 || die "Missing required command: $1"; } +have_cmd() { command -v "$1" >/dev/null 2>&1; } +is_done() { [[ -f "${MARKERS}/${1}.done" ]]; } +mark_done() { touch "${MARKERS}/${1}.done"; } + +fetch() { + local url="$1" out="$2" + if [[ -f "$out" ]]; then echo "[fetch] already exists: $out"; return 0; fi + echo "[fetch] downloading: $url" + if have_cmd curl; then + curl -L --fail --retry 3 --retry-delay 2 -o "$out" "$url" + elif have_cmd wget; then + wget -O "$out" "$url" + else + die "Need curl or wget" + fi +} + +extract() { + local tb="$1" dest="$2" + mkdir -p "$dest" + case "$tb" in + *.tar.gz|*.tgz) tar -xzf "$tb" -C "$dest" ;; + *.tar.bz2) tar -xjf "$tb" -C "$dest" ;; + *.tar.xz) tar -xJf "$tb" -C "$dest" ;; + *) die "Don't know how to extract: $tb" ;; + esac +} + +if is_done "${NAME}"; then + echo "[${NAME}] already installed at ${PREFIX}" + exit 0 +fi +unset MAKEFLAGS MFLAGS MAKELEVEL +need_cmd tar +need_cmd make +need_cmd gcc +need_cmd curl || need_cmd wget + +TB="${TARBALLS}/openssl-1.0.2u.tar.gz" +URL="https://www.openssl.org/source/old/1.0.2/openssl-1.0.2u.tar.gz" +fetch "$URL" "$TB" + +SRC="${BUILD}/${NAME}-src" +rm -rf "$SRC" +mkdir -p "$SRC" +extract "$TB" "$SRC" + +cd "${SRC}/openssl-1.0.2u" +./config shared --prefix="${PREFIX}" --openssldir="${PREFIX}/ssl" +make -j"${JOBS}" +make install_sw + +mark_done "${NAME}" +echo "[${NAME}] installed to ${PREFIX}" \ No newline at end of file diff --git a/designs/src/NVDLA/dev/install/install_perl5_10.sh b/designs/src/NVDLA/dev/install/install_perl5_10.sh new file mode 100644 index 0000000..edb02f1 --- /dev/null +++ b/designs/src/NVDLA/dev/install/install_perl5_10.sh @@ -0,0 +1,82 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(pwd)" +PKG_ROOT="${ROOT_DIR}/packages" +PREFIX="${PKG_ROOT}/perl-5.10.1" +TARBALLS="${PKG_ROOT}/_tarballs" +BUILD="${PKG_ROOT}/_build" +MARKERS="${PKG_ROOT}/_installed" +NAME="perl-5.10.1" +JOBS="${JOBS:-$(nproc)}" + +mkdir -p "${PREFIX}" "${TARBALLS}" "${BUILD}" "${MARKERS}" + +die() { echo "ERROR: $*" >&2; exit 1; } +need_cmd() { command -v "$1" >/dev/null 2>&1 || die "Missing required command: $1"; } +have_cmd() { command -v "$1" >/dev/null 2>&1; } +is_done() { [[ -f "${MARKERS}/${1}.done" ]]; } +mark_done() { touch "${MARKERS}/${1}.done"; } + +fetch() { + local url="$1" out="$2" + if [[ -f "$out" ]]; then echo "[fetch] already exists: $out"; return 0; fi + echo "[fetch] downloading: $url" + if have_cmd curl; then + curl -L --fail --retry 3 --retry-delay 2 -o "$out" "$url" + elif have_cmd wget; then + wget -O "$out" "$url" + else + die "Need curl or wget" + fi +} + +extract() { + local tb="$1" dest="$2" + mkdir -p "$dest" + case "$tb" in + *.tar.gz|*.tgz) tar -xzf "$tb" -C "$dest" ;; + *.tar.bz2) tar -xjf "$tb" -C "$dest" ;; + *.tar.xz) tar -xJf "$tb" -C "$dest" ;; + *) die "Don't know how to extract: $tb" ;; + esac +} + +if is_done "${NAME}"; then + echo "[${NAME}] already installed at ${PREFIX}" + exit 0 +fi + +need_cmd tar +need_cmd make +need_cmd gcc +need_cmd g++ +need_cmd curl || need_cmd wget + +TB="${TARBALLS}/perl-5.10.1.tar.gz" +URL="https://www.cpan.org/src/5.0/perl-5.10.1.tar.gz" +fetch "$URL" "$TB" + +SRC="${BUILD}/${NAME}-src" +rm -rf "$SRC" +mkdir -p "$SRC" +extract "$TB" "$SRC" +unset MAKEFLAGS MFLAGS MAKELEVEL +cd "${SRC}/perl-5.10.1" +./Configure -des -Dprefix="${PREFIX}" -Dlibs='-lm' + +make -j"${JOBS}" +make test || echo "[${NAME}] WARNING: perl test suite had failures; continuing." +make install + +# Bootstrap cpanm into this perl +PERL_BIN="${PREFIX}/bin/perl" +CPANM="${PREFIX}/bin/cpanm" +if [[ ! -x "$CPANM" ]]; then + fetch "https://cpanmin.us/" "${BUILD}/cpanm.pl" + "${PERL_BIN}" "${BUILD}/cpanm.pl" App::cpanminus +fi +"${CPANM}" --notest Capture::Tiny XML::Simple YAML IO::Tee +mark_done "${NAME}" +echo "[${NAME}] installed to ${PREFIX}" +echo "Use it via: export PATH=\"${PREFIX}/bin:\$PATH\"" \ No newline at end of file diff --git a/designs/src/NVDLA/dev/install/install_py2_6.sh b/designs/src/NVDLA/dev/install/install_py2_6.sh new file mode 100644 index 0000000..dd4a9da --- /dev/null +++ b/designs/src/NVDLA/dev/install/install_py2_6.sh @@ -0,0 +1,81 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(pwd)" +PKG_ROOT="${ROOT_DIR}/packages" +PREFIX="${PKG_ROOT}/python-2.7.18" +OPENSSL_PREFIX="${PKG_ROOT}/openssl-1.0.2u" +TARBALLS="${PKG_ROOT}/_tarballs" +BUILD="${PKG_ROOT}/_build" +MARKERS="${PKG_ROOT}/_installed" +NAME="python-2.7.18" +JOBS="${JOBS:-$(nproc)}" + +mkdir -p "${PREFIX}" "${TARBALLS}" "${BUILD}" "${MARKERS}" + +die() { echo "ERROR: $*" >&2; exit 1; } +need_cmd() { command -v "$1" >/dev/null 2>&1 || die "Missing required command: $1"; } +have_cmd() { command -v "$1" >/dev/null 2>&1; } +is_done() { [[ -f "${MARKERS}/${1}.done" ]]; } +mark_done() { touch "${MARKERS}/${1}.done"; } + +fetch() { + local url="$1" out="$2" + if [[ -f "$out" ]]; then echo "[fetch] already exists: $out"; return 0; fi + echo "[fetch] downloading: $url" + if have_cmd curl; then + curl -L --fail --retry 3 --retry-delay 2 -o "$out" "$url" + elif have_cmd wget; then + wget -O "$out" "$url" + else + die "Need curl or wget" + fi +} + +extract() { + local tb="$1" dest="$2" + mkdir -p "$dest" + case "$tb" in + *.tar.gz|*.tgz) tar -xzf "$tb" -C "$dest" ;; + *.tar.bz2) tar -xjf "$tb" -C "$dest" ;; + *.tar.xz) tar -xJf "$tb" -C "$dest" ;; + *) die "Don't know how to extract: $tb" ;; + esac +} + +if is_done "${NAME}"; then + echo "[${NAME}] already installed at ${PREFIX}" + exit 0 +fi + +need_cmd tar +need_cmd make +need_cmd gcc +need_cmd curl || need_cmd wget + +# Require OpenSSL 1.0.2u installed (Python 2.7 ssl on modern Ubuntu otherwise breaks) +[[ -d "${OPENSSL_PREFIX}/include" ]] || die "OpenSSL 1.0.2u not found at ${OPENSSL_PREFIX}. Run install_openssl-1.0.2u.sh first." + +TB="${TARBALLS}/Python-2.7.18.tgz" +URL="https://www.python.org/ftp/python/2.7.18/Python-2.7.18.tgz" +fetch "$URL" "$TB" + +SRC="${BUILD}/${NAME}-src" +rm -rf "$SRC" +mkdir -p "$SRC" +extract "$TB" "$SRC" + +cd "${SRC}/Python-2.7.18" + +export CPPFLAGS="-I${OPENSSL_PREFIX}/include" +export LDFLAGS="-L${OPENSSL_PREFIX}/lib -Wl,-rpath,${OPENSSL_PREFIX}/lib" +export LD_LIBRARY_PATH="${OPENSSL_PREFIX}/lib:${LD_LIBRARY_PATH:-}" +unset MAKEFLAGS MFLAGS MAKELEVEL +./configure --prefix="${PREFIX}" --enable-shared --enable-unicode=ucs4 +make -j"${JOBS}" +make install + +mark_done "${NAME}" +echo "[${NAME}] installed to ${PREFIX}" +echo "Runtime note: set LD_LIBRARY_PATH so libpython can be found:" +echo " export LD_LIBRARY_PATH=\"${PREFIX}/lib:${OPENSSL_PREFIX}/lib:\$LD_LIBRARY_PATH\"" \ No newline at end of file diff --git a/designs/src/NVDLA/dev/install/install_systemc2_3_0.sh b/designs/src/NVDLA/dev/install/install_systemc2_3_0.sh new file mode 100644 index 0000000..e41e74c --- /dev/null +++ b/designs/src/NVDLA/dev/install/install_systemc2_3_0.sh @@ -0,0 +1,80 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT_DIR="$(pwd)" +PKG_ROOT="${ROOT_DIR}/packages" +PREFIX="${PKG_ROOT}/systemc-2.3.0" +TARBALLS="${PKG_ROOT}/_tarballs" +BUILD="${PKG_ROOT}/_build" +MARKERS="${PKG_ROOT}/_installed" +NAME="systemc-2.3.0" +JOBS="${JOBS:-$(nproc)}" + +mkdir -p "${PREFIX}" "${TARBALLS}" "${BUILD}" "${MARKERS}" + +die() { echo "ERROR: $*" >&2; exit 1; } +need_cmd() { command -v "$1" >/dev/null 2>&1 || die "Missing required command: $1"; } +have_cmd() { command -v "$1" >/dev/null 2>&1; } +is_done() { [[ -f "${MARKERS}/${1}.done" ]]; } +mark_done() { touch "${MARKERS}/${1}.done"; } + +fetch() { + local url="$1" out="$2" + if [[ -f "$out" ]]; then echo "[fetch] already exists: $out"; return 0; fi + echo "[fetch] downloading: $url" + if have_cmd curl; then + curl -L --fail --retry 3 --retry-delay 2 -o "$out" "$url" + elif have_cmd wget; then + wget -O "$out" "$url" + else + die "Need curl or wget" + fi +} + +extract() { + local tb="$1" dest="$2" + mkdir -p "$dest" + case "$tb" in + *.tar.gz|*.tgz) tar -xzf "$tb" -C "$dest" ;; + *.tar.bz2) tar -xjf "$tb" -C "$dest" ;; + *.tar.xz) tar -xJf "$tb" -C "$dest" ;; + *) die "Don't know how to extract: $tb" ;; + esac +} + +if is_done "${NAME}"; then + echo "[${NAME}] already installed at ${PREFIX}" + exit 0 +fi + +need_cmd tar +need_cmd make +need_cmd g++ +need_cmd curl || need_cmd wget + +TB="${TARBALLS}/systemc-2.3.0.tgz" +URL="https://www.accellera.org/images/downloads/standards/systemc/systemc-2.3.0.tgz" +fetch "$URL" "$TB" + +SRC="${BUILD}/${NAME}-src" +rm -rf "$SRC" +mkdir -p "$SRC" +extract "$TB" "$SRC" + +SYS_SRC="${SRC}/systemc-2.3.0" +[[ -d "$SYS_SRC" ]] || die "Expected source dir not found: $SYS_SRC" + +BUILD_DIR="${BUILD}/${NAME}-build" +rm -rf "$BUILD_DIR" +mkdir -p "$BUILD_DIR" +cd "$BUILD_DIR" + +"${SYS_SRC}/configure" --prefix="${PREFIX}" +make -j"${JOBS}" +make install + +mark_done "${NAME}" +echo "[${NAME}] installed to ${PREFIX}" +echo "Use via:" +echo " export SYSTEMC_HOME=\"${PREFIX}\"" +echo " export LD_LIBRARY_PATH=\"${PREFIX}/lib-linux64:\$LD_LIBRARY_PATH\"" \ No newline at end of file diff --git a/designs/src/NVDLA/dev/repo b/designs/src/NVDLA/dev/repo new file mode 160000 index 0000000..771f20c --- /dev/null +++ b/designs/src/NVDLA/dev/repo @@ -0,0 +1 @@ +Subproject commit 771f20cc9e69759d7277978eb41e8d47f1547374 diff --git a/designs/src/NVDLA/dev/setup.sh b/designs/src/NVDLA/dev/setup.sh new file mode 100644 index 0000000..3b905a6 --- /dev/null +++ b/designs/src/NVDLA/dev/setup.sh @@ -0,0 +1,31 @@ +#!/usr/bin/env bash +set -euo pipefail + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" +export USER=${USER:-no_user} +if [ "$HOME" = "/" ]; then + HOME=/tmp/ +fi + +# Prerequisite Setup +bash "$(pwd)/install/install_jdk11.sh" +bash "$(pwd)/install/install_openssl.sh" +bash "$(pwd)/install/install_perl5_10.sh" +bash "$(pwd)/install/install_py2_6.sh" +bash "$(pwd)/install/install_systemc2_3_0.sh" + +cp tree.make ./repo/tree.make + +PKG_ROOT="${DIR}/packages" +PERL_PREFIX="${PKG_ROOT}/perl-5.10.1" +PY_PREFIX="${PKG_ROOT}/python-2.7.18" +PERL="${PERL_PREFIX}/bin/perl" +PYTHON="${PY_PREFIX}/bin/python" +export LD_LIBRARY_PATH="${PY_PREFIX}/lib:${LD_LIBRARY_PATH:-}" + +cd repo +${PERL} ./tools/bin/tmake -build vmod +rm outdir/nv_small/vmod/nvdla/cfgrom/* +cp ../NV_NVDLA_cfgrom_REPLACE.v outdir/nv_small/vmod/nvdla/cfgrom/NV_NVDLA_cfgrom.v +cp -r outdir/nv_small/vmod ../../ diff --git a/designs/src/NVDLA/dev/tree.make b/designs/src/NVDLA/dev/tree.make new file mode 100644 index 0000000..39c73f7 --- /dev/null +++ b/designs/src/NVDLA/dev/tree.make @@ -0,0 +1,30 @@ +## ================================================================ +## NVDLA Open Source Project +## +## Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +## NVDLA Open Hardware License; Check LICENSE which comes with +## this distribution for more information. +## ================================================================ + + +##======================= +## Project Name Setup, multiple projects supported +##======================= +PROJECTS := nv_small + +##======================= +##Linux Environment Setup +##======================= +PKG_ROOT ?= $(BENCH_DESIGN_HOME)/src/NVDLA/dev/packages +PERL_PREFIX ?= $(PKG_ROOT)/perl-5.10.1 +PY_PREFIX ?= $(PKG_ROOT)/python-2.7.18 +USE_DESIGNWARE := 0 +CPP := $(shell command -v cpp) +GCC := $(shell command -v gcc) +CXX := $(shell command -v g++) +JAVA := $(PKG_ROOT)/openjdk-11/bin/java +SYSTEMC_HOME ?= $(PKG_ROOT)/systemc-2.3.0 +PERL ?= $(PERL_PREFIX)/bin/perl +PYTHON ?= $(PY_PREFIX)/bin/python +SYSTEMC ?= $(SYSTEMC_HOME)/lib-linux64 +VERILATOR := verilator \ No newline at end of file diff --git a/designs/src/NVDLA/macros.v b/designs/src/NVDLA/macros.v new file mode 100644 index 0000000..306ae1c --- /dev/null +++ b/designs/src/NVDLA/macros.v @@ -0,0 +1,29056 @@ +// ============================================================================= +// macros.v — NVDLA RAM wrappers bridging original port names → fakeram ports +// Technology : ASAP7 (7nm) | Generator: bgoldbug/dynamic_fakeram +// +// All original ports are preserved on every wrapper so existing NVDLA RTL +// connections compile without modification. +// +// Functional port mapping (forwarded to fakeram instance): +// CLK_R / CLK_W → r0_clk / w0_clk (RAMDP dual-clock) +// CLK → r0_clk + w0_clk (RAMPDP single-clock) +// RE → r0_ce_in +// WE → w0_we_in +// (tied) → w0_ce_in = 1'b1 +// RADR_[N-1:0] → r0_addr_in (MSB→LSB concat) +// WADR_[N-1:0] → w0_addr_in (MSB→LSB concat) +// WD_[W-1:0] → w0_wd_in (MSB→LSB concat) +// RD_[W-1:0] ← r0_rd_out (via rd_bus wire) +// +// NC ports (declared for compatibility, not forwarded — fakeram has no equiv): +// IDDQ — test/IDDQ mode → not connected +// SVOP_[N:0] — scan vector output → not connected +// SLEEP_EN_[7:0] — power-gate zone enable → not connected +// RET_EN — retention enable → not connected +// ============================================================================= +`timescale 1ns/1ps + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=128 width=11 addr=7b +module RAMDP_128X11_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [10:0] rd_bus; + assign {RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_11x128_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_128X11_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=128 width=6 addr=7b +module RAMDP_128X6_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [5:0] rd_bus; + assign {RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_6x128_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_128X6_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=16 width=256 addr=4b +module RAMDP_16X256_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [255:0] rd_bus; + assign {RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_256x16_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_16X256_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=16 width=272 addr=4b +module RAMDP_16X272_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_271, + WD_270, + WD_269, + WD_268, + WD_267, + WD_266, + WD_265, + WD_264, + WD_263, + WD_262, + WD_261, + WD_260, + WD_259, + WD_258, + WD_257, + WD_256, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_271, + RD_270, + RD_269, + RD_268, + RD_267, + RD_266, + RD_265, + RD_264, + RD_263, + RD_262, + RD_261, + RD_260, + RD_259, + RD_258, + RD_257, + RD_256, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_271; + input WD_270; + input WD_269; + input WD_268; + input WD_267; + input WD_266; + input WD_265; + input WD_264; + input WD_263; + input WD_262; + input WD_261; + input WD_260; + input WD_259; + input WD_258; + input WD_257; + input WD_256; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_271; + output RD_270; + output RD_269; + output RD_268; + output RD_267; + output RD_266; + output RD_265; + output RD_264; + output RD_263; + output RD_262; + output RD_261; + output RD_260; + output RD_259; + output RD_258; + output RD_257; + output RD_256; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [271:0] rd_bus; + assign {RD_271, RD_270, RD_269, RD_268, RD_267, RD_266, RD_265, RD_264, RD_263, RD_262, RD_261, RD_260, RD_259, RD_258, RD_257, RD_256, RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_272x16_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_271, WD_270, WD_269, WD_268, WD_267, WD_266, WD_265, WD_264, WD_263, WD_262, WD_261, WD_260, WD_259, WD_258, WD_257, WD_256, WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_16X272_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=16 width=64 addr=4b +module RAMDP_16X64_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [63:0] rd_bus; + assign {RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_64x16_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_16X64_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=20 width=288 addr=5b +module RAMDP_20X288_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_287, + WD_286, + WD_285, + WD_284, + WD_283, + WD_282, + WD_281, + WD_280, + WD_279, + WD_278, + WD_277, + WD_276, + WD_275, + WD_274, + WD_273, + WD_272, + WD_271, + WD_270, + WD_269, + WD_268, + WD_267, + WD_266, + WD_265, + WD_264, + WD_263, + WD_262, + WD_261, + WD_260, + WD_259, + WD_258, + WD_257, + WD_256, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_287, + RD_286, + RD_285, + RD_284, + RD_283, + RD_282, + RD_281, + RD_280, + RD_279, + RD_278, + RD_277, + RD_276, + RD_275, + RD_274, + RD_273, + RD_272, + RD_271, + RD_270, + RD_269, + RD_268, + RD_267, + RD_266, + RD_265, + RD_264, + RD_263, + RD_262, + RD_261, + RD_260, + RD_259, + RD_258, + RD_257, + RD_256, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_287; + input WD_286; + input WD_285; + input WD_284; + input WD_283; + input WD_282; + input WD_281; + input WD_280; + input WD_279; + input WD_278; + input WD_277; + input WD_276; + input WD_275; + input WD_274; + input WD_273; + input WD_272; + input WD_271; + input WD_270; + input WD_269; + input WD_268; + input WD_267; + input WD_266; + input WD_265; + input WD_264; + input WD_263; + input WD_262; + input WD_261; + input WD_260; + input WD_259; + input WD_258; + input WD_257; + input WD_256; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_287; + output RD_286; + output RD_285; + output RD_284; + output RD_283; + output RD_282; + output RD_281; + output RD_280; + output RD_279; + output RD_278; + output RD_277; + output RD_276; + output RD_275; + output RD_274; + output RD_273; + output RD_272; + output RD_271; + output RD_270; + output RD_269; + output RD_268; + output RD_267; + output RD_266; + output RD_265; + output RD_264; + output RD_263; + output RD_262; + output RD_261; + output RD_260; + output RD_259; + output RD_258; + output RD_257; + output RD_256; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [287:0] rd_bus; + assign {RD_287, RD_286, RD_285, RD_284, RD_283, RD_282, RD_281, RD_280, RD_279, RD_278, RD_277, RD_276, RD_275, RD_274, RD_273, RD_272, RD_271, RD_270, RD_269, RD_268, RD_267, RD_266, RD_265, RD_264, RD_263, RD_262, RD_261, RD_260, RD_259, RD_258, RD_257, RD_256, RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_288x20_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_287, WD_286, WD_285, WD_284, WD_283, WD_282, WD_281, WD_280, WD_279, WD_278, WD_277, WD_276, WD_275, WD_274, WD_273, WD_272, WD_271, WD_270, WD_269, WD_268, WD_267, WD_266, WD_265, WD_264, WD_263, WD_262, WD_261, WD_260, WD_259, WD_258, WD_257, WD_256, WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_20X288_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=20 width=80 addr=5b +module RAMDP_20X80_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [79:0] rd_bus; + assign {RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_80x20_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_20X80_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=256 width=4 addr=8b +module RAMDP_256X4_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [3:0] rd_bus; + assign {RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_4x256_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_256X4_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=256 width=7 addr=8b +module RAMDP_256X7_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [6:0] rd_bus; + assign {RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_7x256_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_256X7_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=256 width=8 addr=8b +module RAMDP_256X8_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [7:0] rd_bus; + assign {RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_8x256_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_256X8_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=32 width=16 addr=5b +module RAMDP_32X16_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [15:0] rd_bus; + assign {RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_16x32_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_32X16_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=32 width=32 addr=5b +module RAMDP_32X32_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [31:0] rd_bus; + assign {RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_32x32_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_32X32_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=60 width=22 addr=6b +module RAMDP_60X22_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [21:0] rd_bus; + assign {RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_22x60_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_60X22_GL_M1_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=64 width=10 addr=6b +module RAMDP_64X10_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [9:0] rd_bus; + assign {RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_10x64_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_64X10_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=64 width=18 addr=6b +module RAMDP_64X18_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [17:0] rd_bus; + assign {RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_18x64_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_64X18_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=80 width=14 addr=7b +module RAMDP_80X14_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [13:0] rd_bus; + assign {RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_14x80_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_80X14_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=80 width=15 addr=7b +module RAMDP_80X15_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [14:0] rd_bus; + assign {RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_15x80_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_80X15_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=80 width=9 addr=7b +module RAMDP_80X9_GL_M2_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [8:0] rd_bus; + assign {RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_9x80_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_80X9_GL_M2_E2 + +// RAMDP dual-clock 1R1W (CLK_R / CLK_W) | depth=8 width=66 addr=3b +module RAMDP_8X66_GL_M1_E2 ( + CLK_R, + CLK_W, + RE, + WE, + RADR_2, + RADR_1, + RADR_0, + WADR_2, + WADR_1, + WADR_0, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + SLEEP_EN_7, + SLEEP_EN_6, + SLEEP_EN_5, + SLEEP_EN_4, + SLEEP_EN_3, + SLEEP_EN_2, + SLEEP_EN_1, + SLEEP_EN_0, + RET_EN, + IDDQ, + SVOP_1, + SVOP_0, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK_R; + input CLK_W; + input RE; + input WE; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_2; + input WADR_1; + input WADR_0; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input SLEEP_EN_7; + input SLEEP_EN_6; + input SLEEP_EN_5; + input SLEEP_EN_4; + input SLEEP_EN_3; + input SLEEP_EN_2; + input SLEEP_EN_1; + input SLEEP_EN_0; + input RET_EN; + input IDDQ; + input SVOP_1; + input SVOP_0; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [65:0] rd_bus; + assign {RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN, IDDQ, SVOP_1, SVOP_0 + + fakeram_66x8_1r1w sram ( + .r0_clk (CLK_R), + .w0_clk (CLK_W), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMDP_8X66_GL_M1_E2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=128 width=18 addr=7b +module RAMPDP_128X18_GL_M2_D2 ( + CLK, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [17:0] rd_bus; + assign {RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_18x128_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_128X18_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=128 width=256 addr=7b +module RAMPDP_128X256_GL_M1_D2 ( + CLK, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [255:0] rd_bus; + assign {RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_256x128_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_128X256_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=128 width=64 addr=7b +module RAMPDP_128X64_GL_M1_D2 ( + CLK, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [63:0] rd_bus; + assign {RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_64x128_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_128X64_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=160 width=144 addr=8b +module RAMPDP_160X144_GL_M2_D2 ( + CLK, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [143:0] rd_bus; + assign {RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_144x160_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_160X144_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=160 width=16 addr=8b +module RAMPDP_160X16_GL_M2_D2 ( + CLK, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [15:0] rd_bus; + assign {RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_16x160_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_160X16_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=160 width=65 addr=8b +module RAMPDP_160X65_GL_M2_D2 ( + CLK, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [64:0] rd_bus; + assign {RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_65x160_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_160X65_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=160 width=82 addr=8b +module RAMPDP_160X82_GL_M2_D2 ( + CLK, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [81:0] rd_bus; + assign {RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_82x160_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_160X82_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=248 width=144 addr=8b +module RAMPDP_248X144_GL_M2_D2 ( + CLK, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [143:0] rd_bus; + assign {RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_144x248_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_248X144_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=248 width=82 addr=8b +module RAMPDP_248X82_GL_M2_D2 ( + CLK, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [81:0] rd_bus; + assign {RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_82x248_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_248X82_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=256 width=11 addr=8b +module RAMPDP_256X11_GL_M4_D2 ( + CLK, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [10:0] rd_bus; + assign {RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_11x256_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_256X11_GL_M4_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=256 width=144 addr=8b +module RAMPDP_256X144_GL_M2_D2 ( + CLK, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [143:0] rd_bus; + assign {RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_144x256_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_256X144_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=256 width=64 addr=8b +module RAMPDP_256X64_GL_M2_D2 ( + CLK, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [63:0] rd_bus; + assign {RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_64x256_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_256X64_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=256 width=80 addr=8b +module RAMPDP_256X80_GL_M2_D2 ( + CLK, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [79:0] rd_bus; + assign {RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_80x256_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_256X80_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=32 width=192 addr=5b +module RAMPDP_32X192_GL_M1_D2 ( + CLK, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [191:0] rd_bus; + assign {RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_192x32_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_32X192_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=32 width=224 addr=5b +module RAMPDP_32X224_GL_M1_D2 ( + CLK, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [223:0] rd_bus; + assign {RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_224x32_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_32X224_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=32 width=256 addr=5b +module RAMPDP_32X256_GL_M1_D2 ( + CLK, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [255:0] rd_bus; + assign {RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_256x32_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_32X256_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=32 width=272 addr=5b +module RAMPDP_32X272_GL_M1_D2 ( + CLK, + WD_271, + WD_270, + WD_269, + WD_268, + WD_267, + WD_266, + WD_265, + WD_264, + WD_263, + WD_262, + WD_261, + WD_260, + WD_259, + WD_258, + WD_257, + WD_256, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_271, + RD_270, + RD_269, + RD_268, + RD_267, + RD_266, + RD_265, + RD_264, + RD_263, + RD_262, + RD_261, + RD_260, + RD_259, + RD_258, + RD_257, + RD_256, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_271; + input WD_270; + input WD_269; + input WD_268; + input WD_267; + input WD_266; + input WD_265; + input WD_264; + input WD_263; + input WD_262; + input WD_261; + input WD_260; + input WD_259; + input WD_258; + input WD_257; + input WD_256; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_271; + output RD_270; + output RD_269; + output RD_268; + output RD_267; + output RD_266; + output RD_265; + output RD_264; + output RD_263; + output RD_262; + output RD_261; + output RD_260; + output RD_259; + output RD_258; + output RD_257; + output RD_256; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [271:0] rd_bus; + assign {RD_271, RD_270, RD_269, RD_268, RD_267, RD_266, RD_265, RD_264, RD_263, RD_262, RD_261, RD_260, RD_259, RD_258, RD_257, RD_256, RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_272x32_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_271, WD_270, WD_269, WD_268, WD_267, WD_266, WD_265, WD_264, WD_263, WD_262, WD_261, WD_260, WD_259, WD_258, WD_257, WD_256, WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_32X272_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=32 width=288 addr=5b +module RAMPDP_32X288_GL_M1_D2 ( + CLK, + WD_287, + WD_286, + WD_285, + WD_284, + WD_283, + WD_282, + WD_281, + WD_280, + WD_279, + WD_278, + WD_277, + WD_276, + WD_275, + WD_274, + WD_273, + WD_272, + WD_271, + WD_270, + WD_269, + WD_268, + WD_267, + WD_266, + WD_265, + WD_264, + WD_263, + WD_262, + WD_261, + WD_260, + WD_259, + WD_258, + WD_257, + WD_256, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_287, + RD_286, + RD_285, + RD_284, + RD_283, + RD_282, + RD_281, + RD_280, + RD_279, + RD_278, + RD_277, + RD_276, + RD_275, + RD_274, + RD_273, + RD_272, + RD_271, + RD_270, + RD_269, + RD_268, + RD_267, + RD_266, + RD_265, + RD_264, + RD_263, + RD_262, + RD_261, + RD_260, + RD_259, + RD_258, + RD_257, + RD_256, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_287; + input WD_286; + input WD_285; + input WD_284; + input WD_283; + input WD_282; + input WD_281; + input WD_280; + input WD_279; + input WD_278; + input WD_277; + input WD_276; + input WD_275; + input WD_274; + input WD_273; + input WD_272; + input WD_271; + input WD_270; + input WD_269; + input WD_268; + input WD_267; + input WD_266; + input WD_265; + input WD_264; + input WD_263; + input WD_262; + input WD_261; + input WD_260; + input WD_259; + input WD_258; + input WD_257; + input WD_256; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_287; + output RD_286; + output RD_285; + output RD_284; + output RD_283; + output RD_282; + output RD_281; + output RD_280; + output RD_279; + output RD_278; + output RD_277; + output RD_276; + output RD_275; + output RD_274; + output RD_273; + output RD_272; + output RD_271; + output RD_270; + output RD_269; + output RD_268; + output RD_267; + output RD_266; + output RD_265; + output RD_264; + output RD_263; + output RD_262; + output RD_261; + output RD_260; + output RD_259; + output RD_258; + output RD_257; + output RD_256; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [287:0] rd_bus; + assign {RD_287, RD_286, RD_285, RD_284, RD_283, RD_282, RD_281, RD_280, RD_279, RD_278, RD_277, RD_276, RD_275, RD_274, RD_273, RD_272, RD_271, RD_270, RD_269, RD_268, RD_267, RD_266, RD_265, RD_264, RD_263, RD_262, RD_261, RD_260, RD_259, RD_258, RD_257, RD_256, RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_288x32_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_287, WD_286, WD_285, WD_284, WD_283, WD_282, WD_281, WD_280, WD_279, WD_278, WD_277, WD_276, WD_275, WD_274, WD_273, WD_272, WD_271, WD_270, WD_269, WD_268, WD_267, WD_266, WD_265, WD_264, WD_263, WD_262, WD_261, WD_260, WD_259, WD_258, WD_257, WD_256, WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_32X288_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=512 width=40 addr=9b +module RAMPDP_512X40_GL_M4_D2 ( + CLK, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_8, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_8, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_8; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_8; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [39:0] rd_bus; + assign {RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_40x512_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_8, RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_8, WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_512X40_GL_M4_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=512 width=64 addr=9b +module RAMPDP_512X64_GL_M4_D2 ( + CLK, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_8, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_8, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_8; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_8; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [63:0] rd_bus; + assign {RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_64x512_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_8, RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_8, WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_512X64_GL_M4_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=512 width=72 addr=9b +module RAMPDP_512X72_GL_M4_D2 ( + CLK, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_8, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_8, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_8; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_8; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [71:0] rd_bus; + assign {RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_72x512_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_8, RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_8, WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_512X72_GL_M4_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=512 width=8 addr=9b +module RAMPDP_512X8_GL_M4_D2 ( + CLK, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_8, + RADR_7, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_8, + WADR_7, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_8; + input RADR_7; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_8; + input WADR_7; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [7:0] rd_bus; + assign {RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_8x512_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_8, RADR_7, RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_8, WADR_7, WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_512X8_GL_M4_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=60 width=168 addr=6b +module RAMPDP_60X168_GL_M1_D2 ( + CLK, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [167:0] rd_bus; + assign {RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_168x60_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_60X168_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=116 addr=6b +module RAMPDP_64X116_GL_M1_D2 ( + CLK, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [115:0] rd_bus; + assign {RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_116x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X116_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=160 addr=6b +module RAMPDP_64X160_GL_M1_D2 ( + CLK, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [159:0] rd_bus; + assign {RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_160x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X160_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=224 addr=6b +module RAMPDP_64X224_GL_M1_D2 ( + CLK, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [223:0] rd_bus; + assign {RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_224x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X224_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=226 addr=6b +module RAMPDP_64X226_GL_M1_D2 ( + CLK, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [225:0] rd_bus; + assign {RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_226x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X226_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=288 addr=6b +module RAMPDP_64X288_GL_M1_D2 ( + CLK, + WD_287, + WD_286, + WD_285, + WD_284, + WD_283, + WD_282, + WD_281, + WD_280, + WD_279, + WD_278, + WD_277, + WD_276, + WD_275, + WD_274, + WD_273, + WD_272, + WD_271, + WD_270, + WD_269, + WD_268, + WD_267, + WD_266, + WD_265, + WD_264, + WD_263, + WD_262, + WD_261, + WD_260, + WD_259, + WD_258, + WD_257, + WD_256, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_287, + RD_286, + RD_285, + RD_284, + RD_283, + RD_282, + RD_281, + RD_280, + RD_279, + RD_278, + RD_277, + RD_276, + RD_275, + RD_274, + RD_273, + RD_272, + RD_271, + RD_270, + RD_269, + RD_268, + RD_267, + RD_266, + RD_265, + RD_264, + RD_263, + RD_262, + RD_261, + RD_260, + RD_259, + RD_258, + RD_257, + RD_256, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_287; + input WD_286; + input WD_285; + input WD_284; + input WD_283; + input WD_282; + input WD_281; + input WD_280; + input WD_279; + input WD_278; + input WD_277; + input WD_276; + input WD_275; + input WD_274; + input WD_273; + input WD_272; + input WD_271; + input WD_270; + input WD_269; + input WD_268; + input WD_267; + input WD_266; + input WD_265; + input WD_264; + input WD_263; + input WD_262; + input WD_261; + input WD_260; + input WD_259; + input WD_258; + input WD_257; + input WD_256; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_287; + output RD_286; + output RD_285; + output RD_284; + output RD_283; + output RD_282; + output RD_281; + output RD_280; + output RD_279; + output RD_278; + output RD_277; + output RD_276; + output RD_275; + output RD_274; + output RD_273; + output RD_272; + output RD_271; + output RD_270; + output RD_269; + output RD_268; + output RD_267; + output RD_266; + output RD_265; + output RD_264; + output RD_263; + output RD_262; + output RD_261; + output RD_260; + output RD_259; + output RD_258; + output RD_257; + output RD_256; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [287:0] rd_bus; + assign {RD_287, RD_286, RD_285, RD_284, RD_283, RD_282, RD_281, RD_280, RD_279, RD_278, RD_277, RD_276, RD_275, RD_274, RD_273, RD_272, RD_271, RD_270, RD_269, RD_268, RD_267, RD_266, RD_265, RD_264, RD_263, RD_262, RD_261, RD_260, RD_259, RD_258, RD_257, RD_256, RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_288x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_287, WD_286, WD_285, WD_284, WD_283, WD_282, WD_281, WD_280, WD_279, WD_278, WD_277, WD_276, WD_275, WD_274, WD_273, WD_272, WD_271, WD_270, WD_269, WD_268, WD_267, WD_266, WD_265, WD_264, WD_263, WD_262, WD_261, WD_260, WD_259, WD_258, WD_257, WD_256, WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X288_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=64 addr=6b +module RAMPDP_64X64_GL_M1_D2 ( + CLK, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [63:0] rd_bus; + assign {RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_64x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X64_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=64 width=66 addr=6b +module RAMPDP_64X66_GL_M1_D2 ( + CLK, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [65:0] rd_bus; + assign {RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_66x64_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_64X66_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=80 width=16 addr=7b +module RAMPDP_80X16_GL_M2_D2 ( + CLK, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [15:0] rd_bus; + assign {RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_16x80_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_80X16_GL_M2_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=80 width=226 addr=7b +module RAMPDP_80X226_GL_M1_D2 ( + CLK, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [225:0] rd_bus; + assign {RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_226x80_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_80X226_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=80 width=256 addr=7b +module RAMPDP_80X256_GL_M1_D2 ( + CLK, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [255:0] rd_bus; + assign {RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_256x80_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_80X256_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=80 width=288 addr=7b +module RAMPDP_80X288_GL_M1_D2 ( + CLK, + WD_287, + WD_286, + WD_285, + WD_284, + WD_283, + WD_282, + WD_281, + WD_280, + WD_279, + WD_278, + WD_277, + WD_276, + WD_275, + WD_274, + WD_273, + WD_272, + WD_271, + WD_270, + WD_269, + WD_268, + WD_267, + WD_266, + WD_265, + WD_264, + WD_263, + WD_262, + WD_261, + WD_260, + WD_259, + WD_258, + WD_257, + WD_256, + WD_255, + WD_254, + WD_253, + WD_252, + WD_251, + WD_250, + WD_249, + WD_248, + WD_247, + WD_246, + WD_245, + WD_244, + WD_243, + WD_242, + WD_241, + WD_240, + WD_239, + WD_238, + WD_237, + WD_236, + WD_235, + WD_234, + WD_233, + WD_232, + WD_231, + WD_230, + WD_229, + WD_228, + WD_227, + WD_226, + WD_225, + WD_224, + WD_223, + WD_222, + WD_221, + WD_220, + WD_219, + WD_218, + WD_217, + WD_216, + WD_215, + WD_214, + WD_213, + WD_212, + WD_211, + WD_210, + WD_209, + WD_208, + WD_207, + WD_206, + WD_205, + WD_204, + WD_203, + WD_202, + WD_201, + WD_200, + WD_199, + WD_198, + WD_197, + WD_196, + WD_195, + WD_194, + WD_193, + WD_192, + WD_191, + WD_190, + WD_189, + WD_188, + WD_187, + WD_186, + WD_185, + WD_184, + WD_183, + WD_182, + WD_181, + WD_180, + WD_179, + WD_178, + WD_177, + WD_176, + WD_175, + WD_174, + WD_173, + WD_172, + WD_171, + WD_170, + WD_169, + WD_168, + WD_167, + WD_166, + WD_165, + WD_164, + WD_163, + WD_162, + WD_161, + WD_160, + WD_159, + WD_158, + WD_157, + WD_156, + WD_155, + WD_154, + WD_153, + WD_152, + WD_151, + WD_150, + WD_149, + WD_148, + WD_147, + WD_146, + WD_145, + WD_144, + WD_143, + WD_142, + WD_141, + WD_140, + WD_139, + WD_138, + WD_137, + WD_136, + WD_135, + WD_134, + WD_133, + WD_132, + WD_131, + WD_130, + WD_129, + WD_128, + WD_127, + WD_126, + WD_125, + WD_124, + WD_123, + WD_122, + WD_121, + WD_120, + WD_119, + WD_118, + WD_117, + WD_116, + WD_115, + WD_114, + WD_113, + WD_112, + WD_111, + WD_110, + WD_109, + WD_108, + WD_107, + WD_106, + WD_105, + WD_104, + WD_103, + WD_102, + WD_101, + WD_100, + WD_99, + WD_98, + WD_97, + WD_96, + WD_95, + WD_94, + WD_93, + WD_92, + WD_91, + WD_90, + WD_89, + WD_88, + WD_87, + WD_86, + WD_85, + WD_84, + WD_83, + WD_82, + WD_81, + WD_80, + WD_79, + WD_78, + WD_77, + WD_76, + WD_75, + WD_74, + WD_73, + WD_72, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_287, + RD_286, + RD_285, + RD_284, + RD_283, + RD_282, + RD_281, + RD_280, + RD_279, + RD_278, + RD_277, + RD_276, + RD_275, + RD_274, + RD_273, + RD_272, + RD_271, + RD_270, + RD_269, + RD_268, + RD_267, + RD_266, + RD_265, + RD_264, + RD_263, + RD_262, + RD_261, + RD_260, + RD_259, + RD_258, + RD_257, + RD_256, + RD_255, + RD_254, + RD_253, + RD_252, + RD_251, + RD_250, + RD_249, + RD_248, + RD_247, + RD_246, + RD_245, + RD_244, + RD_243, + RD_242, + RD_241, + RD_240, + RD_239, + RD_238, + RD_237, + RD_236, + RD_235, + RD_234, + RD_233, + RD_232, + RD_231, + RD_230, + RD_229, + RD_228, + RD_227, + RD_226, + RD_225, + RD_224, + RD_223, + RD_222, + RD_221, + RD_220, + RD_219, + RD_218, + RD_217, + RD_216, + RD_215, + RD_214, + RD_213, + RD_212, + RD_211, + RD_210, + RD_209, + RD_208, + RD_207, + RD_206, + RD_205, + RD_204, + RD_203, + RD_202, + RD_201, + RD_200, + RD_199, + RD_198, + RD_197, + RD_196, + RD_195, + RD_194, + RD_193, + RD_192, + RD_191, + RD_190, + RD_189, + RD_188, + RD_187, + RD_186, + RD_185, + RD_184, + RD_183, + RD_182, + RD_181, + RD_180, + RD_179, + RD_178, + RD_177, + RD_176, + RD_175, + RD_174, + RD_173, + RD_172, + RD_171, + RD_170, + RD_169, + RD_168, + RD_167, + RD_166, + RD_165, + RD_164, + RD_163, + RD_162, + RD_161, + RD_160, + RD_159, + RD_158, + RD_157, + RD_156, + RD_155, + RD_154, + RD_153, + RD_152, + RD_151, + RD_150, + RD_149, + RD_148, + RD_147, + RD_146, + RD_145, + RD_144, + RD_143, + RD_142, + RD_141, + RD_140, + RD_139, + RD_138, + RD_137, + RD_136, + RD_135, + RD_134, + RD_133, + RD_132, + RD_131, + RD_130, + RD_129, + RD_128, + RD_127, + RD_126, + RD_125, + RD_124, + RD_123, + RD_122, + RD_121, + RD_120, + RD_119, + RD_118, + RD_117, + RD_116, + RD_115, + RD_114, + RD_113, + RD_112, + RD_111, + RD_110, + RD_109, + RD_108, + RD_107, + RD_106, + RD_105, + RD_104, + RD_103, + RD_102, + RD_101, + RD_100, + RD_99, + RD_98, + RD_97, + RD_96, + RD_95, + RD_94, + RD_93, + RD_92, + RD_91, + RD_90, + RD_89, + RD_88, + RD_87, + RD_86, + RD_85, + RD_84, + RD_83, + RD_82, + RD_81, + RD_80, + RD_79, + RD_78, + RD_77, + RD_76, + RD_75, + RD_74, + RD_73, + RD_72, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_287; + input WD_286; + input WD_285; + input WD_284; + input WD_283; + input WD_282; + input WD_281; + input WD_280; + input WD_279; + input WD_278; + input WD_277; + input WD_276; + input WD_275; + input WD_274; + input WD_273; + input WD_272; + input WD_271; + input WD_270; + input WD_269; + input WD_268; + input WD_267; + input WD_266; + input WD_265; + input WD_264; + input WD_263; + input WD_262; + input WD_261; + input WD_260; + input WD_259; + input WD_258; + input WD_257; + input WD_256; + input WD_255; + input WD_254; + input WD_253; + input WD_252; + input WD_251; + input WD_250; + input WD_249; + input WD_248; + input WD_247; + input WD_246; + input WD_245; + input WD_244; + input WD_243; + input WD_242; + input WD_241; + input WD_240; + input WD_239; + input WD_238; + input WD_237; + input WD_236; + input WD_235; + input WD_234; + input WD_233; + input WD_232; + input WD_231; + input WD_230; + input WD_229; + input WD_228; + input WD_227; + input WD_226; + input WD_225; + input WD_224; + input WD_223; + input WD_222; + input WD_221; + input WD_220; + input WD_219; + input WD_218; + input WD_217; + input WD_216; + input WD_215; + input WD_214; + input WD_213; + input WD_212; + input WD_211; + input WD_210; + input WD_209; + input WD_208; + input WD_207; + input WD_206; + input WD_205; + input WD_204; + input WD_203; + input WD_202; + input WD_201; + input WD_200; + input WD_199; + input WD_198; + input WD_197; + input WD_196; + input WD_195; + input WD_194; + input WD_193; + input WD_192; + input WD_191; + input WD_190; + input WD_189; + input WD_188; + input WD_187; + input WD_186; + input WD_185; + input WD_184; + input WD_183; + input WD_182; + input WD_181; + input WD_180; + input WD_179; + input WD_178; + input WD_177; + input WD_176; + input WD_175; + input WD_174; + input WD_173; + input WD_172; + input WD_171; + input WD_170; + input WD_169; + input WD_168; + input WD_167; + input WD_166; + input WD_165; + input WD_164; + input WD_163; + input WD_162; + input WD_161; + input WD_160; + input WD_159; + input WD_158; + input WD_157; + input WD_156; + input WD_155; + input WD_154; + input WD_153; + input WD_152; + input WD_151; + input WD_150; + input WD_149; + input WD_148; + input WD_147; + input WD_146; + input WD_145; + input WD_144; + input WD_143; + input WD_142; + input WD_141; + input WD_140; + input WD_139; + input WD_138; + input WD_137; + input WD_136; + input WD_135; + input WD_134; + input WD_133; + input WD_132; + input WD_131; + input WD_130; + input WD_129; + input WD_128; + input WD_127; + input WD_126; + input WD_125; + input WD_124; + input WD_123; + input WD_122; + input WD_121; + input WD_120; + input WD_119; + input WD_118; + input WD_117; + input WD_116; + input WD_115; + input WD_114; + input WD_113; + input WD_112; + input WD_111; + input WD_110; + input WD_109; + input WD_108; + input WD_107; + input WD_106; + input WD_105; + input WD_104; + input WD_103; + input WD_102; + input WD_101; + input WD_100; + input WD_99; + input WD_98; + input WD_97; + input WD_96; + input WD_95; + input WD_94; + input WD_93; + input WD_92; + input WD_91; + input WD_90; + input WD_89; + input WD_88; + input WD_87; + input WD_86; + input WD_85; + input WD_84; + input WD_83; + input WD_82; + input WD_81; + input WD_80; + input WD_79; + input WD_78; + input WD_77; + input WD_76; + input WD_75; + input WD_74; + input WD_73; + input WD_72; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_287; + output RD_286; + output RD_285; + output RD_284; + output RD_283; + output RD_282; + output RD_281; + output RD_280; + output RD_279; + output RD_278; + output RD_277; + output RD_276; + output RD_275; + output RD_274; + output RD_273; + output RD_272; + output RD_271; + output RD_270; + output RD_269; + output RD_268; + output RD_267; + output RD_266; + output RD_265; + output RD_264; + output RD_263; + output RD_262; + output RD_261; + output RD_260; + output RD_259; + output RD_258; + output RD_257; + output RD_256; + output RD_255; + output RD_254; + output RD_253; + output RD_252; + output RD_251; + output RD_250; + output RD_249; + output RD_248; + output RD_247; + output RD_246; + output RD_245; + output RD_244; + output RD_243; + output RD_242; + output RD_241; + output RD_240; + output RD_239; + output RD_238; + output RD_237; + output RD_236; + output RD_235; + output RD_234; + output RD_233; + output RD_232; + output RD_231; + output RD_230; + output RD_229; + output RD_228; + output RD_227; + output RD_226; + output RD_225; + output RD_224; + output RD_223; + output RD_222; + output RD_221; + output RD_220; + output RD_219; + output RD_218; + output RD_217; + output RD_216; + output RD_215; + output RD_214; + output RD_213; + output RD_212; + output RD_211; + output RD_210; + output RD_209; + output RD_208; + output RD_207; + output RD_206; + output RD_205; + output RD_204; + output RD_203; + output RD_202; + output RD_201; + output RD_200; + output RD_199; + output RD_198; + output RD_197; + output RD_196; + output RD_195; + output RD_194; + output RD_193; + output RD_192; + output RD_191; + output RD_190; + output RD_189; + output RD_188; + output RD_187; + output RD_186; + output RD_185; + output RD_184; + output RD_183; + output RD_182; + output RD_181; + output RD_180; + output RD_179; + output RD_178; + output RD_177; + output RD_176; + output RD_175; + output RD_174; + output RD_173; + output RD_172; + output RD_171; + output RD_170; + output RD_169; + output RD_168; + output RD_167; + output RD_166; + output RD_165; + output RD_164; + output RD_163; + output RD_162; + output RD_161; + output RD_160; + output RD_159; + output RD_158; + output RD_157; + output RD_156; + output RD_155; + output RD_154; + output RD_153; + output RD_152; + output RD_151; + output RD_150; + output RD_149; + output RD_148; + output RD_147; + output RD_146; + output RD_145; + output RD_144; + output RD_143; + output RD_142; + output RD_141; + output RD_140; + output RD_139; + output RD_138; + output RD_137; + output RD_136; + output RD_135; + output RD_134; + output RD_133; + output RD_132; + output RD_131; + output RD_130; + output RD_129; + output RD_128; + output RD_127; + output RD_126; + output RD_125; + output RD_124; + output RD_123; + output RD_122; + output RD_121; + output RD_120; + output RD_119; + output RD_118; + output RD_117; + output RD_116; + output RD_115; + output RD_114; + output RD_113; + output RD_112; + output RD_111; + output RD_110; + output RD_109; + output RD_108; + output RD_107; + output RD_106; + output RD_105; + output RD_104; + output RD_103; + output RD_102; + output RD_101; + output RD_100; + output RD_99; + output RD_98; + output RD_97; + output RD_96; + output RD_95; + output RD_94; + output RD_93; + output RD_92; + output RD_91; + output RD_90; + output RD_89; + output RD_88; + output RD_87; + output RD_86; + output RD_85; + output RD_84; + output RD_83; + output RD_82; + output RD_81; + output RD_80; + output RD_79; + output RD_78; + output RD_77; + output RD_76; + output RD_75; + output RD_74; + output RD_73; + output RD_72; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [287:0] rd_bus; + assign {RD_287, RD_286, RD_285, RD_284, RD_283, RD_282, RD_281, RD_280, RD_279, RD_278, RD_277, RD_276, RD_275, RD_274, RD_273, RD_272, RD_271, RD_270, RD_269, RD_268, RD_267, RD_266, RD_265, RD_264, RD_263, RD_262, RD_261, RD_260, RD_259, RD_258, RD_257, RD_256, RD_255, RD_254, RD_253, RD_252, RD_251, RD_250, RD_249, RD_248, RD_247, RD_246, RD_245, RD_244, RD_243, RD_242, RD_241, RD_240, RD_239, RD_238, RD_237, RD_236, RD_235, RD_234, RD_233, RD_232, RD_231, RD_230, RD_229, RD_228, RD_227, RD_226, RD_225, RD_224, RD_223, RD_222, RD_221, RD_220, RD_219, RD_218, RD_217, RD_216, RD_215, RD_214, RD_213, RD_212, RD_211, RD_210, RD_209, RD_208, RD_207, RD_206, RD_205, RD_204, RD_203, RD_202, RD_201, RD_200, RD_199, RD_198, RD_197, RD_196, RD_195, RD_194, RD_193, RD_192, RD_191, RD_190, RD_189, RD_188, RD_187, RD_186, RD_185, RD_184, RD_183, RD_182, RD_181, RD_180, RD_179, RD_178, RD_177, RD_176, RD_175, RD_174, RD_173, RD_172, RD_171, RD_170, RD_169, RD_168, RD_167, RD_166, RD_165, RD_164, RD_163, RD_162, RD_161, RD_160, RD_159, RD_158, RD_157, RD_156, RD_155, RD_154, RD_153, RD_152, RD_151, RD_150, RD_149, RD_148, RD_147, RD_146, RD_145, RD_144, RD_143, RD_142, RD_141, RD_140, RD_139, RD_138, RD_137, RD_136, RD_135, RD_134, RD_133, RD_132, RD_131, RD_130, RD_129, RD_128, RD_127, RD_126, RD_125, RD_124, RD_123, RD_122, RD_121, RD_120, RD_119, RD_118, RD_117, RD_116, RD_115, RD_114, RD_113, RD_112, RD_111, RD_110, RD_109, RD_108, RD_107, RD_106, RD_105, RD_104, RD_103, RD_102, RD_101, RD_100, RD_99, RD_98, RD_97, RD_96, RD_95, RD_94, RD_93, RD_92, RD_91, RD_90, RD_89, RD_88, RD_87, RD_86, RD_85, RD_84, RD_83, RD_82, RD_81, RD_80, RD_79, RD_78, RD_77, RD_76, RD_75, RD_74, RD_73, RD_72, RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_288x80_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_287, WD_286, WD_285, WD_284, WD_283, WD_282, WD_281, WD_280, WD_279, WD_278, WD_277, WD_276, WD_275, WD_274, WD_273, WD_272, WD_271, WD_270, WD_269, WD_268, WD_267, WD_266, WD_265, WD_264, WD_263, WD_262, WD_261, WD_260, WD_259, WD_258, WD_257, WD_256, WD_255, WD_254, WD_253, WD_252, WD_251, WD_250, WD_249, WD_248, WD_247, WD_246, WD_245, WD_244, WD_243, WD_242, WD_241, WD_240, WD_239, WD_238, WD_237, WD_236, WD_235, WD_234, WD_233, WD_232, WD_231, WD_230, WD_229, WD_228, WD_227, WD_226, WD_225, WD_224, WD_223, WD_222, WD_221, WD_220, WD_219, WD_218, WD_217, WD_216, WD_215, WD_214, WD_213, WD_212, WD_211, WD_210, WD_209, WD_208, WD_207, WD_206, WD_205, WD_204, WD_203, WD_202, WD_201, WD_200, WD_199, WD_198, WD_197, WD_196, WD_195, WD_194, WD_193, WD_192, WD_191, WD_190, WD_189, WD_188, WD_187, WD_186, WD_185, WD_184, WD_183, WD_182, WD_181, WD_180, WD_179, WD_178, WD_177, WD_176, WD_175, WD_174, WD_173, WD_172, WD_171, WD_170, WD_169, WD_168, WD_167, WD_166, WD_165, WD_164, WD_163, WD_162, WD_161, WD_160, WD_159, WD_158, WD_157, WD_156, WD_155, WD_154, WD_153, WD_152, WD_151, WD_150, WD_149, WD_148, WD_147, WD_146, WD_145, WD_144, WD_143, WD_142, WD_141, WD_140, WD_139, WD_138, WD_137, WD_136, WD_135, WD_134, WD_133, WD_132, WD_131, WD_130, WD_129, WD_128, WD_127, WD_126, WD_125, WD_124, WD_123, WD_122, WD_121, WD_120, WD_119, WD_118, WD_117, WD_116, WD_115, WD_114, WD_113, WD_112, WD_111, WD_110, WD_109, WD_108, WD_107, WD_106, WD_105, WD_104, WD_103, WD_102, WD_101, WD_100, WD_99, WD_98, WD_97, WD_96, WD_95, WD_94, WD_93, WD_92, WD_91, WD_90, WD_89, WD_88, WD_87, WD_86, WD_85, WD_84, WD_83, WD_82, WD_81, WD_80, WD_79, WD_78, WD_77, WD_76, WD_75, WD_74, WD_73, WD_72, WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_80X288_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=80 width=66 addr=7b +module RAMPDP_80X66_GL_M1_D2 ( + CLK, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [65:0] rd_bus; + assign {RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_66x80_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_80X66_GL_M1_D2 + +// RAMPDP single-clock pseudo-dual-port 1R1W (CLK) | depth=80 width=72 addr=7b +module RAMPDP_80X72_GL_M1_D2 ( + CLK, + WD_71, + WD_70, + WD_69, + WD_68, + WD_67, + WD_66, + WD_65, + WD_64, + WD_63, + WD_62, + WD_61, + WD_60, + WD_59, + WD_58, + WD_57, + WD_56, + WD_55, + WD_54, + WD_53, + WD_52, + WD_51, + WD_50, + WD_49, + WD_48, + WD_47, + WD_46, + WD_45, + WD_44, + WD_43, + WD_42, + WD_41, + WD_40, + WD_39, + WD_38, + WD_37, + WD_36, + WD_35, + WD_34, + WD_33, + WD_32, + WD_31, + WD_30, + WD_29, + WD_28, + WD_27, + WD_26, + WD_25, + WD_24, + WD_23, + WD_22, + WD_21, + WD_20, + WD_19, + WD_18, + WD_17, + WD_16, + WD_15, + WD_14, + WD_13, + WD_12, + WD_11, + WD_10, + WD_9, + WD_8, + WD_7, + WD_6, + WD_5, + WD_4, + WD_3, + WD_2, + WD_1, + WD_0, + RE, + WE, + RADR_6, + RADR_5, + RADR_4, + RADR_3, + RADR_2, + RADR_1, + RADR_0, + WADR_6, + WADR_5, + WADR_4, + WADR_3, + WADR_2, + WADR_1, + WADR_0, + IDDQ, + SVOP_0, + SVOP_1, + SVOP_2, + SVOP_3, + SVOP_4, + SVOP_5, + SVOP_6, + SVOP_7, + SLEEP_EN_0, + SLEEP_EN_1, + SLEEP_EN_2, + SLEEP_EN_3, + SLEEP_EN_4, + SLEEP_EN_5, + SLEEP_EN_6, + SLEEP_EN_7, + RET_EN, + RD_71, + RD_70, + RD_69, + RD_68, + RD_67, + RD_66, + RD_65, + RD_64, + RD_63, + RD_62, + RD_61, + RD_60, + RD_59, + RD_58, + RD_57, + RD_56, + RD_55, + RD_54, + RD_53, + RD_52, + RD_51, + RD_50, + RD_49, + RD_48, + RD_47, + RD_46, + RD_45, + RD_44, + RD_43, + RD_42, + RD_41, + RD_40, + RD_39, + RD_38, + RD_37, + RD_36, + RD_35, + RD_34, + RD_33, + RD_32, + RD_31, + RD_30, + RD_29, + RD_28, + RD_27, + RD_26, + RD_25, + RD_24, + RD_23, + RD_22, + RD_21, + RD_20, + RD_19, + RD_18, + RD_17, + RD_16, + RD_15, + RD_14, + RD_13, + RD_12, + RD_11, + RD_10, + RD_9, + RD_8, + RD_7, + RD_6, + RD_5, + RD_4, + RD_3, + RD_2, + RD_1, + RD_0 +); + input CLK; + input WD_71; + input WD_70; + input WD_69; + input WD_68; + input WD_67; + input WD_66; + input WD_65; + input WD_64; + input WD_63; + input WD_62; + input WD_61; + input WD_60; + input WD_59; + input WD_58; + input WD_57; + input WD_56; + input WD_55; + input WD_54; + input WD_53; + input WD_52; + input WD_51; + input WD_50; + input WD_49; + input WD_48; + input WD_47; + input WD_46; + input WD_45; + input WD_44; + input WD_43; + input WD_42; + input WD_41; + input WD_40; + input WD_39; + input WD_38; + input WD_37; + input WD_36; + input WD_35; + input WD_34; + input WD_33; + input WD_32; + input WD_31; + input WD_30; + input WD_29; + input WD_28; + input WD_27; + input WD_26; + input WD_25; + input WD_24; + input WD_23; + input WD_22; + input WD_21; + input WD_20; + input WD_19; + input WD_18; + input WD_17; + input WD_16; + input WD_15; + input WD_14; + input WD_13; + input WD_12; + input WD_11; + input WD_10; + input WD_9; + input WD_8; + input WD_7; + input WD_6; + input WD_5; + input WD_4; + input WD_3; + input WD_2; + input WD_1; + input WD_0; + input RE; + input WE; + input RADR_6; + input RADR_5; + input RADR_4; + input RADR_3; + input RADR_2; + input RADR_1; + input RADR_0; + input WADR_6; + input WADR_5; + input WADR_4; + input WADR_3; + input WADR_2; + input WADR_1; + input WADR_0; + input IDDQ; + input SVOP_0; + input SVOP_1; + input SVOP_2; + input SVOP_3; + input SVOP_4; + input SVOP_5; + input SVOP_6; + input SVOP_7; + input SLEEP_EN_0; + input SLEEP_EN_1; + input SLEEP_EN_2; + input SLEEP_EN_3; + input SLEEP_EN_4; + input SLEEP_EN_5; + input SLEEP_EN_6; + input SLEEP_EN_7; + input RET_EN; + output RD_71; + output RD_70; + output RD_69; + output RD_68; + output RD_67; + output RD_66; + output RD_65; + output RD_64; + output RD_63; + output RD_62; + output RD_61; + output RD_60; + output RD_59; + output RD_58; + output RD_57; + output RD_56; + output RD_55; + output RD_54; + output RD_53; + output RD_52; + output RD_51; + output RD_50; + output RD_49; + output RD_48; + output RD_47; + output RD_46; + output RD_45; + output RD_44; + output RD_43; + output RD_42; + output RD_41; + output RD_40; + output RD_39; + output RD_38; + output RD_37; + output RD_36; + output RD_35; + output RD_34; + output RD_33; + output RD_32; + output RD_31; + output RD_30; + output RD_29; + output RD_28; + output RD_27; + output RD_26; + output RD_25; + output RD_24; + output RD_23; + output RD_22; + output RD_21; + output RD_20; + output RD_19; + output RD_18; + output RD_17; + output RD_16; + output RD_15; + output RD_14; + output RD_13; + output RD_12; + output RD_11; + output RD_10; + output RD_9; + output RD_8; + output RD_7; + output RD_6; + output RD_5; + output RD_4; + output RD_3; + output RD_2; + output RD_1; + output RD_0; + + // Internal read-data bus + wire [71:0] rd_bus; + assign {RD_71, RD_70, RD_69, RD_68, RD_67, RD_66, RD_65, RD_64, RD_63, RD_62, RD_61, RD_60, RD_59, RD_58, RD_57, RD_56, RD_55, RD_54, RD_53, RD_52, RD_51, RD_50, RD_49, RD_48, RD_47, RD_46, RD_45, RD_44, RD_43, RD_42, RD_41, RD_40, RD_39, RD_38, RD_37, RD_36, RD_35, RD_34, RD_33, RD_32, RD_31, RD_30, RD_29, RD_28, RD_27, RD_26, RD_25, RD_24, RD_23, RD_22, RD_21, RD_20, RD_19, RD_18, RD_17, RD_16, RD_15, RD_14, RD_13, RD_12, RD_11, RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = rd_bus; + + // NC (no fakeram equivalent — declared for compatibility, tied off): + // IDDQ, SVOP_0, SVOP_1, SVOP_2, SVOP_3, SVOP_4, SVOP_5, SVOP_6, SVOP_7, SLEEP_EN_0, SLEEP_EN_1, SLEEP_EN_2, SLEEP_EN_3, SLEEP_EN_4, SLEEP_EN_5, SLEEP_EN_6, SLEEP_EN_7, RET_EN + + fakeram_72x80_1r1w sram ( + .r0_clk (CLK), + .w0_clk (CLK), + .r0_ce_in (RE), + .w0_ce_in (1'b1), + .w0_we_in (WE), + .r0_addr_in ({RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}), + .w0_addr_in ({WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}), + .w0_wd_in ({WD_71, WD_70, WD_69, WD_68, WD_67, WD_66, WD_65, WD_64, WD_63, WD_62, WD_61, WD_60, WD_59, WD_58, WD_57, WD_56, WD_55, WD_54, WD_53, WD_52, WD_51, WD_50, WD_49, WD_48, WD_47, WD_46, WD_45, WD_44, WD_43, WD_42, WD_41, WD_40, WD_39, WD_38, WD_37, WD_36, WD_35, WD_34, WD_33, WD_32, WD_31, WD_30, WD_29, WD_28, WD_27, WD_26, WD_25, WD_24, WD_23, WD_22, WD_21, WD_20, WD_19, WD_18, WD_17, WD_16, WD_15, WD_14, WD_13, WD_12, WD_11, WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}), + .r0_rd_out (rd_bus) + ); + +endmodule // RAMPDP_80X72_GL_M1_D2 \ No newline at end of file diff --git a/designs/src/NVDLA/verilog.mk b/designs/src/NVDLA/verilog.mk new file mode 100644 index 0000000..2d938aa --- /dev/null +++ b/designs/src/NVDLA/verilog.mk @@ -0,0 +1,11 @@ +VMOD_RAM_DIR := $(BENCH_DESIGN_HOME)/src/NVDLA/vmod/rams/synth +VMOD_VLIBS_DIR := $(BENCH_DESIGN_HOME)/src/NVDLA/vmod/vlibs +VMOD_NVDLA_DIR := $(BENCH_DESIGN_HOME)/src/NVDLA/vmod/nvdla + +# Write file list to disk, don't expand into env + +export VERILOG_FILES := $(shell find $(VMOD_RAM_DIR) $(VMOD_VLIBS_DIR) $(VMOD_NVDLA_DIR) -type f -name "*.v") \ + $(BENCH_DESIGN_HOME)/src/NVDLA/macros.v + +export VERILOG_INCLUDE_DIRS := $(sort $(shell find $(VMOD) -type f -name "*.vh" -printf "%h\n" | sort -u)) + diff --git a/designs/src/NVDLA/vmod/include/NV_HWACC_NVDLA_tick_defines.vh b/designs/src/NVDLA/vmod/include/NV_HWACC_NVDLA_tick_defines.vh new file mode 100644 index 0000000..fb015ed --- /dev/null +++ b/designs/src/NVDLA/vmod/include/NV_HWACC_NVDLA_tick_defines.vh @@ -0,0 +1,75 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_HWACC_NVDLA_tick_defines.vh +//`include "NV_HWACC_common_tick_defines.vh" +`ifndef NV_HWACC_NVDLA_tick_defines_vh +`define NV_HWACC_NVDLA_tick_defines_vh +//this section contains IP specific defines +`ifdef NV_FPGA_SYSTEM +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA +`define NV_HWACC_NVDLA_SFPGA_UFPGA +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_EMU +`endif +`endif +`ifdef NV_FPGA_UNIT +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA +`define NV_HWACC_NVDLA_SFPGA_UFPGA +`endif +`ifndef NV_HWACC_NVDLA_UFPGA_EMU +`define NV_HWACC_NVDLA_UFPGA_EMU +`endif +`endif +`ifdef NV_EMULATION +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_UFPGA_EMU +`define NV_HWACC_NVDLA_UFPGA_EMU +`endif +`endif +//DEFINES +//defines shared between system fpga and unit fpga and emulation +`ifdef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +//add defines here +`endif +//defines shared between system fpga and unit fpga +`ifdef NV_HWACC_NVDLA_SFPGA_UFPGA +//add defines here +`endif +//defines shared between system fpga and emulation +`ifdef NV_HWACC_NVDLA_SFPGA_EMU +//add defines here +`endif +//defines shared between unit fpga and emulation +`ifdef NV_HWACC_NVDLA_UFPGA_EMU +//add defines here +`endif +//defines used only in system fpga +`ifdef NV_FPGA_SYSTEM +//add defines here +`endif +//defines used only in unit fpga +`ifdef NV_FPGA_UNIT +//add defines here +`endif +//defines used only in emulation +`ifdef NV_EMULATION +//add defines here +`endif +`endif //NV_HWACC_NVDLA_tick_defines_vh diff --git a/designs/src/NVDLA/vmod/include/NV_HWACC_NVDLA_tick_defines.vh.vcp b/designs/src/NVDLA/vmod/include/NV_HWACC_NVDLA_tick_defines.vh.vcp new file mode 100644 index 0000000..fb015ed --- /dev/null +++ b/designs/src/NVDLA/vmod/include/NV_HWACC_NVDLA_tick_defines.vh.vcp @@ -0,0 +1,75 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_HWACC_NVDLA_tick_defines.vh +//`include "NV_HWACC_common_tick_defines.vh" +`ifndef NV_HWACC_NVDLA_tick_defines_vh +`define NV_HWACC_NVDLA_tick_defines_vh +//this section contains IP specific defines +`ifdef NV_FPGA_SYSTEM +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA +`define NV_HWACC_NVDLA_SFPGA_UFPGA +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_EMU +`endif +`endif +`ifdef NV_FPGA_UNIT +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA +`define NV_HWACC_NVDLA_SFPGA_UFPGA +`endif +`ifndef NV_HWACC_NVDLA_UFPGA_EMU +`define NV_HWACC_NVDLA_UFPGA_EMU +`endif +`endif +`ifdef NV_EMULATION +`ifndef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_SFPGA_EMU +`define NV_HWACC_NVDLA_SFPGA_EMU +`endif +`ifndef NV_HWACC_NVDLA_UFPGA_EMU +`define NV_HWACC_NVDLA_UFPGA_EMU +`endif +`endif +//DEFINES +//defines shared between system fpga and unit fpga and emulation +`ifdef NV_HWACC_NVDLA_SFPGA_UFPGA_EMU +//add defines here +`endif +//defines shared between system fpga and unit fpga +`ifdef NV_HWACC_NVDLA_SFPGA_UFPGA +//add defines here +`endif +//defines shared between system fpga and emulation +`ifdef NV_HWACC_NVDLA_SFPGA_EMU +//add defines here +`endif +//defines shared between unit fpga and emulation +`ifdef NV_HWACC_NVDLA_UFPGA_EMU +//add defines here +`endif +//defines used only in system fpga +`ifdef NV_FPGA_SYSTEM +//add defines here +`endif +//defines used only in unit fpga +`ifdef NV_FPGA_UNIT +//add defines here +`endif +//defines used only in emulation +`ifdef NV_EMULATION +//add defines here +`endif +`endif //NV_HWACC_NVDLA_tick_defines_vh diff --git a/designs/src/NVDLA/vmod/include/simulate_x_tick.vh b/designs/src/NVDLA/vmod/include/simulate_x_tick.vh new file mode 100644 index 0000000..54e3a5a --- /dev/null +++ b/designs/src/NVDLA/vmod/include/simulate_x_tick.vh @@ -0,0 +1,40 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: simulate_x_tick.vh +`ifdef _SIMULATE_X_VH_ +`else +`define _SIMULATE_X_VH_ +`ifndef SYNTHESIS +`define SIMULATION_ONLY +`endif +// deprecated tick defines +`ifdef SIMULATION_ONLY +`define x_or_0 1'bx +`define x_or_1 1'bx +`else +`define x_or_0 1'b0 +`define x_or_1 1'b1 +`endif +// formerly recommended tick defines +`ifdef SIMULATION_ONLY +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +// newly recommended tick defines +// (-sv parsing is enabled everywhere now, and explicit widths are no longer needed) +`ifdef SIMULATION_ONLY +`define sv_x_or_0 'x +`define sv_x_or_1 'x +`else +`define sv_x_or_0 '0 +`define sv_x_or_1 '1 +`endif +`endif diff --git a/designs/src/NVDLA/vmod/include/simulate_x_tick.vh.vcp b/designs/src/NVDLA/vmod/include/simulate_x_tick.vh.vcp new file mode 100644 index 0000000..54e3a5a --- /dev/null +++ b/designs/src/NVDLA/vmod/include/simulate_x_tick.vh.vcp @@ -0,0 +1,40 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: simulate_x_tick.vh +`ifdef _SIMULATE_X_VH_ +`else +`define _SIMULATE_X_VH_ +`ifndef SYNTHESIS +`define SIMULATION_ONLY +`endif +// deprecated tick defines +`ifdef SIMULATION_ONLY +`define x_or_0 1'bx +`define x_or_1 1'bx +`else +`define x_or_0 1'b0 +`define x_or_1 1'b1 +`endif +// formerly recommended tick defines +`ifdef SIMULATION_ONLY +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +// newly recommended tick defines +// (-sv parsing is enabled everywhere now, and explicit widths are no longer needed) +`ifdef SIMULATION_ONLY +`define sv_x_or_0 'x +`define sv_x_or_1 'x +`else +`define sv_x_or_0 '0 +`define sv_x_or_1 '1 +`endif +`endif diff --git a/designs/src/NVDLA/vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v b/designs/src/NVDLA/vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v new file mode 100644 index 0000000..90d5ceb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v @@ -0,0 +1,78 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_apb2csb.v +module NV_NVDLA_apb2csb ( + pclk + ,prstn + ,csb2nvdla_ready + ,nvdla2csb_data + ,nvdla2csb_valid + ,paddr + ,penable + ,psel + ,pwdata + ,pwrite + ,csb2nvdla_addr + ,csb2nvdla_nposted + ,csb2nvdla_valid + ,csb2nvdla_wdat + ,csb2nvdla_write + ,prdata + ,pready + ); +input pclk; +input prstn; +//apb interface +input psel; +input penable; +input pwrite; +input [31:0] paddr; +input [31:0] pwdata; +output [31:0] prdata; +output pready; +//csb interface +output csb2nvdla_valid; +input csb2nvdla_ready; +output [15:0] csb2nvdla_addr; +output [31:0] csb2nvdla_wdat; +output csb2nvdla_write; +output csb2nvdla_nposted; +input nvdla2csb_valid; +input [31:0] nvdla2csb_data; +//input nvdla2csb_wr_complete; +reg rd_trans_low; +wire rd_trans_vld; +wire wr_trans_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign wr_trans_vld = psel & penable & pwrite; +assign rd_trans_vld = psel & penable & ~pwrite; +always @(posedge pclk or negedge prstn) begin + if (!prstn) begin + rd_trans_low <= 1'b0; + end else begin + if(nvdla2csb_valid & rd_trans_low) + rd_trans_low <= 1'b0; + else if (csb2nvdla_ready & rd_trans_vld) + rd_trans_low <= 1'b1; + end +end +assign csb2nvdla_valid = wr_trans_vld | rd_trans_vld & ~rd_trans_low; +assign csb2nvdla_addr = paddr[17:2]; +assign csb2nvdla_wdat = pwdata[31:0]; +assign csb2nvdla_write = pwrite; +assign csb2nvdla_nposted = 1'b0; +assign prdata = nvdla2csb_data[31:0]; +assign pready = ~(wr_trans_vld & ~csb2nvdla_ready | rd_trans_vld & ~nvdla2csb_valid); +endmodule // NV_NVDLA_apb2csb diff --git a/designs/src/NVDLA/vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v.vcp b/designs/src/NVDLA/vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v.vcp new file mode 100644 index 0000000..90d5ceb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/apb2csb/NV_NVDLA_apb2csb.v.vcp @@ -0,0 +1,78 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_apb2csb.v +module NV_NVDLA_apb2csb ( + pclk + ,prstn + ,csb2nvdla_ready + ,nvdla2csb_data + ,nvdla2csb_valid + ,paddr + ,penable + ,psel + ,pwdata + ,pwrite + ,csb2nvdla_addr + ,csb2nvdla_nposted + ,csb2nvdla_valid + ,csb2nvdla_wdat + ,csb2nvdla_write + ,prdata + ,pready + ); +input pclk; +input prstn; +//apb interface +input psel; +input penable; +input pwrite; +input [31:0] paddr; +input [31:0] pwdata; +output [31:0] prdata; +output pready; +//csb interface +output csb2nvdla_valid; +input csb2nvdla_ready; +output [15:0] csb2nvdla_addr; +output [31:0] csb2nvdla_wdat; +output csb2nvdla_write; +output csb2nvdla_nposted; +input nvdla2csb_valid; +input [31:0] nvdla2csb_data; +//input nvdla2csb_wr_complete; +reg rd_trans_low; +wire rd_trans_vld; +wire wr_trans_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign wr_trans_vld = psel & penable & pwrite; +assign rd_trans_vld = psel & penable & ~pwrite; +always @(posedge pclk or negedge prstn) begin + if (!prstn) begin + rd_trans_low <= 1'b0; + end else begin + if(nvdla2csb_valid & rd_trans_low) + rd_trans_low <= 1'b0; + else if (csb2nvdla_ready & rd_trans_vld) + rd_trans_low <= 1'b1; + end +end +assign csb2nvdla_valid = wr_trans_vld | rd_trans_vld & ~rd_trans_low; +assign csb2nvdla_addr = paddr[17:2]; +assign csb2nvdla_wdat = pwdata[31:0]; +assign csb2nvdla_write = pwrite; +assign csb2nvdla_nposted = 1'b0; +assign prdata = nvdla2csb_data[31:0]; +assign pready = ~(wr_trans_vld & ~csb2nvdla_ready | rd_trans_vld & ~nvdla2csb_valid); +endmodule // NV_NVDLA_apb2csb diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v new file mode 100644 index 0000000..2847591 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v @@ -0,0 +1,654 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_cq.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ld2st_wr_prdy + , ld2st_wr_idle + , ld2st_wr_pvld + , ld2st_wr_pd + , ld2st_rd_prdy + , ld2st_rd_pvld + , ld2st_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ld2st_wr_prdy; +output ld2st_wr_idle; +input ld2st_wr_pvld; +input [160:0] ld2st_wr_pd; +input ld2st_rd_prdy; +output ld2st_rd_pvld; +output [160:0] ld2st_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ld2st_wr_pvld_in; // registered ld2st_wr_pvld +reg wr_busy_in; // inputs being held this cycle? +assign ld2st_wr_prdy = !wr_busy_in; +wire ld2st_wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant ld2st_wr_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = ld2st_wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (ld2st_wr_pvld_in && ld2st_wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (ld2st_wr_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_wr_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + ld2st_wr_pvld_in <= ld2st_wr_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + ld2st_wr_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg ld2st_wr_busy_int; // copy for internal use +assign wr_reserving = ld2st_wr_pvld_in && !ld2st_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [4:0] ld2st_wr_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? ld2st_wr_count : (ld2st_wr_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (ld2st_wr_count + 1'd1) : ld2st_wr_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_20 = ( wr_count_next_no_wr_popping == 5'd20 ); +wire wr_count_next_is_20 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_20; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign ld2st_wr_busy_next = wr_count_next_is_20 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check ld2st_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = ld2st_wr_pvld_in && ld2st_wr_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_wr_busy_int <= 1'b0; + ld2st_wr_count <= 5'd0; + end else begin + ld2st_wr_busy_int <= ld2st_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ld2st_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ld2st_wr_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ld2st_wr_pvld_in +// +// RAM +// +reg [4:0] ld2st_wr_adr; // current write address +// spyglass disable_block W484 +// next ld2st_wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = (ld2st_wr_adr == 5'd19) ? 5'd0 : (ld2st_wr_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + ld2st_wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [4:0] ld2st_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ld2st_wr_count > 5'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && ld2st_wr_pvld; +wire [160:0] ld2st_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ld2st_wr_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( ld2st_wr_adr ) + , .ra ( (ld2st_wr_count == 0) ? 5'd20 : ld2st_rd_adr ) + , .dout ( ld2st_rd_pd_p ) + ); +wire [4:0] rd_adr_next_popping = (ld2st_rd_adr == 5'd19) ? 5'd0 : (ld2st_rd_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + ld2st_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ld2st_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ld2st_rd_pvld_p; // data out of fifo is valid +reg ld2st_rd_pvld_int; // internal copy of ld2st_rd_pvld +assign ld2st_rd_pvld = ld2st_rd_pvld_int; +assign rd_popping = ld2st_rd_pvld_p && !(ld2st_rd_pvld_int && !ld2st_rd_prdy); +reg [4:0] ld2st_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? ld2st_rd_count_p : + (ld2st_rd_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ld2st_rd_count_p + 1'd1) : + ld2st_rd_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ld2st_rd_pvld_p = ld2st_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_rd_count_p <= 5'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ld2st_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ld2st_rd_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [160:0] ld2st_rd_pd; // output data register +wire rd_req_next = (ld2st_rd_pvld_p || (ld2st_rd_pvld_int && !ld2st_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_rd_pvld_int <= 1'b0; + end else begin + ld2st_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ld2st_rd_pd <= ld2st_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ld2st_rd_pd <= {161{`x_or_0}}; + end +//synopsys translate_on +end +// +// Read-side Idle Calculation +// +wire rd_idle = !ld2st_rd_pvld_int && !rd_pushing && ld2st_rd_count_p == 0; +// +// Write-Side Idle Calculation +// +wire ld2st_wr_idle_d0 = !ld2st_wr_pvld_in && rd_idle && !wr_pushing && ld2st_wr_count == 0; +wire ld2st_wr_idle = ld2st_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ld2st_wr_pvld_in && !ld2st_wr_busy_int) || (ld2st_wr_busy_int != ld2st_wr_busy_next)) || (rd_pushing || rd_popping || (ld2st_rd_pvld_int && ld2st_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_cq_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd20 : wr_limit_reg} ) + , .curr ( {27'd0, ld2st_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_BDMA_cq +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [160:0] di; +input iwe; +input we; +input [4:0] wa; +input [4:0] ra; +output [160:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [160:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [160:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [4:0] Wa0_vmw; +reg we0_vmw; +reg [160:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout_p ) + ); +assign dout = (ra == 20) ? di_d : dout_p; +`else +reg [160:0] ram_ff0; +reg [160:0] ram_ff1; +reg [160:0] ram_ff2; +reg [160:0] ram_ff3; +reg [160:0] ram_ff4; +reg [160:0] ram_ff5; +reg [160:0] ram_ff6; +reg [160:0] ram_ff7; +reg [160:0] ram_ff8; +reg [160:0] ram_ff9; +reg [160:0] ram_ff10; +reg [160:0] ram_ff11; +reg [160:0] ram_ff12; +reg [160:0] ram_ff13; +reg [160:0] ram_ff14; +reg [160:0] ram_ff15; +reg [160:0] ram_ff16; +reg [160:0] ram_ff17; +reg [160:0] ram_ff18; +reg [160:0] ram_ff19; +always @( posedge clk_mgated ) begin + if ( we && wa == 5'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 5'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 5'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 5'd3 ) begin + ram_ff3 <= di_d; + end + if ( we && wa == 5'd4 ) begin + ram_ff4 <= di_d; + end + if ( we && wa == 5'd5 ) begin + ram_ff5 <= di_d; + end + if ( we && wa == 5'd6 ) begin + ram_ff6 <= di_d; + end + if ( we && wa == 5'd7 ) begin + ram_ff7 <= di_d; + end + if ( we && wa == 5'd8 ) begin + ram_ff8 <= di_d; + end + if ( we && wa == 5'd9 ) begin + ram_ff9 <= di_d; + end + if ( we && wa == 5'd10 ) begin + ram_ff10 <= di_d; + end + if ( we && wa == 5'd11 ) begin + ram_ff11 <= di_d; + end + if ( we && wa == 5'd12 ) begin + ram_ff12 <= di_d; + end + if ( we && wa == 5'd13 ) begin + ram_ff13 <= di_d; + end + if ( we && wa == 5'd14 ) begin + ram_ff14 <= di_d; + end + if ( we && wa == 5'd15 ) begin + ram_ff15 <= di_d; + end + if ( we && wa == 5'd16 ) begin + ram_ff16 <= di_d; + end + if ( we && wa == 5'd17 ) begin + ram_ff17 <= di_d; + end + if ( we && wa == 5'd18 ) begin + ram_ff18 <= di_d; + end + if ( we && wa == 5'd19 ) begin + ram_ff19 <= di_d; + end +end +reg [160:0] dout; +always @(*) begin + case( ra ) + 5'd0: dout = ram_ff0; + 5'd1: dout = ram_ff1; + 5'd2: dout = ram_ff2; + 5'd3: dout = ram_ff3; + 5'd4: dout = ram_ff4; + 5'd5: dout = ram_ff5; + 5'd6: dout = ram_ff6; + 5'd7: dout = ram_ff7; + 5'd8: dout = ram_ff8; + 5'd9: dout = ram_ff9; + 5'd10: dout = ram_ff10; + 5'd11: dout = ram_ff11; + 5'd12: dout = ram_ff12; + 5'd13: dout = ram_ff13; + 5'd14: dout = ram_ff14; + 5'd15: dout = ram_ff15; + 5'd16: dout = ram_ff16; + 5'd17: dout = ram_ff17; + 5'd18: dout = ram_ff18; + 5'd19: dout = ram_ff19; + 5'd20: dout = di_d; +//VCS coverage off + default: dout = {161{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [4:0] Wa0; +input we0; +input [160:0] Di0; +input [4:0] Ra0; +output [160:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 161'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [160:0] mem[19:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [160:0] Q0 = mem[0]; +wire [160:0] Q1 = mem[1]; +wire [160:0] Q2 = mem[2]; +wire [160:0] Q3 = mem[3]; +wire [160:0] Q4 = mem[4]; +wire [160:0] Q5 = mem[5]; +wire [160:0] Q6 = mem[6]; +wire [160:0] Q7 = mem[7]; +wire [160:0] Q8 = mem[8]; +wire [160:0] Q9 = mem[9]; +wire [160:0] Q10 = mem[10]; +wire [160:0] Q11 = mem[11]; +wire [160:0] Q12 = mem[12]; +wire [160:0] Q13 = mem[13]; +wire [160:0] Q14 = mem[14]; +wire [160:0] Q15 = mem[15]; +wire [160:0] Q16 = mem[16]; +wire [160:0] Q17 = mem[17]; +wire [160:0] Q18 = mem[18]; +wire [160:0] Q19 = mem[19]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161] } +endmodule // vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +//vmw: Memory vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +//vmw: Address-size 5 +//vmw: Data-size 161 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[160:0] data0[160:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[160:0] data1[160:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v.vcp new file mode 100644 index 0000000..2847591 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v.vcp @@ -0,0 +1,654 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_cq.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ld2st_wr_prdy + , ld2st_wr_idle + , ld2st_wr_pvld + , ld2st_wr_pd + , ld2st_rd_prdy + , ld2st_rd_pvld + , ld2st_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ld2st_wr_prdy; +output ld2st_wr_idle; +input ld2st_wr_pvld; +input [160:0] ld2st_wr_pd; +input ld2st_rd_prdy; +output ld2st_rd_pvld; +output [160:0] ld2st_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ld2st_wr_pvld_in; // registered ld2st_wr_pvld +reg wr_busy_in; // inputs being held this cycle? +assign ld2st_wr_prdy = !wr_busy_in; +wire ld2st_wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant ld2st_wr_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = ld2st_wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (ld2st_wr_pvld_in && ld2st_wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (ld2st_wr_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_wr_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + ld2st_wr_pvld_in <= ld2st_wr_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + ld2st_wr_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg ld2st_wr_busy_int; // copy for internal use +assign wr_reserving = ld2st_wr_pvld_in && !ld2st_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [4:0] ld2st_wr_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? ld2st_wr_count : (ld2st_wr_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (ld2st_wr_count + 1'd1) : ld2st_wr_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_20 = ( wr_count_next_no_wr_popping == 5'd20 ); +wire wr_count_next_is_20 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_20; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign ld2st_wr_busy_next = wr_count_next_is_20 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check ld2st_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = ld2st_wr_pvld_in && ld2st_wr_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_wr_busy_int <= 1'b0; + ld2st_wr_count <= 5'd0; + end else begin + ld2st_wr_busy_int <= ld2st_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ld2st_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ld2st_wr_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ld2st_wr_pvld_in +// +// RAM +// +reg [4:0] ld2st_wr_adr; // current write address +// spyglass disable_block W484 +// next ld2st_wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = (ld2st_wr_adr == 5'd19) ? 5'd0 : (ld2st_wr_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + ld2st_wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [4:0] ld2st_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ld2st_wr_count > 5'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && ld2st_wr_pvld; +wire [160:0] ld2st_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ld2st_wr_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( ld2st_wr_adr ) + , .ra ( (ld2st_wr_count == 0) ? 5'd20 : ld2st_rd_adr ) + , .dout ( ld2st_rd_pd_p ) + ); +wire [4:0] rd_adr_next_popping = (ld2st_rd_adr == 5'd19) ? 5'd0 : (ld2st_rd_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + ld2st_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ld2st_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ld2st_rd_pvld_p; // data out of fifo is valid +reg ld2st_rd_pvld_int; // internal copy of ld2st_rd_pvld +assign ld2st_rd_pvld = ld2st_rd_pvld_int; +assign rd_popping = ld2st_rd_pvld_p && !(ld2st_rd_pvld_int && !ld2st_rd_prdy); +reg [4:0] ld2st_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? ld2st_rd_count_p : + (ld2st_rd_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ld2st_rd_count_p + 1'd1) : + ld2st_rd_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ld2st_rd_pvld_p = ld2st_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_rd_count_p <= 5'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ld2st_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ld2st_rd_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [160:0] ld2st_rd_pd; // output data register +wire rd_req_next = (ld2st_rd_pvld_p || (ld2st_rd_pvld_int && !ld2st_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ld2st_rd_pvld_int <= 1'b0; + end else begin + ld2st_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ld2st_rd_pd <= ld2st_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ld2st_rd_pd <= {161{`x_or_0}}; + end +//synopsys translate_on +end +// +// Read-side Idle Calculation +// +wire rd_idle = !ld2st_rd_pvld_int && !rd_pushing && ld2st_rd_count_p == 0; +// +// Write-Side Idle Calculation +// +wire ld2st_wr_idle_d0 = !ld2st_wr_pvld_in && rd_idle && !wr_pushing && ld2st_wr_count == 0; +wire ld2st_wr_idle = ld2st_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ld2st_wr_pvld_in && !ld2st_wr_busy_int) || (ld2st_wr_busy_int != ld2st_wr_busy_next)) || (rd_pushing || rd_popping || (ld2st_rd_pvld_int && ld2st_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_cq_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd20 : wr_limit_reg} ) + , .curr ( {27'd0, ld2st_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_BDMA_cq +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [160:0] di; +input iwe; +input we; +input [4:0] wa; +input [4:0] ra; +output [160:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [160:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [160:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [4:0] Wa0_vmw; +reg we0_vmw; +reg [160:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout_p ) + ); +assign dout = (ra == 20) ? di_d : dout_p; +`else +reg [160:0] ram_ff0; +reg [160:0] ram_ff1; +reg [160:0] ram_ff2; +reg [160:0] ram_ff3; +reg [160:0] ram_ff4; +reg [160:0] ram_ff5; +reg [160:0] ram_ff6; +reg [160:0] ram_ff7; +reg [160:0] ram_ff8; +reg [160:0] ram_ff9; +reg [160:0] ram_ff10; +reg [160:0] ram_ff11; +reg [160:0] ram_ff12; +reg [160:0] ram_ff13; +reg [160:0] ram_ff14; +reg [160:0] ram_ff15; +reg [160:0] ram_ff16; +reg [160:0] ram_ff17; +reg [160:0] ram_ff18; +reg [160:0] ram_ff19; +always @( posedge clk_mgated ) begin + if ( we && wa == 5'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 5'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 5'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 5'd3 ) begin + ram_ff3 <= di_d; + end + if ( we && wa == 5'd4 ) begin + ram_ff4 <= di_d; + end + if ( we && wa == 5'd5 ) begin + ram_ff5 <= di_d; + end + if ( we && wa == 5'd6 ) begin + ram_ff6 <= di_d; + end + if ( we && wa == 5'd7 ) begin + ram_ff7 <= di_d; + end + if ( we && wa == 5'd8 ) begin + ram_ff8 <= di_d; + end + if ( we && wa == 5'd9 ) begin + ram_ff9 <= di_d; + end + if ( we && wa == 5'd10 ) begin + ram_ff10 <= di_d; + end + if ( we && wa == 5'd11 ) begin + ram_ff11 <= di_d; + end + if ( we && wa == 5'd12 ) begin + ram_ff12 <= di_d; + end + if ( we && wa == 5'd13 ) begin + ram_ff13 <= di_d; + end + if ( we && wa == 5'd14 ) begin + ram_ff14 <= di_d; + end + if ( we && wa == 5'd15 ) begin + ram_ff15 <= di_d; + end + if ( we && wa == 5'd16 ) begin + ram_ff16 <= di_d; + end + if ( we && wa == 5'd17 ) begin + ram_ff17 <= di_d; + end + if ( we && wa == 5'd18 ) begin + ram_ff18 <= di_d; + end + if ( we && wa == 5'd19 ) begin + ram_ff19 <= di_d; + end +end +reg [160:0] dout; +always @(*) begin + case( ra ) + 5'd0: dout = ram_ff0; + 5'd1: dout = ram_ff1; + 5'd2: dout = ram_ff2; + 5'd3: dout = ram_ff3; + 5'd4: dout = ram_ff4; + 5'd5: dout = ram_ff5; + 5'd6: dout = ram_ff6; + 5'd7: dout = ram_ff7; + 5'd8: dout = ram_ff8; + 5'd9: dout = ram_ff9; + 5'd10: dout = ram_ff10; + 5'd11: dout = ram_ff11; + 5'd12: dout = ram_ff12; + 5'd13: dout = ram_ff13; + 5'd14: dout = ram_ff14; + 5'd15: dout = ram_ff15; + 5'd16: dout = ram_ff16; + 5'd17: dout = ram_ff17; + 5'd18: dout = ram_ff18; + 5'd19: dout = ram_ff19; + 5'd20: dout = di_d; +//VCS coverage off + default: dout = {161{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [4:0] Wa0; +input we0; +input [160:0] Di0; +input [4:0] Ra0; +output [160:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 161'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [160:0] mem[19:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [160:0] Q0 = mem[0]; +wire [160:0] Q1 = mem[1]; +wire [160:0] Q2 = mem[2]; +wire [160:0] Q3 = mem[3]; +wire [160:0] Q4 = mem[4]; +wire [160:0] Q5 = mem[5]; +wire [160:0] Q6 = mem[6]; +wire [160:0] Q7 = mem[7]; +wire [160:0] Q8 = mem[8]; +wire [160:0] Q9 = mem[9]; +wire [160:0] Q10 = mem[10]; +wire [160:0] Q11 = mem[11]; +wire [160:0] Q12 = mem[12]; +wire [160:0] Q13 = mem[13]; +wire [160:0] Q14 = mem[14]; +wire [160:0] Q15 = mem[15]; +wire [160:0] Q16 = mem[16]; +wire [160:0] Q17 = mem[17]; +wire [160:0] Q18 = mem[18]; +wire [160:0] Q19 = mem[19]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161] } +endmodule // vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +//vmw: Memory vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +//vmw: Address-size 5 +//vmw: Data-size 161 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[160:0] data0[160:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[160:0] data1[160:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_BDMA_cq_flopram_rwsa_20x161 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v new file mode 100644 index 0000000..bb1c8d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v @@ -0,0 +1,1297 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_csb.v +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_csb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2bdma_req_pd //|< i + ,csb2bdma_req_pvld //|< i + ,csb2ld_rdy //|< i + ,dma_write_stall_count //|< i + ,ld2csb_grp0_dma_stall_inc //|< i + ,ld2csb_grp1_dma_stall_inc //|< i + ,ld2csb_idle //|< i + ,pwrbus_ram_pd //|< i + ,st2csb_grp0_done //|< i + ,st2csb_grp1_done //|< i + ,st2csb_idle //|< i + ,bdma2csb_resp_pd //|> o + ,bdma2csb_resp_valid //|> o + ,bdma2glb_done_intr_pd //|> o + ,csb2bdma_req_prdy //|> o + ,csb2gate_slcg_en //|> o + ,csb2ld_vld //|> o + ,dma_write_stall_count_cen //|> o + ,reg2dp_cmd_dst_ram_type //|> o + ,reg2dp_cmd_interrupt //|> o + ,reg2dp_cmd_interrupt_ptr //|> o + ,reg2dp_cmd_src_ram_type //|> o + ,reg2dp_dst_addr_high_v8 //|> o + ,reg2dp_dst_addr_low_v32 //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_surf_stride //|> o + ,reg2dp_line_repeat_number //|> o + ,reg2dp_line_size //|> o + ,reg2dp_src_addr_high_v8 //|> o + ,reg2dp_src_addr_low_v32 //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_surf_stride //|> o + ,reg2dp_surf_repeat_number //|> o + ); +// +// NV_NVDLA_BDMA_csb_ports.v +// +input nvdla_core_clk; /* csb2bdma_req, bdma2csb_resp, bdma2glb_done_intr */ +input nvdla_core_rstn; /* csb2bdma_req, bdma2csb_resp, bdma2glb_done_intr */ +input csb2bdma_req_pvld; /* data valid */ +output csb2bdma_req_prdy; /* data return handshake */ +input [62:0] csb2bdma_req_pd; +output bdma2csb_resp_valid; /* data valid */ +output [33:0] bdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] bdma2glb_done_intr_pd; +input [31:0] pwrbus_ram_pd; +//&Ports /^obs_bus/; +input st2csb_grp0_done; +input st2csb_grp1_done; +input st2csb_idle; +output reg2dp_cmd_dst_ram_type; +output reg2dp_cmd_interrupt; +output reg2dp_cmd_interrupt_ptr; +output reg2dp_cmd_src_ram_type; +output [31:0] reg2dp_dst_addr_high_v8; +output [26:0] reg2dp_dst_addr_low_v32; +output [26:0] reg2dp_dst_line_stride; +output [26:0] reg2dp_dst_surf_stride; +output [23:0] reg2dp_line_repeat_number; +output [12:0] reg2dp_line_size; +output [31:0] reg2dp_src_addr_high_v8; +output [26:0] reg2dp_src_addr_low_v32; +output [26:0] reg2dp_src_line_stride; +output [26:0] reg2dp_src_surf_stride; +output [23:0] reg2dp_surf_repeat_number; +input csb2ld_rdy; +input ld2csb_grp0_dma_stall_inc; +input ld2csb_grp1_dma_stall_inc; +input ld2csb_idle; +output csb2ld_vld; +output csb2gate_slcg_en; +input [31:0] dma_write_stall_count; +output dma_write_stall_count_cen; +reg [33:0] bdma2csb_resp_pd; +reg bdma2csb_resp_valid; +reg [1:0] bdma2glb_done_intr_pd; +reg csb_processing_d; +reg [4:0] gather_count; +reg gather_ptr; +reg gather_vld; +reg grp0_cmd_launch_trigger; +reg grp0_read_stall_cnt_adv; +reg [31:0] grp0_read_stall_cnt_cnt_cur; +reg [33:0] grp0_read_stall_cnt_cnt_dec; +reg [33:0] grp0_read_stall_cnt_cnt_ext; +reg [33:0] grp0_read_stall_cnt_cnt_inc; +reg [33:0] grp0_read_stall_cnt_cnt_mod; +reg [33:0] grp0_read_stall_cnt_cnt_new; +reg [33:0] grp0_read_stall_cnt_cnt_nxt; +reg [31:0] grp0_read_stall_count; +reg grp1_cmd_launch_trigger; +reg grp1_read_stall_cnt_adv; +reg [31:0] grp1_read_stall_cnt_cnt_cur; +reg [33:0] grp1_read_stall_cnt_cnt_dec; +reg [33:0] grp1_read_stall_cnt_cnt_ext; +reg [33:0] grp1_read_stall_cnt_cnt_inc; +reg [33:0] grp1_read_stall_cnt_cnt_mod; +reg [33:0] grp1_read_stall_cnt_cnt_new; +reg [33:0] grp1_read_stall_cnt_cnt_nxt; +reg [31:0] grp1_read_stall_count; +reg [4:0] launch_count; +reg launch_ptr; +reg op_en_trigger; +reg [62:0] req_pd; +reg req_vld; +reg slcg_en; +reg status_grp0_busy; +reg [31:0] status_grp0_read_stall_count; +reg [31:0] status_grp0_write_stall_count; +reg status_grp1_busy; +reg [31:0] status_grp1_read_stall_count; +reg [31:0] status_grp1_write_stall_count; +wire cmd_launch_rdy; +wire cmd_launch_vld; +wire [288:0] csb_fifo_rd_pd; +wire csb_fifo_rd_prdy; +wire csb_fifo_rd_pvld; +wire [4:0] csb_fifo_wr_count; +wire csb_fifo_wr_idle; +wire [288:0] csb_fifo_wr_pd; +wire csb_fifo_wr_prdy; +wire csb_fifo_wr_pvld; +wire csb_idle; +wire csb_processing; +wire dma_read_stall_count_cen; +wire gather_rdy; +wire gather_to_launch; +wire grp0_cmd_launch; +wire grp0_read_stall_count_dec; +wire grp1_cmd_launch; +wire grp1_read_stall_count_dec; +wire is_last_cmd; +wire is_last_cmd_rdy; +wire launch_rdy; +wire launch_vld; +wire load_idle; +wire mon_csb_fifo_rd_pvld; +wire mon_csb_fifo_wr_prdy; +wire nvdla_bdma_cfg_cmd_0_dst_ram_type; +wire nvdla_bdma_cfg_cmd_0_src_ram_type; +wire [31:0] nvdla_bdma_cfg_dst_addr_high_0_v8; +wire [26:0] nvdla_bdma_cfg_dst_addr_low_0_v32; +wire [26:0] nvdla_bdma_cfg_dst_line_0_stride; +wire [26:0] nvdla_bdma_cfg_dst_surf_0_stride; +wire nvdla_bdma_cfg_launch0_0_grp0_launch; +wire nvdla_bdma_cfg_launch0_0_grp0_launch_trigger; +wire nvdla_bdma_cfg_launch1_0_grp1_launch; +wire nvdla_bdma_cfg_launch1_0_grp1_launch_trigger; +wire [12:0] nvdla_bdma_cfg_line_0_size; +wire [23:0] nvdla_bdma_cfg_line_repeat_0_number; +wire nvdla_bdma_cfg_op_0_en; +wire nvdla_bdma_cfg_op_0_en_trigger; +wire [31:0] nvdla_bdma_cfg_src_addr_high_0_v8; +wire [26:0] nvdla_bdma_cfg_src_addr_low_0_v32; +wire [26:0] nvdla_bdma_cfg_src_line_0_stride; +wire [26:0] nvdla_bdma_cfg_src_surf_0_stride; +wire nvdla_bdma_cfg_status_0_stall_count_en; +wire [23:0] nvdla_bdma_cfg_surf_repeat_0_number; +wire [7:0] nvdla_bdma_status_0_free_slot; +wire nvdla_bdma_status_0_grp0_busy; +wire nvdla_bdma_status_0_grp1_busy; +wire nvdla_bdma_status_0_idle; +wire [31:0] nvdla_bdma_status_grp0_read_stall_0_count; +wire [31:0] nvdla_bdma_status_grp0_write_stall_0_count; +wire [31:0] nvdla_bdma_status_grp1_read_stall_0_count; +wire [31:0] nvdla_bdma_status_grp1_write_stall_0_count; +wire [11:0] reg_offset; +wire [31:0] reg_rd_data; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level_NC; +wire req_nposted; +wire req_srcpriv_NC; +wire [31:0] req_wdat; +wire [3:0] req_wrbe_NC; +wire req_write; +wire [33:0] rsp_pd; +wire rsp_rd_error; +wire [32:0] rsp_rd_pd; +wire [31:0] rsp_rd_rdat; +wire rsp_rd_vld; +wire rsp_vld; +wire rsp_wr_error; +wire [32:0] rsp_wr_pd; +wire [31:0] rsp_wr_rdat; +wire rsp_wr_vld; +wire status_grp0_clr; +wire status_grp0_set; +wire status_grp1_clr; +wire status_grp1_set; +wire store_idle; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//============== +// CSB +//============== +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// &Viva width_learning_on; +// REQ INTERFACE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_vld <= 1'b0; + end else begin + req_vld <= csb2bdma_req_pvld; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2bdma_req_pvld) == 1'b1) begin + req_pd <= csb2bdma_req_pd; +// VCS coverage off + end else if ((csb2bdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2bdma_req_prdy = 1'b1; +// ======== +// REQUEST +// ======== +// flow=pvld_prdy +assign req_level_NC = req_pd[62:61]; +assign req_nposted = req_pd[55:55]; +assign req_addr = req_pd[21:0]; +assign req_wrbe_NC = req_pd[60:57]; +assign req_srcpriv_NC = req_pd[56:56]; +assign req_write = req_pd[54:54]; +assign req_wdat = req_pd[53:22]; +// ======== +// RESPONSE +// ======== +// flow=valid +// packet=dla_xx2csb_rd_erpt +assign rsp_rd_pd[32:32] = rsp_rd_error; +assign rsp_rd_pd[31:0] = rsp_rd_rdat; +// packet=dla_xx2csb_wr_erpt +assign rsp_wr_pd[32:32] = rsp_wr_error; +assign rsp_wr_pd[31:0] = rsp_wr_rdat; +assign rsp_rd_vld = req_vld & ~req_write; +assign rsp_rd_rdat = {32{rsp_rd_vld}} & reg_rd_data; +assign rsp_rd_error = 1'b0; +assign rsp_wr_vld = req_vld & req_write & req_nposted; +assign rsp_wr_rdat = {32{1'b0}}; +assign rsp_wr_error = 1'b0; +// ======== +// REQUEST +// ======== +assign rsp_vld = rsp_rd_vld | rsp_wr_vld; +assign rsp_pd[33:33] = ({1{rsp_rd_vld}} & {1'h0}) + | ({1{rsp_wr_vld}} & {1'h1}); +assign rsp_pd[32:0] = ({33{rsp_rd_vld}} & rsp_rd_pd) + | ({33{rsp_wr_vld}} & rsp_wr_pd); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2csb_resp_valid <= 1'b0; + end else begin + bdma2csb_resp_valid <= rsp_vld; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_vld) == 1'b1) begin + bdma2csb_resp_pd <= rsp_pd; +// VCS coverage off + end else if ((rsp_vld) == 1'b0) begin + end else begin + bdma2csb_resp_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign reg_offset = {req_addr[9:0],{2{1'b0}}}; +assign reg_wr_en = req_vld & req_write; +assign reg_wr_data = req_wdat; +NV_NVDLA_BDMA_reg u_NV_NVDLA_BDMA_reg ( + .reg_rd_data (reg_rd_data[31:0]) //|> w + ,.reg_offset (reg_offset[11:0]) //|< w + ,.reg_wr_data (reg_wr_data[31:0]) //|< w + ,.reg_wr_en (reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.nvdla_bdma_cfg_cmd_0_dst_ram_type (nvdla_bdma_cfg_cmd_0_dst_ram_type) //|> w + ,.nvdla_bdma_cfg_cmd_0_src_ram_type (nvdla_bdma_cfg_cmd_0_src_ram_type) //|> w + ,.nvdla_bdma_cfg_dst_addr_high_0_v8 (nvdla_bdma_cfg_dst_addr_high_0_v8[31:0]) //|> w + ,.nvdla_bdma_cfg_dst_addr_low_0_v32 (nvdla_bdma_cfg_dst_addr_low_0_v32[26:0]) //|> w + ,.nvdla_bdma_cfg_dst_line_0_stride (nvdla_bdma_cfg_dst_line_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_dst_surf_0_stride (nvdla_bdma_cfg_dst_surf_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_launch0_0_grp0_launch (nvdla_bdma_cfg_launch0_0_grp0_launch) //|> w + ,.nvdla_bdma_cfg_launch0_0_grp0_launch_trigger (nvdla_bdma_cfg_launch0_0_grp0_launch_trigger) //|> w + ,.nvdla_bdma_cfg_launch1_0_grp1_launch (nvdla_bdma_cfg_launch1_0_grp1_launch) //|> w + ,.nvdla_bdma_cfg_launch1_0_grp1_launch_trigger (nvdla_bdma_cfg_launch1_0_grp1_launch_trigger) //|> w + ,.nvdla_bdma_cfg_line_0_size (nvdla_bdma_cfg_line_0_size[12:0]) //|> w + ,.nvdla_bdma_cfg_line_repeat_0_number (nvdla_bdma_cfg_line_repeat_0_number[23:0]) //|> w + ,.nvdla_bdma_cfg_op_0_en (nvdla_bdma_cfg_op_0_en) //|> w + ,.nvdla_bdma_cfg_op_0_en_trigger (nvdla_bdma_cfg_op_0_en_trigger) //|> w + ,.nvdla_bdma_cfg_src_addr_high_0_v8 (nvdla_bdma_cfg_src_addr_high_0_v8[31:0]) //|> w + ,.nvdla_bdma_cfg_src_addr_low_0_v32 (nvdla_bdma_cfg_src_addr_low_0_v32[26:0]) //|> w + ,.nvdla_bdma_cfg_src_line_0_stride (nvdla_bdma_cfg_src_line_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_src_surf_0_stride (nvdla_bdma_cfg_src_surf_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_status_0_stall_count_en (nvdla_bdma_cfg_status_0_stall_count_en) //|> w + ,.nvdla_bdma_cfg_surf_repeat_0_number (nvdla_bdma_cfg_surf_repeat_0_number[23:0]) //|> w + ,.nvdla_bdma_status_0_free_slot (nvdla_bdma_status_0_free_slot[7:0]) //|< w + ,.nvdla_bdma_status_0_grp0_busy (nvdla_bdma_status_0_grp0_busy) //|< w + ,.nvdla_bdma_status_0_grp1_busy (nvdla_bdma_status_0_grp1_busy) //|< w + ,.nvdla_bdma_status_0_idle (nvdla_bdma_status_0_idle) //|< w + ,.nvdla_bdma_status_grp0_read_stall_0_count (nvdla_bdma_status_grp0_read_stall_0_count[31:0]) //|< w + ,.nvdla_bdma_status_grp0_write_stall_0_count (nvdla_bdma_status_grp0_write_stall_0_count[31:0]) //|< w + ,.nvdla_bdma_status_grp1_read_stall_0_count (nvdla_bdma_status_grp1_read_stall_0_count[31:0]) //|< w + ,.nvdla_bdma_status_grp1_write_stall_0_count (nvdla_bdma_status_grp1_write_stall_0_count[31:0]) //|< w + ); +assign csb_fifo_wr_pd = {nvdla_bdma_cfg_src_addr_low_0_v32, +nvdla_bdma_cfg_src_addr_high_0_v8, +nvdla_bdma_cfg_dst_addr_low_0_v32, +nvdla_bdma_cfg_dst_addr_high_0_v8, +nvdla_bdma_cfg_line_0_size, +nvdla_bdma_cfg_cmd_0_src_ram_type, +nvdla_bdma_cfg_cmd_0_dst_ram_type, +nvdla_bdma_cfg_line_repeat_0_number, +nvdla_bdma_cfg_src_line_0_stride, +nvdla_bdma_cfg_dst_line_0_stride, +nvdla_bdma_cfg_surf_repeat_0_number, +nvdla_bdma_cfg_src_surf_0_stride, +nvdla_bdma_cfg_dst_surf_0_stride}; +NV_NVDLA_BDMA_LOAD_csb_fifo csb_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb_fifo_wr_count (csb_fifo_wr_count[4:0]) //|> w + ,.csb_fifo_wr_prdy (csb_fifo_wr_prdy) //|> w + ,.csb_fifo_wr_idle (csb_fifo_wr_idle) //|> w + ,.csb_fifo_wr_pvld (csb_fifo_wr_pvld) //|< w + ,.csb_fifo_wr_pd (csb_fifo_wr_pd[288:0]) //|< w + ,.csb_fifo_rd_prdy (csb_fifo_rd_prdy) //|< w + ,.csb_fifo_rd_pvld (csb_fifo_rd_pvld) //|> w + ,.csb_fifo_rd_pd (csb_fifo_rd_pd[288:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign {reg2dp_src_addr_low_v32, +reg2dp_src_addr_high_v8, +reg2dp_dst_addr_low_v32, +reg2dp_dst_addr_high_v8, +reg2dp_line_size, +reg2dp_cmd_src_ram_type, +reg2dp_cmd_dst_ram_type, +reg2dp_line_repeat_number, +reg2dp_src_line_stride, +reg2dp_dst_line_stride, +reg2dp_surf_repeat_number, +reg2dp_src_surf_stride, +reg2dp_dst_surf_stride} = csb_fifo_rd_pd; +// Status Gen +assign mon_csb_fifo_wr_prdy = csb_fifo_wr_prdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"memory copy command is dropped") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, csb_fifo_wr_pvld && !mon_csb_fifo_wr_prdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign nvdla_bdma_status_0_free_slot[7:0] = 20 - csb_fifo_wr_count; +//================== +// cmd -> gather_count --(when intr) -> launch_count -> pop from csb_fifo +//================== +// CSB CMD FIFO +// Memory copy command consists of content from several BDMA registers, and when BDMA_CFG_CMD register is written +// a launch of command is triggered, and this command is pushed into CSB cmd FIFO, and wait there for next pop and execution +// nvdla_bdma_cfg_op_0_en_trigger is one cycle ahead of nvdla_bdma_cfg_op_0_en in arreggen, so need flop it before using +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_trigger <= 1'b0; + end else begin + op_en_trigger <= nvdla_bdma_cfg_op_0_en_trigger; + end +end +assign csb_fifo_wr_pvld = op_en_trigger & nvdla_bdma_cfg_op_0_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp0_cmd_launch_trigger <= 1'b0; + end else begin + grp0_cmd_launch_trigger <= nvdla_bdma_cfg_launch0_0_grp0_launch_trigger; + end +end +assign grp0_cmd_launch = grp0_cmd_launch_trigger & nvdla_bdma_cfg_launch0_0_grp0_launch; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp1_cmd_launch_trigger <= 1'b0; + end else begin + grp1_cmd_launch_trigger <= nvdla_bdma_cfg_launch1_0_grp1_launch_trigger; + end +end +assign grp1_cmd_launch = grp1_cmd_launch_trigger & nvdla_bdma_cfg_launch1_0_grp1_launch; +assign cmd_launch_vld = grp0_cmd_launch | grp1_cmd_launch; +// command stalling: commands will only be popped from csb_fifo when the the last one with interrupt needed +//================== +assign gather_to_launch = gather_vld & gather_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gather_count <= {5{1'b0}}; + end else begin + if (gather_to_launch) begin + if (csb_fifo_wr_pvld) begin + gather_count <= 1; + end else begin + gather_count <= 0; + end + end else begin + if (csb_fifo_wr_pvld) begin + gather_count <= gather_count + 1; + end + end + end +end +assign cmd_launch_rdy = gather_rdy || !gather_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gather_vld <= 1'b0; + end else begin + if ((cmd_launch_rdy) == 1'b1) begin + gather_vld <= cmd_launch_vld; +// VCS coverage off + end else if ((cmd_launch_rdy) == 1'b0) begin + end else begin + gather_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd_launch_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gather_ptr <= 1'b0; + end else begin + if (grp0_cmd_launch) begin + gather_ptr <= 1'b0; + end else if (grp1_cmd_launch) begin + gather_ptr <= 1'b1; + end + end +end +assign gather_rdy = (!launch_vld) || is_last_cmd_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gather must be ready when there is a launch command") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, cmd_launch_vld & !cmd_launch_rdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property bdma_load__two_groups_are_launched_continously__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + launch_vld & gather_vld; + endproperty +// Cover 0 : "launch_vld & gather_vld" + FUNCPOINT_bdma_load__two_groups_are_launched_continously__0_COV : cover property (bdma_load__two_groups_are_launched_continously__0_cov); + `endif +`endif +//VCS coverage on +assign mon_csb_fifo_rd_pvld = csb_fifo_rd_pvld; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when launch is valid, csb_fifo must have valid data") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, launch_vld & !mon_csb_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign launch_rdy = csb2ld_rdy; +assign csb_fifo_rd_prdy = csb2ld_rdy; +assign launch_vld = launch_count!=0; +assign csb2ld_vld = launch_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + launch_count <= {5{1'b0}}; + launch_ptr <= 1'b0; + end else begin + if (launch_vld) begin + if (launch_rdy) begin + if (is_last_cmd) begin + if (gather_vld) begin + launch_count <= gather_count; + launch_ptr <= gather_ptr; + end else begin + launch_count <= launch_count - 1; + end + end else begin + launch_count <= launch_count - 1; + end + end + end else begin + if (gather_vld) begin + launch_count <= gather_count; + launch_ptr <= gather_ptr; + end + end + end +end +assign is_last_cmd = (launch_count==1); +assign is_last_cmd_rdy = launch_rdy & is_last_cmd; +assign reg2dp_cmd_interrupt = is_last_cmd_rdy; +assign reg2dp_cmd_interrupt_ptr = launch_ptr; +//================== +// STATUS SET/CLR +//================== +assign status_grp0_set = grp0_cmd_launch; +assign status_grp0_clr = st2csb_grp0_done; +assign status_grp1_set = grp1_cmd_launch; +assign status_grp1_clr = st2csb_grp1_done; +//================== +// STATUS IDLE +//================== +assign store_idle = st2csb_idle; +assign load_idle = ld2csb_idle; +assign csb_idle = csb_fifo_wr_idle; +assign nvdla_bdma_status_0_idle = store_idle & load_idle & csb_idle; +//================== +// STATUS BUSY +//================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp0_busy <= 1'b0; + end else begin + if (status_grp0_set) begin + status_grp0_busy <= 1'b1; + end else if (status_grp0_clr) begin + status_grp0_busy <= 1'b0; + end + end +end +assign nvdla_bdma_status_0_grp0_busy = status_grp0_busy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp1_busy <= 1'b0; + end else begin + if (status_grp1_set) begin + status_grp1_busy <= 1'b1; + end else if (status_grp1_clr) begin + status_grp1_busy <= 1'b0; + end + end +end +assign nvdla_bdma_status_0_grp1_busy = status_grp1_busy; +//================== +// STATUS STATISTIC +//================== +assign dma_write_stall_count_cen = nvdla_bdma_cfg_status_0_stall_count_en; +assign dma_read_stall_count_cen = nvdla_bdma_cfg_status_0_stall_count_en; + assign grp0_read_stall_count_dec = 1'b0; +// grp0_read_stall_cnt adv logic + always @( + ld2csb_grp0_dma_stall_inc + or grp0_read_stall_count_dec + ) begin + grp0_read_stall_cnt_adv = ld2csb_grp0_dma_stall_inc ^ grp0_read_stall_count_dec; + end +// grp0_read_stall_cnt cnt logic + always @( + grp0_read_stall_cnt_cnt_cur + or ld2csb_grp0_dma_stall_inc + or grp0_read_stall_count_dec + or grp0_read_stall_cnt_adv + or status_grp0_clr + ) begin +// VCS sop_coverage_off start + grp0_read_stall_cnt_cnt_ext[33:0] = {1'b0, 1'b0, grp0_read_stall_cnt_cnt_cur}; + grp0_read_stall_cnt_cnt_inc[33:0] = grp0_read_stall_cnt_cnt_cur + 1'b1; // spyglass disable W164b + grp0_read_stall_cnt_cnt_dec[33:0] = grp0_read_stall_cnt_cnt_cur - 1'b1; // spyglass disable W164b + grp0_read_stall_cnt_cnt_mod[33:0] = (ld2csb_grp0_dma_stall_inc && !grp0_read_stall_count_dec)? grp0_read_stall_cnt_cnt_inc : (!ld2csb_grp0_dma_stall_inc && grp0_read_stall_count_dec)? grp0_read_stall_cnt_cnt_dec : grp0_read_stall_cnt_cnt_ext; + grp0_read_stall_cnt_cnt_new[33:0] = (grp0_read_stall_cnt_adv)? grp0_read_stall_cnt_cnt_mod[33:0] : grp0_read_stall_cnt_cnt_ext[33:0]; + grp0_read_stall_cnt_cnt_nxt[33:0] = (status_grp0_clr)? 34'd0 : grp0_read_stall_cnt_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// grp0_read_stall_cnt flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp0_read_stall_cnt_cnt_cur[31:0] <= 0; + end else begin + if (dma_read_stall_count_cen) begin + grp0_read_stall_cnt_cnt_cur[31:0] <= grp0_read_stall_cnt_cnt_nxt[31:0]; + end + end + end +// grp0_read_stall_cnt output logic + always @( + grp0_read_stall_cnt_cnt_cur + ) begin + grp0_read_stall_count[31:0] = grp0_read_stall_cnt_cnt_cur[31:0]; + end + assign grp1_read_stall_count_dec = 1'b0; +// grp1_read_stall_cnt adv logic + always @( + ld2csb_grp1_dma_stall_inc + or grp1_read_stall_count_dec + ) begin + grp1_read_stall_cnt_adv = ld2csb_grp1_dma_stall_inc ^ grp1_read_stall_count_dec; + end +// grp1_read_stall_cnt cnt logic + always @( + grp1_read_stall_cnt_cnt_cur + or ld2csb_grp1_dma_stall_inc + or grp1_read_stall_count_dec + or grp1_read_stall_cnt_adv + or status_grp1_clr + ) begin +// VCS sop_coverage_off start + grp1_read_stall_cnt_cnt_ext[33:0] = {1'b0, 1'b0, grp1_read_stall_cnt_cnt_cur}; + grp1_read_stall_cnt_cnt_inc[33:0] = grp1_read_stall_cnt_cnt_cur + 1'b1; // spyglass disable W164b + grp1_read_stall_cnt_cnt_dec[33:0] = grp1_read_stall_cnt_cnt_cur - 1'b1; // spyglass disable W164b + grp1_read_stall_cnt_cnt_mod[33:0] = (ld2csb_grp1_dma_stall_inc && !grp1_read_stall_count_dec)? grp1_read_stall_cnt_cnt_inc : (!ld2csb_grp1_dma_stall_inc && grp1_read_stall_count_dec)? grp1_read_stall_cnt_cnt_dec : grp1_read_stall_cnt_cnt_ext; + grp1_read_stall_cnt_cnt_new[33:0] = (grp1_read_stall_cnt_adv)? grp1_read_stall_cnt_cnt_mod[33:0] : grp1_read_stall_cnt_cnt_ext[33:0]; + grp1_read_stall_cnt_cnt_nxt[33:0] = (status_grp1_clr)? 34'd0 : grp1_read_stall_cnt_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// grp1_read_stall_cnt flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp1_read_stall_cnt_cnt_cur[31:0] <= 0; + end else begin + if (dma_read_stall_count_cen) begin + grp1_read_stall_cnt_cnt_cur[31:0] <= grp1_read_stall_cnt_cnt_nxt[31:0]; + end + end + end +// grp1_read_stall_cnt output logic + always @( + grp1_read_stall_cnt_cnt_cur + ) begin + grp1_read_stall_count[31:0] = grp1_read_stall_cnt_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp0_read_stall_count <= {32{1'b0}}; + end else begin + if (status_grp0_set) begin + status_grp0_read_stall_count <= 0; + end else if (status_grp0_clr) begin + status_grp0_read_stall_count <= grp0_read_stall_count; + end + end +end +assign nvdla_bdma_status_grp0_read_stall_0_count = status_grp0_read_stall_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp1_read_stall_count <= {32{1'b0}}; + end else begin + if (status_grp1_set) begin + status_grp1_read_stall_count <= 0; + end else if (status_grp1_clr) begin + status_grp1_read_stall_count <= grp1_read_stall_count; + end + end +end +assign nvdla_bdma_status_grp1_read_stall_0_count = status_grp1_read_stall_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp0_write_stall_count <= {32{1'b0}}; + end else begin + if (status_grp0_set) begin + status_grp0_write_stall_count <= 0; + end else if (status_grp0_clr) begin + status_grp0_write_stall_count <= dma_write_stall_count; + end + end +end +assign nvdla_bdma_status_grp0_write_stall_0_count = status_grp0_write_stall_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp1_write_stall_count <= {32{1'b0}}; + end else begin + if (status_grp1_set) begin + status_grp1_write_stall_count <= 0; + end else if (status_grp1_clr) begin + status_grp1_write_stall_count <= dma_write_stall_count; + end + end +end +assign nvdla_bdma_status_grp1_write_stall_0_count = status_grp1_write_stall_count; +//============== +// Interrupt to GLB +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2glb_done_intr_pd[0] <= 1'b0; + end else begin + bdma2glb_done_intr_pd[0] <= status_grp0_clr; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2glb_done_intr_pd[1] <= 1'b0; + end else begin + bdma2glb_done_intr_pd[1] <= status_grp1_clr; + end +end +//====================================== +// OBS +//assign obs_bus_bdma_csb_idle = nvdla_bdma_status_0_idle; +//assign obs_bus_bdma_csb_busy = csb_processing; +//assign obs_bus_bdma_csb_fifo_rd_pvld = csb_fifo_rd_pvld; +//assign obs_bus_bdma_csb_fifo_wr_idle = csb_fifo_wr_idle; +//assign obs_bus_bdma_csb_fifo_wr_prdy = csb_fifo_wr_prdy; +//assign obs_bus_bdma_csb_fifo_wr_pvld = csb_fifo_wr_pvld; +//assign obs_bus_bdma_csb_gather_rdy = gather_rdy; +//assign obs_bus_bdma_csb_gather_vld = gather_vld; +//assign obs_bus_bdma_csb_launch_rdy = launch_rdy; +//assign obs_bus_bdma_csb_launch_vld = launch_vld; +//assign obs_bus_bdma_csb2gate_slcg_en = slcg_en; +//====================================== +// SLCG +assign csb_processing = cmd_launch_vld | gather_vld | launch_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb_processing_d <= 1'b0; + end else begin + csb_processing_d <= csb_processing; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_en <= 1'b0; + end else begin + slcg_en <= csb_processing | csb_processing_d; + end +end +assign csb2gate_slcg_en = slcg_en; +endmodule // NV_NVDLA_BDMA_csb +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_LOAD_csb_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus csb_fifo_wr -rd_pipebus csb_fifo_rd -rd_reg -wr_idle -wr_count -d 20 -w 289 -rand_none -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_LOAD_csb_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , csb_fifo_wr_count + , csb_fifo_wr_prdy + , csb_fifo_wr_idle + , csb_fifo_wr_pvld + , csb_fifo_wr_pd + , csb_fifo_rd_prdy + , csb_fifo_rd_pvld + , csb_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output [4:0] csb_fifo_wr_count; +output csb_fifo_wr_prdy; +output csb_fifo_wr_idle; +input csb_fifo_wr_pvld; +input [288:0] csb_fifo_wr_pd; +input csb_fifo_rd_prdy; +output csb_fifo_rd_pvld; +output [288:0] csb_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg csb_fifo_wr_busy_int; // copy for internal use +assign csb_fifo_wr_prdy = !csb_fifo_wr_busy_int; +assign wr_reserving = csb_fifo_wr_pvld && !csb_fifo_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [4:0] csb_fifo_wr_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? csb_fifo_wr_count : (csb_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (csb_fifo_wr_count + 1'd1) : csb_fifo_wr_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_20 = ( wr_count_next_no_wr_popping == 5'd20 ); +wire wr_count_next_is_20 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_20; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire csb_fifo_wr_busy_next = wr_count_next_is_20 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check csb_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_wr_busy_int <= 1'b0; + csb_fifo_wr_count <= 5'd0; + end else begin + csb_fifo_wr_busy_int <= csb_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + csb_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + csb_fifo_wr_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as csb_fifo_wr_pvld +// +// RAM +// +reg [4:0] csb_fifo_wr_adr; // current write address +wire [4:0] csb_fifo_rd_adr_p; // read address to use for ram +wire [288:0] csb_fifo_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_20x289 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( csb_fifo_wr_adr ) + , .we ( wr_pushing ) + , .di ( csb_fifo_wr_pd ) + , .ra ( csb_fifo_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( csb_fifo_rd_pd_p ) + , .ore ( ore ) + ); +// next csb_fifo_wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = (csb_fifo_wr_adr == 5'd19) ? 5'd0 : (csb_fifo_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + csb_fifo_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + csb_fifo_wr_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [4:0] csb_fifo_rd_adr; // current read address +// next read address +wire [4:0] rd_adr_next = (csb_fifo_rd_adr == 5'd19) ? 5'd0 : (csb_fifo_rd_adr + 1'd1); // spyglass disable W484 +assign csb_fifo_rd_adr_p = rd_popping ? rd_adr_next : csb_fifo_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + csb_fifo_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + csb_fifo_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg csb_fifo_rd_pvld_p; // data out of fifo is valid +reg csb_fifo_rd_pvld_int; // internal copy of csb_fifo_rd_pvld +assign csb_fifo_rd_pvld = csb_fifo_rd_pvld_int; +assign rd_popping = csb_fifo_rd_pvld_p && !(csb_fifo_rd_pvld_int && !csb_fifo_rd_prdy); +reg [4:0] csb_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? csb_fifo_rd_count_p : + (csb_fifo_rd_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (csb_fifo_rd_count_p + 1'd1) : + csb_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~csb_fifo_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_rd_count_p <= 5'd0; + csb_fifo_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + csb_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + csb_fifo_rd_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + csb_fifo_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + csb_fifo_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (csb_fifo_rd_pvld_p || (csb_fifo_rd_pvld_int && !csb_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_rd_pvld_int <= 1'b0; + end else begin + csb_fifo_rd_pvld_int <= rd_req_next; + end +end +assign csb_fifo_rd_pd = csb_fifo_rd_pd_p; +assign ore = rd_popping; +// +// Read-side Idle Calculation +// +wire rd_idle = !csb_fifo_rd_pvld_int && !rd_pushing && csb_fifo_rd_count_p == 0; +// +// Write-Side Idle Calculation +// +wire csb_fifo_wr_idle_d0 = !csb_fifo_wr_pvld && rd_idle && !wr_pushing && csb_fifo_wr_count == 0; +wire csb_fifo_wr_idle = csb_fifo_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (csb_fifo_wr_pvld && !csb_fifo_wr_busy_int) || (csb_fifo_wr_busy_int != csb_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (csb_fifo_rd_pvld_int && csb_fifo_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd20 : wr_limit_reg} ) + , .curr ( {27'd0, csb_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_LOAD_csb_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_BDMA_LOAD_csb_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v.vcp new file mode 100644 index 0000000..bb1c8d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v.vcp @@ -0,0 +1,1297 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_csb.v +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_csb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2bdma_req_pd //|< i + ,csb2bdma_req_pvld //|< i + ,csb2ld_rdy //|< i + ,dma_write_stall_count //|< i + ,ld2csb_grp0_dma_stall_inc //|< i + ,ld2csb_grp1_dma_stall_inc //|< i + ,ld2csb_idle //|< i + ,pwrbus_ram_pd //|< i + ,st2csb_grp0_done //|< i + ,st2csb_grp1_done //|< i + ,st2csb_idle //|< i + ,bdma2csb_resp_pd //|> o + ,bdma2csb_resp_valid //|> o + ,bdma2glb_done_intr_pd //|> o + ,csb2bdma_req_prdy //|> o + ,csb2gate_slcg_en //|> o + ,csb2ld_vld //|> o + ,dma_write_stall_count_cen //|> o + ,reg2dp_cmd_dst_ram_type //|> o + ,reg2dp_cmd_interrupt //|> o + ,reg2dp_cmd_interrupt_ptr //|> o + ,reg2dp_cmd_src_ram_type //|> o + ,reg2dp_dst_addr_high_v8 //|> o + ,reg2dp_dst_addr_low_v32 //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_surf_stride //|> o + ,reg2dp_line_repeat_number //|> o + ,reg2dp_line_size //|> o + ,reg2dp_src_addr_high_v8 //|> o + ,reg2dp_src_addr_low_v32 //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_surf_stride //|> o + ,reg2dp_surf_repeat_number //|> o + ); +// +// NV_NVDLA_BDMA_csb_ports.v +// +input nvdla_core_clk; /* csb2bdma_req, bdma2csb_resp, bdma2glb_done_intr */ +input nvdla_core_rstn; /* csb2bdma_req, bdma2csb_resp, bdma2glb_done_intr */ +input csb2bdma_req_pvld; /* data valid */ +output csb2bdma_req_prdy; /* data return handshake */ +input [62:0] csb2bdma_req_pd; +output bdma2csb_resp_valid; /* data valid */ +output [33:0] bdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] bdma2glb_done_intr_pd; +input [31:0] pwrbus_ram_pd; +//&Ports /^obs_bus/; +input st2csb_grp0_done; +input st2csb_grp1_done; +input st2csb_idle; +output reg2dp_cmd_dst_ram_type; +output reg2dp_cmd_interrupt; +output reg2dp_cmd_interrupt_ptr; +output reg2dp_cmd_src_ram_type; +output [31:0] reg2dp_dst_addr_high_v8; +output [26:0] reg2dp_dst_addr_low_v32; +output [26:0] reg2dp_dst_line_stride; +output [26:0] reg2dp_dst_surf_stride; +output [23:0] reg2dp_line_repeat_number; +output [12:0] reg2dp_line_size; +output [31:0] reg2dp_src_addr_high_v8; +output [26:0] reg2dp_src_addr_low_v32; +output [26:0] reg2dp_src_line_stride; +output [26:0] reg2dp_src_surf_stride; +output [23:0] reg2dp_surf_repeat_number; +input csb2ld_rdy; +input ld2csb_grp0_dma_stall_inc; +input ld2csb_grp1_dma_stall_inc; +input ld2csb_idle; +output csb2ld_vld; +output csb2gate_slcg_en; +input [31:0] dma_write_stall_count; +output dma_write_stall_count_cen; +reg [33:0] bdma2csb_resp_pd; +reg bdma2csb_resp_valid; +reg [1:0] bdma2glb_done_intr_pd; +reg csb_processing_d; +reg [4:0] gather_count; +reg gather_ptr; +reg gather_vld; +reg grp0_cmd_launch_trigger; +reg grp0_read_stall_cnt_adv; +reg [31:0] grp0_read_stall_cnt_cnt_cur; +reg [33:0] grp0_read_stall_cnt_cnt_dec; +reg [33:0] grp0_read_stall_cnt_cnt_ext; +reg [33:0] grp0_read_stall_cnt_cnt_inc; +reg [33:0] grp0_read_stall_cnt_cnt_mod; +reg [33:0] grp0_read_stall_cnt_cnt_new; +reg [33:0] grp0_read_stall_cnt_cnt_nxt; +reg [31:0] grp0_read_stall_count; +reg grp1_cmd_launch_trigger; +reg grp1_read_stall_cnt_adv; +reg [31:0] grp1_read_stall_cnt_cnt_cur; +reg [33:0] grp1_read_stall_cnt_cnt_dec; +reg [33:0] grp1_read_stall_cnt_cnt_ext; +reg [33:0] grp1_read_stall_cnt_cnt_inc; +reg [33:0] grp1_read_stall_cnt_cnt_mod; +reg [33:0] grp1_read_stall_cnt_cnt_new; +reg [33:0] grp1_read_stall_cnt_cnt_nxt; +reg [31:0] grp1_read_stall_count; +reg [4:0] launch_count; +reg launch_ptr; +reg op_en_trigger; +reg [62:0] req_pd; +reg req_vld; +reg slcg_en; +reg status_grp0_busy; +reg [31:0] status_grp0_read_stall_count; +reg [31:0] status_grp0_write_stall_count; +reg status_grp1_busy; +reg [31:0] status_grp1_read_stall_count; +reg [31:0] status_grp1_write_stall_count; +wire cmd_launch_rdy; +wire cmd_launch_vld; +wire [288:0] csb_fifo_rd_pd; +wire csb_fifo_rd_prdy; +wire csb_fifo_rd_pvld; +wire [4:0] csb_fifo_wr_count; +wire csb_fifo_wr_idle; +wire [288:0] csb_fifo_wr_pd; +wire csb_fifo_wr_prdy; +wire csb_fifo_wr_pvld; +wire csb_idle; +wire csb_processing; +wire dma_read_stall_count_cen; +wire gather_rdy; +wire gather_to_launch; +wire grp0_cmd_launch; +wire grp0_read_stall_count_dec; +wire grp1_cmd_launch; +wire grp1_read_stall_count_dec; +wire is_last_cmd; +wire is_last_cmd_rdy; +wire launch_rdy; +wire launch_vld; +wire load_idle; +wire mon_csb_fifo_rd_pvld; +wire mon_csb_fifo_wr_prdy; +wire nvdla_bdma_cfg_cmd_0_dst_ram_type; +wire nvdla_bdma_cfg_cmd_0_src_ram_type; +wire [31:0] nvdla_bdma_cfg_dst_addr_high_0_v8; +wire [26:0] nvdla_bdma_cfg_dst_addr_low_0_v32; +wire [26:0] nvdla_bdma_cfg_dst_line_0_stride; +wire [26:0] nvdla_bdma_cfg_dst_surf_0_stride; +wire nvdla_bdma_cfg_launch0_0_grp0_launch; +wire nvdla_bdma_cfg_launch0_0_grp0_launch_trigger; +wire nvdla_bdma_cfg_launch1_0_grp1_launch; +wire nvdla_bdma_cfg_launch1_0_grp1_launch_trigger; +wire [12:0] nvdla_bdma_cfg_line_0_size; +wire [23:0] nvdla_bdma_cfg_line_repeat_0_number; +wire nvdla_bdma_cfg_op_0_en; +wire nvdla_bdma_cfg_op_0_en_trigger; +wire [31:0] nvdla_bdma_cfg_src_addr_high_0_v8; +wire [26:0] nvdla_bdma_cfg_src_addr_low_0_v32; +wire [26:0] nvdla_bdma_cfg_src_line_0_stride; +wire [26:0] nvdla_bdma_cfg_src_surf_0_stride; +wire nvdla_bdma_cfg_status_0_stall_count_en; +wire [23:0] nvdla_bdma_cfg_surf_repeat_0_number; +wire [7:0] nvdla_bdma_status_0_free_slot; +wire nvdla_bdma_status_0_grp0_busy; +wire nvdla_bdma_status_0_grp1_busy; +wire nvdla_bdma_status_0_idle; +wire [31:0] nvdla_bdma_status_grp0_read_stall_0_count; +wire [31:0] nvdla_bdma_status_grp0_write_stall_0_count; +wire [31:0] nvdla_bdma_status_grp1_read_stall_0_count; +wire [31:0] nvdla_bdma_status_grp1_write_stall_0_count; +wire [11:0] reg_offset; +wire [31:0] reg_rd_data; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level_NC; +wire req_nposted; +wire req_srcpriv_NC; +wire [31:0] req_wdat; +wire [3:0] req_wrbe_NC; +wire req_write; +wire [33:0] rsp_pd; +wire rsp_rd_error; +wire [32:0] rsp_rd_pd; +wire [31:0] rsp_rd_rdat; +wire rsp_rd_vld; +wire rsp_vld; +wire rsp_wr_error; +wire [32:0] rsp_wr_pd; +wire [31:0] rsp_wr_rdat; +wire rsp_wr_vld; +wire status_grp0_clr; +wire status_grp0_set; +wire status_grp1_clr; +wire status_grp1_set; +wire store_idle; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//============== +// CSB +//============== +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// &Viva width_learning_on; +// REQ INTERFACE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_vld <= 1'b0; + end else begin + req_vld <= csb2bdma_req_pvld; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2bdma_req_pvld) == 1'b1) begin + req_pd <= csb2bdma_req_pd; +// VCS coverage off + end else if ((csb2bdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2bdma_req_prdy = 1'b1; +// ======== +// REQUEST +// ======== +// flow=pvld_prdy +assign req_level_NC = req_pd[62:61]; +assign req_nposted = req_pd[55:55]; +assign req_addr = req_pd[21:0]; +assign req_wrbe_NC = req_pd[60:57]; +assign req_srcpriv_NC = req_pd[56:56]; +assign req_write = req_pd[54:54]; +assign req_wdat = req_pd[53:22]; +// ======== +// RESPONSE +// ======== +// flow=valid +// packet=dla_xx2csb_rd_erpt +assign rsp_rd_pd[32:32] = rsp_rd_error; +assign rsp_rd_pd[31:0] = rsp_rd_rdat; +// packet=dla_xx2csb_wr_erpt +assign rsp_wr_pd[32:32] = rsp_wr_error; +assign rsp_wr_pd[31:0] = rsp_wr_rdat; +assign rsp_rd_vld = req_vld & ~req_write; +assign rsp_rd_rdat = {32{rsp_rd_vld}} & reg_rd_data; +assign rsp_rd_error = 1'b0; +assign rsp_wr_vld = req_vld & req_write & req_nposted; +assign rsp_wr_rdat = {32{1'b0}}; +assign rsp_wr_error = 1'b0; +// ======== +// REQUEST +// ======== +assign rsp_vld = rsp_rd_vld | rsp_wr_vld; +assign rsp_pd[33:33] = ({1{rsp_rd_vld}} & {1'h0}) + | ({1{rsp_wr_vld}} & {1'h1}); +assign rsp_pd[32:0] = ({33{rsp_rd_vld}} & rsp_rd_pd) + | ({33{rsp_wr_vld}} & rsp_wr_pd); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2csb_resp_valid <= 1'b0; + end else begin + bdma2csb_resp_valid <= rsp_vld; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_vld) == 1'b1) begin + bdma2csb_resp_pd <= rsp_pd; +// VCS coverage off + end else if ((rsp_vld) == 1'b0) begin + end else begin + bdma2csb_resp_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign reg_offset = {req_addr[9:0],{2{1'b0}}}; +assign reg_wr_en = req_vld & req_write; +assign reg_wr_data = req_wdat; +NV_NVDLA_BDMA_reg u_NV_NVDLA_BDMA_reg ( + .reg_rd_data (reg_rd_data[31:0]) //|> w + ,.reg_offset (reg_offset[11:0]) //|< w + ,.reg_wr_data (reg_wr_data[31:0]) //|< w + ,.reg_wr_en (reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.nvdla_bdma_cfg_cmd_0_dst_ram_type (nvdla_bdma_cfg_cmd_0_dst_ram_type) //|> w + ,.nvdla_bdma_cfg_cmd_0_src_ram_type (nvdla_bdma_cfg_cmd_0_src_ram_type) //|> w + ,.nvdla_bdma_cfg_dst_addr_high_0_v8 (nvdla_bdma_cfg_dst_addr_high_0_v8[31:0]) //|> w + ,.nvdla_bdma_cfg_dst_addr_low_0_v32 (nvdla_bdma_cfg_dst_addr_low_0_v32[26:0]) //|> w + ,.nvdla_bdma_cfg_dst_line_0_stride (nvdla_bdma_cfg_dst_line_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_dst_surf_0_stride (nvdla_bdma_cfg_dst_surf_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_launch0_0_grp0_launch (nvdla_bdma_cfg_launch0_0_grp0_launch) //|> w + ,.nvdla_bdma_cfg_launch0_0_grp0_launch_trigger (nvdla_bdma_cfg_launch0_0_grp0_launch_trigger) //|> w + ,.nvdla_bdma_cfg_launch1_0_grp1_launch (nvdla_bdma_cfg_launch1_0_grp1_launch) //|> w + ,.nvdla_bdma_cfg_launch1_0_grp1_launch_trigger (nvdla_bdma_cfg_launch1_0_grp1_launch_trigger) //|> w + ,.nvdla_bdma_cfg_line_0_size (nvdla_bdma_cfg_line_0_size[12:0]) //|> w + ,.nvdla_bdma_cfg_line_repeat_0_number (nvdla_bdma_cfg_line_repeat_0_number[23:0]) //|> w + ,.nvdla_bdma_cfg_op_0_en (nvdla_bdma_cfg_op_0_en) //|> w + ,.nvdla_bdma_cfg_op_0_en_trigger (nvdla_bdma_cfg_op_0_en_trigger) //|> w + ,.nvdla_bdma_cfg_src_addr_high_0_v8 (nvdla_bdma_cfg_src_addr_high_0_v8[31:0]) //|> w + ,.nvdla_bdma_cfg_src_addr_low_0_v32 (nvdla_bdma_cfg_src_addr_low_0_v32[26:0]) //|> w + ,.nvdla_bdma_cfg_src_line_0_stride (nvdla_bdma_cfg_src_line_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_src_surf_0_stride (nvdla_bdma_cfg_src_surf_0_stride[26:0]) //|> w + ,.nvdla_bdma_cfg_status_0_stall_count_en (nvdla_bdma_cfg_status_0_stall_count_en) //|> w + ,.nvdla_bdma_cfg_surf_repeat_0_number (nvdla_bdma_cfg_surf_repeat_0_number[23:0]) //|> w + ,.nvdla_bdma_status_0_free_slot (nvdla_bdma_status_0_free_slot[7:0]) //|< w + ,.nvdla_bdma_status_0_grp0_busy (nvdla_bdma_status_0_grp0_busy) //|< w + ,.nvdla_bdma_status_0_grp1_busy (nvdla_bdma_status_0_grp1_busy) //|< w + ,.nvdla_bdma_status_0_idle (nvdla_bdma_status_0_idle) //|< w + ,.nvdla_bdma_status_grp0_read_stall_0_count (nvdla_bdma_status_grp0_read_stall_0_count[31:0]) //|< w + ,.nvdla_bdma_status_grp0_write_stall_0_count (nvdla_bdma_status_grp0_write_stall_0_count[31:0]) //|< w + ,.nvdla_bdma_status_grp1_read_stall_0_count (nvdla_bdma_status_grp1_read_stall_0_count[31:0]) //|< w + ,.nvdla_bdma_status_grp1_write_stall_0_count (nvdla_bdma_status_grp1_write_stall_0_count[31:0]) //|< w + ); +assign csb_fifo_wr_pd = {nvdla_bdma_cfg_src_addr_low_0_v32, +nvdla_bdma_cfg_src_addr_high_0_v8, +nvdla_bdma_cfg_dst_addr_low_0_v32, +nvdla_bdma_cfg_dst_addr_high_0_v8, +nvdla_bdma_cfg_line_0_size, +nvdla_bdma_cfg_cmd_0_src_ram_type, +nvdla_bdma_cfg_cmd_0_dst_ram_type, +nvdla_bdma_cfg_line_repeat_0_number, +nvdla_bdma_cfg_src_line_0_stride, +nvdla_bdma_cfg_dst_line_0_stride, +nvdla_bdma_cfg_surf_repeat_0_number, +nvdla_bdma_cfg_src_surf_0_stride, +nvdla_bdma_cfg_dst_surf_0_stride}; +NV_NVDLA_BDMA_LOAD_csb_fifo csb_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb_fifo_wr_count (csb_fifo_wr_count[4:0]) //|> w + ,.csb_fifo_wr_prdy (csb_fifo_wr_prdy) //|> w + ,.csb_fifo_wr_idle (csb_fifo_wr_idle) //|> w + ,.csb_fifo_wr_pvld (csb_fifo_wr_pvld) //|< w + ,.csb_fifo_wr_pd (csb_fifo_wr_pd[288:0]) //|< w + ,.csb_fifo_rd_prdy (csb_fifo_rd_prdy) //|< w + ,.csb_fifo_rd_pvld (csb_fifo_rd_pvld) //|> w + ,.csb_fifo_rd_pd (csb_fifo_rd_pd[288:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign {reg2dp_src_addr_low_v32, +reg2dp_src_addr_high_v8, +reg2dp_dst_addr_low_v32, +reg2dp_dst_addr_high_v8, +reg2dp_line_size, +reg2dp_cmd_src_ram_type, +reg2dp_cmd_dst_ram_type, +reg2dp_line_repeat_number, +reg2dp_src_line_stride, +reg2dp_dst_line_stride, +reg2dp_surf_repeat_number, +reg2dp_src_surf_stride, +reg2dp_dst_surf_stride} = csb_fifo_rd_pd; +// Status Gen +assign mon_csb_fifo_wr_prdy = csb_fifo_wr_prdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"memory copy command is dropped") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, csb_fifo_wr_pvld && !mon_csb_fifo_wr_prdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign nvdla_bdma_status_0_free_slot[7:0] = 20 - csb_fifo_wr_count; +//================== +// cmd -> gather_count --(when intr) -> launch_count -> pop from csb_fifo +//================== +// CSB CMD FIFO +// Memory copy command consists of content from several BDMA registers, and when BDMA_CFG_CMD register is written +// a launch of command is triggered, and this command is pushed into CSB cmd FIFO, and wait there for next pop and execution +// nvdla_bdma_cfg_op_0_en_trigger is one cycle ahead of nvdla_bdma_cfg_op_0_en in arreggen, so need flop it before using +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_trigger <= 1'b0; + end else begin + op_en_trigger <= nvdla_bdma_cfg_op_0_en_trigger; + end +end +assign csb_fifo_wr_pvld = op_en_trigger & nvdla_bdma_cfg_op_0_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp0_cmd_launch_trigger <= 1'b0; + end else begin + grp0_cmd_launch_trigger <= nvdla_bdma_cfg_launch0_0_grp0_launch_trigger; + end +end +assign grp0_cmd_launch = grp0_cmd_launch_trigger & nvdla_bdma_cfg_launch0_0_grp0_launch; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp1_cmd_launch_trigger <= 1'b0; + end else begin + grp1_cmd_launch_trigger <= nvdla_bdma_cfg_launch1_0_grp1_launch_trigger; + end +end +assign grp1_cmd_launch = grp1_cmd_launch_trigger & nvdla_bdma_cfg_launch1_0_grp1_launch; +assign cmd_launch_vld = grp0_cmd_launch | grp1_cmd_launch; +// command stalling: commands will only be popped from csb_fifo when the the last one with interrupt needed +//================== +assign gather_to_launch = gather_vld & gather_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gather_count <= {5{1'b0}}; + end else begin + if (gather_to_launch) begin + if (csb_fifo_wr_pvld) begin + gather_count <= 1; + end else begin + gather_count <= 0; + end + end else begin + if (csb_fifo_wr_pvld) begin + gather_count <= gather_count + 1; + end + end + end +end +assign cmd_launch_rdy = gather_rdy || !gather_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gather_vld <= 1'b0; + end else begin + if ((cmd_launch_rdy) == 1'b1) begin + gather_vld <= cmd_launch_vld; +// VCS coverage off + end else if ((cmd_launch_rdy) == 1'b0) begin + end else begin + gather_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd_launch_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gather_ptr <= 1'b0; + end else begin + if (grp0_cmd_launch) begin + gather_ptr <= 1'b0; + end else if (grp1_cmd_launch) begin + gather_ptr <= 1'b1; + end + end +end +assign gather_rdy = (!launch_vld) || is_last_cmd_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gather must be ready when there is a launch command") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, cmd_launch_vld & !cmd_launch_rdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property bdma_load__two_groups_are_launched_continously__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + launch_vld & gather_vld; + endproperty +// Cover 0 : "launch_vld & gather_vld" + FUNCPOINT_bdma_load__two_groups_are_launched_continously__0_COV : cover property (bdma_load__two_groups_are_launched_continously__0_cov); + `endif +`endif +//VCS coverage on +assign mon_csb_fifo_rd_pvld = csb_fifo_rd_pvld; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when launch is valid, csb_fifo must have valid data") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, launch_vld & !mon_csb_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign launch_rdy = csb2ld_rdy; +assign csb_fifo_rd_prdy = csb2ld_rdy; +assign launch_vld = launch_count!=0; +assign csb2ld_vld = launch_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + launch_count <= {5{1'b0}}; + launch_ptr <= 1'b0; + end else begin + if (launch_vld) begin + if (launch_rdy) begin + if (is_last_cmd) begin + if (gather_vld) begin + launch_count <= gather_count; + launch_ptr <= gather_ptr; + end else begin + launch_count <= launch_count - 1; + end + end else begin + launch_count <= launch_count - 1; + end + end + end else begin + if (gather_vld) begin + launch_count <= gather_count; + launch_ptr <= gather_ptr; + end + end + end +end +assign is_last_cmd = (launch_count==1); +assign is_last_cmd_rdy = launch_rdy & is_last_cmd; +assign reg2dp_cmd_interrupt = is_last_cmd_rdy; +assign reg2dp_cmd_interrupt_ptr = launch_ptr; +//================== +// STATUS SET/CLR +//================== +assign status_grp0_set = grp0_cmd_launch; +assign status_grp0_clr = st2csb_grp0_done; +assign status_grp1_set = grp1_cmd_launch; +assign status_grp1_clr = st2csb_grp1_done; +//================== +// STATUS IDLE +//================== +assign store_idle = st2csb_idle; +assign load_idle = ld2csb_idle; +assign csb_idle = csb_fifo_wr_idle; +assign nvdla_bdma_status_0_idle = store_idle & load_idle & csb_idle; +//================== +// STATUS BUSY +//================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp0_busy <= 1'b0; + end else begin + if (status_grp0_set) begin + status_grp0_busy <= 1'b1; + end else if (status_grp0_clr) begin + status_grp0_busy <= 1'b0; + end + end +end +assign nvdla_bdma_status_0_grp0_busy = status_grp0_busy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp1_busy <= 1'b0; + end else begin + if (status_grp1_set) begin + status_grp1_busy <= 1'b1; + end else if (status_grp1_clr) begin + status_grp1_busy <= 1'b0; + end + end +end +assign nvdla_bdma_status_0_grp1_busy = status_grp1_busy; +//================== +// STATUS STATISTIC +//================== +assign dma_write_stall_count_cen = nvdla_bdma_cfg_status_0_stall_count_en; +assign dma_read_stall_count_cen = nvdla_bdma_cfg_status_0_stall_count_en; + assign grp0_read_stall_count_dec = 1'b0; +// grp0_read_stall_cnt adv logic + always @( + ld2csb_grp0_dma_stall_inc + or grp0_read_stall_count_dec + ) begin + grp0_read_stall_cnt_adv = ld2csb_grp0_dma_stall_inc ^ grp0_read_stall_count_dec; + end +// grp0_read_stall_cnt cnt logic + always @( + grp0_read_stall_cnt_cnt_cur + or ld2csb_grp0_dma_stall_inc + or grp0_read_stall_count_dec + or grp0_read_stall_cnt_adv + or status_grp0_clr + ) begin +// VCS sop_coverage_off start + grp0_read_stall_cnt_cnt_ext[33:0] = {1'b0, 1'b0, grp0_read_stall_cnt_cnt_cur}; + grp0_read_stall_cnt_cnt_inc[33:0] = grp0_read_stall_cnt_cnt_cur + 1'b1; // spyglass disable W164b + grp0_read_stall_cnt_cnt_dec[33:0] = grp0_read_stall_cnt_cnt_cur - 1'b1; // spyglass disable W164b + grp0_read_stall_cnt_cnt_mod[33:0] = (ld2csb_grp0_dma_stall_inc && !grp0_read_stall_count_dec)? grp0_read_stall_cnt_cnt_inc : (!ld2csb_grp0_dma_stall_inc && grp0_read_stall_count_dec)? grp0_read_stall_cnt_cnt_dec : grp0_read_stall_cnt_cnt_ext; + grp0_read_stall_cnt_cnt_new[33:0] = (grp0_read_stall_cnt_adv)? grp0_read_stall_cnt_cnt_mod[33:0] : grp0_read_stall_cnt_cnt_ext[33:0]; + grp0_read_stall_cnt_cnt_nxt[33:0] = (status_grp0_clr)? 34'd0 : grp0_read_stall_cnt_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// grp0_read_stall_cnt flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp0_read_stall_cnt_cnt_cur[31:0] <= 0; + end else begin + if (dma_read_stall_count_cen) begin + grp0_read_stall_cnt_cnt_cur[31:0] <= grp0_read_stall_cnt_cnt_nxt[31:0]; + end + end + end +// grp0_read_stall_cnt output logic + always @( + grp0_read_stall_cnt_cnt_cur + ) begin + grp0_read_stall_count[31:0] = grp0_read_stall_cnt_cnt_cur[31:0]; + end + assign grp1_read_stall_count_dec = 1'b0; +// grp1_read_stall_cnt adv logic + always @( + ld2csb_grp1_dma_stall_inc + or grp1_read_stall_count_dec + ) begin + grp1_read_stall_cnt_adv = ld2csb_grp1_dma_stall_inc ^ grp1_read_stall_count_dec; + end +// grp1_read_stall_cnt cnt logic + always @( + grp1_read_stall_cnt_cnt_cur + or ld2csb_grp1_dma_stall_inc + or grp1_read_stall_count_dec + or grp1_read_stall_cnt_adv + or status_grp1_clr + ) begin +// VCS sop_coverage_off start + grp1_read_stall_cnt_cnt_ext[33:0] = {1'b0, 1'b0, grp1_read_stall_cnt_cnt_cur}; + grp1_read_stall_cnt_cnt_inc[33:0] = grp1_read_stall_cnt_cnt_cur + 1'b1; // spyglass disable W164b + grp1_read_stall_cnt_cnt_dec[33:0] = grp1_read_stall_cnt_cnt_cur - 1'b1; // spyglass disable W164b + grp1_read_stall_cnt_cnt_mod[33:0] = (ld2csb_grp1_dma_stall_inc && !grp1_read_stall_count_dec)? grp1_read_stall_cnt_cnt_inc : (!ld2csb_grp1_dma_stall_inc && grp1_read_stall_count_dec)? grp1_read_stall_cnt_cnt_dec : grp1_read_stall_cnt_cnt_ext; + grp1_read_stall_cnt_cnt_new[33:0] = (grp1_read_stall_cnt_adv)? grp1_read_stall_cnt_cnt_mod[33:0] : grp1_read_stall_cnt_cnt_ext[33:0]; + grp1_read_stall_cnt_cnt_nxt[33:0] = (status_grp1_clr)? 34'd0 : grp1_read_stall_cnt_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// grp1_read_stall_cnt flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grp1_read_stall_cnt_cnt_cur[31:0] <= 0; + end else begin + if (dma_read_stall_count_cen) begin + grp1_read_stall_cnt_cnt_cur[31:0] <= grp1_read_stall_cnt_cnt_nxt[31:0]; + end + end + end +// grp1_read_stall_cnt output logic + always @( + grp1_read_stall_cnt_cnt_cur + ) begin + grp1_read_stall_count[31:0] = grp1_read_stall_cnt_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp0_read_stall_count <= {32{1'b0}}; + end else begin + if (status_grp0_set) begin + status_grp0_read_stall_count <= 0; + end else if (status_grp0_clr) begin + status_grp0_read_stall_count <= grp0_read_stall_count; + end + end +end +assign nvdla_bdma_status_grp0_read_stall_0_count = status_grp0_read_stall_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp1_read_stall_count <= {32{1'b0}}; + end else begin + if (status_grp1_set) begin + status_grp1_read_stall_count <= 0; + end else if (status_grp1_clr) begin + status_grp1_read_stall_count <= grp1_read_stall_count; + end + end +end +assign nvdla_bdma_status_grp1_read_stall_0_count = status_grp1_read_stall_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp0_write_stall_count <= {32{1'b0}}; + end else begin + if (status_grp0_set) begin + status_grp0_write_stall_count <= 0; + end else if (status_grp0_clr) begin + status_grp0_write_stall_count <= dma_write_stall_count; + end + end +end +assign nvdla_bdma_status_grp0_write_stall_0_count = status_grp0_write_stall_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_grp1_write_stall_count <= {32{1'b0}}; + end else begin + if (status_grp1_set) begin + status_grp1_write_stall_count <= 0; + end else if (status_grp1_clr) begin + status_grp1_write_stall_count <= dma_write_stall_count; + end + end +end +assign nvdla_bdma_status_grp1_write_stall_0_count = status_grp1_write_stall_count; +//============== +// Interrupt to GLB +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2glb_done_intr_pd[0] <= 1'b0; + end else begin + bdma2glb_done_intr_pd[0] <= status_grp0_clr; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2glb_done_intr_pd[1] <= 1'b0; + end else begin + bdma2glb_done_intr_pd[1] <= status_grp1_clr; + end +end +//====================================== +// OBS +//assign obs_bus_bdma_csb_idle = nvdla_bdma_status_0_idle; +//assign obs_bus_bdma_csb_busy = csb_processing; +//assign obs_bus_bdma_csb_fifo_rd_pvld = csb_fifo_rd_pvld; +//assign obs_bus_bdma_csb_fifo_wr_idle = csb_fifo_wr_idle; +//assign obs_bus_bdma_csb_fifo_wr_prdy = csb_fifo_wr_prdy; +//assign obs_bus_bdma_csb_fifo_wr_pvld = csb_fifo_wr_pvld; +//assign obs_bus_bdma_csb_gather_rdy = gather_rdy; +//assign obs_bus_bdma_csb_gather_vld = gather_vld; +//assign obs_bus_bdma_csb_launch_rdy = launch_rdy; +//assign obs_bus_bdma_csb_launch_vld = launch_vld; +//assign obs_bus_bdma_csb2gate_slcg_en = slcg_en; +//====================================== +// SLCG +assign csb_processing = cmd_launch_vld | gather_vld | launch_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb_processing_d <= 1'b0; + end else begin + csb_processing_d <= csb_processing; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_en <= 1'b0; + end else begin + slcg_en <= csb_processing | csb_processing_d; + end +end +assign csb2gate_slcg_en = slcg_en; +endmodule // NV_NVDLA_BDMA_csb +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_LOAD_csb_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus csb_fifo_wr -rd_pipebus csb_fifo_rd -rd_reg -wr_idle -wr_count -d 20 -w 289 -rand_none -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_LOAD_csb_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , csb_fifo_wr_count + , csb_fifo_wr_prdy + , csb_fifo_wr_idle + , csb_fifo_wr_pvld + , csb_fifo_wr_pd + , csb_fifo_rd_prdy + , csb_fifo_rd_pvld + , csb_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output [4:0] csb_fifo_wr_count; +output csb_fifo_wr_prdy; +output csb_fifo_wr_idle; +input csb_fifo_wr_pvld; +input [288:0] csb_fifo_wr_pd; +input csb_fifo_rd_prdy; +output csb_fifo_rd_pvld; +output [288:0] csb_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg csb_fifo_wr_busy_int; // copy for internal use +assign csb_fifo_wr_prdy = !csb_fifo_wr_busy_int; +assign wr_reserving = csb_fifo_wr_pvld && !csb_fifo_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [4:0] csb_fifo_wr_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? csb_fifo_wr_count : (csb_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (csb_fifo_wr_count + 1'd1) : csb_fifo_wr_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_20 = ( wr_count_next_no_wr_popping == 5'd20 ); +wire wr_count_next_is_20 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_20; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire csb_fifo_wr_busy_next = wr_count_next_is_20 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check csb_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_wr_busy_int <= 1'b0; + csb_fifo_wr_count <= 5'd0; + end else begin + csb_fifo_wr_busy_int <= csb_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + csb_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + csb_fifo_wr_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as csb_fifo_wr_pvld +// +// RAM +// +reg [4:0] csb_fifo_wr_adr; // current write address +wire [4:0] csb_fifo_rd_adr_p; // read address to use for ram +wire [288:0] csb_fifo_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_20x289 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( csb_fifo_wr_adr ) + , .we ( wr_pushing ) + , .di ( csb_fifo_wr_pd ) + , .ra ( csb_fifo_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( csb_fifo_rd_pd_p ) + , .ore ( ore ) + ); +// next csb_fifo_wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = (csb_fifo_wr_adr == 5'd19) ? 5'd0 : (csb_fifo_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + csb_fifo_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + csb_fifo_wr_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [4:0] csb_fifo_rd_adr; // current read address +// next read address +wire [4:0] rd_adr_next = (csb_fifo_rd_adr == 5'd19) ? 5'd0 : (csb_fifo_rd_adr + 1'd1); // spyglass disable W484 +assign csb_fifo_rd_adr_p = rd_popping ? rd_adr_next : csb_fifo_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + csb_fifo_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + csb_fifo_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg csb_fifo_rd_pvld_p; // data out of fifo is valid +reg csb_fifo_rd_pvld_int; // internal copy of csb_fifo_rd_pvld +assign csb_fifo_rd_pvld = csb_fifo_rd_pvld_int; +assign rd_popping = csb_fifo_rd_pvld_p && !(csb_fifo_rd_pvld_int && !csb_fifo_rd_prdy); +reg [4:0] csb_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? csb_fifo_rd_count_p : + (csb_fifo_rd_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (csb_fifo_rd_count_p + 1'd1) : + csb_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~csb_fifo_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_rd_count_p <= 5'd0; + csb_fifo_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + csb_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + csb_fifo_rd_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + csb_fifo_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + csb_fifo_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (csb_fifo_rd_pvld_p || (csb_fifo_rd_pvld_int && !csb_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + csb_fifo_rd_pvld_int <= 1'b0; + end else begin + csb_fifo_rd_pvld_int <= rd_req_next; + end +end +assign csb_fifo_rd_pd = csb_fifo_rd_pd_p; +assign ore = rd_popping; +// +// Read-side Idle Calculation +// +wire rd_idle = !csb_fifo_rd_pvld_int && !rd_pushing && csb_fifo_rd_count_p == 0; +// +// Write-Side Idle Calculation +// +wire csb_fifo_wr_idle_d0 = !csb_fifo_wr_pvld && rd_idle && !wr_pushing && csb_fifo_wr_count == 0; +wire csb_fifo_wr_idle = csb_fifo_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (csb_fifo_wr_pvld && !csb_fifo_wr_busy_int) || (csb_fifo_wr_busy_int != csb_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (csb_fifo_rd_pvld_int && csb_fifo_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_LOAD_csb_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd20 : wr_limit_reg} ) + , .curr ( {27'd0, csb_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_LOAD_csb_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_BDMA_LOAD_csb_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v new file mode 100644 index 0000000..c7a7395 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v @@ -0,0 +1,392 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_gate.v +module NV_NVDLA_BDMA_gate ( + csb2gate_slcg_en + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,ld2gate_slcg_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,st2gate_slcg_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input csb2gate_slcg_en; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input ld2gate_slcg_en; +input nvdla_core_clk; +input nvdla_core_rstn; +input st2gate_slcg_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +wire slcg_en; +//======================================= +//CLock Gating: +assign slcg_en = csb2gate_slcg_en | ld2gate_slcg_en | st2gate_slcg_en; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_BDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v.vcp new file mode 100644 index 0000000..c7a7395 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v.vcp @@ -0,0 +1,392 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_gate.v +module NV_NVDLA_BDMA_gate ( + csb2gate_slcg_en + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,ld2gate_slcg_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,st2gate_slcg_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input csb2gate_slcg_en; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input ld2gate_slcg_en; +input nvdla_core_clk; +input nvdla_core_rstn; +input st2gate_slcg_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +wire slcg_en; +//======================================= +//CLock Gating: +assign slcg_en = csb2gate_slcg_en | ld2gate_slcg_en | st2gate_slcg_en; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_BDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_BDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v new file mode 100644 index 0000000..1188c90 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v @@ -0,0 +1,1287 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_load.v +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_load ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,bdma2mcif_rd_req_ready //|< i + ,csb2ld_vld //|< i + ,ld2st_wr_idle //|< i + ,ld2st_wr_prdy //|< i + ,reg2dp_cmd_dst_ram_type //|< i + ,reg2dp_cmd_interrupt //|< i + ,reg2dp_cmd_interrupt_ptr //|< i + ,reg2dp_cmd_src_ram_type //|< i + ,reg2dp_dst_addr_high_v8 //|< i + ,reg2dp_dst_addr_low_v32 //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_surf_stride //|< i + ,reg2dp_line_repeat_number //|< i + ,reg2dp_line_size //|< i + ,reg2dp_src_addr_high_v8 //|< i + ,reg2dp_src_addr_low_v32 //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_surf_stride //|< i + ,reg2dp_surf_repeat_number //|< i + ,st2ld_load_idle //|< i + ,bdma2mcif_rd_req_pd //|> o + ,bdma2mcif_rd_req_valid //|> o + ,csb2ld_rdy //|> o + ,ld2csb_grp0_dma_stall_inc //|> o + ,ld2csb_grp1_dma_stall_inc //|> o + ,ld2csb_idle //|> o + ,ld2gate_slcg_en //|> o + ,ld2st_wr_pd //|> o + ,ld2st_wr_pvld //|> o + ); +// +// NV_NVDLA_BDMA_load_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output bdma2mcif_rd_req_valid; /* data valid */ +input bdma2mcif_rd_req_ready; /* data return handshake */ +output [78:0] bdma2mcif_rd_req_pd; +output ld2st_wr_pvld; /* data valid */ +input ld2st_wr_prdy; /* data return handshake */ +output [160:0] ld2st_wr_pd; +//&Ports /^obs_bus/; +input reg2dp_cmd_dst_ram_type; +input reg2dp_cmd_interrupt; +input reg2dp_cmd_interrupt_ptr; +input reg2dp_cmd_src_ram_type; +input [31:0] reg2dp_dst_addr_high_v8; +input [26:0] reg2dp_dst_addr_low_v32; +input [26:0] reg2dp_dst_line_stride; +input [26:0] reg2dp_dst_surf_stride; +input [23:0] reg2dp_line_repeat_number; +input [12:0] reg2dp_line_size; +input [31:0] reg2dp_src_addr_high_v8; +input [26:0] reg2dp_src_addr_low_v32; +input [26:0] reg2dp_src_line_stride; +input [26:0] reg2dp_src_surf_stride; +input [23:0] reg2dp_surf_repeat_number; +input csb2ld_vld; +output csb2ld_rdy; +output ld2csb_grp0_dma_stall_inc; +output ld2csb_grp1_dma_stall_inc; +output ld2csb_idle; +input ld2st_wr_idle; +input st2ld_load_idle; +output ld2gate_slcg_en; +reg ld2gate_slcg_en; +reg [63:0] line_addr; +reg [23:0] line_count; +reg mon_line_addr_c; +reg mon_surf_addr_c; +reg reg_cmd_src_ram_type; +reg [23:0] reg_line_repeat_number; +reg [12:0] reg_line_size; +reg [31:0] reg_line_stride; +reg [23:0] reg_surf_repeat_number; +reg [31:0] reg_surf_stride; +reg [63:0] surf_addr; +reg [23:0] surf_count; +reg tran_valid; +wire cmd_ready; +wire cmd_valid; +wire cv_dma_rd_req_rdy; +wire cv_dma_rd_req_vld; +wire [78:0] cv_int_rd_req_pd; +wire [78:0] cv_int_rd_req_pd_d0; +wire cv_int_rd_req_ready; +wire cv_int_rd_req_ready_d0; +wire cv_int_rd_req_valid; +wire cv_int_rd_req_valid_d0; +wire cv_rd_req_rdyi; +wire [63:0] dma_rd_req_addr; +wire [78:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [14:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire dma_stall_inc; +wire is_cube_end; +wire is_last_req_in_line; +wire is_src_ram_type_switching; +wire is_surf_end; +wire [63:0] ld2st_addr; +wire ld2st_cmd_dst_ram_type; +wire ld2st_cmd_interrupt; +wire ld2st_cmd_interrupt_ptr; +wire ld2st_cmd_src_ram_type; +wire [23:0] ld2st_line_repeat_number; +wire [12:0] ld2st_line_size; +wire [26:0] ld2st_line_stride; +wire [23:0] ld2st_surf_repeat_number; +wire [26:0] ld2st_surf_stride; +wire ld_idle; +wire load_cmd; +wire load_cmd_en; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire mc_rd_req_rdyi; +wire rd_req_rdyi; +wire [63:0] reg2dp_addr; +wire [63:0] reg2dp_dst_addr; +wire [31:0] reg2dp_src_line_stride_ext; +wire [31:0] reg2dp_src_surf_stride_ext; +wire tran_accept; +wire [63:0] tran_addr; +wire tran_ready; +wire [14:0] tran_size; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//============== +// LOAD: PROCESS +//============== +// when Load process is idle or finished the execution of last command, it will pop the next command from CSB cmd FIFO +// input rename +// FLAG: processing +// downstreams are dmaif and context-Q +// after the csb cmd queue, will have one more layer to buffer the command when processing +// will load when cmd layer is empty, or when reach the last transaction and will be accepted by downstream(dma and CQ) +// cmd_valid cmd_ready +// _|_______________|_ +// | pipe | +// |___________________| +// v ^ +// tran_valid tran_ready +assign csb2ld_rdy = ld2st_wr_prdy & cmd_ready & load_cmd_en; +assign ld2st_wr_pvld = csb2ld_vld & cmd_ready & load_cmd_en; +assign cmd_valid = csb2ld_vld & ld2st_wr_prdy & load_cmd_en; +assign cmd_ready = (!tran_valid) | (tran_accept & is_cube_end); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_valid <= 1'b0; + end else begin + if ((cmd_ready) == 1'b1) begin + tran_valid <= cmd_valid; +// VCS coverage off + end else if ((cmd_ready) == 1'b0) begin + end else begin + tran_valid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd_ready))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign tran_ready = dma_rd_req_rdy; +assign tran_accept = tran_valid & tran_ready; +assign load_cmd = cmd_valid & cmd_ready; +assign is_src_ram_type_switching = (reg2dp_cmd_src_ram_type!=reg_cmd_src_ram_type); +assign load_cmd_en = csb2ld_vld & ((ld_idle & st2ld_load_idle) || !is_src_ram_type_switching); +//============================== +// IDLE +assign ld_idle = ld2st_wr_idle & !tran_valid; +assign ld2csb_idle = ld_idle; +//============================== +// SLCG +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ld2gate_slcg_en <= 1'b0; + end else begin + ld2gate_slcg_en <= !ld_idle; + end +end +// Constant Reg on each COMMAND +assign reg2dp_dst_addr[63:0] = {reg2dp_dst_addr_high_v8,reg2dp_dst_addr_low_v32,5'd0}; +assign reg2dp_addr[63:0] = {reg2dp_src_addr_high_v8,reg2dp_src_addr_low_v32,5'd0}; +assign reg2dp_src_line_stride_ext = {reg2dp_src_line_stride,5'h0}; +assign reg2dp_src_surf_stride_ext = {reg2dp_src_surf_stride,5'h0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_line_size <= {13{1'b0}}; + reg_cmd_src_ram_type <= 1'b0; + reg_line_stride <= {32{1'b0}}; + reg_surf_stride <= {32{1'b0}}; + reg_line_repeat_number <= {24{1'b0}}; + reg_surf_repeat_number <= {24{1'b0}}; + end else begin + if (load_cmd) begin + reg_line_size <= reg2dp_line_size; + reg_cmd_src_ram_type <= reg2dp_cmd_src_ram_type; + reg_line_stride <= reg2dp_src_line_stride_ext; + reg_surf_stride <= reg2dp_src_surf_stride_ext; +//reg_cmd_dst_ram_type <= reg2dp_cmd_dst_ram_type; +//reg_cmd_interrupt <= reg2dp_cmd_interrupt; + reg_line_repeat_number <= reg2dp_line_repeat_number; +//reg_dst_line_stride <= reg2dp_dst_line_stride; + reg_surf_repeat_number <= reg2dp_surf_repeat_number; +//reg_dst_surf_stride <= reg2dp_dst_surf_stride; +//reg_src_addr <= reg2dp_src_addr; +//reg_dst_addr <= reg2dp_dst_addr; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"Line Address is overlapped within one single command") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_line_size<<5) > reg_line_stride); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// =================================== +// Context Queue Write +// =================================== +// below are required cmd information needed in store side to reassemble the return data, +// and format the DMA write request, one emtry is needed for each MOMERY COPY COMMAND +assign ld2st_addr = reg2dp_dst_addr; +assign ld2st_line_size = reg2dp_line_size; +assign ld2st_cmd_src_ram_type = reg2dp_cmd_src_ram_type; +assign ld2st_cmd_dst_ram_type = reg2dp_cmd_dst_ram_type; +assign ld2st_cmd_interrupt = reg2dp_cmd_interrupt; +assign ld2st_cmd_interrupt_ptr = reg2dp_cmd_interrupt_ptr; +assign ld2st_line_stride = reg2dp_dst_line_stride; +assign ld2st_surf_stride = reg2dp_dst_surf_stride; +assign ld2st_line_repeat_number = reg2dp_line_repeat_number; +assign ld2st_surf_repeat_number = reg2dp_surf_repeat_number; +// PKT_PACK_WIRE( bdma_ld2st , ld2st_ , ld2st_wr_pd ) +assign ld2st_wr_pd[63:0] = ld2st_addr[63:0]; +assign ld2st_wr_pd[76:64] = ld2st_line_size[12:0]; +assign ld2st_wr_pd[77] = ld2st_cmd_src_ram_type ; +assign ld2st_wr_pd[78] = ld2st_cmd_dst_ram_type ; +assign ld2st_wr_pd[79] = ld2st_cmd_interrupt ; +assign ld2st_wr_pd[80] = ld2st_cmd_interrupt_ptr ; +assign ld2st_wr_pd[107:81] = ld2st_line_stride[26:0]; +assign ld2st_wr_pd[120:108] = ld2st_line_repeat_number[12:0]; +assign ld2st_wr_pd[147:121] = ld2st_surf_stride[26:0]; +assign ld2st_wr_pd[160:148] = ld2st_surf_repeat_number[12:0]; +// Variable Reg on each COMMAND +// 3-D support tran->line->surf->cube +// cube consists of multiple surfaces(surf) +// surf consists of multiple lines +// line consists of multiple transaction(tran) +assign is_last_req_in_line = 1'b1; +assign is_surf_end = is_last_req_in_line & (line_count==reg_line_repeat_number); +assign is_cube_end = is_surf_end & (surf_count==reg_surf_repeat_number); +// tran_addr is the start address of each DMA request +// will load a new one from CSB FIFO for every mem copy command +// will change every time one DMA request is aacpetted by xxif +assign tran_addr = line_addr; +// Line_addr is the start address of every line +// load a new one from CSB FIFO for every mem copy command +// will change every time one a block is done and jump to the next line +always @(posedge nvdla_core_clk) begin + if (load_cmd) begin + line_addr <= reg2dp_addr; + end else if (tran_accept) begin + if (is_surf_end) begin + {mon_line_addr_c,line_addr} <= surf_addr + reg_surf_stride; + end else begin + {mon_line_addr_c,line_addr} <= line_addr + reg_line_stride; + end + end +end +// Surf_addr is the base address of each surface +// load a new one from CSB FIFO for every mem copy command +// will change every time one a block is done and jump to the next surface +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_addr <= {64{1'b0}}; + {mon_surf_addr_c,surf_addr} <= {65{1'b0}}; + end else begin + if (load_cmd) begin + surf_addr <= reg2dp_addr; + end else if (tran_accept) begin + if (is_surf_end) begin + {mon_surf_addr_c,surf_addr} <= surf_addr + reg_surf_stride; + end + end + end +end +//===TRAN SIZE +// for each DMA request, tran_size is to tell how many 32B DATA block indicated +assign tran_size = {{2{1'b0}}, reg_line_size};// reg_line_size; +// ===LINE COUNT +// count++ when just to next line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_count <= {24{1'b0}}; + end else begin + if (tran_accept) begin + if (is_surf_end) begin + line_count <= 0; + end else begin + line_count <= line_count + 1; + end + end + end +end +// SURF COUNT +// count++ when just to next surf +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_count <= {24{1'b0}}; + end else begin + if (tran_accept) begin + if (is_cube_end) begin + surf_count <= 0; + end else if (is_surf_end) begin + surf_count <= surf_count + 1; + end + end + end +end +//============== +// LOAD: DMA OUT +//============== +// ===DMA Request: ADDR/SIZE/INTR +assign dma_rd_req_vld = tran_valid; +assign dma_rd_req_addr = tran_addr; +assign dma_rd_req_type = reg_cmd_src_ram_type; +assign dma_rd_req_size = tran_size; +// PKT_PACK_WIRE( dma_read_cmd , dma_rd_req_ , dma_rd_req_pd ) +assign dma_rd_req_pd[63:0] = dma_rd_req_addr[63:0]; +assign dma_rd_req_pd[78:64] = dma_rd_req_size[14:0]; +// rd Channel: Request +assign cv_dma_rd_req_vld = dma_rd_req_vld & (dma_rd_req_type == 1'b0); +assign mc_dma_rd_req_vld = dma_rd_req_vld & (dma_rd_req_type == 1'b1); +assign cv_rd_req_rdyi = cv_dma_rd_req_rdy & (dma_rd_req_type == 1'b0); +assign mc_rd_req_rdyi = mc_dma_rd_req_rdy & (dma_rd_req_type == 1'b1); +assign rd_req_rdyi = mc_rd_req_rdyi | cv_rd_req_rdyi; +assign dma_rd_req_rdy= rd_req_rdyi; +NV_NVDLA_BDMA_LOAD_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma_rd_req_pd (dma_rd_req_pd[78:0]) //|< w + ,.mc_dma_rd_req_vld (mc_dma_rd_req_vld) //|< w + ,.mc_int_rd_req_ready (mc_int_rd_req_ready) //|< w + ,.mc_dma_rd_req_rdy (mc_dma_rd_req_rdy) //|> w + ,.mc_int_rd_req_pd (mc_int_rd_req_pd[78:0]) //|> w + ,.mc_int_rd_req_valid (mc_int_rd_req_valid) //|> w + ); +NV_NVDLA_BDMA_LOAD_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cv_dma_rd_req_vld (cv_dma_rd_req_vld) //|< w + ,.cv_int_rd_req_ready (cv_int_rd_req_ready) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[78:0]) //|< w + ,.cv_dma_rd_req_rdy (cv_dma_rd_req_rdy) //|> w + ,.cv_int_rd_req_pd (cv_int_rd_req_pd[78:0]) //|> w + ,.cv_int_rd_req_valid (cv_int_rd_req_valid) //|> w + ); +assign mc_int_rd_req_valid_d0 = mc_int_rd_req_valid; +assign mc_int_rd_req_ready = mc_int_rd_req_ready_d0; +assign mc_int_rd_req_pd_d0[78:0] = mc_int_rd_req_pd[78:0]; +assign bdma2mcif_rd_req_valid = mc_int_rd_req_valid_d0; +assign mc_int_rd_req_ready_d0 = bdma2mcif_rd_req_ready; +assign bdma2mcif_rd_req_pd[78:0] = mc_int_rd_req_pd_d0[78:0]; +assign cv_int_rd_req_valid_d0 = cv_int_rd_req_valid; +assign cv_int_rd_req_ready = cv_int_rd_req_ready_d0; +assign cv_int_rd_req_pd_d0[78:0] = cv_int_rd_req_pd[78:0]; +//&Viva width_learning_off; +assign dma_stall_inc = dma_rd_req_vld & !dma_rd_req_rdy; +assign ld2csb_grp0_dma_stall_inc = dma_stall_inc & reg2dp_cmd_interrupt_ptr==0; +assign ld2csb_grp1_dma_stall_inc = dma_stall_inc & reg2dp_cmd_interrupt_ptr==1; +//====================================== +// OBS Signals +//====================================== +//assign obs_bus_bdma_load_cmd = load_cmd; +//assign obs_bus_bdma_load_cmd_en = load_cmd_en; +//assign obs_bus_bdma_load_idle = ld_idle; +//assign obs_bus_bdma_load_ram_switch = is_src_ram_type_switching; +//assign obs_bus_bdma_load_tran_ready = tran_ready; +//assign obs_bus_bdma_load_tran_valid = tran_valid; +//assign obs_bus_bdma_load_ld2st_wr_pvld = ld2st_wr_pvld; +//assign obs_bus_bdma_load_ld2st_wr_prdy = ld2st_wr_prdy; +//assign obs_bus_bdma_load_ld2st_wr_idle = ld2st_wr_idle; +endmodule // NV_NVDLA_BDMA_load +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_rd_req_pd (mc_int_rd_req_valid,mc_int_rd_req_ready) <= dma_rd_req_pd[78:0] (mc_dma_rd_req_vld,mc_dma_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_LOAD_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_req_pd + ,mc_dma_rd_req_vld + ,mc_int_rd_req_ready + ,mc_dma_rd_req_rdy + ,mc_int_rd_req_pd + ,mc_int_rd_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] dma_rd_req_pd; +input mc_dma_rd_req_vld; +input mc_int_rd_req_ready; +output mc_dma_rd_req_rdy; +output [78:0] mc_int_rd_req_pd; +output mc_int_rd_req_valid; +reg mc_dma_rd_req_rdy; +reg [78:0] mc_int_rd_req_pd; +reg mc_int_rd_req_valid; +reg [78:0] p1_pipe_data; +reg [78:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [78:0] p1_skid_data; +reg [78:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_dma_rd_req_vld + or p1_pipe_rand_ready + or dma_rd_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = dma_rd_req_pd[78:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : dma_rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_dma_rd_req_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_dma_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mc_int_rd_req_ready + or p1_pipe_data + ) begin + mc_int_rd_req_valid = p1_pipe_valid; + p1_pipe_ready = mc_int_rd_req_ready; + mc_int_rd_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_rd_req_valid^mc_int_rd_req_ready^mc_dma_rd_req_vld^mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mc_dma_rd_req_vld && !mc_dma_rd_req_rdy), (mc_dma_rd_req_vld), (mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_LOAD_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_rd_req_pd (cv_int_rd_req_valid,cv_int_rd_req_ready) <= dma_rd_req_pd[78:0] (cv_dma_rd_req_vld,cv_dma_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_LOAD_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cv_dma_rd_req_vld + ,cv_int_rd_req_ready + ,dma_rd_req_pd + ,cv_dma_rd_req_rdy + ,cv_int_rd_req_pd + ,cv_int_rd_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cv_dma_rd_req_vld; +input cv_int_rd_req_ready; +input [78:0] dma_rd_req_pd; +output cv_dma_rd_req_rdy; +output [78:0] cv_int_rd_req_pd; +output cv_int_rd_req_valid; +reg cv_dma_rd_req_rdy; +reg [78:0] cv_int_rd_req_pd; +reg cv_int_rd_req_valid; +reg [78:0] p2_pipe_data; +reg [78:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [78:0] p2_skid_data; +reg [78:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + cv_dma_rd_req_vld + or p2_pipe_rand_ready + or dma_rd_req_pd + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = cv_dma_rd_req_vld; + cv_dma_rd_req_rdy = p2_pipe_rand_ready; + p2_pipe_rand_data = dma_rd_req_pd[78:0]; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : cv_dma_rd_req_vld; + cv_dma_rd_req_rdy = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : dma_rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or cv_dma_rd_req_vld + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && cv_dma_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) skid buffer +always @( + p2_pipe_rand_valid + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_rand_valid && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_rand_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_rand_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_rand_valid + or p2_skid_valid + or p2_pipe_rand_data + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? p2_pipe_rand_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or cv_int_rd_req_ready + or p2_pipe_data + ) begin + cv_int_rd_req_valid = p2_pipe_valid; + p2_pipe_ready = cv_int_rd_req_ready; + cv_int_rd_req_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cv_int_rd_req_valid^cv_int_rd_req_ready^cv_dma_rd_req_vld^cv_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (cv_dma_rd_req_vld && !cv_dma_rd_req_rdy), (cv_dma_rd_req_vld), (cv_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_LOAD_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v.vcp new file mode 100644 index 0000000..1188c90 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v.vcp @@ -0,0 +1,1287 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_load.v +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_load ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,bdma2mcif_rd_req_ready //|< i + ,csb2ld_vld //|< i + ,ld2st_wr_idle //|< i + ,ld2st_wr_prdy //|< i + ,reg2dp_cmd_dst_ram_type //|< i + ,reg2dp_cmd_interrupt //|< i + ,reg2dp_cmd_interrupt_ptr //|< i + ,reg2dp_cmd_src_ram_type //|< i + ,reg2dp_dst_addr_high_v8 //|< i + ,reg2dp_dst_addr_low_v32 //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_surf_stride //|< i + ,reg2dp_line_repeat_number //|< i + ,reg2dp_line_size //|< i + ,reg2dp_src_addr_high_v8 //|< i + ,reg2dp_src_addr_low_v32 //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_surf_stride //|< i + ,reg2dp_surf_repeat_number //|< i + ,st2ld_load_idle //|< i + ,bdma2mcif_rd_req_pd //|> o + ,bdma2mcif_rd_req_valid //|> o + ,csb2ld_rdy //|> o + ,ld2csb_grp0_dma_stall_inc //|> o + ,ld2csb_grp1_dma_stall_inc //|> o + ,ld2csb_idle //|> o + ,ld2gate_slcg_en //|> o + ,ld2st_wr_pd //|> o + ,ld2st_wr_pvld //|> o + ); +// +// NV_NVDLA_BDMA_load_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output bdma2mcif_rd_req_valid; /* data valid */ +input bdma2mcif_rd_req_ready; /* data return handshake */ +output [78:0] bdma2mcif_rd_req_pd; +output ld2st_wr_pvld; /* data valid */ +input ld2st_wr_prdy; /* data return handshake */ +output [160:0] ld2st_wr_pd; +//&Ports /^obs_bus/; +input reg2dp_cmd_dst_ram_type; +input reg2dp_cmd_interrupt; +input reg2dp_cmd_interrupt_ptr; +input reg2dp_cmd_src_ram_type; +input [31:0] reg2dp_dst_addr_high_v8; +input [26:0] reg2dp_dst_addr_low_v32; +input [26:0] reg2dp_dst_line_stride; +input [26:0] reg2dp_dst_surf_stride; +input [23:0] reg2dp_line_repeat_number; +input [12:0] reg2dp_line_size; +input [31:0] reg2dp_src_addr_high_v8; +input [26:0] reg2dp_src_addr_low_v32; +input [26:0] reg2dp_src_line_stride; +input [26:0] reg2dp_src_surf_stride; +input [23:0] reg2dp_surf_repeat_number; +input csb2ld_vld; +output csb2ld_rdy; +output ld2csb_grp0_dma_stall_inc; +output ld2csb_grp1_dma_stall_inc; +output ld2csb_idle; +input ld2st_wr_idle; +input st2ld_load_idle; +output ld2gate_slcg_en; +reg ld2gate_slcg_en; +reg [63:0] line_addr; +reg [23:0] line_count; +reg mon_line_addr_c; +reg mon_surf_addr_c; +reg reg_cmd_src_ram_type; +reg [23:0] reg_line_repeat_number; +reg [12:0] reg_line_size; +reg [31:0] reg_line_stride; +reg [23:0] reg_surf_repeat_number; +reg [31:0] reg_surf_stride; +reg [63:0] surf_addr; +reg [23:0] surf_count; +reg tran_valid; +wire cmd_ready; +wire cmd_valid; +wire cv_dma_rd_req_rdy; +wire cv_dma_rd_req_vld; +wire [78:0] cv_int_rd_req_pd; +wire [78:0] cv_int_rd_req_pd_d0; +wire cv_int_rd_req_ready; +wire cv_int_rd_req_ready_d0; +wire cv_int_rd_req_valid; +wire cv_int_rd_req_valid_d0; +wire cv_rd_req_rdyi; +wire [63:0] dma_rd_req_addr; +wire [78:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [14:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire dma_stall_inc; +wire is_cube_end; +wire is_last_req_in_line; +wire is_src_ram_type_switching; +wire is_surf_end; +wire [63:0] ld2st_addr; +wire ld2st_cmd_dst_ram_type; +wire ld2st_cmd_interrupt; +wire ld2st_cmd_interrupt_ptr; +wire ld2st_cmd_src_ram_type; +wire [23:0] ld2st_line_repeat_number; +wire [12:0] ld2st_line_size; +wire [26:0] ld2st_line_stride; +wire [23:0] ld2st_surf_repeat_number; +wire [26:0] ld2st_surf_stride; +wire ld_idle; +wire load_cmd; +wire load_cmd_en; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire mc_rd_req_rdyi; +wire rd_req_rdyi; +wire [63:0] reg2dp_addr; +wire [63:0] reg2dp_dst_addr; +wire [31:0] reg2dp_src_line_stride_ext; +wire [31:0] reg2dp_src_surf_stride_ext; +wire tran_accept; +wire [63:0] tran_addr; +wire tran_ready; +wire [14:0] tran_size; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//============== +// LOAD: PROCESS +//============== +// when Load process is idle or finished the execution of last command, it will pop the next command from CSB cmd FIFO +// input rename +// FLAG: processing +// downstreams are dmaif and context-Q +// after the csb cmd queue, will have one more layer to buffer the command when processing +// will load when cmd layer is empty, or when reach the last transaction and will be accepted by downstream(dma and CQ) +// cmd_valid cmd_ready +// _|_______________|_ +// | pipe | +// |___________________| +// v ^ +// tran_valid tran_ready +assign csb2ld_rdy = ld2st_wr_prdy & cmd_ready & load_cmd_en; +assign ld2st_wr_pvld = csb2ld_vld & cmd_ready & load_cmd_en; +assign cmd_valid = csb2ld_vld & ld2st_wr_prdy & load_cmd_en; +assign cmd_ready = (!tran_valid) | (tran_accept & is_cube_end); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_valid <= 1'b0; + end else begin + if ((cmd_ready) == 1'b1) begin + tran_valid <= cmd_valid; +// VCS coverage off + end else if ((cmd_ready) == 1'b0) begin + end else begin + tran_valid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd_ready))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign tran_ready = dma_rd_req_rdy; +assign tran_accept = tran_valid & tran_ready; +assign load_cmd = cmd_valid & cmd_ready; +assign is_src_ram_type_switching = (reg2dp_cmd_src_ram_type!=reg_cmd_src_ram_type); +assign load_cmd_en = csb2ld_vld & ((ld_idle & st2ld_load_idle) || !is_src_ram_type_switching); +//============================== +// IDLE +assign ld_idle = ld2st_wr_idle & !tran_valid; +assign ld2csb_idle = ld_idle; +//============================== +// SLCG +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ld2gate_slcg_en <= 1'b0; + end else begin + ld2gate_slcg_en <= !ld_idle; + end +end +// Constant Reg on each COMMAND +assign reg2dp_dst_addr[63:0] = {reg2dp_dst_addr_high_v8,reg2dp_dst_addr_low_v32,5'd0}; +assign reg2dp_addr[63:0] = {reg2dp_src_addr_high_v8,reg2dp_src_addr_low_v32,5'd0}; +assign reg2dp_src_line_stride_ext = {reg2dp_src_line_stride,5'h0}; +assign reg2dp_src_surf_stride_ext = {reg2dp_src_surf_stride,5'h0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_line_size <= {13{1'b0}}; + reg_cmd_src_ram_type <= 1'b0; + reg_line_stride <= {32{1'b0}}; + reg_surf_stride <= {32{1'b0}}; + reg_line_repeat_number <= {24{1'b0}}; + reg_surf_repeat_number <= {24{1'b0}}; + end else begin + if (load_cmd) begin + reg_line_size <= reg2dp_line_size; + reg_cmd_src_ram_type <= reg2dp_cmd_src_ram_type; + reg_line_stride <= reg2dp_src_line_stride_ext; + reg_surf_stride <= reg2dp_src_surf_stride_ext; +//reg_cmd_dst_ram_type <= reg2dp_cmd_dst_ram_type; +//reg_cmd_interrupt <= reg2dp_cmd_interrupt; + reg_line_repeat_number <= reg2dp_line_repeat_number; +//reg_dst_line_stride <= reg2dp_dst_line_stride; + reg_surf_repeat_number <= reg2dp_surf_repeat_number; +//reg_dst_surf_stride <= reg2dp_dst_surf_stride; +//reg_src_addr <= reg2dp_src_addr; +//reg_dst_addr <= reg2dp_dst_addr; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"Line Address is overlapped within one single command") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_line_size<<5) > reg_line_stride); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// =================================== +// Context Queue Write +// =================================== +// below are required cmd information needed in store side to reassemble the return data, +// and format the DMA write request, one emtry is needed for each MOMERY COPY COMMAND +assign ld2st_addr = reg2dp_dst_addr; +assign ld2st_line_size = reg2dp_line_size; +assign ld2st_cmd_src_ram_type = reg2dp_cmd_src_ram_type; +assign ld2st_cmd_dst_ram_type = reg2dp_cmd_dst_ram_type; +assign ld2st_cmd_interrupt = reg2dp_cmd_interrupt; +assign ld2st_cmd_interrupt_ptr = reg2dp_cmd_interrupt_ptr; +assign ld2st_line_stride = reg2dp_dst_line_stride; +assign ld2st_surf_stride = reg2dp_dst_surf_stride; +assign ld2st_line_repeat_number = reg2dp_line_repeat_number; +assign ld2st_surf_repeat_number = reg2dp_surf_repeat_number; +// PKT_PACK_WIRE( bdma_ld2st , ld2st_ , ld2st_wr_pd ) +assign ld2st_wr_pd[63:0] = ld2st_addr[63:0]; +assign ld2st_wr_pd[76:64] = ld2st_line_size[12:0]; +assign ld2st_wr_pd[77] = ld2st_cmd_src_ram_type ; +assign ld2st_wr_pd[78] = ld2st_cmd_dst_ram_type ; +assign ld2st_wr_pd[79] = ld2st_cmd_interrupt ; +assign ld2st_wr_pd[80] = ld2st_cmd_interrupt_ptr ; +assign ld2st_wr_pd[107:81] = ld2st_line_stride[26:0]; +assign ld2st_wr_pd[120:108] = ld2st_line_repeat_number[12:0]; +assign ld2st_wr_pd[147:121] = ld2st_surf_stride[26:0]; +assign ld2st_wr_pd[160:148] = ld2st_surf_repeat_number[12:0]; +// Variable Reg on each COMMAND +// 3-D support tran->line->surf->cube +// cube consists of multiple surfaces(surf) +// surf consists of multiple lines +// line consists of multiple transaction(tran) +assign is_last_req_in_line = 1'b1; +assign is_surf_end = is_last_req_in_line & (line_count==reg_line_repeat_number); +assign is_cube_end = is_surf_end & (surf_count==reg_surf_repeat_number); +// tran_addr is the start address of each DMA request +// will load a new one from CSB FIFO for every mem copy command +// will change every time one DMA request is aacpetted by xxif +assign tran_addr = line_addr; +// Line_addr is the start address of every line +// load a new one from CSB FIFO for every mem copy command +// will change every time one a block is done and jump to the next line +always @(posedge nvdla_core_clk) begin + if (load_cmd) begin + line_addr <= reg2dp_addr; + end else if (tran_accept) begin + if (is_surf_end) begin + {mon_line_addr_c,line_addr} <= surf_addr + reg_surf_stride; + end else begin + {mon_line_addr_c,line_addr} <= line_addr + reg_line_stride; + end + end +end +// Surf_addr is the base address of each surface +// load a new one from CSB FIFO for every mem copy command +// will change every time one a block is done and jump to the next surface +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_addr <= {64{1'b0}}; + {mon_surf_addr_c,surf_addr} <= {65{1'b0}}; + end else begin + if (load_cmd) begin + surf_addr <= reg2dp_addr; + end else if (tran_accept) begin + if (is_surf_end) begin + {mon_surf_addr_c,surf_addr} <= surf_addr + reg_surf_stride; + end + end + end +end +//===TRAN SIZE +// for each DMA request, tran_size is to tell how many 32B DATA block indicated +assign tran_size = {{2{1'b0}}, reg_line_size};// reg_line_size; +// ===LINE COUNT +// count++ when just to next line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_count <= {24{1'b0}}; + end else begin + if (tran_accept) begin + if (is_surf_end) begin + line_count <= 0; + end else begin + line_count <= line_count + 1; + end + end + end +end +// SURF COUNT +// count++ when just to next surf +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_count <= {24{1'b0}}; + end else begin + if (tran_accept) begin + if (is_cube_end) begin + surf_count <= 0; + end else if (is_surf_end) begin + surf_count <= surf_count + 1; + end + end + end +end +//============== +// LOAD: DMA OUT +//============== +// ===DMA Request: ADDR/SIZE/INTR +assign dma_rd_req_vld = tran_valid; +assign dma_rd_req_addr = tran_addr; +assign dma_rd_req_type = reg_cmd_src_ram_type; +assign dma_rd_req_size = tran_size; +// PKT_PACK_WIRE( dma_read_cmd , dma_rd_req_ , dma_rd_req_pd ) +assign dma_rd_req_pd[63:0] = dma_rd_req_addr[63:0]; +assign dma_rd_req_pd[78:64] = dma_rd_req_size[14:0]; +// rd Channel: Request +assign cv_dma_rd_req_vld = dma_rd_req_vld & (dma_rd_req_type == 1'b0); +assign mc_dma_rd_req_vld = dma_rd_req_vld & (dma_rd_req_type == 1'b1); +assign cv_rd_req_rdyi = cv_dma_rd_req_rdy & (dma_rd_req_type == 1'b0); +assign mc_rd_req_rdyi = mc_dma_rd_req_rdy & (dma_rd_req_type == 1'b1); +assign rd_req_rdyi = mc_rd_req_rdyi | cv_rd_req_rdyi; +assign dma_rd_req_rdy= rd_req_rdyi; +NV_NVDLA_BDMA_LOAD_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma_rd_req_pd (dma_rd_req_pd[78:0]) //|< w + ,.mc_dma_rd_req_vld (mc_dma_rd_req_vld) //|< w + ,.mc_int_rd_req_ready (mc_int_rd_req_ready) //|< w + ,.mc_dma_rd_req_rdy (mc_dma_rd_req_rdy) //|> w + ,.mc_int_rd_req_pd (mc_int_rd_req_pd[78:0]) //|> w + ,.mc_int_rd_req_valid (mc_int_rd_req_valid) //|> w + ); +NV_NVDLA_BDMA_LOAD_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cv_dma_rd_req_vld (cv_dma_rd_req_vld) //|< w + ,.cv_int_rd_req_ready (cv_int_rd_req_ready) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[78:0]) //|< w + ,.cv_dma_rd_req_rdy (cv_dma_rd_req_rdy) //|> w + ,.cv_int_rd_req_pd (cv_int_rd_req_pd[78:0]) //|> w + ,.cv_int_rd_req_valid (cv_int_rd_req_valid) //|> w + ); +assign mc_int_rd_req_valid_d0 = mc_int_rd_req_valid; +assign mc_int_rd_req_ready = mc_int_rd_req_ready_d0; +assign mc_int_rd_req_pd_d0[78:0] = mc_int_rd_req_pd[78:0]; +assign bdma2mcif_rd_req_valid = mc_int_rd_req_valid_d0; +assign mc_int_rd_req_ready_d0 = bdma2mcif_rd_req_ready; +assign bdma2mcif_rd_req_pd[78:0] = mc_int_rd_req_pd_d0[78:0]; +assign cv_int_rd_req_valid_d0 = cv_int_rd_req_valid; +assign cv_int_rd_req_ready = cv_int_rd_req_ready_d0; +assign cv_int_rd_req_pd_d0[78:0] = cv_int_rd_req_pd[78:0]; +//&Viva width_learning_off; +assign dma_stall_inc = dma_rd_req_vld & !dma_rd_req_rdy; +assign ld2csb_grp0_dma_stall_inc = dma_stall_inc & reg2dp_cmd_interrupt_ptr==0; +assign ld2csb_grp1_dma_stall_inc = dma_stall_inc & reg2dp_cmd_interrupt_ptr==1; +//====================================== +// OBS Signals +//====================================== +//assign obs_bus_bdma_load_cmd = load_cmd; +//assign obs_bus_bdma_load_cmd_en = load_cmd_en; +//assign obs_bus_bdma_load_idle = ld_idle; +//assign obs_bus_bdma_load_ram_switch = is_src_ram_type_switching; +//assign obs_bus_bdma_load_tran_ready = tran_ready; +//assign obs_bus_bdma_load_tran_valid = tran_valid; +//assign obs_bus_bdma_load_ld2st_wr_pvld = ld2st_wr_pvld; +//assign obs_bus_bdma_load_ld2st_wr_prdy = ld2st_wr_prdy; +//assign obs_bus_bdma_load_ld2st_wr_idle = ld2st_wr_idle; +endmodule // NV_NVDLA_BDMA_load +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_rd_req_pd (mc_int_rd_req_valid,mc_int_rd_req_ready) <= dma_rd_req_pd[78:0] (mc_dma_rd_req_vld,mc_dma_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_LOAD_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_req_pd + ,mc_dma_rd_req_vld + ,mc_int_rd_req_ready + ,mc_dma_rd_req_rdy + ,mc_int_rd_req_pd + ,mc_int_rd_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] dma_rd_req_pd; +input mc_dma_rd_req_vld; +input mc_int_rd_req_ready; +output mc_dma_rd_req_rdy; +output [78:0] mc_int_rd_req_pd; +output mc_int_rd_req_valid; +reg mc_dma_rd_req_rdy; +reg [78:0] mc_int_rd_req_pd; +reg mc_int_rd_req_valid; +reg [78:0] p1_pipe_data; +reg [78:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [78:0] p1_skid_data; +reg [78:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_dma_rd_req_vld + or p1_pipe_rand_ready + or dma_rd_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = dma_rd_req_pd[78:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : dma_rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_dma_rd_req_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_dma_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mc_int_rd_req_ready + or p1_pipe_data + ) begin + mc_int_rd_req_valid = p1_pipe_valid; + p1_pipe_ready = mc_int_rd_req_ready; + mc_int_rd_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_rd_req_valid^mc_int_rd_req_ready^mc_dma_rd_req_vld^mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mc_dma_rd_req_vld && !mc_dma_rd_req_rdy), (mc_dma_rd_req_vld), (mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_LOAD_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_rd_req_pd (cv_int_rd_req_valid,cv_int_rd_req_ready) <= dma_rd_req_pd[78:0] (cv_dma_rd_req_vld,cv_dma_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_LOAD_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cv_dma_rd_req_vld + ,cv_int_rd_req_ready + ,dma_rd_req_pd + ,cv_dma_rd_req_rdy + ,cv_int_rd_req_pd + ,cv_int_rd_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cv_dma_rd_req_vld; +input cv_int_rd_req_ready; +input [78:0] dma_rd_req_pd; +output cv_dma_rd_req_rdy; +output [78:0] cv_int_rd_req_pd; +output cv_int_rd_req_valid; +reg cv_dma_rd_req_rdy; +reg [78:0] cv_int_rd_req_pd; +reg cv_int_rd_req_valid; +reg [78:0] p2_pipe_data; +reg [78:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [78:0] p2_skid_data; +reg [78:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + cv_dma_rd_req_vld + or p2_pipe_rand_ready + or dma_rd_req_pd + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = cv_dma_rd_req_vld; + cv_dma_rd_req_rdy = p2_pipe_rand_ready; + p2_pipe_rand_data = dma_rd_req_pd[78:0]; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : cv_dma_rd_req_vld; + cv_dma_rd_req_rdy = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : dma_rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_load_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or cv_dma_rd_req_vld + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && cv_dma_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) skid buffer +always @( + p2_pipe_rand_valid + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_rand_valid && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_rand_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_rand_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_rand_valid + or p2_skid_valid + or p2_pipe_rand_data + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? p2_pipe_rand_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or cv_int_rd_req_ready + or p2_pipe_data + ) begin + cv_int_rd_req_valid = p2_pipe_valid; + p2_pipe_ready = cv_int_rd_req_ready; + cv_int_rd_req_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cv_int_rd_req_valid^cv_int_rd_req_ready^cv_dma_rd_req_vld^cv_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (cv_dma_rd_req_vld && !cv_dma_rd_req_rdy), (cv_dma_rd_req_vld), (cv_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_LOAD_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v new file mode 100644 index 0000000..d673705 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v @@ -0,0 +1,437 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_reg.v +module NV_NVDLA_BDMA_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,nvdla_bdma_cfg_cmd_0_dst_ram_type + ,nvdla_bdma_cfg_cmd_0_src_ram_type + ,nvdla_bdma_cfg_dst_addr_high_0_v8 + ,nvdla_bdma_cfg_dst_addr_low_0_v32 + ,nvdla_bdma_cfg_dst_line_0_stride + ,nvdla_bdma_cfg_dst_surf_0_stride + ,nvdla_bdma_cfg_launch0_0_grp0_launch + ,nvdla_bdma_cfg_launch0_0_grp0_launch_trigger + ,nvdla_bdma_cfg_launch1_0_grp1_launch + ,nvdla_bdma_cfg_launch1_0_grp1_launch_trigger + ,nvdla_bdma_cfg_line_0_size + ,nvdla_bdma_cfg_line_repeat_0_number + ,nvdla_bdma_cfg_op_0_en + ,nvdla_bdma_cfg_op_0_en_trigger + ,nvdla_bdma_cfg_src_addr_high_0_v8 + ,nvdla_bdma_cfg_src_addr_low_0_v32 + ,nvdla_bdma_cfg_src_line_0_stride + ,nvdla_bdma_cfg_src_surf_0_stride + ,nvdla_bdma_cfg_status_0_stall_count_en + ,nvdla_bdma_cfg_surf_repeat_0_number + ,nvdla_bdma_status_0_free_slot + ,nvdla_bdma_status_0_grp0_busy + ,nvdla_bdma_status_0_grp1_busy + ,nvdla_bdma_status_0_idle + ,nvdla_bdma_status_grp0_read_stall_0_count + ,nvdla_bdma_status_grp0_write_stall_0_count + ,nvdla_bdma_status_grp1_read_stall_0_count + ,nvdla_bdma_status_grp1_write_stall_0_count + ); +wire [31:0] nvdla_bdma_cfg_cmd_0_out; +wire [31:0] nvdla_bdma_cfg_dst_addr_high_0_out; +wire [31:0] nvdla_bdma_cfg_dst_addr_low_0_out; +wire [31:0] nvdla_bdma_cfg_dst_line_0_out; +wire [31:0] nvdla_bdma_cfg_dst_surf_0_out; +wire [31:0] nvdla_bdma_cfg_launch0_0_out; +wire [31:0] nvdla_bdma_cfg_launch1_0_out; +wire [31:0] nvdla_bdma_cfg_line_0_out; +wire [31:0] nvdla_bdma_cfg_line_repeat_0_out; +wire [31:0] nvdla_bdma_cfg_op_0_out; +wire [31:0] nvdla_bdma_cfg_src_addr_high_0_out; +wire [31:0] nvdla_bdma_cfg_src_addr_low_0_out; +wire [31:0] nvdla_bdma_cfg_src_line_0_out; +wire [31:0] nvdla_bdma_cfg_src_surf_0_out; +wire [31:0] nvdla_bdma_cfg_status_0_out; +wire [31:0] nvdla_bdma_cfg_surf_repeat_0_out; +wire [31:0] nvdla_bdma_status_0_out; +wire [31:0] nvdla_bdma_status_grp0_read_stall_0_out; +wire [31:0] nvdla_bdma_status_grp0_write_stall_0_out; +wire [31:0] nvdla_bdma_status_grp1_read_stall_0_out; +wire [31:0] nvdla_bdma_status_grp1_write_stall_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output nvdla_bdma_cfg_cmd_0_dst_ram_type; +output nvdla_bdma_cfg_cmd_0_src_ram_type; +output [31:0] nvdla_bdma_cfg_dst_addr_high_0_v8; +output [26:0] nvdla_bdma_cfg_dst_addr_low_0_v32; +output [26:0] nvdla_bdma_cfg_dst_line_0_stride; +output [26:0] nvdla_bdma_cfg_dst_surf_0_stride; +output nvdla_bdma_cfg_launch0_0_grp0_launch; +output nvdla_bdma_cfg_launch0_0_grp0_launch_trigger; +output nvdla_bdma_cfg_launch1_0_grp1_launch; +output nvdla_bdma_cfg_launch1_0_grp1_launch_trigger; +output [12:0] nvdla_bdma_cfg_line_0_size; +output [23:0] nvdla_bdma_cfg_line_repeat_0_number; +output nvdla_bdma_cfg_op_0_en; +output nvdla_bdma_cfg_op_0_en_trigger; +output [31:0] nvdla_bdma_cfg_src_addr_high_0_v8; +output [26:0] nvdla_bdma_cfg_src_addr_low_0_v32; +output [26:0] nvdla_bdma_cfg_src_line_0_stride; +output [26:0] nvdla_bdma_cfg_src_surf_0_stride; +output nvdla_bdma_cfg_status_0_stall_count_en; +output [23:0] nvdla_bdma_cfg_surf_repeat_0_number; +// Read-only register inputs +input [7:0] nvdla_bdma_status_0_free_slot; +input nvdla_bdma_status_0_grp0_busy; +input nvdla_bdma_status_0_grp1_busy; +input nvdla_bdma_status_0_idle; +input [31:0] nvdla_bdma_status_grp0_read_stall_0_count; +input [31:0] nvdla_bdma_status_grp0_write_stall_0_count; +input [31:0] nvdla_bdma_status_grp1_read_stall_0_count; +input [31:0] nvdla_bdma_status_grp1_write_stall_0_count; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg nvdla_bdma_cfg_cmd_0_dst_ram_type; +reg nvdla_bdma_cfg_cmd_0_src_ram_type; +reg [31:0] nvdla_bdma_cfg_dst_addr_high_0_v8; +reg [26:0] nvdla_bdma_cfg_dst_addr_low_0_v32; +reg [26:0] nvdla_bdma_cfg_dst_line_0_stride; +reg [26:0] nvdla_bdma_cfg_dst_surf_0_stride; +reg nvdla_bdma_cfg_launch0_0_grp0_launch; +reg nvdla_bdma_cfg_launch1_0_grp1_launch; +reg [12:0] nvdla_bdma_cfg_line_0_size; +reg [23:0] nvdla_bdma_cfg_line_repeat_0_number; +reg nvdla_bdma_cfg_op_0_en; +reg [31:0] nvdla_bdma_cfg_src_addr_high_0_v8; +reg [26:0] nvdla_bdma_cfg_src_addr_low_0_v32; +reg [26:0] nvdla_bdma_cfg_src_line_0_stride; +reg [26:0] nvdla_bdma_cfg_src_surf_0_stride; +reg nvdla_bdma_cfg_status_0_stall_count_en; +reg [23:0] nvdla_bdma_cfg_surf_repeat_0_number; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_bdma_cfg_cmd_0_wren = (reg_offset_wr == (32'h4014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_addr_high_0_wren = (reg_offset_wr == (32'h400c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_addr_low_0_wren = (reg_offset_wr == (32'h4008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_line_0_wren = (reg_offset_wr == (32'h4020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_surf_0_wren = (reg_offset_wr == (32'h402c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_launch0_0_wren = (reg_offset_wr == (32'h4034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_launch1_0_wren = (reg_offset_wr == (32'h4038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_line_0_wren = (reg_offset_wr == (32'h4010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_line_repeat_0_wren = (reg_offset_wr == (32'h4018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_op_0_wren = (reg_offset_wr == (32'h4030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_addr_high_0_wren = (reg_offset_wr == (32'h4004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_addr_low_0_wren = (reg_offset_wr == (32'h4000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_line_0_wren = (reg_offset_wr == (32'h401c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_surf_0_wren = (reg_offset_wr == (32'h4028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_status_0_wren = (reg_offset_wr == (32'h403c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_surf_repeat_0_wren = (reg_offset_wr == (32'h4024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_0_wren = (reg_offset_wr == (32'h4040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp0_read_stall_0_wren = (reg_offset_wr == (32'h4044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp0_write_stall_0_wren = (reg_offset_wr == (32'h4048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp1_read_stall_0_wren = (reg_offset_wr == (32'h404c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp1_write_stall_0_wren = (reg_offset_wr == (32'h4050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_bdma_cfg_cmd_0_out[31:0] = { 30'b0, nvdla_bdma_cfg_cmd_0_dst_ram_type, nvdla_bdma_cfg_cmd_0_src_ram_type }; +assign nvdla_bdma_cfg_dst_addr_high_0_out[31:0] = { nvdla_bdma_cfg_dst_addr_high_0_v8 }; +assign nvdla_bdma_cfg_dst_addr_low_0_out[31:0] = { nvdla_bdma_cfg_dst_addr_low_0_v32, 5'b0 }; +assign nvdla_bdma_cfg_dst_line_0_out[31:0] = { nvdla_bdma_cfg_dst_line_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_dst_surf_0_out[31:0] = { nvdla_bdma_cfg_dst_surf_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_launch0_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_launch0_0_grp0_launch }; +assign nvdla_bdma_cfg_launch1_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_launch1_0_grp1_launch }; +assign nvdla_bdma_cfg_line_0_out[31:0] = { 19'b0, nvdla_bdma_cfg_line_0_size }; +assign nvdla_bdma_cfg_line_repeat_0_out[31:0] = { 8'b0, nvdla_bdma_cfg_line_repeat_0_number }; +assign nvdla_bdma_cfg_op_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_op_0_en }; +assign nvdla_bdma_cfg_src_addr_high_0_out[31:0] = { nvdla_bdma_cfg_src_addr_high_0_v8 }; +assign nvdla_bdma_cfg_src_addr_low_0_out[31:0] = { nvdla_bdma_cfg_src_addr_low_0_v32, 5'b0 }; +assign nvdla_bdma_cfg_src_line_0_out[31:0] = { nvdla_bdma_cfg_src_line_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_src_surf_0_out[31:0] = { nvdla_bdma_cfg_src_surf_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_status_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_status_0_stall_count_en }; +assign nvdla_bdma_cfg_surf_repeat_0_out[31:0] = { 8'b0, nvdla_bdma_cfg_surf_repeat_0_number }; +assign nvdla_bdma_status_0_out[31:0] = { 21'b0, nvdla_bdma_status_0_grp1_busy, nvdla_bdma_status_0_grp0_busy, nvdla_bdma_status_0_idle, nvdla_bdma_status_0_free_slot }; +assign nvdla_bdma_status_grp0_read_stall_0_out[31:0] = { nvdla_bdma_status_grp0_read_stall_0_count }; +assign nvdla_bdma_status_grp0_write_stall_0_out[31:0] = { nvdla_bdma_status_grp0_write_stall_0_count }; +assign nvdla_bdma_status_grp1_read_stall_0_out[31:0] = { nvdla_bdma_status_grp1_read_stall_0_count }; +assign nvdla_bdma_status_grp1_write_stall_0_out[31:0] = { nvdla_bdma_status_grp1_write_stall_0_count }; +assign nvdla_bdma_cfg_launch0_0_grp0_launch_trigger = nvdla_bdma_cfg_launch0_0_wren; //(W563) +assign nvdla_bdma_cfg_launch1_0_grp1_launch_trigger = nvdla_bdma_cfg_launch1_0_wren; //(W563) +assign nvdla_bdma_cfg_op_0_en_trigger = nvdla_bdma_cfg_op_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_bdma_cfg_cmd_0_out + or nvdla_bdma_cfg_dst_addr_high_0_out + or nvdla_bdma_cfg_dst_addr_low_0_out + or nvdla_bdma_cfg_dst_line_0_out + or nvdla_bdma_cfg_dst_surf_0_out + or nvdla_bdma_cfg_launch0_0_out + or nvdla_bdma_cfg_launch1_0_out + or nvdla_bdma_cfg_line_0_out + or nvdla_bdma_cfg_line_repeat_0_out + or nvdla_bdma_cfg_op_0_out + or nvdla_bdma_cfg_src_addr_high_0_out + or nvdla_bdma_cfg_src_addr_low_0_out + or nvdla_bdma_cfg_src_line_0_out + or nvdla_bdma_cfg_src_surf_0_out + or nvdla_bdma_cfg_status_0_out + or nvdla_bdma_cfg_surf_repeat_0_out + or nvdla_bdma_status_0_out + or nvdla_bdma_status_grp0_read_stall_0_out + or nvdla_bdma_status_grp0_write_stall_0_out + or nvdla_bdma_status_grp1_read_stall_0_out + or nvdla_bdma_status_grp1_write_stall_0_out + ) begin + case (reg_offset_rd_int) + (32'h4014 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_cmd_0_out ; + end + (32'h400c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_addr_high_0_out ; + end + (32'h4008 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_addr_low_0_out ; + end + (32'h4020 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_line_0_out ; + end + (32'h402c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_surf_0_out ; + end + (32'h4034 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_launch0_0_out ; + end + (32'h4038 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_launch1_0_out ; + end + (32'h4010 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_line_0_out ; + end + (32'h4018 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_line_repeat_0_out ; + end + (32'h4030 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_op_0_out ; + end + (32'h4004 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_addr_high_0_out ; + end + (32'h4000 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_addr_low_0_out ; + end + (32'h401c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_line_0_out ; + end + (32'h4028 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_surf_0_out ; + end + (32'h403c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_status_0_out ; + end + (32'h4024 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_surf_repeat_0_out ; + end + (32'h4040 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_0_out ; + end + (32'h4044 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp0_read_stall_0_out ; + end + (32'h4048 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp0_write_stall_0_out ; + end + (32'h404c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp1_read_stall_0_out ; + end + (32'h4050 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp1_write_stall_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nvdla_bdma_cfg_cmd_0_dst_ram_type <= 1'b0; + nvdla_bdma_cfg_cmd_0_src_ram_type <= 1'b0; + nvdla_bdma_cfg_dst_addr_high_0_v8[31:0] <= 32'b00000000000000000000000000000000; + nvdla_bdma_cfg_dst_addr_low_0_v32[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_dst_line_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_dst_surf_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_launch0_0_grp0_launch <= 1'b0; + nvdla_bdma_cfg_launch1_0_grp1_launch <= 1'b0; + nvdla_bdma_cfg_line_0_size[12:0] <= 13'b0000000000000; + nvdla_bdma_cfg_line_repeat_0_number[23:0] <= 24'b000000000000000000000000; + nvdla_bdma_cfg_op_0_en <= 1'b0; + nvdla_bdma_cfg_src_addr_high_0_v8[31:0] <= 32'b00000000000000000000000000000000; + nvdla_bdma_cfg_src_addr_low_0_v32[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_src_line_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_src_surf_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_status_0_stall_count_en <= 1'b0; + nvdla_bdma_cfg_surf_repeat_0_number[23:0] <= 24'b000000000000000000000000; + end else begin +// Register: NVDLA_BDMA_CFG_CMD_0 Field: dst_ram_type + if (nvdla_bdma_cfg_cmd_0_wren) begin + nvdla_bdma_cfg_cmd_0_dst_ram_type <= reg_wr_data[1]; + end +// Register: NVDLA_BDMA_CFG_CMD_0 Field: src_ram_type + if (nvdla_bdma_cfg_cmd_0_wren) begin + nvdla_bdma_cfg_cmd_0_src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_DST_ADDR_HIGH_0 Field: v8 + if (nvdla_bdma_cfg_dst_addr_high_0_wren) begin + nvdla_bdma_cfg_dst_addr_high_0_v8[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_BDMA_CFG_DST_ADDR_LOW_0 Field: v32 + if (nvdla_bdma_cfg_dst_addr_low_0_wren) begin + nvdla_bdma_cfg_dst_addr_low_0_v32[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_DST_LINE_0 Field: stride + if (nvdla_bdma_cfg_dst_line_0_wren) begin + nvdla_bdma_cfg_dst_line_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_DST_SURF_0 Field: stride + if (nvdla_bdma_cfg_dst_surf_0_wren) begin + nvdla_bdma_cfg_dst_surf_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_LAUNCH0_0 Field: grp0_launch + if (nvdla_bdma_cfg_launch0_0_wren) begin + nvdla_bdma_cfg_launch0_0_grp0_launch <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_LAUNCH1_0 Field: grp1_launch + if (nvdla_bdma_cfg_launch1_0_wren) begin + nvdla_bdma_cfg_launch1_0_grp1_launch <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_LINE_0 Field: size + if (nvdla_bdma_cfg_line_0_wren) begin + nvdla_bdma_cfg_line_0_size[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_BDMA_CFG_LINE_REPEAT_0 Field: number + if (nvdla_bdma_cfg_line_repeat_0_wren) begin + nvdla_bdma_cfg_line_repeat_0_number[23:0] <= reg_wr_data[23:0]; + end +// Register: NVDLA_BDMA_CFG_OP_0 Field: en + if (nvdla_bdma_cfg_op_0_wren) begin + nvdla_bdma_cfg_op_0_en <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_SRC_ADDR_HIGH_0 Field: v8 + if (nvdla_bdma_cfg_src_addr_high_0_wren) begin + nvdla_bdma_cfg_src_addr_high_0_v8[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_BDMA_CFG_SRC_ADDR_LOW_0 Field: v32 + if (nvdla_bdma_cfg_src_addr_low_0_wren) begin + nvdla_bdma_cfg_src_addr_low_0_v32[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_SRC_LINE_0 Field: stride + if (nvdla_bdma_cfg_src_line_0_wren) begin + nvdla_bdma_cfg_src_line_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_SRC_SURF_0 Field: stride + if (nvdla_bdma_cfg_src_surf_0_wren) begin + nvdla_bdma_cfg_src_surf_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_STATUS_0 Field: stall_count_en + if (nvdla_bdma_cfg_status_0_wren) begin + nvdla_bdma_cfg_status_0_stall_count_en <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_SURF_REPEAT_0 Field: number + if (nvdla_bdma_cfg_surf_repeat_0_wren) begin + nvdla_bdma_cfg_surf_repeat_0_number[23:0] <= reg_wr_data[23:0]; + end +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::free_slot +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::grp0_busy +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::grp1_busy +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::idle +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP0_READ_STALL_0::count +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP0_WRITE_STALL_0::count +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP1_READ_STALL_0::count +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP1_WRITE_STALL_0::count + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h4014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_CMD_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_cmd_0_out, nvdla_bdma_cfg_cmd_0_out); + (32'h400c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_addr_high_0_out, nvdla_bdma_cfg_dst_addr_high_0_out); + (32'h4008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_addr_low_0_out, nvdla_bdma_cfg_dst_addr_low_0_out); + (32'h4020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_LINE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_line_0_out, nvdla_bdma_cfg_dst_line_0_out); + (32'h402c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_SURF_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_surf_0_out, nvdla_bdma_cfg_dst_surf_0_out); + (32'h4034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LAUNCH0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_launch0_0_out, nvdla_bdma_cfg_launch0_0_out); + (32'h4038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LAUNCH1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_launch1_0_out, nvdla_bdma_cfg_launch1_0_out); + (32'h4010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LINE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_line_0_out, nvdla_bdma_cfg_line_0_out); + (32'h4018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LINE_REPEAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_line_repeat_0_out, nvdla_bdma_cfg_line_repeat_0_out); + (32'h4030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_OP_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_op_0_out, nvdla_bdma_cfg_op_0_out); + (32'h4004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_addr_high_0_out, nvdla_bdma_cfg_src_addr_high_0_out); + (32'h4000 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_addr_low_0_out, nvdla_bdma_cfg_src_addr_low_0_out); + (32'h401c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_LINE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_line_0_out, nvdla_bdma_cfg_src_line_0_out); + (32'h4028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_SURF_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_surf_0_out, nvdla_bdma_cfg_src_surf_0_out); + (32'h403c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_STATUS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_status_0_out, nvdla_bdma_cfg_status_0_out); + (32'h4024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SURF_REPEAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_surf_repeat_0_out, nvdla_bdma_cfg_surf_repeat_0_out); + (32'h4040 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h4044 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP0_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h4048 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP0_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h404c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP1_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h4050 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP1_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_BDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v.vcp new file mode 100644 index 0000000..d673705 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v.vcp @@ -0,0 +1,437 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_reg.v +module NV_NVDLA_BDMA_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,nvdla_bdma_cfg_cmd_0_dst_ram_type + ,nvdla_bdma_cfg_cmd_0_src_ram_type + ,nvdla_bdma_cfg_dst_addr_high_0_v8 + ,nvdla_bdma_cfg_dst_addr_low_0_v32 + ,nvdla_bdma_cfg_dst_line_0_stride + ,nvdla_bdma_cfg_dst_surf_0_stride + ,nvdla_bdma_cfg_launch0_0_grp0_launch + ,nvdla_bdma_cfg_launch0_0_grp0_launch_trigger + ,nvdla_bdma_cfg_launch1_0_grp1_launch + ,nvdla_bdma_cfg_launch1_0_grp1_launch_trigger + ,nvdla_bdma_cfg_line_0_size + ,nvdla_bdma_cfg_line_repeat_0_number + ,nvdla_bdma_cfg_op_0_en + ,nvdla_bdma_cfg_op_0_en_trigger + ,nvdla_bdma_cfg_src_addr_high_0_v8 + ,nvdla_bdma_cfg_src_addr_low_0_v32 + ,nvdla_bdma_cfg_src_line_0_stride + ,nvdla_bdma_cfg_src_surf_0_stride + ,nvdla_bdma_cfg_status_0_stall_count_en + ,nvdla_bdma_cfg_surf_repeat_0_number + ,nvdla_bdma_status_0_free_slot + ,nvdla_bdma_status_0_grp0_busy + ,nvdla_bdma_status_0_grp1_busy + ,nvdla_bdma_status_0_idle + ,nvdla_bdma_status_grp0_read_stall_0_count + ,nvdla_bdma_status_grp0_write_stall_0_count + ,nvdla_bdma_status_grp1_read_stall_0_count + ,nvdla_bdma_status_grp1_write_stall_0_count + ); +wire [31:0] nvdla_bdma_cfg_cmd_0_out; +wire [31:0] nvdla_bdma_cfg_dst_addr_high_0_out; +wire [31:0] nvdla_bdma_cfg_dst_addr_low_0_out; +wire [31:0] nvdla_bdma_cfg_dst_line_0_out; +wire [31:0] nvdla_bdma_cfg_dst_surf_0_out; +wire [31:0] nvdla_bdma_cfg_launch0_0_out; +wire [31:0] nvdla_bdma_cfg_launch1_0_out; +wire [31:0] nvdla_bdma_cfg_line_0_out; +wire [31:0] nvdla_bdma_cfg_line_repeat_0_out; +wire [31:0] nvdla_bdma_cfg_op_0_out; +wire [31:0] nvdla_bdma_cfg_src_addr_high_0_out; +wire [31:0] nvdla_bdma_cfg_src_addr_low_0_out; +wire [31:0] nvdla_bdma_cfg_src_line_0_out; +wire [31:0] nvdla_bdma_cfg_src_surf_0_out; +wire [31:0] nvdla_bdma_cfg_status_0_out; +wire [31:0] nvdla_bdma_cfg_surf_repeat_0_out; +wire [31:0] nvdla_bdma_status_0_out; +wire [31:0] nvdla_bdma_status_grp0_read_stall_0_out; +wire [31:0] nvdla_bdma_status_grp0_write_stall_0_out; +wire [31:0] nvdla_bdma_status_grp1_read_stall_0_out; +wire [31:0] nvdla_bdma_status_grp1_write_stall_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output nvdla_bdma_cfg_cmd_0_dst_ram_type; +output nvdla_bdma_cfg_cmd_0_src_ram_type; +output [31:0] nvdla_bdma_cfg_dst_addr_high_0_v8; +output [26:0] nvdla_bdma_cfg_dst_addr_low_0_v32; +output [26:0] nvdla_bdma_cfg_dst_line_0_stride; +output [26:0] nvdla_bdma_cfg_dst_surf_0_stride; +output nvdla_bdma_cfg_launch0_0_grp0_launch; +output nvdla_bdma_cfg_launch0_0_grp0_launch_trigger; +output nvdla_bdma_cfg_launch1_0_grp1_launch; +output nvdla_bdma_cfg_launch1_0_grp1_launch_trigger; +output [12:0] nvdla_bdma_cfg_line_0_size; +output [23:0] nvdla_bdma_cfg_line_repeat_0_number; +output nvdla_bdma_cfg_op_0_en; +output nvdla_bdma_cfg_op_0_en_trigger; +output [31:0] nvdla_bdma_cfg_src_addr_high_0_v8; +output [26:0] nvdla_bdma_cfg_src_addr_low_0_v32; +output [26:0] nvdla_bdma_cfg_src_line_0_stride; +output [26:0] nvdla_bdma_cfg_src_surf_0_stride; +output nvdla_bdma_cfg_status_0_stall_count_en; +output [23:0] nvdla_bdma_cfg_surf_repeat_0_number; +// Read-only register inputs +input [7:0] nvdla_bdma_status_0_free_slot; +input nvdla_bdma_status_0_grp0_busy; +input nvdla_bdma_status_0_grp1_busy; +input nvdla_bdma_status_0_idle; +input [31:0] nvdla_bdma_status_grp0_read_stall_0_count; +input [31:0] nvdla_bdma_status_grp0_write_stall_0_count; +input [31:0] nvdla_bdma_status_grp1_read_stall_0_count; +input [31:0] nvdla_bdma_status_grp1_write_stall_0_count; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg nvdla_bdma_cfg_cmd_0_dst_ram_type; +reg nvdla_bdma_cfg_cmd_0_src_ram_type; +reg [31:0] nvdla_bdma_cfg_dst_addr_high_0_v8; +reg [26:0] nvdla_bdma_cfg_dst_addr_low_0_v32; +reg [26:0] nvdla_bdma_cfg_dst_line_0_stride; +reg [26:0] nvdla_bdma_cfg_dst_surf_0_stride; +reg nvdla_bdma_cfg_launch0_0_grp0_launch; +reg nvdla_bdma_cfg_launch1_0_grp1_launch; +reg [12:0] nvdla_bdma_cfg_line_0_size; +reg [23:0] nvdla_bdma_cfg_line_repeat_0_number; +reg nvdla_bdma_cfg_op_0_en; +reg [31:0] nvdla_bdma_cfg_src_addr_high_0_v8; +reg [26:0] nvdla_bdma_cfg_src_addr_low_0_v32; +reg [26:0] nvdla_bdma_cfg_src_line_0_stride; +reg [26:0] nvdla_bdma_cfg_src_surf_0_stride; +reg nvdla_bdma_cfg_status_0_stall_count_en; +reg [23:0] nvdla_bdma_cfg_surf_repeat_0_number; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_bdma_cfg_cmd_0_wren = (reg_offset_wr == (32'h4014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_addr_high_0_wren = (reg_offset_wr == (32'h400c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_addr_low_0_wren = (reg_offset_wr == (32'h4008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_line_0_wren = (reg_offset_wr == (32'h4020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_dst_surf_0_wren = (reg_offset_wr == (32'h402c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_launch0_0_wren = (reg_offset_wr == (32'h4034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_launch1_0_wren = (reg_offset_wr == (32'h4038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_line_0_wren = (reg_offset_wr == (32'h4010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_line_repeat_0_wren = (reg_offset_wr == (32'h4018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_op_0_wren = (reg_offset_wr == (32'h4030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_addr_high_0_wren = (reg_offset_wr == (32'h4004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_addr_low_0_wren = (reg_offset_wr == (32'h4000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_line_0_wren = (reg_offset_wr == (32'h401c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_src_surf_0_wren = (reg_offset_wr == (32'h4028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_status_0_wren = (reg_offset_wr == (32'h403c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_cfg_surf_repeat_0_wren = (reg_offset_wr == (32'h4024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_0_wren = (reg_offset_wr == (32'h4040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp0_read_stall_0_wren = (reg_offset_wr == (32'h4044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp0_write_stall_0_wren = (reg_offset_wr == (32'h4048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp1_read_stall_0_wren = (reg_offset_wr == (32'h404c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_bdma_status_grp1_write_stall_0_wren = (reg_offset_wr == (32'h4050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_bdma_cfg_cmd_0_out[31:0] = { 30'b0, nvdla_bdma_cfg_cmd_0_dst_ram_type, nvdla_bdma_cfg_cmd_0_src_ram_type }; +assign nvdla_bdma_cfg_dst_addr_high_0_out[31:0] = { nvdla_bdma_cfg_dst_addr_high_0_v8 }; +assign nvdla_bdma_cfg_dst_addr_low_0_out[31:0] = { nvdla_bdma_cfg_dst_addr_low_0_v32, 5'b0 }; +assign nvdla_bdma_cfg_dst_line_0_out[31:0] = { nvdla_bdma_cfg_dst_line_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_dst_surf_0_out[31:0] = { nvdla_bdma_cfg_dst_surf_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_launch0_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_launch0_0_grp0_launch }; +assign nvdla_bdma_cfg_launch1_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_launch1_0_grp1_launch }; +assign nvdla_bdma_cfg_line_0_out[31:0] = { 19'b0, nvdla_bdma_cfg_line_0_size }; +assign nvdla_bdma_cfg_line_repeat_0_out[31:0] = { 8'b0, nvdla_bdma_cfg_line_repeat_0_number }; +assign nvdla_bdma_cfg_op_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_op_0_en }; +assign nvdla_bdma_cfg_src_addr_high_0_out[31:0] = { nvdla_bdma_cfg_src_addr_high_0_v8 }; +assign nvdla_bdma_cfg_src_addr_low_0_out[31:0] = { nvdla_bdma_cfg_src_addr_low_0_v32, 5'b0 }; +assign nvdla_bdma_cfg_src_line_0_out[31:0] = { nvdla_bdma_cfg_src_line_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_src_surf_0_out[31:0] = { nvdla_bdma_cfg_src_surf_0_stride, 5'b0 }; +assign nvdla_bdma_cfg_status_0_out[31:0] = { 31'b0, nvdla_bdma_cfg_status_0_stall_count_en }; +assign nvdla_bdma_cfg_surf_repeat_0_out[31:0] = { 8'b0, nvdla_bdma_cfg_surf_repeat_0_number }; +assign nvdla_bdma_status_0_out[31:0] = { 21'b0, nvdla_bdma_status_0_grp1_busy, nvdla_bdma_status_0_grp0_busy, nvdla_bdma_status_0_idle, nvdla_bdma_status_0_free_slot }; +assign nvdla_bdma_status_grp0_read_stall_0_out[31:0] = { nvdla_bdma_status_grp0_read_stall_0_count }; +assign nvdla_bdma_status_grp0_write_stall_0_out[31:0] = { nvdla_bdma_status_grp0_write_stall_0_count }; +assign nvdla_bdma_status_grp1_read_stall_0_out[31:0] = { nvdla_bdma_status_grp1_read_stall_0_count }; +assign nvdla_bdma_status_grp1_write_stall_0_out[31:0] = { nvdla_bdma_status_grp1_write_stall_0_count }; +assign nvdla_bdma_cfg_launch0_0_grp0_launch_trigger = nvdla_bdma_cfg_launch0_0_wren; //(W563) +assign nvdla_bdma_cfg_launch1_0_grp1_launch_trigger = nvdla_bdma_cfg_launch1_0_wren; //(W563) +assign nvdla_bdma_cfg_op_0_en_trigger = nvdla_bdma_cfg_op_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_bdma_cfg_cmd_0_out + or nvdla_bdma_cfg_dst_addr_high_0_out + or nvdla_bdma_cfg_dst_addr_low_0_out + or nvdla_bdma_cfg_dst_line_0_out + or nvdla_bdma_cfg_dst_surf_0_out + or nvdla_bdma_cfg_launch0_0_out + or nvdla_bdma_cfg_launch1_0_out + or nvdla_bdma_cfg_line_0_out + or nvdla_bdma_cfg_line_repeat_0_out + or nvdla_bdma_cfg_op_0_out + or nvdla_bdma_cfg_src_addr_high_0_out + or nvdla_bdma_cfg_src_addr_low_0_out + or nvdla_bdma_cfg_src_line_0_out + or nvdla_bdma_cfg_src_surf_0_out + or nvdla_bdma_cfg_status_0_out + or nvdla_bdma_cfg_surf_repeat_0_out + or nvdla_bdma_status_0_out + or nvdla_bdma_status_grp0_read_stall_0_out + or nvdla_bdma_status_grp0_write_stall_0_out + or nvdla_bdma_status_grp1_read_stall_0_out + or nvdla_bdma_status_grp1_write_stall_0_out + ) begin + case (reg_offset_rd_int) + (32'h4014 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_cmd_0_out ; + end + (32'h400c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_addr_high_0_out ; + end + (32'h4008 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_addr_low_0_out ; + end + (32'h4020 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_line_0_out ; + end + (32'h402c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_dst_surf_0_out ; + end + (32'h4034 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_launch0_0_out ; + end + (32'h4038 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_launch1_0_out ; + end + (32'h4010 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_line_0_out ; + end + (32'h4018 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_line_repeat_0_out ; + end + (32'h4030 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_op_0_out ; + end + (32'h4004 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_addr_high_0_out ; + end + (32'h4000 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_addr_low_0_out ; + end + (32'h401c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_line_0_out ; + end + (32'h4028 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_src_surf_0_out ; + end + (32'h403c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_status_0_out ; + end + (32'h4024 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_cfg_surf_repeat_0_out ; + end + (32'h4040 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_0_out ; + end + (32'h4044 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp0_read_stall_0_out ; + end + (32'h4048 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp0_write_stall_0_out ; + end + (32'h404c & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp1_read_stall_0_out ; + end + (32'h4050 & 32'h00000fff): begin + reg_rd_data = nvdla_bdma_status_grp1_write_stall_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nvdla_bdma_cfg_cmd_0_dst_ram_type <= 1'b0; + nvdla_bdma_cfg_cmd_0_src_ram_type <= 1'b0; + nvdla_bdma_cfg_dst_addr_high_0_v8[31:0] <= 32'b00000000000000000000000000000000; + nvdla_bdma_cfg_dst_addr_low_0_v32[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_dst_line_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_dst_surf_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_launch0_0_grp0_launch <= 1'b0; + nvdla_bdma_cfg_launch1_0_grp1_launch <= 1'b0; + nvdla_bdma_cfg_line_0_size[12:0] <= 13'b0000000000000; + nvdla_bdma_cfg_line_repeat_0_number[23:0] <= 24'b000000000000000000000000; + nvdla_bdma_cfg_op_0_en <= 1'b0; + nvdla_bdma_cfg_src_addr_high_0_v8[31:0] <= 32'b00000000000000000000000000000000; + nvdla_bdma_cfg_src_addr_low_0_v32[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_src_line_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_src_surf_0_stride[26:0] <= 27'b000000000000000000000000000; + nvdla_bdma_cfg_status_0_stall_count_en <= 1'b0; + nvdla_bdma_cfg_surf_repeat_0_number[23:0] <= 24'b000000000000000000000000; + end else begin +// Register: NVDLA_BDMA_CFG_CMD_0 Field: dst_ram_type + if (nvdla_bdma_cfg_cmd_0_wren) begin + nvdla_bdma_cfg_cmd_0_dst_ram_type <= reg_wr_data[1]; + end +// Register: NVDLA_BDMA_CFG_CMD_0 Field: src_ram_type + if (nvdla_bdma_cfg_cmd_0_wren) begin + nvdla_bdma_cfg_cmd_0_src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_DST_ADDR_HIGH_0 Field: v8 + if (nvdla_bdma_cfg_dst_addr_high_0_wren) begin + nvdla_bdma_cfg_dst_addr_high_0_v8[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_BDMA_CFG_DST_ADDR_LOW_0 Field: v32 + if (nvdla_bdma_cfg_dst_addr_low_0_wren) begin + nvdla_bdma_cfg_dst_addr_low_0_v32[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_DST_LINE_0 Field: stride + if (nvdla_bdma_cfg_dst_line_0_wren) begin + nvdla_bdma_cfg_dst_line_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_DST_SURF_0 Field: stride + if (nvdla_bdma_cfg_dst_surf_0_wren) begin + nvdla_bdma_cfg_dst_surf_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_LAUNCH0_0 Field: grp0_launch + if (nvdla_bdma_cfg_launch0_0_wren) begin + nvdla_bdma_cfg_launch0_0_grp0_launch <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_LAUNCH1_0 Field: grp1_launch + if (nvdla_bdma_cfg_launch1_0_wren) begin + nvdla_bdma_cfg_launch1_0_grp1_launch <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_LINE_0 Field: size + if (nvdla_bdma_cfg_line_0_wren) begin + nvdla_bdma_cfg_line_0_size[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_BDMA_CFG_LINE_REPEAT_0 Field: number + if (nvdla_bdma_cfg_line_repeat_0_wren) begin + nvdla_bdma_cfg_line_repeat_0_number[23:0] <= reg_wr_data[23:0]; + end +// Register: NVDLA_BDMA_CFG_OP_0 Field: en + if (nvdla_bdma_cfg_op_0_wren) begin + nvdla_bdma_cfg_op_0_en <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_SRC_ADDR_HIGH_0 Field: v8 + if (nvdla_bdma_cfg_src_addr_high_0_wren) begin + nvdla_bdma_cfg_src_addr_high_0_v8[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_BDMA_CFG_SRC_ADDR_LOW_0 Field: v32 + if (nvdla_bdma_cfg_src_addr_low_0_wren) begin + nvdla_bdma_cfg_src_addr_low_0_v32[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_SRC_LINE_0 Field: stride + if (nvdla_bdma_cfg_src_line_0_wren) begin + nvdla_bdma_cfg_src_line_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_SRC_SURF_0 Field: stride + if (nvdla_bdma_cfg_src_surf_0_wren) begin + nvdla_bdma_cfg_src_surf_0_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_BDMA_CFG_STATUS_0 Field: stall_count_en + if (nvdla_bdma_cfg_status_0_wren) begin + nvdla_bdma_cfg_status_0_stall_count_en <= reg_wr_data[0]; + end +// Register: NVDLA_BDMA_CFG_SURF_REPEAT_0 Field: number + if (nvdla_bdma_cfg_surf_repeat_0_wren) begin + nvdla_bdma_cfg_surf_repeat_0_number[23:0] <= reg_wr_data[23:0]; + end +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::free_slot +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::grp0_busy +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::grp1_busy +// Not generating flops for read-only field NVDLA_BDMA_STATUS_0::idle +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP0_READ_STALL_0::count +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP0_WRITE_STALL_0::count +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP1_READ_STALL_0::count +// Not generating flops for read-only field NVDLA_BDMA_STATUS_GRP1_WRITE_STALL_0::count + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h4014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_CMD_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_cmd_0_out, nvdla_bdma_cfg_cmd_0_out); + (32'h400c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_addr_high_0_out, nvdla_bdma_cfg_dst_addr_high_0_out); + (32'h4008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_addr_low_0_out, nvdla_bdma_cfg_dst_addr_low_0_out); + (32'h4020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_LINE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_line_0_out, nvdla_bdma_cfg_dst_line_0_out); + (32'h402c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_DST_SURF_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_dst_surf_0_out, nvdla_bdma_cfg_dst_surf_0_out); + (32'h4034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LAUNCH0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_launch0_0_out, nvdla_bdma_cfg_launch0_0_out); + (32'h4038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LAUNCH1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_launch1_0_out, nvdla_bdma_cfg_launch1_0_out); + (32'h4010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LINE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_line_0_out, nvdla_bdma_cfg_line_0_out); + (32'h4018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_LINE_REPEAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_line_repeat_0_out, nvdla_bdma_cfg_line_repeat_0_out); + (32'h4030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_OP_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_op_0_out, nvdla_bdma_cfg_op_0_out); + (32'h4004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_addr_high_0_out, nvdla_bdma_cfg_src_addr_high_0_out); + (32'h4000 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_addr_low_0_out, nvdla_bdma_cfg_src_addr_low_0_out); + (32'h401c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_LINE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_line_0_out, nvdla_bdma_cfg_src_line_0_out); + (32'h4028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SRC_SURF_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_src_surf_0_out, nvdla_bdma_cfg_src_surf_0_out); + (32'h403c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_STATUS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_status_0_out, nvdla_bdma_cfg_status_0_out); + (32'h4024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_BDMA_CFG_SURF_REPEAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_bdma_cfg_surf_repeat_0_out, nvdla_bdma_cfg_surf_repeat_0_out); + (32'h4040 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h4044 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP0_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h4048 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP0_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h404c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP1_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h4050 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_BDMA_STATUS_GRP1_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_BDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v new file mode 100644 index 0000000..9711414 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v @@ -0,0 +1,3725 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_store.v +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_store ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,bdma2mcif_wr_req_ready //|< i + ,dma_write_stall_count_cen //|< i + ,ld2st_rd_pd //|< i + ,ld2st_rd_pvld //|< i + ,mcif2bdma_rd_rsp_pd //|< i + ,mcif2bdma_rd_rsp_valid //|< i + ,mcif2bdma_wr_rsp_complete //|< i + ,pwrbus_ram_pd //|< i + ,bdma2mcif_rd_cdt_lat_fifo_pop //|> o + ,bdma2mcif_wr_req_pd //|> o + ,bdma2mcif_wr_req_valid //|> o + ,dma_write_stall_count //|> o + ,ld2st_rd_prdy //|> o + ,mcif2bdma_rd_rsp_ready //|> o + ,st2csb_grp0_done //|> o + ,st2csb_grp1_done //|> o + ,st2csb_idle //|> o + ,st2gate_slcg_en //|> o + ,st2ld_load_idle //|> o + ); +// +// NV_NVDLA_BDMA_store_ports.v +// +input nvdla_core_clk; /* mcif2bdma_rd_rsp, cvif2bdma_rd_rsp, bdma2mcif_rd_cdt, bdma2cvif_rd_cdt, bdma2mcif_wr_req, bdma2cvif_wr_req, mcif2bdma_wr_rsp, cvif2bdma_wr_rsp, ld2st_rd */ +input nvdla_core_rstn; /* mcif2bdma_rd_rsp, cvif2bdma_rd_rsp, bdma2mcif_rd_cdt, bdma2cvif_rd_cdt, bdma2mcif_wr_req, bdma2cvif_wr_req, mcif2bdma_wr_rsp, cvif2bdma_wr_rsp, ld2st_rd */ +input mcif2bdma_rd_rsp_valid; /* data valid */ +output mcif2bdma_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2bdma_rd_rsp_pd; +output bdma2mcif_rd_cdt_lat_fifo_pop; +output bdma2mcif_wr_req_valid; /* data valid */ +input bdma2mcif_wr_req_ready; /* data return handshake */ +output [514:0] bdma2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ +input mcif2bdma_wr_rsp_complete; +input ld2st_rd_pvld; /* data valid */ +output ld2st_rd_prdy; /* data return handshake */ +input [160:0] ld2st_rd_pd; +input [31:0] pwrbus_ram_pd; +//&Ports /^obs_bus/; +output st2ld_load_idle; +output st2csb_grp0_done; +output st2csb_grp1_done; +output st2csb_idle; +output st2gate_slcg_en; +output [31:0] dma_write_stall_count; +input dma_write_stall_count_cen; +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg bdma2mcif_rd_cdt_lat_fifo_pop; +reg [11:0] beat_count; +reg cmd_en; +reg cv_dma_wr_rsp_complete; +reg cv_pending; +reg dat_en; +reg [514:0] dma_wr_req_pd; +reg dma_wr_rsp_complete; +reg [31:0] dma_write_stall_count; +reg [63:0] line_addr; +reg [12:0] line_count; +reg mc_dma_wr_rsp_complete; +reg mc_pending; +reg mon_line_addr_c; +reg mon_surf_addr_c; +reg reg_cmd_dst_ram_type; +reg reg_cmd_interrupt; +reg reg_cmd_interrupt_ptr; +reg reg_cmd_src_ram_type; +reg [12:0] reg_line_repeat_number; +reg [12:0] reg_line_size; +reg [26:0] reg_line_stride; +reg [12:0] reg_surf_repeat_number; +reg [26:0] reg_surf_stride; +reg st2gate_slcg_en; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [63:0] surf_addr; +reg [12:0] surf_count; +reg tran_cmd_valid; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire [11:0] beat_size; +wire [513:0] cv_dma_rd_rsp_pd; +wire cv_dma_rd_rsp_vld; +wire cv_dma_wr_req_rdy; +wire cv_dma_wr_req_vld; +wire [513:0] cv_int_rd_rsp_pd; +wire cv_int_rd_rsp_ready; +wire cv_int_rd_rsp_valid; +wire [514:0] cv_int_wr_req_pd; +wire [514:0] cv_int_wr_req_pd_d0; +wire cv_int_wr_req_ready; +wire cv_int_wr_req_ready_d0; +wire cv_int_wr_req_valid; +wire cv_int_wr_req_valid_d0; +wire cv_int_wr_rsp_complete; +wire cv_releasing; +wire cv_wr_req_rdyi; +wire dma_rd_cdt_lat_fifo_pop; +wire [513:0] dma_rd_rsp_pd; +wire dma_rd_rsp_ram_type; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [63:0] dma_wr_cmd_addr; +wire [77:0] dma_wr_cmd_pd; +wire dma_wr_cmd_rdy; +wire dma_wr_cmd_require_ack; +wire [12:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [513:0] dma_wr_dat_data; +wire [1:0] dma_wr_dat_mask; +wire [513:0] dma_wr_dat_pd; +wire dma_wr_dat_pvld; +wire dma_wr_dat_rdy; +wire dma_wr_dat_vld; +wire dma_wr_req_ram_type; +wire dma_wr_req_rdy; +wire dma_wr_req_vld; +wire dma_write_stall_count_dec; +wire dma_write_stall_count_inc; +wire fifo_intr_rd_pd; +wire fifo_intr_rd_prdy; +wire fifo_intr_rd_pvld; +wire fifo_intr_wr_idle; +wire fifo_intr_wr_pd; +wire fifo_intr_wr_pvld; +wire grp0_done; +wire grp1_done; +wire is_cube_last; +wire is_last_beat; +wire is_surf_last; +wire [63:0] ld2st_addr; +wire ld2st_cmd_dst_ram_type; +wire ld2st_cmd_interrupt; +wire ld2st_cmd_interrupt_ptr; +wire ld2st_cmd_src_ram_type; +wire [12:0] ld2st_line_repeat_number; +wire [12:0] ld2st_line_size; +wire [26:0] ld2st_line_stride; +wire ld2st_rd_accept; +wire [12:0] ld2st_surf_repeat_number; +wire [26:0] ld2st_surf_stride; +wire [513:0] mc_dma_rd_rsp_pd; +wire mc_dma_rd_rsp_vld; +wire mc_dma_wr_req_rdy; +wire mc_dma_wr_req_vld; +wire [513:0] mc_int_rd_rsp_pd; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire [514:0] mc_int_wr_req_pd; +wire [514:0] mc_int_wr_req_pd_d0; +wire mc_int_wr_req_ready; +wire mc_int_wr_req_ready_d0; +wire mc_int_wr_req_valid; +wire mc_int_wr_req_valid_d0; +wire mc_int_wr_rsp_complete; +wire mc_releasing; +wire mc_wr_req_rdyi; +wire [513:0] mcif2bdma_rd_rsp_pd_d0; +wire mcif2bdma_rd_rsp_ready_d0; +wire mcif2bdma_rd_rsp_valid_d0; +wire releasing; +wire require_ack; +wire st_idle; +wire tran_cmd_accept; +wire tran_dat_accept; +wire wr_req_rdyi; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//================================== +//===Return DATA from DMA READ RSP CHANNEL +//================================== +assign dma_rd_rsp_ram_type = reg_cmd_src_ram_type; +// rd Channel: Response +assign mcif2bdma_rd_rsp_valid_d0 = mcif2bdma_rd_rsp_valid; +assign mcif2bdma_rd_rsp_ready = mcif2bdma_rd_rsp_ready_d0; +assign mcif2bdma_rd_rsp_pd_d0[513:0] = mcif2bdma_rd_rsp_pd[513:0]; +assign mc_int_rd_rsp_valid = mcif2bdma_rd_rsp_valid_d0; +assign mcif2bdma_rd_rsp_ready_d0 = mc_int_rd_rsp_ready; +assign mc_int_rd_rsp_pd[513:0] = mcif2bdma_rd_rsp_pd_d0[513:0]; +NV_NVDLA_BDMA_STORE_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.mc_int_rd_rsp_pd (mc_int_rd_rsp_pd[513:0]) //|< w + ,.mc_int_rd_rsp_valid (mc_int_rd_rsp_valid) //|< w + ,.mc_dma_rd_rsp_pd (mc_dma_rd_rsp_pd[513:0]) //|> w + ,.mc_dma_rd_rsp_vld (mc_dma_rd_rsp_vld) //|> w + ,.mc_int_rd_rsp_ready (mc_int_rd_rsp_ready) //|> w + ); +assign dma_rd_rsp_vld = mc_dma_rd_rsp_vld; +assign dma_rd_rsp_pd = ({514{mc_dma_rd_rsp_vld}} & mc_dma_rd_rsp_pd); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"DMAIF: mcif and cvif should never return data both") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mc_dma_rd_rsp_vld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + bdma2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1); + end +end +//================================== +//===Load Cmd from Context QUEUE +//================================== +// input rename +// ro = ri || !vo; // ready +// vo <0= (ro)? vi : vo; // valid +// do <= (ro && vi)? di : do; // data +assign ld2st_rd_prdy = (tran_dat_accept & is_last_beat & is_cube_last) || (!tran_cmd_valid); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_cmd_valid <= 1'b0; + end else begin + if ((ld2st_rd_prdy) == 1'b1) begin + tran_cmd_valid <= ld2st_rd_pvld; +// VCS coverage off + end else if ((ld2st_rd_prdy) == 1'b0) begin + end else begin + tran_cmd_valid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ld2st_rd_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign ld2st_rd_accept = ld2st_rd_prdy & ld2st_rd_pvld; +// PKT_UNPACK_WIRE( bdma_ld2st , ld2st_ , ld2st_rd_pd ) +assign ld2st_addr[63:0] = ld2st_rd_pd[63:0]; +assign ld2st_line_size[12:0] = ld2st_rd_pd[76:64]; +assign ld2st_cmd_src_ram_type = ld2st_rd_pd[77]; +assign ld2st_cmd_dst_ram_type = ld2st_rd_pd[78]; +assign ld2st_cmd_interrupt = ld2st_rd_pd[79]; +assign ld2st_cmd_interrupt_ptr = ld2st_rd_pd[80]; +assign ld2st_line_stride[26:0] = ld2st_rd_pd[107:81]; +assign ld2st_line_repeat_number[12:0] = ld2st_rd_pd[120:108]; +assign ld2st_surf_stride[26:0] = ld2st_rd_pd[147:121]; +assign ld2st_surf_repeat_number[12:0] = ld2st_rd_pd[160:148]; +always @(posedge nvdla_core_clk) begin + if (ld2st_rd_accept) begin +//reg_addr <= ld2st_addr; + reg_line_size <= ld2st_line_size; + reg_cmd_src_ram_type <= ld2st_cmd_src_ram_type; + reg_cmd_dst_ram_type <= ld2st_cmd_dst_ram_type; + reg_cmd_interrupt <= ld2st_cmd_interrupt; + reg_cmd_interrupt_ptr <= ld2st_cmd_interrupt_ptr; + reg_line_stride <= ld2st_line_stride; + reg_line_repeat_number <= ld2st_line_repeat_number; + reg_surf_stride <= ld2st_surf_stride; + reg_surf_repeat_number <= ld2st_surf_repeat_number; + end +end +assign dma_rd_cdt_lat_fifo_pop = dma_wr_dat_pvld & dma_wr_dat_rdy; +NV_NVDLA_BDMA_STORE_lat_fifo lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lat_fifo_wr_prdy (dma_rd_rsp_rdy) //|> w + ,.lat_fifo_wr_pvld (dma_rd_rsp_vld) //|< w + ,.lat_fifo_wr_pd (dma_rd_rsp_pd[513:0]) //|< w + ,.lat_fifo_rd_prdy (dma_wr_dat_rdy) //|< w + ,.lat_fifo_rd_pvld (dma_wr_dat_pvld) //|> w + ,.lat_fifo_rd_pd (dma_wr_dat_data[513:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//================================== +//===DMA WRITE DATA +//================================== +//===FLAG: cmd or data +//===LDC: first Command and follow with corespoing data +// Only when all beat is ready in r2w FIFO, wr_cmd will be sent +// and after cmd is sent, data will be sent to XXIF without bubble +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (tran_cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end else if (tran_dat_accept & is_last_beat) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end + end +end +//================================== +//===Beat Count +//================================== +assign beat_size = reg_line_size[12:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {12{1'b0}}; + end else begin + if (tran_dat_accept) begin + if (is_last_beat) begin + beat_count <= 0; + end else begin + beat_count <= beat_count + 1; + end + end + end +end +assign is_last_beat = (beat_count==beat_size); +//================================== +// Interrupt Handler +//================================== +NV_NVDLA_BDMA_STORE_fifo_intr u_fifo_intr ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fifo_intr_wr_idle (fifo_intr_wr_idle) //|> w + ,.fifo_intr_wr_pvld (fifo_intr_wr_pvld) //|< w + ,.fifo_intr_wr_pd (fifo_intr_wr_pd) //|< w + ,.fifo_intr_rd_prdy (fifo_intr_rd_prdy) //|< w + ,.fifo_intr_rd_pvld (fifo_intr_rd_pvld) //|> w + ,.fifo_intr_rd_pd (fifo_intr_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign fifo_intr_wr_pd = reg_cmd_interrupt_ptr; +assign fifo_intr_wr_pvld = dma_wr_cmd_vld & dma_wr_cmd_rdy & dma_wr_cmd_require_ack; +assign fifo_intr_rd_prdy = dma_wr_rsp_complete; +assign grp0_done = fifo_intr_rd_pvld & fifo_intr_rd_prdy & (fifo_intr_rd_pd==0); +assign grp1_done = fifo_intr_rd_pvld & fifo_intr_rd_prdy & (fifo_intr_rd_pd==1); +assign st2csb_grp0_done = grp0_done; +assign st2csb_grp1_done = grp1_done; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when write complete, intr_ptr should be already in the head of fifo_intr read side") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, !fifo_intr_rd_pvld & dma_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//================================== +//===DMA WRITE REQ +//================================== +// Line_addr is the start address of every line +// load a new one from CSB FIFO for every mem copy command +// will change every time one a block is done and jump to the next line +always @(posedge nvdla_core_clk) begin + if (ld2st_rd_accept) begin + line_addr <= ld2st_addr; + end else if (tran_dat_accept & is_last_beat) begin + if (is_surf_last) begin + {mon_line_addr_c,line_addr} <= surf_addr + (reg_surf_stride<<5); + end else begin + {mon_line_addr_c,line_addr} <= line_addr + (reg_line_stride<<5); + end + end +end +// Surf_addr is the base address of each surface +// will change every time one a block is done and jump to the next surface +always @(posedge nvdla_core_clk) begin + if (ld2st_rd_accept) begin + surf_addr <= ld2st_addr; + end else if (tran_dat_accept & is_last_beat) begin + if (is_surf_last) begin + {mon_surf_addr_c,surf_addr} <= surf_addr + (reg_surf_stride<<5); + end + end +end +//===TRAN SIZE +// for each DMA request, tran_size is to tell how many 32B DATA block indicated +// ===LINE COUNT +// count++ when just to next line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_count <= {13{1'b0}}; + end else begin + if (tran_dat_accept & is_last_beat) begin + if (is_surf_last) begin + line_count <= 0; + end else begin + line_count <= line_count + 1; + end + end + end +end +// SURF COUNT +// count++ when just to next surf +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_count <= {13{1'b0}}; + end else begin + if (tran_dat_accept & is_last_beat) begin + if (is_cube_last) begin + surf_count <= 0; + end else if (is_surf_last) begin + surf_count <= surf_count + 1; + end + end + end +end +//===Require ACK +assign is_surf_last = (line_count==reg_line_repeat_number); +assign is_cube_last = (surf_count==reg_surf_repeat_number) && is_surf_last; +//===DMA WRITE OUT +assign dma_wr_cmd_rdy = dma_wr_req_rdy & cmd_en; +assign dma_wr_dat_rdy = dma_wr_req_rdy & dat_en; +assign tran_cmd_accept = dma_wr_cmd_rdy & dma_wr_req_vld; +assign tran_dat_accept = dma_wr_dat_rdy & dma_wr_req_vld; +//DMA WRITE req : cmd +assign dma_wr_cmd_vld = cmd_en & tran_cmd_valid; +assign dma_wr_cmd_addr = line_addr; +assign dma_wr_cmd_size = reg_line_size; +assign dma_wr_cmd_require_ack = reg_cmd_interrupt & is_cube_last; +// PKT_PACK_WIRE( dma_write_cmd , dma_wr_cmd_ , dma_wr_cmd_pd ) +assign dma_wr_cmd_pd[63:0] = dma_wr_cmd_addr[63:0]; +assign dma_wr_cmd_pd[76:64] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[77] = dma_wr_cmd_require_ack ; +//DMA WRITE req : data +assign dma_wr_dat_vld = dat_en & dma_wr_dat_pvld; +//assign dma_wr_dat_data = lat_fifo_rd_pd; +assign dma_wr_dat_mask = (reg_line_size[0]==0 && is_last_beat) ? 2'b01 : 2'b11; +// PKT_PACK_WIRE( dma_write_data , dma_wr_dat_ , dma_wr_dat_pd ) +assign dma_wr_dat_pd[511:0] = dma_wr_dat_data[511:0]; +assign dma_wr_dat_pd[513:512] = dma_wr_dat_mask[1:0]; +// req: cmd|data +assign dma_wr_req_vld = dma_wr_cmd_vld | dma_wr_dat_vld; +always @( + cmd_en + or dma_wr_cmd_pd + or dma_wr_dat_pd + ) begin + dma_wr_req_pd = 0; + if (cmd_en) begin + dma_wr_req_pd[77:0] = dma_wr_cmd_pd; + dma_wr_req_pd[514:514] = 1'd0 /* PKT_nvdla_dma_wr_req_dma_write_cmd_ID */ ; + end else begin + dma_wr_req_pd[513:0] = dma_wr_dat_pd; + dma_wr_req_pd[514:514] = 1'd1 /* PKT_nvdla_dma_wr_req_dma_write_data_ID */ ; + end +end +//DMA WRITE req : pkt : cmd+data +assign dma_wr_req_ram_type = reg_cmd_dst_ram_type; +// wr Channel: Request +assign mc_dma_wr_req_vld = dma_wr_req_vld & (dma_wr_req_ram_type == 1'b1); +assign mc_wr_req_rdyi = mc_dma_wr_req_rdy & (dma_wr_req_ram_type == 1'b1); +assign wr_req_rdyi = mc_wr_req_rdyi; +assign dma_wr_req_rdy= wr_req_rdyi; +NV_NVDLA_BDMA_STORE_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma_wr_req_pd (dma_wr_req_pd[514:0]) //|< r + ,.mc_dma_wr_req_vld (mc_dma_wr_req_vld) //|< w + ,.mc_int_wr_req_ready (mc_int_wr_req_ready) //|< w + ,.mc_dma_wr_req_rdy (mc_dma_wr_req_rdy) //|> w + ,.mc_int_wr_req_pd (mc_int_wr_req_pd[514:0]) //|> w + ,.mc_int_wr_req_valid (mc_int_wr_req_valid) //|> w + ); +assign mc_int_wr_req_valid_d0 = mc_int_wr_req_valid; +assign mc_int_wr_req_ready = mc_int_wr_req_ready_d0; +assign mc_int_wr_req_pd_d0[514:0] = mc_int_wr_req_pd[514:0]; +assign bdma2mcif_wr_req_valid = mc_int_wr_req_valid_d0; +assign mc_int_wr_req_ready_d0 = bdma2mcif_wr_req_ready; +assign bdma2mcif_wr_req_pd[514:0] = mc_int_wr_req_pd_d0[514:0]; +// wr Channel: Response +assign mc_int_wr_rsp_complete = mcif2bdma_wr_rsp_complete; +assign require_ack = (dma_wr_req_pd[514:514]==0) & (dma_wr_req_pd[77:77]==1); +assign ack_raw_vld = dma_wr_req_vld & wr_req_rdyi & require_ack; +assign ack_raw_id = dma_wr_req_ram_type; +// stage1: bot +assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld; +always @(posedge nvdla_core_clk) begin + if ((ack_raw_vld & ack_raw_rdy) == 1'b1) begin + ack_bot_id <= ack_raw_id; +// VCS coverage off + end else if ((ack_raw_vld & ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_bot_vld <= 1'b0; + end else begin + if ((ack_raw_rdy) == 1'b1) begin + ack_bot_vld <= ack_raw_vld; +// VCS coverage off + end else if ((ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_raw_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"dmaif bot never push back") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, ack_raw_vld & !ack_raw_rdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// stage2: top +assign ack_bot_rdy = ack_top_rdy || !ack_top_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_id <= 1'b0; + end else begin + if ((ack_bot_vld & ack_bot_rdy) == 1'b1) begin + ack_top_id <= ack_bot_id; +// VCS coverage off + end else if ((ack_bot_vld & ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_vld & ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_vld <= 1'b0; + end else begin + if ((ack_bot_rdy) == 1'b1) begin + ack_top_vld <= ack_bot_vld; +// VCS coverage off + end else if ((ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign ack_top_rdy = releasing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_dma_wr_rsp_complete <= 1'b0; + end else begin + mc_dma_wr_rsp_complete <= mc_int_wr_rsp_complete; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_wr_rsp_complete <= 1'b0; + end else begin + dma_wr_rsp_complete <= releasing; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_pending <= 1'b0; + end else begin + if (ack_top_id==0) begin + if (mc_dma_wr_rsp_complete) begin + mc_pending <= 1'b1; + end + end else if (ack_top_id==1) begin + if (mc_pending) begin + mc_pending <= 1'b0; + end + end + end +end +assign mc_releasing = ack_top_id==1'b1 & (mc_dma_wr_rsp_complete | mc_pending); +assign releasing = mc_releasing; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no release both together") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, mc_releasing ); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no mc resp back and pending together") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, mc_pending & mc_dma_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no ack_top_vld when resp from mc") zzz_assert_never_12x (nvdla_core_clk, `ASSERT_RESET, (mc_pending | mc_dma_wr_rsp_complete) & !ack_top_vld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property dmaif_bdma__two_completes__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete; + endproperty +// Cover 0 : "mc_dma_wr_rsp_complete & cv_dma_wr_rsp_complete" + FUNCPOINT_dmaif_bdma__two_completes__0_COV : cover property (dmaif_bdma__two_completes__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__one_pending_complete_with_mc__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete; + endproperty +// Cover 1 : "cv_pending & mc_dma_wr_rsp_complete" + FUNCPOINT_dmaif_bdma__one_pending_complete_with_mc__1_COV : cover property (dmaif_bdma__one_pending_complete_with_mc__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__one_pending_complete_with_cv__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_pending; + endproperty +// Cover 2 : "mc_pending & cv_dma_wr_rsp_complete" + FUNCPOINT_dmaif_bdma__one_pending_complete_with_cv__2_COV : cover property (dmaif_bdma__one_pending_complete_with_cv__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_in_order__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete & ack_top_id==1'b1; + endproperty +// Cover 3 : "cv_int_wr_rsp_complete & mc_dma_wr_rsp_complete & ack_top_id==1'b1" + FUNCPOINT_dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_in_order__3_COV : cover property (dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_in_order__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_out_of_order__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete & ack_top_id==1'b0; + endproperty +// Cover 4 : "cv_int_wr_rsp_complete & mc_dma_wr_rsp_complete & ack_top_id==1'b0" + FUNCPOINT_dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_out_of_order__4_COV : cover property (dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_out_of_order__4_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_in_order__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_int_wr_rsp_complete & ack_top_id==1'b0; + endproperty +// Cover 5 : "mc_int_wr_rsp_complete & cv_dma_wr_rsp_complete & ack_top_id==1'b0" + FUNCPOINT_dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_in_order__5_COV : cover property (dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_in_order__5_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_out_of_order__6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_int_wr_rsp_complete & ack_top_id==1'b1; + endproperty +// Cover 6 : "mc_int_wr_rsp_complete & cv_dma_wr_rsp_complete & ack_top_id==1'b1" + FUNCPOINT_dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_out_of_order__6_COV : cover property (dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_out_of_order__6_cov); + `endif +`endif +//VCS coverage on +//====================================== +// STATUS +//====================================== +// STATUS stall count +assign dma_write_stall_count_inc = dma_wr_req_vld & !dma_wr_req_rdy; + assign dma_write_stall_count_dec = 1'b0; +// stl adv logic + always @( + dma_write_stall_count_inc + or dma_write_stall_count_dec + ) begin + stl_adv = dma_write_stall_count_inc ^ dma_write_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or dma_write_stall_count_inc + or dma_write_stall_count_dec + or stl_adv + or dma_wr_rsp_complete + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (dma_write_stall_count_inc && !dma_write_stall_count_dec)? stl_cnt_inc : (!dma_write_stall_count_inc && dma_write_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (dma_wr_rsp_complete)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (dma_write_stall_count_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + dma_write_stall_count[31:0] = stl_cnt_cur[31:0]; + end +// STATUS IDLE +assign st_idle = fifo_intr_wr_idle & !tran_cmd_valid; +assign st2csb_idle = st_idle; +assign st2ld_load_idle = cmd_en & !tran_cmd_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + st2gate_slcg_en <= 1'b0; + end else begin + st2gate_slcg_en <= !st_idle; + end +end +//====================================== +// OBS +//assign obs_bus_bdma_store_ack_bot_vld = ack_bot_vld; +//assign obs_bus_bdma_store_ack_top_vld = ack_top_vld; +//assign obs_bus_bdma_store_ack_pending = releasing; +//assign obs_bus_bdma_store_ack_release = releasing; +//assign obs_bus_bdma_store_cmd_en = cmd_en; +//assign obs_bus_bdma_store_dat_en = dat_en; +//assign obs_bus_bdma_store_cv_rd_rsp_rdy = dma_rd_rsp_rdy; +//assign obs_bus_bdma_store_cv_rd_rsp_vld = cv_dma_rd_rsp_vld; +//assign obs_bus_bdma_store_cv_wr_req_rdy = cv_dma_wr_req_rdy; +//assign obs_bus_bdma_store_cv_wr_req_vld = cv_dma_wr_req_vld; +//assign obs_bus_bdma_store_cv_wr_rsp_complete = cv_dma_wr_rsp_complete; +//assign obs_bus_bdma_store_grp0_done = grp0_done; +//assign obs_bus_bdma_store_grp1_done = grp1_done; +//assign obs_bus_bdma_store_idle = st_idle; +//assign obs_bus_bdma_store_is_cube_last = is_cube_last; +//assign obs_bus_bdma_store_is_surf_last = is_surf_last; +//assign obs_bus_bdma_store_lat_fifo_rd_prdy = lat_fifo_rd_prdy; +//assign obs_bus_bdma_store_lat_fifo_rd_pvld = lat_fifo_rd_pvld; +//assign obs_bus_bdma_store_lat_fifo_wr_prdy = lat_fifo_wr_prdy; +//assign obs_bus_bdma_store_lat_fifo_wr_pvld = lat_fifo_wr_pvld; +//assign obs_bus_bdma_store_mc_rd_rsp_rdy = dma_rd_rsp_rdy; +//assign obs_bus_bdma_store_mc_rd_rsp_vld = mc_dma_rd_rsp_vld; +//assign obs_bus_bdma_store_mc_wr_req_rdy = mc_dma_wr_req_rdy; +//assign obs_bus_bdma_store_mc_wr_req_vld = mc_dma_wr_req_vld; +//assign obs_bus_bdma_store_mc_wr_rsp_complete = mc_dma_wr_rsp_complete; +endmodule // NV_NVDLA_BDMA_store +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os mc_dma_rd_rsp_pd (mc_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= mc_int_rd_rsp_pd[513:0] (mc_int_rd_rsp_valid,mc_int_rd_rsp_ready) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_STORE_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_rsp_rdy + ,mc_int_rd_rsp_pd + ,mc_int_rd_rsp_valid + ,mc_dma_rd_rsp_pd + ,mc_dma_rd_rsp_vld + ,mc_int_rd_rsp_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dma_rd_rsp_rdy; +input [513:0] mc_int_rd_rsp_pd; +input mc_int_rd_rsp_valid; +output [513:0] mc_dma_rd_rsp_pd; +output mc_dma_rd_rsp_vld; +output mc_int_rd_rsp_ready; +reg [513:0] mc_dma_rd_rsp_pd; +reg mc_dma_rd_rsp_vld; +reg mc_int_rd_rsp_ready; +reg [513:0] p1_pipe_data; +reg [513:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [513:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [513:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_int_rd_rsp_valid + or p1_pipe_rand_ready + or mc_int_rd_rsp_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = p1_pipe_rand_ready; + p1_pipe_rand_data = mc_int_rd_rsp_pd[513:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : mc_int_rd_rsp_pd[513:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_int_rd_rsp_valid + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_int_rd_rsp_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_pipe_rand_valid)? p1_pipe_rand_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_pipe_rand_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or dma_rd_rsp_rdy + or p1_pipe_skid_data + ) begin + mc_dma_rd_rsp_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = dma_rd_rsp_rdy; + mc_dma_rd_rsp_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_dma_rd_rsp_vld^dma_rd_rsp_rdy^mc_int_rd_rsp_valid^mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (mc_int_rd_rsp_valid && !mc_int_rd_rsp_ready), (mc_int_rd_rsp_valid), (mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_STORE_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cv_dma_rd_rsp_pd (cv_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= cv_int_rd_rsp_pd[513:0] (cv_int_rd_rsp_valid,cv_int_rd_rsp_ready) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_wr_req_pd (mc_int_wr_req_valid,mc_int_wr_req_ready) <= dma_wr_req_pd[514:0] (mc_dma_wr_req_vld,mc_dma_wr_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_STORE_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_wr_req_pd + ,mc_dma_wr_req_vld + ,mc_int_wr_req_ready + ,mc_dma_wr_req_rdy + ,mc_int_wr_req_pd + ,mc_int_wr_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [514:0] dma_wr_req_pd; +input mc_dma_wr_req_vld; +input mc_int_wr_req_ready; +output mc_dma_wr_req_rdy; +output [514:0] mc_int_wr_req_pd; +output mc_int_wr_req_valid; +reg mc_dma_wr_req_rdy; +reg [514:0] mc_int_wr_req_pd; +reg mc_int_wr_req_valid; +reg [514:0] p3_pipe_data; +reg [514:0] p3_pipe_rand_data; +reg p3_pipe_rand_ready; +reg p3_pipe_rand_valid; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [514:0] p3_skid_data; +reg [514:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) randomizer +`ifndef SYNTHESIS +reg p3_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p3_pipe_rand_active + or + `endif + mc_dma_wr_req_vld + or p3_pipe_rand_ready + or dma_wr_req_pd + ) begin + `ifdef SYNTHESIS + p3_pipe_rand_valid = mc_dma_wr_req_vld; + mc_dma_wr_req_rdy = p3_pipe_rand_ready; + p3_pipe_rand_data = dma_wr_req_pd[514:0]; + `else +// VCS coverage off + p3_pipe_rand_valid = (p3_pipe_rand_active)? 1'b0 : mc_dma_wr_req_vld; + mc_dma_wr_req_rdy = (p3_pipe_rand_active)? 1'b0 : p3_pipe_rand_ready; + p3_pipe_rand_data = (p3_pipe_rand_active)? 'bx : dma_wr_req_pd[514:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p3_pipe_stall_cycles; +integer p3_pipe_stall_probability; +integer p3_pipe_stall_cycles_min; +integer p3_pipe_stall_cycles_max; +initial begin + p3_pipe_stall_cycles = 0; + p3_pipe_stall_probability = 0; + p3_pipe_stall_cycles_min = 1; + p3_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability" ) ) p3_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min" ) ) p3_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max" ) ) p3_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p3_pipe_rand_enable; +reg p3_pipe_rand_poised; +always @( + p3_pipe_stall_cycles + or p3_pipe_stall_probability + or mc_dma_wr_req_vld + ) begin + p3_pipe_rand_active = p3_pipe_stall_cycles != 0; + p3_pipe_rand_enable = p3_pipe_stall_probability != 0; + p3_pipe_rand_poised = p3_pipe_rand_enable && !p3_pipe_rand_active && mc_dma_wr_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_stall_cycles <= 1'b0; + end else begin + if (p3_pipe_rand_poised) begin + if (p3_pipe_stall_probability >= prand_inst0(1, 100)) begin + p3_pipe_stall_cycles <= prand_inst1(p3_pipe_stall_cycles_min, p3_pipe_stall_cycles_max); + end + end else if (p3_pipe_rand_active) begin + p3_pipe_stall_cycles <= p3_pipe_stall_cycles - 1; + end else begin + p3_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (3) skid buffer +always @( + p3_pipe_rand_valid + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = p3_pipe_rand_valid && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + p3_pipe_rand_ready <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + p3_pipe_rand_ready <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? p3_pipe_rand_data : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or p3_pipe_rand_valid + or p3_skid_valid + or p3_pipe_rand_data + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? p3_pipe_rand_valid : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? p3_pipe_rand_data : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or mc_int_wr_req_ready + or p3_pipe_data + ) begin + mc_int_wr_req_valid = p3_pipe_valid; + p3_pipe_ready = mc_int_wr_req_ready; + mc_int_wr_req_pd = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_wr_req_valid^mc_int_wr_req_ready^mc_dma_wr_req_vld^mc_dma_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_18x (nvdla_core_clk, `ASSERT_RESET, (mc_dma_wr_req_vld && !mc_dma_wr_req_rdy), (mc_dma_wr_req_vld), (mc_dma_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_STORE_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_wr_req_pd (cv_int_wr_req_valid,cv_int_wr_req_ready) <= dma_wr_req_pd[514:0] (cv_dma_wr_req_vld,cv_dma_wr_req_rdy) +// ************************************************************************************************************** +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_STORE_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_fifo_wr -rd_pipebus lat_fifo_rd -rd_reg -d 245 -w 514 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_STORE_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_fifo_wr_prdy + , lat_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_fifo_wr_pause +`endif + , lat_fifo_wr_pd + , lat_fifo_rd_prdy + , lat_fifo_rd_pvld + , lat_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_fifo_wr_prdy; +input lat_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_fifo_wr_pause; +`endif +input [513:0] lat_fifo_wr_pd; +input lat_fifo_rd_prdy; +output lat_fifo_rd_pvld; +output [513:0] lat_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_fifo_wr_busy_int; // copy for internal use +assign lat_fifo_wr_prdy = !lat_fifo_wr_busy_int; +assign wr_reserving = lat_fifo_wr_pvld && !lat_fifo_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] lat_fifo_wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? lat_fifo_wr_count : (lat_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_fifo_wr_count + 1'd1) : lat_fifo_wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_245 = ( wr_count_next_no_wr_popping == 8'd245 ); +wire wr_count_next_is_245 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_245; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_fifo_wr_busy_next = wr_count_next_is_245 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_fifo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_fifo_wr_busy_next = wr_count_next_is_245 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_wr_busy_int <= 1'b0; + lat_fifo_wr_count <= 8'd0; + end else begin + lat_fifo_wr_busy_int <= lat_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_fifo_wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_fifo_wr_pvld +// +// RAM +// +reg [7:0] lat_fifo_wr_adr; // current write address +wire [7:0] lat_fifo_rd_adr_p; // read address to use for ram +wire [513:0] lat_fifo_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_245x514 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_fifo_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_fifo_wr_pd ) + , .ra ( lat_fifo_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_fifo_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_fifo_wr_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (lat_fifo_wr_adr == 8'd244) ? 8'd0 : (lat_fifo_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_wr_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + lat_fifo_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_fifo_wr_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] lat_fifo_rd_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (lat_fifo_rd_adr == 8'd244) ? 8'd0 : (lat_fifo_rd_adr + 1'd1); // spyglass disable W484 +assign lat_fifo_rd_adr_p = rd_popping ? rd_adr_next : lat_fifo_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_rd_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + lat_fifo_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_fifo_rd_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_fifo_rd_pvld_p; // data out of fifo is valid +reg lat_fifo_rd_pvld_int; // internal copy of lat_fifo_rd_pvld +assign lat_fifo_rd_pvld = lat_fifo_rd_pvld_int; +assign rd_popping = lat_fifo_rd_pvld_p && !(lat_fifo_rd_pvld_int && !lat_fifo_rd_prdy); +reg [7:0] lat_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? lat_fifo_rd_count_p : + (lat_fifo_rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_fifo_rd_count_p + 1'd1) : + lat_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_fifo_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_rd_count_p <= 8'd0; + lat_fifo_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_fifo_rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_fifo_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_fifo_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_fifo_rd_pvld_p || (lat_fifo_rd_pvld_int && !lat_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_rd_pvld_int <= 1'b0; + end else begin + lat_fifo_rd_pvld_int <= rd_req_next; + end +end +assign lat_fifo_rd_pd = lat_fifo_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_fifo_wr_pvld && !lat_fifo_wr_busy_int) || (lat_fifo_wr_busy_int != lat_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (lat_fifo_rd_pvld_int && lat_fifo_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_fifo_wr_pvld && !(!lat_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd245 : wr_limit_reg} ) + , .curr ( {24'd0, lat_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_STORE_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_BDMA_STORE_lat_fifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_STORE_fifo_r2w -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus fifo_r2w_wr -rd_pipebus fifo_r2w_rd -rd_reg -d 4 -w 514 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_STORE_fifo_r2w ( + nvdla_core_clk + , nvdla_core_rstn + , fifo_r2w_wr_prdy + , fifo_r2w_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , fifo_r2w_wr_pause +`endif + , fifo_r2w_wr_pd + , fifo_r2w_rd_prdy + , fifo_r2w_rd_pvld + , fifo_r2w_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output fifo_r2w_wr_prdy; +input fifo_r2w_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input fifo_r2w_wr_pause; +`endif +input [513:0] fifo_r2w_wr_pd; +input fifo_r2w_rd_prdy; +output fifo_r2w_rd_pvld; +output [513:0] fifo_r2w_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg fifo_r2w_wr_busy_int; // copy for internal use +assign fifo_r2w_wr_prdy = !fifo_r2w_wr_busy_int; +assign wr_reserving = fifo_r2w_wr_pvld && !fifo_r2w_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [2:0] fifo_r2w_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? fifo_r2w_wr_count : (fifo_r2w_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (fifo_r2w_wr_count + 1'd1) : fifo_r2w_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire fifo_r2w_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check fifo_r2w_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || fifo_r2w_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire fifo_r2w_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check fifo_r2w_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_wr_busy_int <= 1'b0; + fifo_r2w_wr_count <= 3'd0; + end else begin + fifo_r2w_wr_busy_int <= fifo_r2w_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + fifo_r2w_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + fifo_r2w_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as fifo_r2w_wr_pvld +// +// RAM +// +reg [1:0] fifo_r2w_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + fifo_r2w_wr_adr <= fifo_r2w_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] fifo_r2w_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [513:0] fifo_r2w_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( fifo_r2w_wr_pd ) + , .we ( ram_we ) + , .wa ( fifo_r2w_wr_adr ) + , .ra ( fifo_r2w_rd_adr ) + , .dout ( fifo_r2w_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = fifo_r2w_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + fifo_r2w_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + fifo_r2w_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg fifo_r2w_rd_pvld_p; // data out of fifo is valid +reg fifo_r2w_rd_pvld_int; // internal copy of fifo_r2w_rd_pvld +assign fifo_r2w_rd_pvld = fifo_r2w_rd_pvld_int; +assign rd_popping = fifo_r2w_rd_pvld_p && !(fifo_r2w_rd_pvld_int && !fifo_r2w_rd_prdy); +reg [2:0] fifo_r2w_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? fifo_r2w_rd_count_p : + (fifo_r2w_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (fifo_r2w_rd_count_p + 1'd1) : + fifo_r2w_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_rd_count_p <= 3'd0; + fifo_r2w_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + fifo_r2w_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + fifo_r2w_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + fifo_r2w_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + fifo_r2w_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [513:0] fifo_r2w_rd_pd; // output data register +wire rd_req_next = (fifo_r2w_rd_pvld_p || (fifo_r2w_rd_pvld_int && !fifo_r2w_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_rd_pvld_int <= 1'b0; + end else begin + fifo_r2w_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + fifo_r2w_rd_pd <= fifo_r2w_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + fifo_r2w_rd_pd <= {514{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (fifo_r2w_wr_pvld && !fifo_r2w_wr_busy_int) || (fifo_r2w_wr_busy_int != fifo_r2w_wr_busy_next)) || (rd_pushing || rd_popping || (fifo_r2w_rd_pvld_int && fifo_r2w_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( fifo_r2w_wr_pvld && !(!fifo_r2w_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, fifo_r2w_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_STORE_fifo_r2w") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_BDMA_STORE_fifo_r2w +// +// Flop-Based RAM +// +module NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [513:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [513:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [513:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [513:0] ram_ff0; +reg [513:0] ram_ff1; +reg [513:0] ram_ff2; +reg [513:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [513:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {514{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [513:0] Di0; +input [1:0] Ra0; +output [513:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 514'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [513:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [513:0] Q0 = mem[0]; +wire [513:0] Q1 = mem[1]; +wire [513:0] Q2 = mem[2]; +wire [513:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514] } +endmodule // vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +//vmw: Memory vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +//vmw: Address-size 2 +//vmw: Data-size 514 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[513:0] data0[513:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[513:0] data1[513:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_STORE_fifo_intr -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus fifo_intr_wr -rd_pipebus fifo_intr_rd -ram_bypass -d 0 -rd_reg -wr_idle -rd_busy_reg -no_wr_busy -w 1 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_STORE_fifo_intr ( + nvdla_core_clk + , nvdla_core_rstn + , fifo_intr_wr_idle + , fifo_intr_wr_pvld + , fifo_intr_wr_pd + , fifo_intr_rd_prdy + , fifo_intr_rd_pvld + , fifo_intr_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output fifo_intr_wr_idle; +input fifo_intr_wr_pvld; +input fifo_intr_wr_pd; +input fifo_intr_rd_prdy; +output fifo_intr_rd_pvld; +output fifo_intr_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] fifo_intr_rd_pd_p = fifo_intr_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg fifo_intr_rd_prdy_d; // fifo_intr_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_intr_rd_prdy_d <= 1'b1; + end else begin + fifo_intr_rd_prdy_d <= fifo_intr_rd_prdy; + end +end +wire fifo_intr_rd_prdy_d_o; // combinatorial rd_busy +reg fifo_intr_rd_pvld_int; // internal copy of fifo_intr_rd_pvld +assign fifo_intr_rd_pvld = fifo_intr_rd_pvld_int; +wire fifo_intr_rd_pvld_p = fifo_intr_wr_pvld ; // no real fifo, take from write-side input +reg fifo_intr_rd_pvld_int_o; // internal copy of fifo_intr_rd_pvld_o +wire fifo_intr_rd_pvld_o = fifo_intr_rd_pvld_int_o; +wire rd_popping = fifo_intr_rd_pvld_p && !(fifo_intr_rd_pvld_int_o && !fifo_intr_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg fifo_intr_rd_pd_o; // output data register +wire rd_req_next_o = (fifo_intr_rd_pvld_p || (fifo_intr_rd_pvld_int_o && !fifo_intr_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_intr_rd_pvld_int_o <= 1'b0; + end else begin + fifo_intr_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (fifo_intr_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + fifo_intr_rd_pd_o <= fifo_intr_rd_pd_p; + end +//synopsys translate_off + else if ( !((fifo_intr_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + fifo_intr_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg fifo_intr_rd_pd; // output data register +reg fifo_intr_rd_pvld_int_d; // so we can bubble-collapse fifo_intr_rd_prdy_d +assign fifo_intr_rd_prdy_d_o = !((fifo_intr_rd_pvld_o && fifo_intr_rd_pvld_int_d && !fifo_intr_rd_prdy_d ) ); +wire rd_req_next = (!fifo_intr_rd_prdy_d_o ? fifo_intr_rd_pvld_o : fifo_intr_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_intr_rd_pvld_int <= 1'b0; + fifo_intr_rd_pvld_int_d <= 1'b0; + end else begin + if ( !fifo_intr_rd_pvld_int || fifo_intr_rd_prdy ) begin + fifo_intr_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!fifo_intr_rd_pvld_int || fifo_intr_rd_prdy) ) begin + end else begin + fifo_intr_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + fifo_intr_rd_pvld_int_d <= fifo_intr_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!fifo_intr_rd_pvld_int || fifo_intr_rd_prdy ) ) begin + case (!fifo_intr_rd_prdy_d_o) + 1'b0: fifo_intr_rd_pd <= fifo_intr_rd_pd_p; + 1'b1: fifo_intr_rd_pd <= fifo_intr_rd_pd_o; +//VCS coverage off + default: fifo_intr_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!fifo_intr_rd_pvld_int || fifo_intr_rd_prdy)) ) begin + end else begin + fifo_intr_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// +// Read-side Idle Calculation +// +wire rd_idle = !fifo_intr_rd_pvld_int_o && !fifo_intr_rd_pvld_int; +// +// Write-Side Idle Calculation +// +wire fifo_intr_wr_idle_d0 = !fifo_intr_wr_pvld && rd_idle; +wire fifo_intr_wr_idle = fifo_intr_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (fifo_intr_wr_pvld || (fifo_intr_rd_pvld_int && fifo_intr_rd_prdy_d) || (fifo_intr_rd_pvld_int_o && fifo_intr_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_STORE_fifo_intr") true +// synopsys dc_script_end +endmodule // NV_NVDLA_BDMA_STORE_fifo_intr diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v.vcp new file mode 100644 index 0000000..9711414 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v.vcp @@ -0,0 +1,3725 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_BDMA_store.v +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_store ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,bdma2mcif_wr_req_ready //|< i + ,dma_write_stall_count_cen //|< i + ,ld2st_rd_pd //|< i + ,ld2st_rd_pvld //|< i + ,mcif2bdma_rd_rsp_pd //|< i + ,mcif2bdma_rd_rsp_valid //|< i + ,mcif2bdma_wr_rsp_complete //|< i + ,pwrbus_ram_pd //|< i + ,bdma2mcif_rd_cdt_lat_fifo_pop //|> o + ,bdma2mcif_wr_req_pd //|> o + ,bdma2mcif_wr_req_valid //|> o + ,dma_write_stall_count //|> o + ,ld2st_rd_prdy //|> o + ,mcif2bdma_rd_rsp_ready //|> o + ,st2csb_grp0_done //|> o + ,st2csb_grp1_done //|> o + ,st2csb_idle //|> o + ,st2gate_slcg_en //|> o + ,st2ld_load_idle //|> o + ); +// +// NV_NVDLA_BDMA_store_ports.v +// +input nvdla_core_clk; /* mcif2bdma_rd_rsp, cvif2bdma_rd_rsp, bdma2mcif_rd_cdt, bdma2cvif_rd_cdt, bdma2mcif_wr_req, bdma2cvif_wr_req, mcif2bdma_wr_rsp, cvif2bdma_wr_rsp, ld2st_rd */ +input nvdla_core_rstn; /* mcif2bdma_rd_rsp, cvif2bdma_rd_rsp, bdma2mcif_rd_cdt, bdma2cvif_rd_cdt, bdma2mcif_wr_req, bdma2cvif_wr_req, mcif2bdma_wr_rsp, cvif2bdma_wr_rsp, ld2st_rd */ +input mcif2bdma_rd_rsp_valid; /* data valid */ +output mcif2bdma_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2bdma_rd_rsp_pd; +output bdma2mcif_rd_cdt_lat_fifo_pop; +output bdma2mcif_wr_req_valid; /* data valid */ +input bdma2mcif_wr_req_ready; /* data return handshake */ +output [514:0] bdma2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ +input mcif2bdma_wr_rsp_complete; +input ld2st_rd_pvld; /* data valid */ +output ld2st_rd_prdy; /* data return handshake */ +input [160:0] ld2st_rd_pd; +input [31:0] pwrbus_ram_pd; +//&Ports /^obs_bus/; +output st2ld_load_idle; +output st2csb_grp0_done; +output st2csb_grp1_done; +output st2csb_idle; +output st2gate_slcg_en; +output [31:0] dma_write_stall_count; +input dma_write_stall_count_cen; +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg bdma2mcif_rd_cdt_lat_fifo_pop; +reg [11:0] beat_count; +reg cmd_en; +reg cv_dma_wr_rsp_complete; +reg cv_pending; +reg dat_en; +reg [514:0] dma_wr_req_pd; +reg dma_wr_rsp_complete; +reg [31:0] dma_write_stall_count; +reg [63:0] line_addr; +reg [12:0] line_count; +reg mc_dma_wr_rsp_complete; +reg mc_pending; +reg mon_line_addr_c; +reg mon_surf_addr_c; +reg reg_cmd_dst_ram_type; +reg reg_cmd_interrupt; +reg reg_cmd_interrupt_ptr; +reg reg_cmd_src_ram_type; +reg [12:0] reg_line_repeat_number; +reg [12:0] reg_line_size; +reg [26:0] reg_line_stride; +reg [12:0] reg_surf_repeat_number; +reg [26:0] reg_surf_stride; +reg st2gate_slcg_en; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [63:0] surf_addr; +reg [12:0] surf_count; +reg tran_cmd_valid; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire [11:0] beat_size; +wire [513:0] cv_dma_rd_rsp_pd; +wire cv_dma_rd_rsp_vld; +wire cv_dma_wr_req_rdy; +wire cv_dma_wr_req_vld; +wire [513:0] cv_int_rd_rsp_pd; +wire cv_int_rd_rsp_ready; +wire cv_int_rd_rsp_valid; +wire [514:0] cv_int_wr_req_pd; +wire [514:0] cv_int_wr_req_pd_d0; +wire cv_int_wr_req_ready; +wire cv_int_wr_req_ready_d0; +wire cv_int_wr_req_valid; +wire cv_int_wr_req_valid_d0; +wire cv_int_wr_rsp_complete; +wire cv_releasing; +wire cv_wr_req_rdyi; +wire dma_rd_cdt_lat_fifo_pop; +wire [513:0] dma_rd_rsp_pd; +wire dma_rd_rsp_ram_type; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [63:0] dma_wr_cmd_addr; +wire [77:0] dma_wr_cmd_pd; +wire dma_wr_cmd_rdy; +wire dma_wr_cmd_require_ack; +wire [12:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [513:0] dma_wr_dat_data; +wire [1:0] dma_wr_dat_mask; +wire [513:0] dma_wr_dat_pd; +wire dma_wr_dat_pvld; +wire dma_wr_dat_rdy; +wire dma_wr_dat_vld; +wire dma_wr_req_ram_type; +wire dma_wr_req_rdy; +wire dma_wr_req_vld; +wire dma_write_stall_count_dec; +wire dma_write_stall_count_inc; +wire fifo_intr_rd_pd; +wire fifo_intr_rd_prdy; +wire fifo_intr_rd_pvld; +wire fifo_intr_wr_idle; +wire fifo_intr_wr_pd; +wire fifo_intr_wr_pvld; +wire grp0_done; +wire grp1_done; +wire is_cube_last; +wire is_last_beat; +wire is_surf_last; +wire [63:0] ld2st_addr; +wire ld2st_cmd_dst_ram_type; +wire ld2st_cmd_interrupt; +wire ld2st_cmd_interrupt_ptr; +wire ld2st_cmd_src_ram_type; +wire [12:0] ld2st_line_repeat_number; +wire [12:0] ld2st_line_size; +wire [26:0] ld2st_line_stride; +wire ld2st_rd_accept; +wire [12:0] ld2st_surf_repeat_number; +wire [26:0] ld2st_surf_stride; +wire [513:0] mc_dma_rd_rsp_pd; +wire mc_dma_rd_rsp_vld; +wire mc_dma_wr_req_rdy; +wire mc_dma_wr_req_vld; +wire [513:0] mc_int_rd_rsp_pd; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire [514:0] mc_int_wr_req_pd; +wire [514:0] mc_int_wr_req_pd_d0; +wire mc_int_wr_req_ready; +wire mc_int_wr_req_ready_d0; +wire mc_int_wr_req_valid; +wire mc_int_wr_req_valid_d0; +wire mc_int_wr_rsp_complete; +wire mc_releasing; +wire mc_wr_req_rdyi; +wire [513:0] mcif2bdma_rd_rsp_pd_d0; +wire mcif2bdma_rd_rsp_ready_d0; +wire mcif2bdma_rd_rsp_valid_d0; +wire releasing; +wire require_ack; +wire st_idle; +wire tran_cmd_accept; +wire tran_dat_accept; +wire wr_req_rdyi; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//================================== +//===Return DATA from DMA READ RSP CHANNEL +//================================== +assign dma_rd_rsp_ram_type = reg_cmd_src_ram_type; +// rd Channel: Response +assign mcif2bdma_rd_rsp_valid_d0 = mcif2bdma_rd_rsp_valid; +assign mcif2bdma_rd_rsp_ready = mcif2bdma_rd_rsp_ready_d0; +assign mcif2bdma_rd_rsp_pd_d0[513:0] = mcif2bdma_rd_rsp_pd[513:0]; +assign mc_int_rd_rsp_valid = mcif2bdma_rd_rsp_valid_d0; +assign mcif2bdma_rd_rsp_ready_d0 = mc_int_rd_rsp_ready; +assign mc_int_rd_rsp_pd[513:0] = mcif2bdma_rd_rsp_pd_d0[513:0]; +NV_NVDLA_BDMA_STORE_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.mc_int_rd_rsp_pd (mc_int_rd_rsp_pd[513:0]) //|< w + ,.mc_int_rd_rsp_valid (mc_int_rd_rsp_valid) //|< w + ,.mc_dma_rd_rsp_pd (mc_dma_rd_rsp_pd[513:0]) //|> w + ,.mc_dma_rd_rsp_vld (mc_dma_rd_rsp_vld) //|> w + ,.mc_int_rd_rsp_ready (mc_int_rd_rsp_ready) //|> w + ); +assign dma_rd_rsp_vld = mc_dma_rd_rsp_vld; +assign dma_rd_rsp_pd = ({514{mc_dma_rd_rsp_vld}} & mc_dma_rd_rsp_pd); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"DMAIF: mcif and cvif should never return data both") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mc_dma_rd_rsp_vld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bdma2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + bdma2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1); + end +end +//================================== +//===Load Cmd from Context QUEUE +//================================== +// input rename +// ro = ri || !vo; // ready +// vo <0= (ro)? vi : vo; // valid +// do <= (ro && vi)? di : do; // data +assign ld2st_rd_prdy = (tran_dat_accept & is_last_beat & is_cube_last) || (!tran_cmd_valid); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_cmd_valid <= 1'b0; + end else begin + if ((ld2st_rd_prdy) == 1'b1) begin + tran_cmd_valid <= ld2st_rd_pvld; +// VCS coverage off + end else if ((ld2st_rd_prdy) == 1'b0) begin + end else begin + tran_cmd_valid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ld2st_rd_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign ld2st_rd_accept = ld2st_rd_prdy & ld2st_rd_pvld; +// PKT_UNPACK_WIRE( bdma_ld2st , ld2st_ , ld2st_rd_pd ) +assign ld2st_addr[63:0] = ld2st_rd_pd[63:0]; +assign ld2st_line_size[12:0] = ld2st_rd_pd[76:64]; +assign ld2st_cmd_src_ram_type = ld2st_rd_pd[77]; +assign ld2st_cmd_dst_ram_type = ld2st_rd_pd[78]; +assign ld2st_cmd_interrupt = ld2st_rd_pd[79]; +assign ld2st_cmd_interrupt_ptr = ld2st_rd_pd[80]; +assign ld2st_line_stride[26:0] = ld2st_rd_pd[107:81]; +assign ld2st_line_repeat_number[12:0] = ld2st_rd_pd[120:108]; +assign ld2st_surf_stride[26:0] = ld2st_rd_pd[147:121]; +assign ld2st_surf_repeat_number[12:0] = ld2st_rd_pd[160:148]; +always @(posedge nvdla_core_clk) begin + if (ld2st_rd_accept) begin +//reg_addr <= ld2st_addr; + reg_line_size <= ld2st_line_size; + reg_cmd_src_ram_type <= ld2st_cmd_src_ram_type; + reg_cmd_dst_ram_type <= ld2st_cmd_dst_ram_type; + reg_cmd_interrupt <= ld2st_cmd_interrupt; + reg_cmd_interrupt_ptr <= ld2st_cmd_interrupt_ptr; + reg_line_stride <= ld2st_line_stride; + reg_line_repeat_number <= ld2st_line_repeat_number; + reg_surf_stride <= ld2st_surf_stride; + reg_surf_repeat_number <= ld2st_surf_repeat_number; + end +end +assign dma_rd_cdt_lat_fifo_pop = dma_wr_dat_pvld & dma_wr_dat_rdy; +NV_NVDLA_BDMA_STORE_lat_fifo lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lat_fifo_wr_prdy (dma_rd_rsp_rdy) //|> w + ,.lat_fifo_wr_pvld (dma_rd_rsp_vld) //|< w + ,.lat_fifo_wr_pd (dma_rd_rsp_pd[513:0]) //|< w + ,.lat_fifo_rd_prdy (dma_wr_dat_rdy) //|< w + ,.lat_fifo_rd_pvld (dma_wr_dat_pvld) //|> w + ,.lat_fifo_rd_pd (dma_wr_dat_data[513:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//================================== +//===DMA WRITE DATA +//================================== +//===FLAG: cmd or data +//===LDC: first Command and follow with corespoing data +// Only when all beat is ready in r2w FIFO, wr_cmd will be sent +// and after cmd is sent, data will be sent to XXIF without bubble +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (tran_cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end else if (tran_dat_accept & is_last_beat) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end + end +end +//================================== +//===Beat Count +//================================== +assign beat_size = reg_line_size[12:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {12{1'b0}}; + end else begin + if (tran_dat_accept) begin + if (is_last_beat) begin + beat_count <= 0; + end else begin + beat_count <= beat_count + 1; + end + end + end +end +assign is_last_beat = (beat_count==beat_size); +//================================== +// Interrupt Handler +//================================== +NV_NVDLA_BDMA_STORE_fifo_intr u_fifo_intr ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fifo_intr_wr_idle (fifo_intr_wr_idle) //|> w + ,.fifo_intr_wr_pvld (fifo_intr_wr_pvld) //|< w + ,.fifo_intr_wr_pd (fifo_intr_wr_pd) //|< w + ,.fifo_intr_rd_prdy (fifo_intr_rd_prdy) //|< w + ,.fifo_intr_rd_pvld (fifo_intr_rd_pvld) //|> w + ,.fifo_intr_rd_pd (fifo_intr_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign fifo_intr_wr_pd = reg_cmd_interrupt_ptr; +assign fifo_intr_wr_pvld = dma_wr_cmd_vld & dma_wr_cmd_rdy & dma_wr_cmd_require_ack; +assign fifo_intr_rd_prdy = dma_wr_rsp_complete; +assign grp0_done = fifo_intr_rd_pvld & fifo_intr_rd_prdy & (fifo_intr_rd_pd==0); +assign grp1_done = fifo_intr_rd_pvld & fifo_intr_rd_prdy & (fifo_intr_rd_pd==1); +assign st2csb_grp0_done = grp0_done; +assign st2csb_grp1_done = grp1_done; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when write complete, intr_ptr should be already in the head of fifo_intr read side") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, !fifo_intr_rd_pvld & dma_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//================================== +//===DMA WRITE REQ +//================================== +// Line_addr is the start address of every line +// load a new one from CSB FIFO for every mem copy command +// will change every time one a block is done and jump to the next line +always @(posedge nvdla_core_clk) begin + if (ld2st_rd_accept) begin + line_addr <= ld2st_addr; + end else if (tran_dat_accept & is_last_beat) begin + if (is_surf_last) begin + {mon_line_addr_c,line_addr} <= surf_addr + (reg_surf_stride<<5); + end else begin + {mon_line_addr_c,line_addr} <= line_addr + (reg_line_stride<<5); + end + end +end +// Surf_addr is the base address of each surface +// will change every time one a block is done and jump to the next surface +always @(posedge nvdla_core_clk) begin + if (ld2st_rd_accept) begin + surf_addr <= ld2st_addr; + end else if (tran_dat_accept & is_last_beat) begin + if (is_surf_last) begin + {mon_surf_addr_c,surf_addr} <= surf_addr + (reg_surf_stride<<5); + end + end +end +//===TRAN SIZE +// for each DMA request, tran_size is to tell how many 32B DATA block indicated +// ===LINE COUNT +// count++ when just to next line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_count <= {13{1'b0}}; + end else begin + if (tran_dat_accept & is_last_beat) begin + if (is_surf_last) begin + line_count <= 0; + end else begin + line_count <= line_count + 1; + end + end + end +end +// SURF COUNT +// count++ when just to next surf +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_count <= {13{1'b0}}; + end else begin + if (tran_dat_accept & is_last_beat) begin + if (is_cube_last) begin + surf_count <= 0; + end else if (is_surf_last) begin + surf_count <= surf_count + 1; + end + end + end +end +//===Require ACK +assign is_surf_last = (line_count==reg_line_repeat_number); +assign is_cube_last = (surf_count==reg_surf_repeat_number) && is_surf_last; +//===DMA WRITE OUT +assign dma_wr_cmd_rdy = dma_wr_req_rdy & cmd_en; +assign dma_wr_dat_rdy = dma_wr_req_rdy & dat_en; +assign tran_cmd_accept = dma_wr_cmd_rdy & dma_wr_req_vld; +assign tran_dat_accept = dma_wr_dat_rdy & dma_wr_req_vld; +//DMA WRITE req : cmd +assign dma_wr_cmd_vld = cmd_en & tran_cmd_valid; +assign dma_wr_cmd_addr = line_addr; +assign dma_wr_cmd_size = reg_line_size; +assign dma_wr_cmd_require_ack = reg_cmd_interrupt & is_cube_last; +// PKT_PACK_WIRE( dma_write_cmd , dma_wr_cmd_ , dma_wr_cmd_pd ) +assign dma_wr_cmd_pd[63:0] = dma_wr_cmd_addr[63:0]; +assign dma_wr_cmd_pd[76:64] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[77] = dma_wr_cmd_require_ack ; +//DMA WRITE req : data +assign dma_wr_dat_vld = dat_en & dma_wr_dat_pvld; +//assign dma_wr_dat_data = lat_fifo_rd_pd; +assign dma_wr_dat_mask = (reg_line_size[0]==0 && is_last_beat) ? 2'b01 : 2'b11; +// PKT_PACK_WIRE( dma_write_data , dma_wr_dat_ , dma_wr_dat_pd ) +assign dma_wr_dat_pd[511:0] = dma_wr_dat_data[511:0]; +assign dma_wr_dat_pd[513:512] = dma_wr_dat_mask[1:0]; +// req: cmd|data +assign dma_wr_req_vld = dma_wr_cmd_vld | dma_wr_dat_vld; +always @( + cmd_en + or dma_wr_cmd_pd + or dma_wr_dat_pd + ) begin + dma_wr_req_pd = 0; + if (cmd_en) begin + dma_wr_req_pd[77:0] = dma_wr_cmd_pd; + dma_wr_req_pd[514:514] = 1'd0 /* PKT_nvdla_dma_wr_req_dma_write_cmd_ID */ ; + end else begin + dma_wr_req_pd[513:0] = dma_wr_dat_pd; + dma_wr_req_pd[514:514] = 1'd1 /* PKT_nvdla_dma_wr_req_dma_write_data_ID */ ; + end +end +//DMA WRITE req : pkt : cmd+data +assign dma_wr_req_ram_type = reg_cmd_dst_ram_type; +// wr Channel: Request +assign mc_dma_wr_req_vld = dma_wr_req_vld & (dma_wr_req_ram_type == 1'b1); +assign mc_wr_req_rdyi = mc_dma_wr_req_rdy & (dma_wr_req_ram_type == 1'b1); +assign wr_req_rdyi = mc_wr_req_rdyi; +assign dma_wr_req_rdy= wr_req_rdyi; +NV_NVDLA_BDMA_STORE_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma_wr_req_pd (dma_wr_req_pd[514:0]) //|< r + ,.mc_dma_wr_req_vld (mc_dma_wr_req_vld) //|< w + ,.mc_int_wr_req_ready (mc_int_wr_req_ready) //|< w + ,.mc_dma_wr_req_rdy (mc_dma_wr_req_rdy) //|> w + ,.mc_int_wr_req_pd (mc_int_wr_req_pd[514:0]) //|> w + ,.mc_int_wr_req_valid (mc_int_wr_req_valid) //|> w + ); +assign mc_int_wr_req_valid_d0 = mc_int_wr_req_valid; +assign mc_int_wr_req_ready = mc_int_wr_req_ready_d0; +assign mc_int_wr_req_pd_d0[514:0] = mc_int_wr_req_pd[514:0]; +assign bdma2mcif_wr_req_valid = mc_int_wr_req_valid_d0; +assign mc_int_wr_req_ready_d0 = bdma2mcif_wr_req_ready; +assign bdma2mcif_wr_req_pd[514:0] = mc_int_wr_req_pd_d0[514:0]; +// wr Channel: Response +assign mc_int_wr_rsp_complete = mcif2bdma_wr_rsp_complete; +assign require_ack = (dma_wr_req_pd[514:514]==0) & (dma_wr_req_pd[77:77]==1); +assign ack_raw_vld = dma_wr_req_vld & wr_req_rdyi & require_ack; +assign ack_raw_id = dma_wr_req_ram_type; +// stage1: bot +assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld; +always @(posedge nvdla_core_clk) begin + if ((ack_raw_vld & ack_raw_rdy) == 1'b1) begin + ack_bot_id <= ack_raw_id; +// VCS coverage off + end else if ((ack_raw_vld & ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_bot_vld <= 1'b0; + end else begin + if ((ack_raw_rdy) == 1'b1) begin + ack_bot_vld <= ack_raw_vld; +// VCS coverage off + end else if ((ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_raw_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"dmaif bot never push back") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, ack_raw_vld & !ack_raw_rdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// stage2: top +assign ack_bot_rdy = ack_top_rdy || !ack_top_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_id <= 1'b0; + end else begin + if ((ack_bot_vld & ack_bot_rdy) == 1'b1) begin + ack_top_id <= ack_bot_id; +// VCS coverage off + end else if ((ack_bot_vld & ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_vld & ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_vld <= 1'b0; + end else begin + if ((ack_bot_rdy) == 1'b1) begin + ack_top_vld <= ack_bot_vld; +// VCS coverage off + end else if ((ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign ack_top_rdy = releasing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_dma_wr_rsp_complete <= 1'b0; + end else begin + mc_dma_wr_rsp_complete <= mc_int_wr_rsp_complete; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_wr_rsp_complete <= 1'b0; + end else begin + dma_wr_rsp_complete <= releasing; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_pending <= 1'b0; + end else begin + if (ack_top_id==0) begin + if (mc_dma_wr_rsp_complete) begin + mc_pending <= 1'b1; + end + end else if (ack_top_id==1) begin + if (mc_pending) begin + mc_pending <= 1'b0; + end + end + end +end +assign mc_releasing = ack_top_id==1'b1 & (mc_dma_wr_rsp_complete | mc_pending); +assign releasing = mc_releasing; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no release both together") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, mc_releasing ); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no mc resp back and pending together") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, mc_pending & mc_dma_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no ack_top_vld when resp from mc") zzz_assert_never_12x (nvdla_core_clk, `ASSERT_RESET, (mc_pending | mc_dma_wr_rsp_complete) & !ack_top_vld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property dmaif_bdma__two_completes__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete; + endproperty +// Cover 0 : "mc_dma_wr_rsp_complete & cv_dma_wr_rsp_complete" + FUNCPOINT_dmaif_bdma__two_completes__0_COV : cover property (dmaif_bdma__two_completes__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__one_pending_complete_with_mc__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete; + endproperty +// Cover 1 : "cv_pending & mc_dma_wr_rsp_complete" + FUNCPOINT_dmaif_bdma__one_pending_complete_with_mc__1_COV : cover property (dmaif_bdma__one_pending_complete_with_mc__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__one_pending_complete_with_cv__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_pending; + endproperty +// Cover 2 : "mc_pending & cv_dma_wr_rsp_complete" + FUNCPOINT_dmaif_bdma__one_pending_complete_with_cv__2_COV : cover property (dmaif_bdma__one_pending_complete_with_cv__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_in_order__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete & ack_top_id==1'b1; + endproperty +// Cover 3 : "cv_int_wr_rsp_complete & mc_dma_wr_rsp_complete & ack_top_id==1'b1" + FUNCPOINT_dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_in_order__3_COV : cover property (dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_in_order__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_out_of_order__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_dma_wr_rsp_complete & ack_top_id==1'b0; + endproperty +// Cover 4 : "cv_int_wr_rsp_complete & mc_dma_wr_rsp_complete & ack_top_id==1'b0" + FUNCPOINT_dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_out_of_order__4_COV : cover property (dmaif_bdma__sequence_complete_cv_one_cycle_after_mc_out_of_order__4_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_in_order__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_int_wr_rsp_complete & ack_top_id==1'b0; + endproperty +// Cover 5 : "mc_int_wr_rsp_complete & cv_dma_wr_rsp_complete & ack_top_id==1'b0" + FUNCPOINT_dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_in_order__5_COV : cover property (dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_in_order__5_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_out_of_order__6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + mc_int_wr_rsp_complete & ack_top_id==1'b1; + endproperty +// Cover 6 : "mc_int_wr_rsp_complete & cv_dma_wr_rsp_complete & ack_top_id==1'b1" + FUNCPOINT_dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_out_of_order__6_COV : cover property (dmaif_bdma__sequence_complete_mc_one_cycle_after_cv_out_of_order__6_cov); + `endif +`endif +//VCS coverage on +//====================================== +// STATUS +//====================================== +// STATUS stall count +assign dma_write_stall_count_inc = dma_wr_req_vld & !dma_wr_req_rdy; + assign dma_write_stall_count_dec = 1'b0; +// stl adv logic + always @( + dma_write_stall_count_inc + or dma_write_stall_count_dec + ) begin + stl_adv = dma_write_stall_count_inc ^ dma_write_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or dma_write_stall_count_inc + or dma_write_stall_count_dec + or stl_adv + or dma_wr_rsp_complete + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (dma_write_stall_count_inc && !dma_write_stall_count_dec)? stl_cnt_inc : (!dma_write_stall_count_inc && dma_write_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (dma_wr_rsp_complete)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (dma_write_stall_count_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + dma_write_stall_count[31:0] = stl_cnt_cur[31:0]; + end +// STATUS IDLE +assign st_idle = fifo_intr_wr_idle & !tran_cmd_valid; +assign st2csb_idle = st_idle; +assign st2ld_load_idle = cmd_en & !tran_cmd_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + st2gate_slcg_en <= 1'b0; + end else begin + st2gate_slcg_en <= !st_idle; + end +end +//====================================== +// OBS +//assign obs_bus_bdma_store_ack_bot_vld = ack_bot_vld; +//assign obs_bus_bdma_store_ack_top_vld = ack_top_vld; +//assign obs_bus_bdma_store_ack_pending = releasing; +//assign obs_bus_bdma_store_ack_release = releasing; +//assign obs_bus_bdma_store_cmd_en = cmd_en; +//assign obs_bus_bdma_store_dat_en = dat_en; +//assign obs_bus_bdma_store_cv_rd_rsp_rdy = dma_rd_rsp_rdy; +//assign obs_bus_bdma_store_cv_rd_rsp_vld = cv_dma_rd_rsp_vld; +//assign obs_bus_bdma_store_cv_wr_req_rdy = cv_dma_wr_req_rdy; +//assign obs_bus_bdma_store_cv_wr_req_vld = cv_dma_wr_req_vld; +//assign obs_bus_bdma_store_cv_wr_rsp_complete = cv_dma_wr_rsp_complete; +//assign obs_bus_bdma_store_grp0_done = grp0_done; +//assign obs_bus_bdma_store_grp1_done = grp1_done; +//assign obs_bus_bdma_store_idle = st_idle; +//assign obs_bus_bdma_store_is_cube_last = is_cube_last; +//assign obs_bus_bdma_store_is_surf_last = is_surf_last; +//assign obs_bus_bdma_store_lat_fifo_rd_prdy = lat_fifo_rd_prdy; +//assign obs_bus_bdma_store_lat_fifo_rd_pvld = lat_fifo_rd_pvld; +//assign obs_bus_bdma_store_lat_fifo_wr_prdy = lat_fifo_wr_prdy; +//assign obs_bus_bdma_store_lat_fifo_wr_pvld = lat_fifo_wr_pvld; +//assign obs_bus_bdma_store_mc_rd_rsp_rdy = dma_rd_rsp_rdy; +//assign obs_bus_bdma_store_mc_rd_rsp_vld = mc_dma_rd_rsp_vld; +//assign obs_bus_bdma_store_mc_wr_req_rdy = mc_dma_wr_req_rdy; +//assign obs_bus_bdma_store_mc_wr_req_vld = mc_dma_wr_req_vld; +//assign obs_bus_bdma_store_mc_wr_rsp_complete = mc_dma_wr_rsp_complete; +endmodule // NV_NVDLA_BDMA_store +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os mc_dma_rd_rsp_pd (mc_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= mc_int_rd_rsp_pd[513:0] (mc_int_rd_rsp_valid,mc_int_rd_rsp_ready) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_STORE_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_rsp_rdy + ,mc_int_rd_rsp_pd + ,mc_int_rd_rsp_valid + ,mc_dma_rd_rsp_pd + ,mc_dma_rd_rsp_vld + ,mc_int_rd_rsp_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dma_rd_rsp_rdy; +input [513:0] mc_int_rd_rsp_pd; +input mc_int_rd_rsp_valid; +output [513:0] mc_dma_rd_rsp_pd; +output mc_dma_rd_rsp_vld; +output mc_int_rd_rsp_ready; +reg [513:0] mc_dma_rd_rsp_pd; +reg mc_dma_rd_rsp_vld; +reg mc_int_rd_rsp_ready; +reg [513:0] p1_pipe_data; +reg [513:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [513:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [513:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_int_rd_rsp_valid + or p1_pipe_rand_ready + or mc_int_rd_rsp_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = p1_pipe_rand_ready; + p1_pipe_rand_data = mc_int_rd_rsp_pd[513:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : mc_int_rd_rsp_pd[513:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_int_rd_rsp_valid + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_int_rd_rsp_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_pipe_rand_valid)? p1_pipe_rand_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_pipe_rand_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or dma_rd_rsp_rdy + or p1_pipe_skid_data + ) begin + mc_dma_rd_rsp_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = dma_rd_rsp_rdy; + mc_dma_rd_rsp_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_dma_rd_rsp_vld^dma_rd_rsp_rdy^mc_int_rd_rsp_valid^mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (mc_int_rd_rsp_valid && !mc_int_rd_rsp_ready), (mc_int_rd_rsp_valid), (mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_STORE_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cv_dma_rd_rsp_pd (cv_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= cv_int_rd_rsp_pd[513:0] (cv_int_rd_rsp_valid,cv_int_rd_rsp_ready) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_wr_req_pd (mc_int_wr_req_valid,mc_int_wr_req_ready) <= dma_wr_req_pd[514:0] (mc_dma_wr_req_vld,mc_dma_wr_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_BDMA_STORE_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_wr_req_pd + ,mc_dma_wr_req_vld + ,mc_int_wr_req_ready + ,mc_dma_wr_req_rdy + ,mc_int_wr_req_pd + ,mc_int_wr_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [514:0] dma_wr_req_pd; +input mc_dma_wr_req_vld; +input mc_int_wr_req_ready; +output mc_dma_wr_req_rdy; +output [514:0] mc_int_wr_req_pd; +output mc_int_wr_req_valid; +reg mc_dma_wr_req_rdy; +reg [514:0] mc_int_wr_req_pd; +reg mc_int_wr_req_valid; +reg [514:0] p3_pipe_data; +reg [514:0] p3_pipe_rand_data; +reg p3_pipe_rand_ready; +reg p3_pipe_rand_valid; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [514:0] p3_skid_data; +reg [514:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) randomizer +`ifndef SYNTHESIS +reg p3_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p3_pipe_rand_active + or + `endif + mc_dma_wr_req_vld + or p3_pipe_rand_ready + or dma_wr_req_pd + ) begin + `ifdef SYNTHESIS + p3_pipe_rand_valid = mc_dma_wr_req_vld; + mc_dma_wr_req_rdy = p3_pipe_rand_ready; + p3_pipe_rand_data = dma_wr_req_pd[514:0]; + `else +// VCS coverage off + p3_pipe_rand_valid = (p3_pipe_rand_active)? 1'b0 : mc_dma_wr_req_vld; + mc_dma_wr_req_rdy = (p3_pipe_rand_active)? 1'b0 : p3_pipe_rand_ready; + p3_pipe_rand_data = (p3_pipe_rand_active)? 'bx : dma_wr_req_pd[514:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p3_pipe_stall_cycles; +integer p3_pipe_stall_probability; +integer p3_pipe_stall_cycles_min; +integer p3_pipe_stall_cycles_max; +initial begin + p3_pipe_stall_cycles = 0; + p3_pipe_stall_probability = 0; + p3_pipe_stall_cycles_min = 1; + p3_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_probability" ) ) p3_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_min" ) ) p3_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_store_pipe_stall_cycles_max" ) ) p3_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p3_pipe_rand_enable; +reg p3_pipe_rand_poised; +always @( + p3_pipe_stall_cycles + or p3_pipe_stall_probability + or mc_dma_wr_req_vld + ) begin + p3_pipe_rand_active = p3_pipe_stall_cycles != 0; + p3_pipe_rand_enable = p3_pipe_stall_probability != 0; + p3_pipe_rand_poised = p3_pipe_rand_enable && !p3_pipe_rand_active && mc_dma_wr_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_stall_cycles <= 1'b0; + end else begin + if (p3_pipe_rand_poised) begin + if (p3_pipe_stall_probability >= prand_inst0(1, 100)) begin + p3_pipe_stall_cycles <= prand_inst1(p3_pipe_stall_cycles_min, p3_pipe_stall_cycles_max); + end + end else if (p3_pipe_rand_active) begin + p3_pipe_stall_cycles <= p3_pipe_stall_cycles - 1; + end else begin + p3_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (3) skid buffer +always @( + p3_pipe_rand_valid + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = p3_pipe_rand_valid && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + p3_pipe_rand_ready <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + p3_pipe_rand_ready <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? p3_pipe_rand_data : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or p3_pipe_rand_valid + or p3_skid_valid + or p3_pipe_rand_data + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? p3_pipe_rand_valid : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? p3_pipe_rand_data : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or mc_int_wr_req_ready + or p3_pipe_data + ) begin + mc_int_wr_req_valid = p3_pipe_valid; + p3_pipe_ready = mc_int_wr_req_ready; + mc_int_wr_req_pd = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_wr_req_valid^mc_int_wr_req_ready^mc_dma_wr_req_vld^mc_dma_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_18x (nvdla_core_clk, `ASSERT_RESET, (mc_dma_wr_req_vld && !mc_dma_wr_req_rdy), (mc_dma_wr_req_vld), (mc_dma_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_BDMA_STORE_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_wr_req_pd (cv_int_wr_req_valid,cv_int_wr_req_ready) <= dma_wr_req_pd[514:0] (cv_dma_wr_req_vld,cv_dma_wr_req_rdy) +// ************************************************************************************************************** +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_STORE_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_fifo_wr -rd_pipebus lat_fifo_rd -rd_reg -d 245 -w 514 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_STORE_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_fifo_wr_prdy + , lat_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_fifo_wr_pause +`endif + , lat_fifo_wr_pd + , lat_fifo_rd_prdy + , lat_fifo_rd_pvld + , lat_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_fifo_wr_prdy; +input lat_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_fifo_wr_pause; +`endif +input [513:0] lat_fifo_wr_pd; +input lat_fifo_rd_prdy; +output lat_fifo_rd_pvld; +output [513:0] lat_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_fifo_wr_busy_int; // copy for internal use +assign lat_fifo_wr_prdy = !lat_fifo_wr_busy_int; +assign wr_reserving = lat_fifo_wr_pvld && !lat_fifo_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] lat_fifo_wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? lat_fifo_wr_count : (lat_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_fifo_wr_count + 1'd1) : lat_fifo_wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_245 = ( wr_count_next_no_wr_popping == 8'd245 ); +wire wr_count_next_is_245 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_245; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_fifo_wr_busy_next = wr_count_next_is_245 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_fifo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_fifo_wr_busy_next = wr_count_next_is_245 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_wr_busy_int <= 1'b0; + lat_fifo_wr_count <= 8'd0; + end else begin + lat_fifo_wr_busy_int <= lat_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_fifo_wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_fifo_wr_pvld +// +// RAM +// +reg [7:0] lat_fifo_wr_adr; // current write address +wire [7:0] lat_fifo_rd_adr_p; // read address to use for ram +wire [513:0] lat_fifo_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_245x514 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_fifo_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_fifo_wr_pd ) + , .ra ( lat_fifo_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_fifo_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_fifo_wr_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (lat_fifo_wr_adr == 8'd244) ? 8'd0 : (lat_fifo_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_wr_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + lat_fifo_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_fifo_wr_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] lat_fifo_rd_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (lat_fifo_rd_adr == 8'd244) ? 8'd0 : (lat_fifo_rd_adr + 1'd1); // spyglass disable W484 +assign lat_fifo_rd_adr_p = rd_popping ? rd_adr_next : lat_fifo_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_rd_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + lat_fifo_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_fifo_rd_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_fifo_rd_pvld_p; // data out of fifo is valid +reg lat_fifo_rd_pvld_int; // internal copy of lat_fifo_rd_pvld +assign lat_fifo_rd_pvld = lat_fifo_rd_pvld_int; +assign rd_popping = lat_fifo_rd_pvld_p && !(lat_fifo_rd_pvld_int && !lat_fifo_rd_prdy); +reg [7:0] lat_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? lat_fifo_rd_count_p : + (lat_fifo_rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_fifo_rd_count_p + 1'd1) : + lat_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_fifo_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_rd_count_p <= 8'd0; + lat_fifo_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_fifo_rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_fifo_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_fifo_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_fifo_rd_pvld_p || (lat_fifo_rd_pvld_int && !lat_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_fifo_rd_pvld_int <= 1'b0; + end else begin + lat_fifo_rd_pvld_int <= rd_req_next; + end +end +assign lat_fifo_rd_pd = lat_fifo_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_fifo_wr_pvld && !lat_fifo_wr_busy_int) || (lat_fifo_wr_busy_int != lat_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (lat_fifo_rd_pvld_int && lat_fifo_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_fifo_wr_pvld && !(!lat_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd245 : wr_limit_reg} ) + , .curr ( {24'd0, lat_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_STORE_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_BDMA_STORE_lat_fifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_STORE_fifo_r2w -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus fifo_r2w_wr -rd_pipebus fifo_r2w_rd -rd_reg -d 4 -w 514 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_STORE_fifo_r2w ( + nvdla_core_clk + , nvdla_core_rstn + , fifo_r2w_wr_prdy + , fifo_r2w_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , fifo_r2w_wr_pause +`endif + , fifo_r2w_wr_pd + , fifo_r2w_rd_prdy + , fifo_r2w_rd_pvld + , fifo_r2w_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output fifo_r2w_wr_prdy; +input fifo_r2w_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input fifo_r2w_wr_pause; +`endif +input [513:0] fifo_r2w_wr_pd; +input fifo_r2w_rd_prdy; +output fifo_r2w_rd_pvld; +output [513:0] fifo_r2w_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg fifo_r2w_wr_busy_int; // copy for internal use +assign fifo_r2w_wr_prdy = !fifo_r2w_wr_busy_int; +assign wr_reserving = fifo_r2w_wr_pvld && !fifo_r2w_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [2:0] fifo_r2w_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? fifo_r2w_wr_count : (fifo_r2w_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (fifo_r2w_wr_count + 1'd1) : fifo_r2w_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire fifo_r2w_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check fifo_r2w_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || fifo_r2w_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire fifo_r2w_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check fifo_r2w_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_wr_busy_int <= 1'b0; + fifo_r2w_wr_count <= 3'd0; + end else begin + fifo_r2w_wr_busy_int <= fifo_r2w_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + fifo_r2w_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + fifo_r2w_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as fifo_r2w_wr_pvld +// +// RAM +// +reg [1:0] fifo_r2w_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + fifo_r2w_wr_adr <= fifo_r2w_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] fifo_r2w_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [513:0] fifo_r2w_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( fifo_r2w_wr_pd ) + , .we ( ram_we ) + , .wa ( fifo_r2w_wr_adr ) + , .ra ( fifo_r2w_rd_adr ) + , .dout ( fifo_r2w_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = fifo_r2w_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + fifo_r2w_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + fifo_r2w_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg fifo_r2w_rd_pvld_p; // data out of fifo is valid +reg fifo_r2w_rd_pvld_int; // internal copy of fifo_r2w_rd_pvld +assign fifo_r2w_rd_pvld = fifo_r2w_rd_pvld_int; +assign rd_popping = fifo_r2w_rd_pvld_p && !(fifo_r2w_rd_pvld_int && !fifo_r2w_rd_prdy); +reg [2:0] fifo_r2w_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? fifo_r2w_rd_count_p : + (fifo_r2w_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (fifo_r2w_rd_count_p + 1'd1) : + fifo_r2w_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_rd_count_p <= 3'd0; + fifo_r2w_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + fifo_r2w_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + fifo_r2w_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + fifo_r2w_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + fifo_r2w_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [513:0] fifo_r2w_rd_pd; // output data register +wire rd_req_next = (fifo_r2w_rd_pvld_p || (fifo_r2w_rd_pvld_int && !fifo_r2w_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_r2w_rd_pvld_int <= 1'b0; + end else begin + fifo_r2w_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + fifo_r2w_rd_pd <= fifo_r2w_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + fifo_r2w_rd_pd <= {514{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (fifo_r2w_wr_pvld && !fifo_r2w_wr_busy_int) || (fifo_r2w_wr_busy_int != fifo_r2w_wr_busy_next)) || (rd_pushing || rd_popping || (fifo_r2w_rd_pvld_int && fifo_r2w_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_BDMA_STORE_fifo_r2w_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( fifo_r2w_wr_pvld && !(!fifo_r2w_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, fifo_r2w_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_STORE_fifo_r2w") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_BDMA_STORE_fifo_r2w +// +// Flop-Based RAM +// +module NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [513:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [513:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [513:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [513:0] ram_ff0; +reg [513:0] ram_ff1; +reg [513:0] ram_ff2; +reg [513:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [513:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {514{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [513:0] Di0; +input [1:0] Ra0; +output [513:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 514'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [513:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [513:0] Q0 = mem[0]; +wire [513:0] Q1 = mem[1]; +wire [513:0] Q2 = mem[2]; +wire [513:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514] } +endmodule // vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +//vmw: Memory vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +//vmw: Address-size 2 +//vmw: Data-size 514 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[513:0] data0[513:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[513:0] data1[513:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_BDMA_STORE_fifo_intr -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus fifo_intr_wr -rd_pipebus fifo_intr_rd -ram_bypass -d 0 -rd_reg -wr_idle -rd_busy_reg -no_wr_busy -w 1 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_BDMA_STORE_fifo_intr ( + nvdla_core_clk + , nvdla_core_rstn + , fifo_intr_wr_idle + , fifo_intr_wr_pvld + , fifo_intr_wr_pd + , fifo_intr_rd_prdy + , fifo_intr_rd_pvld + , fifo_intr_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output fifo_intr_wr_idle; +input fifo_intr_wr_pvld; +input fifo_intr_wr_pd; +input fifo_intr_rd_prdy; +output fifo_intr_rd_pvld; +output fifo_intr_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] fifo_intr_rd_pd_p = fifo_intr_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg fifo_intr_rd_prdy_d; // fifo_intr_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_intr_rd_prdy_d <= 1'b1; + end else begin + fifo_intr_rd_prdy_d <= fifo_intr_rd_prdy; + end +end +wire fifo_intr_rd_prdy_d_o; // combinatorial rd_busy +reg fifo_intr_rd_pvld_int; // internal copy of fifo_intr_rd_pvld +assign fifo_intr_rd_pvld = fifo_intr_rd_pvld_int; +wire fifo_intr_rd_pvld_p = fifo_intr_wr_pvld ; // no real fifo, take from write-side input +reg fifo_intr_rd_pvld_int_o; // internal copy of fifo_intr_rd_pvld_o +wire fifo_intr_rd_pvld_o = fifo_intr_rd_pvld_int_o; +wire rd_popping = fifo_intr_rd_pvld_p && !(fifo_intr_rd_pvld_int_o && !fifo_intr_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg fifo_intr_rd_pd_o; // output data register +wire rd_req_next_o = (fifo_intr_rd_pvld_p || (fifo_intr_rd_pvld_int_o && !fifo_intr_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_intr_rd_pvld_int_o <= 1'b0; + end else begin + fifo_intr_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (fifo_intr_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + fifo_intr_rd_pd_o <= fifo_intr_rd_pd_p; + end +//synopsys translate_off + else if ( !((fifo_intr_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + fifo_intr_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg fifo_intr_rd_pd; // output data register +reg fifo_intr_rd_pvld_int_d; // so we can bubble-collapse fifo_intr_rd_prdy_d +assign fifo_intr_rd_prdy_d_o = !((fifo_intr_rd_pvld_o && fifo_intr_rd_pvld_int_d && !fifo_intr_rd_prdy_d ) ); +wire rd_req_next = (!fifo_intr_rd_prdy_d_o ? fifo_intr_rd_pvld_o : fifo_intr_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + fifo_intr_rd_pvld_int <= 1'b0; + fifo_intr_rd_pvld_int_d <= 1'b0; + end else begin + if ( !fifo_intr_rd_pvld_int || fifo_intr_rd_prdy ) begin + fifo_intr_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!fifo_intr_rd_pvld_int || fifo_intr_rd_prdy) ) begin + end else begin + fifo_intr_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + fifo_intr_rd_pvld_int_d <= fifo_intr_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!fifo_intr_rd_pvld_int || fifo_intr_rd_prdy ) ) begin + case (!fifo_intr_rd_prdy_d_o) + 1'b0: fifo_intr_rd_pd <= fifo_intr_rd_pd_p; + 1'b1: fifo_intr_rd_pd <= fifo_intr_rd_pd_o; +//VCS coverage off + default: fifo_intr_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!fifo_intr_rd_pvld_int || fifo_intr_rd_prdy)) ) begin + end else begin + fifo_intr_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// +// Read-side Idle Calculation +// +wire rd_idle = !fifo_intr_rd_pvld_int_o && !fifo_intr_rd_pvld_int; +// +// Write-Side Idle Calculation +// +wire fifo_intr_wr_idle_d0 = !fifo_intr_wr_pvld && rd_idle; +wire fifo_intr_wr_idle = fifo_intr_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (fifo_intr_wr_pvld || (fifo_intr_rd_pvld_int && fifo_intr_rd_prdy_d) || (fifo_intr_rd_pvld_int_o && fifo_intr_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_BDMA_STORE_fifo_intr") true +// synopsys dc_script_end +endmodule // NV_NVDLA_BDMA_STORE_fifo_intr diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_bdma.v b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_bdma.v new file mode 100644 index 0000000..4479025 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_bdma.v @@ -0,0 +1,215 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_bdma.v +module NV_NVDLA_bdma ( + bdma2mcif_rd_req_ready //|< i + ,bdma2mcif_wr_req_ready //|< i + ,csb2bdma_req_pd //|< i + ,csb2bdma_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,mcif2bdma_rd_rsp_pd //|< i + ,mcif2bdma_rd_rsp_valid //|< i + ,mcif2bdma_wr_rsp_complete //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,bdma2csb_resp_pd //|> o + ,bdma2csb_resp_valid //|> o + ,bdma2glb_done_intr_pd //|> o + ,bdma2mcif_rd_cdt_lat_fifo_pop //|> o + ,bdma2mcif_rd_req_pd //|> o + ,bdma2mcif_rd_req_valid //|> o + ,bdma2mcif_wr_req_pd //|> o + ,bdma2mcif_wr_req_valid //|> o + ,csb2bdma_req_prdy //|> o + ,mcif2bdma_rd_rsp_ready //|> o + ); +// +// NV_NVDLA_bdma_ports.v +// +input nvdla_core_clk; /* bdma2csb_resp, bdma2cvif_rd_cdt, bdma2cvif_rd_req, bdma2cvif_wr_req, bdma2glb_done_intr, bdma2mcif_rd_cdt, bdma2mcif_rd_req, bdma2mcif_wr_req, csb2bdma_req, cvif2bdma_rd_rsp, cvif2bdma_wr_rsp, mcif2bdma_rd_rsp, mcif2bdma_wr_rsp */ +input nvdla_core_rstn; /* bdma2csb_resp, bdma2cvif_rd_cdt, bdma2cvif_rd_req, bdma2cvif_wr_req, bdma2glb_done_intr, bdma2mcif_rd_cdt, bdma2mcif_rd_req, bdma2mcif_wr_req, csb2bdma_req, cvif2bdma_rd_rsp, cvif2bdma_wr_rsp, mcif2bdma_rd_rsp, mcif2bdma_wr_rsp */ +output bdma2csb_resp_valid; /* data valid */ +output [33:0] bdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] bdma2glb_done_intr_pd; +output bdma2mcif_rd_cdt_lat_fifo_pop; +output bdma2mcif_rd_req_valid; /* data valid */ +input bdma2mcif_rd_req_ready; /* data return handshake */ +output [78:0] bdma2mcif_rd_req_pd; +output bdma2mcif_wr_req_valid; /* data valid */ +input bdma2mcif_wr_req_ready; /* data return handshake */ +output [514:0] bdma2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ +input csb2bdma_req_pvld; /* data valid */ +output csb2bdma_req_prdy; /* data return handshake */ +input [62:0] csb2bdma_req_pd; +input mcif2bdma_rd_rsp_valid; /* data valid */ +output mcif2bdma_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2bdma_rd_rsp_pd; +input mcif2bdma_wr_rsp_complete; +input [31:0] pwrbus_ram_pd; +//&Ports /^obs_bus/; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire csb2gate_slcg_en; +wire csb2ld_rdy; +wire csb2ld_vld; +wire [31:0] dma_write_stall_count; +wire dma_write_stall_count_cen; +wire ld2csb_grp0_dma_stall_inc; +wire ld2csb_grp1_dma_stall_inc; +wire ld2csb_idle; +wire ld2gate_slcg_en; +wire [160:0] ld2st_rd_pd; +wire ld2st_rd_prdy; +wire ld2st_rd_pvld; +wire ld2st_wr_idle; +wire [160:0] ld2st_wr_pd; +wire ld2st_wr_prdy; +wire ld2st_wr_pvld; +wire nvdla_gated_clk; +wire reg2dp_cmd_dst_ram_type; +wire reg2dp_cmd_interrupt; +wire reg2dp_cmd_interrupt_ptr; +wire reg2dp_cmd_src_ram_type; +wire [31:0] reg2dp_dst_addr_high_v8; +wire [26:0] reg2dp_dst_addr_low_v32; +wire [26:0] reg2dp_dst_line_stride; +wire [26:0] reg2dp_dst_surf_stride; +wire [23:0] reg2dp_line_repeat_number; +wire [12:0] reg2dp_line_size; +wire [31:0] reg2dp_src_addr_high_v8; +wire [26:0] reg2dp_src_addr_low_v32; +wire [26:0] reg2dp_src_line_stride; +wire [26:0] reg2dp_src_surf_stride; +wire [23:0] reg2dp_surf_repeat_number; +wire st2csb_grp0_done; +wire st2csb_grp1_done; +wire st2csb_idle; +wire st2gate_slcg_en; +wire st2ld_load_idle; +// &Forget dangle .*; +NV_NVDLA_BDMA_csb u_csb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2bdma_req_pvld (csb2bdma_req_pvld) //|< i + ,.csb2bdma_req_prdy (csb2bdma_req_prdy) //|> o + ,.csb2bdma_req_pd (csb2bdma_req_pd[62:0]) //|< i + ,.bdma2csb_resp_valid (bdma2csb_resp_valid) //|> o + ,.bdma2csb_resp_pd (bdma2csb_resp_pd[33:0]) //|> o + ,.bdma2glb_done_intr_pd (bdma2glb_done_intr_pd[1:0]) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.st2csb_grp0_done (st2csb_grp0_done) //|< w + ,.st2csb_grp1_done (st2csb_grp1_done) //|< w + ,.st2csb_idle (st2csb_idle) //|< w + ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type) //|> w + ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt) //|> w + ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr) //|> w + ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type) //|> w + ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0]) //|> w + ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0]) //|> w + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0]) //|> w + ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0]) //|> w + ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0]) //|> w + ,.reg2dp_line_size (reg2dp_line_size[12:0]) //|> w + ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0]) //|> w + ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0]) //|> w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0]) //|> w + ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0]) //|> w + ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0]) //|> w + ,.csb2ld_rdy (csb2ld_rdy) //|< w + ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc) //|< w + ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc) //|< w + ,.ld2csb_idle (ld2csb_idle) //|< w + ,.csb2ld_vld (csb2ld_vld) //|> w + ,.csb2gate_slcg_en (csb2gate_slcg_en) //|> w + ,.dma_write_stall_count (dma_write_stall_count[31:0]) //|< w + ,.dma_write_stall_count_cen (dma_write_stall_count_cen) //|> w + ); +NV_NVDLA_BDMA_gate u_gate ( + .csb2gate_slcg_en (csb2gate_slcg_en) //|< w + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.ld2gate_slcg_en (ld2gate_slcg_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.st2gate_slcg_en (st2gate_slcg_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_BDMA_load u_load ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bdma2mcif_rd_req_valid (bdma2mcif_rd_req_valid) //|> o + ,.bdma2mcif_rd_req_ready (bdma2mcif_rd_req_ready) //|< i + ,.bdma2mcif_rd_req_pd (bdma2mcif_rd_req_pd[78:0]) //|> o + ,.ld2st_wr_pvld (ld2st_wr_pvld) //|> w + ,.ld2st_wr_prdy (ld2st_wr_prdy) //|< w + ,.ld2st_wr_pd (ld2st_wr_pd[160:0]) //|> w + ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type) //|< w + ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt) //|< w + ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr) //|< w + ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type) //|< w + ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0]) //|< w + ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0]) //|< w + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0]) //|< w + ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0]) //|< w + ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0]) //|< w + ,.reg2dp_line_size (reg2dp_line_size[12:0]) //|< w + ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0]) //|< w + ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0]) //|< w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0]) //|< w + ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0]) //|< w + ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0]) //|< w + ,.csb2ld_vld (csb2ld_vld) //|< w + ,.csb2ld_rdy (csb2ld_rdy) //|> w + ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc) //|> w + ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc) //|> w + ,.ld2csb_idle (ld2csb_idle) //|> w + ,.ld2st_wr_idle (ld2st_wr_idle) //|< w + ,.st2ld_load_idle (st2ld_load_idle) //|< w + ,.ld2gate_slcg_en (ld2gate_slcg_en) //|> w + ); +NV_NVDLA_BDMA_store u_store ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2bdma_rd_rsp_valid (mcif2bdma_rd_rsp_valid) //|< i + ,.mcif2bdma_rd_rsp_ready (mcif2bdma_rd_rsp_ready) //|> o + ,.mcif2bdma_rd_rsp_pd (mcif2bdma_rd_rsp_pd[513:0]) //|< i + ,.bdma2mcif_rd_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid) //|> o + ,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready) //|< i + ,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd[514:0]) //|> o + ,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete) //|< i + ,.ld2st_rd_pvld (ld2st_rd_pvld) //|< w + ,.ld2st_rd_prdy (ld2st_rd_prdy) //|> w + ,.ld2st_rd_pd (ld2st_rd_pd[160:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.st2ld_load_idle (st2ld_load_idle) //|> w + ,.st2csb_grp0_done (st2csb_grp0_done) //|> w + ,.st2csb_grp1_done (st2csb_grp1_done) //|> w + ,.st2csb_idle (st2csb_idle) //|> w + ,.st2gate_slcg_en (st2gate_slcg_en) //|> w + ,.dma_write_stall_count (dma_write_stall_count[31:0]) //|> w + ,.dma_write_stall_count_cen (dma_write_stall_count_cen) //|< w + ); +NV_NVDLA_BDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ld2st_wr_prdy (ld2st_wr_prdy) //|> w + ,.ld2st_wr_idle (ld2st_wr_idle) //|> w + ,.ld2st_wr_pvld (ld2st_wr_pvld) //|< w + ,.ld2st_wr_pd (ld2st_wr_pd[160:0]) //|< w + ,.ld2st_rd_prdy (ld2st_rd_prdy) //|< w + ,.ld2st_rd_pvld (ld2st_rd_pvld) //|> w + ,.ld2st_rd_pd (ld2st_rd_pd[160:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +endmodule // NV_NVDLA_bdma diff --git a/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_bdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_bdma.v.vcp new file mode 100644 index 0000000..4479025 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/bdma/NV_NVDLA_bdma.v.vcp @@ -0,0 +1,215 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_bdma.v +module NV_NVDLA_bdma ( + bdma2mcif_rd_req_ready //|< i + ,bdma2mcif_wr_req_ready //|< i + ,csb2bdma_req_pd //|< i + ,csb2bdma_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,mcif2bdma_rd_rsp_pd //|< i + ,mcif2bdma_rd_rsp_valid //|< i + ,mcif2bdma_wr_rsp_complete //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,bdma2csb_resp_pd //|> o + ,bdma2csb_resp_valid //|> o + ,bdma2glb_done_intr_pd //|> o + ,bdma2mcif_rd_cdt_lat_fifo_pop //|> o + ,bdma2mcif_rd_req_pd //|> o + ,bdma2mcif_rd_req_valid //|> o + ,bdma2mcif_wr_req_pd //|> o + ,bdma2mcif_wr_req_valid //|> o + ,csb2bdma_req_prdy //|> o + ,mcif2bdma_rd_rsp_ready //|> o + ); +// +// NV_NVDLA_bdma_ports.v +// +input nvdla_core_clk; /* bdma2csb_resp, bdma2cvif_rd_cdt, bdma2cvif_rd_req, bdma2cvif_wr_req, bdma2glb_done_intr, bdma2mcif_rd_cdt, bdma2mcif_rd_req, bdma2mcif_wr_req, csb2bdma_req, cvif2bdma_rd_rsp, cvif2bdma_wr_rsp, mcif2bdma_rd_rsp, mcif2bdma_wr_rsp */ +input nvdla_core_rstn; /* bdma2csb_resp, bdma2cvif_rd_cdt, bdma2cvif_rd_req, bdma2cvif_wr_req, bdma2glb_done_intr, bdma2mcif_rd_cdt, bdma2mcif_rd_req, bdma2mcif_wr_req, csb2bdma_req, cvif2bdma_rd_rsp, cvif2bdma_wr_rsp, mcif2bdma_rd_rsp, mcif2bdma_wr_rsp */ +output bdma2csb_resp_valid; /* data valid */ +output [33:0] bdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] bdma2glb_done_intr_pd; +output bdma2mcif_rd_cdt_lat_fifo_pop; +output bdma2mcif_rd_req_valid; /* data valid */ +input bdma2mcif_rd_req_ready; /* data return handshake */ +output [78:0] bdma2mcif_rd_req_pd; +output bdma2mcif_wr_req_valid; /* data valid */ +input bdma2mcif_wr_req_ready; /* data return handshake */ +output [514:0] bdma2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ +input csb2bdma_req_pvld; /* data valid */ +output csb2bdma_req_prdy; /* data return handshake */ +input [62:0] csb2bdma_req_pd; +input mcif2bdma_rd_rsp_valid; /* data valid */ +output mcif2bdma_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2bdma_rd_rsp_pd; +input mcif2bdma_wr_rsp_complete; +input [31:0] pwrbus_ram_pd; +//&Ports /^obs_bus/; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire csb2gate_slcg_en; +wire csb2ld_rdy; +wire csb2ld_vld; +wire [31:0] dma_write_stall_count; +wire dma_write_stall_count_cen; +wire ld2csb_grp0_dma_stall_inc; +wire ld2csb_grp1_dma_stall_inc; +wire ld2csb_idle; +wire ld2gate_slcg_en; +wire [160:0] ld2st_rd_pd; +wire ld2st_rd_prdy; +wire ld2st_rd_pvld; +wire ld2st_wr_idle; +wire [160:0] ld2st_wr_pd; +wire ld2st_wr_prdy; +wire ld2st_wr_pvld; +wire nvdla_gated_clk; +wire reg2dp_cmd_dst_ram_type; +wire reg2dp_cmd_interrupt; +wire reg2dp_cmd_interrupt_ptr; +wire reg2dp_cmd_src_ram_type; +wire [31:0] reg2dp_dst_addr_high_v8; +wire [26:0] reg2dp_dst_addr_low_v32; +wire [26:0] reg2dp_dst_line_stride; +wire [26:0] reg2dp_dst_surf_stride; +wire [23:0] reg2dp_line_repeat_number; +wire [12:0] reg2dp_line_size; +wire [31:0] reg2dp_src_addr_high_v8; +wire [26:0] reg2dp_src_addr_low_v32; +wire [26:0] reg2dp_src_line_stride; +wire [26:0] reg2dp_src_surf_stride; +wire [23:0] reg2dp_surf_repeat_number; +wire st2csb_grp0_done; +wire st2csb_grp1_done; +wire st2csb_idle; +wire st2gate_slcg_en; +wire st2ld_load_idle; +// &Forget dangle .*; +NV_NVDLA_BDMA_csb u_csb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2bdma_req_pvld (csb2bdma_req_pvld) //|< i + ,.csb2bdma_req_prdy (csb2bdma_req_prdy) //|> o + ,.csb2bdma_req_pd (csb2bdma_req_pd[62:0]) //|< i + ,.bdma2csb_resp_valid (bdma2csb_resp_valid) //|> o + ,.bdma2csb_resp_pd (bdma2csb_resp_pd[33:0]) //|> o + ,.bdma2glb_done_intr_pd (bdma2glb_done_intr_pd[1:0]) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.st2csb_grp0_done (st2csb_grp0_done) //|< w + ,.st2csb_grp1_done (st2csb_grp1_done) //|< w + ,.st2csb_idle (st2csb_idle) //|< w + ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type) //|> w + ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt) //|> w + ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr) //|> w + ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type) //|> w + ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0]) //|> w + ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0]) //|> w + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0]) //|> w + ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0]) //|> w + ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0]) //|> w + ,.reg2dp_line_size (reg2dp_line_size[12:0]) //|> w + ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0]) //|> w + ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0]) //|> w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0]) //|> w + ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0]) //|> w + ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0]) //|> w + ,.csb2ld_rdy (csb2ld_rdy) //|< w + ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc) //|< w + ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc) //|< w + ,.ld2csb_idle (ld2csb_idle) //|< w + ,.csb2ld_vld (csb2ld_vld) //|> w + ,.csb2gate_slcg_en (csb2gate_slcg_en) //|> w + ,.dma_write_stall_count (dma_write_stall_count[31:0]) //|< w + ,.dma_write_stall_count_cen (dma_write_stall_count_cen) //|> w + ); +NV_NVDLA_BDMA_gate u_gate ( + .csb2gate_slcg_en (csb2gate_slcg_en) //|< w + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.ld2gate_slcg_en (ld2gate_slcg_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.st2gate_slcg_en (st2gate_slcg_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_BDMA_load u_load ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bdma2mcif_rd_req_valid (bdma2mcif_rd_req_valid) //|> o + ,.bdma2mcif_rd_req_ready (bdma2mcif_rd_req_ready) //|< i + ,.bdma2mcif_rd_req_pd (bdma2mcif_rd_req_pd[78:0]) //|> o + ,.ld2st_wr_pvld (ld2st_wr_pvld) //|> w + ,.ld2st_wr_prdy (ld2st_wr_prdy) //|< w + ,.ld2st_wr_pd (ld2st_wr_pd[160:0]) //|> w + ,.reg2dp_cmd_dst_ram_type (reg2dp_cmd_dst_ram_type) //|< w + ,.reg2dp_cmd_interrupt (reg2dp_cmd_interrupt) //|< w + ,.reg2dp_cmd_interrupt_ptr (reg2dp_cmd_interrupt_ptr) //|< w + ,.reg2dp_cmd_src_ram_type (reg2dp_cmd_src_ram_type) //|< w + ,.reg2dp_dst_addr_high_v8 (reg2dp_dst_addr_high_v8[31:0]) //|< w + ,.reg2dp_dst_addr_low_v32 (reg2dp_dst_addr_low_v32[26:0]) //|< w + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[26:0]) //|< w + ,.reg2dp_dst_surf_stride (reg2dp_dst_surf_stride[26:0]) //|< w + ,.reg2dp_line_repeat_number (reg2dp_line_repeat_number[23:0]) //|< w + ,.reg2dp_line_size (reg2dp_line_size[12:0]) //|< w + ,.reg2dp_src_addr_high_v8 (reg2dp_src_addr_high_v8[31:0]) //|< w + ,.reg2dp_src_addr_low_v32 (reg2dp_src_addr_low_v32[26:0]) //|< w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[26:0]) //|< w + ,.reg2dp_src_surf_stride (reg2dp_src_surf_stride[26:0]) //|< w + ,.reg2dp_surf_repeat_number (reg2dp_surf_repeat_number[23:0]) //|< w + ,.csb2ld_vld (csb2ld_vld) //|< w + ,.csb2ld_rdy (csb2ld_rdy) //|> w + ,.ld2csb_grp0_dma_stall_inc (ld2csb_grp0_dma_stall_inc) //|> w + ,.ld2csb_grp1_dma_stall_inc (ld2csb_grp1_dma_stall_inc) //|> w + ,.ld2csb_idle (ld2csb_idle) //|> w + ,.ld2st_wr_idle (ld2st_wr_idle) //|< w + ,.st2ld_load_idle (st2ld_load_idle) //|< w + ,.ld2gate_slcg_en (ld2gate_slcg_en) //|> w + ); +NV_NVDLA_BDMA_store u_store ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2bdma_rd_rsp_valid (mcif2bdma_rd_rsp_valid) //|< i + ,.mcif2bdma_rd_rsp_ready (mcif2bdma_rd_rsp_ready) //|> o + ,.mcif2bdma_rd_rsp_pd (mcif2bdma_rd_rsp_pd[513:0]) //|< i + ,.bdma2mcif_rd_cdt_lat_fifo_pop (bdma2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.bdma2mcif_wr_req_valid (bdma2mcif_wr_req_valid) //|> o + ,.bdma2mcif_wr_req_ready (bdma2mcif_wr_req_ready) //|< i + ,.bdma2mcif_wr_req_pd (bdma2mcif_wr_req_pd[514:0]) //|> o + ,.mcif2bdma_wr_rsp_complete (mcif2bdma_wr_rsp_complete) //|< i + ,.ld2st_rd_pvld (ld2st_rd_pvld) //|< w + ,.ld2st_rd_prdy (ld2st_rd_prdy) //|> w + ,.ld2st_rd_pd (ld2st_rd_pd[160:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.st2ld_load_idle (st2ld_load_idle) //|> w + ,.st2csb_grp0_done (st2csb_grp0_done) //|> w + ,.st2csb_grp1_done (st2csb_grp1_done) //|> w + ,.st2csb_idle (st2csb_idle) //|> w + ,.st2gate_slcg_en (st2gate_slcg_en) //|> w + ,.dma_write_stall_count (dma_write_stall_count[31:0]) //|> w + ,.dma_write_stall_count_cen (dma_write_stall_count_cen) //|< w + ); +NV_NVDLA_BDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ld2st_wr_prdy (ld2st_wr_prdy) //|> w + ,.ld2st_wr_idle (ld2st_wr_idle) //|> w + ,.ld2st_wr_pvld (ld2st_wr_pvld) //|< w + ,.ld2st_wr_pd (ld2st_wr_pd[160:0]) //|< w + ,.ld2st_rd_prdy (ld2st_rd_prdy) //|< w + ,.ld2st_rd_pvld (ld2st_rd_pvld) //|> w + ,.ld2st_rd_pd (ld2st_rd_pd[160:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +endmodule // NV_NVDLA_bdma diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v new file mode 100644 index 0000000..dc25048 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v @@ -0,0 +1,250 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_CALC_int8.v +module NV_NVDLA_CACC_CALC_int8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_truncate + ,in_data + ,in_op + ,in_op_valid + ,in_sel + ,in_valid + ,out_final_data + ,out_final_sat + ,out_final_valid + ,out_partial_data + ,out_partial_valid + ); +input [4:0] cfg_truncate; +input [21:0] in_data; +input [33:0] in_op; +input in_op_valid; +input in_sel; +input in_valid; +output [31:0] out_final_data; +output out_final_sat; +output out_final_valid; +output [33:0] out_partial_data; +output out_partial_valid; +input nvdla_core_clk; +input nvdla_core_rstn; +reg [32:0] i_sat_bits; +reg i_sat_sel; +reg i_sat_vld; +reg [34:0] i_sum_pd; +reg [31:0] out_final_data; +reg out_final_sat; +reg out_final_valid; +reg [33:0] out_partial_data; +reg out_partial_valid; +wire [21:0] di_pd; +wire [31:0] i_final_result; +wire i_final_vld; +wire i_guide; +wire [33:0] i_partial_result; +wire i_partial_vld; +wire i_point5; +wire [31:0] i_pos_pd; +wire [33:0] i_pre_sft_pd; +wire [33:0] i_sat_pd; +wire i_sat_sign; +wire i_sel; +wire [31:0] i_sft_max; +wire i_sft_need_sat; +wire [33:0] i_sft_pd; +wire [14:0] i_stick; +wire i_sum_msb; +wire [34:0] i_sum_pd_nxt; +wire i_sum_sign; +wire [31:0] i_tru_pd; +wire i_vld; +wire [33:0] in_mask_op; +wire mon_pos_pd_c; +wire [33:0] oi_pd; +assign i_sel = in_sel; +assign i_vld = in_valid; +assign in_mask_op = in_op_valid ? in_op[33:0] : 34'b0; +assign di_pd = in_data[21:0]; +assign oi_pd = in_mask_op[33:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + i_sat_vld <= 1'b0; + end else begin + i_sat_vld <= i_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + i_sat_sel <= 1'b0; + end else begin + if ((i_vld) == 1'b1) begin + i_sat_sel <= i_sel; +// VCS coverage off + end else if ((i_vld) == 1'b0) begin + end else begin + i_sat_sel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +//==================== +// Addition +//==================== +assign i_sum_pd_nxt[34:0] = $signed(di_pd) + $signed(oi_pd); +always @(posedge nvdla_core_clk) begin + if ((i_vld) == 1'b1) begin + i_sum_pd <= i_sum_pd_nxt; +// VCS coverage off + end else if ((i_vld) == 1'b0) begin + end else begin + i_sum_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +//==================== +// narrow down to 34bit, and need satuation only +//==================== +assign i_sum_sign = i_sum_pd[34 +1 -1]; +assign i_sum_msb = i_sum_pd[34 +1 -2]; +assign i_sat_sign = i_sum_sign; +always @( + i_sum_sign + or i_sum_msb + or i_sum_pd + ) begin + if (i_sum_sign ^ i_sum_msb) begin // overflow, need satuation + i_sat_bits = {33{~i_sum_sign}}; + end else begin + i_sat_bits = i_sum_pd[32:0]; + end +end +assign i_sat_pd = {i_sat_sign,i_sat_bits}; +assign i_partial_result = i_sat_pd; +//==================== +// narrow down to 32bit, and need rounding and satuation +//==================== +assign i_pre_sft_pd = i_sat_sel ? i_sat_pd[33:0] : {34{1'b0}}; +assign {i_sft_pd[33:0], i_guide, i_stick[14:0]} = ($signed({i_pre_sft_pd, 16'b0}) >>> cfg_truncate); +assign i_sft_need_sat = (i_sat_sign & ~(&i_sft_pd[32:31])) | + (~i_sat_sign & (|i_sft_pd[32:31])) | + (~i_sat_sign & (&{i_sft_pd[30:0], i_point5})); +assign i_sft_max = i_sat_sign ? {1'b1, 31'b0} : ~{1'b1, 31'b0}; +assign i_point5 = i_sat_sel & i_guide & (~i_sat_sign | (|i_stick)); +assign {mon_pos_pd_c, i_pos_pd[31:0]} = i_sft_pd[31:0] + i_point5; +assign i_tru_pd = i_pos_pd; +assign i_final_result = i_sft_need_sat ? i_sft_max : i_tru_pd; +assign i_partial_vld = i_sat_vld & ~i_sat_sel; +assign i_final_vld = i_sat_vld & i_sat_sel; +//==================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_partial_valid <= 1'b0; + end else begin + out_partial_valid <= i_partial_vld; + end +end +// spyglass disable_block STARC05-3.3.1.4b +always @(posedge nvdla_core_clk) begin + if ((i_partial_vld) == 1'b1) begin + out_partial_data <= i_partial_result; +// VCS coverage off + end else if ((i_partial_vld) == 1'b0) begin + end else begin + out_partial_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +// spyglass enable_block STARC05-3.3.1.4b +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_final_valid <= 1'b0; + end else begin + out_final_valid <= i_final_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_final_sat <= 1'b0; + end else begin + out_final_sat <= i_final_vld & i_sft_need_sat; + end +end +// spyglass disable_block STARC05-3.3.1.4b +always @(posedge nvdla_core_clk) begin + if ((i_final_vld) == 1'b1) begin + out_final_data <= i_final_result; +// VCS coverage off + end else if ((i_final_vld) == 1'b0) begin + end else begin + out_final_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +// spyglass enable_block STARC05-3.3.1.4b +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cacc_calc_int8__partial_sum_need_sat__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sum_sign ^ i_sum_msb; + endproperty +// Cover 0 : "i_sum_sign ^ i_sum_msb" + FUNCPOINT_cacc_calc_int8__partial_sum_need_sat__0_COV : cover property (cacc_calc_int8__partial_sum_need_sat__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cacc_calc_int8__out32_need_sat_pos__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sft_need_sat & ~i_sat_sign & ~i_point5; + endproperty +// Cover 1 : "i_sft_need_sat & ~i_sat_sign & ~i_point5" + FUNCPOINT_cacc_calc_int8__out32_need_sat_pos__1_COV : cover property (cacc_calc_int8__out32_need_sat_pos__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cacc_calc_int8__out32_round_need_sat_pos__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sft_need_sat & ~i_sat_sign & i_point5; + endproperty +// Cover 2 : "i_sft_need_sat & ~i_sat_sign & i_point5" + FUNCPOINT_cacc_calc_int8__out32_round_need_sat_pos__2_COV : cover property (cacc_calc_int8__out32_round_need_sat_pos__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cacc_calc_int8__out32_round_need_sat_neg__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sft_need_sat & i_sat_sign; + endproperty +// Cover 3 : "i_sft_need_sat & i_sat_sign" + FUNCPOINT_cacc_calc_int8__out32_round_need_sat_neg__3_COV : cover property (cacc_calc_int8__out32_round_need_sat_neg__3_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CACC_CALC_int8 diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v.vcp new file mode 100644 index 0000000..dc25048 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_CALC_int8.v.vcp @@ -0,0 +1,250 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_CALC_int8.v +module NV_NVDLA_CACC_CALC_int8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_truncate + ,in_data + ,in_op + ,in_op_valid + ,in_sel + ,in_valid + ,out_final_data + ,out_final_sat + ,out_final_valid + ,out_partial_data + ,out_partial_valid + ); +input [4:0] cfg_truncate; +input [21:0] in_data; +input [33:0] in_op; +input in_op_valid; +input in_sel; +input in_valid; +output [31:0] out_final_data; +output out_final_sat; +output out_final_valid; +output [33:0] out_partial_data; +output out_partial_valid; +input nvdla_core_clk; +input nvdla_core_rstn; +reg [32:0] i_sat_bits; +reg i_sat_sel; +reg i_sat_vld; +reg [34:0] i_sum_pd; +reg [31:0] out_final_data; +reg out_final_sat; +reg out_final_valid; +reg [33:0] out_partial_data; +reg out_partial_valid; +wire [21:0] di_pd; +wire [31:0] i_final_result; +wire i_final_vld; +wire i_guide; +wire [33:0] i_partial_result; +wire i_partial_vld; +wire i_point5; +wire [31:0] i_pos_pd; +wire [33:0] i_pre_sft_pd; +wire [33:0] i_sat_pd; +wire i_sat_sign; +wire i_sel; +wire [31:0] i_sft_max; +wire i_sft_need_sat; +wire [33:0] i_sft_pd; +wire [14:0] i_stick; +wire i_sum_msb; +wire [34:0] i_sum_pd_nxt; +wire i_sum_sign; +wire [31:0] i_tru_pd; +wire i_vld; +wire [33:0] in_mask_op; +wire mon_pos_pd_c; +wire [33:0] oi_pd; +assign i_sel = in_sel; +assign i_vld = in_valid; +assign in_mask_op = in_op_valid ? in_op[33:0] : 34'b0; +assign di_pd = in_data[21:0]; +assign oi_pd = in_mask_op[33:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + i_sat_vld <= 1'b0; + end else begin + i_sat_vld <= i_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + i_sat_sel <= 1'b0; + end else begin + if ((i_vld) == 1'b1) begin + i_sat_sel <= i_sel; +// VCS coverage off + end else if ((i_vld) == 1'b0) begin + end else begin + i_sat_sel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +//==================== +// Addition +//==================== +assign i_sum_pd_nxt[34:0] = $signed(di_pd) + $signed(oi_pd); +always @(posedge nvdla_core_clk) begin + if ((i_vld) == 1'b1) begin + i_sum_pd <= i_sum_pd_nxt; +// VCS coverage off + end else if ((i_vld) == 1'b0) begin + end else begin + i_sum_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +//==================== +// narrow down to 34bit, and need satuation only +//==================== +assign i_sum_sign = i_sum_pd[34 +1 -1]; +assign i_sum_msb = i_sum_pd[34 +1 -2]; +assign i_sat_sign = i_sum_sign; +always @( + i_sum_sign + or i_sum_msb + or i_sum_pd + ) begin + if (i_sum_sign ^ i_sum_msb) begin // overflow, need satuation + i_sat_bits = {33{~i_sum_sign}}; + end else begin + i_sat_bits = i_sum_pd[32:0]; + end +end +assign i_sat_pd = {i_sat_sign,i_sat_bits}; +assign i_partial_result = i_sat_pd; +//==================== +// narrow down to 32bit, and need rounding and satuation +//==================== +assign i_pre_sft_pd = i_sat_sel ? i_sat_pd[33:0] : {34{1'b0}}; +assign {i_sft_pd[33:0], i_guide, i_stick[14:0]} = ($signed({i_pre_sft_pd, 16'b0}) >>> cfg_truncate); +assign i_sft_need_sat = (i_sat_sign & ~(&i_sft_pd[32:31])) | + (~i_sat_sign & (|i_sft_pd[32:31])) | + (~i_sat_sign & (&{i_sft_pd[30:0], i_point5})); +assign i_sft_max = i_sat_sign ? {1'b1, 31'b0} : ~{1'b1, 31'b0}; +assign i_point5 = i_sat_sel & i_guide & (~i_sat_sign | (|i_stick)); +assign {mon_pos_pd_c, i_pos_pd[31:0]} = i_sft_pd[31:0] + i_point5; +assign i_tru_pd = i_pos_pd; +assign i_final_result = i_sft_need_sat ? i_sft_max : i_tru_pd; +assign i_partial_vld = i_sat_vld & ~i_sat_sel; +assign i_final_vld = i_sat_vld & i_sat_sel; +//==================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_partial_valid <= 1'b0; + end else begin + out_partial_valid <= i_partial_vld; + end +end +// spyglass disable_block STARC05-3.3.1.4b +always @(posedge nvdla_core_clk) begin + if ((i_partial_vld) == 1'b1) begin + out_partial_data <= i_partial_result; +// VCS coverage off + end else if ((i_partial_vld) == 1'b0) begin + end else begin + out_partial_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +// spyglass enable_block STARC05-3.3.1.4b +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_final_valid <= 1'b0; + end else begin + out_final_valid <= i_final_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_final_sat <= 1'b0; + end else begin + out_final_sat <= i_final_vld & i_sft_need_sat; + end +end +// spyglass disable_block STARC05-3.3.1.4b +always @(posedge nvdla_core_clk) begin + if ((i_final_vld) == 1'b1) begin + out_final_data <= i_final_result; +// VCS coverage off + end else if ((i_final_vld) == 1'b0) begin + end else begin + out_final_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +// spyglass enable_block STARC05-3.3.1.4b +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cacc_calc_int8__partial_sum_need_sat__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sum_sign ^ i_sum_msb; + endproperty +// Cover 0 : "i_sum_sign ^ i_sum_msb" + FUNCPOINT_cacc_calc_int8__partial_sum_need_sat__0_COV : cover property (cacc_calc_int8__partial_sum_need_sat__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cacc_calc_int8__out32_need_sat_pos__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sft_need_sat & ~i_sat_sign & ~i_point5; + endproperty +// Cover 1 : "i_sft_need_sat & ~i_sat_sign & ~i_point5" + FUNCPOINT_cacc_calc_int8__out32_need_sat_pos__1_COV : cover property (cacc_calc_int8__out32_need_sat_pos__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cacc_calc_int8__out32_round_need_sat_pos__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sft_need_sat & ~i_sat_sign & i_point5; + endproperty +// Cover 2 : "i_sft_need_sat & ~i_sat_sign & i_point5" + FUNCPOINT_cacc_calc_int8__out32_round_need_sat_pos__2_COV : cover property (cacc_calc_int8__out32_round_need_sat_pos__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cacc_calc_int8__out32_round_need_sat_neg__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + i_sft_need_sat & i_sat_sign; + endproperty +// Cover 3 : "i_sft_need_sat & i_sat_sign" + FUNCPOINT_cacc_calc_int8__out32_round_need_sat_neg__3_COV : cover property (cacc_calc_int8__out32_round_need_sat_neg__3_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CACC_CALC_int8 diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v new file mode 100644 index 0000000..1ad9142 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v @@ -0,0 +1,103 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_assembly_buffer.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_assembly_buffer ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,abuf_rd_addr //|< i + ,abuf_rd_en //|< i + ,abuf_wr_addr //|< i + ,abuf_wr_data //|< i + ,abuf_wr_en //|< i + ,pwrbus_ram_pd //|< i + ,abuf_rd_data //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [3 +1 -1:0] abuf_rd_addr; +input abuf_rd_en; +input [3 +1 -1:0] abuf_wr_addr; +input [34*8 -1:0] abuf_wr_data; +input abuf_wr_en; +input [31:0] pwrbus_ram_pd; +output [34*8 -1:0] abuf_rd_data; +// spyglass disable_block NoWidthInBasedNum-ML +// instance SRAM +wire [34*8 -1:0] abuf_rd_data_ecc; +wire [3 +1 -1:0] abuf_rd_addr; +//: my $dep= 8*2; +//: my $wid= 34*8; +//: print qq( +//: nv_ram_rws_${dep}x${wid} u_accu_abuf_0 ( +//: .clk (nvdla_core_clk) //|< i +//: ,.ra (abuf_rd_addr) //|< i +//: ,.re (abuf_rd_en) //|< i +//: ,.dout (abuf_rd_data_ecc) //|> w +//: ,.wa (abuf_wr_addr) //|< r +//: ,.we (abuf_wr_en) //|< r +//: ,.di (abuf_wr_data) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +//: ); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +nv_ram_rws_16x272 u_accu_abuf_0 ( +.clk (nvdla_core_clk) //|< i +,.ra (abuf_rd_addr) //|< i +,.re (abuf_rd_en) //|< i +,.dout (abuf_rd_data_ecc) //|> w +,.wa (abuf_wr_addr) //|< r +,.we (abuf_wr_en) //|< r +,.di (abuf_wr_data) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// 1 pipe for sram read data. +//: &eperl::flop("-q abuf_rd_en_d1 -d \"abuf_rd_en\" -clk nvdla_core_clk -rst nvdla_core_rstn"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg abuf_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + abuf_rd_en_d1 <= 'b0; + end else begin + abuf_rd_en_d1 <= abuf_rd_en; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [34*8 -1:0] abuf_rd_raw_data = abuf_rd_data_ecc; +// spyglass disable_block STARC05-3.3.1.4b +//: my $kk=34*8; +//: &eperl::flop("-wid ${kk} -norst -q abuf_rd_raw_data_d1 -en \"abuf_rd_en_d1\" -d \"abuf_rd_raw_data\" -clk nvdla_core_clk"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [271:0] abuf_rd_raw_data_d1; +always @(posedge nvdla_core_clk) begin + if ((abuf_rd_en_d1) == 1'b1) begin + abuf_rd_raw_data_d1 <= abuf_rd_raw_data; + // VCS coverage off + end else if ((abuf_rd_en_d1) == 1'b0) begin + end else begin + abuf_rd_raw_data_d1 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC05-3.3.1.4b +assign abuf_rd_data = abuf_rd_raw_data_d1; +endmodule // NV_NVDLA_CACC_assembly_buffer diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v.vcp new file mode 100644 index 0000000..22bedd5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v.vcp @@ -0,0 +1,64 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_assembly_buffer.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_assembly_buffer ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,abuf_rd_addr //|< i + ,abuf_rd_en //|< i + ,abuf_wr_addr //|< i + ,abuf_wr_data //|< i + ,abuf_wr_en //|< i + ,pwrbus_ram_pd //|< i + ,abuf_rd_data //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [3 +1 -1:0] abuf_rd_addr; +input abuf_rd_en; +input [3 +1 -1:0] abuf_wr_addr; +input [34*8 -1:0] abuf_wr_data; +input abuf_wr_en; +input [31:0] pwrbus_ram_pd; +output [34*8 -1:0] abuf_rd_data; +// spyglass disable_block NoWidthInBasedNum-ML +// instance SRAM +wire [34*8 -1:0] abuf_rd_data_ecc; +wire [3 +1 -1:0] abuf_rd_addr; +//: my $dep= 8*2; +//: my $wid= 34*8; +//: print qq( +//: nv_ram_rws_${dep}x${wid} u_accu_abuf_0 ( +//: .clk (nvdla_core_clk) //|< i +//: ,.ra (abuf_rd_addr) //|< i +//: ,.re (abuf_rd_en) //|< i +//: ,.dout (abuf_rd_data_ecc) //|> w +//: ,.wa (abuf_wr_addr) //|< r +//: ,.we (abuf_wr_en) //|< r +//: ,.di (abuf_wr_data) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +//: ); +//: ); +// 1 pipe for sram read data. +//: &eperl::flop("-q abuf_rd_en_d1 -d \"abuf_rd_en\" -clk nvdla_core_clk -rst nvdla_core_rstn"); +wire [34*8 -1:0] abuf_rd_raw_data = abuf_rd_data_ecc; +// spyglass disable_block STARC05-3.3.1.4b +//: my $kk=34*8; +//: &eperl::flop("-wid ${kk} -norst -q abuf_rd_raw_data_d1 -en \"abuf_rd_en_d1\" -d \"abuf_rd_raw_data\" -clk nvdla_core_clk"); +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC05-3.3.1.4b +assign abuf_rd_data = abuf_rd_raw_data_d1; +endmodule // NV_NVDLA_CACC_assembly_buffer diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v new file mode 100644 index 0000000..03e9dca --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_assembly_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_assembly_ctrl ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2reg_done + ,mac_a2accu_pd + ,mac_a2accu_pvld + ,mac_b2accu_pd + ,mac_b2accu_pvld + ,reg2dp_clip_truncate + ,reg2dp_conv_mode + ,reg2dp_op_en + ,reg2dp_proc_precision + ,abuf_rd_addr + ,abuf_rd_en + ,accu_ctrl_pd + ,accu_ctrl_ram_valid + ,accu_ctrl_valid + ,cfg_in_en_mask + ,cfg_is_wg + ,cfg_truncate + ,slcg_cell_en + ,wait_for_op_en + ); +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_proc_precision; +input [4:0] reg2dp_clip_truncate; +output[3 +1 -1:0]abuf_rd_addr; +output abuf_rd_en; +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input [8:0] mac_a2accu_pd; +input mac_a2accu_pvld; +input [8:0] mac_b2accu_pd; //always equal mac_a2accu_pd +input mac_b2accu_pvld; +output [12:0] accu_ctrl_pd; +output accu_ctrl_ram_valid; +output accu_ctrl_valid; +output cfg_in_en_mask; +output cfg_is_wg; +output [4:0] cfg_truncate; +output slcg_cell_en; +output wait_for_op_en; +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.1.6 +// cross partition,1T +//: &eperl::flop("-q accu_valid -d \"mac_a2accu_pvld\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 9 -q accu_pd -en \"mac_a2accu_pvld\" -d \"mac_a2accu_pd\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg accu_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_valid <= 'b0; + end else begin + accu_valid <= mac_a2accu_pvld; + end +end +reg [8:0] accu_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_pd <= 'b0; + end else begin + if ((mac_a2accu_pvld) == 1'b1) begin + accu_pd <= mac_a2accu_pd; + // VCS coverage off + end else if ((mac_a2accu_pvld) == 1'b0) begin + end else begin + accu_pd <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// generator input status signal ///// +////////////////////////////////////////////////////////////// +wire accu_stripe_st = accu_pd[5]; +wire accu_stripe_end = accu_pd[6]; +wire accu_channel_end = accu_pd[7]; +wire accu_layer_end = accu_pd[8]; +wire is_int8 = (reg2dp_proc_precision == 2'h0); +wire is_winograd = 1'b0; +// SLCG +wire slcg_cell_en_w = reg2dp_op_en; +//: &eperl::flop(" -q slcg_cell_en_d1 -d \"slcg_cell_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q slcg_cell_en_d2 -d \"slcg_cell_en_d1\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q slcg_cell_en_d3 -d \"slcg_cell_en_d2\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg slcg_cell_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_cell_en_d1 <= 'b0; + end else begin + slcg_cell_en_d1 <= slcg_cell_en_w; + end +end +reg slcg_cell_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_cell_en_d2 <= 'b0; + end else begin + slcg_cell_en_d2 <= slcg_cell_en_d1; + end +end +reg slcg_cell_en_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_cell_en_d3 <= 'b0; + end else begin + slcg_cell_en_d3 <= slcg_cell_en_d2; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire slcg_cell_en = slcg_cell_en_d3; +// get layer operation begin +wire wait_for_op_en_w = dp2reg_done ? 1'b1 : reg2dp_op_en ? 1'b0 : wait_for_op_en; +//: &eperl::flop(" -q wait_for_op_en -d \"wait_for_op_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg wait_for_op_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wait_for_op_en <= 1; + end else begin + wait_for_op_en <= wait_for_op_en_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// get address and other contrl +reg cfg_winograd; +reg [3 +1 -1:0] accu_cnt; +wire [3 +1 -1:0] accu_cnt_w; +wire [3 +1 -1:0] accu_cnt_inc; +wire mon_accu_cnt_inc; +reg accu_channel_st; +wire layer_st = wait_for_op_en & reg2dp_op_en; +assign {mon_accu_cnt_inc, accu_cnt_inc} = accu_cnt + 1'b1; +assign accu_cnt_w = (layer_st | accu_stripe_end) ? {3 +1{1'b0}} : accu_cnt_inc; +wire [3 +1 -1:0] accu_addr = accu_cnt; +wire accu_channel_st_w = layer_st ? 1'b1 : (accu_valid & accu_stripe_end) ? accu_channel_end : accu_channel_st; +wire accu_rd_en = accu_valid & (~accu_channel_st); +wire cfg_in_en_mask_w = 1'b1; +//: &eperl::flop("-q accu_ram_valid -d accu_rd_en"); +//: &eperl::flop("-nodeclare -q accu_cnt -en \"layer_st | accu_valid\" -d \"accu_cnt_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q accu_channel_st -en \"layer_st | accu_valid\" -d \"accu_channel_st_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg accu_ram_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ram_valid <= 'b0; + end else begin + accu_ram_valid <= accu_rd_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_cnt <= 'b0; + end else begin + if ((layer_st | accu_valid) == 1'b1) begin + accu_cnt <= accu_cnt_w; + // VCS coverage off + end else if ((layer_st | accu_valid) == 1'b0) begin + end else begin + accu_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_channel_st <= 1; + end else begin + if ((layer_st | accu_valid) == 1'b1) begin + accu_channel_st <= accu_channel_st_w; + // VCS coverage off + end else if ((layer_st | accu_valid) == 1'b0) begin + end else begin + accu_channel_st <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire accu_ctrl_valid_d0 = accu_valid; +wire accu_ram_valid_d0 = accu_ram_valid; +wire [3 +1 -1:0] accu_addr_d0 = accu_addr; +wire accu_stripe_end_d0 = accu_stripe_end; +wire accu_channel_end_d0 = accu_channel_end; +wire accu_layer_end_d0 = accu_layer_end; +//: &eperl::flop("-nodeclare -q cfg_winograd -en \"layer_st\" -d \"is_winograd\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 5 -q cfg_truncate -en \"layer_st\" -d \"reg2dp_clip_truncate\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cfg_is_wg -en \"layer_st\" -d \"is_winograd\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cfg_in_en_mask -en \"layer_st\" -d \"cfg_in_en_mask_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_winograd <= 'b0; + end else begin + if ((layer_st) == 1'b1) begin + cfg_winograd <= is_winograd; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + cfg_winograd <= 'bx; + // VCS coverage on + end + end +end +reg [4:0] cfg_truncate; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_truncate <= 'b0; + end else begin + if ((layer_st) == 1'b1) begin + cfg_truncate <= reg2dp_clip_truncate; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + cfg_truncate <= 'bx; + // VCS coverage on + end + end +end +reg cfg_is_wg; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_is_wg <= 'b0; + end else begin + if ((layer_st) == 1'b1) begin + cfg_is_wg <= is_winograd; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + cfg_is_wg <= 'bx; + // VCS coverage on + end + end +end +reg cfg_in_en_mask; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_in_en_mask <= 'b0; + end else begin + if ((layer_st) == 1'b1) begin + cfg_in_en_mask <= cfg_in_en_mask_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + cfg_in_en_mask <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire abuf_rd_en = accu_rd_en; +wire [3 +1 -1:0] abuf_rd_addr = accu_addr; +// regout +//: my $kk=3 +1; +//: &eperl::flop(" -q accu_ctrl_valid -d \"accu_ctrl_valid_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_ram_valid -d \"accu_ram_valid_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q accu_ctrl_addr -en \"accu_ctrl_valid_d0\" -d \"accu_addr_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_stripe_end -en \"accu_ctrl_valid_d0\" -d \"accu_stripe_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_channel_end -en \"accu_ctrl_valid_d0\" -d \"accu_channel_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_layer_end -en \"accu_ctrl_valid_d0\" -d \"accu_layer_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_dlv_elem_mask -en \"accu_ctrl_valid_d0\" -d \"accu_channel_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: my $jj=6-$kk; +//: print "assign accu_ctrl_pd[5:0] = {{${jj}{1'b0}},accu_ctrl_addr}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg accu_ctrl_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_valid <= 'b0; + end else begin + accu_ctrl_valid <= accu_ctrl_valid_d0; + end +end +reg accu_ctrl_ram_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_ram_valid <= 'b0; + end else begin + accu_ctrl_ram_valid <= accu_ram_valid_d0; + end +end +reg [3:0] accu_ctrl_addr; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_addr <= 'b0; + end else begin + if ((accu_ctrl_valid_d0) == 1'b1) begin + accu_ctrl_addr <= accu_addr_d0; + // VCS coverage off + end else if ((accu_ctrl_valid_d0) == 1'b0) begin + end else begin + accu_ctrl_addr <= 'bx; + // VCS coverage on + end + end +end +reg accu_ctrl_stripe_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_stripe_end <= 'b0; + end else begin + if ((accu_ctrl_valid_d0) == 1'b1) begin + accu_ctrl_stripe_end <= accu_stripe_end_d0; + // VCS coverage off + end else if ((accu_ctrl_valid_d0) == 1'b0) begin + end else begin + accu_ctrl_stripe_end <= 'bx; + // VCS coverage on + end + end +end +reg accu_ctrl_channel_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_channel_end <= 'b0; + end else begin + if ((accu_ctrl_valid_d0) == 1'b1) begin + accu_ctrl_channel_end <= accu_channel_end_d0; + // VCS coverage off + end else if ((accu_ctrl_valid_d0) == 1'b0) begin + end else begin + accu_ctrl_channel_end <= 'bx; + // VCS coverage on + end + end +end +reg accu_ctrl_layer_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_layer_end <= 'b0; + end else begin + if ((accu_ctrl_valid_d0) == 1'b1) begin + accu_ctrl_layer_end <= accu_layer_end_d0; + // VCS coverage off + end else if ((accu_ctrl_valid_d0) == 1'b0) begin + end else begin + accu_ctrl_layer_end <= 'bx; + // VCS coverage on + end + end +end +reg accu_ctrl_dlv_elem_mask; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_dlv_elem_mask <= 'b0; + end else begin + if ((accu_ctrl_valid_d0) == 1'b1) begin + accu_ctrl_dlv_elem_mask <= accu_channel_end_d0; + // VCS coverage off + end else if ((accu_ctrl_valid_d0) == 1'b0) begin + end else begin + accu_ctrl_dlv_elem_mask <= 'bx; + // VCS coverage on + end + end +end +assign accu_ctrl_pd[5:0] = {{2{1'b0}},accu_ctrl_addr}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.1.6 +assign accu_ctrl_pd[8:6] = 3'b1; //reserve +assign accu_ctrl_pd[9] = accu_ctrl_stripe_end ; +assign accu_ctrl_pd[10] = accu_ctrl_channel_end ; +assign accu_ctrl_pd[11] = accu_ctrl_layer_end ; +assign accu_ctrl_pd[12] = accu_ctrl_dlv_elem_mask; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v.vcp new file mode 100644 index 0000000..3b23073 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v.vcp @@ -0,0 +1,131 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_assembly_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_assembly_ctrl ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2reg_done + ,mac_a2accu_pd + ,mac_a2accu_pvld + ,mac_b2accu_pd + ,mac_b2accu_pvld + ,reg2dp_clip_truncate + ,reg2dp_conv_mode + ,reg2dp_op_en + ,reg2dp_proc_precision + ,abuf_rd_addr + ,abuf_rd_en + ,accu_ctrl_pd + ,accu_ctrl_ram_valid + ,accu_ctrl_valid + ,cfg_in_en_mask + ,cfg_is_wg + ,cfg_truncate + ,slcg_cell_en + ,wait_for_op_en + ); +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_proc_precision; +input [4:0] reg2dp_clip_truncate; +output[3 +1 -1:0]abuf_rd_addr; +output abuf_rd_en; +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input [8:0] mac_a2accu_pd; +input mac_a2accu_pvld; +input [8:0] mac_b2accu_pd; //always equal mac_a2accu_pd +input mac_b2accu_pvld; +output [12:0] accu_ctrl_pd; +output accu_ctrl_ram_valid; +output accu_ctrl_valid; +output cfg_in_en_mask; +output cfg_is_wg; +output [4:0] cfg_truncate; +output slcg_cell_en; +output wait_for_op_en; +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.1.6 +// cross partition,1T +//: &eperl::flop("-q accu_valid -d \"mac_a2accu_pvld\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 9 -q accu_pd -en \"mac_a2accu_pvld\" -d \"mac_a2accu_pd\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +////////////////////////////////////////////////////////////// +///// generator input status signal ///// +////////////////////////////////////////////////////////////// +wire accu_stripe_st = accu_pd[5]; +wire accu_stripe_end = accu_pd[6]; +wire accu_channel_end = accu_pd[7]; +wire accu_layer_end = accu_pd[8]; +wire is_int8 = (reg2dp_proc_precision == 2'h0); +wire is_winograd = 1'b0; +// SLCG +wire slcg_cell_en_w = reg2dp_op_en; +//: &eperl::flop(" -q slcg_cell_en_d1 -d \"slcg_cell_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q slcg_cell_en_d2 -d \"slcg_cell_en_d1\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q slcg_cell_en_d3 -d \"slcg_cell_en_d2\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +wire slcg_cell_en = slcg_cell_en_d3; +// get layer operation begin +wire wait_for_op_en_w = dp2reg_done ? 1'b1 : reg2dp_op_en ? 1'b0 : wait_for_op_en; +//: &eperl::flop(" -q wait_for_op_en -d \"wait_for_op_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 1"); +// get address and other contrl +reg cfg_winograd; +reg [3 +1 -1:0] accu_cnt; +wire [3 +1 -1:0] accu_cnt_w; +wire [3 +1 -1:0] accu_cnt_inc; +wire mon_accu_cnt_inc; +reg accu_channel_st; +wire layer_st = wait_for_op_en & reg2dp_op_en; +assign {mon_accu_cnt_inc, accu_cnt_inc} = accu_cnt + 1'b1; +assign accu_cnt_w = (layer_st | accu_stripe_end) ? {3 +1{1'b0}} : accu_cnt_inc; +wire [3 +1 -1:0] accu_addr = accu_cnt; +wire accu_channel_st_w = layer_st ? 1'b1 : (accu_valid & accu_stripe_end) ? accu_channel_end : accu_channel_st; +wire accu_rd_en = accu_valid & (~accu_channel_st); +wire cfg_in_en_mask_w = 1'b1; +//: &eperl::flop("-q accu_ram_valid -d accu_rd_en"); +//: &eperl::flop("-nodeclare -q accu_cnt -en \"layer_st | accu_valid\" -d \"accu_cnt_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q accu_channel_st -en \"layer_st | accu_valid\" -d \"accu_channel_st_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 1"); +wire accu_ctrl_valid_d0 = accu_valid; +wire accu_ram_valid_d0 = accu_ram_valid; +wire [3 +1 -1:0] accu_addr_d0 = accu_addr; +wire accu_stripe_end_d0 = accu_stripe_end; +wire accu_channel_end_d0 = accu_channel_end; +wire accu_layer_end_d0 = accu_layer_end; +//: &eperl::flop("-nodeclare -q cfg_winograd -en \"layer_st\" -d \"is_winograd\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 5 -q cfg_truncate -en \"layer_st\" -d \"reg2dp_clip_truncate\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cfg_is_wg -en \"layer_st\" -d \"is_winograd\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cfg_in_en_mask -en \"layer_st\" -d \"cfg_in_en_mask_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +wire abuf_rd_en = accu_rd_en; +wire [3 +1 -1:0] abuf_rd_addr = accu_addr; +// regout +//: my $kk=3 +1; +//: &eperl::flop(" -q accu_ctrl_valid -d \"accu_ctrl_valid_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_ram_valid -d \"accu_ram_valid_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q accu_ctrl_addr -en \"accu_ctrl_valid_d0\" -d \"accu_addr_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_stripe_end -en \"accu_ctrl_valid_d0\" -d \"accu_stripe_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_channel_end -en \"accu_ctrl_valid_d0\" -d \"accu_channel_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_layer_end -en \"accu_ctrl_valid_d0\" -d \"accu_layer_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q accu_ctrl_dlv_elem_mask -en \"accu_ctrl_valid_d0\" -d \"accu_channel_end_d0\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: my $jj=6-$kk; +//: print "assign accu_ctrl_pd[5:0] = {{${jj}{1'b0}},accu_ctrl_addr}; \n"; +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.1.6 +assign accu_ctrl_pd[8:6] = 3'b1; //reserve +assign accu_ctrl_pd[9] = accu_ctrl_stripe_end ; +assign accu_ctrl_pd[10] = accu_ctrl_channel_end ; +assign accu_ctrl_pd[11] = accu_ctrl_layer_end ; +assign accu_ctrl_pd[12] = accu_ctrl_dlv_elem_mask; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v new file mode 100644 index 0000000..7dd0dda --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v @@ -0,0 +1,876 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_calculator.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_calculator ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,abuf_rd_data //|< i + ,accu_ctrl_pd //|< i + ,accu_ctrl_ram_valid //|< i + ,accu_ctrl_valid //|< i + ,cfg_in_en_mask //|< i + ,cfg_is_wg //|< i + ,cfg_truncate //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_a2accu_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac_a2accu_data0 //|< i +,mac_a2accu_data1 //|< i +,mac_a2accu_data2 //|< i +,mac_a2accu_data3 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac_a2accu_mask //|< i + ,mac_a2accu_mode //|< i + ,mac_a2accu_pvld //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_b2accu_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac_b2accu_data0 //|< i +,mac_b2accu_data1 //|< i +,mac_b2accu_data2 //|< i +,mac_b2accu_data3 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac_b2accu_mask //|< i + ,mac_b2accu_mode //|< i + ,mac_b2accu_pvld //|< i + ,nvdla_cell_clk //|< i + ,abuf_wr_addr //|> o + ,abuf_wr_data //|> o + ,abuf_wr_en //|> o + ,dlv_data //|> o + ,dlv_mask //|> o + ,dlv_pd //|> o + ,dlv_valid //|> o + ,dp2reg_sat_count //|> o + ); +input nvdla_cell_clk; +input nvdla_core_clk; +input nvdla_core_rstn; +input [34*8 -1:0] abuf_rd_data; +input [12:0] accu_ctrl_pd; +input accu_ctrl_ram_valid; +input accu_ctrl_valid; +input cfg_in_en_mask; +input cfg_is_wg; +input [4:0] cfg_truncate; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_a2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac_a2accu_data0; +input [19 -1:0] mac_a2accu_data1; +input [19 -1:0] mac_a2accu_data2; +input [19 -1:0] mac_a2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2-1:0] mac_a2accu_mask; +input mac_a2accu_mode; +input mac_a2accu_pvld; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_b2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac_b2accu_data0; +input [19 -1:0] mac_b2accu_data1; +input [19 -1:0] mac_b2accu_data2; +input [19 -1:0] mac_b2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2-1:0] mac_b2accu_mask; +input mac_b2accu_mode; +input mac_b2accu_pvld; +output [3 +1 -1:0] abuf_wr_addr; +output [34*8 -1:0] abuf_wr_data; +output abuf_wr_en; +output [32*8 -1:0] dlv_data; +output dlv_mask; +output [1:0] dlv_pd; +output dlv_valid; +output [31:0] dp2reg_sat_count; +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.1.6 +// unpack abuffer read data +//: my $kk=34; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: wire [${kk}-1:0] abuf_in_data_${i} = abuf_rd_data[($i+1)*${kk}-1:$i*${kk}]; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [34-1:0] abuf_in_data_0 = abuf_rd_data[(0+1)*34-1:0*34]; +wire [34-1:0] abuf_in_data_1 = abuf_rd_data[(1+1)*34-1:1*34]; +wire [34-1:0] abuf_in_data_2 = abuf_rd_data[(2+1)*34-1:2*34]; +wire [34-1:0] abuf_in_data_3 = abuf_rd_data[(3+1)*34-1:3*34]; +wire [34-1:0] abuf_in_data_4 = abuf_rd_data[(4+1)*34-1:4*34]; +wire [34-1:0] abuf_in_data_5 = abuf_rd_data[(5+1)*34-1:5*34]; +wire [34-1:0] abuf_in_data_6 = abuf_rd_data[(6+1)*34-1:6*34]; +wire [34-1:0] abuf_in_data_7 = abuf_rd_data[(7+1)*34-1:7*34]; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//1T delay, the same T with data/mask +//: &eperl::flop("-wid 13 -q accu_ctrl_pd_d1 -en accu_ctrl_valid -d accu_ctrl_pd"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [12:0] accu_ctrl_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu_ctrl_pd_d1 <= 'b0; + end else begin + if ((accu_ctrl_valid) == 1'b1) begin + accu_ctrl_pd_d1 <= accu_ctrl_pd; + // VCS coverage off + end else if ((accu_ctrl_valid) == 1'b0) begin + end else begin + accu_ctrl_pd_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire calc_valid_in = (mac_b2accu_pvld | mac_a2accu_pvld); +// spyglass disable_block STARC05-3.3.1.4b +//: &eperl::retime("-stage 3 -o calc_valid -i calc_valid_in"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg calc_valid_in_d1; +always @(posedge nvdla_core_clk) begin + calc_valid_in_d1 <= calc_valid_in; +end + +reg calc_valid_in_d2; +always @(posedge nvdla_core_clk) begin + calc_valid_in_d2 <= calc_valid_in_d1; +end + +reg calc_valid_in_d3; +always @(posedge nvdla_core_clk) begin + calc_valid_in_d3 <= calc_valid_in_d2; +end + +wire calc_valid; +assign calc_valid = calc_valid_in_d3; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block STARC05-3.3.1.4b +// unpack pd form abuffer control +wire [5:0] calc_addr = accu_ctrl_pd_d1[5:0]; +wire [2:0] calc_mode = accu_ctrl_pd_d1[8:6]; +wire calc_stripe_end = accu_ctrl_pd_d1[9]; +wire calc_channel_end = accu_ctrl_pd_d1[10]; +wire calc_layer_end = accu_ctrl_pd_d1[11]; +wire calc_dlv_elem_mask = accu_ctrl_pd_d1[12]; +//: my $kk=19; +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print "wire [${kk}-1:0] calc_elem_${i} = mac_a2accu_data${i}; \n"; +//: } +//: for(my $i = 8/2; $i < 8; $i ++) { +//: my $j = $i - 8/2; +//: print "wire [${kk}-1:0] calc_elem_${i} = mac_b2accu_data${j}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [19-1:0] calc_elem_0 = mac_a2accu_data0; +wire [19-1:0] calc_elem_1 = mac_a2accu_data1; +wire [19-1:0] calc_elem_2 = mac_a2accu_data2; +wire [19-1:0] calc_elem_3 = mac_a2accu_data3; +wire [19-1:0] calc_elem_4 = mac_b2accu_data0; +wire [19-1:0] calc_elem_5 = mac_b2accu_data1; +wire [19-1:0] calc_elem_6 = mac_b2accu_data2; +wire [19-1:0] calc_elem_7 = mac_b2accu_data3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8 -1:0] calc_in_mask = {mac_b2accu_mask, mac_a2accu_mask}; +wire [8 -1:0] calc_op_en = calc_in_mask & {8{cfg_in_en_mask}}; +wire [8 -1:0] calc_op1_vld = calc_in_mask & {8{cfg_in_en_mask & accu_ctrl_ram_valid}}; +wire calc_dlv_valid = calc_valid & calc_channel_end; +wire calc_wr_en = calc_valid & (~calc_channel_end); +//: my $hh= 22-19; +//: my $pp= 34; +//: my $bb= 19; +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: wire [21:0]calc_op0_${i} = {{${hh}{calc_elem_${i}[${bb}-1]}},calc_elem_${i}}; +//: wire [${pp}-1:0] calc_op1_${i} = abuf_in_data_${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [21:0]calc_op0_0 = {{3{calc_elem_0[19-1]}},calc_elem_0}; +wire [34-1:0] calc_op1_0 = abuf_in_data_0; + +wire [21:0]calc_op0_1 = {{3{calc_elem_1[19-1]}},calc_elem_1}; +wire [34-1:0] calc_op1_1 = abuf_in_data_1; + +wire [21:0]calc_op0_2 = {{3{calc_elem_2[19-1]}},calc_elem_2}; +wire [34-1:0] calc_op1_2 = abuf_in_data_2; + +wire [21:0]calc_op0_3 = {{3{calc_elem_3[19-1]}},calc_elem_3}; +wire [34-1:0] calc_op1_3 = abuf_in_data_3; + +wire [21:0]calc_op0_4 = {{3{calc_elem_4[19-1]}},calc_elem_4}; +wire [34-1:0] calc_op1_4 = abuf_in_data_4; + +wire [21:0]calc_op0_5 = {{3{calc_elem_5[19-1]}},calc_elem_5}; +wire [34-1:0] calc_op1_5 = abuf_in_data_5; + +wire [21:0]calc_op0_6 = {{3{calc_elem_6[19-1]}},calc_elem_6}; +wire [34-1:0] calc_op1_6 = abuf_in_data_6; + +wire [21:0]calc_op0_7 = {{3{calc_elem_7[19-1]}},calc_elem_7}; +wire [34-1:0] calc_op1_7 = abuf_in_data_7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// instance int8 adders +wire [8 -1:0] calc_fout_sat; +wire [8 -1:0] calc_pout_vld; +wire [8 -1:0] calc_fout_vld; +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: wire [34 -1:0] calc_pout_${i}_sum; +//: wire [32 -1:0] calc_fout_${i}_sum; +//: ) +//: } +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: NV_NVDLA_CACC_CALC_int8 u_cell_int8_${i} ( +//: .cfg_truncate (cfg_truncate) //|< w +//: ,.in_data (calc_op0_${i}) //|< r +//: ,.in_op (calc_op1_${i}) //|< r +//: ,.in_op_valid (calc_op1_vld[${i}]) //|< r +//: ,.in_sel (calc_dlv_valid) //|< r +//: ,.in_valid (calc_op_en[${i}]) //|< r +//: ,.out_final_data (calc_fout_${i}_sum) //|> w +//: ,.out_final_sat (calc_fout_sat[${i}]) //|> w +//: ,.out_final_valid (calc_fout_vld[${i}]) //|> w +//: ,.out_partial_data (calc_pout_${i}_sum) //|> w +//: ,.out_partial_valid (calc_pout_vld[${i}]) //|> w +//: ,.nvdla_core_clk (nvdla_cell_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ); +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [34 -1:0] calc_pout_0_sum; +wire [32 -1:0] calc_fout_0_sum; + +wire [34 -1:0] calc_pout_1_sum; +wire [32 -1:0] calc_fout_1_sum; + +wire [34 -1:0] calc_pout_2_sum; +wire [32 -1:0] calc_fout_2_sum; + +wire [34 -1:0] calc_pout_3_sum; +wire [32 -1:0] calc_fout_3_sum; + +wire [34 -1:0] calc_pout_4_sum; +wire [32 -1:0] calc_fout_4_sum; + +wire [34 -1:0] calc_pout_5_sum; +wire [32 -1:0] calc_fout_5_sum; + +wire [34 -1:0] calc_pout_6_sum; +wire [32 -1:0] calc_fout_6_sum; + +wire [34 -1:0] calc_pout_7_sum; +wire [32 -1:0] calc_fout_7_sum; + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_0 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_0) //|< r +,.in_op (calc_op1_0) //|< r +,.in_op_valid (calc_op1_vld[0]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[0]) //|< r +,.out_final_data (calc_fout_0_sum) //|> w +,.out_final_sat (calc_fout_sat[0]) //|> w +,.out_final_valid (calc_fout_vld[0]) //|> w +,.out_partial_data (calc_pout_0_sum) //|> w +,.out_partial_valid (calc_pout_vld[0]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_1 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_1) //|< r +,.in_op (calc_op1_1) //|< r +,.in_op_valid (calc_op1_vld[1]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[1]) //|< r +,.out_final_data (calc_fout_1_sum) //|> w +,.out_final_sat (calc_fout_sat[1]) //|> w +,.out_final_valid (calc_fout_vld[1]) //|> w +,.out_partial_data (calc_pout_1_sum) //|> w +,.out_partial_valid (calc_pout_vld[1]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_2 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_2) //|< r +,.in_op (calc_op1_2) //|< r +,.in_op_valid (calc_op1_vld[2]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[2]) //|< r +,.out_final_data (calc_fout_2_sum) //|> w +,.out_final_sat (calc_fout_sat[2]) //|> w +,.out_final_valid (calc_fout_vld[2]) //|> w +,.out_partial_data (calc_pout_2_sum) //|> w +,.out_partial_valid (calc_pout_vld[2]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_3 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_3) //|< r +,.in_op (calc_op1_3) //|< r +,.in_op_valid (calc_op1_vld[3]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[3]) //|< r +,.out_final_data (calc_fout_3_sum) //|> w +,.out_final_sat (calc_fout_sat[3]) //|> w +,.out_final_valid (calc_fout_vld[3]) //|> w +,.out_partial_data (calc_pout_3_sum) //|> w +,.out_partial_valid (calc_pout_vld[3]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_4 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_4) //|< r +,.in_op (calc_op1_4) //|< r +,.in_op_valid (calc_op1_vld[4]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[4]) //|< r +,.out_final_data (calc_fout_4_sum) //|> w +,.out_final_sat (calc_fout_sat[4]) //|> w +,.out_final_valid (calc_fout_vld[4]) //|> w +,.out_partial_data (calc_pout_4_sum) //|> w +,.out_partial_valid (calc_pout_vld[4]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_5 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_5) //|< r +,.in_op (calc_op1_5) //|< r +,.in_op_valid (calc_op1_vld[5]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[5]) //|< r +,.out_final_data (calc_fout_5_sum) //|> w +,.out_final_sat (calc_fout_sat[5]) //|> w +,.out_final_valid (calc_fout_vld[5]) //|> w +,.out_partial_data (calc_pout_5_sum) //|> w +,.out_partial_valid (calc_pout_vld[5]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_6 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_6) //|< r +,.in_op (calc_op1_6) //|< r +,.in_op_valid (calc_op1_vld[6]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[6]) //|< r +,.out_final_data (calc_fout_6_sum) //|> w +,.out_final_sat (calc_fout_sat[6]) //|> w +,.out_final_valid (calc_fout_vld[6]) //|> w +,.out_partial_data (calc_pout_6_sum) //|> w +,.out_partial_valid (calc_pout_vld[6]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +NV_NVDLA_CACC_CALC_int8 u_cell_int8_7 ( +.cfg_truncate (cfg_truncate) //|< w +,.in_data (calc_op0_7) //|< r +,.in_op (calc_op1_7) //|< r +,.in_op_valid (calc_op1_vld[7]) //|< r +,.in_sel (calc_dlv_valid) //|< r +,.in_valid (calc_op_en[7]) //|< r +,.out_final_data (calc_fout_7_sum) //|> w +,.out_final_sat (calc_fout_sat[7]) //|> w +,.out_final_valid (calc_fout_vld[7]) //|> w +,.out_partial_data (calc_pout_7_sum) //|> w +,.out_partial_valid (calc_pout_vld[7]) //|> w +,.nvdla_core_clk (nvdla_cell_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire calc_valid_d0 = calc_valid; +wire calc_wr_en_d0 = calc_wr_en; +wire [5:0] calc_addr_d0 = calc_addr; +wire calc_dlv_valid_d0 = calc_dlv_valid; +wire calc_stripe_end_d0 = calc_stripe_end; +wire calc_layer_end_d0 = calc_layer_end; +// Latency pipeline to balance with calc cells, signal for both abuffer & dbuffer +//: my $start = 0; +//: for(my $i = $start; $i < $start + 2; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q calc_valid_d${j} -d \"calc_valid_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q calc_wr_en_d${j} -d \"calc_wr_en_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 6 -q calc_addr_d${j} -en \"calc_valid_d${i}\" -d \"calc_addr_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: } +//: my $pin = $start + 2; +//: print qq( +//: wire calc_valid_out = calc_valid_d${pin}; +//: wire calc_wr_en_out = calc_wr_en_d${pin}; +//: wire [5:0] calc_addr_out = calc_addr_d${pin}; +//: ); +//: +//: for(my $i = $start; $i < $start + 2; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q calc_dlv_valid_d${j} -d \"calc_dlv_valid_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q calc_stripe_end_d${j} -en \"calc_dlv_valid_d${i}\" -d \"calc_stripe_end_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q calc_layer_end_d${j} -en \"calc_dlv_valid_d${i}\" -d \"calc_layer_end_d${i} \" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: } +//: my $fin = $start + 2; +//: print qq( +//: wire calc_dlv_valid_out = calc_dlv_valid_d${fin}; +//: wire calc_stripe_end_out = calc_stripe_end_d${fin}; +//: wire calc_layer_end_out = calc_layer_end_d${fin}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg calc_valid_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_valid_d1 <= 'b0; + end else begin + calc_valid_d1 <= calc_valid_d0; + end +end +reg calc_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_wr_en_d1 <= 'b0; + end else begin + calc_wr_en_d1 <= calc_wr_en_d0; + end +end +reg [5:0] calc_addr_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_addr_d1 <= 'b0; + end else begin + if ((calc_valid_d0) == 1'b1) begin + calc_addr_d1 <= calc_addr_d0; + // VCS coverage off + end else if ((calc_valid_d0) == 1'b0) begin + end else begin + calc_addr_d1 <= 'bx; + // VCS coverage on + end + end +end +reg calc_valid_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_valid_d2 <= 'b0; + end else begin + calc_valid_d2 <= calc_valid_d1; + end +end +reg calc_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_wr_en_d2 <= 'b0; + end else begin + calc_wr_en_d2 <= calc_wr_en_d1; + end +end +reg [5:0] calc_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_addr_d2 <= 'b0; + end else begin + if ((calc_valid_d1) == 1'b1) begin + calc_addr_d2 <= calc_addr_d1; + // VCS coverage off + end else if ((calc_valid_d1) == 1'b0) begin + end else begin + calc_addr_d2 <= 'bx; + // VCS coverage on + end + end +end + +wire calc_valid_out = calc_valid_d2; +wire calc_wr_en_out = calc_wr_en_d2; +wire [5:0] calc_addr_out = calc_addr_d2; +reg calc_dlv_valid_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_dlv_valid_d1 <= 'b0; + end else begin + calc_dlv_valid_d1 <= calc_dlv_valid_d0; + end +end +reg calc_stripe_end_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_stripe_end_d1 <= 'b0; + end else begin + if ((calc_dlv_valid_d0) == 1'b1) begin + calc_stripe_end_d1 <= calc_stripe_end_d0; + // VCS coverage off + end else if ((calc_dlv_valid_d0) == 1'b0) begin + end else begin + calc_stripe_end_d1 <= 'bx; + // VCS coverage on + end + end +end +reg calc_layer_end_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_layer_end_d1 <= 'b0; + end else begin + if ((calc_dlv_valid_d0) == 1'b1) begin + calc_layer_end_d1 <= calc_layer_end_d0 ; + // VCS coverage off + end else if ((calc_dlv_valid_d0) == 1'b0) begin + end else begin + calc_layer_end_d1 <= 'bx; + // VCS coverage on + end + end +end +reg calc_dlv_valid_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_dlv_valid_d2 <= 'b0; + end else begin + calc_dlv_valid_d2 <= calc_dlv_valid_d1; + end +end +reg calc_stripe_end_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_stripe_end_d2 <= 'b0; + end else begin + if ((calc_dlv_valid_d1) == 1'b1) begin + calc_stripe_end_d2 <= calc_stripe_end_d1; + // VCS coverage off + end else if ((calc_dlv_valid_d1) == 1'b0) begin + end else begin + calc_stripe_end_d2 <= 'bx; + // VCS coverage on + end + end +end +reg calc_layer_end_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + calc_layer_end_d2 <= 'b0; + end else begin + if ((calc_dlv_valid_d1) == 1'b1) begin + calc_layer_end_d2 <= calc_layer_end_d1 ; + // VCS coverage off + end else if ((calc_dlv_valid_d1) == 1'b0) begin + end else begin + calc_layer_end_d2 <= 'bx; + // VCS coverage on + end + end +end + +wire calc_dlv_valid_out = calc_dlv_valid_d2; +wire calc_stripe_end_out = calc_stripe_end_d2; +wire calc_layer_end_out = calc_layer_end_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// Gather of accumulator result +//: my $int8_out = 34; +//: my $final_out = 32; +//: for(my $i=0; $i <8; $i ++) { +//: print qq( +//: wire [${int8_out}-1:0] calc_pout_${i} = ({${int8_out}{calc_pout_vld[${i}]}} & calc_pout_${i}_sum);); +//: } +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: wire [${final_out}-1:0] calc_fout_${i} = ({${final_out}{calc_fout_vld[${i}]}} & calc_fout_${i}_sum);); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [34-1:0] calc_pout_0 = ({34{calc_pout_vld[0]}} & calc_pout_0_sum); +wire [34-1:0] calc_pout_1 = ({34{calc_pout_vld[1]}} & calc_pout_1_sum); +wire [34-1:0] calc_pout_2 = ({34{calc_pout_vld[2]}} & calc_pout_2_sum); +wire [34-1:0] calc_pout_3 = ({34{calc_pout_vld[3]}} & calc_pout_3_sum); +wire [34-1:0] calc_pout_4 = ({34{calc_pout_vld[4]}} & calc_pout_4_sum); +wire [34-1:0] calc_pout_5 = ({34{calc_pout_vld[5]}} & calc_pout_5_sum); +wire [34-1:0] calc_pout_6 = ({34{calc_pout_vld[6]}} & calc_pout_6_sum); +wire [34-1:0] calc_pout_7 = ({34{calc_pout_vld[7]}} & calc_pout_7_sum); +wire [32-1:0] calc_fout_0 = ({32{calc_fout_vld[0]}} & calc_fout_0_sum); +wire [32-1:0] calc_fout_1 = ({32{calc_fout_vld[1]}} & calc_fout_1_sum); +wire [32-1:0] calc_fout_2 = ({32{calc_fout_vld[2]}} & calc_fout_2_sum); +wire [32-1:0] calc_fout_3 = ({32{calc_fout_vld[3]}} & calc_fout_3_sum); +wire [32-1:0] calc_fout_4 = ({32{calc_fout_vld[4]}} & calc_fout_4_sum); +wire [32-1:0] calc_fout_5 = ({32{calc_fout_vld[5]}} & calc_fout_5_sum); +wire [32-1:0] calc_fout_6 = ({32{calc_fout_vld[6]}} & calc_fout_6_sum); +wire [32-1:0] calc_fout_7 = ({32{calc_fout_vld[7]}} & calc_fout_7_sum); +//| eperl: generated_end (DO NOT EDIT ABOVE) +// to abuffer, 1 pipe +wire [34*8 -1:0] abuf_wr_data_w; +// spyglass disable_block STARC05-3.3.1.4b +//: my $kk=34*8; +//: my $jj=3 +1; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq ( +//: assign abuf_wr_data_w[34*($i+1)-1:34*$i] = calc_pout_${i}; ); +//: } +//: &eperl::flop(" -q abuf_wr_en -d \"calc_wr_en_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${jj} -q abuf_wr_addr -en \"calc_wr_en_out\" -d \"calc_addr_out[${jj}-1:0]\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q abuf_wr_data -en \"calc_wr_en_out\" -d \"abuf_wr_data_w\" -clk nvdla_core_clk -norst"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign abuf_wr_data_w[34*(0+1)-1:34*0] = calc_pout_0; +assign abuf_wr_data_w[34*(1+1)-1:34*1] = calc_pout_1; +assign abuf_wr_data_w[34*(2+1)-1:34*2] = calc_pout_2; +assign abuf_wr_data_w[34*(3+1)-1:34*3] = calc_pout_3; +assign abuf_wr_data_w[34*(4+1)-1:34*4] = calc_pout_4; +assign abuf_wr_data_w[34*(5+1)-1:34*5] = calc_pout_5; +assign abuf_wr_data_w[34*(6+1)-1:34*6] = calc_pout_6; +assign abuf_wr_data_w[34*(7+1)-1:34*7] = calc_pout_7; reg abuf_wr_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + abuf_wr_en <= 'b0; + end else begin + abuf_wr_en <= calc_wr_en_out; + end +end +reg [3:0] abuf_wr_addr; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + abuf_wr_addr <= 'b0; + end else begin + if ((calc_wr_en_out) == 1'b1) begin + abuf_wr_addr <= calc_addr_out[4-1:0]; + // VCS coverage off + end else if ((calc_wr_en_out) == 1'b0) begin + end else begin + abuf_wr_addr <= 'bx; + // VCS coverage on + end + end +end +reg [271:0] abuf_wr_data; +always @(posedge nvdla_core_clk) begin + if ((calc_wr_en_out) == 1'b1) begin + abuf_wr_data <= abuf_wr_data_w; + // VCS coverage off + end else if ((calc_wr_en_out) == 1'b0) begin + end else begin + abuf_wr_data <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block STARC05-3.3.1.4b +// to dbuffer, 1 pipe. +wire [32*8 -1:0] dlv_data_w; +// spyglass disable_block STARC05-3.3.1.4b +//: my $kk=32*8; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( +//: assign dlv_data_w[32*($i+1)-1:32*$i] = calc_fout_${i};); +//: } +//: +//: &eperl::flop("-wid ${kk} -q dlv_data -en \"calc_dlv_valid_out\" -d \"dlv_data_w\" -clk nvdla_core_clk -norst"); +//: &eperl::flop(" -q dlv_valid -d \"calc_dlv_valid_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_mask -d \"calc_dlv_valid_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_stripe_end -en \"calc_dlv_valid_out\" -d \"calc_stripe_end_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_layer_end -en \"calc_dlv_valid_out\" -d \"calc_layer_end_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dlv_data_w[32*(0+1)-1:32*0] = calc_fout_0; +assign dlv_data_w[32*(1+1)-1:32*1] = calc_fout_1; +assign dlv_data_w[32*(2+1)-1:32*2] = calc_fout_2; +assign dlv_data_w[32*(3+1)-1:32*3] = calc_fout_3; +assign dlv_data_w[32*(4+1)-1:32*4] = calc_fout_4; +assign dlv_data_w[32*(5+1)-1:32*5] = calc_fout_5; +assign dlv_data_w[32*(6+1)-1:32*6] = calc_fout_6; +assign dlv_data_w[32*(7+1)-1:32*7] = calc_fout_7;reg [255:0] dlv_data; +always @(posedge nvdla_core_clk) begin + if ((calc_dlv_valid_out) == 1'b1) begin + dlv_data <= dlv_data_w; + // VCS coverage off + end else if ((calc_dlv_valid_out) == 1'b0) begin + end else begin + dlv_data <= 'bx; + // VCS coverage on + end +end +reg dlv_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_valid <= 'b0; + end else begin + dlv_valid <= calc_dlv_valid_out; + end +end +reg dlv_mask; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_mask <= 'b0; + end else begin + dlv_mask <= calc_dlv_valid_out; + end +end +reg dlv_stripe_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_stripe_end <= 'b0; + end else begin + if ((calc_dlv_valid_out) == 1'b1) begin + dlv_stripe_end <= calc_stripe_end_out; + // VCS coverage off + end else if ((calc_dlv_valid_out) == 1'b0) begin + end else begin + dlv_stripe_end <= 'bx; + // VCS coverage on + end + end +end +reg dlv_layer_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_layer_end <= 'b0; + end else begin + if ((calc_dlv_valid_out) == 1'b1) begin + dlv_layer_end <= calc_layer_end_out; + // VCS coverage off + end else if ((calc_dlv_valid_out) == 1'b0) begin + end else begin + dlv_layer_end <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block STARC05-3.3.1.4b +assign dlv_pd[0] = dlv_stripe_end ; +assign dlv_pd[1] = dlv_layer_end ; +// overflow count +reg dlv_sat_end_d1; +wire [8 -1:0] dlv_sat_bit = calc_fout_sat; +wire dlv_sat_end = calc_layer_end_out & calc_stripe_end_out; +wire dlv_sat_clr = calc_dlv_valid_out & ~dlv_sat_end & dlv_sat_end_d1; +//: my $kk= 8; +//: my $jj= 3; +//: &eperl::flop(" -q dlv_sat_vld_d1 -d \"calc_dlv_valid_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_sat_end_d1 -en \"calc_dlv_valid_out\" -d \"dlv_sat_end\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 1"); +//: &eperl::flop(" -wid ${kk} -q dlv_sat_bit_d1 -en \"calc_dlv_valid_out\" -d \"dlv_sat_bit\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_sat_clr_d1 -d \"dlv_sat_clr\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: print "wire [${jj}-1:0] sat_sum = "; +//: for(my $i=0; $i<8 -1 ; $i++){ +//: print "dlv_sat_bit_d1[${i}]+"; +//: } +//: my $i=8 -1; +//: print "dlv_sat_bit_d1[${i}]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg dlv_sat_vld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_sat_vld_d1 <= 'b0; + end else begin + dlv_sat_vld_d1 <= calc_dlv_valid_out; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_sat_end_d1 <= 1; + end else begin + if ((calc_dlv_valid_out) == 1'b1) begin + dlv_sat_end_d1 <= dlv_sat_end; + // VCS coverage off + end else if ((calc_dlv_valid_out) == 1'b0) begin + end else begin + dlv_sat_end_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] dlv_sat_bit_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_sat_bit_d1 <= 'b0; + end else begin + if ((calc_dlv_valid_out) == 1'b1) begin + dlv_sat_bit_d1 <= dlv_sat_bit; + // VCS coverage off + end else if ((calc_dlv_valid_out) == 1'b0) begin + end else begin + dlv_sat_bit_d1 <= 'bx; + // VCS coverage on + end + end +end +reg dlv_sat_clr_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_sat_clr_d1 <= 'b0; + end else begin + dlv_sat_clr_d1 <= dlv_sat_clr; + end +end +wire [3-1:0] sat_sum = dlv_sat_bit_d1[0]+dlv_sat_bit_d1[1]+dlv_sat_bit_d1[2]+dlv_sat_bit_d1[3]+dlv_sat_bit_d1[4]+dlv_sat_bit_d1[5]+dlv_sat_bit_d1[6]+dlv_sat_bit_d1[7]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [31:0] sat_count_inc; +reg [31:0] sat_count; +wire sat_carry; +wire [31:0] sat_count_w; +wire sat_reg_en; +assign {sat_carry, sat_count_inc[31:0]} = sat_count + sat_sum; +assign sat_count_w = (dlv_sat_clr_d1) ? {24'b0, sat_sum} : sat_carry ? {32{1'b1}} : sat_count_inc; +assign sat_reg_en = dlv_sat_vld_d1 & ((|sat_sum) | dlv_sat_clr_d1); +//: &eperl::flop("-nodeclare -q sat_count -en \"sat_reg_en\" -d \"sat_count_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sat_count <= 'b0; + end else begin + if ((sat_reg_en) == 1'b1) begin + sat_count <= sat_count_w; + // VCS coverage off + end else if ((sat_reg_en) == 1'b0) begin + end else begin + sat_count <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.1.6 +assign dp2reg_sat_count = sat_count; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v.vcp new file mode 100644 index 0000000..cc66bb8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v.vcp @@ -0,0 +1,258 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_calculator.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_calculator ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,abuf_rd_data //|< i + ,accu_ctrl_pd //|< i + ,accu_ctrl_ram_valid //|< i + ,accu_ctrl_valid //|< i + ,cfg_in_en_mask //|< i + ,cfg_is_wg //|< i + ,cfg_truncate //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_a2accu_data${i} //|< i ) +//: } + ,mac_a2accu_mask //|< i + ,mac_a2accu_mode //|< i + ,mac_a2accu_pvld //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_b2accu_data${i} //|< i ) +//: } + ,mac_b2accu_mask //|< i + ,mac_b2accu_mode //|< i + ,mac_b2accu_pvld //|< i + ,nvdla_cell_clk //|< i + ,abuf_wr_addr //|> o + ,abuf_wr_data //|> o + ,abuf_wr_en //|> o + ,dlv_data //|> o + ,dlv_mask //|> o + ,dlv_pd //|> o + ,dlv_valid //|> o + ,dp2reg_sat_count //|> o + ); +input nvdla_cell_clk; +input nvdla_core_clk; +input nvdla_core_rstn; +input [34*8 -1:0] abuf_rd_data; +input [12:0] accu_ctrl_pd; +input accu_ctrl_ram_valid; +input accu_ctrl_valid; +input cfg_in_en_mask; +input cfg_is_wg; +input [4:0] cfg_truncate; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_a2accu_data${i}; ) +//: } +input [8/2-1:0] mac_a2accu_mask; +input mac_a2accu_mode; +input mac_a2accu_pvld; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_b2accu_data${i}; ) +//: } +input [8/2-1:0] mac_b2accu_mask; +input mac_b2accu_mode; +input mac_b2accu_pvld; +output [3 +1 -1:0] abuf_wr_addr; +output [34*8 -1:0] abuf_wr_data; +output abuf_wr_en; +output [32*8 -1:0] dlv_data; +output dlv_mask; +output [1:0] dlv_pd; +output dlv_valid; +output [31:0] dp2reg_sat_count; +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.1.6 +// unpack abuffer read data +//: my $kk=34; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: wire [${kk}-1:0] abuf_in_data_${i} = abuf_rd_data[($i+1)*${kk}-1:$i*${kk}]; ) +//: } +//1T delay, the same T with data/mask +//: &eperl::flop("-wid 13 -q accu_ctrl_pd_d1 -en accu_ctrl_valid -d accu_ctrl_pd"); +wire calc_valid_in = (mac_b2accu_pvld | mac_a2accu_pvld); +// spyglass disable_block STARC05-3.3.1.4b +//: &eperl::retime("-stage 3 -o calc_valid -i calc_valid_in"); +// spyglass enable_block STARC05-3.3.1.4b +// unpack pd form abuffer control +wire [5:0] calc_addr = accu_ctrl_pd_d1[5:0]; +wire [2:0] calc_mode = accu_ctrl_pd_d1[8:6]; +wire calc_stripe_end = accu_ctrl_pd_d1[9]; +wire calc_channel_end = accu_ctrl_pd_d1[10]; +wire calc_layer_end = accu_ctrl_pd_d1[11]; +wire calc_dlv_elem_mask = accu_ctrl_pd_d1[12]; +//: my $kk=19; +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print "wire [${kk}-1:0] calc_elem_${i} = mac_a2accu_data${i}; \n"; +//: } +//: for(my $i = 8/2; $i < 8; $i ++) { +//: my $j = $i - 8/2; +//: print "wire [${kk}-1:0] calc_elem_${i} = mac_b2accu_data${j}; \n"; +//: } +wire [8 -1:0] calc_in_mask = {mac_b2accu_mask, mac_a2accu_mask}; +wire [8 -1:0] calc_op_en = calc_in_mask & {8{cfg_in_en_mask}}; +wire [8 -1:0] calc_op1_vld = calc_in_mask & {8{cfg_in_en_mask & accu_ctrl_ram_valid}}; +wire calc_dlv_valid = calc_valid & calc_channel_end; +wire calc_wr_en = calc_valid & (~calc_channel_end); +//: my $hh= 22-19; +//: my $pp= 34; +//: my $bb= 19; +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: wire [21:0]calc_op0_${i} = {{${hh}{calc_elem_${i}[${bb}-1]}},calc_elem_${i}}; +//: wire [${pp}-1:0] calc_op1_${i} = abuf_in_data_${i}; +//: ); +//: } +// instance int8 adders +wire [8 -1:0] calc_fout_sat; +wire [8 -1:0] calc_pout_vld; +wire [8 -1:0] calc_fout_vld; +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: wire [34 -1:0] calc_pout_${i}_sum; +//: wire [32 -1:0] calc_fout_${i}_sum; +//: ) +//: } +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: NV_NVDLA_CACC_CALC_int8 u_cell_int8_${i} ( +//: .cfg_truncate (cfg_truncate) //|< w +//: ,.in_data (calc_op0_${i}) //|< r +//: ,.in_op (calc_op1_${i}) //|< r +//: ,.in_op_valid (calc_op1_vld[${i}]) //|< r +//: ,.in_sel (calc_dlv_valid) //|< r +//: ,.in_valid (calc_op_en[${i}]) //|< r +//: ,.out_final_data (calc_fout_${i}_sum) //|> w +//: ,.out_final_sat (calc_fout_sat[${i}]) //|> w +//: ,.out_final_valid (calc_fout_vld[${i}]) //|> w +//: ,.out_partial_data (calc_pout_${i}_sum) //|> w +//: ,.out_partial_valid (calc_pout_vld[${i}]) //|> w +//: ,.nvdla_core_clk (nvdla_cell_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ); +//: ) +//: } +wire calc_valid_d0 = calc_valid; +wire calc_wr_en_d0 = calc_wr_en; +wire [5:0] calc_addr_d0 = calc_addr; +wire calc_dlv_valid_d0 = calc_dlv_valid; +wire calc_stripe_end_d0 = calc_stripe_end; +wire calc_layer_end_d0 = calc_layer_end; +// Latency pipeline to balance with calc cells, signal for both abuffer & dbuffer +//: my $start = 0; +//: for(my $i = $start; $i < $start + 2; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q calc_valid_d${j} -d \"calc_valid_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q calc_wr_en_d${j} -d \"calc_wr_en_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 6 -q calc_addr_d${j} -en \"calc_valid_d${i}\" -d \"calc_addr_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: } +//: my $pin = $start + 2; +//: print qq( +//: wire calc_valid_out = calc_valid_d${pin}; +//: wire calc_wr_en_out = calc_wr_en_d${pin}; +//: wire [5:0] calc_addr_out = calc_addr_d${pin}; +//: ); +//: +//: for(my $i = $start; $i < $start + 2; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q calc_dlv_valid_d${j} -d \"calc_dlv_valid_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q calc_stripe_end_d${j} -en \"calc_dlv_valid_d${i}\" -d \"calc_stripe_end_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q calc_layer_end_d${j} -en \"calc_dlv_valid_d${i}\" -d \"calc_layer_end_d${i} \" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: } +//: my $fin = $start + 2; +//: print qq( +//: wire calc_dlv_valid_out = calc_dlv_valid_d${fin}; +//: wire calc_stripe_end_out = calc_stripe_end_d${fin}; +//: wire calc_layer_end_out = calc_layer_end_d${fin}; +//: ); +// Gather of accumulator result +//: my $int8_out = 34; +//: my $final_out = 32; +//: for(my $i=0; $i <8; $i ++) { +//: print qq( +//: wire [${int8_out}-1:0] calc_pout_${i} = ({${int8_out}{calc_pout_vld[${i}]}} & calc_pout_${i}_sum);); +//: } +//: for(my $i = 0; $i <8; $i ++) { +//: print qq( +//: wire [${final_out}-1:0] calc_fout_${i} = ({${final_out}{calc_fout_vld[${i}]}} & calc_fout_${i}_sum);); +//: } +// to abuffer, 1 pipe +wire [34*8 -1:0] abuf_wr_data_w; +// spyglass disable_block STARC05-3.3.1.4b +//: my $kk=34*8; +//: my $jj=3 +1; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq ( +//: assign abuf_wr_data_w[34*($i+1)-1:34*$i] = calc_pout_${i}; ); +//: } +//: &eperl::flop(" -q abuf_wr_en -d \"calc_wr_en_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${jj} -q abuf_wr_addr -en \"calc_wr_en_out\" -d \"calc_addr_out[${jj}-1:0]\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q abuf_wr_data -en \"calc_wr_en_out\" -d \"abuf_wr_data_w\" -clk nvdla_core_clk -norst"); +// spyglass enable_block STARC05-3.3.1.4b +// to dbuffer, 1 pipe. +wire [32*8 -1:0] dlv_data_w; +// spyglass disable_block STARC05-3.3.1.4b +//: my $kk=32*8; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( +//: assign dlv_data_w[32*($i+1)-1:32*$i] = calc_fout_${i};); +//: } +//: +//: &eperl::flop("-wid ${kk} -q dlv_data -en \"calc_dlv_valid_out\" -d \"dlv_data_w\" -clk nvdla_core_clk -norst"); +//: &eperl::flop(" -q dlv_valid -d \"calc_dlv_valid_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_mask -d \"calc_dlv_valid_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_stripe_end -en \"calc_dlv_valid_out\" -d \"calc_stripe_end_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_layer_end -en \"calc_dlv_valid_out\" -d \"calc_layer_end_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +// spyglass enable_block STARC05-3.3.1.4b +assign dlv_pd[0] = dlv_stripe_end ; +assign dlv_pd[1] = dlv_layer_end ; +// overflow count +reg dlv_sat_end_d1; +wire [8 -1:0] dlv_sat_bit = calc_fout_sat; +wire dlv_sat_end = calc_layer_end_out & calc_stripe_end_out; +wire dlv_sat_clr = calc_dlv_valid_out & ~dlv_sat_end & dlv_sat_end_d1; +//: my $kk= 8; +//: my $jj= 3; +//: &eperl::flop(" -q dlv_sat_vld_d1 -d \"calc_dlv_valid_out\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_sat_end_d1 -en \"calc_dlv_valid_out\" -d \"dlv_sat_end\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 1"); +//: &eperl::flop(" -wid ${kk} -q dlv_sat_bit_d1 -en \"calc_dlv_valid_out\" -d \"dlv_sat_bit\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_sat_clr_d1 -d \"dlv_sat_clr\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: print "wire [${jj}-1:0] sat_sum = "; +//: for(my $i=0; $i<8 -1 ; $i++){ +//: print "dlv_sat_bit_d1[${i}]+"; +//: } +//: my $i=8 -1; +//: print "dlv_sat_bit_d1[${i}]; \n"; +wire [31:0] sat_count_inc; +reg [31:0] sat_count; +wire sat_carry; +wire [31:0] sat_count_w; +wire sat_reg_en; +assign {sat_carry, sat_count_inc[31:0]} = sat_count + sat_sum; +assign sat_count_w = (dlv_sat_clr_d1) ? {24'b0, sat_sum} : sat_carry ? {32{1'b1}} : sat_count_inc; +assign sat_reg_en = dlv_sat_vld_d1 & ((|sat_sum) | dlv_sat_clr_d1); +//: &eperl::flop("-nodeclare -q sat_count -en \"sat_reg_en\" -d \"sat_count_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.1.6 +assign dp2reg_sat_count = sat_count; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v new file mode 100644 index 0000000..a86105e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v @@ -0,0 +1,212 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_delivery_buffer.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_delivery_buffer ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2sdp_ready //|< i + ,dbuf_rd_addr //|< i + ,dbuf_rd_en //|< i + ,dbuf_rd_layer_end //|< i + ,dbuf_wr_addr //|< i + ,dbuf_wr_data //|< i + ,dbuf_wr_en //|< i + ,pwrbus_ram_pd //|< i + ,cacc2glb_done_intr_pd //|> o + ,cacc2sdp_pd //|> o + ,cacc2sdp_valid //|> o + ,dbuf_rd_ready //|> o + ,accu2sc_credit_size //|> o + ,accu2sc_credit_vld //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc2sdp_ready; +input [3 +1 -1:0] dbuf_rd_addr; +input dbuf_rd_en; +input dbuf_rd_layer_end; +input [3 +1 -1:0] dbuf_wr_addr; +input [32*8 -1:0] dbuf_wr_data; +input dbuf_wr_en; +input [31:0] pwrbus_ram_pd; +output [1:0] cacc2glb_done_intr_pd; +output [32*1 +2 -1:0] cacc2sdp_pd; +output cacc2sdp_valid; +output dbuf_rd_ready; +output [2:0] accu2sc_credit_size; +output accu2sc_credit_vld; +// Instance RAMs +wire [32*8 -1:0] dbuf_rd_data; +reg [(32*8)/(32*1)-1:0] data_left_mask; +wire dbuf_rd_en_new = ~(|data_left_mask) & dbuf_rd_en; +// spyglass disable_block NoWidthInBasedNum-ML +//: my $dep= 8*2; +//: my $wid= 32*8; +//: print qq( +//: nv_ram_rws_${dep}x${wid} u_accu_dbuf ( +//: .clk (nvdla_core_clk) //|< i +//: ,.ra (dbuf_rd_addr) //|< r +//: ,.re (dbuf_rd_en_new) //|< r +//: ,.dout (dbuf_rd_data) //|> w +//: ,.wa (dbuf_wr_addr) //|< r +//: ,.we (dbuf_wr_en) //|< r +//: ,.di (dbuf_wr_data) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +//: ); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +nv_ram_rws_16x256 u_accu_dbuf ( +.clk (nvdla_core_clk) //|< i +,.ra (dbuf_rd_addr) //|< r +,.re (dbuf_rd_en_new) //|< r +,.dout (dbuf_rd_data) //|> w +,.wa (dbuf_wr_addr) //|< r +,.we (dbuf_wr_en) //|< r +,.di (dbuf_wr_data) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get signal for SDP +//: &eperl::flop("-q dbuf_rd_valid -d \"dbuf_rd_en_new\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: my $kk=(32*8)/(32*1); +//: print qq( +//: reg [${kk}-1:0] rd_data_mask; //which data to be fetched by sdp. +//: wire [${kk}-1:0] rd_data_mask_pre; ); +//: if(${kk}>=2){ +//: print "assign rd_data_mask_pre = cacc2sdp_valid & cacc2sdp_ready ? {rd_data_mask[${kk}-2:0],rd_data_mask[${kk}-1]} : rd_data_mask; \n"; +//: } else { +//: print "assign rd_data_mask_pre = rd_data_mask; \n"; +//:} +//: &eperl::flop("-nodeclare -q rd_data_mask -d rd_data_mask_pre -rval \" 'b1\" "); +//: print qq( +//: wire [${kk}-1:0] data_left_mask_pre = dbuf_rd_en_new ? {${kk}{1'b1}} : (cacc2sdp_valid & cacc2sdp_ready) ? (data_left_mask<<1'b1) : data_left_mask; +//: ); +//: &eperl::flop("-nodeclare -q data_left_mask -d data_left_mask_pre "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg dbuf_rd_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_rd_valid <= 'b0; + end else begin + dbuf_rd_valid <= dbuf_rd_en_new; + end +end + +reg [8-1:0] rd_data_mask; //which data to be fetched by sdp. +wire [8-1:0] rd_data_mask_pre; assign rd_data_mask_pre = cacc2sdp_valid & cacc2sdp_ready ? {rd_data_mask[8-2:0],rd_data_mask[8-1]} : rd_data_mask; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_data_mask <= 'b1; + end else begin + rd_data_mask <= rd_data_mask_pre; + end +end + +wire [8-1:0] data_left_mask_pre = dbuf_rd_en_new ? {8{1'b1}} : (cacc2sdp_valid & cacc2sdp_ready) ? (data_left_mask<<1'b1) : data_left_mask; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_left_mask <= 'b0; + end else begin + data_left_mask <= data_left_mask_pre; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire cacc2sdp_valid = (|data_left_mask); +wire dbuf_rd_ready = ~(|data_left_mask); +//: my $t1=""; +//: my $kk= 32*1; +//: print "wire [${kk}-1:0] cacc2sdp_pd_data= "; +//: for (my $i=0; $i<(32*8)/(32*1); $i++){ +//: $t1 .= "dbuf_rd_data[($i+1)*${kk}-1:$i*${kk}]&{${kk}{rd_data_mask[${i}]}} |"; +//: } +//: my $t2= "{${kk}{1'b0}}"; +//: print "$t1"."$t2".";\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [32-1:0] cacc2sdp_pd_data= dbuf_rd_data[(0+1)*32-1:0*32]&{32{rd_data_mask[0]}} |dbuf_rd_data[(1+1)*32-1:1*32]&{32{rd_data_mask[1]}} |dbuf_rd_data[(2+1)*32-1:2*32]&{32{rd_data_mask[2]}} |dbuf_rd_data[(3+1)*32-1:3*32]&{32{rd_data_mask[3]}} |dbuf_rd_data[(4+1)*32-1:4*32]&{32{rd_data_mask[4]}} |dbuf_rd_data[(5+1)*32-1:5*32]&{32{rd_data_mask[5]}} |dbuf_rd_data[(6+1)*32-1:6*32]&{32{rd_data_mask[6]}} |dbuf_rd_data[(7+1)*32-1:7*32]&{32{rd_data_mask[7]}} |{32{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//layer_end handle +reg dbuf_rd_layer_end_latch; +wire dbuf_rd_layer_end_latch_w = dbuf_rd_layer_end? 1'b1 : ~(|data_left_mask) ? 1'b0 : dbuf_rd_layer_end_latch; +//: &eperl::flop("-q dbuf_rd_layer_end_latch -d dbuf_rd_layer_end_latch_w -nodeclare"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_rd_layer_end_latch <= 'b0; + end else begin + dbuf_rd_layer_end_latch <= dbuf_rd_layer_end_latch_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////regout to SDP +////: my $kk=CACC_SDP_DATA_WIDTH; +////: &eperl::flop("-q cacc2sdp_valid -d cacc2sdp_valid_w"); +////: &eperl::flop("-wid ${kk} -q cacc2sdp_pd_data -d cacc2sdp_pd_data_w"); +wire last_data; +wire cacc2sdp_batch_end = 1'b0; +wire cacc2sdp_layer_end = dbuf_rd_layer_end_latch&last_data&cacc2sdp_valid&cacc2sdp_ready; //data_left_mask=0; +assign cacc2sdp_pd[32*1 -1:0] = cacc2sdp_pd_data; +assign cacc2sdp_pd[32*1 +2 -2] = cacc2sdp_batch_end; +assign cacc2sdp_pd[32*1 +2 -1] = cacc2sdp_layer_end; +// generate CACC done interrupt +wire [1:0] cacc_done_intr_w; +reg intr_sel; +wire cacc_done = cacc2sdp_valid & cacc2sdp_ready & cacc2sdp_layer_end; +assign cacc_done_intr_w[0] = cacc_done & ~intr_sel; +assign cacc_done_intr_w[1] = cacc_done & intr_sel; +wire intr_sel_w = cacc_done ? ~intr_sel : intr_sel; +//: &eperl::flop("-nodeclare -q intr_sel -d \"intr_sel_w \" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cacc_done_intr -d \"cacc_done_intr_w \" -wid 2 -clk nvdla_core_clk -rst nvdla_core_rstn "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intr_sel <= 'b0; + end else begin + intr_sel <= intr_sel_w ; + end +end +reg [1:0] cacc_done_intr; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_intr <= 'b0; + end else begin + cacc_done_intr <= cacc_done_intr_w ; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cacc2glb_done_intr_pd = cacc_done_intr; +///// generate credit signal +assign accu2sc_credit_size = 3'h1; +assign last_data = (data_left_mask=={1'b1,{(32*8)/(32*1)-1{1'b0}}}); +//: &eperl::flop(" -q accu2sc_credit_vld -d \"cacc2sdp_valid & cacc2sdp_ready & last_data\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg accu2sc_credit_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + accu2sc_credit_vld <= 'b0; + end else begin + accu2sc_credit_vld <= cacc2sdp_valid & cacc2sdp_ready & last_data; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block NoWidthInBasedNum-ML +endmodule // NV_NVDLA_CACC_delivery_buffer diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v.vcp new file mode 100644 index 0000000..76b6388 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v.vcp @@ -0,0 +1,125 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_delivery_buffer.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_delivery_buffer ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2sdp_ready //|< i + ,dbuf_rd_addr //|< i + ,dbuf_rd_en //|< i + ,dbuf_rd_layer_end //|< i + ,dbuf_wr_addr //|< i + ,dbuf_wr_data //|< i + ,dbuf_wr_en //|< i + ,pwrbus_ram_pd //|< i + ,cacc2glb_done_intr_pd //|> o + ,cacc2sdp_pd //|> o + ,cacc2sdp_valid //|> o + ,dbuf_rd_ready //|> o + ,accu2sc_credit_size //|> o + ,accu2sc_credit_vld //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc2sdp_ready; +input [3 +1 -1:0] dbuf_rd_addr; +input dbuf_rd_en; +input dbuf_rd_layer_end; +input [3 +1 -1:0] dbuf_wr_addr; +input [32*8 -1:0] dbuf_wr_data; +input dbuf_wr_en; +input [31:0] pwrbus_ram_pd; +output [1:0] cacc2glb_done_intr_pd; +output [32*1 +2 -1:0] cacc2sdp_pd; +output cacc2sdp_valid; +output dbuf_rd_ready; +output [2:0] accu2sc_credit_size; +output accu2sc_credit_vld; +// Instance RAMs +wire [32*8 -1:0] dbuf_rd_data; +reg [(32*8)/(32*1)-1:0] data_left_mask; +wire dbuf_rd_en_new = ~(|data_left_mask) & dbuf_rd_en; +// spyglass disable_block NoWidthInBasedNum-ML +//: my $dep= 8*2; +//: my $wid= 32*8; +//: print qq( +//: nv_ram_rws_${dep}x${wid} u_accu_dbuf ( +//: .clk (nvdla_core_clk) //|< i +//: ,.ra (dbuf_rd_addr) //|< r +//: ,.re (dbuf_rd_en_new) //|< r +//: ,.dout (dbuf_rd_data) //|> w +//: ,.wa (dbuf_wr_addr) //|< r +//: ,.we (dbuf_wr_en) //|< r +//: ,.di (dbuf_wr_data) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +//: ); +//: ); +//get signal for SDP +//: &eperl::flop("-q dbuf_rd_valid -d \"dbuf_rd_en_new\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: my $kk=(32*8)/(32*1); +//: print qq( +//: reg [${kk}-1:0] rd_data_mask; //which data to be fetched by sdp. +//: wire [${kk}-1:0] rd_data_mask_pre; ); +//: if(${kk}>=2){ +//: print "assign rd_data_mask_pre = cacc2sdp_valid & cacc2sdp_ready ? {rd_data_mask[${kk}-2:0],rd_data_mask[${kk}-1]} : rd_data_mask; \n"; +//: } else { +//: print "assign rd_data_mask_pre = rd_data_mask; \n"; +//:} +//: &eperl::flop("-nodeclare -q rd_data_mask -d rd_data_mask_pre -rval \" 'b1\" "); +//: print qq( +//: wire [${kk}-1:0] data_left_mask_pre = dbuf_rd_en_new ? {${kk}{1'b1}} : (cacc2sdp_valid & cacc2sdp_ready) ? (data_left_mask<<1'b1) : data_left_mask; +//: ); +//: &eperl::flop("-nodeclare -q data_left_mask -d data_left_mask_pre "); +wire cacc2sdp_valid = (|data_left_mask); +wire dbuf_rd_ready = ~(|data_left_mask); +//: my $t1=""; +//: my $kk= 32*1; +//: print "wire [${kk}-1:0] cacc2sdp_pd_data= "; +//: for (my $i=0; $i<(32*8)/(32*1); $i++){ +//: $t1 .= "dbuf_rd_data[($i+1)*${kk}-1:$i*${kk}]&{${kk}{rd_data_mask[${i}]}} |"; +//: } +//: my $t2= "{${kk}{1'b0}}"; +//: print "$t1"."$t2".";\n"; +//layer_end handle +reg dbuf_rd_layer_end_latch; +wire dbuf_rd_layer_end_latch_w = dbuf_rd_layer_end? 1'b1 : ~(|data_left_mask) ? 1'b0 : dbuf_rd_layer_end_latch; +//: &eperl::flop("-q dbuf_rd_layer_end_latch -d dbuf_rd_layer_end_latch_w -nodeclare"); +////regout to SDP +////: my $kk=CACC_SDP_DATA_WIDTH; +////: &eperl::flop("-q cacc2sdp_valid -d cacc2sdp_valid_w"); +////: &eperl::flop("-wid ${kk} -q cacc2sdp_pd_data -d cacc2sdp_pd_data_w"); +wire last_data; +wire cacc2sdp_batch_end = 1'b0; +wire cacc2sdp_layer_end = dbuf_rd_layer_end_latch&last_data&cacc2sdp_valid&cacc2sdp_ready; //data_left_mask=0; +assign cacc2sdp_pd[32*1 -1:0] = cacc2sdp_pd_data; +assign cacc2sdp_pd[32*1 +2 -2] = cacc2sdp_batch_end; +assign cacc2sdp_pd[32*1 +2 -1] = cacc2sdp_layer_end; +// generate CACC done interrupt +wire [1:0] cacc_done_intr_w; +reg intr_sel; +wire cacc_done = cacc2sdp_valid & cacc2sdp_ready & cacc2sdp_layer_end; +assign cacc_done_intr_w[0] = cacc_done & ~intr_sel; +assign cacc_done_intr_w[1] = cacc_done & intr_sel; +wire intr_sel_w = cacc_done ? ~intr_sel : intr_sel; +//: &eperl::flop("-nodeclare -q intr_sel -d \"intr_sel_w \" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cacc_done_intr -d \"cacc_done_intr_w \" -wid 2 -clk nvdla_core_clk -rst nvdla_core_rstn "); +assign cacc2glb_done_intr_pd = cacc_done_intr; +///// generate credit signal +assign accu2sc_credit_size = 3'h1; +assign last_data = (data_left_mask=={1'b1,{(32*8)/(32*1)-1{1'b0}}}); +//: &eperl::flop(" -q accu2sc_credit_vld -d \"cacc2sdp_valid & cacc2sdp_ready & last_data\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +// spyglass enable_block NoWidthInBasedNum-ML +endmodule // NV_NVDLA_CACC_delivery_buffer diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v new file mode 100644 index 0000000..96afc97 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v @@ -0,0 +1,540 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_delivery_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_delivery_ctrl ( + nvdla_core_clk + ,nvdla_core_rstn + ,cacc2sdp_ready + ,cacc2sdp_valid + ,dbuf_rd_ready + ,dlv_data + ,dlv_mask + ,dlv_pd + ,dlv_valid + ,reg2dp_batches + ,reg2dp_conv_mode + ,reg2dp_dataout_addr + ,reg2dp_dataout_channel + ,reg2dp_dataout_height + ,reg2dp_dataout_width + ,reg2dp_line_packed + ,reg2dp_line_stride + ,reg2dp_op_en + ,reg2dp_proc_precision + ,reg2dp_surf_packed + ,reg2dp_surf_stride + ,wait_for_op_en + ,dbuf_rd_addr + ,dbuf_rd_en + ,dbuf_rd_layer_end + ,dbuf_wr_addr + ,dbuf_wr_data + ,dbuf_wr_en + ,dp2reg_done + ); +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_dataout_width; +input [12:0] reg2dp_dataout_height; +input [12:0] reg2dp_dataout_channel; +input [31-3:0] reg2dp_dataout_addr; +input [0:0] reg2dp_line_packed; +input [0:0] reg2dp_surf_packed; +input [4:0] reg2dp_batches; +input [23:0] reg2dp_line_stride; +input [23:0] reg2dp_surf_stride; +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc2sdp_ready; +input cacc2sdp_valid; +input dbuf_rd_ready; +input[32*8 -1:0] dlv_data; +input dlv_mask; +input [1:0] dlv_pd; +input dlv_valid; +input wait_for_op_en; +output [3 +1 -1:0] dbuf_rd_addr; +output dbuf_rd_en; +output dbuf_rd_layer_end; +output [3 +1 -1:0] dbuf_wr_addr; +output [32*8 -1:0] dbuf_wr_data; +output dbuf_wr_en; +output dp2reg_done; +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.1.6 +////////////////////////////////////////////////////////////// +///// parse input status signal ///// +////////////////////////////////////////////////////////////// +wire dlv_stripe_end = dlv_pd[0]; +wire dlv_layer_end = dlv_pd[1]; +////////////////////////////////////////////////////////////// +///// register input signal from regfile ///// +////////////////////////////////////////////////////////////// +wire [12 -6:0] cur_channel_w = {reg2dp_dataout_channel[12 -1:5]} ; +//: my $kk = 12 -5; +//: my $aw = 32-3; +//: &eperl::flop(" -q cur_op_en -en wait_for_op_en & \"reg2dp_op_en\" -d \"reg2dp_op_en\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cur_conv_mode -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_conv_mode\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 2 -q cur_proc_precision -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_proc_precision\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 13 -q cur_width -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_dataout_width\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 13 -q cur_height -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_dataout_height\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q cur_channel -en \"wait_for_op_en & reg2dp_op_en\" -d \"cur_channel_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid $aw -q cur_dataout_addr -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_dataout_addr\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 5 -q cur_batches -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_batches\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 24 -q cur_line_stride -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_line_stride\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 24 -q cur_surf_stride -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_surf_stride\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cur_line_packed -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_line_packed\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cur_surf_packed -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_surf_packed\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg cur_op_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_op_en <= 'b0; + end else begin + if ((wait_for_op_en) == 1'b1) begin + cur_op_en <= reg2dp_op_en; + // VCS coverage off + end else if ((wait_for_op_en) == 1'b0) begin + end else begin + cur_op_en <= 'bx; + // VCS coverage on + end + end +end +reg cur_conv_mode; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_conv_mode <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_conv_mode <= reg2dp_conv_mode; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_conv_mode <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] cur_proc_precision; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_proc_precision <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_proc_precision <= reg2dp_proc_precision; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_proc_precision <= 'bx; + // VCS coverage on + end + end +end +reg [12:0] cur_width; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_width <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_width <= reg2dp_dataout_width; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_width <= 'bx; + // VCS coverage on + end + end +end +reg [12:0] cur_height; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_height <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_height <= reg2dp_dataout_height; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_height <= 'bx; + // VCS coverage on + end + end +end +reg [6:0] cur_channel; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_channel <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_channel <= cur_channel_w; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_channel <= 'bx; + // VCS coverage on + end + end +end +reg [28:0] cur_dataout_addr; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_dataout_addr <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_dataout_addr <= reg2dp_dataout_addr; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_dataout_addr <= 'bx; + // VCS coverage on + end + end +end +reg [4:0] cur_batches; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_batches <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_batches <= reg2dp_batches; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_batches <= 'bx; + // VCS coverage on + end + end +end +reg [23:0] cur_line_stride; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_line_stride <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_line_stride <= reg2dp_line_stride; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_line_stride <= 'bx; + // VCS coverage on + end + end +end +reg [23:0] cur_surf_stride; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_surf_stride <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_surf_stride <= reg2dp_surf_stride; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_surf_stride <= 'bx; + // VCS coverage on + end + end +end +reg cur_line_packed; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_line_packed <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_line_packed <= reg2dp_line_packed; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_line_packed <= 'bx; + // VCS coverage on + end + end +end +reg cur_surf_packed; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_surf_packed <= 'b0; + end else begin + if ((wait_for_op_en & reg2dp_op_en) == 1'b1) begin + cur_surf_packed <= reg2dp_surf_packed; + // VCS coverage off + end else if ((wait_for_op_en & reg2dp_op_en) == 1'b0) begin + end else begin + cur_surf_packed <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// generate current status signals ///// +////////////////////////////////////////////////////////////// +wire is_int8_w = (reg2dp_proc_precision == 2'h0); +wire is_int8 = (cur_proc_precision == 2'h0); +wire is_winograd = 1'b0; +////////////////////////////////////////////////////////////// +///// generate write signal, 1 pipe for write data +////////////////////////////////////////////////////////////// +wire dbuf_wr_en_w = dlv_valid; +wire [32*8 -1:0] dbuf_wr_data_w = dlv_data; +reg [3 +1 -1:0] dbuf_wr_addr_pre; +reg [3 +1 -1:0] dbuf_wr_addr; +wire [3 +1 -1:0] dbuf_wr_addr_w; +wire mon_dbuf_wr_addr_w; +assign {mon_dbuf_wr_addr_w, dbuf_wr_addr_w} = dbuf_wr_addr_pre + 1'b1; +//: my $kk=32*8; +//: &eperl::flop("-nodeclare -q dbuf_wr_addr_pre -en \"dlv_valid\" -d \"dbuf_wr_addr_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dbuf_wr_addr -en \"dlv_valid\" -d \"dbuf_wr_addr_pre\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dbuf_wr_en -d \"dbuf_wr_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q dbuf_wr_data -en \"dbuf_wr_en_w\" -d \"dbuf_wr_data_w\" -clk nvdla_core_clk -rst nvdla_core_rstn"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_wr_addr_pre <= 'b0; + end else begin + if ((dlv_valid) == 1'b1) begin + dbuf_wr_addr_pre <= dbuf_wr_addr_w; + // VCS coverage off + end else if ((dlv_valid) == 1'b0) begin + end else begin + dbuf_wr_addr_pre <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_wr_addr <= 'b0; + end else begin + if ((dlv_valid) == 1'b1) begin + dbuf_wr_addr <= dbuf_wr_addr_pre; + // VCS coverage off + end else if ((dlv_valid) == 1'b0) begin + end else begin + dbuf_wr_addr <= 'bx; + // VCS coverage on + end + end +end +reg dbuf_wr_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_wr_en <= 'b0; + end else begin + dbuf_wr_en <= dbuf_wr_en_w; + end +end +reg [255:0] dbuf_wr_data; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_wr_data <= 'b0; + end else begin + if ((dbuf_wr_en_w) == 1'b1) begin + dbuf_wr_data <= dbuf_wr_data_w; + // VCS coverage off + end else if ((dbuf_wr_en_w) == 1'b0) begin + end else begin + dbuf_wr_data <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///// generate stored data size, add delay for write, due to ecc,could set 0 currently. +wire dlv_push_valid = dlv_valid; +wire dlv_push_size = 1'b1; +//: my $latency = 1; +//: print "wire dlv_push_valid_d0 = dlv_push_valid;\n"; +//: print "wire dlv_push_size_d0 = dlv_push_size;\n"; +//: +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q dlv_push_valid_d${j} -d \"dlv_push_valid_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_push_size_d${j} -en \"dlv_push_valid_d${i}\" -d \"dlv_push_size_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: } +//: +//: print "wire dlv_data_add_valid = dlv_push_valid_d${latency};\n"; +//: print "wire dlv_data_add_size = dlv_push_size_d${latency};\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire dlv_push_valid_d0 = dlv_push_valid; +wire dlv_push_size_d0 = dlv_push_size; +reg dlv_push_valid_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_push_valid_d1 <= 'b0; + end else begin + dlv_push_valid_d1 <= dlv_push_valid_d0; + end +end +reg dlv_push_size_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_push_size_d1 <= 'b0; + end else begin + if ((dlv_push_valid_d0) == 1'b1) begin + dlv_push_size_d1 <= dlv_push_size_d0; + // VCS coverage off + end else if ((dlv_push_valid_d0) == 1'b0) begin + end else begin + dlv_push_size_d1 <= 'bx; + // VCS coverage on + end + end +end +wire dlv_data_add_valid = dlv_push_valid_d1; +wire dlv_data_add_size = dlv_push_size_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//// dbuffer data counter +wire dlv_pop; +wire [8*2 -1:0] dlv_data_avl_w; +wire mon_dlv_data_avl_w; +reg [8*2 -1:0] dlv_data_avl; +wire dlv_data_avl_add = dlv_data_add_valid ? dlv_data_add_size : 1'h0; +wire dlv_data_avl_sub = dlv_pop ? 1'b1 : 1'b0; +wire dlv_data_sub_valid = dlv_pop; +assign {mon_dlv_data_avl_w,dlv_data_avl_w} = dlv_data_avl + dlv_data_avl_add - dlv_data_avl_sub; +//: my $kk=8*2; +//: &eperl::flop("-nodeclare -wid ${kk} -q dlv_data_avl -en \"dlv_data_add_valid | dlv_data_sub_valid\" -d \"dlv_data_avl_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_data_avl <= 'b0; + end else begin + if ((dlv_data_add_valid | dlv_data_sub_valid) == 1'b1) begin + dlv_data_avl <= dlv_data_avl_w; + // VCS coverage off + end else if ((dlv_data_add_valid | dlv_data_sub_valid) == 1'b0) begin + end else begin + dlv_data_avl <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///// generate dbuf read request +reg [3 +1 -1:0] dbuf_rd_addr_cnt; +wire [3 +1 -1:0] dbuf_rd_addr_cnt_inc; +wire mon_dbuf_rd_addr_cnt_inc; +assign dlv_pop = dbuf_rd_en & dbuf_rd_ready; +assign {mon_dbuf_rd_addr_cnt_inc,dbuf_rd_addr_cnt_inc} = dbuf_rd_addr_cnt + 1'b1; +wire dbuf_empty = ~(|dlv_data_avl); +assign dbuf_rd_en = ~dbuf_empty; +assign dbuf_rd_addr = dbuf_rd_addr_cnt; +//: &eperl::flop("-nodeclare -q dbuf_rd_addr_cnt -en \"dlv_pop\" -d \"dbuf_rd_addr_cnt_inc\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbuf_rd_addr_cnt <= 'b0; + end else begin + if ((dlv_pop) == 1'b1) begin + dbuf_rd_addr_cnt <= dbuf_rd_addr_cnt_inc; + // VCS coverage off + end else if ((dlv_pop) == 1'b0) begin + end else begin + dbuf_rd_addr_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////// generate dp2reg_done signal +wire dp2reg_done_w = dlv_valid & dlv_stripe_end & dlv_layer_end; +//: &eperl::flop(" -q dp2reg_done -d \"dp2reg_done_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg dp2reg_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_done <= 'b0; + end else begin + dp2reg_done <= dp2reg_done_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////// generate output package for sdp +reg [3 +1 -1:0] dlv_end_tag0_addr; +reg [3 +1 -1:0] dlv_end_tag1_addr; +reg dlv_end_tag0_vld; +reg dlv_end_tag1_vld; +wire dlv_end_set = dlv_valid & dlv_stripe_end & dlv_layer_end; +wire [3 +1 -1:0] dlv_end_addr_w = dbuf_wr_addr_pre; +wire dlv_end_clr = dlv_pop & (dbuf_rd_addr == dlv_end_tag0_addr) & dlv_end_tag0_vld; +wire dlv_end_tag0_vld_w = (dlv_end_tag1_vld | dlv_end_set) ? 1'b1 : dlv_end_clr ? 1'b0 : dlv_end_tag0_vld; +wire dlv_end_tag1_vld_w = (dlv_end_tag0_vld & dlv_end_set) ? 1'b1 : dlv_end_clr ? 1'b0 : dlv_end_tag1_vld; +wire dlv_end_tag0_en = (dlv_end_set & ~dlv_end_tag0_vld) | (dlv_end_set & dlv_end_clr) |(dlv_end_clr & dlv_end_tag1_vld); +wire dlv_end_tag1_en = (dlv_end_set & dlv_end_tag0_vld & ~dlv_end_clr); +wire [3 +1 -1:0] dlv_end_tag0_addr_w = dlv_end_tag1_vld ? dlv_end_tag1_addr : dlv_end_addr_w; +wire [3 +1 -1:0] dlv_end_tag1_addr_w = dlv_end_addr_w; +wire dbuf_rd_layer_end = dlv_end_clr; +//: &eperl::flop("-nodeclare -q dlv_end_tag0_vld -d \"dlv_end_tag0_vld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_end_tag1_vld -d \"dlv_end_tag1_vld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_end_tag0_addr -en \"dlv_end_tag0_en\" -d \"dlv_end_tag0_addr_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_end_tag1_addr -en \"dlv_end_tag1_en\" -d \"dlv_end_tag1_addr_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_end_tag0_vld <= 'b0; + end else begin + dlv_end_tag0_vld <= dlv_end_tag0_vld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_end_tag1_vld <= 'b0; + end else begin + dlv_end_tag1_vld <= dlv_end_tag1_vld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_end_tag0_addr <= 'b0; + end else begin + if ((dlv_end_tag0_en) == 1'b1) begin + dlv_end_tag0_addr <= dlv_end_tag0_addr_w; + // VCS coverage off + end else if ((dlv_end_tag0_en) == 1'b0) begin + end else begin + dlv_end_tag0_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dlv_end_tag1_addr <= 'b0; + end else begin + if ((dlv_end_tag1_en) == 1'b1) begin + dlv_end_tag1_addr <= dlv_end_tag1_addr_w; + // VCS coverage off + end else if ((dlv_end_tag1_en) == 1'b0) begin + end else begin + dlv_end_tag1_addr <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.1.6 +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v.vcp new file mode 100644 index 0000000..ce9bde8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v.vcp @@ -0,0 +1,183 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_delivery_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_CACC_delivery_ctrl ( + nvdla_core_clk + ,nvdla_core_rstn + ,cacc2sdp_ready + ,cacc2sdp_valid + ,dbuf_rd_ready + ,dlv_data + ,dlv_mask + ,dlv_pd + ,dlv_valid + ,reg2dp_batches + ,reg2dp_conv_mode + ,reg2dp_dataout_addr + ,reg2dp_dataout_channel + ,reg2dp_dataout_height + ,reg2dp_dataout_width + ,reg2dp_line_packed + ,reg2dp_line_stride + ,reg2dp_op_en + ,reg2dp_proc_precision + ,reg2dp_surf_packed + ,reg2dp_surf_stride + ,wait_for_op_en + ,dbuf_rd_addr + ,dbuf_rd_en + ,dbuf_rd_layer_end + ,dbuf_wr_addr + ,dbuf_wr_data + ,dbuf_wr_en + ,dp2reg_done + ); +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_dataout_width; +input [12:0] reg2dp_dataout_height; +input [12:0] reg2dp_dataout_channel; +input [31-3:0] reg2dp_dataout_addr; +input [0:0] reg2dp_line_packed; +input [0:0] reg2dp_surf_packed; +input [4:0] reg2dp_batches; +input [23:0] reg2dp_line_stride; +input [23:0] reg2dp_surf_stride; +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc2sdp_ready; +input cacc2sdp_valid; +input dbuf_rd_ready; +input[32*8 -1:0] dlv_data; +input dlv_mask; +input [1:0] dlv_pd; +input dlv_valid; +input wait_for_op_en; +output [3 +1 -1:0] dbuf_rd_addr; +output dbuf_rd_en; +output dbuf_rd_layer_end; +output [3 +1 -1:0] dbuf_wr_addr; +output [32*8 -1:0] dbuf_wr_data; +output dbuf_wr_en; +output dp2reg_done; +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.1.6 +////////////////////////////////////////////////////////////// +///// parse input status signal ///// +////////////////////////////////////////////////////////////// +wire dlv_stripe_end = dlv_pd[0]; +wire dlv_layer_end = dlv_pd[1]; +////////////////////////////////////////////////////////////// +///// register input signal from regfile ///// +////////////////////////////////////////////////////////////// +wire [12 -6:0] cur_channel_w = {reg2dp_dataout_channel[12 -1:5]} ; +//: my $kk = 12 -5; +//: my $aw = 32-3; +//: &eperl::flop(" -q cur_op_en -en wait_for_op_en & \"reg2dp_op_en\" -d \"reg2dp_op_en\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cur_conv_mode -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_conv_mode\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 2 -q cur_proc_precision -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_proc_precision\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 13 -q cur_width -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_dataout_width\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 13 -q cur_height -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_dataout_height\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q cur_channel -en \"wait_for_op_en & reg2dp_op_en\" -d \"cur_channel_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid $aw -q cur_dataout_addr -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_dataout_addr\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 5 -q cur_batches -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_batches\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 24 -q cur_line_stride -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_line_stride\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid 24 -q cur_surf_stride -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_surf_stride\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cur_line_packed -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_line_packed\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q cur_surf_packed -en \"wait_for_op_en & reg2dp_op_en\" -d \"reg2dp_surf_packed\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +////////////////////////////////////////////////////////////// +///// generate current status signals ///// +////////////////////////////////////////////////////////////// +wire is_int8_w = (reg2dp_proc_precision == 2'h0); +wire is_int8 = (cur_proc_precision == 2'h0); +wire is_winograd = 1'b0; +////////////////////////////////////////////////////////////// +///// generate write signal, 1 pipe for write data +////////////////////////////////////////////////////////////// +wire dbuf_wr_en_w = dlv_valid; +wire [32*8 -1:0] dbuf_wr_data_w = dlv_data; +reg [3 +1 -1:0] dbuf_wr_addr_pre; +reg [3 +1 -1:0] dbuf_wr_addr; +wire [3 +1 -1:0] dbuf_wr_addr_w; +wire mon_dbuf_wr_addr_w; +assign {mon_dbuf_wr_addr_w, dbuf_wr_addr_w} = dbuf_wr_addr_pre + 1'b1; +//: my $kk=32*8; +//: &eperl::flop("-nodeclare -q dbuf_wr_addr_pre -en \"dlv_valid\" -d \"dbuf_wr_addr_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dbuf_wr_addr -en \"dlv_valid\" -d \"dbuf_wr_addr_pre\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dbuf_wr_en -d \"dbuf_wr_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-wid ${kk} -q dbuf_wr_data -en \"dbuf_wr_en_w\" -d \"dbuf_wr_data_w\" -clk nvdla_core_clk -rst nvdla_core_rstn"); +///// generate stored data size, add delay for write, due to ecc,could set 0 currently. +wire dlv_push_valid = dlv_valid; +wire dlv_push_size = 1'b1; +//: my $latency = 1; +//: print "wire dlv_push_valid_d0 = dlv_push_valid;\n"; +//: print "wire dlv_push_size_d0 = dlv_push_size;\n"; +//: +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q dlv_push_valid_d${j} -d \"dlv_push_valid_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop(" -q dlv_push_size_d${j} -en \"dlv_push_valid_d${i}\" -d \"dlv_push_size_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: } +//: +//: print "wire dlv_data_add_valid = dlv_push_valid_d${latency};\n"; +//: print "wire dlv_data_add_size = dlv_push_size_d${latency};\n"; +//// dbuffer data counter +wire dlv_pop; +wire [8*2 -1:0] dlv_data_avl_w; +wire mon_dlv_data_avl_w; +reg [8*2 -1:0] dlv_data_avl; +wire dlv_data_avl_add = dlv_data_add_valid ? dlv_data_add_size : 1'h0; +wire dlv_data_avl_sub = dlv_pop ? 1'b1 : 1'b0; +wire dlv_data_sub_valid = dlv_pop; +assign {mon_dlv_data_avl_w,dlv_data_avl_w} = dlv_data_avl + dlv_data_avl_add - dlv_data_avl_sub; +//: my $kk=8*2; +//: &eperl::flop("-nodeclare -wid ${kk} -q dlv_data_avl -en \"dlv_data_add_valid | dlv_data_sub_valid\" -d \"dlv_data_avl_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +///// generate dbuf read request +reg [3 +1 -1:0] dbuf_rd_addr_cnt; +wire [3 +1 -1:0] dbuf_rd_addr_cnt_inc; +wire mon_dbuf_rd_addr_cnt_inc; +assign dlv_pop = dbuf_rd_en & dbuf_rd_ready; +assign {mon_dbuf_rd_addr_cnt_inc,dbuf_rd_addr_cnt_inc} = dbuf_rd_addr_cnt + 1'b1; +wire dbuf_empty = ~(|dlv_data_avl); +assign dbuf_rd_en = ~dbuf_empty; +assign dbuf_rd_addr = dbuf_rd_addr_cnt; +//: &eperl::flop("-nodeclare -q dbuf_rd_addr_cnt -en \"dlv_pop\" -d \"dbuf_rd_addr_cnt_inc\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +/////// generate dp2reg_done signal +wire dp2reg_done_w = dlv_valid & dlv_stripe_end & dlv_layer_end; +//: &eperl::flop(" -q dp2reg_done -d \"dp2reg_done_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +/////// generate output package for sdp +reg [3 +1 -1:0] dlv_end_tag0_addr; +reg [3 +1 -1:0] dlv_end_tag1_addr; +reg dlv_end_tag0_vld; +reg dlv_end_tag1_vld; +wire dlv_end_set = dlv_valid & dlv_stripe_end & dlv_layer_end; +wire [3 +1 -1:0] dlv_end_addr_w = dbuf_wr_addr_pre; +wire dlv_end_clr = dlv_pop & (dbuf_rd_addr == dlv_end_tag0_addr) & dlv_end_tag0_vld; +wire dlv_end_tag0_vld_w = (dlv_end_tag1_vld | dlv_end_set) ? 1'b1 : dlv_end_clr ? 1'b0 : dlv_end_tag0_vld; +wire dlv_end_tag1_vld_w = (dlv_end_tag0_vld & dlv_end_set) ? 1'b1 : dlv_end_clr ? 1'b0 : dlv_end_tag1_vld; +wire dlv_end_tag0_en = (dlv_end_set & ~dlv_end_tag0_vld) | (dlv_end_set & dlv_end_clr) |(dlv_end_clr & dlv_end_tag1_vld); +wire dlv_end_tag1_en = (dlv_end_set & dlv_end_tag0_vld & ~dlv_end_clr); +wire [3 +1 -1:0] dlv_end_tag0_addr_w = dlv_end_tag1_vld ? dlv_end_tag1_addr : dlv_end_addr_w; +wire [3 +1 -1:0] dlv_end_tag1_addr_w = dlv_end_addr_w; +wire dbuf_rd_layer_end = dlv_end_clr; +//: &eperl::flop("-nodeclare -q dlv_end_tag0_vld -d \"dlv_end_tag0_vld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_end_tag1_vld -d \"dlv_end_tag1_vld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_end_tag0_addr -en \"dlv_end_tag0_en\" -d \"dlv_end_tag0_addr_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +//: &eperl::flop("-nodeclare -q dlv_end_tag1_addr -en \"dlv_end_tag1_en\" -d \"dlv_end_tag1_addr_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -rval 0"); +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.1.6 +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v new file mode 100644 index 0000000..cab416d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v @@ -0,0 +1,297 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_dual_reg.v +module NV_NVDLA_CACC_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,batches + ,clip_truncate + ,cya + ,dataout_addr + ,line_packed + ,surf_packed + ,dataout_height + ,dataout_width + ,dataout_channel + ,line_stride + ,conv_mode + ,proc_precision + ,op_en_trigger + ,surf_stride + ,op_en + ,sat_count + ); +wire [31:0] nvdla_cacc_d_batch_number_0_out; +wire [31:0] nvdla_cacc_d_clip_cfg_0_out; +wire [31:0] nvdla_cacc_d_cya_0_out; +wire [31:0] nvdla_cacc_d_dataout_addr_0_out; +wire [31:0] nvdla_cacc_d_dataout_map_0_out; +wire [31:0] nvdla_cacc_d_dataout_size_0_0_out; +wire [31:0] nvdla_cacc_d_dataout_size_1_0_out; +wire [31:0] nvdla_cacc_d_line_stride_0_out; +wire [31:0] nvdla_cacc_d_misc_cfg_0_out; +wire [31:0] nvdla_cacc_d_op_enable_0_out; +wire [31:0] nvdla_cacc_d_out_saturation_0_out; +wire [31:0] nvdla_cacc_d_surf_stride_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [4:0] batches; +output [4:0] clip_truncate; +output [31:0] cya; +output [31:0] dataout_addr; +output line_packed; +output surf_packed; +output [12:0] dataout_height; +output [12:0] dataout_width; +output [12:0] dataout_channel; +output [23:0] line_stride; +output conv_mode; +output [1:0] proc_precision; +output op_en_trigger; +output [23:0] surf_stride; +// Read-only register inputs +input op_en; +input [31:0] sat_count; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [4:0] batches; +reg [4:0] clip_truncate; +reg conv_mode; +reg [31:0] cya; +reg [31:0] dataout_addr; +reg [12:0] dataout_channel; +reg [12:0] dataout_height; +reg [12:0] dataout_width; +reg line_packed; +reg [23:0] line_stride; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg surf_packed; +reg [23:0] surf_stride; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cacc_d_batch_number_0_wren = (reg_offset_wr == (32'h901c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_clip_cfg_0_wren = (reg_offset_wr == (32'h902c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_cya_0_wren = (reg_offset_wr == (32'h9034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_addr_0_wren = (reg_offset_wr == (32'h9018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_map_0_wren = (reg_offset_wr == (32'h9028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_size_0_0_wren = (reg_offset_wr == (32'h9010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_size_1_0_wren = (reg_offset_wr == (32'h9014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_line_stride_0_wren = (reg_offset_wr == (32'h9020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_misc_cfg_0_wren = (reg_offset_wr == (32'h900c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_op_enable_0_wren = (reg_offset_wr == (32'h9008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_out_saturation_0_wren = (reg_offset_wr == (32'h9030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_surf_stride_0_wren = (reg_offset_wr == (32'h9024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cacc_d_batch_number_0_out[31:0] = { 27'b0, batches }; +assign nvdla_cacc_d_clip_cfg_0_out[31:0] = { 27'b0, clip_truncate }; +assign nvdla_cacc_d_cya_0_out[31:0] = { cya }; +assign nvdla_cacc_d_dataout_addr_0_out[31:0] = { dataout_addr}; +assign nvdla_cacc_d_dataout_map_0_out[31:0] = { 15'b0, surf_packed, 15'b0, line_packed }; +assign nvdla_cacc_d_dataout_size_0_0_out[31:0] = { 3'b0, dataout_height, 3'b0, dataout_width }; +assign nvdla_cacc_d_dataout_size_1_0_out[31:0] = { 19'b0, dataout_channel }; +assign nvdla_cacc_d_line_stride_0_out[31:0] = { 8'b0, line_stride}; +assign nvdla_cacc_d_misc_cfg_0_out[31:0] = { 18'b0, proc_precision, 11'b0, conv_mode }; +assign nvdla_cacc_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cacc_d_out_saturation_0_out[31:0] = { sat_count }; +assign nvdla_cacc_d_surf_stride_0_out[31:0] = { 8'b0, surf_stride}; +assign op_en_trigger = nvdla_cacc_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cacc_d_batch_number_0_out + or nvdla_cacc_d_clip_cfg_0_out + or nvdla_cacc_d_cya_0_out + or nvdla_cacc_d_dataout_addr_0_out + or nvdla_cacc_d_dataout_map_0_out + or nvdla_cacc_d_dataout_size_0_0_out + or nvdla_cacc_d_dataout_size_1_0_out + or nvdla_cacc_d_line_stride_0_out + or nvdla_cacc_d_misc_cfg_0_out + or nvdla_cacc_d_op_enable_0_out + or nvdla_cacc_d_out_saturation_0_out + or nvdla_cacc_d_surf_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'h901c & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_batch_number_0_out ; + end + (32'h902c & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_clip_cfg_0_out ; + end + (32'h9034 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_cya_0_out ; + end + (32'h9018 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_addr_0_out ; + end + (32'h9028 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_map_0_out ; + end + (32'h9010 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_size_0_0_out ; + end + (32'h9014 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_size_1_0_out ; + end + (32'h9020 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_line_stride_0_out ; + end + (32'h900c & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_misc_cfg_0_out ; + end + (32'h9008 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_op_enable_0_out ; + end + (32'h9030 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_out_saturation_0_out ; + end + (32'h9024 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_surf_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + batches[4:0] <= 5'b00000; + clip_truncate[4:0] <= 5'b00000; + cya[31:0] <= 32'b00000000000000000000000000000000; + dataout_addr[31:0] <= 32'h0; + line_packed <= 1'b0; + surf_packed <= 1'b0; + dataout_height[12:0] <= 13'b0000000000000; + dataout_width[12:0] <= 13'b0000000000000; + dataout_channel[12:0] <= 13'b0000000000000; + line_stride[23:0] <= 24'b000000000000000000000000; + conv_mode <= 1'b0; + proc_precision[1:0] <= 2'b01; + surf_stride[23:0] <= 24'b000000000000000000000000; + end else begin +// Register: NVDLA_CACC_D_BATCH_NUMBER_0 Field: batches + if (nvdla_cacc_d_batch_number_0_wren) begin + batches[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CACC_D_CLIP_CFG_0 Field: clip_truncate + if (nvdla_cacc_d_clip_cfg_0_wren) begin + clip_truncate[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CACC_D_CYA_0 Field: cya + if (nvdla_cacc_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CACC_D_DATAOUT_ADDR_0 Field: dataout_addr + if (nvdla_cacc_d_dataout_addr_0_wren) begin + dataout_addr[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CACC_D_DATAOUT_MAP_0 Field: line_packed + if (nvdla_cacc_d_dataout_map_0_wren) begin + line_packed <= reg_wr_data[0]; + end +// Register: NVDLA_CACC_D_DATAOUT_MAP_0 Field: surf_packed + if (nvdla_cacc_d_dataout_map_0_wren) begin + surf_packed <= reg_wr_data[16]; + end +// Register: NVDLA_CACC_D_DATAOUT_SIZE_0_0 Field: dataout_height + if (nvdla_cacc_d_dataout_size_0_0_wren) begin + dataout_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CACC_D_DATAOUT_SIZE_0_0 Field: dataout_width + if (nvdla_cacc_d_dataout_size_0_0_wren) begin + dataout_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CACC_D_DATAOUT_SIZE_1_0 Field: dataout_channel + if (nvdla_cacc_d_dataout_size_1_0_wren) begin + dataout_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CACC_D_LINE_STRIDE_0 Field: line_stride + if (nvdla_cacc_d_line_stride_0_wren) begin + line_stride[23:0] <= reg_wr_data[23:0]; + end +// Register: NVDLA_CACC_D_MISC_CFG_0 Field: conv_mode + if (nvdla_cacc_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CACC_D_MISC_CFG_0 Field: proc_precision + if (nvdla_cacc_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Not generating flops for field NVDLA_CACC_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_CACC_D_OUT_SATURATION_0::sat_count +// Register: NVDLA_CACC_D_SURF_STRIDE_0 Field: surf_stride + if (nvdla_cacc_d_surf_stride_0_wren) begin + surf_stride[23:0] <= reg_wr_data[23:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h901c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_BATCH_NUMBER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_batch_number_0_out, nvdla_cacc_d_batch_number_0_out); + (32'h902c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_CLIP_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_clip_cfg_0_out, nvdla_cacc_d_clip_cfg_0_out); + (32'h9034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_cya_0_out, nvdla_cacc_d_cya_0_out); + (32'h9018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_ADDR_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_addr_0_out, nvdla_cacc_d_dataout_addr_0_out); + (32'h9028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_MAP_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_map_0_out, nvdla_cacc_d_dataout_map_0_out); + (32'h9010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_size_0_0_out, nvdla_cacc_d_dataout_size_0_0_out); + (32'h9014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_size_1_0_out, nvdla_cacc_d_dataout_size_1_0_out); + (32'h9020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_line_stride_0_out, nvdla_cacc_d_line_stride_0_out); + (32'h900c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_misc_cfg_0_out, nvdla_cacc_d_misc_cfg_0_out); + (32'h9008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_op_enable_0_out, nvdla_cacc_d_op_enable_0_out); + (32'h9030 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CACC_D_OUT_SATURATION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h9024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_surf_stride_0_out, nvdla_cacc_d_surf_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CACC_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v.vcp new file mode 100644 index 0000000..cab416d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v.vcp @@ -0,0 +1,297 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_dual_reg.v +module NV_NVDLA_CACC_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,batches + ,clip_truncate + ,cya + ,dataout_addr + ,line_packed + ,surf_packed + ,dataout_height + ,dataout_width + ,dataout_channel + ,line_stride + ,conv_mode + ,proc_precision + ,op_en_trigger + ,surf_stride + ,op_en + ,sat_count + ); +wire [31:0] nvdla_cacc_d_batch_number_0_out; +wire [31:0] nvdla_cacc_d_clip_cfg_0_out; +wire [31:0] nvdla_cacc_d_cya_0_out; +wire [31:0] nvdla_cacc_d_dataout_addr_0_out; +wire [31:0] nvdla_cacc_d_dataout_map_0_out; +wire [31:0] nvdla_cacc_d_dataout_size_0_0_out; +wire [31:0] nvdla_cacc_d_dataout_size_1_0_out; +wire [31:0] nvdla_cacc_d_line_stride_0_out; +wire [31:0] nvdla_cacc_d_misc_cfg_0_out; +wire [31:0] nvdla_cacc_d_op_enable_0_out; +wire [31:0] nvdla_cacc_d_out_saturation_0_out; +wire [31:0] nvdla_cacc_d_surf_stride_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [4:0] batches; +output [4:0] clip_truncate; +output [31:0] cya; +output [31:0] dataout_addr; +output line_packed; +output surf_packed; +output [12:0] dataout_height; +output [12:0] dataout_width; +output [12:0] dataout_channel; +output [23:0] line_stride; +output conv_mode; +output [1:0] proc_precision; +output op_en_trigger; +output [23:0] surf_stride; +// Read-only register inputs +input op_en; +input [31:0] sat_count; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [4:0] batches; +reg [4:0] clip_truncate; +reg conv_mode; +reg [31:0] cya; +reg [31:0] dataout_addr; +reg [12:0] dataout_channel; +reg [12:0] dataout_height; +reg [12:0] dataout_width; +reg line_packed; +reg [23:0] line_stride; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg surf_packed; +reg [23:0] surf_stride; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cacc_d_batch_number_0_wren = (reg_offset_wr == (32'h901c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_clip_cfg_0_wren = (reg_offset_wr == (32'h902c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_cya_0_wren = (reg_offset_wr == (32'h9034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_addr_0_wren = (reg_offset_wr == (32'h9018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_map_0_wren = (reg_offset_wr == (32'h9028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_size_0_0_wren = (reg_offset_wr == (32'h9010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_dataout_size_1_0_wren = (reg_offset_wr == (32'h9014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_line_stride_0_wren = (reg_offset_wr == (32'h9020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_misc_cfg_0_wren = (reg_offset_wr == (32'h900c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_op_enable_0_wren = (reg_offset_wr == (32'h9008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_out_saturation_0_wren = (reg_offset_wr == (32'h9030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_d_surf_stride_0_wren = (reg_offset_wr == (32'h9024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cacc_d_batch_number_0_out[31:0] = { 27'b0, batches }; +assign nvdla_cacc_d_clip_cfg_0_out[31:0] = { 27'b0, clip_truncate }; +assign nvdla_cacc_d_cya_0_out[31:0] = { cya }; +assign nvdla_cacc_d_dataout_addr_0_out[31:0] = { dataout_addr}; +assign nvdla_cacc_d_dataout_map_0_out[31:0] = { 15'b0, surf_packed, 15'b0, line_packed }; +assign nvdla_cacc_d_dataout_size_0_0_out[31:0] = { 3'b0, dataout_height, 3'b0, dataout_width }; +assign nvdla_cacc_d_dataout_size_1_0_out[31:0] = { 19'b0, dataout_channel }; +assign nvdla_cacc_d_line_stride_0_out[31:0] = { 8'b0, line_stride}; +assign nvdla_cacc_d_misc_cfg_0_out[31:0] = { 18'b0, proc_precision, 11'b0, conv_mode }; +assign nvdla_cacc_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cacc_d_out_saturation_0_out[31:0] = { sat_count }; +assign nvdla_cacc_d_surf_stride_0_out[31:0] = { 8'b0, surf_stride}; +assign op_en_trigger = nvdla_cacc_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cacc_d_batch_number_0_out + or nvdla_cacc_d_clip_cfg_0_out + or nvdla_cacc_d_cya_0_out + or nvdla_cacc_d_dataout_addr_0_out + or nvdla_cacc_d_dataout_map_0_out + or nvdla_cacc_d_dataout_size_0_0_out + or nvdla_cacc_d_dataout_size_1_0_out + or nvdla_cacc_d_line_stride_0_out + or nvdla_cacc_d_misc_cfg_0_out + or nvdla_cacc_d_op_enable_0_out + or nvdla_cacc_d_out_saturation_0_out + or nvdla_cacc_d_surf_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'h901c & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_batch_number_0_out ; + end + (32'h902c & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_clip_cfg_0_out ; + end + (32'h9034 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_cya_0_out ; + end + (32'h9018 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_addr_0_out ; + end + (32'h9028 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_map_0_out ; + end + (32'h9010 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_size_0_0_out ; + end + (32'h9014 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_dataout_size_1_0_out ; + end + (32'h9020 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_line_stride_0_out ; + end + (32'h900c & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_misc_cfg_0_out ; + end + (32'h9008 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_op_enable_0_out ; + end + (32'h9030 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_out_saturation_0_out ; + end + (32'h9024 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_d_surf_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + batches[4:0] <= 5'b00000; + clip_truncate[4:0] <= 5'b00000; + cya[31:0] <= 32'b00000000000000000000000000000000; + dataout_addr[31:0] <= 32'h0; + line_packed <= 1'b0; + surf_packed <= 1'b0; + dataout_height[12:0] <= 13'b0000000000000; + dataout_width[12:0] <= 13'b0000000000000; + dataout_channel[12:0] <= 13'b0000000000000; + line_stride[23:0] <= 24'b000000000000000000000000; + conv_mode <= 1'b0; + proc_precision[1:0] <= 2'b01; + surf_stride[23:0] <= 24'b000000000000000000000000; + end else begin +// Register: NVDLA_CACC_D_BATCH_NUMBER_0 Field: batches + if (nvdla_cacc_d_batch_number_0_wren) begin + batches[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CACC_D_CLIP_CFG_0 Field: clip_truncate + if (nvdla_cacc_d_clip_cfg_0_wren) begin + clip_truncate[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CACC_D_CYA_0 Field: cya + if (nvdla_cacc_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CACC_D_DATAOUT_ADDR_0 Field: dataout_addr + if (nvdla_cacc_d_dataout_addr_0_wren) begin + dataout_addr[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CACC_D_DATAOUT_MAP_0 Field: line_packed + if (nvdla_cacc_d_dataout_map_0_wren) begin + line_packed <= reg_wr_data[0]; + end +// Register: NVDLA_CACC_D_DATAOUT_MAP_0 Field: surf_packed + if (nvdla_cacc_d_dataout_map_0_wren) begin + surf_packed <= reg_wr_data[16]; + end +// Register: NVDLA_CACC_D_DATAOUT_SIZE_0_0 Field: dataout_height + if (nvdla_cacc_d_dataout_size_0_0_wren) begin + dataout_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CACC_D_DATAOUT_SIZE_0_0 Field: dataout_width + if (nvdla_cacc_d_dataout_size_0_0_wren) begin + dataout_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CACC_D_DATAOUT_SIZE_1_0 Field: dataout_channel + if (nvdla_cacc_d_dataout_size_1_0_wren) begin + dataout_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CACC_D_LINE_STRIDE_0 Field: line_stride + if (nvdla_cacc_d_line_stride_0_wren) begin + line_stride[23:0] <= reg_wr_data[23:0]; + end +// Register: NVDLA_CACC_D_MISC_CFG_0 Field: conv_mode + if (nvdla_cacc_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CACC_D_MISC_CFG_0 Field: proc_precision + if (nvdla_cacc_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Not generating flops for field NVDLA_CACC_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_CACC_D_OUT_SATURATION_0::sat_count +// Register: NVDLA_CACC_D_SURF_STRIDE_0 Field: surf_stride + if (nvdla_cacc_d_surf_stride_0_wren) begin + surf_stride[23:0] <= reg_wr_data[23:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h901c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_BATCH_NUMBER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_batch_number_0_out, nvdla_cacc_d_batch_number_0_out); + (32'h902c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_CLIP_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_clip_cfg_0_out, nvdla_cacc_d_clip_cfg_0_out); + (32'h9034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_cya_0_out, nvdla_cacc_d_cya_0_out); + (32'h9018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_ADDR_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_addr_0_out, nvdla_cacc_d_dataout_addr_0_out); + (32'h9028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_MAP_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_map_0_out, nvdla_cacc_d_dataout_map_0_out); + (32'h9010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_size_0_0_out, nvdla_cacc_d_dataout_size_0_0_out); + (32'h9014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_DATAOUT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_dataout_size_1_0_out, nvdla_cacc_d_dataout_size_1_0_out); + (32'h9020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_line_stride_0_out, nvdla_cacc_d_line_stride_0_out); + (32'h900c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_misc_cfg_0_out, nvdla_cacc_d_misc_cfg_0_out); + (32'h9008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_op_enable_0_out, nvdla_cacc_d_op_enable_0_out); + (32'h9030 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CACC_D_OUT_SATURATION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h9024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_D_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_d_surf_stride_0_out, nvdla_cacc_d_surf_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CACC_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v new file mode 100644 index 0000000..6380adc --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v @@ -0,0 +1,897 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CACC_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cacc_req_pd //|< i + ,csb2cacc_req_pvld //|< i + ,dp2reg_done //|< i + ,dp2reg_sat_count //|< i + ,cacc2csb_resp_pd //|> o + ,cacc2csb_resp_valid //|> o + ,csb2cacc_req_prdy //|> o + ,reg2dp_batches //|> o + ,reg2dp_clip_truncate //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_cya //|> o + ,reg2dp_dataout_addr //|> o + ,reg2dp_dataout_channel //|> o + ,reg2dp_dataout_height //|> o + ,reg2dp_dataout_width //|> o + ,reg2dp_line_packed //|> o + ,reg2dp_line_stride //|> o + ,reg2dp_op_en //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_surf_packed //|> o + ,reg2dp_surf_stride //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cacc_req_pd; +input csb2cacc_req_pvld; +input dp2reg_done; +input [31:0] dp2reg_sat_count; +output [33:0] cacc2csb_resp_pd; +output cacc2csb_resp_valid; +output csb2cacc_req_prdy; +output [4:0] reg2dp_batches; +output [4:0] reg2dp_clip_truncate; +output reg2dp_conv_mode; +output [31:0] reg2dp_cya; +output [31:0] reg2dp_dataout_addr; +output [12:0] reg2dp_dataout_channel; +output [12:0] reg2dp_dataout_height; +output [12:0] reg2dp_dataout_width; +output reg2dp_line_packed; +output [23:0] reg2dp_line_stride; +output reg2dp_op_en; +output [1:0] reg2dp_proc_precision; +output reg2dp_surf_packed; +output [23:0] reg2dp_surf_stride; +output [6:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [4:0] reg2dp_d0_batches; +wire [4:0] reg2dp_d0_clip_truncate; +wire reg2dp_d0_conv_mode; +wire [31:0] reg2dp_d0_cya; +wire [31:0] reg2dp_d0_dataout_addr; +wire [12:0] reg2dp_d0_dataout_channel; +wire [12:0] reg2dp_d0_dataout_height; +wire [12:0] reg2dp_d0_dataout_width; +wire reg2dp_d0_line_packed; +wire [23:0] reg2dp_d0_line_stride; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_proc_precision; +wire reg2dp_d0_surf_packed; +wire [23:0] reg2dp_d0_surf_stride; +wire [4:0] reg2dp_d1_batches; +wire [4:0] reg2dp_d1_clip_truncate; +wire reg2dp_d1_conv_mode; +wire [31:0] reg2dp_d1_cya; +wire [31:0] reg2dp_d1_dataout_addr; +wire [12:0] reg2dp_d1_dataout_channel; +wire [12:0] reg2dp_d1_dataout_height; +wire [12:0] reg2dp_d1_dataout_width; +wire reg2dp_d1_line_packed; +wire [23:0] reg2dp_d1_line_stride; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_proc_precision; +wire reg2dp_d1_surf_packed; +wire [23:0] reg2dp_d1_surf_stride; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [6:0] slcg_op_en_d0; +reg [33:0] cacc2csb_resp_pd; +reg cacc2csb_resp_valid; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg dp2reg_d0_reg; +reg [31:0] dp2reg_d0_sat_count; +reg [31:0] dp2reg_d0_sat_count_w; +reg dp2reg_d0_set; +reg dp2reg_d1_clr; +reg dp2reg_d1_reg; +reg [31:0] dp2reg_d1_sat_count; +reg [31:0] dp2reg_d1_sat_count_w; +reg dp2reg_d1_set; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [4:0] reg2dp_batches; +reg [4:0] reg2dp_clip_truncate; +reg reg2dp_conv_mode; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [31:0] reg2dp_dataout_addr; +reg [12:0] reg2dp_dataout_channel; +reg [12:0] reg2dp_dataout_height; +reg [12:0] reg2dp_dataout_width; +reg reg2dp_line_packed; +reg [23:0] reg2dp_line_stride; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_proc_precision; +reg reg2dp_surf_packed; +reg [23:0] reg2dp_surf_stride; +reg [62:0] req_pd; +reg req_pvld; +reg [6:0] slcg_op_en_d1; +reg [6:0] slcg_op_en_d2; +reg [6:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CACC_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CACC_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.batches (reg2dp_d0_batches[4:0]) //|> w + ,.clip_truncate (reg2dp_d0_clip_truncate[4:0]) //|> w + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.dataout_addr (reg2dp_d0_dataout_addr[31:0]) //|> w + ,.line_packed (reg2dp_d0_line_packed) //|> w + ,.surf_packed (reg2dp_d0_surf_packed) //|> w + ,.dataout_height (reg2dp_d0_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d0_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d0_dataout_channel[12:0]) //|> w + ,.line_stride (reg2dp_d0_line_stride[23:0]) //|> w + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.surf_stride (reg2dp_d0_surf_stride[23:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.sat_count (dp2reg_d0_sat_count[31:0]) //|< r + ); +NV_NVDLA_CACC_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.batches (reg2dp_d1_batches[4:0]) //|> w + ,.clip_truncate (reg2dp_d1_clip_truncate[4:0]) //|> w + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.dataout_addr (reg2dp_d1_dataout_addr[31:0]) //|> w + ,.line_packed (reg2dp_d1_line_packed) //|> w + ,.surf_packed (reg2dp_d1_surf_packed) //|> w + ,.dataout_height (reg2dp_d1_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d1_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d1_dataout_channel[12:0]) //|> w + ,.line_stride (reg2dp_d1_line_stride[23:0]) //|> w + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.surf_stride (reg2dp_d1_surf_stride[23:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.sat_count (dp2reg_d1_sat_count[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {7{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {7{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {7{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {7{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h9008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h9008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h9008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cacc_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cacc_req_pvld) == 1'b1) begin + req_pd <= csb2cacc_req_pd; +// VCS coverage off + end else if ((csb2cacc_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cacc_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cacc_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cacc2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cacc2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid <= 1'b0; + end else begin + cacc2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_batches + or reg2dp_d0_batches + ) begin + reg2dp_batches = dp2reg_consumer ? reg2dp_d1_batches : reg2dp_d0_batches; +end +always @( + dp2reg_consumer + or reg2dp_d1_clip_truncate + or reg2dp_d0_clip_truncate + ) begin + reg2dp_clip_truncate = dp2reg_consumer ? reg2dp_d1_clip_truncate : reg2dp_d0_clip_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_addr + or reg2dp_d0_dataout_addr + ) begin + reg2dp_dataout_addr = dp2reg_consumer ? reg2dp_d1_dataout_addr : reg2dp_d0_dataout_addr; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_packed + or reg2dp_d0_line_packed + ) begin + reg2dp_line_packed = dp2reg_consumer ? reg2dp_d1_line_packed : reg2dp_d0_line_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_packed + or reg2dp_d0_surf_packed + ) begin + reg2dp_surf_packed = dp2reg_consumer ? reg2dp_d1_surf_packed : reg2dp_d0_surf_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_height + or reg2dp_d0_dataout_height + ) begin + reg2dp_dataout_height = dp2reg_consumer ? reg2dp_d1_dataout_height : reg2dp_d0_dataout_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_width + or reg2dp_d0_dataout_width + ) begin + reg2dp_dataout_width = dp2reg_consumer ? reg2dp_d1_dataout_width : reg2dp_d0_dataout_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_channel + or reg2dp_d0_dataout_channel + ) begin + reg2dp_dataout_channel = dp2reg_consumer ? reg2dp_d1_dataout_channel : reg2dp_d0_dataout_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_stride + or reg2dp_d0_line_stride + ) begin + reg2dp_line_stride = dp2reg_consumer ? reg2dp_d1_line_stride : reg2dp_d0_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_stride + or reg2dp_d0_surf_stride + ) begin + reg2dp_surf_stride = dp2reg_consumer ? reg2dp_d1_surf_stride : reg2dp_d0_surf_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// for general counting register // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////////////////////////////////////////////////////////////////////// +// for output saturation register // +//////////////////////////////////////////////////////////////////////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_sat_count + or dp2reg_d0_clr + or dp2reg_d0_sat_count + ) begin + dp2reg_d0_sat_count_w = (dp2reg_d0_set) ? dp2reg_sat_count : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_sat_count; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_sat_count <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_sat_count <= dp2reg_d0_sat_count_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_sat_count <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_sat_count + or dp2reg_d1_clr + or dp2reg_d1_sat_count + ) begin + dp2reg_d1_sat_count_w = (dp2reg_d1_set) ? dp2reg_sat_count : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_sat_count; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_sat_count <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_sat_count <= dp2reg_d1_sat_count_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_sat_count <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CACC_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v.vcp new file mode 100644 index 0000000..6380adc --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v.vcp @@ -0,0 +1,897 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CACC_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cacc_req_pd //|< i + ,csb2cacc_req_pvld //|< i + ,dp2reg_done //|< i + ,dp2reg_sat_count //|< i + ,cacc2csb_resp_pd //|> o + ,cacc2csb_resp_valid //|> o + ,csb2cacc_req_prdy //|> o + ,reg2dp_batches //|> o + ,reg2dp_clip_truncate //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_cya //|> o + ,reg2dp_dataout_addr //|> o + ,reg2dp_dataout_channel //|> o + ,reg2dp_dataout_height //|> o + ,reg2dp_dataout_width //|> o + ,reg2dp_line_packed //|> o + ,reg2dp_line_stride //|> o + ,reg2dp_op_en //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_surf_packed //|> o + ,reg2dp_surf_stride //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cacc_req_pd; +input csb2cacc_req_pvld; +input dp2reg_done; +input [31:0] dp2reg_sat_count; +output [33:0] cacc2csb_resp_pd; +output cacc2csb_resp_valid; +output csb2cacc_req_prdy; +output [4:0] reg2dp_batches; +output [4:0] reg2dp_clip_truncate; +output reg2dp_conv_mode; +output [31:0] reg2dp_cya; +output [31:0] reg2dp_dataout_addr; +output [12:0] reg2dp_dataout_channel; +output [12:0] reg2dp_dataout_height; +output [12:0] reg2dp_dataout_width; +output reg2dp_line_packed; +output [23:0] reg2dp_line_stride; +output reg2dp_op_en; +output [1:0] reg2dp_proc_precision; +output reg2dp_surf_packed; +output [23:0] reg2dp_surf_stride; +output [6:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [4:0] reg2dp_d0_batches; +wire [4:0] reg2dp_d0_clip_truncate; +wire reg2dp_d0_conv_mode; +wire [31:0] reg2dp_d0_cya; +wire [31:0] reg2dp_d0_dataout_addr; +wire [12:0] reg2dp_d0_dataout_channel; +wire [12:0] reg2dp_d0_dataout_height; +wire [12:0] reg2dp_d0_dataout_width; +wire reg2dp_d0_line_packed; +wire [23:0] reg2dp_d0_line_stride; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_proc_precision; +wire reg2dp_d0_surf_packed; +wire [23:0] reg2dp_d0_surf_stride; +wire [4:0] reg2dp_d1_batches; +wire [4:0] reg2dp_d1_clip_truncate; +wire reg2dp_d1_conv_mode; +wire [31:0] reg2dp_d1_cya; +wire [31:0] reg2dp_d1_dataout_addr; +wire [12:0] reg2dp_d1_dataout_channel; +wire [12:0] reg2dp_d1_dataout_height; +wire [12:0] reg2dp_d1_dataout_width; +wire reg2dp_d1_line_packed; +wire [23:0] reg2dp_d1_line_stride; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_proc_precision; +wire reg2dp_d1_surf_packed; +wire [23:0] reg2dp_d1_surf_stride; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [6:0] slcg_op_en_d0; +reg [33:0] cacc2csb_resp_pd; +reg cacc2csb_resp_valid; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg dp2reg_d0_reg; +reg [31:0] dp2reg_d0_sat_count; +reg [31:0] dp2reg_d0_sat_count_w; +reg dp2reg_d0_set; +reg dp2reg_d1_clr; +reg dp2reg_d1_reg; +reg [31:0] dp2reg_d1_sat_count; +reg [31:0] dp2reg_d1_sat_count_w; +reg dp2reg_d1_set; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [4:0] reg2dp_batches; +reg [4:0] reg2dp_clip_truncate; +reg reg2dp_conv_mode; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [31:0] reg2dp_dataout_addr; +reg [12:0] reg2dp_dataout_channel; +reg [12:0] reg2dp_dataout_height; +reg [12:0] reg2dp_dataout_width; +reg reg2dp_line_packed; +reg [23:0] reg2dp_line_stride; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_proc_precision; +reg reg2dp_surf_packed; +reg [23:0] reg2dp_surf_stride; +reg [62:0] req_pd; +reg req_pvld; +reg [6:0] slcg_op_en_d1; +reg [6:0] slcg_op_en_d2; +reg [6:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CACC_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CACC_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.batches (reg2dp_d0_batches[4:0]) //|> w + ,.clip_truncate (reg2dp_d0_clip_truncate[4:0]) //|> w + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.dataout_addr (reg2dp_d0_dataout_addr[31:0]) //|> w + ,.line_packed (reg2dp_d0_line_packed) //|> w + ,.surf_packed (reg2dp_d0_surf_packed) //|> w + ,.dataout_height (reg2dp_d0_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d0_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d0_dataout_channel[12:0]) //|> w + ,.line_stride (reg2dp_d0_line_stride[23:0]) //|> w + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.surf_stride (reg2dp_d0_surf_stride[23:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.sat_count (dp2reg_d0_sat_count[31:0]) //|< r + ); +NV_NVDLA_CACC_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.batches (reg2dp_d1_batches[4:0]) //|> w + ,.clip_truncate (reg2dp_d1_clip_truncate[4:0]) //|> w + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.dataout_addr (reg2dp_d1_dataout_addr[31:0]) //|> w + ,.line_packed (reg2dp_d1_line_packed) //|> w + ,.surf_packed (reg2dp_d1_surf_packed) //|> w + ,.dataout_height (reg2dp_d1_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d1_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d1_dataout_channel[12:0]) //|> w + ,.line_stride (reg2dp_d1_line_stride[23:0]) //|> w + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.surf_stride (reg2dp_d1_surf_stride[23:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.sat_count (dp2reg_d1_sat_count[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {7{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {7{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {7{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {7{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h9008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h9008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h9008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cacc_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cacc_req_pvld) == 1'b1) begin + req_pd <= csb2cacc_req_pd; +// VCS coverage off + end else if ((csb2cacc_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cacc_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cacc_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cacc2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cacc2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid <= 1'b0; + end else begin + cacc2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_batches + or reg2dp_d0_batches + ) begin + reg2dp_batches = dp2reg_consumer ? reg2dp_d1_batches : reg2dp_d0_batches; +end +always @( + dp2reg_consumer + or reg2dp_d1_clip_truncate + or reg2dp_d0_clip_truncate + ) begin + reg2dp_clip_truncate = dp2reg_consumer ? reg2dp_d1_clip_truncate : reg2dp_d0_clip_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_addr + or reg2dp_d0_dataout_addr + ) begin + reg2dp_dataout_addr = dp2reg_consumer ? reg2dp_d1_dataout_addr : reg2dp_d0_dataout_addr; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_packed + or reg2dp_d0_line_packed + ) begin + reg2dp_line_packed = dp2reg_consumer ? reg2dp_d1_line_packed : reg2dp_d0_line_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_packed + or reg2dp_d0_surf_packed + ) begin + reg2dp_surf_packed = dp2reg_consumer ? reg2dp_d1_surf_packed : reg2dp_d0_surf_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_height + or reg2dp_d0_dataout_height + ) begin + reg2dp_dataout_height = dp2reg_consumer ? reg2dp_d1_dataout_height : reg2dp_d0_dataout_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_width + or reg2dp_d0_dataout_width + ) begin + reg2dp_dataout_width = dp2reg_consumer ? reg2dp_d1_dataout_width : reg2dp_d0_dataout_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_channel + or reg2dp_d0_dataout_channel + ) begin + reg2dp_dataout_channel = dp2reg_consumer ? reg2dp_d1_dataout_channel : reg2dp_d0_dataout_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_stride + or reg2dp_d0_line_stride + ) begin + reg2dp_line_stride = dp2reg_consumer ? reg2dp_d1_line_stride : reg2dp_d0_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_stride + or reg2dp_d0_surf_stride + ) begin + reg2dp_surf_stride = dp2reg_consumer ? reg2dp_d1_surf_stride : reg2dp_d0_surf_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// for general counting register // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////////////////////////////////////////////////////////////////////// +// for output saturation register // +//////////////////////////////////////////////////////////////////////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_sat_count + or dp2reg_d0_clr + or dp2reg_d0_sat_count + ) begin + dp2reg_d0_sat_count_w = (dp2reg_d0_set) ? dp2reg_sat_count : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_sat_count; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_sat_count <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_sat_count <= dp2reg_d0_sat_count_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_sat_count <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_sat_count + or dp2reg_d1_clr + or dp2reg_d1_sat_count + ) begin + dp2reg_d1_sat_count_w = (dp2reg_d1_set) ? dp2reg_sat_count : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_sat_count; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_sat_count <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_sat_count <= dp2reg_d1_sat_count_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_sat_count <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CACC_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v new file mode 100644 index 0000000..ef9ffad --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_single_reg.v +module NV_NVDLA_CACC_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cacc_s_pointer_0_out; +wire [31:0] nvdla_cacc_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cacc_s_pointer_0_wren = (reg_offset_wr == (32'h9004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_s_status_0_wren = (reg_offset_wr == (32'h9000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cacc_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cacc_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cacc_s_pointer_0_out + or nvdla_cacc_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h9004 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_s_pointer_0_out ; + end + (32'h9000 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CACC_S_POINTER_0::consumer +// Register: NVDLA_CACC_S_POINTER_0 Field: producer + if (nvdla_cacc_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CACC_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CACC_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h9004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_s_pointer_0_out, nvdla_cacc_s_pointer_0_out); + (32'h9000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CACC_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CACC_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v.vcp new file mode 100644 index 0000000..ef9ffad --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_single_reg.v +module NV_NVDLA_CACC_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cacc_s_pointer_0_out; +wire [31:0] nvdla_cacc_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cacc_s_pointer_0_wren = (reg_offset_wr == (32'h9004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cacc_s_status_0_wren = (reg_offset_wr == (32'h9000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cacc_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cacc_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cacc_s_pointer_0_out + or nvdla_cacc_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h9004 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_s_pointer_0_out ; + end + (32'h9000 & 32'h00000fff): begin + reg_rd_data = nvdla_cacc_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CACC_S_POINTER_0::consumer +// Register: NVDLA_CACC_S_POINTER_0 Field: producer + if (nvdla_cacc_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CACC_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CACC_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h9004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CACC_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cacc_s_pointer_0_out, nvdla_cacc_s_pointer_0_out); + (32'h9000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CACC_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CACC_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v new file mode 100644 index 0000000..a9309c9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_slcg.v +module NV_NVDLA_CACC_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CACC_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v.vcp new file mode 100644 index 0000000..a9309c9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v.vcp @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC_slcg.v +module NV_NVDLA_CACC_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CACC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CACC_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_cacc.v b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_cacc.v new file mode 100644 index 0000000..06c69cb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_cacc.v @@ -0,0 +1,369 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cacc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_cacc ( + cacc2sdp_ready //|< i + ,csb2cacc_req_pd //|< i + ,csb2cacc_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_a2accu_data${i} //|< i +//: ,mac_b2accu_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac_a2accu_data0 //|< i +,mac_b2accu_data0 //|< i +,mac_a2accu_data1 //|< i +,mac_b2accu_data1 //|< i +,mac_a2accu_data2 //|< i +,mac_b2accu_data2 //|< i +,mac_a2accu_data3 //|< i +,mac_b2accu_data3 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac_a2accu_mask //|< i + ,mac_a2accu_mode //|< i + ,mac_a2accu_pd //|< i + ,mac_a2accu_pvld //|< i + ,mac_b2accu_mask //|< i + ,mac_b2accu_mode //|< i + ,mac_b2accu_pd //|< i + ,mac_b2accu_pvld //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,accu2sc_credit_size //|> o + ,accu2sc_credit_vld //|> o + ,cacc2csb_resp_pd //|> o + ,cacc2csb_resp_valid //|> o + ,cacc2glb_done_intr_pd //|> o + ,cacc2sdp_pd //|> o + ,cacc2sdp_valid //|> o + ,csb2cacc_req_prdy //|> o + ); +// +// NV_NVDLA_cacc_ports.v +// +input nvdla_core_clk; /* csb2cacc_req, cacc2csb_resp, mac_a2accu, mac_b2accu, cacc2sdp, accu2sc_credit, cacc2glb_done_intr */ +input nvdla_core_rstn; /* csb2cacc_req, cacc2csb_resp, mac_a2accu, mac_b2accu, cacc2sdp, accu2sc_credit, cacc2glb_done_intr */ +input [31:0] pwrbus_ram_pd; +input csb2cacc_req_pvld; /* data valid */ +output csb2cacc_req_prdy; /* data return handshake */ +input [62:0] csb2cacc_req_pd; +output cacc2csb_resp_valid; /* data valid */ +output [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input mac_a2accu_pvld; /* data valid */ +input [8/2-1:0] mac_a2accu_mask; +input mac_a2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_a2accu_data${i}; //|< i +//: input [19 -1:0] mac_b2accu_data${i}; //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac_a2accu_data0; //|< i +input [19 -1:0] mac_b2accu_data0; //|< i +input [19 -1:0] mac_a2accu_data1; //|< i +input [19 -1:0] mac_b2accu_data1; //|< i +input [19 -1:0] mac_a2accu_data2; //|< i +input [19 -1:0] mac_b2accu_data2; //|< i +input [19 -1:0] mac_a2accu_data3; //|< i +input [19 -1:0] mac_b2accu_data3; //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] mac_a2accu_pd; +input mac_b2accu_pvld; /* data valid */ +input [8/2-1:0] mac_b2accu_mask; +input mac_b2accu_mode; +input [8:0] mac_b2accu_pd; +output cacc2sdp_valid; /* data valid */ +input cacc2sdp_ready; /* data return handshake */ +output [32*1 +2 -1:0] cacc2sdp_pd; +output accu2sc_credit_vld; /* data valid */ +output [2:0] accu2sc_credit_size; +output [1:0] cacc2glb_done_intr_pd; +//Port for SLCG +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire [3 +1 -1:0] abuf_rd_addr; +wire [34*8 -1:0] abuf_rd_data; +wire abuf_rd_en; +wire [3 +1 -1:0] abuf_wr_addr; +wire [34*8 -1:0] abuf_wr_data; +wire abuf_wr_en; +wire [12:0] accu_ctrl_pd; +wire accu_ctrl_ram_valid; +wire accu_ctrl_valid; +wire cfg_in_en_mask; +wire cfg_is_wg; +wire [4:0] cfg_truncate; +wire [3 +1 -1:0] dbuf_rd_addr; +wire dbuf_rd_en; +wire dbuf_rd_layer_end; +wire dbuf_rd_ready; +wire [3 +1 -1:0] dbuf_wr_addr; +wire [32*8 -1:0] dbuf_wr_data; +wire dbuf_wr_en; +wire [32*8 -1:0] dlv_data; +wire dlv_mask; +wire [1:0] dlv_pd; +wire dlv_valid; +wire dp2reg_done; +wire [31:0] dp2reg_sat_count; +wire nvdla_cell_gated_clk; +wire nvdla_op_gated_clk_0; +wire nvdla_op_gated_clk_1; +wire nvdla_op_gated_clk_2; +wire [4:0] reg2dp_batches; +wire [4:0] reg2dp_clip_truncate; +wire [0:0] reg2dp_conv_mode; +wire [31:0] reg2dp_cya; +wire [31:0] reg2dp_dataout_addr; +wire [12:0] reg2dp_dataout_channel; +wire [12:0] reg2dp_dataout_height; +wire [12:0] reg2dp_dataout_width; +wire [0:0] reg2dp_line_packed; +wire [23:0] reg2dp_line_stride; +wire [0:0] reg2dp_op_en; +wire [1:0] reg2dp_proc_precision; +wire [0:0] reg2dp_surf_packed; +wire [23:0] reg2dp_surf_stride; +wire slcg_cell_en; +wire [6:0] slcg_op_en; +wire wait_for_op_en; +//========================================================== +// Regfile +//========================================================== +NV_NVDLA_CACC_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2cacc_req_pd (csb2cacc_req_pd) //|< i + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.dp2reg_sat_count (dp2reg_sat_count) //|< w + ,.cacc2csb_resp_pd (cacc2csb_resp_pd) //|> o + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) //|> o + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) //|> o + ,.reg2dp_batches (reg2dp_batches) //|> w + ,.reg2dp_clip_truncate (reg2dp_clip_truncate) //|> w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w + ,.reg2dp_cya (reg2dp_cya) //|> w * + ,.reg2dp_dataout_addr (reg2dp_dataout_addr) //|> w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel) //|> w + ,.reg2dp_dataout_height (reg2dp_dataout_height) //|> w + ,.reg2dp_dataout_width (reg2dp_dataout_width) //|> w + ,.reg2dp_line_packed (reg2dp_line_packed) //|> w + ,.reg2dp_line_stride (reg2dp_line_stride) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision) //|> w + ,.reg2dp_surf_packed (reg2dp_surf_packed) //|> w + ,.reg2dp_surf_stride (reg2dp_surf_stride) //|> w + ,.slcg_op_en (slcg_op_en) //|> w + ); +//========================================================== +// Assembly controller +//========================================================== +NV_NVDLA_CACC_assembly_ctrl u_assembly_ctrl ( + .reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision) //|< w + ,.reg2dp_clip_truncate (reg2dp_clip_truncate) //|< w + ,.nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.mac_a2accu_pd (mac_a2accu_pd) //|< i + ,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i + ,.mac_b2accu_pd (mac_b2accu_pd) //|< i + ,.mac_b2accu_pvld (mac_b2accu_pvld) //|< i + ,.abuf_rd_addr (abuf_rd_addr) //|> w + ,.abuf_rd_en (abuf_rd_en) //|> w + ,.accu_ctrl_pd (accu_ctrl_pd) //|> w + ,.accu_ctrl_ram_valid ( accu_ctrl_ram_valid) //|> w + ,.accu_ctrl_valid (accu_ctrl_valid) //|> w + ,.cfg_in_en_mask (cfg_in_en_mask) //|> w + ,.cfg_is_wg (cfg_is_wg) //|> w + ,.cfg_truncate (cfg_truncate) //|> w + ,.slcg_cell_en (slcg_cell_en) //|> w + ,.wait_for_op_en (wait_for_op_en) //|> w + ); +//========================================================== +// Assembly buffer +//========================================================== +NV_NVDLA_CACC_assembly_buffer u_assembly_buffer ( + .nvdla_core_clk (nvdla_op_gated_clk_1) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.abuf_rd_addr (abuf_rd_addr) //|< w + ,.abuf_rd_en (abuf_rd_en) //|< w + ,.abuf_wr_addr (abuf_wr_addr) //|< w + ,.abuf_wr_data (abuf_wr_data) //|< w + ,.abuf_wr_en (abuf_wr_en) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i + ,.abuf_rd_data (abuf_rd_data) //|> w + ); +//========================================================== +// CACC calculator +//========================================================== +NV_NVDLA_CACC_calculator u_calculator ( + .nvdla_cell_clk (nvdla_cell_gated_clk) //|< w + ,.nvdla_core_clk (nvdla_op_gated_clk_2) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.abuf_rd_data (abuf_rd_data) //|< w + ,.accu_ctrl_pd (accu_ctrl_pd) //|< w + ,.accu_ctrl_ram_valid (accu_ctrl_ram_valid) //|< w + ,.accu_ctrl_valid (accu_ctrl_valid) //|< w + ,.cfg_in_en_mask (cfg_in_en_mask) //|< w + ,.cfg_is_wg (cfg_is_wg) //|< w + ,.cfg_truncate (cfg_truncate) //|< w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_a2accu_data${i} (mac_a2accu_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac_a2accu_data0 (mac_a2accu_data0) //|< i +,.mac_a2accu_data1 (mac_a2accu_data1) //|< i +,.mac_a2accu_data2 (mac_a2accu_data2) //|< i +,.mac_a2accu_data3 (mac_a2accu_data3) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac_a2accu_mask (mac_a2accu_mask) //|< i + ,.mac_a2accu_mode (mac_a2accu_mode) //|< i + ,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_b2accu_data${i} (mac_b2accu_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac_b2accu_data0 (mac_b2accu_data0) //|< i +,.mac_b2accu_data1 (mac_b2accu_data1) //|< i +,.mac_b2accu_data2 (mac_b2accu_data2) //|< i +,.mac_b2accu_data3 (mac_b2accu_data3) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac_b2accu_mask (mac_b2accu_mask) //|< i + ,.mac_b2accu_mode (mac_b2accu_mode) //|< i + ,.mac_b2accu_pvld (mac_b2accu_pvld) //|< i + ,.abuf_wr_addr (abuf_wr_addr) //|> w + ,.abuf_wr_data (abuf_wr_data) //|> w + ,.abuf_wr_en (abuf_wr_en) //|> w + ,.dlv_data (dlv_data) //|> w + ,.dlv_mask (dlv_mask) //|> w + ,.dlv_pd (dlv_pd) //|> w + ,.dlv_valid (dlv_valid) //|> w + ,.dp2reg_sat_count (dp2reg_sat_count) //|> w + ); +//========================================================== +// Delivery controller +//========================================================== +NV_NVDLA_CACC_delivery_ctrl u_delivery_ctrl ( + .reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision) //|< w + ,.reg2dp_dataout_width (reg2dp_dataout_width) //|< w + ,.reg2dp_dataout_height (reg2dp_dataout_height) //|< w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel) //|< w + ,.reg2dp_dataout_addr (reg2dp_dataout_addr[31:3]) //|< w + ,.reg2dp_line_packed (reg2dp_line_packed) //|< w + ,.reg2dp_surf_packed (reg2dp_surf_packed) //|< w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|< w + ,.reg2dp_line_stride (reg2dp_line_stride) //|< w + ,.reg2dp_surf_stride (reg2dp_surf_stride) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2sdp_ready (cacc2sdp_ready) //|< i + ,.cacc2sdp_valid (cacc2sdp_valid) //|< o + ,.dbuf_rd_ready (dbuf_rd_ready) //|< w + ,.dlv_data (dlv_data) //|< w + ,.dlv_mask (dlv_mask) //|< w + ,.dlv_pd (dlv_pd) //|< w + ,.dlv_valid (dlv_valid) //|< w + ,.wait_for_op_en (wait_for_op_en) //|< w + ,.dbuf_rd_addr (dbuf_rd_addr) //|> w + ,.dbuf_rd_en (dbuf_rd_en) //|> w + ,.dbuf_rd_layer_end (dbuf_rd_layer_end) //|> w + ,.dbuf_wr_addr (dbuf_wr_addr) //|> w + ,.dbuf_wr_data (dbuf_wr_data) //|> w + ,.dbuf_wr_en (dbuf_wr_en) //|> w + ,.dp2reg_done (dp2reg_done) //|> w + ); +//========================================================== +// Delivery buffer +//========================================================== +NV_NVDLA_CACC_delivery_buffer u_delivery_buffer ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2sdp_ready (cacc2sdp_ready) //|< i + ,.dbuf_rd_addr (dbuf_rd_addr) //|< w + ,.dbuf_rd_en (dbuf_rd_en) //|< w + ,.dbuf_rd_layer_end (dbuf_rd_layer_end) //|< w + ,.dbuf_wr_addr (dbuf_wr_addr) //|< w + ,.dbuf_wr_data (dbuf_wr_data) //|< w + ,.dbuf_wr_en (dbuf_wr_en) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd) //|> o + ,.cacc2sdp_pd (cacc2sdp_pd) //|> o + ,.cacc2sdp_valid (cacc2sdp_valid) //|> o + ,.dbuf_rd_ready (dbuf_rd_ready) //|> w + ,.accu2sc_credit_size (accu2sc_credit_size) //|> o + ,.accu2sc_credit_vld (accu2sc_credit_vld) //|> o + ); +//========================================================== +// SLCG groups +//========================================================== +NV_NVDLA_CACC_slcg u_slcg_op_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[0]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w + ); +NV_NVDLA_CACC_slcg u_slcg_op_1 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[1]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w + ); +NV_NVDLA_CACC_slcg u_slcg_op_2 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[2]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w + ); +NV_NVDLA_CACC_slcg u_slcg_cell_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[3]) //|< w + ,.slcg_en_src_1 (slcg_cell_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_cell_gated_clk) //|> w + ); +endmodule // NV_NVDLA_cacc diff --git a/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_cacc.v.vcp b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_cacc.v.vcp new file mode 100644 index 0000000..43ddc2c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cacc/NV_NVDLA_cacc.v.vcp @@ -0,0 +1,333 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cacc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +module NV_NVDLA_cacc ( + cacc2sdp_ready //|< i + ,csb2cacc_req_pd //|< i + ,csb2cacc_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_a2accu_data${i} //|< i +//: ,mac_b2accu_data${i} //|< i ) +//: } + ,mac_a2accu_mask //|< i + ,mac_a2accu_mode //|< i + ,mac_a2accu_pd //|< i + ,mac_a2accu_pvld //|< i + ,mac_b2accu_mask //|< i + ,mac_b2accu_mode //|< i + ,mac_b2accu_pd //|< i + ,mac_b2accu_pvld //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,accu2sc_credit_size //|> o + ,accu2sc_credit_vld //|> o + ,cacc2csb_resp_pd //|> o + ,cacc2csb_resp_valid //|> o + ,cacc2glb_done_intr_pd //|> o + ,cacc2sdp_pd //|> o + ,cacc2sdp_valid //|> o + ,csb2cacc_req_prdy //|> o + ); +// +// NV_NVDLA_cacc_ports.v +// +input nvdla_core_clk; /* csb2cacc_req, cacc2csb_resp, mac_a2accu, mac_b2accu, cacc2sdp, accu2sc_credit, cacc2glb_done_intr */ +input nvdla_core_rstn; /* csb2cacc_req, cacc2csb_resp, mac_a2accu, mac_b2accu, cacc2sdp, accu2sc_credit, cacc2glb_done_intr */ +input [31:0] pwrbus_ram_pd; +input csb2cacc_req_pvld; /* data valid */ +output csb2cacc_req_prdy; /* data return handshake */ +input [62:0] csb2cacc_req_pd; +output cacc2csb_resp_valid; /* data valid */ +output [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input mac_a2accu_pvld; /* data valid */ +input [8/2-1:0] mac_a2accu_mask; +input mac_a2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_a2accu_data${i}; //|< i +//: input [19 -1:0] mac_b2accu_data${i}; //|< i ) +//: } +input [8:0] mac_a2accu_pd; +input mac_b2accu_pvld; /* data valid */ +input [8/2-1:0] mac_b2accu_mask; +input mac_b2accu_mode; +input [8:0] mac_b2accu_pd; +output cacc2sdp_valid; /* data valid */ +input cacc2sdp_ready; /* data return handshake */ +output [32*1 +2 -1:0] cacc2sdp_pd; +output accu2sc_credit_vld; /* data valid */ +output [2:0] accu2sc_credit_size; +output [1:0] cacc2glb_done_intr_pd; +//Port for SLCG +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire [3 +1 -1:0] abuf_rd_addr; +wire [34*8 -1:0] abuf_rd_data; +wire abuf_rd_en; +wire [3 +1 -1:0] abuf_wr_addr; +wire [34*8 -1:0] abuf_wr_data; +wire abuf_wr_en; +wire [12:0] accu_ctrl_pd; +wire accu_ctrl_ram_valid; +wire accu_ctrl_valid; +wire cfg_in_en_mask; +wire cfg_is_wg; +wire [4:0] cfg_truncate; +wire [3 +1 -1:0] dbuf_rd_addr; +wire dbuf_rd_en; +wire dbuf_rd_layer_end; +wire dbuf_rd_ready; +wire [3 +1 -1:0] dbuf_wr_addr; +wire [32*8 -1:0] dbuf_wr_data; +wire dbuf_wr_en; +wire [32*8 -1:0] dlv_data; +wire dlv_mask; +wire [1:0] dlv_pd; +wire dlv_valid; +wire dp2reg_done; +wire [31:0] dp2reg_sat_count; +wire nvdla_cell_gated_clk; +wire nvdla_op_gated_clk_0; +wire nvdla_op_gated_clk_1; +wire nvdla_op_gated_clk_2; +wire [4:0] reg2dp_batches; +wire [4:0] reg2dp_clip_truncate; +wire [0:0] reg2dp_conv_mode; +wire [31:0] reg2dp_cya; +wire [31:0] reg2dp_dataout_addr; +wire [12:0] reg2dp_dataout_channel; +wire [12:0] reg2dp_dataout_height; +wire [12:0] reg2dp_dataout_width; +wire [0:0] reg2dp_line_packed; +wire [23:0] reg2dp_line_stride; +wire [0:0] reg2dp_op_en; +wire [1:0] reg2dp_proc_precision; +wire [0:0] reg2dp_surf_packed; +wire [23:0] reg2dp_surf_stride; +wire slcg_cell_en; +wire [6:0] slcg_op_en; +wire wait_for_op_en; +//========================================================== +// Regfile +//========================================================== +NV_NVDLA_CACC_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2cacc_req_pd (csb2cacc_req_pd) //|< i + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.dp2reg_sat_count (dp2reg_sat_count) //|< w + ,.cacc2csb_resp_pd (cacc2csb_resp_pd) //|> o + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) //|> o + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) //|> o + ,.reg2dp_batches (reg2dp_batches) //|> w + ,.reg2dp_clip_truncate (reg2dp_clip_truncate) //|> w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w + ,.reg2dp_cya (reg2dp_cya) //|> w * + ,.reg2dp_dataout_addr (reg2dp_dataout_addr) //|> w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel) //|> w + ,.reg2dp_dataout_height (reg2dp_dataout_height) //|> w + ,.reg2dp_dataout_width (reg2dp_dataout_width) //|> w + ,.reg2dp_line_packed (reg2dp_line_packed) //|> w + ,.reg2dp_line_stride (reg2dp_line_stride) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision) //|> w + ,.reg2dp_surf_packed (reg2dp_surf_packed) //|> w + ,.reg2dp_surf_stride (reg2dp_surf_stride) //|> w + ,.slcg_op_en (slcg_op_en) //|> w + ); +//========================================================== +// Assembly controller +//========================================================== +NV_NVDLA_CACC_assembly_ctrl u_assembly_ctrl ( + .reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision) //|< w + ,.reg2dp_clip_truncate (reg2dp_clip_truncate) //|< w + ,.nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.mac_a2accu_pd (mac_a2accu_pd) //|< i + ,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i + ,.mac_b2accu_pd (mac_b2accu_pd) //|< i + ,.mac_b2accu_pvld (mac_b2accu_pvld) //|< i + ,.abuf_rd_addr (abuf_rd_addr) //|> w + ,.abuf_rd_en (abuf_rd_en) //|> w + ,.accu_ctrl_pd (accu_ctrl_pd) //|> w + ,.accu_ctrl_ram_valid ( accu_ctrl_ram_valid) //|> w + ,.accu_ctrl_valid (accu_ctrl_valid) //|> w + ,.cfg_in_en_mask (cfg_in_en_mask) //|> w + ,.cfg_is_wg (cfg_is_wg) //|> w + ,.cfg_truncate (cfg_truncate) //|> w + ,.slcg_cell_en (slcg_cell_en) //|> w + ,.wait_for_op_en (wait_for_op_en) //|> w + ); +//========================================================== +// Assembly buffer +//========================================================== +NV_NVDLA_CACC_assembly_buffer u_assembly_buffer ( + .nvdla_core_clk (nvdla_op_gated_clk_1) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.abuf_rd_addr (abuf_rd_addr) //|< w + ,.abuf_rd_en (abuf_rd_en) //|< w + ,.abuf_wr_addr (abuf_wr_addr) //|< w + ,.abuf_wr_data (abuf_wr_data) //|< w + ,.abuf_wr_en (abuf_wr_en) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i + ,.abuf_rd_data (abuf_rd_data) //|> w + ); +//========================================================== +// CACC calculator +//========================================================== +NV_NVDLA_CACC_calculator u_calculator ( + .nvdla_cell_clk (nvdla_cell_gated_clk) //|< w + ,.nvdla_core_clk (nvdla_op_gated_clk_2) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.abuf_rd_data (abuf_rd_data) //|< w + ,.accu_ctrl_pd (accu_ctrl_pd) //|< w + ,.accu_ctrl_ram_valid (accu_ctrl_ram_valid) //|< w + ,.accu_ctrl_valid (accu_ctrl_valid) //|< w + ,.cfg_in_en_mask (cfg_in_en_mask) //|< w + ,.cfg_is_wg (cfg_is_wg) //|< w + ,.cfg_truncate (cfg_truncate) //|< w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_a2accu_data${i} (mac_a2accu_data${i}) //|< i ) +//: } + ,.mac_a2accu_mask (mac_a2accu_mask) //|< i + ,.mac_a2accu_mode (mac_a2accu_mode) //|< i + ,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_b2accu_data${i} (mac_b2accu_data${i}) //|< i ) +//: } + ,.mac_b2accu_mask (mac_b2accu_mask) //|< i + ,.mac_b2accu_mode (mac_b2accu_mode) //|< i + ,.mac_b2accu_pvld (mac_b2accu_pvld) //|< i + ,.abuf_wr_addr (abuf_wr_addr) //|> w + ,.abuf_wr_data (abuf_wr_data) //|> w + ,.abuf_wr_en (abuf_wr_en) //|> w + ,.dlv_data (dlv_data) //|> w + ,.dlv_mask (dlv_mask) //|> w + ,.dlv_pd (dlv_pd) //|> w + ,.dlv_valid (dlv_valid) //|> w + ,.dp2reg_sat_count (dp2reg_sat_count) //|> w + ); +//========================================================== +// Delivery controller +//========================================================== +NV_NVDLA_CACC_delivery_ctrl u_delivery_ctrl ( + .reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision) //|< w + ,.reg2dp_dataout_width (reg2dp_dataout_width) //|< w + ,.reg2dp_dataout_height (reg2dp_dataout_height) //|< w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel) //|< w + ,.reg2dp_dataout_addr (reg2dp_dataout_addr[31:3]) //|< w + ,.reg2dp_line_packed (reg2dp_line_packed) //|< w + ,.reg2dp_surf_packed (reg2dp_surf_packed) //|< w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|< w + ,.reg2dp_line_stride (reg2dp_line_stride) //|< w + ,.reg2dp_surf_stride (reg2dp_surf_stride) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2sdp_ready (cacc2sdp_ready) //|< i + ,.cacc2sdp_valid (cacc2sdp_valid) //|< o + ,.dbuf_rd_ready (dbuf_rd_ready) //|< w + ,.dlv_data (dlv_data) //|< w + ,.dlv_mask (dlv_mask) //|< w + ,.dlv_pd (dlv_pd) //|< w + ,.dlv_valid (dlv_valid) //|< w + ,.wait_for_op_en (wait_for_op_en) //|< w + ,.dbuf_rd_addr (dbuf_rd_addr) //|> w + ,.dbuf_rd_en (dbuf_rd_en) //|> w + ,.dbuf_rd_layer_end (dbuf_rd_layer_end) //|> w + ,.dbuf_wr_addr (dbuf_wr_addr) //|> w + ,.dbuf_wr_data (dbuf_wr_data) //|> w + ,.dbuf_wr_en (dbuf_wr_en) //|> w + ,.dp2reg_done (dp2reg_done) //|> w + ); +//========================================================== +// Delivery buffer +//========================================================== +NV_NVDLA_CACC_delivery_buffer u_delivery_buffer ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2sdp_ready (cacc2sdp_ready) //|< i + ,.dbuf_rd_addr (dbuf_rd_addr) //|< w + ,.dbuf_rd_en (dbuf_rd_en) //|< w + ,.dbuf_rd_layer_end (dbuf_rd_layer_end) //|< w + ,.dbuf_wr_addr (dbuf_wr_addr) //|< w + ,.dbuf_wr_data (dbuf_wr_data) //|< w + ,.dbuf_wr_en (dbuf_wr_en) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd) //|> o + ,.cacc2sdp_pd (cacc2sdp_pd) //|> o + ,.cacc2sdp_valid (cacc2sdp_valid) //|> o + ,.dbuf_rd_ready (dbuf_rd_ready) //|> w + ,.accu2sc_credit_size (accu2sc_credit_size) //|> o + ,.accu2sc_credit_vld (accu2sc_credit_vld) //|> o + ); +//========================================================== +// SLCG groups +//========================================================== +NV_NVDLA_CACC_slcg u_slcg_op_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[0]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w + ); +NV_NVDLA_CACC_slcg u_slcg_op_1 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[1]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w + ); +NV_NVDLA_CACC_slcg u_slcg_op_2 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[2]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w + ); +NV_NVDLA_CACC_slcg u_slcg_cell_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[3]) //|< w + ,.slcg_en_src_1 (slcg_cell_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_cell_gated_clk) //|> w + ); +endmodule // NV_NVDLA_cacc diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_core_reset.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_core_reset.v new file mode 100644 index 0000000..59339d6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_core_reset.v @@ -0,0 +1,75 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_core_reset.v +module NV_NVDLA_core_reset ( + dla_reset_rstn //|< i + ,direct_reset_ //|< i + ,test_mode //|< i + ,synced_rstn //|> o + ,core_reset_rstn //|< i + ,nvdla_clk //|< i + ); +// +// NV_NVDLA_reset_ports.v +// +input dla_reset_rstn; +input direct_reset_; +input test_mode; +output synced_rstn; +input core_reset_rstn; +input nvdla_clk; +wire synced_core_rstn; +wire synced_dla_rstn; +reg combined_rstn; + sync_reset sync_reset_synced_dla_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_dla_rstn) //|> w + ); +//&Instance sync3d_reset u_car_rstn_sync; +// &Connect inreset_ dla_reset_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_dla_rstn; + sync_reset sync_reset_synced_core_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (core_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_core_rstn) //|> w + ); +//&Instance sync3d_reset u_falcon_rstn_sync; +// &Connect inreset_ core_reset_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_core_rstn; +//assign combined_rstn = synced_dla_rstn & synced_core_rstn; +always @(posedge nvdla_clk or negedge synced_dla_rstn) begin + if (!synced_dla_rstn) begin + combined_rstn <= 1'b0; + end else begin + combined_rstn <= synced_dla_rstn & synced_core_rstn; + end +end + sync_reset sync_reset_synced_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (combined_rstn) //|< r + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_rstn) //|> o + ); +// &Connect inreset_ combined_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_rstn; +endmodule // NV_NVDLA_core_reset diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_core_reset.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_core_reset.v.vcp new file mode 100644 index 0000000..59339d6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_core_reset.v.vcp @@ -0,0 +1,75 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_core_reset.v +module NV_NVDLA_core_reset ( + dla_reset_rstn //|< i + ,direct_reset_ //|< i + ,test_mode //|< i + ,synced_rstn //|> o + ,core_reset_rstn //|< i + ,nvdla_clk //|< i + ); +// +// NV_NVDLA_reset_ports.v +// +input dla_reset_rstn; +input direct_reset_; +input test_mode; +output synced_rstn; +input core_reset_rstn; +input nvdla_clk; +wire synced_core_rstn; +wire synced_dla_rstn; +reg combined_rstn; + sync_reset sync_reset_synced_dla_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_dla_rstn) //|> w + ); +//&Instance sync3d_reset u_car_rstn_sync; +// &Connect inreset_ dla_reset_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_dla_rstn; + sync_reset sync_reset_synced_core_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (core_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_core_rstn) //|> w + ); +//&Instance sync3d_reset u_falcon_rstn_sync; +// &Connect inreset_ core_reset_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_core_rstn; +//assign combined_rstn = synced_dla_rstn & synced_core_rstn; +always @(posedge nvdla_clk or negedge synced_dla_rstn) begin + if (!synced_dla_rstn) begin + combined_rstn <= 1'b0; + end else begin + combined_rstn <= synced_dla_rstn & synced_core_rstn; + end +end + sync_reset sync_reset_synced_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (combined_rstn) //|< r + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_rstn) //|> o + ); +// &Connect inreset_ combined_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_rstn; +endmodule // NV_NVDLA_core_reset diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_reset.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_reset.v new file mode 100644 index 0000000..d13815b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_reset.v @@ -0,0 +1,37 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_reset.v +module NV_NVDLA_reset ( + dla_reset_rstn //|< i + ,direct_reset_ //|< i + ,test_mode //|< i + ,synced_rstn //|> o + ,nvdla_clk //|< i + ); +// +// NV_NVDLA_reset_ports.v +// +input dla_reset_rstn; +input direct_reset_; +input test_mode; +output synced_rstn; +input nvdla_clk; + sync_reset sync_reset_synced_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_rstn) //|> o + ); +//&Instance sync3d_reset u_vi_sync_reset; +// &Connect inreset_ dla_reset_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_rstn; +endmodule // NV_NVDLA_reset diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_reset.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_reset.v.vcp new file mode 100644 index 0000000..d13815b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_reset.v.vcp @@ -0,0 +1,37 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_reset.v +module NV_NVDLA_reset ( + dla_reset_rstn //|< i + ,direct_reset_ //|< i + ,test_mode //|< i + ,synced_rstn //|> o + ,nvdla_clk //|< i + ); +// +// NV_NVDLA_reset_ports.v +// +input dla_reset_rstn; +input direct_reset_; +input test_mode; +output synced_rstn; +input nvdla_clk; + sync_reset sync_reset_synced_rstn ( + .clk (nvdla_clk) //|< i + ,.inreset_ (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.outreset_ (synced_rstn) //|> o + ); +//&Instance sync3d_reset u_vi_sync_reset; +// &Connect inreset_ dla_reset_rstn; +// &Connect test_mode test_mode; +// &Connect direct_reset_ direct_reset_; +// &Connect clk nvdla_clk; +// &Connect outreset_ synced_rstn; +endmodule // NV_NVDLA_reset diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d.v new file mode 100644 index 0000000..4ef39e4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d.v @@ -0,0 +1,35 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_ssync3d.v +module NV_NVDLA_ssync3d ( + i_clk + ,sync_i + ,o_clk + ,sync_o + ); +input i_clk; +input sync_i; +input o_clk; +output sync_o; +wire [0:0] sync_i_o_clk_sync_src_data_next; +// verilint 528 off +wire [0:0] sync_i_o_clk_sync_src_data; +// verilint 528 on +wire [0:0] sync_i_o_clk_sync_dst_data; +assign sync_i_o_clk_sync_src_data_next = sync_i; +assign sync_o = sync_i_o_clk_sync_dst_data; +p_STRICTSYNC3DOTM sync_i_o_clk_sync_0 ( + .SRC_CLK (i_clk) + , .SRC_D_NEXT (sync_i_o_clk_sync_src_data_next[0]) + , .SRC_D (sync_i_o_clk_sync_src_data[0]) + , .DST_CLK (o_clk) + , .DST_Q (sync_i_o_clk_sync_dst_data[0]) + , .ATPG_CTL (1'b0) + , .TEST_MODE (1'b0) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d.v.vcp new file mode 100644 index 0000000..4ef39e4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d.v.vcp @@ -0,0 +1,35 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_ssync3d.v +module NV_NVDLA_ssync3d ( + i_clk + ,sync_i + ,o_clk + ,sync_o + ); +input i_clk; +input sync_i; +input o_clk; +output sync_o; +wire [0:0] sync_i_o_clk_sync_src_data_next; +// verilint 528 off +wire [0:0] sync_i_o_clk_sync_src_data; +// verilint 528 on +wire [0:0] sync_i_o_clk_sync_dst_data; +assign sync_i_o_clk_sync_src_data_next = sync_i; +assign sync_o = sync_i_o_clk_sync_dst_data; +p_STRICTSYNC3DOTM sync_i_o_clk_sync_0 ( + .SRC_CLK (i_clk) + , .SRC_D_NEXT (sync_i_o_clk_sync_src_data_next[0]) + , .SRC_D (sync_i_o_clk_sync_src_data[0]) + , .DST_CLK (o_clk) + , .DST_Q (sync_i_o_clk_sync_dst_data[0]) + , .ATPG_CTL (1'b0) + , .TEST_MODE (1'b0) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d_c.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d_c.v new file mode 100644 index 0000000..46986f5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d_c.v @@ -0,0 +1,41 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_ssync3d_c.v +module NV_NVDLA_ssync3d_c ( + i_clk + ,i_rstn + ,sync_i + ,o_clk + ,o_rstn + ,sync_o + ); +input i_clk; +input i_rstn; +input sync_i; +input o_clk; +input o_rstn; +output sync_o; +wire [0:0] sync_i_o_clk_sync_src_data_next; +// verilint 528 off +wire [0:0] sync_i_o_clk_sync_src_data; +// verilint 528 on +wire [0:0] sync_i_o_clk_sync_dst_data; +assign sync_i_o_clk_sync_src_data_next = sync_i; +assign sync_o = sync_i_o_clk_sync_dst_data; +p_STRICTSYNC3DOTM_C_PPP sync_i_o_clk_sync_0 ( + .SRC_CLK (i_clk) + , .SRC_CLRN (i_rstn) + , .SRC_D_NEXT (sync_i_o_clk_sync_src_data_next[0]) + , .SRC_D (sync_i_o_clk_sync_src_data[0]) + , .DST_CLK (o_clk) + , .DST_CLRN (o_rstn) + , .DST_Q (sync_i_o_clk_sync_dst_data[0]) + , .ATPG_CTL (1'b0) + , .TEST_MODE (1'b0) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d_c.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d_c.v.vcp new file mode 100644 index 0000000..46986f5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_ssync3d_c.v.vcp @@ -0,0 +1,41 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_ssync3d_c.v +module NV_NVDLA_ssync3d_c ( + i_clk + ,i_rstn + ,sync_i + ,o_clk + ,o_rstn + ,sync_o + ); +input i_clk; +input i_rstn; +input sync_i; +input o_clk; +input o_rstn; +output sync_o; +wire [0:0] sync_i_o_clk_sync_src_data_next; +// verilint 528 off +wire [0:0] sync_i_o_clk_sync_src_data; +// verilint 528 on +wire [0:0] sync_i_o_clk_sync_dst_data; +assign sync_i_o_clk_sync_src_data_next = sync_i; +assign sync_o = sync_i_o_clk_sync_dst_data; +p_STRICTSYNC3DOTM_C_PPP sync_i_o_clk_sync_0 ( + .SRC_CLK (i_clk) + , .SRC_CLRN (i_rstn) + , .SRC_D_NEXT (sync_i_o_clk_sync_src_data_next[0]) + , .SRC_D (sync_i_o_clk_sync_src_data[0]) + , .DST_CLK (o_clk) + , .DST_CLRN (o_rstn) + , .DST_Q (sync_i_o_clk_sync_dst_data[0]) + , .ATPG_CTL (1'b0) + , .TEST_MODE (1'b0) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d.v new file mode 100644 index 0000000..45f5470 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d.v @@ -0,0 +1,276 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sync3d.v +module NV_NVDLA_sync3d ( + clk + ,sync_i + ,sync_o + ); +input clk; +input sync_i; +output sync_o; +//// generated by ::sync -input sync_i -output sync_o -clock clk -width 1 -type 3D -dft_xclamp +wire [0:0] sync_ibus; +wire [0:0] sync_rbus; +wire [0:0] sync_bbus; +wire [0:0] sync_sbus; +`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`ifndef SYNC_PL_NO_RANDOMIZATION +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS + `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`endif +`endif +`endif +// VCS coverage off +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +reg [0:0] RandSyncBusPipe [0:1]; +reg [0:0] RandSyncBusCurr; +reg [0:0] RandSyncBusNext; +reg [0:0] RandSyncBusRand; +reg [0:0] RandSyncBusPick; +reg [1:1] RandSyncBusKnown; +reg [1:1] RandSyncBusDelta; +reg RandSyncEnable; +reg RandSyncBusEnable; +reg RandSyncBitEnable; +reg RandSyncDiff; +reg RandSyncDone; +reg RandSyncSnap; +reg RandSyncEval; +`endif +// VCS coverage on +// input bus +wire sync_ibus_preDFTxclamp; +wire dft_xclamp_hold_mux_s_sync_i; +wire dft_xclamp_hold_mux_i1_sync_i; +assign sync_ibus_preDFTxclamp = sync_i ; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_hold_sync_i (.Y(dft_xclamp_hold_mux_s_sync_i) ); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_hold_sync_i (.Y(dft_xclamp_hold_mux_i1_sync_i) ); +MUX2HDD2 UJ_FP_MUX_sync_i_dft_xclamp_before_sync ( + .S (dft_xclamp_hold_mux_s_sync_i), + .I0 (sync_ibus_preDFTxclamp), + .I1 (dft_xclamp_hold_mux_i1_sync_i), + .Z (sync_ibus) +); +// random bus +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + assign sync_rbus = RandSyncBusRand; +`else + assign sync_rbus = sync_ibus; +`endif +// buffer bus +assign sync_bbus = sync_rbus; +// sync bus +sync3d sync_0 ( + .clk(clk), + .d(sync_bbus[0]), + .q(sync_sbus[0]) + ); +// defeating sync randomizer +`ifndef NO_PLI_OR_EMU +`ifndef GATES +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + `ifdef NVTOOLS_SYNC2D_GENERIC_CELL +//defparam sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0; + `else + defparam sync_0.first_stage_of_sync.mode = 0; + `endif +`endif +`endif +`endif +// output bus +assign sync_o = sync_sbus; +// VCS coverage off +`ifndef NO_PLI_OR_EMU +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +initial begin + if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m"); +end +initial begin + RandSyncEnable = 1'b1; + if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable = 1'b0; + if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable = 1'b0; +end +// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE. +// curr +always @(sync_ibus) begin + RandSyncBusCurr <= sync_ibus; +end +// snap (glitch filter) +initial RandSyncSnap = 1'b0; +always @(posedge clk) begin + RandSyncSnap <= (RandSyncSnap === 1'bx)? 1'b0 : !RandSyncSnap; +end +// eval (glitch filter) +initial RandSyncEval = 1'b0; +always @(RandSyncBusCurr) begin + RandSyncEval <= (RandSyncEval === 1'bx)? 1'b0 : !RandSyncEval; +end +// eval +always @(RandSyncEval or RandSyncSnap) begin: rand_sync_block + integer i, j; +// bump + for (i=1; i>=1; i=i-1) begin + RandSyncBusPipe[i] = RandSyncBusPipe[i-1]; + end + RandSyncBusPipe[0] = RandSyncBusCurr; +// next + RandSyncBusNext = RandSyncBusPipe[0]; +// rand + if (RandSyncEnable) begin +// known + for (i=1; i>=1; i=i-1) begin + RandSyncBusKnown[i] = |RandSyncBusPipe[i] !== 1'bx; + end +// delta + for (i=1; i>=1; i=i-1) begin + RandSyncBusDelta[i] = |(RandSyncBusPipe[i] ^ RandSyncBusPipe[i-1]); + end + if (&RandSyncBusKnown && |RandSyncBusDelta) begin + RandSyncBusNext = RandSyncBusPipe[1]; + RandSyncBusEnable = prand_inst0(1, 100) > (100 - 50); + if (RandSyncBusEnable) begin + RandSyncDone = 1'b0; + for (i=1; i>=1; i=i-1) begin + RandSyncDiff = RandSyncBusPipe[i] !== RandSyncBusPipe[i-1]; + if (RandSyncDiff && !RandSyncDone) begin + RandSyncBusPickTask (RandSyncBusPipe[i], RandSyncBusPipe[i-1]); + if (RandSyncBusNext !== RandSyncBusPick) begin + RandSyncBusNext = RandSyncBusPick; + RandSyncDone = 1'b1; + end + end + end + end + end + end + RandSyncBusRand = RandSyncBusNext; +end +// task +task RandSyncBusPickTask; // rand value = mixture + input [0:0] RandSyncTaskBusPrev; + input [0:0] RandSyncTaskBusCurr; + integer i; + for (i=0; i<=0; i=i+1) begin + if (RandSyncTaskBusCurr[i] === RandSyncTaskBusPrev[i]) begin + RandSyncBusPick[i] = RandSyncTaskBusCurr[i]; + end else begin + RandSyncBitEnable = prand_inst1(1, 100) > (100 - 50); + RandSyncBusPick[i] = (RandSyncBitEnable)? RandSyncTaskBusCurr[i] : RandSyncTaskBusPrev[i]; + end + end +endtask +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +`endif +// VCS coverage on +endmodule // NV_NVDLA_sync3d diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d.v.vcp new file mode 100644 index 0000000..45f5470 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d.v.vcp @@ -0,0 +1,276 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sync3d.v +module NV_NVDLA_sync3d ( + clk + ,sync_i + ,sync_o + ); +input clk; +input sync_i; +output sync_o; +//// generated by ::sync -input sync_i -output sync_o -clock clk -width 1 -type 3D -dft_xclamp +wire [0:0] sync_ibus; +wire [0:0] sync_rbus; +wire [0:0] sync_bbus; +wire [0:0] sync_sbus; +`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`ifndef SYNC_PL_NO_RANDOMIZATION +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS + `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`endif +`endif +`endif +// VCS coverage off +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +reg [0:0] RandSyncBusPipe [0:1]; +reg [0:0] RandSyncBusCurr; +reg [0:0] RandSyncBusNext; +reg [0:0] RandSyncBusRand; +reg [0:0] RandSyncBusPick; +reg [1:1] RandSyncBusKnown; +reg [1:1] RandSyncBusDelta; +reg RandSyncEnable; +reg RandSyncBusEnable; +reg RandSyncBitEnable; +reg RandSyncDiff; +reg RandSyncDone; +reg RandSyncSnap; +reg RandSyncEval; +`endif +// VCS coverage on +// input bus +wire sync_ibus_preDFTxclamp; +wire dft_xclamp_hold_mux_s_sync_i; +wire dft_xclamp_hold_mux_i1_sync_i; +assign sync_ibus_preDFTxclamp = sync_i ; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_hold_sync_i (.Y(dft_xclamp_hold_mux_s_sync_i) ); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_hold_sync_i (.Y(dft_xclamp_hold_mux_i1_sync_i) ); +MUX2HDD2 UJ_FP_MUX_sync_i_dft_xclamp_before_sync ( + .S (dft_xclamp_hold_mux_s_sync_i), + .I0 (sync_ibus_preDFTxclamp), + .I1 (dft_xclamp_hold_mux_i1_sync_i), + .Z (sync_ibus) +); +// random bus +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + assign sync_rbus = RandSyncBusRand; +`else + assign sync_rbus = sync_ibus; +`endif +// buffer bus +assign sync_bbus = sync_rbus; +// sync bus +sync3d sync_0 ( + .clk(clk), + .d(sync_bbus[0]), + .q(sync_sbus[0]) + ); +// defeating sync randomizer +`ifndef NO_PLI_OR_EMU +`ifndef GATES +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + `ifdef NVTOOLS_SYNC2D_GENERIC_CELL +//defparam sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0; + `else + defparam sync_0.first_stage_of_sync.mode = 0; + `endif +`endif +`endif +`endif +// output bus +assign sync_o = sync_sbus; +// VCS coverage off +`ifndef NO_PLI_OR_EMU +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +initial begin + if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m"); +end +initial begin + RandSyncEnable = 1'b1; + if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable = 1'b0; + if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable = 1'b0; +end +// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE. +// curr +always @(sync_ibus) begin + RandSyncBusCurr <= sync_ibus; +end +// snap (glitch filter) +initial RandSyncSnap = 1'b0; +always @(posedge clk) begin + RandSyncSnap <= (RandSyncSnap === 1'bx)? 1'b0 : !RandSyncSnap; +end +// eval (glitch filter) +initial RandSyncEval = 1'b0; +always @(RandSyncBusCurr) begin + RandSyncEval <= (RandSyncEval === 1'bx)? 1'b0 : !RandSyncEval; +end +// eval +always @(RandSyncEval or RandSyncSnap) begin: rand_sync_block + integer i, j; +// bump + for (i=1; i>=1; i=i-1) begin + RandSyncBusPipe[i] = RandSyncBusPipe[i-1]; + end + RandSyncBusPipe[0] = RandSyncBusCurr; +// next + RandSyncBusNext = RandSyncBusPipe[0]; +// rand + if (RandSyncEnable) begin +// known + for (i=1; i>=1; i=i-1) begin + RandSyncBusKnown[i] = |RandSyncBusPipe[i] !== 1'bx; + end +// delta + for (i=1; i>=1; i=i-1) begin + RandSyncBusDelta[i] = |(RandSyncBusPipe[i] ^ RandSyncBusPipe[i-1]); + end + if (&RandSyncBusKnown && |RandSyncBusDelta) begin + RandSyncBusNext = RandSyncBusPipe[1]; + RandSyncBusEnable = prand_inst0(1, 100) > (100 - 50); + if (RandSyncBusEnable) begin + RandSyncDone = 1'b0; + for (i=1; i>=1; i=i-1) begin + RandSyncDiff = RandSyncBusPipe[i] !== RandSyncBusPipe[i-1]; + if (RandSyncDiff && !RandSyncDone) begin + RandSyncBusPickTask (RandSyncBusPipe[i], RandSyncBusPipe[i-1]); + if (RandSyncBusNext !== RandSyncBusPick) begin + RandSyncBusNext = RandSyncBusPick; + RandSyncDone = 1'b1; + end + end + end + end + end + end + RandSyncBusRand = RandSyncBusNext; +end +// task +task RandSyncBusPickTask; // rand value = mixture + input [0:0] RandSyncTaskBusPrev; + input [0:0] RandSyncTaskBusCurr; + integer i; + for (i=0; i<=0; i=i+1) begin + if (RandSyncTaskBusCurr[i] === RandSyncTaskBusPrev[i]) begin + RandSyncBusPick[i] = RandSyncTaskBusCurr[i]; + end else begin + RandSyncBitEnable = prand_inst1(1, 100) > (100 - 50); + RandSyncBusPick[i] = (RandSyncBitEnable)? RandSyncTaskBusCurr[i] : RandSyncTaskBusPrev[i]; + end + end +endtask +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +`endif +// VCS coverage on +endmodule // NV_NVDLA_sync3d diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_c.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_c.v new file mode 100644 index 0000000..7d89ae5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_c.v @@ -0,0 +1,279 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sync3d_c.v +module NV_NVDLA_sync3d_c ( + clk + ,rst + ,sync_i + ,sync_o + ); +input clk; +input rst; +input sync_i; +output sync_o; +//// generated by ::sync -input sync_i -output sync_o -clock clk -reset rst -width 1 -type 3D -dft_xclamp +wire [0:0] sync_ibus; +wire [0:0] sync_rbus; +wire [0:0] sync_bbus; +wire [0:0] sync_sbus; +`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`ifndef SYNC_PL_NO_RANDOMIZATION +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS + `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`endif +`endif +`endif +// VCS coverage off +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +reg [0:0] RandSyncBusPipe [0:1]; +reg [0:0] RandSyncBusCurr; +reg [0:0] RandSyncBusNext; +reg [0:0] RandSyncBusRand; +reg [0:0] RandSyncBusPick; +reg [1:1] RandSyncBusKnown; +reg [1:1] RandSyncBusDelta; +reg RandSyncEnable; +reg RandSyncBusEnable; +reg RandSyncBitEnable; +reg RandSyncDiff; +reg RandSyncDone; +reg RandSyncSnap; +reg RandSyncEval; +`endif +// VCS coverage on +// input bus +wire sync_ibus_preDFTxclamp; +wire dft_xclamp_hold_mux_s_sync_i; +wire dft_xclamp_hold_mux_i1_sync_i; +assign sync_ibus_preDFTxclamp = sync_i ; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_hold_sync_i (.Y(dft_xclamp_hold_mux_s_sync_i) ); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_hold_sync_i (.Y(dft_xclamp_hold_mux_i1_sync_i) ); +MUX2HDD2 UJ_FP_MUX_sync_i_dft_xclamp_before_sync ( + .S (dft_xclamp_hold_mux_s_sync_i), + .I0 (sync_ibus_preDFTxclamp), + .I1 (dft_xclamp_hold_mux_i1_sync_i), + .Z (sync_ibus) +); +// random bus +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + assign sync_rbus = RandSyncBusRand; +`else + assign sync_rbus = sync_ibus; +`endif +// buffer bus +assign sync_bbus = sync_rbus; +// sync bus +sync3d_c_ppp sync_0 ( + .clk(clk), + .clr_(rst), + .d(sync_bbus[0]), + .q(sync_sbus[0]) + ); +// defeating sync randomizer +`ifndef NO_PLI_OR_EMU +`ifndef GATES +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + `ifdef NVTOOLS_SYNC2D_GENERIC_CELL +//defparam sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0; + `else + defparam sync_0.first_stage_of_sync.mode = 0; + `endif +`endif +`endif +`endif +// output bus +assign sync_o = sync_sbus; +// VCS coverage off +`ifndef NO_PLI_OR_EMU +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +initial begin + if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m"); +end +initial begin + RandSyncEnable = 1'b1; + if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable = 1'b0; + if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable = 1'b0; +end +// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE. +// curr +always @(sync_ibus) begin + RandSyncBusCurr <= sync_ibus; +end +// snap (glitch filter) +initial RandSyncSnap = 1'b0; +always @(posedge clk) begin + RandSyncSnap <= (RandSyncSnap === 1'bx)? 1'b0 : !RandSyncSnap; +end +// eval (glitch filter) +initial RandSyncEval = 1'b0; +always @(RandSyncBusCurr or negedge rst) begin + RandSyncEval <= (RandSyncEval === 1'bx)? 1'b0 : !RandSyncEval; +end +// eval +always @(RandSyncEval or RandSyncSnap) begin: rand_sync_block + integer i, j; +// bump + for (i=1; i>=1; i=i-1) begin + RandSyncBusPipe[i] = RandSyncBusPipe[i-1]; + end + RandSyncBusPipe[0] = RandSyncBusCurr; +// next + RandSyncBusNext = RandSyncBusPipe[0]; +// rand + if (RandSyncEnable && rst) begin +// known + for (i=1; i>=1; i=i-1) begin + RandSyncBusKnown[i] = |RandSyncBusPipe[i] !== 1'bx; + end +// delta + for (i=1; i>=1; i=i-1) begin + RandSyncBusDelta[i] = |(RandSyncBusPipe[i] ^ RandSyncBusPipe[i-1]); + end + if (&RandSyncBusKnown && |RandSyncBusDelta) begin + RandSyncBusNext = RandSyncBusPipe[1]; + RandSyncBusEnable = prand_inst0(1, 100) > (100 - 50); + if (RandSyncBusEnable) begin + RandSyncDone = 1'b0; + for (i=1; i>=1; i=i-1) begin + RandSyncDiff = RandSyncBusPipe[i] !== RandSyncBusPipe[i-1]; + if (RandSyncDiff && !RandSyncDone) begin + RandSyncBusPickTask (RandSyncBusPipe[i], RandSyncBusPipe[i-1]); + if (RandSyncBusNext !== RandSyncBusPick) begin + RandSyncBusNext = RandSyncBusPick; + RandSyncDone = 1'b1; + end + end + end + end + end + end + RandSyncBusRand = RandSyncBusNext; +end +// task +task RandSyncBusPickTask; // rand value = mixture + input [0:0] RandSyncTaskBusPrev; + input [0:0] RandSyncTaskBusCurr; + integer i; + for (i=0; i<=0; i=i+1) begin + if (RandSyncTaskBusCurr[i] === RandSyncTaskBusPrev[i]) begin + RandSyncBusPick[i] = RandSyncTaskBusCurr[i]; + end else begin + RandSyncBitEnable = prand_inst1(1, 100) > (100 - 50); + RandSyncBusPick[i] = (RandSyncBitEnable)? RandSyncTaskBusCurr[i] : RandSyncTaskBusPrev[i]; + end + end +endtask +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +`endif +// VCS coverage on +endmodule // NV_NVDLA_sync3d_c diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_c.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_c.v.vcp new file mode 100644 index 0000000..7d89ae5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_c.v.vcp @@ -0,0 +1,279 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sync3d_c.v +module NV_NVDLA_sync3d_c ( + clk + ,rst + ,sync_i + ,sync_o + ); +input clk; +input rst; +input sync_i; +output sync_o; +//// generated by ::sync -input sync_i -output sync_o -clock clk -reset rst -width 1 -type 3D -dft_xclamp +wire [0:0] sync_ibus; +wire [0:0] sync_rbus; +wire [0:0] sync_bbus; +wire [0:0] sync_sbus; +`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`ifndef SYNC_PL_NO_RANDOMIZATION +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS + `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`endif +`endif +`endif +// VCS coverage off +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +reg [0:0] RandSyncBusPipe [0:1]; +reg [0:0] RandSyncBusCurr; +reg [0:0] RandSyncBusNext; +reg [0:0] RandSyncBusRand; +reg [0:0] RandSyncBusPick; +reg [1:1] RandSyncBusKnown; +reg [1:1] RandSyncBusDelta; +reg RandSyncEnable; +reg RandSyncBusEnable; +reg RandSyncBitEnable; +reg RandSyncDiff; +reg RandSyncDone; +reg RandSyncSnap; +reg RandSyncEval; +`endif +// VCS coverage on +// input bus +wire sync_ibus_preDFTxclamp; +wire dft_xclamp_hold_mux_s_sync_i; +wire dft_xclamp_hold_mux_i1_sync_i; +assign sync_ibus_preDFTxclamp = sync_i ; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_hold_sync_i (.Y(dft_xclamp_hold_mux_s_sync_i) ); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_hold_sync_i (.Y(dft_xclamp_hold_mux_i1_sync_i) ); +MUX2HDD2 UJ_FP_MUX_sync_i_dft_xclamp_before_sync ( + .S (dft_xclamp_hold_mux_s_sync_i), + .I0 (sync_ibus_preDFTxclamp), + .I1 (dft_xclamp_hold_mux_i1_sync_i), + .Z (sync_ibus) +); +// random bus +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + assign sync_rbus = RandSyncBusRand; +`else + assign sync_rbus = sync_ibus; +`endif +// buffer bus +assign sync_bbus = sync_rbus; +// sync bus +sync3d_c_ppp sync_0 ( + .clk(clk), + .clr_(rst), + .d(sync_bbus[0]), + .q(sync_sbus[0]) + ); +// defeating sync randomizer +`ifndef NO_PLI_OR_EMU +`ifndef GATES +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + `ifdef NVTOOLS_SYNC2D_GENERIC_CELL +//defparam sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0; + `else + defparam sync_0.first_stage_of_sync.mode = 0; + `endif +`endif +`endif +`endif +// output bus +assign sync_o = sync_sbus; +// VCS coverage off +`ifndef NO_PLI_OR_EMU +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +initial begin + if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m"); +end +initial begin + RandSyncEnable = 1'b1; + if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable = 1'b0; + if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable = 1'b0; +end +// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE. +// curr +always @(sync_ibus) begin + RandSyncBusCurr <= sync_ibus; +end +// snap (glitch filter) +initial RandSyncSnap = 1'b0; +always @(posedge clk) begin + RandSyncSnap <= (RandSyncSnap === 1'bx)? 1'b0 : !RandSyncSnap; +end +// eval (glitch filter) +initial RandSyncEval = 1'b0; +always @(RandSyncBusCurr or negedge rst) begin + RandSyncEval <= (RandSyncEval === 1'bx)? 1'b0 : !RandSyncEval; +end +// eval +always @(RandSyncEval or RandSyncSnap) begin: rand_sync_block + integer i, j; +// bump + for (i=1; i>=1; i=i-1) begin + RandSyncBusPipe[i] = RandSyncBusPipe[i-1]; + end + RandSyncBusPipe[0] = RandSyncBusCurr; +// next + RandSyncBusNext = RandSyncBusPipe[0]; +// rand + if (RandSyncEnable && rst) begin +// known + for (i=1; i>=1; i=i-1) begin + RandSyncBusKnown[i] = |RandSyncBusPipe[i] !== 1'bx; + end +// delta + for (i=1; i>=1; i=i-1) begin + RandSyncBusDelta[i] = |(RandSyncBusPipe[i] ^ RandSyncBusPipe[i-1]); + end + if (&RandSyncBusKnown && |RandSyncBusDelta) begin + RandSyncBusNext = RandSyncBusPipe[1]; + RandSyncBusEnable = prand_inst0(1, 100) > (100 - 50); + if (RandSyncBusEnable) begin + RandSyncDone = 1'b0; + for (i=1; i>=1; i=i-1) begin + RandSyncDiff = RandSyncBusPipe[i] !== RandSyncBusPipe[i-1]; + if (RandSyncDiff && !RandSyncDone) begin + RandSyncBusPickTask (RandSyncBusPipe[i], RandSyncBusPipe[i-1]); + if (RandSyncBusNext !== RandSyncBusPick) begin + RandSyncBusNext = RandSyncBusPick; + RandSyncDone = 1'b1; + end + end + end + end + end + end + RandSyncBusRand = RandSyncBusNext; +end +// task +task RandSyncBusPickTask; // rand value = mixture + input [0:0] RandSyncTaskBusPrev; + input [0:0] RandSyncTaskBusCurr; + integer i; + for (i=0; i<=0; i=i+1) begin + if (RandSyncTaskBusCurr[i] === RandSyncTaskBusPrev[i]) begin + RandSyncBusPick[i] = RandSyncTaskBusCurr[i]; + end else begin + RandSyncBitEnable = prand_inst1(1, 100) > (100 - 50); + RandSyncBusPick[i] = (RandSyncBitEnable)? RandSyncTaskBusCurr[i] : RandSyncTaskBusPrev[i]; + end + end +endtask +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +`endif +// VCS coverage on +endmodule // NV_NVDLA_sync3d_c diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_s.v b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_s.v new file mode 100644 index 0000000..56381d0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_s.v @@ -0,0 +1,279 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sync3d_s.v +module NV_NVDLA_sync3d_s ( + clk + ,prst + ,sync_i + ,sync_o + ); +input clk; +input prst; +input sync_i; +output sync_o; +//// generated by ::sync -input sync_i -output sync_o -clock clk -preset prst -width 1 -type 3D -dft_xclamp +wire [0:0] sync_ibus; +wire [0:0] sync_rbus; +wire [0:0] sync_bbus; +wire [0:0] sync_sbus; +`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`ifndef SYNC_PL_NO_RANDOMIZATION +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS + `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`endif +`endif +`endif +// VCS coverage off +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +reg [0:0] RandSyncBusPipe [0:1]; +reg [0:0] RandSyncBusCurr; +reg [0:0] RandSyncBusNext; +reg [0:0] RandSyncBusRand; +reg [0:0] RandSyncBusPick; +reg [1:1] RandSyncBusKnown; +reg [1:1] RandSyncBusDelta; +reg RandSyncEnable; +reg RandSyncBusEnable; +reg RandSyncBitEnable; +reg RandSyncDiff; +reg RandSyncDone; +reg RandSyncSnap; +reg RandSyncEval; +`endif +// VCS coverage on +// input bus +wire sync_ibus_preDFTxclamp; +wire dft_xclamp_hold_mux_s_sync_i; +wire dft_xclamp_hold_mux_i1_sync_i; +assign sync_ibus_preDFTxclamp = sync_i ; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_hold_sync_i (.Y(dft_xclamp_hold_mux_s_sync_i) ); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_hold_sync_i (.Y(dft_xclamp_hold_mux_i1_sync_i) ); +MUX2HDD2 UJ_FP_MUX_sync_i_dft_xclamp_before_sync ( + .S (dft_xclamp_hold_mux_s_sync_i), + .I0 (sync_ibus_preDFTxclamp), + .I1 (dft_xclamp_hold_mux_i1_sync_i), + .Z (sync_ibus) +); +// random bus +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + assign sync_rbus = RandSyncBusRand; +`else + assign sync_rbus = sync_ibus; +`endif +// buffer bus +assign sync_bbus = sync_rbus; +// sync bus +sync3d_s_ppp sync_0 ( + .clk(clk), + .set_(prst), + .d(sync_bbus[0]), + .q(sync_sbus[0]) + ); +// defeating sync randomizer +`ifndef NO_PLI_OR_EMU +`ifndef GATES +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + `ifdef NVTOOLS_SYNC2D_GENERIC_CELL +//defparam sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0; + `else + defparam sync_0.first_stage_of_sync.mode = 0; + `endif +`endif +`endif +`endif +// output bus +assign sync_o = sync_sbus; +// VCS coverage off +`ifndef NO_PLI_OR_EMU +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +initial begin + if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m"); +end +initial begin + RandSyncEnable = 1'b1; + if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable = 1'b0; + if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable = 1'b0; +end +// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE. +// curr +always @(sync_ibus) begin + RandSyncBusCurr <= sync_ibus; +end +// snap (glitch filter) +initial RandSyncSnap = 1'b0; +always @(posedge clk) begin + RandSyncSnap <= (RandSyncSnap === 1'bx)? 1'b0 : !RandSyncSnap; +end +// eval (glitch filter) +initial RandSyncEval = 1'b0; +always @(RandSyncBusCurr or negedge prst) begin + RandSyncEval <= (RandSyncEval === 1'bx)? 1'b0 : !RandSyncEval; +end +// eval +always @(RandSyncEval or RandSyncSnap) begin: rand_sync_block + integer i, j; +// bump + for (i=1; i>=1; i=i-1) begin + RandSyncBusPipe[i] = RandSyncBusPipe[i-1]; + end + RandSyncBusPipe[0] = RandSyncBusCurr; +// next + RandSyncBusNext = RandSyncBusPipe[0]; +// rand + if (RandSyncEnable && prst) begin +// known + for (i=1; i>=1; i=i-1) begin + RandSyncBusKnown[i] = |RandSyncBusPipe[i] !== 1'bx; + end +// delta + for (i=1; i>=1; i=i-1) begin + RandSyncBusDelta[i] = |(RandSyncBusPipe[i] ^ RandSyncBusPipe[i-1]); + end + if (&RandSyncBusKnown && |RandSyncBusDelta) begin + RandSyncBusNext = RandSyncBusPipe[1]; + RandSyncBusEnable = prand_inst0(1, 100) > (100 - 50); + if (RandSyncBusEnable) begin + RandSyncDone = 1'b0; + for (i=1; i>=1; i=i-1) begin + RandSyncDiff = RandSyncBusPipe[i] !== RandSyncBusPipe[i-1]; + if (RandSyncDiff && !RandSyncDone) begin + RandSyncBusPickTask (RandSyncBusPipe[i], RandSyncBusPipe[i-1]); + if (RandSyncBusNext !== RandSyncBusPick) begin + RandSyncBusNext = RandSyncBusPick; + RandSyncDone = 1'b1; + end + end + end + end + end + end + RandSyncBusRand = RandSyncBusNext; +end +// task +task RandSyncBusPickTask; // rand value = mixture + input [0:0] RandSyncTaskBusPrev; + input [0:0] RandSyncTaskBusCurr; + integer i; + for (i=0; i<=0; i=i+1) begin + if (RandSyncTaskBusCurr[i] === RandSyncTaskBusPrev[i]) begin + RandSyncBusPick[i] = RandSyncTaskBusCurr[i]; + end else begin + RandSyncBitEnable = prand_inst1(1, 100) > (100 - 50); + RandSyncBusPick[i] = (RandSyncBitEnable)? RandSyncTaskBusCurr[i] : RandSyncTaskBusPrev[i]; + end + end +endtask +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +`endif +// VCS coverage on +endmodule // NV_NVDLA_sync3d_s diff --git a/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_s.v.vcp b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_s.v.vcp new file mode 100644 index 0000000..56381d0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/car/NV_NVDLA_sync3d_s.v.vcp @@ -0,0 +1,279 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sync3d_s.v +module NV_NVDLA_sync3d_s ( + clk + ,prst + ,sync_i + ,sync_o + ); +input clk; +input prst; +input sync_i; +output sync_o; +//// generated by ::sync -input sync_i -output sync_o -clock clk -preset prst -width 1 -type 3D -dft_xclamp +wire [0:0] sync_ibus; +wire [0:0] sync_rbus; +wire [0:0] sync_bbus; +wire [0:0] sync_sbus; +`undef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`ifndef SYNC_PL_NO_RANDOMIZATION +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS + `define SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +`endif +`endif +`endif +// VCS coverage off +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +reg [0:0] RandSyncBusPipe [0:1]; +reg [0:0] RandSyncBusCurr; +reg [0:0] RandSyncBusNext; +reg [0:0] RandSyncBusRand; +reg [0:0] RandSyncBusPick; +reg [1:1] RandSyncBusKnown; +reg [1:1] RandSyncBusDelta; +reg RandSyncEnable; +reg RandSyncBusEnable; +reg RandSyncBitEnable; +reg RandSyncDiff; +reg RandSyncDone; +reg RandSyncSnap; +reg RandSyncEval; +`endif +// VCS coverage on +// input bus +wire sync_ibus_preDFTxclamp; +wire dft_xclamp_hold_mux_s_sync_i; +wire dft_xclamp_hold_mux_i1_sync_i; +assign sync_ibus_preDFTxclamp = sync_i ; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_hold_sync_i (.Y(dft_xclamp_hold_mux_s_sync_i) ); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_hold_sync_i (.Y(dft_xclamp_hold_mux_i1_sync_i) ); +MUX2HDD2 UJ_FP_MUX_sync_i_dft_xclamp_before_sync ( + .S (dft_xclamp_hold_mux_s_sync_i), + .I0 (sync_ibus_preDFTxclamp), + .I1 (dft_xclamp_hold_mux_i1_sync_i), + .Z (sync_ibus) +); +// random bus +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + assign sync_rbus = RandSyncBusRand; +`else + assign sync_rbus = sync_ibus; +`endif +// buffer bus +assign sync_bbus = sync_rbus; +// sync bus +sync3d_s_ppp sync_0 ( + .clk(clk), + .set_(prst), + .d(sync_bbus[0]), + .q(sync_sbus[0]) + ); +// defeating sync randomizer +`ifndef NO_PLI_OR_EMU +`ifndef GATES +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS + `ifdef NVTOOLS_SYNC2D_GENERIC_CELL +//defparam sync_0.NV_GENERIC_CELL.first_stage_of_sync.mode = 0; + `else + defparam sync_0.first_stage_of_sync.mode = 0; + `endif +`endif +`endif +`endif +// output bus +assign sync_o = sync_sbus; +// VCS coverage off +`ifndef NO_PLI_OR_EMU +`ifdef SYNC_PL_NOSYNTHESIS_NOSYNTH_GCS +initial begin + if ($test$plusargs("RandSyncInfo")) $display ("INFO: RandSync: @ %m"); +end +initial begin + RandSyncEnable = 1'b1; + if ($test$plusargs("RandSyncGlobalDisable")) RandSyncEnable = 1'b0; + if ($test$plusargs("RandSyncLocalDisable")) RandSyncEnable = 1'b0; +end +// SRC before DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC equals DSTCLK: new SRC is sampled to CUR, CUR is sampled to PRE, CUR/PRE are randomized. +// SRC after DSTCLK: old SRC is sampled again to CUR (NOP), CUR is sampled to PRE, CUR == PRE. +// curr +always @(sync_ibus) begin + RandSyncBusCurr <= sync_ibus; +end +// snap (glitch filter) +initial RandSyncSnap = 1'b0; +always @(posedge clk) begin + RandSyncSnap <= (RandSyncSnap === 1'bx)? 1'b0 : !RandSyncSnap; +end +// eval (glitch filter) +initial RandSyncEval = 1'b0; +always @(RandSyncBusCurr or negedge prst) begin + RandSyncEval <= (RandSyncEval === 1'bx)? 1'b0 : !RandSyncEval; +end +// eval +always @(RandSyncEval or RandSyncSnap) begin: rand_sync_block + integer i, j; +// bump + for (i=1; i>=1; i=i-1) begin + RandSyncBusPipe[i] = RandSyncBusPipe[i-1]; + end + RandSyncBusPipe[0] = RandSyncBusCurr; +// next + RandSyncBusNext = RandSyncBusPipe[0]; +// rand + if (RandSyncEnable && prst) begin +// known + for (i=1; i>=1; i=i-1) begin + RandSyncBusKnown[i] = |RandSyncBusPipe[i] !== 1'bx; + end +// delta + for (i=1; i>=1; i=i-1) begin + RandSyncBusDelta[i] = |(RandSyncBusPipe[i] ^ RandSyncBusPipe[i-1]); + end + if (&RandSyncBusKnown && |RandSyncBusDelta) begin + RandSyncBusNext = RandSyncBusPipe[1]; + RandSyncBusEnable = prand_inst0(1, 100) > (100 - 50); + if (RandSyncBusEnable) begin + RandSyncDone = 1'b0; + for (i=1; i>=1; i=i-1) begin + RandSyncDiff = RandSyncBusPipe[i] !== RandSyncBusPipe[i-1]; + if (RandSyncDiff && !RandSyncDone) begin + RandSyncBusPickTask (RandSyncBusPipe[i], RandSyncBusPipe[i-1]); + if (RandSyncBusNext !== RandSyncBusPick) begin + RandSyncBusNext = RandSyncBusPick; + RandSyncDone = 1'b1; + end + end + end + end + end + end + RandSyncBusRand = RandSyncBusNext; +end +// task +task RandSyncBusPickTask; // rand value = mixture + input [0:0] RandSyncTaskBusPrev; + input [0:0] RandSyncTaskBusCurr; + integer i; + for (i=0; i<=0; i=i+1) begin + if (RandSyncTaskBusCurr[i] === RandSyncTaskBusPrev[i]) begin + RandSyncBusPick[i] = RandSyncTaskBusCurr[i]; + end else begin + RandSyncBitEnable = prand_inst1(1, 100) > (100 - 50); + RandSyncBusPick[i] = (RandSyncBitEnable)? RandSyncTaskBusCurr[i] : RandSyncTaskBusPrev[i]; + end + end +endtask +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +`endif +// VCS coverage on +endmodule // NV_NVDLA_sync3d_s diff --git a/designs/src/NVDLA/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v b/designs/src/NVDLA/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v new file mode 100644 index 0000000..1189e7c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v @@ -0,0 +1,10615 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cbuf.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +`include "simulate_x_tick.vh" +module NV_NVDLA_cbuf ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//port 0 for data, 1 for weight +//: for(my $i=0; $i<2 ; $i++){ +//: print qq( +//: ,cdma2buf_wr_addr${i} //|< i +//: ,cdma2buf_wr_data${i} //|< i +//: ,cdma2buf_wr_en${i} //|< i +//: ,cdma2buf_wr_sel${i} //|< i +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,cdma2buf_wr_addr0 //|< i +,cdma2buf_wr_data0 //|< i +,cdma2buf_wr_en0 //|< i +,cdma2buf_wr_sel0 //|< i + +,cdma2buf_wr_addr1 //|< i +,cdma2buf_wr_data1 //|< i +,cdma2buf_wr_en1 //|< i +,cdma2buf_wr_sel1 //|< i + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,pwrbus_ram_pd //|< i + ,sc2buf_dat_rd_addr //|< i + ,sc2buf_dat_rd_en //|< i + ,sc2buf_dat_rd_shift //|< i + ,sc2buf_dat_rd_next1_en //< i + ,sc2buf_dat_rd_next1_addr //< i + ,sc2buf_dat_rd_data //|> o + ,sc2buf_dat_rd_valid //|> o + ,sc2buf_wt_rd_addr //|< i + ,sc2buf_wt_rd_en //|< i + ,sc2buf_wt_rd_data //|> o + ,sc2buf_wt_rd_valid //|> o + `ifdef CBUF_WEIGHT_COMPRESSED + ,sc2buf_wmb_rd_addr //|< i + ,sc2buf_wmb_rd_en //|< i + ,sc2buf_wmb_rd_data //|> o + ,sc2buf_wmb_rd_valid //|> o + `endif + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +//: for(my $i=0; $i<2 ; $i++) { +//: print qq( +//: input[14 -1:0] cdma2buf_wr_addr${i}; //|< i +//: input[64 -1:0] cdma2buf_wr_data${i}; //|< i +//: input cdma2buf_wr_en${i}; //|< i +//: input[1 -1:0] cdma2buf_wr_sel${i}; //|< i +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input[14 -1:0] cdma2buf_wr_addr0; //|< i +input[64 -1:0] cdma2buf_wr_data0; //|< i +input cdma2buf_wr_en0; //|< i +input[1 -1:0] cdma2buf_wr_sel0; //|< i + +input[14 -1:0] cdma2buf_wr_addr1; //|< i +input[64 -1:0] cdma2buf_wr_data1; //|< i +input cdma2buf_wr_en1; //|< i +input[1 -1:0] cdma2buf_wr_sel1; //|< i + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input sc2buf_dat_rd_en; /* data valid */ +input [14 -1:0] sc2buf_dat_rd_addr; +input [7 -1:0] sc2buf_dat_rd_shift; //|< i +input sc2buf_dat_rd_next1_en; //< i +input [14 -1:0] sc2buf_dat_rd_next1_addr; //< i +output sc2buf_dat_rd_valid; /* data valid */ +output [64 -1:0] sc2buf_dat_rd_data; +input sc2buf_wt_rd_en; /* data valid */ +input [14 -1:0] sc2buf_wt_rd_addr; +output sc2buf_wt_rd_valid; /* data valid */ +output [64 -1:0] sc2buf_wt_rd_data; +`ifdef CBUF_WEIGHT_COMPRESSED +input sc2buf_wmb_rd_en; /* data valid */ +input [14 -1:0] sc2buf_wmb_rd_addr; +output sc2buf_wmb_rd_valid; /* data valid */ +output [64 -1:0] sc2buf_wmb_rd_data; +`endif +`ifndef SYNTHESIS +`ifdef CDMA2CBUF_DEBUG_PRINT +`ifdef VERILATOR +`else +reg cdma2cbuf_data_begin, cdma2cbuf_wt_begin; +integer data_file, wt_file; +initial begin + assign cdma2cbuf_wt_begin=0; + assign cdma2cbuf_data_begin=0; + @(negedge cdma2buf_wr_en1) assign cdma2cbuf_wt_begin=1; + @(negedge cdma2buf_wr_en0) assign cdma2cbuf_data_begin=1; + data_file = $fopen("cdma2cbuf_data_rtl.dat"); + wt_file = $fopen("cdma2cbuf_weight_rtl.dat"); + if(cdma2cbuf_data_begin & cdma2cbuf_wt_begin) begin + forever @(posedge nvdla_core_clk) begin + if(cdma2buf_wr_en0) begin + $fwrite(data_file,"%h\n",cdma2buf_wr_data0); + end + if (cdma2buf_wr_en1) begin + $fwrite(wt_file,"%h\n",cdma2buf_wr_data1); + end + end + end +end +`endif +`endif +`endif // SYNTHESIS +//////////step1:write handle +//decode write address to sram +//: my $bank_slice= "13:9"; #address part for select bank +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: for(my $i=0; $i<2 ; $i++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_wr${i}_en_d0 = cdma2buf_wr_en${i}&&(cdma2buf_wr_addr${i}[${bank_slice}]==${j}) &&(cdma2buf_wr_sel${i}[${k}]==1'b1); ); +//: } +//: if(2==2){ +//: print qq( +//: wire bank${j}_ram${k}_wr${i}_en_d0 = cdma2buf_wr_en${i}&&(cdma2buf_wr_addr${i}[${bank_slice}]==${j})&&(cdma2buf_wr_addr${i}[0]==${k}); ); +//: } +//: if(2==3){ +//: #complicated,reserve, no use currently +//: } +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire bank0_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==0)&&(cdma2buf_wr_addr0[0]==0); +wire bank0_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==0)&&(cdma2buf_wr_addr1[0]==0); +wire bank0_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==0)&&(cdma2buf_wr_addr0[0]==1); +wire bank0_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==0)&&(cdma2buf_wr_addr1[0]==1); +wire bank1_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==1)&&(cdma2buf_wr_addr0[0]==0); +wire bank1_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==1)&&(cdma2buf_wr_addr1[0]==0); +wire bank1_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==1)&&(cdma2buf_wr_addr0[0]==1); +wire bank1_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==1)&&(cdma2buf_wr_addr1[0]==1); +wire bank2_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==2)&&(cdma2buf_wr_addr0[0]==0); +wire bank2_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==2)&&(cdma2buf_wr_addr1[0]==0); +wire bank2_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==2)&&(cdma2buf_wr_addr0[0]==1); +wire bank2_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==2)&&(cdma2buf_wr_addr1[0]==1); +wire bank3_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==3)&&(cdma2buf_wr_addr0[0]==0); +wire bank3_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==3)&&(cdma2buf_wr_addr1[0]==0); +wire bank3_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==3)&&(cdma2buf_wr_addr0[0]==1); +wire bank3_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==3)&&(cdma2buf_wr_addr1[0]==1); +wire bank4_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==4)&&(cdma2buf_wr_addr0[0]==0); +wire bank4_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==4)&&(cdma2buf_wr_addr1[0]==0); +wire bank4_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==4)&&(cdma2buf_wr_addr0[0]==1); +wire bank4_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==4)&&(cdma2buf_wr_addr1[0]==1); +wire bank5_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==5)&&(cdma2buf_wr_addr0[0]==0); +wire bank5_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==5)&&(cdma2buf_wr_addr1[0]==0); +wire bank5_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==5)&&(cdma2buf_wr_addr0[0]==1); +wire bank5_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==5)&&(cdma2buf_wr_addr1[0]==1); +wire bank6_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==6)&&(cdma2buf_wr_addr0[0]==0); +wire bank6_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==6)&&(cdma2buf_wr_addr1[0]==0); +wire bank6_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==6)&&(cdma2buf_wr_addr0[0]==1); +wire bank6_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==6)&&(cdma2buf_wr_addr1[0]==1); +wire bank7_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==7)&&(cdma2buf_wr_addr0[0]==0); +wire bank7_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==7)&&(cdma2buf_wr_addr1[0]==0); +wire bank7_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==7)&&(cdma2buf_wr_addr0[0]==1); +wire bank7_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==7)&&(cdma2buf_wr_addr1[0]==1); +wire bank8_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==8)&&(cdma2buf_wr_addr0[0]==0); +wire bank8_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==8)&&(cdma2buf_wr_addr1[0]==0); +wire bank8_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==8)&&(cdma2buf_wr_addr0[0]==1); +wire bank8_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==8)&&(cdma2buf_wr_addr1[0]==1); +wire bank9_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==9)&&(cdma2buf_wr_addr0[0]==0); +wire bank9_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==9)&&(cdma2buf_wr_addr1[0]==0); +wire bank9_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==9)&&(cdma2buf_wr_addr0[0]==1); +wire bank9_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==9)&&(cdma2buf_wr_addr1[0]==1); +wire bank10_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==10)&&(cdma2buf_wr_addr0[0]==0); +wire bank10_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==10)&&(cdma2buf_wr_addr1[0]==0); +wire bank10_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==10)&&(cdma2buf_wr_addr0[0]==1); +wire bank10_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==10)&&(cdma2buf_wr_addr1[0]==1); +wire bank11_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==11)&&(cdma2buf_wr_addr0[0]==0); +wire bank11_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==11)&&(cdma2buf_wr_addr1[0]==0); +wire bank11_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==11)&&(cdma2buf_wr_addr0[0]==1); +wire bank11_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==11)&&(cdma2buf_wr_addr1[0]==1); +wire bank12_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==12)&&(cdma2buf_wr_addr0[0]==0); +wire bank12_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==12)&&(cdma2buf_wr_addr1[0]==0); +wire bank12_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==12)&&(cdma2buf_wr_addr0[0]==1); +wire bank12_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==12)&&(cdma2buf_wr_addr1[0]==1); +wire bank13_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==13)&&(cdma2buf_wr_addr0[0]==0); +wire bank13_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==13)&&(cdma2buf_wr_addr1[0]==0); +wire bank13_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==13)&&(cdma2buf_wr_addr0[0]==1); +wire bank13_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==13)&&(cdma2buf_wr_addr1[0]==1); +wire bank14_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==14)&&(cdma2buf_wr_addr0[0]==0); +wire bank14_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==14)&&(cdma2buf_wr_addr1[0]==0); +wire bank14_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==14)&&(cdma2buf_wr_addr0[0]==1); +wire bank14_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==14)&&(cdma2buf_wr_addr1[0]==1); +wire bank15_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==15)&&(cdma2buf_wr_addr0[0]==0); +wire bank15_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==15)&&(cdma2buf_wr_addr1[0]==0); +wire bank15_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==15)&&(cdma2buf_wr_addr0[0]==1); +wire bank15_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==15)&&(cdma2buf_wr_addr1[0]==1); +wire bank16_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==16)&&(cdma2buf_wr_addr0[0]==0); +wire bank16_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==16)&&(cdma2buf_wr_addr1[0]==0); +wire bank16_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==16)&&(cdma2buf_wr_addr0[0]==1); +wire bank16_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==16)&&(cdma2buf_wr_addr1[0]==1); +wire bank17_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==17)&&(cdma2buf_wr_addr0[0]==0); +wire bank17_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==17)&&(cdma2buf_wr_addr1[0]==0); +wire bank17_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==17)&&(cdma2buf_wr_addr0[0]==1); +wire bank17_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==17)&&(cdma2buf_wr_addr1[0]==1); +wire bank18_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==18)&&(cdma2buf_wr_addr0[0]==0); +wire bank18_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==18)&&(cdma2buf_wr_addr1[0]==0); +wire bank18_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==18)&&(cdma2buf_wr_addr0[0]==1); +wire bank18_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==18)&&(cdma2buf_wr_addr1[0]==1); +wire bank19_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==19)&&(cdma2buf_wr_addr0[0]==0); +wire bank19_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==19)&&(cdma2buf_wr_addr1[0]==0); +wire bank19_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==19)&&(cdma2buf_wr_addr0[0]==1); +wire bank19_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==19)&&(cdma2buf_wr_addr1[0]==1); +wire bank20_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==20)&&(cdma2buf_wr_addr0[0]==0); +wire bank20_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==20)&&(cdma2buf_wr_addr1[0]==0); +wire bank20_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==20)&&(cdma2buf_wr_addr0[0]==1); +wire bank20_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==20)&&(cdma2buf_wr_addr1[0]==1); +wire bank21_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==21)&&(cdma2buf_wr_addr0[0]==0); +wire bank21_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==21)&&(cdma2buf_wr_addr1[0]==0); +wire bank21_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==21)&&(cdma2buf_wr_addr0[0]==1); +wire bank21_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==21)&&(cdma2buf_wr_addr1[0]==1); +wire bank22_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==22)&&(cdma2buf_wr_addr0[0]==0); +wire bank22_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==22)&&(cdma2buf_wr_addr1[0]==0); +wire bank22_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==22)&&(cdma2buf_wr_addr0[0]==1); +wire bank22_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==22)&&(cdma2buf_wr_addr1[0]==1); +wire bank23_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==23)&&(cdma2buf_wr_addr0[0]==0); +wire bank23_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==23)&&(cdma2buf_wr_addr1[0]==0); +wire bank23_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==23)&&(cdma2buf_wr_addr0[0]==1); +wire bank23_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==23)&&(cdma2buf_wr_addr1[0]==1); +wire bank24_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==24)&&(cdma2buf_wr_addr0[0]==0); +wire bank24_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==24)&&(cdma2buf_wr_addr1[0]==0); +wire bank24_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==24)&&(cdma2buf_wr_addr0[0]==1); +wire bank24_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==24)&&(cdma2buf_wr_addr1[0]==1); +wire bank25_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==25)&&(cdma2buf_wr_addr0[0]==0); +wire bank25_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==25)&&(cdma2buf_wr_addr1[0]==0); +wire bank25_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==25)&&(cdma2buf_wr_addr0[0]==1); +wire bank25_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==25)&&(cdma2buf_wr_addr1[0]==1); +wire bank26_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==26)&&(cdma2buf_wr_addr0[0]==0); +wire bank26_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==26)&&(cdma2buf_wr_addr1[0]==0); +wire bank26_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==26)&&(cdma2buf_wr_addr0[0]==1); +wire bank26_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==26)&&(cdma2buf_wr_addr1[0]==1); +wire bank27_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==27)&&(cdma2buf_wr_addr0[0]==0); +wire bank27_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==27)&&(cdma2buf_wr_addr1[0]==0); +wire bank27_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==27)&&(cdma2buf_wr_addr0[0]==1); +wire bank27_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==27)&&(cdma2buf_wr_addr1[0]==1); +wire bank28_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==28)&&(cdma2buf_wr_addr0[0]==0); +wire bank28_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==28)&&(cdma2buf_wr_addr1[0]==0); +wire bank28_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==28)&&(cdma2buf_wr_addr0[0]==1); +wire bank28_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==28)&&(cdma2buf_wr_addr1[0]==1); +wire bank29_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==29)&&(cdma2buf_wr_addr0[0]==0); +wire bank29_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==29)&&(cdma2buf_wr_addr1[0]==0); +wire bank29_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==29)&&(cdma2buf_wr_addr0[0]==1); +wire bank29_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==29)&&(cdma2buf_wr_addr1[0]==1); +wire bank30_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==30)&&(cdma2buf_wr_addr0[0]==0); +wire bank30_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==30)&&(cdma2buf_wr_addr1[0]==0); +wire bank30_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==30)&&(cdma2buf_wr_addr0[0]==1); +wire bank30_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==30)&&(cdma2buf_wr_addr1[0]==1); +wire bank31_ram0_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==31)&&(cdma2buf_wr_addr0[0]==0); +wire bank31_ram0_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==31)&&(cdma2buf_wr_addr1[0]==0); +wire bank31_ram1_wr0_en_d0 = cdma2buf_wr_en0&&(cdma2buf_wr_addr0[13:9]==31)&&(cdma2buf_wr_addr0[0]==1); +wire bank31_ram1_wr1_en_d0 = cdma2buf_wr_en1&&(cdma2buf_wr_addr1[13:9]==31)&&(cdma2buf_wr_addr1[0]==1); +//| eperl: generated_end (DO NOT EDIT ABOVE) +//generate sram write en +//: my $t1=""; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: for(my $i=0; $i<2; $i++){ +//: ${t1} .= "bank${j}_ram${k}_wr${i}_en_d0 |"; +//: } +//: print "wire bank${j}_ram${k}_wr_en_d0 = ${t1}"."1'b0; \n"; +//: $t1=""; +//: &eperl::flop("-q bank${j}_ram${k}_wr_en_d1 -d bank${j}_ram${k}_wr_en_d0"); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire bank0_ram0_wr_en_d0 = bank0_ram0_wr0_en_d0 |bank0_ram0_wr1_en_d0 |1'b0; +reg bank0_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_wr_en_d1 <= 'b0; + end else begin + bank0_ram0_wr_en_d1 <= bank0_ram0_wr_en_d0; + end +end +wire bank0_ram1_wr_en_d0 = bank0_ram1_wr0_en_d0 |bank0_ram1_wr1_en_d0 |1'b0; +reg bank0_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_wr_en_d1 <= 'b0; + end else begin + bank0_ram1_wr_en_d1 <= bank0_ram1_wr_en_d0; + end +end +wire bank1_ram0_wr_en_d0 = bank1_ram0_wr0_en_d0 |bank1_ram0_wr1_en_d0 |1'b0; +reg bank1_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_wr_en_d1 <= 'b0; + end else begin + bank1_ram0_wr_en_d1 <= bank1_ram0_wr_en_d0; + end +end +wire bank1_ram1_wr_en_d0 = bank1_ram1_wr0_en_d0 |bank1_ram1_wr1_en_d0 |1'b0; +reg bank1_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_wr_en_d1 <= 'b0; + end else begin + bank1_ram1_wr_en_d1 <= bank1_ram1_wr_en_d0; + end +end +wire bank2_ram0_wr_en_d0 = bank2_ram0_wr0_en_d0 |bank2_ram0_wr1_en_d0 |1'b0; +reg bank2_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_wr_en_d1 <= 'b0; + end else begin + bank2_ram0_wr_en_d1 <= bank2_ram0_wr_en_d0; + end +end +wire bank2_ram1_wr_en_d0 = bank2_ram1_wr0_en_d0 |bank2_ram1_wr1_en_d0 |1'b0; +reg bank2_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_wr_en_d1 <= 'b0; + end else begin + bank2_ram1_wr_en_d1 <= bank2_ram1_wr_en_d0; + end +end +wire bank3_ram0_wr_en_d0 = bank3_ram0_wr0_en_d0 |bank3_ram0_wr1_en_d0 |1'b0; +reg bank3_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_wr_en_d1 <= 'b0; + end else begin + bank3_ram0_wr_en_d1 <= bank3_ram0_wr_en_d0; + end +end +wire bank3_ram1_wr_en_d0 = bank3_ram1_wr0_en_d0 |bank3_ram1_wr1_en_d0 |1'b0; +reg bank3_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_wr_en_d1 <= 'b0; + end else begin + bank3_ram1_wr_en_d1 <= bank3_ram1_wr_en_d0; + end +end +wire bank4_ram0_wr_en_d0 = bank4_ram0_wr0_en_d0 |bank4_ram0_wr1_en_d0 |1'b0; +reg bank4_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_wr_en_d1 <= 'b0; + end else begin + bank4_ram0_wr_en_d1 <= bank4_ram0_wr_en_d0; + end +end +wire bank4_ram1_wr_en_d0 = bank4_ram1_wr0_en_d0 |bank4_ram1_wr1_en_d0 |1'b0; +reg bank4_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_wr_en_d1 <= 'b0; + end else begin + bank4_ram1_wr_en_d1 <= bank4_ram1_wr_en_d0; + end +end +wire bank5_ram0_wr_en_d0 = bank5_ram0_wr0_en_d0 |bank5_ram0_wr1_en_d0 |1'b0; +reg bank5_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_wr_en_d1 <= 'b0; + end else begin + bank5_ram0_wr_en_d1 <= bank5_ram0_wr_en_d0; + end +end +wire bank5_ram1_wr_en_d0 = bank5_ram1_wr0_en_d0 |bank5_ram1_wr1_en_d0 |1'b0; +reg bank5_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_wr_en_d1 <= 'b0; + end else begin + bank5_ram1_wr_en_d1 <= bank5_ram1_wr_en_d0; + end +end +wire bank6_ram0_wr_en_d0 = bank6_ram0_wr0_en_d0 |bank6_ram0_wr1_en_d0 |1'b0; +reg bank6_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_wr_en_d1 <= 'b0; + end else begin + bank6_ram0_wr_en_d1 <= bank6_ram0_wr_en_d0; + end +end +wire bank6_ram1_wr_en_d0 = bank6_ram1_wr0_en_d0 |bank6_ram1_wr1_en_d0 |1'b0; +reg bank6_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_wr_en_d1 <= 'b0; + end else begin + bank6_ram1_wr_en_d1 <= bank6_ram1_wr_en_d0; + end +end +wire bank7_ram0_wr_en_d0 = bank7_ram0_wr0_en_d0 |bank7_ram0_wr1_en_d0 |1'b0; +reg bank7_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_wr_en_d1 <= 'b0; + end else begin + bank7_ram0_wr_en_d1 <= bank7_ram0_wr_en_d0; + end +end +wire bank7_ram1_wr_en_d0 = bank7_ram1_wr0_en_d0 |bank7_ram1_wr1_en_d0 |1'b0; +reg bank7_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_wr_en_d1 <= 'b0; + end else begin + bank7_ram1_wr_en_d1 <= bank7_ram1_wr_en_d0; + end +end +wire bank8_ram0_wr_en_d0 = bank8_ram0_wr0_en_d0 |bank8_ram0_wr1_en_d0 |1'b0; +reg bank8_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_wr_en_d1 <= 'b0; + end else begin + bank8_ram0_wr_en_d1 <= bank8_ram0_wr_en_d0; + end +end +wire bank8_ram1_wr_en_d0 = bank8_ram1_wr0_en_d0 |bank8_ram1_wr1_en_d0 |1'b0; +reg bank8_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_wr_en_d1 <= 'b0; + end else begin + bank8_ram1_wr_en_d1 <= bank8_ram1_wr_en_d0; + end +end +wire bank9_ram0_wr_en_d0 = bank9_ram0_wr0_en_d0 |bank9_ram0_wr1_en_d0 |1'b0; +reg bank9_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_wr_en_d1 <= 'b0; + end else begin + bank9_ram0_wr_en_d1 <= bank9_ram0_wr_en_d0; + end +end +wire bank9_ram1_wr_en_d0 = bank9_ram1_wr0_en_d0 |bank9_ram1_wr1_en_d0 |1'b0; +reg bank9_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_wr_en_d1 <= 'b0; + end else begin + bank9_ram1_wr_en_d1 <= bank9_ram1_wr_en_d0; + end +end +wire bank10_ram0_wr_en_d0 = bank10_ram0_wr0_en_d0 |bank10_ram0_wr1_en_d0 |1'b0; +reg bank10_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_wr_en_d1 <= 'b0; + end else begin + bank10_ram0_wr_en_d1 <= bank10_ram0_wr_en_d0; + end +end +wire bank10_ram1_wr_en_d0 = bank10_ram1_wr0_en_d0 |bank10_ram1_wr1_en_d0 |1'b0; +reg bank10_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_wr_en_d1 <= 'b0; + end else begin + bank10_ram1_wr_en_d1 <= bank10_ram1_wr_en_d0; + end +end +wire bank11_ram0_wr_en_d0 = bank11_ram0_wr0_en_d0 |bank11_ram0_wr1_en_d0 |1'b0; +reg bank11_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_wr_en_d1 <= 'b0; + end else begin + bank11_ram0_wr_en_d1 <= bank11_ram0_wr_en_d0; + end +end +wire bank11_ram1_wr_en_d0 = bank11_ram1_wr0_en_d0 |bank11_ram1_wr1_en_d0 |1'b0; +reg bank11_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_wr_en_d1 <= 'b0; + end else begin + bank11_ram1_wr_en_d1 <= bank11_ram1_wr_en_d0; + end +end +wire bank12_ram0_wr_en_d0 = bank12_ram0_wr0_en_d0 |bank12_ram0_wr1_en_d0 |1'b0; +reg bank12_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_wr_en_d1 <= 'b0; + end else begin + bank12_ram0_wr_en_d1 <= bank12_ram0_wr_en_d0; + end +end +wire bank12_ram1_wr_en_d0 = bank12_ram1_wr0_en_d0 |bank12_ram1_wr1_en_d0 |1'b0; +reg bank12_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_wr_en_d1 <= 'b0; + end else begin + bank12_ram1_wr_en_d1 <= bank12_ram1_wr_en_d0; + end +end +wire bank13_ram0_wr_en_d0 = bank13_ram0_wr0_en_d0 |bank13_ram0_wr1_en_d0 |1'b0; +reg bank13_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_wr_en_d1 <= 'b0; + end else begin + bank13_ram0_wr_en_d1 <= bank13_ram0_wr_en_d0; + end +end +wire bank13_ram1_wr_en_d0 = bank13_ram1_wr0_en_d0 |bank13_ram1_wr1_en_d0 |1'b0; +reg bank13_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_wr_en_d1 <= 'b0; + end else begin + bank13_ram1_wr_en_d1 <= bank13_ram1_wr_en_d0; + end +end +wire bank14_ram0_wr_en_d0 = bank14_ram0_wr0_en_d0 |bank14_ram0_wr1_en_d0 |1'b0; +reg bank14_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_wr_en_d1 <= 'b0; + end else begin + bank14_ram0_wr_en_d1 <= bank14_ram0_wr_en_d0; + end +end +wire bank14_ram1_wr_en_d0 = bank14_ram1_wr0_en_d0 |bank14_ram1_wr1_en_d0 |1'b0; +reg bank14_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_wr_en_d1 <= 'b0; + end else begin + bank14_ram1_wr_en_d1 <= bank14_ram1_wr_en_d0; + end +end +wire bank15_ram0_wr_en_d0 = bank15_ram0_wr0_en_d0 |bank15_ram0_wr1_en_d0 |1'b0; +reg bank15_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_wr_en_d1 <= 'b0; + end else begin + bank15_ram0_wr_en_d1 <= bank15_ram0_wr_en_d0; + end +end +wire bank15_ram1_wr_en_d0 = bank15_ram1_wr0_en_d0 |bank15_ram1_wr1_en_d0 |1'b0; +reg bank15_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_wr_en_d1 <= 'b0; + end else begin + bank15_ram1_wr_en_d1 <= bank15_ram1_wr_en_d0; + end +end +wire bank16_ram0_wr_en_d0 = bank16_ram0_wr0_en_d0 |bank16_ram0_wr1_en_d0 |1'b0; +reg bank16_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_wr_en_d1 <= 'b0; + end else begin + bank16_ram0_wr_en_d1 <= bank16_ram0_wr_en_d0; + end +end +wire bank16_ram1_wr_en_d0 = bank16_ram1_wr0_en_d0 |bank16_ram1_wr1_en_d0 |1'b0; +reg bank16_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_wr_en_d1 <= 'b0; + end else begin + bank16_ram1_wr_en_d1 <= bank16_ram1_wr_en_d0; + end +end +wire bank17_ram0_wr_en_d0 = bank17_ram0_wr0_en_d0 |bank17_ram0_wr1_en_d0 |1'b0; +reg bank17_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_wr_en_d1 <= 'b0; + end else begin + bank17_ram0_wr_en_d1 <= bank17_ram0_wr_en_d0; + end +end +wire bank17_ram1_wr_en_d0 = bank17_ram1_wr0_en_d0 |bank17_ram1_wr1_en_d0 |1'b0; +reg bank17_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_wr_en_d1 <= 'b0; + end else begin + bank17_ram1_wr_en_d1 <= bank17_ram1_wr_en_d0; + end +end +wire bank18_ram0_wr_en_d0 = bank18_ram0_wr0_en_d0 |bank18_ram0_wr1_en_d0 |1'b0; +reg bank18_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_wr_en_d1 <= 'b0; + end else begin + bank18_ram0_wr_en_d1 <= bank18_ram0_wr_en_d0; + end +end +wire bank18_ram1_wr_en_d0 = bank18_ram1_wr0_en_d0 |bank18_ram1_wr1_en_d0 |1'b0; +reg bank18_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_wr_en_d1 <= 'b0; + end else begin + bank18_ram1_wr_en_d1 <= bank18_ram1_wr_en_d0; + end +end +wire bank19_ram0_wr_en_d0 = bank19_ram0_wr0_en_d0 |bank19_ram0_wr1_en_d0 |1'b0; +reg bank19_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_wr_en_d1 <= 'b0; + end else begin + bank19_ram0_wr_en_d1 <= bank19_ram0_wr_en_d0; + end +end +wire bank19_ram1_wr_en_d0 = bank19_ram1_wr0_en_d0 |bank19_ram1_wr1_en_d0 |1'b0; +reg bank19_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_wr_en_d1 <= 'b0; + end else begin + bank19_ram1_wr_en_d1 <= bank19_ram1_wr_en_d0; + end +end +wire bank20_ram0_wr_en_d0 = bank20_ram0_wr0_en_d0 |bank20_ram0_wr1_en_d0 |1'b0; +reg bank20_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_wr_en_d1 <= 'b0; + end else begin + bank20_ram0_wr_en_d1 <= bank20_ram0_wr_en_d0; + end +end +wire bank20_ram1_wr_en_d0 = bank20_ram1_wr0_en_d0 |bank20_ram1_wr1_en_d0 |1'b0; +reg bank20_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_wr_en_d1 <= 'b0; + end else begin + bank20_ram1_wr_en_d1 <= bank20_ram1_wr_en_d0; + end +end +wire bank21_ram0_wr_en_d0 = bank21_ram0_wr0_en_d0 |bank21_ram0_wr1_en_d0 |1'b0; +reg bank21_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_wr_en_d1 <= 'b0; + end else begin + bank21_ram0_wr_en_d1 <= bank21_ram0_wr_en_d0; + end +end +wire bank21_ram1_wr_en_d0 = bank21_ram1_wr0_en_d0 |bank21_ram1_wr1_en_d0 |1'b0; +reg bank21_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_wr_en_d1 <= 'b0; + end else begin + bank21_ram1_wr_en_d1 <= bank21_ram1_wr_en_d0; + end +end +wire bank22_ram0_wr_en_d0 = bank22_ram0_wr0_en_d0 |bank22_ram0_wr1_en_d0 |1'b0; +reg bank22_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_wr_en_d1 <= 'b0; + end else begin + bank22_ram0_wr_en_d1 <= bank22_ram0_wr_en_d0; + end +end +wire bank22_ram1_wr_en_d0 = bank22_ram1_wr0_en_d0 |bank22_ram1_wr1_en_d0 |1'b0; +reg bank22_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_wr_en_d1 <= 'b0; + end else begin + bank22_ram1_wr_en_d1 <= bank22_ram1_wr_en_d0; + end +end +wire bank23_ram0_wr_en_d0 = bank23_ram0_wr0_en_d0 |bank23_ram0_wr1_en_d0 |1'b0; +reg bank23_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_wr_en_d1 <= 'b0; + end else begin + bank23_ram0_wr_en_d1 <= bank23_ram0_wr_en_d0; + end +end +wire bank23_ram1_wr_en_d0 = bank23_ram1_wr0_en_d0 |bank23_ram1_wr1_en_d0 |1'b0; +reg bank23_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_wr_en_d1 <= 'b0; + end else begin + bank23_ram1_wr_en_d1 <= bank23_ram1_wr_en_d0; + end +end +wire bank24_ram0_wr_en_d0 = bank24_ram0_wr0_en_d0 |bank24_ram0_wr1_en_d0 |1'b0; +reg bank24_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_wr_en_d1 <= 'b0; + end else begin + bank24_ram0_wr_en_d1 <= bank24_ram0_wr_en_d0; + end +end +wire bank24_ram1_wr_en_d0 = bank24_ram1_wr0_en_d0 |bank24_ram1_wr1_en_d0 |1'b0; +reg bank24_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_wr_en_d1 <= 'b0; + end else begin + bank24_ram1_wr_en_d1 <= bank24_ram1_wr_en_d0; + end +end +wire bank25_ram0_wr_en_d0 = bank25_ram0_wr0_en_d0 |bank25_ram0_wr1_en_d0 |1'b0; +reg bank25_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_wr_en_d1 <= 'b0; + end else begin + bank25_ram0_wr_en_d1 <= bank25_ram0_wr_en_d0; + end +end +wire bank25_ram1_wr_en_d0 = bank25_ram1_wr0_en_d0 |bank25_ram1_wr1_en_d0 |1'b0; +reg bank25_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_wr_en_d1 <= 'b0; + end else begin + bank25_ram1_wr_en_d1 <= bank25_ram1_wr_en_d0; + end +end +wire bank26_ram0_wr_en_d0 = bank26_ram0_wr0_en_d0 |bank26_ram0_wr1_en_d0 |1'b0; +reg bank26_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_wr_en_d1 <= 'b0; + end else begin + bank26_ram0_wr_en_d1 <= bank26_ram0_wr_en_d0; + end +end +wire bank26_ram1_wr_en_d0 = bank26_ram1_wr0_en_d0 |bank26_ram1_wr1_en_d0 |1'b0; +reg bank26_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_wr_en_d1 <= 'b0; + end else begin + bank26_ram1_wr_en_d1 <= bank26_ram1_wr_en_d0; + end +end +wire bank27_ram0_wr_en_d0 = bank27_ram0_wr0_en_d0 |bank27_ram0_wr1_en_d0 |1'b0; +reg bank27_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_wr_en_d1 <= 'b0; + end else begin + bank27_ram0_wr_en_d1 <= bank27_ram0_wr_en_d0; + end +end +wire bank27_ram1_wr_en_d0 = bank27_ram1_wr0_en_d0 |bank27_ram1_wr1_en_d0 |1'b0; +reg bank27_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_wr_en_d1 <= 'b0; + end else begin + bank27_ram1_wr_en_d1 <= bank27_ram1_wr_en_d0; + end +end +wire bank28_ram0_wr_en_d0 = bank28_ram0_wr0_en_d0 |bank28_ram0_wr1_en_d0 |1'b0; +reg bank28_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_wr_en_d1 <= 'b0; + end else begin + bank28_ram0_wr_en_d1 <= bank28_ram0_wr_en_d0; + end +end +wire bank28_ram1_wr_en_d0 = bank28_ram1_wr0_en_d0 |bank28_ram1_wr1_en_d0 |1'b0; +reg bank28_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_wr_en_d1 <= 'b0; + end else begin + bank28_ram1_wr_en_d1 <= bank28_ram1_wr_en_d0; + end +end +wire bank29_ram0_wr_en_d0 = bank29_ram0_wr0_en_d0 |bank29_ram0_wr1_en_d0 |1'b0; +reg bank29_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_wr_en_d1 <= 'b0; + end else begin + bank29_ram0_wr_en_d1 <= bank29_ram0_wr_en_d0; + end +end +wire bank29_ram1_wr_en_d0 = bank29_ram1_wr0_en_d0 |bank29_ram1_wr1_en_d0 |1'b0; +reg bank29_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_wr_en_d1 <= 'b0; + end else begin + bank29_ram1_wr_en_d1 <= bank29_ram1_wr_en_d0; + end +end +wire bank30_ram0_wr_en_d0 = bank30_ram0_wr0_en_d0 |bank30_ram0_wr1_en_d0 |1'b0; +reg bank30_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_wr_en_d1 <= 'b0; + end else begin + bank30_ram0_wr_en_d1 <= bank30_ram0_wr_en_d0; + end +end +wire bank30_ram1_wr_en_d0 = bank30_ram1_wr0_en_d0 |bank30_ram1_wr1_en_d0 |1'b0; +reg bank30_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_wr_en_d1 <= 'b0; + end else begin + bank30_ram1_wr_en_d1 <= bank30_ram1_wr_en_d0; + end +end +wire bank31_ram0_wr_en_d0 = bank31_ram0_wr0_en_d0 |bank31_ram0_wr1_en_d0 |1'b0; +reg bank31_ram0_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_wr_en_d1 <= 'b0; + end else begin + bank31_ram0_wr_en_d1 <= bank31_ram0_wr_en_d0; + end +end +wire bank31_ram1_wr_en_d0 = bank31_ram1_wr0_en_d0 |bank31_ram1_wr1_en_d0 |1'b0; +reg bank31_ram1_wr_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_wr_en_d1 <= 'b0; + end else begin + bank31_ram1_wr_en_d1 <= bank31_ram1_wr_en_d0; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// 1 pipe for timing +//: my $kk=14; +//: my $jj=64; +//: for(my $i=0; $i<2 ; $i++){ +//: &eperl::flop("-wid ${kk} -q cdma2buf_wr_addr${i}_d1 -d cdma2buf_wr_addr${i}"); +//: &eperl::flop("-wid ${jj} -norst -q cdma2buf_wr_data${i}_d1 -d cdma2buf_wr_data${i}"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [13:0] cdma2buf_wr_addr0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2buf_wr_addr0_d1 <= 'b0; + end else begin + cdma2buf_wr_addr0_d1 <= cdma2buf_wr_addr0; + end +end +reg [63:0] cdma2buf_wr_data0_d1; +always @(posedge nvdla_core_clk) begin + cdma2buf_wr_data0_d1 <= cdma2buf_wr_data0; +end +reg [13:0] cdma2buf_wr_addr1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2buf_wr_addr1_d1 <= 'b0; + end else begin + cdma2buf_wr_addr1_d1 <= cdma2buf_wr_addr1; + end +end +reg [63:0] cdma2buf_wr_data1_d1; +always @(posedge nvdla_core_clk) begin + cdma2buf_wr_data1_d1 <= cdma2buf_wr_data1; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//generate bank write en +//: my $t1=""; +//: for(my $i=0; $i<2; $i++){ +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2; $k++){ +//: $t1 .= "bank${j}_ram${k}_wr${i}_en_d0 |"; +//: } +//: print "wire bank${j}_wr${i}_en_d0 = ${t1}"."1'b0; \n"; +//: &eperl::flop("-q bank${j}_wr${i}_en_d1 -d bank${j}_wr${i}_en_d0"); +//: $t1=""; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire bank0_wr0_en_d0 = bank0_ram0_wr0_en_d0 |bank0_ram1_wr0_en_d0 |1'b0; +reg bank0_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_wr0_en_d1 <= 'b0; + end else begin + bank0_wr0_en_d1 <= bank0_wr0_en_d0; + end +end +wire bank1_wr0_en_d0 = bank1_ram0_wr0_en_d0 |bank1_ram1_wr0_en_d0 |1'b0; +reg bank1_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_wr0_en_d1 <= 'b0; + end else begin + bank1_wr0_en_d1 <= bank1_wr0_en_d0; + end +end +wire bank2_wr0_en_d0 = bank2_ram0_wr0_en_d0 |bank2_ram1_wr0_en_d0 |1'b0; +reg bank2_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_wr0_en_d1 <= 'b0; + end else begin + bank2_wr0_en_d1 <= bank2_wr0_en_d0; + end +end +wire bank3_wr0_en_d0 = bank3_ram0_wr0_en_d0 |bank3_ram1_wr0_en_d0 |1'b0; +reg bank3_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_wr0_en_d1 <= 'b0; + end else begin + bank3_wr0_en_d1 <= bank3_wr0_en_d0; + end +end +wire bank4_wr0_en_d0 = bank4_ram0_wr0_en_d0 |bank4_ram1_wr0_en_d0 |1'b0; +reg bank4_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_wr0_en_d1 <= 'b0; + end else begin + bank4_wr0_en_d1 <= bank4_wr0_en_d0; + end +end +wire bank5_wr0_en_d0 = bank5_ram0_wr0_en_d0 |bank5_ram1_wr0_en_d0 |1'b0; +reg bank5_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_wr0_en_d1 <= 'b0; + end else begin + bank5_wr0_en_d1 <= bank5_wr0_en_d0; + end +end +wire bank6_wr0_en_d0 = bank6_ram0_wr0_en_d0 |bank6_ram1_wr0_en_d0 |1'b0; +reg bank6_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_wr0_en_d1 <= 'b0; + end else begin + bank6_wr0_en_d1 <= bank6_wr0_en_d0; + end +end +wire bank7_wr0_en_d0 = bank7_ram0_wr0_en_d0 |bank7_ram1_wr0_en_d0 |1'b0; +reg bank7_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_wr0_en_d1 <= 'b0; + end else begin + bank7_wr0_en_d1 <= bank7_wr0_en_d0; + end +end +wire bank8_wr0_en_d0 = bank8_ram0_wr0_en_d0 |bank8_ram1_wr0_en_d0 |1'b0; +reg bank8_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_wr0_en_d1 <= 'b0; + end else begin + bank8_wr0_en_d1 <= bank8_wr0_en_d0; + end +end +wire bank9_wr0_en_d0 = bank9_ram0_wr0_en_d0 |bank9_ram1_wr0_en_d0 |1'b0; +reg bank9_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_wr0_en_d1 <= 'b0; + end else begin + bank9_wr0_en_d1 <= bank9_wr0_en_d0; + end +end +wire bank10_wr0_en_d0 = bank10_ram0_wr0_en_d0 |bank10_ram1_wr0_en_d0 |1'b0; +reg bank10_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_wr0_en_d1 <= 'b0; + end else begin + bank10_wr0_en_d1 <= bank10_wr0_en_d0; + end +end +wire bank11_wr0_en_d0 = bank11_ram0_wr0_en_d0 |bank11_ram1_wr0_en_d0 |1'b0; +reg bank11_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_wr0_en_d1 <= 'b0; + end else begin + bank11_wr0_en_d1 <= bank11_wr0_en_d0; + end +end +wire bank12_wr0_en_d0 = bank12_ram0_wr0_en_d0 |bank12_ram1_wr0_en_d0 |1'b0; +reg bank12_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_wr0_en_d1 <= 'b0; + end else begin + bank12_wr0_en_d1 <= bank12_wr0_en_d0; + end +end +wire bank13_wr0_en_d0 = bank13_ram0_wr0_en_d0 |bank13_ram1_wr0_en_d0 |1'b0; +reg bank13_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_wr0_en_d1 <= 'b0; + end else begin + bank13_wr0_en_d1 <= bank13_wr0_en_d0; + end +end +wire bank14_wr0_en_d0 = bank14_ram0_wr0_en_d0 |bank14_ram1_wr0_en_d0 |1'b0; +reg bank14_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_wr0_en_d1 <= 'b0; + end else begin + bank14_wr0_en_d1 <= bank14_wr0_en_d0; + end +end +wire bank15_wr0_en_d0 = bank15_ram0_wr0_en_d0 |bank15_ram1_wr0_en_d0 |1'b0; +reg bank15_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_wr0_en_d1 <= 'b0; + end else begin + bank15_wr0_en_d1 <= bank15_wr0_en_d0; + end +end +wire bank16_wr0_en_d0 = bank16_ram0_wr0_en_d0 |bank16_ram1_wr0_en_d0 |1'b0; +reg bank16_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_wr0_en_d1 <= 'b0; + end else begin + bank16_wr0_en_d1 <= bank16_wr0_en_d0; + end +end +wire bank17_wr0_en_d0 = bank17_ram0_wr0_en_d0 |bank17_ram1_wr0_en_d0 |1'b0; +reg bank17_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_wr0_en_d1 <= 'b0; + end else begin + bank17_wr0_en_d1 <= bank17_wr0_en_d0; + end +end +wire bank18_wr0_en_d0 = bank18_ram0_wr0_en_d0 |bank18_ram1_wr0_en_d0 |1'b0; +reg bank18_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_wr0_en_d1 <= 'b0; + end else begin + bank18_wr0_en_d1 <= bank18_wr0_en_d0; + end +end +wire bank19_wr0_en_d0 = bank19_ram0_wr0_en_d0 |bank19_ram1_wr0_en_d0 |1'b0; +reg bank19_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_wr0_en_d1 <= 'b0; + end else begin + bank19_wr0_en_d1 <= bank19_wr0_en_d0; + end +end +wire bank20_wr0_en_d0 = bank20_ram0_wr0_en_d0 |bank20_ram1_wr0_en_d0 |1'b0; +reg bank20_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_wr0_en_d1 <= 'b0; + end else begin + bank20_wr0_en_d1 <= bank20_wr0_en_d0; + end +end +wire bank21_wr0_en_d0 = bank21_ram0_wr0_en_d0 |bank21_ram1_wr0_en_d0 |1'b0; +reg bank21_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_wr0_en_d1 <= 'b0; + end else begin + bank21_wr0_en_d1 <= bank21_wr0_en_d0; + end +end +wire bank22_wr0_en_d0 = bank22_ram0_wr0_en_d0 |bank22_ram1_wr0_en_d0 |1'b0; +reg bank22_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_wr0_en_d1 <= 'b0; + end else begin + bank22_wr0_en_d1 <= bank22_wr0_en_d0; + end +end +wire bank23_wr0_en_d0 = bank23_ram0_wr0_en_d0 |bank23_ram1_wr0_en_d0 |1'b0; +reg bank23_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_wr0_en_d1 <= 'b0; + end else begin + bank23_wr0_en_d1 <= bank23_wr0_en_d0; + end +end +wire bank24_wr0_en_d0 = bank24_ram0_wr0_en_d0 |bank24_ram1_wr0_en_d0 |1'b0; +reg bank24_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_wr0_en_d1 <= 'b0; + end else begin + bank24_wr0_en_d1 <= bank24_wr0_en_d0; + end +end +wire bank25_wr0_en_d0 = bank25_ram0_wr0_en_d0 |bank25_ram1_wr0_en_d0 |1'b0; +reg bank25_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_wr0_en_d1 <= 'b0; + end else begin + bank25_wr0_en_d1 <= bank25_wr0_en_d0; + end +end +wire bank26_wr0_en_d0 = bank26_ram0_wr0_en_d0 |bank26_ram1_wr0_en_d0 |1'b0; +reg bank26_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_wr0_en_d1 <= 'b0; + end else begin + bank26_wr0_en_d1 <= bank26_wr0_en_d0; + end +end +wire bank27_wr0_en_d0 = bank27_ram0_wr0_en_d0 |bank27_ram1_wr0_en_d0 |1'b0; +reg bank27_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_wr0_en_d1 <= 'b0; + end else begin + bank27_wr0_en_d1 <= bank27_wr0_en_d0; + end +end +wire bank28_wr0_en_d0 = bank28_ram0_wr0_en_d0 |bank28_ram1_wr0_en_d0 |1'b0; +reg bank28_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_wr0_en_d1 <= 'b0; + end else begin + bank28_wr0_en_d1 <= bank28_wr0_en_d0; + end +end +wire bank29_wr0_en_d0 = bank29_ram0_wr0_en_d0 |bank29_ram1_wr0_en_d0 |1'b0; +reg bank29_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_wr0_en_d1 <= 'b0; + end else begin + bank29_wr0_en_d1 <= bank29_wr0_en_d0; + end +end +wire bank30_wr0_en_d0 = bank30_ram0_wr0_en_d0 |bank30_ram1_wr0_en_d0 |1'b0; +reg bank30_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_wr0_en_d1 <= 'b0; + end else begin + bank30_wr0_en_d1 <= bank30_wr0_en_d0; + end +end +wire bank31_wr0_en_d0 = bank31_ram0_wr0_en_d0 |bank31_ram1_wr0_en_d0 |1'b0; +reg bank31_wr0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_wr0_en_d1 <= 'b0; + end else begin + bank31_wr0_en_d1 <= bank31_wr0_en_d0; + end +end +wire bank0_wr1_en_d0 = bank0_ram0_wr1_en_d0 |bank0_ram1_wr1_en_d0 |1'b0; +reg bank0_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_wr1_en_d1 <= 'b0; + end else begin + bank0_wr1_en_d1 <= bank0_wr1_en_d0; + end +end +wire bank1_wr1_en_d0 = bank1_ram0_wr1_en_d0 |bank1_ram1_wr1_en_d0 |1'b0; +reg bank1_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_wr1_en_d1 <= 'b0; + end else begin + bank1_wr1_en_d1 <= bank1_wr1_en_d0; + end +end +wire bank2_wr1_en_d0 = bank2_ram0_wr1_en_d0 |bank2_ram1_wr1_en_d0 |1'b0; +reg bank2_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_wr1_en_d1 <= 'b0; + end else begin + bank2_wr1_en_d1 <= bank2_wr1_en_d0; + end +end +wire bank3_wr1_en_d0 = bank3_ram0_wr1_en_d0 |bank3_ram1_wr1_en_d0 |1'b0; +reg bank3_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_wr1_en_d1 <= 'b0; + end else begin + bank3_wr1_en_d1 <= bank3_wr1_en_d0; + end +end +wire bank4_wr1_en_d0 = bank4_ram0_wr1_en_d0 |bank4_ram1_wr1_en_d0 |1'b0; +reg bank4_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_wr1_en_d1 <= 'b0; + end else begin + bank4_wr1_en_d1 <= bank4_wr1_en_d0; + end +end +wire bank5_wr1_en_d0 = bank5_ram0_wr1_en_d0 |bank5_ram1_wr1_en_d0 |1'b0; +reg bank5_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_wr1_en_d1 <= 'b0; + end else begin + bank5_wr1_en_d1 <= bank5_wr1_en_d0; + end +end +wire bank6_wr1_en_d0 = bank6_ram0_wr1_en_d0 |bank6_ram1_wr1_en_d0 |1'b0; +reg bank6_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_wr1_en_d1 <= 'b0; + end else begin + bank6_wr1_en_d1 <= bank6_wr1_en_d0; + end +end +wire bank7_wr1_en_d0 = bank7_ram0_wr1_en_d0 |bank7_ram1_wr1_en_d0 |1'b0; +reg bank7_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_wr1_en_d1 <= 'b0; + end else begin + bank7_wr1_en_d1 <= bank7_wr1_en_d0; + end +end +wire bank8_wr1_en_d0 = bank8_ram0_wr1_en_d0 |bank8_ram1_wr1_en_d0 |1'b0; +reg bank8_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_wr1_en_d1 <= 'b0; + end else begin + bank8_wr1_en_d1 <= bank8_wr1_en_d0; + end +end +wire bank9_wr1_en_d0 = bank9_ram0_wr1_en_d0 |bank9_ram1_wr1_en_d0 |1'b0; +reg bank9_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_wr1_en_d1 <= 'b0; + end else begin + bank9_wr1_en_d1 <= bank9_wr1_en_d0; + end +end +wire bank10_wr1_en_d0 = bank10_ram0_wr1_en_d0 |bank10_ram1_wr1_en_d0 |1'b0; +reg bank10_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_wr1_en_d1 <= 'b0; + end else begin + bank10_wr1_en_d1 <= bank10_wr1_en_d0; + end +end +wire bank11_wr1_en_d0 = bank11_ram0_wr1_en_d0 |bank11_ram1_wr1_en_d0 |1'b0; +reg bank11_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_wr1_en_d1 <= 'b0; + end else begin + bank11_wr1_en_d1 <= bank11_wr1_en_d0; + end +end +wire bank12_wr1_en_d0 = bank12_ram0_wr1_en_d0 |bank12_ram1_wr1_en_d0 |1'b0; +reg bank12_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_wr1_en_d1 <= 'b0; + end else begin + bank12_wr1_en_d1 <= bank12_wr1_en_d0; + end +end +wire bank13_wr1_en_d0 = bank13_ram0_wr1_en_d0 |bank13_ram1_wr1_en_d0 |1'b0; +reg bank13_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_wr1_en_d1 <= 'b0; + end else begin + bank13_wr1_en_d1 <= bank13_wr1_en_d0; + end +end +wire bank14_wr1_en_d0 = bank14_ram0_wr1_en_d0 |bank14_ram1_wr1_en_d0 |1'b0; +reg bank14_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_wr1_en_d1 <= 'b0; + end else begin + bank14_wr1_en_d1 <= bank14_wr1_en_d0; + end +end +wire bank15_wr1_en_d0 = bank15_ram0_wr1_en_d0 |bank15_ram1_wr1_en_d0 |1'b0; +reg bank15_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_wr1_en_d1 <= 'b0; + end else begin + bank15_wr1_en_d1 <= bank15_wr1_en_d0; + end +end +wire bank16_wr1_en_d0 = bank16_ram0_wr1_en_d0 |bank16_ram1_wr1_en_d0 |1'b0; +reg bank16_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_wr1_en_d1 <= 'b0; + end else begin + bank16_wr1_en_d1 <= bank16_wr1_en_d0; + end +end +wire bank17_wr1_en_d0 = bank17_ram0_wr1_en_d0 |bank17_ram1_wr1_en_d0 |1'b0; +reg bank17_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_wr1_en_d1 <= 'b0; + end else begin + bank17_wr1_en_d1 <= bank17_wr1_en_d0; + end +end +wire bank18_wr1_en_d0 = bank18_ram0_wr1_en_d0 |bank18_ram1_wr1_en_d0 |1'b0; +reg bank18_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_wr1_en_d1 <= 'b0; + end else begin + bank18_wr1_en_d1 <= bank18_wr1_en_d0; + end +end +wire bank19_wr1_en_d0 = bank19_ram0_wr1_en_d0 |bank19_ram1_wr1_en_d0 |1'b0; +reg bank19_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_wr1_en_d1 <= 'b0; + end else begin + bank19_wr1_en_d1 <= bank19_wr1_en_d0; + end +end +wire bank20_wr1_en_d0 = bank20_ram0_wr1_en_d0 |bank20_ram1_wr1_en_d0 |1'b0; +reg bank20_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_wr1_en_d1 <= 'b0; + end else begin + bank20_wr1_en_d1 <= bank20_wr1_en_d0; + end +end +wire bank21_wr1_en_d0 = bank21_ram0_wr1_en_d0 |bank21_ram1_wr1_en_d0 |1'b0; +reg bank21_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_wr1_en_d1 <= 'b0; + end else begin + bank21_wr1_en_d1 <= bank21_wr1_en_d0; + end +end +wire bank22_wr1_en_d0 = bank22_ram0_wr1_en_d0 |bank22_ram1_wr1_en_d0 |1'b0; +reg bank22_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_wr1_en_d1 <= 'b0; + end else begin + bank22_wr1_en_d1 <= bank22_wr1_en_d0; + end +end +wire bank23_wr1_en_d0 = bank23_ram0_wr1_en_d0 |bank23_ram1_wr1_en_d0 |1'b0; +reg bank23_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_wr1_en_d1 <= 'b0; + end else begin + bank23_wr1_en_d1 <= bank23_wr1_en_d0; + end +end +wire bank24_wr1_en_d0 = bank24_ram0_wr1_en_d0 |bank24_ram1_wr1_en_d0 |1'b0; +reg bank24_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_wr1_en_d1 <= 'b0; + end else begin + bank24_wr1_en_d1 <= bank24_wr1_en_d0; + end +end +wire bank25_wr1_en_d0 = bank25_ram0_wr1_en_d0 |bank25_ram1_wr1_en_d0 |1'b0; +reg bank25_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_wr1_en_d1 <= 'b0; + end else begin + bank25_wr1_en_d1 <= bank25_wr1_en_d0; + end +end +wire bank26_wr1_en_d0 = bank26_ram0_wr1_en_d0 |bank26_ram1_wr1_en_d0 |1'b0; +reg bank26_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_wr1_en_d1 <= 'b0; + end else begin + bank26_wr1_en_d1 <= bank26_wr1_en_d0; + end +end +wire bank27_wr1_en_d0 = bank27_ram0_wr1_en_d0 |bank27_ram1_wr1_en_d0 |1'b0; +reg bank27_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_wr1_en_d1 <= 'b0; + end else begin + bank27_wr1_en_d1 <= bank27_wr1_en_d0; + end +end +wire bank28_wr1_en_d0 = bank28_ram0_wr1_en_d0 |bank28_ram1_wr1_en_d0 |1'b0; +reg bank28_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_wr1_en_d1 <= 'b0; + end else begin + bank28_wr1_en_d1 <= bank28_wr1_en_d0; + end +end +wire bank29_wr1_en_d0 = bank29_ram0_wr1_en_d0 |bank29_ram1_wr1_en_d0 |1'b0; +reg bank29_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_wr1_en_d1 <= 'b0; + end else begin + bank29_wr1_en_d1 <= bank29_wr1_en_d0; + end +end +wire bank30_wr1_en_d0 = bank30_ram0_wr1_en_d0 |bank30_ram1_wr1_en_d0 |1'b0; +reg bank30_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_wr1_en_d1 <= 'b0; + end else begin + bank30_wr1_en_d1 <= bank30_wr1_en_d0; + end +end +wire bank31_wr1_en_d0 = bank31_ram0_wr1_en_d0 |bank31_ram1_wr1_en_d0 |1'b0; +reg bank31_wr1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_wr1_en_d1 <= 'b0; + end else begin + bank31_wr1_en_d1 <= bank31_wr1_en_d0; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//generate bank write addr/data +//: my $t1=""; +//: my $d1=""; +//: my $kk= 14; +//: my $jj= 64; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $i=0; $i<2; $i++){ +//: $t1 .="({${kk}{bank${j}_wr${i}_en_d1}}&cdma2buf_wr_addr${i}_d1)|"; +//: $d1 .="({${jj}{bank${j}_wr${i}_en_d1}}&cdma2buf_wr_data${i}_d1)|"; +//: } +//: my $t2 .="{${kk}{1'b0}}"; +//: my $d2 .="{${jj}{1'b0}}"; +//: print "wire [${kk}-1:0] bank${j}_wr_addr_d1 = ${t1}${t2}; \n"; +//: print "wire [${jj}-1:0] bank${j}_wr_data_d1 = ${d1}${d2}; \n"; +//: $t1=""; +//: $d1=""; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [14-1:0] bank0_wr_addr_d1 = ({14{bank0_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank0_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank0_wr_data_d1 = ({64{bank0_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank0_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank1_wr_addr_d1 = ({14{bank1_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank1_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank1_wr_data_d1 = ({64{bank1_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank1_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank2_wr_addr_d1 = ({14{bank2_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank2_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank2_wr_data_d1 = ({64{bank2_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank2_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank3_wr_addr_d1 = ({14{bank3_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank3_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank3_wr_data_d1 = ({64{bank3_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank3_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank4_wr_addr_d1 = ({14{bank4_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank4_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank4_wr_data_d1 = ({64{bank4_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank4_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank5_wr_addr_d1 = ({14{bank5_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank5_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank5_wr_data_d1 = ({64{bank5_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank5_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank6_wr_addr_d1 = ({14{bank6_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank6_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank6_wr_data_d1 = ({64{bank6_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank6_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank7_wr_addr_d1 = ({14{bank7_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank7_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank7_wr_data_d1 = ({64{bank7_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank7_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank8_wr_addr_d1 = ({14{bank8_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank8_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank8_wr_data_d1 = ({64{bank8_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank8_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank9_wr_addr_d1 = ({14{bank9_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank9_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank9_wr_data_d1 = ({64{bank9_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank9_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank10_wr_addr_d1 = ({14{bank10_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank10_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank10_wr_data_d1 = ({64{bank10_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank10_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank11_wr_addr_d1 = ({14{bank11_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank11_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank11_wr_data_d1 = ({64{bank11_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank11_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank12_wr_addr_d1 = ({14{bank12_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank12_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank12_wr_data_d1 = ({64{bank12_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank12_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank13_wr_addr_d1 = ({14{bank13_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank13_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank13_wr_data_d1 = ({64{bank13_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank13_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank14_wr_addr_d1 = ({14{bank14_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank14_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank14_wr_data_d1 = ({64{bank14_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank14_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank15_wr_addr_d1 = ({14{bank15_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank15_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank15_wr_data_d1 = ({64{bank15_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank15_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank16_wr_addr_d1 = ({14{bank16_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank16_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank16_wr_data_d1 = ({64{bank16_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank16_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank17_wr_addr_d1 = ({14{bank17_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank17_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank17_wr_data_d1 = ({64{bank17_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank17_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank18_wr_addr_d1 = ({14{bank18_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank18_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank18_wr_data_d1 = ({64{bank18_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank18_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank19_wr_addr_d1 = ({14{bank19_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank19_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank19_wr_data_d1 = ({64{bank19_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank19_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank20_wr_addr_d1 = ({14{bank20_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank20_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank20_wr_data_d1 = ({64{bank20_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank20_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank21_wr_addr_d1 = ({14{bank21_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank21_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank21_wr_data_d1 = ({64{bank21_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank21_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank22_wr_addr_d1 = ({14{bank22_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank22_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank22_wr_data_d1 = ({64{bank22_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank22_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank23_wr_addr_d1 = ({14{bank23_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank23_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank23_wr_data_d1 = ({64{bank23_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank23_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank24_wr_addr_d1 = ({14{bank24_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank24_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank24_wr_data_d1 = ({64{bank24_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank24_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank25_wr_addr_d1 = ({14{bank25_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank25_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank25_wr_data_d1 = ({64{bank25_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank25_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank26_wr_addr_d1 = ({14{bank26_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank26_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank26_wr_data_d1 = ({64{bank26_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank26_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank27_wr_addr_d1 = ({14{bank27_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank27_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank27_wr_data_d1 = ({64{bank27_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank27_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank28_wr_addr_d1 = ({14{bank28_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank28_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank28_wr_data_d1 = ({64{bank28_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank28_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank29_wr_addr_d1 = ({14{bank29_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank29_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank29_wr_data_d1 = ({64{bank29_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank29_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank30_wr_addr_d1 = ({14{bank30_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank30_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank30_wr_data_d1 = ({64{bank30_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank30_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; +wire [14-1:0] bank31_wr_addr_d1 = ({14{bank31_wr0_en_d1}}&cdma2buf_wr_addr0_d1)|({14{bank31_wr1_en_d1}}&cdma2buf_wr_addr1_d1)|{14{1'b0}}; +wire [64-1:0] bank31_wr_data_d1 = ({64{bank31_wr0_en_d1}}&cdma2buf_wr_data0_d1)|({64{bank31_wr1_en_d1}}&cdma2buf_wr_data1_d1)|{64{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//map bank to sram. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire[9 -1 -1:0] bank${j}_ram${k}_wr_addr_d1 = bank${j}_wr_addr_d1[9 -1 -1:0]; +//: wire[64 -1:0] bank${j}_ram${k}_wr_data_d1 = bank${j}_wr_data_d1; +//: ) +//: } +//: if((2==2)||(2==3)){ +//: print qq( +//: wire[9 -1 -1:0] bank${j}_ram${k}_wr_addr_d1 = bank${j}_wr_addr_d1[9 -1:1]; +//: wire[64 -1:0] bank${j}_ram${k}_wr_data_d1 = bank${j}_wr_data_d1; +//: ) +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire[9 -1 -1:0] bank0_ram0_wr_addr_d1 = bank0_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank0_ram0_wr_data_d1 = bank0_wr_data_d1; + +wire[9 -1 -1:0] bank0_ram1_wr_addr_d1 = bank0_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank0_ram1_wr_data_d1 = bank0_wr_data_d1; + +wire[9 -1 -1:0] bank1_ram0_wr_addr_d1 = bank1_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank1_ram0_wr_data_d1 = bank1_wr_data_d1; + +wire[9 -1 -1:0] bank1_ram1_wr_addr_d1 = bank1_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank1_ram1_wr_data_d1 = bank1_wr_data_d1; + +wire[9 -1 -1:0] bank2_ram0_wr_addr_d1 = bank2_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank2_ram0_wr_data_d1 = bank2_wr_data_d1; + +wire[9 -1 -1:0] bank2_ram1_wr_addr_d1 = bank2_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank2_ram1_wr_data_d1 = bank2_wr_data_d1; + +wire[9 -1 -1:0] bank3_ram0_wr_addr_d1 = bank3_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank3_ram0_wr_data_d1 = bank3_wr_data_d1; + +wire[9 -1 -1:0] bank3_ram1_wr_addr_d1 = bank3_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank3_ram1_wr_data_d1 = bank3_wr_data_d1; + +wire[9 -1 -1:0] bank4_ram0_wr_addr_d1 = bank4_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank4_ram0_wr_data_d1 = bank4_wr_data_d1; + +wire[9 -1 -1:0] bank4_ram1_wr_addr_d1 = bank4_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank4_ram1_wr_data_d1 = bank4_wr_data_d1; + +wire[9 -1 -1:0] bank5_ram0_wr_addr_d1 = bank5_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank5_ram0_wr_data_d1 = bank5_wr_data_d1; + +wire[9 -1 -1:0] bank5_ram1_wr_addr_d1 = bank5_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank5_ram1_wr_data_d1 = bank5_wr_data_d1; + +wire[9 -1 -1:0] bank6_ram0_wr_addr_d1 = bank6_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank6_ram0_wr_data_d1 = bank6_wr_data_d1; + +wire[9 -1 -1:0] bank6_ram1_wr_addr_d1 = bank6_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank6_ram1_wr_data_d1 = bank6_wr_data_d1; + +wire[9 -1 -1:0] bank7_ram0_wr_addr_d1 = bank7_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank7_ram0_wr_data_d1 = bank7_wr_data_d1; + +wire[9 -1 -1:0] bank7_ram1_wr_addr_d1 = bank7_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank7_ram1_wr_data_d1 = bank7_wr_data_d1; + +wire[9 -1 -1:0] bank8_ram0_wr_addr_d1 = bank8_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank8_ram0_wr_data_d1 = bank8_wr_data_d1; + +wire[9 -1 -1:0] bank8_ram1_wr_addr_d1 = bank8_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank8_ram1_wr_data_d1 = bank8_wr_data_d1; + +wire[9 -1 -1:0] bank9_ram0_wr_addr_d1 = bank9_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank9_ram0_wr_data_d1 = bank9_wr_data_d1; + +wire[9 -1 -1:0] bank9_ram1_wr_addr_d1 = bank9_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank9_ram1_wr_data_d1 = bank9_wr_data_d1; + +wire[9 -1 -1:0] bank10_ram0_wr_addr_d1 = bank10_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank10_ram0_wr_data_d1 = bank10_wr_data_d1; + +wire[9 -1 -1:0] bank10_ram1_wr_addr_d1 = bank10_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank10_ram1_wr_data_d1 = bank10_wr_data_d1; + +wire[9 -1 -1:0] bank11_ram0_wr_addr_d1 = bank11_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank11_ram0_wr_data_d1 = bank11_wr_data_d1; + +wire[9 -1 -1:0] bank11_ram1_wr_addr_d1 = bank11_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank11_ram1_wr_data_d1 = bank11_wr_data_d1; + +wire[9 -1 -1:0] bank12_ram0_wr_addr_d1 = bank12_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank12_ram0_wr_data_d1 = bank12_wr_data_d1; + +wire[9 -1 -1:0] bank12_ram1_wr_addr_d1 = bank12_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank12_ram1_wr_data_d1 = bank12_wr_data_d1; + +wire[9 -1 -1:0] bank13_ram0_wr_addr_d1 = bank13_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank13_ram0_wr_data_d1 = bank13_wr_data_d1; + +wire[9 -1 -1:0] bank13_ram1_wr_addr_d1 = bank13_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank13_ram1_wr_data_d1 = bank13_wr_data_d1; + +wire[9 -1 -1:0] bank14_ram0_wr_addr_d1 = bank14_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank14_ram0_wr_data_d1 = bank14_wr_data_d1; + +wire[9 -1 -1:0] bank14_ram1_wr_addr_d1 = bank14_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank14_ram1_wr_data_d1 = bank14_wr_data_d1; + +wire[9 -1 -1:0] bank15_ram0_wr_addr_d1 = bank15_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank15_ram0_wr_data_d1 = bank15_wr_data_d1; + +wire[9 -1 -1:0] bank15_ram1_wr_addr_d1 = bank15_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank15_ram1_wr_data_d1 = bank15_wr_data_d1; + +wire[9 -1 -1:0] bank16_ram0_wr_addr_d1 = bank16_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank16_ram0_wr_data_d1 = bank16_wr_data_d1; + +wire[9 -1 -1:0] bank16_ram1_wr_addr_d1 = bank16_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank16_ram1_wr_data_d1 = bank16_wr_data_d1; + +wire[9 -1 -1:0] bank17_ram0_wr_addr_d1 = bank17_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank17_ram0_wr_data_d1 = bank17_wr_data_d1; + +wire[9 -1 -1:0] bank17_ram1_wr_addr_d1 = bank17_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank17_ram1_wr_data_d1 = bank17_wr_data_d1; + +wire[9 -1 -1:0] bank18_ram0_wr_addr_d1 = bank18_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank18_ram0_wr_data_d1 = bank18_wr_data_d1; + +wire[9 -1 -1:0] bank18_ram1_wr_addr_d1 = bank18_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank18_ram1_wr_data_d1 = bank18_wr_data_d1; + +wire[9 -1 -1:0] bank19_ram0_wr_addr_d1 = bank19_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank19_ram0_wr_data_d1 = bank19_wr_data_d1; + +wire[9 -1 -1:0] bank19_ram1_wr_addr_d1 = bank19_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank19_ram1_wr_data_d1 = bank19_wr_data_d1; + +wire[9 -1 -1:0] bank20_ram0_wr_addr_d1 = bank20_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank20_ram0_wr_data_d1 = bank20_wr_data_d1; + +wire[9 -1 -1:0] bank20_ram1_wr_addr_d1 = bank20_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank20_ram1_wr_data_d1 = bank20_wr_data_d1; + +wire[9 -1 -1:0] bank21_ram0_wr_addr_d1 = bank21_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank21_ram0_wr_data_d1 = bank21_wr_data_d1; + +wire[9 -1 -1:0] bank21_ram1_wr_addr_d1 = bank21_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank21_ram1_wr_data_d1 = bank21_wr_data_d1; + +wire[9 -1 -1:0] bank22_ram0_wr_addr_d1 = bank22_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank22_ram0_wr_data_d1 = bank22_wr_data_d1; + +wire[9 -1 -1:0] bank22_ram1_wr_addr_d1 = bank22_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank22_ram1_wr_data_d1 = bank22_wr_data_d1; + +wire[9 -1 -1:0] bank23_ram0_wr_addr_d1 = bank23_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank23_ram0_wr_data_d1 = bank23_wr_data_d1; + +wire[9 -1 -1:0] bank23_ram1_wr_addr_d1 = bank23_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank23_ram1_wr_data_d1 = bank23_wr_data_d1; + +wire[9 -1 -1:0] bank24_ram0_wr_addr_d1 = bank24_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank24_ram0_wr_data_d1 = bank24_wr_data_d1; + +wire[9 -1 -1:0] bank24_ram1_wr_addr_d1 = bank24_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank24_ram1_wr_data_d1 = bank24_wr_data_d1; + +wire[9 -1 -1:0] bank25_ram0_wr_addr_d1 = bank25_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank25_ram0_wr_data_d1 = bank25_wr_data_d1; + +wire[9 -1 -1:0] bank25_ram1_wr_addr_d1 = bank25_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank25_ram1_wr_data_d1 = bank25_wr_data_d1; + +wire[9 -1 -1:0] bank26_ram0_wr_addr_d1 = bank26_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank26_ram0_wr_data_d1 = bank26_wr_data_d1; + +wire[9 -1 -1:0] bank26_ram1_wr_addr_d1 = bank26_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank26_ram1_wr_data_d1 = bank26_wr_data_d1; + +wire[9 -1 -1:0] bank27_ram0_wr_addr_d1 = bank27_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank27_ram0_wr_data_d1 = bank27_wr_data_d1; + +wire[9 -1 -1:0] bank27_ram1_wr_addr_d1 = bank27_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank27_ram1_wr_data_d1 = bank27_wr_data_d1; + +wire[9 -1 -1:0] bank28_ram0_wr_addr_d1 = bank28_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank28_ram0_wr_data_d1 = bank28_wr_data_d1; + +wire[9 -1 -1:0] bank28_ram1_wr_addr_d1 = bank28_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank28_ram1_wr_data_d1 = bank28_wr_data_d1; + +wire[9 -1 -1:0] bank29_ram0_wr_addr_d1 = bank29_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank29_ram0_wr_data_d1 = bank29_wr_data_d1; + +wire[9 -1 -1:0] bank29_ram1_wr_addr_d1 = bank29_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank29_ram1_wr_data_d1 = bank29_wr_data_d1; + +wire[9 -1 -1:0] bank30_ram0_wr_addr_d1 = bank30_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank30_ram0_wr_data_d1 = bank30_wr_data_d1; + +wire[9 -1 -1:0] bank30_ram1_wr_addr_d1 = bank30_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank30_ram1_wr_data_d1 = bank30_wr_data_d1; + +wire[9 -1 -1:0] bank31_ram0_wr_addr_d1 = bank31_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank31_ram0_wr_data_d1 = bank31_wr_data_d1; + +wire[9 -1 -1:0] bank31_ram1_wr_addr_d1 = bank31_wr_addr_d1[9 -1:1]; +wire[64 -1:0] bank31_ram1_wr_data_d1 = bank31_wr_data_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// 1 pipe before write to sram, for timing +//: my $kk=9 -1; +//: my $jj=64; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: &eperl::flop("-q bank${j}_ram${k}_wr_en_d2 -d bank${j}_ram${k}_wr_en_d1"); +//: &eperl::flop("-wid ${kk} -q bank${j}_ram${k}_wr_addr_d2 -d bank${j}_ram${k}_wr_addr_d1"); +//: &eperl::flop("-wid ${jj} -norst -q bank${j}_ram${k}_wr_data_d2 -d bank${j}_ram${k}_wr_data_d1"); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg bank0_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_wr_en_d2 <= 'b0; + end else begin + bank0_ram0_wr_en_d2 <= bank0_ram0_wr_en_d1; + end +end +reg [7:0] bank0_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_wr_addr_d2 <= 'b0; + end else begin + bank0_ram0_wr_addr_d2 <= bank0_ram0_wr_addr_d1; + end +end +reg [63:0] bank0_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank0_ram0_wr_data_d2 <= bank0_ram0_wr_data_d1; +end +reg bank0_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_wr_en_d2 <= 'b0; + end else begin + bank0_ram1_wr_en_d2 <= bank0_ram1_wr_en_d1; + end +end +reg [7:0] bank0_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_wr_addr_d2 <= 'b0; + end else begin + bank0_ram1_wr_addr_d2 <= bank0_ram1_wr_addr_d1; + end +end +reg [63:0] bank0_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank0_ram1_wr_data_d2 <= bank0_ram1_wr_data_d1; +end +reg bank1_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_wr_en_d2 <= 'b0; + end else begin + bank1_ram0_wr_en_d2 <= bank1_ram0_wr_en_d1; + end +end +reg [7:0] bank1_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_wr_addr_d2 <= 'b0; + end else begin + bank1_ram0_wr_addr_d2 <= bank1_ram0_wr_addr_d1; + end +end +reg [63:0] bank1_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank1_ram0_wr_data_d2 <= bank1_ram0_wr_data_d1; +end +reg bank1_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_wr_en_d2 <= 'b0; + end else begin + bank1_ram1_wr_en_d2 <= bank1_ram1_wr_en_d1; + end +end +reg [7:0] bank1_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_wr_addr_d2 <= 'b0; + end else begin + bank1_ram1_wr_addr_d2 <= bank1_ram1_wr_addr_d1; + end +end +reg [63:0] bank1_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank1_ram1_wr_data_d2 <= bank1_ram1_wr_data_d1; +end +reg bank2_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_wr_en_d2 <= 'b0; + end else begin + bank2_ram0_wr_en_d2 <= bank2_ram0_wr_en_d1; + end +end +reg [7:0] bank2_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_wr_addr_d2 <= 'b0; + end else begin + bank2_ram0_wr_addr_d2 <= bank2_ram0_wr_addr_d1; + end +end +reg [63:0] bank2_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank2_ram0_wr_data_d2 <= bank2_ram0_wr_data_d1; +end +reg bank2_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_wr_en_d2 <= 'b0; + end else begin + bank2_ram1_wr_en_d2 <= bank2_ram1_wr_en_d1; + end +end +reg [7:0] bank2_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_wr_addr_d2 <= 'b0; + end else begin + bank2_ram1_wr_addr_d2 <= bank2_ram1_wr_addr_d1; + end +end +reg [63:0] bank2_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank2_ram1_wr_data_d2 <= bank2_ram1_wr_data_d1; +end +reg bank3_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_wr_en_d2 <= 'b0; + end else begin + bank3_ram0_wr_en_d2 <= bank3_ram0_wr_en_d1; + end +end +reg [7:0] bank3_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_wr_addr_d2 <= 'b0; + end else begin + bank3_ram0_wr_addr_d2 <= bank3_ram0_wr_addr_d1; + end +end +reg [63:0] bank3_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank3_ram0_wr_data_d2 <= bank3_ram0_wr_data_d1; +end +reg bank3_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_wr_en_d2 <= 'b0; + end else begin + bank3_ram1_wr_en_d2 <= bank3_ram1_wr_en_d1; + end +end +reg [7:0] bank3_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_wr_addr_d2 <= 'b0; + end else begin + bank3_ram1_wr_addr_d2 <= bank3_ram1_wr_addr_d1; + end +end +reg [63:0] bank3_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank3_ram1_wr_data_d2 <= bank3_ram1_wr_data_d1; +end +reg bank4_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_wr_en_d2 <= 'b0; + end else begin + bank4_ram0_wr_en_d2 <= bank4_ram0_wr_en_d1; + end +end +reg [7:0] bank4_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_wr_addr_d2 <= 'b0; + end else begin + bank4_ram0_wr_addr_d2 <= bank4_ram0_wr_addr_d1; + end +end +reg [63:0] bank4_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank4_ram0_wr_data_d2 <= bank4_ram0_wr_data_d1; +end +reg bank4_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_wr_en_d2 <= 'b0; + end else begin + bank4_ram1_wr_en_d2 <= bank4_ram1_wr_en_d1; + end +end +reg [7:0] bank4_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_wr_addr_d2 <= 'b0; + end else begin + bank4_ram1_wr_addr_d2 <= bank4_ram1_wr_addr_d1; + end +end +reg [63:0] bank4_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank4_ram1_wr_data_d2 <= bank4_ram1_wr_data_d1; +end +reg bank5_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_wr_en_d2 <= 'b0; + end else begin + bank5_ram0_wr_en_d2 <= bank5_ram0_wr_en_d1; + end +end +reg [7:0] bank5_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_wr_addr_d2 <= 'b0; + end else begin + bank5_ram0_wr_addr_d2 <= bank5_ram0_wr_addr_d1; + end +end +reg [63:0] bank5_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank5_ram0_wr_data_d2 <= bank5_ram0_wr_data_d1; +end +reg bank5_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_wr_en_d2 <= 'b0; + end else begin + bank5_ram1_wr_en_d2 <= bank5_ram1_wr_en_d1; + end +end +reg [7:0] bank5_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_wr_addr_d2 <= 'b0; + end else begin + bank5_ram1_wr_addr_d2 <= bank5_ram1_wr_addr_d1; + end +end +reg [63:0] bank5_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank5_ram1_wr_data_d2 <= bank5_ram1_wr_data_d1; +end +reg bank6_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_wr_en_d2 <= 'b0; + end else begin + bank6_ram0_wr_en_d2 <= bank6_ram0_wr_en_d1; + end +end +reg [7:0] bank6_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_wr_addr_d2 <= 'b0; + end else begin + bank6_ram0_wr_addr_d2 <= bank6_ram0_wr_addr_d1; + end +end +reg [63:0] bank6_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank6_ram0_wr_data_d2 <= bank6_ram0_wr_data_d1; +end +reg bank6_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_wr_en_d2 <= 'b0; + end else begin + bank6_ram1_wr_en_d2 <= bank6_ram1_wr_en_d1; + end +end +reg [7:0] bank6_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_wr_addr_d2 <= 'b0; + end else begin + bank6_ram1_wr_addr_d2 <= bank6_ram1_wr_addr_d1; + end +end +reg [63:0] bank6_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank6_ram1_wr_data_d2 <= bank6_ram1_wr_data_d1; +end +reg bank7_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_wr_en_d2 <= 'b0; + end else begin + bank7_ram0_wr_en_d2 <= bank7_ram0_wr_en_d1; + end +end +reg [7:0] bank7_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_wr_addr_d2 <= 'b0; + end else begin + bank7_ram0_wr_addr_d2 <= bank7_ram0_wr_addr_d1; + end +end +reg [63:0] bank7_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank7_ram0_wr_data_d2 <= bank7_ram0_wr_data_d1; +end +reg bank7_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_wr_en_d2 <= 'b0; + end else begin + bank7_ram1_wr_en_d2 <= bank7_ram1_wr_en_d1; + end +end +reg [7:0] bank7_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_wr_addr_d2 <= 'b0; + end else begin + bank7_ram1_wr_addr_d2 <= bank7_ram1_wr_addr_d1; + end +end +reg [63:0] bank7_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank7_ram1_wr_data_d2 <= bank7_ram1_wr_data_d1; +end +reg bank8_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_wr_en_d2 <= 'b0; + end else begin + bank8_ram0_wr_en_d2 <= bank8_ram0_wr_en_d1; + end +end +reg [7:0] bank8_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_wr_addr_d2 <= 'b0; + end else begin + bank8_ram0_wr_addr_d2 <= bank8_ram0_wr_addr_d1; + end +end +reg [63:0] bank8_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank8_ram0_wr_data_d2 <= bank8_ram0_wr_data_d1; +end +reg bank8_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_wr_en_d2 <= 'b0; + end else begin + bank8_ram1_wr_en_d2 <= bank8_ram1_wr_en_d1; + end +end +reg [7:0] bank8_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_wr_addr_d2 <= 'b0; + end else begin + bank8_ram1_wr_addr_d2 <= bank8_ram1_wr_addr_d1; + end +end +reg [63:0] bank8_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank8_ram1_wr_data_d2 <= bank8_ram1_wr_data_d1; +end +reg bank9_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_wr_en_d2 <= 'b0; + end else begin + bank9_ram0_wr_en_d2 <= bank9_ram0_wr_en_d1; + end +end +reg [7:0] bank9_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_wr_addr_d2 <= 'b0; + end else begin + bank9_ram0_wr_addr_d2 <= bank9_ram0_wr_addr_d1; + end +end +reg [63:0] bank9_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank9_ram0_wr_data_d2 <= bank9_ram0_wr_data_d1; +end +reg bank9_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_wr_en_d2 <= 'b0; + end else begin + bank9_ram1_wr_en_d2 <= bank9_ram1_wr_en_d1; + end +end +reg [7:0] bank9_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_wr_addr_d2 <= 'b0; + end else begin + bank9_ram1_wr_addr_d2 <= bank9_ram1_wr_addr_d1; + end +end +reg [63:0] bank9_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank9_ram1_wr_data_d2 <= bank9_ram1_wr_data_d1; +end +reg bank10_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_wr_en_d2 <= 'b0; + end else begin + bank10_ram0_wr_en_d2 <= bank10_ram0_wr_en_d1; + end +end +reg [7:0] bank10_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_wr_addr_d2 <= 'b0; + end else begin + bank10_ram0_wr_addr_d2 <= bank10_ram0_wr_addr_d1; + end +end +reg [63:0] bank10_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank10_ram0_wr_data_d2 <= bank10_ram0_wr_data_d1; +end +reg bank10_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_wr_en_d2 <= 'b0; + end else begin + bank10_ram1_wr_en_d2 <= bank10_ram1_wr_en_d1; + end +end +reg [7:0] bank10_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_wr_addr_d2 <= 'b0; + end else begin + bank10_ram1_wr_addr_d2 <= bank10_ram1_wr_addr_d1; + end +end +reg [63:0] bank10_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank10_ram1_wr_data_d2 <= bank10_ram1_wr_data_d1; +end +reg bank11_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_wr_en_d2 <= 'b0; + end else begin + bank11_ram0_wr_en_d2 <= bank11_ram0_wr_en_d1; + end +end +reg [7:0] bank11_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_wr_addr_d2 <= 'b0; + end else begin + bank11_ram0_wr_addr_d2 <= bank11_ram0_wr_addr_d1; + end +end +reg [63:0] bank11_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank11_ram0_wr_data_d2 <= bank11_ram0_wr_data_d1; +end +reg bank11_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_wr_en_d2 <= 'b0; + end else begin + bank11_ram1_wr_en_d2 <= bank11_ram1_wr_en_d1; + end +end +reg [7:0] bank11_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_wr_addr_d2 <= 'b0; + end else begin + bank11_ram1_wr_addr_d2 <= bank11_ram1_wr_addr_d1; + end +end +reg [63:0] bank11_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank11_ram1_wr_data_d2 <= bank11_ram1_wr_data_d1; +end +reg bank12_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_wr_en_d2 <= 'b0; + end else begin + bank12_ram0_wr_en_d2 <= bank12_ram0_wr_en_d1; + end +end +reg [7:0] bank12_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_wr_addr_d2 <= 'b0; + end else begin + bank12_ram0_wr_addr_d2 <= bank12_ram0_wr_addr_d1; + end +end +reg [63:0] bank12_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank12_ram0_wr_data_d2 <= bank12_ram0_wr_data_d1; +end +reg bank12_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_wr_en_d2 <= 'b0; + end else begin + bank12_ram1_wr_en_d2 <= bank12_ram1_wr_en_d1; + end +end +reg [7:0] bank12_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_wr_addr_d2 <= 'b0; + end else begin + bank12_ram1_wr_addr_d2 <= bank12_ram1_wr_addr_d1; + end +end +reg [63:0] bank12_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank12_ram1_wr_data_d2 <= bank12_ram1_wr_data_d1; +end +reg bank13_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_wr_en_d2 <= 'b0; + end else begin + bank13_ram0_wr_en_d2 <= bank13_ram0_wr_en_d1; + end +end +reg [7:0] bank13_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_wr_addr_d2 <= 'b0; + end else begin + bank13_ram0_wr_addr_d2 <= bank13_ram0_wr_addr_d1; + end +end +reg [63:0] bank13_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank13_ram0_wr_data_d2 <= bank13_ram0_wr_data_d1; +end +reg bank13_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_wr_en_d2 <= 'b0; + end else begin + bank13_ram1_wr_en_d2 <= bank13_ram1_wr_en_d1; + end +end +reg [7:0] bank13_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_wr_addr_d2 <= 'b0; + end else begin + bank13_ram1_wr_addr_d2 <= bank13_ram1_wr_addr_d1; + end +end +reg [63:0] bank13_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank13_ram1_wr_data_d2 <= bank13_ram1_wr_data_d1; +end +reg bank14_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_wr_en_d2 <= 'b0; + end else begin + bank14_ram0_wr_en_d2 <= bank14_ram0_wr_en_d1; + end +end +reg [7:0] bank14_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_wr_addr_d2 <= 'b0; + end else begin + bank14_ram0_wr_addr_d2 <= bank14_ram0_wr_addr_d1; + end +end +reg [63:0] bank14_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank14_ram0_wr_data_d2 <= bank14_ram0_wr_data_d1; +end +reg bank14_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_wr_en_d2 <= 'b0; + end else begin + bank14_ram1_wr_en_d2 <= bank14_ram1_wr_en_d1; + end +end +reg [7:0] bank14_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_wr_addr_d2 <= 'b0; + end else begin + bank14_ram1_wr_addr_d2 <= bank14_ram1_wr_addr_d1; + end +end +reg [63:0] bank14_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank14_ram1_wr_data_d2 <= bank14_ram1_wr_data_d1; +end +reg bank15_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_wr_en_d2 <= 'b0; + end else begin + bank15_ram0_wr_en_d2 <= bank15_ram0_wr_en_d1; + end +end +reg [7:0] bank15_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_wr_addr_d2 <= 'b0; + end else begin + bank15_ram0_wr_addr_d2 <= bank15_ram0_wr_addr_d1; + end +end +reg [63:0] bank15_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank15_ram0_wr_data_d2 <= bank15_ram0_wr_data_d1; +end +reg bank15_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_wr_en_d2 <= 'b0; + end else begin + bank15_ram1_wr_en_d2 <= bank15_ram1_wr_en_d1; + end +end +reg [7:0] bank15_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_wr_addr_d2 <= 'b0; + end else begin + bank15_ram1_wr_addr_d2 <= bank15_ram1_wr_addr_d1; + end +end +reg [63:0] bank15_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank15_ram1_wr_data_d2 <= bank15_ram1_wr_data_d1; +end +reg bank16_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_wr_en_d2 <= 'b0; + end else begin + bank16_ram0_wr_en_d2 <= bank16_ram0_wr_en_d1; + end +end +reg [7:0] bank16_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_wr_addr_d2 <= 'b0; + end else begin + bank16_ram0_wr_addr_d2 <= bank16_ram0_wr_addr_d1; + end +end +reg [63:0] bank16_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank16_ram0_wr_data_d2 <= bank16_ram0_wr_data_d1; +end +reg bank16_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_wr_en_d2 <= 'b0; + end else begin + bank16_ram1_wr_en_d2 <= bank16_ram1_wr_en_d1; + end +end +reg [7:0] bank16_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_wr_addr_d2 <= 'b0; + end else begin + bank16_ram1_wr_addr_d2 <= bank16_ram1_wr_addr_d1; + end +end +reg [63:0] bank16_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank16_ram1_wr_data_d2 <= bank16_ram1_wr_data_d1; +end +reg bank17_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_wr_en_d2 <= 'b0; + end else begin + bank17_ram0_wr_en_d2 <= bank17_ram0_wr_en_d1; + end +end +reg [7:0] bank17_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_wr_addr_d2 <= 'b0; + end else begin + bank17_ram0_wr_addr_d2 <= bank17_ram0_wr_addr_d1; + end +end +reg [63:0] bank17_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank17_ram0_wr_data_d2 <= bank17_ram0_wr_data_d1; +end +reg bank17_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_wr_en_d2 <= 'b0; + end else begin + bank17_ram1_wr_en_d2 <= bank17_ram1_wr_en_d1; + end +end +reg [7:0] bank17_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_wr_addr_d2 <= 'b0; + end else begin + bank17_ram1_wr_addr_d2 <= bank17_ram1_wr_addr_d1; + end +end +reg [63:0] bank17_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank17_ram1_wr_data_d2 <= bank17_ram1_wr_data_d1; +end +reg bank18_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_wr_en_d2 <= 'b0; + end else begin + bank18_ram0_wr_en_d2 <= bank18_ram0_wr_en_d1; + end +end +reg [7:0] bank18_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_wr_addr_d2 <= 'b0; + end else begin + bank18_ram0_wr_addr_d2 <= bank18_ram0_wr_addr_d1; + end +end +reg [63:0] bank18_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank18_ram0_wr_data_d2 <= bank18_ram0_wr_data_d1; +end +reg bank18_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_wr_en_d2 <= 'b0; + end else begin + bank18_ram1_wr_en_d2 <= bank18_ram1_wr_en_d1; + end +end +reg [7:0] bank18_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_wr_addr_d2 <= 'b0; + end else begin + bank18_ram1_wr_addr_d2 <= bank18_ram1_wr_addr_d1; + end +end +reg [63:0] bank18_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank18_ram1_wr_data_d2 <= bank18_ram1_wr_data_d1; +end +reg bank19_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_wr_en_d2 <= 'b0; + end else begin + bank19_ram0_wr_en_d2 <= bank19_ram0_wr_en_d1; + end +end +reg [7:0] bank19_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_wr_addr_d2 <= 'b0; + end else begin + bank19_ram0_wr_addr_d2 <= bank19_ram0_wr_addr_d1; + end +end +reg [63:0] bank19_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank19_ram0_wr_data_d2 <= bank19_ram0_wr_data_d1; +end +reg bank19_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_wr_en_d2 <= 'b0; + end else begin + bank19_ram1_wr_en_d2 <= bank19_ram1_wr_en_d1; + end +end +reg [7:0] bank19_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_wr_addr_d2 <= 'b0; + end else begin + bank19_ram1_wr_addr_d2 <= bank19_ram1_wr_addr_d1; + end +end +reg [63:0] bank19_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank19_ram1_wr_data_d2 <= bank19_ram1_wr_data_d1; +end +reg bank20_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_wr_en_d2 <= 'b0; + end else begin + bank20_ram0_wr_en_d2 <= bank20_ram0_wr_en_d1; + end +end +reg [7:0] bank20_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_wr_addr_d2 <= 'b0; + end else begin + bank20_ram0_wr_addr_d2 <= bank20_ram0_wr_addr_d1; + end +end +reg [63:0] bank20_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank20_ram0_wr_data_d2 <= bank20_ram0_wr_data_d1; +end +reg bank20_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_wr_en_d2 <= 'b0; + end else begin + bank20_ram1_wr_en_d2 <= bank20_ram1_wr_en_d1; + end +end +reg [7:0] bank20_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_wr_addr_d2 <= 'b0; + end else begin + bank20_ram1_wr_addr_d2 <= bank20_ram1_wr_addr_d1; + end +end +reg [63:0] bank20_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank20_ram1_wr_data_d2 <= bank20_ram1_wr_data_d1; +end +reg bank21_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_wr_en_d2 <= 'b0; + end else begin + bank21_ram0_wr_en_d2 <= bank21_ram0_wr_en_d1; + end +end +reg [7:0] bank21_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_wr_addr_d2 <= 'b0; + end else begin + bank21_ram0_wr_addr_d2 <= bank21_ram0_wr_addr_d1; + end +end +reg [63:0] bank21_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank21_ram0_wr_data_d2 <= bank21_ram0_wr_data_d1; +end +reg bank21_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_wr_en_d2 <= 'b0; + end else begin + bank21_ram1_wr_en_d2 <= bank21_ram1_wr_en_d1; + end +end +reg [7:0] bank21_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_wr_addr_d2 <= 'b0; + end else begin + bank21_ram1_wr_addr_d2 <= bank21_ram1_wr_addr_d1; + end +end +reg [63:0] bank21_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank21_ram1_wr_data_d2 <= bank21_ram1_wr_data_d1; +end +reg bank22_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_wr_en_d2 <= 'b0; + end else begin + bank22_ram0_wr_en_d2 <= bank22_ram0_wr_en_d1; + end +end +reg [7:0] bank22_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_wr_addr_d2 <= 'b0; + end else begin + bank22_ram0_wr_addr_d2 <= bank22_ram0_wr_addr_d1; + end +end +reg [63:0] bank22_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank22_ram0_wr_data_d2 <= bank22_ram0_wr_data_d1; +end +reg bank22_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_wr_en_d2 <= 'b0; + end else begin + bank22_ram1_wr_en_d2 <= bank22_ram1_wr_en_d1; + end +end +reg [7:0] bank22_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_wr_addr_d2 <= 'b0; + end else begin + bank22_ram1_wr_addr_d2 <= bank22_ram1_wr_addr_d1; + end +end +reg [63:0] bank22_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank22_ram1_wr_data_d2 <= bank22_ram1_wr_data_d1; +end +reg bank23_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_wr_en_d2 <= 'b0; + end else begin + bank23_ram0_wr_en_d2 <= bank23_ram0_wr_en_d1; + end +end +reg [7:0] bank23_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_wr_addr_d2 <= 'b0; + end else begin + bank23_ram0_wr_addr_d2 <= bank23_ram0_wr_addr_d1; + end +end +reg [63:0] bank23_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank23_ram0_wr_data_d2 <= bank23_ram0_wr_data_d1; +end +reg bank23_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_wr_en_d2 <= 'b0; + end else begin + bank23_ram1_wr_en_d2 <= bank23_ram1_wr_en_d1; + end +end +reg [7:0] bank23_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_wr_addr_d2 <= 'b0; + end else begin + bank23_ram1_wr_addr_d2 <= bank23_ram1_wr_addr_d1; + end +end +reg [63:0] bank23_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank23_ram1_wr_data_d2 <= bank23_ram1_wr_data_d1; +end +reg bank24_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_wr_en_d2 <= 'b0; + end else begin + bank24_ram0_wr_en_d2 <= bank24_ram0_wr_en_d1; + end +end +reg [7:0] bank24_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_wr_addr_d2 <= 'b0; + end else begin + bank24_ram0_wr_addr_d2 <= bank24_ram0_wr_addr_d1; + end +end +reg [63:0] bank24_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank24_ram0_wr_data_d2 <= bank24_ram0_wr_data_d1; +end +reg bank24_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_wr_en_d2 <= 'b0; + end else begin + bank24_ram1_wr_en_d2 <= bank24_ram1_wr_en_d1; + end +end +reg [7:0] bank24_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_wr_addr_d2 <= 'b0; + end else begin + bank24_ram1_wr_addr_d2 <= bank24_ram1_wr_addr_d1; + end +end +reg [63:0] bank24_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank24_ram1_wr_data_d2 <= bank24_ram1_wr_data_d1; +end +reg bank25_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_wr_en_d2 <= 'b0; + end else begin + bank25_ram0_wr_en_d2 <= bank25_ram0_wr_en_d1; + end +end +reg [7:0] bank25_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_wr_addr_d2 <= 'b0; + end else begin + bank25_ram0_wr_addr_d2 <= bank25_ram0_wr_addr_d1; + end +end +reg [63:0] bank25_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank25_ram0_wr_data_d2 <= bank25_ram0_wr_data_d1; +end +reg bank25_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_wr_en_d2 <= 'b0; + end else begin + bank25_ram1_wr_en_d2 <= bank25_ram1_wr_en_d1; + end +end +reg [7:0] bank25_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_wr_addr_d2 <= 'b0; + end else begin + bank25_ram1_wr_addr_d2 <= bank25_ram1_wr_addr_d1; + end +end +reg [63:0] bank25_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank25_ram1_wr_data_d2 <= bank25_ram1_wr_data_d1; +end +reg bank26_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_wr_en_d2 <= 'b0; + end else begin + bank26_ram0_wr_en_d2 <= bank26_ram0_wr_en_d1; + end +end +reg [7:0] bank26_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_wr_addr_d2 <= 'b0; + end else begin + bank26_ram0_wr_addr_d2 <= bank26_ram0_wr_addr_d1; + end +end +reg [63:0] bank26_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank26_ram0_wr_data_d2 <= bank26_ram0_wr_data_d1; +end +reg bank26_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_wr_en_d2 <= 'b0; + end else begin + bank26_ram1_wr_en_d2 <= bank26_ram1_wr_en_d1; + end +end +reg [7:0] bank26_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_wr_addr_d2 <= 'b0; + end else begin + bank26_ram1_wr_addr_d2 <= bank26_ram1_wr_addr_d1; + end +end +reg [63:0] bank26_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank26_ram1_wr_data_d2 <= bank26_ram1_wr_data_d1; +end +reg bank27_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_wr_en_d2 <= 'b0; + end else begin + bank27_ram0_wr_en_d2 <= bank27_ram0_wr_en_d1; + end +end +reg [7:0] bank27_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_wr_addr_d2 <= 'b0; + end else begin + bank27_ram0_wr_addr_d2 <= bank27_ram0_wr_addr_d1; + end +end +reg [63:0] bank27_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank27_ram0_wr_data_d2 <= bank27_ram0_wr_data_d1; +end +reg bank27_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_wr_en_d2 <= 'b0; + end else begin + bank27_ram1_wr_en_d2 <= bank27_ram1_wr_en_d1; + end +end +reg [7:0] bank27_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_wr_addr_d2 <= 'b0; + end else begin + bank27_ram1_wr_addr_d2 <= bank27_ram1_wr_addr_d1; + end +end +reg [63:0] bank27_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank27_ram1_wr_data_d2 <= bank27_ram1_wr_data_d1; +end +reg bank28_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_wr_en_d2 <= 'b0; + end else begin + bank28_ram0_wr_en_d2 <= bank28_ram0_wr_en_d1; + end +end +reg [7:0] bank28_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_wr_addr_d2 <= 'b0; + end else begin + bank28_ram0_wr_addr_d2 <= bank28_ram0_wr_addr_d1; + end +end +reg [63:0] bank28_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank28_ram0_wr_data_d2 <= bank28_ram0_wr_data_d1; +end +reg bank28_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_wr_en_d2 <= 'b0; + end else begin + bank28_ram1_wr_en_d2 <= bank28_ram1_wr_en_d1; + end +end +reg [7:0] bank28_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_wr_addr_d2 <= 'b0; + end else begin + bank28_ram1_wr_addr_d2 <= bank28_ram1_wr_addr_d1; + end +end +reg [63:0] bank28_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank28_ram1_wr_data_d2 <= bank28_ram1_wr_data_d1; +end +reg bank29_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_wr_en_d2 <= 'b0; + end else begin + bank29_ram0_wr_en_d2 <= bank29_ram0_wr_en_d1; + end +end +reg [7:0] bank29_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_wr_addr_d2 <= 'b0; + end else begin + bank29_ram0_wr_addr_d2 <= bank29_ram0_wr_addr_d1; + end +end +reg [63:0] bank29_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank29_ram0_wr_data_d2 <= bank29_ram0_wr_data_d1; +end +reg bank29_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_wr_en_d2 <= 'b0; + end else begin + bank29_ram1_wr_en_d2 <= bank29_ram1_wr_en_d1; + end +end +reg [7:0] bank29_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_wr_addr_d2 <= 'b0; + end else begin + bank29_ram1_wr_addr_d2 <= bank29_ram1_wr_addr_d1; + end +end +reg [63:0] bank29_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank29_ram1_wr_data_d2 <= bank29_ram1_wr_data_d1; +end +reg bank30_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_wr_en_d2 <= 'b0; + end else begin + bank30_ram0_wr_en_d2 <= bank30_ram0_wr_en_d1; + end +end +reg [7:0] bank30_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_wr_addr_d2 <= 'b0; + end else begin + bank30_ram0_wr_addr_d2 <= bank30_ram0_wr_addr_d1; + end +end +reg [63:0] bank30_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank30_ram0_wr_data_d2 <= bank30_ram0_wr_data_d1; +end +reg bank30_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_wr_en_d2 <= 'b0; + end else begin + bank30_ram1_wr_en_d2 <= bank30_ram1_wr_en_d1; + end +end +reg [7:0] bank30_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_wr_addr_d2 <= 'b0; + end else begin + bank30_ram1_wr_addr_d2 <= bank30_ram1_wr_addr_d1; + end +end +reg [63:0] bank30_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank30_ram1_wr_data_d2 <= bank30_ram1_wr_data_d1; +end +reg bank31_ram0_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_wr_en_d2 <= 'b0; + end else begin + bank31_ram0_wr_en_d2 <= bank31_ram0_wr_en_d1; + end +end +reg [7:0] bank31_ram0_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_wr_addr_d2 <= 'b0; + end else begin + bank31_ram0_wr_addr_d2 <= bank31_ram0_wr_addr_d1; + end +end +reg [63:0] bank31_ram0_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank31_ram0_wr_data_d2 <= bank31_ram0_wr_data_d1; +end +reg bank31_ram1_wr_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_wr_en_d2 <= 'b0; + end else begin + bank31_ram1_wr_en_d2 <= bank31_ram1_wr_en_d1; + end +end +reg [7:0] bank31_ram1_wr_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_wr_addr_d2 <= 'b0; + end else begin + bank31_ram1_wr_addr_d2 <= bank31_ram1_wr_addr_d1; + end +end +reg [63:0] bank31_ram1_wr_data_d2; +always @(posedge nvdla_core_clk) begin + bank31_ram1_wr_data_d2 <= bank31_ram1_wr_data_d1; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////step2: read data handle +//decode read data address to sram. +wire sc2buf_dat_rd_en0 = sc2buf_dat_rd_en; +wire sc2buf_dat_rd_en1 = sc2buf_dat_rd_en & sc2buf_dat_rd_next1_en; +wire[14 -1:0] sc2buf_dat_rd_addr0 = sc2buf_dat_rd_addr; +wire[14 -1:0] sc2buf_dat_rd_addr1 = sc2buf_dat_rd_next1_addr; +//: my $bank_slice= "13:9"; #address part for select bank +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd_en = sc2buf_dat_rd_en&&(sc2buf_dat_rd_addr[${bank_slice}]==${j}); ); +//: } +//: if(2==2){ +//: for(my $i=0; $i<2; $i++){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd${i}_en = sc2buf_dat_rd_en${i}&&(sc2buf_dat_rd_addr${i}[${bank_slice}]==${j})&&(sc2buf_dat_rd_addr${i}[0]==${k}); ); +//: } +//: } +//: if(2==3){ +//: #complicated,reserve, no use currently +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire bank0_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==0)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank0_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==0)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank0_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==0)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank0_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==0)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank1_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==1)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank1_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==1)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank1_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==1)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank1_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==1)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank2_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==2)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank2_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==2)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank2_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==2)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank2_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==2)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank3_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==3)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank3_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==3)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank3_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==3)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank3_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==3)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank4_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==4)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank4_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==4)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank4_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==4)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank4_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==4)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank5_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==5)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank5_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==5)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank5_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==5)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank5_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==5)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank6_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==6)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank6_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==6)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank6_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==6)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank6_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==6)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank7_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==7)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank7_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==7)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank7_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==7)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank7_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==7)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank8_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==8)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank8_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==8)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank8_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==8)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank8_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==8)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank9_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==9)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank9_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==9)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank9_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==9)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank9_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==9)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank10_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==10)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank10_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==10)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank10_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==10)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank10_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==10)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank11_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==11)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank11_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==11)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank11_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==11)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank11_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==11)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank12_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==12)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank12_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==12)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank12_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==12)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank12_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==12)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank13_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==13)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank13_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==13)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank13_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==13)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank13_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==13)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank14_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==14)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank14_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==14)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank14_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==14)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank14_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==14)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank15_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==15)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank15_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==15)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank15_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==15)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank15_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==15)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank16_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==16)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank16_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==16)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank16_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==16)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank16_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==16)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank17_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==17)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank17_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==17)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank17_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==17)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank17_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==17)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank18_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==18)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank18_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==18)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank18_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==18)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank18_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==18)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank19_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==19)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank19_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==19)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank19_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==19)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank19_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==19)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank20_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==20)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank20_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==20)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank20_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==20)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank20_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==20)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank21_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==21)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank21_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==21)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank21_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==21)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank21_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==21)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank22_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==22)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank22_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==22)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank22_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==22)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank22_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==22)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank23_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==23)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank23_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==23)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank23_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==23)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank23_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==23)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank24_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==24)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank24_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==24)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank24_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==24)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank24_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==24)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank25_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==25)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank25_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==25)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank25_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==25)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank25_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==25)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank26_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==26)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank26_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==26)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank26_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==26)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank26_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==26)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank27_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==27)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank27_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==27)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank27_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==27)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank27_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==27)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank28_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==28)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank28_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==28)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank28_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==28)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank28_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==28)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank29_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==29)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank29_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==29)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank29_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==29)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank29_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==29)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank30_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==30)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank30_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==30)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank30_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==30)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank30_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==30)&&(sc2buf_dat_rd_addr1[0]==1); +wire bank31_ram0_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==31)&&(sc2buf_dat_rd_addr0[0]==0); +wire bank31_ram0_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==31)&&(sc2buf_dat_rd_addr1[0]==0); +wire bank31_ram1_data_rd0_en = sc2buf_dat_rd_en0&&(sc2buf_dat_rd_addr0[13:9]==31)&&(sc2buf_dat_rd_addr0[0]==1); +wire bank31_ram1_data_rd1_en = sc2buf_dat_rd_en1&&(sc2buf_dat_rd_addr1[13:9]==31)&&(sc2buf_dat_rd_addr1[0]==1); +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sram data read address. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_data_rd_addr = {9 -1{bank${j}_ram${k}_data_rd_en}}&(sc2buf_dat_rd_addr[9 -1 -1:0]); ); +//: } +//: for(my $i=0; $i<2; $i++){ +//: if((2==2)||(2==3)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_data_rd${i}_addr = {9 -1{bank${j}_ram${k}_data_rd${i}_en}}&(sc2buf_dat_rd_addr${i}[9 -1:1]); ); +//: } +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [9 -1 -1:0] bank0_ram0_data_rd0_addr = {9 -1{bank0_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank0_ram0_data_rd1_addr = {9 -1{bank0_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank0_ram1_data_rd0_addr = {9 -1{bank0_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank0_ram1_data_rd1_addr = {9 -1{bank0_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank1_ram0_data_rd0_addr = {9 -1{bank1_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank1_ram0_data_rd1_addr = {9 -1{bank1_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank1_ram1_data_rd0_addr = {9 -1{bank1_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank1_ram1_data_rd1_addr = {9 -1{bank1_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank2_ram0_data_rd0_addr = {9 -1{bank2_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank2_ram0_data_rd1_addr = {9 -1{bank2_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank2_ram1_data_rd0_addr = {9 -1{bank2_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank2_ram1_data_rd1_addr = {9 -1{bank2_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank3_ram0_data_rd0_addr = {9 -1{bank3_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank3_ram0_data_rd1_addr = {9 -1{bank3_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank3_ram1_data_rd0_addr = {9 -1{bank3_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank3_ram1_data_rd1_addr = {9 -1{bank3_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank4_ram0_data_rd0_addr = {9 -1{bank4_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank4_ram0_data_rd1_addr = {9 -1{bank4_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank4_ram1_data_rd0_addr = {9 -1{bank4_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank4_ram1_data_rd1_addr = {9 -1{bank4_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank5_ram0_data_rd0_addr = {9 -1{bank5_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank5_ram0_data_rd1_addr = {9 -1{bank5_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank5_ram1_data_rd0_addr = {9 -1{bank5_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank5_ram1_data_rd1_addr = {9 -1{bank5_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank6_ram0_data_rd0_addr = {9 -1{bank6_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank6_ram0_data_rd1_addr = {9 -1{bank6_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank6_ram1_data_rd0_addr = {9 -1{bank6_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank6_ram1_data_rd1_addr = {9 -1{bank6_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank7_ram0_data_rd0_addr = {9 -1{bank7_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank7_ram0_data_rd1_addr = {9 -1{bank7_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank7_ram1_data_rd0_addr = {9 -1{bank7_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank7_ram1_data_rd1_addr = {9 -1{bank7_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank8_ram0_data_rd0_addr = {9 -1{bank8_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank8_ram0_data_rd1_addr = {9 -1{bank8_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank8_ram1_data_rd0_addr = {9 -1{bank8_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank8_ram1_data_rd1_addr = {9 -1{bank8_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank9_ram0_data_rd0_addr = {9 -1{bank9_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank9_ram0_data_rd1_addr = {9 -1{bank9_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank9_ram1_data_rd0_addr = {9 -1{bank9_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank9_ram1_data_rd1_addr = {9 -1{bank9_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank10_ram0_data_rd0_addr = {9 -1{bank10_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank10_ram0_data_rd1_addr = {9 -1{bank10_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank10_ram1_data_rd0_addr = {9 -1{bank10_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank10_ram1_data_rd1_addr = {9 -1{bank10_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank11_ram0_data_rd0_addr = {9 -1{bank11_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank11_ram0_data_rd1_addr = {9 -1{bank11_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank11_ram1_data_rd0_addr = {9 -1{bank11_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank11_ram1_data_rd1_addr = {9 -1{bank11_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank12_ram0_data_rd0_addr = {9 -1{bank12_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank12_ram0_data_rd1_addr = {9 -1{bank12_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank12_ram1_data_rd0_addr = {9 -1{bank12_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank12_ram1_data_rd1_addr = {9 -1{bank12_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank13_ram0_data_rd0_addr = {9 -1{bank13_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank13_ram0_data_rd1_addr = {9 -1{bank13_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank13_ram1_data_rd0_addr = {9 -1{bank13_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank13_ram1_data_rd1_addr = {9 -1{bank13_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank14_ram0_data_rd0_addr = {9 -1{bank14_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank14_ram0_data_rd1_addr = {9 -1{bank14_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank14_ram1_data_rd0_addr = {9 -1{bank14_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank14_ram1_data_rd1_addr = {9 -1{bank14_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank15_ram0_data_rd0_addr = {9 -1{bank15_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank15_ram0_data_rd1_addr = {9 -1{bank15_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank15_ram1_data_rd0_addr = {9 -1{bank15_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank15_ram1_data_rd1_addr = {9 -1{bank15_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank16_ram0_data_rd0_addr = {9 -1{bank16_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank16_ram0_data_rd1_addr = {9 -1{bank16_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank16_ram1_data_rd0_addr = {9 -1{bank16_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank16_ram1_data_rd1_addr = {9 -1{bank16_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank17_ram0_data_rd0_addr = {9 -1{bank17_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank17_ram0_data_rd1_addr = {9 -1{bank17_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank17_ram1_data_rd0_addr = {9 -1{bank17_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank17_ram1_data_rd1_addr = {9 -1{bank17_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank18_ram0_data_rd0_addr = {9 -1{bank18_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank18_ram0_data_rd1_addr = {9 -1{bank18_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank18_ram1_data_rd0_addr = {9 -1{bank18_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank18_ram1_data_rd1_addr = {9 -1{bank18_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank19_ram0_data_rd0_addr = {9 -1{bank19_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank19_ram0_data_rd1_addr = {9 -1{bank19_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank19_ram1_data_rd0_addr = {9 -1{bank19_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank19_ram1_data_rd1_addr = {9 -1{bank19_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank20_ram0_data_rd0_addr = {9 -1{bank20_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank20_ram0_data_rd1_addr = {9 -1{bank20_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank20_ram1_data_rd0_addr = {9 -1{bank20_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank20_ram1_data_rd1_addr = {9 -1{bank20_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank21_ram0_data_rd0_addr = {9 -1{bank21_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank21_ram0_data_rd1_addr = {9 -1{bank21_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank21_ram1_data_rd0_addr = {9 -1{bank21_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank21_ram1_data_rd1_addr = {9 -1{bank21_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank22_ram0_data_rd0_addr = {9 -1{bank22_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank22_ram0_data_rd1_addr = {9 -1{bank22_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank22_ram1_data_rd0_addr = {9 -1{bank22_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank22_ram1_data_rd1_addr = {9 -1{bank22_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank23_ram0_data_rd0_addr = {9 -1{bank23_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank23_ram0_data_rd1_addr = {9 -1{bank23_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank23_ram1_data_rd0_addr = {9 -1{bank23_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank23_ram1_data_rd1_addr = {9 -1{bank23_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank24_ram0_data_rd0_addr = {9 -1{bank24_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank24_ram0_data_rd1_addr = {9 -1{bank24_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank24_ram1_data_rd0_addr = {9 -1{bank24_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank24_ram1_data_rd1_addr = {9 -1{bank24_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank25_ram0_data_rd0_addr = {9 -1{bank25_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank25_ram0_data_rd1_addr = {9 -1{bank25_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank25_ram1_data_rd0_addr = {9 -1{bank25_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank25_ram1_data_rd1_addr = {9 -1{bank25_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank26_ram0_data_rd0_addr = {9 -1{bank26_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank26_ram0_data_rd1_addr = {9 -1{bank26_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank26_ram1_data_rd0_addr = {9 -1{bank26_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank26_ram1_data_rd1_addr = {9 -1{bank26_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank27_ram0_data_rd0_addr = {9 -1{bank27_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank27_ram0_data_rd1_addr = {9 -1{bank27_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank27_ram1_data_rd0_addr = {9 -1{bank27_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank27_ram1_data_rd1_addr = {9 -1{bank27_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank28_ram0_data_rd0_addr = {9 -1{bank28_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank28_ram0_data_rd1_addr = {9 -1{bank28_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank28_ram1_data_rd0_addr = {9 -1{bank28_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank28_ram1_data_rd1_addr = {9 -1{bank28_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank29_ram0_data_rd0_addr = {9 -1{bank29_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank29_ram0_data_rd1_addr = {9 -1{bank29_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank29_ram1_data_rd0_addr = {9 -1{bank29_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank29_ram1_data_rd1_addr = {9 -1{bank29_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank30_ram0_data_rd0_addr = {9 -1{bank30_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank30_ram0_data_rd1_addr = {9 -1{bank30_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank30_ram1_data_rd0_addr = {9 -1{bank30_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank30_ram1_data_rd1_addr = {9 -1{bank30_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank31_ram0_data_rd0_addr = {9 -1{bank31_ram0_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank31_ram0_data_rd1_addr = {9 -1{bank31_ram0_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +wire [9 -1 -1:0] bank31_ram1_data_rd0_addr = {9 -1{bank31_ram1_data_rd0_en}}&(sc2buf_dat_rd_addr0[9 -1:1]); +wire [9 -1 -1:0] bank31_ram1_data_rd1_addr = {9 -1{bank31_ram1_data_rd1_en}}&(sc2buf_dat_rd_addr1[9 -1:1]); +//| eperl: generated_end (DO NOT EDIT ABOVE) +//add flop for sram data read en +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: &eperl::flop("-q bank${j}_ram${k}_data_rd_en_d1 -d bank${j}_ram${k}_data_rd_en"); +//: &eperl::flop("-q bank${j}_ram${k}_data_rd_en_d2 -d bank${j}_ram${k}_data_rd_en_d1"); +//: } +//: for(my $i=0; $i<2; $i++){ +//: if((2==2)||(2==3)){ +//: &eperl::flop("-q bank${j}_ram${k}_data_rd${i}_en_d1 -d bank${j}_ram${k}_data_rd${i}_en"); +//: &eperl::flop("-q bank${j}_ram${k}_data_rd${i}_en_d2 -d bank${j}_ram${k}_data_rd${i}_en_d1"); +//: } +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg bank0_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank0_ram0_data_rd0_en_d1 <= bank0_ram0_data_rd0_en; + end +end +reg bank0_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank0_ram0_data_rd0_en_d2 <= bank0_ram0_data_rd0_en_d1; + end +end +reg bank0_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank0_ram0_data_rd1_en_d1 <= bank0_ram0_data_rd1_en; + end +end +reg bank0_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank0_ram0_data_rd1_en_d2 <= bank0_ram0_data_rd1_en_d1; + end +end +reg bank0_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank0_ram1_data_rd0_en_d1 <= bank0_ram1_data_rd0_en; + end +end +reg bank0_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank0_ram1_data_rd0_en_d2 <= bank0_ram1_data_rd0_en_d1; + end +end +reg bank0_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank0_ram1_data_rd1_en_d1 <= bank0_ram1_data_rd1_en; + end +end +reg bank0_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank0_ram1_data_rd1_en_d2 <= bank0_ram1_data_rd1_en_d1; + end +end +reg bank1_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank1_ram0_data_rd0_en_d1 <= bank1_ram0_data_rd0_en; + end +end +reg bank1_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank1_ram0_data_rd0_en_d2 <= bank1_ram0_data_rd0_en_d1; + end +end +reg bank1_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank1_ram0_data_rd1_en_d1 <= bank1_ram0_data_rd1_en; + end +end +reg bank1_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank1_ram0_data_rd1_en_d2 <= bank1_ram0_data_rd1_en_d1; + end +end +reg bank1_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank1_ram1_data_rd0_en_d1 <= bank1_ram1_data_rd0_en; + end +end +reg bank1_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank1_ram1_data_rd0_en_d2 <= bank1_ram1_data_rd0_en_d1; + end +end +reg bank1_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank1_ram1_data_rd1_en_d1 <= bank1_ram1_data_rd1_en; + end +end +reg bank1_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank1_ram1_data_rd1_en_d2 <= bank1_ram1_data_rd1_en_d1; + end +end +reg bank2_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank2_ram0_data_rd0_en_d1 <= bank2_ram0_data_rd0_en; + end +end +reg bank2_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank2_ram0_data_rd0_en_d2 <= bank2_ram0_data_rd0_en_d1; + end +end +reg bank2_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank2_ram0_data_rd1_en_d1 <= bank2_ram0_data_rd1_en; + end +end +reg bank2_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank2_ram0_data_rd1_en_d2 <= bank2_ram0_data_rd1_en_d1; + end +end +reg bank2_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank2_ram1_data_rd0_en_d1 <= bank2_ram1_data_rd0_en; + end +end +reg bank2_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank2_ram1_data_rd0_en_d2 <= bank2_ram1_data_rd0_en_d1; + end +end +reg bank2_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank2_ram1_data_rd1_en_d1 <= bank2_ram1_data_rd1_en; + end +end +reg bank2_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank2_ram1_data_rd1_en_d2 <= bank2_ram1_data_rd1_en_d1; + end +end +reg bank3_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank3_ram0_data_rd0_en_d1 <= bank3_ram0_data_rd0_en; + end +end +reg bank3_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank3_ram0_data_rd0_en_d2 <= bank3_ram0_data_rd0_en_d1; + end +end +reg bank3_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank3_ram0_data_rd1_en_d1 <= bank3_ram0_data_rd1_en; + end +end +reg bank3_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank3_ram0_data_rd1_en_d2 <= bank3_ram0_data_rd1_en_d1; + end +end +reg bank3_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank3_ram1_data_rd0_en_d1 <= bank3_ram1_data_rd0_en; + end +end +reg bank3_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank3_ram1_data_rd0_en_d2 <= bank3_ram1_data_rd0_en_d1; + end +end +reg bank3_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank3_ram1_data_rd1_en_d1 <= bank3_ram1_data_rd1_en; + end +end +reg bank3_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank3_ram1_data_rd1_en_d2 <= bank3_ram1_data_rd1_en_d1; + end +end +reg bank4_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank4_ram0_data_rd0_en_d1 <= bank4_ram0_data_rd0_en; + end +end +reg bank4_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank4_ram0_data_rd0_en_d2 <= bank4_ram0_data_rd0_en_d1; + end +end +reg bank4_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank4_ram0_data_rd1_en_d1 <= bank4_ram0_data_rd1_en; + end +end +reg bank4_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank4_ram0_data_rd1_en_d2 <= bank4_ram0_data_rd1_en_d1; + end +end +reg bank4_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank4_ram1_data_rd0_en_d1 <= bank4_ram1_data_rd0_en; + end +end +reg bank4_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank4_ram1_data_rd0_en_d2 <= bank4_ram1_data_rd0_en_d1; + end +end +reg bank4_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank4_ram1_data_rd1_en_d1 <= bank4_ram1_data_rd1_en; + end +end +reg bank4_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank4_ram1_data_rd1_en_d2 <= bank4_ram1_data_rd1_en_d1; + end +end +reg bank5_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank5_ram0_data_rd0_en_d1 <= bank5_ram0_data_rd0_en; + end +end +reg bank5_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank5_ram0_data_rd0_en_d2 <= bank5_ram0_data_rd0_en_d1; + end +end +reg bank5_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank5_ram0_data_rd1_en_d1 <= bank5_ram0_data_rd1_en; + end +end +reg bank5_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank5_ram0_data_rd1_en_d2 <= bank5_ram0_data_rd1_en_d1; + end +end +reg bank5_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank5_ram1_data_rd0_en_d1 <= bank5_ram1_data_rd0_en; + end +end +reg bank5_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank5_ram1_data_rd0_en_d2 <= bank5_ram1_data_rd0_en_d1; + end +end +reg bank5_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank5_ram1_data_rd1_en_d1 <= bank5_ram1_data_rd1_en; + end +end +reg bank5_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank5_ram1_data_rd1_en_d2 <= bank5_ram1_data_rd1_en_d1; + end +end +reg bank6_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank6_ram0_data_rd0_en_d1 <= bank6_ram0_data_rd0_en; + end +end +reg bank6_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank6_ram0_data_rd0_en_d2 <= bank6_ram0_data_rd0_en_d1; + end +end +reg bank6_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank6_ram0_data_rd1_en_d1 <= bank6_ram0_data_rd1_en; + end +end +reg bank6_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank6_ram0_data_rd1_en_d2 <= bank6_ram0_data_rd1_en_d1; + end +end +reg bank6_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank6_ram1_data_rd0_en_d1 <= bank6_ram1_data_rd0_en; + end +end +reg bank6_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank6_ram1_data_rd0_en_d2 <= bank6_ram1_data_rd0_en_d1; + end +end +reg bank6_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank6_ram1_data_rd1_en_d1 <= bank6_ram1_data_rd1_en; + end +end +reg bank6_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank6_ram1_data_rd1_en_d2 <= bank6_ram1_data_rd1_en_d1; + end +end +reg bank7_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank7_ram0_data_rd0_en_d1 <= bank7_ram0_data_rd0_en; + end +end +reg bank7_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank7_ram0_data_rd0_en_d2 <= bank7_ram0_data_rd0_en_d1; + end +end +reg bank7_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank7_ram0_data_rd1_en_d1 <= bank7_ram0_data_rd1_en; + end +end +reg bank7_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank7_ram0_data_rd1_en_d2 <= bank7_ram0_data_rd1_en_d1; + end +end +reg bank7_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank7_ram1_data_rd0_en_d1 <= bank7_ram1_data_rd0_en; + end +end +reg bank7_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank7_ram1_data_rd0_en_d2 <= bank7_ram1_data_rd0_en_d1; + end +end +reg bank7_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank7_ram1_data_rd1_en_d1 <= bank7_ram1_data_rd1_en; + end +end +reg bank7_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank7_ram1_data_rd1_en_d2 <= bank7_ram1_data_rd1_en_d1; + end +end +reg bank8_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank8_ram0_data_rd0_en_d1 <= bank8_ram0_data_rd0_en; + end +end +reg bank8_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank8_ram0_data_rd0_en_d2 <= bank8_ram0_data_rd0_en_d1; + end +end +reg bank8_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank8_ram0_data_rd1_en_d1 <= bank8_ram0_data_rd1_en; + end +end +reg bank8_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank8_ram0_data_rd1_en_d2 <= bank8_ram0_data_rd1_en_d1; + end +end +reg bank8_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank8_ram1_data_rd0_en_d1 <= bank8_ram1_data_rd0_en; + end +end +reg bank8_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank8_ram1_data_rd0_en_d2 <= bank8_ram1_data_rd0_en_d1; + end +end +reg bank8_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank8_ram1_data_rd1_en_d1 <= bank8_ram1_data_rd1_en; + end +end +reg bank8_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank8_ram1_data_rd1_en_d2 <= bank8_ram1_data_rd1_en_d1; + end +end +reg bank9_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank9_ram0_data_rd0_en_d1 <= bank9_ram0_data_rd0_en; + end +end +reg bank9_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank9_ram0_data_rd0_en_d2 <= bank9_ram0_data_rd0_en_d1; + end +end +reg bank9_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank9_ram0_data_rd1_en_d1 <= bank9_ram0_data_rd1_en; + end +end +reg bank9_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank9_ram0_data_rd1_en_d2 <= bank9_ram0_data_rd1_en_d1; + end +end +reg bank9_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank9_ram1_data_rd0_en_d1 <= bank9_ram1_data_rd0_en; + end +end +reg bank9_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank9_ram1_data_rd0_en_d2 <= bank9_ram1_data_rd0_en_d1; + end +end +reg bank9_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank9_ram1_data_rd1_en_d1 <= bank9_ram1_data_rd1_en; + end +end +reg bank9_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank9_ram1_data_rd1_en_d2 <= bank9_ram1_data_rd1_en_d1; + end +end +reg bank10_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank10_ram0_data_rd0_en_d1 <= bank10_ram0_data_rd0_en; + end +end +reg bank10_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank10_ram0_data_rd0_en_d2 <= bank10_ram0_data_rd0_en_d1; + end +end +reg bank10_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank10_ram0_data_rd1_en_d1 <= bank10_ram0_data_rd1_en; + end +end +reg bank10_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank10_ram0_data_rd1_en_d2 <= bank10_ram0_data_rd1_en_d1; + end +end +reg bank10_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank10_ram1_data_rd0_en_d1 <= bank10_ram1_data_rd0_en; + end +end +reg bank10_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank10_ram1_data_rd0_en_d2 <= bank10_ram1_data_rd0_en_d1; + end +end +reg bank10_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank10_ram1_data_rd1_en_d1 <= bank10_ram1_data_rd1_en; + end +end +reg bank10_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank10_ram1_data_rd1_en_d2 <= bank10_ram1_data_rd1_en_d1; + end +end +reg bank11_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank11_ram0_data_rd0_en_d1 <= bank11_ram0_data_rd0_en; + end +end +reg bank11_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank11_ram0_data_rd0_en_d2 <= bank11_ram0_data_rd0_en_d1; + end +end +reg bank11_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank11_ram0_data_rd1_en_d1 <= bank11_ram0_data_rd1_en; + end +end +reg bank11_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank11_ram0_data_rd1_en_d2 <= bank11_ram0_data_rd1_en_d1; + end +end +reg bank11_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank11_ram1_data_rd0_en_d1 <= bank11_ram1_data_rd0_en; + end +end +reg bank11_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank11_ram1_data_rd0_en_d2 <= bank11_ram1_data_rd0_en_d1; + end +end +reg bank11_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank11_ram1_data_rd1_en_d1 <= bank11_ram1_data_rd1_en; + end +end +reg bank11_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank11_ram1_data_rd1_en_d2 <= bank11_ram1_data_rd1_en_d1; + end +end +reg bank12_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank12_ram0_data_rd0_en_d1 <= bank12_ram0_data_rd0_en; + end +end +reg bank12_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank12_ram0_data_rd0_en_d2 <= bank12_ram0_data_rd0_en_d1; + end +end +reg bank12_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank12_ram0_data_rd1_en_d1 <= bank12_ram0_data_rd1_en; + end +end +reg bank12_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank12_ram0_data_rd1_en_d2 <= bank12_ram0_data_rd1_en_d1; + end +end +reg bank12_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank12_ram1_data_rd0_en_d1 <= bank12_ram1_data_rd0_en; + end +end +reg bank12_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank12_ram1_data_rd0_en_d2 <= bank12_ram1_data_rd0_en_d1; + end +end +reg bank12_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank12_ram1_data_rd1_en_d1 <= bank12_ram1_data_rd1_en; + end +end +reg bank12_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank12_ram1_data_rd1_en_d2 <= bank12_ram1_data_rd1_en_d1; + end +end +reg bank13_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank13_ram0_data_rd0_en_d1 <= bank13_ram0_data_rd0_en; + end +end +reg bank13_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank13_ram0_data_rd0_en_d2 <= bank13_ram0_data_rd0_en_d1; + end +end +reg bank13_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank13_ram0_data_rd1_en_d1 <= bank13_ram0_data_rd1_en; + end +end +reg bank13_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank13_ram0_data_rd1_en_d2 <= bank13_ram0_data_rd1_en_d1; + end +end +reg bank13_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank13_ram1_data_rd0_en_d1 <= bank13_ram1_data_rd0_en; + end +end +reg bank13_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank13_ram1_data_rd0_en_d2 <= bank13_ram1_data_rd0_en_d1; + end +end +reg bank13_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank13_ram1_data_rd1_en_d1 <= bank13_ram1_data_rd1_en; + end +end +reg bank13_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank13_ram1_data_rd1_en_d2 <= bank13_ram1_data_rd1_en_d1; + end +end +reg bank14_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank14_ram0_data_rd0_en_d1 <= bank14_ram0_data_rd0_en; + end +end +reg bank14_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank14_ram0_data_rd0_en_d2 <= bank14_ram0_data_rd0_en_d1; + end +end +reg bank14_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank14_ram0_data_rd1_en_d1 <= bank14_ram0_data_rd1_en; + end +end +reg bank14_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank14_ram0_data_rd1_en_d2 <= bank14_ram0_data_rd1_en_d1; + end +end +reg bank14_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank14_ram1_data_rd0_en_d1 <= bank14_ram1_data_rd0_en; + end +end +reg bank14_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank14_ram1_data_rd0_en_d2 <= bank14_ram1_data_rd0_en_d1; + end +end +reg bank14_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank14_ram1_data_rd1_en_d1 <= bank14_ram1_data_rd1_en; + end +end +reg bank14_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank14_ram1_data_rd1_en_d2 <= bank14_ram1_data_rd1_en_d1; + end +end +reg bank15_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank15_ram0_data_rd0_en_d1 <= bank15_ram0_data_rd0_en; + end +end +reg bank15_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank15_ram0_data_rd0_en_d2 <= bank15_ram0_data_rd0_en_d1; + end +end +reg bank15_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank15_ram0_data_rd1_en_d1 <= bank15_ram0_data_rd1_en; + end +end +reg bank15_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank15_ram0_data_rd1_en_d2 <= bank15_ram0_data_rd1_en_d1; + end +end +reg bank15_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank15_ram1_data_rd0_en_d1 <= bank15_ram1_data_rd0_en; + end +end +reg bank15_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank15_ram1_data_rd0_en_d2 <= bank15_ram1_data_rd0_en_d1; + end +end +reg bank15_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank15_ram1_data_rd1_en_d1 <= bank15_ram1_data_rd1_en; + end +end +reg bank15_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank15_ram1_data_rd1_en_d2 <= bank15_ram1_data_rd1_en_d1; + end +end +reg bank16_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank16_ram0_data_rd0_en_d1 <= bank16_ram0_data_rd0_en; + end +end +reg bank16_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank16_ram0_data_rd0_en_d2 <= bank16_ram0_data_rd0_en_d1; + end +end +reg bank16_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank16_ram0_data_rd1_en_d1 <= bank16_ram0_data_rd1_en; + end +end +reg bank16_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank16_ram0_data_rd1_en_d2 <= bank16_ram0_data_rd1_en_d1; + end +end +reg bank16_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank16_ram1_data_rd0_en_d1 <= bank16_ram1_data_rd0_en; + end +end +reg bank16_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank16_ram1_data_rd0_en_d2 <= bank16_ram1_data_rd0_en_d1; + end +end +reg bank16_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank16_ram1_data_rd1_en_d1 <= bank16_ram1_data_rd1_en; + end +end +reg bank16_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank16_ram1_data_rd1_en_d2 <= bank16_ram1_data_rd1_en_d1; + end +end +reg bank17_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank17_ram0_data_rd0_en_d1 <= bank17_ram0_data_rd0_en; + end +end +reg bank17_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank17_ram0_data_rd0_en_d2 <= bank17_ram0_data_rd0_en_d1; + end +end +reg bank17_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank17_ram0_data_rd1_en_d1 <= bank17_ram0_data_rd1_en; + end +end +reg bank17_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank17_ram0_data_rd1_en_d2 <= bank17_ram0_data_rd1_en_d1; + end +end +reg bank17_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank17_ram1_data_rd0_en_d1 <= bank17_ram1_data_rd0_en; + end +end +reg bank17_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank17_ram1_data_rd0_en_d2 <= bank17_ram1_data_rd0_en_d1; + end +end +reg bank17_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank17_ram1_data_rd1_en_d1 <= bank17_ram1_data_rd1_en; + end +end +reg bank17_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank17_ram1_data_rd1_en_d2 <= bank17_ram1_data_rd1_en_d1; + end +end +reg bank18_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank18_ram0_data_rd0_en_d1 <= bank18_ram0_data_rd0_en; + end +end +reg bank18_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank18_ram0_data_rd0_en_d2 <= bank18_ram0_data_rd0_en_d1; + end +end +reg bank18_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank18_ram0_data_rd1_en_d1 <= bank18_ram0_data_rd1_en; + end +end +reg bank18_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank18_ram0_data_rd1_en_d2 <= bank18_ram0_data_rd1_en_d1; + end +end +reg bank18_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank18_ram1_data_rd0_en_d1 <= bank18_ram1_data_rd0_en; + end +end +reg bank18_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank18_ram1_data_rd0_en_d2 <= bank18_ram1_data_rd0_en_d1; + end +end +reg bank18_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank18_ram1_data_rd1_en_d1 <= bank18_ram1_data_rd1_en; + end +end +reg bank18_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank18_ram1_data_rd1_en_d2 <= bank18_ram1_data_rd1_en_d1; + end +end +reg bank19_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank19_ram0_data_rd0_en_d1 <= bank19_ram0_data_rd0_en; + end +end +reg bank19_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank19_ram0_data_rd0_en_d2 <= bank19_ram0_data_rd0_en_d1; + end +end +reg bank19_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank19_ram0_data_rd1_en_d1 <= bank19_ram0_data_rd1_en; + end +end +reg bank19_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank19_ram0_data_rd1_en_d2 <= bank19_ram0_data_rd1_en_d1; + end +end +reg bank19_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank19_ram1_data_rd0_en_d1 <= bank19_ram1_data_rd0_en; + end +end +reg bank19_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank19_ram1_data_rd0_en_d2 <= bank19_ram1_data_rd0_en_d1; + end +end +reg bank19_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank19_ram1_data_rd1_en_d1 <= bank19_ram1_data_rd1_en; + end +end +reg bank19_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank19_ram1_data_rd1_en_d2 <= bank19_ram1_data_rd1_en_d1; + end +end +reg bank20_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank20_ram0_data_rd0_en_d1 <= bank20_ram0_data_rd0_en; + end +end +reg bank20_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank20_ram0_data_rd0_en_d2 <= bank20_ram0_data_rd0_en_d1; + end +end +reg bank20_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank20_ram0_data_rd1_en_d1 <= bank20_ram0_data_rd1_en; + end +end +reg bank20_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank20_ram0_data_rd1_en_d2 <= bank20_ram0_data_rd1_en_d1; + end +end +reg bank20_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank20_ram1_data_rd0_en_d1 <= bank20_ram1_data_rd0_en; + end +end +reg bank20_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank20_ram1_data_rd0_en_d2 <= bank20_ram1_data_rd0_en_d1; + end +end +reg bank20_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank20_ram1_data_rd1_en_d1 <= bank20_ram1_data_rd1_en; + end +end +reg bank20_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank20_ram1_data_rd1_en_d2 <= bank20_ram1_data_rd1_en_d1; + end +end +reg bank21_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank21_ram0_data_rd0_en_d1 <= bank21_ram0_data_rd0_en; + end +end +reg bank21_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank21_ram0_data_rd0_en_d2 <= bank21_ram0_data_rd0_en_d1; + end +end +reg bank21_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank21_ram0_data_rd1_en_d1 <= bank21_ram0_data_rd1_en; + end +end +reg bank21_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank21_ram0_data_rd1_en_d2 <= bank21_ram0_data_rd1_en_d1; + end +end +reg bank21_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank21_ram1_data_rd0_en_d1 <= bank21_ram1_data_rd0_en; + end +end +reg bank21_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank21_ram1_data_rd0_en_d2 <= bank21_ram1_data_rd0_en_d1; + end +end +reg bank21_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank21_ram1_data_rd1_en_d1 <= bank21_ram1_data_rd1_en; + end +end +reg bank21_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank21_ram1_data_rd1_en_d2 <= bank21_ram1_data_rd1_en_d1; + end +end +reg bank22_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank22_ram0_data_rd0_en_d1 <= bank22_ram0_data_rd0_en; + end +end +reg bank22_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank22_ram0_data_rd0_en_d2 <= bank22_ram0_data_rd0_en_d1; + end +end +reg bank22_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank22_ram0_data_rd1_en_d1 <= bank22_ram0_data_rd1_en; + end +end +reg bank22_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank22_ram0_data_rd1_en_d2 <= bank22_ram0_data_rd1_en_d1; + end +end +reg bank22_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank22_ram1_data_rd0_en_d1 <= bank22_ram1_data_rd0_en; + end +end +reg bank22_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank22_ram1_data_rd0_en_d2 <= bank22_ram1_data_rd0_en_d1; + end +end +reg bank22_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank22_ram1_data_rd1_en_d1 <= bank22_ram1_data_rd1_en; + end +end +reg bank22_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank22_ram1_data_rd1_en_d2 <= bank22_ram1_data_rd1_en_d1; + end +end +reg bank23_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank23_ram0_data_rd0_en_d1 <= bank23_ram0_data_rd0_en; + end +end +reg bank23_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank23_ram0_data_rd0_en_d2 <= bank23_ram0_data_rd0_en_d1; + end +end +reg bank23_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank23_ram0_data_rd1_en_d1 <= bank23_ram0_data_rd1_en; + end +end +reg bank23_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank23_ram0_data_rd1_en_d2 <= bank23_ram0_data_rd1_en_d1; + end +end +reg bank23_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank23_ram1_data_rd0_en_d1 <= bank23_ram1_data_rd0_en; + end +end +reg bank23_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank23_ram1_data_rd0_en_d2 <= bank23_ram1_data_rd0_en_d1; + end +end +reg bank23_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank23_ram1_data_rd1_en_d1 <= bank23_ram1_data_rd1_en; + end +end +reg bank23_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank23_ram1_data_rd1_en_d2 <= bank23_ram1_data_rd1_en_d1; + end +end +reg bank24_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank24_ram0_data_rd0_en_d1 <= bank24_ram0_data_rd0_en; + end +end +reg bank24_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank24_ram0_data_rd0_en_d2 <= bank24_ram0_data_rd0_en_d1; + end +end +reg bank24_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank24_ram0_data_rd1_en_d1 <= bank24_ram0_data_rd1_en; + end +end +reg bank24_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank24_ram0_data_rd1_en_d2 <= bank24_ram0_data_rd1_en_d1; + end +end +reg bank24_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank24_ram1_data_rd0_en_d1 <= bank24_ram1_data_rd0_en; + end +end +reg bank24_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank24_ram1_data_rd0_en_d2 <= bank24_ram1_data_rd0_en_d1; + end +end +reg bank24_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank24_ram1_data_rd1_en_d1 <= bank24_ram1_data_rd1_en; + end +end +reg bank24_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank24_ram1_data_rd1_en_d2 <= bank24_ram1_data_rd1_en_d1; + end +end +reg bank25_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank25_ram0_data_rd0_en_d1 <= bank25_ram0_data_rd0_en; + end +end +reg bank25_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank25_ram0_data_rd0_en_d2 <= bank25_ram0_data_rd0_en_d1; + end +end +reg bank25_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank25_ram0_data_rd1_en_d1 <= bank25_ram0_data_rd1_en; + end +end +reg bank25_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank25_ram0_data_rd1_en_d2 <= bank25_ram0_data_rd1_en_d1; + end +end +reg bank25_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank25_ram1_data_rd0_en_d1 <= bank25_ram1_data_rd0_en; + end +end +reg bank25_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank25_ram1_data_rd0_en_d2 <= bank25_ram1_data_rd0_en_d1; + end +end +reg bank25_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank25_ram1_data_rd1_en_d1 <= bank25_ram1_data_rd1_en; + end +end +reg bank25_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank25_ram1_data_rd1_en_d2 <= bank25_ram1_data_rd1_en_d1; + end +end +reg bank26_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank26_ram0_data_rd0_en_d1 <= bank26_ram0_data_rd0_en; + end +end +reg bank26_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank26_ram0_data_rd0_en_d2 <= bank26_ram0_data_rd0_en_d1; + end +end +reg bank26_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank26_ram0_data_rd1_en_d1 <= bank26_ram0_data_rd1_en; + end +end +reg bank26_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank26_ram0_data_rd1_en_d2 <= bank26_ram0_data_rd1_en_d1; + end +end +reg bank26_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank26_ram1_data_rd0_en_d1 <= bank26_ram1_data_rd0_en; + end +end +reg bank26_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank26_ram1_data_rd0_en_d2 <= bank26_ram1_data_rd0_en_d1; + end +end +reg bank26_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank26_ram1_data_rd1_en_d1 <= bank26_ram1_data_rd1_en; + end +end +reg bank26_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank26_ram1_data_rd1_en_d2 <= bank26_ram1_data_rd1_en_d1; + end +end +reg bank27_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank27_ram0_data_rd0_en_d1 <= bank27_ram0_data_rd0_en; + end +end +reg bank27_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank27_ram0_data_rd0_en_d2 <= bank27_ram0_data_rd0_en_d1; + end +end +reg bank27_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank27_ram0_data_rd1_en_d1 <= bank27_ram0_data_rd1_en; + end +end +reg bank27_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank27_ram0_data_rd1_en_d2 <= bank27_ram0_data_rd1_en_d1; + end +end +reg bank27_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank27_ram1_data_rd0_en_d1 <= bank27_ram1_data_rd0_en; + end +end +reg bank27_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank27_ram1_data_rd0_en_d2 <= bank27_ram1_data_rd0_en_d1; + end +end +reg bank27_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank27_ram1_data_rd1_en_d1 <= bank27_ram1_data_rd1_en; + end +end +reg bank27_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank27_ram1_data_rd1_en_d2 <= bank27_ram1_data_rd1_en_d1; + end +end +reg bank28_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank28_ram0_data_rd0_en_d1 <= bank28_ram0_data_rd0_en; + end +end +reg bank28_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank28_ram0_data_rd0_en_d2 <= bank28_ram0_data_rd0_en_d1; + end +end +reg bank28_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank28_ram0_data_rd1_en_d1 <= bank28_ram0_data_rd1_en; + end +end +reg bank28_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank28_ram0_data_rd1_en_d2 <= bank28_ram0_data_rd1_en_d1; + end +end +reg bank28_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank28_ram1_data_rd0_en_d1 <= bank28_ram1_data_rd0_en; + end +end +reg bank28_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank28_ram1_data_rd0_en_d2 <= bank28_ram1_data_rd0_en_d1; + end +end +reg bank28_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank28_ram1_data_rd1_en_d1 <= bank28_ram1_data_rd1_en; + end +end +reg bank28_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank28_ram1_data_rd1_en_d2 <= bank28_ram1_data_rd1_en_d1; + end +end +reg bank29_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank29_ram0_data_rd0_en_d1 <= bank29_ram0_data_rd0_en; + end +end +reg bank29_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank29_ram0_data_rd0_en_d2 <= bank29_ram0_data_rd0_en_d1; + end +end +reg bank29_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank29_ram0_data_rd1_en_d1 <= bank29_ram0_data_rd1_en; + end +end +reg bank29_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank29_ram0_data_rd1_en_d2 <= bank29_ram0_data_rd1_en_d1; + end +end +reg bank29_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank29_ram1_data_rd0_en_d1 <= bank29_ram1_data_rd0_en; + end +end +reg bank29_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank29_ram1_data_rd0_en_d2 <= bank29_ram1_data_rd0_en_d1; + end +end +reg bank29_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank29_ram1_data_rd1_en_d1 <= bank29_ram1_data_rd1_en; + end +end +reg bank29_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank29_ram1_data_rd1_en_d2 <= bank29_ram1_data_rd1_en_d1; + end +end +reg bank30_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank30_ram0_data_rd0_en_d1 <= bank30_ram0_data_rd0_en; + end +end +reg bank30_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank30_ram0_data_rd0_en_d2 <= bank30_ram0_data_rd0_en_d1; + end +end +reg bank30_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank30_ram0_data_rd1_en_d1 <= bank30_ram0_data_rd1_en; + end +end +reg bank30_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank30_ram0_data_rd1_en_d2 <= bank30_ram0_data_rd1_en_d1; + end +end +reg bank30_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank30_ram1_data_rd0_en_d1 <= bank30_ram1_data_rd0_en; + end +end +reg bank30_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank30_ram1_data_rd0_en_d2 <= bank30_ram1_data_rd0_en_d1; + end +end +reg bank30_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank30_ram1_data_rd1_en_d1 <= bank30_ram1_data_rd1_en; + end +end +reg bank30_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank30_ram1_data_rd1_en_d2 <= bank30_ram1_data_rd1_en_d1; + end +end +reg bank31_ram0_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_data_rd0_en_d1 <= 'b0; + end else begin + bank31_ram0_data_rd0_en_d1 <= bank31_ram0_data_rd0_en; + end +end +reg bank31_ram0_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_data_rd0_en_d2 <= 'b0; + end else begin + bank31_ram0_data_rd0_en_d2 <= bank31_ram0_data_rd0_en_d1; + end +end +reg bank31_ram0_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_data_rd1_en_d1 <= 'b0; + end else begin + bank31_ram0_data_rd1_en_d1 <= bank31_ram0_data_rd1_en; + end +end +reg bank31_ram0_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_data_rd1_en_d2 <= 'b0; + end else begin + bank31_ram0_data_rd1_en_d2 <= bank31_ram0_data_rd1_en_d1; + end +end +reg bank31_ram1_data_rd0_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_data_rd0_en_d1 <= 'b0; + end else begin + bank31_ram1_data_rd0_en_d1 <= bank31_ram1_data_rd0_en; + end +end +reg bank31_ram1_data_rd0_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_data_rd0_en_d2 <= 'b0; + end else begin + bank31_ram1_data_rd0_en_d2 <= bank31_ram1_data_rd0_en_d1; + end +end +reg bank31_ram1_data_rd1_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_data_rd1_en_d1 <= 'b0; + end else begin + bank31_ram1_data_rd1_en_d1 <= bank31_ram1_data_rd1_en; + end +end +reg bank31_ram1_data_rd1_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_data_rd1_en_d2 <= 'b0; + end else begin + bank31_ram1_data_rd1_en_d2 <= bank31_ram1_data_rd1_en_d1; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sram data read valid. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd_valid = bank${j}_ram${k}_data_rd_en_d2; ) +//: } +//: for(my $i=0; $i<2; $i++){ +//: if((2==2)||(2==3)){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd${i}_valid = bank${j}_ram${k}_data_rd${i}_en_d2; ) +//: } +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire bank0_ram0_data_rd0_valid = bank0_ram0_data_rd0_en_d2; +wire bank0_ram0_data_rd1_valid = bank0_ram0_data_rd1_en_d2; +wire bank0_ram1_data_rd0_valid = bank0_ram1_data_rd0_en_d2; +wire bank0_ram1_data_rd1_valid = bank0_ram1_data_rd1_en_d2; +wire bank1_ram0_data_rd0_valid = bank1_ram0_data_rd0_en_d2; +wire bank1_ram0_data_rd1_valid = bank1_ram0_data_rd1_en_d2; +wire bank1_ram1_data_rd0_valid = bank1_ram1_data_rd0_en_d2; +wire bank1_ram1_data_rd1_valid = bank1_ram1_data_rd1_en_d2; +wire bank2_ram0_data_rd0_valid = bank2_ram0_data_rd0_en_d2; +wire bank2_ram0_data_rd1_valid = bank2_ram0_data_rd1_en_d2; +wire bank2_ram1_data_rd0_valid = bank2_ram1_data_rd0_en_d2; +wire bank2_ram1_data_rd1_valid = bank2_ram1_data_rd1_en_d2; +wire bank3_ram0_data_rd0_valid = bank3_ram0_data_rd0_en_d2; +wire bank3_ram0_data_rd1_valid = bank3_ram0_data_rd1_en_d2; +wire bank3_ram1_data_rd0_valid = bank3_ram1_data_rd0_en_d2; +wire bank3_ram1_data_rd1_valid = bank3_ram1_data_rd1_en_d2; +wire bank4_ram0_data_rd0_valid = bank4_ram0_data_rd0_en_d2; +wire bank4_ram0_data_rd1_valid = bank4_ram0_data_rd1_en_d2; +wire bank4_ram1_data_rd0_valid = bank4_ram1_data_rd0_en_d2; +wire bank4_ram1_data_rd1_valid = bank4_ram1_data_rd1_en_d2; +wire bank5_ram0_data_rd0_valid = bank5_ram0_data_rd0_en_d2; +wire bank5_ram0_data_rd1_valid = bank5_ram0_data_rd1_en_d2; +wire bank5_ram1_data_rd0_valid = bank5_ram1_data_rd0_en_d2; +wire bank5_ram1_data_rd1_valid = bank5_ram1_data_rd1_en_d2; +wire bank6_ram0_data_rd0_valid = bank6_ram0_data_rd0_en_d2; +wire bank6_ram0_data_rd1_valid = bank6_ram0_data_rd1_en_d2; +wire bank6_ram1_data_rd0_valid = bank6_ram1_data_rd0_en_d2; +wire bank6_ram1_data_rd1_valid = bank6_ram1_data_rd1_en_d2; +wire bank7_ram0_data_rd0_valid = bank7_ram0_data_rd0_en_d2; +wire bank7_ram0_data_rd1_valid = bank7_ram0_data_rd1_en_d2; +wire bank7_ram1_data_rd0_valid = bank7_ram1_data_rd0_en_d2; +wire bank7_ram1_data_rd1_valid = bank7_ram1_data_rd1_en_d2; +wire bank8_ram0_data_rd0_valid = bank8_ram0_data_rd0_en_d2; +wire bank8_ram0_data_rd1_valid = bank8_ram0_data_rd1_en_d2; +wire bank8_ram1_data_rd0_valid = bank8_ram1_data_rd0_en_d2; +wire bank8_ram1_data_rd1_valid = bank8_ram1_data_rd1_en_d2; +wire bank9_ram0_data_rd0_valid = bank9_ram0_data_rd0_en_d2; +wire bank9_ram0_data_rd1_valid = bank9_ram0_data_rd1_en_d2; +wire bank9_ram1_data_rd0_valid = bank9_ram1_data_rd0_en_d2; +wire bank9_ram1_data_rd1_valid = bank9_ram1_data_rd1_en_d2; +wire bank10_ram0_data_rd0_valid = bank10_ram0_data_rd0_en_d2; +wire bank10_ram0_data_rd1_valid = bank10_ram0_data_rd1_en_d2; +wire bank10_ram1_data_rd0_valid = bank10_ram1_data_rd0_en_d2; +wire bank10_ram1_data_rd1_valid = bank10_ram1_data_rd1_en_d2; +wire bank11_ram0_data_rd0_valid = bank11_ram0_data_rd0_en_d2; +wire bank11_ram0_data_rd1_valid = bank11_ram0_data_rd1_en_d2; +wire bank11_ram1_data_rd0_valid = bank11_ram1_data_rd0_en_d2; +wire bank11_ram1_data_rd1_valid = bank11_ram1_data_rd1_en_d2; +wire bank12_ram0_data_rd0_valid = bank12_ram0_data_rd0_en_d2; +wire bank12_ram0_data_rd1_valid = bank12_ram0_data_rd1_en_d2; +wire bank12_ram1_data_rd0_valid = bank12_ram1_data_rd0_en_d2; +wire bank12_ram1_data_rd1_valid = bank12_ram1_data_rd1_en_d2; +wire bank13_ram0_data_rd0_valid = bank13_ram0_data_rd0_en_d2; +wire bank13_ram0_data_rd1_valid = bank13_ram0_data_rd1_en_d2; +wire bank13_ram1_data_rd0_valid = bank13_ram1_data_rd0_en_d2; +wire bank13_ram1_data_rd1_valid = bank13_ram1_data_rd1_en_d2; +wire bank14_ram0_data_rd0_valid = bank14_ram0_data_rd0_en_d2; +wire bank14_ram0_data_rd1_valid = bank14_ram0_data_rd1_en_d2; +wire bank14_ram1_data_rd0_valid = bank14_ram1_data_rd0_en_d2; +wire bank14_ram1_data_rd1_valid = bank14_ram1_data_rd1_en_d2; +wire bank15_ram0_data_rd0_valid = bank15_ram0_data_rd0_en_d2; +wire bank15_ram0_data_rd1_valid = bank15_ram0_data_rd1_en_d2; +wire bank15_ram1_data_rd0_valid = bank15_ram1_data_rd0_en_d2; +wire bank15_ram1_data_rd1_valid = bank15_ram1_data_rd1_en_d2; +wire bank16_ram0_data_rd0_valid = bank16_ram0_data_rd0_en_d2; +wire bank16_ram0_data_rd1_valid = bank16_ram0_data_rd1_en_d2; +wire bank16_ram1_data_rd0_valid = bank16_ram1_data_rd0_en_d2; +wire bank16_ram1_data_rd1_valid = bank16_ram1_data_rd1_en_d2; +wire bank17_ram0_data_rd0_valid = bank17_ram0_data_rd0_en_d2; +wire bank17_ram0_data_rd1_valid = bank17_ram0_data_rd1_en_d2; +wire bank17_ram1_data_rd0_valid = bank17_ram1_data_rd0_en_d2; +wire bank17_ram1_data_rd1_valid = bank17_ram1_data_rd1_en_d2; +wire bank18_ram0_data_rd0_valid = bank18_ram0_data_rd0_en_d2; +wire bank18_ram0_data_rd1_valid = bank18_ram0_data_rd1_en_d2; +wire bank18_ram1_data_rd0_valid = bank18_ram1_data_rd0_en_d2; +wire bank18_ram1_data_rd1_valid = bank18_ram1_data_rd1_en_d2; +wire bank19_ram0_data_rd0_valid = bank19_ram0_data_rd0_en_d2; +wire bank19_ram0_data_rd1_valid = bank19_ram0_data_rd1_en_d2; +wire bank19_ram1_data_rd0_valid = bank19_ram1_data_rd0_en_d2; +wire bank19_ram1_data_rd1_valid = bank19_ram1_data_rd1_en_d2; +wire bank20_ram0_data_rd0_valid = bank20_ram0_data_rd0_en_d2; +wire bank20_ram0_data_rd1_valid = bank20_ram0_data_rd1_en_d2; +wire bank20_ram1_data_rd0_valid = bank20_ram1_data_rd0_en_d2; +wire bank20_ram1_data_rd1_valid = bank20_ram1_data_rd1_en_d2; +wire bank21_ram0_data_rd0_valid = bank21_ram0_data_rd0_en_d2; +wire bank21_ram0_data_rd1_valid = bank21_ram0_data_rd1_en_d2; +wire bank21_ram1_data_rd0_valid = bank21_ram1_data_rd0_en_d2; +wire bank21_ram1_data_rd1_valid = bank21_ram1_data_rd1_en_d2; +wire bank22_ram0_data_rd0_valid = bank22_ram0_data_rd0_en_d2; +wire bank22_ram0_data_rd1_valid = bank22_ram0_data_rd1_en_d2; +wire bank22_ram1_data_rd0_valid = bank22_ram1_data_rd0_en_d2; +wire bank22_ram1_data_rd1_valid = bank22_ram1_data_rd1_en_d2; +wire bank23_ram0_data_rd0_valid = bank23_ram0_data_rd0_en_d2; +wire bank23_ram0_data_rd1_valid = bank23_ram0_data_rd1_en_d2; +wire bank23_ram1_data_rd0_valid = bank23_ram1_data_rd0_en_d2; +wire bank23_ram1_data_rd1_valid = bank23_ram1_data_rd1_en_d2; +wire bank24_ram0_data_rd0_valid = bank24_ram0_data_rd0_en_d2; +wire bank24_ram0_data_rd1_valid = bank24_ram0_data_rd1_en_d2; +wire bank24_ram1_data_rd0_valid = bank24_ram1_data_rd0_en_d2; +wire bank24_ram1_data_rd1_valid = bank24_ram1_data_rd1_en_d2; +wire bank25_ram0_data_rd0_valid = bank25_ram0_data_rd0_en_d2; +wire bank25_ram0_data_rd1_valid = bank25_ram0_data_rd1_en_d2; +wire bank25_ram1_data_rd0_valid = bank25_ram1_data_rd0_en_d2; +wire bank25_ram1_data_rd1_valid = bank25_ram1_data_rd1_en_d2; +wire bank26_ram0_data_rd0_valid = bank26_ram0_data_rd0_en_d2; +wire bank26_ram0_data_rd1_valid = bank26_ram0_data_rd1_en_d2; +wire bank26_ram1_data_rd0_valid = bank26_ram1_data_rd0_en_d2; +wire bank26_ram1_data_rd1_valid = bank26_ram1_data_rd1_en_d2; +wire bank27_ram0_data_rd0_valid = bank27_ram0_data_rd0_en_d2; +wire bank27_ram0_data_rd1_valid = bank27_ram0_data_rd1_en_d2; +wire bank27_ram1_data_rd0_valid = bank27_ram1_data_rd0_en_d2; +wire bank27_ram1_data_rd1_valid = bank27_ram1_data_rd1_en_d2; +wire bank28_ram0_data_rd0_valid = bank28_ram0_data_rd0_en_d2; +wire bank28_ram0_data_rd1_valid = bank28_ram0_data_rd1_en_d2; +wire bank28_ram1_data_rd0_valid = bank28_ram1_data_rd0_en_d2; +wire bank28_ram1_data_rd1_valid = bank28_ram1_data_rd1_en_d2; +wire bank29_ram0_data_rd0_valid = bank29_ram0_data_rd0_en_d2; +wire bank29_ram0_data_rd1_valid = bank29_ram0_data_rd1_en_d2; +wire bank29_ram1_data_rd0_valid = bank29_ram1_data_rd0_en_d2; +wire bank29_ram1_data_rd1_valid = bank29_ram1_data_rd1_en_d2; +wire bank30_ram0_data_rd0_valid = bank30_ram0_data_rd0_en_d2; +wire bank30_ram0_data_rd1_valid = bank30_ram0_data_rd1_en_d2; +wire bank30_ram1_data_rd0_valid = bank30_ram1_data_rd0_en_d2; +wire bank30_ram1_data_rd1_valid = bank30_ram1_data_rd1_en_d2; +wire bank31_ram0_data_rd0_valid = bank31_ram0_data_rd0_en_d2; +wire bank31_ram0_data_rd1_valid = bank31_ram0_data_rd1_en_d2; +wire bank31_ram1_data_rd0_valid = bank31_ram1_data_rd0_en_d2; +wire bank31_ram1_data_rd1_valid = bank31_ram1_data_rd1_en_d2; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sc data read valid. +//: my $t1=""; +//: my $t2=""; +//: if((2==0)||(2==1)||(2==4)){ +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: $t1 .= "bank${j}_ram${k}_data_rd_valid|"; +//: } +//: } +//: print "wire [0:0] sc2buf_dat_rd_valid_w = $t1"."1'b0; \n"; +//: } +//: if((2==2)||(2==3)){ +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: $t1 .= "bank${j}_ram${k}_data_rd0_valid|"; +//: $t2 .= "bank${j}_ram${k}_data_rd1_valid|"; +//: } +//: } +//: print "wire sc2buf_dat_rd_valid0 = ${t1}"."1'b0; \n"; +//: print "wire sc2buf_dat_rd_valid1 = ${t2}"."1'b0; \n"; +//: print "wire [0:0] sc2buf_dat_rd_valid_w = sc2buf_dat_rd_valid0 || sc2buf_dat_rd_valid1; \n"; +//: } +//: &eperl::retime("-O sc2buf_dat_rd_valid -i sc2buf_dat_rd_valid_w -stage 4 -clk nvdla_core_clk"); +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: print qq( +//: wire [64 -1:0] bank${j}_ram${k}_rd_data; ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire sc2buf_dat_rd_valid0 = bank0_ram0_data_rd0_valid|bank0_ram1_data_rd0_valid|bank1_ram0_data_rd0_valid|bank1_ram1_data_rd0_valid|bank2_ram0_data_rd0_valid|bank2_ram1_data_rd0_valid|bank3_ram0_data_rd0_valid|bank3_ram1_data_rd0_valid|bank4_ram0_data_rd0_valid|bank4_ram1_data_rd0_valid|bank5_ram0_data_rd0_valid|bank5_ram1_data_rd0_valid|bank6_ram0_data_rd0_valid|bank6_ram1_data_rd0_valid|bank7_ram0_data_rd0_valid|bank7_ram1_data_rd0_valid|bank8_ram0_data_rd0_valid|bank8_ram1_data_rd0_valid|bank9_ram0_data_rd0_valid|bank9_ram1_data_rd0_valid|bank10_ram0_data_rd0_valid|bank10_ram1_data_rd0_valid|bank11_ram0_data_rd0_valid|bank11_ram1_data_rd0_valid|bank12_ram0_data_rd0_valid|bank12_ram1_data_rd0_valid|bank13_ram0_data_rd0_valid|bank13_ram1_data_rd0_valid|bank14_ram0_data_rd0_valid|bank14_ram1_data_rd0_valid|bank15_ram0_data_rd0_valid|bank15_ram1_data_rd0_valid|bank16_ram0_data_rd0_valid|bank16_ram1_data_rd0_valid|bank17_ram0_data_rd0_valid|bank17_ram1_data_rd0_valid|bank18_ram0_data_rd0_valid|bank18_ram1_data_rd0_valid|bank19_ram0_data_rd0_valid|bank19_ram1_data_rd0_valid|bank20_ram0_data_rd0_valid|bank20_ram1_data_rd0_valid|bank21_ram0_data_rd0_valid|bank21_ram1_data_rd0_valid|bank22_ram0_data_rd0_valid|bank22_ram1_data_rd0_valid|bank23_ram0_data_rd0_valid|bank23_ram1_data_rd0_valid|bank24_ram0_data_rd0_valid|bank24_ram1_data_rd0_valid|bank25_ram0_data_rd0_valid|bank25_ram1_data_rd0_valid|bank26_ram0_data_rd0_valid|bank26_ram1_data_rd0_valid|bank27_ram0_data_rd0_valid|bank27_ram1_data_rd0_valid|bank28_ram0_data_rd0_valid|bank28_ram1_data_rd0_valid|bank29_ram0_data_rd0_valid|bank29_ram1_data_rd0_valid|bank30_ram0_data_rd0_valid|bank30_ram1_data_rd0_valid|bank31_ram0_data_rd0_valid|bank31_ram1_data_rd0_valid|1'b0; +wire sc2buf_dat_rd_valid1 = bank0_ram0_data_rd1_valid|bank0_ram1_data_rd1_valid|bank1_ram0_data_rd1_valid|bank1_ram1_data_rd1_valid|bank2_ram0_data_rd1_valid|bank2_ram1_data_rd1_valid|bank3_ram0_data_rd1_valid|bank3_ram1_data_rd1_valid|bank4_ram0_data_rd1_valid|bank4_ram1_data_rd1_valid|bank5_ram0_data_rd1_valid|bank5_ram1_data_rd1_valid|bank6_ram0_data_rd1_valid|bank6_ram1_data_rd1_valid|bank7_ram0_data_rd1_valid|bank7_ram1_data_rd1_valid|bank8_ram0_data_rd1_valid|bank8_ram1_data_rd1_valid|bank9_ram0_data_rd1_valid|bank9_ram1_data_rd1_valid|bank10_ram0_data_rd1_valid|bank10_ram1_data_rd1_valid|bank11_ram0_data_rd1_valid|bank11_ram1_data_rd1_valid|bank12_ram0_data_rd1_valid|bank12_ram1_data_rd1_valid|bank13_ram0_data_rd1_valid|bank13_ram1_data_rd1_valid|bank14_ram0_data_rd1_valid|bank14_ram1_data_rd1_valid|bank15_ram0_data_rd1_valid|bank15_ram1_data_rd1_valid|bank16_ram0_data_rd1_valid|bank16_ram1_data_rd1_valid|bank17_ram0_data_rd1_valid|bank17_ram1_data_rd1_valid|bank18_ram0_data_rd1_valid|bank18_ram1_data_rd1_valid|bank19_ram0_data_rd1_valid|bank19_ram1_data_rd1_valid|bank20_ram0_data_rd1_valid|bank20_ram1_data_rd1_valid|bank21_ram0_data_rd1_valid|bank21_ram1_data_rd1_valid|bank22_ram0_data_rd1_valid|bank22_ram1_data_rd1_valid|bank23_ram0_data_rd1_valid|bank23_ram1_data_rd1_valid|bank24_ram0_data_rd1_valid|bank24_ram1_data_rd1_valid|bank25_ram0_data_rd1_valid|bank25_ram1_data_rd1_valid|bank26_ram0_data_rd1_valid|bank26_ram1_data_rd1_valid|bank27_ram0_data_rd1_valid|bank27_ram1_data_rd1_valid|bank28_ram0_data_rd1_valid|bank28_ram1_data_rd1_valid|bank29_ram0_data_rd1_valid|bank29_ram1_data_rd1_valid|bank30_ram0_data_rd1_valid|bank30_ram1_data_rd1_valid|bank31_ram0_data_rd1_valid|bank31_ram1_data_rd1_valid|1'b0; +wire [0:0] sc2buf_dat_rd_valid_w = sc2buf_dat_rd_valid0 || sc2buf_dat_rd_valid1; +reg sc2buf_dat_rd_valid_w_d1; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_valid_w_d1 <= sc2buf_dat_rd_valid_w; +end + +reg sc2buf_dat_rd_valid_w_d2; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_valid_w_d2 <= sc2buf_dat_rd_valid_w_d1; +end + +reg sc2buf_dat_rd_valid_w_d3; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_valid_w_d3 <= sc2buf_dat_rd_valid_w_d2; +end + +reg sc2buf_dat_rd_valid_w_d4; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_valid_w_d4 <= sc2buf_dat_rd_valid_w_d3; +end + +wire sc2buf_dat_rd_valid; +assign sc2buf_dat_rd_valid = sc2buf_dat_rd_valid_w_d4; + + +wire [64 -1:0] bank0_ram0_rd_data; +wire [64 -1:0] bank0_ram1_rd_data; +wire [64 -1:0] bank1_ram0_rd_data; +wire [64 -1:0] bank1_ram1_rd_data; +wire [64 -1:0] bank2_ram0_rd_data; +wire [64 -1:0] bank2_ram1_rd_data; +wire [64 -1:0] bank3_ram0_rd_data; +wire [64 -1:0] bank3_ram1_rd_data; +wire [64 -1:0] bank4_ram0_rd_data; +wire [64 -1:0] bank4_ram1_rd_data; +wire [64 -1:0] bank5_ram0_rd_data; +wire [64 -1:0] bank5_ram1_rd_data; +wire [64 -1:0] bank6_ram0_rd_data; +wire [64 -1:0] bank6_ram1_rd_data; +wire [64 -1:0] bank7_ram0_rd_data; +wire [64 -1:0] bank7_ram1_rd_data; +wire [64 -1:0] bank8_ram0_rd_data; +wire [64 -1:0] bank8_ram1_rd_data; +wire [64 -1:0] bank9_ram0_rd_data; +wire [64 -1:0] bank9_ram1_rd_data; +wire [64 -1:0] bank10_ram0_rd_data; +wire [64 -1:0] bank10_ram1_rd_data; +wire [64 -1:0] bank11_ram0_rd_data; +wire [64 -1:0] bank11_ram1_rd_data; +wire [64 -1:0] bank12_ram0_rd_data; +wire [64 -1:0] bank12_ram1_rd_data; +wire [64 -1:0] bank13_ram0_rd_data; +wire [64 -1:0] bank13_ram1_rd_data; +wire [64 -1:0] bank14_ram0_rd_data; +wire [64 -1:0] bank14_ram1_rd_data; +wire [64 -1:0] bank15_ram0_rd_data; +wire [64 -1:0] bank15_ram1_rd_data; +wire [64 -1:0] bank16_ram0_rd_data; +wire [64 -1:0] bank16_ram1_rd_data; +wire [64 -1:0] bank17_ram0_rd_data; +wire [64 -1:0] bank17_ram1_rd_data; +wire [64 -1:0] bank18_ram0_rd_data; +wire [64 -1:0] bank18_ram1_rd_data; +wire [64 -1:0] bank19_ram0_rd_data; +wire [64 -1:0] bank19_ram1_rd_data; +wire [64 -1:0] bank20_ram0_rd_data; +wire [64 -1:0] bank20_ram1_rd_data; +wire [64 -1:0] bank21_ram0_rd_data; +wire [64 -1:0] bank21_ram1_rd_data; +wire [64 -1:0] bank22_ram0_rd_data; +wire [64 -1:0] bank22_ram1_rd_data; +wire [64 -1:0] bank23_ram0_rd_data; +wire [64 -1:0] bank23_ram1_rd_data; +wire [64 -1:0] bank24_ram0_rd_data; +wire [64 -1:0] bank24_ram1_rd_data; +wire [64 -1:0] bank25_ram0_rd_data; +wire [64 -1:0] bank25_ram1_rd_data; +wire [64 -1:0] bank26_ram0_rd_data; +wire [64 -1:0] bank26_ram1_rd_data; +wire [64 -1:0] bank27_ram0_rd_data; +wire [64 -1:0] bank27_ram1_rd_data; +wire [64 -1:0] bank28_ram0_rd_data; +wire [64 -1:0] bank28_ram1_rd_data; +wire [64 -1:0] bank29_ram0_rd_data; +wire [64 -1:0] bank29_ram1_rd_data; +wire [64 -1:0] bank30_ram0_rd_data; +wire [64 -1:0] bank30_ram1_rd_data; +wire [64 -1:0] bank31_ram0_rd_data; +wire [64 -1:0] bank31_ram1_rd_data; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sc data read bank output data. +//: my $t1=""; +//: my $kk=64; +//: if(2==0){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd_data = bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd_valid}}; ); +//: } +//: } +//: if(2==1){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd_valid}}}; +//: ); +//: } +//: } +//: if(2==2){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd0_data = (bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd0_valid}})| +//: (bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd0_valid}}); +//: wire [${kk}-1:0] bank${j}_data_rd1_data = (bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd1_valid}})| +//: (bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd1_valid}}); +//: ); +//: } +//: } +//: if(2==3){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd0_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd0_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd0_valid}}}| +//: {bank${j}_ram3_rd_data&{64{bank${j}_ram3_data_rd0_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_data_rd0_valid}}}; +//: wire [${kk}-1:0] bank${j}_data_rd1_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd1_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd1_valid}}}| +//: {bank${j}_ram3_rd_data&{64{bank${j}_ram3_data_rd1_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_data_rd1_valid}}}; +//: ); +//: } +//: } +//: if(2==4){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd_data = {bank${j}_ram3_rd_data&{64{bank${j}_ram3_data_rd_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_data_rd_valid}}, +//: bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd_valid}}}; +//: ); +//: } +//: } +//: my $kk=7; +//: &eperl::retime("-O sc2buf_dat_rd_shift_5T -i sc2buf_dat_rd_shift -wid ${kk} -stage 5 -clk nvdla_core_clk"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [64-1:0] bank0_data_rd0_data = (bank0_ram1_rd_data&{64{bank0_ram1_data_rd0_valid}})| +(bank0_ram0_rd_data&{64{bank0_ram0_data_rd0_valid}}); +wire [64-1:0] bank0_data_rd1_data = (bank0_ram1_rd_data&{64{bank0_ram1_data_rd1_valid}})| +(bank0_ram0_rd_data&{64{bank0_ram0_data_rd1_valid}}); + +wire [64-1:0] bank1_data_rd0_data = (bank1_ram1_rd_data&{64{bank1_ram1_data_rd0_valid}})| +(bank1_ram0_rd_data&{64{bank1_ram0_data_rd0_valid}}); +wire [64-1:0] bank1_data_rd1_data = (bank1_ram1_rd_data&{64{bank1_ram1_data_rd1_valid}})| +(bank1_ram0_rd_data&{64{bank1_ram0_data_rd1_valid}}); + +wire [64-1:0] bank2_data_rd0_data = (bank2_ram1_rd_data&{64{bank2_ram1_data_rd0_valid}})| +(bank2_ram0_rd_data&{64{bank2_ram0_data_rd0_valid}}); +wire [64-1:0] bank2_data_rd1_data = (bank2_ram1_rd_data&{64{bank2_ram1_data_rd1_valid}})| +(bank2_ram0_rd_data&{64{bank2_ram0_data_rd1_valid}}); + +wire [64-1:0] bank3_data_rd0_data = (bank3_ram1_rd_data&{64{bank3_ram1_data_rd0_valid}})| +(bank3_ram0_rd_data&{64{bank3_ram0_data_rd0_valid}}); +wire [64-1:0] bank3_data_rd1_data = (bank3_ram1_rd_data&{64{bank3_ram1_data_rd1_valid}})| +(bank3_ram0_rd_data&{64{bank3_ram0_data_rd1_valid}}); + +wire [64-1:0] bank4_data_rd0_data = (bank4_ram1_rd_data&{64{bank4_ram1_data_rd0_valid}})| +(bank4_ram0_rd_data&{64{bank4_ram0_data_rd0_valid}}); +wire [64-1:0] bank4_data_rd1_data = (bank4_ram1_rd_data&{64{bank4_ram1_data_rd1_valid}})| +(bank4_ram0_rd_data&{64{bank4_ram0_data_rd1_valid}}); + +wire [64-1:0] bank5_data_rd0_data = (bank5_ram1_rd_data&{64{bank5_ram1_data_rd0_valid}})| +(bank5_ram0_rd_data&{64{bank5_ram0_data_rd0_valid}}); +wire [64-1:0] bank5_data_rd1_data = (bank5_ram1_rd_data&{64{bank5_ram1_data_rd1_valid}})| +(bank5_ram0_rd_data&{64{bank5_ram0_data_rd1_valid}}); + +wire [64-1:0] bank6_data_rd0_data = (bank6_ram1_rd_data&{64{bank6_ram1_data_rd0_valid}})| +(bank6_ram0_rd_data&{64{bank6_ram0_data_rd0_valid}}); +wire [64-1:0] bank6_data_rd1_data = (bank6_ram1_rd_data&{64{bank6_ram1_data_rd1_valid}})| +(bank6_ram0_rd_data&{64{bank6_ram0_data_rd1_valid}}); + +wire [64-1:0] bank7_data_rd0_data = (bank7_ram1_rd_data&{64{bank7_ram1_data_rd0_valid}})| +(bank7_ram0_rd_data&{64{bank7_ram0_data_rd0_valid}}); +wire [64-1:0] bank7_data_rd1_data = (bank7_ram1_rd_data&{64{bank7_ram1_data_rd1_valid}})| +(bank7_ram0_rd_data&{64{bank7_ram0_data_rd1_valid}}); + +wire [64-1:0] bank8_data_rd0_data = (bank8_ram1_rd_data&{64{bank8_ram1_data_rd0_valid}})| +(bank8_ram0_rd_data&{64{bank8_ram0_data_rd0_valid}}); +wire [64-1:0] bank8_data_rd1_data = (bank8_ram1_rd_data&{64{bank8_ram1_data_rd1_valid}})| +(bank8_ram0_rd_data&{64{bank8_ram0_data_rd1_valid}}); + +wire [64-1:0] bank9_data_rd0_data = (bank9_ram1_rd_data&{64{bank9_ram1_data_rd0_valid}})| +(bank9_ram0_rd_data&{64{bank9_ram0_data_rd0_valid}}); +wire [64-1:0] bank9_data_rd1_data = (bank9_ram1_rd_data&{64{bank9_ram1_data_rd1_valid}})| +(bank9_ram0_rd_data&{64{bank9_ram0_data_rd1_valid}}); + +wire [64-1:0] bank10_data_rd0_data = (bank10_ram1_rd_data&{64{bank10_ram1_data_rd0_valid}})| +(bank10_ram0_rd_data&{64{bank10_ram0_data_rd0_valid}}); +wire [64-1:0] bank10_data_rd1_data = (bank10_ram1_rd_data&{64{bank10_ram1_data_rd1_valid}})| +(bank10_ram0_rd_data&{64{bank10_ram0_data_rd1_valid}}); + +wire [64-1:0] bank11_data_rd0_data = (bank11_ram1_rd_data&{64{bank11_ram1_data_rd0_valid}})| +(bank11_ram0_rd_data&{64{bank11_ram0_data_rd0_valid}}); +wire [64-1:0] bank11_data_rd1_data = (bank11_ram1_rd_data&{64{bank11_ram1_data_rd1_valid}})| +(bank11_ram0_rd_data&{64{bank11_ram0_data_rd1_valid}}); + +wire [64-1:0] bank12_data_rd0_data = (bank12_ram1_rd_data&{64{bank12_ram1_data_rd0_valid}})| +(bank12_ram0_rd_data&{64{bank12_ram0_data_rd0_valid}}); +wire [64-1:0] bank12_data_rd1_data = (bank12_ram1_rd_data&{64{bank12_ram1_data_rd1_valid}})| +(bank12_ram0_rd_data&{64{bank12_ram0_data_rd1_valid}}); + +wire [64-1:0] bank13_data_rd0_data = (bank13_ram1_rd_data&{64{bank13_ram1_data_rd0_valid}})| +(bank13_ram0_rd_data&{64{bank13_ram0_data_rd0_valid}}); +wire [64-1:0] bank13_data_rd1_data = (bank13_ram1_rd_data&{64{bank13_ram1_data_rd1_valid}})| +(bank13_ram0_rd_data&{64{bank13_ram0_data_rd1_valid}}); + +wire [64-1:0] bank14_data_rd0_data = (bank14_ram1_rd_data&{64{bank14_ram1_data_rd0_valid}})| +(bank14_ram0_rd_data&{64{bank14_ram0_data_rd0_valid}}); +wire [64-1:0] bank14_data_rd1_data = (bank14_ram1_rd_data&{64{bank14_ram1_data_rd1_valid}})| +(bank14_ram0_rd_data&{64{bank14_ram0_data_rd1_valid}}); + +wire [64-1:0] bank15_data_rd0_data = (bank15_ram1_rd_data&{64{bank15_ram1_data_rd0_valid}})| +(bank15_ram0_rd_data&{64{bank15_ram0_data_rd0_valid}}); +wire [64-1:0] bank15_data_rd1_data = (bank15_ram1_rd_data&{64{bank15_ram1_data_rd1_valid}})| +(bank15_ram0_rd_data&{64{bank15_ram0_data_rd1_valid}}); + +wire [64-1:0] bank16_data_rd0_data = (bank16_ram1_rd_data&{64{bank16_ram1_data_rd0_valid}})| +(bank16_ram0_rd_data&{64{bank16_ram0_data_rd0_valid}}); +wire [64-1:0] bank16_data_rd1_data = (bank16_ram1_rd_data&{64{bank16_ram1_data_rd1_valid}})| +(bank16_ram0_rd_data&{64{bank16_ram0_data_rd1_valid}}); + +wire [64-1:0] bank17_data_rd0_data = (bank17_ram1_rd_data&{64{bank17_ram1_data_rd0_valid}})| +(bank17_ram0_rd_data&{64{bank17_ram0_data_rd0_valid}}); +wire [64-1:0] bank17_data_rd1_data = (bank17_ram1_rd_data&{64{bank17_ram1_data_rd1_valid}})| +(bank17_ram0_rd_data&{64{bank17_ram0_data_rd1_valid}}); + +wire [64-1:0] bank18_data_rd0_data = (bank18_ram1_rd_data&{64{bank18_ram1_data_rd0_valid}})| +(bank18_ram0_rd_data&{64{bank18_ram0_data_rd0_valid}}); +wire [64-1:0] bank18_data_rd1_data = (bank18_ram1_rd_data&{64{bank18_ram1_data_rd1_valid}})| +(bank18_ram0_rd_data&{64{bank18_ram0_data_rd1_valid}}); + +wire [64-1:0] bank19_data_rd0_data = (bank19_ram1_rd_data&{64{bank19_ram1_data_rd0_valid}})| +(bank19_ram0_rd_data&{64{bank19_ram0_data_rd0_valid}}); +wire [64-1:0] bank19_data_rd1_data = (bank19_ram1_rd_data&{64{bank19_ram1_data_rd1_valid}})| +(bank19_ram0_rd_data&{64{bank19_ram0_data_rd1_valid}}); + +wire [64-1:0] bank20_data_rd0_data = (bank20_ram1_rd_data&{64{bank20_ram1_data_rd0_valid}})| +(bank20_ram0_rd_data&{64{bank20_ram0_data_rd0_valid}}); +wire [64-1:0] bank20_data_rd1_data = (bank20_ram1_rd_data&{64{bank20_ram1_data_rd1_valid}})| +(bank20_ram0_rd_data&{64{bank20_ram0_data_rd1_valid}}); + +wire [64-1:0] bank21_data_rd0_data = (bank21_ram1_rd_data&{64{bank21_ram1_data_rd0_valid}})| +(bank21_ram0_rd_data&{64{bank21_ram0_data_rd0_valid}}); +wire [64-1:0] bank21_data_rd1_data = (bank21_ram1_rd_data&{64{bank21_ram1_data_rd1_valid}})| +(bank21_ram0_rd_data&{64{bank21_ram0_data_rd1_valid}}); + +wire [64-1:0] bank22_data_rd0_data = (bank22_ram1_rd_data&{64{bank22_ram1_data_rd0_valid}})| +(bank22_ram0_rd_data&{64{bank22_ram0_data_rd0_valid}}); +wire [64-1:0] bank22_data_rd1_data = (bank22_ram1_rd_data&{64{bank22_ram1_data_rd1_valid}})| +(bank22_ram0_rd_data&{64{bank22_ram0_data_rd1_valid}}); + +wire [64-1:0] bank23_data_rd0_data = (bank23_ram1_rd_data&{64{bank23_ram1_data_rd0_valid}})| +(bank23_ram0_rd_data&{64{bank23_ram0_data_rd0_valid}}); +wire [64-1:0] bank23_data_rd1_data = (bank23_ram1_rd_data&{64{bank23_ram1_data_rd1_valid}})| +(bank23_ram0_rd_data&{64{bank23_ram0_data_rd1_valid}}); + +wire [64-1:0] bank24_data_rd0_data = (bank24_ram1_rd_data&{64{bank24_ram1_data_rd0_valid}})| +(bank24_ram0_rd_data&{64{bank24_ram0_data_rd0_valid}}); +wire [64-1:0] bank24_data_rd1_data = (bank24_ram1_rd_data&{64{bank24_ram1_data_rd1_valid}})| +(bank24_ram0_rd_data&{64{bank24_ram0_data_rd1_valid}}); + +wire [64-1:0] bank25_data_rd0_data = (bank25_ram1_rd_data&{64{bank25_ram1_data_rd0_valid}})| +(bank25_ram0_rd_data&{64{bank25_ram0_data_rd0_valid}}); +wire [64-1:0] bank25_data_rd1_data = (bank25_ram1_rd_data&{64{bank25_ram1_data_rd1_valid}})| +(bank25_ram0_rd_data&{64{bank25_ram0_data_rd1_valid}}); + +wire [64-1:0] bank26_data_rd0_data = (bank26_ram1_rd_data&{64{bank26_ram1_data_rd0_valid}})| +(bank26_ram0_rd_data&{64{bank26_ram0_data_rd0_valid}}); +wire [64-1:0] bank26_data_rd1_data = (bank26_ram1_rd_data&{64{bank26_ram1_data_rd1_valid}})| +(bank26_ram0_rd_data&{64{bank26_ram0_data_rd1_valid}}); + +wire [64-1:0] bank27_data_rd0_data = (bank27_ram1_rd_data&{64{bank27_ram1_data_rd0_valid}})| +(bank27_ram0_rd_data&{64{bank27_ram0_data_rd0_valid}}); +wire [64-1:0] bank27_data_rd1_data = (bank27_ram1_rd_data&{64{bank27_ram1_data_rd1_valid}})| +(bank27_ram0_rd_data&{64{bank27_ram0_data_rd1_valid}}); + +wire [64-1:0] bank28_data_rd0_data = (bank28_ram1_rd_data&{64{bank28_ram1_data_rd0_valid}})| +(bank28_ram0_rd_data&{64{bank28_ram0_data_rd0_valid}}); +wire [64-1:0] bank28_data_rd1_data = (bank28_ram1_rd_data&{64{bank28_ram1_data_rd1_valid}})| +(bank28_ram0_rd_data&{64{bank28_ram0_data_rd1_valid}}); + +wire [64-1:0] bank29_data_rd0_data = (bank29_ram1_rd_data&{64{bank29_ram1_data_rd0_valid}})| +(bank29_ram0_rd_data&{64{bank29_ram0_data_rd0_valid}}); +wire [64-1:0] bank29_data_rd1_data = (bank29_ram1_rd_data&{64{bank29_ram1_data_rd1_valid}})| +(bank29_ram0_rd_data&{64{bank29_ram0_data_rd1_valid}}); + +wire [64-1:0] bank30_data_rd0_data = (bank30_ram1_rd_data&{64{bank30_ram1_data_rd0_valid}})| +(bank30_ram0_rd_data&{64{bank30_ram0_data_rd0_valid}}); +wire [64-1:0] bank30_data_rd1_data = (bank30_ram1_rd_data&{64{bank30_ram1_data_rd1_valid}})| +(bank30_ram0_rd_data&{64{bank30_ram0_data_rd1_valid}}); + +wire [64-1:0] bank31_data_rd0_data = (bank31_ram1_rd_data&{64{bank31_ram1_data_rd0_valid}})| +(bank31_ram0_rd_data&{64{bank31_ram0_data_rd0_valid}}); +wire [64-1:0] bank31_data_rd1_data = (bank31_ram1_rd_data&{64{bank31_ram1_data_rd1_valid}})| +(bank31_ram0_rd_data&{64{bank31_ram0_data_rd1_valid}}); +reg [7-1:0] sc2buf_dat_rd_shift_d1; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_shift_d1[7-1:0] <= sc2buf_dat_rd_shift[7-1:0]; +end + +reg [7-1:0] sc2buf_dat_rd_shift_d2; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_shift_d2[7-1:0] <= sc2buf_dat_rd_shift_d1[7-1:0]; +end + +reg [7-1:0] sc2buf_dat_rd_shift_d3; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_shift_d3[7-1:0] <= sc2buf_dat_rd_shift_d2[7-1:0]; +end + +reg [7-1:0] sc2buf_dat_rd_shift_d4; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_shift_d4[7-1:0] <= sc2buf_dat_rd_shift_d3[7-1:0]; +end + +reg [7-1:0] sc2buf_dat_rd_shift_d5; +always @(posedge nvdla_core_clk) begin + sc2buf_dat_rd_shift_d5[7-1:0] <= sc2buf_dat_rd_shift_d4[7-1:0]; +end + +wire [7-1:0] sc2buf_dat_rd_shift_5T; +assign sc2buf_dat_rd_shift_5T = sc2buf_dat_rd_shift_d5; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// pipe solution. for timing concern, 4 level pipe. +//: my $kk=64; +//: if((2==0)||(2==1)||(2==4)){ +//: for (my $i=0; $i<32; $i++){ +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_data_rd_data -d bank${i}_data_rd_data"); +//: } +//: +//: for (my $i=0; $i<32/4; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l2group${i}_data_rd_data_w = l1group${ni}_data_rd_data | l1group${nii}_data_rd_data | l1group${niii}_data_rd_data | l1group${niiii}_data_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_data_rd_data -d l2group${i}_data_rd_data_w"); +//: } +//: +//: for (my $i=0; $i<32/16; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l3group${i}_data_rd_data_w = l2group${ni}_data_rd_data | l2group${nii}_data_rd_data | l2group${niii}_data_rd_data | l2group${niiii}_data_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_data_rd_data -d l3group${i}_data_rd_data_w"); +//: } +//: +//: if(32==16){ +//: &eperl::flop("-wid ${kk} -norst -q l4group_data_rd_data -d l3group0_data_rd_data"); +//: } +//: if(32==32) { +//: print qq( +//: wire [${kk}-1:0] l4group_data_rd_data_w = l3group0_data_rd_data | l3group1_data_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l4group_data_rd_data -d l4group_data_rd_data_w"); +//: } +//: print "wire[${kk}-1:0] sc2buf_dat_rd_data = l4group_data_rd_data[${kk}-1:0]; \n"; +//: } +//: +//: +//: my $kk=64; +//: if((2==2)||(2==3)){ +//: for (my $i=0; $i<32; $i++){ +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_data_rd0_data -d bank${i}_data_rd0_data"); +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_data_rd1_data -d bank${i}_data_rd1_data"); +//: } +//: +//: for (my $i=0; $i<32/4; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l2group${i}_data_rd0_data_w = l1group${ni}_data_rd0_data | l1group${nii}_data_rd0_data | l1group${niii}_data_rd0_data | l1group${niiii}_data_rd0_data; +//: wire [${kk}-1:0] l2group${i}_data_rd1_data_w = l1group${ni}_data_rd1_data | l1group${nii}_data_rd1_data | l1group${niii}_data_rd1_data | l1group${niiii}_data_rd1_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_data_rd0_data -d l2group${i}_data_rd0_data_w"); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_data_rd1_data -d l2group${i}_data_rd1_data_w"); +//: } +//: +//: for (my $i=0; $i<32/16; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l3group${i}_data_rd0_data_w = l2group${ni}_data_rd0_data | l2group${nii}_data_rd0_data | l2group${niii}_data_rd0_data | l2group${niiii}_data_rd0_data; +//: wire [${kk}-1:0] l3group${i}_data_rd1_data_w = l2group${ni}_data_rd1_data | l2group${nii}_data_rd1_data | l2group${niii}_data_rd1_data | l2group${niiii}_data_rd1_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_data_rd0_data -d l3group${i}_data_rd0_data_w"); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_data_rd1_data -d l3group${i}_data_rd1_data_w"); +//: } +//: +//: if(32==16){ +//: print qq( +//: wire [${kk}-1:0] l4group_data_rd0_data = l3group0_data_rd0_data; +//: wire [${kk}-1:0] l4group_data_rd1_data = l3group0_data_rd1_data; +//: ); +//: } +//: if(32==32) { +//: print qq( +//: wire [${kk}-1:0] l4group_data_rd0_data = l3group0_data_rd0_data | l3group1_data_rd0_data; +//: wire [${kk}-1:0] l4group_data_rd1_data = l3group0_data_rd1_data | l3group1_data_rd1_data; +//: ); +//: } +//: print qq( +//: wire [${kk}*2-1:0] l4group_data_rd_data_w = {l4group_data_rd1_data,l4group_data_rd0_data}>>{sc2buf_dat_rd_shift_5T,3'b0}; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l4group_data_rd_data -d l4group_data_rd_data_w[${kk}-1:0]"); +//: print "wire[${kk}-1:0] sc2buf_dat_rd_data = l4group_data_rd_data[${kk}-1:0]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [63:0] l1group0_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group0_data_rd0_data <= bank0_data_rd0_data; +end +reg [63:0] l1group0_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group0_data_rd1_data <= bank0_data_rd1_data; +end +reg [63:0] l1group1_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group1_data_rd0_data <= bank1_data_rd0_data; +end +reg [63:0] l1group1_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group1_data_rd1_data <= bank1_data_rd1_data; +end +reg [63:0] l1group2_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group2_data_rd0_data <= bank2_data_rd0_data; +end +reg [63:0] l1group2_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group2_data_rd1_data <= bank2_data_rd1_data; +end +reg [63:0] l1group3_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group3_data_rd0_data <= bank3_data_rd0_data; +end +reg [63:0] l1group3_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group3_data_rd1_data <= bank3_data_rd1_data; +end +reg [63:0] l1group4_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group4_data_rd0_data <= bank4_data_rd0_data; +end +reg [63:0] l1group4_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group4_data_rd1_data <= bank4_data_rd1_data; +end +reg [63:0] l1group5_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group5_data_rd0_data <= bank5_data_rd0_data; +end +reg [63:0] l1group5_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group5_data_rd1_data <= bank5_data_rd1_data; +end +reg [63:0] l1group6_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group6_data_rd0_data <= bank6_data_rd0_data; +end +reg [63:0] l1group6_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group6_data_rd1_data <= bank6_data_rd1_data; +end +reg [63:0] l1group7_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group7_data_rd0_data <= bank7_data_rd0_data; +end +reg [63:0] l1group7_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group7_data_rd1_data <= bank7_data_rd1_data; +end +reg [63:0] l1group8_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group8_data_rd0_data <= bank8_data_rd0_data; +end +reg [63:0] l1group8_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group8_data_rd1_data <= bank8_data_rd1_data; +end +reg [63:0] l1group9_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group9_data_rd0_data <= bank9_data_rd0_data; +end +reg [63:0] l1group9_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group9_data_rd1_data <= bank9_data_rd1_data; +end +reg [63:0] l1group10_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group10_data_rd0_data <= bank10_data_rd0_data; +end +reg [63:0] l1group10_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group10_data_rd1_data <= bank10_data_rd1_data; +end +reg [63:0] l1group11_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group11_data_rd0_data <= bank11_data_rd0_data; +end +reg [63:0] l1group11_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group11_data_rd1_data <= bank11_data_rd1_data; +end +reg [63:0] l1group12_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group12_data_rd0_data <= bank12_data_rd0_data; +end +reg [63:0] l1group12_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group12_data_rd1_data <= bank12_data_rd1_data; +end +reg [63:0] l1group13_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group13_data_rd0_data <= bank13_data_rd0_data; +end +reg [63:0] l1group13_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group13_data_rd1_data <= bank13_data_rd1_data; +end +reg [63:0] l1group14_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group14_data_rd0_data <= bank14_data_rd0_data; +end +reg [63:0] l1group14_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group14_data_rd1_data <= bank14_data_rd1_data; +end +reg [63:0] l1group15_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group15_data_rd0_data <= bank15_data_rd0_data; +end +reg [63:0] l1group15_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group15_data_rd1_data <= bank15_data_rd1_data; +end +reg [63:0] l1group16_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group16_data_rd0_data <= bank16_data_rd0_data; +end +reg [63:0] l1group16_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group16_data_rd1_data <= bank16_data_rd1_data; +end +reg [63:0] l1group17_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group17_data_rd0_data <= bank17_data_rd0_data; +end +reg [63:0] l1group17_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group17_data_rd1_data <= bank17_data_rd1_data; +end +reg [63:0] l1group18_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group18_data_rd0_data <= bank18_data_rd0_data; +end +reg [63:0] l1group18_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group18_data_rd1_data <= bank18_data_rd1_data; +end +reg [63:0] l1group19_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group19_data_rd0_data <= bank19_data_rd0_data; +end +reg [63:0] l1group19_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group19_data_rd1_data <= bank19_data_rd1_data; +end +reg [63:0] l1group20_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group20_data_rd0_data <= bank20_data_rd0_data; +end +reg [63:0] l1group20_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group20_data_rd1_data <= bank20_data_rd1_data; +end +reg [63:0] l1group21_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group21_data_rd0_data <= bank21_data_rd0_data; +end +reg [63:0] l1group21_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group21_data_rd1_data <= bank21_data_rd1_data; +end +reg [63:0] l1group22_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group22_data_rd0_data <= bank22_data_rd0_data; +end +reg [63:0] l1group22_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group22_data_rd1_data <= bank22_data_rd1_data; +end +reg [63:0] l1group23_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group23_data_rd0_data <= bank23_data_rd0_data; +end +reg [63:0] l1group23_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group23_data_rd1_data <= bank23_data_rd1_data; +end +reg [63:0] l1group24_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group24_data_rd0_data <= bank24_data_rd0_data; +end +reg [63:0] l1group24_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group24_data_rd1_data <= bank24_data_rd1_data; +end +reg [63:0] l1group25_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group25_data_rd0_data <= bank25_data_rd0_data; +end +reg [63:0] l1group25_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group25_data_rd1_data <= bank25_data_rd1_data; +end +reg [63:0] l1group26_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group26_data_rd0_data <= bank26_data_rd0_data; +end +reg [63:0] l1group26_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group26_data_rd1_data <= bank26_data_rd1_data; +end +reg [63:0] l1group27_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group27_data_rd0_data <= bank27_data_rd0_data; +end +reg [63:0] l1group27_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group27_data_rd1_data <= bank27_data_rd1_data; +end +reg [63:0] l1group28_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group28_data_rd0_data <= bank28_data_rd0_data; +end +reg [63:0] l1group28_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group28_data_rd1_data <= bank28_data_rd1_data; +end +reg [63:0] l1group29_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group29_data_rd0_data <= bank29_data_rd0_data; +end +reg [63:0] l1group29_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group29_data_rd1_data <= bank29_data_rd1_data; +end +reg [63:0] l1group30_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group30_data_rd0_data <= bank30_data_rd0_data; +end +reg [63:0] l1group30_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group30_data_rd1_data <= bank30_data_rd1_data; +end +reg [63:0] l1group31_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l1group31_data_rd0_data <= bank31_data_rd0_data; +end +reg [63:0] l1group31_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l1group31_data_rd1_data <= bank31_data_rd1_data; +end + +wire [64-1:0] l2group0_data_rd0_data_w = l1group0_data_rd0_data | l1group1_data_rd0_data | l1group2_data_rd0_data | l1group3_data_rd0_data; +wire [64-1:0] l2group0_data_rd1_data_w = l1group0_data_rd1_data | l1group1_data_rd1_data | l1group2_data_rd1_data | l1group3_data_rd1_data; +reg [63:0] l2group0_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group0_data_rd0_data <= l2group0_data_rd0_data_w; +end +reg [63:0] l2group0_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group0_data_rd1_data <= l2group0_data_rd1_data_w; +end + +wire [64-1:0] l2group1_data_rd0_data_w = l1group4_data_rd0_data | l1group5_data_rd0_data | l1group6_data_rd0_data | l1group7_data_rd0_data; +wire [64-1:0] l2group1_data_rd1_data_w = l1group4_data_rd1_data | l1group5_data_rd1_data | l1group6_data_rd1_data | l1group7_data_rd1_data; +reg [63:0] l2group1_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group1_data_rd0_data <= l2group1_data_rd0_data_w; +end +reg [63:0] l2group1_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group1_data_rd1_data <= l2group1_data_rd1_data_w; +end + +wire [64-1:0] l2group2_data_rd0_data_w = l1group8_data_rd0_data | l1group9_data_rd0_data | l1group10_data_rd0_data | l1group11_data_rd0_data; +wire [64-1:0] l2group2_data_rd1_data_w = l1group8_data_rd1_data | l1group9_data_rd1_data | l1group10_data_rd1_data | l1group11_data_rd1_data; +reg [63:0] l2group2_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group2_data_rd0_data <= l2group2_data_rd0_data_w; +end +reg [63:0] l2group2_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group2_data_rd1_data <= l2group2_data_rd1_data_w; +end + +wire [64-1:0] l2group3_data_rd0_data_w = l1group12_data_rd0_data | l1group13_data_rd0_data | l1group14_data_rd0_data | l1group15_data_rd0_data; +wire [64-1:0] l2group3_data_rd1_data_w = l1group12_data_rd1_data | l1group13_data_rd1_data | l1group14_data_rd1_data | l1group15_data_rd1_data; +reg [63:0] l2group3_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group3_data_rd0_data <= l2group3_data_rd0_data_w; +end +reg [63:0] l2group3_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group3_data_rd1_data <= l2group3_data_rd1_data_w; +end + +wire [64-1:0] l2group4_data_rd0_data_w = l1group16_data_rd0_data | l1group17_data_rd0_data | l1group18_data_rd0_data | l1group19_data_rd0_data; +wire [64-1:0] l2group4_data_rd1_data_w = l1group16_data_rd1_data | l1group17_data_rd1_data | l1group18_data_rd1_data | l1group19_data_rd1_data; +reg [63:0] l2group4_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group4_data_rd0_data <= l2group4_data_rd0_data_w; +end +reg [63:0] l2group4_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group4_data_rd1_data <= l2group4_data_rd1_data_w; +end + +wire [64-1:0] l2group5_data_rd0_data_w = l1group20_data_rd0_data | l1group21_data_rd0_data | l1group22_data_rd0_data | l1group23_data_rd0_data; +wire [64-1:0] l2group5_data_rd1_data_w = l1group20_data_rd1_data | l1group21_data_rd1_data | l1group22_data_rd1_data | l1group23_data_rd1_data; +reg [63:0] l2group5_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group5_data_rd0_data <= l2group5_data_rd0_data_w; +end +reg [63:0] l2group5_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group5_data_rd1_data <= l2group5_data_rd1_data_w; +end + +wire [64-1:0] l2group6_data_rd0_data_w = l1group24_data_rd0_data | l1group25_data_rd0_data | l1group26_data_rd0_data | l1group27_data_rd0_data; +wire [64-1:0] l2group6_data_rd1_data_w = l1group24_data_rd1_data | l1group25_data_rd1_data | l1group26_data_rd1_data | l1group27_data_rd1_data; +reg [63:0] l2group6_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group6_data_rd0_data <= l2group6_data_rd0_data_w; +end +reg [63:0] l2group6_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group6_data_rd1_data <= l2group6_data_rd1_data_w; +end + +wire [64-1:0] l2group7_data_rd0_data_w = l1group28_data_rd0_data | l1group29_data_rd0_data | l1group30_data_rd0_data | l1group31_data_rd0_data; +wire [64-1:0] l2group7_data_rd1_data_w = l1group28_data_rd1_data | l1group29_data_rd1_data | l1group30_data_rd1_data | l1group31_data_rd1_data; +reg [63:0] l2group7_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l2group7_data_rd0_data <= l2group7_data_rd0_data_w; +end +reg [63:0] l2group7_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l2group7_data_rd1_data <= l2group7_data_rd1_data_w; +end + +wire [64-1:0] l3group0_data_rd0_data_w = l2group0_data_rd0_data | l2group1_data_rd0_data | l2group2_data_rd0_data | l2group3_data_rd0_data; +wire [64-1:0] l3group0_data_rd1_data_w = l2group0_data_rd1_data | l2group1_data_rd1_data | l2group2_data_rd1_data | l2group3_data_rd1_data; +reg [63:0] l3group0_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l3group0_data_rd0_data <= l3group0_data_rd0_data_w; +end +reg [63:0] l3group0_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l3group0_data_rd1_data <= l3group0_data_rd1_data_w; +end + +wire [64-1:0] l3group1_data_rd0_data_w = l2group4_data_rd0_data | l2group5_data_rd0_data | l2group6_data_rd0_data | l2group7_data_rd0_data; +wire [64-1:0] l3group1_data_rd1_data_w = l2group4_data_rd1_data | l2group5_data_rd1_data | l2group6_data_rd1_data | l2group7_data_rd1_data; +reg [63:0] l3group1_data_rd0_data; +always @(posedge nvdla_core_clk) begin + l3group1_data_rd0_data <= l3group1_data_rd0_data_w; +end +reg [63:0] l3group1_data_rd1_data; +always @(posedge nvdla_core_clk) begin + l3group1_data_rd1_data <= l3group1_data_rd1_data_w; +end + +wire [64-1:0] l4group_data_rd0_data = l3group0_data_rd0_data | l3group1_data_rd0_data; +wire [64-1:0] l4group_data_rd1_data = l3group0_data_rd1_data | l3group1_data_rd1_data; + +wire [64*2-1:0] l4group_data_rd_data_w = {l4group_data_rd1_data,l4group_data_rd0_data}>>{sc2buf_dat_rd_shift_5T,3'b0}; +reg [63:0] l4group_data_rd_data; +always @(posedge nvdla_core_clk) begin + l4group_data_rd_data <= l4group_data_rd_data_w[64-1:0]; +end +wire[64-1:0] sc2buf_dat_rd_data = l4group_data_rd_data[64-1:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////get sc data read data. no pipe +////: my $t1=""; +////: my $t2=""; +////: my $kk=CBUF_RD_PORT_WIDTH; +////: if((CBUF_BANK_RAM_CASE==0)||(CBUF_BANK_RAM_CASE==1)||(CBUF_BANK_RAM_CASE==4)){ +////: for(my $j=0; $j> {sc2buf_dat_rd_shift_5T,3'b0}; +//wire[64 -1:0] sc2buf_dat_rd_data = sc2buf_dat_rd_data_temp[64 -1:0]; +/////////////////////step3: read weight handle +//decode read weight address to sram. +//: my $bank_slice= "13:9"; #address part for select bank +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[${bank_slice}]==${j}); ) +//: } +//: if(2==2){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[${bank_slice}]==${j})&&(sc2buf_wt_rd_addr[0]==${k}); ) +//: } +//: if(2==3){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[${bank_slice}]==${j})&&(sc2buf_wt_rd_addr[0]==${k}/2); ) +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire bank0_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==0)&&(sc2buf_wt_rd_addr[0]==0); +wire bank0_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==0)&&(sc2buf_wt_rd_addr[0]==1); +wire bank1_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==1)&&(sc2buf_wt_rd_addr[0]==0); +wire bank1_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==1)&&(sc2buf_wt_rd_addr[0]==1); +wire bank2_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==2)&&(sc2buf_wt_rd_addr[0]==0); +wire bank2_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==2)&&(sc2buf_wt_rd_addr[0]==1); +wire bank3_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==3)&&(sc2buf_wt_rd_addr[0]==0); +wire bank3_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==3)&&(sc2buf_wt_rd_addr[0]==1); +wire bank4_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==4)&&(sc2buf_wt_rd_addr[0]==0); +wire bank4_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==4)&&(sc2buf_wt_rd_addr[0]==1); +wire bank5_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==5)&&(sc2buf_wt_rd_addr[0]==0); +wire bank5_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==5)&&(sc2buf_wt_rd_addr[0]==1); +wire bank6_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==6)&&(sc2buf_wt_rd_addr[0]==0); +wire bank6_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==6)&&(sc2buf_wt_rd_addr[0]==1); +wire bank7_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==7)&&(sc2buf_wt_rd_addr[0]==0); +wire bank7_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==7)&&(sc2buf_wt_rd_addr[0]==1); +wire bank8_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==8)&&(sc2buf_wt_rd_addr[0]==0); +wire bank8_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==8)&&(sc2buf_wt_rd_addr[0]==1); +wire bank9_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==9)&&(sc2buf_wt_rd_addr[0]==0); +wire bank9_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==9)&&(sc2buf_wt_rd_addr[0]==1); +wire bank10_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==10)&&(sc2buf_wt_rd_addr[0]==0); +wire bank10_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==10)&&(sc2buf_wt_rd_addr[0]==1); +wire bank11_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==11)&&(sc2buf_wt_rd_addr[0]==0); +wire bank11_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==11)&&(sc2buf_wt_rd_addr[0]==1); +wire bank12_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==12)&&(sc2buf_wt_rd_addr[0]==0); +wire bank12_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==12)&&(sc2buf_wt_rd_addr[0]==1); +wire bank13_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==13)&&(sc2buf_wt_rd_addr[0]==0); +wire bank13_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==13)&&(sc2buf_wt_rd_addr[0]==1); +wire bank14_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==14)&&(sc2buf_wt_rd_addr[0]==0); +wire bank14_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==14)&&(sc2buf_wt_rd_addr[0]==1); +wire bank15_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==15)&&(sc2buf_wt_rd_addr[0]==0); +wire bank15_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==15)&&(sc2buf_wt_rd_addr[0]==1); +wire bank16_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==16)&&(sc2buf_wt_rd_addr[0]==0); +wire bank16_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==16)&&(sc2buf_wt_rd_addr[0]==1); +wire bank17_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==17)&&(sc2buf_wt_rd_addr[0]==0); +wire bank17_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==17)&&(sc2buf_wt_rd_addr[0]==1); +wire bank18_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==18)&&(sc2buf_wt_rd_addr[0]==0); +wire bank18_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==18)&&(sc2buf_wt_rd_addr[0]==1); +wire bank19_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==19)&&(sc2buf_wt_rd_addr[0]==0); +wire bank19_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==19)&&(sc2buf_wt_rd_addr[0]==1); +wire bank20_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==20)&&(sc2buf_wt_rd_addr[0]==0); +wire bank20_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==20)&&(sc2buf_wt_rd_addr[0]==1); +wire bank21_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==21)&&(sc2buf_wt_rd_addr[0]==0); +wire bank21_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==21)&&(sc2buf_wt_rd_addr[0]==1); +wire bank22_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==22)&&(sc2buf_wt_rd_addr[0]==0); +wire bank22_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==22)&&(sc2buf_wt_rd_addr[0]==1); +wire bank23_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==23)&&(sc2buf_wt_rd_addr[0]==0); +wire bank23_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==23)&&(sc2buf_wt_rd_addr[0]==1); +wire bank24_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==24)&&(sc2buf_wt_rd_addr[0]==0); +wire bank24_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==24)&&(sc2buf_wt_rd_addr[0]==1); +wire bank25_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==25)&&(sc2buf_wt_rd_addr[0]==0); +wire bank25_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==25)&&(sc2buf_wt_rd_addr[0]==1); +wire bank26_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==26)&&(sc2buf_wt_rd_addr[0]==0); +wire bank26_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==26)&&(sc2buf_wt_rd_addr[0]==1); +wire bank27_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==27)&&(sc2buf_wt_rd_addr[0]==0); +wire bank27_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==27)&&(sc2buf_wt_rd_addr[0]==1); +wire bank28_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==28)&&(sc2buf_wt_rd_addr[0]==0); +wire bank28_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==28)&&(sc2buf_wt_rd_addr[0]==1); +wire bank29_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==29)&&(sc2buf_wt_rd_addr[0]==0); +wire bank29_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==29)&&(sc2buf_wt_rd_addr[0]==1); +wire bank30_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==30)&&(sc2buf_wt_rd_addr[0]==0); +wire bank30_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==30)&&(sc2buf_wt_rd_addr[0]==1); +wire bank31_ram0_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==31)&&(sc2buf_wt_rd_addr[0]==0); +wire bank31_ram1_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[13:9]==31)&&(sc2buf_wt_rd_addr[0]==1); +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sram weight read address. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_wt_rd_addr = {9 -1{bank${j}_ram${k}_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1 -1:0]); ) +//: } +//: if((2==2)||(2==3)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_wt_rd_addr = {9 -1{bank${j}_ram${k}_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); ) +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [9 -1 -1:0] bank0_ram0_wt_rd_addr = {9 -1{bank0_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank0_ram1_wt_rd_addr = {9 -1{bank0_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank1_ram0_wt_rd_addr = {9 -1{bank1_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank1_ram1_wt_rd_addr = {9 -1{bank1_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank2_ram0_wt_rd_addr = {9 -1{bank2_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank2_ram1_wt_rd_addr = {9 -1{bank2_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank3_ram0_wt_rd_addr = {9 -1{bank3_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank3_ram1_wt_rd_addr = {9 -1{bank3_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank4_ram0_wt_rd_addr = {9 -1{bank4_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank4_ram1_wt_rd_addr = {9 -1{bank4_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank5_ram0_wt_rd_addr = {9 -1{bank5_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank5_ram1_wt_rd_addr = {9 -1{bank5_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank6_ram0_wt_rd_addr = {9 -1{bank6_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank6_ram1_wt_rd_addr = {9 -1{bank6_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank7_ram0_wt_rd_addr = {9 -1{bank7_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank7_ram1_wt_rd_addr = {9 -1{bank7_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank8_ram0_wt_rd_addr = {9 -1{bank8_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank8_ram1_wt_rd_addr = {9 -1{bank8_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank9_ram0_wt_rd_addr = {9 -1{bank9_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank9_ram1_wt_rd_addr = {9 -1{bank9_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank10_ram0_wt_rd_addr = {9 -1{bank10_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank10_ram1_wt_rd_addr = {9 -1{bank10_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank11_ram0_wt_rd_addr = {9 -1{bank11_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank11_ram1_wt_rd_addr = {9 -1{bank11_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank12_ram0_wt_rd_addr = {9 -1{bank12_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank12_ram1_wt_rd_addr = {9 -1{bank12_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank13_ram0_wt_rd_addr = {9 -1{bank13_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank13_ram1_wt_rd_addr = {9 -1{bank13_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank14_ram0_wt_rd_addr = {9 -1{bank14_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank14_ram1_wt_rd_addr = {9 -1{bank14_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank15_ram0_wt_rd_addr = {9 -1{bank15_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank15_ram1_wt_rd_addr = {9 -1{bank15_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank16_ram0_wt_rd_addr = {9 -1{bank16_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank16_ram1_wt_rd_addr = {9 -1{bank16_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank17_ram0_wt_rd_addr = {9 -1{bank17_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank17_ram1_wt_rd_addr = {9 -1{bank17_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank18_ram0_wt_rd_addr = {9 -1{bank18_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank18_ram1_wt_rd_addr = {9 -1{bank18_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank19_ram0_wt_rd_addr = {9 -1{bank19_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank19_ram1_wt_rd_addr = {9 -1{bank19_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank20_ram0_wt_rd_addr = {9 -1{bank20_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank20_ram1_wt_rd_addr = {9 -1{bank20_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank21_ram0_wt_rd_addr = {9 -1{bank21_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank21_ram1_wt_rd_addr = {9 -1{bank21_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank22_ram0_wt_rd_addr = {9 -1{bank22_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank22_ram1_wt_rd_addr = {9 -1{bank22_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank23_ram0_wt_rd_addr = {9 -1{bank23_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank23_ram1_wt_rd_addr = {9 -1{bank23_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank24_ram0_wt_rd_addr = {9 -1{bank24_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank24_ram1_wt_rd_addr = {9 -1{bank24_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank25_ram0_wt_rd_addr = {9 -1{bank25_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank25_ram1_wt_rd_addr = {9 -1{bank25_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank26_ram0_wt_rd_addr = {9 -1{bank26_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank26_ram1_wt_rd_addr = {9 -1{bank26_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank27_ram0_wt_rd_addr = {9 -1{bank27_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank27_ram1_wt_rd_addr = {9 -1{bank27_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank28_ram0_wt_rd_addr = {9 -1{bank28_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank28_ram1_wt_rd_addr = {9 -1{bank28_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank29_ram0_wt_rd_addr = {9 -1{bank29_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank29_ram1_wt_rd_addr = {9 -1{bank29_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank30_ram0_wt_rd_addr = {9 -1{bank30_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank30_ram1_wt_rd_addr = {9 -1{bank30_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank31_ram0_wt_rd_addr = {9 -1{bank31_ram0_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +wire [9 -1 -1:0] bank31_ram1_wt_rd_addr = {9 -1{bank31_ram1_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); +//| eperl: generated_end (DO NOT EDIT ABOVE) +//add flop for sram weight read en +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: &eperl::flop("-q bank${j}_ram${k}_wt_rd_en_d1 -d bank${j}_ram${k}_wt_rd_en"); +//: &eperl::flop("-q bank${j}_ram${k}_wt_rd_en_d2 -d bank${j}_ram${k}_wt_rd_en_d1"); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg bank0_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank0_ram0_wt_rd_en_d1 <= bank0_ram0_wt_rd_en; + end +end +reg bank0_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank0_ram0_wt_rd_en_d2 <= bank0_ram0_wt_rd_en_d1; + end +end +reg bank0_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank0_ram1_wt_rd_en_d1 <= bank0_ram1_wt_rd_en; + end +end +reg bank0_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank0_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank0_ram1_wt_rd_en_d2 <= bank0_ram1_wt_rd_en_d1; + end +end +reg bank1_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank1_ram0_wt_rd_en_d1 <= bank1_ram0_wt_rd_en; + end +end +reg bank1_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank1_ram0_wt_rd_en_d2 <= bank1_ram0_wt_rd_en_d1; + end +end +reg bank1_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank1_ram1_wt_rd_en_d1 <= bank1_ram1_wt_rd_en; + end +end +reg bank1_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank1_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank1_ram1_wt_rd_en_d2 <= bank1_ram1_wt_rd_en_d1; + end +end +reg bank2_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank2_ram0_wt_rd_en_d1 <= bank2_ram0_wt_rd_en; + end +end +reg bank2_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank2_ram0_wt_rd_en_d2 <= bank2_ram0_wt_rd_en_d1; + end +end +reg bank2_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank2_ram1_wt_rd_en_d1 <= bank2_ram1_wt_rd_en; + end +end +reg bank2_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank2_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank2_ram1_wt_rd_en_d2 <= bank2_ram1_wt_rd_en_d1; + end +end +reg bank3_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank3_ram0_wt_rd_en_d1 <= bank3_ram0_wt_rd_en; + end +end +reg bank3_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank3_ram0_wt_rd_en_d2 <= bank3_ram0_wt_rd_en_d1; + end +end +reg bank3_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank3_ram1_wt_rd_en_d1 <= bank3_ram1_wt_rd_en; + end +end +reg bank3_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank3_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank3_ram1_wt_rd_en_d2 <= bank3_ram1_wt_rd_en_d1; + end +end +reg bank4_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank4_ram0_wt_rd_en_d1 <= bank4_ram0_wt_rd_en; + end +end +reg bank4_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank4_ram0_wt_rd_en_d2 <= bank4_ram0_wt_rd_en_d1; + end +end +reg bank4_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank4_ram1_wt_rd_en_d1 <= bank4_ram1_wt_rd_en; + end +end +reg bank4_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank4_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank4_ram1_wt_rd_en_d2 <= bank4_ram1_wt_rd_en_d1; + end +end +reg bank5_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank5_ram0_wt_rd_en_d1 <= bank5_ram0_wt_rd_en; + end +end +reg bank5_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank5_ram0_wt_rd_en_d2 <= bank5_ram0_wt_rd_en_d1; + end +end +reg bank5_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank5_ram1_wt_rd_en_d1 <= bank5_ram1_wt_rd_en; + end +end +reg bank5_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank5_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank5_ram1_wt_rd_en_d2 <= bank5_ram1_wt_rd_en_d1; + end +end +reg bank6_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank6_ram0_wt_rd_en_d1 <= bank6_ram0_wt_rd_en; + end +end +reg bank6_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank6_ram0_wt_rd_en_d2 <= bank6_ram0_wt_rd_en_d1; + end +end +reg bank6_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank6_ram1_wt_rd_en_d1 <= bank6_ram1_wt_rd_en; + end +end +reg bank6_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank6_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank6_ram1_wt_rd_en_d2 <= bank6_ram1_wt_rd_en_d1; + end +end +reg bank7_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank7_ram0_wt_rd_en_d1 <= bank7_ram0_wt_rd_en; + end +end +reg bank7_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank7_ram0_wt_rd_en_d2 <= bank7_ram0_wt_rd_en_d1; + end +end +reg bank7_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank7_ram1_wt_rd_en_d1 <= bank7_ram1_wt_rd_en; + end +end +reg bank7_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank7_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank7_ram1_wt_rd_en_d2 <= bank7_ram1_wt_rd_en_d1; + end +end +reg bank8_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank8_ram0_wt_rd_en_d1 <= bank8_ram0_wt_rd_en; + end +end +reg bank8_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank8_ram0_wt_rd_en_d2 <= bank8_ram0_wt_rd_en_d1; + end +end +reg bank8_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank8_ram1_wt_rd_en_d1 <= bank8_ram1_wt_rd_en; + end +end +reg bank8_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank8_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank8_ram1_wt_rd_en_d2 <= bank8_ram1_wt_rd_en_d1; + end +end +reg bank9_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank9_ram0_wt_rd_en_d1 <= bank9_ram0_wt_rd_en; + end +end +reg bank9_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank9_ram0_wt_rd_en_d2 <= bank9_ram0_wt_rd_en_d1; + end +end +reg bank9_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank9_ram1_wt_rd_en_d1 <= bank9_ram1_wt_rd_en; + end +end +reg bank9_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank9_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank9_ram1_wt_rd_en_d2 <= bank9_ram1_wt_rd_en_d1; + end +end +reg bank10_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank10_ram0_wt_rd_en_d1 <= bank10_ram0_wt_rd_en; + end +end +reg bank10_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank10_ram0_wt_rd_en_d2 <= bank10_ram0_wt_rd_en_d1; + end +end +reg bank10_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank10_ram1_wt_rd_en_d1 <= bank10_ram1_wt_rd_en; + end +end +reg bank10_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank10_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank10_ram1_wt_rd_en_d2 <= bank10_ram1_wt_rd_en_d1; + end +end +reg bank11_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank11_ram0_wt_rd_en_d1 <= bank11_ram0_wt_rd_en; + end +end +reg bank11_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank11_ram0_wt_rd_en_d2 <= bank11_ram0_wt_rd_en_d1; + end +end +reg bank11_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank11_ram1_wt_rd_en_d1 <= bank11_ram1_wt_rd_en; + end +end +reg bank11_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank11_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank11_ram1_wt_rd_en_d2 <= bank11_ram1_wt_rd_en_d1; + end +end +reg bank12_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank12_ram0_wt_rd_en_d1 <= bank12_ram0_wt_rd_en; + end +end +reg bank12_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank12_ram0_wt_rd_en_d2 <= bank12_ram0_wt_rd_en_d1; + end +end +reg bank12_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank12_ram1_wt_rd_en_d1 <= bank12_ram1_wt_rd_en; + end +end +reg bank12_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank12_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank12_ram1_wt_rd_en_d2 <= bank12_ram1_wt_rd_en_d1; + end +end +reg bank13_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank13_ram0_wt_rd_en_d1 <= bank13_ram0_wt_rd_en; + end +end +reg bank13_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank13_ram0_wt_rd_en_d2 <= bank13_ram0_wt_rd_en_d1; + end +end +reg bank13_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank13_ram1_wt_rd_en_d1 <= bank13_ram1_wt_rd_en; + end +end +reg bank13_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank13_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank13_ram1_wt_rd_en_d2 <= bank13_ram1_wt_rd_en_d1; + end +end +reg bank14_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank14_ram0_wt_rd_en_d1 <= bank14_ram0_wt_rd_en; + end +end +reg bank14_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank14_ram0_wt_rd_en_d2 <= bank14_ram0_wt_rd_en_d1; + end +end +reg bank14_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank14_ram1_wt_rd_en_d1 <= bank14_ram1_wt_rd_en; + end +end +reg bank14_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank14_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank14_ram1_wt_rd_en_d2 <= bank14_ram1_wt_rd_en_d1; + end +end +reg bank15_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank15_ram0_wt_rd_en_d1 <= bank15_ram0_wt_rd_en; + end +end +reg bank15_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank15_ram0_wt_rd_en_d2 <= bank15_ram0_wt_rd_en_d1; + end +end +reg bank15_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank15_ram1_wt_rd_en_d1 <= bank15_ram1_wt_rd_en; + end +end +reg bank15_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank15_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank15_ram1_wt_rd_en_d2 <= bank15_ram1_wt_rd_en_d1; + end +end +reg bank16_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank16_ram0_wt_rd_en_d1 <= bank16_ram0_wt_rd_en; + end +end +reg bank16_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank16_ram0_wt_rd_en_d2 <= bank16_ram0_wt_rd_en_d1; + end +end +reg bank16_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank16_ram1_wt_rd_en_d1 <= bank16_ram1_wt_rd_en; + end +end +reg bank16_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank16_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank16_ram1_wt_rd_en_d2 <= bank16_ram1_wt_rd_en_d1; + end +end +reg bank17_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank17_ram0_wt_rd_en_d1 <= bank17_ram0_wt_rd_en; + end +end +reg bank17_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank17_ram0_wt_rd_en_d2 <= bank17_ram0_wt_rd_en_d1; + end +end +reg bank17_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank17_ram1_wt_rd_en_d1 <= bank17_ram1_wt_rd_en; + end +end +reg bank17_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank17_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank17_ram1_wt_rd_en_d2 <= bank17_ram1_wt_rd_en_d1; + end +end +reg bank18_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank18_ram0_wt_rd_en_d1 <= bank18_ram0_wt_rd_en; + end +end +reg bank18_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank18_ram0_wt_rd_en_d2 <= bank18_ram0_wt_rd_en_d1; + end +end +reg bank18_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank18_ram1_wt_rd_en_d1 <= bank18_ram1_wt_rd_en; + end +end +reg bank18_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank18_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank18_ram1_wt_rd_en_d2 <= bank18_ram1_wt_rd_en_d1; + end +end +reg bank19_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank19_ram0_wt_rd_en_d1 <= bank19_ram0_wt_rd_en; + end +end +reg bank19_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank19_ram0_wt_rd_en_d2 <= bank19_ram0_wt_rd_en_d1; + end +end +reg bank19_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank19_ram1_wt_rd_en_d1 <= bank19_ram1_wt_rd_en; + end +end +reg bank19_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank19_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank19_ram1_wt_rd_en_d2 <= bank19_ram1_wt_rd_en_d1; + end +end +reg bank20_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank20_ram0_wt_rd_en_d1 <= bank20_ram0_wt_rd_en; + end +end +reg bank20_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank20_ram0_wt_rd_en_d2 <= bank20_ram0_wt_rd_en_d1; + end +end +reg bank20_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank20_ram1_wt_rd_en_d1 <= bank20_ram1_wt_rd_en; + end +end +reg bank20_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank20_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank20_ram1_wt_rd_en_d2 <= bank20_ram1_wt_rd_en_d1; + end +end +reg bank21_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank21_ram0_wt_rd_en_d1 <= bank21_ram0_wt_rd_en; + end +end +reg bank21_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank21_ram0_wt_rd_en_d2 <= bank21_ram0_wt_rd_en_d1; + end +end +reg bank21_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank21_ram1_wt_rd_en_d1 <= bank21_ram1_wt_rd_en; + end +end +reg bank21_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank21_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank21_ram1_wt_rd_en_d2 <= bank21_ram1_wt_rd_en_d1; + end +end +reg bank22_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank22_ram0_wt_rd_en_d1 <= bank22_ram0_wt_rd_en; + end +end +reg bank22_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank22_ram0_wt_rd_en_d2 <= bank22_ram0_wt_rd_en_d1; + end +end +reg bank22_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank22_ram1_wt_rd_en_d1 <= bank22_ram1_wt_rd_en; + end +end +reg bank22_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank22_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank22_ram1_wt_rd_en_d2 <= bank22_ram1_wt_rd_en_d1; + end +end +reg bank23_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank23_ram0_wt_rd_en_d1 <= bank23_ram0_wt_rd_en; + end +end +reg bank23_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank23_ram0_wt_rd_en_d2 <= bank23_ram0_wt_rd_en_d1; + end +end +reg bank23_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank23_ram1_wt_rd_en_d1 <= bank23_ram1_wt_rd_en; + end +end +reg bank23_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank23_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank23_ram1_wt_rd_en_d2 <= bank23_ram1_wt_rd_en_d1; + end +end +reg bank24_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank24_ram0_wt_rd_en_d1 <= bank24_ram0_wt_rd_en; + end +end +reg bank24_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank24_ram0_wt_rd_en_d2 <= bank24_ram0_wt_rd_en_d1; + end +end +reg bank24_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank24_ram1_wt_rd_en_d1 <= bank24_ram1_wt_rd_en; + end +end +reg bank24_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank24_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank24_ram1_wt_rd_en_d2 <= bank24_ram1_wt_rd_en_d1; + end +end +reg bank25_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank25_ram0_wt_rd_en_d1 <= bank25_ram0_wt_rd_en; + end +end +reg bank25_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank25_ram0_wt_rd_en_d2 <= bank25_ram0_wt_rd_en_d1; + end +end +reg bank25_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank25_ram1_wt_rd_en_d1 <= bank25_ram1_wt_rd_en; + end +end +reg bank25_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank25_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank25_ram1_wt_rd_en_d2 <= bank25_ram1_wt_rd_en_d1; + end +end +reg bank26_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank26_ram0_wt_rd_en_d1 <= bank26_ram0_wt_rd_en; + end +end +reg bank26_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank26_ram0_wt_rd_en_d2 <= bank26_ram0_wt_rd_en_d1; + end +end +reg bank26_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank26_ram1_wt_rd_en_d1 <= bank26_ram1_wt_rd_en; + end +end +reg bank26_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank26_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank26_ram1_wt_rd_en_d2 <= bank26_ram1_wt_rd_en_d1; + end +end +reg bank27_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank27_ram0_wt_rd_en_d1 <= bank27_ram0_wt_rd_en; + end +end +reg bank27_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank27_ram0_wt_rd_en_d2 <= bank27_ram0_wt_rd_en_d1; + end +end +reg bank27_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank27_ram1_wt_rd_en_d1 <= bank27_ram1_wt_rd_en; + end +end +reg bank27_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank27_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank27_ram1_wt_rd_en_d2 <= bank27_ram1_wt_rd_en_d1; + end +end +reg bank28_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank28_ram0_wt_rd_en_d1 <= bank28_ram0_wt_rd_en; + end +end +reg bank28_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank28_ram0_wt_rd_en_d2 <= bank28_ram0_wt_rd_en_d1; + end +end +reg bank28_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank28_ram1_wt_rd_en_d1 <= bank28_ram1_wt_rd_en; + end +end +reg bank28_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank28_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank28_ram1_wt_rd_en_d2 <= bank28_ram1_wt_rd_en_d1; + end +end +reg bank29_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank29_ram0_wt_rd_en_d1 <= bank29_ram0_wt_rd_en; + end +end +reg bank29_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank29_ram0_wt_rd_en_d2 <= bank29_ram0_wt_rd_en_d1; + end +end +reg bank29_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank29_ram1_wt_rd_en_d1 <= bank29_ram1_wt_rd_en; + end +end +reg bank29_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank29_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank29_ram1_wt_rd_en_d2 <= bank29_ram1_wt_rd_en_d1; + end +end +reg bank30_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank30_ram0_wt_rd_en_d1 <= bank30_ram0_wt_rd_en; + end +end +reg bank30_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank30_ram0_wt_rd_en_d2 <= bank30_ram0_wt_rd_en_d1; + end +end +reg bank30_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank30_ram1_wt_rd_en_d1 <= bank30_ram1_wt_rd_en; + end +end +reg bank30_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank30_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank30_ram1_wt_rd_en_d2 <= bank30_ram1_wt_rd_en_d1; + end +end +reg bank31_ram0_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_wt_rd_en_d1 <= 'b0; + end else begin + bank31_ram0_wt_rd_en_d1 <= bank31_ram0_wt_rd_en; + end +end +reg bank31_ram0_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram0_wt_rd_en_d2 <= 'b0; + end else begin + bank31_ram0_wt_rd_en_d2 <= bank31_ram0_wt_rd_en_d1; + end +end +reg bank31_ram1_wt_rd_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_wt_rd_en_d1 <= 'b0; + end else begin + bank31_ram1_wt_rd_en_d1 <= bank31_ram1_wt_rd_en; + end +end +reg bank31_ram1_wt_rd_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bank31_ram1_wt_rd_en_d2 <= 'b0; + end else begin + bank31_ram1_wt_rd_en_d2 <= bank31_ram1_wt_rd_en_d1; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sram weight read valid. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_valid = bank${j}_ram${k}_wt_rd_en_d2; ) +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire bank0_ram0_wt_rd_valid = bank0_ram0_wt_rd_en_d2; +wire bank0_ram1_wt_rd_valid = bank0_ram1_wt_rd_en_d2; +wire bank1_ram0_wt_rd_valid = bank1_ram0_wt_rd_en_d2; +wire bank1_ram1_wt_rd_valid = bank1_ram1_wt_rd_en_d2; +wire bank2_ram0_wt_rd_valid = bank2_ram0_wt_rd_en_d2; +wire bank2_ram1_wt_rd_valid = bank2_ram1_wt_rd_en_d2; +wire bank3_ram0_wt_rd_valid = bank3_ram0_wt_rd_en_d2; +wire bank3_ram1_wt_rd_valid = bank3_ram1_wt_rd_en_d2; +wire bank4_ram0_wt_rd_valid = bank4_ram0_wt_rd_en_d2; +wire bank4_ram1_wt_rd_valid = bank4_ram1_wt_rd_en_d2; +wire bank5_ram0_wt_rd_valid = bank5_ram0_wt_rd_en_d2; +wire bank5_ram1_wt_rd_valid = bank5_ram1_wt_rd_en_d2; +wire bank6_ram0_wt_rd_valid = bank6_ram0_wt_rd_en_d2; +wire bank6_ram1_wt_rd_valid = bank6_ram1_wt_rd_en_d2; +wire bank7_ram0_wt_rd_valid = bank7_ram0_wt_rd_en_d2; +wire bank7_ram1_wt_rd_valid = bank7_ram1_wt_rd_en_d2; +wire bank8_ram0_wt_rd_valid = bank8_ram0_wt_rd_en_d2; +wire bank8_ram1_wt_rd_valid = bank8_ram1_wt_rd_en_d2; +wire bank9_ram0_wt_rd_valid = bank9_ram0_wt_rd_en_d2; +wire bank9_ram1_wt_rd_valid = bank9_ram1_wt_rd_en_d2; +wire bank10_ram0_wt_rd_valid = bank10_ram0_wt_rd_en_d2; +wire bank10_ram1_wt_rd_valid = bank10_ram1_wt_rd_en_d2; +wire bank11_ram0_wt_rd_valid = bank11_ram0_wt_rd_en_d2; +wire bank11_ram1_wt_rd_valid = bank11_ram1_wt_rd_en_d2; +wire bank12_ram0_wt_rd_valid = bank12_ram0_wt_rd_en_d2; +wire bank12_ram1_wt_rd_valid = bank12_ram1_wt_rd_en_d2; +wire bank13_ram0_wt_rd_valid = bank13_ram0_wt_rd_en_d2; +wire bank13_ram1_wt_rd_valid = bank13_ram1_wt_rd_en_d2; +wire bank14_ram0_wt_rd_valid = bank14_ram0_wt_rd_en_d2; +wire bank14_ram1_wt_rd_valid = bank14_ram1_wt_rd_en_d2; +wire bank15_ram0_wt_rd_valid = bank15_ram0_wt_rd_en_d2; +wire bank15_ram1_wt_rd_valid = bank15_ram1_wt_rd_en_d2; +wire bank16_ram0_wt_rd_valid = bank16_ram0_wt_rd_en_d2; +wire bank16_ram1_wt_rd_valid = bank16_ram1_wt_rd_en_d2; +wire bank17_ram0_wt_rd_valid = bank17_ram0_wt_rd_en_d2; +wire bank17_ram1_wt_rd_valid = bank17_ram1_wt_rd_en_d2; +wire bank18_ram0_wt_rd_valid = bank18_ram0_wt_rd_en_d2; +wire bank18_ram1_wt_rd_valid = bank18_ram1_wt_rd_en_d2; +wire bank19_ram0_wt_rd_valid = bank19_ram0_wt_rd_en_d2; +wire bank19_ram1_wt_rd_valid = bank19_ram1_wt_rd_en_d2; +wire bank20_ram0_wt_rd_valid = bank20_ram0_wt_rd_en_d2; +wire bank20_ram1_wt_rd_valid = bank20_ram1_wt_rd_en_d2; +wire bank21_ram0_wt_rd_valid = bank21_ram0_wt_rd_en_d2; +wire bank21_ram1_wt_rd_valid = bank21_ram1_wt_rd_en_d2; +wire bank22_ram0_wt_rd_valid = bank22_ram0_wt_rd_en_d2; +wire bank22_ram1_wt_rd_valid = bank22_ram1_wt_rd_en_d2; +wire bank23_ram0_wt_rd_valid = bank23_ram0_wt_rd_en_d2; +wire bank23_ram1_wt_rd_valid = bank23_ram1_wt_rd_en_d2; +wire bank24_ram0_wt_rd_valid = bank24_ram0_wt_rd_en_d2; +wire bank24_ram1_wt_rd_valid = bank24_ram1_wt_rd_en_d2; +wire bank25_ram0_wt_rd_valid = bank25_ram0_wt_rd_en_d2; +wire bank25_ram1_wt_rd_valid = bank25_ram1_wt_rd_en_d2; +wire bank26_ram0_wt_rd_valid = bank26_ram0_wt_rd_en_d2; +wire bank26_ram1_wt_rd_valid = bank26_ram1_wt_rd_en_d2; +wire bank27_ram0_wt_rd_valid = bank27_ram0_wt_rd_en_d2; +wire bank27_ram1_wt_rd_valid = bank27_ram1_wt_rd_en_d2; +wire bank28_ram0_wt_rd_valid = bank28_ram0_wt_rd_en_d2; +wire bank28_ram1_wt_rd_valid = bank28_ram1_wt_rd_en_d2; +wire bank29_ram0_wt_rd_valid = bank29_ram0_wt_rd_en_d2; +wire bank29_ram1_wt_rd_valid = bank29_ram1_wt_rd_en_d2; +wire bank30_ram0_wt_rd_valid = bank30_ram0_wt_rd_en_d2; +wire bank30_ram1_wt_rd_valid = bank30_ram1_wt_rd_en_d2; +wire bank31_ram0_wt_rd_valid = bank31_ram0_wt_rd_en_d2; +wire bank31_ram1_wt_rd_valid = bank31_ram1_wt_rd_en_d2; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sc weight read valid. +//: my $t1=""; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: $t1 .= "bank${j}_ram${k}_wt_rd_valid|"; +//: } +//: } +//: print "wire [0:0] sc2buf_wt_rd_valid_w ="."${t1}"."1'b0 ;\n"; +//: &eperl::retime("-O sc2buf_wt_rd_valid -i sc2buf_wt_rd_valid_w -stage 4 -clk nvdla_core_clk"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [0:0] sc2buf_wt_rd_valid_w =bank0_ram0_wt_rd_valid|bank0_ram1_wt_rd_valid|bank1_ram0_wt_rd_valid|bank1_ram1_wt_rd_valid|bank2_ram0_wt_rd_valid|bank2_ram1_wt_rd_valid|bank3_ram0_wt_rd_valid|bank3_ram1_wt_rd_valid|bank4_ram0_wt_rd_valid|bank4_ram1_wt_rd_valid|bank5_ram0_wt_rd_valid|bank5_ram1_wt_rd_valid|bank6_ram0_wt_rd_valid|bank6_ram1_wt_rd_valid|bank7_ram0_wt_rd_valid|bank7_ram1_wt_rd_valid|bank8_ram0_wt_rd_valid|bank8_ram1_wt_rd_valid|bank9_ram0_wt_rd_valid|bank9_ram1_wt_rd_valid|bank10_ram0_wt_rd_valid|bank10_ram1_wt_rd_valid|bank11_ram0_wt_rd_valid|bank11_ram1_wt_rd_valid|bank12_ram0_wt_rd_valid|bank12_ram1_wt_rd_valid|bank13_ram0_wt_rd_valid|bank13_ram1_wt_rd_valid|bank14_ram0_wt_rd_valid|bank14_ram1_wt_rd_valid|bank15_ram0_wt_rd_valid|bank15_ram1_wt_rd_valid|bank16_ram0_wt_rd_valid|bank16_ram1_wt_rd_valid|bank17_ram0_wt_rd_valid|bank17_ram1_wt_rd_valid|bank18_ram0_wt_rd_valid|bank18_ram1_wt_rd_valid|bank19_ram0_wt_rd_valid|bank19_ram1_wt_rd_valid|bank20_ram0_wt_rd_valid|bank20_ram1_wt_rd_valid|bank21_ram0_wt_rd_valid|bank21_ram1_wt_rd_valid|bank22_ram0_wt_rd_valid|bank22_ram1_wt_rd_valid|bank23_ram0_wt_rd_valid|bank23_ram1_wt_rd_valid|bank24_ram0_wt_rd_valid|bank24_ram1_wt_rd_valid|bank25_ram0_wt_rd_valid|bank25_ram1_wt_rd_valid|bank26_ram0_wt_rd_valid|bank26_ram1_wt_rd_valid|bank27_ram0_wt_rd_valid|bank27_ram1_wt_rd_valid|bank28_ram0_wt_rd_valid|bank28_ram1_wt_rd_valid|bank29_ram0_wt_rd_valid|bank29_ram1_wt_rd_valid|bank30_ram0_wt_rd_valid|bank30_ram1_wt_rd_valid|bank31_ram0_wt_rd_valid|bank31_ram1_wt_rd_valid|1'b0 ; +reg sc2buf_wt_rd_valid_w_d1; +always @(posedge nvdla_core_clk) begin + sc2buf_wt_rd_valid_w_d1 <= sc2buf_wt_rd_valid_w; +end + +reg sc2buf_wt_rd_valid_w_d2; +always @(posedge nvdla_core_clk) begin + sc2buf_wt_rd_valid_w_d2 <= sc2buf_wt_rd_valid_w_d1; +end + +reg sc2buf_wt_rd_valid_w_d3; +always @(posedge nvdla_core_clk) begin + sc2buf_wt_rd_valid_w_d3 <= sc2buf_wt_rd_valid_w_d2; +end + +reg sc2buf_wt_rd_valid_w_d4; +always @(posedge nvdla_core_clk) begin + sc2buf_wt_rd_valid_w_d4 <= sc2buf_wt_rd_valid_w_d3; +end + +wire sc2buf_wt_rd_valid; +assign sc2buf_wt_rd_valid = sc2buf_wt_rd_valid_w_d4; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//get sc weight read bank output data. +//: my $t1=""; +//: my $kk=64; +//: if(2==0){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}; ); +//: } +//: } +//: if(2==1){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}}; ); +//: } +//: } +//: if(2==2){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = (bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}})| +//: (bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}); +//: ); +//: } +//: } +//: if(2==3){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}}| +//: {bank${j}_ram3_rd_data&{64{bank${j}_ram3_wt_rd_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_wt_rd_valid}}}; +//: ); +//: } +//: } +//: if(2==4){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = {bank${j}_ram3_rd_data&{64{bank${j}_ram3_wt_rd_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_wt_rd_valid}}, +//: bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}}; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [64-1:0] bank0_wt_rd_data = (bank0_ram1_rd_data&{64{bank0_ram1_wt_rd_valid}})| +(bank0_ram0_rd_data&{64{bank0_ram0_wt_rd_valid}}); + +wire [64-1:0] bank1_wt_rd_data = (bank1_ram1_rd_data&{64{bank1_ram1_wt_rd_valid}})| +(bank1_ram0_rd_data&{64{bank1_ram0_wt_rd_valid}}); + +wire [64-1:0] bank2_wt_rd_data = (bank2_ram1_rd_data&{64{bank2_ram1_wt_rd_valid}})| +(bank2_ram0_rd_data&{64{bank2_ram0_wt_rd_valid}}); + +wire [64-1:0] bank3_wt_rd_data = (bank3_ram1_rd_data&{64{bank3_ram1_wt_rd_valid}})| +(bank3_ram0_rd_data&{64{bank3_ram0_wt_rd_valid}}); + +wire [64-1:0] bank4_wt_rd_data = (bank4_ram1_rd_data&{64{bank4_ram1_wt_rd_valid}})| +(bank4_ram0_rd_data&{64{bank4_ram0_wt_rd_valid}}); + +wire [64-1:0] bank5_wt_rd_data = (bank5_ram1_rd_data&{64{bank5_ram1_wt_rd_valid}})| +(bank5_ram0_rd_data&{64{bank5_ram0_wt_rd_valid}}); + +wire [64-1:0] bank6_wt_rd_data = (bank6_ram1_rd_data&{64{bank6_ram1_wt_rd_valid}})| +(bank6_ram0_rd_data&{64{bank6_ram0_wt_rd_valid}}); + +wire [64-1:0] bank7_wt_rd_data = (bank7_ram1_rd_data&{64{bank7_ram1_wt_rd_valid}})| +(bank7_ram0_rd_data&{64{bank7_ram0_wt_rd_valid}}); + +wire [64-1:0] bank8_wt_rd_data = (bank8_ram1_rd_data&{64{bank8_ram1_wt_rd_valid}})| +(bank8_ram0_rd_data&{64{bank8_ram0_wt_rd_valid}}); + +wire [64-1:0] bank9_wt_rd_data = (bank9_ram1_rd_data&{64{bank9_ram1_wt_rd_valid}})| +(bank9_ram0_rd_data&{64{bank9_ram0_wt_rd_valid}}); + +wire [64-1:0] bank10_wt_rd_data = (bank10_ram1_rd_data&{64{bank10_ram1_wt_rd_valid}})| +(bank10_ram0_rd_data&{64{bank10_ram0_wt_rd_valid}}); + +wire [64-1:0] bank11_wt_rd_data = (bank11_ram1_rd_data&{64{bank11_ram1_wt_rd_valid}})| +(bank11_ram0_rd_data&{64{bank11_ram0_wt_rd_valid}}); + +wire [64-1:0] bank12_wt_rd_data = (bank12_ram1_rd_data&{64{bank12_ram1_wt_rd_valid}})| +(bank12_ram0_rd_data&{64{bank12_ram0_wt_rd_valid}}); + +wire [64-1:0] bank13_wt_rd_data = (bank13_ram1_rd_data&{64{bank13_ram1_wt_rd_valid}})| +(bank13_ram0_rd_data&{64{bank13_ram0_wt_rd_valid}}); + +wire [64-1:0] bank14_wt_rd_data = (bank14_ram1_rd_data&{64{bank14_ram1_wt_rd_valid}})| +(bank14_ram0_rd_data&{64{bank14_ram0_wt_rd_valid}}); + +wire [64-1:0] bank15_wt_rd_data = (bank15_ram1_rd_data&{64{bank15_ram1_wt_rd_valid}})| +(bank15_ram0_rd_data&{64{bank15_ram0_wt_rd_valid}}); + +wire [64-1:0] bank16_wt_rd_data = (bank16_ram1_rd_data&{64{bank16_ram1_wt_rd_valid}})| +(bank16_ram0_rd_data&{64{bank16_ram0_wt_rd_valid}}); + +wire [64-1:0] bank17_wt_rd_data = (bank17_ram1_rd_data&{64{bank17_ram1_wt_rd_valid}})| +(bank17_ram0_rd_data&{64{bank17_ram0_wt_rd_valid}}); + +wire [64-1:0] bank18_wt_rd_data = (bank18_ram1_rd_data&{64{bank18_ram1_wt_rd_valid}})| +(bank18_ram0_rd_data&{64{bank18_ram0_wt_rd_valid}}); + +wire [64-1:0] bank19_wt_rd_data = (bank19_ram1_rd_data&{64{bank19_ram1_wt_rd_valid}})| +(bank19_ram0_rd_data&{64{bank19_ram0_wt_rd_valid}}); + +wire [64-1:0] bank20_wt_rd_data = (bank20_ram1_rd_data&{64{bank20_ram1_wt_rd_valid}})| +(bank20_ram0_rd_data&{64{bank20_ram0_wt_rd_valid}}); + +wire [64-1:0] bank21_wt_rd_data = (bank21_ram1_rd_data&{64{bank21_ram1_wt_rd_valid}})| +(bank21_ram0_rd_data&{64{bank21_ram0_wt_rd_valid}}); + +wire [64-1:0] bank22_wt_rd_data = (bank22_ram1_rd_data&{64{bank22_ram1_wt_rd_valid}})| +(bank22_ram0_rd_data&{64{bank22_ram0_wt_rd_valid}}); + +wire [64-1:0] bank23_wt_rd_data = (bank23_ram1_rd_data&{64{bank23_ram1_wt_rd_valid}})| +(bank23_ram0_rd_data&{64{bank23_ram0_wt_rd_valid}}); + +wire [64-1:0] bank24_wt_rd_data = (bank24_ram1_rd_data&{64{bank24_ram1_wt_rd_valid}})| +(bank24_ram0_rd_data&{64{bank24_ram0_wt_rd_valid}}); + +wire [64-1:0] bank25_wt_rd_data = (bank25_ram1_rd_data&{64{bank25_ram1_wt_rd_valid}})| +(bank25_ram0_rd_data&{64{bank25_ram0_wt_rd_valid}}); + +wire [64-1:0] bank26_wt_rd_data = (bank26_ram1_rd_data&{64{bank26_ram1_wt_rd_valid}})| +(bank26_ram0_rd_data&{64{bank26_ram0_wt_rd_valid}}); + +wire [64-1:0] bank27_wt_rd_data = (bank27_ram1_rd_data&{64{bank27_ram1_wt_rd_valid}})| +(bank27_ram0_rd_data&{64{bank27_ram0_wt_rd_valid}}); + +wire [64-1:0] bank28_wt_rd_data = (bank28_ram1_rd_data&{64{bank28_ram1_wt_rd_valid}})| +(bank28_ram0_rd_data&{64{bank28_ram0_wt_rd_valid}}); + +wire [64-1:0] bank29_wt_rd_data = (bank29_ram1_rd_data&{64{bank29_ram1_wt_rd_valid}})| +(bank29_ram0_rd_data&{64{bank29_ram0_wt_rd_valid}}); + +wire [64-1:0] bank30_wt_rd_data = (bank30_ram1_rd_data&{64{bank30_ram1_wt_rd_valid}})| +(bank30_ram0_rd_data&{64{bank30_ram0_wt_rd_valid}}); + +wire [64-1:0] bank31_wt_rd_data = (bank31_ram1_rd_data&{64{bank31_ram1_wt_rd_valid}})| +(bank31_ram0_rd_data&{64{bank31_ram0_wt_rd_valid}}); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// pipe solution. for timing concern, 4 level pipe. +//: my $kk=64; +//: for (my $i=0; $i<32; $i++){ +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_wt_rd_data -d bank${i}_wt_rd_data"); +//: } +//: +//: for (my $i=0; $i<32/4; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l2group${i}_wt_rd_data_w = l1group${ni}_wt_rd_data | l1group${nii}_wt_rd_data | l1group${niii}_wt_rd_data | l1group${niiii}_wt_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_wt_rd_data -d l2group${i}_wt_rd_data_w"); +//: } +//: +//: for (my $i=0; $i<32/16; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l3group${i}_wt_rd_data_w = l2group${ni}_wt_rd_data | l2group${nii}_wt_rd_data | l2group${niii}_wt_rd_data | l2group${niiii}_wt_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_wt_rd_data -d l3group${i}_wt_rd_data_w"); +//: } +//: +//: if(32==16){ +//: &eperl::flop("-wid ${kk} -norst -q l4group_wt_rd_data -d l3group0_wt_rd_data"); +//: } +//: if(32==32) { +//: print qq( +//: wire [${kk}-1:0] l4group_wt_rd_data_w = l3group0_wt_rd_data | l3group1_wt_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l4group_wt_rd_data -d l4group_wt_rd_data_w"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [63:0] l1group0_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group0_wt_rd_data <= bank0_wt_rd_data; +end +reg [63:0] l1group1_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group1_wt_rd_data <= bank1_wt_rd_data; +end +reg [63:0] l1group2_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group2_wt_rd_data <= bank2_wt_rd_data; +end +reg [63:0] l1group3_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group3_wt_rd_data <= bank3_wt_rd_data; +end +reg [63:0] l1group4_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group4_wt_rd_data <= bank4_wt_rd_data; +end +reg [63:0] l1group5_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group5_wt_rd_data <= bank5_wt_rd_data; +end +reg [63:0] l1group6_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group6_wt_rd_data <= bank6_wt_rd_data; +end +reg [63:0] l1group7_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group7_wt_rd_data <= bank7_wt_rd_data; +end +reg [63:0] l1group8_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group8_wt_rd_data <= bank8_wt_rd_data; +end +reg [63:0] l1group9_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group9_wt_rd_data <= bank9_wt_rd_data; +end +reg [63:0] l1group10_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group10_wt_rd_data <= bank10_wt_rd_data; +end +reg [63:0] l1group11_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group11_wt_rd_data <= bank11_wt_rd_data; +end +reg [63:0] l1group12_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group12_wt_rd_data <= bank12_wt_rd_data; +end +reg [63:0] l1group13_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group13_wt_rd_data <= bank13_wt_rd_data; +end +reg [63:0] l1group14_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group14_wt_rd_data <= bank14_wt_rd_data; +end +reg [63:0] l1group15_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group15_wt_rd_data <= bank15_wt_rd_data; +end +reg [63:0] l1group16_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group16_wt_rd_data <= bank16_wt_rd_data; +end +reg [63:0] l1group17_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group17_wt_rd_data <= bank17_wt_rd_data; +end +reg [63:0] l1group18_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group18_wt_rd_data <= bank18_wt_rd_data; +end +reg [63:0] l1group19_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group19_wt_rd_data <= bank19_wt_rd_data; +end +reg [63:0] l1group20_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group20_wt_rd_data <= bank20_wt_rd_data; +end +reg [63:0] l1group21_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group21_wt_rd_data <= bank21_wt_rd_data; +end +reg [63:0] l1group22_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group22_wt_rd_data <= bank22_wt_rd_data; +end +reg [63:0] l1group23_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group23_wt_rd_data <= bank23_wt_rd_data; +end +reg [63:0] l1group24_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group24_wt_rd_data <= bank24_wt_rd_data; +end +reg [63:0] l1group25_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group25_wt_rd_data <= bank25_wt_rd_data; +end +reg [63:0] l1group26_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group26_wt_rd_data <= bank26_wt_rd_data; +end +reg [63:0] l1group27_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group27_wt_rd_data <= bank27_wt_rd_data; +end +reg [63:0] l1group28_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group28_wt_rd_data <= bank28_wt_rd_data; +end +reg [63:0] l1group29_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group29_wt_rd_data <= bank29_wt_rd_data; +end +reg [63:0] l1group30_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group30_wt_rd_data <= bank30_wt_rd_data; +end +reg [63:0] l1group31_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l1group31_wt_rd_data <= bank31_wt_rd_data; +end + +wire [64-1:0] l2group0_wt_rd_data_w = l1group0_wt_rd_data | l1group1_wt_rd_data | l1group2_wt_rd_data | l1group3_wt_rd_data; +reg [63:0] l2group0_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group0_wt_rd_data <= l2group0_wt_rd_data_w; +end + +wire [64-1:0] l2group1_wt_rd_data_w = l1group4_wt_rd_data | l1group5_wt_rd_data | l1group6_wt_rd_data | l1group7_wt_rd_data; +reg [63:0] l2group1_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group1_wt_rd_data <= l2group1_wt_rd_data_w; +end + +wire [64-1:0] l2group2_wt_rd_data_w = l1group8_wt_rd_data | l1group9_wt_rd_data | l1group10_wt_rd_data | l1group11_wt_rd_data; +reg [63:0] l2group2_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group2_wt_rd_data <= l2group2_wt_rd_data_w; +end + +wire [64-1:0] l2group3_wt_rd_data_w = l1group12_wt_rd_data | l1group13_wt_rd_data | l1group14_wt_rd_data | l1group15_wt_rd_data; +reg [63:0] l2group3_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group3_wt_rd_data <= l2group3_wt_rd_data_w; +end + +wire [64-1:0] l2group4_wt_rd_data_w = l1group16_wt_rd_data | l1group17_wt_rd_data | l1group18_wt_rd_data | l1group19_wt_rd_data; +reg [63:0] l2group4_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group4_wt_rd_data <= l2group4_wt_rd_data_w; +end + +wire [64-1:0] l2group5_wt_rd_data_w = l1group20_wt_rd_data | l1group21_wt_rd_data | l1group22_wt_rd_data | l1group23_wt_rd_data; +reg [63:0] l2group5_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group5_wt_rd_data <= l2group5_wt_rd_data_w; +end + +wire [64-1:0] l2group6_wt_rd_data_w = l1group24_wt_rd_data | l1group25_wt_rd_data | l1group26_wt_rd_data | l1group27_wt_rd_data; +reg [63:0] l2group6_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group6_wt_rd_data <= l2group6_wt_rd_data_w; +end + +wire [64-1:0] l2group7_wt_rd_data_w = l1group28_wt_rd_data | l1group29_wt_rd_data | l1group30_wt_rd_data | l1group31_wt_rd_data; +reg [63:0] l2group7_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l2group7_wt_rd_data <= l2group7_wt_rd_data_w; +end + +wire [64-1:0] l3group0_wt_rd_data_w = l2group0_wt_rd_data | l2group1_wt_rd_data | l2group2_wt_rd_data | l2group3_wt_rd_data; +reg [63:0] l3group0_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l3group0_wt_rd_data <= l3group0_wt_rd_data_w; +end + +wire [64-1:0] l3group1_wt_rd_data_w = l2group4_wt_rd_data | l2group5_wt_rd_data | l2group6_wt_rd_data | l2group7_wt_rd_data; +reg [63:0] l3group1_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l3group1_wt_rd_data <= l3group1_wt_rd_data_w; +end + +wire [64-1:0] l4group_wt_rd_data_w = l3group0_wt_rd_data | l3group1_wt_rd_data; +reg [63:0] l4group_wt_rd_data; +always @(posedge nvdla_core_clk) begin + l4group_wt_rd_data <= l4group_wt_rd_data_w; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire[64 -1:0] sc2buf_wt_rd_data = l4group_wt_rd_data[64 -1:0]; +////get sc weight read data. +////: my $t1=""; +////: my $kk=CBUF_RD_PORT_WIDTH; +////: for(my $j=0; $j w +//: ,.wa (bank${i}_ram${j}_wr_addr_d2[9 -1 -1:0]) //|< r +//: ,.we (bank${i}_ram${j}_wr_en_d2) //|< r +//: ,.di (bank${i}_ram${j}_wr_data_d2) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +//: ); +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +nv_ram_rws_256x64 u_cbuf_ram_bank0_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank0_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank0_ram0_rd_en_d1) //|< r +,.dout (bank0_ram0_rd_data) //|> w +,.wa (bank0_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank0_ram0_wr_en_d2) //|< r +,.di (bank0_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank0_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank0_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank0_ram1_rd_en_d1) //|< r +,.dout (bank0_ram1_rd_data) //|> w +,.wa (bank0_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank0_ram1_wr_en_d2) //|< r +,.di (bank0_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank1_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank1_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank1_ram0_rd_en_d1) //|< r +,.dout (bank1_ram0_rd_data) //|> w +,.wa (bank1_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank1_ram0_wr_en_d2) //|< r +,.di (bank1_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank1_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank1_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank1_ram1_rd_en_d1) //|< r +,.dout (bank1_ram1_rd_data) //|> w +,.wa (bank1_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank1_ram1_wr_en_d2) //|< r +,.di (bank1_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank2_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank2_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank2_ram0_rd_en_d1) //|< r +,.dout (bank2_ram0_rd_data) //|> w +,.wa (bank2_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank2_ram0_wr_en_d2) //|< r +,.di (bank2_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank2_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank2_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank2_ram1_rd_en_d1) //|< r +,.dout (bank2_ram1_rd_data) //|> w +,.wa (bank2_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank2_ram1_wr_en_d2) //|< r +,.di (bank2_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank3_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank3_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank3_ram0_rd_en_d1) //|< r +,.dout (bank3_ram0_rd_data) //|> w +,.wa (bank3_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank3_ram0_wr_en_d2) //|< r +,.di (bank3_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank3_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank3_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank3_ram1_rd_en_d1) //|< r +,.dout (bank3_ram1_rd_data) //|> w +,.wa (bank3_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank3_ram1_wr_en_d2) //|< r +,.di (bank3_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank4_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank4_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank4_ram0_rd_en_d1) //|< r +,.dout (bank4_ram0_rd_data) //|> w +,.wa (bank4_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank4_ram0_wr_en_d2) //|< r +,.di (bank4_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank4_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank4_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank4_ram1_rd_en_d1) //|< r +,.dout (bank4_ram1_rd_data) //|> w +,.wa (bank4_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank4_ram1_wr_en_d2) //|< r +,.di (bank4_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank5_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank5_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank5_ram0_rd_en_d1) //|< r +,.dout (bank5_ram0_rd_data) //|> w +,.wa (bank5_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank5_ram0_wr_en_d2) //|< r +,.di (bank5_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank5_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank5_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank5_ram1_rd_en_d1) //|< r +,.dout (bank5_ram1_rd_data) //|> w +,.wa (bank5_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank5_ram1_wr_en_d2) //|< r +,.di (bank5_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank6_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank6_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank6_ram0_rd_en_d1) //|< r +,.dout (bank6_ram0_rd_data) //|> w +,.wa (bank6_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank6_ram0_wr_en_d2) //|< r +,.di (bank6_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank6_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank6_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank6_ram1_rd_en_d1) //|< r +,.dout (bank6_ram1_rd_data) //|> w +,.wa (bank6_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank6_ram1_wr_en_d2) //|< r +,.di (bank6_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank7_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank7_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank7_ram0_rd_en_d1) //|< r +,.dout (bank7_ram0_rd_data) //|> w +,.wa (bank7_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank7_ram0_wr_en_d2) //|< r +,.di (bank7_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank7_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank7_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank7_ram1_rd_en_d1) //|< r +,.dout (bank7_ram1_rd_data) //|> w +,.wa (bank7_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank7_ram1_wr_en_d2) //|< r +,.di (bank7_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank8_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank8_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank8_ram0_rd_en_d1) //|< r +,.dout (bank8_ram0_rd_data) //|> w +,.wa (bank8_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank8_ram0_wr_en_d2) //|< r +,.di (bank8_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank8_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank8_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank8_ram1_rd_en_d1) //|< r +,.dout (bank8_ram1_rd_data) //|> w +,.wa (bank8_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank8_ram1_wr_en_d2) //|< r +,.di (bank8_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank9_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank9_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank9_ram0_rd_en_d1) //|< r +,.dout (bank9_ram0_rd_data) //|> w +,.wa (bank9_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank9_ram0_wr_en_d2) //|< r +,.di (bank9_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank9_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank9_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank9_ram1_rd_en_d1) //|< r +,.dout (bank9_ram1_rd_data) //|> w +,.wa (bank9_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank9_ram1_wr_en_d2) //|< r +,.di (bank9_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank10_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank10_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank10_ram0_rd_en_d1) //|< r +,.dout (bank10_ram0_rd_data) //|> w +,.wa (bank10_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank10_ram0_wr_en_d2) //|< r +,.di (bank10_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank10_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank10_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank10_ram1_rd_en_d1) //|< r +,.dout (bank10_ram1_rd_data) //|> w +,.wa (bank10_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank10_ram1_wr_en_d2) //|< r +,.di (bank10_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank11_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank11_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank11_ram0_rd_en_d1) //|< r +,.dout (bank11_ram0_rd_data) //|> w +,.wa (bank11_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank11_ram0_wr_en_d2) //|< r +,.di (bank11_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank11_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank11_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank11_ram1_rd_en_d1) //|< r +,.dout (bank11_ram1_rd_data) //|> w +,.wa (bank11_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank11_ram1_wr_en_d2) //|< r +,.di (bank11_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank12_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank12_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank12_ram0_rd_en_d1) //|< r +,.dout (bank12_ram0_rd_data) //|> w +,.wa (bank12_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank12_ram0_wr_en_d2) //|< r +,.di (bank12_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank12_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank12_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank12_ram1_rd_en_d1) //|< r +,.dout (bank12_ram1_rd_data) //|> w +,.wa (bank12_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank12_ram1_wr_en_d2) //|< r +,.di (bank12_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank13_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank13_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank13_ram0_rd_en_d1) //|< r +,.dout (bank13_ram0_rd_data) //|> w +,.wa (bank13_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank13_ram0_wr_en_d2) //|< r +,.di (bank13_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank13_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank13_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank13_ram1_rd_en_d1) //|< r +,.dout (bank13_ram1_rd_data) //|> w +,.wa (bank13_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank13_ram1_wr_en_d2) //|< r +,.di (bank13_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank14_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank14_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank14_ram0_rd_en_d1) //|< r +,.dout (bank14_ram0_rd_data) //|> w +,.wa (bank14_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank14_ram0_wr_en_d2) //|< r +,.di (bank14_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank14_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank14_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank14_ram1_rd_en_d1) //|< r +,.dout (bank14_ram1_rd_data) //|> w +,.wa (bank14_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank14_ram1_wr_en_d2) //|< r +,.di (bank14_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank15_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank15_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank15_ram0_rd_en_d1) //|< r +,.dout (bank15_ram0_rd_data) //|> w +,.wa (bank15_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank15_ram0_wr_en_d2) //|< r +,.di (bank15_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank15_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank15_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank15_ram1_rd_en_d1) //|< r +,.dout (bank15_ram1_rd_data) //|> w +,.wa (bank15_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank15_ram1_wr_en_d2) //|< r +,.di (bank15_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank16_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank16_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank16_ram0_rd_en_d1) //|< r +,.dout (bank16_ram0_rd_data) //|> w +,.wa (bank16_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank16_ram0_wr_en_d2) //|< r +,.di (bank16_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank16_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank16_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank16_ram1_rd_en_d1) //|< r +,.dout (bank16_ram1_rd_data) //|> w +,.wa (bank16_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank16_ram1_wr_en_d2) //|< r +,.di (bank16_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank17_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank17_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank17_ram0_rd_en_d1) //|< r +,.dout (bank17_ram0_rd_data) //|> w +,.wa (bank17_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank17_ram0_wr_en_d2) //|< r +,.di (bank17_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank17_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank17_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank17_ram1_rd_en_d1) //|< r +,.dout (bank17_ram1_rd_data) //|> w +,.wa (bank17_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank17_ram1_wr_en_d2) //|< r +,.di (bank17_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank18_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank18_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank18_ram0_rd_en_d1) //|< r +,.dout (bank18_ram0_rd_data) //|> w +,.wa (bank18_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank18_ram0_wr_en_d2) //|< r +,.di (bank18_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank18_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank18_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank18_ram1_rd_en_d1) //|< r +,.dout (bank18_ram1_rd_data) //|> w +,.wa (bank18_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank18_ram1_wr_en_d2) //|< r +,.di (bank18_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank19_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank19_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank19_ram0_rd_en_d1) //|< r +,.dout (bank19_ram0_rd_data) //|> w +,.wa (bank19_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank19_ram0_wr_en_d2) //|< r +,.di (bank19_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank19_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank19_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank19_ram1_rd_en_d1) //|< r +,.dout (bank19_ram1_rd_data) //|> w +,.wa (bank19_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank19_ram1_wr_en_d2) //|< r +,.di (bank19_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank20_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank20_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank20_ram0_rd_en_d1) //|< r +,.dout (bank20_ram0_rd_data) //|> w +,.wa (bank20_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank20_ram0_wr_en_d2) //|< r +,.di (bank20_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank20_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank20_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank20_ram1_rd_en_d1) //|< r +,.dout (bank20_ram1_rd_data) //|> w +,.wa (bank20_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank20_ram1_wr_en_d2) //|< r +,.di (bank20_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank21_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank21_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank21_ram0_rd_en_d1) //|< r +,.dout (bank21_ram0_rd_data) //|> w +,.wa (bank21_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank21_ram0_wr_en_d2) //|< r +,.di (bank21_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank21_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank21_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank21_ram1_rd_en_d1) //|< r +,.dout (bank21_ram1_rd_data) //|> w +,.wa (bank21_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank21_ram1_wr_en_d2) //|< r +,.di (bank21_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank22_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank22_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank22_ram0_rd_en_d1) //|< r +,.dout (bank22_ram0_rd_data) //|> w +,.wa (bank22_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank22_ram0_wr_en_d2) //|< r +,.di (bank22_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank22_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank22_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank22_ram1_rd_en_d1) //|< r +,.dout (bank22_ram1_rd_data) //|> w +,.wa (bank22_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank22_ram1_wr_en_d2) //|< r +,.di (bank22_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank23_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank23_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank23_ram0_rd_en_d1) //|< r +,.dout (bank23_ram0_rd_data) //|> w +,.wa (bank23_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank23_ram0_wr_en_d2) //|< r +,.di (bank23_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank23_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank23_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank23_ram1_rd_en_d1) //|< r +,.dout (bank23_ram1_rd_data) //|> w +,.wa (bank23_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank23_ram1_wr_en_d2) //|< r +,.di (bank23_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank24_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank24_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank24_ram0_rd_en_d1) //|< r +,.dout (bank24_ram0_rd_data) //|> w +,.wa (bank24_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank24_ram0_wr_en_d2) //|< r +,.di (bank24_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank24_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank24_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank24_ram1_rd_en_d1) //|< r +,.dout (bank24_ram1_rd_data) //|> w +,.wa (bank24_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank24_ram1_wr_en_d2) //|< r +,.di (bank24_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank25_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank25_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank25_ram0_rd_en_d1) //|< r +,.dout (bank25_ram0_rd_data) //|> w +,.wa (bank25_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank25_ram0_wr_en_d2) //|< r +,.di (bank25_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank25_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank25_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank25_ram1_rd_en_d1) //|< r +,.dout (bank25_ram1_rd_data) //|> w +,.wa (bank25_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank25_ram1_wr_en_d2) //|< r +,.di (bank25_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank26_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank26_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank26_ram0_rd_en_d1) //|< r +,.dout (bank26_ram0_rd_data) //|> w +,.wa (bank26_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank26_ram0_wr_en_d2) //|< r +,.di (bank26_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank26_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank26_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank26_ram1_rd_en_d1) //|< r +,.dout (bank26_ram1_rd_data) //|> w +,.wa (bank26_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank26_ram1_wr_en_d2) //|< r +,.di (bank26_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank27_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank27_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank27_ram0_rd_en_d1) //|< r +,.dout (bank27_ram0_rd_data) //|> w +,.wa (bank27_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank27_ram0_wr_en_d2) //|< r +,.di (bank27_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank27_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank27_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank27_ram1_rd_en_d1) //|< r +,.dout (bank27_ram1_rd_data) //|> w +,.wa (bank27_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank27_ram1_wr_en_d2) //|< r +,.di (bank27_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank28_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank28_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank28_ram0_rd_en_d1) //|< r +,.dout (bank28_ram0_rd_data) //|> w +,.wa (bank28_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank28_ram0_wr_en_d2) //|< r +,.di (bank28_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank28_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank28_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank28_ram1_rd_en_d1) //|< r +,.dout (bank28_ram1_rd_data) //|> w +,.wa (bank28_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank28_ram1_wr_en_d2) //|< r +,.di (bank28_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank29_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank29_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank29_ram0_rd_en_d1) //|< r +,.dout (bank29_ram0_rd_data) //|> w +,.wa (bank29_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank29_ram0_wr_en_d2) //|< r +,.di (bank29_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank29_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank29_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank29_ram1_rd_en_d1) //|< r +,.dout (bank29_ram1_rd_data) //|> w +,.wa (bank29_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank29_ram1_wr_en_d2) //|< r +,.di (bank29_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank30_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank30_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank30_ram0_rd_en_d1) //|< r +,.dout (bank30_ram0_rd_data) //|> w +,.wa (bank30_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank30_ram0_wr_en_d2) //|< r +,.di (bank30_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank30_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank30_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank30_ram1_rd_en_d1) //|< r +,.dout (bank30_ram1_rd_data) //|> w +,.wa (bank30_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank30_ram1_wr_en_d2) //|< r +,.di (bank30_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank31_ram0 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank31_ram0_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank31_ram0_rd_en_d1) //|< r +,.dout (bank31_ram0_rd_data) //|> w +,.wa (bank31_ram0_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank31_ram0_wr_en_d2) //|< r +,.di (bank31_ram0_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +nv_ram_rws_256x64 u_cbuf_ram_bank31_ram1 ( +.clk (nvdla_core_clk) //|< i +,.ra (bank31_ram1_rd_addr_d1[9 -1 -1:0]) //|< r +,.re (bank31_ram1_rd_en_d1) //|< r +,.dout (bank31_ram1_rd_data) //|> w +,.wa (bank31_ram1_wr_addr_d2[9 -1 -1:0]) //|< r +,.we (bank31_ram1_wr_en_d2) //|< r +,.di (bank31_ram1_wr_data_d2) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v.vcp b/designs/src/NVDLA/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v.vcp new file mode 100644 index 0000000..8f640ed --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v.vcp @@ -0,0 +1,822 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cbuf.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +`include "simulate_x_tick.vh" +module NV_NVDLA_cbuf ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//port 0 for data, 1 for weight +//: for(my $i=0; $i<2 ; $i++){ +//: print qq( +//: ,cdma2buf_wr_addr${i} //|< i +//: ,cdma2buf_wr_data${i} //|< i +//: ,cdma2buf_wr_en${i} //|< i +//: ,cdma2buf_wr_sel${i} //|< i +//: ) +//: } + ,pwrbus_ram_pd //|< i + ,sc2buf_dat_rd_addr //|< i + ,sc2buf_dat_rd_en //|< i + ,sc2buf_dat_rd_shift //|< i + ,sc2buf_dat_rd_next1_en //< i + ,sc2buf_dat_rd_next1_addr //< i + ,sc2buf_dat_rd_data //|> o + ,sc2buf_dat_rd_valid //|> o + ,sc2buf_wt_rd_addr //|< i + ,sc2buf_wt_rd_en //|< i + ,sc2buf_wt_rd_data //|> o + ,sc2buf_wt_rd_valid //|> o + `ifdef CBUF_WEIGHT_COMPRESSED + ,sc2buf_wmb_rd_addr //|< i + ,sc2buf_wmb_rd_en //|< i + ,sc2buf_wmb_rd_data //|> o + ,sc2buf_wmb_rd_valid //|> o + `endif + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +//: for(my $i=0; $i<2 ; $i++) { +//: print qq( +//: input[14 -1:0] cdma2buf_wr_addr${i}; //|< i +//: input[64 -1:0] cdma2buf_wr_data${i}; //|< i +//: input cdma2buf_wr_en${i}; //|< i +//: input[1 -1:0] cdma2buf_wr_sel${i}; //|< i +//: ) +//: } +input sc2buf_dat_rd_en; /* data valid */ +input [14 -1:0] sc2buf_dat_rd_addr; +input [7 -1:0] sc2buf_dat_rd_shift; //|< i +input sc2buf_dat_rd_next1_en; //< i +input [14 -1:0] sc2buf_dat_rd_next1_addr; //< i +output sc2buf_dat_rd_valid; /* data valid */ +output [64 -1:0] sc2buf_dat_rd_data; +input sc2buf_wt_rd_en; /* data valid */ +input [14 -1:0] sc2buf_wt_rd_addr; +output sc2buf_wt_rd_valid; /* data valid */ +output [64 -1:0] sc2buf_wt_rd_data; +`ifdef CBUF_WEIGHT_COMPRESSED +input sc2buf_wmb_rd_en; /* data valid */ +input [14 -1:0] sc2buf_wmb_rd_addr; +output sc2buf_wmb_rd_valid; /* data valid */ +output [64 -1:0] sc2buf_wmb_rd_data; +`endif +`ifndef SYNTHESIS +`ifdef CDMA2CBUF_DEBUG_PRINT +`ifdef VERILATOR +`else +reg cdma2cbuf_data_begin, cdma2cbuf_wt_begin; +integer data_file, wt_file; +initial begin + assign cdma2cbuf_wt_begin=0; + assign cdma2cbuf_data_begin=0; + @(negedge cdma2buf_wr_en1) assign cdma2cbuf_wt_begin=1; + @(negedge cdma2buf_wr_en0) assign cdma2cbuf_data_begin=1; + data_file = $fopen("cdma2cbuf_data_rtl.dat"); + wt_file = $fopen("cdma2cbuf_weight_rtl.dat"); + if(cdma2cbuf_data_begin & cdma2cbuf_wt_begin) begin + forever @(posedge nvdla_core_clk) begin + if(cdma2buf_wr_en0) begin + $fwrite(data_file,"%h\n",cdma2buf_wr_data0); + end + if (cdma2buf_wr_en1) begin + $fwrite(wt_file,"%h\n",cdma2buf_wr_data1); + end + end + end +end +`endif +`endif +`endif // SYNTHESIS +//////////step1:write handle +//decode write address to sram +//: my $bank_slice= "13:9"; #address part for select bank +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: for(my $i=0; $i<2 ; $i++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_wr${i}_en_d0 = cdma2buf_wr_en${i}&&(cdma2buf_wr_addr${i}[${bank_slice}]==${j}) &&(cdma2buf_wr_sel${i}[${k}]==1'b1); ); +//: } +//: if(2==2){ +//: print qq( +//: wire bank${j}_ram${k}_wr${i}_en_d0 = cdma2buf_wr_en${i}&&(cdma2buf_wr_addr${i}[${bank_slice}]==${j})&&(cdma2buf_wr_addr${i}[0]==${k}); ); +//: } +//: if(2==3){ +//: #complicated,reserve, no use currently +//: } +//: } +//: } +//: } +//generate sram write en +//: my $t1=""; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: for(my $i=0; $i<2; $i++){ +//: ${t1} .= "bank${j}_ram${k}_wr${i}_en_d0 |"; +//: } +//: print "wire bank${j}_ram${k}_wr_en_d0 = ${t1}"."1'b0; \n"; +//: $t1=""; +//: &eperl::flop("-q bank${j}_ram${k}_wr_en_d1 -d bank${j}_ram${k}_wr_en_d0"); +//: } +//: } +// 1 pipe for timing +//: my $kk=14; +//: my $jj=64; +//: for(my $i=0; $i<2 ; $i++){ +//: &eperl::flop("-wid ${kk} -q cdma2buf_wr_addr${i}_d1 -d cdma2buf_wr_addr${i}"); +//: &eperl::flop("-wid ${jj} -norst -q cdma2buf_wr_data${i}_d1 -d cdma2buf_wr_data${i}"); +//: } +//generate bank write en +//: my $t1=""; +//: for(my $i=0; $i<2; $i++){ +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2; $k++){ +//: $t1 .= "bank${j}_ram${k}_wr${i}_en_d0 |"; +//: } +//: print "wire bank${j}_wr${i}_en_d0 = ${t1}"."1'b0; \n"; +//: &eperl::flop("-q bank${j}_wr${i}_en_d1 -d bank${j}_wr${i}_en_d0"); +//: $t1=""; +//: } +//: } +//generate bank write addr/data +//: my $t1=""; +//: my $d1=""; +//: my $kk= 14; +//: my $jj= 64; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $i=0; $i<2; $i++){ +//: $t1 .="({${kk}{bank${j}_wr${i}_en_d1}}&cdma2buf_wr_addr${i}_d1)|"; +//: $d1 .="({${jj}{bank${j}_wr${i}_en_d1}}&cdma2buf_wr_data${i}_d1)|"; +//: } +//: my $t2 .="{${kk}{1'b0}}"; +//: my $d2 .="{${jj}{1'b0}}"; +//: print "wire [${kk}-1:0] bank${j}_wr_addr_d1 = ${t1}${t2}; \n"; +//: print "wire [${jj}-1:0] bank${j}_wr_data_d1 = ${d1}${d2}; \n"; +//: $t1=""; +//: $d1=""; +//: } +//map bank to sram. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire[9 -1 -1:0] bank${j}_ram${k}_wr_addr_d1 = bank${j}_wr_addr_d1[9 -1 -1:0]; +//: wire[64 -1:0] bank${j}_ram${k}_wr_data_d1 = bank${j}_wr_data_d1; +//: ) +//: } +//: if((2==2)||(2==3)){ +//: print qq( +//: wire[9 -1 -1:0] bank${j}_ram${k}_wr_addr_d1 = bank${j}_wr_addr_d1[9 -1:1]; +//: wire[64 -1:0] bank${j}_ram${k}_wr_data_d1 = bank${j}_wr_data_d1; +//: ) +//: } +//: } +//: } +// 1 pipe before write to sram, for timing +//: my $kk=9 -1; +//: my $jj=64; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: &eperl::flop("-q bank${j}_ram${k}_wr_en_d2 -d bank${j}_ram${k}_wr_en_d1"); +//: &eperl::flop("-wid ${kk} -q bank${j}_ram${k}_wr_addr_d2 -d bank${j}_ram${k}_wr_addr_d1"); +//: &eperl::flop("-wid ${jj} -norst -q bank${j}_ram${k}_wr_data_d2 -d bank${j}_ram${k}_wr_data_d1"); +//: } +//: } +//////////////////////step2: read data handle +//decode read data address to sram. +wire sc2buf_dat_rd_en0 = sc2buf_dat_rd_en; +wire sc2buf_dat_rd_en1 = sc2buf_dat_rd_en & sc2buf_dat_rd_next1_en; +wire[14 -1:0] sc2buf_dat_rd_addr0 = sc2buf_dat_rd_addr; +wire[14 -1:0] sc2buf_dat_rd_addr1 = sc2buf_dat_rd_next1_addr; +//: my $bank_slice= "13:9"; #address part for select bank +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd_en = sc2buf_dat_rd_en&&(sc2buf_dat_rd_addr[${bank_slice}]==${j}); ); +//: } +//: if(2==2){ +//: for(my $i=0; $i<2; $i++){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd${i}_en = sc2buf_dat_rd_en${i}&&(sc2buf_dat_rd_addr${i}[${bank_slice}]==${j})&&(sc2buf_dat_rd_addr${i}[0]==${k}); ); +//: } +//: } +//: if(2==3){ +//: #complicated,reserve, no use currently +//: } +//: } +//: } +//get sram data read address. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_data_rd_addr = {9 -1{bank${j}_ram${k}_data_rd_en}}&(sc2buf_dat_rd_addr[9 -1 -1:0]); ); +//: } +//: for(my $i=0; $i<2; $i++){ +//: if((2==2)||(2==3)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_data_rd${i}_addr = {9 -1{bank${j}_ram${k}_data_rd${i}_en}}&(sc2buf_dat_rd_addr${i}[9 -1:1]); ); +//: } +//: } +//: } +//: } +//add flop for sram data read en +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: &eperl::flop("-q bank${j}_ram${k}_data_rd_en_d1 -d bank${j}_ram${k}_data_rd_en"); +//: &eperl::flop("-q bank${j}_ram${k}_data_rd_en_d2 -d bank${j}_ram${k}_data_rd_en_d1"); +//: } +//: for(my $i=0; $i<2; $i++){ +//: if((2==2)||(2==3)){ +//: &eperl::flop("-q bank${j}_ram${k}_data_rd${i}_en_d1 -d bank${j}_ram${k}_data_rd${i}_en"); +//: &eperl::flop("-q bank${j}_ram${k}_data_rd${i}_en_d2 -d bank${j}_ram${k}_data_rd${i}_en_d1"); +//: } +//: } +//: } +//: } +//get sram data read valid. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd_valid = bank${j}_ram${k}_data_rd_en_d2; ) +//: } +//: for(my $i=0; $i<2; $i++){ +//: if((2==2)||(2==3)){ +//: print qq( +//: wire bank${j}_ram${k}_data_rd${i}_valid = bank${j}_ram${k}_data_rd${i}_en_d2; ) +//: } +//: } +//: } +//: } +//get sc data read valid. +//: my $t1=""; +//: my $t2=""; +//: if((2==0)||(2==1)||(2==4)){ +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: $t1 .= "bank${j}_ram${k}_data_rd_valid|"; +//: } +//: } +//: print "wire [0:0] sc2buf_dat_rd_valid_w = $t1"."1'b0; \n"; +//: } +//: if((2==2)||(2==3)){ +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: $t1 .= "bank${j}_ram${k}_data_rd0_valid|"; +//: $t2 .= "bank${j}_ram${k}_data_rd1_valid|"; +//: } +//: } +//: print "wire sc2buf_dat_rd_valid0 = ${t1}"."1'b0; \n"; +//: print "wire sc2buf_dat_rd_valid1 = ${t2}"."1'b0; \n"; +//: print "wire [0:0] sc2buf_dat_rd_valid_w = sc2buf_dat_rd_valid0 || sc2buf_dat_rd_valid1; \n"; +//: } +//: &eperl::retime("-O sc2buf_dat_rd_valid -i sc2buf_dat_rd_valid_w -stage 4 -clk nvdla_core_clk"); +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: print qq( +//: wire [64 -1:0] bank${j}_ram${k}_rd_data; ); +//: } +//: } +//get sc data read bank output data. +//: my $t1=""; +//: my $kk=64; +//: if(2==0){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd_data = bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd_valid}}; ); +//: } +//: } +//: if(2==1){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd_valid}}}; +//: ); +//: } +//: } +//: if(2==2){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd0_data = (bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd0_valid}})| +//: (bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd0_valid}}); +//: wire [${kk}-1:0] bank${j}_data_rd1_data = (bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd1_valid}})| +//: (bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd1_valid}}); +//: ); +//: } +//: } +//: if(2==3){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd0_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd0_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd0_valid}}}| +//: {bank${j}_ram3_rd_data&{64{bank${j}_ram3_data_rd0_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_data_rd0_valid}}}; +//: wire [${kk}-1:0] bank${j}_data_rd1_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd1_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd1_valid}}}| +//: {bank${j}_ram3_rd_data&{64{bank${j}_ram3_data_rd1_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_data_rd1_valid}}}; +//: ); +//: } +//: } +//: if(2==4){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_data_rd_data = {bank${j}_ram3_rd_data&{64{bank${j}_ram3_data_rd_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_data_rd_valid}}, +//: bank${j}_ram1_rd_data&{64{bank${j}_ram1_data_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_data_rd_valid}}}; +//: ); +//: } +//: } +//: my $kk=7; +//: &eperl::retime("-O sc2buf_dat_rd_shift_5T -i sc2buf_dat_rd_shift -wid ${kk} -stage 5 -clk nvdla_core_clk"); +// pipe solution. for timing concern, 4 level pipe. +//: my $kk=64; +//: if((2==0)||(2==1)||(2==4)){ +//: for (my $i=0; $i<32; $i++){ +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_data_rd_data -d bank${i}_data_rd_data"); +//: } +//: +//: for (my $i=0; $i<32/4; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l2group${i}_data_rd_data_w = l1group${ni}_data_rd_data | l1group${nii}_data_rd_data | l1group${niii}_data_rd_data | l1group${niiii}_data_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_data_rd_data -d l2group${i}_data_rd_data_w"); +//: } +//: +//: for (my $i=0; $i<32/16; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l3group${i}_data_rd_data_w = l2group${ni}_data_rd_data | l2group${nii}_data_rd_data | l2group${niii}_data_rd_data | l2group${niiii}_data_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_data_rd_data -d l3group${i}_data_rd_data_w"); +//: } +//: +//: if(32==16){ +//: &eperl::flop("-wid ${kk} -norst -q l4group_data_rd_data -d l3group0_data_rd_data"); +//: } +//: if(32==32) { +//: print qq( +//: wire [${kk}-1:0] l4group_data_rd_data_w = l3group0_data_rd_data | l3group1_data_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l4group_data_rd_data -d l4group_data_rd_data_w"); +//: } +//: print "wire[${kk}-1:0] sc2buf_dat_rd_data = l4group_data_rd_data[${kk}-1:0]; \n"; +//: } +//: +//: +//: my $kk=64; +//: if((2==2)||(2==3)){ +//: for (my $i=0; $i<32; $i++){ +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_data_rd0_data -d bank${i}_data_rd0_data"); +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_data_rd1_data -d bank${i}_data_rd1_data"); +//: } +//: +//: for (my $i=0; $i<32/4; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l2group${i}_data_rd0_data_w = l1group${ni}_data_rd0_data | l1group${nii}_data_rd0_data | l1group${niii}_data_rd0_data | l1group${niiii}_data_rd0_data; +//: wire [${kk}-1:0] l2group${i}_data_rd1_data_w = l1group${ni}_data_rd1_data | l1group${nii}_data_rd1_data | l1group${niii}_data_rd1_data | l1group${niiii}_data_rd1_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_data_rd0_data -d l2group${i}_data_rd0_data_w"); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_data_rd1_data -d l2group${i}_data_rd1_data_w"); +//: } +//: +//: for (my $i=0; $i<32/16; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l3group${i}_data_rd0_data_w = l2group${ni}_data_rd0_data | l2group${nii}_data_rd0_data | l2group${niii}_data_rd0_data | l2group${niiii}_data_rd0_data; +//: wire [${kk}-1:0] l3group${i}_data_rd1_data_w = l2group${ni}_data_rd1_data | l2group${nii}_data_rd1_data | l2group${niii}_data_rd1_data | l2group${niiii}_data_rd1_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_data_rd0_data -d l3group${i}_data_rd0_data_w"); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_data_rd1_data -d l3group${i}_data_rd1_data_w"); +//: } +//: +//: if(32==16){ +//: print qq( +//: wire [${kk}-1:0] l4group_data_rd0_data = l3group0_data_rd0_data; +//: wire [${kk}-1:0] l4group_data_rd1_data = l3group0_data_rd1_data; +//: ); +//: } +//: if(32==32) { +//: print qq( +//: wire [${kk}-1:0] l4group_data_rd0_data = l3group0_data_rd0_data | l3group1_data_rd0_data; +//: wire [${kk}-1:0] l4group_data_rd1_data = l3group0_data_rd1_data | l3group1_data_rd1_data; +//: ); +//: } +//: print qq( +//: wire [${kk}*2-1:0] l4group_data_rd_data_w = {l4group_data_rd1_data,l4group_data_rd0_data}>>{sc2buf_dat_rd_shift_5T,3'b0}; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l4group_data_rd_data -d l4group_data_rd_data_w[${kk}-1:0]"); +//: print "wire[${kk}-1:0] sc2buf_dat_rd_data = l4group_data_rd_data[${kk}-1:0]; \n"; +//: } +////get sc data read data. no pipe +////: my $t1=""; +////: my $t2=""; +////: my $kk=CBUF_RD_PORT_WIDTH; +////: if((CBUF_BANK_RAM_CASE==0)||(CBUF_BANK_RAM_CASE==1)||(CBUF_BANK_RAM_CASE==4)){ +////: for(my $j=0; $j> {sc2buf_dat_rd_shift_5T,3'b0}; +//wire[64 -1:0] sc2buf_dat_rd_data = sc2buf_dat_rd_data_temp[64 -1:0]; +/////////////////////step3: read weight handle +//decode read weight address to sram. +//: my $bank_slice= "13:9"; #address part for select bank +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[${bank_slice}]==${j}); ) +//: } +//: if(2==2){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[${bank_slice}]==${j})&&(sc2buf_wt_rd_addr[0]==${k}); ) +//: } +//: if(2==3){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_en = sc2buf_wt_rd_en&&(sc2buf_wt_rd_addr[${bank_slice}]==${j})&&(sc2buf_wt_rd_addr[0]==${k}/2); ) +//: } +//: } +//: } +//get sram weight read address. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: if((2==0)||(2==1)||(2==4)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_wt_rd_addr = {9 -1{bank${j}_ram${k}_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1 -1:0]); ) +//: } +//: if((2==2)||(2==3)){ +//: print qq( +//: wire [9 -1 -1:0] bank${j}_ram${k}_wt_rd_addr = {9 -1{bank${j}_ram${k}_wt_rd_en}}&(sc2buf_wt_rd_addr[9 -1:1]); ) +//: } +//: } +//: } +//add flop for sram weight read en +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: &eperl::flop("-q bank${j}_ram${k}_wt_rd_en_d1 -d bank${j}_ram${k}_wt_rd_en"); +//: &eperl::flop("-q bank${j}_ram${k}_wt_rd_en_d2 -d bank${j}_ram${k}_wt_rd_en_d1"); +//: } +//: } +//get sram weight read valid. +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: print qq( +//: wire bank${j}_ram${k}_wt_rd_valid = bank${j}_ram${k}_wt_rd_en_d2; ) +//: } +//: } +//get sc weight read valid. +//: my $t1=""; +//: for(my $j=0; $j<32 ; $j++){ +//: for(my $k=0; $k<2 ; $k++){ +//: $t1 .= "bank${j}_ram${k}_wt_rd_valid|"; +//: } +//: } +//: print "wire [0:0] sc2buf_wt_rd_valid_w ="."${t1}"."1'b0 ;\n"; +//: &eperl::retime("-O sc2buf_wt_rd_valid -i sc2buf_wt_rd_valid_w -stage 4 -clk nvdla_core_clk"); +//get sc weight read bank output data. +//: my $t1=""; +//: my $kk=64; +//: if(2==0){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}; ); +//: } +//: } +//: if(2==1){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}}; ); +//: } +//: } +//: if(2==2){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = (bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}})| +//: (bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}); +//: ); +//: } +//: } +//: if(2==3){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = {bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}}| +//: {bank${j}_ram3_rd_data&{64{bank${j}_ram3_wt_rd_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_wt_rd_valid}}}; +//: ); +//: } +//: } +//: if(2==4){ +//: for(my $j=0; $j<32 ; $j++){ +//: print qq( +//: wire [${kk}-1:0] bank${j}_wt_rd_data = {bank${j}_ram3_rd_data&{64{bank${j}_ram3_wt_rd_valid}}, +//: bank${j}_ram2_rd_data&{64{bank${j}_ram2_wt_rd_valid}}, +//: bank${j}_ram1_rd_data&{64{bank${j}_ram1_wt_rd_valid}}, +//: bank${j}_ram0_rd_data&{64{bank${j}_ram0_wt_rd_valid}}}; +//: ); +//: } +//: } +// pipe solution. for timing concern, 4 level pipe. +//: my $kk=64; +//: for (my $i=0; $i<32; $i++){ +//: &eperl::flop("-wid ${kk} -norst -q l1group${i}_wt_rd_data -d bank${i}_wt_rd_data"); +//: } +//: +//: for (my $i=0; $i<32/4; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l2group${i}_wt_rd_data_w = l1group${ni}_wt_rd_data | l1group${nii}_wt_rd_data | l1group${niii}_wt_rd_data | l1group${niiii}_wt_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l2group${i}_wt_rd_data -d l2group${i}_wt_rd_data_w"); +//: } +//: +//: for (my $i=0; $i<32/16; $i++){ +//: my $ni=$i*4; +//: my $nii=$i*4+1; +//: my $niii=$i*4+2; +//: my $niiii=$i*4+3; +//: print qq( +//: wire [${kk}-1:0] l3group${i}_wt_rd_data_w = l2group${ni}_wt_rd_data | l2group${nii}_wt_rd_data | l2group${niii}_wt_rd_data | l2group${niiii}_wt_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l3group${i}_wt_rd_data -d l3group${i}_wt_rd_data_w"); +//: } +//: +//: if(32==16){ +//: &eperl::flop("-wid ${kk} -norst -q l4group_wt_rd_data -d l3group0_wt_rd_data"); +//: } +//: if(32==32) { +//: print qq( +//: wire [${kk}-1:0] l4group_wt_rd_data_w = l3group0_wt_rd_data | l3group1_wt_rd_data; +//: ); +//: &eperl::flop("-wid ${kk} -norst -q l4group_wt_rd_data -d l4group_wt_rd_data_w"); +//: } +wire[64 -1:0] sc2buf_wt_rd_data = l4group_wt_rd_data[64 -1:0]; +////get sc weight read data. +////: my $t1=""; +////: my $kk=CBUF_RD_PORT_WIDTH; +////: for(my $j=0; $j w +//: ,.wa (bank${i}_ram${j}_wr_addr_d2[9 -1 -1:0]) //|< r +//: ,.we (bank${i}_ram${j}_wr_en_d2) //|< r +//: ,.di (bank${i}_ram${j}_wr_data_d2) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +//: ); +//: ); +//: } +//: } +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v new file mode 100644 index 0000000..28a9a37 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v @@ -0,0 +1,763 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_CVT_cell.v +module NV_NVDLA_CDMA_CVT_cell ( + cfg_mul_in_rsc_z //|< i + ,cfg_in_precision //|< i + ,cfg_out_precision //|< i + ,cfg_truncate //|< i + ,chn_alu_in_rsc_vz //|< i + ,chn_alu_in_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_in_rsc_lz //|> o + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [15:0] cfg_mul_in_rsc_z; +input [1:0] cfg_in_precision; +input [1:0] cfg_out_precision; +input [5:0] cfg_truncate; +input chn_alu_in_rsc_vz; +input [15:0] chn_alu_in_rsc_z; +input chn_data_in_rsc_vz; +input [16:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_alu_in_rsc_lz; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [15:0] chn_data_out_rsc_z; +wire [15:0] cfg_mul_in; +wire [17:0] chn_alu_ext; +wire [15:0] chn_alu_in; +wire chn_alu_prdy; +wire chn_alu_pvld; +wire [17:0] chn_data_ext; +wire [16:0] chn_data_in; +wire [15:0] chn_data_out; +wire [15:0] chn_dout; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire chn_sync_prdy; +wire chn_sync_pvld; +wire [15:0] dout_int16_sat; +wire [7:0] dout_int8_sat; +wire mon_sub_c; +wire [33:0] mul_data_out; +wire [33:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [17:0] sub_data_out; +wire [17:0] sub_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire [16:0] tru_data_out; +wire [16:0] tru_dout; +wire tru_out_prdy; +wire tru_out_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_alu_pvld = chn_alu_in_rsc_vz; +assign chn_data_in[16:0] = chn_data_in_rsc_z[16:0]; +assign chn_alu_in[15:0] = chn_alu_in_rsc_z[15:0]; +assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0]; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_alu_in_rsc_lz = chn_alu_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +assign chn_data_out_rsc_z[15:0] = chn_data_out[15:0]; +assign chn_sync_pvld = chn_alu_pvld & chn_in_pvld; +assign chn_alu_prdy = chn_sync_prdy & chn_in_pvld; +assign chn_in_prdy = chn_sync_prdy & chn_alu_pvld; +assign chn_data_ext[17:0] = {{1{chn_data_in[16]}}, chn_data_in[16:0]}; +assign chn_alu_ext[17:0] = {{2{chn_alu_in[15]}}, chn_alu_in[15:0]}; +//sub +assign {mon_sub_c,sub_dout[17:0]} = $signed(chn_data_ext[17:0]) -$signed(chn_alu_ext[17:0]); +NV_NVDLA_CDMA_CVT_CELL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_sync_pvld (chn_sync_pvld) //|< w + ,.sub_dout (sub_dout[17:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_sync_prdy (chn_sync_prdy) //|> w + ,.sub_data_out (sub_data_out[17:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[33:0] = $signed(sub_data_out[17:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDMA_CVT_CELL_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[33:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[33:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(34 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(6 )) u_shiftright_su ( + .data_in (mul_data_out[33:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_dout[16:0]) //|> w + ); +//signed +//unsigned +assign tru_data_out[16:0] = tru_dout[16:0]; +assign tru_out_pvld = mul_out_pvld; +assign mul_out_prdy = tru_out_prdy; +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(16 )) u_saturate_int16 ( + .data_in (tru_data_out[16:0]) //|< w + ,.data_out (dout_int16_sat[15:0]) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(8 )) u_saturate_int8 ( + .data_in (tru_data_out[16:0]) //|< w + ,.data_out (dout_int8_sat[7:0]) //|> w + ); +assign chn_dout = (cfg_out_precision[1:0] == 1 ) ? dout_int16_sat[15:0] : {{(16 - 8 ){dout_int8_sat[8 -1]}},dout_int8_sat[7:0]}; +NV_NVDLA_CDMA_CVT_CELL_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_dout (chn_dout[15:0]) //|< w + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.tru_out_pvld (tru_out_pvld) //|< w + ,.chn_data_out (chn_data_out[15:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.tru_out_prdy (tru_out_prdy) //|> w + ); +endmodule // NV_NVDLA_CDMA_CVT_cell +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[17:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[17:0] (chn_sync_pvld,chn_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_CVT_CELL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_sync_pvld + ,sub_dout + ,sub_out_prdy + ,chn_sync_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_sync_pvld; +input [17:0] sub_dout; +input sub_out_prdy; +output chn_sync_prdy; +output [17:0] sub_data_out; +output sub_out_pvld; +reg chn_sync_prdy; +reg [17:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [17:0] p1_skid_data; +reg [17:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [17:0] sub_data_out; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + chn_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[17:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_sync_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[17:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[17:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_sync_pvld^chn_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_sync_pvld && !chn_sync_prdy), (chn_sync_pvld), (chn_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_CVT_CELL_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[33:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[33:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_CVT_CELL_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [33:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [33:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [33:0] mul_data_out; +reg mul_out_pvld; +reg [33:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [33:0] p2_skid_data; +reg [33:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[33:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[33:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[33:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_CVT_CELL_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[15:0] (chn_out_pvld,chn_out_prdy) <= chn_dout[15:0] (tru_out_pvld,tru_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_CVT_CELL_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_dout + ,chn_out_prdy + ,tru_out_pvld + ,chn_data_out + ,chn_out_pvld + ,tru_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [15:0] chn_dout; +input chn_out_prdy; +input tru_out_pvld; +output [15:0] chn_data_out; +output chn_out_pvld; +output tru_out_prdy; +reg [15:0] chn_data_out; +reg chn_out_pvld; +reg [15:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [15:0] p3_skid_data; +reg [15:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg tru_out_prdy; +//## pipe (3) skid buffer +always @( + tru_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = tru_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + tru_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + tru_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? chn_dout[15:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or tru_out_pvld + or p3_skid_valid + or chn_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? tru_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? chn_dout[15:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or chn_out_prdy + or p3_pipe_data + ) begin + chn_out_pvld = p3_pipe_valid; + p3_pipe_ready = chn_out_prdy; + chn_data_out[15:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^tru_out_pvld^tru_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (tru_out_pvld && !tru_out_prdy), (tru_out_pvld), (tru_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_CVT_CELL_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v.vcp new file mode 100644 index 0000000..28a9a37 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v.vcp @@ -0,0 +1,763 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_CVT_cell.v +module NV_NVDLA_CDMA_CVT_cell ( + cfg_mul_in_rsc_z //|< i + ,cfg_in_precision //|< i + ,cfg_out_precision //|< i + ,cfg_truncate //|< i + ,chn_alu_in_rsc_vz //|< i + ,chn_alu_in_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_in_rsc_lz //|> o + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [15:0] cfg_mul_in_rsc_z; +input [1:0] cfg_in_precision; +input [1:0] cfg_out_precision; +input [5:0] cfg_truncate; +input chn_alu_in_rsc_vz; +input [15:0] chn_alu_in_rsc_z; +input chn_data_in_rsc_vz; +input [16:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_alu_in_rsc_lz; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [15:0] chn_data_out_rsc_z; +wire [15:0] cfg_mul_in; +wire [17:0] chn_alu_ext; +wire [15:0] chn_alu_in; +wire chn_alu_prdy; +wire chn_alu_pvld; +wire [17:0] chn_data_ext; +wire [16:0] chn_data_in; +wire [15:0] chn_data_out; +wire [15:0] chn_dout; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire chn_sync_prdy; +wire chn_sync_pvld; +wire [15:0] dout_int16_sat; +wire [7:0] dout_int8_sat; +wire mon_sub_c; +wire [33:0] mul_data_out; +wire [33:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [17:0] sub_data_out; +wire [17:0] sub_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire [16:0] tru_data_out; +wire [16:0] tru_dout; +wire tru_out_prdy; +wire tru_out_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_alu_pvld = chn_alu_in_rsc_vz; +assign chn_data_in[16:0] = chn_data_in_rsc_z[16:0]; +assign chn_alu_in[15:0] = chn_alu_in_rsc_z[15:0]; +assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0]; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_alu_in_rsc_lz = chn_alu_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +assign chn_data_out_rsc_z[15:0] = chn_data_out[15:0]; +assign chn_sync_pvld = chn_alu_pvld & chn_in_pvld; +assign chn_alu_prdy = chn_sync_prdy & chn_in_pvld; +assign chn_in_prdy = chn_sync_prdy & chn_alu_pvld; +assign chn_data_ext[17:0] = {{1{chn_data_in[16]}}, chn_data_in[16:0]}; +assign chn_alu_ext[17:0] = {{2{chn_alu_in[15]}}, chn_alu_in[15:0]}; +//sub +assign {mon_sub_c,sub_dout[17:0]} = $signed(chn_data_ext[17:0]) -$signed(chn_alu_ext[17:0]); +NV_NVDLA_CDMA_CVT_CELL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_sync_pvld (chn_sync_pvld) //|< w + ,.sub_dout (sub_dout[17:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_sync_prdy (chn_sync_prdy) //|> w + ,.sub_data_out (sub_data_out[17:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[33:0] = $signed(sub_data_out[17:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDMA_CVT_CELL_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[33:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[33:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(34 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(6 )) u_shiftright_su ( + .data_in (mul_data_out[33:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_dout[16:0]) //|> w + ); +//signed +//unsigned +assign tru_data_out[16:0] = tru_dout[16:0]; +assign tru_out_pvld = mul_out_pvld; +assign mul_out_prdy = tru_out_prdy; +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(16 )) u_saturate_int16 ( + .data_in (tru_data_out[16:0]) //|< w + ,.data_out (dout_int16_sat[15:0]) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(8 )) u_saturate_int8 ( + .data_in (tru_data_out[16:0]) //|< w + ,.data_out (dout_int8_sat[7:0]) //|> w + ); +assign chn_dout = (cfg_out_precision[1:0] == 1 ) ? dout_int16_sat[15:0] : {{(16 - 8 ){dout_int8_sat[8 -1]}},dout_int8_sat[7:0]}; +NV_NVDLA_CDMA_CVT_CELL_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_dout (chn_dout[15:0]) //|< w + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.tru_out_pvld (tru_out_pvld) //|< w + ,.chn_data_out (chn_data_out[15:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.tru_out_prdy (tru_out_prdy) //|> w + ); +endmodule // NV_NVDLA_CDMA_CVT_cell +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[17:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[17:0] (chn_sync_pvld,chn_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_CVT_CELL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_sync_pvld + ,sub_dout + ,sub_out_prdy + ,chn_sync_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_sync_pvld; +input [17:0] sub_dout; +input sub_out_prdy; +output chn_sync_prdy; +output [17:0] sub_data_out; +output sub_out_pvld; +reg chn_sync_prdy; +reg [17:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [17:0] p1_skid_data; +reg [17:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [17:0] sub_data_out; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + chn_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[17:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_sync_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[17:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[17:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_sync_pvld^chn_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_sync_pvld && !chn_sync_prdy), (chn_sync_pvld), (chn_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_CVT_CELL_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[33:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[33:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_CVT_CELL_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [33:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [33:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [33:0] mul_data_out; +reg mul_out_pvld; +reg [33:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [33:0] p2_skid_data; +reg [33:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[33:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[33:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[33:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_CVT_CELL_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[15:0] (chn_out_pvld,chn_out_prdy) <= chn_dout[15:0] (tru_out_pvld,tru_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_CVT_CELL_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_dout + ,chn_out_prdy + ,tru_out_pvld + ,chn_data_out + ,chn_out_pvld + ,tru_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [15:0] chn_dout; +input chn_out_prdy; +input tru_out_pvld; +output [15:0] chn_data_out; +output chn_out_pvld; +output tru_out_prdy; +reg [15:0] chn_data_out; +reg chn_out_pvld; +reg [15:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [15:0] p3_skid_data; +reg [15:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg tru_out_prdy; +//## pipe (3) skid buffer +always @( + tru_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = tru_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + tru_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + tru_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? chn_dout[15:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or tru_out_pvld + or p3_skid_valid + or chn_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? tru_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? chn_dout[15:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or chn_out_prdy + or p3_pipe_data + ) begin + chn_out_pvld = p3_pipe_valid; + p3_pipe_ready = chn_out_prdy; + chn_data_out[15:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^tru_out_pvld^tru_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (tru_out_pvld && !tru_out_prdy), (tru_out_pvld), (tru_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_CVT_CELL_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v new file mode 100644 index 0000000..d4d3010 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_DC_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_DC_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [5:0] wr_data; +input rd_ready; +output rd_req; +output [5:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [5:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {6{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [5:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_128x6 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_DC_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_DC_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_DC_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_DC_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_DC_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_DC_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v.vcp new file mode 100644 index 0000000..d4d3010 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v.vcp @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_DC_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_DC_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [5:0] wr_data; +input rd_ready; +output rd_req; +output [5:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [5:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {6{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [5:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_128x6 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_DC_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_DC_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_DC_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_DC_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_DC_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_DC_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v new file mode 100644 index 0000000..f59e64e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v @@ -0,0 +1,1267 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_IMG_ctrl ( + nvdla_core_clk + ,nvdla_core_ng_clk + ,nvdla_core_rstn + ,pack_is_done + ,reg2dp_conv_mode + ,reg2dp_data_bank + ,reg2dp_data_reuse + ,reg2dp_datain_format + ,reg2dp_datain_width + ,reg2dp_in_precision + ,reg2dp_op_en + ,reg2dp_pad_left + ,reg2dp_pad_right + ,reg2dp_pixel_format + ,reg2dp_pixel_mapping + ,reg2dp_pixel_sign_override + ,reg2dp_pixel_x_offset + ,reg2dp_proc_precision + ,reg2dp_skip_data_rls + ,sc2cdma_dat_pending_req + ,sg_is_done + ,status2dma_fsm_switch + ,img2status_state + ,is_running + ,layer_st + ,pixel_bank + ,pixel_data_expand + ,pixel_data_shrink + ,pixel_early_end + ,pixel_order + ,pixel_packed_10b + ,pixel_planar + ,pixel_planar0_bundle_limit + ,pixel_planar0_bundle_limit_1st + ,pixel_planar0_byte_sft + ,pixel_planar0_lp_burst + ,pixel_planar0_lp_vld + ,pixel_planar0_rp_burst + ,pixel_planar0_rp_vld + ,pixel_planar0_sft + ,pixel_planar0_width_burst + ,pixel_planar1_bundle_limit + ,pixel_planar1_bundle_limit_1st + ,pixel_planar1_byte_sft + ,pixel_planar1_lp_burst + ,pixel_planar1_lp_vld + ,pixel_planar1_rp_burst + ,pixel_planar1_rp_vld + ,pixel_planar1_sft + ,pixel_planar1_width_burst + ,pixel_precision + ,pixel_uint + ,slcg_img_gate_dc + ,slcg_img_gate_wg + ); +//////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_ng_clk; +input nvdla_core_rstn; +input pack_is_done; +input sc2cdma_dat_pending_req; +input sg_is_done; +input status2dma_fsm_switch; +output [1:0] img2status_state; +output is_running; +output layer_st; +output [5:0] pixel_bank;// +output pixel_data_expand; +output pixel_data_shrink; +output pixel_early_end; +output [10:0] pixel_order; +output pixel_packed_10b; +output pixel_planar; +output [3:0] pixel_planar0_bundle_limit; +output [3:0] pixel_planar0_bundle_limit_1st; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: output [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: output [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [3-1:0] pixel_planar0_byte_sft; +output [3-1:0] pixel_planar1_byte_sft; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [3:0] pixel_planar0_lp_burst; +output pixel_planar0_lp_vld; +output [3:0] pixel_planar0_rp_burst; +output pixel_planar0_rp_vld; +output [2:0] pixel_planar0_sft; +output [13:0] pixel_planar0_width_burst; +output [4:0] pixel_planar1_bundle_limit; +output [4:0] pixel_planar1_bundle_limit_1st; +output [2:0] pixel_planar1_lp_burst; +output pixel_planar1_lp_vld; +output [2:0] pixel_planar1_rp_burst; +output pixel_planar1_rp_vld; +output [2:0] pixel_planar1_sft; +output [13:0] pixel_planar1_width_burst; +output [1:0] pixel_precision; +output pixel_uint; +output slcg_img_gate_dc; +output slcg_img_gate_wg; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_datain_format; +input [5:0] reg2dp_pixel_format; +input [0:0] reg2dp_pixel_mapping; +input [0:0] reg2dp_pixel_sign_override; +input [12:0] reg2dp_datain_width; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_pixel_x_offset; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +//////////////////////////////////////////////////////// +reg [1:0] cur_state; +reg [4:0] delay_cnt; +reg [1:0] img2status_state; +reg is_running_d1; +reg [4:0] last_data_bank; +reg last_img; +reg last_skip_data_rls; +reg [1:0] nxt_state; +reg pending_req; +reg pending_req_d1; +reg [5:0] pixel_bank; +reg pixel_data_expand; +reg pixel_data_shrink; +reg pixel_early_end; +reg [10:0] pixel_order; +reg [10:0] pixel_order_nxt; +reg pixel_packed_10b; +reg pixel_packed_10b_nxt; +reg pixel_planar; +reg [3:0] pixel_planar0_bundle_limit; +reg [3:0] pixel_planar0_bundle_limit_1st; +reg [3:0] pixel_planar0_lp_burst; +reg pixel_planar0_lp_vld; +reg [4:0] pixel_planar0_mask_nxt; +reg [3:0] pixel_planar0_rp_burst; +reg pixel_planar0_rp_vld; +reg [2:0] pixel_planar0_sft; +reg [2:0] pixel_planar0_sft_nxt; +reg [13:0] pixel_planar0_width_burst; +reg [4:0] pixel_planar1_bundle_limit; +reg [4:0] pixel_planar1_bundle_limit_1st; +reg [2:0] pixel_planar1_lp_burst; +reg pixel_planar1_lp_vld; +reg [4:0] pixel_planar1_mask_nxt; +reg [2:0] pixel_planar1_rp_burst; +reg pixel_planar1_rp_vld; +reg [2:0] pixel_planar1_sft; +reg [2:0] pixel_planar1_sft_nxt; +reg [13:0] pixel_planar1_width_burst; +reg pixel_planar_nxt; +reg [1:0] pixel_precision; +reg [1:0] pixel_precision_nxt; +reg pixel_uint; +reg [1:0] slcg_img_gate_d1; +reg [1:0] slcg_img_gate_d2; +reg [1:0] slcg_img_gate_d3; +wire [2:0] byte_per_pixel; +wire [4:0] delay_cnt_end; +wire [4:0] delay_cnt_w; +wire [1:0] img2status_state_w; +wire img_done; +wire img_en; +wire img_end; +wire is_dc; +wire is_done; +wire is_first_running; +wire is_idle; +wire is_input_int8; +wire is_int8; +wire is_pending; +wire is_pixel; +wire is_running; +wire layer_st; +wire mode_match; +wire mon_delay_cnt_w; +wire [2:0] mon_pixel_element_sft_w; +wire mon_pixel_planar0_burst_need_w; +wire [2:0] mon_pixel_planar0_byte_sft_w; +wire [1:0] mon_pixel_planar0_lp_burst_w; +wire [10:0] mon_pixel_planar0_rp_burst_w; +wire mon_pixel_planar0_width_burst_w; +wire [3:0] mon_pixel_planar1_burst_need_w; +wire [2:0] mon_pixel_planar1_byte_sft_w; +wire [2:0] mon_pixel_planar1_lp_burst_w; +wire [11:0] mon_pixel_planar1_rp_burst_w; +wire [1:0] mon_pixel_planar1_total_burst_w; +wire [2:0] mon_pixel_planar1_total_width_w; +wire [3:0] mon_pixel_planar1_width_burst_w; +wire need_pending; +wire pending_req_end; +wire pixel_data_expand_nxt; +wire pixel_data_shrink_nxt; +wire pixel_early_end_w; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: wire [${atmmbw}-1:0] pixel_element_sft_w ; +//: wire [${atmmbw}-1:0] pixel_planar0_byte_sft_w; +//: wire [${atmmbw}-1:0] pixel_planar1_byte_sft_w; +//: reg [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: reg [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [3-1:0] pixel_element_sft_w ; +wire [3-1:0] pixel_planar0_byte_sft_w; +wire [3-1:0] pixel_planar1_byte_sft_w; +reg [3-1:0] pixel_planar0_byte_sft; +reg [3-1:0] pixel_planar1_byte_sft; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [3:0] pixel_planar0_bundle_limit_1st_w; +wire [3:0] pixel_planar0_bundle_limit_w; +wire [13:0] pixel_planar0_burst_need_w; +wire [13:0] pixel_planar0_fetch_width; +wire [3:0] pixel_planar0_lp_burst_w; +wire [4:0] pixel_planar0_lp_filled; +wire pixel_planar0_lp_vld_w; +wire [3:0] pixel_planar0_rp_burst_w; +wire pixel_planar0_rp_vld_w; +wire [13:0] pixel_planar0_width_burst_w; +wire [4:0] pixel_planar1_bundle_limit_1st_w; +wire [4:0] pixel_planar1_bundle_limit_w; +wire [13:0] pixel_planar1_burst_need_w; +wire [13:0] pixel_planar1_fetch_width; +wire [2:0] pixel_planar1_lp_burst_w; +wire [4:0] pixel_planar1_lp_filled; +wire pixel_planar1_lp_vld_w; +wire [2:0] pixel_planar1_rp_burst_w; +wire pixel_planar1_rp_vld_w; +wire [2:0] pixel_planar1_tail_width_w; +wire [1:0] pixel_planar1_total_burst_w; +//: my $dmaif_bw = int( log(int(64/8)) / log(2) ); +//: print qq( +//: wire [${dmaif_bw}-1:0] pixel_planar1_total_width_w; +//: wire [${dmaif_bw}-1:0] mon_pixel_planar1_tail_width_w; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [3-1:0] pixel_planar1_total_width_w; +wire [3-1:0] mon_pixel_planar1_tail_width_w; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [13:0] pixel_planar1_width_burst_w; +wire [4:0] pixel_planar1_x_offset; +wire [13:0] pixel_store_width; +wire pixel_tail_1_w; +wire pixel_tail_2_w; +wire pixel_uint_nxt; +wire planar1_vld_w; +wire slcg_img_en_w; +wire [1:0] slcg_img_gate_w; +//////////////////////////////////////////////////////////////////////// +// CDMA image input data fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +localparam IMG_STATE_IDLE = 2'b00; +localparam IMG_STATE_PEND = 2'b01; +localparam IMG_STATE_BUSY = 2'b10; +localparam IMG_STATE_DONE = 2'b11; +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + IMG_STATE_IDLE: begin + if ((img_en & need_pending)) begin + nxt_state = IMG_STATE_PEND; + end + else if ((img_en & reg2dp_data_reuse & last_skip_data_rls & mode_match)) begin + nxt_state = IMG_STATE_DONE; + end + else if (img_en) begin + nxt_state = IMG_STATE_BUSY; + end + end + IMG_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = IMG_STATE_BUSY; + end + end + IMG_STATE_BUSY: begin + if (img_done) begin + nxt_state = IMG_STATE_DONE; + end + end + IMG_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = IMG_STATE_IDLE; + end + end + endcase + end +end +//: &eperl::flop("-nodeclare -rval \"IMG_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_state <= IMG_STATE_IDLE; + end else begin + cur_state <= nxt_state; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = img_en & is_idle; +assign is_idle = (cur_state == IMG_STATE_IDLE); +assign is_pending = (cur_state == IMG_STATE_PEND); +assign is_running = (cur_state == IMG_STATE_BUSY); +assign is_done = (cur_state == IMG_STATE_DONE); +assign img2status_state_w = (nxt_state == IMG_STATE_PEND) ? 1 : + (nxt_state == IMG_STATE_BUSY) ? 2 : + (nxt_state == IMG_STATE_DONE) ? 3 : + 0 ; +assign is_first_running = is_running & ~is_running_d1; +//: &eperl::flop("-nodeclare -rval \"0\" -d \"img2status_state_w\" -q img2status_state"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img2status_state <= 'b0; + end else begin + img2status_state <= img2status_state_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_running_d1 <= 1'b0; + end else begin + is_running_d1 <= is_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +assign pending_req_end = pending_req_d1 & ~pending_req; +//================ Non-SLCG clock domain ================// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"img_en\" -q last_img"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{5{1'b1}}\" -en \"reg2dp_op_en & is_idle\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"img_en & reg2dp_skip_data_rls\" -q last_skip_data_rls"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"sc2cdma_dat_pending_req\" -q pending_req"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"pending_req\" -q pending_req_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_img <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_img <= img_en; + // VCS coverage off + end else if ((reg2dp_op_en & is_idle) == 1'b0) begin + end else begin + last_img <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_data_bank <= {5{1'b1}}; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_data_bank <= reg2dp_data_bank; + // VCS coverage off + end else if ((reg2dp_op_en & is_idle) == 1'b0) begin + end else begin + last_data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_skip_data_rls <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_skip_data_rls <= img_en & reg2dp_skip_data_rls; + // VCS coverage off + end else if ((reg2dp_op_en & is_idle) == 1'b0) begin + end else begin + last_skip_data_rls <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req <= 1'b0; + end else begin + pending_req <= sc2cdma_dat_pending_req; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req_d1 <= 1'b0; + end else begin + pending_req_d1 <= pending_req; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_img_en_w = img_en & (is_running | is_pending | is_done); +assign slcg_img_gate_w = {2{~slcg_img_en_w}}; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_img_gate_w\" -q slcg_img_gate_d1"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_img_gate_d1\" -q slcg_img_gate_d2"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_img_gate_d2\" -q slcg_img_gate_d3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_img_gate_d1 <= {2{1'b1}}; + end else begin + slcg_img_gate_d1 <= slcg_img_gate_w; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_img_gate_d2 <= {2{1'b1}}; + end else begin + slcg_img_gate_d2 <= slcg_img_gate_d1; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_img_gate_d3 <= {2{1'b1}}; + end else begin + slcg_img_gate_d3 <= slcg_img_gate_d2; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign slcg_img_gate_dc = slcg_img_gate_d3[0]; +assign slcg_img_gate_wg = slcg_img_gate_d3[1]; +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign img_end = is_running & ~is_first_running & sg_is_done & pack_is_done; +assign img_done = img_end & (delay_cnt == delay_cnt_end); +assign delay_cnt_end = (3 + 3 + 3 ) ; +assign {mon_delay_cnt_w, + delay_cnt_w} = ~is_running ? 6'b0 : + img_end ? delay_cnt + 1'b1 : {1'b0, delay_cnt}; +assign need_pending = (last_data_bank != reg2dp_data_bank); +assign mode_match = img_en & last_img; +assign is_dc = (reg2dp_conv_mode == 1'h0 ); +assign is_pixel = (reg2dp_datain_format == 1'h1 ); +assign img_en = reg2dp_op_en & is_dc & is_pixel; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"img_end | is_done\" -d \"delay_cnt_w\" -q delay_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + delay_cnt <= {5{1'b0}}; + end else begin + if ((img_end | is_done) == 1'b1) begin + delay_cnt <= delay_cnt_w; + // VCS coverage off + end else if ((img_end | is_done) == 1'b0) begin + end else begin + delay_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// pixel format parser // +//////////////////////////////////////////////////////////////////////// +// +always @(*) begin + pixel_planar_nxt = 1'h0; + pixel_precision_nxt = 2'h0; + pixel_order_nxt = 11'h1; + pixel_packed_10b_nxt = 1'b0; +//pixel_planar0_sft_nxt = 3'h3;//log2(atmm/BytePerPixel(4 in a8r8g8b8)) +//pixel_planar1_sft_nxt = 3'h5;//log2(?) +//pixel_planar0_mask_nxt = 5'h7;//atomm/(BytePerPixel) -1 +//pixel_planar1_mask_nxt = 5'h1f;//? + pixel_planar0_sft_nxt = 3'h1; + pixel_planar1_sft_nxt = 3'h3; + pixel_planar0_mask_nxt = 5'h1; + pixel_planar1_mask_nxt = 5'h7; + case(reg2dp_pixel_format) + 6'h0 : +// 0 T_R8, + begin +//pixel_planar0_sft_nxt = 3'h5; +//pixel_planar0_mask_nxt = 5'h1f; + pixel_planar0_sft_nxt = 3'h3; + pixel_planar0_mask_nxt = 5'h7; + end + 6'hc, 6'h10 : +// c T_A8B8G8R8, +// 10 T_X8B8G8R8, + begin + pixel_order_nxt = 11'h1; + end + 6'hd, 6'h11, 6'h1a : +// d T_A8R8G8B8, +// 11 T_X8R8G8B8, +// 1a T_A8Y8U8V8, + begin + pixel_order_nxt = 11'h2; + end + 6'he, 6'h12, 6'h1b : +// e T_B8G8R8A8, +// 12 T_B8G8R8X8, +// 1b T_V8U8Y8A8, + begin + pixel_order_nxt = 11'h8; + end + 6'hf, 6'h13 : +// f T_R8G8B8A8, +// 13 T_R8G8B8X8, + begin + pixel_order_nxt = 11'h20; + end + 6'h1c : +// 1c T_Y8___U8V8_N444, + begin + pixel_planar_nxt = 1'h1; + pixel_order_nxt = 11'h200; +//pixel_planar0_sft_nxt = 3'h5; +//pixel_planar1_sft_nxt = 3'h4; +//pixel_planar0_mask_nxt = 5'h1f; +//pixel_planar1_mask_nxt = 5'hf; + pixel_planar0_sft_nxt = 3'h3; + pixel_planar1_sft_nxt = 3'h2; + pixel_planar0_mask_nxt = 5'h7; + pixel_planar1_mask_nxt = 5'h3; + end + 6'h1d : +// 1d T_Y8___V8U8_N444, + begin + pixel_planar_nxt = 1'h1; +//pixel_planar0_sft_nxt = 3'h5; +//pixel_planar1_sft_nxt = 3'h4; +//pixel_planar0_mask_nxt = 5'h1f; +//pixel_planar1_mask_nxt = 5'hf; + pixel_planar0_sft_nxt = 3'h3; + pixel_planar1_sft_nxt = 3'h2; + pixel_planar0_mask_nxt = 5'h7; + pixel_planar1_mask_nxt = 5'h3; + end + endcase +end +assign is_int8 = 1'b1; +assign is_input_int8 = 1'b1; +assign pixel_data_expand_nxt = 1'b0; +assign pixel_data_shrink_nxt = 1'b0; +//////// pixel_lp_burst, pixel_width_burst, pixel_rp_burst //////// +assign pixel_uint_nxt = (reg2dp_pixel_sign_override == 1'h0 ); +assign pixel_planar1_x_offset = (reg2dp_pixel_x_offset & pixel_planar1_mask_nxt); +assign pixel_planar0_lp_filled = reg2dp_pad_left & pixel_planar0_mask_nxt; +assign pixel_planar1_lp_filled = reg2dp_pad_left & pixel_planar1_mask_nxt; +assign {mon_pixel_planar0_lp_burst_w[1:0], + pixel_planar0_lp_burst_w} = (reg2dp_pixel_x_offset >= pixel_planar0_lp_filled) ? (reg2dp_pad_left >> pixel_planar0_sft_nxt) : + (reg2dp_pad_left >> pixel_planar0_sft_nxt) + 1'b1; +assign {mon_pixel_planar1_lp_burst_w[2:0], + pixel_planar1_lp_burst_w} = (pixel_planar1_x_offset >= pixel_planar1_lp_filled) ? (reg2dp_pad_left >> pixel_planar1_sft_nxt) : + (reg2dp_pad_left >> pixel_planar1_sft_nxt) + 1'b1; +assign pixel_planar0_fetch_width = reg2dp_datain_width + reg2dp_pixel_x_offset; +assign pixel_planar1_fetch_width = reg2dp_datain_width + pixel_planar1_x_offset; +assign pixel_planar0_width_burst_w = (pixel_planar0_fetch_width >> pixel_planar0_sft_nxt) + 14'b1; +assign pixel_planar1_width_burst_w = (pixel_planar1_fetch_width >> pixel_planar1_sft_nxt) + 14'b1; +//assign {mon_pixel_planar0_width_burst_w[0], +// pixel_planar0_width_burst_w} = (pixel_planar0_fetch_width >> pixel_planar0_sft_nxt) + 14'b1; +//assign {mon_pixel_planar1_width_burst_w[3:0], +// pixel_planar1_width_burst_w} = (pixel_planar1_fetch_width >> pixel_planar1_sft_nxt) + 14'b1; +assign pixel_store_width = reg2dp_pad_left + reg2dp_datain_width + reg2dp_pad_right; +assign pixel_planar0_burst_need_w = (pixel_store_width >> pixel_planar0_sft_nxt) + 14'h2; +assign pixel_planar1_burst_need_w = (pixel_store_width >> pixel_planar1_sft_nxt) + 14'h2; +//assign {mon_pixel_planar0_burst_need_w[0], +// pixel_planar0_burst_need_w} = (pixel_store_width >> pixel_planar0_sft_nxt) + 14'h2; +//assign {mon_pixel_planar1_burst_need_w[0], +// pixel_planar1_burst_need_w} = (pixel_store_width >> pixel_planar1_sft_nxt) + 14'h2; +assign {mon_pixel_planar0_rp_burst_w[10:0], + pixel_planar0_rp_burst_w} = (pixel_planar0_burst_need_w - {10'd0,pixel_planar0_lp_burst_w}) - pixel_planar0_width_burst_w; +assign {mon_pixel_planar1_rp_burst_w[11:0], + pixel_planar1_rp_burst_w} = (pixel_planar1_burst_need_w - {11'd0,pixel_planar1_lp_burst_w}) - pixel_planar1_width_burst_w; +assign byte_per_pixel = ~(|pixel_precision_nxt) ? 3'h3 : 3'h6; +//////////////////////////////////////////////// +// early end control +//////////////////////////////////////////////// +//: my $dmaif_bw = int( log(int(64/8)) / log(2) ); +//: print qq( +//: assign {mon_pixel_planar1_total_width_w, +//: pixel_planar1_total_width_w} = reg2dp_pad_left + reg2dp_datain_width[${dmaif_bw}-1:0] + reg2dp_pad_right + 1; +//: assign {pixel_planar1_tail_width_w, +//: mon_pixel_planar1_tail_width_w} = pixel_planar1_total_width_w * byte_per_pixel + {${dmaif_bw}{1'b1}}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_pixel_planar1_total_width_w, +pixel_planar1_total_width_w} = reg2dp_pad_left + reg2dp_datain_width[3-1:0] + reg2dp_pad_right + 1; +assign {pixel_planar1_tail_width_w, +mon_pixel_planar1_tail_width_w} = pixel_planar1_total_width_w * byte_per_pixel + {3{1'b1}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: if($dmaif/$atmm == 1 ) { +//: print qq( +//: assign pixel_early_end_w = pixel_planar_nxt & ((pixel_planar1_tail_width_w==3'd1) | (pixel_planar1_tail_width_w==3'd4) | ((pixel_planar1_tail_width_w==3'd2) & {pixel_planar1_total_width_w,1'b0} > $dmaif) ); +//: ); +//: } elsif($dmaif/$atmm == 2 ) { +//: print qq( +//: assign {mon_pixel_planar1_total_burst_w[1:0], pixel_planar1_total_burst_w[1:0]} +//: = pixel_planar1_lp_burst_w[1:0] + pixel_planar1_rp_burst_w[1:0] + pixel_planar1_width_burst_w[1:0]; +//: assign pixel_tail_1_w = (pixel_planar1_tail_width_w == 3'h1) | (pixel_planar1_tail_width_w == 3'h4); +//: assign pixel_tail_2_w = (pixel_planar1_tail_width_w == 3'h2) | (pixel_planar1_tail_width_w == 3'h5); +//: assign pixel_early_end_w = pixel_planar_nxt & (pixel_tail_1_w | (pixel_tail_2_w & ~pixel_planar1_total_burst_w[1])); +//: ); +//: } elsif($dmaif/$atmm == 4 ) { +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pixel_early_end_w = pixel_planar_nxt & ((pixel_planar1_tail_width_w==3'd1) | (pixel_planar1_tail_width_w==3'd4) | ((pixel_planar1_tail_width_w==3'd2) & {pixel_planar1_total_width_w,1'b0} > 8) ); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////// +//////////////////////////////////////////////// +// assign {mon_pixel_element_sft_w, +// pixel_element_sft_w} = (reg2dp_pixel_x_offset - reg2dp_pad_left); +// 5bits means atmm bit-width +// assign {mon_pixel_planar0_byte_sft_w[4:0], +// pixel_planar0_byte_sft_w} = {pixel_element_sft_w, 5'b0} >> pixel_planar0_sft_nxt; +// assign {mon_pixel_planar1_byte_sft_w[4:0], +// pixel_planar1_byte_sft_w} = {pixel_element_sft_w, 5'b0} >> pixel_planar1_sft_nxt; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: assign {mon_pixel_element_sft_w, +//: pixel_element_sft_w} = (reg2dp_pixel_x_offset - {2'd0,reg2dp_pad_left[${atmmbw}-1:0]}); +//: assign {mon_pixel_planar0_byte_sft_w[2:0], +//: pixel_planar0_byte_sft_w} = {pixel_element_sft_w, ${atmmbw}'b0} >> pixel_planar0_sft_nxt; +//: assign {mon_pixel_planar1_byte_sft_w[2:0], +//: pixel_planar1_byte_sft_w} = {pixel_element_sft_w, ${atmmbw}'b0} >> pixel_planar1_sft_nxt; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_pixel_element_sft_w, +pixel_element_sft_w} = (reg2dp_pixel_x_offset - {2'd0,reg2dp_pad_left[3-1:0]}); +assign {mon_pixel_planar0_byte_sft_w[2:0], +pixel_planar0_byte_sft_w} = {pixel_element_sft_w, 3'b0} >> pixel_planar0_sft_nxt; +assign {mon_pixel_planar1_byte_sft_w[2:0], +pixel_planar1_byte_sft_w} = {pixel_element_sft_w, 3'b0} >> pixel_planar1_sft_nxt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pixel_planar0_bundle_limit_w = 4'h8; +assign pixel_planar0_bundle_limit_1st_w = 4'h9; +assign pixel_planar1_bundle_limit_w = 5'h10; +assign pixel_planar1_bundle_limit_1st_w = 5'h11; +assign planar1_vld_w = pixel_planar_nxt; +assign pixel_planar0_lp_vld_w = (|pixel_planar0_lp_burst_w); +assign pixel_planar1_lp_vld_w = (|pixel_planar1_lp_burst_w); +assign pixel_planar0_rp_vld_w = (|pixel_planar0_rp_burst_w); +assign pixel_planar1_rp_vld_w = (|pixel_planar1_rp_burst_w); +//: my $atmmbw = int( log(8) / log(2) ); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_planar_nxt\" -q pixel_planar"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"layer_st\" -d \"pixel_precision_nxt\" -q pixel_precision"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"pixel_order_nxt\" -q pixel_order"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_packed_10b_nxt\" -q pixel_packed_10b"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_data_expand_nxt\" -q pixel_data_expand"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_data_shrink_nxt\" -q pixel_data_shrink"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_uint_nxt\" -q pixel_uint"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_sft_nxt\" -q pixel_planar0_sft"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_sft_nxt\" -q pixel_planar1_sft"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_lp_burst_w\" -q pixel_planar0_lp_burst"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_lp_burst_w\" -q pixel_planar1_lp_burst"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_planar0_lp_vld_w\" -q pixel_planar0_lp_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_lp_vld_w\" -q pixel_planar1_lp_vld"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_width_burst_w\" -q pixel_planar0_width_burst"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_width_burst_w\" -q pixel_planar1_width_burst"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_rp_burst_w\" -q pixel_planar0_rp_burst"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_rp_burst_w\" -q pixel_planar1_rp_burst"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_planar0_rp_vld_w\" -q pixel_planar0_rp_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_rp_vld_w\" -q pixel_planar1_rp_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st & planar1_vld_w\" -d \"pixel_early_end_w\" -q pixel_early_end"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_byte_sft_w\" -q pixel_planar0_byte_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_byte_sft_w\" -q pixel_planar1_byte_sft"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"reg2dp_data_bank + 1'b1\" -q pixel_bank"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_bundle_limit_w\" -q pixel_planar0_bundle_limit"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_bundle_limit_w\" -q pixel_planar1_bundle_limit"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_bundle_limit_1st_w\" -q pixel_planar0_bundle_limit_1st"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_bundle_limit_1st_w\" -q pixel_planar1_bundle_limit_1st"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar <= pixel_planar_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_precision <= {2{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_precision <= pixel_precision_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_precision <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_order <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_order <= pixel_order_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_order <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_packed_10b <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_packed_10b <= pixel_packed_10b_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_packed_10b <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_data_expand <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_data_expand <= pixel_data_expand_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_data_expand <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_data_shrink <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_data_shrink <= pixel_data_shrink_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_data_shrink <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_uint <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_uint <= pixel_uint_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_uint <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_sft <= {3{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_sft <= pixel_planar0_sft_nxt; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_sft <= {3{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_sft <= pixel_planar1_sft_nxt; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_lp_burst <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_lp_burst <= pixel_planar0_lp_burst_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_lp_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_lp_burst <= {3{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_lp_burst <= pixel_planar1_lp_burst_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_lp_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_lp_vld <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_lp_vld <= pixel_planar0_lp_vld_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_lp_vld <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_lp_vld <= 1'b0; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_lp_vld <= pixel_planar1_lp_vld_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_lp_vld <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_width_burst <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_width_burst <= pixel_planar0_width_burst_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_width_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_width_burst <= {14{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_width_burst <= pixel_planar1_width_burst_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_width_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_rp_burst <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_rp_burst <= pixel_planar0_rp_burst_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_rp_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_rp_burst <= {3{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_rp_burst <= pixel_planar1_rp_burst_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_rp_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_rp_vld <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_rp_vld <= pixel_planar0_rp_vld_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_rp_vld <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_rp_vld <= 1'b0; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_rp_vld <= pixel_planar1_rp_vld_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_rp_vld <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_early_end <= 1'b0; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_early_end <= pixel_early_end_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_early_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_byte_sft <= {3{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_byte_sft <= pixel_planar0_byte_sft_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_byte_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_byte_sft <= {3{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_byte_sft <= pixel_planar1_byte_sft_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_byte_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_bank <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_bank <= reg2dp_data_bank + 1'b1; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_bundle_limit <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_bundle_limit <= pixel_planar0_bundle_limit_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_bundle_limit <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_bundle_limit <= {5{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_bundle_limit <= pixel_planar1_bundle_limit_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_bundle_limit <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar0_bundle_limit_1st <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_planar0_bundle_limit_1st <= pixel_planar0_bundle_limit_1st_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_planar0_bundle_limit_1st <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_planar1_bundle_limit_1st <= {5{1'b0}}; + end else begin + if ((layer_st & planar1_vld_w) == 1'b1) begin + pixel_planar1_bundle_limit_1st <= pixel_planar1_bundle_limit_1st_w; + // VCS coverage off + end else if ((layer_st & planar1_vld_w) == 1'b0) begin + end else begin + pixel_planar1_bundle_limit_1st <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_img_ctrl__img_reuse__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cur_state == IMG_STATE_IDLE) & (nxt_state == IMG_STATE_DONE)); + endproperty +// Cover 0 : "((cur_state == IMG_STATE_IDLE) & (nxt_state == IMG_STATE_DONE))" + FUNCPOINT_cdma_img_ctrl__img_reuse__0_COV : cover property (cdma_img_ctrl__img_reuse__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_ctrl__img_yuv_tail_0__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & pixel_planar_nxt & ~pixel_tail_1_w & ~pixel_tail_2_w); + endproperty +// Cover 1 : "(layer_st & pixel_planar_nxt & ~pixel_tail_1_w & ~pixel_tail_2_w)" + FUNCPOINT_cdma_img_ctrl__img_yuv_tail_0__1_COV : cover property (cdma_img_ctrl__img_yuv_tail_0__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_ctrl__img_yuv_tail_1__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & pixel_planar_nxt & pixel_tail_1_w); + endproperty +// Cover 2 : "(layer_st & pixel_planar_nxt & pixel_tail_1_w)" + FUNCPOINT_cdma_img_ctrl__img_yuv_tail_1__2_COV : cover property (cdma_img_ctrl__img_yuv_tail_1__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_ctrl__img_yuv_tail_2__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & pixel_planar_nxt & pixel_tail_2_w); + endproperty +// Cover 3 : "(layer_st & pixel_planar_nxt & pixel_tail_2_w)" + FUNCPOINT_cdma_img_ctrl__img_yuv_tail_2__3_COV : cover property (cdma_img_ctrl__img_yuv_tail_2__3_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,2,0,"No Xs allowed on cur_state") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, cur_state); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(img_end | is_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! PIXEL for non-DC") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & ~is_dc & is_pixel)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! Invalid image type") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & img_en & (reg2dp_pixel_format > 6'h23 ))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Pixel format is not pitch linear!") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (reg2dp_pixel_mapping != 1'h0 ))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Pixel X offset is out of range!") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|(reg2dp_pixel_x_offset & ~pixel_planar0_mask_nxt)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Unmatch input int8 precision") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (img_en & ((pixel_precision_nxt == 2'h0) ^ (reg2dp_in_precision == 2'h0 )))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Unmatch input int16 precision") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (img_en & (((pixel_precision_nxt == 2'h1) | (pixel_precision_nxt == 2'h2)) ^ (reg2dp_in_precision == 2'h1 )))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Unmatch input fp16 precision") zzz_assert_never_39x (nvdla_core_clk, `ASSERT_RESET, (img_en & ((pixel_precision_nxt == 2'h3) ^ (reg2dp_in_precision == 2'h2 )))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_lp_burst_w is overflow!") zzz_assert_never_40x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar0_lp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_lp_burst_w is overflow!") zzz_assert_never_41x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar1_lp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_burst_need_w is overflow!") zzz_assert_never_42x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar0_burst_need_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_burst_need_w is overflow!") zzz_assert_never_43x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar1_burst_need_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_rp_burst_w is overflow!") zzz_assert_never_44x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar0_rp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_rp_burst_w is overflow!") zzz_assert_never_45x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar1_rp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_lp_burst_w is out of range!") zzz_assert_never_46x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar0_lp_burst_w > 4'h8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_lp_burst_w is out of range!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar1_lp_burst_w > 3'h4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_rp_burst_w is out of range!") zzz_assert_never_48x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar0_rp_burst_w > 4'h9))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_rp_burst_w is out of range!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar1_rp_burst_w > 3'h5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_tail_width_w is out of range!") zzz_assert_never_50x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar1_tail_width_w == 3'h7))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_IMG_ctrl diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v.vcp new file mode 100644 index 0000000..6daa638 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v.vcp @@ -0,0 +1,715 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_IMG_ctrl ( + nvdla_core_clk + ,nvdla_core_ng_clk + ,nvdla_core_rstn + ,pack_is_done + ,reg2dp_conv_mode + ,reg2dp_data_bank + ,reg2dp_data_reuse + ,reg2dp_datain_format + ,reg2dp_datain_width + ,reg2dp_in_precision + ,reg2dp_op_en + ,reg2dp_pad_left + ,reg2dp_pad_right + ,reg2dp_pixel_format + ,reg2dp_pixel_mapping + ,reg2dp_pixel_sign_override + ,reg2dp_pixel_x_offset + ,reg2dp_proc_precision + ,reg2dp_skip_data_rls + ,sc2cdma_dat_pending_req + ,sg_is_done + ,status2dma_fsm_switch + ,img2status_state + ,is_running + ,layer_st + ,pixel_bank + ,pixel_data_expand + ,pixel_data_shrink + ,pixel_early_end + ,pixel_order + ,pixel_packed_10b + ,pixel_planar + ,pixel_planar0_bundle_limit + ,pixel_planar0_bundle_limit_1st + ,pixel_planar0_byte_sft + ,pixel_planar0_lp_burst + ,pixel_planar0_lp_vld + ,pixel_planar0_rp_burst + ,pixel_planar0_rp_vld + ,pixel_planar0_sft + ,pixel_planar0_width_burst + ,pixel_planar1_bundle_limit + ,pixel_planar1_bundle_limit_1st + ,pixel_planar1_byte_sft + ,pixel_planar1_lp_burst + ,pixel_planar1_lp_vld + ,pixel_planar1_rp_burst + ,pixel_planar1_rp_vld + ,pixel_planar1_sft + ,pixel_planar1_width_burst + ,pixel_precision + ,pixel_uint + ,slcg_img_gate_dc + ,slcg_img_gate_wg + ); +//////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_ng_clk; +input nvdla_core_rstn; +input pack_is_done; +input sc2cdma_dat_pending_req; +input sg_is_done; +input status2dma_fsm_switch; +output [1:0] img2status_state; +output is_running; +output layer_st; +output [5:0] pixel_bank;// +output pixel_data_expand; +output pixel_data_shrink; +output pixel_early_end; +output [10:0] pixel_order; +output pixel_packed_10b; +output pixel_planar; +output [3:0] pixel_planar0_bundle_limit; +output [3:0] pixel_planar0_bundle_limit_1st; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: output [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: output [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +output [3:0] pixel_planar0_lp_burst; +output pixel_planar0_lp_vld; +output [3:0] pixel_planar0_rp_burst; +output pixel_planar0_rp_vld; +output [2:0] pixel_planar0_sft; +output [13:0] pixel_planar0_width_burst; +output [4:0] pixel_planar1_bundle_limit; +output [4:0] pixel_planar1_bundle_limit_1st; +output [2:0] pixel_planar1_lp_burst; +output pixel_planar1_lp_vld; +output [2:0] pixel_planar1_rp_burst; +output pixel_planar1_rp_vld; +output [2:0] pixel_planar1_sft; +output [13:0] pixel_planar1_width_burst; +output [1:0] pixel_precision; +output pixel_uint; +output slcg_img_gate_dc; +output slcg_img_gate_wg; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_datain_format; +input [5:0] reg2dp_pixel_format; +input [0:0] reg2dp_pixel_mapping; +input [0:0] reg2dp_pixel_sign_override; +input [12:0] reg2dp_datain_width; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_pixel_x_offset; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +//////////////////////////////////////////////////////// +reg [1:0] cur_state; +reg [4:0] delay_cnt; +reg [1:0] img2status_state; +reg is_running_d1; +reg [4:0] last_data_bank; +reg last_img; +reg last_skip_data_rls; +reg [1:0] nxt_state; +reg pending_req; +reg pending_req_d1; +reg [5:0] pixel_bank; +reg pixel_data_expand; +reg pixel_data_shrink; +reg pixel_early_end; +reg [10:0] pixel_order; +reg [10:0] pixel_order_nxt; +reg pixel_packed_10b; +reg pixel_packed_10b_nxt; +reg pixel_planar; +reg [3:0] pixel_planar0_bundle_limit; +reg [3:0] pixel_planar0_bundle_limit_1st; +reg [3:0] pixel_planar0_lp_burst; +reg pixel_planar0_lp_vld; +reg [4:0] pixel_planar0_mask_nxt; +reg [3:0] pixel_planar0_rp_burst; +reg pixel_planar0_rp_vld; +reg [2:0] pixel_planar0_sft; +reg [2:0] pixel_planar0_sft_nxt; +reg [13:0] pixel_planar0_width_burst; +reg [4:0] pixel_planar1_bundle_limit; +reg [4:0] pixel_planar1_bundle_limit_1st; +reg [2:0] pixel_planar1_lp_burst; +reg pixel_planar1_lp_vld; +reg [4:0] pixel_planar1_mask_nxt; +reg [2:0] pixel_planar1_rp_burst; +reg pixel_planar1_rp_vld; +reg [2:0] pixel_planar1_sft; +reg [2:0] pixel_planar1_sft_nxt; +reg [13:0] pixel_planar1_width_burst; +reg pixel_planar_nxt; +reg [1:0] pixel_precision; +reg [1:0] pixel_precision_nxt; +reg pixel_uint; +reg [1:0] slcg_img_gate_d1; +reg [1:0] slcg_img_gate_d2; +reg [1:0] slcg_img_gate_d3; +wire [2:0] byte_per_pixel; +wire [4:0] delay_cnt_end; +wire [4:0] delay_cnt_w; +wire [1:0] img2status_state_w; +wire img_done; +wire img_en; +wire img_end; +wire is_dc; +wire is_done; +wire is_first_running; +wire is_idle; +wire is_input_int8; +wire is_int8; +wire is_pending; +wire is_pixel; +wire is_running; +wire layer_st; +wire mode_match; +wire mon_delay_cnt_w; +wire [2:0] mon_pixel_element_sft_w; +wire mon_pixel_planar0_burst_need_w; +wire [2:0] mon_pixel_planar0_byte_sft_w; +wire [1:0] mon_pixel_planar0_lp_burst_w; +wire [10:0] mon_pixel_planar0_rp_burst_w; +wire mon_pixel_planar0_width_burst_w; +wire [3:0] mon_pixel_planar1_burst_need_w; +wire [2:0] mon_pixel_planar1_byte_sft_w; +wire [2:0] mon_pixel_planar1_lp_burst_w; +wire [11:0] mon_pixel_planar1_rp_burst_w; +wire [1:0] mon_pixel_planar1_total_burst_w; +wire [2:0] mon_pixel_planar1_total_width_w; +wire [3:0] mon_pixel_planar1_width_burst_w; +wire need_pending; +wire pending_req_end; +wire pixel_data_expand_nxt; +wire pixel_data_shrink_nxt; +wire pixel_early_end_w; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: wire [${atmmbw}-1:0] pixel_element_sft_w ; +//: wire [${atmmbw}-1:0] pixel_planar0_byte_sft_w; +//: wire [${atmmbw}-1:0] pixel_planar1_byte_sft_w; +//: reg [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: reg [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +wire [3:0] pixel_planar0_bundle_limit_1st_w; +wire [3:0] pixel_planar0_bundle_limit_w; +wire [13:0] pixel_planar0_burst_need_w; +wire [13:0] pixel_planar0_fetch_width; +wire [3:0] pixel_planar0_lp_burst_w; +wire [4:0] pixel_planar0_lp_filled; +wire pixel_planar0_lp_vld_w; +wire [3:0] pixel_planar0_rp_burst_w; +wire pixel_planar0_rp_vld_w; +wire [13:0] pixel_planar0_width_burst_w; +wire [4:0] pixel_planar1_bundle_limit_1st_w; +wire [4:0] pixel_planar1_bundle_limit_w; +wire [13:0] pixel_planar1_burst_need_w; +wire [13:0] pixel_planar1_fetch_width; +wire [2:0] pixel_planar1_lp_burst_w; +wire [4:0] pixel_planar1_lp_filled; +wire pixel_planar1_lp_vld_w; +wire [2:0] pixel_planar1_rp_burst_w; +wire pixel_planar1_rp_vld_w; +wire [2:0] pixel_planar1_tail_width_w; +wire [1:0] pixel_planar1_total_burst_w; +//: my $dmaif_bw = int( log(int(64/8)) / log(2) ); +//: print qq( +//: wire [${dmaif_bw}-1:0] pixel_planar1_total_width_w; +//: wire [${dmaif_bw}-1:0] mon_pixel_planar1_tail_width_w; +//: ); +wire [13:0] pixel_planar1_width_burst_w; +wire [4:0] pixel_planar1_x_offset; +wire [13:0] pixel_store_width; +wire pixel_tail_1_w; +wire pixel_tail_2_w; +wire pixel_uint_nxt; +wire planar1_vld_w; +wire slcg_img_en_w; +wire [1:0] slcg_img_gate_w; +//////////////////////////////////////////////////////////////////////// +// CDMA image input data fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +localparam IMG_STATE_IDLE = 2'b00; +localparam IMG_STATE_PEND = 2'b01; +localparam IMG_STATE_BUSY = 2'b10; +localparam IMG_STATE_DONE = 2'b11; +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + IMG_STATE_IDLE: begin + if ((img_en & need_pending)) begin + nxt_state = IMG_STATE_PEND; + end + else if ((img_en & reg2dp_data_reuse & last_skip_data_rls & mode_match)) begin + nxt_state = IMG_STATE_DONE; + end + else if (img_en) begin + nxt_state = IMG_STATE_BUSY; + end + end + IMG_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = IMG_STATE_BUSY; + end + end + IMG_STATE_BUSY: begin + if (img_done) begin + nxt_state = IMG_STATE_DONE; + end + end + IMG_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = IMG_STATE_IDLE; + end + end + endcase + end +end +//: &eperl::flop("-nodeclare -rval \"IMG_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = img_en & is_idle; +assign is_idle = (cur_state == IMG_STATE_IDLE); +assign is_pending = (cur_state == IMG_STATE_PEND); +assign is_running = (cur_state == IMG_STATE_BUSY); +assign is_done = (cur_state == IMG_STATE_DONE); +assign img2status_state_w = (nxt_state == IMG_STATE_PEND) ? 1 : + (nxt_state == IMG_STATE_BUSY) ? 2 : + (nxt_state == IMG_STATE_DONE) ? 3 : + 0 ; +assign is_first_running = is_running & ~is_running_d1; +//: &eperl::flop("-nodeclare -rval \"0\" -d \"img2status_state_w\" -q img2status_state"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +assign pending_req_end = pending_req_d1 & ~pending_req; +//================ Non-SLCG clock domain ================// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"img_en\" -q last_img"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{5{1'b1}}\" -en \"reg2dp_op_en & is_idle\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"img_en & reg2dp_skip_data_rls\" -q last_skip_data_rls"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"sc2cdma_dat_pending_req\" -q pending_req"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"pending_req\" -q pending_req_d1"); +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_img_en_w = img_en & (is_running | is_pending | is_done); +assign slcg_img_gate_w = {2{~slcg_img_en_w}}; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_img_gate_w\" -q slcg_img_gate_d1"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_img_gate_d1\" -q slcg_img_gate_d2"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_img_gate_d2\" -q slcg_img_gate_d3"); +assign slcg_img_gate_dc = slcg_img_gate_d3[0]; +assign slcg_img_gate_wg = slcg_img_gate_d3[1]; +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign img_end = is_running & ~is_first_running & sg_is_done & pack_is_done; +assign img_done = img_end & (delay_cnt == delay_cnt_end); +assign delay_cnt_end = (3 + 3 + 3 ) ; +assign {mon_delay_cnt_w, + delay_cnt_w} = ~is_running ? 6'b0 : + img_end ? delay_cnt + 1'b1 : {1'b0, delay_cnt}; +assign need_pending = (last_data_bank != reg2dp_data_bank); +assign mode_match = img_en & last_img; +assign is_dc = (reg2dp_conv_mode == 1'h0 ); +assign is_pixel = (reg2dp_datain_format == 1'h1 ); +assign img_en = reg2dp_op_en & is_dc & is_pixel; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"img_end | is_done\" -d \"delay_cnt_w\" -q delay_cnt"); +//////////////////////////////////////////////////////////////////////// +// pixel format parser // +//////////////////////////////////////////////////////////////////////// +// +always @(*) begin + pixel_planar_nxt = 1'h0; + pixel_precision_nxt = 2'h0; + pixel_order_nxt = 11'h1; + pixel_packed_10b_nxt = 1'b0; +//pixel_planar0_sft_nxt = 3'h3;//log2(atmm/BytePerPixel(4 in a8r8g8b8)) +//pixel_planar1_sft_nxt = 3'h5;//log2(?) +//pixel_planar0_mask_nxt = 5'h7;//atomm/(BytePerPixel) -1 +//pixel_planar1_mask_nxt = 5'h1f;//? + pixel_planar0_sft_nxt = 3'h1; + pixel_planar1_sft_nxt = 3'h3; + pixel_planar0_mask_nxt = 5'h1; + pixel_planar1_mask_nxt = 5'h7; + case(reg2dp_pixel_format) + 6'h0 : +// 0 T_R8, + begin +//pixel_planar0_sft_nxt = 3'h5; +//pixel_planar0_mask_nxt = 5'h1f; + pixel_planar0_sft_nxt = 3'h3; + pixel_planar0_mask_nxt = 5'h7; + end + 6'hc, 6'h10 : +// c T_A8B8G8R8, +// 10 T_X8B8G8R8, + begin + pixel_order_nxt = 11'h1; + end + 6'hd, 6'h11, 6'h1a : +// d T_A8R8G8B8, +// 11 T_X8R8G8B8, +// 1a T_A8Y8U8V8, + begin + pixel_order_nxt = 11'h2; + end + 6'he, 6'h12, 6'h1b : +// e T_B8G8R8A8, +// 12 T_B8G8R8X8, +// 1b T_V8U8Y8A8, + begin + pixel_order_nxt = 11'h8; + end + 6'hf, 6'h13 : +// f T_R8G8B8A8, +// 13 T_R8G8B8X8, + begin + pixel_order_nxt = 11'h20; + end + 6'h1c : +// 1c T_Y8___U8V8_N444, + begin + pixel_planar_nxt = 1'h1; + pixel_order_nxt = 11'h200; +//pixel_planar0_sft_nxt = 3'h5; +//pixel_planar1_sft_nxt = 3'h4; +//pixel_planar0_mask_nxt = 5'h1f; +//pixel_planar1_mask_nxt = 5'hf; + pixel_planar0_sft_nxt = 3'h3; + pixel_planar1_sft_nxt = 3'h2; + pixel_planar0_mask_nxt = 5'h7; + pixel_planar1_mask_nxt = 5'h3; + end + 6'h1d : +// 1d T_Y8___V8U8_N444, + begin + pixel_planar_nxt = 1'h1; +//pixel_planar0_sft_nxt = 3'h5; +//pixel_planar1_sft_nxt = 3'h4; +//pixel_planar0_mask_nxt = 5'h1f; +//pixel_planar1_mask_nxt = 5'hf; + pixel_planar0_sft_nxt = 3'h3; + pixel_planar1_sft_nxt = 3'h2; + pixel_planar0_mask_nxt = 5'h7; + pixel_planar1_mask_nxt = 5'h3; + end + endcase +end +assign is_int8 = 1'b1; +assign is_input_int8 = 1'b1; +assign pixel_data_expand_nxt = 1'b0; +assign pixel_data_shrink_nxt = 1'b0; +//////// pixel_lp_burst, pixel_width_burst, pixel_rp_burst //////// +assign pixel_uint_nxt = (reg2dp_pixel_sign_override == 1'h0 ); +assign pixel_planar1_x_offset = (reg2dp_pixel_x_offset & pixel_planar1_mask_nxt); +assign pixel_planar0_lp_filled = reg2dp_pad_left & pixel_planar0_mask_nxt; +assign pixel_planar1_lp_filled = reg2dp_pad_left & pixel_planar1_mask_nxt; +assign {mon_pixel_planar0_lp_burst_w[1:0], + pixel_planar0_lp_burst_w} = (reg2dp_pixel_x_offset >= pixel_planar0_lp_filled) ? (reg2dp_pad_left >> pixel_planar0_sft_nxt) : + (reg2dp_pad_left >> pixel_planar0_sft_nxt) + 1'b1; +assign {mon_pixel_planar1_lp_burst_w[2:0], + pixel_planar1_lp_burst_w} = (pixel_planar1_x_offset >= pixel_planar1_lp_filled) ? (reg2dp_pad_left >> pixel_planar1_sft_nxt) : + (reg2dp_pad_left >> pixel_planar1_sft_nxt) + 1'b1; +assign pixel_planar0_fetch_width = reg2dp_datain_width + reg2dp_pixel_x_offset; +assign pixel_planar1_fetch_width = reg2dp_datain_width + pixel_planar1_x_offset; +assign pixel_planar0_width_burst_w = (pixel_planar0_fetch_width >> pixel_planar0_sft_nxt) + 14'b1; +assign pixel_planar1_width_burst_w = (pixel_planar1_fetch_width >> pixel_planar1_sft_nxt) + 14'b1; +//assign {mon_pixel_planar0_width_burst_w[0], +// pixel_planar0_width_burst_w} = (pixel_planar0_fetch_width >> pixel_planar0_sft_nxt) + 14'b1; +//assign {mon_pixel_planar1_width_burst_w[3:0], +// pixel_planar1_width_burst_w} = (pixel_planar1_fetch_width >> pixel_planar1_sft_nxt) + 14'b1; +assign pixel_store_width = reg2dp_pad_left + reg2dp_datain_width + reg2dp_pad_right; +assign pixel_planar0_burst_need_w = (pixel_store_width >> pixel_planar0_sft_nxt) + 14'h2; +assign pixel_planar1_burst_need_w = (pixel_store_width >> pixel_planar1_sft_nxt) + 14'h2; +//assign {mon_pixel_planar0_burst_need_w[0], +// pixel_planar0_burst_need_w} = (pixel_store_width >> pixel_planar0_sft_nxt) + 14'h2; +//assign {mon_pixel_planar1_burst_need_w[0], +// pixel_planar1_burst_need_w} = (pixel_store_width >> pixel_planar1_sft_nxt) + 14'h2; +assign {mon_pixel_planar0_rp_burst_w[10:0], + pixel_planar0_rp_burst_w} = (pixel_planar0_burst_need_w - {10'd0,pixel_planar0_lp_burst_w}) - pixel_planar0_width_burst_w; +assign {mon_pixel_planar1_rp_burst_w[11:0], + pixel_planar1_rp_burst_w} = (pixel_planar1_burst_need_w - {11'd0,pixel_planar1_lp_burst_w}) - pixel_planar1_width_burst_w; +assign byte_per_pixel = ~(|pixel_precision_nxt) ? 3'h3 : 3'h6; +//////////////////////////////////////////////// +// early end control +//////////////////////////////////////////////// +//: my $dmaif_bw = int( log(int(64/8)) / log(2) ); +//: print qq( +//: assign {mon_pixel_planar1_total_width_w, +//: pixel_planar1_total_width_w} = reg2dp_pad_left + reg2dp_datain_width[${dmaif_bw}-1:0] + reg2dp_pad_right + 1; +//: assign {pixel_planar1_tail_width_w, +//: mon_pixel_planar1_tail_width_w} = pixel_planar1_total_width_w * byte_per_pixel + {${dmaif_bw}{1'b1}}; +//: ); +///////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: if($dmaif/$atmm == 1 ) { +//: print qq( +//: assign pixel_early_end_w = pixel_planar_nxt & ((pixel_planar1_tail_width_w==3'd1) | (pixel_planar1_tail_width_w==3'd4) | ((pixel_planar1_tail_width_w==3'd2) & {pixel_planar1_total_width_w,1'b0} > $dmaif) ); +//: ); +//: } elsif($dmaif/$atmm == 2 ) { +//: print qq( +//: assign {mon_pixel_planar1_total_burst_w[1:0], pixel_planar1_total_burst_w[1:0]} +//: = pixel_planar1_lp_burst_w[1:0] + pixel_planar1_rp_burst_w[1:0] + pixel_planar1_width_burst_w[1:0]; +//: assign pixel_tail_1_w = (pixel_planar1_tail_width_w == 3'h1) | (pixel_planar1_tail_width_w == 3'h4); +//: assign pixel_tail_2_w = (pixel_planar1_tail_width_w == 3'h2) | (pixel_planar1_tail_width_w == 3'h5); +//: assign pixel_early_end_w = pixel_planar_nxt & (pixel_tail_1_w | (pixel_tail_2_w & ~pixel_planar1_total_burst_w[1])); +//: ); +//: } elsif($dmaif/$atmm == 4 ) { +//: } +//////////////////////////////////////////////// +//////////////////////////////////////////////// +// assign {mon_pixel_element_sft_w, +// pixel_element_sft_w} = (reg2dp_pixel_x_offset - reg2dp_pad_left); +// 5bits means atmm bit-width +// assign {mon_pixel_planar0_byte_sft_w[4:0], +// pixel_planar0_byte_sft_w} = {pixel_element_sft_w, 5'b0} >> pixel_planar0_sft_nxt; +// assign {mon_pixel_planar1_byte_sft_w[4:0], +// pixel_planar1_byte_sft_w} = {pixel_element_sft_w, 5'b0} >> pixel_planar1_sft_nxt; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: assign {mon_pixel_element_sft_w, +//: pixel_element_sft_w} = (reg2dp_pixel_x_offset - {2'd0,reg2dp_pad_left[${atmmbw}-1:0]}); +//: assign {mon_pixel_planar0_byte_sft_w[2:0], +//: pixel_planar0_byte_sft_w} = {pixel_element_sft_w, ${atmmbw}'b0} >> pixel_planar0_sft_nxt; +//: assign {mon_pixel_planar1_byte_sft_w[2:0], +//: pixel_planar1_byte_sft_w} = {pixel_element_sft_w, ${atmmbw}'b0} >> pixel_planar1_sft_nxt; +//: ); +assign pixel_planar0_bundle_limit_w = 4'h8; +assign pixel_planar0_bundle_limit_1st_w = 4'h9; +assign pixel_planar1_bundle_limit_w = 5'h10; +assign pixel_planar1_bundle_limit_1st_w = 5'h11; +assign planar1_vld_w = pixel_planar_nxt; +assign pixel_planar0_lp_vld_w = (|pixel_planar0_lp_burst_w); +assign pixel_planar1_lp_vld_w = (|pixel_planar1_lp_burst_w); +assign pixel_planar0_rp_vld_w = (|pixel_planar0_rp_burst_w); +assign pixel_planar1_rp_vld_w = (|pixel_planar1_rp_burst_w); +//: my $atmmbw = int( log(8) / log(2) ); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_planar_nxt\" -q pixel_planar"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"layer_st\" -d \"pixel_precision_nxt\" -q pixel_precision"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"pixel_order_nxt\" -q pixel_order"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_packed_10b_nxt\" -q pixel_packed_10b"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_data_expand_nxt\" -q pixel_data_expand"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_data_shrink_nxt\" -q pixel_data_shrink"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_uint_nxt\" -q pixel_uint"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_sft_nxt\" -q pixel_planar0_sft"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_sft_nxt\" -q pixel_planar1_sft"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_lp_burst_w\" -q pixel_planar0_lp_burst"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_lp_burst_w\" -q pixel_planar1_lp_burst"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_planar0_lp_vld_w\" -q pixel_planar0_lp_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_lp_vld_w\" -q pixel_planar1_lp_vld"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_width_burst_w\" -q pixel_planar0_width_burst"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_width_burst_w\" -q pixel_planar1_width_burst"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_rp_burst_w\" -q pixel_planar0_rp_burst"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_rp_burst_w\" -q pixel_planar1_rp_burst"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_planar0_rp_vld_w\" -q pixel_planar0_rp_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_rp_vld_w\" -q pixel_planar1_rp_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st & planar1_vld_w\" -d \"pixel_early_end_w\" -q pixel_early_end"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_byte_sft_w\" -q pixel_planar0_byte_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_byte_sft_w\" -q pixel_planar1_byte_sft"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"reg2dp_data_bank + 1'b1\" -q pixel_bank"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_bundle_limit_w\" -q pixel_planar0_bundle_limit"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_bundle_limit_w\" -q pixel_planar1_bundle_limit"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"pixel_planar0_bundle_limit_1st_w\" -q pixel_planar0_bundle_limit_1st"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st & planar1_vld_w\" -d \"pixel_planar1_bundle_limit_1st_w\" -q pixel_planar1_bundle_limit_1st"); +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_img_ctrl__img_reuse__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cur_state == IMG_STATE_IDLE) & (nxt_state == IMG_STATE_DONE)); + endproperty +// Cover 0 : "((cur_state == IMG_STATE_IDLE) & (nxt_state == IMG_STATE_DONE))" + FUNCPOINT_cdma_img_ctrl__img_reuse__0_COV : cover property (cdma_img_ctrl__img_reuse__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_ctrl__img_yuv_tail_0__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & pixel_planar_nxt & ~pixel_tail_1_w & ~pixel_tail_2_w); + endproperty +// Cover 1 : "(layer_st & pixel_planar_nxt & ~pixel_tail_1_w & ~pixel_tail_2_w)" + FUNCPOINT_cdma_img_ctrl__img_yuv_tail_0__1_COV : cover property (cdma_img_ctrl__img_yuv_tail_0__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_ctrl__img_yuv_tail_1__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & pixel_planar_nxt & pixel_tail_1_w); + endproperty +// Cover 2 : "(layer_st & pixel_planar_nxt & pixel_tail_1_w)" + FUNCPOINT_cdma_img_ctrl__img_yuv_tail_1__2_COV : cover property (cdma_img_ctrl__img_yuv_tail_1__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_ctrl__img_yuv_tail_2__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & pixel_planar_nxt & pixel_tail_2_w); + endproperty +// Cover 3 : "(layer_st & pixel_planar_nxt & pixel_tail_2_w)" + FUNCPOINT_cdma_img_ctrl__img_yuv_tail_2__3_COV : cover property (cdma_img_ctrl__img_yuv_tail_2__3_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,2,0,"No Xs allowed on cur_state") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, cur_state); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(img_end | is_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st & planar1_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! PIXEL for non-DC") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & ~is_dc & is_pixel)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! Invalid image type") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & img_en & (reg2dp_pixel_format > 6'h23 ))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Pixel format is not pitch linear!") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (reg2dp_pixel_mapping != 1'h0 ))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Pixel X offset is out of range!") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|(reg2dp_pixel_x_offset & ~pixel_planar0_mask_nxt)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Unmatch input int8 precision") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (img_en & ((pixel_precision_nxt == 2'h0) ^ (reg2dp_in_precision == 2'h0 )))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Unmatch input int16 precision") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (img_en & (((pixel_precision_nxt == 2'h1) | (pixel_precision_nxt == 2'h2)) ^ (reg2dp_in_precision == 2'h1 )))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! Unmatch input fp16 precision") zzz_assert_never_39x (nvdla_core_clk, `ASSERT_RESET, (img_en & ((pixel_precision_nxt == 2'h3) ^ (reg2dp_in_precision == 2'h2 )))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_lp_burst_w is overflow!") zzz_assert_never_40x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar0_lp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_lp_burst_w is overflow!") zzz_assert_never_41x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar1_lp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_burst_need_w is overflow!") zzz_assert_never_42x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar0_burst_need_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_burst_need_w is overflow!") zzz_assert_never_43x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar1_burst_need_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_rp_burst_w is overflow!") zzz_assert_never_44x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar0_rp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_rp_burst_w is overflow!") zzz_assert_never_45x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (|mon_pixel_planar1_rp_burst_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_lp_burst_w is out of range!") zzz_assert_never_46x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar0_lp_burst_w > 4'h8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_lp_burst_w is out of range!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar1_lp_burst_w > 3'h4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar0_rp_burst_w is out of range!") zzz_assert_never_48x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar0_rp_burst_w > 4'h9))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_rp_burst_w is out of range!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar1_rp_burst_w > 3'h5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pixel_planar1_tail_width_w is out of range!") zzz_assert_never_50x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (pixel_planar1_tail_width_w == 3'h7))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_IMG_ctrl diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v new file mode 100644 index 0000000..edf7a2f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_IMG_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [10:0] wr_data; +input rd_ready; +output rd_req; +output [10:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [10:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {11{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [10:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_128x11 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_IMG_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_IMG_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_IMG_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_IMG_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v.vcp new file mode 100644 index 0000000..edf7a2f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v.vcp @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_IMG_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [10:0] wr_data; +input rd_ready; +output rd_req; +output [10:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [10:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {11{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [10:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_128x11 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_IMG_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_IMG_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_IMG_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_IMG_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v new file mode 100644 index 0000000..6a6e52b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v @@ -0,0 +1,3136 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_pack.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_IMG_pack ( + nvdla_core_clk + ,nvdla_core_rstn +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,img2sbuf_p${i}_rd_data +//: ,img2sbuf_p${i}_rd_addr +//: ,img2sbuf_p${i}_rd_en +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,img2sbuf_p0_rd_data +,img2sbuf_p0_rd_addr +,img2sbuf_p0_rd_en + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,is_running + ,layer_st + ,pixel_bank + ,pixel_data_expand + ,pixel_data_shrink + ,pixel_early_end + ,pixel_packed_10b + ,pixel_planar + ,pixel_planar0_sft + ,pixel_planar1_sft + ,pixel_precision + ,pixel_uint + ,reg2dp_datain_channel + ,reg2dp_datain_width + ,reg2dp_mean_ax + ,reg2dp_mean_bv + ,reg2dp_mean_gu + ,reg2dp_mean_ry + ,reg2dp_pad_left + ,reg2dp_pad_right + ,sg2pack_data_entries + ,sg2pack_entry_end + ,sg2pack_entry_mid + ,sg2pack_entry_st + ,sg2pack_height_total + ,sg2pack_img_pd + ,sg2pack_img_pvld + ,sg2pack_mn_enable + ,sg2pack_sub_h_end + ,sg2pack_sub_h_mid + ,sg2pack_sub_h_st + ,status2dma_wr_idx +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_sel +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,img2cvt_dat_wr_addr${i} +//: ,img2cvt_dat_wr_data${i} +//: ,img2cvt_mn_wr_data${i} +//: ,img2cvt_dat_wr_pad_mask${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,img2cvt_dat_wr_addr +,img2cvt_dat_wr_data +,img2cvt_mn_wr_data +,img2cvt_dat_wr_pad_mask + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,img2cvt_dat_wr_addr +//,img2cvt_dat_wr_data + ,img2cvt_dat_wr_en +//,img2cvt_dat_wr_hsel + ,img2cvt_dat_wr_info_pd +//,img2cvt_dat_wr_pad_mask +//,img2cvt_mn_wr_data + ,img2status_dat_entries + ,img2status_dat_slices + ,img2status_dat_updt + ,pack_is_done + ,sg2pack_img_prdy + ); +///////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: input [${atmm}-1:0] img2sbuf_p${i}_rd_data; +//: output [7:0] img2sbuf_p${i}_rd_addr; +//: output img2sbuf_p${i}_rd_en; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [64-1:0] img2sbuf_p0_rd_data; +output [7:0] img2sbuf_p0_rd_addr; +output img2sbuf_p0_rd_en; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input is_running; +input layer_st; +input [5:0] pixel_bank; +input pixel_data_expand; +input pixel_data_shrink; +input pixel_early_end; +input pixel_packed_10b; +input pixel_planar; +input [2:0] pixel_planar0_sft; +input [2:0] pixel_planar1_sft; +input [1:0] pixel_precision; +input pixel_uint; +input [14:0] sg2pack_data_entries; +input [14:0] sg2pack_entry_end; +input [14:0] sg2pack_entry_mid; +input [14:0] sg2pack_entry_st; +input [12:0] sg2pack_height_total; +input [10:0] sg2pack_img_pd; +input sg2pack_img_pvld; +input sg2pack_mn_enable; +input [3:0] sg2pack_sub_h_end; +input [3:0] sg2pack_sub_h_mid; +input [3:0] sg2pack_sub_h_st; +input [14:0] status2dma_wr_idx; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_sel; +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr${i}; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] img2cvt_dat_wr_addr; +output [64-1:0] img2cvt_dat_wr_data; +output [8*16-1:0] img2cvt_mn_wr_data; +output [8-1:0] img2cvt_dat_wr_pad_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////output [11:0] img2cvt_dat_wr_addr; +////output [511:0] img2cvt_dat_wr_data; +output img2cvt_dat_wr_en; +////output img2cvt_dat_wr_hsel; +output [11:0] img2cvt_dat_wr_info_pd; +////output [1023:0] img2cvt_mn_wr_data; +////output [63:0] img2cvt_dat_wr_pad_mask;//element per dmaif +output [14:0] img2status_dat_entries; +output [13:0] img2status_dat_slices; +output img2status_dat_updt; +output pack_is_done; +output sg2pack_img_prdy; +input [12:0] reg2dp_datain_width; +input [12:0] reg2dp_datain_channel; +input [15:0] reg2dp_mean_ry; +input [15:0] reg2dp_mean_gu; +input [15:0] reg2dp_mean_bv; +input [15:0] reg2dp_mean_ax; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +///////////////////////////////////////////////////////////// +reg [5:0] data_planar0_add; +reg [13:0] data_planar0_cur_cnt; +//reg [13:0] data_planar0_ori_cnt; +reg [2:0] data_planar0_p1_flag; +//reg [2:0] data_planar0_p1_ori_flag; +reg [5:0] data_planar1_add; +reg [13:0] data_planar1_cur_cnt; +//reg [13:0] data_planar1_ori_cnt; +reg [2:0] data_planar1_p1_flag; +//reg [2:0] data_planar1_p1_ori_flag; +reg [13:0] data_width_mark_1; +reg [13:0] data_width_mark_2; +reg is_running_d1; +//: my $atmmbw = int(log(8)/log(2)); +//: print qq( +//: reg [${atmmbw}-1:0] lp_planar0_mask_sft; +//: wire [${atmmbw}-1:0] lp_planar0_mask_sft_w; +//: reg [${atmmbw}-1:0] lp_planar1_mask_sft; +//: wire [${atmmbw}-1:0] lp_planar1_mask_sft_w; +//: reg [${atmmbw}-1:0] rp_planar0_mask_sft; +//: wire [${atmmbw}-1:0] rp_planar0_mask_sft_w; +//: reg [${atmmbw}-1:0] rp_planar1_mask_sft; +//: wire [${atmmbw}-1:0] rp_planar1_mask_sft_w; +//: reg [${atmmbw}-1:0] zero_planar0_mask_sft; +//: wire [${atmmbw}-1:0] zero_planar0_mask_sft_w; +//: reg [${atmmbw}-1:0] zero_planar1_mask_sft; +//: wire [${atmmbw}-1:0] zero_planar1_mask_sft_w; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [3-1:0] lp_planar0_mask_sft; +wire [3-1:0] lp_planar0_mask_sft_w; +reg [3-1:0] lp_planar1_mask_sft; +wire [3-1:0] lp_planar1_mask_sft_w; +reg [3-1:0] rp_planar0_mask_sft; +wire [3-1:0] rp_planar0_mask_sft_w; +reg [3-1:0] rp_planar1_mask_sft; +wire [3-1:0] rp_planar1_mask_sft_w; +reg [3-1:0] zero_planar0_mask_sft; +wire [3-1:0] zero_planar0_mask_sft_w; +reg [3-1:0] zero_planar1_mask_sft; +wire [3-1:0] zero_planar1_mask_sft_w; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [64/8 -1:0] mask_pad_planar0_c0_d1; +reg [64/8 -1:0] mask_pad_planar1_c0_d1; +reg [64/8 -1:0] mask_pad_planar1_c1_d1; +reg [64/8 -1:0] mn_mask_uv_hi_d1; +reg [64/8 -1:0] mn_mask_uv_lo_d1; +reg [64/8 -1:0] mn_mask_y_d1; +reg pack_is_done; +reg [4:0] pad_left_d1; +//reg [64 -1:0] pk_mn_out_data_h0; +//reg [64 -1:0] pk_mn_out_data_h1; +reg [14:0] pk_out_addr; +reg [14:0] pk_out_data_entries; +reg [64 -1:0] pk_out_data_h0; +//reg [511:0] pk_out_data_h1; +reg [3:0] pk_out_data_slices; +reg pk_out_data_updt; +reg pk_out_ext128; +//reg pk_out_ext64; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: reg [${k}-1:0] pk_out_hsel; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [3:0] pk_out_mask; +reg pk_out_mean; +reg [64/8 -1:0] pk_out_pad_mask_h0; +//reg [63:0] pk_out_pad_mask_h1; +reg [2:0] pk_out_sub_h; +reg pk_out_uint; +reg pk_out_vld; +reg pk_rsp_1st_height_d1; +reg pk_rsp_layer_end_d1; +reg pk_rsp_loop_end_d1; +reg pk_rsp_one_line_end_d1; +reg [64 -1:0] pk_rsp_planar0_c0_d1; +reg [64 -1:0] pk_rsp_planar1_c0_d1; +reg [64 -1:0] pk_rsp_planar1_c1_d1; +reg [2:0] pk_rsp_sub_h_d1; +reg pk_rsp_sub_h_end_d1; +reg pk_rsp_vld_d1; +reg [14:0] pk_rsp_wr_base; +reg [1:0] pk_rsp_wr_cnt; +reg [14:0] pk_rsp_wr_h_offset; +reg [14:0] pk_rsp_wr_w_offset; +reg [14:0] pk_rsp_wr_w_offset_ori; +reg rd_1st_height_d1; +reg [12:0] rd_height_cnt; +reg rd_layer_end_d1; +reg rd_local_vld; +reg [3:0] rd_loop_cnt; +reg rd_loop_end_d1; +reg rd_one_line_end_d1; +reg [7:0] rd_p0_addr_d1; +reg [8 -1:0] rd_p0_pad_mask_d1; +reg [6:0] rd_p0_planar0_idx; +reg [6:0] rd_p0_planar0_ori_idx; +reg [6:0] rd_p0_planar1_idx; +reg [6:0] rd_p0_planar1_ori_idx; +reg rd_p0_vld_d1; +reg [8 -1:0] rd_p0_zero_mask_d1; +reg [7:0] rd_p1_addr_d1; +reg [8 -1:0] rd_p1_pad_mask_d1; +reg [6:0] rd_p1_planar0_idx; +reg [6:0] rd_p1_planar0_ori_idx; +reg [6:0] rd_p1_planar1_idx; +reg [6:0] rd_p1_planar1_ori_idx; +reg rd_p1_vld_d1; +reg [8 -1:0] rd_p1_zero_mask_d1; +reg [1:0] rd_pburst_cnt; +reg rd_planar_cnt; +reg rd_planar_d1; +reg [2:0] rd_sub_h_d1; +reg rd_sub_h_end_d1; +reg rd_vld_d1; +//reg [4:0] rp_planar0_mask_sft; +//wire [4:0] rp_planar0_mask_sft_w; +//reg [4:0] rp_planar1_mask_sft; +//wire [4:0] rp_planar1_mask_sft_w; +//reg [4:0] zero_planar0_mask_sft; +//wire [4:0] zero_planar0_mask_sft_w; +//reg [4:0] zero_planar1_mask_sft; +//wire [4:0] zero_planar1_mask_sft_w; +wire [64 -1:0] dat_l0; +wire [64*2-1:0] dat_l1; +wire [64 -1:0] dat_l1_hi; +wire [64 -1:0] dat_l1_lo; +wire [64*3-1:0] dat_yuv; +wire [64*3-1:0] dat_8b_yuv; +wire [5:0] data_planar0_add_w; +wire [13:0] data_planar0_cur_cnt_w; +wire data_planar0_en; +//wire data_planar0_ori_en; +wire [13:0] data_planar0_p0_cnt_w; +wire [2:0] data_planar0_p0_cur_flag; +wire [8 -1:0] data_planar0_p0_lp_mask; +wire [8 -1:0] data_planar0_p0_pad_mask; +wire [8 -1:0] data_planar0_p0_rp_mask; +wire [8 -1:0] data_planar0_p0_zero_mask; +wire [13:0] data_planar0_p1_cnt_w; +wire [2:0] data_planar0_p1_cur_flag; +wire [2:0] data_planar0_p1_flag_w; +wire [8 -1:0] data_planar0_p1_lp_mask; +wire [8 -1:0] data_planar0_p1_pad_mask; +wire [8 -1:0] data_planar0_p1_rp_mask; +wire [8 -1:0] data_planar0_p1_zero_mask; +wire [5:0] data_planar1_add_w; +wire [13:0] data_planar1_cur_cnt_w; +wire data_planar1_en; +//wire data_planar1_ori_en; +wire [13:0] data_planar1_p0_cnt_w; +wire [2:0] data_planar1_p0_cur_flag; +wire [8 -1:0] data_planar1_p0_lp_mask; +wire [8 -1:0] data_planar1_p0_pad_mask; +wire [8 -1:0] data_planar1_p0_rp_mask; +wire [8 -1:0] data_planar1_p0_zero_mask; +wire [13:0] data_planar1_p1_cnt_w; +wire [2:0] data_planar1_p1_cur_flag; +wire [2:0] data_planar1_p1_flag_w; +wire [8 -1:0] data_planar1_p1_lp_mask; +wire [8 -1:0] data_planar1_p1_pad_mask; +wire [8 -1:0] data_planar1_p1_rp_mask; +wire [8 -1:0] data_planar1_p1_zero_mask; +wire [13:0] data_width_mark_0; +wire [13:0] data_width_mark_1_w; +wire [13:0] data_width_mark_2_w; +wire img_layer_end; +wire img_line_end; +wire [3:0] img_p0_burst; +wire [4:0] img_p1_burst; +wire [10:0] img_pd; +wire is_1st_height; +wire is_addr_wrap; +wire is_base_wrap; +wire is_first_running; +wire is_last_height; +wire is_last_loop; +wire is_last_pburst; +wire is_last_planar; +wire is_last_sub_h; +wire [64/8 -1:0] mask_pad; +wire [64/8 -1:0] mask_zero; +//wire [511:0] mn_16b_mnorm; +//wire [1535:0] mn_16b_myuv; +//wire [64 -1:0] mn_8b_mnorm; +//wire [64*3-1:0] mn_8b_myuv; +//: my $mn_bw = int(64 / 8) * 16 ; +//: print qq( +//: wire [${mn_bw}-1:0] mn_ch1; +//: wire [${mn_bw}-1:0] mn_ch4; +//: wire [${mn_bw}*3-1:0] mn_ch3; +//: wire [${mn_bw}*3-1:0] mn_8b_myuv; +//: wire [${mn_bw}-1:0] mn_ch1_4; +//: wire [${mn_bw}-1:0] mn_8b_mnorm; +//: wire [${mn_bw}-1:0] pk_rsp_mn_data_h0; +//: reg [${mn_bw}-1:0] pk_mn_out_data_h0; +//: wire [${mn_bw}-1:0] pk_mn_out_data; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [128-1:0] mn_ch1; +wire [128-1:0] mn_ch4; +wire [128*3-1:0] mn_ch3; +wire [128*3-1:0] mn_8b_myuv; +wire [128-1:0] mn_ch1_4; +wire [128-1:0] mn_8b_mnorm; +wire [128-1:0] pk_rsp_mn_data_h0; +reg [128-1:0] pk_mn_out_data_h0; +wire [128-1:0] pk_mn_out_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [64 -1:0] mn_ch1; +//wire [64 -1:0] mn_ch1_4; +//wire [64*3-1:0] mn_ch3; +//wire [64 -1:0] mn_ch4; +wire [(64/8)*2-1:0] mn_mask_uv; +wire mn_mask_uv_0_en; +wire mn_mask_uv_1_en; +wire [64/8 -1:0] mn_mask_uv_hi; +wire [64/8 -1:0] mn_mask_uv_lo; +wire [64/8 -1:0] mn_mask_y; +wire mn_mask_y_en; +wire [(64/8)*3-1:0] mn_mask_yuv; +wire mon_data_planar0_p0_cnt_w; +wire mon_data_planar0_p1_cnt_w; +wire mon_data_planar1_p0_cnt_w; +wire mon_data_planar1_p1_cnt_w; +wire [2:0] mon_lp_planar0_mask_sft_w; +wire [2:0] mon_lp_planar1_mask_sft_w; +wire [2:0] mon_pk_rsp_wr_addr_wrap; +wire [1:0] mon_pk_rsp_wr_base_wrap; +wire mon_pk_rsp_wr_cnt_w; +wire mon_pk_rsp_wr_h_offset_w; +wire mon_pk_rsp_wr_w_offset_w; +wire mon_rd_loop_cnt_inc; +wire mon_rd_loop_cnt_limit; +wire [2:0] mon_rp_planar0_mask_sft_w; +wire [2:0] mon_rp_planar1_mask_sft_w; +wire [2:0] mon_zero_planar0_mask_sft_w; +wire [2:0] mon_zero_planar1_mask_sft_w; +wire pack_is_done_w; +wire [(64/8)*3-1:0] pad_mask_8b_yuv; +wire [64/8 -1:0] pad_mask_l0; +wire [(64/8)*2-1:0] pad_mask_l1; +wire [64/8 -1:0] pad_mask_l1_hi; +wire [64/8 -1:0] pad_mask_l1_lo; +wire [(64/8)*3-1:0] pad_mask_yuv; +//wire [64 -1:0] pk_mn_out_data; +wire [64 -1:0] pk_out_data; +wire [11:0] pk_out_info_pd; +//wire pk_out_interleave; +//wire [127:0] pk_out_pad_mask; +wire [64/8 -1:0] pk_out_pad_mask; +wire pk_rsp_1st_height; +wire pk_rsp_cur_1st_height; +wire pk_rsp_cur_layer_end; +wire pk_rsp_cur_loop_end; +wire pk_rsp_cur_one_line_end; +wire [2:0] pk_rsp_cur_sub_h; +wire pk_rsp_cur_sub_h_end; +wire pk_rsp_cur_vld; +//wire [1023:0] pk_rsp_dat_ergb; +//wire [1023:0] pk_rsp_dat_mergb; +wire [64 -1:0] pk_rsp_dat_mnorm; +wire [64 -1:0] pk_rsp_dat_normal; +wire [64 -1:0] pk_rsp_data_h0; +wire pk_rsp_data_h0_en; +//wire [511:0] pk_rsp_data_h1; +//wire pk_rsp_data_h1_en; +wire pk_rsp_data_updt; +wire pk_rsp_early_end; +wire pk_rsp_layer_end; +wire pk_rsp_loop_end; +//wire [64 -1:0] pk_rsp_mn_data_h0; +wire pk_rsp_mn_data_h0_en; +//wire [511:0] pk_rsp_mn_data_h1; +wire pk_rsp_mn_data_h1_en; +wire [7:0] pk_rsp_mn_sel; +wire pk_rsp_one_line_end; +wire [4:0] pk_rsp_out_sel; +wire [8*8 -1:0] pk_rsp_p0_data; +wire [8 -1:0] pk_rsp_p0_pad_mask; +wire [8 -1:0] pk_rsp_p0_zero_mask; +wire [8*8 -1:0] pk_rsp_p1_data; +wire [8 -1:0] pk_rsp_p1_pad_mask; +wire [8 -1:0] pk_rsp_p1_zero_mask; +//wire [127:0] pk_rsp_pad_mask_ergb; +wire [64/8 -1:0] pk_rsp_pad_mask_h0; +//wire [63:0] pk_rsp_pad_mask_h1; +wire [64/8 -1:0] pk_rsp_pad_mask_norm; +wire pk_rsp_pipe_sel; +wire pk_rsp_planar; +wire pk_rsp_planar0_c0_en; +wire pk_rsp_planar1_c0_en; +wire pk_rsp_planar1_c1_en; +wire [2:0] pk_rsp_sub_h; +wire pk_rsp_sub_h_end; +wire pk_rsp_vld; +wire pk_rsp_vld_d1_w; +wire [14:0] pk_rsp_wr_addr; +wire [16:0] pk_rsp_wr_addr_inc; +wire [5:0] pk_rsp_wr_addr_wrap; +wire pk_rsp_wr_base_en; +wire [15:0] pk_rsp_wr_base_inc; +wire [14:0] pk_rsp_wr_base_w; +wire [5:0] pk_rsp_wr_base_wrap; +wire [1:0] pk_rsp_wr_cnt_w; +wire [14:0] pk_rsp_wr_entries; +//wire pk_rsp_wr_ext128; +//wire pk_rsp_wr_ext64; +wire pk_rsp_wr_h_offset_en; +wire [14:0] pk_rsp_wr_h_offset_w; +wire [3:0] pk_rsp_wr_mask; +wire [2:0] pk_rsp_wr_size_ori; +wire [3:0] pk_rsp_wr_slices; +wire [1:0] pk_rsp_wr_sub_addr; +wire pk_rsp_wr_vld; +wire [2:0] pk_rsp_wr_w_add; +wire pk_rsp_wr_w_offset_en; +wire pk_rsp_wr_w_offset_ori_en; +wire [14:0] pk_rsp_wr_w_offset_w; +wire [13:0] rd_height_cnt_inc; +wire [12:0] rd_height_cnt_w; +wire rd_height_en; +wire rd_height_end; +wire [2:0] rd_idx_add; +wire rd_line_end; +wire rd_local_vld_w; +wire [3:0] rd_loop_cnt_inc; +wire [3:0] rd_loop_cnt_limit; +wire [3:0] rd_loop_cnt_w; +wire rd_loop_en; +wire rd_loop_end; +wire [7:0] rd_p0_addr; +wire [8 -1:0] rd_p0_pad_mask; +wire [7:0] rd_p0_planar0_idx_inc; +wire [6:0] rd_p0_planar0_idx_w; +wire [7:0] rd_p0_planar1_idx_inc; +wire [6:0] rd_p0_planar1_idx_w; +wire rd_p0_vld; +wire [8 -1:0] rd_p0_zero_mask; +wire [7:0] rd_p1_addr; +wire [8 -1:0] rd_p1_pad_mask; +wire [7:0] rd_p1_planar0_idx_inc; +wire [6:0] rd_p1_planar0_idx_w; +wire [7:0] rd_p1_planar1_idx_inc; +wire [6:0] rd_p1_planar1_idx_w; +wire rd_p1_vld; +wire [8 -1:0] rd_p1_zero_mask; +wire [1:0] rd_pburst_cnt_w; +wire rd_pburst_en; +wire rd_pburst_end; +wire [1:0] rd_pburst_limit; +wire rd_planar0_burst_end; +wire rd_planar0_en; +wire rd_planar0_line_end; +wire rd_planar0_ori_en; +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: print qq( +//: wire [${atmm_num}-1:0] rd_planar0_rd_mask; +//: wire [${atmm_num}-1:0] rd_planar1_rd_mask; +//: wire [${atmm_num}-1:0] rd_rd_mask; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [1-1:0] rd_planar0_rd_mask; +wire [1-1:0] rd_planar1_rd_mask; +wire [1-1:0] rd_rd_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire rd_planar1_burst_end; +wire rd_planar1_en; +wire rd_planar1_line_end; +wire rd_planar1_ori_en; +wire rd_planar_cnt_w; +wire rd_planar_en; +wire rd_planar_end; +wire [2:0] rd_sub_h_cnt; +wire rd_sub_h_end; +wire rd_vld; +wire [64 -1:0] rdat; +//wire [13:0] z14; +//wire [5:0] z6; +//////////////////////////////////////////////////////////////////////// +// signals from other modules // +//////////////////////////////////////////////////////////////////////// +assign img_pd = sg2pack_img_pvld ? sg2pack_img_pd : 11'b0; +assign img_p0_burst[3:0] = img_pd[3:0]; +assign img_p1_burst[4:0] = img_pd[8:4]; +assign img_line_end = img_pd[9]; +assign img_layer_end = img_pd[10]; +assign is_first_running = ~is_running_d1 & is_running; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_running_d1 <= 1'b0; + end else begin + is_running_d1 <= is_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// general signals // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"reg2dp_pad_left\" -q pad_left_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pad_left_d1 <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pad_left_d1 <= reg2dp_pad_left; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pad_left_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign data_width_mark_0 = {{9{1'b0}}, pad_left_d1}; +assign data_width_mark_1_w = reg2dp_pad_left + reg2dp_datain_width + 1'b1; +assign data_width_mark_2_w = reg2dp_pad_left + reg2dp_datain_width + 1'b1 + reg2dp_pad_right; +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_width_mark_1_w\" -q data_width_mark_1"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_width_mark_2_w\" -q data_width_mark_2"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width_mark_1 <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_width_mark_1 <= data_width_mark_1_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_width_mark_1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width_mark_2 <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_width_mark_2 <= data_width_mark_2_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_width_mark_2 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// 5'b0 means atmm bw +//: my $atmmbw = int(log(8)/log(2)); +//: print qq( +//: assign {mon_lp_planar0_mask_sft_w, lp_planar0_mask_sft_w} = ({data_width_mark_0[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar0_sft); +//: assign {mon_lp_planar1_mask_sft_w, lp_planar1_mask_sft_w} = ({data_width_mark_0[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar1_sft); +//: +//: assign {mon_rp_planar0_mask_sft_w, rp_planar0_mask_sft_w} = ({data_width_mark_1[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar0_sft); +//: assign {mon_rp_planar1_mask_sft_w, rp_planar1_mask_sft_w} = ({data_width_mark_1[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar1_sft); +//: +//: assign {mon_zero_planar0_mask_sft_w, zero_planar0_mask_sft_w} = ({data_width_mark_2[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar0_sft); +//: assign {mon_zero_planar1_mask_sft_w, zero_planar1_mask_sft_w} = ({data_width_mark_2[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar1_sft); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_lp_planar0_mask_sft_w, lp_planar0_mask_sft_w} = ({data_width_mark_0[3-1:0], 3'b0} >> pixel_planar0_sft); +assign {mon_lp_planar1_mask_sft_w, lp_planar1_mask_sft_w} = ({data_width_mark_0[3-1:0], 3'b0} >> pixel_planar1_sft); + +assign {mon_rp_planar0_mask_sft_w, rp_planar0_mask_sft_w} = ({data_width_mark_1[3-1:0], 3'b0} >> pixel_planar0_sft); +assign {mon_rp_planar1_mask_sft_w, rp_planar1_mask_sft_w} = ({data_width_mark_1[3-1:0], 3'b0} >> pixel_planar1_sft); + +assign {mon_zero_planar0_mask_sft_w, zero_planar0_mask_sft_w} = ({data_width_mark_2[3-1:0], 3'b0} >> pixel_planar0_sft); +assign {mon_zero_planar1_mask_sft_w, zero_planar1_mask_sft_w} = ({data_width_mark_2[3-1:0], 3'b0} >> pixel_planar1_sft); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign data_planar0_add_w = (1'b1 << pixel_planar0_sft); +assign data_planar1_add_w = (1'b1 << pixel_planar1_sft); +//: my $atmmbw = int(log(8)/log(2)); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"lp_planar0_mask_sft_w\" -q lp_planar0_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"lp_planar1_mask_sft_w\" -q lp_planar1_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"rp_planar0_mask_sft_w\" -q rp_planar0_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"rp_planar1_mask_sft_w\" -q rp_planar1_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"zero_planar0_mask_sft_w\" -q zero_planar0_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"zero_planar1_mask_sft_w\" -q zero_planar1_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"is_first_running\" -d \"data_planar0_add_w\" -q data_planar0_add"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"is_first_running\" -d \"data_planar1_add_w\" -q data_planar1_add"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lp_planar0_mask_sft <= {3{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + lp_planar0_mask_sft <= lp_planar0_mask_sft_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + lp_planar0_mask_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lp_planar1_mask_sft <= {3{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + lp_planar1_mask_sft <= lp_planar1_mask_sft_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + lp_planar1_mask_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rp_planar0_mask_sft <= {3{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + rp_planar0_mask_sft <= rp_planar0_mask_sft_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + rp_planar0_mask_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rp_planar1_mask_sft <= {3{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + rp_planar1_mask_sft <= rp_planar1_mask_sft_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + rp_planar1_mask_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + zero_planar0_mask_sft <= {3{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + zero_planar0_mask_sft <= zero_planar0_mask_sft_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + zero_planar0_mask_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + zero_planar1_mask_sft <= {3{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + zero_planar1_mask_sft <= zero_planar1_mask_sft_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + zero_planar1_mask_sft <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_planar0_add <= {6{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + data_planar0_add <= data_planar0_add_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + data_planar0_add <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_planar1_add <= {6{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + data_planar1_add <= data_planar1_add_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + data_planar1_add <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Shared buffer read sequnce generator // +//////////////////////////////////////////////////////////////////////// +assign is_1st_height = ~(|rd_height_cnt); +assign is_last_height = (rd_height_cnt == sg2pack_height_total); +assign rd_height_cnt_inc = rd_height_cnt + 1'b1; +assign rd_height_cnt_w = (is_first_running) ? 13'b0 : rd_height_cnt_inc[12:0]; +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"rd_height_en\" -d \"rd_height_cnt_w\" -q rd_height_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_height_cnt <= {13{1'b0}}; + end else begin + if ((rd_height_en) == 1'b1) begin + rd_height_cnt <= rd_height_cnt_w; + // VCS coverage off + end else if ((rd_height_en) == 1'b0) begin + end else begin + rd_height_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// sub height counter //////// +assign is_last_sub_h = 1'b1; +assign rd_sub_h_cnt = 3'b0; +//////// loop cnt //////// +// img_p0_burst[3:1],means img_p0_burst/2, 2 means atmm_num/per_dmaif +//: my $dmaif = 64; +//: my $atmm_num = int($dmaif/8/8); +//: if($atmm_num == 1) { +//: print qq( +//: assign rd_loop_cnt_limit = img_p0_burst[3:0]; +//: ) +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign {mon_rd_loop_cnt_limit, rd_loop_cnt_limit} = img_p0_burst[3:1] + img_p0_burst[0]; +//: ) +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign {mon_rd_loop_cnt_limit, rd_loop_cnt_limit} = img_p0_burst[3:2] + (|img_p0_burst[1:0]); +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign rd_loop_cnt_limit = img_p0_burst[3:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_rd_loop_cnt_inc, rd_loop_cnt_inc} = rd_loop_cnt + 1'b1; +assign is_last_loop = (rd_loop_cnt_inc >= rd_loop_cnt_limit); +assign rd_loop_cnt_w = (is_first_running | is_last_loop) ? 4'b0 : rd_loop_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"rd_loop_en\" -d \"rd_loop_cnt_w\" -q rd_loop_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_loop_cnt <= {4{1'b0}}; + end else begin + if ((rd_loop_en) == 1'b1) begin + rd_loop_cnt <= rd_loop_cnt_w; + // VCS coverage off + end else if ((rd_loop_en) == 1'b0) begin + end else begin + rd_loop_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// planar cnt //////// +assign rd_planar_cnt_w = (is_first_running | is_last_planar) ? 1'b0 : ~rd_planar_cnt; +assign is_last_planar = ~pixel_planar | rd_planar_cnt; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_planar_en\" -d \"rd_planar_cnt_w\" -q rd_planar_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_planar_cnt <= 1'b0; + end else begin + if ((rd_planar_en) == 1'b1) begin + rd_planar_cnt <= rd_planar_cnt_w; + // VCS coverage off + end else if ((rd_planar_en) == 1'b0) begin + end else begin + rd_planar_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// partial burst cnt //////// +//assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p0_burst[0])) ? 1'b1 : 1'b0; +//: my $dmaif = 64; +//: my $atmm_num = int($dmaif/8/8); +//: if($atmm_num == 1) { +//: print qq( +//: //assign rd_pburst_limit = 2'b0; +//: assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p1_burst[0])) ? 2'b1 : 2'b0; +//: ) +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p0_burst[0])) ? 2'b1 : 2'b0; +//: ) +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | (img_p0_burst[1:0]==2'd0))) ? 2'b3 +//: (rd_planar_cnt & (~is_last_loop | (img_p0_burst[1:0]==2'd1))) ? 2'b0 +//: (rd_planar_cnt & (~is_last_loop | (img_p0_burst[1:0]==2'd2))) ? 2'b1 : 2'b2; +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//assign rd_pburst_limit = 2'b0; +assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p1_burst[0])) ? 2'b1 : 2'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign is_last_pburst = (rd_pburst_cnt == rd_pburst_limit); +assign rd_pburst_cnt_w = (is_first_running | is_last_pburst) ? 2'b0 : rd_pburst_cnt + 1'b1; +//: &eperl::flop("-nodeclare -rval \"2'b0\" -en \"rd_pburst_en\" -d \"rd_pburst_cnt_w\" -q rd_pburst_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pburst_cnt <= 2'b0; + end else begin + if ((rd_pburst_en) == 1'b1) begin + rd_pburst_cnt <= rd_pburst_cnt_w; + // VCS coverage off + end else if ((rd_pburst_en) == 1'b0) begin + end else begin + rd_pburst_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// control logic //////// +assign sg2pack_img_prdy = rd_vld & rd_sub_h_end; +assign rd_vld = (sg2pack_img_pvld | rd_local_vld); +assign rd_local_vld_w = (~is_running) ? 1'b0 : + rd_sub_h_end ? 1'b0 : + sg2pack_img_pvld ? 1'b1 : rd_local_vld; +assign rd_pburst_end = rd_vld & is_last_pburst; +assign rd_planar_end = rd_vld & is_last_pburst & is_last_planar; +assign rd_loop_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop; +assign rd_sub_h_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop & is_last_sub_h; +assign rd_line_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop & is_last_sub_h & img_line_end; +assign rd_height_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop & is_last_sub_h & img_line_end & is_last_height; +assign rd_pburst_en = is_first_running | rd_vld; +assign rd_planar_en = is_first_running | (rd_pburst_end & pixel_planar); +assign rd_loop_en = is_first_running | rd_planar_end; +assign rd_height_en = is_first_running | rd_line_end; +assign rd_planar0_burst_end = rd_vld & is_last_pburst & ~rd_planar_cnt & is_last_loop; +assign rd_planar1_burst_end = rd_vld & is_last_pburst & rd_planar_cnt & is_last_loop; +assign rd_planar0_line_end = rd_vld & is_last_pburst & ~rd_planar_cnt & is_last_loop & is_last_sub_h & img_line_end; +assign rd_planar1_line_end = rd_vld & is_last_pburst & rd_planar_cnt & is_last_loop & is_last_sub_h & img_line_end; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rd_local_vld_w\" -q rd_local_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rd_vld\" -q rd_vld_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_local_vld <= 1'b0; + end else begin + rd_local_vld <= rd_local_vld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_vld_d1 <= 1'b0; + end else begin + rd_vld_d1 <= rd_vld; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// read control logic generator // +//////////////////////////////////////////////////////////////////////// +//////// read enalbe mask //////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign rd_planar0_rd_mask = 1'h1; +//: assign rd_planar1_rd_mask = 1'h1; +//: +//: assign rd_p0_vld = rd_vld & rd_rd_mask[0]; +//: +//: assign rd_idx_add = 3'h1; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rd_planar0_rd_mask = (is_last_loop & is_last_pburst & img_p0_burst[0]) ? 2'h1 : 2'h3; +//: assign rd_planar1_rd_mask = (is_last_loop & is_last_pburst & img_p1_burst[0]) ? 2'h1 : 2'h3; +//: +//: assign rd_p0_vld = rd_vld & rd_rd_mask[0]; +//: assign rd_p1_vld = rd_vld & rd_rd_mask[1]; +//: +//: assign rd_idx_add = rd_rd_mask[1] ? 3'h2 : 3'h1; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rd_planar0_rd_mask = (is_last_loop & is_last_pburst & (img_p0_burst[1:0]==2'd0)) ? 4'h1 : +//: (is_last_loop & is_last_pburst & (img_p0_burst[1:0]==2'd1)) ? 4'h3 : +//: (is_last_loop & is_last_pburst & (img_p0_burst[1:0]==2'd2)) ? 4'h7 : 4'hf; +//: assign rd_planar1_rd_mask = (is_last_loop & is_last_pburst & (img_p1_burst[1:0]==2'd0)) ? 4'h1 : +//: (is_last_loop & is_last_pburst & (img_p1_burst[1:0]==2'd1)) ? 4'h3 : +//: (is_last_loop & is_last_pburst & (img_p1_burst[1:0]==2'd2)) ? 4'h7 : 4'hf; +//: +//: assign rd_p0_vld = rd_vld & rd_rd_mask[0]; +//: assign rd_p1_vld = rd_vld & rd_rd_mask[1]; +//: assign rd_p2_vld = rd_vld & rd_rd_mask[2]; +//: assign rd_p3_vld = rd_vld & rd_rd_mask[3]; +//: +//: assign rd_idx_add = rd_rd_mask[3] ? 3'h4 : rd_rd_mask[2] ? 3'h3 : rd_rd_mask[1] ? 3'h2 : 3'h1; +//: ); +//: } +//: foreach my $i(0..$atmm_num -1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rd_p${i}_vld\" -q rd_p${i}_vld_d1"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign rd_planar0_rd_mask = 1'h1; +assign rd_planar1_rd_mask = 1'h1; + +assign rd_p0_vld = rd_vld & rd_rd_mask[0]; + +assign rd_idx_add = 3'h1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_p0_vld_d1 <= 1'b0; + end else begin + rd_p0_vld_d1 <= rd_p0_vld; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign rd_rd_mask = rd_planar_cnt ? rd_planar1_rd_mask : rd_planar0_rd_mask; +//////// read address //////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: assign rd_p${i}_planar0_idx_inc = rd_p${i}_planar0_idx + rd_idx_add; +//: assign rd_p${i}_planar1_idx_inc = rd_p${i}_planar1_idx + rd_idx_add; +//: assign rd_p${i}_planar0_idx_w = is_first_running ? 7'b${i} : rd_p${i}_planar0_idx_inc[8 -2:0]; +//: assign rd_p${i}_planar1_idx_w = is_first_running ? 7'b${i} : rd_p${i}_planar1_idx_inc[8 -2:0]; +//: assign rd_p${i}_addr = (~rd_planar_cnt) ? {1'b0, rd_p${i}_planar0_idx[0], rd_p${i}_planar0_idx[8 -2:1]} : {1'b1, rd_p${i}_planar1_idx[0], rd_p${i}_planar1_idx[8 -2:1]}; +//: ); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar0_en\" -d \"rd_p${i}_planar0_idx_w\" -q rd_p${i}_planar0_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar1_en\" -d \"rd_p${i}_planar1_idx_w\" -q rd_p${i}_planar1_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar0_ori_en\" -d \"rd_p${i}_planar0_idx_w\" -q rd_p${i}_planar0_ori_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar1_ori_en\" -d \"rd_p${i}_planar1_idx_w\" -q rd_p${i}_planar1_ori_idx"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rd_p${i}_vld\" -d \"rd_p${i}_addr\" -q rd_p${i}_addr_d1"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign rd_p0_planar0_idx_inc = rd_p0_planar0_idx + rd_idx_add; +assign rd_p0_planar1_idx_inc = rd_p0_planar1_idx + rd_idx_add; +assign rd_p0_planar0_idx_w = is_first_running ? 7'b0 : rd_p0_planar0_idx_inc[8 -2:0]; +assign rd_p0_planar1_idx_w = is_first_running ? 7'b0 : rd_p0_planar1_idx_inc[8 -2:0]; +assign rd_p0_addr = (~rd_planar_cnt) ? {1'b0, rd_p0_planar0_idx[0], rd_p0_planar0_idx[8 -2:1]} : {1'b1, rd_p0_planar1_idx[0], rd_p0_planar1_idx[8 -2:1]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_p0_planar0_idx <= {7{1'b0}}; + end else begin + if ((rd_planar0_en) == 1'b1) begin + rd_p0_planar0_idx <= rd_p0_planar0_idx_w; + // VCS coverage off + end else if ((rd_planar0_en) == 1'b0) begin + end else begin + rd_p0_planar0_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_p0_planar1_idx <= {7{1'b0}}; + end else begin + if ((rd_planar1_en) == 1'b1) begin + rd_p0_planar1_idx <= rd_p0_planar1_idx_w; + // VCS coverage off + end else if ((rd_planar1_en) == 1'b0) begin + end else begin + rd_p0_planar1_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_p0_planar0_ori_idx <= {7{1'b0}}; + end else begin + if ((rd_planar0_ori_en) == 1'b1) begin + rd_p0_planar0_ori_idx <= rd_p0_planar0_idx_w; + // VCS coverage off + end else if ((rd_planar0_ori_en) == 1'b0) begin + end else begin + rd_p0_planar0_ori_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_p0_planar1_ori_idx <= {7{1'b0}}; + end else begin + if ((rd_planar1_ori_en) == 1'b1) begin + rd_p0_planar1_ori_idx <= rd_p0_planar1_idx_w; + // VCS coverage off + end else if ((rd_planar1_ori_en) == 1'b0) begin + end else begin + rd_p0_planar1_ori_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_p0_addr_d1 <= {8{1'b0}}; + end else begin + if ((rd_p0_vld) == 1'b1) begin + rd_p0_addr_d1 <= rd_p0_addr; + // VCS coverage off + end else if ((rd_p0_vld) == 1'b0) begin + end else begin + rd_p0_addr_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// assign rd_p0_planar0_idx_w = is_first_running ? 7'b0 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p0_planar0_ori_idx : +// rd_p0_planar0_idx_inc[8 -2:0]; +// assign rd_p1_planar0_idx_w = is_first_running ? 7'b1 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p1_planar0_ori_idx : +// rd_p1_planar0_idx_inc[8 -2:0]; +// +// assign rd_p0_planar1_idx_w = is_first_running ? 7'b0 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p0_planar1_ori_idx : +// rd_p0_planar1_idx_inc[8 -2:0]; +// assign rd_p1_planar1_idx_w = is_first_running ? 7'b1 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p1_planar1_ori_idx : +// rd_p1_planar1_idx_inc[8 -2:0]; +assign rd_planar0_en = is_first_running | (rd_vld & ~rd_planar_cnt); +assign rd_planar1_en = is_first_running | (rd_vld & rd_planar_cnt); +assign rd_planar0_ori_en = is_first_running; +assign rd_planar1_ori_en = is_first_running; +//////// status logic ///////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: assign {mon_data_planar0_p${i}_cnt_w, data_planar0_p${i}_cnt_w} = data_planar0_cur_cnt + data_planar0_add * (${i}+1); +//: assign {mon_data_planar1_p${i}_cnt_w, data_planar1_p${i}_cnt_w} = data_planar1_cur_cnt + data_planar1_add * (${i}+1); +//: +//: assign data_planar0_p${i}_cur_flag[0] = (data_planar0_p${i}_cnt_w > data_width_mark_0); +//: assign data_planar0_p${i}_cur_flag[1] = (data_planar0_p${i}_cnt_w > data_width_mark_1); +//: assign data_planar0_p${i}_cur_flag[2] = (data_planar0_p${i}_cnt_w > data_width_mark_2); +//: assign data_planar1_p${i}_cur_flag[0] = (data_planar1_p${i}_cnt_w > data_width_mark_0); +//: assign data_planar1_p${i}_cur_flag[1] = (data_planar1_p${i}_cnt_w > data_width_mark_1); +//: assign data_planar1_p${i}_cur_flag[2] = (data_planar1_p${i}_cnt_w > data_width_mark_2); +//: +//: ); +//: } +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : data_planar0_p0_cnt_w; +//: assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : data_planar1_p0_cnt_w; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar0_p1_cnt_w : data_planar0_p0_cnt_w; +//: assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar1_p1_cnt_w : data_planar1_p0_cnt_w; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : (rd_p3_vld) ? data_planar0_p3_cnt_w : +//: (rd_p2_vld) ? data_planar0_p2_cnt_w : +//: (rd_p1_vld) ? data_planar0_p1_cnt_w : data_planar0_p0_cnt_w; +//: assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : (rd_p3_vld) ? data_planar1_p3_cnt_w : +//: (rd_p2_vld) ? data_planar1_p2_cnt_w : +//: (rd_p1_vld) ? data_planar1_p1_cnt_w : data_planar1_p0_cnt_w; +//: ); +//: } +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"data_planar0_en\" -d \"data_planar0_cur_cnt_w\" -q data_planar0_cur_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"data_planar1_en\" -d \"data_planar1_cur_cnt_w\" -q data_planar1_cur_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_data_planar0_p0_cnt_w, data_planar0_p0_cnt_w} = data_planar0_cur_cnt + data_planar0_add * (0+1); +assign {mon_data_planar1_p0_cnt_w, data_planar1_p0_cnt_w} = data_planar1_cur_cnt + data_planar1_add * (0+1); + +assign data_planar0_p0_cur_flag[0] = (data_planar0_p0_cnt_w > data_width_mark_0); +assign data_planar0_p0_cur_flag[1] = (data_planar0_p0_cnt_w > data_width_mark_1); +assign data_planar0_p0_cur_flag[2] = (data_planar0_p0_cnt_w > data_width_mark_2); +assign data_planar1_p0_cur_flag[0] = (data_planar1_p0_cnt_w > data_width_mark_0); +assign data_planar1_p0_cur_flag[1] = (data_planar1_p0_cnt_w > data_width_mark_1); +assign data_planar1_p0_cur_flag[2] = (data_planar1_p0_cnt_w > data_width_mark_2); + + +assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : data_planar0_p0_cnt_w; +assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : data_planar1_p0_cnt_w; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_planar0_cur_cnt <= {14{1'b0}}; + end else begin + if ((data_planar0_en) == 1'b1) begin + data_planar0_cur_cnt <= data_planar0_cur_cnt_w; + // VCS coverage off + end else if ((data_planar0_en) == 1'b0) begin + end else begin + data_planar0_cur_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_planar1_cur_cnt <= {14{1'b0}}; + end else begin + if ((data_planar1_en) == 1'b1) begin + data_planar1_cur_cnt <= data_planar1_cur_cnt_w; + // VCS coverage off + end else if ((data_planar1_en) == 1'b0) begin + end else begin + data_planar1_cur_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///// assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar0_p1_cnt_w : data_planar0_p0_cnt_w; +///// assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar1_p1_cnt_w : data_planar1_p0_cnt_w; +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 2) { +//: print qq( +//: assign data_planar0_p1_flag_w = (is_first_running | rd_planar0_line_end) ? 3'b0 : data_planar0_p1_cur_flag; +//: assign data_planar1_p1_flag_w = (is_first_running | rd_planar1_line_end) ? 3'b0 : data_planar1_p1_cur_flag; +//: ); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"data_planar0_en\" -d \"data_planar0_p1_flag_w\" -q data_planar0_p1_flag"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"data_planar1_en\" -d \"data_planar1_p1_flag_w\" -q data_planar1_p1_flag"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: wire [1:0] data_planar0_p0_flag_nex; +//: wire [1:0] data_planar1_p0_flag_nex; +//: wire [13:0] data_planar0_cnt_sub; +//: wire mon_data_planar0_cnt_sub; +//: assign {mon_data_planar0_cnt_sub,data_planar0_cnt_sub[13:0]} = (data_planar0_p0_cnt_w - {8'd0,data_planar0_add}); +//: assign data_planar0_p0_flag_nex[0] = data_planar0_cnt_sub > data_width_mark_0; +//: assign data_planar0_p0_flag_nex[1] = data_planar0_cnt_sub > data_width_mark_1; +//: //assign data_planar0_p0_flag_nex[0] = (data_planar0_p0_cnt_w - data_planar0_add) > data_width_mark_0; +//: //assign data_planar0_p0_flag_nex[1] = (data_planar0_p0_cnt_w - data_planar0_add) > data_width_mark_1; +//: assign data_planar0_p0_lp_mask = ~data_planar0_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: ~data_planar0_p0_flag_nex[0] ? ~({${atmm}{1'b1}} << lp_planar0_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar0_p0_rp_mask = ~data_planar0_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: ~data_planar0_p0_flag_nex[1] ? ({${atmm}{1'b1}} << rp_planar0_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar0_p0_zero_mask = ~data_planar0_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar0_mask_sft); +//: assign data_planar0_p0_pad_mask = (data_planar0_p0_lp_mask | data_planar0_p0_rp_mask) & ~data_planar0_p0_zero_mask; +//: +//: wire [13:0] data_planar1_cnt_sub; +//: wire mon_data_planar1_cnt_sub; +//: assign {mon_data_planar1_cnt_sub,data_planar1_cnt_sub[13:0]} = (data_planar1_p0_cnt_w - {8'd0,data_planar1_add}); +//: assign data_planar1_p0_flag_nex[0] = data_planar1_cnt_sub > data_width_mark_0; +//: assign data_planar1_p0_flag_nex[1] = data_planar1_cnt_sub > data_width_mark_1; +//: //assign data_planar1_p0_flag_nex[0] = (data_planar1_p0_cnt_w - data_planar1_add) > data_width_mark_0; +//: //assign data_planar1_p0_flag_nex[1] = (data_planar1_p0_cnt_w - data_planar1_add) > data_width_mark_1; +//: +//: assign data_planar1_p0_lp_mask = ~data_planar1_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: ~data_planar1_p0_flag_nex[0] ? ~({${atmm}{1'b1}} << lp_planar1_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar1_p0_rp_mask = ~data_planar1_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: ~data_planar1_p0_flag_nex[1] ? ({${atmm}{1'b1}} << rp_planar1_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar1_p0_zero_mask = ~data_planar1_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar1_mask_sft); +//: assign data_planar1_p0_pad_mask = (data_planar1_p0_lp_mask | data_planar1_p0_rp_mask) & ~data_planar1_p0_zero_mask; +//: ); +//: } elsif ($atmm_num == 2) { +//: print qq( +//: assign data_planar0_p0_lp_mask = ~data_planar0_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar0_p1_flag[0] & data_planar0_p0_cur_flag[0]) ? ~({${atmm}{1'b1}} << lp_planar0_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar0_p0_rp_mask = ~data_planar0_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar0_p1_flag[1] & data_planar0_p0_cur_flag[1]) ? ({${atmm}{1'b1}} << rp_planar0_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar0_p0_zero_mask = ~data_planar0_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar0_mask_sft); +//: assign data_planar0_p0_pad_mask = (data_planar0_p0_lp_mask | data_planar0_p0_rp_mask) & ~data_planar0_p0_zero_mask; +//: +//: assign data_planar0_p1_lp_mask = ~data_planar0_p1_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar0_p0_cur_flag[0] & data_planar0_p1_cur_flag[0]) ? ~({${atmm}{1'b1}} << lp_planar0_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar0_p1_rp_mask = ~data_planar0_p1_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar0_p0_cur_flag[1] & data_planar0_p1_cur_flag[1]) ? ({${atmm}{1'b1}} << rp_planar0_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar0_p1_zero_mask = ~data_planar0_p1_cur_flag[2] ? {${atmm}{1'b0}} : +//: data_planar0_p0_cur_flag[2] ? {${atmm}{1'b1}} : ({${atmm}{1'b1}} << zero_planar0_mask_sft); +//: assign data_planar0_p1_pad_mask = (data_planar0_p1_lp_mask | data_planar0_p1_rp_mask) & ~data_planar0_p1_zero_mask; +//: +//: assign data_planar1_p0_lp_mask = ~data_planar1_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar1_p1_flag[0] ) ? ~({${atmm}{1'b1}} << lp_planar1_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar1_p0_rp_mask = ~data_planar1_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar1_p1_flag[1] ) ? ({${atmm}{1'b1}} << rp_planar1_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar1_p0_zero_mask = ~data_planar1_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar1_mask_sft); +//: assign data_planar1_p0_pad_mask = (data_planar1_p0_lp_mask | data_planar1_p0_rp_mask) & ~data_planar1_p0_zero_mask; +//: +//: assign data_planar1_p1_lp_mask = ~data_planar1_p1_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar1_p0_cur_flag[0] & data_planar1_p1_cur_flag[0]) ? ~({${atmm}{1'b1}} << lp_planar1_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar1_p1_rp_mask = ~data_planar1_p1_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar1_p0_cur_flag[1] & data_planar1_p1_cur_flag[1]) ? ({${atmm}{1'b1}} << rp_planar1_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar1_p1_zero_mask = ~data_planar1_p1_cur_flag[2] ? {${atmm}{1'b0}} : +//: data_planar1_p0_cur_flag[2] ? {${atmm}{1'b1}} : ({${atmm}{1'b1}} << zero_planar1_mask_sft); +//: assign data_planar1_p1_pad_mask = (data_planar1_p1_lp_mask | data_planar1_p1_rp_mask) & ~data_planar1_p1_zero_mask; +//: ); +//: } elsif ($atmm_num == 4) { +//: print qq( +//: ); +//: } +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: assign rd_p${i}_pad_mask = ~rd_planar_cnt ? data_planar0_p${i}_pad_mask : data_planar1_p${i}_pad_mask; +//: assign rd_p${i}_zero_mask = ~rd_planar_cnt ? data_planar0_p${i}_zero_mask : data_planar1_p${i}_zero_mask; +//: ); +//: &eperl::flop("-nodeclare -norst -en \"rd_vld\" -d \"rd_p${i}_pad_mask\" -q rd_p${i}_pad_mask_d1"); +//: &eperl::flop("-nodeclare -norst -en \"rd_vld\" -d \"rd_p${i}_zero_mask\" -q rd_p${i}_zero_mask_d1"); +//: print " //assign img2sbuf_p${i}_rd_en = rd_p${i}_vld_d1; \n"; +//: print " //assign img2sbuf_p${i}_rd_addr = rd_p${i}_addr_d1; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [1:0] data_planar0_p0_flag_nex; +wire [1:0] data_planar1_p0_flag_nex; +wire [13:0] data_planar0_cnt_sub; +wire mon_data_planar0_cnt_sub; +assign {mon_data_planar0_cnt_sub,data_planar0_cnt_sub[13:0]} = (data_planar0_p0_cnt_w - {8'd0,data_planar0_add}); +assign data_planar0_p0_flag_nex[0] = data_planar0_cnt_sub > data_width_mark_0; +assign data_planar0_p0_flag_nex[1] = data_planar0_cnt_sub > data_width_mark_1; +//assign data_planar0_p0_flag_nex[0] = (data_planar0_p0_cnt_w - data_planar0_add) > data_width_mark_0; +//assign data_planar0_p0_flag_nex[1] = (data_planar0_p0_cnt_w - data_planar0_add) > data_width_mark_1; +assign data_planar0_p0_lp_mask = ~data_planar0_p0_cur_flag[0] ? {8{1'b1}} : +~data_planar0_p0_flag_nex[0] ? ~({8{1'b1}} << lp_planar0_mask_sft) : {8{1'b0}}; +assign data_planar0_p0_rp_mask = ~data_planar0_p0_cur_flag[1] ? {8{1'b0}} : +~data_planar0_p0_flag_nex[1] ? ({8{1'b1}} << rp_planar0_mask_sft) : {8{1'b1}}; +assign data_planar0_p0_zero_mask = ~data_planar0_p0_cur_flag[2] ? {8{1'b0}} : ({8{1'b1}} << zero_planar0_mask_sft); +assign data_planar0_p0_pad_mask = (data_planar0_p0_lp_mask | data_planar0_p0_rp_mask) & ~data_planar0_p0_zero_mask; + +wire [13:0] data_planar1_cnt_sub; +wire mon_data_planar1_cnt_sub; +assign {mon_data_planar1_cnt_sub,data_planar1_cnt_sub[13:0]} = (data_planar1_p0_cnt_w - {8'd0,data_planar1_add}); +assign data_planar1_p0_flag_nex[0] = data_planar1_cnt_sub > data_width_mark_0; +assign data_planar1_p0_flag_nex[1] = data_planar1_cnt_sub > data_width_mark_1; +//assign data_planar1_p0_flag_nex[0] = (data_planar1_p0_cnt_w - data_planar1_add) > data_width_mark_0; +//assign data_planar1_p0_flag_nex[1] = (data_planar1_p0_cnt_w - data_planar1_add) > data_width_mark_1; + +assign data_planar1_p0_lp_mask = ~data_planar1_p0_cur_flag[0] ? {8{1'b1}} : +~data_planar1_p0_flag_nex[0] ? ~({8{1'b1}} << lp_planar1_mask_sft) : {8{1'b0}}; +assign data_planar1_p0_rp_mask = ~data_planar1_p0_cur_flag[1] ? {8{1'b0}} : +~data_planar1_p0_flag_nex[1] ? ({8{1'b1}} << rp_planar1_mask_sft) : {8{1'b1}}; +assign data_planar1_p0_zero_mask = ~data_planar1_p0_cur_flag[2] ? {8{1'b0}} : ({8{1'b1}} << zero_planar1_mask_sft); +assign data_planar1_p0_pad_mask = (data_planar1_p0_lp_mask | data_planar1_p0_rp_mask) & ~data_planar1_p0_zero_mask; + +assign rd_p0_pad_mask = ~rd_planar_cnt ? data_planar0_p0_pad_mask : data_planar1_p0_pad_mask; +assign rd_p0_zero_mask = ~rd_planar_cnt ? data_planar0_p0_zero_mask : data_planar1_p0_zero_mask; +always @(posedge nvdla_core_clk) begin + if ((rd_vld) == 1'b1) begin + rd_p0_pad_mask_d1 <= rd_p0_pad_mask; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_p0_pad_mask_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((rd_vld) == 1'b1) begin + rd_p0_zero_mask_d1 <= rd_p0_zero_mask; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_p0_zero_mask_d1 <= 'bx; + // VCS coverage on + end +end + //assign img2sbuf_p0_rd_en = rd_p0_vld_d1; + //assign img2sbuf_p0_rd_addr = rd_p0_addr_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign data_planar0_en = is_first_running | (rd_vld & ~rd_planar_cnt); +assign data_planar1_en = is_first_running | (rd_vld & rd_planar_cnt); +//assign data_planar0_ori_en = is_first_running; +//assign data_planar1_ori_en = is_first_running; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"rd_planar_cnt\" -q rd_planar_d1"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rd_vld\" -d \"rd_sub_h_cnt\" -q rd_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"rd_sub_h_end\" -q rd_sub_h_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"rd_loop_end\" -q rd_loop_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"(is_last_pburst & is_last_planar & is_last_loop & img_line_end)\" -q rd_one_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"is_1st_height\" -q rd_1st_height_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"img_layer_end & rd_height_end\" -q rd_layer_end_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_planar_d1 <= 1'b0; + end else begin + if ((rd_vld) == 1'b1) begin + rd_planar_d1 <= rd_planar_cnt; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_planar_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_h_d1 <= {3{1'b0}}; + end else begin + if ((rd_vld) == 1'b1) begin + rd_sub_h_d1 <= rd_sub_h_cnt; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_sub_h_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_h_end_d1 <= 1'b0; + end else begin + if ((rd_vld) == 1'b1) begin + rd_sub_h_end_d1 <= rd_sub_h_end; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_sub_h_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_loop_end_d1 <= 1'b0; + end else begin + if ((rd_vld) == 1'b1) begin + rd_loop_end_d1 <= rd_loop_end; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_loop_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_one_line_end_d1 <= 1'b0; + end else begin + if ((rd_vld) == 1'b1) begin + rd_one_line_end_d1 <= (is_last_pburst & is_last_planar & is_last_loop & img_line_end); + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_one_line_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_1st_height_d1 <= 1'b0; + end else begin + if ((rd_vld) == 1'b1) begin + rd_1st_height_d1 <= is_1st_height; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_1st_height_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_layer_end_d1 <= 1'b0; + end else begin + if ((rd_vld) == 1'b1) begin + rd_layer_end_d1 <= img_layer_end & rd_height_end; + // VCS coverage off + end else if ((rd_vld) == 1'b0) begin + end else begin + rd_layer_end_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// connect to shared buffer // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print " assign img2sbuf_p${i}_rd_en = rd_p${i}_vld_d1; \n"; +//: print " assign img2sbuf_p${i}_rd_addr = rd_p${i}_addr_d1; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign img2sbuf_p0_rd_en = rd_p0_vld_d1; + assign img2sbuf_p0_rd_addr = rd_p0_addr_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// pipeline register for shared buffer read latency // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: my $i; +//: my $j; +//: my $limit = 1 + 2; +//: for($i = 1; $i < $limit; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"rd_vld_d${i}\" -q rd_vld_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_planar_d${i}\" -q rd_planar_d${j}"); +//: &eperl::flop("-wid 3 -rval \"{3{1'b0}}\" -en \"rd_vld_d${i}\" -d \"rd_sub_h_d${i}\" -q rd_sub_h_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_sub_h_end_d${i}\" -q rd_sub_h_end_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_loop_end_d${i}\" -q rd_loop_end_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_one_line_end_d${i}\" -q rd_one_line_end_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_1st_height_d${i}\" -q rd_1st_height_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_layer_end_d${i}\" -q rd_layer_end_d${j}"); +//: foreach my $k (0..$atmm_num -1) { +//: &eperl::flop("-wid $atmm -norst -en \"rd_vld_d${i}\" -d \"rd_p${k}_pad_mask_d${i}\" -q rd_p${k}_pad_mask_d${j}"); +//: &eperl::flop("-wid $atmm -norst -en \"rd_vld_d${i}\" -d \"rd_p${k}_zero_mask_d${i}\" -q rd_p${k}_zero_mask_d${j}"); +//: } +//: } +//: +//: $i = $limit; +//: print qq ( +//: assign pk_rsp_vld = rd_vld_d${i}; +//: assign pk_rsp_planar = rd_planar_d${i}; +//: assign pk_rsp_sub_h = rd_sub_h_d${i}; +//: assign pk_rsp_sub_h_end = rd_sub_h_end_d${i}; +//: assign pk_rsp_loop_end = rd_loop_end_d${i}; +//: assign pk_rsp_one_line_end = rd_one_line_end_d${i}; +//: assign pk_rsp_1st_height = rd_1st_height_d${i}; +//: assign pk_rsp_layer_end = rd_layer_end_d${i}; +//: ); +//: foreach my $k (0..$atmm_num -1) { +//: print qq( +//: assign pk_rsp_p${k}_pad_mask = rd_p${k}_pad_mask_d${i}; +//: assign pk_rsp_p${k}_zero_mask = rd_p${k}_zero_mask_d${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg rd_vld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_vld_d2 <= 1'b0; + end else begin + rd_vld_d2 <= rd_vld_d1; + end +end +reg rd_planar_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_planar_d2 <= 1'b0; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_planar_d2 <= rd_planar_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_planar_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [2:0] rd_sub_h_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_h_d2 <= {3{1'b0}}; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_sub_h_d2 <= rd_sub_h_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_sub_h_d2 <= 'bx; + // VCS coverage on + end + end +end +reg rd_sub_h_end_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_h_end_d2 <= 1'b0; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_sub_h_end_d2 <= rd_sub_h_end_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_sub_h_end_d2 <= 'bx; + // VCS coverage on + end + end +end +reg rd_loop_end_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_loop_end_d2 <= 1'b0; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_loop_end_d2 <= rd_loop_end_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_loop_end_d2 <= 'bx; + // VCS coverage on + end + end +end +reg rd_one_line_end_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_one_line_end_d2 <= 1'b0; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_one_line_end_d2 <= rd_one_line_end_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_one_line_end_d2 <= 'bx; + // VCS coverage on + end + end +end +reg rd_1st_height_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_1st_height_d2 <= 1'b0; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_1st_height_d2 <= rd_1st_height_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_1st_height_d2 <= 'bx; + // VCS coverage on + end + end +end +reg rd_layer_end_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_layer_end_d2 <= 1'b0; + end else begin + if ((rd_vld_d1) == 1'b1) begin + rd_layer_end_d2 <= rd_layer_end_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_layer_end_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] rd_p0_pad_mask_d2; +always @(posedge nvdla_core_clk) begin + if ((rd_vld_d1) == 1'b1) begin + rd_p0_pad_mask_d2 <= rd_p0_pad_mask_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_p0_pad_mask_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] rd_p0_zero_mask_d2; +always @(posedge nvdla_core_clk) begin + if ((rd_vld_d1) == 1'b1) begin + rd_p0_zero_mask_d2 <= rd_p0_zero_mask_d1; + // VCS coverage off + end else if ((rd_vld_d1) == 1'b0) begin + end else begin + rd_p0_zero_mask_d2 <= 'bx; + // VCS coverage on + end +end +reg rd_vld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_vld_d3 <= 1'b0; + end else begin + rd_vld_d3 <= rd_vld_d2; + end +end +reg rd_planar_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_planar_d3 <= 1'b0; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_planar_d3 <= rd_planar_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_planar_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [2:0] rd_sub_h_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_h_d3 <= {3{1'b0}}; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_sub_h_d3 <= rd_sub_h_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_sub_h_d3 <= 'bx; + // VCS coverage on + end + end +end +reg rd_sub_h_end_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_h_end_d3 <= 1'b0; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_sub_h_end_d3 <= rd_sub_h_end_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_sub_h_end_d3 <= 'bx; + // VCS coverage on + end + end +end +reg rd_loop_end_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_loop_end_d3 <= 1'b0; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_loop_end_d3 <= rd_loop_end_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_loop_end_d3 <= 'bx; + // VCS coverage on + end + end +end +reg rd_one_line_end_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_one_line_end_d3 <= 1'b0; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_one_line_end_d3 <= rd_one_line_end_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_one_line_end_d3 <= 'bx; + // VCS coverage on + end + end +end +reg rd_1st_height_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_1st_height_d3 <= 1'b0; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_1st_height_d3 <= rd_1st_height_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_1st_height_d3 <= 'bx; + // VCS coverage on + end + end +end +reg rd_layer_end_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_layer_end_d3 <= 1'b0; + end else begin + if ((rd_vld_d2) == 1'b1) begin + rd_layer_end_d3 <= rd_layer_end_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_layer_end_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] rd_p0_pad_mask_d3; +always @(posedge nvdla_core_clk) begin + if ((rd_vld_d2) == 1'b1) begin + rd_p0_pad_mask_d3 <= rd_p0_pad_mask_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_p0_pad_mask_d3 <= 'bx; + // VCS coverage on + end +end +reg [7:0] rd_p0_zero_mask_d3; +always @(posedge nvdla_core_clk) begin + if ((rd_vld_d2) == 1'b1) begin + rd_p0_zero_mask_d3 <= rd_p0_zero_mask_d2; + // VCS coverage off + end else if ((rd_vld_d2) == 1'b0) begin + end else begin + rd_p0_zero_mask_d3 <= 'bx; + // VCS coverage on + end +end + +assign pk_rsp_vld = rd_vld_d3; +assign pk_rsp_planar = rd_planar_d3; +assign pk_rsp_sub_h = rd_sub_h_d3; +assign pk_rsp_sub_h_end = rd_sub_h_end_d3; +assign pk_rsp_loop_end = rd_loop_end_d3; +assign pk_rsp_one_line_end = rd_one_line_end_d3; +assign pk_rsp_1st_height = rd_1st_height_d3; +assign pk_rsp_layer_end = rd_layer_end_d3; + +assign pk_rsp_p0_pad_mask = rd_p0_pad_mask_d3; +assign pk_rsp_p0_zero_mask = rd_p0_zero_mask_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pk_rsp_early_end = pixel_early_end & pk_rsp_one_line_end; +assign pk_rsp_vld_d1_w = pk_rsp_vld & pixel_planar & ~(pk_rsp_early_end); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pk_rsp_vld_d1_w\" -q pk_rsp_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_sub_h\" -q pk_rsp_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_sub_h_end\" -q pk_rsp_sub_h_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_loop_end\" -q pk_rsp_loop_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_one_line_end\" -q pk_rsp_one_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_1st_height\" -q pk_rsp_1st_height_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_layer_end\" -q pk_rsp_layer_end_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_vld_d1 <= 1'b0; + end else begin + pk_rsp_vld_d1 <= pk_rsp_vld_d1_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_sub_h_d1 <= {3{1'b0}}; + end else begin + if ((pk_rsp_vld_d1_w) == 1'b1) begin + pk_rsp_sub_h_d1 <= pk_rsp_sub_h; + // VCS coverage off + end else if ((pk_rsp_vld_d1_w) == 1'b0) begin + end else begin + pk_rsp_sub_h_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_sub_h_end_d1 <= 1'b0; + end else begin + if ((pk_rsp_vld_d1_w) == 1'b1) begin + pk_rsp_sub_h_end_d1 <= pk_rsp_sub_h_end; + // VCS coverage off + end else if ((pk_rsp_vld_d1_w) == 1'b0) begin + end else begin + pk_rsp_sub_h_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_loop_end_d1 <= 1'b0; + end else begin + if ((pk_rsp_vld_d1_w) == 1'b1) begin + pk_rsp_loop_end_d1 <= pk_rsp_loop_end; + // VCS coverage off + end else if ((pk_rsp_vld_d1_w) == 1'b0) begin + end else begin + pk_rsp_loop_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_one_line_end_d1 <= 1'b0; + end else begin + if ((pk_rsp_vld_d1_w) == 1'b1) begin + pk_rsp_one_line_end_d1 <= pk_rsp_one_line_end; + // VCS coverage off + end else if ((pk_rsp_vld_d1_w) == 1'b0) begin + end else begin + pk_rsp_one_line_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_1st_height_d1 <= 1'b0; + end else begin + if ((pk_rsp_vld_d1_w) == 1'b1) begin + pk_rsp_1st_height_d1 <= pk_rsp_1st_height; + // VCS coverage off + end else if ((pk_rsp_vld_d1_w) == 1'b0) begin + end else begin + pk_rsp_1st_height_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_layer_end_d1 <= 1'b0; + end else begin + if ((pk_rsp_vld_d1_w) == 1'b1) begin + pk_rsp_layer_end_d1 <= pk_rsp_layer_end; + // VCS coverage off + end else if ((pk_rsp_vld_d1_w) == 1'b0) begin + end else begin + pk_rsp_layer_end_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// connect to sbuf ram input // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $k (0..$atmm_num -1) { +//: print qq( +//: assign pk_rsp_p${k}_data = img2sbuf_p${k}_rd_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pk_rsp_p0_data = img2sbuf_p0_rd_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// data write logic // +//////////////////////////////////////////////////////////////////////// +//////// control and status logic //////// +assign pk_rsp_pipe_sel = (~pixel_planar | (pk_rsp_vld & pk_rsp_early_end)); +assign pk_rsp_cur_vld = pk_rsp_pipe_sel ? pk_rsp_vld : pk_rsp_vld_d1; +assign pk_rsp_cur_sub_h = pk_rsp_pipe_sel ? pk_rsp_sub_h : pk_rsp_sub_h_d1; +assign pk_rsp_cur_sub_h_end = pk_rsp_pipe_sel ? pk_rsp_sub_h_end : pk_rsp_sub_h_end_d1; +assign pk_rsp_cur_loop_end = pk_rsp_pipe_sel ? pk_rsp_loop_end : pk_rsp_loop_end_d1; +assign pk_rsp_cur_one_line_end = pk_rsp_pipe_sel ? pk_rsp_one_line_end : pk_rsp_one_line_end_d1; +assign pk_rsp_cur_1st_height = pk_rsp_pipe_sel ? pk_rsp_1st_height : pk_rsp_1st_height_d1; +assign pk_rsp_cur_layer_end = pk_rsp_pipe_sel ? pk_rsp_layer_end : pk_rsp_layer_end_d1; +assign pk_rsp_wr_vld = pk_rsp_cur_vld; +assign {mon_pk_rsp_wr_cnt_w, + pk_rsp_wr_cnt_w} = (is_first_running | ~pk_rsp_planar) ? 3'b0 : pk_rsp_wr_cnt + 1'b1; +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"pk_rsp_vld\" -d \"pk_rsp_wr_cnt_w\" -q pk_rsp_wr_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_wr_cnt <= {2{1'b0}}; + end else begin + if ((pk_rsp_vld) == 1'b1) begin + pk_rsp_wr_cnt <= pk_rsp_wr_cnt_w; + // VCS coverage off + end else if ((pk_rsp_vld) == 1'b0) begin + end else begin + pk_rsp_wr_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign pk_rsp_wr_size_ori = pixel_packed_10b ? 3'h4 : 3'h2; +//assign pk_rsp_wr_mask = pixel_packed_10b ? 4'hf : 4'h3; +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: print qq( +//: assign pk_rsp_wr_size_ori = 3'h${atmm_num};//3'h2 +//: assign pk_rsp_wr_mask = {{(4-${atmm_num}){1'b0}},{${atmm_num}{1'b1}}};//4'h3; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pk_rsp_wr_size_ori = 3'h1;//3'h2 +assign pk_rsp_wr_mask = {{(4-1){1'b0}},{1{1'b1}}};//4'h3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////assign pk_rsp_wr_ext64 = (pk_rsp_cur_one_line_end & (pk_rsp_wr_sub_addr == 2'h2) & pixel_data_shrink & ~pixel_packed_10b); +////assign pk_rsp_wr_ext128 = (pk_rsp_cur_one_line_end & ~pk_rsp_wr_sub_addr[1] & (pixel_data_shrink | (~pixel_data_expand & ~pixel_packed_10b))); +////assign pk_out_interleave = 1'b0; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pk_rsp_wr_vld\" -q pk_out_vld"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_cur_sub_h\" -q pk_out_sub_h"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"pk_rsp_wr_mask\" -q pk_out_mask"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"is_first_running\" -d \"sg2pack_mn_enable\" -q pk_out_mean"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"is_first_running\" -d \"pixel_uint\" -q pk_out_uint"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_vld <= 1'b0; + end else begin + pk_out_vld <= pk_rsp_wr_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_sub_h <= {3{1'b0}}; + end else begin + if ((pk_rsp_wr_vld) == 1'b1) begin + pk_out_sub_h <= pk_rsp_cur_sub_h; + // VCS coverage off + end else if ((pk_rsp_wr_vld) == 1'b0) begin + end else begin + pk_out_sub_h <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_mask <= {4{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pk_out_mask <= pk_rsp_wr_mask; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pk_out_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_mean <= 1'b0; + end else begin + if ((is_first_running) == 1'b1) begin + pk_out_mean <= sg2pack_mn_enable; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pk_out_mean <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_uint <= 1'b0; + end else begin + if ((is_first_running) == 1'b1) begin + pk_out_uint <= pixel_uint; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pk_out_uint <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_ext64\" -q pk_out_ext64"); +////: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_ext128\" -q pk_out_ext128"); +// PKT_PACK_WIRE( nvdla_ram_info , pk_out_ , pk_out_info_pd ) +assign pk_out_info_pd[3:0] = pk_out_mask[3:0]; +assign pk_out_info_pd[4] = 1'b0;//pk_out_interleave ; +assign pk_out_info_pd[5] = 1'b0;//pk_out_ext64 ; +assign pk_out_info_pd[6] = 1'b0;//pk_out_ext128 ; +assign pk_out_info_pd[7] = pk_out_mean ; +assign pk_out_info_pd[8] = pk_out_uint ; +assign pk_out_info_pd[11:9] = pk_out_sub_h[2:0]; +//////////////////////////////////////////////////////////////////////// +// data output logic // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign rdat = pk_rsp_p0_data; +//: assign mask_zero = {pk_rsp_p0_zero_mask}; +//: assign mask_pad = {pk_rsp_p0_pad_mask}; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rdat = {pk_rsp_p1_data, pk_rsp_p0_data}; +//: assign mask_zero = {pk_rsp_p1_zero_mask, pk_rsp_p0_zero_mask}; +//: assign mask_pad = {pk_rsp_p1_pad_mask, pk_rsp_p0_pad_mask}; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rdat = {pk_rsp_p3_data, pk_rsp_p2_data, pk_rsp_p1_data, pk_rsp_p0_data}; +//: assign mask_zero = {pk_rsp_p3_zero_mask, pk_rsp_p2_zero_mask, pk_rsp_p1_zero_mask, pk_rsp_p0_zero_mask}; +//: assign mask_pad = {pk_rsp_p3_pad_mask, pk_rsp_p2_pad_mask, pk_rsp_p1_pad_mask, pk_rsp_p0_pad_mask}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign rdat = pk_rsp_p0_data; +assign mask_zero = {pk_rsp_p0_zero_mask}; +assign mask_pad = {pk_rsp_p0_pad_mask}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign z14 = 14'b0; +//assign z6 = 6'b0; +assign pk_rsp_dat_normal = rdat; +////assign pk_rsp_dat_ergb = {rdat[15*32+31:15*32+30], z14, rdat[15*32+29:15*32+20], z6, rdat[15*32+19:15*32+10], z6,rdat[15*32+9:15*32], z6, +//// rdat[14*32+31:14*32+30], z14, rdat[14*32+29:14*32+20], z6, rdat[14*32+19:14*32+10], z6,rdat[14*32+9:14*32], z6, +//// rdat[13*32+31:13*32+30], z14, rdat[13*32+29:13*32+20], z6, rdat[13*32+19:13*32+10], z6,rdat[13*32+9:13*32], z6, +//// rdat[12*32+31:12*32+30], z14, rdat[12*32+29:12*32+20], z6, rdat[12*32+19:12*32+10], z6,rdat[12*32+9:12*32], z6, +//// rdat[11*32+31:11*32+30], z14, rdat[11*32+29:11*32+20], z6, rdat[11*32+19:11*32+10], z6,rdat[11*32+9:11*32], z6, +//// rdat[10*32+31:10*32+30], z14, rdat[10*32+29:10*32+20], z6, rdat[10*32+19:10*32+10], z6,rdat[10*32+9:10*32], z6, +//// rdat[9*32+31:9*32+30], z14, rdat[9*32+29:9*32+20], z6, rdat[9*32+19:9*32+10], z6,rdat[9*32+9:9*32], z6, +//// rdat[8*32+31:8*32+30], z14, rdat[8*32+29:8*32+20], z6, rdat[8*32+19:8*32+10], z6,rdat[8*32+9:8*32], z6, +//// rdat[7*32+31:7*32+30], z14, rdat[7*32+29:7*32+20], z6, rdat[7*32+19:7*32+10], z6,rdat[7*32+9:7*32], z6, +//// rdat[6*32+31:6*32+30], z14, rdat[6*32+29:6*32+20], z6, rdat[6*32+19:6*32+10], z6,rdat[6*32+9:6*32], z6, +//// rdat[5*32+31:5*32+30], z14, rdat[5*32+29:5*32+20], z6, rdat[5*32+19:5*32+10], z6,rdat[5*32+9:5*32], z6, +//// rdat[4*32+31:4*32+30], z14, rdat[4*32+29:4*32+20], z6, rdat[4*32+19:4*32+10], z6,rdat[4*32+9:4*32], z6, +//// rdat[3*32+31:3*32+30], z14, rdat[3*32+29:3*32+20], z6, rdat[3*32+19:3*32+10], z6,rdat[3*32+9:3*32], z6, +//// rdat[2*32+31:2*32+30], z14, rdat[2*32+29:2*32+20], z6, rdat[2*32+19:2*32+10], z6,rdat[2*32+9:2*32], z6, +//// rdat[1*32+31:1*32+30], z14, rdat[1*32+29:1*32+20], z6, rdat[1*32+19:1*32+10], z6,rdat[1*32+9:1*32], z6, +//// rdat[0*32+31:0*32+30], z14, rdat[0*32+29:0*32+20], z6, rdat[0*32+19:0*32+10], z6,rdat[0*32+9:0*32], z6}; +/////: for(my $i = 0; $i < 16; $i ++) { +/////: my $b0 = sprintf("%3d", ($i * 64)); +/////: my $b1 = sprintf("%3d", ($i * 64 + 63)); +/////: my $b2 = $i * 4; +/////: print "assign pk_rsp_dat_mergb[${b1}:${b0}] = (~pixel_packed_10b | mask_zero[${b2}] | mask_pad[${b2}]) ? 64'b0 : pk_rsp_dat_ergb[${b1}:${b0}];\n"; +/////: } +/////: print "\n\n\n"; +/////: +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $ele_num = int($dmaif/$bpe); +//: for(my $i = 0; $i < $ele_num; $i ++) { +//: my $b0 = sprintf("%3d", ($i * $bpe)); +//: my $b1 = sprintf("%3d", ($i * $bpe + $bpe -1)); +//: print qq( assign pk_rsp_dat_mnorm[${b1}:${b0}] = (pixel_packed_10b | mask_zero[${i}] | mask_pad[${i}]) ? ${bpe}'b0 : pk_rsp_dat_normal[${b1}:${b0}]; \n); +//: } +//: print "\n\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign pk_rsp_dat_mnorm[ 7: 0] = (pixel_packed_10b | mask_zero[0] | mask_pad[0]) ? 8'b0 : pk_rsp_dat_normal[ 7: 0]; + assign pk_rsp_dat_mnorm[ 15: 8] = (pixel_packed_10b | mask_zero[1] | mask_pad[1]) ? 8'b0 : pk_rsp_dat_normal[ 15: 8]; + assign pk_rsp_dat_mnorm[ 23: 16] = (pixel_packed_10b | mask_zero[2] | mask_pad[2]) ? 8'b0 : pk_rsp_dat_normal[ 23: 16]; + assign pk_rsp_dat_mnorm[ 31: 24] = (pixel_packed_10b | mask_zero[3] | mask_pad[3]) ? 8'b0 : pk_rsp_dat_normal[ 31: 24]; + assign pk_rsp_dat_mnorm[ 39: 32] = (pixel_packed_10b | mask_zero[4] | mask_pad[4]) ? 8'b0 : pk_rsp_dat_normal[ 39: 32]; + assign pk_rsp_dat_mnorm[ 47: 40] = (pixel_packed_10b | mask_zero[5] | mask_pad[5]) ? 8'b0 : pk_rsp_dat_normal[ 47: 40]; + assign pk_rsp_dat_mnorm[ 55: 48] = (pixel_packed_10b | mask_zero[6] | mask_pad[6]) ? 8'b0 : pk_rsp_dat_normal[ 55: 48]; + assign pk_rsp_dat_mnorm[ 63: 56] = (pixel_packed_10b | mask_zero[7] | mask_pad[7]) ? 8'b0 : pk_rsp_dat_normal[ 63: 56]; + + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_l0 = pk_rsp_planar0_c0_d1; +assign dat_l1_lo = pk_rsp_planar1_c0_en ? pk_rsp_dat_mnorm : pk_rsp_planar1_c0_d1; +assign dat_l1_hi = pk_rsp_planar1_c1_en ? pk_rsp_dat_mnorm : pk_rsp_planar1_c1_d1; +assign dat_l1 = {dat_l1_hi, dat_l1_lo}; +assign dat_8b_yuv = { +//: my $bpe = 8; +//: my $dmaif = 64; +//: my $m = ($dmaif/$bpe); +//: foreach my $i(0..$m -2) { +//: my $k = $m -$i -1; +//: print " dat_l1[${k}*2*${bpe}+2*${bpe}-1:${k}*2*${bpe}], dat_l0[${k}*${bpe}+${bpe}-1:${k}*${bpe}], \n"; +//: } +//: print " dat_l1[2*${bpe}-1:0], dat_l0[${bpe}-1:0]}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + dat_l1[7*2*8+2*8-1:7*2*8], dat_l0[7*8+8-1:7*8], + dat_l1[6*2*8+2*8-1:6*2*8], dat_l0[6*8+8-1:6*8], + dat_l1[5*2*8+2*8-1:5*2*8], dat_l0[5*8+8-1:5*8], + dat_l1[4*2*8+2*8-1:4*2*8], dat_l0[4*8+8-1:4*8], + dat_l1[3*2*8+2*8-1:3*2*8], dat_l0[3*8+8-1:3*8], + dat_l1[2*2*8+2*8-1:2*2*8], dat_l0[2*8+8-1:2*8], + dat_l1[1*2*8+2*8-1:1*2*8], dat_l0[1*8+8-1:1*8], + dat_l1[2*8-1:0], dat_l0[8-1:0]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_yuv = dat_8b_yuv; +assign pk_rsp_out_sel[0] = (pixel_packed_10b); +assign pk_rsp_out_sel[1] = (~pixel_planar & ~pixel_packed_10b); +assign pk_rsp_out_sel[2] = (pixel_planar & (pk_rsp_wr_cnt == 2'h0)); +assign pk_rsp_out_sel[3] = (pixel_planar & (pk_rsp_wr_cnt == 2'h1)); +assign pk_rsp_out_sel[4] = (pixel_planar & (pk_rsp_wr_cnt == 2'h2)); +//assign pk_rsp_data_h1 = pk_rsp_dat_mergb[1023:512]; +assign pk_rsp_data_h0 = //({256*2{pk_rsp_out_sel[0]}} & pk_rsp_dat_mergb[511:0]) | + ({64{pk_rsp_out_sel[1]}} & pk_rsp_dat_mnorm) | + ({64{pk_rsp_out_sel[2]}} & dat_yuv[64 -1:0]) | + ({64{pk_rsp_out_sel[3]}} & dat_yuv[64*2-1:64]) | + ({64{pk_rsp_out_sel[4]}} & dat_yuv[64*3-1:64*2]); +assign pk_rsp_pad_mask_norm = mask_pad; +//assign pk_rsp_pad_mask_ergb = {{2{mask_pad[63]}}, {2{mask_pad[62]}}, {2{mask_pad[61]}}, {2{mask_pad[60]}}, {2{mask_pad[59]}}, {2{mask_pad[58]}}, {2{mask_pad[57]}}, {2{mask_pad[56]}}, {2{mask_pad[55]}}, {2{mask_pad[54]}}, {2{mask_pad[53]}}, {2{mask_pad[52]}}, {2{mask_pad[51]}}, {2{mask_pad[50]}}, {2{mask_pad[49]}}, {2{mask_pad[48]}}, {2{mask_pad[47]}}, {2{mask_pad[46]}}, {2{mask_pad[45]}}, {2{mask_pad[44]}}, {2{mask_pad[43]}}, {2{mask_pad[42]}}, {2{mask_pad[41]}}, {2{mask_pad[40]}}, {2{mask_pad[39]}}, {2{mask_pad[38]}}, {2{mask_pad[37]}}, {2{mask_pad[36]}}, {2{mask_pad[35]}}, {2{mask_pad[34]}}, {2{mask_pad[33]}}, {2{mask_pad[32]}}, {2{mask_pad[31]}}, {2{mask_pad[30]}}, {2{mask_pad[29]}}, {2{mask_pad[28]}}, {2{mask_pad[27]}}, {2{mask_pad[26]}}, {2{mask_pad[25]}}, {2{mask_pad[24]}}, {2{mask_pad[23]}}, {2{mask_pad[22]}}, {2{mask_pad[21]}}, {2{mask_pad[20]}}, {2{mask_pad[19]}}, {2{mask_pad[18]}}, {2{mask_pad[17]}}, {2{mask_pad[16]}}, {2{mask_pad[15]}}, {2{mask_pad[14]}}, {2{mask_pad[13]}}, {2{mask_pad[12]}}, {2{mask_pad[11]}}, {2{mask_pad[10]}}, {2{mask_pad[9]}}, {2{mask_pad[8]}}, {2{mask_pad[7]}}, {2{mask_pad[6]}}, {2{mask_pad[5]}}, {2{mask_pad[4]}}, {2{mask_pad[3]}}, {2{mask_pad[2]}}, {2{mask_pad[1]}}, {2{mask_pad[0]}}}; +assign pad_mask_l0 = mask_pad_planar0_c0_d1; +assign pad_mask_l1_lo = pk_rsp_planar1_c0_en ? mask_pad : mask_pad_planar1_c0_d1; +assign pad_mask_l1_hi = pk_rsp_planar1_c1_en ? mask_pad : mask_pad_planar1_c1_d1; +assign pad_mask_l1 = {pad_mask_l1_hi, pad_mask_l1_lo}; +assign pad_mask_8b_yuv = { +//: my $bpe = 8; +//: my $dmaif = 64; +//: my $m = ($dmaif/$bpe); +//: my $byte = 8/8; +//: foreach my $i(0..$m -2) { +//: my $k = $m -$i -1; +//: print " {pad_mask_l1[${k}*2*${byte}+2*${byte}-1:${k}*2*${byte}], pad_mask_l0[${k}*${byte}+${byte}-1:${k}*${byte}]}, \n"; +//: } +//: print " {pad_mask_l1[2*${byte}-1:0], pad_mask_l0[${byte}-1:0]}}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {pad_mask_l1[7*2*1+2*1-1:7*2*1], pad_mask_l0[7*1+1-1:7*1]}, + {pad_mask_l1[6*2*1+2*1-1:6*2*1], pad_mask_l0[6*1+1-1:6*1]}, + {pad_mask_l1[5*2*1+2*1-1:5*2*1], pad_mask_l0[5*1+1-1:5*1]}, + {pad_mask_l1[4*2*1+2*1-1:4*2*1], pad_mask_l0[4*1+1-1:4*1]}, + {pad_mask_l1[3*2*1+2*1-1:3*2*1], pad_mask_l0[3*1+1-1:3*1]}, + {pad_mask_l1[2*2*1+2*1-1:2*2*1], pad_mask_l0[2*1+1-1:2*1]}, + {pad_mask_l1[1*2*1+2*1-1:1*2*1], pad_mask_l0[1*1+1-1:1*1]}, + {pad_mask_l1[2*1-1:0], pad_mask_l0[1-1:0]}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pad_mask_yuv = pad_mask_8b_yuv; +//assign pk_rsp_pad_mask_h1 = pixel_packed_10b ? pk_rsp_pad_mask_ergb[127:64] : 64'b0; +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $ele_num = int( $dmaif/$bpe ); +//: print qq( +//: assign pk_rsp_pad_mask_h0 = //({64{pk_rsp_out_sel[0]}} & pk_rsp_pad_mask_ergb[63:0]) | +//: ({${ele_num}{pk_rsp_out_sel[1]}} & pk_rsp_pad_mask_norm) | +//: ({${ele_num}{pk_rsp_out_sel[2]}} & pad_mask_yuv[${ele_num}-1:0]) | +//: ({${ele_num}{pk_rsp_out_sel[3]}} & pad_mask_yuv[${ele_num}*2-1:${ele_num}]) | +//: ({${ele_num}{pk_rsp_out_sel[4]}} & pad_mask_yuv[${ele_num}*3-1:${ele_num}*2]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pk_rsp_pad_mask_h0 = //({64{pk_rsp_out_sel[0]}} & pk_rsp_pad_mask_ergb[63:0]) | +({8{pk_rsp_out_sel[1]}} & pk_rsp_pad_mask_norm) | +({8{pk_rsp_out_sel[2]}} & pad_mask_yuv[8-1:0]) | +({8{pk_rsp_out_sel[3]}} & pad_mask_yuv[8*2-1:8]) | +({8{pk_rsp_out_sel[4]}} & pad_mask_yuv[8*3-1:8*2]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pk_rsp_planar0_c0_en = (pk_rsp_vld & pixel_planar & ~pk_rsp_planar); +assign pk_rsp_planar1_c0_en = (pk_rsp_vld & pixel_planar & pk_rsp_planar & (pk_rsp_wr_cnt == 2'h0)); +assign pk_rsp_planar1_c1_en = (pk_rsp_vld & pixel_planar & pk_rsp_planar & (pk_rsp_wr_cnt == 2'h1)); +assign pk_rsp_data_h0_en = pk_rsp_wr_vld; +//assign pk_rsp_data_h1_en = pk_rsp_wr_vld & pixel_packed_10b; +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $ele_num = int($dmaif/$bpe); +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"pk_rsp_planar0_c0_en\" -d \"pk_rsp_dat_mnorm\" -q pk_rsp_planar0_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"pk_rsp_planar1_c0_en\" -d \"pk_rsp_dat_mnorm\" -q pk_rsp_planar1_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"pk_rsp_planar1_c1_en\" -d \"pk_rsp_dat_mnorm\" -q pk_rsp_planar1_c1_d1"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_planar0_c0_en\" -d \"mask_pad\" -q mask_pad_planar0_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_planar1_c0_en\" -d \"mask_pad\" -q mask_pad_planar1_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_planar1_c1_en\" -d \"mask_pad\" -q mask_pad_planar1_c1_d1"); +//: &eperl::flop("-nodeclare -norst -en \"pk_rsp_data_h0_en\" -d \"pk_rsp_data_h0\" -q pk_out_data_h0"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_data_h0_en\" -d \"pk_rsp_pad_mask_h0\" -q pk_out_pad_mask_h0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_planar0_c0_d1 <= {64{1'b0}}; + end else begin + if ((pk_rsp_planar0_c0_en) == 1'b1) begin + pk_rsp_planar0_c0_d1 <= pk_rsp_dat_mnorm; + // VCS coverage off + end else if ((pk_rsp_planar0_c0_en) == 1'b0) begin + end else begin + pk_rsp_planar0_c0_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_planar1_c0_d1 <= {64{1'b0}}; + end else begin + if ((pk_rsp_planar1_c0_en) == 1'b1) begin + pk_rsp_planar1_c0_d1 <= pk_rsp_dat_mnorm; + // VCS coverage off + end else if ((pk_rsp_planar1_c0_en) == 1'b0) begin + end else begin + pk_rsp_planar1_c0_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_planar1_c1_d1 <= {64{1'b0}}; + end else begin + if ((pk_rsp_planar1_c1_en) == 1'b1) begin + pk_rsp_planar1_c1_d1 <= pk_rsp_dat_mnorm; + // VCS coverage off + end else if ((pk_rsp_planar1_c1_en) == 1'b0) begin + end else begin + pk_rsp_planar1_c1_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mask_pad_planar0_c0_d1 <= {8{1'b0}}; + end else begin + if ((pk_rsp_planar0_c0_en) == 1'b1) begin + mask_pad_planar0_c0_d1 <= mask_pad; + // VCS coverage off + end else if ((pk_rsp_planar0_c0_en) == 1'b0) begin + end else begin + mask_pad_planar0_c0_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mask_pad_planar1_c0_d1 <= {8{1'b0}}; + end else begin + if ((pk_rsp_planar1_c0_en) == 1'b1) begin + mask_pad_planar1_c0_d1 <= mask_pad; + // VCS coverage off + end else if ((pk_rsp_planar1_c0_en) == 1'b0) begin + end else begin + mask_pad_planar1_c0_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mask_pad_planar1_c1_d1 <= {8{1'b0}}; + end else begin + if ((pk_rsp_planar1_c1_en) == 1'b1) begin + mask_pad_planar1_c1_d1 <= mask_pad; + // VCS coverage off + end else if ((pk_rsp_planar1_c1_en) == 1'b0) begin + end else begin + mask_pad_planar1_c1_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((pk_rsp_data_h0_en) == 1'b1) begin + pk_out_data_h0 <= pk_rsp_data_h0; + // VCS coverage off + end else if ((pk_rsp_data_h0_en) == 1'b0) begin + end else begin + pk_out_data_h0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_pad_mask_h0 <= {8{1'b0}}; + end else begin + if ((pk_rsp_data_h0_en) == 1'b1) begin + pk_out_pad_mask_h0 <= pk_rsp_pad_mask_h0; + // VCS coverage off + end else if ((pk_rsp_data_h0_en) == 1'b0) begin + end else begin + pk_out_pad_mask_h0 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// //: &eperl::flop("-nodeclare -norst -en \"pk_rsp_data_h1_en\" -d \"pk_rsp_data_h1\" -q pk_out_data_h1"); +// //: &eperl::flop("-nodeclare -rval \"{64{1'b0}}\" -en \"pk_rsp_data_h1_en | is_first_running\" -d \"pk_rsp_pad_mask_h1\" -q pk_out_pad_mask_h1"); +//assign pk_out_data = {pk_out_data_h1, pk_out_data_h0}; +assign pk_out_data = pk_out_data_h0; +//assign pk_out_pad_mask = {pk_out_pad_mask_h1, pk_out_pad_mask_h0}; +assign pk_out_pad_mask = pk_out_pad_mask_h0; +//////////////////////////////////////////////////////////////////////// +// mean data replacement and output logic // +//////////////////////////////////////////////////////////////////////// +assign mn_mask_y = mn_mask_y_d1; +assign mn_mask_uv_lo = mn_mask_uv_0_en ? mask_zero : mn_mask_uv_lo_d1; +assign mn_mask_uv_hi = mn_mask_uv_1_en ? mask_zero : mn_mask_uv_hi_d1; +assign mn_mask_uv = {mn_mask_uv_hi, mn_mask_uv_lo}; +assign mn_mask_yuv = { +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm-2) { +//: my $k = $atmm - $i -1; +//: print qq( +//: mn_mask_uv[${k}*2*${atmm_num}+2*${atmm_num}-1:${k}*2*${atmm_num}], mn_mask_y[${k}*${atmm_num}+${atmm_num}-1:${k}*${atmm_num}], +//: ); +//: } +//: print " mn_mask_uv[2*${atmm_num}-1:0], mn_mask_y[${atmm_num}-1:0]}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +mn_mask_uv[7*2*1+2*1-1:7*2*1], mn_mask_y[7*1+1-1:7*1], + +mn_mask_uv[6*2*1+2*1-1:6*2*1], mn_mask_y[6*1+1-1:6*1], + +mn_mask_uv[5*2*1+2*1-1:5*2*1], mn_mask_y[5*1+1-1:5*1], + +mn_mask_uv[4*2*1+2*1-1:4*2*1], mn_mask_y[4*1+1-1:4*1], + +mn_mask_uv[3*2*1+2*1-1:3*2*1], mn_mask_y[3*1+1-1:3*1], + +mn_mask_uv[2*2*1+2*1-1:2*2*1], mn_mask_y[2*1+1-1:2*1], + +mn_mask_uv[1*2*1+2*1-1:1*2*1], mn_mask_y[1*1+1-1:1*1], + mn_mask_uv[2*1-1:0], mn_mask_y[1-1:0]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign mn_ch1 = {64{reg2dp_mean_ry}}; +//assign mn_ch4 = {16{reg2dp_mean_ax, reg2dp_mean_bv, reg2dp_mean_gu, reg2dp_mean_ry}}; +//assign mn_ch3 = {64{reg2dp_mean_bv, reg2dp_mean_gu, reg2dp_mean_ry}}; +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $bpe3 = (8*3); +//: my $Bnum = int($dmaif/$bpe); +//: print qq( +//: assign mn_ch1 = {${Bnum}{reg2dp_mean_ry[15:0]}}; +//: assign mn_ch4 = {(${Bnum}/4){reg2dp_mean_ax[15:0], reg2dp_mean_bv[15:0], reg2dp_mean_gu[15:0], reg2dp_mean_ry[15:0]}}; +//: assign mn_ch3 = {${Bnum}{reg2dp_mean_bv[15:0], reg2dp_mean_gu[15:0], reg2dp_mean_ry[15:0]}}; +//: assign mn_ch1_4 = ~(|reg2dp_datain_channel) ? mn_ch1 : mn_ch4; +//: ); +//: for(my $i = 0; $i < $Bnum; $i ++) { +//: print "assign mn_8b_mnorm[${i}*16+15:${i}*16] = mask_zero[${i}] ? 16'b0 : mn_ch1_4[${i}*16+15:${i}*16];\n"; +//: ## print "assign mn_8b_myuv[${i}*48+47:${i}*48] = mn_mask_yuv[${i}] ? 48'b0 : mn_ch3[${i}*48+47:${i}*48];\n"; +//: } +//: my $Bnum_3 = int( $Bnum * 3 ); +//: for(my $i = 0; $i < $Bnum_3; $i ++) { +//: print "assign mn_8b_myuv[${i}*16+15:${i}*16] = mn_mask_yuv[${i}] ? 16'b0 : mn_ch3[${i}*16+15:${i}*16];\n"; +//: } +//: print "\n\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign mn_ch1 = {8{reg2dp_mean_ry[15:0]}}; +assign mn_ch4 = {(8/4){reg2dp_mean_ax[15:0], reg2dp_mean_bv[15:0], reg2dp_mean_gu[15:0], reg2dp_mean_ry[15:0]}}; +assign mn_ch3 = {8{reg2dp_mean_bv[15:0], reg2dp_mean_gu[15:0], reg2dp_mean_ry[15:0]}}; +assign mn_ch1_4 = ~(|reg2dp_datain_channel) ? mn_ch1 : mn_ch4; +assign mn_8b_mnorm[0*16+15:0*16] = mask_zero[0] ? 16'b0 : mn_ch1_4[0*16+15:0*16]; +assign mn_8b_mnorm[1*16+15:1*16] = mask_zero[1] ? 16'b0 : mn_ch1_4[1*16+15:1*16]; +assign mn_8b_mnorm[2*16+15:2*16] = mask_zero[2] ? 16'b0 : mn_ch1_4[2*16+15:2*16]; +assign mn_8b_mnorm[3*16+15:3*16] = mask_zero[3] ? 16'b0 : mn_ch1_4[3*16+15:3*16]; +assign mn_8b_mnorm[4*16+15:4*16] = mask_zero[4] ? 16'b0 : mn_ch1_4[4*16+15:4*16]; +assign mn_8b_mnorm[5*16+15:5*16] = mask_zero[5] ? 16'b0 : mn_ch1_4[5*16+15:5*16]; +assign mn_8b_mnorm[6*16+15:6*16] = mask_zero[6] ? 16'b0 : mn_ch1_4[6*16+15:6*16]; +assign mn_8b_mnorm[7*16+15:7*16] = mask_zero[7] ? 16'b0 : mn_ch1_4[7*16+15:7*16]; +assign mn_8b_myuv[0*16+15:0*16] = mn_mask_yuv[0] ? 16'b0 : mn_ch3[0*16+15:0*16]; +assign mn_8b_myuv[1*16+15:1*16] = mn_mask_yuv[1] ? 16'b0 : mn_ch3[1*16+15:1*16]; +assign mn_8b_myuv[2*16+15:2*16] = mn_mask_yuv[2] ? 16'b0 : mn_ch3[2*16+15:2*16]; +assign mn_8b_myuv[3*16+15:3*16] = mn_mask_yuv[3] ? 16'b0 : mn_ch3[3*16+15:3*16]; +assign mn_8b_myuv[4*16+15:4*16] = mn_mask_yuv[4] ? 16'b0 : mn_ch3[4*16+15:4*16]; +assign mn_8b_myuv[5*16+15:5*16] = mn_mask_yuv[5] ? 16'b0 : mn_ch3[5*16+15:5*16]; +assign mn_8b_myuv[6*16+15:6*16] = mn_mask_yuv[6] ? 16'b0 : mn_ch3[6*16+15:6*16]; +assign mn_8b_myuv[7*16+15:7*16] = mn_mask_yuv[7] ? 16'b0 : mn_ch3[7*16+15:7*16]; +assign mn_8b_myuv[8*16+15:8*16] = mn_mask_yuv[8] ? 16'b0 : mn_ch3[8*16+15:8*16]; +assign mn_8b_myuv[9*16+15:9*16] = mn_mask_yuv[9] ? 16'b0 : mn_ch3[9*16+15:9*16]; +assign mn_8b_myuv[10*16+15:10*16] = mn_mask_yuv[10] ? 16'b0 : mn_ch3[10*16+15:10*16]; +assign mn_8b_myuv[11*16+15:11*16] = mn_mask_yuv[11] ? 16'b0 : mn_ch3[11*16+15:11*16]; +assign mn_8b_myuv[12*16+15:12*16] = mn_mask_yuv[12] ? 16'b0 : mn_ch3[12*16+15:12*16]; +assign mn_8b_myuv[13*16+15:13*16] = mn_mask_yuv[13] ? 16'b0 : mn_ch3[13*16+15:13*16]; +assign mn_8b_myuv[14*16+15:14*16] = mn_mask_yuv[14] ? 16'b0 : mn_ch3[14*16+15:14*16]; +assign mn_8b_myuv[15*16+15:15*16] = mn_mask_yuv[15] ? 16'b0 : mn_ch3[15*16+15:15*16]; +assign mn_8b_myuv[16*16+15:16*16] = mn_mask_yuv[16] ? 16'b0 : mn_ch3[16*16+15:16*16]; +assign mn_8b_myuv[17*16+15:17*16] = mn_mask_yuv[17] ? 16'b0 : mn_ch3[17*16+15:17*16]; +assign mn_8b_myuv[18*16+15:18*16] = mn_mask_yuv[18] ? 16'b0 : mn_ch3[18*16+15:18*16]; +assign mn_8b_myuv[19*16+15:19*16] = mn_mask_yuv[19] ? 16'b0 : mn_ch3[19*16+15:19*16]; +assign mn_8b_myuv[20*16+15:20*16] = mn_mask_yuv[20] ? 16'b0 : mn_ch3[20*16+15:20*16]; +assign mn_8b_myuv[21*16+15:21*16] = mn_mask_yuv[21] ? 16'b0 : mn_ch3[21*16+15:21*16]; +assign mn_8b_myuv[22*16+15:22*16] = mn_mask_yuv[22] ? 16'b0 : mn_ch3[22*16+15:22*16]; +assign mn_8b_myuv[23*16+15:23*16] = mn_mask_yuv[23] ? 16'b0 : mn_ch3[23*16+15:23*16]; + + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pk_rsp_mn_sel[0] = ~pixel_planar & (pixel_packed_10b | ~(|pixel_precision)); +assign pk_rsp_mn_sel[1] = ~pixel_planar & ~pixel_packed_10b & (|pixel_precision); +assign pk_rsp_mn_sel[2] = pixel_planar & (pk_rsp_wr_cnt == 2'h0) & ~(|pixel_precision); +assign pk_rsp_mn_sel[3] = pixel_planar & (pk_rsp_wr_cnt == 2'h0) & (|pixel_precision); +assign pk_rsp_mn_sel[4] = pixel_planar & (pk_rsp_wr_cnt == 2'h1) & ~(|pixel_precision); +assign pk_rsp_mn_sel[5] = pixel_planar & (pk_rsp_wr_cnt == 2'h1) & (|pixel_precision); +assign pk_rsp_mn_sel[6] = pixel_planar & (pk_rsp_wr_cnt == 2'h2) & ~(|pixel_precision); +assign pk_rsp_mn_sel[7] = pixel_planar & (pk_rsp_wr_cnt == 2'h2) & (|pixel_precision); +//assign pk_rsp_mn_data_h1 = ({256 *2{pk_rsp_mn_sel[0]}} & mn_8b_mnorm[1023:512]) | +// ({256 *2{pk_rsp_mn_sel[2]}} & mn_8b_myuv[1023:512]) | +// ({256 *2{pk_rsp_mn_sel[4]}} & mn_8b_myuv[2047:1536]) | +// ({256 *2{pk_rsp_mn_sel[6]}} & mn_8b_myuv[3071:2560]); +// +//: my $mn_bw = int(64 / 8) * 16 ; +//: print qq( +//: assign pk_rsp_mn_data_h0 = ({${mn_bw}{pk_rsp_mn_sel[0]}} & mn_8b_mnorm) | +//: ({${mn_bw}{pk_rsp_mn_sel[2]}} & mn_8b_myuv[${mn_bw}-1:0]) | +//: ({${mn_bw}{pk_rsp_mn_sel[4]}} & mn_8b_myuv[${mn_bw}*2-1:${mn_bw}]) | +//: ({${mn_bw}{pk_rsp_mn_sel[6]}} & mn_8b_myuv[${mn_bw}*3-1:${mn_bw}*2]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pk_rsp_mn_data_h0 = ({128{pk_rsp_mn_sel[0]}} & mn_8b_mnorm) | +({128{pk_rsp_mn_sel[2]}} & mn_8b_myuv[128-1:0]) | +({128{pk_rsp_mn_sel[4]}} & mn_8b_myuv[128*2-1:128]) | +({128{pk_rsp_mn_sel[6]}} & mn_8b_myuv[128*3-1:128*2]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign mn_mask_y_en = pk_rsp_planar0_c0_en; +assign mn_mask_uv_0_en = pk_rsp_planar1_c0_en; +assign mn_mask_uv_1_en = pk_rsp_planar1_c1_en; +assign pk_rsp_mn_data_h0_en = pk_rsp_wr_vld; +assign pk_rsp_mn_data_h1_en = (pk_rsp_wr_vld & (~(|pixel_precision) | pixel_packed_10b)); +//: my $Bnum = 64/8; +//: &eperl::flop("-nodeclare -rval \"{${Bnum}{1'b0}}\" -en \"mn_mask_y_en\" -d \"mask_zero\" -q mn_mask_y_d1"); +//: &eperl::flop("-nodeclare -rval \"{${Bnum}{1'b0}}\" -en \"mn_mask_uv_0_en\" -d \"mask_zero\" -q mn_mask_uv_lo_d1"); +//: &eperl::flop("-nodeclare -rval \"{${Bnum}{1'b0}}\" -en \"mn_mask_uv_1_en\" -d \"mask_zero\" -q mn_mask_uv_hi_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mn_mask_y_d1 <= {8{1'b0}}; + end else begin + if ((mn_mask_y_en) == 1'b1) begin + mn_mask_y_d1 <= mask_zero; + // VCS coverage off + end else if ((mn_mask_y_en) == 1'b0) begin + end else begin + mn_mask_y_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mn_mask_uv_lo_d1 <= {8{1'b0}}; + end else begin + if ((mn_mask_uv_0_en) == 1'b1) begin + mn_mask_uv_lo_d1 <= mask_zero; + // VCS coverage off + end else if ((mn_mask_uv_0_en) == 1'b0) begin + end else begin + mn_mask_uv_lo_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mn_mask_uv_hi_d1 <= {8{1'b0}}; + end else begin + if ((mn_mask_uv_1_en) == 1'b1) begin + mn_mask_uv_hi_d1 <= mask_zero; + // VCS coverage off + end else if ((mn_mask_uv_1_en) == 1'b0) begin + end else begin + mn_mask_uv_hi_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////: &eperl::flop("-nodeclare -norst -en \"pk_rsp_mn_data_h1_en\" -d \"pk_rsp_mn_data_h1\" -q pk_mn_out_data_h1"); +//: &eperl::flop("-nodeclare -norst -en \"pk_rsp_mn_data_h0_en\" -d \"pk_rsp_mn_data_h0\" -q pk_mn_out_data_h0"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((pk_rsp_mn_data_h0_en) == 1'b1) begin + pk_mn_out_data_h0 <= pk_rsp_mn_data_h0; + // VCS coverage off + end else if ((pk_rsp_mn_data_h0_en) == 1'b0) begin + end else begin + pk_mn_out_data_h0 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign pk_mn_out_data = {pk_mn_out_data_h1, pk_mn_out_data_h0}; +assign pk_mn_out_data = {pk_mn_out_data_h0}; +//////////////////////////////////////////////////////////////////////// +// cbuf write addresss generator // +//////////////////////////////////////////////////////////////////////// +//////// address base //////// +assign pk_rsp_wr_entries = pk_rsp_cur_1st_height ? sg2pack_entry_st : + pk_rsp_cur_layer_end ? sg2pack_entry_end : sg2pack_entry_mid; +assign pk_rsp_wr_slices = pk_rsp_cur_1st_height ? sg2pack_sub_h_st : + pk_rsp_cur_layer_end ? sg2pack_sub_h_end : sg2pack_sub_h_mid; +assign pk_rsp_wr_base_inc = is_first_running ? {1'b0, status2dma_wr_idx} : (pk_rsp_wr_base + pk_rsp_wr_entries); +assign is_base_wrap = (pk_rsp_wr_base_inc[15 : 9 ] >= {1'd0,pixel_bank}); +assign {mon_pk_rsp_wr_base_wrap[1:0], pk_rsp_wr_base_wrap} = (pk_rsp_wr_base_inc[15 : 9 ] - {1'b0,pixel_bank}); +assign pk_rsp_wr_base_w = is_base_wrap ? {pk_rsp_wr_base_wrap, pk_rsp_wr_base_inc[8 :0]} : pk_rsp_wr_base_inc[15 -1:0]; +assign pk_rsp_wr_base_en = is_first_running | (pk_rsp_wr_vld & pk_rsp_cur_one_line_end & pk_rsp_cur_sub_h_end); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_base_en\" -d \"pk_rsp_wr_base_w\" -q pk_rsp_wr_base"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_wr_base <= {15{1'b0}}; + end else begin + if ((pk_rsp_wr_base_en) == 1'b1) begin + pk_rsp_wr_base <= pk_rsp_wr_base_w; + // VCS coverage off + end else if ((pk_rsp_wr_base_en) == 1'b0) begin + end else begin + pk_rsp_wr_base <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// h_offset //////// +assign {mon_pk_rsp_wr_h_offset_w, + pk_rsp_wr_h_offset_w} = (is_first_running | pk_rsp_cur_sub_h_end) ? 16'b0 : + pk_rsp_wr_h_offset + sg2pack_data_entries; +assign pk_rsp_wr_h_offset_en = is_first_running | (pk_rsp_wr_vld & pk_rsp_cur_loop_end); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_h_offset_en\" -d \"pk_rsp_wr_h_offset_w\" -q pk_rsp_wr_h_offset"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_wr_h_offset <= {15{1'b0}}; + end else begin + if ((pk_rsp_wr_h_offset_en) == 1'b1) begin + pk_rsp_wr_h_offset <= pk_rsp_wr_h_offset_w; + // VCS coverage off + end else if ((pk_rsp_wr_h_offset_en) == 1'b0) begin + end else begin + pk_rsp_wr_h_offset <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////// w_offset //////// +//assign pk_rsp_wr_w_add = pixel_data_shrink ? {1'b0, pk_rsp_wr_size_ori[2:1]} : +// pixel_data_expand ? {pk_rsp_wr_size_ori[1:0], 1'b0} : pk_rsp_wr_size_ori; +assign pk_rsp_wr_w_add = pk_rsp_wr_size_ori; +assign {mon_pk_rsp_wr_w_offset_w, + pk_rsp_wr_w_offset_w} = (is_first_running | (pk_rsp_cur_one_line_end & pk_rsp_cur_sub_h_end)) ? 15'b0 : + (pk_rsp_cur_loop_end & ~pk_rsp_cur_sub_h_end) ? pk_rsp_wr_w_offset_ori : + pk_rsp_wr_w_offset + pk_rsp_wr_w_add; +assign pk_rsp_wr_w_offset_en = is_first_running | pk_rsp_wr_vld; +assign pk_rsp_wr_w_offset_ori_en = is_first_running; +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_w_offset_en\" -d \"pk_rsp_wr_w_offset_w\" -q pk_rsp_wr_w_offset"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_w_offset_ori_en\" -d \"pk_rsp_wr_w_offset_w\" -q pk_rsp_wr_w_offset_ori"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_wr_w_offset <= {15{1'b0}}; + end else begin + if ((pk_rsp_wr_w_offset_en) == 1'b1) begin + pk_rsp_wr_w_offset <= pk_rsp_wr_w_offset_w; + // VCS coverage off + end else if ((pk_rsp_wr_w_offset_en) == 1'b0) begin + end else begin + pk_rsp_wr_w_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_rsp_wr_w_offset_ori <= {15{1'b0}}; + end else begin + if ((pk_rsp_wr_w_offset_ori_en) == 1'b1) begin + pk_rsp_wr_w_offset_ori <= pk_rsp_wr_w_offset_w; + // VCS coverage off + end else if ((pk_rsp_wr_w_offset_ori_en) == 1'b0) begin + end else begin + pk_rsp_wr_w_offset_ori <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////// total_address //////// +//: my $dmaif = (64/8); +//: my $atmc = 8; +//: my $atmm = 8; +//: my $Bnum = int( $dmaif/$atmm ); +//: my $Cnum = int( $atmc/$atmm ); +//: my $ss = int( log($Cnum)/log(2) ); +//: print qq( +//: assign pk_rsp_wr_addr_inc = pk_rsp_wr_base + pk_rsp_wr_h_offset + pk_rsp_wr_w_offset[14:${ss}]; +//: ); +//: if($ss > 0){ +//: print qq( +//: assign pk_rsp_wr_sub_addr = pk_rsp_wr_w_offset[${ss}-1:0]; +//: ); +//: ##} else { +//: ##print qq( +//: ##assign pk_rsp_wr_sub_addr = 2'd0; +//: ##); +//: } +//: +//: if($atmc > $dmaif){ +//: my $k = int( $atmc/$dmaif ); +//: if($k == 2) { +//: if($Bnum == 1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[0]\" -q pk_out_hsel"); +//: } elsif($Bnum == 2) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[1]\" -q pk_out_hsel"); +//: } elsif($Bnum == 4) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[2]\" -q pk_out_hsel"); +//: } +//: } elsif($k == 4) { +//: if($Bnum == 1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[1:0]\" -q pk_out_hsel[1:0]"); +//: } elsif($Bnum == 2) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[2:1]\" -q pk_out_hsel[1:0]"); +//: } elsif($Bnum == 4) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[3:2]\" -q pk_out_hsel[1:0]"); +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pk_rsp_wr_addr_inc = pk_rsp_wr_base + pk_rsp_wr_h_offset + pk_rsp_wr_w_offset[14:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign is_addr_wrap = (pk_rsp_wr_addr_inc[15 +1: 9 ] >= {2'd0, pixel_bank}); +assign {mon_pk_rsp_wr_addr_wrap[2:0], pk_rsp_wr_addr_wrap} = (pk_rsp_wr_addr_inc[16 : 9 ] - {2'b0,pixel_bank}); +assign pk_rsp_wr_addr = is_addr_wrap ? {pk_rsp_wr_addr_wrap, pk_rsp_wr_addr_inc[8 :0]} : pk_rsp_wr_addr_inc[14:0]; +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_addr\" -q pk_out_addr"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_addr <= {15{1'b0}}; + end else begin + if ((pk_rsp_wr_vld) == 1'b1) begin + pk_out_addr <= pk_rsp_wr_addr; + // VCS coverage off + end else if ((pk_rsp_wr_vld) == 1'b0) begin + end else begin + pk_out_addr <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// update status // +//////////////////////////////////////////////////////////////////////// +assign pk_rsp_data_updt = pk_rsp_wr_vld & pk_rsp_cur_one_line_end & pk_rsp_cur_sub_h_end; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pk_rsp_data_updt\" -q pk_out_data_updt"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_data_updt\" -d \"pk_rsp_wr_entries\" -q pk_out_data_entries"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"pk_rsp_data_updt\" -d \"pk_rsp_wr_slices\" -q pk_out_data_slices"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_data_updt <= 1'b0; + end else begin + pk_out_data_updt <= pk_rsp_data_updt; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_data_entries <= {15{1'b0}}; + end else begin + if ((pk_rsp_data_updt) == 1'b1) begin + pk_out_data_entries <= pk_rsp_wr_entries; + // VCS coverage off + end else if ((pk_rsp_data_updt) == 1'b0) begin + end else begin + pk_out_data_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pk_out_data_slices <= {4{1'b0}}; + end else begin + if ((pk_rsp_data_updt) == 1'b1) begin + pk_out_data_slices <= pk_rsp_wr_slices; + // VCS coverage off + end else if ((pk_rsp_data_updt) == 1'b0) begin + end else begin + pk_out_data_slices <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// output connection // +//////////////////////////////////////////////////////////////////////// +assign img2status_dat_updt = pk_out_data_updt; +assign img2status_dat_slices = {{10{1'b0}}, pk_out_data_slices}; +assign img2status_dat_entries = pk_out_data_entries; +assign img2cvt_dat_wr_en = pk_out_vld; +//assign img2cvt_dat_wr_addr = pk_out_addr; +//assign img2cvt_dat_wr_sel = pk_out_hsel; +//assign img2cvt_dat_wr_data = pk_out_data; +//assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; +assign img2cvt_dat_wr_info_pd = pk_out_info_pd; +//assign img2cvt_mn_wr_data = pk_mn_out_data; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: assign img2cvt_dat_wr_sel = pk_out_hsel; +//: assign img2cvt_dat_wr_addr = pk_out_addr; +//: assign img2cvt_dat_wr_data = pk_out_data; +//: assign img2cvt_mn_wr_data = pk_mn_out_data; +//: assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: assign img2cvt_dat_wr_mask = ?; // +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign img2cvt_dat_wr_addr${i} = img2cvt_dat_wr_addr${i} ;// +//: assign img2cvt_dat_wr_data${i} = img2cvt_dat_wr_data${i} ;// +//: assign img2cvt_mn_wr_data${i} = img2cvt_mn_wr_data${i} ;// +//: assign img2cvt_dat_wr_pad_mask${i} = img2cvt_dat_wr_pad_mask${i};// +//: ); +//: } +//: } else { +//: print qq( +//: assign img2cvt_dat_wr_addr = {2'd0,pk_out_addr}; +//: assign img2cvt_dat_wr_data = pk_out_data; +//: assign img2cvt_mn_wr_data = pk_mn_out_data; +//: assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign img2cvt_dat_wr_addr = {2'd0,pk_out_addr}; +assign img2cvt_dat_wr_data = pk_out_data; +assign img2cvt_mn_wr_data = pk_mn_out_data; +assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// global status // +//////////////////////////////////////////////////////////////////////// +assign pack_is_done_w = is_first_running ? 1'b0 : + pk_rsp_wr_vld & pk_rsp_cur_layer_end ? 1'b1 : pack_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"pack_is_done_w\" -q pack_is_done"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_is_done <= 1'b1; + end else begin + pack_is_done <= pack_is_done_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_img_pack__pk_rsp_wr_base_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (pk_rsp_wr_base_en & is_base_wrap); + endproperty +// Cover 0 : "(pk_rsp_wr_base_en & is_base_wrap)" + FUNCPOINT_cdma_img_pack__pk_rsp_wr_base_wrap__0_COV : cover property (cdma_img_pack__pk_rsp_wr_base_wrap__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_pack__pack_early_end__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (pk_rsp_vld & pk_rsp_early_end); + endproperty +// Cover 1 : "(pk_rsp_vld & pk_rsp_early_end)" + FUNCPOINT_cdma_img_pack__pack_early_end__1_COV : cover property (cdma_img_pack__pack_early_end__1_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_height_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_loop_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_pburst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_p0_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_p1_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_63x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_71x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar0_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_85x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar0_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c1_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_h1_en | is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_h0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mn_mask_y_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mn_mask_uv_0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mn_mask_uv_1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_h_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_w_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_100x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_w_offset_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_104x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_109x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! p0_burst and p1_burst mismatch!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (sg2pack_img_pvld & pixel_planar & (img_p0_burst * 2 != img_p1_burst) & (img_p0_burst * 2 != img_p1_burst + 1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! layer_end signal conflict with local cnt!") zzz_assert_never_14x (nvdla_core_clk, `ASSERT_RESET, (rd_line_end & (is_last_height ^ img_layer_end))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rd_sub_h_limit is overflow!") zzz_assert_never_16x (nvdla_core_clk, `ASSERT_RESET, (mon_rd_sub_h_limit & is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rd_loop_cnt_limit is overflow!") zzz_assert_never_17x (nvdla_core_clk, `ASSERT_RESET, (mon_rd_loop_cnt_limit & is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p0_cnt_w is overflow!") zzz_assert_never_45x (nvdla_core_clk, `ASSERT_RESET, (data_planar0_en & mon_data_planar0_p0_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p1_cnt_w is overflow!") zzz_assert_never_46x (nvdla_core_clk, `ASSERT_RESET, (data_planar0_en & mon_data_planar0_p1_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p0_cnt_w is overflow!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (data_planar1_en & mon_data_planar1_p0_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p1_cnt_w is overflow!") zzz_assert_never_48x (nvdla_core_clk, `ASSERT_RESET, (data_planar1_en & mon_data_planar1_p1_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p0_cur_flag invalid!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & ~rd_planar_cnt & data_planar0_p0_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p1_cur_flag invalid!") zzz_assert_never_50x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & ~rd_planar_cnt & data_planar0_p1_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p0_cur_flag invalid!") zzz_assert_never_51x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & rd_planar_cnt & data_planar1_p0_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p1_cur_flag invalid!") zzz_assert_never_52x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & rd_planar_cnt & data_planar1_p1_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_cnt is overflow!") zzz_assert_never_80x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_vld & mon_pk_rsp_wr_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_cnt is out of range!") zzz_assert_never_81x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_vld & (pk_rsp_wr_cnt > 2'h2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_base_wrap is overflow!") zzz_assert_never_94x (nvdla_core_clk, `ASSERT_RESET, (is_base_wrap & (|mon_pk_rsp_wr_base_wrap) & pk_rsp_wr_base_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_base_w is out of range!") zzz_assert_never_95x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_base_en & (pk_rsp_wr_base_w >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_h_offset_w is overflow!") zzz_assert_never_97x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_h_offset_en & mon_pk_rsp_wr_h_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_h_offset_w is out of range!") zzz_assert_never_98x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_h_offset_en & (pk_rsp_wr_h_offset_w >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_w_offset_w is overflow!") zzz_assert_never_101x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_w_offset_en & mon_pk_rsp_wr_w_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_w_offset_w is out of range!") zzz_assert_never_102x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_w_offset_en & (pk_rsp_wr_w_offset_w[13:2] >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! store 16 bytes when not line end!") zzz_assert_never_103x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_w_offset_en & ~pk_rsp_cur_one_line_end & ~(|pk_rsp_wr_w_add))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_addr_wrap is overflow!") zzz_assert_never_106x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_vld & is_addr_wrap & (|mon_pk_rsp_wr_addr_wrap))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_addr is out of range!") zzz_assert_never_107x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_vld & (pk_rsp_wr_addr >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_sub_addr conflict with pk_rsp_wr_w_add!") zzz_assert_never_108x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_vld & (pk_rsp_wr_w_add + pk_rsp_wr_sub_addr > 4'h4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pack_is_done cleared when idle!") zzz_assert_never_111x (nvdla_core_clk, `ASSERT_RESET, (~pack_is_done & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_IMG_pack diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v.vcp new file mode 100644 index 0000000..6cdd272 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v.vcp @@ -0,0 +1,1571 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_pack.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_IMG_pack ( + nvdla_core_clk + ,nvdla_core_rstn +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,img2sbuf_p${i}_rd_data +//: ,img2sbuf_p${i}_rd_addr +//: ,img2sbuf_p${i}_rd_en +//: ); +//: } + ,is_running + ,layer_st + ,pixel_bank + ,pixel_data_expand + ,pixel_data_shrink + ,pixel_early_end + ,pixel_packed_10b + ,pixel_planar + ,pixel_planar0_sft + ,pixel_planar1_sft + ,pixel_precision + ,pixel_uint + ,reg2dp_datain_channel + ,reg2dp_datain_width + ,reg2dp_mean_ax + ,reg2dp_mean_bv + ,reg2dp_mean_gu + ,reg2dp_mean_ry + ,reg2dp_pad_left + ,reg2dp_pad_right + ,sg2pack_data_entries + ,sg2pack_entry_end + ,sg2pack_entry_mid + ,sg2pack_entry_st + ,sg2pack_height_total + ,sg2pack_img_pd + ,sg2pack_img_pvld + ,sg2pack_mn_enable + ,sg2pack_sub_h_end + ,sg2pack_sub_h_mid + ,sg2pack_sub_h_st + ,status2dma_wr_idx +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_sel +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,img2cvt_dat_wr_addr${i} +//: ,img2cvt_dat_wr_data${i} +//: ,img2cvt_mn_wr_data${i} +//: ,img2cvt_dat_wr_pad_mask${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } +//,img2cvt_dat_wr_addr +//,img2cvt_dat_wr_data + ,img2cvt_dat_wr_en +//,img2cvt_dat_wr_hsel + ,img2cvt_dat_wr_info_pd +//,img2cvt_dat_wr_pad_mask +//,img2cvt_mn_wr_data + ,img2status_dat_entries + ,img2status_dat_slices + ,img2status_dat_updt + ,pack_is_done + ,sg2pack_img_prdy + ); +///////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: input [${atmm}-1:0] img2sbuf_p${i}_rd_data; +//: output [7:0] img2sbuf_p${i}_rd_addr; +//: output img2sbuf_p${i}_rd_en; +//: ); +//: } +input is_running; +input layer_st; +input [5:0] pixel_bank; +input pixel_data_expand; +input pixel_data_shrink; +input pixel_early_end; +input pixel_packed_10b; +input pixel_planar; +input [2:0] pixel_planar0_sft; +input [2:0] pixel_planar1_sft; +input [1:0] pixel_precision; +input pixel_uint; +input [14:0] sg2pack_data_entries; +input [14:0] sg2pack_entry_end; +input [14:0] sg2pack_entry_mid; +input [14:0] sg2pack_entry_st; +input [12:0] sg2pack_height_total; +input [10:0] sg2pack_img_pd; +input sg2pack_img_pvld; +input sg2pack_mn_enable; +input [3:0] sg2pack_sub_h_end; +input [3:0] sg2pack_sub_h_mid; +input [3:0] sg2pack_sub_h_st; +input [14:0] status2dma_wr_idx; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_sel; +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr${i}; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +////output [11:0] img2cvt_dat_wr_addr; +////output [511:0] img2cvt_dat_wr_data; +output img2cvt_dat_wr_en; +////output img2cvt_dat_wr_hsel; +output [11:0] img2cvt_dat_wr_info_pd; +////output [1023:0] img2cvt_mn_wr_data; +////output [63:0] img2cvt_dat_wr_pad_mask;//element per dmaif +output [14:0] img2status_dat_entries; +output [13:0] img2status_dat_slices; +output img2status_dat_updt; +output pack_is_done; +output sg2pack_img_prdy; +input [12:0] reg2dp_datain_width; +input [12:0] reg2dp_datain_channel; +input [15:0] reg2dp_mean_ry; +input [15:0] reg2dp_mean_gu; +input [15:0] reg2dp_mean_bv; +input [15:0] reg2dp_mean_ax; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +///////////////////////////////////////////////////////////// +reg [5:0] data_planar0_add; +reg [13:0] data_planar0_cur_cnt; +//reg [13:0] data_planar0_ori_cnt; +reg [2:0] data_planar0_p1_flag; +//reg [2:0] data_planar0_p1_ori_flag; +reg [5:0] data_planar1_add; +reg [13:0] data_planar1_cur_cnt; +//reg [13:0] data_planar1_ori_cnt; +reg [2:0] data_planar1_p1_flag; +//reg [2:0] data_planar1_p1_ori_flag; +reg [13:0] data_width_mark_1; +reg [13:0] data_width_mark_2; +reg is_running_d1; +//: my $atmmbw = int(log(8)/log(2)); +//: print qq( +//: reg [${atmmbw}-1:0] lp_planar0_mask_sft; +//: wire [${atmmbw}-1:0] lp_planar0_mask_sft_w; +//: reg [${atmmbw}-1:0] lp_planar1_mask_sft; +//: wire [${atmmbw}-1:0] lp_planar1_mask_sft_w; +//: reg [${atmmbw}-1:0] rp_planar0_mask_sft; +//: wire [${atmmbw}-1:0] rp_planar0_mask_sft_w; +//: reg [${atmmbw}-1:0] rp_planar1_mask_sft; +//: wire [${atmmbw}-1:0] rp_planar1_mask_sft_w; +//: reg [${atmmbw}-1:0] zero_planar0_mask_sft; +//: wire [${atmmbw}-1:0] zero_planar0_mask_sft_w; +//: reg [${atmmbw}-1:0] zero_planar1_mask_sft; +//: wire [${atmmbw}-1:0] zero_planar1_mask_sft_w; +//: ); +reg [64/8 -1:0] mask_pad_planar0_c0_d1; +reg [64/8 -1:0] mask_pad_planar1_c0_d1; +reg [64/8 -1:0] mask_pad_planar1_c1_d1; +reg [64/8 -1:0] mn_mask_uv_hi_d1; +reg [64/8 -1:0] mn_mask_uv_lo_d1; +reg [64/8 -1:0] mn_mask_y_d1; +reg pack_is_done; +reg [4:0] pad_left_d1; +//reg [64 -1:0] pk_mn_out_data_h0; +//reg [64 -1:0] pk_mn_out_data_h1; +reg [14:0] pk_out_addr; +reg [14:0] pk_out_data_entries; +reg [64 -1:0] pk_out_data_h0; +//reg [511:0] pk_out_data_h1; +reg [3:0] pk_out_data_slices; +reg pk_out_data_updt; +reg pk_out_ext128; +//reg pk_out_ext64; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: reg [${k}-1:0] pk_out_hsel; +//: ); +//: } +reg [3:0] pk_out_mask; +reg pk_out_mean; +reg [64/8 -1:0] pk_out_pad_mask_h0; +//reg [63:0] pk_out_pad_mask_h1; +reg [2:0] pk_out_sub_h; +reg pk_out_uint; +reg pk_out_vld; +reg pk_rsp_1st_height_d1; +reg pk_rsp_layer_end_d1; +reg pk_rsp_loop_end_d1; +reg pk_rsp_one_line_end_d1; +reg [64 -1:0] pk_rsp_planar0_c0_d1; +reg [64 -1:0] pk_rsp_planar1_c0_d1; +reg [64 -1:0] pk_rsp_planar1_c1_d1; +reg [2:0] pk_rsp_sub_h_d1; +reg pk_rsp_sub_h_end_d1; +reg pk_rsp_vld_d1; +reg [14:0] pk_rsp_wr_base; +reg [1:0] pk_rsp_wr_cnt; +reg [14:0] pk_rsp_wr_h_offset; +reg [14:0] pk_rsp_wr_w_offset; +reg [14:0] pk_rsp_wr_w_offset_ori; +reg rd_1st_height_d1; +reg [12:0] rd_height_cnt; +reg rd_layer_end_d1; +reg rd_local_vld; +reg [3:0] rd_loop_cnt; +reg rd_loop_end_d1; +reg rd_one_line_end_d1; +reg [7:0] rd_p0_addr_d1; +reg [8 -1:0] rd_p0_pad_mask_d1; +reg [6:0] rd_p0_planar0_idx; +reg [6:0] rd_p0_planar0_ori_idx; +reg [6:0] rd_p0_planar1_idx; +reg [6:0] rd_p0_planar1_ori_idx; +reg rd_p0_vld_d1; +reg [8 -1:0] rd_p0_zero_mask_d1; +reg [7:0] rd_p1_addr_d1; +reg [8 -1:0] rd_p1_pad_mask_d1; +reg [6:0] rd_p1_planar0_idx; +reg [6:0] rd_p1_planar0_ori_idx; +reg [6:0] rd_p1_planar1_idx; +reg [6:0] rd_p1_planar1_ori_idx; +reg rd_p1_vld_d1; +reg [8 -1:0] rd_p1_zero_mask_d1; +reg [1:0] rd_pburst_cnt; +reg rd_planar_cnt; +reg rd_planar_d1; +reg [2:0] rd_sub_h_d1; +reg rd_sub_h_end_d1; +reg rd_vld_d1; +//reg [4:0] rp_planar0_mask_sft; +//wire [4:0] rp_planar0_mask_sft_w; +//reg [4:0] rp_planar1_mask_sft; +//wire [4:0] rp_planar1_mask_sft_w; +//reg [4:0] zero_planar0_mask_sft; +//wire [4:0] zero_planar0_mask_sft_w; +//reg [4:0] zero_planar1_mask_sft; +//wire [4:0] zero_planar1_mask_sft_w; +wire [64 -1:0] dat_l0; +wire [64*2-1:0] dat_l1; +wire [64 -1:0] dat_l1_hi; +wire [64 -1:0] dat_l1_lo; +wire [64*3-1:0] dat_yuv; +wire [64*3-1:0] dat_8b_yuv; +wire [5:0] data_planar0_add_w; +wire [13:0] data_planar0_cur_cnt_w; +wire data_planar0_en; +//wire data_planar0_ori_en; +wire [13:0] data_planar0_p0_cnt_w; +wire [2:0] data_planar0_p0_cur_flag; +wire [8 -1:0] data_planar0_p0_lp_mask; +wire [8 -1:0] data_planar0_p0_pad_mask; +wire [8 -1:0] data_planar0_p0_rp_mask; +wire [8 -1:0] data_planar0_p0_zero_mask; +wire [13:0] data_planar0_p1_cnt_w; +wire [2:0] data_planar0_p1_cur_flag; +wire [2:0] data_planar0_p1_flag_w; +wire [8 -1:0] data_planar0_p1_lp_mask; +wire [8 -1:0] data_planar0_p1_pad_mask; +wire [8 -1:0] data_planar0_p1_rp_mask; +wire [8 -1:0] data_planar0_p1_zero_mask; +wire [5:0] data_planar1_add_w; +wire [13:0] data_planar1_cur_cnt_w; +wire data_planar1_en; +//wire data_planar1_ori_en; +wire [13:0] data_planar1_p0_cnt_w; +wire [2:0] data_planar1_p0_cur_flag; +wire [8 -1:0] data_planar1_p0_lp_mask; +wire [8 -1:0] data_planar1_p0_pad_mask; +wire [8 -1:0] data_planar1_p0_rp_mask; +wire [8 -1:0] data_planar1_p0_zero_mask; +wire [13:0] data_planar1_p1_cnt_w; +wire [2:0] data_planar1_p1_cur_flag; +wire [2:0] data_planar1_p1_flag_w; +wire [8 -1:0] data_planar1_p1_lp_mask; +wire [8 -1:0] data_planar1_p1_pad_mask; +wire [8 -1:0] data_planar1_p1_rp_mask; +wire [8 -1:0] data_planar1_p1_zero_mask; +wire [13:0] data_width_mark_0; +wire [13:0] data_width_mark_1_w; +wire [13:0] data_width_mark_2_w; +wire img_layer_end; +wire img_line_end; +wire [3:0] img_p0_burst; +wire [4:0] img_p1_burst; +wire [10:0] img_pd; +wire is_1st_height; +wire is_addr_wrap; +wire is_base_wrap; +wire is_first_running; +wire is_last_height; +wire is_last_loop; +wire is_last_pburst; +wire is_last_planar; +wire is_last_sub_h; +wire [64/8 -1:0] mask_pad; +wire [64/8 -1:0] mask_zero; +//wire [511:0] mn_16b_mnorm; +//wire [1535:0] mn_16b_myuv; +//wire [64 -1:0] mn_8b_mnorm; +//wire [64*3-1:0] mn_8b_myuv; +//: my $mn_bw = int(64 / 8) * 16 ; +//: print qq( +//: wire [${mn_bw}-1:0] mn_ch1; +//: wire [${mn_bw}-1:0] mn_ch4; +//: wire [${mn_bw}*3-1:0] mn_ch3; +//: wire [${mn_bw}*3-1:0] mn_8b_myuv; +//: wire [${mn_bw}-1:0] mn_ch1_4; +//: wire [${mn_bw}-1:0] mn_8b_mnorm; +//: wire [${mn_bw}-1:0] pk_rsp_mn_data_h0; +//: reg [${mn_bw}-1:0] pk_mn_out_data_h0; +//: wire [${mn_bw}-1:0] pk_mn_out_data; +//: ); +//wire [64 -1:0] mn_ch1; +//wire [64 -1:0] mn_ch1_4; +//wire [64*3-1:0] mn_ch3; +//wire [64 -1:0] mn_ch4; +wire [(64/8)*2-1:0] mn_mask_uv; +wire mn_mask_uv_0_en; +wire mn_mask_uv_1_en; +wire [64/8 -1:0] mn_mask_uv_hi; +wire [64/8 -1:0] mn_mask_uv_lo; +wire [64/8 -1:0] mn_mask_y; +wire mn_mask_y_en; +wire [(64/8)*3-1:0] mn_mask_yuv; +wire mon_data_planar0_p0_cnt_w; +wire mon_data_planar0_p1_cnt_w; +wire mon_data_planar1_p0_cnt_w; +wire mon_data_planar1_p1_cnt_w; +wire [2:0] mon_lp_planar0_mask_sft_w; +wire [2:0] mon_lp_planar1_mask_sft_w; +wire [2:0] mon_pk_rsp_wr_addr_wrap; +wire [1:0] mon_pk_rsp_wr_base_wrap; +wire mon_pk_rsp_wr_cnt_w; +wire mon_pk_rsp_wr_h_offset_w; +wire mon_pk_rsp_wr_w_offset_w; +wire mon_rd_loop_cnt_inc; +wire mon_rd_loop_cnt_limit; +wire [2:0] mon_rp_planar0_mask_sft_w; +wire [2:0] mon_rp_planar1_mask_sft_w; +wire [2:0] mon_zero_planar0_mask_sft_w; +wire [2:0] mon_zero_planar1_mask_sft_w; +wire pack_is_done_w; +wire [(64/8)*3-1:0] pad_mask_8b_yuv; +wire [64/8 -1:0] pad_mask_l0; +wire [(64/8)*2-1:0] pad_mask_l1; +wire [64/8 -1:0] pad_mask_l1_hi; +wire [64/8 -1:0] pad_mask_l1_lo; +wire [(64/8)*3-1:0] pad_mask_yuv; +//wire [64 -1:0] pk_mn_out_data; +wire [64 -1:0] pk_out_data; +wire [11:0] pk_out_info_pd; +//wire pk_out_interleave; +//wire [127:0] pk_out_pad_mask; +wire [64/8 -1:0] pk_out_pad_mask; +wire pk_rsp_1st_height; +wire pk_rsp_cur_1st_height; +wire pk_rsp_cur_layer_end; +wire pk_rsp_cur_loop_end; +wire pk_rsp_cur_one_line_end; +wire [2:0] pk_rsp_cur_sub_h; +wire pk_rsp_cur_sub_h_end; +wire pk_rsp_cur_vld; +//wire [1023:0] pk_rsp_dat_ergb; +//wire [1023:0] pk_rsp_dat_mergb; +wire [64 -1:0] pk_rsp_dat_mnorm; +wire [64 -1:0] pk_rsp_dat_normal; +wire [64 -1:0] pk_rsp_data_h0; +wire pk_rsp_data_h0_en; +//wire [511:0] pk_rsp_data_h1; +//wire pk_rsp_data_h1_en; +wire pk_rsp_data_updt; +wire pk_rsp_early_end; +wire pk_rsp_layer_end; +wire pk_rsp_loop_end; +//wire [64 -1:0] pk_rsp_mn_data_h0; +wire pk_rsp_mn_data_h0_en; +//wire [511:0] pk_rsp_mn_data_h1; +wire pk_rsp_mn_data_h1_en; +wire [7:0] pk_rsp_mn_sel; +wire pk_rsp_one_line_end; +wire [4:0] pk_rsp_out_sel; +wire [8*8 -1:0] pk_rsp_p0_data; +wire [8 -1:0] pk_rsp_p0_pad_mask; +wire [8 -1:0] pk_rsp_p0_zero_mask; +wire [8*8 -1:0] pk_rsp_p1_data; +wire [8 -1:0] pk_rsp_p1_pad_mask; +wire [8 -1:0] pk_rsp_p1_zero_mask; +//wire [127:0] pk_rsp_pad_mask_ergb; +wire [64/8 -1:0] pk_rsp_pad_mask_h0; +//wire [63:0] pk_rsp_pad_mask_h1; +wire [64/8 -1:0] pk_rsp_pad_mask_norm; +wire pk_rsp_pipe_sel; +wire pk_rsp_planar; +wire pk_rsp_planar0_c0_en; +wire pk_rsp_planar1_c0_en; +wire pk_rsp_planar1_c1_en; +wire [2:0] pk_rsp_sub_h; +wire pk_rsp_sub_h_end; +wire pk_rsp_vld; +wire pk_rsp_vld_d1_w; +wire [14:0] pk_rsp_wr_addr; +wire [16:0] pk_rsp_wr_addr_inc; +wire [5:0] pk_rsp_wr_addr_wrap; +wire pk_rsp_wr_base_en; +wire [15:0] pk_rsp_wr_base_inc; +wire [14:0] pk_rsp_wr_base_w; +wire [5:0] pk_rsp_wr_base_wrap; +wire [1:0] pk_rsp_wr_cnt_w; +wire [14:0] pk_rsp_wr_entries; +//wire pk_rsp_wr_ext128; +//wire pk_rsp_wr_ext64; +wire pk_rsp_wr_h_offset_en; +wire [14:0] pk_rsp_wr_h_offset_w; +wire [3:0] pk_rsp_wr_mask; +wire [2:0] pk_rsp_wr_size_ori; +wire [3:0] pk_rsp_wr_slices; +wire [1:0] pk_rsp_wr_sub_addr; +wire pk_rsp_wr_vld; +wire [2:0] pk_rsp_wr_w_add; +wire pk_rsp_wr_w_offset_en; +wire pk_rsp_wr_w_offset_ori_en; +wire [14:0] pk_rsp_wr_w_offset_w; +wire [13:0] rd_height_cnt_inc; +wire [12:0] rd_height_cnt_w; +wire rd_height_en; +wire rd_height_end; +wire [2:0] rd_idx_add; +wire rd_line_end; +wire rd_local_vld_w; +wire [3:0] rd_loop_cnt_inc; +wire [3:0] rd_loop_cnt_limit; +wire [3:0] rd_loop_cnt_w; +wire rd_loop_en; +wire rd_loop_end; +wire [7:0] rd_p0_addr; +wire [8 -1:0] rd_p0_pad_mask; +wire [7:0] rd_p0_planar0_idx_inc; +wire [6:0] rd_p0_planar0_idx_w; +wire [7:0] rd_p0_planar1_idx_inc; +wire [6:0] rd_p0_planar1_idx_w; +wire rd_p0_vld; +wire [8 -1:0] rd_p0_zero_mask; +wire [7:0] rd_p1_addr; +wire [8 -1:0] rd_p1_pad_mask; +wire [7:0] rd_p1_planar0_idx_inc; +wire [6:0] rd_p1_planar0_idx_w; +wire [7:0] rd_p1_planar1_idx_inc; +wire [6:0] rd_p1_planar1_idx_w; +wire rd_p1_vld; +wire [8 -1:0] rd_p1_zero_mask; +wire [1:0] rd_pburst_cnt_w; +wire rd_pburst_en; +wire rd_pburst_end; +wire [1:0] rd_pburst_limit; +wire rd_planar0_burst_end; +wire rd_planar0_en; +wire rd_planar0_line_end; +wire rd_planar0_ori_en; +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: print qq( +//: wire [${atmm_num}-1:0] rd_planar0_rd_mask; +//: wire [${atmm_num}-1:0] rd_planar1_rd_mask; +//: wire [${atmm_num}-1:0] rd_rd_mask; +//: ); +wire rd_planar1_burst_end; +wire rd_planar1_en; +wire rd_planar1_line_end; +wire rd_planar1_ori_en; +wire rd_planar_cnt_w; +wire rd_planar_en; +wire rd_planar_end; +wire [2:0] rd_sub_h_cnt; +wire rd_sub_h_end; +wire rd_vld; +wire [64 -1:0] rdat; +//wire [13:0] z14; +//wire [5:0] z6; +//////////////////////////////////////////////////////////////////////// +// signals from other modules // +//////////////////////////////////////////////////////////////////////// +assign img_pd = sg2pack_img_pvld ? sg2pack_img_pd : 11'b0; +assign img_p0_burst[3:0] = img_pd[3:0]; +assign img_p1_burst[4:0] = img_pd[8:4]; +assign img_line_end = img_pd[9]; +assign img_layer_end = img_pd[10]; +assign is_first_running = ~is_running_d1 & is_running; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//////////////////////////////////////////////////////////////////////// +// general signals // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"reg2dp_pad_left\" -q pad_left_d1"); +assign data_width_mark_0 = {{9{1'b0}}, pad_left_d1}; +assign data_width_mark_1_w = reg2dp_pad_left + reg2dp_datain_width + 1'b1; +assign data_width_mark_2_w = reg2dp_pad_left + reg2dp_datain_width + 1'b1 + reg2dp_pad_right; +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_width_mark_1_w\" -q data_width_mark_1"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_width_mark_2_w\" -q data_width_mark_2"); +// 5'b0 means atmm bw +//: my $atmmbw = int(log(8)/log(2)); +//: print qq( +//: assign {mon_lp_planar0_mask_sft_w, lp_planar0_mask_sft_w} = ({data_width_mark_0[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar0_sft); +//: assign {mon_lp_planar1_mask_sft_w, lp_planar1_mask_sft_w} = ({data_width_mark_0[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar1_sft); +//: +//: assign {mon_rp_planar0_mask_sft_w, rp_planar0_mask_sft_w} = ({data_width_mark_1[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar0_sft); +//: assign {mon_rp_planar1_mask_sft_w, rp_planar1_mask_sft_w} = ({data_width_mark_1[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar1_sft); +//: +//: assign {mon_zero_planar0_mask_sft_w, zero_planar0_mask_sft_w} = ({data_width_mark_2[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar0_sft); +//: assign {mon_zero_planar1_mask_sft_w, zero_planar1_mask_sft_w} = ({data_width_mark_2[${atmmbw}-1:0], ${atmmbw}'b0} >> pixel_planar1_sft); +//: ); +assign data_planar0_add_w = (1'b1 << pixel_planar0_sft); +assign data_planar1_add_w = (1'b1 << pixel_planar1_sft); +//: my $atmmbw = int(log(8)/log(2)); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"lp_planar0_mask_sft_w\" -q lp_planar0_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"lp_planar1_mask_sft_w\" -q lp_planar1_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"rp_planar0_mask_sft_w\" -q rp_planar0_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"rp_planar1_mask_sft_w\" -q rp_planar1_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"zero_planar0_mask_sft_w\" -q zero_planar0_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{${atmmbw}{1'b0}}\" -en \"is_first_running\" -d \"zero_planar1_mask_sft_w\" -q zero_planar1_mask_sft"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"is_first_running\" -d \"data_planar0_add_w\" -q data_planar0_add"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"is_first_running\" -d \"data_planar1_add_w\" -q data_planar1_add"); +//////////////////////////////////////////////////////////////////////// +// Shared buffer read sequnce generator // +//////////////////////////////////////////////////////////////////////// +assign is_1st_height = ~(|rd_height_cnt); +assign is_last_height = (rd_height_cnt == sg2pack_height_total); +assign rd_height_cnt_inc = rd_height_cnt + 1'b1; +assign rd_height_cnt_w = (is_first_running) ? 13'b0 : rd_height_cnt_inc[12:0]; +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"rd_height_en\" -d \"rd_height_cnt_w\" -q rd_height_cnt"); +//////// sub height counter //////// +assign is_last_sub_h = 1'b1; +assign rd_sub_h_cnt = 3'b0; +//////// loop cnt //////// +// img_p0_burst[3:1],means img_p0_burst/2, 2 means atmm_num/per_dmaif +//: my $dmaif = 64; +//: my $atmm_num = int($dmaif/8/8); +//: if($atmm_num == 1) { +//: print qq( +//: assign rd_loop_cnt_limit = img_p0_burst[3:0]; +//: ) +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign {mon_rd_loop_cnt_limit, rd_loop_cnt_limit} = img_p0_burst[3:1] + img_p0_burst[0]; +//: ) +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign {mon_rd_loop_cnt_limit, rd_loop_cnt_limit} = img_p0_burst[3:2] + (|img_p0_burst[1:0]); +//: ) +//: } +assign {mon_rd_loop_cnt_inc, rd_loop_cnt_inc} = rd_loop_cnt + 1'b1; +assign is_last_loop = (rd_loop_cnt_inc >= rd_loop_cnt_limit); +assign rd_loop_cnt_w = (is_first_running | is_last_loop) ? 4'b0 : rd_loop_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"rd_loop_en\" -d \"rd_loop_cnt_w\" -q rd_loop_cnt"); +//////// planar cnt //////// +assign rd_planar_cnt_w = (is_first_running | is_last_planar) ? 1'b0 : ~rd_planar_cnt; +assign is_last_planar = ~pixel_planar | rd_planar_cnt; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_planar_en\" -d \"rd_planar_cnt_w\" -q rd_planar_cnt"); +//////// partial burst cnt //////// +//assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p0_burst[0])) ? 1'b1 : 1'b0; +//: my $dmaif = 64; +//: my $atmm_num = int($dmaif/8/8); +//: if($atmm_num == 1) { +//: print qq( +//: //assign rd_pburst_limit = 2'b0; +//: assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p1_burst[0])) ? 2'b1 : 2'b0; +//: ) +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | ~img_p0_burst[0])) ? 2'b1 : 2'b0; +//: ) +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rd_pburst_limit = (rd_planar_cnt & (~is_last_loop | (img_p0_burst[1:0]==2'd0))) ? 2'b3 +//: (rd_planar_cnt & (~is_last_loop | (img_p0_burst[1:0]==2'd1))) ? 2'b0 +//: (rd_planar_cnt & (~is_last_loop | (img_p0_burst[1:0]==2'd2))) ? 2'b1 : 2'b2; +//: ) +//: } +assign is_last_pburst = (rd_pburst_cnt == rd_pburst_limit); +assign rd_pburst_cnt_w = (is_first_running | is_last_pburst) ? 2'b0 : rd_pburst_cnt + 1'b1; +//: &eperl::flop("-nodeclare -rval \"2'b0\" -en \"rd_pburst_en\" -d \"rd_pburst_cnt_w\" -q rd_pburst_cnt"); +//////// control logic //////// +assign sg2pack_img_prdy = rd_vld & rd_sub_h_end; +assign rd_vld = (sg2pack_img_pvld | rd_local_vld); +assign rd_local_vld_w = (~is_running) ? 1'b0 : + rd_sub_h_end ? 1'b0 : + sg2pack_img_pvld ? 1'b1 : rd_local_vld; +assign rd_pburst_end = rd_vld & is_last_pburst; +assign rd_planar_end = rd_vld & is_last_pburst & is_last_planar; +assign rd_loop_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop; +assign rd_sub_h_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop & is_last_sub_h; +assign rd_line_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop & is_last_sub_h & img_line_end; +assign rd_height_end = rd_vld & is_last_pburst & is_last_planar & is_last_loop & is_last_sub_h & img_line_end & is_last_height; +assign rd_pburst_en = is_first_running | rd_vld; +assign rd_planar_en = is_first_running | (rd_pburst_end & pixel_planar); +assign rd_loop_en = is_first_running | rd_planar_end; +assign rd_height_en = is_first_running | rd_line_end; +assign rd_planar0_burst_end = rd_vld & is_last_pburst & ~rd_planar_cnt & is_last_loop; +assign rd_planar1_burst_end = rd_vld & is_last_pburst & rd_planar_cnt & is_last_loop; +assign rd_planar0_line_end = rd_vld & is_last_pburst & ~rd_planar_cnt & is_last_loop & is_last_sub_h & img_line_end; +assign rd_planar1_line_end = rd_vld & is_last_pburst & rd_planar_cnt & is_last_loop & is_last_sub_h & img_line_end; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rd_local_vld_w\" -q rd_local_vld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rd_vld\" -q rd_vld_d1"); +//////////////////////////////////////////////////////////////////////// +// read control logic generator // +//////////////////////////////////////////////////////////////////////// +//////// read enalbe mask //////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign rd_planar0_rd_mask = 1'h1; +//: assign rd_planar1_rd_mask = 1'h1; +//: +//: assign rd_p0_vld = rd_vld & rd_rd_mask[0]; +//: +//: assign rd_idx_add = 3'h1; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rd_planar0_rd_mask = (is_last_loop & is_last_pburst & img_p0_burst[0]) ? 2'h1 : 2'h3; +//: assign rd_planar1_rd_mask = (is_last_loop & is_last_pburst & img_p1_burst[0]) ? 2'h1 : 2'h3; +//: +//: assign rd_p0_vld = rd_vld & rd_rd_mask[0]; +//: assign rd_p1_vld = rd_vld & rd_rd_mask[1]; +//: +//: assign rd_idx_add = rd_rd_mask[1] ? 3'h2 : 3'h1; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rd_planar0_rd_mask = (is_last_loop & is_last_pburst & (img_p0_burst[1:0]==2'd0)) ? 4'h1 : +//: (is_last_loop & is_last_pburst & (img_p0_burst[1:0]==2'd1)) ? 4'h3 : +//: (is_last_loop & is_last_pburst & (img_p0_burst[1:0]==2'd2)) ? 4'h7 : 4'hf; +//: assign rd_planar1_rd_mask = (is_last_loop & is_last_pburst & (img_p1_burst[1:0]==2'd0)) ? 4'h1 : +//: (is_last_loop & is_last_pburst & (img_p1_burst[1:0]==2'd1)) ? 4'h3 : +//: (is_last_loop & is_last_pburst & (img_p1_burst[1:0]==2'd2)) ? 4'h7 : 4'hf; +//: +//: assign rd_p0_vld = rd_vld & rd_rd_mask[0]; +//: assign rd_p1_vld = rd_vld & rd_rd_mask[1]; +//: assign rd_p2_vld = rd_vld & rd_rd_mask[2]; +//: assign rd_p3_vld = rd_vld & rd_rd_mask[3]; +//: +//: assign rd_idx_add = rd_rd_mask[3] ? 3'h4 : rd_rd_mask[2] ? 3'h3 : rd_rd_mask[1] ? 3'h2 : 3'h1; +//: ); +//: } +//: foreach my $i(0..$atmm_num -1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rd_p${i}_vld\" -q rd_p${i}_vld_d1"); +//: } +assign rd_rd_mask = rd_planar_cnt ? rd_planar1_rd_mask : rd_planar0_rd_mask; +//////// read address //////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: assign rd_p${i}_planar0_idx_inc = rd_p${i}_planar0_idx + rd_idx_add; +//: assign rd_p${i}_planar1_idx_inc = rd_p${i}_planar1_idx + rd_idx_add; +//: assign rd_p${i}_planar0_idx_w = is_first_running ? 7'b${i} : rd_p${i}_planar0_idx_inc[8 -2:0]; +//: assign rd_p${i}_planar1_idx_w = is_first_running ? 7'b${i} : rd_p${i}_planar1_idx_inc[8 -2:0]; +//: assign rd_p${i}_addr = (~rd_planar_cnt) ? {1'b0, rd_p${i}_planar0_idx[0], rd_p${i}_planar0_idx[8 -2:1]} : {1'b1, rd_p${i}_planar1_idx[0], rd_p${i}_planar1_idx[8 -2:1]}; +//: ); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar0_en\" -d \"rd_p${i}_planar0_idx_w\" -q rd_p${i}_planar0_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar1_en\" -d \"rd_p${i}_planar1_idx_w\" -q rd_p${i}_planar1_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar0_ori_en\" -d \"rd_p${i}_planar0_idx_w\" -q rd_p${i}_planar0_ori_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rd_planar1_ori_en\" -d \"rd_p${i}_planar1_idx_w\" -q rd_p${i}_planar1_ori_idx"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rd_p${i}_vld\" -d \"rd_p${i}_addr\" -q rd_p${i}_addr_d1"); +//: } +// assign rd_p0_planar0_idx_w = is_first_running ? 7'b0 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p0_planar0_ori_idx : +// rd_p0_planar0_idx_inc[8 -2:0]; +// assign rd_p1_planar0_idx_w = is_first_running ? 7'b1 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p1_planar0_ori_idx : +// rd_p1_planar0_idx_inc[8 -2:0]; +// +// assign rd_p0_planar1_idx_w = is_first_running ? 7'b0 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p0_planar1_ori_idx : +// rd_p0_planar1_idx_inc[8 -2:0]; +// assign rd_p1_planar1_idx_w = is_first_running ? 7'b1 : +// //(is_last_loop & is_last_pburst & ~is_last_sub_h) ? rd_p1_planar1_ori_idx : +// rd_p1_planar1_idx_inc[8 -2:0]; +assign rd_planar0_en = is_first_running | (rd_vld & ~rd_planar_cnt); +assign rd_planar1_en = is_first_running | (rd_vld & rd_planar_cnt); +assign rd_planar0_ori_en = is_first_running; +assign rd_planar1_ori_en = is_first_running; +//////// status logic ///////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: assign {mon_data_planar0_p${i}_cnt_w, data_planar0_p${i}_cnt_w} = data_planar0_cur_cnt + data_planar0_add * (${i}+1); +//: assign {mon_data_planar1_p${i}_cnt_w, data_planar1_p${i}_cnt_w} = data_planar1_cur_cnt + data_planar1_add * (${i}+1); +//: +//: assign data_planar0_p${i}_cur_flag[0] = (data_planar0_p${i}_cnt_w > data_width_mark_0); +//: assign data_planar0_p${i}_cur_flag[1] = (data_planar0_p${i}_cnt_w > data_width_mark_1); +//: assign data_planar0_p${i}_cur_flag[2] = (data_planar0_p${i}_cnt_w > data_width_mark_2); +//: assign data_planar1_p${i}_cur_flag[0] = (data_planar1_p${i}_cnt_w > data_width_mark_0); +//: assign data_planar1_p${i}_cur_flag[1] = (data_planar1_p${i}_cnt_w > data_width_mark_1); +//: assign data_planar1_p${i}_cur_flag[2] = (data_planar1_p${i}_cnt_w > data_width_mark_2); +//: +//: ); +//: } +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : data_planar0_p0_cnt_w; +//: assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : data_planar1_p0_cnt_w; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar0_p1_cnt_w : data_planar0_p0_cnt_w; +//: assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar1_p1_cnt_w : data_planar1_p0_cnt_w; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : (rd_p3_vld) ? data_planar0_p3_cnt_w : +//: (rd_p2_vld) ? data_planar0_p2_cnt_w : +//: (rd_p1_vld) ? data_planar0_p1_cnt_w : data_planar0_p0_cnt_w; +//: assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : (rd_p3_vld) ? data_planar1_p3_cnt_w : +//: (rd_p2_vld) ? data_planar1_p2_cnt_w : +//: (rd_p1_vld) ? data_planar1_p1_cnt_w : data_planar1_p0_cnt_w; +//: ); +//: } +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"data_planar0_en\" -d \"data_planar0_cur_cnt_w\" -q data_planar0_cur_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"data_planar1_en\" -d \"data_planar1_cur_cnt_w\" -q data_planar1_cur_cnt"); +///// assign data_planar0_cur_cnt_w = (is_first_running | rd_planar0_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar0_p1_cnt_w : data_planar0_p0_cnt_w; +///// assign data_planar1_cur_cnt_w = (is_first_running | rd_planar1_line_end) ? 14'b0 : (rd_p1_vld) ? data_planar1_p1_cnt_w : data_planar1_p0_cnt_w; +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 2) { +//: print qq( +//: assign data_planar0_p1_flag_w = (is_first_running | rd_planar0_line_end) ? 3'b0 : data_planar0_p1_cur_flag; +//: assign data_planar1_p1_flag_w = (is_first_running | rd_planar1_line_end) ? 3'b0 : data_planar1_p1_cur_flag; +//: ); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"data_planar0_en\" -d \"data_planar0_p1_flag_w\" -q data_planar0_p1_flag"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"data_planar1_en\" -d \"data_planar1_p1_flag_w\" -q data_planar1_p1_flag"); +//: } +/////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: wire [1:0] data_planar0_p0_flag_nex; +//: wire [1:0] data_planar1_p0_flag_nex; +//: wire [13:0] data_planar0_cnt_sub; +//: wire mon_data_planar0_cnt_sub; +//: assign {mon_data_planar0_cnt_sub,data_planar0_cnt_sub[13:0]} = (data_planar0_p0_cnt_w - {8'd0,data_planar0_add}); +//: assign data_planar0_p0_flag_nex[0] = data_planar0_cnt_sub > data_width_mark_0; +//: assign data_planar0_p0_flag_nex[1] = data_planar0_cnt_sub > data_width_mark_1; +//: //assign data_planar0_p0_flag_nex[0] = (data_planar0_p0_cnt_w - data_planar0_add) > data_width_mark_0; +//: //assign data_planar0_p0_flag_nex[1] = (data_planar0_p0_cnt_w - data_planar0_add) > data_width_mark_1; +//: assign data_planar0_p0_lp_mask = ~data_planar0_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: ~data_planar0_p0_flag_nex[0] ? ~({${atmm}{1'b1}} << lp_planar0_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar0_p0_rp_mask = ~data_planar0_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: ~data_planar0_p0_flag_nex[1] ? ({${atmm}{1'b1}} << rp_planar0_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar0_p0_zero_mask = ~data_planar0_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar0_mask_sft); +//: assign data_planar0_p0_pad_mask = (data_planar0_p0_lp_mask | data_planar0_p0_rp_mask) & ~data_planar0_p0_zero_mask; +//: +//: wire [13:0] data_planar1_cnt_sub; +//: wire mon_data_planar1_cnt_sub; +//: assign {mon_data_planar1_cnt_sub,data_planar1_cnt_sub[13:0]} = (data_planar1_p0_cnt_w - {8'd0,data_planar1_add}); +//: assign data_planar1_p0_flag_nex[0] = data_planar1_cnt_sub > data_width_mark_0; +//: assign data_planar1_p0_flag_nex[1] = data_planar1_cnt_sub > data_width_mark_1; +//: //assign data_planar1_p0_flag_nex[0] = (data_planar1_p0_cnt_w - data_planar1_add) > data_width_mark_0; +//: //assign data_planar1_p0_flag_nex[1] = (data_planar1_p0_cnt_w - data_planar1_add) > data_width_mark_1; +//: +//: assign data_planar1_p0_lp_mask = ~data_planar1_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: ~data_planar1_p0_flag_nex[0] ? ~({${atmm}{1'b1}} << lp_planar1_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar1_p0_rp_mask = ~data_planar1_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: ~data_planar1_p0_flag_nex[1] ? ({${atmm}{1'b1}} << rp_planar1_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar1_p0_zero_mask = ~data_planar1_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar1_mask_sft); +//: assign data_planar1_p0_pad_mask = (data_planar1_p0_lp_mask | data_planar1_p0_rp_mask) & ~data_planar1_p0_zero_mask; +//: ); +//: } elsif ($atmm_num == 2) { +//: print qq( +//: assign data_planar0_p0_lp_mask = ~data_planar0_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar0_p1_flag[0] & data_planar0_p0_cur_flag[0]) ? ~({${atmm}{1'b1}} << lp_planar0_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar0_p0_rp_mask = ~data_planar0_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar0_p1_flag[1] & data_planar0_p0_cur_flag[1]) ? ({${atmm}{1'b1}} << rp_planar0_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar0_p0_zero_mask = ~data_planar0_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar0_mask_sft); +//: assign data_planar0_p0_pad_mask = (data_planar0_p0_lp_mask | data_planar0_p0_rp_mask) & ~data_planar0_p0_zero_mask; +//: +//: assign data_planar0_p1_lp_mask = ~data_planar0_p1_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar0_p0_cur_flag[0] & data_planar0_p1_cur_flag[0]) ? ~({${atmm}{1'b1}} << lp_planar0_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar0_p1_rp_mask = ~data_planar0_p1_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar0_p0_cur_flag[1] & data_planar0_p1_cur_flag[1]) ? ({${atmm}{1'b1}} << rp_planar0_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar0_p1_zero_mask = ~data_planar0_p1_cur_flag[2] ? {${atmm}{1'b0}} : +//: data_planar0_p0_cur_flag[2] ? {${atmm}{1'b1}} : ({${atmm}{1'b1}} << zero_planar0_mask_sft); +//: assign data_planar0_p1_pad_mask = (data_planar0_p1_lp_mask | data_planar0_p1_rp_mask) & ~data_planar0_p1_zero_mask; +//: +//: assign data_planar1_p0_lp_mask = ~data_planar1_p0_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar1_p1_flag[0] ) ? ~({${atmm}{1'b1}} << lp_planar1_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar1_p0_rp_mask = ~data_planar1_p0_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar1_p1_flag[1] ) ? ({${atmm}{1'b1}} << rp_planar1_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar1_p0_zero_mask = ~data_planar1_p0_cur_flag[2] ? {${atmm}{1'b0}} : ({${atmm}{1'b1}} << zero_planar1_mask_sft); +//: assign data_planar1_p0_pad_mask = (data_planar1_p0_lp_mask | data_planar1_p0_rp_mask) & ~data_planar1_p0_zero_mask; +//: +//: assign data_planar1_p1_lp_mask = ~data_planar1_p1_cur_flag[0] ? {${atmm}{1'b1}} : +//: (~data_planar1_p0_cur_flag[0] & data_planar1_p1_cur_flag[0]) ? ~({${atmm}{1'b1}} << lp_planar1_mask_sft) : {${atmm}{1'b0}}; +//: assign data_planar1_p1_rp_mask = ~data_planar1_p1_cur_flag[1] ? {${atmm}{1'b0}} : +//: (~data_planar1_p0_cur_flag[1] & data_planar1_p1_cur_flag[1]) ? ({${atmm}{1'b1}} << rp_planar1_mask_sft) : {${atmm}{1'b1}}; +//: assign data_planar1_p1_zero_mask = ~data_planar1_p1_cur_flag[2] ? {${atmm}{1'b0}} : +//: data_planar1_p0_cur_flag[2] ? {${atmm}{1'b1}} : ({${atmm}{1'b1}} << zero_planar1_mask_sft); +//: assign data_planar1_p1_pad_mask = (data_planar1_p1_lp_mask | data_planar1_p1_rp_mask) & ~data_planar1_p1_zero_mask; +//: ); +//: } elsif ($atmm_num == 4) { +//: print qq( +//: ); +//: } +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: assign rd_p${i}_pad_mask = ~rd_planar_cnt ? data_planar0_p${i}_pad_mask : data_planar1_p${i}_pad_mask; +//: assign rd_p${i}_zero_mask = ~rd_planar_cnt ? data_planar0_p${i}_zero_mask : data_planar1_p${i}_zero_mask; +//: ); +//: &eperl::flop("-nodeclare -norst -en \"rd_vld\" -d \"rd_p${i}_pad_mask\" -q rd_p${i}_pad_mask_d1"); +//: &eperl::flop("-nodeclare -norst -en \"rd_vld\" -d \"rd_p${i}_zero_mask\" -q rd_p${i}_zero_mask_d1"); +//: print " //assign img2sbuf_p${i}_rd_en = rd_p${i}_vld_d1; \n"; +//: print " //assign img2sbuf_p${i}_rd_addr = rd_p${i}_addr_d1; \n"; +//: } +assign data_planar0_en = is_first_running | (rd_vld & ~rd_planar_cnt); +assign data_planar1_en = is_first_running | (rd_vld & rd_planar_cnt); +//assign data_planar0_ori_en = is_first_running; +//assign data_planar1_ori_en = is_first_running; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"rd_planar_cnt\" -q rd_planar_d1"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rd_vld\" -d \"rd_sub_h_cnt\" -q rd_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"rd_sub_h_end\" -q rd_sub_h_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"rd_loop_end\" -q rd_loop_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"(is_last_pburst & is_last_planar & is_last_loop & img_line_end)\" -q rd_one_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"is_1st_height\" -q rd_1st_height_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rd_vld\" -d \"img_layer_end & rd_height_end\" -q rd_layer_end_d1"); +//////////////////////////////////////////////////////////////////////// +// connect to shared buffer // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print " assign img2sbuf_p${i}_rd_en = rd_p${i}_vld_d1; \n"; +//: print " assign img2sbuf_p${i}_rd_addr = rd_p${i}_addr_d1; \n"; +//: } +//////////////////////////////////////////////////////////////////////// +// pipeline register for shared buffer read latency // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: my $i; +//: my $j; +//: my $limit = 1 + 2; +//: for($i = 1; $i < $limit; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"rd_vld_d${i}\" -q rd_vld_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_planar_d${i}\" -q rd_planar_d${j}"); +//: &eperl::flop("-wid 3 -rval \"{3{1'b0}}\" -en \"rd_vld_d${i}\" -d \"rd_sub_h_d${i}\" -q rd_sub_h_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_sub_h_end_d${i}\" -q rd_sub_h_end_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_loop_end_d${i}\" -q rd_loop_end_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_one_line_end_d${i}\" -q rd_one_line_end_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_1st_height_d${i}\" -q rd_1st_height_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"rd_vld_d${i}\" -d \"rd_layer_end_d${i}\" -q rd_layer_end_d${j}"); +//: foreach my $k (0..$atmm_num -1) { +//: &eperl::flop("-wid $atmm -norst -en \"rd_vld_d${i}\" -d \"rd_p${k}_pad_mask_d${i}\" -q rd_p${k}_pad_mask_d${j}"); +//: &eperl::flop("-wid $atmm -norst -en \"rd_vld_d${i}\" -d \"rd_p${k}_zero_mask_d${i}\" -q rd_p${k}_zero_mask_d${j}"); +//: } +//: } +//: +//: $i = $limit; +//: print qq ( +//: assign pk_rsp_vld = rd_vld_d${i}; +//: assign pk_rsp_planar = rd_planar_d${i}; +//: assign pk_rsp_sub_h = rd_sub_h_d${i}; +//: assign pk_rsp_sub_h_end = rd_sub_h_end_d${i}; +//: assign pk_rsp_loop_end = rd_loop_end_d${i}; +//: assign pk_rsp_one_line_end = rd_one_line_end_d${i}; +//: assign pk_rsp_1st_height = rd_1st_height_d${i}; +//: assign pk_rsp_layer_end = rd_layer_end_d${i}; +//: ); +//: foreach my $k (0..$atmm_num -1) { +//: print qq( +//: assign pk_rsp_p${k}_pad_mask = rd_p${k}_pad_mask_d${i}; +//: assign pk_rsp_p${k}_zero_mask = rd_p${k}_zero_mask_d${i}; +//: ); +//: } +assign pk_rsp_early_end = pixel_early_end & pk_rsp_one_line_end; +assign pk_rsp_vld_d1_w = pk_rsp_vld & pixel_planar & ~(pk_rsp_early_end); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pk_rsp_vld_d1_w\" -q pk_rsp_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_sub_h\" -q pk_rsp_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_sub_h_end\" -q pk_rsp_sub_h_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_loop_end\" -q pk_rsp_loop_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_one_line_end\" -q pk_rsp_one_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_1st_height\" -q pk_rsp_1st_height_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_vld_d1_w\" -d \"pk_rsp_layer_end\" -q pk_rsp_layer_end_d1"); +//////////////////////////////////////////////////////////////////////// +// connect to sbuf ram input // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $k (0..$atmm_num -1) { +//: print qq( +//: assign pk_rsp_p${k}_data = img2sbuf_p${k}_rd_data; +//: ); +//: } +//////////////////////////////////////////////////////////////////////// +// data write logic // +//////////////////////////////////////////////////////////////////////// +//////// control and status logic //////// +assign pk_rsp_pipe_sel = (~pixel_planar | (pk_rsp_vld & pk_rsp_early_end)); +assign pk_rsp_cur_vld = pk_rsp_pipe_sel ? pk_rsp_vld : pk_rsp_vld_d1; +assign pk_rsp_cur_sub_h = pk_rsp_pipe_sel ? pk_rsp_sub_h : pk_rsp_sub_h_d1; +assign pk_rsp_cur_sub_h_end = pk_rsp_pipe_sel ? pk_rsp_sub_h_end : pk_rsp_sub_h_end_d1; +assign pk_rsp_cur_loop_end = pk_rsp_pipe_sel ? pk_rsp_loop_end : pk_rsp_loop_end_d1; +assign pk_rsp_cur_one_line_end = pk_rsp_pipe_sel ? pk_rsp_one_line_end : pk_rsp_one_line_end_d1; +assign pk_rsp_cur_1st_height = pk_rsp_pipe_sel ? pk_rsp_1st_height : pk_rsp_1st_height_d1; +assign pk_rsp_cur_layer_end = pk_rsp_pipe_sel ? pk_rsp_layer_end : pk_rsp_layer_end_d1; +assign pk_rsp_wr_vld = pk_rsp_cur_vld; +assign {mon_pk_rsp_wr_cnt_w, + pk_rsp_wr_cnt_w} = (is_first_running | ~pk_rsp_planar) ? 3'b0 : pk_rsp_wr_cnt + 1'b1; +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"pk_rsp_vld\" -d \"pk_rsp_wr_cnt_w\" -q pk_rsp_wr_cnt"); +//assign pk_rsp_wr_size_ori = pixel_packed_10b ? 3'h4 : 3'h2; +//assign pk_rsp_wr_mask = pixel_packed_10b ? 4'hf : 4'h3; +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: print qq( +//: assign pk_rsp_wr_size_ori = 3'h${atmm_num};//3'h2 +//: assign pk_rsp_wr_mask = {{(4-${atmm_num}){1'b0}},{${atmm_num}{1'b1}}};//4'h3; +//: ); +////assign pk_rsp_wr_ext64 = (pk_rsp_cur_one_line_end & (pk_rsp_wr_sub_addr == 2'h2) & pixel_data_shrink & ~pixel_packed_10b); +////assign pk_rsp_wr_ext128 = (pk_rsp_cur_one_line_end & ~pk_rsp_wr_sub_addr[1] & (pixel_data_shrink | (~pixel_data_expand & ~pixel_packed_10b))); +////assign pk_out_interleave = 1'b0; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pk_rsp_wr_vld\" -q pk_out_vld"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_cur_sub_h\" -q pk_out_sub_h"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"pk_rsp_wr_mask\" -q pk_out_mask"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"is_first_running\" -d \"sg2pack_mn_enable\" -q pk_out_mean"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"is_first_running\" -d \"pixel_uint\" -q pk_out_uint"); +////: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_ext64\" -q pk_out_ext64"); +////: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_ext128\" -q pk_out_ext128"); +// PKT_PACK_WIRE( nvdla_ram_info , pk_out_ , pk_out_info_pd ) +assign pk_out_info_pd[3:0] = pk_out_mask[3:0]; +assign pk_out_info_pd[4] = 1'b0;//pk_out_interleave ; +assign pk_out_info_pd[5] = 1'b0;//pk_out_ext64 ; +assign pk_out_info_pd[6] = 1'b0;//pk_out_ext128 ; +assign pk_out_info_pd[7] = pk_out_mean ; +assign pk_out_info_pd[8] = pk_out_uint ; +assign pk_out_info_pd[11:9] = pk_out_sub_h[2:0]; +//////////////////////////////////////////////////////////////////////// +// data output logic // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign rdat = pk_rsp_p0_data; +//: assign mask_zero = {pk_rsp_p0_zero_mask}; +//: assign mask_pad = {pk_rsp_p0_pad_mask}; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rdat = {pk_rsp_p1_data, pk_rsp_p0_data}; +//: assign mask_zero = {pk_rsp_p1_zero_mask, pk_rsp_p0_zero_mask}; +//: assign mask_pad = {pk_rsp_p1_pad_mask, pk_rsp_p0_pad_mask}; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rdat = {pk_rsp_p3_data, pk_rsp_p2_data, pk_rsp_p1_data, pk_rsp_p0_data}; +//: assign mask_zero = {pk_rsp_p3_zero_mask, pk_rsp_p2_zero_mask, pk_rsp_p1_zero_mask, pk_rsp_p0_zero_mask}; +//: assign mask_pad = {pk_rsp_p3_pad_mask, pk_rsp_p2_pad_mask, pk_rsp_p1_pad_mask, pk_rsp_p0_pad_mask}; +//: ); +//: } +//assign z14 = 14'b0; +//assign z6 = 6'b0; +assign pk_rsp_dat_normal = rdat; +////assign pk_rsp_dat_ergb = {rdat[15*32+31:15*32+30], z14, rdat[15*32+29:15*32+20], z6, rdat[15*32+19:15*32+10], z6,rdat[15*32+9:15*32], z6, +//// rdat[14*32+31:14*32+30], z14, rdat[14*32+29:14*32+20], z6, rdat[14*32+19:14*32+10], z6,rdat[14*32+9:14*32], z6, +//// rdat[13*32+31:13*32+30], z14, rdat[13*32+29:13*32+20], z6, rdat[13*32+19:13*32+10], z6,rdat[13*32+9:13*32], z6, +//// rdat[12*32+31:12*32+30], z14, rdat[12*32+29:12*32+20], z6, rdat[12*32+19:12*32+10], z6,rdat[12*32+9:12*32], z6, +//// rdat[11*32+31:11*32+30], z14, rdat[11*32+29:11*32+20], z6, rdat[11*32+19:11*32+10], z6,rdat[11*32+9:11*32], z6, +//// rdat[10*32+31:10*32+30], z14, rdat[10*32+29:10*32+20], z6, rdat[10*32+19:10*32+10], z6,rdat[10*32+9:10*32], z6, +//// rdat[9*32+31:9*32+30], z14, rdat[9*32+29:9*32+20], z6, rdat[9*32+19:9*32+10], z6,rdat[9*32+9:9*32], z6, +//// rdat[8*32+31:8*32+30], z14, rdat[8*32+29:8*32+20], z6, rdat[8*32+19:8*32+10], z6,rdat[8*32+9:8*32], z6, +//// rdat[7*32+31:7*32+30], z14, rdat[7*32+29:7*32+20], z6, rdat[7*32+19:7*32+10], z6,rdat[7*32+9:7*32], z6, +//// rdat[6*32+31:6*32+30], z14, rdat[6*32+29:6*32+20], z6, rdat[6*32+19:6*32+10], z6,rdat[6*32+9:6*32], z6, +//// rdat[5*32+31:5*32+30], z14, rdat[5*32+29:5*32+20], z6, rdat[5*32+19:5*32+10], z6,rdat[5*32+9:5*32], z6, +//// rdat[4*32+31:4*32+30], z14, rdat[4*32+29:4*32+20], z6, rdat[4*32+19:4*32+10], z6,rdat[4*32+9:4*32], z6, +//// rdat[3*32+31:3*32+30], z14, rdat[3*32+29:3*32+20], z6, rdat[3*32+19:3*32+10], z6,rdat[3*32+9:3*32], z6, +//// rdat[2*32+31:2*32+30], z14, rdat[2*32+29:2*32+20], z6, rdat[2*32+19:2*32+10], z6,rdat[2*32+9:2*32], z6, +//// rdat[1*32+31:1*32+30], z14, rdat[1*32+29:1*32+20], z6, rdat[1*32+19:1*32+10], z6,rdat[1*32+9:1*32], z6, +//// rdat[0*32+31:0*32+30], z14, rdat[0*32+29:0*32+20], z6, rdat[0*32+19:0*32+10], z6,rdat[0*32+9:0*32], z6}; +/////: for(my $i = 0; $i < 16; $i ++) { +/////: my $b0 = sprintf("%3d", ($i * 64)); +/////: my $b1 = sprintf("%3d", ($i * 64 + 63)); +/////: my $b2 = $i * 4; +/////: print "assign pk_rsp_dat_mergb[${b1}:${b0}] = (~pixel_packed_10b | mask_zero[${b2}] | mask_pad[${b2}]) ? 64'b0 : pk_rsp_dat_ergb[${b1}:${b0}];\n"; +/////: } +/////: print "\n\n\n"; +/////: +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $ele_num = int($dmaif/$bpe); +//: for(my $i = 0; $i < $ele_num; $i ++) { +//: my $b0 = sprintf("%3d", ($i * $bpe)); +//: my $b1 = sprintf("%3d", ($i * $bpe + $bpe -1)); +//: print qq( assign pk_rsp_dat_mnorm[${b1}:${b0}] = (pixel_packed_10b | mask_zero[${i}] | mask_pad[${i}]) ? ${bpe}'b0 : pk_rsp_dat_normal[${b1}:${b0}]; \n); +//: } +//: print "\n\n\n"; +assign dat_l0 = pk_rsp_planar0_c0_d1; +assign dat_l1_lo = pk_rsp_planar1_c0_en ? pk_rsp_dat_mnorm : pk_rsp_planar1_c0_d1; +assign dat_l1_hi = pk_rsp_planar1_c1_en ? pk_rsp_dat_mnorm : pk_rsp_planar1_c1_d1; +assign dat_l1 = {dat_l1_hi, dat_l1_lo}; +assign dat_8b_yuv = { +//: my $bpe = 8; +//: my $dmaif = 64; +//: my $m = ($dmaif/$bpe); +//: foreach my $i(0..$m -2) { +//: my $k = $m -$i -1; +//: print " dat_l1[${k}*2*${bpe}+2*${bpe}-1:${k}*2*${bpe}], dat_l0[${k}*${bpe}+${bpe}-1:${k}*${bpe}], \n"; +//: } +//: print " dat_l1[2*${bpe}-1:0], dat_l0[${bpe}-1:0]}; \n"; +assign dat_yuv = dat_8b_yuv; +assign pk_rsp_out_sel[0] = (pixel_packed_10b); +assign pk_rsp_out_sel[1] = (~pixel_planar & ~pixel_packed_10b); +assign pk_rsp_out_sel[2] = (pixel_planar & (pk_rsp_wr_cnt == 2'h0)); +assign pk_rsp_out_sel[3] = (pixel_planar & (pk_rsp_wr_cnt == 2'h1)); +assign pk_rsp_out_sel[4] = (pixel_planar & (pk_rsp_wr_cnt == 2'h2)); +//assign pk_rsp_data_h1 = pk_rsp_dat_mergb[1023:512]; +assign pk_rsp_data_h0 = //({256*2{pk_rsp_out_sel[0]}} & pk_rsp_dat_mergb[511:0]) | + ({64{pk_rsp_out_sel[1]}} & pk_rsp_dat_mnorm) | + ({64{pk_rsp_out_sel[2]}} & dat_yuv[64 -1:0]) | + ({64{pk_rsp_out_sel[3]}} & dat_yuv[64*2-1:64]) | + ({64{pk_rsp_out_sel[4]}} & dat_yuv[64*3-1:64*2]); +assign pk_rsp_pad_mask_norm = mask_pad; +//assign pk_rsp_pad_mask_ergb = {{2{mask_pad[63]}}, {2{mask_pad[62]}}, {2{mask_pad[61]}}, {2{mask_pad[60]}}, {2{mask_pad[59]}}, {2{mask_pad[58]}}, {2{mask_pad[57]}}, {2{mask_pad[56]}}, {2{mask_pad[55]}}, {2{mask_pad[54]}}, {2{mask_pad[53]}}, {2{mask_pad[52]}}, {2{mask_pad[51]}}, {2{mask_pad[50]}}, {2{mask_pad[49]}}, {2{mask_pad[48]}}, {2{mask_pad[47]}}, {2{mask_pad[46]}}, {2{mask_pad[45]}}, {2{mask_pad[44]}}, {2{mask_pad[43]}}, {2{mask_pad[42]}}, {2{mask_pad[41]}}, {2{mask_pad[40]}}, {2{mask_pad[39]}}, {2{mask_pad[38]}}, {2{mask_pad[37]}}, {2{mask_pad[36]}}, {2{mask_pad[35]}}, {2{mask_pad[34]}}, {2{mask_pad[33]}}, {2{mask_pad[32]}}, {2{mask_pad[31]}}, {2{mask_pad[30]}}, {2{mask_pad[29]}}, {2{mask_pad[28]}}, {2{mask_pad[27]}}, {2{mask_pad[26]}}, {2{mask_pad[25]}}, {2{mask_pad[24]}}, {2{mask_pad[23]}}, {2{mask_pad[22]}}, {2{mask_pad[21]}}, {2{mask_pad[20]}}, {2{mask_pad[19]}}, {2{mask_pad[18]}}, {2{mask_pad[17]}}, {2{mask_pad[16]}}, {2{mask_pad[15]}}, {2{mask_pad[14]}}, {2{mask_pad[13]}}, {2{mask_pad[12]}}, {2{mask_pad[11]}}, {2{mask_pad[10]}}, {2{mask_pad[9]}}, {2{mask_pad[8]}}, {2{mask_pad[7]}}, {2{mask_pad[6]}}, {2{mask_pad[5]}}, {2{mask_pad[4]}}, {2{mask_pad[3]}}, {2{mask_pad[2]}}, {2{mask_pad[1]}}, {2{mask_pad[0]}}}; +assign pad_mask_l0 = mask_pad_planar0_c0_d1; +assign pad_mask_l1_lo = pk_rsp_planar1_c0_en ? mask_pad : mask_pad_planar1_c0_d1; +assign pad_mask_l1_hi = pk_rsp_planar1_c1_en ? mask_pad : mask_pad_planar1_c1_d1; +assign pad_mask_l1 = {pad_mask_l1_hi, pad_mask_l1_lo}; +assign pad_mask_8b_yuv = { +//: my $bpe = 8; +//: my $dmaif = 64; +//: my $m = ($dmaif/$bpe); +//: my $byte = 8/8; +//: foreach my $i(0..$m -2) { +//: my $k = $m -$i -1; +//: print " {pad_mask_l1[${k}*2*${byte}+2*${byte}-1:${k}*2*${byte}], pad_mask_l0[${k}*${byte}+${byte}-1:${k}*${byte}]}, \n"; +//: } +//: print " {pad_mask_l1[2*${byte}-1:0], pad_mask_l0[${byte}-1:0]}}; \n"; +assign pad_mask_yuv = pad_mask_8b_yuv; +//assign pk_rsp_pad_mask_h1 = pixel_packed_10b ? pk_rsp_pad_mask_ergb[127:64] : 64'b0; +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $ele_num = int( $dmaif/$bpe ); +//: print qq( +//: assign pk_rsp_pad_mask_h0 = //({64{pk_rsp_out_sel[0]}} & pk_rsp_pad_mask_ergb[63:0]) | +//: ({${ele_num}{pk_rsp_out_sel[1]}} & pk_rsp_pad_mask_norm) | +//: ({${ele_num}{pk_rsp_out_sel[2]}} & pad_mask_yuv[${ele_num}-1:0]) | +//: ({${ele_num}{pk_rsp_out_sel[3]}} & pad_mask_yuv[${ele_num}*2-1:${ele_num}]) | +//: ({${ele_num}{pk_rsp_out_sel[4]}} & pad_mask_yuv[${ele_num}*3-1:${ele_num}*2]); +//: ); +assign pk_rsp_planar0_c0_en = (pk_rsp_vld & pixel_planar & ~pk_rsp_planar); +assign pk_rsp_planar1_c0_en = (pk_rsp_vld & pixel_planar & pk_rsp_planar & (pk_rsp_wr_cnt == 2'h0)); +assign pk_rsp_planar1_c1_en = (pk_rsp_vld & pixel_planar & pk_rsp_planar & (pk_rsp_wr_cnt == 2'h1)); +assign pk_rsp_data_h0_en = pk_rsp_wr_vld; +//assign pk_rsp_data_h1_en = pk_rsp_wr_vld & pixel_packed_10b; +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $ele_num = int($dmaif/$bpe); +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"pk_rsp_planar0_c0_en\" -d \"pk_rsp_dat_mnorm\" -q pk_rsp_planar0_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"pk_rsp_planar1_c0_en\" -d \"pk_rsp_dat_mnorm\" -q pk_rsp_planar1_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"pk_rsp_planar1_c1_en\" -d \"pk_rsp_dat_mnorm\" -q pk_rsp_planar1_c1_d1"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_planar0_c0_en\" -d \"mask_pad\" -q mask_pad_planar0_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_planar1_c0_en\" -d \"mask_pad\" -q mask_pad_planar1_c0_d1"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_planar1_c1_en\" -d \"mask_pad\" -q mask_pad_planar1_c1_d1"); +//: &eperl::flop("-nodeclare -norst -en \"pk_rsp_data_h0_en\" -d \"pk_rsp_data_h0\" -q pk_out_data_h0"); +//: &eperl::flop("-nodeclare -rval \"{${ele_num}{1'b0}}\" -en \"pk_rsp_data_h0_en\" -d \"pk_rsp_pad_mask_h0\" -q pk_out_pad_mask_h0"); +// //: &eperl::flop("-nodeclare -norst -en \"pk_rsp_data_h1_en\" -d \"pk_rsp_data_h1\" -q pk_out_data_h1"); +// //: &eperl::flop("-nodeclare -rval \"{64{1'b0}}\" -en \"pk_rsp_data_h1_en | is_first_running\" -d \"pk_rsp_pad_mask_h1\" -q pk_out_pad_mask_h1"); +//assign pk_out_data = {pk_out_data_h1, pk_out_data_h0}; +assign pk_out_data = pk_out_data_h0; +//assign pk_out_pad_mask = {pk_out_pad_mask_h1, pk_out_pad_mask_h0}; +assign pk_out_pad_mask = pk_out_pad_mask_h0; +//////////////////////////////////////////////////////////////////////// +// mean data replacement and output logic // +//////////////////////////////////////////////////////////////////////// +assign mn_mask_y = mn_mask_y_d1; +assign mn_mask_uv_lo = mn_mask_uv_0_en ? mask_zero : mn_mask_uv_lo_d1; +assign mn_mask_uv_hi = mn_mask_uv_1_en ? mask_zero : mn_mask_uv_hi_d1; +assign mn_mask_uv = {mn_mask_uv_hi, mn_mask_uv_lo}; +assign mn_mask_yuv = { +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm-2) { +//: my $k = $atmm - $i -1; +//: print qq( +//: mn_mask_uv[${k}*2*${atmm_num}+2*${atmm_num}-1:${k}*2*${atmm_num}], mn_mask_y[${k}*${atmm_num}+${atmm_num}-1:${k}*${atmm_num}], +//: ); +//: } +//: print " mn_mask_uv[2*${atmm_num}-1:0], mn_mask_y[${atmm_num}-1:0]}; \n"; +//assign mn_ch1 = {64{reg2dp_mean_ry}}; +//assign mn_ch4 = {16{reg2dp_mean_ax, reg2dp_mean_bv, reg2dp_mean_gu, reg2dp_mean_ry}}; +//assign mn_ch3 = {64{reg2dp_mean_bv, reg2dp_mean_gu, reg2dp_mean_ry}}; +//: my $dmaif = 64; +//: my $bpe = 8; +//: my $bpe3 = (8*3); +//: my $Bnum = int($dmaif/$bpe); +//: print qq( +//: assign mn_ch1 = {${Bnum}{reg2dp_mean_ry[15:0]}}; +//: assign mn_ch4 = {(${Bnum}/4){reg2dp_mean_ax[15:0], reg2dp_mean_bv[15:0], reg2dp_mean_gu[15:0], reg2dp_mean_ry[15:0]}}; +//: assign mn_ch3 = {${Bnum}{reg2dp_mean_bv[15:0], reg2dp_mean_gu[15:0], reg2dp_mean_ry[15:0]}}; +//: assign mn_ch1_4 = ~(|reg2dp_datain_channel) ? mn_ch1 : mn_ch4; +//: ); +//: for(my $i = 0; $i < $Bnum; $i ++) { +//: print "assign mn_8b_mnorm[${i}*16+15:${i}*16] = mask_zero[${i}] ? 16'b0 : mn_ch1_4[${i}*16+15:${i}*16];\n"; +//: ## print "assign mn_8b_myuv[${i}*48+47:${i}*48] = mn_mask_yuv[${i}] ? 48'b0 : mn_ch3[${i}*48+47:${i}*48];\n"; +//: } +//: my $Bnum_3 = int( $Bnum * 3 ); +//: for(my $i = 0; $i < $Bnum_3; $i ++) { +//: print "assign mn_8b_myuv[${i}*16+15:${i}*16] = mn_mask_yuv[${i}] ? 16'b0 : mn_ch3[${i}*16+15:${i}*16];\n"; +//: } +//: print "\n\n\n"; +assign pk_rsp_mn_sel[0] = ~pixel_planar & (pixel_packed_10b | ~(|pixel_precision)); +assign pk_rsp_mn_sel[1] = ~pixel_planar & ~pixel_packed_10b & (|pixel_precision); +assign pk_rsp_mn_sel[2] = pixel_planar & (pk_rsp_wr_cnt == 2'h0) & ~(|pixel_precision); +assign pk_rsp_mn_sel[3] = pixel_planar & (pk_rsp_wr_cnt == 2'h0) & (|pixel_precision); +assign pk_rsp_mn_sel[4] = pixel_planar & (pk_rsp_wr_cnt == 2'h1) & ~(|pixel_precision); +assign pk_rsp_mn_sel[5] = pixel_planar & (pk_rsp_wr_cnt == 2'h1) & (|pixel_precision); +assign pk_rsp_mn_sel[6] = pixel_planar & (pk_rsp_wr_cnt == 2'h2) & ~(|pixel_precision); +assign pk_rsp_mn_sel[7] = pixel_planar & (pk_rsp_wr_cnt == 2'h2) & (|pixel_precision); +//assign pk_rsp_mn_data_h1 = ({256 *2{pk_rsp_mn_sel[0]}} & mn_8b_mnorm[1023:512]) | +// ({256 *2{pk_rsp_mn_sel[2]}} & mn_8b_myuv[1023:512]) | +// ({256 *2{pk_rsp_mn_sel[4]}} & mn_8b_myuv[2047:1536]) | +// ({256 *2{pk_rsp_mn_sel[6]}} & mn_8b_myuv[3071:2560]); +// +//: my $mn_bw = int(64 / 8) * 16 ; +//: print qq( +//: assign pk_rsp_mn_data_h0 = ({${mn_bw}{pk_rsp_mn_sel[0]}} & mn_8b_mnorm) | +//: ({${mn_bw}{pk_rsp_mn_sel[2]}} & mn_8b_myuv[${mn_bw}-1:0]) | +//: ({${mn_bw}{pk_rsp_mn_sel[4]}} & mn_8b_myuv[${mn_bw}*2-1:${mn_bw}]) | +//: ({${mn_bw}{pk_rsp_mn_sel[6]}} & mn_8b_myuv[${mn_bw}*3-1:${mn_bw}*2]); +//: ); +assign mn_mask_y_en = pk_rsp_planar0_c0_en; +assign mn_mask_uv_0_en = pk_rsp_planar1_c0_en; +assign mn_mask_uv_1_en = pk_rsp_planar1_c1_en; +assign pk_rsp_mn_data_h0_en = pk_rsp_wr_vld; +assign pk_rsp_mn_data_h1_en = (pk_rsp_wr_vld & (~(|pixel_precision) | pixel_packed_10b)); +//: my $Bnum = 64/8; +//: &eperl::flop("-nodeclare -rval \"{${Bnum}{1'b0}}\" -en \"mn_mask_y_en\" -d \"mask_zero\" -q mn_mask_y_d1"); +//: &eperl::flop("-nodeclare -rval \"{${Bnum}{1'b0}}\" -en \"mn_mask_uv_0_en\" -d \"mask_zero\" -q mn_mask_uv_lo_d1"); +//: &eperl::flop("-nodeclare -rval \"{${Bnum}{1'b0}}\" -en \"mn_mask_uv_1_en\" -d \"mask_zero\" -q mn_mask_uv_hi_d1"); +////: &eperl::flop("-nodeclare -norst -en \"pk_rsp_mn_data_h1_en\" -d \"pk_rsp_mn_data_h1\" -q pk_mn_out_data_h1"); +//: &eperl::flop("-nodeclare -norst -en \"pk_rsp_mn_data_h0_en\" -d \"pk_rsp_mn_data_h0\" -q pk_mn_out_data_h0"); +//assign pk_mn_out_data = {pk_mn_out_data_h1, pk_mn_out_data_h0}; +assign pk_mn_out_data = {pk_mn_out_data_h0}; +//////////////////////////////////////////////////////////////////////// +// cbuf write addresss generator // +//////////////////////////////////////////////////////////////////////// +//////// address base //////// +assign pk_rsp_wr_entries = pk_rsp_cur_1st_height ? sg2pack_entry_st : + pk_rsp_cur_layer_end ? sg2pack_entry_end : sg2pack_entry_mid; +assign pk_rsp_wr_slices = pk_rsp_cur_1st_height ? sg2pack_sub_h_st : + pk_rsp_cur_layer_end ? sg2pack_sub_h_end : sg2pack_sub_h_mid; +assign pk_rsp_wr_base_inc = is_first_running ? {1'b0, status2dma_wr_idx} : (pk_rsp_wr_base + pk_rsp_wr_entries); +assign is_base_wrap = (pk_rsp_wr_base_inc[15 : 9 ] >= {1'd0,pixel_bank}); +assign {mon_pk_rsp_wr_base_wrap[1:0], pk_rsp_wr_base_wrap} = (pk_rsp_wr_base_inc[15 : 9 ] - {1'b0,pixel_bank}); +assign pk_rsp_wr_base_w = is_base_wrap ? {pk_rsp_wr_base_wrap, pk_rsp_wr_base_inc[8 :0]} : pk_rsp_wr_base_inc[15 -1:0]; +assign pk_rsp_wr_base_en = is_first_running | (pk_rsp_wr_vld & pk_rsp_cur_one_line_end & pk_rsp_cur_sub_h_end); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_base_en\" -d \"pk_rsp_wr_base_w\" -q pk_rsp_wr_base"); +//////// h_offset //////// +assign {mon_pk_rsp_wr_h_offset_w, + pk_rsp_wr_h_offset_w} = (is_first_running | pk_rsp_cur_sub_h_end) ? 16'b0 : + pk_rsp_wr_h_offset + sg2pack_data_entries; +assign pk_rsp_wr_h_offset_en = is_first_running | (pk_rsp_wr_vld & pk_rsp_cur_loop_end); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_h_offset_en\" -d \"pk_rsp_wr_h_offset_w\" -q pk_rsp_wr_h_offset"); +///////// w_offset //////// +//assign pk_rsp_wr_w_add = pixel_data_shrink ? {1'b0, pk_rsp_wr_size_ori[2:1]} : +// pixel_data_expand ? {pk_rsp_wr_size_ori[1:0], 1'b0} : pk_rsp_wr_size_ori; +assign pk_rsp_wr_w_add = pk_rsp_wr_size_ori; +assign {mon_pk_rsp_wr_w_offset_w, + pk_rsp_wr_w_offset_w} = (is_first_running | (pk_rsp_cur_one_line_end & pk_rsp_cur_sub_h_end)) ? 15'b0 : + (pk_rsp_cur_loop_end & ~pk_rsp_cur_sub_h_end) ? pk_rsp_wr_w_offset_ori : + pk_rsp_wr_w_offset + pk_rsp_wr_w_add; +assign pk_rsp_wr_w_offset_en = is_first_running | pk_rsp_wr_vld; +assign pk_rsp_wr_w_offset_ori_en = is_first_running; +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_w_offset_en\" -d \"pk_rsp_wr_w_offset_w\" -q pk_rsp_wr_w_offset"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_w_offset_ori_en\" -d \"pk_rsp_wr_w_offset_w\" -q pk_rsp_wr_w_offset_ori"); +///////// total_address //////// +//: my $dmaif = (64/8); +//: my $atmc = 8; +//: my $atmm = 8; +//: my $Bnum = int( $dmaif/$atmm ); +//: my $Cnum = int( $atmc/$atmm ); +//: my $ss = int( log($Cnum)/log(2) ); +//: print qq( +//: assign pk_rsp_wr_addr_inc = pk_rsp_wr_base + pk_rsp_wr_h_offset + pk_rsp_wr_w_offset[14:${ss}]; +//: ); +//: if($ss > 0){ +//: print qq( +//: assign pk_rsp_wr_sub_addr = pk_rsp_wr_w_offset[${ss}-1:0]; +//: ); +//: ##} else { +//: ##print qq( +//: ##assign pk_rsp_wr_sub_addr = 2'd0; +//: ##); +//: } +//: +//: if($atmc > $dmaif){ +//: my $k = int( $atmc/$dmaif ); +//: if($k == 2) { +//: if($Bnum == 1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[0]\" -q pk_out_hsel"); +//: } elsif($Bnum == 2) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[1]\" -q pk_out_hsel"); +//: } elsif($Bnum == 4) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[2]\" -q pk_out_hsel"); +//: } +//: } elsif($k == 4) { +//: if($Bnum == 1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[1:0]\" -q pk_out_hsel[1:0]"); +//: } elsif($Bnum == 2) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[2:1]\" -q pk_out_hsel[1:0]"); +//: } elsif($Bnum == 4) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_sub_addr[3:2]\" -q pk_out_hsel[1:0]"); +//: } +//: } +//: } +assign is_addr_wrap = (pk_rsp_wr_addr_inc[15 +1: 9 ] >= {2'd0, pixel_bank}); +assign {mon_pk_rsp_wr_addr_wrap[2:0], pk_rsp_wr_addr_wrap} = (pk_rsp_wr_addr_inc[16 : 9 ] - {2'b0,pixel_bank}); +assign pk_rsp_wr_addr = is_addr_wrap ? {pk_rsp_wr_addr_wrap, pk_rsp_wr_addr_inc[8 :0]} : pk_rsp_wr_addr_inc[14:0]; +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_wr_vld\" -d \"pk_rsp_wr_addr\" -q pk_out_addr"); +//////////////////////////////////////////////////////////////////////// +// update status // +//////////////////////////////////////////////////////////////////////// +assign pk_rsp_data_updt = pk_rsp_wr_vld & pk_rsp_cur_one_line_end & pk_rsp_cur_sub_h_end; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pk_rsp_data_updt\" -q pk_out_data_updt"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"pk_rsp_data_updt\" -d \"pk_rsp_wr_entries\" -q pk_out_data_entries"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"pk_rsp_data_updt\" -d \"pk_rsp_wr_slices\" -q pk_out_data_slices"); +//////////////////////////////////////////////////////////////////////// +// output connection // +//////////////////////////////////////////////////////////////////////// +assign img2status_dat_updt = pk_out_data_updt; +assign img2status_dat_slices = {{10{1'b0}}, pk_out_data_slices}; +assign img2status_dat_entries = pk_out_data_entries; +assign img2cvt_dat_wr_en = pk_out_vld; +//assign img2cvt_dat_wr_addr = pk_out_addr; +//assign img2cvt_dat_wr_sel = pk_out_hsel; +//assign img2cvt_dat_wr_data = pk_out_data; +//assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; +assign img2cvt_dat_wr_info_pd = pk_out_info_pd; +//assign img2cvt_mn_wr_data = pk_mn_out_data; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: assign img2cvt_dat_wr_sel = pk_out_hsel; +//: assign img2cvt_dat_wr_addr = pk_out_addr; +//: assign img2cvt_dat_wr_data = pk_out_data; +//: assign img2cvt_mn_wr_data = pk_mn_out_data; +//: assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: assign img2cvt_dat_wr_mask = ?; // +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign img2cvt_dat_wr_addr${i} = img2cvt_dat_wr_addr${i} ;// +//: assign img2cvt_dat_wr_data${i} = img2cvt_dat_wr_data${i} ;// +//: assign img2cvt_mn_wr_data${i} = img2cvt_mn_wr_data${i} ;// +//: assign img2cvt_dat_wr_pad_mask${i} = img2cvt_dat_wr_pad_mask${i};// +//: ); +//: } +//: } else { +//: print qq( +//: assign img2cvt_dat_wr_addr = {2'd0,pk_out_addr}; +//: assign img2cvt_dat_wr_data = pk_out_data; +//: assign img2cvt_mn_wr_data = pk_mn_out_data; +//: assign img2cvt_dat_wr_pad_mask = pk_out_pad_mask; +//: ); +//: } +//////////////////////////////////////////////////////////////////////// +// global status // +//////////////////////////////////////////////////////////////////////// +assign pack_is_done_w = is_first_running ? 1'b0 : + pk_rsp_wr_vld & pk_rsp_cur_layer_end ? 1'b1 : pack_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"pack_is_done_w\" -q pack_is_done"); +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_img_pack__pk_rsp_wr_base_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (pk_rsp_wr_base_en & is_base_wrap); + endproperty +// Cover 0 : "(pk_rsp_wr_base_en & is_base_wrap)" + FUNCPOINT_cdma_img_pack__pk_rsp_wr_base_wrap__0_COV : cover property (cdma_img_pack__pk_rsp_wr_base_wrap__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_img_pack__pack_early_end__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (pk_rsp_vld & pk_rsp_early_end); + endproperty +// Cover 1 : "(pk_rsp_vld & pk_rsp_early_end)" + FUNCPOINT_cdma_img_pack__pack_early_end__1_COV : cover property (cdma_img_pack__pack_early_end__1_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_height_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_loop_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_pburst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_p0_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_p1_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar0_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_planar1_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_63x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_71x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar0_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_85x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar0_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_planar1_c1_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_h1_en | is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_h0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mn_mask_y_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mn_mask_uv_0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mn_mask_uv_1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_h_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_w_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_100x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_w_offset_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_104x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_wr_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_109x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pk_rsp_data_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! p0_burst and p1_burst mismatch!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (sg2pack_img_pvld & pixel_planar & (img_p0_burst * 2 != img_p1_burst) & (img_p0_burst * 2 != img_p1_burst + 1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! layer_end signal conflict with local cnt!") zzz_assert_never_14x (nvdla_core_clk, `ASSERT_RESET, (rd_line_end & (is_last_height ^ img_layer_end))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rd_sub_h_limit is overflow!") zzz_assert_never_16x (nvdla_core_clk, `ASSERT_RESET, (mon_rd_sub_h_limit & is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rd_loop_cnt_limit is overflow!") zzz_assert_never_17x (nvdla_core_clk, `ASSERT_RESET, (mon_rd_loop_cnt_limit & is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p0_cnt_w is overflow!") zzz_assert_never_45x (nvdla_core_clk, `ASSERT_RESET, (data_planar0_en & mon_data_planar0_p0_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p1_cnt_w is overflow!") zzz_assert_never_46x (nvdla_core_clk, `ASSERT_RESET, (data_planar0_en & mon_data_planar0_p1_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p0_cnt_w is overflow!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (data_planar1_en & mon_data_planar1_p0_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p1_cnt_w is overflow!") zzz_assert_never_48x (nvdla_core_clk, `ASSERT_RESET, (data_planar1_en & mon_data_planar1_p1_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p0_cur_flag invalid!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & ~rd_planar_cnt & data_planar0_p0_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar0_p1_cur_flag invalid!") zzz_assert_never_50x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & ~rd_planar_cnt & data_planar0_p1_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p0_cur_flag invalid!") zzz_assert_never_51x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & rd_planar_cnt & data_planar1_p0_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! data_planar1_p1_cur_flag invalid!") zzz_assert_never_52x (nvdla_core_clk, `ASSERT_RESET, (rd_vld & rd_planar_cnt & data_planar1_p1_cur_flag[2] & ~img_line_end)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_cnt is overflow!") zzz_assert_never_80x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_vld & mon_pk_rsp_wr_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_cnt is out of range!") zzz_assert_never_81x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_vld & (pk_rsp_wr_cnt > 2'h2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_base_wrap is overflow!") zzz_assert_never_94x (nvdla_core_clk, `ASSERT_RESET, (is_base_wrap & (|mon_pk_rsp_wr_base_wrap) & pk_rsp_wr_base_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_base_w is out of range!") zzz_assert_never_95x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_base_en & (pk_rsp_wr_base_w >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_h_offset_w is overflow!") zzz_assert_never_97x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_h_offset_en & mon_pk_rsp_wr_h_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_h_offset_w is out of range!") zzz_assert_never_98x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_h_offset_en & (pk_rsp_wr_h_offset_w >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_w_offset_w is overflow!") zzz_assert_never_101x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_w_offset_en & mon_pk_rsp_wr_w_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_w_offset_w is out of range!") zzz_assert_never_102x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_w_offset_en & (pk_rsp_wr_w_offset_w[13:2] >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! store 16 bytes when not line end!") zzz_assert_never_103x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_w_offset_en & ~pk_rsp_cur_one_line_end & ~(|pk_rsp_wr_w_add))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_addr_wrap is overflow!") zzz_assert_never_106x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_vld & is_addr_wrap & (|mon_pk_rsp_wr_addr_wrap))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_addr is out of range!") zzz_assert_never_107x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_vld & (pk_rsp_wr_addr >= 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pk_rsp_wr_sub_addr conflict with pk_rsp_wr_w_add!") zzz_assert_never_108x (nvdla_core_clk, `ASSERT_RESET, (pk_rsp_wr_vld & (pk_rsp_wr_w_add + pk_rsp_wr_sub_addr > 4'h4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! pack_is_done cleared when idle!") zzz_assert_never_111x (nvdla_core_clk, `ASSERT_RESET, (~pack_is_done & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_IMG_pack diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v new file mode 100644 index 0000000..a6370e9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v @@ -0,0 +1,2460 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_sg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_IMG_sg ( + nvdla_core_clk + ,nvdla_core_rstn + ,img2status_dat_entries + ,img2status_dat_updt + ,img_dat2mcif_rd_req_ready + ,is_running + ,layer_st + ,mcif2img_dat_rd_rsp_pd + ,mcif2img_dat_rd_rsp_valid + ,pixel_order + ,pixel_planar + ,pixel_planar0_bundle_limit + ,pixel_planar0_bundle_limit_1st + ,pixel_planar0_byte_sft + ,pixel_planar0_lp_burst + ,pixel_planar0_lp_vld + ,pixel_planar0_rp_burst + ,pixel_planar0_rp_vld + ,pixel_planar0_width_burst + ,pixel_planar1_bundle_limit + ,pixel_planar1_bundle_limit_1st + ,pixel_planar1_byte_sft + ,pixel_planar1_lp_burst + ,pixel_planar1_lp_vld + ,pixel_planar1_rp_burst + ,pixel_planar1_rp_vld + ,pixel_planar1_width_burst + ,pwrbus_ram_pd + ,reg2dp_datain_addr_high_0 + ,reg2dp_datain_addr_high_1 + ,reg2dp_datain_addr_low_0 + ,reg2dp_datain_addr_low_1 + ,reg2dp_datain_height + ,reg2dp_datain_ram_type + ,reg2dp_dma_en + ,reg2dp_entries + ,reg2dp_line_stride + ,reg2dp_mean_format + ,reg2dp_op_en + ,reg2dp_pixel_y_offset + ,reg2dp_uv_line_stride + ,sg2pack_img_prdy + ,status2dma_free_entries + ,status2dma_fsm_switch + ,dp2reg_img_rd_latency + ,dp2reg_img_rd_stall +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,img2sbuf_p${i}_wr_addr +//: ,img2sbuf_p${i}_wr_data +//: ,img2sbuf_p${i}_wr_en +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,img2sbuf_p0_wr_addr +,img2sbuf_p0_wr_data +,img2sbuf_p0_wr_en + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,img_dat2mcif_rd_req_pd + ,img_dat2mcif_rd_req_valid + ,mcif2img_dat_rd_rsp_ready + ,sg2pack_data_entries + ,sg2pack_entry_end + ,sg2pack_entry_mid + ,sg2pack_entry_st + ,sg2pack_height_total + ,sg2pack_img_pd + ,sg2pack_img_pvld + ,sg2pack_mn_enable + ,sg2pack_sub_h_end + ,sg2pack_sub_h_mid + ,sg2pack_sub_h_st + ,sg_is_done + ); +////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +output [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +output img_dat2mcif_rd_req_valid; +input img_dat2mcif_rd_req_ready; +input [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +input mcif2img_dat_rd_rsp_valid; +output mcif2img_dat_rd_rsp_ready; +input [14:0] img2status_dat_entries; +input img2status_dat_updt; +input is_running; +input layer_st; +input [10:0] pixel_order; +input pixel_planar; +input [3:0] pixel_planar0_bundle_limit; +input [3:0] pixel_planar0_bundle_limit_1st; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: input [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: input [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [3-1:0] pixel_planar0_byte_sft; +input [3-1:0] pixel_planar1_byte_sft; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [3:0] pixel_planar0_lp_burst; +input pixel_planar0_lp_vld; +input [3:0] pixel_planar0_rp_burst; +input pixel_planar0_rp_vld; +input [13:0] pixel_planar0_width_burst; +input [4:0] pixel_planar1_bundle_limit; +input [4:0] pixel_planar1_bundle_limit_1st; +input [2:0] pixel_planar1_lp_burst; +input pixel_planar1_lp_vld; +input [2:0] pixel_planar1_rp_burst; +input pixel_planar1_rp_vld; +input [13:0] pixel_planar1_width_burst; +input [31:0] pwrbus_ram_pd; +input reg2dp_op_en; +input sg2pack_img_prdy; +input [14:0] status2dma_free_entries; +input status2dma_fsm_switch; +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: output [7:0] img2sbuf_p${i}_wr_addr; +//: output [${atmm}-1:0] img2sbuf_p${i}_wr_data; +//: output img2sbuf_p${i}_wr_en; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [7:0] img2sbuf_p0_wr_addr; +output [64-1:0] img2sbuf_p0_wr_data; +output img2sbuf_p0_wr_en; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [14:0] sg2pack_data_entries; +output [14:0] sg2pack_entry_end; +output [14:0] sg2pack_entry_mid; +output [14:0] sg2pack_entry_st; +output [12:0] sg2pack_height_total; +output [10:0] sg2pack_img_pd; +output sg2pack_img_pvld; +output sg2pack_mn_enable; +output [3:0] sg2pack_sub_h_end; +output [3:0] sg2pack_sub_h_mid; +output [3:0] sg2pack_sub_h_st; +output sg_is_done; +input [2:0] reg2dp_pixel_y_offset; +input [12:0] reg2dp_datain_height; +input [0:0] reg2dp_datain_ram_type; +input [31:0] reg2dp_datain_addr_high_0; +input [31:0] reg2dp_datain_addr_low_0; +input [31:0] reg2dp_datain_addr_high_1; +input [31:0] reg2dp_datain_addr_low_1; +input [31:0] reg2dp_line_stride; +input [31:0] reg2dp_uv_line_stride; +input [0:0] reg2dp_mean_format; +input [13:0] reg2dp_entries; +input [0:0] reg2dp_dma_en; +output [31:0] dp2reg_img_rd_stall; +output [31:0] dp2reg_img_rd_latency; +////////////////////////////////////////////////////////// +reg [14:0] data_entries; +reg [13:0] data_height; +reg [4:0] dma_rsp_size_cnt; +reg [31:0] dp2reg_img_rd_latency; +reg [31:0] dp2reg_img_rd_stall; +reg [12:0] height_cnt_total; +reg [14:0] img_entry_onfly; +reg img_rd_latency_cen; +reg img_rd_latency_clr; +reg img_rd_latency_dec; +reg img_rd_latency_inc; +reg img_rd_stall_cen; +reg img_rd_stall_clr; +reg img_rd_stall_inc; +reg is_cbuf_ready; +reg is_running_d1; +reg ltc_1_adv; +reg [8:0] ltc_1_cnt_cur; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg ltc_2_adv; +reg [31:0] ltc_2_cnt_cur; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg mn_enable_d1; +reg [14:0] pre_entry_end_d1; +reg [14:0] pre_entry_mid_d1; +reg [14:0] pre_entry_st_d1; +reg [63:0] req_addr_d1; +reg req_bundle_end_d1; +reg req_end_d1; +reg req_grant_end_d1; +reg [12:0] req_height_cnt; +reg [63:0] req_img_p0_addr_base; +reg [3:0] req_img_p0_bundle_cnt; +reg [13:0] req_img_p0_burst_cnt; +reg [28:0] req_img_p0_burst_offset; +reg [31:0] req_img_p0_line_offset; +reg [1:0] req_img_p0_sec_cnt; +reg [63:0] req_img_p1_addr_base; +reg [4:0] req_img_p1_bundle_cnt; +reg [13:0] req_img_p1_burst_cnt; +reg [28:0] req_img_p1_burst_offset; +reg [31:0] req_img_p1_line_offset; +reg [1:0] req_img_p1_sec_cnt; +reg req_img_planar_cnt; +reg req_is_done; +reg req_is_dummy_d1; +reg req_line_end_d1; +reg req_line_st_d1; +reg req_planar_d1; +reg [4:0] req_size_d1; +reg [4:0] req_size_out_d1; +reg req_valid; +reg req_valid_d1; +reg rsp_img_1st_burst; +reg rsp_img_bundle_done_d1; +reg rsp_img_bundle_end; +reg [8*8 -1:0] rsp_img_c0l0; +reg [8*8 -1:0] rsp_img_c1l0; +reg rsp_img_end; +reg rsp_img_is_done; +reg rsp_img_layer_end_d1; +reg rsp_img_line_end; +reg rsp_img_line_end_d1; +reg rsp_img_line_st; +reg [7:0] rsp_img_p0_addr_d1; +reg [3:0] rsp_img_p0_burst_cnt; +reg [3:0] rsp_img_p0_burst_size_d1; +reg [8*8 -1:0] rsp_img_p0_data; +reg [8*8 -1:0] rsp_img_p0_data_d1; +reg [6:0] rsp_img_p0_planar0_idx; +reg [6:0] rsp_img_p0_planar1_idx; +reg rsp_img_p0_vld; +reg rsp_img_p0_vld_d1; +reg [7:0] rsp_img_p1_addr_d1; +reg [4:0] rsp_img_p1_burst_cnt; +reg [4:0] rsp_img_p1_burst_size_d1; +reg [8*8 -1:0] rsp_img_p1_data; +reg [8*8 -1:0] rsp_img_p1_data_d1; +reg [6:0] rsp_img_p1_planar0_idx; +reg [6:0] rsp_img_p1_planar1_idx; +reg rsp_img_p1_vld; +reg rsp_img_p1_vld_d1; +reg rsp_img_planar; +reg rsp_img_req_end; +reg rsp_img_vld; +reg [4:0] rsp_img_w_burst_size; +reg sg_is_done; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire [14:0] cur_required_entry; +wire [14:0] data_entries_w; +wire [13:0] data_height_w; +wire dma_blocking; +wire [63:0] dma_rd_req_addr; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [14:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire [64 -1:0] dma_rd_rsp_data; +wire [(64/8/8)-1:0] dma_rd_rsp_mask; +wire [( 64 + (64/8/8) )-1:0] dma_rd_rsp_pd; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [10:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire dma_rsp_blocking; +wire dma_rsp_bundle_end; +wire dma_rsp_dummy; +wire dma_rsp_end; +wire [10:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire dma_rsp_line_end; +wire dma_rsp_line_st; +wire [1:0] dma_rsp_mask; +wire dma_rsp_planar; +wire [4:0] dma_rsp_size; +wire [4:0] dma_rsp_size_cnt_inc; +wire [4:0] dma_rsp_size_cnt_w; +wire dma_rsp_vld; +wire [4:0] dma_rsp_w_burst_size; +wire dp2reg_img_rd_stall_dec; +wire [14:0] img_entry_onfly_add; +wire img_entry_onfly_en; +wire [14:0] img_entry_onfly_sub; +wire [14:0] img_entry_onfly_w; +wire is_1st_height; +wire is_cbuf_enough; +wire is_cbuf_ready_w; +wire is_first_running; +wire is_img_1st_burst; +wire is_img_bundle_end; +wire is_img_dummy; +wire is_img_last_burst; +wire is_img_last_planar; +wire is_last_height; +wire is_last_req; +wire is_p0_1st_burst; +wire is_p0_bundle_end; +wire is_p0_cur_sec_end; +wire is_p0_last_burst; +wire is_p0_req_real; +wire is_p1_1st_burst; +wire is_p1_bundle_end; +wire is_p1_cur_sec_end; +wire is_p1_last_burst; +wire is_p1_req_real; +wire ltc_1_dec; +wire ltc_1_inc; +wire ltc_2_dec; +wire ltc_2_inc; +wire mn_enable; +wire mon_data_entries_w; +wire mon_dma_rsp_size_cnt_inc; +wire mon_img_entry_onfly_w; +wire [3:0] mon_pre_entry_end_w; +wire [3:0] mon_pre_entry_st_w; +wire mon_req_height_cnt_inc; +wire mon_req_img_p0_addr; +wire mon_req_img_p0_bundle_cnt_w; +wire mon_req_img_p0_burst_offset_w; +wire mon_req_img_p0_line_offset_w; +wire mon_req_img_p0_sec_cnt_w; +wire mon_req_img_p1_addr; +wire mon_req_img_p1_bundle_cnt_w; +wire mon_req_img_p1_burst_offset_w; +wire mon_req_img_p1_line_offset_w; +wire mon_req_img_p1_sec_cnt_w; +wire mon_req_size_out; +wire mon_rsp_img_p0_burst_cnt_inc; +wire [8*8 -1:0] mon_rsp_img_p0_data_d1_w; +wire mon_rsp_img_p1_burst_cnt_inc; +wire [8*8 -1:0] mon_rsp_img_p1_data_d1_w; +wire mon_total_required_entry; +reg [8:0] outs_dp2reg_img_rd_latency; +wire planar1_enable; +wire [14:0] pre_entry_end_w; +wire [14:0] pre_entry_st_w; +reg [3:0] pre_sub_h_end_d1; +reg [3:0] pre_sub_h_mid_d1; +reg [3:0] pre_sub_h_st_d1; +wire rd_req_rdyi; +wire [63:0] req_addr; +wire req_adv; +wire req_bundle_end; +wire req_grant_end; +wire [12:0] req_height_cnt_inc; +wire [12:0] req_height_cnt_w; +wire req_height_en; +wire [4:0] req_img_burst_size; +wire [63:0] req_img_p0_addr; +wire [63:0] req_img_p0_addr_base_w; +wire [3:0] req_img_p0_bundle_cnt_w; +wire [14:0] req_img_p0_burst_cnt_dec; +wire [13:0] req_img_p0_burst_cnt_w; +wire req_img_p0_burst_en; +wire req_img_p0_burst_offset_en; +wire [28:0] req_img_p0_burst_offset_w; +wire [3:0] req_img_p0_burst_size; +wire [3:0] req_img_p0_cur_burst; +wire [31:0] req_img_p0_line_offset_w; +wire [1:0] req_img_p0_sec_cnt_w; +wire req_img_p0_sec_en; +wire [63:0] req_img_p1_addr; +wire [63:0] req_img_p1_addr_base_w; +wire [4:0] req_img_p1_bundle_cnt_w; +wire [14:0] req_img_p1_burst_cnt_dec; +wire [13:0] req_img_p1_burst_cnt_w; +wire req_img_p1_burst_en; +wire req_img_p1_burst_offset_en; +wire [28:0] req_img_p1_burst_offset_w; +wire [4:0] req_img_p1_burst_size; +wire [4:0] req_img_p1_cur_burst; +wire [31:0] req_img_p1_line_offset_w; +wire [1:0] req_img_p1_sec_cnt_w; +wire req_img_p1_sec_en; +wire req_img_planar_cnt_w; +wire req_img_planar_en; +wire req_img_reg_en; +wire req_is_done_w; +wire req_is_dummy; +wire req_line_end; +wire req_line_st; +wire req_ready_d1; +wire req_reg_en; +wire [4:0] req_size; +wire [4:0] req_size_out; +wire req_valid_d1_w; +wire req_valid_w; +wire [64 -1:0] rsp_dat; +wire rsp_img_1st_burst_w; +wire rsp_img_bundle_done; +wire rsp_img_c0l0_wr_en; +wire rsp_img_c1l0_wr_en; +wire [64 -1:0] rsp_img_data_sw_o0; +wire [64 -1:0] rsp_img_data_sw_o1; +wire [64 -1:0] rsp_img_data_sw_o3; +wire [64 -1:0] rsp_img_data_sw_o5; +wire [64 -1:0] rsp_img_data_sw_o9; +wire rsp_img_is_done_w; +wire [8*8 -1:0] rsp_img_l0_data; +wire [7:0] rsp_img_p0_addr; +wire rsp_img_p0_burst_cnt_en; +wire [3:0] rsp_img_p0_burst_cnt_inc; +wire [3:0] rsp_img_p0_burst_cnt_w; +wire rsp_img_p0_burst_size_en; +wire [3:0] rsp_img_p0_burst_size_w; +reg [8*8 -1:0] rsp_img_p0_cache_data; +reg [8*8 -1:0] rsp_img_p1_cache_data; +wire [8*8 -1:0] rsp_img_p0_data_d1_w; +wire [8*8 -1:0] rsp_img_p0_data_atmm1; +wire [8*8 -1:0] rsp_img_p0_data_atmm0; +wire [8*8 -1:0] rsp_img_p0_data_w; +wire rsp_img_p0_planar0_en; +wire [7:0] rsp_img_p0_planar0_idx_inc; +wire [6:0] rsp_img_p0_planar0_idx_w; +wire rsp_img_p0_planar1_en; +wire [7:0] rsp_img_p0_planar1_idx_inc; +wire [6:0] rsp_img_p0_planar1_idx_w; +wire rsp_img_p0_vld_d1_w; +wire rsp_img_p0_vld_w; +wire [7:0] rsp_img_p1_addr; +wire rsp_img_p1_burst_cnt_en; +wire [4:0] rsp_img_p1_burst_cnt_inc; +wire [4:0] rsp_img_p1_burst_cnt_w; +wire rsp_img_p1_burst_size_en; +wire [4:0] rsp_img_p1_burst_size_w; +wire [8*8 -1:0] rsp_img_p1_data_d1_w; +wire [8*8 -1:0] rsp_img_p1_data_w; +wire rsp_img_p1_planar0_en; +wire [7:0] rsp_img_p1_planar0_idx_inc; +wire [6:0] rsp_img_p1_planar0_idx_w; +wire rsp_img_p1_planar1_en; +wire [7:0] rsp_img_p1_planar1_idx_inc; +wire [6:0] rsp_img_p1_planar1_idx_w; +wire rsp_img_p1_vld_d1_w; +wire rsp_img_p1_vld_w; +wire [2:0] rsp_img_planar_idx_add; +wire [10:0] rsp_img_sel; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: wire [${atmmbw}-1:0] rsp_img_sft; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [3-1:0] rsp_img_sft; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire rsp_img_vld_w; +wire sg2pack_img_layer_end; +wire sg2pack_img_line_end; +wire [3:0] sg2pack_img_p0_burst; +wire [4:0] sg2pack_img_p1_burst; +wire [10:0] sg2pack_pop_data; +wire sg2pack_pop_ready; +wire sg2pack_pop_req; +wire [10:0] sg2pack_push_data; +wire sg2pack_push_ready; +wire sg2pack_push_req; +wire sg_is_done_w; +wire [3:0] sub_h_end_limit; +wire sub_h_end_sel; +wire [3:0] sub_h_end_w; +wire [3:0] sub_h_mid_w; +wire [3:0] sub_h_st_limit; +wire sub_h_st_sel; +wire [3:0] sub_h_st_w; +wire [14:0] total_required_entry; +//////////////////////////////////////////////////////////////////////// +// general signal // +//////////////////////////////////////////////////////////////////////// +assign planar1_enable = pixel_planar; +assign data_height_w = reg2dp_datain_height + 1'b1; +assign mn_enable = (reg2dp_mean_format == 1'h1 ); +assign {mon_data_entries_w, data_entries_w} = reg2dp_entries + 1'b1; +assign is_first_running = is_running & ~is_running_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"mn_enable\" -q mn_enable_d1"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_height_w\" -q data_height"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"reg2dp_datain_height\" -q height_cnt_total"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"layer_st\" -d \"data_entries_w\" -q data_entries"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_running_d1 <= 1'b0; + end else begin + is_running_d1 <= is_running; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mn_enable_d1 <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + mn_enable_d1 <= mn_enable; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + mn_enable_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_height <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_height <= data_height_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_height <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + height_cnt_total <= {13{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + height_cnt_total <= reg2dp_datain_height; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + height_cnt_total <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_entries <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_entries <= data_entries_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_entries <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// generator preparing parameters // +//////////////////////////////////////////////////////////////////////// +///////////// sub_h for total control ///////////// +assign sub_h_st_limit = 4'b1; +assign sub_h_mid_w = 4'h1; +assign sub_h_end_limit = 4'h1; +assign sub_h_st_sel = (~(|data_height[13:4]) && (data_height[3:0] <= sub_h_st_limit)); +assign sub_h_end_sel = (~(|data_height[13:4]) && (data_height[3:0] <= sub_h_end_limit)); +assign sub_h_st_w = sub_h_st_sel ? data_height[3:0] : sub_h_st_limit; +assign sub_h_end_w = sub_h_end_sel ? data_height[3:0] : sub_h_end_limit; +assign {mon_pre_entry_st_w, pre_entry_st_w} = sub_h_st_w * data_entries; +assign {mon_pre_entry_end_w, pre_entry_end_w} = sub_h_end_w * data_entries; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"sub_h_st_w\" -q pre_sub_h_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"sub_h_mid_w\" -q pre_sub_h_mid_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"sub_h_end_w\" -q pre_sub_h_end_d1"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"is_first_running\" -d \"pre_entry_st_w\" -q pre_entry_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"is_first_running\" -d \"data_entries\" -q pre_entry_mid_d1"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"is_first_running\" -d \"pre_entry_end_w\" -q pre_entry_end_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_sub_h_st_d1 <= {4{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pre_sub_h_st_d1 <= sub_h_st_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pre_sub_h_st_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_sub_h_mid_d1 <= {4{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pre_sub_h_mid_d1 <= sub_h_mid_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pre_sub_h_mid_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_sub_h_end_d1 <= {4{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pre_sub_h_end_d1 <= sub_h_end_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pre_sub_h_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_entry_st_d1 <= {15{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pre_entry_st_d1 <= pre_entry_st_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pre_entry_st_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_entry_mid_d1 <= {15{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pre_entry_mid_d1 <= data_entries; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pre_entry_mid_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_entry_end_d1 <= {15{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + pre_entry_end_d1 <= pre_entry_end_w; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + pre_entry_end_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// request generator for input image // +//////////////////////////////////////////////////////////////////////// +localparam SRC_DUMMY = 2'h0; +localparam SRC_P0 = 2'h1; +localparam SRC_P1 = 2'h2; +///////////// height counter ///////////// +assign is_1st_height = ~(|req_height_cnt); +assign is_last_height = (req_height_cnt == height_cnt_total); +assign {mon_req_height_cnt_inc, req_height_cnt_inc} = req_height_cnt + 1'b1; +assign req_height_cnt_w = is_first_running ? 13'b0 : req_height_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"req_height_en\" -d \"req_height_cnt_w\" -q req_height_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_height_cnt <= {13{1'b0}}; + end else begin + if ((req_height_en) == 1'b1) begin + req_height_cnt <= req_height_cnt_w; + // VCS coverage off + end else if ((req_height_en) == 1'b0) begin + end else begin + req_height_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// image planar count ///////////// +assign is_img_last_planar = (req_img_planar_cnt == pixel_planar); +assign req_img_planar_cnt_w = (is_first_running | is_img_last_planar) ? 1'b0 : ~req_img_planar_cnt; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_img_planar_en\" -d \"req_img_planar_cnt_w\" -q req_img_planar_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_planar_cnt <= 1'b0; + end else begin + if ((req_img_planar_en) == 1'b1) begin + req_img_planar_cnt <= req_img_planar_cnt_w; + // VCS coverage off + end else if ((req_img_planar_en) == 1'b0) begin + end else begin + req_img_planar_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// image planar 0 bundle and burst count ///////////// +assign {mon_req_img_p0_bundle_cnt_w, + req_img_p0_bundle_cnt_w} = (is_first_running | is_p0_last_burst) ? {1'b0, pixel_planar0_bundle_limit_1st} : + is_p0_bundle_end ? {1'b0, pixel_planar0_bundle_limit} : + req_img_p0_bundle_cnt - req_img_p0_cur_burst; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"req_img_p0_burst_en\" -d \"req_img_p0_bundle_cnt_w\" -q req_img_p0_bundle_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p0_bundle_cnt <= {4{1'b0}}; + end else begin + if ((req_img_p0_burst_en) == 1'b1) begin + req_img_p0_bundle_cnt <= req_img_p0_bundle_cnt_w; + // VCS coverage off + end else if ((req_img_p0_burst_en) == 1'b0) begin + end else begin + req_img_p0_bundle_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign req_img_p0_burst_cnt_dec = req_img_p0_burst_cnt - req_img_p0_bundle_cnt; +assign req_img_p0_cur_burst = req_img_p0_burst_cnt_dec[14] ? req_img_p0_burst_cnt[3:0] : req_img_p0_bundle_cnt; +assign req_img_p0_burst_cnt_w = ((is_first_running | is_p0_last_burst) & pixel_planar0_lp_vld) ? {{10{1'b0}}, pixel_planar0_lp_burst} : + ((is_first_running | is_p0_last_burst) & ~pixel_planar0_lp_vld) ? pixel_planar0_width_burst : + ((req_img_p0_sec_cnt == 2'h0) & is_p0_cur_sec_end) ? pixel_planar0_width_burst : + ((req_img_p0_sec_cnt == 2'h1) & is_p0_cur_sec_end) ? {{10{1'b0}}, pixel_planar0_rp_burst} : + req_img_p0_burst_cnt_dec[13:0]; +assign {mon_req_img_p0_sec_cnt_w, + req_img_p0_sec_cnt_w} = ((is_first_running | is_p0_last_burst) & pixel_planar0_lp_vld) ? 3'h0 : + ((is_first_running | is_p0_last_burst) & ~pixel_planar0_lp_vld) ? 3'h1 : req_img_p0_sec_cnt + 1'b1; +assign is_p0_cur_sec_end = (req_img_p0_burst_cnt <= {{10{1'b0}}, req_img_p0_bundle_cnt}); +assign is_p0_1st_burst = ((req_img_p0_burst_cnt == {{10{1'b0}}, pixel_planar0_lp_burst}) & (req_img_p0_sec_cnt == 2'h0)) | + ((req_img_p0_burst_cnt == pixel_planar0_width_burst) & (req_img_p0_sec_cnt == 2'h1) & ~pixel_planar0_lp_vld); +assign is_p0_last_burst = (is_p0_cur_sec_end & (req_img_p0_sec_cnt == 2'h1) & ~pixel_planar0_rp_vld) | + (is_p0_cur_sec_end & (req_img_p0_sec_cnt == 2'h2)); +assign is_p0_bundle_end = (req_img_p0_cur_burst == req_img_p0_bundle_cnt) | is_p0_last_burst; +assign req_img_p0_burst_size = req_img_p0_cur_burst; +assign is_p0_req_real = (req_img_p0_sec_cnt == 2'b1); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"req_img_p0_burst_en\" -d \"req_img_p0_burst_cnt_w\" -q req_img_p0_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_img_p0_sec_en\" -d \"req_img_p0_sec_cnt_w\" -q req_img_p0_sec_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p0_burst_cnt <= {14{1'b0}}; + end else begin + if ((req_img_p0_burst_en) == 1'b1) begin + req_img_p0_burst_cnt <= req_img_p0_burst_cnt_w; + // VCS coverage off + end else if ((req_img_p0_burst_en) == 1'b0) begin + end else begin + req_img_p0_burst_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p0_sec_cnt <= {2{1'b0}}; + end else begin + if ((req_img_p0_sec_en) == 1'b1) begin + req_img_p0_sec_cnt <= req_img_p0_sec_cnt_w; + // VCS coverage off + end else if ((req_img_p0_sec_en) == 1'b0) begin + end else begin + req_img_p0_sec_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// image planar 1 bundle and burst count ///////////// +assign {mon_req_img_p1_bundle_cnt_w, + req_img_p1_bundle_cnt_w} = (is_first_running | is_p1_last_burst) ? {1'b0, pixel_planar1_bundle_limit_1st} : + is_p1_bundle_end ? {1'b0, pixel_planar1_bundle_limit} : + req_img_p1_bundle_cnt - req_img_p1_cur_burst; +assign req_img_p1_burst_cnt_dec = req_img_p1_burst_cnt - req_img_p1_bundle_cnt; +assign req_img_p1_cur_burst = req_img_p1_burst_cnt_dec[14] ? req_img_p1_burst_cnt[4:0] : req_img_p1_bundle_cnt; +assign req_img_p1_burst_cnt_w = ((is_first_running | is_p1_last_burst) & pixel_planar1_lp_vld) ? {{11{1'b0}}, pixel_planar1_lp_burst} : + ((is_first_running | is_p1_last_burst) & ~pixel_planar1_lp_vld) ? pixel_planar1_width_burst : + ((req_img_p1_sec_cnt == 2'h0) & is_p1_cur_sec_end) ? pixel_planar1_width_burst : + ((req_img_p1_sec_cnt == 2'h1) & is_p1_cur_sec_end) ? {{11{1'b0}}, pixel_planar1_rp_burst} : + req_img_p1_burst_cnt_dec[13:0]; +assign {mon_req_img_p1_sec_cnt_w, + req_img_p1_sec_cnt_w} = ((is_first_running | is_p1_last_burst) & pixel_planar1_lp_vld) ? 3'h0 : + ((is_first_running | is_p1_last_burst) & ~pixel_planar1_lp_vld) ? 3'h1 : + req_img_p1_sec_cnt + 1'b1; +assign req_img_p1_burst_size = req_img_p1_cur_burst; +assign is_p1_cur_sec_end = req_img_p1_burst_cnt_dec[14] | (req_img_p1_burst_cnt == {{9{1'b0}}, req_img_p1_bundle_cnt}); +assign is_p1_1st_burst = ((req_img_p1_burst_cnt == {{11{1'b0}}, pixel_planar1_lp_burst}) & (req_img_p1_sec_cnt == 2'h0)) | + ((req_img_p1_burst_cnt == pixel_planar1_width_burst) & (req_img_p1_sec_cnt == 2'h1) & ~pixel_planar1_lp_vld); +assign is_p1_last_burst = (is_p1_cur_sec_end & (req_img_p1_sec_cnt == 2'h1) & ~pixel_planar1_rp_vld) | + (is_p1_cur_sec_end & (req_img_p1_sec_cnt == 2'h2)); +assign is_p1_bundle_end = (req_img_p1_cur_burst == req_img_p1_bundle_cnt) | is_p1_last_burst; +assign is_p1_req_real = (req_img_p1_sec_cnt == 2'b1); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"req_img_p1_burst_en\" -d \"req_img_p1_bundle_cnt_w\" -q req_img_p1_bundle_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"req_img_p1_burst_en\" -d \"req_img_p1_burst_cnt_w\" -q req_img_p1_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_img_p1_sec_en\" -d \"req_img_p1_sec_cnt_w\" -q req_img_p1_sec_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p1_bundle_cnt <= {5{1'b0}}; + end else begin + if ((req_img_p1_burst_en) == 1'b1) begin + req_img_p1_bundle_cnt <= req_img_p1_bundle_cnt_w; + // VCS coverage off + end else if ((req_img_p1_burst_en) == 1'b0) begin + end else begin + req_img_p1_bundle_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p1_burst_cnt <= {14{1'b0}}; + end else begin + if ((req_img_p1_burst_en) == 1'b1) begin + req_img_p1_burst_cnt <= req_img_p1_burst_cnt_w; + // VCS coverage off + end else if ((req_img_p1_burst_en) == 1'b0) begin + end else begin + req_img_p1_burst_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p1_sec_cnt <= {2{1'b0}}; + end else begin + if ((req_img_p1_sec_en) == 1'b1) begin + req_img_p1_sec_cnt <= req_img_p1_sec_cnt_w; + // VCS coverage off + end else if ((req_img_p1_sec_en) == 1'b0) begin + end else begin + req_img_p1_sec_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// image burst signal ///////////// +assign is_img_1st_burst = ~req_img_planar_cnt ? is_p0_1st_burst : is_p1_1st_burst; +assign is_img_last_burst = ~req_img_planar_cnt ? is_p0_last_burst : is_p1_last_burst; +assign is_img_bundle_end = ~req_img_planar_cnt ? is_p0_bundle_end : is_p1_bundle_end; +assign req_img_burst_size = ~req_img_planar_cnt ? {1'b0, req_img_p0_burst_size} : req_img_p1_burst_size; +assign is_img_dummy = ~req_img_planar_cnt ? ~is_p0_req_real : ~is_p1_req_real; +///////////// control signal ///////////// +assign req_valid_w = (~is_running) ? 1'b0 : + is_first_running ? 1'b1 : + (req_reg_en & is_last_req) ? 1'b0 : req_valid; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_w\" -q req_valid"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_valid <= 1'b0; + end else begin + req_valid <= req_valid_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign req_adv = req_valid & (~req_valid_d1 | req_ready_d1); +assign is_last_req = (is_img_last_burst & is_img_last_planar & is_last_height); +assign req_img_reg_en = req_adv; +assign req_reg_en = req_adv; +assign req_img_p0_burst_en = is_first_running | (req_img_reg_en & ~req_img_planar_cnt); +assign req_img_p0_sec_en = is_first_running | (req_img_reg_en & ~req_img_planar_cnt & is_p0_cur_sec_end); +assign req_img_p1_burst_en = is_first_running | (req_img_reg_en & req_img_planar_cnt); +assign req_img_p1_sec_en = is_first_running | (req_img_reg_en & req_img_planar_cnt & is_p1_cur_sec_end); +assign req_img_p0_burst_offset_en = is_first_running | (req_img_reg_en & ~req_img_planar_cnt & (is_p0_req_real | is_p0_last_burst)); +assign req_img_p1_burst_offset_en = is_first_running | (req_img_reg_en & req_img_planar_cnt & (is_p1_req_real | is_p1_last_burst)); +assign req_img_planar_en = is_first_running | (req_img_reg_en & is_img_bundle_end); +assign req_height_en = is_first_running | (req_img_reg_en & is_img_last_burst & is_img_last_planar); +///////////// address line offset for image ///////////// +assign {mon_req_img_p0_line_offset_w, + req_img_p0_line_offset_w} = (is_first_running) ? 33'b0 : (req_img_p0_line_offset + reg2dp_line_stride); +assign {mon_req_img_p1_line_offset_w, + req_img_p1_line_offset_w} = (is_first_running) ? 33'b0 : (req_img_p1_line_offset + reg2dp_uv_line_stride); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"req_height_en\" -d \"req_img_p0_line_offset_w\" -q req_img_p0_line_offset"); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"req_height_en & planar1_enable\" -d \"req_img_p1_line_offset_w\" -q req_img_p1_line_offset"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p0_line_offset <= {32{1'b0}}; + end else begin + if ((req_height_en) == 1'b1) begin + req_img_p0_line_offset <= req_img_p0_line_offset_w; + // VCS coverage off + end else if ((req_height_en) == 1'b0) begin + end else begin + req_img_p0_line_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p1_line_offset <= {32{1'b0}}; + end else begin + if ((req_height_en & planar1_enable) == 1'b1) begin + req_img_p1_line_offset <= req_img_p1_line_offset_w; + // VCS coverage off + end else if ((req_height_en & planar1_enable) == 1'b0) begin + end else begin + req_img_p1_line_offset <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// address burst offset for image ///////////// +//: my $atmm = 8; +//: my $k = 33 - int(log($atmm)/log(2)); +//: print qq( +//: assign {mon_req_img_p0_burst_offset_w, +//: req_img_p0_burst_offset_w} = (is_first_running | is_p0_last_burst) ? ${k}'b0 : (req_img_p0_burst_offset + req_img_p0_cur_burst); +//: assign {mon_req_img_p1_burst_offset_w, +//: req_img_p1_burst_offset_w} = (is_first_running | is_p1_last_burst) ? ${k}'b0 : (req_img_p1_burst_offset + req_img_p1_cur_burst); +//: ); +//: &eperl::flop("-nodeclare -rval \"{(${k}-1){1'b0}}\" -en \"req_img_p0_burst_offset_en\" -d \"req_img_p0_burst_offset_w\" -q req_img_p0_burst_offset"); +//: &eperl::flop("-nodeclare -rval \"{(${k}-1){1'b0}}\" -en \"req_img_p1_burst_offset_en\" -d \"req_img_p1_burst_offset_w\" -q req_img_p1_burst_offset"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_req_img_p0_burst_offset_w, +req_img_p0_burst_offset_w} = (is_first_running | is_p0_last_burst) ? 30'b0 : (req_img_p0_burst_offset + req_img_p0_cur_burst); +assign {mon_req_img_p1_burst_offset_w, +req_img_p1_burst_offset_w} = (is_first_running | is_p1_last_burst) ? 30'b0 : (req_img_p1_burst_offset + req_img_p1_cur_burst); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p0_burst_offset <= {(30-1){1'b0}}; + end else begin + if ((req_img_p0_burst_offset_en) == 1'b1) begin + req_img_p0_burst_offset <= req_img_p0_burst_offset_w; + // VCS coverage off + end else if ((req_img_p0_burst_offset_en) == 1'b0) begin + end else begin + req_img_p0_burst_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_img_p1_burst_offset <= {(30-1){1'b0}}; + end else begin + if ((req_img_p1_burst_offset_en) == 1'b1) begin + req_img_p1_burst_offset <= req_img_p1_burst_offset_w; + // VCS coverage off + end else if ((req_img_p1_burst_offset_en) == 1'b0) begin + end else begin + req_img_p1_burst_offset <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// address base for image ///////////// +assign req_img_p0_addr_base_w = {reg2dp_datain_addr_high_0, reg2dp_datain_addr_low_0}; +assign req_img_p1_addr_base_w = {reg2dp_datain_addr_high_1, reg2dp_datain_addr_low_1}; +//: my $atmm = 8; +//: my $k = int(log($atmm)/log(2)); +//: print qq( +//: assign {mon_req_img_p0_addr, +//: req_img_p0_addr} = req_img_p0_addr_base + req_img_p0_line_offset + {req_img_p0_burst_offset,${k}'d0}; +//: assign {mon_req_img_p1_addr, +//: req_img_p1_addr} = req_img_p1_addr_base + req_img_p1_line_offset + {req_img_p1_burst_offset,${k}'d0}; +//: ); +//: &eperl::flop("-nodeclare -norst -en \"layer_st\" -d \"req_img_p0_addr_base_w\" -q req_img_p0_addr_base"); +//: &eperl::flop("-nodeclare -norst -en \"layer_st\" -d \"req_img_p1_addr_base_w\" -q req_img_p1_addr_base"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_req_img_p0_addr, +req_img_p0_addr} = req_img_p0_addr_base + req_img_p0_line_offset + {req_img_p0_burst_offset,3'd0}; +assign {mon_req_img_p1_addr, +req_img_p1_addr} = req_img_p1_addr_base + req_img_p1_line_offset + {req_img_p1_burst_offset,3'd0}; +always @(posedge nvdla_core_clk) begin + if ((layer_st) == 1'b1) begin + req_img_p0_addr_base <= req_img_p0_addr_base_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + req_img_p0_addr_base <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((layer_st) == 1'b1) begin + req_img_p1_addr_base <= req_img_p1_addr_base_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + req_img_p1_addr_base <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// request package ///////////// +assign req_valid_d1_w = ~is_running ? 1'b0 : + req_valid ? 1'b1 : + req_ready_d1 ? 1'b0 : req_valid_d1; +assign req_addr = req_img_planar_cnt ? req_img_p1_addr : req_img_p0_addr ; +assign req_size = req_img_burst_size; +assign {mon_req_size_out, + req_size_out} = req_size - 1'b1; +assign req_line_st = is_img_1st_burst; +assign req_bundle_end = (is_img_bundle_end & is_img_last_planar); +assign req_line_end = (is_img_last_burst & is_img_last_planar); +assign req_grant_end = (is_img_last_burst & is_img_last_planar); +assign req_is_dummy = is_img_dummy; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_d1_w\" -q req_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"{64{1'b0}}\" -en \"req_reg_en\" -d \"req_addr\" -q req_addr_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"req_reg_en\" -d \"req_size\" -q req_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"req_reg_en\" -d \"req_size_out\" -q req_size_out_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_line_st\" -q req_line_st_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_bundle_end\" -q req_bundle_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_line_end\" -q req_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_grant_end\" -q req_grant_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"is_last_req\" -q req_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_img_planar_cnt\" -q req_planar_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_is_dummy\" -q req_is_dummy_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_valid_d1 <= 1'b0; + end else begin + req_valid_d1 <= req_valid_d1_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_d1 <= {64{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_addr_d1 <= req_addr; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_addr_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_d1 <= {5{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_size_d1 <= req_size; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_size_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_out_d1 <= {5{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_size_out_d1 <= req_size_out; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_size_out_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_line_st_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_line_st_d1 <= req_line_st; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_line_st_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_bundle_end_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_bundle_end_d1 <= req_bundle_end; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_bundle_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_line_end_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_line_end_d1 <= req_line_end; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_line_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_grant_end_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_grant_end_d1 <= req_grant_end; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_grant_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_end_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_end_d1 <= is_last_req; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_planar_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_planar_d1 <= req_img_planar_cnt; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_planar_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_is_dummy_d1 <= 1'b0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_is_dummy_d1 <= req_is_dummy; + // VCS coverage off + end else if ((req_reg_en) == 1'b0) begin + end else begin + req_is_dummy_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef NVDLA_PRINT_CDMA +always @ (posedge nvdla_core_clk) +begin + if(req_valid_d1 & req_ready_d1) + begin + $display("[CDMA IMG REQ] Dummy = %d, Addr = 0x%010h, size = %0d, time = %0d", req_is_dummy_d1, req_addr_d1, req_size_d1, $stime); + end +end +`endif +//////////////////////////////////////////////////////////////////////// +// request arbiter and cbuf entry monitor // +//////////////////////////////////////////////////////////////////////// +assign req_ready_d1 = ((dma_rd_req_rdy | req_is_dummy_d1) & dma_req_fifo_ready & is_cbuf_ready); +assign req_is_done_w = is_first_running ? 1'b0 : + (req_valid_d1 & req_ready_d1 & req_end_d1) ? 1'b1 : req_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"req_is_done_w\" -q req_is_done"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_is_done <= 1'b1; + end else begin + req_is_done <= req_is_done_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// cbuf monitor ///////////// +assign cur_required_entry = (is_cbuf_ready | req_is_done) ? 15'b0 : + is_last_height ? pre_entry_end_d1 : + is_1st_height ? pre_entry_st_d1 : pre_entry_mid_d1; +assign {mon_total_required_entry, + total_required_entry} = cur_required_entry + img_entry_onfly; +assign is_cbuf_enough = (status2dma_free_entries >= total_required_entry); +assign is_cbuf_ready_w = (~is_running | is_first_running) ? 1'b0 : + (req_valid_d1 & req_ready_d1 & req_grant_end_d1) ? 1'b0 : + (~is_cbuf_ready) ? is_cbuf_enough : is_cbuf_ready; +assign img_entry_onfly_sub = img2status_dat_updt ? img2status_dat_entries : 15'b0; +assign img_entry_onfly_add = (~req_is_done & is_cbuf_enough & ~is_cbuf_ready) ? cur_required_entry : 15'b0; +assign {mon_img_entry_onfly_w, + img_entry_onfly_w} = img_entry_onfly + img_entry_onfly_add - img_entry_onfly_sub; +assign img_entry_onfly_en = (~req_is_done & is_cbuf_enough & ~is_cbuf_ready) | img2status_dat_updt; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_cbuf_ready_w\" -q is_cbuf_ready"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"img_entry_onfly_en\" -d \"img_entry_onfly_w\" -q img_entry_onfly"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_cbuf_ready <= 1'b0; + end else begin + is_cbuf_ready <= is_cbuf_ready_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_entry_onfly <= {15{1'b0}}; + end else begin + if ((img_entry_onfly_en) == 1'b1) begin + img_entry_onfly <= img_entry_onfly_w; + // VCS coverage off + end else if ((img_entry_onfly_en) == 1'b0) begin + end else begin + img_entry_onfly <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// CDMA IMG read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_datain_ram_type) + ,.mcif_rd_req_pd (img_dat2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2img_dat_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2img_dat_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2img_dat_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////// +// PKT_PACK_WIRE( dma_read_cmd , dma_rd_req_ , dma_rd_req_pd ) +assign dma_rd_req_pd[32 -1:0] = dma_rd_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_rd_req_size[14:0]; +assign dma_rd_req_vld = req_valid_d1 & dma_req_fifo_ready & is_cbuf_ready & ~req_is_dummy_d1; +assign dma_rd_req_addr = req_addr_d1; +assign dma_rd_req_size = {{10{1'b0}}, req_size_out_d1}; +assign dma_rd_req_type = reg2dp_datain_ram_type; +assign dma_rd_rsp_rdy = ~dma_blocking; +assign dma_blocking = dma_rsp_blocking; +NV_NVDLA_CDMA_IMG_fifo u_NV_NVDLA_CDMA_IMG_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[10:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w + ,.rd_data (dma_rsp_fifo_data[10:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = req_valid_d1 & is_cbuf_ready & (dma_rd_req_rdy | req_is_dummy_d1) ; +assign dma_req_fifo_data = {req_planar_d1, + req_end_d1, + req_line_end_d1, + req_bundle_end_d1, + req_line_st_d1, + req_is_dummy_d1, + req_size_d1[4:0]}; +//////////////////////////////////////////////////////////////////////// +// CDMA IMG read response logic // +//////////////////////////////////////////////////////////////////////// +assign dma_rd_rsp_data[64 -1:0] = dma_rd_rsp_pd[64 -1:0]; +assign dma_rd_rsp_mask[(64/8/8)-1:0] = dma_rd_rsp_pd[( 64 + (64/8/8) )-1:64]; +assign {dma_rsp_planar, + dma_rsp_end, + dma_rsp_line_end, + dma_rsp_bundle_end, + dma_rsp_line_st, + dma_rsp_dummy, + dma_rsp_size} = dma_rsp_fifo_data; +assign dma_rsp_blocking = (dma_rsp_fifo_req & dma_rsp_dummy); +assign dma_rsp_mask[0] = (~dma_rsp_fifo_req) ? 1'b0 : + ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[0]) : 1'b1; +//: my $msk = (64/8/8); +//: if($msk >= 2) { +//: print qq( +//: assign dma_rsp_mask[1] = (~dma_rsp_fifo_req) ? 1'b0 : +//: ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[1]) : +//: (dma_rsp_size[4:1] == dma_rsp_size_cnt[4:1]) ? 1'b0 : 1'b1; +//: ); +//: } elsif($msk == 4) { +//: print qq( +//: assign dma_rsp_mask[2] = (~dma_rsp_fifo_req) ? 1'b0 : +//: ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[2]) : +//: ((dma_rsp_size[4:2] == dma_rsp_size_cnt[4:2]) & (&dma_rsp_size_cnt[11])) ? 1'b0 : 1'b1; +//: assign dma_rsp_mask[3] = (~dma_rsp_fifo_req) ? 1'b0 : +//: ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[3]) : +//: (dma_rsp_size[4:2] == dma_rsp_size_cnt[4:2]) ? 1'b0 : 1'b1; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_dma_rsp_size_cnt_inc, + dma_rsp_size_cnt_inc} = dma_rsp_size_cnt +//: my $msk = (64/8/8); +//: foreach my $i (0..$msk-1) { +//: print qq( +//: + dma_rsp_mask[$i] +//: ); +//: } +//: print qq( ; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + ++ dma_rsp_mask[0] + ; +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 5'b0 : dma_rsp_size_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"dma_rsp_vld\" -d \"dma_rsp_size_cnt_w\" -q dma_rsp_size_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rsp_size_cnt <= {5{1'b0}}; + end else begin + if ((dma_rsp_vld) == 1'b1) begin + dma_rsp_size_cnt <= dma_rsp_size_cnt_w; + // VCS coverage off + end else if ((dma_rsp_vld) == 1'b0) begin + end else begin + dma_rsp_size_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rsp_vld = dma_rsp_fifo_req & (dma_rsp_dummy | dma_rd_rsp_vld); +assign dma_rsp_fifo_ready = (dma_rsp_vld & (dma_rsp_size_cnt_inc == dma_rsp_size)); +//////////////////////////////////////////////////////////////////////// +// CDMA pixel data response logic stage 1 // +//////////////////////////////////////////////////////////////////////// +assign rsp_img_vld_w = dma_rsp_vld; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_img_vld_w\" -q rsp_img_vld"); +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num-1) { +//: print qq( +//: assign rsp_img_p${i}_vld_w = dma_rsp_mask[${i}]; +//: +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: if (!nvdla_core_rstn) begin +//: rsp_img_p${i}_vld <= 1'b0; +//: end else begin +//: rsp_img_p${i}_vld <= rsp_img_p${i}_vld_w; +//: end +//: +//: always @(posedge nvdla_core_clk) +//: if (rsp_img_p${i}_vld_w) begin +//: rsp_img_p${i}_data <= rsp_img_p${i}_data_w; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_vld <= 1'b0; + end else begin + rsp_img_vld <= rsp_img_vld_w; + end +end + +assign rsp_img_p0_vld_w = dma_rsp_mask[0]; + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +rsp_img_p0_vld <= 1'b0; +end else begin +rsp_img_p0_vld <= rsp_img_p0_vld_w; +end + +always @(posedge nvdla_core_clk) +if (rsp_img_p0_vld_w) begin +rsp_img_p0_data <= rsp_img_p0_data_w; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign rsp_dat = dma_rd_rsp_data; +//10'h1 ABGR, VU, single, unchange +//10'h2 ARGB, AYUV, 8bpp +//10'h4 ARGB, AYUV, 16bpp +//10'h8 BGRA, VUYA, 8bpp +//10'h10 BGRA, VUYA, 16bpp +//10'h20 RGBA, YUVA, 8bpp +//10'h40 ARGB, AYUV, packed_10b +//10'h80 BGRA, YUVA, packed_10b +//10'h100 RGBA, packed_10b +//10'h200 UV, 8bpp +//10'h400 UV, 16bpp +assign rsp_img_sel[0] = pixel_order[0] | (~dma_rsp_planar & pixel_planar); +assign rsp_img_sel[1] = pixel_order[1]; +assign rsp_img_sel[2] = pixel_order[2]; +assign rsp_img_sel[3] = pixel_order[3]; +assign rsp_img_sel[4] = pixel_order[4]; +assign rsp_img_sel[5] = pixel_order[5]; +assign rsp_img_sel[6] = pixel_order[6]; +assign rsp_img_sel[7] = pixel_order[7]; +assign rsp_img_sel[8] = pixel_order[8]; +assign rsp_img_sel[9] = pixel_order[9] & dma_rsp_planar; +assign rsp_img_sel[10] = pixel_order[10] & dma_rsp_planar; +//////// reordering //////// +assign rsp_img_data_sw_o0 = rsp_dat; +assign rsp_img_data_sw_o1 = { +//: my $dmaif = 64/32;## +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*32+31:${k}*32+24], rsp_dat[${k}*32+7:${k}*32], rsp_dat[${k}*32+15:${k}*32+8], rsp_dat[${k}*32+23:${k}*32+16], +//: ); +//: } +//: } +//: print " rsp_dat[0*32+31:0*32+24], rsp_dat[0*32+7:0*32], rsp_dat[0*32+15:0*32+8], rsp_dat[0*32+23:0*32+16]}; \n"; +//: +//: +//: print " assign rsp_img_data_sw_o3 = { \n"; +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*32+7:${k}*32], rsp_dat[${k}*32+31:${k}*32+24], rsp_dat[${k}*32+23:${k}*32+16], rsp_dat[${k}*32+15:${k}*32+8], +//: ); +//: } +//: } +//: print " rsp_dat[0*32+7:0*32], rsp_dat[0*32+31:0*32+24], rsp_dat[0*32+23:0*32+16], rsp_dat[0*32+15:0*32+8]}; \n"; +//: +//: +//: print " assign rsp_img_data_sw_o5 = { \n"; +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*32+7:${k}*32], rsp_dat[${k}*32+15:${k}*32+8], rsp_dat[${k}*32+23:${k}*32+16], rsp_dat[${k}*32+31:${k}*32+24], +//: ); +//: } +//: } +//: print " rsp_dat[0*32+7:0*32], rsp_dat[0*32+15:0*32+8], rsp_dat[0*32+23:0*32+16], rsp_dat[0*32+31:0*32+24]}; \n"; +//: my $dmaif = 64/16; ## +//: print " assign rsp_img_data_sw_o9 = { \n"; +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*16+7:${k}*16], rsp_dat[${k}*16+15:${k}*16+8], +//: ); +//: } +//: } +//: print " rsp_dat[0*16+7:0*16], rsp_dat[0*16+15:0*16+8]}; \n"; +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: print " assign { \n"; +//: if($atmm_num > 1) { +//: foreach my $i (0..$atmm_num -2) { +//: my $k = $atmm_num - $i -1; +//: print " rsp_img_p${k}_data_w, "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +rsp_dat[1*32+31:1*32+24], rsp_dat[1*32+7:1*32], rsp_dat[1*32+15:1*32+8], rsp_dat[1*32+23:1*32+16], + rsp_dat[0*32+31:0*32+24], rsp_dat[0*32+7:0*32], rsp_dat[0*32+15:0*32+8], rsp_dat[0*32+23:0*32+16]}; + assign rsp_img_data_sw_o3 = { + +rsp_dat[1*32+7:1*32], rsp_dat[1*32+31:1*32+24], rsp_dat[1*32+23:1*32+16], rsp_dat[1*32+15:1*32+8], + rsp_dat[0*32+7:0*32], rsp_dat[0*32+31:0*32+24], rsp_dat[0*32+23:0*32+16], rsp_dat[0*32+15:0*32+8]}; + assign rsp_img_data_sw_o5 = { + +rsp_dat[1*32+7:1*32], rsp_dat[1*32+15:1*32+8], rsp_dat[1*32+23:1*32+16], rsp_dat[1*32+31:1*32+24], + rsp_dat[0*32+7:0*32], rsp_dat[0*32+15:0*32+8], rsp_dat[0*32+23:0*32+16], rsp_dat[0*32+31:0*32+24]}; + assign rsp_img_data_sw_o9 = { + +rsp_dat[3*16+7:3*16], rsp_dat[3*16+15:3*16+8], + +rsp_dat[2*16+7:2*16], rsp_dat[2*16+15:2*16+8], + +rsp_dat[1*16+7:1*16], rsp_dat[1*16+15:1*16+8], + rsp_dat[0*16+7:0*16], rsp_dat[0*16+15:0*16+8]}; + assign { + +//| eperl: generated_end (DO NOT EDIT ABOVE) + rsp_img_p0_data_w} = ({64{rsp_img_sel[0]}} & rsp_img_data_sw_o0) | + ({64{rsp_img_sel[1]}} & rsp_img_data_sw_o1) | + ({64{rsp_img_sel[3]}} & rsp_img_data_sw_o3) | + ({64{rsp_img_sel[5]}} & rsp_img_data_sw_o5) | + ({64{rsp_img_sel[9]}} & rsp_img_data_sw_o9); +assign dma_rsp_w_burst_size = dma_rsp_size; +assign rsp_img_1st_burst_w = dma_rsp_line_st & (dma_rsp_size_cnt == 5'h0); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_planar\" -q rsp_img_planar"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"rsp_img_1st_burst_w\" -q rsp_img_1st_burst"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_line_st\" -q rsp_img_line_st"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_fifo_ready\" -q rsp_img_req_end"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"rsp_img_vld_w & dma_rsp_fifo_ready\" -d \"dma_rsp_w_burst_size\" -q rsp_img_w_burst_size"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_line_end & dma_rsp_fifo_ready\" -q rsp_img_line_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_bundle_end & dma_rsp_fifo_ready\" -q rsp_img_bundle_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_end & dma_rsp_fifo_ready\" -q rsp_img_end"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_planar <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_planar <= dma_rsp_planar; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_planar <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_1st_burst <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_1st_burst <= rsp_img_1st_burst_w; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_1st_burst <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_line_st <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_line_st <= dma_rsp_line_st; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_line_st <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_req_end <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_req_end <= dma_rsp_fifo_ready; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_req_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_w_burst_size <= {5{1'b0}}; + end else begin + if ((rsp_img_vld_w & dma_rsp_fifo_ready) == 1'b1) begin + rsp_img_w_burst_size <= dma_rsp_w_burst_size; + // VCS coverage off + end else if ((rsp_img_vld_w & dma_rsp_fifo_ready) == 1'b0) begin + end else begin + rsp_img_w_burst_size <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_line_end <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_line_end <= dma_rsp_line_end & dma_rsp_fifo_ready; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_line_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_bundle_end <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_bundle_end <= dma_rsp_bundle_end & dma_rsp_fifo_ready; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_bundle_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_end <= 1'b0; + end else begin + if ((rsp_img_vld_w) == 1'b1) begin + rsp_img_end <= dma_rsp_end & dma_rsp_fifo_ready; + // VCS coverage off + end else if ((rsp_img_vld_w) == 1'b0) begin + end else begin + rsp_img_end <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// CDMA pixel data response logic stage 2: cache and sbuf write // +//////////////////////////////////////////////////////////////////////// +//////// cache line control //////// +assign rsp_img_c0l0_wr_en = (rsp_img_p0_vld & (~rsp_img_planar)); +assign rsp_img_c1l0_wr_en = (rsp_img_p0_vld & rsp_img_planar); +//assign rsp_img_l0_data = rsp_img_p1_vld ? rsp_img_p1_data : rsp_img_p0_data; +// need cache more when more dmaif/atmm +//: my $dmaif = 64; +//: my $atmm = (8 * 8); +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: /////rsp_img_p0_cache_data p0 means planar 0 +//: ); +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c0l0_wr_en \" -d \"rsp_img_p0_data\" -q rsp_img_p0_cache_data"); +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c1l0_wr_en \" -d \"rsp_img_p0_data\" -q rsp_img_p1_cache_data"); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rsp_img_l0_data = rsp_img_p1_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rsp_img_l0_data = rsp_img_p3_vld ? rsp_img_p3_data : rsp_img_p2_vld ? rsp_img_p2_data : rsp_img_p1_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: assign rsp_img_l1_data = rsp_img_p3_vld ? rsp_img_p2_data : rsp_img_p2_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: assign rsp_img_l2_data = rsp_img_p3_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: ); +//: } +//: +//: if($atmm_num > 1) { +//: foreach my $i(0..$atmm_num-2) { +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c0l${i}_wr_en\" -d \"rsp_img_l${i}_data\" -q rsp_img_c0l${i}"); +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c1l${i}_wr_en\" -d \"rsp_img_l${i}_data\" -q rsp_img_c1l${i}"); +//: print " //////// data write control logic: normal write back //////// \n"; +//: print " assign rsp_img_p${i}_cache_data = ({${atmm} {~rsp_img_planar}} & rsp_img_c0l${i}) | ({${atmm} { rsp_img_planar}} & rsp_img_c1l${i}); \n"; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +/////rsp_img_p0_cache_data p0 means planar 0 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_cache_data <= {64{1'b0}}; + end else begin + if ((rsp_img_c0l0_wr_en ) == 1'b1) begin + rsp_img_p0_cache_data <= rsp_img_p0_data; + // VCS coverage off + end else if ((rsp_img_c0l0_wr_en ) == 1'b0) begin + end else begin + rsp_img_p0_cache_data <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p1_cache_data <= {64{1'b0}}; + end else begin + if ((rsp_img_c1l0_wr_en ) == 1'b1) begin + rsp_img_p1_cache_data <= rsp_img_p0_data; + // VCS coverage off + end else if ((rsp_img_c1l0_wr_en ) == 1'b0) begin + end else begin + rsp_img_p1_cache_data <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//per atmm +//: my $dmaif = 64; +//: my $atmm = (8*8); +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst); +//: +//: assign rsp_img_p0_data_atmm0 = rsp_img_p0_data; +//: assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm0,(rsp_img_c0l0_wr_en ? rsp_img_p0_cache_data : rsp_img_p1_cache_data)} >> {rsp_img_sft, 3'b0}); +//: +//: assign rsp_img_planar_idx_add = 3'h1; +//: ); +//: } elsif ($atmm_num == 2) { +//: print qq( +//: assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst | rsp_img_p1_vld); +//: assign rsp_img_p1_vld_d1_w = rsp_img_p1_vld & (~rsp_img_1st_burst ); +//: +//: assign rsp_img_p0_data_atmm0 = rsp_img_1st_burst ? rsp_img_p0_data : rsp_img_p0_cache_data; +//: assign rsp_img_p0_data_atmm1 = rsp_img_1st_burst ? rsp_img_p1_data : rsp_img_p0_data; +//: assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: assign {mon_rsp_img_p1_data_d1_w, rsp_img_p1_data_d1_w} = ({rsp_img_p1_data, rsp_img_p0_data} >> {rsp_img_sft, 3'b0}); +//: +//: assign rsp_img_planar_idx_add = rsp_img_p1_vld_d1_w ? 3'h2 : 3'h1; +//: ); +//: } elsif ($atmm_num == 4) { +//: print qq( +//: assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst | rsp_img_p1_vld | rsp_img_p2_vld | rsp_img_p3_vld ); +//: assign rsp_img_p1_vld_d1_w = rsp_img_p1_vld & (~rsp_img_1st_burst | rsp_img_p2_vld | rsp_img_p3_vld ); +//: assign rsp_img_p2_vld_d1_w = rsp_img_p2_vld & (~rsp_img_1st_burst | rsp_img_p3_vld ); +//: assign rsp_img_p3_vld_d1_w = rsp_img_p3_vld & (~rsp_img_1st_burst ); +//: +//: assign rsp_img_p0_data_atmm0 = rsp_img_1st_burst ? rsp_img_p0_data : rsp_img_p0_cache_data; +//: assign rsp_img_p0_data_atmm1 = rsp_img_1st_burst ? rsp_img_p1_data : rsp_img_p1_cache_data; +//: assign rsp_img_p0_data_atmm2 = rsp_img_1st_burst ? rsp_img_p2_data : rsp_img_p2_cache_data; +//: assign rsp_img_p0_data_atmm3 = rsp_img_1st_burst ? rsp_img_p3_data : rsp_img_p0_data; +//: // assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm3, rsp_img_p0_data_atmm2, rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: // assign {mon_rsp_img_p1_data_d1_w, rsp_img_p1_data_d1_w} = ({rsp_img_p0_data_atmm3, rsp_img_p0_data_atmm2, rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: // assign {mon_rsp_img_p2_data_d1_w, rsp_img_p2_data_d1_w} = ({rsp_img_p0_data_atmm3, rsp_img_p0_data_atmm2, rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: // assign {mon_rsp_img_p3_data_d1_w, rsp_img_p3_data_d1_w} = ({rsp_img_p3_data, rsp_img_p2_data, rsp_img_p1_data, rsp_img_p0_data} >> {rsp_img_sft, 3'b0}); +//: +//: assign rsp_img_planar_idx_add = rsp_img_p3_vld_d1_w ? 3'h4 : rsp_img_p2_vld_d1_w ? 3'h3 : rsp_img_p1_vld_d1_w ? 3'h2 : 3'h1; +//: ); +//: } +//: foreach my $i(0..$atmm_num -1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_img_p${i}_vld_d1_w\" -q rsp_img_p${i}_vld_d1"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_img_p${i}_vld_d1_w\" -d \"rsp_img_p${i}_data_d1_w\" -q rsp_img_p${i}_data_d1"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst); + +assign rsp_img_p0_data_atmm0 = rsp_img_p0_data; +assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm0,(rsp_img_c0l0_wr_en ? rsp_img_p0_cache_data : rsp_img_p1_cache_data)} >> {rsp_img_sft, 3'b0}); + +assign rsp_img_planar_idx_add = 3'h1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_vld_d1 <= 1'b0; + end else begin + rsp_img_p0_vld_d1 <= rsp_img_p0_vld_d1_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_img_p0_vld_d1_w) == 1'b1) begin + rsp_img_p0_data_d1 <= rsp_img_p0_data_d1_w; + // VCS coverage off + end else if ((rsp_img_p0_vld_d1_w) == 1'b0) begin + end else begin + rsp_img_p0_data_d1 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign rsp_img_p0_data_atmm0 = rsp_img_1st_burst ? rsp_img_p0_data : rsp_img_p0_cache_data; +//assign rsp_img_p0_data_atmm1 = rsp_img_1st_burst ? rsp_img_p1_data : rsp_img_p0_data; +//assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//assign {mon_rsp_img_p1_data_d1_w, rsp_img_p1_data_d1_w} = ({rsp_img_p1_data, rsp_img_p0_data} >> {rsp_img_sft, 3'b0}); +assign rsp_img_sft = rsp_img_planar ? pixel_planar1_byte_sft : pixel_planar0_byte_sft; +//////// data write control logic: normal write back //////// +//assign rsp_img_planar_idx_add = rsp_img_p1_vld_d1_w ? 2'h2 : 2'h1; +//: my $dmaif = 64; +//: my $atmm = (8*8); +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: assign rsp_img_p${i}_planar0_idx_inc = rsp_img_p${i}_planar0_idx + rsp_img_planar_idx_add; +//: assign rsp_img_p${i}_planar1_idx_inc = rsp_img_p${i}_planar1_idx + rsp_img_planar_idx_add; +//: assign rsp_img_p${i}_planar0_idx_w = is_first_running ? 7'b${i} : rsp_img_p${i}_planar0_idx_inc[8 -2:0]; +//: assign rsp_img_p${i}_planar1_idx_w = is_first_running ? 7'b${i} : rsp_img_p${i}_planar1_idx_inc[8 -2:0]; +//: assign rsp_img_p${i}_planar0_en = is_first_running | (rsp_img_p${i}_vld_d1_w & ~rsp_img_planar); +//: assign rsp_img_p${i}_planar1_en = is_first_running | (rsp_img_p${i}_vld_d1_w & rsp_img_planar); +//: assign rsp_img_p${i}_addr = (~rsp_img_planar) ? {1'b0, rsp_img_p${i}_planar0_idx[0], rsp_img_p${i}_planar0_idx[8 -2:1]} : +//: {1'b1, rsp_img_p${i}_planar1_idx[0], rsp_img_p${i}_planar1_idx[8 -2:1]}; +//: ); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rsp_img_p${i}_planar0_en\" -d \"rsp_img_p${i}_planar0_idx_w\" -q rsp_img_p${i}_planar0_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rsp_img_p${i}_planar1_en\" -d \"rsp_img_p${i}_planar1_idx_w\" -q rsp_img_p${i}_planar1_idx"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_img_p${i}_vld_d1_w\" -d \"rsp_img_p${i}_addr\" -q rsp_img_p${i}_addr_d1"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign rsp_img_p0_planar0_idx_inc = rsp_img_p0_planar0_idx + rsp_img_planar_idx_add; +assign rsp_img_p0_planar1_idx_inc = rsp_img_p0_planar1_idx + rsp_img_planar_idx_add; +assign rsp_img_p0_planar0_idx_w = is_first_running ? 7'b0 : rsp_img_p0_planar0_idx_inc[8 -2:0]; +assign rsp_img_p0_planar1_idx_w = is_first_running ? 7'b0 : rsp_img_p0_planar1_idx_inc[8 -2:0]; +assign rsp_img_p0_planar0_en = is_first_running | (rsp_img_p0_vld_d1_w & ~rsp_img_planar); +assign rsp_img_p0_planar1_en = is_first_running | (rsp_img_p0_vld_d1_w & rsp_img_planar); +assign rsp_img_p0_addr = (~rsp_img_planar) ? {1'b0, rsp_img_p0_planar0_idx[0], rsp_img_p0_planar0_idx[8 -2:1]} : +{1'b1, rsp_img_p0_planar1_idx[0], rsp_img_p0_planar1_idx[8 -2:1]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_planar0_idx <= {7{1'b0}}; + end else begin + if ((rsp_img_p0_planar0_en) == 1'b1) begin + rsp_img_p0_planar0_idx <= rsp_img_p0_planar0_idx_w; + // VCS coverage off + end else if ((rsp_img_p0_planar0_en) == 1'b0) begin + end else begin + rsp_img_p0_planar0_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_planar1_idx <= {7{1'b0}}; + end else begin + if ((rsp_img_p0_planar1_en) == 1'b1) begin + rsp_img_p0_planar1_idx <= rsp_img_p0_planar1_idx_w; + // VCS coverage off + end else if ((rsp_img_p0_planar1_en) == 1'b0) begin + end else begin + rsp_img_p0_planar1_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_addr_d1 <= {8{1'b0}}; + end else begin + if ((rsp_img_p0_vld_d1_w) == 1'b1) begin + rsp_img_p0_addr_d1 <= rsp_img_p0_addr; + // VCS coverage off + end else if ((rsp_img_p0_vld_d1_w) == 1'b0) begin + end else begin + rsp_img_p0_addr_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// data write control logic: MISC output //////// +assign {mon_rsp_img_p0_burst_cnt_inc, + rsp_img_p0_burst_cnt_inc} = rsp_img_p0_burst_cnt + rsp_img_w_burst_size[3:0] - rsp_img_line_st; +assign {mon_rsp_img_p1_burst_cnt_inc, + rsp_img_p1_burst_cnt_inc} = rsp_img_p1_burst_cnt + rsp_img_w_burst_size - rsp_img_line_st; +assign rsp_img_p0_burst_cnt_w = is_first_running ? 4'b0 : + (rsp_img_vld & rsp_img_bundle_end) ? 4'b0 : + (~rsp_img_planar) ? rsp_img_p0_burst_cnt_inc : rsp_img_p0_burst_cnt; +assign rsp_img_p1_burst_cnt_w = is_first_running ? 5'b0 : + (rsp_img_vld & rsp_img_bundle_end) ? 5'b0 : + (rsp_img_planar) ? rsp_img_p1_burst_cnt_inc : rsp_img_p1_burst_cnt; +assign rsp_img_bundle_done = (rsp_img_vld & rsp_img_bundle_end); +assign rsp_img_p0_burst_size_w = ~rsp_img_planar ? rsp_img_p0_burst_cnt_inc : rsp_img_p0_burst_cnt; +assign rsp_img_p1_burst_size_w = rsp_img_p1_burst_cnt_inc; +assign rsp_img_p0_burst_cnt_en = is_first_running | (rsp_img_vld & rsp_img_req_end); +assign rsp_img_p1_burst_cnt_en = is_first_running | (rsp_img_vld & rsp_img_req_end & pixel_planar); +assign rsp_img_p0_burst_size_en = is_first_running | (rsp_img_vld & rsp_img_bundle_end); +assign rsp_img_p1_burst_size_en = is_first_running | (rsp_img_vld & rsp_img_bundle_end & pixel_planar); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"rsp_img_p0_burst_cnt_en\" -d \"rsp_img_p0_burst_cnt_w\" -q rsp_img_p0_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"rsp_img_p1_burst_cnt_en\" -d \"rsp_img_p1_burst_cnt_w\" -q rsp_img_p1_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"rsp_img_p0_burst_size_en\" -d \"rsp_img_p0_burst_size_w\" -q rsp_img_p0_burst_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"rsp_img_p1_burst_size_en\" -d \"rsp_img_p1_burst_size_w\" -q rsp_img_p1_burst_size_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_img_bundle_done\" -q rsp_img_bundle_done_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_bundle_done\" -d \"rsp_img_line_end\" -q rsp_img_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_bundle_done\" -d \"rsp_img_end\" -q rsp_img_layer_end_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_burst_cnt <= {4{1'b0}}; + end else begin + if ((rsp_img_p0_burst_cnt_en) == 1'b1) begin + rsp_img_p0_burst_cnt <= rsp_img_p0_burst_cnt_w; + // VCS coverage off + end else if ((rsp_img_p0_burst_cnt_en) == 1'b0) begin + end else begin + rsp_img_p0_burst_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p1_burst_cnt <= {5{1'b0}}; + end else begin + if ((rsp_img_p1_burst_cnt_en) == 1'b1) begin + rsp_img_p1_burst_cnt <= rsp_img_p1_burst_cnt_w; + // VCS coverage off + end else if ((rsp_img_p1_burst_cnt_en) == 1'b0) begin + end else begin + rsp_img_p1_burst_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p0_burst_size_d1 <= {4{1'b0}}; + end else begin + if ((rsp_img_p0_burst_size_en) == 1'b1) begin + rsp_img_p0_burst_size_d1 <= rsp_img_p0_burst_size_w; + // VCS coverage off + end else if ((rsp_img_p0_burst_size_en) == 1'b0) begin + end else begin + rsp_img_p0_burst_size_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_p1_burst_size_d1 <= {5{1'b0}}; + end else begin + if ((rsp_img_p1_burst_size_en) == 1'b1) begin + rsp_img_p1_burst_size_d1 <= rsp_img_p1_burst_size_w; + // VCS coverage off + end else if ((rsp_img_p1_burst_size_en) == 1'b0) begin + end else begin + rsp_img_p1_burst_size_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_bundle_done_d1 <= 1'b0; + end else begin + rsp_img_bundle_done_d1 <= rsp_img_bundle_done; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_line_end_d1 <= 1'b0; + end else begin + if ((rsp_img_bundle_done) == 1'b1) begin + rsp_img_line_end_d1 <= rsp_img_line_end; + // VCS coverage off + end else if ((rsp_img_bundle_done) == 1'b0) begin + end else begin + rsp_img_line_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_layer_end_d1 <= 1'b0; + end else begin + if ((rsp_img_bundle_done) == 1'b1) begin + rsp_img_layer_end_d1 <= rsp_img_end; + // VCS coverage off + end else if ((rsp_img_bundle_done) == 1'b0) begin + end else begin + rsp_img_layer_end_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// data write control logic: status //////// +assign rsp_img_is_done_w = is_first_running ? 1'b0 : + (rsp_img_end & rsp_img_line_end) ? 1'b1 : rsp_img_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"is_running\" -d \"rsp_img_is_done_w\" -q rsp_img_is_done"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_img_is_done <= 1'b1; + end else begin + if ((is_running) == 1'b1) begin + rsp_img_is_done <= rsp_img_is_done_w; + // VCS coverage off + end else if ((is_running) == 1'b0) begin + end else begin + rsp_img_is_done <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Shared buffer write signals // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: assign img2sbuf_p${i}_wr_addr = rsp_img_p${i}_addr_d1; +//: assign img2sbuf_p${i}_wr_data = rsp_img_p${i}_data_d1; +//: assign img2sbuf_p${i}_wr_en = rsp_img_p${i}_vld_d1; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign img2sbuf_p0_wr_addr = rsp_img_p0_addr_d1; +assign img2sbuf_p0_wr_data = rsp_img_p0_data_d1; +assign img2sbuf_p0_wr_en = rsp_img_p0_vld_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign img2sbuf_p0_wr_en = rsp_img_p0_vld_d1; +//assign img2sbuf_p1_wr_en = rsp_img_p1_vld_d1; +//assign img2sbuf_p0_wr_addr = rsp_img_p0_addr_d1; +//assign img2sbuf_p1_wr_addr = rsp_img_p1_addr_d1; +//assign img2sbuf_p0_wr_data = rsp_img_p0_data_d1; +//assign img2sbuf_p1_wr_data = rsp_img_p1_data_d1; +//////////////////////////////////////////////////////////////////////// +// Signal from SG to PACK // +//////////////////////////////////////////////////////////////////////// +assign sg2pack_img_line_end = rsp_img_line_end_d1; +assign sg2pack_img_layer_end = rsp_img_layer_end_d1; +assign sg2pack_img_p0_burst = rsp_img_p0_burst_size_d1; +assign sg2pack_img_p1_burst = rsp_img_p1_burst_size_d1; +// PKT_PACK_WIRE( sg2pack_info , sg2pack_img_ , sg2pack_push_data ) +assign sg2pack_push_data[3:0] = sg2pack_img_p0_burst[3:0]; +assign sg2pack_push_data[8:4] = sg2pack_img_p1_burst[4:0]; +assign sg2pack_push_data[9] = sg2pack_img_line_end ; +assign sg2pack_push_data[10] = sg2pack_img_layer_end ; +assign sg2pack_push_req = rsp_img_bundle_done_d1; +assign sg2pack_img_pvld = sg2pack_pop_req; +assign sg2pack_img_pd = sg2pack_pop_data; +assign sg2pack_pop_ready = sg2pack_img_prdy; +NV_NVDLA_CDMA_IMG_sg2pack_fifo u_NV_NVDLA_CDMA_IMG_sg2pack_fifo ( + .clk (nvdla_core_clk) + ,.reset_ (nvdla_core_rstn) + ,.wr_ready (sg2pack_push_ready) + ,.wr_req (sg2pack_push_req) + ,.wr_data (sg2pack_push_data[10:0]) + ,.rd_ready (sg2pack_pop_ready) + ,.rd_req (sg2pack_pop_req) + ,.rd_data (sg2pack_pop_data[10:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +assign sg2pack_height_total = height_cnt_total; +assign sg2pack_mn_enable = mn_enable_d1; +assign sg2pack_data_entries = data_entries; +assign sg2pack_entry_st = pre_entry_st_d1; +assign sg2pack_entry_mid = pre_entry_mid_d1; +assign sg2pack_entry_end = pre_entry_end_d1; +assign sg2pack_sub_h_st = pre_sub_h_st_d1; +assign sg2pack_sub_h_mid = pre_sub_h_mid_d1; +assign sg2pack_sub_h_end = pre_sub_h_end_d1; +//////////////////////////////////////////////////////////////////////// +// Global status // +//////////////////////////////////////////////////////////////////////// +assign sg_is_done_w = ~is_first_running & req_is_done & rsp_img_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"is_running\" -d \"sg_is_done_w\" -q sg_is_done"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg_is_done <= 1'b1; + end else begin + if ((is_running) == 1'b1) begin + sg_is_done <= sg_is_done_w; + // VCS coverage off + end else if ((is_running) == 1'b0) begin + end else begin + sg_is_done <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_stall_inc <= 1'b0; + end else begin + img_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_stall_clr <= 1'b0; + end else begin + img_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_stall_cen <= 1'b0; + end else begin + img_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_img_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = img_rd_stall_inc ^ dp2reg_img_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (img_rd_stall_inc && !dp2reg_img_rd_stall_dec)? stl_cnt_inc : (!img_rd_stall_inc && dp2reg_img_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (img_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (img_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_img_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_inc <= 1'b0; + end else begin + img_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_dec <= 1'b0; + end else begin + img_rd_latency_dec <= dma_rsp_fifo_ready & ~dma_rsp_dummy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_clr <= 1'b0; + end else begin + img_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_cen <= 1'b0; + end else begin + img_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign ltc_1_inc = (outs_dp2reg_img_rd_latency!=511) & img_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_img_rd_latency!=511) & img_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (img_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (img_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_img_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +assign ltc_2_dec = 1'b0; +assign ltc_2_inc = (~&dp2reg_img_rd_latency) & (|outs_dp2reg_img_rd_latency); +// ltc_2 adv logic +always @(*) begin + ltc_2_adv = ltc_2_inc ^ ltc_2_dec; +end +// ltc_2 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_2_cnt_ext[33:0] = {1'b0, 1'b0, ltc_2_cnt_cur}; + ltc_2_cnt_inc[33:0] = ltc_2_cnt_cur + 1'b1; // spyglass disable W164b + ltc_2_cnt_dec[33:0] = ltc_2_cnt_cur - 1'b1; // spyglass disable W164b + ltc_2_cnt_mod[33:0] = (ltc_2_inc && !ltc_2_dec)? ltc_2_cnt_inc : (!ltc_2_inc && ltc_2_dec)? ltc_2_cnt_dec : ltc_2_cnt_ext; + ltc_2_cnt_new[33:0] = (ltc_2_adv)? ltc_2_cnt_mod[33:0] : ltc_2_cnt_ext[33:0]; + ltc_2_cnt_nxt[33:0] = (img_rd_latency_clr)? 34'd0 : ltc_2_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// ltc_2 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_2_cnt_cur[31:0] <= 0; + end else begin + if (img_rd_latency_cen) begin + ltc_2_cnt_cur[31:0] <= ltc_2_cnt_nxt[31:0]; + end + end +end +// ltc_2 output logic +always @(*) begin + dp2reg_img_rd_latency[31:0] = ltc_2_cnt_cur[31:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_img_sg__img_read_response_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (dma_rd_rsp_vld & ~dma_rd_rsp_rdy); + endproperty +// Cover 0 : "(dma_rd_rsp_vld & ~dma_rd_rsp_rdy)" + FUNCPOINT_cdma_img_sg__img_read_response_block__0_COV : cover property (cdma_img_sg__img_read_response_block__0_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_height_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_planar_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_sec_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_sec_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_height_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_height_en & planar1_enable))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_burst_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_burst_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_46x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(img_entry_onfly_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rsp_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_vld_w & dma_rsp_fifo_ready))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_c0l0_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_c1l0_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_burst_cnt_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_burst_cnt_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_burst_size_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_burst_size_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_bundle_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_bundle_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Config error! Pixel height offset is not zero!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (is_running & (|reg2dp_pixel_y_offset))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data_entries_w is much to big!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_data_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_bundle_cnt_w is overflow!") zzz_assert_never_18x (nvdla_core_clk, `ASSERT_RESET, (req_img_p0_burst_en & mon_req_img_p0_bundle_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_sec_cnt_w is overflow!") zzz_assert_never_19x (nvdla_core_clk, `ASSERT_RESET, (req_img_p0_burst_en & mon_req_img_p0_sec_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_bundle_cnt_w is overflow!") zzz_assert_never_23x (nvdla_core_clk, `ASSERT_RESET, (req_img_p1_burst_en & mon_req_img_p1_bundle_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_sec_cnt_w is overflow!") zzz_assert_never_24x (nvdla_core_clk, `ASSERT_RESET, (req_img_p1_burst_en & mon_req_img_p1_sec_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_reg_en set when not running!") zzz_assert_never_25x (nvdla_core_clk, `ASSERT_RESET, (~is_running & req_reg_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_valid set when not running!") zzz_assert_never_26x (nvdla_core_clk, `ASSERT_RESET, (~is_running & req_valid)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_line_offset_w is overflow!") zzz_assert_never_29x (nvdla_core_clk, `ASSERT_RESET, (req_height_en & mon_req_img_p0_line_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_line_offset_w is overflow!") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (req_height_en & planar1_enable & mon_req_img_p1_line_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_burst_offset_w is overflow!") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (req_img_p0_burst_offset_en & mon_req_img_p0_burst_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_burst_offset_w is overflow!") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (req_img_p1_burst_offset_en & mon_req_img_p1_burst_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_size_out is overflow!") zzz_assert_never_45x (nvdla_core_clk, `ASSERT_RESET, (req_reg_en & mon_req_size_out)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! total_required_entry is overflow!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (mon_total_required_entry & ~is_cbuf_ready)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! total_required_entry is out of range!") zzz_assert_never_48x (nvdla_core_clk, `ASSERT_RESET, ((total_required_entry > 3840) & ~req_is_done_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! img_entry_onfly_w is overflow!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (mon_img_entry_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! img_entry_onfly_w is out of range!") zzz_assert_never_50x (nvdla_core_clk, `ASSERT_RESET, (img_entry_onfly_w > 3840)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! img_entry_onfly is not empty when idle!") zzz_assert_never_51x (nvdla_core_clk, `ASSERT_RESET, (~is_running & (|img_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Receive input data when not busy") zzz_assert_never_53x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_55x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_fifo_ready & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo idle when data return") zzz_assert_never_56x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_57x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > dma_rsp_size)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_58x (nvdla_core_clk, `ASSERT_RESET, (mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_59x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > 6'h30)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Data input when idle!") zzz_assert_never_60x (nvdla_core_clk, `ASSERT_RESET, (~is_running & dma_rd_rsp_vld)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_p1_vld_d1 valid when rsp_img_p0_vld_d1 not!") zzz_assert_never_71x (nvdla_core_clk, `ASSERT_RESET, (~rsp_img_p0_vld_d1 & rsp_img_p1_vld_d1)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_p0_burst_cnt_inc is overflow!") zzz_assert_never_84x (nvdla_core_clk, `ASSERT_RESET, (rsp_img_p0_burst_cnt_en & mon_rsp_img_p0_burst_cnt_inc & ~rsp_img_planar)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_p1_burst_cnt_inc is overflow!") zzz_assert_never_85x (nvdla_core_clk, `ASSERT_RESET, (rsp_img_p1_burst_cnt_en & mon_rsp_img_p1_burst_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_w_burst_size is out of range when planar0!") zzz_assert_never_86x (nvdla_core_clk, `ASSERT_RESET, (rsp_img_p0_burst_cnt_en & rsp_img_w_burst_size[4] & ~rsp_img_planar)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_is_done is 0 when not busy!") zzz_assert_never_88x (nvdla_core_clk, `ASSERT_RESET, (~is_running & ~rsp_img_is_done)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sg2pack_fifo push block!") zzz_assert_never_89x (nvdla_core_clk, `ASSERT_RESET, (sg2pack_push_req & ~sg2pack_push_ready)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sg2pack_fifo pop invalid!") zzz_assert_never_90x (nvdla_core_clk, `ASSERT_RESET, (~sg2pack_pop_req & sg2pack_pop_ready)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sg_is_done is 0 when not busy!") zzz_assert_never_92x (nvdla_core_clk, `ASSERT_RESET, (~is_running & ~sg_is_done)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_93x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && img_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_IMG_sg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v.vcp new file mode 100644 index 0000000..f369c87 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v.vcp @@ -0,0 +1,1430 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_sg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_IMG_sg ( + nvdla_core_clk + ,nvdla_core_rstn + ,img2status_dat_entries + ,img2status_dat_updt + ,img_dat2mcif_rd_req_ready + ,is_running + ,layer_st + ,mcif2img_dat_rd_rsp_pd + ,mcif2img_dat_rd_rsp_valid + ,pixel_order + ,pixel_planar + ,pixel_planar0_bundle_limit + ,pixel_planar0_bundle_limit_1st + ,pixel_planar0_byte_sft + ,pixel_planar0_lp_burst + ,pixel_planar0_lp_vld + ,pixel_planar0_rp_burst + ,pixel_planar0_rp_vld + ,pixel_planar0_width_burst + ,pixel_planar1_bundle_limit + ,pixel_planar1_bundle_limit_1st + ,pixel_planar1_byte_sft + ,pixel_planar1_lp_burst + ,pixel_planar1_lp_vld + ,pixel_planar1_rp_burst + ,pixel_planar1_rp_vld + ,pixel_planar1_width_burst + ,pwrbus_ram_pd + ,reg2dp_datain_addr_high_0 + ,reg2dp_datain_addr_high_1 + ,reg2dp_datain_addr_low_0 + ,reg2dp_datain_addr_low_1 + ,reg2dp_datain_height + ,reg2dp_datain_ram_type + ,reg2dp_dma_en + ,reg2dp_entries + ,reg2dp_line_stride + ,reg2dp_mean_format + ,reg2dp_op_en + ,reg2dp_pixel_y_offset + ,reg2dp_uv_line_stride + ,sg2pack_img_prdy + ,status2dma_free_entries + ,status2dma_fsm_switch + ,dp2reg_img_rd_latency + ,dp2reg_img_rd_stall +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,img2sbuf_p${i}_wr_addr +//: ,img2sbuf_p${i}_wr_data +//: ,img2sbuf_p${i}_wr_en +//: ); +//: } + ,img_dat2mcif_rd_req_pd + ,img_dat2mcif_rd_req_valid + ,mcif2img_dat_rd_rsp_ready + ,sg2pack_data_entries + ,sg2pack_entry_end + ,sg2pack_entry_mid + ,sg2pack_entry_st + ,sg2pack_height_total + ,sg2pack_img_pd + ,sg2pack_img_pvld + ,sg2pack_mn_enable + ,sg2pack_sub_h_end + ,sg2pack_sub_h_mid + ,sg2pack_sub_h_st + ,sg_is_done + ); +////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +output [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +output img_dat2mcif_rd_req_valid; +input img_dat2mcif_rd_req_ready; +input [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +input mcif2img_dat_rd_rsp_valid; +output mcif2img_dat_rd_rsp_ready; +input [14:0] img2status_dat_entries; +input img2status_dat_updt; +input is_running; +input layer_st; +input [10:0] pixel_order; +input pixel_planar; +input [3:0] pixel_planar0_bundle_limit; +input [3:0] pixel_planar0_bundle_limit_1st; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: input [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: input [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +input [3:0] pixel_planar0_lp_burst; +input pixel_planar0_lp_vld; +input [3:0] pixel_planar0_rp_burst; +input pixel_planar0_rp_vld; +input [13:0] pixel_planar0_width_burst; +input [4:0] pixel_planar1_bundle_limit; +input [4:0] pixel_planar1_bundle_limit_1st; +input [2:0] pixel_planar1_lp_burst; +input pixel_planar1_lp_vld; +input [2:0] pixel_planar1_rp_burst; +input pixel_planar1_rp_vld; +input [13:0] pixel_planar1_width_burst; +input [31:0] pwrbus_ram_pd; +input reg2dp_op_en; +input sg2pack_img_prdy; +input [14:0] status2dma_free_entries; +input status2dma_fsm_switch; +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: output [7:0] img2sbuf_p${i}_wr_addr; +//: output [${atmm}-1:0] img2sbuf_p${i}_wr_data; +//: output img2sbuf_p${i}_wr_en; +//: ); +//: } +output [14:0] sg2pack_data_entries; +output [14:0] sg2pack_entry_end; +output [14:0] sg2pack_entry_mid; +output [14:0] sg2pack_entry_st; +output [12:0] sg2pack_height_total; +output [10:0] sg2pack_img_pd; +output sg2pack_img_pvld; +output sg2pack_mn_enable; +output [3:0] sg2pack_sub_h_end; +output [3:0] sg2pack_sub_h_mid; +output [3:0] sg2pack_sub_h_st; +output sg_is_done; +input [2:0] reg2dp_pixel_y_offset; +input [12:0] reg2dp_datain_height; +input [0:0] reg2dp_datain_ram_type; +input [31:0] reg2dp_datain_addr_high_0; +input [31:0] reg2dp_datain_addr_low_0; +input [31:0] reg2dp_datain_addr_high_1; +input [31:0] reg2dp_datain_addr_low_1; +input [31:0] reg2dp_line_stride; +input [31:0] reg2dp_uv_line_stride; +input [0:0] reg2dp_mean_format; +input [13:0] reg2dp_entries; +input [0:0] reg2dp_dma_en; +output [31:0] dp2reg_img_rd_stall; +output [31:0] dp2reg_img_rd_latency; +////////////////////////////////////////////////////////// +reg [14:0] data_entries; +reg [13:0] data_height; +reg [4:0] dma_rsp_size_cnt; +reg [31:0] dp2reg_img_rd_latency; +reg [31:0] dp2reg_img_rd_stall; +reg [12:0] height_cnt_total; +reg [14:0] img_entry_onfly; +reg img_rd_latency_cen; +reg img_rd_latency_clr; +reg img_rd_latency_dec; +reg img_rd_latency_inc; +reg img_rd_stall_cen; +reg img_rd_stall_clr; +reg img_rd_stall_inc; +reg is_cbuf_ready; +reg is_running_d1; +reg ltc_1_adv; +reg [8:0] ltc_1_cnt_cur; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg ltc_2_adv; +reg [31:0] ltc_2_cnt_cur; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg mn_enable_d1; +reg [14:0] pre_entry_end_d1; +reg [14:0] pre_entry_mid_d1; +reg [14:0] pre_entry_st_d1; +reg [63:0] req_addr_d1; +reg req_bundle_end_d1; +reg req_end_d1; +reg req_grant_end_d1; +reg [12:0] req_height_cnt; +reg [63:0] req_img_p0_addr_base; +reg [3:0] req_img_p0_bundle_cnt; +reg [13:0] req_img_p0_burst_cnt; +reg [28:0] req_img_p0_burst_offset; +reg [31:0] req_img_p0_line_offset; +reg [1:0] req_img_p0_sec_cnt; +reg [63:0] req_img_p1_addr_base; +reg [4:0] req_img_p1_bundle_cnt; +reg [13:0] req_img_p1_burst_cnt; +reg [28:0] req_img_p1_burst_offset; +reg [31:0] req_img_p1_line_offset; +reg [1:0] req_img_p1_sec_cnt; +reg req_img_planar_cnt; +reg req_is_done; +reg req_is_dummy_d1; +reg req_line_end_d1; +reg req_line_st_d1; +reg req_planar_d1; +reg [4:0] req_size_d1; +reg [4:0] req_size_out_d1; +reg req_valid; +reg req_valid_d1; +reg rsp_img_1st_burst; +reg rsp_img_bundle_done_d1; +reg rsp_img_bundle_end; +reg [8*8 -1:0] rsp_img_c0l0; +reg [8*8 -1:0] rsp_img_c1l0; +reg rsp_img_end; +reg rsp_img_is_done; +reg rsp_img_layer_end_d1; +reg rsp_img_line_end; +reg rsp_img_line_end_d1; +reg rsp_img_line_st; +reg [7:0] rsp_img_p0_addr_d1; +reg [3:0] rsp_img_p0_burst_cnt; +reg [3:0] rsp_img_p0_burst_size_d1; +reg [8*8 -1:0] rsp_img_p0_data; +reg [8*8 -1:0] rsp_img_p0_data_d1; +reg [6:0] rsp_img_p0_planar0_idx; +reg [6:0] rsp_img_p0_planar1_idx; +reg rsp_img_p0_vld; +reg rsp_img_p0_vld_d1; +reg [7:0] rsp_img_p1_addr_d1; +reg [4:0] rsp_img_p1_burst_cnt; +reg [4:0] rsp_img_p1_burst_size_d1; +reg [8*8 -1:0] rsp_img_p1_data; +reg [8*8 -1:0] rsp_img_p1_data_d1; +reg [6:0] rsp_img_p1_planar0_idx; +reg [6:0] rsp_img_p1_planar1_idx; +reg rsp_img_p1_vld; +reg rsp_img_p1_vld_d1; +reg rsp_img_planar; +reg rsp_img_req_end; +reg rsp_img_vld; +reg [4:0] rsp_img_w_burst_size; +reg sg_is_done; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire [14:0] cur_required_entry; +wire [14:0] data_entries_w; +wire [13:0] data_height_w; +wire dma_blocking; +wire [63:0] dma_rd_req_addr; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [14:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire [64 -1:0] dma_rd_rsp_data; +wire [(64/8/8)-1:0] dma_rd_rsp_mask; +wire [( 64 + (64/8/8) )-1:0] dma_rd_rsp_pd; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [10:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire dma_rsp_blocking; +wire dma_rsp_bundle_end; +wire dma_rsp_dummy; +wire dma_rsp_end; +wire [10:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire dma_rsp_line_end; +wire dma_rsp_line_st; +wire [1:0] dma_rsp_mask; +wire dma_rsp_planar; +wire [4:0] dma_rsp_size; +wire [4:0] dma_rsp_size_cnt_inc; +wire [4:0] dma_rsp_size_cnt_w; +wire dma_rsp_vld; +wire [4:0] dma_rsp_w_burst_size; +wire dp2reg_img_rd_stall_dec; +wire [14:0] img_entry_onfly_add; +wire img_entry_onfly_en; +wire [14:0] img_entry_onfly_sub; +wire [14:0] img_entry_onfly_w; +wire is_1st_height; +wire is_cbuf_enough; +wire is_cbuf_ready_w; +wire is_first_running; +wire is_img_1st_burst; +wire is_img_bundle_end; +wire is_img_dummy; +wire is_img_last_burst; +wire is_img_last_planar; +wire is_last_height; +wire is_last_req; +wire is_p0_1st_burst; +wire is_p0_bundle_end; +wire is_p0_cur_sec_end; +wire is_p0_last_burst; +wire is_p0_req_real; +wire is_p1_1st_burst; +wire is_p1_bundle_end; +wire is_p1_cur_sec_end; +wire is_p1_last_burst; +wire is_p1_req_real; +wire ltc_1_dec; +wire ltc_1_inc; +wire ltc_2_dec; +wire ltc_2_inc; +wire mn_enable; +wire mon_data_entries_w; +wire mon_dma_rsp_size_cnt_inc; +wire mon_img_entry_onfly_w; +wire [3:0] mon_pre_entry_end_w; +wire [3:0] mon_pre_entry_st_w; +wire mon_req_height_cnt_inc; +wire mon_req_img_p0_addr; +wire mon_req_img_p0_bundle_cnt_w; +wire mon_req_img_p0_burst_offset_w; +wire mon_req_img_p0_line_offset_w; +wire mon_req_img_p0_sec_cnt_w; +wire mon_req_img_p1_addr; +wire mon_req_img_p1_bundle_cnt_w; +wire mon_req_img_p1_burst_offset_w; +wire mon_req_img_p1_line_offset_w; +wire mon_req_img_p1_sec_cnt_w; +wire mon_req_size_out; +wire mon_rsp_img_p0_burst_cnt_inc; +wire [8*8 -1:0] mon_rsp_img_p0_data_d1_w; +wire mon_rsp_img_p1_burst_cnt_inc; +wire [8*8 -1:0] mon_rsp_img_p1_data_d1_w; +wire mon_total_required_entry; +reg [8:0] outs_dp2reg_img_rd_latency; +wire planar1_enable; +wire [14:0] pre_entry_end_w; +wire [14:0] pre_entry_st_w; +reg [3:0] pre_sub_h_end_d1; +reg [3:0] pre_sub_h_mid_d1; +reg [3:0] pre_sub_h_st_d1; +wire rd_req_rdyi; +wire [63:0] req_addr; +wire req_adv; +wire req_bundle_end; +wire req_grant_end; +wire [12:0] req_height_cnt_inc; +wire [12:0] req_height_cnt_w; +wire req_height_en; +wire [4:0] req_img_burst_size; +wire [63:0] req_img_p0_addr; +wire [63:0] req_img_p0_addr_base_w; +wire [3:0] req_img_p0_bundle_cnt_w; +wire [14:0] req_img_p0_burst_cnt_dec; +wire [13:0] req_img_p0_burst_cnt_w; +wire req_img_p0_burst_en; +wire req_img_p0_burst_offset_en; +wire [28:0] req_img_p0_burst_offset_w; +wire [3:0] req_img_p0_burst_size; +wire [3:0] req_img_p0_cur_burst; +wire [31:0] req_img_p0_line_offset_w; +wire [1:0] req_img_p0_sec_cnt_w; +wire req_img_p0_sec_en; +wire [63:0] req_img_p1_addr; +wire [63:0] req_img_p1_addr_base_w; +wire [4:0] req_img_p1_bundle_cnt_w; +wire [14:0] req_img_p1_burst_cnt_dec; +wire [13:0] req_img_p1_burst_cnt_w; +wire req_img_p1_burst_en; +wire req_img_p1_burst_offset_en; +wire [28:0] req_img_p1_burst_offset_w; +wire [4:0] req_img_p1_burst_size; +wire [4:0] req_img_p1_cur_burst; +wire [31:0] req_img_p1_line_offset_w; +wire [1:0] req_img_p1_sec_cnt_w; +wire req_img_p1_sec_en; +wire req_img_planar_cnt_w; +wire req_img_planar_en; +wire req_img_reg_en; +wire req_is_done_w; +wire req_is_dummy; +wire req_line_end; +wire req_line_st; +wire req_ready_d1; +wire req_reg_en; +wire [4:0] req_size; +wire [4:0] req_size_out; +wire req_valid_d1_w; +wire req_valid_w; +wire [64 -1:0] rsp_dat; +wire rsp_img_1st_burst_w; +wire rsp_img_bundle_done; +wire rsp_img_c0l0_wr_en; +wire rsp_img_c1l0_wr_en; +wire [64 -1:0] rsp_img_data_sw_o0; +wire [64 -1:0] rsp_img_data_sw_o1; +wire [64 -1:0] rsp_img_data_sw_o3; +wire [64 -1:0] rsp_img_data_sw_o5; +wire [64 -1:0] rsp_img_data_sw_o9; +wire rsp_img_is_done_w; +wire [8*8 -1:0] rsp_img_l0_data; +wire [7:0] rsp_img_p0_addr; +wire rsp_img_p0_burst_cnt_en; +wire [3:0] rsp_img_p0_burst_cnt_inc; +wire [3:0] rsp_img_p0_burst_cnt_w; +wire rsp_img_p0_burst_size_en; +wire [3:0] rsp_img_p0_burst_size_w; +reg [8*8 -1:0] rsp_img_p0_cache_data; +reg [8*8 -1:0] rsp_img_p1_cache_data; +wire [8*8 -1:0] rsp_img_p0_data_d1_w; +wire [8*8 -1:0] rsp_img_p0_data_atmm1; +wire [8*8 -1:0] rsp_img_p0_data_atmm0; +wire [8*8 -1:0] rsp_img_p0_data_w; +wire rsp_img_p0_planar0_en; +wire [7:0] rsp_img_p0_planar0_idx_inc; +wire [6:0] rsp_img_p0_planar0_idx_w; +wire rsp_img_p0_planar1_en; +wire [7:0] rsp_img_p0_planar1_idx_inc; +wire [6:0] rsp_img_p0_planar1_idx_w; +wire rsp_img_p0_vld_d1_w; +wire rsp_img_p0_vld_w; +wire [7:0] rsp_img_p1_addr; +wire rsp_img_p1_burst_cnt_en; +wire [4:0] rsp_img_p1_burst_cnt_inc; +wire [4:0] rsp_img_p1_burst_cnt_w; +wire rsp_img_p1_burst_size_en; +wire [4:0] rsp_img_p1_burst_size_w; +wire [8*8 -1:0] rsp_img_p1_data_d1_w; +wire [8*8 -1:0] rsp_img_p1_data_w; +wire rsp_img_p1_planar0_en; +wire [7:0] rsp_img_p1_planar0_idx_inc; +wire [6:0] rsp_img_p1_planar0_idx_w; +wire rsp_img_p1_planar1_en; +wire [7:0] rsp_img_p1_planar1_idx_inc; +wire [6:0] rsp_img_p1_planar1_idx_w; +wire rsp_img_p1_vld_d1_w; +wire rsp_img_p1_vld_w; +wire [2:0] rsp_img_planar_idx_add; +wire [10:0] rsp_img_sel; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: wire [${atmmbw}-1:0] rsp_img_sft; +//: ); +wire rsp_img_vld_w; +wire sg2pack_img_layer_end; +wire sg2pack_img_line_end; +wire [3:0] sg2pack_img_p0_burst; +wire [4:0] sg2pack_img_p1_burst; +wire [10:0] sg2pack_pop_data; +wire sg2pack_pop_ready; +wire sg2pack_pop_req; +wire [10:0] sg2pack_push_data; +wire sg2pack_push_ready; +wire sg2pack_push_req; +wire sg_is_done_w; +wire [3:0] sub_h_end_limit; +wire sub_h_end_sel; +wire [3:0] sub_h_end_w; +wire [3:0] sub_h_mid_w; +wire [3:0] sub_h_st_limit; +wire sub_h_st_sel; +wire [3:0] sub_h_st_w; +wire [14:0] total_required_entry; +//////////////////////////////////////////////////////////////////////// +// general signal // +//////////////////////////////////////////////////////////////////////// +assign planar1_enable = pixel_planar; +assign data_height_w = reg2dp_datain_height + 1'b1; +assign mn_enable = (reg2dp_mean_format == 1'h1 ); +assign {mon_data_entries_w, data_entries_w} = reg2dp_entries + 1'b1; +assign is_first_running = is_running & ~is_running_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"mn_enable\" -q mn_enable_d1"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_height_w\" -q data_height"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"reg2dp_datain_height\" -q height_cnt_total"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"layer_st\" -d \"data_entries_w\" -q data_entries"); +//////////////////////////////////////////////////////////////////////// +// generator preparing parameters // +//////////////////////////////////////////////////////////////////////// +///////////// sub_h for total control ///////////// +assign sub_h_st_limit = 4'b1; +assign sub_h_mid_w = 4'h1; +assign sub_h_end_limit = 4'h1; +assign sub_h_st_sel = (~(|data_height[13:4]) && (data_height[3:0] <= sub_h_st_limit)); +assign sub_h_end_sel = (~(|data_height[13:4]) && (data_height[3:0] <= sub_h_end_limit)); +assign sub_h_st_w = sub_h_st_sel ? data_height[3:0] : sub_h_st_limit; +assign sub_h_end_w = sub_h_end_sel ? data_height[3:0] : sub_h_end_limit; +assign {mon_pre_entry_st_w, pre_entry_st_w} = sub_h_st_w * data_entries; +assign {mon_pre_entry_end_w, pre_entry_end_w} = sub_h_end_w * data_entries; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"sub_h_st_w\" -q pre_sub_h_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"sub_h_mid_w\" -q pre_sub_h_mid_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"is_first_running\" -d \"sub_h_end_w\" -q pre_sub_h_end_d1"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"is_first_running\" -d \"pre_entry_st_w\" -q pre_entry_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"is_first_running\" -d \"data_entries\" -q pre_entry_mid_d1"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"is_first_running\" -d \"pre_entry_end_w\" -q pre_entry_end_d1"); +//////////////////////////////////////////////////////////////////////// +// request generator for input image // +//////////////////////////////////////////////////////////////////////// +localparam SRC_DUMMY = 2'h0; +localparam SRC_P0 = 2'h1; +localparam SRC_P1 = 2'h2; +///////////// height counter ///////////// +assign is_1st_height = ~(|req_height_cnt); +assign is_last_height = (req_height_cnt == height_cnt_total); +assign {mon_req_height_cnt_inc, req_height_cnt_inc} = req_height_cnt + 1'b1; +assign req_height_cnt_w = is_first_running ? 13'b0 : req_height_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"req_height_en\" -d \"req_height_cnt_w\" -q req_height_cnt"); +///////////// image planar count ///////////// +assign is_img_last_planar = (req_img_planar_cnt == pixel_planar); +assign req_img_planar_cnt_w = (is_first_running | is_img_last_planar) ? 1'b0 : ~req_img_planar_cnt; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_img_planar_en\" -d \"req_img_planar_cnt_w\" -q req_img_planar_cnt"); +///////////// image planar 0 bundle and burst count ///////////// +assign {mon_req_img_p0_bundle_cnt_w, + req_img_p0_bundle_cnt_w} = (is_first_running | is_p0_last_burst) ? {1'b0, pixel_planar0_bundle_limit_1st} : + is_p0_bundle_end ? {1'b0, pixel_planar0_bundle_limit} : + req_img_p0_bundle_cnt - req_img_p0_cur_burst; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"req_img_p0_burst_en\" -d \"req_img_p0_bundle_cnt_w\" -q req_img_p0_bundle_cnt"); +assign req_img_p0_burst_cnt_dec = req_img_p0_burst_cnt - req_img_p0_bundle_cnt; +assign req_img_p0_cur_burst = req_img_p0_burst_cnt_dec[14] ? req_img_p0_burst_cnt[3:0] : req_img_p0_bundle_cnt; +assign req_img_p0_burst_cnt_w = ((is_first_running | is_p0_last_burst) & pixel_planar0_lp_vld) ? {{10{1'b0}}, pixel_planar0_lp_burst} : + ((is_first_running | is_p0_last_burst) & ~pixel_planar0_lp_vld) ? pixel_planar0_width_burst : + ((req_img_p0_sec_cnt == 2'h0) & is_p0_cur_sec_end) ? pixel_planar0_width_burst : + ((req_img_p0_sec_cnt == 2'h1) & is_p0_cur_sec_end) ? {{10{1'b0}}, pixel_planar0_rp_burst} : + req_img_p0_burst_cnt_dec[13:0]; +assign {mon_req_img_p0_sec_cnt_w, + req_img_p0_sec_cnt_w} = ((is_first_running | is_p0_last_burst) & pixel_planar0_lp_vld) ? 3'h0 : + ((is_first_running | is_p0_last_burst) & ~pixel_planar0_lp_vld) ? 3'h1 : req_img_p0_sec_cnt + 1'b1; +assign is_p0_cur_sec_end = (req_img_p0_burst_cnt <= {{10{1'b0}}, req_img_p0_bundle_cnt}); +assign is_p0_1st_burst = ((req_img_p0_burst_cnt == {{10{1'b0}}, pixel_planar0_lp_burst}) & (req_img_p0_sec_cnt == 2'h0)) | + ((req_img_p0_burst_cnt == pixel_planar0_width_burst) & (req_img_p0_sec_cnt == 2'h1) & ~pixel_planar0_lp_vld); +assign is_p0_last_burst = (is_p0_cur_sec_end & (req_img_p0_sec_cnt == 2'h1) & ~pixel_planar0_rp_vld) | + (is_p0_cur_sec_end & (req_img_p0_sec_cnt == 2'h2)); +assign is_p0_bundle_end = (req_img_p0_cur_burst == req_img_p0_bundle_cnt) | is_p0_last_burst; +assign req_img_p0_burst_size = req_img_p0_cur_burst; +assign is_p0_req_real = (req_img_p0_sec_cnt == 2'b1); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"req_img_p0_burst_en\" -d \"req_img_p0_burst_cnt_w\" -q req_img_p0_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_img_p0_sec_en\" -d \"req_img_p0_sec_cnt_w\" -q req_img_p0_sec_cnt"); +///////////// image planar 1 bundle and burst count ///////////// +assign {mon_req_img_p1_bundle_cnt_w, + req_img_p1_bundle_cnt_w} = (is_first_running | is_p1_last_burst) ? {1'b0, pixel_planar1_bundle_limit_1st} : + is_p1_bundle_end ? {1'b0, pixel_planar1_bundle_limit} : + req_img_p1_bundle_cnt - req_img_p1_cur_burst; +assign req_img_p1_burst_cnt_dec = req_img_p1_burst_cnt - req_img_p1_bundle_cnt; +assign req_img_p1_cur_burst = req_img_p1_burst_cnt_dec[14] ? req_img_p1_burst_cnt[4:0] : req_img_p1_bundle_cnt; +assign req_img_p1_burst_cnt_w = ((is_first_running | is_p1_last_burst) & pixel_planar1_lp_vld) ? {{11{1'b0}}, pixel_planar1_lp_burst} : + ((is_first_running | is_p1_last_burst) & ~pixel_planar1_lp_vld) ? pixel_planar1_width_burst : + ((req_img_p1_sec_cnt == 2'h0) & is_p1_cur_sec_end) ? pixel_planar1_width_burst : + ((req_img_p1_sec_cnt == 2'h1) & is_p1_cur_sec_end) ? {{11{1'b0}}, pixel_planar1_rp_burst} : + req_img_p1_burst_cnt_dec[13:0]; +assign {mon_req_img_p1_sec_cnt_w, + req_img_p1_sec_cnt_w} = ((is_first_running | is_p1_last_burst) & pixel_planar1_lp_vld) ? 3'h0 : + ((is_first_running | is_p1_last_burst) & ~pixel_planar1_lp_vld) ? 3'h1 : + req_img_p1_sec_cnt + 1'b1; +assign req_img_p1_burst_size = req_img_p1_cur_burst; +assign is_p1_cur_sec_end = req_img_p1_burst_cnt_dec[14] | (req_img_p1_burst_cnt == {{9{1'b0}}, req_img_p1_bundle_cnt}); +assign is_p1_1st_burst = ((req_img_p1_burst_cnt == {{11{1'b0}}, pixel_planar1_lp_burst}) & (req_img_p1_sec_cnt == 2'h0)) | + ((req_img_p1_burst_cnt == pixel_planar1_width_burst) & (req_img_p1_sec_cnt == 2'h1) & ~pixel_planar1_lp_vld); +assign is_p1_last_burst = (is_p1_cur_sec_end & (req_img_p1_sec_cnt == 2'h1) & ~pixel_planar1_rp_vld) | + (is_p1_cur_sec_end & (req_img_p1_sec_cnt == 2'h2)); +assign is_p1_bundle_end = (req_img_p1_cur_burst == req_img_p1_bundle_cnt) | is_p1_last_burst; +assign is_p1_req_real = (req_img_p1_sec_cnt == 2'b1); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"req_img_p1_burst_en\" -d \"req_img_p1_bundle_cnt_w\" -q req_img_p1_bundle_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"req_img_p1_burst_en\" -d \"req_img_p1_burst_cnt_w\" -q req_img_p1_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_img_p1_sec_en\" -d \"req_img_p1_sec_cnt_w\" -q req_img_p1_sec_cnt"); +///////////// image burst signal ///////////// +assign is_img_1st_burst = ~req_img_planar_cnt ? is_p0_1st_burst : is_p1_1st_burst; +assign is_img_last_burst = ~req_img_planar_cnt ? is_p0_last_burst : is_p1_last_burst; +assign is_img_bundle_end = ~req_img_planar_cnt ? is_p0_bundle_end : is_p1_bundle_end; +assign req_img_burst_size = ~req_img_planar_cnt ? {1'b0, req_img_p0_burst_size} : req_img_p1_burst_size; +assign is_img_dummy = ~req_img_planar_cnt ? ~is_p0_req_real : ~is_p1_req_real; +///////////// control signal ///////////// +assign req_valid_w = (~is_running) ? 1'b0 : + is_first_running ? 1'b1 : + (req_reg_en & is_last_req) ? 1'b0 : req_valid; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_w\" -q req_valid"); +assign req_adv = req_valid & (~req_valid_d1 | req_ready_d1); +assign is_last_req = (is_img_last_burst & is_img_last_planar & is_last_height); +assign req_img_reg_en = req_adv; +assign req_reg_en = req_adv; +assign req_img_p0_burst_en = is_first_running | (req_img_reg_en & ~req_img_planar_cnt); +assign req_img_p0_sec_en = is_first_running | (req_img_reg_en & ~req_img_planar_cnt & is_p0_cur_sec_end); +assign req_img_p1_burst_en = is_first_running | (req_img_reg_en & req_img_planar_cnt); +assign req_img_p1_sec_en = is_first_running | (req_img_reg_en & req_img_planar_cnt & is_p1_cur_sec_end); +assign req_img_p0_burst_offset_en = is_first_running | (req_img_reg_en & ~req_img_planar_cnt & (is_p0_req_real | is_p0_last_burst)); +assign req_img_p1_burst_offset_en = is_first_running | (req_img_reg_en & req_img_planar_cnt & (is_p1_req_real | is_p1_last_burst)); +assign req_img_planar_en = is_first_running | (req_img_reg_en & is_img_bundle_end); +assign req_height_en = is_first_running | (req_img_reg_en & is_img_last_burst & is_img_last_planar); +///////////// address line offset for image ///////////// +assign {mon_req_img_p0_line_offset_w, + req_img_p0_line_offset_w} = (is_first_running) ? 33'b0 : (req_img_p0_line_offset + reg2dp_line_stride); +assign {mon_req_img_p1_line_offset_w, + req_img_p1_line_offset_w} = (is_first_running) ? 33'b0 : (req_img_p1_line_offset + reg2dp_uv_line_stride); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"req_height_en\" -d \"req_img_p0_line_offset_w\" -q req_img_p0_line_offset"); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"req_height_en & planar1_enable\" -d \"req_img_p1_line_offset_w\" -q req_img_p1_line_offset"); +///////////// address burst offset for image ///////////// +//: my $atmm = 8; +//: my $k = 33 - int(log($atmm)/log(2)); +//: print qq( +//: assign {mon_req_img_p0_burst_offset_w, +//: req_img_p0_burst_offset_w} = (is_first_running | is_p0_last_burst) ? ${k}'b0 : (req_img_p0_burst_offset + req_img_p0_cur_burst); +//: assign {mon_req_img_p1_burst_offset_w, +//: req_img_p1_burst_offset_w} = (is_first_running | is_p1_last_burst) ? ${k}'b0 : (req_img_p1_burst_offset + req_img_p1_cur_burst); +//: ); +//: &eperl::flop("-nodeclare -rval \"{(${k}-1){1'b0}}\" -en \"req_img_p0_burst_offset_en\" -d \"req_img_p0_burst_offset_w\" -q req_img_p0_burst_offset"); +//: &eperl::flop("-nodeclare -rval \"{(${k}-1){1'b0}}\" -en \"req_img_p1_burst_offset_en\" -d \"req_img_p1_burst_offset_w\" -q req_img_p1_burst_offset"); +///////////// address base for image ///////////// +assign req_img_p0_addr_base_w = {reg2dp_datain_addr_high_0, reg2dp_datain_addr_low_0}; +assign req_img_p1_addr_base_w = {reg2dp_datain_addr_high_1, reg2dp_datain_addr_low_1}; +//: my $atmm = 8; +//: my $k = int(log($atmm)/log(2)); +//: print qq( +//: assign {mon_req_img_p0_addr, +//: req_img_p0_addr} = req_img_p0_addr_base + req_img_p0_line_offset + {req_img_p0_burst_offset,${k}'d0}; +//: assign {mon_req_img_p1_addr, +//: req_img_p1_addr} = req_img_p1_addr_base + req_img_p1_line_offset + {req_img_p1_burst_offset,${k}'d0}; +//: ); +//: &eperl::flop("-nodeclare -norst -en \"layer_st\" -d \"req_img_p0_addr_base_w\" -q req_img_p0_addr_base"); +//: &eperl::flop("-nodeclare -norst -en \"layer_st\" -d \"req_img_p1_addr_base_w\" -q req_img_p1_addr_base"); +///////////// request package ///////////// +assign req_valid_d1_w = ~is_running ? 1'b0 : + req_valid ? 1'b1 : + req_ready_d1 ? 1'b0 : req_valid_d1; +assign req_addr = req_img_planar_cnt ? req_img_p1_addr : req_img_p0_addr ; +assign req_size = req_img_burst_size; +assign {mon_req_size_out, + req_size_out} = req_size - 1'b1; +assign req_line_st = is_img_1st_burst; +assign req_bundle_end = (is_img_bundle_end & is_img_last_planar); +assign req_line_end = (is_img_last_burst & is_img_last_planar); +assign req_grant_end = (is_img_last_burst & is_img_last_planar); +assign req_is_dummy = is_img_dummy; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_d1_w\" -q req_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"{64{1'b0}}\" -en \"req_reg_en\" -d \"req_addr\" -q req_addr_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"req_reg_en\" -d \"req_size\" -q req_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"req_reg_en\" -d \"req_size_out\" -q req_size_out_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_line_st\" -q req_line_st_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_bundle_end\" -q req_bundle_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_line_end\" -q req_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_grant_end\" -q req_grant_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"is_last_req\" -q req_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_img_planar_cnt\" -q req_planar_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_reg_en\" -d \"req_is_dummy\" -q req_is_dummy_d1"); +`ifdef NVDLA_PRINT_CDMA +always @ (posedge nvdla_core_clk) +begin + if(req_valid_d1 & req_ready_d1) + begin + $display("[CDMA IMG REQ] Dummy = %d, Addr = 0x%010h, size = %0d, time = %0d", req_is_dummy_d1, req_addr_d1, req_size_d1, $stime); + end +end +`endif +//////////////////////////////////////////////////////////////////////// +// request arbiter and cbuf entry monitor // +//////////////////////////////////////////////////////////////////////// +assign req_ready_d1 = ((dma_rd_req_rdy | req_is_dummy_d1) & dma_req_fifo_ready & is_cbuf_ready); +assign req_is_done_w = is_first_running ? 1'b0 : + (req_valid_d1 & req_ready_d1 & req_end_d1) ? 1'b1 : req_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"req_is_done_w\" -q req_is_done"); +///////////// cbuf monitor ///////////// +assign cur_required_entry = (is_cbuf_ready | req_is_done) ? 15'b0 : + is_last_height ? pre_entry_end_d1 : + is_1st_height ? pre_entry_st_d1 : pre_entry_mid_d1; +assign {mon_total_required_entry, + total_required_entry} = cur_required_entry + img_entry_onfly; +assign is_cbuf_enough = (status2dma_free_entries >= total_required_entry); +assign is_cbuf_ready_w = (~is_running | is_first_running) ? 1'b0 : + (req_valid_d1 & req_ready_d1 & req_grant_end_d1) ? 1'b0 : + (~is_cbuf_ready) ? is_cbuf_enough : is_cbuf_ready; +assign img_entry_onfly_sub = img2status_dat_updt ? img2status_dat_entries : 15'b0; +assign img_entry_onfly_add = (~req_is_done & is_cbuf_enough & ~is_cbuf_ready) ? cur_required_entry : 15'b0; +assign {mon_img_entry_onfly_w, + img_entry_onfly_w} = img_entry_onfly + img_entry_onfly_add - img_entry_onfly_sub; +assign img_entry_onfly_en = (~req_is_done & is_cbuf_enough & ~is_cbuf_ready) | img2status_dat_updt; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_cbuf_ready_w\" -q is_cbuf_ready"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"img_entry_onfly_en\" -d \"img_entry_onfly_w\" -q img_entry_onfly"); +//////////////////////////////////////////////////////////////////////// +// CDMA IMG read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_datain_ram_type) + ,.mcif_rd_req_pd (img_dat2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2img_dat_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2img_dat_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2img_dat_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////// +// PKT_PACK_WIRE( dma_read_cmd , dma_rd_req_ , dma_rd_req_pd ) +assign dma_rd_req_pd[32 -1:0] = dma_rd_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_rd_req_size[14:0]; +assign dma_rd_req_vld = req_valid_d1 & dma_req_fifo_ready & is_cbuf_ready & ~req_is_dummy_d1; +assign dma_rd_req_addr = req_addr_d1; +assign dma_rd_req_size = {{10{1'b0}}, req_size_out_d1}; +assign dma_rd_req_type = reg2dp_datain_ram_type; +assign dma_rd_rsp_rdy = ~dma_blocking; +assign dma_blocking = dma_rsp_blocking; +NV_NVDLA_CDMA_IMG_fifo u_NV_NVDLA_CDMA_IMG_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[10:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w + ,.rd_data (dma_rsp_fifo_data[10:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = req_valid_d1 & is_cbuf_ready & (dma_rd_req_rdy | req_is_dummy_d1) ; +assign dma_req_fifo_data = {req_planar_d1, + req_end_d1, + req_line_end_d1, + req_bundle_end_d1, + req_line_st_d1, + req_is_dummy_d1, + req_size_d1[4:0]}; +//////////////////////////////////////////////////////////////////////// +// CDMA IMG read response logic // +//////////////////////////////////////////////////////////////////////// +assign dma_rd_rsp_data[64 -1:0] = dma_rd_rsp_pd[64 -1:0]; +assign dma_rd_rsp_mask[(64/8/8)-1:0] = dma_rd_rsp_pd[( 64 + (64/8/8) )-1:64]; +assign {dma_rsp_planar, + dma_rsp_end, + dma_rsp_line_end, + dma_rsp_bundle_end, + dma_rsp_line_st, + dma_rsp_dummy, + dma_rsp_size} = dma_rsp_fifo_data; +assign dma_rsp_blocking = (dma_rsp_fifo_req & dma_rsp_dummy); +assign dma_rsp_mask[0] = (~dma_rsp_fifo_req) ? 1'b0 : + ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[0]) : 1'b1; +//: my $msk = (64/8/8); +//: if($msk >= 2) { +//: print qq( +//: assign dma_rsp_mask[1] = (~dma_rsp_fifo_req) ? 1'b0 : +//: ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[1]) : +//: (dma_rsp_size[4:1] == dma_rsp_size_cnt[4:1]) ? 1'b0 : 1'b1; +//: ); +//: } elsif($msk == 4) { +//: print qq( +//: assign dma_rsp_mask[2] = (~dma_rsp_fifo_req) ? 1'b0 : +//: ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[2]) : +//: ((dma_rsp_size[4:2] == dma_rsp_size_cnt[4:2]) & (&dma_rsp_size_cnt[11])) ? 1'b0 : 1'b1; +//: assign dma_rsp_mask[3] = (~dma_rsp_fifo_req) ? 1'b0 : +//: ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[3]) : +//: (dma_rsp_size[4:2] == dma_rsp_size_cnt[4:2]) ? 1'b0 : 1'b1; +//: ); +//: } +assign {mon_dma_rsp_size_cnt_inc, + dma_rsp_size_cnt_inc} = dma_rsp_size_cnt +//: my $msk = (64/8/8); +//: foreach my $i (0..$msk-1) { +//: print qq( +//: + dma_rsp_mask[$i] +//: ); +//: } +//: print qq( ; ); +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 5'b0 : dma_rsp_size_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"dma_rsp_vld\" -d \"dma_rsp_size_cnt_w\" -q dma_rsp_size_cnt"); +assign dma_rsp_vld = dma_rsp_fifo_req & (dma_rsp_dummy | dma_rd_rsp_vld); +assign dma_rsp_fifo_ready = (dma_rsp_vld & (dma_rsp_size_cnt_inc == dma_rsp_size)); +//////////////////////////////////////////////////////////////////////// +// CDMA pixel data response logic stage 1 // +//////////////////////////////////////////////////////////////////////// +assign rsp_img_vld_w = dma_rsp_vld; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_img_vld_w\" -q rsp_img_vld"); +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num-1) { +//: print qq( +//: assign rsp_img_p${i}_vld_w = dma_rsp_mask[${i}]; +//: +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: if (!nvdla_core_rstn) begin +//: rsp_img_p${i}_vld <= 1'b0; +//: end else begin +//: rsp_img_p${i}_vld <= rsp_img_p${i}_vld_w; +//: end +//: +//: always @(posedge nvdla_core_clk) +//: if (rsp_img_p${i}_vld_w) begin +//: rsp_img_p${i}_data <= rsp_img_p${i}_data_w; +//: end +//: ); +//: } +assign rsp_dat = dma_rd_rsp_data; +//10'h1 ABGR, VU, single, unchange +//10'h2 ARGB, AYUV, 8bpp +//10'h4 ARGB, AYUV, 16bpp +//10'h8 BGRA, VUYA, 8bpp +//10'h10 BGRA, VUYA, 16bpp +//10'h20 RGBA, YUVA, 8bpp +//10'h40 ARGB, AYUV, packed_10b +//10'h80 BGRA, YUVA, packed_10b +//10'h100 RGBA, packed_10b +//10'h200 UV, 8bpp +//10'h400 UV, 16bpp +assign rsp_img_sel[0] = pixel_order[0] | (~dma_rsp_planar & pixel_planar); +assign rsp_img_sel[1] = pixel_order[1]; +assign rsp_img_sel[2] = pixel_order[2]; +assign rsp_img_sel[3] = pixel_order[3]; +assign rsp_img_sel[4] = pixel_order[4]; +assign rsp_img_sel[5] = pixel_order[5]; +assign rsp_img_sel[6] = pixel_order[6]; +assign rsp_img_sel[7] = pixel_order[7]; +assign rsp_img_sel[8] = pixel_order[8]; +assign rsp_img_sel[9] = pixel_order[9] & dma_rsp_planar; +assign rsp_img_sel[10] = pixel_order[10] & dma_rsp_planar; +//////// reordering //////// +assign rsp_img_data_sw_o0 = rsp_dat; +assign rsp_img_data_sw_o1 = { +//: my $dmaif = 64/32;## +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*32+31:${k}*32+24], rsp_dat[${k}*32+7:${k}*32], rsp_dat[${k}*32+15:${k}*32+8], rsp_dat[${k}*32+23:${k}*32+16], +//: ); +//: } +//: } +//: print " rsp_dat[0*32+31:0*32+24], rsp_dat[0*32+7:0*32], rsp_dat[0*32+15:0*32+8], rsp_dat[0*32+23:0*32+16]}; \n"; +//: +//: +//: print " assign rsp_img_data_sw_o3 = { \n"; +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*32+7:${k}*32], rsp_dat[${k}*32+31:${k}*32+24], rsp_dat[${k}*32+23:${k}*32+16], rsp_dat[${k}*32+15:${k}*32+8], +//: ); +//: } +//: } +//: print " rsp_dat[0*32+7:0*32], rsp_dat[0*32+31:0*32+24], rsp_dat[0*32+23:0*32+16], rsp_dat[0*32+15:0*32+8]}; \n"; +//: +//: +//: print " assign rsp_img_data_sw_o5 = { \n"; +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*32+7:${k}*32], rsp_dat[${k}*32+15:${k}*32+8], rsp_dat[${k}*32+23:${k}*32+16], rsp_dat[${k}*32+31:${k}*32+24], +//: ); +//: } +//: } +//: print " rsp_dat[0*32+7:0*32], rsp_dat[0*32+15:0*32+8], rsp_dat[0*32+23:0*32+16], rsp_dat[0*32+31:0*32+24]}; \n"; +//: my $dmaif = 64/16; ## +//: print " assign rsp_img_data_sw_o9 = { \n"; +//: if($dmaif > 1) { +//: foreach my $i (0..$dmaif-2) { +//: my $k = $dmaif - $i -1; +//: print qq( +//: rsp_dat[${k}*16+7:${k}*16], rsp_dat[${k}*16+15:${k}*16+8], +//: ); +//: } +//: } +//: print " rsp_dat[0*16+7:0*16], rsp_dat[0*16+15:0*16+8]}; \n"; +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $atmm_num = ($dmaif / $atmm); +//: print " assign { \n"; +//: if($atmm_num > 1) { +//: foreach my $i (0..$atmm_num -2) { +//: my $k = $atmm_num - $i -1; +//: print " rsp_img_p${k}_data_w, "; +//: } +//: } + rsp_img_p0_data_w} = ({64{rsp_img_sel[0]}} & rsp_img_data_sw_o0) | + ({64{rsp_img_sel[1]}} & rsp_img_data_sw_o1) | + ({64{rsp_img_sel[3]}} & rsp_img_data_sw_o3) | + ({64{rsp_img_sel[5]}} & rsp_img_data_sw_o5) | + ({64{rsp_img_sel[9]}} & rsp_img_data_sw_o9); +assign dma_rsp_w_burst_size = dma_rsp_size; +assign rsp_img_1st_burst_w = dma_rsp_line_st & (dma_rsp_size_cnt == 5'h0); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_planar\" -q rsp_img_planar"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"rsp_img_1st_burst_w\" -q rsp_img_1st_burst"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_line_st\" -q rsp_img_line_st"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_fifo_ready\" -q rsp_img_req_end"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"rsp_img_vld_w & dma_rsp_fifo_ready\" -d \"dma_rsp_w_burst_size\" -q rsp_img_w_burst_size"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_line_end & dma_rsp_fifo_ready\" -q rsp_img_line_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_bundle_end & dma_rsp_fifo_ready\" -q rsp_img_bundle_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_vld_w\" -d \"dma_rsp_end & dma_rsp_fifo_ready\" -q rsp_img_end"); +//////////////////////////////////////////////////////////////////////// +// CDMA pixel data response logic stage 2: cache and sbuf write // +//////////////////////////////////////////////////////////////////////// +//////// cache line control //////// +assign rsp_img_c0l0_wr_en = (rsp_img_p0_vld & (~rsp_img_planar)); +assign rsp_img_c1l0_wr_en = (rsp_img_p0_vld & rsp_img_planar); +//assign rsp_img_l0_data = rsp_img_p1_vld ? rsp_img_p1_data : rsp_img_p0_data; +// need cache more when more dmaif/atmm +//: my $dmaif = 64; +//: my $atmm = (8 * 8); +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: /////rsp_img_p0_cache_data p0 means planar 0 +//: ); +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c0l0_wr_en \" -d \"rsp_img_p0_data\" -q rsp_img_p0_cache_data"); +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c1l0_wr_en \" -d \"rsp_img_p0_data\" -q rsp_img_p1_cache_data"); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign rsp_img_l0_data = rsp_img_p1_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign rsp_img_l0_data = rsp_img_p3_vld ? rsp_img_p3_data : rsp_img_p2_vld ? rsp_img_p2_data : rsp_img_p1_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: assign rsp_img_l1_data = rsp_img_p3_vld ? rsp_img_p2_data : rsp_img_p2_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: assign rsp_img_l2_data = rsp_img_p3_vld ? rsp_img_p1_data : rsp_img_p0_data; +//: ); +//: } +//: +//: if($atmm_num > 1) { +//: foreach my $i(0..$atmm_num-2) { +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c0l${i}_wr_en\" -d \"rsp_img_l${i}_data\" -q rsp_img_c0l${i}"); +//: &eperl::flop("-nodeclare -rval \"{${atmm}{1'b0}}\" -en \"rsp_img_c1l${i}_wr_en\" -d \"rsp_img_l${i}_data\" -q rsp_img_c1l${i}"); +//: print " //////// data write control logic: normal write back //////// \n"; +//: print " assign rsp_img_p${i}_cache_data = ({${atmm} {~rsp_img_planar}} & rsp_img_c0l${i}) | ({${atmm} { rsp_img_planar}} & rsp_img_c1l${i}); \n"; +//: } +//: } +//per atmm +//: my $dmaif = 64; +//: my $atmm = (8*8); +//: my $atmm_num = ($dmaif / $atmm); +//: if($atmm_num == 1) { +//: print qq( +//: assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst); +//: +//: assign rsp_img_p0_data_atmm0 = rsp_img_p0_data; +//: assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm0,(rsp_img_c0l0_wr_en ? rsp_img_p0_cache_data : rsp_img_p1_cache_data)} >> {rsp_img_sft, 3'b0}); +//: +//: assign rsp_img_planar_idx_add = 3'h1; +//: ); +//: } elsif ($atmm_num == 2) { +//: print qq( +//: assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst | rsp_img_p1_vld); +//: assign rsp_img_p1_vld_d1_w = rsp_img_p1_vld & (~rsp_img_1st_burst ); +//: +//: assign rsp_img_p0_data_atmm0 = rsp_img_1st_burst ? rsp_img_p0_data : rsp_img_p0_cache_data; +//: assign rsp_img_p0_data_atmm1 = rsp_img_1st_burst ? rsp_img_p1_data : rsp_img_p0_data; +//: assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: assign {mon_rsp_img_p1_data_d1_w, rsp_img_p1_data_d1_w} = ({rsp_img_p1_data, rsp_img_p0_data} >> {rsp_img_sft, 3'b0}); +//: +//: assign rsp_img_planar_idx_add = rsp_img_p1_vld_d1_w ? 3'h2 : 3'h1; +//: ); +//: } elsif ($atmm_num == 4) { +//: print qq( +//: assign rsp_img_p0_vld_d1_w = rsp_img_p0_vld & (~rsp_img_1st_burst | rsp_img_p1_vld | rsp_img_p2_vld | rsp_img_p3_vld ); +//: assign rsp_img_p1_vld_d1_w = rsp_img_p1_vld & (~rsp_img_1st_burst | rsp_img_p2_vld | rsp_img_p3_vld ); +//: assign rsp_img_p2_vld_d1_w = rsp_img_p2_vld & (~rsp_img_1st_burst | rsp_img_p3_vld ); +//: assign rsp_img_p3_vld_d1_w = rsp_img_p3_vld & (~rsp_img_1st_burst ); +//: +//: assign rsp_img_p0_data_atmm0 = rsp_img_1st_burst ? rsp_img_p0_data : rsp_img_p0_cache_data; +//: assign rsp_img_p0_data_atmm1 = rsp_img_1st_burst ? rsp_img_p1_data : rsp_img_p1_cache_data; +//: assign rsp_img_p0_data_atmm2 = rsp_img_1st_burst ? rsp_img_p2_data : rsp_img_p2_cache_data; +//: assign rsp_img_p0_data_atmm3 = rsp_img_1st_burst ? rsp_img_p3_data : rsp_img_p0_data; +//: // assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm3, rsp_img_p0_data_atmm2, rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: // assign {mon_rsp_img_p1_data_d1_w, rsp_img_p1_data_d1_w} = ({rsp_img_p0_data_atmm3, rsp_img_p0_data_atmm2, rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: // assign {mon_rsp_img_p2_data_d1_w, rsp_img_p2_data_d1_w} = ({rsp_img_p0_data_atmm3, rsp_img_p0_data_atmm2, rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//: // assign {mon_rsp_img_p3_data_d1_w, rsp_img_p3_data_d1_w} = ({rsp_img_p3_data, rsp_img_p2_data, rsp_img_p1_data, rsp_img_p0_data} >> {rsp_img_sft, 3'b0}); +//: +//: assign rsp_img_planar_idx_add = rsp_img_p3_vld_d1_w ? 3'h4 : rsp_img_p2_vld_d1_w ? 3'h3 : rsp_img_p1_vld_d1_w ? 3'h2 : 3'h1; +//: ); +//: } +//: foreach my $i(0..$atmm_num -1) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_img_p${i}_vld_d1_w\" -q rsp_img_p${i}_vld_d1"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_img_p${i}_vld_d1_w\" -d \"rsp_img_p${i}_data_d1_w\" -q rsp_img_p${i}_data_d1"); +//: } +//assign rsp_img_p0_data_atmm0 = rsp_img_1st_burst ? rsp_img_p0_data : rsp_img_p0_cache_data; +//assign rsp_img_p0_data_atmm1 = rsp_img_1st_burst ? rsp_img_p1_data : rsp_img_p0_data; +//assign {mon_rsp_img_p0_data_d1_w, rsp_img_p0_data_d1_w} = ({rsp_img_p0_data_atmm1, rsp_img_p0_data_atmm0} >> {rsp_img_sft, 3'b0}); +//assign {mon_rsp_img_p1_data_d1_w, rsp_img_p1_data_d1_w} = ({rsp_img_p1_data, rsp_img_p0_data} >> {rsp_img_sft, 3'b0}); +assign rsp_img_sft = rsp_img_planar ? pixel_planar1_byte_sft : pixel_planar0_byte_sft; +//////// data write control logic: normal write back //////// +//assign rsp_img_planar_idx_add = rsp_img_p1_vld_d1_w ? 2'h2 : 2'h1; +//: my $dmaif = 64; +//: my $atmm = (8*8); +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: assign rsp_img_p${i}_planar0_idx_inc = rsp_img_p${i}_planar0_idx + rsp_img_planar_idx_add; +//: assign rsp_img_p${i}_planar1_idx_inc = rsp_img_p${i}_planar1_idx + rsp_img_planar_idx_add; +//: assign rsp_img_p${i}_planar0_idx_w = is_first_running ? 7'b${i} : rsp_img_p${i}_planar0_idx_inc[8 -2:0]; +//: assign rsp_img_p${i}_planar1_idx_w = is_first_running ? 7'b${i} : rsp_img_p${i}_planar1_idx_inc[8 -2:0]; +//: assign rsp_img_p${i}_planar0_en = is_first_running | (rsp_img_p${i}_vld_d1_w & ~rsp_img_planar); +//: assign rsp_img_p${i}_planar1_en = is_first_running | (rsp_img_p${i}_vld_d1_w & rsp_img_planar); +//: assign rsp_img_p${i}_addr = (~rsp_img_planar) ? {1'b0, rsp_img_p${i}_planar0_idx[0], rsp_img_p${i}_planar0_idx[8 -2:1]} : +//: {1'b1, rsp_img_p${i}_planar1_idx[0], rsp_img_p${i}_planar1_idx[8 -2:1]}; +//: ); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rsp_img_p${i}_planar0_en\" -d \"rsp_img_p${i}_planar0_idx_w\" -q rsp_img_p${i}_planar0_idx"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"rsp_img_p${i}_planar1_en\" -d \"rsp_img_p${i}_planar1_idx_w\" -q rsp_img_p${i}_planar1_idx"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_img_p${i}_vld_d1_w\" -d \"rsp_img_p${i}_addr\" -q rsp_img_p${i}_addr_d1"); +//: } +//////// data write control logic: MISC output //////// +assign {mon_rsp_img_p0_burst_cnt_inc, + rsp_img_p0_burst_cnt_inc} = rsp_img_p0_burst_cnt + rsp_img_w_burst_size[3:0] - rsp_img_line_st; +assign {mon_rsp_img_p1_burst_cnt_inc, + rsp_img_p1_burst_cnt_inc} = rsp_img_p1_burst_cnt + rsp_img_w_burst_size - rsp_img_line_st; +assign rsp_img_p0_burst_cnt_w = is_first_running ? 4'b0 : + (rsp_img_vld & rsp_img_bundle_end) ? 4'b0 : + (~rsp_img_planar) ? rsp_img_p0_burst_cnt_inc : rsp_img_p0_burst_cnt; +assign rsp_img_p1_burst_cnt_w = is_first_running ? 5'b0 : + (rsp_img_vld & rsp_img_bundle_end) ? 5'b0 : + (rsp_img_planar) ? rsp_img_p1_burst_cnt_inc : rsp_img_p1_burst_cnt; +assign rsp_img_bundle_done = (rsp_img_vld & rsp_img_bundle_end); +assign rsp_img_p0_burst_size_w = ~rsp_img_planar ? rsp_img_p0_burst_cnt_inc : rsp_img_p0_burst_cnt; +assign rsp_img_p1_burst_size_w = rsp_img_p1_burst_cnt_inc; +assign rsp_img_p0_burst_cnt_en = is_first_running | (rsp_img_vld & rsp_img_req_end); +assign rsp_img_p1_burst_cnt_en = is_first_running | (rsp_img_vld & rsp_img_req_end & pixel_planar); +assign rsp_img_p0_burst_size_en = is_first_running | (rsp_img_vld & rsp_img_bundle_end); +assign rsp_img_p1_burst_size_en = is_first_running | (rsp_img_vld & rsp_img_bundle_end & pixel_planar); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"rsp_img_p0_burst_cnt_en\" -d \"rsp_img_p0_burst_cnt_w\" -q rsp_img_p0_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"rsp_img_p1_burst_cnt_en\" -d \"rsp_img_p1_burst_cnt_w\" -q rsp_img_p1_burst_cnt"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"rsp_img_p0_burst_size_en\" -d \"rsp_img_p0_burst_size_w\" -q rsp_img_p0_burst_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"rsp_img_p1_burst_size_en\" -d \"rsp_img_p1_burst_size_w\" -q rsp_img_p1_burst_size_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_img_bundle_done\" -q rsp_img_bundle_done_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_bundle_done\" -d \"rsp_img_line_end\" -q rsp_img_line_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_img_bundle_done\" -d \"rsp_img_end\" -q rsp_img_layer_end_d1"); +//////// data write control logic: status //////// +assign rsp_img_is_done_w = is_first_running ? 1'b0 : + (rsp_img_end & rsp_img_line_end) ? 1'b1 : rsp_img_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"is_running\" -d \"rsp_img_is_done_w\" -q rsp_img_is_done"); +//////////////////////////////////////////////////////////////////////// +// Shared buffer write signals // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i (0..$atmm_num -1) { +//: print qq( +//: assign img2sbuf_p${i}_wr_addr = rsp_img_p${i}_addr_d1; +//: assign img2sbuf_p${i}_wr_data = rsp_img_p${i}_data_d1; +//: assign img2sbuf_p${i}_wr_en = rsp_img_p${i}_vld_d1; +//: ); +//: } +//assign img2sbuf_p0_wr_en = rsp_img_p0_vld_d1; +//assign img2sbuf_p1_wr_en = rsp_img_p1_vld_d1; +//assign img2sbuf_p0_wr_addr = rsp_img_p0_addr_d1; +//assign img2sbuf_p1_wr_addr = rsp_img_p1_addr_d1; +//assign img2sbuf_p0_wr_data = rsp_img_p0_data_d1; +//assign img2sbuf_p1_wr_data = rsp_img_p1_data_d1; +//////////////////////////////////////////////////////////////////////// +// Signal from SG to PACK // +//////////////////////////////////////////////////////////////////////// +assign sg2pack_img_line_end = rsp_img_line_end_d1; +assign sg2pack_img_layer_end = rsp_img_layer_end_d1; +assign sg2pack_img_p0_burst = rsp_img_p0_burst_size_d1; +assign sg2pack_img_p1_burst = rsp_img_p1_burst_size_d1; +// PKT_PACK_WIRE( sg2pack_info , sg2pack_img_ , sg2pack_push_data ) +assign sg2pack_push_data[3:0] = sg2pack_img_p0_burst[3:0]; +assign sg2pack_push_data[8:4] = sg2pack_img_p1_burst[4:0]; +assign sg2pack_push_data[9] = sg2pack_img_line_end ; +assign sg2pack_push_data[10] = sg2pack_img_layer_end ; +assign sg2pack_push_req = rsp_img_bundle_done_d1; +assign sg2pack_img_pvld = sg2pack_pop_req; +assign sg2pack_img_pd = sg2pack_pop_data; +assign sg2pack_pop_ready = sg2pack_img_prdy; +NV_NVDLA_CDMA_IMG_sg2pack_fifo u_NV_NVDLA_CDMA_IMG_sg2pack_fifo ( + .clk (nvdla_core_clk) + ,.reset_ (nvdla_core_rstn) + ,.wr_ready (sg2pack_push_ready) + ,.wr_req (sg2pack_push_req) + ,.wr_data (sg2pack_push_data[10:0]) + ,.rd_ready (sg2pack_pop_ready) + ,.rd_req (sg2pack_pop_req) + ,.rd_data (sg2pack_pop_data[10:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +assign sg2pack_height_total = height_cnt_total; +assign sg2pack_mn_enable = mn_enable_d1; +assign sg2pack_data_entries = data_entries; +assign sg2pack_entry_st = pre_entry_st_d1; +assign sg2pack_entry_mid = pre_entry_mid_d1; +assign sg2pack_entry_end = pre_entry_end_d1; +assign sg2pack_sub_h_st = pre_sub_h_st_d1; +assign sg2pack_sub_h_mid = pre_sub_h_mid_d1; +assign sg2pack_sub_h_end = pre_sub_h_end_d1; +//////////////////////////////////////////////////////////////////////// +// Global status // +//////////////////////////////////////////////////////////////////////// +assign sg_is_done_w = ~is_first_running & req_is_done & rsp_img_is_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"is_running\" -d \"sg_is_done_w\" -q sg_is_done"); +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_stall_inc <= 1'b0; + end else begin + img_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_stall_clr <= 1'b0; + end else begin + img_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_stall_cen <= 1'b0; + end else begin + img_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_img_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = img_rd_stall_inc ^ dp2reg_img_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (img_rd_stall_inc && !dp2reg_img_rd_stall_dec)? stl_cnt_inc : (!img_rd_stall_inc && dp2reg_img_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (img_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (img_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_img_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_inc <= 1'b0; + end else begin + img_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_dec <= 1'b0; + end else begin + img_rd_latency_dec <= dma_rsp_fifo_ready & ~dma_rsp_dummy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_clr <= 1'b0; + end else begin + img_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + img_rd_latency_cen <= 1'b0; + end else begin + img_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign ltc_1_inc = (outs_dp2reg_img_rd_latency!=511) & img_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_img_rd_latency!=511) & img_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (img_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (img_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_img_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +assign ltc_2_dec = 1'b0; +assign ltc_2_inc = (~&dp2reg_img_rd_latency) & (|outs_dp2reg_img_rd_latency); +// ltc_2 adv logic +always @(*) begin + ltc_2_adv = ltc_2_inc ^ ltc_2_dec; +end +// ltc_2 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_2_cnt_ext[33:0] = {1'b0, 1'b0, ltc_2_cnt_cur}; + ltc_2_cnt_inc[33:0] = ltc_2_cnt_cur + 1'b1; // spyglass disable W164b + ltc_2_cnt_dec[33:0] = ltc_2_cnt_cur - 1'b1; // spyglass disable W164b + ltc_2_cnt_mod[33:0] = (ltc_2_inc && !ltc_2_dec)? ltc_2_cnt_inc : (!ltc_2_inc && ltc_2_dec)? ltc_2_cnt_dec : ltc_2_cnt_ext; + ltc_2_cnt_new[33:0] = (ltc_2_adv)? ltc_2_cnt_mod[33:0] : ltc_2_cnt_ext[33:0]; + ltc_2_cnt_nxt[33:0] = (img_rd_latency_clr)? 34'd0 : ltc_2_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// ltc_2 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_2_cnt_cur[31:0] <= 0; + end else begin + if (img_rd_latency_cen) begin + ltc_2_cnt_cur[31:0] <= ltc_2_cnt_nxt[31:0]; + end + end +end +// ltc_2 output logic +always @(*) begin + dp2reg_img_rd_latency[31:0] = ltc_2_cnt_cur[31:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_img_sg__img_read_response_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (dma_rd_rsp_vld & ~dma_rd_rsp_rdy); + endproperty +// Cover 0 : "(dma_rd_rsp_vld & ~dma_rd_rsp_rdy)" + FUNCPOINT_cdma_img_sg__img_read_response_block__0_COV : cover property (cdma_img_sg__img_read_response_block__0_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_height_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_planar_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_sec_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_burst_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_sec_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_height_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_height_en & planar1_enable))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p0_burst_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_img_p1_burst_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_46x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(img_entry_onfly_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rsp_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_vld_w & dma_rsp_fifo_ready))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_c0l0_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_c1l0_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_planar0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_planar1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_vld_d1_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_burst_cnt_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_burst_cnt_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p0_burst_size_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_p1_burst_size_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_bundle_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_img_bundle_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Config error! Pixel height offset is not zero!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (is_running & (|reg2dp_pixel_y_offset))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data_entries_w is much to big!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_data_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_bundle_cnt_w is overflow!") zzz_assert_never_18x (nvdla_core_clk, `ASSERT_RESET, (req_img_p0_burst_en & mon_req_img_p0_bundle_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_sec_cnt_w is overflow!") zzz_assert_never_19x (nvdla_core_clk, `ASSERT_RESET, (req_img_p0_burst_en & mon_req_img_p0_sec_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_bundle_cnt_w is overflow!") zzz_assert_never_23x (nvdla_core_clk, `ASSERT_RESET, (req_img_p1_burst_en & mon_req_img_p1_bundle_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_sec_cnt_w is overflow!") zzz_assert_never_24x (nvdla_core_clk, `ASSERT_RESET, (req_img_p1_burst_en & mon_req_img_p1_sec_cnt_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_reg_en set when not running!") zzz_assert_never_25x (nvdla_core_clk, `ASSERT_RESET, (~is_running & req_reg_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_valid set when not running!") zzz_assert_never_26x (nvdla_core_clk, `ASSERT_RESET, (~is_running & req_valid)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_line_offset_w is overflow!") zzz_assert_never_29x (nvdla_core_clk, `ASSERT_RESET, (req_height_en & mon_req_img_p0_line_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_line_offset_w is overflow!") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (req_height_en & planar1_enable & mon_req_img_p1_line_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p0_burst_offset_w is overflow!") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (req_img_p0_burst_offset_en & mon_req_img_p0_burst_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_img_p1_burst_offset_w is overflow!") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (req_img_p1_burst_offset_en & mon_req_img_p1_burst_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_size_out is overflow!") zzz_assert_never_45x (nvdla_core_clk, `ASSERT_RESET, (req_reg_en & mon_req_size_out)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! total_required_entry is overflow!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (mon_total_required_entry & ~is_cbuf_ready)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! total_required_entry is out of range!") zzz_assert_never_48x (nvdla_core_clk, `ASSERT_RESET, ((total_required_entry > 3840) & ~req_is_done_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! img_entry_onfly_w is overflow!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (mon_img_entry_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! img_entry_onfly_w is out of range!") zzz_assert_never_50x (nvdla_core_clk, `ASSERT_RESET, (img_entry_onfly_w > 3840)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! img_entry_onfly is not empty when idle!") zzz_assert_never_51x (nvdla_core_clk, `ASSERT_RESET, (~is_running & (|img_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Receive input data when not busy") zzz_assert_never_53x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_55x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_fifo_ready & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo idle when data return") zzz_assert_never_56x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_57x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > dma_rsp_size)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_58x (nvdla_core_clk, `ASSERT_RESET, (mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_59x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > 6'h30)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Data input when idle!") zzz_assert_never_60x (nvdla_core_clk, `ASSERT_RESET, (~is_running & dma_rd_rsp_vld)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_p1_vld_d1 valid when rsp_img_p0_vld_d1 not!") zzz_assert_never_71x (nvdla_core_clk, `ASSERT_RESET, (~rsp_img_p0_vld_d1 & rsp_img_p1_vld_d1)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_p0_burst_cnt_inc is overflow!") zzz_assert_never_84x (nvdla_core_clk, `ASSERT_RESET, (rsp_img_p0_burst_cnt_en & mon_rsp_img_p0_burst_cnt_inc & ~rsp_img_planar)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_p1_burst_cnt_inc is overflow!") zzz_assert_never_85x (nvdla_core_clk, `ASSERT_RESET, (rsp_img_p1_burst_cnt_en & mon_rsp_img_p1_burst_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_w_burst_size is out of range when planar0!") zzz_assert_never_86x (nvdla_core_clk, `ASSERT_RESET, (rsp_img_p0_burst_cnt_en & rsp_img_w_burst_size[4] & ~rsp_img_planar)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_img_is_done is 0 when not busy!") zzz_assert_never_88x (nvdla_core_clk, `ASSERT_RESET, (~is_running & ~rsp_img_is_done)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sg2pack_fifo push block!") zzz_assert_never_89x (nvdla_core_clk, `ASSERT_RESET, (sg2pack_push_req & ~sg2pack_push_ready)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sg2pack_fifo pop invalid!") zzz_assert_never_90x (nvdla_core_clk, `ASSERT_RESET, (~sg2pack_pop_req & sg2pack_pop_ready)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sg_is_done is 0 when not busy!") zzz_assert_never_92x (nvdla_core_clk, `ASSERT_RESET, (~is_running & ~sg_is_done)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_93x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && img_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_IMG_sg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v new file mode 100644 index 0000000..67b6c48 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v @@ -0,0 +1,1291 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_sg2pack_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_IMG_sg2pack_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [10:0] wr_data; +input rd_ready; +output rd_req; +output [10:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [6:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing && (wr_count > 8'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [10:0] rd_data_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ram ( + .clk( clk ) + , .clk_mgated( clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( (wr_count == 0) ? 8'd128 : {1'b0,rd_adr} ) + , .dout ( rd_data_p ) + ); +wire [6:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign rd_req_p = rd_count_p != 0 || rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [10:0] rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge clk_mgated ) begin + if ( (rd_popping) ) begin + rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + rd_data <= {11{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_IMG_sg2pack_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_IMG_sg2pack_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [10:0] di; +input iwe; +input we; +input [6:0] wa; +input [7:0] ra; +output [10:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [10:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [10:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [6:0] Wa0_vmw; +reg we0_vmw; +reg [10:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[6:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 128) ? di_d : dout_p; +`else +reg [10:0] ram_ff0; +reg [10:0] ram_ff1; +reg [10:0] ram_ff2; +reg [10:0] ram_ff3; +reg [10:0] ram_ff4; +reg [10:0] ram_ff5; +reg [10:0] ram_ff6; +reg [10:0] ram_ff7; +reg [10:0] ram_ff8; +reg [10:0] ram_ff9; +reg [10:0] ram_ff10; +reg [10:0] ram_ff11; +reg [10:0] ram_ff12; +reg [10:0] ram_ff13; +reg [10:0] ram_ff14; +reg [10:0] ram_ff15; +reg [10:0] ram_ff16; +reg [10:0] ram_ff17; +reg [10:0] ram_ff18; +reg [10:0] ram_ff19; +reg [10:0] ram_ff20; +reg [10:0] ram_ff21; +reg [10:0] ram_ff22; +reg [10:0] ram_ff23; +reg [10:0] ram_ff24; +reg [10:0] ram_ff25; +reg [10:0] ram_ff26; +reg [10:0] ram_ff27; +reg [10:0] ram_ff28; +reg [10:0] ram_ff29; +reg [10:0] ram_ff30; +reg [10:0] ram_ff31; +reg [10:0] ram_ff32; +reg [10:0] ram_ff33; +reg [10:0] ram_ff34; +reg [10:0] ram_ff35; +reg [10:0] ram_ff36; +reg [10:0] ram_ff37; +reg [10:0] ram_ff38; +reg [10:0] ram_ff39; +reg [10:0] ram_ff40; +reg [10:0] ram_ff41; +reg [10:0] ram_ff42; +reg [10:0] ram_ff43; +reg [10:0] ram_ff44; +reg [10:0] ram_ff45; +reg [10:0] ram_ff46; +reg [10:0] ram_ff47; +reg [10:0] ram_ff48; +reg [10:0] ram_ff49; +reg [10:0] ram_ff50; +reg [10:0] ram_ff51; +reg [10:0] ram_ff52; +reg [10:0] ram_ff53; +reg [10:0] ram_ff54; +reg [10:0] ram_ff55; +reg [10:0] ram_ff56; +reg [10:0] ram_ff57; +reg [10:0] ram_ff58; +reg [10:0] ram_ff59; +reg [10:0] ram_ff60; +reg [10:0] ram_ff61; +reg [10:0] ram_ff62; +reg [10:0] ram_ff63; +reg [10:0] ram_ff64; +reg [10:0] ram_ff65; +reg [10:0] ram_ff66; +reg [10:0] ram_ff67; +reg [10:0] ram_ff68; +reg [10:0] ram_ff69; +reg [10:0] ram_ff70; +reg [10:0] ram_ff71; +reg [10:0] ram_ff72; +reg [10:0] ram_ff73; +reg [10:0] ram_ff74; +reg [10:0] ram_ff75; +reg [10:0] ram_ff76; +reg [10:0] ram_ff77; +reg [10:0] ram_ff78; +reg [10:0] ram_ff79; +reg [10:0] ram_ff80; +reg [10:0] ram_ff81; +reg [10:0] ram_ff82; +reg [10:0] ram_ff83; +reg [10:0] ram_ff84; +reg [10:0] ram_ff85; +reg [10:0] ram_ff86; +reg [10:0] ram_ff87; +reg [10:0] ram_ff88; +reg [10:0] ram_ff89; +reg [10:0] ram_ff90; +reg [10:0] ram_ff91; +reg [10:0] ram_ff92; +reg [10:0] ram_ff93; +reg [10:0] ram_ff94; +reg [10:0] ram_ff95; +reg [10:0] ram_ff96; +reg [10:0] ram_ff97; +reg [10:0] ram_ff98; +reg [10:0] ram_ff99; +reg [10:0] ram_ff100; +reg [10:0] ram_ff101; +reg [10:0] ram_ff102; +reg [10:0] ram_ff103; +reg [10:0] ram_ff104; +reg [10:0] ram_ff105; +reg [10:0] ram_ff106; +reg [10:0] ram_ff107; +reg [10:0] ram_ff108; +reg [10:0] ram_ff109; +reg [10:0] ram_ff110; +reg [10:0] ram_ff111; +reg [10:0] ram_ff112; +reg [10:0] ram_ff113; +reg [10:0] ram_ff114; +reg [10:0] ram_ff115; +reg [10:0] ram_ff116; +reg [10:0] ram_ff117; +reg [10:0] ram_ff118; +reg [10:0] ram_ff119; +reg [10:0] ram_ff120; +reg [10:0] ram_ff121; +reg [10:0] ram_ff122; +reg [10:0] ram_ff123; +reg [10:0] ram_ff124; +reg [10:0] ram_ff125; +reg [10:0] ram_ff126; +reg [10:0] ram_ff127; +always @( posedge clk_mgated ) begin + if ( we && wa == 7'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 7'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 7'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 7'd3 ) begin + ram_ff3 <= di_d; + end + if ( we && wa == 7'd4 ) begin + ram_ff4 <= di_d; + end + if ( we && wa == 7'd5 ) begin + ram_ff5 <= di_d; + end + if ( we && wa == 7'd6 ) begin + ram_ff6 <= di_d; + end + if ( we && wa == 7'd7 ) begin + ram_ff7 <= di_d; + end + if ( we && wa == 7'd8 ) begin + ram_ff8 <= di_d; + end + if ( we && wa == 7'd9 ) begin + ram_ff9 <= di_d; + end + if ( we && wa == 7'd10 ) begin + ram_ff10 <= di_d; + end + if ( we && wa == 7'd11 ) begin + ram_ff11 <= di_d; + end + if ( we && wa == 7'd12 ) begin + ram_ff12 <= di_d; + end + if ( we && wa == 7'd13 ) begin + ram_ff13 <= di_d; + end + if ( we && wa == 7'd14 ) begin + ram_ff14 <= di_d; + end + if ( we && wa == 7'd15 ) begin + ram_ff15 <= di_d; + end + if ( we && wa == 7'd16 ) begin + ram_ff16 <= di_d; + end + if ( we && wa == 7'd17 ) begin + ram_ff17 <= di_d; + end + if ( we && wa == 7'd18 ) begin + ram_ff18 <= di_d; + end + if ( we && wa == 7'd19 ) begin + ram_ff19 <= di_d; + end + if ( we && wa == 7'd20 ) begin + ram_ff20 <= di_d; + end + if ( we && wa == 7'd21 ) begin + ram_ff21 <= di_d; + end + if ( we && wa == 7'd22 ) begin + ram_ff22 <= di_d; + end + if ( we && wa == 7'd23 ) begin + ram_ff23 <= di_d; + end + if ( we && wa == 7'd24 ) begin + ram_ff24 <= di_d; + end + if ( we && wa == 7'd25 ) begin + ram_ff25 <= di_d; + end + if ( we && wa == 7'd26 ) begin + ram_ff26 <= di_d; + end + if ( we && wa == 7'd27 ) begin + ram_ff27 <= di_d; + end + if ( we && wa == 7'd28 ) begin + ram_ff28 <= di_d; + end + if ( we && wa == 7'd29 ) begin + ram_ff29 <= di_d; + end + if ( we && wa == 7'd30 ) begin + ram_ff30 <= di_d; + end + if ( we && wa == 7'd31 ) begin + ram_ff31 <= di_d; + end + if ( we && wa == 7'd32 ) begin + ram_ff32 <= di_d; + end + if ( we && wa == 7'd33 ) begin + ram_ff33 <= di_d; + end + if ( we && wa == 7'd34 ) begin + ram_ff34 <= di_d; + end + if ( we && wa == 7'd35 ) begin + ram_ff35 <= di_d; + end + if ( we && wa == 7'd36 ) begin + ram_ff36 <= di_d; + end + if ( we && wa == 7'd37 ) begin + ram_ff37 <= di_d; + end + if ( we && wa == 7'd38 ) begin + ram_ff38 <= di_d; + end + if ( we && wa == 7'd39 ) begin + ram_ff39 <= di_d; + end + if ( we && wa == 7'd40 ) begin + ram_ff40 <= di_d; + end + if ( we && wa == 7'd41 ) begin + ram_ff41 <= di_d; + end + if ( we && wa == 7'd42 ) begin + ram_ff42 <= di_d; + end + if ( we && wa == 7'd43 ) begin + ram_ff43 <= di_d; + end + if ( we && wa == 7'd44 ) begin + ram_ff44 <= di_d; + end + if ( we && wa == 7'd45 ) begin + ram_ff45 <= di_d; + end + if ( we && wa == 7'd46 ) begin + ram_ff46 <= di_d; + end + if ( we && wa == 7'd47 ) begin + ram_ff47 <= di_d; + end + if ( we && wa == 7'd48 ) begin + ram_ff48 <= di_d; + end + if ( we && wa == 7'd49 ) begin + ram_ff49 <= di_d; + end + if ( we && wa == 7'd50 ) begin + ram_ff50 <= di_d; + end + if ( we && wa == 7'd51 ) begin + ram_ff51 <= di_d; + end + if ( we && wa == 7'd52 ) begin + ram_ff52 <= di_d; + end + if ( we && wa == 7'd53 ) begin + ram_ff53 <= di_d; + end + if ( we && wa == 7'd54 ) begin + ram_ff54 <= di_d; + end + if ( we && wa == 7'd55 ) begin + ram_ff55 <= di_d; + end + if ( we && wa == 7'd56 ) begin + ram_ff56 <= di_d; + end + if ( we && wa == 7'd57 ) begin + ram_ff57 <= di_d; + end + if ( we && wa == 7'd58 ) begin + ram_ff58 <= di_d; + end + if ( we && wa == 7'd59 ) begin + ram_ff59 <= di_d; + end + if ( we && wa == 7'd60 ) begin + ram_ff60 <= di_d; + end + if ( we && wa == 7'd61 ) begin + ram_ff61 <= di_d; + end + if ( we && wa == 7'd62 ) begin + ram_ff62 <= di_d; + end + if ( we && wa == 7'd63 ) begin + ram_ff63 <= di_d; + end + if ( we && wa == 7'd64 ) begin + ram_ff64 <= di_d; + end + if ( we && wa == 7'd65 ) begin + ram_ff65 <= di_d; + end + if ( we && wa == 7'd66 ) begin + ram_ff66 <= di_d; + end + if ( we && wa == 7'd67 ) begin + ram_ff67 <= di_d; + end + if ( we && wa == 7'd68 ) begin + ram_ff68 <= di_d; + end + if ( we && wa == 7'd69 ) begin + ram_ff69 <= di_d; + end + if ( we && wa == 7'd70 ) begin + ram_ff70 <= di_d; + end + if ( we && wa == 7'd71 ) begin + ram_ff71 <= di_d; + end + if ( we && wa == 7'd72 ) begin + ram_ff72 <= di_d; + end + if ( we && wa == 7'd73 ) begin + ram_ff73 <= di_d; + end + if ( we && wa == 7'd74 ) begin + ram_ff74 <= di_d; + end + if ( we && wa == 7'd75 ) begin + ram_ff75 <= di_d; + end + if ( we && wa == 7'd76 ) begin + ram_ff76 <= di_d; + end + if ( we && wa == 7'd77 ) begin + ram_ff77 <= di_d; + end + if ( we && wa == 7'd78 ) begin + ram_ff78 <= di_d; + end + if ( we && wa == 7'd79 ) begin + ram_ff79 <= di_d; + end + if ( we && wa == 7'd80 ) begin + ram_ff80 <= di_d; + end + if ( we && wa == 7'd81 ) begin + ram_ff81 <= di_d; + end + if ( we && wa == 7'd82 ) begin + ram_ff82 <= di_d; + end + if ( we && wa == 7'd83 ) begin + ram_ff83 <= di_d; + end + if ( we && wa == 7'd84 ) begin + ram_ff84 <= di_d; + end + if ( we && wa == 7'd85 ) begin + ram_ff85 <= di_d; + end + if ( we && wa == 7'd86 ) begin + ram_ff86 <= di_d; + end + if ( we && wa == 7'd87 ) begin + ram_ff87 <= di_d; + end + if ( we && wa == 7'd88 ) begin + ram_ff88 <= di_d; + end + if ( we && wa == 7'd89 ) begin + ram_ff89 <= di_d; + end + if ( we && wa == 7'd90 ) begin + ram_ff90 <= di_d; + end + if ( we && wa == 7'd91 ) begin + ram_ff91 <= di_d; + end + if ( we && wa == 7'd92 ) begin + ram_ff92 <= di_d; + end + if ( we && wa == 7'd93 ) begin + ram_ff93 <= di_d; + end + if ( we && wa == 7'd94 ) begin + ram_ff94 <= di_d; + end + if ( we && wa == 7'd95 ) begin + ram_ff95 <= di_d; + end + if ( we && wa == 7'd96 ) begin + ram_ff96 <= di_d; + end + if ( we && wa == 7'd97 ) begin + ram_ff97 <= di_d; + end + if ( we && wa == 7'd98 ) begin + ram_ff98 <= di_d; + end + if ( we && wa == 7'd99 ) begin + ram_ff99 <= di_d; + end + if ( we && wa == 7'd100 ) begin + ram_ff100 <= di_d; + end + if ( we && wa == 7'd101 ) begin + ram_ff101 <= di_d; + end + if ( we && wa == 7'd102 ) begin + ram_ff102 <= di_d; + end + if ( we && wa == 7'd103 ) begin + ram_ff103 <= di_d; + end + if ( we && wa == 7'd104 ) begin + ram_ff104 <= di_d; + end + if ( we && wa == 7'd105 ) begin + ram_ff105 <= di_d; + end + if ( we && wa == 7'd106 ) begin + ram_ff106 <= di_d; + end + if ( we && wa == 7'd107 ) begin + ram_ff107 <= di_d; + end + if ( we && wa == 7'd108 ) begin + ram_ff108 <= di_d; + end + if ( we && wa == 7'd109 ) begin + ram_ff109 <= di_d; + end + if ( we && wa == 7'd110 ) begin + ram_ff110 <= di_d; + end + if ( we && wa == 7'd111 ) begin + ram_ff111 <= di_d; + end + if ( we && wa == 7'd112 ) begin + ram_ff112 <= di_d; + end + if ( we && wa == 7'd113 ) begin + ram_ff113 <= di_d; + end + if ( we && wa == 7'd114 ) begin + ram_ff114 <= di_d; + end + if ( we && wa == 7'd115 ) begin + ram_ff115 <= di_d; + end + if ( we && wa == 7'd116 ) begin + ram_ff116 <= di_d; + end + if ( we && wa == 7'd117 ) begin + ram_ff117 <= di_d; + end + if ( we && wa == 7'd118 ) begin + ram_ff118 <= di_d; + end + if ( we && wa == 7'd119 ) begin + ram_ff119 <= di_d; + end + if ( we && wa == 7'd120 ) begin + ram_ff120 <= di_d; + end + if ( we && wa == 7'd121 ) begin + ram_ff121 <= di_d; + end + if ( we && wa == 7'd122 ) begin + ram_ff122 <= di_d; + end + if ( we && wa == 7'd123 ) begin + ram_ff123 <= di_d; + end + if ( we && wa == 7'd124 ) begin + ram_ff124 <= di_d; + end + if ( we && wa == 7'd125 ) begin + ram_ff125 <= di_d; + end + if ( we && wa == 7'd126 ) begin + ram_ff126 <= di_d; + end + if ( we && wa == 7'd127 ) begin + ram_ff127 <= di_d; + end +end +reg [10:0] dout; +always @(*) begin + case( ra ) + 8'd0: dout = ram_ff0; + 8'd1: dout = ram_ff1; + 8'd2: dout = ram_ff2; + 8'd3: dout = ram_ff3; + 8'd4: dout = ram_ff4; + 8'd5: dout = ram_ff5; + 8'd6: dout = ram_ff6; + 8'd7: dout = ram_ff7; + 8'd8: dout = ram_ff8; + 8'd9: dout = ram_ff9; + 8'd10: dout = ram_ff10; + 8'd11: dout = ram_ff11; + 8'd12: dout = ram_ff12; + 8'd13: dout = ram_ff13; + 8'd14: dout = ram_ff14; + 8'd15: dout = ram_ff15; + 8'd16: dout = ram_ff16; + 8'd17: dout = ram_ff17; + 8'd18: dout = ram_ff18; + 8'd19: dout = ram_ff19; + 8'd20: dout = ram_ff20; + 8'd21: dout = ram_ff21; + 8'd22: dout = ram_ff22; + 8'd23: dout = ram_ff23; + 8'd24: dout = ram_ff24; + 8'd25: dout = ram_ff25; + 8'd26: dout = ram_ff26; + 8'd27: dout = ram_ff27; + 8'd28: dout = ram_ff28; + 8'd29: dout = ram_ff29; + 8'd30: dout = ram_ff30; + 8'd31: dout = ram_ff31; + 8'd32: dout = ram_ff32; + 8'd33: dout = ram_ff33; + 8'd34: dout = ram_ff34; + 8'd35: dout = ram_ff35; + 8'd36: dout = ram_ff36; + 8'd37: dout = ram_ff37; + 8'd38: dout = ram_ff38; + 8'd39: dout = ram_ff39; + 8'd40: dout = ram_ff40; + 8'd41: dout = ram_ff41; + 8'd42: dout = ram_ff42; + 8'd43: dout = ram_ff43; + 8'd44: dout = ram_ff44; + 8'd45: dout = ram_ff45; + 8'd46: dout = ram_ff46; + 8'd47: dout = ram_ff47; + 8'd48: dout = ram_ff48; + 8'd49: dout = ram_ff49; + 8'd50: dout = ram_ff50; + 8'd51: dout = ram_ff51; + 8'd52: dout = ram_ff52; + 8'd53: dout = ram_ff53; + 8'd54: dout = ram_ff54; + 8'd55: dout = ram_ff55; + 8'd56: dout = ram_ff56; + 8'd57: dout = ram_ff57; + 8'd58: dout = ram_ff58; + 8'd59: dout = ram_ff59; + 8'd60: dout = ram_ff60; + 8'd61: dout = ram_ff61; + 8'd62: dout = ram_ff62; + 8'd63: dout = ram_ff63; + 8'd64: dout = ram_ff64; + 8'd65: dout = ram_ff65; + 8'd66: dout = ram_ff66; + 8'd67: dout = ram_ff67; + 8'd68: dout = ram_ff68; + 8'd69: dout = ram_ff69; + 8'd70: dout = ram_ff70; + 8'd71: dout = ram_ff71; + 8'd72: dout = ram_ff72; + 8'd73: dout = ram_ff73; + 8'd74: dout = ram_ff74; + 8'd75: dout = ram_ff75; + 8'd76: dout = ram_ff76; + 8'd77: dout = ram_ff77; + 8'd78: dout = ram_ff78; + 8'd79: dout = ram_ff79; + 8'd80: dout = ram_ff80; + 8'd81: dout = ram_ff81; + 8'd82: dout = ram_ff82; + 8'd83: dout = ram_ff83; + 8'd84: dout = ram_ff84; + 8'd85: dout = ram_ff85; + 8'd86: dout = ram_ff86; + 8'd87: dout = ram_ff87; + 8'd88: dout = ram_ff88; + 8'd89: dout = ram_ff89; + 8'd90: dout = ram_ff90; + 8'd91: dout = ram_ff91; + 8'd92: dout = ram_ff92; + 8'd93: dout = ram_ff93; + 8'd94: dout = ram_ff94; + 8'd95: dout = ram_ff95; + 8'd96: dout = ram_ff96; + 8'd97: dout = ram_ff97; + 8'd98: dout = ram_ff98; + 8'd99: dout = ram_ff99; + 8'd100: dout = ram_ff100; + 8'd101: dout = ram_ff101; + 8'd102: dout = ram_ff102; + 8'd103: dout = ram_ff103; + 8'd104: dout = ram_ff104; + 8'd105: dout = ram_ff105; + 8'd106: dout = ram_ff106; + 8'd107: dout = ram_ff107; + 8'd108: dout = ram_ff108; + 8'd109: dout = ram_ff109; + 8'd110: dout = ram_ff110; + 8'd111: dout = ram_ff111; + 8'd112: dout = ram_ff112; + 8'd113: dout = ram_ff113; + 8'd114: dout = ram_ff114; + 8'd115: dout = ram_ff115; + 8'd116: dout = ram_ff116; + 8'd117: dout = ram_ff117; + 8'd118: dout = ram_ff118; + 8'd119: dout = ram_ff119; + 8'd120: dout = ram_ff120; + 8'd121: dout = ram_ff121; + 8'd122: dout = ram_ff122; + 8'd123: dout = ram_ff123; + 8'd124: dout = ram_ff124; + 8'd125: dout = ram_ff125; + 8'd126: dout = ram_ff126; + 8'd127: dout = ram_ff127; + 8'd128: dout = di_d; +//VCS coverage off + default: dout = {11{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [6:0] Wa0; +input we0; +input [10:0] Di0; +input [6:0] Ra0; +output [10:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 11'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [10:0] mem[127:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [10:0] Q0 = mem[0]; +wire [10:0] Q1 = mem[1]; +wire [10:0] Q2 = mem[2]; +wire [10:0] Q3 = mem[3]; +wire [10:0] Q4 = mem[4]; +wire [10:0] Q5 = mem[5]; +wire [10:0] Q6 = mem[6]; +wire [10:0] Q7 = mem[7]; +wire [10:0] Q8 = mem[8]; +wire [10:0] Q9 = mem[9]; +wire [10:0] Q10 = mem[10]; +wire [10:0] Q11 = mem[11]; +wire [10:0] Q12 = mem[12]; +wire [10:0] Q13 = mem[13]; +wire [10:0] Q14 = mem[14]; +wire [10:0] Q15 = mem[15]; +wire [10:0] Q16 = mem[16]; +wire [10:0] Q17 = mem[17]; +wire [10:0] Q18 = mem[18]; +wire [10:0] Q19 = mem[19]; +wire [10:0] Q20 = mem[20]; +wire [10:0] Q21 = mem[21]; +wire [10:0] Q22 = mem[22]; +wire [10:0] Q23 = mem[23]; +wire [10:0] Q24 = mem[24]; +wire [10:0] Q25 = mem[25]; +wire [10:0] Q26 = mem[26]; +wire [10:0] Q27 = mem[27]; +wire [10:0] Q28 = mem[28]; +wire [10:0] Q29 = mem[29]; +wire [10:0] Q30 = mem[30]; +wire [10:0] Q31 = mem[31]; +wire [10:0] Q32 = mem[32]; +wire [10:0] Q33 = mem[33]; +wire [10:0] Q34 = mem[34]; +wire [10:0] Q35 = mem[35]; +wire [10:0] Q36 = mem[36]; +wire [10:0] Q37 = mem[37]; +wire [10:0] Q38 = mem[38]; +wire [10:0] Q39 = mem[39]; +wire [10:0] Q40 = mem[40]; +wire [10:0] Q41 = mem[41]; +wire [10:0] Q42 = mem[42]; +wire [10:0] Q43 = mem[43]; +wire [10:0] Q44 = mem[44]; +wire [10:0] Q45 = mem[45]; +wire [10:0] Q46 = mem[46]; +wire [10:0] Q47 = mem[47]; +wire [10:0] Q48 = mem[48]; +wire [10:0] Q49 = mem[49]; +wire [10:0] Q50 = mem[50]; +wire [10:0] Q51 = mem[51]; +wire [10:0] Q52 = mem[52]; +wire [10:0] Q53 = mem[53]; +wire [10:0] Q54 = mem[54]; +wire [10:0] Q55 = mem[55]; +wire [10:0] Q56 = mem[56]; +wire [10:0] Q57 = mem[57]; +wire [10:0] Q58 = mem[58]; +wire [10:0] Q59 = mem[59]; +wire [10:0] Q60 = mem[60]; +wire [10:0] Q61 = mem[61]; +wire [10:0] Q62 = mem[62]; +wire [10:0] Q63 = mem[63]; +wire [10:0] Q64 = mem[64]; +wire [10:0] Q65 = mem[65]; +wire [10:0] Q66 = mem[66]; +wire [10:0] Q67 = mem[67]; +wire [10:0] Q68 = mem[68]; +wire [10:0] Q69 = mem[69]; +wire [10:0] Q70 = mem[70]; +wire [10:0] Q71 = mem[71]; +wire [10:0] Q72 = mem[72]; +wire [10:0] Q73 = mem[73]; +wire [10:0] Q74 = mem[74]; +wire [10:0] Q75 = mem[75]; +wire [10:0] Q76 = mem[76]; +wire [10:0] Q77 = mem[77]; +wire [10:0] Q78 = mem[78]; +wire [10:0] Q79 = mem[79]; +wire [10:0] Q80 = mem[80]; +wire [10:0] Q81 = mem[81]; +wire [10:0] Q82 = mem[82]; +wire [10:0] Q83 = mem[83]; +wire [10:0] Q84 = mem[84]; +wire [10:0] Q85 = mem[85]; +wire [10:0] Q86 = mem[86]; +wire [10:0] Q87 = mem[87]; +wire [10:0] Q88 = mem[88]; +wire [10:0] Q89 = mem[89]; +wire [10:0] Q90 = mem[90]; +wire [10:0] Q91 = mem[91]; +wire [10:0] Q92 = mem[92]; +wire [10:0] Q93 = mem[93]; +wire [10:0] Q94 = mem[94]; +wire [10:0] Q95 = mem[95]; +wire [10:0] Q96 = mem[96]; +wire [10:0] Q97 = mem[97]; +wire [10:0] Q98 = mem[98]; +wire [10:0] Q99 = mem[99]; +wire [10:0] Q100 = mem[100]; +wire [10:0] Q101 = mem[101]; +wire [10:0] Q102 = mem[102]; +wire [10:0] Q103 = mem[103]; +wire [10:0] Q104 = mem[104]; +wire [10:0] Q105 = mem[105]; +wire [10:0] Q106 = mem[106]; +wire [10:0] Q107 = mem[107]; +wire [10:0] Q108 = mem[108]; +wire [10:0] Q109 = mem[109]; +wire [10:0] Q110 = mem[110]; +wire [10:0] Q111 = mem[111]; +wire [10:0] Q112 = mem[112]; +wire [10:0] Q113 = mem[113]; +wire [10:0] Q114 = mem[114]; +wire [10:0] Q115 = mem[115]; +wire [10:0] Q116 = mem[116]; +wire [10:0] Q117 = mem[117]; +wire [10:0] Q118 = mem[118]; +wire [10:0] Q119 = mem[119]; +wire [10:0] Q120 = mem[120]; +wire [10:0] Q121 = mem[121]; +wire [10:0] Q122 = mem[122]; +wire [10:0] Q123 = mem[123]; +wire [10:0] Q124 = mem[124]; +wire [10:0] Q125 = mem[125]; +wire [10:0] Q126 = mem[126]; +wire [10:0] Q127 = mem[127]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11] } +endmodule // vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +//vmw: Memory vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +//vmw: Address-size 7 +//vmw: Data-size 11 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[10:0] data0[10:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[10:0] data1[10:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v.vcp new file mode 100644 index 0000000..67b6c48 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v.vcp @@ -0,0 +1,1291 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_IMG_sg2pack_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_IMG_sg2pack_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [10:0] wr_data; +input rd_ready; +output rd_req; +output [10:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [6:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing && (wr_count > 8'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [10:0] rd_data_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ram ( + .clk( clk ) + , .clk_mgated( clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( (wr_count == 0) ? 8'd128 : {1'b0,rd_adr} ) + , .dout ( rd_data_p ) + ); +wire [6:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign rd_req_p = rd_count_p != 0 || rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [10:0] rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge clk_mgated ) begin + if ( (rd_popping) ) begin + rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + rd_data <= {11{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_IMG_sg2pack_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_IMG_sg2pack_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_IMG_sg2pack_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [10:0] di; +input iwe; +input we; +input [6:0] wa; +input [7:0] ra; +output [10:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [10:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [10:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [6:0] Wa0_vmw; +reg we0_vmw; +reg [10:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[6:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 128) ? di_d : dout_p; +`else +reg [10:0] ram_ff0; +reg [10:0] ram_ff1; +reg [10:0] ram_ff2; +reg [10:0] ram_ff3; +reg [10:0] ram_ff4; +reg [10:0] ram_ff5; +reg [10:0] ram_ff6; +reg [10:0] ram_ff7; +reg [10:0] ram_ff8; +reg [10:0] ram_ff9; +reg [10:0] ram_ff10; +reg [10:0] ram_ff11; +reg [10:0] ram_ff12; +reg [10:0] ram_ff13; +reg [10:0] ram_ff14; +reg [10:0] ram_ff15; +reg [10:0] ram_ff16; +reg [10:0] ram_ff17; +reg [10:0] ram_ff18; +reg [10:0] ram_ff19; +reg [10:0] ram_ff20; +reg [10:0] ram_ff21; +reg [10:0] ram_ff22; +reg [10:0] ram_ff23; +reg [10:0] ram_ff24; +reg [10:0] ram_ff25; +reg [10:0] ram_ff26; +reg [10:0] ram_ff27; +reg [10:0] ram_ff28; +reg [10:0] ram_ff29; +reg [10:0] ram_ff30; +reg [10:0] ram_ff31; +reg [10:0] ram_ff32; +reg [10:0] ram_ff33; +reg [10:0] ram_ff34; +reg [10:0] ram_ff35; +reg [10:0] ram_ff36; +reg [10:0] ram_ff37; +reg [10:0] ram_ff38; +reg [10:0] ram_ff39; +reg [10:0] ram_ff40; +reg [10:0] ram_ff41; +reg [10:0] ram_ff42; +reg [10:0] ram_ff43; +reg [10:0] ram_ff44; +reg [10:0] ram_ff45; +reg [10:0] ram_ff46; +reg [10:0] ram_ff47; +reg [10:0] ram_ff48; +reg [10:0] ram_ff49; +reg [10:0] ram_ff50; +reg [10:0] ram_ff51; +reg [10:0] ram_ff52; +reg [10:0] ram_ff53; +reg [10:0] ram_ff54; +reg [10:0] ram_ff55; +reg [10:0] ram_ff56; +reg [10:0] ram_ff57; +reg [10:0] ram_ff58; +reg [10:0] ram_ff59; +reg [10:0] ram_ff60; +reg [10:0] ram_ff61; +reg [10:0] ram_ff62; +reg [10:0] ram_ff63; +reg [10:0] ram_ff64; +reg [10:0] ram_ff65; +reg [10:0] ram_ff66; +reg [10:0] ram_ff67; +reg [10:0] ram_ff68; +reg [10:0] ram_ff69; +reg [10:0] ram_ff70; +reg [10:0] ram_ff71; +reg [10:0] ram_ff72; +reg [10:0] ram_ff73; +reg [10:0] ram_ff74; +reg [10:0] ram_ff75; +reg [10:0] ram_ff76; +reg [10:0] ram_ff77; +reg [10:0] ram_ff78; +reg [10:0] ram_ff79; +reg [10:0] ram_ff80; +reg [10:0] ram_ff81; +reg [10:0] ram_ff82; +reg [10:0] ram_ff83; +reg [10:0] ram_ff84; +reg [10:0] ram_ff85; +reg [10:0] ram_ff86; +reg [10:0] ram_ff87; +reg [10:0] ram_ff88; +reg [10:0] ram_ff89; +reg [10:0] ram_ff90; +reg [10:0] ram_ff91; +reg [10:0] ram_ff92; +reg [10:0] ram_ff93; +reg [10:0] ram_ff94; +reg [10:0] ram_ff95; +reg [10:0] ram_ff96; +reg [10:0] ram_ff97; +reg [10:0] ram_ff98; +reg [10:0] ram_ff99; +reg [10:0] ram_ff100; +reg [10:0] ram_ff101; +reg [10:0] ram_ff102; +reg [10:0] ram_ff103; +reg [10:0] ram_ff104; +reg [10:0] ram_ff105; +reg [10:0] ram_ff106; +reg [10:0] ram_ff107; +reg [10:0] ram_ff108; +reg [10:0] ram_ff109; +reg [10:0] ram_ff110; +reg [10:0] ram_ff111; +reg [10:0] ram_ff112; +reg [10:0] ram_ff113; +reg [10:0] ram_ff114; +reg [10:0] ram_ff115; +reg [10:0] ram_ff116; +reg [10:0] ram_ff117; +reg [10:0] ram_ff118; +reg [10:0] ram_ff119; +reg [10:0] ram_ff120; +reg [10:0] ram_ff121; +reg [10:0] ram_ff122; +reg [10:0] ram_ff123; +reg [10:0] ram_ff124; +reg [10:0] ram_ff125; +reg [10:0] ram_ff126; +reg [10:0] ram_ff127; +always @( posedge clk_mgated ) begin + if ( we && wa == 7'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 7'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 7'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 7'd3 ) begin + ram_ff3 <= di_d; + end + if ( we && wa == 7'd4 ) begin + ram_ff4 <= di_d; + end + if ( we && wa == 7'd5 ) begin + ram_ff5 <= di_d; + end + if ( we && wa == 7'd6 ) begin + ram_ff6 <= di_d; + end + if ( we && wa == 7'd7 ) begin + ram_ff7 <= di_d; + end + if ( we && wa == 7'd8 ) begin + ram_ff8 <= di_d; + end + if ( we && wa == 7'd9 ) begin + ram_ff9 <= di_d; + end + if ( we && wa == 7'd10 ) begin + ram_ff10 <= di_d; + end + if ( we && wa == 7'd11 ) begin + ram_ff11 <= di_d; + end + if ( we && wa == 7'd12 ) begin + ram_ff12 <= di_d; + end + if ( we && wa == 7'd13 ) begin + ram_ff13 <= di_d; + end + if ( we && wa == 7'd14 ) begin + ram_ff14 <= di_d; + end + if ( we && wa == 7'd15 ) begin + ram_ff15 <= di_d; + end + if ( we && wa == 7'd16 ) begin + ram_ff16 <= di_d; + end + if ( we && wa == 7'd17 ) begin + ram_ff17 <= di_d; + end + if ( we && wa == 7'd18 ) begin + ram_ff18 <= di_d; + end + if ( we && wa == 7'd19 ) begin + ram_ff19 <= di_d; + end + if ( we && wa == 7'd20 ) begin + ram_ff20 <= di_d; + end + if ( we && wa == 7'd21 ) begin + ram_ff21 <= di_d; + end + if ( we && wa == 7'd22 ) begin + ram_ff22 <= di_d; + end + if ( we && wa == 7'd23 ) begin + ram_ff23 <= di_d; + end + if ( we && wa == 7'd24 ) begin + ram_ff24 <= di_d; + end + if ( we && wa == 7'd25 ) begin + ram_ff25 <= di_d; + end + if ( we && wa == 7'd26 ) begin + ram_ff26 <= di_d; + end + if ( we && wa == 7'd27 ) begin + ram_ff27 <= di_d; + end + if ( we && wa == 7'd28 ) begin + ram_ff28 <= di_d; + end + if ( we && wa == 7'd29 ) begin + ram_ff29 <= di_d; + end + if ( we && wa == 7'd30 ) begin + ram_ff30 <= di_d; + end + if ( we && wa == 7'd31 ) begin + ram_ff31 <= di_d; + end + if ( we && wa == 7'd32 ) begin + ram_ff32 <= di_d; + end + if ( we && wa == 7'd33 ) begin + ram_ff33 <= di_d; + end + if ( we && wa == 7'd34 ) begin + ram_ff34 <= di_d; + end + if ( we && wa == 7'd35 ) begin + ram_ff35 <= di_d; + end + if ( we && wa == 7'd36 ) begin + ram_ff36 <= di_d; + end + if ( we && wa == 7'd37 ) begin + ram_ff37 <= di_d; + end + if ( we && wa == 7'd38 ) begin + ram_ff38 <= di_d; + end + if ( we && wa == 7'd39 ) begin + ram_ff39 <= di_d; + end + if ( we && wa == 7'd40 ) begin + ram_ff40 <= di_d; + end + if ( we && wa == 7'd41 ) begin + ram_ff41 <= di_d; + end + if ( we && wa == 7'd42 ) begin + ram_ff42 <= di_d; + end + if ( we && wa == 7'd43 ) begin + ram_ff43 <= di_d; + end + if ( we && wa == 7'd44 ) begin + ram_ff44 <= di_d; + end + if ( we && wa == 7'd45 ) begin + ram_ff45 <= di_d; + end + if ( we && wa == 7'd46 ) begin + ram_ff46 <= di_d; + end + if ( we && wa == 7'd47 ) begin + ram_ff47 <= di_d; + end + if ( we && wa == 7'd48 ) begin + ram_ff48 <= di_d; + end + if ( we && wa == 7'd49 ) begin + ram_ff49 <= di_d; + end + if ( we && wa == 7'd50 ) begin + ram_ff50 <= di_d; + end + if ( we && wa == 7'd51 ) begin + ram_ff51 <= di_d; + end + if ( we && wa == 7'd52 ) begin + ram_ff52 <= di_d; + end + if ( we && wa == 7'd53 ) begin + ram_ff53 <= di_d; + end + if ( we && wa == 7'd54 ) begin + ram_ff54 <= di_d; + end + if ( we && wa == 7'd55 ) begin + ram_ff55 <= di_d; + end + if ( we && wa == 7'd56 ) begin + ram_ff56 <= di_d; + end + if ( we && wa == 7'd57 ) begin + ram_ff57 <= di_d; + end + if ( we && wa == 7'd58 ) begin + ram_ff58 <= di_d; + end + if ( we && wa == 7'd59 ) begin + ram_ff59 <= di_d; + end + if ( we && wa == 7'd60 ) begin + ram_ff60 <= di_d; + end + if ( we && wa == 7'd61 ) begin + ram_ff61 <= di_d; + end + if ( we && wa == 7'd62 ) begin + ram_ff62 <= di_d; + end + if ( we && wa == 7'd63 ) begin + ram_ff63 <= di_d; + end + if ( we && wa == 7'd64 ) begin + ram_ff64 <= di_d; + end + if ( we && wa == 7'd65 ) begin + ram_ff65 <= di_d; + end + if ( we && wa == 7'd66 ) begin + ram_ff66 <= di_d; + end + if ( we && wa == 7'd67 ) begin + ram_ff67 <= di_d; + end + if ( we && wa == 7'd68 ) begin + ram_ff68 <= di_d; + end + if ( we && wa == 7'd69 ) begin + ram_ff69 <= di_d; + end + if ( we && wa == 7'd70 ) begin + ram_ff70 <= di_d; + end + if ( we && wa == 7'd71 ) begin + ram_ff71 <= di_d; + end + if ( we && wa == 7'd72 ) begin + ram_ff72 <= di_d; + end + if ( we && wa == 7'd73 ) begin + ram_ff73 <= di_d; + end + if ( we && wa == 7'd74 ) begin + ram_ff74 <= di_d; + end + if ( we && wa == 7'd75 ) begin + ram_ff75 <= di_d; + end + if ( we && wa == 7'd76 ) begin + ram_ff76 <= di_d; + end + if ( we && wa == 7'd77 ) begin + ram_ff77 <= di_d; + end + if ( we && wa == 7'd78 ) begin + ram_ff78 <= di_d; + end + if ( we && wa == 7'd79 ) begin + ram_ff79 <= di_d; + end + if ( we && wa == 7'd80 ) begin + ram_ff80 <= di_d; + end + if ( we && wa == 7'd81 ) begin + ram_ff81 <= di_d; + end + if ( we && wa == 7'd82 ) begin + ram_ff82 <= di_d; + end + if ( we && wa == 7'd83 ) begin + ram_ff83 <= di_d; + end + if ( we && wa == 7'd84 ) begin + ram_ff84 <= di_d; + end + if ( we && wa == 7'd85 ) begin + ram_ff85 <= di_d; + end + if ( we && wa == 7'd86 ) begin + ram_ff86 <= di_d; + end + if ( we && wa == 7'd87 ) begin + ram_ff87 <= di_d; + end + if ( we && wa == 7'd88 ) begin + ram_ff88 <= di_d; + end + if ( we && wa == 7'd89 ) begin + ram_ff89 <= di_d; + end + if ( we && wa == 7'd90 ) begin + ram_ff90 <= di_d; + end + if ( we && wa == 7'd91 ) begin + ram_ff91 <= di_d; + end + if ( we && wa == 7'd92 ) begin + ram_ff92 <= di_d; + end + if ( we && wa == 7'd93 ) begin + ram_ff93 <= di_d; + end + if ( we && wa == 7'd94 ) begin + ram_ff94 <= di_d; + end + if ( we && wa == 7'd95 ) begin + ram_ff95 <= di_d; + end + if ( we && wa == 7'd96 ) begin + ram_ff96 <= di_d; + end + if ( we && wa == 7'd97 ) begin + ram_ff97 <= di_d; + end + if ( we && wa == 7'd98 ) begin + ram_ff98 <= di_d; + end + if ( we && wa == 7'd99 ) begin + ram_ff99 <= di_d; + end + if ( we && wa == 7'd100 ) begin + ram_ff100 <= di_d; + end + if ( we && wa == 7'd101 ) begin + ram_ff101 <= di_d; + end + if ( we && wa == 7'd102 ) begin + ram_ff102 <= di_d; + end + if ( we && wa == 7'd103 ) begin + ram_ff103 <= di_d; + end + if ( we && wa == 7'd104 ) begin + ram_ff104 <= di_d; + end + if ( we && wa == 7'd105 ) begin + ram_ff105 <= di_d; + end + if ( we && wa == 7'd106 ) begin + ram_ff106 <= di_d; + end + if ( we && wa == 7'd107 ) begin + ram_ff107 <= di_d; + end + if ( we && wa == 7'd108 ) begin + ram_ff108 <= di_d; + end + if ( we && wa == 7'd109 ) begin + ram_ff109 <= di_d; + end + if ( we && wa == 7'd110 ) begin + ram_ff110 <= di_d; + end + if ( we && wa == 7'd111 ) begin + ram_ff111 <= di_d; + end + if ( we && wa == 7'd112 ) begin + ram_ff112 <= di_d; + end + if ( we && wa == 7'd113 ) begin + ram_ff113 <= di_d; + end + if ( we && wa == 7'd114 ) begin + ram_ff114 <= di_d; + end + if ( we && wa == 7'd115 ) begin + ram_ff115 <= di_d; + end + if ( we && wa == 7'd116 ) begin + ram_ff116 <= di_d; + end + if ( we && wa == 7'd117 ) begin + ram_ff117 <= di_d; + end + if ( we && wa == 7'd118 ) begin + ram_ff118 <= di_d; + end + if ( we && wa == 7'd119 ) begin + ram_ff119 <= di_d; + end + if ( we && wa == 7'd120 ) begin + ram_ff120 <= di_d; + end + if ( we && wa == 7'd121 ) begin + ram_ff121 <= di_d; + end + if ( we && wa == 7'd122 ) begin + ram_ff122 <= di_d; + end + if ( we && wa == 7'd123 ) begin + ram_ff123 <= di_d; + end + if ( we && wa == 7'd124 ) begin + ram_ff124 <= di_d; + end + if ( we && wa == 7'd125 ) begin + ram_ff125 <= di_d; + end + if ( we && wa == 7'd126 ) begin + ram_ff126 <= di_d; + end + if ( we && wa == 7'd127 ) begin + ram_ff127 <= di_d; + end +end +reg [10:0] dout; +always @(*) begin + case( ra ) + 8'd0: dout = ram_ff0; + 8'd1: dout = ram_ff1; + 8'd2: dout = ram_ff2; + 8'd3: dout = ram_ff3; + 8'd4: dout = ram_ff4; + 8'd5: dout = ram_ff5; + 8'd6: dout = ram_ff6; + 8'd7: dout = ram_ff7; + 8'd8: dout = ram_ff8; + 8'd9: dout = ram_ff9; + 8'd10: dout = ram_ff10; + 8'd11: dout = ram_ff11; + 8'd12: dout = ram_ff12; + 8'd13: dout = ram_ff13; + 8'd14: dout = ram_ff14; + 8'd15: dout = ram_ff15; + 8'd16: dout = ram_ff16; + 8'd17: dout = ram_ff17; + 8'd18: dout = ram_ff18; + 8'd19: dout = ram_ff19; + 8'd20: dout = ram_ff20; + 8'd21: dout = ram_ff21; + 8'd22: dout = ram_ff22; + 8'd23: dout = ram_ff23; + 8'd24: dout = ram_ff24; + 8'd25: dout = ram_ff25; + 8'd26: dout = ram_ff26; + 8'd27: dout = ram_ff27; + 8'd28: dout = ram_ff28; + 8'd29: dout = ram_ff29; + 8'd30: dout = ram_ff30; + 8'd31: dout = ram_ff31; + 8'd32: dout = ram_ff32; + 8'd33: dout = ram_ff33; + 8'd34: dout = ram_ff34; + 8'd35: dout = ram_ff35; + 8'd36: dout = ram_ff36; + 8'd37: dout = ram_ff37; + 8'd38: dout = ram_ff38; + 8'd39: dout = ram_ff39; + 8'd40: dout = ram_ff40; + 8'd41: dout = ram_ff41; + 8'd42: dout = ram_ff42; + 8'd43: dout = ram_ff43; + 8'd44: dout = ram_ff44; + 8'd45: dout = ram_ff45; + 8'd46: dout = ram_ff46; + 8'd47: dout = ram_ff47; + 8'd48: dout = ram_ff48; + 8'd49: dout = ram_ff49; + 8'd50: dout = ram_ff50; + 8'd51: dout = ram_ff51; + 8'd52: dout = ram_ff52; + 8'd53: dout = ram_ff53; + 8'd54: dout = ram_ff54; + 8'd55: dout = ram_ff55; + 8'd56: dout = ram_ff56; + 8'd57: dout = ram_ff57; + 8'd58: dout = ram_ff58; + 8'd59: dout = ram_ff59; + 8'd60: dout = ram_ff60; + 8'd61: dout = ram_ff61; + 8'd62: dout = ram_ff62; + 8'd63: dout = ram_ff63; + 8'd64: dout = ram_ff64; + 8'd65: dout = ram_ff65; + 8'd66: dout = ram_ff66; + 8'd67: dout = ram_ff67; + 8'd68: dout = ram_ff68; + 8'd69: dout = ram_ff69; + 8'd70: dout = ram_ff70; + 8'd71: dout = ram_ff71; + 8'd72: dout = ram_ff72; + 8'd73: dout = ram_ff73; + 8'd74: dout = ram_ff74; + 8'd75: dout = ram_ff75; + 8'd76: dout = ram_ff76; + 8'd77: dout = ram_ff77; + 8'd78: dout = ram_ff78; + 8'd79: dout = ram_ff79; + 8'd80: dout = ram_ff80; + 8'd81: dout = ram_ff81; + 8'd82: dout = ram_ff82; + 8'd83: dout = ram_ff83; + 8'd84: dout = ram_ff84; + 8'd85: dout = ram_ff85; + 8'd86: dout = ram_ff86; + 8'd87: dout = ram_ff87; + 8'd88: dout = ram_ff88; + 8'd89: dout = ram_ff89; + 8'd90: dout = ram_ff90; + 8'd91: dout = ram_ff91; + 8'd92: dout = ram_ff92; + 8'd93: dout = ram_ff93; + 8'd94: dout = ram_ff94; + 8'd95: dout = ram_ff95; + 8'd96: dout = ram_ff96; + 8'd97: dout = ram_ff97; + 8'd98: dout = ram_ff98; + 8'd99: dout = ram_ff99; + 8'd100: dout = ram_ff100; + 8'd101: dout = ram_ff101; + 8'd102: dout = ram_ff102; + 8'd103: dout = ram_ff103; + 8'd104: dout = ram_ff104; + 8'd105: dout = ram_ff105; + 8'd106: dout = ram_ff106; + 8'd107: dout = ram_ff107; + 8'd108: dout = ram_ff108; + 8'd109: dout = ram_ff109; + 8'd110: dout = ram_ff110; + 8'd111: dout = ram_ff111; + 8'd112: dout = ram_ff112; + 8'd113: dout = ram_ff113; + 8'd114: dout = ram_ff114; + 8'd115: dout = ram_ff115; + 8'd116: dout = ram_ff116; + 8'd117: dout = ram_ff117; + 8'd118: dout = ram_ff118; + 8'd119: dout = ram_ff119; + 8'd120: dout = ram_ff120; + 8'd121: dout = ram_ff121; + 8'd122: dout = ram_ff122; + 8'd123: dout = ram_ff123; + 8'd124: dout = ram_ff124; + 8'd125: dout = ram_ff125; + 8'd126: dout = ram_ff126; + 8'd127: dout = ram_ff127; + 8'd128: dout = di_d; +//VCS coverage off + default: dout = {11{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [6:0] Wa0; +input we0; +input [10:0] Di0; +input [6:0] Ra0; +output [10:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 11'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [10:0] mem[127:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [10:0] Q0 = mem[0]; +wire [10:0] Q1 = mem[1]; +wire [10:0] Q2 = mem[2]; +wire [10:0] Q3 = mem[3]; +wire [10:0] Q4 = mem[4]; +wire [10:0] Q5 = mem[5]; +wire [10:0] Q6 = mem[6]; +wire [10:0] Q7 = mem[7]; +wire [10:0] Q8 = mem[8]; +wire [10:0] Q9 = mem[9]; +wire [10:0] Q10 = mem[10]; +wire [10:0] Q11 = mem[11]; +wire [10:0] Q12 = mem[12]; +wire [10:0] Q13 = mem[13]; +wire [10:0] Q14 = mem[14]; +wire [10:0] Q15 = mem[15]; +wire [10:0] Q16 = mem[16]; +wire [10:0] Q17 = mem[17]; +wire [10:0] Q18 = mem[18]; +wire [10:0] Q19 = mem[19]; +wire [10:0] Q20 = mem[20]; +wire [10:0] Q21 = mem[21]; +wire [10:0] Q22 = mem[22]; +wire [10:0] Q23 = mem[23]; +wire [10:0] Q24 = mem[24]; +wire [10:0] Q25 = mem[25]; +wire [10:0] Q26 = mem[26]; +wire [10:0] Q27 = mem[27]; +wire [10:0] Q28 = mem[28]; +wire [10:0] Q29 = mem[29]; +wire [10:0] Q30 = mem[30]; +wire [10:0] Q31 = mem[31]; +wire [10:0] Q32 = mem[32]; +wire [10:0] Q33 = mem[33]; +wire [10:0] Q34 = mem[34]; +wire [10:0] Q35 = mem[35]; +wire [10:0] Q36 = mem[36]; +wire [10:0] Q37 = mem[37]; +wire [10:0] Q38 = mem[38]; +wire [10:0] Q39 = mem[39]; +wire [10:0] Q40 = mem[40]; +wire [10:0] Q41 = mem[41]; +wire [10:0] Q42 = mem[42]; +wire [10:0] Q43 = mem[43]; +wire [10:0] Q44 = mem[44]; +wire [10:0] Q45 = mem[45]; +wire [10:0] Q46 = mem[46]; +wire [10:0] Q47 = mem[47]; +wire [10:0] Q48 = mem[48]; +wire [10:0] Q49 = mem[49]; +wire [10:0] Q50 = mem[50]; +wire [10:0] Q51 = mem[51]; +wire [10:0] Q52 = mem[52]; +wire [10:0] Q53 = mem[53]; +wire [10:0] Q54 = mem[54]; +wire [10:0] Q55 = mem[55]; +wire [10:0] Q56 = mem[56]; +wire [10:0] Q57 = mem[57]; +wire [10:0] Q58 = mem[58]; +wire [10:0] Q59 = mem[59]; +wire [10:0] Q60 = mem[60]; +wire [10:0] Q61 = mem[61]; +wire [10:0] Q62 = mem[62]; +wire [10:0] Q63 = mem[63]; +wire [10:0] Q64 = mem[64]; +wire [10:0] Q65 = mem[65]; +wire [10:0] Q66 = mem[66]; +wire [10:0] Q67 = mem[67]; +wire [10:0] Q68 = mem[68]; +wire [10:0] Q69 = mem[69]; +wire [10:0] Q70 = mem[70]; +wire [10:0] Q71 = mem[71]; +wire [10:0] Q72 = mem[72]; +wire [10:0] Q73 = mem[73]; +wire [10:0] Q74 = mem[74]; +wire [10:0] Q75 = mem[75]; +wire [10:0] Q76 = mem[76]; +wire [10:0] Q77 = mem[77]; +wire [10:0] Q78 = mem[78]; +wire [10:0] Q79 = mem[79]; +wire [10:0] Q80 = mem[80]; +wire [10:0] Q81 = mem[81]; +wire [10:0] Q82 = mem[82]; +wire [10:0] Q83 = mem[83]; +wire [10:0] Q84 = mem[84]; +wire [10:0] Q85 = mem[85]; +wire [10:0] Q86 = mem[86]; +wire [10:0] Q87 = mem[87]; +wire [10:0] Q88 = mem[88]; +wire [10:0] Q89 = mem[89]; +wire [10:0] Q90 = mem[90]; +wire [10:0] Q91 = mem[91]; +wire [10:0] Q92 = mem[92]; +wire [10:0] Q93 = mem[93]; +wire [10:0] Q94 = mem[94]; +wire [10:0] Q95 = mem[95]; +wire [10:0] Q96 = mem[96]; +wire [10:0] Q97 = mem[97]; +wire [10:0] Q98 = mem[98]; +wire [10:0] Q99 = mem[99]; +wire [10:0] Q100 = mem[100]; +wire [10:0] Q101 = mem[101]; +wire [10:0] Q102 = mem[102]; +wire [10:0] Q103 = mem[103]; +wire [10:0] Q104 = mem[104]; +wire [10:0] Q105 = mem[105]; +wire [10:0] Q106 = mem[106]; +wire [10:0] Q107 = mem[107]; +wire [10:0] Q108 = mem[108]; +wire [10:0] Q109 = mem[109]; +wire [10:0] Q110 = mem[110]; +wire [10:0] Q111 = mem[111]; +wire [10:0] Q112 = mem[112]; +wire [10:0] Q113 = mem[113]; +wire [10:0] Q114 = mem[114]; +wire [10:0] Q115 = mem[115]; +wire [10:0] Q116 = mem[116]; +wire [10:0] Q117 = mem[117]; +wire [10:0] Q118 = mem[118]; +wire [10:0] Q119 = mem[119]; +wire [10:0] Q120 = mem[120]; +wire [10:0] Q121 = mem[121]; +wire [10:0] Q122 = mem[122]; +wire [10:0] Q123 = mem[123]; +wire [10:0] Q124 = mem[124]; +wire [10:0] Q125 = mem[125]; +wire [10:0] Q126 = mem[126]; +wire [10:0] Q127 = mem[127]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11] } +endmodule // vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +//vmw: Memory vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +//vmw: Address-size 7 +//vmw: Data-size 11 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[10:0] data0[10:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[10:0] data1[10:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v new file mode 100644 index 0000000..745b6a2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v @@ -0,0 +1,538 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WG_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WG_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [4:0] wr_data; +input rd_ready; +output rd_req; +output [4:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [4:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {5{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [4:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire [31 : 0] pwrbus_ram_pd; +NV_NVDLA_CDMA_WG_fifo_folded_ram_rws_128x5 ram ( + .clk ( clk ) + , .clk_mgated ( clk_mgated ) + , .reset_ ( reset_ ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [4:0] rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge clk_mgated ) begin + if ( (rd_popping) ) begin + rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + rd_data <= {5{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WG_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WG_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WG_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WG_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WG_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_WG_fifo +// folded ram wrapper +// +module NV_NVDLA_CDMA_WG_fifo_folded_ram_rws_128x5( + clk + , clk_mgated + , reset_ + , pwrbus_ram_pd + , wa + , we + , di + , ra + , re + , dout + ); +input clk; +input clk_mgated; +input reset_; +input [31 : 0] pwrbus_ram_pd; +input [6:0] wa; +input we; +input [4:0] di; +input [6:0] ra; +input re; +output [4:0] dout; +// Folded Ram +// +// We assume incrementing write addresses. +// The read address could get backed up if there is flow control. +// +// We keep a write collection buffer (buff). +// We don't write it into the ram (we_f) until we write the first datum of the next row. +// The read side may read from the buffer instead of the ram if the data is there (use_buff_d_next). +// When the read side does read from the ram (re_f), it does it once per row. +// +// One special case to worry about is when a write and read are occurring to the +// same address in the same cycle. That is allowed only when -ram_bypass_reg +// is in effect. If -ram_bypass_reg is implemented externally to this module, +// then we just do a dummy use_buff_d_next=1 even though the data will be wrong +// and ignored. If -ram_bypass_reg is implemented internally to this module (default), +// then we use_buff_d_next=1 and also copy di to buff_d. Both cases prevent us +// from doing reads to the underlying ram. +// +// In the near future, we will optimize away some unnecessary assertions of we_f and re_f +// to the ram. We seem to have a general problem at a higher level (even in non-folded +// rams) of having some superfluous assertions of these power-wasting signals. +// Some changes need to be made above this level to fix this. For now, we keep it +// the same as with non-folded rams. +// +// If master clk gating (SLCG) is in effect, then the logic here is gated +// by the mgated clk, but the ram itself is not gated because it has its own SLCG. +// +reg [9:0] buff; +reg [6:0] buff_wa; +wire [5:0] buff_wa_f = buff_wa[6:1]; +wire [5:0] ra_f = ra[6:1]; +wire same_addr_write_and_read = we && re && wa == ra; +wire use_buff_d_next = (ra_f == buff_wa_f && buff_wa[0:0] >= ra[0:0]) || same_addr_write_and_read; +reg use_buff_d; +wire we_f = we && wa[0:0] == 1'd0; +reg did_re_f; +wire re_f = re && !use_buff_d_next && (ra[0:0] == 1'd0 || !did_re_f); +reg [4:0] buff_d; +wire [9:0] dout_f; +reg [0:0] ro_d; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + buff_wa <= 7'd0; + did_re_f <= 1'd0; + end else begin + if ( we ) begin + buff_wa <= wa; // note: resettable to avoid ramgen assert during first superfluous write + end + did_re_f <= re_f || (!use_buff_d_next && did_re_f && ra[0:0] != 1'd0); + end +end +always @( posedge clk_mgated ) begin + if ( we ) begin + case( wa[0:0] ) + 1'd0: buff[4:0] <= di; + 1'd1: buff[9:5] <= di; +// VCS coverage off + default: buff <= {10{`x_or_0}}; +// VCS coverage on + endcase + end + if ( re ) begin + if ( use_buff_d_next ) begin + use_buff_d <= 1'b1; + case( ra[0:0] ) + 1'd0: buff_d <= buff[4:0]; + 1'd1: buff_d <= buff[9:5]; +// VCS coverage off + default: buff_d <= {5{`x_or_0}}; +// VCS coverage on + endcase + end else begin + use_buff_d <= 1'b0; + ro_d <= ra[0:0]; + end + end +end +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rws_64x10 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( buff_wa_f ) + , .we ( we_f ) + , .di ( buff ) + , .ra ( ra_f ) + , .re ( re_f ) + , .dout ( dout_f ) + ); +reg [4:0] dout_fm; +always @(*) begin + case( ro_d ) + 1'd0: dout_fm = dout_f[4:0]; + 1'd1: dout_fm = dout_f[9:5]; +// VCS coverage off + default: dout_fm = {5{`x_or_0}}; +// VCS coverage on + endcase +end +assign dout = use_buff_d ? buff_d : dout_fm; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v.vcp new file mode 100644 index 0000000..745b6a2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v.vcp @@ -0,0 +1,538 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WG_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WG_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [4:0] wr_data; +input rd_ready; +output rd_req; +output [4:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [4:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {5{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [4:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire [31 : 0] pwrbus_ram_pd; +NV_NVDLA_CDMA_WG_fifo_folded_ram_rws_128x5 ram ( + .clk ( clk ) + , .clk_mgated ( clk_mgated ) + , .reset_ ( reset_ ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [4:0] rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge clk_mgated ) begin + if ( (rd_popping) ) begin + rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + rd_data <= {5{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WG_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WG_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WG_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WG_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WG_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_WG_fifo +// folded ram wrapper +// +module NV_NVDLA_CDMA_WG_fifo_folded_ram_rws_128x5( + clk + , clk_mgated + , reset_ + , pwrbus_ram_pd + , wa + , we + , di + , ra + , re + , dout + ); +input clk; +input clk_mgated; +input reset_; +input [31 : 0] pwrbus_ram_pd; +input [6:0] wa; +input we; +input [4:0] di; +input [6:0] ra; +input re; +output [4:0] dout; +// Folded Ram +// +// We assume incrementing write addresses. +// The read address could get backed up if there is flow control. +// +// We keep a write collection buffer (buff). +// We don't write it into the ram (we_f) until we write the first datum of the next row. +// The read side may read from the buffer instead of the ram if the data is there (use_buff_d_next). +// When the read side does read from the ram (re_f), it does it once per row. +// +// One special case to worry about is when a write and read are occurring to the +// same address in the same cycle. That is allowed only when -ram_bypass_reg +// is in effect. If -ram_bypass_reg is implemented externally to this module, +// then we just do a dummy use_buff_d_next=1 even though the data will be wrong +// and ignored. If -ram_bypass_reg is implemented internally to this module (default), +// then we use_buff_d_next=1 and also copy di to buff_d. Both cases prevent us +// from doing reads to the underlying ram. +// +// In the near future, we will optimize away some unnecessary assertions of we_f and re_f +// to the ram. We seem to have a general problem at a higher level (even in non-folded +// rams) of having some superfluous assertions of these power-wasting signals. +// Some changes need to be made above this level to fix this. For now, we keep it +// the same as with non-folded rams. +// +// If master clk gating (SLCG) is in effect, then the logic here is gated +// by the mgated clk, but the ram itself is not gated because it has its own SLCG. +// +reg [9:0] buff; +reg [6:0] buff_wa; +wire [5:0] buff_wa_f = buff_wa[6:1]; +wire [5:0] ra_f = ra[6:1]; +wire same_addr_write_and_read = we && re && wa == ra; +wire use_buff_d_next = (ra_f == buff_wa_f && buff_wa[0:0] >= ra[0:0]) || same_addr_write_and_read; +reg use_buff_d; +wire we_f = we && wa[0:0] == 1'd0; +reg did_re_f; +wire re_f = re && !use_buff_d_next && (ra[0:0] == 1'd0 || !did_re_f); +reg [4:0] buff_d; +wire [9:0] dout_f; +reg [0:0] ro_d; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + buff_wa <= 7'd0; + did_re_f <= 1'd0; + end else begin + if ( we ) begin + buff_wa <= wa; // note: resettable to avoid ramgen assert during first superfluous write + end + did_re_f <= re_f || (!use_buff_d_next && did_re_f && ra[0:0] != 1'd0); + end +end +always @( posedge clk_mgated ) begin + if ( we ) begin + case( wa[0:0] ) + 1'd0: buff[4:0] <= di; + 1'd1: buff[9:5] <= di; +// VCS coverage off + default: buff <= {10{`x_or_0}}; +// VCS coverage on + endcase + end + if ( re ) begin + if ( use_buff_d_next ) begin + use_buff_d <= 1'b1; + case( ra[0:0] ) + 1'd0: buff_d <= buff[4:0]; + 1'd1: buff_d <= buff[9:5]; +// VCS coverage off + default: buff_d <= {5{`x_or_0}}; +// VCS coverage on + endcase + end else begin + use_buff_d <= 1'b0; + ro_d <= ra[0:0]; + end + end +end +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rws_64x10 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( buff_wa_f ) + , .we ( we_f ) + , .di ( buff ) + , .ra ( ra_f ) + , .re ( re_f ) + , .dout ( dout_f ) + ); +reg [4:0] dout_fm; +always @(*) begin + case( ro_d ) + 1'd0: dout_fm = dout_f[4:0]; + 1'd1: dout_fm = dout_f[9:5]; +// VCS coverage off + default: dout_fm = {5{`x_or_0}}; +// VCS coverage on + endcase +end +assign dout = use_buff_d ? buff_d : dout_fm; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v new file mode 100644 index 0000000..fc2d010 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [5:0] wr_data; +input rd_ready; +output rd_req; +output [5:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [5:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {6{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [5:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_128x6 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WT_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WT_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_WT_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v.vcp new file mode 100644 index 0000000..fc2d010 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v.vcp @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [5:0] wr_data; +input rd_ready; +output rd_req; +output [5:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [5:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {6{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_128 = ( wr_count_next_no_wr_popping == 8'd128 ); +wire wr_count_next_is_128 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_128; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_128 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 8'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [6:0] wr_adr; // current write address +wire [6:0] rd_adr_p; // read address to use for ram +wire [5:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_128x6 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [7:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 8'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WT_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd128 : wr_limit_reg} ) + , .curr ( {24'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WT_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_WT_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v new file mode 100644 index 0000000..95696c2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v @@ -0,0 +1,68 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_sp_arb.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_sp_arb ( + req0 + ,req1 + ,gnt_busy + ,gnt0 + ,gnt1 + ); +//Declaring ports +input req0; +input req1; +input gnt_busy; +output gnt0; +output gnt1; +//Declaring registers and wires +reg [1:0] gnt; +reg [1:0] gnt_pre; +wire [1:0] req; +assign req = { + req1 +,req0 +}; +assign { + gnt1 +,gnt0 +} = gnt; +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {2{!gnt_busy}} & gnt_pre; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +always @( + req + ) begin + gnt_pre = 2'd0; + casez (req) + 2'b?1: begin + gnt_pre[0] = 1'b1; + end + 2'b10: begin + gnt_pre[1] = 1'b1; + end + 2'b00: begin + gnt_pre = 2'd0; + end +//VCS coverage off + default : begin + gnt_pre[1:0] = {2{`x_or_0}}; + end +//VCS coverage on + endcase +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +endmodule // NV_NVDLA_CDMA_WT_sp_arb diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v.vcp new file mode 100644 index 0000000..95696c2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v.vcp @@ -0,0 +1,68 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_sp_arb.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_sp_arb ( + req0 + ,req1 + ,gnt_busy + ,gnt0 + ,gnt1 + ); +//Declaring ports +input req0; +input req1; +input gnt_busy; +output gnt0; +output gnt1; +//Declaring registers and wires +reg [1:0] gnt; +reg [1:0] gnt_pre; +wire [1:0] req; +assign req = { + req1 +,req0 +}; +assign { + gnt1 +,gnt0 +} = gnt; +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {2{!gnt_busy}} & gnt_pre; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +always @( + req + ) begin + gnt_pre = 2'd0; + casez (req) + 2'b?1: begin + gnt_pre[0] = 1'b1; + end + 2'b10: begin + gnt_pre[1] = 1'b1; + end + 2'b00: begin + gnt_pre = 2'd0; + end +//VCS coverage off + default : begin + gnt_pre[1:0] = {2{`x_or_0}}; + end +//VCS coverage on + endcase +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +endmodule // NV_NVDLA_CDMA_WT_sp_arb diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v new file mode 100644 index 0000000..c6a5059 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_wgs_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_wgs_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [31:0] wr_data; +input rd_ready; +output rd_req; +output [31:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [31:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {32{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_32 = ( wr_count_next_no_wr_popping == 6'd32 ); +wire wr_count_next_is_32 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_32; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_32 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 6'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [4:0] wr_adr; // current write address +wire [4:0] rd_adr_p; // read address to use for ram +wire [31:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_32x32 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [4:0] rd_adr; // current read address +// next read address +wire [4:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [5:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 6'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd32 : wr_limit_reg} ) + , .curr ( {26'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WT_wgs_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_WT_wgs_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v.vcp new file mode 100644 index 0000000..c6a5059 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v.vcp @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_wgs_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_wgs_fifo ( + clk + , reset_ + , wr_ready + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +input wr_req; +input [31:0] wr_data; +input rd_ready; +output rd_req; +output [31:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg [31:0] wr_data_in; // registered wr_data +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge clk ) begin + if ( !wr_busy_in && wr_req ) begin + wr_data_in <= wr_data; + end +//synopsys translate_off + else if ( !(!wr_busy_in && wr_req) ) begin + end else begin + wr_data_in <= {32{`x_or_0}}; + end +//synopsys translate_on +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_32 = ( wr_count_next_no_wr_popping == 6'd32 ); +wire wr_count_next_is_32 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_32; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_32 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 6'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [4:0] wr_adr; // current write address +wire [4:0] rd_adr_p; // read address to use for ram +wire [31:0] rd_data_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_32x32 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( wr_adr ) + , .we ( wr_pushing ) + , .di ( wr_data_in ) + , .ra ( rd_adr_p ) + , .re ( rd_enable ) + , .dout ( rd_data_p ) + , .ore ( ore ) + ); +// next wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + wr_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [4:0] rd_adr; // current read address +// next read address +wire [4:0] rd_adr_next = rd_adr + 1'd1; // spyglass disable W484 +assign rd_adr_p = rd_popping ? rd_adr_next : rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [5:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~rd_req_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count_p <= 6'd0; + rd_req_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rd_req_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_req_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +assign rd_data = rd_data_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req_int && rd_ready) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WT_wgs_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd32 : wr_limit_reg} ) + , .curr ( {26'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WT_wgs_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDMA_WT_wgs_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v new file mode 100644 index 0000000..a04f87e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v @@ -0,0 +1,594 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_wrr_arb.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_wrr_arb ( + req0 + ,req1 + ,wt0 + ,wt1 + ,gnt_busy + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ); +//Declaring ports +input req0; +input req1; +input [4:0] wt0; +input [4:0] wt1; +input gnt_busy; +input clk; +input reset_; +output gnt0; +output gnt1; +//Declaring clock and reset +//Declaring registers and wires +reg [1:0] gnt; +reg [1:0] gnt_pre; +reg [1:0] wrr_gnt; +reg [4:0] wt_left; +reg [4:0] wt_left_nxt; +wire [4:0] new_wt_left0; +wire [4:0] new_wt_left1; +wire [1:0] req; +assign req = { + (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt1 +,gnt0 +} = gnt; +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {2{!gnt_busy}} & gnt_pre; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[4:0] = wt0 - 1'b1; +assign new_wt_left1[4:0] = wt1 - 1'b1; +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + ) begin + gnt_pre = {2{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 2'b00 : begin + if (req[0]) begin + gnt_pre = 2'b01; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 2'b10; + wt_left_nxt = new_wt_left1; + end + end + 2'b01 : begin + if (req[1]) begin + gnt_pre = 2'b10; + wt_left_nxt = new_wt_left1; + end + else if (req[0]) begin + gnt_pre = 2'b01; + wt_left_nxt = new_wt_left0; + end + end + 2'b10 : begin + if (req[0]) begin + gnt_pre = 2'b01; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 2'b10; + wt_left_nxt = new_wt_left1; + end + end +//VCS coverage off + default : begin + gnt_pre[1:0] = {2{`x_or_0}}; + wt_left_nxt[4:0] = {5{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {2{1'b0}}; + wt_left <= {5{1'b0}}; + end else begin + if (!gnt_busy & req != {2{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end + end +end +//end of always block +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,2,0,"gnt not zero one hot") zzz_grant_zero_one_hot_1x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_2x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_3x (clk, `ASSERT_RESET, (!gnt_busy & |(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt when gnt_busy ") zzz_gnt_when_busy_4x (clk, `ASSERT_RESET, (gnt_busy & |gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef COVER +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_clk = clk; +wire testpoint_0_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_reset_ +// Clock signal: testpoint_0_internal_clk + reg testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk; + initial + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b0; + always @(posedge testpoint_0_internal_clk or negedge testpoint_0_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_reset_) + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_WT_wrr_arb ::: Client 0 granted ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 0 granted ::: testpoint_0_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_clk = clk; +wire testpoint_1_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_reset_ +// Clock signal: testpoint_1_internal_clk + reg testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk; + initial + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b0; + always @(posedge testpoint_1_internal_clk or negedge testpoint_1_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_reset_) + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_WT_wrr_arb ::: Client 1 granted ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 1 granted ::: testpoint_1_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_2_internal_clk = clk; +wire testpoint_2_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_2_internal_reset_ +// Clock signal: testpoint_2_internal_clk + reg testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk; + initial + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b0; + always @(posedge testpoint_2_internal_clk or negedge testpoint_2_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_2 + if (~testpoint_2_internal_reset_) + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_2_count_0; + reg testpoint_2_goal_0; + initial testpoint_2_goal_0 = 0; + initial testpoint_2_count_0 = 0; + always@(testpoint_2_count_0) begin + if(testpoint_2_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_2_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_WT_wrr_arb ::: All clients requesting at the same time ::: ( req[0] && req[1])"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_WT_wrr_arb ::: All clients requesting at the same time ::: testpoint_2_goal_0 + testpoint_2_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_2_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_2_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2 + if (testpoint_2_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_WT_wrr_arb ::: All clients requesting at the same time ::: testpoint_2_goal_0"); + `endif + if ((( req[0] && req[1])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + testpoint_2_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) begin + `endif + testpoint_2_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_2_goal_0_active = ((( req[0] && req[1])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +endmodule // NV_NVDLA_CDMA_WT_wrr_arb diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v.vcp new file mode 100644 index 0000000..a04f87e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v.vcp @@ -0,0 +1,594 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_WT_wrr_arb.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_wrr_arb ( + req0 + ,req1 + ,wt0 + ,wt1 + ,gnt_busy + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ); +//Declaring ports +input req0; +input req1; +input [4:0] wt0; +input [4:0] wt1; +input gnt_busy; +input clk; +input reset_; +output gnt0; +output gnt1; +//Declaring clock and reset +//Declaring registers and wires +reg [1:0] gnt; +reg [1:0] gnt_pre; +reg [1:0] wrr_gnt; +reg [4:0] wt_left; +reg [4:0] wt_left_nxt; +wire [4:0] new_wt_left0; +wire [4:0] new_wt_left1; +wire [1:0] req; +assign req = { + (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt1 +,gnt0 +} = gnt; +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {2{!gnt_busy}} & gnt_pre; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[4:0] = wt0 - 1'b1; +assign new_wt_left1[4:0] = wt1 - 1'b1; +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + ) begin + gnt_pre = {2{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 2'b00 : begin + if (req[0]) begin + gnt_pre = 2'b01; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 2'b10; + wt_left_nxt = new_wt_left1; + end + end + 2'b01 : begin + if (req[1]) begin + gnt_pre = 2'b10; + wt_left_nxt = new_wt_left1; + end + else if (req[0]) begin + gnt_pre = 2'b01; + wt_left_nxt = new_wt_left0; + end + end + 2'b10 : begin + if (req[0]) begin + gnt_pre = 2'b01; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 2'b10; + wt_left_nxt = new_wt_left1; + end + end +//VCS coverage off + default : begin + gnt_pre[1:0] = {2{`x_or_0}}; + wt_left_nxt[4:0] = {5{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {2{1'b0}}; + wt_left <= {5{1'b0}}; + end else begin + if (!gnt_busy & req != {2{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end + end +end +//end of always block +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,2,0,"gnt not zero one hot") zzz_grant_zero_one_hot_1x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_2x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_3x (clk, `ASSERT_RESET, (!gnt_busy & |(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt when gnt_busy ") zzz_gnt_when_busy_4x (clk, `ASSERT_RESET, (gnt_busy & |gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef COVER +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_clk = clk; +wire testpoint_0_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_reset_ +// Clock signal: testpoint_0_internal_clk + reg testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk; + initial + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b0; + always @(posedge testpoint_0_internal_clk or negedge testpoint_0_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_reset_) + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_WT_wrr_arb ::: Client 0 granted ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 0 granted ::: testpoint_0_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_clk = clk; +wire testpoint_1_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_reset_ +// Clock signal: testpoint_1_internal_clk + reg testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk; + initial + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b0; + always @(posedge testpoint_1_internal_clk or negedge testpoint_1_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_reset_) + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_WT_wrr_arb ::: Client 1 granted ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_WT_wrr_arb ::: Client 1 granted ::: testpoint_1_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_2_internal_clk = clk; +wire testpoint_2_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_2_internal_reset_ +// Clock signal: testpoint_2_internal_clk + reg testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk; + initial + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b0; + always @(posedge testpoint_2_internal_clk or negedge testpoint_2_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_2 + if (~testpoint_2_internal_reset_) + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_2_count_0; + reg testpoint_2_goal_0; + initial testpoint_2_goal_0 = 0; + initial testpoint_2_count_0 = 0; + always@(testpoint_2_count_0) begin + if(testpoint_2_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_2_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_WT_wrr_arb ::: All clients requesting at the same time ::: ( req[0] && req[1])"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_WT_wrr_arb ::: All clients requesting at the same time ::: testpoint_2_goal_0 + testpoint_2_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_2_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_2_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2 + if (testpoint_2_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_WT_wrr_arb ::: All clients requesting at the same time ::: testpoint_2_goal_0"); + `endif + if ((( req[0] && req[1])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + testpoint_2_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) begin + `endif + testpoint_2_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_2_goal_0_active = ((( req[0] && req[1])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +endmodule // NV_NVDLA_CDMA_WT_wrr_arb diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v new file mode 100644 index 0000000..bb2ba36 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v @@ -0,0 +1,2168 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_cvt.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_cvt ( + nvdla_core_clk + ,nvdla_core_rstn + ,dc2cvt_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,dc2cvt_dat_wr_sel +//: ,dc2cvt_dat_wr_addr +//: ,dc2cvt_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,dc2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,dc2cvt_dat_wr_addr${i} +//: ,dc2cvt_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,dc2cvt_dat_wr_addr +//: ,dc2cvt_dat_wr_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,dc2cvt_dat_wr_addr +,dc2cvt_dat_wr_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,dc2cvt_dat_wr_info_pd + ,img2cvt_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_sel +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,img2cvt_dat_wr_addr${i} +//: ,img2cvt_dat_wr_data${i} +//: ,img2cvt_mn_wr_data${i} +//: ,img2cvt_dat_wr_pad_mask${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,img2cvt_dat_wr_addr +,img2cvt_dat_wr_data +,img2cvt_mn_wr_data +,img2cvt_dat_wr_pad_mask + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// ,img2cvt_dat_wr_addr +// ,img2cvt_dat_wr_hsel +// ,img2cvt_dat_wr_data +// ,img2cvt_mn_wr_data + ,img2cvt_dat_wr_info_pd + ,cdma2buf_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,cdma2buf_dat_wr_sel +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_dat_wr_addr${i} +//: ,cdma2buf_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,cdma2buf_dat_wr_addr +,cdma2buf_dat_wr_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// ,cdma2buf_dat_wr_addr +// ,cdma2buf_dat_wr_hsel +// ,cdma2buf_dat_wr_data + ,nvdla_hls_clk + ,slcg_hls_en + ,nvdla_core_ng_clk + ,reg2dp_op_en + ,reg2dp_in_precision + ,reg2dp_proc_precision + ,reg2dp_cvt_en + ,reg2dp_cvt_truncate + ,reg2dp_cvt_offset + ,reg2dp_cvt_scale + ,reg2dp_nan_to_zero + ,reg2dp_pad_value + ,dp2reg_done +// ,img2cvt_dat_wr_pad_mask + ,dp2reg_nan_data_num + ,dp2reg_inf_data_num + ,dp2reg_dat_flush_done + ); +/////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dc2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: input [${k}-1:0] dc2cvt_dat_wr_sel; +//: input [16:0] dc2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: input [${k}-1:0] dc2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: input [16:0] dc2cvt_dat_wr_addr${i}; +//: input [${dmaif}-1:0] dc2cvt_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: input [16:0] dc2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [16:0] dc2cvt_dat_wr_addr; +input [64-1:0] dc2cvt_dat_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [11:0] dc2cvt_dat_wr_info_pd; +// input dc2cvt_dat_wr_en; +// input [11:0] dc2cvt_dat_wr_addr; +// input dc2cvt_dat_wr_hsel; +// input [64 -1:0] dc2cvt_dat_wr_data; +// input [11:0] dc2cvt_dat_wr_info_pd; +//////////////// img +input img2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: input [${k}-1:0] img2cvt_dat_wr_sel; +//: input [16:0] img2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] img2cvt_dat_wr_data; +//: input [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: input [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: input [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: input [16:0] img2cvt_dat_wr_addr${i}; +//: input [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: input [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: input [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: input [16:0] img2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] img2cvt_dat_wr_data; +//: input [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: input [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [16:0] img2cvt_dat_wr_addr; +input [64-1:0] img2cvt_dat_wr_data; +input [8*16-1:0] img2cvt_mn_wr_data; +input [8-1:0] img2cvt_dat_wr_pad_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [11:0] img2cvt_dat_wr_info_pd; +// input [11:0] img2cvt_dat_wr_addr; +// input img2cvt_dat_wr_hsel; +// //input [1023:0] img2cvt_dat_wr_data; +// input [64 -1:0] img2cvt_dat_wr_data; +// //input [127:0] img2cvt_dat_wr_pad_mask; +// //input [1023:0] img2cvt_mn_wr_data; +// //: my $dmaif = NVDLA_CDMA_DMAIF_BW; +// //: my $Bnum = $dmaif / NVDLA_BPE; +// //: print qq(input [$Bnum-1:0] img2cvt_dat_wr_pad_mask; ); +// input [64 -1:0] img2cvt_mn_wr_data; +output cdma2buf_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_sel; +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] cdma2buf_dat_wr_addr; +output [64-1:0] cdma2buf_dat_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// output cdma2buf_dat_wr_en; +// output [11:0] cdma2buf_dat_wr_addr; +// output [1:0] cdma2buf_dat_wr_hsel; +// //output [1023:0] cdma2buf_dat_wr_data; +// output [64 -1:0] cdma2buf_dat_wr_data; +input nvdla_hls_clk; +output slcg_hls_en; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_cvt_en; +input [5:0] reg2dp_cvt_truncate; +input [15:0] reg2dp_cvt_offset; +input [15:0] reg2dp_cvt_scale; +input [0:0] reg2dp_nan_to_zero; +input [15:0] reg2dp_pad_value; +input dp2reg_done; +output [31:0] dp2reg_nan_data_num; +output [31:0] dp2reg_inf_data_num; +output dp2reg_dat_flush_done; +/////////////////////////////////////////////////////////////////// +reg [5:0] cfg_cvt_en; +reg cfg_in_int8; +reg [1:0] cfg_in_precision; +reg [1:0] cfg_proc_precision; +reg [15:0] cfg_scale; +reg [5:0] cfg_truncate; +reg [15:0] cfg_offset; +reg cfg_out_int8; +reg [15:0] cfg_pad_value; +reg [16:0] cvt_out_addr_d1; +reg [16:0] cvt_out_addr_reg; +//: my $dmaif=64; +//: my $atmm=8; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmm_num= $Bnum / $atmm; +//: foreach my $k (0..$atmm_num -1) { +//: print qq(reg [${atmm}*${bpe}-1:0] cvt_out_data_p${k}_reg; \n); +//: print qq(wire [${atmm}*${bpe}-1:0] cvt_out_data_p${k}; \n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [8*8-1:0] cvt_out_data_p0_reg; +wire [8*8-1:0] cvt_out_data_p0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [3:0] cvt_out_nz_mask_d1; +reg cvt_out_pad_vld_d1; +reg cvt_out_vld_d1; +reg cvt_out_vld_reg; +reg [64 -1:0] cvt_wr_data_d1; +reg cvt_wr_en_d1; +reg cvt_wr_mean_d1; +reg [64/8*16-1:0] cvt_wr_mean_data_d1; +reg [17:0] dat_cbuf_flush_idx; +wire [31:0] dp2reg_inf_data_num; +wire [31:0] dp2reg_nan_data_num; +reg is_data_expand; +reg is_data_normal; +reg is_input_fp16; +reg [0:0] is_input_int8; +reg op_en; +reg op_en_d0; +reg cvt_wr_uint_d1; +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: foreach my $i (0..$Bnum -1) { +//: print qq( +//: reg [16:0] oprand_0_${i}_d0; +//: reg [15:0] oprand_1_${i}_d0; +//: wire [16:0] oprand_0_${i}_ori; +//: wire [15:0] oprand_1_${i}_ori; +//: wire [15:0] cellout_${i}; +//: ); +//: } +//: print qq( +//: wire [$Bnum-1:0] oprand_0_8b_sign; +//: wire [$Bnum-1:0] mon_cell_op0_ready; +//: wire [$Bnum-1:0] mon_cell_op1_ready; +//: wire [$Bnum-1:0] cvt_cell_en; +//: reg [$Bnum-1:0] cell_en_d0; +//: reg [$Bnum-1:0] cvt_cell_en_d1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [16:0] oprand_0_0_d0; +reg [15:0] oprand_1_0_d0; +wire [16:0] oprand_0_0_ori; +wire [15:0] oprand_1_0_ori; +wire [15:0] cellout_0; + +reg [16:0] oprand_0_1_d0; +reg [15:0] oprand_1_1_d0; +wire [16:0] oprand_0_1_ori; +wire [15:0] oprand_1_1_ori; +wire [15:0] cellout_1; + +reg [16:0] oprand_0_2_d0; +reg [15:0] oprand_1_2_d0; +wire [16:0] oprand_0_2_ori; +wire [15:0] oprand_1_2_ori; +wire [15:0] cellout_2; + +reg [16:0] oprand_0_3_d0; +reg [15:0] oprand_1_3_d0; +wire [16:0] oprand_0_3_ori; +wire [15:0] oprand_1_3_ori; +wire [15:0] cellout_3; + +reg [16:0] oprand_0_4_d0; +reg [15:0] oprand_1_4_d0; +wire [16:0] oprand_0_4_ori; +wire [15:0] oprand_1_4_ori; +wire [15:0] cellout_4; + +reg [16:0] oprand_0_5_d0; +reg [15:0] oprand_1_5_d0; +wire [16:0] oprand_0_5_ori; +wire [15:0] oprand_1_5_ori; +wire [15:0] cellout_5; + +reg [16:0] oprand_0_6_d0; +reg [15:0] oprand_1_6_d0; +wire [16:0] oprand_0_6_ori; +wire [15:0] oprand_1_6_ori; +wire [15:0] cellout_6; + +reg [16:0] oprand_0_7_d0; +reg [15:0] oprand_1_7_d0; +wire [16:0] oprand_0_7_ori; +wire [15:0] oprand_1_7_ori; +wire [15:0] cellout_7; + +wire [8-1:0] oprand_0_8b_sign; +wire [8-1:0] mon_cell_op0_ready; +wire [8-1:0] mon_cell_op1_ready; +wire [8-1:0] cvt_cell_en; +reg [8-1:0] cell_en_d0; +reg [8-1:0] cvt_cell_en_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg slcg_hls_en_d1; +reg slcg_hls_en_d2; +reg slcg_hls_en_d3; +wire [15:0] cfg_pad_value_w; +wire cfg_reg_en; +wire [64 -1:0] cvt_data_cell; +wire [16:0] cvt_out_addr; +wire [16:0] cvt_out_addr_bp; +wire [16:0] cvt_out_addr_reg_w; +wire [64 -1:0] cvt_out_data_masked; +wire [64 -1:0] cvt_out_data_mix; +wire [3:0] cvt_out_nz_mask_bp; +wire cvt_out_pad_vld_bp; +wire cvt_out_vld; +wire cvt_out_vld_bp; +wire cvt_out_vld_reg_w; +wire [16:0] cvt_wr_addr; +wire [64 -1:0] cvt_wr_data; +wire cvt_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: my $s = int($atmc/$dmaif); +//: print qq( +//: wire [${k}-1:0] cvt_wr_sel; +//: wire [${k}-1:0] cvt_out_sel; +//: reg [${k}-1:0] cvt_out_sel_d1; +//: wire [${k}-1:0] cvt_out_sel_bp; +//: reg [${s}-1:0] cvt_out_sel_reg; +//: wire [${k}-1:0] cvt_out_reg_en; +//: reg [${k}-1:0] cvt_out_reg_en_d1; +//: wire [${k}-1:0] cvt_out_reg_en_bp; +//: ); +//: } else { +//: print qq( +//: wire cvt_out_reg_en; +//: reg cvt_out_reg_en_d1; +//: wire cvt_out_reg_en_bp; +//: ); +//: } +//: print qq( +//: wire [${Bnum}-1:0] cvt_wr_pad_mask; +//: reg [${Bnum}-1:0] cvt_out_pad_mask_d1; +//: wire [${Bnum}-1:0] cvt_out_pad_mask_bp; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire cvt_out_reg_en; +reg cvt_out_reg_en_d1; +wire cvt_out_reg_en_bp; + +wire [8-1:0] cvt_wr_pad_mask; +reg [8-1:0] cvt_out_pad_mask_d1; +wire [8-1:0] cvt_out_pad_mask_bp; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [11:0] cvt_wr_info_pd; +wire [3:0] cvt_wr_mask; +wire cvt_wr_mean; +wire [64/8*16-1:0] cvt_wr_mean_data; +wire [2:0] cvt_wr_sub_h; +wire cvt_wr_uint; +wire [17:0] dat_cbuf_flush_idx_w; +wire dat_cbuf_flush_vld_w; +wire [31:0] dat_half_mask; +wire [64 -1:0] dat_nan_mask; +wire is_data_expand_w; +wire is_data_normal_w; +wire is_input_fp16_w; +wire is_input_int8_w; +wire is_output_int8_w; +wire mon_dat_cbuf_flush_idx_w; +wire nan_carry; +wire nan_reg_en; +wire op_en_w; +wire slcg_hls_en_w; +/////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// prepare input signals // +//////////////////////////////////////////////////////////////////////// +assign op_en_w = ~dp2reg_done & reg2dp_op_en; +assign cfg_reg_en = op_en_w & ~op_en; +assign is_input_int8_w = 1'b1; +assign is_input_fp16_w = 1'b0; +assign is_output_int8_w = 1'b1; +assign is_data_expand_w = is_input_int8_w & ~is_output_int8_w; +assign is_data_normal_w = is_input_int8_w ~^ is_output_int8_w; +//assign nan_pass_w = ~reg2dp_nan_to_zero | ~is_input_fp16_w; +//assign cfg_pad_value_w = is_output_int8_w ? {2{reg2dp_pad_value[7:0]}} : reg2dp_pad_value; +assign cfg_pad_value_w = reg2dp_pad_value; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"op_en_w\" -q op_en"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_in_precision\" -q cfg_in_precision"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_proc_precision\" -q cfg_proc_precision"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_cvt_scale\" -q cfg_scale"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_cvt_truncate\" -q cfg_truncate"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_cvt_offset\" -q cfg_offset"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"cfg_reg_en\" -d \"{6{reg2dp_cvt_en}}\" -q cfg_cvt_en"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_input_int8_w\" -q cfg_in_int8"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_output_int8_w\" -q cfg_out_int8"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"cfg_reg_en\" -d \"cfg_pad_value_w\" -q cfg_pad_value"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_input_int8_w\" -q is_input_int8"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_input_fp16_w\" -q is_input_fp16"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_data_expand_w\" -q is_data_expand"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_data_normal_w\" -q is_data_normal"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en <= 1'b0; + end else begin + op_en <= op_en_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_in_precision <= {2{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_in_precision <= reg2dp_in_precision; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_in_precision <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_proc_precision <= {2{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_proc_precision <= reg2dp_proc_precision; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_proc_precision <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_scale <= {16{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_scale <= reg2dp_cvt_scale; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_scale <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_truncate <= {6{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_truncate <= reg2dp_cvt_truncate; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_truncate <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_offset <= {16{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_offset <= reg2dp_cvt_offset; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_cvt_en <= {6{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_cvt_en <= {6{reg2dp_cvt_en}}; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_cvt_en <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_in_int8 <= 1'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_in_int8 <= is_input_int8_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_in_int8 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_out_int8 <= 1'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_out_int8 <= is_output_int8_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_out_int8 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_pad_value <= {16{1'b0}}; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_pad_value <= cfg_pad_value_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_pad_value <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_input_int8 <= 1'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + is_input_int8 <= is_input_int8_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + is_input_int8 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_input_fp16 <= 1'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + is_input_fp16 <= is_input_fp16_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + is_input_fp16 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_data_expand <= 1'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + is_data_expand <= is_data_expand_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + is_data_expand <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_data_normal <= 1'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + is_data_normal <= is_data_normal_w; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + is_data_normal <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// //: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"cfg_reg_en\" -d \"nan_pass_w\" -q nan_pass"); +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_hls_en_w = reg2dp_op_en & reg2dp_cvt_en; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_hls_en_w\" -q slcg_hls_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_hls_en_d1\" -q slcg_hls_en_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_hls_en_d2\" -q slcg_hls_en_d3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_hls_en_d1 <= 1'b0; + end else begin + slcg_hls_en_d1 <= slcg_hls_en_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_hls_en_d2 <= 1'b0; + end else begin + slcg_hls_en_d2 <= slcg_hls_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_hls_en_d3 <= 1'b0; + end else begin + slcg_hls_en_d3 <= slcg_hls_en_d2; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign slcg_hls_en = slcg_hls_en_d3; +//////////////////////////////////////////////////////////////////////// +// Input signals // +//////////////////////////////////////////////////////////////////////// +assign cvt_wr_info_pd = ({12 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_info_pd) + | ({12 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_info_pd); +assign cvt_wr_mask[3:0] = cvt_wr_info_pd[3:0]; +//assign cvt_wr_interleave = cvt_wr_info_pd[4]; +//assign cvt_wr_ext64 = cvt_wr_info_pd[5]; +//assign cvt_wr_ext128 = cvt_wr_info_pd[6]; +assign cvt_wr_mean = cvt_wr_info_pd[7]; +assign cvt_wr_uint = cvt_wr_info_pd[8]; +assign cvt_wr_sub_h[2:0] = cvt_wr_info_pd[11:9]; +assign cvt_wr_en = (dc2cvt_dat_wr_en | img2cvt_dat_wr_en); +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: assign cvt_wr_pad_mask = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask : ${Bnum}'d0; +//: assign cvt_wr_sel = dc2cvt_dat_wr_en ? dc2cvt_dat_wr_sel +//: : img2cvt_dat_wr_en ? img2cvt_dat_wr_sel : 0; +//: assign cvt_wr_addr = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr) +//: | ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr); +//: assign cvt_wr_data = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data) +//: | ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data); +//: assign cvt_wr_mean_data = img2cvt_mn_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: assign cvt_dat_wr_mask = (dc2cvt_dat_wr_en & dc2cvt_dat_wr_mask) +//: | (img2cvt_dat_wr_en & img2cvt_dat_wr_mask); +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign cvt_wr_pad_mask${i} = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask${i} : ${Bnum}'d0; +//: assign cvt_wr_addr${i} = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr${i}) +//: | ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr${i}); +//: assign cvt_wr_data${i} = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data${i}) +//: | ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data${i}); +//: assign cvt_wr_mean_data${i} = img2cvt_mn_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: assign cvt_wr_pad_mask = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask : ${Bnum}'d0; +//: assign cvt_wr_addr = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr) +//: | ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr); +//: assign cvt_wr_data = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data) +//: | ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data); +//: assign cvt_wr_mean_data = img2cvt_mn_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cvt_wr_pad_mask = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask : 8'd0; +assign cvt_wr_addr = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr) +| ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr); +assign cvt_wr_data = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data) +| ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data); +assign cvt_wr_mean_data = img2cvt_mn_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// generator mux control signals // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: assign cvt_out_sel = cvt_wr_sel; +//: assign cvt_out_reg_en = cvt_wr_en ? cvt_out_sel : 0; +//: ); +//: } else { +//: print qq( +//: //assign cvt_out_reg_en = cvt_wr_en; +//: assign cvt_out_reg_en = 1'b0; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//assign cvt_out_reg_en = cvt_wr_en; +assign cvt_out_reg_en = 1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvt_out_addr = cvt_wr_addr; +assign cvt_out_vld = cvt_wr_en; +//: my $dmaif=64; +//: my $atmm=8; +//: my $Bnum = $dmaif / 8; +//: my $atmm_num = $Bnum / $atmm; +//: if($atmm_num == 1) { +//: print qq( +//: assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {${atmm}{cvt_wr_mask[0]}} : ${Bnum}'b0; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {{${atmm}{cvt_wr_mask[1]}},{${atmm}{cvt_wr_mask[0]}}} : ${Bnum}'b0; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {{${atmm}{cvt_wr_mask[3]}},{${atmm}{cvt_wr_mask[2]}},{${atmm}{cvt_wr_mask[1]}},{${atmm}{cvt_wr_mask[0]}}} : ${Bnum}'b0; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {8{cvt_wr_mask[0]}} : 8'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign cvt_out_reg_en = cvt_wr_en ? {{4{cvt_out_sel[1]}}, {4{cvt_out_sel[0]}}} : 8'b0; +//////////////////////////////////////////////////////////////////////// +// One pipeline stage for retiming // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_wr_en\" -q cvt_wr_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cvt_wr_en\" -d \"cvt_wr_mean\" -q cvt_wr_mean_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cvt_wr_en\" -d \"cvt_wr_uint\" -q cvt_wr_uint_d1"); +//: &eperl::flop("-nodeclare -norst -en \"cvt_wr_en & cvt_wr_mean\" -d \"cvt_wr_mean_data\" -q cvt_wr_mean_data_d1"); +//: &eperl::flop("-nodeclare -norst -en \"cvt_wr_en\" -d \"cvt_wr_data\" -q cvt_wr_data_d1"); +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: &eperl::flop("-nodeclare -rval \"${Bnum}'b0\" -en \"cvt_wr_en | cvt_wr_en_d1\" -d \"cvt_cell_en\" -q cvt_cell_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_out_vld\" -q cvt_out_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"img2cvt_dat_wr_en\" -q cvt_out_pad_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"{17{1'b0}}\" -en \"cvt_wr_en\" -d \"cvt_out_addr\" -q cvt_out_addr_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"cvt_wr_en\" -d \"cvt_wr_mask\" -q cvt_out_nz_mask_d1"); +//: &eperl::flop("-nodeclare -rval \"${Bnum}'b0\" -en \"img2cvt_dat_wr_en\" -d \"cvt_wr_pad_mask\" -q cvt_out_pad_mask_d1"); +//: my $atmc=8*8; +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: if($dmaif < $atmc) { +//: &eperl::flop("-nodeclare -rval \"${k}'b0\" -d \"cvt_out_reg_en\" -q cvt_out_reg_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"cvt_wr_en\" -d \"cvt_out_sel\" -q cvt_out_sel_d1"); +//: } else { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_out_reg_en\" -q cvt_out_reg_en_d1"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_wr_en_d1 <= 1'b0; + end else begin + cvt_wr_en_d1 <= cvt_wr_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_wr_mean_d1 <= 1'b0; + end else begin + if ((cvt_wr_en) == 1'b1) begin + cvt_wr_mean_d1 <= cvt_wr_mean; + // VCS coverage off + end else if ((cvt_wr_en) == 1'b0) begin + end else begin + cvt_wr_mean_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_wr_uint_d1 <= 1'b0; + end else begin + if ((cvt_wr_en) == 1'b1) begin + cvt_wr_uint_d1 <= cvt_wr_uint; + // VCS coverage off + end else if ((cvt_wr_en) == 1'b0) begin + end else begin + cvt_wr_uint_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_wr_en & cvt_wr_mean) == 1'b1) begin + cvt_wr_mean_data_d1 <= cvt_wr_mean_data; + // VCS coverage off + end else if ((cvt_wr_en & cvt_wr_mean) == 1'b0) begin + end else begin + cvt_wr_mean_data_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_wr_en) == 1'b1) begin + cvt_wr_data_d1 <= cvt_wr_data; + // VCS coverage off + end else if ((cvt_wr_en) == 1'b0) begin + end else begin + cvt_wr_data_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_cell_en_d1 <= 8'b0; + end else begin + if ((cvt_wr_en | cvt_wr_en_d1) == 1'b1) begin + cvt_cell_en_d1 <= cvt_cell_en; + // VCS coverage off + end else if ((cvt_wr_en | cvt_wr_en_d1) == 1'b0) begin + end else begin + cvt_cell_en_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_vld_d1 <= 1'b0; + end else begin + cvt_out_vld_d1 <= cvt_out_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_vld_d1 <= 1'b0; + end else begin + cvt_out_pad_vld_d1 <= img2cvt_dat_wr_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_addr_d1 <= {17{1'b0}}; + end else begin + if ((cvt_wr_en) == 1'b1) begin + cvt_out_addr_d1 <= cvt_out_addr; + // VCS coverage off + end else if ((cvt_wr_en) == 1'b0) begin + end else begin + cvt_out_addr_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_nz_mask_d1 <= {4{1'b0}}; + end else begin + if ((cvt_wr_en) == 1'b1) begin + cvt_out_nz_mask_d1 <= cvt_wr_mask; + // VCS coverage off + end else if ((cvt_wr_en) == 1'b0) begin + end else begin + cvt_out_nz_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_mask_d1 <= 8'b0; + end else begin + if ((img2cvt_dat_wr_en) == 1'b1) begin + cvt_out_pad_mask_d1 <= cvt_wr_pad_mask; + // VCS coverage off + end else if ((img2cvt_dat_wr_en) == 1'b0) begin + end else begin + cvt_out_pad_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_reg_en_d1 <= 1'b0; + end else begin + cvt_out_reg_en_d1 <= cvt_out_reg_en; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// generate input signals for convertor cells // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: foreach my $i(0..$Bnum-1) { +//: my $j = $i + 1; +//: print qq ( +//: assign oprand_0_8b_sign[${i}] = (cvt_wr_data_d1[${j}*${bpe}-1] & ~cvt_wr_uint_d1); +//: assign oprand_0_${i}_ori = {{(17-${bpe}){oprand_0_8b_sign[${i}]}}, cvt_wr_data_d1[${j}*${bpe}-1:${i}*${bpe}]} ; +//: assign oprand_1_${i}_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[${j}*16-1:${i}*16] : cfg_offset[15:0]; +//: ); +//: &eperl::flop("-nodeclare -norst -en \"cvt_cell_en_d1[${i}]\" -d \"oprand_0_${i}_ori\" -q oprand_0_${i}_d0"); +//: &eperl::flop("-nodeclare -norst -en \"cvt_cell_en_d1[${i}]\" -d \"oprand_1_${i}_ori\" -q oprand_1_${i}_d0"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign oprand_0_8b_sign[0] = (cvt_wr_data_d1[1*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_0_ori = {{(17-8){oprand_0_8b_sign[0]}}, cvt_wr_data_d1[1*8-1:0*8]} ; +assign oprand_1_0_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[1*16-1:0*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[0]) == 1'b1) begin + oprand_0_0_d0 <= oprand_0_0_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[0]) == 1'b0) begin + end else begin + oprand_0_0_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[0]) == 1'b1) begin + oprand_1_0_d0 <= oprand_1_0_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[0]) == 1'b0) begin + end else begin + oprand_1_0_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[1] = (cvt_wr_data_d1[2*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_1_ori = {{(17-8){oprand_0_8b_sign[1]}}, cvt_wr_data_d1[2*8-1:1*8]} ; +assign oprand_1_1_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[2*16-1:1*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[1]) == 1'b1) begin + oprand_0_1_d0 <= oprand_0_1_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[1]) == 1'b0) begin + end else begin + oprand_0_1_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[1]) == 1'b1) begin + oprand_1_1_d0 <= oprand_1_1_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[1]) == 1'b0) begin + end else begin + oprand_1_1_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[2] = (cvt_wr_data_d1[3*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_2_ori = {{(17-8){oprand_0_8b_sign[2]}}, cvt_wr_data_d1[3*8-1:2*8]} ; +assign oprand_1_2_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[3*16-1:2*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[2]) == 1'b1) begin + oprand_0_2_d0 <= oprand_0_2_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[2]) == 1'b0) begin + end else begin + oprand_0_2_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[2]) == 1'b1) begin + oprand_1_2_d0 <= oprand_1_2_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[2]) == 1'b0) begin + end else begin + oprand_1_2_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[3] = (cvt_wr_data_d1[4*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_3_ori = {{(17-8){oprand_0_8b_sign[3]}}, cvt_wr_data_d1[4*8-1:3*8]} ; +assign oprand_1_3_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[4*16-1:3*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[3]) == 1'b1) begin + oprand_0_3_d0 <= oprand_0_3_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[3]) == 1'b0) begin + end else begin + oprand_0_3_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[3]) == 1'b1) begin + oprand_1_3_d0 <= oprand_1_3_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[3]) == 1'b0) begin + end else begin + oprand_1_3_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[4] = (cvt_wr_data_d1[5*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_4_ori = {{(17-8){oprand_0_8b_sign[4]}}, cvt_wr_data_d1[5*8-1:4*8]} ; +assign oprand_1_4_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[5*16-1:4*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[4]) == 1'b1) begin + oprand_0_4_d0 <= oprand_0_4_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[4]) == 1'b0) begin + end else begin + oprand_0_4_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[4]) == 1'b1) begin + oprand_1_4_d0 <= oprand_1_4_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[4]) == 1'b0) begin + end else begin + oprand_1_4_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[5] = (cvt_wr_data_d1[6*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_5_ori = {{(17-8){oprand_0_8b_sign[5]}}, cvt_wr_data_d1[6*8-1:5*8]} ; +assign oprand_1_5_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[6*16-1:5*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[5]) == 1'b1) begin + oprand_0_5_d0 <= oprand_0_5_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[5]) == 1'b0) begin + end else begin + oprand_0_5_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[5]) == 1'b1) begin + oprand_1_5_d0 <= oprand_1_5_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[5]) == 1'b0) begin + end else begin + oprand_1_5_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[6] = (cvt_wr_data_d1[7*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_6_ori = {{(17-8){oprand_0_8b_sign[6]}}, cvt_wr_data_d1[7*8-1:6*8]} ; +assign oprand_1_6_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[7*16-1:6*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[6]) == 1'b1) begin + oprand_0_6_d0 <= oprand_0_6_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[6]) == 1'b0) begin + end else begin + oprand_0_6_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[6]) == 1'b1) begin + oprand_1_6_d0 <= oprand_1_6_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[6]) == 1'b0) begin + end else begin + oprand_1_6_d0 <= 'bx; + // VCS coverage on + end +end + +assign oprand_0_8b_sign[7] = (cvt_wr_data_d1[8*8-1] & ~cvt_wr_uint_d1); +assign oprand_0_7_ori = {{(17-8){oprand_0_8b_sign[7]}}, cvt_wr_data_d1[8*8-1:7*8]} ; +assign oprand_1_7_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[8*16-1:7*16] : cfg_offset[15:0]; +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[7]) == 1'b1) begin + oprand_0_7_d0 <= oprand_0_7_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[7]) == 1'b0) begin + end else begin + oprand_0_7_d0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((cvt_cell_en_d1[7]) == 1'b1) begin + oprand_1_7_d0 <= oprand_1_7_ori; + // VCS coverage off + end else if ((cvt_cell_en_d1[7]) == 1'b0) begin + end else begin + oprand_1_7_d0 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = ($dmaif / $bpe); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_wr_en_d1\" -q op_en_d0"); +//: &eperl::flop("-nodeclare -rval \"${Bnum}'b0\" -en \"cvt_wr_en_d1 | op_en_d0\" -d \"cvt_cell_en_d1\" -q cell_en_d0 "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d0 <= 1'b0; + end else begin + op_en_d0 <= cvt_wr_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cell_en_d0 <= 8'b0; + end else begin + if ((cvt_wr_en_d1 | op_en_d0) == 1'b1) begin + cell_en_d0 <= cvt_cell_en_d1; + // VCS coverage off + end else if ((cvt_wr_en_d1 | op_en_d0) == 1'b0) begin + end else begin + cell_en_d0 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// instance of convert cells // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: foreach my $i (0..$Bnum-1) { +//: print qq ( +//: NV_NVDLA_CDMA_CVT_cell u_cell_${i} ( +//: .nvdla_core_clk (nvdla_hls_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.chn_data_in_rsc_z (oprand_0_${i}_d0[16:0]) +//: ,.chn_data_in_rsc_vz (cell_en_d0[${i}]) +//: // spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.chn_data_in_rsc_lz (mon_cell_op0_ready[${i}]) +//: // spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.chn_alu_in_rsc_z (oprand_1_${i}_d0[15:0]) +//: ,.chn_alu_in_rsc_vz (cell_en_d0[${i}]) +//: // spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.chn_alu_in_rsc_lz (mon_cell_op1_ready[${i}]) +//: // spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +//: ,.cfg_in_precision (cfg_in_precision[1:0]) +//: ,.cfg_out_precision (cfg_proc_precision[1:0]) +//: ,.cfg_truncate (cfg_truncate[5:0]) +//: ,.chn_data_out_rsc_z (cellout_${i}[15:0]) +//: ,.chn_data_out_rsc_vz (1'b1) +//: ,.chn_data_out_rsc_lz ( ) +//: );\n); +//: } +//: print "\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +NV_NVDLA_CDMA_CVT_cell u_cell_0 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_0_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[0]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[0]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_0_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[0]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[0]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_0[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_1 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_1_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[1]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[1]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_1_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[1]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[1]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_1[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_2 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_2_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[2]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[2]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_2_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[2]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[2]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_2[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_3 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_3_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[3]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[3]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_3_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[3]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[3]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_3[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_4 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_4_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[4]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[4]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_4_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[4]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[4]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_4[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_5 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_5_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[5]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[5]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_5_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[5]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[5]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_5[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_6 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_6_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[6]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[6]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_6_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[6]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[6]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_6[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + +NV_NVDLA_CDMA_CVT_cell u_cell_7 ( +.nvdla_core_clk (nvdla_hls_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (oprand_0_7_d0[16:0]) +,.chn_data_in_rsc_vz (cell_en_d0[7]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_data_in_rsc_lz (mon_cell_op0_ready[7]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_z (oprand_1_7_d0[15:0]) +,.chn_alu_in_rsc_vz (cell_en_d0[7]) +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.chn_alu_in_rsc_lz (mon_cell_op1_ready[7]) +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +,.cfg_in_precision (cfg_in_precision[1:0]) +,.cfg_out_precision (cfg_proc_precision[1:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.chn_data_out_rsc_z (cellout_7[15:0]) +,.chn_data_out_rsc_vz (1'b1) +,.chn_data_out_rsc_lz ( ) +); + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvt_data_cell = { +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: if($Bnum > 1) { +//: foreach my $i(0..$Bnum-2){ +//: my $j = $Bnum - $i -1; +//: print qq(cellout_${j}[${bpe}-1:0], ); +//: } +//: } +//: print qq(cellout_0[${bpe}-1:0]}; \n); +//| eperl: generated_beg (DO NOT EDIT BELOW) +cellout_7[8-1:0], cellout_6[8-1:0], cellout_5[8-1:0], cellout_4[8-1:0], cellout_3[8-1:0], cellout_2[8-1:0], cellout_1[8-1:0], cellout_0[8-1:0]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// stage 2: pipeline to match latency of conver cells // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: for(my $i = 1; $i <= 3 +1; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"cvt_out_vld_d${i}\" -q cvt_out_vld_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"cvt_out_pad_vld_d${i}\" -q cvt_out_pad_vld_d${j}"); +//: if($dmaif < $atmc) { +//: &eperl::flop("-wid $k -rval \"{${k}{1'b0}}\" -en \"cvt_out_vld_d${i}\" -d \"cvt_out_sel_d${i}\" -q cvt_out_sel_d${j}"); +//: &eperl::flop("-wid $k -rval \"{${k}{1'b0}}\" -en \"cvt_out_vld_d${i} | cvt_out_vld_d2\" -d \"cvt_out_reg_en_d${i}\" -q cvt_out_reg_en_d${j}"); +//: } else { +//: &eperl::flop("-wid $k -rval \"1'b0\" -en \"cvt_out_vld_d${i} | cvt_out_vld_d2\" -d \"cvt_out_reg_en_d${i}\" -q cvt_out_reg_en_d${j}"); +//: } +//: &eperl::flop("-wid 17 -rval \"{17{1'b0}}\" -en \"cvt_out_vld_d${i}\" -d \"cvt_out_addr_d${i}\" -q cvt_out_addr_d${j}"); +//: &eperl::flop("-wid 4 -rval \"{4{1'b0}}\" -en \"cvt_out_vld_d${i}\" -d \"cvt_out_nz_mask_d${i}\" -q cvt_out_nz_mask_d${j}"); +//: &eperl::flop("-wid $Bnum -rval \"{${Bnum}{1'b0}}\" -en \"cvt_out_pad_vld_d${i}\" -d \"cvt_out_pad_mask_d${i}\" -q cvt_out_pad_mask_d${j}"); +//: print "\n\n"; +//: } +//: my $i = 3 +2; +//: if($dmaif < $atmc){ +//: print qq( +//: assign cvt_out_sel_bp = cfg_cvt_en[1] ? cvt_out_sel_d${i} : cvt_out_sel_d1; +//: ); +//: } +//: print qq( +//: assign cvt_out_vld_bp = cfg_cvt_en[1] ? cvt_out_vld_d${i} : cvt_out_vld_d1; +//: assign cvt_out_addr_bp = cfg_cvt_en[1] ? cvt_out_addr_d${i} : cvt_out_addr_d1; +//: assign cvt_out_nz_mask_bp = cfg_cvt_en[2] ? cvt_out_nz_mask_d${i} : cvt_out_nz_mask_d1; +//: assign cvt_out_pad_vld_bp = cfg_cvt_en[3] ? cvt_out_pad_vld_d${i} : cvt_out_pad_vld_d1; +//: assign cvt_out_pad_mask_bp = ~cvt_out_pad_vld_bp ? ${Bnum}'b0 : (cfg_cvt_en[3] ? cvt_out_pad_mask_d${i} : cvt_out_pad_mask_d1); +//: assign cvt_out_reg_en_bp = cfg_cvt_en[4] ? cvt_out_reg_en_d${i} : cvt_out_reg_en_d1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg cvt_out_vld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_vld_d2 <= 1'b0; + end else begin + cvt_out_vld_d2 <= cvt_out_vld_d1; + end +end +reg cvt_out_pad_vld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_vld_d2 <= 1'b0; + end else begin + cvt_out_pad_vld_d2 <= cvt_out_pad_vld_d1; + end +end +reg cvt_out_reg_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_reg_en_d2 <= 1'b0; + end else begin + if ((cvt_out_vld_d1 | cvt_out_vld_d2) == 1'b1) begin + cvt_out_reg_en_d2 <= cvt_out_reg_en_d1; + // VCS coverage off + end else if ((cvt_out_vld_d1 | cvt_out_vld_d2) == 1'b0) begin + end else begin + cvt_out_reg_en_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [16:0] cvt_out_addr_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_addr_d2 <= {17{1'b0}}; + end else begin + if ((cvt_out_vld_d1) == 1'b1) begin + cvt_out_addr_d2 <= cvt_out_addr_d1; + // VCS coverage off + end else if ((cvt_out_vld_d1) == 1'b0) begin + end else begin + cvt_out_addr_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] cvt_out_nz_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_nz_mask_d2 <= {4{1'b0}}; + end else begin + if ((cvt_out_vld_d1) == 1'b1) begin + cvt_out_nz_mask_d2 <= cvt_out_nz_mask_d1; + // VCS coverage off + end else if ((cvt_out_vld_d1) == 1'b0) begin + end else begin + cvt_out_nz_mask_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] cvt_out_pad_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_mask_d2 <= {8{1'b0}}; + end else begin + if ((cvt_out_pad_vld_d1) == 1'b1) begin + cvt_out_pad_mask_d2 <= cvt_out_pad_mask_d1; + // VCS coverage off + end else if ((cvt_out_pad_vld_d1) == 1'b0) begin + end else begin + cvt_out_pad_mask_d2 <= 'bx; + // VCS coverage on + end + end +end + + +reg cvt_out_vld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_vld_d3 <= 1'b0; + end else begin + cvt_out_vld_d3 <= cvt_out_vld_d2; + end +end +reg cvt_out_pad_vld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_vld_d3 <= 1'b0; + end else begin + cvt_out_pad_vld_d3 <= cvt_out_pad_vld_d2; + end +end +reg cvt_out_reg_en_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_reg_en_d3 <= 1'b0; + end else begin + if ((cvt_out_vld_d2 | cvt_out_vld_d2) == 1'b1) begin + cvt_out_reg_en_d3 <= cvt_out_reg_en_d2; + // VCS coverage off + end else if ((cvt_out_vld_d2 | cvt_out_vld_d2) == 1'b0) begin + end else begin + cvt_out_reg_en_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [16:0] cvt_out_addr_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_addr_d3 <= {17{1'b0}}; + end else begin + if ((cvt_out_vld_d2) == 1'b1) begin + cvt_out_addr_d3 <= cvt_out_addr_d2; + // VCS coverage off + end else if ((cvt_out_vld_d2) == 1'b0) begin + end else begin + cvt_out_addr_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] cvt_out_nz_mask_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_nz_mask_d3 <= {4{1'b0}}; + end else begin + if ((cvt_out_vld_d2) == 1'b1) begin + cvt_out_nz_mask_d3 <= cvt_out_nz_mask_d2; + // VCS coverage off + end else if ((cvt_out_vld_d2) == 1'b0) begin + end else begin + cvt_out_nz_mask_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] cvt_out_pad_mask_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_mask_d3 <= {8{1'b0}}; + end else begin + if ((cvt_out_pad_vld_d2) == 1'b1) begin + cvt_out_pad_mask_d3 <= cvt_out_pad_mask_d2; + // VCS coverage off + end else if ((cvt_out_pad_vld_d2) == 1'b0) begin + end else begin + cvt_out_pad_mask_d3 <= 'bx; + // VCS coverage on + end + end +end + + +reg cvt_out_vld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_vld_d4 <= 1'b0; + end else begin + cvt_out_vld_d4 <= cvt_out_vld_d3; + end +end +reg cvt_out_pad_vld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_vld_d4 <= 1'b0; + end else begin + cvt_out_pad_vld_d4 <= cvt_out_pad_vld_d3; + end +end +reg cvt_out_reg_en_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_reg_en_d4 <= 1'b0; + end else begin + if ((cvt_out_vld_d3 | cvt_out_vld_d2) == 1'b1) begin + cvt_out_reg_en_d4 <= cvt_out_reg_en_d3; + // VCS coverage off + end else if ((cvt_out_vld_d3 | cvt_out_vld_d2) == 1'b0) begin + end else begin + cvt_out_reg_en_d4 <= 'bx; + // VCS coverage on + end + end +end +reg [16:0] cvt_out_addr_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_addr_d4 <= {17{1'b0}}; + end else begin + if ((cvt_out_vld_d3) == 1'b1) begin + cvt_out_addr_d4 <= cvt_out_addr_d3; + // VCS coverage off + end else if ((cvt_out_vld_d3) == 1'b0) begin + end else begin + cvt_out_addr_d4 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] cvt_out_nz_mask_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_nz_mask_d4 <= {4{1'b0}}; + end else begin + if ((cvt_out_vld_d3) == 1'b1) begin + cvt_out_nz_mask_d4 <= cvt_out_nz_mask_d3; + // VCS coverage off + end else if ((cvt_out_vld_d3) == 1'b0) begin + end else begin + cvt_out_nz_mask_d4 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] cvt_out_pad_mask_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_mask_d4 <= {8{1'b0}}; + end else begin + if ((cvt_out_pad_vld_d3) == 1'b1) begin + cvt_out_pad_mask_d4 <= cvt_out_pad_mask_d3; + // VCS coverage off + end else if ((cvt_out_pad_vld_d3) == 1'b0) begin + end else begin + cvt_out_pad_mask_d4 <= 'bx; + // VCS coverage on + end + end +end + + +reg cvt_out_vld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_vld_d5 <= 1'b0; + end else begin + cvt_out_vld_d5 <= cvt_out_vld_d4; + end +end +reg cvt_out_pad_vld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_vld_d5 <= 1'b0; + end else begin + cvt_out_pad_vld_d5 <= cvt_out_pad_vld_d4; + end +end +reg cvt_out_reg_en_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_reg_en_d5 <= 1'b0; + end else begin + if ((cvt_out_vld_d4 | cvt_out_vld_d2) == 1'b1) begin + cvt_out_reg_en_d5 <= cvt_out_reg_en_d4; + // VCS coverage off + end else if ((cvt_out_vld_d4 | cvt_out_vld_d2) == 1'b0) begin + end else begin + cvt_out_reg_en_d5 <= 'bx; + // VCS coverage on + end + end +end +reg [16:0] cvt_out_addr_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_addr_d5 <= {17{1'b0}}; + end else begin + if ((cvt_out_vld_d4) == 1'b1) begin + cvt_out_addr_d5 <= cvt_out_addr_d4; + // VCS coverage off + end else if ((cvt_out_vld_d4) == 1'b0) begin + end else begin + cvt_out_addr_d5 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] cvt_out_nz_mask_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_nz_mask_d5 <= {4{1'b0}}; + end else begin + if ((cvt_out_vld_d4) == 1'b1) begin + cvt_out_nz_mask_d5 <= cvt_out_nz_mask_d4; + // VCS coverage off + end else if ((cvt_out_vld_d4) == 1'b0) begin + end else begin + cvt_out_nz_mask_d5 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] cvt_out_pad_mask_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_pad_mask_d5 <= {8{1'b0}}; + end else begin + if ((cvt_out_pad_vld_d4) == 1'b1) begin + cvt_out_pad_mask_d5 <= cvt_out_pad_mask_d4; + // VCS coverage off + end else if ((cvt_out_pad_vld_d4) == 1'b0) begin + end else begin + cvt_out_pad_mask_d5 <= 'bx; + // VCS coverage on + end + end +end + + + +assign cvt_out_vld_bp = cfg_cvt_en[1] ? cvt_out_vld_d5 : cvt_out_vld_d1; +assign cvt_out_addr_bp = cfg_cvt_en[1] ? cvt_out_addr_d5 : cvt_out_addr_d1; +assign cvt_out_nz_mask_bp = cfg_cvt_en[2] ? cvt_out_nz_mask_d5 : cvt_out_nz_mask_d1; +assign cvt_out_pad_vld_bp = cfg_cvt_en[3] ? cvt_out_pad_vld_d5 : cvt_out_pad_vld_d1; +assign cvt_out_pad_mask_bp = ~cvt_out_pad_vld_bp ? 8'b0 : (cfg_cvt_en[3] ? cvt_out_pad_mask_d5 : cvt_out_pad_mask_d1); +assign cvt_out_reg_en_bp = cfg_cvt_en[4] ? cvt_out_reg_en_d5 : cvt_out_reg_en_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// stage 3: final pipeline stage // +//////////////////////////////////////////////////////////////////////// +assign cvt_out_data_mix = cfg_cvt_en[5] ? cvt_data_cell : cvt_wr_data_d1; +//: my $dmaif=64; +//: my $atmm=8; +//: my $bpe = 8; +//: my $atmmbw= $atmm * $bpe; +//: my $Bnum = $dmaif / $bpe; +//: my $atmm_num= $Bnum / $atmm; +//: for(my $i = 0; $i < $Bnum; $i ++) { +//: my $b0 = $i * $bpe; +//: my $b1 = ($i + 1) * $bpe - 1; +//: print "assign cvt_out_data_masked[${b1}:${b0}] = cvt_out_pad_mask_bp[${i}] ? cfg_pad_value[${bpe}-1:0] : cvt_out_data_mix[${b1}:${b0}]; \n"; +//: } +//: foreach my $k (0..$atmm_num -1) { +//: print qq(assign cvt_out_data_p${k} = cvt_out_nz_mask_bp[${k}] ? cvt_out_data_masked[(${k}+1)*${atmmbw}-1:${k}*${atmmbw}] : 0; \n); +//: ##&eperl::flop("-nodeclare -rval \"${atmmbw}'b0\" -en \"cvt_out_reg_en_bp == ${k}\" -d \"cvt_out_data_p${k}\" -q cvt_out_data_p${k}_reg"); +//: &eperl::flop("-nodeclare -rval \"${atmmbw}'b0\" -d \"cvt_out_data_p${k}\" -q cvt_out_data_p${k}_reg"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cvt_out_data_masked[7:0] = cvt_out_pad_mask_bp[0] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[7:0]; +assign cvt_out_data_masked[15:8] = cvt_out_pad_mask_bp[1] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[15:8]; +assign cvt_out_data_masked[23:16] = cvt_out_pad_mask_bp[2] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[23:16]; +assign cvt_out_data_masked[31:24] = cvt_out_pad_mask_bp[3] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[31:24]; +assign cvt_out_data_masked[39:32] = cvt_out_pad_mask_bp[4] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[39:32]; +assign cvt_out_data_masked[47:40] = cvt_out_pad_mask_bp[5] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[47:40]; +assign cvt_out_data_masked[55:48] = cvt_out_pad_mask_bp[6] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[55:48]; +assign cvt_out_data_masked[63:56] = cvt_out_pad_mask_bp[7] ? cfg_pad_value[8-1:0] : cvt_out_data_mix[63:56]; +assign cvt_out_data_p0 = cvt_out_nz_mask_bp[0] ? cvt_out_data_masked[(0+1)*64-1:0*64] : 0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_data_p0_reg <= 64'b0; + end else begin + cvt_out_data_p0_reg <= cvt_out_data_p0; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvt_out_vld_reg_w = cvt_out_vld_bp | dat_cbuf_flush_vld_w; +//: my $dmaif=64/8; +//: my $atmc=8; +//: if ( $dmaif < $atmc ) { +//: my $k = int( log( int($atmc/$dmaif) ) / log(2) ); +//: print "assign cvt_out_addr_reg_w = dat_cbuf_flush_vld_w ? dat_cbuf_flush_idx[17:${k}] : cvt_out_addr_bp; \n"; +//: } else { +//: print "assign cvt_out_addr_reg_w = dat_cbuf_flush_vld_w ? dat_cbuf_flush_idx[16:0] : cvt_out_addr_bp; \n"; +//: } +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmc=8; +//: if($Bnum < $atmc) { +//: my $dmaif_num = $atmc / $Bnum; +//: my $k = int(log($dmaif_num)/log(2)); +//: print qq(wire [$dmaif_num-1:0] cvt_out_sel_reg_w; \n); +//: if($dmaif_num == 2) { +//: print qq(assign cvt_out_sel_reg_w = dat_cbuf_flush_vld_w ? {dat_cbuf_flush_idx[0], ~dat_cbuf_flush_idx[0]} : {cvt_out_sel_bp[0],~cvt_out_sel_bp[0]}; \n); +//: } elsif($dmaif_num == 4) { +//: print qq( +//: assign cvt_out_sel_reg_w = dat_cbuf_flush_vld_w ? {dat_cbuf_flush_idx[1:0]==2'b11, dat_cbuf_flush_idx[1:0]==2'b10, +//: dat_cbuf_flush_idx[1:0]==2'b01, dat_cbuf_flush_idx[1:0]==2'b00} : +//: {cvt_out_sel_bp[1:0]==2'b11,cvt_out_sel_bp[1:0]==2'b10, +//: cvt_out_sel_bp[1:0]==2'b01,cvt_out_sel_bp[1:0]==2'b00}; +//: ); +//: } +//: +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"${dmaif_num}'b0\" -en \"cvt_out_vld_reg_w\" -d \"cvt_out_sel_reg_w\" -q cvt_out_sel_reg"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cvt_out_addr_reg_w = dat_cbuf_flush_vld_w ? dat_cbuf_flush_idx[16:0] : cvt_out_addr_bp; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//================ Non-SLCG clock domain ================// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"cvt_out_vld_reg_w\" -q cvt_out_vld_reg"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"cvt_out_vld_reg_w\" -d \"cvt_out_addr_reg_w\" -q cvt_out_addr_reg"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_vld_reg <= 1'b0; + end else begin + cvt_out_vld_reg <= cvt_out_vld_reg_w; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_out_addr_reg <= {17{1'b0}}; + end else begin + if ((cvt_out_vld_reg_w) == 1'b1) begin + cvt_out_addr_reg <= cvt_out_addr_reg_w; + // VCS coverage off + end else if ((cvt_out_vld_reg_w) == 1'b0) begin + end else begin + cvt_out_addr_reg <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Data buffer flush logic // +//////////////////////////////////////////////////////////////////////// +assign {mon_dat_cbuf_flush_idx_w, + dat_cbuf_flush_idx_w} = dat_cbuf_flush_idx + 1'b1; +//: my $bank_entry = 32 * 512; +//: my $bank_entry_bw = int( log( $bank_entry)/log(2) ); +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $k; +//: if($dmaif < $atmc) { +//: $k = int(log(int($atmc/$dmaif))/log(2)); +//: } else { +//: $k = 0; +//: } +//: print qq( +//: assign dat_cbuf_flush_vld_w = ~dat_cbuf_flush_idx[${bank_entry_bw}+$k-1];//max value = half bank entry * 2^$k +//: assign dp2reg_dat_flush_done = dat_cbuf_flush_idx[${bank_entry_bw}+$k-1]; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dat_cbuf_flush_vld_w = ~dat_cbuf_flush_idx[14+0-1];//max value = half bank entry * 2^0 +assign dp2reg_dat_flush_done = dat_cbuf_flush_idx[14+0-1]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign dat_cbuf_flush_vld_w = ~dat_cbuf_flush_idx[17]; +//assign dp2reg_dat_flush_done = dat_cbuf_flush_idx[17]; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{18{1'b0}}\" -en \"dat_cbuf_flush_vld_w\" -d \"dat_cbuf_flush_idx_w\" -q dat_cbuf_flush_idx"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_cbuf_flush_idx <= {18{1'b0}}; + end else begin + if ((dat_cbuf_flush_vld_w) == 1'b1) begin + dat_cbuf_flush_idx <= dat_cbuf_flush_idx_w; + // VCS coverage off + end else if ((dat_cbuf_flush_vld_w) == 1'b0) begin + end else begin + dat_cbuf_flush_idx <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// output ports // +//////////////////////////////////////////////////////////////////////// +assign cdma2buf_dat_wr_en = cvt_out_vld_reg; +assign cdma2buf_dat_wr_addr = cvt_out_addr_reg; +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmc=8; +//: if($Bnum < $atmc) { +//: print qq(assign cdma2buf_dat_wr_sel = cvt_out_sel_reg; \n ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cdma2buf_dat_wr_data = { +//: my $dmaif=64; +//: my $atmm=8; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmm_num= $Bnum / $atmm; +//: if($atmm_num > 1){ +//: foreach my $i(0..$atmm_num -2) { +//: my $j = $atmm_num - $i -1; +//: print "cvt_out_data_p${j}_reg, "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + cvt_out_data_p0_reg}; +assign dat_nan_mask = {64{1'b1}}; +assign dp2reg_nan_data_num = 32'b0; +assign dp2reg_inf_data_num = 32'b0; +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_47x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_48x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_49x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en | cvt_wr_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_50x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(img2cvt_dat_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en_d1 | op_en_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_63x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1 | cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2 | cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3 | cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4 | cvt_out_vld_d5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[0]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[1]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[2]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[3]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_94x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[4]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[5]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[6]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[7]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_reg_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_reg_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(dat_cbuf_flush_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_102x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(nan_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_103x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(inf_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,2,0,"Error! CVT input conflict!") zzz_assert_zero_one_hot_16x (nvdla_core_clk, `ASSERT_RESET, {dc2cvt_dat_wr_en, img2cvt_dat_wr_en}); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Disable when input data") zzz_assert_never_17x (nvdla_core_clk, `ASSERT_RESET, (~op_en & cvt_wr_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set two high masks") zzz_assert_never_18x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & (|cvt_wr_mask[3:2]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Img set two hight masks when int8 input") zzz_assert_never_20x (nvdla_core_clk, `ASSERT_RESET, (img2cvt_dat_wr_en & (|cvt_wr_mask[3:2]) & is_input_int8[0])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set mean flag") zzz_assert_never_21x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & cvt_wr_mean)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set uint flag") zzz_assert_never_23x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & cvt_wr_uint)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set sub h flag") zzz_assert_never_25x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & (|cvt_wr_sub_h))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Input data mask error!") zzz_assert_never_27x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & (cvt_wr_mask != 4'h1) & (cvt_wr_mask != 4'h3) & (cvt_wr_mask != 4'hf))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Input data high mask set when input int8!") zzz_assert_never_28x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_mask[3] & cfg_in_int8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Expand when 16bit input!") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cfg_in_int8 & is_data_expand)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Expand out of range when sel set!") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & cvt_wr_sel & is_data_expand & cvt_wr_mask[1])); // spyglass disable W504 SelfDeterminedExpr-ML +//nv_assert_never #(0,0,"Error! Half mask without output!") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cvt_wr_ext64 & ~cvt_wr_ext128 & ~cvt_wr_mask[1])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Half mask without output!") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cvt_wr_mask[1])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cvt mode is not enable when format change!") zzz_assert_never_40x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cfg_cvt_en[0] & (cfg_in_precision[1:0] != cfg_proc_precision[1:0]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! invalid precision transform!") zzz_assert_never_41x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & (cfg_in_precision[1:0] == 2'h2 ) & (cfg_proc_precision[1:0] != 2'h2 ))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cell op0 is not ready when input valid!") zzz_assert_never_60x (nvdla_core_clk, `ASSERT_RESET, ((|(cell_en_d0 & ~mon_cell_op0_ready)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cell op1 is not ready when input valid!") zzz_assert_never_61x (nvdla_core_clk, `ASSERT_RESET, ((|(cell_en_d0 & ~mon_cell_op1_ready)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CVT and flush write hazard!") zzz_assert_never_100x (nvdla_core_ng_clk, `ASSERT_RESET, (cvt_out_vld_bp & dat_cbuf_flush_vld_w)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_cvt diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v.vcp new file mode 100644 index 0000000..20dffdb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v.vcp @@ -0,0 +1,881 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_cvt.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_cvt ( + nvdla_core_clk + ,nvdla_core_rstn + ,dc2cvt_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,dc2cvt_dat_wr_sel +//: ,dc2cvt_dat_wr_addr +//: ,dc2cvt_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,dc2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,dc2cvt_dat_wr_addr${i} +//: ,dc2cvt_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,dc2cvt_dat_wr_addr +//: ,dc2cvt_dat_wr_data +//: ); +//: } + ,dc2cvt_dat_wr_info_pd + ,img2cvt_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_sel +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,img2cvt_dat_wr_addr${i} +//: ,img2cvt_dat_wr_data${i} +//: ,img2cvt_mn_wr_data${i} +//: ,img2cvt_dat_wr_pad_mask${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } +// ,img2cvt_dat_wr_addr +// ,img2cvt_dat_wr_hsel +// ,img2cvt_dat_wr_data +// ,img2cvt_mn_wr_data + ,img2cvt_dat_wr_info_pd + ,cdma2buf_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,cdma2buf_dat_wr_sel +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_dat_wr_addr${i} +//: ,cdma2buf_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } +// ,cdma2buf_dat_wr_addr +// ,cdma2buf_dat_wr_hsel +// ,cdma2buf_dat_wr_data + ,nvdla_hls_clk + ,slcg_hls_en + ,nvdla_core_ng_clk + ,reg2dp_op_en + ,reg2dp_in_precision + ,reg2dp_proc_precision + ,reg2dp_cvt_en + ,reg2dp_cvt_truncate + ,reg2dp_cvt_offset + ,reg2dp_cvt_scale + ,reg2dp_nan_to_zero + ,reg2dp_pad_value + ,dp2reg_done +// ,img2cvt_dat_wr_pad_mask + ,dp2reg_nan_data_num + ,dp2reg_inf_data_num + ,dp2reg_dat_flush_done + ); +/////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dc2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: input [${k}-1:0] dc2cvt_dat_wr_sel; +//: input [16:0] dc2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: input [${k}-1:0] dc2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: input [16:0] dc2cvt_dat_wr_addr${i}; +//: input [${dmaif}-1:0] dc2cvt_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: input [16:0] dc2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } +input [11:0] dc2cvt_dat_wr_info_pd; +// input dc2cvt_dat_wr_en; +// input [11:0] dc2cvt_dat_wr_addr; +// input dc2cvt_dat_wr_hsel; +// input [64 -1:0] dc2cvt_dat_wr_data; +// input [11:0] dc2cvt_dat_wr_info_pd; +//////////////// img +input img2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: input [${k}-1:0] img2cvt_dat_wr_sel; +//: input [16:0] img2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] img2cvt_dat_wr_data; +//: input [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: input [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: input [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: input [16:0] img2cvt_dat_wr_addr${i}; +//: input [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: input [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: input [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: input [16:0] img2cvt_dat_wr_addr; +//: input [${dmaif}-1:0] img2cvt_dat_wr_data; +//: input [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: input [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +input [11:0] img2cvt_dat_wr_info_pd; +// input [11:0] img2cvt_dat_wr_addr; +// input img2cvt_dat_wr_hsel; +// //input [1023:0] img2cvt_dat_wr_data; +// input [64 -1:0] img2cvt_dat_wr_data; +// //input [127:0] img2cvt_dat_wr_pad_mask; +// //input [1023:0] img2cvt_mn_wr_data; +// //: my $dmaif = NVDLA_CDMA_DMAIF_BW; +// //: my $Bnum = $dmaif / NVDLA_BPE; +// //: print qq(input [$Bnum-1:0] img2cvt_dat_wr_pad_mask; ); +// input [64 -1:0] img2cvt_mn_wr_data; +output cdma2buf_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_sel; +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } +// output cdma2buf_dat_wr_en; +// output [11:0] cdma2buf_dat_wr_addr; +// output [1:0] cdma2buf_dat_wr_hsel; +// //output [1023:0] cdma2buf_dat_wr_data; +// output [64 -1:0] cdma2buf_dat_wr_data; +input nvdla_hls_clk; +output slcg_hls_en; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_cvt_en; +input [5:0] reg2dp_cvt_truncate; +input [15:0] reg2dp_cvt_offset; +input [15:0] reg2dp_cvt_scale; +input [0:0] reg2dp_nan_to_zero; +input [15:0] reg2dp_pad_value; +input dp2reg_done; +output [31:0] dp2reg_nan_data_num; +output [31:0] dp2reg_inf_data_num; +output dp2reg_dat_flush_done; +/////////////////////////////////////////////////////////////////// +reg [5:0] cfg_cvt_en; +reg cfg_in_int8; +reg [1:0] cfg_in_precision; +reg [1:0] cfg_proc_precision; +reg [15:0] cfg_scale; +reg [5:0] cfg_truncate; +reg [15:0] cfg_offset; +reg cfg_out_int8; +reg [15:0] cfg_pad_value; +reg [16:0] cvt_out_addr_d1; +reg [16:0] cvt_out_addr_reg; +//: my $dmaif=64; +//: my $atmm=8; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmm_num= $Bnum / $atmm; +//: foreach my $k (0..$atmm_num -1) { +//: print qq(reg [${atmm}*${bpe}-1:0] cvt_out_data_p${k}_reg; \n); +//: print qq(wire [${atmm}*${bpe}-1:0] cvt_out_data_p${k}; \n); +//: } +reg [3:0] cvt_out_nz_mask_d1; +reg cvt_out_pad_vld_d1; +reg cvt_out_vld_d1; +reg cvt_out_vld_reg; +reg [64 -1:0] cvt_wr_data_d1; +reg cvt_wr_en_d1; +reg cvt_wr_mean_d1; +reg [64/8*16-1:0] cvt_wr_mean_data_d1; +reg [17:0] dat_cbuf_flush_idx; +wire [31:0] dp2reg_inf_data_num; +wire [31:0] dp2reg_nan_data_num; +reg is_data_expand; +reg is_data_normal; +reg is_input_fp16; +reg [0:0] is_input_int8; +reg op_en; +reg op_en_d0; +reg cvt_wr_uint_d1; +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: foreach my $i (0..$Bnum -1) { +//: print qq( +//: reg [16:0] oprand_0_${i}_d0; +//: reg [15:0] oprand_1_${i}_d0; +//: wire [16:0] oprand_0_${i}_ori; +//: wire [15:0] oprand_1_${i}_ori; +//: wire [15:0] cellout_${i}; +//: ); +//: } +//: print qq( +//: wire [$Bnum-1:0] oprand_0_8b_sign; +//: wire [$Bnum-1:0] mon_cell_op0_ready; +//: wire [$Bnum-1:0] mon_cell_op1_ready; +//: wire [$Bnum-1:0] cvt_cell_en; +//: reg [$Bnum-1:0] cell_en_d0; +//: reg [$Bnum-1:0] cvt_cell_en_d1; +//: ); +reg slcg_hls_en_d1; +reg slcg_hls_en_d2; +reg slcg_hls_en_d3; +wire [15:0] cfg_pad_value_w; +wire cfg_reg_en; +wire [64 -1:0] cvt_data_cell; +wire [16:0] cvt_out_addr; +wire [16:0] cvt_out_addr_bp; +wire [16:0] cvt_out_addr_reg_w; +wire [64 -1:0] cvt_out_data_masked; +wire [64 -1:0] cvt_out_data_mix; +wire [3:0] cvt_out_nz_mask_bp; +wire cvt_out_pad_vld_bp; +wire cvt_out_vld; +wire cvt_out_vld_bp; +wire cvt_out_vld_reg_w; +wire [16:0] cvt_wr_addr; +wire [64 -1:0] cvt_wr_data; +wire cvt_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: my $s = int($atmc/$dmaif); +//: print qq( +//: wire [${k}-1:0] cvt_wr_sel; +//: wire [${k}-1:0] cvt_out_sel; +//: reg [${k}-1:0] cvt_out_sel_d1; +//: wire [${k}-1:0] cvt_out_sel_bp; +//: reg [${s}-1:0] cvt_out_sel_reg; +//: wire [${k}-1:0] cvt_out_reg_en; +//: reg [${k}-1:0] cvt_out_reg_en_d1; +//: wire [${k}-1:0] cvt_out_reg_en_bp; +//: ); +//: } else { +//: print qq( +//: wire cvt_out_reg_en; +//: reg cvt_out_reg_en_d1; +//: wire cvt_out_reg_en_bp; +//: ); +//: } +//: print qq( +//: wire [${Bnum}-1:0] cvt_wr_pad_mask; +//: reg [${Bnum}-1:0] cvt_out_pad_mask_d1; +//: wire [${Bnum}-1:0] cvt_out_pad_mask_bp; +//: ); +wire [11:0] cvt_wr_info_pd; +wire [3:0] cvt_wr_mask; +wire cvt_wr_mean; +wire [64/8*16-1:0] cvt_wr_mean_data; +wire [2:0] cvt_wr_sub_h; +wire cvt_wr_uint; +wire [17:0] dat_cbuf_flush_idx_w; +wire dat_cbuf_flush_vld_w; +wire [31:0] dat_half_mask; +wire [64 -1:0] dat_nan_mask; +wire is_data_expand_w; +wire is_data_normal_w; +wire is_input_fp16_w; +wire is_input_int8_w; +wire is_output_int8_w; +wire mon_dat_cbuf_flush_idx_w; +wire nan_carry; +wire nan_reg_en; +wire op_en_w; +wire slcg_hls_en_w; +/////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// prepare input signals // +//////////////////////////////////////////////////////////////////////// +assign op_en_w = ~dp2reg_done & reg2dp_op_en; +assign cfg_reg_en = op_en_w & ~op_en; +assign is_input_int8_w = 1'b1; +assign is_input_fp16_w = 1'b0; +assign is_output_int8_w = 1'b1; +assign is_data_expand_w = is_input_int8_w & ~is_output_int8_w; +assign is_data_normal_w = is_input_int8_w ~^ is_output_int8_w; +//assign nan_pass_w = ~reg2dp_nan_to_zero | ~is_input_fp16_w; +//assign cfg_pad_value_w = is_output_int8_w ? {2{reg2dp_pad_value[7:0]}} : reg2dp_pad_value; +assign cfg_pad_value_w = reg2dp_pad_value; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"op_en_w\" -q op_en"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_in_precision\" -q cfg_in_precision"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_proc_precision\" -q cfg_proc_precision"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_cvt_scale\" -q cfg_scale"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_cvt_truncate\" -q cfg_truncate"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"cfg_reg_en\" -d \"reg2dp_cvt_offset\" -q cfg_offset"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"cfg_reg_en\" -d \"{6{reg2dp_cvt_en}}\" -q cfg_cvt_en"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_input_int8_w\" -q cfg_in_int8"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_output_int8_w\" -q cfg_out_int8"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"cfg_reg_en\" -d \"cfg_pad_value_w\" -q cfg_pad_value"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_input_int8_w\" -q is_input_int8"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_input_fp16_w\" -q is_input_fp16"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_data_expand_w\" -q is_data_expand"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cfg_reg_en\" -d \"is_data_normal_w\" -q is_data_normal"); +// //: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"cfg_reg_en\" -d \"nan_pass_w\" -q nan_pass"); +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_hls_en_w = reg2dp_op_en & reg2dp_cvt_en; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_hls_en_w\" -q slcg_hls_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_hls_en_d1\" -q slcg_hls_en_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_hls_en_d2\" -q slcg_hls_en_d3"); +assign slcg_hls_en = slcg_hls_en_d3; +//////////////////////////////////////////////////////////////////////// +// Input signals // +//////////////////////////////////////////////////////////////////////// +assign cvt_wr_info_pd = ({12 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_info_pd) + | ({12 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_info_pd); +assign cvt_wr_mask[3:0] = cvt_wr_info_pd[3:0]; +//assign cvt_wr_interleave = cvt_wr_info_pd[4]; +//assign cvt_wr_ext64 = cvt_wr_info_pd[5]; +//assign cvt_wr_ext128 = cvt_wr_info_pd[6]; +assign cvt_wr_mean = cvt_wr_info_pd[7]; +assign cvt_wr_uint = cvt_wr_info_pd[8]; +assign cvt_wr_sub_h[2:0] = cvt_wr_info_pd[11:9]; +assign cvt_wr_en = (dc2cvt_dat_wr_en | img2cvt_dat_wr_en); +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: assign cvt_wr_pad_mask = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask : ${Bnum}'d0; +//: assign cvt_wr_sel = dc2cvt_dat_wr_en ? dc2cvt_dat_wr_sel +//: : img2cvt_dat_wr_en ? img2cvt_dat_wr_sel : 0; +//: assign cvt_wr_addr = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr) +//: | ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr); +//: assign cvt_wr_data = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data) +//: | ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data); +//: assign cvt_wr_mean_data = img2cvt_mn_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: assign cvt_dat_wr_mask = (dc2cvt_dat_wr_en & dc2cvt_dat_wr_mask) +//: | (img2cvt_dat_wr_en & img2cvt_dat_wr_mask); +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign cvt_wr_pad_mask${i} = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask${i} : ${Bnum}'d0; +//: assign cvt_wr_addr${i} = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr${i}) +//: | ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr${i}); +//: assign cvt_wr_data${i} = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data${i}) +//: | ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data${i}); +//: assign cvt_wr_mean_data${i} = img2cvt_mn_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: assign cvt_wr_pad_mask = img2cvt_dat_wr_en ? img2cvt_dat_wr_pad_mask : ${Bnum}'d0; +//: assign cvt_wr_addr = ({17 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_addr) +//: | ({17 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_addr); +//: assign cvt_wr_data = ({64 {dc2cvt_dat_wr_en}} & dc2cvt_dat_wr_data) +//: | ({64 {img2cvt_dat_wr_en}} & img2cvt_dat_wr_data); +//: assign cvt_wr_mean_data = img2cvt_mn_wr_data; +//: ); +//: } +//////////////////////////////////////////////////////////////////////// +// generator mux control signals // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: assign cvt_out_sel = cvt_wr_sel; +//: assign cvt_out_reg_en = cvt_wr_en ? cvt_out_sel : 0; +//: ); +//: } else { +//: print qq( +//: //assign cvt_out_reg_en = cvt_wr_en; +//: assign cvt_out_reg_en = 1'b0; +//: ); +//: } +assign cvt_out_addr = cvt_wr_addr; +assign cvt_out_vld = cvt_wr_en; +//: my $dmaif=64; +//: my $atmm=8; +//: my $Bnum = $dmaif / 8; +//: my $atmm_num = $Bnum / $atmm; +//: if($atmm_num == 1) { +//: print qq( +//: assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {${atmm}{cvt_wr_mask[0]}} : ${Bnum}'b0; +//: ); +//: } elsif($atmm_num == 2) { +//: print qq( +//: assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {{${atmm}{cvt_wr_mask[1]}},{${atmm}{cvt_wr_mask[0]}}} : ${Bnum}'b0; +//: ); +//: } elsif($atmm_num == 4) { +//: print qq( +//: assign cvt_cell_en = (cvt_wr_en & cfg_cvt_en[0]) ? {{${atmm}{cvt_wr_mask[3]}},{${atmm}{cvt_wr_mask[2]}},{${atmm}{cvt_wr_mask[1]}},{${atmm}{cvt_wr_mask[0]}}} : ${Bnum}'b0; +//: ); +//: } +//assign cvt_out_reg_en = cvt_wr_en ? {{4{cvt_out_sel[1]}}, {4{cvt_out_sel[0]}}} : 8'b0; +//////////////////////////////////////////////////////////////////////// +// One pipeline stage for retiming // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_wr_en\" -q cvt_wr_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cvt_wr_en\" -d \"cvt_wr_mean\" -q cvt_wr_mean_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"cvt_wr_en\" -d \"cvt_wr_uint\" -q cvt_wr_uint_d1"); +//: &eperl::flop("-nodeclare -norst -en \"cvt_wr_en & cvt_wr_mean\" -d \"cvt_wr_mean_data\" -q cvt_wr_mean_data_d1"); +//: &eperl::flop("-nodeclare -norst -en \"cvt_wr_en\" -d \"cvt_wr_data\" -q cvt_wr_data_d1"); +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: &eperl::flop("-nodeclare -rval \"${Bnum}'b0\" -en \"cvt_wr_en | cvt_wr_en_d1\" -d \"cvt_cell_en\" -q cvt_cell_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_out_vld\" -q cvt_out_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"img2cvt_dat_wr_en\" -q cvt_out_pad_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"{17{1'b0}}\" -en \"cvt_wr_en\" -d \"cvt_out_addr\" -q cvt_out_addr_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"cvt_wr_en\" -d \"cvt_wr_mask\" -q cvt_out_nz_mask_d1"); +//: &eperl::flop("-nodeclare -rval \"${Bnum}'b0\" -en \"img2cvt_dat_wr_en\" -d \"cvt_wr_pad_mask\" -q cvt_out_pad_mask_d1"); +//: my $atmc=8*8; +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: if($dmaif < $atmc) { +//: &eperl::flop("-nodeclare -rval \"${k}'b0\" -d \"cvt_out_reg_en\" -q cvt_out_reg_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"cvt_wr_en\" -d \"cvt_out_sel\" -q cvt_out_sel_d1"); +//: } else { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_out_reg_en\" -q cvt_out_reg_en_d1"); +//: } +//////////////////////////////////////////////////////////////////////// +// generate input signals for convertor cells // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: foreach my $i(0..$Bnum-1) { +//: my $j = $i + 1; +//: print qq ( +//: assign oprand_0_8b_sign[${i}] = (cvt_wr_data_d1[${j}*${bpe}-1] & ~cvt_wr_uint_d1); +//: assign oprand_0_${i}_ori = {{(17-${bpe}){oprand_0_8b_sign[${i}]}}, cvt_wr_data_d1[${j}*${bpe}-1:${i}*${bpe}]} ; +//: assign oprand_1_${i}_ori = cvt_wr_mean_d1 ? cvt_wr_mean_data_d1[${j}*16-1:${i}*16] : cfg_offset[15:0]; +//: ); +//: &eperl::flop("-nodeclare -norst -en \"cvt_cell_en_d1[${i}]\" -d \"oprand_0_${i}_ori\" -q oprand_0_${i}_d0"); +//: &eperl::flop("-nodeclare -norst -en \"cvt_cell_en_d1[${i}]\" -d \"oprand_1_${i}_ori\" -q oprand_1_${i}_d0"); +//: } +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = ($dmaif / $bpe); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cvt_wr_en_d1\" -q op_en_d0"); +//: &eperl::flop("-nodeclare -rval \"${Bnum}'b0\" -en \"cvt_wr_en_d1 | op_en_d0\" -d \"cvt_cell_en_d1\" -q cell_en_d0 "); +//////////////////////////////////////////////////////////////////////// +// instance of convert cells // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: foreach my $i (0..$Bnum-1) { +//: print qq ( +//: NV_NVDLA_CDMA_CVT_cell u_cell_${i} ( +//: .nvdla_core_clk (nvdla_hls_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.chn_data_in_rsc_z (oprand_0_${i}_d0[16:0]) +//: ,.chn_data_in_rsc_vz (cell_en_d0[${i}]) +//: // spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.chn_data_in_rsc_lz (mon_cell_op0_ready[${i}]) +//: // spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.chn_alu_in_rsc_z (oprand_1_${i}_d0[15:0]) +//: ,.chn_alu_in_rsc_vz (cell_en_d0[${i}]) +//: // spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.chn_alu_in_rsc_lz (mon_cell_op1_ready[${i}]) +//: // spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +//: ,.cfg_mul_in_rsc_z (cfg_scale[15:0]) +//: ,.cfg_in_precision (cfg_in_precision[1:0]) +//: ,.cfg_out_precision (cfg_proc_precision[1:0]) +//: ,.cfg_truncate (cfg_truncate[5:0]) +//: ,.chn_data_out_rsc_z (cellout_${i}[15:0]) +//: ,.chn_data_out_rsc_vz (1'b1) +//: ,.chn_data_out_rsc_lz ( ) +//: );\n); +//: } +//: print "\n"; +assign cvt_data_cell = { +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: if($Bnum > 1) { +//: foreach my $i(0..$Bnum-2){ +//: my $j = $Bnum - $i -1; +//: print qq(cellout_${j}[${bpe}-1:0], ); +//: } +//: } +//: print qq(cellout_0[${bpe}-1:0]}; \n); +//////////////////////////////////////////////////////////////////////// +// stage 2: pipeline to match latency of conver cells // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: for(my $i = 1; $i <= 3 +1; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"cvt_out_vld_d${i}\" -q cvt_out_vld_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"cvt_out_pad_vld_d${i}\" -q cvt_out_pad_vld_d${j}"); +//: if($dmaif < $atmc) { +//: &eperl::flop("-wid $k -rval \"{${k}{1'b0}}\" -en \"cvt_out_vld_d${i}\" -d \"cvt_out_sel_d${i}\" -q cvt_out_sel_d${j}"); +//: &eperl::flop("-wid $k -rval \"{${k}{1'b0}}\" -en \"cvt_out_vld_d${i} | cvt_out_vld_d2\" -d \"cvt_out_reg_en_d${i}\" -q cvt_out_reg_en_d${j}"); +//: } else { +//: &eperl::flop("-wid $k -rval \"1'b0\" -en \"cvt_out_vld_d${i} | cvt_out_vld_d2\" -d \"cvt_out_reg_en_d${i}\" -q cvt_out_reg_en_d${j}"); +//: } +//: &eperl::flop("-wid 17 -rval \"{17{1'b0}}\" -en \"cvt_out_vld_d${i}\" -d \"cvt_out_addr_d${i}\" -q cvt_out_addr_d${j}"); +//: &eperl::flop("-wid 4 -rval \"{4{1'b0}}\" -en \"cvt_out_vld_d${i}\" -d \"cvt_out_nz_mask_d${i}\" -q cvt_out_nz_mask_d${j}"); +//: &eperl::flop("-wid $Bnum -rval \"{${Bnum}{1'b0}}\" -en \"cvt_out_pad_vld_d${i}\" -d \"cvt_out_pad_mask_d${i}\" -q cvt_out_pad_mask_d${j}"); +//: print "\n\n"; +//: } +//: my $i = 3 +2; +//: if($dmaif < $atmc){ +//: print qq( +//: assign cvt_out_sel_bp = cfg_cvt_en[1] ? cvt_out_sel_d${i} : cvt_out_sel_d1; +//: ); +//: } +//: print qq( +//: assign cvt_out_vld_bp = cfg_cvt_en[1] ? cvt_out_vld_d${i} : cvt_out_vld_d1; +//: assign cvt_out_addr_bp = cfg_cvt_en[1] ? cvt_out_addr_d${i} : cvt_out_addr_d1; +//: assign cvt_out_nz_mask_bp = cfg_cvt_en[2] ? cvt_out_nz_mask_d${i} : cvt_out_nz_mask_d1; +//: assign cvt_out_pad_vld_bp = cfg_cvt_en[3] ? cvt_out_pad_vld_d${i} : cvt_out_pad_vld_d1; +//: assign cvt_out_pad_mask_bp = ~cvt_out_pad_vld_bp ? ${Bnum}'b0 : (cfg_cvt_en[3] ? cvt_out_pad_mask_d${i} : cvt_out_pad_mask_d1); +//: assign cvt_out_reg_en_bp = cfg_cvt_en[4] ? cvt_out_reg_en_d${i} : cvt_out_reg_en_d1; +//: ); +//////////////////////////////////////////////////////////////////////// +// stage 3: final pipeline stage // +//////////////////////////////////////////////////////////////////////// +assign cvt_out_data_mix = cfg_cvt_en[5] ? cvt_data_cell : cvt_wr_data_d1; +//: my $dmaif=64; +//: my $atmm=8; +//: my $bpe = 8; +//: my $atmmbw= $atmm * $bpe; +//: my $Bnum = $dmaif / $bpe; +//: my $atmm_num= $Bnum / $atmm; +//: for(my $i = 0; $i < $Bnum; $i ++) { +//: my $b0 = $i * $bpe; +//: my $b1 = ($i + 1) * $bpe - 1; +//: print "assign cvt_out_data_masked[${b1}:${b0}] = cvt_out_pad_mask_bp[${i}] ? cfg_pad_value[${bpe}-1:0] : cvt_out_data_mix[${b1}:${b0}]; \n"; +//: } +//: foreach my $k (0..$atmm_num -1) { +//: print qq(assign cvt_out_data_p${k} = cvt_out_nz_mask_bp[${k}] ? cvt_out_data_masked[(${k}+1)*${atmmbw}-1:${k}*${atmmbw}] : 0; \n); +//: ##&eperl::flop("-nodeclare -rval \"${atmmbw}'b0\" -en \"cvt_out_reg_en_bp == ${k}\" -d \"cvt_out_data_p${k}\" -q cvt_out_data_p${k}_reg"); +//: &eperl::flop("-nodeclare -rval \"${atmmbw}'b0\" -d \"cvt_out_data_p${k}\" -q cvt_out_data_p${k}_reg"); +//: } +assign cvt_out_vld_reg_w = cvt_out_vld_bp | dat_cbuf_flush_vld_w; +//: my $dmaif=64/8; +//: my $atmc=8; +//: if ( $dmaif < $atmc ) { +//: my $k = int( log( int($atmc/$dmaif) ) / log(2) ); +//: print "assign cvt_out_addr_reg_w = dat_cbuf_flush_vld_w ? dat_cbuf_flush_idx[17:${k}] : cvt_out_addr_bp; \n"; +//: } else { +//: print "assign cvt_out_addr_reg_w = dat_cbuf_flush_vld_w ? dat_cbuf_flush_idx[16:0] : cvt_out_addr_bp; \n"; +//: } +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmc=8; +//: if($Bnum < $atmc) { +//: my $dmaif_num = $atmc / $Bnum; +//: my $k = int(log($dmaif_num)/log(2)); +//: print qq(wire [$dmaif_num-1:0] cvt_out_sel_reg_w; \n); +//: if($dmaif_num == 2) { +//: print qq(assign cvt_out_sel_reg_w = dat_cbuf_flush_vld_w ? {dat_cbuf_flush_idx[0], ~dat_cbuf_flush_idx[0]} : {cvt_out_sel_bp[0],~cvt_out_sel_bp[0]}; \n); +//: } elsif($dmaif_num == 4) { +//: print qq( +//: assign cvt_out_sel_reg_w = dat_cbuf_flush_vld_w ? {dat_cbuf_flush_idx[1:0]==2'b11, dat_cbuf_flush_idx[1:0]==2'b10, +//: dat_cbuf_flush_idx[1:0]==2'b01, dat_cbuf_flush_idx[1:0]==2'b00} : +//: {cvt_out_sel_bp[1:0]==2'b11,cvt_out_sel_bp[1:0]==2'b10, +//: cvt_out_sel_bp[1:0]==2'b01,cvt_out_sel_bp[1:0]==2'b00}; +//: ); +//: } +//: +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"${dmaif_num}'b0\" -en \"cvt_out_vld_reg_w\" -d \"cvt_out_sel_reg_w\" -q cvt_out_sel_reg"); +//: } +//================ Non-SLCG clock domain ================// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"cvt_out_vld_reg_w\" -q cvt_out_vld_reg"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"cvt_out_vld_reg_w\" -d \"cvt_out_addr_reg_w\" -q cvt_out_addr_reg"); +//////////////////////////////////////////////////////////////////////// +// Data buffer flush logic // +//////////////////////////////////////////////////////////////////////// +assign {mon_dat_cbuf_flush_idx_w, + dat_cbuf_flush_idx_w} = dat_cbuf_flush_idx + 1'b1; +//: my $bank_entry = 32 * 512; +//: my $bank_entry_bw = int( log( $bank_entry)/log(2) ); +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $k; +//: if($dmaif < $atmc) { +//: $k = int(log(int($atmc/$dmaif))/log(2)); +//: } else { +//: $k = 0; +//: } +//: print qq( +//: assign dat_cbuf_flush_vld_w = ~dat_cbuf_flush_idx[${bank_entry_bw}+$k-1];//max value = half bank entry * 2^$k +//: assign dp2reg_dat_flush_done = dat_cbuf_flush_idx[${bank_entry_bw}+$k-1]; +//: ); +//assign dat_cbuf_flush_vld_w = ~dat_cbuf_flush_idx[17]; +//assign dp2reg_dat_flush_done = dat_cbuf_flush_idx[17]; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{18{1'b0}}\" -en \"dat_cbuf_flush_vld_w\" -d \"dat_cbuf_flush_idx_w\" -q dat_cbuf_flush_idx"); +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// output ports // +//////////////////////////////////////////////////////////////////////// +assign cdma2buf_dat_wr_en = cvt_out_vld_reg; +assign cdma2buf_dat_wr_addr = cvt_out_addr_reg; +//: my $dmaif=64; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmc=8; +//: if($Bnum < $atmc) { +//: print qq(assign cdma2buf_dat_wr_sel = cvt_out_sel_reg; \n ); +//: } +assign cdma2buf_dat_wr_data = { +//: my $dmaif=64; +//: my $atmm=8; +//: my $bpe = 8; +//: my $Bnum = $dmaif / $bpe; +//: my $atmm_num= $Bnum / $atmm; +//: if($atmm_num > 1){ +//: foreach my $i(0..$atmm_num -2) { +//: my $j = $atmm_num - $i -1; +//: print "cvt_out_data_p${j}_reg, "; +//: } +//: } + cvt_out_data_p0_reg}; +assign dat_nan_mask = {64{1'b1}}; +assign dp2reg_nan_data_num = 32'b0; +assign dp2reg_inf_data_num = 32'b0; +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cfg_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_47x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_48x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_49x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en | cvt_wr_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_50x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(img2cvt_dat_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_wr_en_d1 | op_en_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_63x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1 | cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2 | cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3 | cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_pad_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4 | cvt_out_vld_d5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[0]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[1]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[2]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[3]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_94x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[4]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[5]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[6]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_reg_en_bp[7]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_reg_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cvt_out_vld_reg_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(dat_cbuf_flush_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_102x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(nan_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_103x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(inf_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,2,0,"Error! CVT input conflict!") zzz_assert_zero_one_hot_16x (nvdla_core_clk, `ASSERT_RESET, {dc2cvt_dat_wr_en, img2cvt_dat_wr_en}); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Disable when input data") zzz_assert_never_17x (nvdla_core_clk, `ASSERT_RESET, (~op_en & cvt_wr_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set two high masks") zzz_assert_never_18x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & (|cvt_wr_mask[3:2]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Img set two hight masks when int8 input") zzz_assert_never_20x (nvdla_core_clk, `ASSERT_RESET, (img2cvt_dat_wr_en & (|cvt_wr_mask[3:2]) & is_input_int8[0])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set mean flag") zzz_assert_never_21x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & cvt_wr_mean)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set uint flag") zzz_assert_never_23x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & cvt_wr_uint)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Dc set sub h flag") zzz_assert_never_25x (nvdla_core_clk, `ASSERT_RESET, (dc2cvt_dat_wr_en & (|cvt_wr_sub_h))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Input data mask error!") zzz_assert_never_27x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & (cvt_wr_mask != 4'h1) & (cvt_wr_mask != 4'h3) & (cvt_wr_mask != 4'hf))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Input data high mask set when input int8!") zzz_assert_never_28x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_mask[3] & cfg_in_int8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Expand when 16bit input!") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cfg_in_int8 & is_data_expand)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Expand out of range when sel set!") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & cvt_wr_sel & is_data_expand & cvt_wr_mask[1])); // spyglass disable W504 SelfDeterminedExpr-ML +//nv_assert_never #(0,0,"Error! Half mask without output!") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cvt_wr_ext64 & ~cvt_wr_ext128 & ~cvt_wr_mask[1])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Half mask without output!") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cvt_wr_mask[1])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cvt mode is not enable when format change!") zzz_assert_never_40x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & ~cfg_cvt_en[0] & (cfg_in_precision[1:0] != cfg_proc_precision[1:0]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! invalid precision transform!") zzz_assert_never_41x (nvdla_core_clk, `ASSERT_RESET, (cvt_wr_en & (cfg_in_precision[1:0] == 2'h2 ) & (cfg_proc_precision[1:0] != 2'h2 ))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cell op0 is not ready when input valid!") zzz_assert_never_60x (nvdla_core_clk, `ASSERT_RESET, ((|(cell_en_d0 & ~mon_cell_op0_ready)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cell op1 is not ready when input valid!") zzz_assert_never_61x (nvdla_core_clk, `ASSERT_RESET, ((|(cell_en_d0 & ~mon_cell_op1_ready)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CVT and flush write hazard!") zzz_assert_never_100x (nvdla_core_ng_clk, `ASSERT_RESET, (cvt_out_vld_bp & dat_cbuf_flush_vld_w)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_cvt diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v new file mode 100644 index 0000000..1891204 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v @@ -0,0 +1,3733 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_dc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_dc ( + input nvdla_core_clk +,input nvdla_core_rstn +,input [31:0] pwrbus_ram_pd +,output dc_dat2mcif_rd_req_valid +,input dc_dat2mcif_rd_req_ready +,output [( 32 + 15 )-1:0] dc_dat2mcif_rd_req_pd +,input mcif2dc_dat_rd_rsp_valid +,output mcif2dc_dat_rd_rsp_ready +,input [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd +,output dc2cvt_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,output [${k}-1:0] dc2cvt_dat_wr_sel +//: ,output [16:0] dc2cvt_dat_wr_addr +//: ,output [${dmaif}-1:0] dc2cvt_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,output [${k}-1:0] dc2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,output [16:0] dc2cvt_dat_wr_addr${i} +//: ,output [${dmaif}-1:0] dc2cvt_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,output [16:0] dc2cvt_dat_wr_addr +//: ,output [${dmaif}-1:0] dc2cvt_dat_wr_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,output [16:0] dc2cvt_dat_wr_addr +,output [64-1:0] dc2cvt_dat_wr_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) +,output [11:0] dc2cvt_dat_wr_info_pd +,output reg [1:0] dc2status_state +,output dc2status_dat_updt +,output [14:0] dc2status_dat_entries +,output [13:0] dc2status_dat_slices +,input status2dma_fsm_switch +,input [13:0] status2dma_valid_slices +,input [14:0] status2dma_free_entries +,input [14:0] status2dma_wr_idx +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,output dc2sbuf_p${i}_wr_en +//: ,output [7:0] dc2sbuf_p${i}_wr_addr +//: ,output [${atmm}-1:0] dc2sbuf_p${i}_wr_data +//: ,output reg dc2sbuf_p${i}_rd_en +//: ,output reg [7:0] dc2sbuf_p${i}_rd_addr +//: ,input [${atmm}-1:0] dc2sbuf_p${i}_rd_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,output dc2sbuf_p0_wr_en +,output [7:0] dc2sbuf_p0_wr_addr +,output [64-1:0] dc2sbuf_p0_wr_data +,output reg dc2sbuf_p0_rd_en +,output reg [7:0] dc2sbuf_p0_rd_addr +,input [64-1:0] dc2sbuf_p0_rd_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) +,input sc2cdma_dat_pending_req +,input nvdla_core_ng_clk +,input reg2dp_op_en +,input reg2dp_conv_mode +,input reg2dp_data_reuse +,input reg2dp_skip_data_rls +,input reg2dp_datain_format +,input [12:0] reg2dp_datain_width +,input [12:0] reg2dp_datain_height +,input [12:0] reg2dp_datain_channel +,input reg2dp_datain_ram_type +,input [31:0] reg2dp_datain_addr_high_0 +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: ,input [31-${atmbw}:0] reg2dp_datain_addr_low_0 +//: ,input [31-${atmbw}:0] reg2dp_line_stride +//: ,input [31-${atmbw}:0] reg2dp_surf_stride +//: ,input [31-${atmbw}:0] reg2dp_batch_stride +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,input [31-3:0] reg2dp_datain_addr_low_0 +,input [31-3:0] reg2dp_line_stride +,input [31-3:0] reg2dp_surf_stride +,input [31-3:0] reg2dp_batch_stride + +//| eperl: generated_end (DO NOT EDIT ABOVE) +,input reg2dp_line_packed +,input reg2dp_surf_packed +,input [4:0] reg2dp_batches +,input [16:0] reg2dp_entries //entry number per slice +,input [11:0] reg2dp_grains +,input [4:0] reg2dp_data_bank +,input reg2dp_dma_en +,output slcg_dc_gate_wg +,output slcg_dc_gate_img +,output reg [31:0] dp2reg_dc_rd_stall +,output reg [31:0] dp2reg_dc_rd_latency + ); +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +reg cbuf_is_ready; +//: my $dmabw=64; +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: reg [16:0] cbuf_wr_addr_$i; +//: wire [16:0] cbuf_wr_addr_d0_$i; +//: reg [16:0] cbuf_wr_addr_d1_$i; +//: reg [16:0] cbuf_wr_addr_d2_$i; +//: reg [16:0] cbuf_wr_addr_d3_$i; +//: reg [$dmabw-1:0] cbuf_wr_data_d3_$i; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [16:0] cbuf_wr_addr_0; +wire [16:0] cbuf_wr_addr_d0_0; +reg [16:0] cbuf_wr_addr_d1_0; +reg [16:0] cbuf_wr_addr_d2_0; +reg [16:0] cbuf_wr_addr_d3_0; +reg [64-1:0] cbuf_wr_data_d3_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg cbuf_wr_en; +reg cbuf_wr_en_d1; +reg cbuf_wr_en_d2; +reg cbuf_wr_en_d3; +//reg cbuf_wr_hsel; +reg [3:0] cbuf_wr_info_mask; +reg [11:0] cbuf_wr_info_pd_d1; +reg [11:0] cbuf_wr_info_pd_d2; +reg [11:0] cbuf_wr_info_pd_d3; +reg [4:0] ch0_cnt; +reg mon_ch0_cnt; +reg [5:0] ch0_p0_rd_addr_cnt; +reg mon_ch0_p0_rd_addr_cnt; +reg [5:0] ch0_p0_wr_addr_cnt; +reg mon_ch0_p0_wr_addr_cnt; +reg [5:0] ch0_p1_rd_addr_cnt; +reg mon_ch0_p1_rd_addr_cnt; +reg [5:0] ch0_p1_wr_addr_cnt; +reg mon_ch0_p1_wr_addr_cnt; +reg [4:0] ch1_cnt; +reg mon_ch1_cnt; +reg [5:0] ch1_p0_wr_addr_cnt; +reg mon_ch1_p0_wr_addr_cnt; +reg [5:0] ch1_p0_rd_addr_cnt; +reg [5:0] ch1_p1_rd_addr_cnt; +reg mon_ch1_p0_rd_addr_cnt; +reg mon_ch1_p1_rd_addr_cnt; +reg [5:0] ch1_p1_wr_addr_cnt; +reg mon_ch1_p1_wr_addr_cnt; +reg [4:0] ch2_cnt; +reg mon_ch2_cnt; +reg [5:0] ch2_p0_rd_addr_cnt; +reg mon_ch2_p0_rd_addr_cnt; +reg [5:0] ch2_p0_wr_addr_cnt; +reg mon_ch2_p0_wr_addr_cnt; +reg [5:0] ch2_p1_wr_addr_cnt; +reg mon_ch2_p1_wr_addr_cnt; +reg [4:0] ch3_cnt; +reg mon_ch3_cnt; +reg [5:0] ch3_p0_wr_addr_cnt; +reg mon_ch3_p0_wr_addr_cnt; +reg [5:0] ch3_p0_rd_addr_cnt; +reg mon_ch3_p0_rd_addr_cnt; +reg [5:0] ch3_p1_wr_addr_cnt; +reg mon_ch3_p1_wr_addr_cnt; +reg [1:0] cur_state; +reg [14:0] dat_entries_d0; +reg [14:0] dat_entries_d1; +reg [14:0] dat_entries_d2; +reg [14:0] dat_entries_d3; +reg [13:0] dat_slices_d0; +reg [13:0] dat_slices_d1; +reg [13:0] dat_slices_d2; +reg [13:0] dat_slices_d3; +reg dat_updt_d0; +reg dat_updt_d1; +reg dat_updt_d2; +reg dat_updt_d3; +reg [5:0] data_bank; +reg [5:0] data_batch; +reg [17:0] data_entries; +reg [13:0] data_height; +reg [10:0] data_surface; +reg [15:0] data_width; +reg [14:0] data_width_sub_one; +reg dbg_is_last_reuse; +////: my $dmaif=NVDLA_CDMA_DMAIF_BW; +////: my $atmm = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_CDMA_BPE; ##atomic_m BW +////: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +////: foreach my $k (0..$M-1) { +////: print qq( +////: reg [7:0] dc2sbuf_p${k}_rd_addr; +////: reg dc2sbuf_p${k}_rd_en; +////: ); +////: } +//reg [1:0] dc2status_state; +reg [14:0] dc_entry_onfly; +reg dc_rd_latency_cen; +reg dc_rd_latency_clr; +reg dc_rd_latency_dec; +reg dc_rd_latency_inc; +reg dc_rd_stall_cen; +reg dc_rd_stall_clr; +reg dc_rd_stall_inc; +reg [4:0] delay_cnt; +wire [3:0] dma_rsp_size; +reg [3:0] dma_rsp_size_cnt; +//reg [31:0] dp2reg_dc_rd_latency; +//reg [31:0] dp2reg_dc_rd_stall; +reg [17:0] entry_per_batch_d2; +reg [11:0] fetch_grain; +reg [14:0] idx_base; +reg [17:0] idx_batch_offset; +reg [17:0] idx_ch_offset; +reg [17:0] idx_grain_offset; +reg mon_idx_grain_offset; +reg [17:0] idx_h_offset; +reg is_blocking; +reg is_req_grain_last_d1; +reg is_req_grain_last_d2; +reg [4:0] last_data_bank; +reg last_dc; +reg last_skip_data_rls; +reg ltc_1_adv; +reg [8:0] ltc_1_cnt_cur; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg ltc_2_adv; +reg [31:0] ltc_2_cnt_cur; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg [1:0] nxt_state; +reg [8:0] outs_dp2reg_dc_rd_latency; +reg pending_req; +reg pending_req_d1; +//bw of below two signals +reg [0:0] pre_gen_sel; +reg [0:0] req_csm_sel; +//: foreach my $i (0..1){ +//: print qq( +//: wire pre_reg_en_d2_g${i}; +//: reg [13:0] req_atomic_${i}_d3; +//: reg [17:0] req_entry_${i}_d3; +//: reg req_pre_valid_${i}_d3; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire pre_reg_en_d2_g0; +reg [13:0] req_atomic_0_d3; +reg [17:0] req_entry_0_d3; +reg req_pre_valid_0_d3; + +wire pre_reg_en_d2_g1; +reg [13:0] req_atomic_1_d3; +reg [17:0] req_entry_1_d3; +reg req_pre_valid_1_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg pre_valid_d1; +reg pre_valid_d2; +reg [13:0] req_atm_cnt_0; +reg [13:0] req_atm_cnt_1; +reg [13:0] req_atm_cnt_2; +reg [13:0] req_atm_cnt_3; +reg [1:0] req_atm_sel; +reg [13:0] req_atomic_d2; +reg [4:0] req_batch_cnt; +reg [10:0] req_ch_cnt; +reg mon_req_ch_cnt; +reg [1:0] req_ch_idx_d1; +reg [2:0] req_cur_ch; +reg [13:0] req_cur_grain_d1; +reg [13:0] req_cur_grain_d2; +reg [13:0] req_height_cnt_d1; +reg [3:0] req_size_d1; +reg [2:0] req_size_out_d1; +reg req_valid_d1; +reg [13:0] rsp_all_h_cnt; +reg [4:0] rsp_batch_cnt; +reg [17:0] rsp_batch_entry_init; +reg [17:0] rsp_batch_entry_last; +reg [10:0] rsp_ch_cnt; +reg mon_rsp_ch_cnt; +reg [2:0] rsp_cur_ch; +reg [11:0] rsp_cur_grain; +//reg [17:0] req_entry_0_d3; +//reg [17:0] req_entry_1_d3; +reg [17:0] rsp_entry_init; +reg [17:0] rsp_entry_last; +reg [11:0] rsp_h_cnt; +reg rsp_rd_ch2ch3; +reg [13:0] rsp_slice_init; +reg [13:0] rsp_slice_last; +reg [15:0] rsp_w_cnt; +reg mon_rsp_w_cnt; +reg [1:0] slcg_dc_gate_d1; +reg [1:0] slcg_dc_gate_d2; +reg [1:0] slcg_dc_gate_d3; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire [15:0] cbuf_idx_inc; +wire [16:0] cbuf_idx_w; +wire cbuf_is_ready_w; +wire cbuf_wr_en_d0; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: wire [${k}-1:0] cbuf_wr_hsel_w; +//: reg [${k}-1:0] cbuf_wr_hsel; +//: wire [${k}-1:0] cbuf_wr_hsel_d0; +//: reg [${k}-1:0] cbuf_wr_hsel_d1; +//: reg [${k}-1:0] cbuf_wr_hsel_d2; +//: reg [${k}-1:0] cbuf_wr_hsel_d3; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [11:0] cbuf_wr_info_pd; +wire [11:0] cbuf_wr_info_pd_d0; +wire ch0_aval; +wire [1:0] ch0_cnt_add; +wire [2:0] ch0_cnt_sub; +wire [7:0] ch0_p0_rd_addr; +wire [7:0] ch0_p0_wr_addr; +wire [7:0] ch0_p1_rd_addr; +wire [7:0] ch0_p1_wr_addr; +wire ch0_rd_addr_cnt_reg_en; +wire ch0_wr_addr_cnt_reg_en; +wire ch1_aval; +wire [1:0] ch1_cnt_add; +wire [2:0] ch1_cnt_sub; +wire [4:0] ch1_cnt_w; +wire [7:0] ch1_p0_wr_addr; +wire [7:0] ch1_p0_rd_addr; +wire [7:0] ch1_p1_rd_addr; +wire [7:0] ch1_p1_wr_addr; +wire ch1_rd_addr_cnt_reg_en; +wire ch1_wr_addr_cnt_reg_en; +wire ch2_aval; +wire [1:0] ch2_cnt_add; +wire [2:0] ch2_cnt_sub; +wire [4:0] ch2_cnt_w; +wire [7:0] ch2_p0_rd_addr; +wire [7:0] ch2_p0_wr_addr; +wire [7:0] ch2_p1_wr_addr; +wire ch2_rd_addr_cnt_reg_en; +wire ch2_wr_addr_cnt_reg_en; +wire ch3_aval; +wire [1:0] ch3_cnt_add; +wire [2:0] ch3_cnt_sub; +wire [4:0] ch3_cnt_w; +wire [7:0] ch3_p0_wr_addr; +wire [7:0] ch3_p0_rd_addr; +wire [7:0] ch3_p1_wr_addr; +wire ch3_rd_addr_cnt_reg_en; +wire ch3_wr_addr_cnt_reg_en; +wire csm_reg_en; +wire cur_atm_done; +wire [17:0] data_entries_w; +wire [13:0] data_height_w; +wire [10:0] data_surface_inc; +wire [10:0] data_surface_w; +wire [14:0] data_width_sub_one_w; +wire dbg_is_last_reuse_w; +wire [1:0] dc2status_state_w; +wire dc_en; +wire [14:0] dc_entry_onfly_add; +wire [14:0] dc_entry_onfly_sub; +wire [14:0] dc_entry_onfly_w; +wire [4:0] delay_cnt_end; +wire [63:0] dma_rd_req_addr_f; +wire [32 -1:0] dma_rd_req_addr; +wire [( 32 + 15 )-1:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [15:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: print qq( +//: wire [${dmaif}+${M}-1:0] dma_rd_rsp_pd; +//: wire [${dmaif}-1:0] dma_rd_rsp_data; +//: ); +//: print qq( +//: wire [${M}-1:0] dma_rd_rsp_mask; +//: ); +//: foreach my $k (0..$M-1) { +//: print qq( wire [${atmm}-1:0] dma_rsp_data_p${k}; \n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [64+1-1:0] dma_rd_rsp_pd; +wire [64-1:0] dma_rd_rsp_data; + +wire [1-1:0] dma_rd_rsp_mask; + wire [64-1:0] dma_rsp_data_p0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [5:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire [1:0] dma_rsp_ch_idx; +wire [5:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire [3:0] dma_rsp_size_cnt_inc; +wire [3:0] dma_rsp_size_cnt_w; +wire dp2reg_dc_rd_stall_dec; +wire [17:0] entry_per_batch; +wire [17:0] entry_required; +wire fetch_done; +wire [11:0] fetch_grain_w; +wire [17:0] idx_batch_offset_w; +wire [17:0] idx_ch_offset_w; +wire [17:0] idx_h_offset_w; +wire [14:0] idx_w_offset_add; +wire [3:0] is_atm_done; +wire is_cbuf_idx_wrap; +wire is_data_normal; +wire is_dc; +wire is_done; +wire is_feature; +wire is_first_running; +wire is_free_entries_enough; +wire is_idle; +wire is_nxt_running; +wire is_packed_1x1; +wire is_pending; +wire is_req_atm_end; +wire is_req_atm_sel_end; +wire is_req_batch_end; +wire is_req_ch_end; +wire is_req_grain_last; +wire is_rsp_all_h_end; +wire is_rsp_batch_end; +wire is_rsp_ch0; +wire is_rsp_ch1; +wire is_rsp_ch2; +wire is_rsp_ch3; +wire is_rsp_ch_end; +wire is_rsp_done; +wire is_rsp_h_end; +wire is_rsp_w_end; +wire is_running; +wire is_w_cnt_div2; +wire is_w_cnt_div4; +wire layer_st; +wire ltc_1_dec; +wire ltc_1_inc; +wire ltc_2_dec; +wire ltc_2_inc; +wire mode_match; +wire [2:0] mon_cbuf_idx_inc; +wire [1:0] mon_cbuf_idx_w; +wire mon_ch1_cnt_w; +wire mon_ch2_cnt_w; +wire mon_ch3_cnt_w; +wire mon_data_entries_w; +wire mon_dc_entry_onfly_w; +wire mon_dma_rsp_size_cnt_inc; +wire [5:0] mon_entry_per_batch; +wire [13:0] mon_entry_required; +wire mon_fetch_grain_w; +wire mon_idx_batch_offset_w; +wire mon_idx_ch_offset_w; +wire mon_idx_h_offset_w; +wire mon_req_addr; +wire mon_req_addr_base_inc; +wire mon_req_addr_batch_base_inc; +wire mon_req_addr_ch_base_inc; +wire mon_req_addr_grain_base_inc; +wire mon_req_atm_cnt_inc; +wire mon_req_atm_left; +wire mon_req_atm_size_addr_limit; +wire [1:0] mon_req_atm_size_out; +wire mon_req_ch_left_w; +wire [15:0] mon_req_cur_atomic; +reg mon_req_height_cnt_d1; +wire mon_req_slice_left; +wire mon_rsp_all_h_cnt_inc; +wire mon_rsp_all_h_left_w; +wire mon_rsp_ch_cnt_inc; +wire mon_rsp_ch_left_w; +wire need_pending; +reg [2:0] rsp_rd_more_atmm; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: print qq( +//: wire p${k}_wr_en; +//: wire [7:0] p${k}_wr_addr; +//: wire p${k}_rd_en_w; +//: reg [7:0] p${k}_rd_addr_w; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire p0_wr_en; +wire [7:0] p0_wr_addr; +wire p0_rd_en_w; +reg [7:0] p0_rd_addr_w; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire pending_req_end; +wire pre_ready; +wire pre_ready_d1; +wire pre_ready_d2; +wire pre_reg_en; +wire pre_reg_en_d1; +wire pre_reg_en_d2; +wire pre_reg_en_d2_init; +wire pre_reg_en_d2_last; +wire rd_req_rdyi; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: wire [63-${atmbw}:0] req_addr; +//: reg [63-${atmbw}:0] req_addr_d1; +//: wire [63-${atmbw}:0] req_addr_base_inc; +//: wire [63-${atmbw}:0] req_addr_base_w; +//: reg [63-${atmbw}:0] req_addr_base; +//: wire [63-${atmbw}:0] req_addr_batch_base_inc; +//: wire [63-${atmbw}:0] req_addr_batch_base_w; +//: wire [63-${atmbw}:0] req_addr_ori; +//: wire [63-${atmbw}:0] req_addr_ch_base_inc; +//: wire [63-${atmbw}:0] req_addr_ch_base_w; +//: wire [63-${atmbw}:0] req_addr_grain_base_inc; +//: wire [63-${atmbw}:0] req_addr_grain_base_w; +//: reg [63-${atmbw}:0] req_addr_batch_base; +//: reg [63-${atmbw}:0] req_addr_ch_base; +//: reg [63-${atmbw}:0] req_addr_grain_base; +//: wire [12+31-${atmbw}:0] grain_addr_w; +//: reg [12+31-${atmbw}:0] grain_addr; +//: wire [2+31-${atmbw}:0] req_addr_ch_base_add; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [63-3:0] req_addr; +reg [63-3:0] req_addr_d1; +wire [63-3:0] req_addr_base_inc; +wire [63-3:0] req_addr_base_w; +reg [63-3:0] req_addr_base; +wire [63-3:0] req_addr_batch_base_inc; +wire [63-3:0] req_addr_batch_base_w; +wire [63-3:0] req_addr_ori; +wire [63-3:0] req_addr_ch_base_inc; +wire [63-3:0] req_addr_ch_base_w; +wire [63-3:0] req_addr_grain_base_inc; +wire [63-3:0] req_addr_grain_base_w; +reg [63-3:0] req_addr_batch_base; +reg [63-3:0] req_addr_ch_base; +reg [63-3:0] req_addr_grain_base; +wire [12+31-3:0] grain_addr_w; +reg [12+31-3:0] grain_addr; +wire [2+31-3:0] req_addr_ch_base_add; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [13:0] req_atm; +wire [13:0] req_atm_cnt; +wire [13:0] req_atm_cnt_0_w; +wire [13:0] req_atm_cnt_1_w; +wire [13:0] req_atm_cnt_2_w; +wire [13:0] req_atm_cnt_3_w; +wire [13:0] req_atm_cnt_inc; +wire [13:0] req_atm_left; +wire req_atm_reg_en; +wire req_atm_reg_en_0; +wire req_atm_reg_en_1; +wire req_atm_reg_en_2; +wire req_atm_reg_en_3; +wire [3:0] req_atm_size; +wire [3:0] req_atm_size_addr_limit; +wire [2:0] req_atm_size_out; +wire req_batch_reg_en; +wire [10:0] req_ch_left_w; +wire [2:0] req_ch_mode; +wire req_ch_reg_en; +wire [13:0] req_cur_atomic; +wire [13:0] req_cur_grain_w; +wire [14:0] req_entry; +wire req_grain_reg_en; +wire req_pre_valid; +wire req_pre_valid_0_w; +wire req_pre_valid_1_w; +wire req_ready_d0; +wire req_ready_d1; +wire req_reg_en; +wire [13:0] req_slice_left; +wire req_valid_d0; +wire [15:0] required_entries; +wire [13:0] rsp_all_h_cnt_inc; +wire [13:0] rsp_all_h_left_w; +wire rsp_all_h_reg_en; +wire rsp_batch_reg_en; +wire rsp_ch0_rd_one; +wire [2:0] rsp_ch0_rd_size; +wire [10:0] rsp_ch_cnt_inc; +wire [10:0] rsp_ch_left_w; +wire [2:0] rsp_ch_mode; +wire rsp_ch_reg_en; +wire [2:0] rsp_cur_ch_w; +wire [11:0] rsp_cur_grain_w; +wire [17:0] rsp_entry; +wire rsp_h_reg_en; +reg rsp_rd_en; +wire [13:0] rsp_slice; +reg [2:0] rsp_w_cnt_add; +wire rsp_w_left1; +wire rsp_w_left2; +wire rsp_w_left3; +wire rsp_w_left4; +wire rsp_w_reg_en; +wire slcg_dc_en_w; +wire [1:0] slcg_dc_gate_w; +wire [13:0] data_width_inc; +//////////////////////////////////////////////////////////////////////// +// CDMA direct convolution data fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +//## fsm (1) defines +localparam DC_STATE_IDLE = 2'b00; +localparam DC_STATE_PEND = 2'b01; +localparam DC_STATE_BUSY = 2'b10; +localparam DC_STATE_DONE = 2'b11; +//## fsm (1) com block +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + DC_STATE_IDLE: begin + if ((dc_en & need_pending)) begin + nxt_state = DC_STATE_PEND; + end + else if ((dc_en & reg2dp_data_reuse & last_skip_data_rls & mode_match)) begin + nxt_state = DC_STATE_DONE; + end + else if (dc_en) begin + nxt_state = DC_STATE_BUSY; + end + end + DC_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = DC_STATE_BUSY; + end + end + DC_STATE_BUSY: begin + if (fetch_done) begin + nxt_state = DC_STATE_DONE; + end + end + DC_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = DC_STATE_IDLE; + end + end + endcase + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_state <= DC_STATE_IDLE; + end else begin + cur_state <= nxt_state; + end +end +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign fetch_done = is_running & is_rsp_done & (delay_cnt == delay_cnt_end); +assign delay_cnt_end = (3 + 3 + 3); // this value is related to status pipeline delay +assign need_pending = (last_data_bank != reg2dp_data_bank); +assign mode_match = dc_en & last_dc; +assign is_feature = (reg2dp_datain_format == 1'h0 ); +assign is_dc = (reg2dp_conv_mode == 1'h0 ); +assign dc_en = reg2dp_op_en & is_dc & is_feature; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + delay_cnt <= {5{1'b0}}; + end else if(~is_running)begin + delay_cnt <= {5{1'b0}}; + end else if(is_rsp_done)begin + delay_cnt <= delay_cnt + 1'b1; + end +end +`ifndef SYNTHESIS +assign dbg_is_last_reuse_w = (is_idle & (nxt_state == DC_STATE_DONE)) ? 1'b1 : + (~is_running & is_nxt_running) ? 1'b0 : + dbg_is_last_reuse; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + dbg_is_last_reuse <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + dbg_is_last_reuse <= dbg_is_last_reuse_w; + end +end +`endif +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = dc_en & is_idle; +assign is_idle = (cur_state == DC_STATE_IDLE); +assign is_pending = (cur_state == DC_STATE_PEND); +assign is_running = (cur_state == DC_STATE_BUSY); +assign is_done = (cur_state == DC_STATE_DONE); +assign is_nxt_running = (nxt_state == DC_STATE_BUSY); +assign is_first_running = ~is_running & is_nxt_running; +assign dc2status_state_w = (nxt_state == DC_STATE_PEND) ? 1 : + (nxt_state == DC_STATE_BUSY) ? 2 : + (nxt_state == DC_STATE_DONE) ? 3 : + 0 ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc2status_state <= 0; + end else begin + dc2status_state <= dc2status_state_w; + end +end +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +assign pending_req_end = pending_req_d1 & ~pending_req; +//================ Non-SLCG clock domain ================// +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_dc <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_dc <= dc_en; + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_data_bank <= {5{1'b1}}; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_data_bank <= reg2dp_data_bank; + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_skip_data_rls <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_skip_data_rls <= dc_en & reg2dp_skip_data_rls; + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req <= 1'b0; + end else begin + pending_req <= sc2cdma_dat_pending_req; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req_d1 <= 1'b0; + end else begin + pending_req_d1 <= pending_req; + end +end +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_dc_en_w = dc_en & (is_running | is_pending | is_done); +assign slcg_dc_gate_w = {2{~slcg_dc_en_w}}; +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_dc_gate_d1 <= {2{1'b1}}; + end else begin + slcg_dc_gate_d1 <= slcg_dc_gate_w; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_dc_gate_d2 <= {2{1'b1}}; + end else begin + slcg_dc_gate_d2 <= slcg_dc_gate_d1; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_dc_gate_d3 <= {2{1'b1}}; + end else begin + slcg_dc_gate_d3 <= slcg_dc_gate_d2; + end +end +assign slcg_dc_gate_wg = slcg_dc_gate_d3[0]; +assign slcg_dc_gate_img = slcg_dc_gate_d3[1]; +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: if($atmbw > 3){ +//: print qq( +//: assign data_width_sub_one_w = (is_packed_1x1) ? {{(2+${atmbw}){1'b0}}, reg2dp_datain_channel[12:${atmbw}]} : {2'b0, reg2dp_datain_width}; +//: assign data_surface_inc = {{(${atmbw}-3){1'b0}}, reg2dp_datain_channel[12:${atmbw}]} + 1'b1; +//: ); +//:} +//: else { +//: print qq( +//: assign data_width_sub_one_w = (is_packed_1x1) ? {{(2+${atmbw}){1'b0}}, reg2dp_datain_channel[12:${atmbw}]} : {2'b0, reg2dp_datain_width}; +//: assign data_surface_inc = {reg2dp_datain_channel[12:${atmbw}]} + 1'b1; +//: ); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign data_width_sub_one_w = (is_packed_1x1) ? {{(2+3){1'b0}}, reg2dp_datain_channel[12:3]} : {2'b0, reg2dp_datain_width}; +assign data_surface_inc = {reg2dp_datain_channel[12:3]} + 1'b1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// assign is_data_expand = 1'b0; +//assign is_data_shrink = 1'b0; +assign is_data_normal = 1'b1; +assign is_packed_1x1 = (reg2dp_datain_width == 13'b0) & (reg2dp_datain_height == 13'b0) & reg2dp_surf_packed; +assign data_width_inc = reg2dp_datain_width + 1'b1; +//assign data_width_w = is_packed_1x1 ? {6'b0, data_surface_inc} : {2'b0, data_width_inc}; +assign data_height_w = reg2dp_datain_height + 1'b1; +assign {mon_data_entries_w, data_entries_w} = reg2dp_entries + 1'b1; +assign data_surface_w = is_packed_1x1 ? 11'b1 : data_surface_inc; +assign {mon_fetch_grain_w, fetch_grain_w} = (~reg2dp_line_packed) ? 13'b1 : reg2dp_grains + 1'b1; +assign grain_addr_w = fetch_grain_w * reg2dp_line_stride; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width <= {16{1'b0}}; + end else begin + if (layer_st) begin + if(is_packed_1x1) + data_width <= {5'b0, data_surface_inc} ; + else + data_width <= {2'b0, data_width_inc}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width_sub_one <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_width_sub_one <= data_width_sub_one_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_height <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_height <= data_height_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_batch <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_batch <= reg2dp_batches + 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_entries <= 0; + end else begin + if ((layer_st) == 1'b1) begin + data_entries <= data_entries_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + fetch_grain <= {12{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + fetch_grain <= fetch_grain_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_surface <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_surface <= data_surface_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grain_addr <= 0; + end else begin + if ((layer_st) == 1'b1) begin + grain_addr <= grain_addr_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_bank <= reg2dp_data_bank + 1'b1; + end + end +end +//////////////////////////////////////////////////////////////////////// +// prepare for address generation // +//////////////////////////////////////////////////////////////////////// +///////////// stage 1 ///////////// +assign pre_ready = ~pre_valid_d1 | pre_ready_d1; +assign pre_reg_en = is_running & (req_height_cnt_d1 != data_height) & pre_ready; +assign {mon_req_slice_left, req_slice_left} = data_height - req_height_cnt_d1; +assign is_req_grain_last = (req_slice_left <= {2'd0,fetch_grain}); +assign req_cur_grain_w = is_req_grain_last ? req_slice_left : {2'd0,fetch_grain}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_req_height_cnt_d1,req_height_cnt_d1} <= {15{1'b0}}; + end else if(layer_st) begin + {mon_req_height_cnt_d1,req_height_cnt_d1} <= {15{1'b0}}; + end else if (pre_reg_en) begin + {mon_req_height_cnt_d1,req_height_cnt_d1} <= req_height_cnt_d1 + req_cur_grain_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_cur_grain_d1 <= {14{1'b0}}; + end else begin + if ((pre_reg_en) == 1'b1) begin + req_cur_grain_d1 <= req_cur_grain_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_req_grain_last_d1 <= 1'b0; + end else begin + if ((pre_reg_en) == 1'b1) begin + is_req_grain_last_d1 <= is_req_grain_last; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_valid_d1 <= 1'b0; + end else if(~is_running)begin + pre_valid_d1 <= 1'b0; + end else begin + if(req_height_cnt_d1 != data_height) + pre_valid_d1 <= 1'b1; + else if(pre_ready_d1) + pre_valid_d1 <= 1'b0; + end +end +///////////// stage 2 ///////////// +assign {mon_req_cur_atomic, req_cur_atomic} = req_cur_grain_d1 * data_width; +assign {mon_entry_per_batch, entry_per_batch} = data_entries * data_batch; +assign pre_ready_d1 = ~pre_valid_d2 | pre_ready_d2; +assign pre_reg_en_d1 = pre_valid_d1 & pre_ready_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atomic_d2 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + req_atomic_d2 <= req_cur_atomic; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + entry_per_batch_d2 <= 0; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + entry_per_batch_d2 <= entry_per_batch; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_cur_grain_d2 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + req_cur_grain_d2 <= req_cur_grain_d1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_req_grain_last_d2 <= 1'b0; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + is_req_grain_last_d2 <= is_req_grain_last_d1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_valid_d2 <= 1'b0; + end else if(~is_running)begin + pre_valid_d2 <= 1'b0; + end else begin + if(pre_valid_d1) + pre_valid_d2 <= 1'b1; + else if(pre_ready_d2) + pre_valid_d2 <= 1'b0; + end +end +///////////// stage 3 ///////////// +assign {mon_entry_required, entry_required} = req_cur_grain_d2 * entry_per_batch_d2; +assign pre_reg_en_d2_g0 = pre_valid_d2 & ~pre_gen_sel & ~req_pre_valid_0_d3; +assign pre_reg_en_d2_g1 = pre_valid_d2 & pre_gen_sel & ~req_pre_valid_1_d3; +assign pre_ready_d2 = ((~pre_gen_sel & ~req_pre_valid_0_d3) | (pre_gen_sel & ~req_pre_valid_1_d3)); +assign pre_reg_en_d2 = pre_valid_d2 & pre_ready_d2; +assign pre_reg_en_d2_init = pre_valid_d2 & pre_ready_d2 & ~is_req_grain_last_d2; +assign pre_reg_en_d2_last = pre_valid_d2 & pre_ready_d2 & is_req_grain_last_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atomic_0_d3 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_g0) == 1'b1) begin + req_atomic_0_d3 <= req_atomic_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atomic_1_d3 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_g1) == 1'b1) begin + req_atomic_1_d3 <= req_atomic_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_entry_0_d3 <= 0; + end else begin + if ((pre_reg_en_d2_g0) == 1'b1) begin + req_entry_0_d3 <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_entry_1_d3 <= 0; + end else begin + if ((pre_reg_en_d2_g1) == 1'b1) begin + req_entry_1_d3 <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_entry_init <= 0; + end else begin + if ((pre_reg_en_d2_init) == 1'b1) begin + rsp_entry_init <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_entry_last <= 0; + end else begin + if ((pre_reg_en_d2_last) == 1'b1) begin + rsp_entry_last <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_batch_entry_init <= 0; + end else begin + if ((pre_reg_en_d2_init) == 1'b1) begin + rsp_batch_entry_init <= entry_per_batch_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_batch_entry_last <= 0; + end else begin + if ((pre_reg_en_d2_last) == 1'b1) begin + rsp_batch_entry_last <= entry_per_batch_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_slice_init <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_init) == 1'b1) begin + rsp_slice_init <= req_cur_grain_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_slice_last <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_last) == 1'b1) begin + rsp_slice_last <= req_cur_grain_d2; + end + end +end +///////////// prepare control logic ///////////// +// assign pre_gen_sel_w = is_running & (pre_valid_d2 ^ pre_gen_sel); +// assign req_csm_sel_w = is_running & ~req_csm_sel; +assign req_pre_valid_0_w = ~is_running ? 1'b0 : + (pre_reg_en_d2_g0) ? 1'b1 : + (~req_csm_sel & csm_reg_en) ? 1'b0 : req_pre_valid_0_d3; +assign req_pre_valid_1_w = ~is_running ? 1'b0 : + (pre_reg_en_d2_g1) ? 1'b1 : + (req_csm_sel & csm_reg_en) ? 1'b0 : req_pre_valid_1_d3; +assign csm_reg_en = req_grain_reg_en; +assign req_pre_valid = ~req_csm_sel ? req_pre_valid_0_d3 : req_pre_valid_1_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_gen_sel <= 0; + end else if(~is_running) begin + pre_gen_sel <= 0; + end else if (pre_reg_en_d2) begin + pre_gen_sel <= pre_gen_sel + 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_csm_sel <= 0; + end else if(~is_running) begin + req_csm_sel <= 0; + end else if (csm_reg_en) begin + req_csm_sel <= req_csm_sel + 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pre_valid_0_d3 <= 1'b0; + end else begin + req_pre_valid_0_d3 <= req_pre_valid_0_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pre_valid_1_d3 <= 1'b0; + end else begin + req_pre_valid_1_d3 <= req_pre_valid_1_w; + end +end +//////////////////////////////////////////////////////////////////////// +// generate address for input feature data // +//////////////////////////////////////////////////////////////////////// +///////////// batch counter ///////////// +// assign {mon_req_batch_cnt_inc, +// req_batch_cnt_inc} = req_batch_cnt + 1'b1; +// assign req_batch_cnt_w = (is_req_batch_end) ? 5'b0 : +// req_batch_cnt_inc; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_batch_cnt <= {5{1'b0}}; + end else if(layer_st) begin + req_batch_cnt <= {5{1'b0}}; + end else begin + if (req_batch_reg_en) begin + if(is_req_batch_end) + req_batch_cnt <= {5{1'b0}}; + else + req_batch_cnt <= req_batch_cnt + 1'b1; + end + end +end +assign is_req_batch_end = (req_batch_cnt == reg2dp_batches); +///////////// channel counter ///////////// +assign req_ch_mode = is_packed_1x1 ? 3'h1 : + /*is_data_shrink ? 3'h4 : */ +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc); +//: my $k; +//: if($m > 1){$k=$atmc;} +//: else {$k=$dmaif;} +//: print qq( +//: 3'h${k}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +3'h1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_req_ch_left_w,req_ch_left_w} = (layer_st | is_req_ch_end) ? {1'b0,data_surface_w} : (data_surface - req_ch_cnt) - {8'd0,req_cur_ch}; +// assign req_cur_ch_w = (req_ch_left_w > {{8{1'b0}}, req_ch_mode}) ? req_ch_mode : req_ch_left_w[2:0]; +// assign {mon_req_ch_cnt_inc, +// req_ch_cnt_inc} = req_ch_cnt + req_cur_ch; +// assign is_req_ch_end = (req_ch_cnt_inc == data_surface); +// assign req_ch_cnt_w = (layer_st | is_req_ch_end) ? 10'b0 : +// req_ch_cnt_inc; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_req_ch_cnt,req_ch_cnt} <= {12{1'b0}}; + end else if(layer_st) begin + {mon_req_ch_cnt,req_ch_cnt} <= {12{1'b0}}; + end else begin + if (req_ch_reg_en) begin + if(is_req_ch_end) + {mon_req_ch_cnt,req_ch_cnt} <= {12{1'b0}}; + else + {mon_req_ch_cnt,req_ch_cnt} <= req_ch_cnt + {8'd0, req_cur_ch}; + end + end +end +//assign is_req_ch_end = (req_ch_cnt == (data_surface-req_cur_ch)); +wire [10:0] data_surface_dec; +wire mon_data_surface_dec; +assign {mon_data_surface_dec,data_surface_dec} = data_surface-{8'd0,req_cur_ch}; +assign is_req_ch_end = (req_ch_cnt == data_surface_dec); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_cur_ch <= {3{1'b0}}; + end else begin + if (layer_st | req_ch_reg_en) begin + if(req_ch_left_w > {{8{1'b0}}, req_ch_mode}) + req_cur_ch <= req_ch_mode; + else + req_cur_ch <= req_ch_left_w[2:0]; + end + end +end +///////////// atomic counter ///////////// +// assign req_atm_sel_inc = req_atm_sel + 1'b1; +// assign is_req_atm_sel_end = (req_atm_sel_inc == req_cur_ch); +// assign req_atm_sel_w = ~is_running ? 1'b0 : +// (is_req_atm_sel_end | is_req_atm_end) ? 2'b0: +// req_atm_sel_inc[1:0]; +assign is_req_atm_end = ((req_cur_ch == 3'h1) & (&is_atm_done[ 0])) + | ((req_cur_ch == 3'h2) & (&is_atm_done[1:0])) + | ((req_cur_ch == 3'h3) & (&is_atm_done[2:0])) + | ((req_cur_ch == 3'h4) & (&is_atm_done[3:0])); +assign req_atm = req_csm_sel ? req_atomic_1_d3 : req_atomic_0_d3; +assign is_atm_done[0] = (req_atm_cnt_0 == req_atm); +assign is_atm_done[1] = (req_atm_cnt_1 == req_atm); +assign is_atm_done[2] = (req_atm_cnt_2 == req_atm); +assign is_atm_done[3] = (req_atm_cnt_3 == req_atm); +assign req_atm_cnt = (req_atm_sel == 2'h0) ? req_atm_cnt_0 : + (req_atm_sel == 2'h1) ? req_atm_cnt_1 : + (req_atm_sel == 2'h2) ? req_atm_cnt_2 : + (req_atm_sel == 2'h3) ? req_atm_cnt_3 : 14'd0; +assign {mon_req_atm_cnt_inc, req_atm_cnt_inc} = req_atm_cnt + req_atm_size; +assign cur_atm_done = (req_atm_sel == 2'h0) ? is_atm_done[0] : + (req_atm_sel == 2'h1) ? is_atm_done[1] : + (req_atm_sel == 2'h2) ? is_atm_done[2] : + (req_atm_sel == 2'h3) ? is_atm_done[3] : 1'b0; +assign {mon_req_atm_left, req_atm_left} = req_atm - req_atm_cnt; +assign {mon_req_atm_size_addr_limit, req_atm_size_addr_limit} = (req_atm_cnt == 14'b0) ? (4'h8 - req_addr[2:0]) : 4'h8; +assign req_atm_size = (req_atm_left < {{10{1'b0}}, req_atm_size_addr_limit}) ? req_atm_left[3:0] : req_atm_size_addr_limit; +assign {mon_req_atm_size_out, req_atm_size_out} = req_atm_size - 1'b1; +assign req_atm_cnt_0_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +assign req_atm_cnt_1_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +assign req_atm_cnt_2_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +assign req_atm_cnt_3_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_sel <= {2{1'b0}}; + end else if(~is_running) begin + req_atm_sel <= {2{1'b0}}; + end else begin + if (req_atm_reg_en) begin + if(is_req_atm_sel_end | is_req_atm_end) + req_atm_sel <= {2{1'b0}}; + else + req_atm_sel <= req_atm_sel + 1'b1; + end + end +end +assign is_req_atm_sel_end = ({2'd0,req_atm_sel} == (req_cur_ch-1)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_0 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_0) == 1'b1) begin + req_atm_cnt_0 <= req_atm_cnt_0_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_1 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_1) == 1'b1) begin + req_atm_cnt_1 <= req_atm_cnt_1_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_2 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_2) == 1'b1) begin + req_atm_cnt_2 <= req_atm_cnt_2_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_3 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_3) == 1'b1) begin + req_atm_cnt_3 <= req_atm_cnt_3_w; + end + end +end +///////////// address counter ///////////// +assign req_addr_ori = {reg2dp_datain_addr_high_0, reg2dp_datain_addr_low_0}; +assign {mon_req_addr_grain_base_inc,req_addr_grain_base_inc} = req_addr_grain_base + grain_addr; +assign {mon_req_addr_batch_base_inc,req_addr_batch_base_inc} = req_addr_batch_base + reg2dp_batch_stride; +assign req_addr_ch_base_add = /*(is_data_shrink) ? {reg2dp_surf_stride, 2'b0} : */ +//{1'b0, reg2dp_surf_stride, 1'b0}; +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $k; +//: if(${dmaif} < ${atmc}) { +//: $k=$dmaif; +//: } else { +//: $k=$atmc; +//: } +//: if($k == 1) { +//: print "{2'b0, reg2dp_surf_stride}; \n"; +//: } elsif($k == 2) { +//: print "{1'b0, reg2dp_surf_stride, 1'b0}; \n"; +//: } elsif($k == 4) { +//: print "{reg2dp_surf_stride, 2'b0}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +{2'b0, reg2dp_surf_stride}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_req_addr_ch_base_inc, req_addr_ch_base_inc} = req_addr_ch_base + req_addr_ch_base_add; +assign {mon_req_addr_base_inc, req_addr_base_inc} = req_addr_base + reg2dp_surf_stride; +assign req_addr_grain_base_w = is_first_running ? req_addr_ori : req_addr_grain_base_inc; +assign req_addr_batch_base_w = is_first_running ? req_addr_ori : + is_req_batch_end ? req_addr_grain_base_inc : req_addr_batch_base_inc; +assign req_addr_ch_base_w = is_first_running ? req_addr_ori : + (is_req_ch_end & is_req_batch_end) ? req_addr_grain_base_inc : + is_req_ch_end ? req_addr_batch_base_inc : req_addr_ch_base_inc; +assign req_addr_base_w = is_first_running ? req_addr_ori : + (is_req_atm_end & is_req_ch_end & is_req_batch_end) ? req_addr_grain_base_inc : + (is_req_atm_end & is_req_ch_end) ? req_addr_batch_base_inc : + is_req_atm_end ? req_addr_ch_base_inc : + is_req_atm_sel_end ? req_addr_ch_base : req_addr_base_inc; +assign {mon_req_addr, req_addr} = req_addr_base + req_atm_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_grain_base <= 0; + end else if ((is_first_running | req_grain_reg_en) == 1'b1) begin + req_addr_grain_base <= req_addr_grain_base_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_batch_base <= 0; + end else begin + if ((is_first_running | req_batch_reg_en) == 1'b1) begin + req_addr_batch_base <= req_addr_batch_base_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_ch_base <= 0; + end else begin + if ((is_first_running | req_ch_reg_en) == 1'b1) begin + req_addr_ch_base <= req_addr_ch_base_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_base <= 0; + end else begin + if ((is_first_running | req_atm_reg_en) == 1'b1) begin + req_addr_base <= req_addr_base_w; + end + end +end +///////////// request package ///////////// +assign req_valid_d0 = is_running & req_pre_valid & cbuf_is_ready & ~cur_atm_done; +// assign req_valid_d1_w = ~is_running ? 1'b0 : +// req_valid_d0 ? 1'b1 : +// req_ready_d1 ? 1'b0 : +// req_valid_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_valid_d1 <= 1'b0; + end else if(~is_running) begin + req_valid_d1 <= 1'b0; + end else if(req_valid_d0) begin + req_valid_d1 <= 1'b1; + end else if(req_ready_d1) begin + req_valid_d1 <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_d1 <= 0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_addr_d1 <= req_addr; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_d1 <= {4{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_size_d1 <= req_atm_size; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_out_d1 <= {3{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_size_out_d1 <= req_atm_size_out; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_ch_idx_d1 <= {2{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_ch_idx_d1 <= req_atm_sel; + end + end +end +///////////// control logic ///////////// +assign req_ready_d1 = dma_req_fifo_ready & dma_rd_req_rdy; +assign req_ready_d0 = req_ready_d1 | ~req_valid_d1; +assign req_reg_en = req_pre_valid & cbuf_is_ready & ~cur_atm_done & req_ready_d0; +assign req_atm_reg_en = req_pre_valid & cbuf_is_ready & (cur_atm_done | req_ready_d0); +assign req_atm_reg_en_0 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h0) & ~is_atm_done[0] & req_ready_d0)); +assign req_atm_reg_en_1 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h1) & ~is_atm_done[1] & req_ready_d0)); +assign req_atm_reg_en_2 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h2) & ~is_atm_done[2] & req_ready_d0)); +assign req_atm_reg_en_3 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h3) & ~is_atm_done[2] & req_ready_d0)); +//When is_req_atm_end is set, we don't need to wait cbuf_is_ready; +assign req_ch_reg_en = req_pre_valid & is_req_atm_end; +assign req_batch_reg_en = req_pre_valid & is_req_atm_end & is_req_ch_end; +assign req_grain_reg_en = req_pre_valid & is_req_atm_end & is_req_ch_end & is_req_batch_end; +//////////////////////////////////////////////////////////////////////// +// CDMA DC read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_datain_ram_type) + ,.mcif_rd_req_pd (dc_dat2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (dc_dat2mcif_rd_req_valid) + ,.mcif_rd_req_ready (dc_dat2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2dc_dat_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2dc_dat_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2dc_dat_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////// +assign dma_rd_req_pd[32 -1:0] = dma_rd_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_rd_req_size[14:0]; +assign dma_rd_req_vld = dma_req_fifo_ready & req_valid_d1; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: my $k = 32; +//: print "assign dma_rd_req_addr_f = {req_addr_d1, ${atmbw}'d0}; \n"; +//: print "assign dma_rd_req_addr = dma_rd_req_addr_f[${k}-1:0]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dma_rd_req_addr_f = {req_addr_d1, 3'd0}; +assign dma_rd_req_addr = dma_rd_req_addr_f[32-1:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rd_req_size = {{13{1'b0}}, req_size_out_d1}; +assign dma_rd_req_type = reg2dp_datain_ram_type; +assign dma_rd_rsp_rdy = ~is_blocking; +NV_NVDLA_CDMA_DC_fifo u_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[5:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w + ,.rd_data (dma_rsp_fifo_data[5:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = req_valid_d1 & dma_rd_req_rdy; +assign dma_req_fifo_data = {req_ch_idx_d1, req_size_d1}; +//////////////////////////////////////////////////////////////////////// +// CDMA DC read response connection // +//////////////////////////////////////////////////////////////////////// +////: my $dmaif=NVDLA_CDMA_DMAIF_BW; +////: my $atmm = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_CDMA_BPE; ##atomic_m BW +////: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +////: print qq( +////: assign dma_rd_rsp_data[${dmaif}-1:0] = dma_rd_rsp_pd[${dmaif}-1:0]; +////: ); +////: if($M>1) { +////: print qq( +////: assign dma_rd_rsp_mask[${M}-1:0] = dma_rd_rsp_pd[${dmaif}+${M}-1:${dmaif}]; +////: ); +////: } +assign dma_rd_rsp_data[64 -1:0] = dma_rd_rsp_pd[64 -1:0]; +assign dma_rd_rsp_mask[( 64 + (64/8/8) )-64 -1:0] = dma_rd_rsp_pd[( 64 + (64/8/8) )-1:64]; +assign {dma_rsp_ch_idx, dma_rsp_size} = dma_rsp_fifo_data; +wire [1:0] active_atom_num; +assign active_atom_num = 2'd0 +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1){ +//: print qq( +//: + dma_rd_rsp_mask[$k] +//: ); +//: } +//: print "; "; +//| eperl: generated_beg (DO NOT EDIT BELOW) + ++ dma_rd_rsp_mask[0] +; +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_dma_rsp_size_cnt_inc,dma_rsp_size_cnt_inc} = dma_rsp_size_cnt + active_atom_num; +assign { +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: if($M>1) { +//: foreach my $k (0..$M-2){ +//: my $i = $M -$k -1; +//: print qq( dma_rsp_data_p${i}, ); +//: } +//: } +//: print qq( dma_rsp_data_p0} = dma_rd_rsp_data; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + dma_rsp_data_p0} = dma_rd_rsp_data; +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 4'b0 : dma_rsp_size_cnt_inc; +assign dma_rsp_fifo_ready = (dma_rd_rsp_vld & ~is_blocking & (dma_rsp_size_cnt_inc == dma_rsp_size)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rsp_size_cnt <= {4{1'b0}}; + end else begin + if ((dma_rd_rsp_vld & ~is_blocking) == 1'b1) begin + dma_rsp_size_cnt <= dma_rsp_size_cnt_w; + end + end +end +//////////////////////////////////////////////////////////////////////// +// DC read data to shared buffer // +//////////////////////////////////////////////////////////////////////// +assign is_rsp_ch0 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h0); +assign is_rsp_ch1 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h1); +assign is_rsp_ch2 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h2); +assign is_rsp_ch3 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h3); +assign ch0_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch0; +assign ch1_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch1; +assign ch2_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch2; +assign ch3_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch0_p0_wr_addr_cnt,ch0_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch0_p1_wr_addr_cnt,ch0_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch0_p0_wr_addr_cnt,ch0_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch0_p1_wr_addr_cnt,ch0_p1_wr_addr_cnt} <= 7'b1; + end else if(ch0_wr_addr_cnt_reg_en) begin + {mon_ch0_p0_wr_addr_cnt,ch0_p0_wr_addr_cnt} <= ch0_p0_wr_addr_cnt + {4'd0, active_atom_num}; + {mon_ch0_p1_wr_addr_cnt,ch0_p1_wr_addr_cnt} <= ch0_p1_wr_addr_cnt + {4'd0, active_atom_num}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch1_p0_wr_addr_cnt,ch1_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch1_p1_wr_addr_cnt,ch1_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch1_p0_wr_addr_cnt,ch1_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch1_p1_wr_addr_cnt,ch1_p1_wr_addr_cnt} <= 7'b1; + end else if (ch1_wr_addr_cnt_reg_en)begin + {mon_ch1_p0_wr_addr_cnt,ch1_p0_wr_addr_cnt} <= ch1_p0_wr_addr_cnt + {4'd0,active_atom_num}; + {mon_ch1_p1_wr_addr_cnt,ch1_p1_wr_addr_cnt} <= ch1_p1_wr_addr_cnt + {4'd0,active_atom_num}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch2_p0_wr_addr_cnt,ch2_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch2_p1_wr_addr_cnt,ch2_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch2_p0_wr_addr_cnt,ch2_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch2_p1_wr_addr_cnt,ch2_p1_wr_addr_cnt} <= 7'b1; + end else if (ch2_wr_addr_cnt_reg_en) begin + {mon_ch2_p0_wr_addr_cnt,ch2_p0_wr_addr_cnt} <= ch2_p0_wr_addr_cnt + {4'd0, active_atom_num}; + {mon_ch2_p1_wr_addr_cnt,ch2_p1_wr_addr_cnt} <= ch2_p1_wr_addr_cnt + {4'd0, active_atom_num}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch3_p0_wr_addr_cnt,ch3_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch3_p1_wr_addr_cnt,ch3_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch3_p0_wr_addr_cnt,ch3_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch3_p1_wr_addr_cnt,ch3_p1_wr_addr_cnt} <= 7'b1; + end else if (ch3_wr_addr_cnt_reg_en) begin + {mon_ch3_p0_wr_addr_cnt,ch3_p0_wr_addr_cnt} <= ch3_p0_wr_addr_cnt + {4'd0, active_atom_num}; + {mon_ch3_p1_wr_addr_cnt,ch3_p1_wr_addr_cnt} <= ch3_p1_wr_addr_cnt + {4'd0, active_atom_num}; + end +end +assign ch0_p0_wr_addr = {2'h0, ch0_p0_wr_addr_cnt[0], ch0_p0_wr_addr_cnt[8 -3:1]}; +assign ch0_p1_wr_addr = {2'h0, ch0_p1_wr_addr_cnt[0], ch0_p1_wr_addr_cnt[8 -3:1]}; +assign ch1_p0_wr_addr = {2'h1, ch1_p0_wr_addr_cnt[0], ch1_p0_wr_addr_cnt[8 -3:1]}; +assign ch1_p1_wr_addr = {2'h1, ch1_p1_wr_addr_cnt[0], ch1_p1_wr_addr_cnt[8 -3:1]}; +assign ch2_p0_wr_addr = {2'h2, ch2_p0_wr_addr_cnt[0], ch2_p0_wr_addr_cnt[8 -3:1]}; +assign ch2_p1_wr_addr = {2'h2, ch2_p1_wr_addr_cnt[0], ch2_p1_wr_addr_cnt[8 -3:1]}; +assign ch3_p0_wr_addr = {2'h3, ch3_p0_wr_addr_cnt[0], ch3_p0_wr_addr_cnt[8 -3:1]}; +assign ch3_p1_wr_addr = {2'h3, ch3_p1_wr_addr_cnt[0], ch3_p1_wr_addr_cnt[8 -3:1]}; +//////////////////////////////////////////////////////////////////////// +// Shared buffer write signals // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: if($M > 1) { +//: print qq( +//: assign p${k}_wr_en = is_running & dma_rd_rsp_vld & ~is_blocking & dma_rd_rsp_mask[$k]; +//: ); +//: } else { +//: print qq( +//: assign p${k}_wr_en = is_running & dma_rd_rsp_vld & ~is_blocking; +//: ); +//: } +//: print qq( +//: assign p${k}_wr_addr = ({8 {p${k}_wr_en & is_rsp_ch0}} & ch0_p${k}_wr_addr) +//: | ({8 {p${k}_wr_en & is_rsp_ch1}} & ch1_p${k}_wr_addr) +//: | ({8 {p${k}_wr_en & is_rsp_ch2}} & ch2_p${k}_wr_addr) +//: | ({8 {p${k}_wr_en & is_rsp_ch3}} & ch3_p${k}_wr_addr); +//: assign dc2sbuf_p${k}_wr_en = p${k}_wr_en; +//: assign dc2sbuf_p${k}_wr_addr = p${k}_wr_addr; +//: assign dc2sbuf_p${k}_wr_data = dma_rsp_data_p${k}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign p0_wr_en = is_running & dma_rd_rsp_vld & ~is_blocking; + +assign p0_wr_addr = ({8 {p0_wr_en & is_rsp_ch0}} & ch0_p0_wr_addr) +| ({8 {p0_wr_en & is_rsp_ch1}} & ch1_p0_wr_addr) +| ({8 {p0_wr_en & is_rsp_ch2}} & ch2_p0_wr_addr) +| ({8 {p0_wr_en & is_rsp_ch3}} & ch3_p0_wr_addr); +assign dc2sbuf_p0_wr_en = p0_wr_en; +assign dc2sbuf_p0_wr_addr = p0_wr_addr; +assign dc2sbuf_p0_wr_data = dma_rsp_data_p0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// DC local buffer count // +//////////////////////////////////////////////////////////////////////// +assign ch0_cnt_add = (ch0_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch1_cnt_add = (ch1_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch2_cnt_add = (ch2_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch3_cnt_add = (ch3_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch0_cnt_sub = (ch0_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +assign ch1_cnt_sub = (ch1_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +assign ch2_cnt_sub = (ch2_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +assign ch3_cnt_sub = (ch3_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +// assign ch1_cnt_sub = (ch1_rd_addr_cnt_reg_en) ? 1'b1 : 1'h0; +// assign ch2_cnt_sub = (ch2_rd_addr_cnt_reg_en) ? 1'b1 : 1'h0; +// assign ch3_cnt_sub = (ch3_rd_addr_cnt_reg_en) ? 1'b1 : 1'h0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch0_cnt,ch0_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch0_cnt,ch0_cnt} <= {6{1'b0}}; + end else if (ch0_wr_addr_cnt_reg_en | ch0_rd_addr_cnt_reg_en) begin + {mon_ch0_cnt,ch0_cnt} <= ch0_cnt + ch0_cnt_add - ch0_cnt_sub; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch1_cnt,ch1_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch1_cnt,ch1_cnt} <= {6{1'b0}}; + end else if (ch1_wr_addr_cnt_reg_en | ch1_rd_addr_cnt_reg_en) begin + {mon_ch1_cnt,ch1_cnt} <= ch1_cnt + ch1_cnt_add - ch1_cnt_sub; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch2_cnt,ch2_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch2_cnt,ch2_cnt} <= {6{1'b0}}; + end else if (ch2_wr_addr_cnt_reg_en | ch2_rd_addr_cnt_reg_en) begin + {mon_ch2_cnt,ch2_cnt} <= ch2_cnt + ch2_cnt_add - ch2_cnt_sub; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch3_cnt,ch3_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch3_cnt,ch3_cnt} <= {6{1'b0}}; + end else if (ch3_wr_addr_cnt_reg_en | ch3_rd_addr_cnt_reg_en) begin + {mon_ch3_cnt,ch3_cnt} <= ch3_cnt + ch3_cnt_add - ch3_cnt_sub; + end +end +//////////////////////////////////////////////////////////////////////// +// DC response data counter---DC reading from Sbuf // +//////////////////////////////////////////////////////////////////////// +///////////// all height counter ///////////// +assign {mon_rsp_all_h_cnt_inc, + rsp_all_h_cnt_inc} = rsp_all_h_cnt + rsp_cur_grain; +assign {mon_rsp_all_h_left_w, + rsp_all_h_left_w} = layer_st ? {1'b0, data_height_w} : data_height - rsp_all_h_cnt_inc; +assign rsp_cur_grain_w = (rsp_all_h_left_w > {{2{1'b0}}, fetch_grain_w}) ? fetch_grain_w : rsp_all_h_left_w[11:0]; +assign is_rsp_all_h_end = (rsp_all_h_cnt_inc == data_height); +assign is_rsp_done = ~reg2dp_op_en | (rsp_all_h_cnt == data_height); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_all_h_cnt <= {14{1'b0}}; + end else if (layer_st) begin + rsp_all_h_cnt <= {14{1'b0}}; + end else begin + if (rsp_all_h_reg_en) begin + rsp_all_h_cnt <= rsp_all_h_cnt_inc; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_cur_grain <= {12{1'b0}}; + end else begin + if ((layer_st | rsp_all_h_reg_en) == 1'b1) begin + rsp_cur_grain <= rsp_cur_grain_w; + end + end +end +///////////// batch counter ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_batch_cnt <= {5{1'b0}}; + end else if (layer_st) begin + rsp_batch_cnt <= {5{1'b0}}; + end else if(rsp_batch_reg_en) begin + if (is_rsp_batch_end) + rsp_batch_cnt <= {5{1'b0}}; + else + rsp_batch_cnt <= rsp_batch_cnt + 1'b1; + end +end +assign is_rsp_batch_end = (rsp_batch_cnt == reg2dp_batches); +///////////// channel counter ///////////// +assign rsp_ch_mode = req_ch_mode; +assign {mon_rsp_ch_cnt_inc, + rsp_ch_cnt_inc} = rsp_ch_cnt + rsp_cur_ch; +assign {mon_rsp_ch_left_w,rsp_ch_left_w} = (layer_st | is_rsp_ch_end) ? {1'b0,data_surface_w} : (data_surface - rsp_ch_cnt_inc); +// assign is_rsp_ch_end = (rsp_ch_cnt_inc == data_surface); +assign rsp_cur_ch_w = (rsp_ch_left_w > {{8{1'b0}}, rsp_ch_mode}) ? rsp_ch_mode : rsp_ch_left_w[2:0]; +//assign is_rsp_ch_end = (rsp_ch_cnt == (data_surface - rsp_cur_ch)); +wire [10:0] data_surface_dec_1; +wire mon_data_surface_dec_1; +assign {mon_data_surface_dec_1,data_surface_dec_1} = data_surface-{8'd0,rsp_cur_ch}; +assign is_rsp_ch_end = (rsp_ch_cnt == data_surface_dec_1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_rsp_ch_cnt,rsp_ch_cnt} <= {12{1'b0}}; + end else if (layer_st) begin + {mon_rsp_ch_cnt,rsp_ch_cnt} <= {12{1'b0}}; + end else if (rsp_ch_reg_en) begin + if(is_rsp_ch_end) + {mon_rsp_ch_cnt,rsp_ch_cnt} <= {12{1'b0}}; + else + {mon_rsp_ch_cnt,rsp_ch_cnt} <= rsp_ch_cnt + rsp_cur_ch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_cur_ch <= {3{1'b0}}; + end else begin + if ((layer_st | rsp_ch_reg_en) == 1'b1) begin + rsp_cur_ch <= rsp_cur_ch_w; + end + end +end +///////////// height counter ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_h_cnt <= {12{1'b0}}; + end else if (layer_st) begin + rsp_h_cnt <= {12{1'b0}}; + end else if(rsp_h_reg_en) begin + if (is_rsp_h_end) + rsp_h_cnt <= {12{1'b0}}; + else + rsp_h_cnt <= rsp_h_cnt + 1'b1; + end +end +assign is_rsp_h_end = (rsp_h_cnt == rsp_cur_grain-1); +///////////// width counter ///////////// +assign rsp_w_left1 = (rsp_w_cnt == {1'b0, data_width_sub_one}); +//assign rsp_w_left2 = (rsp_w_cnt == {1'b0, data_width-3'd2}); +//assign rsp_w_left3 = (rsp_w_cnt == {1'b0, data_width-3'd3}); +//assign rsp_w_left4 = (rsp_w_cnt == {1'b0, data_width-3'd4}); +wire mon_data_width_dec2; +wire [15:0] data_width_dec2; +wire mon_data_width_dec3; +wire [15:0] data_width_dec3; +wire mon_data_width_dec4; +wire [15:0] data_width_dec4; +assign {mon_data_width_dec2,data_width_dec2} = data_width-16'd2; +assign {mon_data_width_dec3,data_width_dec3} = data_width-16'd3; +assign {mon_data_width_dec4,data_width_dec4} = data_width-16'd4; +assign rsp_w_left2 = (rsp_w_cnt == data_width_dec2); +assign rsp_w_left3 = (rsp_w_cnt == data_width_dec3); +assign rsp_w_left4 = (rsp_w_cnt == data_width_dec4); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_rsp_w_cnt,rsp_w_cnt} <= {17{1'b0}}; + end else if (layer_st) begin + {mon_rsp_w_cnt,rsp_w_cnt} <= {17{1'b0}}; + end else if (rsp_w_reg_en) begin + if(is_rsp_w_end) + {mon_rsp_w_cnt,rsp_w_cnt} <= {17{1'b0}}; + else + {mon_rsp_w_cnt,rsp_w_cnt} <= rsp_w_cnt + rsp_w_cnt_add; + end +end +//assign is_rsp_w_end = (rsp_w_cnt == (data_width-rsp_w_cnt_add)); +wire mon_width_dec; +wire [15:0] width_dec; +assign {mon_width_dec,width_dec} = data_width - {13'd0, rsp_w_cnt_add}; +assign is_rsp_w_end = (rsp_w_cnt == width_dec); +///////////// response control signal ///////////// +// +assign rsp_ch0_rd_one = ~(rsp_cur_ch == 3'h1) | + rsp_w_left1 | + (is_data_normal & rsp_ch_cnt[1])/* | + (is_data_shrink & rsp_ch_cnt[2])*/; +// assign rsp_rd_one = ((rsp_cur_ch == 3'h1) & rsp_w_left1) | +// ((rsp_cur_ch == 3'h1) & is_data_normal & rsp_ch_cnt[1]) | +// ((rsp_cur_ch == 3'h1) & is_data_shrink & rsp_ch_cnt[2]) | +// ((rsp_cur_ch == 3'h3) & is_data_shrink & rsp_ch_cnt[2] & rsp_rd_ch2ch3); +always @(*) +begin +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: ##my $m = int($dmaif/$atmc); +//: ##if(($dmaif==1) && ($atmc==1)) { +//: if($dmaif==1) { +//: print qq( +//: rsp_rd_more_atmm[2:0] = 3'd0; +//: ); +//: } elsif(($dmaif==2) && ($atmc==1)) { +//: print qq( +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: ); +//: } elsif(($dmaif==4) && ($atmc==1)) { +//: print qq( +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else if(rsp_w_left3) +//: rsp_rd_more_atmm[2:0] = 3'b011; +//: else +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: ); +//: } elsif(($dmaif==2) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else begin +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end else begin//(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else if(rsp_w_left3) +//: rsp_rd_more_atmm[2:0] = 3'b011; +//: else //(rsp_w_left4) +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else// if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd4) begin +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end else if(rsp_cur_ch == 3'd3) begin +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end else if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end else begin // if(rsp_w_left2) begin +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else if(rsp_w_left3) +//: rsp_rd_more_atmm[2:0] = 3'b011; +//: else //(rsp_w_left4) +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +rsp_rd_more_atmm[2:0] = 3'd0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +end +// assign rsp_w_cnt_add = (rsp_ch0_rd_one) ? 2'h1 : 2'h2; +assign rsp_ch0_rd_size = rsp_w_cnt_add; +// +// assign rsp_w_reg_en = ~is_rsp_done & is_running & +// ((rsp_cur_ch == 3'h1 & (ch0_cnt >= {3'b0, rsp_w_cnt_add})) +// | (rsp_cur_ch == 3'h2 & ch0_aval & ch1_aval) +// | (rsp_cur_ch > 3'h2 & rsp_rd_ch2ch3)); +assign rsp_w_reg_en = rsp_rd_en; +assign rsp_h_reg_en = rsp_w_reg_en & is_rsp_w_end; +assign rsp_ch_reg_en = rsp_h_reg_en & is_rsp_h_end; +assign rsp_batch_reg_en = rsp_ch_reg_en & is_rsp_ch_end; +assign rsp_all_h_reg_en = rsp_batch_reg_en & is_rsp_batch_end; +//////////////////////////////////////////////////////////////////////// +// generate shared buffer rd signals // +//////////////////////////////////////////////////////////////////////// +///////////// read enable signal ///////////// +assign ch0_aval = (|ch0_cnt); +assign ch1_aval = (|ch1_cnt); +assign ch2_aval = (|ch2_cnt); +assign ch3_aval = (|ch3_cnt); +// assign rsp_rd_en = ~is_rsp_done & is_running & +// ((rsp_cur_ch == 3'h1 & (ch0_cnt >= {3'b0, rsp_w_cnt_add})) | +// (rsp_cur_ch == 3'h2 & ch0_aval & ch1_aval) | +// (rsp_cur_ch == 3'h3 & ~rsp_rd_ch2ch3 & ch0_aval & ch1_aval) | +// (rsp_cur_ch == 3'h3 & rsp_rd_ch2ch3 & ch2_aval) | +// (rsp_cur_ch == 3'h4 & ~rsp_rd_ch2ch3 & ch0_aval & ch1_aval) | +// (rsp_cur_ch == 3'h4 & rsp_rd_ch2ch3 & ch2_aval & ch3_aval)); +always @(*) +begin + if(~is_rsp_done & is_running) begin +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: ##my $m = int($dmaif/$atmc); +//: ##if(($dmaif==1) && ($atmc==1)) { +//: if($dmaif==1) { +//: print qq( +//: rsp_rd_en = ch0_aval; +//: rsp_w_cnt_add = 3'd1; +//: ); +//: } elsif(($dmaif==2) && ($atmc==1)) { +//: print qq( +//: rsp_rd_en = ch0_aval; +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else +//: rsp_w_cnt_add = 3'd2; +//: ); +//: } elsif(($dmaif==4) && ($atmc==1)) { +//: print qq( +//: rsp_rd_en = ch0_aval; +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: else if(rsp_w_left3) +//: rsp_w_cnt_add = 3'd3; +//: else +//: rsp_w_cnt_add = 3'd4; +//: ); +//: } elsif(($dmaif==2) && ($atmc==2)) { +//: print qq( +//: rsp_w_cnt_add = 3'd1; +//: if(rsp_cur_ch == 3'd2) +//: rsp_rd_en = ch0_aval & ch1_aval; +//: else //rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: ); +//: } elsif(($dmaif==4) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: rsp_rd_en = ch0_aval; +//: rsp_w_cnt_add = 3'd1; +//: end else begin//(rsp_w_left2) +//: rsp_rd_en = ch0_aval & ch1_aval; +//: rsp_w_cnt_add = 3'd2; +//: end +//: end else begin//rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: else if(rsp_w_left3) +//: rsp_w_cnt_add = 3'd1; +//: else //(rsp_w_left4) +//: rsp_w_cnt_add = 3'd4; +//: end +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: rsp_rd_en = ch0_aval & ch1_aval; +//: rsp_w_cnt_add = 3'd1; +//: end else begin//rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else// if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd4) begin +//: rsp_w_cnt_add = 3'd1; +//: rsp_rd_en = ch0_aval & ch1_aval & ch2_aval & ch3_aval; +//: end else if(rsp_cur_ch == 3'd3) begin +//: rsp_w_cnt_add = 3'd1; +//: rsp_rd_en = ch0_aval & ch1_aval & ch2_aval; +//: end else if(rsp_cur_ch == 3'd2) begin +//: rsp_rd_en = ch0_aval & ch1_aval; +//: if(rsp_w_left1) begin +//: rsp_w_cnt_add = 3'd1; +//: end else begin // if(rsp_w_left2) begin +//: rsp_w_cnt_add = 3'd2; +//: end +//: end else begin//rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: else if(rsp_w_left3) +//: rsp_w_cnt_add = 3'd1; +//: else //(rsp_w_left4) +//: rsp_w_cnt_add = 3'd4; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +rsp_rd_en = ch0_aval; +rsp_w_cnt_add = 3'd1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + rsp_rd_en = 1'b0; + rsp_w_cnt_add = 3'd0; + end +end +assign p0_rd_en_w = rsp_rd_en; +// assign p1_rd_en_w = rsp_rd_en & ~rsp_rd_one; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: if($M > 1) { +//: foreach my $k (0..$M-2) { +//: my $i = $k +1; +//: print qq( +//: assign p${i}_rd_en_w = rsp_rd_en & rsp_rd_more_atmm[$k]; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////// channel address counter ///////////// +assign ch0_rd_addr_cnt_reg_en = rsp_rd_en & ~rsp_rd_ch2ch3; +assign ch1_rd_addr_cnt_reg_en = rsp_rd_en & (rsp_cur_ch >= 3'h2) & ~rsp_rd_ch2ch3; +assign ch2_rd_addr_cnt_reg_en = rsp_rd_en & (rsp_cur_ch >= 3'h3) & rsp_rd_ch2ch3; +assign ch3_rd_addr_cnt_reg_en = rsp_rd_en & (rsp_cur_ch == 3'h4) & rsp_rd_ch2ch3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch0_p0_rd_addr_cnt,ch0_p0_rd_addr_cnt} <= 7'b0; + {mon_ch0_p1_rd_addr_cnt,ch0_p1_rd_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch0_p0_rd_addr_cnt,ch0_p0_rd_addr_cnt} <= 7'b0; + {mon_ch0_p1_rd_addr_cnt,ch0_p1_rd_addr_cnt} <= 7'b1; + end else if(ch0_rd_addr_cnt_reg_en) begin + {mon_ch0_p0_rd_addr_cnt,ch0_p0_rd_addr_cnt} <= ch0_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + {mon_ch0_p1_rd_addr_cnt,ch0_p1_rd_addr_cnt} <= ch0_p1_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch1_p0_rd_addr_cnt,ch1_p0_rd_addr_cnt} <= 7'b0; + {mon_ch1_p1_rd_addr_cnt,ch1_p1_rd_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch1_p0_rd_addr_cnt,ch1_p0_rd_addr_cnt} <= 7'b0; + {mon_ch1_p1_rd_addr_cnt,ch1_p1_rd_addr_cnt} <= 7'b1; + end else if(ch1_rd_addr_cnt_reg_en) begin + {mon_ch1_p0_rd_addr_cnt,ch1_p0_rd_addr_cnt} <= ch1_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + {mon_ch1_p1_rd_addr_cnt,ch1_p1_rd_addr_cnt} <= ch1_p1_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch2_p0_rd_addr_cnt,ch2_p0_rd_addr_cnt} <= 7'b0; + end else if(layer_st) begin + {mon_ch2_p0_rd_addr_cnt,ch2_p0_rd_addr_cnt} <= 7'b0; + end else if(ch2_rd_addr_cnt_reg_en) begin + {mon_ch2_p0_rd_addr_cnt,ch2_p0_rd_addr_cnt} <= ch2_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch3_p0_rd_addr_cnt,ch3_p0_rd_addr_cnt} <= 7'b0; + end else if(layer_st) begin + {mon_ch3_p0_rd_addr_cnt,ch3_p0_rd_addr_cnt} <= 7'b0; + end else if(ch3_rd_addr_cnt_reg_en) begin + {mon_ch3_p0_rd_addr_cnt,ch3_p0_rd_addr_cnt} <= ch3_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_rd_ch2ch3 <= 1'b0; + end else if(layer_st) begin + rsp_rd_ch2ch3 <= 1'b0; + if (rsp_rd_en) begin + if((rsp_cur_ch <= 3'h2)) + rsp_rd_ch2ch3 <= 1'b0; + else + rsp_rd_ch2ch3 <= ~rsp_rd_ch2ch3; + end + end +end +assign ch0_p0_rd_addr = {2'h0, ch0_p0_rd_addr_cnt[0], ch0_p0_rd_addr_cnt[8 -3:1]}; +assign ch0_p1_rd_addr = {2'h0, ch0_p1_rd_addr_cnt[0], ch0_p1_rd_addr_cnt[8 -3:1]}; +assign ch1_p0_rd_addr = {2'h1, ch1_p0_rd_addr_cnt[0], ch1_p0_rd_addr_cnt[8 -3:1]}; +assign ch1_p1_rd_addr = {2'h1, ch1_p1_rd_addr_cnt[0], ch1_p1_rd_addr_cnt[8 -3:1]}; +assign ch2_p0_rd_addr = {2'h2, ch2_p0_rd_addr_cnt[0], ch2_p0_rd_addr_cnt[8 -3:1]}; +assign ch3_p0_rd_addr = {2'h3, ch3_p0_rd_addr_cnt[0], ch3_p0_rd_addr_cnt[8 -3:1]}; +///////////// shared buffer read address ///////////// +always @(*) begin +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc+0.99); +//: ##foreach my $k (0..$m-1){ +//: ## print " p${k}_rd_addr_w = 8'd0; \n"; +//: ##} +//: ##if(($dmaif==1) && ($atmc==1)) { +//: if($dmaif==1) { +//: print qq( +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: ); +//: } elsif(($dmaif==2) && ($atmc==1)) { +//: print qq( +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: ); +//: } elsif(($dmaif==4) && ($atmc==1)) { +//: print qq( +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch0_p1_rd_addr; +//: ); +//: } elsif(($dmaif==2) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: end else begin //rsp_cur_ch==1 +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else begin//(rsp_w_left2) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch1_p0_rd_addr; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = 8'd0; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left3) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = 8'd0; +//: end else begin //(rsp_w_left4) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch0_p1_rd_addr; +//: end +//: end +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = 8'd0; +//: end else begin // if(rsp_w_left2) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: end +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd4) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch2_p0_rd_addr; +//: p3_rd_addr_w = ch3_p0_rd_addr; +//: end else if(rsp_cur_ch == 3'd3) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch2_p0_rd_addr; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else begin // if(rsp_w_left2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch0_p1_rd_addr; +//: p3_rd_addr_w = ch1_p1_rd_addr; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = 8'd0; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left3) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = 8'd0; +//: end else begin //(rsp_w_left4) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch0_p1_rd_addr; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +p0_rd_addr_w = ch0_p0_rd_addr; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +end +// assign p0_rd_addr_w = rsp_rd_ch2ch3 ? ch2_p0_rd_addr : ch0_p0_rd_addr; +// assign p1_rd_addr_w = (rsp_cur_ch == 3'h1) ? ch0_p1_rd_addr : ( rsp_rd_ch2ch3 ? ch3_p0_rd_addr : ch1_p0_rd_addr); +///////////// blocking signal ///////////// +// assign is_blocking_w = (~is_running | layer_st) ? 1'b0 : (~is_blocking & rsp_rd_en & rsp_ch0_rd_one); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_blocking <= 1'b0; + end else if(~is_running | layer_st) begin + is_blocking <= 1'b0; + end else begin + is_blocking <= ~is_blocking & rsp_rd_en & rsp_ch0_rd_one; + end +end +///////////// output to shared buffer ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: print qq( +//: dc2sbuf_p${k}_rd_en <= 1'b0; +//: ); +//: } +//: print qq( +//: end else begin +//: ); +//: foreach my $k (0..$M-1) { +//: print qq( +//: dc2sbuf_p${k}_rd_en <= p${k}_rd_en_w; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +dc2sbuf_p0_rd_en <= 1'b0; + +end else begin + +dc2sbuf_p0_rd_en <= p0_rd_en_w; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +end +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: dc2sbuf_p${k}_rd_addr <= {8{1'b0}}; +//: end else if (p${k}_rd_en_w) begin +//: dc2sbuf_p${k}_rd_addr <= p${k}_rd_addr_w; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dc2sbuf_p0_rd_addr <= {8{1'b0}}; +end else if (p0_rd_en_w) begin +dc2sbuf_p0_rd_addr <= p0_rd_addr_w; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// generate write signal to convertor // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: if(($dmaif==1) && ($atmc==1)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: idx_ch_offset + data_width; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = 1'b0; +//: ); +//: } elsif(($dmaif==1) && ($atmc==2)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[0]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[0] & (rsp_cur_ch == 3'h2)); +//: assign cbuf_wr_hsel_w = (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[0]) ; +//: ); +//: } elsif(($dmaif==1) && ($atmc==4)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (&rsp_ch_cnt[1:0]) ? idx_ch_offset + data_width : idx_ch_offset; +//: //assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[2] & (rsp_cur_ch == 3'h1)); +//: //assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[2] & (rsp_cur_ch == 3'h2)); +//: assign is_w_cnt_div4 = is_data_normal & (data_surface[1:0] == 2'b01) & (data_surface - rsp_ch_cnt == 1); +//: assign is_w_cnt_div2 = is_data_normal & (data_surface[1:0] == 2'b10) & (data_surface - rsp_ch_cnt <= 2); +//: assign cbuf_wr_hsel_w[0] = (is_w_cnt_div4 & rsp_w_cnt[0]) | (is_w_cnt_div2 & rsp_ch_cnt[0]) | (is_data_normal & rsp_ch_cnt[0]) ; +//: assign cbuf_wr_hsel_w[1] = (is_w_cnt_div4 & rsp_w_cnt[1]) | (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[1]) ; +//: ); +//: } elsif((($dmaif==2) || ($dmaif==4)) && ($atmc==1)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: idx_ch_offset + data_width; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = 1'b0; +//: ); +//: } elsif((($dmaif==2) || ($dmaif==4)) && ($atmc==2)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[0]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[0] & (rsp_cur_ch == 3'h2)); +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[1]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h1)); +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h2)); +//: assign cbuf_wr_hsel_w = (is_w_cnt_div4 & rsp_w_cnt[1]) | (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[1]) ; +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[1]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h1)); +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h2)); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_idx_ch_offset_w, +idx_ch_offset_w} = (layer_st) ? 18'b0 : +(is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +idx_ch_offset + data_width; +assign is_w_cnt_div4 = 1'b0; +assign is_w_cnt_div2 = 1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_idx_batch_offset_w, idx_batch_offset_w} = (layer_st | is_rsp_batch_end) ? 19'b0 : (idx_batch_offset + data_entries); +assign {mon_idx_h_offset_w, + idx_h_offset_w} = (layer_st) ? 18'b0 : + (is_rsp_h_end) ? {1'b0, idx_ch_offset_w} : + (is_rsp_all_h_end) ? idx_h_offset + rsp_batch_entry_last : idx_h_offset + rsp_batch_entry_init; +// assign {mon_idx_ch_offset_w, +// idx_ch_offset_w} = (layer_st) ? 18'b0 : +// (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +// (rsp_ch_cnt[1]) ? idx_ch_offset + data_width[12:0] : idx_ch_offset; +// +// assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h1)); +// assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h2)); +// +// assign cbuf_wr_hsel_w = (is_w_cnt_div4 & rsp_w_cnt[1]) | (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[1]) ; +//assign idx_w_offset_add = is_w_cnt_div4 ? {rsp_w_cnt[12 +2:2]} : ( is_w_cnt_div2 ? rsp_w_cnt[12+1 :1] : rsp_w_cnt[12:0] ); +assign idx_w_offset_add = is_w_cnt_div4 ? {1'b0,rsp_w_cnt[15:2]} : ( is_w_cnt_div2 ? rsp_w_cnt[14+1 :1] : rsp_w_cnt[14:0] ); +assign {mon_cbuf_idx_inc[2:0], cbuf_idx_inc} = idx_base + (idx_grain_offset + idx_h_offset) + idx_w_offset_add; +assign is_cbuf_idx_wrap = cbuf_idx_inc >= {1'b0, data_bank, 9'b0}; +assign cbuf_idx_w = ~is_cbuf_idx_wrap ? {2'b0, cbuf_idx_inc[14:0]} : {2'd0,cbuf_idx_inc[14 :0]} - {2'b0, data_bank, 9'b0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_base <= 0; + end else begin + if ((is_first_running) == 1'b1) begin + idx_base <= status2dma_wr_idx; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_batch_offset <= 0; + end else begin + if ((layer_st | rsp_batch_reg_en) == 1'b1) begin + idx_batch_offset <= idx_batch_offset_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_ch_offset <= 0; + end else begin + if ((layer_st | rsp_ch_reg_en) == 1'b1) begin + idx_ch_offset <= idx_ch_offset_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_h_offset <= {18{1'b0}}; + end else begin + if ((layer_st | rsp_h_reg_en) == 1'b1) begin + idx_h_offset <= idx_h_offset_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_idx_grain_offset,idx_grain_offset} <= {19{1'b0}}; + end else if(layer_st) begin + {mon_idx_grain_offset,idx_grain_offset} <= {19{1'b0}}; + end else if(rsp_all_h_reg_en) begin + {mon_idx_grain_offset,idx_grain_offset} <= idx_grain_offset + rsp_entry; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cbuf_wr_en <= 1'b0; + end else begin + cbuf_wr_en <= rsp_rd_en; + end +end +// +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_addr_$i <= 0; +//: end else if(rsp_w_reg_en) begin +//: cbuf_wr_addr_$i <= cbuf_idx_w + $i; +//: end +//: end +//: ); +//: } +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: if($dmaif < $atmc) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_hsel <= 0; +//: end else begin +//: if ((rsp_w_reg_en) == 1'b1) begin +//: cbuf_wr_hsel <= cbuf_wr_hsel_w; +//: end +//: end +//: end +//: ); +//: } elsif($dmaif > $atmc) { +//: print qq( +//: reg [$dmaif-1:0] cbuf_wr_mask; +//: wire [$dmaif-1:0] cbuf_wr_mask_d0; +//: reg [$dmaif-1:0] cbuf_wr_mask_d1; +//: reg [$dmaif-1:0] cbuf_wr_mask_d2; +//: reg [$dmaif-1:0] cbuf_wr_mask_d3; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_mask <= 0; +//: end else begin +//: cbuf_wr_mask <= {; +//: ); +//: if($dmaif > 1) { +//: foreach my $k (0..$dmaif-2) { +//: my $i = $dmaif - $k -2; +//: print " p${i}_rd_en_w, "; +//: } +//: } +//: print qq( +//: p0_rd_en_w}; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_addr_0 <= 0; +end else if(rsp_w_reg_en) begin +cbuf_wr_addr_0 <= cbuf_idx_w + 0; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cbuf_wr_info_mask <= 0; + end else begin +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: print " cbuf_wr_info_mask <= {{(4-$M){1'b0}} "; +//: foreach my $k (0..$M-1) { +//: my $i = $M - $k -1; +//: print " ,p${i}_rd_en_w "; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + cbuf_wr_info_mask <= {{(4-1){1'b0}} ,p0_rd_en_w +//| eperl: generated_end (DO NOT EDIT ABOVE) + }; + end +end +assign cbuf_wr_info_pd[3:0] = cbuf_wr_info_mask[3:0]; +assign cbuf_wr_info_pd[4] = 1'b0;//cbuf_wr_info_interleave ; +assign cbuf_wr_info_pd[5] = 1'b0;//cbuf_wr_info_ext64 ; +assign cbuf_wr_info_pd[6] = 1'b0;//cbuf_wr_info_ext128 ; +assign cbuf_wr_info_pd[7] = 1'b0;//cbuf_wr_info_mean ; +assign cbuf_wr_info_pd[8] = 1'b0;//cbuf_wr_info_uint ; +assign cbuf_wr_info_pd[11:9] = 3'd0;//cbuf_wr_info_sub_h[2:0]; +//////////////////////////////////////////////////////////////////////// +// pipeline to sync the sbuf read to output to convertor // +//////////////////////////////////////////////////////////////////////// +assign cbuf_wr_en_d0 = cbuf_wr_en; +assign cbuf_wr_info_pd_d0 = cbuf_wr_info_pd; +// +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $latency = (2 +1); +//: +//: if($dmaif < $atmc) { +//: print qq( assign cbuf_wr_hsel_d0 = cbuf_wr_hsel; ); +//: foreach my $i (0..$latency-1) { +//: my $j = $i + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_hsel_d${j} <= 1'b0; +//: end else if (cbuf_wr_en_d${i}) begin +//: cbuf_wr_hsel_d${j} <= cbuf_wr_hsel_d${i}; +//: end +//: end +//: ); +//: } +//: } elsif($dmaif > $atmc) { +//: print qq( assign cbuf_wr_mask_d0 = cbuf_wr_mask; ); +//: foreach my $i (0..$latency-1) { +//: my $j = $i + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_mask_d${j} <= 1'b0; +//: end else if (cbuf_wr_en_d${i}) begin +//: cbuf_wr_mask_d${j} <= cbuf_wr_mask_d${i}; +//: end +//: end +//: ); +//: } +//: } +//: ################################################################### +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: assign cbuf_wr_addr_d0_${i} = cbuf_wr_addr_${i}; +//: ); +//: foreach my $k (0..$latency-1) { +//: my $j = $k + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_addr_d${j}_${i} <= 0; +//: end else if ((cbuf_wr_en_d${k}) == 1'b1) begin +//: cbuf_wr_addr_d${j}_${i} <= cbuf_wr_addr_d${k}_${i}; +//: end +//: end +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cbuf_wr_addr_d0_0 = cbuf_wr_addr_0; + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_addr_d1_0 <= 0; +end else if ((cbuf_wr_en_d0) == 1'b1) begin +cbuf_wr_addr_d1_0 <= cbuf_wr_addr_d0_0; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_addr_d2_0 <= 0; +end else if ((cbuf_wr_en_d1) == 1'b1) begin +cbuf_wr_addr_d2_0 <= cbuf_wr_addr_d1_0; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_addr_d3_0 <= 0; +end else if ((cbuf_wr_en_d2) == 1'b1) begin +cbuf_wr_addr_d3_0 <= cbuf_wr_addr_d2_0; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// +//: my $latency = (2 +1); +//: foreach my $i (0..$latency-1) { +//: my $j = $i + 1; +//: print qq ( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_en_d${j} <= 1'b0; +//: end else begin +//: cbuf_wr_en_d${j} <= cbuf_wr_en_d${i}; +//: end +//: end +//: +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_info_pd_d${j} <= {12{1'b0}}; +//: end else if(cbuf_wr_en_d${i}) begin +//: cbuf_wr_info_pd_d${j} <= cbuf_wr_info_pd_d${i}; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_en_d1 <= 1'b0; +end else begin +cbuf_wr_en_d1 <= cbuf_wr_en_d0; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_info_pd_d1 <= {12{1'b0}}; +end else if(cbuf_wr_en_d0) begin +cbuf_wr_info_pd_d1 <= cbuf_wr_info_pd_d0; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_en_d2 <= 1'b0; +end else begin +cbuf_wr_en_d2 <= cbuf_wr_en_d1; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_info_pd_d2 <= {12{1'b0}}; +end else if(cbuf_wr_en_d1) begin +cbuf_wr_info_pd_d2 <= cbuf_wr_info_pd_d1; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_en_d3 <= 1'b0; +end else begin +cbuf_wr_en_d3 <= cbuf_wr_en_d2; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +cbuf_wr_info_pd_d3 <= {12{1'b0}}; +end else if(cbuf_wr_en_d2) begin +cbuf_wr_info_pd_d3 <= cbuf_wr_info_pd_d2; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// ################################################################### +//: my $latency = (2 +1); +//: my $lb = $latency - 1; +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: if($dmaif <= $atmc) { +//: print qq ( +//: always @(posedge nvdla_core_clk) begin +//: if (cbuf_wr_en_d${lb}) begin +//: cbuf_wr_data_d${latency}_0 <= { +//: ); +//: if($dmaif > 1){ +//: foreach my $p (0..$dmaif-2){ +//: my $q = $dmaif -$p -1; +//: print qq( dc2sbuf_p${q}_rd_data, ); +//: } +//: } +//: print qq ( +//: dc2sbuf_p0_rd_data}; +//: end +//: end +//: ); +//: } else { +//: my $cnum = int($dmaif/$atmc); +//: foreach my $k (0.. $cnum-1){ +//: my $ks = $k * $atmc; +//: print qq ( +//: always @(posedge nvdla_core_clk) begin +//: if (cbuf_wr_en_d${lb}) begin +//: cbuf_wr_data_d${latency}_${k} <= { +//: ); +//: if($atmc > 1){ +//: foreach my $p (0..$atmc-2){ +//: my $q = $atmc -$p -1; +//: my $bs = $q + $ks; +//: print qq( dc2sbuf_p${bs}_rd_data, ); +//: } +//: } +//: print qq ( +//: dc2sbuf_p${ks}_rd_data}; +//: end +//: end +//: ); +//: } +//: } +//: ################################################################### +//: +//: if($dmaif <= $atmc) { +//: print qq( +//: assign dc2cvt_dat_wr_addr = cbuf_wr_addr_d${latency}_0; +//: assign dc2cvt_dat_wr_data = cbuf_wr_data_d${latency}_0; +//: ); +//: } else { +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: assign dc2cvt_dat_wr_addr${i} = cbuf_wr_addr_d${latency}_${i}; +//: assign dc2cvt_dat_wr_data${i} = cbuf_wr_data_d${latency}_${i}; +//: ); +//: } +//: } +//: ################################################################### +//: print qq ( +//: assign dc2cvt_dat_wr_en = cbuf_wr_en_d${latency}; +//: assign dc2cvt_dat_wr_info_pd = cbuf_wr_info_pd_d${latency}; +//: ); +//: ################################################################### +//: if($dmaif < $atmc) { +//: print qq ( +//: assign dc2cvt_dat_wr_sel = cbuf_wr_hsel_d${latency}; +//: ); +//: } elsif ($dmaif > $atmc) { +//: print qq ( +//: assign dc2cvt_dat_wr_mask = cbuf_wr_mask_d${latency}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk) begin +if (cbuf_wr_en_d2) begin +cbuf_wr_data_d3_0 <= { + +dc2sbuf_p0_rd_data}; +end +end + +assign dc2cvt_dat_wr_addr = cbuf_wr_addr_d3_0; +assign dc2cvt_dat_wr_data = cbuf_wr_data_d3_0; + +assign dc2cvt_dat_wr_en = cbuf_wr_en_d3; +assign dc2cvt_dat_wr_info_pd = cbuf_wr_info_pd_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// convolution buffer slices & entries management // +//////////////////////////////////////////////////////////////////////// +///////////// calculate onfly slices and entries ///////////// +assign req_entry = req_csm_sel ? req_entry_1_d3[14:0] : req_entry_0_d3[14:0]; +assign rsp_entry = is_rsp_all_h_end ? rsp_entry_last : rsp_entry_init; +assign dc_entry_onfly_add = ~req_grain_reg_en ? 15'b0 : req_entry; +assign dc_entry_onfly_sub = ~dc2status_dat_updt ? 15'b0 : dc2status_dat_entries; +assign {mon_dc_entry_onfly_w, + dc_entry_onfly_w} = dc_entry_onfly + dc_entry_onfly_add - dc_entry_onfly_sub; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_entry_onfly <= {15{1'b0}}; + end else if ((req_grain_reg_en | dc2status_dat_updt) == 1'b1) begin + dc_entry_onfly <= dc_entry_onfly_w; + end +end +///////////// calculate if free entries is enough ///////////// +assign required_entries = dc_entry_onfly + req_entry; +assign is_free_entries_enough = (required_entries <= {1'b0, status2dma_free_entries}); +assign cbuf_is_ready_w = (~is_running | ~req_pre_valid | csm_reg_en) ? 1'b0 : is_free_entries_enough; +assign rsp_slice = is_rsp_all_h_end ? rsp_slice_last : rsp_slice_init; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cbuf_is_ready <= 1'b0; + end else begin + cbuf_is_ready <= cbuf_is_ready_w; + end +end +///////////// update CDMA data status ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d0 <= 1'b0; + end else begin + dat_updt_d0 <= rsp_all_h_reg_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d0 <= {15{1'b0}}; + end else begin + if ((rsp_all_h_reg_en) == 1'b1) begin + dat_entries_d0 <= rsp_entry[14:0];//15bit is enough + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d0 <= {14{1'b0}}; + end else begin + if ((rsp_all_h_reg_en) == 1'b1) begin + dat_slices_d0 <= rsp_slice; + end + end +end +//: my $latency = (2 + 1); +//: my @list = ("updt", "entries", "slices"); +//: foreach my $i (0..$latency-1) { +//: my $k = $i + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: dat_updt_d${k} <= 1'b0; +//: end else begin +//: dat_updt_d${k} <= dat_updt_d${i}; +//: end +//: end +//: ); +//: foreach my $j (1..2) { +//: my $name = $list[$j]; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: dat_${name}_d${k} <= 0; +//: end else begin +//: if ((dat_updt_d${i}) == 1'b1) begin +//: dat_${name}_d${k} <= dat_${name}_d${i}; +//: end +//: end +//: end +//: ); +//: } +//: } +//: +//: foreach my $j (0..2) { +//: my $name = $list[$j]; +//: print qq( +//: assign dc2status_dat_${name} = dat_${name}_d${latency}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_updt_d1 <= 1'b0; +end else begin +dat_updt_d1 <= dat_updt_d0; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_entries_d1 <= 0; +end else begin +if ((dat_updt_d0) == 1'b1) begin +dat_entries_d1 <= dat_entries_d0; +end +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_slices_d1 <= 0; +end else begin +if ((dat_updt_d0) == 1'b1) begin +dat_slices_d1 <= dat_slices_d0; +end +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_updt_d2 <= 1'b0; +end else begin +dat_updt_d2 <= dat_updt_d1; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_entries_d2 <= 0; +end else begin +if ((dat_updt_d1) == 1'b1) begin +dat_entries_d2 <= dat_entries_d1; +end +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_slices_d2 <= 0; +end else begin +if ((dat_updt_d1) == 1'b1) begin +dat_slices_d2 <= dat_slices_d1; +end +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_updt_d3 <= 1'b0; +end else begin +dat_updt_d3 <= dat_updt_d2; +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_entries_d3 <= 0; +end else begin +if ((dat_updt_d2) == 1'b1) begin +dat_entries_d3 <= dat_entries_d2; +end +end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +dat_slices_d3 <= 0; +end else begin +if ((dat_updt_d2) == 1'b1) begin +dat_slices_d3 <= dat_slices_d2; +end +end +end + +assign dc2status_dat_updt = dat_updt_d3; + +assign dc2status_dat_entries = dat_entries_d3; + +assign dc2status_dat_slices = dat_slices_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_stall_inc <= 1'b0; + end else begin + dc_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_stall_clr <= 1'b0; + end else begin + dc_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_stall_cen <= 1'b0; + end else begin + dc_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_dc_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = dc_rd_stall_inc ^ dp2reg_dc_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (dc_rd_stall_inc && !dp2reg_dc_rd_stall_dec)? stl_cnt_inc : (!dc_rd_stall_inc && dp2reg_dc_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (dc_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (dc_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_dc_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_inc <= 1'b0; + end else begin + dc_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_dec <= 1'b0; + end else begin + dc_rd_latency_dec <= dma_rsp_fifo_ready & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_clr <= 1'b0; + end else begin + dc_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_cen <= 1'b0; + end else begin + dc_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign ltc_1_inc = (outs_dp2reg_dc_rd_latency!=511) & dc_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_dc_rd_latency!=511) & dc_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (dc_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (dc_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_dc_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +assign ltc_2_dec = 1'b0; +assign ltc_2_inc = (~&dp2reg_dc_rd_latency) & (|outs_dp2reg_dc_rd_latency); +// ltc_2 adv logic +always @(*) begin + ltc_2_adv = ltc_2_inc ^ ltc_2_dec; +end +// ltc_2 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_2_cnt_ext[33:0] = {1'b0, 1'b0, ltc_2_cnt_cur}; + ltc_2_cnt_inc[33:0] = ltc_2_cnt_cur + 1'b1; // spyglass disable W164b + ltc_2_cnt_dec[33:0] = ltc_2_cnt_cur - 1'b1; // spyglass disable W164b + ltc_2_cnt_mod[33:0] = (ltc_2_inc && !ltc_2_dec)? ltc_2_cnt_inc : (!ltc_2_inc && ltc_2_dec)? ltc_2_cnt_dec : ltc_2_cnt_ext; + ltc_2_cnt_new[33:0] = (ltc_2_adv)? ltc_2_cnt_mod[33:0] : ltc_2_cnt_ext[33:0]; + ltc_2_cnt_nxt[33:0] = (dc_rd_latency_clr)? 34'd0 : ltc_2_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// ltc_2 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_2_cnt_cur[31:0] <= 0; + end else begin + if (dc_rd_latency_cen) begin + ltc_2_cnt_cur[31:0] <= ltc_2_cnt_nxt[31:0]; + end + end +end +// ltc_2 output logic +always @(*) begin + dp2reg_dc_rd_latency[31:0] = ltc_2_cnt_cur[31:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_dc__cbuf_idx_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (rsp_w_reg_en & is_cbuf_idx_wrap); + endproperty +// Cover 0 : "(rsp_w_reg_en & is_cbuf_idx_wrap)" + FUNCPOINT_cdma_dc__cbuf_idx_wrap__0_COV : cover property (cdma_dc__cbuf_idx_wrap__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_dc__input_fully_connected__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & is_packed_1x1); + endproperty +// Cover 1 : "(layer_st & is_packed_1x1)" + FUNCPOINT_cdma_dc__input_fully_connected__1_COV : cover property (cdma_dc__input_fully_connected__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_dc__dc_batch_size_EQ_0__2_0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 0); + endproperty +// Cover 2_0 : "reg2dp_batches == 0" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_0__2_0_COV : cover property (cdma_dc__dc_batch_size_EQ_0__2_0_cov); + property cdma_dc__dc_batch_size_EQ_1__2_1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 1); + endproperty +// Cover 2_1 : "reg2dp_batches == 1" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_1__2_1_COV : cover property (cdma_dc__dc_batch_size_EQ_1__2_1_cov); + property cdma_dc__dc_batch_size_EQ_2__2_2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 2); + endproperty +// Cover 2_2 : "reg2dp_batches == 2" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_2__2_2_COV : cover property (cdma_dc__dc_batch_size_EQ_2__2_2_cov); + property cdma_dc__dc_batch_size_EQ_3__2_3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 3); + endproperty +// Cover 2_3 : "reg2dp_batches == 3" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_3__2_3_COV : cover property (cdma_dc__dc_batch_size_EQ_3__2_3_cov); + property cdma_dc__dc_batch_size_EQ_4__2_4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 4); + endproperty +// Cover 2_4 : "reg2dp_batches == 4" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_4__2_4_COV : cover property (cdma_dc__dc_batch_size_EQ_4__2_4_cov); + property cdma_dc__dc_batch_size_EQ_5__2_5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 5); + endproperty +// Cover 2_5 : "reg2dp_batches == 5" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_5__2_5_COV : cover property (cdma_dc__dc_batch_size_EQ_5__2_5_cov); + property cdma_dc__dc_batch_size_EQ_6__2_6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 6); + endproperty +// Cover 2_6 : "reg2dp_batches == 6" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_6__2_6_COV : cover property (cdma_dc__dc_batch_size_EQ_6__2_6_cov); + property cdma_dc__dc_batch_size_EQ_7__2_7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 7); + endproperty +// Cover 2_7 : "reg2dp_batches == 7" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_7__2_7_COV : cover property (cdma_dc__dc_batch_size_EQ_7__2_7_cov); + property cdma_dc__dc_batch_size_EQ_8__2_8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 8); + endproperty +// Cover 2_8 : "reg2dp_batches == 8" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_8__2_8_COV : cover property (cdma_dc__dc_batch_size_EQ_8__2_8_cov); + property cdma_dc__dc_batch_size_EQ_9__2_9_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 9); + endproperty +// Cover 2_9 : "reg2dp_batches == 9" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_9__2_9_COV : cover property (cdma_dc__dc_batch_size_EQ_9__2_9_cov); + property cdma_dc__dc_batch_size_EQ_10__2_10_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 10); + endproperty +// Cover 2_10 : "reg2dp_batches == 10" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_10__2_10_COV : cover property (cdma_dc__dc_batch_size_EQ_10__2_10_cov); + property cdma_dc__dc_batch_size_EQ_11__2_11_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 11); + endproperty +// Cover 2_11 : "reg2dp_batches == 11" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_11__2_11_COV : cover property (cdma_dc__dc_batch_size_EQ_11__2_11_cov); + property cdma_dc__dc_batch_size_EQ_12__2_12_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 12); + endproperty +// Cover 2_12 : "reg2dp_batches == 12" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_12__2_12_COV : cover property (cdma_dc__dc_batch_size_EQ_12__2_12_cov); + property cdma_dc__dc_batch_size_EQ_13__2_13_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 13); + endproperty +// Cover 2_13 : "reg2dp_batches == 13" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_13__2_13_COV : cover property (cdma_dc__dc_batch_size_EQ_13__2_13_cov); + property cdma_dc__dc_batch_size_EQ_14__2_14_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 14); + endproperty +// Cover 2_14 : "reg2dp_batches == 14" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_14__2_14_COV : cover property (cdma_dc__dc_batch_size_EQ_14__2_14_cov); + property cdma_dc__dc_batch_size_EQ_15__2_15_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 15); + endproperty +// Cover 2_15 : "reg2dp_batches == 15" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_15__2_15_COV : cover property (cdma_dc__dc_batch_size_EQ_15__2_15_cov); + property cdma_dc__dc_batch_size_EQ_16__2_16_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 16); + endproperty +// Cover 2_16 : "reg2dp_batches == 16" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_16__2_16_COV : cover property (cdma_dc__dc_batch_size_EQ_16__2_16_cov); + property cdma_dc__dc_batch_size_EQ_17__2_17_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 17); + endproperty +// Cover 2_17 : "reg2dp_batches == 17" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_17__2_17_COV : cover property (cdma_dc__dc_batch_size_EQ_17__2_17_cov); + property cdma_dc__dc_batch_size_EQ_18__2_18_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 18); + endproperty +// Cover 2_18 : "reg2dp_batches == 18" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_18__2_18_COV : cover property (cdma_dc__dc_batch_size_EQ_18__2_18_cov); + property cdma_dc__dc_batch_size_EQ_19__2_19_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 19); + endproperty +// Cover 2_19 : "reg2dp_batches == 19" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_19__2_19_COV : cover property (cdma_dc__dc_batch_size_EQ_19__2_19_cov); + property cdma_dc__dc_batch_size_EQ_20__2_20_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 20); + endproperty +// Cover 2_20 : "reg2dp_batches == 20" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_20__2_20_COV : cover property (cdma_dc__dc_batch_size_EQ_20__2_20_cov); + property cdma_dc__dc_batch_size_EQ_21__2_21_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 21); + endproperty +// Cover 2_21 : "reg2dp_batches == 21" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_21__2_21_COV : cover property (cdma_dc__dc_batch_size_EQ_21__2_21_cov); + property cdma_dc__dc_batch_size_EQ_22__2_22_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 22); + endproperty +// Cover 2_22 : "reg2dp_batches == 22" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_22__2_22_COV : cover property (cdma_dc__dc_batch_size_EQ_22__2_22_cov); + property cdma_dc__dc_batch_size_EQ_23__2_23_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 23); + endproperty +// Cover 2_23 : "reg2dp_batches == 23" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_23__2_23_COV : cover property (cdma_dc__dc_batch_size_EQ_23__2_23_cov); + property cdma_dc__dc_batch_size_EQ_24__2_24_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 24); + endproperty +// Cover 2_24 : "reg2dp_batches == 24" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_24__2_24_COV : cover property (cdma_dc__dc_batch_size_EQ_24__2_24_cov); + property cdma_dc__dc_batch_size_EQ_25__2_25_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 25); + endproperty +// Cover 2_25 : "reg2dp_batches == 25" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_25__2_25_COV : cover property (cdma_dc__dc_batch_size_EQ_25__2_25_cov); + property cdma_dc__dc_batch_size_EQ_26__2_26_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 26); + endproperty +// Cover 2_26 : "reg2dp_batches == 26" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_26__2_26_COV : cover property (cdma_dc__dc_batch_size_EQ_26__2_26_cov); + property cdma_dc__dc_batch_size_EQ_27__2_27_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 27); + endproperty +// Cover 2_27 : "reg2dp_batches == 27" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_27__2_27_COV : cover property (cdma_dc__dc_batch_size_EQ_27__2_27_cov); + property cdma_dc__dc_batch_size_EQ_28__2_28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 28); + endproperty +// Cover 2_28 : "reg2dp_batches == 28" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_28__2_28_COV : cover property (cdma_dc__dc_batch_size_EQ_28__2_28_cov); + property cdma_dc__dc_batch_size_EQ_29__2_29_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 29); + endproperty +// Cover 2_29 : "reg2dp_batches == 29" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_29__2_29_COV : cover property (cdma_dc__dc_batch_size_EQ_29__2_29_cov); + property cdma_dc__dc_batch_size_EQ_30__2_30_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 30); + endproperty +// Cover 2_30 : "reg2dp_batches == 30" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_30__2_30_COV : cover property (cdma_dc__dc_batch_size_EQ_30__2_30_cov); + property cdma_dc__dc_batch_size_EQ_31__2_31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 31); + endproperty +// Cover 2_31 : "reg2dp_batches == 31" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_31__2_31_COV : cover property (cdma_dc__dc_batch_size_EQ_31__2_31_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_dc__dc_reuse__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cur_state == DC_STATE_IDLE) & (nxt_state == DC_STATE_DONE)); + endproperty +// Cover 3 : "((cur_state == DC_STATE_IDLE) & (nxt_state == DC_STATE_DONE))" + FUNCPOINT_cdma_dc__dc_reuse__3_COV : cover property (cdma_dc__dc_reuse__3_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,2,0,"No Xs allowed on cur_state") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, cur_state); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_rsp_done | is_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | pre_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_g0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_g1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_init))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_last))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_50x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | pre_reg_en_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | csm_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_grain_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_atm_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rd_rsp_vld & ~is_blocking))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch0_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch1_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch2_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch3_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch0_wr_addr_cnt_reg_en | ch0_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch1_wr_addr_cnt_reg_en | ch1_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch2_wr_addr_cnt_reg_en | ch2_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch3_wr_addr_cnt_reg_en | ch3_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_103x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_all_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_107x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_108x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_115x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_w_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch0_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_117x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch1_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_118x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch2_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_119x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch3_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_121x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_123x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(p0_rd_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_124x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(p1_rd_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_125x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_126x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_127x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_128x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_129x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_all_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_130x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_w_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_141x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cbuf_wr_en_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_144x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cbuf_wr_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_147x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cbuf_wr_en_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_150x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_grain_reg_en | dc2status_dat_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_154x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_all_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_156x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_158x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_160x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML +//nv_assert_never #(0,0,"Error config! data bank is not big enough!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (is_running & ((data_bank * 256) < (data_entries * data_height)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data bank is not big enough!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (is_running & ((data_bank * 512) < (data_entries * data_height)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! fifo is not empty when done!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel counter is not empty when done!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & ((|ch0_cnt) | (|ch1_cnt) | (|ch2_cnt) | (|ch3_cnt)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Req is not done when rsp is done!") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & (req_height_cnt_d1 != data_height) & ~dbg_is_last_reuse)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Req is valid when rsp is done!") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & req_pre_valid)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_onfly is non zero when idle") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, (fetch_done & |(dc_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! reg2dp_grains is overflow!") zzz_assert_never_24x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_fetch_grain_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data_entries_w is overflow!") zzz_assert_never_25x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_data_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_one_hot #(0,3,0,"Error! conflict data type mode") zzz_assert_one_hot_26x (nvdla_core_clk, `ASSERT_RESET, ({is_data_normal, is_data_expand, is_data_shrink})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_height_cnt_inc is overflow!") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (mon_req_height_cnt_d1)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_slice_left is overflow!") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, ((|mon_req_slice_left))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cur_atomic is overflow!") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (pre_reg_en_d1 & (|mon_req_cur_atomic))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_per_batch is overflow!") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (pre_reg_en_d1 & (|mon_entry_per_batch))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cur_atomic is out of range when HoG!") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (is_running & ~is_feature & (|req_cur_atomic[12 -1: 12 -2]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_required is overflow!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, ((|mon_entry_required))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_ch_left_w is overflow") zzz_assert_never_55x (nvdla_core_clk, `ASSERT_RESET, (mon_req_ch_left_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cur_ch is out of range") zzz_assert_never_56x (nvdla_core_clk, `ASSERT_RESET, (req_cur_ch > 3'h4)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_ch_cnt is large than data_surface") zzz_assert_never_57x (nvdla_core_clk, `ASSERT_RESET, (is_running & (req_ch_cnt > data_surface))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_atm_left is overflow!") zzz_assert_never_63x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & (|mon_req_atm_left))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_atm_size_addr_limit is overflow!") zzz_assert_never_64x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & (|mon_req_atm_size_addr_limit))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_atm_size_out is overflow!") zzz_assert_never_65x (nvdla_core_clk, `ASSERT_RESET, (req_reg_en & (|mon_req_atm_size_out))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_grain_base_inc is overflow!") zzz_assert_never_70x (nvdla_core_clk, `ASSERT_RESET, (req_grain_reg_en & mon_req_addr_grain_base_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_batch_base_inc is overflow!") zzz_assert_never_71x (nvdla_core_clk, `ASSERT_RESET, (req_batch_reg_en & mon_req_addr_batch_base_inc & (|reg2dp_batches))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_ch_base_inc is overflow!") zzz_assert_never_72x (nvdla_core_clk, `ASSERT_RESET, (req_ch_reg_en & mon_req_addr_ch_base_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_base_inc is overflow!") zzz_assert_never_73x (nvdla_core_clk, `ASSERT_RESET, (req_atm_reg_en & mon_req_addr_base_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr is overflow!") zzz_assert_never_74x (nvdla_core_clk, `ASSERT_RESET, (req_reg_en & mon_req_addr)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Receive input data when not busy") zzz_assert_never_80x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_82x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_fifo_ready & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_83x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > dma_rsp_size)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_84x (nvdla_core_clk, `ASSERT_RESET, (mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_85x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > 8'h8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,4,0,"Error! ch_reg_en is not one hot") zzz_assert_zero_one_hot_94x (nvdla_core_clk, `ASSERT_RESET, {ch0_wr_addr_cnt_reg_en, ch1_wr_addr_cnt_reg_en, ch2_wr_addr_cnt_reg_en, ch3_wr_addr_cnt_reg_en}); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 0 is not zero when idle!") zzz_assert_never_99x (nvdla_core_clk, `ASSERT_RESET, ((|ch0_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 1 is not zero when idle!") zzz_assert_never_100x (nvdla_core_clk, `ASSERT_RESET, ((|ch1_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 2 is not zero when idle!") zzz_assert_never_101x (nvdla_core_clk, `ASSERT_RESET, ((|ch2_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 3 is not zero when idle!") zzz_assert_never_102x (nvdla_core_clk, `ASSERT_RESET, ((|ch3_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_all_h_cnt_inc is overflow") zzz_assert_never_105x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_all_h_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_all_h_left_w is overflow") zzz_assert_never_106x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_all_h_left_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_cnt_inc is overflow") zzz_assert_never_110x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_ch_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_left_w is overflow") zzz_assert_never_111x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_ch_left_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_cur_ch is out of range") zzz_assert_never_112x (nvdla_core_clk, `ASSERT_RESET, (rsp_cur_ch > 3'h4)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Blocking data response when not enabled") zzz_assert_never_122x (nvdla_core_clk, `ASSERT_RESET, (is_blocking & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! idx_batch_offset_w is overflow!") zzz_assert_never_135x (nvdla_core_clk, `ASSERT_RESET, (rsp_batch_reg_en & mon_idx_batch_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! idx_ch_offset_w is overflow!") zzz_assert_never_136x (nvdla_core_clk, `ASSERT_RESET, (rsp_ch_reg_en & mon_idx_ch_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! idx_h_offset_w is overflow!") zzz_assert_never_137x (nvdla_core_clk, `ASSERT_RESET, (rsp_h_reg_en & mon_idx_h_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cbuf_idx_inc is overflow!") zzz_assert_never_138x (nvdla_core_clk, `ASSERT_RESET, (rsp_w_reg_en & mon_cbuf_idx_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cbuf_idx_w is overflow!") zzz_assert_never_139x (nvdla_core_clk, `ASSERT_RESET, (rsp_w_reg_en & (|mon_cbuf_idx_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Error! conflict div mode") zzz_assert_zero_one_hot_140x (nvdla_core_clk, `ASSERT_RESET, ({/*is_w_cnt_div8,*/ is_w_cnt_div4, is_w_cnt_div2})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dc_entry_onfly_w is overflow") zzz_assert_never_151x (nvdla_core_clk, `ASSERT_RESET, (mon_dc_entry_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dc_entry_onfly_w is out of range") zzz_assert_never_152x (nvdla_core_clk, `ASSERT_RESET, (dc_entry_onfly_w > 16384)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dc_entry_onfly_w is non zero when idle") zzz_assert_never_153x (nvdla_core_clk, `ASSERT_RESET, (~is_running & |(dc_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Update to status when idle!") zzz_assert_never_162x (nvdla_core_clk, `ASSERT_RESET, (dc2status_dat_updt & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_163x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && dc_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_dc diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v.vcp new file mode 100644 index 0000000..7aaccd6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v.vcp @@ -0,0 +1,3350 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_dc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_dc ( + input nvdla_core_clk +,input nvdla_core_rstn +,input [31:0] pwrbus_ram_pd +,output dc_dat2mcif_rd_req_valid +,input dc_dat2mcif_rd_req_ready +,output [( 32 + 15 )-1:0] dc_dat2mcif_rd_req_pd +,input mcif2dc_dat_rd_rsp_valid +,output mcif2dc_dat_rd_rsp_ready +,input [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd +,output dc2cvt_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,output [${k}-1:0] dc2cvt_dat_wr_sel +//: ,output [16:0] dc2cvt_dat_wr_addr +//: ,output [${dmaif}-1:0] dc2cvt_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,output [${k}-1:0] dc2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,output [16:0] dc2cvt_dat_wr_addr${i} +//: ,output [${dmaif}-1:0] dc2cvt_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,output [16:0] dc2cvt_dat_wr_addr +//: ,output [${dmaif}-1:0] dc2cvt_dat_wr_data +//: ); +//: } +,output [11:0] dc2cvt_dat_wr_info_pd +,output reg [1:0] dc2status_state +,output dc2status_dat_updt +,output [14:0] dc2status_dat_entries +,output [13:0] dc2status_dat_slices +,input status2dma_fsm_switch +,input [13:0] status2dma_valid_slices +,input [14:0] status2dma_free_entries +,input [14:0] status2dma_wr_idx +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,output dc2sbuf_p${i}_wr_en +//: ,output [7:0] dc2sbuf_p${i}_wr_addr +//: ,output [${atmm}-1:0] dc2sbuf_p${i}_wr_data +//: ,output reg dc2sbuf_p${i}_rd_en +//: ,output reg [7:0] dc2sbuf_p${i}_rd_addr +//: ,input [${atmm}-1:0] dc2sbuf_p${i}_rd_data +//: ); +//: } +,input sc2cdma_dat_pending_req +,input nvdla_core_ng_clk +,input reg2dp_op_en +,input reg2dp_conv_mode +,input reg2dp_data_reuse +,input reg2dp_skip_data_rls +,input reg2dp_datain_format +,input [12:0] reg2dp_datain_width +,input [12:0] reg2dp_datain_height +,input [12:0] reg2dp_datain_channel +,input reg2dp_datain_ram_type +,input [31:0] reg2dp_datain_addr_high_0 +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: ,input [31-${atmbw}:0] reg2dp_datain_addr_low_0 +//: ,input [31-${atmbw}:0] reg2dp_line_stride +//: ,input [31-${atmbw}:0] reg2dp_surf_stride +//: ,input [31-${atmbw}:0] reg2dp_batch_stride +//: ); +,input reg2dp_line_packed +,input reg2dp_surf_packed +,input [4:0] reg2dp_batches +,input [16:0] reg2dp_entries //entry number per slice +,input [11:0] reg2dp_grains +,input [4:0] reg2dp_data_bank +,input reg2dp_dma_en +,output slcg_dc_gate_wg +,output slcg_dc_gate_img +,output reg [31:0] dp2reg_dc_rd_stall +,output reg [31:0] dp2reg_dc_rd_latency + ); +///////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////// +reg cbuf_is_ready; +//: my $dmabw=64; +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: reg [16:0] cbuf_wr_addr_$i; +//: wire [16:0] cbuf_wr_addr_d0_$i; +//: reg [16:0] cbuf_wr_addr_d1_$i; +//: reg [16:0] cbuf_wr_addr_d2_$i; +//: reg [16:0] cbuf_wr_addr_d3_$i; +//: reg [$dmabw-1:0] cbuf_wr_data_d3_$i; +//: ); +//: } +reg cbuf_wr_en; +reg cbuf_wr_en_d1; +reg cbuf_wr_en_d2; +reg cbuf_wr_en_d3; +//reg cbuf_wr_hsel; +reg [3:0] cbuf_wr_info_mask; +reg [11:0] cbuf_wr_info_pd_d1; +reg [11:0] cbuf_wr_info_pd_d2; +reg [11:0] cbuf_wr_info_pd_d3; +reg [4:0] ch0_cnt; +reg mon_ch0_cnt; +reg [5:0] ch0_p0_rd_addr_cnt; +reg mon_ch0_p0_rd_addr_cnt; +reg [5:0] ch0_p0_wr_addr_cnt; +reg mon_ch0_p0_wr_addr_cnt; +reg [5:0] ch0_p1_rd_addr_cnt; +reg mon_ch0_p1_rd_addr_cnt; +reg [5:0] ch0_p1_wr_addr_cnt; +reg mon_ch0_p1_wr_addr_cnt; +reg [4:0] ch1_cnt; +reg mon_ch1_cnt; +reg [5:0] ch1_p0_wr_addr_cnt; +reg mon_ch1_p0_wr_addr_cnt; +reg [5:0] ch1_p0_rd_addr_cnt; +reg [5:0] ch1_p1_rd_addr_cnt; +reg mon_ch1_p0_rd_addr_cnt; +reg mon_ch1_p1_rd_addr_cnt; +reg [5:0] ch1_p1_wr_addr_cnt; +reg mon_ch1_p1_wr_addr_cnt; +reg [4:0] ch2_cnt; +reg mon_ch2_cnt; +reg [5:0] ch2_p0_rd_addr_cnt; +reg mon_ch2_p0_rd_addr_cnt; +reg [5:0] ch2_p0_wr_addr_cnt; +reg mon_ch2_p0_wr_addr_cnt; +reg [5:0] ch2_p1_wr_addr_cnt; +reg mon_ch2_p1_wr_addr_cnt; +reg [4:0] ch3_cnt; +reg mon_ch3_cnt; +reg [5:0] ch3_p0_wr_addr_cnt; +reg mon_ch3_p0_wr_addr_cnt; +reg [5:0] ch3_p0_rd_addr_cnt; +reg mon_ch3_p0_rd_addr_cnt; +reg [5:0] ch3_p1_wr_addr_cnt; +reg mon_ch3_p1_wr_addr_cnt; +reg [1:0] cur_state; +reg [14:0] dat_entries_d0; +reg [14:0] dat_entries_d1; +reg [14:0] dat_entries_d2; +reg [14:0] dat_entries_d3; +reg [13:0] dat_slices_d0; +reg [13:0] dat_slices_d1; +reg [13:0] dat_slices_d2; +reg [13:0] dat_slices_d3; +reg dat_updt_d0; +reg dat_updt_d1; +reg dat_updt_d2; +reg dat_updt_d3; +reg [5:0] data_bank; +reg [5:0] data_batch; +reg [17:0] data_entries; +reg [13:0] data_height; +reg [10:0] data_surface; +reg [15:0] data_width; +reg [14:0] data_width_sub_one; +reg dbg_is_last_reuse; +////: my $dmaif=NVDLA_CDMA_DMAIF_BW; +////: my $atmm = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_CDMA_BPE; ##atomic_m BW +////: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +////: foreach my $k (0..$M-1) { +////: print qq( +////: reg [7:0] dc2sbuf_p${k}_rd_addr; +////: reg dc2sbuf_p${k}_rd_en; +////: ); +////: } +//reg [1:0] dc2status_state; +reg [14:0] dc_entry_onfly; +reg dc_rd_latency_cen; +reg dc_rd_latency_clr; +reg dc_rd_latency_dec; +reg dc_rd_latency_inc; +reg dc_rd_stall_cen; +reg dc_rd_stall_clr; +reg dc_rd_stall_inc; +reg [4:0] delay_cnt; +wire [3:0] dma_rsp_size; +reg [3:0] dma_rsp_size_cnt; +//reg [31:0] dp2reg_dc_rd_latency; +//reg [31:0] dp2reg_dc_rd_stall; +reg [17:0] entry_per_batch_d2; +reg [11:0] fetch_grain; +reg [14:0] idx_base; +reg [17:0] idx_batch_offset; +reg [17:0] idx_ch_offset; +reg [17:0] idx_grain_offset; +reg mon_idx_grain_offset; +reg [17:0] idx_h_offset; +reg is_blocking; +reg is_req_grain_last_d1; +reg is_req_grain_last_d2; +reg [4:0] last_data_bank; +reg last_dc; +reg last_skip_data_rls; +reg ltc_1_adv; +reg [8:0] ltc_1_cnt_cur; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg ltc_2_adv; +reg [31:0] ltc_2_cnt_cur; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg [1:0] nxt_state; +reg [8:0] outs_dp2reg_dc_rd_latency; +reg pending_req; +reg pending_req_d1; +//bw of below two signals +reg [0:0] pre_gen_sel; +reg [0:0] req_csm_sel; +//: foreach my $i (0..1){ +//: print qq( +//: wire pre_reg_en_d2_g${i}; +//: reg [13:0] req_atomic_${i}_d3; +//: reg [17:0] req_entry_${i}_d3; +//: reg req_pre_valid_${i}_d3; +//: ); +//: } +reg pre_valid_d1; +reg pre_valid_d2; +reg [13:0] req_atm_cnt_0; +reg [13:0] req_atm_cnt_1; +reg [13:0] req_atm_cnt_2; +reg [13:0] req_atm_cnt_3; +reg [1:0] req_atm_sel; +reg [13:0] req_atomic_d2; +reg [4:0] req_batch_cnt; +reg [10:0] req_ch_cnt; +reg mon_req_ch_cnt; +reg [1:0] req_ch_idx_d1; +reg [2:0] req_cur_ch; +reg [13:0] req_cur_grain_d1; +reg [13:0] req_cur_grain_d2; +reg [13:0] req_height_cnt_d1; +reg [3:0] req_size_d1; +reg [2:0] req_size_out_d1; +reg req_valid_d1; +reg [13:0] rsp_all_h_cnt; +reg [4:0] rsp_batch_cnt; +reg [17:0] rsp_batch_entry_init; +reg [17:0] rsp_batch_entry_last; +reg [10:0] rsp_ch_cnt; +reg mon_rsp_ch_cnt; +reg [2:0] rsp_cur_ch; +reg [11:0] rsp_cur_grain; +//reg [17:0] req_entry_0_d3; +//reg [17:0] req_entry_1_d3; +reg [17:0] rsp_entry_init; +reg [17:0] rsp_entry_last; +reg [11:0] rsp_h_cnt; +reg rsp_rd_ch2ch3; +reg [13:0] rsp_slice_init; +reg [13:0] rsp_slice_last; +reg [15:0] rsp_w_cnt; +reg mon_rsp_w_cnt; +reg [1:0] slcg_dc_gate_d1; +reg [1:0] slcg_dc_gate_d2; +reg [1:0] slcg_dc_gate_d3; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire [15:0] cbuf_idx_inc; +wire [16:0] cbuf_idx_w; +wire cbuf_is_ready_w; +wire cbuf_wr_en_d0; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: wire [${k}-1:0] cbuf_wr_hsel_w; +//: reg [${k}-1:0] cbuf_wr_hsel; +//: wire [${k}-1:0] cbuf_wr_hsel_d0; +//: reg [${k}-1:0] cbuf_wr_hsel_d1; +//: reg [${k}-1:0] cbuf_wr_hsel_d2; +//: reg [${k}-1:0] cbuf_wr_hsel_d3; +//: ); +//: } +wire [11:0] cbuf_wr_info_pd; +wire [11:0] cbuf_wr_info_pd_d0; +wire ch0_aval; +wire [1:0] ch0_cnt_add; +wire [2:0] ch0_cnt_sub; +wire [7:0] ch0_p0_rd_addr; +wire [7:0] ch0_p0_wr_addr; +wire [7:0] ch0_p1_rd_addr; +wire [7:0] ch0_p1_wr_addr; +wire ch0_rd_addr_cnt_reg_en; +wire ch0_wr_addr_cnt_reg_en; +wire ch1_aval; +wire [1:0] ch1_cnt_add; +wire [2:0] ch1_cnt_sub; +wire [4:0] ch1_cnt_w; +wire [7:0] ch1_p0_wr_addr; +wire [7:0] ch1_p0_rd_addr; +wire [7:0] ch1_p1_rd_addr; +wire [7:0] ch1_p1_wr_addr; +wire ch1_rd_addr_cnt_reg_en; +wire ch1_wr_addr_cnt_reg_en; +wire ch2_aval; +wire [1:0] ch2_cnt_add; +wire [2:0] ch2_cnt_sub; +wire [4:0] ch2_cnt_w; +wire [7:0] ch2_p0_rd_addr; +wire [7:0] ch2_p0_wr_addr; +wire [7:0] ch2_p1_wr_addr; +wire ch2_rd_addr_cnt_reg_en; +wire ch2_wr_addr_cnt_reg_en; +wire ch3_aval; +wire [1:0] ch3_cnt_add; +wire [2:0] ch3_cnt_sub; +wire [4:0] ch3_cnt_w; +wire [7:0] ch3_p0_wr_addr; +wire [7:0] ch3_p0_rd_addr; +wire [7:0] ch3_p1_wr_addr; +wire ch3_rd_addr_cnt_reg_en; +wire ch3_wr_addr_cnt_reg_en; +wire csm_reg_en; +wire cur_atm_done; +wire [17:0] data_entries_w; +wire [13:0] data_height_w; +wire [10:0] data_surface_inc; +wire [10:0] data_surface_w; +wire [14:0] data_width_sub_one_w; +wire dbg_is_last_reuse_w; +wire [1:0] dc2status_state_w; +wire dc_en; +wire [14:0] dc_entry_onfly_add; +wire [14:0] dc_entry_onfly_sub; +wire [14:0] dc_entry_onfly_w; +wire [4:0] delay_cnt_end; +wire [63:0] dma_rd_req_addr_f; +wire [32 -1:0] dma_rd_req_addr; +wire [( 32 + 15 )-1:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [15:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: print qq( +//: wire [${dmaif}+${M}-1:0] dma_rd_rsp_pd; +//: wire [${dmaif}-1:0] dma_rd_rsp_data; +//: ); +//: print qq( +//: wire [${M}-1:0] dma_rd_rsp_mask; +//: ); +//: foreach my $k (0..$M-1) { +//: print qq( wire [${atmm}-1:0] dma_rsp_data_p${k}; \n); +//: } +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [5:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire [1:0] dma_rsp_ch_idx; +wire [5:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire [3:0] dma_rsp_size_cnt_inc; +wire [3:0] dma_rsp_size_cnt_w; +wire dp2reg_dc_rd_stall_dec; +wire [17:0] entry_per_batch; +wire [17:0] entry_required; +wire fetch_done; +wire [11:0] fetch_grain_w; +wire [17:0] idx_batch_offset_w; +wire [17:0] idx_ch_offset_w; +wire [17:0] idx_h_offset_w; +wire [14:0] idx_w_offset_add; +wire [3:0] is_atm_done; +wire is_cbuf_idx_wrap; +wire is_data_normal; +wire is_dc; +wire is_done; +wire is_feature; +wire is_first_running; +wire is_free_entries_enough; +wire is_idle; +wire is_nxt_running; +wire is_packed_1x1; +wire is_pending; +wire is_req_atm_end; +wire is_req_atm_sel_end; +wire is_req_batch_end; +wire is_req_ch_end; +wire is_req_grain_last; +wire is_rsp_all_h_end; +wire is_rsp_batch_end; +wire is_rsp_ch0; +wire is_rsp_ch1; +wire is_rsp_ch2; +wire is_rsp_ch3; +wire is_rsp_ch_end; +wire is_rsp_done; +wire is_rsp_h_end; +wire is_rsp_w_end; +wire is_running; +wire is_w_cnt_div2; +wire is_w_cnt_div4; +wire layer_st; +wire ltc_1_dec; +wire ltc_1_inc; +wire ltc_2_dec; +wire ltc_2_inc; +wire mode_match; +wire [2:0] mon_cbuf_idx_inc; +wire [1:0] mon_cbuf_idx_w; +wire mon_ch1_cnt_w; +wire mon_ch2_cnt_w; +wire mon_ch3_cnt_w; +wire mon_data_entries_w; +wire mon_dc_entry_onfly_w; +wire mon_dma_rsp_size_cnt_inc; +wire [5:0] mon_entry_per_batch; +wire [13:0] mon_entry_required; +wire mon_fetch_grain_w; +wire mon_idx_batch_offset_w; +wire mon_idx_ch_offset_w; +wire mon_idx_h_offset_w; +wire mon_req_addr; +wire mon_req_addr_base_inc; +wire mon_req_addr_batch_base_inc; +wire mon_req_addr_ch_base_inc; +wire mon_req_addr_grain_base_inc; +wire mon_req_atm_cnt_inc; +wire mon_req_atm_left; +wire mon_req_atm_size_addr_limit; +wire [1:0] mon_req_atm_size_out; +wire mon_req_ch_left_w; +wire [15:0] mon_req_cur_atomic; +reg mon_req_height_cnt_d1; +wire mon_req_slice_left; +wire mon_rsp_all_h_cnt_inc; +wire mon_rsp_all_h_left_w; +wire mon_rsp_ch_cnt_inc; +wire mon_rsp_ch_left_w; +wire need_pending; +reg [2:0] rsp_rd_more_atmm; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: print qq( +//: wire p${k}_wr_en; +//: wire [7:0] p${k}_wr_addr; +//: wire p${k}_rd_en_w; +//: reg [7:0] p${k}_rd_addr_w; +//: ); +//: } +wire pending_req_end; +wire pre_ready; +wire pre_ready_d1; +wire pre_ready_d2; +wire pre_reg_en; +wire pre_reg_en_d1; +wire pre_reg_en_d2; +wire pre_reg_en_d2_init; +wire pre_reg_en_d2_last; +wire rd_req_rdyi; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: wire [63-${atmbw}:0] req_addr; +//: reg [63-${atmbw}:0] req_addr_d1; +//: wire [63-${atmbw}:0] req_addr_base_inc; +//: wire [63-${atmbw}:0] req_addr_base_w; +//: reg [63-${atmbw}:0] req_addr_base; +//: wire [63-${atmbw}:0] req_addr_batch_base_inc; +//: wire [63-${atmbw}:0] req_addr_batch_base_w; +//: wire [63-${atmbw}:0] req_addr_ori; +//: wire [63-${atmbw}:0] req_addr_ch_base_inc; +//: wire [63-${atmbw}:0] req_addr_ch_base_w; +//: wire [63-${atmbw}:0] req_addr_grain_base_inc; +//: wire [63-${atmbw}:0] req_addr_grain_base_w; +//: reg [63-${atmbw}:0] req_addr_batch_base; +//: reg [63-${atmbw}:0] req_addr_ch_base; +//: reg [63-${atmbw}:0] req_addr_grain_base; +//: wire [12+31-${atmbw}:0] grain_addr_w; +//: reg [12+31-${atmbw}:0] grain_addr; +//: wire [2+31-${atmbw}:0] req_addr_ch_base_add; +//: ); +wire [13:0] req_atm; +wire [13:0] req_atm_cnt; +wire [13:0] req_atm_cnt_0_w; +wire [13:0] req_atm_cnt_1_w; +wire [13:0] req_atm_cnt_2_w; +wire [13:0] req_atm_cnt_3_w; +wire [13:0] req_atm_cnt_inc; +wire [13:0] req_atm_left; +wire req_atm_reg_en; +wire req_atm_reg_en_0; +wire req_atm_reg_en_1; +wire req_atm_reg_en_2; +wire req_atm_reg_en_3; +wire [3:0] req_atm_size; +wire [3:0] req_atm_size_addr_limit; +wire [2:0] req_atm_size_out; +wire req_batch_reg_en; +wire [10:0] req_ch_left_w; +wire [2:0] req_ch_mode; +wire req_ch_reg_en; +wire [13:0] req_cur_atomic; +wire [13:0] req_cur_grain_w; +wire [14:0] req_entry; +wire req_grain_reg_en; +wire req_pre_valid; +wire req_pre_valid_0_w; +wire req_pre_valid_1_w; +wire req_ready_d0; +wire req_ready_d1; +wire req_reg_en; +wire [13:0] req_slice_left; +wire req_valid_d0; +wire [15:0] required_entries; +wire [13:0] rsp_all_h_cnt_inc; +wire [13:0] rsp_all_h_left_w; +wire rsp_all_h_reg_en; +wire rsp_batch_reg_en; +wire rsp_ch0_rd_one; +wire [2:0] rsp_ch0_rd_size; +wire [10:0] rsp_ch_cnt_inc; +wire [10:0] rsp_ch_left_w; +wire [2:0] rsp_ch_mode; +wire rsp_ch_reg_en; +wire [2:0] rsp_cur_ch_w; +wire [11:0] rsp_cur_grain_w; +wire [17:0] rsp_entry; +wire rsp_h_reg_en; +reg rsp_rd_en; +wire [13:0] rsp_slice; +reg [2:0] rsp_w_cnt_add; +wire rsp_w_left1; +wire rsp_w_left2; +wire rsp_w_left3; +wire rsp_w_left4; +wire rsp_w_reg_en; +wire slcg_dc_en_w; +wire [1:0] slcg_dc_gate_w; +wire [13:0] data_width_inc; +//////////////////////////////////////////////////////////////////////// +// CDMA direct convolution data fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +//## fsm (1) defines +localparam DC_STATE_IDLE = 2'b00; +localparam DC_STATE_PEND = 2'b01; +localparam DC_STATE_BUSY = 2'b10; +localparam DC_STATE_DONE = 2'b11; +//## fsm (1) com block +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + DC_STATE_IDLE: begin + if ((dc_en & need_pending)) begin + nxt_state = DC_STATE_PEND; + end + else if ((dc_en & reg2dp_data_reuse & last_skip_data_rls & mode_match)) begin + nxt_state = DC_STATE_DONE; + end + else if (dc_en) begin + nxt_state = DC_STATE_BUSY; + end + end + DC_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = DC_STATE_BUSY; + end + end + DC_STATE_BUSY: begin + if (fetch_done) begin + nxt_state = DC_STATE_DONE; + end + end + DC_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = DC_STATE_IDLE; + end + end + endcase + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_state <= DC_STATE_IDLE; + end else begin + cur_state <= nxt_state; + end +end +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign fetch_done = is_running & is_rsp_done & (delay_cnt == delay_cnt_end); +assign delay_cnt_end = (3 + 3 + 3); // this value is related to status pipeline delay +assign need_pending = (last_data_bank != reg2dp_data_bank); +assign mode_match = dc_en & last_dc; +assign is_feature = (reg2dp_datain_format == 1'h0 ); +assign is_dc = (reg2dp_conv_mode == 1'h0 ); +assign dc_en = reg2dp_op_en & is_dc & is_feature; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + delay_cnt <= {5{1'b0}}; + end else if(~is_running)begin + delay_cnt <= {5{1'b0}}; + end else if(is_rsp_done)begin + delay_cnt <= delay_cnt + 1'b1; + end +end +`ifndef SYNTHESIS +assign dbg_is_last_reuse_w = (is_idle & (nxt_state == DC_STATE_DONE)) ? 1'b1 : + (~is_running & is_nxt_running) ? 1'b0 : + dbg_is_last_reuse; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + dbg_is_last_reuse <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + dbg_is_last_reuse <= dbg_is_last_reuse_w; + end +end +`endif +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = dc_en & is_idle; +assign is_idle = (cur_state == DC_STATE_IDLE); +assign is_pending = (cur_state == DC_STATE_PEND); +assign is_running = (cur_state == DC_STATE_BUSY); +assign is_done = (cur_state == DC_STATE_DONE); +assign is_nxt_running = (nxt_state == DC_STATE_BUSY); +assign is_first_running = ~is_running & is_nxt_running; +assign dc2status_state_w = (nxt_state == DC_STATE_PEND) ? 1 : + (nxt_state == DC_STATE_BUSY) ? 2 : + (nxt_state == DC_STATE_DONE) ? 3 : + 0 ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc2status_state <= 0; + end else begin + dc2status_state <= dc2status_state_w; + end +end +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +assign pending_req_end = pending_req_d1 & ~pending_req; +//================ Non-SLCG clock domain ================// +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_dc <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_dc <= dc_en; + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_data_bank <= {5{1'b1}}; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_data_bank <= reg2dp_data_bank; + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_skip_data_rls <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_skip_data_rls <= dc_en & reg2dp_skip_data_rls; + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req <= 1'b0; + end else begin + pending_req <= sc2cdma_dat_pending_req; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req_d1 <= 1'b0; + end else begin + pending_req_d1 <= pending_req; + end +end +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_dc_en_w = dc_en & (is_running | is_pending | is_done); +assign slcg_dc_gate_w = {2{~slcg_dc_en_w}}; +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_dc_gate_d1 <= {2{1'b1}}; + end else begin + slcg_dc_gate_d1 <= slcg_dc_gate_w; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_dc_gate_d2 <= {2{1'b1}}; + end else begin + slcg_dc_gate_d2 <= slcg_dc_gate_d1; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_dc_gate_d3 <= {2{1'b1}}; + end else begin + slcg_dc_gate_d3 <= slcg_dc_gate_d2; + end +end +assign slcg_dc_gate_wg = slcg_dc_gate_d3[0]; +assign slcg_dc_gate_img = slcg_dc_gate_d3[1]; +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: if($atmbw > 3){ +//: print qq( +//: assign data_width_sub_one_w = (is_packed_1x1) ? {{(2+${atmbw}){1'b0}}, reg2dp_datain_channel[12:${atmbw}]} : {2'b0, reg2dp_datain_width}; +//: assign data_surface_inc = {{(${atmbw}-3){1'b0}}, reg2dp_datain_channel[12:${atmbw}]} + 1'b1; +//: ); +//:} +//: else { +//: print qq( +//: assign data_width_sub_one_w = (is_packed_1x1) ? {{(2+${atmbw}){1'b0}}, reg2dp_datain_channel[12:${atmbw}]} : {2'b0, reg2dp_datain_width}; +//: assign data_surface_inc = {reg2dp_datain_channel[12:${atmbw}]} + 1'b1; +//: ); +//:} +// assign is_data_expand = 1'b0; +//assign is_data_shrink = 1'b0; +assign is_data_normal = 1'b1; +assign is_packed_1x1 = (reg2dp_datain_width == 13'b0) & (reg2dp_datain_height == 13'b0) & reg2dp_surf_packed; +assign data_width_inc = reg2dp_datain_width + 1'b1; +//assign data_width_w = is_packed_1x1 ? {6'b0, data_surface_inc} : {2'b0, data_width_inc}; +assign data_height_w = reg2dp_datain_height + 1'b1; +assign {mon_data_entries_w, data_entries_w} = reg2dp_entries + 1'b1; +assign data_surface_w = is_packed_1x1 ? 11'b1 : data_surface_inc; +assign {mon_fetch_grain_w, fetch_grain_w} = (~reg2dp_line_packed) ? 13'b1 : reg2dp_grains + 1'b1; +assign grain_addr_w = fetch_grain_w * reg2dp_line_stride; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width <= {16{1'b0}}; + end else begin + if (layer_st) begin + if(is_packed_1x1) + data_width <= {5'b0, data_surface_inc} ; + else + data_width <= {2'b0, data_width_inc}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width_sub_one <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_width_sub_one <= data_width_sub_one_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_height <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_height <= data_height_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_batch <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_batch <= reg2dp_batches + 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_entries <= 0; + end else begin + if ((layer_st) == 1'b1) begin + data_entries <= data_entries_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + fetch_grain <= {12{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + fetch_grain <= fetch_grain_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_surface <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_surface <= data_surface_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + grain_addr <= 0; + end else begin + if ((layer_st) == 1'b1) begin + grain_addr <= grain_addr_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_bank <= reg2dp_data_bank + 1'b1; + end + end +end +//////////////////////////////////////////////////////////////////////// +// prepare for address generation // +//////////////////////////////////////////////////////////////////////// +///////////// stage 1 ///////////// +assign pre_ready = ~pre_valid_d1 | pre_ready_d1; +assign pre_reg_en = is_running & (req_height_cnt_d1 != data_height) & pre_ready; +assign {mon_req_slice_left, req_slice_left} = data_height - req_height_cnt_d1; +assign is_req_grain_last = (req_slice_left <= {2'd0,fetch_grain}); +assign req_cur_grain_w = is_req_grain_last ? req_slice_left : {2'd0,fetch_grain}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_req_height_cnt_d1,req_height_cnt_d1} <= {15{1'b0}}; + end else if(layer_st) begin + {mon_req_height_cnt_d1,req_height_cnt_d1} <= {15{1'b0}}; + end else if (pre_reg_en) begin + {mon_req_height_cnt_d1,req_height_cnt_d1} <= req_height_cnt_d1 + req_cur_grain_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_cur_grain_d1 <= {14{1'b0}}; + end else begin + if ((pre_reg_en) == 1'b1) begin + req_cur_grain_d1 <= req_cur_grain_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_req_grain_last_d1 <= 1'b0; + end else begin + if ((pre_reg_en) == 1'b1) begin + is_req_grain_last_d1 <= is_req_grain_last; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_valid_d1 <= 1'b0; + end else if(~is_running)begin + pre_valid_d1 <= 1'b0; + end else begin + if(req_height_cnt_d1 != data_height) + pre_valid_d1 <= 1'b1; + else if(pre_ready_d1) + pre_valid_d1 <= 1'b0; + end +end +///////////// stage 2 ///////////// +assign {mon_req_cur_atomic, req_cur_atomic} = req_cur_grain_d1 * data_width; +assign {mon_entry_per_batch, entry_per_batch} = data_entries * data_batch; +assign pre_ready_d1 = ~pre_valid_d2 | pre_ready_d2; +assign pre_reg_en_d1 = pre_valid_d1 & pre_ready_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atomic_d2 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + req_atomic_d2 <= req_cur_atomic; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + entry_per_batch_d2 <= 0; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + entry_per_batch_d2 <= entry_per_batch; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_cur_grain_d2 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + req_cur_grain_d2 <= req_cur_grain_d1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_req_grain_last_d2 <= 1'b0; + end else begin + if ((pre_reg_en_d1) == 1'b1) begin + is_req_grain_last_d2 <= is_req_grain_last_d1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_valid_d2 <= 1'b0; + end else if(~is_running)begin + pre_valid_d2 <= 1'b0; + end else begin + if(pre_valid_d1) + pre_valid_d2 <= 1'b1; + else if(pre_ready_d2) + pre_valid_d2 <= 1'b0; + end +end +///////////// stage 3 ///////////// +assign {mon_entry_required, entry_required} = req_cur_grain_d2 * entry_per_batch_d2; +assign pre_reg_en_d2_g0 = pre_valid_d2 & ~pre_gen_sel & ~req_pre_valid_0_d3; +assign pre_reg_en_d2_g1 = pre_valid_d2 & pre_gen_sel & ~req_pre_valid_1_d3; +assign pre_ready_d2 = ((~pre_gen_sel & ~req_pre_valid_0_d3) | (pre_gen_sel & ~req_pre_valid_1_d3)); +assign pre_reg_en_d2 = pre_valid_d2 & pre_ready_d2; +assign pre_reg_en_d2_init = pre_valid_d2 & pre_ready_d2 & ~is_req_grain_last_d2; +assign pre_reg_en_d2_last = pre_valid_d2 & pre_ready_d2 & is_req_grain_last_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atomic_0_d3 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_g0) == 1'b1) begin + req_atomic_0_d3 <= req_atomic_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atomic_1_d3 <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_g1) == 1'b1) begin + req_atomic_1_d3 <= req_atomic_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_entry_0_d3 <= 0; + end else begin + if ((pre_reg_en_d2_g0) == 1'b1) begin + req_entry_0_d3 <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_entry_1_d3 <= 0; + end else begin + if ((pre_reg_en_d2_g1) == 1'b1) begin + req_entry_1_d3 <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_entry_init <= 0; + end else begin + if ((pre_reg_en_d2_init) == 1'b1) begin + rsp_entry_init <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_entry_last <= 0; + end else begin + if ((pre_reg_en_d2_last) == 1'b1) begin + rsp_entry_last <= entry_required; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_batch_entry_init <= 0; + end else begin + if ((pre_reg_en_d2_init) == 1'b1) begin + rsp_batch_entry_init <= entry_per_batch_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_batch_entry_last <= 0; + end else begin + if ((pre_reg_en_d2_last) == 1'b1) begin + rsp_batch_entry_last <= entry_per_batch_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_slice_init <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_init) == 1'b1) begin + rsp_slice_init <= req_cur_grain_d2; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_slice_last <= {14{1'b0}}; + end else begin + if ((pre_reg_en_d2_last) == 1'b1) begin + rsp_slice_last <= req_cur_grain_d2; + end + end +end +///////////// prepare control logic ///////////// +// assign pre_gen_sel_w = is_running & (pre_valid_d2 ^ pre_gen_sel); +// assign req_csm_sel_w = is_running & ~req_csm_sel; +assign req_pre_valid_0_w = ~is_running ? 1'b0 : + (pre_reg_en_d2_g0) ? 1'b1 : + (~req_csm_sel & csm_reg_en) ? 1'b0 : req_pre_valid_0_d3; +assign req_pre_valid_1_w = ~is_running ? 1'b0 : + (pre_reg_en_d2_g1) ? 1'b1 : + (req_csm_sel & csm_reg_en) ? 1'b0 : req_pre_valid_1_d3; +assign csm_reg_en = req_grain_reg_en; +assign req_pre_valid = ~req_csm_sel ? req_pre_valid_0_d3 : req_pre_valid_1_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_gen_sel <= 0; + end else if(~is_running) begin + pre_gen_sel <= 0; + end else if (pre_reg_en_d2) begin + pre_gen_sel <= pre_gen_sel + 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_csm_sel <= 0; + end else if(~is_running) begin + req_csm_sel <= 0; + end else if (csm_reg_en) begin + req_csm_sel <= req_csm_sel + 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pre_valid_0_d3 <= 1'b0; + end else begin + req_pre_valid_0_d3 <= req_pre_valid_0_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pre_valid_1_d3 <= 1'b0; + end else begin + req_pre_valid_1_d3 <= req_pre_valid_1_w; + end +end +//////////////////////////////////////////////////////////////////////// +// generate address for input feature data // +//////////////////////////////////////////////////////////////////////// +///////////// batch counter ///////////// +// assign {mon_req_batch_cnt_inc, +// req_batch_cnt_inc} = req_batch_cnt + 1'b1; +// assign req_batch_cnt_w = (is_req_batch_end) ? 5'b0 : +// req_batch_cnt_inc; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_batch_cnt <= {5{1'b0}}; + end else if(layer_st) begin + req_batch_cnt <= {5{1'b0}}; + end else begin + if (req_batch_reg_en) begin + if(is_req_batch_end) + req_batch_cnt <= {5{1'b0}}; + else + req_batch_cnt <= req_batch_cnt + 1'b1; + end + end +end +assign is_req_batch_end = (req_batch_cnt == reg2dp_batches); +///////////// channel counter ///////////// +assign req_ch_mode = is_packed_1x1 ? 3'h1 : + /*is_data_shrink ? 3'h4 : */ +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc); +//: my $k; +//: if($m > 1){$k=$atmc;} +//: else {$k=$dmaif;} +//: print qq( +//: 3'h${k}; +//: ); +assign {mon_req_ch_left_w,req_ch_left_w} = (layer_st | is_req_ch_end) ? {1'b0,data_surface_w} : (data_surface - req_ch_cnt) - {8'd0,req_cur_ch}; +// assign req_cur_ch_w = (req_ch_left_w > {{8{1'b0}}, req_ch_mode}) ? req_ch_mode : req_ch_left_w[2:0]; +// assign {mon_req_ch_cnt_inc, +// req_ch_cnt_inc} = req_ch_cnt + req_cur_ch; +// assign is_req_ch_end = (req_ch_cnt_inc == data_surface); +// assign req_ch_cnt_w = (layer_st | is_req_ch_end) ? 10'b0 : +// req_ch_cnt_inc; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_req_ch_cnt,req_ch_cnt} <= {12{1'b0}}; + end else if(layer_st) begin + {mon_req_ch_cnt,req_ch_cnt} <= {12{1'b0}}; + end else begin + if (req_ch_reg_en) begin + if(is_req_ch_end) + {mon_req_ch_cnt,req_ch_cnt} <= {12{1'b0}}; + else + {mon_req_ch_cnt,req_ch_cnt} <= req_ch_cnt + {8'd0, req_cur_ch}; + end + end +end +//assign is_req_ch_end = (req_ch_cnt == (data_surface-req_cur_ch)); +wire [10:0] data_surface_dec; +wire mon_data_surface_dec; +assign {mon_data_surface_dec,data_surface_dec} = data_surface-{8'd0,req_cur_ch}; +assign is_req_ch_end = (req_ch_cnt == data_surface_dec); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_cur_ch <= {3{1'b0}}; + end else begin + if (layer_st | req_ch_reg_en) begin + if(req_ch_left_w > {{8{1'b0}}, req_ch_mode}) + req_cur_ch <= req_ch_mode; + else + req_cur_ch <= req_ch_left_w[2:0]; + end + end +end +///////////// atomic counter ///////////// +// assign req_atm_sel_inc = req_atm_sel + 1'b1; +// assign is_req_atm_sel_end = (req_atm_sel_inc == req_cur_ch); +// assign req_atm_sel_w = ~is_running ? 1'b0 : +// (is_req_atm_sel_end | is_req_atm_end) ? 2'b0: +// req_atm_sel_inc[1:0]; +assign is_req_atm_end = ((req_cur_ch == 3'h1) & (&is_atm_done[ 0])) + | ((req_cur_ch == 3'h2) & (&is_atm_done[1:0])) + | ((req_cur_ch == 3'h3) & (&is_atm_done[2:0])) + | ((req_cur_ch == 3'h4) & (&is_atm_done[3:0])); +assign req_atm = req_csm_sel ? req_atomic_1_d3 : req_atomic_0_d3; +assign is_atm_done[0] = (req_atm_cnt_0 == req_atm); +assign is_atm_done[1] = (req_atm_cnt_1 == req_atm); +assign is_atm_done[2] = (req_atm_cnt_2 == req_atm); +assign is_atm_done[3] = (req_atm_cnt_3 == req_atm); +assign req_atm_cnt = (req_atm_sel == 2'h0) ? req_atm_cnt_0 : + (req_atm_sel == 2'h1) ? req_atm_cnt_1 : + (req_atm_sel == 2'h2) ? req_atm_cnt_2 : + (req_atm_sel == 2'h3) ? req_atm_cnt_3 : 14'd0; +assign {mon_req_atm_cnt_inc, req_atm_cnt_inc} = req_atm_cnt + req_atm_size; +assign cur_atm_done = (req_atm_sel == 2'h0) ? is_atm_done[0] : + (req_atm_sel == 2'h1) ? is_atm_done[1] : + (req_atm_sel == 2'h2) ? is_atm_done[2] : + (req_atm_sel == 2'h3) ? is_atm_done[3] : 1'b0; +assign {mon_req_atm_left, req_atm_left} = req_atm - req_atm_cnt; +assign {mon_req_atm_size_addr_limit, req_atm_size_addr_limit} = (req_atm_cnt == 14'b0) ? (4'h8 - req_addr[2:0]) : 4'h8; +assign req_atm_size = (req_atm_left < {{10{1'b0}}, req_atm_size_addr_limit}) ? req_atm_left[3:0] : req_atm_size_addr_limit; +assign {mon_req_atm_size_out, req_atm_size_out} = req_atm_size - 1'b1; +assign req_atm_cnt_0_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +assign req_atm_cnt_1_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +assign req_atm_cnt_2_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +assign req_atm_cnt_3_w = (~is_running | is_req_atm_end) ? 14'b0 : req_atm_cnt_inc; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_sel <= {2{1'b0}}; + end else if(~is_running) begin + req_atm_sel <= {2{1'b0}}; + end else begin + if (req_atm_reg_en) begin + if(is_req_atm_sel_end | is_req_atm_end) + req_atm_sel <= {2{1'b0}}; + else + req_atm_sel <= req_atm_sel + 1'b1; + end + end +end +assign is_req_atm_sel_end = ({2'd0,req_atm_sel} == (req_cur_ch-1)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_0 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_0) == 1'b1) begin + req_atm_cnt_0 <= req_atm_cnt_0_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_1 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_1) == 1'b1) begin + req_atm_cnt_1 <= req_atm_cnt_1_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_2 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_2) == 1'b1) begin + req_atm_cnt_2 <= req_atm_cnt_2_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_atm_cnt_3 <= {14{1'b0}}; + end else begin + if ((layer_st | req_atm_reg_en_3) == 1'b1) begin + req_atm_cnt_3 <= req_atm_cnt_3_w; + end + end +end +///////////// address counter ///////////// +assign req_addr_ori = {reg2dp_datain_addr_high_0, reg2dp_datain_addr_low_0}; +assign {mon_req_addr_grain_base_inc,req_addr_grain_base_inc} = req_addr_grain_base + grain_addr; +assign {mon_req_addr_batch_base_inc,req_addr_batch_base_inc} = req_addr_batch_base + reg2dp_batch_stride; +assign req_addr_ch_base_add = /*(is_data_shrink) ? {reg2dp_surf_stride, 2'b0} : */ +//{1'b0, reg2dp_surf_stride, 1'b0}; +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $k; +//: if(${dmaif} < ${atmc}) { +//: $k=$dmaif; +//: } else { +//: $k=$atmc; +//: } +//: if($k == 1) { +//: print "{2'b0, reg2dp_surf_stride}; \n"; +//: } elsif($k == 2) { +//: print "{1'b0, reg2dp_surf_stride, 1'b0}; \n"; +//: } elsif($k == 4) { +//: print "{reg2dp_surf_stride, 2'b0}; \n"; +//: } +assign {mon_req_addr_ch_base_inc, req_addr_ch_base_inc} = req_addr_ch_base + req_addr_ch_base_add; +assign {mon_req_addr_base_inc, req_addr_base_inc} = req_addr_base + reg2dp_surf_stride; +assign req_addr_grain_base_w = is_first_running ? req_addr_ori : req_addr_grain_base_inc; +assign req_addr_batch_base_w = is_first_running ? req_addr_ori : + is_req_batch_end ? req_addr_grain_base_inc : req_addr_batch_base_inc; +assign req_addr_ch_base_w = is_first_running ? req_addr_ori : + (is_req_ch_end & is_req_batch_end) ? req_addr_grain_base_inc : + is_req_ch_end ? req_addr_batch_base_inc : req_addr_ch_base_inc; +assign req_addr_base_w = is_first_running ? req_addr_ori : + (is_req_atm_end & is_req_ch_end & is_req_batch_end) ? req_addr_grain_base_inc : + (is_req_atm_end & is_req_ch_end) ? req_addr_batch_base_inc : + is_req_atm_end ? req_addr_ch_base_inc : + is_req_atm_sel_end ? req_addr_ch_base : req_addr_base_inc; +assign {mon_req_addr, req_addr} = req_addr_base + req_atm_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_grain_base <= 0; + end else if ((is_first_running | req_grain_reg_en) == 1'b1) begin + req_addr_grain_base <= req_addr_grain_base_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_batch_base <= 0; + end else begin + if ((is_first_running | req_batch_reg_en) == 1'b1) begin + req_addr_batch_base <= req_addr_batch_base_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_ch_base <= 0; + end else begin + if ((is_first_running | req_ch_reg_en) == 1'b1) begin + req_addr_ch_base <= req_addr_ch_base_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_base <= 0; + end else begin + if ((is_first_running | req_atm_reg_en) == 1'b1) begin + req_addr_base <= req_addr_base_w; + end + end +end +///////////// request package ///////////// +assign req_valid_d0 = is_running & req_pre_valid & cbuf_is_ready & ~cur_atm_done; +// assign req_valid_d1_w = ~is_running ? 1'b0 : +// req_valid_d0 ? 1'b1 : +// req_ready_d1 ? 1'b0 : +// req_valid_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_valid_d1 <= 1'b0; + end else if(~is_running) begin + req_valid_d1 <= 1'b0; + end else if(req_valid_d0) begin + req_valid_d1 <= 1'b1; + end else if(req_ready_d1) begin + req_valid_d1 <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_addr_d1 <= 0; + end else begin + if ((req_reg_en) == 1'b1) begin + req_addr_d1 <= req_addr; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_d1 <= {4{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_size_d1 <= req_atm_size; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_out_d1 <= {3{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_size_out_d1 <= req_atm_size_out; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_ch_idx_d1 <= {2{1'b0}}; + end else begin + if ((req_reg_en) == 1'b1) begin + req_ch_idx_d1 <= req_atm_sel; + end + end +end +///////////// control logic ///////////// +assign req_ready_d1 = dma_req_fifo_ready & dma_rd_req_rdy; +assign req_ready_d0 = req_ready_d1 | ~req_valid_d1; +assign req_reg_en = req_pre_valid & cbuf_is_ready & ~cur_atm_done & req_ready_d0; +assign req_atm_reg_en = req_pre_valid & cbuf_is_ready & (cur_atm_done | req_ready_d0); +assign req_atm_reg_en_0 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h0) & ~is_atm_done[0] & req_ready_d0)); +assign req_atm_reg_en_1 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h1) & ~is_atm_done[1] & req_ready_d0)); +assign req_atm_reg_en_2 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h2) & ~is_atm_done[2] & req_ready_d0)); +assign req_atm_reg_en_3 = req_pre_valid & cbuf_is_ready & (is_req_atm_end | ((req_atm_sel == 2'h3) & ~is_atm_done[2] & req_ready_d0)); +//When is_req_atm_end is set, we don't need to wait cbuf_is_ready; +assign req_ch_reg_en = req_pre_valid & is_req_atm_end; +assign req_batch_reg_en = req_pre_valid & is_req_atm_end & is_req_ch_end; +assign req_grain_reg_en = req_pre_valid & is_req_atm_end & is_req_ch_end & is_req_batch_end; +//////////////////////////////////////////////////////////////////////// +// CDMA DC read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_datain_ram_type) + ,.mcif_rd_req_pd (dc_dat2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (dc_dat2mcif_rd_req_valid) + ,.mcif_rd_req_ready (dc_dat2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2dc_dat_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2dc_dat_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2dc_dat_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////// +assign dma_rd_req_pd[32 -1:0] = dma_rd_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_rd_req_size[14:0]; +assign dma_rd_req_vld = dma_req_fifo_ready & req_valid_d1; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: my $k = 32; +//: print "assign dma_rd_req_addr_f = {req_addr_d1, ${atmbw}'d0}; \n"; +//: print "assign dma_rd_req_addr = dma_rd_req_addr_f[${k}-1:0]; \n"; +assign dma_rd_req_size = {{13{1'b0}}, req_size_out_d1}; +assign dma_rd_req_type = reg2dp_datain_ram_type; +assign dma_rd_rsp_rdy = ~is_blocking; +NV_NVDLA_CDMA_DC_fifo u_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[5:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w + ,.rd_data (dma_rsp_fifo_data[5:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = req_valid_d1 & dma_rd_req_rdy; +assign dma_req_fifo_data = {req_ch_idx_d1, req_size_d1}; +//////////////////////////////////////////////////////////////////////// +// CDMA DC read response connection // +//////////////////////////////////////////////////////////////////////// +////: my $dmaif=NVDLA_CDMA_DMAIF_BW; +////: my $atmm = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_CDMA_BPE; ##atomic_m BW +////: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +////: print qq( +////: assign dma_rd_rsp_data[${dmaif}-1:0] = dma_rd_rsp_pd[${dmaif}-1:0]; +////: ); +////: if($M>1) { +////: print qq( +////: assign dma_rd_rsp_mask[${M}-1:0] = dma_rd_rsp_pd[${dmaif}+${M}-1:${dmaif}]; +////: ); +////: } +assign dma_rd_rsp_data[64 -1:0] = dma_rd_rsp_pd[64 -1:0]; +assign dma_rd_rsp_mask[( 64 + (64/8/8) )-64 -1:0] = dma_rd_rsp_pd[( 64 + (64/8/8) )-1:64]; +assign {dma_rsp_ch_idx, dma_rsp_size} = dma_rsp_fifo_data; +wire [1:0] active_atom_num; +assign active_atom_num = 2'd0 +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1){ +//: print qq( +//: + dma_rd_rsp_mask[$k] +//: ); +//: } +//: print "; "; +assign {mon_dma_rsp_size_cnt_inc,dma_rsp_size_cnt_inc} = dma_rsp_size_cnt + active_atom_num; +assign { +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: if($M>1) { +//: foreach my $k (0..$M-2){ +//: my $i = $M -$k -1; +//: print qq( dma_rsp_data_p${i}, ); +//: } +//: } +//: print qq( dma_rsp_data_p0} = dma_rd_rsp_data; ); +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 4'b0 : dma_rsp_size_cnt_inc; +assign dma_rsp_fifo_ready = (dma_rd_rsp_vld & ~is_blocking & (dma_rsp_size_cnt_inc == dma_rsp_size)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rsp_size_cnt <= {4{1'b0}}; + end else begin + if ((dma_rd_rsp_vld & ~is_blocking) == 1'b1) begin + dma_rsp_size_cnt <= dma_rsp_size_cnt_w; + end + end +end +//////////////////////////////////////////////////////////////////////// +// DC read data to shared buffer // +//////////////////////////////////////////////////////////////////////// +assign is_rsp_ch0 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h0); +assign is_rsp_ch1 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h1); +assign is_rsp_ch2 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h2); +assign is_rsp_ch3 = dma_rsp_fifo_req & (dma_rsp_ch_idx == 2'h3); +assign ch0_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch0; +assign ch1_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch1; +assign ch2_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch2; +assign ch3_wr_addr_cnt_reg_en = dma_rd_rsp_vld & ~is_blocking & is_running & is_rsp_ch3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch0_p0_wr_addr_cnt,ch0_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch0_p1_wr_addr_cnt,ch0_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch0_p0_wr_addr_cnt,ch0_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch0_p1_wr_addr_cnt,ch0_p1_wr_addr_cnt} <= 7'b1; + end else if(ch0_wr_addr_cnt_reg_en) begin + {mon_ch0_p0_wr_addr_cnt,ch0_p0_wr_addr_cnt} <= ch0_p0_wr_addr_cnt + {4'd0, active_atom_num}; + {mon_ch0_p1_wr_addr_cnt,ch0_p1_wr_addr_cnt} <= ch0_p1_wr_addr_cnt + {4'd0, active_atom_num}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch1_p0_wr_addr_cnt,ch1_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch1_p1_wr_addr_cnt,ch1_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch1_p0_wr_addr_cnt,ch1_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch1_p1_wr_addr_cnt,ch1_p1_wr_addr_cnt} <= 7'b1; + end else if (ch1_wr_addr_cnt_reg_en)begin + {mon_ch1_p0_wr_addr_cnt,ch1_p0_wr_addr_cnt} <= ch1_p0_wr_addr_cnt + {4'd0,active_atom_num}; + {mon_ch1_p1_wr_addr_cnt,ch1_p1_wr_addr_cnt} <= ch1_p1_wr_addr_cnt + {4'd0,active_atom_num}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch2_p0_wr_addr_cnt,ch2_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch2_p1_wr_addr_cnt,ch2_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch2_p0_wr_addr_cnt,ch2_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch2_p1_wr_addr_cnt,ch2_p1_wr_addr_cnt} <= 7'b1; + end else if (ch2_wr_addr_cnt_reg_en) begin + {mon_ch2_p0_wr_addr_cnt,ch2_p0_wr_addr_cnt} <= ch2_p0_wr_addr_cnt + {4'd0, active_atom_num}; + {mon_ch2_p1_wr_addr_cnt,ch2_p1_wr_addr_cnt} <= ch2_p1_wr_addr_cnt + {4'd0, active_atom_num}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch3_p0_wr_addr_cnt,ch3_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch3_p1_wr_addr_cnt,ch3_p1_wr_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch3_p0_wr_addr_cnt,ch3_p0_wr_addr_cnt} <= {7{1'b0}}; + {mon_ch3_p1_wr_addr_cnt,ch3_p1_wr_addr_cnt} <= 7'b1; + end else if (ch3_wr_addr_cnt_reg_en) begin + {mon_ch3_p0_wr_addr_cnt,ch3_p0_wr_addr_cnt} <= ch3_p0_wr_addr_cnt + {4'd0, active_atom_num}; + {mon_ch3_p1_wr_addr_cnt,ch3_p1_wr_addr_cnt} <= ch3_p1_wr_addr_cnt + {4'd0, active_atom_num}; + end +end +assign ch0_p0_wr_addr = {2'h0, ch0_p0_wr_addr_cnt[0], ch0_p0_wr_addr_cnt[8 -3:1]}; +assign ch0_p1_wr_addr = {2'h0, ch0_p1_wr_addr_cnt[0], ch0_p1_wr_addr_cnt[8 -3:1]}; +assign ch1_p0_wr_addr = {2'h1, ch1_p0_wr_addr_cnt[0], ch1_p0_wr_addr_cnt[8 -3:1]}; +assign ch1_p1_wr_addr = {2'h1, ch1_p1_wr_addr_cnt[0], ch1_p1_wr_addr_cnt[8 -3:1]}; +assign ch2_p0_wr_addr = {2'h2, ch2_p0_wr_addr_cnt[0], ch2_p0_wr_addr_cnt[8 -3:1]}; +assign ch2_p1_wr_addr = {2'h2, ch2_p1_wr_addr_cnt[0], ch2_p1_wr_addr_cnt[8 -3:1]}; +assign ch3_p0_wr_addr = {2'h3, ch3_p0_wr_addr_cnt[0], ch3_p0_wr_addr_cnt[8 -3:1]}; +assign ch3_p1_wr_addr = {2'h3, ch3_p1_wr_addr_cnt[0], ch3_p1_wr_addr_cnt[8 -3:1]}; +//////////////////////////////////////////////////////////////////////// +// Shared buffer write signals // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: if($M > 1) { +//: print qq( +//: assign p${k}_wr_en = is_running & dma_rd_rsp_vld & ~is_blocking & dma_rd_rsp_mask[$k]; +//: ); +//: } else { +//: print qq( +//: assign p${k}_wr_en = is_running & dma_rd_rsp_vld & ~is_blocking; +//: ); +//: } +//: print qq( +//: assign p${k}_wr_addr = ({8 {p${k}_wr_en & is_rsp_ch0}} & ch0_p${k}_wr_addr) +//: | ({8 {p${k}_wr_en & is_rsp_ch1}} & ch1_p${k}_wr_addr) +//: | ({8 {p${k}_wr_en & is_rsp_ch2}} & ch2_p${k}_wr_addr) +//: | ({8 {p${k}_wr_en & is_rsp_ch3}} & ch3_p${k}_wr_addr); +//: assign dc2sbuf_p${k}_wr_en = p${k}_wr_en; +//: assign dc2sbuf_p${k}_wr_addr = p${k}_wr_addr; +//: assign dc2sbuf_p${k}_wr_data = dma_rsp_data_p${k}; +//: ); +//: } +//////////////////////////////////////////////////////////////////////// +// DC local buffer count // +//////////////////////////////////////////////////////////////////////// +assign ch0_cnt_add = (ch0_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch1_cnt_add = (ch1_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch2_cnt_add = (ch2_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch3_cnt_add = (ch3_wr_addr_cnt_reg_en) ? active_atom_num : 2'h0; +assign ch0_cnt_sub = (ch0_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +assign ch1_cnt_sub = (ch1_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +assign ch2_cnt_sub = (ch2_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +assign ch3_cnt_sub = (ch3_rd_addr_cnt_reg_en) ? rsp_ch0_rd_size : 3'h0; +// assign ch1_cnt_sub = (ch1_rd_addr_cnt_reg_en) ? 1'b1 : 1'h0; +// assign ch2_cnt_sub = (ch2_rd_addr_cnt_reg_en) ? 1'b1 : 1'h0; +// assign ch3_cnt_sub = (ch3_rd_addr_cnt_reg_en) ? 1'b1 : 1'h0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch0_cnt,ch0_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch0_cnt,ch0_cnt} <= {6{1'b0}}; + end else if (ch0_wr_addr_cnt_reg_en | ch0_rd_addr_cnt_reg_en) begin + {mon_ch0_cnt,ch0_cnt} <= ch0_cnt + ch0_cnt_add - ch0_cnt_sub; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch1_cnt,ch1_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch1_cnt,ch1_cnt} <= {6{1'b0}}; + end else if (ch1_wr_addr_cnt_reg_en | ch1_rd_addr_cnt_reg_en) begin + {mon_ch1_cnt,ch1_cnt} <= ch1_cnt + ch1_cnt_add - ch1_cnt_sub; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch2_cnt,ch2_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch2_cnt,ch2_cnt} <= {6{1'b0}}; + end else if (ch2_wr_addr_cnt_reg_en | ch2_rd_addr_cnt_reg_en) begin + {mon_ch2_cnt,ch2_cnt} <= ch2_cnt + ch2_cnt_add - ch2_cnt_sub; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch3_cnt,ch3_cnt} <= {6{1'b0}}; + end else if(layer_st) begin + {mon_ch3_cnt,ch3_cnt} <= {6{1'b0}}; + end else if (ch3_wr_addr_cnt_reg_en | ch3_rd_addr_cnt_reg_en) begin + {mon_ch3_cnt,ch3_cnt} <= ch3_cnt + ch3_cnt_add - ch3_cnt_sub; + end +end +//////////////////////////////////////////////////////////////////////// +// DC response data counter---DC reading from Sbuf // +//////////////////////////////////////////////////////////////////////// +///////////// all height counter ///////////// +assign {mon_rsp_all_h_cnt_inc, + rsp_all_h_cnt_inc} = rsp_all_h_cnt + rsp_cur_grain; +assign {mon_rsp_all_h_left_w, + rsp_all_h_left_w} = layer_st ? {1'b0, data_height_w} : data_height - rsp_all_h_cnt_inc; +assign rsp_cur_grain_w = (rsp_all_h_left_w > {{2{1'b0}}, fetch_grain_w}) ? fetch_grain_w : rsp_all_h_left_w[11:0]; +assign is_rsp_all_h_end = (rsp_all_h_cnt_inc == data_height); +assign is_rsp_done = ~reg2dp_op_en | (rsp_all_h_cnt == data_height); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_all_h_cnt <= {14{1'b0}}; + end else if (layer_st) begin + rsp_all_h_cnt <= {14{1'b0}}; + end else begin + if (rsp_all_h_reg_en) begin + rsp_all_h_cnt <= rsp_all_h_cnt_inc; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_cur_grain <= {12{1'b0}}; + end else begin + if ((layer_st | rsp_all_h_reg_en) == 1'b1) begin + rsp_cur_grain <= rsp_cur_grain_w; + end + end +end +///////////// batch counter ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_batch_cnt <= {5{1'b0}}; + end else if (layer_st) begin + rsp_batch_cnt <= {5{1'b0}}; + end else if(rsp_batch_reg_en) begin + if (is_rsp_batch_end) + rsp_batch_cnt <= {5{1'b0}}; + else + rsp_batch_cnt <= rsp_batch_cnt + 1'b1; + end +end +assign is_rsp_batch_end = (rsp_batch_cnt == reg2dp_batches); +///////////// channel counter ///////////// +assign rsp_ch_mode = req_ch_mode; +assign {mon_rsp_ch_cnt_inc, + rsp_ch_cnt_inc} = rsp_ch_cnt + rsp_cur_ch; +assign {mon_rsp_ch_left_w,rsp_ch_left_w} = (layer_st | is_rsp_ch_end) ? {1'b0,data_surface_w} : (data_surface - rsp_ch_cnt_inc); +// assign is_rsp_ch_end = (rsp_ch_cnt_inc == data_surface); +assign rsp_cur_ch_w = (rsp_ch_left_w > {{8{1'b0}}, rsp_ch_mode}) ? rsp_ch_mode : rsp_ch_left_w[2:0]; +//assign is_rsp_ch_end = (rsp_ch_cnt == (data_surface - rsp_cur_ch)); +wire [10:0] data_surface_dec_1; +wire mon_data_surface_dec_1; +assign {mon_data_surface_dec_1,data_surface_dec_1} = data_surface-{8'd0,rsp_cur_ch}; +assign is_rsp_ch_end = (rsp_ch_cnt == data_surface_dec_1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_rsp_ch_cnt,rsp_ch_cnt} <= {12{1'b0}}; + end else if (layer_st) begin + {mon_rsp_ch_cnt,rsp_ch_cnt} <= {12{1'b0}}; + end else if (rsp_ch_reg_en) begin + if(is_rsp_ch_end) + {mon_rsp_ch_cnt,rsp_ch_cnt} <= {12{1'b0}}; + else + {mon_rsp_ch_cnt,rsp_ch_cnt} <= rsp_ch_cnt + rsp_cur_ch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_cur_ch <= {3{1'b0}}; + end else begin + if ((layer_st | rsp_ch_reg_en) == 1'b1) begin + rsp_cur_ch <= rsp_cur_ch_w; + end + end +end +///////////// height counter ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_h_cnt <= {12{1'b0}}; + end else if (layer_st) begin + rsp_h_cnt <= {12{1'b0}}; + end else if(rsp_h_reg_en) begin + if (is_rsp_h_end) + rsp_h_cnt <= {12{1'b0}}; + else + rsp_h_cnt <= rsp_h_cnt + 1'b1; + end +end +assign is_rsp_h_end = (rsp_h_cnt == rsp_cur_grain-1); +///////////// width counter ///////////// +assign rsp_w_left1 = (rsp_w_cnt == {1'b0, data_width_sub_one}); +//assign rsp_w_left2 = (rsp_w_cnt == {1'b0, data_width-3'd2}); +//assign rsp_w_left3 = (rsp_w_cnt == {1'b0, data_width-3'd3}); +//assign rsp_w_left4 = (rsp_w_cnt == {1'b0, data_width-3'd4}); +wire mon_data_width_dec2; +wire [15:0] data_width_dec2; +wire mon_data_width_dec3; +wire [15:0] data_width_dec3; +wire mon_data_width_dec4; +wire [15:0] data_width_dec4; +assign {mon_data_width_dec2,data_width_dec2} = data_width-16'd2; +assign {mon_data_width_dec3,data_width_dec3} = data_width-16'd3; +assign {mon_data_width_dec4,data_width_dec4} = data_width-16'd4; +assign rsp_w_left2 = (rsp_w_cnt == data_width_dec2); +assign rsp_w_left3 = (rsp_w_cnt == data_width_dec3); +assign rsp_w_left4 = (rsp_w_cnt == data_width_dec4); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_rsp_w_cnt,rsp_w_cnt} <= {17{1'b0}}; + end else if (layer_st) begin + {mon_rsp_w_cnt,rsp_w_cnt} <= {17{1'b0}}; + end else if (rsp_w_reg_en) begin + if(is_rsp_w_end) + {mon_rsp_w_cnt,rsp_w_cnt} <= {17{1'b0}}; + else + {mon_rsp_w_cnt,rsp_w_cnt} <= rsp_w_cnt + rsp_w_cnt_add; + end +end +//assign is_rsp_w_end = (rsp_w_cnt == (data_width-rsp_w_cnt_add)); +wire mon_width_dec; +wire [15:0] width_dec; +assign {mon_width_dec,width_dec} = data_width - {13'd0, rsp_w_cnt_add}; +assign is_rsp_w_end = (rsp_w_cnt == width_dec); +///////////// response control signal ///////////// +// +assign rsp_ch0_rd_one = ~(rsp_cur_ch == 3'h1) | + rsp_w_left1 | + (is_data_normal & rsp_ch_cnt[1])/* | + (is_data_shrink & rsp_ch_cnt[2])*/; +// assign rsp_rd_one = ((rsp_cur_ch == 3'h1) & rsp_w_left1) | +// ((rsp_cur_ch == 3'h1) & is_data_normal & rsp_ch_cnt[1]) | +// ((rsp_cur_ch == 3'h1) & is_data_shrink & rsp_ch_cnt[2]) | +// ((rsp_cur_ch == 3'h3) & is_data_shrink & rsp_ch_cnt[2] & rsp_rd_ch2ch3); +always @(*) +begin +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: ##my $m = int($dmaif/$atmc); +//: ##if(($dmaif==1) && ($atmc==1)) { +//: if($dmaif==1) { +//: print qq( +//: rsp_rd_more_atmm[2:0] = 3'd0; +//: ); +//: } elsif(($dmaif==2) && ($atmc==1)) { +//: print qq( +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: ); +//: } elsif(($dmaif==4) && ($atmc==1)) { +//: print qq( +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else if(rsp_w_left3) +//: rsp_rd_more_atmm[2:0] = 3'b011; +//: else +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: ); +//: } elsif(($dmaif==2) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else begin +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end else begin//(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else if(rsp_w_left3) +//: rsp_rd_more_atmm[2:0] = 3'b011; +//: else //(rsp_w_left4) +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else// if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd4) begin +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end else if(rsp_cur_ch == 3'd3) begin +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end else if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: end else begin // if(rsp_w_left2) begin +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) +//: rsp_rd_more_atmm[2:0] = 3'b000; +//: else if(rsp_w_left2) +//: rsp_rd_more_atmm[2:0] = 3'b001; +//: else if(rsp_w_left3) +//: rsp_rd_more_atmm[2:0] = 3'b011; +//: else //(rsp_w_left4) +//: rsp_rd_more_atmm[2:0] = 3'b111; +//: end +//: ); +//: } +end +// assign rsp_w_cnt_add = (rsp_ch0_rd_one) ? 2'h1 : 2'h2; +assign rsp_ch0_rd_size = rsp_w_cnt_add; +// +// assign rsp_w_reg_en = ~is_rsp_done & is_running & +// ((rsp_cur_ch == 3'h1 & (ch0_cnt >= {3'b0, rsp_w_cnt_add})) +// | (rsp_cur_ch == 3'h2 & ch0_aval & ch1_aval) +// | (rsp_cur_ch > 3'h2 & rsp_rd_ch2ch3)); +assign rsp_w_reg_en = rsp_rd_en; +assign rsp_h_reg_en = rsp_w_reg_en & is_rsp_w_end; +assign rsp_ch_reg_en = rsp_h_reg_en & is_rsp_h_end; +assign rsp_batch_reg_en = rsp_ch_reg_en & is_rsp_ch_end; +assign rsp_all_h_reg_en = rsp_batch_reg_en & is_rsp_batch_end; +//////////////////////////////////////////////////////////////////////// +// generate shared buffer rd signals // +//////////////////////////////////////////////////////////////////////// +///////////// read enable signal ///////////// +assign ch0_aval = (|ch0_cnt); +assign ch1_aval = (|ch1_cnt); +assign ch2_aval = (|ch2_cnt); +assign ch3_aval = (|ch3_cnt); +// assign rsp_rd_en = ~is_rsp_done & is_running & +// ((rsp_cur_ch == 3'h1 & (ch0_cnt >= {3'b0, rsp_w_cnt_add})) | +// (rsp_cur_ch == 3'h2 & ch0_aval & ch1_aval) | +// (rsp_cur_ch == 3'h3 & ~rsp_rd_ch2ch3 & ch0_aval & ch1_aval) | +// (rsp_cur_ch == 3'h3 & rsp_rd_ch2ch3 & ch2_aval) | +// (rsp_cur_ch == 3'h4 & ~rsp_rd_ch2ch3 & ch0_aval & ch1_aval) | +// (rsp_cur_ch == 3'h4 & rsp_rd_ch2ch3 & ch2_aval & ch3_aval)); +always @(*) +begin + if(~is_rsp_done & is_running) begin +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: ##my $m = int($dmaif/$atmc); +//: ##if(($dmaif==1) && ($atmc==1)) { +//: if($dmaif==1) { +//: print qq( +//: rsp_rd_en = ch0_aval; +//: rsp_w_cnt_add = 3'd1; +//: ); +//: } elsif(($dmaif==2) && ($atmc==1)) { +//: print qq( +//: rsp_rd_en = ch0_aval; +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else +//: rsp_w_cnt_add = 3'd2; +//: ); +//: } elsif(($dmaif==4) && ($atmc==1)) { +//: print qq( +//: rsp_rd_en = ch0_aval; +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: else if(rsp_w_left3) +//: rsp_w_cnt_add = 3'd3; +//: else +//: rsp_w_cnt_add = 3'd4; +//: ); +//: } elsif(($dmaif==2) && ($atmc==2)) { +//: print qq( +//: rsp_w_cnt_add = 3'd1; +//: if(rsp_cur_ch == 3'd2) +//: rsp_rd_en = ch0_aval & ch1_aval; +//: else //rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: ); +//: } elsif(($dmaif==4) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: rsp_rd_en = ch0_aval; +//: rsp_w_cnt_add = 3'd1; +//: end else begin//(rsp_w_left2) +//: rsp_rd_en = ch0_aval & ch1_aval; +//: rsp_w_cnt_add = 3'd2; +//: end +//: end else begin//rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: else if(rsp_w_left3) +//: rsp_w_cnt_add = 3'd1; +//: else //(rsp_w_left4) +//: rsp_w_cnt_add = 3'd4; +//: end +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: rsp_rd_en = ch0_aval & ch1_aval; +//: rsp_w_cnt_add = 3'd1; +//: end else begin//rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else// if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd4) begin +//: rsp_w_cnt_add = 3'd1; +//: rsp_rd_en = ch0_aval & ch1_aval & ch2_aval & ch3_aval; +//: end else if(rsp_cur_ch == 3'd3) begin +//: rsp_w_cnt_add = 3'd1; +//: rsp_rd_en = ch0_aval & ch1_aval & ch2_aval; +//: end else if(rsp_cur_ch == 3'd2) begin +//: rsp_rd_en = ch0_aval & ch1_aval; +//: if(rsp_w_left1) begin +//: rsp_w_cnt_add = 3'd1; +//: end else begin // if(rsp_w_left2) begin +//: rsp_w_cnt_add = 3'd2; +//: end +//: end else begin//rsp_cur_ch==1 +//: rsp_rd_en = (ch0_cnt >= {2'b0, rsp_w_cnt_add}); +//: if(rsp_w_left1) +//: rsp_w_cnt_add = 3'd1; +//: else if(rsp_w_left2) +//: rsp_w_cnt_add = 3'd2; +//: else if(rsp_w_left3) +//: rsp_w_cnt_add = 3'd1; +//: else //(rsp_w_left4) +//: rsp_w_cnt_add = 3'd4; +//: end +//: ); +//: } + end else begin + rsp_rd_en = 1'b0; + rsp_w_cnt_add = 3'd0; + end +end +assign p0_rd_en_w = rsp_rd_en; +// assign p1_rd_en_w = rsp_rd_en & ~rsp_rd_one; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: if($M > 1) { +//: foreach my $k (0..$M-2) { +//: my $i = $k +1; +//: print qq( +//: assign p${i}_rd_en_w = rsp_rd_en & rsp_rd_more_atmm[$k]; +//: ); +//: } +//: } +///////////// channel address counter ///////////// +assign ch0_rd_addr_cnt_reg_en = rsp_rd_en & ~rsp_rd_ch2ch3; +assign ch1_rd_addr_cnt_reg_en = rsp_rd_en & (rsp_cur_ch >= 3'h2) & ~rsp_rd_ch2ch3; +assign ch2_rd_addr_cnt_reg_en = rsp_rd_en & (rsp_cur_ch >= 3'h3) & rsp_rd_ch2ch3; +assign ch3_rd_addr_cnt_reg_en = rsp_rd_en & (rsp_cur_ch == 3'h4) & rsp_rd_ch2ch3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch0_p0_rd_addr_cnt,ch0_p0_rd_addr_cnt} <= 7'b0; + {mon_ch0_p1_rd_addr_cnt,ch0_p1_rd_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch0_p0_rd_addr_cnt,ch0_p0_rd_addr_cnt} <= 7'b0; + {mon_ch0_p1_rd_addr_cnt,ch0_p1_rd_addr_cnt} <= 7'b1; + end else if(ch0_rd_addr_cnt_reg_en) begin + {mon_ch0_p0_rd_addr_cnt,ch0_p0_rd_addr_cnt} <= ch0_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + {mon_ch0_p1_rd_addr_cnt,ch0_p1_rd_addr_cnt} <= ch0_p1_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch1_p0_rd_addr_cnt,ch1_p0_rd_addr_cnt} <= 7'b0; + {mon_ch1_p1_rd_addr_cnt,ch1_p1_rd_addr_cnt} <= 7'b1; + end else if(layer_st) begin + {mon_ch1_p0_rd_addr_cnt,ch1_p0_rd_addr_cnt} <= 7'b0; + {mon_ch1_p1_rd_addr_cnt,ch1_p1_rd_addr_cnt} <= 7'b1; + end else if(ch1_rd_addr_cnt_reg_en) begin + {mon_ch1_p0_rd_addr_cnt,ch1_p0_rd_addr_cnt} <= ch1_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + {mon_ch1_p1_rd_addr_cnt,ch1_p1_rd_addr_cnt} <= ch1_p1_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch2_p0_rd_addr_cnt,ch2_p0_rd_addr_cnt} <= 7'b0; + end else if(layer_st) begin + {mon_ch2_p0_rd_addr_cnt,ch2_p0_rd_addr_cnt} <= 7'b0; + end else if(ch2_rd_addr_cnt_reg_en) begin + {mon_ch2_p0_rd_addr_cnt,ch2_p0_rd_addr_cnt} <= ch2_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_ch3_p0_rd_addr_cnt,ch3_p0_rd_addr_cnt} <= 7'b0; + end else if(layer_st) begin + {mon_ch3_p0_rd_addr_cnt,ch3_p0_rd_addr_cnt} <= 7'b0; + end else if(ch3_rd_addr_cnt_reg_en) begin + {mon_ch3_p0_rd_addr_cnt,ch3_p0_rd_addr_cnt} <= ch3_p0_rd_addr_cnt + {3'd0,rsp_ch0_rd_size}; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_rd_ch2ch3 <= 1'b0; + end else if(layer_st) begin + rsp_rd_ch2ch3 <= 1'b0; + if (rsp_rd_en) begin + if((rsp_cur_ch <= 3'h2)) + rsp_rd_ch2ch3 <= 1'b0; + else + rsp_rd_ch2ch3 <= ~rsp_rd_ch2ch3; + end + end +end +assign ch0_p0_rd_addr = {2'h0, ch0_p0_rd_addr_cnt[0], ch0_p0_rd_addr_cnt[8 -3:1]}; +assign ch0_p1_rd_addr = {2'h0, ch0_p1_rd_addr_cnt[0], ch0_p1_rd_addr_cnt[8 -3:1]}; +assign ch1_p0_rd_addr = {2'h1, ch1_p0_rd_addr_cnt[0], ch1_p0_rd_addr_cnt[8 -3:1]}; +assign ch1_p1_rd_addr = {2'h1, ch1_p1_rd_addr_cnt[0], ch1_p1_rd_addr_cnt[8 -3:1]}; +assign ch2_p0_rd_addr = {2'h2, ch2_p0_rd_addr_cnt[0], ch2_p0_rd_addr_cnt[8 -3:1]}; +assign ch3_p0_rd_addr = {2'h3, ch3_p0_rd_addr_cnt[0], ch3_p0_rd_addr_cnt[8 -3:1]}; +///////////// shared buffer read address ///////////// +always @(*) begin +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc+0.99); +//: ##foreach my $k (0..$m-1){ +//: ## print " p${k}_rd_addr_w = 8'd0; \n"; +//: ##} +//: ##if(($dmaif==1) && ($atmc==1)) { +//: if($dmaif==1) { +//: print qq( +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: ); +//: } elsif(($dmaif==2) && ($atmc==1)) { +//: print qq( +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: ); +//: } elsif(($dmaif==4) && ($atmc==1)) { +//: print qq( +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch0_p1_rd_addr; +//: ); +//: } elsif(($dmaif==2) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: end else begin //rsp_cur_ch==1 +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==2)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else begin//(rsp_w_left2) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch1_p0_rd_addr; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = 8'd0; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left3) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = 8'd0; +//: end else begin //(rsp_w_left4) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch0_p1_rd_addr; +//: end +//: end +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = 8'd0; +//: end else begin // if(rsp_w_left2) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: end +//: end +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: if(rsp_cur_ch == 3'd4) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch2_p0_rd_addr; +//: p3_rd_addr_w = ch3_p0_rd_addr; +//: end else if(rsp_cur_ch == 3'd3) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch2_p0_rd_addr; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_cur_ch == 3'd2) begin +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else begin // if(rsp_w_left2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch1_p0_rd_addr; +//: p2_rd_addr_w = ch0_p1_rd_addr; +//: p3_rd_addr_w = ch1_p1_rd_addr; +//: end +//: end else begin//rsp_cur_ch==1 +//: if(rsp_w_left1) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = 8'd0; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left2) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = 8'd0; +//: p3_rd_addr_w = 8'd0; +//: end else if(rsp_w_left3) begin +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = 8'd0; +//: end else begin //(rsp_w_left4) +//: p0_rd_addr_w = ch0_p0_rd_addr; +//: p1_rd_addr_w = ch0_p1_rd_addr; +//: p2_rd_addr_w = ch0_p0_rd_addr; +//: p3_rd_addr_w = ch0_p1_rd_addr; +//: end +//: end +//: ); +//: } +end +// assign p0_rd_addr_w = rsp_rd_ch2ch3 ? ch2_p0_rd_addr : ch0_p0_rd_addr; +// assign p1_rd_addr_w = (rsp_cur_ch == 3'h1) ? ch0_p1_rd_addr : ( rsp_rd_ch2ch3 ? ch3_p0_rd_addr : ch1_p0_rd_addr); +///////////// blocking signal ///////////// +// assign is_blocking_w = (~is_running | layer_st) ? 1'b0 : (~is_blocking & rsp_rd_en & rsp_ch0_rd_one); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_blocking <= 1'b0; + end else if(~is_running | layer_st) begin + is_blocking <= 1'b0; + end else begin + is_blocking <= ~is_blocking & rsp_rd_en & rsp_ch0_rd_one; + end +end +///////////// output to shared buffer ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: print qq( +//: dc2sbuf_p${k}_rd_en <= 1'b0; +//: ); +//: } +//: print qq( +//: end else begin +//: ); +//: foreach my $k (0..$M-1) { +//: print qq( +//: dc2sbuf_p${k}_rd_en <= p${k}_rd_en_w; +//: ); +//: } + end +end +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $k (0..$M-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: dc2sbuf_p${k}_rd_addr <= {8{1'b0}}; +//: end else if (p${k}_rd_en_w) begin +//: dc2sbuf_p${k}_rd_addr <= p${k}_rd_addr_w; +//: end +//: end +//: ); +//: } +//////////////////////////////////////////////////////////////////////// +// generate write signal to convertor // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: if(($dmaif==1) && ($atmc==1)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: idx_ch_offset + data_width; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = 1'b0; +//: ); +//: } elsif(($dmaif==1) && ($atmc==2)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[0]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[0] & (rsp_cur_ch == 3'h2)); +//: assign cbuf_wr_hsel_w = (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[0]) ; +//: ); +//: } elsif(($dmaif==1) && ($atmc==4)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (&rsp_ch_cnt[1:0]) ? idx_ch_offset + data_width : idx_ch_offset; +//: //assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[2] & (rsp_cur_ch == 3'h1)); +//: //assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[2] & (rsp_cur_ch == 3'h2)); +//: assign is_w_cnt_div4 = is_data_normal & (data_surface[1:0] == 2'b01) & (data_surface - rsp_ch_cnt == 1); +//: assign is_w_cnt_div2 = is_data_normal & (data_surface[1:0] == 2'b10) & (data_surface - rsp_ch_cnt <= 2); +//: assign cbuf_wr_hsel_w[0] = (is_w_cnt_div4 & rsp_w_cnt[0]) | (is_w_cnt_div2 & rsp_ch_cnt[0]) | (is_data_normal & rsp_ch_cnt[0]) ; +//: assign cbuf_wr_hsel_w[1] = (is_w_cnt_div4 & rsp_w_cnt[1]) | (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[1]) ; +//: ); +//: } elsif((($dmaif==2) || ($dmaif==4)) && ($atmc==1)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: idx_ch_offset + data_width; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = 1'b0; +//: ); +//: } elsif((($dmaif==2) || ($dmaif==4)) && ($atmc==2)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[0]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = 1'b0; +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[0] & (rsp_cur_ch == 3'h2)); +//: ); +//: } elsif(($dmaif==2) && ($atmc==4)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[1]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h1)); +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h2)); +//: assign cbuf_wr_hsel_w = (is_w_cnt_div4 & rsp_w_cnt[1]) | (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[1]) ; +//: ); +//: } elsif(($dmaif==4) && ($atmc==4)) { +//: print qq( +//: assign {mon_idx_ch_offset_w, +//: idx_ch_offset_w} = (layer_st) ? 18'b0 : +//: (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +//: (rsp_ch_cnt[1]) ? idx_ch_offset + data_width : idx_ch_offset; +//: assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h1)); +//: assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h2)); +//: ); +//: } +assign {mon_idx_batch_offset_w, idx_batch_offset_w} = (layer_st | is_rsp_batch_end) ? 19'b0 : (idx_batch_offset + data_entries); +assign {mon_idx_h_offset_w, + idx_h_offset_w} = (layer_st) ? 18'b0 : + (is_rsp_h_end) ? {1'b0, idx_ch_offset_w} : + (is_rsp_all_h_end) ? idx_h_offset + rsp_batch_entry_last : idx_h_offset + rsp_batch_entry_init; +// assign {mon_idx_ch_offset_w, +// idx_ch_offset_w} = (layer_st) ? 18'b0 : +// (is_rsp_ch_end) ? {1'b0, idx_batch_offset_w} : +// (rsp_ch_cnt[1]) ? idx_ch_offset + data_width[12:0] : idx_ch_offset; +// +// assign is_w_cnt_div4 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h1)); +// assign is_w_cnt_div2 = (is_data_normal & is_rsp_ch_end & ~rsp_ch_cnt[1] & (rsp_cur_ch == 3'h2)); +// +// assign cbuf_wr_hsel_w = (is_w_cnt_div4 & rsp_w_cnt[1]) | (is_w_cnt_div2 & rsp_w_cnt[0]) | (is_data_normal & rsp_ch_cnt[1]) ; +//assign idx_w_offset_add = is_w_cnt_div4 ? {rsp_w_cnt[12 +2:2]} : ( is_w_cnt_div2 ? rsp_w_cnt[12+1 :1] : rsp_w_cnt[12:0] ); +assign idx_w_offset_add = is_w_cnt_div4 ? {1'b0,rsp_w_cnt[15:2]} : ( is_w_cnt_div2 ? rsp_w_cnt[14+1 :1] : rsp_w_cnt[14:0] ); +assign {mon_cbuf_idx_inc[2:0], cbuf_idx_inc} = idx_base + (idx_grain_offset + idx_h_offset) + idx_w_offset_add; +assign is_cbuf_idx_wrap = cbuf_idx_inc >= {1'b0, data_bank, 9'b0}; +assign cbuf_idx_w = ~is_cbuf_idx_wrap ? {2'b0, cbuf_idx_inc[14:0]} : {2'd0,cbuf_idx_inc[14 :0]} - {2'b0, data_bank, 9'b0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_base <= 0; + end else begin + if ((is_first_running) == 1'b1) begin + idx_base <= status2dma_wr_idx; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_batch_offset <= 0; + end else begin + if ((layer_st | rsp_batch_reg_en) == 1'b1) begin + idx_batch_offset <= idx_batch_offset_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_ch_offset <= 0; + end else begin + if ((layer_st | rsp_ch_reg_en) == 1'b1) begin + idx_ch_offset <= idx_ch_offset_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx_h_offset <= {18{1'b0}}; + end else begin + if ((layer_st | rsp_h_reg_en) == 1'b1) begin + idx_h_offset <= idx_h_offset_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_idx_grain_offset,idx_grain_offset} <= {19{1'b0}}; + end else if(layer_st) begin + {mon_idx_grain_offset,idx_grain_offset} <= {19{1'b0}}; + end else if(rsp_all_h_reg_en) begin + {mon_idx_grain_offset,idx_grain_offset} <= idx_grain_offset + rsp_entry; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cbuf_wr_en <= 1'b0; + end else begin + cbuf_wr_en <= rsp_rd_en; + end +end +// +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_addr_$i <= 0; +//: end else if(rsp_w_reg_en) begin +//: cbuf_wr_addr_$i <= cbuf_idx_w + $i; +//: end +//: end +//: ); +//: } +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: if($dmaif < $atmc) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_hsel <= 0; +//: end else begin +//: if ((rsp_w_reg_en) == 1'b1) begin +//: cbuf_wr_hsel <= cbuf_wr_hsel_w; +//: end +//: end +//: end +//: ); +//: } elsif($dmaif > $atmc) { +//: print qq( +//: reg [$dmaif-1:0] cbuf_wr_mask; +//: wire [$dmaif-1:0] cbuf_wr_mask_d0; +//: reg [$dmaif-1:0] cbuf_wr_mask_d1; +//: reg [$dmaif-1:0] cbuf_wr_mask_d2; +//: reg [$dmaif-1:0] cbuf_wr_mask_d3; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_mask <= 0; +//: end else begin +//: cbuf_wr_mask <= {; +//: ); +//: if($dmaif > 1) { +//: foreach my $k (0..$dmaif-2) { +//: my $i = $dmaif - $k -2; +//: print " p${i}_rd_en_w, "; +//: } +//: } +//: print qq( +//: p0_rd_en_w}; +//: end +//: end +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cbuf_wr_info_mask <= 0; + end else begin +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: print " cbuf_wr_info_mask <= {{(4-$M){1'b0}} "; +//: foreach my $k (0..$M-1) { +//: my $i = $M - $k -1; +//: print " ,p${i}_rd_en_w "; +//: } + }; + end +end +assign cbuf_wr_info_pd[3:0] = cbuf_wr_info_mask[3:0]; +assign cbuf_wr_info_pd[4] = 1'b0;//cbuf_wr_info_interleave ; +assign cbuf_wr_info_pd[5] = 1'b0;//cbuf_wr_info_ext64 ; +assign cbuf_wr_info_pd[6] = 1'b0;//cbuf_wr_info_ext128 ; +assign cbuf_wr_info_pd[7] = 1'b0;//cbuf_wr_info_mean ; +assign cbuf_wr_info_pd[8] = 1'b0;//cbuf_wr_info_uint ; +assign cbuf_wr_info_pd[11:9] = 3'd0;//cbuf_wr_info_sub_h[2:0]; +//////////////////////////////////////////////////////////////////////// +// pipeline to sync the sbuf read to output to convertor // +//////////////////////////////////////////////////////////////////////// +assign cbuf_wr_en_d0 = cbuf_wr_en; +assign cbuf_wr_info_pd_d0 = cbuf_wr_info_pd; +// +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: my $latency = (2 +1); +//: +//: if($dmaif < $atmc) { +//: print qq( assign cbuf_wr_hsel_d0 = cbuf_wr_hsel; ); +//: foreach my $i (0..$latency-1) { +//: my $j = $i + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_hsel_d${j} <= 1'b0; +//: end else if (cbuf_wr_en_d${i}) begin +//: cbuf_wr_hsel_d${j} <= cbuf_wr_hsel_d${i}; +//: end +//: end +//: ); +//: } +//: } elsif($dmaif > $atmc) { +//: print qq( assign cbuf_wr_mask_d0 = cbuf_wr_mask; ); +//: foreach my $i (0..$latency-1) { +//: my $j = $i + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_mask_d${j} <= 1'b0; +//: end else if (cbuf_wr_en_d${i}) begin +//: cbuf_wr_mask_d${j} <= cbuf_wr_mask_d${i}; +//: end +//: end +//: ); +//: } +//: } +//: ################################################################### +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: assign cbuf_wr_addr_d0_${i} = cbuf_wr_addr_${i}; +//: ); +//: foreach my $k (0..$latency-1) { +//: my $j = $k + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_addr_d${j}_${i} <= 0; +//: end else if ((cbuf_wr_en_d${k}) == 1'b1) begin +//: cbuf_wr_addr_d${j}_${i} <= cbuf_wr_addr_d${k}_${i}; +//: end +//: end +//: ); +//: } +//: } +//////////////////////////////////// +//: my $latency = (2 +1); +//: foreach my $i (0..$latency-1) { +//: my $j = $i + 1; +//: print qq ( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_en_d${j} <= 1'b0; +//: end else begin +//: cbuf_wr_en_d${j} <= cbuf_wr_en_d${i}; +//: end +//: end +//: +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: cbuf_wr_info_pd_d${j} <= {12{1'b0}}; +//: end else if(cbuf_wr_en_d${i}) begin +//: cbuf_wr_info_pd_d${j} <= cbuf_wr_info_pd_d${i}; +//: end +//: end +//: ); +//: } +// ################################################################### +//: my $latency = (2 +1); +//: my $lb = $latency - 1; +//: my $dmaif=64/8/8; +//: my $atmc=8/8; +//: if($dmaif <= $atmc) { +//: print qq ( +//: always @(posedge nvdla_core_clk) begin +//: if (cbuf_wr_en_d${lb}) begin +//: cbuf_wr_data_d${latency}_0 <= { +//: ); +//: if($dmaif > 1){ +//: foreach my $p (0..$dmaif-2){ +//: my $q = $dmaif -$p -1; +//: print qq( dc2sbuf_p${q}_rd_data, ); +//: } +//: } +//: print qq ( +//: dc2sbuf_p0_rd_data}; +//: end +//: end +//: ); +//: } else { +//: my $cnum = int($dmaif/$atmc); +//: foreach my $k (0.. $cnum-1){ +//: my $ks = $k * $atmc; +//: print qq ( +//: always @(posedge nvdla_core_clk) begin +//: if (cbuf_wr_en_d${lb}) begin +//: cbuf_wr_data_d${latency}_${k} <= { +//: ); +//: if($atmc > 1){ +//: foreach my $p (0..$atmc-2){ +//: my $q = $atmc -$p -1; +//: my $bs = $q + $ks; +//: print qq( dc2sbuf_p${bs}_rd_data, ); +//: } +//: } +//: print qq ( +//: dc2sbuf_p${ks}_rd_data}; +//: end +//: end +//: ); +//: } +//: } +//: ################################################################### +//: +//: if($dmaif <= $atmc) { +//: print qq( +//: assign dc2cvt_dat_wr_addr = cbuf_wr_addr_d${latency}_0; +//: assign dc2cvt_dat_wr_data = cbuf_wr_data_d${latency}_0; +//: ); +//: } else { +//: my $m = int($dmaif/$atmc+0.99); +//: foreach my $i (0..$m-1) { +//: print qq( +//: assign dc2cvt_dat_wr_addr${i} = cbuf_wr_addr_d${latency}_${i}; +//: assign dc2cvt_dat_wr_data${i} = cbuf_wr_data_d${latency}_${i}; +//: ); +//: } +//: } +//: ################################################################### +//: print qq ( +//: assign dc2cvt_dat_wr_en = cbuf_wr_en_d${latency}; +//: assign dc2cvt_dat_wr_info_pd = cbuf_wr_info_pd_d${latency}; +//: ); +//: ################################################################### +//: if($dmaif < $atmc) { +//: print qq ( +//: assign dc2cvt_dat_wr_sel = cbuf_wr_hsel_d${latency}; +//: ); +//: } elsif ($dmaif > $atmc) { +//: print qq ( +//: assign dc2cvt_dat_wr_mask = cbuf_wr_mask_d${latency}; +//: ); +//: } +////////////////////////////////////////////////////// +////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// convolution buffer slices & entries management // +//////////////////////////////////////////////////////////////////////// +///////////// calculate onfly slices and entries ///////////// +assign req_entry = req_csm_sel ? req_entry_1_d3[14:0] : req_entry_0_d3[14:0]; +assign rsp_entry = is_rsp_all_h_end ? rsp_entry_last : rsp_entry_init; +assign dc_entry_onfly_add = ~req_grain_reg_en ? 15'b0 : req_entry; +assign dc_entry_onfly_sub = ~dc2status_dat_updt ? 15'b0 : dc2status_dat_entries; +assign {mon_dc_entry_onfly_w, + dc_entry_onfly_w} = dc_entry_onfly + dc_entry_onfly_add - dc_entry_onfly_sub; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_entry_onfly <= {15{1'b0}}; + end else if ((req_grain_reg_en | dc2status_dat_updt) == 1'b1) begin + dc_entry_onfly <= dc_entry_onfly_w; + end +end +///////////// calculate if free entries is enough ///////////// +assign required_entries = dc_entry_onfly + req_entry; +assign is_free_entries_enough = (required_entries <= {1'b0, status2dma_free_entries}); +assign cbuf_is_ready_w = (~is_running | ~req_pre_valid | csm_reg_en) ? 1'b0 : is_free_entries_enough; +assign rsp_slice = is_rsp_all_h_end ? rsp_slice_last : rsp_slice_init; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cbuf_is_ready <= 1'b0; + end else begin + cbuf_is_ready <= cbuf_is_ready_w; + end +end +///////////// update CDMA data status ///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d0 <= 1'b0; + end else begin + dat_updt_d0 <= rsp_all_h_reg_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d0 <= {15{1'b0}}; + end else begin + if ((rsp_all_h_reg_en) == 1'b1) begin + dat_entries_d0 <= rsp_entry[14:0];//15bit is enough + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d0 <= {14{1'b0}}; + end else begin + if ((rsp_all_h_reg_en) == 1'b1) begin + dat_slices_d0 <= rsp_slice; + end + end +end +//: my $latency = (2 + 1); +//: my @list = ("updt", "entries", "slices"); +//: foreach my $i (0..$latency-1) { +//: my $k = $i + 1; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: dat_updt_d${k} <= 1'b0; +//: end else begin +//: dat_updt_d${k} <= dat_updt_d${i}; +//: end +//: end +//: ); +//: foreach my $j (1..2) { +//: my $name = $list[$j]; +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: dat_${name}_d${k} <= 0; +//: end else begin +//: if ((dat_updt_d${i}) == 1'b1) begin +//: dat_${name}_d${k} <= dat_${name}_d${i}; +//: end +//: end +//: end +//: ); +//: } +//: } +//: +//: foreach my $j (0..2) { +//: my $name = $list[$j]; +//: print qq( +//: assign dc2status_dat_${name} = dat_${name}_d${latency}; +//: ); +//: } +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_stall_inc <= 1'b0; + end else begin + dc_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_stall_clr <= 1'b0; + end else begin + dc_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_stall_cen <= 1'b0; + end else begin + dc_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_dc_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = dc_rd_stall_inc ^ dp2reg_dc_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (dc_rd_stall_inc && !dp2reg_dc_rd_stall_dec)? stl_cnt_inc : (!dc_rd_stall_inc && dp2reg_dc_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (dc_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (dc_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_dc_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_inc <= 1'b0; + end else begin + dc_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_dec <= 1'b0; + end else begin + dc_rd_latency_dec <= dma_rsp_fifo_ready & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_clr <= 1'b0; + end else begin + dc_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dc_rd_latency_cen <= 1'b0; + end else begin + dc_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign ltc_1_inc = (outs_dp2reg_dc_rd_latency!=511) & dc_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_dc_rd_latency!=511) & dc_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (dc_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (dc_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_dc_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +assign ltc_2_dec = 1'b0; +assign ltc_2_inc = (~&dp2reg_dc_rd_latency) & (|outs_dp2reg_dc_rd_latency); +// ltc_2 adv logic +always @(*) begin + ltc_2_adv = ltc_2_inc ^ ltc_2_dec; +end +// ltc_2 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_2_cnt_ext[33:0] = {1'b0, 1'b0, ltc_2_cnt_cur}; + ltc_2_cnt_inc[33:0] = ltc_2_cnt_cur + 1'b1; // spyglass disable W164b + ltc_2_cnt_dec[33:0] = ltc_2_cnt_cur - 1'b1; // spyglass disable W164b + ltc_2_cnt_mod[33:0] = (ltc_2_inc && !ltc_2_dec)? ltc_2_cnt_inc : (!ltc_2_inc && ltc_2_dec)? ltc_2_cnt_dec : ltc_2_cnt_ext; + ltc_2_cnt_new[33:0] = (ltc_2_adv)? ltc_2_cnt_mod[33:0] : ltc_2_cnt_ext[33:0]; + ltc_2_cnt_nxt[33:0] = (dc_rd_latency_clr)? 34'd0 : ltc_2_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// ltc_2 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_2_cnt_cur[31:0] <= 0; + end else begin + if (dc_rd_latency_cen) begin + ltc_2_cnt_cur[31:0] <= ltc_2_cnt_nxt[31:0]; + end + end +end +// ltc_2 output logic +always @(*) begin + dp2reg_dc_rd_latency[31:0] = ltc_2_cnt_cur[31:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_dc__cbuf_idx_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (rsp_w_reg_en & is_cbuf_idx_wrap); + endproperty +// Cover 0 : "(rsp_w_reg_en & is_cbuf_idx_wrap)" + FUNCPOINT_cdma_dc__cbuf_idx_wrap__0_COV : cover property (cdma_dc__cbuf_idx_wrap__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_dc__input_fully_connected__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (layer_st & is_packed_1x1); + endproperty +// Cover 1 : "(layer_st & is_packed_1x1)" + FUNCPOINT_cdma_dc__input_fully_connected__1_COV : cover property (cdma_dc__input_fully_connected__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_dc__dc_batch_size_EQ_0__2_0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 0); + endproperty +// Cover 2_0 : "reg2dp_batches == 0" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_0__2_0_COV : cover property (cdma_dc__dc_batch_size_EQ_0__2_0_cov); + property cdma_dc__dc_batch_size_EQ_1__2_1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 1); + endproperty +// Cover 2_1 : "reg2dp_batches == 1" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_1__2_1_COV : cover property (cdma_dc__dc_batch_size_EQ_1__2_1_cov); + property cdma_dc__dc_batch_size_EQ_2__2_2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 2); + endproperty +// Cover 2_2 : "reg2dp_batches == 2" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_2__2_2_COV : cover property (cdma_dc__dc_batch_size_EQ_2__2_2_cov); + property cdma_dc__dc_batch_size_EQ_3__2_3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 3); + endproperty +// Cover 2_3 : "reg2dp_batches == 3" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_3__2_3_COV : cover property (cdma_dc__dc_batch_size_EQ_3__2_3_cov); + property cdma_dc__dc_batch_size_EQ_4__2_4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 4); + endproperty +// Cover 2_4 : "reg2dp_batches == 4" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_4__2_4_COV : cover property (cdma_dc__dc_batch_size_EQ_4__2_4_cov); + property cdma_dc__dc_batch_size_EQ_5__2_5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 5); + endproperty +// Cover 2_5 : "reg2dp_batches == 5" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_5__2_5_COV : cover property (cdma_dc__dc_batch_size_EQ_5__2_5_cov); + property cdma_dc__dc_batch_size_EQ_6__2_6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 6); + endproperty +// Cover 2_6 : "reg2dp_batches == 6" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_6__2_6_COV : cover property (cdma_dc__dc_batch_size_EQ_6__2_6_cov); + property cdma_dc__dc_batch_size_EQ_7__2_7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 7); + endproperty +// Cover 2_7 : "reg2dp_batches == 7" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_7__2_7_COV : cover property (cdma_dc__dc_batch_size_EQ_7__2_7_cov); + property cdma_dc__dc_batch_size_EQ_8__2_8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 8); + endproperty +// Cover 2_8 : "reg2dp_batches == 8" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_8__2_8_COV : cover property (cdma_dc__dc_batch_size_EQ_8__2_8_cov); + property cdma_dc__dc_batch_size_EQ_9__2_9_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 9); + endproperty +// Cover 2_9 : "reg2dp_batches == 9" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_9__2_9_COV : cover property (cdma_dc__dc_batch_size_EQ_9__2_9_cov); + property cdma_dc__dc_batch_size_EQ_10__2_10_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 10); + endproperty +// Cover 2_10 : "reg2dp_batches == 10" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_10__2_10_COV : cover property (cdma_dc__dc_batch_size_EQ_10__2_10_cov); + property cdma_dc__dc_batch_size_EQ_11__2_11_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 11); + endproperty +// Cover 2_11 : "reg2dp_batches == 11" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_11__2_11_COV : cover property (cdma_dc__dc_batch_size_EQ_11__2_11_cov); + property cdma_dc__dc_batch_size_EQ_12__2_12_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 12); + endproperty +// Cover 2_12 : "reg2dp_batches == 12" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_12__2_12_COV : cover property (cdma_dc__dc_batch_size_EQ_12__2_12_cov); + property cdma_dc__dc_batch_size_EQ_13__2_13_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 13); + endproperty +// Cover 2_13 : "reg2dp_batches == 13" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_13__2_13_COV : cover property (cdma_dc__dc_batch_size_EQ_13__2_13_cov); + property cdma_dc__dc_batch_size_EQ_14__2_14_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 14); + endproperty +// Cover 2_14 : "reg2dp_batches == 14" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_14__2_14_COV : cover property (cdma_dc__dc_batch_size_EQ_14__2_14_cov); + property cdma_dc__dc_batch_size_EQ_15__2_15_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 15); + endproperty +// Cover 2_15 : "reg2dp_batches == 15" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_15__2_15_COV : cover property (cdma_dc__dc_batch_size_EQ_15__2_15_cov); + property cdma_dc__dc_batch_size_EQ_16__2_16_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 16); + endproperty +// Cover 2_16 : "reg2dp_batches == 16" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_16__2_16_COV : cover property (cdma_dc__dc_batch_size_EQ_16__2_16_cov); + property cdma_dc__dc_batch_size_EQ_17__2_17_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 17); + endproperty +// Cover 2_17 : "reg2dp_batches == 17" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_17__2_17_COV : cover property (cdma_dc__dc_batch_size_EQ_17__2_17_cov); + property cdma_dc__dc_batch_size_EQ_18__2_18_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 18); + endproperty +// Cover 2_18 : "reg2dp_batches == 18" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_18__2_18_COV : cover property (cdma_dc__dc_batch_size_EQ_18__2_18_cov); + property cdma_dc__dc_batch_size_EQ_19__2_19_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 19); + endproperty +// Cover 2_19 : "reg2dp_batches == 19" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_19__2_19_COV : cover property (cdma_dc__dc_batch_size_EQ_19__2_19_cov); + property cdma_dc__dc_batch_size_EQ_20__2_20_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 20); + endproperty +// Cover 2_20 : "reg2dp_batches == 20" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_20__2_20_COV : cover property (cdma_dc__dc_batch_size_EQ_20__2_20_cov); + property cdma_dc__dc_batch_size_EQ_21__2_21_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 21); + endproperty +// Cover 2_21 : "reg2dp_batches == 21" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_21__2_21_COV : cover property (cdma_dc__dc_batch_size_EQ_21__2_21_cov); + property cdma_dc__dc_batch_size_EQ_22__2_22_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 22); + endproperty +// Cover 2_22 : "reg2dp_batches == 22" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_22__2_22_COV : cover property (cdma_dc__dc_batch_size_EQ_22__2_22_cov); + property cdma_dc__dc_batch_size_EQ_23__2_23_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 23); + endproperty +// Cover 2_23 : "reg2dp_batches == 23" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_23__2_23_COV : cover property (cdma_dc__dc_batch_size_EQ_23__2_23_cov); + property cdma_dc__dc_batch_size_EQ_24__2_24_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 24); + endproperty +// Cover 2_24 : "reg2dp_batches == 24" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_24__2_24_COV : cover property (cdma_dc__dc_batch_size_EQ_24__2_24_cov); + property cdma_dc__dc_batch_size_EQ_25__2_25_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 25); + endproperty +// Cover 2_25 : "reg2dp_batches == 25" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_25__2_25_COV : cover property (cdma_dc__dc_batch_size_EQ_25__2_25_cov); + property cdma_dc__dc_batch_size_EQ_26__2_26_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 26); + endproperty +// Cover 2_26 : "reg2dp_batches == 26" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_26__2_26_COV : cover property (cdma_dc__dc_batch_size_EQ_26__2_26_cov); + property cdma_dc__dc_batch_size_EQ_27__2_27_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 27); + endproperty +// Cover 2_27 : "reg2dp_batches == 27" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_27__2_27_COV : cover property (cdma_dc__dc_batch_size_EQ_27__2_27_cov); + property cdma_dc__dc_batch_size_EQ_28__2_28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 28); + endproperty +// Cover 2_28 : "reg2dp_batches == 28" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_28__2_28_COV : cover property (cdma_dc__dc_batch_size_EQ_28__2_28_cov); + property cdma_dc__dc_batch_size_EQ_29__2_29_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 29); + endproperty +// Cover 2_29 : "reg2dp_batches == 29" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_29__2_29_COV : cover property (cdma_dc__dc_batch_size_EQ_29__2_29_cov); + property cdma_dc__dc_batch_size_EQ_30__2_30_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 30); + endproperty +// Cover 2_30 : "reg2dp_batches == 30" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_30__2_30_COV : cover property (cdma_dc__dc_batch_size_EQ_30__2_30_cov); + property cdma_dc__dc_batch_size_EQ_31__2_31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((is_running) && nvdla_core_rstn) |-> (reg2dp_batches == 31); + endproperty +// Cover 2_31 : "reg2dp_batches == 31" + FUNCPOINT_cdma_dc__dc_batch_size_EQ_31__2_31_COV : cover property (cdma_dc__dc_batch_size_EQ_31__2_31_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_dc__dc_reuse__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cur_state == DC_STATE_IDLE) & (nxt_state == DC_STATE_DONE)); + endproperty +// Cover 3 : "((cur_state == DC_STATE_IDLE) & (nxt_state == DC_STATE_DONE))" + FUNCPOINT_cdma_dc__dc_reuse__3_COV : cover property (cdma_dc__dc_reuse__3_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,2,0,"No Xs allowed on cur_state") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, cur_state); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_rsp_done | is_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | pre_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_g0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_g1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_init))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(pre_reg_en_d2_last))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_50x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | pre_reg_en_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | csm_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | req_atm_reg_en_3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_grain_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running | req_atm_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rd_rsp_vld & ~is_blocking))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch0_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch1_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch2_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch3_wr_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch0_wr_addr_cnt_reg_en | ch0_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch1_wr_addr_cnt_reg_en | ch1_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch2_wr_addr_cnt_reg_en | ch2_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch3_wr_addr_cnt_reg_en | ch3_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_103x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_all_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_107x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_108x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_115x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_w_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch0_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_117x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch1_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_118x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch2_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_119x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | ch3_rd_addr_cnt_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_121x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_123x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(p0_rd_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_124x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(p1_rd_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_125x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_126x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_batch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_127x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_ch_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_128x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_129x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | rsp_all_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_130x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_w_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_141x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cbuf_wr_en_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_144x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cbuf_wr_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_147x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cbuf_wr_en_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_150x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_grain_reg_en | dc2status_dat_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_154x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_all_h_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_156x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_158x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_160x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML +//nv_assert_never #(0,0,"Error config! data bank is not big enough!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (is_running & ((data_bank * 256) < (data_entries * data_height)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data bank is not big enough!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (is_running & ((data_bank * 512) < (data_entries * data_height)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! fifo is not empty when done!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel counter is not empty when done!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & ((|ch0_cnt) | (|ch1_cnt) | (|ch2_cnt) | (|ch3_cnt)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Req is not done when rsp is done!") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & (req_height_cnt_d1 != data_height) & ~dbg_is_last_reuse)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Req is valid when rsp is done!") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & req_pre_valid)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_onfly is non zero when idle") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, (fetch_done & |(dc_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! reg2dp_grains is overflow!") zzz_assert_never_24x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_fetch_grain_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data_entries_w is overflow!") zzz_assert_never_25x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_data_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_one_hot #(0,3,0,"Error! conflict data type mode") zzz_assert_one_hot_26x (nvdla_core_clk, `ASSERT_RESET, ({is_data_normal, is_data_expand, is_data_shrink})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_height_cnt_inc is overflow!") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (mon_req_height_cnt_d1)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_slice_left is overflow!") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, ((|mon_req_slice_left))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cur_atomic is overflow!") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (pre_reg_en_d1 & (|mon_req_cur_atomic))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_per_batch is overflow!") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (pre_reg_en_d1 & (|mon_entry_per_batch))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cur_atomic is out of range when HoG!") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (is_running & ~is_feature & (|req_cur_atomic[12 -1: 12 -2]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_required is overflow!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, ((|mon_entry_required))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_ch_left_w is overflow") zzz_assert_never_55x (nvdla_core_clk, `ASSERT_RESET, (mon_req_ch_left_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cur_ch is out of range") zzz_assert_never_56x (nvdla_core_clk, `ASSERT_RESET, (req_cur_ch > 3'h4)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_ch_cnt is large than data_surface") zzz_assert_never_57x (nvdla_core_clk, `ASSERT_RESET, (is_running & (req_ch_cnt > data_surface))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_atm_left is overflow!") zzz_assert_never_63x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & (|mon_req_atm_left))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_atm_size_addr_limit is overflow!") zzz_assert_never_64x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & (|mon_req_atm_size_addr_limit))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_atm_size_out is overflow!") zzz_assert_never_65x (nvdla_core_clk, `ASSERT_RESET, (req_reg_en & (|mon_req_atm_size_out))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_grain_base_inc is overflow!") zzz_assert_never_70x (nvdla_core_clk, `ASSERT_RESET, (req_grain_reg_en & mon_req_addr_grain_base_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_batch_base_inc is overflow!") zzz_assert_never_71x (nvdla_core_clk, `ASSERT_RESET, (req_batch_reg_en & mon_req_addr_batch_base_inc & (|reg2dp_batches))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_ch_base_inc is overflow!") zzz_assert_never_72x (nvdla_core_clk, `ASSERT_RESET, (req_ch_reg_en & mon_req_addr_ch_base_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr_base_inc is overflow!") zzz_assert_never_73x (nvdla_core_clk, `ASSERT_RESET, (req_atm_reg_en & mon_req_addr_base_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_addr is overflow!") zzz_assert_never_74x (nvdla_core_clk, `ASSERT_RESET, (req_reg_en & mon_req_addr)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Receive input data when not busy") zzz_assert_never_80x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_82x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_fifo_ready & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_83x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > dma_rsp_size)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_84x (nvdla_core_clk, `ASSERT_RESET, (mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_85x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > 8'h8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,4,0,"Error! ch_reg_en is not one hot") zzz_assert_zero_one_hot_94x (nvdla_core_clk, `ASSERT_RESET, {ch0_wr_addr_cnt_reg_en, ch1_wr_addr_cnt_reg_en, ch2_wr_addr_cnt_reg_en, ch3_wr_addr_cnt_reg_en}); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 0 is not zero when idle!") zzz_assert_never_99x (nvdla_core_clk, `ASSERT_RESET, ((|ch0_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 1 is not zero when idle!") zzz_assert_never_100x (nvdla_core_clk, `ASSERT_RESET, ((|ch1_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 2 is not zero when idle!") zzz_assert_never_101x (nvdla_core_clk, `ASSERT_RESET, ((|ch2_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Channel 3 is not zero when idle!") zzz_assert_never_102x (nvdla_core_clk, `ASSERT_RESET, ((|ch3_cnt) & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_all_h_cnt_inc is overflow") zzz_assert_never_105x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_all_h_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_all_h_left_w is overflow") zzz_assert_never_106x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_all_h_left_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_cnt_inc is overflow") zzz_assert_never_110x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_ch_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_left_w is overflow") zzz_assert_never_111x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_ch_left_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_cur_ch is out of range") zzz_assert_never_112x (nvdla_core_clk, `ASSERT_RESET, (rsp_cur_ch > 3'h4)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Blocking data response when not enabled") zzz_assert_never_122x (nvdla_core_clk, `ASSERT_RESET, (is_blocking & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! idx_batch_offset_w is overflow!") zzz_assert_never_135x (nvdla_core_clk, `ASSERT_RESET, (rsp_batch_reg_en & mon_idx_batch_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! idx_ch_offset_w is overflow!") zzz_assert_never_136x (nvdla_core_clk, `ASSERT_RESET, (rsp_ch_reg_en & mon_idx_ch_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! idx_h_offset_w is overflow!") zzz_assert_never_137x (nvdla_core_clk, `ASSERT_RESET, (rsp_h_reg_en & mon_idx_h_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cbuf_idx_inc is overflow!") zzz_assert_never_138x (nvdla_core_clk, `ASSERT_RESET, (rsp_w_reg_en & mon_cbuf_idx_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! cbuf_idx_w is overflow!") zzz_assert_never_139x (nvdla_core_clk, `ASSERT_RESET, (rsp_w_reg_en & (|mon_cbuf_idx_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Error! conflict div mode") zzz_assert_zero_one_hot_140x (nvdla_core_clk, `ASSERT_RESET, ({/*is_w_cnt_div8,*/ is_w_cnt_div4, is_w_cnt_div2})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dc_entry_onfly_w is overflow") zzz_assert_never_151x (nvdla_core_clk, `ASSERT_RESET, (mon_dc_entry_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dc_entry_onfly_w is out of range") zzz_assert_never_152x (nvdla_core_clk, `ASSERT_RESET, (dc_entry_onfly_w > 16384)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dc_entry_onfly_w is non zero when idle") zzz_assert_never_153x (nvdla_core_clk, `ASSERT_RESET, (~is_running & |(dc_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Update to status when idle!") zzz_assert_never_162x (nvdla_core_clk, `ASSERT_RESET, (dc2status_dat_updt & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_163x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && dc_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_dc diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v new file mode 100644 index 0000000..692dd68 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v @@ -0,0 +1,366 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_dma_mux.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_dma_mux ( + nvdla_core_clk + ,nvdla_core_rstn + ,dc_dat2mcif_rd_req_valid + ,dc_dat2mcif_rd_req_ready + ,dc_dat2mcif_rd_req_pd + ,img_dat2mcif_rd_req_valid + ,img_dat2mcif_rd_req_ready + ,img_dat2mcif_rd_req_pd + ,cdma_dat2mcif_rd_req_valid + ,cdma_dat2mcif_rd_req_ready + ,cdma_dat2mcif_rd_req_pd + ,mcif2cdma_dat_rd_rsp_valid + ,mcif2cdma_dat_rd_rsp_ready + ,mcif2cdma_dat_rd_rsp_pd + ,mcif2dc_dat_rd_rsp_valid + ,mcif2dc_dat_rd_rsp_ready + ,mcif2dc_dat_rd_rsp_pd + ,mcif2img_dat_rd_rsp_valid + ,mcif2img_dat_rd_rsp_ready + ,mcif2img_dat_rd_rsp_pd + ); +//////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dc_dat2mcif_rd_req_valid; /* data valid */ +output dc_dat2mcif_rd_req_ready; /* data return handshake */ +input [( 32 + 15 )-1:0] dc_dat2mcif_rd_req_pd; +output mcif2dc_dat_rd_rsp_valid; /* data valid */ +input mcif2dc_dat_rd_rsp_ready; /* data return handshake */ +output [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd; +input img_dat2mcif_rd_req_valid; /* data valid */ +output img_dat2mcif_rd_req_ready; /* data return handshake */ +input [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +output mcif2img_dat_rd_rsp_valid; /* data valid */ +input mcif2img_dat_rd_rsp_ready; /* data return handshake */ +output [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +output cdma_dat2mcif_rd_req_valid; /* data valid */ +input cdma_dat2mcif_rd_req_ready; /* data return handshake */ +output [( 32 + 15 )-1:0] cdma_dat2mcif_rd_req_pd; +input mcif2cdma_dat_rd_rsp_valid; /* data valid */ +output mcif2cdma_dat_rd_rsp_ready; /* data return handshake */ +input [( 64 + (64/8/8) )-1:0] mcif2cdma_dat_rd_rsp_pd; +//////////////////////////////////////////////////////////////////// +wire [( 32 + 15 )-1:0] cdma_dat2mcif_rd_req_pd; +wire cdma_dat2mcif_rd_req_valid; +wire dc_dat2mcif_rd_req_ready; +wire img_dat2mcif_rd_req_ready; +wire mc_sel_dc_w; +wire mc_sel_img_w; +wire mcif2cdma_dat_rd_rsp_ready; +wire [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd; +wire mcif2dc_dat_rd_rsp_valid; +wire [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +wire mcif2img_dat_rd_rsp_valid; +wire [( 32 + 15 )-1:0] req_mc_in_pd; +wire req_mc_in_pvld; +wire req_mc_out_prdy; +wire [( 64 + (64/8/8) )-1:0] rsp_mc_in_pd; +wire rsp_mc_in_pvld; +wire rsp_mc_out_prdy; +reg mc_sel_dc; +reg mc_sel_img; +//////////////////////////////////////////////////////////////////////// +// Data request channel // +//////////////////////////////////////////////////////////////////////// +//////////////// MCIF interface //////////////// +assign mc_sel_dc_w = dc_dat2mcif_rd_req_valid; +assign mc_sel_img_w = img_dat2mcif_rd_req_valid; +assign req_mc_in_pvld = dc_dat2mcif_rd_req_valid | + img_dat2mcif_rd_req_valid; +assign req_mc_in_pd = ({( 32 + 15 ) {mc_sel_dc_w}} & dc_dat2mcif_rd_req_pd) | + ({( 32 + 15 ) {mc_sel_img_w}} & img_dat2mcif_rd_req_pd); +//: my $k = ( 32 + 15 ); +//: &eperl::pipe("-is -wid ${k} -do req_mc_out_pd -vo req_mc_out_pvld -ri req_mc_out_prdy -di req_mc_in_pd -vi req_mc_in_pvld -ro req_mc_in_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg req_mc_in_prdy; +reg skid_flop_req_mc_in_prdy; +reg skid_flop_req_mc_in_pvld; +reg [47-1:0] skid_flop_req_mc_in_pd; +reg pipe_skid_req_mc_in_pvld; +reg [47-1:0] pipe_skid_req_mc_in_pd; +// Wire +wire skid_req_mc_in_pvld; +wire [47-1:0] skid_req_mc_in_pd; +wire skid_req_mc_in_prdy; +wire pipe_skid_req_mc_in_prdy; +wire req_mc_out_pvld; +wire [47-1:0] req_mc_out_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_mc_in_prdy <= 1'b1; + skid_flop_req_mc_in_prdy <= 1'b1; + end else begin + req_mc_in_prdy <= skid_req_mc_in_prdy; + skid_flop_req_mc_in_prdy <= skid_req_mc_in_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_req_mc_in_pvld <= 1'b0; + end else begin + if (skid_flop_req_mc_in_prdy) begin + skid_flop_req_mc_in_pvld <= req_mc_in_pvld; + end + end +end +assign skid_req_mc_in_pvld = (skid_flop_req_mc_in_prdy) ? req_mc_in_pvld : skid_flop_req_mc_in_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_req_mc_in_prdy & req_mc_in_pvld) begin + skid_flop_req_mc_in_pd[47-1:0] <= req_mc_in_pd[47-1:0]; + end +end +assign skid_req_mc_in_pd[47-1:0] = (skid_flop_req_mc_in_prdy) ? req_mc_in_pd[47-1:0] : skid_flop_req_mc_in_pd[47-1:0]; + + +// PIPE READY +assign skid_req_mc_in_prdy = pipe_skid_req_mc_in_prdy || !pipe_skid_req_mc_in_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_req_mc_in_pvld <= 1'b0; + end else begin + if (skid_req_mc_in_prdy) begin + pipe_skid_req_mc_in_pvld <= skid_req_mc_in_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_req_mc_in_prdy && skid_req_mc_in_pvld) begin + pipe_skid_req_mc_in_pd[47-1:0] <= skid_req_mc_in_pd[47-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_req_mc_in_prdy = req_mc_out_prdy; +assign req_mc_out_pvld = pipe_skid_req_mc_in_pvld; +assign req_mc_out_pd = pipe_skid_req_mc_in_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dc_dat2mcif_rd_req_ready = req_mc_in_prdy & dc_dat2mcif_rd_req_valid; +assign img_dat2mcif_rd_req_ready = req_mc_in_prdy & img_dat2mcif_rd_req_valid; +assign cdma_dat2mcif_rd_req_valid = req_mc_out_pvld; +assign cdma_dat2mcif_rd_req_pd = req_mc_out_pd; +assign req_mc_out_prdy = cdma_dat2mcif_rd_req_ready; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_mc_in_pvld & req_mc_in_prdy\" -d \"mc_sel_dc_w\" -q mc_sel_dc"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_mc_in_pvld & req_mc_in_prdy\" -d \"mc_sel_img_w\" -q mc_sel_img"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_sel_dc <= 1'b0; + end else begin + if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b1) begin + mc_sel_dc <= mc_sel_dc_w; + // VCS coverage off + end else if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b0) begin + end else begin + mc_sel_dc <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_sel_img <= 1'b0; + end else begin + if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b1) begin + mc_sel_img <= mc_sel_img_w; + // VCS coverage off + end else if ((req_mc_in_pvld & req_mc_in_prdy) == 1'b0) begin + end else begin + mc_sel_img <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// CVIF interface //////////////// +//////////////////////////////////////////////////////////////////////// +// Data response channel // +//////////////////////////////////////////////////////////////////////// +//////////////// MCIF interface //////////////// +assign rsp_mc_in_pvld = mcif2cdma_dat_rd_rsp_valid; +assign rsp_mc_in_pd = mcif2cdma_dat_rd_rsp_pd; +//: my $k = ( 64 + (64/8/8) ); +//: &eperl::pipe("-is -wid $k -do rsp_mc_out_pd -vo rsp_mc_out_pvld -ri rsp_mc_out_prdy -di rsp_mc_in_pd -vi rsp_mc_in_pvld -ro rsp_mc_in_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg rsp_mc_in_prdy; +reg skid_flop_rsp_mc_in_prdy; +reg skid_flop_rsp_mc_in_pvld; +reg [65-1:0] skid_flop_rsp_mc_in_pd; +reg pipe_skid_rsp_mc_in_pvld; +reg [65-1:0] pipe_skid_rsp_mc_in_pd; +// Wire +wire skid_rsp_mc_in_pvld; +wire [65-1:0] skid_rsp_mc_in_pd; +wire skid_rsp_mc_in_prdy; +wire pipe_skid_rsp_mc_in_prdy; +wire rsp_mc_out_pvld; +wire [65-1:0] rsp_mc_out_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_mc_in_prdy <= 1'b1; + skid_flop_rsp_mc_in_prdy <= 1'b1; + end else begin + rsp_mc_in_prdy <= skid_rsp_mc_in_prdy; + skid_flop_rsp_mc_in_prdy <= skid_rsp_mc_in_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_rsp_mc_in_pvld <= 1'b0; + end else begin + if (skid_flop_rsp_mc_in_prdy) begin + skid_flop_rsp_mc_in_pvld <= rsp_mc_in_pvld; + end + end +end +assign skid_rsp_mc_in_pvld = (skid_flop_rsp_mc_in_prdy) ? rsp_mc_in_pvld : skid_flop_rsp_mc_in_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_rsp_mc_in_prdy & rsp_mc_in_pvld) begin + skid_flop_rsp_mc_in_pd[65-1:0] <= rsp_mc_in_pd[65-1:0]; + end +end +assign skid_rsp_mc_in_pd[65-1:0] = (skid_flop_rsp_mc_in_prdy) ? rsp_mc_in_pd[65-1:0] : skid_flop_rsp_mc_in_pd[65-1:0]; + + +// PIPE READY +assign skid_rsp_mc_in_prdy = pipe_skid_rsp_mc_in_prdy || !pipe_skid_rsp_mc_in_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_rsp_mc_in_pvld <= 1'b0; + end else begin + if (skid_rsp_mc_in_prdy) begin + pipe_skid_rsp_mc_in_pvld <= skid_rsp_mc_in_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_rsp_mc_in_prdy && skid_rsp_mc_in_pvld) begin + pipe_skid_rsp_mc_in_pd[65-1:0] <= skid_rsp_mc_in_pd[65-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_rsp_mc_in_prdy = rsp_mc_out_prdy; +assign rsp_mc_out_pvld = pipe_skid_rsp_mc_in_pvld; +assign rsp_mc_out_pd = pipe_skid_rsp_mc_in_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign mcif2cdma_dat_rd_rsp_ready = rsp_mc_in_prdy; +assign mcif2dc_dat_rd_rsp_valid = rsp_mc_out_pvld & mc_sel_dc; +assign mcif2img_dat_rd_rsp_valid = rsp_mc_out_pvld & mc_sel_img; +assign mcif2dc_dat_rd_rsp_pd = {( 64 + (64/8/8) ) {mc_sel_dc}} & rsp_mc_out_pd; +assign mcif2img_dat_rd_rsp_pd = {( 64 + (64/8/8) ) {mc_sel_img}} & rsp_mc_out_pd; +assign rsp_mc_out_prdy = (mc_sel_dc & mcif2dc_dat_rd_rsp_ready) | + (mc_sel_img & mcif2img_dat_rd_rsp_ready); +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (req_mc_out_pvld^req_mc_out_prdy^req_mc_in_pvld^req_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (req_cv_out_pvld^req_cv_out_prdy^req_cv_in_pvld^req_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rsp_mc_out_pvld^rsp_mc_out_prdy^rsp_mc_in_pvld^rsp_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rsp_cv_out_pvld^rsp_cv_out_prdy^rsp_cv_in_pvld^rsp_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (req_mc_in_pvld && !req_mc_in_prdy), (req_mc_in_pvld), (req_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_7x (nvdla_core_clk, `ASSERT_RESET, (req_cv_in_pvld && !req_cv_in_prdy), (req_cv_in_pvld), (req_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_19x (nvdla_core_clk, `ASSERT_RESET, (rsp_mc_in_pvld && !rsp_mc_in_prdy), (rsp_mc_in_pvld), (rsp_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,2,0,"Error! DMA resp conflict!") zzz_assert_zero_one_hot_22x (nvdla_core_clk, `ASSERT_RESET, {mcif2cdma_dat_rd_rsp_valid, cvif2cdma_dat_rd_rsp_valid}); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_dma_mux diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v.vcp new file mode 100644 index 0000000..1c37ce5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v.vcp @@ -0,0 +1,183 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_dma_mux.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_dma_mux ( + nvdla_core_clk + ,nvdla_core_rstn + ,dc_dat2mcif_rd_req_valid + ,dc_dat2mcif_rd_req_ready + ,dc_dat2mcif_rd_req_pd + ,img_dat2mcif_rd_req_valid + ,img_dat2mcif_rd_req_ready + ,img_dat2mcif_rd_req_pd + ,cdma_dat2mcif_rd_req_valid + ,cdma_dat2mcif_rd_req_ready + ,cdma_dat2mcif_rd_req_pd + ,mcif2cdma_dat_rd_rsp_valid + ,mcif2cdma_dat_rd_rsp_ready + ,mcif2cdma_dat_rd_rsp_pd + ,mcif2dc_dat_rd_rsp_valid + ,mcif2dc_dat_rd_rsp_ready + ,mcif2dc_dat_rd_rsp_pd + ,mcif2img_dat_rd_rsp_valid + ,mcif2img_dat_rd_rsp_ready + ,mcif2img_dat_rd_rsp_pd + ); +//////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dc_dat2mcif_rd_req_valid; /* data valid */ +output dc_dat2mcif_rd_req_ready; /* data return handshake */ +input [( 32 + 15 )-1:0] dc_dat2mcif_rd_req_pd; +output mcif2dc_dat_rd_rsp_valid; /* data valid */ +input mcif2dc_dat_rd_rsp_ready; /* data return handshake */ +output [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd; +input img_dat2mcif_rd_req_valid; /* data valid */ +output img_dat2mcif_rd_req_ready; /* data return handshake */ +input [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +output mcif2img_dat_rd_rsp_valid; /* data valid */ +input mcif2img_dat_rd_rsp_ready; /* data return handshake */ +output [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +output cdma_dat2mcif_rd_req_valid; /* data valid */ +input cdma_dat2mcif_rd_req_ready; /* data return handshake */ +output [( 32 + 15 )-1:0] cdma_dat2mcif_rd_req_pd; +input mcif2cdma_dat_rd_rsp_valid; /* data valid */ +output mcif2cdma_dat_rd_rsp_ready; /* data return handshake */ +input [( 64 + (64/8/8) )-1:0] mcif2cdma_dat_rd_rsp_pd; +//////////////////////////////////////////////////////////////////// +wire [( 32 + 15 )-1:0] cdma_dat2mcif_rd_req_pd; +wire cdma_dat2mcif_rd_req_valid; +wire dc_dat2mcif_rd_req_ready; +wire img_dat2mcif_rd_req_ready; +wire mc_sel_dc_w; +wire mc_sel_img_w; +wire mcif2cdma_dat_rd_rsp_ready; +wire [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd; +wire mcif2dc_dat_rd_rsp_valid; +wire [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +wire mcif2img_dat_rd_rsp_valid; +wire [( 32 + 15 )-1:0] req_mc_in_pd; +wire req_mc_in_pvld; +wire req_mc_out_prdy; +wire [( 64 + (64/8/8) )-1:0] rsp_mc_in_pd; +wire rsp_mc_in_pvld; +wire rsp_mc_out_prdy; +reg mc_sel_dc; +reg mc_sel_img; +//////////////////////////////////////////////////////////////////////// +// Data request channel // +//////////////////////////////////////////////////////////////////////// +//////////////// MCIF interface //////////////// +assign mc_sel_dc_w = dc_dat2mcif_rd_req_valid; +assign mc_sel_img_w = img_dat2mcif_rd_req_valid; +assign req_mc_in_pvld = dc_dat2mcif_rd_req_valid | + img_dat2mcif_rd_req_valid; +assign req_mc_in_pd = ({( 32 + 15 ) {mc_sel_dc_w}} & dc_dat2mcif_rd_req_pd) | + ({( 32 + 15 ) {mc_sel_img_w}} & img_dat2mcif_rd_req_pd); +//: my $k = ( 32 + 15 ); +//: &eperl::pipe("-is -wid ${k} -do req_mc_out_pd -vo req_mc_out_pvld -ri req_mc_out_prdy -di req_mc_in_pd -vi req_mc_in_pvld -ro req_mc_in_prdy"); +assign dc_dat2mcif_rd_req_ready = req_mc_in_prdy & dc_dat2mcif_rd_req_valid; +assign img_dat2mcif_rd_req_ready = req_mc_in_prdy & img_dat2mcif_rd_req_valid; +assign cdma_dat2mcif_rd_req_valid = req_mc_out_pvld; +assign cdma_dat2mcif_rd_req_pd = req_mc_out_pd; +assign req_mc_out_prdy = cdma_dat2mcif_rd_req_ready; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_mc_in_pvld & req_mc_in_prdy\" -d \"mc_sel_dc_w\" -q mc_sel_dc"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_mc_in_pvld & req_mc_in_prdy\" -d \"mc_sel_img_w\" -q mc_sel_img"); +//////////////// CVIF interface //////////////// +//////////////////////////////////////////////////////////////////////// +// Data response channel // +//////////////////////////////////////////////////////////////////////// +//////////////// MCIF interface //////////////// +assign rsp_mc_in_pvld = mcif2cdma_dat_rd_rsp_valid; +assign rsp_mc_in_pd = mcif2cdma_dat_rd_rsp_pd; +//: my $k = ( 64 + (64/8/8) ); +//: &eperl::pipe("-is -wid $k -do rsp_mc_out_pd -vo rsp_mc_out_pvld -ri rsp_mc_out_prdy -di rsp_mc_in_pd -vi rsp_mc_in_pvld -ro rsp_mc_in_prdy"); +assign mcif2cdma_dat_rd_rsp_ready = rsp_mc_in_prdy; +assign mcif2dc_dat_rd_rsp_valid = rsp_mc_out_pvld & mc_sel_dc; +assign mcif2img_dat_rd_rsp_valid = rsp_mc_out_pvld & mc_sel_img; +assign mcif2dc_dat_rd_rsp_pd = {( 64 + (64/8/8) ) {mc_sel_dc}} & rsp_mc_out_pd; +assign mcif2img_dat_rd_rsp_pd = {( 64 + (64/8/8) ) {mc_sel_img}} & rsp_mc_out_pd; +assign rsp_mc_out_prdy = (mc_sel_dc & mcif2dc_dat_rd_rsp_ready) | + (mc_sel_img & mcif2img_dat_rd_rsp_ready); +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (req_mc_out_pvld^req_mc_out_prdy^req_mc_in_pvld^req_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_mc_in_pvld & req_mc_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (req_cv_out_pvld^req_cv_out_prdy^req_cv_in_pvld^req_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_cv_in_pvld & req_cv_in_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rsp_mc_out_pvld^rsp_mc_out_prdy^rsp_mc_in_pvld^rsp_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rsp_cv_out_pvld^rsp_cv_out_prdy^rsp_cv_in_pvld^rsp_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (req_mc_in_pvld && !req_mc_in_prdy), (req_mc_in_pvld), (req_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_7x (nvdla_core_clk, `ASSERT_RESET, (req_cv_in_pvld && !req_cv_in_prdy), (req_cv_in_pvld), (req_cv_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_19x (nvdla_core_clk, `ASSERT_RESET, (rsp_mc_in_pvld && !rsp_mc_in_prdy), (rsp_mc_in_pvld), (rsp_mc_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,2,0,"Error! DMA resp conflict!") zzz_assert_zero_one_hot_22x (nvdla_core_clk, `ASSERT_RESET, {mcif2cdma_dat_rd_rsp_valid, cvif2cdma_dat_rd_rsp_valid}); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_dma_mux diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v new file mode 100644 index 0000000..dfdd7b9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v @@ -0,0 +1,1131 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_dual_reg.v +module NV_NVDLA_CDMA_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,data_bank + ,weight_bank + ,batches + ,batch_stride + ,conv_x_stride + ,conv_y_stride + ,cvt_en + ,cvt_truncate + ,cvt_offset + ,cvt_scale + ,cya + ,datain_addr_high_0 + ,datain_addr_high_1 + ,datain_addr_low_0 + ,datain_addr_low_1 + ,line_packed + ,surf_packed + ,datain_ram_type + ,datain_format + ,pixel_format + ,pixel_mapping + ,pixel_sign_override + ,datain_height + ,datain_width + ,datain_channel + ,datain_height_ext + ,datain_width_ext + ,entries + ,grains + ,line_stride + ,uv_line_stride + ,mean_format + ,mean_gu + ,mean_ry + ,mean_ax + ,mean_bv + ,conv_mode + ,data_reuse + ,in_precision + ,proc_precision + ,skip_data_rls + ,skip_weight_rls + ,weight_reuse + ,nan_to_zero + ,op_en_trigger + ,dma_en + ,pixel_x_offset + ,pixel_y_offset + ,rsv_per_line + ,rsv_per_uv_line + ,rsv_height + ,rsv_y_index + ,surf_stride + ,weight_addr_high + ,weight_addr_low + ,weight_bytes + ,weight_format + ,weight_ram_type + ,byte_per_kernel + ,weight_kernel + ,wgs_addr_high + ,wgs_addr_low + ,wmb_addr_high + ,wmb_addr_low + ,wmb_bytes + ,pad_bottom + ,pad_left + ,pad_right + ,pad_top + ,pad_value + ,inf_data_num + ,inf_weight_num + ,nan_data_num + ,nan_weight_num + ,op_en + ,dat_rd_latency + ,dat_rd_stall + ,wt_rd_latency + ,wt_rd_stall + ); +wire [31:0] nvdla_cdma_d_bank_0_out; +wire [31:0] nvdla_cdma_d_batch_number_0_out; +wire [31:0] nvdla_cdma_d_batch_stride_0_out; +wire [31:0] nvdla_cdma_d_conv_stride_0_out; +wire [31:0] nvdla_cdma_d_cvt_cfg_0_out; +wire [31:0] nvdla_cdma_d_cvt_offset_0_out; +wire [31:0] nvdla_cdma_d_cvt_scale_0_out; +wire [31:0] nvdla_cdma_d_cya_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_high_0_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_high_1_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_low_0_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_low_1_0_out; +wire [31:0] nvdla_cdma_d_dain_map_0_out; +wire [31:0] nvdla_cdma_d_dain_ram_type_0_out; +wire [31:0] nvdla_cdma_d_datain_format_0_out; +wire [31:0] nvdla_cdma_d_datain_size_0_0_out; +wire [31:0] nvdla_cdma_d_datain_size_1_0_out; +wire [31:0] nvdla_cdma_d_datain_size_ext_0_0_out; +wire [31:0] nvdla_cdma_d_entry_per_slice_0_out; +wire [31:0] nvdla_cdma_d_fetch_grain_0_out; +wire [31:0] nvdla_cdma_d_inf_input_data_num_0_out; +wire [31:0] nvdla_cdma_d_inf_input_weight_num_0_out; +wire [31:0] nvdla_cdma_d_line_stride_0_out; +wire [31:0] nvdla_cdma_d_line_uv_stride_0_out; +wire [31:0] nvdla_cdma_d_mean_format_0_out; +wire [31:0] nvdla_cdma_d_mean_global_0_0_out; +wire [31:0] nvdla_cdma_d_mean_global_1_0_out; +wire [31:0] nvdla_cdma_d_misc_cfg_0_out; +wire [31:0] nvdla_cdma_d_nan_flush_to_zero_0_out; +wire [31:0] nvdla_cdma_d_nan_input_data_num_0_out; +wire [31:0] nvdla_cdma_d_nan_input_weight_num_0_out; +wire [31:0] nvdla_cdma_d_op_enable_0_out; +wire [31:0] nvdla_cdma_d_perf_dat_read_latency_0_out; +wire [31:0] nvdla_cdma_d_perf_dat_read_stall_0_out; +wire [31:0] nvdla_cdma_d_perf_enable_0_out; +wire [31:0] nvdla_cdma_d_perf_wt_read_latency_0_out; +wire [31:0] nvdla_cdma_d_perf_wt_read_stall_0_out; +wire [31:0] nvdla_cdma_d_pixel_offset_0_out; +wire [31:0] nvdla_cdma_d_reserved_x_cfg_0_out; +wire [31:0] nvdla_cdma_d_reserved_y_cfg_0_out; +wire [31:0] nvdla_cdma_d_surf_stride_0_out; +wire [31:0] nvdla_cdma_d_weight_addr_high_0_out; +wire [31:0] nvdla_cdma_d_weight_addr_low_0_out; +wire [31:0] nvdla_cdma_d_weight_bytes_0_out; +wire [31:0] nvdla_cdma_d_weight_format_0_out; +wire [31:0] nvdla_cdma_d_weight_ram_type_0_out; +wire [31:0] nvdla_cdma_d_weight_size_0_0_out; +wire [31:0] nvdla_cdma_d_weight_size_1_0_out; +wire [31:0] nvdla_cdma_d_wgs_addr_high_0_out; +wire [31:0] nvdla_cdma_d_wgs_addr_low_0_out; +wire [31:0] nvdla_cdma_d_wmb_addr_high_0_out; +wire [31:0] nvdla_cdma_d_wmb_addr_low_0_out; +wire [31:0] nvdla_cdma_d_wmb_bytes_0_out; +wire [31:0] nvdla_cdma_d_zero_padding_0_out; +wire [31:0] nvdla_cdma_d_zero_padding_value_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [4:0] data_bank; +output [4:0] weight_bank; +output [4:0] batches; +output [31:0] batch_stride; +output [2:0] conv_x_stride; +output [2:0] conv_y_stride; +output cvt_en; +output [5:0] cvt_truncate; +output [15:0] cvt_offset; +output [15:0] cvt_scale; +output [31:0] cya; +output [31:0] datain_addr_high_0; +output [31:0] datain_addr_high_1; +output [31:0] datain_addr_low_0; +output [31:0] datain_addr_low_1; +output line_packed; +output surf_packed; +output datain_ram_type; +output datain_format; +output [5:0] pixel_format; +output pixel_mapping; +output pixel_sign_override; +output [12:0] datain_height; +output [12:0] datain_width; +output [12:0] datain_channel; +output [12:0] datain_height_ext; +output [12:0] datain_width_ext; +output [13:0] entries; +output [11:0] grains; +output [31:0] line_stride; +output [31:0] uv_line_stride; +output mean_format; +output [15:0] mean_gu; +output [15:0] mean_ry; +output [15:0] mean_ax; +output [15:0] mean_bv; +output conv_mode; +output data_reuse; +output [1:0] in_precision; +output [1:0] proc_precision; +output skip_data_rls; +output skip_weight_rls; +output weight_reuse; +output nan_to_zero; +output op_en_trigger; +output dma_en; +output [4:0] pixel_x_offset; +output [2:0] pixel_y_offset; +output [9:0] rsv_per_line; +output [9:0] rsv_per_uv_line; +output [2:0] rsv_height; +output [4:0] rsv_y_index; +output [31:0] surf_stride; +output [31:0] weight_addr_high; +output [31:0] weight_addr_low; +output [31:0] weight_bytes; +output weight_format; +output weight_ram_type; +output [17:0] byte_per_kernel; +output [12:0] weight_kernel; +output [31:0] wgs_addr_high; +output [31:0] wgs_addr_low; +output [31:0] wmb_addr_high; +output [31:0] wmb_addr_low; +output [27:0] wmb_bytes; +output [5:0] pad_bottom; +output [4:0] pad_left; +output [5:0] pad_right; +output [4:0] pad_top; +output [15:0] pad_value; +// Read-only register inputs +input [31:0] inf_data_num; +input [31:0] inf_weight_num; +input [31:0] nan_data_num; +input [31:0] nan_weight_num; +input op_en; +input [31:0] dat_rd_latency; +input [31:0] dat_rd_stall; +input [31:0] wt_rd_latency; +input [31:0] wt_rd_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [31:0] batch_stride; +reg [4:0] batches; +reg [17:0] byte_per_kernel; +reg conv_mode; +reg [2:0] conv_x_stride; +reg [2:0] conv_y_stride; +reg cvt_en; +reg [15:0] cvt_offset; +reg [15:0] cvt_scale; +reg [5:0] cvt_truncate; +reg [31:0] cya; +reg [4:0] data_bank; +reg data_reuse; +reg [31:0] datain_addr_high_0; +reg [31:0] datain_addr_high_1; +reg [31:0] datain_addr_low_0; +reg [31:0] datain_addr_low_1; +reg [12:0] datain_channel; +reg datain_format; +reg [12:0] datain_height; +reg [12:0] datain_height_ext; +reg datain_ram_type; +reg [12:0] datain_width; +reg [12:0] datain_width_ext; +reg dma_en; +reg [13:0] entries; +reg [11:0] grains; +reg [1:0] in_precision; +reg line_packed; +reg [31:0] line_stride; +reg [15:0] mean_ax; +reg [15:0] mean_bv; +reg mean_format; +reg [15:0] mean_gu; +reg [15:0] mean_ry; +reg nan_to_zero; +reg [5:0] pad_bottom; +reg [4:0] pad_left; +reg [5:0] pad_right; +reg [4:0] pad_top; +reg [15:0] pad_value; +reg [5:0] pixel_format; +reg pixel_mapping; +reg pixel_sign_override; +reg [4:0] pixel_x_offset; +reg [2:0] pixel_y_offset; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [2:0] rsv_height; +reg [9:0] rsv_per_line; +reg [9:0] rsv_per_uv_line; +reg [4:0] rsv_y_index; +reg skip_data_rls; +reg skip_weight_rls; +reg surf_packed; +reg [31:0] surf_stride; +reg [31:0] uv_line_stride; +reg [31:0] weight_addr_high; +reg [31:0] weight_addr_low; +reg [4:0] weight_bank; +reg [31:0] weight_bytes; +reg weight_format; +reg [12:0] weight_kernel; +reg weight_ram_type; +reg weight_reuse; +reg [31:0] wgs_addr_high; +reg [31:0] wgs_addr_low; +reg [31:0] wmb_addr_high; +reg [31:0] wmb_addr_low; +reg [27:0] wmb_bytes; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdma_d_bank_0_wren = (reg_offset_wr == (32'h50bc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_batch_number_0_wren = (reg_offset_wr == (32'h5058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_batch_stride_0_wren = (reg_offset_wr == (32'h505c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_conv_stride_0_wren = (reg_offset_wr == (32'h50b0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cvt_cfg_0_wren = (reg_offset_wr == (32'h50a4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cvt_offset_0_wren = (reg_offset_wr == (32'h50a8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cvt_scale_0_wren = (reg_offset_wr == (32'h50ac & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cya_0_wren = (reg_offset_wr == (32'h50e8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_high_0_0_wren = (reg_offset_wr == (32'h5030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_high_1_0_wren = (reg_offset_wr == (32'h5038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_low_0_0_wren = (reg_offset_wr == (32'h5034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_low_1_0_wren = (reg_offset_wr == (32'h503c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_map_0_wren = (reg_offset_wr == (32'h504c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_ram_type_0_wren = (reg_offset_wr == (32'h502c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_format_0_wren = (reg_offset_wr == (32'h5018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_size_0_0_wren = (reg_offset_wr == (32'h501c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_size_1_0_wren = (reg_offset_wr == (32'h5020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_size_ext_0_0_wren = (reg_offset_wr == (32'h5024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_entry_per_slice_0_wren = (reg_offset_wr == (32'h5060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_fetch_grain_0_wren = (reg_offset_wr == (32'h5064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_inf_input_data_num_0_wren = (reg_offset_wr == (32'h50cc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_inf_input_weight_num_0_wren = (reg_offset_wr == (32'h50d0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_line_stride_0_wren = (reg_offset_wr == (32'h5040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_line_uv_stride_0_wren = (reg_offset_wr == (32'h5044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_mean_format_0_wren = (reg_offset_wr == (32'h5098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_mean_global_0_0_wren = (reg_offset_wr == (32'h509c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_mean_global_1_0_wren = (reg_offset_wr == (32'h50a0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_misc_cfg_0_wren = (reg_offset_wr == (32'h5014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_nan_flush_to_zero_0_wren = (reg_offset_wr == (32'h50c0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_nan_input_data_num_0_wren = (reg_offset_wr == (32'h50c4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_nan_input_weight_num_0_wren = (reg_offset_wr == (32'h50c8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_op_enable_0_wren = (reg_offset_wr == (32'h5010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_dat_read_latency_0_wren = (reg_offset_wr == (32'h50e0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_dat_read_stall_0_wren = (reg_offset_wr == (32'h50d8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_enable_0_wren = (reg_offset_wr == (32'h50d4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_wt_read_latency_0_wren = (reg_offset_wr == (32'h50e4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_wt_read_stall_0_wren = (reg_offset_wr == (32'h50dc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_pixel_offset_0_wren = (reg_offset_wr == (32'h5028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_reserved_x_cfg_0_wren = (reg_offset_wr == (32'h5050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_reserved_y_cfg_0_wren = (reg_offset_wr == (32'h5054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_surf_stride_0_wren = (reg_offset_wr == (32'h5048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_addr_high_0_wren = (reg_offset_wr == (32'h5078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_addr_low_0_wren = (reg_offset_wr == (32'h507c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_bytes_0_wren = (reg_offset_wr == (32'h5080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_format_0_wren = (reg_offset_wr == (32'h5068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_ram_type_0_wren = (reg_offset_wr == (32'h5074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_size_0_0_wren = (reg_offset_wr == (32'h506c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_size_1_0_wren = (reg_offset_wr == (32'h5070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wgs_addr_high_0_wren = (reg_offset_wr == (32'h5084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wgs_addr_low_0_wren = (reg_offset_wr == (32'h5088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wmb_addr_high_0_wren = (reg_offset_wr == (32'h508c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wmb_addr_low_0_wren = (reg_offset_wr == (32'h5090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wmb_bytes_0_wren = (reg_offset_wr == (32'h5094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_zero_padding_0_wren = (reg_offset_wr == (32'h50b4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_zero_padding_value_0_wren = (reg_offset_wr == (32'h50b8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdma_d_bank_0_out[31:0] = { 11'b0, weight_bank, 11'b0, data_bank }; +assign nvdla_cdma_d_batch_number_0_out[31:0] = { 27'b0, batches }; +assign nvdla_cdma_d_batch_stride_0_out[31:0] = { batch_stride }; +assign nvdla_cdma_d_conv_stride_0_out[31:0] = { 13'b0, conv_y_stride, 13'b0, conv_x_stride }; +assign nvdla_cdma_d_cvt_cfg_0_out[31:0] = { 22'b0, cvt_truncate, 3'b0, cvt_en }; +assign nvdla_cdma_d_cvt_offset_0_out[31:0] = { 16'b0, cvt_offset }; +assign nvdla_cdma_d_cvt_scale_0_out[31:0] = { 16'b0, cvt_scale }; +assign nvdla_cdma_d_cya_0_out[31:0] = { cya }; +assign nvdla_cdma_d_dain_addr_high_0_0_out[31:0] = { datain_addr_high_0 }; +assign nvdla_cdma_d_dain_addr_high_1_0_out[31:0] = { datain_addr_high_1 }; +assign nvdla_cdma_d_dain_addr_low_0_0_out[31:0] = { datain_addr_low_0 }; +assign nvdla_cdma_d_dain_addr_low_1_0_out[31:0] = { datain_addr_low_1 }; +assign nvdla_cdma_d_dain_map_0_out[31:0] = { 15'b0, surf_packed, 15'b0, line_packed }; +assign nvdla_cdma_d_dain_ram_type_0_out[31:0] = { 31'b0, datain_ram_type }; +assign nvdla_cdma_d_datain_format_0_out[31:0] = { 11'b0, pixel_sign_override, 3'b0, pixel_mapping, 2'b0, pixel_format, 7'b0, datain_format }; +assign nvdla_cdma_d_datain_size_0_0_out[31:0] = { 3'b0, datain_height, 3'b0, datain_width }; +assign nvdla_cdma_d_datain_size_1_0_out[31:0] = { 19'b0, datain_channel }; +assign nvdla_cdma_d_datain_size_ext_0_0_out[31:0] = { 3'b0, datain_height_ext, 3'b0, datain_width_ext }; +assign nvdla_cdma_d_entry_per_slice_0_out[31:0] = { 18'b0, entries }; +assign nvdla_cdma_d_fetch_grain_0_out[31:0] = { 20'b0, grains }; +assign nvdla_cdma_d_inf_input_data_num_0_out[31:0] = { inf_data_num }; +assign nvdla_cdma_d_inf_input_weight_num_0_out[31:0] = { inf_weight_num }; +assign nvdla_cdma_d_line_stride_0_out[31:0] = { line_stride }; +assign nvdla_cdma_d_line_uv_stride_0_out[31:0] = { uv_line_stride }; +assign nvdla_cdma_d_mean_format_0_out[31:0] = { 31'b0, mean_format }; +assign nvdla_cdma_d_mean_global_0_0_out[31:0] = { mean_gu, mean_ry }; +assign nvdla_cdma_d_mean_global_1_0_out[31:0] = { mean_ax, mean_bv }; +assign nvdla_cdma_d_misc_cfg_0_out[31:0] = { 3'b0, skip_weight_rls, 3'b0, skip_data_rls, 3'b0, weight_reuse, 3'b0, data_reuse, 2'b0, proc_precision, 2'b0, in_precision, 7'b0, conv_mode }; +assign nvdla_cdma_d_nan_flush_to_zero_0_out[31:0] = { 31'b0, nan_to_zero }; +assign nvdla_cdma_d_nan_input_data_num_0_out[31:0] = { nan_data_num }; +assign nvdla_cdma_d_nan_input_weight_num_0_out[31:0] = { nan_weight_num }; +assign nvdla_cdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cdma_d_perf_dat_read_latency_0_out[31:0] = { dat_rd_latency }; +assign nvdla_cdma_d_perf_dat_read_stall_0_out[31:0] = { dat_rd_stall }; +assign nvdla_cdma_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_cdma_d_perf_wt_read_latency_0_out[31:0] = { wt_rd_latency }; +assign nvdla_cdma_d_perf_wt_read_stall_0_out[31:0] = { wt_rd_stall }; +assign nvdla_cdma_d_pixel_offset_0_out[31:0] = { 13'b0, pixel_y_offset, 11'b0, pixel_x_offset }; +assign nvdla_cdma_d_reserved_x_cfg_0_out[31:0] = { 6'b0, rsv_per_uv_line, 6'b0, rsv_per_line }; +assign nvdla_cdma_d_reserved_y_cfg_0_out[31:0] = { 11'b0, rsv_y_index, 13'b0, rsv_height }; +assign nvdla_cdma_d_surf_stride_0_out[31:0] = { surf_stride }; +assign nvdla_cdma_d_weight_addr_high_0_out[31:0] = { weight_addr_high }; +assign nvdla_cdma_d_weight_addr_low_0_out[31:0] = { weight_addr_low }; +assign nvdla_cdma_d_weight_bytes_0_out[31:0] = { weight_bytes }; +assign nvdla_cdma_d_weight_format_0_out[31:0] = { 31'b0, weight_format }; +assign nvdla_cdma_d_weight_ram_type_0_out[31:0] = { 31'b0, weight_ram_type }; +assign nvdla_cdma_d_weight_size_0_0_out[31:0] = { 14'b0, byte_per_kernel }; +assign nvdla_cdma_d_weight_size_1_0_out[31:0] = { 19'b0, weight_kernel }; +assign nvdla_cdma_d_wgs_addr_high_0_out[31:0] = { wgs_addr_high }; +assign nvdla_cdma_d_wgs_addr_low_0_out[31:0] = { wgs_addr_low }; +assign nvdla_cdma_d_wmb_addr_high_0_out[31:0] = { wmb_addr_high }; +assign nvdla_cdma_d_wmb_addr_low_0_out[31:0] = { wmb_addr_low }; +assign nvdla_cdma_d_wmb_bytes_0_out[31:0] = { 4'b0, wmb_bytes }; +assign nvdla_cdma_d_zero_padding_0_out[31:0] = { 2'b0, pad_bottom, 3'b0, pad_top, 2'b0, pad_right, 3'b0, pad_left }; +assign nvdla_cdma_d_zero_padding_value_0_out[31:0] = { 16'b0, pad_value }; +assign op_en_trigger = nvdla_cdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdma_d_bank_0_out + or nvdla_cdma_d_batch_number_0_out + or nvdla_cdma_d_batch_stride_0_out + or nvdla_cdma_d_conv_stride_0_out + or nvdla_cdma_d_cvt_cfg_0_out + or nvdla_cdma_d_cvt_offset_0_out + or nvdla_cdma_d_cvt_scale_0_out + or nvdla_cdma_d_cya_0_out + or nvdla_cdma_d_dain_addr_high_0_0_out + or nvdla_cdma_d_dain_addr_high_1_0_out + or nvdla_cdma_d_dain_addr_low_0_0_out + or nvdla_cdma_d_dain_addr_low_1_0_out + or nvdla_cdma_d_dain_map_0_out + or nvdla_cdma_d_dain_ram_type_0_out + or nvdla_cdma_d_datain_format_0_out + or nvdla_cdma_d_datain_size_0_0_out + or nvdla_cdma_d_datain_size_1_0_out + or nvdla_cdma_d_datain_size_ext_0_0_out + or nvdla_cdma_d_entry_per_slice_0_out + or nvdla_cdma_d_fetch_grain_0_out + or nvdla_cdma_d_inf_input_data_num_0_out + or nvdla_cdma_d_inf_input_weight_num_0_out + or nvdla_cdma_d_line_stride_0_out + or nvdla_cdma_d_line_uv_stride_0_out + or nvdla_cdma_d_mean_format_0_out + or nvdla_cdma_d_mean_global_0_0_out + or nvdla_cdma_d_mean_global_1_0_out + or nvdla_cdma_d_misc_cfg_0_out + or nvdla_cdma_d_nan_flush_to_zero_0_out + or nvdla_cdma_d_nan_input_data_num_0_out + or nvdla_cdma_d_nan_input_weight_num_0_out + or nvdla_cdma_d_op_enable_0_out + or nvdla_cdma_d_perf_dat_read_latency_0_out + or nvdla_cdma_d_perf_dat_read_stall_0_out + or nvdla_cdma_d_perf_enable_0_out + or nvdla_cdma_d_perf_wt_read_latency_0_out + or nvdla_cdma_d_perf_wt_read_stall_0_out + or nvdla_cdma_d_pixel_offset_0_out + or nvdla_cdma_d_reserved_x_cfg_0_out + or nvdla_cdma_d_reserved_y_cfg_0_out + or nvdla_cdma_d_surf_stride_0_out + or nvdla_cdma_d_weight_addr_high_0_out + or nvdla_cdma_d_weight_addr_low_0_out + or nvdla_cdma_d_weight_bytes_0_out + or nvdla_cdma_d_weight_format_0_out + or nvdla_cdma_d_weight_ram_type_0_out + or nvdla_cdma_d_weight_size_0_0_out + or nvdla_cdma_d_weight_size_1_0_out + or nvdla_cdma_d_wgs_addr_high_0_out + or nvdla_cdma_d_wgs_addr_low_0_out + or nvdla_cdma_d_wmb_addr_high_0_out + or nvdla_cdma_d_wmb_addr_low_0_out + or nvdla_cdma_d_wmb_bytes_0_out + or nvdla_cdma_d_zero_padding_0_out + or nvdla_cdma_d_zero_padding_value_0_out + ) begin + case (reg_offset_rd_int) + (32'h50bc & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_bank_0_out ; + end + (32'h5058 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_batch_number_0_out ; + end + (32'h505c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_batch_stride_0_out ; + end + (32'h50b0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_conv_stride_0_out ; + end + (32'h50a4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cvt_cfg_0_out ; + end + (32'h50a8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cvt_offset_0_out ; + end + (32'h50ac & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cvt_scale_0_out ; + end + (32'h50e8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cya_0_out ; + end + (32'h5030 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_high_0_0_out ; + end + (32'h5038 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_high_1_0_out ; + end + (32'h5034 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_low_0_0_out ; + end + (32'h503c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_low_1_0_out ; + end + (32'h504c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_map_0_out ; + end + (32'h502c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_ram_type_0_out ; + end + (32'h5018 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_format_0_out ; + end + (32'h501c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_size_0_0_out ; + end + (32'h5020 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_size_1_0_out ; + end + (32'h5024 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_size_ext_0_0_out ; + end + (32'h5060 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_entry_per_slice_0_out ; + end + (32'h5064 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_fetch_grain_0_out ; + end + (32'h50cc & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_inf_input_data_num_0_out ; + end + (32'h50d0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_inf_input_weight_num_0_out ; + end + (32'h5040 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_line_stride_0_out ; + end + (32'h5044 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_line_uv_stride_0_out ; + end + (32'h5098 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_mean_format_0_out ; + end + (32'h509c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_mean_global_0_0_out ; + end + (32'h50a0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_mean_global_1_0_out ; + end + (32'h5014 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_misc_cfg_0_out ; + end + (32'h50c0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_nan_flush_to_zero_0_out ; + end + (32'h50c4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_nan_input_data_num_0_out ; + end + (32'h50c8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_nan_input_weight_num_0_out ; + end + (32'h5010 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_op_enable_0_out ; + end + (32'h50e0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_dat_read_latency_0_out ; + end + (32'h50d8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_dat_read_stall_0_out ; + end + (32'h50d4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_enable_0_out ; + end + (32'h50e4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_wt_read_latency_0_out ; + end + (32'h50dc & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_wt_read_stall_0_out ; + end + (32'h5028 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_pixel_offset_0_out ; + end + (32'h5050 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_reserved_x_cfg_0_out ; + end + (32'h5054 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_reserved_y_cfg_0_out ; + end + (32'h5048 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_surf_stride_0_out ; + end + (32'h5078 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_addr_high_0_out ; + end + (32'h507c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_addr_low_0_out ; + end + (32'h5080 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_bytes_0_out ; + end + (32'h5068 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_format_0_out ; + end + (32'h5074 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_ram_type_0_out ; + end + (32'h506c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_size_0_0_out ; + end + (32'h5070 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_size_1_0_out ; + end + (32'h5084 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wgs_addr_high_0_out ; + end + (32'h5088 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wgs_addr_low_0_out ; + end + (32'h508c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wmb_addr_high_0_out ; + end + (32'h5090 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wmb_addr_low_0_out ; + end + (32'h5094 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wmb_bytes_0_out ; + end + (32'h50b4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_zero_padding_0_out ; + end + (32'h50b8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_zero_padding_value_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank[4:0] <= 5'b00000; + weight_bank[4:0] <= 5'b00000; + batches[4:0] <= 5'b00000; + batch_stride[31:0] <= 32'b00000000000000000000000000000000; + conv_x_stride[2:0] <= 3'b000; + conv_y_stride[2:0] <= 3'b000; + cvt_en <= 1'b0; + cvt_truncate[5:0] <= 6'b000000; + cvt_offset[15:0] <= 16'b0000000000000000; + cvt_scale[15:0] <= 16'b0000000000000000; + cya[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_high_0[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_high_1[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_low_0[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_low_1[31:0] <= 32'b00000000000000000000000000000000; + line_packed <= 1'b0; + surf_packed <= 1'b0; + datain_ram_type <= 1'b0; + datain_format <= 1'b0; + pixel_format[5:0] <= 6'b001100; + pixel_mapping <= 1'b0; + pixel_sign_override <= 1'b0; + datain_height[12:0] <= 13'b0000000000000; + datain_width[12:0] <= 13'b0000000000000; + datain_channel[12:0] <= 13'b0000000000000; + datain_height_ext[12:0] <= 13'b0000000000000; + datain_width_ext[12:0] <= 13'b0000000000000; + entries[13:0] <= 14'b000000000000; + grains[11:0] <= 12'b000000000000; + line_stride[31:0] <= 32'b00000000000000000000000000000000; + uv_line_stride[31:0] <= 32'b00000000000000000000000000000000; + mean_format <= 1'b0; + mean_gu[15:0] <= 16'b0000000000000000; + mean_ry[15:0] <= 16'b0000000000000000; + mean_ax[15:0] <= 16'b0000000000000000; + mean_bv[15:0] <= 16'b0000000000000000; + conv_mode <= 1'b0; + data_reuse <= 1'b0; + in_precision[1:0] <= 2'b01; + proc_precision[1:0] <= 2'b01; + skip_data_rls <= 1'b0; + skip_weight_rls <= 1'b0; + weight_reuse <= 1'b0; + nan_to_zero <= 1'b0; + dma_en <= 1'b0; + pixel_x_offset[4:0] <= 5'b00000; + pixel_y_offset[2:0] <= 3'b000; + rsv_per_line[9:0] <= 10'b0000000000; + rsv_per_uv_line[9:0] <= 10'b0000000000; + rsv_height[2:0] <= 3'b000; + rsv_y_index[4:0] <= 5'b00000; + surf_stride[31:0] <= 32'b00000000000000000000000000000000; + weight_addr_high[31:0] <= 32'b00000000000000000000000000000000; + weight_addr_low[31:0] <= 32'b00000000000000000000000000000000; + weight_bytes[31:0] <= 32'b00000000000000000000000000000000; + weight_format <= 1'b0; + weight_ram_type <= 1'b0; + byte_per_kernel[17:0] <= 18'b000000000000000000; + weight_kernel[12:0] <= 13'b0000000000000; + wgs_addr_high[31:0] <= 32'b00000000000000000000000000000000; + wgs_addr_low[31:0] <= 32'b00000000000000000000000000000000; + wmb_addr_high[31:0] <= 32'b00000000000000000000000000000000; + wmb_addr_low[31:0] <= 32'b00000000000000000000000000000000; + wmb_bytes[27:0] <= 28'b0000000000000000000000000000; + pad_bottom[5:0] <= 6'b000000; + pad_left[4:0] <= 5'b00000; + pad_right[5:0] <= 6'b000000; + pad_top[4:0] <= 5'b00000; + pad_value[15:0] <= 16'b0000000000000000; + end else begin +// Register: NVDLA_CDMA_D_BANK_0 Field: data_bank + if (nvdla_cdma_d_bank_0_wren) begin + data_bank[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_BANK_0 Field: weight_bank + if (nvdla_cdma_d_bank_0_wren) begin + weight_bank[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CDMA_D_BATCH_NUMBER_0 Field: batches + if (nvdla_cdma_d_batch_number_0_wren) begin + batches[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_BATCH_STRIDE_0 Field: batch_stride + if (nvdla_cdma_d_batch_stride_0_wren) begin + batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_CONV_STRIDE_0 Field: conv_x_stride + if (nvdla_cdma_d_conv_stride_0_wren) begin + conv_x_stride[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_CDMA_D_CONV_STRIDE_0 Field: conv_y_stride + if (nvdla_cdma_d_conv_stride_0_wren) begin + conv_y_stride[2:0] <= reg_wr_data[18:16]; + end +// Register: NVDLA_CDMA_D_CVT_CFG_0 Field: cvt_en + if (nvdla_cdma_d_cvt_cfg_0_wren) begin + cvt_en <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_CVT_CFG_0 Field: cvt_truncate + if (nvdla_cdma_d_cvt_cfg_0_wren) begin + cvt_truncate[5:0] <= reg_wr_data[9:4]; + end +// Register: NVDLA_CDMA_D_CVT_OFFSET_0 Field: cvt_offset + if (nvdla_cdma_d_cvt_offset_0_wren) begin + cvt_offset[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_CVT_SCALE_0 Field: cvt_scale + if (nvdla_cdma_d_cvt_scale_0_wren) begin + cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_CYA_0 Field: cya + if (nvdla_cdma_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_HIGH_0_0 Field: datain_addr_high_0 + if (nvdla_cdma_d_dain_addr_high_0_0_wren) begin + datain_addr_high_0[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_HIGH_1_0 Field: datain_addr_high_1 + if (nvdla_cdma_d_dain_addr_high_1_0_wren) begin + datain_addr_high_1[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_LOW_0_0 Field: datain_addr_low_0 + if (nvdla_cdma_d_dain_addr_low_0_0_wren) begin + datain_addr_low_0[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_LOW_1_0 Field: datain_addr_low_1 + if (nvdla_cdma_d_dain_addr_low_1_0_wren) begin + datain_addr_low_1[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_MAP_0 Field: line_packed + if (nvdla_cdma_d_dain_map_0_wren) begin + line_packed <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_DAIN_MAP_0 Field: surf_packed + if (nvdla_cdma_d_dain_map_0_wren) begin + surf_packed <= reg_wr_data[16]; + end +// Register: NVDLA_CDMA_D_DAIN_RAM_TYPE_0 Field: datain_ram_type + if (nvdla_cdma_d_dain_ram_type_0_wren) begin + datain_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: datain_format + if (nvdla_cdma_d_datain_format_0_wren) begin + datain_format <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: pixel_format + if (nvdla_cdma_d_datain_format_0_wren) begin + pixel_format[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: pixel_mapping + if (nvdla_cdma_d_datain_format_0_wren) begin + pixel_mapping <= reg_wr_data[16]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: pixel_sign_override + if (nvdla_cdma_d_datain_format_0_wren) begin + pixel_sign_override <= reg_wr_data[20]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_0_0 Field: datain_height + if (nvdla_cdma_d_datain_size_0_0_wren) begin + datain_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_0_0 Field: datain_width + if (nvdla_cdma_d_datain_size_0_0_wren) begin + datain_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_1_0 Field: datain_channel + if (nvdla_cdma_d_datain_size_1_0_wren) begin + datain_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_EXT_0_0 Field: datain_height_ext + if (nvdla_cdma_d_datain_size_ext_0_0_wren) begin + datain_height_ext[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_EXT_0_0 Field: datain_width_ext + if (nvdla_cdma_d_datain_size_ext_0_0_wren) begin + datain_width_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_ENTRY_PER_SLICE_0 Field: entries + if (nvdla_cdma_d_entry_per_slice_0_wren) begin + entries[13:0] <= reg_wr_data[13:0]; + end +// Register: NVDLA_CDMA_D_FETCH_GRAIN_0 Field: grains + if (nvdla_cdma_d_fetch_grain_0_wren) begin + grains[11:0] <= reg_wr_data[11:0]; + end +// Not generating flops for read-only field NVDLA_CDMA_D_INF_INPUT_DATA_NUM_0::inf_data_num +// Not generating flops for read-only field NVDLA_CDMA_D_INF_INPUT_WEIGHT_NUM_0::inf_weight_num +// Register: NVDLA_CDMA_D_LINE_STRIDE_0 Field: line_stride + if (nvdla_cdma_d_line_stride_0_wren) begin + line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_LINE_UV_STRIDE_0 Field: uv_line_stride + if (nvdla_cdma_d_line_uv_stride_0_wren) begin + uv_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_MEAN_FORMAT_0 Field: mean_format + if (nvdla_cdma_d_mean_format_0_wren) begin + mean_format <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_0_0 Field: mean_gu + if (nvdla_cdma_d_mean_global_0_0_wren) begin + mean_gu[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_0_0 Field: mean_ry + if (nvdla_cdma_d_mean_global_0_0_wren) begin + mean_ry[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_1_0 Field: mean_ax + if (nvdla_cdma_d_mean_global_1_0_wren) begin + mean_ax[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_1_0 Field: mean_bv + if (nvdla_cdma_d_mean_global_1_0_wren) begin + mean_bv[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: conv_mode + if (nvdla_cdma_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: data_reuse + if (nvdla_cdma_d_misc_cfg_0_wren) begin + data_reuse <= reg_wr_data[16]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: in_precision + if (nvdla_cdma_d_misc_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[9:8]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: proc_precision + if (nvdla_cdma_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: skip_data_rls + if (nvdla_cdma_d_misc_cfg_0_wren) begin + skip_data_rls <= reg_wr_data[24]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: skip_weight_rls + if (nvdla_cdma_d_misc_cfg_0_wren) begin + skip_weight_rls <= reg_wr_data[28]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: weight_reuse + if (nvdla_cdma_d_misc_cfg_0_wren) begin + weight_reuse <= reg_wr_data[20]; + end +// Register: NVDLA_CDMA_D_NAN_FLUSH_TO_ZERO_0 Field: nan_to_zero + if (nvdla_cdma_d_nan_flush_to_zero_0_wren) begin + nan_to_zero <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDMA_D_NAN_INPUT_DATA_NUM_0::nan_data_num +// Not generating flops for read-only field NVDLA_CDMA_D_NAN_INPUT_WEIGHT_NUM_0::nan_weight_num +// Not generating flops for field NVDLA_CDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_DAT_READ_LATENCY_0::dat_rd_latency +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_DAT_READ_STALL_0::dat_rd_stall +// Register: NVDLA_CDMA_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_cdma_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_WT_READ_LATENCY_0::wt_rd_latency +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_WT_READ_STALL_0::wt_rd_stall +// Register: NVDLA_CDMA_D_PIXEL_OFFSET_0 Field: pixel_x_offset + if (nvdla_cdma_d_pixel_offset_0_wren) begin + pixel_x_offset[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_PIXEL_OFFSET_0 Field: pixel_y_offset + if (nvdla_cdma_d_pixel_offset_0_wren) begin + pixel_y_offset[2:0] <= reg_wr_data[18:16]; + end +// Register: NVDLA_CDMA_D_RESERVED_X_CFG_0 Field: rsv_per_line + if (nvdla_cdma_d_reserved_x_cfg_0_wren) begin + rsv_per_line[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_CDMA_D_RESERVED_X_CFG_0 Field: rsv_per_uv_line + if (nvdla_cdma_d_reserved_x_cfg_0_wren) begin + rsv_per_uv_line[9:0] <= reg_wr_data[25:16]; + end +// Register: NVDLA_CDMA_D_RESERVED_Y_CFG_0 Field: rsv_height + if (nvdla_cdma_d_reserved_y_cfg_0_wren) begin + rsv_height[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_CDMA_D_RESERVED_Y_CFG_0 Field: rsv_y_index + if (nvdla_cdma_d_reserved_y_cfg_0_wren) begin + rsv_y_index[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CDMA_D_SURF_STRIDE_0 Field: surf_stride + if (nvdla_cdma_d_surf_stride_0_wren) begin + surf_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_ADDR_HIGH_0 Field: weight_addr_high + if (nvdla_cdma_d_weight_addr_high_0_wren) begin + weight_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_ADDR_LOW_0 Field: weight_addr_low + if (nvdla_cdma_d_weight_addr_low_0_wren) begin + weight_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_BYTES_0 Field: weight_bytes + if (nvdla_cdma_d_weight_bytes_0_wren) begin + weight_bytes[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_FORMAT_0 Field: weight_format + if (nvdla_cdma_d_weight_format_0_wren) begin + weight_format <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_RAM_TYPE_0 Field: weight_ram_type + if (nvdla_cdma_d_weight_ram_type_0_wren) begin + weight_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_SIZE_0_0 Field: byte_per_kernel + if (nvdla_cdma_d_weight_size_0_0_wren) begin + byte_per_kernel[17:0] <= reg_wr_data[17:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_SIZE_1_0 Field: weight_kernel + if (nvdla_cdma_d_weight_size_1_0_wren) begin + weight_kernel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_WGS_ADDR_HIGH_0 Field: wgs_addr_high + if (nvdla_cdma_d_wgs_addr_high_0_wren) begin + wgs_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WGS_ADDR_LOW_0 Field: wgs_addr_low + if (nvdla_cdma_d_wgs_addr_low_0_wren) begin + wgs_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WMB_ADDR_HIGH_0 Field: wmb_addr_high + if (nvdla_cdma_d_wmb_addr_high_0_wren) begin + wmb_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WMB_ADDR_LOW_0 Field: wmb_addr_low + if (nvdla_cdma_d_wmb_addr_low_0_wren) begin + wmb_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WMB_BYTES_0 Field: wmb_bytes + if (nvdla_cdma_d_wmb_bytes_0_wren) begin + wmb_bytes[27:0] <= reg_wr_data[27:0]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_bottom + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_bottom[5:0] <= reg_wr_data[29:24]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_left + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_left[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_right + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_right[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_top + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_top[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_VALUE_0 Field: pad_value + if (nvdla_cdma_d_zero_padding_value_0_wren) begin + pad_value[15:0] <= reg_wr_data[15:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h50bc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_BANK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_bank_0_out, nvdla_cdma_d_bank_0_out); + (32'h5058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_BATCH_NUMBER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_batch_number_0_out, nvdla_cdma_d_batch_number_0_out); + (32'h505c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_batch_stride_0_out, nvdla_cdma_d_batch_stride_0_out); + (32'h50b0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CONV_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_conv_stride_0_out, nvdla_cdma_d_conv_stride_0_out); + (32'h50a4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CVT_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cvt_cfg_0_out, nvdla_cdma_d_cvt_cfg_0_out); + (32'h50a8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CVT_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cvt_offset_0_out, nvdla_cdma_d_cvt_offset_0_out); + (32'h50ac & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CVT_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cvt_scale_0_out, nvdla_cdma_d_cvt_scale_0_out); + (32'h50e8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cya_0_out, nvdla_cdma_d_cya_0_out); + (32'h5030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_HIGH_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_high_0_0_out, nvdla_cdma_d_dain_addr_high_0_0_out); + (32'h5038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_HIGH_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_high_1_0_out, nvdla_cdma_d_dain_addr_high_1_0_out); + (32'h5034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_LOW_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_low_0_0_out, nvdla_cdma_d_dain_addr_low_0_0_out); + (32'h503c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_LOW_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_low_1_0_out, nvdla_cdma_d_dain_addr_low_1_0_out); + (32'h504c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_MAP_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_map_0_out, nvdla_cdma_d_dain_map_0_out); + (32'h502c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_ram_type_0_out, nvdla_cdma_d_dain_ram_type_0_out); + (32'h5018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_format_0_out, nvdla_cdma_d_datain_format_0_out); + (32'h501c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_size_0_0_out, nvdla_cdma_d_datain_size_0_0_out); + (32'h5020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_size_1_0_out, nvdla_cdma_d_datain_size_1_0_out); + (32'h5024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_SIZE_EXT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_size_ext_0_0_out, nvdla_cdma_d_datain_size_ext_0_0_out); + (32'h5060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_ENTRY_PER_SLICE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_entry_per_slice_0_out, nvdla_cdma_d_entry_per_slice_0_out); + (32'h5064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_FETCH_GRAIN_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_fetch_grain_0_out, nvdla_cdma_d_fetch_grain_0_out); + (32'h50cc & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_INF_INPUT_DATA_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50d0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_INF_INPUT_WEIGHT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_line_stride_0_out, nvdla_cdma_d_line_stride_0_out); + (32'h5044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_LINE_UV_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_line_uv_stride_0_out, nvdla_cdma_d_line_uv_stride_0_out); + (32'h5098 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MEAN_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_mean_format_0_out, nvdla_cdma_d_mean_format_0_out); + (32'h509c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MEAN_GLOBAL_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_mean_global_0_0_out, nvdla_cdma_d_mean_global_0_0_out); + (32'h50a0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MEAN_GLOBAL_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_mean_global_1_0_out, nvdla_cdma_d_mean_global_1_0_out); + (32'h5014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_misc_cfg_0_out, nvdla_cdma_d_misc_cfg_0_out); + (32'h50c0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_NAN_FLUSH_TO_ZERO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_nan_flush_to_zero_0_out, nvdla_cdma_d_nan_flush_to_zero_0_out); + (32'h50c4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_NAN_INPUT_DATA_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50c8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_NAN_INPUT_WEIGHT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_op_enable_0_out, nvdla_cdma_d_op_enable_0_out); + (32'h50e0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_DAT_READ_LATENCY_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50d8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_DAT_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50d4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_perf_enable_0_out, nvdla_cdma_d_perf_enable_0_out); + (32'h50e4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_WT_READ_LATENCY_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50dc & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_WT_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_PIXEL_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_pixel_offset_0_out, nvdla_cdma_d_pixel_offset_0_out); + (32'h5050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_RESERVED_X_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_reserved_x_cfg_0_out, nvdla_cdma_d_reserved_x_cfg_0_out); + (32'h5054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_RESERVED_Y_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_reserved_y_cfg_0_out, nvdla_cdma_d_reserved_y_cfg_0_out); + (32'h5048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_surf_stride_0_out, nvdla_cdma_d_surf_stride_0_out); + (32'h5078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_addr_high_0_out, nvdla_cdma_d_weight_addr_high_0_out); + (32'h507c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_addr_low_0_out, nvdla_cdma_d_weight_addr_low_0_out); + (32'h5080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_bytes_0_out, nvdla_cdma_d_weight_bytes_0_out); + (32'h5068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_format_0_out, nvdla_cdma_d_weight_format_0_out); + (32'h5074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_ram_type_0_out, nvdla_cdma_d_weight_ram_type_0_out); + (32'h506c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_size_0_0_out, nvdla_cdma_d_weight_size_0_0_out); + (32'h5070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_size_1_0_out, nvdla_cdma_d_weight_size_1_0_out); + (32'h5084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WGS_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wgs_addr_high_0_out, nvdla_cdma_d_wgs_addr_high_0_out); + (32'h5088 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WGS_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wgs_addr_low_0_out, nvdla_cdma_d_wgs_addr_low_0_out); + (32'h508c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WMB_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wmb_addr_high_0_out, nvdla_cdma_d_wmb_addr_high_0_out); + (32'h5090 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WMB_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wmb_addr_low_0_out, nvdla_cdma_d_wmb_addr_low_0_out); + (32'h5094 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WMB_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wmb_bytes_0_out, nvdla_cdma_d_wmb_bytes_0_out); + (32'h50b4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_ZERO_PADDING_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_zero_padding_0_out, nvdla_cdma_d_zero_padding_0_out); + (32'h50b8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_ZERO_PADDING_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_zero_padding_value_0_out, nvdla_cdma_d_zero_padding_value_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDMA_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v.vcp new file mode 100644 index 0000000..dfdd7b9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v.vcp @@ -0,0 +1,1131 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_dual_reg.v +module NV_NVDLA_CDMA_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,data_bank + ,weight_bank + ,batches + ,batch_stride + ,conv_x_stride + ,conv_y_stride + ,cvt_en + ,cvt_truncate + ,cvt_offset + ,cvt_scale + ,cya + ,datain_addr_high_0 + ,datain_addr_high_1 + ,datain_addr_low_0 + ,datain_addr_low_1 + ,line_packed + ,surf_packed + ,datain_ram_type + ,datain_format + ,pixel_format + ,pixel_mapping + ,pixel_sign_override + ,datain_height + ,datain_width + ,datain_channel + ,datain_height_ext + ,datain_width_ext + ,entries + ,grains + ,line_stride + ,uv_line_stride + ,mean_format + ,mean_gu + ,mean_ry + ,mean_ax + ,mean_bv + ,conv_mode + ,data_reuse + ,in_precision + ,proc_precision + ,skip_data_rls + ,skip_weight_rls + ,weight_reuse + ,nan_to_zero + ,op_en_trigger + ,dma_en + ,pixel_x_offset + ,pixel_y_offset + ,rsv_per_line + ,rsv_per_uv_line + ,rsv_height + ,rsv_y_index + ,surf_stride + ,weight_addr_high + ,weight_addr_low + ,weight_bytes + ,weight_format + ,weight_ram_type + ,byte_per_kernel + ,weight_kernel + ,wgs_addr_high + ,wgs_addr_low + ,wmb_addr_high + ,wmb_addr_low + ,wmb_bytes + ,pad_bottom + ,pad_left + ,pad_right + ,pad_top + ,pad_value + ,inf_data_num + ,inf_weight_num + ,nan_data_num + ,nan_weight_num + ,op_en + ,dat_rd_latency + ,dat_rd_stall + ,wt_rd_latency + ,wt_rd_stall + ); +wire [31:0] nvdla_cdma_d_bank_0_out; +wire [31:0] nvdla_cdma_d_batch_number_0_out; +wire [31:0] nvdla_cdma_d_batch_stride_0_out; +wire [31:0] nvdla_cdma_d_conv_stride_0_out; +wire [31:0] nvdla_cdma_d_cvt_cfg_0_out; +wire [31:0] nvdla_cdma_d_cvt_offset_0_out; +wire [31:0] nvdla_cdma_d_cvt_scale_0_out; +wire [31:0] nvdla_cdma_d_cya_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_high_0_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_high_1_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_low_0_0_out; +wire [31:0] nvdla_cdma_d_dain_addr_low_1_0_out; +wire [31:0] nvdla_cdma_d_dain_map_0_out; +wire [31:0] nvdla_cdma_d_dain_ram_type_0_out; +wire [31:0] nvdla_cdma_d_datain_format_0_out; +wire [31:0] nvdla_cdma_d_datain_size_0_0_out; +wire [31:0] nvdla_cdma_d_datain_size_1_0_out; +wire [31:0] nvdla_cdma_d_datain_size_ext_0_0_out; +wire [31:0] nvdla_cdma_d_entry_per_slice_0_out; +wire [31:0] nvdla_cdma_d_fetch_grain_0_out; +wire [31:0] nvdla_cdma_d_inf_input_data_num_0_out; +wire [31:0] nvdla_cdma_d_inf_input_weight_num_0_out; +wire [31:0] nvdla_cdma_d_line_stride_0_out; +wire [31:0] nvdla_cdma_d_line_uv_stride_0_out; +wire [31:0] nvdla_cdma_d_mean_format_0_out; +wire [31:0] nvdla_cdma_d_mean_global_0_0_out; +wire [31:0] nvdla_cdma_d_mean_global_1_0_out; +wire [31:0] nvdla_cdma_d_misc_cfg_0_out; +wire [31:0] nvdla_cdma_d_nan_flush_to_zero_0_out; +wire [31:0] nvdla_cdma_d_nan_input_data_num_0_out; +wire [31:0] nvdla_cdma_d_nan_input_weight_num_0_out; +wire [31:0] nvdla_cdma_d_op_enable_0_out; +wire [31:0] nvdla_cdma_d_perf_dat_read_latency_0_out; +wire [31:0] nvdla_cdma_d_perf_dat_read_stall_0_out; +wire [31:0] nvdla_cdma_d_perf_enable_0_out; +wire [31:0] nvdla_cdma_d_perf_wt_read_latency_0_out; +wire [31:0] nvdla_cdma_d_perf_wt_read_stall_0_out; +wire [31:0] nvdla_cdma_d_pixel_offset_0_out; +wire [31:0] nvdla_cdma_d_reserved_x_cfg_0_out; +wire [31:0] nvdla_cdma_d_reserved_y_cfg_0_out; +wire [31:0] nvdla_cdma_d_surf_stride_0_out; +wire [31:0] nvdla_cdma_d_weight_addr_high_0_out; +wire [31:0] nvdla_cdma_d_weight_addr_low_0_out; +wire [31:0] nvdla_cdma_d_weight_bytes_0_out; +wire [31:0] nvdla_cdma_d_weight_format_0_out; +wire [31:0] nvdla_cdma_d_weight_ram_type_0_out; +wire [31:0] nvdla_cdma_d_weight_size_0_0_out; +wire [31:0] nvdla_cdma_d_weight_size_1_0_out; +wire [31:0] nvdla_cdma_d_wgs_addr_high_0_out; +wire [31:0] nvdla_cdma_d_wgs_addr_low_0_out; +wire [31:0] nvdla_cdma_d_wmb_addr_high_0_out; +wire [31:0] nvdla_cdma_d_wmb_addr_low_0_out; +wire [31:0] nvdla_cdma_d_wmb_bytes_0_out; +wire [31:0] nvdla_cdma_d_zero_padding_0_out; +wire [31:0] nvdla_cdma_d_zero_padding_value_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [4:0] data_bank; +output [4:0] weight_bank; +output [4:0] batches; +output [31:0] batch_stride; +output [2:0] conv_x_stride; +output [2:0] conv_y_stride; +output cvt_en; +output [5:0] cvt_truncate; +output [15:0] cvt_offset; +output [15:0] cvt_scale; +output [31:0] cya; +output [31:0] datain_addr_high_0; +output [31:0] datain_addr_high_1; +output [31:0] datain_addr_low_0; +output [31:0] datain_addr_low_1; +output line_packed; +output surf_packed; +output datain_ram_type; +output datain_format; +output [5:0] pixel_format; +output pixel_mapping; +output pixel_sign_override; +output [12:0] datain_height; +output [12:0] datain_width; +output [12:0] datain_channel; +output [12:0] datain_height_ext; +output [12:0] datain_width_ext; +output [13:0] entries; +output [11:0] grains; +output [31:0] line_stride; +output [31:0] uv_line_stride; +output mean_format; +output [15:0] mean_gu; +output [15:0] mean_ry; +output [15:0] mean_ax; +output [15:0] mean_bv; +output conv_mode; +output data_reuse; +output [1:0] in_precision; +output [1:0] proc_precision; +output skip_data_rls; +output skip_weight_rls; +output weight_reuse; +output nan_to_zero; +output op_en_trigger; +output dma_en; +output [4:0] pixel_x_offset; +output [2:0] pixel_y_offset; +output [9:0] rsv_per_line; +output [9:0] rsv_per_uv_line; +output [2:0] rsv_height; +output [4:0] rsv_y_index; +output [31:0] surf_stride; +output [31:0] weight_addr_high; +output [31:0] weight_addr_low; +output [31:0] weight_bytes; +output weight_format; +output weight_ram_type; +output [17:0] byte_per_kernel; +output [12:0] weight_kernel; +output [31:0] wgs_addr_high; +output [31:0] wgs_addr_low; +output [31:0] wmb_addr_high; +output [31:0] wmb_addr_low; +output [27:0] wmb_bytes; +output [5:0] pad_bottom; +output [4:0] pad_left; +output [5:0] pad_right; +output [4:0] pad_top; +output [15:0] pad_value; +// Read-only register inputs +input [31:0] inf_data_num; +input [31:0] inf_weight_num; +input [31:0] nan_data_num; +input [31:0] nan_weight_num; +input op_en; +input [31:0] dat_rd_latency; +input [31:0] dat_rd_stall; +input [31:0] wt_rd_latency; +input [31:0] wt_rd_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [31:0] batch_stride; +reg [4:0] batches; +reg [17:0] byte_per_kernel; +reg conv_mode; +reg [2:0] conv_x_stride; +reg [2:0] conv_y_stride; +reg cvt_en; +reg [15:0] cvt_offset; +reg [15:0] cvt_scale; +reg [5:0] cvt_truncate; +reg [31:0] cya; +reg [4:0] data_bank; +reg data_reuse; +reg [31:0] datain_addr_high_0; +reg [31:0] datain_addr_high_1; +reg [31:0] datain_addr_low_0; +reg [31:0] datain_addr_low_1; +reg [12:0] datain_channel; +reg datain_format; +reg [12:0] datain_height; +reg [12:0] datain_height_ext; +reg datain_ram_type; +reg [12:0] datain_width; +reg [12:0] datain_width_ext; +reg dma_en; +reg [13:0] entries; +reg [11:0] grains; +reg [1:0] in_precision; +reg line_packed; +reg [31:0] line_stride; +reg [15:0] mean_ax; +reg [15:0] mean_bv; +reg mean_format; +reg [15:0] mean_gu; +reg [15:0] mean_ry; +reg nan_to_zero; +reg [5:0] pad_bottom; +reg [4:0] pad_left; +reg [5:0] pad_right; +reg [4:0] pad_top; +reg [15:0] pad_value; +reg [5:0] pixel_format; +reg pixel_mapping; +reg pixel_sign_override; +reg [4:0] pixel_x_offset; +reg [2:0] pixel_y_offset; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [2:0] rsv_height; +reg [9:0] rsv_per_line; +reg [9:0] rsv_per_uv_line; +reg [4:0] rsv_y_index; +reg skip_data_rls; +reg skip_weight_rls; +reg surf_packed; +reg [31:0] surf_stride; +reg [31:0] uv_line_stride; +reg [31:0] weight_addr_high; +reg [31:0] weight_addr_low; +reg [4:0] weight_bank; +reg [31:0] weight_bytes; +reg weight_format; +reg [12:0] weight_kernel; +reg weight_ram_type; +reg weight_reuse; +reg [31:0] wgs_addr_high; +reg [31:0] wgs_addr_low; +reg [31:0] wmb_addr_high; +reg [31:0] wmb_addr_low; +reg [27:0] wmb_bytes; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdma_d_bank_0_wren = (reg_offset_wr == (32'h50bc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_batch_number_0_wren = (reg_offset_wr == (32'h5058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_batch_stride_0_wren = (reg_offset_wr == (32'h505c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_conv_stride_0_wren = (reg_offset_wr == (32'h50b0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cvt_cfg_0_wren = (reg_offset_wr == (32'h50a4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cvt_offset_0_wren = (reg_offset_wr == (32'h50a8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cvt_scale_0_wren = (reg_offset_wr == (32'h50ac & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_cya_0_wren = (reg_offset_wr == (32'h50e8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_high_0_0_wren = (reg_offset_wr == (32'h5030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_high_1_0_wren = (reg_offset_wr == (32'h5038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_low_0_0_wren = (reg_offset_wr == (32'h5034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_addr_low_1_0_wren = (reg_offset_wr == (32'h503c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_map_0_wren = (reg_offset_wr == (32'h504c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_dain_ram_type_0_wren = (reg_offset_wr == (32'h502c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_format_0_wren = (reg_offset_wr == (32'h5018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_size_0_0_wren = (reg_offset_wr == (32'h501c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_size_1_0_wren = (reg_offset_wr == (32'h5020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_datain_size_ext_0_0_wren = (reg_offset_wr == (32'h5024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_entry_per_slice_0_wren = (reg_offset_wr == (32'h5060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_fetch_grain_0_wren = (reg_offset_wr == (32'h5064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_inf_input_data_num_0_wren = (reg_offset_wr == (32'h50cc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_inf_input_weight_num_0_wren = (reg_offset_wr == (32'h50d0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_line_stride_0_wren = (reg_offset_wr == (32'h5040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_line_uv_stride_0_wren = (reg_offset_wr == (32'h5044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_mean_format_0_wren = (reg_offset_wr == (32'h5098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_mean_global_0_0_wren = (reg_offset_wr == (32'h509c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_mean_global_1_0_wren = (reg_offset_wr == (32'h50a0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_misc_cfg_0_wren = (reg_offset_wr == (32'h5014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_nan_flush_to_zero_0_wren = (reg_offset_wr == (32'h50c0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_nan_input_data_num_0_wren = (reg_offset_wr == (32'h50c4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_nan_input_weight_num_0_wren = (reg_offset_wr == (32'h50c8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_op_enable_0_wren = (reg_offset_wr == (32'h5010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_dat_read_latency_0_wren = (reg_offset_wr == (32'h50e0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_dat_read_stall_0_wren = (reg_offset_wr == (32'h50d8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_enable_0_wren = (reg_offset_wr == (32'h50d4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_wt_read_latency_0_wren = (reg_offset_wr == (32'h50e4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_perf_wt_read_stall_0_wren = (reg_offset_wr == (32'h50dc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_pixel_offset_0_wren = (reg_offset_wr == (32'h5028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_reserved_x_cfg_0_wren = (reg_offset_wr == (32'h5050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_reserved_y_cfg_0_wren = (reg_offset_wr == (32'h5054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_surf_stride_0_wren = (reg_offset_wr == (32'h5048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_addr_high_0_wren = (reg_offset_wr == (32'h5078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_addr_low_0_wren = (reg_offset_wr == (32'h507c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_bytes_0_wren = (reg_offset_wr == (32'h5080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_format_0_wren = (reg_offset_wr == (32'h5068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_ram_type_0_wren = (reg_offset_wr == (32'h5074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_size_0_0_wren = (reg_offset_wr == (32'h506c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_weight_size_1_0_wren = (reg_offset_wr == (32'h5070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wgs_addr_high_0_wren = (reg_offset_wr == (32'h5084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wgs_addr_low_0_wren = (reg_offset_wr == (32'h5088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wmb_addr_high_0_wren = (reg_offset_wr == (32'h508c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wmb_addr_low_0_wren = (reg_offset_wr == (32'h5090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_wmb_bytes_0_wren = (reg_offset_wr == (32'h5094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_zero_padding_0_wren = (reg_offset_wr == (32'h50b4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_d_zero_padding_value_0_wren = (reg_offset_wr == (32'h50b8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdma_d_bank_0_out[31:0] = { 11'b0, weight_bank, 11'b0, data_bank }; +assign nvdla_cdma_d_batch_number_0_out[31:0] = { 27'b0, batches }; +assign nvdla_cdma_d_batch_stride_0_out[31:0] = { batch_stride }; +assign nvdla_cdma_d_conv_stride_0_out[31:0] = { 13'b0, conv_y_stride, 13'b0, conv_x_stride }; +assign nvdla_cdma_d_cvt_cfg_0_out[31:0] = { 22'b0, cvt_truncate, 3'b0, cvt_en }; +assign nvdla_cdma_d_cvt_offset_0_out[31:0] = { 16'b0, cvt_offset }; +assign nvdla_cdma_d_cvt_scale_0_out[31:0] = { 16'b0, cvt_scale }; +assign nvdla_cdma_d_cya_0_out[31:0] = { cya }; +assign nvdla_cdma_d_dain_addr_high_0_0_out[31:0] = { datain_addr_high_0 }; +assign nvdla_cdma_d_dain_addr_high_1_0_out[31:0] = { datain_addr_high_1 }; +assign nvdla_cdma_d_dain_addr_low_0_0_out[31:0] = { datain_addr_low_0 }; +assign nvdla_cdma_d_dain_addr_low_1_0_out[31:0] = { datain_addr_low_1 }; +assign nvdla_cdma_d_dain_map_0_out[31:0] = { 15'b0, surf_packed, 15'b0, line_packed }; +assign nvdla_cdma_d_dain_ram_type_0_out[31:0] = { 31'b0, datain_ram_type }; +assign nvdla_cdma_d_datain_format_0_out[31:0] = { 11'b0, pixel_sign_override, 3'b0, pixel_mapping, 2'b0, pixel_format, 7'b0, datain_format }; +assign nvdla_cdma_d_datain_size_0_0_out[31:0] = { 3'b0, datain_height, 3'b0, datain_width }; +assign nvdla_cdma_d_datain_size_1_0_out[31:0] = { 19'b0, datain_channel }; +assign nvdla_cdma_d_datain_size_ext_0_0_out[31:0] = { 3'b0, datain_height_ext, 3'b0, datain_width_ext }; +assign nvdla_cdma_d_entry_per_slice_0_out[31:0] = { 18'b0, entries }; +assign nvdla_cdma_d_fetch_grain_0_out[31:0] = { 20'b0, grains }; +assign nvdla_cdma_d_inf_input_data_num_0_out[31:0] = { inf_data_num }; +assign nvdla_cdma_d_inf_input_weight_num_0_out[31:0] = { inf_weight_num }; +assign nvdla_cdma_d_line_stride_0_out[31:0] = { line_stride }; +assign nvdla_cdma_d_line_uv_stride_0_out[31:0] = { uv_line_stride }; +assign nvdla_cdma_d_mean_format_0_out[31:0] = { 31'b0, mean_format }; +assign nvdla_cdma_d_mean_global_0_0_out[31:0] = { mean_gu, mean_ry }; +assign nvdla_cdma_d_mean_global_1_0_out[31:0] = { mean_ax, mean_bv }; +assign nvdla_cdma_d_misc_cfg_0_out[31:0] = { 3'b0, skip_weight_rls, 3'b0, skip_data_rls, 3'b0, weight_reuse, 3'b0, data_reuse, 2'b0, proc_precision, 2'b0, in_precision, 7'b0, conv_mode }; +assign nvdla_cdma_d_nan_flush_to_zero_0_out[31:0] = { 31'b0, nan_to_zero }; +assign nvdla_cdma_d_nan_input_data_num_0_out[31:0] = { nan_data_num }; +assign nvdla_cdma_d_nan_input_weight_num_0_out[31:0] = { nan_weight_num }; +assign nvdla_cdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cdma_d_perf_dat_read_latency_0_out[31:0] = { dat_rd_latency }; +assign nvdla_cdma_d_perf_dat_read_stall_0_out[31:0] = { dat_rd_stall }; +assign nvdla_cdma_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_cdma_d_perf_wt_read_latency_0_out[31:0] = { wt_rd_latency }; +assign nvdla_cdma_d_perf_wt_read_stall_0_out[31:0] = { wt_rd_stall }; +assign nvdla_cdma_d_pixel_offset_0_out[31:0] = { 13'b0, pixel_y_offset, 11'b0, pixel_x_offset }; +assign nvdla_cdma_d_reserved_x_cfg_0_out[31:0] = { 6'b0, rsv_per_uv_line, 6'b0, rsv_per_line }; +assign nvdla_cdma_d_reserved_y_cfg_0_out[31:0] = { 11'b0, rsv_y_index, 13'b0, rsv_height }; +assign nvdla_cdma_d_surf_stride_0_out[31:0] = { surf_stride }; +assign nvdla_cdma_d_weight_addr_high_0_out[31:0] = { weight_addr_high }; +assign nvdla_cdma_d_weight_addr_low_0_out[31:0] = { weight_addr_low }; +assign nvdla_cdma_d_weight_bytes_0_out[31:0] = { weight_bytes }; +assign nvdla_cdma_d_weight_format_0_out[31:0] = { 31'b0, weight_format }; +assign nvdla_cdma_d_weight_ram_type_0_out[31:0] = { 31'b0, weight_ram_type }; +assign nvdla_cdma_d_weight_size_0_0_out[31:0] = { 14'b0, byte_per_kernel }; +assign nvdla_cdma_d_weight_size_1_0_out[31:0] = { 19'b0, weight_kernel }; +assign nvdla_cdma_d_wgs_addr_high_0_out[31:0] = { wgs_addr_high }; +assign nvdla_cdma_d_wgs_addr_low_0_out[31:0] = { wgs_addr_low }; +assign nvdla_cdma_d_wmb_addr_high_0_out[31:0] = { wmb_addr_high }; +assign nvdla_cdma_d_wmb_addr_low_0_out[31:0] = { wmb_addr_low }; +assign nvdla_cdma_d_wmb_bytes_0_out[31:0] = { 4'b0, wmb_bytes }; +assign nvdla_cdma_d_zero_padding_0_out[31:0] = { 2'b0, pad_bottom, 3'b0, pad_top, 2'b0, pad_right, 3'b0, pad_left }; +assign nvdla_cdma_d_zero_padding_value_0_out[31:0] = { 16'b0, pad_value }; +assign op_en_trigger = nvdla_cdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdma_d_bank_0_out + or nvdla_cdma_d_batch_number_0_out + or nvdla_cdma_d_batch_stride_0_out + or nvdla_cdma_d_conv_stride_0_out + or nvdla_cdma_d_cvt_cfg_0_out + or nvdla_cdma_d_cvt_offset_0_out + or nvdla_cdma_d_cvt_scale_0_out + or nvdla_cdma_d_cya_0_out + or nvdla_cdma_d_dain_addr_high_0_0_out + or nvdla_cdma_d_dain_addr_high_1_0_out + or nvdla_cdma_d_dain_addr_low_0_0_out + or nvdla_cdma_d_dain_addr_low_1_0_out + or nvdla_cdma_d_dain_map_0_out + or nvdla_cdma_d_dain_ram_type_0_out + or nvdla_cdma_d_datain_format_0_out + or nvdla_cdma_d_datain_size_0_0_out + or nvdla_cdma_d_datain_size_1_0_out + or nvdla_cdma_d_datain_size_ext_0_0_out + or nvdla_cdma_d_entry_per_slice_0_out + or nvdla_cdma_d_fetch_grain_0_out + or nvdla_cdma_d_inf_input_data_num_0_out + or nvdla_cdma_d_inf_input_weight_num_0_out + or nvdla_cdma_d_line_stride_0_out + or nvdla_cdma_d_line_uv_stride_0_out + or nvdla_cdma_d_mean_format_0_out + or nvdla_cdma_d_mean_global_0_0_out + or nvdla_cdma_d_mean_global_1_0_out + or nvdla_cdma_d_misc_cfg_0_out + or nvdla_cdma_d_nan_flush_to_zero_0_out + or nvdla_cdma_d_nan_input_data_num_0_out + or nvdla_cdma_d_nan_input_weight_num_0_out + or nvdla_cdma_d_op_enable_0_out + or nvdla_cdma_d_perf_dat_read_latency_0_out + or nvdla_cdma_d_perf_dat_read_stall_0_out + or nvdla_cdma_d_perf_enable_0_out + or nvdla_cdma_d_perf_wt_read_latency_0_out + or nvdla_cdma_d_perf_wt_read_stall_0_out + or nvdla_cdma_d_pixel_offset_0_out + or nvdla_cdma_d_reserved_x_cfg_0_out + or nvdla_cdma_d_reserved_y_cfg_0_out + or nvdla_cdma_d_surf_stride_0_out + or nvdla_cdma_d_weight_addr_high_0_out + or nvdla_cdma_d_weight_addr_low_0_out + or nvdla_cdma_d_weight_bytes_0_out + or nvdla_cdma_d_weight_format_0_out + or nvdla_cdma_d_weight_ram_type_0_out + or nvdla_cdma_d_weight_size_0_0_out + or nvdla_cdma_d_weight_size_1_0_out + or nvdla_cdma_d_wgs_addr_high_0_out + or nvdla_cdma_d_wgs_addr_low_0_out + or nvdla_cdma_d_wmb_addr_high_0_out + or nvdla_cdma_d_wmb_addr_low_0_out + or nvdla_cdma_d_wmb_bytes_0_out + or nvdla_cdma_d_zero_padding_0_out + or nvdla_cdma_d_zero_padding_value_0_out + ) begin + case (reg_offset_rd_int) + (32'h50bc & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_bank_0_out ; + end + (32'h5058 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_batch_number_0_out ; + end + (32'h505c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_batch_stride_0_out ; + end + (32'h50b0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_conv_stride_0_out ; + end + (32'h50a4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cvt_cfg_0_out ; + end + (32'h50a8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cvt_offset_0_out ; + end + (32'h50ac & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cvt_scale_0_out ; + end + (32'h50e8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_cya_0_out ; + end + (32'h5030 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_high_0_0_out ; + end + (32'h5038 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_high_1_0_out ; + end + (32'h5034 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_low_0_0_out ; + end + (32'h503c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_addr_low_1_0_out ; + end + (32'h504c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_map_0_out ; + end + (32'h502c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_dain_ram_type_0_out ; + end + (32'h5018 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_format_0_out ; + end + (32'h501c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_size_0_0_out ; + end + (32'h5020 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_size_1_0_out ; + end + (32'h5024 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_datain_size_ext_0_0_out ; + end + (32'h5060 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_entry_per_slice_0_out ; + end + (32'h5064 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_fetch_grain_0_out ; + end + (32'h50cc & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_inf_input_data_num_0_out ; + end + (32'h50d0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_inf_input_weight_num_0_out ; + end + (32'h5040 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_line_stride_0_out ; + end + (32'h5044 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_line_uv_stride_0_out ; + end + (32'h5098 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_mean_format_0_out ; + end + (32'h509c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_mean_global_0_0_out ; + end + (32'h50a0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_mean_global_1_0_out ; + end + (32'h5014 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_misc_cfg_0_out ; + end + (32'h50c0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_nan_flush_to_zero_0_out ; + end + (32'h50c4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_nan_input_data_num_0_out ; + end + (32'h50c8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_nan_input_weight_num_0_out ; + end + (32'h5010 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_op_enable_0_out ; + end + (32'h50e0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_dat_read_latency_0_out ; + end + (32'h50d8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_dat_read_stall_0_out ; + end + (32'h50d4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_enable_0_out ; + end + (32'h50e4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_wt_read_latency_0_out ; + end + (32'h50dc & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_perf_wt_read_stall_0_out ; + end + (32'h5028 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_pixel_offset_0_out ; + end + (32'h5050 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_reserved_x_cfg_0_out ; + end + (32'h5054 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_reserved_y_cfg_0_out ; + end + (32'h5048 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_surf_stride_0_out ; + end + (32'h5078 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_addr_high_0_out ; + end + (32'h507c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_addr_low_0_out ; + end + (32'h5080 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_bytes_0_out ; + end + (32'h5068 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_format_0_out ; + end + (32'h5074 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_ram_type_0_out ; + end + (32'h506c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_size_0_0_out ; + end + (32'h5070 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_weight_size_1_0_out ; + end + (32'h5084 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wgs_addr_high_0_out ; + end + (32'h5088 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wgs_addr_low_0_out ; + end + (32'h508c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wmb_addr_high_0_out ; + end + (32'h5090 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wmb_addr_low_0_out ; + end + (32'h5094 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_wmb_bytes_0_out ; + end + (32'h50b4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_zero_padding_0_out ; + end + (32'h50b8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_d_zero_padding_value_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank[4:0] <= 5'b00000; + weight_bank[4:0] <= 5'b00000; + batches[4:0] <= 5'b00000; + batch_stride[31:0] <= 32'b00000000000000000000000000000000; + conv_x_stride[2:0] <= 3'b000; + conv_y_stride[2:0] <= 3'b000; + cvt_en <= 1'b0; + cvt_truncate[5:0] <= 6'b000000; + cvt_offset[15:0] <= 16'b0000000000000000; + cvt_scale[15:0] <= 16'b0000000000000000; + cya[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_high_0[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_high_1[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_low_0[31:0] <= 32'b00000000000000000000000000000000; + datain_addr_low_1[31:0] <= 32'b00000000000000000000000000000000; + line_packed <= 1'b0; + surf_packed <= 1'b0; + datain_ram_type <= 1'b0; + datain_format <= 1'b0; + pixel_format[5:0] <= 6'b001100; + pixel_mapping <= 1'b0; + pixel_sign_override <= 1'b0; + datain_height[12:0] <= 13'b0000000000000; + datain_width[12:0] <= 13'b0000000000000; + datain_channel[12:0] <= 13'b0000000000000; + datain_height_ext[12:0] <= 13'b0000000000000; + datain_width_ext[12:0] <= 13'b0000000000000; + entries[13:0] <= 14'b000000000000; + grains[11:0] <= 12'b000000000000; + line_stride[31:0] <= 32'b00000000000000000000000000000000; + uv_line_stride[31:0] <= 32'b00000000000000000000000000000000; + mean_format <= 1'b0; + mean_gu[15:0] <= 16'b0000000000000000; + mean_ry[15:0] <= 16'b0000000000000000; + mean_ax[15:0] <= 16'b0000000000000000; + mean_bv[15:0] <= 16'b0000000000000000; + conv_mode <= 1'b0; + data_reuse <= 1'b0; + in_precision[1:0] <= 2'b01; + proc_precision[1:0] <= 2'b01; + skip_data_rls <= 1'b0; + skip_weight_rls <= 1'b0; + weight_reuse <= 1'b0; + nan_to_zero <= 1'b0; + dma_en <= 1'b0; + pixel_x_offset[4:0] <= 5'b00000; + pixel_y_offset[2:0] <= 3'b000; + rsv_per_line[9:0] <= 10'b0000000000; + rsv_per_uv_line[9:0] <= 10'b0000000000; + rsv_height[2:0] <= 3'b000; + rsv_y_index[4:0] <= 5'b00000; + surf_stride[31:0] <= 32'b00000000000000000000000000000000; + weight_addr_high[31:0] <= 32'b00000000000000000000000000000000; + weight_addr_low[31:0] <= 32'b00000000000000000000000000000000; + weight_bytes[31:0] <= 32'b00000000000000000000000000000000; + weight_format <= 1'b0; + weight_ram_type <= 1'b0; + byte_per_kernel[17:0] <= 18'b000000000000000000; + weight_kernel[12:0] <= 13'b0000000000000; + wgs_addr_high[31:0] <= 32'b00000000000000000000000000000000; + wgs_addr_low[31:0] <= 32'b00000000000000000000000000000000; + wmb_addr_high[31:0] <= 32'b00000000000000000000000000000000; + wmb_addr_low[31:0] <= 32'b00000000000000000000000000000000; + wmb_bytes[27:0] <= 28'b0000000000000000000000000000; + pad_bottom[5:0] <= 6'b000000; + pad_left[4:0] <= 5'b00000; + pad_right[5:0] <= 6'b000000; + pad_top[4:0] <= 5'b00000; + pad_value[15:0] <= 16'b0000000000000000; + end else begin +// Register: NVDLA_CDMA_D_BANK_0 Field: data_bank + if (nvdla_cdma_d_bank_0_wren) begin + data_bank[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_BANK_0 Field: weight_bank + if (nvdla_cdma_d_bank_0_wren) begin + weight_bank[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CDMA_D_BATCH_NUMBER_0 Field: batches + if (nvdla_cdma_d_batch_number_0_wren) begin + batches[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_BATCH_STRIDE_0 Field: batch_stride + if (nvdla_cdma_d_batch_stride_0_wren) begin + batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_CONV_STRIDE_0 Field: conv_x_stride + if (nvdla_cdma_d_conv_stride_0_wren) begin + conv_x_stride[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_CDMA_D_CONV_STRIDE_0 Field: conv_y_stride + if (nvdla_cdma_d_conv_stride_0_wren) begin + conv_y_stride[2:0] <= reg_wr_data[18:16]; + end +// Register: NVDLA_CDMA_D_CVT_CFG_0 Field: cvt_en + if (nvdla_cdma_d_cvt_cfg_0_wren) begin + cvt_en <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_CVT_CFG_0 Field: cvt_truncate + if (nvdla_cdma_d_cvt_cfg_0_wren) begin + cvt_truncate[5:0] <= reg_wr_data[9:4]; + end +// Register: NVDLA_CDMA_D_CVT_OFFSET_0 Field: cvt_offset + if (nvdla_cdma_d_cvt_offset_0_wren) begin + cvt_offset[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_CVT_SCALE_0 Field: cvt_scale + if (nvdla_cdma_d_cvt_scale_0_wren) begin + cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_CYA_0 Field: cya + if (nvdla_cdma_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_HIGH_0_0 Field: datain_addr_high_0 + if (nvdla_cdma_d_dain_addr_high_0_0_wren) begin + datain_addr_high_0[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_HIGH_1_0 Field: datain_addr_high_1 + if (nvdla_cdma_d_dain_addr_high_1_0_wren) begin + datain_addr_high_1[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_LOW_0_0 Field: datain_addr_low_0 + if (nvdla_cdma_d_dain_addr_low_0_0_wren) begin + datain_addr_low_0[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_ADDR_LOW_1_0 Field: datain_addr_low_1 + if (nvdla_cdma_d_dain_addr_low_1_0_wren) begin + datain_addr_low_1[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_DAIN_MAP_0 Field: line_packed + if (nvdla_cdma_d_dain_map_0_wren) begin + line_packed <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_DAIN_MAP_0 Field: surf_packed + if (nvdla_cdma_d_dain_map_0_wren) begin + surf_packed <= reg_wr_data[16]; + end +// Register: NVDLA_CDMA_D_DAIN_RAM_TYPE_0 Field: datain_ram_type + if (nvdla_cdma_d_dain_ram_type_0_wren) begin + datain_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: datain_format + if (nvdla_cdma_d_datain_format_0_wren) begin + datain_format <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: pixel_format + if (nvdla_cdma_d_datain_format_0_wren) begin + pixel_format[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: pixel_mapping + if (nvdla_cdma_d_datain_format_0_wren) begin + pixel_mapping <= reg_wr_data[16]; + end +// Register: NVDLA_CDMA_D_DATAIN_FORMAT_0 Field: pixel_sign_override + if (nvdla_cdma_d_datain_format_0_wren) begin + pixel_sign_override <= reg_wr_data[20]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_0_0 Field: datain_height + if (nvdla_cdma_d_datain_size_0_0_wren) begin + datain_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_0_0 Field: datain_width + if (nvdla_cdma_d_datain_size_0_0_wren) begin + datain_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_1_0 Field: datain_channel + if (nvdla_cdma_d_datain_size_1_0_wren) begin + datain_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_EXT_0_0 Field: datain_height_ext + if (nvdla_cdma_d_datain_size_ext_0_0_wren) begin + datain_height_ext[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CDMA_D_DATAIN_SIZE_EXT_0_0 Field: datain_width_ext + if (nvdla_cdma_d_datain_size_ext_0_0_wren) begin + datain_width_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_ENTRY_PER_SLICE_0 Field: entries + if (nvdla_cdma_d_entry_per_slice_0_wren) begin + entries[13:0] <= reg_wr_data[13:0]; + end +// Register: NVDLA_CDMA_D_FETCH_GRAIN_0 Field: grains + if (nvdla_cdma_d_fetch_grain_0_wren) begin + grains[11:0] <= reg_wr_data[11:0]; + end +// Not generating flops for read-only field NVDLA_CDMA_D_INF_INPUT_DATA_NUM_0::inf_data_num +// Not generating flops for read-only field NVDLA_CDMA_D_INF_INPUT_WEIGHT_NUM_0::inf_weight_num +// Register: NVDLA_CDMA_D_LINE_STRIDE_0 Field: line_stride + if (nvdla_cdma_d_line_stride_0_wren) begin + line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_LINE_UV_STRIDE_0 Field: uv_line_stride + if (nvdla_cdma_d_line_uv_stride_0_wren) begin + uv_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_MEAN_FORMAT_0 Field: mean_format + if (nvdla_cdma_d_mean_format_0_wren) begin + mean_format <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_0_0 Field: mean_gu + if (nvdla_cdma_d_mean_global_0_0_wren) begin + mean_gu[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_0_0 Field: mean_ry + if (nvdla_cdma_d_mean_global_0_0_wren) begin + mean_ry[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_1_0 Field: mean_ax + if (nvdla_cdma_d_mean_global_1_0_wren) begin + mean_ax[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDMA_D_MEAN_GLOBAL_1_0 Field: mean_bv + if (nvdla_cdma_d_mean_global_1_0_wren) begin + mean_bv[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: conv_mode + if (nvdla_cdma_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: data_reuse + if (nvdla_cdma_d_misc_cfg_0_wren) begin + data_reuse <= reg_wr_data[16]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: in_precision + if (nvdla_cdma_d_misc_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[9:8]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: proc_precision + if (nvdla_cdma_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: skip_data_rls + if (nvdla_cdma_d_misc_cfg_0_wren) begin + skip_data_rls <= reg_wr_data[24]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: skip_weight_rls + if (nvdla_cdma_d_misc_cfg_0_wren) begin + skip_weight_rls <= reg_wr_data[28]; + end +// Register: NVDLA_CDMA_D_MISC_CFG_0 Field: weight_reuse + if (nvdla_cdma_d_misc_cfg_0_wren) begin + weight_reuse <= reg_wr_data[20]; + end +// Register: NVDLA_CDMA_D_NAN_FLUSH_TO_ZERO_0 Field: nan_to_zero + if (nvdla_cdma_d_nan_flush_to_zero_0_wren) begin + nan_to_zero <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDMA_D_NAN_INPUT_DATA_NUM_0::nan_data_num +// Not generating flops for read-only field NVDLA_CDMA_D_NAN_INPUT_WEIGHT_NUM_0::nan_weight_num +// Not generating flops for field NVDLA_CDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_DAT_READ_LATENCY_0::dat_rd_latency +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_DAT_READ_STALL_0::dat_rd_stall +// Register: NVDLA_CDMA_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_cdma_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_WT_READ_LATENCY_0::wt_rd_latency +// Not generating flops for read-only field NVDLA_CDMA_D_PERF_WT_READ_STALL_0::wt_rd_stall +// Register: NVDLA_CDMA_D_PIXEL_OFFSET_0 Field: pixel_x_offset + if (nvdla_cdma_d_pixel_offset_0_wren) begin + pixel_x_offset[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_PIXEL_OFFSET_0 Field: pixel_y_offset + if (nvdla_cdma_d_pixel_offset_0_wren) begin + pixel_y_offset[2:0] <= reg_wr_data[18:16]; + end +// Register: NVDLA_CDMA_D_RESERVED_X_CFG_0 Field: rsv_per_line + if (nvdla_cdma_d_reserved_x_cfg_0_wren) begin + rsv_per_line[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_CDMA_D_RESERVED_X_CFG_0 Field: rsv_per_uv_line + if (nvdla_cdma_d_reserved_x_cfg_0_wren) begin + rsv_per_uv_line[9:0] <= reg_wr_data[25:16]; + end +// Register: NVDLA_CDMA_D_RESERVED_Y_CFG_0 Field: rsv_height + if (nvdla_cdma_d_reserved_y_cfg_0_wren) begin + rsv_height[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_CDMA_D_RESERVED_Y_CFG_0 Field: rsv_y_index + if (nvdla_cdma_d_reserved_y_cfg_0_wren) begin + rsv_y_index[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CDMA_D_SURF_STRIDE_0 Field: surf_stride + if (nvdla_cdma_d_surf_stride_0_wren) begin + surf_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_ADDR_HIGH_0 Field: weight_addr_high + if (nvdla_cdma_d_weight_addr_high_0_wren) begin + weight_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_ADDR_LOW_0 Field: weight_addr_low + if (nvdla_cdma_d_weight_addr_low_0_wren) begin + weight_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_BYTES_0 Field: weight_bytes + if (nvdla_cdma_d_weight_bytes_0_wren) begin + weight_bytes[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_FORMAT_0 Field: weight_format + if (nvdla_cdma_d_weight_format_0_wren) begin + weight_format <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_RAM_TYPE_0 Field: weight_ram_type + if (nvdla_cdma_d_weight_ram_type_0_wren) begin + weight_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_SIZE_0_0 Field: byte_per_kernel + if (nvdla_cdma_d_weight_size_0_0_wren) begin + byte_per_kernel[17:0] <= reg_wr_data[17:0]; + end +// Register: NVDLA_CDMA_D_WEIGHT_SIZE_1_0 Field: weight_kernel + if (nvdla_cdma_d_weight_size_1_0_wren) begin + weight_kernel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDMA_D_WGS_ADDR_HIGH_0 Field: wgs_addr_high + if (nvdla_cdma_d_wgs_addr_high_0_wren) begin + wgs_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WGS_ADDR_LOW_0 Field: wgs_addr_low + if (nvdla_cdma_d_wgs_addr_low_0_wren) begin + wgs_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WMB_ADDR_HIGH_0 Field: wmb_addr_high + if (nvdla_cdma_d_wmb_addr_high_0_wren) begin + wmb_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WMB_ADDR_LOW_0 Field: wmb_addr_low + if (nvdla_cdma_d_wmb_addr_low_0_wren) begin + wmb_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDMA_D_WMB_BYTES_0 Field: wmb_bytes + if (nvdla_cdma_d_wmb_bytes_0_wren) begin + wmb_bytes[27:0] <= reg_wr_data[27:0]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_bottom + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_bottom[5:0] <= reg_wr_data[29:24]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_left + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_left[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_right + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_right[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_0 Field: pad_top + if (nvdla_cdma_d_zero_padding_0_wren) begin + pad_top[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CDMA_D_ZERO_PADDING_VALUE_0 Field: pad_value + if (nvdla_cdma_d_zero_padding_value_0_wren) begin + pad_value[15:0] <= reg_wr_data[15:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h50bc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_BANK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_bank_0_out, nvdla_cdma_d_bank_0_out); + (32'h5058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_BATCH_NUMBER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_batch_number_0_out, nvdla_cdma_d_batch_number_0_out); + (32'h505c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_batch_stride_0_out, nvdla_cdma_d_batch_stride_0_out); + (32'h50b0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CONV_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_conv_stride_0_out, nvdla_cdma_d_conv_stride_0_out); + (32'h50a4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CVT_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cvt_cfg_0_out, nvdla_cdma_d_cvt_cfg_0_out); + (32'h50a8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CVT_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cvt_offset_0_out, nvdla_cdma_d_cvt_offset_0_out); + (32'h50ac & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CVT_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cvt_scale_0_out, nvdla_cdma_d_cvt_scale_0_out); + (32'h50e8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_cya_0_out, nvdla_cdma_d_cya_0_out); + (32'h5030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_HIGH_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_high_0_0_out, nvdla_cdma_d_dain_addr_high_0_0_out); + (32'h5038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_HIGH_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_high_1_0_out, nvdla_cdma_d_dain_addr_high_1_0_out); + (32'h5034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_LOW_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_low_0_0_out, nvdla_cdma_d_dain_addr_low_0_0_out); + (32'h503c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_ADDR_LOW_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_addr_low_1_0_out, nvdla_cdma_d_dain_addr_low_1_0_out); + (32'h504c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_MAP_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_map_0_out, nvdla_cdma_d_dain_map_0_out); + (32'h502c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DAIN_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_dain_ram_type_0_out, nvdla_cdma_d_dain_ram_type_0_out); + (32'h5018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_format_0_out, nvdla_cdma_d_datain_format_0_out); + (32'h501c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_size_0_0_out, nvdla_cdma_d_datain_size_0_0_out); + (32'h5020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_size_1_0_out, nvdla_cdma_d_datain_size_1_0_out); + (32'h5024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_DATAIN_SIZE_EXT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_datain_size_ext_0_0_out, nvdla_cdma_d_datain_size_ext_0_0_out); + (32'h5060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_ENTRY_PER_SLICE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_entry_per_slice_0_out, nvdla_cdma_d_entry_per_slice_0_out); + (32'h5064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_FETCH_GRAIN_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_fetch_grain_0_out, nvdla_cdma_d_fetch_grain_0_out); + (32'h50cc & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_INF_INPUT_DATA_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50d0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_INF_INPUT_WEIGHT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_line_stride_0_out, nvdla_cdma_d_line_stride_0_out); + (32'h5044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_LINE_UV_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_line_uv_stride_0_out, nvdla_cdma_d_line_uv_stride_0_out); + (32'h5098 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MEAN_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_mean_format_0_out, nvdla_cdma_d_mean_format_0_out); + (32'h509c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MEAN_GLOBAL_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_mean_global_0_0_out, nvdla_cdma_d_mean_global_0_0_out); + (32'h50a0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MEAN_GLOBAL_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_mean_global_1_0_out, nvdla_cdma_d_mean_global_1_0_out); + (32'h5014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_misc_cfg_0_out, nvdla_cdma_d_misc_cfg_0_out); + (32'h50c0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_NAN_FLUSH_TO_ZERO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_nan_flush_to_zero_0_out, nvdla_cdma_d_nan_flush_to_zero_0_out); + (32'h50c4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_NAN_INPUT_DATA_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50c8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_NAN_INPUT_WEIGHT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_op_enable_0_out, nvdla_cdma_d_op_enable_0_out); + (32'h50e0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_DAT_READ_LATENCY_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50d8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_DAT_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50d4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_perf_enable_0_out, nvdla_cdma_d_perf_enable_0_out); + (32'h50e4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_WT_READ_LATENCY_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h50dc & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_D_PERF_WT_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_PIXEL_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_pixel_offset_0_out, nvdla_cdma_d_pixel_offset_0_out); + (32'h5050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_RESERVED_X_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_reserved_x_cfg_0_out, nvdla_cdma_d_reserved_x_cfg_0_out); + (32'h5054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_RESERVED_Y_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_reserved_y_cfg_0_out, nvdla_cdma_d_reserved_y_cfg_0_out); + (32'h5048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_surf_stride_0_out, nvdla_cdma_d_surf_stride_0_out); + (32'h5078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_addr_high_0_out, nvdla_cdma_d_weight_addr_high_0_out); + (32'h507c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_addr_low_0_out, nvdla_cdma_d_weight_addr_low_0_out); + (32'h5080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_bytes_0_out, nvdla_cdma_d_weight_bytes_0_out); + (32'h5068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_format_0_out, nvdla_cdma_d_weight_format_0_out); + (32'h5074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_ram_type_0_out, nvdla_cdma_d_weight_ram_type_0_out); + (32'h506c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_size_0_0_out, nvdla_cdma_d_weight_size_0_0_out); + (32'h5070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WEIGHT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_weight_size_1_0_out, nvdla_cdma_d_weight_size_1_0_out); + (32'h5084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WGS_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wgs_addr_high_0_out, nvdla_cdma_d_wgs_addr_high_0_out); + (32'h5088 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WGS_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wgs_addr_low_0_out, nvdla_cdma_d_wgs_addr_low_0_out); + (32'h508c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WMB_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wmb_addr_high_0_out, nvdla_cdma_d_wmb_addr_high_0_out); + (32'h5090 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WMB_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wmb_addr_low_0_out, nvdla_cdma_d_wmb_addr_low_0_out); + (32'h5094 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_WMB_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_wmb_bytes_0_out, nvdla_cdma_d_wmb_bytes_0_out); + (32'h50b4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_ZERO_PADDING_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_zero_padding_0_out, nvdla_cdma_d_zero_padding_0_out); + (32'h50b8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_D_ZERO_PADDING_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_d_zero_padding_value_0_out, nvdla_cdma_d_zero_padding_value_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDMA_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v new file mode 100644 index 0000000..838ecea --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v @@ -0,0 +1,574 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_img.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_img ( + img_dat2mcif_rd_req_ready //|< i + ,mcif2img_dat_rd_rsp_pd //|< i + ,mcif2img_dat_rd_rsp_valid //|< i + ,img_dat2mcif_rd_req_pd //|> o + ,img_dat2mcif_rd_req_valid //|> o + ,mcif2img_dat_rd_rsp_ready //|> o + ,nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_data_reuse //|< i + ,reg2dp_datain_addr_high_0 //|< i + ,reg2dp_datain_addr_high_1 //|< i + ,reg2dp_datain_addr_low_0 //|< i + ,reg2dp_datain_addr_low_1 //|< i + ,reg2dp_datain_channel //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_datain_height //|< i + ,reg2dp_datain_ram_type //|< i + ,reg2dp_datain_width //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_entries //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_line_stride //|< i + ,reg2dp_mean_ax //|< i + ,reg2dp_mean_bv //|< i + ,reg2dp_mean_format //|< i + ,reg2dp_mean_gu //|< i + ,reg2dp_mean_ry //|< i + ,reg2dp_op_en //|< i + ,reg2dp_pad_left //|< i + ,reg2dp_pad_right //|< i + ,reg2dp_pixel_format //|< i + ,reg2dp_pixel_mapping //|< i + ,reg2dp_pixel_sign_override //|< i + ,reg2dp_pixel_x_offset //|< i + ,reg2dp_pixel_y_offset //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_rsv_height //|< i * + ,reg2dp_rsv_per_line //|< i * + ,reg2dp_rsv_per_uv_line //|< i * + ,reg2dp_rsv_y_index //|< i * + ,reg2dp_skip_data_rls //|< i + ,reg2dp_uv_line_stride //|< i + ,sc2cdma_dat_pending_req //|< i + ,status2dma_free_entries //|< i + ,status2dma_fsm_switch //|< i + ,status2dma_valid_slices //|< i * + ,status2dma_wr_idx //|< i + ,dp2reg_img_rd_latency //|> o + ,dp2reg_img_rd_stall //|> o +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_sel +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,img2cvt_dat_wr_addr${i} +//: ,img2cvt_dat_wr_data${i} +//: ,img2cvt_mn_wr_data${i} +//: ,img2cvt_dat_wr_pad_mask${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,img2cvt_dat_wr_addr +,img2cvt_dat_wr_data +,img2cvt_mn_wr_data +,img2cvt_dat_wr_pad_mask + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,img2cvt_dat_wr_en //|> o + ,img2cvt_dat_wr_info_pd //|> o +//,img2cvt_dat_wr_pad_mask //|> o +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,img2sbuf_p${i}_wr_en +//: ,img2sbuf_p${i}_wr_addr +//: ,img2sbuf_p${i}_wr_data +//: ,img2sbuf_p${i}_rd_en +//: ,img2sbuf_p${i}_rd_addr +//: ,img2sbuf_p${i}_rd_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,img2sbuf_p0_wr_en +,img2sbuf_p0_wr_addr +,img2sbuf_p0_wr_data +,img2sbuf_p0_rd_en +,img2sbuf_p0_rd_addr +,img2sbuf_p0_rd_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,img2status_dat_entries //|> o + ,img2status_dat_slices //|> o + ,img2status_dat_updt //|> o + ,img2status_state //|> o + ,slcg_img_gate_dc //|> o + ,slcg_img_gate_wg //|> o + ); +/////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output img_dat2mcif_rd_req_valid; +input img_dat2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +input mcif2img_dat_rd_rsp_valid; +output mcif2img_dat_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +output img2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_sel ; +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr${i}; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] img2cvt_dat_wr_addr; +output [64-1:0] img2cvt_dat_wr_data; +output [8*16-1:0] img2cvt_mn_wr_data; +output [8-1:0] img2cvt_dat_wr_pad_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [11:0] img2cvt_dat_wr_info_pd; +////: my $ele_num=NVDLA_CDMA_DMAIF_BW/NVDLA_CDMA_BPE; +////: print qq( output [${ele_num}-1:0] img2cvt_dat_wr_pad_mask; ); +output [1:0] img2status_state; +output img2status_dat_updt; +output [14:0] img2status_dat_entries; +output [13:0] img2status_dat_slices; +input [13:0] status2dma_valid_slices; +input [14:0] status2dma_free_entries; +input [14:0] status2dma_wr_idx; +input status2dma_fsm_switch; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: output img2sbuf_p${i}_wr_en ; +//: output [7:0] img2sbuf_p${i}_wr_addr; +//: output [${atmm}-1:0] img2sbuf_p${i}_wr_data; +//: output img2sbuf_p${i}_rd_en; +//: output [7:0] img2sbuf_p${i}_rd_addr; +//: input [${atmm}-1:0] img2sbuf_p${i}_rd_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output img2sbuf_p0_wr_en ; +output [7:0] img2sbuf_p0_wr_addr; +output [64-1:0] img2sbuf_p0_wr_data; +output img2sbuf_p0_rd_en; +output [7:0] img2sbuf_p0_rd_addr; +input [64-1:0] img2sbuf_p0_rd_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input sc2cdma_dat_pending_req; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [0:0] reg2dp_datain_format; +input [5:0] reg2dp_pixel_format; +input [0:0] reg2dp_pixel_mapping; +input [0:0] reg2dp_pixel_sign_override; +input [12:0] reg2dp_datain_width; +input [12:0] reg2dp_datain_height; +input [12:0] reg2dp_datain_channel; +input [4:0] reg2dp_pixel_x_offset; +input [2:0] reg2dp_pixel_y_offset; +input [0:0] reg2dp_datain_ram_type; +input [31:0] reg2dp_datain_addr_high_0; +input [31:0] reg2dp_datain_addr_low_0; +input [31:0] reg2dp_datain_addr_low_1; +input [31:0] reg2dp_line_stride; +input [31:0] reg2dp_uv_line_stride; +input [31:0] reg2dp_datain_addr_high_1; +input [0:0] reg2dp_mean_format; +input [15:0] reg2dp_mean_ry; +input [15:0] reg2dp_mean_gu; +input [15:0] reg2dp_mean_bv; +input [15:0] reg2dp_mean_ax; +input [13:0] reg2dp_entries; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +//input [NVDLA_CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SIZE-1:0] reg2dp_pad_value; +input [4:0] reg2dp_data_bank; +input [0:0] reg2dp_dma_en; +input [9:0] reg2dp_rsv_per_line; +input [9:0] reg2dp_rsv_per_uv_line; +input [2:0] reg2dp_rsv_height; +input [4:0] reg2dp_rsv_y_index; +output slcg_img_gate_dc; +output slcg_img_gate_wg; +output [31:0] dp2reg_img_rd_stall; +output [31:0] dp2reg_img_rd_latency; +///////////////////////////////////////////////////////////////////////////////////////// +wire is_running; +wire layer_st; +wire pack_is_done; +wire [5:0] pixel_bank; +wire pixel_data_expand; +wire pixel_data_shrink; +wire pixel_early_end; +wire [10:0] pixel_order; +wire pixel_packed_10b; +wire pixel_planar; +wire [3:0] pixel_planar0_bundle_limit; +wire [3:0] pixel_planar0_bundle_limit_1st; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: wire [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: wire [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [3-1:0] pixel_planar0_byte_sft; +wire [3-1:0] pixel_planar1_byte_sft; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [3:0] pixel_planar0_lp_burst; +wire pixel_planar0_lp_vld; +wire [3:0] pixel_planar0_rp_burst; +wire pixel_planar0_rp_vld; +wire [2:0] pixel_planar0_sft; +wire [13:0] pixel_planar0_width_burst; +wire [4:0] pixel_planar1_bundle_limit; +wire [4:0] pixel_planar1_bundle_limit_1st; +wire [2:0] pixel_planar1_lp_burst; +wire pixel_planar1_lp_vld; +wire [2:0] pixel_planar1_rp_burst; +wire pixel_planar1_rp_vld; +wire [2:0] pixel_planar1_sft; +wire [13:0] pixel_planar1_width_burst; +wire [1:0] pixel_precision; +wire pixel_uint; +wire [14:0] sg2pack_data_entries; +wire [14:0] sg2pack_entry_end; +wire [14:0] sg2pack_entry_mid; +wire [14:0] sg2pack_entry_st; +wire [12:0] sg2pack_height_total; +wire [10:0] sg2pack_img_pd; +wire sg2pack_img_prdy; +wire sg2pack_img_pvld; +wire sg2pack_mn_enable; +wire [3:0] sg2pack_sub_h_end; +wire [3:0] sg2pack_sub_h_mid; +wire [3:0] sg2pack_sub_h_st; +wire sg_is_done; +///////////////////////////////////////////////////////////////////////////////////////// +NV_NVDLA_CDMA_IMG_ctrl u_ctrl ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_ng_clk (nvdla_core_ng_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pack_is_done (pack_is_done) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.sg_is_done (sg_is_done) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.img2status_state (img2status_state[1:0]) + ,.is_running (is_running) + ,.layer_st (layer_st) + ,.pixel_bank (pixel_bank) + ,.pixel_data_expand (pixel_data_expand) + ,.pixel_data_shrink (pixel_data_shrink) + ,.pixel_early_end (pixel_early_end) + ,.pixel_order (pixel_order) + ,.pixel_packed_10b (pixel_packed_10b) + ,.pixel_planar (pixel_planar) + ,.pixel_planar0_bundle_limit (pixel_planar0_bundle_limit) + ,.pixel_planar0_bundle_limit_1st (pixel_planar0_bundle_limit_1st) + ,.pixel_planar0_byte_sft (pixel_planar0_byte_sft) + ,.pixel_planar0_lp_burst (pixel_planar0_lp_burst) + ,.pixel_planar0_lp_vld (pixel_planar0_lp_vld) + ,.pixel_planar0_rp_burst (pixel_planar0_rp_burst) + ,.pixel_planar0_rp_vld (pixel_planar0_rp_vld) + ,.pixel_planar0_sft (pixel_planar0_sft) + ,.pixel_planar0_width_burst (pixel_planar0_width_burst) + ,.pixel_planar1_bundle_limit (pixel_planar1_bundle_limit) + ,.pixel_planar1_bundle_limit_1st (pixel_planar1_bundle_limit_1st) + ,.pixel_planar1_byte_sft (pixel_planar1_byte_sft) + ,.pixel_planar1_lp_burst (pixel_planar1_lp_burst) + ,.pixel_planar1_lp_vld (pixel_planar1_lp_vld) + ,.pixel_planar1_rp_burst (pixel_planar1_rp_burst) + ,.pixel_planar1_rp_vld (pixel_planar1_rp_vld) + ,.pixel_planar1_sft (pixel_planar1_sft) + ,.pixel_planar1_width_burst (pixel_planar1_width_burst) + ,.pixel_precision (pixel_precision) + ,.pixel_uint (pixel_uint) + ,.slcg_img_gate_dc (slcg_img_gate_dc) + ,.slcg_img_gate_wg (slcg_img_gate_wg) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_datain_format (reg2dp_datain_format[0]) + ,.reg2dp_pixel_format (reg2dp_pixel_format[5:0]) + ,.reg2dp_pixel_mapping (reg2dp_pixel_mapping[0]) + ,.reg2dp_pixel_sign_override (reg2dp_pixel_sign_override[0]) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_pixel_x_offset (reg2dp_pixel_x_offset[4:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) + ); +NV_NVDLA_CDMA_IMG_sg u_sg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.img2status_dat_entries (img2status_dat_entries) + ,.img2status_dat_updt (img2status_dat_updt) + ,.is_running (is_running) + ,.layer_st (layer_st) + ,.img_dat2mcif_rd_req_pd (img_dat2mcif_rd_req_pd) + ,.img_dat2mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.img_dat2mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.mcif2img_dat_rd_rsp_pd (mcif2img_dat_rd_rsp_pd) + ,.mcif2img_dat_rd_rsp_valid (mcif2img_dat_rd_rsp_valid) + ,.mcif2img_dat_rd_rsp_ready (mcif2img_dat_rd_rsp_ready) + ,.pixel_order (pixel_order[10:0]) + ,.pixel_planar (pixel_planar) + ,.pixel_planar0_bundle_limit (pixel_planar0_bundle_limit[3:0]) + ,.pixel_planar0_bundle_limit_1st (pixel_planar0_bundle_limit_1st[3:0]) + ,.pixel_planar0_byte_sft (pixel_planar0_byte_sft) + ,.pixel_planar0_lp_burst (pixel_planar0_lp_burst[3:0]) + ,.pixel_planar0_lp_vld (pixel_planar0_lp_vld) + ,.pixel_planar0_rp_burst (pixel_planar0_rp_burst[3:0]) + ,.pixel_planar0_rp_vld (pixel_planar0_rp_vld) + ,.pixel_planar0_width_burst (pixel_planar0_width_burst ) + ,.pixel_planar1_bundle_limit (pixel_planar1_bundle_limit[4:0]) + ,.pixel_planar1_bundle_limit_1st (pixel_planar1_bundle_limit_1st[4:0]) + ,.pixel_planar1_byte_sft (pixel_planar1_byte_sft) + ,.pixel_planar1_lp_burst (pixel_planar1_lp_burst[2:0]) + ,.pixel_planar1_lp_vld (pixel_planar1_lp_vld) + ,.pixel_planar1_rp_burst (pixel_planar1_rp_burst[2:0]) + ,.pixel_planar1_rp_vld (pixel_planar1_rp_vld) + ,.pixel_planar1_width_burst (pixel_planar1_width_burst) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.sg2pack_img_prdy (sg2pack_img_prdy) + ,.status2dma_free_entries (status2dma_free_entries) + ,.status2dma_fsm_switch (status2dma_fsm_switch) +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,.img2sbuf_p${i}_wr_addr (img2sbuf_p${i}_wr_addr) +//: ,.img2sbuf_p${i}_wr_data (img2sbuf_p${i}_wr_data) +//: ,.img2sbuf_p${i}_wr_en (img2sbuf_p${i}_wr_en) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2sbuf_p0_wr_addr (img2sbuf_p0_wr_addr) +,.img2sbuf_p0_wr_data (img2sbuf_p0_wr_data) +,.img2sbuf_p0_wr_en (img2sbuf_p0_wr_en) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sg2pack_data_entries (sg2pack_data_entries) + ,.sg2pack_entry_end (sg2pack_entry_end) + ,.sg2pack_entry_mid (sg2pack_entry_mid) + ,.sg2pack_entry_st (sg2pack_entry_st) + ,.sg2pack_height_total (sg2pack_height_total[12:0]) + ,.sg2pack_img_pd (sg2pack_img_pd[10:0]) + ,.sg2pack_img_pvld (sg2pack_img_pvld) + ,.sg2pack_mn_enable (sg2pack_mn_enable) + ,.sg2pack_sub_h_end (sg2pack_sub_h_end[3:0]) + ,.sg2pack_sub_h_mid (sg2pack_sub_h_mid[3:0]) + ,.sg2pack_sub_h_st (sg2pack_sub_h_st[3:0]) + ,.sg_is_done (sg_is_done) + ,.reg2dp_pixel_y_offset (reg2dp_pixel_y_offset[2:0]) + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type[0]) + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) + ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0) + ,.reg2dp_datain_addr_high_1 (reg2dp_datain_addr_high_1[31:0]) + ,.reg2dp_datain_addr_low_1 (reg2dp_datain_addr_low_1) + ,.reg2dp_line_stride (reg2dp_line_stride) + ,.reg2dp_uv_line_stride (reg2dp_uv_line_stride) + ,.reg2dp_mean_format (reg2dp_mean_format[0]) + ,.reg2dp_entries (reg2dp_entries[13:0]) + ,.reg2dp_dma_en (reg2dp_dma_en[0]) + ,.dp2reg_img_rd_stall (dp2reg_img_rd_stall[31:0]) + ,.dp2reg_img_rd_latency (dp2reg_img_rd_latency[31:0]) + ); +NV_NVDLA_CDMA_IMG_pack u_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,.img2sbuf_p${i}_rd_data (img2sbuf_p${i}_rd_data) +//: ,.img2sbuf_p${i}_rd_addr (img2sbuf_p${i}_rd_addr) +//: ,.img2sbuf_p${i}_rd_en (img2sbuf_p${i}_rd_en) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2sbuf_p0_rd_data (img2sbuf_p0_rd_data) +,.img2sbuf_p0_rd_addr (img2sbuf_p0_rd_addr) +,.img2sbuf_p0_rd_en (img2sbuf_p0_rd_en) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.is_running (is_running) + ,.layer_st (layer_st) + ,.pixel_bank (pixel_bank) + ,.pixel_data_expand (pixel_data_expand) + ,.pixel_data_shrink (pixel_data_shrink) + ,.pixel_early_end (pixel_early_end) + ,.pixel_packed_10b (pixel_packed_10b) + ,.pixel_planar (pixel_planar) + ,.pixel_planar0_sft (pixel_planar0_sft[2:0]) + ,.pixel_planar1_sft (pixel_planar1_sft[2:0]) + ,.pixel_precision (pixel_precision[1:0]) + ,.pixel_uint (pixel_uint) + ,.sg2pack_data_entries (sg2pack_data_entries) + ,.sg2pack_entry_end (sg2pack_entry_end) + ,.sg2pack_entry_mid (sg2pack_entry_mid) + ,.sg2pack_entry_st (sg2pack_entry_st) + ,.sg2pack_height_total (sg2pack_height_total[12:0]) + ,.sg2pack_img_pd (sg2pack_img_pd[10:0]) + ,.sg2pack_img_pvld (sg2pack_img_pvld) + ,.sg2pack_mn_enable (sg2pack_mn_enable) + ,.sg2pack_sub_h_end (sg2pack_sub_h_end[3:0]) + ,.sg2pack_sub_h_mid (sg2pack_sub_h_mid[3:0]) + ,.sg2pack_sub_h_st (sg2pack_sub_h_st[3:0]) + ,.status2dma_wr_idx (status2dma_wr_idx[14:0]) +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_sel (img2cvt_dat_wr_sel ) +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_mask (img2cvt_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.img2cvt_dat_wr_addr${i} (img2cvt_dat_wr_addr${i} ) +//: ,.img2cvt_dat_wr_data${i} (img2cvt_dat_wr_data${i} ) +//: ,.img2cvt_mn_wr_data${i} (img2cvt_mn_wr_data${i} ) +//: ,.img2cvt_dat_wr_pad_mask${i} (img2cvt_dat_wr_pad_mask${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr[11:0]) +//,.img2cvt_dat_wr_data (img2cvt_dat_wr_data) + ,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) +//,.img2cvt_dat_wr_hsel (img2cvt_dat_wr_sel) + ,.img2cvt_dat_wr_info_pd (img2cvt_dat_wr_info_pd[11:0]) +//,.img2cvt_mn_wr_data (img2cvt_mn_wr_data) + ,.img2status_dat_entries (img2status_dat_entries) + ,.img2status_dat_slices (img2status_dat_slices) + ,.img2status_dat_updt (img2status_dat_updt) + ,.pack_is_done (pack_is_done) + ,.sg2pack_img_prdy (sg2pack_img_prdy) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) + ,.reg2dp_mean_ry (reg2dp_mean_ry[15:0]) + ,.reg2dp_mean_gu (reg2dp_mean_gu[15:0]) + ,.reg2dp_mean_bv (reg2dp_mean_bv[15:0]) + ,.reg2dp_mean_ax (reg2dp_mean_ax[15:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) +//,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask) + ); +endmodule // NV_NVDLA_CDMA_img diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v.vcp new file mode 100644 index 0000000..868eefc --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v.vcp @@ -0,0 +1,510 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_img.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_img ( + img_dat2mcif_rd_req_ready //|< i + ,mcif2img_dat_rd_rsp_pd //|< i + ,mcif2img_dat_rd_rsp_valid //|< i + ,img_dat2mcif_rd_req_pd //|> o + ,img_dat2mcif_rd_req_valid //|> o + ,mcif2img_dat_rd_rsp_ready //|> o + ,nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_data_reuse //|< i + ,reg2dp_datain_addr_high_0 //|< i + ,reg2dp_datain_addr_high_1 //|< i + ,reg2dp_datain_addr_low_0 //|< i + ,reg2dp_datain_addr_low_1 //|< i + ,reg2dp_datain_channel //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_datain_height //|< i + ,reg2dp_datain_ram_type //|< i + ,reg2dp_datain_width //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_entries //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_line_stride //|< i + ,reg2dp_mean_ax //|< i + ,reg2dp_mean_bv //|< i + ,reg2dp_mean_format //|< i + ,reg2dp_mean_gu //|< i + ,reg2dp_mean_ry //|< i + ,reg2dp_op_en //|< i + ,reg2dp_pad_left //|< i + ,reg2dp_pad_right //|< i + ,reg2dp_pixel_format //|< i + ,reg2dp_pixel_mapping //|< i + ,reg2dp_pixel_sign_override //|< i + ,reg2dp_pixel_x_offset //|< i + ,reg2dp_pixel_y_offset //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_rsv_height //|< i * + ,reg2dp_rsv_per_line //|< i * + ,reg2dp_rsv_per_uv_line //|< i * + ,reg2dp_rsv_y_index //|< i * + ,reg2dp_skip_data_rls //|< i + ,reg2dp_uv_line_stride //|< i + ,sc2cdma_dat_pending_req //|< i + ,status2dma_free_entries //|< i + ,status2dma_fsm_switch //|< i + ,status2dma_valid_slices //|< i * + ,status2dma_wr_idx //|< i + ,dp2reg_img_rd_latency //|> o + ,dp2reg_img_rd_stall //|> o +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_sel +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,img2cvt_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,img2cvt_dat_wr_addr${i} +//: ,img2cvt_dat_wr_data${i} +//: ,img2cvt_mn_wr_data${i} +//: ,img2cvt_dat_wr_pad_mask${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,img2cvt_dat_wr_addr +//: ,img2cvt_dat_wr_data +//: ,img2cvt_mn_wr_data +//: ,img2cvt_dat_wr_pad_mask +//: ); +//: } + ,img2cvt_dat_wr_en //|> o + ,img2cvt_dat_wr_info_pd //|> o +//,img2cvt_dat_wr_pad_mask //|> o +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,img2sbuf_p${i}_wr_en +//: ,img2sbuf_p${i}_wr_addr +//: ,img2sbuf_p${i}_wr_data +//: ,img2sbuf_p${i}_rd_en +//: ,img2sbuf_p${i}_rd_addr +//: ,img2sbuf_p${i}_rd_data +//: ); +//: } + ,img2status_dat_entries //|> o + ,img2status_dat_slices //|> o + ,img2status_dat_updt //|> o + ,img2status_state //|> o + ,slcg_img_gate_dc //|> o + ,slcg_img_gate_wg //|> o + ); +/////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output img_dat2mcif_rd_req_valid; +input img_dat2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +input mcif2img_dat_rd_rsp_valid; +output mcif2img_dat_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +output img2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_sel ; +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr${i}; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] img2cvt_dat_wr_addr; +//: output [${dmaif}-1:0] img2cvt_dat_wr_data; +//: output [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: output [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +output [11:0] img2cvt_dat_wr_info_pd; +////: my $ele_num=NVDLA_CDMA_DMAIF_BW/NVDLA_CDMA_BPE; +////: print qq( output [${ele_num}-1:0] img2cvt_dat_wr_pad_mask; ); +output [1:0] img2status_state; +output img2status_dat_updt; +output [14:0] img2status_dat_entries; +output [13:0] img2status_dat_slices; +input [13:0] status2dma_valid_slices; +input [14:0] status2dma_free_entries; +input [14:0] status2dma_wr_idx; +input status2dma_fsm_switch; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: output img2sbuf_p${i}_wr_en ; +//: output [7:0] img2sbuf_p${i}_wr_addr; +//: output [${atmm}-1:0] img2sbuf_p${i}_wr_data; +//: output img2sbuf_p${i}_rd_en; +//: output [7:0] img2sbuf_p${i}_rd_addr; +//: input [${atmm}-1:0] img2sbuf_p${i}_rd_data; +//: ); +//: } +input sc2cdma_dat_pending_req; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [0:0] reg2dp_datain_format; +input [5:0] reg2dp_pixel_format; +input [0:0] reg2dp_pixel_mapping; +input [0:0] reg2dp_pixel_sign_override; +input [12:0] reg2dp_datain_width; +input [12:0] reg2dp_datain_height; +input [12:0] reg2dp_datain_channel; +input [4:0] reg2dp_pixel_x_offset; +input [2:0] reg2dp_pixel_y_offset; +input [0:0] reg2dp_datain_ram_type; +input [31:0] reg2dp_datain_addr_high_0; +input [31:0] reg2dp_datain_addr_low_0; +input [31:0] reg2dp_datain_addr_low_1; +input [31:0] reg2dp_line_stride; +input [31:0] reg2dp_uv_line_stride; +input [31:0] reg2dp_datain_addr_high_1; +input [0:0] reg2dp_mean_format; +input [15:0] reg2dp_mean_ry; +input [15:0] reg2dp_mean_gu; +input [15:0] reg2dp_mean_bv; +input [15:0] reg2dp_mean_ax; +input [13:0] reg2dp_entries; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +//input [NVDLA_CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SIZE-1:0] reg2dp_pad_value; +input [4:0] reg2dp_data_bank; +input [0:0] reg2dp_dma_en; +input [9:0] reg2dp_rsv_per_line; +input [9:0] reg2dp_rsv_per_uv_line; +input [2:0] reg2dp_rsv_height; +input [4:0] reg2dp_rsv_y_index; +output slcg_img_gate_dc; +output slcg_img_gate_wg; +output [31:0] dp2reg_img_rd_stall; +output [31:0] dp2reg_img_rd_latency; +///////////////////////////////////////////////////////////////////////////////////////// +wire is_running; +wire layer_st; +wire pack_is_done; +wire [5:0] pixel_bank; +wire pixel_data_expand; +wire pixel_data_shrink; +wire pixel_early_end; +wire [10:0] pixel_order; +wire pixel_packed_10b; +wire pixel_planar; +wire [3:0] pixel_planar0_bundle_limit; +wire [3:0] pixel_planar0_bundle_limit_1st; +//: my $atmmbw = int( log(8) / log(2) ); +//: print qq( +//: wire [${atmmbw}-1:0] pixel_planar0_byte_sft; +//: wire [${atmmbw}-1:0] pixel_planar1_byte_sft; +//: ); +wire [3:0] pixel_planar0_lp_burst; +wire pixel_planar0_lp_vld; +wire [3:0] pixel_planar0_rp_burst; +wire pixel_planar0_rp_vld; +wire [2:0] pixel_planar0_sft; +wire [13:0] pixel_planar0_width_burst; +wire [4:0] pixel_planar1_bundle_limit; +wire [4:0] pixel_planar1_bundle_limit_1st; +wire [2:0] pixel_planar1_lp_burst; +wire pixel_planar1_lp_vld; +wire [2:0] pixel_planar1_rp_burst; +wire pixel_planar1_rp_vld; +wire [2:0] pixel_planar1_sft; +wire [13:0] pixel_planar1_width_burst; +wire [1:0] pixel_precision; +wire pixel_uint; +wire [14:0] sg2pack_data_entries; +wire [14:0] sg2pack_entry_end; +wire [14:0] sg2pack_entry_mid; +wire [14:0] sg2pack_entry_st; +wire [12:0] sg2pack_height_total; +wire [10:0] sg2pack_img_pd; +wire sg2pack_img_prdy; +wire sg2pack_img_pvld; +wire sg2pack_mn_enable; +wire [3:0] sg2pack_sub_h_end; +wire [3:0] sg2pack_sub_h_mid; +wire [3:0] sg2pack_sub_h_st; +wire sg_is_done; +///////////////////////////////////////////////////////////////////////////////////////// +NV_NVDLA_CDMA_IMG_ctrl u_ctrl ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_ng_clk (nvdla_core_ng_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pack_is_done (pack_is_done) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.sg_is_done (sg_is_done) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.img2status_state (img2status_state[1:0]) + ,.is_running (is_running) + ,.layer_st (layer_st) + ,.pixel_bank (pixel_bank) + ,.pixel_data_expand (pixel_data_expand) + ,.pixel_data_shrink (pixel_data_shrink) + ,.pixel_early_end (pixel_early_end) + ,.pixel_order (pixel_order) + ,.pixel_packed_10b (pixel_packed_10b) + ,.pixel_planar (pixel_planar) + ,.pixel_planar0_bundle_limit (pixel_planar0_bundle_limit) + ,.pixel_planar0_bundle_limit_1st (pixel_planar0_bundle_limit_1st) + ,.pixel_planar0_byte_sft (pixel_planar0_byte_sft) + ,.pixel_planar0_lp_burst (pixel_planar0_lp_burst) + ,.pixel_planar0_lp_vld (pixel_planar0_lp_vld) + ,.pixel_planar0_rp_burst (pixel_planar0_rp_burst) + ,.pixel_planar0_rp_vld (pixel_planar0_rp_vld) + ,.pixel_planar0_sft (pixel_planar0_sft) + ,.pixel_planar0_width_burst (pixel_planar0_width_burst) + ,.pixel_planar1_bundle_limit (pixel_planar1_bundle_limit) + ,.pixel_planar1_bundle_limit_1st (pixel_planar1_bundle_limit_1st) + ,.pixel_planar1_byte_sft (pixel_planar1_byte_sft) + ,.pixel_planar1_lp_burst (pixel_planar1_lp_burst) + ,.pixel_planar1_lp_vld (pixel_planar1_lp_vld) + ,.pixel_planar1_rp_burst (pixel_planar1_rp_burst) + ,.pixel_planar1_rp_vld (pixel_planar1_rp_vld) + ,.pixel_planar1_sft (pixel_planar1_sft) + ,.pixel_planar1_width_burst (pixel_planar1_width_burst) + ,.pixel_precision (pixel_precision) + ,.pixel_uint (pixel_uint) + ,.slcg_img_gate_dc (slcg_img_gate_dc) + ,.slcg_img_gate_wg (slcg_img_gate_wg) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_datain_format (reg2dp_datain_format[0]) + ,.reg2dp_pixel_format (reg2dp_pixel_format[5:0]) + ,.reg2dp_pixel_mapping (reg2dp_pixel_mapping[0]) + ,.reg2dp_pixel_sign_override (reg2dp_pixel_sign_override[0]) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_pixel_x_offset (reg2dp_pixel_x_offset[4:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) + ); +NV_NVDLA_CDMA_IMG_sg u_sg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.img2status_dat_entries (img2status_dat_entries) + ,.img2status_dat_updt (img2status_dat_updt) + ,.is_running (is_running) + ,.layer_st (layer_st) + ,.img_dat2mcif_rd_req_pd (img_dat2mcif_rd_req_pd) + ,.img_dat2mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.img_dat2mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.mcif2img_dat_rd_rsp_pd (mcif2img_dat_rd_rsp_pd) + ,.mcif2img_dat_rd_rsp_valid (mcif2img_dat_rd_rsp_valid) + ,.mcif2img_dat_rd_rsp_ready (mcif2img_dat_rd_rsp_ready) + ,.pixel_order (pixel_order[10:0]) + ,.pixel_planar (pixel_planar) + ,.pixel_planar0_bundle_limit (pixel_planar0_bundle_limit[3:0]) + ,.pixel_planar0_bundle_limit_1st (pixel_planar0_bundle_limit_1st[3:0]) + ,.pixel_planar0_byte_sft (pixel_planar0_byte_sft) + ,.pixel_planar0_lp_burst (pixel_planar0_lp_burst[3:0]) + ,.pixel_planar0_lp_vld (pixel_planar0_lp_vld) + ,.pixel_planar0_rp_burst (pixel_planar0_rp_burst[3:0]) + ,.pixel_planar0_rp_vld (pixel_planar0_rp_vld) + ,.pixel_planar0_width_burst (pixel_planar0_width_burst ) + ,.pixel_planar1_bundle_limit (pixel_planar1_bundle_limit[4:0]) + ,.pixel_planar1_bundle_limit_1st (pixel_planar1_bundle_limit_1st[4:0]) + ,.pixel_planar1_byte_sft (pixel_planar1_byte_sft) + ,.pixel_planar1_lp_burst (pixel_planar1_lp_burst[2:0]) + ,.pixel_planar1_lp_vld (pixel_planar1_lp_vld) + ,.pixel_planar1_rp_burst (pixel_planar1_rp_burst[2:0]) + ,.pixel_planar1_rp_vld (pixel_planar1_rp_vld) + ,.pixel_planar1_width_burst (pixel_planar1_width_burst) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.sg2pack_img_prdy (sg2pack_img_prdy) + ,.status2dma_free_entries (status2dma_free_entries) + ,.status2dma_fsm_switch (status2dma_fsm_switch) +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,.img2sbuf_p${i}_wr_addr (img2sbuf_p${i}_wr_addr) +//: ,.img2sbuf_p${i}_wr_data (img2sbuf_p${i}_wr_data) +//: ,.img2sbuf_p${i}_wr_en (img2sbuf_p${i}_wr_en) +//: ); +//: } + ,.sg2pack_data_entries (sg2pack_data_entries) + ,.sg2pack_entry_end (sg2pack_entry_end) + ,.sg2pack_entry_mid (sg2pack_entry_mid) + ,.sg2pack_entry_st (sg2pack_entry_st) + ,.sg2pack_height_total (sg2pack_height_total[12:0]) + ,.sg2pack_img_pd (sg2pack_img_pd[10:0]) + ,.sg2pack_img_pvld (sg2pack_img_pvld) + ,.sg2pack_mn_enable (sg2pack_mn_enable) + ,.sg2pack_sub_h_end (sg2pack_sub_h_end[3:0]) + ,.sg2pack_sub_h_mid (sg2pack_sub_h_mid[3:0]) + ,.sg2pack_sub_h_st (sg2pack_sub_h_st[3:0]) + ,.sg_is_done (sg_is_done) + ,.reg2dp_pixel_y_offset (reg2dp_pixel_y_offset[2:0]) + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type[0]) + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) + ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0) + ,.reg2dp_datain_addr_high_1 (reg2dp_datain_addr_high_1[31:0]) + ,.reg2dp_datain_addr_low_1 (reg2dp_datain_addr_low_1) + ,.reg2dp_line_stride (reg2dp_line_stride) + ,.reg2dp_uv_line_stride (reg2dp_uv_line_stride) + ,.reg2dp_mean_format (reg2dp_mean_format[0]) + ,.reg2dp_entries (reg2dp_entries[13:0]) + ,.reg2dp_dma_en (reg2dp_dma_en[0]) + ,.dp2reg_img_rd_stall (dp2reg_img_rd_stall[31:0]) + ,.dp2reg_img_rd_latency (dp2reg_img_rd_latency[31:0]) + ); +NV_NVDLA_CDMA_IMG_pack u_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) +//: my $dmaif = 64; +//: my $atmm = 8*8; +//: my $atmm_num = ($dmaif / $atmm); +//: foreach my $i(0..$atmm_num -1) { +//: print qq( +//: ,.img2sbuf_p${i}_rd_data (img2sbuf_p${i}_rd_data) +//: ,.img2sbuf_p${i}_rd_addr (img2sbuf_p${i}_rd_addr) +//: ,.img2sbuf_p${i}_rd_en (img2sbuf_p${i}_rd_en) +//: ); +//: } + ,.is_running (is_running) + ,.layer_st (layer_st) + ,.pixel_bank (pixel_bank) + ,.pixel_data_expand (pixel_data_expand) + ,.pixel_data_shrink (pixel_data_shrink) + ,.pixel_early_end (pixel_early_end) + ,.pixel_packed_10b (pixel_packed_10b) + ,.pixel_planar (pixel_planar) + ,.pixel_planar0_sft (pixel_planar0_sft[2:0]) + ,.pixel_planar1_sft (pixel_planar1_sft[2:0]) + ,.pixel_precision (pixel_precision[1:0]) + ,.pixel_uint (pixel_uint) + ,.sg2pack_data_entries (sg2pack_data_entries) + ,.sg2pack_entry_end (sg2pack_entry_end) + ,.sg2pack_entry_mid (sg2pack_entry_mid) + ,.sg2pack_entry_st (sg2pack_entry_st) + ,.sg2pack_height_total (sg2pack_height_total[12:0]) + ,.sg2pack_img_pd (sg2pack_img_pd[10:0]) + ,.sg2pack_img_pvld (sg2pack_img_pvld) + ,.sg2pack_mn_enable (sg2pack_mn_enable) + ,.sg2pack_sub_h_end (sg2pack_sub_h_end[3:0]) + ,.sg2pack_sub_h_mid (sg2pack_sub_h_mid[3:0]) + ,.sg2pack_sub_h_st (sg2pack_sub_h_st[3:0]) + ,.status2dma_wr_idx (status2dma_wr_idx[14:0]) +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_sel (img2cvt_dat_wr_sel ) +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_mask (img2cvt_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.img2cvt_dat_wr_addr${i} (img2cvt_dat_wr_addr${i} ) +//: ,.img2cvt_dat_wr_data${i} (img2cvt_dat_wr_data${i} ) +//: ,.img2cvt_mn_wr_data${i} (img2cvt_mn_wr_data${i} ) +//: ,.img2cvt_dat_wr_pad_mask${i} (img2cvt_dat_wr_pad_mask${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } +//,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr[11:0]) +//,.img2cvt_dat_wr_data (img2cvt_dat_wr_data) + ,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) +//,.img2cvt_dat_wr_hsel (img2cvt_dat_wr_sel) + ,.img2cvt_dat_wr_info_pd (img2cvt_dat_wr_info_pd[11:0]) +//,.img2cvt_mn_wr_data (img2cvt_mn_wr_data) + ,.img2status_dat_entries (img2status_dat_entries) + ,.img2status_dat_slices (img2status_dat_slices) + ,.img2status_dat_updt (img2status_dat_updt) + ,.pack_is_done (pack_is_done) + ,.sg2pack_img_prdy (sg2pack_img_prdy) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) + ,.reg2dp_mean_ry (reg2dp_mean_ry[15:0]) + ,.reg2dp_mean_gu (reg2dp_mean_gu[15:0]) + ,.reg2dp_mean_bv (reg2dp_mean_bv[15:0]) + ,.reg2dp_mean_ax (reg2dp_mean_ax[15:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) +//,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask) + ); +endmodule // NV_NVDLA_CDMA_img diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v new file mode 100644 index 0000000..e5171d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v @@ -0,0 +1,2779 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cdma_req_pd //|< i + ,csb2cdma_req_pvld //|< i + ,dp2reg_dat_flush_done //|< i + ,dp2reg_dc_rd_latency //|< i + ,dp2reg_dc_rd_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_img_rd_latency //|< i + ,dp2reg_img_rd_stall //|< i + ,dp2reg_inf_data_num //|< i + ,dp2reg_inf_weight_num //|< i + ,dp2reg_nan_data_num //|< i + ,dp2reg_nan_weight_num //|< i + ,dp2reg_wg_rd_latency //|< i + ,dp2reg_wg_rd_stall //|< i + ,dp2reg_wt_flush_done //|< i + ,dp2reg_wt_rd_latency //|< i + ,dp2reg_wt_rd_stall //|< i + ,cdma2csb_resp_pd //|> o + ,cdma2csb_resp_valid //|> o + ,csb2cdma_req_prdy //|> o + ,dp2reg_consumer //|> o + ,reg2dp_arb_weight //|> o + ,reg2dp_arb_wmb //|> o + ,reg2dp_batch_stride //|> o + ,reg2dp_batches //|> o + ,reg2dp_byte_per_kernel //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_conv_x_stride //|> o + ,reg2dp_conv_y_stride //|> o + ,reg2dp_cvt_en //|> o + ,reg2dp_cvt_offset //|> o + ,reg2dp_cvt_scale //|> o + ,reg2dp_cvt_truncate //|> o + ,reg2dp_cya //|> o + ,reg2dp_data_bank //|> o + ,reg2dp_data_reuse //|> o + ,reg2dp_datain_addr_high_0 //|> o + ,reg2dp_datain_addr_high_1 //|> o + ,reg2dp_datain_addr_low_0 //|> o + ,reg2dp_datain_addr_low_1 //|> o + ,reg2dp_datain_channel //|> o + ,reg2dp_datain_format //|> o + ,reg2dp_datain_height //|> o + ,reg2dp_datain_height_ext //|> o + ,reg2dp_datain_ram_type //|> o + ,reg2dp_datain_width //|> o + ,reg2dp_datain_width_ext //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_entries //|> o + ,reg2dp_grains //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_line_packed //|> o + ,reg2dp_line_stride //|> o + ,reg2dp_mean_ax //|> o + ,reg2dp_mean_bv //|> o + ,reg2dp_mean_format //|> o + ,reg2dp_mean_gu //|> o + ,reg2dp_mean_ry //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_bottom //|> o + ,reg2dp_pad_left //|> o + ,reg2dp_pad_right //|> o + ,reg2dp_pad_top //|> o + ,reg2dp_pad_value //|> o + ,reg2dp_pixel_format //|> o + ,reg2dp_pixel_mapping //|> o + ,reg2dp_pixel_sign_override //|> o + ,reg2dp_pixel_x_offset //|> o + ,reg2dp_pixel_y_offset //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_rsv_height //|> o + ,reg2dp_rsv_per_line //|> o + ,reg2dp_rsv_per_uv_line //|> o + ,reg2dp_rsv_y_index //|> o + ,reg2dp_skip_data_rls //|> o + ,reg2dp_skip_weight_rls //|> o + ,reg2dp_surf_packed //|> o + ,reg2dp_surf_stride //|> o + ,reg2dp_uv_line_stride //|> o + ,reg2dp_weight_addr_high //|> o + ,reg2dp_weight_addr_low //|> o + ,reg2dp_weight_bank //|> o + ,reg2dp_weight_bytes //|> o + ,reg2dp_weight_format //|> o + ,reg2dp_weight_kernel //|> o + ,reg2dp_weight_ram_type //|> o + ,reg2dp_weight_reuse //|> o + ,reg2dp_wgs_addr_high //|> o + ,reg2dp_wgs_addr_low //|> o + ,reg2dp_wmb_addr_high //|> o + ,reg2dp_wmb_addr_low //|> o + ,reg2dp_wmb_bytes //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cdma_req_pd; +input csb2cdma_req_pvld; +input dp2reg_dat_flush_done; +input [31:0] dp2reg_dc_rd_latency; +input [31:0] dp2reg_dc_rd_stall; +input dp2reg_done; +input [31:0] dp2reg_img_rd_latency; +input [31:0] dp2reg_img_rd_stall; +input [31:0] dp2reg_inf_data_num; +input [31:0] dp2reg_inf_weight_num; +input [31:0] dp2reg_nan_data_num; +input [31:0] dp2reg_nan_weight_num; +input [31:0] dp2reg_wg_rd_latency; +input [31:0] dp2reg_wg_rd_stall; +input dp2reg_wt_flush_done; +input [31:0] dp2reg_wt_rd_latency; +input [31:0] dp2reg_wt_rd_stall; +output [33:0] cdma2csb_resp_pd; +output cdma2csb_resp_valid; +output csb2cdma_req_prdy; +output dp2reg_consumer; +output [3:0] reg2dp_arb_weight; +output [3:0] reg2dp_arb_wmb; +output [31:0] reg2dp_batch_stride; +output [4:0] reg2dp_batches; +output [17:0] reg2dp_byte_per_kernel; +output reg2dp_conv_mode; +output [2:0] reg2dp_conv_x_stride; +output [2:0] reg2dp_conv_y_stride; +output reg2dp_cvt_en; +output [15:0] reg2dp_cvt_offset; +output [15:0] reg2dp_cvt_scale; +output [5:0] reg2dp_cvt_truncate; +output [31:0] reg2dp_cya; +output [4:0] reg2dp_data_bank; +output reg2dp_data_reuse; +output [31:0] reg2dp_datain_addr_high_0; +output [31:0] reg2dp_datain_addr_high_1; +output [31:0] reg2dp_datain_addr_low_0; +output [31:0] reg2dp_datain_addr_low_1; +output [12:0] reg2dp_datain_channel; +output reg2dp_datain_format; +output [12:0] reg2dp_datain_height; +output [12:0] reg2dp_datain_height_ext; +output reg2dp_datain_ram_type; +output [12:0] reg2dp_datain_width; +output [12:0] reg2dp_datain_width_ext; +output reg2dp_dma_en; +output [13:0] reg2dp_entries; +output [11:0] reg2dp_grains; +output [1:0] reg2dp_in_precision; +output reg2dp_line_packed; +output [31:0] reg2dp_line_stride; +output [15:0] reg2dp_mean_ax; +output [15:0] reg2dp_mean_bv; +output reg2dp_mean_format; +output [15:0] reg2dp_mean_gu; +output [15:0] reg2dp_mean_ry; +output reg2dp_nan_to_zero; +output reg2dp_op_en; +output [5:0] reg2dp_pad_bottom; +output [4:0] reg2dp_pad_left; +output [5:0] reg2dp_pad_right; +output [4:0] reg2dp_pad_top; +output [15:0] reg2dp_pad_value; +output [5:0] reg2dp_pixel_format; +output reg2dp_pixel_mapping; +output reg2dp_pixel_sign_override; +output [4:0] reg2dp_pixel_x_offset; +output [2:0] reg2dp_pixel_y_offset; +output [1:0] reg2dp_proc_precision; +output [2:0] reg2dp_rsv_height; +output [9:0] reg2dp_rsv_per_line; +output [9:0] reg2dp_rsv_per_uv_line; +output [4:0] reg2dp_rsv_y_index; +output reg2dp_skip_data_rls; +output reg2dp_skip_weight_rls; +output reg2dp_surf_packed; +output [31:0] reg2dp_surf_stride; +output [31:0] reg2dp_uv_line_stride; +output [31:0] reg2dp_weight_addr_high; +output [31:0] reg2dp_weight_addr_low; +output [4:0] reg2dp_weight_bank; +output [31:0] reg2dp_weight_bytes; +output reg2dp_weight_format; +output [12:0] reg2dp_weight_kernel; +output reg2dp_weight_ram_type; +output reg2dp_weight_reuse; +output [31:0] reg2dp_wgs_addr_high; +output [31:0] reg2dp_wgs_addr_low; +output [31:0] reg2dp_wmb_addr_high; +output [31:0] reg2dp_wmb_addr_low; +output [27:0] reg2dp_wmb_bytes; +output [7:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [31:0] reg2dp_d0_batch_stride; +wire [4:0] reg2dp_d0_batches; +wire [17:0] reg2dp_d0_byte_per_kernel; +wire reg2dp_d0_conv_mode; +wire [2:0] reg2dp_d0_conv_x_stride; +wire [2:0] reg2dp_d0_conv_y_stride; +wire reg2dp_d0_cvt_en; +wire [15:0] reg2dp_d0_cvt_offset; +wire [15:0] reg2dp_d0_cvt_scale; +wire [5:0] reg2dp_d0_cvt_truncate; +wire [31:0] reg2dp_d0_cya; +wire [4:0] reg2dp_d0_data_bank; +wire reg2dp_d0_data_reuse; +wire [31:0] reg2dp_d0_datain_addr_high_0; +wire [31:0] reg2dp_d0_datain_addr_high_1; +wire [31:0] reg2dp_d0_datain_addr_low_0; +wire [31:0] reg2dp_d0_datain_addr_low_1; +wire [12:0] reg2dp_d0_datain_channel; +wire reg2dp_d0_datain_format; +wire [12:0] reg2dp_d0_datain_height; +wire [12:0] reg2dp_d0_datain_height_ext; +wire reg2dp_d0_datain_ram_type; +wire [12:0] reg2dp_d0_datain_width; +wire [12:0] reg2dp_d0_datain_width_ext; +wire reg2dp_d0_dma_en; +wire [13:0] reg2dp_d0_entries; +wire [11:0] reg2dp_d0_grains; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_line_packed; +wire [31:0] reg2dp_d0_line_stride; +wire [15:0] reg2dp_d0_mean_ax; +wire [15:0] reg2dp_d0_mean_bv; +wire reg2dp_d0_mean_format; +wire [15:0] reg2dp_d0_mean_gu; +wire [15:0] reg2dp_d0_mean_ry; +wire reg2dp_d0_nan_to_zero; +wire reg2dp_d0_op_en_trigger; +wire [5:0] reg2dp_d0_pad_bottom; +wire [4:0] reg2dp_d0_pad_left; +wire [5:0] reg2dp_d0_pad_right; +wire [4:0] reg2dp_d0_pad_top; +wire [15:0] reg2dp_d0_pad_value; +wire [5:0] reg2dp_d0_pixel_format; +wire reg2dp_d0_pixel_mapping; +wire reg2dp_d0_pixel_sign_override; +wire [4:0] reg2dp_d0_pixel_x_offset; +wire [2:0] reg2dp_d0_pixel_y_offset; +wire [1:0] reg2dp_d0_proc_precision; +wire [2:0] reg2dp_d0_rsv_height; +wire [9:0] reg2dp_d0_rsv_per_line; +wire [9:0] reg2dp_d0_rsv_per_uv_line; +wire [4:0] reg2dp_d0_rsv_y_index; +wire reg2dp_d0_skip_data_rls; +wire reg2dp_d0_skip_weight_rls; +wire reg2dp_d0_surf_packed; +wire [31:0] reg2dp_d0_surf_stride; +wire [31:0] reg2dp_d0_uv_line_stride; +wire [31:0] reg2dp_d0_weight_addr_high; +wire [31:0] reg2dp_d0_weight_addr_low; +wire [4:0] reg2dp_d0_weight_bank; +wire [31:0] reg2dp_d0_weight_bytes; +wire reg2dp_d0_weight_format; +wire [12:0] reg2dp_d0_weight_kernel; +wire reg2dp_d0_weight_ram_type; +wire reg2dp_d0_weight_reuse; +wire [31:0] reg2dp_d0_wgs_addr_high; +wire [31:0] reg2dp_d0_wgs_addr_low; +wire [31:0] reg2dp_d0_wmb_addr_high; +wire [31:0] reg2dp_d0_wmb_addr_low; +wire [27:0] reg2dp_d0_wmb_bytes; +wire [31:0] reg2dp_d1_batch_stride; +wire [4:0] reg2dp_d1_batches; +wire [17:0] reg2dp_d1_byte_per_kernel; +wire reg2dp_d1_conv_mode; +wire [2:0] reg2dp_d1_conv_x_stride; +wire [2:0] reg2dp_d1_conv_y_stride; +wire reg2dp_d1_cvt_en; +wire [15:0] reg2dp_d1_cvt_offset; +wire [15:0] reg2dp_d1_cvt_scale; +wire [5:0] reg2dp_d1_cvt_truncate; +wire [31:0] reg2dp_d1_cya; +wire [4:0] reg2dp_d1_data_bank; +wire reg2dp_d1_data_reuse; +wire [31:0] reg2dp_d1_datain_addr_high_0; +wire [31:0] reg2dp_d1_datain_addr_high_1; +wire [31:0] reg2dp_d1_datain_addr_low_0; +wire [31:0] reg2dp_d1_datain_addr_low_1; +wire [12:0] reg2dp_d1_datain_channel; +wire reg2dp_d1_datain_format; +wire [12:0] reg2dp_d1_datain_height; +wire [12:0] reg2dp_d1_datain_height_ext; +wire reg2dp_d1_datain_ram_type; +wire [12:0] reg2dp_d1_datain_width; +wire [12:0] reg2dp_d1_datain_width_ext; +wire reg2dp_d1_dma_en; +wire [13:0] reg2dp_d1_entries; +wire [11:0] reg2dp_d1_grains; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_line_packed; +wire [31:0] reg2dp_d1_line_stride; +wire [15:0] reg2dp_d1_mean_ax; +wire [15:0] reg2dp_d1_mean_bv; +wire reg2dp_d1_mean_format; +wire [15:0] reg2dp_d1_mean_gu; +wire [15:0] reg2dp_d1_mean_ry; +wire reg2dp_d1_nan_to_zero; +wire reg2dp_d1_op_en_trigger; +wire [5:0] reg2dp_d1_pad_bottom; +wire [4:0] reg2dp_d1_pad_left; +wire [5:0] reg2dp_d1_pad_right; +wire [4:0] reg2dp_d1_pad_top; +wire [15:0] reg2dp_d1_pad_value; +wire [5:0] reg2dp_d1_pixel_format; +wire reg2dp_d1_pixel_mapping; +wire reg2dp_d1_pixel_sign_override; +wire [4:0] reg2dp_d1_pixel_x_offset; +wire [2:0] reg2dp_d1_pixel_y_offset; +wire [1:0] reg2dp_d1_proc_precision; +wire [2:0] reg2dp_d1_rsv_height; +wire [9:0] reg2dp_d1_rsv_per_line; +wire [9:0] reg2dp_d1_rsv_per_uv_line; +wire [4:0] reg2dp_d1_rsv_y_index; +wire reg2dp_d1_skip_data_rls; +wire reg2dp_d1_skip_weight_rls; +wire reg2dp_d1_surf_packed; +wire [31:0] reg2dp_d1_surf_stride; +wire [31:0] reg2dp_d1_uv_line_stride; +wire [31:0] reg2dp_d1_weight_addr_high; +wire [31:0] reg2dp_d1_weight_addr_low; +wire [4:0] reg2dp_d1_weight_bank; +wire [31:0] reg2dp_d1_weight_bytes; +wire reg2dp_d1_weight_format; +wire [12:0] reg2dp_d1_weight_kernel; +wire reg2dp_d1_weight_ram_type; +wire reg2dp_d1_weight_reuse; +wire [31:0] reg2dp_d1_wgs_addr_high; +wire [31:0] reg2dp_d1_wgs_addr_low; +wire [31:0] reg2dp_d1_wmb_addr_high; +wire [31:0] reg2dp_d1_wmb_addr_low; +wire [27:0] reg2dp_d1_wmb_bytes; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [7:0] slcg_op_en_d0; +reg [33:0] cdma2csb_resp_pd; +reg cdma2csb_resp_valid; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_dat_rd_latency; +reg [31:0] dp2reg_d0_dat_rd_latency_w; +reg [31:0] dp2reg_d0_dat_rd_stall; +reg [31:0] dp2reg_d0_dat_rd_stall_w; +reg [31:0] dp2reg_d0_inf_data_num; +reg [31:0] dp2reg_d0_inf_data_num_w; +reg [31:0] dp2reg_d0_inf_weight_num; +reg [31:0] dp2reg_d0_inf_weight_num_w; +reg [31:0] dp2reg_d0_nan_data_num; +reg [31:0] dp2reg_d0_nan_data_num_w; +reg [31:0] dp2reg_d0_nan_weight_num; +reg [31:0] dp2reg_d0_nan_weight_num_w; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg [31:0] dp2reg_d0_wt_rd_latency; +reg [31:0] dp2reg_d0_wt_rd_latency_w; +reg [31:0] dp2reg_d0_wt_rd_stall; +reg [31:0] dp2reg_d0_wt_rd_stall_w; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_dat_rd_latency; +reg [31:0] dp2reg_d1_dat_rd_latency_w; +reg [31:0] dp2reg_d1_dat_rd_stall; +reg [31:0] dp2reg_d1_dat_rd_stall_w; +reg [31:0] dp2reg_d1_inf_data_num; +reg [31:0] dp2reg_d1_inf_data_num_w; +reg [31:0] dp2reg_d1_inf_weight_num; +reg [31:0] dp2reg_d1_inf_weight_num_w; +reg [31:0] dp2reg_d1_nan_data_num; +reg [31:0] dp2reg_d1_nan_data_num_w; +reg [31:0] dp2reg_d1_nan_weight_num; +reg [31:0] dp2reg_d1_nan_weight_num_w; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [31:0] dp2reg_d1_wt_rd_latency; +reg [31:0] dp2reg_d1_wt_rd_latency_w; +reg [31:0] dp2reg_d1_wt_rd_stall; +reg [31:0] dp2reg_d1_wt_rd_stall_w; +reg dp2reg_flush_done; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [31:0] reg2dp_batch_stride; +reg [4:0] reg2dp_batches; +reg [17:0] reg2dp_byte_per_kernel; +reg reg2dp_conv_mode; +reg [2:0] reg2dp_conv_x_stride; +reg [2:0] reg2dp_conv_y_stride; +reg reg2dp_cvt_en; +reg [15:0] reg2dp_cvt_offset; +reg [15:0] reg2dp_cvt_scale; +reg [5:0] reg2dp_cvt_truncate; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [4:0] reg2dp_data_bank; +reg reg2dp_data_reuse; +reg [31:0] reg2dp_datain_addr_high_0; +reg [31:0] reg2dp_datain_addr_high_1; +reg [31:0] reg2dp_datain_addr_low_0; +reg [31:0] reg2dp_datain_addr_low_1; +reg [12:0] reg2dp_datain_channel; +reg reg2dp_datain_format; +reg [12:0] reg2dp_datain_height; +reg [12:0] reg2dp_datain_height_ext; +reg reg2dp_datain_ram_type; +reg [12:0] reg2dp_datain_width; +reg [12:0] reg2dp_datain_width_ext; +reg reg2dp_dma_en; +reg [13:0] reg2dp_entries; +reg [11:0] reg2dp_grains; +reg [1:0] reg2dp_in_precision; +reg reg2dp_line_packed; +reg [31:0] reg2dp_line_stride; +reg [15:0] reg2dp_mean_ax; +reg [15:0] reg2dp_mean_bv; +reg reg2dp_mean_format; +reg [15:0] reg2dp_mean_gu; +reg [15:0] reg2dp_mean_ry; +reg reg2dp_nan_to_zero; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [5:0] reg2dp_pad_bottom; +reg [4:0] reg2dp_pad_left; +reg [5:0] reg2dp_pad_right; +reg [4:0] reg2dp_pad_top; +reg [15:0] reg2dp_pad_value; +reg [5:0] reg2dp_pixel_format; +reg reg2dp_pixel_mapping; +reg reg2dp_pixel_sign_override; +reg [4:0] reg2dp_pixel_x_offset; +reg [2:0] reg2dp_pixel_y_offset; +reg [1:0] reg2dp_proc_precision; +reg [2:0] reg2dp_rsv_height; +reg [9:0] reg2dp_rsv_per_line; +reg [9:0] reg2dp_rsv_per_uv_line; +reg [4:0] reg2dp_rsv_y_index; +reg reg2dp_skip_data_rls; +reg reg2dp_skip_weight_rls; +reg reg2dp_surf_packed; +reg [31:0] reg2dp_surf_stride; +reg [31:0] reg2dp_uv_line_stride; +reg [31:0] reg2dp_weight_addr_high; +reg [31:0] reg2dp_weight_addr_low; +reg [4:0] reg2dp_weight_bank; +reg [31:0] reg2dp_weight_bytes; +reg reg2dp_weight_format; +reg [12:0] reg2dp_weight_kernel; +reg reg2dp_weight_ram_type; +reg reg2dp_weight_reuse; +reg [31:0] reg2dp_wgs_addr_high; +reg [31:0] reg2dp_wgs_addr_low; +reg [31:0] reg2dp_wmb_addr_high; +reg [31:0] reg2dp_wmb_addr_low; +reg [27:0] reg2dp_wmb_bytes; +reg [62:0] req_pd; +reg req_pvld; +reg [7:0] slcg_op_en_d1; +reg [7:0] slcg_op_en_d2; +reg [7:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CDMA_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb_weight (reg2dp_arb_weight[3:0]) //|> o + ,.arb_wmb (reg2dp_arb_wmb[3:0]) //|> o + ,.producer (reg2dp_producer) //|> w + ,.flush_done (dp2reg_flush_done) //|< r + ,.consumer (dp2reg_consumer) //|< o + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CDMA_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_bank (reg2dp_d0_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d0_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d0_batches[4:0]) //|> w + ,.batch_stride (reg2dp_d0_batch_stride[31:0]) //|> w + ,.conv_x_stride (reg2dp_d0_conv_x_stride[2:0]) //|> w + ,.conv_y_stride (reg2dp_d0_conv_y_stride[2:0]) //|> w + ,.cvt_en (reg2dp_d0_cvt_en) //|> w + ,.cvt_truncate (reg2dp_d0_cvt_truncate[5:0]) //|> w + ,.cvt_offset (reg2dp_d0_cvt_offset[15:0]) //|> w + ,.cvt_scale (reg2dp_d0_cvt_scale[15:0]) //|> w + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.datain_addr_high_0 (reg2dp_d0_datain_addr_high_0[31:0]) //|> w + ,.datain_addr_high_1 (reg2dp_d0_datain_addr_high_1[31:0]) //|> w + ,.datain_addr_low_0 (reg2dp_d0_datain_addr_low_0[31:0]) //|> w + ,.datain_addr_low_1 (reg2dp_d0_datain_addr_low_1[31:0]) //|> w + ,.line_packed (reg2dp_d0_line_packed) //|> w + ,.surf_packed (reg2dp_d0_surf_packed) //|> w + ,.datain_ram_type (reg2dp_d0_datain_ram_type) //|> w + ,.datain_format (reg2dp_d0_datain_format) //|> w + ,.pixel_format (reg2dp_d0_pixel_format[5:0]) //|> w + ,.pixel_mapping (reg2dp_d0_pixel_mapping) //|> w + ,.pixel_sign_override (reg2dp_d0_pixel_sign_override) //|> w + ,.datain_height (reg2dp_d0_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d0_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d0_datain_channel[12:0]) //|> w + ,.datain_height_ext (reg2dp_d0_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d0_datain_width_ext[12:0]) //|> w + ,.entries (reg2dp_d0_entries[13:0]) //|> w + ,.grains (reg2dp_d0_grains[11:0]) //|> w + ,.line_stride (reg2dp_d0_line_stride[31:0]) //|> w + ,.uv_line_stride (reg2dp_d0_uv_line_stride[31:0]) //|> w + ,.mean_format (reg2dp_d0_mean_format) //|> w + ,.mean_gu (reg2dp_d0_mean_gu[15:0]) //|> w + ,.mean_ry (reg2dp_d0_mean_ry[15:0]) //|> w + ,.mean_ax (reg2dp_d0_mean_ax[15:0]) //|> w + ,.mean_bv (reg2dp_d0_mean_bv[15:0]) //|> w + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.data_reuse (reg2dp_d0_data_reuse) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d0_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d0_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d0_weight_reuse) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.pixel_x_offset (reg2dp_d0_pixel_x_offset[4:0]) //|> w + ,.pixel_y_offset (reg2dp_d0_pixel_y_offset[2:0]) //|> w + ,.rsv_per_line (reg2dp_d0_rsv_per_line[9:0]) //|> w + ,.rsv_per_uv_line (reg2dp_d0_rsv_per_uv_line[9:0]) //|> w + ,.rsv_height (reg2dp_d0_rsv_height[2:0]) //|> w + ,.rsv_y_index (reg2dp_d0_rsv_y_index[4:0]) //|> w + ,.surf_stride (reg2dp_d0_surf_stride[31:0]) //|> w + ,.weight_addr_high (reg2dp_d0_weight_addr_high[31:0]) //|> w + ,.weight_addr_low (reg2dp_d0_weight_addr_low[31:0]) //|> w + ,.weight_bytes (reg2dp_d0_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d0_weight_format) //|> w + ,.weight_ram_type (reg2dp_d0_weight_ram_type) //|> w + ,.byte_per_kernel (reg2dp_d0_byte_per_kernel[17:0]) //|> w + ,.weight_kernel (reg2dp_d0_weight_kernel[12:0]) //|> w + ,.wgs_addr_high (reg2dp_d0_wgs_addr_high[31:0]) //|> w + ,.wgs_addr_low (reg2dp_d0_wgs_addr_low[31:0]) //|> w + ,.wmb_addr_high (reg2dp_d0_wmb_addr_high[31:0]) //|> w + ,.wmb_addr_low (reg2dp_d0_wmb_addr_low[31:0]) //|> w + ,.wmb_bytes (reg2dp_d0_wmb_bytes[27:0]) //|> w + ,.pad_bottom (reg2dp_d0_pad_bottom[5:0]) //|> w + ,.pad_left (reg2dp_d0_pad_left[4:0]) //|> w + ,.pad_right (reg2dp_d0_pad_right[5:0]) //|> w + ,.pad_top (reg2dp_d0_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d0_pad_value[15:0]) //|> w + ,.inf_data_num (dp2reg_d0_inf_data_num[31:0]) //|< r + ,.inf_weight_num (dp2reg_d0_inf_weight_num[31:0]) //|< r + ,.nan_data_num (dp2reg_d0_nan_data_num[31:0]) //|< r + ,.nan_weight_num (dp2reg_d0_nan_weight_num[31:0]) //|< r + ,.op_en (reg2dp_d0_op_en) //|< r + ,.dat_rd_latency (dp2reg_d0_dat_rd_latency[31:0]) //|< r + ,.dat_rd_stall (dp2reg_d0_dat_rd_stall[31:0]) //|< r + ,.wt_rd_latency (dp2reg_d0_wt_rd_latency[31:0]) //|< r + ,.wt_rd_stall (dp2reg_d0_wt_rd_stall[31:0]) //|< r + ); +NV_NVDLA_CDMA_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_bank (reg2dp_d1_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d1_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d1_batches[4:0]) //|> w + ,.batch_stride (reg2dp_d1_batch_stride[31:0]) //|> w + ,.conv_x_stride (reg2dp_d1_conv_x_stride[2:0]) //|> w + ,.conv_y_stride (reg2dp_d1_conv_y_stride[2:0]) //|> w + ,.cvt_en (reg2dp_d1_cvt_en) //|> w + ,.cvt_truncate (reg2dp_d1_cvt_truncate[5:0]) //|> w + ,.cvt_offset (reg2dp_d1_cvt_offset[15:0]) //|> w + ,.cvt_scale (reg2dp_d1_cvt_scale[15:0]) //|> w + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.datain_addr_high_0 (reg2dp_d1_datain_addr_high_0[31:0]) //|> w + ,.datain_addr_high_1 (reg2dp_d1_datain_addr_high_1[31:0]) //|> w + ,.datain_addr_low_0 (reg2dp_d1_datain_addr_low_0[31:0]) //|> w + ,.datain_addr_low_1 (reg2dp_d1_datain_addr_low_1[31:0]) //|> w + ,.line_packed (reg2dp_d1_line_packed) //|> w + ,.surf_packed (reg2dp_d1_surf_packed) //|> w + ,.datain_ram_type (reg2dp_d1_datain_ram_type) //|> w + ,.datain_format (reg2dp_d1_datain_format) //|> w + ,.pixel_format (reg2dp_d1_pixel_format[5:0]) //|> w + ,.pixel_mapping (reg2dp_d1_pixel_mapping) //|> w + ,.pixel_sign_override (reg2dp_d1_pixel_sign_override) //|> w + ,.datain_height (reg2dp_d1_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d1_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d1_datain_channel[12:0]) //|> w + ,.datain_height_ext (reg2dp_d1_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d1_datain_width_ext[12:0]) //|> w + ,.entries (reg2dp_d1_entries[13:0]) //|> w + ,.grains (reg2dp_d1_grains[11:0]) //|> w + ,.line_stride (reg2dp_d1_line_stride[31:0]) //|> w + ,.uv_line_stride (reg2dp_d1_uv_line_stride[31:0]) //|> w + ,.mean_format (reg2dp_d1_mean_format) //|> w + ,.mean_gu (reg2dp_d1_mean_gu[15:0]) //|> w + ,.mean_ry (reg2dp_d1_mean_ry[15:0]) //|> w + ,.mean_ax (reg2dp_d1_mean_ax[15:0]) //|> w + ,.mean_bv (reg2dp_d1_mean_bv[15:0]) //|> w + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.data_reuse (reg2dp_d1_data_reuse) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d1_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d1_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d1_weight_reuse) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.pixel_x_offset (reg2dp_d1_pixel_x_offset[4:0]) //|> w + ,.pixel_y_offset (reg2dp_d1_pixel_y_offset[2:0]) //|> w + ,.rsv_per_line (reg2dp_d1_rsv_per_line[9:0]) //|> w + ,.rsv_per_uv_line (reg2dp_d1_rsv_per_uv_line[9:0]) //|> w + ,.rsv_height (reg2dp_d1_rsv_height[2:0]) //|> w + ,.rsv_y_index (reg2dp_d1_rsv_y_index[4:0]) //|> w + ,.surf_stride (reg2dp_d1_surf_stride[31:0]) //|> w + ,.weight_addr_high (reg2dp_d1_weight_addr_high[31:0]) //|> w + ,.weight_addr_low (reg2dp_d1_weight_addr_low[31:0]) //|> w + ,.weight_bytes (reg2dp_d1_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d1_weight_format) //|> w + ,.weight_ram_type (reg2dp_d1_weight_ram_type) //|> w + ,.byte_per_kernel (reg2dp_d1_byte_per_kernel[17:0]) //|> w + ,.weight_kernel (reg2dp_d1_weight_kernel[12:0]) //|> w + ,.wgs_addr_high (reg2dp_d1_wgs_addr_high[31:0]) //|> w + ,.wgs_addr_low (reg2dp_d1_wgs_addr_low[31:0]) //|> w + ,.wmb_addr_high (reg2dp_d1_wmb_addr_high[31:0]) //|> w + ,.wmb_addr_low (reg2dp_d1_wmb_addr_low[31:0]) //|> w + ,.wmb_bytes (reg2dp_d1_wmb_bytes[27:0]) //|> w + ,.pad_bottom (reg2dp_d1_pad_bottom[5:0]) //|> w + ,.pad_left (reg2dp_d1_pad_left[4:0]) //|> w + ,.pad_right (reg2dp_d1_pad_right[5:0]) //|> w + ,.pad_top (reg2dp_d1_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d1_pad_value[15:0]) //|> w + ,.inf_data_num (dp2reg_d1_inf_data_num[31:0]) //|< r + ,.inf_weight_num (dp2reg_d1_inf_weight_num[31:0]) //|< r + ,.nan_data_num (dp2reg_d1_nan_data_num[31:0]) //|< r + ,.nan_weight_num (dp2reg_d1_nan_weight_num[31:0]) //|< r + ,.op_en (reg2dp_d1_op_en) //|< r + ,.dat_rd_latency (dp2reg_d1_dat_rd_latency[31:0]) //|< r + ,.dat_rd_stall (dp2reg_d1_dat_rd_stall[31:0]) //|< r + ,.wt_rd_latency (dp2reg_d1_wt_rd_latency[31:0]) //|< r + ,.wt_rd_stall (dp2reg_d1_wt_rd_stall[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {8{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {8{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {8{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {8{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h5010 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h5010 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h5010 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cdma_req_pvld) == 1'b1) begin + req_pd <= csb2cdma_req_pd; +// VCS coverage off + end else if ((csb2cdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2csb_resp_valid <= 1'b0; + end else begin + cdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_data_bank + or reg2dp_d0_data_bank + ) begin + reg2dp_data_bank = dp2reg_consumer ? reg2dp_d1_data_bank : reg2dp_d0_data_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bank + or reg2dp_d0_weight_bank + ) begin + reg2dp_weight_bank = dp2reg_consumer ? reg2dp_d1_weight_bank : reg2dp_d0_weight_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_batches + or reg2dp_d0_batches + ) begin + reg2dp_batches = dp2reg_consumer ? reg2dp_d1_batches : reg2dp_d0_batches; +end +always @( + dp2reg_consumer + or reg2dp_d1_batch_stride + or reg2dp_d0_batch_stride + ) begin + reg2dp_batch_stride = dp2reg_consumer ? reg2dp_d1_batch_stride : reg2dp_d0_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_x_stride + or reg2dp_d0_conv_x_stride + ) begin + reg2dp_conv_x_stride = dp2reg_consumer ? reg2dp_d1_conv_x_stride : reg2dp_d0_conv_x_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_y_stride + or reg2dp_d0_conv_y_stride + ) begin + reg2dp_conv_y_stride = dp2reg_consumer ? reg2dp_d1_conv_y_stride : reg2dp_d0_conv_y_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_en + or reg2dp_d0_cvt_en + ) begin + reg2dp_cvt_en = dp2reg_consumer ? reg2dp_d1_cvt_en : reg2dp_d0_cvt_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_truncate + or reg2dp_d0_cvt_truncate + ) begin + reg2dp_cvt_truncate = dp2reg_consumer ? reg2dp_d1_cvt_truncate : reg2dp_d0_cvt_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_offset + or reg2dp_d0_cvt_offset + ) begin + reg2dp_cvt_offset = dp2reg_consumer ? reg2dp_d1_cvt_offset : reg2dp_d0_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_scale + or reg2dp_d0_cvt_scale + ) begin + reg2dp_cvt_scale = dp2reg_consumer ? reg2dp_d1_cvt_scale : reg2dp_d0_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_high_0 + or reg2dp_d0_datain_addr_high_0 + ) begin + reg2dp_datain_addr_high_0 = dp2reg_consumer ? reg2dp_d1_datain_addr_high_0 : reg2dp_d0_datain_addr_high_0; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_high_1 + or reg2dp_d0_datain_addr_high_1 + ) begin + reg2dp_datain_addr_high_1 = dp2reg_consumer ? reg2dp_d1_datain_addr_high_1 : reg2dp_d0_datain_addr_high_1; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_low_0 + or reg2dp_d0_datain_addr_low_0 + ) begin + reg2dp_datain_addr_low_0 = dp2reg_consumer ? reg2dp_d1_datain_addr_low_0 : reg2dp_d0_datain_addr_low_0; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_low_1 + or reg2dp_d0_datain_addr_low_1 + ) begin + reg2dp_datain_addr_low_1 = dp2reg_consumer ? reg2dp_d1_datain_addr_low_1 : reg2dp_d0_datain_addr_low_1; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_packed + or reg2dp_d0_line_packed + ) begin + reg2dp_line_packed = dp2reg_consumer ? reg2dp_d1_line_packed : reg2dp_d0_line_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_packed + or reg2dp_d0_surf_packed + ) begin + reg2dp_surf_packed = dp2reg_consumer ? reg2dp_d1_surf_packed : reg2dp_d0_surf_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_ram_type + or reg2dp_d0_datain_ram_type + ) begin + reg2dp_datain_ram_type = dp2reg_consumer ? reg2dp_d1_datain_ram_type : reg2dp_d0_datain_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_format + or reg2dp_d0_datain_format + ) begin + reg2dp_datain_format = dp2reg_consumer ? reg2dp_d1_datain_format : reg2dp_d0_datain_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_format + or reg2dp_d0_pixel_format + ) begin + reg2dp_pixel_format = dp2reg_consumer ? reg2dp_d1_pixel_format : reg2dp_d0_pixel_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_mapping + or reg2dp_d0_pixel_mapping + ) begin + reg2dp_pixel_mapping = dp2reg_consumer ? reg2dp_d1_pixel_mapping : reg2dp_d0_pixel_mapping; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_sign_override + or reg2dp_d0_pixel_sign_override + ) begin + reg2dp_pixel_sign_override = dp2reg_consumer ? reg2dp_d1_pixel_sign_override : reg2dp_d0_pixel_sign_override; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height + or reg2dp_d0_datain_height + ) begin + reg2dp_datain_height = dp2reg_consumer ? reg2dp_d1_datain_height : reg2dp_d0_datain_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width + or reg2dp_d0_datain_width + ) begin + reg2dp_datain_width = dp2reg_consumer ? reg2dp_d1_datain_width : reg2dp_d0_datain_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_channel + or reg2dp_d0_datain_channel + ) begin + reg2dp_datain_channel = dp2reg_consumer ? reg2dp_d1_datain_channel : reg2dp_d0_datain_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height_ext + or reg2dp_d0_datain_height_ext + ) begin + reg2dp_datain_height_ext = dp2reg_consumer ? reg2dp_d1_datain_height_ext : reg2dp_d0_datain_height_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width_ext + or reg2dp_d0_datain_width_ext + ) begin + reg2dp_datain_width_ext = dp2reg_consumer ? reg2dp_d1_datain_width_ext : reg2dp_d0_datain_width_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_entries + or reg2dp_d0_entries + ) begin + reg2dp_entries = dp2reg_consumer ? reg2dp_d1_entries : reg2dp_d0_entries; +end +always @( + dp2reg_consumer + or reg2dp_d1_grains + or reg2dp_d0_grains + ) begin + reg2dp_grains = dp2reg_consumer ? reg2dp_d1_grains : reg2dp_d0_grains; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_stride + or reg2dp_d0_line_stride + ) begin + reg2dp_line_stride = dp2reg_consumer ? reg2dp_d1_line_stride : reg2dp_d0_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_uv_line_stride + or reg2dp_d0_uv_line_stride + ) begin + reg2dp_uv_line_stride = dp2reg_consumer ? reg2dp_d1_uv_line_stride : reg2dp_d0_uv_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_format + or reg2dp_d0_mean_format + ) begin + reg2dp_mean_format = dp2reg_consumer ? reg2dp_d1_mean_format : reg2dp_d0_mean_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_gu + or reg2dp_d0_mean_gu + ) begin + reg2dp_mean_gu = dp2reg_consumer ? reg2dp_d1_mean_gu : reg2dp_d0_mean_gu; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_ry + or reg2dp_d0_mean_ry + ) begin + reg2dp_mean_ry = dp2reg_consumer ? reg2dp_d1_mean_ry : reg2dp_d0_mean_ry; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_ax + or reg2dp_d0_mean_ax + ) begin + reg2dp_mean_ax = dp2reg_consumer ? reg2dp_d1_mean_ax : reg2dp_d0_mean_ax; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_bv + or reg2dp_d0_mean_bv + ) begin + reg2dp_mean_bv = dp2reg_consumer ? reg2dp_d1_mean_bv : reg2dp_d0_mean_bv; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_data_reuse + or reg2dp_d0_data_reuse + ) begin + reg2dp_data_reuse = dp2reg_consumer ? reg2dp_d1_data_reuse : reg2dp_d0_data_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_data_rls + or reg2dp_d0_skip_data_rls + ) begin + reg2dp_skip_data_rls = dp2reg_consumer ? reg2dp_d1_skip_data_rls : reg2dp_d0_skip_data_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_weight_rls + or reg2dp_d0_skip_weight_rls + ) begin + reg2dp_skip_weight_rls = dp2reg_consumer ? reg2dp_d1_skip_weight_rls : reg2dp_d0_skip_weight_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_reuse + or reg2dp_d0_weight_reuse + ) begin + reg2dp_weight_reuse = dp2reg_consumer ? reg2dp_d1_weight_reuse : reg2dp_d0_weight_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_x_offset + or reg2dp_d0_pixel_x_offset + ) begin + reg2dp_pixel_x_offset = dp2reg_consumer ? reg2dp_d1_pixel_x_offset : reg2dp_d0_pixel_x_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_y_offset + or reg2dp_d0_pixel_y_offset + ) begin + reg2dp_pixel_y_offset = dp2reg_consumer ? reg2dp_d1_pixel_y_offset : reg2dp_d0_pixel_y_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_per_line + or reg2dp_d0_rsv_per_line + ) begin + reg2dp_rsv_per_line = dp2reg_consumer ? reg2dp_d1_rsv_per_line : reg2dp_d0_rsv_per_line; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_per_uv_line + or reg2dp_d0_rsv_per_uv_line + ) begin + reg2dp_rsv_per_uv_line = dp2reg_consumer ? reg2dp_d1_rsv_per_uv_line : reg2dp_d0_rsv_per_uv_line; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_height + or reg2dp_d0_rsv_height + ) begin + reg2dp_rsv_height = dp2reg_consumer ? reg2dp_d1_rsv_height : reg2dp_d0_rsv_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_y_index + or reg2dp_d0_rsv_y_index + ) begin + reg2dp_rsv_y_index = dp2reg_consumer ? reg2dp_d1_rsv_y_index : reg2dp_d0_rsv_y_index; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_stride + or reg2dp_d0_surf_stride + ) begin + reg2dp_surf_stride = dp2reg_consumer ? reg2dp_d1_surf_stride : reg2dp_d0_surf_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_addr_high + or reg2dp_d0_weight_addr_high + ) begin + reg2dp_weight_addr_high = dp2reg_consumer ? reg2dp_d1_weight_addr_high : reg2dp_d0_weight_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_addr_low + or reg2dp_d0_weight_addr_low + ) begin + reg2dp_weight_addr_low = dp2reg_consumer ? reg2dp_d1_weight_addr_low : reg2dp_d0_weight_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bytes + or reg2dp_d0_weight_bytes + ) begin + reg2dp_weight_bytes = dp2reg_consumer ? reg2dp_d1_weight_bytes : reg2dp_d0_weight_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_format + or reg2dp_d0_weight_format + ) begin + reg2dp_weight_format = dp2reg_consumer ? reg2dp_d1_weight_format : reg2dp_d0_weight_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_ram_type + or reg2dp_d0_weight_ram_type + ) begin + reg2dp_weight_ram_type = dp2reg_consumer ? reg2dp_d1_weight_ram_type : reg2dp_d0_weight_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_byte_per_kernel + or reg2dp_d0_byte_per_kernel + ) begin + reg2dp_byte_per_kernel = dp2reg_consumer ? reg2dp_d1_byte_per_kernel : reg2dp_d0_byte_per_kernel; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_kernel + or reg2dp_d0_weight_kernel + ) begin + reg2dp_weight_kernel = dp2reg_consumer ? reg2dp_d1_weight_kernel : reg2dp_d0_weight_kernel; +end +always @( + dp2reg_consumer + or reg2dp_d1_wgs_addr_high + or reg2dp_d0_wgs_addr_high + ) begin + reg2dp_wgs_addr_high = dp2reg_consumer ? reg2dp_d1_wgs_addr_high : reg2dp_d0_wgs_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_wgs_addr_low + or reg2dp_d0_wgs_addr_low + ) begin + reg2dp_wgs_addr_low = dp2reg_consumer ? reg2dp_d1_wgs_addr_low : reg2dp_d0_wgs_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_addr_high + or reg2dp_d0_wmb_addr_high + ) begin + reg2dp_wmb_addr_high = dp2reg_consumer ? reg2dp_d1_wmb_addr_high : reg2dp_d0_wmb_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_addr_low + or reg2dp_d0_wmb_addr_low + ) begin + reg2dp_wmb_addr_low = dp2reg_consumer ? reg2dp_d1_wmb_addr_low : reg2dp_d0_wmb_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_bytes + or reg2dp_d0_wmb_bytes + ) begin + reg2dp_wmb_bytes = dp2reg_consumer ? reg2dp_d1_wmb_bytes : reg2dp_d0_wmb_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_bottom + or reg2dp_d0_pad_bottom + ) begin + reg2dp_pad_bottom = dp2reg_consumer ? reg2dp_d1_pad_bottom : reg2dp_d0_pad_bottom; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_left + or reg2dp_d0_pad_left + ) begin + reg2dp_pad_left = dp2reg_consumer ? reg2dp_d1_pad_left : reg2dp_d0_pad_left; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_right + or reg2dp_d0_pad_right + ) begin + reg2dp_pad_right = dp2reg_consumer ? reg2dp_d1_pad_right : reg2dp_d0_pad_right; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_top + or reg2dp_d0_pad_top + ) begin + reg2dp_pad_top = dp2reg_consumer ? reg2dp_d1_pad_top : reg2dp_d0_pad_top; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value + or reg2dp_d0_pad_value + ) begin + reg2dp_pad_value = dp2reg_consumer ? reg2dp_d1_pad_value : reg2dp_d0_pad_value; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// for interrupt // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// for cbuf flushing logic // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_flush_done <= 1'b0; + end else begin + dp2reg_flush_done <= dp2reg_wt_flush_done & dp2reg_dat_flush_done; + end +end +//////////////////////////////////////////////////////////////////////// +// for general counting register // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////////////////////////////////////////////////////////////////////// +// for NaN and infinity counting registers // +//////////////////////////////////////////////////////////////////////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_nan_weight_num + or dp2reg_d0_clr + or dp2reg_d0_nan_weight_num + ) begin + dp2reg_d0_nan_weight_num_w = (dp2reg_d0_set) ? dp2reg_nan_weight_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_weight_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_weight_num + or dp2reg_d0_clr + or dp2reg_d0_inf_weight_num + ) begin + dp2reg_d0_inf_weight_num_w = (dp2reg_d0_set) ? dp2reg_inf_weight_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_weight_num; +end +always @( + dp2reg_d0_set + or dp2reg_nan_data_num + or dp2reg_d0_clr + or dp2reg_d0_nan_data_num + ) begin + dp2reg_d0_nan_data_num_w = (dp2reg_d0_set) ? dp2reg_nan_data_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_data_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_data_num + or dp2reg_d0_clr + or dp2reg_d0_inf_data_num + ) begin + dp2reg_d0_inf_data_num_w = (dp2reg_d0_set) ? dp2reg_inf_data_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_data_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_weight_num <= dp2reg_d0_nan_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_weight_num <= dp2reg_d0_inf_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_data_num <= dp2reg_d0_nan_data_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_data_num <= dp2reg_d0_inf_data_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_nan_weight_num + or dp2reg_d1_clr + or dp2reg_d1_nan_weight_num + ) begin + dp2reg_d1_nan_weight_num_w = (dp2reg_d1_set) ? dp2reg_nan_weight_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_weight_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_weight_num + or dp2reg_d1_clr + or dp2reg_d1_inf_weight_num + ) begin + dp2reg_d1_inf_weight_num_w = (dp2reg_d1_set) ? dp2reg_inf_weight_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_weight_num; +end +always @( + dp2reg_d1_set + or dp2reg_nan_data_num + or dp2reg_d1_clr + or dp2reg_d1_nan_data_num + ) begin + dp2reg_d1_nan_data_num_w = (dp2reg_d1_set) ? dp2reg_nan_data_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_data_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_data_num + or dp2reg_d1_clr + or dp2reg_d1_inf_data_num + ) begin + dp2reg_d1_inf_data_num_w = (dp2reg_d1_set) ? dp2reg_inf_data_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_data_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_weight_num <= dp2reg_d1_nan_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_weight_num <= dp2reg_d1_inf_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_data_num <= dp2reg_d1_nan_data_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_data_num <= dp2reg_d1_inf_data_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// for perf conting registers // +//////////////////////////////////////////////////////////////////////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_wt_rd_stall + or dp2reg_d0_clr + or dp2reg_d0_wt_rd_stall + ) begin + dp2reg_d0_wt_rd_stall_w = (dp2reg_d0_set) ? dp2reg_wt_rd_stall : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_wt_rd_stall; +end +always @( + dp2reg_d0_set + or dp2reg_wt_rd_latency + or dp2reg_d0_clr + or dp2reg_d0_wt_rd_latency + ) begin + dp2reg_d0_wt_rd_latency_w = (dp2reg_d0_set) ? dp2reg_wt_rd_latency : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_wt_rd_latency; +end +always @( + dp2reg_d0_set + or dp2reg_dc_rd_stall + or dp2reg_wg_rd_stall + or dp2reg_img_rd_stall + or dp2reg_d0_clr + or dp2reg_d0_dat_rd_stall + ) begin + dp2reg_d0_dat_rd_stall_w = (dp2reg_d0_set) ? (dp2reg_dc_rd_stall | dp2reg_wg_rd_stall | dp2reg_img_rd_stall) : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_dat_rd_stall; +end +always @( + dp2reg_d0_set + or dp2reg_dc_rd_latency + or dp2reg_wg_rd_latency + or dp2reg_img_rd_latency + or dp2reg_d0_clr + or dp2reg_d0_dat_rd_latency + ) begin + dp2reg_d0_dat_rd_latency_w = (dp2reg_d0_set) ? (dp2reg_dc_rd_latency | dp2reg_wg_rd_latency | dp2reg_img_rd_latency) : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_dat_rd_latency; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wt_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_wt_rd_stall <= dp2reg_d0_wt_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_wt_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wt_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_wt_rd_latency <= dp2reg_d0_wt_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_wt_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_dat_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_dat_rd_stall <= dp2reg_d0_dat_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_dat_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_dat_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_dat_rd_latency <= dp2reg_d0_dat_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_dat_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_wt_rd_stall + or dp2reg_d1_clr + or dp2reg_d1_wt_rd_stall + ) begin + dp2reg_d1_wt_rd_stall_w = (dp2reg_d1_set) ? dp2reg_wt_rd_stall : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_wt_rd_stall; +end +always @( + dp2reg_d1_set + or dp2reg_wt_rd_latency + or dp2reg_d1_clr + or dp2reg_d1_wt_rd_latency + ) begin + dp2reg_d1_wt_rd_latency_w = (dp2reg_d1_set) ? dp2reg_wt_rd_latency : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_wt_rd_latency; +end +always @( + dp2reg_d1_set + or dp2reg_dc_rd_stall + or dp2reg_wg_rd_stall + or dp2reg_img_rd_stall + or dp2reg_d1_clr + or dp2reg_d1_dat_rd_stall + ) begin + dp2reg_d1_dat_rd_stall_w = (dp2reg_d1_set) ? (dp2reg_dc_rd_stall | dp2reg_wg_rd_stall | dp2reg_img_rd_stall) : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_dat_rd_stall; +end +always @( + dp2reg_d1_set + or dp2reg_dc_rd_latency + or dp2reg_wg_rd_latency + or dp2reg_img_rd_latency + or dp2reg_d1_clr + or dp2reg_d1_dat_rd_latency + ) begin + dp2reg_d1_dat_rd_latency_w = (dp2reg_d1_set) ? (dp2reg_dc_rd_latency | dp2reg_wg_rd_latency | dp2reg_img_rd_latency) : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_dat_rd_latency; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wt_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_wt_rd_stall <= dp2reg_d1_wt_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_wt_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wt_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_wt_rd_latency <= dp2reg_d1_wt_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_wt_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_dat_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_dat_rd_stall <= dp2reg_d1_dat_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_dat_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_dat_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_dat_rd_latency <= dp2reg_d1_dat_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_dat_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v.vcp new file mode 100644 index 0000000..e5171d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v.vcp @@ -0,0 +1,2779 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cdma_req_pd //|< i + ,csb2cdma_req_pvld //|< i + ,dp2reg_dat_flush_done //|< i + ,dp2reg_dc_rd_latency //|< i + ,dp2reg_dc_rd_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_img_rd_latency //|< i + ,dp2reg_img_rd_stall //|< i + ,dp2reg_inf_data_num //|< i + ,dp2reg_inf_weight_num //|< i + ,dp2reg_nan_data_num //|< i + ,dp2reg_nan_weight_num //|< i + ,dp2reg_wg_rd_latency //|< i + ,dp2reg_wg_rd_stall //|< i + ,dp2reg_wt_flush_done //|< i + ,dp2reg_wt_rd_latency //|< i + ,dp2reg_wt_rd_stall //|< i + ,cdma2csb_resp_pd //|> o + ,cdma2csb_resp_valid //|> o + ,csb2cdma_req_prdy //|> o + ,dp2reg_consumer //|> o + ,reg2dp_arb_weight //|> o + ,reg2dp_arb_wmb //|> o + ,reg2dp_batch_stride //|> o + ,reg2dp_batches //|> o + ,reg2dp_byte_per_kernel //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_conv_x_stride //|> o + ,reg2dp_conv_y_stride //|> o + ,reg2dp_cvt_en //|> o + ,reg2dp_cvt_offset //|> o + ,reg2dp_cvt_scale //|> o + ,reg2dp_cvt_truncate //|> o + ,reg2dp_cya //|> o + ,reg2dp_data_bank //|> o + ,reg2dp_data_reuse //|> o + ,reg2dp_datain_addr_high_0 //|> o + ,reg2dp_datain_addr_high_1 //|> o + ,reg2dp_datain_addr_low_0 //|> o + ,reg2dp_datain_addr_low_1 //|> o + ,reg2dp_datain_channel //|> o + ,reg2dp_datain_format //|> o + ,reg2dp_datain_height //|> o + ,reg2dp_datain_height_ext //|> o + ,reg2dp_datain_ram_type //|> o + ,reg2dp_datain_width //|> o + ,reg2dp_datain_width_ext //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_entries //|> o + ,reg2dp_grains //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_line_packed //|> o + ,reg2dp_line_stride //|> o + ,reg2dp_mean_ax //|> o + ,reg2dp_mean_bv //|> o + ,reg2dp_mean_format //|> o + ,reg2dp_mean_gu //|> o + ,reg2dp_mean_ry //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_bottom //|> o + ,reg2dp_pad_left //|> o + ,reg2dp_pad_right //|> o + ,reg2dp_pad_top //|> o + ,reg2dp_pad_value //|> o + ,reg2dp_pixel_format //|> o + ,reg2dp_pixel_mapping //|> o + ,reg2dp_pixel_sign_override //|> o + ,reg2dp_pixel_x_offset //|> o + ,reg2dp_pixel_y_offset //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_rsv_height //|> o + ,reg2dp_rsv_per_line //|> o + ,reg2dp_rsv_per_uv_line //|> o + ,reg2dp_rsv_y_index //|> o + ,reg2dp_skip_data_rls //|> o + ,reg2dp_skip_weight_rls //|> o + ,reg2dp_surf_packed //|> o + ,reg2dp_surf_stride //|> o + ,reg2dp_uv_line_stride //|> o + ,reg2dp_weight_addr_high //|> o + ,reg2dp_weight_addr_low //|> o + ,reg2dp_weight_bank //|> o + ,reg2dp_weight_bytes //|> o + ,reg2dp_weight_format //|> o + ,reg2dp_weight_kernel //|> o + ,reg2dp_weight_ram_type //|> o + ,reg2dp_weight_reuse //|> o + ,reg2dp_wgs_addr_high //|> o + ,reg2dp_wgs_addr_low //|> o + ,reg2dp_wmb_addr_high //|> o + ,reg2dp_wmb_addr_low //|> o + ,reg2dp_wmb_bytes //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cdma_req_pd; +input csb2cdma_req_pvld; +input dp2reg_dat_flush_done; +input [31:0] dp2reg_dc_rd_latency; +input [31:0] dp2reg_dc_rd_stall; +input dp2reg_done; +input [31:0] dp2reg_img_rd_latency; +input [31:0] dp2reg_img_rd_stall; +input [31:0] dp2reg_inf_data_num; +input [31:0] dp2reg_inf_weight_num; +input [31:0] dp2reg_nan_data_num; +input [31:0] dp2reg_nan_weight_num; +input [31:0] dp2reg_wg_rd_latency; +input [31:0] dp2reg_wg_rd_stall; +input dp2reg_wt_flush_done; +input [31:0] dp2reg_wt_rd_latency; +input [31:0] dp2reg_wt_rd_stall; +output [33:0] cdma2csb_resp_pd; +output cdma2csb_resp_valid; +output csb2cdma_req_prdy; +output dp2reg_consumer; +output [3:0] reg2dp_arb_weight; +output [3:0] reg2dp_arb_wmb; +output [31:0] reg2dp_batch_stride; +output [4:0] reg2dp_batches; +output [17:0] reg2dp_byte_per_kernel; +output reg2dp_conv_mode; +output [2:0] reg2dp_conv_x_stride; +output [2:0] reg2dp_conv_y_stride; +output reg2dp_cvt_en; +output [15:0] reg2dp_cvt_offset; +output [15:0] reg2dp_cvt_scale; +output [5:0] reg2dp_cvt_truncate; +output [31:0] reg2dp_cya; +output [4:0] reg2dp_data_bank; +output reg2dp_data_reuse; +output [31:0] reg2dp_datain_addr_high_0; +output [31:0] reg2dp_datain_addr_high_1; +output [31:0] reg2dp_datain_addr_low_0; +output [31:0] reg2dp_datain_addr_low_1; +output [12:0] reg2dp_datain_channel; +output reg2dp_datain_format; +output [12:0] reg2dp_datain_height; +output [12:0] reg2dp_datain_height_ext; +output reg2dp_datain_ram_type; +output [12:0] reg2dp_datain_width; +output [12:0] reg2dp_datain_width_ext; +output reg2dp_dma_en; +output [13:0] reg2dp_entries; +output [11:0] reg2dp_grains; +output [1:0] reg2dp_in_precision; +output reg2dp_line_packed; +output [31:0] reg2dp_line_stride; +output [15:0] reg2dp_mean_ax; +output [15:0] reg2dp_mean_bv; +output reg2dp_mean_format; +output [15:0] reg2dp_mean_gu; +output [15:0] reg2dp_mean_ry; +output reg2dp_nan_to_zero; +output reg2dp_op_en; +output [5:0] reg2dp_pad_bottom; +output [4:0] reg2dp_pad_left; +output [5:0] reg2dp_pad_right; +output [4:0] reg2dp_pad_top; +output [15:0] reg2dp_pad_value; +output [5:0] reg2dp_pixel_format; +output reg2dp_pixel_mapping; +output reg2dp_pixel_sign_override; +output [4:0] reg2dp_pixel_x_offset; +output [2:0] reg2dp_pixel_y_offset; +output [1:0] reg2dp_proc_precision; +output [2:0] reg2dp_rsv_height; +output [9:0] reg2dp_rsv_per_line; +output [9:0] reg2dp_rsv_per_uv_line; +output [4:0] reg2dp_rsv_y_index; +output reg2dp_skip_data_rls; +output reg2dp_skip_weight_rls; +output reg2dp_surf_packed; +output [31:0] reg2dp_surf_stride; +output [31:0] reg2dp_uv_line_stride; +output [31:0] reg2dp_weight_addr_high; +output [31:0] reg2dp_weight_addr_low; +output [4:0] reg2dp_weight_bank; +output [31:0] reg2dp_weight_bytes; +output reg2dp_weight_format; +output [12:0] reg2dp_weight_kernel; +output reg2dp_weight_ram_type; +output reg2dp_weight_reuse; +output [31:0] reg2dp_wgs_addr_high; +output [31:0] reg2dp_wgs_addr_low; +output [31:0] reg2dp_wmb_addr_high; +output [31:0] reg2dp_wmb_addr_low; +output [27:0] reg2dp_wmb_bytes; +output [7:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [31:0] reg2dp_d0_batch_stride; +wire [4:0] reg2dp_d0_batches; +wire [17:0] reg2dp_d0_byte_per_kernel; +wire reg2dp_d0_conv_mode; +wire [2:0] reg2dp_d0_conv_x_stride; +wire [2:0] reg2dp_d0_conv_y_stride; +wire reg2dp_d0_cvt_en; +wire [15:0] reg2dp_d0_cvt_offset; +wire [15:0] reg2dp_d0_cvt_scale; +wire [5:0] reg2dp_d0_cvt_truncate; +wire [31:0] reg2dp_d0_cya; +wire [4:0] reg2dp_d0_data_bank; +wire reg2dp_d0_data_reuse; +wire [31:0] reg2dp_d0_datain_addr_high_0; +wire [31:0] reg2dp_d0_datain_addr_high_1; +wire [31:0] reg2dp_d0_datain_addr_low_0; +wire [31:0] reg2dp_d0_datain_addr_low_1; +wire [12:0] reg2dp_d0_datain_channel; +wire reg2dp_d0_datain_format; +wire [12:0] reg2dp_d0_datain_height; +wire [12:0] reg2dp_d0_datain_height_ext; +wire reg2dp_d0_datain_ram_type; +wire [12:0] reg2dp_d0_datain_width; +wire [12:0] reg2dp_d0_datain_width_ext; +wire reg2dp_d0_dma_en; +wire [13:0] reg2dp_d0_entries; +wire [11:0] reg2dp_d0_grains; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_line_packed; +wire [31:0] reg2dp_d0_line_stride; +wire [15:0] reg2dp_d0_mean_ax; +wire [15:0] reg2dp_d0_mean_bv; +wire reg2dp_d0_mean_format; +wire [15:0] reg2dp_d0_mean_gu; +wire [15:0] reg2dp_d0_mean_ry; +wire reg2dp_d0_nan_to_zero; +wire reg2dp_d0_op_en_trigger; +wire [5:0] reg2dp_d0_pad_bottom; +wire [4:0] reg2dp_d0_pad_left; +wire [5:0] reg2dp_d0_pad_right; +wire [4:0] reg2dp_d0_pad_top; +wire [15:0] reg2dp_d0_pad_value; +wire [5:0] reg2dp_d0_pixel_format; +wire reg2dp_d0_pixel_mapping; +wire reg2dp_d0_pixel_sign_override; +wire [4:0] reg2dp_d0_pixel_x_offset; +wire [2:0] reg2dp_d0_pixel_y_offset; +wire [1:0] reg2dp_d0_proc_precision; +wire [2:0] reg2dp_d0_rsv_height; +wire [9:0] reg2dp_d0_rsv_per_line; +wire [9:0] reg2dp_d0_rsv_per_uv_line; +wire [4:0] reg2dp_d0_rsv_y_index; +wire reg2dp_d0_skip_data_rls; +wire reg2dp_d0_skip_weight_rls; +wire reg2dp_d0_surf_packed; +wire [31:0] reg2dp_d0_surf_stride; +wire [31:0] reg2dp_d0_uv_line_stride; +wire [31:0] reg2dp_d0_weight_addr_high; +wire [31:0] reg2dp_d0_weight_addr_low; +wire [4:0] reg2dp_d0_weight_bank; +wire [31:0] reg2dp_d0_weight_bytes; +wire reg2dp_d0_weight_format; +wire [12:0] reg2dp_d0_weight_kernel; +wire reg2dp_d0_weight_ram_type; +wire reg2dp_d0_weight_reuse; +wire [31:0] reg2dp_d0_wgs_addr_high; +wire [31:0] reg2dp_d0_wgs_addr_low; +wire [31:0] reg2dp_d0_wmb_addr_high; +wire [31:0] reg2dp_d0_wmb_addr_low; +wire [27:0] reg2dp_d0_wmb_bytes; +wire [31:0] reg2dp_d1_batch_stride; +wire [4:0] reg2dp_d1_batches; +wire [17:0] reg2dp_d1_byte_per_kernel; +wire reg2dp_d1_conv_mode; +wire [2:0] reg2dp_d1_conv_x_stride; +wire [2:0] reg2dp_d1_conv_y_stride; +wire reg2dp_d1_cvt_en; +wire [15:0] reg2dp_d1_cvt_offset; +wire [15:0] reg2dp_d1_cvt_scale; +wire [5:0] reg2dp_d1_cvt_truncate; +wire [31:0] reg2dp_d1_cya; +wire [4:0] reg2dp_d1_data_bank; +wire reg2dp_d1_data_reuse; +wire [31:0] reg2dp_d1_datain_addr_high_0; +wire [31:0] reg2dp_d1_datain_addr_high_1; +wire [31:0] reg2dp_d1_datain_addr_low_0; +wire [31:0] reg2dp_d1_datain_addr_low_1; +wire [12:0] reg2dp_d1_datain_channel; +wire reg2dp_d1_datain_format; +wire [12:0] reg2dp_d1_datain_height; +wire [12:0] reg2dp_d1_datain_height_ext; +wire reg2dp_d1_datain_ram_type; +wire [12:0] reg2dp_d1_datain_width; +wire [12:0] reg2dp_d1_datain_width_ext; +wire reg2dp_d1_dma_en; +wire [13:0] reg2dp_d1_entries; +wire [11:0] reg2dp_d1_grains; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_line_packed; +wire [31:0] reg2dp_d1_line_stride; +wire [15:0] reg2dp_d1_mean_ax; +wire [15:0] reg2dp_d1_mean_bv; +wire reg2dp_d1_mean_format; +wire [15:0] reg2dp_d1_mean_gu; +wire [15:0] reg2dp_d1_mean_ry; +wire reg2dp_d1_nan_to_zero; +wire reg2dp_d1_op_en_trigger; +wire [5:0] reg2dp_d1_pad_bottom; +wire [4:0] reg2dp_d1_pad_left; +wire [5:0] reg2dp_d1_pad_right; +wire [4:0] reg2dp_d1_pad_top; +wire [15:0] reg2dp_d1_pad_value; +wire [5:0] reg2dp_d1_pixel_format; +wire reg2dp_d1_pixel_mapping; +wire reg2dp_d1_pixel_sign_override; +wire [4:0] reg2dp_d1_pixel_x_offset; +wire [2:0] reg2dp_d1_pixel_y_offset; +wire [1:0] reg2dp_d1_proc_precision; +wire [2:0] reg2dp_d1_rsv_height; +wire [9:0] reg2dp_d1_rsv_per_line; +wire [9:0] reg2dp_d1_rsv_per_uv_line; +wire [4:0] reg2dp_d1_rsv_y_index; +wire reg2dp_d1_skip_data_rls; +wire reg2dp_d1_skip_weight_rls; +wire reg2dp_d1_surf_packed; +wire [31:0] reg2dp_d1_surf_stride; +wire [31:0] reg2dp_d1_uv_line_stride; +wire [31:0] reg2dp_d1_weight_addr_high; +wire [31:0] reg2dp_d1_weight_addr_low; +wire [4:0] reg2dp_d1_weight_bank; +wire [31:0] reg2dp_d1_weight_bytes; +wire reg2dp_d1_weight_format; +wire [12:0] reg2dp_d1_weight_kernel; +wire reg2dp_d1_weight_ram_type; +wire reg2dp_d1_weight_reuse; +wire [31:0] reg2dp_d1_wgs_addr_high; +wire [31:0] reg2dp_d1_wgs_addr_low; +wire [31:0] reg2dp_d1_wmb_addr_high; +wire [31:0] reg2dp_d1_wmb_addr_low; +wire [27:0] reg2dp_d1_wmb_bytes; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [7:0] slcg_op_en_d0; +reg [33:0] cdma2csb_resp_pd; +reg cdma2csb_resp_valid; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_dat_rd_latency; +reg [31:0] dp2reg_d0_dat_rd_latency_w; +reg [31:0] dp2reg_d0_dat_rd_stall; +reg [31:0] dp2reg_d0_dat_rd_stall_w; +reg [31:0] dp2reg_d0_inf_data_num; +reg [31:0] dp2reg_d0_inf_data_num_w; +reg [31:0] dp2reg_d0_inf_weight_num; +reg [31:0] dp2reg_d0_inf_weight_num_w; +reg [31:0] dp2reg_d0_nan_data_num; +reg [31:0] dp2reg_d0_nan_data_num_w; +reg [31:0] dp2reg_d0_nan_weight_num; +reg [31:0] dp2reg_d0_nan_weight_num_w; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg [31:0] dp2reg_d0_wt_rd_latency; +reg [31:0] dp2reg_d0_wt_rd_latency_w; +reg [31:0] dp2reg_d0_wt_rd_stall; +reg [31:0] dp2reg_d0_wt_rd_stall_w; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_dat_rd_latency; +reg [31:0] dp2reg_d1_dat_rd_latency_w; +reg [31:0] dp2reg_d1_dat_rd_stall; +reg [31:0] dp2reg_d1_dat_rd_stall_w; +reg [31:0] dp2reg_d1_inf_data_num; +reg [31:0] dp2reg_d1_inf_data_num_w; +reg [31:0] dp2reg_d1_inf_weight_num; +reg [31:0] dp2reg_d1_inf_weight_num_w; +reg [31:0] dp2reg_d1_nan_data_num; +reg [31:0] dp2reg_d1_nan_data_num_w; +reg [31:0] dp2reg_d1_nan_weight_num; +reg [31:0] dp2reg_d1_nan_weight_num_w; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [31:0] dp2reg_d1_wt_rd_latency; +reg [31:0] dp2reg_d1_wt_rd_latency_w; +reg [31:0] dp2reg_d1_wt_rd_stall; +reg [31:0] dp2reg_d1_wt_rd_stall_w; +reg dp2reg_flush_done; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [31:0] reg2dp_batch_stride; +reg [4:0] reg2dp_batches; +reg [17:0] reg2dp_byte_per_kernel; +reg reg2dp_conv_mode; +reg [2:0] reg2dp_conv_x_stride; +reg [2:0] reg2dp_conv_y_stride; +reg reg2dp_cvt_en; +reg [15:0] reg2dp_cvt_offset; +reg [15:0] reg2dp_cvt_scale; +reg [5:0] reg2dp_cvt_truncate; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [4:0] reg2dp_data_bank; +reg reg2dp_data_reuse; +reg [31:0] reg2dp_datain_addr_high_0; +reg [31:0] reg2dp_datain_addr_high_1; +reg [31:0] reg2dp_datain_addr_low_0; +reg [31:0] reg2dp_datain_addr_low_1; +reg [12:0] reg2dp_datain_channel; +reg reg2dp_datain_format; +reg [12:0] reg2dp_datain_height; +reg [12:0] reg2dp_datain_height_ext; +reg reg2dp_datain_ram_type; +reg [12:0] reg2dp_datain_width; +reg [12:0] reg2dp_datain_width_ext; +reg reg2dp_dma_en; +reg [13:0] reg2dp_entries; +reg [11:0] reg2dp_grains; +reg [1:0] reg2dp_in_precision; +reg reg2dp_line_packed; +reg [31:0] reg2dp_line_stride; +reg [15:0] reg2dp_mean_ax; +reg [15:0] reg2dp_mean_bv; +reg reg2dp_mean_format; +reg [15:0] reg2dp_mean_gu; +reg [15:0] reg2dp_mean_ry; +reg reg2dp_nan_to_zero; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [5:0] reg2dp_pad_bottom; +reg [4:0] reg2dp_pad_left; +reg [5:0] reg2dp_pad_right; +reg [4:0] reg2dp_pad_top; +reg [15:0] reg2dp_pad_value; +reg [5:0] reg2dp_pixel_format; +reg reg2dp_pixel_mapping; +reg reg2dp_pixel_sign_override; +reg [4:0] reg2dp_pixel_x_offset; +reg [2:0] reg2dp_pixel_y_offset; +reg [1:0] reg2dp_proc_precision; +reg [2:0] reg2dp_rsv_height; +reg [9:0] reg2dp_rsv_per_line; +reg [9:0] reg2dp_rsv_per_uv_line; +reg [4:0] reg2dp_rsv_y_index; +reg reg2dp_skip_data_rls; +reg reg2dp_skip_weight_rls; +reg reg2dp_surf_packed; +reg [31:0] reg2dp_surf_stride; +reg [31:0] reg2dp_uv_line_stride; +reg [31:0] reg2dp_weight_addr_high; +reg [31:0] reg2dp_weight_addr_low; +reg [4:0] reg2dp_weight_bank; +reg [31:0] reg2dp_weight_bytes; +reg reg2dp_weight_format; +reg [12:0] reg2dp_weight_kernel; +reg reg2dp_weight_ram_type; +reg reg2dp_weight_reuse; +reg [31:0] reg2dp_wgs_addr_high; +reg [31:0] reg2dp_wgs_addr_low; +reg [31:0] reg2dp_wmb_addr_high; +reg [31:0] reg2dp_wmb_addr_low; +reg [27:0] reg2dp_wmb_bytes; +reg [62:0] req_pd; +reg req_pvld; +reg [7:0] slcg_op_en_d1; +reg [7:0] slcg_op_en_d2; +reg [7:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CDMA_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb_weight (reg2dp_arb_weight[3:0]) //|> o + ,.arb_wmb (reg2dp_arb_wmb[3:0]) //|> o + ,.producer (reg2dp_producer) //|> w + ,.flush_done (dp2reg_flush_done) //|< r + ,.consumer (dp2reg_consumer) //|< o + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CDMA_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_bank (reg2dp_d0_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d0_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d0_batches[4:0]) //|> w + ,.batch_stride (reg2dp_d0_batch_stride[31:0]) //|> w + ,.conv_x_stride (reg2dp_d0_conv_x_stride[2:0]) //|> w + ,.conv_y_stride (reg2dp_d0_conv_y_stride[2:0]) //|> w + ,.cvt_en (reg2dp_d0_cvt_en) //|> w + ,.cvt_truncate (reg2dp_d0_cvt_truncate[5:0]) //|> w + ,.cvt_offset (reg2dp_d0_cvt_offset[15:0]) //|> w + ,.cvt_scale (reg2dp_d0_cvt_scale[15:0]) //|> w + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.datain_addr_high_0 (reg2dp_d0_datain_addr_high_0[31:0]) //|> w + ,.datain_addr_high_1 (reg2dp_d0_datain_addr_high_1[31:0]) //|> w + ,.datain_addr_low_0 (reg2dp_d0_datain_addr_low_0[31:0]) //|> w + ,.datain_addr_low_1 (reg2dp_d0_datain_addr_low_1[31:0]) //|> w + ,.line_packed (reg2dp_d0_line_packed) //|> w + ,.surf_packed (reg2dp_d0_surf_packed) //|> w + ,.datain_ram_type (reg2dp_d0_datain_ram_type) //|> w + ,.datain_format (reg2dp_d0_datain_format) //|> w + ,.pixel_format (reg2dp_d0_pixel_format[5:0]) //|> w + ,.pixel_mapping (reg2dp_d0_pixel_mapping) //|> w + ,.pixel_sign_override (reg2dp_d0_pixel_sign_override) //|> w + ,.datain_height (reg2dp_d0_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d0_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d0_datain_channel[12:0]) //|> w + ,.datain_height_ext (reg2dp_d0_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d0_datain_width_ext[12:0]) //|> w + ,.entries (reg2dp_d0_entries[13:0]) //|> w + ,.grains (reg2dp_d0_grains[11:0]) //|> w + ,.line_stride (reg2dp_d0_line_stride[31:0]) //|> w + ,.uv_line_stride (reg2dp_d0_uv_line_stride[31:0]) //|> w + ,.mean_format (reg2dp_d0_mean_format) //|> w + ,.mean_gu (reg2dp_d0_mean_gu[15:0]) //|> w + ,.mean_ry (reg2dp_d0_mean_ry[15:0]) //|> w + ,.mean_ax (reg2dp_d0_mean_ax[15:0]) //|> w + ,.mean_bv (reg2dp_d0_mean_bv[15:0]) //|> w + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.data_reuse (reg2dp_d0_data_reuse) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d0_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d0_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d0_weight_reuse) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.pixel_x_offset (reg2dp_d0_pixel_x_offset[4:0]) //|> w + ,.pixel_y_offset (reg2dp_d0_pixel_y_offset[2:0]) //|> w + ,.rsv_per_line (reg2dp_d0_rsv_per_line[9:0]) //|> w + ,.rsv_per_uv_line (reg2dp_d0_rsv_per_uv_line[9:0]) //|> w + ,.rsv_height (reg2dp_d0_rsv_height[2:0]) //|> w + ,.rsv_y_index (reg2dp_d0_rsv_y_index[4:0]) //|> w + ,.surf_stride (reg2dp_d0_surf_stride[31:0]) //|> w + ,.weight_addr_high (reg2dp_d0_weight_addr_high[31:0]) //|> w + ,.weight_addr_low (reg2dp_d0_weight_addr_low[31:0]) //|> w + ,.weight_bytes (reg2dp_d0_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d0_weight_format) //|> w + ,.weight_ram_type (reg2dp_d0_weight_ram_type) //|> w + ,.byte_per_kernel (reg2dp_d0_byte_per_kernel[17:0]) //|> w + ,.weight_kernel (reg2dp_d0_weight_kernel[12:0]) //|> w + ,.wgs_addr_high (reg2dp_d0_wgs_addr_high[31:0]) //|> w + ,.wgs_addr_low (reg2dp_d0_wgs_addr_low[31:0]) //|> w + ,.wmb_addr_high (reg2dp_d0_wmb_addr_high[31:0]) //|> w + ,.wmb_addr_low (reg2dp_d0_wmb_addr_low[31:0]) //|> w + ,.wmb_bytes (reg2dp_d0_wmb_bytes[27:0]) //|> w + ,.pad_bottom (reg2dp_d0_pad_bottom[5:0]) //|> w + ,.pad_left (reg2dp_d0_pad_left[4:0]) //|> w + ,.pad_right (reg2dp_d0_pad_right[5:0]) //|> w + ,.pad_top (reg2dp_d0_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d0_pad_value[15:0]) //|> w + ,.inf_data_num (dp2reg_d0_inf_data_num[31:0]) //|< r + ,.inf_weight_num (dp2reg_d0_inf_weight_num[31:0]) //|< r + ,.nan_data_num (dp2reg_d0_nan_data_num[31:0]) //|< r + ,.nan_weight_num (dp2reg_d0_nan_weight_num[31:0]) //|< r + ,.op_en (reg2dp_d0_op_en) //|< r + ,.dat_rd_latency (dp2reg_d0_dat_rd_latency[31:0]) //|< r + ,.dat_rd_stall (dp2reg_d0_dat_rd_stall[31:0]) //|< r + ,.wt_rd_latency (dp2reg_d0_wt_rd_latency[31:0]) //|< r + ,.wt_rd_stall (dp2reg_d0_wt_rd_stall[31:0]) //|< r + ); +NV_NVDLA_CDMA_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_bank (reg2dp_d1_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d1_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d1_batches[4:0]) //|> w + ,.batch_stride (reg2dp_d1_batch_stride[31:0]) //|> w + ,.conv_x_stride (reg2dp_d1_conv_x_stride[2:0]) //|> w + ,.conv_y_stride (reg2dp_d1_conv_y_stride[2:0]) //|> w + ,.cvt_en (reg2dp_d1_cvt_en) //|> w + ,.cvt_truncate (reg2dp_d1_cvt_truncate[5:0]) //|> w + ,.cvt_offset (reg2dp_d1_cvt_offset[15:0]) //|> w + ,.cvt_scale (reg2dp_d1_cvt_scale[15:0]) //|> w + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.datain_addr_high_0 (reg2dp_d1_datain_addr_high_0[31:0]) //|> w + ,.datain_addr_high_1 (reg2dp_d1_datain_addr_high_1[31:0]) //|> w + ,.datain_addr_low_0 (reg2dp_d1_datain_addr_low_0[31:0]) //|> w + ,.datain_addr_low_1 (reg2dp_d1_datain_addr_low_1[31:0]) //|> w + ,.line_packed (reg2dp_d1_line_packed) //|> w + ,.surf_packed (reg2dp_d1_surf_packed) //|> w + ,.datain_ram_type (reg2dp_d1_datain_ram_type) //|> w + ,.datain_format (reg2dp_d1_datain_format) //|> w + ,.pixel_format (reg2dp_d1_pixel_format[5:0]) //|> w + ,.pixel_mapping (reg2dp_d1_pixel_mapping) //|> w + ,.pixel_sign_override (reg2dp_d1_pixel_sign_override) //|> w + ,.datain_height (reg2dp_d1_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d1_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d1_datain_channel[12:0]) //|> w + ,.datain_height_ext (reg2dp_d1_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d1_datain_width_ext[12:0]) //|> w + ,.entries (reg2dp_d1_entries[13:0]) //|> w + ,.grains (reg2dp_d1_grains[11:0]) //|> w + ,.line_stride (reg2dp_d1_line_stride[31:0]) //|> w + ,.uv_line_stride (reg2dp_d1_uv_line_stride[31:0]) //|> w + ,.mean_format (reg2dp_d1_mean_format) //|> w + ,.mean_gu (reg2dp_d1_mean_gu[15:0]) //|> w + ,.mean_ry (reg2dp_d1_mean_ry[15:0]) //|> w + ,.mean_ax (reg2dp_d1_mean_ax[15:0]) //|> w + ,.mean_bv (reg2dp_d1_mean_bv[15:0]) //|> w + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.data_reuse (reg2dp_d1_data_reuse) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d1_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d1_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d1_weight_reuse) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.pixel_x_offset (reg2dp_d1_pixel_x_offset[4:0]) //|> w + ,.pixel_y_offset (reg2dp_d1_pixel_y_offset[2:0]) //|> w + ,.rsv_per_line (reg2dp_d1_rsv_per_line[9:0]) //|> w + ,.rsv_per_uv_line (reg2dp_d1_rsv_per_uv_line[9:0]) //|> w + ,.rsv_height (reg2dp_d1_rsv_height[2:0]) //|> w + ,.rsv_y_index (reg2dp_d1_rsv_y_index[4:0]) //|> w + ,.surf_stride (reg2dp_d1_surf_stride[31:0]) //|> w + ,.weight_addr_high (reg2dp_d1_weight_addr_high[31:0]) //|> w + ,.weight_addr_low (reg2dp_d1_weight_addr_low[31:0]) //|> w + ,.weight_bytes (reg2dp_d1_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d1_weight_format) //|> w + ,.weight_ram_type (reg2dp_d1_weight_ram_type) //|> w + ,.byte_per_kernel (reg2dp_d1_byte_per_kernel[17:0]) //|> w + ,.weight_kernel (reg2dp_d1_weight_kernel[12:0]) //|> w + ,.wgs_addr_high (reg2dp_d1_wgs_addr_high[31:0]) //|> w + ,.wgs_addr_low (reg2dp_d1_wgs_addr_low[31:0]) //|> w + ,.wmb_addr_high (reg2dp_d1_wmb_addr_high[31:0]) //|> w + ,.wmb_addr_low (reg2dp_d1_wmb_addr_low[31:0]) //|> w + ,.wmb_bytes (reg2dp_d1_wmb_bytes[27:0]) //|> w + ,.pad_bottom (reg2dp_d1_pad_bottom[5:0]) //|> w + ,.pad_left (reg2dp_d1_pad_left[4:0]) //|> w + ,.pad_right (reg2dp_d1_pad_right[5:0]) //|> w + ,.pad_top (reg2dp_d1_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d1_pad_value[15:0]) //|> w + ,.inf_data_num (dp2reg_d1_inf_data_num[31:0]) //|< r + ,.inf_weight_num (dp2reg_d1_inf_weight_num[31:0]) //|< r + ,.nan_data_num (dp2reg_d1_nan_data_num[31:0]) //|< r + ,.nan_weight_num (dp2reg_d1_nan_weight_num[31:0]) //|< r + ,.op_en (reg2dp_d1_op_en) //|< r + ,.dat_rd_latency (dp2reg_d1_dat_rd_latency[31:0]) //|< r + ,.dat_rd_stall (dp2reg_d1_dat_rd_stall[31:0]) //|< r + ,.wt_rd_latency (dp2reg_d1_wt_rd_latency[31:0]) //|< r + ,.wt_rd_stall (dp2reg_d1_wt_rd_stall[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {8{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {8{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {8{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {8{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h5010 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h5010 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h5010 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cdma_req_pvld) == 1'b1) begin + req_pd <= csb2cdma_req_pd; +// VCS coverage off + end else if ((csb2cdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2csb_resp_valid <= 1'b0; + end else begin + cdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_data_bank + or reg2dp_d0_data_bank + ) begin + reg2dp_data_bank = dp2reg_consumer ? reg2dp_d1_data_bank : reg2dp_d0_data_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bank + or reg2dp_d0_weight_bank + ) begin + reg2dp_weight_bank = dp2reg_consumer ? reg2dp_d1_weight_bank : reg2dp_d0_weight_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_batches + or reg2dp_d0_batches + ) begin + reg2dp_batches = dp2reg_consumer ? reg2dp_d1_batches : reg2dp_d0_batches; +end +always @( + dp2reg_consumer + or reg2dp_d1_batch_stride + or reg2dp_d0_batch_stride + ) begin + reg2dp_batch_stride = dp2reg_consumer ? reg2dp_d1_batch_stride : reg2dp_d0_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_x_stride + or reg2dp_d0_conv_x_stride + ) begin + reg2dp_conv_x_stride = dp2reg_consumer ? reg2dp_d1_conv_x_stride : reg2dp_d0_conv_x_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_y_stride + or reg2dp_d0_conv_y_stride + ) begin + reg2dp_conv_y_stride = dp2reg_consumer ? reg2dp_d1_conv_y_stride : reg2dp_d0_conv_y_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_en + or reg2dp_d0_cvt_en + ) begin + reg2dp_cvt_en = dp2reg_consumer ? reg2dp_d1_cvt_en : reg2dp_d0_cvt_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_truncate + or reg2dp_d0_cvt_truncate + ) begin + reg2dp_cvt_truncate = dp2reg_consumer ? reg2dp_d1_cvt_truncate : reg2dp_d0_cvt_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_offset + or reg2dp_d0_cvt_offset + ) begin + reg2dp_cvt_offset = dp2reg_consumer ? reg2dp_d1_cvt_offset : reg2dp_d0_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_scale + or reg2dp_d0_cvt_scale + ) begin + reg2dp_cvt_scale = dp2reg_consumer ? reg2dp_d1_cvt_scale : reg2dp_d0_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_high_0 + or reg2dp_d0_datain_addr_high_0 + ) begin + reg2dp_datain_addr_high_0 = dp2reg_consumer ? reg2dp_d1_datain_addr_high_0 : reg2dp_d0_datain_addr_high_0; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_high_1 + or reg2dp_d0_datain_addr_high_1 + ) begin + reg2dp_datain_addr_high_1 = dp2reg_consumer ? reg2dp_d1_datain_addr_high_1 : reg2dp_d0_datain_addr_high_1; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_low_0 + or reg2dp_d0_datain_addr_low_0 + ) begin + reg2dp_datain_addr_low_0 = dp2reg_consumer ? reg2dp_d1_datain_addr_low_0 : reg2dp_d0_datain_addr_low_0; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_addr_low_1 + or reg2dp_d0_datain_addr_low_1 + ) begin + reg2dp_datain_addr_low_1 = dp2reg_consumer ? reg2dp_d1_datain_addr_low_1 : reg2dp_d0_datain_addr_low_1; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_packed + or reg2dp_d0_line_packed + ) begin + reg2dp_line_packed = dp2reg_consumer ? reg2dp_d1_line_packed : reg2dp_d0_line_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_packed + or reg2dp_d0_surf_packed + ) begin + reg2dp_surf_packed = dp2reg_consumer ? reg2dp_d1_surf_packed : reg2dp_d0_surf_packed; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_ram_type + or reg2dp_d0_datain_ram_type + ) begin + reg2dp_datain_ram_type = dp2reg_consumer ? reg2dp_d1_datain_ram_type : reg2dp_d0_datain_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_format + or reg2dp_d0_datain_format + ) begin + reg2dp_datain_format = dp2reg_consumer ? reg2dp_d1_datain_format : reg2dp_d0_datain_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_format + or reg2dp_d0_pixel_format + ) begin + reg2dp_pixel_format = dp2reg_consumer ? reg2dp_d1_pixel_format : reg2dp_d0_pixel_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_mapping + or reg2dp_d0_pixel_mapping + ) begin + reg2dp_pixel_mapping = dp2reg_consumer ? reg2dp_d1_pixel_mapping : reg2dp_d0_pixel_mapping; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_sign_override + or reg2dp_d0_pixel_sign_override + ) begin + reg2dp_pixel_sign_override = dp2reg_consumer ? reg2dp_d1_pixel_sign_override : reg2dp_d0_pixel_sign_override; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height + or reg2dp_d0_datain_height + ) begin + reg2dp_datain_height = dp2reg_consumer ? reg2dp_d1_datain_height : reg2dp_d0_datain_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width + or reg2dp_d0_datain_width + ) begin + reg2dp_datain_width = dp2reg_consumer ? reg2dp_d1_datain_width : reg2dp_d0_datain_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_channel + or reg2dp_d0_datain_channel + ) begin + reg2dp_datain_channel = dp2reg_consumer ? reg2dp_d1_datain_channel : reg2dp_d0_datain_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height_ext + or reg2dp_d0_datain_height_ext + ) begin + reg2dp_datain_height_ext = dp2reg_consumer ? reg2dp_d1_datain_height_ext : reg2dp_d0_datain_height_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width_ext + or reg2dp_d0_datain_width_ext + ) begin + reg2dp_datain_width_ext = dp2reg_consumer ? reg2dp_d1_datain_width_ext : reg2dp_d0_datain_width_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_entries + or reg2dp_d0_entries + ) begin + reg2dp_entries = dp2reg_consumer ? reg2dp_d1_entries : reg2dp_d0_entries; +end +always @( + dp2reg_consumer + or reg2dp_d1_grains + or reg2dp_d0_grains + ) begin + reg2dp_grains = dp2reg_consumer ? reg2dp_d1_grains : reg2dp_d0_grains; +end +always @( + dp2reg_consumer + or reg2dp_d1_line_stride + or reg2dp_d0_line_stride + ) begin + reg2dp_line_stride = dp2reg_consumer ? reg2dp_d1_line_stride : reg2dp_d0_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_uv_line_stride + or reg2dp_d0_uv_line_stride + ) begin + reg2dp_uv_line_stride = dp2reg_consumer ? reg2dp_d1_uv_line_stride : reg2dp_d0_uv_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_format + or reg2dp_d0_mean_format + ) begin + reg2dp_mean_format = dp2reg_consumer ? reg2dp_d1_mean_format : reg2dp_d0_mean_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_gu + or reg2dp_d0_mean_gu + ) begin + reg2dp_mean_gu = dp2reg_consumer ? reg2dp_d1_mean_gu : reg2dp_d0_mean_gu; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_ry + or reg2dp_d0_mean_ry + ) begin + reg2dp_mean_ry = dp2reg_consumer ? reg2dp_d1_mean_ry : reg2dp_d0_mean_ry; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_ax + or reg2dp_d0_mean_ax + ) begin + reg2dp_mean_ax = dp2reg_consumer ? reg2dp_d1_mean_ax : reg2dp_d0_mean_ax; +end +always @( + dp2reg_consumer + or reg2dp_d1_mean_bv + or reg2dp_d0_mean_bv + ) begin + reg2dp_mean_bv = dp2reg_consumer ? reg2dp_d1_mean_bv : reg2dp_d0_mean_bv; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_data_reuse + or reg2dp_d0_data_reuse + ) begin + reg2dp_data_reuse = dp2reg_consumer ? reg2dp_d1_data_reuse : reg2dp_d0_data_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_data_rls + or reg2dp_d0_skip_data_rls + ) begin + reg2dp_skip_data_rls = dp2reg_consumer ? reg2dp_d1_skip_data_rls : reg2dp_d0_skip_data_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_weight_rls + or reg2dp_d0_skip_weight_rls + ) begin + reg2dp_skip_weight_rls = dp2reg_consumer ? reg2dp_d1_skip_weight_rls : reg2dp_d0_skip_weight_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_reuse + or reg2dp_d0_weight_reuse + ) begin + reg2dp_weight_reuse = dp2reg_consumer ? reg2dp_d1_weight_reuse : reg2dp_d0_weight_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_x_offset + or reg2dp_d0_pixel_x_offset + ) begin + reg2dp_pixel_x_offset = dp2reg_consumer ? reg2dp_d1_pixel_x_offset : reg2dp_d0_pixel_x_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_pixel_y_offset + or reg2dp_d0_pixel_y_offset + ) begin + reg2dp_pixel_y_offset = dp2reg_consumer ? reg2dp_d1_pixel_y_offset : reg2dp_d0_pixel_y_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_per_line + or reg2dp_d0_rsv_per_line + ) begin + reg2dp_rsv_per_line = dp2reg_consumer ? reg2dp_d1_rsv_per_line : reg2dp_d0_rsv_per_line; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_per_uv_line + or reg2dp_d0_rsv_per_uv_line + ) begin + reg2dp_rsv_per_uv_line = dp2reg_consumer ? reg2dp_d1_rsv_per_uv_line : reg2dp_d0_rsv_per_uv_line; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_height + or reg2dp_d0_rsv_height + ) begin + reg2dp_rsv_height = dp2reg_consumer ? reg2dp_d1_rsv_height : reg2dp_d0_rsv_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_rsv_y_index + or reg2dp_d0_rsv_y_index + ) begin + reg2dp_rsv_y_index = dp2reg_consumer ? reg2dp_d1_rsv_y_index : reg2dp_d0_rsv_y_index; +end +always @( + dp2reg_consumer + or reg2dp_d1_surf_stride + or reg2dp_d0_surf_stride + ) begin + reg2dp_surf_stride = dp2reg_consumer ? reg2dp_d1_surf_stride : reg2dp_d0_surf_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_addr_high + or reg2dp_d0_weight_addr_high + ) begin + reg2dp_weight_addr_high = dp2reg_consumer ? reg2dp_d1_weight_addr_high : reg2dp_d0_weight_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_addr_low + or reg2dp_d0_weight_addr_low + ) begin + reg2dp_weight_addr_low = dp2reg_consumer ? reg2dp_d1_weight_addr_low : reg2dp_d0_weight_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bytes + or reg2dp_d0_weight_bytes + ) begin + reg2dp_weight_bytes = dp2reg_consumer ? reg2dp_d1_weight_bytes : reg2dp_d0_weight_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_format + or reg2dp_d0_weight_format + ) begin + reg2dp_weight_format = dp2reg_consumer ? reg2dp_d1_weight_format : reg2dp_d0_weight_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_ram_type + or reg2dp_d0_weight_ram_type + ) begin + reg2dp_weight_ram_type = dp2reg_consumer ? reg2dp_d1_weight_ram_type : reg2dp_d0_weight_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_byte_per_kernel + or reg2dp_d0_byte_per_kernel + ) begin + reg2dp_byte_per_kernel = dp2reg_consumer ? reg2dp_d1_byte_per_kernel : reg2dp_d0_byte_per_kernel; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_kernel + or reg2dp_d0_weight_kernel + ) begin + reg2dp_weight_kernel = dp2reg_consumer ? reg2dp_d1_weight_kernel : reg2dp_d0_weight_kernel; +end +always @( + dp2reg_consumer + or reg2dp_d1_wgs_addr_high + or reg2dp_d0_wgs_addr_high + ) begin + reg2dp_wgs_addr_high = dp2reg_consumer ? reg2dp_d1_wgs_addr_high : reg2dp_d0_wgs_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_wgs_addr_low + or reg2dp_d0_wgs_addr_low + ) begin + reg2dp_wgs_addr_low = dp2reg_consumer ? reg2dp_d1_wgs_addr_low : reg2dp_d0_wgs_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_addr_high + or reg2dp_d0_wmb_addr_high + ) begin + reg2dp_wmb_addr_high = dp2reg_consumer ? reg2dp_d1_wmb_addr_high : reg2dp_d0_wmb_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_addr_low + or reg2dp_d0_wmb_addr_low + ) begin + reg2dp_wmb_addr_low = dp2reg_consumer ? reg2dp_d1_wmb_addr_low : reg2dp_d0_wmb_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_bytes + or reg2dp_d0_wmb_bytes + ) begin + reg2dp_wmb_bytes = dp2reg_consumer ? reg2dp_d1_wmb_bytes : reg2dp_d0_wmb_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_bottom + or reg2dp_d0_pad_bottom + ) begin + reg2dp_pad_bottom = dp2reg_consumer ? reg2dp_d1_pad_bottom : reg2dp_d0_pad_bottom; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_left + or reg2dp_d0_pad_left + ) begin + reg2dp_pad_left = dp2reg_consumer ? reg2dp_d1_pad_left : reg2dp_d0_pad_left; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_right + or reg2dp_d0_pad_right + ) begin + reg2dp_pad_right = dp2reg_consumer ? reg2dp_d1_pad_right : reg2dp_d0_pad_right; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_top + or reg2dp_d0_pad_top + ) begin + reg2dp_pad_top = dp2reg_consumer ? reg2dp_d1_pad_top : reg2dp_d0_pad_top; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value + or reg2dp_d0_pad_value + ) begin + reg2dp_pad_value = dp2reg_consumer ? reg2dp_d1_pad_value : reg2dp_d0_pad_value; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// for interrupt // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// for cbuf flushing logic // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_flush_done <= 1'b0; + end else begin + dp2reg_flush_done <= dp2reg_wt_flush_done & dp2reg_dat_flush_done; + end +end +//////////////////////////////////////////////////////////////////////// +// for general counting register // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////////////////////////////////////////////////////////////////////// +// for NaN and infinity counting registers // +//////////////////////////////////////////////////////////////////////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_nan_weight_num + or dp2reg_d0_clr + or dp2reg_d0_nan_weight_num + ) begin + dp2reg_d0_nan_weight_num_w = (dp2reg_d0_set) ? dp2reg_nan_weight_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_weight_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_weight_num + or dp2reg_d0_clr + or dp2reg_d0_inf_weight_num + ) begin + dp2reg_d0_inf_weight_num_w = (dp2reg_d0_set) ? dp2reg_inf_weight_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_weight_num; +end +always @( + dp2reg_d0_set + or dp2reg_nan_data_num + or dp2reg_d0_clr + or dp2reg_d0_nan_data_num + ) begin + dp2reg_d0_nan_data_num_w = (dp2reg_d0_set) ? dp2reg_nan_data_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_data_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_data_num + or dp2reg_d0_clr + or dp2reg_d0_inf_data_num + ) begin + dp2reg_d0_inf_data_num_w = (dp2reg_d0_set) ? dp2reg_inf_data_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_data_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_weight_num <= dp2reg_d0_nan_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_weight_num <= dp2reg_d0_inf_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_data_num <= dp2reg_d0_nan_data_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_data_num <= dp2reg_d0_inf_data_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_nan_weight_num + or dp2reg_d1_clr + or dp2reg_d1_nan_weight_num + ) begin + dp2reg_d1_nan_weight_num_w = (dp2reg_d1_set) ? dp2reg_nan_weight_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_weight_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_weight_num + or dp2reg_d1_clr + or dp2reg_d1_inf_weight_num + ) begin + dp2reg_d1_inf_weight_num_w = (dp2reg_d1_set) ? dp2reg_inf_weight_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_weight_num; +end +always @( + dp2reg_d1_set + or dp2reg_nan_data_num + or dp2reg_d1_clr + or dp2reg_d1_nan_data_num + ) begin + dp2reg_d1_nan_data_num_w = (dp2reg_d1_set) ? dp2reg_nan_data_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_data_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_data_num + or dp2reg_d1_clr + or dp2reg_d1_inf_data_num + ) begin + dp2reg_d1_inf_data_num_w = (dp2reg_d1_set) ? dp2reg_inf_data_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_data_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_weight_num <= dp2reg_d1_nan_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_weight_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_weight_num <= dp2reg_d1_inf_weight_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_weight_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_data_num <= dp2reg_d1_nan_data_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_data_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_data_num <= dp2reg_d1_inf_data_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_data_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// for perf conting registers // +//////////////////////////////////////////////////////////////////////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_wt_rd_stall + or dp2reg_d0_clr + or dp2reg_d0_wt_rd_stall + ) begin + dp2reg_d0_wt_rd_stall_w = (dp2reg_d0_set) ? dp2reg_wt_rd_stall : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_wt_rd_stall; +end +always @( + dp2reg_d0_set + or dp2reg_wt_rd_latency + or dp2reg_d0_clr + or dp2reg_d0_wt_rd_latency + ) begin + dp2reg_d0_wt_rd_latency_w = (dp2reg_d0_set) ? dp2reg_wt_rd_latency : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_wt_rd_latency; +end +always @( + dp2reg_d0_set + or dp2reg_dc_rd_stall + or dp2reg_wg_rd_stall + or dp2reg_img_rd_stall + or dp2reg_d0_clr + or dp2reg_d0_dat_rd_stall + ) begin + dp2reg_d0_dat_rd_stall_w = (dp2reg_d0_set) ? (dp2reg_dc_rd_stall | dp2reg_wg_rd_stall | dp2reg_img_rd_stall) : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_dat_rd_stall; +end +always @( + dp2reg_d0_set + or dp2reg_dc_rd_latency + or dp2reg_wg_rd_latency + or dp2reg_img_rd_latency + or dp2reg_d0_clr + or dp2reg_d0_dat_rd_latency + ) begin + dp2reg_d0_dat_rd_latency_w = (dp2reg_d0_set) ? (dp2reg_dc_rd_latency | dp2reg_wg_rd_latency | dp2reg_img_rd_latency) : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_dat_rd_latency; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wt_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_wt_rd_stall <= dp2reg_d0_wt_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_wt_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wt_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_wt_rd_latency <= dp2reg_d0_wt_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_wt_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_dat_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_dat_rd_stall <= dp2reg_d0_dat_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_dat_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_dat_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_dat_rd_latency <= dp2reg_d0_dat_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_dat_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_wt_rd_stall + or dp2reg_d1_clr + or dp2reg_d1_wt_rd_stall + ) begin + dp2reg_d1_wt_rd_stall_w = (dp2reg_d1_set) ? dp2reg_wt_rd_stall : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_wt_rd_stall; +end +always @( + dp2reg_d1_set + or dp2reg_wt_rd_latency + or dp2reg_d1_clr + or dp2reg_d1_wt_rd_latency + ) begin + dp2reg_d1_wt_rd_latency_w = (dp2reg_d1_set) ? dp2reg_wt_rd_latency : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_wt_rd_latency; +end +always @( + dp2reg_d1_set + or dp2reg_dc_rd_stall + or dp2reg_wg_rd_stall + or dp2reg_img_rd_stall + or dp2reg_d1_clr + or dp2reg_d1_dat_rd_stall + ) begin + dp2reg_d1_dat_rd_stall_w = (dp2reg_d1_set) ? (dp2reg_dc_rd_stall | dp2reg_wg_rd_stall | dp2reg_img_rd_stall) : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_dat_rd_stall; +end +always @( + dp2reg_d1_set + or dp2reg_dc_rd_latency + or dp2reg_wg_rd_latency + or dp2reg_img_rd_latency + or dp2reg_d1_clr + or dp2reg_d1_dat_rd_latency + ) begin + dp2reg_d1_dat_rd_latency_w = (dp2reg_d1_set) ? (dp2reg_dc_rd_latency | dp2reg_wg_rd_latency | dp2reg_img_rd_latency) : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_dat_rd_latency; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wt_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_wt_rd_stall <= dp2reg_d1_wt_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_wt_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wt_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_wt_rd_latency <= dp2reg_d1_wt_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_wt_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_dat_rd_stall <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_dat_rd_stall <= dp2reg_d1_dat_rd_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_dat_rd_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_dat_rd_latency <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_dat_rd_latency <= dp2reg_d1_dat_rd_latency_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_dat_rd_latency <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v new file mode 100644 index 0000000..c4c972b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v @@ -0,0 +1,2187 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_shared_buffer.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_shared_buffer ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dc2sbuf_p0_wr_en //|< i + ,dc2sbuf_p0_wr_addr //|< i + ,dc2sbuf_p0_wr_data //|< i + ,dc2sbuf_p1_wr_en //|< i + ,dc2sbuf_p1_wr_addr //|< i + ,dc2sbuf_p1_wr_data //|< i + ,img2sbuf_p0_wr_en //|< i + ,img2sbuf_p0_wr_addr //|< i + ,img2sbuf_p0_wr_data //|< i + ,img2sbuf_p1_wr_en //|< i + ,img2sbuf_p1_wr_addr //|< i + ,img2sbuf_p1_wr_data //|< i + ,dc2sbuf_p0_rd_en //|< i + ,dc2sbuf_p0_rd_addr //|< i + ,dc2sbuf_p0_rd_data //|> o + ,dc2sbuf_p1_rd_en //|< i + ,dc2sbuf_p1_rd_addr //|< i + ,dc2sbuf_p1_rd_data //|> o + ,img2sbuf_p0_rd_en //|< i + ,img2sbuf_p0_rd_addr //|< i + ,img2sbuf_p0_rd_data //|> o + ,img2sbuf_p1_rd_en //|< i + ,img2sbuf_p1_rd_addr //|< i + ,img2sbuf_p1_rd_data //|> o + ); +// +// NV_NVDLA_CDMA_shared_buffer_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dc2sbuf_p0_wr_en; /* data valid */ +input [7:0] dc2sbuf_p0_wr_addr; +input [8*8 -1:0] dc2sbuf_p0_wr_data; +input dc2sbuf_p1_wr_en; /* data valid */ +input [7:0] dc2sbuf_p1_wr_addr; +input [8*8 -1:0] dc2sbuf_p1_wr_data; +input img2sbuf_p0_wr_en; /* data valid */ +input [7:0] img2sbuf_p0_wr_addr; +input [8*8 -1:0] img2sbuf_p0_wr_data; +input img2sbuf_p1_wr_en; /* data valid */ +input [7:0] img2sbuf_p1_wr_addr; +input [8*8 -1:0] img2sbuf_p1_wr_data; +input dc2sbuf_p0_rd_en; /* data valid */ +input [7:0] dc2sbuf_p0_rd_addr; +output [8*8 -1:0] dc2sbuf_p0_rd_data; +input dc2sbuf_p1_rd_en; /* data valid */ +input [7:0] dc2sbuf_p1_rd_addr; +output [8*8 -1:0] dc2sbuf_p1_rd_data; +input img2sbuf_p0_rd_en; /* data valid */ +input [7:0] img2sbuf_p0_rd_addr; +output [8*8 -1:0] img2sbuf_p0_rd_data; +input img2sbuf_p1_rd_en; /* data valid */ +input [7:0] img2sbuf_p1_rd_addr; +output [8*8 -1:0] img2sbuf_p1_rd_data; +////////////// +// REGS // +////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $b0; +//: my $val; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($k = 0; $k < 2; $k ++) { +//: print qq(reg sbuf_p${k}_re_${serial}_norm_d1;\n); +//: } +//: } +//: $b0 = 8*8 - 1; +//: for($k = 0; $k < 2; $k ++) { +//: print qq(reg [${b0}:0] sbuf_p${k}_rdat_d2;\n); +//: print qq(reg sbuf_p${k}_rd_en_d1;\n); +//: } +//: if($def_wino) { +//: for($j = 0; $j < 16/4; $j ++) { +//: $val = sprintf("%02d", $j); +//: for($k = 0; $k < 2; $k ++) { +//: print qq(reg sbuf_p${k}_re_${val}_wg_d1;\n); +//: } +//: } +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq(reg sbuf_p${k}_wg_sel_q${i}_d1;\n); +//: } +//: } +//: } +//: print qq (\n\n); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg sbuf_p0_re_00_norm_d1; +reg sbuf_p1_re_00_norm_d1; +reg sbuf_p0_re_01_norm_d1; +reg sbuf_p1_re_01_norm_d1; +reg sbuf_p0_re_02_norm_d1; +reg sbuf_p1_re_02_norm_d1; +reg sbuf_p0_re_03_norm_d1; +reg sbuf_p1_re_03_norm_d1; +reg sbuf_p0_re_04_norm_d1; +reg sbuf_p1_re_04_norm_d1; +reg sbuf_p0_re_05_norm_d1; +reg sbuf_p1_re_05_norm_d1; +reg sbuf_p0_re_06_norm_d1; +reg sbuf_p1_re_06_norm_d1; +reg sbuf_p0_re_07_norm_d1; +reg sbuf_p1_re_07_norm_d1; +reg sbuf_p0_re_08_norm_d1; +reg sbuf_p1_re_08_norm_d1; +reg sbuf_p0_re_09_norm_d1; +reg sbuf_p1_re_09_norm_d1; +reg sbuf_p0_re_10_norm_d1; +reg sbuf_p1_re_10_norm_d1; +reg sbuf_p0_re_11_norm_d1; +reg sbuf_p1_re_11_norm_d1; +reg sbuf_p0_re_12_norm_d1; +reg sbuf_p1_re_12_norm_d1; +reg sbuf_p0_re_13_norm_d1; +reg sbuf_p1_re_13_norm_d1; +reg sbuf_p0_re_14_norm_d1; +reg sbuf_p1_re_14_norm_d1; +reg sbuf_p0_re_15_norm_d1; +reg sbuf_p1_re_15_norm_d1; +reg [63:0] sbuf_p0_rdat_d2; +reg sbuf_p0_rd_en_d1; +reg [63:0] sbuf_p1_rdat_d2; +reg sbuf_p1_rd_en_d1; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////// +// WIRES // +////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $b0; +//: my $val; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: $b0 = int(log(16)/log(2)) - 1; +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq ( +//: wire [${b0}:0] ${name}2sbuf_p0_wr_bsel; +//: wire [${b0}:0] ${name}2sbuf_p1_wr_bsel;\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (wire ${name}2sbuf_p${k}_wr_sel_${serial};\n); +//: } +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (wire sbuf_we_${serial};\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: print qq (wire [${b0}:0] sbuf_wa_${serial};\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $b0 = 8*8 - 1; +//: print qq (wire [${b0}:0] sbuf_wdat_${serial};\n); +//: } +//: $b0 = int(log(16)/log(2)) - 1; +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: wire [${b0}:0] ${name}2sbuf_p0_rd_bsel; +//: wire [${b0}:0] ${name}2sbuf_p1_rd_bsel;\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($i = 0; $i < @input_list_1; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list_1[$i]; +//: print qq (wire ${name}2sbuf_p${k}_rd_sel_${serial};\n); +//: } +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (wire sbuf_p${k}_re_${serial};\n); +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (wire sbuf_re_${serial};\n); +//: } +//: $b0 = 8*8 - 1; +//: for($i = 0; $i < 16; $i ++) { +//: $serial = sprintf("%02d", $i); +//: print qq (wire [${b0}:0] sbuf_rdat_${serial};\n); +//: } +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: wire [${b0}:0] ${name}2sbuf_p0_rd_esel; +//: wire [${b0}:0] ${name}2sbuf_p1_rd_esel;\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: print qq (wire [${b0}:0] sbuf_ra_${serial};\n); +//: } +//: $b0 = 8*8 - 1; +//: for($k = 0; $k < 2; $k ++) { +//: print qq (wire [${b0}:0] sbuf_p${k}_norm_rdat;\n); +//: } +//: for($k = 0; $k < 2; $k ++) { +//: print qq (wire [${b0}:0] sbuf_p${k}_rdat;\n); +//: } +//: if($def_wino) { +//: $b0 = int(log(16)/log(2)) - 3; +//: print qq ( +//: wire [${b0}:0] wg2sbuf_p0_rd_bsel; +//: wire [${b0}:0] wg2sbuf_p1_rd_bsel;\n); +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $i = int($j/4); +//: for($k = 0; $k < 2; $k ++) { +//: print qq (wire wg2sbuf_p${k}_rd_sel_${serial};\n); +//: } +//: } +//: +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: print qq ( +//: wire [${b0}:0] wg2sbuf_p0_rd_esel; +//: wire [${b0}:0] wg2sbuf_p1_rd_esel;\n); +//: $b0 = 8*8 - 1; +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq (wire [${b0}:0] sbuf_p${k}_wg_rdat_src_${i};\n); +//: } +//: } +//: for($k = 0; $k < 2; $k ++) { +//: print qq(wire [${b0}:0] sbuf_p${k}_wg_rdat;\n); +//: } +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq(wire sbuf_p${k}_wg_sel_q${i};\n); +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [3:0] dc2sbuf_p0_wr_bsel; +wire [3:0] dc2sbuf_p1_wr_bsel; + +wire [3:0] img2sbuf_p0_wr_bsel; +wire [3:0] img2sbuf_p1_wr_bsel; +wire dc2sbuf_p0_wr_sel_00; +wire dc2sbuf_p1_wr_sel_00; +wire img2sbuf_p0_wr_sel_00; +wire img2sbuf_p1_wr_sel_00; +wire dc2sbuf_p0_wr_sel_01; +wire dc2sbuf_p1_wr_sel_01; +wire img2sbuf_p0_wr_sel_01; +wire img2sbuf_p1_wr_sel_01; +wire dc2sbuf_p0_wr_sel_02; +wire dc2sbuf_p1_wr_sel_02; +wire img2sbuf_p0_wr_sel_02; +wire img2sbuf_p1_wr_sel_02; +wire dc2sbuf_p0_wr_sel_03; +wire dc2sbuf_p1_wr_sel_03; +wire img2sbuf_p0_wr_sel_03; +wire img2sbuf_p1_wr_sel_03; +wire dc2sbuf_p0_wr_sel_04; +wire dc2sbuf_p1_wr_sel_04; +wire img2sbuf_p0_wr_sel_04; +wire img2sbuf_p1_wr_sel_04; +wire dc2sbuf_p0_wr_sel_05; +wire dc2sbuf_p1_wr_sel_05; +wire img2sbuf_p0_wr_sel_05; +wire img2sbuf_p1_wr_sel_05; +wire dc2sbuf_p0_wr_sel_06; +wire dc2sbuf_p1_wr_sel_06; +wire img2sbuf_p0_wr_sel_06; +wire img2sbuf_p1_wr_sel_06; +wire dc2sbuf_p0_wr_sel_07; +wire dc2sbuf_p1_wr_sel_07; +wire img2sbuf_p0_wr_sel_07; +wire img2sbuf_p1_wr_sel_07; +wire dc2sbuf_p0_wr_sel_08; +wire dc2sbuf_p1_wr_sel_08; +wire img2sbuf_p0_wr_sel_08; +wire img2sbuf_p1_wr_sel_08; +wire dc2sbuf_p0_wr_sel_09; +wire dc2sbuf_p1_wr_sel_09; +wire img2sbuf_p0_wr_sel_09; +wire img2sbuf_p1_wr_sel_09; +wire dc2sbuf_p0_wr_sel_10; +wire dc2sbuf_p1_wr_sel_10; +wire img2sbuf_p0_wr_sel_10; +wire img2sbuf_p1_wr_sel_10; +wire dc2sbuf_p0_wr_sel_11; +wire dc2sbuf_p1_wr_sel_11; +wire img2sbuf_p0_wr_sel_11; +wire img2sbuf_p1_wr_sel_11; +wire dc2sbuf_p0_wr_sel_12; +wire dc2sbuf_p1_wr_sel_12; +wire img2sbuf_p0_wr_sel_12; +wire img2sbuf_p1_wr_sel_12; +wire dc2sbuf_p0_wr_sel_13; +wire dc2sbuf_p1_wr_sel_13; +wire img2sbuf_p0_wr_sel_13; +wire img2sbuf_p1_wr_sel_13; +wire dc2sbuf_p0_wr_sel_14; +wire dc2sbuf_p1_wr_sel_14; +wire img2sbuf_p0_wr_sel_14; +wire img2sbuf_p1_wr_sel_14; +wire dc2sbuf_p0_wr_sel_15; +wire dc2sbuf_p1_wr_sel_15; +wire img2sbuf_p0_wr_sel_15; +wire img2sbuf_p1_wr_sel_15; +wire sbuf_we_00; +wire sbuf_we_01; +wire sbuf_we_02; +wire sbuf_we_03; +wire sbuf_we_04; +wire sbuf_we_05; +wire sbuf_we_06; +wire sbuf_we_07; +wire sbuf_we_08; +wire sbuf_we_09; +wire sbuf_we_10; +wire sbuf_we_11; +wire sbuf_we_12; +wire sbuf_we_13; +wire sbuf_we_14; +wire sbuf_we_15; +wire [3:0] sbuf_wa_00; +wire [3:0] sbuf_wa_01; +wire [3:0] sbuf_wa_02; +wire [3:0] sbuf_wa_03; +wire [3:0] sbuf_wa_04; +wire [3:0] sbuf_wa_05; +wire [3:0] sbuf_wa_06; +wire [3:0] sbuf_wa_07; +wire [3:0] sbuf_wa_08; +wire [3:0] sbuf_wa_09; +wire [3:0] sbuf_wa_10; +wire [3:0] sbuf_wa_11; +wire [3:0] sbuf_wa_12; +wire [3:0] sbuf_wa_13; +wire [3:0] sbuf_wa_14; +wire [3:0] sbuf_wa_15; +wire [63:0] sbuf_wdat_00; +wire [63:0] sbuf_wdat_01; +wire [63:0] sbuf_wdat_02; +wire [63:0] sbuf_wdat_03; +wire [63:0] sbuf_wdat_04; +wire [63:0] sbuf_wdat_05; +wire [63:0] sbuf_wdat_06; +wire [63:0] sbuf_wdat_07; +wire [63:0] sbuf_wdat_08; +wire [63:0] sbuf_wdat_09; +wire [63:0] sbuf_wdat_10; +wire [63:0] sbuf_wdat_11; +wire [63:0] sbuf_wdat_12; +wire [63:0] sbuf_wdat_13; +wire [63:0] sbuf_wdat_14; +wire [63:0] sbuf_wdat_15; + +wire [3:0] dc2sbuf_p0_rd_bsel; +wire [3:0] dc2sbuf_p1_rd_bsel; + +wire [3:0] img2sbuf_p0_rd_bsel; +wire [3:0] img2sbuf_p1_rd_bsel; +wire dc2sbuf_p0_rd_sel_00; +wire dc2sbuf_p1_rd_sel_00; +wire img2sbuf_p0_rd_sel_00; +wire img2sbuf_p1_rd_sel_00; +wire dc2sbuf_p0_rd_sel_01; +wire dc2sbuf_p1_rd_sel_01; +wire img2sbuf_p0_rd_sel_01; +wire img2sbuf_p1_rd_sel_01; +wire dc2sbuf_p0_rd_sel_02; +wire dc2sbuf_p1_rd_sel_02; +wire img2sbuf_p0_rd_sel_02; +wire img2sbuf_p1_rd_sel_02; +wire dc2sbuf_p0_rd_sel_03; +wire dc2sbuf_p1_rd_sel_03; +wire img2sbuf_p0_rd_sel_03; +wire img2sbuf_p1_rd_sel_03; +wire dc2sbuf_p0_rd_sel_04; +wire dc2sbuf_p1_rd_sel_04; +wire img2sbuf_p0_rd_sel_04; +wire img2sbuf_p1_rd_sel_04; +wire dc2sbuf_p0_rd_sel_05; +wire dc2sbuf_p1_rd_sel_05; +wire img2sbuf_p0_rd_sel_05; +wire img2sbuf_p1_rd_sel_05; +wire dc2sbuf_p0_rd_sel_06; +wire dc2sbuf_p1_rd_sel_06; +wire img2sbuf_p0_rd_sel_06; +wire img2sbuf_p1_rd_sel_06; +wire dc2sbuf_p0_rd_sel_07; +wire dc2sbuf_p1_rd_sel_07; +wire img2sbuf_p0_rd_sel_07; +wire img2sbuf_p1_rd_sel_07; +wire dc2sbuf_p0_rd_sel_08; +wire dc2sbuf_p1_rd_sel_08; +wire img2sbuf_p0_rd_sel_08; +wire img2sbuf_p1_rd_sel_08; +wire dc2sbuf_p0_rd_sel_09; +wire dc2sbuf_p1_rd_sel_09; +wire img2sbuf_p0_rd_sel_09; +wire img2sbuf_p1_rd_sel_09; +wire dc2sbuf_p0_rd_sel_10; +wire dc2sbuf_p1_rd_sel_10; +wire img2sbuf_p0_rd_sel_10; +wire img2sbuf_p1_rd_sel_10; +wire dc2sbuf_p0_rd_sel_11; +wire dc2sbuf_p1_rd_sel_11; +wire img2sbuf_p0_rd_sel_11; +wire img2sbuf_p1_rd_sel_11; +wire dc2sbuf_p0_rd_sel_12; +wire dc2sbuf_p1_rd_sel_12; +wire img2sbuf_p0_rd_sel_12; +wire img2sbuf_p1_rd_sel_12; +wire dc2sbuf_p0_rd_sel_13; +wire dc2sbuf_p1_rd_sel_13; +wire img2sbuf_p0_rd_sel_13; +wire img2sbuf_p1_rd_sel_13; +wire dc2sbuf_p0_rd_sel_14; +wire dc2sbuf_p1_rd_sel_14; +wire img2sbuf_p0_rd_sel_14; +wire img2sbuf_p1_rd_sel_14; +wire dc2sbuf_p0_rd_sel_15; +wire dc2sbuf_p1_rd_sel_15; +wire img2sbuf_p0_rd_sel_15; +wire img2sbuf_p1_rd_sel_15; +wire sbuf_p0_re_00; +wire sbuf_p1_re_00; +wire sbuf_p0_re_01; +wire sbuf_p1_re_01; +wire sbuf_p0_re_02; +wire sbuf_p1_re_02; +wire sbuf_p0_re_03; +wire sbuf_p1_re_03; +wire sbuf_p0_re_04; +wire sbuf_p1_re_04; +wire sbuf_p0_re_05; +wire sbuf_p1_re_05; +wire sbuf_p0_re_06; +wire sbuf_p1_re_06; +wire sbuf_p0_re_07; +wire sbuf_p1_re_07; +wire sbuf_p0_re_08; +wire sbuf_p1_re_08; +wire sbuf_p0_re_09; +wire sbuf_p1_re_09; +wire sbuf_p0_re_10; +wire sbuf_p1_re_10; +wire sbuf_p0_re_11; +wire sbuf_p1_re_11; +wire sbuf_p0_re_12; +wire sbuf_p1_re_12; +wire sbuf_p0_re_13; +wire sbuf_p1_re_13; +wire sbuf_p0_re_14; +wire sbuf_p1_re_14; +wire sbuf_p0_re_15; +wire sbuf_p1_re_15; +wire sbuf_re_00; +wire sbuf_re_01; +wire sbuf_re_02; +wire sbuf_re_03; +wire sbuf_re_04; +wire sbuf_re_05; +wire sbuf_re_06; +wire sbuf_re_07; +wire sbuf_re_08; +wire sbuf_re_09; +wire sbuf_re_10; +wire sbuf_re_11; +wire sbuf_re_12; +wire sbuf_re_13; +wire sbuf_re_14; +wire sbuf_re_15; +wire [63:0] sbuf_rdat_00; +wire [63:0] sbuf_rdat_01; +wire [63:0] sbuf_rdat_02; +wire [63:0] sbuf_rdat_03; +wire [63:0] sbuf_rdat_04; +wire [63:0] sbuf_rdat_05; +wire [63:0] sbuf_rdat_06; +wire [63:0] sbuf_rdat_07; +wire [63:0] sbuf_rdat_08; +wire [63:0] sbuf_rdat_09; +wire [63:0] sbuf_rdat_10; +wire [63:0] sbuf_rdat_11; +wire [63:0] sbuf_rdat_12; +wire [63:0] sbuf_rdat_13; +wire [63:0] sbuf_rdat_14; +wire [63:0] sbuf_rdat_15; + +wire [3:0] dc2sbuf_p0_rd_esel; +wire [3:0] dc2sbuf_p1_rd_esel; + +wire [3:0] img2sbuf_p0_rd_esel; +wire [3:0] img2sbuf_p1_rd_esel; +wire [3:0] sbuf_ra_00; +wire [3:0] sbuf_ra_01; +wire [3:0] sbuf_ra_02; +wire [3:0] sbuf_ra_03; +wire [3:0] sbuf_ra_04; +wire [3:0] sbuf_ra_05; +wire [3:0] sbuf_ra_06; +wire [3:0] sbuf_ra_07; +wire [3:0] sbuf_ra_08; +wire [3:0] sbuf_ra_09; +wire [3:0] sbuf_ra_10; +wire [3:0] sbuf_ra_11; +wire [3:0] sbuf_ra_12; +wire [3:0] sbuf_ra_13; +wire [3:0] sbuf_ra_14; +wire [3:0] sbuf_ra_15; +wire [63:0] sbuf_p0_norm_rdat; +wire [63:0] sbuf_p1_norm_rdat; +wire [63:0] sbuf_p0_rdat; +wire [63:0] sbuf_p1_rdat; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Input port to RAMS // +//////////////////////////////////////////////////////////////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $b1; +//: my $b0; +//: my $bits; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my $name; +//: +//: $b1 = int(log(256)/log(2)) - 1; +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)); +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq ( +//: assign ${name}2sbuf_p0_wr_bsel = ${name}2sbuf_p0_wr_addr[${b1}:${b0}]; +//: assign ${name}2sbuf_p1_wr_bsel = ${name}2sbuf_p1_wr_addr[${b1}:${b0}];\n); +//: } +//: print qq (\n\n); +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(16)/log(2)); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (assign ${name}2sbuf_p${k}_wr_sel_${serial} = (${name}2sbuf_p${k}_wr_bsel == ${bits}'d${j}) & ${name}2sbuf_p${k}_wr_en;\n); +//: } +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (assign sbuf_we_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (${name}2sbuf_p${k}_wr_sel_${serial}); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: } +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(256)/log(2)) - int(log(16)/log(2)); +//: $b1 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: $b0 = 0; +//: print qq (assign sbuf_wa_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (({${bits}{${name}2sbuf_p${k}_wr_sel_${serial}}} & ${name}2sbuf_p${k}_wr_addr[${b1}:${b0}])); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = 8*8; +//: print qq (assign sbuf_wdat_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (({${bits}{${name}2sbuf_p${k}_wr_sel_${serial}}} & ${name}2sbuf_p${k}_wr_data)); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dc2sbuf_p0_wr_bsel = dc2sbuf_p0_wr_addr[7:4]; +assign dc2sbuf_p1_wr_bsel = dc2sbuf_p1_wr_addr[7:4]; + +assign img2sbuf_p0_wr_bsel = img2sbuf_p0_wr_addr[7:4]; +assign img2sbuf_p1_wr_bsel = img2sbuf_p1_wr_addr[7:4]; + + +assign dc2sbuf_p0_wr_sel_00 = (dc2sbuf_p0_wr_bsel == 4'd0) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_00 = (dc2sbuf_p1_wr_bsel == 4'd0) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_00 = (img2sbuf_p0_wr_bsel == 4'd0) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_00 = (img2sbuf_p1_wr_bsel == 4'd0) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_01 = (dc2sbuf_p0_wr_bsel == 4'd1) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_01 = (dc2sbuf_p1_wr_bsel == 4'd1) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_01 = (img2sbuf_p0_wr_bsel == 4'd1) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_01 = (img2sbuf_p1_wr_bsel == 4'd1) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_02 = (dc2sbuf_p0_wr_bsel == 4'd2) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_02 = (dc2sbuf_p1_wr_bsel == 4'd2) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_02 = (img2sbuf_p0_wr_bsel == 4'd2) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_02 = (img2sbuf_p1_wr_bsel == 4'd2) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_03 = (dc2sbuf_p0_wr_bsel == 4'd3) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_03 = (dc2sbuf_p1_wr_bsel == 4'd3) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_03 = (img2sbuf_p0_wr_bsel == 4'd3) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_03 = (img2sbuf_p1_wr_bsel == 4'd3) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_04 = (dc2sbuf_p0_wr_bsel == 4'd4) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_04 = (dc2sbuf_p1_wr_bsel == 4'd4) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_04 = (img2sbuf_p0_wr_bsel == 4'd4) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_04 = (img2sbuf_p1_wr_bsel == 4'd4) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_05 = (dc2sbuf_p0_wr_bsel == 4'd5) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_05 = (dc2sbuf_p1_wr_bsel == 4'd5) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_05 = (img2sbuf_p0_wr_bsel == 4'd5) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_05 = (img2sbuf_p1_wr_bsel == 4'd5) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_06 = (dc2sbuf_p0_wr_bsel == 4'd6) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_06 = (dc2sbuf_p1_wr_bsel == 4'd6) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_06 = (img2sbuf_p0_wr_bsel == 4'd6) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_06 = (img2sbuf_p1_wr_bsel == 4'd6) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_07 = (dc2sbuf_p0_wr_bsel == 4'd7) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_07 = (dc2sbuf_p1_wr_bsel == 4'd7) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_07 = (img2sbuf_p0_wr_bsel == 4'd7) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_07 = (img2sbuf_p1_wr_bsel == 4'd7) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_08 = (dc2sbuf_p0_wr_bsel == 4'd8) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_08 = (dc2sbuf_p1_wr_bsel == 4'd8) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_08 = (img2sbuf_p0_wr_bsel == 4'd8) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_08 = (img2sbuf_p1_wr_bsel == 4'd8) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_09 = (dc2sbuf_p0_wr_bsel == 4'd9) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_09 = (dc2sbuf_p1_wr_bsel == 4'd9) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_09 = (img2sbuf_p0_wr_bsel == 4'd9) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_09 = (img2sbuf_p1_wr_bsel == 4'd9) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_10 = (dc2sbuf_p0_wr_bsel == 4'd10) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_10 = (dc2sbuf_p1_wr_bsel == 4'd10) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_10 = (img2sbuf_p0_wr_bsel == 4'd10) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_10 = (img2sbuf_p1_wr_bsel == 4'd10) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_11 = (dc2sbuf_p0_wr_bsel == 4'd11) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_11 = (dc2sbuf_p1_wr_bsel == 4'd11) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_11 = (img2sbuf_p0_wr_bsel == 4'd11) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_11 = (img2sbuf_p1_wr_bsel == 4'd11) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_12 = (dc2sbuf_p0_wr_bsel == 4'd12) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_12 = (dc2sbuf_p1_wr_bsel == 4'd12) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_12 = (img2sbuf_p0_wr_bsel == 4'd12) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_12 = (img2sbuf_p1_wr_bsel == 4'd12) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_13 = (dc2sbuf_p0_wr_bsel == 4'd13) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_13 = (dc2sbuf_p1_wr_bsel == 4'd13) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_13 = (img2sbuf_p0_wr_bsel == 4'd13) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_13 = (img2sbuf_p1_wr_bsel == 4'd13) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_14 = (dc2sbuf_p0_wr_bsel == 4'd14) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_14 = (dc2sbuf_p1_wr_bsel == 4'd14) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_14 = (img2sbuf_p0_wr_bsel == 4'd14) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_14 = (img2sbuf_p1_wr_bsel == 4'd14) & img2sbuf_p1_wr_en; +assign dc2sbuf_p0_wr_sel_15 = (dc2sbuf_p0_wr_bsel == 4'd15) & dc2sbuf_p0_wr_en; +assign dc2sbuf_p1_wr_sel_15 = (dc2sbuf_p1_wr_bsel == 4'd15) & dc2sbuf_p1_wr_en; +assign img2sbuf_p0_wr_sel_15 = (img2sbuf_p0_wr_bsel == 4'd15) & img2sbuf_p0_wr_en; +assign img2sbuf_p1_wr_sel_15 = (img2sbuf_p1_wr_bsel == 4'd15) & img2sbuf_p1_wr_en; +assign sbuf_we_00 = dc2sbuf_p0_wr_sel_00 | + dc2sbuf_p1_wr_sel_00 | + img2sbuf_p0_wr_sel_00 | + img2sbuf_p1_wr_sel_00; + + + +assign sbuf_we_01 = dc2sbuf_p0_wr_sel_01 | + dc2sbuf_p1_wr_sel_01 | + img2sbuf_p0_wr_sel_01 | + img2sbuf_p1_wr_sel_01; + + + +assign sbuf_we_02 = dc2sbuf_p0_wr_sel_02 | + dc2sbuf_p1_wr_sel_02 | + img2sbuf_p0_wr_sel_02 | + img2sbuf_p1_wr_sel_02; + + + +assign sbuf_we_03 = dc2sbuf_p0_wr_sel_03 | + dc2sbuf_p1_wr_sel_03 | + img2sbuf_p0_wr_sel_03 | + img2sbuf_p1_wr_sel_03; + + + +assign sbuf_we_04 = dc2sbuf_p0_wr_sel_04 | + dc2sbuf_p1_wr_sel_04 | + img2sbuf_p0_wr_sel_04 | + img2sbuf_p1_wr_sel_04; + + + +assign sbuf_we_05 = dc2sbuf_p0_wr_sel_05 | + dc2sbuf_p1_wr_sel_05 | + img2sbuf_p0_wr_sel_05 | + img2sbuf_p1_wr_sel_05; + + + +assign sbuf_we_06 = dc2sbuf_p0_wr_sel_06 | + dc2sbuf_p1_wr_sel_06 | + img2sbuf_p0_wr_sel_06 | + img2sbuf_p1_wr_sel_06; + + + +assign sbuf_we_07 = dc2sbuf_p0_wr_sel_07 | + dc2sbuf_p1_wr_sel_07 | + img2sbuf_p0_wr_sel_07 | + img2sbuf_p1_wr_sel_07; + + + +assign sbuf_we_08 = dc2sbuf_p0_wr_sel_08 | + dc2sbuf_p1_wr_sel_08 | + img2sbuf_p0_wr_sel_08 | + img2sbuf_p1_wr_sel_08; + + + +assign sbuf_we_09 = dc2sbuf_p0_wr_sel_09 | + dc2sbuf_p1_wr_sel_09 | + img2sbuf_p0_wr_sel_09 | + img2sbuf_p1_wr_sel_09; + + + +assign sbuf_we_10 = dc2sbuf_p0_wr_sel_10 | + dc2sbuf_p1_wr_sel_10 | + img2sbuf_p0_wr_sel_10 | + img2sbuf_p1_wr_sel_10; + + + +assign sbuf_we_11 = dc2sbuf_p0_wr_sel_11 | + dc2sbuf_p1_wr_sel_11 | + img2sbuf_p0_wr_sel_11 | + img2sbuf_p1_wr_sel_11; + + + +assign sbuf_we_12 = dc2sbuf_p0_wr_sel_12 | + dc2sbuf_p1_wr_sel_12 | + img2sbuf_p0_wr_sel_12 | + img2sbuf_p1_wr_sel_12; + + + +assign sbuf_we_13 = dc2sbuf_p0_wr_sel_13 | + dc2sbuf_p1_wr_sel_13 | + img2sbuf_p0_wr_sel_13 | + img2sbuf_p1_wr_sel_13; + + + +assign sbuf_we_14 = dc2sbuf_p0_wr_sel_14 | + dc2sbuf_p1_wr_sel_14 | + img2sbuf_p0_wr_sel_14 | + img2sbuf_p1_wr_sel_14; + + + +assign sbuf_we_15 = dc2sbuf_p0_wr_sel_15 | + dc2sbuf_p1_wr_sel_15 | + img2sbuf_p0_wr_sel_15 | + img2sbuf_p1_wr_sel_15; + + + +assign sbuf_wa_00 = ({4{dc2sbuf_p0_wr_sel_00}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_00}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_00}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_00}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_01 = ({4{dc2sbuf_p0_wr_sel_01}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_01}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_01}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_01}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_02 = ({4{dc2sbuf_p0_wr_sel_02}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_02}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_02}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_02}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_03 = ({4{dc2sbuf_p0_wr_sel_03}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_03}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_03}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_03}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_04 = ({4{dc2sbuf_p0_wr_sel_04}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_04}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_04}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_04}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_05 = ({4{dc2sbuf_p0_wr_sel_05}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_05}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_05}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_05}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_06 = ({4{dc2sbuf_p0_wr_sel_06}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_06}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_06}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_06}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_07 = ({4{dc2sbuf_p0_wr_sel_07}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_07}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_07}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_07}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_08 = ({4{dc2sbuf_p0_wr_sel_08}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_08}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_08}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_08}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_09 = ({4{dc2sbuf_p0_wr_sel_09}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_09}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_09}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_09}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_10 = ({4{dc2sbuf_p0_wr_sel_10}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_10}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_10}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_10}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_11 = ({4{dc2sbuf_p0_wr_sel_11}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_11}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_11}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_11}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_12 = ({4{dc2sbuf_p0_wr_sel_12}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_12}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_12}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_12}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_13 = ({4{dc2sbuf_p0_wr_sel_13}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_13}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_13}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_13}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_14 = ({4{dc2sbuf_p0_wr_sel_14}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_14}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_14}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_14}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wa_15 = ({4{dc2sbuf_p0_wr_sel_15}} & dc2sbuf_p0_wr_addr[3:0]) | + ({4{dc2sbuf_p1_wr_sel_15}} & dc2sbuf_p1_wr_addr[3:0]) | + ({4{img2sbuf_p0_wr_sel_15}} & img2sbuf_p0_wr_addr[3:0]) | + ({4{img2sbuf_p1_wr_sel_15}} & img2sbuf_p1_wr_addr[3:0]); + + + +assign sbuf_wdat_00 = ({64{dc2sbuf_p0_wr_sel_00}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_00}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_00}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_00}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_01 = ({64{dc2sbuf_p0_wr_sel_01}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_01}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_01}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_01}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_02 = ({64{dc2sbuf_p0_wr_sel_02}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_02}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_02}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_02}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_03 = ({64{dc2sbuf_p0_wr_sel_03}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_03}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_03}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_03}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_04 = ({64{dc2sbuf_p0_wr_sel_04}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_04}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_04}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_04}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_05 = ({64{dc2sbuf_p0_wr_sel_05}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_05}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_05}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_05}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_06 = ({64{dc2sbuf_p0_wr_sel_06}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_06}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_06}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_06}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_07 = ({64{dc2sbuf_p0_wr_sel_07}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_07}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_07}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_07}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_08 = ({64{dc2sbuf_p0_wr_sel_08}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_08}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_08}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_08}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_09 = ({64{dc2sbuf_p0_wr_sel_09}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_09}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_09}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_09}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_10 = ({64{dc2sbuf_p0_wr_sel_10}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_10}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_10}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_10}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_11 = ({64{dc2sbuf_p0_wr_sel_11}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_11}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_11}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_11}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_12 = ({64{dc2sbuf_p0_wr_sel_12}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_12}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_12}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_12}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_13 = ({64{dc2sbuf_p0_wr_sel_13}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_13}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_13}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_13}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_14 = ({64{dc2sbuf_p0_wr_sel_14}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_14}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_14}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_14}} & img2sbuf_p1_wr_data); + + + +assign sbuf_wdat_15 = ({64{dc2sbuf_p0_wr_sel_15}} & dc2sbuf_p0_wr_data) | + ({64{dc2sbuf_p1_wr_sel_15}} & dc2sbuf_p1_wr_data) | + ({64{img2sbuf_p0_wr_sel_15}} & img2sbuf_p0_wr_data) | + ({64{img2sbuf_p1_wr_sel_15}} & img2sbuf_p1_wr_data); + + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////\n"; +// Instance 16 256bx8 RAMs as local shared buffers //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $serial; +//: my $bits; +//: my $depth; +//: $bits = 8*8; +//: $depth = 256 / 16; +//: for($i = 0; $i < 16; $i ++) { +//: $serial = sprintf("%02d", $i); +//: print qq { +//: nv_ram_rws_${depth}x${bits} u_shared_buffer_${serial} ( +//: .clk (nvdla_core_clk) //|< i +//: ,.ra (sbuf_ra_${serial}) //|< r +//: ,.re (sbuf_re_${serial}) //|< r +//: ,.dout (sbuf_rdat_${serial}) //|> w +//: ,.wa (sbuf_wa_${serial}) //|< r +//: ,.we (sbuf_we_${serial}) //|< r +//: ,.di (sbuf_wdat_${serial}) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +//: );\n\n}; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +nv_ram_rws_16x64 u_shared_buffer_00 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_00) //|< r +,.re (sbuf_re_00) //|< r +,.dout (sbuf_rdat_00) //|> w +,.wa (sbuf_wa_00) //|< r +,.we (sbuf_we_00) //|< r +,.di (sbuf_wdat_00) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_01 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_01) //|< r +,.re (sbuf_re_01) //|< r +,.dout (sbuf_rdat_01) //|> w +,.wa (sbuf_wa_01) //|< r +,.we (sbuf_we_01) //|< r +,.di (sbuf_wdat_01) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_02 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_02) //|< r +,.re (sbuf_re_02) //|< r +,.dout (sbuf_rdat_02) //|> w +,.wa (sbuf_wa_02) //|< r +,.we (sbuf_we_02) //|< r +,.di (sbuf_wdat_02) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_03 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_03) //|< r +,.re (sbuf_re_03) //|< r +,.dout (sbuf_rdat_03) //|> w +,.wa (sbuf_wa_03) //|< r +,.we (sbuf_we_03) //|< r +,.di (sbuf_wdat_03) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_04 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_04) //|< r +,.re (sbuf_re_04) //|< r +,.dout (sbuf_rdat_04) //|> w +,.wa (sbuf_wa_04) //|< r +,.we (sbuf_we_04) //|< r +,.di (sbuf_wdat_04) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_05 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_05) //|< r +,.re (sbuf_re_05) //|< r +,.dout (sbuf_rdat_05) //|> w +,.wa (sbuf_wa_05) //|< r +,.we (sbuf_we_05) //|< r +,.di (sbuf_wdat_05) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_06 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_06) //|< r +,.re (sbuf_re_06) //|< r +,.dout (sbuf_rdat_06) //|> w +,.wa (sbuf_wa_06) //|< r +,.we (sbuf_we_06) //|< r +,.di (sbuf_wdat_06) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_07 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_07) //|< r +,.re (sbuf_re_07) //|< r +,.dout (sbuf_rdat_07) //|> w +,.wa (sbuf_wa_07) //|< r +,.we (sbuf_we_07) //|< r +,.di (sbuf_wdat_07) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_08 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_08) //|< r +,.re (sbuf_re_08) //|< r +,.dout (sbuf_rdat_08) //|> w +,.wa (sbuf_wa_08) //|< r +,.we (sbuf_we_08) //|< r +,.di (sbuf_wdat_08) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_09 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_09) //|< r +,.re (sbuf_re_09) //|< r +,.dout (sbuf_rdat_09) //|> w +,.wa (sbuf_wa_09) //|< r +,.we (sbuf_we_09) //|< r +,.di (sbuf_wdat_09) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_10 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_10) //|< r +,.re (sbuf_re_10) //|< r +,.dout (sbuf_rdat_10) //|> w +,.wa (sbuf_wa_10) //|< r +,.we (sbuf_we_10) //|< r +,.di (sbuf_wdat_10) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_11 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_11) //|< r +,.re (sbuf_re_11) //|< r +,.dout (sbuf_rdat_11) //|> w +,.wa (sbuf_wa_11) //|< r +,.we (sbuf_we_11) //|< r +,.di (sbuf_wdat_11) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_12 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_12) //|< r +,.re (sbuf_re_12) //|< r +,.dout (sbuf_rdat_12) //|> w +,.wa (sbuf_wa_12) //|< r +,.we (sbuf_we_12) //|< r +,.di (sbuf_wdat_12) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_13 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_13) //|< r +,.re (sbuf_re_13) //|< r +,.dout (sbuf_rdat_13) //|> w +,.wa (sbuf_wa_13) //|< r +,.we (sbuf_we_13) //|< r +,.di (sbuf_wdat_13) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_14 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_14) //|< r +,.re (sbuf_re_14) //|< r +,.dout (sbuf_rdat_14) //|> w +,.wa (sbuf_wa_14) //|< r +,.we (sbuf_we_14) //|< r +,.di (sbuf_wdat_14) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +nv_ram_rws_16x64 u_shared_buffer_15 ( +.clk (nvdla_core_clk) //|< i +,.ra (sbuf_ra_15) //|< r +,.re (sbuf_re_15) //|< r +,.dout (sbuf_rdat_15) //|> w +,.wa (sbuf_wa_15) //|< r +,.we (sbuf_we_15) //|< r +,.di (sbuf_wdat_15) //|< r +,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +); + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage 1 //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: my $b1; +//: my $b0; +//: my $bits; +//: +//: $b1 = int(log(256)/log(2)) - 1; +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)); +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: assign ${name}2sbuf_p0_rd_bsel = ${name}2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign ${name}2sbuf_p1_rd_bsel = ${name}2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: } +//: +//: if($def_wino) { +//: $b1 = int(log(256)/log(2)) - 1; +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) + 2; +//: print qq ( +//: assign wg2sbuf_p0_rd_bsel = wg2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign wg2sbuf_p1_rd_bsel = wg2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: print qq (\n\n); +//: +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(16)/log(2)); +//: for($i = 0; $i < @input_list_1; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list_1[$i]; +//: print qq (assign ${name}2sbuf_p${k}_rd_sel_${serial} = (${name}2sbuf_p${k}_rd_bsel == ${bits}'d${j}) & ${name}2sbuf_p${k}_rd_en;\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(16)/log(2)) - 2; +//: $i = int($j/4); +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign wg2sbuf_p${k}_rd_sel_${serial} = (wg2sbuf_p${k}_rd_bsel == ${bits}'d${i}) & wg2sbuf_p${k}_rd_en;\n); +//: } +//: } +//: print qq (\n\n); +//: +//: } +//: for($j = 0; $j < 16; $j ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (assign sbuf_p${k}_re_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq (${name}2sbuf_p${k}_rd_sel_${serial}); +//: if($i != @input_list - 1) { +//: print qq ( | ); +//: } else { +//: print qq (;\n); +//: } +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (assign sbuf_re_${serial} = sbuf_p0_re_${serial} | sbuf_p1_re_${serial};\n); +//: } +//: print qq (\n\n); +//: +//: $b1 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: $b0 = 0; +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: assign ${name}2sbuf_p0_rd_esel = ${name}2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign ${name}2sbuf_p1_rd_esel = ${name}2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: } +//: +//: if($def_wino) { +//: $b1 = int(log(256)/log(2)) - int(log(16)/log(2)) + 1; +//: $b0 = 2; +//: print qq ( +//: assign wg2sbuf_p0_rd_esel = wg2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign wg2sbuf_p1_rd_esel = wg2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: print qq (\n\n); +//: +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(256)/log(2)) - int(log(16)/log(2)); +//: print qq (assign sbuf_ra_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (({${bits}{${name}2sbuf_p${k}_rd_sel_${serial}}} & ${name}2sbuf_p${k}_rd_esel)); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq(assign sbuf_p${k}_wg_sel_q${i} = (wg2sbuf_p${k}_rd_addr[1:0] == 2'h${i}) & wg2sbuf_p${k}_rd_en;\n); +//: } +//: } +//: print qq (\n\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dc2sbuf_p0_rd_bsel = dc2sbuf_p0_rd_addr[7:4]; +assign dc2sbuf_p1_rd_bsel = dc2sbuf_p1_rd_addr[7:4]; + +assign img2sbuf_p0_rd_bsel = img2sbuf_p0_rd_addr[7:4]; +assign img2sbuf_p1_rd_bsel = img2sbuf_p1_rd_addr[7:4]; +assign dc2sbuf_p0_rd_sel_00 = (dc2sbuf_p0_rd_bsel == 4'd0) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_00 = (dc2sbuf_p1_rd_bsel == 4'd0) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_00 = (img2sbuf_p0_rd_bsel == 4'd0) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_00 = (img2sbuf_p1_rd_bsel == 4'd0) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_01 = (dc2sbuf_p0_rd_bsel == 4'd1) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_01 = (dc2sbuf_p1_rd_bsel == 4'd1) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_01 = (img2sbuf_p0_rd_bsel == 4'd1) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_01 = (img2sbuf_p1_rd_bsel == 4'd1) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_02 = (dc2sbuf_p0_rd_bsel == 4'd2) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_02 = (dc2sbuf_p1_rd_bsel == 4'd2) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_02 = (img2sbuf_p0_rd_bsel == 4'd2) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_02 = (img2sbuf_p1_rd_bsel == 4'd2) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_03 = (dc2sbuf_p0_rd_bsel == 4'd3) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_03 = (dc2sbuf_p1_rd_bsel == 4'd3) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_03 = (img2sbuf_p0_rd_bsel == 4'd3) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_03 = (img2sbuf_p1_rd_bsel == 4'd3) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_04 = (dc2sbuf_p0_rd_bsel == 4'd4) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_04 = (dc2sbuf_p1_rd_bsel == 4'd4) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_04 = (img2sbuf_p0_rd_bsel == 4'd4) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_04 = (img2sbuf_p1_rd_bsel == 4'd4) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_05 = (dc2sbuf_p0_rd_bsel == 4'd5) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_05 = (dc2sbuf_p1_rd_bsel == 4'd5) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_05 = (img2sbuf_p0_rd_bsel == 4'd5) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_05 = (img2sbuf_p1_rd_bsel == 4'd5) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_06 = (dc2sbuf_p0_rd_bsel == 4'd6) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_06 = (dc2sbuf_p1_rd_bsel == 4'd6) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_06 = (img2sbuf_p0_rd_bsel == 4'd6) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_06 = (img2sbuf_p1_rd_bsel == 4'd6) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_07 = (dc2sbuf_p0_rd_bsel == 4'd7) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_07 = (dc2sbuf_p1_rd_bsel == 4'd7) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_07 = (img2sbuf_p0_rd_bsel == 4'd7) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_07 = (img2sbuf_p1_rd_bsel == 4'd7) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_08 = (dc2sbuf_p0_rd_bsel == 4'd8) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_08 = (dc2sbuf_p1_rd_bsel == 4'd8) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_08 = (img2sbuf_p0_rd_bsel == 4'd8) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_08 = (img2sbuf_p1_rd_bsel == 4'd8) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_09 = (dc2sbuf_p0_rd_bsel == 4'd9) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_09 = (dc2sbuf_p1_rd_bsel == 4'd9) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_09 = (img2sbuf_p0_rd_bsel == 4'd9) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_09 = (img2sbuf_p1_rd_bsel == 4'd9) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_10 = (dc2sbuf_p0_rd_bsel == 4'd10) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_10 = (dc2sbuf_p1_rd_bsel == 4'd10) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_10 = (img2sbuf_p0_rd_bsel == 4'd10) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_10 = (img2sbuf_p1_rd_bsel == 4'd10) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_11 = (dc2sbuf_p0_rd_bsel == 4'd11) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_11 = (dc2sbuf_p1_rd_bsel == 4'd11) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_11 = (img2sbuf_p0_rd_bsel == 4'd11) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_11 = (img2sbuf_p1_rd_bsel == 4'd11) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_12 = (dc2sbuf_p0_rd_bsel == 4'd12) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_12 = (dc2sbuf_p1_rd_bsel == 4'd12) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_12 = (img2sbuf_p0_rd_bsel == 4'd12) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_12 = (img2sbuf_p1_rd_bsel == 4'd12) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_13 = (dc2sbuf_p0_rd_bsel == 4'd13) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_13 = (dc2sbuf_p1_rd_bsel == 4'd13) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_13 = (img2sbuf_p0_rd_bsel == 4'd13) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_13 = (img2sbuf_p1_rd_bsel == 4'd13) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_14 = (dc2sbuf_p0_rd_bsel == 4'd14) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_14 = (dc2sbuf_p1_rd_bsel == 4'd14) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_14 = (img2sbuf_p0_rd_bsel == 4'd14) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_14 = (img2sbuf_p1_rd_bsel == 4'd14) & img2sbuf_p1_rd_en; +assign dc2sbuf_p0_rd_sel_15 = (dc2sbuf_p0_rd_bsel == 4'd15) & dc2sbuf_p0_rd_en; +assign dc2sbuf_p1_rd_sel_15 = (dc2sbuf_p1_rd_bsel == 4'd15) & dc2sbuf_p1_rd_en; +assign img2sbuf_p0_rd_sel_15 = (img2sbuf_p0_rd_bsel == 4'd15) & img2sbuf_p0_rd_en; +assign img2sbuf_p1_rd_sel_15 = (img2sbuf_p1_rd_bsel == 4'd15) & img2sbuf_p1_rd_en; + + +assign sbuf_p0_re_00 = dc2sbuf_p0_rd_sel_00 | img2sbuf_p0_rd_sel_00; +assign sbuf_p1_re_00 = dc2sbuf_p1_rd_sel_00 | img2sbuf_p1_rd_sel_00; +assign sbuf_p0_re_01 = dc2sbuf_p0_rd_sel_01 | img2sbuf_p0_rd_sel_01; +assign sbuf_p1_re_01 = dc2sbuf_p1_rd_sel_01 | img2sbuf_p1_rd_sel_01; +assign sbuf_p0_re_02 = dc2sbuf_p0_rd_sel_02 | img2sbuf_p0_rd_sel_02; +assign sbuf_p1_re_02 = dc2sbuf_p1_rd_sel_02 | img2sbuf_p1_rd_sel_02; +assign sbuf_p0_re_03 = dc2sbuf_p0_rd_sel_03 | img2sbuf_p0_rd_sel_03; +assign sbuf_p1_re_03 = dc2sbuf_p1_rd_sel_03 | img2sbuf_p1_rd_sel_03; +assign sbuf_p0_re_04 = dc2sbuf_p0_rd_sel_04 | img2sbuf_p0_rd_sel_04; +assign sbuf_p1_re_04 = dc2sbuf_p1_rd_sel_04 | img2sbuf_p1_rd_sel_04; +assign sbuf_p0_re_05 = dc2sbuf_p0_rd_sel_05 | img2sbuf_p0_rd_sel_05; +assign sbuf_p1_re_05 = dc2sbuf_p1_rd_sel_05 | img2sbuf_p1_rd_sel_05; +assign sbuf_p0_re_06 = dc2sbuf_p0_rd_sel_06 | img2sbuf_p0_rd_sel_06; +assign sbuf_p1_re_06 = dc2sbuf_p1_rd_sel_06 | img2sbuf_p1_rd_sel_06; +assign sbuf_p0_re_07 = dc2sbuf_p0_rd_sel_07 | img2sbuf_p0_rd_sel_07; +assign sbuf_p1_re_07 = dc2sbuf_p1_rd_sel_07 | img2sbuf_p1_rd_sel_07; +assign sbuf_p0_re_08 = dc2sbuf_p0_rd_sel_08 | img2sbuf_p0_rd_sel_08; +assign sbuf_p1_re_08 = dc2sbuf_p1_rd_sel_08 | img2sbuf_p1_rd_sel_08; +assign sbuf_p0_re_09 = dc2sbuf_p0_rd_sel_09 | img2sbuf_p0_rd_sel_09; +assign sbuf_p1_re_09 = dc2sbuf_p1_rd_sel_09 | img2sbuf_p1_rd_sel_09; +assign sbuf_p0_re_10 = dc2sbuf_p0_rd_sel_10 | img2sbuf_p0_rd_sel_10; +assign sbuf_p1_re_10 = dc2sbuf_p1_rd_sel_10 | img2sbuf_p1_rd_sel_10; +assign sbuf_p0_re_11 = dc2sbuf_p0_rd_sel_11 | img2sbuf_p0_rd_sel_11; +assign sbuf_p1_re_11 = dc2sbuf_p1_rd_sel_11 | img2sbuf_p1_rd_sel_11; +assign sbuf_p0_re_12 = dc2sbuf_p0_rd_sel_12 | img2sbuf_p0_rd_sel_12; +assign sbuf_p1_re_12 = dc2sbuf_p1_rd_sel_12 | img2sbuf_p1_rd_sel_12; +assign sbuf_p0_re_13 = dc2sbuf_p0_rd_sel_13 | img2sbuf_p0_rd_sel_13; +assign sbuf_p1_re_13 = dc2sbuf_p1_rd_sel_13 | img2sbuf_p1_rd_sel_13; +assign sbuf_p0_re_14 = dc2sbuf_p0_rd_sel_14 | img2sbuf_p0_rd_sel_14; +assign sbuf_p1_re_14 = dc2sbuf_p1_rd_sel_14 | img2sbuf_p1_rd_sel_14; +assign sbuf_p0_re_15 = dc2sbuf_p0_rd_sel_15 | img2sbuf_p0_rd_sel_15; +assign sbuf_p1_re_15 = dc2sbuf_p1_rd_sel_15 | img2sbuf_p1_rd_sel_15; + + +assign sbuf_re_00 = sbuf_p0_re_00 | sbuf_p1_re_00; +assign sbuf_re_01 = sbuf_p0_re_01 | sbuf_p1_re_01; +assign sbuf_re_02 = sbuf_p0_re_02 | sbuf_p1_re_02; +assign sbuf_re_03 = sbuf_p0_re_03 | sbuf_p1_re_03; +assign sbuf_re_04 = sbuf_p0_re_04 | sbuf_p1_re_04; +assign sbuf_re_05 = sbuf_p0_re_05 | sbuf_p1_re_05; +assign sbuf_re_06 = sbuf_p0_re_06 | sbuf_p1_re_06; +assign sbuf_re_07 = sbuf_p0_re_07 | sbuf_p1_re_07; +assign sbuf_re_08 = sbuf_p0_re_08 | sbuf_p1_re_08; +assign sbuf_re_09 = sbuf_p0_re_09 | sbuf_p1_re_09; +assign sbuf_re_10 = sbuf_p0_re_10 | sbuf_p1_re_10; +assign sbuf_re_11 = sbuf_p0_re_11 | sbuf_p1_re_11; +assign sbuf_re_12 = sbuf_p0_re_12 | sbuf_p1_re_12; +assign sbuf_re_13 = sbuf_p0_re_13 | sbuf_p1_re_13; +assign sbuf_re_14 = sbuf_p0_re_14 | sbuf_p1_re_14; +assign sbuf_re_15 = sbuf_p0_re_15 | sbuf_p1_re_15; + + + +assign dc2sbuf_p0_rd_esel = dc2sbuf_p0_rd_addr[3:0]; +assign dc2sbuf_p1_rd_esel = dc2sbuf_p1_rd_addr[3:0]; + +assign img2sbuf_p0_rd_esel = img2sbuf_p0_rd_addr[3:0]; +assign img2sbuf_p1_rd_esel = img2sbuf_p1_rd_addr[3:0]; +assign sbuf_ra_00 = ({4{dc2sbuf_p0_rd_sel_00}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_00}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_00}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_00}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_01 = ({4{dc2sbuf_p0_rd_sel_01}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_01}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_01}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_01}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_02 = ({4{dc2sbuf_p0_rd_sel_02}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_02}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_02}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_02}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_03 = ({4{dc2sbuf_p0_rd_sel_03}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_03}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_03}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_03}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_04 = ({4{dc2sbuf_p0_rd_sel_04}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_04}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_04}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_04}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_05 = ({4{dc2sbuf_p0_rd_sel_05}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_05}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_05}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_05}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_06 = ({4{dc2sbuf_p0_rd_sel_06}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_06}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_06}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_06}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_07 = ({4{dc2sbuf_p0_rd_sel_07}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_07}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_07}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_07}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_08 = ({4{dc2sbuf_p0_rd_sel_08}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_08}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_08}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_08}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_09 = ({4{dc2sbuf_p0_rd_sel_09}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_09}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_09}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_09}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_10 = ({4{dc2sbuf_p0_rd_sel_10}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_10}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_10}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_10}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_11 = ({4{dc2sbuf_p0_rd_sel_11}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_11}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_11}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_11}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_12 = ({4{dc2sbuf_p0_rd_sel_12}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_12}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_12}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_12}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_13 = ({4{dc2sbuf_p0_rd_sel_13}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_13}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_13}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_13}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_14 = ({4{dc2sbuf_p0_rd_sel_14}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_14}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_14}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_14}} & img2sbuf_p1_rd_esel); + +assign sbuf_ra_15 = ({4{dc2sbuf_p0_rd_sel_15}} & dc2sbuf_p0_rd_esel) | + ({4{dc2sbuf_p1_rd_sel_15}} & dc2sbuf_p1_rd_esel) | + ({4{img2sbuf_p0_rd_sel_15}} & img2sbuf_p0_rd_esel) | + ({4{img2sbuf_p1_rd_sel_15}} & img2sbuf_p1_rd_esel); + + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage1 register //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $val; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my $name; +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($k = 0; $k < 2; $k ++) { +//: if($def_wino) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_re_${serial} & ~wg2sbuf_p${k}_rd_en\" -q sbuf_p${k}_re_${serial}_norm_d1"); +//: } else { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_re_${serial}\" -q sbuf_p${k}_re_${serial}_norm_d1"); +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($j = 0; $j < 16/4; $j ++) { +//: $val = sprintf("%02d", $j); +//: $serial = sprintf("%02d", $j*4); +//: for($k = 0; $k < 2; $k ++) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_re_${serial} & wg2sbuf_p${k}_rd_en\" -q sbuf_p${k}_re_${val}_wg_d1"); +//: } +//: } +//: print qq (\n\n); +//: +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_wg_sel_q${i}\" -q sbuf_p${k}_wg_sel_q${i}_d1"); +//: } +//: } +//: print qq (\n\n); +//: +//: } +//: if($def_wino) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p0_rd_en | wg2sbuf_p0_rd_en | img2sbuf_p0_rd_en\" -q sbuf_p0_rd_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p1_rd_en | wg2sbuf_p1_rd_en | img2sbuf_p1_rd_en\" -q sbuf_p1_rd_en_d1"); +//: } else { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p0_rd_en | img2sbuf_p0_rd_en\" -q sbuf_p0_rd_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p1_rd_en | img2sbuf_p1_rd_en\" -q sbuf_p1_rd_en_d1"); +//: } +//: print qq (\n\n); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_00_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_00_norm_d1 <= sbuf_p0_re_00; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_00_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_00_norm_d1 <= sbuf_p1_re_00; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_01_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_01_norm_d1 <= sbuf_p0_re_01; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_01_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_01_norm_d1 <= sbuf_p1_re_01; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_02_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_02_norm_d1 <= sbuf_p0_re_02; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_02_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_02_norm_d1 <= sbuf_p1_re_02; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_03_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_03_norm_d1 <= sbuf_p0_re_03; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_03_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_03_norm_d1 <= sbuf_p1_re_03; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_04_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_04_norm_d1 <= sbuf_p0_re_04; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_04_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_04_norm_d1 <= sbuf_p1_re_04; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_05_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_05_norm_d1 <= sbuf_p0_re_05; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_05_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_05_norm_d1 <= sbuf_p1_re_05; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_06_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_06_norm_d1 <= sbuf_p0_re_06; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_06_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_06_norm_d1 <= sbuf_p1_re_06; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_07_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_07_norm_d1 <= sbuf_p0_re_07; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_07_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_07_norm_d1 <= sbuf_p1_re_07; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_08_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_08_norm_d1 <= sbuf_p0_re_08; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_08_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_08_norm_d1 <= sbuf_p1_re_08; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_09_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_09_norm_d1 <= sbuf_p0_re_09; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_09_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_09_norm_d1 <= sbuf_p1_re_09; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_10_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_10_norm_d1 <= sbuf_p0_re_10; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_10_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_10_norm_d1 <= sbuf_p1_re_10; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_11_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_11_norm_d1 <= sbuf_p0_re_11; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_11_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_11_norm_d1 <= sbuf_p1_re_11; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_12_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_12_norm_d1 <= sbuf_p0_re_12; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_12_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_12_norm_d1 <= sbuf_p1_re_12; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_13_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_13_norm_d1 <= sbuf_p0_re_13; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_13_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_13_norm_d1 <= sbuf_p1_re_13; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_14_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_14_norm_d1 <= sbuf_p0_re_14; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_14_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_14_norm_d1 <= sbuf_p1_re_14; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_re_15_norm_d1 <= 1'b0; + end else begin + sbuf_p0_re_15_norm_d1 <= sbuf_p0_re_15; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_re_15_norm_d1 <= 1'b0; + end else begin + sbuf_p1_re_15_norm_d1 <= sbuf_p1_re_15; + end +end + + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p0_rd_en_d1 <= 1'b0; + end else begin + sbuf_p0_rd_en_d1 <= dc2sbuf_p0_rd_en | img2sbuf_p0_rd_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_p1_rd_en_d1 <= 1'b0; + end else begin + sbuf_p1_rd_en_d1 <= dc2sbuf_p1_rd_en | img2sbuf_p1_rd_en; + end +end + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage2 //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $j; +//: my $k; +//: my $b1; +//: my $b0; +//: my $val; +//: my $serial; +//: my $def_wino = 0; +//: +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign sbuf_p${k}_norm_rdat = ); +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (({8*8{sbuf_p${k}_re_${serial}_norm_d1}} & sbuf_rdat_${serial})); +//: if($j != 16 - 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n); +//: } +//: } +//: print qq (\n\n); +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq (assign sbuf_p${k}_wg_rdat_src_${i} = ); +//: for($j = 0; $j < 16/4; $j ++) { +//: $val = sprintf("%02d", $j); +//: $serial = sprintf("%02d", $j*4 + $i); +//: print qq (({8*8{sbuf_p${k}_re_${val}_wg_d1}} & sbuf_rdat_${serial})); +//: if($j != 16/4 - 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n); +//: } +//: } +//: print qq (\n\n); +//: } +//: } +//: print qq (\n\n); +//: +//: for($k = 0; $k < 2; $k ++) { +//: print qq(assign sbuf_p${k}_wg_rdat = ); +//: for($i = 0; $i < 4; $i ++) { +//: $b1 = int(8*8/4 * ($i + 1) - 1); +//: $b0 = int(8*8/4 * $i); +//: print qq(\({8*8{sbuf_p${k}_wg_sel_q${i}_d1}} & \{); +//: for($j = 3; $j >= 0; $j --) { +//: print qq(sbuf_p${k}_wg_rdat_src_${j}[${b1}:${b0}]); +//: if($j != 0) { +//: print qq(, ); +//: } else { +//: print qq(\}\)); +//: } +//: } +//: if($i != 3) { +//: print qq( |\n ); +//: } else { +//: print qq(;\n); +//: } +//: } +//: print qq(\n); +//: } +//: print qq (\n\n); +//: +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign sbuf_p${k}_rdat = sbuf_p${k}_norm_rdat | sbuf_p${k}_wg_rdat;\n); +//: } +//: } else { +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign sbuf_p${k}_rdat = sbuf_p${k}_norm_rdat;\n); +//: } +//: } +//: print qq (\n\n); +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign sbuf_p0_norm_rdat = ({8*8{sbuf_p0_re_00_norm_d1}} & sbuf_rdat_00) | + ({8*8{sbuf_p0_re_01_norm_d1}} & sbuf_rdat_01) | + ({8*8{sbuf_p0_re_02_norm_d1}} & sbuf_rdat_02) | + ({8*8{sbuf_p0_re_03_norm_d1}} & sbuf_rdat_03) | + ({8*8{sbuf_p0_re_04_norm_d1}} & sbuf_rdat_04) | + ({8*8{sbuf_p0_re_05_norm_d1}} & sbuf_rdat_05) | + ({8*8{sbuf_p0_re_06_norm_d1}} & sbuf_rdat_06) | + ({8*8{sbuf_p0_re_07_norm_d1}} & sbuf_rdat_07) | + ({8*8{sbuf_p0_re_08_norm_d1}} & sbuf_rdat_08) | + ({8*8{sbuf_p0_re_09_norm_d1}} & sbuf_rdat_09) | + ({8*8{sbuf_p0_re_10_norm_d1}} & sbuf_rdat_10) | + ({8*8{sbuf_p0_re_11_norm_d1}} & sbuf_rdat_11) | + ({8*8{sbuf_p0_re_12_norm_d1}} & sbuf_rdat_12) | + ({8*8{sbuf_p0_re_13_norm_d1}} & sbuf_rdat_13) | + ({8*8{sbuf_p0_re_14_norm_d1}} & sbuf_rdat_14) | + ({8*8{sbuf_p0_re_15_norm_d1}} & sbuf_rdat_15); + + +assign sbuf_p1_norm_rdat = ({8*8{sbuf_p1_re_00_norm_d1}} & sbuf_rdat_00) | + ({8*8{sbuf_p1_re_01_norm_d1}} & sbuf_rdat_01) | + ({8*8{sbuf_p1_re_02_norm_d1}} & sbuf_rdat_02) | + ({8*8{sbuf_p1_re_03_norm_d1}} & sbuf_rdat_03) | + ({8*8{sbuf_p1_re_04_norm_d1}} & sbuf_rdat_04) | + ({8*8{sbuf_p1_re_05_norm_d1}} & sbuf_rdat_05) | + ({8*8{sbuf_p1_re_06_norm_d1}} & sbuf_rdat_06) | + ({8*8{sbuf_p1_re_07_norm_d1}} & sbuf_rdat_07) | + ({8*8{sbuf_p1_re_08_norm_d1}} & sbuf_rdat_08) | + ({8*8{sbuf_p1_re_09_norm_d1}} & sbuf_rdat_09) | + ({8*8{sbuf_p1_re_10_norm_d1}} & sbuf_rdat_10) | + ({8*8{sbuf_p1_re_11_norm_d1}} & sbuf_rdat_11) | + ({8*8{sbuf_p1_re_12_norm_d1}} & sbuf_rdat_12) | + ({8*8{sbuf_p1_re_13_norm_d1}} & sbuf_rdat_13) | + ({8*8{sbuf_p1_re_14_norm_d1}} & sbuf_rdat_14) | + ({8*8{sbuf_p1_re_15_norm_d1}} & sbuf_rdat_15); + + + + +assign sbuf_p0_rdat = sbuf_p0_norm_rdat; +assign sbuf_p1_rdat = sbuf_p1_norm_rdat; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage2 register //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $k; +//: for($k = 0; $k < 2; $k ++) { +//: &eperl::flop("-nodeclare -norst -en \"sbuf_p${k}_rd_en_d1\" -d \"sbuf_p${k}_rdat\" -q sbuf_p${k}_rdat_d2"); +//: } +//: print qq (\n\n); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((sbuf_p0_rd_en_d1) == 1'b1) begin + sbuf_p0_rdat_d2 <= sbuf_p0_rdat; + // VCS coverage off + end else if ((sbuf_p0_rd_en_d1) == 1'b0) begin + end else begin + sbuf_p0_rdat_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sbuf_p1_rd_en_d1) == 1'b1) begin + sbuf_p1_rdat_d2 <= sbuf_p1_rdat; + // VCS coverage off + end else if ((sbuf_p1_rd_en_d1) == 1'b0) begin + end else begin + sbuf_p1_rdat_d2 <= 'bx; + // VCS coverage on + end +end + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: connect output data signal //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $k; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq (assign ${name}2sbuf_p${k}_rd_data = sbuf_p${k}_rdat_d2;\n); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dc2sbuf_p0_rd_data = sbuf_p0_rdat_d2; +assign img2sbuf_p0_rd_data = sbuf_p0_rdat_d2; +assign dc2sbuf_p1_rd_data = sbuf_p1_rdat_d2; +assign img2sbuf_p1_rd_data = sbuf_p1_rdat_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"multiple write to shared buffer") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, ((dc2sbuf_p0_wr_en | dc2sbuf_p1_wr_en) & (img2sbuf_p0_wr_en | img2sbuf_p1_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"multiple read to shared buffer") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, ((dc2sbuf_p0_rd_en | dc2sbuf_p1_rd_en) & (img2sbuf_p0_rd_en | img2sbuf_p1_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"dc write same buffer") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (dc2sbuf_p0_wr_en & dc2sbuf_p1_wr_en & (dc2sbuf_p0_wr_bsel == dc2sbuf_p1_wr_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"img write same buffer") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (img2sbuf_p0_wr_en & img2sbuf_p1_wr_en & (img2sbuf_p0_wr_bsel == img2sbuf_p1_wr_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"dc read same buffer") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (dc2sbuf_p0_rd_en & dc2sbuf_p1_rd_en & (dc2sbuf_p0_rd_bsel == dc2sbuf_p1_rd_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"img read same buffer") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (img2sbuf_p0_rd_en & img2sbuf_p1_rd_en & (img2sbuf_p0_rd_bsel == img2sbuf_p1_rd_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML +//for(my $i = 0; $i < 16; $i ++) { +// my $j = sprintf("%02d", $i); +// my $k = $i + 9; +// vprint qq { +// nv_assert_never #(0,0,"Error! shared ram ${j} read and write hazard!") zzz_assert_never_${k} (nvdla_core_clk, `ASSERT_RESET, (sbuf_re_${j} & sbuf_we_${j} & (sbuf_ra_${j} == sbuf_wa_${j}))); \/\/ spyglass disable W504 SelfDeterminedExpr-ML}; +//} +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_shared_buffer diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v.vcp new file mode 100644 index 0000000..9d274ad --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v.vcp @@ -0,0 +1,722 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_shared_buffer.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_shared_buffer ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dc2sbuf_p0_wr_en //|< i + ,dc2sbuf_p0_wr_addr //|< i + ,dc2sbuf_p0_wr_data //|< i + ,dc2sbuf_p1_wr_en //|< i + ,dc2sbuf_p1_wr_addr //|< i + ,dc2sbuf_p1_wr_data //|< i + ,img2sbuf_p0_wr_en //|< i + ,img2sbuf_p0_wr_addr //|< i + ,img2sbuf_p0_wr_data //|< i + ,img2sbuf_p1_wr_en //|< i + ,img2sbuf_p1_wr_addr //|< i + ,img2sbuf_p1_wr_data //|< i + ,dc2sbuf_p0_rd_en //|< i + ,dc2sbuf_p0_rd_addr //|< i + ,dc2sbuf_p0_rd_data //|> o + ,dc2sbuf_p1_rd_en //|< i + ,dc2sbuf_p1_rd_addr //|< i + ,dc2sbuf_p1_rd_data //|> o + ,img2sbuf_p0_rd_en //|< i + ,img2sbuf_p0_rd_addr //|< i + ,img2sbuf_p0_rd_data //|> o + ,img2sbuf_p1_rd_en //|< i + ,img2sbuf_p1_rd_addr //|< i + ,img2sbuf_p1_rd_data //|> o + ); +// +// NV_NVDLA_CDMA_shared_buffer_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dc2sbuf_p0_wr_en; /* data valid */ +input [7:0] dc2sbuf_p0_wr_addr; +input [8*8 -1:0] dc2sbuf_p0_wr_data; +input dc2sbuf_p1_wr_en; /* data valid */ +input [7:0] dc2sbuf_p1_wr_addr; +input [8*8 -1:0] dc2sbuf_p1_wr_data; +input img2sbuf_p0_wr_en; /* data valid */ +input [7:0] img2sbuf_p0_wr_addr; +input [8*8 -1:0] img2sbuf_p0_wr_data; +input img2sbuf_p1_wr_en; /* data valid */ +input [7:0] img2sbuf_p1_wr_addr; +input [8*8 -1:0] img2sbuf_p1_wr_data; +input dc2sbuf_p0_rd_en; /* data valid */ +input [7:0] dc2sbuf_p0_rd_addr; +output [8*8 -1:0] dc2sbuf_p0_rd_data; +input dc2sbuf_p1_rd_en; /* data valid */ +input [7:0] dc2sbuf_p1_rd_addr; +output [8*8 -1:0] dc2sbuf_p1_rd_data; +input img2sbuf_p0_rd_en; /* data valid */ +input [7:0] img2sbuf_p0_rd_addr; +output [8*8 -1:0] img2sbuf_p0_rd_data; +input img2sbuf_p1_rd_en; /* data valid */ +input [7:0] img2sbuf_p1_rd_addr; +output [8*8 -1:0] img2sbuf_p1_rd_data; +////////////// +// REGS // +////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $b0; +//: my $val; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($k = 0; $k < 2; $k ++) { +//: print qq(reg sbuf_p${k}_re_${serial}_norm_d1;\n); +//: } +//: } +//: $b0 = 8*8 - 1; +//: for($k = 0; $k < 2; $k ++) { +//: print qq(reg [${b0}:0] sbuf_p${k}_rdat_d2;\n); +//: print qq(reg sbuf_p${k}_rd_en_d1;\n); +//: } +//: if($def_wino) { +//: for($j = 0; $j < 16/4; $j ++) { +//: $val = sprintf("%02d", $j); +//: for($k = 0; $k < 2; $k ++) { +//: print qq(reg sbuf_p${k}_re_${val}_wg_d1;\n); +//: } +//: } +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq(reg sbuf_p${k}_wg_sel_q${i}_d1;\n); +//: } +//: } +//: } +//: print qq (\n\n); +////////////// +// WIRES // +////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $b0; +//: my $val; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: $b0 = int(log(16)/log(2)) - 1; +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq ( +//: wire [${b0}:0] ${name}2sbuf_p0_wr_bsel; +//: wire [${b0}:0] ${name}2sbuf_p1_wr_bsel;\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (wire ${name}2sbuf_p${k}_wr_sel_${serial};\n); +//: } +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (wire sbuf_we_${serial};\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: print qq (wire [${b0}:0] sbuf_wa_${serial};\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $b0 = 8*8 - 1; +//: print qq (wire [${b0}:0] sbuf_wdat_${serial};\n); +//: } +//: $b0 = int(log(16)/log(2)) - 1; +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: wire [${b0}:0] ${name}2sbuf_p0_rd_bsel; +//: wire [${b0}:0] ${name}2sbuf_p1_rd_bsel;\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($i = 0; $i < @input_list_1; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list_1[$i]; +//: print qq (wire ${name}2sbuf_p${k}_rd_sel_${serial};\n); +//: } +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (wire sbuf_p${k}_re_${serial};\n); +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (wire sbuf_re_${serial};\n); +//: } +//: $b0 = 8*8 - 1; +//: for($i = 0; $i < 16; $i ++) { +//: $serial = sprintf("%02d", $i); +//: print qq (wire [${b0}:0] sbuf_rdat_${serial};\n); +//: } +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: wire [${b0}:0] ${name}2sbuf_p0_rd_esel; +//: wire [${b0}:0] ${name}2sbuf_p1_rd_esel;\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: print qq (wire [${b0}:0] sbuf_ra_${serial};\n); +//: } +//: $b0 = 8*8 - 1; +//: for($k = 0; $k < 2; $k ++) { +//: print qq (wire [${b0}:0] sbuf_p${k}_norm_rdat;\n); +//: } +//: for($k = 0; $k < 2; $k ++) { +//: print qq (wire [${b0}:0] sbuf_p${k}_rdat;\n); +//: } +//: if($def_wino) { +//: $b0 = int(log(16)/log(2)) - 3; +//: print qq ( +//: wire [${b0}:0] wg2sbuf_p0_rd_bsel; +//: wire [${b0}:0] wg2sbuf_p1_rd_bsel;\n); +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $i = int($j/4); +//: for($k = 0; $k < 2; $k ++) { +//: print qq (wire wg2sbuf_p${k}_rd_sel_${serial};\n); +//: } +//: } +//: +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: print qq ( +//: wire [${b0}:0] wg2sbuf_p0_rd_esel; +//: wire [${b0}:0] wg2sbuf_p1_rd_esel;\n); +//: $b0 = 8*8 - 1; +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq (wire [${b0}:0] sbuf_p${k}_wg_rdat_src_${i};\n); +//: } +//: } +//: for($k = 0; $k < 2; $k ++) { +//: print qq(wire [${b0}:0] sbuf_p${k}_wg_rdat;\n); +//: } +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq(wire sbuf_p${k}_wg_sel_q${i};\n); +//: } +//: } +//: } +//////////////////////////////////////////////////////////////////////// +// Input port to RAMS // +//////////////////////////////////////////////////////////////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $b1; +//: my $b0; +//: my $bits; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my $name; +//: +//: $b1 = int(log(256)/log(2)) - 1; +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)); +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq ( +//: assign ${name}2sbuf_p0_wr_bsel = ${name}2sbuf_p0_wr_addr[${b1}:${b0}]; +//: assign ${name}2sbuf_p1_wr_bsel = ${name}2sbuf_p1_wr_addr[${b1}:${b0}];\n); +//: } +//: print qq (\n\n); +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(16)/log(2)); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (assign ${name}2sbuf_p${k}_wr_sel_${serial} = (${name}2sbuf_p${k}_wr_bsel == ${bits}'d${j}) & ${name}2sbuf_p${k}_wr_en;\n); +//: } +//: } +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (assign sbuf_we_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (${name}2sbuf_p${k}_wr_sel_${serial}); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: } +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(256)/log(2)) - int(log(16)/log(2)); +//: $b1 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: $b0 = 0; +//: print qq (assign sbuf_wa_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (({${bits}{${name}2sbuf_p${k}_wr_sel_${serial}}} & ${name}2sbuf_p${k}_wr_addr[${b1}:${b0}])); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = 8*8; +//: print qq (assign sbuf_wdat_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (({${bits}{${name}2sbuf_p${k}_wr_sel_${serial}}} & ${name}2sbuf_p${k}_wr_data)); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: } +////////////////////////////////////////////////////////////////////////\n"; +// Instance 16 256bx8 RAMs as local shared buffers //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $serial; +//: my $bits; +//: my $depth; +//: $bits = 8*8; +//: $depth = 256 / 16; +//: for($i = 0; $i < 16; $i ++) { +//: $serial = sprintf("%02d", $i); +//: print qq { +//: nv_ram_rws_${depth}x${bits} u_shared_buffer_${serial} ( +//: .clk (nvdla_core_clk) //|< i +//: ,.ra (sbuf_ra_${serial}) //|< r +//: ,.re (sbuf_re_${serial}) //|< r +//: ,.dout (sbuf_rdat_${serial}) //|> w +//: ,.wa (sbuf_wa_${serial}) //|< r +//: ,.we (sbuf_we_${serial}) //|< r +//: ,.di (sbuf_wdat_${serial}) //|< r +//: ,.pwrbus_ram_pd (pwrbus_ram_pd) //|< i +//: );\n\n}; +//: } +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage 1 //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: my $b1; +//: my $b0; +//: my $bits; +//: +//: $b1 = int(log(256)/log(2)) - 1; +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)); +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: assign ${name}2sbuf_p0_rd_bsel = ${name}2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign ${name}2sbuf_p1_rd_bsel = ${name}2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: } +//: +//: if($def_wino) { +//: $b1 = int(log(256)/log(2)) - 1; +//: $b0 = int(log(256)/log(2)) - int(log(16)/log(2)) + 2; +//: print qq ( +//: assign wg2sbuf_p0_rd_bsel = wg2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign wg2sbuf_p1_rd_bsel = wg2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: print qq (\n\n); +//: +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(16)/log(2)); +//: for($i = 0; $i < @input_list_1; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list_1[$i]; +//: print qq (assign ${name}2sbuf_p${k}_rd_sel_${serial} = (${name}2sbuf_p${k}_rd_bsel == ${bits}'d${j}) & ${name}2sbuf_p${k}_rd_en;\n); +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(16)/log(2)) - 2; +//: $i = int($j/4); +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign wg2sbuf_p${k}_rd_sel_${serial} = (wg2sbuf_p${k}_rd_bsel == ${bits}'d${i}) & wg2sbuf_p${k}_rd_en;\n); +//: } +//: } +//: print qq (\n\n); +//: +//: } +//: for($j = 0; $j < 16; $j ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (assign sbuf_p${k}_re_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq (${name}2sbuf_p${k}_rd_sel_${serial}); +//: if($i != @input_list - 1) { +//: print qq ( | ); +//: } else { +//: print qq (;\n); +//: } +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (assign sbuf_re_${serial} = sbuf_p0_re_${serial} | sbuf_p1_re_${serial};\n); +//: } +//: print qq (\n\n); +//: +//: $b1 = int(log(256)/log(2)) - int(log(16)/log(2)) - 1; +//: $b0 = 0; +//: for($i = 0; $i < @input_list_1; $i ++) { +//: $name = $input_list_1[$i]; +//: print qq ( +//: assign ${name}2sbuf_p0_rd_esel = ${name}2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign ${name}2sbuf_p1_rd_esel = ${name}2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: } +//: +//: if($def_wino) { +//: $b1 = int(log(256)/log(2)) - int(log(16)/log(2)) + 1; +//: $b0 = 2; +//: print qq ( +//: assign wg2sbuf_p0_rd_esel = wg2sbuf_p0_rd_addr[${b1}:${b0}]; +//: assign wg2sbuf_p1_rd_esel = wg2sbuf_p1_rd_addr[${b1}:${b0}];\n); +//: print qq (\n\n); +//: +//: } +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: $bits = int(log(256)/log(2)) - int(log(16)/log(2)); +//: print qq (assign sbuf_ra_${serial} = ); +//: for($i = 0; $i < @input_list; $i ++) { +//: for($k = 0; $k < 2; $k ++) { +//: $name = $input_list[$i]; +//: print qq (({${bits}{${name}2sbuf_p${k}_rd_sel_${serial}}} & ${name}2sbuf_p${k}_rd_esel)); +//: if($i != @input_list - 1 || $k != 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n\n); +//: } +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq(assign sbuf_p${k}_wg_sel_q${i} = (wg2sbuf_p${k}_rd_addr[1:0] == 2'h${i}) & wg2sbuf_p${k}_rd_en;\n); +//: } +//: } +//: print qq (\n\n); +//: } +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage1 register //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $j; +//: my $k; +//: my $serial; +//: my $val; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my $name; +//: +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: for($k = 0; $k < 2; $k ++) { +//: if($def_wino) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_re_${serial} & ~wg2sbuf_p${k}_rd_en\" -q sbuf_p${k}_re_${serial}_norm_d1"); +//: } else { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_re_${serial}\" -q sbuf_p${k}_re_${serial}_norm_d1"); +//: } +//: } +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($j = 0; $j < 16/4; $j ++) { +//: $val = sprintf("%02d", $j); +//: $serial = sprintf("%02d", $j*4); +//: for($k = 0; $k < 2; $k ++) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_re_${serial} & wg2sbuf_p${k}_rd_en\" -q sbuf_p${k}_re_${val}_wg_d1"); +//: } +//: } +//: print qq (\n\n); +//: +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_p${k}_wg_sel_q${i}\" -q sbuf_p${k}_wg_sel_q${i}_d1"); +//: } +//: } +//: print qq (\n\n); +//: +//: } +//: if($def_wino) { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p0_rd_en | wg2sbuf_p0_rd_en | img2sbuf_p0_rd_en\" -q sbuf_p0_rd_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p1_rd_en | wg2sbuf_p1_rd_en | img2sbuf_p1_rd_en\" -q sbuf_p1_rd_en_d1"); +//: } else { +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p0_rd_en | img2sbuf_p0_rd_en\" -q sbuf_p0_rd_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dc2sbuf_p1_rd_en | img2sbuf_p1_rd_en\" -q sbuf_p1_rd_en_d1"); +//: } +//: print qq (\n\n); +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage2 //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $j; +//: my $k; +//: my $b1; +//: my $b0; +//: my $val; +//: my $serial; +//: my $def_wino = 0; +//: +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign sbuf_p${k}_norm_rdat = ); +//: for($j = 0; $j < 16; $j ++) { +//: $serial = sprintf("%02d", $j); +//: print qq (({8*8{sbuf_p${k}_re_${serial}_norm_d1}} & sbuf_rdat_${serial})); +//: if($j != 16 - 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n); +//: } +//: } +//: print qq (\n\n); +//: } +//: print qq (\n\n); +//: +//: if($def_wino) { +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < 4; $i ++) { +//: print qq (assign sbuf_p${k}_wg_rdat_src_${i} = ); +//: for($j = 0; $j < 16/4; $j ++) { +//: $val = sprintf("%02d", $j); +//: $serial = sprintf("%02d", $j*4 + $i); +//: print qq (({8*8{sbuf_p${k}_re_${val}_wg_d1}} & sbuf_rdat_${serial})); +//: if($j != 16/4 - 1) { +//: print qq ( |\n ); +//: } else { +//: print qq (;\n); +//: } +//: } +//: print qq (\n\n); +//: } +//: } +//: print qq (\n\n); +//: +//: for($k = 0; $k < 2; $k ++) { +//: print qq(assign sbuf_p${k}_wg_rdat = ); +//: for($i = 0; $i < 4; $i ++) { +//: $b1 = int(8*8/4 * ($i + 1) - 1); +//: $b0 = int(8*8/4 * $i); +//: print qq(\({8*8{sbuf_p${k}_wg_sel_q${i}_d1}} & \{); +//: for($j = 3; $j >= 0; $j --) { +//: print qq(sbuf_p${k}_wg_rdat_src_${j}[${b1}:${b0}]); +//: if($j != 0) { +//: print qq(, ); +//: } else { +//: print qq(\}\)); +//: } +//: } +//: if($i != 3) { +//: print qq( |\n ); +//: } else { +//: print qq(;\n); +//: } +//: } +//: print qq(\n); +//: } +//: print qq (\n\n); +//: +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign sbuf_p${k}_rdat = sbuf_p${k}_norm_rdat | sbuf_p${k}_wg_rdat;\n); +//: } +//: } else { +//: for($k = 0; $k < 2; $k ++) { +//: print qq (assign sbuf_p${k}_rdat = sbuf_p${k}_norm_rdat;\n); +//: } +//: } +//: print qq (\n\n); +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: stage2 register //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $k; +//: for($k = 0; $k < 2; $k ++) { +//: &eperl::flop("-nodeclare -norst -en \"sbuf_p${k}_rd_en_d1\" -d \"sbuf_p${k}_rdat\" -q sbuf_p${k}_rdat_d2"); +//: } +//: print qq (\n\n); +////////////////////////////////////////////////////////////////////////\n"; +// RAMs to output port: connect output data signal //\n"; +////////////////////////////////////////////////////////////////////////\n"; +//: my $i; +//: my $k; +//: my @input_list; +//: my $def_wino = 0; +//: if($def_wino) { +//: @input_list = ("dc", "wg", "img"); +//: } else { +//: @input_list = ("dc", "img"); +//: } +//: my @input_list_1 = ("dc", "img"); +//: my $name; +//: for($k = 0; $k < 2; $k ++) { +//: for($i = 0; $i < @input_list; $i ++) { +//: $name = $input_list[$i]; +//: print qq (assign ${name}2sbuf_p${k}_rd_data = sbuf_p${k}_rdat_d2;\n); +//: } +//: } +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"multiple write to shared buffer") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, ((dc2sbuf_p0_wr_en | dc2sbuf_p1_wr_en) & (img2sbuf_p0_wr_en | img2sbuf_p1_wr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"multiple read to shared buffer") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, ((dc2sbuf_p0_rd_en | dc2sbuf_p1_rd_en) & (img2sbuf_p0_rd_en | img2sbuf_p1_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"dc write same buffer") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (dc2sbuf_p0_wr_en & dc2sbuf_p1_wr_en & (dc2sbuf_p0_wr_bsel == dc2sbuf_p1_wr_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"img write same buffer") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (img2sbuf_p0_wr_en & img2sbuf_p1_wr_en & (img2sbuf_p0_wr_bsel == img2sbuf_p1_wr_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"dc read same buffer") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (dc2sbuf_p0_rd_en & dc2sbuf_p1_rd_en & (dc2sbuf_p0_rd_bsel == dc2sbuf_p1_rd_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"img read same buffer") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (img2sbuf_p0_rd_en & img2sbuf_p1_rd_en & (img2sbuf_p0_rd_bsel == img2sbuf_p1_rd_bsel))); // spyglass disable W504 SelfDeterminedExpr-ML +//for(my $i = 0; $i < 16; $i ++) { +// my $j = sprintf("%02d", $i); +// my $k = $i + 9; +// vprint qq { +// nv_assert_never #(0,0,"Error! shared ram ${j} read and write hazard!") zzz_assert_never_${k} (nvdla_core_clk, `ASSERT_RESET, (sbuf_re_${j} & sbuf_we_${j} & (sbuf_ra_${j} == sbuf_wa_${j}))); \/\/ spyglass disable W504 SelfDeterminedExpr-ML}; +//} +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_shared_buffer diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v new file mode 100644 index 0000000..36e4204 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v @@ -0,0 +1,159 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_single_reg.v +module NV_NVDLA_CDMA_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,arb_weight + ,arb_wmb + ,producer + ,flush_done + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cdma_s_arbiter_0_out; +wire [31:0] nvdla_cdma_s_cbuf_flush_status_0_out; +wire [31:0] nvdla_cdma_s_pointer_0_out; +wire [31:0] nvdla_cdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [3:0] arb_weight; +output [3:0] arb_wmb; +output producer; +// Read-only register inputs +input flush_done; +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +reg [3:0] arb_weight; +reg [3:0] arb_wmb; +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdma_s_arbiter_0_wren = (reg_offset_wr == (32'h5008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_s_cbuf_flush_status_0_wren = (reg_offset_wr == (32'h500c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_s_pointer_0_wren = (reg_offset_wr == (32'h5004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_s_status_0_wren = (reg_offset_wr == (32'h5000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdma_s_arbiter_0_out[31:0] = { 12'b0, arb_wmb, 12'b0, arb_weight }; +assign nvdla_cdma_s_cbuf_flush_status_0_out[31:0] = { 31'b0, flush_done }; +assign nvdla_cdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdma_s_arbiter_0_out + or nvdla_cdma_s_cbuf_flush_status_0_out + or nvdla_cdma_s_pointer_0_out + or nvdla_cdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h5008 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_arbiter_0_out ; + end + (32'h500c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_cbuf_flush_status_0_out ; + end + (32'h5004 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_pointer_0_out ; + end + (32'h5000 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + arb_weight[3:0] <= 4'b1111; + arb_wmb[3:0] <= 4'b0011; + producer <= 1'b0; + end else begin +// Register: NVDLA_CDMA_S_ARBITER_0 Field: arb_weight + if (nvdla_cdma_s_arbiter_0_wren) begin + arb_weight[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_CDMA_S_ARBITER_0 Field: arb_wmb + if (nvdla_cdma_s_arbiter_0_wren) begin + arb_wmb[3:0] <= reg_wr_data[19:16]; + end +// Not generating flops for read-only field NVDLA_CDMA_S_CBUF_FLUSH_STATUS_0::flush_done +// Not generating flops for read-only field NVDLA_CDMA_S_POINTER_0::consumer +// Register: NVDLA_CDMA_S_POINTER_0 Field: producer + if (nvdla_cdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h5008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_S_ARBITER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_s_arbiter_0_out, nvdla_cdma_s_arbiter_0_out); + (32'h500c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_S_CBUF_FLUSH_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_s_pointer_0_out, nvdla_cdma_s_pointer_0_out); + (32'h5000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDMA_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v.vcp new file mode 100644 index 0000000..36e4204 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v.vcp @@ -0,0 +1,159 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_single_reg.v +module NV_NVDLA_CDMA_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,arb_weight + ,arb_wmb + ,producer + ,flush_done + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cdma_s_arbiter_0_out; +wire [31:0] nvdla_cdma_s_cbuf_flush_status_0_out; +wire [31:0] nvdla_cdma_s_pointer_0_out; +wire [31:0] nvdla_cdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [3:0] arb_weight; +output [3:0] arb_wmb; +output producer; +// Read-only register inputs +input flush_done; +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +reg [3:0] arb_weight; +reg [3:0] arb_wmb; +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdma_s_arbiter_0_wren = (reg_offset_wr == (32'h5008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_s_cbuf_flush_status_0_wren = (reg_offset_wr == (32'h500c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_s_pointer_0_wren = (reg_offset_wr == (32'h5004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdma_s_status_0_wren = (reg_offset_wr == (32'h5000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdma_s_arbiter_0_out[31:0] = { 12'b0, arb_wmb, 12'b0, arb_weight }; +assign nvdla_cdma_s_cbuf_flush_status_0_out[31:0] = { 31'b0, flush_done }; +assign nvdla_cdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdma_s_arbiter_0_out + or nvdla_cdma_s_cbuf_flush_status_0_out + or nvdla_cdma_s_pointer_0_out + or nvdla_cdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h5008 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_arbiter_0_out ; + end + (32'h500c & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_cbuf_flush_status_0_out ; + end + (32'h5004 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_pointer_0_out ; + end + (32'h5000 & 32'h00000fff): begin + reg_rd_data = nvdla_cdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + arb_weight[3:0] <= 4'b1111; + arb_wmb[3:0] <= 4'b0011; + producer <= 1'b0; + end else begin +// Register: NVDLA_CDMA_S_ARBITER_0 Field: arb_weight + if (nvdla_cdma_s_arbiter_0_wren) begin + arb_weight[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_CDMA_S_ARBITER_0 Field: arb_wmb + if (nvdla_cdma_s_arbiter_0_wren) begin + arb_wmb[3:0] <= reg_wr_data[19:16]; + end +// Not generating flops for read-only field NVDLA_CDMA_S_CBUF_FLUSH_STATUS_0::flush_done +// Not generating flops for read-only field NVDLA_CDMA_S_POINTER_0::consumer +// Register: NVDLA_CDMA_S_POINTER_0 Field: producer + if (nvdla_cdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h5008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_S_ARBITER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_s_arbiter_0_out, nvdla_cdma_s_arbiter_0_out); + (32'h500c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_S_CBUF_FLUSH_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h5004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdma_s_pointer_0_out, nvdla_cdma_s_pointer_0_out); + (32'h5000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDMA_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v new file mode 100644 index 0000000..1a28924 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v @@ -0,0 +1,393 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_slcg.v +module NV_NVDLA_CDMA_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,slcg_en_src_2 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input slcg_en_src_2; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1 & slcg_en_src_2; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CDMA_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v.vcp new file mode 100644 index 0000000..1a28924 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v.vcp @@ -0,0 +1,393 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_slcg.v +module NV_NVDLA_CDMA_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,slcg_en_src_2 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input slcg_en_src_2; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1 & slcg_en_src_2; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDMA_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CDMA_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v new file mode 100644 index 0000000..a1f3cf1 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v @@ -0,0 +1,819 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_status.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_status ( + nvdla_core_clk + ,nvdla_core_rstn + ,dc2status_dat_entries + ,dc2status_dat_slices + ,dc2status_dat_updt + ,dc2status_state + ,dp2reg_consumer + ,img2status_dat_entries + ,img2status_dat_slices + ,img2status_dat_updt + ,img2status_state + ,reg2dp_data_bank + ,reg2dp_op_en + ,sc2cdma_dat_entries + ,sc2cdma_dat_pending_req + ,sc2cdma_dat_slices + ,sc2cdma_dat_updt + ,wt2status_state + ,cdma2sc_dat_entries + ,cdma2sc_dat_pending_ack + ,cdma2sc_dat_slices + ,cdma2sc_dat_updt + ,cdma_dat2glb_done_intr_pd + ,cdma_wt2glb_done_intr_pd + ,dp2reg_done + ,status2dma_free_entries + ,status2dma_fsm_switch + ,status2dma_valid_slices + ,status2dma_wr_idx + ); +///////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dc2status_dat_updt; +input [14:0] dc2status_dat_entries; +input [13:0] dc2status_dat_slices; +input img2status_dat_updt; +input [14:0] img2status_dat_entries; +input [13:0] img2status_dat_slices; +input sc2cdma_dat_updt; +input [14:0] sc2cdma_dat_entries; +input [13:0] sc2cdma_dat_slices; +output cdma2sc_dat_updt; +output [14:0] cdma2sc_dat_entries; +output [13:0] cdma2sc_dat_slices; +output [13:0] status2dma_valid_slices; +output [14:0] status2dma_free_entries; +output [14:0] status2dma_wr_idx; +input [1:0] dc2status_state; +input [1:0] img2status_state; +input [1:0] wt2status_state; +output dp2reg_done; +output status2dma_fsm_switch; +output [1:0] cdma_wt2glb_done_intr_pd; +output [1:0] cdma_dat2glb_done_intr_pd; +input sc2cdma_dat_pending_req; +output cdma2sc_dat_pending_ack; +input [0:0] reg2dp_op_en; +input [4:0] reg2dp_data_bank; +///////////////////////////////////////////////////////// +reg dat2status_done_d1; +reg [1:0] dat_done_intr; +reg [14:0] dat_entries_d1; +reg [14:0] dat_entries_d2; +reg [14:0] dat_entries_d3; +reg [14:0] dat_entries_d4; +reg [14:0] dat_entries_d5; +reg [14:0] dat_entries_d6; +reg [14:0] dat_entries_d7; +reg [14:0] dat_entries_d8; +reg [14:0] dat_entries_d9; +reg [13:0] dat_slices_d1; +reg [13:0] dat_slices_d2; +reg [13:0] dat_slices_d3; +reg [13:0] dat_slices_d4; +reg [13:0] dat_slices_d5; +reg [13:0] dat_slices_d6; +reg [13:0] dat_slices_d7; +reg [13:0] dat_slices_d8; +reg [13:0] dat_slices_d9; +reg dat_updt_d1; +reg dat_updt_d2; +reg dat_updt_d3; +reg dat_updt_d4; +reg dat_updt_d5; +reg dat_updt_d6; +reg dat_updt_d7; +reg dat_updt_d8; +reg dat_updt_d9; +reg layer_end; +reg pending_ack; +reg pending_req; +reg [5:0] real_bank; +reg [14:0] status2dma_free_entries; +reg status2dma_fsm_switch; +reg [14:0] status2dma_valid_entries; +reg [13:0] status2dma_valid_slices; +reg [14:0] status2dma_wr_idx; +reg wt2status_done_d1; +reg [1:0] wt_done_intr; +wire dat2status_done; +wire [1:0] dat_done_intr_w; +wire [14:0] dat_entries_d0; +wire [13:0] dat_slices_d0; +wire dat_updt_d0; +wire dc2status_done; +wire dc2status_pend; +wire [14:0] entries_add; +wire entries_reg_en; +wire [14:0] entries_sub; +wire img2status_done; +wire img2status_pend; +wire layer_end_w; +wire mon_status2dma_free_entries_w; +wire mon_status2dma_valid_entries_w; +wire mon_status2dma_valid_slices_w; +wire mon_status2dma_wr_idx_inc_wrap; +wire pending_ack_w; +wire real_bank_reg_en; +wire [5:0] real_bank_w; +wire [13:0] slices_add; +wire [13:0] slices_sub; +wire [14:0] status2dma_free_entries_w; +wire status2dma_fsm_switch_w; +wire [14:0] status2dma_valid_entries_w; +wire [13:0] status2dma_valid_slices_w; +wire [15:0] status2dma_wr_idx_inc; +wire [14:0] status2dma_wr_idx_inc_wrap; +wire status2dma_wr_idx_overflow; +wire [14:0] status2dma_wr_idx_w; +wire update_all; +wire update_dma; +wire wt2status_done; +wire [1:0] wt_done_intr_w; +input dp2reg_consumer; +//////////////////////////////////////////////////////////////////////// +// control CDMA working status // +//////////////////////////////////////////////////////////////////////// +assign wt2status_done = (wt2status_state == 3 ); +assign dc2status_done = (dc2status_state == 3 ); +assign dc2status_pend = (dc2status_state == 1 ); +assign img2status_done = (img2status_state == 3 ); +assign img2status_pend = (img2status_state == 1 ); +assign dat2status_done = (dc2status_done | img2status_done); +assign status2dma_fsm_switch_w = reg2dp_op_en & ~status2dma_fsm_switch & wt2status_done & dat2status_done; +assign wt_done_intr_w[0] = reg2dp_op_en & ~dp2reg_consumer & ~wt2status_done_d1 & wt2status_done; +assign wt_done_intr_w[1] = reg2dp_op_en & dp2reg_consumer & ~wt2status_done_d1 & wt2status_done; +assign dat_done_intr_w[0] = reg2dp_op_en & ~dp2reg_consumer & ~dat2status_done_d1 & dat2status_done; +assign dat_done_intr_w[1] = reg2dp_op_en & dp2reg_consumer & ~dat2status_done_d1 & dat2status_done; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"status2dma_fsm_switch_w\" -q status2dma_fsm_switch"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"reg2dp_op_en & wt2status_done\" -q wt2status_done_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"reg2dp_op_en & dat2status_done\" -q dat2status_done_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -d \"wt_done_intr_w\" -q wt_done_intr"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -d \"dat_done_intr_w\" -q dat_done_intr"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status2dma_fsm_switch <= 1'b0; + end else begin + status2dma_fsm_switch <= status2dma_fsm_switch_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2status_done_d1 <= 1'b0; + end else begin + wt2status_done_d1 <= reg2dp_op_en & wt2status_done; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat2status_done_d1 <= 1'b0; + end else begin + dat2status_done_d1 <= reg2dp_op_en & dat2status_done; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_done_intr <= {2{1'b0}}; + end else begin + wt_done_intr <= wt_done_intr_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_done_intr <= {2{1'b0}}; + end else begin + dat_done_intr <= dat_done_intr_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp2reg_done = status2dma_fsm_switch; +assign cdma_wt2glb_done_intr_pd = wt_done_intr; +assign cdma_dat2glb_done_intr_pd = dat_done_intr; +//////////////////////////////////////////////////////////////////////// +// manage data bank status // +//////////////////////////////////////////////////////////////////////// +assign layer_end_w = status2dma_fsm_switch ? 1'b1 : + reg2dp_op_en ? 1'b0 : + layer_end; +assign real_bank_w = reg2dp_data_bank + 1'b1; +assign real_bank_reg_en = reg2dp_op_en && (real_bank_w != real_bank); +assign pending_ack_w = (reg2dp_op_en & (dc2status_pend | img2status_pend)); +assign update_dma = dc2status_dat_updt | img2status_dat_updt; +assign update_all = update_dma | sc2cdma_dat_updt | (pending_ack & pending_req); +assign entries_add = ({15{dc2status_dat_updt}} & dc2status_dat_entries) | + ({15{img2status_dat_updt}} & img2status_dat_entries); +assign entries_sub = sc2cdma_dat_updt ? sc2cdma_dat_entries : 15'b0; +assign {mon_status2dma_valid_entries_w, + status2dma_valid_entries_w} = (pending_ack & pending_req) ? 15'b0 : + status2dma_valid_entries + entries_add - entries_sub; +assign slices_add = ({14{dc2status_dat_updt}} & dc2status_dat_slices) | + ({14{img2status_dat_updt}} & img2status_dat_slices); +assign slices_sub = sc2cdma_dat_updt ? sc2cdma_dat_slices : 14'b0; +assign {mon_status2dma_valid_slices_w, + status2dma_valid_slices_w} = (pending_ack & pending_req) ? 15'b0 : + status2dma_valid_slices + slices_add - slices_sub; +//: my $bank_depth = 512 ; +//: my $bankdep_bw = int( log($bank_depth)/log(2) ); +//: print qq( +//: assign {mon_status2dma_free_entries_w, +//: status2dma_free_entries_w} = {real_bank, ${bankdep_bw}'b0} - status2dma_valid_entries_w; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_status2dma_free_entries_w, +status2dma_free_entries_w} = {real_bank, 9'b0} - status2dma_valid_entries_w; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign entries_reg_en = (status2dma_free_entries_w != status2dma_free_entries); +assign status2dma_wr_idx_inc = status2dma_wr_idx + entries_add; +//: my $bank_depth = 512 ; +//: my $bankdep_bw = int( log($bank_depth)/log(2) ); +//: print qq( assign {mon_status2dma_wr_idx_inc_wrap, +//: status2dma_wr_idx_inc_wrap} = status2dma_wr_idx + entries_add - {real_bank, ${bankdep_bw}'b0}; +//: assign status2dma_wr_idx_overflow = (status2dma_wr_idx_inc >= {1'b0, real_bank, ${bankdep_bw}'b0}); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign {mon_status2dma_wr_idx_inc_wrap, +status2dma_wr_idx_inc_wrap} = status2dma_wr_idx + entries_add - {real_bank, 9'b0}; +assign status2dma_wr_idx_overflow = (status2dma_wr_idx_inc >= {1'b0, real_bank, 9'b0}); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign status2dma_wr_idx_w = (pending_ack & pending_req) ? 15'b0 : + (~update_dma) ? status2dma_wr_idx : + status2dma_wr_idx_overflow ? status2dma_wr_idx_inc_wrap : + status2dma_wr_idx_inc[15 -1:0]; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"layer_end_w\" -q layer_end"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"update_all\" -d \"status2dma_valid_entries_w\" -q status2dma_valid_entries"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"update_all\" -d \"status2dma_valid_slices_w\" -q status2dma_valid_slices"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"entries_reg_en\" -d \"status2dma_free_entries_w\" -q status2dma_free_entries"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"update_all\" -d \"status2dma_wr_idx_w\" -q status2dma_wr_idx"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"real_bank_reg_en\" -d \"real_bank_w\" -q real_bank"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pending_ack_w\" -q pending_ack"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2cdma_dat_pending_req\" -q pending_req"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_end <= 1'b1; + end else begin + layer_end <= layer_end_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status2dma_valid_entries <= {15{1'b0}}; + end else begin + if ((update_all) == 1'b1) begin + status2dma_valid_entries <= status2dma_valid_entries_w; + // VCS coverage off + end else if ((update_all) == 1'b0) begin + end else begin + status2dma_valid_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status2dma_valid_slices <= {14{1'b0}}; + end else begin + if ((update_all) == 1'b1) begin + status2dma_valid_slices <= status2dma_valid_slices_w; + // VCS coverage off + end else if ((update_all) == 1'b0) begin + end else begin + status2dma_valid_slices <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status2dma_free_entries <= {15{1'b0}}; + end else begin + if ((entries_reg_en) == 1'b1) begin + status2dma_free_entries <= status2dma_free_entries_w; + // VCS coverage off + end else if ((entries_reg_en) == 1'b0) begin + end else begin + status2dma_free_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status2dma_wr_idx <= {15{1'b0}}; + end else begin + if ((update_all) == 1'b1) begin + status2dma_wr_idx <= status2dma_wr_idx_w; + // VCS coverage off + end else if ((update_all) == 1'b0) begin + end else begin + status2dma_wr_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + real_bank <= {6{1'b0}}; + end else begin + if ((real_bank_reg_en) == 1'b1) begin + real_bank <= real_bank_w; + // VCS coverage off + end else if ((real_bank_reg_en) == 1'b0) begin + end else begin + real_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_ack <= 1'b0; + end else begin + pending_ack <= pending_ack_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req <= 1'b0; + end else begin + pending_req <= sc2cdma_dat_pending_req; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cdma2sc_dat_pending_ack = pending_ack; +//: my $latency = (3 + 3 + 3); +//: print "assign dat_updt_d0 = update_dma;\n"; +//: print "assign dat_entries_d0 = entries_add;\n"; +//: print "assign dat_slices_d0 = slices_add;\n"; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_updt_d${i}\" -q dat_updt_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"dat_updt_d${i}\" -d \"dat_entries_d${i}\" -q dat_entries_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dat_updt_d${i}\" -d \"dat_slices_d${i}\" -q dat_slices_d${j}"); +//: } +//: my $k = $latency; +//: print "assign cdma2sc_dat_updt = dat_updt_d${k};\n"; +//: print "assign cdma2sc_dat_entries = dat_entries_d${k};\n"; +//: print "assign cdma2sc_dat_slices = dat_slices_d${k};\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_updt_d0 = update_dma; +assign dat_entries_d0 = entries_add; +assign dat_slices_d0 = slices_add; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d1 <= 1'b0; + end else begin + dat_updt_d1 <= dat_updt_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d1 <= {15{1'b0}}; + end else begin + if ((dat_updt_d0) == 1'b1) begin + dat_entries_d1 <= dat_entries_d0; + // VCS coverage off + end else if ((dat_updt_d0) == 1'b0) begin + end else begin + dat_entries_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d1 <= {14{1'b0}}; + end else begin + if ((dat_updt_d0) == 1'b1) begin + dat_slices_d1 <= dat_slices_d0; + // VCS coverage off + end else if ((dat_updt_d0) == 1'b0) begin + end else begin + dat_slices_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d2 <= 1'b0; + end else begin + dat_updt_d2 <= dat_updt_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d2 <= {15{1'b0}}; + end else begin + if ((dat_updt_d1) == 1'b1) begin + dat_entries_d2 <= dat_entries_d1; + // VCS coverage off + end else if ((dat_updt_d1) == 1'b0) begin + end else begin + dat_entries_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d2 <= {14{1'b0}}; + end else begin + if ((dat_updt_d1) == 1'b1) begin + dat_slices_d2 <= dat_slices_d1; + // VCS coverage off + end else if ((dat_updt_d1) == 1'b0) begin + end else begin + dat_slices_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d3 <= 1'b0; + end else begin + dat_updt_d3 <= dat_updt_d2; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d3 <= {15{1'b0}}; + end else begin + if ((dat_updt_d2) == 1'b1) begin + dat_entries_d3 <= dat_entries_d2; + // VCS coverage off + end else if ((dat_updt_d2) == 1'b0) begin + end else begin + dat_entries_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d3 <= {14{1'b0}}; + end else begin + if ((dat_updt_d2) == 1'b1) begin + dat_slices_d3 <= dat_slices_d2; + // VCS coverage off + end else if ((dat_updt_d2) == 1'b0) begin + end else begin + dat_slices_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d4 <= 1'b0; + end else begin + dat_updt_d4 <= dat_updt_d3; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d4 <= {15{1'b0}}; + end else begin + if ((dat_updt_d3) == 1'b1) begin + dat_entries_d4 <= dat_entries_d3; + // VCS coverage off + end else if ((dat_updt_d3) == 1'b0) begin + end else begin + dat_entries_d4 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d4 <= {14{1'b0}}; + end else begin + if ((dat_updt_d3) == 1'b1) begin + dat_slices_d4 <= dat_slices_d3; + // VCS coverage off + end else if ((dat_updt_d3) == 1'b0) begin + end else begin + dat_slices_d4 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d5 <= 1'b0; + end else begin + dat_updt_d5 <= dat_updt_d4; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d5 <= {15{1'b0}}; + end else begin + if ((dat_updt_d4) == 1'b1) begin + dat_entries_d5 <= dat_entries_d4; + // VCS coverage off + end else if ((dat_updt_d4) == 1'b0) begin + end else begin + dat_entries_d5 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d5 <= {14{1'b0}}; + end else begin + if ((dat_updt_d4) == 1'b1) begin + dat_slices_d5 <= dat_slices_d4; + // VCS coverage off + end else if ((dat_updt_d4) == 1'b0) begin + end else begin + dat_slices_d5 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d6 <= 1'b0; + end else begin + dat_updt_d6 <= dat_updt_d5; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d6 <= {15{1'b0}}; + end else begin + if ((dat_updt_d5) == 1'b1) begin + dat_entries_d6 <= dat_entries_d5; + // VCS coverage off + end else if ((dat_updt_d5) == 1'b0) begin + end else begin + dat_entries_d6 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d6 <= {14{1'b0}}; + end else begin + if ((dat_updt_d5) == 1'b1) begin + dat_slices_d6 <= dat_slices_d5; + // VCS coverage off + end else if ((dat_updt_d5) == 1'b0) begin + end else begin + dat_slices_d6 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d7 <= 1'b0; + end else begin + dat_updt_d7 <= dat_updt_d6; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d7 <= {15{1'b0}}; + end else begin + if ((dat_updt_d6) == 1'b1) begin + dat_entries_d7 <= dat_entries_d6; + // VCS coverage off + end else if ((dat_updt_d6) == 1'b0) begin + end else begin + dat_entries_d7 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d7 <= {14{1'b0}}; + end else begin + if ((dat_updt_d6) == 1'b1) begin + dat_slices_d7 <= dat_slices_d6; + // VCS coverage off + end else if ((dat_updt_d6) == 1'b0) begin + end else begin + dat_slices_d7 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d8 <= 1'b0; + end else begin + dat_updt_d8 <= dat_updt_d7; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d8 <= {15{1'b0}}; + end else begin + if ((dat_updt_d7) == 1'b1) begin + dat_entries_d8 <= dat_entries_d7; + // VCS coverage off + end else if ((dat_updt_d7) == 1'b0) begin + end else begin + dat_entries_d8 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d8 <= {14{1'b0}}; + end else begin + if ((dat_updt_d7) == 1'b1) begin + dat_slices_d8 <= dat_slices_d7; + // VCS coverage off + end else if ((dat_updt_d7) == 1'b0) begin + end else begin + dat_slices_d8 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_updt_d9 <= 1'b0; + end else begin + dat_updt_d9 <= dat_updt_d8; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entries_d9 <= {15{1'b0}}; + end else begin + if ((dat_updt_d8) == 1'b1) begin + dat_entries_d9 <= dat_entries_d8; + // VCS coverage off + end else if ((dat_updt_d8) == 1'b0) begin + end else begin + dat_entries_d9 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slices_d9 <= {14{1'b0}}; + end else begin + if ((dat_updt_d8) == 1'b1) begin + dat_slices_d9 <= dat_slices_d8; + // VCS coverage off + end else if ((dat_updt_d8) == 1'b0) begin + end else begin + dat_slices_d9 <= 'bx; + // VCS coverage on + end + end +end +assign cdma2sc_dat_updt = dat_updt_d9; +assign cdma2sc_dat_entries = dat_entries_d9; +assign cdma2sc_dat_slices = dat_slices_d9; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_status__status_base_overflow__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (update_dma & status2dma_wr_idx_overflow); + endproperty +// Cover 0 : "(update_dma & status2dma_wr_idx_overflow)" + FUNCPOINT_cdma_status__status_base_overflow__0_COV : cover property (cdma_status__status_base_overflow__0_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(update_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(update_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(entries_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(update_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(real_bank_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d6))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d6))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d7))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d7))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"CDMA submodule done when op_en is invalid") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (~reg2dp_op_en & (wt2status_done | dc2status_done | wg2status_done | img2status_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are done") zzz_assert_zero_one_hot_2x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_done, wg2status_done, img2status_done})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are updating") zzz_assert_zero_one_hot_26x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_dat_updt, wg2status_dat_updt, img2status_dat_updt})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are done") zzz_assert_zero_one_hot_27x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_done, wg2status_done, img2status_done})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are pend") zzz_assert_zero_one_hot_28x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_pend, wg2status_pend, img2status_pend})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"DMA increase when pending") zzz_assert_never_29x (nvdla_core_clk, `ASSERT_RESET, (pending_ack & update_dma)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error clear") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (sc2cdma_dat_updt & ((sc2cdma_dat_entries == status2dma_valid_entries) ^ (sc2cdma_dat_slices == status2dma_valid_slices)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_entries_w is overflow!") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, (update_all & mon_status2dma_valid_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_entries_w is out of range!") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (update_all && (status2dma_valid_entries_w > 16384))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_slices_w is overflow!") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (update_all & mon_status2dma_valid_slices_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_slices_w is out of range!") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (update_all && (status2dma_valid_slices_w > 3840))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_status diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v.vcp new file mode 100644 index 0000000..0cef064 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v.vcp @@ -0,0 +1,351 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_status.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_status ( + nvdla_core_clk + ,nvdla_core_rstn + ,dc2status_dat_entries + ,dc2status_dat_slices + ,dc2status_dat_updt + ,dc2status_state + ,dp2reg_consumer + ,img2status_dat_entries + ,img2status_dat_slices + ,img2status_dat_updt + ,img2status_state + ,reg2dp_data_bank + ,reg2dp_op_en + ,sc2cdma_dat_entries + ,sc2cdma_dat_pending_req + ,sc2cdma_dat_slices + ,sc2cdma_dat_updt + ,wt2status_state + ,cdma2sc_dat_entries + ,cdma2sc_dat_pending_ack + ,cdma2sc_dat_slices + ,cdma2sc_dat_updt + ,cdma_dat2glb_done_intr_pd + ,cdma_wt2glb_done_intr_pd + ,dp2reg_done + ,status2dma_free_entries + ,status2dma_fsm_switch + ,status2dma_valid_slices + ,status2dma_wr_idx + ); +///////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dc2status_dat_updt; +input [14:0] dc2status_dat_entries; +input [13:0] dc2status_dat_slices; +input img2status_dat_updt; +input [14:0] img2status_dat_entries; +input [13:0] img2status_dat_slices; +input sc2cdma_dat_updt; +input [14:0] sc2cdma_dat_entries; +input [13:0] sc2cdma_dat_slices; +output cdma2sc_dat_updt; +output [14:0] cdma2sc_dat_entries; +output [13:0] cdma2sc_dat_slices; +output [13:0] status2dma_valid_slices; +output [14:0] status2dma_free_entries; +output [14:0] status2dma_wr_idx; +input [1:0] dc2status_state; +input [1:0] img2status_state; +input [1:0] wt2status_state; +output dp2reg_done; +output status2dma_fsm_switch; +output [1:0] cdma_wt2glb_done_intr_pd; +output [1:0] cdma_dat2glb_done_intr_pd; +input sc2cdma_dat_pending_req; +output cdma2sc_dat_pending_ack; +input [0:0] reg2dp_op_en; +input [4:0] reg2dp_data_bank; +///////////////////////////////////////////////////////// +reg dat2status_done_d1; +reg [1:0] dat_done_intr; +reg [14:0] dat_entries_d1; +reg [14:0] dat_entries_d2; +reg [14:0] dat_entries_d3; +reg [14:0] dat_entries_d4; +reg [14:0] dat_entries_d5; +reg [14:0] dat_entries_d6; +reg [14:0] dat_entries_d7; +reg [14:0] dat_entries_d8; +reg [14:0] dat_entries_d9; +reg [13:0] dat_slices_d1; +reg [13:0] dat_slices_d2; +reg [13:0] dat_slices_d3; +reg [13:0] dat_slices_d4; +reg [13:0] dat_slices_d5; +reg [13:0] dat_slices_d6; +reg [13:0] dat_slices_d7; +reg [13:0] dat_slices_d8; +reg [13:0] dat_slices_d9; +reg dat_updt_d1; +reg dat_updt_d2; +reg dat_updt_d3; +reg dat_updt_d4; +reg dat_updt_d5; +reg dat_updt_d6; +reg dat_updt_d7; +reg dat_updt_d8; +reg dat_updt_d9; +reg layer_end; +reg pending_ack; +reg pending_req; +reg [5:0] real_bank; +reg [14:0] status2dma_free_entries; +reg status2dma_fsm_switch; +reg [14:0] status2dma_valid_entries; +reg [13:0] status2dma_valid_slices; +reg [14:0] status2dma_wr_idx; +reg wt2status_done_d1; +reg [1:0] wt_done_intr; +wire dat2status_done; +wire [1:0] dat_done_intr_w; +wire [14:0] dat_entries_d0; +wire [13:0] dat_slices_d0; +wire dat_updt_d0; +wire dc2status_done; +wire dc2status_pend; +wire [14:0] entries_add; +wire entries_reg_en; +wire [14:0] entries_sub; +wire img2status_done; +wire img2status_pend; +wire layer_end_w; +wire mon_status2dma_free_entries_w; +wire mon_status2dma_valid_entries_w; +wire mon_status2dma_valid_slices_w; +wire mon_status2dma_wr_idx_inc_wrap; +wire pending_ack_w; +wire real_bank_reg_en; +wire [5:0] real_bank_w; +wire [13:0] slices_add; +wire [13:0] slices_sub; +wire [14:0] status2dma_free_entries_w; +wire status2dma_fsm_switch_w; +wire [14:0] status2dma_valid_entries_w; +wire [13:0] status2dma_valid_slices_w; +wire [15:0] status2dma_wr_idx_inc; +wire [14:0] status2dma_wr_idx_inc_wrap; +wire status2dma_wr_idx_overflow; +wire [14:0] status2dma_wr_idx_w; +wire update_all; +wire update_dma; +wire wt2status_done; +wire [1:0] wt_done_intr_w; +input dp2reg_consumer; +//////////////////////////////////////////////////////////////////////// +// control CDMA working status // +//////////////////////////////////////////////////////////////////////// +assign wt2status_done = (wt2status_state == 3 ); +assign dc2status_done = (dc2status_state == 3 ); +assign dc2status_pend = (dc2status_state == 1 ); +assign img2status_done = (img2status_state == 3 ); +assign img2status_pend = (img2status_state == 1 ); +assign dat2status_done = (dc2status_done | img2status_done); +assign status2dma_fsm_switch_w = reg2dp_op_en & ~status2dma_fsm_switch & wt2status_done & dat2status_done; +assign wt_done_intr_w[0] = reg2dp_op_en & ~dp2reg_consumer & ~wt2status_done_d1 & wt2status_done; +assign wt_done_intr_w[1] = reg2dp_op_en & dp2reg_consumer & ~wt2status_done_d1 & wt2status_done; +assign dat_done_intr_w[0] = reg2dp_op_en & ~dp2reg_consumer & ~dat2status_done_d1 & dat2status_done; +assign dat_done_intr_w[1] = reg2dp_op_en & dp2reg_consumer & ~dat2status_done_d1 & dat2status_done; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"status2dma_fsm_switch_w\" -q status2dma_fsm_switch"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"reg2dp_op_en & wt2status_done\" -q wt2status_done_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"reg2dp_op_en & dat2status_done\" -q dat2status_done_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -d \"wt_done_intr_w\" -q wt_done_intr"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -d \"dat_done_intr_w\" -q dat_done_intr"); +assign dp2reg_done = status2dma_fsm_switch; +assign cdma_wt2glb_done_intr_pd = wt_done_intr; +assign cdma_dat2glb_done_intr_pd = dat_done_intr; +//////////////////////////////////////////////////////////////////////// +// manage data bank status // +//////////////////////////////////////////////////////////////////////// +assign layer_end_w = status2dma_fsm_switch ? 1'b1 : + reg2dp_op_en ? 1'b0 : + layer_end; +assign real_bank_w = reg2dp_data_bank + 1'b1; +assign real_bank_reg_en = reg2dp_op_en && (real_bank_w != real_bank); +assign pending_ack_w = (reg2dp_op_en & (dc2status_pend | img2status_pend)); +assign update_dma = dc2status_dat_updt | img2status_dat_updt; +assign update_all = update_dma | sc2cdma_dat_updt | (pending_ack & pending_req); +assign entries_add = ({15{dc2status_dat_updt}} & dc2status_dat_entries) | + ({15{img2status_dat_updt}} & img2status_dat_entries); +assign entries_sub = sc2cdma_dat_updt ? sc2cdma_dat_entries : 15'b0; +assign {mon_status2dma_valid_entries_w, + status2dma_valid_entries_w} = (pending_ack & pending_req) ? 15'b0 : + status2dma_valid_entries + entries_add - entries_sub; +assign slices_add = ({14{dc2status_dat_updt}} & dc2status_dat_slices) | + ({14{img2status_dat_updt}} & img2status_dat_slices); +assign slices_sub = sc2cdma_dat_updt ? sc2cdma_dat_slices : 14'b0; +assign {mon_status2dma_valid_slices_w, + status2dma_valid_slices_w} = (pending_ack & pending_req) ? 15'b0 : + status2dma_valid_slices + slices_add - slices_sub; +//: my $bank_depth = 512 ; +//: my $bankdep_bw = int( log($bank_depth)/log(2) ); +//: print qq( +//: assign {mon_status2dma_free_entries_w, +//: status2dma_free_entries_w} = {real_bank, ${bankdep_bw}'b0} - status2dma_valid_entries_w; +//: ); +assign entries_reg_en = (status2dma_free_entries_w != status2dma_free_entries); +assign status2dma_wr_idx_inc = status2dma_wr_idx + entries_add; +//: my $bank_depth = 512 ; +//: my $bankdep_bw = int( log($bank_depth)/log(2) ); +//: print qq( assign {mon_status2dma_wr_idx_inc_wrap, +//: status2dma_wr_idx_inc_wrap} = status2dma_wr_idx + entries_add - {real_bank, ${bankdep_bw}'b0}; +//: assign status2dma_wr_idx_overflow = (status2dma_wr_idx_inc >= {1'b0, real_bank, ${bankdep_bw}'b0}); +//: ); +assign status2dma_wr_idx_w = (pending_ack & pending_req) ? 15'b0 : + (~update_dma) ? status2dma_wr_idx : + status2dma_wr_idx_overflow ? status2dma_wr_idx_inc_wrap : + status2dma_wr_idx_inc[15 -1:0]; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"layer_end_w\" -q layer_end"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"update_all\" -d \"status2dma_valid_entries_w\" -q status2dma_valid_entries"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"update_all\" -d \"status2dma_valid_slices_w\" -q status2dma_valid_slices"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"entries_reg_en\" -d \"status2dma_free_entries_w\" -q status2dma_free_entries"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"update_all\" -d \"status2dma_wr_idx_w\" -q status2dma_wr_idx"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"real_bank_reg_en\" -d \"real_bank_w\" -q real_bank"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pending_ack_w\" -q pending_ack"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2cdma_dat_pending_req\" -q pending_req"); +assign cdma2sc_dat_pending_ack = pending_ack; +//: my $latency = (3 + 3 + 3); +//: print "assign dat_updt_d0 = update_dma;\n"; +//: print "assign dat_entries_d0 = entries_add;\n"; +//: print "assign dat_slices_d0 = slices_add;\n"; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_updt_d${i}\" -q dat_updt_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"dat_updt_d${i}\" -d \"dat_entries_d${i}\" -q dat_entries_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dat_updt_d${i}\" -d \"dat_slices_d${i}\" -q dat_slices_d${j}"); +//: } +//: my $k = $latency; +//: print "assign cdma2sc_dat_updt = dat_updt_d${k};\n"; +//: print "assign cdma2sc_dat_entries = dat_entries_d${k};\n"; +//: print "assign cdma2sc_dat_slices = dat_slices_d${k};\n"; +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_status__status_base_overflow__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (update_dma & status2dma_wr_idx_overflow); + endproperty +// Cover 0 : "(update_dma & status2dma_wr_idx_overflow)" + FUNCPOINT_cdma_status__status_base_overflow__0_COV : cover property (cdma_status__status_base_overflow__0_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(update_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(update_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(entries_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(update_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(real_bank_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d3))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d4))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d5))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d6))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d6))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d7))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d7))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dat_updt_d8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"CDMA submodule done when op_en is invalid") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (~reg2dp_op_en & (wt2status_done | dc2status_done | wg2status_done | img2status_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are done") zzz_assert_zero_one_hot_2x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_done, wg2status_done, img2status_done})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are updating") zzz_assert_zero_one_hot_26x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_dat_updt, wg2status_dat_updt, img2status_dat_updt})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are done") zzz_assert_zero_one_hot_27x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_done, wg2status_done, img2status_done})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,3,0,"Two of DC, WG and IMG are pend") zzz_assert_zero_one_hot_28x (nvdla_core_clk, `ASSERT_RESET, ({dc2status_pend, wg2status_pend, img2status_pend})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"DMA increase when pending") zzz_assert_never_29x (nvdla_core_clk, `ASSERT_RESET, (pending_ack & update_dma)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error clear") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (sc2cdma_dat_updt & ((sc2cdma_dat_entries == status2dma_valid_entries) ^ (sc2cdma_dat_slices == status2dma_valid_slices)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_entries_w is overflow!") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, (update_all & mon_status2dma_valid_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_entries_w is out of range!") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (update_all && (status2dma_valid_entries_w > 16384))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_slices_w is overflow!") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (update_all & mon_status2dma_valid_slices_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! status2dma_valid_slices_w is out of range!") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (update_all && (status2dma_valid_slices_w > 3840))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_status diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v new file mode 100644 index 0000000..42c0b3e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v @@ -0,0 +1,4457 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_wg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_wg ( + nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,mcif2wg_dat_rd_rsp_pd //|< i + ,mcif2wg_dat_rd_rsp_valid //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_conv_x_stride //|< i + ,reg2dp_conv_y_stride //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_data_reuse //|< i + ,reg2dp_datain_addr_high_0 //|< i + ,reg2dp_datain_addr_low_0 //|< i + ,reg2dp_datain_channel //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_datain_height //|< i + ,reg2dp_datain_height_ext //|< i + ,reg2dp_datain_ram_type //|< i + ,reg2dp_datain_width //|< i + ,reg2dp_datain_width_ext //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_entries //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_line_stride //|< i + ,reg2dp_op_en //|< i + ,reg2dp_pad_bottom //|< i * + ,reg2dp_pad_left //|< i + ,reg2dp_pad_right //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_skip_data_rls //|< i + ,reg2dp_surf_stride //|< i + ,sc2cdma_dat_pending_req //|< i + ,status2dma_free_entries //|< i + ,status2dma_fsm_switch //|< i + ,status2dma_valid_slices //|< i * + ,status2dma_wr_idx //|< i + ,wg2sbuf_p0_rd_data //|< i + ,wg2sbuf_p1_rd_data //|< i + ,wg_dat2mcif_rd_req_ready //|< i + ,dp2reg_wg_rd_latency //|> o + ,dp2reg_wg_rd_stall //|> o + ,mcif2wg_dat_rd_rsp_ready //|> o + ,slcg_wg_gate_dc //|> o + ,slcg_wg_gate_img //|> o + ,wg2cvt_dat_wr_addr //|> o + ,wg2cvt_dat_wr_data //|> o + ,wg2cvt_dat_wr_en //|> o + ,wg2cvt_dat_wr_sel //|> o + ,wg2cvt_dat_wr_info_pd //|> o + ,wg2sbuf_p0_rd_addr //|> o + ,wg2sbuf_p0_rd_en //|> o + ,wg2sbuf_p0_wr_addr //|> o + ,wg2sbuf_p0_wr_data //|> o + ,wg2sbuf_p0_wr_en //|> o + ,wg2sbuf_p1_rd_addr //|> o + ,wg2sbuf_p1_rd_en //|> o + ,wg2sbuf_p1_wr_addr //|> o + ,wg2sbuf_p1_wr_data //|> o + ,wg2sbuf_p1_wr_en //|> o + ,wg2status_dat_entries //|> o + ,wg2status_dat_slices //|> o + ,wg2status_dat_updt //|> o + ,wg2status_state //|> o + ,wg_dat2mcif_rd_req_pd //|> o + ,wg_dat2mcif_rd_req_valid //|> o + ); +// +// NV_NVDLA_CDMA_wg_ports.v +// +input nvdla_core_clk; /* wg_dat2mcif_rd_req, wg_dat2cvif_rd_req, mcif2wg_dat_rd_rsp, cvif2wg_dat_rd_rsp, wg2cvt_dat_wr, wg2cvt_dat_wr_info, switch_status2dma, state_wg2status, dat_up_wg2status, bc_status2dma, wg2sbuf_p0_wr, wg2sbuf_p1_wr, wg2sbuf_p0_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p0_rd_nvdla_ram_data_DATA_WIDTH_256, wg2sbuf_p1_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p1_rd_nvdla_ram_data_DATA_WIDTH_256, sc2cdma_dat_pending */ +input nvdla_core_rstn; /* wg_dat2mcif_rd_req, wg_dat2cvif_rd_req, mcif2wg_dat_rd_rsp, cvif2wg_dat_rd_rsp, wg2cvt_dat_wr, wg2cvt_dat_wr_info, switch_status2dma, state_wg2status, dat_up_wg2status, bc_status2dma, wg2sbuf_p0_wr, wg2sbuf_p1_wr, wg2sbuf_p0_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p0_rd_nvdla_ram_data_DATA_WIDTH_256, wg2sbuf_p1_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p1_rd_nvdla_ram_data_DATA_WIDTH_256, sc2cdma_dat_pending */ +input [31:0] pwrbus_ram_pd; +output wg_dat2mcif_rd_req_valid; /* data valid */ +input wg_dat2mcif_rd_req_ready; /* data return handshake */ +output [78:0] wg_dat2mcif_rd_req_pd; +input mcif2wg_dat_rd_rsp_valid; /* data valid */ +output mcif2wg_dat_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2wg_dat_rd_rsp_pd; +output wg2cvt_dat_wr_en; /* data valid */ +output [11:0] wg2cvt_dat_wr_addr; +output wg2cvt_dat_wr_sel; +output [511:0] wg2cvt_dat_wr_data; +output [11:0] wg2cvt_dat_wr_info_pd; +input status2dma_fsm_switch; +output [1:0] wg2status_state; +output wg2status_dat_updt; /* data valid */ +output [14:0] wg2status_dat_entries; +output [13:0] wg2status_dat_slices; +input [13:0] status2dma_valid_slices; +input [14:0] status2dma_free_entries; +input [11:0] status2dma_wr_idx; +output wg2sbuf_p0_wr_en; /* data valid */ +output [7:0] wg2sbuf_p0_wr_addr; +output [255:0] wg2sbuf_p0_wr_data; +output wg2sbuf_p1_wr_en; /* data valid */ +output [7:0] wg2sbuf_p1_wr_addr; +output [255:0] wg2sbuf_p1_wr_data; +output wg2sbuf_p0_rd_en; /* data valid */ +output [7:0] wg2sbuf_p0_rd_addr; +input [255:0] wg2sbuf_p0_rd_data; +output wg2sbuf_p1_rd_en; /* data valid */ +output [7:0] wg2sbuf_p1_rd_addr; +input [255:0] wg2sbuf_p1_rd_data; +input sc2cdma_dat_pending_req; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [0:0] reg2dp_datain_format; +input [12:0] reg2dp_datain_width; +input [12:0] reg2dp_datain_height; +input [12:0] reg2dp_datain_width_ext; +input [12:0] reg2dp_datain_height_ext; +input [12:0] reg2dp_datain_channel; +input [0:0] reg2dp_datain_ram_type; +input [31:0] reg2dp_datain_addr_high_0; +input [26:0] reg2dp_datain_addr_low_0; +input [26:0] reg2dp_line_stride; +input [26:0] reg2dp_surf_stride; +input [13:0] reg2dp_entries; +input [2:0] reg2dp_conv_x_stride; +input [2:0] reg2dp_conv_y_stride; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +input [4:0] reg2dp_pad_top; +input [5:0] reg2dp_pad_bottom; +input [15:0] reg2dp_pad_value; +input [4:0] reg2dp_data_bank; +input [0:0] reg2dp_dma_en; +output slcg_wg_gate_dc; +output slcg_wg_gate_img; +output [31:0] dp2reg_wg_rd_stall; +output [31:0] dp2reg_wg_rd_latency; +reg [26:0] c_offset_d1; +reg [3:0] conv_x_stride; +reg [10:0] conv_xy_stride; +reg [3:0] conv_y_stride; +reg [1:0] cur_state; +reg [4:0] data_bank; +reg [14:0] data_entries; +reg [13:0] data_height; +reg [9:0] data_surf; +reg [11:0] data_width_ext; +reg [4:0] delay_cnt; +reg [3:0] dma_rsp_size; +reg [3:0] dma_rsp_size_cnt; +reg [31:0] dp2reg_wg_rd_latency; +reg [31:0] dp2reg_wg_rd_stall; +reg [14:0] h_coord; +reg [14:0] h_coord_sub_h; +reg [14:0] h_coord_surf; +reg [10:0] h_ext_surf; +reg [10:0] height_ext_total; +reg is_cbuf_ready; +reg is_req_done; +reg is_rsp_done; +reg is_running_d1; +reg is_x_stride_one; +reg [4:0] last_data_bank; +reg [3:0] last_lp; +reg [3:0] last_rp; +reg last_skip_data_rls; +reg last_wg; +reg layer_st_d1; +reg [4:0] lp_end; +reg ltc_1_adv; +reg [8:0] ltc_1_cnt_cur; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg ltc_2_adv; +reg [31:0] ltc_2_cnt_cur; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg no_lp; +reg [1:0] nxt_state; +reg [8:0] outs_dp2reg_wg_rd_latency; +reg pending_req; +reg pending_req_d1; +reg [3:0] rd_cube_cnt; +reg [2:0] rd_sub_cnt; +reg [58:0] req_addr_d2; +reg req_dummy_d1; +reg req_dummy_d2; +reg [10:0] req_h_ext_cnt; +reg [3:0] req_size_d1; +reg [3:0] req_size_d2; +reg [2:0] req_size_out_d1; +reg [2:0] req_size_out_d2; +reg [1:0] req_sub_h_cnt; +reg [12:0] req_sub_w_cnt; +reg [8:0] req_surf_cnt; +reg req_valid_d1; +reg req_valid_d2; +reg [1:0] req_w_set_cnt; +reg [2:0] req_y_std_cnt; +reg [5:0] rp_end; +reg [11:0] rsp_addr_base; +reg [11:0] rsp_addr_d1; +reg [11:0] rsp_addr_offset; +reg [11:0] rsp_ch_offset; +reg [11:0] rsp_ch_surf_base; +reg [11:0] rsp_ch_w_base; +reg [11:0] rsp_ch_x_std_base; +reg [11:0] rsp_ch_y_std_base; +reg rsp_dat_vld_d1; +reg rsp_dat_vld_d2; +reg [511:0] rsp_data_d1; +reg [511:0] rsp_data_l0c0; +reg [511:0] rsp_data_l0c1; +reg [511:0] rsp_data_l1c0; +reg [511:0] rsp_data_l1c1; +reg rsp_en_d1; +reg [10:0] rsp_h_ext_cnt; +reg rsp_hsel_d1; +reg rsp_layer_done_d1; +reg rsp_slice_done_d1; +reg [2:0] rsp_sub_cube_cnt; +reg [8:0] rsp_surf_cnt; +reg [10:0] rsp_width_cnt; +reg [2:0] rsp_x_std_cnt; +reg [2:0] rsp_y_std_cnt; +reg [3:0] sbuf_avl_cube; +reg sbuf_blocking; +reg sbuf_cube_inc_en_d1; +reg [3:0] sbuf_cube_inc_size_d1; +reg sbuf_rd_en_d1; +reg [7:0] sbuf_rd_p0_idx_d1; +reg [7:0] sbuf_rd_p1_idx_d1; +reg [1:0] sbuf_rd_sel_d1; +reg [1:0] sbuf_wr_line; +reg [3:0] sbuf_wr_p0_base; +reg [3:0] sbuf_wr_p0_base_ori; +reg [3:0] sbuf_wr_p0_ch; +reg [3:0] sbuf_wr_p0_ch_ori; +reg [255:0] sbuf_wr_p0_data_d1; +reg sbuf_wr_p0_en_d1; +reg [7:0] sbuf_wr_p0_idx_d1; +reg [2:0] sbuf_wr_p0_offset; +reg [2:0] sbuf_wr_p0_offset_ori; +reg [3:0] sbuf_wr_p1_base; +reg [3:0] sbuf_wr_p1_base_ori; +reg [1:0] sbuf_wr_p1_ch; +reg [1:0] sbuf_wr_p1_ch_ori; +reg [255:0] sbuf_wr_p1_data_d1; +reg sbuf_wr_p1_en_d1; +reg [7:0] sbuf_wr_p1_idx_d1; +reg [2:0] sbuf_wr_p1_offset; +reg [2:0] sbuf_wr_p1_offset_ori; +reg [1:0] slcg_wg_gate_d1; +reg [1:0] slcg_wg_gate_d2; +reg [1:0] slcg_wg_gate_d3; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [8:0] surf_cnt_total; +reg [10:0] w_ext_surf; +reg [1:0] wg2status_state; +reg [14:0] wg_entry_onfly; +reg wg_rd_latency_cen; +reg wg_rd_latency_clr; +reg wg_rd_latency_dec; +reg wg_rd_latency_inc; +reg wg_rd_stall_cen; +reg wg_rd_stall_clr; +reg wg_rd_stall_inc; +reg [10:0] width_ext_total; +reg [1:0] width_set_total; +reg [12:0] x_offset_d1; +reg [26:0] y_offset_d1; +wire [26:0] c_offset; +wire cbuf_wr_info_ext128; +wire cbuf_wr_info_ext64; +wire cbuf_wr_info_interleave; +wire [3:0] cbuf_wr_info_mask; +wire cbuf_wr_info_mean; +wire [2:0] cbuf_wr_info_sub_h; +wire cbuf_wr_info_uint; +wire [3:0] conv_x_stride_w; +wire [10:0] conv_xy_stride_w; +wire [3:0] conv_y_stride_w; +wire [1023:0] dat_cur; +wire [1023:0] dat_cur_remapped; +wire [14:0] data_entries_add; +wire [14:0] data_entries_w; +wire [14:0] data_height_st_w; +wire [13:0] data_height_w; +wire [9:0] data_surf_w; +wire [11:0] data_width_ext_w; +wire [4:0] delay_cnt_end; +wire [4:0] delay_cnt_w; +wire [511:0] dma_pad_data; +wire [63:0] dma_rd_req_addr; +wire [78:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [15:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire dma_rd_rsp_blocking; +wire [511:0] dma_rd_rsp_data; +wire [1:0] dma_rd_rsp_mask; +wire [513:0] dma_rd_rsp_pd; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [4:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire [511:0] dma_rsp_data; +wire [255:0] dma_rsp_data_p0; +wire [255:0] dma_rsp_data_p1; +wire dma_rsp_dummy; +wire [4:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire [1:0] dma_rsp_mask; +wire [3:0] dma_rsp_size_cnt_inc; +wire [3:0] dma_rsp_size_cnt_w; +wire dma_rsp_vld; +wire dp2reg_wg_rd_stall_dec; +wire fetch_done; +wire [14:0] h_coord_w; +wire [10:0] h_ext_surf_w; +wire height_dummy; +wire is_cbuf_ready_w; +wire is_done; +wire is_feature; +wire is_first_running; +wire is_idle; +wire is_int8; +wire is_last_req; +wire is_last_rsp; +wire is_pending; +wire is_req_done_w; +wire is_req_last_di; +wire is_req_last_h_ext; +wire is_req_last_lp; +wire is_req_last_rp; +wire is_req_last_sub_h; +wire is_req_last_sub_w; +wire is_req_last_surf; +wire is_req_last_w_set; +wire is_req_last_width; +wire is_req_last_y_std; +wire is_rsp_addr_wrap; +wire is_rsp_done_w; +wire is_rsp_last_h_ext; +wire is_rsp_last_sub_cube; +wire is_rsp_last_surf; +wire is_rsp_last_width; +wire is_rsp_last_x_std; +wire is_rsp_last_y_std; +wire is_running; +wire is_sbuf_wr_last_line; +wire is_slice_done; +wire is_w_set_di; +wire is_w_set_lp; +wire is_w_set_rp; +wire is_wg; +wire is_x_stride_one_w; +wire [3:0] last_lp_w; +wire [3:0] last_rp_w; +wire layer_st; +wire [4:0] lp_end_w; +wire ltc_1_dec; +wire ltc_1_inc; +wire ltc_2_dec; +wire ltc_2_inc; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [513:0] mc_dma_rd_rsp_pd; +wire mc_dma_rd_rsp_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire [513:0] mc_int_rd_rsp_pd; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire mc_rd_req_rdyi; +wire [513:0] mcif2wg_dat_rd_rsp_pd_d0; +wire mcif2wg_dat_rd_rsp_ready_d0; +wire mcif2wg_dat_rd_rsp_valid_d0; +wire mode_match; +wire [8:0] mon_c_offset; +wire [4:0] mon_conv_xy_stride_w; +wire mon_data_entries_w; +wire mon_delay_cnt_w; +wire mon_dma_rsp_size_cnt_inc; +wire mon_h_coord_w; +wire [9:0] mon_h_ext_surf_w; +wire mon_lp_end_w; +wire mon_rd_cube_cnt_w; +wire mon_rd_sub_cnt_w; +wire mon_req_addr_w; +wire mon_req_cubf_needed; +wire mon_req_h_ext_cnt_inc; +wire mon_req_size_out; +wire mon_req_sub_h_cnt_w; +wire mon_req_sub_w_cnt_inc; +wire mon_req_surf_cnt_inc; +wire mon_req_w_set_cnt_inc; +wire mon_req_y_std_cnt_inc; +wire mon_rp_end_w; +wire mon_rsp_addr_inc; +wire mon_rsp_addr_offset_w; +wire [1:0] mon_rsp_addr_wrap; +wire mon_rsp_ch_offset_w; +wire mon_rsp_h_ext_cnt_inc; +wire mon_rsp_sub_cube_cnt_inc; +wire mon_rsp_surf_cnt_inc; +wire mon_rsp_width_cnt_inc; +wire mon_rsp_x_std_cnt_inc; +wire mon_rsp_y_std_cnt_inc; +wire mon_sbuf_avl_cube_w; +wire mon_sbuf_wr_line_w; +wire mon_sbuf_wr_p0_base_w; +wire mon_sbuf_wr_p0_ch_inc; +wire mon_sbuf_wr_p0_idx_lo; +wire mon_sbuf_wr_p1_base_w; +wire mon_sbuf_wr_p1_ch_inc; +wire mon_sbuf_wr_p1_idx_lo; +wire [10:0] mon_w_ext_surf_w; +wire mon_wg_entry_onfly_w; +wire [12:0] mon_y_offset; +wire need_pending; +wire no_lp_w; +wire pending_req_end; +wire [3:0] rd_cube_cnt_w; +wire rd_req_rdyi; +wire [2:0] rd_sub_cnt_w; +wire [58:0] req_addr_base; +wire [58:0] req_addr_w; +wire req_adv; +wire [14:0] req_cbuf_needed; +wire [10:0] req_h_ext_cnt_inc; +wire [10:0] req_h_ext_cnt_w; +wire req_h_ext_en; +wire req_ready; +wire req_ready_d1; +wire req_ready_d2; +wire [3:0] req_size; +wire [2:0] req_size_out; +wire [1:0] req_sub_h_cnt_w; +wire req_sub_h_en; +wire [12:0] req_sub_w_cnt_inc; +wire [12:0] req_sub_w_cnt_w; +wire [3:0] req_sub_w_cur; +wire req_sub_w_en; +wire [8:0] req_surf_cnt_inc; +wire [8:0] req_surf_cnt_w; +wire req_surf_en; +wire req_valid; +wire req_valid_d1_w; +wire req_valid_d2_w; +wire [1:0] req_w_set_cnt_inc; +wire [1:0] req_w_set_cnt_w; +wire req_w_set_en; +wire [2:0] req_y_std_cnt_inc; +wire [2:0] req_y_std_cnt_w; +wire req_y_std_en; +wire [5:0] rp_end_w; +wire [11:0] rsp_addr; +wire [12:0] rsp_addr_inc; +wire [11:0] rsp_addr_offset_w; +wire [11:0] rsp_addr_wrap; +wire rsp_ch_offset_en; +wire [11:0] rsp_ch_offset_w; +wire [11:0] rsp_ch_surf_add; +wire rsp_ch_surf_base_en; +wire rsp_ch_w_base_en; +wire [11:0] rsp_ch_x_std_add; +wire rsp_ch_x_std_base_en; +wire [11:0] rsp_ch_y_std_add; +wire rsp_ch_y_std_base_en; +wire [511:0] rsp_data_d1_w; +wire [1023:0] rsp_data_l0; +wire rsp_data_l0c0_en; +wire rsp_data_l0c1_en; +wire [1023:0] rsp_data_l1; +wire rsp_data_l1c0_en; +wire rsp_data_l1c1_en; +wire rsp_en; +wire [10:0] rsp_h_ext_cnt_inc; +wire [10:0] rsp_h_ext_cnt_w; +wire rsp_h_ext_en; +wire rsp_hsel; +wire [1:0] rsp_sel; +wire [1:0] rsp_sel_d0; +wire [2:0] rsp_sub_cube_cnt_inc; +wire [2:0] rsp_sub_cube_cnt_w; +wire rsp_sub_cube_en; +wire [8:0] rsp_surf_cnt_inc; +wire [8:0] rsp_surf_cnt_w; +wire rsp_surf_en; +wire rsp_vld; +wire rsp_vld_d0; +wire [10:0] rsp_width_cnt_inc; +wire [10:0] rsp_width_cnt_w; +wire rsp_width_en; +wire [2:0] rsp_x_std_cnt_inc; +wire [2:0] rsp_x_std_cnt_w; +wire rsp_x_std_en; +wire [2:0] rsp_y_std_cnt_inc; +wire [2:0] rsp_y_std_cnt_w; +wire rsp_y_std_en; +wire [3:0] sbuf_avl_cube_add; +wire sbuf_avl_cube_en; +wire sbuf_avl_cube_sub; +wire [3:0] sbuf_avl_cube_w; +wire sbuf_blocking_w; +wire sbuf_cube_inc_en; +wire [3:0] sbuf_cube_inc_size; +wire sbuf_rd_en; +wire [7:0] sbuf_rd_p0_idx; +wire [7:0] sbuf_rd_p1_idx; +wire [1:0] sbuf_wr_add; +wire sbuf_wr_addr_en; +wire sbuf_wr_addr_ori_en; +wire [1:0] sbuf_wr_line_w; +wire [3:0] sbuf_wr_p0_base_w; +wire [3:0] sbuf_wr_p0_ch_inc; +wire [3:0] sbuf_wr_p0_ch_w; +wire sbuf_wr_p0_en; +wire [7:0] sbuf_wr_p0_idx; +wire [3:0] sbuf_wr_p0_idx_lo; +wire sbuf_wr_p0_of; +wire sbuf_wr_p0_of_0; +wire sbuf_wr_p0_of_1; +wire [3:0] sbuf_wr_p0_offset_inc; +wire [2:0] sbuf_wr_p0_offset_w; +wire [3:0] sbuf_wr_p1_base_w; +wire [1:0] sbuf_wr_p1_ch_inc; +wire [1:0] sbuf_wr_p1_ch_w; +wire sbuf_wr_p1_en; +wire [7:0] sbuf_wr_p1_idx; +wire [3:0] sbuf_wr_p1_idx_lo; +wire sbuf_wr_p1_of; +wire sbuf_wr_p1_of_0; +wire sbuf_wr_p1_of_1; +wire [3:0] sbuf_wr_p1_offset_inc; +wire [2:0] sbuf_wr_p1_offset_w; +wire [1:0] sbuf_x_stride_inc_size; +wire slcg_wg_en_w; +wire [1:0] slcg_wg_gate_w; +wire [8:0] surf_cnt_total_w; +wire [10:0] w_ext_surf_w; +wire [1:0] wg2status_state_w; +wire wg_en; +wire [14:0] wg_entry_onfly_add; +wire wg_entry_onfly_en; +wire [14:0] wg_entry_onfly_sub; +wire [14:0] wg_entry_onfly_w; +wire width_dummy; +wire [1:0] width_set_total_w; +wire [12:0] x_offset; +wire [26:0] y_offset; +//////////////////////////////////////////////////////////////////////// +// CDMA winograd convolution data fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +//## fsm (1) defines +localparam WG_STATE_IDLE = 2'b00; +localparam WG_STATE_PEND = 2'b01; +localparam WG_STATE_BUSY = 2'b10; +localparam WG_STATE_DONE = 2'b11; +//## fsm (1) com block +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + WG_STATE_IDLE: begin + if ((wg_en & need_pending)) begin + nxt_state = WG_STATE_PEND; + end + else if ((wg_en & reg2dp_data_reuse & last_skip_data_rls & mode_match)) begin + nxt_state = WG_STATE_DONE; + end + else if (wg_en) begin + nxt_state = WG_STATE_BUSY; + end + end + WG_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = WG_STATE_BUSY; + end + end + WG_STATE_BUSY: begin + if (fetch_done) begin + nxt_state = WG_STATE_DONE; + end + end + WG_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = WG_STATE_IDLE; + end + end + endcase + end +end +//## fsm (1) seq block +//: &eperl::flop("-nodeclare -rval \"WG_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_state <= WG_STATE_IDLE; + end else begin + cur_state <= nxt_state; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign fetch_done = is_running & is_req_done & is_rsp_done & (delay_cnt == delay_cnt_end); +assign delay_cnt_end = (3 + 3 + 3 ) ; +assign {mon_delay_cnt_w, + delay_cnt_w} = ~is_running ? 6'b0 : + is_rsp_done ? delay_cnt + 1'b1 : + {1'b0, delay_cnt}; +assign need_pending = (last_data_bank != reg2dp_data_bank); +assign mode_match = wg_en & last_wg; +assign is_feature = (reg2dp_datain_format == 1'h0 ); +assign is_wg = (reg2dp_conv_mode == 1'h1 ); +assign wg_en = reg2dp_op_en & is_wg & is_feature; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"is_rsp_done | is_done\" -d \"delay_cnt_w\" -q delay_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + delay_cnt <= {5{1'b0}}; + end else begin + if ((is_rsp_done | is_done) == 1'b1) begin + delay_cnt <= delay_cnt_w; + // VCS coverage off + end else if ((is_rsp_done | is_done) == 1'b0) begin + end else begin + delay_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = wg_en & is_idle; +assign is_idle = (cur_state == WG_STATE_IDLE); +assign is_pending = (cur_state == WG_STATE_PEND); +assign is_running = (cur_state == WG_STATE_BUSY); +assign is_done = (cur_state == WG_STATE_DONE); +assign is_first_running = ~is_running_d1 & is_running; +assign wg2status_state_w = (nxt_state == WG_STATE_PEND) ? 1 : + (nxt_state == WG_STATE_BUSY) ? 2 : + (nxt_state == WG_STATE_DONE) ? 3 : + 0 ; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"layer_st\" -q layer_st_d1"); +//: &eperl::flop("-nodeclare -rval \"0\" -d \"wg2status_state_w\" -q wg2status_state"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_st_d1 <= 1'b0; + end else begin + layer_st_d1 <= layer_st; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg2status_state <= 'b0; + end else begin + wg2status_state <= wg2status_state_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_running_d1 <= 1'b0; + end else begin + is_running_d1 <= is_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +assign pending_req_end = pending_req_d1 & ~pending_req; +//================ Non-SLCG clock domain ================// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"wg_en\" -q last_wg"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{5{1'b1}}\" -en \"reg2dp_op_en & is_idle\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"wg_en & reg2dp_skip_data_rls\" -q last_skip_data_rls"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"sc2cdma_dat_pending_req\" -q pending_req"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"pending_req\" -q pending_req_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_wg <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_wg <= wg_en; + // VCS coverage off + end else if ((reg2dp_op_en & is_idle) == 1'b0) begin + end else begin + last_wg <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_data_bank <= {5{1'b1}}; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_data_bank <= reg2dp_data_bank; + // VCS coverage off + end else if ((reg2dp_op_en & is_idle) == 1'b0) begin + end else begin + last_data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_skip_data_rls <= 1'b0; + end else begin + if ((reg2dp_op_en & is_idle) == 1'b1) begin + last_skip_data_rls <= wg_en & reg2dp_skip_data_rls; + // VCS coverage off + end else if ((reg2dp_op_en & is_idle) == 1'b0) begin + end else begin + last_skip_data_rls <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req <= 1'b0; + end else begin + pending_req <= sc2cdma_dat_pending_req; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req_d1 <= 1'b0; + end else begin + pending_req_d1 <= pending_req; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_wg_en_w = wg_en & (is_running | is_pending | is_done); +assign slcg_wg_gate_w = {2{~slcg_wg_en_w}}; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_wg_gate_w\" -q slcg_wg_gate_d1"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_wg_gate_d1\" -q slcg_wg_gate_d2"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_wg_gate_d2\" -q slcg_wg_gate_d3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_wg_gate_d1 <= {2{1'b1}}; + end else begin + slcg_wg_gate_d1 <= slcg_wg_gate_w; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_wg_gate_d2 <= {2{1'b1}}; + end else begin + slcg_wg_gate_d2 <= slcg_wg_gate_d1; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_wg_gate_d3 <= {2{1'b1}}; + end else begin + slcg_wg_gate_d3 <= slcg_wg_gate_d2; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign slcg_wg_gate_dc = slcg_wg_gate_d3[0]; +assign slcg_wg_gate_img = slcg_wg_gate_d3[1]; +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +assign is_int8 = 1'b1; +assign surf_cnt_total_w = {1'b0, reg2dp_datain_channel[12:5]}; +assign data_surf_w = {1'b0, reg2dp_datain_channel[12:5]} + 1'b1; +assign is_x_stride_one_w = ~(|reg2dp_conv_x_stride); +assign data_height_st_w = 14'b0 - reg2dp_pad_top; +assign data_height_w = reg2dp_datain_height + 1'b1; +assign data_width_ext_w = reg2dp_datain_width_ext[12:2] + 1'b1; +assign {mon_conv_xy_stride_w, + conv_xy_stride_w} = conv_x_stride_w * data_width_ext_w; +assign {mon_w_ext_surf_w, + w_ext_surf_w} = data_width_ext_w * data_surf; +assign {mon_h_ext_surf_w, + h_ext_surf_w} = conv_xy_stride * data_surf; +assign conv_x_stride_w = reg2dp_conv_x_stride + 1'b1; +assign conv_y_stride_w = reg2dp_conv_y_stride + 1'b1; +assign {mon_data_entries_w, + data_entries_w} = {reg2dp_entries[12:0], 2'b0} + 3'h4; +assign width_set_total_w[1:0] = (|reg2dp_pad_left) + (|reg2dp_pad_right); +assign no_lp_w = ~(|reg2dp_pad_left); +assign {mon_lp_end_w, + lp_end_w} = ~(|reg2dp_pad_left[2:0]) ? (reg2dp_pad_left - 4'h8) : + {reg2dp_pad_left[4:3], 3'b0}; +assign last_lp_w = ~(|reg2dp_pad_left[2:0]) ? 4'h8 : {1'b0, reg2dp_pad_left[2:0]}; +assign {mon_rp_end_w, + rp_end_w} = ~(|reg2dp_pad_right[2:0]) ? (reg2dp_pad_right - 4'h8) : + {reg2dp_pad_right[5:3], 3'b0}; +assign last_rp_w = ~(|reg2dp_pad_right[2:0]) ? 4'h8 : {1'b0, reg2dp_pad_right[2:0]}; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"is_x_stride_one_w\" -q is_x_stride_one"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_height_w\" -q data_height"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"layer_st\" -d \"surf_cnt_total_w\" -q surf_cnt_total"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st\" -d \"data_width_ext_w\" -q data_width_ext"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st\" -d \"data_surf_w\" -q data_surf"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_x_stride_w\" -q conv_x_stride"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_y_stride_w\" -q conv_y_stride"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"conv_xy_stride_w\" -q conv_xy_stride"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"layer_st\" -d \"data_entries_w\" -q data_entries"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"reg2dp_data_bank + 1'b1\" -q data_bank"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"layer_st\" -d \"width_set_total_w\" -q width_set_total"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"layer_st\" -d \"no_lp_w\" -q no_lp"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"lp_end_w\" -q lp_end"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"last_lp_w\" -q last_lp"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"rp_end_w\" -q rp_end"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"last_rp_w\" -q last_rp"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"reg2dp_datain_width_ext[12:2]\" -q width_ext_total"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"reg2dp_datain_height_ext[12:2]\" -q height_ext_total"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st_d1\" -d \"w_ext_surf_w\" -q w_ext_surf"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st_d1\" -d \"h_ext_surf_w\" -q h_ext_surf"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_x_stride_one <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + is_x_stride_one <= is_x_stride_one_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + is_x_stride_one <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_height <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_height <= data_height_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_height <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_cnt_total <= {9{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + surf_cnt_total <= surf_cnt_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + surf_cnt_total <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_width_ext <= {12{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_width_ext <= data_width_ext_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_width_ext <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_surf <= {10{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_surf <= data_surf_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_surf <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_x_stride <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + conv_x_stride <= conv_x_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + conv_x_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_y_stride <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + conv_y_stride <= conv_y_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + conv_y_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_xy_stride <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + conv_xy_stride <= conv_xy_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + conv_xy_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_entries <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_entries <= data_entries_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_bank <= reg2dp_data_bank + 1'b1; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_set_total <= {2{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + width_set_total <= width_set_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + width_set_total <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + no_lp <= 1'b1; + end else begin + if ((layer_st) == 1'b1) begin + no_lp <= no_lp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + no_lp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lp_end <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + lp_end <= lp_end_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + lp_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_lp <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + last_lp <= last_lp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + last_lp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rp_end <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + rp_end <= rp_end_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + rp_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_rp <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + last_rp <= last_rp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + last_rp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_ext_total <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + width_ext_total <= reg2dp_datain_width_ext[12:2]; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + width_ext_total <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + height_ext_total <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + height_ext_total <= reg2dp_datain_height_ext[12:2]; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + height_ext_total <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + w_ext_surf <= {11{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + w_ext_surf <= w_ext_surf_w; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + w_ext_surf <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_ext_surf <= {11{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + h_ext_surf <= h_ext_surf_w; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + h_ext_surf <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// entries on-the-fly // +//////////////////////////////////////////////////////////////////////// +//how many entries onfly +//current onfly entries + valid entries can be write in Cbuf - entries per slice +assign wg_entry_onfly_add = (~is_req_done & ~is_cbuf_ready & is_cbuf_ready_w) ? data_entries : 15'b0; +assign wg_entry_onfly_sub = wg2status_dat_updt ? wg2status_dat_entries : 15'b0; +assign {mon_wg_entry_onfly_w, + wg_entry_onfly_w} = wg_entry_onfly + wg_entry_onfly_add - wg_entry_onfly_sub; +assign wg_entry_onfly_en = wg2status_dat_updt | (~is_req_done & ~is_cbuf_ready & is_cbuf_ready_w); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"wg_entry_onfly_en\" -d \"wg_entry_onfly_w\" -q wg_entry_onfly"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_entry_onfly <= {15{1'b0}}; + end else begin + if ((wg_entry_onfly_en) == 1'b1) begin + wg_entry_onfly <= wg_entry_onfly_w; + // VCS coverage off + end else if ((wg_entry_onfly_en) == 1'b0) begin + end else begin + wg_entry_onfly <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// prepare for address generation // +//////////////////////////////////////////////////////////////////////// +//////////////// extended height count //////////////// +assign {mon_req_h_ext_cnt_inc, + req_h_ext_cnt_inc} = req_h_ext_cnt + 1'b1; +assign req_h_ext_cnt_w = layer_st ? 11'b0 : + req_h_ext_cnt_inc; +assign is_req_last_h_ext = (req_h_ext_cnt == height_ext_total); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"req_h_ext_en\" -d \"req_h_ext_cnt_w\" -q req_h_ext_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_h_ext_cnt <= {11{1'b0}}; + end else begin + if ((req_h_ext_en) == 1'b1) begin + req_h_ext_cnt <= req_h_ext_cnt_w; + // VCS coverage off + end else if ((req_h_ext_en) == 1'b0) begin + end else begin + req_h_ext_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// surface count //////////////// +assign {mon_req_surf_cnt_inc, + req_surf_cnt_inc} = req_surf_cnt + 1'b1; +assign req_surf_cnt_w = (layer_st | is_req_last_surf) ? 9'b0 : + req_surf_cnt_inc; +assign is_req_last_surf = (req_surf_cnt == surf_cnt_total); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"req_surf_en\" -d \"req_surf_cnt_w\" -q req_surf_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_surf_cnt <= {9{1'b0}}; + end else begin + if ((req_surf_en) == 1'b1) begin + req_surf_cnt <= req_surf_cnt_w; + // VCS coverage off + end else if ((req_surf_en) == 1'b0) begin + end else begin + req_surf_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// conv y stride count //////////////// +assign {mon_req_y_std_cnt_inc, + req_y_std_cnt_inc} = req_y_std_cnt + 1'b1; +assign req_y_std_cnt_w = (layer_st | is_req_last_y_std) ? 3'b0 : + req_y_std_cnt_inc; +assign is_req_last_y_std = (req_y_std_cnt == reg2dp_conv_y_stride); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"req_y_std_en\" -d \"req_y_std_cnt_w\" -q req_y_std_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_y_std_cnt <= {3{1'b0}}; + end else begin + if ((req_y_std_en) == 1'b1) begin + req_y_std_cnt <= req_y_std_cnt_w; + // VCS coverage off + end else if ((req_y_std_en) == 1'b0) begin + end else begin + req_y_std_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// width set count //////////////// +assign {mon_req_w_set_cnt_inc, + req_w_set_cnt_inc} = req_w_set_cnt + 1'b1; +assign req_w_set_cnt_w = (layer_st | is_req_last_w_set) ? 2'b0 : + req_w_set_cnt_inc; +assign is_req_last_w_set = (req_w_set_cnt == width_set_total); +assign is_w_set_rp = (req_w_set_cnt == 2'h2) | (no_lp & (req_w_set_cnt == 2'h1)); +assign is_w_set_lp = ~no_lp & (req_w_set_cnt == 2'h0); +assign is_w_set_di = no_lp ? (req_w_set_cnt == 2'h0) : (req_w_set_cnt == 2'h1); +assign width_dummy = ~is_w_set_di; +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_w_set_en\" -d \"req_w_set_cnt_w\" -q req_w_set_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_w_set_cnt <= {2{1'b0}}; + end else begin + if ((req_w_set_en) == 1'b1) begin + req_w_set_cnt <= req_w_set_cnt_w; + // VCS coverage off + end else if ((req_w_set_en) == 1'b0) begin + end else begin + req_w_set_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// sub width count //////////////// +assign {mon_req_sub_w_cnt_inc, + req_sub_w_cnt_inc} = req_sub_w_cnt + 4'h8; +assign req_sub_w_cnt_w = (layer_st | is_req_last_sub_w) ? 13'b0 : + req_sub_w_cnt_inc; +assign req_sub_w_cur = is_req_last_lp ? last_lp : + is_req_last_rp ? last_rp : + is_req_last_di ? (reg2dp_datain_width[2:0] + 1'b1) : + 4'h8; +assign is_req_last_lp = (is_w_set_lp & (~(|req_sub_w_cnt[12:5]) & (req_sub_w_cnt[4:0] == lp_end))); +assign is_req_last_rp = (is_w_set_rp & (~(|req_sub_w_cnt[12:6]) & (req_sub_w_cnt[5:0] == rp_end))); +assign is_req_last_di = (is_w_set_di & (req_sub_w_cnt == {reg2dp_datain_width[12:3], 3'b0})); +assign is_req_last_sub_w = is_req_last_lp | is_req_last_di | is_req_last_rp; +assign is_req_last_width = is_req_last_sub_w & is_req_last_w_set; +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"req_sub_w_en\" -d \"req_sub_w_cnt_w\" -q req_sub_w_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_sub_w_cnt <= {13{1'b0}}; + end else begin + if ((req_sub_w_en) == 1'b1) begin + req_sub_w_cnt <= req_sub_w_cnt_w; + // VCS coverage off + end else if ((req_sub_w_en) == 1'b0) begin + end else begin + req_sub_w_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// sub h count //////////////// +assign {mon_req_sub_h_cnt_w, + req_sub_h_cnt_w} = (layer_st | is_req_last_sub_h) ? 3'b0 : + (req_sub_h_cnt + 1'b1); +assign is_req_last_sub_h = (req_sub_h_cnt == 2'h3); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_sub_h_en\" -d \"req_sub_h_cnt_w\" -q req_sub_h_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_sub_h_cnt <= {2{1'b0}}; + end else begin + if ((req_sub_h_en) == 1'b1) begin + req_sub_h_cnt <= req_sub_h_cnt_w; + // VCS coverage off + end else if ((req_sub_h_en) == 1'b0) begin + end else begin + req_sub_h_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// loop control logic //////////////// +assign is_req_done_w = layer_st ? 1'b0 : + is_last_req ? 1'b1 : + is_req_done; +assign req_valid = is_running & ~is_req_done & is_cbuf_ready; +assign data_entries_add = (is_req_last_h_ext & is_cbuf_ready) ? 15'b0 : data_entries; +assign {mon_req_cubf_needed, + req_cbuf_needed} = data_entries_add + wg_entry_onfly; +assign is_cbuf_ready_w = (~is_running | req_h_ext_en) ? 1'b0 : + (~is_cbuf_ready) ? (req_cbuf_needed <= status2dma_free_entries) : + is_cbuf_ready; +assign req_ready = ~req_valid_d1 | req_ready_d1; +assign req_adv = req_valid & req_ready; +assign req_sub_h_en = layer_st | req_adv; +assign req_sub_w_en = layer_st | (req_adv & is_req_last_sub_h); +assign req_w_set_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w); +assign req_y_std_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set); +assign req_surf_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set & is_req_last_y_std); +assign req_h_ext_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set & is_req_last_y_std & is_req_last_surf); +assign is_last_req = (is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set & is_req_last_y_std & is_req_last_surf & is_req_last_h_ext); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"req_h_ext_en\" -d \"is_req_done_w\" -q is_req_done"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_cbuf_ready_w\" -q is_cbuf_ready"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_req_done <= 1'b1; + end else begin + if ((req_h_ext_en) == 1'b1) begin + is_req_done <= is_req_done_w; + // VCS coverage off + end else if ((req_h_ext_en) == 1'b0) begin + end else begin + is_req_done <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_cbuf_ready <= 1'b0; + end else begin + is_cbuf_ready <= is_cbuf_ready_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// height coordinate count //////////////// +assign {mon_h_coord_w, + h_coord_w} = (layer_st) ? {1'b0, data_height_st_w} : + (~is_req_last_sub_h) ? (h_coord + conv_y_stride) : + (~is_req_last_width & is_req_last_sub_h) ? {1'b0, h_coord_sub_h} : + (~is_req_last_y_std & is_req_last_width & is_req_last_sub_h) ? (h_coord_sub_h + 1'h1) : + (~is_req_last_surf & is_req_last_y_std & is_req_last_width & is_req_last_sub_h) ? {1'b0, h_coord_surf} : + (h_coord_surf + {conv_y_stride, 2'b0}); +assign height_dummy = (h_coord[13 +1]) | (h_coord[13:0] >= data_height); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"req_sub_h_en\" -d \"h_coord_w\" -q h_coord"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"req_y_std_en\" -d \"h_coord_w\" -q h_coord_sub_h"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"req_surf_en\" -d \"h_coord_w\" -q h_coord_surf"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_coord <= {15{1'b0}}; + end else begin + if ((req_sub_h_en) == 1'b1) begin + h_coord <= h_coord_w; + // VCS coverage off + end else if ((req_sub_h_en) == 1'b0) begin + end else begin + h_coord <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_coord_sub_h <= {15{1'b0}}; + end else begin + if ((req_y_std_en) == 1'b1) begin + h_coord_sub_h <= h_coord_w; + // VCS coverage off + end else if ((req_y_std_en) == 1'b0) begin + end else begin + h_coord_sub_h <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_coord_surf <= {15{1'b0}}; + end else begin + if ((req_surf_en) == 1'b1) begin + h_coord_surf <= h_coord_w; + // VCS coverage off + end else if ((req_surf_en) == 1'b0) begin + end else begin + h_coord_surf <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// package signals //////////////// +assign x_offset = req_sub_w_cnt[12:0]; +assign {mon_y_offset, + y_offset} = h_coord[12:0] * reg2dp_line_stride; +assign {mon_c_offset, + c_offset} = req_surf_cnt * reg2dp_surf_stride; +assign req_size = req_sub_w_cur; +assign {mon_req_size_out, + req_size_out} = req_sub_w_cur - 1'b1; +assign req_ready_d1 = ~req_valid_d2 | req_ready_d2; +assign req_valid_d1_w = ~is_running ? 1'b0 : + req_valid ? 1'b1 : + req_ready_d1 ? 1'b0 : + req_valid_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_d1_w\" -q req_valid_d1"); +//: &eperl::flop("-nodeclare -norst -en \"req_adv\" -d \"x_offset\" -q x_offset_d1"); +//: &eperl::flop("-nodeclare -norst -en \"req_adv\" -d \"y_offset\" -q y_offset_d1"); +//: &eperl::flop("-nodeclare -norst -en \"req_adv\" -d \"c_offset\" -q c_offset_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"req_adv\" -d \"req_size\" -q req_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"req_adv\" -d \"req_size_out\" -q req_size_out_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_adv\" -d \"width_dummy | height_dummy\" -q req_dummy_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_valid_d1 <= 1'b0; + end else begin + req_valid_d1 <= req_valid_d1_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((req_adv) == 1'b1) begin + x_offset_d1 <= x_offset; + // VCS coverage off + end else if ((req_adv) == 1'b0) begin + end else begin + x_offset_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((req_adv) == 1'b1) begin + y_offset_d1 <= y_offset; + // VCS coverage off + end else if ((req_adv) == 1'b0) begin + end else begin + y_offset_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((req_adv) == 1'b1) begin + c_offset_d1 <= c_offset; + // VCS coverage off + end else if ((req_adv) == 1'b0) begin + end else begin + c_offset_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_d1 <= {4{1'b0}}; + end else begin + if ((req_adv) == 1'b1) begin + req_size_d1 <= req_size; + // VCS coverage off + end else if ((req_adv) == 1'b0) begin + end else begin + req_size_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_out_d1 <= {3{1'b0}}; + end else begin + if ((req_adv) == 1'b1) begin + req_size_out_d1 <= req_size_out; + // VCS coverage off + end else if ((req_adv) == 1'b0) begin + end else begin + req_size_out_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_dummy_d1 <= 1'b0; + end else begin + if ((req_adv) == 1'b1) begin + req_dummy_d1 <= width_dummy | height_dummy; + // VCS coverage off + end else if ((req_adv) == 1'b0) begin + end else begin + req_dummy_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// package signals d2 //////////////// +assign req_addr_base = {reg2dp_datain_addr_high_0, reg2dp_datain_addr_low_0}; +assign {mon_req_addr_w, + req_addr_w} = req_addr_base + x_offset_d1 + y_offset_d1 + c_offset_d1; +assign req_valid_d2_w = ~is_running ? 1'b0 : + req_valid_d1 ? 1'b1 : + req_ready_d2 ? 1'b0 : + req_valid_d2; +assign req_ready_d2 = dma_req_fifo_ready & (dma_rd_req_rdy | (req_valid_d2 & req_dummy_d2)); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_d2_w\" -q req_valid_d2"); +//: &eperl::flop("-nodeclare -norst -en \"req_valid_d1 & req_ready_d1 & ~req_dummy_d1\" -d \"req_addr_w\" -q req_addr_d2"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"req_valid_d1 & req_ready_d1\" -d \"req_size_d1\" -q req_size_d2"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"req_valid_d1 & req_ready_d1\" -d \"req_size_out_d1\" -q req_size_out_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_valid_d1 & req_ready_d1\" -d \"req_dummy_d1\" -q req_dummy_d2"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_valid_d2 <= 1'b0; + end else begin + req_valid_d2 <= req_valid_d2_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((req_valid_d1 & req_ready_d1 & ~req_dummy_d1) == 1'b1) begin + req_addr_d2 <= req_addr_w; + // VCS coverage off + end else if ((req_valid_d1 & req_ready_d1 & ~req_dummy_d1) == 1'b0) begin + end else begin + req_addr_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_d2 <= {4{1'b0}}; + end else begin + if ((req_valid_d1 & req_ready_d1) == 1'b1) begin + req_size_d2 <= req_size_d1; + // VCS coverage off + end else if ((req_valid_d1 & req_ready_d1) == 1'b0) begin + end else begin + req_size_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_size_out_d2 <= {3{1'b0}}; + end else begin + if ((req_valid_d1 & req_ready_d1) == 1'b1) begin + req_size_out_d2 <= req_size_out_d1; + // VCS coverage off + end else if ((req_valid_d1 & req_ready_d1) == 1'b0) begin + end else begin + req_size_out_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_dummy_d2 <= 1'b0; + end else begin + if ((req_valid_d1 & req_ready_d1) == 1'b1) begin + req_dummy_d2 <= req_dummy_d1; + // VCS coverage off + end else if ((req_valid_d1 & req_ready_d1) == 1'b0) begin + end else begin + req_dummy_d2 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef NVDLA_PRINT_CDMA +always @ (posedge nvdla_core_clk) +begin + if(req_valid_d2 & req_ready_d2) + begin + $display("[CDMA WG REQ] Dummy = %d, Addr = 0x%010h, size = %0d, time = %0d", req_dummy_d2, req_addr_d2, req_size_d2, $stime); + end +end +`endif +//////////////////////////////////////////////////////////////////////// +// CDMA DC read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_datain_ram_type) + ,.mcif_rd_req_pd (wg_dat2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (wg_dat2mcif_rd_req_valid) + ,.mcif_rd_req_ready (wg_dat2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2wg_dat_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2wg_dat_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2wg_dat_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////// +assign dma_rd_req_pd[63:0] = dma_rd_req_addr[63:0]; +assign dma_rd_req_pd[78:64] = dma_rd_req_size[14:0]; +//assign dma_rd_req_vld = dma_req_fifo_ready & req_valid_d1 & cbuf_entry_ready; +assign dma_rd_req_vld = dma_req_fifo_ready & req_valid_d2 & ~req_dummy_d2; +assign dma_rd_req_addr = {req_addr_d2[58:0], 5'b0}; +assign dma_rd_req_size = {{13{1'b0}}, req_size_out_d2}; +assign dma_rd_req_type = reg2dp_datain_ram_type; +assign dma_rd_rsp_rdy = ~dma_rd_rsp_blocking; +NV_NVDLA_CDMA_WG_fifo u_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[4:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w + ,.rd_data (dma_rsp_fifo_data[4:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = req_valid_d2 & (dma_rd_req_rdy | req_dummy_d2); +assign dma_req_fifo_data = {req_dummy_d2, req_size_d2}; +//////////////////////////////////////////////////////////////////////// +// CDMA WG read response connection // +//////////////////////////////////////////////////////////////////////// +assign dma_rd_rsp_data[511:0] = dma_rd_rsp_pd[511:0]; +assign dma_rd_rsp_mask[1:0] = dma_rd_rsp_pd[513:512]; +assign {dma_rsp_dummy, dma_rsp_size} = dma_rsp_fifo_data; +assign dma_rd_rsp_blocking = (dma_rsp_fifo_req & dma_rsp_dummy) | sbuf_blocking; +assign dma_rsp_mask[0] = (~dma_rsp_fifo_req | sbuf_blocking) ? 1'b0 : + ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[0]) : + 1'b1; +assign dma_rsp_mask[1] = (~dma_rsp_fifo_req | sbuf_blocking) ? 1'b0 : + ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[1]) : + (dma_rsp_size[3:1] == dma_rsp_size_cnt[3:1]) ? 1'b0 : + 1'b1; +assign {mon_dma_rsp_size_cnt_inc, + dma_rsp_size_cnt_inc} = dma_rsp_size_cnt + dma_rsp_mask[0] + dma_rsp_mask[1]; +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 4'b0 : + dma_rsp_size_cnt_inc; +assign dma_rsp_vld = dma_rsp_fifo_req & ~sbuf_blocking & (dma_rsp_dummy | dma_rd_rsp_vld); +assign dma_rsp_fifo_ready = (dma_rsp_vld & (dma_rsp_size_cnt_inc == dma_rsp_size)); +assign dma_pad_data = {64{reg2dp_pad_value[7:0]}}; +assign dma_rsp_data = dma_rsp_dummy ? dma_pad_data[511:0] : dma_rd_rsp_data[511:0]; +assign {dma_rsp_data_p1, dma_rsp_data_p0} = dma_rsp_data; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"dma_rsp_vld\" -d \"dma_rsp_size_cnt_w\" -q dma_rsp_size_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rsp_size_cnt <= {4{1'b0}}; + end else begin + if ((dma_rsp_vld) == 1'b1) begin + dma_rsp_size_cnt <= dma_rsp_size_cnt_w; + // VCS coverage off + end else if ((dma_rsp_vld) == 1'b0) begin + end else begin + dma_rsp_size_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WG write data to shared buffer // +//////////////////////////////////////////////////////////////////////// +//////////////// line selection //////////////// +assign {mon_sbuf_wr_line_w, + sbuf_wr_line_w} = (layer_st) ? 3'b0 : + sbuf_wr_line + 1'b1; +assign is_sbuf_wr_last_line = (sbuf_wr_line == 2'h3); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"layer_st | dma_rsp_fifo_ready\" -d \"sbuf_wr_line_w\" -q sbuf_wr_line"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_line <= {2{1'b0}}; + end else begin + if ((layer_st | dma_rsp_fifo_ready) == 1'b1) begin + sbuf_wr_line <= sbuf_wr_line_w; + // VCS coverage off + end else if ((layer_st | dma_rsp_fifo_ready) == 1'b0) begin + end else begin + sbuf_wr_line <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// write port 0 //////////////// +assign sbuf_wr_add = dma_rsp_mask[1] ? 2'h2 : 2'h1; +assign {mon_sbuf_wr_p0_base_w, + sbuf_wr_p0_base_w} = (layer_st) ? 5'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? {1'b0, sbuf_wr_p0_base_ori} : + ((sbuf_wr_p0_ch[1:0] == 2'h3) & sbuf_wr_p0_of) ? sbuf_wr_p0_base + conv_x_stride : + ((sbuf_wr_p0_ch[1:0] == 2'h2) & is_x_stride_one & dma_rsp_mask[1]) ? sbuf_wr_p1_base + conv_x_stride : + sbuf_wr_p0_base; +assign {mon_sbuf_wr_p1_base_w, + sbuf_wr_p1_base_w} = (layer_st) ? 5'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? {1'b0, sbuf_wr_p1_base_ori} : + ((sbuf_wr_p1_ch[1:0] == 2'h3) & sbuf_wr_p1_of) ? sbuf_wr_p1_base + conv_x_stride : + ((sbuf_wr_p1_ch[1:0] == 2'h2) & is_x_stride_one & dma_rsp_mask[1]) ? sbuf_wr_p1_base + conv_x_stride : + sbuf_wr_p1_base; +assign sbuf_wr_p0_offset_inc = sbuf_wr_p0_offset + sbuf_wr_add; +assign sbuf_wr_p1_offset_inc = sbuf_wr_p1_offset + sbuf_wr_add; +assign sbuf_wr_p0_of_0 = (sbuf_wr_p0_offset_inc == conv_x_stride) | is_x_stride_one; +assign sbuf_wr_p0_of_1 = (sbuf_wr_p0_offset_inc > conv_x_stride); +assign sbuf_wr_p0_of = sbuf_wr_p0_of_0 | sbuf_wr_p0_of_1; +assign sbuf_wr_p1_of_0 = (sbuf_wr_p1_offset_inc == conv_x_stride) | is_x_stride_one; +assign sbuf_wr_p1_of_1 = (sbuf_wr_p1_offset_inc > conv_x_stride); +assign sbuf_wr_p1_of = sbuf_wr_p1_of_0 | sbuf_wr_p1_of_1; +assign sbuf_wr_p0_offset_w = (layer_st | is_x_stride_one) ? 3'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p0_offset_ori : + (sbuf_wr_p0_of_1) ? 3'b1 : + (sbuf_wr_p0_of_0) ? 3'b0 : + sbuf_wr_p0_offset_inc[2:0]; +assign sbuf_wr_p1_offset_w = (is_x_stride_one_w) ? 3'b0 : + (layer_st) ? 3'b1 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p1_offset_ori : + (sbuf_wr_p1_of_1) ? 3'b1 : + (sbuf_wr_p1_of_0) ? 3'b0 : + sbuf_wr_p1_offset_inc[2:0]; +assign {mon_sbuf_wr_p0_ch_inc, + sbuf_wr_p0_ch_inc} = (is_x_stride_one) ? (sbuf_wr_p0_ch + sbuf_wr_add) : + (sbuf_wr_p0_ch + 1'b1); +assign {mon_sbuf_wr_p1_ch_inc, + sbuf_wr_p1_ch_inc} = (is_x_stride_one) ? (sbuf_wr_p1_ch + sbuf_wr_add) : + (sbuf_wr_p1_ch + 1'b1); +assign sbuf_wr_p0_ch_w = (layer_st) ? 4'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p0_ch_ori : + (dma_rsp_fifo_ready & is_sbuf_wr_last_line & sbuf_wr_p0_of) ? {2'd0, sbuf_wr_p0_ch_inc[1:0]} : + (dma_rsp_fifo_ready & is_sbuf_wr_last_line & ~sbuf_wr_p0_of) ? {2'd0, sbuf_wr_p0_ch[1:0]} : + (sbuf_wr_p0_of) ? sbuf_wr_p0_ch_inc : + sbuf_wr_p0_ch; +assign sbuf_wr_p1_ch_w = (layer_st & is_x_stride_one_w) ? 2'b1 : + (layer_st & ~is_x_stride_one_w) ? 2'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p1_ch_ori : + (sbuf_wr_p1_of) ? sbuf_wr_p1_ch_inc : + sbuf_wr_p1_ch; +assign sbuf_wr_addr_en = layer_st | dma_rsp_vld; +assign sbuf_wr_addr_ori_en = layer_st | (dma_rsp_fifo_ready & is_sbuf_wr_last_line); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p0_base_w\" -q sbuf_wr_p0_base"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p1_base_w\" -q sbuf_wr_p1_base"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p0_offset_w\" -q sbuf_wr_p0_offset"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p1_offset_w\" -q sbuf_wr_p1_offset"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p0_ch_w\" -q sbuf_wr_p0_ch"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p1_ch_w\" -q sbuf_wr_p1_ch"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p0_base_w\" -q sbuf_wr_p0_base_ori"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p1_base_w\" -q sbuf_wr_p1_base_ori"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p0_offset_w\" -q sbuf_wr_p0_offset_ori"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p1_offset_w\" -q sbuf_wr_p1_offset_ori"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p0_ch_w\" -q sbuf_wr_p0_ch_ori"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p1_ch_w\" -q sbuf_wr_p1_ch_ori"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_base <= {4{1'b0}}; + end else begin + if ((sbuf_wr_addr_en) == 1'b1) begin + sbuf_wr_p0_base <= sbuf_wr_p0_base_w; + // VCS coverage off + end else if ((sbuf_wr_addr_en) == 1'b0) begin + end else begin + sbuf_wr_p0_base <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_base <= {4{1'b0}}; + end else begin + if ((sbuf_wr_addr_en) == 1'b1) begin + sbuf_wr_p1_base <= sbuf_wr_p1_base_w; + // VCS coverage off + end else if ((sbuf_wr_addr_en) == 1'b0) begin + end else begin + sbuf_wr_p1_base <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_offset <= {3{1'b0}}; + end else begin + if ((sbuf_wr_addr_en) == 1'b1) begin + sbuf_wr_p0_offset <= sbuf_wr_p0_offset_w; + // VCS coverage off + end else if ((sbuf_wr_addr_en) == 1'b0) begin + end else begin + sbuf_wr_p0_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_offset <= {3{1'b0}}; + end else begin + if ((sbuf_wr_addr_en) == 1'b1) begin + sbuf_wr_p1_offset <= sbuf_wr_p1_offset_w; + // VCS coverage off + end else if ((sbuf_wr_addr_en) == 1'b0) begin + end else begin + sbuf_wr_p1_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_ch <= {4{1'b0}}; + end else begin + if ((sbuf_wr_addr_en) == 1'b1) begin + sbuf_wr_p0_ch <= sbuf_wr_p0_ch_w; + // VCS coverage off + end else if ((sbuf_wr_addr_en) == 1'b0) begin + end else begin + sbuf_wr_p0_ch <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_ch <= {2{1'b0}}; + end else begin + if ((sbuf_wr_addr_en) == 1'b1) begin + sbuf_wr_p1_ch <= sbuf_wr_p1_ch_w; + // VCS coverage off + end else if ((sbuf_wr_addr_en) == 1'b0) begin + end else begin + sbuf_wr_p1_ch <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_base_ori <= {4{1'b0}}; + end else begin + if ((sbuf_wr_addr_ori_en) == 1'b1) begin + sbuf_wr_p0_base_ori <= sbuf_wr_p0_base_w; + // VCS coverage off + end else if ((sbuf_wr_addr_ori_en) == 1'b0) begin + end else begin + sbuf_wr_p0_base_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_base_ori <= {4{1'b0}}; + end else begin + if ((sbuf_wr_addr_ori_en) == 1'b1) begin + sbuf_wr_p1_base_ori <= sbuf_wr_p1_base_w; + // VCS coverage off + end else if ((sbuf_wr_addr_ori_en) == 1'b0) begin + end else begin + sbuf_wr_p1_base_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_offset_ori <= {3{1'b0}}; + end else begin + if ((sbuf_wr_addr_ori_en) == 1'b1) begin + sbuf_wr_p0_offset_ori <= sbuf_wr_p0_offset_w; + // VCS coverage off + end else if ((sbuf_wr_addr_ori_en) == 1'b0) begin + end else begin + sbuf_wr_p0_offset_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_offset_ori <= {3{1'b0}}; + end else begin + if ((sbuf_wr_addr_ori_en) == 1'b1) begin + sbuf_wr_p1_offset_ori <= sbuf_wr_p1_offset_w; + // VCS coverage off + end else if ((sbuf_wr_addr_ori_en) == 1'b0) begin + end else begin + sbuf_wr_p1_offset_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_ch_ori <= {4{1'b0}}; + end else begin + if ((sbuf_wr_addr_ori_en) == 1'b1) begin + sbuf_wr_p0_ch_ori <= sbuf_wr_p0_ch_w; + // VCS coverage off + end else if ((sbuf_wr_addr_ori_en) == 1'b0) begin + end else begin + sbuf_wr_p0_ch_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_ch_ori <= {2{1'b0}}; + end else begin + if ((sbuf_wr_addr_ori_en) == 1'b1) begin + sbuf_wr_p1_ch_ori <= sbuf_wr_p1_ch_w; + // VCS coverage off + end else if ((sbuf_wr_addr_ori_en) == 1'b0) begin + end else begin + sbuf_wr_p1_ch_ori <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// current write index //////////////// +assign {mon_sbuf_wr_p0_idx_lo, + sbuf_wr_p0_idx_lo} = sbuf_wr_p0_base + sbuf_wr_p0_offset; +assign {mon_sbuf_wr_p1_idx_lo, + sbuf_wr_p1_idx_lo} = sbuf_wr_p1_base + sbuf_wr_p1_offset; +assign sbuf_wr_p0_idx = {sbuf_wr_p0_idx_lo[0], sbuf_wr_line[0], sbuf_wr_p0_ch[1:0], sbuf_wr_line[1], sbuf_wr_p0_idx_lo[8 -5:1]}; +assign sbuf_wr_p1_idx = {sbuf_wr_p1_idx_lo[0], sbuf_wr_line[0], sbuf_wr_p1_ch[1:0], sbuf_wr_line[1], sbuf_wr_p1_idx_lo[8 -5:1]}; +assign sbuf_x_stride_inc_size = (~dma_rsp_fifo_ready | ~is_sbuf_wr_last_line) ? 2'b0 : + (sbuf_wr_p0_of) ? sbuf_wr_p0_ch_inc[3:2] : sbuf_wr_p0_ch[3:2]; +assign sbuf_cube_inc_size = sbuf_x_stride_inc_size[1] ? {conv_x_stride[2:0], 1'b0} : + sbuf_x_stride_inc_size[0] ? conv_x_stride : + 4'b0; +assign sbuf_wr_p0_en = dma_rsp_vld & dma_rsp_mask[0]; +assign sbuf_wr_p1_en = dma_rsp_vld & dma_rsp_mask[1]; +assign sbuf_cube_inc_en = dma_rsp_fifo_ready & is_sbuf_wr_last_line; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_wr_p0_en\" -q sbuf_wr_p0_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_wr_p1_en\" -q sbuf_wr_p1_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_wr_p0_en\" -d \"sbuf_wr_p0_idx\" -q sbuf_wr_p0_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_wr_p1_en\" -d \"sbuf_wr_p1_idx\" -q sbuf_wr_p1_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{256{1'b0}}\" -en \"sbuf_wr_p0_en\" -d \"dma_rsp_data_p0\" -q sbuf_wr_p0_data_d1"); +//: &eperl::flop("-nodeclare -rval \"{256{1'b0}}\" -en \"sbuf_wr_p1_en\" -d \"dma_rsp_data_p1\" -q sbuf_wr_p1_data_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_cube_inc_en\" -q sbuf_cube_inc_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_cube_inc_en\" -d \"sbuf_cube_inc_size\" -q sbuf_cube_inc_size_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_en_d1 <= 1'b0; + end else begin + sbuf_wr_p0_en_d1 <= sbuf_wr_p0_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_en_d1 <= 1'b0; + end else begin + sbuf_wr_p1_en_d1 <= sbuf_wr_p1_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_idx_d1 <= {8{1'b0}}; + end else begin + if ((sbuf_wr_p0_en) == 1'b1) begin + sbuf_wr_p0_idx_d1 <= sbuf_wr_p0_idx; + // VCS coverage off + end else if ((sbuf_wr_p0_en) == 1'b0) begin + end else begin + sbuf_wr_p0_idx_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_idx_d1 <= {8{1'b0}}; + end else begin + if ((sbuf_wr_p1_en) == 1'b1) begin + sbuf_wr_p1_idx_d1 <= sbuf_wr_p1_idx; + // VCS coverage off + end else if ((sbuf_wr_p1_en) == 1'b0) begin + end else begin + sbuf_wr_p1_idx_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p0_data_d1 <= {256{1'b0}}; + end else begin + if ((sbuf_wr_p0_en) == 1'b1) begin + sbuf_wr_p0_data_d1 <= dma_rsp_data_p0; + // VCS coverage off + end else if ((sbuf_wr_p0_en) == 1'b0) begin + end else begin + sbuf_wr_p0_data_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_wr_p1_data_d1 <= {256{1'b0}}; + end else begin + if ((sbuf_wr_p1_en) == 1'b1) begin + sbuf_wr_p1_data_d1 <= dma_rsp_data_p1; + // VCS coverage off + end else if ((sbuf_wr_p1_en) == 1'b0) begin + end else begin + sbuf_wr_p1_data_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_cube_inc_en_d1 <= 1'b0; + end else begin + sbuf_cube_inc_en_d1 <= sbuf_cube_inc_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_cube_inc_size_d1 <= {4{1'b0}}; + end else begin + if ((sbuf_cube_inc_en) == 1'b1) begin + sbuf_cube_inc_size_d1 <= sbuf_cube_inc_size; + // VCS coverage off + end else if ((sbuf_cube_inc_en) == 1'b0) begin + end else begin + sbuf_cube_inc_size_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Shared buffer write signals // +//////////////////////////////////////////////////////////////////////// +assign wg2sbuf_p0_wr_en = sbuf_wr_p0_en_d1; +assign wg2sbuf_p1_wr_en = sbuf_wr_p1_en_d1; +assign wg2sbuf_p0_wr_addr = sbuf_wr_p0_idx_d1; +assign wg2sbuf_p1_wr_addr = sbuf_wr_p1_idx_d1; +assign wg2sbuf_p0_wr_data = sbuf_wr_p0_data_d1; +assign wg2sbuf_p1_wr_data = sbuf_wr_p1_data_d1; +//////////////////////////////////////////////////////////////////////// +// WG read data from shared buffer // +//////////////////////////////////////////////////////////////////////// +assign sbuf_avl_cube_add = sbuf_cube_inc_en_d1 ? sbuf_cube_inc_size_d1 : 4'b0; +assign sbuf_avl_cube_sub = sbuf_rd_en & (rd_sub_cnt == 3'h7); +assign {mon_sbuf_avl_cube_w, + sbuf_avl_cube_w} = (layer_st) ? 5'b0 : + (sbuf_avl_cube + sbuf_avl_cube_add - sbuf_avl_cube_sub); +assign sbuf_blocking_w = (sbuf_avl_cube_w >= 4'h8) ? 1'b1 : 1'b0; +assign sbuf_rd_en = (|sbuf_avl_cube); +assign {mon_rd_sub_cnt_w, + rd_sub_cnt_w} = (layer_st) ? 4'b0 : + (rd_sub_cnt + 1'b1); +assign sbuf_avl_cube_en = sbuf_avl_cube_sub | sbuf_cube_inc_en_d1; +assign {mon_rd_cube_cnt_w, + rd_cube_cnt_w} = (layer_st) ? 5'b0 : + rd_cube_cnt + 1; +assign sbuf_rd_p0_idx = {rd_cube_cnt[0], 1'b0, rd_sub_cnt[0], rd_cube_cnt[8 -5:1], rd_sub_cnt[2:1]}; +assign sbuf_rd_p1_idx = {rd_cube_cnt[0], 1'b1, rd_sub_cnt[0], rd_cube_cnt[8 -5:1], rd_sub_cnt[2:1]}; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st | sbuf_avl_cube_en\" -d \"sbuf_avl_cube_w\" -q sbuf_avl_cube"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st | sbuf_avl_cube_en\" -d \"sbuf_blocking_w\" -q sbuf_blocking"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st | sbuf_avl_cube_sub\" -d \"rd_cube_cnt_w\" -q rd_cube_cnt"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st | sbuf_rd_en\" -d \"rd_sub_cnt_w\" -q rd_sub_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_rd_en\" -q sbuf_rd_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_rd_en\" -d \"sbuf_rd_p0_idx\" -q sbuf_rd_p0_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_rd_en\" -d \"sbuf_rd_p1_idx\" -q sbuf_rd_p1_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sbuf_rd_en\" -d \"rd_sub_cnt[1:0]\" -q sbuf_rd_sel_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_avl_cube <= {4{1'b0}}; + end else begin + if ((layer_st | sbuf_avl_cube_en) == 1'b1) begin + sbuf_avl_cube <= sbuf_avl_cube_w; + // VCS coverage off + end else if ((layer_st | sbuf_avl_cube_en) == 1'b0) begin + end else begin + sbuf_avl_cube <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_blocking <= 1'b0; + end else begin + if ((layer_st | sbuf_avl_cube_en) == 1'b1) begin + sbuf_blocking <= sbuf_blocking_w; + // VCS coverage off + end else if ((layer_st | sbuf_avl_cube_en) == 1'b0) begin + end else begin + sbuf_blocking <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_cube_cnt <= {4{1'b0}}; + end else begin + if ((layer_st | sbuf_avl_cube_sub) == 1'b1) begin + rd_cube_cnt <= rd_cube_cnt_w; + // VCS coverage off + end else if ((layer_st | sbuf_avl_cube_sub) == 1'b0) begin + end else begin + rd_cube_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_cnt <= {3{1'b0}}; + end else begin + if ((layer_st | sbuf_rd_en) == 1'b1) begin + rd_sub_cnt <= rd_sub_cnt_w; + // VCS coverage off + end else if ((layer_st | sbuf_rd_en) == 1'b0) begin + end else begin + rd_sub_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_rd_en_d1 <= 1'b0; + end else begin + sbuf_rd_en_d1 <= sbuf_rd_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_rd_p0_idx_d1 <= {8{1'b0}}; + end else begin + if ((sbuf_rd_en) == 1'b1) begin + sbuf_rd_p0_idx_d1 <= sbuf_rd_p0_idx; + // VCS coverage off + end else if ((sbuf_rd_en) == 1'b0) begin + end else begin + sbuf_rd_p0_idx_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_rd_p1_idx_d1 <= {8{1'b0}}; + end else begin + if ((sbuf_rd_en) == 1'b1) begin + sbuf_rd_p1_idx_d1 <= sbuf_rd_p1_idx; + // VCS coverage off + end else if ((sbuf_rd_en) == 1'b0) begin + end else begin + sbuf_rd_p1_idx_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sbuf_rd_sel_d1 <= {2{1'b0}}; + end else begin + if ((sbuf_rd_en) == 1'b1) begin + sbuf_rd_sel_d1 <= rd_sub_cnt[1:0]; + // VCS coverage off + end else if ((sbuf_rd_en) == 1'b0) begin + end else begin + sbuf_rd_sel_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Shared buffer read signals // +//////////////////////////////////////////////////////////////////////// +assign wg2sbuf_p0_rd_en = sbuf_rd_en_d1; +assign wg2sbuf_p1_rd_en = sbuf_rd_en_d1; +assign wg2sbuf_p0_rd_addr = sbuf_rd_p0_idx_d1; +assign wg2sbuf_p1_rd_addr = sbuf_rd_p1_idx_d1; +//////////////////////////////////////////////////////////////////////// +// pipeline to sync the sbuf read to output to convertor // +//////////////////////////////////////////////////////////////////////// +//: my $latency = 2; +//: my $i; +//: my $j; +//: if($latency == 0) { +//: print "assign rsp_vld = sbuf_rd_en_d1;\n"; +//: print "assign rsp_sel = sbuf_rd_sel_d1;\n"; +//: } else { +//: print "assign rsp_vld_d0 = sbuf_rd_en_d1;\n"; +//: print "assign rsp_sel_d0 = sbuf_rd_sel_d1;\n"; +//: for($i = 0; $i < $latency; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"rsp_vld_d${i}\" -q rsp_vld_d${j}"); +//: &eperl::flop("-wid 2 -rval \"{2{1'b0}}\" -en \"rsp_vld_d${i}\" -d \"rsp_sel_d${i}\" -q rsp_sel_d${j}"); +//: } +//: print "\n\n"; +//: print "assign rsp_vld = rsp_vld_d${i};\n"; +//: print "assign rsp_sel = rsp_sel_d${i};\n\n\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign rsp_vld_d0 = sbuf_rd_en_d1; +assign rsp_sel_d0 = sbuf_rd_sel_d1; +reg rsp_vld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_vld_d1 <= 1'b0; + end else begin + rsp_vld_d1 <= rsp_vld_d0; + end +end +reg [1:0] rsp_sel_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sel_d1 <= {2{1'b0}}; + end else begin + if ((rsp_vld_d0) == 1'b1) begin + rsp_sel_d1 <= rsp_sel_d0; + // VCS coverage off + end else if ((rsp_vld_d0) == 1'b0) begin + end else begin + rsp_sel_d1 <= 'bx; + // VCS coverage on + end + end +end +reg rsp_vld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_vld_d2 <= 1'b0; + end else begin + rsp_vld_d2 <= rsp_vld_d1; + end +end +reg [1:0] rsp_sel_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sel_d2 <= {2{1'b0}}; + end else begin + if ((rsp_vld_d1) == 1'b1) begin + rsp_sel_d2 <= rsp_sel_d1; + // VCS coverage off + end else if ((rsp_vld_d1) == 1'b0) begin + end else begin + rsp_sel_d2 <= 'bx; + // VCS coverage on + end + end +end + + +assign rsp_vld = rsp_vld_d2; +assign rsp_sel = rsp_sel_d2; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WG local cache // +//////////////////////////////////////////////////////////////////////// +assign rsp_data_l0c0_en = (rsp_vld & (rsp_sel == 2'h0)); +assign rsp_data_l0c1_en = (rsp_vld & (rsp_sel == 2'h1)); +assign rsp_data_l1c0_en = (rsp_vld & (rsp_sel == 2'h2)); +assign rsp_data_l1c1_en = (rsp_vld & (rsp_sel == 2'h3)); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l0c0_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l0c0"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l0c1_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l0c1"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l1c0_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l1c0"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l1c1_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l1c1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_vld\" -q rsp_dat_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_dat_vld_d1\" -q rsp_dat_vld_d2"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((rsp_data_l0c0_en) == 1'b1) begin + rsp_data_l0c0 <= {wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}; + // VCS coverage off + end else if ((rsp_data_l0c0_en) == 1'b0) begin + end else begin + rsp_data_l0c0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_data_l0c1_en) == 1'b1) begin + rsp_data_l0c1 <= {wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}; + // VCS coverage off + end else if ((rsp_data_l0c1_en) == 1'b0) begin + end else begin + rsp_data_l0c1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_data_l1c0_en) == 1'b1) begin + rsp_data_l1c0 <= {wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}; + // VCS coverage off + end else if ((rsp_data_l1c0_en) == 1'b0) begin + end else begin + rsp_data_l1c0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_data_l1c1_en) == 1'b1) begin + rsp_data_l1c1 <= {wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}; + // VCS coverage off + end else if ((rsp_data_l1c1_en) == 1'b0) begin + end else begin + rsp_data_l1c1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_dat_vld_d1 <= 1'b0; + end else begin + rsp_dat_vld_d1 <= rsp_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_dat_vld_d2 <= 1'b0; + end else begin + rsp_dat_vld_d2 <= rsp_dat_vld_d1; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WG response data counter // +//////////////////////////////////////////////////////////////////////// +//////////////// sub cube count //////////////// +assign {mon_rsp_sub_cube_cnt_inc, + rsp_sub_cube_cnt_inc} = rsp_sub_cube_cnt + 1'b1; +assign rsp_sub_cube_cnt_w = (layer_st | is_rsp_last_sub_cube) ? 3'b0 : + rsp_sub_cube_cnt_inc; +assign is_rsp_last_sub_cube = (rsp_sub_cube_cnt == 3'h7); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rsp_sub_cube_en\" -d \"rsp_sub_cube_cnt_w\" -q rsp_sub_cube_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sub_cube_cnt <= {3{1'b0}}; + end else begin + if ((rsp_sub_cube_en) == 1'b1) begin + rsp_sub_cube_cnt <= rsp_sub_cube_cnt_w; + // VCS coverage off + end else if ((rsp_sub_cube_en) == 1'b0) begin + end else begin + rsp_sub_cube_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// conv x stride count //////////////// +assign {mon_rsp_x_std_cnt_inc, + rsp_x_std_cnt_inc} = rsp_x_std_cnt + 1'b1; +assign rsp_x_std_cnt_w = (layer_st | is_rsp_last_x_std) ? 3'b0 : + rsp_x_std_cnt_inc; +assign is_rsp_last_x_std = (rsp_x_std_cnt == reg2dp_conv_x_stride); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rsp_x_std_en\" -d \"rsp_x_std_cnt_w\" -q rsp_x_std_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_x_std_cnt <= {3{1'b0}}; + end else begin + if ((rsp_x_std_en) == 1'b1) begin + rsp_x_std_cnt <= rsp_x_std_cnt_w; + // VCS coverage off + end else if ((rsp_x_std_en) == 1'b0) begin + end else begin + rsp_x_std_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// width_ext count //////////////// +assign {mon_rsp_width_cnt_inc, + rsp_width_cnt_inc} = rsp_width_cnt + 1'b1; +assign rsp_width_cnt_w = (layer_st | is_rsp_last_width) ? 11'b0 : + rsp_width_cnt_inc; +assign is_rsp_last_width = (rsp_width_cnt == width_ext_total); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"rsp_width_en\" -d \"rsp_width_cnt_w\" -q rsp_width_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_width_cnt <= {11{1'b0}}; + end else begin + if ((rsp_width_en) == 1'b1) begin + rsp_width_cnt <= rsp_width_cnt_w; + // VCS coverage off + end else if ((rsp_width_en) == 1'b0) begin + end else begin + rsp_width_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// conv y stride count //////////////// +assign {mon_rsp_y_std_cnt_inc, + rsp_y_std_cnt_inc} = rsp_y_std_cnt + 1'b1; +assign rsp_y_std_cnt_w = (layer_st | is_rsp_last_y_std) ? 3'b0 : + rsp_y_std_cnt_inc; +assign is_rsp_last_y_std = (rsp_y_std_cnt == reg2dp_conv_y_stride); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rsp_y_std_en\" -d \"rsp_y_std_cnt_w\" -q rsp_y_std_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_y_std_cnt <= {3{1'b0}}; + end else begin + if ((rsp_y_std_en) == 1'b1) begin + rsp_y_std_cnt <= rsp_y_std_cnt_w; + // VCS coverage off + end else if ((rsp_y_std_en) == 1'b0) begin + end else begin + rsp_y_std_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// surf count //////////////// +assign {mon_rsp_surf_cnt_inc, + rsp_surf_cnt_inc} = rsp_surf_cnt + 1'b1; +assign rsp_surf_cnt_w = (layer_st | is_rsp_last_surf) ? 4'b0 : + rsp_surf_cnt_inc; +assign is_rsp_last_surf = (rsp_surf_cnt == surf_cnt_total); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"rsp_surf_en\" -d \"rsp_surf_cnt_w\" -q rsp_surf_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_surf_cnt <= {9{1'b0}}; + end else begin + if ((rsp_surf_en) == 1'b1) begin + rsp_surf_cnt <= rsp_surf_cnt_w; + // VCS coverage off + end else if ((rsp_surf_en) == 1'b0) begin + end else begin + rsp_surf_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// height ext //////////////// +assign {mon_rsp_h_ext_cnt_inc, + rsp_h_ext_cnt_inc} = rsp_h_ext_cnt + 1'b1; +assign rsp_h_ext_cnt_w = layer_st ? 11'b0 : + rsp_h_ext_cnt_inc; +assign is_rsp_last_h_ext = (rsp_h_ext_cnt == height_ext_total); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"rsp_h_ext_en\" -d \"rsp_h_ext_cnt_w\" -q rsp_h_ext_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_h_ext_cnt <= {11{1'b0}}; + end else begin + if ((rsp_h_ext_en) == 1'b1) begin + rsp_h_ext_cnt <= rsp_h_ext_cnt_w; + // VCS coverage off + end else if ((rsp_h_ext_en) == 1'b0) begin + end else begin + rsp_h_ext_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// control signal //////////////// +assign rsp_en = rsp_dat_vld_d2; +assign rsp_sub_cube_en = layer_st | rsp_en; +assign rsp_x_std_en = layer_st | (rsp_en & is_rsp_last_sub_cube); +assign rsp_width_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std); +assign rsp_y_std_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width); +assign rsp_surf_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std); +assign rsp_h_ext_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std & is_rsp_last_surf); +assign is_slice_done = (is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std & is_rsp_last_surf); +assign is_last_rsp = (is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std & is_rsp_last_surf & is_rsp_last_h_ext); +//////////////////////////////////////////////////////////////////////// +// WG response CBUF address generator // +//////////////////////////////////////////////////////////////////////// +//////////////// base address //////////////// +assign {mon_rsp_addr_offset_w, + rsp_addr_offset_w} = layer_st ? 13'b0 : + rsp_addr_offset + data_entries; +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"is_first_running\" -d \"status2dma_wr_idx\" -q rsp_addr_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_h_ext_en\" -d \"rsp_addr_offset_w\" -q rsp_addr_offset"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_addr_base <= {12{1'b0}}; + end else begin + if ((is_first_running) == 1'b1) begin + rsp_addr_base <= status2dma_wr_idx; + // VCS coverage off + end else if ((is_first_running) == 1'b0) begin + end else begin + rsp_addr_base <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_addr_offset <= {12{1'b0}}; + end else begin + if ((rsp_h_ext_en) == 1'b1) begin + rsp_addr_offset <= rsp_addr_offset_w; + // VCS coverage off + end else if ((rsp_h_ext_en) == 1'b0) begin + end else begin + rsp_addr_offset <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// offset //////////////// +//aaa = rsp_sub_surf * data_width_ext +//bbb = rsp_sub_surf * data_width_ext * conv_x_stride; +//ccc = rsp_sub_surf_per_surf * data_width_ext; +assign rsp_ch_x_std_add = {w_ext_surf[12 -3:0], 2'b0}; +assign rsp_ch_y_std_add = {h_ext_surf[12 -3:0], 2'b0}; +assign rsp_ch_surf_add = {data_width_ext[12 -3:0], 2'b0}; +assign {mon_rsp_ch_offset_w, + rsp_ch_offset_w} = (layer_st) ? 13'b0 : + (~is_rsp_last_sub_cube) ? (rsp_ch_offset + data_width_ext) : + (~is_rsp_last_x_std) ? (rsp_ch_x_std_base + rsp_ch_x_std_add) : + (~is_rsp_last_width) ? (rsp_ch_w_base + 1'b1) : + (~is_rsp_last_y_std) ? (rsp_ch_y_std_base + rsp_ch_y_std_add) : + (~is_rsp_last_surf) ? (rsp_ch_surf_base + rsp_ch_surf_add) : + 13'b0; +assign rsp_ch_offset_en = (rsp_en & rsp_sub_cube_cnt[0]); +assign rsp_ch_x_std_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube; +assign rsp_ch_w_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube & is_rsp_last_x_std; +assign rsp_ch_y_std_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width; +assign rsp_ch_surf_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std; +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_offset_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_offset"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_x_std_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_x_std_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_w_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_w_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_y_std_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_y_std_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_surf_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_surf_base"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_ch_offset <= {12{1'b0}}; + end else begin + if ((rsp_ch_offset_en) == 1'b1) begin + rsp_ch_offset <= rsp_ch_offset_w; + // VCS coverage off + end else if ((rsp_ch_offset_en) == 1'b0) begin + end else begin + rsp_ch_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_ch_x_std_base <= {12{1'b0}}; + end else begin + if ((rsp_ch_x_std_base_en) == 1'b1) begin + rsp_ch_x_std_base <= rsp_ch_offset_w; + // VCS coverage off + end else if ((rsp_ch_x_std_base_en) == 1'b0) begin + end else begin + rsp_ch_x_std_base <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_ch_w_base <= {12{1'b0}}; + end else begin + if ((rsp_ch_w_base_en) == 1'b1) begin + rsp_ch_w_base <= rsp_ch_offset_w; + // VCS coverage off + end else if ((rsp_ch_w_base_en) == 1'b0) begin + end else begin + rsp_ch_w_base <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_ch_y_std_base <= {12{1'b0}}; + end else begin + if ((rsp_ch_y_std_base_en) == 1'b1) begin + rsp_ch_y_std_base <= rsp_ch_offset_w; + // VCS coverage off + end else if ((rsp_ch_y_std_base_en) == 1'b0) begin + end else begin + rsp_ch_y_std_base <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_ch_surf_base <= {12{1'b0}}; + end else begin + if ((rsp_ch_surf_base_en) == 1'b1) begin + rsp_ch_surf_base <= rsp_ch_offset_w; + // VCS coverage off + end else if ((rsp_ch_surf_base_en) == 1'b0) begin + end else begin + rsp_ch_surf_base <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// write address //////////////// +assign {mon_rsp_addr_inc, + rsp_addr_inc} = rsp_addr_base + rsp_addr_offset + rsp_ch_offset; +assign {mon_rsp_addr_wrap, +//rsp_addr_wrap} = rsp_addr_inc - {1'b0, data_bank, 8'b0}; + rsp_addr_wrap} = rsp_addr_inc - {data_bank, 9'b0}; +//assign is_rsp_addr_wrap = rsp_addr_inc[12 : 8 ] >= {1'b0, data_bank}; +assign is_rsp_addr_wrap = {1'b0,rsp_addr_inc[12 : 9 ]} >= data_bank; +assign rsp_addr = ~is_rsp_addr_wrap ? rsp_addr_inc[12 -1:0] : + rsp_addr_wrap; +assign rsp_hsel = rsp_sub_cube_cnt[0]; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_en\" -q rsp_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_en\" -d \"rsp_addr\" -q rsp_addr_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_en\" -d \"rsp_hsel\" -q rsp_hsel_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_en & is_slice_done\" -q rsp_slice_done_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_en\" -d \"is_last_rsp\" -q rsp_layer_done_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_en_d1 <= 1'b0; + end else begin + rsp_en_d1 <= rsp_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_addr_d1 <= {12{1'b0}}; + end else begin + if ((rsp_en) == 1'b1) begin + rsp_addr_d1 <= rsp_addr; + // VCS coverage off + end else if ((rsp_en) == 1'b0) begin + end else begin + rsp_addr_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_hsel_d1 <= 1'b0; + end else begin + if ((rsp_en) == 1'b1) begin + rsp_hsel_d1 <= rsp_hsel; + // VCS coverage off + end else if ((rsp_en) == 1'b0) begin + end else begin + rsp_hsel_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_slice_done_d1 <= 1'b0; + end else begin + rsp_slice_done_d1 <= rsp_en & is_slice_done; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_layer_done_d1 <= 1'b0; + end else begin + if ((rsp_en) == 1'b1) begin + rsp_layer_done_d1 <= is_last_rsp; + // VCS coverage off + end else if ((rsp_en) == 1'b0) begin + end else begin + rsp_layer_done_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WG response data output // +//////////////////////////////////////////////////////////////////////// +assign rsp_data_l0 = {rsp_data_l0c1, rsp_data_l0c0}; +assign rsp_data_l1 = {rsp_data_l1c1, rsp_data_l1c0}; +assign dat_cur = rsp_sub_cube_cnt[1] ? rsp_data_l1 : rsp_data_l0; +assign dat_cur_remapped = dat_cur; +assign rsp_data_d1_w = rsp_sub_cube_cnt[0] ? dat_cur_remapped[1023:512] : + dat_cur_remapped[511:0]; +//: &eperl::flop("-nodeclare -norst -en \"rsp_en\" -d \"rsp_data_d1_w\" -q rsp_data_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((rsp_en) == 1'b1) begin + rsp_data_d1 <= rsp_data_d1_w; + // VCS coverage off + end else if ((rsp_en) == 1'b0) begin + end else begin + rsp_data_d1 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WG to CDMA convertor // +//////////////////////////////////////////////////////////////////////// +assign wg2cvt_dat_wr_en = rsp_en_d1; +assign wg2cvt_dat_wr_addr = rsp_addr_d1; +assign wg2cvt_dat_wr_sel = rsp_hsel_d1; +assign wg2cvt_dat_wr_data = rsp_data_d1; +assign cbuf_wr_info_mask = 4'h3; +assign cbuf_wr_info_interleave = 1'b0; +assign cbuf_wr_info_ext64 = 1'b0; +assign cbuf_wr_info_ext128 = 1'b0; +assign cbuf_wr_info_mean = 1'b0; +assign cbuf_wr_info_uint = 1'b0; +assign cbuf_wr_info_sub_h = 3'b0; +assign wg2cvt_dat_wr_info_pd[3:0] = cbuf_wr_info_mask[3:0]; +assign wg2cvt_dat_wr_info_pd[4] = cbuf_wr_info_interleave ; +assign wg2cvt_dat_wr_info_pd[5] = cbuf_wr_info_ext64 ; +assign wg2cvt_dat_wr_info_pd[6] = cbuf_wr_info_ext128 ; +assign wg2cvt_dat_wr_info_pd[7] = cbuf_wr_info_mean ; +assign wg2cvt_dat_wr_info_pd[8] = cbuf_wr_info_uint ; +assign wg2cvt_dat_wr_info_pd[11:9] = cbuf_wr_info_sub_h[2:0]; +//////////////////////////////////////////////////////////////////////// +// WG response done signal // +//////////////////////////////////////////////////////////////////////// +assign is_rsp_done_w = layer_st ? 1'b0 : + (rsp_en_d1 & rsp_layer_done_d1) ? 1'b1 : + is_rsp_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"is_rsp_done_w\" -q is_rsp_done"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_rsp_done <= 1'b1; + end else begin + is_rsp_done <= is_rsp_done_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WG to status update // +//////////////////////////////////////////////////////////////////////// +assign wg2status_dat_updt = rsp_slice_done_d1; +assign wg2status_dat_entries = data_entries; +assign wg2status_dat_slices = 14'h4; +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_stall_inc <= 1'b0; + end else begin + wg_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_stall_clr <= 1'b0; + end else begin + wg_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_stall_cen <= 1'b0; + end else begin + wg_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_wg_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = wg_rd_stall_inc ^ dp2reg_wg_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wg_rd_stall_inc && !dp2reg_wg_rd_stall_dec)? stl_cnt_inc : (!wg_rd_stall_inc && dp2reg_wg_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (wg_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (wg_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_wg_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_inc <= 1'b0; + end else begin + wg_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_dec <= 1'b0; + end else begin + wg_rd_latency_dec <= dma_rsp_fifo_ready & ~dma_rsp_dummy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_clr <= 1'b0; + end else begin + wg_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_cen <= 1'b0; + end else begin + wg_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign ltc_1_inc = (outs_dp2reg_wg_rd_latency!=511) & wg_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_wg_rd_latency!=511) & wg_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (wg_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (wg_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_wg_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +assign ltc_2_dec = 1'b0; +assign ltc_2_inc = (~&dp2reg_wg_rd_latency) & (|outs_dp2reg_wg_rd_latency); +// ltc_2 adv logic +always @(*) begin + ltc_2_adv = ltc_2_inc ^ ltc_2_dec; +end +// ltc_2 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_2_cnt_ext[33:0] = {1'b0, 1'b0, ltc_2_cnt_cur}; + ltc_2_cnt_inc[33:0] = ltc_2_cnt_cur + 1'b1; // spyglass disable W164b + ltc_2_cnt_dec[33:0] = ltc_2_cnt_cur - 1'b1; // spyglass disable W164b + ltc_2_cnt_mod[33:0] = (ltc_2_inc && !ltc_2_dec)? ltc_2_cnt_inc : (!ltc_2_inc && ltc_2_dec)? ltc_2_cnt_dec : ltc_2_cnt_ext; + ltc_2_cnt_new[33:0] = (ltc_2_adv)? ltc_2_cnt_mod[33:0] : ltc_2_cnt_ext[33:0]; + ltc_2_cnt_nxt[33:0] = (wg_rd_latency_clr)? 34'd0 : ltc_2_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// ltc_2 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_2_cnt_cur[31:0] <= 0; + end else begin + if (wg_rd_latency_cen) begin + ltc_2_cnt_cur[31:0] <= ltc_2_cnt_nxt[31:0]; + end + end +end +// ltc_2 output logic +always @(*) begin + dp2reg_wg_rd_latency[31:0] = ltc_2_cnt_cur[31:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_wg__rsp_addr_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (rsp_en & is_rsp_addr_wrap); + endproperty +// Cover 0 : "(rsp_en & is_rsp_addr_wrap)" + FUNCPOINT_cdma_wg__rsp_addr_wrap__0_COV : cover property (cdma_wg__rsp_addr_wrap__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_wg__wg_conv_stride_EQ_0__1_0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_0 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_0__1_0_COV : cover property (cdma_wg__wg_conv_stride_EQ_0__1_0_cov); + property cdma_wg__wg_conv_stride_EQ_1__1_1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_1 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_1__1_1_COV : cover property (cdma_wg__wg_conv_stride_EQ_1__1_1_cov); + property cdma_wg__wg_conv_stride_EQ_2__1_2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_2 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_2__1_2_COV : cover property (cdma_wg__wg_conv_stride_EQ_2__1_2_cov); + property cdma_wg__wg_conv_stride_EQ_3__1_3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_3 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_3__1_3_COV : cover property (cdma_wg__wg_conv_stride_EQ_3__1_3_cov); + property cdma_wg__wg_conv_stride_EQ_4__1_4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_4 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_4__1_4_COV : cover property (cdma_wg__wg_conv_stride_EQ_4__1_4_cov); + property cdma_wg__wg_conv_stride_EQ_5__1_5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_5 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_5__1_5_COV : cover property (cdma_wg__wg_conv_stride_EQ_5__1_5_cov); + property cdma_wg__wg_conv_stride_EQ_6__1_6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_6 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_6__1_6_COV : cover property (cdma_wg__wg_conv_stride_EQ_6__1_6_cov); + property cdma_wg__wg_conv_stride_EQ_7__1_7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_7 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_7__1_7_COV : cover property (cdma_wg__wg_conv_stride_EQ_7__1_7_cov); + property cdma_wg__wg_conv_stride_EQ_8__1_8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_8 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_8__1_8_COV : cover property (cdma_wg__wg_conv_stride_EQ_8__1_8_cov); + property cdma_wg__wg_conv_stride_EQ_9__1_9_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_9 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_9__1_9_COV : cover property (cdma_wg__wg_conv_stride_EQ_9__1_9_cov); + property cdma_wg__wg_conv_stride_EQ_10__1_10_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_10 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_10__1_10_COV : cover property (cdma_wg__wg_conv_stride_EQ_10__1_10_cov); + property cdma_wg__wg_conv_stride_EQ_11__1_11_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_11 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_11__1_11_COV : cover property (cdma_wg__wg_conv_stride_EQ_11__1_11_cov); + property cdma_wg__wg_conv_stride_EQ_12__1_12_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_12 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_12__1_12_COV : cover property (cdma_wg__wg_conv_stride_EQ_12__1_12_cov); + property cdma_wg__wg_conv_stride_EQ_13__1_13_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_13 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_13__1_13_COV : cover property (cdma_wg__wg_conv_stride_EQ_13__1_13_cov); + property cdma_wg__wg_conv_stride_EQ_14__1_14_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_14 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_14__1_14_COV : cover property (cdma_wg__wg_conv_stride_EQ_14__1_14_cov); + property cdma_wg__wg_conv_stride_EQ_15__1_15_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_15 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_15__1_15_COV : cover property (cdma_wg__wg_conv_stride_EQ_15__1_15_cov); + property cdma_wg__wg_conv_stride_EQ_16__1_16_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_16 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_16__1_16_COV : cover property (cdma_wg__wg_conv_stride_EQ_16__1_16_cov); + property cdma_wg__wg_conv_stride_EQ_17__1_17_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_17 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_17__1_17_COV : cover property (cdma_wg__wg_conv_stride_EQ_17__1_17_cov); + property cdma_wg__wg_conv_stride_EQ_18__1_18_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_18 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_18__1_18_COV : cover property (cdma_wg__wg_conv_stride_EQ_18__1_18_cov); + property cdma_wg__wg_conv_stride_EQ_19__1_19_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_19 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_19__1_19_COV : cover property (cdma_wg__wg_conv_stride_EQ_19__1_19_cov); + property cdma_wg__wg_conv_stride_EQ_20__1_20_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_20 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_20__1_20_COV : cover property (cdma_wg__wg_conv_stride_EQ_20__1_20_cov); + property cdma_wg__wg_conv_stride_EQ_21__1_21_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_21 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_21__1_21_COV : cover property (cdma_wg__wg_conv_stride_EQ_21__1_21_cov); + property cdma_wg__wg_conv_stride_EQ_22__1_22_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_22 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_22__1_22_COV : cover property (cdma_wg__wg_conv_stride_EQ_22__1_22_cov); + property cdma_wg__wg_conv_stride_EQ_23__1_23_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_23 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_23__1_23_COV : cover property (cdma_wg__wg_conv_stride_EQ_23__1_23_cov); + property cdma_wg__wg_conv_stride_EQ_24__1_24_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_24 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_24__1_24_COV : cover property (cdma_wg__wg_conv_stride_EQ_24__1_24_cov); + property cdma_wg__wg_conv_stride_EQ_25__1_25_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_25 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_25__1_25_COV : cover property (cdma_wg__wg_conv_stride_EQ_25__1_25_cov); + property cdma_wg__wg_conv_stride_EQ_26__1_26_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_26 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_26__1_26_COV : cover property (cdma_wg__wg_conv_stride_EQ_26__1_26_cov); + property cdma_wg__wg_conv_stride_EQ_27__1_27_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_27 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_27__1_27_COV : cover property (cdma_wg__wg_conv_stride_EQ_27__1_27_cov); + property cdma_wg__wg_conv_stride_EQ_28__1_28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_28 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_28__1_28_COV : cover property (cdma_wg__wg_conv_stride_EQ_28__1_28_cov); + property cdma_wg__wg_conv_stride_EQ_29__1_29_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_29 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_29__1_29_COV : cover property (cdma_wg__wg_conv_stride_EQ_29__1_29_cov); + property cdma_wg__wg_conv_stride_EQ_30__1_30_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_30 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_30__1_30_COV : cover property (cdma_wg__wg_conv_stride_EQ_30__1_30_cov); + property cdma_wg__wg_conv_stride_EQ_31__1_31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_31 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_31__1_31_COV : cover property (cdma_wg__wg_conv_stride_EQ_31__1_31_cov); + property cdma_wg__wg_conv_stride_EQ_32__1_32_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_32 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_32__1_32_COV : cover property (cdma_wg__wg_conv_stride_EQ_32__1_32_cov); + property cdma_wg__wg_conv_stride_EQ_33__1_33_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_33 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_33__1_33_COV : cover property (cdma_wg__wg_conv_stride_EQ_33__1_33_cov); + property cdma_wg__wg_conv_stride_EQ_34__1_34_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_34 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_34__1_34_COV : cover property (cdma_wg__wg_conv_stride_EQ_34__1_34_cov); + property cdma_wg__wg_conv_stride_EQ_35__1_35_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_35 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_35__1_35_COV : cover property (cdma_wg__wg_conv_stride_EQ_35__1_35_cov); + property cdma_wg__wg_conv_stride_EQ_36__1_36_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_36 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_36__1_36_COV : cover property (cdma_wg__wg_conv_stride_EQ_36__1_36_cov); + property cdma_wg__wg_conv_stride_EQ_37__1_37_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_37 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_37__1_37_COV : cover property (cdma_wg__wg_conv_stride_EQ_37__1_37_cov); + property cdma_wg__wg_conv_stride_EQ_38__1_38_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_38 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_38__1_38_COV : cover property (cdma_wg__wg_conv_stride_EQ_38__1_38_cov); + property cdma_wg__wg_conv_stride_EQ_39__1_39_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_39 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_39__1_39_COV : cover property (cdma_wg__wg_conv_stride_EQ_39__1_39_cov); + property cdma_wg__wg_conv_stride_EQ_40__1_40_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_40 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_40__1_40_COV : cover property (cdma_wg__wg_conv_stride_EQ_40__1_40_cov); + property cdma_wg__wg_conv_stride_EQ_41__1_41_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_41 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_41__1_41_COV : cover property (cdma_wg__wg_conv_stride_EQ_41__1_41_cov); + property cdma_wg__wg_conv_stride_EQ_42__1_42_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_42 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_42__1_42_COV : cover property (cdma_wg__wg_conv_stride_EQ_42__1_42_cov); + property cdma_wg__wg_conv_stride_EQ_43__1_43_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_43 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_43__1_43_COV : cover property (cdma_wg__wg_conv_stride_EQ_43__1_43_cov); + property cdma_wg__wg_conv_stride_EQ_44__1_44_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_44 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_44__1_44_COV : cover property (cdma_wg__wg_conv_stride_EQ_44__1_44_cov); + property cdma_wg__wg_conv_stride_EQ_45__1_45_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_45 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_45__1_45_COV : cover property (cdma_wg__wg_conv_stride_EQ_45__1_45_cov); + property cdma_wg__wg_conv_stride_EQ_46__1_46_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_46 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_46__1_46_COV : cover property (cdma_wg__wg_conv_stride_EQ_46__1_46_cov); + property cdma_wg__wg_conv_stride_EQ_47__1_47_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_47 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_47__1_47_COV : cover property (cdma_wg__wg_conv_stride_EQ_47__1_47_cov); + property cdma_wg__wg_conv_stride_EQ_48__1_48_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_48 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_48__1_48_COV : cover property (cdma_wg__wg_conv_stride_EQ_48__1_48_cov); + property cdma_wg__wg_conv_stride_EQ_49__1_49_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_49 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_49__1_49_COV : cover property (cdma_wg__wg_conv_stride_EQ_49__1_49_cov); + property cdma_wg__wg_conv_stride_EQ_50__1_50_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_50 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_50__1_50_COV : cover property (cdma_wg__wg_conv_stride_EQ_50__1_50_cov); + property cdma_wg__wg_conv_stride_EQ_51__1_51_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_51 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_51__1_51_COV : cover property (cdma_wg__wg_conv_stride_EQ_51__1_51_cov); + property cdma_wg__wg_conv_stride_EQ_52__1_52_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_52 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_52__1_52_COV : cover property (cdma_wg__wg_conv_stride_EQ_52__1_52_cov); + property cdma_wg__wg_conv_stride_EQ_53__1_53_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_53 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_53__1_53_COV : cover property (cdma_wg__wg_conv_stride_EQ_53__1_53_cov); + property cdma_wg__wg_conv_stride_EQ_54__1_54_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_54 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_54__1_54_COV : cover property (cdma_wg__wg_conv_stride_EQ_54__1_54_cov); + property cdma_wg__wg_conv_stride_EQ_55__1_55_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_55 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_55__1_55_COV : cover property (cdma_wg__wg_conv_stride_EQ_55__1_55_cov); + property cdma_wg__wg_conv_stride_EQ_56__1_56_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_56 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_56__1_56_COV : cover property (cdma_wg__wg_conv_stride_EQ_56__1_56_cov); + property cdma_wg__wg_conv_stride_EQ_57__1_57_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_57 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_57__1_57_COV : cover property (cdma_wg__wg_conv_stride_EQ_57__1_57_cov); + property cdma_wg__wg_conv_stride_EQ_58__1_58_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_58 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_58__1_58_COV : cover property (cdma_wg__wg_conv_stride_EQ_58__1_58_cov); + property cdma_wg__wg_conv_stride_EQ_59__1_59_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_59 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_59__1_59_COV : cover property (cdma_wg__wg_conv_stride_EQ_59__1_59_cov); + property cdma_wg__wg_conv_stride_EQ_60__1_60_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_60 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_60__1_60_COV : cover property (cdma_wg__wg_conv_stride_EQ_60__1_60_cov); + property cdma_wg__wg_conv_stride_EQ_61__1_61_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_61 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_61__1_61_COV : cover property (cdma_wg__wg_conv_stride_EQ_61__1_61_cov); + property cdma_wg__wg_conv_stride_EQ_62__1_62_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_62 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_62__1_62_COV : cover property (cdma_wg__wg_conv_stride_EQ_62__1_62_cov); + property cdma_wg__wg_conv_stride_EQ_63__1_63_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_63 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_63__1_63_COV : cover property (cdma_wg__wg_conv_stride_EQ_63__1_63_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_wg__wg_reuse__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cur_state == WG_STATE_IDLE) & (nxt_state == WG_STATE_DONE)); + endproperty +// Cover 2 : "((cur_state == WG_STATE_IDLE) & (nxt_state == WG_STATE_DONE))" + FUNCPOINT_cdma_wg__wg_reuse__2_COV : cover property (cdma_wg__wg_reuse__2_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_rsp_done | is_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wg_entry_onfly_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_surf_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_y_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_w_set_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_sub_w_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_sub_h_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_sub_h_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_y_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_surf_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_adv))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_adv))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_adv))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_valid_d1 & req_ready_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_71x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_valid_d1 & req_ready_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_valid_d1 & req_ready_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rsp_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | dma_rsp_fifo_ready))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_85x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_100x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_cube_inc_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_104x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_avl_cube_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_avl_cube_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_106x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_avl_cube_sub))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_107x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_108x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_109x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_vld_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_114x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_115x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_sub_cube_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_x_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_117x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_width_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_118x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_y_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_119x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_surf_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_120x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_121x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_122x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_124x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_125x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_x_std_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_126x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_w_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_127x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_y_std_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_128x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_surf_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_131x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_132x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_133x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! fifo is not empty when done!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Req is not done when rsp is done!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (is_running & is_rsp_done & ~is_req_done)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_onfly is non zero when idle") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (fetch_done & |(wg_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! None feature input when wg!") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (layer_st & is_wg & ~is_feature)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data_entries_w is overflow!") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_data_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! width is not divisible by conv_x_stride") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (layer_st & ((reg2dp_pad_left + reg2dp_datain_width + reg2dp_pad_right + 1) % conv_x_stride_w != 0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! height is not divisible by conv_y_stride") zzz_assert_never_35x (nvdla_core_clk, `ASSERT_RESET, (layer_st & ((reg2dp_pad_top + reg2dp_datain_height + reg2dp_pad_bottom + 1) % conv_y_stride_w != 0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! channel is not divisible by 16/32") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (layer_st & ((is_int8 & (reg2dp_datain_channel[4:0] != 5'h1f)) | (~is_int8 & (reg2dp_datain_channel[3:0] != 4'hf))))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! width_ext is not divisible by 4") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (reg2dp_datain_width_ext[1:0] != 2'b11))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! height_ext is not divisible by 4") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (reg2dp_datain_height_ext[1:0] != 2'b11))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! width and width_ext not match") zzz_assert_never_39x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (((reg2dp_pad_left + reg2dp_datain_width + reg2dp_pad_right + 1) / conv_x_stride_w) != (reg2dp_datain_width_ext + 1)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! height and height_ext not match") zzz_assert_never_40x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (((reg2dp_pad_top + reg2dp_datain_height + reg2dp_pad_bottom + 1) / conv_y_stride_w) != (reg2dp_datain_height_ext + 1)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! reg2dp_entries is out of range in winograd mode!") zzz_assert_never_41x (nvdla_core_clk, `ASSERT_RESET, (layer_st & is_wg & (|reg2dp_entries[11:10]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! w_ext_surf_w is overflow!") zzz_assert_never_46x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & (|mon_w_ext_surf_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! h_ext_surf_w is overflow!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & (|mon_h_ext_surf_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! w_ext_surf_w is out of range when normal!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & w_ext_surf_w[12 -2])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! h_ext_surf_w is out of range when normal!") zzz_assert_never_51x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & h_ext_surf_w[12 -2])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wg_entry_onfly_w is overflow!") zzz_assert_never_53x (nvdla_core_clk, `ASSERT_RESET, (wg_entry_onfly_en & mon_wg_entry_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wg_entry_onfly is not zero when idle!") zzz_assert_never_54x (nvdla_core_clk, `ASSERT_RESET, (~is_running & (|wg_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_one_hot #(0,3,0,"Error! width section select error!") zzz_assert_one_hot_59x (nvdla_core_clk, `ASSERT_RESET, ({is_w_set_lp, is_w_set_di, is_w_set_rp})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cbuf_needed is overflow!") zzz_assert_never_63x (nvdla_core_clk, `ASSERT_RESET, (mon_req_cubf_needed)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Receive input data when not busy") zzz_assert_never_74x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_76x (nvdla_core_clk, `ASSERT_RESET, (~dma_rsp_fifo_req & dma_rd_rsp_vld)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_77x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > dma_rsp_size)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_78x (nvdla_core_clk, `ASSERT_RESET, (mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_79x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > 8'h8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! p0 overflow conflict!") zzz_assert_never_93x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & ~is_x_stride_one & sbuf_wr_p0_of_0 & sbuf_wr_p1_of_0 & (~is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! p1 overflow conflict!") zzz_assert_never_94x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & ~is_x_stride_one & sbuf_wr_p0_of_1 & sbuf_wr_p1_of_1 & (~is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf_wr_p0_ch_inc is overflow!") zzz_assert_never_95x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & mon_sbuf_wr_p0_ch_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf_wr_p0_ch_inc is out of range!") zzz_assert_never_96x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & (sbuf_wr_p0_ch_inc[3:2] > 2'h2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf x_stride increase size out of range!") zzz_assert_never_102x (nvdla_core_clk, `ASSERT_RESET, (sbuf_cube_inc_en & sbuf_x_stride_inc_size[1] & (|reg2dp_conv_x_stride))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf cube increase size out of range!") zzz_assert_never_103x (nvdla_core_clk, `ASSERT_RESET, (sbuf_cube_inc_en & (sbuf_cube_inc_size > 4'h8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rd_sub_cnt is not zero when idle!") zzz_assert_never_111x (nvdla_core_clk, `ASSERT_RESET, (~is_running & (|rd_sub_cnt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf_avl_cube_w is overflow!") zzz_assert_never_112x (nvdla_core_clk, `ASSERT_RESET, (sbuf_avl_cube_en & mon_sbuf_avl_cube_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_addr_offset is overflow!") zzz_assert_never_123x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_addr_offset_w & rsp_h_ext_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_offset_w is overflow!") zzz_assert_never_129x (nvdla_core_clk, `ASSERT_RESET, (rsp_ch_offset_en & mon_rsp_ch_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_offset_w is out of range!") zzz_assert_never_130x (nvdla_core_clk, `ASSERT_RESET, (rsp_ch_offset_en & (rsp_ch_offset_w > 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_addr_inc is overflow!") zzz_assert_never_134x (nvdla_core_clk, `ASSERT_RESET, (rsp_en & mon_rsp_addr_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_135x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && wg_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_wg +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_rd_req_pd (mc_int_rd_req_valid,mc_int_rd_req_ready) <= dma_rd_req_pd[78:0] (mc_dma_rd_req_vld,mc_dma_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_WG_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_req_pd + ,mc_dma_rd_req_vld + ,mc_int_rd_req_ready + ,mc_dma_rd_req_rdy + ,mc_int_rd_req_pd + ,mc_int_rd_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] dma_rd_req_pd; +input mc_dma_rd_req_vld; +input mc_int_rd_req_ready; +output mc_dma_rd_req_rdy; +output [78:0] mc_int_rd_req_pd; +output mc_int_rd_req_valid; +reg mc_dma_rd_req_rdy; +reg [78:0] mc_int_rd_req_pd; +reg mc_int_rd_req_valid; +reg [78:0] p1_pipe_data; +reg [78:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [78:0] p1_skid_data; +reg [78:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_dma_rd_req_vld + or p1_pipe_rand_ready + or dma_rd_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = dma_rd_req_pd[78:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : dma_rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_dma_rd_req_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_dma_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mc_int_rd_req_ready + or p1_pipe_data + ) begin + mc_int_rd_req_valid = p1_pipe_valid; + p1_pipe_ready = mc_int_rd_req_ready; + mc_int_rd_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_136x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_rd_req_valid^mc_int_rd_req_ready^mc_dma_rd_req_vld^mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_137x (nvdla_core_clk, `ASSERT_RESET, (mc_dma_rd_req_vld && !mc_dma_rd_req_rdy), (mc_dma_rd_req_vld), (mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_WG_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_rd_req_pd (cv_int_rd_req_valid,cv_int_rd_req_ready) <= dma_rd_req_pd[78:0] (cv_dma_rd_req_vld,cv_dma_rd_req_rdy) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os mc_dma_rd_rsp_pd (mc_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= mc_int_rd_rsp_pd[513:0] (mc_int_rd_rsp_valid,mc_int_rd_rsp_ready) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_WG_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_rsp_rdy + ,mc_int_rd_rsp_pd + ,mc_int_rd_rsp_valid + ,mc_dma_rd_rsp_pd + ,mc_dma_rd_rsp_vld + ,mc_int_rd_rsp_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dma_rd_rsp_rdy; +input [513:0] mc_int_rd_rsp_pd; +input mc_int_rd_rsp_valid; +output [513:0] mc_dma_rd_rsp_pd; +output mc_dma_rd_rsp_vld; +output mc_int_rd_rsp_ready; +reg [513:0] mc_dma_rd_rsp_pd; +reg mc_dma_rd_rsp_vld; +reg mc_int_rd_rsp_ready; +reg [513:0] p3_pipe_data; +reg [513:0] p3_pipe_rand_data; +reg p3_pipe_rand_ready; +reg p3_pipe_rand_valid; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg [513:0] p3_pipe_skid_data; +reg p3_pipe_skid_ready; +reg p3_pipe_skid_valid; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [513:0] p3_skid_data; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) randomizer +`ifndef SYNTHESIS +reg p3_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p3_pipe_rand_active + or + `endif + mc_int_rd_rsp_valid + or p3_pipe_rand_ready + or mc_int_rd_rsp_pd + ) begin + `ifdef SYNTHESIS + p3_pipe_rand_valid = mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = p3_pipe_rand_ready; + p3_pipe_rand_data = mc_int_rd_rsp_pd[513:0]; + `else +// VCS coverage off + p3_pipe_rand_valid = (p3_pipe_rand_active)? 1'b0 : mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = (p3_pipe_rand_active)? 1'b0 : p3_pipe_rand_ready; + p3_pipe_rand_data = (p3_pipe_rand_active)? 'bx : mc_int_rd_rsp_pd[513:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p3_pipe_stall_cycles; +integer p3_pipe_stall_probability; +integer p3_pipe_stall_cycles_min; +integer p3_pipe_stall_cycles_max; +initial begin + p3_pipe_stall_cycles = 0; + p3_pipe_stall_probability = 0; + p3_pipe_stall_cycles_min = 1; + p3_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability" ) ) p3_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min" ) ) p3_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max" ) ) p3_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p3_pipe_rand_enable; +reg p3_pipe_rand_poised; +always @( + p3_pipe_stall_cycles + or p3_pipe_stall_probability + or mc_int_rd_rsp_valid + ) begin + p3_pipe_rand_active = p3_pipe_stall_cycles != 0; + p3_pipe_rand_enable = p3_pipe_stall_probability != 0; + p3_pipe_rand_poised = p3_pipe_rand_enable && !p3_pipe_rand_active && mc_int_rd_rsp_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_stall_cycles <= 1'b0; + end else begin + if (p3_pipe_rand_poised) begin + if (p3_pipe_stall_probability >= prand_inst0(1, 100)) begin + p3_pipe_stall_cycles <= prand_inst1(p3_pipe_stall_cycles_min, p3_pipe_stall_cycles_max); + end + end else if (p3_pipe_rand_active) begin + p3_pipe_stall_cycles <= p3_pipe_stall_cycles - 1; + end else begin + p3_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_pipe_rand_valid)? p3_pipe_rand_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_pipe_rand_ready = p3_pipe_ready_bc; +end +//## pipe (3) skid buffer +always @( + p3_pipe_valid + or p3_skid_ready_flop + or p3_pipe_skid_ready + or p3_skid_valid + ) begin + p3_skid_catch = p3_pipe_valid && p3_skid_ready_flop && !p3_pipe_skid_ready; + p3_skid_ready = (p3_skid_valid)? p3_pipe_skid_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + p3_pipe_ready <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_pipe_skid_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + p3_pipe_ready <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or p3_pipe_valid + or p3_skid_valid + or p3_pipe_data + or p3_skid_data + ) begin + p3_pipe_skid_valid = (p3_skid_ready_flop)? p3_pipe_valid : p3_skid_valid; +// VCS sop_coverage_off start + p3_pipe_skid_data = (p3_skid_ready_flop)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) output +always @( + p3_pipe_skid_valid + or dma_rd_rsp_rdy + or p3_pipe_skid_data + ) begin + mc_dma_rd_rsp_vld = p3_pipe_skid_valid; + p3_pipe_skid_ready = dma_rd_rsp_rdy; + mc_dma_rd_rsp_pd = p3_pipe_skid_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_140x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_dma_rd_rsp_vld^dma_rd_rsp_rdy^mc_int_rd_rsp_valid^mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_141x (nvdla_core_clk, `ASSERT_RESET, (mc_int_rd_rsp_valid && !mc_int_rd_rsp_ready), (mc_int_rd_rsp_valid), (mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_WG_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cv_dma_rd_rsp_pd (cv_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= cv_int_rd_rsp_pd[513:0] (cv_int_rd_rsp_valid,cv_int_rd_rsp_ready) +// ************************************************************************************************************** diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v.vcp new file mode 100644 index 0000000..fa73e94 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v.vcp @@ -0,0 +1,2899 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_wg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_wg ( + nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,mcif2wg_dat_rd_rsp_pd //|< i + ,mcif2wg_dat_rd_rsp_valid //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_conv_x_stride //|< i + ,reg2dp_conv_y_stride //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_data_reuse //|< i + ,reg2dp_datain_addr_high_0 //|< i + ,reg2dp_datain_addr_low_0 //|< i + ,reg2dp_datain_channel //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_datain_height //|< i + ,reg2dp_datain_height_ext //|< i + ,reg2dp_datain_ram_type //|< i + ,reg2dp_datain_width //|< i + ,reg2dp_datain_width_ext //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_entries //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_line_stride //|< i + ,reg2dp_op_en //|< i + ,reg2dp_pad_bottom //|< i * + ,reg2dp_pad_left //|< i + ,reg2dp_pad_right //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_skip_data_rls //|< i + ,reg2dp_surf_stride //|< i + ,sc2cdma_dat_pending_req //|< i + ,status2dma_free_entries //|< i + ,status2dma_fsm_switch //|< i + ,status2dma_valid_slices //|< i * + ,status2dma_wr_idx //|< i + ,wg2sbuf_p0_rd_data //|< i + ,wg2sbuf_p1_rd_data //|< i + ,wg_dat2mcif_rd_req_ready //|< i + ,dp2reg_wg_rd_latency //|> o + ,dp2reg_wg_rd_stall //|> o + ,mcif2wg_dat_rd_rsp_ready //|> o + ,slcg_wg_gate_dc //|> o + ,slcg_wg_gate_img //|> o + ,wg2cvt_dat_wr_addr //|> o + ,wg2cvt_dat_wr_data //|> o + ,wg2cvt_dat_wr_en //|> o + ,wg2cvt_dat_wr_sel //|> o + ,wg2cvt_dat_wr_info_pd //|> o + ,wg2sbuf_p0_rd_addr //|> o + ,wg2sbuf_p0_rd_en //|> o + ,wg2sbuf_p0_wr_addr //|> o + ,wg2sbuf_p0_wr_data //|> o + ,wg2sbuf_p0_wr_en //|> o + ,wg2sbuf_p1_rd_addr //|> o + ,wg2sbuf_p1_rd_en //|> o + ,wg2sbuf_p1_wr_addr //|> o + ,wg2sbuf_p1_wr_data //|> o + ,wg2sbuf_p1_wr_en //|> o + ,wg2status_dat_entries //|> o + ,wg2status_dat_slices //|> o + ,wg2status_dat_updt //|> o + ,wg2status_state //|> o + ,wg_dat2mcif_rd_req_pd //|> o + ,wg_dat2mcif_rd_req_valid //|> o + ); +// +// NV_NVDLA_CDMA_wg_ports.v +// +input nvdla_core_clk; /* wg_dat2mcif_rd_req, wg_dat2cvif_rd_req, mcif2wg_dat_rd_rsp, cvif2wg_dat_rd_rsp, wg2cvt_dat_wr, wg2cvt_dat_wr_info, switch_status2dma, state_wg2status, dat_up_wg2status, bc_status2dma, wg2sbuf_p0_wr, wg2sbuf_p1_wr, wg2sbuf_p0_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p0_rd_nvdla_ram_data_DATA_WIDTH_256, wg2sbuf_p1_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p1_rd_nvdla_ram_data_DATA_WIDTH_256, sc2cdma_dat_pending */ +input nvdla_core_rstn; /* wg_dat2mcif_rd_req, wg_dat2cvif_rd_req, mcif2wg_dat_rd_rsp, cvif2wg_dat_rd_rsp, wg2cvt_dat_wr, wg2cvt_dat_wr_info, switch_status2dma, state_wg2status, dat_up_wg2status, bc_status2dma, wg2sbuf_p0_wr, wg2sbuf_p1_wr, wg2sbuf_p0_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p0_rd_nvdla_ram_data_DATA_WIDTH_256, wg2sbuf_p1_rd_nvdla_ram_addr_ADDR_WIDTH_8_BE_1, wg2sbuf_p1_rd_nvdla_ram_data_DATA_WIDTH_256, sc2cdma_dat_pending */ +input [31:0] pwrbus_ram_pd; +output wg_dat2mcif_rd_req_valid; /* data valid */ +input wg_dat2mcif_rd_req_ready; /* data return handshake */ +output [78:0] wg_dat2mcif_rd_req_pd; +input mcif2wg_dat_rd_rsp_valid; /* data valid */ +output mcif2wg_dat_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2wg_dat_rd_rsp_pd; +output wg2cvt_dat_wr_en; /* data valid */ +output [11:0] wg2cvt_dat_wr_addr; +output wg2cvt_dat_wr_sel; +output [511:0] wg2cvt_dat_wr_data; +output [11:0] wg2cvt_dat_wr_info_pd; +input status2dma_fsm_switch; +output [1:0] wg2status_state; +output wg2status_dat_updt; /* data valid */ +output [14:0] wg2status_dat_entries; +output [13:0] wg2status_dat_slices; +input [13:0] status2dma_valid_slices; +input [14:0] status2dma_free_entries; +input [11:0] status2dma_wr_idx; +output wg2sbuf_p0_wr_en; /* data valid */ +output [7:0] wg2sbuf_p0_wr_addr; +output [255:0] wg2sbuf_p0_wr_data; +output wg2sbuf_p1_wr_en; /* data valid */ +output [7:0] wg2sbuf_p1_wr_addr; +output [255:0] wg2sbuf_p1_wr_data; +output wg2sbuf_p0_rd_en; /* data valid */ +output [7:0] wg2sbuf_p0_rd_addr; +input [255:0] wg2sbuf_p0_rd_data; +output wg2sbuf_p1_rd_en; /* data valid */ +output [7:0] wg2sbuf_p1_rd_addr; +input [255:0] wg2sbuf_p1_rd_data; +input sc2cdma_dat_pending_req; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [0:0] reg2dp_datain_format; +input [12:0] reg2dp_datain_width; +input [12:0] reg2dp_datain_height; +input [12:0] reg2dp_datain_width_ext; +input [12:0] reg2dp_datain_height_ext; +input [12:0] reg2dp_datain_channel; +input [0:0] reg2dp_datain_ram_type; +input [31:0] reg2dp_datain_addr_high_0; +input [26:0] reg2dp_datain_addr_low_0; +input [26:0] reg2dp_line_stride; +input [26:0] reg2dp_surf_stride; +input [13:0] reg2dp_entries; +input [2:0] reg2dp_conv_x_stride; +input [2:0] reg2dp_conv_y_stride; +input [4:0] reg2dp_pad_left; +input [5:0] reg2dp_pad_right; +input [4:0] reg2dp_pad_top; +input [5:0] reg2dp_pad_bottom; +input [15:0] reg2dp_pad_value; +input [4:0] reg2dp_data_bank; +input [0:0] reg2dp_dma_en; +output slcg_wg_gate_dc; +output slcg_wg_gate_img; +output [31:0] dp2reg_wg_rd_stall; +output [31:0] dp2reg_wg_rd_latency; +reg [26:0] c_offset_d1; +reg [3:0] conv_x_stride; +reg [10:0] conv_xy_stride; +reg [3:0] conv_y_stride; +reg [1:0] cur_state; +reg [4:0] data_bank; +reg [14:0] data_entries; +reg [13:0] data_height; +reg [9:0] data_surf; +reg [11:0] data_width_ext; +reg [4:0] delay_cnt; +reg [3:0] dma_rsp_size; +reg [3:0] dma_rsp_size_cnt; +reg [31:0] dp2reg_wg_rd_latency; +reg [31:0] dp2reg_wg_rd_stall; +reg [14:0] h_coord; +reg [14:0] h_coord_sub_h; +reg [14:0] h_coord_surf; +reg [10:0] h_ext_surf; +reg [10:0] height_ext_total; +reg is_cbuf_ready; +reg is_req_done; +reg is_rsp_done; +reg is_running_d1; +reg is_x_stride_one; +reg [4:0] last_data_bank; +reg [3:0] last_lp; +reg [3:0] last_rp; +reg last_skip_data_rls; +reg last_wg; +reg layer_st_d1; +reg [4:0] lp_end; +reg ltc_1_adv; +reg [8:0] ltc_1_cnt_cur; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg ltc_2_adv; +reg [31:0] ltc_2_cnt_cur; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg no_lp; +reg [1:0] nxt_state; +reg [8:0] outs_dp2reg_wg_rd_latency; +reg pending_req; +reg pending_req_d1; +reg [3:0] rd_cube_cnt; +reg [2:0] rd_sub_cnt; +reg [58:0] req_addr_d2; +reg req_dummy_d1; +reg req_dummy_d2; +reg [10:0] req_h_ext_cnt; +reg [3:0] req_size_d1; +reg [3:0] req_size_d2; +reg [2:0] req_size_out_d1; +reg [2:0] req_size_out_d2; +reg [1:0] req_sub_h_cnt; +reg [12:0] req_sub_w_cnt; +reg [8:0] req_surf_cnt; +reg req_valid_d1; +reg req_valid_d2; +reg [1:0] req_w_set_cnt; +reg [2:0] req_y_std_cnt; +reg [5:0] rp_end; +reg [11:0] rsp_addr_base; +reg [11:0] rsp_addr_d1; +reg [11:0] rsp_addr_offset; +reg [11:0] rsp_ch_offset; +reg [11:0] rsp_ch_surf_base; +reg [11:0] rsp_ch_w_base; +reg [11:0] rsp_ch_x_std_base; +reg [11:0] rsp_ch_y_std_base; +reg rsp_dat_vld_d1; +reg rsp_dat_vld_d2; +reg [511:0] rsp_data_d1; +reg [511:0] rsp_data_l0c0; +reg [511:0] rsp_data_l0c1; +reg [511:0] rsp_data_l1c0; +reg [511:0] rsp_data_l1c1; +reg rsp_en_d1; +reg [10:0] rsp_h_ext_cnt; +reg rsp_hsel_d1; +reg rsp_layer_done_d1; +reg rsp_slice_done_d1; +reg [2:0] rsp_sub_cube_cnt; +reg [8:0] rsp_surf_cnt; +reg [10:0] rsp_width_cnt; +reg [2:0] rsp_x_std_cnt; +reg [2:0] rsp_y_std_cnt; +reg [3:0] sbuf_avl_cube; +reg sbuf_blocking; +reg sbuf_cube_inc_en_d1; +reg [3:0] sbuf_cube_inc_size_d1; +reg sbuf_rd_en_d1; +reg [7:0] sbuf_rd_p0_idx_d1; +reg [7:0] sbuf_rd_p1_idx_d1; +reg [1:0] sbuf_rd_sel_d1; +reg [1:0] sbuf_wr_line; +reg [3:0] sbuf_wr_p0_base; +reg [3:0] sbuf_wr_p0_base_ori; +reg [3:0] sbuf_wr_p0_ch; +reg [3:0] sbuf_wr_p0_ch_ori; +reg [255:0] sbuf_wr_p0_data_d1; +reg sbuf_wr_p0_en_d1; +reg [7:0] sbuf_wr_p0_idx_d1; +reg [2:0] sbuf_wr_p0_offset; +reg [2:0] sbuf_wr_p0_offset_ori; +reg [3:0] sbuf_wr_p1_base; +reg [3:0] sbuf_wr_p1_base_ori; +reg [1:0] sbuf_wr_p1_ch; +reg [1:0] sbuf_wr_p1_ch_ori; +reg [255:0] sbuf_wr_p1_data_d1; +reg sbuf_wr_p1_en_d1; +reg [7:0] sbuf_wr_p1_idx_d1; +reg [2:0] sbuf_wr_p1_offset; +reg [2:0] sbuf_wr_p1_offset_ori; +reg [1:0] slcg_wg_gate_d1; +reg [1:0] slcg_wg_gate_d2; +reg [1:0] slcg_wg_gate_d3; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [8:0] surf_cnt_total; +reg [10:0] w_ext_surf; +reg [1:0] wg2status_state; +reg [14:0] wg_entry_onfly; +reg wg_rd_latency_cen; +reg wg_rd_latency_clr; +reg wg_rd_latency_dec; +reg wg_rd_latency_inc; +reg wg_rd_stall_cen; +reg wg_rd_stall_clr; +reg wg_rd_stall_inc; +reg [10:0] width_ext_total; +reg [1:0] width_set_total; +reg [12:0] x_offset_d1; +reg [26:0] y_offset_d1; +wire [26:0] c_offset; +wire cbuf_wr_info_ext128; +wire cbuf_wr_info_ext64; +wire cbuf_wr_info_interleave; +wire [3:0] cbuf_wr_info_mask; +wire cbuf_wr_info_mean; +wire [2:0] cbuf_wr_info_sub_h; +wire cbuf_wr_info_uint; +wire [3:0] conv_x_stride_w; +wire [10:0] conv_xy_stride_w; +wire [3:0] conv_y_stride_w; +wire [1023:0] dat_cur; +wire [1023:0] dat_cur_remapped; +wire [14:0] data_entries_add; +wire [14:0] data_entries_w; +wire [14:0] data_height_st_w; +wire [13:0] data_height_w; +wire [9:0] data_surf_w; +wire [11:0] data_width_ext_w; +wire [4:0] delay_cnt_end; +wire [4:0] delay_cnt_w; +wire [511:0] dma_pad_data; +wire [63:0] dma_rd_req_addr; +wire [78:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [15:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire dma_rd_rsp_blocking; +wire [511:0] dma_rd_rsp_data; +wire [1:0] dma_rd_rsp_mask; +wire [513:0] dma_rd_rsp_pd; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [4:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire [511:0] dma_rsp_data; +wire [255:0] dma_rsp_data_p0; +wire [255:0] dma_rsp_data_p1; +wire dma_rsp_dummy; +wire [4:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire [1:0] dma_rsp_mask; +wire [3:0] dma_rsp_size_cnt_inc; +wire [3:0] dma_rsp_size_cnt_w; +wire dma_rsp_vld; +wire dp2reg_wg_rd_stall_dec; +wire fetch_done; +wire [14:0] h_coord_w; +wire [10:0] h_ext_surf_w; +wire height_dummy; +wire is_cbuf_ready_w; +wire is_done; +wire is_feature; +wire is_first_running; +wire is_idle; +wire is_int8; +wire is_last_req; +wire is_last_rsp; +wire is_pending; +wire is_req_done_w; +wire is_req_last_di; +wire is_req_last_h_ext; +wire is_req_last_lp; +wire is_req_last_rp; +wire is_req_last_sub_h; +wire is_req_last_sub_w; +wire is_req_last_surf; +wire is_req_last_w_set; +wire is_req_last_width; +wire is_req_last_y_std; +wire is_rsp_addr_wrap; +wire is_rsp_done_w; +wire is_rsp_last_h_ext; +wire is_rsp_last_sub_cube; +wire is_rsp_last_surf; +wire is_rsp_last_width; +wire is_rsp_last_x_std; +wire is_rsp_last_y_std; +wire is_running; +wire is_sbuf_wr_last_line; +wire is_slice_done; +wire is_w_set_di; +wire is_w_set_lp; +wire is_w_set_rp; +wire is_wg; +wire is_x_stride_one_w; +wire [3:0] last_lp_w; +wire [3:0] last_rp_w; +wire layer_st; +wire [4:0] lp_end_w; +wire ltc_1_dec; +wire ltc_1_inc; +wire ltc_2_dec; +wire ltc_2_inc; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [513:0] mc_dma_rd_rsp_pd; +wire mc_dma_rd_rsp_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire [513:0] mc_int_rd_rsp_pd; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire mc_rd_req_rdyi; +wire [513:0] mcif2wg_dat_rd_rsp_pd_d0; +wire mcif2wg_dat_rd_rsp_ready_d0; +wire mcif2wg_dat_rd_rsp_valid_d0; +wire mode_match; +wire [8:0] mon_c_offset; +wire [4:0] mon_conv_xy_stride_w; +wire mon_data_entries_w; +wire mon_delay_cnt_w; +wire mon_dma_rsp_size_cnt_inc; +wire mon_h_coord_w; +wire [9:0] mon_h_ext_surf_w; +wire mon_lp_end_w; +wire mon_rd_cube_cnt_w; +wire mon_rd_sub_cnt_w; +wire mon_req_addr_w; +wire mon_req_cubf_needed; +wire mon_req_h_ext_cnt_inc; +wire mon_req_size_out; +wire mon_req_sub_h_cnt_w; +wire mon_req_sub_w_cnt_inc; +wire mon_req_surf_cnt_inc; +wire mon_req_w_set_cnt_inc; +wire mon_req_y_std_cnt_inc; +wire mon_rp_end_w; +wire mon_rsp_addr_inc; +wire mon_rsp_addr_offset_w; +wire [1:0] mon_rsp_addr_wrap; +wire mon_rsp_ch_offset_w; +wire mon_rsp_h_ext_cnt_inc; +wire mon_rsp_sub_cube_cnt_inc; +wire mon_rsp_surf_cnt_inc; +wire mon_rsp_width_cnt_inc; +wire mon_rsp_x_std_cnt_inc; +wire mon_rsp_y_std_cnt_inc; +wire mon_sbuf_avl_cube_w; +wire mon_sbuf_wr_line_w; +wire mon_sbuf_wr_p0_base_w; +wire mon_sbuf_wr_p0_ch_inc; +wire mon_sbuf_wr_p0_idx_lo; +wire mon_sbuf_wr_p1_base_w; +wire mon_sbuf_wr_p1_ch_inc; +wire mon_sbuf_wr_p1_idx_lo; +wire [10:0] mon_w_ext_surf_w; +wire mon_wg_entry_onfly_w; +wire [12:0] mon_y_offset; +wire need_pending; +wire no_lp_w; +wire pending_req_end; +wire [3:0] rd_cube_cnt_w; +wire rd_req_rdyi; +wire [2:0] rd_sub_cnt_w; +wire [58:0] req_addr_base; +wire [58:0] req_addr_w; +wire req_adv; +wire [14:0] req_cbuf_needed; +wire [10:0] req_h_ext_cnt_inc; +wire [10:0] req_h_ext_cnt_w; +wire req_h_ext_en; +wire req_ready; +wire req_ready_d1; +wire req_ready_d2; +wire [3:0] req_size; +wire [2:0] req_size_out; +wire [1:0] req_sub_h_cnt_w; +wire req_sub_h_en; +wire [12:0] req_sub_w_cnt_inc; +wire [12:0] req_sub_w_cnt_w; +wire [3:0] req_sub_w_cur; +wire req_sub_w_en; +wire [8:0] req_surf_cnt_inc; +wire [8:0] req_surf_cnt_w; +wire req_surf_en; +wire req_valid; +wire req_valid_d1_w; +wire req_valid_d2_w; +wire [1:0] req_w_set_cnt_inc; +wire [1:0] req_w_set_cnt_w; +wire req_w_set_en; +wire [2:0] req_y_std_cnt_inc; +wire [2:0] req_y_std_cnt_w; +wire req_y_std_en; +wire [5:0] rp_end_w; +wire [11:0] rsp_addr; +wire [12:0] rsp_addr_inc; +wire [11:0] rsp_addr_offset_w; +wire [11:0] rsp_addr_wrap; +wire rsp_ch_offset_en; +wire [11:0] rsp_ch_offset_w; +wire [11:0] rsp_ch_surf_add; +wire rsp_ch_surf_base_en; +wire rsp_ch_w_base_en; +wire [11:0] rsp_ch_x_std_add; +wire rsp_ch_x_std_base_en; +wire [11:0] rsp_ch_y_std_add; +wire rsp_ch_y_std_base_en; +wire [511:0] rsp_data_d1_w; +wire [1023:0] rsp_data_l0; +wire rsp_data_l0c0_en; +wire rsp_data_l0c1_en; +wire [1023:0] rsp_data_l1; +wire rsp_data_l1c0_en; +wire rsp_data_l1c1_en; +wire rsp_en; +wire [10:0] rsp_h_ext_cnt_inc; +wire [10:0] rsp_h_ext_cnt_w; +wire rsp_h_ext_en; +wire rsp_hsel; +wire [1:0] rsp_sel; +wire [1:0] rsp_sel_d0; +wire [2:0] rsp_sub_cube_cnt_inc; +wire [2:0] rsp_sub_cube_cnt_w; +wire rsp_sub_cube_en; +wire [8:0] rsp_surf_cnt_inc; +wire [8:0] rsp_surf_cnt_w; +wire rsp_surf_en; +wire rsp_vld; +wire rsp_vld_d0; +wire [10:0] rsp_width_cnt_inc; +wire [10:0] rsp_width_cnt_w; +wire rsp_width_en; +wire [2:0] rsp_x_std_cnt_inc; +wire [2:0] rsp_x_std_cnt_w; +wire rsp_x_std_en; +wire [2:0] rsp_y_std_cnt_inc; +wire [2:0] rsp_y_std_cnt_w; +wire rsp_y_std_en; +wire [3:0] sbuf_avl_cube_add; +wire sbuf_avl_cube_en; +wire sbuf_avl_cube_sub; +wire [3:0] sbuf_avl_cube_w; +wire sbuf_blocking_w; +wire sbuf_cube_inc_en; +wire [3:0] sbuf_cube_inc_size; +wire sbuf_rd_en; +wire [7:0] sbuf_rd_p0_idx; +wire [7:0] sbuf_rd_p1_idx; +wire [1:0] sbuf_wr_add; +wire sbuf_wr_addr_en; +wire sbuf_wr_addr_ori_en; +wire [1:0] sbuf_wr_line_w; +wire [3:0] sbuf_wr_p0_base_w; +wire [3:0] sbuf_wr_p0_ch_inc; +wire [3:0] sbuf_wr_p0_ch_w; +wire sbuf_wr_p0_en; +wire [7:0] sbuf_wr_p0_idx; +wire [3:0] sbuf_wr_p0_idx_lo; +wire sbuf_wr_p0_of; +wire sbuf_wr_p0_of_0; +wire sbuf_wr_p0_of_1; +wire [3:0] sbuf_wr_p0_offset_inc; +wire [2:0] sbuf_wr_p0_offset_w; +wire [3:0] sbuf_wr_p1_base_w; +wire [1:0] sbuf_wr_p1_ch_inc; +wire [1:0] sbuf_wr_p1_ch_w; +wire sbuf_wr_p1_en; +wire [7:0] sbuf_wr_p1_idx; +wire [3:0] sbuf_wr_p1_idx_lo; +wire sbuf_wr_p1_of; +wire sbuf_wr_p1_of_0; +wire sbuf_wr_p1_of_1; +wire [3:0] sbuf_wr_p1_offset_inc; +wire [2:0] sbuf_wr_p1_offset_w; +wire [1:0] sbuf_x_stride_inc_size; +wire slcg_wg_en_w; +wire [1:0] slcg_wg_gate_w; +wire [8:0] surf_cnt_total_w; +wire [10:0] w_ext_surf_w; +wire [1:0] wg2status_state_w; +wire wg_en; +wire [14:0] wg_entry_onfly_add; +wire wg_entry_onfly_en; +wire [14:0] wg_entry_onfly_sub; +wire [14:0] wg_entry_onfly_w; +wire width_dummy; +wire [1:0] width_set_total_w; +wire [12:0] x_offset; +wire [26:0] y_offset; +//////////////////////////////////////////////////////////////////////// +// CDMA winograd convolution data fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +//## fsm (1) defines +localparam WG_STATE_IDLE = 2'b00; +localparam WG_STATE_PEND = 2'b01; +localparam WG_STATE_BUSY = 2'b10; +localparam WG_STATE_DONE = 2'b11; +//## fsm (1) com block +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + WG_STATE_IDLE: begin + if ((wg_en & need_pending)) begin + nxt_state = WG_STATE_PEND; + end + else if ((wg_en & reg2dp_data_reuse & last_skip_data_rls & mode_match)) begin + nxt_state = WG_STATE_DONE; + end + else if (wg_en) begin + nxt_state = WG_STATE_BUSY; + end + end + WG_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = WG_STATE_BUSY; + end + end + WG_STATE_BUSY: begin + if (fetch_done) begin + nxt_state = WG_STATE_DONE; + end + end + WG_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = WG_STATE_IDLE; + end + end + endcase + end +end +//## fsm (1) seq block +//: &eperl::flop("-nodeclare -rval \"WG_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign fetch_done = is_running & is_req_done & is_rsp_done & (delay_cnt == delay_cnt_end); +assign delay_cnt_end = (3 + 3 + 3 ) ; +assign {mon_delay_cnt_w, + delay_cnt_w} = ~is_running ? 6'b0 : + is_rsp_done ? delay_cnt + 1'b1 : + {1'b0, delay_cnt}; +assign need_pending = (last_data_bank != reg2dp_data_bank); +assign mode_match = wg_en & last_wg; +assign is_feature = (reg2dp_datain_format == 1'h0 ); +assign is_wg = (reg2dp_conv_mode == 1'h1 ); +assign wg_en = reg2dp_op_en & is_wg & is_feature; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"is_rsp_done | is_done\" -d \"delay_cnt_w\" -q delay_cnt"); +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = wg_en & is_idle; +assign is_idle = (cur_state == WG_STATE_IDLE); +assign is_pending = (cur_state == WG_STATE_PEND); +assign is_running = (cur_state == WG_STATE_BUSY); +assign is_done = (cur_state == WG_STATE_DONE); +assign is_first_running = ~is_running_d1 & is_running; +assign wg2status_state_w = (nxt_state == WG_STATE_PEND) ? 1 : + (nxt_state == WG_STATE_BUSY) ? 2 : + (nxt_state == WG_STATE_DONE) ? 3 : + 0 ; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"layer_st\" -q layer_st_d1"); +//: &eperl::flop("-nodeclare -rval \"0\" -d \"wg2status_state_w\" -q wg2status_state"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_running\" -q is_running_d1"); +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +assign pending_req_end = pending_req_d1 & ~pending_req; +//================ Non-SLCG clock domain ================// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"wg_en\" -q last_wg"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{5{1'b1}}\" -en \"reg2dp_op_en & is_idle\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"reg2dp_op_en & is_idle\" -d \"wg_en & reg2dp_skip_data_rls\" -q last_skip_data_rls"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"sc2cdma_dat_pending_req\" -q pending_req"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"pending_req\" -q pending_req_d1"); +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_wg_en_w = wg_en & (is_running | is_pending | is_done); +assign slcg_wg_gate_w = {2{~slcg_wg_en_w}}; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_wg_gate_w\" -q slcg_wg_gate_d1"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_wg_gate_d1\" -q slcg_wg_gate_d2"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{2{1'b1}}\" -d \"slcg_wg_gate_d2\" -q slcg_wg_gate_d3"); +assign slcg_wg_gate_dc = slcg_wg_gate_d3[0]; +assign slcg_wg_gate_img = slcg_wg_gate_d3[1]; +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +assign is_int8 = 1'b1; +assign surf_cnt_total_w = {1'b0, reg2dp_datain_channel[12:5]}; +assign data_surf_w = {1'b0, reg2dp_datain_channel[12:5]} + 1'b1; +assign is_x_stride_one_w = ~(|reg2dp_conv_x_stride); +assign data_height_st_w = 14'b0 - reg2dp_pad_top; +assign data_height_w = reg2dp_datain_height + 1'b1; +assign data_width_ext_w = reg2dp_datain_width_ext[12:2] + 1'b1; +assign {mon_conv_xy_stride_w, + conv_xy_stride_w} = conv_x_stride_w * data_width_ext_w; +assign {mon_w_ext_surf_w, + w_ext_surf_w} = data_width_ext_w * data_surf; +assign {mon_h_ext_surf_w, + h_ext_surf_w} = conv_xy_stride * data_surf; +assign conv_x_stride_w = reg2dp_conv_x_stride + 1'b1; +assign conv_y_stride_w = reg2dp_conv_y_stride + 1'b1; +assign {mon_data_entries_w, + data_entries_w} = {reg2dp_entries[12:0], 2'b0} + 3'h4; +assign width_set_total_w[1:0] = (|reg2dp_pad_left) + (|reg2dp_pad_right); +assign no_lp_w = ~(|reg2dp_pad_left); +assign {mon_lp_end_w, + lp_end_w} = ~(|reg2dp_pad_left[2:0]) ? (reg2dp_pad_left - 4'h8) : + {reg2dp_pad_left[4:3], 3'b0}; +assign last_lp_w = ~(|reg2dp_pad_left[2:0]) ? 4'h8 : {1'b0, reg2dp_pad_left[2:0]}; +assign {mon_rp_end_w, + rp_end_w} = ~(|reg2dp_pad_right[2:0]) ? (reg2dp_pad_right - 4'h8) : + {reg2dp_pad_right[5:3], 3'b0}; +assign last_rp_w = ~(|reg2dp_pad_right[2:0]) ? 4'h8 : {1'b0, reg2dp_pad_right[2:0]}; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"is_x_stride_one_w\" -q is_x_stride_one"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_height_w\" -q data_height"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"layer_st\" -d \"surf_cnt_total_w\" -q surf_cnt_total"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st\" -d \"data_width_ext_w\" -q data_width_ext"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st\" -d \"data_surf_w\" -q data_surf"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_x_stride_w\" -q conv_x_stride"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_y_stride_w\" -q conv_y_stride"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"conv_xy_stride_w\" -q conv_xy_stride"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"layer_st\" -d \"data_entries_w\" -q data_entries"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"reg2dp_data_bank + 1'b1\" -q data_bank"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"layer_st\" -d \"width_set_total_w\" -q width_set_total"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"layer_st\" -d \"no_lp_w\" -q no_lp"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"lp_end_w\" -q lp_end"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"last_lp_w\" -q last_lp"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"rp_end_w\" -q rp_end"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"last_rp_w\" -q last_rp"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"reg2dp_datain_width_ext[12:2]\" -q width_ext_total"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"reg2dp_datain_height_ext[12:2]\" -q height_ext_total"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st_d1\" -d \"w_ext_surf_w\" -q w_ext_surf"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st_d1\" -d \"h_ext_surf_w\" -q h_ext_surf"); +//////////////////////////////////////////////////////////////////////// +// entries on-the-fly // +//////////////////////////////////////////////////////////////////////// +//how many entries onfly +//current onfly entries + valid entries can be write in Cbuf - entries per slice +assign wg_entry_onfly_add = (~is_req_done & ~is_cbuf_ready & is_cbuf_ready_w) ? data_entries : 15'b0; +assign wg_entry_onfly_sub = wg2status_dat_updt ? wg2status_dat_entries : 15'b0; +assign {mon_wg_entry_onfly_w, + wg_entry_onfly_w} = wg_entry_onfly + wg_entry_onfly_add - wg_entry_onfly_sub; +assign wg_entry_onfly_en = wg2status_dat_updt | (~is_req_done & ~is_cbuf_ready & is_cbuf_ready_w); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"wg_entry_onfly_en\" -d \"wg_entry_onfly_w\" -q wg_entry_onfly"); +//////////////////////////////////////////////////////////////////////// +// prepare for address generation // +//////////////////////////////////////////////////////////////////////// +//////////////// extended height count //////////////// +assign {mon_req_h_ext_cnt_inc, + req_h_ext_cnt_inc} = req_h_ext_cnt + 1'b1; +assign req_h_ext_cnt_w = layer_st ? 11'b0 : + req_h_ext_cnt_inc; +assign is_req_last_h_ext = (req_h_ext_cnt == height_ext_total); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"req_h_ext_en\" -d \"req_h_ext_cnt_w\" -q req_h_ext_cnt"); +//////////////// surface count //////////////// +assign {mon_req_surf_cnt_inc, + req_surf_cnt_inc} = req_surf_cnt + 1'b1; +assign req_surf_cnt_w = (layer_st | is_req_last_surf) ? 9'b0 : + req_surf_cnt_inc; +assign is_req_last_surf = (req_surf_cnt == surf_cnt_total); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"req_surf_en\" -d \"req_surf_cnt_w\" -q req_surf_cnt"); +//////////////// conv y stride count //////////////// +assign {mon_req_y_std_cnt_inc, + req_y_std_cnt_inc} = req_y_std_cnt + 1'b1; +assign req_y_std_cnt_w = (layer_st | is_req_last_y_std) ? 3'b0 : + req_y_std_cnt_inc; +assign is_req_last_y_std = (req_y_std_cnt == reg2dp_conv_y_stride); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"req_y_std_en\" -d \"req_y_std_cnt_w\" -q req_y_std_cnt"); +//////////////// width set count //////////////// +assign {mon_req_w_set_cnt_inc, + req_w_set_cnt_inc} = req_w_set_cnt + 1'b1; +assign req_w_set_cnt_w = (layer_st | is_req_last_w_set) ? 2'b0 : + req_w_set_cnt_inc; +assign is_req_last_w_set = (req_w_set_cnt == width_set_total); +assign is_w_set_rp = (req_w_set_cnt == 2'h2) | (no_lp & (req_w_set_cnt == 2'h1)); +assign is_w_set_lp = ~no_lp & (req_w_set_cnt == 2'h0); +assign is_w_set_di = no_lp ? (req_w_set_cnt == 2'h0) : (req_w_set_cnt == 2'h1); +assign width_dummy = ~is_w_set_di; +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_w_set_en\" -d \"req_w_set_cnt_w\" -q req_w_set_cnt"); +//////////////// sub width count //////////////// +assign {mon_req_sub_w_cnt_inc, + req_sub_w_cnt_inc} = req_sub_w_cnt + 4'h8; +assign req_sub_w_cnt_w = (layer_st | is_req_last_sub_w) ? 13'b0 : + req_sub_w_cnt_inc; +assign req_sub_w_cur = is_req_last_lp ? last_lp : + is_req_last_rp ? last_rp : + is_req_last_di ? (reg2dp_datain_width[2:0] + 1'b1) : + 4'h8; +assign is_req_last_lp = (is_w_set_lp & (~(|req_sub_w_cnt[12:5]) & (req_sub_w_cnt[4:0] == lp_end))); +assign is_req_last_rp = (is_w_set_rp & (~(|req_sub_w_cnt[12:6]) & (req_sub_w_cnt[5:0] == rp_end))); +assign is_req_last_di = (is_w_set_di & (req_sub_w_cnt == {reg2dp_datain_width[12:3], 3'b0})); +assign is_req_last_sub_w = is_req_last_lp | is_req_last_di | is_req_last_rp; +assign is_req_last_width = is_req_last_sub_w & is_req_last_w_set; +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"req_sub_w_en\" -d \"req_sub_w_cnt_w\" -q req_sub_w_cnt"); +//////////////// sub h count //////////////// +assign {mon_req_sub_h_cnt_w, + req_sub_h_cnt_w} = (layer_st | is_req_last_sub_h) ? 3'b0 : + (req_sub_h_cnt + 1'b1); +assign is_req_last_sub_h = (req_sub_h_cnt == 2'h3); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"req_sub_h_en\" -d \"req_sub_h_cnt_w\" -q req_sub_h_cnt"); +//////////////// loop control logic //////////////// +assign is_req_done_w = layer_st ? 1'b0 : + is_last_req ? 1'b1 : + is_req_done; +assign req_valid = is_running & ~is_req_done & is_cbuf_ready; +assign data_entries_add = (is_req_last_h_ext & is_cbuf_ready) ? 15'b0 : data_entries; +assign {mon_req_cubf_needed, + req_cbuf_needed} = data_entries_add + wg_entry_onfly; +assign is_cbuf_ready_w = (~is_running | req_h_ext_en) ? 1'b0 : + (~is_cbuf_ready) ? (req_cbuf_needed <= status2dma_free_entries) : + is_cbuf_ready; +assign req_ready = ~req_valid_d1 | req_ready_d1; +assign req_adv = req_valid & req_ready; +assign req_sub_h_en = layer_st | req_adv; +assign req_sub_w_en = layer_st | (req_adv & is_req_last_sub_h); +assign req_w_set_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w); +assign req_y_std_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set); +assign req_surf_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set & is_req_last_y_std); +assign req_h_ext_en = layer_st | (req_adv & is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set & is_req_last_y_std & is_req_last_surf); +assign is_last_req = (is_req_last_sub_h & is_req_last_sub_w & is_req_last_w_set & is_req_last_y_std & is_req_last_surf & is_req_last_h_ext); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"req_h_ext_en\" -d \"is_req_done_w\" -q is_req_done"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_cbuf_ready_w\" -q is_cbuf_ready"); +//////////////// height coordinate count //////////////// +assign {mon_h_coord_w, + h_coord_w} = (layer_st) ? {1'b0, data_height_st_w} : + (~is_req_last_sub_h) ? (h_coord + conv_y_stride) : + (~is_req_last_width & is_req_last_sub_h) ? {1'b0, h_coord_sub_h} : + (~is_req_last_y_std & is_req_last_width & is_req_last_sub_h) ? (h_coord_sub_h + 1'h1) : + (~is_req_last_surf & is_req_last_y_std & is_req_last_width & is_req_last_sub_h) ? {1'b0, h_coord_surf} : + (h_coord_surf + {conv_y_stride, 2'b0}); +assign height_dummy = (h_coord[13 +1]) | (h_coord[13:0] >= data_height); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"req_sub_h_en\" -d \"h_coord_w\" -q h_coord"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"req_y_std_en\" -d \"h_coord_w\" -q h_coord_sub_h"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"req_surf_en\" -d \"h_coord_w\" -q h_coord_surf"); +//////////////// package signals //////////////// +assign x_offset = req_sub_w_cnt[12:0]; +assign {mon_y_offset, + y_offset} = h_coord[12:0] * reg2dp_line_stride; +assign {mon_c_offset, + c_offset} = req_surf_cnt * reg2dp_surf_stride; +assign req_size = req_sub_w_cur; +assign {mon_req_size_out, + req_size_out} = req_sub_w_cur - 1'b1; +assign req_ready_d1 = ~req_valid_d2 | req_ready_d2; +assign req_valid_d1_w = ~is_running ? 1'b0 : + req_valid ? 1'b1 : + req_ready_d1 ? 1'b0 : + req_valid_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_d1_w\" -q req_valid_d1"); +//: &eperl::flop("-nodeclare -norst -en \"req_adv\" -d \"x_offset\" -q x_offset_d1"); +//: &eperl::flop("-nodeclare -norst -en \"req_adv\" -d \"y_offset\" -q y_offset_d1"); +//: &eperl::flop("-nodeclare -norst -en \"req_adv\" -d \"c_offset\" -q c_offset_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"req_adv\" -d \"req_size\" -q req_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"req_adv\" -d \"req_size_out\" -q req_size_out_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_adv\" -d \"width_dummy | height_dummy\" -q req_dummy_d1"); +//////////////// package signals d2 //////////////// +assign req_addr_base = {reg2dp_datain_addr_high_0, reg2dp_datain_addr_low_0}; +assign {mon_req_addr_w, + req_addr_w} = req_addr_base + x_offset_d1 + y_offset_d1 + c_offset_d1; +assign req_valid_d2_w = ~is_running ? 1'b0 : + req_valid_d1 ? 1'b1 : + req_ready_d2 ? 1'b0 : + req_valid_d2; +assign req_ready_d2 = dma_req_fifo_ready & (dma_rd_req_rdy | (req_valid_d2 & req_dummy_d2)); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"req_valid_d2_w\" -q req_valid_d2"); +//: &eperl::flop("-nodeclare -norst -en \"req_valid_d1 & req_ready_d1 & ~req_dummy_d1\" -d \"req_addr_w\" -q req_addr_d2"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"req_valid_d1 & req_ready_d1\" -d \"req_size_d1\" -q req_size_d2"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"req_valid_d1 & req_ready_d1\" -d \"req_size_out_d1\" -q req_size_out_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"req_valid_d1 & req_ready_d1\" -d \"req_dummy_d1\" -q req_dummy_d2"); +`ifdef NVDLA_PRINT_CDMA +always @ (posedge nvdla_core_clk) +begin + if(req_valid_d2 & req_ready_d2) + begin + $display("[CDMA WG REQ] Dummy = %d, Addr = 0x%010h, size = %0d, time = %0d", req_dummy_d2, req_addr_d2, req_size_d2, $stime); + end +end +`endif +//////////////////////////////////////////////////////////////////////// +// CDMA DC read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_datain_ram_type) + ,.mcif_rd_req_pd (wg_dat2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (wg_dat2mcif_rd_req_valid) + ,.mcif_rd_req_ready (wg_dat2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2wg_dat_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2wg_dat_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2wg_dat_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////// +assign dma_rd_req_pd[63:0] = dma_rd_req_addr[63:0]; +assign dma_rd_req_pd[78:64] = dma_rd_req_size[14:0]; +//assign dma_rd_req_vld = dma_req_fifo_ready & req_valid_d1 & cbuf_entry_ready; +assign dma_rd_req_vld = dma_req_fifo_ready & req_valid_d2 & ~req_dummy_d2; +assign dma_rd_req_addr = {req_addr_d2[58:0], 5'b0}; +assign dma_rd_req_size = {{13{1'b0}}, req_size_out_d2}; +assign dma_rd_req_type = reg2dp_datain_ram_type; +assign dma_rd_rsp_rdy = ~dma_rd_rsp_blocking; +NV_NVDLA_CDMA_WG_fifo u_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[4:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w + ,.rd_data (dma_rsp_fifo_data[4:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = req_valid_d2 & (dma_rd_req_rdy | req_dummy_d2); +assign dma_req_fifo_data = {req_dummy_d2, req_size_d2}; +//////////////////////////////////////////////////////////////////////// +// CDMA WG read response connection // +//////////////////////////////////////////////////////////////////////// +assign dma_rd_rsp_data[511:0] = dma_rd_rsp_pd[511:0]; +assign dma_rd_rsp_mask[1:0] = dma_rd_rsp_pd[513:512]; +assign {dma_rsp_dummy, dma_rsp_size} = dma_rsp_fifo_data; +assign dma_rd_rsp_blocking = (dma_rsp_fifo_req & dma_rsp_dummy) | sbuf_blocking; +assign dma_rsp_mask[0] = (~dma_rsp_fifo_req | sbuf_blocking) ? 1'b0 : + ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[0]) : + 1'b1; +assign dma_rsp_mask[1] = (~dma_rsp_fifo_req | sbuf_blocking) ? 1'b0 : + ~dma_rsp_dummy ? (dma_rd_rsp_vld & dma_rd_rsp_mask[1]) : + (dma_rsp_size[3:1] == dma_rsp_size_cnt[3:1]) ? 1'b0 : + 1'b1; +assign {mon_dma_rsp_size_cnt_inc, + dma_rsp_size_cnt_inc} = dma_rsp_size_cnt + dma_rsp_mask[0] + dma_rsp_mask[1]; +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 4'b0 : + dma_rsp_size_cnt_inc; +assign dma_rsp_vld = dma_rsp_fifo_req & ~sbuf_blocking & (dma_rsp_dummy | dma_rd_rsp_vld); +assign dma_rsp_fifo_ready = (dma_rsp_vld & (dma_rsp_size_cnt_inc == dma_rsp_size)); +assign dma_pad_data = {64{reg2dp_pad_value[7:0]}}; +assign dma_rsp_data = dma_rsp_dummy ? dma_pad_data[511:0] : dma_rd_rsp_data[511:0]; +assign {dma_rsp_data_p1, dma_rsp_data_p0} = dma_rsp_data; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"dma_rsp_vld\" -d \"dma_rsp_size_cnt_w\" -q dma_rsp_size_cnt"); +//////////////////////////////////////////////////////////////////////// +// WG write data to shared buffer // +//////////////////////////////////////////////////////////////////////// +//////////////// line selection //////////////// +assign {mon_sbuf_wr_line_w, + sbuf_wr_line_w} = (layer_st) ? 3'b0 : + sbuf_wr_line + 1'b1; +assign is_sbuf_wr_last_line = (sbuf_wr_line == 2'h3); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"layer_st | dma_rsp_fifo_ready\" -d \"sbuf_wr_line_w\" -q sbuf_wr_line"); +//////////////// write port 0 //////////////// +assign sbuf_wr_add = dma_rsp_mask[1] ? 2'h2 : 2'h1; +assign {mon_sbuf_wr_p0_base_w, + sbuf_wr_p0_base_w} = (layer_st) ? 5'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? {1'b0, sbuf_wr_p0_base_ori} : + ((sbuf_wr_p0_ch[1:0] == 2'h3) & sbuf_wr_p0_of) ? sbuf_wr_p0_base + conv_x_stride : + ((sbuf_wr_p0_ch[1:0] == 2'h2) & is_x_stride_one & dma_rsp_mask[1]) ? sbuf_wr_p1_base + conv_x_stride : + sbuf_wr_p0_base; +assign {mon_sbuf_wr_p1_base_w, + sbuf_wr_p1_base_w} = (layer_st) ? 5'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? {1'b0, sbuf_wr_p1_base_ori} : + ((sbuf_wr_p1_ch[1:0] == 2'h3) & sbuf_wr_p1_of) ? sbuf_wr_p1_base + conv_x_stride : + ((sbuf_wr_p1_ch[1:0] == 2'h2) & is_x_stride_one & dma_rsp_mask[1]) ? sbuf_wr_p1_base + conv_x_stride : + sbuf_wr_p1_base; +assign sbuf_wr_p0_offset_inc = sbuf_wr_p0_offset + sbuf_wr_add; +assign sbuf_wr_p1_offset_inc = sbuf_wr_p1_offset + sbuf_wr_add; +assign sbuf_wr_p0_of_0 = (sbuf_wr_p0_offset_inc == conv_x_stride) | is_x_stride_one; +assign sbuf_wr_p0_of_1 = (sbuf_wr_p0_offset_inc > conv_x_stride); +assign sbuf_wr_p0_of = sbuf_wr_p0_of_0 | sbuf_wr_p0_of_1; +assign sbuf_wr_p1_of_0 = (sbuf_wr_p1_offset_inc == conv_x_stride) | is_x_stride_one; +assign sbuf_wr_p1_of_1 = (sbuf_wr_p1_offset_inc > conv_x_stride); +assign sbuf_wr_p1_of = sbuf_wr_p1_of_0 | sbuf_wr_p1_of_1; +assign sbuf_wr_p0_offset_w = (layer_st | is_x_stride_one) ? 3'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p0_offset_ori : + (sbuf_wr_p0_of_1) ? 3'b1 : + (sbuf_wr_p0_of_0) ? 3'b0 : + sbuf_wr_p0_offset_inc[2:0]; +assign sbuf_wr_p1_offset_w = (is_x_stride_one_w) ? 3'b0 : + (layer_st) ? 3'b1 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p1_offset_ori : + (sbuf_wr_p1_of_1) ? 3'b1 : + (sbuf_wr_p1_of_0) ? 3'b0 : + sbuf_wr_p1_offset_inc[2:0]; +assign {mon_sbuf_wr_p0_ch_inc, + sbuf_wr_p0_ch_inc} = (is_x_stride_one) ? (sbuf_wr_p0_ch + sbuf_wr_add) : + (sbuf_wr_p0_ch + 1'b1); +assign {mon_sbuf_wr_p1_ch_inc, + sbuf_wr_p1_ch_inc} = (is_x_stride_one) ? (sbuf_wr_p1_ch + sbuf_wr_add) : + (sbuf_wr_p1_ch + 1'b1); +assign sbuf_wr_p0_ch_w = (layer_st) ? 4'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p0_ch_ori : + (dma_rsp_fifo_ready & is_sbuf_wr_last_line & sbuf_wr_p0_of) ? {2'd0, sbuf_wr_p0_ch_inc[1:0]} : + (dma_rsp_fifo_ready & is_sbuf_wr_last_line & ~sbuf_wr_p0_of) ? {2'd0, sbuf_wr_p0_ch[1:0]} : + (sbuf_wr_p0_of) ? sbuf_wr_p0_ch_inc : + sbuf_wr_p0_ch; +assign sbuf_wr_p1_ch_w = (layer_st & is_x_stride_one_w) ? 2'b1 : + (layer_st & ~is_x_stride_one_w) ? 2'b0 : + (dma_rsp_fifo_ready & ~is_sbuf_wr_last_line) ? sbuf_wr_p1_ch_ori : + (sbuf_wr_p1_of) ? sbuf_wr_p1_ch_inc : + sbuf_wr_p1_ch; +assign sbuf_wr_addr_en = layer_st | dma_rsp_vld; +assign sbuf_wr_addr_ori_en = layer_st | (dma_rsp_fifo_ready & is_sbuf_wr_last_line); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p0_base_w\" -q sbuf_wr_p0_base"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p1_base_w\" -q sbuf_wr_p1_base"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p0_offset_w\" -q sbuf_wr_p0_offset"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p1_offset_w\" -q sbuf_wr_p1_offset"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p0_ch_w\" -q sbuf_wr_p0_ch"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sbuf_wr_addr_en\" -d \"sbuf_wr_p1_ch_w\" -q sbuf_wr_p1_ch"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p0_base_w\" -q sbuf_wr_p0_base_ori"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p1_base_w\" -q sbuf_wr_p1_base_ori"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p0_offset_w\" -q sbuf_wr_p0_offset_ori"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p1_offset_w\" -q sbuf_wr_p1_offset_ori"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p0_ch_w\" -q sbuf_wr_p0_ch_ori"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sbuf_wr_addr_ori_en\" -d \"sbuf_wr_p1_ch_w\" -q sbuf_wr_p1_ch_ori"); +//////////////// current write index //////////////// +assign {mon_sbuf_wr_p0_idx_lo, + sbuf_wr_p0_idx_lo} = sbuf_wr_p0_base + sbuf_wr_p0_offset; +assign {mon_sbuf_wr_p1_idx_lo, + sbuf_wr_p1_idx_lo} = sbuf_wr_p1_base + sbuf_wr_p1_offset; +assign sbuf_wr_p0_idx = {sbuf_wr_p0_idx_lo[0], sbuf_wr_line[0], sbuf_wr_p0_ch[1:0], sbuf_wr_line[1], sbuf_wr_p0_idx_lo[8 -5:1]}; +assign sbuf_wr_p1_idx = {sbuf_wr_p1_idx_lo[0], sbuf_wr_line[0], sbuf_wr_p1_ch[1:0], sbuf_wr_line[1], sbuf_wr_p1_idx_lo[8 -5:1]}; +assign sbuf_x_stride_inc_size = (~dma_rsp_fifo_ready | ~is_sbuf_wr_last_line) ? 2'b0 : + (sbuf_wr_p0_of) ? sbuf_wr_p0_ch_inc[3:2] : sbuf_wr_p0_ch[3:2]; +assign sbuf_cube_inc_size = sbuf_x_stride_inc_size[1] ? {conv_x_stride[2:0], 1'b0} : + sbuf_x_stride_inc_size[0] ? conv_x_stride : + 4'b0; +assign sbuf_wr_p0_en = dma_rsp_vld & dma_rsp_mask[0]; +assign sbuf_wr_p1_en = dma_rsp_vld & dma_rsp_mask[1]; +assign sbuf_cube_inc_en = dma_rsp_fifo_ready & is_sbuf_wr_last_line; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_wr_p0_en\" -q sbuf_wr_p0_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_wr_p1_en\" -q sbuf_wr_p1_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_wr_p0_en\" -d \"sbuf_wr_p0_idx\" -q sbuf_wr_p0_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_wr_p1_en\" -d \"sbuf_wr_p1_idx\" -q sbuf_wr_p1_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{256{1'b0}}\" -en \"sbuf_wr_p0_en\" -d \"dma_rsp_data_p0\" -q sbuf_wr_p0_data_d1"); +//: &eperl::flop("-nodeclare -rval \"{256{1'b0}}\" -en \"sbuf_wr_p1_en\" -d \"dma_rsp_data_p1\" -q sbuf_wr_p1_data_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_cube_inc_en\" -q sbuf_cube_inc_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"sbuf_cube_inc_en\" -d \"sbuf_cube_inc_size\" -q sbuf_cube_inc_size_d1"); +//////////////////////////////////////////////////////////////////////// +// Shared buffer write signals // +//////////////////////////////////////////////////////////////////////// +assign wg2sbuf_p0_wr_en = sbuf_wr_p0_en_d1; +assign wg2sbuf_p1_wr_en = sbuf_wr_p1_en_d1; +assign wg2sbuf_p0_wr_addr = sbuf_wr_p0_idx_d1; +assign wg2sbuf_p1_wr_addr = sbuf_wr_p1_idx_d1; +assign wg2sbuf_p0_wr_data = sbuf_wr_p0_data_d1; +assign wg2sbuf_p1_wr_data = sbuf_wr_p1_data_d1; +//////////////////////////////////////////////////////////////////////// +// WG read data from shared buffer // +//////////////////////////////////////////////////////////////////////// +assign sbuf_avl_cube_add = sbuf_cube_inc_en_d1 ? sbuf_cube_inc_size_d1 : 4'b0; +assign sbuf_avl_cube_sub = sbuf_rd_en & (rd_sub_cnt == 3'h7); +assign {mon_sbuf_avl_cube_w, + sbuf_avl_cube_w} = (layer_st) ? 5'b0 : + (sbuf_avl_cube + sbuf_avl_cube_add - sbuf_avl_cube_sub); +assign sbuf_blocking_w = (sbuf_avl_cube_w >= 4'h8) ? 1'b1 : 1'b0; +assign sbuf_rd_en = (|sbuf_avl_cube); +assign {mon_rd_sub_cnt_w, + rd_sub_cnt_w} = (layer_st) ? 4'b0 : + (rd_sub_cnt + 1'b1); +assign sbuf_avl_cube_en = sbuf_avl_cube_sub | sbuf_cube_inc_en_d1; +assign {mon_rd_cube_cnt_w, + rd_cube_cnt_w} = (layer_st) ? 5'b0 : + rd_cube_cnt + 1; +assign sbuf_rd_p0_idx = {rd_cube_cnt[0], 1'b0, rd_sub_cnt[0], rd_cube_cnt[8 -5:1], rd_sub_cnt[2:1]}; +assign sbuf_rd_p1_idx = {rd_cube_cnt[0], 1'b1, rd_sub_cnt[0], rd_cube_cnt[8 -5:1], rd_sub_cnt[2:1]}; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st | sbuf_avl_cube_en\" -d \"sbuf_avl_cube_w\" -q sbuf_avl_cube"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st | sbuf_avl_cube_en\" -d \"sbuf_blocking_w\" -q sbuf_blocking"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st | sbuf_avl_cube_sub\" -d \"rd_cube_cnt_w\" -q rd_cube_cnt"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"layer_st | sbuf_rd_en\" -d \"rd_sub_cnt_w\" -q rd_sub_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sbuf_rd_en\" -q sbuf_rd_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_rd_en\" -d \"sbuf_rd_p0_idx\" -q sbuf_rd_p0_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"sbuf_rd_en\" -d \"sbuf_rd_p1_idx\" -q sbuf_rd_p1_idx_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sbuf_rd_en\" -d \"rd_sub_cnt[1:0]\" -q sbuf_rd_sel_d1"); +//////////////////////////////////////////////////////////////////////// +// Shared buffer read signals // +//////////////////////////////////////////////////////////////////////// +assign wg2sbuf_p0_rd_en = sbuf_rd_en_d1; +assign wg2sbuf_p1_rd_en = sbuf_rd_en_d1; +assign wg2sbuf_p0_rd_addr = sbuf_rd_p0_idx_d1; +assign wg2sbuf_p1_rd_addr = sbuf_rd_p1_idx_d1; +//////////////////////////////////////////////////////////////////////// +// pipeline to sync the sbuf read to output to convertor // +//////////////////////////////////////////////////////////////////////// +//: my $latency = 2; +//: my $i; +//: my $j; +//: if($latency == 0) { +//: print "assign rsp_vld = sbuf_rd_en_d1;\n"; +//: print "assign rsp_sel = sbuf_rd_sel_d1;\n"; +//: } else { +//: print "assign rsp_vld_d0 = sbuf_rd_en_d1;\n"; +//: print "assign rsp_sel_d0 = sbuf_rd_sel_d1;\n"; +//: for($i = 0; $i < $latency; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"rsp_vld_d${i}\" -q rsp_vld_d${j}"); +//: &eperl::flop("-wid 2 -rval \"{2{1'b0}}\" -en \"rsp_vld_d${i}\" -d \"rsp_sel_d${i}\" -q rsp_sel_d${j}"); +//: } +//: print "\n\n"; +//: print "assign rsp_vld = rsp_vld_d${i};\n"; +//: print "assign rsp_sel = rsp_sel_d${i};\n\n\n"; +//: } +//////////////////////////////////////////////////////////////////////// +// WG local cache // +//////////////////////////////////////////////////////////////////////// +assign rsp_data_l0c0_en = (rsp_vld & (rsp_sel == 2'h0)); +assign rsp_data_l0c1_en = (rsp_vld & (rsp_sel == 2'h1)); +assign rsp_data_l1c0_en = (rsp_vld & (rsp_sel == 2'h2)); +assign rsp_data_l1c1_en = (rsp_vld & (rsp_sel == 2'h3)); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l0c0_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l0c0"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l0c1_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l0c1"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l1c0_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l1c0"); +//: &eperl::flop("-nodeclare -norst -en \"rsp_data_l1c1_en\" -d \"{wg2sbuf_p1_rd_data, wg2sbuf_p0_rd_data}\" -q rsp_data_l1c1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_vld\" -q rsp_dat_vld_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_dat_vld_d1\" -q rsp_dat_vld_d2"); +//////////////////////////////////////////////////////////////////////// +// WG response data counter // +//////////////////////////////////////////////////////////////////////// +//////////////// sub cube count //////////////// +assign {mon_rsp_sub_cube_cnt_inc, + rsp_sub_cube_cnt_inc} = rsp_sub_cube_cnt + 1'b1; +assign rsp_sub_cube_cnt_w = (layer_st | is_rsp_last_sub_cube) ? 3'b0 : + rsp_sub_cube_cnt_inc; +assign is_rsp_last_sub_cube = (rsp_sub_cube_cnt == 3'h7); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rsp_sub_cube_en\" -d \"rsp_sub_cube_cnt_w\" -q rsp_sub_cube_cnt"); +//////////////// conv x stride count //////////////// +assign {mon_rsp_x_std_cnt_inc, + rsp_x_std_cnt_inc} = rsp_x_std_cnt + 1'b1; +assign rsp_x_std_cnt_w = (layer_st | is_rsp_last_x_std) ? 3'b0 : + rsp_x_std_cnt_inc; +assign is_rsp_last_x_std = (rsp_x_std_cnt == reg2dp_conv_x_stride); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rsp_x_std_en\" -d \"rsp_x_std_cnt_w\" -q rsp_x_std_cnt"); +//////////////// width_ext count //////////////// +assign {mon_rsp_width_cnt_inc, + rsp_width_cnt_inc} = rsp_width_cnt + 1'b1; +assign rsp_width_cnt_w = (layer_st | is_rsp_last_width) ? 11'b0 : + rsp_width_cnt_inc; +assign is_rsp_last_width = (rsp_width_cnt == width_ext_total); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"rsp_width_en\" -d \"rsp_width_cnt_w\" -q rsp_width_cnt"); +//////////////// conv y stride count //////////////// +assign {mon_rsp_y_std_cnt_inc, + rsp_y_std_cnt_inc} = rsp_y_std_cnt + 1'b1; +assign rsp_y_std_cnt_w = (layer_st | is_rsp_last_y_std) ? 3'b0 : + rsp_y_std_cnt_inc; +assign is_rsp_last_y_std = (rsp_y_std_cnt == reg2dp_conv_y_stride); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"rsp_y_std_en\" -d \"rsp_y_std_cnt_w\" -q rsp_y_std_cnt"); +//////////////// surf count //////////////// +assign {mon_rsp_surf_cnt_inc, + rsp_surf_cnt_inc} = rsp_surf_cnt + 1'b1; +assign rsp_surf_cnt_w = (layer_st | is_rsp_last_surf) ? 4'b0 : + rsp_surf_cnt_inc; +assign is_rsp_last_surf = (rsp_surf_cnt == surf_cnt_total); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"rsp_surf_en\" -d \"rsp_surf_cnt_w\" -q rsp_surf_cnt"); +//////////////// height ext //////////////// +assign {mon_rsp_h_ext_cnt_inc, + rsp_h_ext_cnt_inc} = rsp_h_ext_cnt + 1'b1; +assign rsp_h_ext_cnt_w = layer_st ? 11'b0 : + rsp_h_ext_cnt_inc; +assign is_rsp_last_h_ext = (rsp_h_ext_cnt == height_ext_total); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"rsp_h_ext_en\" -d \"rsp_h_ext_cnt_w\" -q rsp_h_ext_cnt"); +//////////////// control signal //////////////// +assign rsp_en = rsp_dat_vld_d2; +assign rsp_sub_cube_en = layer_st | rsp_en; +assign rsp_x_std_en = layer_st | (rsp_en & is_rsp_last_sub_cube); +assign rsp_width_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std); +assign rsp_y_std_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width); +assign rsp_surf_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std); +assign rsp_h_ext_en = layer_st | (rsp_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std & is_rsp_last_surf); +assign is_slice_done = (is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std & is_rsp_last_surf); +assign is_last_rsp = (is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std & is_rsp_last_surf & is_rsp_last_h_ext); +//////////////////////////////////////////////////////////////////////// +// WG response CBUF address generator // +//////////////////////////////////////////////////////////////////////// +//////////////// base address //////////////// +assign {mon_rsp_addr_offset_w, + rsp_addr_offset_w} = layer_st ? 13'b0 : + rsp_addr_offset + data_entries; +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"is_first_running\" -d \"status2dma_wr_idx\" -q rsp_addr_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_h_ext_en\" -d \"rsp_addr_offset_w\" -q rsp_addr_offset"); +//////////////// offset //////////////// +//aaa = rsp_sub_surf * data_width_ext +//bbb = rsp_sub_surf * data_width_ext * conv_x_stride; +//ccc = rsp_sub_surf_per_surf * data_width_ext; +assign rsp_ch_x_std_add = {w_ext_surf[12 -3:0], 2'b0}; +assign rsp_ch_y_std_add = {h_ext_surf[12 -3:0], 2'b0}; +assign rsp_ch_surf_add = {data_width_ext[12 -3:0], 2'b0}; +assign {mon_rsp_ch_offset_w, + rsp_ch_offset_w} = (layer_st) ? 13'b0 : + (~is_rsp_last_sub_cube) ? (rsp_ch_offset + data_width_ext) : + (~is_rsp_last_x_std) ? (rsp_ch_x_std_base + rsp_ch_x_std_add) : + (~is_rsp_last_width) ? (rsp_ch_w_base + 1'b1) : + (~is_rsp_last_y_std) ? (rsp_ch_y_std_base + rsp_ch_y_std_add) : + (~is_rsp_last_surf) ? (rsp_ch_surf_base + rsp_ch_surf_add) : + 13'b0; +assign rsp_ch_offset_en = (rsp_en & rsp_sub_cube_cnt[0]); +assign rsp_ch_x_std_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube; +assign rsp_ch_w_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube & is_rsp_last_x_std; +assign rsp_ch_y_std_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width; +assign rsp_ch_surf_base_en = rsp_ch_offset_en & is_rsp_last_sub_cube & is_rsp_last_x_std & is_rsp_last_width & is_rsp_last_y_std; +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_offset_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_offset"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_x_std_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_x_std_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_w_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_w_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_y_std_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_y_std_base"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_ch_surf_base_en\" -d \"rsp_ch_offset_w\" -q rsp_ch_surf_base"); +//////////////// write address //////////////// +assign {mon_rsp_addr_inc, + rsp_addr_inc} = rsp_addr_base + rsp_addr_offset + rsp_ch_offset; +assign {mon_rsp_addr_wrap, +//rsp_addr_wrap} = rsp_addr_inc - {1'b0, data_bank, 8'b0}; + rsp_addr_wrap} = rsp_addr_inc - {data_bank, 9'b0}; +//assign is_rsp_addr_wrap = rsp_addr_inc[12 : 8 ] >= {1'b0, data_bank}; +assign is_rsp_addr_wrap = {1'b0,rsp_addr_inc[12 : 9 ]} >= data_bank; +assign rsp_addr = ~is_rsp_addr_wrap ? rsp_addr_inc[12 -1:0] : + rsp_addr_wrap; +assign rsp_hsel = rsp_sub_cube_cnt[0]; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_en\" -q rsp_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"rsp_en\" -d \"rsp_addr\" -q rsp_addr_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_en\" -d \"rsp_hsel\" -q rsp_hsel_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"rsp_en & is_slice_done\" -q rsp_slice_done_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"rsp_en\" -d \"is_last_rsp\" -q rsp_layer_done_d1"); +//////////////////////////////////////////////////////////////////////// +// WG response data output // +//////////////////////////////////////////////////////////////////////// +assign rsp_data_l0 = {rsp_data_l0c1, rsp_data_l0c0}; +assign rsp_data_l1 = {rsp_data_l1c1, rsp_data_l1c0}; +assign dat_cur = rsp_sub_cube_cnt[1] ? rsp_data_l1 : rsp_data_l0; +assign dat_cur_remapped = dat_cur; +assign rsp_data_d1_w = rsp_sub_cube_cnt[0] ? dat_cur_remapped[1023:512] : + dat_cur_remapped[511:0]; +//: &eperl::flop("-nodeclare -norst -en \"rsp_en\" -d \"rsp_data_d1_w\" -q rsp_data_d1"); +//////////////////////////////////////////////////////////////////////// +// WG to CDMA convertor // +//////////////////////////////////////////////////////////////////////// +assign wg2cvt_dat_wr_en = rsp_en_d1; +assign wg2cvt_dat_wr_addr = rsp_addr_d1; +assign wg2cvt_dat_wr_sel = rsp_hsel_d1; +assign wg2cvt_dat_wr_data = rsp_data_d1; +assign cbuf_wr_info_mask = 4'h3; +assign cbuf_wr_info_interleave = 1'b0; +assign cbuf_wr_info_ext64 = 1'b0; +assign cbuf_wr_info_ext128 = 1'b0; +assign cbuf_wr_info_mean = 1'b0; +assign cbuf_wr_info_uint = 1'b0; +assign cbuf_wr_info_sub_h = 3'b0; +assign wg2cvt_dat_wr_info_pd[3:0] = cbuf_wr_info_mask[3:0]; +assign wg2cvt_dat_wr_info_pd[4] = cbuf_wr_info_interleave ; +assign wg2cvt_dat_wr_info_pd[5] = cbuf_wr_info_ext64 ; +assign wg2cvt_dat_wr_info_pd[6] = cbuf_wr_info_ext128 ; +assign wg2cvt_dat_wr_info_pd[7] = cbuf_wr_info_mean ; +assign wg2cvt_dat_wr_info_pd[8] = cbuf_wr_info_uint ; +assign wg2cvt_dat_wr_info_pd[11:9] = cbuf_wr_info_sub_h[2:0]; +//////////////////////////////////////////////////////////////////////// +// WG response done signal // +//////////////////////////////////////////////////////////////////////// +assign is_rsp_done_w = layer_st ? 1'b0 : + (rsp_en_d1 & rsp_layer_done_d1) ? 1'b1 : + is_rsp_done; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"is_rsp_done_w\" -q is_rsp_done"); +//////////////////////////////////////////////////////////////////////// +// WG to status update // +//////////////////////////////////////////////////////////////////////// +assign wg2status_dat_updt = rsp_slice_done_d1; +assign wg2status_dat_entries = data_entries; +assign wg2status_dat_slices = 14'h4; +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_stall_inc <= 1'b0; + end else begin + wg_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_stall_clr <= 1'b0; + end else begin + wg_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_stall_cen <= 1'b0; + end else begin + wg_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_wg_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = wg_rd_stall_inc ^ dp2reg_wg_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wg_rd_stall_inc && !dp2reg_wg_rd_stall_dec)? stl_cnt_inc : (!wg_rd_stall_inc && dp2reg_wg_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (wg_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (wg_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_wg_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_inc <= 1'b0; + end else begin + wg_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_dec <= 1'b0; + end else begin + wg_rd_latency_dec <= dma_rsp_fifo_ready & ~dma_rsp_dummy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_clr <= 1'b0; + end else begin + wg_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wg_rd_latency_cen <= 1'b0; + end else begin + wg_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign ltc_1_inc = (outs_dp2reg_wg_rd_latency!=511) & wg_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_wg_rd_latency!=511) & wg_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (wg_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (wg_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_wg_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +assign ltc_2_dec = 1'b0; +assign ltc_2_inc = (~&dp2reg_wg_rd_latency) & (|outs_dp2reg_wg_rd_latency); +// ltc_2 adv logic +always @(*) begin + ltc_2_adv = ltc_2_inc ^ ltc_2_dec; +end +// ltc_2 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_2_cnt_ext[33:0] = {1'b0, 1'b0, ltc_2_cnt_cur}; + ltc_2_cnt_inc[33:0] = ltc_2_cnt_cur + 1'b1; // spyglass disable W164b + ltc_2_cnt_dec[33:0] = ltc_2_cnt_cur - 1'b1; // spyglass disable W164b + ltc_2_cnt_mod[33:0] = (ltc_2_inc && !ltc_2_dec)? ltc_2_cnt_inc : (!ltc_2_inc && ltc_2_dec)? ltc_2_cnt_dec : ltc_2_cnt_ext; + ltc_2_cnt_new[33:0] = (ltc_2_adv)? ltc_2_cnt_mod[33:0] : ltc_2_cnt_ext[33:0]; + ltc_2_cnt_nxt[33:0] = (wg_rd_latency_clr)? 34'd0 : ltc_2_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// ltc_2 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_2_cnt_cur[31:0] <= 0; + end else begin + if (wg_rd_latency_cen) begin + ltc_2_cnt_cur[31:0] <= ltc_2_cnt_nxt[31:0]; + end + end +end +// ltc_2 output logic +always @(*) begin + dp2reg_wg_rd_latency[31:0] = ltc_2_cnt_cur[31:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_wg__rsp_addr_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (rsp_en & is_rsp_addr_wrap); + endproperty +// Cover 0 : "(rsp_en & is_rsp_addr_wrap)" + FUNCPOINT_cdma_wg__rsp_addr_wrap__0_COV : cover property (cdma_wg__rsp_addr_wrap__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_wg__wg_conv_stride_EQ_0__1_0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_0 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_0__1_0_COV : cover property (cdma_wg__wg_conv_stride_EQ_0__1_0_cov); + property cdma_wg__wg_conv_stride_EQ_1__1_1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_1 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_1__1_1_COV : cover property (cdma_wg__wg_conv_stride_EQ_1__1_1_cov); + property cdma_wg__wg_conv_stride_EQ_2__1_2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_2 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_2__1_2_COV : cover property (cdma_wg__wg_conv_stride_EQ_2__1_2_cov); + property cdma_wg__wg_conv_stride_EQ_3__1_3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_3 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_3__1_3_COV : cover property (cdma_wg__wg_conv_stride_EQ_3__1_3_cov); + property cdma_wg__wg_conv_stride_EQ_4__1_4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_4 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_4__1_4_COV : cover property (cdma_wg__wg_conv_stride_EQ_4__1_4_cov); + property cdma_wg__wg_conv_stride_EQ_5__1_5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_5 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_5__1_5_COV : cover property (cdma_wg__wg_conv_stride_EQ_5__1_5_cov); + property cdma_wg__wg_conv_stride_EQ_6__1_6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_6 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_6__1_6_COV : cover property (cdma_wg__wg_conv_stride_EQ_6__1_6_cov); + property cdma_wg__wg_conv_stride_EQ_7__1_7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_7 : "(reg2dp_conv_x_stride == 0) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_7__1_7_COV : cover property (cdma_wg__wg_conv_stride_EQ_7__1_7_cov); + property cdma_wg__wg_conv_stride_EQ_8__1_8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_8 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_8__1_8_COV : cover property (cdma_wg__wg_conv_stride_EQ_8__1_8_cov); + property cdma_wg__wg_conv_stride_EQ_9__1_9_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_9 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_9__1_9_COV : cover property (cdma_wg__wg_conv_stride_EQ_9__1_9_cov); + property cdma_wg__wg_conv_stride_EQ_10__1_10_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_10 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_10__1_10_COV : cover property (cdma_wg__wg_conv_stride_EQ_10__1_10_cov); + property cdma_wg__wg_conv_stride_EQ_11__1_11_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_11 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_11__1_11_COV : cover property (cdma_wg__wg_conv_stride_EQ_11__1_11_cov); + property cdma_wg__wg_conv_stride_EQ_12__1_12_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_12 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_12__1_12_COV : cover property (cdma_wg__wg_conv_stride_EQ_12__1_12_cov); + property cdma_wg__wg_conv_stride_EQ_13__1_13_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_13 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_13__1_13_COV : cover property (cdma_wg__wg_conv_stride_EQ_13__1_13_cov); + property cdma_wg__wg_conv_stride_EQ_14__1_14_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_14 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_14__1_14_COV : cover property (cdma_wg__wg_conv_stride_EQ_14__1_14_cov); + property cdma_wg__wg_conv_stride_EQ_15__1_15_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_15 : "(reg2dp_conv_x_stride == 1) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_15__1_15_COV : cover property (cdma_wg__wg_conv_stride_EQ_15__1_15_cov); + property cdma_wg__wg_conv_stride_EQ_16__1_16_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_16 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_16__1_16_COV : cover property (cdma_wg__wg_conv_stride_EQ_16__1_16_cov); + property cdma_wg__wg_conv_stride_EQ_17__1_17_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_17 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_17__1_17_COV : cover property (cdma_wg__wg_conv_stride_EQ_17__1_17_cov); + property cdma_wg__wg_conv_stride_EQ_18__1_18_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_18 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_18__1_18_COV : cover property (cdma_wg__wg_conv_stride_EQ_18__1_18_cov); + property cdma_wg__wg_conv_stride_EQ_19__1_19_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_19 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_19__1_19_COV : cover property (cdma_wg__wg_conv_stride_EQ_19__1_19_cov); + property cdma_wg__wg_conv_stride_EQ_20__1_20_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_20 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_20__1_20_COV : cover property (cdma_wg__wg_conv_stride_EQ_20__1_20_cov); + property cdma_wg__wg_conv_stride_EQ_21__1_21_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_21 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_21__1_21_COV : cover property (cdma_wg__wg_conv_stride_EQ_21__1_21_cov); + property cdma_wg__wg_conv_stride_EQ_22__1_22_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_22 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_22__1_22_COV : cover property (cdma_wg__wg_conv_stride_EQ_22__1_22_cov); + property cdma_wg__wg_conv_stride_EQ_23__1_23_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_23 : "(reg2dp_conv_x_stride == 2) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_23__1_23_COV : cover property (cdma_wg__wg_conv_stride_EQ_23__1_23_cov); + property cdma_wg__wg_conv_stride_EQ_24__1_24_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_24 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_24__1_24_COV : cover property (cdma_wg__wg_conv_stride_EQ_24__1_24_cov); + property cdma_wg__wg_conv_stride_EQ_25__1_25_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_25 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_25__1_25_COV : cover property (cdma_wg__wg_conv_stride_EQ_25__1_25_cov); + property cdma_wg__wg_conv_stride_EQ_26__1_26_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_26 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_26__1_26_COV : cover property (cdma_wg__wg_conv_stride_EQ_26__1_26_cov); + property cdma_wg__wg_conv_stride_EQ_27__1_27_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_27 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_27__1_27_COV : cover property (cdma_wg__wg_conv_stride_EQ_27__1_27_cov); + property cdma_wg__wg_conv_stride_EQ_28__1_28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_28 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_28__1_28_COV : cover property (cdma_wg__wg_conv_stride_EQ_28__1_28_cov); + property cdma_wg__wg_conv_stride_EQ_29__1_29_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_29 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_29__1_29_COV : cover property (cdma_wg__wg_conv_stride_EQ_29__1_29_cov); + property cdma_wg__wg_conv_stride_EQ_30__1_30_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_30 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_30__1_30_COV : cover property (cdma_wg__wg_conv_stride_EQ_30__1_30_cov); + property cdma_wg__wg_conv_stride_EQ_31__1_31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_31 : "(reg2dp_conv_x_stride == 3) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_31__1_31_COV : cover property (cdma_wg__wg_conv_stride_EQ_31__1_31_cov); + property cdma_wg__wg_conv_stride_EQ_32__1_32_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_32 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_32__1_32_COV : cover property (cdma_wg__wg_conv_stride_EQ_32__1_32_cov); + property cdma_wg__wg_conv_stride_EQ_33__1_33_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_33 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_33__1_33_COV : cover property (cdma_wg__wg_conv_stride_EQ_33__1_33_cov); + property cdma_wg__wg_conv_stride_EQ_34__1_34_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_34 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_34__1_34_COV : cover property (cdma_wg__wg_conv_stride_EQ_34__1_34_cov); + property cdma_wg__wg_conv_stride_EQ_35__1_35_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_35 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_35__1_35_COV : cover property (cdma_wg__wg_conv_stride_EQ_35__1_35_cov); + property cdma_wg__wg_conv_stride_EQ_36__1_36_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_36 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_36__1_36_COV : cover property (cdma_wg__wg_conv_stride_EQ_36__1_36_cov); + property cdma_wg__wg_conv_stride_EQ_37__1_37_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_37 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_37__1_37_COV : cover property (cdma_wg__wg_conv_stride_EQ_37__1_37_cov); + property cdma_wg__wg_conv_stride_EQ_38__1_38_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_38 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_38__1_38_COV : cover property (cdma_wg__wg_conv_stride_EQ_38__1_38_cov); + property cdma_wg__wg_conv_stride_EQ_39__1_39_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_39 : "(reg2dp_conv_x_stride == 4) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_39__1_39_COV : cover property (cdma_wg__wg_conv_stride_EQ_39__1_39_cov); + property cdma_wg__wg_conv_stride_EQ_40__1_40_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_40 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_40__1_40_COV : cover property (cdma_wg__wg_conv_stride_EQ_40__1_40_cov); + property cdma_wg__wg_conv_stride_EQ_41__1_41_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_41 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_41__1_41_COV : cover property (cdma_wg__wg_conv_stride_EQ_41__1_41_cov); + property cdma_wg__wg_conv_stride_EQ_42__1_42_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_42 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_42__1_42_COV : cover property (cdma_wg__wg_conv_stride_EQ_42__1_42_cov); + property cdma_wg__wg_conv_stride_EQ_43__1_43_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_43 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_43__1_43_COV : cover property (cdma_wg__wg_conv_stride_EQ_43__1_43_cov); + property cdma_wg__wg_conv_stride_EQ_44__1_44_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_44 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_44__1_44_COV : cover property (cdma_wg__wg_conv_stride_EQ_44__1_44_cov); + property cdma_wg__wg_conv_stride_EQ_45__1_45_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_45 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_45__1_45_COV : cover property (cdma_wg__wg_conv_stride_EQ_45__1_45_cov); + property cdma_wg__wg_conv_stride_EQ_46__1_46_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_46 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_46__1_46_COV : cover property (cdma_wg__wg_conv_stride_EQ_46__1_46_cov); + property cdma_wg__wg_conv_stride_EQ_47__1_47_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_47 : "(reg2dp_conv_x_stride == 5) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_47__1_47_COV : cover property (cdma_wg__wg_conv_stride_EQ_47__1_47_cov); + property cdma_wg__wg_conv_stride_EQ_48__1_48_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_48 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_48__1_48_COV : cover property (cdma_wg__wg_conv_stride_EQ_48__1_48_cov); + property cdma_wg__wg_conv_stride_EQ_49__1_49_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_49 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_49__1_49_COV : cover property (cdma_wg__wg_conv_stride_EQ_49__1_49_cov); + property cdma_wg__wg_conv_stride_EQ_50__1_50_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_50 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_50__1_50_COV : cover property (cdma_wg__wg_conv_stride_EQ_50__1_50_cov); + property cdma_wg__wg_conv_stride_EQ_51__1_51_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_51 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_51__1_51_COV : cover property (cdma_wg__wg_conv_stride_EQ_51__1_51_cov); + property cdma_wg__wg_conv_stride_EQ_52__1_52_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_52 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_52__1_52_COV : cover property (cdma_wg__wg_conv_stride_EQ_52__1_52_cov); + property cdma_wg__wg_conv_stride_EQ_53__1_53_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_53 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_53__1_53_COV : cover property (cdma_wg__wg_conv_stride_EQ_53__1_53_cov); + property cdma_wg__wg_conv_stride_EQ_54__1_54_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_54 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_54__1_54_COV : cover property (cdma_wg__wg_conv_stride_EQ_54__1_54_cov); + property cdma_wg__wg_conv_stride_EQ_55__1_55_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_55 : "(reg2dp_conv_x_stride == 6) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_55__1_55_COV : cover property (cdma_wg__wg_conv_stride_EQ_55__1_55_cov); + property cdma_wg__wg_conv_stride_EQ_56__1_56_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 0)); + endproperty +// Cover 1_56 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 0)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_56__1_56_COV : cover property (cdma_wg__wg_conv_stride_EQ_56__1_56_cov); + property cdma_wg__wg_conv_stride_EQ_57__1_57_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 1)); + endproperty +// Cover 1_57 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 1)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_57__1_57_COV : cover property (cdma_wg__wg_conv_stride_EQ_57__1_57_cov); + property cdma_wg__wg_conv_stride_EQ_58__1_58_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 2)); + endproperty +// Cover 1_58 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 2)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_58__1_58_COV : cover property (cdma_wg__wg_conv_stride_EQ_58__1_58_cov); + property cdma_wg__wg_conv_stride_EQ_59__1_59_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 3)); + endproperty +// Cover 1_59 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 3)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_59__1_59_COV : cover property (cdma_wg__wg_conv_stride_EQ_59__1_59_cov); + property cdma_wg__wg_conv_stride_EQ_60__1_60_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 4)); + endproperty +// Cover 1_60 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 4)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_60__1_60_COV : cover property (cdma_wg__wg_conv_stride_EQ_60__1_60_cov); + property cdma_wg__wg_conv_stride_EQ_61__1_61_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 5)); + endproperty +// Cover 1_61 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 5)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_61__1_61_COV : cover property (cdma_wg__wg_conv_stride_EQ_61__1_61_cov); + property cdma_wg__wg_conv_stride_EQ_62__1_62_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 6)); + endproperty +// Cover 1_62 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 6)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_62__1_62_COV : cover property (cdma_wg__wg_conv_stride_EQ_62__1_62_cov); + property cdma_wg__wg_conv_stride_EQ_63__1_63_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((layer_st) && nvdla_core_rstn) |-> ((reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 7)); + endproperty +// Cover 1_63 : "(reg2dp_conv_x_stride == 7) && (reg2dp_conv_y_stride == 7)" + FUNCPOINT_cdma_wg__wg_conv_stride_EQ_63__1_63_COV : cover property (cdma_wg__wg_conv_stride_EQ_63__1_63_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property cdma_wg__wg_reuse__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cur_state == WG_STATE_IDLE) & (nxt_state == WG_STATE_DONE)); + endproperty +// Cover 2 : "((cur_state == WG_STATE_IDLE) & (nxt_state == WG_STATE_DONE))" + FUNCPOINT_cdma_wg__wg_reuse__2_COV : cover property (cdma_wg__wg_reuse__2_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_rsp_done | is_done))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(reg2dp_op_en & is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wg_entry_onfly_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_surf_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_y_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_w_set_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_sub_w_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_sub_h_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_sub_h_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_y_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_surf_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_adv))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_adv))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_adv))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_valid_d1 & req_ready_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_71x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_valid_d1 & req_ready_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(req_valid_d1 & req_ready_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rsp_vld))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | dma_rsp_fifo_ready))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_85x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_addr_ori_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p0_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_100x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_wr_p1_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_cube_inc_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_104x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_avl_cube_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_avl_cube_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_106x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_avl_cube_sub))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_107x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_108x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_109x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(sbuf_rd_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_vld_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_114x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_vld_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_115x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_sub_cube_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_x_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_117x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_width_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_118x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_y_std_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_119x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_surf_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_120x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_121x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(is_first_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_122x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_h_ext_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_124x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_offset_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_125x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_x_std_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_126x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_w_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_127x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_y_std_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_128x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_ch_surf_base_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_131x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_132x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_133x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rsp_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! fifo is not empty when done!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (is_rsp_done & dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Req is not done when rsp is done!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (is_running & is_rsp_done & ~is_req_done)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! entry_onfly is non zero when idle") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (fetch_done & |(wg_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error Config! None feature input when wg!") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (layer_st & is_wg & ~is_feature)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! data_entries_w is overflow!") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (layer_st & mon_data_entries_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! width is not divisible by conv_x_stride") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (layer_st & ((reg2dp_pad_left + reg2dp_datain_width + reg2dp_pad_right + 1) % conv_x_stride_w != 0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! height is not divisible by conv_y_stride") zzz_assert_never_35x (nvdla_core_clk, `ASSERT_RESET, (layer_st & ((reg2dp_pad_top + reg2dp_datain_height + reg2dp_pad_bottom + 1) % conv_y_stride_w != 0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! channel is not divisible by 16/32") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (layer_st & ((is_int8 & (reg2dp_datain_channel[4:0] != 5'h1f)) | (~is_int8 & (reg2dp_datain_channel[3:0] != 4'hf))))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! width_ext is not divisible by 4") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (reg2dp_datain_width_ext[1:0] != 2'b11))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! height_ext is not divisible by 4") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (reg2dp_datain_height_ext[1:0] != 2'b11))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! width and width_ext not match") zzz_assert_never_39x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (((reg2dp_pad_left + reg2dp_datain_width + reg2dp_pad_right + 1) / conv_x_stride_w) != (reg2dp_datain_width_ext + 1)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! height and height_ext not match") zzz_assert_never_40x (nvdla_core_clk, `ASSERT_RESET, (layer_st & (((reg2dp_pad_top + reg2dp_datain_height + reg2dp_pad_bottom + 1) / conv_y_stride_w) != (reg2dp_datain_height_ext + 1)))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error config! reg2dp_entries is out of range in winograd mode!") zzz_assert_never_41x (nvdla_core_clk, `ASSERT_RESET, (layer_st & is_wg & (|reg2dp_entries[11:10]))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! w_ext_surf_w is overflow!") zzz_assert_never_46x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & (|mon_w_ext_surf_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! h_ext_surf_w is overflow!") zzz_assert_never_47x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & (|mon_h_ext_surf_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! w_ext_surf_w is out of range when normal!") zzz_assert_never_49x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & w_ext_surf_w[12 -2])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! h_ext_surf_w is out of range when normal!") zzz_assert_never_51x (nvdla_core_clk, `ASSERT_RESET, (layer_st_d1 & h_ext_surf_w[12 -2])); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wg_entry_onfly_w is overflow!") zzz_assert_never_53x (nvdla_core_clk, `ASSERT_RESET, (wg_entry_onfly_en & mon_wg_entry_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wg_entry_onfly is not zero when idle!") zzz_assert_never_54x (nvdla_core_clk, `ASSERT_RESET, (~is_running & (|wg_entry_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_one_hot #(0,3,0,"Error! width section select error!") zzz_assert_one_hot_59x (nvdla_core_clk, `ASSERT_RESET, ({is_w_set_lp, is_w_set_di, is_w_set_rp})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! req_cbuf_needed is overflow!") zzz_assert_never_63x (nvdla_core_clk, `ASSERT_RESET, (mon_req_cubf_needed)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Receive input data when not busy") zzz_assert_never_74x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & ~is_running)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_76x (nvdla_core_clk, `ASSERT_RESET, (~dma_rsp_fifo_req & dma_rd_rsp_vld)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_77x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > dma_rsp_size)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_78x (nvdla_core_clk, `ASSERT_RESET, (mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_79x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_size_cnt_inc > 8'h8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! p0 overflow conflict!") zzz_assert_never_93x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & ~is_x_stride_one & sbuf_wr_p0_of_0 & sbuf_wr_p1_of_0 & (~is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! p1 overflow conflict!") zzz_assert_never_94x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & ~is_x_stride_one & sbuf_wr_p0_of_1 & sbuf_wr_p1_of_1 & (~is_idle))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf_wr_p0_ch_inc is overflow!") zzz_assert_never_95x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & mon_sbuf_wr_p0_ch_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf_wr_p0_ch_inc is out of range!") zzz_assert_never_96x (nvdla_core_clk, `ASSERT_RESET, (sbuf_wr_addr_en & (sbuf_wr_p0_ch_inc[3:2] > 2'h2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf x_stride increase size out of range!") zzz_assert_never_102x (nvdla_core_clk, `ASSERT_RESET, (sbuf_cube_inc_en & sbuf_x_stride_inc_size[1] & (|reg2dp_conv_x_stride))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf cube increase size out of range!") zzz_assert_never_103x (nvdla_core_clk, `ASSERT_RESET, (sbuf_cube_inc_en & (sbuf_cube_inc_size > 4'h8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rd_sub_cnt is not zero when idle!") zzz_assert_never_111x (nvdla_core_clk, `ASSERT_RESET, (~is_running & (|rd_sub_cnt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! sbuf_avl_cube_w is overflow!") zzz_assert_never_112x (nvdla_core_clk, `ASSERT_RESET, (sbuf_avl_cube_en & mon_sbuf_avl_cube_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_addr_offset is overflow!") zzz_assert_never_123x (nvdla_core_clk, `ASSERT_RESET, (mon_rsp_addr_offset_w & rsp_h_ext_en)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_offset_w is overflow!") zzz_assert_never_129x (nvdla_core_clk, `ASSERT_RESET, (rsp_ch_offset_en & mon_rsp_ch_offset_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_ch_offset_w is out of range!") zzz_assert_never_130x (nvdla_core_clk, `ASSERT_RESET, (rsp_ch_offset_en & (rsp_ch_offset_w > 12'd3840))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! rsp_addr_inc is overflow!") zzz_assert_never_134x (nvdla_core_clk, `ASSERT_RESET, (rsp_en & mon_rsp_addr_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_135x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && wg_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_wg +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_rd_req_pd (mc_int_rd_req_valid,mc_int_rd_req_ready) <= dma_rd_req_pd[78:0] (mc_dma_rd_req_vld,mc_dma_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_WG_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_req_pd + ,mc_dma_rd_req_vld + ,mc_int_rd_req_ready + ,mc_dma_rd_req_rdy + ,mc_int_rd_req_pd + ,mc_int_rd_req_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] dma_rd_req_pd; +input mc_dma_rd_req_vld; +input mc_int_rd_req_ready; +output mc_dma_rd_req_rdy; +output [78:0] mc_int_rd_req_pd; +output mc_int_rd_req_valid; +reg mc_dma_rd_req_rdy; +reg [78:0] mc_int_rd_req_pd; +reg mc_int_rd_req_valid; +reg [78:0] p1_pipe_data; +reg [78:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [78:0] p1_skid_data; +reg [78:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_dma_rd_req_vld + or p1_pipe_rand_ready + or dma_rd_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = dma_rd_req_pd[78:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_dma_rd_req_vld; + mc_dma_rd_req_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : dma_rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_dma_rd_req_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_dma_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mc_int_rd_req_ready + or p1_pipe_data + ) begin + mc_int_rd_req_valid = p1_pipe_valid; + p1_pipe_ready = mc_int_rd_req_ready; + mc_int_rd_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_136x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_rd_req_valid^mc_int_rd_req_ready^mc_dma_rd_req_vld^mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_137x (nvdla_core_clk, `ASSERT_RESET, (mc_dma_rd_req_vld && !mc_dma_rd_req_rdy), (mc_dma_rd_req_vld), (mc_dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_WG_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_rd_req_pd (cv_int_rd_req_valid,cv_int_rd_req_ready) <= dma_rd_req_pd[78:0] (cv_dma_rd_req_vld,cv_dma_rd_req_rdy) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os mc_dma_rd_rsp_pd (mc_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= mc_int_rd_rsp_pd[513:0] (mc_int_rd_rsp_valid,mc_int_rd_rsp_ready) +// ************************************************************************************************************** +module NV_NVDLA_CDMA_WG_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_rd_rsp_rdy + ,mc_int_rd_rsp_pd + ,mc_int_rd_rsp_valid + ,mc_dma_rd_rsp_pd + ,mc_dma_rd_rsp_vld + ,mc_int_rd_rsp_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dma_rd_rsp_rdy; +input [513:0] mc_int_rd_rsp_pd; +input mc_int_rd_rsp_valid; +output [513:0] mc_dma_rd_rsp_pd; +output mc_dma_rd_rsp_vld; +output mc_int_rd_rsp_ready; +reg [513:0] mc_dma_rd_rsp_pd; +reg mc_dma_rd_rsp_vld; +reg mc_int_rd_rsp_ready; +reg [513:0] p3_pipe_data; +reg [513:0] p3_pipe_rand_data; +reg p3_pipe_rand_ready; +reg p3_pipe_rand_valid; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg [513:0] p3_pipe_skid_data; +reg p3_pipe_skid_ready; +reg p3_pipe_skid_valid; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [513:0] p3_skid_data; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) randomizer +`ifndef SYNTHESIS +reg p3_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p3_pipe_rand_active + or + `endif + mc_int_rd_rsp_valid + or p3_pipe_rand_ready + or mc_int_rd_rsp_pd + ) begin + `ifdef SYNTHESIS + p3_pipe_rand_valid = mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = p3_pipe_rand_ready; + p3_pipe_rand_data = mc_int_rd_rsp_pd[513:0]; + `else +// VCS coverage off + p3_pipe_rand_valid = (p3_pipe_rand_active)? 1'b0 : mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = (p3_pipe_rand_active)? 1'b0 : p3_pipe_rand_ready; + p3_pipe_rand_data = (p3_pipe_rand_active)? 'bx : mc_int_rd_rsp_pd[513:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p3_pipe_stall_cycles; +integer p3_pipe_stall_probability; +integer p3_pipe_stall_cycles_min; +integer p3_pipe_stall_cycles_max; +initial begin + p3_pipe_stall_cycles = 0; + p3_pipe_stall_probability = 0; + p3_pipe_stall_cycles_min = 1; + p3_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_probability" ) ) p3_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_min" ) ) p3_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_wg_pipe_stall_cycles_max" ) ) p3_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p3_pipe_rand_enable; +reg p3_pipe_rand_poised; +always @( + p3_pipe_stall_cycles + or p3_pipe_stall_probability + or mc_int_rd_rsp_valid + ) begin + p3_pipe_rand_active = p3_pipe_stall_cycles != 0; + p3_pipe_rand_enable = p3_pipe_stall_probability != 0; + p3_pipe_rand_poised = p3_pipe_rand_enable && !p3_pipe_rand_active && mc_int_rd_rsp_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_stall_cycles <= 1'b0; + end else begin + if (p3_pipe_rand_poised) begin + if (p3_pipe_stall_probability >= prand_inst0(1, 100)) begin + p3_pipe_stall_cycles <= prand_inst1(p3_pipe_stall_cycles_min, p3_pipe_stall_cycles_max); + end + end else if (p3_pipe_rand_active) begin + p3_pipe_stall_cycles <= p3_pipe_stall_cycles - 1; + end else begin + p3_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_pipe_rand_valid)? p3_pipe_rand_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_pipe_rand_ready = p3_pipe_ready_bc; +end +//## pipe (3) skid buffer +always @( + p3_pipe_valid + or p3_skid_ready_flop + or p3_pipe_skid_ready + or p3_skid_valid + ) begin + p3_skid_catch = p3_pipe_valid && p3_skid_ready_flop && !p3_pipe_skid_ready; + p3_skid_ready = (p3_skid_valid)? p3_pipe_skid_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + p3_pipe_ready <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_pipe_skid_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + p3_pipe_ready <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or p3_pipe_valid + or p3_skid_valid + or p3_pipe_data + or p3_skid_data + ) begin + p3_pipe_skid_valid = (p3_skid_ready_flop)? p3_pipe_valid : p3_skid_valid; +// VCS sop_coverage_off start + p3_pipe_skid_data = (p3_skid_ready_flop)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) output +always @( + p3_pipe_skid_valid + or dma_rd_rsp_rdy + or p3_pipe_skid_data + ) begin + mc_dma_rd_rsp_vld = p3_pipe_skid_valid; + p3_pipe_skid_ready = dma_rd_rsp_rdy; + mc_dma_rd_rsp_pd = p3_pipe_skid_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_140x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_dma_rd_rsp_vld^dma_rd_rsp_rdy^mc_int_rd_rsp_valid^mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_141x (nvdla_core_clk, `ASSERT_RESET, (mc_int_rd_rsp_valid && !mc_int_rd_rsp_ready), (mc_int_rd_rsp_valid), (mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDMA_WG_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cv_dma_rd_rsp_pd (cv_dma_rd_rsp_vld,dma_rd_rsp_rdy) <= cv_int_rd_rsp_pd[513:0] (cv_int_rd_rsp_valid,cv_int_rd_rsp_ready) +// ************************************************************************************************************** diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v new file mode 100644 index 0000000..d522ec4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v @@ -0,0 +1,2992 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_wt.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_wt ( + nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,cdma_wt2mcif_rd_req_ready //|< i + ,mcif2cdma_wt_rd_rsp_pd //|< i + ,mcif2cdma_wt_rd_rsp_valid //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_arb_weight //|< i + ,reg2dp_arb_wmb //|< i + ,reg2dp_byte_per_kernel //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_nan_to_zero //|< i + ,reg2dp_op_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_skip_weight_rls //|< i + ,reg2dp_weight_addr_high //|< i + ,reg2dp_weight_addr_low //|< i + ,reg2dp_weight_bank //|< i + ,reg2dp_weight_bytes //|< i + ,reg2dp_weight_format //|< i + ,reg2dp_weight_kernel //|< i + ,reg2dp_weight_ram_type //|< i + ,reg2dp_weight_reuse //|< i + ,reg2dp_wgs_addr_high //|< i + ,reg2dp_wgs_addr_low //|< i + ,reg2dp_wmb_addr_high //|< i + ,reg2dp_wmb_addr_low //|< i + ,reg2dp_wmb_bytes //|< i + ,sc2cdma_wmb_entries //|< i + ,sc2cdma_wt_entries //|< i + ,sc2cdma_wt_kernels //|< i * + ,sc2cdma_wt_pending_req //|< i + ,sc2cdma_wt_updt //|< i + ,status2dma_fsm_switch //|< i + ,cdma2buf_wt_wr_en //|> o +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,cdma2buf_wt_wr_sel +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_wt_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_wt_wr_addr${i} +//: ,cdma2buf_wt_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,cdma2buf_wt_wr_addr +,cdma2buf_wt_wr_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,cdma2buf_wt_wr_addr //|> o +//,cdma2buf_wt_wr_data //|> o +//,cdma2buf_wt_wr_hsel //|> o + ,cdma2sc_wmb_entries //|> o + ,cdma2sc_wt_entries //|> o + ,cdma2sc_wt_kernels //|> o + ,cdma2sc_wt_pending_ack //|> o + ,cdma2sc_wt_updt //|> o + ,cdma_wt2mcif_rd_req_pd //|> o + ,cdma_wt2mcif_rd_req_valid //|> o + ,dp2reg_inf_weight_num //|> o + ,dp2reg_nan_weight_num //|> o + ,dp2reg_wt_flush_done //|> o + ,dp2reg_wt_rd_latency //|> o + ,dp2reg_wt_rd_stall //|> o + ,mcif2cdma_wt_rd_rsp_ready //|> o + ,wt2status_state //|> o + ); +///////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output cdma_wt2mcif_rd_req_valid; +input cdma_wt2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] cdma_wt2mcif_rd_req_pd; +input mcif2cdma_wt_rd_rsp_valid; +output mcif2cdma_wt_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2cdma_wt_rd_rsp_pd; +output cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_sel ; +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] cdma2buf_wt_wr_addr; +output [64-1:0] cdma2buf_wt_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input status2dma_fsm_switch; +output [1:0] wt2status_state; +output cdma2sc_wt_updt; +output [13:0] cdma2sc_wt_kernels; +output [14:0] cdma2sc_wt_entries; +output [11:0] cdma2sc_wmb_entries; +input sc2cdma_wt_updt; +input [13:0] sc2cdma_wt_kernels; +input [14:0] sc2cdma_wt_entries; +input [8:0] sc2cdma_wmb_entries; +input sc2cdma_wt_pending_req; +output cdma2sc_wt_pending_ack; +input nvdla_core_ng_clk; +input [3:0] reg2dp_arb_weight; +input [3:0] reg2dp_arb_wmb; +input [0:0] reg2dp_op_en; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_weight_reuse; +input [0:0] reg2dp_skip_weight_rls; +input [0:0] reg2dp_weight_format; +input [17:0] reg2dp_byte_per_kernel; +input [12:0] reg2dp_weight_kernel; +input [0:0] reg2dp_weight_ram_type; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: input [31-${atmbw}:0] reg2dp_weight_addr_low; +//: input [31-${atmbw}:0] reg2dp_wgs_addr_low; +//: input [31-${atmbw}:0] reg2dp_wmb_addr_low; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [31-3:0] reg2dp_weight_addr_low; +input [31-3:0] reg2dp_wgs_addr_low; +input [31-3:0] reg2dp_wmb_addr_low; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [31:0] reg2dp_weight_addr_high; +input [31:0] reg2dp_weight_bytes; +input [31:0] reg2dp_wgs_addr_high; +input [31:0] reg2dp_wmb_addr_high; +input [27:0] reg2dp_wmb_bytes; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_weight_bank; +input [0:0] reg2dp_nan_to_zero; +input [0:0] reg2dp_dma_en; +output [31:0] dp2reg_nan_weight_num; +output [31:0] dp2reg_inf_weight_num; +output dp2reg_wt_flush_done; +output [31:0] dp2reg_wt_rd_stall; +output [31:0] dp2reg_wt_rd_latency; +///////////////////////////////////////////////////// +reg [18:0] byte_per_kernel; +reg [16:0] cdma2buf_wt_wr_addr; +reg cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: my $s = int($atmc/$dmaif); +//: print qq( +//: reg [${s}-1:0] cdma2buf_wt_wr_sel ; +//: wire [${k}-1:0] cdma2buf_wt_wr_sel_w; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//reg cdma2buf_wt_wr_sel; +reg [1:0] cur_state; +reg [1:0] dbg_dma_req_src_b0; +reg [1:0] dbg_dma_req_src_b1; +reg dbg_src_rd_ptr; +reg dbg_src_wr_ptr; +reg [31:0] dbg_wmb_kernel_bits; +reg [31:0] dbg_wt_kernel_bytes; +wire [3:0] dma_req_size; +wire [2:0] dma_req_size_out; +//: my $mask = (64/8/8); +//: my $atmm = (8 * 8); +//: print qq( +//: wire [${atmm}-1:0] wt_local_data_w; +//: reg [${atmm}-1:0] wt_local_data; +//: wire [${atmm}-1:0] wmb_local_data_w; +//: reg [${atmm}-1:0] wmb_local_data; +//: reg [${atmm}-1:0] wgs_local_data; +//: ); +//: foreach my $i(0..$mask-1) { +//: print qq( +//: wire [${atmm}-1:0] dma_rsp_data_p${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [64-1:0] wt_local_data_w; +reg [64-1:0] wt_local_data; +wire [64-1:0] wmb_local_data_w; +reg [64-1:0] wmb_local_data; +reg [64-1:0] wgs_local_data; + +wire [64-1:0] dma_rsp_data_p0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [64 -1:0] wt_cbuf_wr_data_ori_w; +wire [64 -1:0] wt_cbuf_wr_data_w; +reg [64 -1:0] cdma2buf_wt_wr_data; +wire [64 -1:0] wmb_cbuf_wr_data_w; +wire [64 -1:0] cdma2buf_wt_wr_data_w; +wire [3:0] dma_rsp_size; +reg [3:0] dma_rsp_size_cnt; +wire [31:0] dp2reg_wt_rd_latency=32'd0; +reg [31:0] dp2reg_wt_rd_stall; +reg [11:0] group; +reg [14:0] incr_wt_entries; +reg [5:0] incr_wt_kernels; +reg incr_wt_updt; +reg [4:0] last_data_bank; +reg last_skip_weight_rls; +reg [4:0] last_weight_bank; +reg layer_st_d1; +reg ltc_1_adv; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg [8:0] ltc_1_cnt_cur; +wire ltc_1_dec; +wire ltc_1_inc; +reg ltc_2_adv; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg ltc_2_dec; +reg ltc_2_inc; +reg [31:0] ltc_2_cnt_cur; +reg nan_pass; +reg [1:0] nxt_state; +reg [8:0] outs_dp2reg_wt_rd_latency; +reg pending_ack; +reg pending_req; +reg pending_req_d1; +reg [25:0] pre_wt_fetched_cnt; +reg [31:0] pre_wt_required_bytes; +reg required_valid; +reg [14:0] sc_wt_entries; +reg sc_wt_updt; +reg status_done; +reg [3:0] status_done_cnt; +reg [11:0] status_group_cnt; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [5:0] weight_bank; +reg [6:0] weight_bank_end; +reg [1:0] wt2status_state; +////: my $bank_entry = NVDLA_CBUF_BANK_NUMBER * NVDLA_CBUF_BANK_DEPTH; +////: my $bank_entry_bw = int( log( $bank_entry)/log(2) ); +////: my $dmaif=NVDLA_CDMA_DMAIF_BW; +////: my $atmc=NVDLA_MAC_ATOMIC_C_SIZE*NVDLA_CDMA_BPE; +////: my $k; +////: if($dmaif < $atmc) { +////: $k = int(log(int($atmc/$dmaif))/log(2)); +////: } else { +////: $k = 0; +////: } +////: print qq( +////: reg [${bank_entry_bw}+$k-1:0] wt_cbuf_flush_idx;//max value = half bank entry * 2^$k +////: ); +reg [17:0] wt_cbuf_flush_idx; +reg [16:0] wt_cbuf_wr_idx; +reg [16:0] wt_data_avl; +reg [13:0] wt_data_onfly; +reg [16:0] wt_data_stored; +reg [25:0] wt_fetched_cnt; +reg [31:0] wt_fp16_inf_flag; +reg wt_fp16_inf_vld; +reg [31:0] wt_fp16_nan_flag; +reg wt_fp16_nan_vld; +reg wt_local_data_vld; +reg wt_rd_latency_cen; +reg wt_rd_latency_clr; +reg wt_rd_latency_dec; +reg wt_rd_latency_inc; +reg wt_rd_stall_cen; +reg wt_rd_stall_clr; +reg wt_rd_stall_inc; +reg wt_req_done_d2; +reg wt_req_done_d3; +reg wt_req_last_d2; +reg [3:0] wt_req_size_d1; +reg [3:0] wt_req_size_d2; +reg [3:0] wt_req_size_d3; +reg [2:0] wt_req_size_out_d2; +reg [2:0] wt_req_size_out_d3; +reg wt_req_stage_vld_d1; +reg wt_req_stage_vld_d2; +reg wt_req_vld_d3; +reg [31:0] wt_required_bytes; +wire arb_sp_out_vld; +wire arb_sp_out_rdy; +wire [16:0] cdma2buf_wt_wr_addr_w; +wire cdma2buf_wt_wr_en_w; +//wire cdma2buf_wt_wr_sel_w; +wire clear_all; +wire [5:0] data_bank_w; +wire [1:0] dbg_dma_req_src; +wire dbg_full_weight; +wire dbg_src_rd_ptr_en; +wire dbg_src_rd_ptr_w; +wire dbg_src_wr_ptr_en; +wire dbg_src_wr_ptr_w; +wire [31:0] dbg_wt_kernel_bytes_w; +wire [63:0] dma_rd_req_addr; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [14:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire [64 -1:0] dma_rd_rsp_data; +wire [( 64 + (64/8/8) )-64 -1:0] dma_rd_rsp_mask; +wire [( 64 + (64/8/8) )-1:0] dma_rd_rsp_pd; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [5:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire [1:0] dma_req_src; +wire [5:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire [3:0] dma_rsp_size_cnt_inc; +wire [3:0] dma_rsp_size_cnt_w; +wire [1:0] dma_rsp_src; +wire [31:0] dp2reg_inf_weight_num_inc; +wire [31:0] dp2reg_inf_weight_num_w; +wire [31:0] dp2reg_nan_weight_num_inc; +wire [31:0] dp2reg_nan_weight_num_w; +wire dp2reg_wt_rd_stall_dec; +wire fetch_done; +wire [10:0] group_op; +wire [11:0] group_w; +wire [25:0] incr_wt_cnt; +wire [14:0] incr_wt_entries_d0; +wire [14:0] incr_wt_entries_w; +wire [5:0] incr_wt_kernels_d0; +wire [5:0] incr_wt_kernels_w; +wire incr_wt_updt_d0; +wire inf_carry; +wire inf_reg_en; +wire is_compressed; +wire is_fp16; +wire is_int8; +wire is_nxt_running; +wire is_pending; +wire is_running; +wire layer_end; +wire layer_st; +wire mon_dma_rsp_size_cnt_inc; +wire mon_incr_wt_cnt; +wire mon_wt_cbuf_flush_idx_w; +wire mon_wt_data_avl_w; +wire mon_wt_data_onfly_w; +wire mon_wt_data_stored_w; +wire mon_wt_fetched_cnt_inc; +wire mon_wt_req_burst_cnt_dec; +wire mon_wt_req_sum; +wire mon_wt_required_bytes_w; +wire nan_carry; +wire nan_pass_w; +wire nan_reg_en; +wire need_pending; +wire [23:0] normal_bpg; +wire pending_req_end; +wire [25:0] pre_wt_fetched_cnt_w; +wire [31:0] pre_wt_required_bytes_w; +wire rd_req_rdyi; +wire required_valid_w; +wire [4:0] status_done_cnt_w; +wire status_done_w; +wire [11:0] status_group_cnt_inc; +wire [11:0] status_group_cnt_w; +wire status_last_group; +wire status_update; +wire [6:0] weight_bank_end_w; +wire [5:0] weight_bank_w; +wire [1:0] wt2status_state_w; +wire [17:0] wt_cbuf_flush_idx_w; +wire wt_cbuf_flush_vld_w; +wire [17:0] wt_cbuf_wr_idx_inc; +wire wt_cbuf_wr_idx_set; +wire [16:0] wt_cbuf_wr_idx_w; +wire wt_cbuf_wr_idx_wrap; +wire wt_cbuf_wr_vld_w; +wire [16:0] wt_data_avl_sub; +wire [16:0] wt_data_avl_w; +wire [3:0] wt_data_onfly_add; +wire wt_data_onfly_reg_en; +wire [3:0] wt_data_onfly_sub; +wire [13:0] wt_data_onfly_w; +wire [16:0] wt_data_stored_sub; +wire [16:0] wt_data_stored_w; +wire [25:0] wt_fetched_cnt_inc; +wire [25:0] wt_fetched_cnt_w; +wire [31:0] wt_fp16_exp_flag_w; +wire [31:0] wt_fp16_inf_flag_w; +wire [5:0] wt_fp16_inf_sum; +wire wt_fp16_inf_vld_w; +wire [31:0] wt_fp16_manti_flag_w; +wire [31:0] wt_fp16_nan_flag_w; +wire [5:0] wt_fp16_nan_sum; +wire wt_fp16_nan_vld_w; +//: my $mask = (64/8/8); +//: if($mask == 4) { +//: print qq( +//: wire [2:0] wt_local_data_cnt; +//: ); +//: } else { +//: print qq( +//: wire [1:0] wt_local_data_cnt; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [1:0] wt_local_data_cnt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [2:0] wt_local_data_cnt; +wire wt_local_data_reg_en; +wire wt_local_data_vld_w; +//wire [511:0] wt_nan_mask; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: wire [64-${atmbw}-1:0] wt_req_addr_w; +//: reg [64-${atmbw}-1:0] wt_req_addr_d2; +//: reg [64-${atmbw}-1:0] wt_req_addr_d3; +//: wire [64-${atmbw}-1:0] dma_req_addr; +//: wire [64-${atmbw}-1-3:0] wt_req_addr_inc; +//: wire [64-${atmbw}-1:0] wmb_req_addr_w; +//: reg [64-${atmbw}-1:0] wmb_req_addr_d2; +//: reg [64-${atmbw}-1:0] wmb_req_addr_d3; +//: wire [64-${atmbw}-1-3:0] wmb_req_addr_inc; +//: wire [64-${atmbw}-1:0] wgs_req_addr_w; +//: wire [64-${atmbw}-1:0] wgs_req_addr_inc; +//: reg [64-${atmbw}-1:0] wgs_req_addr_d1; +//: wire [64-${atmbw}-1+9:0] arb_wrr_req_package_in_00; +//: wire [64-${atmbw}-1+9:0] arb_wrr_req_package_in_01; +//: wire [64-${atmbw}-1+9:0] arb_wrr_out_package_w; +//: reg [64-${atmbw}-1+9:0] arb_wrr_out_package; +//: reg [64-${atmbw}-1+9:0] arb_wrr_out_back_package; +//: reg [64-${atmbw}-1+9:0] arb_sp_req_package_in_00; +//: reg [64-${atmbw}-1+9:0] arb_sp_req_package_in_01; +//: ); +//: my $atmm = 8; +//: my $k = int( log(${atmm}) / log(2) ); +//: print qq( +//: wire [32-${k}-1:0] wt_req_burst_cnt_w; +//: reg [32-${k}-1:0] wt_req_burst_cnt_d1; +//: wire [32-${k}-1:0] wt_req_burst_cnt_dec; +//: wire [28-${k}-1:0] wmb_req_burst_cnt_w; +//: wire [28-${k}-1:0] wmb_req_burst_cnt_dec; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [64-3-1:0] wt_req_addr_w; +reg [64-3-1:0] wt_req_addr_d2; +reg [64-3-1:0] wt_req_addr_d3; +wire [64-3-1:0] dma_req_addr; +wire [64-3-1-3:0] wt_req_addr_inc; +wire [64-3-1:0] wmb_req_addr_w; +reg [64-3-1:0] wmb_req_addr_d2; +reg [64-3-1:0] wmb_req_addr_d3; +wire [64-3-1-3:0] wmb_req_addr_inc; +wire [64-3-1:0] wgs_req_addr_w; +wire [64-3-1:0] wgs_req_addr_inc; +reg [64-3-1:0] wgs_req_addr_d1; +wire [64-3-1+9:0] arb_wrr_req_package_in_00; +wire [64-3-1+9:0] arb_wrr_req_package_in_01; +wire [64-3-1+9:0] arb_wrr_out_package_w; +reg [64-3-1+9:0] arb_wrr_out_package; +reg [64-3-1+9:0] arb_wrr_out_back_package; +reg [64-3-1+9:0] arb_sp_req_package_in_00; +reg [64-3-1+9:0] arb_sp_req_package_in_01; + +wire [32-3-1:0] wt_req_burst_cnt_w; +reg [32-3-1:0] wt_req_burst_cnt_d1; +wire [32-3-1:0] wt_req_burst_cnt_dec; +wire [28-3-1:0] wmb_req_burst_cnt_w; +wire [28-3-1:0] wmb_req_burst_cnt_dec; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire wt_req_done_w; +wire wt_req_last_w; +wire wt_req_overflow; +wire wt_req_overflow_d3; +wire wt_req_rdy; +wire wt_req_reg_en; +wire wt_req_reg_en_d0; +wire wt_req_reg_en_d1; +wire wt_req_reg_en_d2; +wire [3:0] wt_req_size_addr_limit; +wire [2:0] wt_req_size_out_w; +wire [3:0] wt_req_size_w; +wire [1:0] wt_req_src_d3; +wire [16:0] wt_req_sum; +wire wt_req_vld_w; +wire [31:0] wt_required_bytes_w; +wire wt_required_en; +wire wt_rsp_valid; +wire wt_satisfied; +wire [31:0] dp2reg_nan_weight_num; +wire [31:0] dp2reg_inf_weight_num; +//////////////////////////////////////////////////////////////////////// +// CDMA weight fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +//## fsm (1) defines +localparam WT_STATE_IDLE = 2'b00; +localparam WT_STATE_PEND = 2'b01; +localparam WT_STATE_BUSY = 2'b10; +localparam WT_STATE_DONE = 2'b11; +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + WT_STATE_IDLE: begin + if ((reg2dp_op_en & need_pending)) begin + nxt_state = WT_STATE_PEND; + end + else if ((reg2dp_op_en & reg2dp_weight_reuse & last_skip_weight_rls)) begin + nxt_state = WT_STATE_DONE; + end + else if (reg2dp_op_en) begin + nxt_state = WT_STATE_BUSY; + end + end + WT_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = WT_STATE_BUSY; + end + end + WT_STATE_BUSY: begin + if (fetch_done) begin + nxt_state = WT_STATE_DONE; + end + end + WT_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = WT_STATE_IDLE; + end + end + endcase + end +end +//: &eperl::flop("-nodeclare -rval \"WT_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_state <= WT_STATE_IDLE; + end else begin + cur_state <= nxt_state; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign status_done_cnt_w[4:0] = layer_st ? 5'b0 : + (status_done & (status_done_cnt != 4'h8)) ? (status_done_cnt + 4'b1) : status_done_cnt; +assign fetch_done = status_done & (status_done_cnt == 4'h8); +assign need_pending = ((last_data_bank != reg2dp_data_bank) | (last_weight_bank != reg2dp_weight_bank)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_done_cnt <= {4{1'b0}}; + end else begin + if ((layer_st | is_running) == 1'b1) begin + status_done_cnt <= status_done_cnt_w[3:0]; + end + end +end +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en && (cur_state == WT_STATE_IDLE); +assign layer_end = status2dma_fsm_switch; +assign is_running = (cur_state == WT_STATE_BUSY); +assign is_pending = (cur_state == WT_STATE_PEND); +assign clear_all = pending_ack & pending_req; +assign is_nxt_running = (nxt_state == WT_STATE_BUSY); +assign wt2status_state_w = (nxt_state == WT_STATE_PEND) ? 1 : + (nxt_state == WT_STATE_BUSY) ? 2 : + (nxt_state == WT_STATE_DONE) ? 3 : + 0 ; +assign pending_req_end = pending_req_d1 & ~pending_req; +//: &eperl::flop("-nodeclare -rval \"0\" -d \"wt2status_state_w\" -q wt2status_state"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2cdma_wt_pending_req\" -q pending_req"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pending_req\" -q pending_req_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_pending\" -q pending_ack"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2status_state <= 'b0; + end else begin + wt2status_state <= wt2status_state_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req <= 1'b0; + end else begin + pending_req <= sc2cdma_wt_pending_req; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_req_d1 <= 1'b0; + end else begin + pending_req_d1 <= pending_req; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pending_ack <= 1'b0; + end else begin + pending_ack <= is_pending; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cdma2sc_wt_pending_ack = pending_ack; +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"layer_end\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"layer_end\" -d \"reg2dp_weight_bank\" -q last_weight_bank"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_end\" -d \"reg2dp_skip_weight_rls\" -q last_skip_weight_rls"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"layer_st\" -q layer_st_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_data_bank <= {5{1'b1}}; + end else begin + if ((layer_end) == 1'b1) begin + last_data_bank <= reg2dp_data_bank; + // VCS coverage off + end else if ((layer_end) == 1'b0) begin + end else begin + last_data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_weight_bank <= {5{1'b1}}; + end else begin + if ((layer_end) == 1'b1) begin + last_weight_bank <= reg2dp_weight_bank; + // VCS coverage off + end else if ((layer_end) == 1'b0) begin + end else begin + last_weight_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_skip_weight_rls <= 1'b0; + end else begin + if ((layer_end) == 1'b1) begin + last_skip_weight_rls <= reg2dp_skip_weight_rls; + // VCS coverage off + end else if ((layer_end) == 1'b0) begin + end else begin + last_skip_weight_rls <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_st_d1 <= 1'b0; + end else begin + layer_st_d1 <= layer_st; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -norst -en \"layer_st\" -d \"reg2dp_byte_per_kernel + 1'b1\" -q byte_per_kernel"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((layer_st) == 1'b1) begin + byte_per_kernel <= reg2dp_byte_per_kernel + 1'b1; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + byte_per_kernel <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign is_int8 = 1'b1; +assign is_fp16 = 1'b0; +//: my $atmk = 8; +//: my $atmkbw = int(log($atmk) / log(2)); +//: print qq( assign group_op = {{($atmkbw-2){1'b0}}, reg2dp_weight_kernel[12:${atmkbw}]}; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign group_op = {{(3-2){1'b0}}, reg2dp_weight_kernel[12:3]}; +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign group_w = group_op + 1'b1; +assign data_bank_w = reg2dp_data_bank + 1'b1; +assign weight_bank_w = reg2dp_weight_bank + 1'b1; +assign weight_bank_end_w = weight_bank_w + data_bank_w; +assign nan_pass_w = ~reg2dp_nan_to_zero | ~is_fp16; +assign is_compressed = 1'b0; +//: &eperl::flop("-nodeclare -rval \"{12{1'b1}}\" -en \"layer_st\" -d \"group_w\" -q group"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b1}}\" -en \"layer_st\" -d \"weight_bank_w\" -q weight_bank"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b1}}\" -en \"layer_st\" -d \"weight_bank_end_w\" -q weight_bank_end"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"layer_st\" -d \"nan_pass_w\" -q nan_pass"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + group <= {12{1'b1}}; + end else begin + if ((layer_st) == 1'b1) begin + group <= group_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + group <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_bank <= {6{1'b1}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_bank <= weight_bank_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_bank_end <= {7{1'b1}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_bank_end <= weight_bank_end_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_bank_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nan_pass <= 1'b1; + end else begin + if ((layer_st) == 1'b1) begin + nan_pass <= nan_pass_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + nan_pass <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// generate address for weight data // +//////////////////////////////////////////////////////////////////////// +localparam SRC_ID_WT = 2'b00; +localparam SRC_ID_WMB = 2'b01; +localparam SRC_ID_WGS = 2'b10; +/////////////////// stage 1 /////////////////// +assign wt_req_reg_en_d0 = wt_req_reg_en; +assign {mon_wt_req_burst_cnt_dec, wt_req_burst_cnt_dec} = wt_req_burst_cnt_d1 - {{25{1'b0}}, wt_req_size_d1}; +//assign wt_req_burst_cnt_w = layer_st ? {reg2dp_weight_bytes, 2'b0} : wt_req_burst_cnt_dec; +//: my $atmm = 8; +//: my $k = int( log(${atmm}) / log(2) ); +//: print qq( assign wt_req_burst_cnt_w = layer_st ? reg2dp_weight_bytes[31:${k}] : wt_req_burst_cnt_dec; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign wt_req_burst_cnt_w = layer_st ? reg2dp_weight_bytes[31:3] : wt_req_burst_cnt_dec; +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wt_req_size_addr_limit = layer_st ? (4'h8 - reg2dp_weight_addr_low[2:0]) : 4'h8; +assign wt_req_size_w = ( {{25{1'b0}}, wt_req_size_addr_limit} > wt_req_burst_cnt_w) ? wt_req_burst_cnt_w[3:0] : wt_req_size_addr_limit; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"wt_req_reg_en_d0\" -d \"wt_req_size_w\" -q wt_req_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{29{1'b0}}\" -en \"wt_req_reg_en_d0\" -d \"wt_req_burst_cnt_w\" -q wt_req_burst_cnt_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_nxt_running\" -q wt_req_stage_vld_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_size_d1 <= {4{1'b0}}; + end else begin + if ((wt_req_reg_en_d0) == 1'b1) begin + wt_req_size_d1 <= wt_req_size_w; + // VCS coverage off + end else if ((wt_req_reg_en_d0) == 1'b0) begin + end else begin + wt_req_size_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_burst_cnt_d1 <= {29{1'b0}}; + end else begin + if ((wt_req_reg_en_d0) == 1'b1) begin + wt_req_burst_cnt_d1 <= wt_req_burst_cnt_w; + // VCS coverage off + end else if ((wt_req_reg_en_d0) == 1'b0) begin + end else begin + wt_req_burst_cnt_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_stage_vld_d1 <= 1'b0; + end else begin + wt_req_stage_vld_d1 <= is_nxt_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////// stage 2 /////////////////// +assign wt_req_reg_en_d1 = wt_req_reg_en; +assign wt_req_last_w = wt_req_stage_vld_d1 && (wt_req_burst_cnt_d1 == {{25{1'b0}}, wt_req_size_d1}); +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: assign wt_req_addr_inc = wt_req_addr_d2[64-${atmbw}-1:3] + 1'b1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign wt_req_addr_inc = wt_req_addr_d2[64-3-1:3] + 1'b1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wt_req_addr_w = (~wt_req_stage_vld_d2) ? {reg2dp_weight_addr_high,reg2dp_weight_addr_low} : {wt_req_addr_inc, 3'b0}; +assign wt_req_size_out_w = wt_req_size_d1[2:0] - 3'b1; +assign wt_req_done_w = layer_st ? 1'b0 : wt_req_last_d2 ? 1'b1 : wt_req_done_d2; +//: &eperl::flop("-nodeclare -rval \"0\" -en \"wt_req_reg_en_d1\" -d \"wt_req_addr_w\" -q wt_req_addr_d2"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"wt_req_reg_en_d1\" -d \"wt_req_size_d1\" -q wt_req_size_d2"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"wt_req_reg_en_d1\" -d \"wt_req_size_out_w\" -q wt_req_size_out_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_reg_en_d1\" -d \"wt_req_last_w\" -q wt_req_last_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"wt_req_reg_en_d1\" -d \"wt_req_done_w\" -q wt_req_done_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_stage_vld_d1 & is_nxt_running\" -q wt_req_stage_vld_d2"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_addr_d2 <= 'b0; + end else begin + if ((wt_req_reg_en_d1) == 1'b1) begin + wt_req_addr_d2 <= wt_req_addr_w; + // VCS coverage off + end else if ((wt_req_reg_en_d1) == 1'b0) begin + end else begin + wt_req_addr_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_size_d2 <= {4{1'b0}}; + end else begin + if ((wt_req_reg_en_d1) == 1'b1) begin + wt_req_size_d2 <= wt_req_size_d1; + // VCS coverage off + end else if ((wt_req_reg_en_d1) == 1'b0) begin + end else begin + wt_req_size_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_size_out_d2 <= {3{1'b0}}; + end else begin + if ((wt_req_reg_en_d1) == 1'b1) begin + wt_req_size_out_d2 <= wt_req_size_out_w; + // VCS coverage off + end else if ((wt_req_reg_en_d1) == 1'b0) begin + end else begin + wt_req_size_out_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_last_d2 <= 1'b0; + end else begin + if ((wt_req_reg_en_d1) == 1'b1) begin + wt_req_last_d2 <= wt_req_last_w; + // VCS coverage off + end else if ((wt_req_reg_en_d1) == 1'b0) begin + end else begin + wt_req_last_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_done_d2 <= 1'b1; + end else begin + if ((wt_req_reg_en_d1) == 1'b1) begin + wt_req_done_d2 <= wt_req_done_w; + // VCS coverage off + end else if ((wt_req_reg_en_d1) == 1'b0) begin + end else begin + wt_req_done_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_stage_vld_d2 <= 1'b0; + end else begin + wt_req_stage_vld_d2 <= wt_req_stage_vld_d1 & is_nxt_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////// stage 3 /////////////////// +assign wt_req_reg_en_d2 = wt_req_reg_en; +assign wt_req_vld_w = is_nxt_running & wt_req_stage_vld_d2; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_vld_w\" -q wt_req_vld_d3"); +//: &eperl::flop("-nodeclare -rval \"0\" -en \"wt_req_reg_en_d2\" -d \"wt_req_addr_d2\" -q wt_req_addr_d3"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"wt_req_reg_en_d2\" -d \"wt_req_size_d2\" -q wt_req_size_d3"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"wt_req_reg_en_d2\" -d \"wt_req_size_out_d2\" -q wt_req_size_out_d3"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"wt_req_reg_en_d2\" -d \"(is_running & wt_req_done_d2)\" -q wt_req_done_d3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_vld_d3 <= 1'b0; + end else begin + wt_req_vld_d3 <= wt_req_vld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_addr_d3 <= 'b0; + end else begin + if ((wt_req_reg_en_d2) == 1'b1) begin + wt_req_addr_d3 <= wt_req_addr_d2; + // VCS coverage off + end else if ((wt_req_reg_en_d2) == 1'b0) begin + end else begin + wt_req_addr_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_size_d3 <= {4{1'b0}}; + end else begin + if ((wt_req_reg_en_d2) == 1'b1) begin + wt_req_size_d3 <= wt_req_size_d2; + // VCS coverage off + end else if ((wt_req_reg_en_d2) == 1'b0) begin + end else begin + wt_req_size_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_size_out_d3 <= {3{1'b0}}; + end else begin + if ((wt_req_reg_en_d2) == 1'b1) begin + wt_req_size_out_d3 <= wt_req_size_out_d2; + // VCS coverage off + end else if ((wt_req_reg_en_d2) == 1'b0) begin + end else begin + wt_req_size_out_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_done_d3 <= 1'b1; + end else begin + if ((wt_req_reg_en_d2) == 1'b1) begin + wt_req_done_d3 <= (is_running & wt_req_done_d2); + // VCS coverage off + end else if ((wt_req_reg_en_d2) == 1'b0) begin + end else begin + wt_req_done_d3 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wt_req_src_d3 = SRC_ID_WT; +/////////////////// overflow control logic /////////////////// +assign {mon_wt_req_sum, wt_req_sum} = wt_data_onfly + wt_data_stored + wt_data_avl; +//: my $atmm8 = ((8*8)/8); +//: my $Cbuf_bank_size = 8 * 512; +//: my $cdma_addr_align = 8; +//: my $Cbuf_bank_fetch_bits = int( log($Cbuf_bank_size/$cdma_addr_align)/log(2) ); +//: print qq( +//: assign wt_req_overflow = is_running && (wt_req_sum > ({weight_bank, ${Cbuf_bank_fetch_bits}'b0} + $atmm8)); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign wt_req_overflow = is_running && (wt_req_sum > ({weight_bank, 9'b0} + 8)); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wt_req_overflow_d3 = wt_req_overflow; +/////////////////// pipeline control logic /////////////////// +assign wt_req_reg_en = layer_st | (is_running & (~wt_req_vld_d3 | wt_req_rdy)); +assign arb_sp_out_rdy = dma_rd_req_rdy & dma_req_fifo_ready; +assign arb_sp_out_vld = wt_req_vld_d3 & ~wt_req_overflow_d3 & ~wt_req_done_d3; +//assign wt_req_rdy = arb_sp_out_rdy; +assign wt_req_rdy = arb_sp_out_rdy & arb_sp_out_vld; +assign dma_req_src = wt_req_src_d3; +assign dma_req_size = wt_req_size_d3; +assign dma_req_size_out = wt_req_size_out_d3; +assign dma_req_addr = wt_req_addr_d3; +//////////////////////////////////////////////////////////////////////// +// CDMA WT read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_weight_ram_type) + ,.mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid ) + ,.mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready ) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +wire dmaif_rd_rsp_prdy; +wire dmaif_rd_rsp_pvld; +wire [( 64 + (64/8/8) )-1:0] dmaif_rd_rsp_pd; +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready ) +//,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) +//,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) +//,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) + ,.dmaif_rd_rsp_pd (dmaif_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dmaif_rd_rsp_pvld ) + ,.dmaif_rd_rsp_prdy (dmaif_rd_rsp_prdy ) +); +/////////////////////////////////////////// +//DorisLei: adding a 8*atmm fifo here for data buffering. +//use case: Cbuf has empty entries, but empty entry number < 8*atmm +//continue reading 8*atmm data from memory and then Cbuf can be fully written +//: my $dmaif = 64; +//: my $atmm8 = 8 * (8 * 8); +//: my $fifo_depth = int( $atmm8/$dmaif ); +//: my $fifo_width = $dmaif; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// +NV_NVDLA_CDMA_WT_8ATMM_fifo u_8atmm_fifo( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.atmm8_wr_prdy (dmaif_rd_rsp_prdy) + ,.atmm8_wr_pvld (dmaif_rd_rsp_pvld) + ,.atmm8_wr_pd (dmaif_rd_rsp_pd) + ,.atmm8_rd_prdy (dma_rd_rsp_rdy ) + ,.atmm8_rd_pvld (dma_rd_rsp_vld ) + ,.atmm8_rd_pd (dma_rd_rsp_pd ) + ,.pwrbus_ram_pd (32'd0) + ); +/////////////////////////////////////////// +assign dma_rd_req_pd[32 -1:0] = dma_rd_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_rd_req_size[14:0]; +assign dma_rd_req_vld = arb_sp_out_vld & dma_req_fifo_ready; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: assign dma_rd_req_addr = {dma_req_addr, ${atmbw}'b0}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dma_rd_req_addr = {dma_req_addr, 3'b0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rd_req_size = {{12{1'b0}}, dma_req_size_out}; +assign dma_rd_req_type = reg2dp_weight_ram_type; +// assign dma_rd_rsp_rdy = 1'b1; +/////////////////////////////////// +//DorisLei redefine dma_rd_rsp_rdy to block reading process when cbuf is full +/////////////////////////////////// +//: my $atmc=8; +//: my $dmaif=64 / 8; +//: if($dmaif < $atmc) { +//: my $k = $atmc/$dmaif - 1; +//: print qq( +//: reg [3:0] dmaif_within_atmc_cnt; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: dmaif_within_atmc_cnt <= 4'd0; +//: else if(wt_cbuf_wr_vld_w) begin +//: if(dmaif_within_atmc_cnt == ${k}) +//: dmaif_within_atmc_cnt <= 4'd0; +//: else +//: dmaif_within_atmc_cnt <= dmaif_within_atmc_cnt + 1'b1; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [16:0] wt_wr_dmatx_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_wr_dmatx_cnt <= 17'd0; + end else if(wt_cbuf_wr_vld_w & (!sc_wt_updt)) begin +//: my $atmc=8; +//: my $dmaif=64 / 8; +//: if($dmaif = $atmc) { +//: print qq( +//: wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1; +//: ); +//: } elsif($dmaif < $atmc) { +//: my $k = $atmc/$dmaif - 1; +//: print qq( +//: if(dmaif_within_atmc_cnt == ${k}) begin +//: wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1; +//: end +//: ); +//: } elsif($dmaif > $atmc) { +//: my $m = $dmaif/$atmc; +//: print qq( +//: wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + ${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else if(!wt_cbuf_wr_vld_w & sc_wt_updt) begin + wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt - sc_wt_entries; + end else if(wt_cbuf_wr_vld_w & sc_wt_updt) begin + wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1 - sc_wt_entries; + end +end +//: my $bank_depth = int( log(512)/log(2) ); +//: print qq( +//: assign dma_rd_rsp_rdy = wt_wr_dmatx_cnt < {weight_bank, ${bank_depth}'b0}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dma_rd_rsp_rdy = wt_wr_dmatx_cnt < {weight_bank, 9'b0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_CDMA_WT_fifo u_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[5:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w * + ,.rd_data (dma_rsp_fifo_data[5:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = arb_sp_out_vld & dma_rd_req_rdy; +assign dma_req_fifo_data = {dma_req_src, dma_req_size}; +//////////////////////////////////////////////////////////////////////// +// For verification/debug // +//////////////////////////////////////////////////////////////////////// +assign dbg_src_rd_ptr_en = (cdma_wt2mcif_rd_req_valid & cdma_wt2mcif_rd_req_ready); +assign dbg_src_rd_ptr_w = ~layer_st & (dbg_src_rd_ptr ^ dbg_src_rd_ptr_en); +assign dbg_src_wr_ptr_en = (dma_rd_req_vld & dma_req_fifo_ready & dma_rd_req_rdy); +assign dbg_src_wr_ptr_w = ~layer_st & (dbg_src_wr_ptr ^ dbg_src_wr_ptr_en); +assign dbg_dma_req_src = dbg_src_rd_ptr ? dbg_dma_req_src_b1 : dbg_dma_req_src_b0; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dbg_src_rd_ptr_w\" -q dbg_src_rd_ptr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dbg_src_wr_ptr_w\" -q dbg_src_wr_ptr"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dbg_src_wr_ptr_en & ~dbg_src_wr_ptr\" -d \"dma_req_src\" -q dbg_dma_req_src_b0"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dbg_src_wr_ptr_en & dbg_src_wr_ptr\" -d \"dma_req_src\" -q dbg_dma_req_src_b1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_src_rd_ptr <= 1'b0; + end else begin + dbg_src_rd_ptr <= dbg_src_rd_ptr_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_src_wr_ptr <= 1'b0; + end else begin + dbg_src_wr_ptr <= dbg_src_wr_ptr_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_dma_req_src_b0 <= {2{1'b0}}; + end else begin + if ((dbg_src_wr_ptr_en & ~dbg_src_wr_ptr) == 1'b1) begin + dbg_dma_req_src_b0 <= dma_req_src; + // VCS coverage off + end else if ((dbg_src_wr_ptr_en & ~dbg_src_wr_ptr) == 1'b0) begin + end else begin + dbg_dma_req_src_b0 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_dma_req_src_b1 <= {2{1'b0}}; + end else begin + if ((dbg_src_wr_ptr_en & dbg_src_wr_ptr) == 1'b1) begin + dbg_dma_req_src_b1 <= dma_req_src; + // VCS coverage off + end else if ((dbg_src_wr_ptr_en & dbg_src_wr_ptr) == 1'b0) begin + end else begin + dbg_dma_req_src_b1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// CDMA read response connection // +//////////////////////////////////////////////////////////////////////// +assign dma_rd_rsp_data[64 -1:0] = dma_rd_rsp_pd[64 -1:0]; +assign dma_rd_rsp_mask[( 64 + (64/8/8) )-64 -1:0] = dma_rd_rsp_pd[( 64 + (64/8/8) )-1:64]; +assign {dma_rsp_src, dma_rsp_size} = dma_rsp_fifo_data; +assign {mon_dma_rsp_size_cnt_inc, dma_rsp_size_cnt_inc} = dma_rsp_size_cnt +//: my $mask = (64/8/8); +//: foreach my $i(0..$mask-1) { +//: print qq( +//: + dma_rd_rsp_mask[$i] +//: ); +//: } +//: print qq( ; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + ++ dma_rd_rsp_mask[0] + ; +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 4'b0 : dma_rsp_size_cnt_inc; +assign dma_rsp_fifo_ready = (dma_rd_rsp_vld & dma_rd_rsp_rdy & (dma_rsp_size_cnt_inc == dma_rsp_size)); +assign wt_rsp_valid = (dma_rd_rsp_vld & dma_rd_rsp_rdy & (dma_rsp_src == SRC_ID_WT)); +assign { +//: my $mask = (64/8/8); +//: if($mask > 1) { +//: foreach my $i(0..$mask-2) { +//: my $j = $mask -$i -1; +//: print qq( dma_rsp_data_p${j} , ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + dma_rsp_data_p0} = dma_rd_rsp_data; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"dma_rd_rsp_vld & dma_rd_rsp_rdy\" -d \"dma_rsp_size_cnt_w\" -q dma_rsp_size_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rsp_size_cnt <= {4{1'b0}}; + end else begin + if ((dma_rd_rsp_vld & dma_rd_rsp_rdy) == 1'b1) begin + dma_rsp_size_cnt <= dma_rsp_size_cnt_w; + // VCS coverage off + end else if ((dma_rd_rsp_vld & dma_rd_rsp_rdy) == 1'b0) begin + end else begin + dma_rsp_size_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WT read data // +//////////////////////////////////////////////////////////////////////// +assign wt_local_data_cnt = wt_local_data_vld +//: my $mask = (64/8/8); +//: foreach my $i(0..$mask-1) { +//: print qq( +//: + dma_rd_rsp_mask[$i] +//: ); +//: } +//: print qq( ; ); +//: my $mask = (64/8/8); +//: if($mask == 1) { +//: print qq( +//: assign wt_local_data_vld_w = 1'b0; +//: assign wt_local_data_reg_en = 1'b0; +//: assign wt_cbuf_wr_vld_w = wt_rsp_valid; +//: assign wt_local_data_w = 0;// bw +//: assign wt_cbuf_wr_data_ori_w = dma_rsp_data_p0; +//: ); +//: } elsif($mask == 2) { +//: print qq( +//: assign wt_local_data_vld_w = wt_local_data_cnt[0]; +//: assign wt_local_data_reg_en = wt_rsp_valid & wt_local_data_cnt[0]; +//: assign wt_cbuf_wr_vld_w = wt_rsp_valid & wt_local_data_cnt[1]; +//: assign wt_local_data_w = dma_rd_rsp_mask[1] ? dma_rsp_data_p1 : dma_rsp_data_p0; +//: assign wt_cbuf_wr_data_ori_w = wt_local_data_vld ? {dma_rsp_data_p0, wt_local_data} : dma_rd_rsp_data; +//: ); +//: } elsif($mask == 4) { +//: print qq( +//: assign wt_local_data_vld_w = |wt_local_data_cnt[1:0]; +//: assign wt_local_data_reg_en = wt_rsp_valid & wt_local_data_vld_w; +//: assign wt_cbuf_wr_vld_w = wt_rsp_valid & wt_local_data_cnt[2]; +//: assign wt_local_data_w = dma_rd_rsp_mask[3] ? dma_rd_rsp_data :// +//: dma_rd_rsp_mask[2] ? {dma_rsp_data_p2, dma_rsp_data_p1, dma_rsp_data_p0}: +//: dma_rd_rsp_mask[1] ? {dma_rsp_data_p1, dma_rsp_data_p0} : dma_rsp_data_p0; +//: assign wt_cbuf_wr_data_ori_w = wt_local_data_vld ? {dma_rsp_data_p0, wt_local_data} : dma_rd_rsp_data;// +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ++ dma_rd_rsp_mask[0] + ; +assign wt_local_data_vld_w = 1'b0; +assign wt_local_data_reg_en = 1'b0; +assign wt_cbuf_wr_vld_w = wt_rsp_valid; +assign wt_local_data_w = 0;// bw +assign wt_cbuf_wr_data_ori_w = dma_rsp_data_p0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wt_cbuf_wr_idx_inc = wt_cbuf_wr_idx + 1'b1; +assign wt_cbuf_wr_idx_set = (layer_st & ~(|wt_cbuf_wr_idx)); +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $k; +//: if($dmaif < $atmc) { +//: $k = int(log(int($atmc/$dmaif))/log(2)); +//: } else { +//: $k = 0; +//: } +//: +//: my $bank_depth_bits = int( log(512)/log(2) + ${k}); +//: print qq( +//: assign wt_cbuf_wr_idx_wrap = (wt_cbuf_wr_idx_inc == {2'd0, weight_bank_end, ${bank_depth_bits}'b0}); +//: assign wt_cbuf_wr_idx_w = (clear_all | wt_cbuf_wr_idx_set | wt_cbuf_wr_idx_wrap) ? {2'd0, data_bank_w, ${bank_depth_bits}'b0} : wt_cbuf_wr_idx_inc[(1 + 16 ) -1:0]; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign wt_cbuf_wr_idx_wrap = (wt_cbuf_wr_idx_inc == {2'd0, weight_bank_end, 9'b0}); +assign wt_cbuf_wr_idx_w = (clear_all | wt_cbuf_wr_idx_set | wt_cbuf_wr_idx_wrap) ? {2'd0, data_bank_w, 9'b0} : wt_cbuf_wr_idx_inc[(1 + 16 ) -1:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign wt_cbuf_wr_data_w = nan_pass ? wt_cbuf_wr_data_ori_w : (wt_cbuf_wr_data_ori_w & wt_nan_mask); +assign wt_cbuf_wr_data_w = wt_cbuf_wr_data_ori_w; +//: &eperl::flop("-nodeclare -norst -en \"wt_local_data_reg_en\" -d \"wt_local_data_w\" -q wt_local_data"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_rsp_valid\" -d \"wt_local_data_vld_w\" -q wt_local_data_vld"); +//: &eperl::flop("-nodeclare -rval \"{17{1'b0}}\" -en \"wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w\" -d \"wt_cbuf_wr_idx_w\" -q wt_cbuf_wr_idx"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((wt_local_data_reg_en) == 1'b1) begin + wt_local_data <= wt_local_data_w; + // VCS coverage off + end else if ((wt_local_data_reg_en) == 1'b0) begin + end else begin + wt_local_data <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_local_data_vld <= 1'b0; + end else begin + if ((wt_rsp_valid) == 1'b1) begin + wt_local_data_vld <= wt_local_data_vld_w; + // VCS coverage off + end else if ((wt_rsp_valid) == 1'b0) begin + end else begin + wt_local_data_vld <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_cbuf_wr_idx <= {17{1'b0}}; + end else begin + if ((wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w) == 1'b1) begin + wt_cbuf_wr_idx <= wt_cbuf_wr_idx_w; + // VCS coverage off + end else if ((wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w) == 1'b0) begin + end else begin + wt_cbuf_wr_idx <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// weight buffer flushing logic // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// Non-SLCG clock domain // +//////////////////////////////////////////////////////////////////////// +assign {mon_wt_cbuf_flush_idx_w, wt_cbuf_flush_idx_w} = wt_cbuf_flush_idx + 1'b1; +//: my $bank_entry = 32 * 512; +//: my $bank_entry_bw = int( log( $bank_entry)/log(2) ); +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $k; +//: if($dmaif < $atmc) { +//: $k = int(log(int($atmc/$dmaif))/log(2)); +//: } else { +//: $k = 0; +//: } +//: print qq( +//: assign wt_cbuf_flush_vld_w = ~wt_cbuf_flush_idx[${bank_entry_bw}+$k-1];//max value = half bank entry * 2^$k +//: assign dp2reg_wt_flush_done = wt_cbuf_flush_idx[${bank_entry_bw}+$k-1]; +//: ); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{18{1'b0}}\" -en \"wt_cbuf_flush_vld_w\" -d \"wt_cbuf_flush_idx_w\" -q wt_cbuf_flush_idx"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign wt_cbuf_flush_vld_w = ~wt_cbuf_flush_idx[14+0-1];//max value = half bank entry * 2^0 +assign dp2reg_wt_flush_done = wt_cbuf_flush_idx[14+0-1]; +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_cbuf_flush_idx <= {18{1'b0}}; + end else begin + if ((wt_cbuf_flush_vld_w) == 1'b1) begin + wt_cbuf_flush_idx <= wt_cbuf_flush_idx_w; + // VCS coverage off + end else if ((wt_cbuf_flush_vld_w) == 1'b0) begin + end else begin + wt_cbuf_flush_idx <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// WT and WMB write to convolution buffer // +//////////////////////////////////////////////////////////////////////// +assign cdma2buf_wt_wr_en_w = wt_cbuf_wr_vld_w | wt_cbuf_flush_vld_w; +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $half_bank_entry_num = 32 * 512 / 2; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: assign cdma2buf_wt_wr_addr_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx[(1 + 16 ) -1:${k}] : +//: ${half_bank_entry_num} + wt_cbuf_flush_idx[16:${k}]; +//: assign cdma2buf_wt_wr_sel_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx[${k}-1:0] : +//: wt_cbuf_flush_idx[${k}-1:0]; +//: assign cdma2buf_wt_wr_data_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_data_w : +//: 0; +//: ); +//: +//: my $dmanum = int($atmc/$dmaif); +//: foreach my $s (0..${dmanum}-1) { +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_sel_w===${k}'d${s}\" -q cdma2buf_wt_wr_sel[${s}]"); +//: } +//: ## &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_sel_w\" -q cdma2buf_wt_wr_sel"); +//: } elsif($dmaif > $atmc) { +//: } else { +//: print qq( +//: assign cdma2buf_wt_wr_addr_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx : ${half_bank_entry_num} + wt_cbuf_flush_idx[16:0]; +//: assign cdma2buf_wt_wr_data_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_data_w : 0; +//: ); +//: } +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"cdma2buf_wt_wr_en_w\" -q cdma2buf_wt_wr_en"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_addr_w\" -q cdma2buf_wt_wr_addr"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cdma2buf_wt_wr_addr_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx : 8192 + wt_cbuf_flush_idx[16:0]; +assign cdma2buf_wt_wr_data_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_data_w : 0; +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2buf_wt_wr_en <= 1'b0; + end else begin + cdma2buf_wt_wr_en <= cdma2buf_wt_wr_en_w; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2buf_wt_wr_addr <= {17{1'b0}}; + end else begin + if ((cdma2buf_wt_wr_en_w) == 1'b1) begin + cdma2buf_wt_wr_addr <= cdma2buf_wt_wr_addr_w; + // VCS coverage off + end else if ((cdma2buf_wt_wr_en_w) == 1'b0) begin + end else begin + cdma2buf_wt_wr_addr <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// Non-SLCG clock domain end // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_data_w\" -q cdma2buf_wt_wr_data"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma2buf_wt_wr_data <= {64{1'b0}}; + end else begin + if ((cdma2buf_wt_wr_en_w) == 1'b1) begin + cdma2buf_wt_wr_data <= cdma2buf_wt_wr_data_w; + // VCS coverage off + end else if ((cdma2buf_wt_wr_en_w) == 1'b0) begin + end else begin + cdma2buf_wt_wr_data <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp2reg_nan_weight_num = 32'b0; +assign dp2reg_inf_weight_num = 32'b0; +//////////////////////////////////////////////////////////////////////// +// WT data status monitor // +//////////////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +//sc2cdma_wt_kernels are useless +//retiming +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"sc2cdma_wt_updt\" -q sc_wt_updt"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{15{1'b0}}\" -en \"sc2cdma_wt_updt\" -d \"sc2cdma_wt_entries\" -q sc_wt_entries"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc_wt_updt <= 1'b0; + end else begin + sc_wt_updt <= sc2cdma_wt_updt; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc_wt_entries <= {15{1'b0}}; + end else begin + if ((sc2cdma_wt_updt) == 1'b1) begin + sc_wt_entries <= sc2cdma_wt_entries; + // VCS coverage off + end else if ((sc2cdma_wt_updt) == 1'b0) begin + end else begin + sc_wt_entries <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//cation: the basic unit of data_stored, data_onfly and data_avl is atomic_m bytes, 32 bytes in Xavier +assign wt_data_onfly_add = (wt_req_reg_en_d2 & wt_req_stage_vld_d2 & ~wt_req_done_d2) ? wt_req_size_d2 : 4'b0; +//atom_m num per cbuf write, =dmaif/atom_m +//: my $dmaif = (64 / 8); +//: my $atmc=8; +//: my $atmm = 8; +//: my $atmm_dmaif = int($dmaif / $atmm); +//: my $atmm_atmc = int($atmc / $atmm); +//: print qq( +//: assign wt_data_onfly_sub = wt_cbuf_wr_vld_w ? 3'd${atmm_dmaif} : 3'b0; +//: ); +//: if($atmm_atmc == 4) { +//: print qq( +//: assign wt_data_stored_sub = status_update ? {incr_wt_entries_w, 2'd0} : 17'b0; +//: assign wt_data_avl_sub = sc_wt_updt ? {sc_wt_entries, 2'b0} : 17'b0; +//: ); +//: } elsif($atmm_atmc == 2) { +//: print qq( +//: assign wt_data_stored_sub = status_update ? {1'b0,incr_wt_entries_w, 1'd0} : 17'b0; +//: assign wt_data_avl_sub = sc_wt_updt ? {1'b0,sc_wt_entries, 1'b0} : 17'b0; +//: ); +//: } elsif($atmm_atmc == 1) { +//: print qq( +//: assign wt_data_stored_sub = status_update ? {2'b0,incr_wt_entries_w} : 17'b0; +//: assign wt_data_avl_sub = sc_wt_updt ? {2'b0,sc_wt_entries} : 17'b0; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign wt_data_onfly_sub = wt_cbuf_wr_vld_w ? 3'd1 : 3'b0; + +assign wt_data_stored_sub = status_update ? {2'b0,incr_wt_entries_w} : 17'b0; +assign wt_data_avl_sub = sc_wt_updt ? {2'b0,sc_wt_entries} : 17'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_wt_data_onfly_w, wt_data_onfly_w} = wt_data_onfly + wt_data_onfly_add - wt_data_onfly_sub; +//assign wt_data_stored_sub = status_update ? {incr_wt_entries_w, 2'b0} : 14'b0; +assign {mon_wt_data_stored_w, wt_data_stored_w} = wt_data_stored + wt_data_onfly_sub - wt_data_stored_sub; +//assign wt_data_avl_sub = sc_wt_updt ? {sc_wt_entries, 2'b0} : 14'b0; +assign {mon_wt_data_avl_w, wt_data_avl_w} = (clear_all) ? 17'b0 : wt_data_avl + wt_data_stored_sub - wt_data_avl_sub; +assign wt_data_onfly_reg_en = ((wt_req_reg_en_d2 & wt_req_stage_vld_d2) | wt_cbuf_wr_vld_w); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{14{1'b0}}\" -en \"wt_data_onfly_reg_en\" -d \"wt_data_onfly_w\" -q wt_data_onfly"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"wt_cbuf_wr_vld_w | status_update\" -d \"wt_data_stored_w\" -q wt_data_stored"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"status_update | sc_wt_updt | clear_all\" -d \"wt_data_avl_w\" -q wt_data_avl"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_data_onfly <= {14{1'b0}}; + end else begin + if ((wt_data_onfly_reg_en) == 1'b1) begin + wt_data_onfly <= wt_data_onfly_w; + // VCS coverage off + end else if ((wt_data_onfly_reg_en) == 1'b0) begin + end else begin + wt_data_onfly <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_data_stored <= {17{1'b0}}; + end else begin + if ((wt_cbuf_wr_vld_w | status_update) == 1'b1) begin + wt_data_stored <= wt_data_stored_w; + // VCS coverage off + end else if ((wt_cbuf_wr_vld_w | status_update) == 1'b0) begin + end else begin + wt_data_stored <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_data_avl <= {17{1'b0}}; + end else begin + if ((status_update | sc_wt_updt | clear_all) == 1'b1) begin + wt_data_avl <= wt_data_avl_w; + // VCS coverage off + end else if ((status_update | sc_wt_updt | clear_all) == 1'b0) begin + end else begin + wt_data_avl <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// status update logic // +//////////////////////////////////////////////////////////////////////// +assign status_group_cnt_inc = status_group_cnt + 1'b1; +assign status_last_group = (status_group_cnt_inc == group); +assign status_group_cnt_w = layer_st ? 12'b0 : status_group_cnt_inc; +assign status_done_w = layer_st ? 1'b0 : + status_last_group ? 1'b1 : status_done; +//: my $atmk = 8; +//: my $atmkbw = int(log($atmk) / log(2)); +//: print qq( +//: assign normal_bpg = {2'd0, byte_per_kernel, ${atmkbw}'b0}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign normal_bpg = {2'd0, byte_per_kernel, 3'b0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {mon_wt_required_bytes_w, + wt_required_bytes_w} = layer_st ? 33'b0 : + status_last_group ? {1'b0, reg2dp_weight_bytes} : + pre_wt_required_bytes + normal_bpg; +assign wt_required_en = ~required_valid & required_valid_w; +assign pre_wt_required_bytes_w = (layer_st) ? 32'b0 : wt_required_bytes; +assign required_valid_w = is_running & ~status_update; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"required_valid_w\" -q required_valid"); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"layer_st | wt_required_en\" -d \"wt_required_bytes_w\" -q wt_required_bytes"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + required_valid <= 1'b0; + end else begin + required_valid <= required_valid_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_required_bytes <= {32{1'b0}}; + end else begin + if ((layer_st | wt_required_en) == 1'b1) begin + wt_required_bytes <= wt_required_bytes_w; + // VCS coverage off + end else if ((layer_st | wt_required_en) == 1'b0) begin + end else begin + wt_required_bytes <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////// caution: one in fetched_cnt refers to 64 bytes //////// +assign {mon_wt_fetched_cnt_inc, wt_fetched_cnt_inc} = wt_fetched_cnt + 1'b1; +assign wt_fetched_cnt_w = layer_st ? 26'b0 : wt_fetched_cnt_inc; +//: my $m = int(log(8)/log(2)); +//: my $dmaif=64/8; ##byte number per dmaif tx +//: my $k = int(log($dmaif)/log(2)); +//: my $atmc=8 * 8; +//: my $dmaifbw=64; +//: if($atmc > $dmaifbw) { +//: my $j = int( log( ${atmc}/${dmaifbw} )/log(2) ); +//: print qq( +//: assign wt_satisfied = is_running & ({wt_fetched_cnt, ${k}'b0} >= wt_required_bytes) & ~(|wt_fetched_cnt[${j}-1:0]); +//: ); +//: } else { +//: print qq( +//: assign wt_satisfied = is_running & ({3'd0, wt_fetched_cnt, ${k}'b0} >= wt_required_bytes); // wt_fetched_cnt[0] +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign wt_satisfied = is_running & ({3'd0, wt_fetched_cnt, 3'b0} >= wt_required_bytes); // wt_fetched_cnt[0] + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign wt_satisfied = is_running & ({wt_fetched_cnt, 6'b0} >= wt_required_bytes) & ~wt_fetched_cnt[0]; +assign status_update = (~required_valid) ? 1'b0 : wt_satisfied; +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st | status_update\" -d \"status_group_cnt_w\" -q status_group_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st | status_update\" -d \"status_done_w\" -q status_done"); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"layer_st | status_update\" -d \"pre_wt_required_bytes_w\" -q pre_wt_required_bytes"); +//: &eperl::flop("-nodeclare -rval \"{26{1'b0}}\" -en \"layer_st | wt_cbuf_wr_vld_w\" -d \"wt_fetched_cnt_w\" -q wt_fetched_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_group_cnt <= {12{1'b0}}; + end else begin + if ((layer_st | status_update) == 1'b1) begin + status_group_cnt <= status_group_cnt_w; + // VCS coverage off + end else if ((layer_st | status_update) == 1'b0) begin + end else begin + status_group_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_done <= 1'b0; + end else begin + if ((layer_st | status_update) == 1'b1) begin + status_done <= status_done_w; + // VCS coverage off + end else if ((layer_st | status_update) == 1'b0) begin + end else begin + status_done <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_wt_required_bytes <= {32{1'b0}}; + end else begin + if ((layer_st | status_update) == 1'b1) begin + pre_wt_required_bytes <= pre_wt_required_bytes_w; + // VCS coverage off + end else if ((layer_st | status_update) == 1'b0) begin + end else begin + pre_wt_required_bytes <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_fetched_cnt <= {26{1'b0}}; + end else begin + if ((layer_st | wt_cbuf_wr_vld_w) == 1'b1) begin + wt_fetched_cnt <= wt_fetched_cnt_w; + // VCS coverage off + end else if ((layer_st | wt_cbuf_wr_vld_w) == 1'b0) begin + end else begin + wt_fetched_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// avaliable kernels monitor // +//////////////////////////////////////////////////////////////////////// +// Avaliable kernel size is useless here. Discard the code; +//////////////////////////////////////////////////////////////////////// +// CDMA WT communicate to CSC // +//////////////////////////////////////////////////////////////////////// +assign pre_wt_fetched_cnt_w = status_last_group ? 26'b0 : wt_fetched_cnt; +assign {mon_incr_wt_cnt, incr_wt_cnt} = wt_fetched_cnt - pre_wt_fetched_cnt; +// dmaif vs atom_c +//: my $dmaif=64/8; +//: my $atmc=8; +//: if($dmaif == $atmc){ +//: print qq( +//: assign incr_wt_entries_w = incr_wt_cnt[14:0]; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log($dmaif/$atmc)/log(2)); +//: print qq( +//: assign incr_wt_entries_w = {incr_wt_cnt[12:0],{${k}{1'b0}}}; +//: ); +//: } elsif($dmaif < $atmc) { +//: my $k = int(log($atmc/$dmaif)/log(2)); +//: print qq( +//: assign incr_wt_entries_w = {{(2+${k}){1'b0}},incr_wt_cnt[12:${k}]}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign incr_wt_entries_w = incr_wt_cnt[14:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign incr_wt_entries_w = incr_wt_cnt[12 :1]; +//: my $atmk = 8; +//: my $atmkbw = int(log($atmk)/log(2)); +//: print qq( +//: assign incr_wt_kernels_w = (~status_last_group) ? 6'd${atmk} : (reg2dp_weight_kernel[${atmkbw}-1:0] + 1'b1); +//: ); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"status_update\" -q incr_wt_updt"); +//: &eperl::flop("-nodeclare -rval \"{26{1'b0}}\" -en \"status_update\" -d \"pre_wt_fetched_cnt_w\" -q pre_wt_fetched_cnt"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"status_update\" -d \"incr_wt_entries_w\" -q incr_wt_entries"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"status_update\" -d \"incr_wt_kernels_w\" -q incr_wt_kernels"); +//: my $i; +//: my $j; +//: my $k; +//: my $name; +//: my $wid; +//: my $cbuf_wr_delay = 3; +//: my @list = ("wt_kernels", "wt_entries"); +//: my @width = (6, 15); +//: +//: for($i = 0; $i < @list; $i ++) { +//: $name = $list[$i]; +//: print "assign incr_${name}_d0 = incr_${name};\n"; +//: } +//: print "assign incr_wt_updt_d0 = incr_wt_updt;\n"; +//: print "\n\n"; +//: +//: for($j = 1; $j <= $cbuf_wr_delay; $j ++) { +//: $k = $j - 1; +//: for($i = 0; $i < @list; $i ++) { +//: $name = $list[$i]; +//: $wid = $width[$i]; +//: &eperl::flop("-wid ${wid} -rval \"'b0\" -en \"incr_wt_updt_d${k}\" -d \"incr_${name}_d${k}\" -q incr_${name}_d${j}"); +//: } +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"incr_wt_updt_d${k}\" -q incr_wt_updt_d${j}"); +//: } +//: print "\n\n"; +//: +//: $j = $cbuf_wr_delay; +//: print "assign cdma2sc_wt_kernels[5:0] = incr_wt_kernels_d${j};\n"; +//: print "assign cdma2sc_wt_entries = incr_wt_entries_d${j};\n"; +//: print "assign cdma2sc_wmb_entries = 12'b0; \n"; +//: print "assign cdma2sc_wt_updt = incr_wt_updt_d${j};\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign incr_wt_kernels_w = (~status_last_group) ? 6'd8 : (reg2dp_weight_kernel[3-1:0] + 1'b1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_updt <= 1'b0; + end else begin + incr_wt_updt <= status_update; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pre_wt_fetched_cnt <= {26{1'b0}}; + end else begin + if ((status_update) == 1'b1) begin + pre_wt_fetched_cnt <= pre_wt_fetched_cnt_w; + // VCS coverage off + end else if ((status_update) == 1'b0) begin + end else begin + pre_wt_fetched_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_entries <= {15{1'b0}}; + end else begin + if ((status_update) == 1'b1) begin + incr_wt_entries <= incr_wt_entries_w; + // VCS coverage off + end else if ((status_update) == 1'b0) begin + end else begin + incr_wt_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_kernels <= {6{1'b0}}; + end else begin + if ((status_update) == 1'b1) begin + incr_wt_kernels <= incr_wt_kernels_w; + // VCS coverage off + end else if ((status_update) == 1'b0) begin + end else begin + incr_wt_kernels <= 'bx; + // VCS coverage on + end + end +end +assign incr_wt_kernels_d0 = incr_wt_kernels; +assign incr_wt_entries_d0 = incr_wt_entries; +assign incr_wt_updt_d0 = incr_wt_updt; + + +reg [5:0] incr_wt_kernels_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_kernels_d1 <= 'b0; + end else begin + if ((incr_wt_updt_d0) == 1'b1) begin + incr_wt_kernels_d1 <= incr_wt_kernels_d0; + // VCS coverage off + end else if ((incr_wt_updt_d0) == 1'b0) begin + end else begin + incr_wt_kernels_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [14:0] incr_wt_entries_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_entries_d1 <= 'b0; + end else begin + if ((incr_wt_updt_d0) == 1'b1) begin + incr_wt_entries_d1 <= incr_wt_entries_d0; + // VCS coverage off + end else if ((incr_wt_updt_d0) == 1'b0) begin + end else begin + incr_wt_entries_d1 <= 'bx; + // VCS coverage on + end + end +end +reg incr_wt_updt_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_updt_d1 <= 1'b0; + end else begin + incr_wt_updt_d1 <= incr_wt_updt_d0; + end +end +reg [5:0] incr_wt_kernels_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_kernels_d2 <= 'b0; + end else begin + if ((incr_wt_updt_d1) == 1'b1) begin + incr_wt_kernels_d2 <= incr_wt_kernels_d1; + // VCS coverage off + end else if ((incr_wt_updt_d1) == 1'b0) begin + end else begin + incr_wt_kernels_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [14:0] incr_wt_entries_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_entries_d2 <= 'b0; + end else begin + if ((incr_wt_updt_d1) == 1'b1) begin + incr_wt_entries_d2 <= incr_wt_entries_d1; + // VCS coverage off + end else if ((incr_wt_updt_d1) == 1'b0) begin + end else begin + incr_wt_entries_d2 <= 'bx; + // VCS coverage on + end + end +end +reg incr_wt_updt_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_updt_d2 <= 1'b0; + end else begin + incr_wt_updt_d2 <= incr_wt_updt_d1; + end +end +reg [5:0] incr_wt_kernels_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_kernels_d3 <= 'b0; + end else begin + if ((incr_wt_updt_d2) == 1'b1) begin + incr_wt_kernels_d3 <= incr_wt_kernels_d2; + // VCS coverage off + end else if ((incr_wt_updt_d2) == 1'b0) begin + end else begin + incr_wt_kernels_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [14:0] incr_wt_entries_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_entries_d3 <= 'b0; + end else begin + if ((incr_wt_updt_d2) == 1'b1) begin + incr_wt_entries_d3 <= incr_wt_entries_d2; + // VCS coverage off + end else if ((incr_wt_updt_d2) == 1'b0) begin + end else begin + incr_wt_entries_d3 <= 'bx; + // VCS coverage on + end + end +end +reg incr_wt_updt_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + incr_wt_updt_d3 <= 1'b0; + end else begin + incr_wt_updt_d3 <= incr_wt_updt_d2; + end +end + + +assign cdma2sc_wt_kernels[5:0] = incr_wt_kernels_d3; +assign cdma2sc_wt_entries = incr_wt_entries_d3; +assign cdma2sc_wmb_entries = 12'b0; +assign cdma2sc_wt_updt = incr_wt_updt_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cdma2sc_wt_kernels[13:6] = 8'b0; +`ifndef SYNTHESIS +assign dbg_wt_kernel_bytes_w[31:0] = layer_st ? 32'b0 : wt_required_bytes_w - wt_required_bytes; +//assign dbg_full_weight = (reg2dp_weight_bytes <= {weight_bank, 8'h0}); +assign dbg_full_weight = (reg2dp_weight_bytes <= {weight_bank, 9'h0}); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"layer_st | wt_required_en\" -d \"dbg_wt_kernel_bytes_w\" -q dbg_wt_kernel_bytes"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_wt_kernel_bytes <= {32{1'b0}}; + end else begin + if ((layer_st | wt_required_en) == 1'b1) begin + dbg_wt_kernel_bytes <= dbg_wt_kernel_bytes_w; + // VCS coverage off + end else if ((layer_st | wt_required_en) == 1'b0) begin + end else begin + dbg_wt_kernel_bytes <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`endif +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_stall_inc <= 1'b0; + end else begin + wt_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_stall_clr <= 1'b0; + end else begin + wt_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_stall_cen <= 1'b0; + end else begin + wt_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_wt_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = wt_rd_stall_inc ^ dp2reg_wt_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wt_rd_stall_inc && !dp2reg_wt_rd_stall_dec)? stl_cnt_inc : (!wt_rd_stall_inc && dp2reg_wt_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (wt_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (wt_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_wt_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_inc <= 1'b0; + end else begin + wt_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_dec <= 1'b0; + end else begin + wt_rd_latency_dec <= dma_rsp_fifo_ready & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_clr <= 1'b0; + end else begin + wt_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_cen <= 1'b0; + end else begin + wt_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +// +assign ltc_1_inc = (outs_dp2reg_wt_rd_latency!=511) & wt_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_wt_rd_latency!=511) & wt_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (wt_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (wt_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_wt_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_wt__cbuf_idx_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w) & wt_cbuf_wr_idx_wrap); + endproperty +// Cover 0 : "((wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w) & wt_cbuf_wr_idx_wrap)" + FUNCPOINT_cdma_wt__cbuf_idx_wrap__0_COV : cover property (cdma_wt__cbuf_idx_wrap__0_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,2,0,"No Xs allowed on cur_state") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, cur_state); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | is_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_end))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_req_reg_en_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_req_reg_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_req_reg_en_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dbg_src_wr_ptr_en & ~dbg_src_wr_ptr))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dbg_src_wr_ptr_en & dbg_src_wr_ptr))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rd_rsp_vld & dma_rd_rsp_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_rsp_valid))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(wt_cbuf_flush_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cdma2buf_wt_wr_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cdma2buf_wt_wr_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cdma2buf_wt_wr_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(nan_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(inf_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(sc2cdma_wt_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(sc2cdma_wt_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(wt_data_onfly_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(wt_cbuf_wr_vld_w | status_update))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(status_update | sc_wt_updt | clear_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wgs_data_onfly_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | wt_required_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | status_update))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | wt_cbuf_wr_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(status_update))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(incr_wt_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(incr_wt_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(incr_wt_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Data banks is more than 15!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && (reg2dp_data_bank == 4'hf))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Weight banks is more than 15!") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && (reg2dp_weight_bank == 4'hf))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Sum of data & weight banks is more than 16 when weight uncompressed") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && ~is_compressed && (weight_bank_end_w > 16))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Sum of data & weight banks is more than 15 when weight compressed!") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && is_compressed && (weight_bank_end_w > 15))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_req_burst_cnt_dec is overflow") zzz_assert_never_19x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && mon_wt_req_burst_cnt_dec)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! FSM done when wt fetch is not!") zzz_assert_never_29x (nvdla_core_clk, `ASSERT_RESET, (is_running & ~is_nxt_running & ~wt_req_done_d3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_onfly is not zero when idle") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (~is_running && (|wt_data_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_stored is not zero when idle") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, (~is_running && (|wt_data_stored))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_56x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_fifo_ready & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_57x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & dma_rd_rsp_rdy & (dma_rsp_size_cnt_inc > dma_rsp_size))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_58x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_59x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & (dma_rsp_size_cnt_inc > 8'h8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"WT and FLUSH write hazard") zzz_assert_never_71x (nvdla_core_clk, `ASSERT_RESET, (wt_cbuf_wr_vld_w & wt_cbuf_flush_vld_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_onfly_w is overflow") zzz_assert_never_80x (nvdla_core_ng_clk, `ASSERT_RESET, (reg2dp_op_en & mon_wt_data_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_stored_w is overflow") zzz_assert_never_81x (nvdla_core_ng_clk, `ASSERT_RESET, (reg2dp_op_en & mon_wt_data_stored_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_onfly is not zero when idle") zzz_assert_never_82x (nvdla_core_ng_clk, `ASSERT_RESET, (~is_running & (|wt_data_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_stored is not zero when idle") zzz_assert_never_83x (nvdla_core_ng_clk, `ASSERT_RESET, (~is_running & (|wt_data_stored))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_avl_w is overflow") zzz_assert_never_84x (nvdla_core_ng_clk, `ASSERT_RESET, (reg2dp_op_en && mon_wt_data_avl_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_fetched_cnt_w is overflow") zzz_assert_never_103x (nvdla_core_clk, `ASSERT_RESET, ((layer_st | wt_cbuf_wr_vld_w) & mon_wt_fetched_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Config error! Run out of weight buffer: uncompressed weight!") zzz_assert_never_121x (nvdla_core_clk, `ASSERT_RESET, (is_running & ~reg2dp_skip_weight_rls & ~dbg_full_weight & ~is_compressed & ~status_done & ((dbg_wt_kernel_bytes + 128) > {weight_bank, 15'b0}))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Config error! Run out of weight buffer: full weight!") zzz_assert_never_124x (nvdla_core_clk, `ASSERT_RESET, (is_running & reg2dp_skip_weight_rls & ~dbg_full_weight)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Weight output update with zero kernels") zzz_assert_never_126x (nvdla_core_clk, `ASSERT_RESET, (cdma2sc_wt_updt & ~(|cdma2sc_wt_kernels))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_127x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && wt_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_wt +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_8ATMM_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , atmm8_wr_prdy + , atmm8_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , atmm8_wr_pause +`endif + , atmm8_wr_pd + , atmm8_rd_prdy + , atmm8_rd_pvld + , atmm8_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output atmm8_wr_prdy; +input atmm8_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input atmm8_wr_pause; +`endif +input [64:0] atmm8_wr_pd; +input atmm8_rd_prdy; +output atmm8_rd_pvld; +output [64:0] atmm8_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg atmm8_wr_busy_int; // copy for internal use +assign atmm8_wr_prdy = !atmm8_wr_busy_int; +assign wr_reserving = atmm8_wr_pvld && !atmm8_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [3:0] atmm8_wr_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? atmm8_wr_count : (atmm8_wr_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (atmm8_wr_count + 1'd1) : atmm8_wr_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire atmm8_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check atmm8_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || atmm8_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire atmm8_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check atmm8_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_wr_busy_int <= 1'b0; + atmm8_wr_count <= 4'd0; + end else begin + atmm8_wr_busy_int <= atmm8_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + atmm8_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + atmm8_wr_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as atmm8_wr_pvld +// +// RAM +// +reg [2:0] atmm8_wr_adr; // current write address +wire [2:0] atmm8_rd_adr_p; // read address to use for ram +wire [64:0] atmm8_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_8x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( atmm8_wr_adr ) + , .we ( wr_pushing ) + , .di ( atmm8_wr_pd ) + , .ra ( atmm8_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( atmm8_rd_pd_p ) + , .ore ( ore ) + ); +// next atmm8_wr_adr if wr_pushing=1 +wire [2:0] wr_adr_next = atmm8_wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + atmm8_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + atmm8_wr_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [2:0] atmm8_rd_adr; // current read address +// next read address +wire [2:0] rd_adr_next = atmm8_rd_adr + 1'd1; // spyglass disable W484 +assign atmm8_rd_adr_p = rd_popping ? rd_adr_next : atmm8_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + atmm8_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + atmm8_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg atmm8_rd_pvld_p; // data out of fifo is valid +reg atmm8_rd_pvld_int; // internal copy of atmm8_rd_pvld +assign atmm8_rd_pvld = atmm8_rd_pvld_int; +assign rd_popping = atmm8_rd_pvld_p && !(atmm8_rd_pvld_int && !atmm8_rd_prdy); +reg [3:0] atmm8_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? atmm8_rd_count_p : + (atmm8_rd_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (atmm8_rd_count_p + 1'd1) : + atmm8_rd_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~atmm8_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_rd_count_p <= 4'd0; + atmm8_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + atmm8_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + atmm8_rd_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + atmm8_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + atmm8_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (atmm8_rd_pvld_p || (atmm8_rd_pvld_int && !atmm8_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_rd_pvld_int <= 1'b0; + end else begin + atmm8_rd_pvld_int <= rd_req_next; + end +end +assign atmm8_rd_pd = atmm8_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (atmm8_wr_pvld && !atmm8_wr_busy_int) || (atmm8_wr_busy_int != atmm8_wr_busy_next)) || (rd_pushing || rd_popping || (atmm8_rd_pvld_int && atmm8_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( atmm8_wr_pvld && !(!atmm8_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, atmm8_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WT_8ATMM_fifo") true +// synopsys dc_script_end +//| &Attachment -no_warn EndModulePrepend; +//| _attach_EndModulePrepend_1; +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +//| _attach_EndModulePrepend_2; +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDMA_WT_8ATMM_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v.vcp new file mode 100644 index 0000000..f549357 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v.vcp @@ -0,0 +1,1976 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_wt.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_CDMA_wt ( + nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,cdma_wt2mcif_rd_req_ready //|< i + ,mcif2cdma_wt_rd_rsp_pd //|< i + ,mcif2cdma_wt_rd_rsp_valid //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_arb_weight //|< i + ,reg2dp_arb_wmb //|< i + ,reg2dp_byte_per_kernel //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_nan_to_zero //|< i + ,reg2dp_op_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_skip_weight_rls //|< i + ,reg2dp_weight_addr_high //|< i + ,reg2dp_weight_addr_low //|< i + ,reg2dp_weight_bank //|< i + ,reg2dp_weight_bytes //|< i + ,reg2dp_weight_format //|< i + ,reg2dp_weight_kernel //|< i + ,reg2dp_weight_ram_type //|< i + ,reg2dp_weight_reuse //|< i + ,reg2dp_wgs_addr_high //|< i + ,reg2dp_wgs_addr_low //|< i + ,reg2dp_wmb_addr_high //|< i + ,reg2dp_wmb_addr_low //|< i + ,reg2dp_wmb_bytes //|< i + ,sc2cdma_wmb_entries //|< i + ,sc2cdma_wt_entries //|< i + ,sc2cdma_wt_kernels //|< i * + ,sc2cdma_wt_pending_req //|< i + ,sc2cdma_wt_updt //|< i + ,status2dma_fsm_switch //|< i + ,cdma2buf_wt_wr_en //|> o +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,cdma2buf_wt_wr_sel +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_wt_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_wt_wr_addr${i} +//: ,cdma2buf_wt_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } +//,cdma2buf_wt_wr_addr //|> o +//,cdma2buf_wt_wr_data //|> o +//,cdma2buf_wt_wr_hsel //|> o + ,cdma2sc_wmb_entries //|> o + ,cdma2sc_wt_entries //|> o + ,cdma2sc_wt_kernels //|> o + ,cdma2sc_wt_pending_ack //|> o + ,cdma2sc_wt_updt //|> o + ,cdma_wt2mcif_rd_req_pd //|> o + ,cdma_wt2mcif_rd_req_valid //|> o + ,dp2reg_inf_weight_num //|> o + ,dp2reg_nan_weight_num //|> o + ,dp2reg_wt_flush_done //|> o + ,dp2reg_wt_rd_latency //|> o + ,dp2reg_wt_rd_stall //|> o + ,mcif2cdma_wt_rd_rsp_ready //|> o + ,wt2status_state //|> o + ); +///////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output cdma_wt2mcif_rd_req_valid; +input cdma_wt2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] cdma_wt2mcif_rd_req_pd; +input mcif2cdma_wt_rd_rsp_valid; +output mcif2cdma_wt_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2cdma_wt_rd_rsp_pd; +output cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_sel ; +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } +input status2dma_fsm_switch; +output [1:0] wt2status_state; +output cdma2sc_wt_updt; +output [13:0] cdma2sc_wt_kernels; +output [14:0] cdma2sc_wt_entries; +output [11:0] cdma2sc_wmb_entries; +input sc2cdma_wt_updt; +input [13:0] sc2cdma_wt_kernels; +input [14:0] sc2cdma_wt_entries; +input [8:0] sc2cdma_wmb_entries; +input sc2cdma_wt_pending_req; +output cdma2sc_wt_pending_ack; +input nvdla_core_ng_clk; +input [3:0] reg2dp_arb_weight; +input [3:0] reg2dp_arb_wmb; +input [0:0] reg2dp_op_en; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_weight_reuse; +input [0:0] reg2dp_skip_weight_rls; +input [0:0] reg2dp_weight_format; +input [17:0] reg2dp_byte_per_kernel; +input [12:0] reg2dp_weight_kernel; +input [0:0] reg2dp_weight_ram_type; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: input [31-${atmbw}:0] reg2dp_weight_addr_low; +//: input [31-${atmbw}:0] reg2dp_wgs_addr_low; +//: input [31-${atmbw}:0] reg2dp_wmb_addr_low; +//: ); +input [31:0] reg2dp_weight_addr_high; +input [31:0] reg2dp_weight_bytes; +input [31:0] reg2dp_wgs_addr_high; +input [31:0] reg2dp_wmb_addr_high; +input [27:0] reg2dp_wmb_bytes; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_weight_bank; +input [0:0] reg2dp_nan_to_zero; +input [0:0] reg2dp_dma_en; +output [31:0] dp2reg_nan_weight_num; +output [31:0] dp2reg_inf_weight_num; +output dp2reg_wt_flush_done; +output [31:0] dp2reg_wt_rd_stall; +output [31:0] dp2reg_wt_rd_latency; +///////////////////////////////////////////////////// +reg [18:0] byte_per_kernel; +reg [16:0] cdma2buf_wt_wr_addr; +reg cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: my $s = int($atmc/$dmaif); +//: print qq( +//: reg [${s}-1:0] cdma2buf_wt_wr_sel ; +//: wire [${k}-1:0] cdma2buf_wt_wr_sel_w; +//: ); +//: } +//reg cdma2buf_wt_wr_sel; +reg [1:0] cur_state; +reg [1:0] dbg_dma_req_src_b0; +reg [1:0] dbg_dma_req_src_b1; +reg dbg_src_rd_ptr; +reg dbg_src_wr_ptr; +reg [31:0] dbg_wmb_kernel_bits; +reg [31:0] dbg_wt_kernel_bytes; +wire [3:0] dma_req_size; +wire [2:0] dma_req_size_out; +//: my $mask = (64/8/8); +//: my $atmm = (8 * 8); +//: print qq( +//: wire [${atmm}-1:0] wt_local_data_w; +//: reg [${atmm}-1:0] wt_local_data; +//: wire [${atmm}-1:0] wmb_local_data_w; +//: reg [${atmm}-1:0] wmb_local_data; +//: reg [${atmm}-1:0] wgs_local_data; +//: ); +//: foreach my $i(0..$mask-1) { +//: print qq( +//: wire [${atmm}-1:0] dma_rsp_data_p${i}; +//: ); +//: } +wire [64 -1:0] wt_cbuf_wr_data_ori_w; +wire [64 -1:0] wt_cbuf_wr_data_w; +reg [64 -1:0] cdma2buf_wt_wr_data; +wire [64 -1:0] wmb_cbuf_wr_data_w; +wire [64 -1:0] cdma2buf_wt_wr_data_w; +wire [3:0] dma_rsp_size; +reg [3:0] dma_rsp_size_cnt; +wire [31:0] dp2reg_wt_rd_latency=32'd0; +reg [31:0] dp2reg_wt_rd_stall; +reg [11:0] group; +reg [14:0] incr_wt_entries; +reg [5:0] incr_wt_kernels; +reg incr_wt_updt; +reg [4:0] last_data_bank; +reg last_skip_weight_rls; +reg [4:0] last_weight_bank; +reg layer_st_d1; +reg ltc_1_adv; +reg [10:0] ltc_1_cnt_dec; +reg [10:0] ltc_1_cnt_ext; +reg [10:0] ltc_1_cnt_inc; +reg [10:0] ltc_1_cnt_mod; +reg [10:0] ltc_1_cnt_new; +reg [10:0] ltc_1_cnt_nxt; +reg [8:0] ltc_1_cnt_cur; +wire ltc_1_dec; +wire ltc_1_inc; +reg ltc_2_adv; +reg [33:0] ltc_2_cnt_dec; +reg [33:0] ltc_2_cnt_ext; +reg [33:0] ltc_2_cnt_inc; +reg [33:0] ltc_2_cnt_mod; +reg [33:0] ltc_2_cnt_new; +reg [33:0] ltc_2_cnt_nxt; +reg ltc_2_dec; +reg ltc_2_inc; +reg [31:0] ltc_2_cnt_cur; +reg nan_pass; +reg [1:0] nxt_state; +reg [8:0] outs_dp2reg_wt_rd_latency; +reg pending_ack; +reg pending_req; +reg pending_req_d1; +reg [25:0] pre_wt_fetched_cnt; +reg [31:0] pre_wt_required_bytes; +reg required_valid; +reg [14:0] sc_wt_entries; +reg sc_wt_updt; +reg status_done; +reg [3:0] status_done_cnt; +reg [11:0] status_group_cnt; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [5:0] weight_bank; +reg [6:0] weight_bank_end; +reg [1:0] wt2status_state; +////: my $bank_entry = NVDLA_CBUF_BANK_NUMBER * NVDLA_CBUF_BANK_DEPTH; +////: my $bank_entry_bw = int( log( $bank_entry)/log(2) ); +////: my $dmaif=NVDLA_CDMA_DMAIF_BW; +////: my $atmc=NVDLA_MAC_ATOMIC_C_SIZE*NVDLA_CDMA_BPE; +////: my $k; +////: if($dmaif < $atmc) { +////: $k = int(log(int($atmc/$dmaif))/log(2)); +////: } else { +////: $k = 0; +////: } +////: print qq( +////: reg [${bank_entry_bw}+$k-1:0] wt_cbuf_flush_idx;//max value = half bank entry * 2^$k +////: ); +reg [17:0] wt_cbuf_flush_idx; +reg [16:0] wt_cbuf_wr_idx; +reg [16:0] wt_data_avl; +reg [13:0] wt_data_onfly; +reg [16:0] wt_data_stored; +reg [25:0] wt_fetched_cnt; +reg [31:0] wt_fp16_inf_flag; +reg wt_fp16_inf_vld; +reg [31:0] wt_fp16_nan_flag; +reg wt_fp16_nan_vld; +reg wt_local_data_vld; +reg wt_rd_latency_cen; +reg wt_rd_latency_clr; +reg wt_rd_latency_dec; +reg wt_rd_latency_inc; +reg wt_rd_stall_cen; +reg wt_rd_stall_clr; +reg wt_rd_stall_inc; +reg wt_req_done_d2; +reg wt_req_done_d3; +reg wt_req_last_d2; +reg [3:0] wt_req_size_d1; +reg [3:0] wt_req_size_d2; +reg [3:0] wt_req_size_d3; +reg [2:0] wt_req_size_out_d2; +reg [2:0] wt_req_size_out_d3; +reg wt_req_stage_vld_d1; +reg wt_req_stage_vld_d2; +reg wt_req_vld_d3; +reg [31:0] wt_required_bytes; +wire arb_sp_out_vld; +wire arb_sp_out_rdy; +wire [16:0] cdma2buf_wt_wr_addr_w; +wire cdma2buf_wt_wr_en_w; +//wire cdma2buf_wt_wr_sel_w; +wire clear_all; +wire [5:0] data_bank_w; +wire [1:0] dbg_dma_req_src; +wire dbg_full_weight; +wire dbg_src_rd_ptr_en; +wire dbg_src_rd_ptr_w; +wire dbg_src_wr_ptr_en; +wire dbg_src_wr_ptr_w; +wire [31:0] dbg_wt_kernel_bytes_w; +wire [63:0] dma_rd_req_addr; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_rdy; +wire [14:0] dma_rd_req_size; +wire dma_rd_req_type; +wire dma_rd_req_vld; +wire [64 -1:0] dma_rd_rsp_data; +wire [( 64 + (64/8/8) )-64 -1:0] dma_rd_rsp_mask; +wire [( 64 + (64/8/8) )-1:0] dma_rd_rsp_pd; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +wire [5:0] dma_req_fifo_data; +wire dma_req_fifo_ready; +wire dma_req_fifo_req; +wire [1:0] dma_req_src; +wire [5:0] dma_rsp_fifo_data; +wire dma_rsp_fifo_ready; +wire dma_rsp_fifo_req; +wire [3:0] dma_rsp_size_cnt_inc; +wire [3:0] dma_rsp_size_cnt_w; +wire [1:0] dma_rsp_src; +wire [31:0] dp2reg_inf_weight_num_inc; +wire [31:0] dp2reg_inf_weight_num_w; +wire [31:0] dp2reg_nan_weight_num_inc; +wire [31:0] dp2reg_nan_weight_num_w; +wire dp2reg_wt_rd_stall_dec; +wire fetch_done; +wire [10:0] group_op; +wire [11:0] group_w; +wire [25:0] incr_wt_cnt; +wire [14:0] incr_wt_entries_d0; +wire [14:0] incr_wt_entries_w; +wire [5:0] incr_wt_kernels_d0; +wire [5:0] incr_wt_kernels_w; +wire incr_wt_updt_d0; +wire inf_carry; +wire inf_reg_en; +wire is_compressed; +wire is_fp16; +wire is_int8; +wire is_nxt_running; +wire is_pending; +wire is_running; +wire layer_end; +wire layer_st; +wire mon_dma_rsp_size_cnt_inc; +wire mon_incr_wt_cnt; +wire mon_wt_cbuf_flush_idx_w; +wire mon_wt_data_avl_w; +wire mon_wt_data_onfly_w; +wire mon_wt_data_stored_w; +wire mon_wt_fetched_cnt_inc; +wire mon_wt_req_burst_cnt_dec; +wire mon_wt_req_sum; +wire mon_wt_required_bytes_w; +wire nan_carry; +wire nan_pass_w; +wire nan_reg_en; +wire need_pending; +wire [23:0] normal_bpg; +wire pending_req_end; +wire [25:0] pre_wt_fetched_cnt_w; +wire [31:0] pre_wt_required_bytes_w; +wire rd_req_rdyi; +wire required_valid_w; +wire [4:0] status_done_cnt_w; +wire status_done_w; +wire [11:0] status_group_cnt_inc; +wire [11:0] status_group_cnt_w; +wire status_last_group; +wire status_update; +wire [6:0] weight_bank_end_w; +wire [5:0] weight_bank_w; +wire [1:0] wt2status_state_w; +wire [17:0] wt_cbuf_flush_idx_w; +wire wt_cbuf_flush_vld_w; +wire [17:0] wt_cbuf_wr_idx_inc; +wire wt_cbuf_wr_idx_set; +wire [16:0] wt_cbuf_wr_idx_w; +wire wt_cbuf_wr_idx_wrap; +wire wt_cbuf_wr_vld_w; +wire [16:0] wt_data_avl_sub; +wire [16:0] wt_data_avl_w; +wire [3:0] wt_data_onfly_add; +wire wt_data_onfly_reg_en; +wire [3:0] wt_data_onfly_sub; +wire [13:0] wt_data_onfly_w; +wire [16:0] wt_data_stored_sub; +wire [16:0] wt_data_stored_w; +wire [25:0] wt_fetched_cnt_inc; +wire [25:0] wt_fetched_cnt_w; +wire [31:0] wt_fp16_exp_flag_w; +wire [31:0] wt_fp16_inf_flag_w; +wire [5:0] wt_fp16_inf_sum; +wire wt_fp16_inf_vld_w; +wire [31:0] wt_fp16_manti_flag_w; +wire [31:0] wt_fp16_nan_flag_w; +wire [5:0] wt_fp16_nan_sum; +wire wt_fp16_nan_vld_w; +//: my $mask = (64/8/8); +//: if($mask == 4) { +//: print qq( +//: wire [2:0] wt_local_data_cnt; +//: ); +//: } else { +//: print qq( +//: wire [1:0] wt_local_data_cnt; +//: ); +//: } +//wire [2:0] wt_local_data_cnt; +wire wt_local_data_reg_en; +wire wt_local_data_vld_w; +//wire [511:0] wt_nan_mask; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: wire [64-${atmbw}-1:0] wt_req_addr_w; +//: reg [64-${atmbw}-1:0] wt_req_addr_d2; +//: reg [64-${atmbw}-1:0] wt_req_addr_d3; +//: wire [64-${atmbw}-1:0] dma_req_addr; +//: wire [64-${atmbw}-1-3:0] wt_req_addr_inc; +//: wire [64-${atmbw}-1:0] wmb_req_addr_w; +//: reg [64-${atmbw}-1:0] wmb_req_addr_d2; +//: reg [64-${atmbw}-1:0] wmb_req_addr_d3; +//: wire [64-${atmbw}-1-3:0] wmb_req_addr_inc; +//: wire [64-${atmbw}-1:0] wgs_req_addr_w; +//: wire [64-${atmbw}-1:0] wgs_req_addr_inc; +//: reg [64-${atmbw}-1:0] wgs_req_addr_d1; +//: wire [64-${atmbw}-1+9:0] arb_wrr_req_package_in_00; +//: wire [64-${atmbw}-1+9:0] arb_wrr_req_package_in_01; +//: wire [64-${atmbw}-1+9:0] arb_wrr_out_package_w; +//: reg [64-${atmbw}-1+9:0] arb_wrr_out_package; +//: reg [64-${atmbw}-1+9:0] arb_wrr_out_back_package; +//: reg [64-${atmbw}-1+9:0] arb_sp_req_package_in_00; +//: reg [64-${atmbw}-1+9:0] arb_sp_req_package_in_01; +//: ); +//: my $atmm = 8; +//: my $k = int( log(${atmm}) / log(2) ); +//: print qq( +//: wire [32-${k}-1:0] wt_req_burst_cnt_w; +//: reg [32-${k}-1:0] wt_req_burst_cnt_d1; +//: wire [32-${k}-1:0] wt_req_burst_cnt_dec; +//: wire [28-${k}-1:0] wmb_req_burst_cnt_w; +//: wire [28-${k}-1:0] wmb_req_burst_cnt_dec; +//: ); +wire wt_req_done_w; +wire wt_req_last_w; +wire wt_req_overflow; +wire wt_req_overflow_d3; +wire wt_req_rdy; +wire wt_req_reg_en; +wire wt_req_reg_en_d0; +wire wt_req_reg_en_d1; +wire wt_req_reg_en_d2; +wire [3:0] wt_req_size_addr_limit; +wire [2:0] wt_req_size_out_w; +wire [3:0] wt_req_size_w; +wire [1:0] wt_req_src_d3; +wire [16:0] wt_req_sum; +wire wt_req_vld_w; +wire [31:0] wt_required_bytes_w; +wire wt_required_en; +wire wt_rsp_valid; +wire wt_satisfied; +wire [31:0] dp2reg_nan_weight_num; +wire [31:0] dp2reg_inf_weight_num; +//////////////////////////////////////////////////////////////////////// +// CDMA weight fetching logic FSM // +//////////////////////////////////////////////////////////////////////// +//## fsm (1) defines +localparam WT_STATE_IDLE = 2'b00; +localparam WT_STATE_PEND = 2'b01; +localparam WT_STATE_BUSY = 2'b10; +localparam WT_STATE_DONE = 2'b11; +always @(*) begin + nxt_state = cur_state; + begin + casez (cur_state) + WT_STATE_IDLE: begin + if ((reg2dp_op_en & need_pending)) begin + nxt_state = WT_STATE_PEND; + end + else if ((reg2dp_op_en & reg2dp_weight_reuse & last_skip_weight_rls)) begin + nxt_state = WT_STATE_DONE; + end + else if (reg2dp_op_en) begin + nxt_state = WT_STATE_BUSY; + end + end + WT_STATE_PEND: begin + if ((pending_req_end)) begin + nxt_state = WT_STATE_BUSY; + end + end + WT_STATE_BUSY: begin + if (fetch_done) begin + nxt_state = WT_STATE_DONE; + end + end + WT_STATE_DONE: begin + if (status2dma_fsm_switch) begin + nxt_state = WT_STATE_IDLE; + end + end + endcase + end +end +//: &eperl::flop("-nodeclare -rval \"WT_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign status_done_cnt_w[4:0] = layer_st ? 5'b0 : + (status_done & (status_done_cnt != 4'h8)) ? (status_done_cnt + 4'b1) : status_done_cnt; +assign fetch_done = status_done & (status_done_cnt == 4'h8); +assign need_pending = ((last_data_bank != reg2dp_data_bank) | (last_weight_bank != reg2dp_weight_bank)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + status_done_cnt <= {4{1'b0}}; + end else begin + if ((layer_st | is_running) == 1'b1) begin + status_done_cnt <= status_done_cnt_w[3:0]; + end + end +end +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en && (cur_state == WT_STATE_IDLE); +assign layer_end = status2dma_fsm_switch; +assign is_running = (cur_state == WT_STATE_BUSY); +assign is_pending = (cur_state == WT_STATE_PEND); +assign clear_all = pending_ack & pending_req; +assign is_nxt_running = (nxt_state == WT_STATE_BUSY); +assign wt2status_state_w = (nxt_state == WT_STATE_PEND) ? 1 : + (nxt_state == WT_STATE_BUSY) ? 2 : + (nxt_state == WT_STATE_DONE) ? 3 : + 0 ; +assign pending_req_end = pending_req_d1 & ~pending_req; +//: &eperl::flop("-nodeclare -rval \"0\" -d \"wt2status_state_w\" -q wt2status_state"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2cdma_wt_pending_req\" -q pending_req"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pending_req\" -q pending_req_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_pending\" -q pending_ack"); +assign cdma2sc_wt_pending_ack = pending_ack; +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"layer_end\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"layer_end\" -d \"reg2dp_weight_bank\" -q last_weight_bank"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_end\" -d \"reg2dp_skip_weight_rls\" -q last_skip_weight_rls"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"layer_st\" -q layer_st_d1"); +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -norst -en \"layer_st\" -d \"reg2dp_byte_per_kernel + 1'b1\" -q byte_per_kernel"); +assign is_int8 = 1'b1; +assign is_fp16 = 1'b0; +//: my $atmk = 8; +//: my $atmkbw = int(log($atmk) / log(2)); +//: print qq( assign group_op = {{($atmkbw-2){1'b0}}, reg2dp_weight_kernel[12:${atmkbw}]}; ); +assign group_w = group_op + 1'b1; +assign data_bank_w = reg2dp_data_bank + 1'b1; +assign weight_bank_w = reg2dp_weight_bank + 1'b1; +assign weight_bank_end_w = weight_bank_w + data_bank_w; +assign nan_pass_w = ~reg2dp_nan_to_zero | ~is_fp16; +assign is_compressed = 1'b0; +//: &eperl::flop("-nodeclare -rval \"{12{1'b1}}\" -en \"layer_st\" -d \"group_w\" -q group"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b1}}\" -en \"layer_st\" -d \"weight_bank_w\" -q weight_bank"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b1}}\" -en \"layer_st\" -d \"weight_bank_end_w\" -q weight_bank_end"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"layer_st\" -d \"nan_pass_w\" -q nan_pass"); +//////////////////////////////////////////////////////////////////////// +// generate address for weight data // +//////////////////////////////////////////////////////////////////////// +localparam SRC_ID_WT = 2'b00; +localparam SRC_ID_WMB = 2'b01; +localparam SRC_ID_WGS = 2'b10; +/////////////////// stage 1 /////////////////// +assign wt_req_reg_en_d0 = wt_req_reg_en; +assign {mon_wt_req_burst_cnt_dec, wt_req_burst_cnt_dec} = wt_req_burst_cnt_d1 - {{25{1'b0}}, wt_req_size_d1}; +//assign wt_req_burst_cnt_w = layer_st ? {reg2dp_weight_bytes, 2'b0} : wt_req_burst_cnt_dec; +//: my $atmm = 8; +//: my $k = int( log(${atmm}) / log(2) ); +//: print qq( assign wt_req_burst_cnt_w = layer_st ? reg2dp_weight_bytes[31:${k}] : wt_req_burst_cnt_dec; ); +assign wt_req_size_addr_limit = layer_st ? (4'h8 - reg2dp_weight_addr_low[2:0]) : 4'h8; +assign wt_req_size_w = ( {{25{1'b0}}, wt_req_size_addr_limit} > wt_req_burst_cnt_w) ? wt_req_burst_cnt_w[3:0] : wt_req_size_addr_limit; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"wt_req_reg_en_d0\" -d \"wt_req_size_w\" -q wt_req_size_d1"); +//: &eperl::flop("-nodeclare -rval \"{29{1'b0}}\" -en \"wt_req_reg_en_d0\" -d \"wt_req_burst_cnt_w\" -q wt_req_burst_cnt_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_nxt_running\" -q wt_req_stage_vld_d1"); +/////////////////// stage 2 /////////////////// +assign wt_req_reg_en_d1 = wt_req_reg_en; +assign wt_req_last_w = wt_req_stage_vld_d1 && (wt_req_burst_cnt_d1 == {{25{1'b0}}, wt_req_size_d1}); +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: assign wt_req_addr_inc = wt_req_addr_d2[64-${atmbw}-1:3] + 1'b1; +//: ); +assign wt_req_addr_w = (~wt_req_stage_vld_d2) ? {reg2dp_weight_addr_high,reg2dp_weight_addr_low} : {wt_req_addr_inc, 3'b0}; +assign wt_req_size_out_w = wt_req_size_d1[2:0] - 3'b1; +assign wt_req_done_w = layer_st ? 1'b0 : wt_req_last_d2 ? 1'b1 : wt_req_done_d2; +//: &eperl::flop("-nodeclare -rval \"0\" -en \"wt_req_reg_en_d1\" -d \"wt_req_addr_w\" -q wt_req_addr_d2"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"wt_req_reg_en_d1\" -d \"wt_req_size_d1\" -q wt_req_size_d2"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"wt_req_reg_en_d1\" -d \"wt_req_size_out_w\" -q wt_req_size_out_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_reg_en_d1\" -d \"wt_req_last_w\" -q wt_req_last_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"wt_req_reg_en_d1\" -d \"wt_req_done_w\" -q wt_req_done_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_stage_vld_d1 & is_nxt_running\" -q wt_req_stage_vld_d2"); +/////////////////// stage 3 /////////////////// +assign wt_req_reg_en_d2 = wt_req_reg_en; +assign wt_req_vld_w = is_nxt_running & wt_req_stage_vld_d2; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_vld_w\" -q wt_req_vld_d3"); +//: &eperl::flop("-nodeclare -rval \"0\" -en \"wt_req_reg_en_d2\" -d \"wt_req_addr_d2\" -q wt_req_addr_d3"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"wt_req_reg_en_d2\" -d \"wt_req_size_d2\" -q wt_req_size_d3"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"wt_req_reg_en_d2\" -d \"wt_req_size_out_d2\" -q wt_req_size_out_d3"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"wt_req_reg_en_d2\" -d \"(is_running & wt_req_done_d2)\" -q wt_req_done_d3"); +assign wt_req_src_d3 = SRC_ID_WT; +/////////////////// overflow control logic /////////////////// +assign {mon_wt_req_sum, wt_req_sum} = wt_data_onfly + wt_data_stored + wt_data_avl; +//: my $atmm8 = ((8*8)/8); +//: my $Cbuf_bank_size = 8 * 512; +//: my $cdma_addr_align = 8; +//: my $Cbuf_bank_fetch_bits = int( log($Cbuf_bank_size/$cdma_addr_align)/log(2) ); +//: print qq( +//: assign wt_req_overflow = is_running && (wt_req_sum > ({weight_bank, ${Cbuf_bank_fetch_bits}'b0} + $atmm8)); +//: ); +assign wt_req_overflow_d3 = wt_req_overflow; +/////////////////// pipeline control logic /////////////////// +assign wt_req_reg_en = layer_st | (is_running & (~wt_req_vld_d3 | wt_req_rdy)); +assign arb_sp_out_rdy = dma_rd_req_rdy & dma_req_fifo_ready; +assign arb_sp_out_vld = wt_req_vld_d3 & ~wt_req_overflow_d3 & ~wt_req_done_d3; +//assign wt_req_rdy = arb_sp_out_rdy; +assign wt_req_rdy = arb_sp_out_rdy & arb_sp_out_vld; +assign dma_req_src = wt_req_src_d3; +assign dma_req_size = wt_req_size_d3; +assign dma_req_size_out = wt_req_size_out_d3; +assign dma_req_addr = wt_req_addr_d3; +//////////////////////////////////////////////////////////////////////// +// CDMA WT read request interface // +//////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +// rd Channel: Request +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_weight_ram_type) + ,.mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid ) + ,.mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready ) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +wire dmaif_rd_rsp_prdy; +wire dmaif_rd_rsp_pvld; +wire [( 64 + (64/8/8) )-1:0] dmaif_rd_rsp_pd; +// rd Channel: Response +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready ) +//,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) +//,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) +//,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) + ,.dmaif_rd_rsp_pd (dmaif_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dmaif_rd_rsp_pvld ) + ,.dmaif_rd_rsp_prdy (dmaif_rd_rsp_prdy ) +); +/////////////////////////////////////////// +//DorisLei: adding a 8*atmm fifo here for data buffering. +//use case: Cbuf has empty entries, but empty entry number < 8*atmm +//continue reading 8*atmm data from memory and then Cbuf can be fully written +//: my $dmaif = 64; +//: my $atmm8 = 8 * (8 * 8); +//: my $fifo_depth = int( $atmm8/$dmaif ); +//: my $fifo_width = $dmaif; +// +NV_NVDLA_CDMA_WT_8ATMM_fifo u_8atmm_fifo( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.atmm8_wr_prdy (dmaif_rd_rsp_prdy) + ,.atmm8_wr_pvld (dmaif_rd_rsp_pvld) + ,.atmm8_wr_pd (dmaif_rd_rsp_pd) + ,.atmm8_rd_prdy (dma_rd_rsp_rdy ) + ,.atmm8_rd_pvld (dma_rd_rsp_vld ) + ,.atmm8_rd_pd (dma_rd_rsp_pd ) + ,.pwrbus_ram_pd (32'd0) + ); +/////////////////////////////////////////// +assign dma_rd_req_pd[32 -1:0] = dma_rd_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_rd_req_size[14:0]; +assign dma_rd_req_vld = arb_sp_out_vld & dma_req_fifo_ready; +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: assign dma_rd_req_addr = {dma_req_addr, ${atmbw}'b0}; +//: ); +assign dma_rd_req_size = {{12{1'b0}}, dma_req_size_out}; +assign dma_rd_req_type = reg2dp_weight_ram_type; +// assign dma_rd_rsp_rdy = 1'b1; +/////////////////////////////////// +//DorisLei redefine dma_rd_rsp_rdy to block reading process when cbuf is full +/////////////////////////////////// +//: my $atmc=8; +//: my $dmaif=64 / 8; +//: if($dmaif < $atmc) { +//: my $k = $atmc/$dmaif - 1; +//: print qq( +//: reg [3:0] dmaif_within_atmc_cnt; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: dmaif_within_atmc_cnt <= 4'd0; +//: else if(wt_cbuf_wr_vld_w) begin +//: if(dmaif_within_atmc_cnt == ${k}) +//: dmaif_within_atmc_cnt <= 4'd0; +//: else +//: dmaif_within_atmc_cnt <= dmaif_within_atmc_cnt + 1'b1; +//: end +//: end +//: ); +//: } +reg [16:0] wt_wr_dmatx_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_wr_dmatx_cnt <= 17'd0; + end else if(wt_cbuf_wr_vld_w & (!sc_wt_updt)) begin +//: my $atmc=8; +//: my $dmaif=64 / 8; +//: if($dmaif = $atmc) { +//: print qq( +//: wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1; +//: ); +//: } elsif($dmaif < $atmc) { +//: my $k = $atmc/$dmaif - 1; +//: print qq( +//: if(dmaif_within_atmc_cnt == ${k}) begin +//: wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1; +//: end +//: ); +//: } elsif($dmaif > $atmc) { +//: my $m = $dmaif/$atmc; +//: print qq( +//: wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + ${m}; +//: ); +//: } + end else if(!wt_cbuf_wr_vld_w & sc_wt_updt) begin + wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt - sc_wt_entries; + end else if(wt_cbuf_wr_vld_w & sc_wt_updt) begin + wt_wr_dmatx_cnt <= wt_wr_dmatx_cnt + 1'b1 - sc_wt_entries; + end +end +//: my $bank_depth = int( log(512)/log(2) ); +//: print qq( +//: assign dma_rd_rsp_rdy = wt_wr_dmatx_cnt < {weight_bank, ${bank_depth}'b0}; +//: ); +NV_NVDLA_CDMA_WT_fifo u_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dma_req_fifo_ready) //|> w + ,.wr_req (dma_req_fifo_req) //|< r + ,.wr_data (dma_req_fifo_data[5:0]) //|< r + ,.rd_ready (dma_rsp_fifo_ready) //|< r + ,.rd_req (dma_rsp_fifo_req) //|> w * + ,.rd_data (dma_rsp_fifo_data[5:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dma_req_fifo_req = arb_sp_out_vld & dma_rd_req_rdy; +assign dma_req_fifo_data = {dma_req_src, dma_req_size}; +//////////////////////////////////////////////////////////////////////// +// For verification/debug // +//////////////////////////////////////////////////////////////////////// +assign dbg_src_rd_ptr_en = (cdma_wt2mcif_rd_req_valid & cdma_wt2mcif_rd_req_ready); +assign dbg_src_rd_ptr_w = ~layer_st & (dbg_src_rd_ptr ^ dbg_src_rd_ptr_en); +assign dbg_src_wr_ptr_en = (dma_rd_req_vld & dma_req_fifo_ready & dma_rd_req_rdy); +assign dbg_src_wr_ptr_w = ~layer_st & (dbg_src_wr_ptr ^ dbg_src_wr_ptr_en); +assign dbg_dma_req_src = dbg_src_rd_ptr ? dbg_dma_req_src_b1 : dbg_dma_req_src_b0; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dbg_src_rd_ptr_w\" -q dbg_src_rd_ptr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dbg_src_wr_ptr_w\" -q dbg_src_wr_ptr"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dbg_src_wr_ptr_en & ~dbg_src_wr_ptr\" -d \"dma_req_src\" -q dbg_dma_req_src_b0"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dbg_src_wr_ptr_en & dbg_src_wr_ptr\" -d \"dma_req_src\" -q dbg_dma_req_src_b1"); +//////////////////////////////////////////////////////////////////////// +// CDMA read response connection // +//////////////////////////////////////////////////////////////////////// +assign dma_rd_rsp_data[64 -1:0] = dma_rd_rsp_pd[64 -1:0]; +assign dma_rd_rsp_mask[( 64 + (64/8/8) )-64 -1:0] = dma_rd_rsp_pd[( 64 + (64/8/8) )-1:64]; +assign {dma_rsp_src, dma_rsp_size} = dma_rsp_fifo_data; +assign {mon_dma_rsp_size_cnt_inc, dma_rsp_size_cnt_inc} = dma_rsp_size_cnt +//: my $mask = (64/8/8); +//: foreach my $i(0..$mask-1) { +//: print qq( +//: + dma_rd_rsp_mask[$i] +//: ); +//: } +//: print qq( ; ); +assign dma_rsp_size_cnt_w = (dma_rsp_size_cnt_inc == dma_rsp_size) ? 4'b0 : dma_rsp_size_cnt_inc; +assign dma_rsp_fifo_ready = (dma_rd_rsp_vld & dma_rd_rsp_rdy & (dma_rsp_size_cnt_inc == dma_rsp_size)); +assign wt_rsp_valid = (dma_rd_rsp_vld & dma_rd_rsp_rdy & (dma_rsp_src == SRC_ID_WT)); +assign { +//: my $mask = (64/8/8); +//: if($mask > 1) { +//: foreach my $i(0..$mask-2) { +//: my $j = $mask -$i -1; +//: print qq( dma_rsp_data_p${j} , ); +//: } +//: } + dma_rsp_data_p0} = dma_rd_rsp_data; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"dma_rd_rsp_vld & dma_rd_rsp_rdy\" -d \"dma_rsp_size_cnt_w\" -q dma_rsp_size_cnt"); +//////////////////////////////////////////////////////////////////////// +// WT read data // +//////////////////////////////////////////////////////////////////////// +assign wt_local_data_cnt = wt_local_data_vld +//: my $mask = (64/8/8); +//: foreach my $i(0..$mask-1) { +//: print qq( +//: + dma_rd_rsp_mask[$i] +//: ); +//: } +//: print qq( ; ); +//: my $mask = (64/8/8); +//: if($mask == 1) { +//: print qq( +//: assign wt_local_data_vld_w = 1'b0; +//: assign wt_local_data_reg_en = 1'b0; +//: assign wt_cbuf_wr_vld_w = wt_rsp_valid; +//: assign wt_local_data_w = 0;// bw +//: assign wt_cbuf_wr_data_ori_w = dma_rsp_data_p0; +//: ); +//: } elsif($mask == 2) { +//: print qq( +//: assign wt_local_data_vld_w = wt_local_data_cnt[0]; +//: assign wt_local_data_reg_en = wt_rsp_valid & wt_local_data_cnt[0]; +//: assign wt_cbuf_wr_vld_w = wt_rsp_valid & wt_local_data_cnt[1]; +//: assign wt_local_data_w = dma_rd_rsp_mask[1] ? dma_rsp_data_p1 : dma_rsp_data_p0; +//: assign wt_cbuf_wr_data_ori_w = wt_local_data_vld ? {dma_rsp_data_p0, wt_local_data} : dma_rd_rsp_data; +//: ); +//: } elsif($mask == 4) { +//: print qq( +//: assign wt_local_data_vld_w = |wt_local_data_cnt[1:0]; +//: assign wt_local_data_reg_en = wt_rsp_valid & wt_local_data_vld_w; +//: assign wt_cbuf_wr_vld_w = wt_rsp_valid & wt_local_data_cnt[2]; +//: assign wt_local_data_w = dma_rd_rsp_mask[3] ? dma_rd_rsp_data :// +//: dma_rd_rsp_mask[2] ? {dma_rsp_data_p2, dma_rsp_data_p1, dma_rsp_data_p0}: +//: dma_rd_rsp_mask[1] ? {dma_rsp_data_p1, dma_rsp_data_p0} : dma_rsp_data_p0; +//: assign wt_cbuf_wr_data_ori_w = wt_local_data_vld ? {dma_rsp_data_p0, wt_local_data} : dma_rd_rsp_data;// +//: ); +//: } +assign wt_cbuf_wr_idx_inc = wt_cbuf_wr_idx + 1'b1; +assign wt_cbuf_wr_idx_set = (layer_st & ~(|wt_cbuf_wr_idx)); +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $k; +//: if($dmaif < $atmc) { +//: $k = int(log(int($atmc/$dmaif))/log(2)); +//: } else { +//: $k = 0; +//: } +//: +//: my $bank_depth_bits = int( log(512)/log(2) + ${k}); +//: print qq( +//: assign wt_cbuf_wr_idx_wrap = (wt_cbuf_wr_idx_inc == {2'd0, weight_bank_end, ${bank_depth_bits}'b0}); +//: assign wt_cbuf_wr_idx_w = (clear_all | wt_cbuf_wr_idx_set | wt_cbuf_wr_idx_wrap) ? {2'd0, data_bank_w, ${bank_depth_bits}'b0} : wt_cbuf_wr_idx_inc[(1 + 16 ) -1:0]; +//: ); +//assign wt_cbuf_wr_data_w = nan_pass ? wt_cbuf_wr_data_ori_w : (wt_cbuf_wr_data_ori_w & wt_nan_mask); +assign wt_cbuf_wr_data_w = wt_cbuf_wr_data_ori_w; +//: &eperl::flop("-nodeclare -norst -en \"wt_local_data_reg_en\" -d \"wt_local_data_w\" -q wt_local_data"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_rsp_valid\" -d \"wt_local_data_vld_w\" -q wt_local_data_vld"); +//: &eperl::flop("-nodeclare -rval \"{17{1'b0}}\" -en \"wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w\" -d \"wt_cbuf_wr_idx_w\" -q wt_cbuf_wr_idx"); +//////////////////////////////////////////////////////////////////////// +// weight buffer flushing logic // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// Non-SLCG clock domain // +//////////////////////////////////////////////////////////////////////// +assign {mon_wt_cbuf_flush_idx_w, wt_cbuf_flush_idx_w} = wt_cbuf_flush_idx + 1'b1; +//: my $bank_entry = 32 * 512; +//: my $bank_entry_bw = int( log( $bank_entry)/log(2) ); +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $k; +//: if($dmaif < $atmc) { +//: $k = int(log(int($atmc/$dmaif))/log(2)); +//: } else { +//: $k = 0; +//: } +//: print qq( +//: assign wt_cbuf_flush_vld_w = ~wt_cbuf_flush_idx[${bank_entry_bw}+$k-1];//max value = half bank entry * 2^$k +//: assign dp2reg_wt_flush_done = wt_cbuf_flush_idx[${bank_entry_bw}+$k-1]; +//: ); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{18{1'b0}}\" -en \"wt_cbuf_flush_vld_w\" -d \"wt_cbuf_flush_idx_w\" -q wt_cbuf_flush_idx"); +//////////////////////////////////////////////////////////////////////// +// WT and WMB write to convolution buffer // +//////////////////////////////////////////////////////////////////////// +assign cdma2buf_wt_wr_en_w = wt_cbuf_wr_vld_w | wt_cbuf_flush_vld_w; +//: my $dmaif=64; +//: my $atmc=8*8; +//: my $half_bank_entry_num = 32 * 512 / 2; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: assign cdma2buf_wt_wr_addr_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx[(1 + 16 ) -1:${k}] : +//: ${half_bank_entry_num} + wt_cbuf_flush_idx[16:${k}]; +//: assign cdma2buf_wt_wr_sel_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx[${k}-1:0] : +//: wt_cbuf_flush_idx[${k}-1:0]; +//: assign cdma2buf_wt_wr_data_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_data_w : +//: 0; +//: ); +//: +//: my $dmanum = int($atmc/$dmaif); +//: foreach my $s (0..${dmanum}-1) { +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_sel_w===${k}'d${s}\" -q cdma2buf_wt_wr_sel[${s}]"); +//: } +//: ## &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_sel_w\" -q cdma2buf_wt_wr_sel"); +//: } elsif($dmaif > $atmc) { +//: } else { +//: print qq( +//: assign cdma2buf_wt_wr_addr_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_idx : ${half_bank_entry_num} + wt_cbuf_flush_idx[16:0]; +//: assign cdma2buf_wt_wr_data_w = wt_cbuf_wr_vld_w ? wt_cbuf_wr_data_w : 0; +//: ); +//: } +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"cdma2buf_wt_wr_en_w\" -q cdma2buf_wt_wr_en"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_addr_w\" -q cdma2buf_wt_wr_addr"); +//////////////////////////////////////////////////////////////////////// +// Non-SLCG clock domain end // +//////////////////////////////////////////////////////////////////////// +//: my $dmaif=64; +//: &eperl::flop("-nodeclare -rval \"{${dmaif}{1'b0}}\" -en \"cdma2buf_wt_wr_en_w\" -d \"cdma2buf_wt_wr_data_w\" -q cdma2buf_wt_wr_data"); +assign dp2reg_nan_weight_num = 32'b0; +assign dp2reg_inf_weight_num = 32'b0; +//////////////////////////////////////////////////////////////////////// +// WT data status monitor // +//////////////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +//sc2cdma_wt_kernels are useless +//retiming +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"sc2cdma_wt_updt\" -q sc_wt_updt"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{15{1'b0}}\" -en \"sc2cdma_wt_updt\" -d \"sc2cdma_wt_entries\" -q sc_wt_entries"); +//cation: the basic unit of data_stored, data_onfly and data_avl is atomic_m bytes, 32 bytes in Xavier +assign wt_data_onfly_add = (wt_req_reg_en_d2 & wt_req_stage_vld_d2 & ~wt_req_done_d2) ? wt_req_size_d2 : 4'b0; +//atom_m num per cbuf write, =dmaif/atom_m +//: my $dmaif = (64 / 8); +//: my $atmc=8; +//: my $atmm = 8; +//: my $atmm_dmaif = int($dmaif / $atmm); +//: my $atmm_atmc = int($atmc / $atmm); +//: print qq( +//: assign wt_data_onfly_sub = wt_cbuf_wr_vld_w ? 3'd${atmm_dmaif} : 3'b0; +//: ); +//: if($atmm_atmc == 4) { +//: print qq( +//: assign wt_data_stored_sub = status_update ? {incr_wt_entries_w, 2'd0} : 17'b0; +//: assign wt_data_avl_sub = sc_wt_updt ? {sc_wt_entries, 2'b0} : 17'b0; +//: ); +//: } elsif($atmm_atmc == 2) { +//: print qq( +//: assign wt_data_stored_sub = status_update ? {1'b0,incr_wt_entries_w, 1'd0} : 17'b0; +//: assign wt_data_avl_sub = sc_wt_updt ? {1'b0,sc_wt_entries, 1'b0} : 17'b0; +//: ); +//: } elsif($atmm_atmc == 1) { +//: print qq( +//: assign wt_data_stored_sub = status_update ? {2'b0,incr_wt_entries_w} : 17'b0; +//: assign wt_data_avl_sub = sc_wt_updt ? {2'b0,sc_wt_entries} : 17'b0; +//: ); +//: } +assign {mon_wt_data_onfly_w, wt_data_onfly_w} = wt_data_onfly + wt_data_onfly_add - wt_data_onfly_sub; +//assign wt_data_stored_sub = status_update ? {incr_wt_entries_w, 2'b0} : 14'b0; +assign {mon_wt_data_stored_w, wt_data_stored_w} = wt_data_stored + wt_data_onfly_sub - wt_data_stored_sub; +//assign wt_data_avl_sub = sc_wt_updt ? {sc_wt_entries, 2'b0} : 14'b0; +assign {mon_wt_data_avl_w, wt_data_avl_w} = (clear_all) ? 17'b0 : wt_data_avl + wt_data_stored_sub - wt_data_avl_sub; +assign wt_data_onfly_reg_en = ((wt_req_reg_en_d2 & wt_req_stage_vld_d2) | wt_cbuf_wr_vld_w); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{14{1'b0}}\" -en \"wt_data_onfly_reg_en\" -d \"wt_data_onfly_w\" -q wt_data_onfly"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"wt_cbuf_wr_vld_w | status_update\" -d \"wt_data_stored_w\" -q wt_data_stored"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{17{1'b0}}\" -en \"status_update | sc_wt_updt | clear_all\" -d \"wt_data_avl_w\" -q wt_data_avl"); +//////////////////////////////////////////////////////////////////////// +// status update logic // +//////////////////////////////////////////////////////////////////////// +assign status_group_cnt_inc = status_group_cnt + 1'b1; +assign status_last_group = (status_group_cnt_inc == group); +assign status_group_cnt_w = layer_st ? 12'b0 : status_group_cnt_inc; +assign status_done_w = layer_st ? 1'b0 : + status_last_group ? 1'b1 : status_done; +//: my $atmk = 8; +//: my $atmkbw = int(log($atmk) / log(2)); +//: print qq( +//: assign normal_bpg = {2'd0, byte_per_kernel, ${atmkbw}'b0}; +//: ); +assign {mon_wt_required_bytes_w, + wt_required_bytes_w} = layer_st ? 33'b0 : + status_last_group ? {1'b0, reg2dp_weight_bytes} : + pre_wt_required_bytes + normal_bpg; +assign wt_required_en = ~required_valid & required_valid_w; +assign pre_wt_required_bytes_w = (layer_st) ? 32'b0 : wt_required_bytes; +assign required_valid_w = is_running & ~status_update; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"required_valid_w\" -q required_valid"); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"layer_st | wt_required_en\" -d \"wt_required_bytes_w\" -q wt_required_bytes"); +//////// caution: one in fetched_cnt refers to 64 bytes //////// +assign {mon_wt_fetched_cnt_inc, wt_fetched_cnt_inc} = wt_fetched_cnt + 1'b1; +assign wt_fetched_cnt_w = layer_st ? 26'b0 : wt_fetched_cnt_inc; +//: my $m = int(log(8)/log(2)); +//: my $dmaif=64/8; ##byte number per dmaif tx +//: my $k = int(log($dmaif)/log(2)); +//: my $atmc=8 * 8; +//: my $dmaifbw=64; +//: if($atmc > $dmaifbw) { +//: my $j = int( log( ${atmc}/${dmaifbw} )/log(2) ); +//: print qq( +//: assign wt_satisfied = is_running & ({wt_fetched_cnt, ${k}'b0} >= wt_required_bytes) & ~(|wt_fetched_cnt[${j}-1:0]); +//: ); +//: } else { +//: print qq( +//: assign wt_satisfied = is_running & ({3'd0, wt_fetched_cnt, ${k}'b0} >= wt_required_bytes); // wt_fetched_cnt[0] +//: ); +//: } +//assign wt_satisfied = is_running & ({wt_fetched_cnt, 6'b0} >= wt_required_bytes) & ~wt_fetched_cnt[0]; +assign status_update = (~required_valid) ? 1'b0 : wt_satisfied; +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st | status_update\" -d \"status_group_cnt_w\" -q status_group_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st | status_update\" -d \"status_done_w\" -q status_done"); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"layer_st | status_update\" -d \"pre_wt_required_bytes_w\" -q pre_wt_required_bytes"); +//: &eperl::flop("-nodeclare -rval \"{26{1'b0}}\" -en \"layer_st | wt_cbuf_wr_vld_w\" -d \"wt_fetched_cnt_w\" -q wt_fetched_cnt"); +//////////////////////////////////////////////////////////////////////// +// avaliable kernels monitor // +//////////////////////////////////////////////////////////////////////// +// Avaliable kernel size is useless here. Discard the code; +//////////////////////////////////////////////////////////////////////// +// CDMA WT communicate to CSC // +//////////////////////////////////////////////////////////////////////// +assign pre_wt_fetched_cnt_w = status_last_group ? 26'b0 : wt_fetched_cnt; +assign {mon_incr_wt_cnt, incr_wt_cnt} = wt_fetched_cnt - pre_wt_fetched_cnt; +// dmaif vs atom_c +//: my $dmaif=64/8; +//: my $atmc=8; +//: if($dmaif == $atmc){ +//: print qq( +//: assign incr_wt_entries_w = incr_wt_cnt[14:0]; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log($dmaif/$atmc)/log(2)); +//: print qq( +//: assign incr_wt_entries_w = {incr_wt_cnt[12:0],{${k}{1'b0}}}; +//: ); +//: } elsif($dmaif < $atmc) { +//: my $k = int(log($atmc/$dmaif)/log(2)); +//: print qq( +//: assign incr_wt_entries_w = {{(2+${k}){1'b0}},incr_wt_cnt[12:${k}]}; +//: ); +//: } +//assign incr_wt_entries_w = incr_wt_cnt[12 :1]; +//: my $atmk = 8; +//: my $atmkbw = int(log($atmk)/log(2)); +//: print qq( +//: assign incr_wt_kernels_w = (~status_last_group) ? 6'd${atmk} : (reg2dp_weight_kernel[${atmkbw}-1:0] + 1'b1); +//: ); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"status_update\" -q incr_wt_updt"); +//: &eperl::flop("-nodeclare -rval \"{26{1'b0}}\" -en \"status_update\" -d \"pre_wt_fetched_cnt_w\" -q pre_wt_fetched_cnt"); +//: &eperl::flop("-nodeclare -rval \"{15{1'b0}}\" -en \"status_update\" -d \"incr_wt_entries_w\" -q incr_wt_entries"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"status_update\" -d \"incr_wt_kernels_w\" -q incr_wt_kernels"); +//: my $i; +//: my $j; +//: my $k; +//: my $name; +//: my $wid; +//: my $cbuf_wr_delay = 3; +//: my @list = ("wt_kernels", "wt_entries"); +//: my @width = (6, 15); +//: +//: for($i = 0; $i < @list; $i ++) { +//: $name = $list[$i]; +//: print "assign incr_${name}_d0 = incr_${name};\n"; +//: } +//: print "assign incr_wt_updt_d0 = incr_wt_updt;\n"; +//: print "\n\n"; +//: +//: for($j = 1; $j <= $cbuf_wr_delay; $j ++) { +//: $k = $j - 1; +//: for($i = 0; $i < @list; $i ++) { +//: $name = $list[$i]; +//: $wid = $width[$i]; +//: &eperl::flop("-wid ${wid} -rval \"'b0\" -en \"incr_wt_updt_d${k}\" -d \"incr_${name}_d${k}\" -q incr_${name}_d${j}"); +//: } +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"incr_wt_updt_d${k}\" -q incr_wt_updt_d${j}"); +//: } +//: print "\n\n"; +//: +//: $j = $cbuf_wr_delay; +//: print "assign cdma2sc_wt_kernels[5:0] = incr_wt_kernels_d${j};\n"; +//: print "assign cdma2sc_wt_entries = incr_wt_entries_d${j};\n"; +//: print "assign cdma2sc_wmb_entries = 12'b0; \n"; +//: print "assign cdma2sc_wt_updt = incr_wt_updt_d${j};\n"; +assign cdma2sc_wt_kernels[13:6] = 8'b0; +`ifndef SYNTHESIS +assign dbg_wt_kernel_bytes_w[31:0] = layer_st ? 32'b0 : wt_required_bytes_w - wt_required_bytes; +//assign dbg_full_weight = (reg2dp_weight_bytes <= {weight_bank, 8'h0}); +assign dbg_full_weight = (reg2dp_weight_bytes <= {weight_bank, 9'h0}); +//: &eperl::flop("-nodeclare -rval \"{32{1'b0}}\" -en \"layer_st | wt_required_en\" -d \"dbg_wt_kernel_bytes_w\" -q dbg_wt_kernel_bytes"); +`endif +//////////////////////////////////////////////////////////////////////// +// performance counting register // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_stall_inc <= 1'b0; + end else begin + wt_rd_stall_inc <= dma_rd_req_vld & ~dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_stall_clr <= 1'b0; + end else begin + wt_rd_stall_clr <= status2dma_fsm_switch & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_stall_cen <= 1'b0; + end else begin + wt_rd_stall_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +assign dp2reg_wt_rd_stall_dec = 1'b0; +// stl adv logic +always @(*) begin + stl_adv = wt_rd_stall_inc ^ dp2reg_wt_rd_stall_dec; +end +// stl cnt logic +always @(*) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wt_rd_stall_inc && !dp2reg_wt_rd_stall_dec)? stl_cnt_inc : (!wt_rd_stall_inc && dp2reg_wt_rd_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (wt_rd_stall_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (wt_rd_stall_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @(*) begin + dp2reg_wt_rd_stall[31:0] = stl_cnt_cur[31:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_inc <= 1'b0; + end else begin + wt_rd_latency_inc <= dma_rd_req_vld & dma_rd_req_rdy & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_dec <= 1'b0; + end else begin + wt_rd_latency_dec <= dma_rsp_fifo_ready & reg2dp_dma_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_clr <= 1'b0; + end else begin + wt_rd_latency_clr <= status2dma_fsm_switch; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rd_latency_cen <= 1'b0; + end else begin + wt_rd_latency_cen <= reg2dp_op_en & reg2dp_dma_en; + end +end +// +assign ltc_1_inc = (outs_dp2reg_wt_rd_latency!=511) & wt_rd_latency_inc; +assign ltc_1_dec = (outs_dp2reg_wt_rd_latency!=511) & wt_rd_latency_dec; +// ltc_1 adv logic +always @(*) begin + ltc_1_adv = ltc_1_inc ^ ltc_1_dec; +end +// ltc_1 cnt logic +always @(*) begin +// VCS sop_coverage_off start + ltc_1_cnt_ext[10:0] = {1'b0, 1'b0, ltc_1_cnt_cur}; + ltc_1_cnt_inc[10:0] = ltc_1_cnt_cur + 1'b1; // spyglass disable W164b + ltc_1_cnt_dec[10:0] = ltc_1_cnt_cur - 1'b1; // spyglass disable W164b + ltc_1_cnt_mod[10:0] = (ltc_1_inc && !ltc_1_dec)? ltc_1_cnt_inc : (!ltc_1_inc && ltc_1_dec)? ltc_1_cnt_dec : ltc_1_cnt_ext; + ltc_1_cnt_new[10:0] = (ltc_1_adv)? ltc_1_cnt_mod[10:0] : ltc_1_cnt_ext[10:0]; + ltc_1_cnt_nxt[10:0] = (wt_rd_latency_clr)? 11'd0 : ltc_1_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// ltc_1 flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ltc_1_cnt_cur[8:0] <= 0; + end else begin + if (wt_rd_latency_cen) begin + ltc_1_cnt_cur[8:0] <= ltc_1_cnt_nxt[8:0]; + end + end +end +// ltc_1 output logic +always @(*) begin + outs_dp2reg_wt_rd_latency[8:0] = ltc_1_cnt_cur[8:0]; +end +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property cdma_wt__cbuf_idx_wrap__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w) & wt_cbuf_wr_idx_wrap); + endproperty +// Cover 0 : "((wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w) & wt_cbuf_wr_idx_wrap)" + FUNCPOINT_cdma_wt__cbuf_idx_wrap__0_COV : cover property (cdma_wt__cbuf_idx_wrap__0_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,2,0,"No Xs allowed on cur_state") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, cur_state); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | is_running))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_end))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_req_reg_en_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_req_reg_en_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_req_reg_en_d2))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dbg_src_wr_ptr_en & ~dbg_src_wr_ptr))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dbg_src_wr_ptr_en & dbg_src_wr_ptr))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dma_rd_rsp_vld & dma_rd_rsp_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_rsp_valid))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wt_cbuf_wr_idx_set | clear_all | wt_cbuf_wr_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(wt_cbuf_flush_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cdma2buf_wt_wr_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(cdma2buf_wt_wr_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cdma2buf_wt_wr_en_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(nan_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(inf_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(sc2cdma_wt_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(sc2cdma_wt_updt))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(wt_data_onfly_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(wt_cbuf_wr_vld_w | status_update))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_ng_clk, `ASSERT_RESET, 1'd1, (^(status_update | sc_wt_updt | clear_all))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(wgs_data_onfly_reg_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | wt_required_en))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | status_update))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_st | wt_cbuf_wr_vld_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(status_update))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(incr_wt_updt_d0))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(incr_wt_updt_d1))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(incr_wt_updt_d2))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Data banks is more than 15!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && (reg2dp_data_bank == 4'hf))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Weight banks is more than 15!") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && (reg2dp_weight_bank == 4'hf))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Sum of data & weight banks is more than 16 when weight uncompressed") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && ~is_compressed && (weight_bank_end_w > 16))); // spyglass disable W504 SelfDeterminedExpr-ML +// nv_assert_never #(0,0,"Config error! Sum of data & weight banks is more than 15 when weight compressed!") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && is_compressed && (weight_bank_end_w > 15))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_req_burst_cnt_dec is overflow") zzz_assert_never_19x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en && mon_wt_req_burst_cnt_dec)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! FSM done when wt fetch is not!") zzz_assert_never_29x (nvdla_core_clk, `ASSERT_RESET, (is_running & ~is_nxt_running & ~wt_req_done_d3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_onfly is not zero when idle") zzz_assert_never_30x (nvdla_core_clk, `ASSERT_RESET, (~is_running && (|wt_data_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_stored is not zero when idle") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, (~is_running && (|wt_data_stored))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response fifo pop error") zzz_assert_never_56x (nvdla_core_clk, `ASSERT_RESET, (dma_rsp_fifo_ready & ~dma_rsp_fifo_req)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"response size mismatch") zzz_assert_never_57x (nvdla_core_clk, `ASSERT_RESET, (dma_rd_rsp_vld & dma_rd_rsp_rdy & (dma_rsp_size_cnt_inc > dma_rsp_size))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is overflow") zzz_assert_never_58x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & mon_dma_rsp_size_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! dma_rsp_size_cnt_inc is out of range") zzz_assert_never_59x (nvdla_core_clk, `ASSERT_RESET, (reg2dp_op_en & (dma_rsp_size_cnt_inc > 8'h8))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"WT and FLUSH write hazard") zzz_assert_never_71x (nvdla_core_clk, `ASSERT_RESET, (wt_cbuf_wr_vld_w & wt_cbuf_flush_vld_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_onfly_w is overflow") zzz_assert_never_80x (nvdla_core_ng_clk, `ASSERT_RESET, (reg2dp_op_en & mon_wt_data_onfly_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_stored_w is overflow") zzz_assert_never_81x (nvdla_core_ng_clk, `ASSERT_RESET, (reg2dp_op_en & mon_wt_data_stored_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_onfly is not zero when idle") zzz_assert_never_82x (nvdla_core_ng_clk, `ASSERT_RESET, (~is_running & (|wt_data_onfly))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_stored is not zero when idle") zzz_assert_never_83x (nvdla_core_ng_clk, `ASSERT_RESET, (~is_running & (|wt_data_stored))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_data_avl_w is overflow") zzz_assert_never_84x (nvdla_core_ng_clk, `ASSERT_RESET, (reg2dp_op_en && mon_wt_data_avl_w)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! wt_fetched_cnt_w is overflow") zzz_assert_never_103x (nvdla_core_clk, `ASSERT_RESET, ((layer_st | wt_cbuf_wr_vld_w) & mon_wt_fetched_cnt_inc)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Config error! Run out of weight buffer: uncompressed weight!") zzz_assert_never_121x (nvdla_core_clk, `ASSERT_RESET, (is_running & ~reg2dp_skip_weight_rls & ~dbg_full_weight & ~is_compressed & ~status_done & ((dbg_wt_kernel_bytes + 128) > {weight_bank, 15'b0}))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Config error! Run out of weight buffer: full weight!") zzz_assert_never_124x (nvdla_core_clk, `ASSERT_RESET, (is_running & reg2dp_skip_weight_rls & ~dbg_full_weight)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Weight output update with zero kernels") zzz_assert_never_126x (nvdla_core_clk, `ASSERT_RESET, (cdma2sc_wt_updt & ~(|cdma2sc_wt_kernels))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_127x (nvdla_core_clk, `ASSERT_RESET, (ltc_1_cnt_nxt > 511 && wt_rd_latency_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDMA_wt +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDMA_WT_8ATMM_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , atmm8_wr_prdy + , atmm8_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , atmm8_wr_pause +`endif + , atmm8_wr_pd + , atmm8_rd_prdy + , atmm8_rd_pvld + , atmm8_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output atmm8_wr_prdy; +input atmm8_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input atmm8_wr_pause; +`endif +input [64:0] atmm8_wr_pd; +input atmm8_rd_prdy; +output atmm8_rd_pvld; +output [64:0] atmm8_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg atmm8_wr_busy_int; // copy for internal use +assign atmm8_wr_prdy = !atmm8_wr_busy_int; +assign wr_reserving = atmm8_wr_pvld && !atmm8_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [3:0] atmm8_wr_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? atmm8_wr_count : (atmm8_wr_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (atmm8_wr_count + 1'd1) : atmm8_wr_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire atmm8_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check atmm8_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || atmm8_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire atmm8_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check atmm8_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_wr_busy_int <= 1'b0; + atmm8_wr_count <= 4'd0; + end else begin + atmm8_wr_busy_int <= atmm8_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + atmm8_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + atmm8_wr_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as atmm8_wr_pvld +// +// RAM +// +reg [2:0] atmm8_wr_adr; // current write address +wire [2:0] atmm8_rd_adr_p; // read address to use for ram +wire [64:0] atmm8_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_8x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( atmm8_wr_adr ) + , .we ( wr_pushing ) + , .di ( atmm8_wr_pd ) + , .ra ( atmm8_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( atmm8_rd_pd_p ) + , .ore ( ore ) + ); +// next atmm8_wr_adr if wr_pushing=1 +wire [2:0] wr_adr_next = atmm8_wr_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + atmm8_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + atmm8_wr_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [2:0] atmm8_rd_adr; // current read address +// next read address +wire [2:0] rd_adr_next = atmm8_rd_adr + 1'd1; // spyglass disable W484 +assign atmm8_rd_adr_p = rd_popping ? rd_adr_next : atmm8_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + atmm8_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + atmm8_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg atmm8_rd_pvld_p; // data out of fifo is valid +reg atmm8_rd_pvld_int; // internal copy of atmm8_rd_pvld +assign atmm8_rd_pvld = atmm8_rd_pvld_int; +assign rd_popping = atmm8_rd_pvld_p && !(atmm8_rd_pvld_int && !atmm8_rd_prdy); +reg [3:0] atmm8_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? atmm8_rd_count_p : + (atmm8_rd_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (atmm8_rd_count_p + 1'd1) : + atmm8_rd_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~atmm8_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_rd_count_p <= 4'd0; + atmm8_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + atmm8_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + atmm8_rd_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + atmm8_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + atmm8_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (atmm8_rd_pvld_p || (atmm8_rd_pvld_int && !atmm8_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + atmm8_rd_pvld_int <= 1'b0; + end else begin + atmm8_rd_pvld_int <= rd_req_next; + end +end +assign atmm8_rd_pd = atmm8_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (atmm8_wr_pvld && !atmm8_wr_busy_int) || (atmm8_wr_busy_int != atmm8_wr_busy_next)) || (rd_pushing || rd_popping || (atmm8_rd_pvld_int && atmm8_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDMA_WT_8ATMM_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( atmm8_wr_pvld && !(!atmm8_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, atmm8_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDMA_WT_8ATMM_fifo") true +// synopsys dc_script_end +//| &Attachment -no_warn EndModulePrepend; +//| _attach_EndModulePrepend_1; +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +//| _attach_EndModulePrepend_2; +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDMA_WT_8ATMM_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.swl b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.swl new file mode 100644 index 0000000..d05ac49 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.swl @@ -0,0 +1,2 @@ +waive -regexp -file NV_NVDLA_CDMA_wt.v -msg ".*width 17 should match right expression.*" -rule W362 +waive -regexp -file NV_NVDLA_CDMA_wt.v -msg ".*should be greater than rhs width 17.*" -rule W484 diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.swl.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.swl.vcp new file mode 100644 index 0000000..d05ac49 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.swl.vcp @@ -0,0 +1,2 @@ +waive -regexp -file NV_NVDLA_CDMA_wt.v -msg ".*width 17 should match right expression.*" -rule W362 +waive -regexp -file NV_NVDLA_CDMA_wt.v -msg ".*should be greater than rhs width 17.*" -rule W484 diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.v b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.v new file mode 100644 index 0000000..fde9f5b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.v @@ -0,0 +1,1416 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_cdma ( + cdma_dat2mcif_rd_req_ready + ,cdma_wt2mcif_rd_req_ready + ,csb2cdma_req_pd + ,csb2cdma_req_pvld + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,mcif2cdma_dat_rd_rsp_pd + ,mcif2cdma_dat_rd_rsp_valid + ,mcif2cdma_wt_rd_rsp_pd + ,mcif2cdma_wt_rd_rsp_valid + ,nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd + ,sc2cdma_dat_entries + ,sc2cdma_dat_pending_req + ,sc2cdma_dat_slices + ,sc2cdma_dat_updt + ,sc2cdma_wmb_entries + ,sc2cdma_wt_entries + ,sc2cdma_wt_kernels + ,sc2cdma_wt_pending_req + ,sc2cdma_wt_updt + ,tmc2slcg_disable_clock_gating + ,cdma2buf_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,cdma2buf_dat_wr_sel +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_dat_wr_addr${i} +//: ,cdma2buf_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,cdma2buf_dat_wr_addr +,cdma2buf_dat_wr_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,cdma2buf_dat_wr_addr +//,cdma2buf_dat_wr_data +//,cdma2buf_dat_wr_hsel + ,cdma2buf_wt_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,cdma2buf_wt_wr_sel +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_wt_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_wt_wr_addr${i} +//: ,cdma2buf_wt_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,cdma2buf_wt_wr_addr +,cdma2buf_wt_wr_data + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,cdma2buf_wt_wr_addr +//,cdma2buf_wt_wr_data +//,cdma2buf_wt_wr_hsel + ,cdma2csb_resp_pd + ,cdma2csb_resp_valid + ,cdma2sc_dat_entries + ,cdma2sc_dat_pending_ack + ,cdma2sc_dat_slices + ,cdma2sc_dat_updt + ,cdma2sc_wmb_entries + ,cdma2sc_wt_entries + ,cdma2sc_wt_kernels + ,cdma2sc_wt_pending_ack + ,cdma2sc_wt_updt + ,cdma_dat2glb_done_intr_pd + ,cdma_dat2mcif_rd_req_pd + ,cdma_dat2mcif_rd_req_valid + ,cdma_wt2glb_done_intr_pd + ,cdma_wt2mcif_rd_req_pd + ,cdma_wt2mcif_rd_req_valid + ,csb2cdma_req_prdy + ,mcif2cdma_dat_rd_rsp_ready + ,mcif2cdma_wt_rd_rsp_ready + ); +/////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +output cdma2csb_resp_valid; +output [33:0] cdma2csb_resp_pd; +input csb2cdma_req_pvld; +output csb2cdma_req_prdy; +input [62:0] csb2cdma_req_pd; +output cdma2buf_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_sel; +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] cdma2buf_dat_wr_addr; +output [64-1:0] cdma2buf_dat_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// output [11:0] cdma2buf_dat_wr_addr; +// output [1:0] cdma2buf_dat_wr_hsel; +// output [1023:0] cdma2buf_dat_wr_data; +output cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_sel ; +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] cdma2buf_wt_wr_addr; +output [64-1:0] cdma2buf_wt_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//output [11:0] cdma2buf_wt_wr_addr; +//output cdma2buf_wt_wr_hsel; +//output [511:0] cdma2buf_wt_wr_data; +output [1:0] cdma_dat2glb_done_intr_pd; +output [1:0] cdma_wt2glb_done_intr_pd; +output cdma_dat2mcif_rd_req_valid; +input cdma_dat2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] cdma_dat2mcif_rd_req_pd; +input mcif2cdma_dat_rd_rsp_valid; +output mcif2cdma_dat_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2cdma_dat_rd_rsp_pd; +output cdma_wt2mcif_rd_req_valid; +input cdma_wt2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] cdma_wt2mcif_rd_req_pd; +input mcif2cdma_wt_rd_rsp_valid; +output mcif2cdma_wt_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2cdma_wt_rd_rsp_pd; +input sc2cdma_dat_pending_req; +input sc2cdma_wt_pending_req; +output cdma2sc_dat_pending_ack; +output cdma2sc_wt_pending_ack; +output cdma2sc_dat_updt; +output [14:0] cdma2sc_dat_entries; +output [13:0] cdma2sc_dat_slices; +input sc2cdma_dat_updt; +input [14:0] sc2cdma_dat_entries; +input [13:0] sc2cdma_dat_slices; +output cdma2sc_wt_updt; +output [13:0] cdma2sc_wt_kernels; +output [14:0] cdma2sc_wt_entries; +output [8:0] cdma2sc_wmb_entries; +input sc2cdma_wt_updt; +input [13:0] sc2cdma_wt_kernels; +input [14:0] sc2cdma_wt_entries; +input [8:0] sc2cdma_wmb_entries; +input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +/////////////////////////////////////////////////////////////////////////// +// +wire [11:0] cdma2sc_wmb_entries_f; +assign cdma2sc_wmb_entries = cdma2sc_wmb_entries_f[8:0]; +// +wire dc2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: wire [${k}-1:0] dc2cvt_dat_wr_sel; +//: wire [16:0] dc2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] dc2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] dc2cvt_dat_wr_addr${i}; +//: wire [${dmaif}-1:0] dc2cvt_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] dc2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [16:0] dc2cvt_dat_wr_addr; +wire [64-1:0] dc2cvt_dat_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [16:0] dc2cvt_dat_wr_addr; +//wire [511:0] dc2cvt_dat_wr_data; +//wire dc2cvt_dat_wr_hsel; +wire [11:0] dc2cvt_dat_wr_info_pd; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire dc2sbuf_p${i}_wr_en; +//: wire [7:0] dc2sbuf_p${i}_wr_addr; +//: wire [${atmm}-1:0] dc2sbuf_p${i}_wr_data; +//: wire dc2sbuf_p${i}_rd_en; +//: wire [7:0] dc2sbuf_p${i}_rd_addr; +//: wire [${atmm}-1:0] dc2sbuf_p${i}_rd_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire dc2sbuf_p0_wr_en; +wire [7:0] dc2sbuf_p0_wr_addr; +wire [64-1:0] dc2sbuf_p0_wr_data; +wire dc2sbuf_p0_rd_en; +wire [7:0] dc2sbuf_p0_rd_addr; +wire [64-1:0] dc2sbuf_p0_rd_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [14:0] dc2status_dat_entries; +wire [13:0] dc2status_dat_slices; +wire dc2status_dat_updt; +wire [1:0] dc2status_state; +wire [( 32 + 15 )-1:0] dc_dat2mcif_rd_req_pd; +wire dc_dat2mcif_rd_req_ready; +wire dc_dat2mcif_rd_req_valid; +wire dp2reg_consumer; +wire dp2reg_dat_flush_done; +wire [31:0] dp2reg_dc_rd_latency; +wire [31:0] dp2reg_dc_rd_stall; +wire dp2reg_done; +wire [31:0] dp2reg_img_rd_latency; +wire [31:0] dp2reg_img_rd_stall; +wire [31:0] dp2reg_inf_data_num; +wire [31:0] dp2reg_inf_weight_num; +wire [31:0] dp2reg_nan_data_num; +wire [31:0] dp2reg_nan_weight_num; +wire [31:0] dp2reg_wg_rd_latency; +wire [31:0] dp2reg_wg_rd_stall; +wire dp2reg_wt_flush_done; +wire [31:0] dp2reg_wt_rd_latency; +wire [31:0] dp2reg_wt_rd_stall; +wire img2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: wire [${k}-1:0] img2cvt_dat_wr_sel; +//: wire [16:0] img2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] img2cvt_dat_wr_data; +//: wire [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: wire [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] img2cvt_dat_wr_addr${i}; +//: wire [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: wire [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: wire [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] img2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] img2cvt_dat_wr_data; +//: wire [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: wire [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [16:0] img2cvt_dat_wr_addr; +wire [64-1:0] img2cvt_dat_wr_data; +wire [8*16-1:0] img2cvt_mn_wr_data; +wire [8-1:0] img2cvt_dat_wr_pad_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [11:0] img2cvt_dat_wr_addr; +//wire [1023:0] img2cvt_dat_wr_data; +//wire img2cvt_dat_wr_hsel; +wire [11:0] img2cvt_dat_wr_info_pd; +//wire [127:0] img2cvt_dat_wr_pad_mask; +//wire [1023:0] img2cvt_mn_wr_data; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire img2sbuf_p${i}_wr_en ; +//: wire [7:0] img2sbuf_p${i}_wr_addr; +//: wire [${atmm}-1:0] img2sbuf_p${i}_wr_data; +//: wire img2sbuf_p${i}_rd_en; +//: wire [7:0] img2sbuf_p${i}_rd_addr; +//: wire [${atmm}-1:0] img2sbuf_p${i}_rd_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire img2sbuf_p0_wr_en ; +wire [7:0] img2sbuf_p0_wr_addr; +wire [64-1:0] img2sbuf_p0_wr_data; +wire img2sbuf_p0_rd_en; +wire [7:0] img2sbuf_p0_rd_addr; +wire [64-1:0] img2sbuf_p0_rd_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [7:0] img2sbuf_p0_rd_addr; +//wire [255:0] img2sbuf_p0_rd_data; +//wire img2sbuf_p0_rd_en; +//wire [7:0] img2sbuf_p0_wr_addr; +//wire [255:0] img2sbuf_p0_wr_data; +//wire img2sbuf_p0_wr_en; +//wire [7:0] img2sbuf_p1_rd_addr; +//wire [255:0] img2sbuf_p1_rd_data; +//wire [8*8 -1:0] img2sbuf_p1_rd_data; +//wire img2sbuf_p1_rd_en; +//wire [7:0] img2sbuf_p1_wr_addr; +//wire [255:0] img2sbuf_p1_wr_data; +//wire img2sbuf_p1_wr_en; +wire [14:0] img2status_dat_entries; +wire [13:0] img2status_dat_slices; +wire img2status_dat_updt; +wire [1:0] img2status_state; +wire [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +wire img_dat2mcif_rd_req_ready; +wire img_dat2mcif_rd_req_valid; +wire [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd; +wire mcif2dc_dat_rd_rsp_ready; +wire mcif2dc_dat_rd_rsp_valid; +wire [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +wire mcif2img_dat_rd_rsp_ready; +wire mcif2img_dat_rd_rsp_valid; +wire nvdla_hls_gated_clk_cvt; +wire nvdla_op_gated_clk_buffer; +wire nvdla_op_gated_clk_cvt; +wire nvdla_op_gated_clk_dc; +wire nvdla_op_gated_clk_img; +wire nvdla_op_gated_clk_mux; +wire nvdla_op_gated_clk_wt; +wire [3:0] reg2dp_arb_weight; +wire [3:0] reg2dp_arb_wmb; +wire [31:0] reg2dp_batch_stride; +wire [4:0] reg2dp_batches; +wire [17:0] reg2dp_byte_per_kernel; +wire [0:0] reg2dp_conv_mode; +wire [2:0] reg2dp_conv_x_stride; +wire [2:0] reg2dp_conv_y_stride; +wire [0:0] reg2dp_cvt_en; +wire [15:0] reg2dp_cvt_offset; +wire [15:0] reg2dp_cvt_scale; +wire [5:0] reg2dp_cvt_truncate; +wire [31:0] reg2dp_cya; +wire [4:0] reg2dp_data_bank; +wire [0:0] reg2dp_data_reuse; +wire [31:0] reg2dp_datain_addr_high_0; +wire [31:0] reg2dp_datain_addr_high_1; +wire [31:0] reg2dp_datain_addr_low_0; +wire [31:0] reg2dp_datain_addr_low_1; +wire [12:0] reg2dp_datain_channel; +wire [0:0] reg2dp_datain_format; +wire [12:0] reg2dp_datain_height; +wire [12:0] reg2dp_datain_height_ext; +wire [0:0] reg2dp_datain_ram_type; +wire [12:0] reg2dp_datain_width; +wire [12:0] reg2dp_datain_width_ext; +wire [0:0] reg2dp_dma_en; +wire [13:0] reg2dp_entries; +wire [11:0] reg2dp_grains; +wire [1:0] reg2dp_in_precision; +wire [0:0] reg2dp_line_packed; +wire [31:0] reg2dp_line_stride; +wire [15:0] reg2dp_mean_ax; +wire [15:0] reg2dp_mean_bv; +wire [0:0] reg2dp_mean_format; +wire [15:0] reg2dp_mean_gu; +wire [15:0] reg2dp_mean_ry; +wire [0:0] reg2dp_nan_to_zero; +wire [0:0] reg2dp_op_en; +wire [5:0] reg2dp_pad_bottom; +wire [4:0] reg2dp_pad_left; +wire [5:0] reg2dp_pad_right; +wire [4:0] reg2dp_pad_top; +wire [15:0] reg2dp_pad_value; +wire [5:0] reg2dp_pixel_format; +wire [0:0] reg2dp_pixel_mapping; +wire [0:0] reg2dp_pixel_sign_override; +wire [4:0] reg2dp_pixel_x_offset; +wire [2:0] reg2dp_pixel_y_offset; +wire [1:0] reg2dp_proc_precision; +wire [2:0] reg2dp_rsv_height; +wire [9:0] reg2dp_rsv_per_line; +wire [9:0] reg2dp_rsv_per_uv_line; +wire [4:0] reg2dp_rsv_y_index; +wire [0:0] reg2dp_skip_data_rls; +wire [0:0] reg2dp_skip_weight_rls; +wire [0:0] reg2dp_surf_packed; +wire [31:0] reg2dp_surf_stride; +wire [31:0] reg2dp_uv_line_stride; +wire [31:0] reg2dp_weight_addr_high; +wire [31:0] reg2dp_weight_addr_low; +wire [4:0] reg2dp_weight_bank; +wire [31:0] reg2dp_weight_bytes; +wire [0:0] reg2dp_weight_format; +wire [12:0] reg2dp_weight_kernel; +wire [0:0] reg2dp_weight_ram_type; +wire [0:0] reg2dp_weight_reuse; +wire [31:0] reg2dp_wgs_addr_high; +wire [31:0] reg2dp_wgs_addr_low; +wire [31:0] reg2dp_wmb_addr_high; +wire [31:0] reg2dp_wmb_addr_low; +wire [27:0] reg2dp_wmb_bytes; +wire slcg_dc_gate_img; +wire slcg_dc_gate_wg; +wire slcg_hls_en; +wire slcg_img_gate_dc; +wire slcg_img_gate_wg; +wire [7:0] slcg_op_en; +wire slcg_wg_gate_dc; +wire slcg_wg_gate_img; +wire [14:0] status2dma_free_entries; +wire status2dma_fsm_switch; +wire [13:0] status2dma_valid_slices; +wire [14:0] status2dma_wr_idx; +wire [1:0] wt2status_state; +/////////////////////////////////////////////////////////////////////////// +//========================================================== +// Regfile +//========================================================== +NV_NVDLA_CDMA_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2cdma_req_pd (csb2cdma_req_pd[62:0]) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.dp2reg_dat_flush_done (dp2reg_dat_flush_done) + ,.dp2reg_dc_rd_latency (dp2reg_dc_rd_latency[31:0]) + ,.dp2reg_dc_rd_stall (dp2reg_dc_rd_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_img_rd_latency (dp2reg_img_rd_latency[31:0]) + ,.dp2reg_img_rd_stall (dp2reg_img_rd_stall[31:0]) + ,.dp2reg_inf_data_num (dp2reg_inf_data_num[31:0]) + ,.dp2reg_inf_weight_num (dp2reg_inf_weight_num[31:0]) + ,.dp2reg_nan_data_num (dp2reg_nan_data_num[31:0]) + ,.dp2reg_nan_weight_num (dp2reg_nan_weight_num[31:0]) + ,.dp2reg_wg_rd_latency (dp2reg_wg_rd_latency[31:0]) + ,.dp2reg_wg_rd_stall (dp2reg_wg_rd_stall[31:0]) + ,.dp2reg_wt_flush_done (dp2reg_wt_flush_done) + ,.dp2reg_wt_rd_latency (dp2reg_wt_rd_latency[31:0]) + ,.dp2reg_wt_rd_stall (dp2reg_wt_rd_stall[31:0]) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd[33:0]) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.dp2reg_consumer (dp2reg_consumer) + ,.reg2dp_arb_weight (reg2dp_arb_weight[3:0]) + ,.reg2dp_arb_wmb (reg2dp_arb_wmb[3:0]) + ,.reg2dp_batch_stride (reg2dp_batch_stride[31:0]) + ,.reg2dp_batches (reg2dp_batches[4:0]) + ,.reg2dp_byte_per_kernel (reg2dp_byte_per_kernel[17:0]) + ,.reg2dp_conv_mode (reg2dp_conv_mode) + ,.reg2dp_conv_x_stride (reg2dp_conv_x_stride[2:0]) + ,.reg2dp_conv_y_stride (reg2dp_conv_y_stride[2:0]) + ,.reg2dp_cvt_en (reg2dp_cvt_en) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[15:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_cvt_truncate (reg2dp_cvt_truncate[5:0]) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_data_reuse (reg2dp_data_reuse) + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) + ,.reg2dp_datain_addr_high_1 (reg2dp_datain_addr_high_1[31:0]) + ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:0]) + ,.reg2dp_datain_addr_low_1 (reg2dp_datain_addr_low_1[31:0]) + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) + ,.reg2dp_datain_format (reg2dp_datain_format) + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_datain_width_ext (reg2dp_datain_width_ext[12:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_entries (reg2dp_entries[13:0]) + ,.reg2dp_grains (reg2dp_grains[11:0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_line_packed (reg2dp_line_packed) + ,.reg2dp_line_stride (reg2dp_line_stride[31:0]) + ,.reg2dp_mean_ax (reg2dp_mean_ax[15:0]) + ,.reg2dp_mean_bv (reg2dp_mean_bv[15:0]) + ,.reg2dp_mean_format (reg2dp_mean_format) + ,.reg2dp_mean_gu (reg2dp_mean_gu[15:0]) + ,.reg2dp_mean_ry (reg2dp_mean_ry[15:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_bottom (reg2dp_pad_bottom[5:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) + ,.reg2dp_pad_top (reg2dp_pad_top[4:0]) + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) + ,.reg2dp_pixel_format (reg2dp_pixel_format[5:0]) + ,.reg2dp_pixel_mapping (reg2dp_pixel_mapping) + ,.reg2dp_pixel_sign_override (reg2dp_pixel_sign_override) + ,.reg2dp_pixel_x_offset (reg2dp_pixel_x_offset[4:0]) + ,.reg2dp_pixel_y_offset (reg2dp_pixel_y_offset[2:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_rsv_height (reg2dp_rsv_height[2:0]) + ,.reg2dp_rsv_per_line (reg2dp_rsv_per_line[9:0]) + ,.reg2dp_rsv_per_uv_line (reg2dp_rsv_per_uv_line[9:0]) + ,.reg2dp_rsv_y_index (reg2dp_rsv_y_index[4:0]) + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls) + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls) + ,.reg2dp_surf_packed (reg2dp_surf_packed) + ,.reg2dp_surf_stride (reg2dp_surf_stride[31:0]) + ,.reg2dp_uv_line_stride (reg2dp_uv_line_stride[31:0]) + ,.reg2dp_weight_addr_high (reg2dp_weight_addr_high[31:0]) + ,.reg2dp_weight_addr_low (reg2dp_weight_addr_low[31:0]) + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) + ,.reg2dp_weight_format (reg2dp_weight_format) + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) + ,.reg2dp_weight_ram_type (reg2dp_weight_ram_type) + ,.reg2dp_weight_reuse (reg2dp_weight_reuse) + ,.reg2dp_wgs_addr_high (reg2dp_wgs_addr_high[31:0]) + ,.reg2dp_wgs_addr_low (reg2dp_wgs_addr_low[31:0]) + ,.reg2dp_wmb_addr_high (reg2dp_wmb_addr_high[31:0]) + ,.reg2dp_wmb_addr_low (reg2dp_wmb_addr_low[31:0]) + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) + ,.slcg_op_en (slcg_op_en[7:0]) + ); +//========================================================== +// Weight DMA +//========================================================== +NV_NVDLA_CDMA_wt u_wt ( + .nvdla_core_clk (nvdla_op_gated_clk_wt) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd ) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd ) + ,.cdma2buf_wt_wr_en (cdma2buf_wt_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_sel (cdma2buf_wt_wr_sel ) +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_mask (cdma2buf_wt_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_wt_wr_addr${i} (cdma2buf_wt_wr_addr${i} ) +//: ,.cdma2buf_wt_wr_data${i} (cdma2buf_wt_wr_data${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +//,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_hsel) +//,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.wt2status_state (wt2status_state[1:0]) + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels ) + ,.cdma2sc_wt_entries (cdma2sc_wt_entries ) + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries_f ) // + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels ) + ,.sc2cdma_wt_entries (sc2cdma_wt_entries ) + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries ) + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) + ,.nvdla_core_ng_clk (nvdla_core_clk) + ,.reg2dp_arb_weight (reg2dp_arb_weight[3:0]) + ,.reg2dp_arb_wmb (reg2dp_arb_wmb[3:0]) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_weight_reuse (reg2dp_weight_reuse[0]) + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls[0]) + ,.reg2dp_weight_format (reg2dp_weight_format[0]) + ,.reg2dp_byte_per_kernel (reg2dp_byte_per_kernel[17:0]) + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) + ,.reg2dp_weight_ram_type (reg2dp_weight_ram_type[0]) + ,.reg2dp_weight_addr_high (reg2dp_weight_addr_high[31:0]) +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: ,.reg2dp_weight_addr_low (reg2dp_weight_addr_low[31:${atmbw}]) +//: ,.reg2dp_wgs_addr_low (reg2dp_wgs_addr_low[31:${atmbw}]) +//: ,.reg2dp_wmb_addr_low (reg2dp_wmb_addr_low[31:${atmbw}]) +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.reg2dp_weight_addr_low (reg2dp_weight_addr_low[31:3]) +,.reg2dp_wgs_addr_low (reg2dp_wgs_addr_low[31:3]) +,.reg2dp_wmb_addr_low (reg2dp_wmb_addr_low[31:3]) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) + ,.reg2dp_wgs_addr_high (reg2dp_wgs_addr_high[31:0]) + ,.reg2dp_wmb_addr_high (reg2dp_wmb_addr_high[31:0]) + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero[0]) + ,.reg2dp_dma_en (reg2dp_dma_en[0]) + ,.dp2reg_nan_weight_num (dp2reg_nan_weight_num[31:0]) + ,.dp2reg_inf_weight_num (dp2reg_inf_weight_num[31:0]) + ,.dp2reg_wt_flush_done (dp2reg_wt_flush_done) + ,.dp2reg_wt_rd_stall (dp2reg_wt_rd_stall[31:0]) + ,.dp2reg_wt_rd_latency (dp2reg_wt_rd_latency[31:0]) + ); +//-------------- SLCG for weight DMA --------------// +NV_NVDLA_CDMA_slcg u_slcg_wt ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[0]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_wt) + ); +//========================================================== +// Direct convolution DMA +//========================================================== +NV_NVDLA_CDMA_dc u_dc ( + .nvdla_core_clk (nvdla_op_gated_clk_dc) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dc_dat2mcif_rd_req_valid (dc_dat2mcif_rd_req_valid) + ,.dc_dat2mcif_rd_req_ready (dc_dat2mcif_rd_req_ready) + ,.dc_dat2mcif_rd_req_pd (dc_dat2mcif_rd_req_pd) + ,.mcif2dc_dat_rd_rsp_valid (mcif2dc_dat_rd_rsp_valid) + ,.mcif2dc_dat_rd_rsp_ready (mcif2dc_dat_rd_rsp_ready) + ,.mcif2dc_dat_rd_rsp_pd (mcif2dc_dat_rd_rsp_pd) + ,.dc2cvt_dat_wr_en (dc2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,.dc2cvt_dat_wr_sel (dc2cvt_dat_wr_sel) +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.dc2cvt_dat_wr_mask (dc2cvt_dat_wr_mask) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.dc2cvt_dat_wr_addr${i} (dc2cvt_dat_wr_addr${i}) +//: ,.dc2cvt_dat_wr_data${i} (dc2cvt_dat_wr_data${i}) +//: ); +//: } +//: } else { +//: print qq( +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.dc2cvt_dat_wr_info_pd (dc2cvt_dat_wr_info_pd[11:0]) +// ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +// ,.dc2cvt_dat_wr_sel (dc2cvt_dat_wr_hsel) +// ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.dc2status_state (dc2status_state[1:0]) + ,.dc2status_dat_updt (dc2status_dat_updt) + ,.dc2status_dat_entries (dc2status_dat_entries ) + ,.dc2status_dat_slices (dc2status_dat_slices ) + ,.status2dma_valid_slices (status2dma_valid_slices) + ,.status2dma_free_entries (status2dma_free_entries) + ,.status2dma_wr_idx (status2dma_wr_idx) +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,.dc2sbuf_p${i}_wr_en (dc2sbuf_p${i}_wr_en ) +//: ,.dc2sbuf_p${i}_wr_addr (dc2sbuf_p${i}_wr_addr ) +//: ,.dc2sbuf_p${i}_wr_data (dc2sbuf_p${i}_wr_data ) +//: ,.dc2sbuf_p${i}_rd_en (dc2sbuf_p${i}_rd_en ) +//: ,.dc2sbuf_p${i}_rd_addr (dc2sbuf_p${i}_rd_addr ) +//: ,.dc2sbuf_p${i}_rd_data (dc2sbuf_p${i}_rd_data ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dc2sbuf_p0_wr_en (dc2sbuf_p0_wr_en ) +,.dc2sbuf_p0_wr_addr (dc2sbuf_p0_wr_addr ) +,.dc2sbuf_p0_wr_data (dc2sbuf_p0_wr_data ) +,.dc2sbuf_p0_rd_en (dc2sbuf_p0_rd_en ) +,.dc2sbuf_p0_rd_addr (dc2sbuf_p0_rd_addr ) +,.dc2sbuf_p0_rd_data (dc2sbuf_p0_rd_data ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// ,.dc2sbuf_p0_wr_en (dc2sbuf_p0_wr_en) +// ,.dc2sbuf_p0_wr_addr (dc2sbuf_p0_wr_addr) +// ,.dc2sbuf_p0_wr_data (dc2sbuf_p0_wr_data) +// ,.dc2sbuf_p0_rd_en (dc2sbuf_p0_rd_en) +// ,.dc2sbuf_p0_rd_addr (dc2sbuf_p0_rd_addr) +// ,.dc2sbuf_p0_rd_data (dc2sbuf_p0_rd_data) +// ,.dc2sbuf_p1_wr_en (dc2sbuf_p1_wr_en) +// ,.dc2sbuf_p1_wr_addr (dc2sbuf_p1_wr_addr) +// ,.dc2sbuf_p1_wr_data (dc2sbuf_p1_wr_data) +// ,.dc2sbuf_p1_rd_en (dc2sbuf_p1_rd_en) +// ,.dc2sbuf_p1_rd_addr (dc2sbuf_p1_rd_addr) +// ,.dc2sbuf_p1_rd_data (dc2sbuf_p1_rd_data) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.nvdla_core_ng_clk (nvdla_core_clk) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) + ,.reg2dp_datain_format (reg2dp_datain_format[0]) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type[0]) + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:${atmbw}]) +//: ,.reg2dp_batch_stride (reg2dp_batch_stride[31:${atmbw}]) +//: ,.reg2dp_line_stride (reg2dp_line_stride[31:${atmbw}]) +//: ,.reg2dp_surf_stride (reg2dp_surf_stride[31:${atmbw}]) +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:3]) +,.reg2dp_batch_stride (reg2dp_batch_stride[31:3]) +,.reg2dp_line_stride (reg2dp_line_stride[31:3]) +,.reg2dp_surf_stride (reg2dp_surf_stride[31:3]) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.reg2dp_line_packed (reg2dp_line_packed[0]) + ,.reg2dp_surf_packed (reg2dp_surf_packed[0]) + ,.reg2dp_batches (reg2dp_batches[4:0]) + ,.reg2dp_entries ({3'd0,reg2dp_entries[13:0]}) // + ,.reg2dp_grains (reg2dp_grains[11:0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_dma_en (reg2dp_dma_en[0]) + ,.slcg_dc_gate_wg (slcg_dc_gate_wg) + ,.slcg_dc_gate_img (slcg_dc_gate_img) + ,.dp2reg_dc_rd_stall (dp2reg_dc_rd_stall[31:0]) + ,.dp2reg_dc_rd_latency (dp2reg_dc_rd_latency[31:0]) + ); +//-------------- SLCG for DC DMA --------------// +NV_NVDLA_CDMA_slcg u_slcg_dc ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[1]) + ,.slcg_en_src_1 (slcg_wg_gate_dc) + ,.slcg_en_src_2 (slcg_img_gate_dc) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_dc) + ); +assign slcg_wg_gate_dc = 1'b1; +assign slcg_wg_gate_img = 1'b1; +assign dp2reg_wg_rd_latency = 32'b0; +assign dp2reg_wg_rd_stall = 32'b0; +//========================================================== +// Image convolution DMA +//========================================================== +NV_NVDLA_CDMA_img u_img ( + .nvdla_core_clk (nvdla_op_gated_clk_img) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.img_dat2mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.img_dat2mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.img_dat2mcif_rd_req_pd (img_dat2mcif_rd_req_pd) + ,.mcif2img_dat_rd_rsp_valid (mcif2img_dat_rd_rsp_valid) + ,.mcif2img_dat_rd_rsp_ready (mcif2img_dat_rd_rsp_ready) + ,.mcif2img_dat_rd_rsp_pd (mcif2img_dat_rd_rsp_pd) + ,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_sel (img2cvt_dat_wr_sel ) +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_mask (img2cvt_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.img2cvt_dat_wr_addr${i} (img2cvt_dat_wr_addr${i} ) +//: ,.img2cvt_dat_wr_data${i} (img2cvt_dat_wr_data${i} ) +//: ,.img2cvt_mn_wr_data${i} (img2cvt_mn_wr_data${i} ) +//: ,.img2cvt_dat_wr_pad_mask${i} (img2cvt_dat_wr_pad_mask${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) //|> w +//,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr[11:0]) //|> w +//,.img2cvt_dat_wr_sel (img2cvt_dat_wr_hsel) //|> w +//,.img2cvt_dat_wr_data (img2cvt_dat_wr_data[1023:0]) //|> w +//,.img2cvt_mn_wr_data (img2cvt_mn_wr_data[1023:0]) //|> w + ,.img2cvt_dat_wr_info_pd (img2cvt_dat_wr_info_pd[11:0]) //|> w + ,.status2dma_fsm_switch (status2dma_fsm_switch) //|< w + ,.img2status_state (img2status_state[1:0]) //|> w + ,.img2status_dat_updt (img2status_dat_updt) //|> w + ,.img2status_dat_entries (img2status_dat_entries[14:0]) //|> w + ,.img2status_dat_slices (img2status_dat_slices) //|> w + ,.status2dma_valid_slices (status2dma_valid_slices) //|< w + ,.status2dma_free_entries (status2dma_free_entries[14:0]) //|< w + ,.status2dma_wr_idx (status2dma_wr_idx) //|< w +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,.img2sbuf_p${i}_wr_en (img2sbuf_p${i}_wr_en ) +//: ,.img2sbuf_p${i}_wr_addr (img2sbuf_p${i}_wr_addr ) +//: ,.img2sbuf_p${i}_wr_data (img2sbuf_p${i}_wr_data ) +//: ,.img2sbuf_p${i}_rd_en (img2sbuf_p${i}_rd_en ) +//: ,.img2sbuf_p${i}_rd_addr (img2sbuf_p${i}_rd_addr ) +//: ,.img2sbuf_p${i}_rd_data (img2sbuf_p${i}_rd_data ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2sbuf_p0_wr_en (img2sbuf_p0_wr_en ) +,.img2sbuf_p0_wr_addr (img2sbuf_p0_wr_addr ) +,.img2sbuf_p0_wr_data (img2sbuf_p0_wr_data ) +,.img2sbuf_p0_rd_en (img2sbuf_p0_rd_en ) +,.img2sbuf_p0_rd_addr (img2sbuf_p0_rd_addr ) +,.img2sbuf_p0_rd_data (img2sbuf_p0_rd_data ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.img2sbuf_p0_wr_en (img2sbuf_p0_wr_en) //|> w +//,.img2sbuf_p0_wr_addr (img2sbuf_p0_wr_addr[7:0]) //|> w +//,.img2sbuf_p0_wr_data (img2sbuf_p0_wr_data[255:0]) //|> w +//,.img2sbuf_p0_rd_en (img2sbuf_p0_rd_en) //|> w +//,.img2sbuf_p0_rd_addr (img2sbuf_p0_rd_addr[7:0]) //|> w +//,.img2sbuf_p0_rd_data (img2sbuf_p0_rd_data[255:0]) //|< w +//,.img2sbuf_p1_wr_en (img2sbuf_p1_wr_en) //|> w +//,.img2sbuf_p1_wr_addr (img2sbuf_p1_wr_addr[7:0]) //|> w +//,.img2sbuf_p1_wr_data (img2sbuf_p1_wr_data[255:0]) //|> w +//,.img2sbuf_p1_rd_en (img2sbuf_p1_rd_en) //|> w +//,.img2sbuf_p1_rd_addr (img2sbuf_p1_rd_addr[7:0]) //|> w +//,.img2sbuf_p1_rd_data (img2sbuf_p1_rd_data[255:0]) //|< w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|< i + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) //|< w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) //|< w + ,.reg2dp_datain_format (reg2dp_datain_format[0]) //|< w + ,.reg2dp_pixel_format (reg2dp_pixel_format[5:0]) //|< w + ,.reg2dp_pixel_mapping (reg2dp_pixel_mapping[0]) //|< w + ,.reg2dp_pixel_sign_override (reg2dp_pixel_sign_override[0]) //|< w + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) //|< w + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) //|< w + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) //|< w + ,.reg2dp_pixel_x_offset (reg2dp_pixel_x_offset[4:0]) //|< w + ,.reg2dp_pixel_y_offset (reg2dp_pixel_y_offset[2:0]) //|< w + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type[0]) //|< w + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) //|< w + ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:0]) + ,.reg2dp_datain_addr_high_1 (reg2dp_datain_addr_high_1[31:0]) //|< w + ,.reg2dp_datain_addr_low_1 (reg2dp_datain_addr_low_1[31:0]) //|< w + ,.reg2dp_line_stride (reg2dp_line_stride[31:0]) //|< w + ,.reg2dp_uv_line_stride (reg2dp_uv_line_stride[31:0]) //|< w + ,.reg2dp_mean_format (reg2dp_mean_format[0]) //|< w + ,.reg2dp_mean_ry (reg2dp_mean_ry[15:0]) //|< w + ,.reg2dp_mean_gu (reg2dp_mean_gu[15:0]) //|< w + ,.reg2dp_mean_bv (reg2dp_mean_bv[15:0]) //|< w + ,.reg2dp_mean_ax (reg2dp_mean_ax[15:0]) //|< w + ,.reg2dp_entries (reg2dp_entries[13:0]) //|< w + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) //|< w + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_dma_en (reg2dp_dma_en[0]) //|< w + ,.reg2dp_rsv_per_line (reg2dp_rsv_per_line[9:0]) //|< w + ,.reg2dp_rsv_per_uv_line (reg2dp_rsv_per_uv_line[9:0]) //|< w + ,.reg2dp_rsv_height (reg2dp_rsv_height[2:0]) //|< w + ,.reg2dp_rsv_y_index (reg2dp_rsv_y_index[4:0]) //|< w + ,.slcg_img_gate_dc (slcg_img_gate_dc) //|> w + ,.slcg_img_gate_wg (slcg_img_gate_wg) //|> w + ,.dp2reg_img_rd_stall (dp2reg_img_rd_stall[31:0]) //|> w + ,.dp2reg_img_rd_latency (dp2reg_img_rd_latency[31:0]) //|> w +//,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask[127:0]) //|> w + ); +// +wire img2sbuf_p1_wr_en; +wire [7:0] img2sbuf_p1_wr_addr; +wire [8*8 -1:0] img2sbuf_p1_wr_data; +wire img2sbuf_p1_rd_en; +wire [7:0] img2sbuf_p1_rd_addr; + assign img2sbuf_p1_wr_en = 1'b0; + assign img2sbuf_p1_wr_addr = 8'b0; + assign img2sbuf_p1_wr_data = 64'b0; + assign img2sbuf_p1_rd_en = 1'b0; + assign img2sbuf_p1_rd_addr = 8'b0; +//-------------- SLCG for IMG DMA --------------// +NV_NVDLA_CDMA_slcg u_slcg_img ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[3]) + ,.slcg_en_src_1 (slcg_dc_gate_img) + ,.slcg_en_src_2 (slcg_wg_gate_img) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_img) + ); +//========================================================== +// DMA mux +//========================================================== +NV_NVDLA_CDMA_dma_mux u_dma_mux ( + .nvdla_core_clk (nvdla_op_gated_clk_mux) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dc_dat2mcif_rd_req_valid (dc_dat2mcif_rd_req_valid) + ,.dc_dat2mcif_rd_req_ready (dc_dat2mcif_rd_req_ready) + ,.dc_dat2mcif_rd_req_pd (dc_dat2mcif_rd_req_pd) + ,.img_dat2mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.img_dat2mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.img_dat2mcif_rd_req_pd (img_dat2mcif_rd_req_pd) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd) + ,.mcif2dc_dat_rd_rsp_valid (mcif2dc_dat_rd_rsp_valid) + ,.mcif2dc_dat_rd_rsp_ready (mcif2dc_dat_rd_rsp_ready) + ,.mcif2dc_dat_rd_rsp_pd (mcif2dc_dat_rd_rsp_pd) + ,.mcif2img_dat_rd_rsp_valid (mcif2img_dat_rd_rsp_valid) + ,.mcif2img_dat_rd_rsp_ready (mcif2img_dat_rd_rsp_ready) + ,.mcif2img_dat_rd_rsp_pd (mcif2img_dat_rd_rsp_pd) + ); +//-------------- SLCG for MUX --------------// +NV_NVDLA_CDMA_slcg u_slcg_mux ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[4]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_mux) + ); +//========================================================== +// DMA data convertor +//========================================================== +NV_NVDLA_CDMA_cvt u_cvt ( + .nvdla_core_clk (nvdla_op_gated_clk_cvt) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dc2cvt_dat_wr_en (dc2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,.dc2cvt_dat_wr_sel (dc2cvt_dat_wr_sel) +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.dc2cvt_dat_wr_mask (dc2cvt_dat_wr_mask) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.dc2cvt_dat_wr_addr${i} (dc2cvt_dat_wr_addr${i}) +//: ,.dc2cvt_dat_wr_data${i} (dc2cvt_dat_wr_data${i}) +//: ); +//: } +//: } else { +//: print qq( +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.dc2cvt_dat_wr_info_pd (dc2cvt_dat_wr_info_pd[11:0]) +//,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//,.dc2cvt_dat_wr_hsel (dc2cvt_dat_wr_hsel) +//,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) + ,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_sel (img2cvt_dat_wr_sel ) +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_mask (img2cvt_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.img2cvt_dat_wr_addr${i} (img2cvt_dat_wr_addr${i} ) +//: ,.img2cvt_dat_wr_data${i} (img2cvt_dat_wr_data${i} ) +//: ,.img2cvt_mn_wr_data${i} (img2cvt_mn_wr_data${i} ) +//: ,.img2cvt_dat_wr_pad_mask${i} (img2cvt_dat_wr_pad_mask${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr) +//,.img2cvt_dat_wr_hsel (img2cvt_dat_wr_hsel) +//,.img2cvt_dat_wr_data (img2cvt_dat_wr_data) +//,.img2cvt_mn_wr_data (img2cvt_mn_wr_data) + ,.img2cvt_dat_wr_info_pd (img2cvt_dat_wr_info_pd[11:0]) + ,.cdma2buf_dat_wr_en (cdma2buf_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_dat_wr_sel (cdma2buf_dat_wr_sel ) +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr ) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.cdma2buf_dat_wr_mask (cdma2buf_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_dat_wr_addr${i} (cdma2buf_dat_wr_addr${i} ) +//: ,.cdma2buf_dat_wr_data${i} (cdma2buf_dat_wr_data${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr ) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr ) +,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_hsel) +//,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) + ,.nvdla_hls_clk (nvdla_hls_gated_clk_cvt) + ,.slcg_hls_en (slcg_hls_en) + ,.nvdla_core_ng_clk (nvdla_core_clk) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_cvt_en (reg2dp_cvt_en[0]) + ,.reg2dp_cvt_truncate (reg2dp_cvt_truncate[5:0]) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[15:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero[0]) + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) + ,.dp2reg_done (dp2reg_done) +//,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask) + ,.dp2reg_nan_data_num (dp2reg_nan_data_num[31:0]) + ,.dp2reg_inf_data_num (dp2reg_inf_data_num[31:0]) + ,.dp2reg_dat_flush_done (dp2reg_dat_flush_done) + ); +//-------------- SLCG for CVT --------------// +NV_NVDLA_CDMA_slcg u_slcg_cvt ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[5]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_cvt) + ); +//-------------- SLCG for CVT HLS CELL --------------// +NV_NVDLA_CDMA_slcg u_slcg_hls ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[6]) + ,.slcg_en_src_1 (slcg_hls_en) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_hls_gated_clk_cvt) + ); +//========================================================== +// Shared buffer +//========================================================== +NV_NVDLA_CDMA_shared_buffer u_shared_buffer ( + .nvdla_core_clk (nvdla_op_gated_clk_buffer) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dc2sbuf_p0_wr_en (dc2sbuf_p0_wr_en) + ,.dc2sbuf_p0_wr_addr (dc2sbuf_p0_wr_addr) + ,.dc2sbuf_p0_wr_data (dc2sbuf_p0_wr_data) + ,.dc2sbuf_p0_rd_en (dc2sbuf_p0_rd_en) + ,.dc2sbuf_p0_rd_addr (dc2sbuf_p0_rd_addr) + ,.dc2sbuf_p0_rd_data (dc2sbuf_p0_rd_data) + ,.dc2sbuf_p1_wr_en (1'b0) + ,.dc2sbuf_p1_wr_addr (8'd0) + ,.dc2sbuf_p1_wr_data ({8*8{1'b0}}) + ,.dc2sbuf_p1_rd_en (1'b0) + ,.dc2sbuf_p1_rd_addr (8'd0) + ,.dc2sbuf_p1_rd_data ( ) + ,.img2sbuf_p0_wr_en (img2sbuf_p0_wr_en) + ,.img2sbuf_p0_wr_addr (img2sbuf_p0_wr_addr) + ,.img2sbuf_p0_wr_data (img2sbuf_p0_wr_data) + ,.img2sbuf_p1_wr_en (img2sbuf_p1_wr_en) + ,.img2sbuf_p1_wr_addr (img2sbuf_p1_wr_addr) + ,.img2sbuf_p1_wr_data (img2sbuf_p1_wr_data) + ,.img2sbuf_p0_rd_en (img2sbuf_p0_rd_en) + ,.img2sbuf_p0_rd_addr (img2sbuf_p0_rd_addr) + ,.img2sbuf_p1_rd_en (img2sbuf_p1_rd_en) + ,.img2sbuf_p1_rd_addr (img2sbuf_p1_rd_addr) + ,.img2sbuf_p1_rd_data ( ) +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,.img2sbuf_p${i}_rd_data (img2sbuf_p${i}_rd_data ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.img2sbuf_p0_rd_data (img2sbuf_p0_rd_data ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ); +//-------------- SLCG for shared buffer --------------// +NV_NVDLA_CDMA_slcg u_slcg_buffer ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[7]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_buffer) + ); +//========================================================== +// CDMA status controller +//========================================================== +NV_NVDLA_CDMA_status u_status ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dc2status_dat_updt (dc2status_dat_updt) + ,.dc2status_dat_entries (dc2status_dat_entries) + ,.dc2status_dat_slices (dc2status_dat_slices) + ,.img2status_dat_updt (img2status_dat_updt) + ,.img2status_dat_entries (img2status_dat_entries) + ,.img2status_dat_slices (img2status_dat_slices) + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) + ,.sc2cdma_dat_entries (sc2cdma_dat_entries) + ,.sc2cdma_dat_slices (sc2cdma_dat_slices) + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) + ,.cdma2sc_dat_entries (cdma2sc_dat_entries) + ,.cdma2sc_dat_slices (cdma2sc_dat_slices) + ,.status2dma_valid_slices (status2dma_valid_slices) + ,.status2dma_free_entries (status2dma_free_entries) + ,.status2dma_wr_idx (status2dma_wr_idx) + ,.dc2status_state (dc2status_state[1:0]) + ,.img2status_state (img2status_state[1:0]) + ,.wt2status_state (wt2status_state[1:0]) + ,.dp2reg_done (dp2reg_done) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.dp2reg_consumer (dp2reg_consumer) + ); +//////////////////////////////////////////////////////////////////////// +// dangle not connected signals // +//////////////////////////////////////////////////////////////////////// +///////////////////// dangles from NV_NVDLA_CDMA_regfile ///////////////////// +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_zero_one_hot #(0,3,0,"Error! DC, WG and IMG slcg gate signal conflict!") zzz_assert_zero_one_hot_1x (nvdla_core_clk, `ASSERT_RESET, ({~slcg_dc_gate_wg, ~slcg_wg_gate_img, ~slcg_img_gate_dc})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Two DC slcg signal mismatch!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (slcg_dc_gate_wg ^ slcg_dc_gate_img)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Two WG slcg signal mismatch!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (slcg_wg_gate_dc ^ slcg_wg_gate_img)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Two IMG slcg signal mismatch!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (slcg_img_gate_dc ^ slcg_img_gate_wg)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_cdma diff --git a/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.v.vcp new file mode 100644 index 0000000..bed13ab --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdma/NV_NVDLA_cdma.v.vcp @@ -0,0 +1,1278 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDMA_define.h +//#define CDMA_SBUF_SDATA_BITS 256 +//DorisL-S---------------- +// +//DorisL-E---------------- +//-------------------------------------------------- +module NV_NVDLA_cdma ( + cdma_dat2mcif_rd_req_ready + ,cdma_wt2mcif_rd_req_ready + ,csb2cdma_req_pd + ,csb2cdma_req_pvld + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,mcif2cdma_dat_rd_rsp_pd + ,mcif2cdma_dat_rd_rsp_valid + ,mcif2cdma_wt_rd_rsp_pd + ,mcif2cdma_wt_rd_rsp_valid + ,nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd + ,sc2cdma_dat_entries + ,sc2cdma_dat_pending_req + ,sc2cdma_dat_slices + ,sc2cdma_dat_updt + ,sc2cdma_wmb_entries + ,sc2cdma_wt_entries + ,sc2cdma_wt_kernels + ,sc2cdma_wt_pending_req + ,sc2cdma_wt_updt + ,tmc2slcg_disable_clock_gating + ,cdma2buf_dat_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,cdma2buf_dat_wr_sel +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_dat_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_dat_wr_addr${i} +//: ,cdma2buf_dat_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_dat_wr_addr +//: ,cdma2buf_dat_wr_data +//: ); +//: } +//,cdma2buf_dat_wr_addr +//,cdma2buf_dat_wr_data +//,cdma2buf_dat_wr_hsel + ,cdma2buf_wt_wr_en +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,cdma2buf_wt_wr_sel +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,cdma2buf_wt_wr_mask +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,cdma2buf_wt_wr_addr${i} +//: ,cdma2buf_wt_wr_data${i} +//: ); +//: } +//: } else { +//: print qq( +//: ,cdma2buf_wt_wr_addr +//: ,cdma2buf_wt_wr_data +//: ); +//: } +//,cdma2buf_wt_wr_addr +//,cdma2buf_wt_wr_data +//,cdma2buf_wt_wr_hsel + ,cdma2csb_resp_pd + ,cdma2csb_resp_valid + ,cdma2sc_dat_entries + ,cdma2sc_dat_pending_ack + ,cdma2sc_dat_slices + ,cdma2sc_dat_updt + ,cdma2sc_wmb_entries + ,cdma2sc_wt_entries + ,cdma2sc_wt_kernels + ,cdma2sc_wt_pending_ack + ,cdma2sc_wt_updt + ,cdma_dat2glb_done_intr_pd + ,cdma_dat2mcif_rd_req_pd + ,cdma_dat2mcif_rd_req_valid + ,cdma_wt2glb_done_intr_pd + ,cdma_wt2mcif_rd_req_pd + ,cdma_wt2mcif_rd_req_valid + ,csb2cdma_req_prdy + ,mcif2cdma_dat_rd_rsp_ready + ,mcif2cdma_wt_rd_rsp_ready + ); +/////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +output cdma2csb_resp_valid; +output [33:0] cdma2csb_resp_pd; +input csb2cdma_req_pvld; +output csb2cdma_req_prdy; +input [62:0] csb2cdma_req_pd; +output cdma2buf_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_sel; +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_dat_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } +// output [11:0] cdma2buf_dat_wr_addr; +// output [1:0] cdma2buf_dat_wr_hsel; +// output [1023:0] cdma2buf_dat_wr_data; +output cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_sel ; +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: output [${k}-1:0] cdma2buf_wt_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr${i}; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: output [16:0] cdma2buf_wt_wr_addr; +//: output [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } +//output [11:0] cdma2buf_wt_wr_addr; +//output cdma2buf_wt_wr_hsel; +//output [511:0] cdma2buf_wt_wr_data; +output [1:0] cdma_dat2glb_done_intr_pd; +output [1:0] cdma_wt2glb_done_intr_pd; +output cdma_dat2mcif_rd_req_valid; +input cdma_dat2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] cdma_dat2mcif_rd_req_pd; +input mcif2cdma_dat_rd_rsp_valid; +output mcif2cdma_dat_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2cdma_dat_rd_rsp_pd; +output cdma_wt2mcif_rd_req_valid; +input cdma_wt2mcif_rd_req_ready; +output [( 32 + 15 )-1:0] cdma_wt2mcif_rd_req_pd; +input mcif2cdma_wt_rd_rsp_valid; +output mcif2cdma_wt_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2cdma_wt_rd_rsp_pd; +input sc2cdma_dat_pending_req; +input sc2cdma_wt_pending_req; +output cdma2sc_dat_pending_ack; +output cdma2sc_wt_pending_ack; +output cdma2sc_dat_updt; +output [14:0] cdma2sc_dat_entries; +output [13:0] cdma2sc_dat_slices; +input sc2cdma_dat_updt; +input [14:0] sc2cdma_dat_entries; +input [13:0] sc2cdma_dat_slices; +output cdma2sc_wt_updt; +output [13:0] cdma2sc_wt_kernels; +output [14:0] cdma2sc_wt_entries; +output [8:0] cdma2sc_wmb_entries; +input sc2cdma_wt_updt; +input [13:0] sc2cdma_wt_kernels; +input [14:0] sc2cdma_wt_entries; +input [8:0] sc2cdma_wmb_entries; +input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +/////////////////////////////////////////////////////////////////////////// +// +wire [11:0] cdma2sc_wmb_entries_f; +assign cdma2sc_wmb_entries = cdma2sc_wmb_entries_f[8:0]; +// +wire dc2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: wire [${k}-1:0] dc2cvt_dat_wr_sel; +//: wire [16:0] dc2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] dc2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] dc2cvt_dat_wr_addr${i}; +//: wire [${dmaif}-1:0] dc2cvt_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] dc2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] dc2cvt_dat_wr_data; +//: ); +//: } +//wire [16:0] dc2cvt_dat_wr_addr; +//wire [511:0] dc2cvt_dat_wr_data; +//wire dc2cvt_dat_wr_hsel; +wire [11:0] dc2cvt_dat_wr_info_pd; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire dc2sbuf_p${i}_wr_en; +//: wire [7:0] dc2sbuf_p${i}_wr_addr; +//: wire [${atmm}-1:0] dc2sbuf_p${i}_wr_data; +//: wire dc2sbuf_p${i}_rd_en; +//: wire [7:0] dc2sbuf_p${i}_rd_addr; +//: wire [${atmm}-1:0] dc2sbuf_p${i}_rd_data; +//: ); +//: } +wire [14:0] dc2status_dat_entries; +wire [13:0] dc2status_dat_slices; +wire dc2status_dat_updt; +wire [1:0] dc2status_state; +wire [( 32 + 15 )-1:0] dc_dat2mcif_rd_req_pd; +wire dc_dat2mcif_rd_req_ready; +wire dc_dat2mcif_rd_req_valid; +wire dp2reg_consumer; +wire dp2reg_dat_flush_done; +wire [31:0] dp2reg_dc_rd_latency; +wire [31:0] dp2reg_dc_rd_stall; +wire dp2reg_done; +wire [31:0] dp2reg_img_rd_latency; +wire [31:0] dp2reg_img_rd_stall; +wire [31:0] dp2reg_inf_data_num; +wire [31:0] dp2reg_inf_weight_num; +wire [31:0] dp2reg_nan_data_num; +wire [31:0] dp2reg_nan_weight_num; +wire [31:0] dp2reg_wg_rd_latency; +wire [31:0] dp2reg_wg_rd_stall; +wire dp2reg_wt_flush_done; +wire [31:0] dp2reg_wt_rd_latency; +wire [31:0] dp2reg_wt_rd_stall; +wire img2cvt_dat_wr_en; +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: wire [${k}-1:0] img2cvt_dat_wr_sel; +//: wire [16:0] img2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] img2cvt_dat_wr_data; +//: wire [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: wire [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] img2cvt_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] img2cvt_dat_wr_addr${i}; +//: wire [${dmaif}-1:0] img2cvt_dat_wr_data${i}; +//: wire [${Bnum}*16-1:0] img2cvt_mn_wr_data${i}; +//: wire [$Bnum-1:0] img2cvt_dat_wr_pad_mask${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] img2cvt_dat_wr_addr; +//: wire [${dmaif}-1:0] img2cvt_dat_wr_data; +//: wire [${Bnum}*16-1:0] img2cvt_mn_wr_data; +//: wire [$Bnum-1:0] img2cvt_dat_wr_pad_mask; +//: ); +//: } +//wire [11:0] img2cvt_dat_wr_addr; +//wire [1023:0] img2cvt_dat_wr_data; +//wire img2cvt_dat_wr_hsel; +wire [11:0] img2cvt_dat_wr_info_pd; +//wire [127:0] img2cvt_dat_wr_pad_mask; +//wire [1023:0] img2cvt_mn_wr_data; +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire img2sbuf_p${i}_wr_en ; +//: wire [7:0] img2sbuf_p${i}_wr_addr; +//: wire [${atmm}-1:0] img2sbuf_p${i}_wr_data; +//: wire img2sbuf_p${i}_rd_en; +//: wire [7:0] img2sbuf_p${i}_rd_addr; +//: wire [${atmm}-1:0] img2sbuf_p${i}_rd_data; +//: ); +//: } +//wire [7:0] img2sbuf_p0_rd_addr; +//wire [255:0] img2sbuf_p0_rd_data; +//wire img2sbuf_p0_rd_en; +//wire [7:0] img2sbuf_p0_wr_addr; +//wire [255:0] img2sbuf_p0_wr_data; +//wire img2sbuf_p0_wr_en; +//wire [7:0] img2sbuf_p1_rd_addr; +//wire [255:0] img2sbuf_p1_rd_data; +//wire [8*8 -1:0] img2sbuf_p1_rd_data; +//wire img2sbuf_p1_rd_en; +//wire [7:0] img2sbuf_p1_wr_addr; +//wire [255:0] img2sbuf_p1_wr_data; +//wire img2sbuf_p1_wr_en; +wire [14:0] img2status_dat_entries; +wire [13:0] img2status_dat_slices; +wire img2status_dat_updt; +wire [1:0] img2status_state; +wire [( 32 + 15 )-1:0] img_dat2mcif_rd_req_pd; +wire img_dat2mcif_rd_req_ready; +wire img_dat2mcif_rd_req_valid; +wire [( 64 + (64/8/8) )-1:0] mcif2dc_dat_rd_rsp_pd; +wire mcif2dc_dat_rd_rsp_ready; +wire mcif2dc_dat_rd_rsp_valid; +wire [( 64 + (64/8/8) )-1:0] mcif2img_dat_rd_rsp_pd; +wire mcif2img_dat_rd_rsp_ready; +wire mcif2img_dat_rd_rsp_valid; +wire nvdla_hls_gated_clk_cvt; +wire nvdla_op_gated_clk_buffer; +wire nvdla_op_gated_clk_cvt; +wire nvdla_op_gated_clk_dc; +wire nvdla_op_gated_clk_img; +wire nvdla_op_gated_clk_mux; +wire nvdla_op_gated_clk_wt; +wire [3:0] reg2dp_arb_weight; +wire [3:0] reg2dp_arb_wmb; +wire [31:0] reg2dp_batch_stride; +wire [4:0] reg2dp_batches; +wire [17:0] reg2dp_byte_per_kernel; +wire [0:0] reg2dp_conv_mode; +wire [2:0] reg2dp_conv_x_stride; +wire [2:0] reg2dp_conv_y_stride; +wire [0:0] reg2dp_cvt_en; +wire [15:0] reg2dp_cvt_offset; +wire [15:0] reg2dp_cvt_scale; +wire [5:0] reg2dp_cvt_truncate; +wire [31:0] reg2dp_cya; +wire [4:0] reg2dp_data_bank; +wire [0:0] reg2dp_data_reuse; +wire [31:0] reg2dp_datain_addr_high_0; +wire [31:0] reg2dp_datain_addr_high_1; +wire [31:0] reg2dp_datain_addr_low_0; +wire [31:0] reg2dp_datain_addr_low_1; +wire [12:0] reg2dp_datain_channel; +wire [0:0] reg2dp_datain_format; +wire [12:0] reg2dp_datain_height; +wire [12:0] reg2dp_datain_height_ext; +wire [0:0] reg2dp_datain_ram_type; +wire [12:0] reg2dp_datain_width; +wire [12:0] reg2dp_datain_width_ext; +wire [0:0] reg2dp_dma_en; +wire [13:0] reg2dp_entries; +wire [11:0] reg2dp_grains; +wire [1:0] reg2dp_in_precision; +wire [0:0] reg2dp_line_packed; +wire [31:0] reg2dp_line_stride; +wire [15:0] reg2dp_mean_ax; +wire [15:0] reg2dp_mean_bv; +wire [0:0] reg2dp_mean_format; +wire [15:0] reg2dp_mean_gu; +wire [15:0] reg2dp_mean_ry; +wire [0:0] reg2dp_nan_to_zero; +wire [0:0] reg2dp_op_en; +wire [5:0] reg2dp_pad_bottom; +wire [4:0] reg2dp_pad_left; +wire [5:0] reg2dp_pad_right; +wire [4:0] reg2dp_pad_top; +wire [15:0] reg2dp_pad_value; +wire [5:0] reg2dp_pixel_format; +wire [0:0] reg2dp_pixel_mapping; +wire [0:0] reg2dp_pixel_sign_override; +wire [4:0] reg2dp_pixel_x_offset; +wire [2:0] reg2dp_pixel_y_offset; +wire [1:0] reg2dp_proc_precision; +wire [2:0] reg2dp_rsv_height; +wire [9:0] reg2dp_rsv_per_line; +wire [9:0] reg2dp_rsv_per_uv_line; +wire [4:0] reg2dp_rsv_y_index; +wire [0:0] reg2dp_skip_data_rls; +wire [0:0] reg2dp_skip_weight_rls; +wire [0:0] reg2dp_surf_packed; +wire [31:0] reg2dp_surf_stride; +wire [31:0] reg2dp_uv_line_stride; +wire [31:0] reg2dp_weight_addr_high; +wire [31:0] reg2dp_weight_addr_low; +wire [4:0] reg2dp_weight_bank; +wire [31:0] reg2dp_weight_bytes; +wire [0:0] reg2dp_weight_format; +wire [12:0] reg2dp_weight_kernel; +wire [0:0] reg2dp_weight_ram_type; +wire [0:0] reg2dp_weight_reuse; +wire [31:0] reg2dp_wgs_addr_high; +wire [31:0] reg2dp_wgs_addr_low; +wire [31:0] reg2dp_wmb_addr_high; +wire [31:0] reg2dp_wmb_addr_low; +wire [27:0] reg2dp_wmb_bytes; +wire slcg_dc_gate_img; +wire slcg_dc_gate_wg; +wire slcg_hls_en; +wire slcg_img_gate_dc; +wire slcg_img_gate_wg; +wire [7:0] slcg_op_en; +wire slcg_wg_gate_dc; +wire slcg_wg_gate_img; +wire [14:0] status2dma_free_entries; +wire status2dma_fsm_switch; +wire [13:0] status2dma_valid_slices; +wire [14:0] status2dma_wr_idx; +wire [1:0] wt2status_state; +/////////////////////////////////////////////////////////////////////////// +//========================================================== +// Regfile +//========================================================== +NV_NVDLA_CDMA_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2cdma_req_pd (csb2cdma_req_pd[62:0]) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.dp2reg_dat_flush_done (dp2reg_dat_flush_done) + ,.dp2reg_dc_rd_latency (dp2reg_dc_rd_latency[31:0]) + ,.dp2reg_dc_rd_stall (dp2reg_dc_rd_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_img_rd_latency (dp2reg_img_rd_latency[31:0]) + ,.dp2reg_img_rd_stall (dp2reg_img_rd_stall[31:0]) + ,.dp2reg_inf_data_num (dp2reg_inf_data_num[31:0]) + ,.dp2reg_inf_weight_num (dp2reg_inf_weight_num[31:0]) + ,.dp2reg_nan_data_num (dp2reg_nan_data_num[31:0]) + ,.dp2reg_nan_weight_num (dp2reg_nan_weight_num[31:0]) + ,.dp2reg_wg_rd_latency (dp2reg_wg_rd_latency[31:0]) + ,.dp2reg_wg_rd_stall (dp2reg_wg_rd_stall[31:0]) + ,.dp2reg_wt_flush_done (dp2reg_wt_flush_done) + ,.dp2reg_wt_rd_latency (dp2reg_wt_rd_latency[31:0]) + ,.dp2reg_wt_rd_stall (dp2reg_wt_rd_stall[31:0]) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd[33:0]) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.dp2reg_consumer (dp2reg_consumer) + ,.reg2dp_arb_weight (reg2dp_arb_weight[3:0]) + ,.reg2dp_arb_wmb (reg2dp_arb_wmb[3:0]) + ,.reg2dp_batch_stride (reg2dp_batch_stride[31:0]) + ,.reg2dp_batches (reg2dp_batches[4:0]) + ,.reg2dp_byte_per_kernel (reg2dp_byte_per_kernel[17:0]) + ,.reg2dp_conv_mode (reg2dp_conv_mode) + ,.reg2dp_conv_x_stride (reg2dp_conv_x_stride[2:0]) + ,.reg2dp_conv_y_stride (reg2dp_conv_y_stride[2:0]) + ,.reg2dp_cvt_en (reg2dp_cvt_en) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[15:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_cvt_truncate (reg2dp_cvt_truncate[5:0]) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_data_reuse (reg2dp_data_reuse) + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) + ,.reg2dp_datain_addr_high_1 (reg2dp_datain_addr_high_1[31:0]) + ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:0]) + ,.reg2dp_datain_addr_low_1 (reg2dp_datain_addr_low_1[31:0]) + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) + ,.reg2dp_datain_format (reg2dp_datain_format) + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_datain_width_ext (reg2dp_datain_width_ext[12:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_entries (reg2dp_entries[13:0]) + ,.reg2dp_grains (reg2dp_grains[11:0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_line_packed (reg2dp_line_packed) + ,.reg2dp_line_stride (reg2dp_line_stride[31:0]) + ,.reg2dp_mean_ax (reg2dp_mean_ax[15:0]) + ,.reg2dp_mean_bv (reg2dp_mean_bv[15:0]) + ,.reg2dp_mean_format (reg2dp_mean_format) + ,.reg2dp_mean_gu (reg2dp_mean_gu[15:0]) + ,.reg2dp_mean_ry (reg2dp_mean_ry[15:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_bottom (reg2dp_pad_bottom[5:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) + ,.reg2dp_pad_top (reg2dp_pad_top[4:0]) + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) + ,.reg2dp_pixel_format (reg2dp_pixel_format[5:0]) + ,.reg2dp_pixel_mapping (reg2dp_pixel_mapping) + ,.reg2dp_pixel_sign_override (reg2dp_pixel_sign_override) + ,.reg2dp_pixel_x_offset (reg2dp_pixel_x_offset[4:0]) + ,.reg2dp_pixel_y_offset (reg2dp_pixel_y_offset[2:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_rsv_height (reg2dp_rsv_height[2:0]) + ,.reg2dp_rsv_per_line (reg2dp_rsv_per_line[9:0]) + ,.reg2dp_rsv_per_uv_line (reg2dp_rsv_per_uv_line[9:0]) + ,.reg2dp_rsv_y_index (reg2dp_rsv_y_index[4:0]) + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls) + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls) + ,.reg2dp_surf_packed (reg2dp_surf_packed) + ,.reg2dp_surf_stride (reg2dp_surf_stride[31:0]) + ,.reg2dp_uv_line_stride (reg2dp_uv_line_stride[31:0]) + ,.reg2dp_weight_addr_high (reg2dp_weight_addr_high[31:0]) + ,.reg2dp_weight_addr_low (reg2dp_weight_addr_low[31:0]) + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) + ,.reg2dp_weight_format (reg2dp_weight_format) + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) + ,.reg2dp_weight_ram_type (reg2dp_weight_ram_type) + ,.reg2dp_weight_reuse (reg2dp_weight_reuse) + ,.reg2dp_wgs_addr_high (reg2dp_wgs_addr_high[31:0]) + ,.reg2dp_wgs_addr_low (reg2dp_wgs_addr_low[31:0]) + ,.reg2dp_wmb_addr_high (reg2dp_wmb_addr_high[31:0]) + ,.reg2dp_wmb_addr_low (reg2dp_wmb_addr_low[31:0]) + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) + ,.slcg_op_en (slcg_op_en[7:0]) + ); +//========================================================== +// Weight DMA +//========================================================== +NV_NVDLA_CDMA_wt u_wt ( + .nvdla_core_clk (nvdla_op_gated_clk_wt) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd ) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd ) + ,.cdma2buf_wt_wr_en (cdma2buf_wt_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_sel (cdma2buf_wt_wr_sel ) +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_mask (cdma2buf_wt_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_wt_wr_addr${i} (cdma2buf_wt_wr_addr${i} ) +//: ,.cdma2buf_wt_wr_data${i} (cdma2buf_wt_wr_data${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) +//: ); +//: } +//,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr ) +//,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_hsel) +//,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data ) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.wt2status_state (wt2status_state[1:0]) + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels ) + ,.cdma2sc_wt_entries (cdma2sc_wt_entries ) + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries_f ) // + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels ) + ,.sc2cdma_wt_entries (sc2cdma_wt_entries ) + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries ) + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) + ,.nvdla_core_ng_clk (nvdla_core_clk) + ,.reg2dp_arb_weight (reg2dp_arb_weight[3:0]) + ,.reg2dp_arb_wmb (reg2dp_arb_wmb[3:0]) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_weight_reuse (reg2dp_weight_reuse[0]) + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls[0]) + ,.reg2dp_weight_format (reg2dp_weight_format[0]) + ,.reg2dp_byte_per_kernel (reg2dp_byte_per_kernel[17:0]) + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) + ,.reg2dp_weight_ram_type (reg2dp_weight_ram_type[0]) + ,.reg2dp_weight_addr_high (reg2dp_weight_addr_high[31:0]) +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: ,.reg2dp_weight_addr_low (reg2dp_weight_addr_low[31:${atmbw}]) +//: ,.reg2dp_wgs_addr_low (reg2dp_wgs_addr_low[31:${atmbw}]) +//: ,.reg2dp_wmb_addr_low (reg2dp_wmb_addr_low[31:${atmbw}]) +//: ); + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) + ,.reg2dp_wgs_addr_high (reg2dp_wgs_addr_high[31:0]) + ,.reg2dp_wmb_addr_high (reg2dp_wmb_addr_high[31:0]) + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero[0]) + ,.reg2dp_dma_en (reg2dp_dma_en[0]) + ,.dp2reg_nan_weight_num (dp2reg_nan_weight_num[31:0]) + ,.dp2reg_inf_weight_num (dp2reg_inf_weight_num[31:0]) + ,.dp2reg_wt_flush_done (dp2reg_wt_flush_done) + ,.dp2reg_wt_rd_stall (dp2reg_wt_rd_stall[31:0]) + ,.dp2reg_wt_rd_latency (dp2reg_wt_rd_latency[31:0]) + ); +//-------------- SLCG for weight DMA --------------// +NV_NVDLA_CDMA_slcg u_slcg_wt ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[0]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_wt) + ); +//========================================================== +// Direct convolution DMA +//========================================================== +NV_NVDLA_CDMA_dc u_dc ( + .nvdla_core_clk (nvdla_op_gated_clk_dc) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dc_dat2mcif_rd_req_valid (dc_dat2mcif_rd_req_valid) + ,.dc_dat2mcif_rd_req_ready (dc_dat2mcif_rd_req_ready) + ,.dc_dat2mcif_rd_req_pd (dc_dat2mcif_rd_req_pd) + ,.mcif2dc_dat_rd_rsp_valid (mcif2dc_dat_rd_rsp_valid) + ,.mcif2dc_dat_rd_rsp_ready (mcif2dc_dat_rd_rsp_ready) + ,.mcif2dc_dat_rd_rsp_pd (mcif2dc_dat_rd_rsp_pd) + ,.dc2cvt_dat_wr_en (dc2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,.dc2cvt_dat_wr_sel (dc2cvt_dat_wr_sel) +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.dc2cvt_dat_wr_mask (dc2cvt_dat_wr_mask) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.dc2cvt_dat_wr_addr${i} (dc2cvt_dat_wr_addr${i}) +//: ,.dc2cvt_dat_wr_data${i} (dc2cvt_dat_wr_data${i}) +//: ); +//: } +//: } else { +//: print qq( +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } + ,.dc2cvt_dat_wr_info_pd (dc2cvt_dat_wr_info_pd[11:0]) +// ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +// ,.dc2cvt_dat_wr_sel (dc2cvt_dat_wr_hsel) +// ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.dc2status_state (dc2status_state[1:0]) + ,.dc2status_dat_updt (dc2status_dat_updt) + ,.dc2status_dat_entries (dc2status_dat_entries ) + ,.dc2status_dat_slices (dc2status_dat_slices ) + ,.status2dma_valid_slices (status2dma_valid_slices) + ,.status2dma_free_entries (status2dma_free_entries) + ,.status2dma_wr_idx (status2dma_wr_idx) +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,.dc2sbuf_p${i}_wr_en (dc2sbuf_p${i}_wr_en ) +//: ,.dc2sbuf_p${i}_wr_addr (dc2sbuf_p${i}_wr_addr ) +//: ,.dc2sbuf_p${i}_wr_data (dc2sbuf_p${i}_wr_data ) +//: ,.dc2sbuf_p${i}_rd_en (dc2sbuf_p${i}_rd_en ) +//: ,.dc2sbuf_p${i}_rd_addr (dc2sbuf_p${i}_rd_addr ) +//: ,.dc2sbuf_p${i}_rd_data (dc2sbuf_p${i}_rd_data ) +//: ); +//: } +// ,.dc2sbuf_p0_wr_en (dc2sbuf_p0_wr_en) +// ,.dc2sbuf_p0_wr_addr (dc2sbuf_p0_wr_addr) +// ,.dc2sbuf_p0_wr_data (dc2sbuf_p0_wr_data) +// ,.dc2sbuf_p0_rd_en (dc2sbuf_p0_rd_en) +// ,.dc2sbuf_p0_rd_addr (dc2sbuf_p0_rd_addr) +// ,.dc2sbuf_p0_rd_data (dc2sbuf_p0_rd_data) +// ,.dc2sbuf_p1_wr_en (dc2sbuf_p1_wr_en) +// ,.dc2sbuf_p1_wr_addr (dc2sbuf_p1_wr_addr) +// ,.dc2sbuf_p1_wr_data (dc2sbuf_p1_wr_data) +// ,.dc2sbuf_p1_rd_en (dc2sbuf_p1_rd_en) +// ,.dc2sbuf_p1_rd_addr (dc2sbuf_p1_rd_addr) +// ,.dc2sbuf_p1_rd_data (dc2sbuf_p1_rd_data) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.nvdla_core_ng_clk (nvdla_core_clk) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) + ,.reg2dp_datain_format (reg2dp_datain_format[0]) + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type[0]) + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) +//: my $atmm = 8; +//: my $atmbw = int(log(${atmm})/log(2)); +//: print qq( +//: ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:${atmbw}]) +//: ,.reg2dp_batch_stride (reg2dp_batch_stride[31:${atmbw}]) +//: ,.reg2dp_line_stride (reg2dp_line_stride[31:${atmbw}]) +//: ,.reg2dp_surf_stride (reg2dp_surf_stride[31:${atmbw}]) +//: ); + ,.reg2dp_line_packed (reg2dp_line_packed[0]) + ,.reg2dp_surf_packed (reg2dp_surf_packed[0]) + ,.reg2dp_batches (reg2dp_batches[4:0]) + ,.reg2dp_entries ({3'd0,reg2dp_entries[13:0]}) // + ,.reg2dp_grains (reg2dp_grains[11:0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.reg2dp_dma_en (reg2dp_dma_en[0]) + ,.slcg_dc_gate_wg (slcg_dc_gate_wg) + ,.slcg_dc_gate_img (slcg_dc_gate_img) + ,.dp2reg_dc_rd_stall (dp2reg_dc_rd_stall[31:0]) + ,.dp2reg_dc_rd_latency (dp2reg_dc_rd_latency[31:0]) + ); +//-------------- SLCG for DC DMA --------------// +NV_NVDLA_CDMA_slcg u_slcg_dc ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[1]) + ,.slcg_en_src_1 (slcg_wg_gate_dc) + ,.slcg_en_src_2 (slcg_img_gate_dc) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_dc) + ); +assign slcg_wg_gate_dc = 1'b1; +assign slcg_wg_gate_img = 1'b1; +assign dp2reg_wg_rd_latency = 32'b0; +assign dp2reg_wg_rd_stall = 32'b0; +//========================================================== +// Image convolution DMA +//========================================================== +NV_NVDLA_CDMA_img u_img ( + .nvdla_core_clk (nvdla_op_gated_clk_img) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.img_dat2mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.img_dat2mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.img_dat2mcif_rd_req_pd (img_dat2mcif_rd_req_pd) + ,.mcif2img_dat_rd_rsp_valid (mcif2img_dat_rd_rsp_valid) + ,.mcif2img_dat_rd_rsp_ready (mcif2img_dat_rd_rsp_ready) + ,.mcif2img_dat_rd_rsp_pd (mcif2img_dat_rd_rsp_pd) + ,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_sel (img2cvt_dat_wr_sel ) +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_mask (img2cvt_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.img2cvt_dat_wr_addr${i} (img2cvt_dat_wr_addr${i} ) +//: ,.img2cvt_dat_wr_data${i} (img2cvt_dat_wr_data${i} ) +//: ,.img2cvt_mn_wr_data${i} (img2cvt_mn_wr_data${i} ) +//: ,.img2cvt_dat_wr_pad_mask${i} (img2cvt_dat_wr_pad_mask${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } +//,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) //|> w +//,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr[11:0]) //|> w +//,.img2cvt_dat_wr_sel (img2cvt_dat_wr_hsel) //|> w +//,.img2cvt_dat_wr_data (img2cvt_dat_wr_data[1023:0]) //|> w +//,.img2cvt_mn_wr_data (img2cvt_mn_wr_data[1023:0]) //|> w + ,.img2cvt_dat_wr_info_pd (img2cvt_dat_wr_info_pd[11:0]) //|> w + ,.status2dma_fsm_switch (status2dma_fsm_switch) //|< w + ,.img2status_state (img2status_state[1:0]) //|> w + ,.img2status_dat_updt (img2status_dat_updt) //|> w + ,.img2status_dat_entries (img2status_dat_entries[14:0]) //|> w + ,.img2status_dat_slices (img2status_dat_slices) //|> w + ,.status2dma_valid_slices (status2dma_valid_slices) //|< w + ,.status2dma_free_entries (status2dma_free_entries[14:0]) //|< w + ,.status2dma_wr_idx (status2dma_wr_idx) //|< w +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,.img2sbuf_p${i}_wr_en (img2sbuf_p${i}_wr_en ) +//: ,.img2sbuf_p${i}_wr_addr (img2sbuf_p${i}_wr_addr ) +//: ,.img2sbuf_p${i}_wr_data (img2sbuf_p${i}_wr_data ) +//: ,.img2sbuf_p${i}_rd_en (img2sbuf_p${i}_rd_en ) +//: ,.img2sbuf_p${i}_rd_addr (img2sbuf_p${i}_rd_addr ) +//: ,.img2sbuf_p${i}_rd_data (img2sbuf_p${i}_rd_data ) +//: ); +//: } +//,.img2sbuf_p0_wr_en (img2sbuf_p0_wr_en) //|> w +//,.img2sbuf_p0_wr_addr (img2sbuf_p0_wr_addr[7:0]) //|> w +//,.img2sbuf_p0_wr_data (img2sbuf_p0_wr_data[255:0]) //|> w +//,.img2sbuf_p0_rd_en (img2sbuf_p0_rd_en) //|> w +//,.img2sbuf_p0_rd_addr (img2sbuf_p0_rd_addr[7:0]) //|> w +//,.img2sbuf_p0_rd_data (img2sbuf_p0_rd_data[255:0]) //|< w +//,.img2sbuf_p1_wr_en (img2sbuf_p1_wr_en) //|> w +//,.img2sbuf_p1_wr_addr (img2sbuf_p1_wr_addr[7:0]) //|> w +//,.img2sbuf_p1_wr_data (img2sbuf_p1_wr_data[255:0]) //|> w +//,.img2sbuf_p1_rd_en (img2sbuf_p1_rd_en) //|> w +//,.img2sbuf_p1_rd_addr (img2sbuf_p1_rd_addr[7:0]) //|> w +//,.img2sbuf_p1_rd_data (img2sbuf_p1_rd_data[255:0]) //|< w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|< i + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) //|< w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) //|< w + ,.reg2dp_datain_format (reg2dp_datain_format[0]) //|< w + ,.reg2dp_pixel_format (reg2dp_pixel_format[5:0]) //|< w + ,.reg2dp_pixel_mapping (reg2dp_pixel_mapping[0]) //|< w + ,.reg2dp_pixel_sign_override (reg2dp_pixel_sign_override[0]) //|< w + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) //|< w + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) //|< w + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) //|< w + ,.reg2dp_pixel_x_offset (reg2dp_pixel_x_offset[4:0]) //|< w + ,.reg2dp_pixel_y_offset (reg2dp_pixel_y_offset[2:0]) //|< w + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type[0]) //|< w + ,.reg2dp_datain_addr_high_0 (reg2dp_datain_addr_high_0[31:0]) //|< w + ,.reg2dp_datain_addr_low_0 (reg2dp_datain_addr_low_0[31:0]) + ,.reg2dp_datain_addr_high_1 (reg2dp_datain_addr_high_1[31:0]) //|< w + ,.reg2dp_datain_addr_low_1 (reg2dp_datain_addr_low_1[31:0]) //|< w + ,.reg2dp_line_stride (reg2dp_line_stride[31:0]) //|< w + ,.reg2dp_uv_line_stride (reg2dp_uv_line_stride[31:0]) //|< w + ,.reg2dp_mean_format (reg2dp_mean_format[0]) //|< w + ,.reg2dp_mean_ry (reg2dp_mean_ry[15:0]) //|< w + ,.reg2dp_mean_gu (reg2dp_mean_gu[15:0]) //|< w + ,.reg2dp_mean_bv (reg2dp_mean_bv[15:0]) //|< w + ,.reg2dp_mean_ax (reg2dp_mean_ax[15:0]) //|< w + ,.reg2dp_entries (reg2dp_entries[13:0]) //|< w + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) //|< w + ,.reg2dp_pad_right (reg2dp_pad_right[5:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_dma_en (reg2dp_dma_en[0]) //|< w + ,.reg2dp_rsv_per_line (reg2dp_rsv_per_line[9:0]) //|< w + ,.reg2dp_rsv_per_uv_line (reg2dp_rsv_per_uv_line[9:0]) //|< w + ,.reg2dp_rsv_height (reg2dp_rsv_height[2:0]) //|< w + ,.reg2dp_rsv_y_index (reg2dp_rsv_y_index[4:0]) //|< w + ,.slcg_img_gate_dc (slcg_img_gate_dc) //|> w + ,.slcg_img_gate_wg (slcg_img_gate_wg) //|> w + ,.dp2reg_img_rd_stall (dp2reg_img_rd_stall[31:0]) //|> w + ,.dp2reg_img_rd_latency (dp2reg_img_rd_latency[31:0]) //|> w +//,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask[127:0]) //|> w + ); +// +wire img2sbuf_p1_wr_en; +wire [7:0] img2sbuf_p1_wr_addr; +wire [8*8 -1:0] img2sbuf_p1_wr_data; +wire img2sbuf_p1_rd_en; +wire [7:0] img2sbuf_p1_rd_addr; + assign img2sbuf_p1_wr_en = 1'b0; + assign img2sbuf_p1_wr_addr = 8'b0; + assign img2sbuf_p1_wr_data = 64'b0; + assign img2sbuf_p1_rd_en = 1'b0; + assign img2sbuf_p1_rd_addr = 8'b0; +//-------------- SLCG for IMG DMA --------------// +NV_NVDLA_CDMA_slcg u_slcg_img ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[3]) + ,.slcg_en_src_1 (slcg_dc_gate_img) + ,.slcg_en_src_2 (slcg_wg_gate_img) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_img) + ); +//========================================================== +// DMA mux +//========================================================== +NV_NVDLA_CDMA_dma_mux u_dma_mux ( + .nvdla_core_clk (nvdla_op_gated_clk_mux) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dc_dat2mcif_rd_req_valid (dc_dat2mcif_rd_req_valid) + ,.dc_dat2mcif_rd_req_ready (dc_dat2mcif_rd_req_ready) + ,.dc_dat2mcif_rd_req_pd (dc_dat2mcif_rd_req_pd) + ,.img_dat2mcif_rd_req_valid (img_dat2mcif_rd_req_valid) + ,.img_dat2mcif_rd_req_ready (img_dat2mcif_rd_req_ready) + ,.img_dat2mcif_rd_req_pd (img_dat2mcif_rd_req_pd) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd) + ,.mcif2dc_dat_rd_rsp_valid (mcif2dc_dat_rd_rsp_valid) + ,.mcif2dc_dat_rd_rsp_ready (mcif2dc_dat_rd_rsp_ready) + ,.mcif2dc_dat_rd_rsp_pd (mcif2dc_dat_rd_rsp_pd) + ,.mcif2img_dat_rd_rsp_valid (mcif2img_dat_rd_rsp_valid) + ,.mcif2img_dat_rd_rsp_ready (mcif2img_dat_rd_rsp_ready) + ,.mcif2img_dat_rd_rsp_pd (mcif2img_dat_rd_rsp_pd) + ); +//-------------- SLCG for MUX --------------// +NV_NVDLA_CDMA_slcg u_slcg_mux ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[4]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_mux) + ); +//========================================================== +// DMA data convertor +//========================================================== +NV_NVDLA_CDMA_cvt u_cvt ( + .nvdla_core_clk (nvdla_op_gated_clk_cvt) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dc2cvt_dat_wr_en (dc2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: print qq( +//: ,.dc2cvt_dat_wr_sel (dc2cvt_dat_wr_sel) +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.dc2cvt_dat_wr_mask (dc2cvt_dat_wr_mask) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.dc2cvt_dat_wr_addr${i} (dc2cvt_dat_wr_addr${i}) +//: ,.dc2cvt_dat_wr_data${i} (dc2cvt_dat_wr_data${i}) +//: ); +//: } +//: } else { +//: print qq( +//: ,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//: ,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) +//: ); +//: } + ,.dc2cvt_dat_wr_info_pd (dc2cvt_dat_wr_info_pd[11:0]) +//,.dc2cvt_dat_wr_addr (dc2cvt_dat_wr_addr) +//,.dc2cvt_dat_wr_hsel (dc2cvt_dat_wr_hsel) +//,.dc2cvt_dat_wr_data (dc2cvt_dat_wr_data) + ,.img2cvt_dat_wr_en (img2cvt_dat_wr_en) +//: my $dmaif=64; +//: my $Bnum = $dmaif / 8; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_sel (img2cvt_dat_wr_sel ) +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.img2cvt_dat_wr_mask (img2cvt_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.img2cvt_dat_wr_addr${i} (img2cvt_dat_wr_addr${i} ) +//: ,.img2cvt_dat_wr_data${i} (img2cvt_dat_wr_data${i} ) +//: ,.img2cvt_mn_wr_data${i} (img2cvt_mn_wr_data${i} ) +//: ,.img2cvt_dat_wr_pad_mask${i} (img2cvt_dat_wr_pad_mask${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr ) +//: ,.img2cvt_dat_wr_data (img2cvt_dat_wr_data ) +//: ,.img2cvt_mn_wr_data (img2cvt_mn_wr_data ) +//: ,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask ) +//: ); +//: } +//,.img2cvt_dat_wr_addr (img2cvt_dat_wr_addr) +//,.img2cvt_dat_wr_hsel (img2cvt_dat_wr_hsel) +//,.img2cvt_dat_wr_data (img2cvt_dat_wr_data) +//,.img2cvt_mn_wr_data (img2cvt_mn_wr_data) + ,.img2cvt_dat_wr_info_pd (img2cvt_dat_wr_info_pd[11:0]) + ,.cdma2buf_dat_wr_en (cdma2buf_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_dat_wr_sel (cdma2buf_dat_wr_sel ) +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr ) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data ) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.cdma2buf_dat_wr_mask (cdma2buf_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_dat_wr_addr${i} (cdma2buf_dat_wr_addr${i} ) +//: ,.cdma2buf_dat_wr_data${i} (cdma2buf_dat_wr_data${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr ) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data ) +//: ); +//: } +//,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_hsel) +//,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) + ,.nvdla_hls_clk (nvdla_hls_gated_clk_cvt) + ,.slcg_hls_en (slcg_hls_en) + ,.nvdla_core_ng_clk (nvdla_core_clk) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_cvt_en (reg2dp_cvt_en[0]) + ,.reg2dp_cvt_truncate (reg2dp_cvt_truncate[5:0]) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[15:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero[0]) + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) + ,.dp2reg_done (dp2reg_done) +//,.img2cvt_dat_wr_pad_mask (img2cvt_dat_wr_pad_mask) + ,.dp2reg_nan_data_num (dp2reg_nan_data_num[31:0]) + ,.dp2reg_inf_data_num (dp2reg_inf_data_num[31:0]) + ,.dp2reg_dat_flush_done (dp2reg_dat_flush_done) + ); +//-------------- SLCG for CVT --------------// +NV_NVDLA_CDMA_slcg u_slcg_cvt ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[5]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_cvt) + ); +//-------------- SLCG for CVT HLS CELL --------------// +NV_NVDLA_CDMA_slcg u_slcg_hls ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[6]) + ,.slcg_en_src_1 (slcg_hls_en) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_hls_gated_clk_cvt) + ); +//========================================================== +// Shared buffer +//========================================================== +NV_NVDLA_CDMA_shared_buffer u_shared_buffer ( + .nvdla_core_clk (nvdla_op_gated_clk_buffer) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dc2sbuf_p0_wr_en (dc2sbuf_p0_wr_en) + ,.dc2sbuf_p0_wr_addr (dc2sbuf_p0_wr_addr) + ,.dc2sbuf_p0_wr_data (dc2sbuf_p0_wr_data) + ,.dc2sbuf_p0_rd_en (dc2sbuf_p0_rd_en) + ,.dc2sbuf_p0_rd_addr (dc2sbuf_p0_rd_addr) + ,.dc2sbuf_p0_rd_data (dc2sbuf_p0_rd_data) + ,.dc2sbuf_p1_wr_en (1'b0) + ,.dc2sbuf_p1_wr_addr (8'd0) + ,.dc2sbuf_p1_wr_data ({8*8{1'b0}}) + ,.dc2sbuf_p1_rd_en (1'b0) + ,.dc2sbuf_p1_rd_addr (8'd0) + ,.dc2sbuf_p1_rd_data ( ) + ,.img2sbuf_p0_wr_en (img2sbuf_p0_wr_en) + ,.img2sbuf_p0_wr_addr (img2sbuf_p0_wr_addr) + ,.img2sbuf_p0_wr_data (img2sbuf_p0_wr_data) + ,.img2sbuf_p1_wr_en (img2sbuf_p1_wr_en) + ,.img2sbuf_p1_wr_addr (img2sbuf_p1_wr_addr) + ,.img2sbuf_p1_wr_data (img2sbuf_p1_wr_data) + ,.img2sbuf_p0_rd_en (img2sbuf_p0_rd_en) + ,.img2sbuf_p0_rd_addr (img2sbuf_p0_rd_addr) + ,.img2sbuf_p1_rd_en (img2sbuf_p1_rd_en) + ,.img2sbuf_p1_rd_addr (img2sbuf_p1_rd_addr) + ,.img2sbuf_p1_rd_data ( ) +//: my $dmaif=64; +//: my $atmm = 8*8; ##atomic_m BW +//: my $M = $dmaif/$atmm; ##atomic_m number per dma transaction +//: foreach my $i (0..$M-1) { +//: print qq( +//: ,.img2sbuf_p${i}_rd_data (img2sbuf_p${i}_rd_data ) +//: ); +//: } + ); +//-------------- SLCG for shared buffer --------------// +NV_NVDLA_CDMA_slcg u_slcg_buffer ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src_0 (slcg_op_en[7]) + ,.slcg_en_src_1 (1'b1) + ,.slcg_en_src_2 (1'b1) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_buffer) + ); +//========================================================== +// CDMA status controller +//========================================================== +NV_NVDLA_CDMA_status u_status ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dc2status_dat_updt (dc2status_dat_updt) + ,.dc2status_dat_entries (dc2status_dat_entries) + ,.dc2status_dat_slices (dc2status_dat_slices) + ,.img2status_dat_updt (img2status_dat_updt) + ,.img2status_dat_entries (img2status_dat_entries) + ,.img2status_dat_slices (img2status_dat_slices) + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) + ,.sc2cdma_dat_entries (sc2cdma_dat_entries) + ,.sc2cdma_dat_slices (sc2cdma_dat_slices) + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) + ,.cdma2sc_dat_entries (cdma2sc_dat_entries) + ,.cdma2sc_dat_slices (cdma2sc_dat_slices) + ,.status2dma_valid_slices (status2dma_valid_slices) + ,.status2dma_free_entries (status2dma_free_entries) + ,.status2dma_wr_idx (status2dma_wr_idx) + ,.dc2status_state (dc2status_state[1:0]) + ,.img2status_state (img2status_state[1:0]) + ,.wt2status_state (wt2status_state[1:0]) + ,.dp2reg_done (dp2reg_done) + ,.status2dma_fsm_switch (status2dma_fsm_switch) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) + ,.reg2dp_op_en (reg2dp_op_en[0]) + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) + ,.dp2reg_consumer (dp2reg_consumer) + ); +//////////////////////////////////////////////////////////////////////// +// dangle not connected signals // +//////////////////////////////////////////////////////////////////////// +///////////////////// dangles from NV_NVDLA_CDMA_regfile ///////////////////// +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_zero_one_hot #(0,3,0,"Error! DC, WG and IMG slcg gate signal conflict!") zzz_assert_zero_one_hot_1x (nvdla_core_clk, `ASSERT_RESET, ({~slcg_dc_gate_wg, ~slcg_wg_gate_img, ~slcg_img_gate_dc})); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Two DC slcg signal mismatch!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (slcg_dc_gate_wg ^ slcg_dc_gate_img)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Two WG slcg signal mismatch!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (slcg_wg_gate_dc ^ slcg_wg_gate_img)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! Two IMG slcg signal mismatch!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (slcg_img_gate_dc ^ slcg_img_gate_wg)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_cdma diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v new file mode 100644 index 0000000..a9589d5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v @@ -0,0 +1,225 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_INTP_unit.v +module NV_NVDLA_CDP_DP_INTP_unit ( + nvdla_core_clk + ,nvdla_core_rstn + ,interp_in0_pd + ,interp_in1_pd + ,interp_in_pd + ,interp_in_scale + ,interp_in_shift + ,interp_in_vld + ,interp_out_rdy + ,interp_in_rdy + ,interp_out_pd + ,interp_out_vld + ); +///////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [38:0] interp_in0_pd; +input [37:0] interp_in1_pd; +input [16:0] interp_in_pd; +input [16:0] interp_in_scale; +input [5:0] interp_in_shift; +input interp_in_vld; +input interp_out_rdy; +output interp_in_rdy; +output [16:0] interp_out_pd; +output interp_out_vld; +///////////////////////////////////////////////////////////////// +reg [88:0] int_add; +reg [56:0] int_mul; +reg [57:0] int_mul_for_Rshift; +reg [39:0] int_sub; +reg int_vld_d0; +reg int_vld_d1; +reg int_vld_d2; +reg [16:0] interp_in0_pd_d0; +reg [16:0] interp_in0_pd_d1; +reg [16:0] interp_in_offset_d0; +reg [5:0] interp_in_shift_d0; +reg [5:0] interp_in_shift_d1; +wire int_in_load; +wire int_in_load_d0; +wire int_in_load_d1; +wire int_in_rdy; +wire int_in_vld; +wire [15:0] int_interp_out_pd; +wire [87:0] int_mul_rs; +wire [31:0] int_mul_shift_frac; +wire [87:0] int_mul_shift_int; +wire int_rdy_d0; +wire int_rdy_d1; +wire int_rdy_d2; +wire [5:0] interp_in_shift_abs; +wire [4:0] intp_in_shift_inv; +wire [5:0] intp_in_shift_inv_inc; +///////////////////////////////////////////////////////////////// +/////////////////////////////////////////// +//interp_in_vld +assign interp_in_rdy = int_in_rdy; +/////////////////////////////////////////// +assign int_in_vld = interp_in_vld; +assign int_in_rdy = ~int_vld_d0 | int_rdy_d0; +assign int_in_load = int_in_vld & int_in_rdy; +/////////////////// +//X1-X0 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_sub[39:0] <= {40{1'b0}}; + interp_in0_pd_d0 <= {17{1'b0}}; + interp_in_offset_d0 <= {17{1'b0}}; + interp_in_shift_d0 <= {6{1'b0}}; + end else begin + if(int_in_load) begin + int_sub[39:0] <= $signed({interp_in1_pd[37],interp_in1_pd[37:0]}) - $signed(interp_in0_pd[38:0]); + interp_in0_pd_d0 <= interp_in_pd[16:0]; + interp_in_offset_d0 <= interp_in_scale[16:0]; + interp_in_shift_d0 <= interp_in_shift[5:0]; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_vld_d0 <= 1'b0; + end else begin + if(int_in_vld) + int_vld_d0 <= 1'b1; + else if(int_rdy_d0) + int_vld_d0 <= 1'b0; + end +end +assign int_rdy_d0 = ~int_vld_d1 | int_rdy_d1; +assign int_in_load_d0 = int_vld_d0 & int_rdy_d0; +/////////////////// +//(X1-X0)*frac +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_mul[56:0] <= {57{1'b0}}; + interp_in0_pd_d1 <= {17{1'b0}}; + interp_in_shift_d1 <= {6{1'b0}}; + end else begin + if(int_in_load_d0) begin + int_mul[56:0] <= $signed(int_sub[39:0]) * $signed(interp_in_offset_d0); + interp_in0_pd_d1 <= interp_in0_pd_d0[16:0]; + interp_in_shift_d1 <= interp_in_shift_d0[5:0]; + end + end +end +//>>16 proc for ((X1-X0)*frac) >>16 +assign intp_in_shift_inv[4:0] = ~interp_in_shift_d1[4:0]; +assign intp_in_shift_inv_inc[5:0] = intp_in_shift_inv[4:0] + 5'd1; +assign interp_in_shift_abs[5:0] = interp_in_shift_d1[5] ? intp_in_shift_inv_inc[5:0]: interp_in_shift_d1[5:0]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_out of range shifter abs shouldn't out of data range of signed-int6") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, int_in_load_d1 & ((interp_in_shift_d1[5] & (interp_in_shift_abs > 6'd32)) | ((~interp_in_shift_d1[5]) & (interp_in_shift_abs > 6'd31)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign {int_mul_shift_int[87:0],int_mul_shift_frac[31:0]} = interp_in_shift_d1[5] ? {{{31{int_mul[56]}}, int_mul[56:0]},32'd0} << interp_in_shift_abs[5:0] : {{{31{int_mul[56]}}, int_mul[56:0]},32'd0} >> interp_in_shift_abs[5:0]; +//rounding process for right shift +always @( + int_mul_shift_int + or int_mul_shift_frac + ) begin +//if(int_mul_shift_int[55]) begin + if(int_mul_shift_int[56]) begin + if(int_mul_shift_frac[31]) begin + if(~(|int_mul_shift_frac[30:0])) + int_mul_for_Rshift = {int_mul_shift_int[56],int_mul_shift_int[56:0]}; + else + int_mul_for_Rshift = $signed(int_mul_shift_int[56:0]) + $signed({56'd0,1'b1}); + end else begin + int_mul_for_Rshift = {int_mul_shift_int[56],int_mul_shift_int[56:0]}; + end + end else begin + int_mul_for_Rshift = $signed(int_mul_shift_int[56:0]) + $signed({56'd0,int_mul_shift_frac[31]}); + end +end +assign int_mul_rs[87:0] = interp_in_shift_d1[5] ? int_mul_shift_int[87:0] : ({{30{int_mul_for_Rshift[57]}}, int_mul_for_Rshift[57:0]}); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_vld_d1 <= 1'b0; + end else begin + if(int_vld_d0) + int_vld_d1 <= 1'b1; + else if(int_rdy_d1) + int_vld_d1 <= 1'b0; + end +end +assign int_rdy_d1 = ~int_vld_d2 | int_rdy_d2; +assign int_in_load_d1 = int_vld_d1 & int_rdy_d1; +//Xo = X0+[(X1-X0)*frac>>16] +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_add[88:0] <= {89{1'b0}}; + end else begin + if(int_in_load_d1) begin + int_add[88:0] <= $signed(int_mul_rs[87:0]) + $signed({{71{interp_in0_pd_d1[16]}}, interp_in0_pd_d1[16:0]}); + end + end +end +assign int_interp_out_pd[15:0] = int_add[88] ? (&int_add[88:15] ? {int_add[88],int_add[14:0]} : 16'h8000) : (|int_add[88:15] ? 16'h7fff : int_add[15:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_vld_d2 <= 1'b0; + end else begin + if(int_vld_d1) + int_vld_d2 <= 1'b1; + else if(int_rdy_d2) + int_vld_d2 <= 1'b0; + end +end +assign int_rdy_d2 = interp_out_rdy; +////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////// +assign interp_out_vld = int_vld_d2; +assign interp_out_pd[16:0] = {int_interp_out_pd[15],int_interp_out_pd[15:0]}; +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_INTP_unit diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v.vcp new file mode 100644 index 0000000..a9589d5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v.vcp @@ -0,0 +1,225 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_INTP_unit.v +module NV_NVDLA_CDP_DP_INTP_unit ( + nvdla_core_clk + ,nvdla_core_rstn + ,interp_in0_pd + ,interp_in1_pd + ,interp_in_pd + ,interp_in_scale + ,interp_in_shift + ,interp_in_vld + ,interp_out_rdy + ,interp_in_rdy + ,interp_out_pd + ,interp_out_vld + ); +///////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [38:0] interp_in0_pd; +input [37:0] interp_in1_pd; +input [16:0] interp_in_pd; +input [16:0] interp_in_scale; +input [5:0] interp_in_shift; +input interp_in_vld; +input interp_out_rdy; +output interp_in_rdy; +output [16:0] interp_out_pd; +output interp_out_vld; +///////////////////////////////////////////////////////////////// +reg [88:0] int_add; +reg [56:0] int_mul; +reg [57:0] int_mul_for_Rshift; +reg [39:0] int_sub; +reg int_vld_d0; +reg int_vld_d1; +reg int_vld_d2; +reg [16:0] interp_in0_pd_d0; +reg [16:0] interp_in0_pd_d1; +reg [16:0] interp_in_offset_d0; +reg [5:0] interp_in_shift_d0; +reg [5:0] interp_in_shift_d1; +wire int_in_load; +wire int_in_load_d0; +wire int_in_load_d1; +wire int_in_rdy; +wire int_in_vld; +wire [15:0] int_interp_out_pd; +wire [87:0] int_mul_rs; +wire [31:0] int_mul_shift_frac; +wire [87:0] int_mul_shift_int; +wire int_rdy_d0; +wire int_rdy_d1; +wire int_rdy_d2; +wire [5:0] interp_in_shift_abs; +wire [4:0] intp_in_shift_inv; +wire [5:0] intp_in_shift_inv_inc; +///////////////////////////////////////////////////////////////// +/////////////////////////////////////////// +//interp_in_vld +assign interp_in_rdy = int_in_rdy; +/////////////////////////////////////////// +assign int_in_vld = interp_in_vld; +assign int_in_rdy = ~int_vld_d0 | int_rdy_d0; +assign int_in_load = int_in_vld & int_in_rdy; +/////////////////// +//X1-X0 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_sub[39:0] <= {40{1'b0}}; + interp_in0_pd_d0 <= {17{1'b0}}; + interp_in_offset_d0 <= {17{1'b0}}; + interp_in_shift_d0 <= {6{1'b0}}; + end else begin + if(int_in_load) begin + int_sub[39:0] <= $signed({interp_in1_pd[37],interp_in1_pd[37:0]}) - $signed(interp_in0_pd[38:0]); + interp_in0_pd_d0 <= interp_in_pd[16:0]; + interp_in_offset_d0 <= interp_in_scale[16:0]; + interp_in_shift_d0 <= interp_in_shift[5:0]; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_vld_d0 <= 1'b0; + end else begin + if(int_in_vld) + int_vld_d0 <= 1'b1; + else if(int_rdy_d0) + int_vld_d0 <= 1'b0; + end +end +assign int_rdy_d0 = ~int_vld_d1 | int_rdy_d1; +assign int_in_load_d0 = int_vld_d0 & int_rdy_d0; +/////////////////// +//(X1-X0)*frac +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_mul[56:0] <= {57{1'b0}}; + interp_in0_pd_d1 <= {17{1'b0}}; + interp_in_shift_d1 <= {6{1'b0}}; + end else begin + if(int_in_load_d0) begin + int_mul[56:0] <= $signed(int_sub[39:0]) * $signed(interp_in_offset_d0); + interp_in0_pd_d1 <= interp_in0_pd_d0[16:0]; + interp_in_shift_d1 <= interp_in_shift_d0[5:0]; + end + end +end +//>>16 proc for ((X1-X0)*frac) >>16 +assign intp_in_shift_inv[4:0] = ~interp_in_shift_d1[4:0]; +assign intp_in_shift_inv_inc[5:0] = intp_in_shift_inv[4:0] + 5'd1; +assign interp_in_shift_abs[5:0] = interp_in_shift_d1[5] ? intp_in_shift_inv_inc[5:0]: interp_in_shift_d1[5:0]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_out of range shifter abs shouldn't out of data range of signed-int6") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, int_in_load_d1 & ((interp_in_shift_d1[5] & (interp_in_shift_abs > 6'd32)) | ((~interp_in_shift_d1[5]) & (interp_in_shift_abs > 6'd31)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign {int_mul_shift_int[87:0],int_mul_shift_frac[31:0]} = interp_in_shift_d1[5] ? {{{31{int_mul[56]}}, int_mul[56:0]},32'd0} << interp_in_shift_abs[5:0] : {{{31{int_mul[56]}}, int_mul[56:0]},32'd0} >> interp_in_shift_abs[5:0]; +//rounding process for right shift +always @( + int_mul_shift_int + or int_mul_shift_frac + ) begin +//if(int_mul_shift_int[55]) begin + if(int_mul_shift_int[56]) begin + if(int_mul_shift_frac[31]) begin + if(~(|int_mul_shift_frac[30:0])) + int_mul_for_Rshift = {int_mul_shift_int[56],int_mul_shift_int[56:0]}; + else + int_mul_for_Rshift = $signed(int_mul_shift_int[56:0]) + $signed({56'd0,1'b1}); + end else begin + int_mul_for_Rshift = {int_mul_shift_int[56],int_mul_shift_int[56:0]}; + end + end else begin + int_mul_for_Rshift = $signed(int_mul_shift_int[56:0]) + $signed({56'd0,int_mul_shift_frac[31]}); + end +end +assign int_mul_rs[87:0] = interp_in_shift_d1[5] ? int_mul_shift_int[87:0] : ({{30{int_mul_for_Rshift[57]}}, int_mul_for_Rshift[57:0]}); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_vld_d1 <= 1'b0; + end else begin + if(int_vld_d0) + int_vld_d1 <= 1'b1; + else if(int_rdy_d1) + int_vld_d1 <= 1'b0; + end +end +assign int_rdy_d1 = ~int_vld_d2 | int_rdy_d2; +assign int_in_load_d1 = int_vld_d1 & int_rdy_d1; +//Xo = X0+[(X1-X0)*frac>>16] +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_add[88:0] <= {89{1'b0}}; + end else begin + if(int_in_load_d1) begin + int_add[88:0] <= $signed(int_mul_rs[87:0]) + $signed({{71{interp_in0_pd_d1[16]}}, interp_in0_pd_d1[16:0]}); + end + end +end +assign int_interp_out_pd[15:0] = int_add[88] ? (&int_add[88:15] ? {int_add[88],int_add[14:0]} : 16'h8000) : (|int_add[88:15] ? 16'h7fff : int_add[15:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_vld_d2 <= 1'b0; + end else begin + if(int_vld_d1) + int_vld_d2 <= 1'b1; + else if(int_rdy_d2) + int_vld_d2 <= 1'b0; + end +end +assign int_rdy_d2 = interp_out_rdy; +////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////////////// +assign interp_out_vld = int_vld_d2; +assign interp_out_pd[16:0] = {int_interp_out_pd[15],int_interp_out_pd[15:0]}; +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_INTP_unit diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v new file mode 100644 index 0000000..d48cfc4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v @@ -0,0 +1,912 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_LUT_CTRL_unit.v +module NV_NVDLA_CDP_DP_LUT_CTRL_unit ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2lut_prdy + ,reg2dp_lut_le_function + ,reg2dp_lut_le_index_offset + ,reg2dp_lut_le_index_select + ,reg2dp_lut_le_start_high + ,reg2dp_lut_le_start_low + ,reg2dp_lut_lo_index_select + ,reg2dp_lut_lo_start_high + ,reg2dp_lut_lo_start_low + ,reg2dp_sqsum_bypass + ,sum2itp_pd + ,sum2itp_pvld + ,dp2lut_X_info + ,dp2lut_X_pd + ,dp2lut_Y_info + ,dp2lut_Y_pd + ,dp2lut_pvld + ,sum2itp_prdy + ); +/////////////////////////////////////////////////// +parameter pINT8_BW = 8 +1;//int8 bitwidth after icvt +parameter pPP_BW = (pINT8_BW + pINT8_BW) -1 + 4;//(pINT8_BW * pINT8_BW) -1 is for int8 mode x^2, +4 is after 9 lrn +/////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [pPP_BW-1:0] sum2itp_pd; +input sum2itp_pvld; +output sum2itp_prdy; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [7:0] reg2dp_lut_le_index_select; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [7:0] reg2dp_lut_lo_index_select; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_sqsum_bypass; +output [17:0] dp2lut_X_info; +output [9:0] dp2lut_X_pd; +output [17:0] dp2lut_Y_info; +output [9:0] dp2lut_Y_pd; +output dp2lut_pvld; +input dp2lut_prdy; +/////////////////////////////////////////////////// +reg X_exp; +reg X_int8_oflow_msb; +reg [15:0] X_lin_frac_int8_msb; +reg Y_dat_info_shift; +reg [pPP_BW:0] Y_dec_offset_msb; +reg Y_int8_oflow_msb; +reg Y_less_than_win_s; +reg [15:0] Y_lin_frac_int8_msb; +reg [7:0] Y_shift_bits; +reg [9:0] Y_shift_msb_int8; +reg [16:0] dat_info_d; +reg [16:0] dat_info_shift; +reg [pPP_BW+1:0] dec_Xindex_msb; +reg [pPP_BW:0] dec_offset_msb; +reg int_X_index_uflow_msb; +reg int_X_input_uflow_d; +reg int_X_input_uflow_msb; +reg int_Y_input_uflow_msb; +reg int_Y_stage0_pvld; +reg int_Y_stage1_pvld; +reg int_stage0_pvld; +reg int_stage1_pvld; +reg int_stage2_pvld; +reg int_stage3_pvld; +reg less_than_win_s; +reg [pPP_BW:0] log2_datout_msb; +reg [pPP_BW-1:0] log2_frac_msb; +reg [0:0] mon_Y_dec_offset_msb; +reg [0:0] mon_dec_Xindex_msb; +reg [0:0] mon_dec_offset_msb; +//reg [9:0] shift_int16; +reg [9:0] shift_msb_int8; +reg sqsum_bypass_enable; +wire [17:0] X_dat_info; +wire [15:0] X_exp_frac_msb; +wire [15:0] X_frac_msb; +wire [9:0] X_index_msb; +wire [15:0] X_lin_frac_msb; +wire X_oflow_int_msb; +wire [17:0] Y_dat_info; +wire [17:0] Y_dat_info_f; +wire [9:0] Y_index_msb; +wire [9:0] Y_index_msb_f; +wire Y_int_stage3_prdy; +wire Y_int_stage3_pvld; +wire [15:0] Y_lin_frac_msb; +wire Y_oflow_int_msb; +//wire [5:0] Y_shift_bits_int16_abs; +wire [4:0] Y_shift_bits_int8_abs; +wire [4:0] Y_shift_bits_inv; +//wire [5:0] Y_shift_bits_inv1; +//wire [37:0] Y_shift_int16_f; +//wire [63:0] Y_shift_int16_s; +wire [pPP_BW:0] Y_shift_msb_int8_f; +wire [31:0] Y_shift_msb_int8_s; +wire [16:0] dat_info; +wire [16:0] dat_info_index_sub; +wire [pPP_BW-1:0] datin_int8; +wire [pPP_BW:0] dec_Xindex_datin_msb; +wire [pPP_BW:0] dec_Yindex_msb; +wire [pPP_BW:0] dec_offset_datin_msb; +wire [pPP_BW:0] dec_offset_datin_msb_f0; +wire [pPP_BW:0] dec_offset_datin_msb_f1; +wire int_X_datin_prdy; +wire int_X_proc_in_vld; +wire int_Y_datin_prdy; +wire int_Y_proc_in_vld; +wire int_Y_stage0_prdy; +wire int_Y_stage1_prdy; +wire int_out_rdy; +wire int_out_vld; +wire int_stage0_prdy; +wire int_stage1_prdy; +wire int_stage2_in_vld; +wire int_stage2_prdy; +wire int_stage3_prdy; +wire load_din_intY; +wire load_in_intX; +wire load_int_Y_stage0; +wire load_int_stage0; +wire load_int_stage1; +wire load_int_stage2; +wire [pPP_BW:0] log2_datin_msb; +wire log2_datin_vld; +wire [7:0] reg2dp_X_index_offset; +wire [37:0] reg2dp_X_offset; +wire [37:0] reg2dp_Y_offset; +wire [7:0] shift_bits; +//wire [6:0] shift_bits_int16_abs; +wire [5:0] shift_bits_int8_abs; +wire [4:0] shift_bits_inv; +//wire [5:0] shift_bits_inv1; +//wire [38:0] shift_int16_f; +//wire [63:0] shift_int16_s; +wire [pPP_BW+1:0] shift_msb_int8_f; +wire [31:0] shift_msb_int8_s; +wire Y_stage3_out_rdy; +/////////////////////////////////////////////////// +//============== +// Work Processing +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + X_exp <= 1'b0; + end else begin + X_exp <= reg2dp_lut_le_function == 1'h0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_shift_bits[7:0] <= {8{1'b0}}; + end else begin + Y_shift_bits[7:0] <= reg2dp_lut_lo_index_select[7:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sqsum_bypass_enable <= 1'b0; + end else begin + sqsum_bypass_enable <= reg2dp_sqsum_bypass == 1'h1; + end +end +/////////////////////////////////////// +assign sum2itp_prdy = int_Y_datin_prdy & int_X_datin_prdy; +assign datin_int8 = sum2itp_pd; +/////////////////////////////////////////////////////////////////////////////////////// +//int X Y table input interlock +assign int_X_proc_in_vld = sum2itp_pvld & int_Y_datin_prdy; +assign int_Y_proc_in_vld = sum2itp_pvld & int_X_datin_prdy; +////////////////////////////////////////////////////////////////////// +// index calculation of X table +////////////////////////////////////////////////////////////////////// +//================================================= +//offset minus +//================================================= +assign reg2dp_X_offset[37:0] = {reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:0]}; +assign load_in_intX = int_X_proc_in_vld & int_X_datin_prdy; +assign dec_offset_datin_msb_f0 = {1'b0,datin_int8}; +assign dec_offset_datin_msb_f1 = {datin_int8[pPP_BW-1],datin_int8}; +assign dec_offset_datin_msb = sqsum_bypass_enable ? dec_offset_datin_msb_f1 : dec_offset_datin_msb_f0; +always @(*) begin + case({dec_offset_datin_msb[pPP_BW],reg2dp_X_offset[pPP_BW]}) + 2'b01: less_than_win_s = 1'b0; + 2'b10: less_than_win_s = 1'b1; + default: less_than_win_s = (dec_offset_datin_msb[pPP_BW:0] < reg2dp_X_offset[pPP_BW:0]) | (dec_offset_datin_msb[pPP_BW:0] == reg2dp_X_offset[pPP_BW:0]); + endcase +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_dec_offset_msb[0],dec_offset_msb[pPP_BW:0]} <= {(pPP_BW+2){1'b0}}; + int_X_input_uflow_msb <= 1'b0; + end else begin + if(load_in_intX) begin + if(less_than_win_s) begin + {mon_dec_offset_msb[0], dec_offset_msb[pPP_BW:0]} <= {(pPP_BW+2){1'b0}}; + int_X_input_uflow_msb <= 1'b1; + end else begin + {mon_dec_offset_msb[0], dec_offset_msb[pPP_BW:0]} <= ($signed(dec_offset_datin_msb) - $signed(reg2dp_X_offset[pPP_BW:0])); + int_X_input_uflow_msb <= 1'b0; + end + end + end +end +assign int_X_datin_prdy = ~int_stage0_pvld | int_stage0_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage0_pvld <= 1'b0; + end else begin + if(int_X_proc_in_vld) + int_stage0_pvld <= 1'b1; + else if(int_stage0_prdy) + int_stage0_pvld <= 1'b0; + end +end +assign int_stage0_prdy = ~int_stage1_pvld | int_stage1_prdy; +assign load_int_stage0 = int_stage0_pvld & int_stage0_prdy; +//=================================================================== +//log2 logic , bypassed when X is a linear table +assign log2_datin_msb = dec_offset_msb ; +assign log2_datin_vld = load_int_stage0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + log2_datout_msb <= {(pPP_BW+1){1'b0}}; + log2_frac_msb <= {pPP_BW{1'b0}}; + end else begin + if(log2_datin_vld) begin + if(int_X_input_uflow_msb) begin + log2_datout_msb <= {(pPP_BW+1){1'b0}}; + log2_frac_msb <= {pPP_BW{1'b0}}; + end else begin + if(X_exp) begin +//Note need modify "my $k = 21" if BW changed. +//: my $k = 21; +//: my $k1 = $k +1; +//: print qq( +//: if(log2_datin_msb[${k}]) begin +//: log2_datout_msb <= ${k1}'d${k}; +//: log2_frac_msb <= log2_datin_msb[${k}-1:0]; +//: ); +//: foreach my $m (0..$k - 2) { +//: my $i = $k - $m -1; +//: print qq( +//: end else if(log2_datin_msb[$i]) begin +//: log2_datout_msb <= ${k1}'d${i}; +//: log2_frac_msb <= {log2_datin_msb[${i}-1:0],{(${k}-${i}){1'b0}}}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(log2_datin_msb[21]) begin +log2_datout_msb <= 22'd21; +log2_frac_msb <= log2_datin_msb[21-1:0]; + +end else if(log2_datin_msb[20]) begin +log2_datout_msb <= 22'd20; +log2_frac_msb <= {log2_datin_msb[20-1:0],{(21-20){1'b0}}}; + +end else if(log2_datin_msb[19]) begin +log2_datout_msb <= 22'd19; +log2_frac_msb <= {log2_datin_msb[19-1:0],{(21-19){1'b0}}}; + +end else if(log2_datin_msb[18]) begin +log2_datout_msb <= 22'd18; +log2_frac_msb <= {log2_datin_msb[18-1:0],{(21-18){1'b0}}}; + +end else if(log2_datin_msb[17]) begin +log2_datout_msb <= 22'd17; +log2_frac_msb <= {log2_datin_msb[17-1:0],{(21-17){1'b0}}}; + +end else if(log2_datin_msb[16]) begin +log2_datout_msb <= 22'd16; +log2_frac_msb <= {log2_datin_msb[16-1:0],{(21-16){1'b0}}}; + +end else if(log2_datin_msb[15]) begin +log2_datout_msb <= 22'd15; +log2_frac_msb <= {log2_datin_msb[15-1:0],{(21-15){1'b0}}}; + +end else if(log2_datin_msb[14]) begin +log2_datout_msb <= 22'd14; +log2_frac_msb <= {log2_datin_msb[14-1:0],{(21-14){1'b0}}}; + +end else if(log2_datin_msb[13]) begin +log2_datout_msb <= 22'd13; +log2_frac_msb <= {log2_datin_msb[13-1:0],{(21-13){1'b0}}}; + +end else if(log2_datin_msb[12]) begin +log2_datout_msb <= 22'd12; +log2_frac_msb <= {log2_datin_msb[12-1:0],{(21-12){1'b0}}}; + +end else if(log2_datin_msb[11]) begin +log2_datout_msb <= 22'd11; +log2_frac_msb <= {log2_datin_msb[11-1:0],{(21-11){1'b0}}}; + +end else if(log2_datin_msb[10]) begin +log2_datout_msb <= 22'd10; +log2_frac_msb <= {log2_datin_msb[10-1:0],{(21-10){1'b0}}}; + +end else if(log2_datin_msb[9]) begin +log2_datout_msb <= 22'd9; +log2_frac_msb <= {log2_datin_msb[9-1:0],{(21-9){1'b0}}}; + +end else if(log2_datin_msb[8]) begin +log2_datout_msb <= 22'd8; +log2_frac_msb <= {log2_datin_msb[8-1:0],{(21-8){1'b0}}}; + +end else if(log2_datin_msb[7]) begin +log2_datout_msb <= 22'd7; +log2_frac_msb <= {log2_datin_msb[7-1:0],{(21-7){1'b0}}}; + +end else if(log2_datin_msb[6]) begin +log2_datout_msb <= 22'd6; +log2_frac_msb <= {log2_datin_msb[6-1:0],{(21-6){1'b0}}}; + +end else if(log2_datin_msb[5]) begin +log2_datout_msb <= 22'd5; +log2_frac_msb <= {log2_datin_msb[5-1:0],{(21-5){1'b0}}}; + +end else if(log2_datin_msb[4]) begin +log2_datout_msb <= 22'd4; +log2_frac_msb <= {log2_datin_msb[4-1:0],{(21-4){1'b0}}}; + +end else if(log2_datin_msb[3]) begin +log2_datout_msb <= 22'd3; +log2_frac_msb <= {log2_datin_msb[3-1:0],{(21-3){1'b0}}}; + +end else if(log2_datin_msb[2]) begin +log2_datout_msb <= 22'd2; +log2_frac_msb <= {log2_datin_msb[2-1:0],{(21-2){1'b0}}}; + +end else if(log2_datin_msb[1]) begin +log2_datout_msb <= 22'd1; +log2_frac_msb <= {log2_datin_msb[1-1:0],{(21-1){1'b0}}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else if(log2_datin_msb[0]) begin + log2_datout_msb <= {(pPP_BW+1){1'b0}}; + log2_frac_msb <= {pPP_BW{1'b0}}; + end + end else + log2_datout_msb <= log2_datin_msb; + end + end + end +end +assign X_exp_frac_msb = log2_frac_msb[pPP_BW-1:pPP_BW-16]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_X_input_uflow_d <= 1'b0; + end else begin + if(log2_datin_vld) + int_X_input_uflow_d <= int_X_input_uflow_msb; + end +end +assign dat_info = {int_X_input_uflow_d,X_exp_frac_msb}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage1_pvld <= 1'b0; + end else begin + if(int_stage0_pvld) + int_stage1_pvld <= 1'b1; + else if(int_stage1_prdy) + int_stage1_pvld <= 1'b0; + end +end +assign int_stage1_prdy = ~int_stage2_pvld | int_stage2_prdy; +//=================================================================== +//exp index offset , only valid for exponent table +assign reg2dp_X_index_offset[7:0] = reg2dp_lut_le_index_offset[7:0]; +assign load_int_stage1 = int_stage1_pvld & int_stage1_prdy; +assign int_stage2_in_vld = int_stage1_pvld; +assign dec_Xindex_datin_msb = log2_datout_msb; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_dec_Xindex_msb[0],dec_Xindex_msb} <= {(pPP_BW+3){1'b0}}; + int_X_index_uflow_msb <= 1'b0; + end else begin + if(load_int_stage1) begin + if(dat_info[16]) begin //uflow + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= {(pPP_BW+3){1'b0}}; + int_X_index_uflow_msb <= 1'b0; + end else if(X_exp) begin +//if((dec_Xindex_datin_msb < {{(pPP_BW+1-7){1'b0}},reg2dp_X_index_offset[6:0]}) & (~reg2dp_X_index_offset[7])) begin + if((dec_Xindex_datin_msb < {{(pPP_BW-6){1'b0}},reg2dp_X_index_offset[6:0]}) & (~reg2dp_X_index_offset[7])) begin + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= {(pPP_BW+3){1'b0}}; + int_X_index_uflow_msb <= 1'b1; + end else begin + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= $signed({1'b0,dec_Xindex_datin_msb}) - $signed({{(pPP_BW-6){reg2dp_X_index_offset[7]}},reg2dp_X_index_offset[7:0]}); + int_X_index_uflow_msb <= 1'b0; + end + end else begin + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= {2'd0,dec_Xindex_datin_msb}; + int_X_index_uflow_msb <= 1'b0; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_LUT_ctrl: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, load_int_stage2 & (|mon_dec_Xindex_msb); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_info_d <= {17{1'b0}}; + end else if ((load_int_stage1) == 1'b1) begin + dat_info_d <= dat_info; + end +end +assign dat_info_index_sub = {dat_info_d[16] | int_X_index_uflow_msb, dat_info_d[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage2_pvld <= 1'b0; + end else begin + if(int_stage2_in_vld) + int_stage2_pvld <= 1'b1; + else if(int_stage2_prdy) + int_stage2_pvld <= 1'b0; + end +end +assign int_stage2_prdy = ~int_stage3_pvld | int_stage3_prdy; +assign load_int_stage2 = int_stage2_pvld & int_stage2_prdy; +//=================================================================== +//shift process for int8/int16, linear only, shift "0" when exponent X +assign shift_bits[7:0] = X_exp ? 8'd0 : reg2dp_lut_le_index_select[7:0]; +//note for int16 should be: assign shift_bits_inv1[5:0] = ~shift_bits[5:0]; +//note for int16 should be: assign shift_bits_int16_abs[6:0] = shift_bits[6]? (shift_bits_inv1[5:0]+1) : shift_bits[5:0]; +//note for int16 should be: assign {shift_int16_s[63:0], shift_int16_f[38:0] } = shift_bits[6]? ({64'd0,dec_Xindex_lsb[38:0]}<>shift_bits_int16_abs); +assign shift_bits_inv[4:0] = ~shift_bits[4:0]; +assign shift_bits_int8_abs[5:0] = shift_bits[5]? (shift_bits_inv[4:0] +1) : shift_bits[4:0]; +assign {shift_msb_int8_s[31:0],shift_msb_int8_f[pPP_BW+1:0]} = shift_bits[5]? ({32'd0,dec_Xindex_msb}<>shift_bits_int8_abs ); +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// shift_int16[9:0] <= {10{1'b0}}; +// X_int16_oflow <= 1'b0; +// end else begin +// if(load_int_stage2) begin +// if(dat_info_index_sub[32]) begin //lsb uflow +// shift_int16[9:0] <= 10'd0; +// X_int16_oflow <= 1'b0; +// end else if(shift_bits[6]) begin +// if({shift_int16_s,shift_int16_f} >= (65 -1)) begin +// shift_int16[9:0] <= 65 - 1; +// X_int16_oflow <= 1'b1; +// end else begin +// shift_int16[9:0] <= shift_int16_f[9:0]; +// X_int16_oflow <= 1'b0; +// end +// end else begin +// if(shift_int16_s >= (65 -1)) begin +// shift_int16[9:0] <= 65 - 1; +// X_int16_oflow <= 1'b1; +// end else begin +// shift_int16[9:0] <= shift_int16_s[9:0]; +// X_int16_oflow <= 1'b0; +// end +// end +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + shift_msb_int8[9:0] <= {10{1'b0}}; + X_int8_oflow_msb <= 1'b0; + end else begin + if(load_int_stage2) begin + if(dat_info_index_sub[16]) begin //uflow + shift_msb_int8[9:0] <= 10'd0; + X_int8_oflow_msb <= 1'b0; + end else if(shift_bits[5]) begin + if({shift_msb_int8_s,shift_msb_int8_f} >= (65 -1)) begin + shift_msb_int8[9:0] <= 65 - 1;//7'd64; + X_int8_oflow_msb <= 1'b1; + end else begin + shift_msb_int8[9:0] <= shift_msb_int8_f[9:0]; + X_int8_oflow_msb <= 1'b0; + end + end else begin + if(shift_msb_int8_s >= (65 -1)) begin + shift_msb_int8[9:0] <= 65 - 1;//7'd64; + X_int8_oflow_msb <= 1'b1; + end else begin + shift_msb_int8[9:0] <= shift_msb_int8_s[9:0]; + X_int8_oflow_msb <= 1'b0; + end + end + end + end +end +assign X_oflow_int_msb = X_int8_oflow_msb; +assign X_index_msb = shift_msb_int8; +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// X_lin_frac_int16[15:0] <= {16{1'b0}}; +// end else begin +// if(load_int_stage2) begin +// if(shift_bits[6]) +// X_lin_frac_int16[15:0] <= 16'd0; +// else +// X_lin_frac_int16[15:0] <= shift_int16_f[38:23]; +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + X_lin_frac_int8_msb[15:0] <= {16{1'b0}}; + end else begin + if(load_int_stage2) begin + if(shift_bits[5]) + X_lin_frac_int8_msb[15:0] <= 16'd0; + else + X_lin_frac_int8_msb[15:0] <= shift_msb_int8_f[pPP_BW+1:pPP_BW-14]; + end + end +end +assign X_lin_frac_msb = X_lin_frac_int8_msb; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_info_shift <= {17{1'b0}}; + end else if ((load_int_stage2) == 1'b1) begin + dat_info_shift <= dat_info_index_sub; + end +end +assign X_frac_msb = X_exp ? dat_info_shift[15:0] : X_lin_frac_msb; +assign X_dat_info = {X_oflow_int_msb,dat_info_shift[16],X_frac_msb};//oflow, uflow, frac +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP INT X table msb info: uflow and oflow occured at same time") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, int_stage3_pvld & dat_info_shift[16] & X_oflow_int_msb); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage3_pvld <= 1'b0; + end else begin + if(int_stage2_pvld) + int_stage3_pvld <= 1'b1; + else if(int_stage3_prdy) + int_stage3_pvld <= 1'b0; + end +end +//assign int_stage3_prdy = ~int_stage4_pvld | int_stage4_prdy; +//assign load_int_stage3 = int_stage3_pvld & int_stage3_prdy; +////////////////////////////////////////////////////////////////////// +//index calculation of Y table +////////////////////////////////////////////////////////////////////// +//================================================== +//input offset +//================================================== +assign reg2dp_Y_offset[37:0] = {reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:0]}; +assign load_din_intY = int_Y_proc_in_vld & int_Y_datin_prdy; +always @(*) begin + case({dec_offset_datin_msb[pPP_BW],reg2dp_Y_offset[pPP_BW]}) + 2'b01: Y_less_than_win_s = 1'b0; + 2'b10: Y_less_than_win_s = 1'b1; + default: Y_less_than_win_s = (dec_offset_datin_msb[pPP_BW:0] < reg2dp_Y_offset[pPP_BW:0]) | (dec_offset_datin_msb[pPP_BW:0] == reg2dp_Y_offset[pPP_BW:0]); + endcase +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_Y_dec_offset_msb[0],Y_dec_offset_msb} <= {(pPP_BW+2){1'b0}}; + int_Y_input_uflow_msb <= 1'b0; + end else begin + if(load_din_intY) begin + if(Y_less_than_win_s) begin + {mon_Y_dec_offset_msb[0], Y_dec_offset_msb} <= {(pPP_BW+2){1'b0}}; + int_Y_input_uflow_msb <= 1'b1; + end else begin + {mon_Y_dec_offset_msb[0], Y_dec_offset_msb} <= ($signed(dec_offset_datin_msb) - $signed(reg2dp_Y_offset[pPP_BW:0])); + int_Y_input_uflow_msb <= 1'b0; + end + end + end +end +assign int_Y_datin_prdy = ~int_Y_stage0_pvld | int_Y_stage0_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_Y_stage0_pvld <= 1'b0; + end else begin + if(int_Y_proc_in_vld) + int_Y_stage0_pvld <= 1'b1; + else if(int_Y_stage0_prdy) + int_Y_stage0_pvld <= 1'b0; + end +end +assign int_Y_stage0_prdy =~int_Y_stage1_pvld | int_Y_stage1_prdy; +assign load_int_Y_stage0 = int_Y_stage0_pvld & int_Y_stage0_prdy; +//=================================================================== +//shift process for Y int8/int16, Y is linear only +//=================================================================== +assign dec_Yindex_msb = Y_dec_offset_msb; +// note int16 should be this : assign Y_shift_bits_inv1[5:0] = ~Y_shift_bits[5:0]; +// note int16 should be this : assign Y_shift_bits_int16_abs = Y_shift_bits[6]? (Y_shift_bits_inv1[5:0]+1) : Y_shift_bits[5:0]; +// note int16 should be this : assign {Y_shift_int16_s[63:0] ,Y_shift_int16_f[37:0]} = Y_shift_bits[6]? ({64'd0,dec_Yindex_lsb[37:0]} << Y_shift_bits_int16_abs) : ({26'd0,dec_Yindex_lsb[37:0],38'd0} >> Y_shift_bits_int16_abs); +assign Y_shift_bits_inv[4:0] = ~Y_shift_bits[4:0]; +assign Y_shift_bits_int8_abs = Y_shift_bits[5]? (Y_shift_bits_inv[4:0] +1) : Y_shift_bits[4:0]; +assign {Y_shift_msb_int8_s[31:0],Y_shift_msb_int8_f} = Y_shift_bits[5]? ({32'd0,dec_Yindex_msb} << Y_shift_bits_int8_abs ) : ({10'd0,dec_Yindex_msb,22'd0} >> Y_shift_bits_int8_abs); +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// Y_shift_int16[9:0] <= {10{1'b0}}; +// Y_int16_oflow <= 1'b0; +// end else begin +// if(load_int_Y_stage0) begin +// if(int_Y_input_uflow_lsb) begin +// Y_shift_int16[9:0] <= 10'd0; +// Y_int16_oflow <= 1'b0; +// end else if(Y_shift_bits[6]) begin +// if({Y_shift_int16_s,Y_shift_int16_f} >= (257 -1)) begin +// Y_shift_int16[9:0] <= 257 - 1; +// Y_int16_oflow <= 1'b1; +// end else begin +// Y_shift_int16[9:0] <= Y_shift_int16_f[9:0]; +// Y_int16_oflow <= 1'b0; +// end +// end else begin +// if(Y_shift_int16_s >= (257 -1)) begin +// Y_shift_int16[9:0] <= 257 - 1; +// Y_int16_oflow <= 1'b1; +// end else begin +// Y_shift_int16[9:0] <= Y_shift_int16_s[9:0]; +// Y_int16_oflow <= 1'b0; +// end +// end +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_shift_msb_int8[9:0] <= {10{1'b0}}; + Y_int8_oflow_msb <= 1'b0; + end else begin + if(load_int_Y_stage0) begin + if(int_Y_input_uflow_msb) begin + Y_shift_msb_int8[9:0] <= 10'd0; + Y_int8_oflow_msb <= 1'b0; + end else if(Y_shift_bits[5]) begin + if({Y_shift_msb_int8_s,Y_shift_msb_int8_f} >= (257 -1)) begin + Y_shift_msb_int8[9:0] <= 257 - 1; + Y_int8_oflow_msb <= 1'b1; + end else begin + Y_shift_msb_int8[9:0] <= Y_shift_msb_int8_f[9:0]; + Y_int8_oflow_msb <= 1'b0; + end + end else begin + if(Y_shift_msb_int8_s >= (257 -1)) begin + Y_shift_msb_int8[9:0] <= 257 - 1; + Y_int8_oflow_msb <= 1'b1; + end else begin + Y_shift_msb_int8[9:0] <= Y_shift_msb_int8_s[9:0]; + Y_int8_oflow_msb <= 1'b0; + end + end + end + end +end +assign Y_oflow_int_msb = Y_int8_oflow_msb; +assign Y_index_msb_f = Y_shift_msb_int8; +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// Y_lin_frac_int16[15:0] <= {16{1'b0}}; +// end else begin +// if(load_int_Y_stage0) begin +// if(Y_shift_bits[6]) +// Y_lin_frac_int16[15:0] <= 16'd0; +// else +// Y_lin_frac_int16[15:0] <= Y_shift_int16_f[37:22]; +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_lin_frac_int8_msb[15:0] <= {16{1'b0}}; + end else begin + if(load_int_Y_stage0) begin + if(Y_shift_bits[5]) + Y_lin_frac_int8_msb[15:0] <= 16'd0; + else + Y_lin_frac_int8_msb[15:0] <= Y_shift_msb_int8_f[pPP_BW:pPP_BW-15]; + end + end +end +assign Y_lin_frac_msb = Y_lin_frac_int8_msb; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_dat_info_shift <= 1'b0; + end else if (load_int_Y_stage0) begin + Y_dat_info_shift <= int_Y_input_uflow_msb; + end +end +assign Y_dat_info_f = {Y_oflow_int_msb,Y_dat_info_shift,Y_lin_frac_msb}; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP INT Y table msb info: uflow and oflow occured at same time") zzz_assert_never_10x (nvdla_core_clk, `ASSERT_RESET, int_Y_stage1_pvld & Y_dat_info_shift & Y_oflow_int_msb); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_Y_stage1_pvld <= 1'b0; + end else begin + if(int_Y_stage0_pvld) + int_Y_stage1_pvld <= 1'b1; + else if(int_Y_stage1_prdy) + int_Y_stage1_pvld <= 1'b0; + end +end +//assign int_Y_stage1_prdy = Y_stage1_in_rdy; +///////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////// +//pipe delay to sync with X table +wire [27:0] Y_stage1_in_pd; +wire Y_stage1_in_vld; +wire Y_stage1_in_rdy; +reg Y_stage2_in_vld; +reg Y_stage3_out_vld; +wire Y_stage2_in_rdy; +reg [27:0] Y_stage2_in_dp; +reg [27:0] Y_stage3_out_pd; +///////////////////////////////////////////////////////////////////////// +assign int_Y_stage1_prdy = Y_stage1_in_rdy; +///////////////////////////////////////////////////////////////////////// +assign Y_stage1_in_pd = {Y_dat_info_f,Y_index_msb_f}; +assign Y_stage1_in_vld = int_Y_stage1_pvld; +///////////////////////////////// +assign Y_stage1_in_rdy = Y_stage2_in_rdy || (~Y_stage2_in_vld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage2_in_vld <= 1'b0; + end else if(Y_stage1_in_vld) begin + Y_stage2_in_vld <= 1'b1; + end else if(Y_stage2_in_rdy) begin + Y_stage2_in_vld <= 1'b0; + end +end +assign Y_stage2_in_rdy = Y_stage3_out_rdy || (~Y_stage3_out_vld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage3_out_vld <= 1'b0; + end else if(Y_stage2_in_vld) begin + Y_stage3_out_vld <= 1'b1; + end else if(Y_stage3_out_rdy) begin + Y_stage3_out_vld <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage2_in_dp <= 28'd0; + end else if(Y_stage1_in_vld & Y_stage1_in_rdy) begin + Y_stage2_in_dp <= Y_stage1_in_pd; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage3_out_pd <= 28'd0; + end else if(Y_stage2_in_vld & Y_stage2_in_rdy) begin + Y_stage3_out_pd <= Y_stage2_in_dp; + end +end +///////////////////////////////// +assign Y_index_msb = Y_stage3_out_pd[9:0]; +assign Y_dat_info = Y_stage3_out_pd[27:10]; +assign Y_int_stage3_pvld = Y_stage3_out_vld; +assign Y_stage3_out_rdy = Y_int_stage3_prdy; +//////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////// +//int X Y tables control output interlock +assign int_stage3_prdy = int_out_rdy & Y_int_stage3_pvld; +assign Y_int_stage3_prdy = int_out_rdy & int_stage3_pvld; +assign int_out_vld = int_stage3_pvld & Y_int_stage3_pvld; +//////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////// +assign dp2lut_pvld = int_out_vld; +assign int_out_rdy = dp2lut_prdy; +assign dp2lut_X_pd = {X_index_msb}; +assign dp2lut_X_info = X_dat_info; +assign dp2lut_Y_pd = {Y_index_msb}; +assign dp2lut_Y_info = Y_dat_info; +//////////// +endmodule // NV_NVDLA_CDP_DP_LUT_CTRL_unit diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v.vcp new file mode 100644 index 0000000..3ed0824 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v.vcp @@ -0,0 +1,825 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_LUT_CTRL_unit.v +module NV_NVDLA_CDP_DP_LUT_CTRL_unit ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2lut_prdy + ,reg2dp_lut_le_function + ,reg2dp_lut_le_index_offset + ,reg2dp_lut_le_index_select + ,reg2dp_lut_le_start_high + ,reg2dp_lut_le_start_low + ,reg2dp_lut_lo_index_select + ,reg2dp_lut_lo_start_high + ,reg2dp_lut_lo_start_low + ,reg2dp_sqsum_bypass + ,sum2itp_pd + ,sum2itp_pvld + ,dp2lut_X_info + ,dp2lut_X_pd + ,dp2lut_Y_info + ,dp2lut_Y_pd + ,dp2lut_pvld + ,sum2itp_prdy + ); +/////////////////////////////////////////////////// +parameter pINT8_BW = 8 +1;//int8 bitwidth after icvt +parameter pPP_BW = (pINT8_BW + pINT8_BW) -1 + 4;//(pINT8_BW * pINT8_BW) -1 is for int8 mode x^2, +4 is after 9 lrn +/////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [pPP_BW-1:0] sum2itp_pd; +input sum2itp_pvld; +output sum2itp_prdy; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [7:0] reg2dp_lut_le_index_select; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [7:0] reg2dp_lut_lo_index_select; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_sqsum_bypass; +output [17:0] dp2lut_X_info; +output [9:0] dp2lut_X_pd; +output [17:0] dp2lut_Y_info; +output [9:0] dp2lut_Y_pd; +output dp2lut_pvld; +input dp2lut_prdy; +/////////////////////////////////////////////////// +reg X_exp; +reg X_int8_oflow_msb; +reg [15:0] X_lin_frac_int8_msb; +reg Y_dat_info_shift; +reg [pPP_BW:0] Y_dec_offset_msb; +reg Y_int8_oflow_msb; +reg Y_less_than_win_s; +reg [15:0] Y_lin_frac_int8_msb; +reg [7:0] Y_shift_bits; +reg [9:0] Y_shift_msb_int8; +reg [16:0] dat_info_d; +reg [16:0] dat_info_shift; +reg [pPP_BW+1:0] dec_Xindex_msb; +reg [pPP_BW:0] dec_offset_msb; +reg int_X_index_uflow_msb; +reg int_X_input_uflow_d; +reg int_X_input_uflow_msb; +reg int_Y_input_uflow_msb; +reg int_Y_stage0_pvld; +reg int_Y_stage1_pvld; +reg int_stage0_pvld; +reg int_stage1_pvld; +reg int_stage2_pvld; +reg int_stage3_pvld; +reg less_than_win_s; +reg [pPP_BW:0] log2_datout_msb; +reg [pPP_BW-1:0] log2_frac_msb; +reg [0:0] mon_Y_dec_offset_msb; +reg [0:0] mon_dec_Xindex_msb; +reg [0:0] mon_dec_offset_msb; +//reg [9:0] shift_int16; +reg [9:0] shift_msb_int8; +reg sqsum_bypass_enable; +wire [17:0] X_dat_info; +wire [15:0] X_exp_frac_msb; +wire [15:0] X_frac_msb; +wire [9:0] X_index_msb; +wire [15:0] X_lin_frac_msb; +wire X_oflow_int_msb; +wire [17:0] Y_dat_info; +wire [17:0] Y_dat_info_f; +wire [9:0] Y_index_msb; +wire [9:0] Y_index_msb_f; +wire Y_int_stage3_prdy; +wire Y_int_stage3_pvld; +wire [15:0] Y_lin_frac_msb; +wire Y_oflow_int_msb; +//wire [5:0] Y_shift_bits_int16_abs; +wire [4:0] Y_shift_bits_int8_abs; +wire [4:0] Y_shift_bits_inv; +//wire [5:0] Y_shift_bits_inv1; +//wire [37:0] Y_shift_int16_f; +//wire [63:0] Y_shift_int16_s; +wire [pPP_BW:0] Y_shift_msb_int8_f; +wire [31:0] Y_shift_msb_int8_s; +wire [16:0] dat_info; +wire [16:0] dat_info_index_sub; +wire [pPP_BW-1:0] datin_int8; +wire [pPP_BW:0] dec_Xindex_datin_msb; +wire [pPP_BW:0] dec_Yindex_msb; +wire [pPP_BW:0] dec_offset_datin_msb; +wire [pPP_BW:0] dec_offset_datin_msb_f0; +wire [pPP_BW:0] dec_offset_datin_msb_f1; +wire int_X_datin_prdy; +wire int_X_proc_in_vld; +wire int_Y_datin_prdy; +wire int_Y_proc_in_vld; +wire int_Y_stage0_prdy; +wire int_Y_stage1_prdy; +wire int_out_rdy; +wire int_out_vld; +wire int_stage0_prdy; +wire int_stage1_prdy; +wire int_stage2_in_vld; +wire int_stage2_prdy; +wire int_stage3_prdy; +wire load_din_intY; +wire load_in_intX; +wire load_int_Y_stage0; +wire load_int_stage0; +wire load_int_stage1; +wire load_int_stage2; +wire [pPP_BW:0] log2_datin_msb; +wire log2_datin_vld; +wire [7:0] reg2dp_X_index_offset; +wire [37:0] reg2dp_X_offset; +wire [37:0] reg2dp_Y_offset; +wire [7:0] shift_bits; +//wire [6:0] shift_bits_int16_abs; +wire [5:0] shift_bits_int8_abs; +wire [4:0] shift_bits_inv; +//wire [5:0] shift_bits_inv1; +//wire [38:0] shift_int16_f; +//wire [63:0] shift_int16_s; +wire [pPP_BW+1:0] shift_msb_int8_f; +wire [31:0] shift_msb_int8_s; +wire Y_stage3_out_rdy; +/////////////////////////////////////////////////// +//============== +// Work Processing +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + X_exp <= 1'b0; + end else begin + X_exp <= reg2dp_lut_le_function == 1'h0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_shift_bits[7:0] <= {8{1'b0}}; + end else begin + Y_shift_bits[7:0] <= reg2dp_lut_lo_index_select[7:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sqsum_bypass_enable <= 1'b0; + end else begin + sqsum_bypass_enable <= reg2dp_sqsum_bypass == 1'h1; + end +end +/////////////////////////////////////// +assign sum2itp_prdy = int_Y_datin_prdy & int_X_datin_prdy; +assign datin_int8 = sum2itp_pd; +/////////////////////////////////////////////////////////////////////////////////////// +//int X Y table input interlock +assign int_X_proc_in_vld = sum2itp_pvld & int_Y_datin_prdy; +assign int_Y_proc_in_vld = sum2itp_pvld & int_X_datin_prdy; +////////////////////////////////////////////////////////////////////// +// index calculation of X table +////////////////////////////////////////////////////////////////////// +//================================================= +//offset minus +//================================================= +assign reg2dp_X_offset[37:0] = {reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:0]}; +assign load_in_intX = int_X_proc_in_vld & int_X_datin_prdy; +assign dec_offset_datin_msb_f0 = {1'b0,datin_int8}; +assign dec_offset_datin_msb_f1 = {datin_int8[pPP_BW-1],datin_int8}; +assign dec_offset_datin_msb = sqsum_bypass_enable ? dec_offset_datin_msb_f1 : dec_offset_datin_msb_f0; +always @(*) begin + case({dec_offset_datin_msb[pPP_BW],reg2dp_X_offset[pPP_BW]}) + 2'b01: less_than_win_s = 1'b0; + 2'b10: less_than_win_s = 1'b1; + default: less_than_win_s = (dec_offset_datin_msb[pPP_BW:0] < reg2dp_X_offset[pPP_BW:0]) | (dec_offset_datin_msb[pPP_BW:0] == reg2dp_X_offset[pPP_BW:0]); + endcase +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_dec_offset_msb[0],dec_offset_msb[pPP_BW:0]} <= {(pPP_BW+2){1'b0}}; + int_X_input_uflow_msb <= 1'b0; + end else begin + if(load_in_intX) begin + if(less_than_win_s) begin + {mon_dec_offset_msb[0], dec_offset_msb[pPP_BW:0]} <= {(pPP_BW+2){1'b0}}; + int_X_input_uflow_msb <= 1'b1; + end else begin + {mon_dec_offset_msb[0], dec_offset_msb[pPP_BW:0]} <= ($signed(dec_offset_datin_msb) - $signed(reg2dp_X_offset[pPP_BW:0])); + int_X_input_uflow_msb <= 1'b0; + end + end + end +end +assign int_X_datin_prdy = ~int_stage0_pvld | int_stage0_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage0_pvld <= 1'b0; + end else begin + if(int_X_proc_in_vld) + int_stage0_pvld <= 1'b1; + else if(int_stage0_prdy) + int_stage0_pvld <= 1'b0; + end +end +assign int_stage0_prdy = ~int_stage1_pvld | int_stage1_prdy; +assign load_int_stage0 = int_stage0_pvld & int_stage0_prdy; +//=================================================================== +//log2 logic , bypassed when X is a linear table +assign log2_datin_msb = dec_offset_msb ; +assign log2_datin_vld = load_int_stage0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + log2_datout_msb <= {(pPP_BW+1){1'b0}}; + log2_frac_msb <= {pPP_BW{1'b0}}; + end else begin + if(log2_datin_vld) begin + if(int_X_input_uflow_msb) begin + log2_datout_msb <= {(pPP_BW+1){1'b0}}; + log2_frac_msb <= {pPP_BW{1'b0}}; + end else begin + if(X_exp) begin +//Note need modify "my $k = 21" if BW changed. +//: my $k = 21; +//: my $k1 = $k +1; +//: print qq( +//: if(log2_datin_msb[${k}]) begin +//: log2_datout_msb <= ${k1}'d${k}; +//: log2_frac_msb <= log2_datin_msb[${k}-1:0]; +//: ); +//: foreach my $m (0..$k - 2) { +//: my $i = $k - $m -1; +//: print qq( +//: end else if(log2_datin_msb[$i]) begin +//: log2_datout_msb <= ${k1}'d${i}; +//: log2_frac_msb <= {log2_datin_msb[${i}-1:0],{(${k}-${i}){1'b0}}}; +//: ); +//: } + end else if(log2_datin_msb[0]) begin + log2_datout_msb <= {(pPP_BW+1){1'b0}}; + log2_frac_msb <= {pPP_BW{1'b0}}; + end + end else + log2_datout_msb <= log2_datin_msb; + end + end + end +end +assign X_exp_frac_msb = log2_frac_msb[pPP_BW-1:pPP_BW-16]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_X_input_uflow_d <= 1'b0; + end else begin + if(log2_datin_vld) + int_X_input_uflow_d <= int_X_input_uflow_msb; + end +end +assign dat_info = {int_X_input_uflow_d,X_exp_frac_msb}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage1_pvld <= 1'b0; + end else begin + if(int_stage0_pvld) + int_stage1_pvld <= 1'b1; + else if(int_stage1_prdy) + int_stage1_pvld <= 1'b0; + end +end +assign int_stage1_prdy = ~int_stage2_pvld | int_stage2_prdy; +//=================================================================== +//exp index offset , only valid for exponent table +assign reg2dp_X_index_offset[7:0] = reg2dp_lut_le_index_offset[7:0]; +assign load_int_stage1 = int_stage1_pvld & int_stage1_prdy; +assign int_stage2_in_vld = int_stage1_pvld; +assign dec_Xindex_datin_msb = log2_datout_msb; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_dec_Xindex_msb[0],dec_Xindex_msb} <= {(pPP_BW+3){1'b0}}; + int_X_index_uflow_msb <= 1'b0; + end else begin + if(load_int_stage1) begin + if(dat_info[16]) begin //uflow + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= {(pPP_BW+3){1'b0}}; + int_X_index_uflow_msb <= 1'b0; + end else if(X_exp) begin +//if((dec_Xindex_datin_msb < {{(pPP_BW+1-7){1'b0}},reg2dp_X_index_offset[6:0]}) & (~reg2dp_X_index_offset[7])) begin + if((dec_Xindex_datin_msb < {{(pPP_BW-6){1'b0}},reg2dp_X_index_offset[6:0]}) & (~reg2dp_X_index_offset[7])) begin + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= {(pPP_BW+3){1'b0}}; + int_X_index_uflow_msb <= 1'b1; + end else begin + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= $signed({1'b0,dec_Xindex_datin_msb}) - $signed({{(pPP_BW-6){reg2dp_X_index_offset[7]}},reg2dp_X_index_offset[7:0]}); + int_X_index_uflow_msb <= 1'b0; + end + end else begin + {mon_dec_Xindex_msb[0], dec_Xindex_msb} <= {2'd0,dec_Xindex_datin_msb}; + int_X_index_uflow_msb <= 1'b0; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_LUT_ctrl: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, load_int_stage2 & (|mon_dec_Xindex_msb); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_info_d <= {17{1'b0}}; + end else if ((load_int_stage1) == 1'b1) begin + dat_info_d <= dat_info; + end +end +assign dat_info_index_sub = {dat_info_d[16] | int_X_index_uflow_msb, dat_info_d[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage2_pvld <= 1'b0; + end else begin + if(int_stage2_in_vld) + int_stage2_pvld <= 1'b1; + else if(int_stage2_prdy) + int_stage2_pvld <= 1'b0; + end +end +assign int_stage2_prdy = ~int_stage3_pvld | int_stage3_prdy; +assign load_int_stage2 = int_stage2_pvld & int_stage2_prdy; +//=================================================================== +//shift process for int8/int16, linear only, shift "0" when exponent X +assign shift_bits[7:0] = X_exp ? 8'd0 : reg2dp_lut_le_index_select[7:0]; +//note for int16 should be: assign shift_bits_inv1[5:0] = ~shift_bits[5:0]; +//note for int16 should be: assign shift_bits_int16_abs[6:0] = shift_bits[6]? (shift_bits_inv1[5:0]+1) : shift_bits[5:0]; +//note for int16 should be: assign {shift_int16_s[63:0], shift_int16_f[38:0] } = shift_bits[6]? ({64'd0,dec_Xindex_lsb[38:0]}<>shift_bits_int16_abs); +assign shift_bits_inv[4:0] = ~shift_bits[4:0]; +assign shift_bits_int8_abs[5:0] = shift_bits[5]? (shift_bits_inv[4:0] +1) : shift_bits[4:0]; +assign {shift_msb_int8_s[31:0],shift_msb_int8_f[pPP_BW+1:0]} = shift_bits[5]? ({32'd0,dec_Xindex_msb}<>shift_bits_int8_abs ); +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// shift_int16[9:0] <= {10{1'b0}}; +// X_int16_oflow <= 1'b0; +// end else begin +// if(load_int_stage2) begin +// if(dat_info_index_sub[32]) begin //lsb uflow +// shift_int16[9:0] <= 10'd0; +// X_int16_oflow <= 1'b0; +// end else if(shift_bits[6]) begin +// if({shift_int16_s,shift_int16_f} >= (65 -1)) begin +// shift_int16[9:0] <= 65 - 1; +// X_int16_oflow <= 1'b1; +// end else begin +// shift_int16[9:0] <= shift_int16_f[9:0]; +// X_int16_oflow <= 1'b0; +// end +// end else begin +// if(shift_int16_s >= (65 -1)) begin +// shift_int16[9:0] <= 65 - 1; +// X_int16_oflow <= 1'b1; +// end else begin +// shift_int16[9:0] <= shift_int16_s[9:0]; +// X_int16_oflow <= 1'b0; +// end +// end +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + shift_msb_int8[9:0] <= {10{1'b0}}; + X_int8_oflow_msb <= 1'b0; + end else begin + if(load_int_stage2) begin + if(dat_info_index_sub[16]) begin //uflow + shift_msb_int8[9:0] <= 10'd0; + X_int8_oflow_msb <= 1'b0; + end else if(shift_bits[5]) begin + if({shift_msb_int8_s,shift_msb_int8_f} >= (65 -1)) begin + shift_msb_int8[9:0] <= 65 - 1;//7'd64; + X_int8_oflow_msb <= 1'b1; + end else begin + shift_msb_int8[9:0] <= shift_msb_int8_f[9:0]; + X_int8_oflow_msb <= 1'b0; + end + end else begin + if(shift_msb_int8_s >= (65 -1)) begin + shift_msb_int8[9:0] <= 65 - 1;//7'd64; + X_int8_oflow_msb <= 1'b1; + end else begin + shift_msb_int8[9:0] <= shift_msb_int8_s[9:0]; + X_int8_oflow_msb <= 1'b0; + end + end + end + end +end +assign X_oflow_int_msb = X_int8_oflow_msb; +assign X_index_msb = shift_msb_int8; +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// X_lin_frac_int16[15:0] <= {16{1'b0}}; +// end else begin +// if(load_int_stage2) begin +// if(shift_bits[6]) +// X_lin_frac_int16[15:0] <= 16'd0; +// else +// X_lin_frac_int16[15:0] <= shift_int16_f[38:23]; +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + X_lin_frac_int8_msb[15:0] <= {16{1'b0}}; + end else begin + if(load_int_stage2) begin + if(shift_bits[5]) + X_lin_frac_int8_msb[15:0] <= 16'd0; + else + X_lin_frac_int8_msb[15:0] <= shift_msb_int8_f[pPP_BW+1:pPP_BW-14]; + end + end +end +assign X_lin_frac_msb = X_lin_frac_int8_msb; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_info_shift <= {17{1'b0}}; + end else if ((load_int_stage2) == 1'b1) begin + dat_info_shift <= dat_info_index_sub; + end +end +assign X_frac_msb = X_exp ? dat_info_shift[15:0] : X_lin_frac_msb; +assign X_dat_info = {X_oflow_int_msb,dat_info_shift[16],X_frac_msb};//oflow, uflow, frac +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP INT X table msb info: uflow and oflow occured at same time") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, int_stage3_pvld & dat_info_shift[16] & X_oflow_int_msb); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_stage3_pvld <= 1'b0; + end else begin + if(int_stage2_pvld) + int_stage3_pvld <= 1'b1; + else if(int_stage3_prdy) + int_stage3_pvld <= 1'b0; + end +end +//assign int_stage3_prdy = ~int_stage4_pvld | int_stage4_prdy; +//assign load_int_stage3 = int_stage3_pvld & int_stage3_prdy; +////////////////////////////////////////////////////////////////////// +//index calculation of Y table +////////////////////////////////////////////////////////////////////// +//================================================== +//input offset +//================================================== +assign reg2dp_Y_offset[37:0] = {reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:0]}; +assign load_din_intY = int_Y_proc_in_vld & int_Y_datin_prdy; +always @(*) begin + case({dec_offset_datin_msb[pPP_BW],reg2dp_Y_offset[pPP_BW]}) + 2'b01: Y_less_than_win_s = 1'b0; + 2'b10: Y_less_than_win_s = 1'b1; + default: Y_less_than_win_s = (dec_offset_datin_msb[pPP_BW:0] < reg2dp_Y_offset[pPP_BW:0]) | (dec_offset_datin_msb[pPP_BW:0] == reg2dp_Y_offset[pPP_BW:0]); + endcase +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_Y_dec_offset_msb[0],Y_dec_offset_msb} <= {(pPP_BW+2){1'b0}}; + int_Y_input_uflow_msb <= 1'b0; + end else begin + if(load_din_intY) begin + if(Y_less_than_win_s) begin + {mon_Y_dec_offset_msb[0], Y_dec_offset_msb} <= {(pPP_BW+2){1'b0}}; + int_Y_input_uflow_msb <= 1'b1; + end else begin + {mon_Y_dec_offset_msb[0], Y_dec_offset_msb} <= ($signed(dec_offset_datin_msb) - $signed(reg2dp_Y_offset[pPP_BW:0])); + int_Y_input_uflow_msb <= 1'b0; + end + end + end +end +assign int_Y_datin_prdy = ~int_Y_stage0_pvld | int_Y_stage0_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_Y_stage0_pvld <= 1'b0; + end else begin + if(int_Y_proc_in_vld) + int_Y_stage0_pvld <= 1'b1; + else if(int_Y_stage0_prdy) + int_Y_stage0_pvld <= 1'b0; + end +end +assign int_Y_stage0_prdy =~int_Y_stage1_pvld | int_Y_stage1_prdy; +assign load_int_Y_stage0 = int_Y_stage0_pvld & int_Y_stage0_prdy; +//=================================================================== +//shift process for Y int8/int16, Y is linear only +//=================================================================== +assign dec_Yindex_msb = Y_dec_offset_msb; +// note int16 should be this : assign Y_shift_bits_inv1[5:0] = ~Y_shift_bits[5:0]; +// note int16 should be this : assign Y_shift_bits_int16_abs = Y_shift_bits[6]? (Y_shift_bits_inv1[5:0]+1) : Y_shift_bits[5:0]; +// note int16 should be this : assign {Y_shift_int16_s[63:0] ,Y_shift_int16_f[37:0]} = Y_shift_bits[6]? ({64'd0,dec_Yindex_lsb[37:0]} << Y_shift_bits_int16_abs) : ({26'd0,dec_Yindex_lsb[37:0],38'd0} >> Y_shift_bits_int16_abs); +assign Y_shift_bits_inv[4:0] = ~Y_shift_bits[4:0]; +assign Y_shift_bits_int8_abs = Y_shift_bits[5]? (Y_shift_bits_inv[4:0] +1) : Y_shift_bits[4:0]; +assign {Y_shift_msb_int8_s[31:0],Y_shift_msb_int8_f} = Y_shift_bits[5]? ({32'd0,dec_Yindex_msb} << Y_shift_bits_int8_abs ) : ({10'd0,dec_Yindex_msb,22'd0} >> Y_shift_bits_int8_abs); +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// Y_shift_int16[9:0] <= {10{1'b0}}; +// Y_int16_oflow <= 1'b0; +// end else begin +// if(load_int_Y_stage0) begin +// if(int_Y_input_uflow_lsb) begin +// Y_shift_int16[9:0] <= 10'd0; +// Y_int16_oflow <= 1'b0; +// end else if(Y_shift_bits[6]) begin +// if({Y_shift_int16_s,Y_shift_int16_f} >= (257 -1)) begin +// Y_shift_int16[9:0] <= 257 - 1; +// Y_int16_oflow <= 1'b1; +// end else begin +// Y_shift_int16[9:0] <= Y_shift_int16_f[9:0]; +// Y_int16_oflow <= 1'b0; +// end +// end else begin +// if(Y_shift_int16_s >= (257 -1)) begin +// Y_shift_int16[9:0] <= 257 - 1; +// Y_int16_oflow <= 1'b1; +// end else begin +// Y_shift_int16[9:0] <= Y_shift_int16_s[9:0]; +// Y_int16_oflow <= 1'b0; +// end +// end +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_shift_msb_int8[9:0] <= {10{1'b0}}; + Y_int8_oflow_msb <= 1'b0; + end else begin + if(load_int_Y_stage0) begin + if(int_Y_input_uflow_msb) begin + Y_shift_msb_int8[9:0] <= 10'd0; + Y_int8_oflow_msb <= 1'b0; + end else if(Y_shift_bits[5]) begin + if({Y_shift_msb_int8_s,Y_shift_msb_int8_f} >= (257 -1)) begin + Y_shift_msb_int8[9:0] <= 257 - 1; + Y_int8_oflow_msb <= 1'b1; + end else begin + Y_shift_msb_int8[9:0] <= Y_shift_msb_int8_f[9:0]; + Y_int8_oflow_msb <= 1'b0; + end + end else begin + if(Y_shift_msb_int8_s >= (257 -1)) begin + Y_shift_msb_int8[9:0] <= 257 - 1; + Y_int8_oflow_msb <= 1'b1; + end else begin + Y_shift_msb_int8[9:0] <= Y_shift_msb_int8_s[9:0]; + Y_int8_oflow_msb <= 1'b0; + end + end + end + end +end +assign Y_oflow_int_msb = Y_int8_oflow_msb; +assign Y_index_msb_f = Y_shift_msb_int8; +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// Y_lin_frac_int16[15:0] <= {16{1'b0}}; +// end else begin +// if(load_int_Y_stage0) begin +// if(Y_shift_bits[6]) +// Y_lin_frac_int16[15:0] <= 16'd0; +// else +// Y_lin_frac_int16[15:0] <= Y_shift_int16_f[37:22]; +// end +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_lin_frac_int8_msb[15:0] <= {16{1'b0}}; + end else begin + if(load_int_Y_stage0) begin + if(Y_shift_bits[5]) + Y_lin_frac_int8_msb[15:0] <= 16'd0; + else + Y_lin_frac_int8_msb[15:0] <= Y_shift_msb_int8_f[pPP_BW:pPP_BW-15]; + end + end +end +assign Y_lin_frac_msb = Y_lin_frac_int8_msb; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_dat_info_shift <= 1'b0; + end else if (load_int_Y_stage0) begin + Y_dat_info_shift <= int_Y_input_uflow_msb; + end +end +assign Y_dat_info_f = {Y_oflow_int_msb,Y_dat_info_shift,Y_lin_frac_msb}; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP INT Y table msb info: uflow and oflow occured at same time") zzz_assert_never_10x (nvdla_core_clk, `ASSERT_RESET, int_Y_stage1_pvld & Y_dat_info_shift & Y_oflow_int_msb); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_Y_stage1_pvld <= 1'b0; + end else begin + if(int_Y_stage0_pvld) + int_Y_stage1_pvld <= 1'b1; + else if(int_Y_stage1_prdy) + int_Y_stage1_pvld <= 1'b0; + end +end +//assign int_Y_stage1_prdy = Y_stage1_in_rdy; +///////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////// +//pipe delay to sync with X table +wire [27:0] Y_stage1_in_pd; +wire Y_stage1_in_vld; +wire Y_stage1_in_rdy; +reg Y_stage2_in_vld; +reg Y_stage3_out_vld; +wire Y_stage2_in_rdy; +reg [27:0] Y_stage2_in_dp; +reg [27:0] Y_stage3_out_pd; +///////////////////////////////////////////////////////////////////////// +assign int_Y_stage1_prdy = Y_stage1_in_rdy; +///////////////////////////////////////////////////////////////////////// +assign Y_stage1_in_pd = {Y_dat_info_f,Y_index_msb_f}; +assign Y_stage1_in_vld = int_Y_stage1_pvld; +///////////////////////////////// +assign Y_stage1_in_rdy = Y_stage2_in_rdy || (~Y_stage2_in_vld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage2_in_vld <= 1'b0; + end else if(Y_stage1_in_vld) begin + Y_stage2_in_vld <= 1'b1; + end else if(Y_stage2_in_rdy) begin + Y_stage2_in_vld <= 1'b0; + end +end +assign Y_stage2_in_rdy = Y_stage3_out_rdy || (~Y_stage3_out_vld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage3_out_vld <= 1'b0; + end else if(Y_stage2_in_vld) begin + Y_stage3_out_vld <= 1'b1; + end else if(Y_stage3_out_rdy) begin + Y_stage3_out_vld <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage2_in_dp <= 28'd0; + end else if(Y_stage1_in_vld & Y_stage1_in_rdy) begin + Y_stage2_in_dp <= Y_stage1_in_pd; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + Y_stage3_out_pd <= 28'd0; + end else if(Y_stage2_in_vld & Y_stage2_in_rdy) begin + Y_stage3_out_pd <= Y_stage2_in_dp; + end +end +///////////////////////////////// +assign Y_index_msb = Y_stage3_out_pd[9:0]; +assign Y_dat_info = Y_stage3_out_pd[27:10]; +assign Y_int_stage3_pvld = Y_stage3_out_vld; +assign Y_stage3_out_rdy = Y_int_stage3_prdy; +//////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////// +//int X Y tables control output interlock +assign int_stage3_prdy = int_out_rdy & Y_int_stage3_pvld; +assign Y_int_stage3_prdy = int_out_rdy & int_stage3_pvld; +assign int_out_vld = int_stage3_pvld & Y_int_stage3_pvld; +//////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////// +assign dp2lut_pvld = int_out_vld; +assign int_out_rdy = dp2lut_prdy; +assign dp2lut_X_pd = {X_index_msb}; +assign dp2lut_X_info = X_dat_info; +assign dp2lut_Y_pd = {Y_index_msb}; +assign dp2lut_Y_info = Y_dat_info; +//////////// +endmodule // NV_NVDLA_CDP_DP_LUT_CTRL_unit diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v new file mode 100644 index 0000000..21b1f16 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v @@ -0,0 +1,250 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_LUT_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_LUT_ctrl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2lut_prdy //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_index_select //|< i + ,reg2dp_lut_le_start_high //|< i + ,reg2dp_lut_le_start_low //|< i + ,reg2dp_lut_lo_index_select //|< i + ,reg2dp_lut_lo_start_high //|< i + ,reg2dp_lut_lo_start_low //|< i + ,reg2dp_sqsum_bypass //|< i + ,sum2itp_pd //|< i + ,sum2itp_pvld //|< i + ,sum2sync_prdy //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,dp2lut_X_entry_${m} +//: ,dp2lut_Xinfo_${m} +//: ,dp2lut_Y_entry_${m} +//: ,dp2lut_Yinfo_${m} +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,dp2lut_X_entry_0 +,dp2lut_Xinfo_0 +,dp2lut_Y_entry_0 +,dp2lut_Yinfo_0 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,dp2lut_pvld //|> o + ,sum2itp_prdy //|> o + ,sum2sync_pd //|> o + ,sum2sync_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////////////////////// +//parameter pINT8_BW = 9;//int8 bitwidth after icvt +//parameter pPP_BW = (pINT8_BW + pINT8_BW) -1 + 4; +//////////////////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [7:0] reg2dp_lut_le_index_select; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [7:0] reg2dp_lut_lo_index_select; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_sqsum_bypass; +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $sqsumo = $icvto *2 -1+4; ##(${tp}*2) -1 is for x^2, +4 is after 9 lrn +//: print "input [${tp}*${sqsumo}-1:0] sum2itp_pd; \n"; +//: print "output [${tp}*${sqsumo}-1:0] sum2sync_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [1*21-1:0] sum2itp_pd; +output [1*21-1:0] sum2sync_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input sum2itp_pvld; +output sum2itp_prdy; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: output [9:0] dp2lut_X_entry_${m}; +//: output [17:0] dp2lut_Xinfo_${m}; +//: output [9:0] dp2lut_Y_entry_${m}; +//: output [17:0] dp2lut_Yinfo_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [9:0] dp2lut_X_entry_0; +output [17:0] dp2lut_Xinfo_0; +output [9:0] dp2lut_Y_entry_0; +output [17:0] dp2lut_Yinfo_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output dp2lut_pvld; +input dp2lut_prdy; +output sum2sync_pvld; +input sum2sync_prdy; +//////////////////////////////////////////////////////////////////////////////////////// +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $sqsumo = $icvto *2 -1+4; +//: foreach my $m (0..${tp}-1) { +//: print qq( +//: wire [17:0] dp2lut_X_info_$m; +//: wire [9:0] dp2lut_X_pd_$m; +//: wire [17:0] dp2lut_Y_info_$m; +//: wire [9:0] dp2lut_Y_pd_$m; +//: wire [${sqsumo}-1:0] sum2itp_pd_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [17:0] dp2lut_X_info_0; +wire [9:0] dp2lut_X_pd_0; +wire [17:0] dp2lut_Y_info_0; +wire [9:0] dp2lut_Y_pd_0; +wire [21-1:0] sum2itp_pd_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [1 -1:0] dp2lut_rdy; +wire [1 -1:0] dp2lut_vld; +wire [1 -1:0] sum2itp_rdy; +wire [1 -1:0] sum2itp_vld; +//////////////////////////////////////////////////////////////////////////////////////// +assign sum2itp_prdy = (&sum2itp_rdy) & sum2sync_prdy; +////////////////////////////////////////////////////////////////////// +//from intp_ctrl input port to sync fifo for interpolation +assign sum2sync_pvld = sum2itp_pvld & (&sum2itp_rdy); +assign sum2sync_pd = sum2itp_pd; +/////////////////////////////////////////// +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $sqsumo = $icvto *2 -1+4; +//: foreach my $m (0..${tp} -1) { +//: print qq( +//: assign sum2itp_vld[$m] = sum2itp_pvld & sum2sync_prdy +//: ); +//: foreach my $j (0..${tp} -1) { +//: if(${j} != ${m}) { +//: print qq( +//: & sum2itp_rdy[$j] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: print qq( +//: assign sum2itp_pd_${m} = sum2itp_pd[${sqsumo}*${m}+${sqsumo}-1:${sqsumo}*${m}]; +//: NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.sum2itp_pd (sum2itp_pd_${m}) +//: ,.sum2itp_pvld (sum2itp_vld[${m}]) +//: ,.sum2itp_prdy (sum2itp_rdy[${m}]) +//: ,.reg2dp_lut_le_function (reg2dp_lut_le_function) +//: ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) +//: ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) +//: ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) +//: ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) +//: ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) +//: ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) +//: ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) +//: ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) +//: ,.dp2lut_X_info (dp2lut_X_info_${m}) +//: ,.dp2lut_X_pd (dp2lut_X_pd_${m}) +//: ,.dp2lut_Y_info (dp2lut_Y_info_${m}) +//: ,.dp2lut_Y_pd (dp2lut_Y_pd_${m}) +//: ,.dp2lut_pvld (dp2lut_vld[${m}]) +//: ,.dp2lut_prdy (dp2lut_rdy[${m}]) +//: ); +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k -1) { +//: print qq( +//: assign dp2lut_X_entry_$m = dp2lut_X_pd_$m; +//: assign dp2lut_Y_entry_$m = dp2lut_Y_pd_$m; +//: assign dp2lut_Xinfo_$m = dp2lut_X_info_$m; +//: assign dp2lut_Yinfo_$m = dp2lut_Y_info_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign sum2itp_vld[0] = sum2itp_pvld & sum2sync_prdy + +; + +assign sum2itp_pd_0 = sum2itp_pd[21*0+21-1:21*0]; +NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.sum2itp_pd (sum2itp_pd_0) +,.sum2itp_pvld (sum2itp_vld[0]) +,.sum2itp_prdy (sum2itp_rdy[0]) +,.reg2dp_lut_le_function (reg2dp_lut_le_function) +,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) +,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) +,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) +,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) +,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) +,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) +,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) +,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) +,.dp2lut_X_info (dp2lut_X_info_0) +,.dp2lut_X_pd (dp2lut_X_pd_0) +,.dp2lut_Y_info (dp2lut_Y_info_0) +,.dp2lut_Y_pd (dp2lut_Y_pd_0) +,.dp2lut_pvld (dp2lut_vld[0]) +,.dp2lut_prdy (dp2lut_rdy[0]) +); + +assign dp2lut_X_entry_0 = dp2lut_X_pd_0; +assign dp2lut_Y_entry_0 = dp2lut_Y_pd_0; +assign dp2lut_Xinfo_0 = dp2lut_X_info_0; +assign dp2lut_Yinfo_0 = dp2lut_Y_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp2lut_pvld = &dp2lut_vld; +//: my $k = 1; +//: foreach my $m (0..$k -1) { +//: print qq( +//: assign dp2lut_rdy[${m}] = dp2lut_prdy +//: ); +//: foreach my $j (0..$k -1) { +//: if(${j} != ${m}) { +//: print qq( +//: & dp2lut_vld[$j] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dp2lut_rdy[0] = dp2lut_prdy + +; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_LUT_ctrl diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v.vcp new file mode 100644 index 0000000..cda0fd8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v.vcp @@ -0,0 +1,177 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_LUT_ctrl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_LUT_ctrl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2lut_prdy //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_index_select //|< i + ,reg2dp_lut_le_start_high //|< i + ,reg2dp_lut_le_start_low //|< i + ,reg2dp_lut_lo_index_select //|< i + ,reg2dp_lut_lo_start_high //|< i + ,reg2dp_lut_lo_start_low //|< i + ,reg2dp_sqsum_bypass //|< i + ,sum2itp_pd //|< i + ,sum2itp_pvld //|< i + ,sum2sync_prdy //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,dp2lut_X_entry_${m} +//: ,dp2lut_Xinfo_${m} +//: ,dp2lut_Y_entry_${m} +//: ,dp2lut_Yinfo_${m} +//: ); +//: } + ,dp2lut_pvld //|> o + ,sum2itp_prdy //|> o + ,sum2sync_pd //|> o + ,sum2sync_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////////////////////// +//parameter pINT8_BW = 9;//int8 bitwidth after icvt +//parameter pPP_BW = (pINT8_BW + pINT8_BW) -1 + 4; +//////////////////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [7:0] reg2dp_lut_le_index_select; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [7:0] reg2dp_lut_lo_index_select; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_sqsum_bypass; +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $sqsumo = $icvto *2 -1+4; ##(${tp}*2) -1 is for x^2, +4 is after 9 lrn +//: print "input [${tp}*${sqsumo}-1:0] sum2itp_pd; \n"; +//: print "output [${tp}*${sqsumo}-1:0] sum2sync_pd; \n"; +input sum2itp_pvld; +output sum2itp_prdy; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: output [9:0] dp2lut_X_entry_${m}; +//: output [17:0] dp2lut_Xinfo_${m}; +//: output [9:0] dp2lut_Y_entry_${m}; +//: output [17:0] dp2lut_Yinfo_${m}; +//: ); +//: } +output dp2lut_pvld; +input dp2lut_prdy; +output sum2sync_pvld; +input sum2sync_prdy; +//////////////////////////////////////////////////////////////////////////////////////// +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $sqsumo = $icvto *2 -1+4; +//: foreach my $m (0..${tp}-1) { +//: print qq( +//: wire [17:0] dp2lut_X_info_$m; +//: wire [9:0] dp2lut_X_pd_$m; +//: wire [17:0] dp2lut_Y_info_$m; +//: wire [9:0] dp2lut_Y_pd_$m; +//: wire [${sqsumo}-1:0] sum2itp_pd_$m; +//: ); +//: } +wire [1 -1:0] dp2lut_rdy; +wire [1 -1:0] dp2lut_vld; +wire [1 -1:0] sum2itp_rdy; +wire [1 -1:0] sum2itp_vld; +//////////////////////////////////////////////////////////////////////////////////////// +assign sum2itp_prdy = (&sum2itp_rdy) & sum2sync_prdy; +////////////////////////////////////////////////////////////////////// +//from intp_ctrl input port to sync fifo for interpolation +assign sum2sync_pvld = sum2itp_pvld & (&sum2itp_rdy); +assign sum2sync_pd = sum2itp_pd; +/////////////////////////////////////////// +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $sqsumo = $icvto *2 -1+4; +//: foreach my $m (0..${tp} -1) { +//: print qq( +//: assign sum2itp_vld[$m] = sum2itp_pvld & sum2sync_prdy +//: ); +//: foreach my $j (0..${tp} -1) { +//: if(${j} != ${m}) { +//: print qq( +//: & sum2itp_rdy[$j] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: print qq( +//: assign sum2itp_pd_${m} = sum2itp_pd[${sqsumo}*${m}+${sqsumo}-1:${sqsumo}*${m}]; +//: NV_NVDLA_CDP_DP_LUT_CTRL_unit u_LUT_CTRL_unit$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.sum2itp_pd (sum2itp_pd_${m}) +//: ,.sum2itp_pvld (sum2itp_vld[${m}]) +//: ,.sum2itp_prdy (sum2itp_rdy[${m}]) +//: ,.reg2dp_lut_le_function (reg2dp_lut_le_function) +//: ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) +//: ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) +//: ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) +//: ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) +//: ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) +//: ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) +//: ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) +//: ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) +//: ,.dp2lut_X_info (dp2lut_X_info_${m}) +//: ,.dp2lut_X_pd (dp2lut_X_pd_${m}) +//: ,.dp2lut_Y_info (dp2lut_Y_info_${m}) +//: ,.dp2lut_Y_pd (dp2lut_Y_pd_${m}) +//: ,.dp2lut_pvld (dp2lut_vld[${m}]) +//: ,.dp2lut_prdy (dp2lut_rdy[${m}]) +//: ); +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k -1) { +//: print qq( +//: assign dp2lut_X_entry_$m = dp2lut_X_pd_$m; +//: assign dp2lut_Y_entry_$m = dp2lut_Y_pd_$m; +//: assign dp2lut_Xinfo_$m = dp2lut_X_info_$m; +//: assign dp2lut_Yinfo_$m = dp2lut_Y_info_$m; +//: ); +//: } +assign dp2lut_pvld = &dp2lut_vld; +//: my $k = 1; +//: foreach my $m (0..$k -1) { +//: print qq( +//: assign dp2lut_rdy[${m}] = dp2lut_prdy +//: ); +//: foreach my $j (0..$k -1) { +//: if(${j} != ${m}) { +//: print qq( +//: & dp2lut_vld[$j] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: } +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_LUT_ctrl diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v new file mode 100644 index 0000000..9163314 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v @@ -0,0 +1,58 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_MUL_unit.v +module NV_NVDLA_CDP_DP_MUL_unit ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_ina_pd + ,mul_inb_pd + ,mul_unit_rdy + ,mul_vld + ,mul_rdy + ,mul_unit_pd + ,mul_unit_vld + ); +////////////////////////////////////////////////////////////////////////// +parameter pINA_BW = 9; +parameter pINB_BW = 16; +////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_vld; +output mul_rdy; +input [pINA_BW-1:0] mul_ina_pd; +input [pINB_BW-1:0] mul_inb_pd; +output mul_unit_vld; +input mul_unit_rdy; +output [pINA_BW+pINB_BW-1:0] mul_unit_pd; +////////////////////////////////////////////////////////////////////////// +reg mul_unit_vld; +reg [pINA_BW+pINB_BW-1:0] mul_unit_pd; +////////////////////////////////////////////////////////////////////////// +assign mul_rdy = ~mul_unit_vld | mul_unit_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_unit_pd <= {(pINA_BW+pINB_BW){1'b0}}; + end else begin + if(mul_vld & mul_rdy) begin + mul_unit_pd <= $signed(mul_inb_pd[pINB_BW-1:0]) * $signed(mul_ina_pd[pINA_BW-1:0]); + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_unit_vld <= 1'b0; + end else begin + if(mul_vld) + mul_unit_vld <= 1'b1; + else if(mul_unit_rdy) + mul_unit_vld <= 1'b0; + end +end +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_MUL_unit diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v.vcp new file mode 100644 index 0000000..9163314 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v.vcp @@ -0,0 +1,58 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_MUL_unit.v +module NV_NVDLA_CDP_DP_MUL_unit ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_ina_pd + ,mul_inb_pd + ,mul_unit_rdy + ,mul_vld + ,mul_rdy + ,mul_unit_pd + ,mul_unit_vld + ); +////////////////////////////////////////////////////////////////////////// +parameter pINA_BW = 9; +parameter pINB_BW = 16; +////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_vld; +output mul_rdy; +input [pINA_BW-1:0] mul_ina_pd; +input [pINB_BW-1:0] mul_inb_pd; +output mul_unit_vld; +input mul_unit_rdy; +output [pINA_BW+pINB_BW-1:0] mul_unit_pd; +////////////////////////////////////////////////////////////////////////// +reg mul_unit_vld; +reg [pINA_BW+pINB_BW-1:0] mul_unit_pd; +////////////////////////////////////////////////////////////////////////// +assign mul_rdy = ~mul_unit_vld | mul_unit_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_unit_pd <= {(pINA_BW+pINB_BW){1'b0}}; + end else begin + if(mul_vld & mul_rdy) begin + mul_unit_pd <= $signed(mul_inb_pd[pINB_BW-1:0]) * $signed(mul_ina_pd[pINA_BW-1:0]); + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_unit_vld <= 1'b0; + end else begin + if(mul_vld) + mul_unit_vld <= 1'b1; + else if(mul_unit_rdy) + mul_unit_vld <= 1'b0; + end +end +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_MUL_unit diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v new file mode 100644 index 0000000..24b631b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v @@ -0,0 +1,2459 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_bufferin.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_bufferin ( + nvdla_core_clk + ,nvdla_core_rstn + ,cdp_rdma2dp_pd + ,cdp_rdma2dp_valid + ,normalz_buf_data_prdy + ,cdp_rdma2dp_ready + ,normalz_buf_data + ,normalz_buf_data_pvld + ); +///////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*(8 +1)+14:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +input normalz_buf_data_prdy; +output cdp_rdma2dp_ready; +//output [1*(8 +1)*3+14:0] normalz_buf_data; +output [(1 +8)*(8 +1)+14:0] normalz_buf_data; +output normalz_buf_data_pvld; +///////////////////////////////////////////////////////////// +reg NormalC2CubeEnd; +reg b_sync_align; +reg b_sync_dly1; +reg buf_dat_vld; +reg buffer_b_sync; +reg [1*(8 +1)*3:0] buffer_data; +reg buffer_data_vld; +reg buffer_last_c; +reg buffer_last_h; +reg buffer_last_w; +reg [2:0] buffer_pos_c; +reg [3:0] buffer_pos_w; +//reg buffer_ready; +reg [3:0] buffer_width; +//reg cdp_rdma2dp_ready; +reg [3:0] cube_end_width_cnt; +reg [1*(8 +1)-1:0] data_1stC_0; +reg [1*(8 +1)-1:0] data_1stC_1; +reg [1*(8 +1)-1:0] data_1stC_2; +reg [1*(8 +1)-1:0] data_1stC_3; +reg [1*(8 +1)-1:0] data_1stC_4; +reg [1*(8 +1)-1:0] data_1stC_5; +reg [1*(8 +1)-1:0] data_1stC_6; +reg [1*(8 +1)-1:0] data_1stC_7; +reg [1*(8 +1)-1:0] data_shift_00; +reg [1*(8 +1)-1:0] data_shift_01; +reg [1*(8 +1)-1:0] data_shift_02; +reg [1*(8 +1)-1:0] data_shift_10; +reg [1*(8 +1)-1:0] data_shift_11; +reg [1*(8 +1)-1:0] data_shift_12; +reg [1*(8 +1)-1:0] data_shift_20; +reg [1*(8 +1)-1:0] data_shift_21; +reg [1*(8 +1)-1:0] data_shift_22; +reg [1*(8 +1)-1:0] data_shift_30; +reg [1*(8 +1)-1:0] data_shift_31; +reg [1*(8 +1)-1:0] data_shift_32; +reg [1*(8 +1)-1:0] data_shift_40; +reg [1*(8 +1)-1:0] data_shift_41; +reg [1*(8 +1)-1:0] data_shift_42; +reg [1*(8 +1)-1:0] data_shift_50; +reg [1*(8 +1)-1:0] data_shift_51; +reg [1*(8 +1)-1:0] data_shift_52; +reg [1*(8 +1)-1:0] data_shift_60; +reg [1*(8 +1)-1:0] data_shift_61; +reg [1*(8 +1)-1:0] data_shift_62; +reg [1*(8 +1)-1:0] data_shift_70; +reg [1*(8 +1)-1:0] data_shift_71; +reg [1*(8 +1)-1:0] data_shift_72; +reg data_shift_valid; +reg hold_here; +reg hold_here_dly; +reg [3:0] is_pos_w_dly; +reg [3:0] is_pos_w_dly2; +reg last_c_align; +reg last_c_dly1; +reg last_h_align; +reg last_h_dly1; +reg last_w_align; +reg last_w_dly1; +reg [3:0] last_width; +reg less2more_dly; +reg less2more_dly2; +reg more2less_dly; +reg [2:0] pos_c_align; +reg [2:0] pos_c_dly1; +reg [3:0] pos_w_align; +reg [3:0] pos_w_dly1; +reg [2:0] stat_cur; +reg [2:0] stat_cur_dly; +reg [2:0] stat_cur_dly2; +reg [2:0] stat_nex; +reg [3:0] width_align; +reg [3:0] width_cur_1; +reg [3:0] width_cur_2; +reg [3:0] width_dly1; +reg [3:0] width_pre; +reg [3:0] width_pre_cnt; +reg [3:0] width_pre_cnt_dly; +reg [3:0] width_pre_dly; +reg [3:0] width_pre_dly2; +wire FIRST_C_bf_end; +wire FIRST_C_end; +wire buf_dat_rdy; +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: print "wire [${k}-1:0] buffer_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [96-1:0] buffer_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire buffer_valid; +wire cube_done; +wire data_shift_load; +wire data_shift_load_all; +wire data_shift_ready; +wire dp_b_sync; +wire [1*(8 +1):0] dp_data; +wire dp_last_c; +wire dp_last_h; +wire dp_last_w; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire [3:0] dp_width; +wire is_b_sync; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire [2:0] is_pos_c; +wire [3:0] is_pos_w; +wire [3:0] is_width; +wire [3:0] is_width_f; +wire l2m_1stC_vld; +wire less2more; +wire load_din; +wire load_din_full; +wire more2less; +wire nvdla_cdp_rdma2dp_ready; +wire rdma2dp_ready_normal; +wire rdma2dp_valid_rebuild; +wire vld; +wire [3:0] width_cur; +///////////////////////////////////////////////////////////// +// +parameter cvt2buf_data_bw = 1*(8 +1); +parameter cvt2buf_info_bw = 15; +parameter cvt2buf_dp_bw = cvt2buf_data_bw + cvt2buf_info_bw; +///////////////////////////////////////////////////////////// +//: my $k = 1*(8 +1)+15; +//: &eperl::pipe(" -is -wid $k -do nvdla_cdp_rdma2dp_pd -vo nvdla_cdp_rdma2dp_valid -ri nvdla_cdp_rdma2dp_ready -di cdp_rdma2dp_pd -vi cdp_rdma2dp_valid -ro cdp_rdma2dp_ready "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg cdp_rdma2dp_ready; +reg skid_flop_cdp_rdma2dp_ready; +reg skid_flop_cdp_rdma2dp_valid; +reg [24-1:0] skid_flop_cdp_rdma2dp_pd; +reg pipe_skid_cdp_rdma2dp_valid; +reg [24-1:0] pipe_skid_cdp_rdma2dp_pd; +// Wire +wire skid_cdp_rdma2dp_valid; +wire [24-1:0] skid_cdp_rdma2dp_pd; +wire skid_cdp_rdma2dp_ready; +wire pipe_skid_cdp_rdma2dp_ready; +wire nvdla_cdp_rdma2dp_valid; +wire [24-1:0] nvdla_cdp_rdma2dp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma2dp_ready <= 1'b1; + skid_flop_cdp_rdma2dp_ready <= 1'b1; + end else begin + cdp_rdma2dp_ready <= skid_cdp_rdma2dp_ready; + skid_flop_cdp_rdma2dp_ready <= skid_cdp_rdma2dp_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_cdp_rdma2dp_valid <= 1'b0; + end else begin + if (skid_flop_cdp_rdma2dp_ready) begin + skid_flop_cdp_rdma2dp_valid <= cdp_rdma2dp_valid; + end + end +end +assign skid_cdp_rdma2dp_valid = (skid_flop_cdp_rdma2dp_ready) ? cdp_rdma2dp_valid : skid_flop_cdp_rdma2dp_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_cdp_rdma2dp_ready & cdp_rdma2dp_valid) begin + skid_flop_cdp_rdma2dp_pd[24-1:0] <= cdp_rdma2dp_pd[24-1:0]; + end +end +assign skid_cdp_rdma2dp_pd[24-1:0] = (skid_flop_cdp_rdma2dp_ready) ? cdp_rdma2dp_pd[24-1:0] : skid_flop_cdp_rdma2dp_pd[24-1:0]; + + +// PIPE READY +assign skid_cdp_rdma2dp_ready = pipe_skid_cdp_rdma2dp_ready || !pipe_skid_cdp_rdma2dp_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_cdp_rdma2dp_valid <= 1'b0; + end else begin + if (skid_cdp_rdma2dp_ready) begin + pipe_skid_cdp_rdma2dp_valid <= skid_cdp_rdma2dp_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_cdp_rdma2dp_ready && skid_cdp_rdma2dp_valid) begin + pipe_skid_cdp_rdma2dp_pd[24-1:0] <= skid_cdp_rdma2dp_pd[24-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_cdp_rdma2dp_ready = nvdla_cdp_rdma2dp_ready; +assign nvdla_cdp_rdma2dp_valid = pipe_skid_cdp_rdma2dp_valid; +assign nvdla_cdp_rdma2dp_pd = pipe_skid_cdp_rdma2dp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// INPUT UNPACK: from RDMA +//============== +assign dp_data[1*(8 +1)-1:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)-1:0]; +assign dp_pos_w[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+3:1*(8 +1)]; +assign dp_width[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+7:1*(8 +1)+4]; +assign dp_pos_c[2:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+10:1*(8 +1)+8]; +assign dp_b_sync = nvdla_cdp_rdma2dp_pd[1*(8 +1)+11]; +assign dp_last_w = nvdla_cdp_rdma2dp_pd[1*(8 +1)+12]; +assign dp_last_h = nvdla_cdp_rdma2dp_pd[1*(8 +1)+13]; +assign dp_last_c = nvdla_cdp_rdma2dp_pd[1*(8 +1)+14]; +assign is_pos_w = dp_pos_w; +assign is_width_f = dp_width[3:0]; +assign is_width[3:0] = is_width_f - 1'b1; +assign is_pos_c = dp_pos_c; +assign is_b_sync = dp_b_sync ; +assign is_last_w = dp_last_w ; +assign is_last_h = dp_last_h ; +assign is_last_c = dp_last_c ; +/////////////////////////////////////////////////// +assign nvdla_cdp_rdma2dp_ready = rdma2dp_ready_normal & (~hold_here); +assign rdma2dp_valid_rebuild = nvdla_cdp_rdma2dp_valid | hold_here; +assign vld = rdma2dp_valid_rebuild; +assign load_din = vld & nvdla_cdp_rdma2dp_ready; +assign load_din_full = rdma2dp_valid_rebuild & rdma2dp_ready_normal; +/////////////////////////////////////////////////// +localparam WAIT = 3'b000; +localparam NORMAL_C = 3'b001; +localparam FIRST_C = 3'b010; +localparam SECOND_C = 3'b011; +localparam CUBE_END = 3'b100; + always @(*) begin + stat_nex = stat_cur; + NormalC2CubeEnd = 0; + begin + casez (stat_cur) + WAIT: begin + if ((is_b_sync & (is_pos_c==3'd0) & load_din)) begin + stat_nex = NORMAL_C; + end + end + NORMAL_C: begin + if ((is_b_sync & (is_pos_c==3'd3) & is_last_c & is_last_h & is_last_w & load_din)) begin + NormalC2CubeEnd = 1; + stat_nex = CUBE_END; + end + else if ((is_b_sync & (is_pos_c==3'd3) & is_last_c) & (~(is_last_h & is_last_w) & load_din)) begin + stat_nex = FIRST_C; + end + end + FIRST_C: begin + if (((is_pos_w == is_width) & (~more2less) & load_din) + ||(more2less & (width_pre_cnt == width_pre) & hold_here & rdma2dp_ready_normal)) begin + stat_nex = SECOND_C; + end + end + SECOND_C: begin + if (is_b_sync & load_din) begin + stat_nex = NORMAL_C; + end + end + CUBE_END: begin + if (cube_done) begin + stat_nex = WAIT; + end + end +// VCS coverage off + default: begin + stat_nex = WAIT; + `ifndef SYNTHESIS + stat_nex = {3{1'bx}}; + `endif + end +// VCS coverage on + endcase + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur <= WAIT; + end else begin + stat_cur <= stat_nex; + end + end +///////////////////////////////////////// +assign rdma2dp_ready_normal = (~data_shift_valid) | data_shift_ready; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_shift_valid <= 1'b0; + end else begin + if(vld) + data_shift_valid <= 1'b1; + else if(data_shift_ready) + data_shift_valid <= 1'b0; + end +end +assign data_shift_ready =(~buf_dat_vld | buf_dat_rdy); +assign data_shift_load_all = data_shift_ready & data_shift_valid; +assign data_shift_load = data_shift_load_all & ((~hold_here_dly) | (stat_cur_dly == CUBE_END)); +///////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_shift_00 <= {1*(8 +1){1'b0}}; + data_shift_10 <= {1*(8 +1){1'b0}}; + data_shift_20 <= {1*(8 +1){1'b0}}; + data_shift_30 <= {1*(8 +1){1'b0}}; + data_shift_40 <= {1*(8 +1){1'b0}}; + data_shift_50 <= {1*(8 +1){1'b0}}; + data_shift_60 <= {1*(8 +1){1'b0}}; + data_shift_70 <= {1*(8 +1){1'b0}}; + data_shift_01 <= {1*(8 +1){1'b0}}; + data_shift_02 <= {1*(8 +1){1'b0}}; + data_shift_11 <= {1*(8 +1){1'b0}}; + data_shift_12 <= {1*(8 +1){1'b0}}; + data_shift_21 <= {1*(8 +1){1'b0}}; + data_shift_22 <= {1*(8 +1){1'b0}}; + data_shift_31 <= {1*(8 +1){1'b0}}; + data_shift_32 <= {1*(8 +1){1'b0}}; + data_shift_41 <= {1*(8 +1){1'b0}}; + data_shift_42 <= {1*(8 +1){1'b0}}; + data_shift_51 <= {1*(8 +1){1'b0}}; + data_shift_52 <= {1*(8 +1){1'b0}}; + data_shift_61 <= {1*(8 +1){1'b0}}; + data_shift_62 <= {1*(8 +1){1'b0}}; + data_shift_71 <= {1*(8 +1){1'b0}}; + data_shift_72 <= {1*(8 +1){1'b0}}; + data_1stC_0 <= {1*(8 +1){1'b0}}; + data_1stC_1 <= {1*(8 +1){1'b0}}; + data_1stC_2 <= {1*(8 +1){1'b0}}; + data_1stC_3 <= {1*(8 +1){1'b0}}; + data_1stC_4 <= {1*(8 +1){1'b0}}; + data_1stC_5 <= {1*(8 +1){1'b0}}; + data_1stC_6 <= {1*(8 +1){1'b0}}; + data_1stC_7 <= {1*(8 +1){1'b0}}; + end else begin + case(stat_cur) + WAIT: begin + if(load_din) begin + if(is_pos_w==4'd0) begin + data_shift_00 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd1) begin + data_shift_10 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd2) begin + data_shift_20 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd3) begin + data_shift_30 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd4) begin + data_shift_40 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd5) begin + data_shift_50 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd6) begin + data_shift_60 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd7) begin + data_shift_70 <= dp_data[cvt2buf_data_bw-1:0]; + end + data_shift_01 <= {cvt2buf_data_bw{1'd0}}; + data_shift_02 <= {cvt2buf_data_bw{1'd0}}; + data_shift_11 <= {cvt2buf_data_bw{1'd0}}; + data_shift_12 <= {cvt2buf_data_bw{1'd0}}; + data_shift_21 <= {cvt2buf_data_bw{1'd0}}; + data_shift_22 <= {cvt2buf_data_bw{1'd0}}; + data_shift_31 <= {cvt2buf_data_bw{1'd0}}; + data_shift_32 <= {cvt2buf_data_bw{1'd0}}; + data_shift_41 <= {cvt2buf_data_bw{1'd0}}; + data_shift_42 <= {cvt2buf_data_bw{1'd0}}; + data_shift_51 <= {cvt2buf_data_bw{1'd0}}; + data_shift_52 <= {cvt2buf_data_bw{1'd0}}; + data_shift_61 <= {cvt2buf_data_bw{1'd0}}; + data_shift_62 <= {cvt2buf_data_bw{1'd0}}; + data_shift_71 <= {cvt2buf_data_bw{1'd0}}; + data_shift_72 <= {cvt2buf_data_bw{1'd0}}; + end end + NORMAL_C: begin + if(load_din) begin + if(is_pos_w==4'd0) begin + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd1) begin + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd2) begin + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd3) begin + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd4) begin + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd5) begin + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd6) begin + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd7) begin + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= dp_data[cvt2buf_data_bw-1:0]; + end + end end + FIRST_C: begin + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd0) begin + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd0) & load_din) begin + data_1stC_0 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd1) begin + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd1) & load_din) begin + data_1stC_1 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd2) begin + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd2) & load_din) begin + data_1stC_2 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd3) begin + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd3) & load_din) begin + data_1stC_3 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd4) begin + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd4) & load_din) begin + data_1stC_4 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd5) begin + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd5) & load_din) begin + data_1stC_5 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd6) begin + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd6) & load_din) begin + data_1stC_6 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd7) begin + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd7) & load_din) begin + data_1stC_7 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + end + end + end// end + SECOND_C: begin + if(load_din) begin + if(is_pos_w==4'd0) begin + data_shift_02 <= 0; + data_shift_01 <= data_1stC_0; + data_shift_00 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd1) begin + data_shift_12 <= 0; + data_shift_11 <= data_1stC_1; + data_shift_10 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd2) begin + data_shift_22 <= 0; + data_shift_21 <= data_1stC_2; + data_shift_20 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd3) begin + data_shift_32 <= 0; + data_shift_31 <= data_1stC_3; + data_shift_30 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd4) begin + data_shift_42 <= 0; + data_shift_41 <= data_1stC_4; + data_shift_40 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd5) begin + data_shift_52 <= 0; + data_shift_51 <= data_1stC_5; + data_shift_50 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd6) begin + data_shift_62 <= 0; + data_shift_61 <= data_1stC_6; + data_shift_60 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd7) begin + data_shift_72 <= 0; + data_shift_71 <= data_1stC_7; + data_shift_70 <= dp_data[cvt2buf_data_bw-1:0]; + end + end end + CUBE_END: begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt==4'd0) begin + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd1) begin + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd2) begin + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd3) begin + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd4) begin + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd5) begin + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd6) begin + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd7) begin + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + end + end end + default: begin + data_shift_02 <= {cvt2buf_data_bw{1'd0}}; + data_shift_01 <= {cvt2buf_data_bw{1'd0}}; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_0 <= {cvt2buf_data_bw{1'd0}}; + data_shift_12 <= {cvt2buf_data_bw{1'd0}}; + data_shift_11 <= {cvt2buf_data_bw{1'd0}}; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_1 <= {cvt2buf_data_bw{1'd0}}; + data_shift_22 <= {cvt2buf_data_bw{1'd0}}; + data_shift_21 <= {cvt2buf_data_bw{1'd0}}; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_2 <= {cvt2buf_data_bw{1'd0}}; + data_shift_32 <= {cvt2buf_data_bw{1'd0}}; + data_shift_31 <= {cvt2buf_data_bw{1'd0}}; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_3 <= {cvt2buf_data_bw{1'd0}}; + data_shift_42 <= {cvt2buf_data_bw{1'd0}}; + data_shift_41 <= {cvt2buf_data_bw{1'd0}}; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_4 <= {cvt2buf_data_bw{1'd0}}; + data_shift_52 <= {cvt2buf_data_bw{1'd0}}; + data_shift_51 <= {cvt2buf_data_bw{1'd0}}; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_5 <= {cvt2buf_data_bw{1'd0}}; + data_shift_62 <= {cvt2buf_data_bw{1'd0}}; + data_shift_61 <= {cvt2buf_data_bw{1'd0}}; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_6 <= {cvt2buf_data_bw{1'd0}}; + data_shift_72 <= {cvt2buf_data_bw{1'd0}}; + data_shift_71 <= {cvt2buf_data_bw{1'd0}}; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_7 <= {cvt2buf_data_bw{1'd0}}; + end + endcase + end + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre <= {4{1'b0}}; + end else begin + if((stat_cur==NORMAL_C) & is_last_c & is_b_sync & (is_pos_c==3'd3) & load_din) + width_pre <= is_width; + end +end +always @( + stat_cur + or is_pos_w + or is_width + ) begin +//if((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din) + if((stat_cur==FIRST_C) & (is_pos_w == 0)) + width_cur_1 = is_width; + else + width_cur_1 = 0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cur_2 <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din) + width_cur_2 <= is_width; + end +end +//assign width_cur = ((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din)? width_cur_1 : width_cur_2; +assign width_cur = ((stat_cur==FIRST_C) & (is_pos_w == 0))? width_cur_1 : width_cur_2; +assign more2less = (stat_cur==FIRST_C) & (width_curwidth_pre); +assign l2m_1stC_vld = (stat_cur==FIRST_C) & less2more & (is_pos_w <= width_pre); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here <= 1'b0; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + hold_here <= 1; + else if((width_pre_cnt == width_pre) & rdma2dp_ready_normal) + hold_here <= 0; + end else if(NormalC2CubeEnd)//stat_cur==CUBE_END) + hold_here <= 1; + else if(cube_done) + hold_here <= 0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt[3:0] <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + width_pre_cnt[3:0] <= is_width+4'd1; + else if(hold_here & rdma2dp_ready_normal) + width_pre_cnt[3:0] <= width_pre_cnt+4'd1; + end else + width_pre_cnt[3:0] <= 4'd0; + end +end +//the last block data need to be output in cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_width <= {4{1'b0}}; + end else begin + if(NormalC2CubeEnd & load_din) + last_width <= is_width; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_width_cnt <= {4{1'b0}}; + end else begin + if(stat_cur==CUBE_END) begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt == last_width) + cube_end_width_cnt <= 4'd0; + else + cube_end_width_cnt <= cube_end_width_cnt + 1; + end + end else + cube_end_width_cnt <= 4'd0; + end +end +assign cube_done = (stat_cur==CUBE_END) && (cube_end_width_cnt == last_width) & rdma2dp_ready_normal; +//1pipe delay for buffer data generation +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly <= {3{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + stat_cur_dly <= stat_cur; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + stat_cur_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + more2less_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + more2less_dly <= more2less; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + more2less_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + less2more_dly <= less2more; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + less2more_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + hold_here_dly <= hold_here; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + hold_here_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly <= {4{1'b0}}; + end else begin + if((stat_cur == CUBE_END) & rdma2dp_ready_normal) + is_pos_w_dly <= cube_end_width_cnt; + else if(load_din) + is_pos_w_dly <= is_pos_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_cnt_dly <= width_pre_cnt; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + width_pre_cnt_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_dly <= width_pre; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + width_pre_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +///////////////////////////// +//buffer data generation for output data +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_data <= {1*(8 +1)*3{1'b0}}; + end else begin + if(((stat_cur_dly==NORMAL_C) || (stat_cur_dly==SECOND_C) || (stat_cur_dly==CUBE_END)) & data_shift_load) begin + if(is_pos_w_dly==4'd0) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(is_pos_w_dly==4'd1) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(is_pos_w_dly==4'd2) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(is_pos_w_dly==4'd3) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(is_pos_w_dly==4'd4) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(is_pos_w_dly==4'd5) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(is_pos_w_dly==4'd6) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(is_pos_w_dly==4'd7) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end else if(stat_cur_dly==FIRST_C) begin + if(more2less_dly) begin +// if((~hold_here_dly) & data_shift_load) begin + if(data_shift_load) begin + if(is_pos_w_dly==4'd0) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(is_pos_w_dly==4'd1) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(is_pos_w_dly==4'd2) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(is_pos_w_dly==4'd3) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(is_pos_w_dly==4'd4) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(is_pos_w_dly==4'd5) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(is_pos_w_dly==4'd6) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(is_pos_w_dly==4'd7) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end else if(hold_here_dly & data_shift_ready) begin + if(width_pre_cnt_dly==4'd0) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(width_pre_cnt_dly==4'd1) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(width_pre_cnt_dly==4'd2) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(width_pre_cnt_dly==4'd3) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(width_pre_cnt_dly==4'd4) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(width_pre_cnt_dly==4'd5) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(width_pre_cnt_dly==4'd6) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(width_pre_cnt_dly==4'd7) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end + end else begin + if((is_pos_w_dly<=width_pre_dly) & data_shift_load) begin + if(is_pos_w_dly==4'd0 ) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(is_pos_w_dly==4'd1 ) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(is_pos_w_dly==4'd2 ) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(is_pos_w_dly==4'd3 ) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(is_pos_w_dly==4'd4 ) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(is_pos_w_dly==4'd5 ) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(is_pos_w_dly==4'd6 ) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(is_pos_w_dly==4'd7 ) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end else if(data_shift_load) begin + buffer_data <= {1*(8 +1)*3{1'd0}}; + end + end + end else if(data_shift_ready) begin + buffer_data <= {1*(8 +1)*3{1'd0}}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf_dat_vld <= 1'b0; + end else begin + if(data_shift_valid) + buf_dat_vld <= 1'b1 ; + else if(buf_dat_rdy) + buf_dat_vld <= 1'b0 ; + end +end +// assign buf_dat_rdy = buffer_ready; +//assign buf_dat_load_all = buf_dat_vld & buf_dat_rdy; +//assign buf_dat_load = buf_dat_load_all & (~hold_here_dly2); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly2 <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + stat_cur_dly2 <= stat_cur_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + stat_cur_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly2 <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + less2more_dly2 <= less2more_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + less2more_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + is_pos_w_dly2 <= is_pos_w_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + is_pos_w_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + width_pre_dly2 <= width_pre_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + width_pre_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + stat_cur_dly2 + or less2more_dly2 + or is_pos_w_dly2 + or width_pre_dly2 + or buf_dat_vld + ) begin + if(((stat_cur_dly2==FIRST_C) & less2more_dly2 & (is_pos_w_dly2 > width_pre_dly2)) || (stat_cur_dly2==WAIT)) + buffer_data_vld = 1'b0; + else + buffer_data_vld = buf_dat_vld; +end +/////////////////////////////////////////////////////////////////////////////////////////// +//output data_info generation +/////////////////////////////////////////////////////////////////////////////////////////// +assign FIRST_C_end = ((stat_cur==FIRST_C) & (width_pre_cnt == width_pre) & more2less & rdma2dp_ready_normal); +assign FIRST_C_bf_end = ((stat_cur==FIRST_C) & (width_pre_cnt < width_pre) & more2less); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_align <= {4{1'b0}}; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + width_align <= is_width; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + width_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_w_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_w_align <= is_last_w; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + last_w_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_h_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_h_align <= is_last_h; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + last_h_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_c_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_c_align <= is_last_c; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + last_c_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_c_align <= {3{1'b0}}; + end else begin + if(FIRST_C_end) + pos_c_align <= 3'd0; + else if(is_b_sync & load_din & (~FIRST_C_bf_end)) + pos_c_align <= is_pos_c; + end +end +always @(*) begin + if(stat_cur==CUBE_END) + pos_w_align = cube_end_width_cnt; + else if(stat_cur==WAIT) + pos_w_align = 4'd0; + else if(stat_cur==FIRST_C) begin + if(more2less) begin + if(hold_here) + pos_w_align = width_pre_cnt; + else + pos_w_align = is_pos_w; + end else if(less2more) begin + if((is_pos_w <= width_pre)) + pos_w_align = is_pos_w; + else + pos_w_align = 4'd0; + end else + pos_w_align = is_pos_w; + end else + pos_w_align = is_pos_w; +end +always @(*) begin + if(stat_cur==CUBE_END) + b_sync_align = cube_done; + else if(stat_cur==WAIT) + b_sync_align = 1'b0; + else if(stat_cur==FIRST_C) begin + if(more2less) + b_sync_align = (width_pre_cnt == width_pre); + else if(less2more) + b_sync_align = (is_pos_w == width_pre) & load_din; + else + b_sync_align = (is_b_sync & load_din); + end + else + b_sync_align = (is_b_sync & load_din); +end +/////////////////// +//Two cycle delay +/////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_w_dly1 <= {4{1'b0}}; + width_dly1 <= {4{1'b0}}; + pos_c_dly1 <= {3{1'b0}}; + b_sync_dly1 <= 1'b0; + last_w_dly1 <= 1'b0; + last_h_dly1 <= 1'b0; + last_c_dly1 <= 1'b0; + end else begin + if((((stat_cur==NORMAL_C)||(stat_cur==SECOND_C)) & load_din) + || ((stat_cur==CUBE_END) & rdma2dp_ready_normal))begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(stat_cur==FIRST_C) begin + if(more2less & rdma2dp_ready_normal) begin + if(hold_here) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(less2more) begin + if(l2m_1stC_vld & load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(load_din)begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_w <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_w <= pos_w_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_pos_w <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_width <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_width <= width_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_c <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_c <= pos_c_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_pos_c <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_b_sync <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_b_sync <= b_sync_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_b_sync <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_w <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_w <= last_w_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_last_w <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_h <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_h <= last_h_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_last_h <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_c <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_c <= last_c_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_last_c <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +///////////////////////////////////////// +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}; +//: print qq( +//: assign buffer_pd[${k}-1:0] = buffer_data[${k}-1+4*${icvto}:4*${icvto}]; +//: assign buffer_pd[${k}+3:${k}] = buffer_pos_w[3:0]; +//: assign buffer_pd[${k}+7:${k}+4] = buffer_width[3:0]; +//: assign buffer_pd[${k}+10:${k}+8] = buffer_pos_c[2:0]; +//: assign buffer_pd[${k}+11] = buffer_b_sync ; +//: assign buffer_pd[${k}+12] = buffer_last_w ; +//: assign buffer_pd[${k}+13] = buffer_last_h ; +//: assign buffer_pd[${k}+14] = buffer_last_c ; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign buffer_pd[81-1:0] = buffer_data[81-1+4*9:4*9]; +assign buffer_pd[81+3:81] = buffer_pos_w[3:0]; +assign buffer_pd[81+7:81+4] = buffer_width[3:0]; +assign buffer_pd[81+10:81+8] = buffer_pos_c[2:0]; +assign buffer_pd[81+11] = buffer_b_sync ; +assign buffer_pd[81+12] = buffer_last_w ; +assign buffer_pd[81+13] = buffer_last_h ; +assign buffer_pd[81+14] = buffer_last_c ; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////////////////////// +assign buffer_valid = buffer_data_vld; +///////////////////////////////////////// +//output data pipe for register out +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: &eperl::pipe(" -is -wid $k -do normalz_buf_data -vo normalz_buf_data_pvld -ri normalz_buf_data_prdy -di buffer_pd -vi buffer_valid -ro buffer_ready "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg buffer_ready; +reg skid_flop_buffer_ready; +reg skid_flop_buffer_valid; +reg [96-1:0] skid_flop_buffer_pd; +reg pipe_skid_buffer_valid; +reg [96-1:0] pipe_skid_buffer_pd; +// Wire +wire skid_buffer_valid; +wire [96-1:0] skid_buffer_pd; +wire skid_buffer_ready; +wire pipe_skid_buffer_ready; +wire normalz_buf_data_pvld; +wire [96-1:0] normalz_buf_data; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_ready <= 1'b1; + skid_flop_buffer_ready <= 1'b1; + end else begin + buffer_ready <= skid_buffer_ready; + skid_flop_buffer_ready <= skid_buffer_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_buffer_valid <= 1'b0; + end else begin + if (skid_flop_buffer_ready) begin + skid_flop_buffer_valid <= buffer_valid; + end + end +end +assign skid_buffer_valid = (skid_flop_buffer_ready) ? buffer_valid : skid_flop_buffer_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_buffer_ready & buffer_valid) begin + skid_flop_buffer_pd[96-1:0] <= buffer_pd[96-1:0]; + end +end +assign skid_buffer_pd[96-1:0] = (skid_flop_buffer_ready) ? buffer_pd[96-1:0] : skid_flop_buffer_pd[96-1:0]; + + +// PIPE READY +assign skid_buffer_ready = pipe_skid_buffer_ready || !pipe_skid_buffer_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_buffer_valid <= 1'b0; + end else begin + if (skid_buffer_ready) begin + pipe_skid_buffer_valid <= skid_buffer_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_buffer_ready && skid_buffer_valid) begin + pipe_skid_buffer_pd[96-1:0] <= skid_buffer_pd[96-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_buffer_ready = normalz_buf_data_prdy; +assign normalz_buf_data_pvld = pipe_skid_buffer_valid; +assign normalz_buf_data = pipe_skid_buffer_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign buf_dat_rdy = buffer_ready; +///////////////////////////////////////// +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_bufin_widthchange__more2less__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & more2less; + endproperty +// Cover 0 : "load_din_full & more2less" + FUNCPOINT_CDP_bufin_widthchange__more2less__0_COV : cover property (CDP_bufin_widthchange__more2less__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_bufin_widthchange__less2more__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & less2more; + endproperty +// Cover 1 : "load_din_full & less2more" + FUNCPOINT_CDP_bufin_widthchange__less2more__1_COV : cover property (CDP_bufin_widthchange__less2more__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_DP_bufferin diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v.vcp new file mode 100644 index 0000000..ccf7bac --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v.vcp @@ -0,0 +1,2291 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_bufferin.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_bufferin ( + nvdla_core_clk + ,nvdla_core_rstn + ,cdp_rdma2dp_pd + ,cdp_rdma2dp_valid + ,normalz_buf_data_prdy + ,cdp_rdma2dp_ready + ,normalz_buf_data + ,normalz_buf_data_pvld + ); +///////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*(8 +1)+14:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +input normalz_buf_data_prdy; +output cdp_rdma2dp_ready; +//output [1*(8 +1)*3+14:0] normalz_buf_data; +output [(1 +8)*(8 +1)+14:0] normalz_buf_data; +output normalz_buf_data_pvld; +///////////////////////////////////////////////////////////// +reg NormalC2CubeEnd; +reg b_sync_align; +reg b_sync_dly1; +reg buf_dat_vld; +reg buffer_b_sync; +reg [1*(8 +1)*3:0] buffer_data; +reg buffer_data_vld; +reg buffer_last_c; +reg buffer_last_h; +reg buffer_last_w; +reg [2:0] buffer_pos_c; +reg [3:0] buffer_pos_w; +//reg buffer_ready; +reg [3:0] buffer_width; +//reg cdp_rdma2dp_ready; +reg [3:0] cube_end_width_cnt; +reg [1*(8 +1)-1:0] data_1stC_0; +reg [1*(8 +1)-1:0] data_1stC_1; +reg [1*(8 +1)-1:0] data_1stC_2; +reg [1*(8 +1)-1:0] data_1stC_3; +reg [1*(8 +1)-1:0] data_1stC_4; +reg [1*(8 +1)-1:0] data_1stC_5; +reg [1*(8 +1)-1:0] data_1stC_6; +reg [1*(8 +1)-1:0] data_1stC_7; +reg [1*(8 +1)-1:0] data_shift_00; +reg [1*(8 +1)-1:0] data_shift_01; +reg [1*(8 +1)-1:0] data_shift_02; +reg [1*(8 +1)-1:0] data_shift_10; +reg [1*(8 +1)-1:0] data_shift_11; +reg [1*(8 +1)-1:0] data_shift_12; +reg [1*(8 +1)-1:0] data_shift_20; +reg [1*(8 +1)-1:0] data_shift_21; +reg [1*(8 +1)-1:0] data_shift_22; +reg [1*(8 +1)-1:0] data_shift_30; +reg [1*(8 +1)-1:0] data_shift_31; +reg [1*(8 +1)-1:0] data_shift_32; +reg [1*(8 +1)-1:0] data_shift_40; +reg [1*(8 +1)-1:0] data_shift_41; +reg [1*(8 +1)-1:0] data_shift_42; +reg [1*(8 +1)-1:0] data_shift_50; +reg [1*(8 +1)-1:0] data_shift_51; +reg [1*(8 +1)-1:0] data_shift_52; +reg [1*(8 +1)-1:0] data_shift_60; +reg [1*(8 +1)-1:0] data_shift_61; +reg [1*(8 +1)-1:0] data_shift_62; +reg [1*(8 +1)-1:0] data_shift_70; +reg [1*(8 +1)-1:0] data_shift_71; +reg [1*(8 +1)-1:0] data_shift_72; +reg data_shift_valid; +reg hold_here; +reg hold_here_dly; +reg [3:0] is_pos_w_dly; +reg [3:0] is_pos_w_dly2; +reg last_c_align; +reg last_c_dly1; +reg last_h_align; +reg last_h_dly1; +reg last_w_align; +reg last_w_dly1; +reg [3:0] last_width; +reg less2more_dly; +reg less2more_dly2; +reg more2less_dly; +reg [2:0] pos_c_align; +reg [2:0] pos_c_dly1; +reg [3:0] pos_w_align; +reg [3:0] pos_w_dly1; +reg [2:0] stat_cur; +reg [2:0] stat_cur_dly; +reg [2:0] stat_cur_dly2; +reg [2:0] stat_nex; +reg [3:0] width_align; +reg [3:0] width_cur_1; +reg [3:0] width_cur_2; +reg [3:0] width_dly1; +reg [3:0] width_pre; +reg [3:0] width_pre_cnt; +reg [3:0] width_pre_cnt_dly; +reg [3:0] width_pre_dly; +reg [3:0] width_pre_dly2; +wire FIRST_C_bf_end; +wire FIRST_C_end; +wire buf_dat_rdy; +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: print "wire [${k}-1:0] buffer_pd; \n"; +wire buffer_valid; +wire cube_done; +wire data_shift_load; +wire data_shift_load_all; +wire data_shift_ready; +wire dp_b_sync; +wire [1*(8 +1):0] dp_data; +wire dp_last_c; +wire dp_last_h; +wire dp_last_w; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire [3:0] dp_width; +wire is_b_sync; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire [2:0] is_pos_c; +wire [3:0] is_pos_w; +wire [3:0] is_width; +wire [3:0] is_width_f; +wire l2m_1stC_vld; +wire less2more; +wire load_din; +wire load_din_full; +wire more2less; +wire nvdla_cdp_rdma2dp_ready; +wire rdma2dp_ready_normal; +wire rdma2dp_valid_rebuild; +wire vld; +wire [3:0] width_cur; +///////////////////////////////////////////////////////////// +// +parameter cvt2buf_data_bw = 1*(8 +1); +parameter cvt2buf_info_bw = 15; +parameter cvt2buf_dp_bw = cvt2buf_data_bw + cvt2buf_info_bw; +///////////////////////////////////////////////////////////// +//: my $k = 1*(8 +1)+15; +//: &eperl::pipe(" -is -wid $k -do nvdla_cdp_rdma2dp_pd -vo nvdla_cdp_rdma2dp_valid -ri nvdla_cdp_rdma2dp_ready -di cdp_rdma2dp_pd -vi cdp_rdma2dp_valid -ro cdp_rdma2dp_ready "); +//============== +// INPUT UNPACK: from RDMA +//============== +assign dp_data[1*(8 +1)-1:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)-1:0]; +assign dp_pos_w[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+3:1*(8 +1)]; +assign dp_width[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+7:1*(8 +1)+4]; +assign dp_pos_c[2:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+10:1*(8 +1)+8]; +assign dp_b_sync = nvdla_cdp_rdma2dp_pd[1*(8 +1)+11]; +assign dp_last_w = nvdla_cdp_rdma2dp_pd[1*(8 +1)+12]; +assign dp_last_h = nvdla_cdp_rdma2dp_pd[1*(8 +1)+13]; +assign dp_last_c = nvdla_cdp_rdma2dp_pd[1*(8 +1)+14]; +assign is_pos_w = dp_pos_w; +assign is_width_f = dp_width[3:0]; +assign is_width[3:0] = is_width_f - 1'b1; +assign is_pos_c = dp_pos_c; +assign is_b_sync = dp_b_sync ; +assign is_last_w = dp_last_w ; +assign is_last_h = dp_last_h ; +assign is_last_c = dp_last_c ; +/////////////////////////////////////////////////// +assign nvdla_cdp_rdma2dp_ready = rdma2dp_ready_normal & (~hold_here); +assign rdma2dp_valid_rebuild = nvdla_cdp_rdma2dp_valid | hold_here; +assign vld = rdma2dp_valid_rebuild; +assign load_din = vld & nvdla_cdp_rdma2dp_ready; +assign load_din_full = rdma2dp_valid_rebuild & rdma2dp_ready_normal; +/////////////////////////////////////////////////// +localparam WAIT = 3'b000; +localparam NORMAL_C = 3'b001; +localparam FIRST_C = 3'b010; +localparam SECOND_C = 3'b011; +localparam CUBE_END = 3'b100; + always @(*) begin + stat_nex = stat_cur; + NormalC2CubeEnd = 0; + begin + casez (stat_cur) + WAIT: begin + if ((is_b_sync & (is_pos_c==3'd0) & load_din)) begin + stat_nex = NORMAL_C; + end + end + NORMAL_C: begin + if ((is_b_sync & (is_pos_c==3'd3) & is_last_c & is_last_h & is_last_w & load_din)) begin + NormalC2CubeEnd = 1; + stat_nex = CUBE_END; + end + else if ((is_b_sync & (is_pos_c==3'd3) & is_last_c) & (~(is_last_h & is_last_w) & load_din)) begin + stat_nex = FIRST_C; + end + end + FIRST_C: begin + if (((is_pos_w == is_width) & (~more2less) & load_din) + ||(more2less & (width_pre_cnt == width_pre) & hold_here & rdma2dp_ready_normal)) begin + stat_nex = SECOND_C; + end + end + SECOND_C: begin + if (is_b_sync & load_din) begin + stat_nex = NORMAL_C; + end + end + CUBE_END: begin + if (cube_done) begin + stat_nex = WAIT; + end + end +// VCS coverage off + default: begin + stat_nex = WAIT; + `ifndef SYNTHESIS + stat_nex = {3{1'bx}}; + `endif + end +// VCS coverage on + endcase + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur <= WAIT; + end else begin + stat_cur <= stat_nex; + end + end +///////////////////////////////////////// +assign rdma2dp_ready_normal = (~data_shift_valid) | data_shift_ready; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_shift_valid <= 1'b0; + end else begin + if(vld) + data_shift_valid <= 1'b1; + else if(data_shift_ready) + data_shift_valid <= 1'b0; + end +end +assign data_shift_ready =(~buf_dat_vld | buf_dat_rdy); +assign data_shift_load_all = data_shift_ready & data_shift_valid; +assign data_shift_load = data_shift_load_all & ((~hold_here_dly) | (stat_cur_dly == CUBE_END)); +///////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_shift_00 <= {1*(8 +1){1'b0}}; + data_shift_10 <= {1*(8 +1){1'b0}}; + data_shift_20 <= {1*(8 +1){1'b0}}; + data_shift_30 <= {1*(8 +1){1'b0}}; + data_shift_40 <= {1*(8 +1){1'b0}}; + data_shift_50 <= {1*(8 +1){1'b0}}; + data_shift_60 <= {1*(8 +1){1'b0}}; + data_shift_70 <= {1*(8 +1){1'b0}}; + data_shift_01 <= {1*(8 +1){1'b0}}; + data_shift_02 <= {1*(8 +1){1'b0}}; + data_shift_11 <= {1*(8 +1){1'b0}}; + data_shift_12 <= {1*(8 +1){1'b0}}; + data_shift_21 <= {1*(8 +1){1'b0}}; + data_shift_22 <= {1*(8 +1){1'b0}}; + data_shift_31 <= {1*(8 +1){1'b0}}; + data_shift_32 <= {1*(8 +1){1'b0}}; + data_shift_41 <= {1*(8 +1){1'b0}}; + data_shift_42 <= {1*(8 +1){1'b0}}; + data_shift_51 <= {1*(8 +1){1'b0}}; + data_shift_52 <= {1*(8 +1){1'b0}}; + data_shift_61 <= {1*(8 +1){1'b0}}; + data_shift_62 <= {1*(8 +1){1'b0}}; + data_shift_71 <= {1*(8 +1){1'b0}}; + data_shift_72 <= {1*(8 +1){1'b0}}; + data_1stC_0 <= {1*(8 +1){1'b0}}; + data_1stC_1 <= {1*(8 +1){1'b0}}; + data_1stC_2 <= {1*(8 +1){1'b0}}; + data_1stC_3 <= {1*(8 +1){1'b0}}; + data_1stC_4 <= {1*(8 +1){1'b0}}; + data_1stC_5 <= {1*(8 +1){1'b0}}; + data_1stC_6 <= {1*(8 +1){1'b0}}; + data_1stC_7 <= {1*(8 +1){1'b0}}; + end else begin + case(stat_cur) + WAIT: begin + if(load_din) begin + if(is_pos_w==4'd0) begin + data_shift_00 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd1) begin + data_shift_10 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd2) begin + data_shift_20 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd3) begin + data_shift_30 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd4) begin + data_shift_40 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd5) begin + data_shift_50 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd6) begin + data_shift_60 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd7) begin + data_shift_70 <= dp_data[cvt2buf_data_bw-1:0]; + end + data_shift_01 <= {cvt2buf_data_bw{1'd0}}; + data_shift_02 <= {cvt2buf_data_bw{1'd0}}; + data_shift_11 <= {cvt2buf_data_bw{1'd0}}; + data_shift_12 <= {cvt2buf_data_bw{1'd0}}; + data_shift_21 <= {cvt2buf_data_bw{1'd0}}; + data_shift_22 <= {cvt2buf_data_bw{1'd0}}; + data_shift_31 <= {cvt2buf_data_bw{1'd0}}; + data_shift_32 <= {cvt2buf_data_bw{1'd0}}; + data_shift_41 <= {cvt2buf_data_bw{1'd0}}; + data_shift_42 <= {cvt2buf_data_bw{1'd0}}; + data_shift_51 <= {cvt2buf_data_bw{1'd0}}; + data_shift_52 <= {cvt2buf_data_bw{1'd0}}; + data_shift_61 <= {cvt2buf_data_bw{1'd0}}; + data_shift_62 <= {cvt2buf_data_bw{1'd0}}; + data_shift_71 <= {cvt2buf_data_bw{1'd0}}; + data_shift_72 <= {cvt2buf_data_bw{1'd0}}; + end end + NORMAL_C: begin + if(load_din) begin + if(is_pos_w==4'd0) begin + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd1) begin + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd2) begin + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd3) begin + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd4) begin + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd5) begin + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd6) begin + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd7) begin + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= dp_data[cvt2buf_data_bw-1:0]; + end + end end + FIRST_C: begin + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd0) begin + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd0) & load_din) begin + data_1stC_0 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd1) begin + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd1) & load_din) begin + data_1stC_1 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd2) begin + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd2) & load_din) begin + data_1stC_2 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd3) begin + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd3) & load_din) begin + data_1stC_3 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd4) begin + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd4) & load_din) begin + data_1stC_4 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd5) begin + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd5) & load_din) begin + data_1stC_5 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd6) begin + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd6) & load_din) begin + data_1stC_6 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + end + end + if(hold_here & rdma2dp_ready_normal) begin + if(width_pre_cnt==4'd7) begin + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + end + end else begin + if((is_pos_w==4'd7) & load_din) begin + data_1stC_7 <= dp_data[cvt2buf_data_bw-1:0]; + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + end + end + end// end + SECOND_C: begin + if(load_din) begin + if(is_pos_w==4'd0) begin + data_shift_02 <= 0; + data_shift_01 <= data_1stC_0; + data_shift_00 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd1) begin + data_shift_12 <= 0; + data_shift_11 <= data_1stC_1; + data_shift_10 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd2) begin + data_shift_22 <= 0; + data_shift_21 <= data_1stC_2; + data_shift_20 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd3) begin + data_shift_32 <= 0; + data_shift_31 <= data_1stC_3; + data_shift_30 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd4) begin + data_shift_42 <= 0; + data_shift_41 <= data_1stC_4; + data_shift_40 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd5) begin + data_shift_52 <= 0; + data_shift_51 <= data_1stC_5; + data_shift_50 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd6) begin + data_shift_62 <= 0; + data_shift_61 <= data_1stC_6; + data_shift_60 <= dp_data[cvt2buf_data_bw-1:0]; + end + if(is_pos_w==4'd7) begin + data_shift_72 <= 0; + data_shift_71 <= data_1stC_7; + data_shift_70 <= dp_data[cvt2buf_data_bw-1:0]; + end + end end + CUBE_END: begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt==4'd0) begin + data_shift_02 <= data_shift_01; + data_shift_01 <= data_shift_00; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd1) begin + data_shift_12 <= data_shift_11; + data_shift_11 <= data_shift_10; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd2) begin + data_shift_22 <= data_shift_21; + data_shift_21 <= data_shift_20; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd3) begin + data_shift_32 <= data_shift_31; + data_shift_31 <= data_shift_30; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd4) begin + data_shift_42 <= data_shift_41; + data_shift_41 <= data_shift_40; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd5) begin + data_shift_52 <= data_shift_51; + data_shift_51 <= data_shift_50; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd6) begin + data_shift_62 <= data_shift_61; + data_shift_61 <= data_shift_60; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + end + if(cube_end_width_cnt==4'd7) begin + data_shift_72 <= data_shift_71; + data_shift_71 <= data_shift_70; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + end + end end + default: begin + data_shift_02 <= {cvt2buf_data_bw{1'd0}}; + data_shift_01 <= {cvt2buf_data_bw{1'd0}}; + data_shift_00 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_0 <= {cvt2buf_data_bw{1'd0}}; + data_shift_12 <= {cvt2buf_data_bw{1'd0}}; + data_shift_11 <= {cvt2buf_data_bw{1'd0}}; + data_shift_10 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_1 <= {cvt2buf_data_bw{1'd0}}; + data_shift_22 <= {cvt2buf_data_bw{1'd0}}; + data_shift_21 <= {cvt2buf_data_bw{1'd0}}; + data_shift_20 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_2 <= {cvt2buf_data_bw{1'd0}}; + data_shift_32 <= {cvt2buf_data_bw{1'd0}}; + data_shift_31 <= {cvt2buf_data_bw{1'd0}}; + data_shift_30 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_3 <= {cvt2buf_data_bw{1'd0}}; + data_shift_42 <= {cvt2buf_data_bw{1'd0}}; + data_shift_41 <= {cvt2buf_data_bw{1'd0}}; + data_shift_40 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_4 <= {cvt2buf_data_bw{1'd0}}; + data_shift_52 <= {cvt2buf_data_bw{1'd0}}; + data_shift_51 <= {cvt2buf_data_bw{1'd0}}; + data_shift_50 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_5 <= {cvt2buf_data_bw{1'd0}}; + data_shift_62 <= {cvt2buf_data_bw{1'd0}}; + data_shift_61 <= {cvt2buf_data_bw{1'd0}}; + data_shift_60 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_6 <= {cvt2buf_data_bw{1'd0}}; + data_shift_72 <= {cvt2buf_data_bw{1'd0}}; + data_shift_71 <= {cvt2buf_data_bw{1'd0}}; + data_shift_70 <= {cvt2buf_data_bw{1'd0}}; + data_1stC_7 <= {cvt2buf_data_bw{1'd0}}; + end + endcase + end + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre <= {4{1'b0}}; + end else begin + if((stat_cur==NORMAL_C) & is_last_c & is_b_sync & (is_pos_c==3'd3) & load_din) + width_pre <= is_width; + end +end +always @( + stat_cur + or is_pos_w + or is_width + ) begin +//if((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din) + if((stat_cur==FIRST_C) & (is_pos_w == 0)) + width_cur_1 = is_width; + else + width_cur_1 = 0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cur_2 <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din) + width_cur_2 <= is_width; + end +end +//assign width_cur = ((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din)? width_cur_1 : width_cur_2; +assign width_cur = ((stat_cur==FIRST_C) & (is_pos_w == 0))? width_cur_1 : width_cur_2; +assign more2less = (stat_cur==FIRST_C) & (width_curwidth_pre); +assign l2m_1stC_vld = (stat_cur==FIRST_C) & less2more & (is_pos_w <= width_pre); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here <= 1'b0; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + hold_here <= 1; + else if((width_pre_cnt == width_pre) & rdma2dp_ready_normal) + hold_here <= 0; + end else if(NormalC2CubeEnd)//stat_cur==CUBE_END) + hold_here <= 1; + else if(cube_done) + hold_here <= 0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt[3:0] <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + width_pre_cnt[3:0] <= is_width+4'd1; + else if(hold_here & rdma2dp_ready_normal) + width_pre_cnt[3:0] <= width_pre_cnt+4'd1; + end else + width_pre_cnt[3:0] <= 4'd0; + end +end +//the last block data need to be output in cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_width <= {4{1'b0}}; + end else begin + if(NormalC2CubeEnd & load_din) + last_width <= is_width; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_width_cnt <= {4{1'b0}}; + end else begin + if(stat_cur==CUBE_END) begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt == last_width) + cube_end_width_cnt <= 4'd0; + else + cube_end_width_cnt <= cube_end_width_cnt + 1; + end + end else + cube_end_width_cnt <= 4'd0; + end +end +assign cube_done = (stat_cur==CUBE_END) && (cube_end_width_cnt == last_width) & rdma2dp_ready_normal; +//1pipe delay for buffer data generation +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly <= {3{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + stat_cur_dly <= stat_cur; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + stat_cur_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + more2less_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + more2less_dly <= more2less; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + more2less_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + less2more_dly <= less2more; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + less2more_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + hold_here_dly <= hold_here; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + hold_here_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly <= {4{1'b0}}; + end else begin + if((stat_cur == CUBE_END) & rdma2dp_ready_normal) + is_pos_w_dly <= cube_end_width_cnt; + else if(load_din) + is_pos_w_dly <= is_pos_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_cnt_dly <= width_pre_cnt; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + width_pre_cnt_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_dly <= width_pre; +// VCS coverage off + end else if ((load_din_full) == 1'b0) begin + end else begin + width_pre_dly <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_full))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +///////////////////////////// +//buffer data generation for output data +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_data <= {1*(8 +1)*3{1'b0}}; + end else begin + if(((stat_cur_dly==NORMAL_C) || (stat_cur_dly==SECOND_C) || (stat_cur_dly==CUBE_END)) & data_shift_load) begin + if(is_pos_w_dly==4'd0) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(is_pos_w_dly==4'd1) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(is_pos_w_dly==4'd2) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(is_pos_w_dly==4'd3) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(is_pos_w_dly==4'd4) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(is_pos_w_dly==4'd5) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(is_pos_w_dly==4'd6) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(is_pos_w_dly==4'd7) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end else if(stat_cur_dly==FIRST_C) begin + if(more2less_dly) begin +// if((~hold_here_dly) & data_shift_load) begin + if(data_shift_load) begin + if(is_pos_w_dly==4'd0) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(is_pos_w_dly==4'd1) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(is_pos_w_dly==4'd2) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(is_pos_w_dly==4'd3) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(is_pos_w_dly==4'd4) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(is_pos_w_dly==4'd5) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(is_pos_w_dly==4'd6) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(is_pos_w_dly==4'd7) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end else if(hold_here_dly & data_shift_ready) begin + if(width_pre_cnt_dly==4'd0) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(width_pre_cnt_dly==4'd1) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(width_pre_cnt_dly==4'd2) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(width_pre_cnt_dly==4'd3) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(width_pre_cnt_dly==4'd4) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(width_pre_cnt_dly==4'd5) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(width_pre_cnt_dly==4'd6) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(width_pre_cnt_dly==4'd7) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end + end else begin + if((is_pos_w_dly<=width_pre_dly) & data_shift_load) begin + if(is_pos_w_dly==4'd0 ) + buffer_data <= {data_shift_00,data_shift_01,data_shift_02}; + if(is_pos_w_dly==4'd1 ) + buffer_data <= {data_shift_10,data_shift_11,data_shift_12}; + if(is_pos_w_dly==4'd2 ) + buffer_data <= {data_shift_20,data_shift_21,data_shift_22}; + if(is_pos_w_dly==4'd3 ) + buffer_data <= {data_shift_30,data_shift_31,data_shift_32}; + if(is_pos_w_dly==4'd4 ) + buffer_data <= {data_shift_40,data_shift_41,data_shift_42}; + if(is_pos_w_dly==4'd5 ) + buffer_data <= {data_shift_50,data_shift_51,data_shift_52}; + if(is_pos_w_dly==4'd6 ) + buffer_data <= {data_shift_60,data_shift_61,data_shift_62}; + if(is_pos_w_dly==4'd7 ) + buffer_data <= {data_shift_70,data_shift_71,data_shift_72}; + end else if(data_shift_load) begin + buffer_data <= {1*(8 +1)*3{1'd0}}; + end + end + end else if(data_shift_ready) begin + buffer_data <= {1*(8 +1)*3{1'd0}}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf_dat_vld <= 1'b0; + end else begin + if(data_shift_valid) + buf_dat_vld <= 1'b1 ; + else if(buf_dat_rdy) + buf_dat_vld <= 1'b0 ; + end +end +// assign buf_dat_rdy = buffer_ready; +//assign buf_dat_load_all = buf_dat_vld & buf_dat_rdy; +//assign buf_dat_load = buf_dat_load_all & (~hold_here_dly2); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly2 <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + stat_cur_dly2 <= stat_cur_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + stat_cur_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly2 <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + less2more_dly2 <= less2more_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + less2more_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + is_pos_w_dly2 <= is_pos_w_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + is_pos_w_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + width_pre_dly2 <= width_pre_dly; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + width_pre_dly2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + stat_cur_dly2 + or less2more_dly2 + or is_pos_w_dly2 + or width_pre_dly2 + or buf_dat_vld + ) begin + if(((stat_cur_dly2==FIRST_C) & less2more_dly2 & (is_pos_w_dly2 > width_pre_dly2)) || (stat_cur_dly2==WAIT)) + buffer_data_vld = 1'b0; + else + buffer_data_vld = buf_dat_vld; +end +/////////////////////////////////////////////////////////////////////////////////////////// +//output data_info generation +/////////////////////////////////////////////////////////////////////////////////////////// +assign FIRST_C_end = ((stat_cur==FIRST_C) & (width_pre_cnt == width_pre) & more2less & rdma2dp_ready_normal); +assign FIRST_C_bf_end = ((stat_cur==FIRST_C) & (width_pre_cnt < width_pre) & more2less); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_align <= {4{1'b0}}; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + width_align <= is_width; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + width_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_w_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_w_align <= is_last_w; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + last_w_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_h_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_h_align <= is_last_h; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + last_h_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_c_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_c_align <= is_last_c; +// VCS coverage off + end else if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b0) begin + end else begin + last_c_align <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_c_align <= {3{1'b0}}; + end else begin + if(FIRST_C_end) + pos_c_align <= 3'd0; + else if(is_b_sync & load_din & (~FIRST_C_bf_end)) + pos_c_align <= is_pos_c; + end +end +always @(*) begin + if(stat_cur==CUBE_END) + pos_w_align = cube_end_width_cnt; + else if(stat_cur==WAIT) + pos_w_align = 4'd0; + else if(stat_cur==FIRST_C) begin + if(more2less) begin + if(hold_here) + pos_w_align = width_pre_cnt; + else + pos_w_align = is_pos_w; + end else if(less2more) begin + if((is_pos_w <= width_pre)) + pos_w_align = is_pos_w; + else + pos_w_align = 4'd0; + end else + pos_w_align = is_pos_w; + end else + pos_w_align = is_pos_w; +end +always @(*) begin + if(stat_cur==CUBE_END) + b_sync_align = cube_done; + else if(stat_cur==WAIT) + b_sync_align = 1'b0; + else if(stat_cur==FIRST_C) begin + if(more2less) + b_sync_align = (width_pre_cnt == width_pre); + else if(less2more) + b_sync_align = (is_pos_w == width_pre) & load_din; + else + b_sync_align = (is_b_sync & load_din); + end + else + b_sync_align = (is_b_sync & load_din); +end +/////////////////// +//Two cycle delay +/////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_w_dly1 <= {4{1'b0}}; + width_dly1 <= {4{1'b0}}; + pos_c_dly1 <= {3{1'b0}}; + b_sync_dly1 <= 1'b0; + last_w_dly1 <= 1'b0; + last_h_dly1 <= 1'b0; + last_c_dly1 <= 1'b0; + end else begin + if((((stat_cur==NORMAL_C)||(stat_cur==SECOND_C)) & load_din) + || ((stat_cur==CUBE_END) & rdma2dp_ready_normal))begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(stat_cur==FIRST_C) begin + if(more2less & rdma2dp_ready_normal) begin + if(hold_here) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(less2more) begin + if(l2m_1stC_vld & load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(load_din)begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_w <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_w <= pos_w_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_pos_w <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_width <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_width <= width_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_c <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_c <= pos_c_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_pos_c <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_b_sync <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_b_sync <= b_sync_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_b_sync <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_w <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_w <= last_w_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_last_w <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_h <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_h <= last_h_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_last_h <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_c <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_c <= last_c_dly1; +// VCS coverage off + end else if ((data_shift_load_all) == 1'b0) begin + end else begin + buffer_last_c <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(data_shift_load_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +///////////////////////////////////////// +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}; +//: print qq( +//: assign buffer_pd[${k}-1:0] = buffer_data[${k}-1+4*${icvto}:4*${icvto}]; +//: assign buffer_pd[${k}+3:${k}] = buffer_pos_w[3:0]; +//: assign buffer_pd[${k}+7:${k}+4] = buffer_width[3:0]; +//: assign buffer_pd[${k}+10:${k}+8] = buffer_pos_c[2:0]; +//: assign buffer_pd[${k}+11] = buffer_b_sync ; +//: assign buffer_pd[${k}+12] = buffer_last_w ; +//: assign buffer_pd[${k}+13] = buffer_last_h ; +//: assign buffer_pd[${k}+14] = buffer_last_c ; +//: ); +///////////////////////////////////////// +assign buffer_valid = buffer_data_vld; +///////////////////////////////////////// +//output data pipe for register out +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: &eperl::pipe(" -is -wid $k -do normalz_buf_data -vo normalz_buf_data_pvld -ri normalz_buf_data_prdy -di buffer_pd -vi buffer_valid -ro buffer_ready "); +assign buf_dat_rdy = buffer_ready; +///////////////////////////////////////// +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_bufin_widthchange__more2less__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & more2less; + endproperty +// Cover 0 : "load_din_full & more2less" + FUNCPOINT_CDP_bufin_widthchange__more2less__0_COV : cover property (CDP_bufin_widthchange__more2less__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_bufin_widthchange__less2more__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & less2more; + endproperty +// Cover 1 : "load_din_full & less2more" + FUNCPOINT_CDP_bufin_widthchange__less2more__1_COV : cover property (CDP_bufin_widthchange__less2more__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_DP_bufferin diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin_tp1.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin_tp1.v new file mode 100644 index 0000000..54e31f9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin_tp1.v @@ -0,0 +1,2598 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_bufferin_tp1.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_bufferin_tp1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cdp_rdma2dp_pd + ,cdp_rdma2dp_valid + ,normalz_buf_data_prdy + ,cdp_rdma2dp_ready + ,normalz_buf_data + ,normalz_buf_data_pvld + ); +////////////////////////////////////////////// +parameter buf2sq_data_bw = (8 +1)*(1 +8); +parameter buf2sq_dp_bw = buf2sq_data_bw + 15; +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*(8 +1)+15-1:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +input normalz_buf_data_prdy; +output cdp_rdma2dp_ready; +output [buf2sq_dp_bw-1:0] normalz_buf_data; +output normalz_buf_data_pvld; +////////////////////////////////////////////// +reg NormalC2CubeEnd; +reg b_sync_align; +reg b_sync_dly1; +reg buf_dat_vld; +reg buffer_b_sync; +reg [buf2sq_data_bw-1:0] buffer_data; +reg buffer_data_vld; +reg buffer_last_c; +reg buffer_last_h; +reg buffer_last_w; +reg [2:0] buffer_pos_c; +reg [3:0] buffer_pos_w; +reg [3:0] buffer_width; +wire cdp_rdma2dp_ready; +reg [3:0] cube_end_width_cnt; +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: foreach my $k (0..8) { +//: print qq( +//: reg [${tp}*${bpe}-1:0] data_shift_${k}${m}; +//: ); +//: } +//: } +//: foreach my $m (0..7) { +//: foreach my $k (0..4) { +//: print qq( +//: reg [${tp}*${bpe}-1:0] data_1stC_${k}${m}; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [1*9-1:0] data_shift_00; + +reg [1*9-1:0] data_shift_10; + +reg [1*9-1:0] data_shift_20; + +reg [1*9-1:0] data_shift_30; + +reg [1*9-1:0] data_shift_40; + +reg [1*9-1:0] data_shift_50; + +reg [1*9-1:0] data_shift_60; + +reg [1*9-1:0] data_shift_70; + +reg [1*9-1:0] data_shift_80; + +reg [1*9-1:0] data_shift_01; + +reg [1*9-1:0] data_shift_11; + +reg [1*9-1:0] data_shift_21; + +reg [1*9-1:0] data_shift_31; + +reg [1*9-1:0] data_shift_41; + +reg [1*9-1:0] data_shift_51; + +reg [1*9-1:0] data_shift_61; + +reg [1*9-1:0] data_shift_71; + +reg [1*9-1:0] data_shift_81; + +reg [1*9-1:0] data_shift_02; + +reg [1*9-1:0] data_shift_12; + +reg [1*9-1:0] data_shift_22; + +reg [1*9-1:0] data_shift_32; + +reg [1*9-1:0] data_shift_42; + +reg [1*9-1:0] data_shift_52; + +reg [1*9-1:0] data_shift_62; + +reg [1*9-1:0] data_shift_72; + +reg [1*9-1:0] data_shift_82; + +reg [1*9-1:0] data_shift_03; + +reg [1*9-1:0] data_shift_13; + +reg [1*9-1:0] data_shift_23; + +reg [1*9-1:0] data_shift_33; + +reg [1*9-1:0] data_shift_43; + +reg [1*9-1:0] data_shift_53; + +reg [1*9-1:0] data_shift_63; + +reg [1*9-1:0] data_shift_73; + +reg [1*9-1:0] data_shift_83; + +reg [1*9-1:0] data_shift_04; + +reg [1*9-1:0] data_shift_14; + +reg [1*9-1:0] data_shift_24; + +reg [1*9-1:0] data_shift_34; + +reg [1*9-1:0] data_shift_44; + +reg [1*9-1:0] data_shift_54; + +reg [1*9-1:0] data_shift_64; + +reg [1*9-1:0] data_shift_74; + +reg [1*9-1:0] data_shift_84; + +reg [1*9-1:0] data_shift_05; + +reg [1*9-1:0] data_shift_15; + +reg [1*9-1:0] data_shift_25; + +reg [1*9-1:0] data_shift_35; + +reg [1*9-1:0] data_shift_45; + +reg [1*9-1:0] data_shift_55; + +reg [1*9-1:0] data_shift_65; + +reg [1*9-1:0] data_shift_75; + +reg [1*9-1:0] data_shift_85; + +reg [1*9-1:0] data_shift_06; + +reg [1*9-1:0] data_shift_16; + +reg [1*9-1:0] data_shift_26; + +reg [1*9-1:0] data_shift_36; + +reg [1*9-1:0] data_shift_46; + +reg [1*9-1:0] data_shift_56; + +reg [1*9-1:0] data_shift_66; + +reg [1*9-1:0] data_shift_76; + +reg [1*9-1:0] data_shift_86; + +reg [1*9-1:0] data_shift_07; + +reg [1*9-1:0] data_shift_17; + +reg [1*9-1:0] data_shift_27; + +reg [1*9-1:0] data_shift_37; + +reg [1*9-1:0] data_shift_47; + +reg [1*9-1:0] data_shift_57; + +reg [1*9-1:0] data_shift_67; + +reg [1*9-1:0] data_shift_77; + +reg [1*9-1:0] data_shift_87; + +reg [1*9-1:0] data_1stC_00; + +reg [1*9-1:0] data_1stC_10; + +reg [1*9-1:0] data_1stC_20; + +reg [1*9-1:0] data_1stC_30; + +reg [1*9-1:0] data_1stC_40; + +reg [1*9-1:0] data_1stC_01; + +reg [1*9-1:0] data_1stC_11; + +reg [1*9-1:0] data_1stC_21; + +reg [1*9-1:0] data_1stC_31; + +reg [1*9-1:0] data_1stC_41; + +reg [1*9-1:0] data_1stC_02; + +reg [1*9-1:0] data_1stC_12; + +reg [1*9-1:0] data_1stC_22; + +reg [1*9-1:0] data_1stC_32; + +reg [1*9-1:0] data_1stC_42; + +reg [1*9-1:0] data_1stC_03; + +reg [1*9-1:0] data_1stC_13; + +reg [1*9-1:0] data_1stC_23; + +reg [1*9-1:0] data_1stC_33; + +reg [1*9-1:0] data_1stC_43; + +reg [1*9-1:0] data_1stC_04; + +reg [1*9-1:0] data_1stC_14; + +reg [1*9-1:0] data_1stC_24; + +reg [1*9-1:0] data_1stC_34; + +reg [1*9-1:0] data_1stC_44; + +reg [1*9-1:0] data_1stC_05; + +reg [1*9-1:0] data_1stC_15; + +reg [1*9-1:0] data_1stC_25; + +reg [1*9-1:0] data_1stC_35; + +reg [1*9-1:0] data_1stC_45; + +reg [1*9-1:0] data_1stC_06; + +reg [1*9-1:0] data_1stC_16; + +reg [1*9-1:0] data_1stC_26; + +reg [1*9-1:0] data_1stC_36; + +reg [1*9-1:0] data_1stC_46; + +reg [1*9-1:0] data_1stC_07; + +reg [1*9-1:0] data_1stC_17; + +reg [1*9-1:0] data_1stC_27; + +reg [1*9-1:0] data_1stC_37; + +reg [1*9-1:0] data_1stC_47; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg data_shift_valid; +reg hold_here; +reg hold_here_dly; +reg [3:0] is_pos_w_dly; +reg [3:0] is_pos_w_dly2; +reg last_c_align; +reg last_c_dly1; +reg last_h_align; +reg last_h_dly1; +reg last_w_align; +reg last_w_dly1; +reg [3:0] last_width; +reg less2more_dly; +reg less2more_dly2; +reg more2less_dly; +reg [1*(8 +1)+15-1:0] nvdla_cdp_rdma2dp_pd; +reg nvdla_cdp_rdma2dp_valid; +reg [2:0] pos_c_align; +reg [2:0] pos_c_dly1; +reg [3:0] pos_w_align; +reg [3:0] pos_w_dly1; +reg [2:0] stat_cur; +reg [2:0] stat_cur_dly; +reg [2:0] stat_cur_dly2; +reg [2:0] stat_nex; +reg [3:0] width_align; +reg [3:0] width_cur_1; +reg [3:0] width_cur_2; +reg [3:0] width_dly1; +reg [3:0] width_pre; +reg [3:0] width_pre_cnt; +reg [3:0] width_pre_cnt_dly; +reg [3:0] width_pre_dly; +reg [3:0] width_pre_dly2; +wire FIRST_C_bf_end; +wire FIRST_C_end; +wire buf_dat_rdy; +wire [buf2sq_dp_bw-1:0] buffer_pd; +wire buffer_valid; +wire cube_done; +wire data_shift_load; +wire data_shift_load_all; +wire data_shift_ready; +wire dp_b_sync; +wire [1*(8 +1)-1:0] dp_data; +wire dp_last_c; +wire dp_last_h; +wire dp_last_w; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire [3:0] dp_width; +wire is_b_sync; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire [2:0] is_pos_c; +wire [3:0] is_pos_w; +wire [3:0] is_width; +wire [3:0] is_width_f; +wire l2m_1stC_vld; +wire less2more; +wire load_din; +wire load_din_full; +wire more2less; +wire nvdla_cdp_rdma2dp_ready; +wire rdma2dp_ready_normal; +wire rdma2dp_valid_rebuild; +wire vld; +wire [3:0] width_cur; +reg [1:0] hold_4ele_cnt; +wire is_hold_4ele_done; +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +// pipe +assign cdp_rdma2dp_ready = nvdla_cdp_rdma2dp_ready || (~nvdla_cdp_rdma2dp_valid); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + nvdla_cdp_rdma2dp_valid <= 1'b0; + else if(cdp_rdma2dp_valid) + nvdla_cdp_rdma2dp_valid <= 1'b1; + else if(nvdla_cdp_rdma2dp_ready) + nvdla_cdp_rdma2dp_valid <= 1'b0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + nvdla_cdp_rdma2dp_pd <= {1*(8 +1)+15{1'b0}}; + else if(cdp_rdma2dp_valid & cdp_rdma2dp_ready) + nvdla_cdp_rdma2dp_pd <= cdp_rdma2dp_pd; +end +///////////////////////////////////////////////////////////// +//============== +// INPUT UNPACK: from RDMA +//============== +assign dp_data[1*(8 +1)-1:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)-1:0]; +assign dp_pos_w[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+3:1*(8 +1)]; +assign dp_width[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+7:1*(8 +1)+4]; +assign dp_pos_c[2:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+10:1*(8 +1)+8]; +assign dp_b_sync = nvdla_cdp_rdma2dp_pd[1*(8 +1)+11]; +assign dp_last_w = nvdla_cdp_rdma2dp_pd[1*(8 +1)+12]; +assign dp_last_h = nvdla_cdp_rdma2dp_pd[1*(8 +1)+13]; +assign dp_last_c = nvdla_cdp_rdma2dp_pd[1*(8 +1)+14]; +assign is_pos_w = dp_pos_w; +assign is_width_f = dp_width[3:0]; +assign is_width[3:0] = is_width_f - 1'b1; +assign is_pos_c = dp_pos_c; +assign is_b_sync = dp_b_sync ; +assign is_last_w = dp_last_w ; +assign is_last_h = dp_last_h ; +assign is_last_c = dp_last_c ; +/////////////////////////////////////////////////// +assign nvdla_cdp_rdma2dp_ready = rdma2dp_ready_normal & (~hold_here); +assign rdma2dp_valid_rebuild = nvdla_cdp_rdma2dp_valid | hold_here; +assign vld = rdma2dp_valid_rebuild; +assign load_din = vld & nvdla_cdp_rdma2dp_ready; +assign load_din_full = rdma2dp_valid_rebuild & rdma2dp_ready_normal; +/////////////////////////////////////////////////// +wire is_4ele_here; +wire is_posc_end; +//: my $atmm = 8; +//: my $tp = 1; +//: my $m = int(4/$tp+0.99) -1; +//: if($tp < 4){ +//: print "assign is_4ele_here = (is_pos_c == ${m}); \n"; +//: } else { +//: print "assign is_4ele_here = (is_pos_c == 0); \n"; +//: } +//: my $k = int($atmm/$tp) -1; +//: print "assign is_posc_end = (is_pos_c == ${k}); \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign is_4ele_here = (is_pos_c == 3); +assign is_posc_end = (is_pos_c == 7); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +localparam WAIT = 3'b000; +localparam NORMAL_C = 3'b001; +localparam FIRST_C = 3'b010; +localparam SECOND_C = 3'b011; +localparam CUBE_END = 3'b100; +always @(*) begin + stat_nex = stat_cur; + NormalC2CubeEnd = 0; + begin + casez (stat_cur) + WAIT: begin + if (is_b_sync & is_4ele_here & load_din) begin +//: my $atmm = 8; +//: if($atmm == 4) { +//: print qq( +//: if(is_last_c & is_last_h & is_last_w) begin +//: NormalC2CubeEnd = 1; +//: stat_nex = CUBE_END; +//: end else if(is_last_c & (~(is_last_h & is_last_w))) begin +//: stat_nex = FIRST_C; +//: end else begin +//: stat_nex = NORMAL_C; +//: end +//: ); +//: } elsif($atmm > 4) { +//: print qq( +//: stat_nex = NORMAL_C; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +stat_nex = NORMAL_C; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end + NORMAL_C: begin + if ((is_b_sync & is_posc_end & is_last_c & is_last_h & is_last_w & load_din)) begin + NormalC2CubeEnd = 1; + stat_nex = CUBE_END; + end else if ((is_b_sync & is_posc_end & is_last_c) & (~(is_last_h & is_last_w) & load_din)) begin + stat_nex = FIRST_C; + end + end + FIRST_C: begin + if ((is_4ele_here & (is_pos_w == is_width) & (~more2less) & load_din) + || (more2less & (width_pre_cnt == width_pre) & is_hold_4ele_done & hold_here & rdma2dp_ready_normal)) begin +//: my $atmm = 8; +//: if($atmm == 4) { +//: print qq( +//: if(is_last_c & is_last_h & is_last_w) +//: stat_nex = CUBE_END; +//: else if(is_posc_end) +//: stat_nex = FIRST_C; +//: else +//: stat_nex = SECOND_C; +//: ); +//: } elsif($atmm > 4) { +//: print qq( +//: stat_nex = SECOND_C; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +stat_nex = SECOND_C; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end + SECOND_C: begin + if (is_b_sync & load_din) + stat_nex = NORMAL_C; + end + CUBE_END: begin + if (cube_done) + stat_nex = WAIT; + end + default: begin + stat_nex = WAIT; + end + endcase + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur <= WAIT; + end else begin + stat_cur <= stat_nex; + end +end +///////////////////////////////////////// +assign rdma2dp_ready_normal = (~data_shift_valid) | data_shift_ready; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_shift_valid <= 1'b0; + end else begin + if(vld) + data_shift_valid <= 1'b1; + else if(data_shift_ready) + data_shift_valid <= 1'b0; + end +end +assign data_shift_ready =(~buf_dat_vld | buf_dat_rdy); +assign data_shift_load_all = data_shift_ready & data_shift_valid; +assign data_shift_load = data_shift_load_all & ((~hold_here_dly) | (stat_cur_dly == CUBE_END)); +///////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: foreach my $k (0..8) { +//: print qq( +//: data_shift_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//: foreach my $m (0..7) { +//: foreach my $k (0..3) { +//: print qq( +//: data_1stC_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +data_shift_00 <= {1*9{1'd0}}; + +data_shift_10 <= {1*9{1'd0}}; + +data_shift_20 <= {1*9{1'd0}}; + +data_shift_30 <= {1*9{1'd0}}; + +data_shift_40 <= {1*9{1'd0}}; + +data_shift_50 <= {1*9{1'd0}}; + +data_shift_60 <= {1*9{1'd0}}; + +data_shift_70 <= {1*9{1'd0}}; + +data_shift_80 <= {1*9{1'd0}}; + +data_shift_01 <= {1*9{1'd0}}; + +data_shift_11 <= {1*9{1'd0}}; + +data_shift_21 <= {1*9{1'd0}}; + +data_shift_31 <= {1*9{1'd0}}; + +data_shift_41 <= {1*9{1'd0}}; + +data_shift_51 <= {1*9{1'd0}}; + +data_shift_61 <= {1*9{1'd0}}; + +data_shift_71 <= {1*9{1'd0}}; + +data_shift_81 <= {1*9{1'd0}}; + +data_shift_02 <= {1*9{1'd0}}; + +data_shift_12 <= {1*9{1'd0}}; + +data_shift_22 <= {1*9{1'd0}}; + +data_shift_32 <= {1*9{1'd0}}; + +data_shift_42 <= {1*9{1'd0}}; + +data_shift_52 <= {1*9{1'd0}}; + +data_shift_62 <= {1*9{1'd0}}; + +data_shift_72 <= {1*9{1'd0}}; + +data_shift_82 <= {1*9{1'd0}}; + +data_shift_03 <= {1*9{1'd0}}; + +data_shift_13 <= {1*9{1'd0}}; + +data_shift_23 <= {1*9{1'd0}}; + +data_shift_33 <= {1*9{1'd0}}; + +data_shift_43 <= {1*9{1'd0}}; + +data_shift_53 <= {1*9{1'd0}}; + +data_shift_63 <= {1*9{1'd0}}; + +data_shift_73 <= {1*9{1'd0}}; + +data_shift_83 <= {1*9{1'd0}}; + +data_shift_04 <= {1*9{1'd0}}; + +data_shift_14 <= {1*9{1'd0}}; + +data_shift_24 <= {1*9{1'd0}}; + +data_shift_34 <= {1*9{1'd0}}; + +data_shift_44 <= {1*9{1'd0}}; + +data_shift_54 <= {1*9{1'd0}}; + +data_shift_64 <= {1*9{1'd0}}; + +data_shift_74 <= {1*9{1'd0}}; + +data_shift_84 <= {1*9{1'd0}}; + +data_shift_05 <= {1*9{1'd0}}; + +data_shift_15 <= {1*9{1'd0}}; + +data_shift_25 <= {1*9{1'd0}}; + +data_shift_35 <= {1*9{1'd0}}; + +data_shift_45 <= {1*9{1'd0}}; + +data_shift_55 <= {1*9{1'd0}}; + +data_shift_65 <= {1*9{1'd0}}; + +data_shift_75 <= {1*9{1'd0}}; + +data_shift_85 <= {1*9{1'd0}}; + +data_shift_06 <= {1*9{1'd0}}; + +data_shift_16 <= {1*9{1'd0}}; + +data_shift_26 <= {1*9{1'd0}}; + +data_shift_36 <= {1*9{1'd0}}; + +data_shift_46 <= {1*9{1'd0}}; + +data_shift_56 <= {1*9{1'd0}}; + +data_shift_66 <= {1*9{1'd0}}; + +data_shift_76 <= {1*9{1'd0}}; + +data_shift_86 <= {1*9{1'd0}}; + +data_shift_07 <= {1*9{1'd0}}; + +data_shift_17 <= {1*9{1'd0}}; + +data_shift_27 <= {1*9{1'd0}}; + +data_shift_37 <= {1*9{1'd0}}; + +data_shift_47 <= {1*9{1'd0}}; + +data_shift_57 <= {1*9{1'd0}}; + +data_shift_67 <= {1*9{1'd0}}; + +data_shift_77 <= {1*9{1'd0}}; + +data_shift_87 <= {1*9{1'd0}}; + +data_1stC_00 <= {1*9{1'd0}}; + +data_1stC_10 <= {1*9{1'd0}}; + +data_1stC_20 <= {1*9{1'd0}}; + +data_1stC_30 <= {1*9{1'd0}}; + +data_1stC_01 <= {1*9{1'd0}}; + +data_1stC_11 <= {1*9{1'd0}}; + +data_1stC_21 <= {1*9{1'd0}}; + +data_1stC_31 <= {1*9{1'd0}}; + +data_1stC_02 <= {1*9{1'd0}}; + +data_1stC_12 <= {1*9{1'd0}}; + +data_1stC_22 <= {1*9{1'd0}}; + +data_1stC_32 <= {1*9{1'd0}}; + +data_1stC_03 <= {1*9{1'd0}}; + +data_1stC_13 <= {1*9{1'd0}}; + +data_1stC_23 <= {1*9{1'd0}}; + +data_1stC_33 <= {1*9{1'd0}}; + +data_1stC_04 <= {1*9{1'd0}}; + +data_1stC_14 <= {1*9{1'd0}}; + +data_1stC_24 <= {1*9{1'd0}}; + +data_1stC_34 <= {1*9{1'd0}}; + +data_1stC_05 <= {1*9{1'd0}}; + +data_1stC_15 <= {1*9{1'd0}}; + +data_1stC_25 <= {1*9{1'd0}}; + +data_1stC_35 <= {1*9{1'd0}}; + +data_1stC_06 <= {1*9{1'd0}}; + +data_1stC_16 <= {1*9{1'd0}}; + +data_1stC_26 <= {1*9{1'd0}}; + +data_1stC_36 <= {1*9{1'd0}}; + +data_1stC_07 <= {1*9{1'd0}}; + +data_1stC_17 <= {1*9{1'd0}}; + +data_1stC_27 <= {1*9{1'd0}}; + +data_1stC_37 <= {1*9{1'd0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + case(stat_cur) + WAIT: begin + if(load_din) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w==4'd${m}) begin +//: data_shift_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: end +//: ); +//: } +//: foreach my $k (0..4) { +//: my $m = $k + 4; +//: foreach my $j (0..7) { +//: print qq( +//: data_shift_${m}${j} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(is_pos_w==4'd0) begin +data_shift_00 <= dp_data[1*9-1:0]; +data_shift_10 <= data_shift_00; +data_shift_20 <= data_shift_10; +data_shift_30 <= data_shift_20; +end + +if(is_pos_w==4'd1) begin +data_shift_01 <= dp_data[1*9-1:0]; +data_shift_11 <= data_shift_01; +data_shift_21 <= data_shift_11; +data_shift_31 <= data_shift_21; +end + +if(is_pos_w==4'd2) begin +data_shift_02 <= dp_data[1*9-1:0]; +data_shift_12 <= data_shift_02; +data_shift_22 <= data_shift_12; +data_shift_32 <= data_shift_22; +end + +if(is_pos_w==4'd3) begin +data_shift_03 <= dp_data[1*9-1:0]; +data_shift_13 <= data_shift_03; +data_shift_23 <= data_shift_13; +data_shift_33 <= data_shift_23; +end + +if(is_pos_w==4'd4) begin +data_shift_04 <= dp_data[1*9-1:0]; +data_shift_14 <= data_shift_04; +data_shift_24 <= data_shift_14; +data_shift_34 <= data_shift_24; +end + +if(is_pos_w==4'd5) begin +data_shift_05 <= dp_data[1*9-1:0]; +data_shift_15 <= data_shift_05; +data_shift_25 <= data_shift_15; +data_shift_35 <= data_shift_25; +end + +if(is_pos_w==4'd6) begin +data_shift_06 <= dp_data[1*9-1:0]; +data_shift_16 <= data_shift_06; +data_shift_26 <= data_shift_16; +data_shift_36 <= data_shift_26; +end + +if(is_pos_w==4'd7) begin +data_shift_07 <= dp_data[1*9-1:0]; +data_shift_17 <= data_shift_07; +data_shift_27 <= data_shift_17; +data_shift_37 <= data_shift_27; +end + +data_shift_40 <= {1*9{1'd0}}; + +data_shift_41 <= {1*9{1'd0}}; + +data_shift_42 <= {1*9{1'd0}}; + +data_shift_43 <= {1*9{1'd0}}; + +data_shift_44 <= {1*9{1'd0}}; + +data_shift_45 <= {1*9{1'd0}}; + +data_shift_46 <= {1*9{1'd0}}; + +data_shift_47 <= {1*9{1'd0}}; + +data_shift_50 <= {1*9{1'd0}}; + +data_shift_51 <= {1*9{1'd0}}; + +data_shift_52 <= {1*9{1'd0}}; + +data_shift_53 <= {1*9{1'd0}}; + +data_shift_54 <= {1*9{1'd0}}; + +data_shift_55 <= {1*9{1'd0}}; + +data_shift_56 <= {1*9{1'd0}}; + +data_shift_57 <= {1*9{1'd0}}; + +data_shift_60 <= {1*9{1'd0}}; + +data_shift_61 <= {1*9{1'd0}}; + +data_shift_62 <= {1*9{1'd0}}; + +data_shift_63 <= {1*9{1'd0}}; + +data_shift_64 <= {1*9{1'd0}}; + +data_shift_65 <= {1*9{1'd0}}; + +data_shift_66 <= {1*9{1'd0}}; + +data_shift_67 <= {1*9{1'd0}}; + +data_shift_70 <= {1*9{1'd0}}; + +data_shift_71 <= {1*9{1'd0}}; + +data_shift_72 <= {1*9{1'd0}}; + +data_shift_73 <= {1*9{1'd0}}; + +data_shift_74 <= {1*9{1'd0}}; + +data_shift_75 <= {1*9{1'd0}}; + +data_shift_76 <= {1*9{1'd0}}; + +data_shift_77 <= {1*9{1'd0}}; + +data_shift_80 <= {1*9{1'd0}}; + +data_shift_81 <= {1*9{1'd0}}; + +data_shift_82 <= {1*9{1'd0}}; + +data_shift_83 <= {1*9{1'd0}}; + +data_shift_84 <= {1*9{1'd0}}; + +data_shift_85 <= {1*9{1'd0}}; + +data_shift_86 <= {1*9{1'd0}}; + +data_shift_87 <= {1*9{1'd0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end end + NORMAL_C: begin + if(load_din) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w==4'd${m}) begin +//: data_shift_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(is_pos_w==4'd0) begin +data_shift_00 <= dp_data[1*9-1:0]; +data_shift_10 <= data_shift_00; +data_shift_20 <= data_shift_10; +data_shift_30 <= data_shift_20; +data_shift_40 <= data_shift_30; +data_shift_50 <= data_shift_40; +data_shift_60 <= data_shift_50; +data_shift_70 <= data_shift_60; +data_shift_80 <= data_shift_70; +end + +if(is_pos_w==4'd1) begin +data_shift_01 <= dp_data[1*9-1:0]; +data_shift_11 <= data_shift_01; +data_shift_21 <= data_shift_11; +data_shift_31 <= data_shift_21; +data_shift_41 <= data_shift_31; +data_shift_51 <= data_shift_41; +data_shift_61 <= data_shift_51; +data_shift_71 <= data_shift_61; +data_shift_81 <= data_shift_71; +end + +if(is_pos_w==4'd2) begin +data_shift_02 <= dp_data[1*9-1:0]; +data_shift_12 <= data_shift_02; +data_shift_22 <= data_shift_12; +data_shift_32 <= data_shift_22; +data_shift_42 <= data_shift_32; +data_shift_52 <= data_shift_42; +data_shift_62 <= data_shift_52; +data_shift_72 <= data_shift_62; +data_shift_82 <= data_shift_72; +end + +if(is_pos_w==4'd3) begin +data_shift_03 <= dp_data[1*9-1:0]; +data_shift_13 <= data_shift_03; +data_shift_23 <= data_shift_13; +data_shift_33 <= data_shift_23; +data_shift_43 <= data_shift_33; +data_shift_53 <= data_shift_43; +data_shift_63 <= data_shift_53; +data_shift_73 <= data_shift_63; +data_shift_83 <= data_shift_73; +end + +if(is_pos_w==4'd4) begin +data_shift_04 <= dp_data[1*9-1:0]; +data_shift_14 <= data_shift_04; +data_shift_24 <= data_shift_14; +data_shift_34 <= data_shift_24; +data_shift_44 <= data_shift_34; +data_shift_54 <= data_shift_44; +data_shift_64 <= data_shift_54; +data_shift_74 <= data_shift_64; +data_shift_84 <= data_shift_74; +end + +if(is_pos_w==4'd5) begin +data_shift_05 <= dp_data[1*9-1:0]; +data_shift_15 <= data_shift_05; +data_shift_25 <= data_shift_15; +data_shift_35 <= data_shift_25; +data_shift_45 <= data_shift_35; +data_shift_55 <= data_shift_45; +data_shift_65 <= data_shift_55; +data_shift_75 <= data_shift_65; +data_shift_85 <= data_shift_75; +end + +if(is_pos_w==4'd6) begin +data_shift_06 <= dp_data[1*9-1:0]; +data_shift_16 <= data_shift_06; +data_shift_26 <= data_shift_16; +data_shift_36 <= data_shift_26; +data_shift_46 <= data_shift_36; +data_shift_56 <= data_shift_46; +data_shift_66 <= data_shift_56; +data_shift_76 <= data_shift_66; +data_shift_86 <= data_shift_76; +end + +if(is_pos_w==4'd7) begin +data_shift_07 <= dp_data[1*9-1:0]; +data_shift_17 <= data_shift_07; +data_shift_27 <= data_shift_17; +data_shift_37 <= data_shift_27; +data_shift_47 <= data_shift_37; +data_shift_57 <= data_shift_47; +data_shift_67 <= data_shift_57; +data_shift_77 <= data_shift_67; +data_shift_87 <= data_shift_77; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end end + FIRST_C: begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(hold_here & rdma2dp_ready_normal) begin +//: if(width_pre_cnt==4'd${m}) begin +//: data_shift_0${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: end else begin +//: if((is_pos_w==4'd${m}) & load_din) begin +//: data_1stC_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_1stC_1${m} <= data_1stC_0${m}; +//: data_1stC_2${m} <= data_1stC_1${m}; +//: data_1stC_3${m} <= data_1stC_2${m}; +//: data_shift_0${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd0) begin +data_shift_00 <= {1*9{1'd0}}; +data_shift_10 <= data_shift_00; +data_shift_20 <= data_shift_10; +data_shift_30 <= data_shift_20; +data_shift_40 <= data_shift_30; +data_shift_50 <= data_shift_40; +data_shift_60 <= data_shift_50; +data_shift_70 <= data_shift_60; +data_shift_80 <= data_shift_70; +end +end else begin +if((is_pos_w==4'd0) & load_din) begin +data_1stC_00 <= dp_data[1*9-1:0]; +data_1stC_10 <= data_1stC_00; +data_1stC_20 <= data_1stC_10; +data_1stC_30 <= data_1stC_20; +data_shift_00 <= {1*9{1'd0}}; +data_shift_10 <= data_shift_00; +data_shift_20 <= data_shift_10; +data_shift_30 <= data_shift_20; +data_shift_40 <= data_shift_30; +data_shift_50 <= data_shift_40; +data_shift_60 <= data_shift_50; +data_shift_70 <= data_shift_60; +data_shift_80 <= data_shift_70; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd1) begin +data_shift_01 <= {1*9{1'd0}}; +data_shift_11 <= data_shift_01; +data_shift_21 <= data_shift_11; +data_shift_31 <= data_shift_21; +data_shift_41 <= data_shift_31; +data_shift_51 <= data_shift_41; +data_shift_61 <= data_shift_51; +data_shift_71 <= data_shift_61; +data_shift_81 <= data_shift_71; +end +end else begin +if((is_pos_w==4'd1) & load_din) begin +data_1stC_01 <= dp_data[1*9-1:0]; +data_1stC_11 <= data_1stC_01; +data_1stC_21 <= data_1stC_11; +data_1stC_31 <= data_1stC_21; +data_shift_01 <= {1*9{1'd0}}; +data_shift_11 <= data_shift_01; +data_shift_21 <= data_shift_11; +data_shift_31 <= data_shift_21; +data_shift_41 <= data_shift_31; +data_shift_51 <= data_shift_41; +data_shift_61 <= data_shift_51; +data_shift_71 <= data_shift_61; +data_shift_81 <= data_shift_71; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd2) begin +data_shift_02 <= {1*9{1'd0}}; +data_shift_12 <= data_shift_02; +data_shift_22 <= data_shift_12; +data_shift_32 <= data_shift_22; +data_shift_42 <= data_shift_32; +data_shift_52 <= data_shift_42; +data_shift_62 <= data_shift_52; +data_shift_72 <= data_shift_62; +data_shift_82 <= data_shift_72; +end +end else begin +if((is_pos_w==4'd2) & load_din) begin +data_1stC_02 <= dp_data[1*9-1:0]; +data_1stC_12 <= data_1stC_02; +data_1stC_22 <= data_1stC_12; +data_1stC_32 <= data_1stC_22; +data_shift_02 <= {1*9{1'd0}}; +data_shift_12 <= data_shift_02; +data_shift_22 <= data_shift_12; +data_shift_32 <= data_shift_22; +data_shift_42 <= data_shift_32; +data_shift_52 <= data_shift_42; +data_shift_62 <= data_shift_52; +data_shift_72 <= data_shift_62; +data_shift_82 <= data_shift_72; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd3) begin +data_shift_03 <= {1*9{1'd0}}; +data_shift_13 <= data_shift_03; +data_shift_23 <= data_shift_13; +data_shift_33 <= data_shift_23; +data_shift_43 <= data_shift_33; +data_shift_53 <= data_shift_43; +data_shift_63 <= data_shift_53; +data_shift_73 <= data_shift_63; +data_shift_83 <= data_shift_73; +end +end else begin +if((is_pos_w==4'd3) & load_din) begin +data_1stC_03 <= dp_data[1*9-1:0]; +data_1stC_13 <= data_1stC_03; +data_1stC_23 <= data_1stC_13; +data_1stC_33 <= data_1stC_23; +data_shift_03 <= {1*9{1'd0}}; +data_shift_13 <= data_shift_03; +data_shift_23 <= data_shift_13; +data_shift_33 <= data_shift_23; +data_shift_43 <= data_shift_33; +data_shift_53 <= data_shift_43; +data_shift_63 <= data_shift_53; +data_shift_73 <= data_shift_63; +data_shift_83 <= data_shift_73; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd4) begin +data_shift_04 <= {1*9{1'd0}}; +data_shift_14 <= data_shift_04; +data_shift_24 <= data_shift_14; +data_shift_34 <= data_shift_24; +data_shift_44 <= data_shift_34; +data_shift_54 <= data_shift_44; +data_shift_64 <= data_shift_54; +data_shift_74 <= data_shift_64; +data_shift_84 <= data_shift_74; +end +end else begin +if((is_pos_w==4'd4) & load_din) begin +data_1stC_04 <= dp_data[1*9-1:0]; +data_1stC_14 <= data_1stC_04; +data_1stC_24 <= data_1stC_14; +data_1stC_34 <= data_1stC_24; +data_shift_04 <= {1*9{1'd0}}; +data_shift_14 <= data_shift_04; +data_shift_24 <= data_shift_14; +data_shift_34 <= data_shift_24; +data_shift_44 <= data_shift_34; +data_shift_54 <= data_shift_44; +data_shift_64 <= data_shift_54; +data_shift_74 <= data_shift_64; +data_shift_84 <= data_shift_74; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd5) begin +data_shift_05 <= {1*9{1'd0}}; +data_shift_15 <= data_shift_05; +data_shift_25 <= data_shift_15; +data_shift_35 <= data_shift_25; +data_shift_45 <= data_shift_35; +data_shift_55 <= data_shift_45; +data_shift_65 <= data_shift_55; +data_shift_75 <= data_shift_65; +data_shift_85 <= data_shift_75; +end +end else begin +if((is_pos_w==4'd5) & load_din) begin +data_1stC_05 <= dp_data[1*9-1:0]; +data_1stC_15 <= data_1stC_05; +data_1stC_25 <= data_1stC_15; +data_1stC_35 <= data_1stC_25; +data_shift_05 <= {1*9{1'd0}}; +data_shift_15 <= data_shift_05; +data_shift_25 <= data_shift_15; +data_shift_35 <= data_shift_25; +data_shift_45 <= data_shift_35; +data_shift_55 <= data_shift_45; +data_shift_65 <= data_shift_55; +data_shift_75 <= data_shift_65; +data_shift_85 <= data_shift_75; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd6) begin +data_shift_06 <= {1*9{1'd0}}; +data_shift_16 <= data_shift_06; +data_shift_26 <= data_shift_16; +data_shift_36 <= data_shift_26; +data_shift_46 <= data_shift_36; +data_shift_56 <= data_shift_46; +data_shift_66 <= data_shift_56; +data_shift_76 <= data_shift_66; +data_shift_86 <= data_shift_76; +end +end else begin +if((is_pos_w==4'd6) & load_din) begin +data_1stC_06 <= dp_data[1*9-1:0]; +data_1stC_16 <= data_1stC_06; +data_1stC_26 <= data_1stC_16; +data_1stC_36 <= data_1stC_26; +data_shift_06 <= {1*9{1'd0}}; +data_shift_16 <= data_shift_06; +data_shift_26 <= data_shift_16; +data_shift_36 <= data_shift_26; +data_shift_46 <= data_shift_36; +data_shift_56 <= data_shift_46; +data_shift_66 <= data_shift_56; +data_shift_76 <= data_shift_66; +data_shift_86 <= data_shift_76; +end +end + +if(hold_here & rdma2dp_ready_normal) begin +if(width_pre_cnt==4'd7) begin +data_shift_07 <= {1*9{1'd0}}; +data_shift_17 <= data_shift_07; +data_shift_27 <= data_shift_17; +data_shift_37 <= data_shift_27; +data_shift_47 <= data_shift_37; +data_shift_57 <= data_shift_47; +data_shift_67 <= data_shift_57; +data_shift_77 <= data_shift_67; +data_shift_87 <= data_shift_77; +end +end else begin +if((is_pos_w==4'd7) & load_din) begin +data_1stC_07 <= dp_data[1*9-1:0]; +data_1stC_17 <= data_1stC_07; +data_1stC_27 <= data_1stC_17; +data_1stC_37 <= data_1stC_27; +data_shift_07 <= {1*9{1'd0}}; +data_shift_17 <= data_shift_07; +data_shift_27 <= data_shift_17; +data_shift_37 <= data_shift_27; +data_shift_47 <= data_shift_37; +data_shift_57 <= data_shift_47; +data_shift_67 <= data_shift_57; +data_shift_77 <= data_shift_67; +data_shift_87 <= data_shift_77; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + SECOND_C: begin + if(load_din) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w==4'd${m}) begin +//: data_shift_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_shift_1${m} <= data_1stC_0${m}; +//: data_shift_2${m} <= data_1stC_1${m}; +//: data_shift_3${m} <= data_1stC_2${m}; +//: data_shift_4${m} <= data_1stC_3${m}; +//: data_shift_5${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_6${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_7${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_8${m} <= {${tp}*${bpe}{1'd0}}; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(is_pos_w==4'd0) begin +data_shift_00 <= dp_data[1*9-1:0]; +data_shift_10 <= data_1stC_00; +data_shift_20 <= data_1stC_10; +data_shift_30 <= data_1stC_20; +data_shift_40 <= data_1stC_30; +data_shift_50 <= {1*9{1'd0}}; +data_shift_60 <= {1*9{1'd0}}; +data_shift_70 <= {1*9{1'd0}}; +data_shift_80 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd1) begin +data_shift_01 <= dp_data[1*9-1:0]; +data_shift_11 <= data_1stC_01; +data_shift_21 <= data_1stC_11; +data_shift_31 <= data_1stC_21; +data_shift_41 <= data_1stC_31; +data_shift_51 <= {1*9{1'd0}}; +data_shift_61 <= {1*9{1'd0}}; +data_shift_71 <= {1*9{1'd0}}; +data_shift_81 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd2) begin +data_shift_02 <= dp_data[1*9-1:0]; +data_shift_12 <= data_1stC_02; +data_shift_22 <= data_1stC_12; +data_shift_32 <= data_1stC_22; +data_shift_42 <= data_1stC_32; +data_shift_52 <= {1*9{1'd0}}; +data_shift_62 <= {1*9{1'd0}}; +data_shift_72 <= {1*9{1'd0}}; +data_shift_82 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd3) begin +data_shift_03 <= dp_data[1*9-1:0]; +data_shift_13 <= data_1stC_03; +data_shift_23 <= data_1stC_13; +data_shift_33 <= data_1stC_23; +data_shift_43 <= data_1stC_33; +data_shift_53 <= {1*9{1'd0}}; +data_shift_63 <= {1*9{1'd0}}; +data_shift_73 <= {1*9{1'd0}}; +data_shift_83 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd4) begin +data_shift_04 <= dp_data[1*9-1:0]; +data_shift_14 <= data_1stC_04; +data_shift_24 <= data_1stC_14; +data_shift_34 <= data_1stC_24; +data_shift_44 <= data_1stC_34; +data_shift_54 <= {1*9{1'd0}}; +data_shift_64 <= {1*9{1'd0}}; +data_shift_74 <= {1*9{1'd0}}; +data_shift_84 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd5) begin +data_shift_05 <= dp_data[1*9-1:0]; +data_shift_15 <= data_1stC_05; +data_shift_25 <= data_1stC_15; +data_shift_35 <= data_1stC_25; +data_shift_45 <= data_1stC_35; +data_shift_55 <= {1*9{1'd0}}; +data_shift_65 <= {1*9{1'd0}}; +data_shift_75 <= {1*9{1'd0}}; +data_shift_85 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd6) begin +data_shift_06 <= dp_data[1*9-1:0]; +data_shift_16 <= data_1stC_06; +data_shift_26 <= data_1stC_16; +data_shift_36 <= data_1stC_26; +data_shift_46 <= data_1stC_36; +data_shift_56 <= {1*9{1'd0}}; +data_shift_66 <= {1*9{1'd0}}; +data_shift_76 <= {1*9{1'd0}}; +data_shift_86 <= {1*9{1'd0}}; +end + +if(is_pos_w==4'd7) begin +data_shift_07 <= dp_data[1*9-1:0]; +data_shift_17 <= data_1stC_07; +data_shift_27 <= data_1stC_17; +data_shift_37 <= data_1stC_27; +data_shift_47 <= data_1stC_37; +data_shift_57 <= {1*9{1'd0}}; +data_shift_67 <= {1*9{1'd0}}; +data_shift_77 <= {1*9{1'd0}}; +data_shift_87 <= {1*9{1'd0}}; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end end + CUBE_END: begin + if(rdma2dp_ready_normal) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(cube_end_width_cnt==4'd${m}) begin +//: data_shift_0${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(cube_end_width_cnt==4'd0) begin +data_shift_00 <= {1*9{1'd0}}; +data_shift_10 <= data_shift_00; +data_shift_20 <= data_shift_10; +data_shift_30 <= data_shift_20; +data_shift_40 <= data_shift_30; +data_shift_50 <= data_shift_40; +data_shift_60 <= data_shift_50; +data_shift_70 <= data_shift_60; +data_shift_80 <= data_shift_70; +end + +if(cube_end_width_cnt==4'd1) begin +data_shift_01 <= {1*9{1'd0}}; +data_shift_11 <= data_shift_01; +data_shift_21 <= data_shift_11; +data_shift_31 <= data_shift_21; +data_shift_41 <= data_shift_31; +data_shift_51 <= data_shift_41; +data_shift_61 <= data_shift_51; +data_shift_71 <= data_shift_61; +data_shift_81 <= data_shift_71; +end + +if(cube_end_width_cnt==4'd2) begin +data_shift_02 <= {1*9{1'd0}}; +data_shift_12 <= data_shift_02; +data_shift_22 <= data_shift_12; +data_shift_32 <= data_shift_22; +data_shift_42 <= data_shift_32; +data_shift_52 <= data_shift_42; +data_shift_62 <= data_shift_52; +data_shift_72 <= data_shift_62; +data_shift_82 <= data_shift_72; +end + +if(cube_end_width_cnt==4'd3) begin +data_shift_03 <= {1*9{1'd0}}; +data_shift_13 <= data_shift_03; +data_shift_23 <= data_shift_13; +data_shift_33 <= data_shift_23; +data_shift_43 <= data_shift_33; +data_shift_53 <= data_shift_43; +data_shift_63 <= data_shift_53; +data_shift_73 <= data_shift_63; +data_shift_83 <= data_shift_73; +end + +if(cube_end_width_cnt==4'd4) begin +data_shift_04 <= {1*9{1'd0}}; +data_shift_14 <= data_shift_04; +data_shift_24 <= data_shift_14; +data_shift_34 <= data_shift_24; +data_shift_44 <= data_shift_34; +data_shift_54 <= data_shift_44; +data_shift_64 <= data_shift_54; +data_shift_74 <= data_shift_64; +data_shift_84 <= data_shift_74; +end + +if(cube_end_width_cnt==4'd5) begin +data_shift_05 <= {1*9{1'd0}}; +data_shift_15 <= data_shift_05; +data_shift_25 <= data_shift_15; +data_shift_35 <= data_shift_25; +data_shift_45 <= data_shift_35; +data_shift_55 <= data_shift_45; +data_shift_65 <= data_shift_55; +data_shift_75 <= data_shift_65; +data_shift_85 <= data_shift_75; +end + +if(cube_end_width_cnt==4'd6) begin +data_shift_06 <= {1*9{1'd0}}; +data_shift_16 <= data_shift_06; +data_shift_26 <= data_shift_16; +data_shift_36 <= data_shift_26; +data_shift_46 <= data_shift_36; +data_shift_56 <= data_shift_46; +data_shift_66 <= data_shift_56; +data_shift_76 <= data_shift_66; +data_shift_86 <= data_shift_76; +end + +if(cube_end_width_cnt==4'd7) begin +data_shift_07 <= {1*9{1'd0}}; +data_shift_17 <= data_shift_07; +data_shift_27 <= data_shift_17; +data_shift_37 <= data_shift_27; +data_shift_47 <= data_shift_37; +data_shift_57 <= data_shift_47; +data_shift_67 <= data_shift_57; +data_shift_77 <= data_shift_67; +data_shift_87 <= data_shift_77; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end end + default: begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: foreach my $k (0..8) { +//: print qq( +//: data_shift_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//: foreach my $m (0..7) { +//: foreach my $k (0..3) { +//: print qq( +//: data_1stC_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +data_shift_00 <= {1*9{1'd0}}; + +data_shift_10 <= {1*9{1'd0}}; + +data_shift_20 <= {1*9{1'd0}}; + +data_shift_30 <= {1*9{1'd0}}; + +data_shift_40 <= {1*9{1'd0}}; + +data_shift_50 <= {1*9{1'd0}}; + +data_shift_60 <= {1*9{1'd0}}; + +data_shift_70 <= {1*9{1'd0}}; + +data_shift_80 <= {1*9{1'd0}}; + +data_shift_01 <= {1*9{1'd0}}; + +data_shift_11 <= {1*9{1'd0}}; + +data_shift_21 <= {1*9{1'd0}}; + +data_shift_31 <= {1*9{1'd0}}; + +data_shift_41 <= {1*9{1'd0}}; + +data_shift_51 <= {1*9{1'd0}}; + +data_shift_61 <= {1*9{1'd0}}; + +data_shift_71 <= {1*9{1'd0}}; + +data_shift_81 <= {1*9{1'd0}}; + +data_shift_02 <= {1*9{1'd0}}; + +data_shift_12 <= {1*9{1'd0}}; + +data_shift_22 <= {1*9{1'd0}}; + +data_shift_32 <= {1*9{1'd0}}; + +data_shift_42 <= {1*9{1'd0}}; + +data_shift_52 <= {1*9{1'd0}}; + +data_shift_62 <= {1*9{1'd0}}; + +data_shift_72 <= {1*9{1'd0}}; + +data_shift_82 <= {1*9{1'd0}}; + +data_shift_03 <= {1*9{1'd0}}; + +data_shift_13 <= {1*9{1'd0}}; + +data_shift_23 <= {1*9{1'd0}}; + +data_shift_33 <= {1*9{1'd0}}; + +data_shift_43 <= {1*9{1'd0}}; + +data_shift_53 <= {1*9{1'd0}}; + +data_shift_63 <= {1*9{1'd0}}; + +data_shift_73 <= {1*9{1'd0}}; + +data_shift_83 <= {1*9{1'd0}}; + +data_shift_04 <= {1*9{1'd0}}; + +data_shift_14 <= {1*9{1'd0}}; + +data_shift_24 <= {1*9{1'd0}}; + +data_shift_34 <= {1*9{1'd0}}; + +data_shift_44 <= {1*9{1'd0}}; + +data_shift_54 <= {1*9{1'd0}}; + +data_shift_64 <= {1*9{1'd0}}; + +data_shift_74 <= {1*9{1'd0}}; + +data_shift_84 <= {1*9{1'd0}}; + +data_shift_05 <= {1*9{1'd0}}; + +data_shift_15 <= {1*9{1'd0}}; + +data_shift_25 <= {1*9{1'd0}}; + +data_shift_35 <= {1*9{1'd0}}; + +data_shift_45 <= {1*9{1'd0}}; + +data_shift_55 <= {1*9{1'd0}}; + +data_shift_65 <= {1*9{1'd0}}; + +data_shift_75 <= {1*9{1'd0}}; + +data_shift_85 <= {1*9{1'd0}}; + +data_shift_06 <= {1*9{1'd0}}; + +data_shift_16 <= {1*9{1'd0}}; + +data_shift_26 <= {1*9{1'd0}}; + +data_shift_36 <= {1*9{1'd0}}; + +data_shift_46 <= {1*9{1'd0}}; + +data_shift_56 <= {1*9{1'd0}}; + +data_shift_66 <= {1*9{1'd0}}; + +data_shift_76 <= {1*9{1'd0}}; + +data_shift_86 <= {1*9{1'd0}}; + +data_shift_07 <= {1*9{1'd0}}; + +data_shift_17 <= {1*9{1'd0}}; + +data_shift_27 <= {1*9{1'd0}}; + +data_shift_37 <= {1*9{1'd0}}; + +data_shift_47 <= {1*9{1'd0}}; + +data_shift_57 <= {1*9{1'd0}}; + +data_shift_67 <= {1*9{1'd0}}; + +data_shift_77 <= {1*9{1'd0}}; + +data_shift_87 <= {1*9{1'd0}}; + +data_1stC_00 <= {1*9{1'd0}}; + +data_1stC_10 <= {1*9{1'd0}}; + +data_1stC_20 <= {1*9{1'd0}}; + +data_1stC_30 <= {1*9{1'd0}}; + +data_1stC_01 <= {1*9{1'd0}}; + +data_1stC_11 <= {1*9{1'd0}}; + +data_1stC_21 <= {1*9{1'd0}}; + +data_1stC_31 <= {1*9{1'd0}}; + +data_1stC_02 <= {1*9{1'd0}}; + +data_1stC_12 <= {1*9{1'd0}}; + +data_1stC_22 <= {1*9{1'd0}}; + +data_1stC_32 <= {1*9{1'd0}}; + +data_1stC_03 <= {1*9{1'd0}}; + +data_1stC_13 <= {1*9{1'd0}}; + +data_1stC_23 <= {1*9{1'd0}}; + +data_1stC_33 <= {1*9{1'd0}}; + +data_1stC_04 <= {1*9{1'd0}}; + +data_1stC_14 <= {1*9{1'd0}}; + +data_1stC_24 <= {1*9{1'd0}}; + +data_1stC_34 <= {1*9{1'd0}}; + +data_1stC_05 <= {1*9{1'd0}}; + +data_1stC_15 <= {1*9{1'd0}}; + +data_1stC_25 <= {1*9{1'd0}}; + +data_1stC_35 <= {1*9{1'd0}}; + +data_1stC_06 <= {1*9{1'd0}}; + +data_1stC_16 <= {1*9{1'd0}}; + +data_1stC_26 <= {1*9{1'd0}}; + +data_1stC_36 <= {1*9{1'd0}}; + +data_1stC_07 <= {1*9{1'd0}}; + +data_1stC_17 <= {1*9{1'd0}}; + +data_1stC_27 <= {1*9{1'd0}}; + +data_1stC_37 <= {1*9{1'd0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + endcase + end + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre <= {4{1'b0}}; + end else begin +//if((stat_cur==NORMAL_C) & is_last_c & is_b_sync & (is_pos_c==3'd3) & load_din) + if((stat_cur==NORMAL_C) & is_last_c & is_b_sync & (is_pos_c==3'd7) & load_din) + width_pre <= is_width; + end +end +always @(*) begin +//if((stat_cur==FIRST_C) & (is_pos_w == 0)) + if((stat_cur==FIRST_C) & (is_pos_w == 0) & (is_pos_c == 0)) + width_cur_1 = is_width; + else + width_cur_1 = 0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cur_2 <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din) + width_cur_2 <= is_width; + end +end +assign width_cur = ((stat_cur==FIRST_C) & (is_pos_w == 0))? width_cur_1 : width_cur_2; +assign more2less = (stat_cur==FIRST_C) & (width_curwidth_pre); +assign l2m_1stC_vld = (stat_cur==FIRST_C) & less2more & (is_pos_w <= width_pre); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here <= 1'b0; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + hold_here <= 1; + else if((width_pre_cnt == width_pre) & rdma2dp_ready_normal) + hold_here <= 0; + end else if(NormalC2CubeEnd) + hold_here <= 1; + else if(cube_done) + hold_here <= 0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt[3:0] <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + width_pre_cnt[3:0] <= is_width+4'd1; + else if(hold_here & rdma2dp_ready_normal) + width_pre_cnt[3:0] <= width_pre_cnt+4'd1; + end else + width_pre_cnt[3:0] <= 4'd0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin + if (!nvdla_core_rstn) + hold_4ele_cnt <= {2{1'b0}}; + else if((stat_cur==FIRST_C) & more2less & hold_here & (width_pre_cnt == width_pre) & rdma2dp_ready_normal) begin + if(is_hold_4ele_done) + hold_4ele_cnt <= {2{1'b0}}; + else + hold_4ele_cnt <= hold_4ele_cnt + 1'b1; + end +end +//: my $atomm = 8; +//: my $tp = 1; +//: my $m = int(4/$tp+0.99) -1; +//: print "assign is_hold_4ele_done = (hold_4ele_cnt == ${m}); "; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign is_hold_4ele_done = (hold_4ele_cnt == 3); +//| eperl: generated_end (DO NOT EDIT ABOVE) +//the last block data need to be output in cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_width <= {4{1'b0}}; + end else begin + if(NormalC2CubeEnd & load_din) + last_width <= is_width; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_width_cnt <= {4{1'b0}}; + end else begin + if(stat_cur==CUBE_END) begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt == last_width) + cube_end_width_cnt <= 4'd0; + else + cube_end_width_cnt <= cube_end_width_cnt + 1; + end + end else + cube_end_width_cnt <= 4'd0; + end +end +reg [2:0] cube_end_c_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_c_cnt <= {3{1'b0}}; + end else begin + if(stat_cur==CUBE_END) begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt == last_width) + cube_end_c_cnt <= cube_end_c_cnt + 1; + end + end else + cube_end_c_cnt <= 3'd0; + end +end +//: my $tp = 1; +//: if( $tp >= 4 ) { +//: print " assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & rdma2dp_ready_normal; \n"; +//: } elsif( $tp == 2 ) { +//: print " assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & (cube_end_c_cnt == 3'd2) & rdma2dp_ready_normal; \n"; +//: } elsif( $tp == 1 ) { +//: print " assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & (cube_end_c_cnt == 3'd3) & rdma2dp_ready_normal; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & (cube_end_c_cnt == 3'd3) & rdma2dp_ready_normal; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & rdma2dp_ready_normal; +//1pipe delay for buffer data generation +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly <= {3{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + stat_cur_dly <= stat_cur; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + more2less_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + more2less_dly <= more2less; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + less2more_dly <= less2more; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + hold_here_dly <= hold_here; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly <= {4{1'b0}}; + end else begin + if((stat_cur == CUBE_END) & rdma2dp_ready_normal) + is_pos_w_dly <= cube_end_width_cnt; + else if(load_din) + is_pos_w_dly <= is_pos_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_cnt_dly <= width_pre_cnt; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_dly <= width_pre; + end + end +end +///////////////////////////// +//buffer data generation for output data +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_data <= {buf2sq_data_bw{1'b0}}; + end else begin + if(((stat_cur_dly==NORMAL_C) || (stat_cur_dly==SECOND_C) || (stat_cur_dly==CUBE_END)) & data_shift_load) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(is_pos_w_dly == 4'd0) +buffer_data <= {data_shift_00,data_shift_10,data_shift_20,data_shift_30, +data_shift_40,data_shift_50,data_shift_60,data_shift_70,data_shift_80}; + +if(is_pos_w_dly == 4'd1) +buffer_data <= {data_shift_01,data_shift_11,data_shift_21,data_shift_31, +data_shift_41,data_shift_51,data_shift_61,data_shift_71,data_shift_81}; + +if(is_pos_w_dly == 4'd2) +buffer_data <= {data_shift_02,data_shift_12,data_shift_22,data_shift_32, +data_shift_42,data_shift_52,data_shift_62,data_shift_72,data_shift_82}; + +if(is_pos_w_dly == 4'd3) +buffer_data <= {data_shift_03,data_shift_13,data_shift_23,data_shift_33, +data_shift_43,data_shift_53,data_shift_63,data_shift_73,data_shift_83}; + +if(is_pos_w_dly == 4'd4) +buffer_data <= {data_shift_04,data_shift_14,data_shift_24,data_shift_34, +data_shift_44,data_shift_54,data_shift_64,data_shift_74,data_shift_84}; + +if(is_pos_w_dly == 4'd5) +buffer_data <= {data_shift_05,data_shift_15,data_shift_25,data_shift_35, +data_shift_45,data_shift_55,data_shift_65,data_shift_75,data_shift_85}; + +if(is_pos_w_dly == 4'd6) +buffer_data <= {data_shift_06,data_shift_16,data_shift_26,data_shift_36, +data_shift_46,data_shift_56,data_shift_66,data_shift_76,data_shift_86}; + +if(is_pos_w_dly == 4'd7) +buffer_data <= {data_shift_07,data_shift_17,data_shift_27,data_shift_37, +data_shift_47,data_shift_57,data_shift_67,data_shift_77,data_shift_87}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else if(stat_cur_dly==FIRST_C) begin + if(more2less_dly) begin + if(data_shift_load) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(is_pos_w_dly == 4'd0) +buffer_data <= {data_shift_00,data_shift_10,data_shift_20,data_shift_30, +data_shift_40,data_shift_50,data_shift_60,data_shift_70,data_shift_80}; + +if(is_pos_w_dly == 4'd1) +buffer_data <= {data_shift_01,data_shift_11,data_shift_21,data_shift_31, +data_shift_41,data_shift_51,data_shift_61,data_shift_71,data_shift_81}; + +if(is_pos_w_dly == 4'd2) +buffer_data <= {data_shift_02,data_shift_12,data_shift_22,data_shift_32, +data_shift_42,data_shift_52,data_shift_62,data_shift_72,data_shift_82}; + +if(is_pos_w_dly == 4'd3) +buffer_data <= {data_shift_03,data_shift_13,data_shift_23,data_shift_33, +data_shift_43,data_shift_53,data_shift_63,data_shift_73,data_shift_83}; + +if(is_pos_w_dly == 4'd4) +buffer_data <= {data_shift_04,data_shift_14,data_shift_24,data_shift_34, +data_shift_44,data_shift_54,data_shift_64,data_shift_74,data_shift_84}; + +if(is_pos_w_dly == 4'd5) +buffer_data <= {data_shift_05,data_shift_15,data_shift_25,data_shift_35, +data_shift_45,data_shift_55,data_shift_65,data_shift_75,data_shift_85}; + +if(is_pos_w_dly == 4'd6) +buffer_data <= {data_shift_06,data_shift_16,data_shift_26,data_shift_36, +data_shift_46,data_shift_56,data_shift_66,data_shift_76,data_shift_86}; + +if(is_pos_w_dly == 4'd7) +buffer_data <= {data_shift_07,data_shift_17,data_shift_27,data_shift_37, +data_shift_47,data_shift_57,data_shift_67,data_shift_77,data_shift_87}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else if(hold_here_dly & data_shift_ready) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(width_pre_cnt_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(width_pre_cnt_dly == 4'd0) +buffer_data <= {data_shift_00,data_shift_10,data_shift_20,data_shift_30, +data_shift_40,data_shift_50,data_shift_60,data_shift_70,data_shift_80}; + +if(width_pre_cnt_dly == 4'd1) +buffer_data <= {data_shift_01,data_shift_11,data_shift_21,data_shift_31, +data_shift_41,data_shift_51,data_shift_61,data_shift_71,data_shift_81}; + +if(width_pre_cnt_dly == 4'd2) +buffer_data <= {data_shift_02,data_shift_12,data_shift_22,data_shift_32, +data_shift_42,data_shift_52,data_shift_62,data_shift_72,data_shift_82}; + +if(width_pre_cnt_dly == 4'd3) +buffer_data <= {data_shift_03,data_shift_13,data_shift_23,data_shift_33, +data_shift_43,data_shift_53,data_shift_63,data_shift_73,data_shift_83}; + +if(width_pre_cnt_dly == 4'd4) +buffer_data <= {data_shift_04,data_shift_14,data_shift_24,data_shift_34, +data_shift_44,data_shift_54,data_shift_64,data_shift_74,data_shift_84}; + +if(width_pre_cnt_dly == 4'd5) +buffer_data <= {data_shift_05,data_shift_15,data_shift_25,data_shift_35, +data_shift_45,data_shift_55,data_shift_65,data_shift_75,data_shift_85}; + +if(width_pre_cnt_dly == 4'd6) +buffer_data <= {data_shift_06,data_shift_16,data_shift_26,data_shift_36, +data_shift_46,data_shift_56,data_shift_66,data_shift_76,data_shift_86}; + +if(width_pre_cnt_dly == 4'd7) +buffer_data <= {data_shift_07,data_shift_17,data_shift_27,data_shift_37, +data_shift_47,data_shift_57,data_shift_67,data_shift_77,data_shift_87}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else begin + if((is_pos_w_dly<=width_pre_dly) & data_shift_load) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(is_pos_w_dly == 4'd0) +buffer_data <= {data_shift_00,data_shift_10,data_shift_20,data_shift_30, +data_shift_40,data_shift_50,data_shift_60,data_shift_70,data_shift_80}; + +if(is_pos_w_dly == 4'd1) +buffer_data <= {data_shift_01,data_shift_11,data_shift_21,data_shift_31, +data_shift_41,data_shift_51,data_shift_61,data_shift_71,data_shift_81}; + +if(is_pos_w_dly == 4'd2) +buffer_data <= {data_shift_02,data_shift_12,data_shift_22,data_shift_32, +data_shift_42,data_shift_52,data_shift_62,data_shift_72,data_shift_82}; + +if(is_pos_w_dly == 4'd3) +buffer_data <= {data_shift_03,data_shift_13,data_shift_23,data_shift_33, +data_shift_43,data_shift_53,data_shift_63,data_shift_73,data_shift_83}; + +if(is_pos_w_dly == 4'd4) +buffer_data <= {data_shift_04,data_shift_14,data_shift_24,data_shift_34, +data_shift_44,data_shift_54,data_shift_64,data_shift_74,data_shift_84}; + +if(is_pos_w_dly == 4'd5) +buffer_data <= {data_shift_05,data_shift_15,data_shift_25,data_shift_35, +data_shift_45,data_shift_55,data_shift_65,data_shift_75,data_shift_85}; + +if(is_pos_w_dly == 4'd6) +buffer_data <= {data_shift_06,data_shift_16,data_shift_26,data_shift_36, +data_shift_46,data_shift_56,data_shift_66,data_shift_76,data_shift_86}; + +if(is_pos_w_dly == 4'd7) +buffer_data <= {data_shift_07,data_shift_17,data_shift_27,data_shift_37, +data_shift_47,data_shift_57,data_shift_67,data_shift_77,data_shift_87}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else if(data_shift_load) begin + buffer_data <= {buf2sq_data_bw{1'b0}}; + end + end + end else if(data_shift_ready) begin + buffer_data <= {buf2sq_data_bw{1'b0}}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf_dat_vld <= 1'b0; + end else begin + if(data_shift_valid) + buf_dat_vld <= 1'b1 ; + else if(buf_dat_rdy) + buf_dat_vld <= 1'b0 ; + end +end +//assign buf_dat_rdy = buffer_ready; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly2 <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + stat_cur_dly2 <= stat_cur_dly; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly2 <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + less2more_dly2 <= less2more_dly; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + is_pos_w_dly2 <= is_pos_w_dly; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + width_pre_dly2 <= width_pre_dly; + end + end +end +always @(*) begin + if(((stat_cur_dly2==FIRST_C) & less2more_dly2 & (is_pos_w_dly2 > width_pre_dly2)) || (stat_cur_dly2==WAIT)) + buffer_data_vld = 1'b0; + else + buffer_data_vld = buf_dat_vld; +end +/////////////////////////////////////////////////////////////////////////////////////////// +//output data_info generation +/////////////////////////////////////////////////////////////////////////////////////////// +assign FIRST_C_end = ((stat_cur==FIRST_C) & (width_pre_cnt == width_pre) & more2less & rdma2dp_ready_normal); +assign FIRST_C_bf_end = ((stat_cur==FIRST_C) & (width_pre_cnt < width_pre) & more2less); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_align <= {4{1'b0}}; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + width_align <= is_width; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_w_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_w_align <= is_last_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_h_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_h_align <= is_last_h; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_c_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_c_align <= is_last_c; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_c_align <= {3{1'b0}}; + end else begin + if(FIRST_C_end) + pos_c_align <= 3'd0; + else if(is_b_sync & load_din & (~FIRST_C_bf_end)) + pos_c_align <= is_pos_c; + end +end +always @(*) begin + if(stat_cur==CUBE_END) + pos_w_align = cube_end_width_cnt; + else if(stat_cur==WAIT) + pos_w_align = 4'd0; + else if(stat_cur==FIRST_C) begin + if(more2less) begin + if(hold_here) + pos_w_align = width_pre_cnt; + else + pos_w_align = is_pos_w; + end else if(less2more) begin + if((is_pos_w <= width_pre)) + pos_w_align = is_pos_w; + else + pos_w_align = 4'd0; + end else + pos_w_align = is_pos_w; + end else + pos_w_align = is_pos_w; +end +always @(*) begin + if(stat_cur==CUBE_END) + b_sync_align = cube_done; + else if(stat_cur==WAIT) + b_sync_align = 1'b0; + else if(stat_cur==FIRST_C) begin + if(more2less) + b_sync_align = (width_pre_cnt == width_pre); + else if(less2more) + b_sync_align = (is_pos_w == width_pre) & load_din; + else + b_sync_align = (is_b_sync & load_din); + end + else + b_sync_align = (is_b_sync & load_din); +end +/////////////////// +//Two cycle delay +/////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_w_dly1 <= {4{1'b0}}; + width_dly1 <= {4{1'b0}}; + pos_c_dly1 <= {3{1'b0}}; + b_sync_dly1 <= 1'b0; + last_w_dly1 <= 1'b0; + last_h_dly1 <= 1'b0; + last_c_dly1 <= 1'b0; + end else begin + if((((stat_cur==NORMAL_C)||(stat_cur==SECOND_C)) & load_din) + || ((stat_cur==CUBE_END) & rdma2dp_ready_normal))begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(stat_cur==FIRST_C) begin + if(more2less & rdma2dp_ready_normal) begin + if(hold_here) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(less2more) begin + if(l2m_1stC_vld & load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(load_din)begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_w <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_w <= pos_w_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_width <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_width <= width_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_c <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_c <= pos_c_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_b_sync <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_b_sync <= b_sync_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_w <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_w <= last_w_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_h <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_h <= last_h_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_c <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_c <= last_c_dly1; + end + end +end +///////////////////////////////////////// +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}; +//: print qq( +//: assign buffer_pd[${k}-1:0] = buffer_data; +//: assign buffer_pd[${k}+3:${k}] = buffer_pos_w[3:0]; +//: assign buffer_pd[${k}+7:${k}+4] = buffer_width[3:0]; +//: assign buffer_pd[${k}+10:${k}+8] = buffer_pos_c[2:0]; +//: assign buffer_pd[${k}+11] = buffer_b_sync ; +//: assign buffer_pd[${k}+12] = buffer_last_w ; +//: assign buffer_pd[${k}+13] = buffer_last_h ; +//: assign buffer_pd[${k}+14] = buffer_last_c ; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign buffer_pd[81-1:0] = buffer_data; +assign buffer_pd[81+3:81] = buffer_pos_w[3:0]; +assign buffer_pd[81+7:81+4] = buffer_width[3:0]; +assign buffer_pd[81+10:81+8] = buffer_pos_c[2:0]; +assign buffer_pd[81+11] = buffer_b_sync ; +assign buffer_pd[81+12] = buffer_last_w ; +assign buffer_pd[81+13] = buffer_last_h ; +assign buffer_pd[81+14] = buffer_last_c ; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////////////////////// +assign buffer_valid = buffer_data_vld; +///////////////////////////////////////// +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: &eperl::pipe(" -is -wid $k -do normalz_buf_data -vo normalz_buf_data_pvld -ri normalz_buf_data_prdy -di buffer_pd -vi buffer_valid -ro buffer_ready "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg buffer_ready; +reg skid_flop_buffer_ready; +reg skid_flop_buffer_valid; +reg [96-1:0] skid_flop_buffer_pd; +reg pipe_skid_buffer_valid; +reg [96-1:0] pipe_skid_buffer_pd; +// Wire +wire skid_buffer_valid; +wire [96-1:0] skid_buffer_pd; +wire skid_buffer_ready; +wire pipe_skid_buffer_ready; +wire normalz_buf_data_pvld; +wire [96-1:0] normalz_buf_data; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_ready <= 1'b1; + skid_flop_buffer_ready <= 1'b1; + end else begin + buffer_ready <= skid_buffer_ready; + skid_flop_buffer_ready <= skid_buffer_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_buffer_valid <= 1'b0; + end else begin + if (skid_flop_buffer_ready) begin + skid_flop_buffer_valid <= buffer_valid; + end + end +end +assign skid_buffer_valid = (skid_flop_buffer_ready) ? buffer_valid : skid_flop_buffer_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_buffer_ready & buffer_valid) begin + skid_flop_buffer_pd[96-1:0] <= buffer_pd[96-1:0]; + end +end +assign skid_buffer_pd[96-1:0] = (skid_flop_buffer_ready) ? buffer_pd[96-1:0] : skid_flop_buffer_pd[96-1:0]; + + +// PIPE READY +assign skid_buffer_ready = pipe_skid_buffer_ready || !pipe_skid_buffer_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_buffer_valid <= 1'b0; + end else begin + if (skid_buffer_ready) begin + pipe_skid_buffer_valid <= skid_buffer_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_buffer_ready && skid_buffer_valid) begin + pipe_skid_buffer_pd[96-1:0] <= skid_buffer_pd[96-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_buffer_ready = normalz_buf_data_prdy; +assign normalz_buf_data_pvld = pipe_skid_buffer_valid; +assign normalz_buf_data = pipe_skid_buffer_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign buf_dat_rdy = buffer_ready; +///////////////////////////////////////// +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_bufin_widthchange__more2less__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & more2less; + endproperty +// Cover 0 : "load_din_full & more2less" + FUNCPOINT_CDP_bufin_widthchange__more2less__0_COV : cover property (CDP_bufin_widthchange__more2less__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_bufin_widthchange__less2more__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & less2more; + endproperty +// Cover 1 : "load_din_full & less2more" + FUNCPOINT_CDP_bufin_widthchange__less2more__1_COV : cover property (CDP_bufin_widthchange__less2more__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_DP_bufferin diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin_tp1.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin_tp1.v.vcp new file mode 100644 index 0000000..8931613 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin_tp1.v.vcp @@ -0,0 +1,1020 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_bufferin_tp1.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_bufferin_tp1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cdp_rdma2dp_pd + ,cdp_rdma2dp_valid + ,normalz_buf_data_prdy + ,cdp_rdma2dp_ready + ,normalz_buf_data + ,normalz_buf_data_pvld + ); +////////////////////////////////////////////// +parameter buf2sq_data_bw = (8 +1)*(1 +8); +parameter buf2sq_dp_bw = buf2sq_data_bw + 15; +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*(8 +1)+15-1:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +input normalz_buf_data_prdy; +output cdp_rdma2dp_ready; +output [buf2sq_dp_bw-1:0] normalz_buf_data; +output normalz_buf_data_pvld; +////////////////////////////////////////////// +reg NormalC2CubeEnd; +reg b_sync_align; +reg b_sync_dly1; +reg buf_dat_vld; +reg buffer_b_sync; +reg [buf2sq_data_bw-1:0] buffer_data; +reg buffer_data_vld; +reg buffer_last_c; +reg buffer_last_h; +reg buffer_last_w; +reg [2:0] buffer_pos_c; +reg [3:0] buffer_pos_w; +reg [3:0] buffer_width; +wire cdp_rdma2dp_ready; +reg [3:0] cube_end_width_cnt; +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: foreach my $k (0..8) { +//: print qq( +//: reg [${tp}*${bpe}-1:0] data_shift_${k}${m}; +//: ); +//: } +//: } +//: foreach my $m (0..7) { +//: foreach my $k (0..4) { +//: print qq( +//: reg [${tp}*${bpe}-1:0] data_1stC_${k}${m}; +//: ); +//: } +//: } +reg data_shift_valid; +reg hold_here; +reg hold_here_dly; +reg [3:0] is_pos_w_dly; +reg [3:0] is_pos_w_dly2; +reg last_c_align; +reg last_c_dly1; +reg last_h_align; +reg last_h_dly1; +reg last_w_align; +reg last_w_dly1; +reg [3:0] last_width; +reg less2more_dly; +reg less2more_dly2; +reg more2less_dly; +reg [1*(8 +1)+15-1:0] nvdla_cdp_rdma2dp_pd; +reg nvdla_cdp_rdma2dp_valid; +reg [2:0] pos_c_align; +reg [2:0] pos_c_dly1; +reg [3:0] pos_w_align; +reg [3:0] pos_w_dly1; +reg [2:0] stat_cur; +reg [2:0] stat_cur_dly; +reg [2:0] stat_cur_dly2; +reg [2:0] stat_nex; +reg [3:0] width_align; +reg [3:0] width_cur_1; +reg [3:0] width_cur_2; +reg [3:0] width_dly1; +reg [3:0] width_pre; +reg [3:0] width_pre_cnt; +reg [3:0] width_pre_cnt_dly; +reg [3:0] width_pre_dly; +reg [3:0] width_pre_dly2; +wire FIRST_C_bf_end; +wire FIRST_C_end; +wire buf_dat_rdy; +wire [buf2sq_dp_bw-1:0] buffer_pd; +wire buffer_valid; +wire cube_done; +wire data_shift_load; +wire data_shift_load_all; +wire data_shift_ready; +wire dp_b_sync; +wire [1*(8 +1)-1:0] dp_data; +wire dp_last_c; +wire dp_last_h; +wire dp_last_w; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire [3:0] dp_width; +wire is_b_sync; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire [2:0] is_pos_c; +wire [3:0] is_pos_w; +wire [3:0] is_width; +wire [3:0] is_width_f; +wire l2m_1stC_vld; +wire less2more; +wire load_din; +wire load_din_full; +wire more2less; +wire nvdla_cdp_rdma2dp_ready; +wire rdma2dp_ready_normal; +wire rdma2dp_valid_rebuild; +wire vld; +wire [3:0] width_cur; +reg [1:0] hold_4ele_cnt; +wire is_hold_4ele_done; +///////////////////////////////////////////////////////////// +// +///////////////////////////////////////////////////////////// +// pipe +assign cdp_rdma2dp_ready = nvdla_cdp_rdma2dp_ready || (~nvdla_cdp_rdma2dp_valid); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + nvdla_cdp_rdma2dp_valid <= 1'b0; + else if(cdp_rdma2dp_valid) + nvdla_cdp_rdma2dp_valid <= 1'b1; + else if(nvdla_cdp_rdma2dp_ready) + nvdla_cdp_rdma2dp_valid <= 1'b0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + nvdla_cdp_rdma2dp_pd <= {1*(8 +1)+15{1'b0}}; + else if(cdp_rdma2dp_valid & cdp_rdma2dp_ready) + nvdla_cdp_rdma2dp_pd <= cdp_rdma2dp_pd; +end +///////////////////////////////////////////////////////////// +//============== +// INPUT UNPACK: from RDMA +//============== +assign dp_data[1*(8 +1)-1:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)-1:0]; +assign dp_pos_w[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+3:1*(8 +1)]; +assign dp_width[3:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+7:1*(8 +1)+4]; +assign dp_pos_c[2:0] = nvdla_cdp_rdma2dp_pd[1*(8 +1)+10:1*(8 +1)+8]; +assign dp_b_sync = nvdla_cdp_rdma2dp_pd[1*(8 +1)+11]; +assign dp_last_w = nvdla_cdp_rdma2dp_pd[1*(8 +1)+12]; +assign dp_last_h = nvdla_cdp_rdma2dp_pd[1*(8 +1)+13]; +assign dp_last_c = nvdla_cdp_rdma2dp_pd[1*(8 +1)+14]; +assign is_pos_w = dp_pos_w; +assign is_width_f = dp_width[3:0]; +assign is_width[3:0] = is_width_f - 1'b1; +assign is_pos_c = dp_pos_c; +assign is_b_sync = dp_b_sync ; +assign is_last_w = dp_last_w ; +assign is_last_h = dp_last_h ; +assign is_last_c = dp_last_c ; +/////////////////////////////////////////////////// +assign nvdla_cdp_rdma2dp_ready = rdma2dp_ready_normal & (~hold_here); +assign rdma2dp_valid_rebuild = nvdla_cdp_rdma2dp_valid | hold_here; +assign vld = rdma2dp_valid_rebuild; +assign load_din = vld & nvdla_cdp_rdma2dp_ready; +assign load_din_full = rdma2dp_valid_rebuild & rdma2dp_ready_normal; +/////////////////////////////////////////////////// +wire is_4ele_here; +wire is_posc_end; +//: my $atmm = 8; +//: my $tp = 1; +//: my $m = int(4/$tp+0.99) -1; +//: if($tp < 4){ +//: print "assign is_4ele_here = (is_pos_c == ${m}); \n"; +//: } else { +//: print "assign is_4ele_here = (is_pos_c == 0); \n"; +//: } +//: my $k = int($atmm/$tp) -1; +//: print "assign is_posc_end = (is_pos_c == ${k}); \n"; +localparam WAIT = 3'b000; +localparam NORMAL_C = 3'b001; +localparam FIRST_C = 3'b010; +localparam SECOND_C = 3'b011; +localparam CUBE_END = 3'b100; +always @(*) begin + stat_nex = stat_cur; + NormalC2CubeEnd = 0; + begin + casez (stat_cur) + WAIT: begin + if (is_b_sync & is_4ele_here & load_din) begin +//: my $atmm = 8; +//: if($atmm == 4) { +//: print qq( +//: if(is_last_c & is_last_h & is_last_w) begin +//: NormalC2CubeEnd = 1; +//: stat_nex = CUBE_END; +//: end else if(is_last_c & (~(is_last_h & is_last_w))) begin +//: stat_nex = FIRST_C; +//: end else begin +//: stat_nex = NORMAL_C; +//: end +//: ); +//: } elsif($atmm > 4) { +//: print qq( +//: stat_nex = NORMAL_C; +//: ); +//: } + end + end + NORMAL_C: begin + if ((is_b_sync & is_posc_end & is_last_c & is_last_h & is_last_w & load_din)) begin + NormalC2CubeEnd = 1; + stat_nex = CUBE_END; + end else if ((is_b_sync & is_posc_end & is_last_c) & (~(is_last_h & is_last_w) & load_din)) begin + stat_nex = FIRST_C; + end + end + FIRST_C: begin + if ((is_4ele_here & (is_pos_w == is_width) & (~more2less) & load_din) + || (more2less & (width_pre_cnt == width_pre) & is_hold_4ele_done & hold_here & rdma2dp_ready_normal)) begin +//: my $atmm = 8; +//: if($atmm == 4) { +//: print qq( +//: if(is_last_c & is_last_h & is_last_w) +//: stat_nex = CUBE_END; +//: else if(is_posc_end) +//: stat_nex = FIRST_C; +//: else +//: stat_nex = SECOND_C; +//: ); +//: } elsif($atmm > 4) { +//: print qq( +//: stat_nex = SECOND_C; +//: ); +//: } + end + end + SECOND_C: begin + if (is_b_sync & load_din) + stat_nex = NORMAL_C; + end + CUBE_END: begin + if (cube_done) + stat_nex = WAIT; + end + default: begin + stat_nex = WAIT; + end + endcase + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur <= WAIT; + end else begin + stat_cur <= stat_nex; + end +end +///////////////////////////////////////// +assign rdma2dp_ready_normal = (~data_shift_valid) | data_shift_ready; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_shift_valid <= 1'b0; + end else begin + if(vld) + data_shift_valid <= 1'b1; + else if(data_shift_ready) + data_shift_valid <= 1'b0; + end +end +assign data_shift_ready =(~buf_dat_vld | buf_dat_rdy); +assign data_shift_load_all = data_shift_ready & data_shift_valid; +assign data_shift_load = data_shift_load_all & ((~hold_here_dly) | (stat_cur_dly == CUBE_END)); +///////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: foreach my $k (0..8) { +//: print qq( +//: data_shift_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//: foreach my $m (0..7) { +//: foreach my $k (0..3) { +//: print qq( +//: data_1stC_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } + end else begin + case(stat_cur) + WAIT: begin + if(load_din) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w==4'd${m}) begin +//: data_shift_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: end +//: ); +//: } +//: foreach my $k (0..4) { +//: my $m = $k + 4; +//: foreach my $j (0..7) { +//: print qq( +//: data_shift_${m}${j} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } + end end + NORMAL_C: begin + if(load_din) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w==4'd${m}) begin +//: data_shift_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: ); +//: } + end end + FIRST_C: begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(hold_here & rdma2dp_ready_normal) begin +//: if(width_pre_cnt==4'd${m}) begin +//: data_shift_0${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: end else begin +//: if((is_pos_w==4'd${m}) & load_din) begin +//: data_1stC_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_1stC_1${m} <= data_1stC_0${m}; +//: data_1stC_2${m} <= data_1stC_1${m}; +//: data_1stC_3${m} <= data_1stC_2${m}; +//: data_shift_0${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: end +//: ); +//: } + end + SECOND_C: begin + if(load_din) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w==4'd${m}) begin +//: data_shift_0${m} <= dp_data[${tp}*${bpe}-1:0]; +//: data_shift_1${m} <= data_1stC_0${m}; +//: data_shift_2${m} <= data_1stC_1${m}; +//: data_shift_3${m} <= data_1stC_2${m}; +//: data_shift_4${m} <= data_1stC_3${m}; +//: data_shift_5${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_6${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_7${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_8${m} <= {${tp}*${bpe}{1'd0}}; +//: end +//: ); +//: } + end end + CUBE_END: begin + if(rdma2dp_ready_normal) begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: print qq( +//: if(cube_end_width_cnt==4'd${m}) begin +//: data_shift_0${m} <= {${tp}*${bpe}{1'd0}}; +//: data_shift_1${m} <= data_shift_0${m}; +//: data_shift_2${m} <= data_shift_1${m}; +//: data_shift_3${m} <= data_shift_2${m}; +//: data_shift_4${m} <= data_shift_3${m}; +//: data_shift_5${m} <= data_shift_4${m}; +//: data_shift_6${m} <= data_shift_5${m}; +//: data_shift_7${m} <= data_shift_6${m}; +//: data_shift_8${m} <= data_shift_7${m}; +//: end +//: ); +//: } + end end + default: begin +//: my $tp = 1; +//: my $bpe = (8 +1); +//: foreach my $m (0..7) { +//: foreach my $k (0..8) { +//: print qq( +//: data_shift_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } +//: foreach my $m (0..7) { +//: foreach my $k (0..3) { +//: print qq( +//: data_1stC_${k}${m} <= {${tp}*${bpe}{1'd0}}; +//: ); +//: } +//: } + end + endcase + end + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre <= {4{1'b0}}; + end else begin +//if((stat_cur==NORMAL_C) & is_last_c & is_b_sync & (is_pos_c==3'd3) & load_din) + if((stat_cur==NORMAL_C) & is_last_c & is_b_sync & (is_pos_c==3'd7) & load_din) + width_pre <= is_width; + end +end +always @(*) begin +//if((stat_cur==FIRST_C) & (is_pos_w == 0)) + if((stat_cur==FIRST_C) & (is_pos_w == 0) & (is_pos_c == 0)) + width_cur_1 = is_width; + else + width_cur_1 = 0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cur_2 <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & (is_pos_w == 0) & load_din) + width_cur_2 <= is_width; + end +end +assign width_cur = ((stat_cur==FIRST_C) & (is_pos_w == 0))? width_cur_1 : width_cur_2; +assign more2less = (stat_cur==FIRST_C) & (width_curwidth_pre); +assign l2m_1stC_vld = (stat_cur==FIRST_C) & less2more & (is_pos_w <= width_pre); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here <= 1'b0; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + hold_here <= 1; + else if((width_pre_cnt == width_pre) & rdma2dp_ready_normal) + hold_here <= 0; + end else if(NormalC2CubeEnd) + hold_here <= 1; + else if(cube_done) + hold_here <= 0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt[3:0] <= {4{1'b0}}; + end else begin + if((stat_cur==FIRST_C) & more2less) begin + if((is_pos_w==is_width) & load_din) + width_pre_cnt[3:0] <= is_width+4'd1; + else if(hold_here & rdma2dp_ready_normal) + width_pre_cnt[3:0] <= width_pre_cnt+4'd1; + end else + width_pre_cnt[3:0] <= 4'd0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin + if (!nvdla_core_rstn) + hold_4ele_cnt <= {2{1'b0}}; + else if((stat_cur==FIRST_C) & more2less & hold_here & (width_pre_cnt == width_pre) & rdma2dp_ready_normal) begin + if(is_hold_4ele_done) + hold_4ele_cnt <= {2{1'b0}}; + else + hold_4ele_cnt <= hold_4ele_cnt + 1'b1; + end +end +//: my $atomm = 8; +//: my $tp = 1; +//: my $m = int(4/$tp+0.99) -1; +//: print "assign is_hold_4ele_done = (hold_4ele_cnt == ${m}); "; +//the last block data need to be output in cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_width <= {4{1'b0}}; + end else begin + if(NormalC2CubeEnd & load_din) + last_width <= is_width; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_width_cnt <= {4{1'b0}}; + end else begin + if(stat_cur==CUBE_END) begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt == last_width) + cube_end_width_cnt <= 4'd0; + else + cube_end_width_cnt <= cube_end_width_cnt + 1; + end + end else + cube_end_width_cnt <= 4'd0; + end +end +reg [2:0] cube_end_c_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_c_cnt <= {3{1'b0}}; + end else begin + if(stat_cur==CUBE_END) begin + if(rdma2dp_ready_normal) begin + if(cube_end_width_cnt == last_width) + cube_end_c_cnt <= cube_end_c_cnt + 1; + end + end else + cube_end_c_cnt <= 3'd0; + end +end +//: my $tp = 1; +//: if( $tp >= 4 ) { +//: print " assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & rdma2dp_ready_normal; \n"; +//: } elsif( $tp == 2 ) { +//: print " assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & (cube_end_c_cnt == 3'd2) & rdma2dp_ready_normal; \n"; +//: } elsif( $tp == 1 ) { +//: print " assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & (cube_end_c_cnt == 3'd3) & rdma2dp_ready_normal; \n"; +//: } +//assign cube_done = (stat_cur==CUBE_END) & (cube_end_width_cnt == last_width) & rdma2dp_ready_normal; +//1pipe delay for buffer data generation +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly <= {3{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + stat_cur_dly <= stat_cur; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + more2less_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + more2less_dly <= more2less; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + less2more_dly <= less2more; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + hold_here_dly <= 1'b0; + end else begin + if ((load_din_full) == 1'b1) begin + hold_here_dly <= hold_here; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly <= {4{1'b0}}; + end else begin + if((stat_cur == CUBE_END) & rdma2dp_ready_normal) + is_pos_w_dly <= cube_end_width_cnt; + else if(load_din) + is_pos_w_dly <= is_pos_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_cnt_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_cnt_dly <= width_pre_cnt; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly <= {4{1'b0}}; + end else begin + if ((load_din_full) == 1'b1) begin + width_pre_dly <= width_pre; + end + end +end +///////////////////////////// +//buffer data generation for output data +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_data <= {buf2sq_data_bw{1'b0}}; + end else begin + if(((stat_cur_dly==NORMAL_C) || (stat_cur_dly==SECOND_C) || (stat_cur_dly==CUBE_END)) & data_shift_load) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } + end else if(stat_cur_dly==FIRST_C) begin + if(more2less_dly) begin + if(data_shift_load) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } + end else if(hold_here_dly & data_shift_ready) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(width_pre_cnt_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } + end + end else begin + if((is_pos_w_dly<=width_pre_dly) & data_shift_load) begin +//: foreach my $m (0..7) { +//: print qq( +//: if(is_pos_w_dly == 4'd${m}) +//: buffer_data <= {data_shift_0${m},data_shift_1${m},data_shift_2${m},data_shift_3${m}, +//: data_shift_4${m},data_shift_5${m},data_shift_6${m},data_shift_7${m},data_shift_8${m}}; +//: ); +//: } + end else if(data_shift_load) begin + buffer_data <= {buf2sq_data_bw{1'b0}}; + end + end + end else if(data_shift_ready) begin + buffer_data <= {buf2sq_data_bw{1'b0}}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf_dat_vld <= 1'b0; + end else begin + if(data_shift_valid) + buf_dat_vld <= 1'b1 ; + else if(buf_dat_rdy) + buf_dat_vld <= 1'b0 ; + end +end +//assign buf_dat_rdy = buffer_ready; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stat_cur_dly2 <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + stat_cur_dly2 <= stat_cur_dly; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + less2more_dly2 <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + less2more_dly2 <= less2more_dly; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_pos_w_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + is_pos_w_dly2 <= is_pos_w_dly; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_pre_dly2 <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + width_pre_dly2 <= width_pre_dly; + end + end +end +always @(*) begin + if(((stat_cur_dly2==FIRST_C) & less2more_dly2 & (is_pos_w_dly2 > width_pre_dly2)) || (stat_cur_dly2==WAIT)) + buffer_data_vld = 1'b0; + else + buffer_data_vld = buf_dat_vld; +end +/////////////////////////////////////////////////////////////////////////////////////////// +//output data_info generation +/////////////////////////////////////////////////////////////////////////////////////////// +assign FIRST_C_end = ((stat_cur==FIRST_C) & (width_pre_cnt == width_pre) & more2less & rdma2dp_ready_normal); +assign FIRST_C_bf_end = ((stat_cur==FIRST_C) & (width_pre_cnt < width_pre) & more2less); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_align <= {4{1'b0}}; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + width_align <= is_width; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_w_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_w_align <= is_last_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_h_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_h_align <= is_last_h; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_c_align <= 1'b0; + end else begin + if (((is_b_sync & load_din & (~FIRST_C_bf_end)) | FIRST_C_end) == 1'b1) begin + last_c_align <= is_last_c; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_c_align <= {3{1'b0}}; + end else begin + if(FIRST_C_end) + pos_c_align <= 3'd0; + else if(is_b_sync & load_din & (~FIRST_C_bf_end)) + pos_c_align <= is_pos_c; + end +end +always @(*) begin + if(stat_cur==CUBE_END) + pos_w_align = cube_end_width_cnt; + else if(stat_cur==WAIT) + pos_w_align = 4'd0; + else if(stat_cur==FIRST_C) begin + if(more2less) begin + if(hold_here) + pos_w_align = width_pre_cnt; + else + pos_w_align = is_pos_w; + end else if(less2more) begin + if((is_pos_w <= width_pre)) + pos_w_align = is_pos_w; + else + pos_w_align = 4'd0; + end else + pos_w_align = is_pos_w; + end else + pos_w_align = is_pos_w; +end +always @(*) begin + if(stat_cur==CUBE_END) + b_sync_align = cube_done; + else if(stat_cur==WAIT) + b_sync_align = 1'b0; + else if(stat_cur==FIRST_C) begin + if(more2less) + b_sync_align = (width_pre_cnt == width_pre); + else if(less2more) + b_sync_align = (is_pos_w == width_pre) & load_din; + else + b_sync_align = (is_b_sync & load_din); + end + else + b_sync_align = (is_b_sync & load_din); +end +/////////////////// +//Two cycle delay +/////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_w_dly1 <= {4{1'b0}}; + width_dly1 <= {4{1'b0}}; + pos_c_dly1 <= {3{1'b0}}; + b_sync_dly1 <= 1'b0; + last_w_dly1 <= 1'b0; + last_h_dly1 <= 1'b0; + last_c_dly1 <= 1'b0; + end else begin + if((((stat_cur==NORMAL_C)||(stat_cur==SECOND_C)) & load_din) + || ((stat_cur==CUBE_END) & rdma2dp_ready_normal))begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(stat_cur==FIRST_C) begin + if(more2less & rdma2dp_ready_normal) begin + if(hold_here) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end else if(load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(less2more) begin + if(l2m_1stC_vld & load_din) begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end else if(load_din)begin + pos_w_dly1 <= pos_w_align; + width_dly1 <= width_align; + pos_c_dly1 <= pos_c_align; + b_sync_dly1 <= b_sync_align; + last_w_dly1 <= last_w_align; + last_h_dly1 <= last_h_align; + last_c_dly1 <= last_c_align; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_w <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_w <= pos_w_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_width <= {4{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_width <= width_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_pos_c <= {3{1'b0}}; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_pos_c <= pos_c_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_b_sync <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_b_sync <= b_sync_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_w <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_w <= last_w_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_h <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_h <= last_h_dly1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_last_c <= 1'b0; + end else begin + if ((data_shift_load_all) == 1'b1) begin + buffer_last_c <= last_c_dly1; + end + end +end +///////////////////////////////////////// +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}; +//: print qq( +//: assign buffer_pd[${k}-1:0] = buffer_data; +//: assign buffer_pd[${k}+3:${k}] = buffer_pos_w[3:0]; +//: assign buffer_pd[${k}+7:${k}+4] = buffer_width[3:0]; +//: assign buffer_pd[${k}+10:${k}+8] = buffer_pos_c[2:0]; +//: assign buffer_pd[${k}+11] = buffer_b_sync ; +//: assign buffer_pd[${k}+12] = buffer_last_w ; +//: assign buffer_pd[${k}+13] = buffer_last_h ; +//: assign buffer_pd[${k}+14] = buffer_last_c ; +//: ); +///////////////////////////////////////// +assign buffer_valid = buffer_data_vld; +///////////////////////////////////////// +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: &eperl::pipe(" -is -wid $k -do normalz_buf_data -vo normalz_buf_data_pvld -ri normalz_buf_data_prdy -di buffer_pd -vi buffer_valid -ro buffer_ready "); +assign buf_dat_rdy = buffer_ready; +///////////////////////////////////////// +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_bufin_widthchange__more2less__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & more2less; + endproperty +// Cover 0 : "load_din_full & more2less" + FUNCPOINT_CDP_bufin_widthchange__more2less__0_COV : cover property (CDP_bufin_widthchange__more2less__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_bufin_widthchange__less2more__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + load_din_full & less2more; + endproperty +// Cover 1 : "load_din_full & less2more" + FUNCPOINT_CDP_bufin_widthchange__less2more__1_COV : cover property (CDP_bufin_widthchange__less2more__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_DP_bufferin diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v new file mode 100644 index 0000000..3f258a8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v @@ -0,0 +1,786 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_cvtin.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_cvtin ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp_rdma2dp_pd //|< i + ,cdp_rdma2dp_valid //|< i + ,cvt2buf_prdy //|< i + ,cvt2sync_prdy //|< i + ,reg2dp_datin_offset //|< i + ,reg2dp_datin_scale //|< i + ,reg2dp_datin_shifter //|< i + ,cdp_rdma2dp_ready //|> o + ,cvt2buf_pd //|> o + ,cvt2buf_pvld //|> o + ,cvt2sync_pd //|> o + ,cvt2sync_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*8 +22:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +output cdp_rdma2dp_ready; +input [15:0] reg2dp_datin_offset;// need fix to bw, 8bits at int8 mode +input [15:0] reg2dp_datin_scale; +input [4:0] reg2dp_datin_shifter; +output [1*(8 +1)+14:0] cvt2buf_pd; +output cvt2buf_pvld; +input cvt2buf_prdy; +output [1*(8 +1)+14:0] cvt2sync_pd; +output cvt2sync_pvld; +input cvt2sync_prdy; +//////////////////////////////////////////////////////////////////////// +reg [15:0] reg2dp_datin_offset_use; +reg [15:0] reg2dp_datin_scale_use; +reg [4:0] reg2dp_datin_shifter_use; +//: my $k=1; +//: my $icvti=8; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print "wire [${icvti}-1:0] cdp_cvtin_input_pd_$m; \n"; +//: print "wire [${icvto}-1:0] cdp_cvtin_output_pd_$m;// bw \n"; +//: } +//: print "wire [${k}-1:0] cdp_cvtin_input_rdy; \n"; +//: print "wire [${k}-1:0] cdp_cvtin_input_vld; \n"; +//: print "wire [${k}-1:0] cdp_cvtin_output_rdy; \n"; +//: print "wire [${k}-1:0] cdp_cvtin_output_vld; \n"; +//: print "wire [${k}*${icvto}-1:0] cdp_cvtin_output_pd; \n"; +//: print "wire [${k}*${icvto}-1:0] icvt_out_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8-1:0] cdp_cvtin_input_pd_0; +wire [9-1:0] cdp_cvtin_output_pd_0;// bw +wire [1-1:0] cdp_cvtin_input_rdy; +wire [1-1:0] cdp_cvtin_input_vld; +wire [1-1:0] cdp_cvtin_output_rdy; +wire [1-1:0] cdp_cvtin_output_vld; +wire [1*9-1:0] cdp_cvtin_output_pd; +wire [1*9-1:0] icvt_out_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire cdp_cvtin_input_rdy_f; +wire cdp_cvtin_input_vld_f; +wire cdp_cvtin_output_rdy_f; +wire cdp_cvtin_output_vld_f; +wire cvtin_o_prdy; +wire cvtin_o_pvld; +wire [22:0] data_info_in_pd; +wire [22:0] data_info_in_pd_d0; +wire [22:0] data_info_in_pd_d1; +wire [22:0] data_info_in_pd_d2; +wire [22:0] data_info_in_pd_d3; +wire data_info_in_rdy; +wire data_info_in_rdy_d0; +wire data_info_in_rdy_d1; +wire data_info_in_rdy_d2; +wire data_info_in_rdy_d3; +wire data_info_in_vld; +wire data_info_in_vld_d0; +wire data_info_in_vld_d1; +wire data_info_in_vld_d2; +wire data_info_in_vld_d3; +wire [22:0] data_info_out_pd; +wire data_info_out_rdy; +wire data_info_out_vld; +wire [1 -1:0] invalid_flag; +////////////////////////////////// +assign cdp_rdma2dp_ready = cdp_cvtin_input_rdy_f & data_info_in_rdy; +//=============================================== +//pipeline delay for data info to sync with data path +//----------------------------------------------- +//data info valid in +assign data_info_in_vld = cdp_rdma2dp_valid & cdp_cvtin_input_rdy_f; +assign data_info_in_pd = cdp_rdma2dp_pd[1*8 +22:1*8]; +assign data_info_in_vld_d0 = data_info_in_vld; +assign data_info_in_rdy = data_info_in_rdy_d0; +assign data_info_in_pd_d0[22:0] = data_info_in_pd[22:0]; +NV_NVDLA_CDP_DP_CVTIN_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d0 (data_info_in_pd_d0[22:0]) //|< w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|< w + ,.data_info_in_vld_d0 (data_info_in_vld_d0) //|< w + ,.data_info_in_pd_d1 (data_info_in_pd_d1[22:0]) //|> w + ,.data_info_in_rdy_d0 (data_info_in_rdy_d0) //|> w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|> w + ); +NV_NVDLA_CDP_DP_CVTIN_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d1 (data_info_in_pd_d1[22:0]) //|< w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|< w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|< w + ,.data_info_in_pd_d2 (data_info_in_pd_d2[22:0]) //|> w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|> w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|> w + ); +NV_NVDLA_CDP_DP_CVTIN_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d2 (data_info_in_pd_d2[22:0]) //|< w + ,.data_info_in_rdy_d3 (data_info_in_rdy_d3) //|< w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|< w + ,.data_info_in_pd_d3 (data_info_in_pd_d3[22:0]) //|> w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|> w + ,.data_info_in_vld_d3 (data_info_in_vld_d3) //|> w + ); +assign data_info_out_vld = data_info_in_vld_d3; +assign data_info_in_rdy_d3 = data_info_out_rdy; +assign data_info_out_pd[22:0] = data_info_in_pd_d3[22:0]; +//=============================================== +//convertor process +//----------------------------------------------- +//cvtin valid input +assign cdp_cvtin_input_vld_f = cdp_rdma2dp_valid & data_info_in_rdy; +//cvtin ready input +assign cdp_cvtin_input_rdy_f = &cdp_cvtin_input_rdy[1 -1:0]; +//cvt sub-unit valid in +//: my $k=1; +//: if(${k}>1) { +//: foreach my $m (0..$k-1) { +//: print "assign cdp_cvtin_input_vld[${m}] = cdp_cvtin_input_vld_f "; +//: foreach my $n (0..$k-1) { +//: if($n != $m) { +//: print "& cdp_cvtin_input_rdy[$n] "; +//: } +//: } +//: print "; \n"; +//: } +//: } +//: elsif(${k}==1) { +//: print "assign cdp_cvtin_input_vld = cdp_cvtin_input_vld_f; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cdp_cvtin_input_vld = cdp_cvtin_input_vld_f; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//cvt sub-unit data in +//: my $k=1; +//: my $cdpbw=8; +//: foreach my $m (0..$k-1) { +//: print "assign cdp_cvtin_input_pd_${m} = cdp_rdma2dp_pd[${cdpbw}*${m}+${cdpbw}-1:${cdpbw}*${m}]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cdp_cvtin_input_pd_0 = cdp_rdma2dp_pd[8*0+8-1:8*0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datin_offset_use <= {16{1'b0}}; + end else begin + reg2dp_datin_offset_use <= reg2dp_datin_offset[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datin_scale_use <= {16{1'b0}}; + end else begin + reg2dp_datin_scale_use <= reg2dp_datin_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datin_shifter_use <= {5{1'b0}}; + end else begin + reg2dp_datin_shifter_use <= reg2dp_datin_shifter[4:0]; + end +end +//: my $k=1; +//: my $icvti=8; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: HLS_cdp_icvt u_HLS_cdp_icvt_$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.chn_data_in_rsc_z (cdp_cvtin_input_pd_${m}) +//: ,.chn_data_in_rsc_vz (cdp_cvtin_input_vld[$m]) +//: ,.chn_data_in_rsc_lz (cdp_cvtin_input_rdy[$m]) +//: ,.cfg_alu_in_rsc_z (reg2dp_datin_offset_use[7:0]) // need change bw +//: ,.cfg_mul_in_rsc_z (reg2dp_datin_scale_use[15:0]) +//: ,.cfg_truncate_rsc_z (reg2dp_datin_shifter_use[4:0]) +//: ,.chn_data_out_rsc_z (cdp_cvtin_output_pd_${m}) +//: ,.chn_data_out_rsc_vz (cdp_cvtin_output_rdy[$m]) +//: ,.chn_data_out_rsc_lz (cdp_cvtin_output_vld[$m]) +//: ); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +HLS_cdp_icvt u_HLS_cdp_icvt_0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.chn_data_in_rsc_z (cdp_cvtin_input_pd_0) +,.chn_data_in_rsc_vz (cdp_cvtin_input_vld[0]) +,.chn_data_in_rsc_lz (cdp_cvtin_input_rdy[0]) +,.cfg_alu_in_rsc_z (reg2dp_datin_offset_use[7:0]) // need change bw +,.cfg_mul_in_rsc_z (reg2dp_datin_scale_use[15:0]) +,.cfg_truncate_rsc_z (reg2dp_datin_shifter_use[4:0]) +,.chn_data_out_rsc_z (cdp_cvtin_output_pd_0) +,.chn_data_out_rsc_vz (cdp_cvtin_output_rdy[0]) +,.chn_data_out_rsc_lz (cdp_cvtin_output_vld[0]) +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//sub-unit output ready +//: my $k=1; +//: if(${k}>1) { +//: foreach my $m (0..$k-1) { +//: print "assign cdp_cvtin_output_rdy[${m}] = cdp_cvtin_output_rdy_f "; +//: foreach my $n (0..$k-1) { +//: if($n != $m) { +//: print "& cdp_cvtin_output_vld[$n] "; +//: } +//: } +//: print "; \n"; +//: } +//: } +//: elsif(${k}==1) { +//: print "assign cdp_cvtin_output_rdy = cdp_cvtin_output_rdy_f; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cdp_cvtin_output_rdy = cdp_cvtin_output_rdy_f; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//output valid +assign cdp_cvtin_output_vld_f = &cdp_cvtin_output_vld; +//output ready +assign cdp_cvtin_output_rdy_f = cvtin_o_prdy & data_info_out_vld; +//output data +//: my $k=1; +//: print "assign cdp_cvtin_output_pd = { "; +//: if(${k}>1) { +//: foreach my $n (0..$k-2) { +//: my $i=$k-$n -1; +//: print "cdp_cvtin_output_pd_${i}, "; +//: } +//: } +//: print "cdp_cvtin_output_pd_0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cdp_cvtin_output_pd = { cdp_cvtin_output_pd_0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//=============================================== +//data info output +//----------------------------------------------- +//data info output ready +assign data_info_out_rdy = cvtin_o_prdy & cdp_cvtin_output_vld_f; +//=============================================== +//convertor output +//----------------------------------------------- +assign cvtin_o_prdy = cvt2buf_prdy & cvt2sync_prdy; +assign cvtin_o_pvld = cdp_cvtin_output_vld_f & data_info_out_vld; +assign invalid_flag = data_info_out_pd[15+1 -1:15]; +//: my $k=1; +//: my $cdpbw=(8 +1); +//: print "assign icvt_out_pd = { "; +//: if(${k}>1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print "(invalid_flag[$i] ? {${cdpbw}{1'b0}} : cdp_cvtin_output_pd[${cdpbw}*${i}+${cdpbw}-1:${cdpbw}*${i}]), \n"; +//: } +//: } +//: print " ({${cdpbw}{(~invalid_flag[0])}} & cdp_cvtin_output_pd[${cdpbw}-1:0])}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign icvt_out_pd = { ({9{(~invalid_flag[0])}} & cdp_cvtin_output_pd[9-1:0])}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvt2buf_pd = {data_info_out_pd[14:0],icvt_out_pd}; +assign cvt2buf_pvld = cvtin_o_pvld & cvt2sync_prdy; +assign cvt2sync_pvld = cvtin_o_pvld & cvt2buf_prdy; +assign cvt2sync_pd = {data_info_out_pd[14:0],icvt_out_pd}; +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_cvtin +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d1[22:0] (data_info_in_vld_d1,data_info_in_rdy_d1) <= data_info_in_pd_d0[22:0] (data_info_in_vld_d0,data_info_in_rdy_d0) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTIN_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d0 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d0 + ,data_info_in_pd_d1 + ,data_info_in_rdy_d0 + ,data_info_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [22:0] data_info_in_pd_d0; +input data_info_in_rdy_d1; +input data_info_in_vld_d0; +output [22:0] data_info_in_pd_d1; +output data_info_in_rdy_d0; +output data_info_in_vld_d1; +reg [22:0] data_info_in_pd_d1; +reg data_info_in_rdy_d0; +reg data_info_in_vld_d1; +reg [22:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? data_info_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && data_info_in_vld_d0)? data_info_in_pd_d0[22:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + data_info_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or data_info_in_rdy_d1 + or p1_pipe_data + ) begin + data_info_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = data_info_in_rdy_d1; + data_info_in_pd_d1[22:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d1^data_info_in_rdy_d1^data_info_in_vld_d0^data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d0 && !data_info_in_rdy_d0), (data_info_in_vld_d0), (data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTIN_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d2[22:0] (data_info_in_vld_d2,data_info_in_rdy_d2) <= data_info_in_pd_d1[22:0] (data_info_in_vld_d1,data_info_in_rdy_d1) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTIN_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d1 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d1 + ,data_info_in_pd_d2 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [22:0] data_info_in_pd_d1; +input data_info_in_rdy_d2; +input data_info_in_vld_d1; +output [22:0] data_info_in_pd_d2; +output data_info_in_rdy_d1; +output data_info_in_vld_d2; +reg [22:0] data_info_in_pd_d2; +reg data_info_in_rdy_d1; +reg data_info_in_vld_d2; +reg [22:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? data_info_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && data_info_in_vld_d1)? data_info_in_pd_d1[22:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + data_info_in_rdy_d1 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or data_info_in_rdy_d2 + or p2_pipe_data + ) begin + data_info_in_vld_d2 = p2_pipe_valid; + p2_pipe_ready = data_info_in_rdy_d2; + data_info_in_pd_d2[22:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d2^data_info_in_rdy_d2^data_info_in_vld_d1^data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d1 && !data_info_in_rdy_d1), (data_info_in_vld_d1), (data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTIN_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d3[22:0] (data_info_in_vld_d3,data_info_in_rdy_d3) <= data_info_in_pd_d2[22:0] (data_info_in_vld_d2,data_info_in_rdy_d2) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTIN_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d2 + ,data_info_in_rdy_d3 + ,data_info_in_vld_d2 + ,data_info_in_pd_d3 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [22:0] data_info_in_pd_d2; +input data_info_in_rdy_d3; +input data_info_in_vld_d2; +output [22:0] data_info_in_pd_d3; +output data_info_in_rdy_d2; +output data_info_in_vld_d3; +reg [22:0] data_info_in_pd_d3; +reg data_info_in_rdy_d2; +reg data_info_in_vld_d3; +reg [22:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? data_info_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && data_info_in_vld_d2)? data_info_in_pd_d2[22:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + data_info_in_rdy_d2 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or data_info_in_rdy_d3 + or p3_pipe_data + ) begin + data_info_in_vld_d3 = p3_pipe_valid; + p3_pipe_ready = data_info_in_rdy_d3; + data_info_in_pd_d3[22:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d3^data_info_in_rdy_d3^data_info_in_vld_d2^data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d2 && !data_info_in_rdy_d2), (data_info_in_vld_d2), (data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTIN_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v.vcp new file mode 100644 index 0000000..894bfd4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v.vcp @@ -0,0 +1,738 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_cvtin.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_cvtin ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp_rdma2dp_pd //|< i + ,cdp_rdma2dp_valid //|< i + ,cvt2buf_prdy //|< i + ,cvt2sync_prdy //|< i + ,reg2dp_datin_offset //|< i + ,reg2dp_datin_scale //|< i + ,reg2dp_datin_shifter //|< i + ,cdp_rdma2dp_ready //|> o + ,cvt2buf_pd //|> o + ,cvt2buf_pvld //|> o + ,cvt2sync_pd //|> o + ,cvt2sync_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*8 +22:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +output cdp_rdma2dp_ready; +input [15:0] reg2dp_datin_offset;// need fix to bw, 8bits at int8 mode +input [15:0] reg2dp_datin_scale; +input [4:0] reg2dp_datin_shifter; +output [1*(8 +1)+14:0] cvt2buf_pd; +output cvt2buf_pvld; +input cvt2buf_prdy; +output [1*(8 +1)+14:0] cvt2sync_pd; +output cvt2sync_pvld; +input cvt2sync_prdy; +//////////////////////////////////////////////////////////////////////// +reg [15:0] reg2dp_datin_offset_use; +reg [15:0] reg2dp_datin_scale_use; +reg [4:0] reg2dp_datin_shifter_use; +//: my $k=1; +//: my $icvti=8; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print "wire [${icvti}-1:0] cdp_cvtin_input_pd_$m; \n"; +//: print "wire [${icvto}-1:0] cdp_cvtin_output_pd_$m;// bw \n"; +//: } +//: print "wire [${k}-1:0] cdp_cvtin_input_rdy; \n"; +//: print "wire [${k}-1:0] cdp_cvtin_input_vld; \n"; +//: print "wire [${k}-1:0] cdp_cvtin_output_rdy; \n"; +//: print "wire [${k}-1:0] cdp_cvtin_output_vld; \n"; +//: print "wire [${k}*${icvto}-1:0] cdp_cvtin_output_pd; \n"; +//: print "wire [${k}*${icvto}-1:0] icvt_out_pd; \n"; +wire cdp_cvtin_input_rdy_f; +wire cdp_cvtin_input_vld_f; +wire cdp_cvtin_output_rdy_f; +wire cdp_cvtin_output_vld_f; +wire cvtin_o_prdy; +wire cvtin_o_pvld; +wire [22:0] data_info_in_pd; +wire [22:0] data_info_in_pd_d0; +wire [22:0] data_info_in_pd_d1; +wire [22:0] data_info_in_pd_d2; +wire [22:0] data_info_in_pd_d3; +wire data_info_in_rdy; +wire data_info_in_rdy_d0; +wire data_info_in_rdy_d1; +wire data_info_in_rdy_d2; +wire data_info_in_rdy_d3; +wire data_info_in_vld; +wire data_info_in_vld_d0; +wire data_info_in_vld_d1; +wire data_info_in_vld_d2; +wire data_info_in_vld_d3; +wire [22:0] data_info_out_pd; +wire data_info_out_rdy; +wire data_info_out_vld; +wire [1 -1:0] invalid_flag; +////////////////////////////////// +assign cdp_rdma2dp_ready = cdp_cvtin_input_rdy_f & data_info_in_rdy; +//=============================================== +//pipeline delay for data info to sync with data path +//----------------------------------------------- +//data info valid in +assign data_info_in_vld = cdp_rdma2dp_valid & cdp_cvtin_input_rdy_f; +assign data_info_in_pd = cdp_rdma2dp_pd[1*8 +22:1*8]; +assign data_info_in_vld_d0 = data_info_in_vld; +assign data_info_in_rdy = data_info_in_rdy_d0; +assign data_info_in_pd_d0[22:0] = data_info_in_pd[22:0]; +NV_NVDLA_CDP_DP_CVTIN_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d0 (data_info_in_pd_d0[22:0]) //|< w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|< w + ,.data_info_in_vld_d0 (data_info_in_vld_d0) //|< w + ,.data_info_in_pd_d1 (data_info_in_pd_d1[22:0]) //|> w + ,.data_info_in_rdy_d0 (data_info_in_rdy_d0) //|> w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|> w + ); +NV_NVDLA_CDP_DP_CVTIN_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d1 (data_info_in_pd_d1[22:0]) //|< w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|< w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|< w + ,.data_info_in_pd_d2 (data_info_in_pd_d2[22:0]) //|> w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|> w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|> w + ); +NV_NVDLA_CDP_DP_CVTIN_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d2 (data_info_in_pd_d2[22:0]) //|< w + ,.data_info_in_rdy_d3 (data_info_in_rdy_d3) //|< w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|< w + ,.data_info_in_pd_d3 (data_info_in_pd_d3[22:0]) //|> w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|> w + ,.data_info_in_vld_d3 (data_info_in_vld_d3) //|> w + ); +assign data_info_out_vld = data_info_in_vld_d3; +assign data_info_in_rdy_d3 = data_info_out_rdy; +assign data_info_out_pd[22:0] = data_info_in_pd_d3[22:0]; +//=============================================== +//convertor process +//----------------------------------------------- +//cvtin valid input +assign cdp_cvtin_input_vld_f = cdp_rdma2dp_valid & data_info_in_rdy; +//cvtin ready input +assign cdp_cvtin_input_rdy_f = &cdp_cvtin_input_rdy[1 -1:0]; +//cvt sub-unit valid in +//: my $k=1; +//: if(${k}>1) { +//: foreach my $m (0..$k-1) { +//: print "assign cdp_cvtin_input_vld[${m}] = cdp_cvtin_input_vld_f "; +//: foreach my $n (0..$k-1) { +//: if($n != $m) { +//: print "& cdp_cvtin_input_rdy[$n] "; +//: } +//: } +//: print "; \n"; +//: } +//: } +//: elsif(${k}==1) { +//: print "assign cdp_cvtin_input_vld = cdp_cvtin_input_vld_f; \n"; +//: } +//cvt sub-unit data in +//: my $k=1; +//: my $cdpbw=8; +//: foreach my $m (0..$k-1) { +//: print "assign cdp_cvtin_input_pd_${m} = cdp_rdma2dp_pd[${cdpbw}*${m}+${cdpbw}-1:${cdpbw}*${m}]; \n"; +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datin_offset_use <= {16{1'b0}}; + end else begin + reg2dp_datin_offset_use <= reg2dp_datin_offset[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datin_scale_use <= {16{1'b0}}; + end else begin + reg2dp_datin_scale_use <= reg2dp_datin_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datin_shifter_use <= {5{1'b0}}; + end else begin + reg2dp_datin_shifter_use <= reg2dp_datin_shifter[4:0]; + end +end +//: my $k=1; +//: my $icvti=8; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: HLS_cdp_icvt u_HLS_cdp_icvt_$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.chn_data_in_rsc_z (cdp_cvtin_input_pd_${m}) +//: ,.chn_data_in_rsc_vz (cdp_cvtin_input_vld[$m]) +//: ,.chn_data_in_rsc_lz (cdp_cvtin_input_rdy[$m]) +//: ,.cfg_alu_in_rsc_z (reg2dp_datin_offset_use[7:0]) // need change bw +//: ,.cfg_mul_in_rsc_z (reg2dp_datin_scale_use[15:0]) +//: ,.cfg_truncate_rsc_z (reg2dp_datin_shifter_use[4:0]) +//: ,.chn_data_out_rsc_z (cdp_cvtin_output_pd_${m}) +//: ,.chn_data_out_rsc_vz (cdp_cvtin_output_rdy[$m]) +//: ,.chn_data_out_rsc_lz (cdp_cvtin_output_vld[$m]) +//: ); +//: ); +//: } +//sub-unit output ready +//: my $k=1; +//: if(${k}>1) { +//: foreach my $m (0..$k-1) { +//: print "assign cdp_cvtin_output_rdy[${m}] = cdp_cvtin_output_rdy_f "; +//: foreach my $n (0..$k-1) { +//: if($n != $m) { +//: print "& cdp_cvtin_output_vld[$n] "; +//: } +//: } +//: print "; \n"; +//: } +//: } +//: elsif(${k}==1) { +//: print "assign cdp_cvtin_output_rdy = cdp_cvtin_output_rdy_f; \n"; +//: } +//output valid +assign cdp_cvtin_output_vld_f = &cdp_cvtin_output_vld; +//output ready +assign cdp_cvtin_output_rdy_f = cvtin_o_prdy & data_info_out_vld; +//output data +//: my $k=1; +//: print "assign cdp_cvtin_output_pd = { "; +//: if(${k}>1) { +//: foreach my $n (0..$k-2) { +//: my $i=$k-$n -1; +//: print "cdp_cvtin_output_pd_${i}, "; +//: } +//: } +//: print "cdp_cvtin_output_pd_0}; \n"; +//=============================================== +//data info output +//----------------------------------------------- +//data info output ready +assign data_info_out_rdy = cvtin_o_prdy & cdp_cvtin_output_vld_f; +//=============================================== +//convertor output +//----------------------------------------------- +assign cvtin_o_prdy = cvt2buf_prdy & cvt2sync_prdy; +assign cvtin_o_pvld = cdp_cvtin_output_vld_f & data_info_out_vld; +assign invalid_flag = data_info_out_pd[15+1 -1:15]; +//: my $k=1; +//: my $cdpbw=(8 +1); +//: print "assign icvt_out_pd = { "; +//: if(${k}>1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print "(invalid_flag[$i] ? {${cdpbw}{1'b0}} : cdp_cvtin_output_pd[${cdpbw}*${i}+${cdpbw}-1:${cdpbw}*${i}]), \n"; +//: } +//: } +//: print " ({${cdpbw}{(~invalid_flag[0])}} & cdp_cvtin_output_pd[${cdpbw}-1:0])}; \n"; +assign cvt2buf_pd = {data_info_out_pd[14:0],icvt_out_pd}; +assign cvt2buf_pvld = cvtin_o_pvld & cvt2sync_prdy; +assign cvt2sync_pvld = cvtin_o_pvld & cvt2buf_prdy; +assign cvt2sync_pd = {data_info_out_pd[14:0],icvt_out_pd}; +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_cvtin +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d1[22:0] (data_info_in_vld_d1,data_info_in_rdy_d1) <= data_info_in_pd_d0[22:0] (data_info_in_vld_d0,data_info_in_rdy_d0) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTIN_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d0 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d0 + ,data_info_in_pd_d1 + ,data_info_in_rdy_d0 + ,data_info_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [22:0] data_info_in_pd_d0; +input data_info_in_rdy_d1; +input data_info_in_vld_d0; +output [22:0] data_info_in_pd_d1; +output data_info_in_rdy_d0; +output data_info_in_vld_d1; +reg [22:0] data_info_in_pd_d1; +reg data_info_in_rdy_d0; +reg data_info_in_vld_d1; +reg [22:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? data_info_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && data_info_in_vld_d0)? data_info_in_pd_d0[22:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + data_info_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or data_info_in_rdy_d1 + or p1_pipe_data + ) begin + data_info_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = data_info_in_rdy_d1; + data_info_in_pd_d1[22:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d1^data_info_in_rdy_d1^data_info_in_vld_d0^data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d0 && !data_info_in_rdy_d0), (data_info_in_vld_d0), (data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTIN_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d2[22:0] (data_info_in_vld_d2,data_info_in_rdy_d2) <= data_info_in_pd_d1[22:0] (data_info_in_vld_d1,data_info_in_rdy_d1) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTIN_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d1 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d1 + ,data_info_in_pd_d2 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [22:0] data_info_in_pd_d1; +input data_info_in_rdy_d2; +input data_info_in_vld_d1; +output [22:0] data_info_in_pd_d2; +output data_info_in_rdy_d1; +output data_info_in_vld_d2; +reg [22:0] data_info_in_pd_d2; +reg data_info_in_rdy_d1; +reg data_info_in_vld_d2; +reg [22:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? data_info_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && data_info_in_vld_d1)? data_info_in_pd_d1[22:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + data_info_in_rdy_d1 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or data_info_in_rdy_d2 + or p2_pipe_data + ) begin + data_info_in_vld_d2 = p2_pipe_valid; + p2_pipe_ready = data_info_in_rdy_d2; + data_info_in_pd_d2[22:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d2^data_info_in_rdy_d2^data_info_in_vld_d1^data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d1 && !data_info_in_rdy_d1), (data_info_in_vld_d1), (data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTIN_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d3[22:0] (data_info_in_vld_d3,data_info_in_rdy_d3) <= data_info_in_pd_d2[22:0] (data_info_in_vld_d2,data_info_in_rdy_d2) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTIN_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d2 + ,data_info_in_rdy_d3 + ,data_info_in_vld_d2 + ,data_info_in_pd_d3 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [22:0] data_info_in_pd_d2; +input data_info_in_rdy_d3; +input data_info_in_vld_d2; +output [22:0] data_info_in_pd_d3; +output data_info_in_rdy_d2; +output data_info_in_vld_d3; +reg [22:0] data_info_in_pd_d3; +reg data_info_in_rdy_d2; +reg data_info_in_vld_d3; +reg [22:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? data_info_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && data_info_in_vld_d2)? data_info_in_pd_d2[22:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + data_info_in_rdy_d2 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or data_info_in_rdy_d3 + or p3_pipe_data + ) begin + data_info_in_vld_d3 = p3_pipe_valid; + p3_pipe_ready = data_info_in_rdy_d3; + data_info_in_pd_d3[22:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d3^data_info_in_rdy_d3^data_info_in_vld_d2^data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d2 && !data_info_in_rdy_d2), (data_info_in_vld_d2), (data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTIN_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v new file mode 100644 index 0000000..069e254 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v @@ -0,0 +1,960 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_cvtout.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_cvtout ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvtout_prdy //|< i + ,mul2ocvt_pd //|< i + ,mul2ocvt_pvld //|< i + ,reg2dp_datout_offset //|< i + ,reg2dp_datout_scale //|< i + ,reg2dp_datout_shifter //|< i + ,sync2ocvt_pd //|< i + ,sync2ocvt_pvld //|< i + ,cvtout_pd //|> o + ,cvtout_pvld //|> o + ,mul2ocvt_prdy //|> o + ,sync2ocvt_prdy //|> o + ); +/////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input cvtout_prdy; +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: print "input [${k}*${ocvti}-1:0] mul2ocvt_pd; \n"; +//: print "output [${k}*${ocvto}+14:0] cvtout_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [1*25-1:0] mul2ocvt_pd; +output [1*8+14:0] cvtout_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input mul2ocvt_pvld; +input [31:0] reg2dp_datout_offset; +input [15:0] reg2dp_datout_scale; +input [5:0] reg2dp_datout_shifter; +input [14:0] sync2ocvt_pd; +input sync2ocvt_pvld; +output cvtout_pvld; +output mul2ocvt_prdy; +output sync2ocvt_prdy; +/////////////////////////////////////////////////////////////////// +reg layer_flag; +reg [31:0] reg2dp_datout_offset_use; +reg [15:0] reg2dp_datout_scale_use; +reg [5:0] reg2dp_datout_shifter_use; +wire cdp_cvtout_in_ready; +wire cdp_cvtout_in_valid; +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${ocvti}-1:0] cdp_cvtout_input_pd_$m; +//: wire [${ocvto}-1:0] cdp_cvtout_output_pd_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [25-1:0] cdp_cvtout_input_pd_0; +wire [8-1:0] cdp_cvtout_output_pd_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire cdp_cvtout_input_rdy; +wire cdp_cvtout_input_vld; +wire [1 -1:0] cdp_cvtout_input_rdys; +wire [1 -1:0] cdp_cvtout_input_vlds; +wire [1*8 -1:0] cdp_cvtout_output_pd; +wire [1 -1:0] cdp_cvtout_output_rdys; +wire [1 -1:0] cdp_cvtout_output_vlds; +wire cdp_cvtout_output_rdy; +wire cdp_cvtout_output_vld; +wire [14:0] data_info_in_pd; +wire [14:0] data_info_in_pd_d0; +wire [14:0] data_info_in_pd_d1; +wire [14:0] data_info_in_pd_d2; +wire [14:0] data_info_in_pd_d3; +wire [14:0] data_info_in_pd_d4; +wire data_info_in_rdy; +wire data_info_in_rdy_d0; +wire data_info_in_rdy_d1; +wire data_info_in_rdy_d2; +wire data_info_in_rdy_d3; +wire data_info_in_rdy_d4; +wire data_info_in_vld; +wire data_info_in_vld_d0; +wire data_info_in_vld_d1; +wire data_info_in_vld_d2; +wire data_info_in_vld_d3; +wire data_info_in_vld_d4; +wire [14:0] data_info_out_pd; +wire data_info_out_rdy; +wire data_info_out_vld; +/////////////////////////////////////////////////////////////////// +//---------------------------------------- +//interlock between data and info +assign cdp_cvtout_in_valid = sync2ocvt_pvld & mul2ocvt_pvld; +assign mul2ocvt_prdy = cdp_cvtout_in_ready & sync2ocvt_pvld; +assign sync2ocvt_prdy = cdp_cvtout_in_ready & mul2ocvt_pvld; +///////////////////////////// +assign cdp_cvtout_in_ready = cdp_cvtout_input_rdy & data_info_in_rdy; +//=============================================== +//pipeline delay for data info to sync with data path +//----------------------------------------------- +//data info valid in +assign data_info_in_vld = cdp_cvtout_in_valid & cdp_cvtout_input_rdy; +//data info data in +assign data_info_in_pd[14:0] = sync2ocvt_pd[14:0]; +assign data_info_in_vld_d0 = data_info_in_vld; +assign data_info_in_rdy = data_info_in_rdy_d0; +assign data_info_in_pd_d0[14:0] = data_info_in_pd[14:0]; +// ::dla_pipe -stages NVDLA_HLS_CDP_OCVT_LATENCY -i data_info_in -o data_info_out -width 15; +NV_NVDLA_CDP_DP_CVTOUT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d0 (data_info_in_pd_d0[14:0]) //|< w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|< w + ,.data_info_in_vld_d0 (data_info_in_vld_d0) //|< w + ,.data_info_in_pd_d1 (data_info_in_pd_d1[14:0]) //|> w + ,.data_info_in_rdy_d0 (data_info_in_rdy_d0) //|> w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|> w + ); +NV_NVDLA_CDP_DP_CVTOUT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d1 (data_info_in_pd_d1[14:0]) //|< w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|< w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|< w + ,.data_info_in_pd_d2 (data_info_in_pd_d2[14:0]) //|> w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|> w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|> w + ); +NV_NVDLA_CDP_DP_CVTOUT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d2 (data_info_in_pd_d2[14:0]) //|< w + ,.data_info_in_rdy_d3 (data_info_in_rdy_d3) //|< w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|< w + ,.data_info_in_pd_d3 (data_info_in_pd_d3[14:0]) //|> w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|> w + ,.data_info_in_vld_d3 (data_info_in_vld_d3) //|> w + ); +NV_NVDLA_CDP_DP_CVTOUT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d3 (data_info_in_pd_d3[14:0]) //|< w + ,.data_info_in_rdy_d4 (data_info_in_rdy_d4) //|< w + ,.data_info_in_vld_d3 (data_info_in_vld_d3) //|< w + ,.data_info_in_pd_d4 (data_info_in_pd_d4[14:0]) //|> w + ,.data_info_in_rdy_d3 (data_info_in_rdy_d3) //|> w + ,.data_info_in_vld_d4 (data_info_in_vld_d4) //|> w + ); +assign data_info_out_vld = data_info_in_vld_d4; +assign data_info_in_rdy_d4 = data_info_out_rdy; +assign data_info_out_pd[14:0] = data_info_in_pd_d4[14:0]; +//=============================================== +//convertor process +//----------------------------------------------- +//cvtout valid input +assign cdp_cvtout_input_vld = cdp_cvtout_in_valid & data_info_in_rdy; +//cvtout ready input +assign cdp_cvtout_input_rdy = &cdp_cvtout_input_rdys; +//cvt sub-unit valid in +//cvt sub-unit data in +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign cdp_cvtout_input_pd_$m = mul2ocvt_pd[${m}*${ocvti}+${ocvti}-1:${m}*${ocvti}]; +//: assign cdp_cvtout_input_vlds[$m] = cdp_cvtout_input_vld +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & cdp_cvtout_input_rdys[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cdp_cvtout_input_pd_0 = mul2ocvt_pd[0*25+25-1:0*25]; +assign cdp_cvtout_input_vlds[0] = cdp_cvtout_input_vld + +& cdp_cvtout_input_rdys[0] + +; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//cvt sub-unit data in +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datout_offset_use[31:0] <= {32{1'b0}}; + end else begin + reg2dp_datout_offset_use[31:0] <= reg2dp_datout_offset[31:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datout_scale_use[15:0] <= {16{1'b0}}; + end else begin + reg2dp_datout_scale_use[15:0] <= reg2dp_datout_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datout_shifter_use[5:0] <= {6{1'b0}}; + end else begin + reg2dp_datout_shifter_use[5:0] <= reg2dp_datout_shifter[5:0]; + end +end +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: HLS_cdp_ocvt u_HLS_cdp_ocvt_$m ( +//: .nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.chn_data_in_rsc_z (cdp_cvtout_input_pd_${m}) //|< w +//: ,.chn_data_in_rsc_vz (cdp_cvtout_input_vlds[$m]) //|< w +//: ,.chn_data_in_rsc_lz (cdp_cvtout_input_rdys[$m]) //|> w +//: ,.cfg_alu_in_rsc_z (reg2dp_datout_offset_use[${ocvti}-1:0]) //|< r +//: ,.cfg_mul_in_rsc_z (reg2dp_datout_scale_use[15:0]) //|< r +//: ,.cfg_truncate_rsc_z (reg2dp_datout_shifter_use[5:0]) //|< r +//: ,.chn_data_out_rsc_z (cdp_cvtout_output_pd_${m}) //|> ? +//: ,.chn_data_out_rsc_vz (cdp_cvtout_output_rdys[$m]) //|< w +//: ,.chn_data_out_rsc_lz (cdp_cvtout_output_vlds[$m]) //|> w +//: ); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +HLS_cdp_ocvt u_HLS_cdp_ocvt_0 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.chn_data_in_rsc_z (cdp_cvtout_input_pd_0) //|< w +,.chn_data_in_rsc_vz (cdp_cvtout_input_vlds[0]) //|< w +,.chn_data_in_rsc_lz (cdp_cvtout_input_rdys[0]) //|> w +,.cfg_alu_in_rsc_z (reg2dp_datout_offset_use[25-1:0]) //|< r +,.cfg_mul_in_rsc_z (reg2dp_datout_scale_use[15:0]) //|< r +,.cfg_truncate_rsc_z (reg2dp_datout_shifter_use[5:0]) //|< r +,.chn_data_out_rsc_z (cdp_cvtout_output_pd_0) //|> ? +,.chn_data_out_rsc_vz (cdp_cvtout_output_rdys[0]) //|< w +,.chn_data_out_rsc_lz (cdp_cvtout_output_vlds[0]) //|> w +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//sub-unit output ready +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign cdp_cvtout_output_rdys[$m] = cdp_cvtout_output_rdy +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & cdp_cvtout_output_vlds[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cdp_cvtout_output_rdys[0] = cdp_cvtout_output_rdy + +& cdp_cvtout_output_vlds[0] + +; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//output valid +assign cdp_cvtout_output_vld = &cdp_cvtout_output_vlds; +//output ready +assign cdp_cvtout_output_rdy = cvtout_prdy & data_info_out_vld; +//output data +assign cdp_cvtout_output_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print qq( +//: cdp_cvtout_output_pd_$i, +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +cdp_cvtout_output_pd_0}; +//=============================================== +//data info output +//----------------------------------------------- +//data info output ready +assign data_info_out_rdy = cvtout_prdy & cdp_cvtout_output_vld; +//=============================================== +//convertor output +//----------------------------------------------- +assign cvtout_pvld = cdp_cvtout_output_vld & data_info_out_vld; +assign cvtout_pd = {data_info_out_pd[14:0],cdp_cvtout_output_pd}; +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_cvtout +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d1[14:0] (data_info_in_vld_d1,data_info_in_rdy_d1) <= data_info_in_pd_d0[14:0] (data_info_in_vld_d0,data_info_in_rdy_d0) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d0 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d0 + ,data_info_in_pd_d1 + ,data_info_in_rdy_d0 + ,data_info_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d0; +input data_info_in_rdy_d1; +input data_info_in_vld_d0; +output [14:0] data_info_in_pd_d1; +output data_info_in_rdy_d0; +output data_info_in_vld_d1; +reg [14:0] data_info_in_pd_d1; +reg data_info_in_rdy_d0; +reg data_info_in_vld_d1; +reg [14:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? data_info_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && data_info_in_vld_d0)? data_info_in_pd_d0[14:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + data_info_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or data_info_in_rdy_d1 + or p1_pipe_data + ) begin + data_info_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = data_info_in_rdy_d1; + data_info_in_pd_d1[14:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d1^data_info_in_rdy_d1^data_info_in_vld_d0^data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d0 && !data_info_in_rdy_d0), (data_info_in_vld_d0), (data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d2[14:0] (data_info_in_vld_d2,data_info_in_rdy_d2) <= data_info_in_pd_d1[14:0] (data_info_in_vld_d1,data_info_in_rdy_d1) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d1 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d1 + ,data_info_in_pd_d2 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d1; +input data_info_in_rdy_d2; +input data_info_in_vld_d1; +output [14:0] data_info_in_pd_d2; +output data_info_in_rdy_d1; +output data_info_in_vld_d2; +reg [14:0] data_info_in_pd_d2; +reg data_info_in_rdy_d1; +reg data_info_in_vld_d2; +reg [14:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? data_info_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && data_info_in_vld_d1)? data_info_in_pd_d1[14:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + data_info_in_rdy_d1 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or data_info_in_rdy_d2 + or p2_pipe_data + ) begin + data_info_in_vld_d2 = p2_pipe_valid; + p2_pipe_ready = data_info_in_rdy_d2; + data_info_in_pd_d2[14:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d2^data_info_in_rdy_d2^data_info_in_vld_d1^data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d1 && !data_info_in_rdy_d1), (data_info_in_vld_d1), (data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d3[14:0] (data_info_in_vld_d3,data_info_in_rdy_d3) <= data_info_in_pd_d2[14:0] (data_info_in_vld_d2,data_info_in_rdy_d2) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d2 + ,data_info_in_rdy_d3 + ,data_info_in_vld_d2 + ,data_info_in_pd_d3 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d2; +input data_info_in_rdy_d3; +input data_info_in_vld_d2; +output [14:0] data_info_in_pd_d3; +output data_info_in_rdy_d2; +output data_info_in_vld_d3; +reg [14:0] data_info_in_pd_d3; +reg data_info_in_rdy_d2; +reg data_info_in_vld_d3; +reg [14:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? data_info_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && data_info_in_vld_d2)? data_info_in_pd_d2[14:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + data_info_in_rdy_d2 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or data_info_in_rdy_d3 + or p3_pipe_data + ) begin + data_info_in_vld_d3 = p3_pipe_valid; + p3_pipe_ready = data_info_in_rdy_d3; + data_info_in_pd_d3[14:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d3^data_info_in_rdy_d3^data_info_in_vld_d2^data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d2 && !data_info_in_rdy_d2), (data_info_in_vld_d2), (data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d4[14:0] (data_info_in_vld_d4,data_info_in_rdy_d4) <= data_info_in_pd_d3[14:0] (data_info_in_vld_d3,data_info_in_rdy_d3) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d3 + ,data_info_in_rdy_d4 + ,data_info_in_vld_d3 + ,data_info_in_pd_d4 + ,data_info_in_rdy_d3 + ,data_info_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d3; +input data_info_in_rdy_d4; +input data_info_in_vld_d3; +output [14:0] data_info_in_pd_d4; +output data_info_in_rdy_d3; +output data_info_in_vld_d4; +reg [14:0] data_info_in_pd_d4; +reg data_info_in_rdy_d3; +reg data_info_in_vld_d4; +reg [14:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? data_info_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && data_info_in_vld_d3)? data_info_in_pd_d3[14:0] : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + data_info_in_rdy_d3 = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or data_info_in_rdy_d4 + or p4_pipe_data + ) begin + data_info_in_vld_d4 = p4_pipe_valid; + p4_pipe_ready = data_info_in_rdy_d4; + data_info_in_pd_d4[14:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d4^data_info_in_rdy_d4^data_info_in_vld_d3^data_info_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d3 && !data_info_in_rdy_d3), (data_info_in_vld_d3), (data_info_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v.vcp new file mode 100644 index 0000000..ce04b2b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v.vcp @@ -0,0 +1,910 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_cvtout.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_cvtout ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvtout_prdy //|< i + ,mul2ocvt_pd //|< i + ,mul2ocvt_pvld //|< i + ,reg2dp_datout_offset //|< i + ,reg2dp_datout_scale //|< i + ,reg2dp_datout_shifter //|< i + ,sync2ocvt_pd //|< i + ,sync2ocvt_pvld //|< i + ,cvtout_pd //|> o + ,cvtout_pvld //|> o + ,mul2ocvt_prdy //|> o + ,sync2ocvt_prdy //|> o + ); +/////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input cvtout_prdy; +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: print "input [${k}*${ocvti}-1:0] mul2ocvt_pd; \n"; +//: print "output [${k}*${ocvto}+14:0] cvtout_pd; \n"; +input mul2ocvt_pvld; +input [31:0] reg2dp_datout_offset; +input [15:0] reg2dp_datout_scale; +input [5:0] reg2dp_datout_shifter; +input [14:0] sync2ocvt_pd; +input sync2ocvt_pvld; +output cvtout_pvld; +output mul2ocvt_prdy; +output sync2ocvt_prdy; +/////////////////////////////////////////////////////////////////// +reg layer_flag; +reg [31:0] reg2dp_datout_offset_use; +reg [15:0] reg2dp_datout_scale_use; +reg [5:0] reg2dp_datout_shifter_use; +wire cdp_cvtout_in_ready; +wire cdp_cvtout_in_valid; +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${ocvti}-1:0] cdp_cvtout_input_pd_$m; +//: wire [${ocvto}-1:0] cdp_cvtout_output_pd_$m; +//: ); +//: } +wire cdp_cvtout_input_rdy; +wire cdp_cvtout_input_vld; +wire [1 -1:0] cdp_cvtout_input_rdys; +wire [1 -1:0] cdp_cvtout_input_vlds; +wire [1*8 -1:0] cdp_cvtout_output_pd; +wire [1 -1:0] cdp_cvtout_output_rdys; +wire [1 -1:0] cdp_cvtout_output_vlds; +wire cdp_cvtout_output_rdy; +wire cdp_cvtout_output_vld; +wire [14:0] data_info_in_pd; +wire [14:0] data_info_in_pd_d0; +wire [14:0] data_info_in_pd_d1; +wire [14:0] data_info_in_pd_d2; +wire [14:0] data_info_in_pd_d3; +wire [14:0] data_info_in_pd_d4; +wire data_info_in_rdy; +wire data_info_in_rdy_d0; +wire data_info_in_rdy_d1; +wire data_info_in_rdy_d2; +wire data_info_in_rdy_d3; +wire data_info_in_rdy_d4; +wire data_info_in_vld; +wire data_info_in_vld_d0; +wire data_info_in_vld_d1; +wire data_info_in_vld_d2; +wire data_info_in_vld_d3; +wire data_info_in_vld_d4; +wire [14:0] data_info_out_pd; +wire data_info_out_rdy; +wire data_info_out_vld; +/////////////////////////////////////////////////////////////////// +//---------------------------------------- +//interlock between data and info +assign cdp_cvtout_in_valid = sync2ocvt_pvld & mul2ocvt_pvld; +assign mul2ocvt_prdy = cdp_cvtout_in_ready & sync2ocvt_pvld; +assign sync2ocvt_prdy = cdp_cvtout_in_ready & mul2ocvt_pvld; +///////////////////////////// +assign cdp_cvtout_in_ready = cdp_cvtout_input_rdy & data_info_in_rdy; +//=============================================== +//pipeline delay for data info to sync with data path +//----------------------------------------------- +//data info valid in +assign data_info_in_vld = cdp_cvtout_in_valid & cdp_cvtout_input_rdy; +//data info data in +assign data_info_in_pd[14:0] = sync2ocvt_pd[14:0]; +assign data_info_in_vld_d0 = data_info_in_vld; +assign data_info_in_rdy = data_info_in_rdy_d0; +assign data_info_in_pd_d0[14:0] = data_info_in_pd[14:0]; +// ::dla_pipe -stages NVDLA_HLS_CDP_OCVT_LATENCY -i data_info_in -o data_info_out -width 15; +NV_NVDLA_CDP_DP_CVTOUT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d0 (data_info_in_pd_d0[14:0]) //|< w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|< w + ,.data_info_in_vld_d0 (data_info_in_vld_d0) //|< w + ,.data_info_in_pd_d1 (data_info_in_pd_d1[14:0]) //|> w + ,.data_info_in_rdy_d0 (data_info_in_rdy_d0) //|> w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|> w + ); +NV_NVDLA_CDP_DP_CVTOUT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d1 (data_info_in_pd_d1[14:0]) //|< w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|< w + ,.data_info_in_vld_d1 (data_info_in_vld_d1) //|< w + ,.data_info_in_pd_d2 (data_info_in_pd_d2[14:0]) //|> w + ,.data_info_in_rdy_d1 (data_info_in_rdy_d1) //|> w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|> w + ); +NV_NVDLA_CDP_DP_CVTOUT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d2 (data_info_in_pd_d2[14:0]) //|< w + ,.data_info_in_rdy_d3 (data_info_in_rdy_d3) //|< w + ,.data_info_in_vld_d2 (data_info_in_vld_d2) //|< w + ,.data_info_in_pd_d3 (data_info_in_pd_d3[14:0]) //|> w + ,.data_info_in_rdy_d2 (data_info_in_rdy_d2) //|> w + ,.data_info_in_vld_d3 (data_info_in_vld_d3) //|> w + ); +NV_NVDLA_CDP_DP_CVTOUT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_info_in_pd_d3 (data_info_in_pd_d3[14:0]) //|< w + ,.data_info_in_rdy_d4 (data_info_in_rdy_d4) //|< w + ,.data_info_in_vld_d3 (data_info_in_vld_d3) //|< w + ,.data_info_in_pd_d4 (data_info_in_pd_d4[14:0]) //|> w + ,.data_info_in_rdy_d3 (data_info_in_rdy_d3) //|> w + ,.data_info_in_vld_d4 (data_info_in_vld_d4) //|> w + ); +assign data_info_out_vld = data_info_in_vld_d4; +assign data_info_in_rdy_d4 = data_info_out_rdy; +assign data_info_out_pd[14:0] = data_info_in_pd_d4[14:0]; +//=============================================== +//convertor process +//----------------------------------------------- +//cvtout valid input +assign cdp_cvtout_input_vld = cdp_cvtout_in_valid & data_info_in_rdy; +//cvtout ready input +assign cdp_cvtout_input_rdy = &cdp_cvtout_input_rdys; +//cvt sub-unit valid in +//cvt sub-unit data in +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign cdp_cvtout_input_pd_$m = mul2ocvt_pd[${m}*${ocvti}+${ocvti}-1:${m}*${ocvti}]; +//: assign cdp_cvtout_input_vlds[$m] = cdp_cvtout_input_vld +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & cdp_cvtout_input_rdys[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//cvt sub-unit data in +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datout_offset_use[31:0] <= {32{1'b0}}; + end else begin + reg2dp_datout_offset_use[31:0] <= reg2dp_datout_offset[31:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datout_scale_use[15:0] <= {16{1'b0}}; + end else begin + reg2dp_datout_scale_use[15:0] <= reg2dp_datout_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_datout_shifter_use[5:0] <= {6{1'b0}}; + end else begin + reg2dp_datout_shifter_use[5:0] <= reg2dp_datout_shifter[5:0]; + end +end +//: my $k = 1; +//: my $icvto = (8 +1); +//: my $ocvti = $icvto + 16; +//: my $ocvto = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: HLS_cdp_ocvt u_HLS_cdp_ocvt_$m ( +//: .nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.chn_data_in_rsc_z (cdp_cvtout_input_pd_${m}) //|< w +//: ,.chn_data_in_rsc_vz (cdp_cvtout_input_vlds[$m]) //|< w +//: ,.chn_data_in_rsc_lz (cdp_cvtout_input_rdys[$m]) //|> w +//: ,.cfg_alu_in_rsc_z (reg2dp_datout_offset_use[${ocvti}-1:0]) //|< r +//: ,.cfg_mul_in_rsc_z (reg2dp_datout_scale_use[15:0]) //|< r +//: ,.cfg_truncate_rsc_z (reg2dp_datout_shifter_use[5:0]) //|< r +//: ,.chn_data_out_rsc_z (cdp_cvtout_output_pd_${m}) //|> ? +//: ,.chn_data_out_rsc_vz (cdp_cvtout_output_rdys[$m]) //|< w +//: ,.chn_data_out_rsc_lz (cdp_cvtout_output_vlds[$m]) //|> w +//: ); +//: ); +//: } +//sub-unit output ready +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign cdp_cvtout_output_rdys[$m] = cdp_cvtout_output_rdy +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & cdp_cvtout_output_vlds[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//output valid +assign cdp_cvtout_output_vld = &cdp_cvtout_output_vlds; +//output ready +assign cdp_cvtout_output_rdy = cvtout_prdy & data_info_out_vld; +//output data +assign cdp_cvtout_output_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print qq( +//: cdp_cvtout_output_pd_$i, +//: ); +//: } +//: } +cdp_cvtout_output_pd_0}; +//=============================================== +//data info output +//----------------------------------------------- +//data info output ready +assign data_info_out_rdy = cvtout_prdy & cdp_cvtout_output_vld; +//=============================================== +//convertor output +//----------------------------------------------- +assign cvtout_pvld = cdp_cvtout_output_vld & data_info_out_vld; +assign cvtout_pd = {data_info_out_pd[14:0],cdp_cvtout_output_pd}; +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_cvtout +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d1[14:0] (data_info_in_vld_d1,data_info_in_rdy_d1) <= data_info_in_pd_d0[14:0] (data_info_in_vld_d0,data_info_in_rdy_d0) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d0 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d0 + ,data_info_in_pd_d1 + ,data_info_in_rdy_d0 + ,data_info_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d0; +input data_info_in_rdy_d1; +input data_info_in_vld_d0; +output [14:0] data_info_in_pd_d1; +output data_info_in_rdy_d0; +output data_info_in_vld_d1; +reg [14:0] data_info_in_pd_d1; +reg data_info_in_rdy_d0; +reg data_info_in_vld_d1; +reg [14:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? data_info_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && data_info_in_vld_d0)? data_info_in_pd_d0[14:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + data_info_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or data_info_in_rdy_d1 + or p1_pipe_data + ) begin + data_info_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = data_info_in_rdy_d1; + data_info_in_pd_d1[14:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d1^data_info_in_rdy_d1^data_info_in_vld_d0^data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d0 && !data_info_in_rdy_d0), (data_info_in_vld_d0), (data_info_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d2[14:0] (data_info_in_vld_d2,data_info_in_rdy_d2) <= data_info_in_pd_d1[14:0] (data_info_in_vld_d1,data_info_in_rdy_d1) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d1 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d1 + ,data_info_in_pd_d2 + ,data_info_in_rdy_d1 + ,data_info_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d1; +input data_info_in_rdy_d2; +input data_info_in_vld_d1; +output [14:0] data_info_in_pd_d2; +output data_info_in_rdy_d1; +output data_info_in_vld_d2; +reg [14:0] data_info_in_pd_d2; +reg data_info_in_rdy_d1; +reg data_info_in_vld_d2; +reg [14:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? data_info_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && data_info_in_vld_d1)? data_info_in_pd_d1[14:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + data_info_in_rdy_d1 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or data_info_in_rdy_d2 + or p2_pipe_data + ) begin + data_info_in_vld_d2 = p2_pipe_valid; + p2_pipe_ready = data_info_in_rdy_d2; + data_info_in_pd_d2[14:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d2^data_info_in_rdy_d2^data_info_in_vld_d1^data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d1 && !data_info_in_rdy_d1), (data_info_in_vld_d1), (data_info_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d3[14:0] (data_info_in_vld_d3,data_info_in_rdy_d3) <= data_info_in_pd_d2[14:0] (data_info_in_vld_d2,data_info_in_rdy_d2) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d2 + ,data_info_in_rdy_d3 + ,data_info_in_vld_d2 + ,data_info_in_pd_d3 + ,data_info_in_rdy_d2 + ,data_info_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d2; +input data_info_in_rdy_d3; +input data_info_in_vld_d2; +output [14:0] data_info_in_pd_d3; +output data_info_in_rdy_d2; +output data_info_in_vld_d3; +reg [14:0] data_info_in_pd_d3; +reg data_info_in_rdy_d2; +reg data_info_in_vld_d3; +reg [14:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? data_info_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && data_info_in_vld_d2)? data_info_in_pd_d2[14:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + data_info_in_rdy_d2 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or data_info_in_rdy_d3 + or p3_pipe_data + ) begin + data_info_in_vld_d3 = p3_pipe_valid; + p3_pipe_ready = data_info_in_rdy_d3; + data_info_in_pd_d3[14:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d3^data_info_in_rdy_d3^data_info_in_vld_d2^data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d2 && !data_info_in_rdy_d2), (data_info_in_vld_d2), (data_info_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none data_info_in_pd_d4[14:0] (data_info_in_vld_d4,data_info_in_rdy_d4) <= data_info_in_pd_d3[14:0] (data_info_in_vld_d3,data_info_in_rdy_d3) +// ************************************************************************************************************** +module NV_NVDLA_CDP_DP_CVTOUT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,data_info_in_pd_d3 + ,data_info_in_rdy_d4 + ,data_info_in_vld_d3 + ,data_info_in_pd_d4 + ,data_info_in_rdy_d3 + ,data_info_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [14:0] data_info_in_pd_d3; +input data_info_in_rdy_d4; +input data_info_in_vld_d3; +output [14:0] data_info_in_pd_d4; +output data_info_in_rdy_d3; +output data_info_in_vld_d4; +reg [14:0] data_info_in_pd_d4; +reg data_info_in_rdy_d3; +reg data_info_in_vld_d4; +reg [14:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? data_info_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && data_info_in_vld_d3)? data_info_in_pd_d3[14:0] : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + data_info_in_rdy_d3 = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or data_info_in_rdy_d4 + or p4_pipe_data + ) begin + data_info_in_vld_d4 = p4_pipe_valid; + p4_pipe_ready = data_info_in_rdy_d4; + data_info_in_pd_d4[14:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (data_info_in_vld_d4^data_info_in_rdy_d4^data_info_in_vld_d3^data_info_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (data_info_in_vld_d3 && !data_info_in_rdy_d3), (data_info_in_vld_d3), (data_info_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_DP_CVTOUT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v new file mode 100644 index 0000000..5710f6c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v @@ -0,0 +1,2440 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_intp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_intp ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2reg_done //|< i + ,intp2mul_prdy //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,lut2intp_X_data_${m}0 //|> o +//: ,lut2intp_X_data_${m}0_17b //|> o +//: ,lut2intp_X_data_${m}1 //|> o +//: ,lut2intp_X_info_${m} //|> o +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,lut2intp_X_data_00 //|> o +,lut2intp_X_data_00_17b //|> o +,lut2intp_X_data_01 //|> o +,lut2intp_X_info_0 //|> o + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,lut2intp_X_sel //|< i + ,lut2intp_Y_sel //|< i + ,lut2intp_pvld //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_lut_le_end_high //|< i + ,reg2dp_lut_le_end_low //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_slope_oflow_scale //|< i + ,reg2dp_lut_le_slope_oflow_shift //|< i + ,reg2dp_lut_le_slope_uflow_scale //|< i + ,reg2dp_lut_le_slope_uflow_shift //|< i + ,reg2dp_lut_le_start_high //|< i + ,reg2dp_lut_le_start_low //|< i + ,reg2dp_lut_lo_end_high //|< i + ,reg2dp_lut_lo_end_low //|< i + ,reg2dp_lut_lo_slope_oflow_scale //|< i + ,reg2dp_lut_lo_slope_oflow_shift //|< i + ,reg2dp_lut_lo_slope_uflow_scale //|< i + ,reg2dp_lut_lo_slope_uflow_shift //|< i + ,reg2dp_lut_lo_start_high //|< i + ,reg2dp_lut_lo_start_low //|< i + ,reg2dp_sqsum_bypass //|< i + ,sync2itp_pd //|< i + ,sync2itp_pvld //|< i + ,dp2reg_d0_perf_lut_hybrid //|> o + ,dp2reg_d0_perf_lut_le_hit //|> o + ,dp2reg_d0_perf_lut_lo_hit //|> o + ,dp2reg_d0_perf_lut_oflow //|> o + ,dp2reg_d0_perf_lut_uflow //|> o + ,dp2reg_d1_perf_lut_hybrid //|> o + ,dp2reg_d1_perf_lut_le_hit //|> o + ,dp2reg_d1_perf_lut_lo_hit //|> o + ,dp2reg_d1_perf_lut_oflow //|> o + ,dp2reg_d1_perf_lut_uflow //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,intp2mul_pd_$m //|> o +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,intp2mul_pd_0 //|> o + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,intp2mul_pvld //|> o + ,lut2intp_prdy //|> o + ,sync2itp_prdy //|> o + ); +////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input intp2mul_prdy; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: input [31:0] lut2intp_X_data_${m}0; +//: input [16:0] lut2intp_X_data_${m}0_17b; +//: input [31:0] lut2intp_X_data_${m}1; +//: input [19:0] lut2intp_X_info_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [31:0] lut2intp_X_data_00; +input [16:0] lut2intp_X_data_00_17b; +input [31:0] lut2intp_X_data_01; +input [19:0] lut2intp_X_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [1 -1:0] lut2intp_X_sel; +input [1 -1:0] lut2intp_Y_sel; +input lut2intp_pvld; +input [31:0] pwrbus_ram_pd; +input [5:0] reg2dp_lut_le_end_high; +input [31:0] reg2dp_lut_le_end_low; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [15:0] reg2dp_lut_le_slope_oflow_scale; +input [4:0] reg2dp_lut_le_slope_oflow_shift; +input [15:0] reg2dp_lut_le_slope_uflow_scale; +input [4:0] reg2dp_lut_le_slope_uflow_shift; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [5:0] reg2dp_lut_lo_end_high; +input [31:0] reg2dp_lut_lo_end_low; +input [15:0] reg2dp_lut_lo_slope_oflow_scale; +input [4:0] reg2dp_lut_lo_slope_oflow_shift; +input [15:0] reg2dp_lut_lo_slope_uflow_scale; +input [4:0] reg2dp_lut_lo_slope_uflow_shift; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_sqsum_bypass; +//: my $k = 1; +//: my $icvto = (8 +1); +//: print "input [${k}*(${icvto}*2+3)-1:0] sync2itp_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [1*(9*2+3)-1:0] sync2itp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input sync2itp_pvld; +output [31:0] dp2reg_d0_perf_lut_hybrid; +output [31:0] dp2reg_d0_perf_lut_le_hit; +output [31:0] dp2reg_d0_perf_lut_lo_hit; +output [31:0] dp2reg_d0_perf_lut_oflow; +output [31:0] dp2reg_d0_perf_lut_uflow; +output [31:0] dp2reg_d1_perf_lut_hybrid; +output [31:0] dp2reg_d1_perf_lut_le_hit; +output [31:0] dp2reg_d1_perf_lut_lo_hit; +output [31:0] dp2reg_d1_perf_lut_oflow; +output [31:0] dp2reg_d1_perf_lut_uflow; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: output [16:0] intp2mul_pd_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [16:0] intp2mul_pd_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output intp2mul_pvld; +output lut2intp_prdy; +output sync2itp_prdy; +////////////////////////////////////////////////////////////////////// +reg X_exp; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: reg [38:0] Xinterp_in0_pd_$m; +//: reg [37:0] Xinterp_in1_pd_$m; +//: reg [16:0] Xinterp_in_pd_$m; +//: reg [16:0] Xinterp_in_scale_$m; +//: reg [5:0] Xinterp_in_shift_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [38:0] Xinterp_in0_pd_0; +reg [37:0] Xinterp_in1_pd_0; +reg [16:0] Xinterp_in_pd_0; +reg [16:0] Xinterp_in_scale_0; +reg [5:0] Xinterp_in_shift_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [31:0] both_hybrid_counter; +reg [1 -1:0] both_hybrid_flag; +reg [31:0] both_of_counter; +reg [1 -1:0] both_of_flag; +reg [31:0] both_uf_counter; +reg [1 -1:0] both_uf_flag; +reg [31:0] dp2reg_d0_perf_lut_hybrid; +reg [31:0] dp2reg_d0_perf_lut_le_hit; +reg [31:0] dp2reg_d0_perf_lut_lo_hit; +reg [31:0] dp2reg_d0_perf_lut_oflow; +reg [31:0] dp2reg_d0_perf_lut_uflow; +reg [31:0] dp2reg_d1_perf_lut_hybrid; +reg [31:0] dp2reg_d1_perf_lut_le_hit; +reg [31:0] dp2reg_d1_perf_lut_lo_hit; +reg [31:0] dp2reg_d1_perf_lut_oflow; +reg [31:0] dp2reg_d1_perf_lut_uflow; +//reg [1*17-1:0] intp2mul_pd; +//reg intp2mul_pvld; +reg intp_pvld_d; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: reg [16:0] ip2mul_pd_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [16:0] ip2mul_pd_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//reg ip2mul_prdy; +reg layer_flg; +//reg [1*103-1:0] lut2intp_data; +//reg lut2intp_prdy; +//reg lut2intp_valid; +reg [37:0] lut_le_max; +reg [38:0] lut_le_min; +reg [37:0] lut_lo_max; +reg [37:0] lut_lo_min; +reg [1 -1:0] only_le_hit; +reg [31:0] only_le_hit_counter; +reg [1 -1:0] only_lo_hit; +reg [31:0] only_lo_hit_counter; +reg [15:0] reg2dp_lut_le_slope_oflow_scale_sync; +reg [4:0] reg2dp_lut_le_slope_oflow_shift_sync; +reg [15:0] reg2dp_lut_le_slope_uflow_scale_sync; +reg [4:0] reg2dp_lut_le_slope_uflow_shift_sync; +reg [15:0] reg2dp_lut_lo_slope_oflow_scale_sync; +reg [4:0] reg2dp_lut_lo_slope_oflow_shift_sync; +reg [15:0] reg2dp_lut_lo_slope_uflow_scale_sync; +reg [4:0] reg2dp_lut_lo_slope_uflow_shift_sync; +reg sqsum_bypass_enable; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [1:0] X_info_$m; +//: wire X_oflow_$m; +//: wire X_uflow_$m; +//: wire [1:0] Y_info_$m; +//: wire Y_oflow_$m; +//: wire Y_uflow_$m; +//: wire [16:0] Xinterp_out_pd_$m; +//: wire [37:0] hit_in1_pd_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [1:0] X_info_0; +wire X_oflow_0; +wire X_uflow_0; +wire [1:0] Y_info_0; +wire Y_oflow_0; +wire Y_uflow_0; +wire [16:0] Xinterp_out_pd_0; +wire [37:0] hit_in1_pd_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [1 -1:0] Xinterp_in_rdy; +wire [1 -1:0] Xinterp_in_vld; +wire [1 -1:0] Xinterp_out_rdy; +wire [1 -1:0] Xinterp_out_vld; +wire [31:0] both_hybrid_counter_nxt; +wire [3:0] both_hybrid_ele; +wire [31:0] both_of_counter_nxt; +wire [3:0] both_of_ele; +wire [31:0] both_uf_counter_nxt; +wire [3:0] both_uf_ele; +wire [1*4-1:0] dat_info_in; +wire [1*2-1:0] info_Xin_pd; +wire [1*2-1:0] info_Yin_pd; +wire [1*4-1:0] info_in_pd; +wire info_in_rdy; +wire info_in_vld; +wire [1*4-1:0] info_o_pd; +wire info_o_rdy; +wire info_o_vld; +wire intp_in_prdy; +wire intp_in_pvld; +wire intp_prdy; +wire intp_prdy_d; +wire intp_pvld; +wire [1*17-1:0] ip2mul_pd; +wire ip2mul_pvld; +wire layer_done; +wire [127:0] le_offset_exp; +wire [6:0] le_offset_use; +wire [16:0] le_slope_oflow_scale; +wire [16:0] le_slope_uflow_scale; +wire [16:0] lo_slope_oflow_scale; +wire [16:0] lo_slope_uflow_scale; +wire [1*103-1:0] lut2intp_pd; +wire lut2intp_ready; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [31:0] lut2ip_X_data_${m}0; +//: wire [16:0] lut2ip_X_data_${m}0_17b; +//: wire [31:0] lut2ip_X_data_${m}1; +//: wire [19:0] lut2ip_X_info_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [31:0] lut2ip_X_data_00; +wire [16:0] lut2ip_X_data_00_17b; +wire [31:0] lut2ip_X_data_01; +wire [19:0] lut2ip_X_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [1 -1:0] lut2ip_X_sel; +wire [1 -1:0] lut2ip_Y_sel; +wire [37:0] lut_le_end; +wire [38:0] lut_le_min_int; +wire [37:0] lut_le_start; +wire [37:0] lut_lo_end; +wire [37:0] lut_lo_start; +wire mon_both_hybrid_counter_nxt; +wire mon_both_of_counter_nxt; +wire mon_both_uf_counter_nxt; +wire [90:0] mon_lut_le_min_int; +wire mon_only_le_hit_counter_nxt; +wire mon_only_lo_hit_counter_nxt; +wire [31:0] only_le_hit_counter_nxt; +wire [3:0] only_le_hit_ele; +wire [31:0] only_lo_hit_counter_nxt; +wire [3:0] only_lo_hit_ele; +/////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + X_exp <= 1'b0; + end else begin + X_exp <= reg2dp_lut_le_function == 1'h0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sqsum_bypass_enable <= 1'b0; + end else begin + sqsum_bypass_enable <= reg2dp_sqsum_bypass == 1'h1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_uflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_le_slope_uflow_shift_sync <= reg2dp_lut_le_slope_uflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_oflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_le_slope_oflow_shift_sync <= reg2dp_lut_le_slope_oflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_uflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_lo_slope_uflow_shift_sync <= reg2dp_lut_lo_slope_uflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_oflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_lo_slope_oflow_shift_sync <= reg2dp_lut_lo_slope_oflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_uflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_le_slope_uflow_scale_sync <= reg2dp_lut_le_slope_uflow_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_oflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_le_slope_oflow_scale_sync <= reg2dp_lut_le_slope_oflow_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_uflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_lo_slope_uflow_scale_sync <= reg2dp_lut_lo_slope_uflow_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_oflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_lo_slope_oflow_scale_sync <= reg2dp_lut_lo_slope_oflow_scale[15:0]; + end +end +/////////////////////////////////////////// +assign le_slope_uflow_scale = {reg2dp_lut_le_slope_uflow_scale_sync[15],reg2dp_lut_le_slope_uflow_scale_sync[15:0]}; +assign le_slope_oflow_scale = {reg2dp_lut_le_slope_oflow_scale_sync[15],reg2dp_lut_le_slope_oflow_scale_sync[15:0]}; +assign lo_slope_uflow_scale = {reg2dp_lut_lo_slope_uflow_scale_sync[15],reg2dp_lut_lo_slope_uflow_scale_sync[15:0]}; +assign lo_slope_oflow_scale = {reg2dp_lut_lo_slope_oflow_scale_sync[15],reg2dp_lut_lo_slope_oflow_scale_sync[15:0]}; +/////////////////////////////////////////// +//lut2intp pipe sync for timing +assign lut2intp_pd = { +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2intp_X_data_${m}0[31:0],lut2intp_X_data_${m}0_17b[16:0],lut2intp_X_data_${m}1[31:0], +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2intp_X_info_${m}[19:0], +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +lut2intp_X_data_00[31:0],lut2intp_X_data_00_17b[16:0],lut2intp_X_data_01[31:0], + +lut2intp_X_info_0[19:0], + +//| eperl: generated_end (DO NOT EDIT ABOVE) + lut2intp_X_sel, + lut2intp_Y_sel + }; +//: my $k = 1*103; +//: &eperl::pipe(" -is -wid $k -do lut2intp_data -vo lut2intp_valid -ri lut2intp_ready -di lut2intp_pd -vi lut2intp_pvld -ro lut2intp_prdy "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg lut2intp_prdy; +reg skid_flop_lut2intp_prdy; +reg skid_flop_lut2intp_pvld; +reg [103-1:0] skid_flop_lut2intp_pd; +reg pipe_skid_lut2intp_pvld; +reg [103-1:0] pipe_skid_lut2intp_pd; +// Wire +wire skid_lut2intp_pvld; +wire [103-1:0] skid_lut2intp_pd; +wire skid_lut2intp_prdy; +wire pipe_skid_lut2intp_prdy; +wire lut2intp_valid; +wire [103-1:0] lut2intp_data; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut2intp_prdy <= 1'b1; + skid_flop_lut2intp_prdy <= 1'b1; + end else begin + lut2intp_prdy <= skid_lut2intp_prdy; + skid_flop_lut2intp_prdy <= skid_lut2intp_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_lut2intp_pvld <= 1'b0; + end else begin + if (skid_flop_lut2intp_prdy) begin + skid_flop_lut2intp_pvld <= lut2intp_pvld; + end + end +end +assign skid_lut2intp_pvld = (skid_flop_lut2intp_prdy) ? lut2intp_pvld : skid_flop_lut2intp_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_lut2intp_prdy & lut2intp_pvld) begin + skid_flop_lut2intp_pd[103-1:0] <= lut2intp_pd[103-1:0]; + end +end +assign skid_lut2intp_pd[103-1:0] = (skid_flop_lut2intp_prdy) ? lut2intp_pd[103-1:0] : skid_flop_lut2intp_pd[103-1:0]; + + +// PIPE READY +assign skid_lut2intp_prdy = pipe_skid_lut2intp_prdy || !pipe_skid_lut2intp_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_lut2intp_pvld <= 1'b0; + end else begin + if (skid_lut2intp_prdy) begin + pipe_skid_lut2intp_pvld <= skid_lut2intp_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_lut2intp_prdy && skid_lut2intp_pvld) begin + pipe_skid_lut2intp_pd[103-1:0] <= skid_lut2intp_pd[103-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_lut2intp_prdy = lut2intp_ready; +assign lut2intp_valid = pipe_skid_lut2intp_pvld; +assign lut2intp_data = pipe_skid_lut2intp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign { +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2ip_X_data_${m}0[31:0],lut2ip_X_data_${m}0_17b[16:0],lut2ip_X_data_${m}1[31:0], +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2ip_X_info_${m}[19:0], +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +lut2ip_X_data_00[31:0],lut2ip_X_data_00_17b[16:0],lut2ip_X_data_01[31:0], + +lut2ip_X_info_0[19:0], + +//| eperl: generated_end (DO NOT EDIT ABOVE) + lut2ip_X_sel, + lut2ip_Y_sel} = lut2intp_data; +/////////////////////////////////////////// +//lock +//from lut2int and sync2itp to intp_in +assign lut2intp_ready = intp_in_prdy & sync2itp_pvld; +assign sync2itp_prdy = intp_in_prdy & lut2intp_valid; +assign intp_in_pvld = sync2itp_pvld & lut2intp_valid; +/////////////////////////////////////////// +assign intp_in_prdy = (&Xinterp_in_rdy) & info_in_rdy; +//: my $k = 1; +//: my $icvto=(8 +1); +//: my $sqbw=${icvto}*2+3; +//: foreach my $m (0..$k -1) { +//: print qq( +//: assign hit_in1_pd_$m = (sqsum_bypass_enable ? {{(38-${sqbw}){sync2itp_pd[${sqbw}*$m+${sqbw}-1]}} ,sync2itp_pd[${sqbw}*$m+${sqbw}-1:${sqbw}*$m]} : {17'd0,sync2itp_pd[${sqbw}*$m+${sqbw}-1:${sqbw}*$m] }); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign hit_in1_pd_0 = (sqsum_bypass_enable ? {{(38-21){sync2itp_pd[21*0+21-1]}} ,sync2itp_pd[21*0+21-1:21*0]} : {17'd0,sync2itp_pd[21*0+21-1:21*0] }); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////////////////////////////// +//start/end prepare for out of range interpolation +///////////////////////////////////////////////// +assign lut_le_end[37:0] = {reg2dp_lut_le_end_high[5:0],reg2dp_lut_le_end_low[31:0]}; +assign lut_le_start[37:0] = {reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:0]}; +assign lut_lo_end[37:0] = {reg2dp_lut_lo_end_high[5:0],reg2dp_lut_lo_end_low[31:0]}; +assign lut_lo_start[37:0] = {reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:0]}; +assign le_offset_use = reg2dp_lut_le_index_offset[6:0]; +assign le_offset_exp[127:0] = reg2dp_lut_le_index_offset[7] ? 128'd0 : (1'b1 << le_offset_use); +assign {mon_lut_le_min_int[90:0],lut_le_min_int[38:0]} = X_exp ? ($signed({{91{lut_le_start[37]}}, lut_le_start[37:0]}) + $signed({1'b0,le_offset_exp})) : {{92{lut_le_start[37]}}, lut_le_start[37:0]}; +// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_le_max[37:0] <= {38{1'b0}}; + end else begin + lut_le_max[37:0] <= lut_le_end; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_le_min[38:0] <= {39{1'b0}}; + end else begin + lut_le_min[38:0] <= lut_le_min_int; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_lo_max[37:0] <= {38{1'b0}}; + end else begin + lut_lo_max[37:0] <= lut_lo_end; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_lo_min[37:0] <= {38{1'b0}}; + end else begin + lut_lo_min[37:0] <= lut_lo_start; + end +end +///////////////////////////////////////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign X_uflow_${m} = lut2ip_X_info_${m}[16]; +//: assign X_oflow_${m} = lut2ip_X_info_${m}[17]; +//: assign Y_uflow_${m} = lut2ip_X_info_${m}[18]; +//: assign Y_oflow_${m} = lut2ip_X_info_${m}[19]; +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m) +//: Xinterp_in0_pd_$m = lut_le_min[38:0]; +//: else if(X_oflow_$m) +//: Xinterp_in0_pd_$m = {lut_le_max[37],lut_le_max[37:0]}; +//: else +//: Xinterp_in0_pd_$m = {{7{lut2ip_X_data_${m}0[31]}},lut2ip_X_data_${m}0[31:0]}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m) +//: Xinterp_in0_pd_$m = {lut_lo_min[37],lut_lo_min[37:0]}; +//: else if(Y_oflow_$m) +//: Xinterp_in0_pd_$m = {lut_lo_max[37],lut_lo_max[37:0]}; +//: else +//: Xinterp_in0_pd_$m = {{7{lut2ip_X_data_${m}0[31]}},lut2ip_X_data_${m}0[31:0]}; +//: end else +//: Xinterp_in0_pd_$m = 39'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m | X_oflow_$m) +//: Xinterp_in1_pd_$m = hit_in1_pd_$m; +//: else +//: Xinterp_in1_pd_$m = {{6{lut2ip_X_data_${m}1[31]}},lut2ip_X_data_${m}1[31:0]}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m | Y_oflow_$m) +//: Xinterp_in1_pd_$m = hit_in1_pd_$m; +//: else +//: Xinterp_in1_pd_$m = {{6{lut2ip_X_data_${m}1[31]}},lut2ip_X_data_${m}1[31:0]}; +//: end else +//: Xinterp_in1_pd_$m = 38'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m] | lut2ip_Y_sel[$m]) +//: Xinterp_in_pd_$m = lut2ip_X_data_${m}0_17b[16:0]; +//: else +//: Xinterp_in_pd_$m = 17'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m) +//: Xinterp_in_scale_$m = le_slope_uflow_scale[16:0]; +//: else if(X_oflow_$m) +//: Xinterp_in_scale_$m = le_slope_oflow_scale[16:0]; +//: else +//: Xinterp_in_scale_$m = {1'b0,lut2ip_X_info_${m}[15:0]}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m) +//: Xinterp_in_scale_$m = lo_slope_uflow_scale[16:0]; +//: else if(Y_oflow_$m) +//: Xinterp_in_scale_$m = lo_slope_oflow_scale[16:0]; +//: else +//: Xinterp_in_scale_$m = {1'b0,lut2ip_X_info_${m}[15:0]}; +//: end else +//: Xinterp_in_scale_$m = 17'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_le_slope_uflow_shift_sync[4]}}, reg2dp_lut_le_slope_uflow_shift_sync[4:0]}; +//: else if(X_oflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_le_slope_oflow_shift_sync[4]}}, reg2dp_lut_le_slope_oflow_shift_sync[4:0]}; +//: else +//: Xinterp_in_shift_$m = {1'b0,5'd16}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_lo_slope_uflow_shift_sync[4]}}, reg2dp_lut_lo_slope_uflow_shift_sync[4:0]}; +//: else if(Y_oflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_lo_slope_oflow_shift_sync[4]}}, reg2dp_lut_lo_slope_oflow_shift_sync[4:0]}; +//: else +//: Xinterp_in_shift_$m = {1'b0,5'd16}; +//: end else +//: Xinterp_in_shift_$m = 6'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign Xinterp_in_vld[$m] = intp_in_pvld & info_in_rdy +//: ); +//: foreach my $i (0..$k-1) { +//: if($i != $m) { +//: print qq( +//: & Xinterp_in_rdy[$i] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: NV_NVDLA_CDP_DP_INTP_unit u_interp_X$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.interp_in0_pd (Xinterp_in0_pd_${m}[38:0]) +//: ,.interp_in1_pd (Xinterp_in1_pd_${m}[37:0]) +//: ,.interp_in_pd (Xinterp_in_pd_${m}[16:0]) +//: ,.interp_in_scale (Xinterp_in_scale_${m}[16:0]) +//: ,.interp_in_shift (Xinterp_in_shift_${m}[5:0]) +//: ,.interp_in_vld (Xinterp_in_vld[$m]) +//: ,.interp_out_rdy (Xinterp_out_rdy[$m]) +//: ,.interp_in_rdy (Xinterp_in_rdy[$m]) +//: ,.interp_out_pd (Xinterp_out_pd_${m}[16:0]) +//: ,.interp_out_vld (Xinterp_out_vld[$m]) +//: ); +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign Xinterp_out_rdy[$m] = intp_prdy & info_o_vld +//: ); +//: foreach my $i (0..$k-1) { +//: if($i != $m) { +//: print qq( +//: & Xinterp_out_vld[$i] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign X_uflow_0 = lut2ip_X_info_0[16]; +assign X_oflow_0 = lut2ip_X_info_0[17]; +assign Y_uflow_0 = lut2ip_X_info_0[18]; +assign Y_oflow_0 = lut2ip_X_info_0[19]; + +always @(*) begin +if(lut2ip_X_sel[0]) begin +if(X_uflow_0) +Xinterp_in0_pd_0 = lut_le_min[38:0]; +else if(X_oflow_0) +Xinterp_in0_pd_0 = {lut_le_max[37],lut_le_max[37:0]}; +else +Xinterp_in0_pd_0 = {{7{lut2ip_X_data_00[31]}},lut2ip_X_data_00[31:0]}; +end else if(lut2ip_Y_sel[0]) begin +if(Y_uflow_0) +Xinterp_in0_pd_0 = {lut_lo_min[37],lut_lo_min[37:0]}; +else if(Y_oflow_0) +Xinterp_in0_pd_0 = {lut_lo_max[37],lut_lo_max[37:0]}; +else +Xinterp_in0_pd_0 = {{7{lut2ip_X_data_00[31]}},lut2ip_X_data_00[31:0]}; +end else +Xinterp_in0_pd_0 = 39'd0; +end + +always @(*) begin +if(lut2ip_X_sel[0]) begin +if(X_uflow_0 | X_oflow_0) +Xinterp_in1_pd_0 = hit_in1_pd_0; +else +Xinterp_in1_pd_0 = {{6{lut2ip_X_data_01[31]}},lut2ip_X_data_01[31:0]}; +end else if(lut2ip_Y_sel[0]) begin +if(Y_uflow_0 | Y_oflow_0) +Xinterp_in1_pd_0 = hit_in1_pd_0; +else +Xinterp_in1_pd_0 = {{6{lut2ip_X_data_01[31]}},lut2ip_X_data_01[31:0]}; +end else +Xinterp_in1_pd_0 = 38'd0; +end + +always @(*) begin +if(lut2ip_X_sel[0] | lut2ip_Y_sel[0]) +Xinterp_in_pd_0 = lut2ip_X_data_00_17b[16:0]; +else +Xinterp_in_pd_0 = 17'd0; +end + +always @(*) begin +if(lut2ip_X_sel[0]) begin +if(X_uflow_0) +Xinterp_in_scale_0 = le_slope_uflow_scale[16:0]; +else if(X_oflow_0) +Xinterp_in_scale_0 = le_slope_oflow_scale[16:0]; +else +Xinterp_in_scale_0 = {1'b0,lut2ip_X_info_0[15:0]}; +end else if(lut2ip_Y_sel[0]) begin +if(Y_uflow_0) +Xinterp_in_scale_0 = lo_slope_uflow_scale[16:0]; +else if(Y_oflow_0) +Xinterp_in_scale_0 = lo_slope_oflow_scale[16:0]; +else +Xinterp_in_scale_0 = {1'b0,lut2ip_X_info_0[15:0]}; +end else +Xinterp_in_scale_0 = 17'd0; +end + +always @(*) begin +if(lut2ip_X_sel[0]) begin +if(X_uflow_0) +Xinterp_in_shift_0 = {{1{reg2dp_lut_le_slope_uflow_shift_sync[4]}}, reg2dp_lut_le_slope_uflow_shift_sync[4:0]}; +else if(X_oflow_0) +Xinterp_in_shift_0 = {{1{reg2dp_lut_le_slope_oflow_shift_sync[4]}}, reg2dp_lut_le_slope_oflow_shift_sync[4:0]}; +else +Xinterp_in_shift_0 = {1'b0,5'd16}; +end else if(lut2ip_Y_sel[0]) begin +if(Y_uflow_0) +Xinterp_in_shift_0 = {{1{reg2dp_lut_lo_slope_uflow_shift_sync[4]}}, reg2dp_lut_lo_slope_uflow_shift_sync[4:0]}; +else if(Y_oflow_0) +Xinterp_in_shift_0 = {{1{reg2dp_lut_lo_slope_oflow_shift_sync[4]}}, reg2dp_lut_lo_slope_oflow_shift_sync[4:0]}; +else +Xinterp_in_shift_0 = {1'b0,5'd16}; +end else +Xinterp_in_shift_0 = 6'd0; +end + +assign Xinterp_in_vld[0] = intp_in_pvld & info_in_rdy + +; + +NV_NVDLA_CDP_DP_INTP_unit u_interp_X0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.interp_in0_pd (Xinterp_in0_pd_0[38:0]) +,.interp_in1_pd (Xinterp_in1_pd_0[37:0]) +,.interp_in_pd (Xinterp_in_pd_0[16:0]) +,.interp_in_scale (Xinterp_in_scale_0[16:0]) +,.interp_in_shift (Xinterp_in_shift_0[5:0]) +,.interp_in_vld (Xinterp_in_vld[0]) +,.interp_out_rdy (Xinterp_out_rdy[0]) +,.interp_in_rdy (Xinterp_in_rdy[0]) +,.interp_out_pd (Xinterp_out_pd_0[16:0]) +,.interp_out_vld (Xinterp_out_vld[0]) +); + +assign Xinterp_out_rdy[0] = intp_prdy & info_o_vld + +; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign info_o_rdy = intp_prdy & ((&Xinterp_out_vld)); +/////////////////////////////////////////////// +//process for normal uflow/oflow info +assign info_in_vld = intp_in_pvld & (&Xinterp_in_rdy); +assign info_Xin_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m - 1; +//: print qq( +//: lut2ip_X_info_${i}[17:16], +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + lut2ip_X_info_0[17:16]}; +assign info_Yin_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m - 1; +//: print qq( +//: lut2ip_X_info_${i}[19:18], +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + lut2ip_X_info_0[19:18]}; +assign dat_info_in = {info_Yin_pd,info_Xin_pd}; +assign info_in_pd = dat_info_in; +NV_NVDLA_CDP_DP_intpinfo_fifo u_intpinfo_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intpinfo_wr_prdy (info_in_rdy) //|> w + ,.intpinfo_wr_pvld (info_in_vld) //|< w +//,.intpinfo_wr_pd ({48'd0,info_in_pd}) //|< w + ,.intpinfo_wr_pd (info_in_pd) //|< w + ,.intpinfo_rd_prdy (info_o_rdy) //|< w + ,.intpinfo_rd_pvld (info_o_vld) //|> w + ,.intpinfo_rd_pd (info_o_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign X_info_$m = info_o_pd[${m}*2+1:${m}*2]; +//: assign Y_info_$m = info_o_pd[${k}*2+${m}*2+1:${k}*2+${m}*2]; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign X_info_0 = info_o_pd[0*2+1:0*2]; +assign Y_info_0 = info_o_pd[1*2+0*2+1:1*2+0*2]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////// +assign intp_pvld = info_o_vld & ((&Xinterp_out_vld)); +assign intp_prdy = ~intp_pvld_d | intp_prdy_d; +//////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intp_pvld_d <= 1'b0; + end else begin + if(intp_pvld) + intp_pvld_d <= 1'b1; + else if(intp_prdy_d) + intp_pvld_d <= 1'b0; + end +end +//assign intp_prdy_d = ip2mul_prdy; +assign ip2mul_pvld = intp_pvld_d; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: ip2mul_pd_$m <= {17{1'b0}}; +//: end else if(intp_pvld & intp_prdy) begin +//: ip2mul_pd_$m <= Xinterp_out_pd_$m; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +ip2mul_pd_0 <= {17{1'b0}}; +end else if(intp_pvld & intp_prdy) begin +ip2mul_pd_0 <= Xinterp_out_pd_0; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////// +//LUT perf counters +//////////////////////////////////////////////// +assign layer_done = dp2reg_done; +//: my $k = 1; +//: foreach my $i (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: both_hybrid_flag[$i] <= 1'b0; +//: both_of_flag[$i] <= 1'b0; +//: both_uf_flag[$i] <= 1'b0; +//: only_le_hit[$i] <= 1'b0; +//: only_lo_hit[$i] <= 1'b0; +//: end else begin +//: if(intp_pvld & intp_prdy) begin +//: both_hybrid_flag[$i] <= ({X_info_$i,Y_info_$i} == 4'b0000) | ({X_info_$i,Y_info_$i} == 4'b0110) | ({X_info_$i,Y_info_$i} == 4'b1001); +//: both_of_flag[$i] <= ({X_info_$i,Y_info_$i} == 4'b1010); +//: both_uf_flag[$i] <= ({X_info_$i,Y_info_$i} == 4'b0101); +//: only_le_hit[$i] <= ({X_info_$i,Y_info_$i} == 4'b0001) | ({X_info_$i,Y_info_$i} == 4'b0010); +//: only_lo_hit[$i] <= ({X_info_$i,Y_info_$i} == 4'b0100) | ({X_info_$i,Y_info_$i} == 4'b1000); +//: end +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +both_hybrid_flag[0] <= 1'b0; +both_of_flag[0] <= 1'b0; +both_uf_flag[0] <= 1'b0; +only_le_hit[0] <= 1'b0; +only_lo_hit[0] <= 1'b0; +end else begin +if(intp_pvld & intp_prdy) begin +both_hybrid_flag[0] <= ({X_info_0,Y_info_0} == 4'b0000) | ({X_info_0,Y_info_0} == 4'b0110) | ({X_info_0,Y_info_0} == 4'b1001); +both_of_flag[0] <= ({X_info_0,Y_info_0} == 4'b1010); +both_uf_flag[0] <= ({X_info_0,Y_info_0} == 4'b0101); +only_le_hit[0] <= ({X_info_0,Y_info_0} == 4'b0001) | ({X_info_0,Y_info_0} == 4'b0010); +only_lo_hit[0] <= ({X_info_0,Y_info_0} == 4'b0100) | ({X_info_0,Y_info_0} == 4'b1000); +end +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +function [3:0] fun_bit_sum_8; + input [7:0] idata; + reg [3:0] ocnt; + begin + ocnt = + (( idata[0] + + idata[1] + + idata[2] ) + + ( idata[3] + + idata[4] + + idata[5] )) + + ( idata[6] + + idata[7] ) ; + fun_bit_sum_8 = ocnt; + end +endfunction +assign both_hybrid_ele = fun_bit_sum_8({{(8-1){1'b0}},both_hybrid_flag}); +assign both_of_ele = fun_bit_sum_8({{(8-1){1'b0}},both_of_flag}); +assign both_uf_ele = fun_bit_sum_8({{(8-1){1'b0}},both_uf_flag}); +assign only_le_hit_ele = fun_bit_sum_8({{(8-1){1'b0}},only_le_hit}); +assign only_lo_hit_ele = fun_bit_sum_8({{(8-1){1'b0}},only_lo_hit}); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + both_hybrid_counter <= {32{1'b0}}; + both_of_counter <= {32{1'b0}}; + both_uf_counter <= {32{1'b0}}; + only_le_hit_counter <= {32{1'b0}}; + only_lo_hit_counter <= {32{1'b0}}; + end else begin + if(layer_done) begin + both_hybrid_counter <= 32'd0; + both_of_counter <= 32'd0; + both_uf_counter <= 32'd0; + only_le_hit_counter <= 32'd0; + only_lo_hit_counter <= 32'd0; + end else if(intp_pvld_d & intp_prdy_d) begin + both_hybrid_counter <= mon_both_hybrid_counter_nxt ? 32'hffff_ffff : both_hybrid_counter_nxt ; + both_of_counter <= mon_both_of_counter_nxt ? 32'hffff_ffff : both_of_counter_nxt ; + both_uf_counter <= mon_both_uf_counter_nxt ? 32'hffff_ffff : both_uf_counter_nxt ; + only_le_hit_counter <= mon_only_le_hit_counter_nxt ? 32'hffff_ffff : only_le_hit_counter_nxt ; + only_lo_hit_counter <= mon_only_lo_hit_counter_nxt ? 32'hffff_ffff : only_lo_hit_counter_nxt ; + end + end +end +assign {mon_both_hybrid_counter_nxt ,both_hybrid_counter_nxt[31:0]} = both_hybrid_counter + both_hybrid_ele; +assign {mon_both_of_counter_nxt ,both_of_counter_nxt[31:0] } = both_of_counter + both_of_ele ; +assign {mon_both_uf_counter_nxt ,both_uf_counter_nxt[31:0] } = both_uf_counter + both_uf_ele ; +assign {mon_only_le_hit_counter_nxt ,only_le_hit_counter_nxt[31:0]} = only_le_hit_counter + only_le_hit_ele ; +assign {mon_only_lo_hit_counter_nxt ,only_lo_hit_counter_nxt[31:0]} = only_lo_hit_counter + only_lo_hit_ele ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flg <= 1'b0; + end else begin + if ((layer_done) == 1'b1) begin + layer_flg <= ~layer_flg; +// VCS coverage off + end else if ((layer_done) == 1'b0) begin + end else begin + layer_flg <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_hybrid <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_hybrid <= both_hybrid_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_hybrid <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_hybrid <= both_hybrid_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_oflow <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_oflow <= both_of_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_oflow <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_oflow <= both_of_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_uflow <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_uflow <= both_uf_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_uflow <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_uflow <= both_uf_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_le_hit <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_le_hit <= only_le_hit_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_le_hit <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_le_hit <= only_le_hit_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_lo_hit <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_lo_hit <= only_lo_hit_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_lo_hit <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_lo_hit <= only_lo_hit_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////// +//intp output pipe sync for timing +//////////////////////////////////////////////// +assign ip2mul_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print qq( +//: ip2mul_pd_${i}[16:0], +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +ip2mul_pd_0[16:0]}; +////////::pipe -bc -is intp2mul_pd(intp2mul_pvld,intp2mul_prdy) <= ip2mul_pd(ip2mul_pvld,ip2mul_prdy); +//: my $k = 1*17; +//: &eperl::pipe(" -wid $k -is -do intp2mul_pd -vo intp2mul_pvld -ri intp2mul_prdy -di ip2mul_pd -vi ip2mul_pvld -ro ip2mul_prdy "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg ip2mul_prdy; +reg skid_flop_ip2mul_prdy; +reg skid_flop_ip2mul_pvld; +reg [17-1:0] skid_flop_ip2mul_pd; +reg pipe_skid_ip2mul_pvld; +reg [17-1:0] pipe_skid_ip2mul_pd; +// Wire +wire skid_ip2mul_pvld; +wire [17-1:0] skid_ip2mul_pd; +wire skid_ip2mul_prdy; +wire pipe_skid_ip2mul_prdy; +wire intp2mul_pvld; +wire [17-1:0] intp2mul_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ip2mul_prdy <= 1'b1; + skid_flop_ip2mul_prdy <= 1'b1; + end else begin + ip2mul_prdy <= skid_ip2mul_prdy; + skid_flop_ip2mul_prdy <= skid_ip2mul_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_ip2mul_pvld <= 1'b0; + end else begin + if (skid_flop_ip2mul_prdy) begin + skid_flop_ip2mul_pvld <= ip2mul_pvld; + end + end +end +assign skid_ip2mul_pvld = (skid_flop_ip2mul_prdy) ? ip2mul_pvld : skid_flop_ip2mul_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_ip2mul_prdy & ip2mul_pvld) begin + skid_flop_ip2mul_pd[17-1:0] <= ip2mul_pd[17-1:0]; + end +end +assign skid_ip2mul_pd[17-1:0] = (skid_flop_ip2mul_prdy) ? ip2mul_pd[17-1:0] : skid_flop_ip2mul_pd[17-1:0]; + + +// PIPE READY +assign skid_ip2mul_prdy = pipe_skid_ip2mul_prdy || !pipe_skid_ip2mul_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_ip2mul_pvld <= 1'b0; + end else begin + if (skid_ip2mul_prdy) begin + pipe_skid_ip2mul_pvld <= skid_ip2mul_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_ip2mul_prdy && skid_ip2mul_pvld) begin + pipe_skid_ip2mul_pd[17-1:0] <= skid_ip2mul_pd[17-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_ip2mul_prdy = intp2mul_prdy; +assign intp2mul_pvld = pipe_skid_ip2mul_pvld; +assign intp2mul_pd = pipe_skid_ip2mul_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign intp_prdy_d = ip2mul_prdy; +assign { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print qq( +//: intp2mul_pd_${i}[16:0], +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +intp2mul_pd_0[16:0]} = intp2mul_pd; +//////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_intp +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_DP_intpinfo_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus intpinfo_wr -rd_pipebus intpinfo_rd -rd_reg -ram_bypass -d 19 -w 80 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_intpinfo_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intpinfo_wr_prdy + , intpinfo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , intpinfo_wr_pause +`endif + , intpinfo_wr_pd + , intpinfo_rd_prdy + , intpinfo_rd_pvld + , intpinfo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output intpinfo_wr_prdy; +input intpinfo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input intpinfo_wr_pause; +`endif +input [3:0] intpinfo_wr_pd; +input intpinfo_rd_prdy; +output intpinfo_rd_pvld; +output [3:0] intpinfo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg intpinfo_wr_busy_int; // copy for internal use +assign intpinfo_wr_prdy = !intpinfo_wr_busy_int; +assign wr_reserving = intpinfo_wr_pvld && !intpinfo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [4:0] intpinfo_wr_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? intpinfo_wr_count : (intpinfo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (intpinfo_wr_count + 1'd1) : intpinfo_wr_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_19 = ( wr_count_next_no_wr_popping == 5'd19 ); +wire wr_count_next_is_19 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_19; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire intpinfo_wr_busy_next = wr_count_next_is_19 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check intpinfo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || intpinfo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire intpinfo_wr_busy_next = wr_count_next_is_19 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check intpinfo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_wr_busy_int <= 1'b0; + intpinfo_wr_count <= 5'd0; + end else begin + intpinfo_wr_busy_int <= intpinfo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + intpinfo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + intpinfo_wr_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as intpinfo_wr_pvld +// +// RAM +// +reg [4:0] intpinfo_wr_adr; // current write address +wire [4:0] intpinfo_rd_adr_p; // read address to use for ram +wire [3:0] intpinfo_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_19x4 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( intpinfo_wr_adr ) + , .we ( wr_pushing && (intpinfo_wr_count != 5'd0 || !rd_popping) ) + , .di ( intpinfo_wr_pd ) + , .ra ( intpinfo_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( intpinfo_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( intpinfo_wr_pd[3:0] ) + , .ore ( ore ) + ); +// next intpinfo_wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = (intpinfo_wr_adr == 5'd18) ? 5'd0 : (intpinfo_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + intpinfo_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + intpinfo_wr_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [4:0] intpinfo_rd_adr; // current read address +// next read address +wire [4:0] rd_adr_next = (intpinfo_rd_adr == 5'd18) ? 5'd0 : (intpinfo_rd_adr + 1'd1); // spyglass disable W484 +assign intpinfo_rd_adr_p = rd_popping ? rd_adr_next : intpinfo_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + intpinfo_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + intpinfo_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (intpinfo_wr_adr == rd_adr_next) : (intpinfo_wr_adr == intpinfo_rd_adr)); +wire [3:0] intpinfo_rd_pd_p_byp = intpinfo_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = intpinfo_wr_count == 0; +wire [3:0] intpinfo_rd_pd_p = intpinfo_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire intpinfo_rd_pvld_p; // data out of fifo is valid +reg intpinfo_rd_pvld_int; // internal copy of intpinfo_rd_pvld +assign intpinfo_rd_pvld = intpinfo_rd_pvld_int; +assign rd_popping = intpinfo_rd_pvld_p && !(intpinfo_rd_pvld_int && !intpinfo_rd_prdy); +reg [4:0] intpinfo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? intpinfo_rd_count_p : + (intpinfo_rd_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (intpinfo_rd_count_p + 1'd1) : + intpinfo_rd_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign intpinfo_rd_pvld_p = intpinfo_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~intpinfo_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_rd_count_p <= 5'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + intpinfo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + intpinfo_rd_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (intpinfo_rd_pvld_p || (intpinfo_rd_pvld_int && !intpinfo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_rd_pvld_int <= 1'b0; + end else begin + intpinfo_rd_pvld_int <= rd_req_next; + end +end +assign intpinfo_rd_pd = intpinfo_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (intpinfo_wr_pvld && !intpinfo_wr_busy_int) || (intpinfo_wr_busy_int != intpinfo_wr_busy_next)) || (rd_pushing || rd_popping || (intpinfo_rd_pvld_int && intpinfo_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( intpinfo_wr_pvld && !(!intpinfo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd19 : wr_limit_reg} ) + , .curr ( {27'd0, intpinfo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_intpinfo_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_intpinfo_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v.vcp new file mode 100644 index 0000000..663f948 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v.vcp @@ -0,0 +1,2045 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_intp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_intp ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2reg_done //|< i + ,intp2mul_prdy //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,lut2intp_X_data_${m}0 //|> o +//: ,lut2intp_X_data_${m}0_17b //|> o +//: ,lut2intp_X_data_${m}1 //|> o +//: ,lut2intp_X_info_${m} //|> o +//: ); +//: } + ,lut2intp_X_sel //|< i + ,lut2intp_Y_sel //|< i + ,lut2intp_pvld //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_lut_le_end_high //|< i + ,reg2dp_lut_le_end_low //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_slope_oflow_scale //|< i + ,reg2dp_lut_le_slope_oflow_shift //|< i + ,reg2dp_lut_le_slope_uflow_scale //|< i + ,reg2dp_lut_le_slope_uflow_shift //|< i + ,reg2dp_lut_le_start_high //|< i + ,reg2dp_lut_le_start_low //|< i + ,reg2dp_lut_lo_end_high //|< i + ,reg2dp_lut_lo_end_low //|< i + ,reg2dp_lut_lo_slope_oflow_scale //|< i + ,reg2dp_lut_lo_slope_oflow_shift //|< i + ,reg2dp_lut_lo_slope_uflow_scale //|< i + ,reg2dp_lut_lo_slope_uflow_shift //|< i + ,reg2dp_lut_lo_start_high //|< i + ,reg2dp_lut_lo_start_low //|< i + ,reg2dp_sqsum_bypass //|< i + ,sync2itp_pd //|< i + ,sync2itp_pvld //|< i + ,dp2reg_d0_perf_lut_hybrid //|> o + ,dp2reg_d0_perf_lut_le_hit //|> o + ,dp2reg_d0_perf_lut_lo_hit //|> o + ,dp2reg_d0_perf_lut_oflow //|> o + ,dp2reg_d0_perf_lut_uflow //|> o + ,dp2reg_d1_perf_lut_hybrid //|> o + ,dp2reg_d1_perf_lut_le_hit //|> o + ,dp2reg_d1_perf_lut_lo_hit //|> o + ,dp2reg_d1_perf_lut_oflow //|> o + ,dp2reg_d1_perf_lut_uflow //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,intp2mul_pd_$m //|> o +//: ); +//: } + ,intp2mul_pvld //|> o + ,lut2intp_prdy //|> o + ,sync2itp_prdy //|> o + ); +////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input intp2mul_prdy; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: input [31:0] lut2intp_X_data_${m}0; +//: input [16:0] lut2intp_X_data_${m}0_17b; +//: input [31:0] lut2intp_X_data_${m}1; +//: input [19:0] lut2intp_X_info_${m}; +//: ); +//: } +input [1 -1:0] lut2intp_X_sel; +input [1 -1:0] lut2intp_Y_sel; +input lut2intp_pvld; +input [31:0] pwrbus_ram_pd; +input [5:0] reg2dp_lut_le_end_high; +input [31:0] reg2dp_lut_le_end_low; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [15:0] reg2dp_lut_le_slope_oflow_scale; +input [4:0] reg2dp_lut_le_slope_oflow_shift; +input [15:0] reg2dp_lut_le_slope_uflow_scale; +input [4:0] reg2dp_lut_le_slope_uflow_shift; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [5:0] reg2dp_lut_lo_end_high; +input [31:0] reg2dp_lut_lo_end_low; +input [15:0] reg2dp_lut_lo_slope_oflow_scale; +input [4:0] reg2dp_lut_lo_slope_oflow_shift; +input [15:0] reg2dp_lut_lo_slope_uflow_scale; +input [4:0] reg2dp_lut_lo_slope_uflow_shift; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_sqsum_bypass; +//: my $k = 1; +//: my $icvto = (8 +1); +//: print "input [${k}*(${icvto}*2+3)-1:0] sync2itp_pd; \n"; +input sync2itp_pvld; +output [31:0] dp2reg_d0_perf_lut_hybrid; +output [31:0] dp2reg_d0_perf_lut_le_hit; +output [31:0] dp2reg_d0_perf_lut_lo_hit; +output [31:0] dp2reg_d0_perf_lut_oflow; +output [31:0] dp2reg_d0_perf_lut_uflow; +output [31:0] dp2reg_d1_perf_lut_hybrid; +output [31:0] dp2reg_d1_perf_lut_le_hit; +output [31:0] dp2reg_d1_perf_lut_lo_hit; +output [31:0] dp2reg_d1_perf_lut_oflow; +output [31:0] dp2reg_d1_perf_lut_uflow; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: output [16:0] intp2mul_pd_$m; +//: ); +//: } +output intp2mul_pvld; +output lut2intp_prdy; +output sync2itp_prdy; +////////////////////////////////////////////////////////////////////// +reg X_exp; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: reg [38:0] Xinterp_in0_pd_$m; +//: reg [37:0] Xinterp_in1_pd_$m; +//: reg [16:0] Xinterp_in_pd_$m; +//: reg [16:0] Xinterp_in_scale_$m; +//: reg [5:0] Xinterp_in_shift_$m; +//: ); +//: } +reg [31:0] both_hybrid_counter; +reg [1 -1:0] both_hybrid_flag; +reg [31:0] both_of_counter; +reg [1 -1:0] both_of_flag; +reg [31:0] both_uf_counter; +reg [1 -1:0] both_uf_flag; +reg [31:0] dp2reg_d0_perf_lut_hybrid; +reg [31:0] dp2reg_d0_perf_lut_le_hit; +reg [31:0] dp2reg_d0_perf_lut_lo_hit; +reg [31:0] dp2reg_d0_perf_lut_oflow; +reg [31:0] dp2reg_d0_perf_lut_uflow; +reg [31:0] dp2reg_d1_perf_lut_hybrid; +reg [31:0] dp2reg_d1_perf_lut_le_hit; +reg [31:0] dp2reg_d1_perf_lut_lo_hit; +reg [31:0] dp2reg_d1_perf_lut_oflow; +reg [31:0] dp2reg_d1_perf_lut_uflow; +//reg [1*17-1:0] intp2mul_pd; +//reg intp2mul_pvld; +reg intp_pvld_d; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: reg [16:0] ip2mul_pd_$m; +//: ); +//: } +//reg ip2mul_prdy; +reg layer_flg; +//reg [1*103-1:0] lut2intp_data; +//reg lut2intp_prdy; +//reg lut2intp_valid; +reg [37:0] lut_le_max; +reg [38:0] lut_le_min; +reg [37:0] lut_lo_max; +reg [37:0] lut_lo_min; +reg [1 -1:0] only_le_hit; +reg [31:0] only_le_hit_counter; +reg [1 -1:0] only_lo_hit; +reg [31:0] only_lo_hit_counter; +reg [15:0] reg2dp_lut_le_slope_oflow_scale_sync; +reg [4:0] reg2dp_lut_le_slope_oflow_shift_sync; +reg [15:0] reg2dp_lut_le_slope_uflow_scale_sync; +reg [4:0] reg2dp_lut_le_slope_uflow_shift_sync; +reg [15:0] reg2dp_lut_lo_slope_oflow_scale_sync; +reg [4:0] reg2dp_lut_lo_slope_oflow_shift_sync; +reg [15:0] reg2dp_lut_lo_slope_uflow_scale_sync; +reg [4:0] reg2dp_lut_lo_slope_uflow_shift_sync; +reg sqsum_bypass_enable; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [1:0] X_info_$m; +//: wire X_oflow_$m; +//: wire X_uflow_$m; +//: wire [1:0] Y_info_$m; +//: wire Y_oflow_$m; +//: wire Y_uflow_$m; +//: wire [16:0] Xinterp_out_pd_$m; +//: wire [37:0] hit_in1_pd_$m; +//: ); +//: } +wire [1 -1:0] Xinterp_in_rdy; +wire [1 -1:0] Xinterp_in_vld; +wire [1 -1:0] Xinterp_out_rdy; +wire [1 -1:0] Xinterp_out_vld; +wire [31:0] both_hybrid_counter_nxt; +wire [3:0] both_hybrid_ele; +wire [31:0] both_of_counter_nxt; +wire [3:0] both_of_ele; +wire [31:0] both_uf_counter_nxt; +wire [3:0] both_uf_ele; +wire [1*4-1:0] dat_info_in; +wire [1*2-1:0] info_Xin_pd; +wire [1*2-1:0] info_Yin_pd; +wire [1*4-1:0] info_in_pd; +wire info_in_rdy; +wire info_in_vld; +wire [1*4-1:0] info_o_pd; +wire info_o_rdy; +wire info_o_vld; +wire intp_in_prdy; +wire intp_in_pvld; +wire intp_prdy; +wire intp_prdy_d; +wire intp_pvld; +wire [1*17-1:0] ip2mul_pd; +wire ip2mul_pvld; +wire layer_done; +wire [127:0] le_offset_exp; +wire [6:0] le_offset_use; +wire [16:0] le_slope_oflow_scale; +wire [16:0] le_slope_uflow_scale; +wire [16:0] lo_slope_oflow_scale; +wire [16:0] lo_slope_uflow_scale; +wire [1*103-1:0] lut2intp_pd; +wire lut2intp_ready; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [31:0] lut2ip_X_data_${m}0; +//: wire [16:0] lut2ip_X_data_${m}0_17b; +//: wire [31:0] lut2ip_X_data_${m}1; +//: wire [19:0] lut2ip_X_info_$m; +//: ); +//: } +wire [1 -1:0] lut2ip_X_sel; +wire [1 -1:0] lut2ip_Y_sel; +wire [37:0] lut_le_end; +wire [38:0] lut_le_min_int; +wire [37:0] lut_le_start; +wire [37:0] lut_lo_end; +wire [37:0] lut_lo_start; +wire mon_both_hybrid_counter_nxt; +wire mon_both_of_counter_nxt; +wire mon_both_uf_counter_nxt; +wire [90:0] mon_lut_le_min_int; +wire mon_only_le_hit_counter_nxt; +wire mon_only_lo_hit_counter_nxt; +wire [31:0] only_le_hit_counter_nxt; +wire [3:0] only_le_hit_ele; +wire [31:0] only_lo_hit_counter_nxt; +wire [3:0] only_lo_hit_ele; +/////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + X_exp <= 1'b0; + end else begin + X_exp <= reg2dp_lut_le_function == 1'h0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sqsum_bypass_enable <= 1'b0; + end else begin + sqsum_bypass_enable <= reg2dp_sqsum_bypass == 1'h1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_uflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_le_slope_uflow_shift_sync <= reg2dp_lut_le_slope_uflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_oflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_le_slope_oflow_shift_sync <= reg2dp_lut_le_slope_oflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_uflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_lo_slope_uflow_shift_sync <= reg2dp_lut_lo_slope_uflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_oflow_shift_sync <= {5{1'b0}}; + end else begin + reg2dp_lut_lo_slope_oflow_shift_sync <= reg2dp_lut_lo_slope_oflow_shift[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_uflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_le_slope_uflow_scale_sync <= reg2dp_lut_le_slope_uflow_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_le_slope_oflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_le_slope_oflow_scale_sync <= reg2dp_lut_le_slope_oflow_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_uflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_lo_slope_uflow_scale_sync <= reg2dp_lut_lo_slope_uflow_scale[15:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_lo_slope_oflow_scale_sync <= {16{1'b0}}; + end else begin + reg2dp_lut_lo_slope_oflow_scale_sync <= reg2dp_lut_lo_slope_oflow_scale[15:0]; + end +end +/////////////////////////////////////////// +assign le_slope_uflow_scale = {reg2dp_lut_le_slope_uflow_scale_sync[15],reg2dp_lut_le_slope_uflow_scale_sync[15:0]}; +assign le_slope_oflow_scale = {reg2dp_lut_le_slope_oflow_scale_sync[15],reg2dp_lut_le_slope_oflow_scale_sync[15:0]}; +assign lo_slope_uflow_scale = {reg2dp_lut_lo_slope_uflow_scale_sync[15],reg2dp_lut_lo_slope_uflow_scale_sync[15:0]}; +assign lo_slope_oflow_scale = {reg2dp_lut_lo_slope_oflow_scale_sync[15],reg2dp_lut_lo_slope_oflow_scale_sync[15:0]}; +/////////////////////////////////////////// +//lut2intp pipe sync for timing +assign lut2intp_pd = { +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2intp_X_data_${m}0[31:0],lut2intp_X_data_${m}0_17b[16:0],lut2intp_X_data_${m}1[31:0], +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2intp_X_info_${m}[19:0], +//: ); +//: } + lut2intp_X_sel, + lut2intp_Y_sel + }; +//: my $k = 1*103; +//: &eperl::pipe(" -is -wid $k -do lut2intp_data -vo lut2intp_valid -ri lut2intp_ready -di lut2intp_pd -vi lut2intp_pvld -ro lut2intp_prdy "); +assign { +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2ip_X_data_${m}0[31:0],lut2ip_X_data_${m}0_17b[16:0],lut2ip_X_data_${m}1[31:0], +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: lut2ip_X_info_${m}[19:0], +//: ); +//: } + lut2ip_X_sel, + lut2ip_Y_sel} = lut2intp_data; +/////////////////////////////////////////// +//lock +//from lut2int and sync2itp to intp_in +assign lut2intp_ready = intp_in_prdy & sync2itp_pvld; +assign sync2itp_prdy = intp_in_prdy & lut2intp_valid; +assign intp_in_pvld = sync2itp_pvld & lut2intp_valid; +/////////////////////////////////////////// +assign intp_in_prdy = (&Xinterp_in_rdy) & info_in_rdy; +//: my $k = 1; +//: my $icvto=(8 +1); +//: my $sqbw=${icvto}*2+3; +//: foreach my $m (0..$k -1) { +//: print qq( +//: assign hit_in1_pd_$m = (sqsum_bypass_enable ? {{(38-${sqbw}){sync2itp_pd[${sqbw}*$m+${sqbw}-1]}} ,sync2itp_pd[${sqbw}*$m+${sqbw}-1:${sqbw}*$m]} : {17'd0,sync2itp_pd[${sqbw}*$m+${sqbw}-1:${sqbw}*$m] }); +//: ); +//: } +///////////////////////////////////////////////// +//start/end prepare for out of range interpolation +///////////////////////////////////////////////// +assign lut_le_end[37:0] = {reg2dp_lut_le_end_high[5:0],reg2dp_lut_le_end_low[31:0]}; +assign lut_le_start[37:0] = {reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:0]}; +assign lut_lo_end[37:0] = {reg2dp_lut_lo_end_high[5:0],reg2dp_lut_lo_end_low[31:0]}; +assign lut_lo_start[37:0] = {reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:0]}; +assign le_offset_use = reg2dp_lut_le_index_offset[6:0]; +assign le_offset_exp[127:0] = reg2dp_lut_le_index_offset[7] ? 128'd0 : (1'b1 << le_offset_use); +assign {mon_lut_le_min_int[90:0],lut_le_min_int[38:0]} = X_exp ? ($signed({{91{lut_le_start[37]}}, lut_le_start[37:0]}) + $signed({1'b0,le_offset_exp})) : {{92{lut_le_start[37]}}, lut_le_start[37:0]}; +// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_le_max[37:0] <= {38{1'b0}}; + end else begin + lut_le_max[37:0] <= lut_le_end; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_le_min[38:0] <= {39{1'b0}}; + end else begin + lut_le_min[38:0] <= lut_le_min_int; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_lo_max[37:0] <= {38{1'b0}}; + end else begin + lut_lo_max[37:0] <= lut_lo_end; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_lo_min[37:0] <= {38{1'b0}}; + end else begin + lut_lo_min[37:0] <= lut_lo_start; + end +end +///////////////////////////////////////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign X_uflow_${m} = lut2ip_X_info_${m}[16]; +//: assign X_oflow_${m} = lut2ip_X_info_${m}[17]; +//: assign Y_uflow_${m} = lut2ip_X_info_${m}[18]; +//: assign Y_oflow_${m} = lut2ip_X_info_${m}[19]; +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m) +//: Xinterp_in0_pd_$m = lut_le_min[38:0]; +//: else if(X_oflow_$m) +//: Xinterp_in0_pd_$m = {lut_le_max[37],lut_le_max[37:0]}; +//: else +//: Xinterp_in0_pd_$m = {{7{lut2ip_X_data_${m}0[31]}},lut2ip_X_data_${m}0[31:0]}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m) +//: Xinterp_in0_pd_$m = {lut_lo_min[37],lut_lo_min[37:0]}; +//: else if(Y_oflow_$m) +//: Xinterp_in0_pd_$m = {lut_lo_max[37],lut_lo_max[37:0]}; +//: else +//: Xinterp_in0_pd_$m = {{7{lut2ip_X_data_${m}0[31]}},lut2ip_X_data_${m}0[31:0]}; +//: end else +//: Xinterp_in0_pd_$m = 39'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m | X_oflow_$m) +//: Xinterp_in1_pd_$m = hit_in1_pd_$m; +//: else +//: Xinterp_in1_pd_$m = {{6{lut2ip_X_data_${m}1[31]}},lut2ip_X_data_${m}1[31:0]}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m | Y_oflow_$m) +//: Xinterp_in1_pd_$m = hit_in1_pd_$m; +//: else +//: Xinterp_in1_pd_$m = {{6{lut2ip_X_data_${m}1[31]}},lut2ip_X_data_${m}1[31:0]}; +//: end else +//: Xinterp_in1_pd_$m = 38'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m] | lut2ip_Y_sel[$m]) +//: Xinterp_in_pd_$m = lut2ip_X_data_${m}0_17b[16:0]; +//: else +//: Xinterp_in_pd_$m = 17'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m) +//: Xinterp_in_scale_$m = le_slope_uflow_scale[16:0]; +//: else if(X_oflow_$m) +//: Xinterp_in_scale_$m = le_slope_oflow_scale[16:0]; +//: else +//: Xinterp_in_scale_$m = {1'b0,lut2ip_X_info_${m}[15:0]}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m) +//: Xinterp_in_scale_$m = lo_slope_uflow_scale[16:0]; +//: else if(Y_oflow_$m) +//: Xinterp_in_scale_$m = lo_slope_oflow_scale[16:0]; +//: else +//: Xinterp_in_scale_$m = {1'b0,lut2ip_X_info_${m}[15:0]}; +//: end else +//: Xinterp_in_scale_$m = 17'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: if(lut2ip_X_sel[$m]) begin +//: if(X_uflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_le_slope_uflow_shift_sync[4]}}, reg2dp_lut_le_slope_uflow_shift_sync[4:0]}; +//: else if(X_oflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_le_slope_oflow_shift_sync[4]}}, reg2dp_lut_le_slope_oflow_shift_sync[4:0]}; +//: else +//: Xinterp_in_shift_$m = {1'b0,5'd16}; +//: end else if(lut2ip_Y_sel[$m]) begin +//: if(Y_uflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_lo_slope_uflow_shift_sync[4]}}, reg2dp_lut_lo_slope_uflow_shift_sync[4:0]}; +//: else if(Y_oflow_$m) +//: Xinterp_in_shift_$m = {{1{reg2dp_lut_lo_slope_oflow_shift_sync[4]}}, reg2dp_lut_lo_slope_oflow_shift_sync[4:0]}; +//: else +//: Xinterp_in_shift_$m = {1'b0,5'd16}; +//: end else +//: Xinterp_in_shift_$m = 6'd0; +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign Xinterp_in_vld[$m] = intp_in_pvld & info_in_rdy +//: ); +//: foreach my $i (0..$k-1) { +//: if($i != $m) { +//: print qq( +//: & Xinterp_in_rdy[$i] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: NV_NVDLA_CDP_DP_INTP_unit u_interp_X$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.interp_in0_pd (Xinterp_in0_pd_${m}[38:0]) +//: ,.interp_in1_pd (Xinterp_in1_pd_${m}[37:0]) +//: ,.interp_in_pd (Xinterp_in_pd_${m}[16:0]) +//: ,.interp_in_scale (Xinterp_in_scale_${m}[16:0]) +//: ,.interp_in_shift (Xinterp_in_shift_${m}[5:0]) +//: ,.interp_in_vld (Xinterp_in_vld[$m]) +//: ,.interp_out_rdy (Xinterp_out_rdy[$m]) +//: ,.interp_in_rdy (Xinterp_in_rdy[$m]) +//: ,.interp_out_pd (Xinterp_out_pd_${m}[16:0]) +//: ,.interp_out_vld (Xinterp_out_vld[$m]) +//: ); +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign Xinterp_out_rdy[$m] = intp_prdy & info_o_vld +//: ); +//: foreach my $i (0..$k-1) { +//: if($i != $m) { +//: print qq( +//: & Xinterp_out_vld[$i] +//: ); +//: } +//: } +//: print qq( +//: ; +//: ); +//: } +assign info_o_rdy = intp_prdy & ((&Xinterp_out_vld)); +/////////////////////////////////////////////// +//process for normal uflow/oflow info +assign info_in_vld = intp_in_pvld & (&Xinterp_in_rdy); +assign info_Xin_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m - 1; +//: print qq( +//: lut2ip_X_info_${i}[17:16], +//: ); +//: } +//: } + lut2ip_X_info_0[17:16]}; +assign info_Yin_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m - 1; +//: print qq( +//: lut2ip_X_info_${i}[19:18], +//: ); +//: } +//: } + lut2ip_X_info_0[19:18]}; +assign dat_info_in = {info_Yin_pd,info_Xin_pd}; +assign info_in_pd = dat_info_in; +NV_NVDLA_CDP_DP_intpinfo_fifo u_intpinfo_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intpinfo_wr_prdy (info_in_rdy) //|> w + ,.intpinfo_wr_pvld (info_in_vld) //|< w +//,.intpinfo_wr_pd ({48'd0,info_in_pd}) //|< w + ,.intpinfo_wr_pd (info_in_pd) //|< w + ,.intpinfo_rd_prdy (info_o_rdy) //|< w + ,.intpinfo_rd_pvld (info_o_vld) //|> w + ,.intpinfo_rd_pd (info_o_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign X_info_$m = info_o_pd[${m}*2+1:${m}*2]; +//: assign Y_info_$m = info_o_pd[${k}*2+${m}*2+1:${k}*2+${m}*2]; +//: ); +//: } +//////////////////////////////////////////////// +assign intp_pvld = info_o_vld & ((&Xinterp_out_vld)); +assign intp_prdy = ~intp_pvld_d | intp_prdy_d; +//////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intp_pvld_d <= 1'b0; + end else begin + if(intp_pvld) + intp_pvld_d <= 1'b1; + else if(intp_prdy_d) + intp_pvld_d <= 1'b0; + end +end +//assign intp_prdy_d = ip2mul_prdy; +assign ip2mul_pvld = intp_pvld_d; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: ip2mul_pd_$m <= {17{1'b0}}; +//: end else if(intp_pvld & intp_prdy) begin +//: ip2mul_pd_$m <= Xinterp_out_pd_$m; +//: end +//: end +//: ); +//: } +//////////////////////////////////////////////// +//LUT perf counters +//////////////////////////////////////////////// +assign layer_done = dp2reg_done; +//: my $k = 1; +//: foreach my $i (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: both_hybrid_flag[$i] <= 1'b0; +//: both_of_flag[$i] <= 1'b0; +//: both_uf_flag[$i] <= 1'b0; +//: only_le_hit[$i] <= 1'b0; +//: only_lo_hit[$i] <= 1'b0; +//: end else begin +//: if(intp_pvld & intp_prdy) begin +//: both_hybrid_flag[$i] <= ({X_info_$i,Y_info_$i} == 4'b0000) | ({X_info_$i,Y_info_$i} == 4'b0110) | ({X_info_$i,Y_info_$i} == 4'b1001); +//: both_of_flag[$i] <= ({X_info_$i,Y_info_$i} == 4'b1010); +//: both_uf_flag[$i] <= ({X_info_$i,Y_info_$i} == 4'b0101); +//: only_le_hit[$i] <= ({X_info_$i,Y_info_$i} == 4'b0001) | ({X_info_$i,Y_info_$i} == 4'b0010); +//: only_lo_hit[$i] <= ({X_info_$i,Y_info_$i} == 4'b0100) | ({X_info_$i,Y_info_$i} == 4'b1000); +//: end +//: end +//: end +//: ); +//: } +function [3:0] fun_bit_sum_8; + input [7:0] idata; + reg [3:0] ocnt; + begin + ocnt = + (( idata[0] + + idata[1] + + idata[2] ) + + ( idata[3] + + idata[4] + + idata[5] )) + + ( idata[6] + + idata[7] ) ; + fun_bit_sum_8 = ocnt; + end +endfunction +assign both_hybrid_ele = fun_bit_sum_8({{(8-1){1'b0}},both_hybrid_flag}); +assign both_of_ele = fun_bit_sum_8({{(8-1){1'b0}},both_of_flag}); +assign both_uf_ele = fun_bit_sum_8({{(8-1){1'b0}},both_uf_flag}); +assign only_le_hit_ele = fun_bit_sum_8({{(8-1){1'b0}},only_le_hit}); +assign only_lo_hit_ele = fun_bit_sum_8({{(8-1){1'b0}},only_lo_hit}); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + both_hybrid_counter <= {32{1'b0}}; + both_of_counter <= {32{1'b0}}; + both_uf_counter <= {32{1'b0}}; + only_le_hit_counter <= {32{1'b0}}; + only_lo_hit_counter <= {32{1'b0}}; + end else begin + if(layer_done) begin + both_hybrid_counter <= 32'd0; + both_of_counter <= 32'd0; + both_uf_counter <= 32'd0; + only_le_hit_counter <= 32'd0; + only_lo_hit_counter <= 32'd0; + end else if(intp_pvld_d & intp_prdy_d) begin + both_hybrid_counter <= mon_both_hybrid_counter_nxt ? 32'hffff_ffff : both_hybrid_counter_nxt ; + both_of_counter <= mon_both_of_counter_nxt ? 32'hffff_ffff : both_of_counter_nxt ; + both_uf_counter <= mon_both_uf_counter_nxt ? 32'hffff_ffff : both_uf_counter_nxt ; + only_le_hit_counter <= mon_only_le_hit_counter_nxt ? 32'hffff_ffff : only_le_hit_counter_nxt ; + only_lo_hit_counter <= mon_only_lo_hit_counter_nxt ? 32'hffff_ffff : only_lo_hit_counter_nxt ; + end + end +end +assign {mon_both_hybrid_counter_nxt ,both_hybrid_counter_nxt[31:0]} = both_hybrid_counter + both_hybrid_ele; +assign {mon_both_of_counter_nxt ,both_of_counter_nxt[31:0] } = both_of_counter + both_of_ele ; +assign {mon_both_uf_counter_nxt ,both_uf_counter_nxt[31:0] } = both_uf_counter + both_uf_ele ; +assign {mon_only_le_hit_counter_nxt ,only_le_hit_counter_nxt[31:0]} = only_le_hit_counter + only_le_hit_ele ; +assign {mon_only_lo_hit_counter_nxt ,only_lo_hit_counter_nxt[31:0]} = only_lo_hit_counter + only_lo_hit_ele ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flg <= 1'b0; + end else begin + if ((layer_done) == 1'b1) begin + layer_flg <= ~layer_flg; +// VCS coverage off + end else if ((layer_done) == 1'b0) begin + end else begin + layer_flg <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_hybrid <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_hybrid <= both_hybrid_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_hybrid <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_hybrid <= both_hybrid_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_oflow <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_oflow <= both_of_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_oflow <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_oflow <= both_of_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_uflow <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_uflow <= both_uf_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_uflow <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_uflow <= both_uf_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_le_hit <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_le_hit <= only_le_hit_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_le_hit <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_le_hit <= only_le_hit_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_lut_lo_hit <= {32{1'b0}}; + end else begin + if ((layer_done & (~layer_flg)) == 1'b1) begin + dp2reg_d0_perf_lut_lo_hit <= only_lo_hit_counter; +// VCS coverage off + end else if ((layer_done & (~layer_flg)) == 1'b0) begin + end else begin + dp2reg_d0_perf_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & (~layer_flg)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_lut_lo_hit <= {32{1'b0}}; + end else begin + if ((layer_done & layer_flg ) == 1'b1) begin + dp2reg_d1_perf_lut_lo_hit <= only_lo_hit_counter; +// VCS coverage off + end else if ((layer_done & layer_flg ) == 1'b0) begin + end else begin + dp2reg_d1_perf_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(layer_done & layer_flg ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////// +//intp output pipe sync for timing +//////////////////////////////////////////////// +assign ip2mul_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print qq( +//: ip2mul_pd_${i}[16:0], +//: ); +//: } +//: } +ip2mul_pd_0[16:0]}; +////////::pipe -bc -is intp2mul_pd(intp2mul_pvld,intp2mul_prdy) <= ip2mul_pd(ip2mul_pvld,ip2mul_prdy); +//: my $k = 1*17; +//: &eperl::pipe(" -wid $k -is -do intp2mul_pd -vo intp2mul_pvld -ri intp2mul_prdy -di ip2mul_pd -vi ip2mul_pvld -ro ip2mul_prdy "); +assign intp_prdy_d = ip2mul_prdy; +assign { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print qq( +//: intp2mul_pd_${i}[16:0], +//: ); +//: } +//: } +intp2mul_pd_0[16:0]} = intp2mul_pd; +//////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_intp +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_DP_intpinfo_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus intpinfo_wr -rd_pipebus intpinfo_rd -rd_reg -ram_bypass -d 19 -w 80 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_intpinfo_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intpinfo_wr_prdy + , intpinfo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , intpinfo_wr_pause +`endif + , intpinfo_wr_pd + , intpinfo_rd_prdy + , intpinfo_rd_pvld + , intpinfo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output intpinfo_wr_prdy; +input intpinfo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input intpinfo_wr_pause; +`endif +input [3:0] intpinfo_wr_pd; +input intpinfo_rd_prdy; +output intpinfo_rd_pvld; +output [3:0] intpinfo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg intpinfo_wr_busy_int; // copy for internal use +assign intpinfo_wr_prdy = !intpinfo_wr_busy_int; +assign wr_reserving = intpinfo_wr_pvld && !intpinfo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [4:0] intpinfo_wr_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? intpinfo_wr_count : (intpinfo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (intpinfo_wr_count + 1'd1) : intpinfo_wr_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_19 = ( wr_count_next_no_wr_popping == 5'd19 ); +wire wr_count_next_is_19 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_19; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire intpinfo_wr_busy_next = wr_count_next_is_19 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check intpinfo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || intpinfo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire intpinfo_wr_busy_next = wr_count_next_is_19 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check intpinfo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_wr_busy_int <= 1'b0; + intpinfo_wr_count <= 5'd0; + end else begin + intpinfo_wr_busy_int <= intpinfo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + intpinfo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + intpinfo_wr_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as intpinfo_wr_pvld +// +// RAM +// +reg [4:0] intpinfo_wr_adr; // current write address +wire [4:0] intpinfo_rd_adr_p; // read address to use for ram +wire [3:0] intpinfo_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_19x4 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( intpinfo_wr_adr ) + , .we ( wr_pushing && (intpinfo_wr_count != 5'd0 || !rd_popping) ) + , .di ( intpinfo_wr_pd ) + , .ra ( intpinfo_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( intpinfo_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( intpinfo_wr_pd[3:0] ) + , .ore ( ore ) + ); +// next intpinfo_wr_adr if wr_pushing=1 +wire [4:0] wr_adr_next = (intpinfo_wr_adr == 5'd18) ? 5'd0 : (intpinfo_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + intpinfo_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + intpinfo_wr_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [4:0] intpinfo_rd_adr; // current read address +// next read address +wire [4:0] rd_adr_next = (intpinfo_rd_adr == 5'd18) ? 5'd0 : (intpinfo_rd_adr + 1'd1); // spyglass disable W484 +assign intpinfo_rd_adr_p = rd_popping ? rd_adr_next : intpinfo_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + intpinfo_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + intpinfo_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (intpinfo_wr_adr == rd_adr_next) : (intpinfo_wr_adr == intpinfo_rd_adr)); +wire [3:0] intpinfo_rd_pd_p_byp = intpinfo_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = intpinfo_wr_count == 0; +wire [3:0] intpinfo_rd_pd_p = intpinfo_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire intpinfo_rd_pvld_p; // data out of fifo is valid +reg intpinfo_rd_pvld_int; // internal copy of intpinfo_rd_pvld +assign intpinfo_rd_pvld = intpinfo_rd_pvld_int; +assign rd_popping = intpinfo_rd_pvld_p && !(intpinfo_rd_pvld_int && !intpinfo_rd_prdy); +reg [4:0] intpinfo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? intpinfo_rd_count_p : + (intpinfo_rd_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (intpinfo_rd_count_p + 1'd1) : + intpinfo_rd_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign intpinfo_rd_pvld_p = intpinfo_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~intpinfo_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_rd_count_p <= 5'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + intpinfo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + intpinfo_rd_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (intpinfo_rd_pvld_p || (intpinfo_rd_pvld_int && !intpinfo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intpinfo_rd_pvld_int <= 1'b0; + end else begin + intpinfo_rd_pvld_int <= rd_req_next; + end +end +assign intpinfo_rd_pd = intpinfo_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (intpinfo_wr_pvld && !intpinfo_wr_busy_int) || (intpinfo_wr_busy_int != intpinfo_wr_busy_next)) || (rd_pushing || rd_popping || (intpinfo_rd_pvld_int && intpinfo_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_intpinfo_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( intpinfo_wr_pvld && !(!intpinfo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd19 : wr_limit_reg} ) + , .curr ( {27'd0, intpinfo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_intpinfo_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_intpinfo_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v new file mode 100644 index 0000000..7b970ef --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v @@ -0,0 +1,6968 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_lut.v +module NV_NVDLA_CDP_DP_lut ( + nvdla_core_clk //|< i + ,nvdla_core_clk_orig //|< i + ,nvdla_core_rstn //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,dp2lut_X_entry_${m} +//: ,dp2lut_Xinfo_${m} +//: ,dp2lut_Y_entry_${m} +//: ,dp2lut_Yinfo_${m} +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,dp2lut_X_entry_0 +,dp2lut_Xinfo_0 +,dp2lut_Y_entry_0 +,dp2lut_Yinfo_0 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,dp2lut_pvld //|< i + ,lut2intp_prdy //|< i + ,reg2dp_lut_access_type //|< i + ,reg2dp_lut_addr //|< i + ,reg2dp_lut_data //|< i + ,reg2dp_lut_data_trigger //|< i + ,reg2dp_lut_hybrid_priority //|< i + ,reg2dp_lut_oflow_priority //|< i + ,reg2dp_lut_table_id //|< i + ,reg2dp_lut_uflow_priority //|< i + ,dp2lut_prdy //|> o + ,dp2reg_lut_data //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,lut2intp_X_data_${m}0 //|> o +//: ,lut2intp_X_data_${m}0_17b //|> o +//: ,lut2intp_X_data_${m}1 //|> o +//: ,lut2intp_X_info_${m} //|> o +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,lut2intp_X_data_00 //|> o +,lut2intp_X_data_00_17b //|> o +,lut2intp_X_data_01 //|> o +,lut2intp_X_info_0 //|> o + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,lut2intp_X_sel //|> o + ,lut2intp_Y_sel //|> o + ,lut2intp_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_clk_orig; +input nvdla_core_rstn; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: input [9:0] dp2lut_X_entry_${m}; +//: input [17:0] dp2lut_Xinfo_${m}; +//: input [9:0] dp2lut_Y_entry_${m}; +//: input [17:0] dp2lut_Yinfo_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [9:0] dp2lut_X_entry_0; +input [17:0] dp2lut_Xinfo_0; +input [9:0] dp2lut_Y_entry_0; +input [17:0] dp2lut_Yinfo_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input dp2lut_pvld; +input lut2intp_prdy; +input reg2dp_lut_access_type; +input [9:0] reg2dp_lut_addr; +input [15:0] reg2dp_lut_data; +input reg2dp_lut_data_trigger; +input reg2dp_lut_hybrid_priority; +input reg2dp_lut_oflow_priority; +input reg2dp_lut_table_id; +input reg2dp_lut_uflow_priority; +output dp2lut_prdy; +output [15:0] dp2reg_lut_data; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: output [31:0] lut2intp_X_data_${m}0; +//: output [16:0] lut2intp_X_data_${m}0_17b; +//: output [31:0] lut2intp_X_data_${m}1; +//: output [19:0] lut2intp_X_info_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [31:0] lut2intp_X_data_00; +output [16:0] lut2intp_X_data_00_17b; +output [31:0] lut2intp_X_data_01; +output [19:0] lut2intp_X_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [1 -1:0] lut2intp_X_sel; +output [1 -1:0] lut2intp_Y_sel; +output lut2intp_pvld; +//////////////////////////////////////////////////////////////////////////// +reg [15:0] density_out; +//: foreach my $m (0..256) { +//: print qq( +//: reg [15:0] density_reg$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [15:0] density_reg0; + +reg [15:0] density_reg1; + +reg [15:0] density_reg2; + +reg [15:0] density_reg3; + +reg [15:0] density_reg4; + +reg [15:0] density_reg5; + +reg [15:0] density_reg6; + +reg [15:0] density_reg7; + +reg [15:0] density_reg8; + +reg [15:0] density_reg9; + +reg [15:0] density_reg10; + +reg [15:0] density_reg11; + +reg [15:0] density_reg12; + +reg [15:0] density_reg13; + +reg [15:0] density_reg14; + +reg [15:0] density_reg15; + +reg [15:0] density_reg16; + +reg [15:0] density_reg17; + +reg [15:0] density_reg18; + +reg [15:0] density_reg19; + +reg [15:0] density_reg20; + +reg [15:0] density_reg21; + +reg [15:0] density_reg22; + +reg [15:0] density_reg23; + +reg [15:0] density_reg24; + +reg [15:0] density_reg25; + +reg [15:0] density_reg26; + +reg [15:0] density_reg27; + +reg [15:0] density_reg28; + +reg [15:0] density_reg29; + +reg [15:0] density_reg30; + +reg [15:0] density_reg31; + +reg [15:0] density_reg32; + +reg [15:0] density_reg33; + +reg [15:0] density_reg34; + +reg [15:0] density_reg35; + +reg [15:0] density_reg36; + +reg [15:0] density_reg37; + +reg [15:0] density_reg38; + +reg [15:0] density_reg39; + +reg [15:0] density_reg40; + +reg [15:0] density_reg41; + +reg [15:0] density_reg42; + +reg [15:0] density_reg43; + +reg [15:0] density_reg44; + +reg [15:0] density_reg45; + +reg [15:0] density_reg46; + +reg [15:0] density_reg47; + +reg [15:0] density_reg48; + +reg [15:0] density_reg49; + +reg [15:0] density_reg50; + +reg [15:0] density_reg51; + +reg [15:0] density_reg52; + +reg [15:0] density_reg53; + +reg [15:0] density_reg54; + +reg [15:0] density_reg55; + +reg [15:0] density_reg56; + +reg [15:0] density_reg57; + +reg [15:0] density_reg58; + +reg [15:0] density_reg59; + +reg [15:0] density_reg60; + +reg [15:0] density_reg61; + +reg [15:0] density_reg62; + +reg [15:0] density_reg63; + +reg [15:0] density_reg64; + +reg [15:0] density_reg65; + +reg [15:0] density_reg66; + +reg [15:0] density_reg67; + +reg [15:0] density_reg68; + +reg [15:0] density_reg69; + +reg [15:0] density_reg70; + +reg [15:0] density_reg71; + +reg [15:0] density_reg72; + +reg [15:0] density_reg73; + +reg [15:0] density_reg74; + +reg [15:0] density_reg75; + +reg [15:0] density_reg76; + +reg [15:0] density_reg77; + +reg [15:0] density_reg78; + +reg [15:0] density_reg79; + +reg [15:0] density_reg80; + +reg [15:0] density_reg81; + +reg [15:0] density_reg82; + +reg [15:0] density_reg83; + +reg [15:0] density_reg84; + +reg [15:0] density_reg85; + +reg [15:0] density_reg86; + +reg [15:0] density_reg87; + +reg [15:0] density_reg88; + +reg [15:0] density_reg89; + +reg [15:0] density_reg90; + +reg [15:0] density_reg91; + +reg [15:0] density_reg92; + +reg [15:0] density_reg93; + +reg [15:0] density_reg94; + +reg [15:0] density_reg95; + +reg [15:0] density_reg96; + +reg [15:0] density_reg97; + +reg [15:0] density_reg98; + +reg [15:0] density_reg99; + +reg [15:0] density_reg100; + +reg [15:0] density_reg101; + +reg [15:0] density_reg102; + +reg [15:0] density_reg103; + +reg [15:0] density_reg104; + +reg [15:0] density_reg105; + +reg [15:0] density_reg106; + +reg [15:0] density_reg107; + +reg [15:0] density_reg108; + +reg [15:0] density_reg109; + +reg [15:0] density_reg110; + +reg [15:0] density_reg111; + +reg [15:0] density_reg112; + +reg [15:0] density_reg113; + +reg [15:0] density_reg114; + +reg [15:0] density_reg115; + +reg [15:0] density_reg116; + +reg [15:0] density_reg117; + +reg [15:0] density_reg118; + +reg [15:0] density_reg119; + +reg [15:0] density_reg120; + +reg [15:0] density_reg121; + +reg [15:0] density_reg122; + +reg [15:0] density_reg123; + +reg [15:0] density_reg124; + +reg [15:0] density_reg125; + +reg [15:0] density_reg126; + +reg [15:0] density_reg127; + +reg [15:0] density_reg128; + +reg [15:0] density_reg129; + +reg [15:0] density_reg130; + +reg [15:0] density_reg131; + +reg [15:0] density_reg132; + +reg [15:0] density_reg133; + +reg [15:0] density_reg134; + +reg [15:0] density_reg135; + +reg [15:0] density_reg136; + +reg [15:0] density_reg137; + +reg [15:0] density_reg138; + +reg [15:0] density_reg139; + +reg [15:0] density_reg140; + +reg [15:0] density_reg141; + +reg [15:0] density_reg142; + +reg [15:0] density_reg143; + +reg [15:0] density_reg144; + +reg [15:0] density_reg145; + +reg [15:0] density_reg146; + +reg [15:0] density_reg147; + +reg [15:0] density_reg148; + +reg [15:0] density_reg149; + +reg [15:0] density_reg150; + +reg [15:0] density_reg151; + +reg [15:0] density_reg152; + +reg [15:0] density_reg153; + +reg [15:0] density_reg154; + +reg [15:0] density_reg155; + +reg [15:0] density_reg156; + +reg [15:0] density_reg157; + +reg [15:0] density_reg158; + +reg [15:0] density_reg159; + +reg [15:0] density_reg160; + +reg [15:0] density_reg161; + +reg [15:0] density_reg162; + +reg [15:0] density_reg163; + +reg [15:0] density_reg164; + +reg [15:0] density_reg165; + +reg [15:0] density_reg166; + +reg [15:0] density_reg167; + +reg [15:0] density_reg168; + +reg [15:0] density_reg169; + +reg [15:0] density_reg170; + +reg [15:0] density_reg171; + +reg [15:0] density_reg172; + +reg [15:0] density_reg173; + +reg [15:0] density_reg174; + +reg [15:0] density_reg175; + +reg [15:0] density_reg176; + +reg [15:0] density_reg177; + +reg [15:0] density_reg178; + +reg [15:0] density_reg179; + +reg [15:0] density_reg180; + +reg [15:0] density_reg181; + +reg [15:0] density_reg182; + +reg [15:0] density_reg183; + +reg [15:0] density_reg184; + +reg [15:0] density_reg185; + +reg [15:0] density_reg186; + +reg [15:0] density_reg187; + +reg [15:0] density_reg188; + +reg [15:0] density_reg189; + +reg [15:0] density_reg190; + +reg [15:0] density_reg191; + +reg [15:0] density_reg192; + +reg [15:0] density_reg193; + +reg [15:0] density_reg194; + +reg [15:0] density_reg195; + +reg [15:0] density_reg196; + +reg [15:0] density_reg197; + +reg [15:0] density_reg198; + +reg [15:0] density_reg199; + +reg [15:0] density_reg200; + +reg [15:0] density_reg201; + +reg [15:0] density_reg202; + +reg [15:0] density_reg203; + +reg [15:0] density_reg204; + +reg [15:0] density_reg205; + +reg [15:0] density_reg206; + +reg [15:0] density_reg207; + +reg [15:0] density_reg208; + +reg [15:0] density_reg209; + +reg [15:0] density_reg210; + +reg [15:0] density_reg211; + +reg [15:0] density_reg212; + +reg [15:0] density_reg213; + +reg [15:0] density_reg214; + +reg [15:0] density_reg215; + +reg [15:0] density_reg216; + +reg [15:0] density_reg217; + +reg [15:0] density_reg218; + +reg [15:0] density_reg219; + +reg [15:0] density_reg220; + +reg [15:0] density_reg221; + +reg [15:0] density_reg222; + +reg [15:0] density_reg223; + +reg [15:0] density_reg224; + +reg [15:0] density_reg225; + +reg [15:0] density_reg226; + +reg [15:0] density_reg227; + +reg [15:0] density_reg228; + +reg [15:0] density_reg229; + +reg [15:0] density_reg230; + +reg [15:0] density_reg231; + +reg [15:0] density_reg232; + +reg [15:0] density_reg233; + +reg [15:0] density_reg234; + +reg [15:0] density_reg235; + +reg [15:0] density_reg236; + +reg [15:0] density_reg237; + +reg [15:0] density_reg238; + +reg [15:0] density_reg239; + +reg [15:0] density_reg240; + +reg [15:0] density_reg241; + +reg [15:0] density_reg242; + +reg [15:0] density_reg243; + +reg [15:0] density_reg244; + +reg [15:0] density_reg245; + +reg [15:0] density_reg246; + +reg [15:0] density_reg247; + +reg [15:0] density_reg248; + +reg [15:0] density_reg249; + +reg [15:0] density_reg250; + +reg [15:0] density_reg251; + +reg [15:0] density_reg252; + +reg [15:0] density_reg253; + +reg [15:0] density_reg254; + +reg [15:0] density_reg255; + +reg [15:0] density_reg256; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg lut2intp_pvld; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [31:0] lut2intp_X_data_${m}0; +//: wire [16:0] lut2intp_X_data_${m}0_17b; +//: wire [31:0] lut2intp_X_data_${m}1; +//: wire [19:0] lut2intp_X_info_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [31:0] lut2intp_X_data_00; +wire [16:0] lut2intp_X_data_00_17b; +wire [31:0] lut2intp_X_data_01; +wire [19:0] lut2intp_X_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [1 -1:0] lut2intp_X_sel; +wire [1 -1:0] lut2intp_Y_sel; +reg [1 -1:0] lutX_sel; +reg [1 -1:0] lutY_sel; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: reg [15:0] lut_X_data_${m}0; +//: reg [15:0] lut_X_data_${m}1; +//: reg [17:0] lut_X_info_${m}; +//: reg [15:0] lut_Y_data_${m}0; +//: reg [15:0] lut_Y_data_${m}1; +//: reg [17:0] lut_Y_info_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [15:0] lut_X_data_00; +reg [15:0] lut_X_data_01; +reg [17:0] lut_X_info_0; +reg [15:0] lut_Y_data_00; +reg [15:0] lut_Y_data_01; +reg [17:0] lut_Y_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [1 -1:0] lut_X_sel; +reg [1 -1:0] lut_Y_sel; +reg [15:0] raw_out; +//: foreach my $m (0..64) { +//: print qq( +//: reg [15:0] raw_reg$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [15:0] raw_reg0; + +reg [15:0] raw_reg1; + +reg [15:0] raw_reg2; + +reg [15:0] raw_reg3; + +reg [15:0] raw_reg4; + +reg [15:0] raw_reg5; + +reg [15:0] raw_reg6; + +reg [15:0] raw_reg7; + +reg [15:0] raw_reg8; + +reg [15:0] raw_reg9; + +reg [15:0] raw_reg10; + +reg [15:0] raw_reg11; + +reg [15:0] raw_reg12; + +reg [15:0] raw_reg13; + +reg [15:0] raw_reg14; + +reg [15:0] raw_reg15; + +reg [15:0] raw_reg16; + +reg [15:0] raw_reg17; + +reg [15:0] raw_reg18; + +reg [15:0] raw_reg19; + +reg [15:0] raw_reg20; + +reg [15:0] raw_reg21; + +reg [15:0] raw_reg22; + +reg [15:0] raw_reg23; + +reg [15:0] raw_reg24; + +reg [15:0] raw_reg25; + +reg [15:0] raw_reg26; + +reg [15:0] raw_reg27; + +reg [15:0] raw_reg28; + +reg [15:0] raw_reg29; + +reg [15:0] raw_reg30; + +reg [15:0] raw_reg31; + +reg [15:0] raw_reg32; + +reg [15:0] raw_reg33; + +reg [15:0] raw_reg34; + +reg [15:0] raw_reg35; + +reg [15:0] raw_reg36; + +reg [15:0] raw_reg37; + +reg [15:0] raw_reg38; + +reg [15:0] raw_reg39; + +reg [15:0] raw_reg40; + +reg [15:0] raw_reg41; + +reg [15:0] raw_reg42; + +reg [15:0] raw_reg43; + +reg [15:0] raw_reg44; + +reg [15:0] raw_reg45; + +reg [15:0] raw_reg46; + +reg [15:0] raw_reg47; + +reg [15:0] raw_reg48; + +reg [15:0] raw_reg49; + +reg [15:0] raw_reg50; + +reg [15:0] raw_reg51; + +reg [15:0] raw_reg52; + +reg [15:0] raw_reg53; + +reg [15:0] raw_reg54; + +reg [15:0] raw_reg55; + +reg [15:0] raw_reg56; + +reg [15:0] raw_reg57; + +reg [15:0] raw_reg58; + +reg [15:0] raw_reg59; + +reg [15:0] raw_reg60; + +reg [15:0] raw_reg61; + +reg [15:0] raw_reg62; + +reg [15:0] raw_reg63; + +reg [15:0] raw_reg64; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire both_hybrid_sel; +wire both_of_sel; +wire both_uf_sel; +wire dp2lut_prdy_f; +wire load_din; +// my $k = 1/2; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [15:0] lutX_data_${m}0; +//: wire [15:0] lutX_data_${m}1; +//: wire [15:0] lutX_info_${m}; +//: wire [31:0] lut_X_dat_${m}0; +//: wire [16:0] lut_X_dat_${m}0_fp17; +//: wire [31:0] lut_X_dat_${m}1; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [15:0] lutX_data_00; +wire [15:0] lutX_data_01; +wire [15:0] lutX_info_0; +wire [31:0] lut_X_dat_00; +wire [16:0] lut_X_dat_00_fp17; +wire [31:0] lut_X_dat_01; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire lut_wr_en; +wire raw_select; +//////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +assign lut_wr_en = (reg2dp_lut_access_type== 1'h1 ) && reg2dp_lut_data_trigger; +assign raw_select = (reg2dp_lut_table_id == 1'h0 ); +//========================================== +//LUT write +//------------------------------------------ +//need update foreach value if LUT depth update +//: foreach my $m (0..64) { +//: print qq( +//: always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: raw_reg${m} <= {16{1'b0}}; +//: end else if (lut_wr_en & raw_select) begin +//: if (reg2dp_lut_addr[9:0] == $m) +//: raw_reg$m <= reg2dp_lut_data[15:0]; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg0 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 0) +raw_reg0 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg1 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 1) +raw_reg1 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg2 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 2) +raw_reg2 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg3 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 3) +raw_reg3 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg4 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 4) +raw_reg4 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg5 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 5) +raw_reg5 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg6 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 6) +raw_reg6 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg7 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 7) +raw_reg7 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg8 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 8) +raw_reg8 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg9 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 9) +raw_reg9 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg10 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 10) +raw_reg10 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg11 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 11) +raw_reg11 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg12 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 12) +raw_reg12 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg13 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 13) +raw_reg13 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg14 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 14) +raw_reg14 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg15 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 15) +raw_reg15 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg16 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 16) +raw_reg16 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg17 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 17) +raw_reg17 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg18 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 18) +raw_reg18 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg19 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 19) +raw_reg19 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg20 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 20) +raw_reg20 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg21 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 21) +raw_reg21 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg22 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 22) +raw_reg22 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg23 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 23) +raw_reg23 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg24 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 24) +raw_reg24 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg25 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 25) +raw_reg25 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg26 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 26) +raw_reg26 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg27 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 27) +raw_reg27 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg28 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 28) +raw_reg28 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg29 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 29) +raw_reg29 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg30 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 30) +raw_reg30 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg31 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 31) +raw_reg31 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg32 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 32) +raw_reg32 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg33 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 33) +raw_reg33 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg34 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 34) +raw_reg34 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg35 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 35) +raw_reg35 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg36 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 36) +raw_reg36 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg37 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 37) +raw_reg37 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg38 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 38) +raw_reg38 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg39 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 39) +raw_reg39 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg40 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 40) +raw_reg40 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg41 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 41) +raw_reg41 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg42 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 42) +raw_reg42 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg43 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 43) +raw_reg43 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg44 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 44) +raw_reg44 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg45 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 45) +raw_reg45 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg46 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 46) +raw_reg46 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg47 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 47) +raw_reg47 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg48 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 48) +raw_reg48 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg49 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 49) +raw_reg49 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg50 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 50) +raw_reg50 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg51 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 51) +raw_reg51 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg52 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 52) +raw_reg52 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg53 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 53) +raw_reg53 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg54 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 54) +raw_reg54 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg55 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 55) +raw_reg55 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg56 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 56) +raw_reg56 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg57 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 57) +raw_reg57 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg58 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 58) +raw_reg58 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg59 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 59) +raw_reg59 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg60 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 60) +raw_reg60 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg61 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 61) +raw_reg61 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg62 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 62) +raw_reg62 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg63 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 63) +raw_reg63 <= reg2dp_lut_data[15:0]; +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +raw_reg64 <= {16{1'b0}}; +end else if (lut_wr_en & raw_select) begin +if (reg2dp_lut_addr[9:0] == 64) +raw_reg64 <= reg2dp_lut_data[15:0]; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//------------------------------------------ +//need update foreach value if LUT depth update +//: foreach my $m (0..256) { +//: print qq( +//: always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: density_reg$m <= {16{1'b0}}; +//: end else begin +//: if (lut_wr_en & (~raw_select)) begin +//: if (reg2dp_lut_addr[9:0] == $m) +//: density_reg$m <= reg2dp_lut_data[15:0]; +//: end +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg0 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 0) +density_reg0 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg1 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 1) +density_reg1 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg2 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 2) +density_reg2 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg3 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 3) +density_reg3 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg4 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 4) +density_reg4 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg5 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 5) +density_reg5 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg6 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 6) +density_reg6 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg7 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 7) +density_reg7 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg8 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 8) +density_reg8 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg9 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 9) +density_reg9 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg10 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 10) +density_reg10 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg11 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 11) +density_reg11 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg12 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 12) +density_reg12 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg13 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 13) +density_reg13 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg14 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 14) +density_reg14 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg15 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 15) +density_reg15 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg16 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 16) +density_reg16 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg17 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 17) +density_reg17 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg18 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 18) +density_reg18 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg19 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 19) +density_reg19 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg20 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 20) +density_reg20 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg21 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 21) +density_reg21 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg22 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 22) +density_reg22 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg23 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 23) +density_reg23 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg24 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 24) +density_reg24 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg25 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 25) +density_reg25 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg26 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 26) +density_reg26 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg27 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 27) +density_reg27 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg28 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 28) +density_reg28 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg29 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 29) +density_reg29 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg30 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 30) +density_reg30 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg31 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 31) +density_reg31 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg32 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 32) +density_reg32 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg33 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 33) +density_reg33 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg34 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 34) +density_reg34 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg35 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 35) +density_reg35 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg36 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 36) +density_reg36 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg37 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 37) +density_reg37 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg38 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 38) +density_reg38 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg39 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 39) +density_reg39 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg40 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 40) +density_reg40 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg41 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 41) +density_reg41 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg42 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 42) +density_reg42 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg43 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 43) +density_reg43 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg44 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 44) +density_reg44 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg45 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 45) +density_reg45 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg46 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 46) +density_reg46 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg47 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 47) +density_reg47 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg48 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 48) +density_reg48 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg49 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 49) +density_reg49 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg50 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 50) +density_reg50 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg51 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 51) +density_reg51 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg52 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 52) +density_reg52 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg53 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 53) +density_reg53 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg54 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 54) +density_reg54 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg55 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 55) +density_reg55 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg56 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 56) +density_reg56 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg57 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 57) +density_reg57 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg58 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 58) +density_reg58 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg59 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 59) +density_reg59 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg60 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 60) +density_reg60 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg61 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 61) +density_reg61 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg62 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 62) +density_reg62 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg63 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 63) +density_reg63 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg64 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 64) +density_reg64 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg65 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 65) +density_reg65 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg66 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 66) +density_reg66 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg67 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 67) +density_reg67 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg68 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 68) +density_reg68 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg69 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 69) +density_reg69 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg70 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 70) +density_reg70 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg71 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 71) +density_reg71 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg72 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 72) +density_reg72 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg73 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 73) +density_reg73 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg74 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 74) +density_reg74 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg75 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 75) +density_reg75 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg76 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 76) +density_reg76 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg77 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 77) +density_reg77 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg78 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 78) +density_reg78 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg79 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 79) +density_reg79 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg80 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 80) +density_reg80 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg81 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 81) +density_reg81 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg82 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 82) +density_reg82 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg83 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 83) +density_reg83 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg84 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 84) +density_reg84 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg85 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 85) +density_reg85 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg86 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 86) +density_reg86 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg87 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 87) +density_reg87 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg88 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 88) +density_reg88 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg89 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 89) +density_reg89 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg90 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 90) +density_reg90 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg91 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 91) +density_reg91 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg92 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 92) +density_reg92 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg93 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 93) +density_reg93 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg94 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 94) +density_reg94 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg95 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 95) +density_reg95 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg96 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 96) +density_reg96 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg97 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 97) +density_reg97 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg98 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 98) +density_reg98 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg99 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 99) +density_reg99 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg100 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 100) +density_reg100 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg101 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 101) +density_reg101 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg102 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 102) +density_reg102 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg103 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 103) +density_reg103 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg104 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 104) +density_reg104 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg105 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 105) +density_reg105 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg106 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 106) +density_reg106 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg107 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 107) +density_reg107 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg108 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 108) +density_reg108 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg109 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 109) +density_reg109 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg110 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 110) +density_reg110 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg111 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 111) +density_reg111 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg112 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 112) +density_reg112 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg113 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 113) +density_reg113 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg114 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 114) +density_reg114 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg115 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 115) +density_reg115 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg116 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 116) +density_reg116 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg117 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 117) +density_reg117 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg118 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 118) +density_reg118 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg119 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 119) +density_reg119 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg120 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 120) +density_reg120 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg121 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 121) +density_reg121 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg122 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 122) +density_reg122 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg123 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 123) +density_reg123 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg124 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 124) +density_reg124 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg125 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 125) +density_reg125 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg126 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 126) +density_reg126 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg127 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 127) +density_reg127 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg128 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 128) +density_reg128 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg129 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 129) +density_reg129 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg130 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 130) +density_reg130 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg131 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 131) +density_reg131 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg132 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 132) +density_reg132 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg133 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 133) +density_reg133 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg134 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 134) +density_reg134 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg135 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 135) +density_reg135 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg136 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 136) +density_reg136 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg137 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 137) +density_reg137 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg138 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 138) +density_reg138 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg139 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 139) +density_reg139 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg140 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 140) +density_reg140 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg141 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 141) +density_reg141 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg142 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 142) +density_reg142 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg143 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 143) +density_reg143 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg144 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 144) +density_reg144 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg145 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 145) +density_reg145 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg146 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 146) +density_reg146 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg147 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 147) +density_reg147 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg148 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 148) +density_reg148 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg149 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 149) +density_reg149 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg150 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 150) +density_reg150 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg151 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 151) +density_reg151 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg152 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 152) +density_reg152 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg153 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 153) +density_reg153 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg154 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 154) +density_reg154 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg155 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 155) +density_reg155 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg156 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 156) +density_reg156 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg157 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 157) +density_reg157 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg158 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 158) +density_reg158 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg159 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 159) +density_reg159 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg160 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 160) +density_reg160 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg161 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 161) +density_reg161 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg162 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 162) +density_reg162 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg163 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 163) +density_reg163 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg164 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 164) +density_reg164 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg165 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 165) +density_reg165 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg166 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 166) +density_reg166 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg167 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 167) +density_reg167 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg168 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 168) +density_reg168 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg169 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 169) +density_reg169 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg170 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 170) +density_reg170 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg171 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 171) +density_reg171 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg172 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 172) +density_reg172 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg173 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 173) +density_reg173 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg174 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 174) +density_reg174 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg175 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 175) +density_reg175 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg176 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 176) +density_reg176 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg177 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 177) +density_reg177 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg178 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 178) +density_reg178 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg179 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 179) +density_reg179 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg180 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 180) +density_reg180 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg181 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 181) +density_reg181 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg182 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 182) +density_reg182 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg183 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 183) +density_reg183 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg184 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 184) +density_reg184 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg185 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 185) +density_reg185 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg186 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 186) +density_reg186 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg187 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 187) +density_reg187 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg188 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 188) +density_reg188 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg189 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 189) +density_reg189 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg190 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 190) +density_reg190 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg191 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 191) +density_reg191 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg192 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 192) +density_reg192 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg193 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 193) +density_reg193 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg194 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 194) +density_reg194 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg195 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 195) +density_reg195 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg196 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 196) +density_reg196 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg197 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 197) +density_reg197 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg198 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 198) +density_reg198 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg199 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 199) +density_reg199 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg200 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 200) +density_reg200 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg201 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 201) +density_reg201 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg202 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 202) +density_reg202 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg203 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 203) +density_reg203 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg204 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 204) +density_reg204 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg205 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 205) +density_reg205 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg206 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 206) +density_reg206 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg207 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 207) +density_reg207 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg208 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 208) +density_reg208 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg209 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 209) +density_reg209 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg210 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 210) +density_reg210 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg211 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 211) +density_reg211 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg212 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 212) +density_reg212 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg213 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 213) +density_reg213 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg214 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 214) +density_reg214 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg215 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 215) +density_reg215 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg216 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 216) +density_reg216 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg217 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 217) +density_reg217 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg218 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 218) +density_reg218 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg219 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 219) +density_reg219 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg220 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 220) +density_reg220 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg221 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 221) +density_reg221 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg222 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 222) +density_reg222 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg223 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 223) +density_reg223 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg224 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 224) +density_reg224 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg225 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 225) +density_reg225 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg226 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 226) +density_reg226 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg227 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 227) +density_reg227 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg228 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 228) +density_reg228 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg229 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 229) +density_reg229 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg230 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 230) +density_reg230 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg231 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 231) +density_reg231 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg232 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 232) +density_reg232 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg233 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 233) +density_reg233 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg234 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 234) +density_reg234 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg235 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 235) +density_reg235 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg236 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 236) +density_reg236 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg237 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 237) +density_reg237 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg238 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 238) +density_reg238 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg239 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 239) +density_reg239 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg240 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 240) +density_reg240 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg241 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 241) +density_reg241 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg242 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 242) +density_reg242 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg243 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 243) +density_reg243 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg244 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 244) +density_reg244 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg245 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 245) +density_reg245 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg246 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 246) +density_reg246 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg247 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 247) +density_reg247 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg248 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 248) +density_reg248 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg249 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 249) +density_reg249 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg250 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 250) +density_reg250 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg251 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 251) +density_reg251 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg252 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 252) +density_reg252 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg253 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 253) +density_reg253 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg254 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 254) +density_reg254 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg255 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 255) +density_reg255 <= reg2dp_lut_data[15:0]; +end +end +end + +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +density_reg256 <= {16{1'b0}}; +end else begin +if (lut_wr_en & (~raw_select)) begin +if (reg2dp_lut_addr[9:0] == 256) +density_reg256 <= reg2dp_lut_data[15:0]; +end +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//========================================== +//LUT read +//------------------------------------------ +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + raw_out <= {16{1'b0}}; + end else begin + case(reg2dp_lut_addr[9:0]) +//: foreach my $m (0..64) { +//: print qq( +//: $m: raw_out <= raw_reg$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +0: raw_out <= raw_reg0; + +1: raw_out <= raw_reg1; + +2: raw_out <= raw_reg2; + +3: raw_out <= raw_reg3; + +4: raw_out <= raw_reg4; + +5: raw_out <= raw_reg5; + +6: raw_out <= raw_reg6; + +7: raw_out <= raw_reg7; + +8: raw_out <= raw_reg8; + +9: raw_out <= raw_reg9; + +10: raw_out <= raw_reg10; + +11: raw_out <= raw_reg11; + +12: raw_out <= raw_reg12; + +13: raw_out <= raw_reg13; + +14: raw_out <= raw_reg14; + +15: raw_out <= raw_reg15; + +16: raw_out <= raw_reg16; + +17: raw_out <= raw_reg17; + +18: raw_out <= raw_reg18; + +19: raw_out <= raw_reg19; + +20: raw_out <= raw_reg20; + +21: raw_out <= raw_reg21; + +22: raw_out <= raw_reg22; + +23: raw_out <= raw_reg23; + +24: raw_out <= raw_reg24; + +25: raw_out <= raw_reg25; + +26: raw_out <= raw_reg26; + +27: raw_out <= raw_reg27; + +28: raw_out <= raw_reg28; + +29: raw_out <= raw_reg29; + +30: raw_out <= raw_reg30; + +31: raw_out <= raw_reg31; + +32: raw_out <= raw_reg32; + +33: raw_out <= raw_reg33; + +34: raw_out <= raw_reg34; + +35: raw_out <= raw_reg35; + +36: raw_out <= raw_reg36; + +37: raw_out <= raw_reg37; + +38: raw_out <= raw_reg38; + +39: raw_out <= raw_reg39; + +40: raw_out <= raw_reg40; + +41: raw_out <= raw_reg41; + +42: raw_out <= raw_reg42; + +43: raw_out <= raw_reg43; + +44: raw_out <= raw_reg44; + +45: raw_out <= raw_reg45; + +46: raw_out <= raw_reg46; + +47: raw_out <= raw_reg47; + +48: raw_out <= raw_reg48; + +49: raw_out <= raw_reg49; + +50: raw_out <= raw_reg50; + +51: raw_out <= raw_reg51; + +52: raw_out <= raw_reg52; + +53: raw_out <= raw_reg53; + +54: raw_out <= raw_reg54; + +55: raw_out <= raw_reg55; + +56: raw_out <= raw_reg56; + +57: raw_out <= raw_reg57; + +58: raw_out <= raw_reg58; + +59: raw_out <= raw_reg59; + +60: raw_out <= raw_reg60; + +61: raw_out <= raw_reg61; + +62: raw_out <= raw_reg62; + +63: raw_out <= raw_reg63; + +64: raw_out <= raw_reg64; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default: raw_out <= raw_reg0; + endcase + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + density_out <= {16{1'b0}}; + end else begin + case (reg2dp_lut_addr[9:0]) +//: foreach my $m (0..256) { +//: print qq( +//: $m: density_out <= density_reg$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +0: density_out <= density_reg0; + +1: density_out <= density_reg1; + +2: density_out <= density_reg2; + +3: density_out <= density_reg3; + +4: density_out <= density_reg4; + +5: density_out <= density_reg5; + +6: density_out <= density_reg6; + +7: density_out <= density_reg7; + +8: density_out <= density_reg8; + +9: density_out <= density_reg9; + +10: density_out <= density_reg10; + +11: density_out <= density_reg11; + +12: density_out <= density_reg12; + +13: density_out <= density_reg13; + +14: density_out <= density_reg14; + +15: density_out <= density_reg15; + +16: density_out <= density_reg16; + +17: density_out <= density_reg17; + +18: density_out <= density_reg18; + +19: density_out <= density_reg19; + +20: density_out <= density_reg20; + +21: density_out <= density_reg21; + +22: density_out <= density_reg22; + +23: density_out <= density_reg23; + +24: density_out <= density_reg24; + +25: density_out <= density_reg25; + +26: density_out <= density_reg26; + +27: density_out <= density_reg27; + +28: density_out <= density_reg28; + +29: density_out <= density_reg29; + +30: density_out <= density_reg30; + +31: density_out <= density_reg31; + +32: density_out <= density_reg32; + +33: density_out <= density_reg33; + +34: density_out <= density_reg34; + +35: density_out <= density_reg35; + +36: density_out <= density_reg36; + +37: density_out <= density_reg37; + +38: density_out <= density_reg38; + +39: density_out <= density_reg39; + +40: density_out <= density_reg40; + +41: density_out <= density_reg41; + +42: density_out <= density_reg42; + +43: density_out <= density_reg43; + +44: density_out <= density_reg44; + +45: density_out <= density_reg45; + +46: density_out <= density_reg46; + +47: density_out <= density_reg47; + +48: density_out <= density_reg48; + +49: density_out <= density_reg49; + +50: density_out <= density_reg50; + +51: density_out <= density_reg51; + +52: density_out <= density_reg52; + +53: density_out <= density_reg53; + +54: density_out <= density_reg54; + +55: density_out <= density_reg55; + +56: density_out <= density_reg56; + +57: density_out <= density_reg57; + +58: density_out <= density_reg58; + +59: density_out <= density_reg59; + +60: density_out <= density_reg60; + +61: density_out <= density_reg61; + +62: density_out <= density_reg62; + +63: density_out <= density_reg63; + +64: density_out <= density_reg64; + +65: density_out <= density_reg65; + +66: density_out <= density_reg66; + +67: density_out <= density_reg67; + +68: density_out <= density_reg68; + +69: density_out <= density_reg69; + +70: density_out <= density_reg70; + +71: density_out <= density_reg71; + +72: density_out <= density_reg72; + +73: density_out <= density_reg73; + +74: density_out <= density_reg74; + +75: density_out <= density_reg75; + +76: density_out <= density_reg76; + +77: density_out <= density_reg77; + +78: density_out <= density_reg78; + +79: density_out <= density_reg79; + +80: density_out <= density_reg80; + +81: density_out <= density_reg81; + +82: density_out <= density_reg82; + +83: density_out <= density_reg83; + +84: density_out <= density_reg84; + +85: density_out <= density_reg85; + +86: density_out <= density_reg86; + +87: density_out <= density_reg87; + +88: density_out <= density_reg88; + +89: density_out <= density_reg89; + +90: density_out <= density_reg90; + +91: density_out <= density_reg91; + +92: density_out <= density_reg92; + +93: density_out <= density_reg93; + +94: density_out <= density_reg94; + +95: density_out <= density_reg95; + +96: density_out <= density_reg96; + +97: density_out <= density_reg97; + +98: density_out <= density_reg98; + +99: density_out <= density_reg99; + +100: density_out <= density_reg100; + +101: density_out <= density_reg101; + +102: density_out <= density_reg102; + +103: density_out <= density_reg103; + +104: density_out <= density_reg104; + +105: density_out <= density_reg105; + +106: density_out <= density_reg106; + +107: density_out <= density_reg107; + +108: density_out <= density_reg108; + +109: density_out <= density_reg109; + +110: density_out <= density_reg110; + +111: density_out <= density_reg111; + +112: density_out <= density_reg112; + +113: density_out <= density_reg113; + +114: density_out <= density_reg114; + +115: density_out <= density_reg115; + +116: density_out <= density_reg116; + +117: density_out <= density_reg117; + +118: density_out <= density_reg118; + +119: density_out <= density_reg119; + +120: density_out <= density_reg120; + +121: density_out <= density_reg121; + +122: density_out <= density_reg122; + +123: density_out <= density_reg123; + +124: density_out <= density_reg124; + +125: density_out <= density_reg125; + +126: density_out <= density_reg126; + +127: density_out <= density_reg127; + +128: density_out <= density_reg128; + +129: density_out <= density_reg129; + +130: density_out <= density_reg130; + +131: density_out <= density_reg131; + +132: density_out <= density_reg132; + +133: density_out <= density_reg133; + +134: density_out <= density_reg134; + +135: density_out <= density_reg135; + +136: density_out <= density_reg136; + +137: density_out <= density_reg137; + +138: density_out <= density_reg138; + +139: density_out <= density_reg139; + +140: density_out <= density_reg140; + +141: density_out <= density_reg141; + +142: density_out <= density_reg142; + +143: density_out <= density_reg143; + +144: density_out <= density_reg144; + +145: density_out <= density_reg145; + +146: density_out <= density_reg146; + +147: density_out <= density_reg147; + +148: density_out <= density_reg148; + +149: density_out <= density_reg149; + +150: density_out <= density_reg150; + +151: density_out <= density_reg151; + +152: density_out <= density_reg152; + +153: density_out <= density_reg153; + +154: density_out <= density_reg154; + +155: density_out <= density_reg155; + +156: density_out <= density_reg156; + +157: density_out <= density_reg157; + +158: density_out <= density_reg158; + +159: density_out <= density_reg159; + +160: density_out <= density_reg160; + +161: density_out <= density_reg161; + +162: density_out <= density_reg162; + +163: density_out <= density_reg163; + +164: density_out <= density_reg164; + +165: density_out <= density_reg165; + +166: density_out <= density_reg166; + +167: density_out <= density_reg167; + +168: density_out <= density_reg168; + +169: density_out <= density_reg169; + +170: density_out <= density_reg170; + +171: density_out <= density_reg171; + +172: density_out <= density_reg172; + +173: density_out <= density_reg173; + +174: density_out <= density_reg174; + +175: density_out <= density_reg175; + +176: density_out <= density_reg176; + +177: density_out <= density_reg177; + +178: density_out <= density_reg178; + +179: density_out <= density_reg179; + +180: density_out <= density_reg180; + +181: density_out <= density_reg181; + +182: density_out <= density_reg182; + +183: density_out <= density_reg183; + +184: density_out <= density_reg184; + +185: density_out <= density_reg185; + +186: density_out <= density_reg186; + +187: density_out <= density_reg187; + +188: density_out <= density_reg188; + +189: density_out <= density_reg189; + +190: density_out <= density_reg190; + +191: density_out <= density_reg191; + +192: density_out <= density_reg192; + +193: density_out <= density_reg193; + +194: density_out <= density_reg194; + +195: density_out <= density_reg195; + +196: density_out <= density_reg196; + +197: density_out <= density_reg197; + +198: density_out <= density_reg198; + +199: density_out <= density_reg199; + +200: density_out <= density_reg200; + +201: density_out <= density_reg201; + +202: density_out <= density_reg202; + +203: density_out <= density_reg203; + +204: density_out <= density_reg204; + +205: density_out <= density_reg205; + +206: density_out <= density_reg206; + +207: density_out <= density_reg207; + +208: density_out <= density_reg208; + +209: density_out <= density_reg209; + +210: density_out <= density_reg210; + +211: density_out <= density_reg211; + +212: density_out <= density_reg212; + +213: density_out <= density_reg213; + +214: density_out <= density_reg214; + +215: density_out <= density_reg215; + +216: density_out <= density_reg216; + +217: density_out <= density_reg217; + +218: density_out <= density_reg218; + +219: density_out <= density_reg219; + +220: density_out <= density_reg220; + +221: density_out <= density_reg221; + +222: density_out <= density_reg222; + +223: density_out <= density_reg223; + +224: density_out <= density_reg224; + +225: density_out <= density_reg225; + +226: density_out <= density_reg226; + +227: density_out <= density_reg227; + +228: density_out <= density_reg228; + +229: density_out <= density_reg229; + +230: density_out <= density_reg230; + +231: density_out <= density_reg231; + +232: density_out <= density_reg232; + +233: density_out <= density_reg233; + +234: density_out <= density_reg234; + +235: density_out <= density_reg235; + +236: density_out <= density_reg236; + +237: density_out <= density_reg237; + +238: density_out <= density_reg238; + +239: density_out <= density_reg239; + +240: density_out <= density_reg240; + +241: density_out <= density_reg241; + +242: density_out <= density_reg242; + +243: density_out <= density_reg243; + +244: density_out <= density_reg244; + +245: density_out <= density_reg245; + +246: density_out <= density_reg246; + +247: density_out <= density_reg247; + +248: density_out <= density_reg248; + +249: density_out <= density_reg249; + +250: density_out <= density_reg250; + +251: density_out <= density_reg251; + +252: density_out <= density_reg252; + +253: density_out <= density_reg253; + +254: density_out <= density_reg254; + +255: density_out <= density_reg255; + +256: density_out <= density_reg256; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default: density_out <= density_reg0; + endcase + end +end +assign dp2reg_lut_data[15:0] = raw_select ? raw_out : density_out; +//========================================== +//data to DP +//------------------------------------------ +assign load_din = dp2lut_pvld & dp2lut_prdy_f; +assign dp2lut_prdy_f = ~lut2intp_pvld | lut2intp_prdy; +assign dp2lut_prdy = dp2lut_prdy_f; +///////////////////////////////// +//lut look up select control +///////////////////////////////// +assign both_hybrid_sel = (reg2dp_lut_hybrid_priority == 1'h1 ); +assign both_of_sel = (reg2dp_lut_oflow_priority == 1'h1 ); +assign both_uf_sel = (reg2dp_lut_uflow_priority == 1'h1 ); +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: case({dp2lut_Xinfo_${m}[17:16],dp2lut_Yinfo_${m}[17:16]}) +//: 4'b0000,4'b0110,4'b1001: lut_X_sel[$m] = ~both_hybrid_sel; //both hit, or one uflow and the other oflow +//: 4'b0001,4'b0010: lut_X_sel[$m] = 1'b1; //X hit, Y uflow/oflow +//: 4'b0100,4'b1000: lut_X_sel[$m] = 1'b0; //X uflow/oflow, Y hit +//: 4'b0101: lut_X_sel[$m] = ~both_uf_sel ; //both uflow +//: 4'b1010: lut_X_sel[$m] = ~both_of_sel ; //both oflow +//: default: lut_X_sel[$m] = 1'd0; +//: endcase +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: case({dp2lut_Xinfo_${m}[17:16],dp2lut_Yinfo_${m}[17:16]}) +//: 4'b0000,4'b0110,4'b1001: lut_Y_sel[$m] = both_hybrid_sel; //both hit, or one uflow and the other oflow +//: 4'b0001,4'b0010: lut_Y_sel[$m] = 1'b0; //X hit, Y uflow/oflow +//: 4'b0100,4'b1000: lut_Y_sel[$m] = 1'b1; //X uflow/oflow, Y hit +//: 4'b0101: lut_Y_sel[$m] = both_uf_sel ; //both uflow +//: 4'b1010: lut_Y_sel[$m] = both_of_sel ; //both oflow +//: default: lut_Y_sel[$m] = 1'd0; +//: endcase +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(*) begin +case({dp2lut_Xinfo_0[17:16],dp2lut_Yinfo_0[17:16]}) +4'b0000,4'b0110,4'b1001: lut_X_sel[0] = ~both_hybrid_sel; //both hit, or one uflow and the other oflow +4'b0001,4'b0010: lut_X_sel[0] = 1'b1; //X hit, Y uflow/oflow +4'b0100,4'b1000: lut_X_sel[0] = 1'b0; //X uflow/oflow, Y hit +4'b0101: lut_X_sel[0] = ~both_uf_sel ; //both uflow +4'b1010: lut_X_sel[0] = ~both_of_sel ; //both oflow +default: lut_X_sel[0] = 1'd0; +endcase +end + +always @(*) begin +case({dp2lut_Xinfo_0[17:16],dp2lut_Yinfo_0[17:16]}) +4'b0000,4'b0110,4'b1001: lut_Y_sel[0] = both_hybrid_sel; //both hit, or one uflow and the other oflow +4'b0001,4'b0010: lut_Y_sel[0] = 1'b0; //X hit, Y uflow/oflow +4'b0100,4'b1000: lut_Y_sel[0] = 1'b1; //X uflow/oflow, Y hit +4'b0101: lut_Y_sel[0] = both_uf_sel ; //both uflow +4'b1010: lut_Y_sel[0] = both_of_sel ; //both oflow +default: lut_Y_sel[0] = 1'd0; +endcase +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP LUT select: Lut X and Lut Y both select or both not selected") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, load_din & (~(&(lut_X_sel ^ lut_Y_sel)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +///////////////////////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_X_data_${m}0[15:0] <= {16{1'b0}}; +//: lut_X_data_${m}1[15:0] <= {16{1'b0}}; +//: end else begin +//: if(load_din & lut_X_sel[$m]) begin +//: if(dp2lut_Xinfo_${m}[16]) begin +//: lut_X_data_${m}0[15:0] <= raw_reg0; +//: lut_X_data_${m}1[15:0] <= raw_reg0; +//: end else if(dp2lut_Xinfo_${m}[17]) begin +//: lut_X_data_${m}0[15:0] <= raw_reg64; +//: lut_X_data_${m}1[15:0] <= raw_reg64; +//: end else begin +//: case(dp2lut_X_entry_${m}[9:0]) +//: ); +//: foreach my $i (0..64-1) { +//: my $j = $i + 1; +//: print qq( +//: $i: begin +//: lut_X_data_${m}0[15:0] <= raw_reg${i}; +//: lut_X_data_${m}1[15:0] <= raw_reg${j}; +//: end +//: ); +//: } +//: print qq( +//: 64: begin +//: lut_X_data_${m}0[15:0] <= raw_reg64; +//: lut_X_data_${m}1[15:0] <= raw_reg64; +//: end +//: default: begin +//: lut_X_data_${m}0[15:0] <= raw_reg0; +//: lut_X_data_${m}1[15:0] <= raw_reg0; +//: end +//: endcase +//: end +//: end +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +lut_X_data_00[15:0] <= {16{1'b0}}; +lut_X_data_01[15:0] <= {16{1'b0}}; +end else begin +if(load_din & lut_X_sel[0]) begin +if(dp2lut_Xinfo_0[16]) begin +lut_X_data_00[15:0] <= raw_reg0; +lut_X_data_01[15:0] <= raw_reg0; +end else if(dp2lut_Xinfo_0[17]) begin +lut_X_data_00[15:0] <= raw_reg64; +lut_X_data_01[15:0] <= raw_reg64; +end else begin +case(dp2lut_X_entry_0[9:0]) + +0: begin +lut_X_data_00[15:0] <= raw_reg0; +lut_X_data_01[15:0] <= raw_reg1; +end + +1: begin +lut_X_data_00[15:0] <= raw_reg1; +lut_X_data_01[15:0] <= raw_reg2; +end + +2: begin +lut_X_data_00[15:0] <= raw_reg2; +lut_X_data_01[15:0] <= raw_reg3; +end + +3: begin +lut_X_data_00[15:0] <= raw_reg3; +lut_X_data_01[15:0] <= raw_reg4; +end + +4: begin +lut_X_data_00[15:0] <= raw_reg4; +lut_X_data_01[15:0] <= raw_reg5; +end + +5: begin +lut_X_data_00[15:0] <= raw_reg5; +lut_X_data_01[15:0] <= raw_reg6; +end + +6: begin +lut_X_data_00[15:0] <= raw_reg6; +lut_X_data_01[15:0] <= raw_reg7; +end + +7: begin +lut_X_data_00[15:0] <= raw_reg7; +lut_X_data_01[15:0] <= raw_reg8; +end + +8: begin +lut_X_data_00[15:0] <= raw_reg8; +lut_X_data_01[15:0] <= raw_reg9; +end + +9: begin +lut_X_data_00[15:0] <= raw_reg9; +lut_X_data_01[15:0] <= raw_reg10; +end + +10: begin +lut_X_data_00[15:0] <= raw_reg10; +lut_X_data_01[15:0] <= raw_reg11; +end + +11: begin +lut_X_data_00[15:0] <= raw_reg11; +lut_X_data_01[15:0] <= raw_reg12; +end + +12: begin +lut_X_data_00[15:0] <= raw_reg12; +lut_X_data_01[15:0] <= raw_reg13; +end + +13: begin +lut_X_data_00[15:0] <= raw_reg13; +lut_X_data_01[15:0] <= raw_reg14; +end + +14: begin +lut_X_data_00[15:0] <= raw_reg14; +lut_X_data_01[15:0] <= raw_reg15; +end + +15: begin +lut_X_data_00[15:0] <= raw_reg15; +lut_X_data_01[15:0] <= raw_reg16; +end + +16: begin +lut_X_data_00[15:0] <= raw_reg16; +lut_X_data_01[15:0] <= raw_reg17; +end + +17: begin +lut_X_data_00[15:0] <= raw_reg17; +lut_X_data_01[15:0] <= raw_reg18; +end + +18: begin +lut_X_data_00[15:0] <= raw_reg18; +lut_X_data_01[15:0] <= raw_reg19; +end + +19: begin +lut_X_data_00[15:0] <= raw_reg19; +lut_X_data_01[15:0] <= raw_reg20; +end + +20: begin +lut_X_data_00[15:0] <= raw_reg20; +lut_X_data_01[15:0] <= raw_reg21; +end + +21: begin +lut_X_data_00[15:0] <= raw_reg21; +lut_X_data_01[15:0] <= raw_reg22; +end + +22: begin +lut_X_data_00[15:0] <= raw_reg22; +lut_X_data_01[15:0] <= raw_reg23; +end + +23: begin +lut_X_data_00[15:0] <= raw_reg23; +lut_X_data_01[15:0] <= raw_reg24; +end + +24: begin +lut_X_data_00[15:0] <= raw_reg24; +lut_X_data_01[15:0] <= raw_reg25; +end + +25: begin +lut_X_data_00[15:0] <= raw_reg25; +lut_X_data_01[15:0] <= raw_reg26; +end + +26: begin +lut_X_data_00[15:0] <= raw_reg26; +lut_X_data_01[15:0] <= raw_reg27; +end + +27: begin +lut_X_data_00[15:0] <= raw_reg27; +lut_X_data_01[15:0] <= raw_reg28; +end + +28: begin +lut_X_data_00[15:0] <= raw_reg28; +lut_X_data_01[15:0] <= raw_reg29; +end + +29: begin +lut_X_data_00[15:0] <= raw_reg29; +lut_X_data_01[15:0] <= raw_reg30; +end + +30: begin +lut_X_data_00[15:0] <= raw_reg30; +lut_X_data_01[15:0] <= raw_reg31; +end + +31: begin +lut_X_data_00[15:0] <= raw_reg31; +lut_X_data_01[15:0] <= raw_reg32; +end + +32: begin +lut_X_data_00[15:0] <= raw_reg32; +lut_X_data_01[15:0] <= raw_reg33; +end + +33: begin +lut_X_data_00[15:0] <= raw_reg33; +lut_X_data_01[15:0] <= raw_reg34; +end + +34: begin +lut_X_data_00[15:0] <= raw_reg34; +lut_X_data_01[15:0] <= raw_reg35; +end + +35: begin +lut_X_data_00[15:0] <= raw_reg35; +lut_X_data_01[15:0] <= raw_reg36; +end + +36: begin +lut_X_data_00[15:0] <= raw_reg36; +lut_X_data_01[15:0] <= raw_reg37; +end + +37: begin +lut_X_data_00[15:0] <= raw_reg37; +lut_X_data_01[15:0] <= raw_reg38; +end + +38: begin +lut_X_data_00[15:0] <= raw_reg38; +lut_X_data_01[15:0] <= raw_reg39; +end + +39: begin +lut_X_data_00[15:0] <= raw_reg39; +lut_X_data_01[15:0] <= raw_reg40; +end + +40: begin +lut_X_data_00[15:0] <= raw_reg40; +lut_X_data_01[15:0] <= raw_reg41; +end + +41: begin +lut_X_data_00[15:0] <= raw_reg41; +lut_X_data_01[15:0] <= raw_reg42; +end + +42: begin +lut_X_data_00[15:0] <= raw_reg42; +lut_X_data_01[15:0] <= raw_reg43; +end + +43: begin +lut_X_data_00[15:0] <= raw_reg43; +lut_X_data_01[15:0] <= raw_reg44; +end + +44: begin +lut_X_data_00[15:0] <= raw_reg44; +lut_X_data_01[15:0] <= raw_reg45; +end + +45: begin +lut_X_data_00[15:0] <= raw_reg45; +lut_X_data_01[15:0] <= raw_reg46; +end + +46: begin +lut_X_data_00[15:0] <= raw_reg46; +lut_X_data_01[15:0] <= raw_reg47; +end + +47: begin +lut_X_data_00[15:0] <= raw_reg47; +lut_X_data_01[15:0] <= raw_reg48; +end + +48: begin +lut_X_data_00[15:0] <= raw_reg48; +lut_X_data_01[15:0] <= raw_reg49; +end + +49: begin +lut_X_data_00[15:0] <= raw_reg49; +lut_X_data_01[15:0] <= raw_reg50; +end + +50: begin +lut_X_data_00[15:0] <= raw_reg50; +lut_X_data_01[15:0] <= raw_reg51; +end + +51: begin +lut_X_data_00[15:0] <= raw_reg51; +lut_X_data_01[15:0] <= raw_reg52; +end + +52: begin +lut_X_data_00[15:0] <= raw_reg52; +lut_X_data_01[15:0] <= raw_reg53; +end + +53: begin +lut_X_data_00[15:0] <= raw_reg53; +lut_X_data_01[15:0] <= raw_reg54; +end + +54: begin +lut_X_data_00[15:0] <= raw_reg54; +lut_X_data_01[15:0] <= raw_reg55; +end + +55: begin +lut_X_data_00[15:0] <= raw_reg55; +lut_X_data_01[15:0] <= raw_reg56; +end + +56: begin +lut_X_data_00[15:0] <= raw_reg56; +lut_X_data_01[15:0] <= raw_reg57; +end + +57: begin +lut_X_data_00[15:0] <= raw_reg57; +lut_X_data_01[15:0] <= raw_reg58; +end + +58: begin +lut_X_data_00[15:0] <= raw_reg58; +lut_X_data_01[15:0] <= raw_reg59; +end + +59: begin +lut_X_data_00[15:0] <= raw_reg59; +lut_X_data_01[15:0] <= raw_reg60; +end + +60: begin +lut_X_data_00[15:0] <= raw_reg60; +lut_X_data_01[15:0] <= raw_reg61; +end + +61: begin +lut_X_data_00[15:0] <= raw_reg61; +lut_X_data_01[15:0] <= raw_reg62; +end + +62: begin +lut_X_data_00[15:0] <= raw_reg62; +lut_X_data_01[15:0] <= raw_reg63; +end + +63: begin +lut_X_data_00[15:0] <= raw_reg63; +lut_X_data_01[15:0] <= raw_reg64; +end + +64: begin +lut_X_data_00[15:0] <= raw_reg64; +lut_X_data_01[15:0] <= raw_reg64; +end +default: begin +lut_X_data_00[15:0] <= raw_reg0; +lut_X_data_01[15:0] <= raw_reg0; +end +endcase +end +end +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////// +///////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_Y_data_${m}0[15:0] <= {16{1'b0}}; +//: lut_Y_data_${m}1[15:0] <= {16{1'b0}}; +//: end else begin +//: if(load_din & lut_Y_sel[$m]) begin +//: if(dp2lut_Yinfo_${m}[16]) begin +//: lut_Y_data_${m}0[15:0] <= density_reg0; +//: lut_Y_data_${m}1[15:0] <= density_reg0; +//: end else if(dp2lut_Yinfo_${m}[17]) begin +//: lut_Y_data_${m}0[15:0] <= density_reg256; +//: lut_Y_data_${m}1[15:0] <= density_reg256; +//: end else begin +//: case(dp2lut_Y_entry_${m}[9:0]) +//: ); +//: foreach my $i (0..256-1) { +//: my $j = $i + 1; +//: print qq( +//: $i: begin +//: lut_Y_data_${m}0[15:0] <= density_reg${i}; +//: lut_Y_data_${m}1[15:0] <= density_reg${j}; +//: end +//: ); +//: } +//: print qq( +//: 256: begin +//: lut_Y_data_${m}0[15:0] <= density_reg256; +//: lut_Y_data_${m}1[15:0] <= density_reg256; +//: end +//: default: begin +//: lut_Y_data_${m}0[15:0] <= density_reg0; +//: lut_Y_data_${m}1[15:0] <= density_reg0; +//: end +//: endcase +//: end +//: end +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +lut_Y_data_00[15:0] <= {16{1'b0}}; +lut_Y_data_01[15:0] <= {16{1'b0}}; +end else begin +if(load_din & lut_Y_sel[0]) begin +if(dp2lut_Yinfo_0[16]) begin +lut_Y_data_00[15:0] <= density_reg0; +lut_Y_data_01[15:0] <= density_reg0; +end else if(dp2lut_Yinfo_0[17]) begin +lut_Y_data_00[15:0] <= density_reg256; +lut_Y_data_01[15:0] <= density_reg256; +end else begin +case(dp2lut_Y_entry_0[9:0]) + +0: begin +lut_Y_data_00[15:0] <= density_reg0; +lut_Y_data_01[15:0] <= density_reg1; +end + +1: begin +lut_Y_data_00[15:0] <= density_reg1; +lut_Y_data_01[15:0] <= density_reg2; +end + +2: begin +lut_Y_data_00[15:0] <= density_reg2; +lut_Y_data_01[15:0] <= density_reg3; +end + +3: begin +lut_Y_data_00[15:0] <= density_reg3; +lut_Y_data_01[15:0] <= density_reg4; +end + +4: begin +lut_Y_data_00[15:0] <= density_reg4; +lut_Y_data_01[15:0] <= density_reg5; +end + +5: begin +lut_Y_data_00[15:0] <= density_reg5; +lut_Y_data_01[15:0] <= density_reg6; +end + +6: begin +lut_Y_data_00[15:0] <= density_reg6; +lut_Y_data_01[15:0] <= density_reg7; +end + +7: begin +lut_Y_data_00[15:0] <= density_reg7; +lut_Y_data_01[15:0] <= density_reg8; +end + +8: begin +lut_Y_data_00[15:0] <= density_reg8; +lut_Y_data_01[15:0] <= density_reg9; +end + +9: begin +lut_Y_data_00[15:0] <= density_reg9; +lut_Y_data_01[15:0] <= density_reg10; +end + +10: begin +lut_Y_data_00[15:0] <= density_reg10; +lut_Y_data_01[15:0] <= density_reg11; +end + +11: begin +lut_Y_data_00[15:0] <= density_reg11; +lut_Y_data_01[15:0] <= density_reg12; +end + +12: begin +lut_Y_data_00[15:0] <= density_reg12; +lut_Y_data_01[15:0] <= density_reg13; +end + +13: begin +lut_Y_data_00[15:0] <= density_reg13; +lut_Y_data_01[15:0] <= density_reg14; +end + +14: begin +lut_Y_data_00[15:0] <= density_reg14; +lut_Y_data_01[15:0] <= density_reg15; +end + +15: begin +lut_Y_data_00[15:0] <= density_reg15; +lut_Y_data_01[15:0] <= density_reg16; +end + +16: begin +lut_Y_data_00[15:0] <= density_reg16; +lut_Y_data_01[15:0] <= density_reg17; +end + +17: begin +lut_Y_data_00[15:0] <= density_reg17; +lut_Y_data_01[15:0] <= density_reg18; +end + +18: begin +lut_Y_data_00[15:0] <= density_reg18; +lut_Y_data_01[15:0] <= density_reg19; +end + +19: begin +lut_Y_data_00[15:0] <= density_reg19; +lut_Y_data_01[15:0] <= density_reg20; +end + +20: begin +lut_Y_data_00[15:0] <= density_reg20; +lut_Y_data_01[15:0] <= density_reg21; +end + +21: begin +lut_Y_data_00[15:0] <= density_reg21; +lut_Y_data_01[15:0] <= density_reg22; +end + +22: begin +lut_Y_data_00[15:0] <= density_reg22; +lut_Y_data_01[15:0] <= density_reg23; +end + +23: begin +lut_Y_data_00[15:0] <= density_reg23; +lut_Y_data_01[15:0] <= density_reg24; +end + +24: begin +lut_Y_data_00[15:0] <= density_reg24; +lut_Y_data_01[15:0] <= density_reg25; +end + +25: begin +lut_Y_data_00[15:0] <= density_reg25; +lut_Y_data_01[15:0] <= density_reg26; +end + +26: begin +lut_Y_data_00[15:0] <= density_reg26; +lut_Y_data_01[15:0] <= density_reg27; +end + +27: begin +lut_Y_data_00[15:0] <= density_reg27; +lut_Y_data_01[15:0] <= density_reg28; +end + +28: begin +lut_Y_data_00[15:0] <= density_reg28; +lut_Y_data_01[15:0] <= density_reg29; +end + +29: begin +lut_Y_data_00[15:0] <= density_reg29; +lut_Y_data_01[15:0] <= density_reg30; +end + +30: begin +lut_Y_data_00[15:0] <= density_reg30; +lut_Y_data_01[15:0] <= density_reg31; +end + +31: begin +lut_Y_data_00[15:0] <= density_reg31; +lut_Y_data_01[15:0] <= density_reg32; +end + +32: begin +lut_Y_data_00[15:0] <= density_reg32; +lut_Y_data_01[15:0] <= density_reg33; +end + +33: begin +lut_Y_data_00[15:0] <= density_reg33; +lut_Y_data_01[15:0] <= density_reg34; +end + +34: begin +lut_Y_data_00[15:0] <= density_reg34; +lut_Y_data_01[15:0] <= density_reg35; +end + +35: begin +lut_Y_data_00[15:0] <= density_reg35; +lut_Y_data_01[15:0] <= density_reg36; +end + +36: begin +lut_Y_data_00[15:0] <= density_reg36; +lut_Y_data_01[15:0] <= density_reg37; +end + +37: begin +lut_Y_data_00[15:0] <= density_reg37; +lut_Y_data_01[15:0] <= density_reg38; +end + +38: begin +lut_Y_data_00[15:0] <= density_reg38; +lut_Y_data_01[15:0] <= density_reg39; +end + +39: begin +lut_Y_data_00[15:0] <= density_reg39; +lut_Y_data_01[15:0] <= density_reg40; +end + +40: begin +lut_Y_data_00[15:0] <= density_reg40; +lut_Y_data_01[15:0] <= density_reg41; +end + +41: begin +lut_Y_data_00[15:0] <= density_reg41; +lut_Y_data_01[15:0] <= density_reg42; +end + +42: begin +lut_Y_data_00[15:0] <= density_reg42; +lut_Y_data_01[15:0] <= density_reg43; +end + +43: begin +lut_Y_data_00[15:0] <= density_reg43; +lut_Y_data_01[15:0] <= density_reg44; +end + +44: begin +lut_Y_data_00[15:0] <= density_reg44; +lut_Y_data_01[15:0] <= density_reg45; +end + +45: begin +lut_Y_data_00[15:0] <= density_reg45; +lut_Y_data_01[15:0] <= density_reg46; +end + +46: begin +lut_Y_data_00[15:0] <= density_reg46; +lut_Y_data_01[15:0] <= density_reg47; +end + +47: begin +lut_Y_data_00[15:0] <= density_reg47; +lut_Y_data_01[15:0] <= density_reg48; +end + +48: begin +lut_Y_data_00[15:0] <= density_reg48; +lut_Y_data_01[15:0] <= density_reg49; +end + +49: begin +lut_Y_data_00[15:0] <= density_reg49; +lut_Y_data_01[15:0] <= density_reg50; +end + +50: begin +lut_Y_data_00[15:0] <= density_reg50; +lut_Y_data_01[15:0] <= density_reg51; +end + +51: begin +lut_Y_data_00[15:0] <= density_reg51; +lut_Y_data_01[15:0] <= density_reg52; +end + +52: begin +lut_Y_data_00[15:0] <= density_reg52; +lut_Y_data_01[15:0] <= density_reg53; +end + +53: begin +lut_Y_data_00[15:0] <= density_reg53; +lut_Y_data_01[15:0] <= density_reg54; +end + +54: begin +lut_Y_data_00[15:0] <= density_reg54; +lut_Y_data_01[15:0] <= density_reg55; +end + +55: begin +lut_Y_data_00[15:0] <= density_reg55; +lut_Y_data_01[15:0] <= density_reg56; +end + +56: begin +lut_Y_data_00[15:0] <= density_reg56; +lut_Y_data_01[15:0] <= density_reg57; +end + +57: begin +lut_Y_data_00[15:0] <= density_reg57; +lut_Y_data_01[15:0] <= density_reg58; +end + +58: begin +lut_Y_data_00[15:0] <= density_reg58; +lut_Y_data_01[15:0] <= density_reg59; +end + +59: begin +lut_Y_data_00[15:0] <= density_reg59; +lut_Y_data_01[15:0] <= density_reg60; +end + +60: begin +lut_Y_data_00[15:0] <= density_reg60; +lut_Y_data_01[15:0] <= density_reg61; +end + +61: begin +lut_Y_data_00[15:0] <= density_reg61; +lut_Y_data_01[15:0] <= density_reg62; +end + +62: begin +lut_Y_data_00[15:0] <= density_reg62; +lut_Y_data_01[15:0] <= density_reg63; +end + +63: begin +lut_Y_data_00[15:0] <= density_reg63; +lut_Y_data_01[15:0] <= density_reg64; +end + +64: begin +lut_Y_data_00[15:0] <= density_reg64; +lut_Y_data_01[15:0] <= density_reg65; +end + +65: begin +lut_Y_data_00[15:0] <= density_reg65; +lut_Y_data_01[15:0] <= density_reg66; +end + +66: begin +lut_Y_data_00[15:0] <= density_reg66; +lut_Y_data_01[15:0] <= density_reg67; +end + +67: begin +lut_Y_data_00[15:0] <= density_reg67; +lut_Y_data_01[15:0] <= density_reg68; +end + +68: begin +lut_Y_data_00[15:0] <= density_reg68; +lut_Y_data_01[15:0] <= density_reg69; +end + +69: begin +lut_Y_data_00[15:0] <= density_reg69; +lut_Y_data_01[15:0] <= density_reg70; +end + +70: begin +lut_Y_data_00[15:0] <= density_reg70; +lut_Y_data_01[15:0] <= density_reg71; +end + +71: begin +lut_Y_data_00[15:0] <= density_reg71; +lut_Y_data_01[15:0] <= density_reg72; +end + +72: begin +lut_Y_data_00[15:0] <= density_reg72; +lut_Y_data_01[15:0] <= density_reg73; +end + +73: begin +lut_Y_data_00[15:0] <= density_reg73; +lut_Y_data_01[15:0] <= density_reg74; +end + +74: begin +lut_Y_data_00[15:0] <= density_reg74; +lut_Y_data_01[15:0] <= density_reg75; +end + +75: begin +lut_Y_data_00[15:0] <= density_reg75; +lut_Y_data_01[15:0] <= density_reg76; +end + +76: begin +lut_Y_data_00[15:0] <= density_reg76; +lut_Y_data_01[15:0] <= density_reg77; +end + +77: begin +lut_Y_data_00[15:0] <= density_reg77; +lut_Y_data_01[15:0] <= density_reg78; +end + +78: begin +lut_Y_data_00[15:0] <= density_reg78; +lut_Y_data_01[15:0] <= density_reg79; +end + +79: begin +lut_Y_data_00[15:0] <= density_reg79; +lut_Y_data_01[15:0] <= density_reg80; +end + +80: begin +lut_Y_data_00[15:0] <= density_reg80; +lut_Y_data_01[15:0] <= density_reg81; +end + +81: begin +lut_Y_data_00[15:0] <= density_reg81; +lut_Y_data_01[15:0] <= density_reg82; +end + +82: begin +lut_Y_data_00[15:0] <= density_reg82; +lut_Y_data_01[15:0] <= density_reg83; +end + +83: begin +lut_Y_data_00[15:0] <= density_reg83; +lut_Y_data_01[15:0] <= density_reg84; +end + +84: begin +lut_Y_data_00[15:0] <= density_reg84; +lut_Y_data_01[15:0] <= density_reg85; +end + +85: begin +lut_Y_data_00[15:0] <= density_reg85; +lut_Y_data_01[15:0] <= density_reg86; +end + +86: begin +lut_Y_data_00[15:0] <= density_reg86; +lut_Y_data_01[15:0] <= density_reg87; +end + +87: begin +lut_Y_data_00[15:0] <= density_reg87; +lut_Y_data_01[15:0] <= density_reg88; +end + +88: begin +lut_Y_data_00[15:0] <= density_reg88; +lut_Y_data_01[15:0] <= density_reg89; +end + +89: begin +lut_Y_data_00[15:0] <= density_reg89; +lut_Y_data_01[15:0] <= density_reg90; +end + +90: begin +lut_Y_data_00[15:0] <= density_reg90; +lut_Y_data_01[15:0] <= density_reg91; +end + +91: begin +lut_Y_data_00[15:0] <= density_reg91; +lut_Y_data_01[15:0] <= density_reg92; +end + +92: begin +lut_Y_data_00[15:0] <= density_reg92; +lut_Y_data_01[15:0] <= density_reg93; +end + +93: begin +lut_Y_data_00[15:0] <= density_reg93; +lut_Y_data_01[15:0] <= density_reg94; +end + +94: begin +lut_Y_data_00[15:0] <= density_reg94; +lut_Y_data_01[15:0] <= density_reg95; +end + +95: begin +lut_Y_data_00[15:0] <= density_reg95; +lut_Y_data_01[15:0] <= density_reg96; +end + +96: begin +lut_Y_data_00[15:0] <= density_reg96; +lut_Y_data_01[15:0] <= density_reg97; +end + +97: begin +lut_Y_data_00[15:0] <= density_reg97; +lut_Y_data_01[15:0] <= density_reg98; +end + +98: begin +lut_Y_data_00[15:0] <= density_reg98; +lut_Y_data_01[15:0] <= density_reg99; +end + +99: begin +lut_Y_data_00[15:0] <= density_reg99; +lut_Y_data_01[15:0] <= density_reg100; +end + +100: begin +lut_Y_data_00[15:0] <= density_reg100; +lut_Y_data_01[15:0] <= density_reg101; +end + +101: begin +lut_Y_data_00[15:0] <= density_reg101; +lut_Y_data_01[15:0] <= density_reg102; +end + +102: begin +lut_Y_data_00[15:0] <= density_reg102; +lut_Y_data_01[15:0] <= density_reg103; +end + +103: begin +lut_Y_data_00[15:0] <= density_reg103; +lut_Y_data_01[15:0] <= density_reg104; +end + +104: begin +lut_Y_data_00[15:0] <= density_reg104; +lut_Y_data_01[15:0] <= density_reg105; +end + +105: begin +lut_Y_data_00[15:0] <= density_reg105; +lut_Y_data_01[15:0] <= density_reg106; +end + +106: begin +lut_Y_data_00[15:0] <= density_reg106; +lut_Y_data_01[15:0] <= density_reg107; +end + +107: begin +lut_Y_data_00[15:0] <= density_reg107; +lut_Y_data_01[15:0] <= density_reg108; +end + +108: begin +lut_Y_data_00[15:0] <= density_reg108; +lut_Y_data_01[15:0] <= density_reg109; +end + +109: begin +lut_Y_data_00[15:0] <= density_reg109; +lut_Y_data_01[15:0] <= density_reg110; +end + +110: begin +lut_Y_data_00[15:0] <= density_reg110; +lut_Y_data_01[15:0] <= density_reg111; +end + +111: begin +lut_Y_data_00[15:0] <= density_reg111; +lut_Y_data_01[15:0] <= density_reg112; +end + +112: begin +lut_Y_data_00[15:0] <= density_reg112; +lut_Y_data_01[15:0] <= density_reg113; +end + +113: begin +lut_Y_data_00[15:0] <= density_reg113; +lut_Y_data_01[15:0] <= density_reg114; +end + +114: begin +lut_Y_data_00[15:0] <= density_reg114; +lut_Y_data_01[15:0] <= density_reg115; +end + +115: begin +lut_Y_data_00[15:0] <= density_reg115; +lut_Y_data_01[15:0] <= density_reg116; +end + +116: begin +lut_Y_data_00[15:0] <= density_reg116; +lut_Y_data_01[15:0] <= density_reg117; +end + +117: begin +lut_Y_data_00[15:0] <= density_reg117; +lut_Y_data_01[15:0] <= density_reg118; +end + +118: begin +lut_Y_data_00[15:0] <= density_reg118; +lut_Y_data_01[15:0] <= density_reg119; +end + +119: begin +lut_Y_data_00[15:0] <= density_reg119; +lut_Y_data_01[15:0] <= density_reg120; +end + +120: begin +lut_Y_data_00[15:0] <= density_reg120; +lut_Y_data_01[15:0] <= density_reg121; +end + +121: begin +lut_Y_data_00[15:0] <= density_reg121; +lut_Y_data_01[15:0] <= density_reg122; +end + +122: begin +lut_Y_data_00[15:0] <= density_reg122; +lut_Y_data_01[15:0] <= density_reg123; +end + +123: begin +lut_Y_data_00[15:0] <= density_reg123; +lut_Y_data_01[15:0] <= density_reg124; +end + +124: begin +lut_Y_data_00[15:0] <= density_reg124; +lut_Y_data_01[15:0] <= density_reg125; +end + +125: begin +lut_Y_data_00[15:0] <= density_reg125; +lut_Y_data_01[15:0] <= density_reg126; +end + +126: begin +lut_Y_data_00[15:0] <= density_reg126; +lut_Y_data_01[15:0] <= density_reg127; +end + +127: begin +lut_Y_data_00[15:0] <= density_reg127; +lut_Y_data_01[15:0] <= density_reg128; +end + +128: begin +lut_Y_data_00[15:0] <= density_reg128; +lut_Y_data_01[15:0] <= density_reg129; +end + +129: begin +lut_Y_data_00[15:0] <= density_reg129; +lut_Y_data_01[15:0] <= density_reg130; +end + +130: begin +lut_Y_data_00[15:0] <= density_reg130; +lut_Y_data_01[15:0] <= density_reg131; +end + +131: begin +lut_Y_data_00[15:0] <= density_reg131; +lut_Y_data_01[15:0] <= density_reg132; +end + +132: begin +lut_Y_data_00[15:0] <= density_reg132; +lut_Y_data_01[15:0] <= density_reg133; +end + +133: begin +lut_Y_data_00[15:0] <= density_reg133; +lut_Y_data_01[15:0] <= density_reg134; +end + +134: begin +lut_Y_data_00[15:0] <= density_reg134; +lut_Y_data_01[15:0] <= density_reg135; +end + +135: begin +lut_Y_data_00[15:0] <= density_reg135; +lut_Y_data_01[15:0] <= density_reg136; +end + +136: begin +lut_Y_data_00[15:0] <= density_reg136; +lut_Y_data_01[15:0] <= density_reg137; +end + +137: begin +lut_Y_data_00[15:0] <= density_reg137; +lut_Y_data_01[15:0] <= density_reg138; +end + +138: begin +lut_Y_data_00[15:0] <= density_reg138; +lut_Y_data_01[15:0] <= density_reg139; +end + +139: begin +lut_Y_data_00[15:0] <= density_reg139; +lut_Y_data_01[15:0] <= density_reg140; +end + +140: begin +lut_Y_data_00[15:0] <= density_reg140; +lut_Y_data_01[15:0] <= density_reg141; +end + +141: begin +lut_Y_data_00[15:0] <= density_reg141; +lut_Y_data_01[15:0] <= density_reg142; +end + +142: begin +lut_Y_data_00[15:0] <= density_reg142; +lut_Y_data_01[15:0] <= density_reg143; +end + +143: begin +lut_Y_data_00[15:0] <= density_reg143; +lut_Y_data_01[15:0] <= density_reg144; +end + +144: begin +lut_Y_data_00[15:0] <= density_reg144; +lut_Y_data_01[15:0] <= density_reg145; +end + +145: begin +lut_Y_data_00[15:0] <= density_reg145; +lut_Y_data_01[15:0] <= density_reg146; +end + +146: begin +lut_Y_data_00[15:0] <= density_reg146; +lut_Y_data_01[15:0] <= density_reg147; +end + +147: begin +lut_Y_data_00[15:0] <= density_reg147; +lut_Y_data_01[15:0] <= density_reg148; +end + +148: begin +lut_Y_data_00[15:0] <= density_reg148; +lut_Y_data_01[15:0] <= density_reg149; +end + +149: begin +lut_Y_data_00[15:0] <= density_reg149; +lut_Y_data_01[15:0] <= density_reg150; +end + +150: begin +lut_Y_data_00[15:0] <= density_reg150; +lut_Y_data_01[15:0] <= density_reg151; +end + +151: begin +lut_Y_data_00[15:0] <= density_reg151; +lut_Y_data_01[15:0] <= density_reg152; +end + +152: begin +lut_Y_data_00[15:0] <= density_reg152; +lut_Y_data_01[15:0] <= density_reg153; +end + +153: begin +lut_Y_data_00[15:0] <= density_reg153; +lut_Y_data_01[15:0] <= density_reg154; +end + +154: begin +lut_Y_data_00[15:0] <= density_reg154; +lut_Y_data_01[15:0] <= density_reg155; +end + +155: begin +lut_Y_data_00[15:0] <= density_reg155; +lut_Y_data_01[15:0] <= density_reg156; +end + +156: begin +lut_Y_data_00[15:0] <= density_reg156; +lut_Y_data_01[15:0] <= density_reg157; +end + +157: begin +lut_Y_data_00[15:0] <= density_reg157; +lut_Y_data_01[15:0] <= density_reg158; +end + +158: begin +lut_Y_data_00[15:0] <= density_reg158; +lut_Y_data_01[15:0] <= density_reg159; +end + +159: begin +lut_Y_data_00[15:0] <= density_reg159; +lut_Y_data_01[15:0] <= density_reg160; +end + +160: begin +lut_Y_data_00[15:0] <= density_reg160; +lut_Y_data_01[15:0] <= density_reg161; +end + +161: begin +lut_Y_data_00[15:0] <= density_reg161; +lut_Y_data_01[15:0] <= density_reg162; +end + +162: begin +lut_Y_data_00[15:0] <= density_reg162; +lut_Y_data_01[15:0] <= density_reg163; +end + +163: begin +lut_Y_data_00[15:0] <= density_reg163; +lut_Y_data_01[15:0] <= density_reg164; +end + +164: begin +lut_Y_data_00[15:0] <= density_reg164; +lut_Y_data_01[15:0] <= density_reg165; +end + +165: begin +lut_Y_data_00[15:0] <= density_reg165; +lut_Y_data_01[15:0] <= density_reg166; +end + +166: begin +lut_Y_data_00[15:0] <= density_reg166; +lut_Y_data_01[15:0] <= density_reg167; +end + +167: begin +lut_Y_data_00[15:0] <= density_reg167; +lut_Y_data_01[15:0] <= density_reg168; +end + +168: begin +lut_Y_data_00[15:0] <= density_reg168; +lut_Y_data_01[15:0] <= density_reg169; +end + +169: begin +lut_Y_data_00[15:0] <= density_reg169; +lut_Y_data_01[15:0] <= density_reg170; +end + +170: begin +lut_Y_data_00[15:0] <= density_reg170; +lut_Y_data_01[15:0] <= density_reg171; +end + +171: begin +lut_Y_data_00[15:0] <= density_reg171; +lut_Y_data_01[15:0] <= density_reg172; +end + +172: begin +lut_Y_data_00[15:0] <= density_reg172; +lut_Y_data_01[15:0] <= density_reg173; +end + +173: begin +lut_Y_data_00[15:0] <= density_reg173; +lut_Y_data_01[15:0] <= density_reg174; +end + +174: begin +lut_Y_data_00[15:0] <= density_reg174; +lut_Y_data_01[15:0] <= density_reg175; +end + +175: begin +lut_Y_data_00[15:0] <= density_reg175; +lut_Y_data_01[15:0] <= density_reg176; +end + +176: begin +lut_Y_data_00[15:0] <= density_reg176; +lut_Y_data_01[15:0] <= density_reg177; +end + +177: begin +lut_Y_data_00[15:0] <= density_reg177; +lut_Y_data_01[15:0] <= density_reg178; +end + +178: begin +lut_Y_data_00[15:0] <= density_reg178; +lut_Y_data_01[15:0] <= density_reg179; +end + +179: begin +lut_Y_data_00[15:0] <= density_reg179; +lut_Y_data_01[15:0] <= density_reg180; +end + +180: begin +lut_Y_data_00[15:0] <= density_reg180; +lut_Y_data_01[15:0] <= density_reg181; +end + +181: begin +lut_Y_data_00[15:0] <= density_reg181; +lut_Y_data_01[15:0] <= density_reg182; +end + +182: begin +lut_Y_data_00[15:0] <= density_reg182; +lut_Y_data_01[15:0] <= density_reg183; +end + +183: begin +lut_Y_data_00[15:0] <= density_reg183; +lut_Y_data_01[15:0] <= density_reg184; +end + +184: begin +lut_Y_data_00[15:0] <= density_reg184; +lut_Y_data_01[15:0] <= density_reg185; +end + +185: begin +lut_Y_data_00[15:0] <= density_reg185; +lut_Y_data_01[15:0] <= density_reg186; +end + +186: begin +lut_Y_data_00[15:0] <= density_reg186; +lut_Y_data_01[15:0] <= density_reg187; +end + +187: begin +lut_Y_data_00[15:0] <= density_reg187; +lut_Y_data_01[15:0] <= density_reg188; +end + +188: begin +lut_Y_data_00[15:0] <= density_reg188; +lut_Y_data_01[15:0] <= density_reg189; +end + +189: begin +lut_Y_data_00[15:0] <= density_reg189; +lut_Y_data_01[15:0] <= density_reg190; +end + +190: begin +lut_Y_data_00[15:0] <= density_reg190; +lut_Y_data_01[15:0] <= density_reg191; +end + +191: begin +lut_Y_data_00[15:0] <= density_reg191; +lut_Y_data_01[15:0] <= density_reg192; +end + +192: begin +lut_Y_data_00[15:0] <= density_reg192; +lut_Y_data_01[15:0] <= density_reg193; +end + +193: begin +lut_Y_data_00[15:0] <= density_reg193; +lut_Y_data_01[15:0] <= density_reg194; +end + +194: begin +lut_Y_data_00[15:0] <= density_reg194; +lut_Y_data_01[15:0] <= density_reg195; +end + +195: begin +lut_Y_data_00[15:0] <= density_reg195; +lut_Y_data_01[15:0] <= density_reg196; +end + +196: begin +lut_Y_data_00[15:0] <= density_reg196; +lut_Y_data_01[15:0] <= density_reg197; +end + +197: begin +lut_Y_data_00[15:0] <= density_reg197; +lut_Y_data_01[15:0] <= density_reg198; +end + +198: begin +lut_Y_data_00[15:0] <= density_reg198; +lut_Y_data_01[15:0] <= density_reg199; +end + +199: begin +lut_Y_data_00[15:0] <= density_reg199; +lut_Y_data_01[15:0] <= density_reg200; +end + +200: begin +lut_Y_data_00[15:0] <= density_reg200; +lut_Y_data_01[15:0] <= density_reg201; +end + +201: begin +lut_Y_data_00[15:0] <= density_reg201; +lut_Y_data_01[15:0] <= density_reg202; +end + +202: begin +lut_Y_data_00[15:0] <= density_reg202; +lut_Y_data_01[15:0] <= density_reg203; +end + +203: begin +lut_Y_data_00[15:0] <= density_reg203; +lut_Y_data_01[15:0] <= density_reg204; +end + +204: begin +lut_Y_data_00[15:0] <= density_reg204; +lut_Y_data_01[15:0] <= density_reg205; +end + +205: begin +lut_Y_data_00[15:0] <= density_reg205; +lut_Y_data_01[15:0] <= density_reg206; +end + +206: begin +lut_Y_data_00[15:0] <= density_reg206; +lut_Y_data_01[15:0] <= density_reg207; +end + +207: begin +lut_Y_data_00[15:0] <= density_reg207; +lut_Y_data_01[15:0] <= density_reg208; +end + +208: begin +lut_Y_data_00[15:0] <= density_reg208; +lut_Y_data_01[15:0] <= density_reg209; +end + +209: begin +lut_Y_data_00[15:0] <= density_reg209; +lut_Y_data_01[15:0] <= density_reg210; +end + +210: begin +lut_Y_data_00[15:0] <= density_reg210; +lut_Y_data_01[15:0] <= density_reg211; +end + +211: begin +lut_Y_data_00[15:0] <= density_reg211; +lut_Y_data_01[15:0] <= density_reg212; +end + +212: begin +lut_Y_data_00[15:0] <= density_reg212; +lut_Y_data_01[15:0] <= density_reg213; +end + +213: begin +lut_Y_data_00[15:0] <= density_reg213; +lut_Y_data_01[15:0] <= density_reg214; +end + +214: begin +lut_Y_data_00[15:0] <= density_reg214; +lut_Y_data_01[15:0] <= density_reg215; +end + +215: begin +lut_Y_data_00[15:0] <= density_reg215; +lut_Y_data_01[15:0] <= density_reg216; +end + +216: begin +lut_Y_data_00[15:0] <= density_reg216; +lut_Y_data_01[15:0] <= density_reg217; +end + +217: begin +lut_Y_data_00[15:0] <= density_reg217; +lut_Y_data_01[15:0] <= density_reg218; +end + +218: begin +lut_Y_data_00[15:0] <= density_reg218; +lut_Y_data_01[15:0] <= density_reg219; +end + +219: begin +lut_Y_data_00[15:0] <= density_reg219; +lut_Y_data_01[15:0] <= density_reg220; +end + +220: begin +lut_Y_data_00[15:0] <= density_reg220; +lut_Y_data_01[15:0] <= density_reg221; +end + +221: begin +lut_Y_data_00[15:0] <= density_reg221; +lut_Y_data_01[15:0] <= density_reg222; +end + +222: begin +lut_Y_data_00[15:0] <= density_reg222; +lut_Y_data_01[15:0] <= density_reg223; +end + +223: begin +lut_Y_data_00[15:0] <= density_reg223; +lut_Y_data_01[15:0] <= density_reg224; +end + +224: begin +lut_Y_data_00[15:0] <= density_reg224; +lut_Y_data_01[15:0] <= density_reg225; +end + +225: begin +lut_Y_data_00[15:0] <= density_reg225; +lut_Y_data_01[15:0] <= density_reg226; +end + +226: begin +lut_Y_data_00[15:0] <= density_reg226; +lut_Y_data_01[15:0] <= density_reg227; +end + +227: begin +lut_Y_data_00[15:0] <= density_reg227; +lut_Y_data_01[15:0] <= density_reg228; +end + +228: begin +lut_Y_data_00[15:0] <= density_reg228; +lut_Y_data_01[15:0] <= density_reg229; +end + +229: begin +lut_Y_data_00[15:0] <= density_reg229; +lut_Y_data_01[15:0] <= density_reg230; +end + +230: begin +lut_Y_data_00[15:0] <= density_reg230; +lut_Y_data_01[15:0] <= density_reg231; +end + +231: begin +lut_Y_data_00[15:0] <= density_reg231; +lut_Y_data_01[15:0] <= density_reg232; +end + +232: begin +lut_Y_data_00[15:0] <= density_reg232; +lut_Y_data_01[15:0] <= density_reg233; +end + +233: begin +lut_Y_data_00[15:0] <= density_reg233; +lut_Y_data_01[15:0] <= density_reg234; +end + +234: begin +lut_Y_data_00[15:0] <= density_reg234; +lut_Y_data_01[15:0] <= density_reg235; +end + +235: begin +lut_Y_data_00[15:0] <= density_reg235; +lut_Y_data_01[15:0] <= density_reg236; +end + +236: begin +lut_Y_data_00[15:0] <= density_reg236; +lut_Y_data_01[15:0] <= density_reg237; +end + +237: begin +lut_Y_data_00[15:0] <= density_reg237; +lut_Y_data_01[15:0] <= density_reg238; +end + +238: begin +lut_Y_data_00[15:0] <= density_reg238; +lut_Y_data_01[15:0] <= density_reg239; +end + +239: begin +lut_Y_data_00[15:0] <= density_reg239; +lut_Y_data_01[15:0] <= density_reg240; +end + +240: begin +lut_Y_data_00[15:0] <= density_reg240; +lut_Y_data_01[15:0] <= density_reg241; +end + +241: begin +lut_Y_data_00[15:0] <= density_reg241; +lut_Y_data_01[15:0] <= density_reg242; +end + +242: begin +lut_Y_data_00[15:0] <= density_reg242; +lut_Y_data_01[15:0] <= density_reg243; +end + +243: begin +lut_Y_data_00[15:0] <= density_reg243; +lut_Y_data_01[15:0] <= density_reg244; +end + +244: begin +lut_Y_data_00[15:0] <= density_reg244; +lut_Y_data_01[15:0] <= density_reg245; +end + +245: begin +lut_Y_data_00[15:0] <= density_reg245; +lut_Y_data_01[15:0] <= density_reg246; +end + +246: begin +lut_Y_data_00[15:0] <= density_reg246; +lut_Y_data_01[15:0] <= density_reg247; +end + +247: begin +lut_Y_data_00[15:0] <= density_reg247; +lut_Y_data_01[15:0] <= density_reg248; +end + +248: begin +lut_Y_data_00[15:0] <= density_reg248; +lut_Y_data_01[15:0] <= density_reg249; +end + +249: begin +lut_Y_data_00[15:0] <= density_reg249; +lut_Y_data_01[15:0] <= density_reg250; +end + +250: begin +lut_Y_data_00[15:0] <= density_reg250; +lut_Y_data_01[15:0] <= density_reg251; +end + +251: begin +lut_Y_data_00[15:0] <= density_reg251; +lut_Y_data_01[15:0] <= density_reg252; +end + +252: begin +lut_Y_data_00[15:0] <= density_reg252; +lut_Y_data_01[15:0] <= density_reg253; +end + +253: begin +lut_Y_data_00[15:0] <= density_reg253; +lut_Y_data_01[15:0] <= density_reg254; +end + +254: begin +lut_Y_data_00[15:0] <= density_reg254; +lut_Y_data_01[15:0] <= density_reg255; +end + +255: begin +lut_Y_data_00[15:0] <= density_reg255; +lut_Y_data_01[15:0] <= density_reg256; +end + +256: begin +lut_Y_data_00[15:0] <= density_reg256; +lut_Y_data_01[15:0] <= density_reg256; +end +default: begin +lut_Y_data_00[15:0] <= density_reg0; +lut_Y_data_01[15:0] <= density_reg0; +end +endcase +end +end +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_X_info_${m} <= {18{1'b0}}; +//: end else if (load_din) begin +//: lut_X_info_${m} <= dp2lut_Xinfo_${m}[17:0]; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +lut_X_info_0 <= {18{1'b0}}; +end else if (load_din) begin +lut_X_info_0 <= dp2lut_Xinfo_0[17:0]; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lutX_sel <= {1{1'b0}}; + end else if (load_din) begin + lutX_sel <= lut_X_sel[1 -1:0]; + end +end +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_Y_info_${m} <= {18{1'b0}}; +//: end else if (load_din) begin +//: lut_Y_info_${m} <= dp2lut_Yinfo_${m}[17:0]; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +lut_Y_info_0 <= {18{1'b0}}; +end else if (load_din) begin +lut_Y_info_0 <= dp2lut_Yinfo_0[17:0]; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lutY_sel <= {1{1'b0}}; + end else if (load_din) begin + lutY_sel <= lut_Y_sel[1 -1:0]; + end +end +//////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign lutX_data_${m}0[15:0] = lutX_sel[$m] ? lut_X_data_${m}0[15:0] : (lutY_sel[$m] ? lut_Y_data_${m}0[15:0] : 16'd0); +//: assign lutX_data_${m}1[15:0] = lutX_sel[$m] ? lut_X_data_${m}1[15:0] : (lutY_sel[$m] ? lut_Y_data_${m}1[15:0] : 16'd0); +//: assign lutX_info_${m}[15:0] = lutX_sel[$m] ? lut_X_info_${m}[15:0] : (lutY_sel[$m] ? lut_Y_info_${m}[15:0] : 16'd0); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign lutX_data_00[15:0] = lutX_sel[0] ? lut_X_data_00[15:0] : (lutY_sel[0] ? lut_Y_data_00[15:0] : 16'd0); +assign lutX_data_01[15:0] = lutX_sel[0] ? lut_X_data_01[15:0] : (lutY_sel[0] ? lut_Y_data_01[15:0] : 16'd0); +assign lutX_info_0[15:0] = lutX_sel[0] ? lut_X_info_0[15:0] : (lutY_sel[0] ? lut_Y_info_0[15:0] : 16'd0); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut2intp_pvld <= 1'b0; + end else begin + if(dp2lut_pvld) + lut2intp_pvld <= 1'b1; + else if(lut2intp_prdy) + lut2intp_pvld <= 1'b0; + end +end +/////////////////////////////////////////////////////////////// +//output data +/////////////////////////////////////////////////////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign lut2intp_X_data_${m}0[31:0] = {{16{lutX_data_${m}0[15]}},lutX_data_${m}0[15:0]}; +//: assign lut2intp_X_data_${m}1[31:0] = {{16{lutX_data_${m}1[15]}},lutX_data_${m}1[15:0]}; +//: assign lut2intp_X_data_${m}0_17b[16:0] = {lutX_data_${m}0[15],lutX_data_${m}0[15:0]}; +//: assign lut2intp_X_info_${m}[19:0] = {lut_Y_info_${m}[17:16],lut_X_info_${m}[17:16],lutX_info_${m}[15:0]}; +//: assign lut2intp_X_sel[$m] = lutX_sel[$m]; +//: assign lut2intp_Y_sel[$m] = lutY_sel[$m]; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign lut2intp_X_data_00[31:0] = {{16{lutX_data_00[15]}},lutX_data_00[15:0]}; +assign lut2intp_X_data_01[31:0] = {{16{lutX_data_01[15]}},lutX_data_01[15:0]}; +assign lut2intp_X_data_00_17b[16:0] = {lutX_data_00[15],lutX_data_00[15:0]}; +assign lut2intp_X_info_0[19:0] = {lut_Y_info_0[17:16],lut_X_info_0[17:16],lutX_info_0[15:0]}; +assign lut2intp_X_sel[0] = lutX_sel[0]; +assign lut2intp_Y_sel[0] = lutY_sel[0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////// +endmodule // NV_NVDLA_CDP_DP_lut diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v.vcp new file mode 100644 index 0000000..ad608e6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v.vcp @@ -0,0 +1,462 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_lut.v +module NV_NVDLA_CDP_DP_lut ( + nvdla_core_clk //|< i + ,nvdla_core_clk_orig //|< i + ,nvdla_core_rstn //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,dp2lut_X_entry_${m} +//: ,dp2lut_Xinfo_${m} +//: ,dp2lut_Y_entry_${m} +//: ,dp2lut_Yinfo_${m} +//: ); +//: } + ,dp2lut_pvld //|< i + ,lut2intp_prdy //|< i + ,reg2dp_lut_access_type //|< i + ,reg2dp_lut_addr //|< i + ,reg2dp_lut_data //|< i + ,reg2dp_lut_data_trigger //|< i + ,reg2dp_lut_hybrid_priority //|< i + ,reg2dp_lut_oflow_priority //|< i + ,reg2dp_lut_table_id //|< i + ,reg2dp_lut_uflow_priority //|< i + ,dp2lut_prdy //|> o + ,dp2reg_lut_data //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,lut2intp_X_data_${m}0 //|> o +//: ,lut2intp_X_data_${m}0_17b //|> o +//: ,lut2intp_X_data_${m}1 //|> o +//: ,lut2intp_X_info_${m} //|> o +//: ); +//: } + ,lut2intp_X_sel //|> o + ,lut2intp_Y_sel //|> o + ,lut2intp_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_clk_orig; +input nvdla_core_rstn; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: input [9:0] dp2lut_X_entry_${m}; +//: input [17:0] dp2lut_Xinfo_${m}; +//: input [9:0] dp2lut_Y_entry_${m}; +//: input [17:0] dp2lut_Yinfo_${m}; +//: ); +//: } +input dp2lut_pvld; +input lut2intp_prdy; +input reg2dp_lut_access_type; +input [9:0] reg2dp_lut_addr; +input [15:0] reg2dp_lut_data; +input reg2dp_lut_data_trigger; +input reg2dp_lut_hybrid_priority; +input reg2dp_lut_oflow_priority; +input reg2dp_lut_table_id; +input reg2dp_lut_uflow_priority; +output dp2lut_prdy; +output [15:0] dp2reg_lut_data; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: output [31:0] lut2intp_X_data_${m}0; +//: output [16:0] lut2intp_X_data_${m}0_17b; +//: output [31:0] lut2intp_X_data_${m}1; +//: output [19:0] lut2intp_X_info_${m}; +//: ); +//: } +output [1 -1:0] lut2intp_X_sel; +output [1 -1:0] lut2intp_Y_sel; +output lut2intp_pvld; +//////////////////////////////////////////////////////////////////////////// +reg [15:0] density_out; +//: foreach my $m (0..256) { +//: print qq( +//: reg [15:0] density_reg$m; +//: ); +//: } +reg lut2intp_pvld; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [31:0] lut2intp_X_data_${m}0; +//: wire [16:0] lut2intp_X_data_${m}0_17b; +//: wire [31:0] lut2intp_X_data_${m}1; +//: wire [19:0] lut2intp_X_info_${m}; +//: ); +//: } +wire [1 -1:0] lut2intp_X_sel; +wire [1 -1:0] lut2intp_Y_sel; +reg [1 -1:0] lutX_sel; +reg [1 -1:0] lutY_sel; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: reg [15:0] lut_X_data_${m}0; +//: reg [15:0] lut_X_data_${m}1; +//: reg [17:0] lut_X_info_${m}; +//: reg [15:0] lut_Y_data_${m}0; +//: reg [15:0] lut_Y_data_${m}1; +//: reg [17:0] lut_Y_info_${m}; +//: ); +//: } +reg [1 -1:0] lut_X_sel; +reg [1 -1:0] lut_Y_sel; +reg [15:0] raw_out; +//: foreach my $m (0..64) { +//: print qq( +//: reg [15:0] raw_reg$m; +//: ); +//: } +wire both_hybrid_sel; +wire both_of_sel; +wire both_uf_sel; +wire dp2lut_prdy_f; +wire load_din; +// my $k = 1/2; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [15:0] lutX_data_${m}0; +//: wire [15:0] lutX_data_${m}1; +//: wire [15:0] lutX_info_${m}; +//: wire [31:0] lut_X_dat_${m}0; +//: wire [16:0] lut_X_dat_${m}0_fp17; +//: wire [31:0] lut_X_dat_${m}1; +//: ); +//: } +wire lut_wr_en; +wire raw_select; +//////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +assign lut_wr_en = (reg2dp_lut_access_type== 1'h1 ) && reg2dp_lut_data_trigger; +assign raw_select = (reg2dp_lut_table_id == 1'h0 ); +//========================================== +//LUT write +//------------------------------------------ +//need update foreach value if LUT depth update +//: foreach my $m (0..64) { +//: print qq( +//: always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: raw_reg${m} <= {16{1'b0}}; +//: end else if (lut_wr_en & raw_select) begin +//: if (reg2dp_lut_addr[9:0] == $m) +//: raw_reg$m <= reg2dp_lut_data[15:0]; +//: end +//: end +//: ); +//: } +//------------------------------------------ +//need update foreach value if LUT depth update +//: foreach my $m (0..256) { +//: print qq( +//: always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: density_reg$m <= {16{1'b0}}; +//: end else begin +//: if (lut_wr_en & (~raw_select)) begin +//: if (reg2dp_lut_addr[9:0] == $m) +//: density_reg$m <= reg2dp_lut_data[15:0]; +//: end +//: end +//: end +//: ); +//: } +//========================================== +//LUT read +//------------------------------------------ +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + raw_out <= {16{1'b0}}; + end else begin + case(reg2dp_lut_addr[9:0]) +//: foreach my $m (0..64) { +//: print qq( +//: $m: raw_out <= raw_reg$m; +//: ); +//: } + default: raw_out <= raw_reg0; + endcase + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + density_out <= {16{1'b0}}; + end else begin + case (reg2dp_lut_addr[9:0]) +//: foreach my $m (0..256) { +//: print qq( +//: $m: density_out <= density_reg$m; +//: ); +//: } + default: density_out <= density_reg0; + endcase + end +end +assign dp2reg_lut_data[15:0] = raw_select ? raw_out : density_out; +//========================================== +//data to DP +//------------------------------------------ +assign load_din = dp2lut_pvld & dp2lut_prdy_f; +assign dp2lut_prdy_f = ~lut2intp_pvld | lut2intp_prdy; +assign dp2lut_prdy = dp2lut_prdy_f; +///////////////////////////////// +//lut look up select control +///////////////////////////////// +assign both_hybrid_sel = (reg2dp_lut_hybrid_priority == 1'h1 ); +assign both_of_sel = (reg2dp_lut_oflow_priority == 1'h1 ); +assign both_uf_sel = (reg2dp_lut_uflow_priority == 1'h1 ); +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: case({dp2lut_Xinfo_${m}[17:16],dp2lut_Yinfo_${m}[17:16]}) +//: 4'b0000,4'b0110,4'b1001: lut_X_sel[$m] = ~both_hybrid_sel; //both hit, or one uflow and the other oflow +//: 4'b0001,4'b0010: lut_X_sel[$m] = 1'b1; //X hit, Y uflow/oflow +//: 4'b0100,4'b1000: lut_X_sel[$m] = 1'b0; //X uflow/oflow, Y hit +//: 4'b0101: lut_X_sel[$m] = ~both_uf_sel ; //both uflow +//: 4'b1010: lut_X_sel[$m] = ~both_of_sel ; //both oflow +//: default: lut_X_sel[$m] = 1'd0; +//: endcase +//: end +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(*) begin +//: case({dp2lut_Xinfo_${m}[17:16],dp2lut_Yinfo_${m}[17:16]}) +//: 4'b0000,4'b0110,4'b1001: lut_Y_sel[$m] = both_hybrid_sel; //both hit, or one uflow and the other oflow +//: 4'b0001,4'b0010: lut_Y_sel[$m] = 1'b0; //X hit, Y uflow/oflow +//: 4'b0100,4'b1000: lut_Y_sel[$m] = 1'b1; //X uflow/oflow, Y hit +//: 4'b0101: lut_Y_sel[$m] = both_uf_sel ; //both uflow +//: 4'b1010: lut_Y_sel[$m] = both_of_sel ; //both oflow +//: default: lut_Y_sel[$m] = 1'd0; +//: endcase +//: end +//: ); +//: } +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP LUT select: Lut X and Lut Y both select or both not selected") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, load_din & (~(&(lut_X_sel ^ lut_Y_sel)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +///////////////////////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_X_data_${m}0[15:0] <= {16{1'b0}}; +//: lut_X_data_${m}1[15:0] <= {16{1'b0}}; +//: end else begin +//: if(load_din & lut_X_sel[$m]) begin +//: if(dp2lut_Xinfo_${m}[16]) begin +//: lut_X_data_${m}0[15:0] <= raw_reg0; +//: lut_X_data_${m}1[15:0] <= raw_reg0; +//: end else if(dp2lut_Xinfo_${m}[17]) begin +//: lut_X_data_${m}0[15:0] <= raw_reg64; +//: lut_X_data_${m}1[15:0] <= raw_reg64; +//: end else begin +//: case(dp2lut_X_entry_${m}[9:0]) +//: ); +//: foreach my $i (0..64-1) { +//: my $j = $i + 1; +//: print qq( +//: $i: begin +//: lut_X_data_${m}0[15:0] <= raw_reg${i}; +//: lut_X_data_${m}1[15:0] <= raw_reg${j}; +//: end +//: ); +//: } +//: print qq( +//: 64: begin +//: lut_X_data_${m}0[15:0] <= raw_reg64; +//: lut_X_data_${m}1[15:0] <= raw_reg64; +//: end +//: default: begin +//: lut_X_data_${m}0[15:0] <= raw_reg0; +//: lut_X_data_${m}1[15:0] <= raw_reg0; +//: end +//: endcase +//: end +//: end +//: end +//: end +//: ); +//: } +///////////////// +///////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_Y_data_${m}0[15:0] <= {16{1'b0}}; +//: lut_Y_data_${m}1[15:0] <= {16{1'b0}}; +//: end else begin +//: if(load_din & lut_Y_sel[$m]) begin +//: if(dp2lut_Yinfo_${m}[16]) begin +//: lut_Y_data_${m}0[15:0] <= density_reg0; +//: lut_Y_data_${m}1[15:0] <= density_reg0; +//: end else if(dp2lut_Yinfo_${m}[17]) begin +//: lut_Y_data_${m}0[15:0] <= density_reg256; +//: lut_Y_data_${m}1[15:0] <= density_reg256; +//: end else begin +//: case(dp2lut_Y_entry_${m}[9:0]) +//: ); +//: foreach my $i (0..256-1) { +//: my $j = $i + 1; +//: print qq( +//: $i: begin +//: lut_Y_data_${m}0[15:0] <= density_reg${i}; +//: lut_Y_data_${m}1[15:0] <= density_reg${j}; +//: end +//: ); +//: } +//: print qq( +//: 256: begin +//: lut_Y_data_${m}0[15:0] <= density_reg256; +//: lut_Y_data_${m}1[15:0] <= density_reg256; +//: end +//: default: begin +//: lut_Y_data_${m}0[15:0] <= density_reg0; +//: lut_Y_data_${m}1[15:0] <= density_reg0; +//: end +//: endcase +//: end +//: end +//: end +//: end +//: ); +//: } +//////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_X_info_${m} <= {18{1'b0}}; +//: end else if (load_din) begin +//: lut_X_info_${m} <= dp2lut_Xinfo_${m}[17:0]; +//: end +//: end +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lutX_sel <= {1{1'b0}}; + end else if (load_din) begin + lutX_sel <= lut_X_sel[1 -1:0]; + end +end +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: lut_Y_info_${m} <= {18{1'b0}}; +//: end else if (load_din) begin +//: lut_Y_info_${m} <= dp2lut_Yinfo_${m}[17:0]; +//: end +//: end +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lutY_sel <= {1{1'b0}}; + end else if (load_din) begin + lutY_sel <= lut_Y_sel[1 -1:0]; + end +end +//////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign lutX_data_${m}0[15:0] = lutX_sel[$m] ? lut_X_data_${m}0[15:0] : (lutY_sel[$m] ? lut_Y_data_${m}0[15:0] : 16'd0); +//: assign lutX_data_${m}1[15:0] = lutX_sel[$m] ? lut_X_data_${m}1[15:0] : (lutY_sel[$m] ? lut_Y_data_${m}1[15:0] : 16'd0); +//: assign lutX_info_${m}[15:0] = lutX_sel[$m] ? lut_X_info_${m}[15:0] : (lutY_sel[$m] ? lut_Y_info_${m}[15:0] : 16'd0); +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut2intp_pvld <= 1'b0; + end else begin + if(dp2lut_pvld) + lut2intp_pvld <= 1'b1; + else if(lut2intp_prdy) + lut2intp_pvld <= 1'b0; + end +end +/////////////////////////////////////////////////////////////// +//output data +/////////////////////////////////////////////////////////////// +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign lut2intp_X_data_${m}0[31:0] = {{16{lutX_data_${m}0[15]}},lutX_data_${m}0[15:0]}; +//: assign lut2intp_X_data_${m}1[31:0] = {{16{lutX_data_${m}1[15]}},lutX_data_${m}1[15:0]}; +//: assign lut2intp_X_data_${m}0_17b[16:0] = {lutX_data_${m}0[15],lutX_data_${m}0[15:0]}; +//: assign lut2intp_X_info_${m}[19:0] = {lut_Y_info_${m}[17:16],lut_X_info_${m}[17:16],lutX_info_${m}[15:0]}; +//: assign lut2intp_X_sel[$m] = lutX_sel[$m]; +//: assign lut2intp_Y_sel[$m] = lutY_sel[$m]; +//: ); +//: } +///////////////////////// +endmodule // NV_NVDLA_CDP_DP_lut diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v new file mode 100644 index 0000000..97073bd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v @@ -0,0 +1,307 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_mul.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_mul ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,intp2mul_pd_$m +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,intp2mul_pd_0 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,intp2mul_pvld //|< i + ,mul2ocvt_prdy //|< i + ,reg2dp_mul_bypass //|< i + ,sync2mul_pd //|< i + ,sync2mul_pvld //|< i + ,intp2mul_prdy //|> o + ,mul2ocvt_pd //|> o + ,mul2ocvt_pvld //|> o + ,sync2mul_prdy //|> o + ); +////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k = 1; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: input [16:0] intp2mul_pd_$m; +//: ); +//: } +//: print qq( +//: input [${k}*${icvto}-1:0] sync2mul_pd; +//: output [${k}*(${icvto}+16)-1:0] mul2ocvt_pd; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [16:0] intp2mul_pd_0; + +input [1*9-1:0] sync2mul_pd; +output [1*(9+16)-1:0] mul2ocvt_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input intp2mul_pvld; +input mul2ocvt_prdy; +input reg2dp_mul_bypass; +input sync2mul_pvld; +output intp2mul_prdy; +output mul2ocvt_pvld; +output sync2mul_prdy; +////////////////////////////////////////////////////// +reg mul_bypass_en; +wire [1*((8 +1)+16)-1:0] intp_out_ext; +wire [1*((8 +1)+16)-1:0] mul2ocvt_pd_f; +wire mul2ocvt_pvld_f; +wire mul_in_rdy; +wire mul_in_vld; +//: my $k = 1; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [(${icvto}+16)-1:0] mul_unit_pd_$m; +//: wire [${icvto}-1:0] mul_ina_pd_$m; +//: wire [15:0] mul_inb_pd_$m; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [(9+16)-1:0] mul_unit_pd_0; +wire [9-1:0] mul_ina_pd_0; +wire [15:0] mul_inb_pd_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [1 -1:0] mul_unit_rdy; +wire [1 -1:0] mul_unit_vld; +wire [1 -1:0] mul_vld; +wire [1 -1:0] mul_rdy; +/////////////////////////////////////////// +//: my $k = 1*((8 +1)+16); +//: &eperl::pipe(" -wid $k -is -do mul2ocvt_pd -vo mul2ocvt_pvld -ri mul2ocvt_prdy -di mul2ocvt_pd_f -vi mul2ocvt_pvld_f -ro mul2ocvt_prdy_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg mul2ocvt_prdy_f; +reg skid_flop_mul2ocvt_prdy_f; +reg skid_flop_mul2ocvt_pvld_f; +reg [25-1:0] skid_flop_mul2ocvt_pd_f; +reg pipe_skid_mul2ocvt_pvld_f; +reg [25-1:0] pipe_skid_mul2ocvt_pd_f; +// Wire +wire skid_mul2ocvt_pvld_f; +wire [25-1:0] skid_mul2ocvt_pd_f; +wire skid_mul2ocvt_prdy_f; +wire pipe_skid_mul2ocvt_prdy_f; +wire mul2ocvt_pvld; +wire [25-1:0] mul2ocvt_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul2ocvt_prdy_f <= 1'b1; + skid_flop_mul2ocvt_prdy_f <= 1'b1; + end else begin + mul2ocvt_prdy_f <= skid_mul2ocvt_prdy_f; + skid_flop_mul2ocvt_prdy_f <= skid_mul2ocvt_prdy_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_mul2ocvt_pvld_f <= 1'b0; + end else begin + if (skid_flop_mul2ocvt_prdy_f) begin + skid_flop_mul2ocvt_pvld_f <= mul2ocvt_pvld_f; + end + end +end +assign skid_mul2ocvt_pvld_f = (skid_flop_mul2ocvt_prdy_f) ? mul2ocvt_pvld_f : skid_flop_mul2ocvt_pvld_f; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_mul2ocvt_prdy_f & mul2ocvt_pvld_f) begin + skid_flop_mul2ocvt_pd_f[25-1:0] <= mul2ocvt_pd_f[25-1:0]; + end +end +assign skid_mul2ocvt_pd_f[25-1:0] = (skid_flop_mul2ocvt_prdy_f) ? mul2ocvt_pd_f[25-1:0] : skid_flop_mul2ocvt_pd_f[25-1:0]; + + +// PIPE READY +assign skid_mul2ocvt_prdy_f = pipe_skid_mul2ocvt_prdy_f || !pipe_skid_mul2ocvt_pvld_f; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_mul2ocvt_pvld_f <= 1'b0; + end else begin + if (skid_mul2ocvt_prdy_f) begin + pipe_skid_mul2ocvt_pvld_f <= skid_mul2ocvt_pvld_f; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_mul2ocvt_prdy_f && skid_mul2ocvt_pvld_f) begin + pipe_skid_mul2ocvt_pd_f[25-1:0] <= skid_mul2ocvt_pd_f[25-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_mul2ocvt_prdy_f = mul2ocvt_prdy; +assign mul2ocvt_pvld = pipe_skid_mul2ocvt_pvld_f; +assign mul2ocvt_pd = pipe_skid_mul2ocvt_pd_f; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_bypass_en <= 1'b0; + end else begin + mul_bypass_en <= reg2dp_mul_bypass == 1'h1; + end +end +//interlock two path data +assign intp2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & sync2mul_pvld; +assign sync2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & intp2mul_pvld; +assign mul_in_vld = mul_bypass_en ? 1'b0 : (sync2mul_pvld & intp2mul_pvld); +assign mul_in_rdy = &mul_rdy; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_vld[$m] = mul_in_vld +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & mul_rdy[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_inb_pd_$m = intp2mul_pd_${m}[15:0]; +//: ); +//: } +//: my $k = 1; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_ina_pd_$m = sync2mul_pd[$m*${icvto}+${icvto}-1:$m*${icvto}]; +//: NV_NVDLA_CDP_DP_MUL_unit u_mul_unit$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.mul_vld (mul_vld[$m]) +//: ,.mul_rdy (mul_rdy[$m]) +//: ,.mul_ina_pd (mul_ina_pd_$m) +//: ,.mul_inb_pd (mul_inb_pd_$m) +//: ,.mul_unit_vld (mul_unit_vld[$m]) +//: ,.mul_unit_rdy (mul_unit_rdy[$m]) +//: ,.mul_unit_pd (mul_unit_pd_$m) +//: ); +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_unit_rdy[$m] = mul2ocvt_prdy_f +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & mul_unit_vld[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign mul_vld[0] = mul_in_vld + +& mul_rdy[0] + +; + +assign mul_inb_pd_0 = intp2mul_pd_0[15:0]; + +assign mul_ina_pd_0 = sync2mul_pd[0*9+9-1:0*9]; +NV_NVDLA_CDP_DP_MUL_unit u_mul_unit0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.mul_vld (mul_vld[0]) +,.mul_rdy (mul_rdy[0]) +,.mul_ina_pd (mul_ina_pd_0) +,.mul_inb_pd (mul_inb_pd_0) +,.mul_unit_vld (mul_unit_vld[0]) +,.mul_unit_rdy (mul_unit_rdy[0]) +,.mul_unit_pd (mul_unit_pd_0) +); + +assign mul_unit_rdy[0] = mul2ocvt_prdy_f + +& mul_unit_vld[0] + +; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////// +//NaN propagation for mul_bypass condition +/////////////////// +assign intp_out_ext = { +//: my $icvto=(8 +1); +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print "{{(${icvto}+16-17){intp2mul_pd_${i}[16]}}, intp2mul_pd_${i}[16:0]},"; +//: } +//: } +//: print "{{(${icvto}+16-17){intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}}; \n"; +//: +//: print "assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : { "; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print "mul_unit_pd_$i,"; +//: } +//: } +//: print " mul_unit_pd_0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +{{(9+16-17){intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}}; +assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : { mul_unit_pd_0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//output select +assign mul2ocvt_pvld_f = mul_bypass_en ? (sync2mul_pvld & intp2mul_pvld) : (&mul_unit_vld); +// /////////////////////////////////////////// +// +// //: my $k = NVDLA_CDP_THROUGHPUT*(NVDLA_CDP_ICVTO_BWPE+16); +// //: &eperl::pipe(" -wid $k -is -do mul2ocvt_pd -vo mul2ocvt_pvld -ri mul2ocvt_prdy -di mul2ocvt_pd_f -vi mul2ocvt_pvld_f -ro mul2ocvt_prdy_f "); +// +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_mul diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v.vcp new file mode 100644 index 0000000..c1596c8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v.vcp @@ -0,0 +1,176 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_mul.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_mul ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,intp2mul_pd_$m +//: ); +//: } + ,intp2mul_pvld //|< i + ,mul2ocvt_prdy //|< i + ,reg2dp_mul_bypass //|< i + ,sync2mul_pd //|< i + ,sync2mul_pvld //|< i + ,intp2mul_prdy //|> o + ,mul2ocvt_pd //|> o + ,mul2ocvt_pvld //|> o + ,sync2mul_prdy //|> o + ); +////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k = 1; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: input [16:0] intp2mul_pd_$m; +//: ); +//: } +//: print qq( +//: input [${k}*${icvto}-1:0] sync2mul_pd; +//: output [${k}*(${icvto}+16)-1:0] mul2ocvt_pd; +//: ); +input intp2mul_pvld; +input mul2ocvt_prdy; +input reg2dp_mul_bypass; +input sync2mul_pvld; +output intp2mul_prdy; +output mul2ocvt_pvld; +output sync2mul_prdy; +////////////////////////////////////////////////////// +reg mul_bypass_en; +wire [1*((8 +1)+16)-1:0] intp_out_ext; +wire [1*((8 +1)+16)-1:0] mul2ocvt_pd_f; +wire mul2ocvt_pvld_f; +wire mul_in_rdy; +wire mul_in_vld; +//: my $k = 1; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [(${icvto}+16)-1:0] mul_unit_pd_$m; +//: wire [${icvto}-1:0] mul_ina_pd_$m; +//: wire [15:0] mul_inb_pd_$m; +//: ); +//: } +wire [1 -1:0] mul_unit_rdy; +wire [1 -1:0] mul_unit_vld; +wire [1 -1:0] mul_vld; +wire [1 -1:0] mul_rdy; +/////////////////////////////////////////// +//: my $k = 1*((8 +1)+16); +//: &eperl::pipe(" -wid $k -is -do mul2ocvt_pd -vo mul2ocvt_pvld -ri mul2ocvt_prdy -di mul2ocvt_pd_f -vi mul2ocvt_pvld_f -ro mul2ocvt_prdy_f "); +/////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_bypass_en <= 1'b0; + end else begin + mul_bypass_en <= reg2dp_mul_bypass == 1'h1; + end +end +//interlock two path data +assign intp2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & sync2mul_pvld; +assign sync2mul_prdy = (mul_bypass_en ? mul2ocvt_prdy_f : mul_in_rdy) & intp2mul_pvld; +assign mul_in_vld = mul_bypass_en ? 1'b0 : (sync2mul_pvld & intp2mul_pvld); +assign mul_in_rdy = &mul_rdy; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_vld[$m] = mul_in_vld +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & mul_rdy[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_inb_pd_$m = intp2mul_pd_${m}[15:0]; +//: ); +//: } +//: my $k = 1; +//: my $icvto=(8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_ina_pd_$m = sync2mul_pd[$m*${icvto}+${icvto}-1:$m*${icvto}]; +//: NV_NVDLA_CDP_DP_MUL_unit u_mul_unit$m ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.mul_vld (mul_vld[$m]) +//: ,.mul_rdy (mul_rdy[$m]) +//: ,.mul_ina_pd (mul_ina_pd_$m) +//: ,.mul_inb_pd (mul_inb_pd_$m) +//: ,.mul_unit_vld (mul_unit_vld[$m]) +//: ,.mul_unit_rdy (mul_unit_rdy[$m]) +//: ,.mul_unit_pd (mul_unit_pd_$m) +//: ); +//: ); +//: } +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign mul_unit_rdy[$m] = mul2ocvt_prdy_f +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: & mul_unit_vld[$i] +//: ); +//: } +//: print qq( +//: ; +//: ); +//: } +/////////////////// +//NaN propagation for mul_bypass condition +/////////////////// +assign intp_out_ext = { +//: my $icvto=(8 +1); +//: my $k = 1; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print "{{(${icvto}+16-17){intp2mul_pd_${i}[16]}}, intp2mul_pd_${i}[16:0]},"; +//: } +//: } +//: print "{{(${icvto}+16-17){intp2mul_pd_0[16]}}, intp2mul_pd_0[16:0]}}; \n"; +//: +//: print "assign mul2ocvt_pd_f = mul_bypass_en ? intp_out_ext : { "; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k -$m -1; +//: print "mul_unit_pd_$i,"; +//: } +//: } +//: print " mul_unit_pd_0}; \n"; +//output select +assign mul2ocvt_pvld_f = mul_bypass_en ? (sync2mul_pvld & intp2mul_pvld) : (&mul_unit_vld); +// /////////////////////////////////////////// +// +// //: my $k = NVDLA_CDP_THROUGHPUT*(NVDLA_CDP_ICVTO_BWPE+16); +// //: &eperl::pipe(" -wid $k -is -do mul2ocvt_pd -vo mul2ocvt_pvld -ri mul2ocvt_prdy -di mul2ocvt_pd_f -vi mul2ocvt_pvld_f -ro mul2ocvt_prdy_f "); +// +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_mul diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v new file mode 100644 index 0000000..3baea59 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v @@ -0,0 +1,329 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_nan.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_nan ( + nvdla_core_clk + ,nvdla_core_rstn + ,cdp_rdma2dp_pd + ,cdp_rdma2dp_valid + ,dp2reg_done + ,nan_preproc_prdy +//,reg2dp_input_data_type + ,reg2dp_nan_to_zero + ,reg2dp_op_en + ,cdp_rdma2dp_ready + ,dp2reg_inf_input_num + ,dp2reg_nan_input_num + ,nan_preproc_pd + ,nan_preproc_pvld + ); +////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*8 +22:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +input dp2reg_done; +input nan_preproc_prdy; +//input [1:0] reg2dp_input_data_type; +input reg2dp_nan_to_zero; +input reg2dp_op_en; +output cdp_rdma2dp_ready; +output [31:0] dp2reg_inf_input_num; +output [31:0] dp2reg_nan_input_num; +output [1*8 +22:0] nan_preproc_pd; +output nan_preproc_pvld; +////////////////////////////////////////////////////// +reg [1*8 +22:0] datin_d; +reg din_pvld_d1; +wire [31:0] dp2reg_inf_input_num=0; +wire [31:0] dp2reg_nan_input_num=0; +//reg fp16_en; +//reg [31:0] inf_in_count; +//reg [31:0] inf_in_num0; +//reg [31:0] inf_in_num1; +reg layer_flag; +//reg mon_inf_in_count; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +//reg [31:0] nan_in_num0; +//reg [31:0] nan_in_num1; +//reg [15:0] nan_preproc_pd0; +//reg [15:0] nan_preproc_pd1; +//reg [15:0] nan_preproc_pd2; +//reg [15:0] nan_preproc_pd3; +reg op_en_d1; +//reg tozero_en; +reg waiting_for_op_en; +reg wdma_layer_flag; +wire cdp_rdma2dp_ready_f; +//wire cube_end; +//wire [3:0] dat_is_inf; +//wire [3:0] dat_is_nan; +wire din_prdy_d1; +//wire [15:0] fp16_in_pd_0; +//wire [15:0] fp16_in_pd_1; +//wire [15:0] fp16_in_pd_2; +//wire [15:0] fp16_in_pd_3; +//wire [2:0] inf_num_in_8byte; +//wire last_c; +//wire last_h; +//wire last_w; +wire layer_end; +wire load_din; +//wire [2:0] nan_num_in_8byte; +wire op_en_load; +wire wdma_done; +////////////////////////////////////////////////////// +//========================================== +//---------------------------------------- +assign cdp_rdma2dp_ready = cdp_rdma2dp_ready_f; +assign cdp_rdma2dp_ready_f = (~din_pvld_d1 | din_prdy_d1) & (~waiting_for_op_en); +assign load_din = cdp_rdma2dp_valid & cdp_rdma2dp_ready_f; +// //---------------------------------------- +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// tozero_en <= 1'b0; +// end else begin +// tozero_en <= reg2dp_nan_to_zero == 1'h1; +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// fp16_en <= 1'b0; +// end else begin +// fp16_en <= reg2dp_input_data_type[1:0]== 2; +// end +// end +// //---------------------------------------- +// assign fp16_in_pd_0 = cdp_rdma2dp_pd[15:0]; +// assign fp16_in_pd_1 = cdp_rdma2dp_pd[31:16]; +// assign fp16_in_pd_2 = cdp_rdma2dp_pd[47:32]; +// assign fp16_in_pd_3 = cdp_rdma2dp_pd[63:48]; +// +// assign dat_is_nan[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (|fp16_in_pd_0[9:0]); +// assign dat_is_nan[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (|fp16_in_pd_1[9:0]); +// assign dat_is_nan[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (|fp16_in_pd_2[9:0]); +// assign dat_is_nan[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (|fp16_in_pd_3[9:0]); +// +// assign dat_is_inf[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (~(|fp16_in_pd_0[9:0])); +// assign dat_is_inf[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (~(|fp16_in_pd_1[9:0])); +// assign dat_is_inf[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (~(|fp16_in_pd_2[9:0])); +// assign dat_is_inf[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (~(|fp16_in_pd_3[9:0])); +////////////////////////////////////////////////////////////////////// +//waiting for op_en +////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 1'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +assign op_en_load = reg2dp_op_en & (~op_en_d1); +assign layer_end = &{cdp_rdma2dp_pd[1*8 +14:1*8 +11],cdp_rdma2dp_pd[1*8 +10:1*8 +8]} & load_din; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_for_op_en <= 1'b1; + end else begin + if(layer_end) + waiting_for_op_en <= 1'b1; + else if(op_en_load) + waiting_for_op_en <= 1'b0; + end +end +// ////////////////////////////////////////////////////////////////////// +// //NaN process mode control +// ////////////////////////////////////////////////////////////////////// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_preproc_pd0 <= {16{1'b0}}; +// nan_preproc_pd1 <= {16{1'b0}}; +// nan_preproc_pd2 <= {16{1'b0}}; +// nan_preproc_pd3 <= {16{1'b0}}; +// datin_info_d <= {23{1'b0}}; +// end else begin +// if(load_din) begin +// nan_preproc_pd0 <= (dat_is_nan[0] & tozero_en) ? 16'd0 : fp16_in_pd_0; +// nan_preproc_pd1 <= (dat_is_nan[1] & tozero_en) ? 16'd0 : fp16_in_pd_1; +// nan_preproc_pd2 <= (dat_is_nan[2] & tozero_en) ? 16'd0 : fp16_in_pd_2; +// nan_preproc_pd3 <= (dat_is_nan[3] & tozero_en) ? 16'd0 : fp16_in_pd_3; +// datin_info_d <= cdp_rdma2dp_pd[86:64]; +// end +// end +// end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_d <= 0; + end else if(load_din) begin + datin_d <= cdp_rdma2dp_pd; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + din_pvld_d1 <= 1'b0; + end else begin + if(cdp_rdma2dp_valid & (~waiting_for_op_en)) + din_pvld_d1 <= 1'b1; + else if(din_prdy_d1) + din_pvld_d1 <= 1'b0; + end +end +assign din_prdy_d1 = nan_preproc_prdy; +//------------------------------------------- +assign nan_preproc_pd = datin_d; +assign nan_preproc_pvld = din_pvld_d1; +// ////////////////////////////////////////////////////////////////////// +// //input NaN element count +// ////////////////////////////////////////////////////////////////////// +// assign last_w = cdp_rdma2dp_pd[1*8 +12]; +// assign last_h = cdp_rdma2dp_pd[1*8 +13]; +// assign last_c = cdp_rdma2dp_pd[1*8 +14]; +// assign cube_end = last_w & last_h & last_c; +// +// function [2:0] fun_bit_sum_4; +// input [3:0] idata; +// reg [2:0] ocnt; +// begin +// ocnt = +// ( idata[0] +// + idata[1] +// + idata[2] ) +// + idata[3] ; +// fun_bit_sum_4 = ocnt; +// end +// endfunction +// +// assign nan_num_in_8byte = fun_bit_sum_4(dat_is_nan); +// assign inf_num_in_8byte = fun_bit_sum_4(dat_is_inf); +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din) begin +// if(cube_end) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte; +// end +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_inf_in_count,inf_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din) begin +// if(cube_end) +// {mon_inf_in_count,inf_in_count[31:0]} <= 32'd0; +// else +// {mon_inf_in_count,inf_in_count[31:0]} <= inf_in_count + inf_num_in_8byte; +// end +// end +// end +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// layer_flag <= 1'b0; +// nan_in_num1 <= {32{1'b0}}; +// inf_in_num1 <= {32{1'b0}}; +// nan_in_num0 <= {32{1'b0}}; +// inf_in_num0 <= {32{1'b0}}; +// end else begin +// if(load_din & cube_end) begin +// layer_flag <= ~layer_flag; +// if(layer_flag) begin +// nan_in_num1 <= nan_in_count; +// inf_in_num1 <= inf_in_count; +// end else begin +// nan_in_num0 <= nan_in_count; +// inf_in_num0 <= inf_in_count; +// end +// end +// end +// end +// //adding dp2reg_done to latch the num and output a sigle one for each +// assign wdma_done = dp2reg_done; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// wdma_layer_flag <= 1'b0; +// dp2reg_nan_input_num <= {32{1'b0}}; +// dp2reg_inf_input_num <= {32{1'b0}}; +// end else begin +// if(wdma_done) begin +// wdma_layer_flag <= ~wdma_layer_flag; +// if(wdma_layer_flag) begin +// dp2reg_nan_input_num <= nan_in_num1; +// dp2reg_inf_input_num <= inf_in_num1; +// end else begin +// dp2reg_nan_input_num <= nan_in_num0; +// dp2reg_inf_input_num <= inf_in_num0; +// end +// end +// end +// end +////////////////////////////////////////////////////////////////////// +//function point +////////////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_NAN_IN__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + |dat_is_nan & fp16_en; + endproperty +// Cover 0 : "|dat_is_nan & fp16_en" + FUNCPOINT_CDP_NAN_IN__0_COV : cover property (CDP_NAN_IN__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_INF_IN__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + |dat_is_inf & fp16_en; + endproperty +// Cover 1 : "|dat_is_inf & fp16_en" + FUNCPOINT_CDP_INF_IN__1_COV : cover property (CDP_INF_IN__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & (~cdp_rdma2dp_ready_f) & cdp_rdma2dp_valid; + endproperty +// Cover 2 : "waiting_for_op_en & (~cdp_rdma2dp_ready_f) & cdp_rdma2dp_valid" + FUNCPOINT_CDP_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__2_COV : cover property (CDP_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__2_cov); + `endif +`endif +//VCS coverage on +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_nan diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v.vcp new file mode 100644 index 0000000..3baea59 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v.vcp @@ -0,0 +1,329 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_nan.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_nan ( + nvdla_core_clk + ,nvdla_core_rstn + ,cdp_rdma2dp_pd + ,cdp_rdma2dp_valid + ,dp2reg_done + ,nan_preproc_prdy +//,reg2dp_input_data_type + ,reg2dp_nan_to_zero + ,reg2dp_op_en + ,cdp_rdma2dp_ready + ,dp2reg_inf_input_num + ,dp2reg_nan_input_num + ,nan_preproc_pd + ,nan_preproc_pvld + ); +////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*8 +22:0] cdp_rdma2dp_pd; +input cdp_rdma2dp_valid; +input dp2reg_done; +input nan_preproc_prdy; +//input [1:0] reg2dp_input_data_type; +input reg2dp_nan_to_zero; +input reg2dp_op_en; +output cdp_rdma2dp_ready; +output [31:0] dp2reg_inf_input_num; +output [31:0] dp2reg_nan_input_num; +output [1*8 +22:0] nan_preproc_pd; +output nan_preproc_pvld; +////////////////////////////////////////////////////// +reg [1*8 +22:0] datin_d; +reg din_pvld_d1; +wire [31:0] dp2reg_inf_input_num=0; +wire [31:0] dp2reg_nan_input_num=0; +//reg fp16_en; +//reg [31:0] inf_in_count; +//reg [31:0] inf_in_num0; +//reg [31:0] inf_in_num1; +reg layer_flag; +//reg mon_inf_in_count; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +//reg [31:0] nan_in_num0; +//reg [31:0] nan_in_num1; +//reg [15:0] nan_preproc_pd0; +//reg [15:0] nan_preproc_pd1; +//reg [15:0] nan_preproc_pd2; +//reg [15:0] nan_preproc_pd3; +reg op_en_d1; +//reg tozero_en; +reg waiting_for_op_en; +reg wdma_layer_flag; +wire cdp_rdma2dp_ready_f; +//wire cube_end; +//wire [3:0] dat_is_inf; +//wire [3:0] dat_is_nan; +wire din_prdy_d1; +//wire [15:0] fp16_in_pd_0; +//wire [15:0] fp16_in_pd_1; +//wire [15:0] fp16_in_pd_2; +//wire [15:0] fp16_in_pd_3; +//wire [2:0] inf_num_in_8byte; +//wire last_c; +//wire last_h; +//wire last_w; +wire layer_end; +wire load_din; +//wire [2:0] nan_num_in_8byte; +wire op_en_load; +wire wdma_done; +////////////////////////////////////////////////////// +//========================================== +//---------------------------------------- +assign cdp_rdma2dp_ready = cdp_rdma2dp_ready_f; +assign cdp_rdma2dp_ready_f = (~din_pvld_d1 | din_prdy_d1) & (~waiting_for_op_en); +assign load_din = cdp_rdma2dp_valid & cdp_rdma2dp_ready_f; +// //---------------------------------------- +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// tozero_en <= 1'b0; +// end else begin +// tozero_en <= reg2dp_nan_to_zero == 1'h1; +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// fp16_en <= 1'b0; +// end else begin +// fp16_en <= reg2dp_input_data_type[1:0]== 2; +// end +// end +// //---------------------------------------- +// assign fp16_in_pd_0 = cdp_rdma2dp_pd[15:0]; +// assign fp16_in_pd_1 = cdp_rdma2dp_pd[31:16]; +// assign fp16_in_pd_2 = cdp_rdma2dp_pd[47:32]; +// assign fp16_in_pd_3 = cdp_rdma2dp_pd[63:48]; +// +// assign dat_is_nan[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (|fp16_in_pd_0[9:0]); +// assign dat_is_nan[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (|fp16_in_pd_1[9:0]); +// assign dat_is_nan[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (|fp16_in_pd_2[9:0]); +// assign dat_is_nan[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (|fp16_in_pd_3[9:0]); +// +// assign dat_is_inf[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (~(|fp16_in_pd_0[9:0])); +// assign dat_is_inf[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (~(|fp16_in_pd_1[9:0])); +// assign dat_is_inf[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (~(|fp16_in_pd_2[9:0])); +// assign dat_is_inf[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (~(|fp16_in_pd_3[9:0])); +////////////////////////////////////////////////////////////////////// +//waiting for op_en +////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 1'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +assign op_en_load = reg2dp_op_en & (~op_en_d1); +assign layer_end = &{cdp_rdma2dp_pd[1*8 +14:1*8 +11],cdp_rdma2dp_pd[1*8 +10:1*8 +8]} & load_din; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_for_op_en <= 1'b1; + end else begin + if(layer_end) + waiting_for_op_en <= 1'b1; + else if(op_en_load) + waiting_for_op_en <= 1'b0; + end +end +// ////////////////////////////////////////////////////////////////////// +// //NaN process mode control +// ////////////////////////////////////////////////////////////////////// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_preproc_pd0 <= {16{1'b0}}; +// nan_preproc_pd1 <= {16{1'b0}}; +// nan_preproc_pd2 <= {16{1'b0}}; +// nan_preproc_pd3 <= {16{1'b0}}; +// datin_info_d <= {23{1'b0}}; +// end else begin +// if(load_din) begin +// nan_preproc_pd0 <= (dat_is_nan[0] & tozero_en) ? 16'd0 : fp16_in_pd_0; +// nan_preproc_pd1 <= (dat_is_nan[1] & tozero_en) ? 16'd0 : fp16_in_pd_1; +// nan_preproc_pd2 <= (dat_is_nan[2] & tozero_en) ? 16'd0 : fp16_in_pd_2; +// nan_preproc_pd3 <= (dat_is_nan[3] & tozero_en) ? 16'd0 : fp16_in_pd_3; +// datin_info_d <= cdp_rdma2dp_pd[86:64]; +// end +// end +// end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_d <= 0; + end else if(load_din) begin + datin_d <= cdp_rdma2dp_pd; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + din_pvld_d1 <= 1'b0; + end else begin + if(cdp_rdma2dp_valid & (~waiting_for_op_en)) + din_pvld_d1 <= 1'b1; + else if(din_prdy_d1) + din_pvld_d1 <= 1'b0; + end +end +assign din_prdy_d1 = nan_preproc_prdy; +//------------------------------------------- +assign nan_preproc_pd = datin_d; +assign nan_preproc_pvld = din_pvld_d1; +// ////////////////////////////////////////////////////////////////////// +// //input NaN element count +// ////////////////////////////////////////////////////////////////////// +// assign last_w = cdp_rdma2dp_pd[1*8 +12]; +// assign last_h = cdp_rdma2dp_pd[1*8 +13]; +// assign last_c = cdp_rdma2dp_pd[1*8 +14]; +// assign cube_end = last_w & last_h & last_c; +// +// function [2:0] fun_bit_sum_4; +// input [3:0] idata; +// reg [2:0] ocnt; +// begin +// ocnt = +// ( idata[0] +// + idata[1] +// + idata[2] ) +// + idata[3] ; +// fun_bit_sum_4 = ocnt; +// end +// endfunction +// +// assign nan_num_in_8byte = fun_bit_sum_4(dat_is_nan); +// assign inf_num_in_8byte = fun_bit_sum_4(dat_is_inf); +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din) begin +// if(cube_end) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte; +// end +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_inf_in_count,inf_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din) begin +// if(cube_end) +// {mon_inf_in_count,inf_in_count[31:0]} <= 32'd0; +// else +// {mon_inf_in_count,inf_in_count[31:0]} <= inf_in_count + inf_num_in_8byte; +// end +// end +// end +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// layer_flag <= 1'b0; +// nan_in_num1 <= {32{1'b0}}; +// inf_in_num1 <= {32{1'b0}}; +// nan_in_num0 <= {32{1'b0}}; +// inf_in_num0 <= {32{1'b0}}; +// end else begin +// if(load_din & cube_end) begin +// layer_flag <= ~layer_flag; +// if(layer_flag) begin +// nan_in_num1 <= nan_in_count; +// inf_in_num1 <= inf_in_count; +// end else begin +// nan_in_num0 <= nan_in_count; +// inf_in_num0 <= inf_in_count; +// end +// end +// end +// end +// //adding dp2reg_done to latch the num and output a sigle one for each +// assign wdma_done = dp2reg_done; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// wdma_layer_flag <= 1'b0; +// dp2reg_nan_input_num <= {32{1'b0}}; +// dp2reg_inf_input_num <= {32{1'b0}}; +// end else begin +// if(wdma_done) begin +// wdma_layer_flag <= ~wdma_layer_flag; +// if(wdma_layer_flag) begin +// dp2reg_nan_input_num <= nan_in_num1; +// dp2reg_inf_input_num <= inf_in_num1; +// end else begin +// dp2reg_nan_input_num <= nan_in_num0; +// dp2reg_inf_input_num <= inf_in_num0; +// end +// end +// end +// end +////////////////////////////////////////////////////////////////////// +//function point +////////////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_NAN_IN__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + |dat_is_nan & fp16_en; + endproperty +// Cover 0 : "|dat_is_nan & fp16_en" + FUNCPOINT_CDP_NAN_IN__0_COV : cover property (CDP_NAN_IN__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_INF_IN__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + |dat_is_inf & fp16_en; + endproperty +// Cover 1 : "|dat_is_inf & fp16_en" + FUNCPOINT_CDP_INF_IN__1_COV : cover property (CDP_INF_IN__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & (~cdp_rdma2dp_ready_f) & cdp_rdma2dp_valid; + endproperty +// Cover 2 : "waiting_for_op_en & (~cdp_rdma2dp_ready_f) & cdp_rdma2dp_valid" + FUNCPOINT_CDP_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__2_COV : cover property (CDP_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__2_cov); + `endif +`endif +//VCS coverage on +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_nan diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v new file mode 100644 index 0000000..57838ef --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v @@ -0,0 +1,579 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_sum.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_sum ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,normalz_buf_data //|< i + ,normalz_buf_data_pvld //|< i + ,reg2dp_normalz_len //|< i + ,sum2itp_prdy //|< i + ,normalz_buf_data_prdy //|> o + ,sum2itp_pd //|> o + ,sum2itp_pvld //|> o + ); +///////////////////////////////////////////////////// +// parameter pINT8_BW = 9; +///////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $k = ${icvto}*(${tp}+8)+15; +//: print qq( +//: input [${k}-1:0] normalz_buf_data; +//: output [${tp}*(${icvto}*2+3)-1:0] sum2itp_pd; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [96-1:0] normalz_buf_data; +output [1*(9*2+3)-1:0] sum2itp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input normalz_buf_data_pvld; +input [1:0] reg2dp_normalz_len; +input sum2itp_prdy; +output normalz_buf_data_prdy; +output sum2itp_pvld; +///////////////////////////////////////////////////// +reg buf2sum_2d_vld; +reg buf2sum_3d_vld; +reg buf2sum_d_vld; +wire buf2sum_2d_rdy; +wire buf2sum_3d_rdy; +wire buf2sum_d_rdy; +wire buf2sum_din_prdy; +wire buf2sum_rdy_f; +wire cdp_buf2sum_ready; +//: my $icvto=(8 +1); +//: my $tp=1 +8; +//: foreach my $i (0..${tp}-1) { +//: print qq( +//: wire [${icvto}-1:0] buf2sum_int8_$i; +//: wire [${icvto}-1:0] inv_${i}; +//: wire [${icvto}-1:0] int8_abs_${i}; +//: reg [${icvto}*2-2:0] int8_sq_${i}; +//: reg mon_int8_sq_${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [9-1:0] buf2sum_int8_0; +wire [9-1:0] inv_0; +wire [9-1:0] int8_abs_0; +reg [9*2-2:0] int8_sq_0; +reg mon_int8_sq_0; + +wire [9-1:0] buf2sum_int8_1; +wire [9-1:0] inv_1; +wire [9-1:0] int8_abs_1; +reg [9*2-2:0] int8_sq_1; +reg mon_int8_sq_1; + +wire [9-1:0] buf2sum_int8_2; +wire [9-1:0] inv_2; +wire [9-1:0] int8_abs_2; +reg [9*2-2:0] int8_sq_2; +reg mon_int8_sq_2; + +wire [9-1:0] buf2sum_int8_3; +wire [9-1:0] inv_3; +wire [9-1:0] int8_abs_3; +reg [9*2-2:0] int8_sq_3; +reg mon_int8_sq_3; + +wire [9-1:0] buf2sum_int8_4; +wire [9-1:0] inv_4; +wire [9-1:0] int8_abs_4; +reg [9*2-2:0] int8_sq_4; +reg mon_int8_sq_4; + +wire [9-1:0] buf2sum_int8_5; +wire [9-1:0] inv_5; +wire [9-1:0] int8_abs_5; +reg [9*2-2:0] int8_sq_5; +reg mon_int8_sq_5; + +wire [9-1:0] buf2sum_int8_6; +wire [9-1:0] inv_6; +wire [9-1:0] int8_abs_6; +reg [9*2-2:0] int8_sq_6; +reg mon_int8_sq_6; + +wire [9-1:0] buf2sum_int8_7; +wire [9-1:0] inv_7; +wire [9-1:0] int8_abs_7; +reg [9*2-2:0] int8_sq_7; +reg mon_int8_sq_7; + +wire [9-1:0] buf2sum_int8_8; +wire [9-1:0] inv_8; +wire [9-1:0] int8_abs_8; +reg [9*2-2:0] int8_sq_8; +reg mon_int8_sq_8; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [7:0] int8_inv_2; +wire [7:0] int8_inv_3; +wire [7:0] int8_inv_4; +wire [7:0] int8_inv_5; +wire [7:0] int8_inv_6; +wire [7:0] int8_inv_7; +wire [7:0] int8_inv_8; +wire [7:0] int8_inv_9; +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $k = ${tp}*(${icvto}*2+3); +//: print qq( +//: wire [${k}-1:0] sum_out_pd; +//: wire [${k}-1:0] sum2itp_data; +//: ); +//: foreach my $i (0..$tp-1){ +//: print qq( +//: wire [${icvto}*2-1+4-1:0] int8_sum_$i; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [21-1:0] sum_out_pd; +wire [21-1:0] sum2itp_data; + +wire [9*2-1+4-1:0] int8_sum_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [41:0] int8_sum_1st; +wire [41:0] int8_sum_2nd; +wire [41:0] int8_sum_3rd; +wire [41:0] int8_sum_4th; +wire [15:0] int_ivt_2; +wire [15:0] int_ivt_3; +wire [15:0] int_ivt_4; +wire [15:0] int_ivt_5; +wire [15:0] int_ivt_6; +wire [15:0] int_ivt_7; +wire [15:0] int_ivt_8; +wire [15:0] int_ivt_9; +wire [16:0] int_sq_datin_2; +wire [16:0] int_sq_datin_3; +wire [16:0] int_sq_datin_4; +wire [16:0] int_sq_datin_5; +wire [16:0] int_sq_datin_6; +wire [16:0] int_sq_datin_7; +wire [16:0] int_sq_datin_8; +wire [16:0] int_sq_datin_9; +wire [16:0] int_sq_datin_abs_2; +wire [16:0] int_sq_datin_abs_3; +wire [16:0] int_sq_datin_abs_4; +wire [16:0] int_sq_datin_abs_5; +wire [16:0] int_sq_datin_abs_6; +wire [16:0] int_sq_datin_abs_7; +wire [16:0] int_sq_datin_abs_8; +wire [16:0] int_sq_datin_abs_9; +wire len3; +wire len5; +wire len7; +wire len9; +wire load_din; +wire load_din_2d; +wire load_din_d; +wire sum2itp_valid; +wire sum_out_prdy; +wire sum_out_pvld; +/////////////////////////////////////////// +//========================================== +//---------------------------------------- +////////::pipe -bc cdp_buf2sum_pd (cdp_buf2sum_valid,cdp_buf2sum_ready) <= normalz_buf_data[230:0] (normalz_buf_data_pvld,normalz_buf_data_prdy); +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $k = ${icvto}*(${tp}+8)+15; +//: &eperl::pipe(" -wid $k -do cdp_buf2sum_pd -vo cdp_buf2sum_valid -ri cdp_buf2sum_ready -di normalz_buf_data -vi normalz_buf_data_pvld -ro normalz_buf_data_prdy "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg pipe_normalz_buf_data_pvld; +reg [96-1:0] pipe_normalz_buf_data; +// Wire +wire normalz_buf_data_prdy; +wire pipe_normalz_buf_data_prdy; +wire cdp_buf2sum_valid; +wire [96-1:0] cdp_buf2sum_pd; +// Code +// PIPE READY +assign normalz_buf_data_prdy = pipe_normalz_buf_data_prdy || !pipe_normalz_buf_data_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_normalz_buf_data_pvld <= 1'b0; + end else begin + if (normalz_buf_data_prdy) begin + pipe_normalz_buf_data_pvld <= normalz_buf_data_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (normalz_buf_data_prdy && normalz_buf_data_pvld) begin + pipe_normalz_buf_data[96-1:0] <= normalz_buf_data[96-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_normalz_buf_data_prdy = cdp_buf2sum_ready; +assign cdp_buf2sum_valid = pipe_normalz_buf_data_pvld; +assign cdp_buf2sum_pd = pipe_normalz_buf_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////////////////////////// +assign load_din = (cdp_buf2sum_valid & buf2sum_rdy_f); +assign cdp_buf2sum_ready = buf2sum_rdy_f; +assign buf2sum_rdy_f = buf2sum_din_prdy; +//========================================== +//: my $icvto=(8 +1); +//: my $tp=1 +8; +//: foreach my $i (0..${tp}-1) { +//: print qq( +//: assign buf2sum_int8_$i = cdp_buf2sum_pd[${icvto}*${i}+${icvto}-1:${icvto}*${i}]; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign buf2sum_int8_0 = cdp_buf2sum_pd[9*0+9-1:9*0]; + +assign buf2sum_int8_1 = cdp_buf2sum_pd[9*1+9-1:9*1]; + +assign buf2sum_int8_2 = cdp_buf2sum_pd[9*2+9-1:9*2]; + +assign buf2sum_int8_3 = cdp_buf2sum_pd[9*3+9-1:9*3]; + +assign buf2sum_int8_4 = cdp_buf2sum_pd[9*4+9-1:9*4]; + +assign buf2sum_int8_5 = cdp_buf2sum_pd[9*5+9-1:9*5]; + +assign buf2sum_int8_6 = cdp_buf2sum_pd[9*6+9-1:9*6]; + +assign buf2sum_int8_7 = cdp_buf2sum_pd[9*7+9-1:9*7]; + +assign buf2sum_int8_8 = cdp_buf2sum_pd[9*8+9-1:9*8]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//======================================================== +//int mode +//-------------------------------------------------------- +//: my $tp=1; +//: my $icvto=(8 +1); +//: foreach my $i (0..${tp}+8-1) { +//: print qq( +//: assign inv_${i} = buf2sum_int8_${i}[${icvto}-1] ? (~buf2sum_int8_${i}[${icvto}-2:0]) : {(${icvto}-1){1'b0}}; +//: assign int8_abs_${i} = buf2sum_int8_${i}[${icvto}-1] ? (inv_${i}[${icvto}-2:0] + {{(${icvto}-2){1'b0}},1'b1}) : buf2sum_int8_${i}; +//: ); +//: } +//: +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: ); +//: foreach my $i (0..${tp}+8-1) { +//: print qq( +//: {mon_int8_sq_${i},int8_sq_${i}} <= {(${icvto}*2-1){1'b0}}; +//: ); +//: } +//: print qq( +//: end else if(load_din) begin +//: {mon_int8_sq_0,int8_sq_0} <= len9 ? (int8_abs_0 * int8_abs_0) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_1,int8_sq_1} <= ( len7|len9)? (int8_abs_1 * int8_abs_1) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_2,int8_sq_2} <= (len5|len7|len9)? (int8_abs_2 * int8_abs_2) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_3,int8_sq_3} <= (int8_abs_3 * int8_abs_3); +//: ); +//: foreach my $i (0..${tp}-1) { +//: my $j = 4 + $i; +//: print "{mon_int8_sq_${j},int8_sq_${j}} <= (int8_abs_${j} * int8_abs_${j}); \n"; +//: } +//: my $b0 = ${tp}+4+0; +//: my $b1 = ${tp}+4+1; +//: my $b2 = ${tp}+4+2; +//: my $b3 = ${tp}+4+3; +//: print qq( +//: {mon_int8_sq_${b0},int8_sq_${b0}} <= (int8_abs_${b0} * int8_abs_${b0}); +//: {mon_int8_sq_${b1},int8_sq_${b1}} <= (len5|len7|len9)? (int8_abs_${b1} * int8_abs_${b1}) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_${b2},int8_sq_${b2}} <= ( len7|len9)? (int8_abs_${b2} * int8_abs_${b2}) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_${b3},int8_sq_${b3}} <= len9 ? (int8_abs_${b3} * int8_abs_${b3}) : {(${icvto}*2){1'b0}}; +//: end +//: end +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign inv_0 = buf2sum_int8_0[9-1] ? (~buf2sum_int8_0[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_0 = buf2sum_int8_0[9-1] ? (inv_0[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_0; + +assign inv_1 = buf2sum_int8_1[9-1] ? (~buf2sum_int8_1[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_1 = buf2sum_int8_1[9-1] ? (inv_1[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_1; + +assign inv_2 = buf2sum_int8_2[9-1] ? (~buf2sum_int8_2[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_2 = buf2sum_int8_2[9-1] ? (inv_2[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_2; + +assign inv_3 = buf2sum_int8_3[9-1] ? (~buf2sum_int8_3[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_3 = buf2sum_int8_3[9-1] ? (inv_3[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_3; + +assign inv_4 = buf2sum_int8_4[9-1] ? (~buf2sum_int8_4[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_4 = buf2sum_int8_4[9-1] ? (inv_4[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_4; + +assign inv_5 = buf2sum_int8_5[9-1] ? (~buf2sum_int8_5[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_5 = buf2sum_int8_5[9-1] ? (inv_5[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_5; + +assign inv_6 = buf2sum_int8_6[9-1] ? (~buf2sum_int8_6[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_6 = buf2sum_int8_6[9-1] ? (inv_6[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_6; + +assign inv_7 = buf2sum_int8_7[9-1] ? (~buf2sum_int8_7[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_7 = buf2sum_int8_7[9-1] ? (inv_7[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_7; + +assign inv_8 = buf2sum_int8_8[9-1] ? (~buf2sum_int8_8[9-2:0]) : {(9-1){1'b0}}; +assign int8_abs_8 = buf2sum_int8_8[9-1] ? (inv_8[9-2:0] + {{(9-2){1'b0}},1'b1}) : buf2sum_int8_8; + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin + +{mon_int8_sq_0,int8_sq_0} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_1,int8_sq_1} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_2,int8_sq_2} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_3,int8_sq_3} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_4,int8_sq_4} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_5,int8_sq_5} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_6,int8_sq_6} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_7,int8_sq_7} <= {(9*2-1){1'b0}}; + +{mon_int8_sq_8,int8_sq_8} <= {(9*2-1){1'b0}}; + +end else if(load_din) begin +{mon_int8_sq_0,int8_sq_0} <= len9 ? (int8_abs_0 * int8_abs_0) : {(9*2){1'b0}}; +{mon_int8_sq_1,int8_sq_1} <= ( len7|len9)? (int8_abs_1 * int8_abs_1) : {(9*2){1'b0}}; +{mon_int8_sq_2,int8_sq_2} <= (len5|len7|len9)? (int8_abs_2 * int8_abs_2) : {(9*2){1'b0}}; +{mon_int8_sq_3,int8_sq_3} <= (int8_abs_3 * int8_abs_3); +{mon_int8_sq_4,int8_sq_4} <= (int8_abs_4 * int8_abs_4); + +{mon_int8_sq_5,int8_sq_5} <= (int8_abs_5 * int8_abs_5); +{mon_int8_sq_6,int8_sq_6} <= (len5|len7|len9)? (int8_abs_6 * int8_abs_6) : {(9*2){1'b0}}; +{mon_int8_sq_7,int8_sq_7} <= ( len7|len9)? (int8_abs_7 * int8_abs_7) : {(9*2){1'b0}}; +{mon_int8_sq_8,int8_sq_8} <= len9 ? (int8_abs_8 * int8_abs_8) : {(9*2){1'b0}}; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign buf2sum_din_prdy = ~buf2sum_d_vld | buf2sum_d_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf2sum_d_vld <= 1'b0; + end else begin + if(cdp_buf2sum_valid) + buf2sum_d_vld <= 1'b1; + else if(buf2sum_d_rdy) + buf2sum_d_vld <= 1'b0; + end +end +assign buf2sum_d_rdy = ~buf2sum_2d_vld | buf2sum_2d_rdy; +//=========== +//sum process +//----------- +assign len3 = (reg2dp_normalz_len[1:0] == 2'h0 ); +assign len5 = (reg2dp_normalz_len[1:0] == 2'h1 ); +assign len7 = (reg2dp_normalz_len[1:0] == 2'h2 ); +assign len9 = (reg2dp_normalz_len[1:0] == 2'h3 ); +assign load_din_d = buf2sum_d_vld & buf2sum_d_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf2sum_2d_vld <= 1'b0; + end else begin + if(buf2sum_d_vld) + buf2sum_2d_vld <= 1'b1; + else if(buf2sum_2d_rdy) + buf2sum_2d_vld <= 1'b0; + end +end +assign buf2sum_2d_rdy = ~buf2sum_3d_vld | buf2sum_3d_rdy ; +assign load_din_2d = buf2sum_2d_vld & buf2sum_2d_rdy; +//: my $tp=1; +//: my $icvto=(8 +1); +//: foreach my $i (0..${tp}-1) { +//: print "int_sum_block_tp1 u_sum_block_$i ( \n"; +//: print qq( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.len5 (len5) +//: ,.len7 (len7) +//: ,.len9 (len9) +//: ,.load_din_2d (load_din_2d) +//: ,.load_din_d (load_din_d) +//: ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) +//: ); +//: +//: foreach my $k (0..8) { +//: my $j = $k + $i; +//: print " ,.sq_pd_int8_${k} (int8_sq_${j}) \n"; +//: } +//: print qq( +//: ,.int8_sum (int8_sum_${i}) +//: ); +//: print " ); \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +int_sum_block_tp1 u_sum_block_0 ( + +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.len5 (len5) +,.len7 (len7) +,.len9 (len9) +,.load_din_2d (load_din_2d) +,.load_din_d (load_din_d) +,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.sq_pd_int8_0 (int8_sq_0) + ,.sq_pd_int8_1 (int8_sq_1) + ,.sq_pd_int8_2 (int8_sq_2) + ,.sq_pd_int8_3 (int8_sq_3) + ,.sq_pd_int8_4 (int8_sq_4) + ,.sq_pd_int8_5 (int8_sq_5) + ,.sq_pd_int8_6 (int8_sq_6) + ,.sq_pd_int8_7 (int8_sq_7) + ,.sq_pd_int8_8 (int8_sq_8) + +,.int8_sum (int8_sum_0) + ); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf2sum_3d_vld <= 1'b0; + end else begin + if(buf2sum_2d_vld) + buf2sum_3d_vld <= 1'b1; + else if(buf2sum_3d_rdy) + buf2sum_3d_vld <= 1'b0; + end +end +assign buf2sum_3d_rdy = sum_out_prdy; +//======================================================= +//data output select +//------------------------------------------------------- +assign sum_out_pd = { +//: my $tp=1; +//: if($tp > 1){ +//: foreach my $i (0..${tp}-2) { +//: my $j = ${tp} - $i -1; +//: print "int8_sum_${j}, "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +int8_sum_0}; +assign sum_out_pvld = buf2sum_3d_vld; +//////////////////////////////////// +//assign sum_out_prdy = sum2itp_ready; +//////////////////////////////////// +assign sum2itp_valid = sum_out_pvld; +assign sum2itp_data = sum_out_pd; +//======================================================= +////////::pipe -bc -is sum2itp_pd (sum2itp_pvld,sum2itp_prdy) <= sum2itp_data (sum2itp_valid,sum2itp_ready); +//: my $k = 1*21; +//: &eperl::pipe("-wid $k -is -do sum2itp_pd -vo sum2itp_pvld -ri sum2itp_prdy -di sum2itp_data -vi sum2itp_valid -ro sum2itp_ready "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg sum2itp_ready; +reg skid_flop_sum2itp_ready; +reg skid_flop_sum2itp_valid; +reg [21-1:0] skid_flop_sum2itp_data; +reg pipe_skid_sum2itp_valid; +reg [21-1:0] pipe_skid_sum2itp_data; +// Wire +wire skid_sum2itp_valid; +wire [21-1:0] skid_sum2itp_data; +wire skid_sum2itp_ready; +wire pipe_skid_sum2itp_ready; +wire sum2itp_pvld; +wire [21-1:0] sum2itp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sum2itp_ready <= 1'b1; + skid_flop_sum2itp_ready <= 1'b1; + end else begin + sum2itp_ready <= skid_sum2itp_ready; + skid_flop_sum2itp_ready <= skid_sum2itp_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_sum2itp_valid <= 1'b0; + end else begin + if (skid_flop_sum2itp_ready) begin + skid_flop_sum2itp_valid <= sum2itp_valid; + end + end +end +assign skid_sum2itp_valid = (skid_flop_sum2itp_ready) ? sum2itp_valid : skid_flop_sum2itp_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_sum2itp_ready & sum2itp_valid) begin + skid_flop_sum2itp_data[21-1:0] <= sum2itp_data[21-1:0]; + end +end +assign skid_sum2itp_data[21-1:0] = (skid_flop_sum2itp_ready) ? sum2itp_data[21-1:0] : skid_flop_sum2itp_data[21-1:0]; + + +// PIPE READY +assign skid_sum2itp_ready = pipe_skid_sum2itp_ready || !pipe_skid_sum2itp_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_sum2itp_valid <= 1'b0; + end else begin + if (skid_sum2itp_ready) begin + pipe_skid_sum2itp_valid <= skid_sum2itp_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_sum2itp_ready && skid_sum2itp_valid) begin + pipe_skid_sum2itp_data[21-1:0] <= skid_sum2itp_data[21-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_sum2itp_ready = sum2itp_prdy; +assign sum2itp_pvld = pipe_skid_sum2itp_valid; +assign sum2itp_pd = pipe_skid_sum2itp_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign sum_out_prdy = sum2itp_ready; +///////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_sum diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v.vcp new file mode 100644 index 0000000..1fdf417 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v.vcp @@ -0,0 +1,280 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_sum.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_sum ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,normalz_buf_data //|< i + ,normalz_buf_data_pvld //|< i + ,reg2dp_normalz_len //|< i + ,sum2itp_prdy //|< i + ,normalz_buf_data_prdy //|> o + ,sum2itp_pd //|> o + ,sum2itp_pvld //|> o + ); +///////////////////////////////////////////////////// +// parameter pINT8_BW = 9; +///////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $k = ${icvto}*(${tp}+8)+15; +//: print qq( +//: input [${k}-1:0] normalz_buf_data; +//: output [${tp}*(${icvto}*2+3)-1:0] sum2itp_pd; +//: ); +input normalz_buf_data_pvld; +input [1:0] reg2dp_normalz_len; +input sum2itp_prdy; +output normalz_buf_data_prdy; +output sum2itp_pvld; +///////////////////////////////////////////////////// +reg buf2sum_2d_vld; +reg buf2sum_3d_vld; +reg buf2sum_d_vld; +wire buf2sum_2d_rdy; +wire buf2sum_3d_rdy; +wire buf2sum_d_rdy; +wire buf2sum_din_prdy; +wire buf2sum_rdy_f; +wire cdp_buf2sum_ready; +//: my $icvto=(8 +1); +//: my $tp=1 +8; +//: foreach my $i (0..${tp}-1) { +//: print qq( +//: wire [${icvto}-1:0] buf2sum_int8_$i; +//: wire [${icvto}-1:0] inv_${i}; +//: wire [${icvto}-1:0] int8_abs_${i}; +//: reg [${icvto}*2-2:0] int8_sq_${i}; +//: reg mon_int8_sq_${i}; +//: ); +//: } +wire [7:0] int8_inv_2; +wire [7:0] int8_inv_3; +wire [7:0] int8_inv_4; +wire [7:0] int8_inv_5; +wire [7:0] int8_inv_6; +wire [7:0] int8_inv_7; +wire [7:0] int8_inv_8; +wire [7:0] int8_inv_9; +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $k = ${tp}*(${icvto}*2+3); +//: print qq( +//: wire [${k}-1:0] sum_out_pd; +//: wire [${k}-1:0] sum2itp_data; +//: ); +//: foreach my $i (0..$tp-1){ +//: print qq( +//: wire [${icvto}*2-1+4-1:0] int8_sum_$i; +//: ); +//: } +wire [41:0] int8_sum_1st; +wire [41:0] int8_sum_2nd; +wire [41:0] int8_sum_3rd; +wire [41:0] int8_sum_4th; +wire [15:0] int_ivt_2; +wire [15:0] int_ivt_3; +wire [15:0] int_ivt_4; +wire [15:0] int_ivt_5; +wire [15:0] int_ivt_6; +wire [15:0] int_ivt_7; +wire [15:0] int_ivt_8; +wire [15:0] int_ivt_9; +wire [16:0] int_sq_datin_2; +wire [16:0] int_sq_datin_3; +wire [16:0] int_sq_datin_4; +wire [16:0] int_sq_datin_5; +wire [16:0] int_sq_datin_6; +wire [16:0] int_sq_datin_7; +wire [16:0] int_sq_datin_8; +wire [16:0] int_sq_datin_9; +wire [16:0] int_sq_datin_abs_2; +wire [16:0] int_sq_datin_abs_3; +wire [16:0] int_sq_datin_abs_4; +wire [16:0] int_sq_datin_abs_5; +wire [16:0] int_sq_datin_abs_6; +wire [16:0] int_sq_datin_abs_7; +wire [16:0] int_sq_datin_abs_8; +wire [16:0] int_sq_datin_abs_9; +wire len3; +wire len5; +wire len7; +wire len9; +wire load_din; +wire load_din_2d; +wire load_din_d; +wire sum2itp_valid; +wire sum_out_prdy; +wire sum_out_pvld; +/////////////////////////////////////////// +//========================================== +//---------------------------------------- +////////::pipe -bc cdp_buf2sum_pd (cdp_buf2sum_valid,cdp_buf2sum_ready) <= normalz_buf_data[230:0] (normalz_buf_data_pvld,normalz_buf_data_prdy); +//: my $tp=1; +//: my $icvto=(8 +1); +//: my $k = ${icvto}*(${tp}+8)+15; +//: &eperl::pipe(" -wid $k -do cdp_buf2sum_pd -vo cdp_buf2sum_valid -ri cdp_buf2sum_ready -di normalz_buf_data -vi normalz_buf_data_pvld -ro normalz_buf_data_prdy "); +///////////////////////////////////////////// +assign load_din = (cdp_buf2sum_valid & buf2sum_rdy_f); +assign cdp_buf2sum_ready = buf2sum_rdy_f; +assign buf2sum_rdy_f = buf2sum_din_prdy; +//========================================== +//: my $icvto=(8 +1); +//: my $tp=1 +8; +//: foreach my $i (0..${tp}-1) { +//: print qq( +//: assign buf2sum_int8_$i = cdp_buf2sum_pd[${icvto}*${i}+${icvto}-1:${icvto}*${i}]; +//: ); +//: } +//======================================================== +//int mode +//-------------------------------------------------------- +//: my $tp=1; +//: my $icvto=(8 +1); +//: foreach my $i (0..${tp}+8-1) { +//: print qq( +//: assign inv_${i} = buf2sum_int8_${i}[${icvto}-1] ? (~buf2sum_int8_${i}[${icvto}-2:0]) : {(${icvto}-1){1'b0}}; +//: assign int8_abs_${i} = buf2sum_int8_${i}[${icvto}-1] ? (inv_${i}[${icvto}-2:0] + {{(${icvto}-2){1'b0}},1'b1}) : buf2sum_int8_${i}; +//: ); +//: } +//: +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: ); +//: foreach my $i (0..${tp}+8-1) { +//: print qq( +//: {mon_int8_sq_${i},int8_sq_${i}} <= {(${icvto}*2-1){1'b0}}; +//: ); +//: } +//: print qq( +//: end else if(load_din) begin +//: {mon_int8_sq_0,int8_sq_0} <= len9 ? (int8_abs_0 * int8_abs_0) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_1,int8_sq_1} <= ( len7|len9)? (int8_abs_1 * int8_abs_1) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_2,int8_sq_2} <= (len5|len7|len9)? (int8_abs_2 * int8_abs_2) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_3,int8_sq_3} <= (int8_abs_3 * int8_abs_3); +//: ); +//: foreach my $i (0..${tp}-1) { +//: my $j = 4 + $i; +//: print "{mon_int8_sq_${j},int8_sq_${j}} <= (int8_abs_${j} * int8_abs_${j}); \n"; +//: } +//: my $b0 = ${tp}+4+0; +//: my $b1 = ${tp}+4+1; +//: my $b2 = ${tp}+4+2; +//: my $b3 = ${tp}+4+3; +//: print qq( +//: {mon_int8_sq_${b0},int8_sq_${b0}} <= (int8_abs_${b0} * int8_abs_${b0}); +//: {mon_int8_sq_${b1},int8_sq_${b1}} <= (len5|len7|len9)? (int8_abs_${b1} * int8_abs_${b1}) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_${b2},int8_sq_${b2}} <= ( len7|len9)? (int8_abs_${b2} * int8_abs_${b2}) : {(${icvto}*2){1'b0}}; +//: {mon_int8_sq_${b3},int8_sq_${b3}} <= len9 ? (int8_abs_${b3} * int8_abs_${b3}) : {(${icvto}*2){1'b0}}; +//: end +//: end +//: ); +assign buf2sum_din_prdy = ~buf2sum_d_vld | buf2sum_d_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf2sum_d_vld <= 1'b0; + end else begin + if(cdp_buf2sum_valid) + buf2sum_d_vld <= 1'b1; + else if(buf2sum_d_rdy) + buf2sum_d_vld <= 1'b0; + end +end +assign buf2sum_d_rdy = ~buf2sum_2d_vld | buf2sum_2d_rdy; +//=========== +//sum process +//----------- +assign len3 = (reg2dp_normalz_len[1:0] == 2'h0 ); +assign len5 = (reg2dp_normalz_len[1:0] == 2'h1 ); +assign len7 = (reg2dp_normalz_len[1:0] == 2'h2 ); +assign len9 = (reg2dp_normalz_len[1:0] == 2'h3 ); +assign load_din_d = buf2sum_d_vld & buf2sum_d_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf2sum_2d_vld <= 1'b0; + end else begin + if(buf2sum_d_vld) + buf2sum_2d_vld <= 1'b1; + else if(buf2sum_2d_rdy) + buf2sum_2d_vld <= 1'b0; + end +end +assign buf2sum_2d_rdy = ~buf2sum_3d_vld | buf2sum_3d_rdy ; +assign load_din_2d = buf2sum_2d_vld & buf2sum_2d_rdy; +//: my $tp=1; +//: my $icvto=(8 +1); +//: foreach my $i (0..${tp}-1) { +//: print "int_sum_block_tp1 u_sum_block_$i ( \n"; +//: print qq( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.len5 (len5) +//: ,.len7 (len7) +//: ,.len9 (len9) +//: ,.load_din_2d (load_din_2d) +//: ,.load_din_d (load_din_d) +//: ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) +//: ); +//: +//: foreach my $k (0..8) { +//: my $j = $k + $i; +//: print " ,.sq_pd_int8_${k} (int8_sq_${j}) \n"; +//: } +//: print qq( +//: ,.int8_sum (int8_sum_${i}) +//: ); +//: print " ); \n"; +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buf2sum_3d_vld <= 1'b0; + end else begin + if(buf2sum_2d_vld) + buf2sum_3d_vld <= 1'b1; + else if(buf2sum_3d_rdy) + buf2sum_3d_vld <= 1'b0; + end +end +assign buf2sum_3d_rdy = sum_out_prdy; +//======================================================= +//data output select +//------------------------------------------------------- +assign sum_out_pd = { +//: my $tp=1; +//: if($tp > 1){ +//: foreach my $i (0..${tp}-2) { +//: my $j = ${tp} - $i -1; +//: print "int8_sum_${j}, "; +//: } +//: } +int8_sum_0}; +assign sum_out_pvld = buf2sum_3d_vld; +//////////////////////////////////// +//assign sum_out_prdy = sum2itp_ready; +//////////////////////////////////// +assign sum2itp_valid = sum_out_pvld; +assign sum2itp_data = sum_out_pd; +//======================================================= +////////::pipe -bc -is sum2itp_pd (sum2itp_pvld,sum2itp_prdy) <= sum2itp_data (sum2itp_valid,sum2itp_ready); +//: my $k = 1*21; +//: &eperl::pipe("-wid $k -is -do sum2itp_pd -vo sum2itp_pvld -ri sum2itp_prdy -di sum2itp_data -vi sum2itp_valid -ro sum2itp_ready "); +assign sum_out_prdy = sum2itp_ready; +///////////////////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_sum diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v new file mode 100644 index 0000000..75e8f1c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v @@ -0,0 +1,1988 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_syncfifo.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_syncfifo ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt2sync_pd //|< i + ,cvt2sync_pvld //|< i + ,pwrbus_ram_pd //|< i + ,sum2sync_pd //|< i + ,sum2sync_pvld //|< i + ,sync2itp_prdy //|< i + ,sync2mul_prdy //|< i + ,sync2ocvt_prdy //|< i + ,cvt2sync_prdy //|> o + ,sum2sync_prdy //|> o + ,sync2itp_pd //|> o + ,sync2itp_pvld //|> o + ,sync2mul_pd //|> o + ,sync2mul_pvld //|> o + ,sync2ocvt_pd //|> o + ,sync2ocvt_pvld //|> o + ); +/////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*(8 +1)+14:0] cvt2sync_pd; +input cvt2sync_pvld; +input [31:0] pwrbus_ram_pd; +input [1*((8 +1)*2+3)-1:0] sum2sync_pd; +input sum2sync_pvld; +input sync2itp_prdy; +input sync2mul_prdy; +input sync2ocvt_prdy; +output cvt2sync_prdy; +output sum2sync_prdy; +output [1*((8 +1)*2+3)-1:0] sync2itp_pd; +output sync2itp_pvld; +output [1*(8 +1)-1:0] sync2mul_pd; +output sync2mul_pvld; +output [14:0] sync2ocvt_pd; +output sync2ocvt_pvld; +/////////////////////////////////////////////////// +//reg [1 * (8 +1)-1:0] data_sync_wr_pd; +//reg data_sync_wr_pvld; +//reg [14:0] info_sync_wr_pd; +//reg info_sync_wr_pvld; +wire [1 * (8 +1)-1:0] data_pd; +wire [1 * (8 +1)-1:0] data_sync_rd_pd; +wire data_sync_rd_prdy; +wire data_sync_rd_pvld; +wire data_sync_wr_prdy; +wire data_vld; +wire [14:0] info_pd; +wire [14:0] info_sync_rd_pd; +wire info_sync_rd_prdy; +wire info_sync_rd_pvld; +wire info_sync_wr_prdy; +wire info_vld; +////////////////////////////////////////////// +////////////////////////////////////////////// +//## pipe (1) randomizer +//: my $dbw = 1 * (8 +1); +//: &eperl::pipe(" -wid $dbw -do data_sync_wr_pd -vo data_sync_wr_pvld -ri data_sync_wr_prdy -di data_pd -vi data_vld -ro data_rdy "); +//: &eperl::pipe(" -wid 15 -do info_sync_wr_pd -vo info_sync_wr_pvld -ri info_sync_wr_prdy -di info_pd -vi info_vld -ro info_rdy "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg pipe_data_vld; +reg [9-1:0] pipe_data_pd; +// Wire +wire data_rdy; +wire pipe_data_rdy; +wire data_sync_wr_pvld; +wire [9-1:0] data_sync_wr_pd; +// Code +// PIPE READY +assign data_rdy = pipe_data_rdy || !pipe_data_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_data_vld <= 1'b0; + end else begin + if (data_rdy) begin + pipe_data_vld <= data_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (data_rdy && data_vld) begin + pipe_data_pd[9-1:0] <= data_pd[9-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_data_rdy = data_sync_wr_prdy; +assign data_sync_wr_pvld = pipe_data_vld; +assign data_sync_wr_pd = pipe_data_pd; +// Reg +reg pipe_info_vld; +reg [15-1:0] pipe_info_pd; +// Wire +wire info_rdy; +wire pipe_info_rdy; +wire info_sync_wr_pvld; +wire [15-1:0] info_sync_wr_pd; +// Code +// PIPE READY +assign info_rdy = pipe_info_rdy || !pipe_info_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_info_vld <= 1'b0; + end else begin + if (info_rdy) begin + pipe_info_vld <= info_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (info_rdy && info_vld) begin + pipe_info_pd[15-1:0] <= info_pd[15-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_info_rdy = info_sync_wr_prdy; +assign info_sync_wr_pvld = pipe_info_vld; +assign info_sync_wr_pd = pipe_info_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////// +//datin sync fifo +assign cvt2sync_prdy = data_rdy & info_rdy; +assign data_vld = cvt2sync_pvld & info_rdy; +assign info_vld = cvt2sync_pvld & data_rdy; +assign data_pd = cvt2sync_pd[1 * (8 +1)-1:0]; +assign info_pd = cvt2sync_pd[1 * (8 +1)+14:1 * (8 +1)]; +////////////////////////////////////////////// +////////////////////////////////////////////// +NV_NVDLA_CDP_DP_data_fifo u_data_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_wr_prdy (data_sync_wr_prdy) //|> w + ,.data_wr_pvld (data_sync_wr_pvld) //|< r + ,.data_wr_pd (data_sync_wr_pd ) //|< r + ,.data_rd_prdy (data_sync_rd_prdy) //|< w + ,.data_rd_pvld (data_sync_rd_pvld) //|> w + ,.data_rd_pd (data_sync_rd_pd ) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign data_sync_rd_prdy = sync2mul_prdy; +assign sync2mul_pvld= data_sync_rd_pvld; +assign sync2mul_pd = data_sync_rd_pd ; +NV_NVDLA_CDP_DP_info_fifo u_info_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.info_wr_prdy (info_sync_wr_prdy) //|> w + ,.info_wr_pvld (info_sync_wr_pvld) //|< r + ,.info_wr_pd (info_sync_wr_pd[14:0]) //|< r + ,.info_rd_prdy (info_sync_rd_prdy) //|< w + ,.info_rd_pvld (info_sync_rd_pvld) //|> w + ,.info_rd_pd (info_sync_rd_pd[14:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign sync2ocvt_pd = info_sync_rd_pd[14:0]; +assign sync2ocvt_pvld = info_sync_rd_pvld; +assign info_sync_rd_prdy = sync2ocvt_prdy; +/////////////////////////////////////////// +NV_NVDLA_CDP_DP_sumpd_fifo u_sumpd_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sumpd_wr_prdy (sum2sync_prdy) //|> o + ,.sumpd_wr_pvld (sum2sync_pvld) //|< i + ,.sumpd_wr_pd (sum2sync_pd ) //|< i + ,.sumpd_rd_prdy (sync2itp_prdy) //|< i + ,.sumpd_rd_pvld (sync2itp_pvld) //|> o + ,.sumpd_rd_pd (sync2itp_pd ) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_syncfifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_DP_info_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus info_wr -rd_pipebus info_rd -rd_reg -ram_bypass -d 80 -w 15 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_info_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , info_wr_prdy + , info_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , info_wr_pause +`endif + , info_wr_pd + , info_rd_prdy + , info_rd_pvld + , info_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output info_wr_prdy; +input info_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input info_wr_pause; +`endif +input [14:0] info_wr_pd; +input info_rd_prdy; +output info_rd_pvld; +output [14:0] info_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg info_wr_busy_int; // copy for internal use +assign info_wr_prdy = !info_wr_busy_int; +assign wr_reserving = info_wr_pvld && !info_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [6:0] info_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? info_wr_count : (info_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (info_wr_count + 1'd1) : info_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire info_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check info_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || info_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire info_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check info_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_wr_busy_int <= 1'b0; + info_wr_count <= 7'd0; + end else begin + info_wr_busy_int <= info_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + info_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + info_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as info_wr_pvld +// +// RAM +// +reg [6:0] info_wr_adr; // current write address +wire [6:0] info_rd_adr_p; // read address to use for ram +wire [14:0] info_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_80x15 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( info_wr_adr ) + , .we ( wr_pushing && (info_wr_count != 7'd0 || !rd_popping) ) + , .di ( info_wr_pd ) + , .ra ( info_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( info_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( info_wr_pd[14:0] ) + , .ore ( ore ) + ); +// next info_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (info_wr_adr == 7'd79) ? 7'd0 : (info_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + info_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + info_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [6:0] info_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (info_rd_adr == 7'd79) ? 7'd0 : (info_rd_adr + 1'd1); // spyglass disable W484 +assign info_rd_adr_p = rd_popping ? rd_adr_next : info_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + info_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + info_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (info_wr_adr == rd_adr_next) : (info_wr_adr == info_rd_adr)); +wire [14:0] info_rd_pd_p_byp = info_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = info_wr_count == 0; +wire [14:0] info_rd_pd_p = info_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire info_rd_pvld_p; // data out of fifo is valid +reg info_rd_pvld_int; // internal copy of info_rd_pvld +assign info_rd_pvld = info_rd_pvld_int; +assign rd_popping = info_rd_pvld_p && !(info_rd_pvld_int && !info_rd_prdy); +reg [6:0] info_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? info_rd_count_p : + (info_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (info_rd_count_p + 1'd1) : + info_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign info_rd_pvld_p = info_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~info_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_rd_count_p <= 7'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + info_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + info_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (info_rd_pvld_p || (info_rd_pvld_int && !info_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_rd_pvld_int <= 1'b0; + end else begin + info_rd_pvld_int <= rd_req_next; + end +end +assign info_rd_pd = info_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (info_wr_pvld && !info_wr_busy_int) || (info_wr_busy_int != info_wr_busy_next)) || (rd_pushing || rd_popping || (info_rd_pvld_int && info_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_info_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_info_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( info_wr_pvld && !(!info_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, info_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_info_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_info_fifo +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_data_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , data_wr_prdy + , data_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , data_wr_pause +`endif + , data_wr_pd + , data_rd_prdy + , data_rd_pvld + , data_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output data_wr_prdy; +input data_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input data_wr_pause; +`endif +input [8:0] data_wr_pd; +input data_rd_prdy; +output data_rd_pvld; +output [8:0] data_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg data_wr_busy_int; // copy for internal use +assign data_wr_prdy = !data_wr_busy_int; +assign wr_reserving = data_wr_pvld && !data_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [6:0] data_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? data_wr_count : (data_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (data_wr_count + 1'd1) : data_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire data_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check data_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || data_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire data_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check data_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_wr_busy_int <= 1'b0; + data_wr_count <= 7'd0; + end else begin + data_wr_busy_int <= data_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + data_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + data_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as data_wr_pvld +// +// RAM +// +reg [6:0] data_wr_adr; // current write address +wire [6:0] data_rd_adr_p; // read address to use for ram +wire [8:0] data_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_80x9 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( data_wr_adr ) + , .we ( wr_pushing && (data_wr_count != 7'd0 || !rd_popping) ) + , .di ( data_wr_pd ) + , .ra ( data_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( data_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( data_wr_pd[8:0] ) + , .ore ( ore ) + ); +// next data_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (data_wr_adr == 7'd79) ? 7'd0 : (data_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + data_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + data_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [6:0] data_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (data_rd_adr == 7'd79) ? 7'd0 : (data_rd_adr + 1'd1); // spyglass disable W484 +assign data_rd_adr_p = rd_popping ? rd_adr_next : data_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + data_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + data_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (data_wr_adr == rd_adr_next) : (data_wr_adr == data_rd_adr)); +wire [8:0] data_rd_pd_p_byp = data_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = data_wr_count == 0; +wire [8:0] data_rd_pd_p = data_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire data_rd_pvld_p; // data out of fifo is valid +reg data_rd_pvld_int; // internal copy of data_rd_pvld +assign data_rd_pvld = data_rd_pvld_int; +assign rd_popping = data_rd_pvld_p && !(data_rd_pvld_int && !data_rd_prdy); +reg [6:0] data_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? data_rd_count_p : + (data_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (data_rd_count_p + 1'd1) : + data_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign data_rd_pvld_p = data_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~data_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_rd_count_p <= 7'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + data_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + data_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (data_rd_pvld_p || (data_rd_pvld_int && !data_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_rd_pvld_int <= 1'b0; + end else begin + data_rd_pvld_int <= rd_req_next; + end +end +assign data_rd_pd = data_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (data_wr_pvld && !data_wr_busy_int) || (data_wr_busy_int != data_wr_busy_next)) || (rd_pushing || rd_popping || (data_rd_pvld_int && data_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_data_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_data_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( data_wr_pvld && !(!data_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, data_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_data_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_data_fifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_DP_sumpd_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus sumpd_wr -rd_pipebus sumpd_rd -rd_reg -ram_bypass -d 60 -w 21 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_sumpd_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , sumpd_wr_prdy + , sumpd_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , sumpd_wr_pause +`endif + , sumpd_wr_pd + , sumpd_rd_prdy + , sumpd_rd_pvld + , sumpd_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output sumpd_wr_prdy; +input sumpd_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input sumpd_wr_pause; +`endif +input [20:0] sumpd_wr_pd; +input sumpd_rd_prdy; +output sumpd_rd_pvld; +output [20:0] sumpd_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg sumpd_wr_busy_int; // copy for internal use +assign sumpd_wr_prdy = !sumpd_wr_busy_int; +assign wr_reserving = sumpd_wr_pvld && !sumpd_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [5:0] sumpd_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? sumpd_wr_count : (sumpd_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (sumpd_wr_count + 1'd1) : sumpd_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_60 = ( wr_count_next_no_wr_popping == 6'd60 ); +wire wr_count_next_is_60 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_60; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire sumpd_wr_busy_next = wr_count_next_is_60 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check sumpd_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || sumpd_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire sumpd_wr_busy_next = wr_count_next_is_60 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check sumpd_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_wr_busy_int <= 1'b0; + sumpd_wr_count <= 6'd0; + end else begin + sumpd_wr_busy_int <= sumpd_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + sumpd_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + sumpd_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as sumpd_wr_pvld +// +// RAM +// +reg [5:0] sumpd_wr_adr; // current write address +wire [5:0] sumpd_rd_adr_p; // read address to use for ram +wire [20:0] sumpd_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_60x21 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( sumpd_wr_adr ) + , .we ( wr_pushing && (sumpd_wr_count != 6'd0 || !rd_popping) ) + , .di ( sumpd_wr_pd ) + , .ra ( sumpd_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( sumpd_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( sumpd_wr_pd[20:0] ) + , .ore ( ore ) + ); +// next sumpd_wr_adr if wr_pushing=1 +wire [5:0] wr_adr_next = (sumpd_wr_adr == 6'd59) ? 6'd0 : (sumpd_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_wr_adr <= 6'd0; + end else begin + if ( wr_pushing ) begin + sumpd_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + sumpd_wr_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [5:0] sumpd_rd_adr; // current read address +// next read address +wire [5:0] rd_adr_next = (sumpd_rd_adr == 6'd59) ? 6'd0 : (sumpd_rd_adr + 1'd1); // spyglass disable W484 +assign sumpd_rd_adr_p = rd_popping ? rd_adr_next : sumpd_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_rd_adr <= 6'd0; + end else begin + if ( rd_popping ) begin + sumpd_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + sumpd_rd_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (sumpd_wr_adr == rd_adr_next) : (sumpd_wr_adr == sumpd_rd_adr)); +wire [20:0] sumpd_rd_pd_p_byp = sumpd_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = sumpd_wr_count == 0; +wire [20:0] sumpd_rd_pd_p = sumpd_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire sumpd_rd_pvld_p; // data out of fifo is valid +reg sumpd_rd_pvld_int; // internal copy of sumpd_rd_pvld +assign sumpd_rd_pvld = sumpd_rd_pvld_int; +assign rd_popping = sumpd_rd_pvld_p && !(sumpd_rd_pvld_int && !sumpd_rd_prdy); +reg [5:0] sumpd_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? sumpd_rd_count_p : + (sumpd_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (sumpd_rd_count_p + 1'd1) : + sumpd_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign sumpd_rd_pvld_p = sumpd_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~sumpd_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_rd_count_p <= 6'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + sumpd_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + sumpd_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (sumpd_rd_pvld_p || (sumpd_rd_pvld_int && !sumpd_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_rd_pvld_int <= 1'b0; + end else begin + sumpd_rd_pvld_int <= rd_req_next; + end +end +assign sumpd_rd_pd = sumpd_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (sumpd_wr_pvld && !sumpd_wr_busy_int) || (sumpd_wr_busy_int != sumpd_wr_busy_next)) || (rd_pushing || rd_popping || (sumpd_rd_pvld_int && sumpd_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( sumpd_wr_pvld && !(!sumpd_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd60 : wr_limit_reg} ) + , .curr ( {26'd0, sumpd_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_sumpd_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_sumpd_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v.vcp new file mode 100644 index 0000000..b7c5e1b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v.vcp @@ -0,0 +1,1915 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_DP_syncfifo.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_DP_syncfifo ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt2sync_pd //|< i + ,cvt2sync_pvld //|< i + ,pwrbus_ram_pd //|< i + ,sum2sync_pd //|< i + ,sum2sync_pvld //|< i + ,sync2itp_prdy //|< i + ,sync2mul_prdy //|< i + ,sync2ocvt_prdy //|< i + ,cvt2sync_prdy //|> o + ,sum2sync_prdy //|> o + ,sync2itp_pd //|> o + ,sync2itp_pvld //|> o + ,sync2mul_pd //|> o + ,sync2mul_pvld //|> o + ,sync2ocvt_pd //|> o + ,sync2ocvt_pvld //|> o + ); +/////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1*(8 +1)+14:0] cvt2sync_pd; +input cvt2sync_pvld; +input [31:0] pwrbus_ram_pd; +input [1*((8 +1)*2+3)-1:0] sum2sync_pd; +input sum2sync_pvld; +input sync2itp_prdy; +input sync2mul_prdy; +input sync2ocvt_prdy; +output cvt2sync_prdy; +output sum2sync_prdy; +output [1*((8 +1)*2+3)-1:0] sync2itp_pd; +output sync2itp_pvld; +output [1*(8 +1)-1:0] sync2mul_pd; +output sync2mul_pvld; +output [14:0] sync2ocvt_pd; +output sync2ocvt_pvld; +/////////////////////////////////////////////////// +//reg [1 * (8 +1)-1:0] data_sync_wr_pd; +//reg data_sync_wr_pvld; +//reg [14:0] info_sync_wr_pd; +//reg info_sync_wr_pvld; +wire [1 * (8 +1)-1:0] data_pd; +wire [1 * (8 +1)-1:0] data_sync_rd_pd; +wire data_sync_rd_prdy; +wire data_sync_rd_pvld; +wire data_sync_wr_prdy; +wire data_vld; +wire [14:0] info_pd; +wire [14:0] info_sync_rd_pd; +wire info_sync_rd_prdy; +wire info_sync_rd_pvld; +wire info_sync_wr_prdy; +wire info_vld; +////////////////////////////////////////////// +////////////////////////////////////////////// +//## pipe (1) randomizer +//: my $dbw = 1 * (8 +1); +//: &eperl::pipe(" -wid $dbw -do data_sync_wr_pd -vo data_sync_wr_pvld -ri data_sync_wr_prdy -di data_pd -vi data_vld -ro data_rdy "); +//: &eperl::pipe(" -wid 15 -do info_sync_wr_pd -vo info_sync_wr_pvld -ri info_sync_wr_prdy -di info_pd -vi info_vld -ro info_rdy "); +////////////////////////////////////////////// +//datin sync fifo +assign cvt2sync_prdy = data_rdy & info_rdy; +assign data_vld = cvt2sync_pvld & info_rdy; +assign info_vld = cvt2sync_pvld & data_rdy; +assign data_pd = cvt2sync_pd[1 * (8 +1)-1:0]; +assign info_pd = cvt2sync_pd[1 * (8 +1)+14:1 * (8 +1)]; +////////////////////////////////////////////// +////////////////////////////////////////////// +NV_NVDLA_CDP_DP_data_fifo u_data_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.data_wr_prdy (data_sync_wr_prdy) //|> w + ,.data_wr_pvld (data_sync_wr_pvld) //|< r + ,.data_wr_pd (data_sync_wr_pd ) //|< r + ,.data_rd_prdy (data_sync_rd_prdy) //|< w + ,.data_rd_pvld (data_sync_rd_pvld) //|> w + ,.data_rd_pd (data_sync_rd_pd ) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign data_sync_rd_prdy = sync2mul_prdy; +assign sync2mul_pvld= data_sync_rd_pvld; +assign sync2mul_pd = data_sync_rd_pd ; +NV_NVDLA_CDP_DP_info_fifo u_info_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.info_wr_prdy (info_sync_wr_prdy) //|> w + ,.info_wr_pvld (info_sync_wr_pvld) //|< r + ,.info_wr_pd (info_sync_wr_pd[14:0]) //|< r + ,.info_rd_prdy (info_sync_rd_prdy) //|< w + ,.info_rd_pvld (info_sync_rd_pvld) //|> w + ,.info_rd_pd (info_sync_rd_pd[14:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign sync2ocvt_pd = info_sync_rd_pd[14:0]; +assign sync2ocvt_pvld = info_sync_rd_pvld; +assign info_sync_rd_prdy = sync2ocvt_prdy; +/////////////////////////////////////////// +NV_NVDLA_CDP_DP_sumpd_fifo u_sumpd_sync_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sumpd_wr_prdy (sum2sync_prdy) //|> o + ,.sumpd_wr_pvld (sum2sync_pvld) //|< i + ,.sumpd_wr_pd (sum2sync_pd ) //|< i + ,.sumpd_rd_prdy (sync2itp_prdy) //|< i + ,.sumpd_rd_pvld (sync2itp_pvld) //|> o + ,.sumpd_rd_pd (sync2itp_pd ) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +/////////////////////////////////////////// +endmodule // NV_NVDLA_CDP_DP_syncfifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_DP_info_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus info_wr -rd_pipebus info_rd -rd_reg -ram_bypass -d 80 -w 15 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_info_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , info_wr_prdy + , info_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , info_wr_pause +`endif + , info_wr_pd + , info_rd_prdy + , info_rd_pvld + , info_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output info_wr_prdy; +input info_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input info_wr_pause; +`endif +input [14:0] info_wr_pd; +input info_rd_prdy; +output info_rd_pvld; +output [14:0] info_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg info_wr_busy_int; // copy for internal use +assign info_wr_prdy = !info_wr_busy_int; +assign wr_reserving = info_wr_pvld && !info_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [6:0] info_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? info_wr_count : (info_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (info_wr_count + 1'd1) : info_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire info_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check info_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || info_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire info_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check info_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_wr_busy_int <= 1'b0; + info_wr_count <= 7'd0; + end else begin + info_wr_busy_int <= info_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + info_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + info_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as info_wr_pvld +// +// RAM +// +reg [6:0] info_wr_adr; // current write address +wire [6:0] info_rd_adr_p; // read address to use for ram +wire [14:0] info_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_80x15 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( info_wr_adr ) + , .we ( wr_pushing && (info_wr_count != 7'd0 || !rd_popping) ) + , .di ( info_wr_pd ) + , .ra ( info_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( info_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( info_wr_pd[14:0] ) + , .ore ( ore ) + ); +// next info_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (info_wr_adr == 7'd79) ? 7'd0 : (info_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + info_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + info_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [6:0] info_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (info_rd_adr == 7'd79) ? 7'd0 : (info_rd_adr + 1'd1); // spyglass disable W484 +assign info_rd_adr_p = rd_popping ? rd_adr_next : info_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + info_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + info_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (info_wr_adr == rd_adr_next) : (info_wr_adr == info_rd_adr)); +wire [14:0] info_rd_pd_p_byp = info_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = info_wr_count == 0; +wire [14:0] info_rd_pd_p = info_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire info_rd_pvld_p; // data out of fifo is valid +reg info_rd_pvld_int; // internal copy of info_rd_pvld +assign info_rd_pvld = info_rd_pvld_int; +assign rd_popping = info_rd_pvld_p && !(info_rd_pvld_int && !info_rd_prdy); +reg [6:0] info_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? info_rd_count_p : + (info_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (info_rd_count_p + 1'd1) : + info_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign info_rd_pvld_p = info_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~info_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_rd_count_p <= 7'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + info_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + info_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (info_rd_pvld_p || (info_rd_pvld_int && !info_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + info_rd_pvld_int <= 1'b0; + end else begin + info_rd_pvld_int <= rd_req_next; + end +end +assign info_rd_pd = info_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (info_wr_pvld && !info_wr_busy_int) || (info_wr_busy_int != info_wr_busy_next)) || (rd_pushing || rd_popping || (info_rd_pvld_int && info_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_info_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_info_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_info_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( info_wr_pvld && !(!info_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, info_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_info_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_info_fifo +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_data_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , data_wr_prdy + , data_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , data_wr_pause +`endif + , data_wr_pd + , data_rd_prdy + , data_rd_pvld + , data_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output data_wr_prdy; +input data_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input data_wr_pause; +`endif +input [8:0] data_wr_pd; +input data_rd_prdy; +output data_rd_pvld; +output [8:0] data_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg data_wr_busy_int; // copy for internal use +assign data_wr_prdy = !data_wr_busy_int; +assign wr_reserving = data_wr_pvld && !data_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [6:0] data_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? data_wr_count : (data_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (data_wr_count + 1'd1) : data_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire data_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check data_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || data_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire data_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check data_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_wr_busy_int <= 1'b0; + data_wr_count <= 7'd0; + end else begin + data_wr_busy_int <= data_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + data_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + data_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as data_wr_pvld +// +// RAM +// +reg [6:0] data_wr_adr; // current write address +wire [6:0] data_rd_adr_p; // read address to use for ram +wire [8:0] data_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_80x9 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( data_wr_adr ) + , .we ( wr_pushing && (data_wr_count != 7'd0 || !rd_popping) ) + , .di ( data_wr_pd ) + , .ra ( data_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( data_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( data_wr_pd[8:0] ) + , .ore ( ore ) + ); +// next data_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (data_wr_adr == 7'd79) ? 7'd0 : (data_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + data_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + data_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [6:0] data_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (data_rd_adr == 7'd79) ? 7'd0 : (data_rd_adr + 1'd1); // spyglass disable W484 +assign data_rd_adr_p = rd_popping ? rd_adr_next : data_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + data_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + data_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (data_wr_adr == rd_adr_next) : (data_wr_adr == data_rd_adr)); +wire [8:0] data_rd_pd_p_byp = data_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = data_wr_count == 0; +wire [8:0] data_rd_pd_p = data_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire data_rd_pvld_p; // data out of fifo is valid +reg data_rd_pvld_int; // internal copy of data_rd_pvld +assign data_rd_pvld = data_rd_pvld_int; +assign rd_popping = data_rd_pvld_p && !(data_rd_pvld_int && !data_rd_prdy); +reg [6:0] data_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? data_rd_count_p : + (data_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (data_rd_count_p + 1'd1) : + data_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign data_rd_pvld_p = data_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~data_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_rd_count_p <= 7'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + data_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + data_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (data_rd_pvld_p || (data_rd_pvld_int && !data_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + data_rd_pvld_int <= 1'b0; + end else begin + data_rd_pvld_int <= rd_req_next; + end +end +assign data_rd_pd = data_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (data_wr_pvld && !data_wr_busy_int) || (data_wr_busy_int != data_wr_busy_next)) || (rd_pushing || rd_popping || (data_rd_pvld_int && data_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_data_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_data_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_data_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( data_wr_pvld && !(!data_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, data_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_data_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_data_fifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_DP_sumpd_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus sumpd_wr -rd_pipebus sumpd_rd -rd_reg -ram_bypass -d 60 -w 21 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_DP_sumpd_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , sumpd_wr_prdy + , sumpd_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , sumpd_wr_pause +`endif + , sumpd_wr_pd + , sumpd_rd_prdy + , sumpd_rd_pvld + , sumpd_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output sumpd_wr_prdy; +input sumpd_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input sumpd_wr_pause; +`endif +input [20:0] sumpd_wr_pd; +input sumpd_rd_prdy; +output sumpd_rd_pvld; +output [20:0] sumpd_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg sumpd_wr_busy_int; // copy for internal use +assign sumpd_wr_prdy = !sumpd_wr_busy_int; +assign wr_reserving = sumpd_wr_pvld && !sumpd_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [5:0] sumpd_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? sumpd_wr_count : (sumpd_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (sumpd_wr_count + 1'd1) : sumpd_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_60 = ( wr_count_next_no_wr_popping == 6'd60 ); +wire wr_count_next_is_60 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_60; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire sumpd_wr_busy_next = wr_count_next_is_60 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check sumpd_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || sumpd_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire sumpd_wr_busy_next = wr_count_next_is_60 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check sumpd_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_wr_busy_int <= 1'b0; + sumpd_wr_count <= 6'd0; + end else begin + sumpd_wr_busy_int <= sumpd_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + sumpd_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + sumpd_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as sumpd_wr_pvld +// +// RAM +// +reg [5:0] sumpd_wr_adr; // current write address +wire [5:0] sumpd_rd_adr_p; // read address to use for ram +wire [20:0] sumpd_rd_pd_p_byp_ram; // read data directly out of ram +wire rd_enable; +wire ore; +wire do_bypass; +wire comb_bypass; +wire rd_popping; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsthp_60x21 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( sumpd_wr_adr ) + , .we ( wr_pushing && (sumpd_wr_count != 6'd0 || !rd_popping) ) + , .di ( sumpd_wr_pd ) + , .ra ( sumpd_rd_adr_p ) + , .re ( (do_bypass && wr_pushing) || rd_enable ) + , .dout ( sumpd_rd_pd_p_byp_ram ) + , .byp_sel ( comb_bypass ) + , .dbyp ( sumpd_wr_pd[20:0] ) + , .ore ( ore ) + ); +// next sumpd_wr_adr if wr_pushing=1 +wire [5:0] wr_adr_next = (sumpd_wr_adr == 6'd59) ? 6'd0 : (sumpd_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_wr_adr <= 6'd0; + end else begin + if ( wr_pushing ) begin + sumpd_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + sumpd_wr_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +reg [5:0] sumpd_rd_adr; // current read address +// next read address +wire [5:0] rd_adr_next = (sumpd_rd_adr == 6'd59) ? 6'd0 : (sumpd_rd_adr + 1'd1); // spyglass disable W484 +assign sumpd_rd_adr_p = rd_popping ? rd_adr_next : sumpd_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_rd_adr <= 6'd0; + end else begin + if ( rd_popping ) begin + sumpd_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + sumpd_rd_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +assign do_bypass = (rd_popping ? (sumpd_wr_adr == rd_adr_next) : (sumpd_wr_adr == sumpd_rd_adr)); +wire [20:0] sumpd_rd_pd_p_byp = sumpd_rd_pd_p_byp_ram; +// +// Combinatorial Bypass +// +// If we're pushing an empty fifo, mux the wr_data directly. +// +assign comb_bypass = sumpd_wr_count == 0; +wire [20:0] sumpd_rd_pd_p = sumpd_rd_pd_p_byp; +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire sumpd_rd_pvld_p; // data out of fifo is valid +reg sumpd_rd_pvld_int; // internal copy of sumpd_rd_pvld +assign sumpd_rd_pvld = sumpd_rd_pvld_int; +assign rd_popping = sumpd_rd_pvld_p && !(sumpd_rd_pvld_int && !sumpd_rd_prdy); +reg [5:0] sumpd_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? sumpd_rd_count_p : + (sumpd_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (sumpd_rd_count_p + 1'd1) : + sumpd_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign sumpd_rd_pvld_p = sumpd_rd_count_p != 0 || rd_pushing; +assign rd_enable = ((rd_count_p_next_not_0) && ((~sumpd_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_rd_count_p <= 6'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + sumpd_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + sumpd_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire rd_req_next = (sumpd_rd_pvld_p || (sumpd_rd_pvld_int && !sumpd_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + sumpd_rd_pvld_int <= 1'b0; + end else begin + sumpd_rd_pvld_int <= rd_req_next; + end +end +assign sumpd_rd_pd = sumpd_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (sumpd_wr_pvld && !sumpd_wr_busy_int) || (sumpd_wr_busy_int != sumpd_wr_busy_next)) || (rd_pushing || rd_popping || (sumpd_rd_pvld_int && sumpd_rd_prdy))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_DP_sumpd_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( sumpd_wr_pvld && !(!sumpd_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd60 : wr_limit_reg} ) + , .curr ( {26'd0, sumpd_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_DP_sumpd_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_DP_sumpd_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v new file mode 100644 index 0000000..3c027ac --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v @@ -0,0 +1,317 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_REG_dual.v +module NV_NVDLA_CDP_RDMA_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,channel + ,height + ,width + ,input_data + ,op_en_trigger + ,dma_en + ,src_base_addr_high + ,src_base_addr_low + ,src_ram_type + ,src_line_stride + ,src_surface_stride + ,op_en + ,perf_read_stall + ); +wire [31:0] nvdla_cdp_rdma_d_cya_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_cube_channel_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_cube_height_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_cube_width_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_format_0_out; +wire [31:0] nvdla_cdp_rdma_d_op_enable_0_out; +wire [31:0] nvdla_cdp_rdma_d_operation_mode_0_out; +wire [31:0] nvdla_cdp_rdma_d_perf_enable_0_out; +wire [31:0] nvdla_cdp_rdma_d_perf_read_stall_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_base_addr_high_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_base_addr_low_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_compression_en_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_dma_cfg_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_line_stride_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_surface_stride_0_out; +wire [1:0] operation_mode; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +wire src_compression_en; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [12:0] channel; +output [12:0] height; +output [12:0] width; +output [1:0] input_data; +output op_en_trigger; +output dma_en; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output src_ram_type; +output [31:0] src_line_stride; +output [31:0] src_surface_stride; +// Read-only register inputs +input op_en; +input [31:0] perf_read_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [12:0] channel; +reg [31:0] cya; +reg dma_en; +reg [12:0] height; +reg [1:0] input_data; +reg [31:0] reg_rd_data; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg src_ram_type; +reg [31:0] src_surface_stride; +reg [12:0] width; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_rdma_d_cya_0_wren = (reg_offset_wr == (32'he040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_cube_channel_0_wren = (reg_offset_wr == (32'he014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_cube_height_0_wren = (reg_offset_wr == (32'he010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_cube_width_0_wren = (reg_offset_wr == (32'he00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_format_0_wren = (reg_offset_wr == (32'he034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_operation_mode_0_wren = (reg_offset_wr == (32'he030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_op_enable_0_wren = (reg_offset_wr == (32'he008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_perf_enable_0_wren = (reg_offset_wr == (32'he038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_perf_read_stall_0_wren = (reg_offset_wr == (32'he03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'he01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'he018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_compression_en_0_wren = (reg_offset_wr == (32'he02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_dma_cfg_0_wren = (reg_offset_wr == (32'he028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_line_stride_0_wren = (reg_offset_wr == (32'he020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_surface_stride_0_wren = (reg_offset_wr == (32'he024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign operation_mode = 2'h0; +assign src_compression_en = 1'h0; +assign nvdla_cdp_rdma_d_cya_0_out[31:0] = { cya }; +assign nvdla_cdp_rdma_d_data_cube_channel_0_out[31:0] = { 19'b0, channel }; +assign nvdla_cdp_rdma_d_data_cube_height_0_out[31:0] = { 19'b0, height }; +assign nvdla_cdp_rdma_d_data_cube_width_0_out[31:0] = { 19'b0, width }; +assign nvdla_cdp_rdma_d_data_format_0_out[31:0] = { 30'b0, input_data }; +assign nvdla_cdp_rdma_d_operation_mode_0_out[31:0] = { 30'b0, operation_mode }; +assign nvdla_cdp_rdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cdp_rdma_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_cdp_rdma_d_perf_read_stall_0_out[31:0] = { perf_read_stall }; +assign nvdla_cdp_rdma_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_cdp_rdma_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low }; +assign nvdla_cdp_rdma_d_src_compression_en_0_out[31:0] = { 31'b0, src_compression_en }; +assign nvdla_cdp_rdma_d_src_dma_cfg_0_out[31:0] = { 31'b0, src_ram_type }; +assign nvdla_cdp_rdma_d_src_line_stride_0_out[31:0] = { src_line_stride }; +assign nvdla_cdp_rdma_d_src_surface_stride_0_out[31:0] = { src_surface_stride }; +assign op_en_trigger = nvdla_cdp_rdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_rdma_d_cya_0_out + or nvdla_cdp_rdma_d_data_cube_channel_0_out + or nvdla_cdp_rdma_d_data_cube_height_0_out + or nvdla_cdp_rdma_d_data_cube_width_0_out + or nvdla_cdp_rdma_d_data_format_0_out + or nvdla_cdp_rdma_d_operation_mode_0_out + or nvdla_cdp_rdma_d_op_enable_0_out + or nvdla_cdp_rdma_d_perf_enable_0_out + or nvdla_cdp_rdma_d_perf_read_stall_0_out + or nvdla_cdp_rdma_d_src_base_addr_high_0_out + or nvdla_cdp_rdma_d_src_base_addr_low_0_out + or nvdla_cdp_rdma_d_src_compression_en_0_out + or nvdla_cdp_rdma_d_src_dma_cfg_0_out + or nvdla_cdp_rdma_d_src_line_stride_0_out + or nvdla_cdp_rdma_d_src_surface_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'he040 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_cya_0_out ; + end + (32'he014 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_cube_channel_0_out ; + end + (32'he010 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_cube_height_0_out ; + end + (32'he00c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_cube_width_0_out ; + end + (32'he034 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_format_0_out ; + end + (32'he030 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_operation_mode_0_out ; + end + (32'he008 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_op_enable_0_out ; + end + (32'he038 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_perf_enable_0_out ; + end + (32'he03c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_perf_read_stall_0_out ; + end + (32'he01c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_base_addr_high_0_out ; + end + (32'he018 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_base_addr_low_0_out ; + end + (32'he02c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_compression_en_0_out ; + end + (32'he028 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_dma_cfg_0_out ; + end + (32'he020 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_line_stride_0_out ; + end + (32'he024 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_surface_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + channel[12:0] <= 13'b0000000000000; + height[12:0] <= 13'b0000000000000; + width[12:0] <= 13'b0000000000000; + input_data[1:0] <= 2'b00; + dma_en <= 1'b0; + src_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + src_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + src_ram_type <= 1'b0; + src_line_stride[31:0] <= 32'b00000000000000000000000000000000; + src_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + end else begin +// Register: NVDLA_CDP_RDMA_D_CYA_0 Field: cya + if (nvdla_cdp_rdma_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_CUBE_CHANNEL_0 Field: channel + if (nvdla_cdp_rdma_d_data_cube_channel_0_wren) begin + channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_CUBE_HEIGHT_0 Field: height + if (nvdla_cdp_rdma_d_data_cube_height_0_wren) begin + height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_CUBE_WIDTH_0 Field: width + if (nvdla_cdp_rdma_d_data_cube_width_0_wren) begin + width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_FORMAT_0 Field: input_data + if (nvdla_cdp_rdma_d_data_format_0_wren) begin + input_data[1:0] <= reg_wr_data[1:0]; + end +// Not generating flops for constant field NVDLA_CDP_RDMA_D_OPERATION_MODE_0::operation_mode +// Not generating flops for field NVDLA_CDP_RDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_CDP_RDMA_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_cdp_rdma_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_RDMA_D_PERF_READ_STALL_0::perf_read_stall +// Register: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_cdp_rdma_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_cdp_rdma_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for constant field NVDLA_CDP_RDMA_D_SRC_COMPRESSION_EN_0::src_compression_en +// Register: NVDLA_CDP_RDMA_D_SRC_DMA_CFG_0 Field: src_ram_type + if (nvdla_cdp_rdma_d_src_dma_cfg_0_wren) begin + src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_RDMA_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_cdp_rdma_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_RDMA_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_cdp_rdma_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'he040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_cya_0_out, nvdla_cdp_rdma_d_cya_0_out); + (32'he014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_CUBE_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_cube_channel_0_out, nvdla_cdp_rdma_d_data_cube_channel_0_out); + (32'he010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_CUBE_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_cube_height_0_out, nvdla_cdp_rdma_d_data_cube_height_0_out); + (32'he00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_CUBE_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_cube_width_0_out, nvdla_cdp_rdma_d_data_cube_width_0_out); + (32'he034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_format_0_out, nvdla_cdp_rdma_d_data_format_0_out); + (32'he030 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_D_OPERATION_MODE_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'he008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_op_enable_0_out, nvdla_cdp_rdma_d_op_enable_0_out); + (32'he038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_perf_enable_0_out, nvdla_cdp_rdma_d_perf_enable_0_out); + (32'he03c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_D_PERF_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'he01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_base_addr_high_0_out, nvdla_cdp_rdma_d_src_base_addr_high_0_out); + (32'he018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_base_addr_low_0_out, nvdla_cdp_rdma_d_src_base_addr_low_0_out); + (32'he02c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_D_SRC_COMPRESSION_EN_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'he028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_dma_cfg_0_out, nvdla_cdp_rdma_d_src_dma_cfg_0_out); + (32'he020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_line_stride_0_out, nvdla_cdp_rdma_d_src_line_stride_0_out); + (32'he024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_surface_stride_0_out, nvdla_cdp_rdma_d_src_surface_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_RDMA_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v.vcp new file mode 100644 index 0000000..3c027ac --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v.vcp @@ -0,0 +1,317 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_REG_dual.v +module NV_NVDLA_CDP_RDMA_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,channel + ,height + ,width + ,input_data + ,op_en_trigger + ,dma_en + ,src_base_addr_high + ,src_base_addr_low + ,src_ram_type + ,src_line_stride + ,src_surface_stride + ,op_en + ,perf_read_stall + ); +wire [31:0] nvdla_cdp_rdma_d_cya_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_cube_channel_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_cube_height_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_cube_width_0_out; +wire [31:0] nvdla_cdp_rdma_d_data_format_0_out; +wire [31:0] nvdla_cdp_rdma_d_op_enable_0_out; +wire [31:0] nvdla_cdp_rdma_d_operation_mode_0_out; +wire [31:0] nvdla_cdp_rdma_d_perf_enable_0_out; +wire [31:0] nvdla_cdp_rdma_d_perf_read_stall_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_base_addr_high_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_base_addr_low_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_compression_en_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_dma_cfg_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_line_stride_0_out; +wire [31:0] nvdla_cdp_rdma_d_src_surface_stride_0_out; +wire [1:0] operation_mode; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +wire src_compression_en; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [12:0] channel; +output [12:0] height; +output [12:0] width; +output [1:0] input_data; +output op_en_trigger; +output dma_en; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output src_ram_type; +output [31:0] src_line_stride; +output [31:0] src_surface_stride; +// Read-only register inputs +input op_en; +input [31:0] perf_read_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [12:0] channel; +reg [31:0] cya; +reg dma_en; +reg [12:0] height; +reg [1:0] input_data; +reg [31:0] reg_rd_data; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg src_ram_type; +reg [31:0] src_surface_stride; +reg [12:0] width; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_rdma_d_cya_0_wren = (reg_offset_wr == (32'he040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_cube_channel_0_wren = (reg_offset_wr == (32'he014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_cube_height_0_wren = (reg_offset_wr == (32'he010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_cube_width_0_wren = (reg_offset_wr == (32'he00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_data_format_0_wren = (reg_offset_wr == (32'he034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_operation_mode_0_wren = (reg_offset_wr == (32'he030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_op_enable_0_wren = (reg_offset_wr == (32'he008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_perf_enable_0_wren = (reg_offset_wr == (32'he038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_perf_read_stall_0_wren = (reg_offset_wr == (32'he03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'he01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'he018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_compression_en_0_wren = (reg_offset_wr == (32'he02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_dma_cfg_0_wren = (reg_offset_wr == (32'he028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_line_stride_0_wren = (reg_offset_wr == (32'he020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_d_src_surface_stride_0_wren = (reg_offset_wr == (32'he024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign operation_mode = 2'h0; +assign src_compression_en = 1'h0; +assign nvdla_cdp_rdma_d_cya_0_out[31:0] = { cya }; +assign nvdla_cdp_rdma_d_data_cube_channel_0_out[31:0] = { 19'b0, channel }; +assign nvdla_cdp_rdma_d_data_cube_height_0_out[31:0] = { 19'b0, height }; +assign nvdla_cdp_rdma_d_data_cube_width_0_out[31:0] = { 19'b0, width }; +assign nvdla_cdp_rdma_d_data_format_0_out[31:0] = { 30'b0, input_data }; +assign nvdla_cdp_rdma_d_operation_mode_0_out[31:0] = { 30'b0, operation_mode }; +assign nvdla_cdp_rdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cdp_rdma_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_cdp_rdma_d_perf_read_stall_0_out[31:0] = { perf_read_stall }; +assign nvdla_cdp_rdma_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_cdp_rdma_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low }; +assign nvdla_cdp_rdma_d_src_compression_en_0_out[31:0] = { 31'b0, src_compression_en }; +assign nvdla_cdp_rdma_d_src_dma_cfg_0_out[31:0] = { 31'b0, src_ram_type }; +assign nvdla_cdp_rdma_d_src_line_stride_0_out[31:0] = { src_line_stride }; +assign nvdla_cdp_rdma_d_src_surface_stride_0_out[31:0] = { src_surface_stride }; +assign op_en_trigger = nvdla_cdp_rdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_rdma_d_cya_0_out + or nvdla_cdp_rdma_d_data_cube_channel_0_out + or nvdla_cdp_rdma_d_data_cube_height_0_out + or nvdla_cdp_rdma_d_data_cube_width_0_out + or nvdla_cdp_rdma_d_data_format_0_out + or nvdla_cdp_rdma_d_operation_mode_0_out + or nvdla_cdp_rdma_d_op_enable_0_out + or nvdla_cdp_rdma_d_perf_enable_0_out + or nvdla_cdp_rdma_d_perf_read_stall_0_out + or nvdla_cdp_rdma_d_src_base_addr_high_0_out + or nvdla_cdp_rdma_d_src_base_addr_low_0_out + or nvdla_cdp_rdma_d_src_compression_en_0_out + or nvdla_cdp_rdma_d_src_dma_cfg_0_out + or nvdla_cdp_rdma_d_src_line_stride_0_out + or nvdla_cdp_rdma_d_src_surface_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'he040 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_cya_0_out ; + end + (32'he014 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_cube_channel_0_out ; + end + (32'he010 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_cube_height_0_out ; + end + (32'he00c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_cube_width_0_out ; + end + (32'he034 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_data_format_0_out ; + end + (32'he030 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_operation_mode_0_out ; + end + (32'he008 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_op_enable_0_out ; + end + (32'he038 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_perf_enable_0_out ; + end + (32'he03c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_perf_read_stall_0_out ; + end + (32'he01c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_base_addr_high_0_out ; + end + (32'he018 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_base_addr_low_0_out ; + end + (32'he02c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_compression_en_0_out ; + end + (32'he028 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_dma_cfg_0_out ; + end + (32'he020 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_line_stride_0_out ; + end + (32'he024 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_d_src_surface_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + channel[12:0] <= 13'b0000000000000; + height[12:0] <= 13'b0000000000000; + width[12:0] <= 13'b0000000000000; + input_data[1:0] <= 2'b00; + dma_en <= 1'b0; + src_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + src_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + src_ram_type <= 1'b0; + src_line_stride[31:0] <= 32'b00000000000000000000000000000000; + src_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + end else begin +// Register: NVDLA_CDP_RDMA_D_CYA_0 Field: cya + if (nvdla_cdp_rdma_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_CUBE_CHANNEL_0 Field: channel + if (nvdla_cdp_rdma_d_data_cube_channel_0_wren) begin + channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_CUBE_HEIGHT_0 Field: height + if (nvdla_cdp_rdma_d_data_cube_height_0_wren) begin + height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_CUBE_WIDTH_0 Field: width + if (nvdla_cdp_rdma_d_data_cube_width_0_wren) begin + width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CDP_RDMA_D_DATA_FORMAT_0 Field: input_data + if (nvdla_cdp_rdma_d_data_format_0_wren) begin + input_data[1:0] <= reg_wr_data[1:0]; + end +// Not generating flops for constant field NVDLA_CDP_RDMA_D_OPERATION_MODE_0::operation_mode +// Not generating flops for field NVDLA_CDP_RDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_CDP_RDMA_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_cdp_rdma_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_RDMA_D_PERF_READ_STALL_0::perf_read_stall +// Register: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_cdp_rdma_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_cdp_rdma_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for constant field NVDLA_CDP_RDMA_D_SRC_COMPRESSION_EN_0::src_compression_en +// Register: NVDLA_CDP_RDMA_D_SRC_DMA_CFG_0 Field: src_ram_type + if (nvdla_cdp_rdma_d_src_dma_cfg_0_wren) begin + src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_RDMA_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_cdp_rdma_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_RDMA_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_cdp_rdma_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'he040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_cya_0_out, nvdla_cdp_rdma_d_cya_0_out); + (32'he014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_CUBE_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_cube_channel_0_out, nvdla_cdp_rdma_d_data_cube_channel_0_out); + (32'he010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_CUBE_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_cube_height_0_out, nvdla_cdp_rdma_d_data_cube_height_0_out); + (32'he00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_CUBE_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_cube_width_0_out, nvdla_cdp_rdma_d_data_cube_width_0_out); + (32'he034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_data_format_0_out, nvdla_cdp_rdma_d_data_format_0_out); + (32'he030 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_D_OPERATION_MODE_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'he008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_op_enable_0_out, nvdla_cdp_rdma_d_op_enable_0_out); + (32'he038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_perf_enable_0_out, nvdla_cdp_rdma_d_perf_enable_0_out); + (32'he03c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_D_PERF_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'he01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_base_addr_high_0_out, nvdla_cdp_rdma_d_src_base_addr_high_0_out); + (32'he018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_base_addr_low_0_out, nvdla_cdp_rdma_d_src_base_addr_low_0_out); + (32'he02c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_D_SRC_COMPRESSION_EN_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'he028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_dma_cfg_0_out, nvdla_cdp_rdma_d_src_dma_cfg_0_out); + (32'he020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_line_stride_0_out, nvdla_cdp_rdma_d_src_line_stride_0_out); + (32'he024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_d_src_surface_stride_0_out, nvdla_cdp_rdma_d_src_surface_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_RDMA_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v new file mode 100644 index 0000000..12252b5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_REG_single.v +module NV_NVDLA_CDP_RDMA_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cdp_rdma_s_pointer_0_out; +wire [31:0] nvdla_cdp_rdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_rdma_s_pointer_0_wren = (reg_offset_wr == (32'he004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_s_status_0_wren = (reg_offset_wr == (32'he000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdp_rdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cdp_rdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_rdma_s_pointer_0_out + or nvdla_cdp_rdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'he004 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_s_pointer_0_out ; + end + (32'he000 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CDP_RDMA_S_POINTER_0::consumer +// Register: NVDLA_CDP_RDMA_S_POINTER_0 Field: producer + if (nvdla_cdp_rdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_RDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CDP_RDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'he004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_s_pointer_0_out, nvdla_cdp_rdma_s_pointer_0_out); + (32'he000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_RDMA_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v.vcp new file mode 100644 index 0000000..12252b5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_REG_single.v +module NV_NVDLA_CDP_RDMA_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cdp_rdma_s_pointer_0_out; +wire [31:0] nvdla_cdp_rdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_rdma_s_pointer_0_wren = (reg_offset_wr == (32'he004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_rdma_s_status_0_wren = (reg_offset_wr == (32'he000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdp_rdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cdp_rdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_rdma_s_pointer_0_out + or nvdla_cdp_rdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'he004 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_s_pointer_0_out ; + end + (32'he000 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_rdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CDP_RDMA_S_POINTER_0::consumer +// Register: NVDLA_CDP_RDMA_S_POINTER_0 Field: producer + if (nvdla_cdp_rdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_RDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CDP_RDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'he004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_RDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_rdma_s_pointer_0_out, nvdla_cdp_rdma_s_pointer_0_out); + (32'he000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_RDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_RDMA_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v new file mode 100644 index 0000000..2f70ad0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v @@ -0,0 +1,690 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , cq_wr_prdy + , cq_wr_pvld + , cq_wr_pd + , cq_rd_prdy + , cq_rd_pvld + , cq_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cq_wr_prdy; +input cq_wr_pvld; +input [6:0] cq_wr_pd; +input cq_rd_prdy; +output cq_rd_pvld; +output [6:0] cq_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg cq_wr_busy_int; // copy for internal use +assign cq_wr_prdy = !cq_wr_busy_int; +assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] cq_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_32 = ( wr_count_next_no_wr_popping == 6'd32 ); +wire wr_count_next_is_32 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_32; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_32 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_busy_int <= 1'b0; + cq_wr_count <= 6'd0; + end else begin + cq_wr_busy_int <= cq_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + cq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + cq_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as cq_wr_pvld +// +// RAM +// +reg [4:0] cq_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + cq_wr_adr <= cq_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [4:0] cq_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [6:0] cq_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( cq_wr_pd ) + , .we ( ram_we ) + , .wa ( cq_wr_adr ) + , .ra ( cq_rd_adr ) + , .dout ( cq_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [4:0] rd_adr_next_popping = cq_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + cq_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg cq_rd_pvld_p; // data out of fifo is valid +reg cq_rd_pvld_int; // internal copy of cq_rd_pvld +assign cq_rd_pvld = cq_rd_pvld_int; +assign rd_popping = cq_rd_pvld_p && !(cq_rd_pvld_int && !cq_rd_prdy); +reg [5:0] cq_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? cq_rd_count_p : + (cq_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq_rd_count_p + 1'd1) : + cq_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_count_p <= 6'd0; + cq_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [6:0] cq_rd_pd; // output data register +wire rd_req_next = (cq_rd_pvld_p || (cq_rd_pvld_int && !cq_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_pvld_int <= 1'b0; + end else begin + cq_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + cq_rd_pd <= cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + cq_rd_pd <= {7{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next)) || (rd_pushing || rd_popping || (cq_rd_pvld_int && cq_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_cq_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_RDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd32 : wr_limit_reg} ) + , .curr ( {26'd0, cq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDP_RDMA_cq +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [6:0] di; +input we; +input [4:0] wa; +input [4:0] ra; +output [6:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [4:0] Wa0_vmw; +reg we0_vmw; +reg [6:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [6:0] ram_ff0; +reg [6:0] ram_ff1; +reg [6:0] ram_ff2; +reg [6:0] ram_ff3; +reg [6:0] ram_ff4; +reg [6:0] ram_ff5; +reg [6:0] ram_ff6; +reg [6:0] ram_ff7; +reg [6:0] ram_ff8; +reg [6:0] ram_ff9; +reg [6:0] ram_ff10; +reg [6:0] ram_ff11; +reg [6:0] ram_ff12; +reg [6:0] ram_ff13; +reg [6:0] ram_ff14; +reg [6:0] ram_ff15; +reg [6:0] ram_ff16; +reg [6:0] ram_ff17; +reg [6:0] ram_ff18; +reg [6:0] ram_ff19; +reg [6:0] ram_ff20; +reg [6:0] ram_ff21; +reg [6:0] ram_ff22; +reg [6:0] ram_ff23; +reg [6:0] ram_ff24; +reg [6:0] ram_ff25; +reg [6:0] ram_ff26; +reg [6:0] ram_ff27; +reg [6:0] ram_ff28; +reg [6:0] ram_ff29; +reg [6:0] ram_ff30; +reg [6:0] ram_ff31; +always @( posedge clk ) begin + if ( we && wa == 5'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 5'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 5'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 5'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 5'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 5'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 5'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 5'd7 ) begin + ram_ff7 <= di; + end + if ( we && wa == 5'd8 ) begin + ram_ff8 <= di; + end + if ( we && wa == 5'd9 ) begin + ram_ff9 <= di; + end + if ( we && wa == 5'd10 ) begin + ram_ff10 <= di; + end + if ( we && wa == 5'd11 ) begin + ram_ff11 <= di; + end + if ( we && wa == 5'd12 ) begin + ram_ff12 <= di; + end + if ( we && wa == 5'd13 ) begin + ram_ff13 <= di; + end + if ( we && wa == 5'd14 ) begin + ram_ff14 <= di; + end + if ( we && wa == 5'd15 ) begin + ram_ff15 <= di; + end + if ( we && wa == 5'd16 ) begin + ram_ff16 <= di; + end + if ( we && wa == 5'd17 ) begin + ram_ff17 <= di; + end + if ( we && wa == 5'd18 ) begin + ram_ff18 <= di; + end + if ( we && wa == 5'd19 ) begin + ram_ff19 <= di; + end + if ( we && wa == 5'd20 ) begin + ram_ff20 <= di; + end + if ( we && wa == 5'd21 ) begin + ram_ff21 <= di; + end + if ( we && wa == 5'd22 ) begin + ram_ff22 <= di; + end + if ( we && wa == 5'd23 ) begin + ram_ff23 <= di; + end + if ( we && wa == 5'd24 ) begin + ram_ff24 <= di; + end + if ( we && wa == 5'd25 ) begin + ram_ff25 <= di; + end + if ( we && wa == 5'd26 ) begin + ram_ff26 <= di; + end + if ( we && wa == 5'd27 ) begin + ram_ff27 <= di; + end + if ( we && wa == 5'd28 ) begin + ram_ff28 <= di; + end + if ( we && wa == 5'd29 ) begin + ram_ff29 <= di; + end + if ( we && wa == 5'd30 ) begin + ram_ff30 <= di; + end + if ( we && wa == 5'd31 ) begin + ram_ff31 <= di; + end +end +reg [6:0] dout; +always @(*) begin + case( ra ) + 5'd0: dout = ram_ff0; + 5'd1: dout = ram_ff1; + 5'd2: dout = ram_ff2; + 5'd3: dout = ram_ff3; + 5'd4: dout = ram_ff4; + 5'd5: dout = ram_ff5; + 5'd6: dout = ram_ff6; + 5'd7: dout = ram_ff7; + 5'd8: dout = ram_ff8; + 5'd9: dout = ram_ff9; + 5'd10: dout = ram_ff10; + 5'd11: dout = ram_ff11; + 5'd12: dout = ram_ff12; + 5'd13: dout = ram_ff13; + 5'd14: dout = ram_ff14; + 5'd15: dout = ram_ff15; + 5'd16: dout = ram_ff16; + 5'd17: dout = ram_ff17; + 5'd18: dout = ram_ff18; + 5'd19: dout = ram_ff19; + 5'd20: dout = ram_ff20; + 5'd21: dout = ram_ff21; + 5'd22: dout = ram_ff22; + 5'd23: dout = ram_ff23; + 5'd24: dout = ram_ff24; + 5'd25: dout = ram_ff25; + 5'd26: dout = ram_ff26; + 5'd27: dout = ram_ff27; + 5'd28: dout = ram_ff28; + 5'd29: dout = ram_ff29; + 5'd30: dout = ram_ff30; + 5'd31: dout = ram_ff31; +//VCS coverage off + default: dout = {7{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [4:0] Wa0; +input we0; +input [6:0] Di0; +input [4:0] Ra0; +output [6:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 7'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [6:0] mem[31:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [6:0] Q0 = mem[0]; +wire [6:0] Q1 = mem[1]; +wire [6:0] Q2 = mem[2]; +wire [6:0] Q3 = mem[3]; +wire [6:0] Q4 = mem[4]; +wire [6:0] Q5 = mem[5]; +wire [6:0] Q6 = mem[6]; +wire [6:0] Q7 = mem[7]; +wire [6:0] Q8 = mem[8]; +wire [6:0] Q9 = mem[9]; +wire [6:0] Q10 = mem[10]; +wire [6:0] Q11 = mem[11]; +wire [6:0] Q12 = mem[12]; +wire [6:0] Q13 = mem[13]; +wire [6:0] Q14 = mem[14]; +wire [6:0] Q15 = mem[15]; +wire [6:0] Q16 = mem[16]; +wire [6:0] Q17 = mem[17]; +wire [6:0] Q18 = mem[18]; +wire [6:0] Q19 = mem[19]; +wire [6:0] Q20 = mem[20]; +wire [6:0] Q21 = mem[21]; +wire [6:0] Q22 = mem[22]; +wire [6:0] Q23 = mem[23]; +wire [6:0] Q24 = mem[24]; +wire [6:0] Q25 = mem[25]; +wire [6:0] Q26 = mem[26]; +wire [6:0] Q27 = mem[27]; +wire [6:0] Q28 = mem[28]; +wire [6:0] Q29 = mem[29]; +wire [6:0] Q30 = mem[30]; +wire [6:0] Q31 = mem[31]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7] } +endmodule // vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +//vmw: Memory vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +//vmw: Address-size 5 +//vmw: Data-size 7 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[6:0] data0[6:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[6:0] data1[6:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v.vcp new file mode 100644 index 0000000..2f70ad0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v.vcp @@ -0,0 +1,690 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , cq_wr_prdy + , cq_wr_pvld + , cq_wr_pd + , cq_rd_prdy + , cq_rd_pvld + , cq_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cq_wr_prdy; +input cq_wr_pvld; +input [6:0] cq_wr_pd; +input cq_rd_prdy; +output cq_rd_pvld; +output [6:0] cq_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg cq_wr_busy_int; // copy for internal use +assign cq_wr_prdy = !cq_wr_busy_int; +assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] cq_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_32 = ( wr_count_next_no_wr_popping == 6'd32 ); +wire wr_count_next_is_32 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_32; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_32 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_busy_int <= 1'b0; + cq_wr_count <= 6'd0; + end else begin + cq_wr_busy_int <= cq_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + cq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + cq_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as cq_wr_pvld +// +// RAM +// +reg [4:0] cq_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_adr <= 5'd0; + end else begin + if ( wr_pushing ) begin + cq_wr_adr <= cq_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [4:0] cq_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [6:0] cq_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( cq_wr_pd ) + , .we ( ram_we ) + , .wa ( cq_wr_adr ) + , .ra ( cq_rd_adr ) + , .dout ( cq_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [4:0] rd_adr_next_popping = cq_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_adr <= 5'd0; + end else begin + if ( rd_popping ) begin + cq_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq_rd_adr <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg cq_rd_pvld_p; // data out of fifo is valid +reg cq_rd_pvld_int; // internal copy of cq_rd_pvld +assign cq_rd_pvld = cq_rd_pvld_int; +assign rd_popping = cq_rd_pvld_p && !(cq_rd_pvld_int && !cq_rd_prdy); +reg [5:0] cq_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? cq_rd_count_p : + (cq_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq_rd_count_p + 1'd1) : + cq_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_count_p <= 6'd0; + cq_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [6:0] cq_rd_pd; // output data register +wire rd_req_next = (cq_rd_pvld_p || (cq_rd_pvld_int && !cq_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_pvld_int <= 1'b0; + end else begin + cq_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + cq_rd_pd <= cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + cq_rd_pd <= {7{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next)) || (rd_pushing || rd_popping || (cq_rd_pvld_int && cq_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_cq_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_RDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd32 : wr_limit_reg} ) + , .curr ( {26'd0, cq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDP_RDMA_cq +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [6:0] di; +input we; +input [4:0] wa; +input [4:0] ra; +output [6:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [4:0] Wa0_vmw; +reg we0_vmw; +reg [6:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [6:0] ram_ff0; +reg [6:0] ram_ff1; +reg [6:0] ram_ff2; +reg [6:0] ram_ff3; +reg [6:0] ram_ff4; +reg [6:0] ram_ff5; +reg [6:0] ram_ff6; +reg [6:0] ram_ff7; +reg [6:0] ram_ff8; +reg [6:0] ram_ff9; +reg [6:0] ram_ff10; +reg [6:0] ram_ff11; +reg [6:0] ram_ff12; +reg [6:0] ram_ff13; +reg [6:0] ram_ff14; +reg [6:0] ram_ff15; +reg [6:0] ram_ff16; +reg [6:0] ram_ff17; +reg [6:0] ram_ff18; +reg [6:0] ram_ff19; +reg [6:0] ram_ff20; +reg [6:0] ram_ff21; +reg [6:0] ram_ff22; +reg [6:0] ram_ff23; +reg [6:0] ram_ff24; +reg [6:0] ram_ff25; +reg [6:0] ram_ff26; +reg [6:0] ram_ff27; +reg [6:0] ram_ff28; +reg [6:0] ram_ff29; +reg [6:0] ram_ff30; +reg [6:0] ram_ff31; +always @( posedge clk ) begin + if ( we && wa == 5'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 5'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 5'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 5'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 5'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 5'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 5'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 5'd7 ) begin + ram_ff7 <= di; + end + if ( we && wa == 5'd8 ) begin + ram_ff8 <= di; + end + if ( we && wa == 5'd9 ) begin + ram_ff9 <= di; + end + if ( we && wa == 5'd10 ) begin + ram_ff10 <= di; + end + if ( we && wa == 5'd11 ) begin + ram_ff11 <= di; + end + if ( we && wa == 5'd12 ) begin + ram_ff12 <= di; + end + if ( we && wa == 5'd13 ) begin + ram_ff13 <= di; + end + if ( we && wa == 5'd14 ) begin + ram_ff14 <= di; + end + if ( we && wa == 5'd15 ) begin + ram_ff15 <= di; + end + if ( we && wa == 5'd16 ) begin + ram_ff16 <= di; + end + if ( we && wa == 5'd17 ) begin + ram_ff17 <= di; + end + if ( we && wa == 5'd18 ) begin + ram_ff18 <= di; + end + if ( we && wa == 5'd19 ) begin + ram_ff19 <= di; + end + if ( we && wa == 5'd20 ) begin + ram_ff20 <= di; + end + if ( we && wa == 5'd21 ) begin + ram_ff21 <= di; + end + if ( we && wa == 5'd22 ) begin + ram_ff22 <= di; + end + if ( we && wa == 5'd23 ) begin + ram_ff23 <= di; + end + if ( we && wa == 5'd24 ) begin + ram_ff24 <= di; + end + if ( we && wa == 5'd25 ) begin + ram_ff25 <= di; + end + if ( we && wa == 5'd26 ) begin + ram_ff26 <= di; + end + if ( we && wa == 5'd27 ) begin + ram_ff27 <= di; + end + if ( we && wa == 5'd28 ) begin + ram_ff28 <= di; + end + if ( we && wa == 5'd29 ) begin + ram_ff29 <= di; + end + if ( we && wa == 5'd30 ) begin + ram_ff30 <= di; + end + if ( we && wa == 5'd31 ) begin + ram_ff31 <= di; + end +end +reg [6:0] dout; +always @(*) begin + case( ra ) + 5'd0: dout = ram_ff0; + 5'd1: dout = ram_ff1; + 5'd2: dout = ram_ff2; + 5'd3: dout = ram_ff3; + 5'd4: dout = ram_ff4; + 5'd5: dout = ram_ff5; + 5'd6: dout = ram_ff6; + 5'd7: dout = ram_ff7; + 5'd8: dout = ram_ff8; + 5'd9: dout = ram_ff9; + 5'd10: dout = ram_ff10; + 5'd11: dout = ram_ff11; + 5'd12: dout = ram_ff12; + 5'd13: dout = ram_ff13; + 5'd14: dout = ram_ff14; + 5'd15: dout = ram_ff15; + 5'd16: dout = ram_ff16; + 5'd17: dout = ram_ff17; + 5'd18: dout = ram_ff18; + 5'd19: dout = ram_ff19; + 5'd20: dout = ram_ff20; + 5'd21: dout = ram_ff21; + 5'd22: dout = ram_ff22; + 5'd23: dout = ram_ff23; + 5'd24: dout = ram_ff24; + 5'd25: dout = ram_ff25; + 5'd26: dout = ram_ff26; + 5'd27: dout = ram_ff27; + 5'd28: dout = ram_ff28; + 5'd29: dout = ram_ff29; + 5'd30: dout = ram_ff30; + 5'd31: dout = ram_ff31; +//VCS coverage off + default: dout = {7{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [4:0] Wa0; +input we0; +input [6:0] Di0; +input [4:0] Ra0; +output [6:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 7'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [6:0] mem[31:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [6:0] Q0 = mem[0]; +wire [6:0] Q1 = mem[1]; +wire [6:0] Q2 = mem[2]; +wire [6:0] Q3 = mem[3]; +wire [6:0] Q4 = mem[4]; +wire [6:0] Q5 = mem[5]; +wire [6:0] Q6 = mem[6]; +wire [6:0] Q7 = mem[7]; +wire [6:0] Q8 = mem[8]; +wire [6:0] Q9 = mem[9]; +wire [6:0] Q10 = mem[10]; +wire [6:0] Q11 = mem[11]; +wire [6:0] Q12 = mem[12]; +wire [6:0] Q13 = mem[13]; +wire [6:0] Q14 = mem[14]; +wire [6:0] Q15 = mem[15]; +wire [6:0] Q16 = mem[16]; +wire [6:0] Q17 = mem[17]; +wire [6:0] Q18 = mem[18]; +wire [6:0] Q19 = mem[19]; +wire [6:0] Q20 = mem[20]; +wire [6:0] Q21 = mem[21]; +wire [6:0] Q22 = mem[22]; +wire [6:0] Q23 = mem[23]; +wire [6:0] Q24 = mem[24]; +wire [6:0] Q25 = mem[25]; +wire [6:0] Q26 = mem[26]; +wire [6:0] Q27 = mem[27]; +wire [6:0] Q28 = mem[28]; +wire [6:0] Q29 = mem[29]; +wire [6:0] Q30 = mem[30]; +wire [6:0] Q31 = mem[31]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7] } +endmodule // vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +//vmw: Memory vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +//vmw: Address-size 5 +//vmw: Data-size 7 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[6:0] data0[6:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[6:0] data1[6:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_32x7 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v new file mode 100644 index 0000000..257d456 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v @@ -0,0 +1,2205 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp_rdma2dp_ready //|< i + ,cq_rd_pd //|< i + ,cq_rd_pvld //|< i + ,mcif2cdp_rd_rsp_pd //|< i + ,mcif2cdp_rd_rsp_valid //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_channel //|< i + ,reg2dp_input_data //|< i + ,reg2dp_src_ram_type //|< i + ,cdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,cdp_rdma2dp_pd //|> o + ,cdp_rdma2dp_valid //|> o + ,cq_rd_prdy //|> o + ,dp2reg_done //|> o + ,eg2ig_done //|> o + ,mcif2cdp_rd_rsp_ready //|> o + ); +///////////////////////////////////////////////////////////////////////////////////////// +input [4:0] reg2dp_channel; +input [1:0] reg2dp_input_data; +input reg2dp_src_ram_type; +output dp2reg_done; +output eg2ig_done; +input nvdla_core_clk; +input nvdla_core_rstn; +input mcif2cdp_rd_rsp_valid; /* data valid */ +output mcif2cdp_rd_rsp_ready; /* data return handshake */ +//: my $k=64; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: print "input [${k}+${M}-1:0] mcif2cdp_rd_rsp_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [64+1-1:0] mcif2cdp_rd_rsp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output cdp2mcif_rd_cdt_lat_fifo_pop; +output cdp_rdma2dp_valid; /* data valid */ +input cdp_rdma2dp_ready; /* data return handshake */ +output [1*8 +22:0] cdp_rdma2dp_pd; +input cq_rd_pvld; /* data valid */ +output cq_rd_prdy; /* data return handshake */ +input [6:0] cq_rd_pd; +input [31:0] pwrbus_ram_pd; +///////////////////////////////////////////////////////////////////////////////////////// +//: my $Mnum = 64/8/8; +//: my $Mnumbit= int( log($Mnum)/log(2) ); +//: if($Mnum > 1){ +//: print " reg [${Mnumbit}-1:0] beat_align; \n"; +//: } else{ +//: print " reg beat_align; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + reg beat_align; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [3:0] beat_cnt; +reg cdp2mcif_rd_cdt_lat_fifo_pop; +wire [1*8 +22:0] cdp_rdma2dp_pd; +//reg cdp_rdma2dp_valid_f; +wire dp2reg_done_flag; +reg [1*8 -1:0] dp_data; +wire dp_rdy; +reg dp_vld; +wire eg2ig_done_flag; +reg [1 -1:0] invalid_flag; +reg is_last_c; +reg is_last_h; +reg is_last_w; +reg [3:0] tran_cnt; +reg [3:0] width_cnt; +wire [4:0] ele_in_channel; +wire cv_dma_rd_rsp_vld; +wire cv_int_rd_rsp_ready; +wire cv_int_rd_rsp_valid; +wire dma_rd_cdt_lat_fifo_pop; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_type; +wire dma_rd_rsp_vld; +wire dp2reg_done_f; +wire dp_b_sync; +wire [7:0] dp_invalid; +wire dp_last_c; +wire dp_last_h; +wire dp_last_w; +wire [1*8 +22:0] dp_pd; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire [3:0] dp_width; +wire eg2ig_done_f; +wire [7:0] fifo_rd_pvld; +wire [5:0] fifo_sel; +wire ig2eg_align; +wire ig2eg_last_c; +wire ig2eg_last_h; +wire ig2eg_last_w; +wire [2:0] ig2eg_width; +wire is_b_sync; +wire is_cube_end; +wire is_last_beat; +wire is_last_tran; +//: my $k=64; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: print "wire [${k}+${M}-1:0] cv_dma_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] cv_int_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] cvif2cdp_rd_rsp_pd_d0; \n"; +//: print "wire [${k}+${M}-1:0] dma_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] lat_rd_pd; \n"; +//: print "wire [${k}+${M}-1:0] mc_dma_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] mc_int_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] mcif2cdp_rd_rsp_pd_d0; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [64+1-1:0] cv_dma_rd_rsp_pd; +wire [64+1-1:0] cv_int_rd_rsp_pd; +wire [64+1-1:0] cvif2cdp_rd_rsp_pd_d0; +wire [64+1-1:0] dma_rd_rsp_pd; +wire [64+1-1:0] lat_rd_pd; +wire [64+1-1:0] mc_dma_rd_rsp_pd; +wire [64+1-1:0] mc_int_rd_rsp_pd; +wire [64+1-1:0] mcif2cdp_rd_rsp_pd_d0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [64 -1:0] lat_rd_data; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: print "wire [${M}-1:0] lat_rd_mask; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [1-1:0] lat_rd_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire lat_rd_prdy; +wire lat_rd_pvld; +wire mc_dma_rd_rsp_vld; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire mcif2cdp_rd_rsp_ready_d0; +wire mcif2cdp_rd_rsp_valid_d0; +wire [5:0] rest_channel; +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${kx}-1:0] ro${m}_rd_pd; +//: wire ro${m}_rd_prdy; +//: wire ro${m}_rd_pvld; +//: wire [${kx}-1:0] ro${m}_wr_pd; +//: ); +//: } +//: foreach my $m (0..$M-1) { +//: print qq( +//: wire ro${m}_wr_pvld; +//: wire ro${m}_wr_rdy; +//: ); +//: } +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire [${F}-1:0] ro${i}_wr_rdys; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8-1:0] ro0_rd_pd; +wire ro0_rd_prdy; +wire ro0_rd_pvld; +wire [8-1:0] ro0_wr_pd; + +wire [8-1:0] ro1_rd_pd; +wire ro1_rd_prdy; +wire ro1_rd_pvld; +wire [8-1:0] ro1_wr_pd; + +wire [8-1:0] ro2_rd_pd; +wire ro2_rd_prdy; +wire ro2_rd_pvld; +wire [8-1:0] ro2_wr_pd; + +wire [8-1:0] ro3_rd_pd; +wire ro3_rd_prdy; +wire ro3_rd_pvld; +wire [8-1:0] ro3_wr_pd; + +wire [8-1:0] ro4_rd_pd; +wire ro4_rd_prdy; +wire ro4_rd_pvld; +wire [8-1:0] ro4_wr_pd; + +wire [8-1:0] ro5_rd_pd; +wire ro5_rd_prdy; +wire ro5_rd_pvld; +wire [8-1:0] ro5_wr_pd; + +wire [8-1:0] ro6_rd_pd; +wire ro6_rd_prdy; +wire ro6_rd_pvld; +wire [8-1:0] ro6_wr_pd; + +wire [8-1:0] ro7_rd_pd; +wire ro7_rd_prdy; +wire ro7_rd_pvld; +wire [8-1:0] ro7_wr_pd; + +wire ro0_wr_pvld; +wire ro0_wr_rdy; + +wire [8-1:0] ro0_wr_rdys; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire tran_cnt_idle; +wire [3:0] tran_num; +wire tran_rdy; +wire tran_vld; +/////////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2cdp_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2cdp_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2cdp_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + cdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_type == 1'b1); + end +end +assign dma_rd_rsp_type = reg2dp_src_ram_type; +//============== +// Latency FIFO to buffer return DATA +//============== +NV_NVDLA_CDP_RDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lat_wr_prdy (dma_rd_rsp_rdy) //|> w + ,.lat_wr_pvld (dma_rd_rsp_vld) //|< w + ,.lat_wr_pd (dma_rd_rsp_pd) //|< w + ,.lat_rd_prdy (lat_rd_prdy) //|< w + ,.lat_rd_pvld (lat_rd_pvld) //|> w + ,.lat_rd_pd (lat_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign lat_rd_data[64 -1:0] = lat_rd_pd[64 -1:0]; +assign lat_rd_mask[1 -1:0] = lat_rd_pd[65 -1: 64]; +assign dma_rd_cdt_lat_fifo_pop = lat_rd_pvld & lat_rd_prdy; +//============== +// Re-Order FIFO to send data to CDP-core in DP order(read NVDLA PP uARCH for details) +//============== +assign lat_rd_prdy = lat_rd_pvld +//: my $msk = 1; +//: foreach my $k (0..$msk-1) { +//: print " & (~lat_rd_mask[$k] | (lat_rd_mask[$k] & ro${k}_wr_rdy)) \n"; +//: } +//: print " ; \n"; +//: +//: my $tp = 1*8; ## throughput +//: my $atmm = 8*8; ## atomic_m +//: my $M = 64/$atmm; ## atomic_m number per dma transaction +//: my $F = $atmm/$tp; ## how many fifo contribute to one atomic_m +//: +//: +//: foreach my $i (0..$M-1){ +//: print " assign ro${i}_wr_pvld = lat_rd_pvld & (lat_rd_mask[${i}] & ro${i}_wr_rdy) \n"; +//: foreach my $s (0..$msk-1) { +//: if($s != $i) { +//: print " & ( ~lat_rd_mask[${s}] | (lat_rd_mask[${s}] & ro${s}_wr_rdy)) \n"; +//: } +//: } +//: print " ; \n"; +//: } +//: +//: +//: foreach my $m (0..$M-1) { +//: print " assign ro${m}_wr_rdy = &ro${m}_wr_rdys; \n"; +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_wr_pd = lat_rd_data[${tp}*${r}+${tp}-1:${tp}*${r}]; \n"; +//: print " NV_NVDLA_CDP_RDMA_ro_fifo u_ro${r}_fifo( \n"; +//: print " .nvdla_core_clk (nvdla_core_clk) \n"; +//: print " ,.nvdla_core_rstn (nvdla_core_rstn) \n"; +//: print " ,.ro_wr_prdy (ro${m}_wr_rdys[$f]) \n"; +//: print " ,.ro_wr_pvld (ro${m}_wr_pvld) \n"; +//: print " ,.ro_wr_pd (ro${r}_wr_pd) \n"; +//: print " ,.ro_rd_prdy (ro${r}_rd_prdy) \n"; +//: print " ,.ro_rd_pvld (ro${r}_rd_pvld) \n"; +//: print " ,.ro_rd_pd (ro${r}_rd_pd) \n"; +//: print " ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) \n"; +//: print " ); \n"; +//: } +//: } +//: +//: +//: my $Fbit = int( log($F)/log(2) ); +//: if($M > 1) { +//: print " assign fifo_sel[5:0] = tran_cnt_idle ? 6'd0 : ((6'd${F}-tran_cnt) + {beat_align,{${Fbit}{1'b0}}}); \n"; +//: } else { +//: print " assign fifo_sel[5:0] = tran_cnt_idle ? 6'd0 : ((6'd${F}-tran_cnt)); \n"; +//: } +//: +//: +//: print " // DATA MUX out \n"; +//: print " always @(*) begin \n"; +//: print " case(fifo_sel) \n"; +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " 6'd$r: begin \n"; +//: print " dp_vld = ro${r}_rd_pvld & (~tran_cnt_idle); \n"; +//: print " end \n"; +//: } +//: } +//: print "default: begin \n"; +//: print " dp_vld = 1'b0; \n"; +//: print "end \n"; +//: print "endcase \n"; +//: print "end \n"; +//: +//: +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_rd_prdy = dp_rdy & (fifo_sel==$r) & (~tran_cnt_idle); \n"; +//: } +//: } +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: print "always @(*) \n"; +//: print "begin \n"; +//: print "case(fifo_sel) \n"; +//: foreach my $r (0..$k-1) { +//: print " 6'd$r: begin \n"; +//: print " dp_data = ro${r}_rd_pd[${kx}-1:0]; \n"; +//: print " end \n"; +//: } +//: print "default: dp_data = {${kx}{1'b0}}; \n"; +//: print "endcase \n"; +//: print "end \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + & (~lat_rd_mask[0] | (lat_rd_mask[0] & ro0_wr_rdy)) + ; + assign ro0_wr_pvld = lat_rd_pvld & (lat_rd_mask[0] & ro0_wr_rdy) + ; + assign ro0_wr_rdy = &ro0_wr_rdys; + assign ro0_wr_pd = lat_rd_data[8*0+8-1:8*0]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro0_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[0]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro0_wr_pd) + ,.ro_rd_prdy (ro0_rd_prdy) + ,.ro_rd_pvld (ro0_rd_pvld) + ,.ro_rd_pd (ro0_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro1_wr_pd = lat_rd_data[8*1+8-1:8*1]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro1_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[1]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro1_wr_pd) + ,.ro_rd_prdy (ro1_rd_prdy) + ,.ro_rd_pvld (ro1_rd_pvld) + ,.ro_rd_pd (ro1_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro2_wr_pd = lat_rd_data[8*2+8-1:8*2]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro2_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[2]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro2_wr_pd) + ,.ro_rd_prdy (ro2_rd_prdy) + ,.ro_rd_pvld (ro2_rd_pvld) + ,.ro_rd_pd (ro2_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro3_wr_pd = lat_rd_data[8*3+8-1:8*3]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro3_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[3]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro3_wr_pd) + ,.ro_rd_prdy (ro3_rd_prdy) + ,.ro_rd_pvld (ro3_rd_pvld) + ,.ro_rd_pd (ro3_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro4_wr_pd = lat_rd_data[8*4+8-1:8*4]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro4_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[4]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro4_wr_pd) + ,.ro_rd_prdy (ro4_rd_prdy) + ,.ro_rd_pvld (ro4_rd_pvld) + ,.ro_rd_pd (ro4_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro5_wr_pd = lat_rd_data[8*5+8-1:8*5]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro5_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[5]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro5_wr_pd) + ,.ro_rd_prdy (ro5_rd_prdy) + ,.ro_rd_pvld (ro5_rd_pvld) + ,.ro_rd_pd (ro5_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro6_wr_pd = lat_rd_data[8*6+8-1:8*6]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro6_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[6]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro6_wr_pd) + ,.ro_rd_prdy (ro6_rd_prdy) + ,.ro_rd_pvld (ro6_rd_pvld) + ,.ro_rd_pd (ro6_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro7_wr_pd = lat_rd_data[8*7+8-1:8*7]; + NV_NVDLA_CDP_RDMA_ro_fifo u_ro7_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[7]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro7_wr_pd) + ,.ro_rd_prdy (ro7_rd_prdy) + ,.ro_rd_pvld (ro7_rd_pvld) + ,.ro_rd_pd (ro7_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign fifo_sel[5:0] = tran_cnt_idle ? 6'd0 : ((6'd8-tran_cnt)); + // DATA MUX out + always @(*) begin + case(fifo_sel) + 6'd0: begin + dp_vld = ro0_rd_pvld & (~tran_cnt_idle); + end + 6'd1: begin + dp_vld = ro1_rd_pvld & (~tran_cnt_idle); + end + 6'd2: begin + dp_vld = ro2_rd_pvld & (~tran_cnt_idle); + end + 6'd3: begin + dp_vld = ro3_rd_pvld & (~tran_cnt_idle); + end + 6'd4: begin + dp_vld = ro4_rd_pvld & (~tran_cnt_idle); + end + 6'd5: begin + dp_vld = ro5_rd_pvld & (~tran_cnt_idle); + end + 6'd6: begin + dp_vld = ro6_rd_pvld & (~tran_cnt_idle); + end + 6'd7: begin + dp_vld = ro7_rd_pvld & (~tran_cnt_idle); + end +default: begin + dp_vld = 1'b0; +end +endcase +end + assign ro0_rd_prdy = dp_rdy & (fifo_sel==0) & (~tran_cnt_idle); + assign ro1_rd_prdy = dp_rdy & (fifo_sel==1) & (~tran_cnt_idle); + assign ro2_rd_prdy = dp_rdy & (fifo_sel==2) & (~tran_cnt_idle); + assign ro3_rd_prdy = dp_rdy & (fifo_sel==3) & (~tran_cnt_idle); + assign ro4_rd_prdy = dp_rdy & (fifo_sel==4) & (~tran_cnt_idle); + assign ro5_rd_prdy = dp_rdy & (fifo_sel==5) & (~tran_cnt_idle); + assign ro6_rd_prdy = dp_rdy & (fifo_sel==6) & (~tran_cnt_idle); + assign ro7_rd_prdy = dp_rdy & (fifo_sel==7) & (~tran_cnt_idle); +always @(*) +begin +case(fifo_sel) + 6'd0: begin + dp_data = ro0_rd_pd[8-1:0]; + end + 6'd1: begin + dp_data = ro1_rd_pd[8-1:0]; + end + 6'd2: begin + dp_data = ro2_rd_pd[8-1:0]; + end + 6'd3: begin + dp_data = ro3_rd_pd[8-1:0]; + end + 6'd4: begin + dp_data = ro4_rd_pd[8-1:0]; + end + 6'd5: begin + dp_data = ro5_rd_pd[8-1:0]; + end + 6'd6: begin + dp_data = ro6_rd_pd[8-1:0]; + end + 6'd7: begin + dp_data = ro7_rd_pd[8-1:0]; + end +default: dp_data = {8{1'b0}}; +endcase +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////// +//replacd by 0 value in invalid position +////////////////////// +//: my $tp = 1; +//: my $atmm = 8; +//: my $tt_fifo_num = 64/8/$tp; +//: my $M = 64/8/$atmm; +//: my $F = $atmm/$tp; +//: +//: my $tpbw = int(log($tp)/log(2)); +//: my $atmmbw = int(log($atmm)/log(2)); +//: print " assign ele_in_channel = {{(5-${atmmbw}){1'b0}},reg2dp_channel[${atmmbw}-1:0]}; \n"; +//: print " assign rest_channel=(6'd${F}-ele_in_channel[${atmmbw}-1:${tpbw}]); \n"; +//: +//: ## if(1 == 8) { +//: print " always @(*) begin \n"; +//: print " case(fifo_sel) \n"; +//: foreach my $r (0..$tt_fifo_num-1) { +//: print " 6'd$r: begin \n"; +//: print " if(is_last_c) begin \n"; +//: print " if({2'd0,tran_cnt} < rest_channel) \n"; +//: print " invalid_flag = {${tp}{1'b1}}; \n"; +//: print " else if({2'd0,tran_cnt} > rest_channel) \n"; +//: print " invalid_flag = {${tp}{1'b0}}; \n"; +//: print " else \n"; +//: +//: if($tp == 1) { +//: print " invalid_flag = {${tp}{1'b0}}; \n"; +//: } else { +//: print " invalid_flag = {${tp}{ele_in_channel[${tpbw}-1:0]==${tpbw}'d0}} & {{(${tp}-1){1'b1}},1'b0} \n"; +//: foreach my $i (0..$tp-2) { +//: my $j = $i + 1; +//: print " | {${tp}{ele_in_channel[${tpbw}-1:0]==${tpbw}'d${j}}} & {{(${tp}-${j}){1'b1}},${j}'b0} \n"; +//: } +//: print " ; \n"; +//: } +//: print " end else \n"; +//: print " invalid_flag = {${tp}{1'b0}}; \n"; +//: print " end \n"; +//: } +//: print "default: invalid_flag = {${tp}{1'b0}}; \n"; +//: print "endcase \n"; +//: print "end \n"; +//: ## } +//: ## elsif(1 == 1) { +//: ## print " always @(*) \n"; +//: ## print " begin \n"; +//: ## print " case(fifo_sel) \n"; +//: ## foreach my $r (0..$tt_fifo_num-1) { +//: ## print " 6'd$r: begin \n"; +//: ## print " if(is_last_c) begin \n"; +//: ## print " if(tran_cnt <= rest_channel) +//: ## print " invalid_flag = 1'h1; \n"; +//: ## print " else \n"; +//: ## print " invalid_flag = 1'h0; \n"; +//: ## print " end else \n"; +//: ## print " invalid_flag = 1'h0; \n"; +//: ## print " end \n"; +//: ## } +//: ## print "default: invalid_flag = 1'h0; \n"; +//: ## print "endcase \n"; +//: ## print "end; \n"; +//: ## } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign ele_in_channel = {{(5-3){1'b0}},reg2dp_channel[3-1:0]}; + assign rest_channel=(6'd8-ele_in_channel[3-1:0]); + always @(*) begin + case(fifo_sel) + 6'd0: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd1: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd2: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd3: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd4: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd5: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd6: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end + 6'd7: begin + if(is_last_c) begin + if({2'd0,tran_cnt} < rest_channel) + invalid_flag = {1{1'b1}}; + else if({2'd0,tran_cnt} > rest_channel) + invalid_flag = {1{1'b0}}; + else + invalid_flag = {1{1'b0}}; + end else + invalid_flag = {1{1'b0}}; + end +default: invalid_flag = {1{1'b0}}; +endcase +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// Return Data Counting +//============== +// unpack from rd_pd, which should be the same order as wr_pd +assign cq_rd_prdy = tran_rdy; +assign tran_vld = cq_rd_pvld; +assign ig2eg_width[2:0] = cq_rd_pd[2:0]; +assign ig2eg_align = cq_rd_pd[3]; +assign ig2eg_last_w = cq_rd_pd[4]; +assign ig2eg_last_h = cq_rd_pd[5]; +assign ig2eg_last_c = cq_rd_pd[6]; +assign tran_num[3:0] = ig2eg_width + 1; +assign tran_cnt_idle = (tran_cnt==0); +assign is_last_tran = (tran_cnt==1); +assign is_last_beat = (beat_cnt==1); +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $r (0..$k-1) { +//: print " assign fifo_rd_pvld[$r] = (fifo_sel==${r}) & ro${r}_rd_pvld; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign fifo_rd_pvld[0] = (fifo_sel==0) & ro0_rd_pvld; + assign fifo_rd_pvld[1] = (fifo_sel==1) & ro1_rd_pvld; + assign fifo_rd_pvld[2] = (fifo_sel==2) & ro2_rd_pvld; + assign fifo_rd_pvld[3] = (fifo_sel==3) & ro3_rd_pvld; + assign fifo_rd_pvld[4] = (fifo_sel==4) & ro4_rd_pvld; + assign fifo_rd_pvld[5] = (fifo_sel==5) & ro5_rd_pvld; + assign fifo_rd_pvld[6] = (fifo_sel==6) & ro6_rd_pvld; + assign fifo_rd_pvld[7] = (fifo_sel==7) & ro7_rd_pvld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire tran_accept; +//the first cq_rd_prdy should start when fifo have data to be read +assign tran_rdy = (tran_cnt_idle & (|fifo_rd_pvld)) || (is_last_tran & is_last_beat & dp_rdy); +assign tran_accept = tran_vld & tran_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_cnt <= 0; + beat_cnt <= 0; + end else begin + if(is_cube_end & tran_rdy) begin + tran_cnt <= 0; + beat_cnt <= 0; + end else if(tran_rdy) begin + if (tran_vld) begin +//: my $tp = 1*8; +//: my $atmm = 8*8; +//: my $F = $atmm/$tp; +//: print " tran_cnt <= 4'd${F}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + tran_cnt <= 4'd8; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + beat_cnt <= tran_num; + end else begin + tran_cnt <= 0; + beat_cnt <= 0; + end + end else if (dp_rdy & (|fifo_rd_pvld)) begin + beat_cnt <= (beat_cnt==1)? width_cnt : beat_cnt - 1; + if (is_last_beat) begin + tran_cnt <= tran_cnt - 1; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_align <= 0; + end else begin + if (tran_rdy) begin + beat_align <= 0; + end else if (dp_rdy & |fifo_rd_pvld) begin + if (is_last_beat) begin + beat_align <= 0; + end else begin + beat_align <= beat_align + 1'b1; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cnt <= {4{1'b0}}; + end else begin + if ((tran_accept) == 1'b1) begin + width_cnt <= tran_num; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + width_cnt <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_last_w <= 1'b0; + is_last_h <= 1'b0; + is_last_c <= 1'b0; + end else begin + if(is_cube_end & tran_rdy) begin + is_last_w <= 1'b0; + is_last_h <= 1'b0; + is_last_c <= 1'b0; + end else if(tran_accept) begin + is_last_w <= ig2eg_last_w; + is_last_h <= ig2eg_last_h; + is_last_c <= ig2eg_last_c; + end + end +end +assign is_b_sync = is_last_beat; +assign dp_pos_w[3:0] = width_cnt - beat_cnt; //spyglass disable W484 +assign dp_width[3:0] = width_cnt; //spyglass disable W484 +wire mon_dp_pos_c; +//: my $tp = 1*8; +//: my $atmm = 8*8; +//: my $F = $atmm/$tp; +//: print " assign {mon_dp_pos_c,dp_pos_c[2:0]} = 4'd${F} - tran_cnt; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign {mon_dp_pos_c,dp_pos_c[2:0]} = 4'd8 - tran_cnt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp_b_sync = is_b_sync; +assign dp_last_w = is_last_w; +assign dp_last_h = is_last_h; +assign dp_last_c = is_last_c; +assign is_cube_end = is_last_w & is_last_h & is_last_c; +assign dp2reg_done_f = is_cube_end & tran_rdy; +assign eg2ig_done_f = is_cube_end & tran_rdy; +//============== +// OUTPUT PACK and PIPE: To Data Processor +//============== +// PD Pack +assign dp_invalid = {{(8-1){1'b0}},invalid_flag}; +// PKT_PACK_WIRE( cdp_rdma2dp , dp_ , dp_pd ) +assign dp_pd[1*8 -1:0] = dp_data[1*8 -1:0]; +assign dp_pd[1*8 +3:1*8] = dp_pos_w[3:0]; +assign dp_pd[1*8 +7:1*8 +4] = dp_width[3:0]; +assign dp_pd[1*8 +10:1*8 +8] = dp_pos_c[2:0]; +assign dp_pd[1*8 +11] = dp_b_sync ; +assign dp_pd[1*8 +12] = dp_last_w ; +assign dp_pd[1*8 +13] = dp_last_h ; +assign dp_pd[1*8 +14] = dp_last_c ; +assign dp_pd[1*8 +22:1*8 +15] = dp_invalid[7:0]; +////////::pipe -bc -is {cdp_rdma2dp_pd,dp2reg_done_flag,eg2ig_done_flag} (cdp_rdma2dp_valid_f,cdp_rdma2dp_ready) <= {dp_pd,dp2reg_done_f,eg2ig_done_f} (dp_vld, dp_rdy); +wire [1*8 +25-1:0] cdp_rdma2dp_pd_i; +assign cdp_rdma2dp_pd_i = {dp_pd,dp2reg_done_f,eg2ig_done_f}; +//assign {cdp_rdma2dp_pd,dp2reg_done_flag,eg2ig_done_flag} = cdp_rdma2dp_pd_o; +//: my $k=1*8 +25; +//: &eperl::pipe(" -wid $k -is -do cdp_rdma2dp_pd_o -vo cdp_rdma2dp_valid_f -ri cdp_rdma2dp_ready -di cdp_rdma2dp_pd_i -vi dp_vld -ro dp_rdy_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg dp_rdy_f; +reg skid_flop_dp_rdy_f; +reg skid_flop_dp_vld; +reg [33-1:0] skid_flop_cdp_rdma2dp_pd_i; +reg pipe_skid_dp_vld; +reg [33-1:0] pipe_skid_cdp_rdma2dp_pd_i; +// Wire +wire skid_dp_vld; +wire [33-1:0] skid_cdp_rdma2dp_pd_i; +wire skid_dp_rdy_f; +wire pipe_skid_dp_rdy_f; +wire cdp_rdma2dp_valid_f; +wire [33-1:0] cdp_rdma2dp_pd_o; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp_rdy_f <= 1'b1; + skid_flop_dp_rdy_f <= 1'b1; + end else begin + dp_rdy_f <= skid_dp_rdy_f; + skid_flop_dp_rdy_f <= skid_dp_rdy_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_dp_vld <= 1'b0; + end else begin + if (skid_flop_dp_rdy_f) begin + skid_flop_dp_vld <= dp_vld; + end + end +end +assign skid_dp_vld = (skid_flop_dp_rdy_f) ? dp_vld : skid_flop_dp_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_dp_rdy_f & dp_vld) begin + skid_flop_cdp_rdma2dp_pd_i[33-1:0] <= cdp_rdma2dp_pd_i[33-1:0]; + end +end +assign skid_cdp_rdma2dp_pd_i[33-1:0] = (skid_flop_dp_rdy_f) ? cdp_rdma2dp_pd_i[33-1:0] : skid_flop_cdp_rdma2dp_pd_i[33-1:0]; + + +// PIPE READY +assign skid_dp_rdy_f = pipe_skid_dp_rdy_f || !pipe_skid_dp_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_dp_vld <= 1'b0; + end else begin + if (skid_dp_rdy_f) begin + pipe_skid_dp_vld <= skid_dp_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_dp_rdy_f && skid_dp_vld) begin + pipe_skid_cdp_rdma2dp_pd_i[33-1:0] <= skid_cdp_rdma2dp_pd_i[33-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_dp_rdy_f = cdp_rdma2dp_ready; +assign cdp_rdma2dp_valid_f = pipe_skid_dp_vld; +assign cdp_rdma2dp_pd_o = pipe_skid_cdp_rdma2dp_pd_i; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp_rdy = dp_rdy_f; +assign {cdp_rdma2dp_pd,dp2reg_done_flag,eg2ig_done_flag} = cdp_rdma2dp_pd_o; +assign cdp_rdma2dp_valid = cdp_rdma2dp_valid_f; +assign dp2reg_done = (cdp_rdma2dp_valid_f & cdp_rdma2dp_ready & dp2reg_done_flag) ? 1'b1 : 1'b0; +assign eg2ig_done = (cdp_rdma2dp_valid_f & cdp_rdma2dp_ready & eg2ig_done_flag) ? 1'b1 : 1'b0; +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_RDMA_eg__bsync_end_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_b_sync & (~dp_rdy); + endproperty +// Cover 0 : "is_b_sync & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__bsync_end_stall__0_COV : cover property (CDP_RDMA_eg__bsync_end_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg__widthe_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_w & (~dp_rdy); + endproperty +// Cover 1 : "is_last_w & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__widthe_end_stall__1_COV : cover property (CDP_RDMA_eg__widthe_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg__cube_end_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_h & (~dp_rdy); + endproperty +// Cover 2 : "is_last_h & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__cube_end_stall__2_COV : cover property (CDP_RDMA_eg__cube_end_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg__channel_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_c & (~dp_rdy); + endproperty +// Cover 3 : "is_last_c & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__channel_end_stall__3_COV : cover property (CDP_RDMA_eg__channel_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg_backpressure_cq__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + tran_rdy & (~tran_vld) & (~is_cube_end); + endproperty +// Cover 4 : "tran_rdy & (~tran_vld) & (~is_cube_end)" + FUNCPOINT_CDP_RDMA_eg_backpressure_cq__4_COV : cover property (CDP_RDMA_eg_backpressure_cq__4_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_RDMA_eg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_RDMA_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 61 -w 514 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] lat_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_61 = ( wr_count_next_no_wr_popping == 6'd61 ); +wire wr_count_next_is_61 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_61; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 6'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [5:0] lat_wr_adr; // current write address +wire [5:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_61x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [5:0] wr_adr_next = (lat_wr_adr == 6'd60) ? 6'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 6'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [5:0] lat_rd_adr; // current read address +// next read address +wire [5:0] rd_adr_next = (lat_rd_adr == 6'd60) ? 6'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 6'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [5:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 6'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd61 : wr_limit_reg} ) + , .curr ( {26'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_RDMA_lat_fifo +// Re-Order Data +// if we have rd_reg, then depth = required - 1 ,so depth=4-1=3 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_RDMA_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -rd_reg -rand_none -ram_bypass -d 4 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +input [7:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [7:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [3:0] ro_wr_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 4'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [2:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [2:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 4'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 4'd8 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [2:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int && !ro_rd_prdy); +reg [3:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 4'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] ro_rd_pd; // output data register +wire rd_req_next = (ro_rd_pvld_p || (ro_rd_pvld_int && !ro_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + end else begin + ro_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ro_rd_pd <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ro_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_ro_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDP_RDMA_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [2:0] wa; +input [3:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [2:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[2:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 8) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +reg [7:0] ram_ff4; +reg [7:0] ram_ff5; +reg [7:0] ram_ff6; +reg [7:0] ram_ff7; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 3'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 3'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 3'd7 ) begin + ram_ff7 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [2:0] Wa0; +input we0; +input [7:0] Di0; +input [2:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[7:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +wire [7:0] Q4 = mem[4]; +wire [7:0] Q5 = mem[5]; +wire [7:0] Q6 = mem[6]; +wire [7:0] Q7 = mem[7]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8] } +endmodule // vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +//vmw: Memory vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +//vmw: Address-size 3 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v.vcp new file mode 100644 index 0000000..4ed6467 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v.vcp @@ -0,0 +1,1766 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp_rdma2dp_ready //|< i + ,cq_rd_pd //|< i + ,cq_rd_pvld //|< i + ,mcif2cdp_rd_rsp_pd //|< i + ,mcif2cdp_rd_rsp_valid //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_channel //|< i + ,reg2dp_input_data //|< i + ,reg2dp_src_ram_type //|< i + ,cdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,cdp_rdma2dp_pd //|> o + ,cdp_rdma2dp_valid //|> o + ,cq_rd_prdy //|> o + ,dp2reg_done //|> o + ,eg2ig_done //|> o + ,mcif2cdp_rd_rsp_ready //|> o + ); +///////////////////////////////////////////////////////////////////////////////////////// +input [4:0] reg2dp_channel; +input [1:0] reg2dp_input_data; +input reg2dp_src_ram_type; +output dp2reg_done; +output eg2ig_done; +input nvdla_core_clk; +input nvdla_core_rstn; +input mcif2cdp_rd_rsp_valid; /* data valid */ +output mcif2cdp_rd_rsp_ready; /* data return handshake */ +//: my $k=64; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: print "input [${k}+${M}-1:0] mcif2cdp_rd_rsp_pd; \n"; +output cdp2mcif_rd_cdt_lat_fifo_pop; +output cdp_rdma2dp_valid; /* data valid */ +input cdp_rdma2dp_ready; /* data return handshake */ +output [1*8 +22:0] cdp_rdma2dp_pd; +input cq_rd_pvld; /* data valid */ +output cq_rd_prdy; /* data return handshake */ +input [6:0] cq_rd_pd; +input [31:0] pwrbus_ram_pd; +///////////////////////////////////////////////////////////////////////////////////////// +//: my $Mnum = 64/8/8; +//: my $Mnumbit= int( log($Mnum)/log(2) ); +//: if($Mnum > 1){ +//: print " reg [${Mnumbit}-1:0] beat_align; \n"; +//: } else{ +//: print " reg beat_align; \n"; +//: } +reg [3:0] beat_cnt; +reg cdp2mcif_rd_cdt_lat_fifo_pop; +wire [1*8 +22:0] cdp_rdma2dp_pd; +//reg cdp_rdma2dp_valid_f; +wire dp2reg_done_flag; +reg [1*8 -1:0] dp_data; +wire dp_rdy; +reg dp_vld; +wire eg2ig_done_flag; +reg [1 -1:0] invalid_flag; +reg is_last_c; +reg is_last_h; +reg is_last_w; +reg [3:0] tran_cnt; +reg [3:0] width_cnt; +wire [4:0] ele_in_channel; +wire cv_dma_rd_rsp_vld; +wire cv_int_rd_rsp_ready; +wire cv_int_rd_rsp_valid; +wire dma_rd_cdt_lat_fifo_pop; +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_type; +wire dma_rd_rsp_vld; +wire dp2reg_done_f; +wire dp_b_sync; +wire [7:0] dp_invalid; +wire dp_last_c; +wire dp_last_h; +wire dp_last_w; +wire [1*8 +22:0] dp_pd; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire [3:0] dp_width; +wire eg2ig_done_f; +wire [7:0] fifo_rd_pvld; +wire [5:0] fifo_sel; +wire ig2eg_align; +wire ig2eg_last_c; +wire ig2eg_last_h; +wire ig2eg_last_w; +wire [2:0] ig2eg_width; +wire is_b_sync; +wire is_cube_end; +wire is_last_beat; +wire is_last_tran; +//: my $k=64; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: print "wire [${k}+${M}-1:0] cv_dma_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] cv_int_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] cvif2cdp_rd_rsp_pd_d0; \n"; +//: print "wire [${k}+${M}-1:0] dma_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] lat_rd_pd; \n"; +//: print "wire [${k}+${M}-1:0] mc_dma_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] mc_int_rd_rsp_pd; \n"; +//: print "wire [${k}+${M}-1:0] mcif2cdp_rd_rsp_pd_d0; \n"; +wire [64 -1:0] lat_rd_data; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: print "wire [${M}-1:0] lat_rd_mask; \n"; +wire lat_rd_prdy; +wire lat_rd_pvld; +wire mc_dma_rd_rsp_vld; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire mcif2cdp_rd_rsp_ready_d0; +wire mcif2cdp_rd_rsp_valid_d0; +wire [5:0] rest_channel; +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${kx}-1:0] ro${m}_rd_pd; +//: wire ro${m}_rd_prdy; +//: wire ro${m}_rd_pvld; +//: wire [${kx}-1:0] ro${m}_wr_pd; +//: ); +//: } +//: foreach my $m (0..$M-1) { +//: print qq( +//: wire ro${m}_wr_pvld; +//: wire ro${m}_wr_rdy; +//: ); +//: } +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire [${F}-1:0] ro${i}_wr_rdys; +//: ); +//: } +wire tran_cnt_idle; +wire [3:0] tran_num; +wire tran_rdy; +wire tran_vld; +/////////////////////////////////////////////////////////////////////////// +//============== +// DMA Interface +//============== +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2cdp_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2cdp_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2cdp_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +/////////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + cdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_type == 1'b1); + end +end +assign dma_rd_rsp_type = reg2dp_src_ram_type; +//============== +// Latency FIFO to buffer return DATA +//============== +NV_NVDLA_CDP_RDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lat_wr_prdy (dma_rd_rsp_rdy) //|> w + ,.lat_wr_pvld (dma_rd_rsp_vld) //|< w + ,.lat_wr_pd (dma_rd_rsp_pd) //|< w + ,.lat_rd_prdy (lat_rd_prdy) //|< w + ,.lat_rd_pvld (lat_rd_pvld) //|> w + ,.lat_rd_pd (lat_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign lat_rd_data[64 -1:0] = lat_rd_pd[64 -1:0]; +assign lat_rd_mask[1 -1:0] = lat_rd_pd[65 -1: 64]; +assign dma_rd_cdt_lat_fifo_pop = lat_rd_pvld & lat_rd_prdy; +//============== +// Re-Order FIFO to send data to CDP-core in DP order(read NVDLA PP uARCH for details) +//============== +assign lat_rd_prdy = lat_rd_pvld +//: my $msk = 1; +//: foreach my $k (0..$msk-1) { +//: print " & (~lat_rd_mask[$k] | (lat_rd_mask[$k] & ro${k}_wr_rdy)) \n"; +//: } +//: print " ; \n"; +//: +//: my $tp = 1*8; ## throughput +//: my $atmm = 8*8; ## atomic_m +//: my $M = 64/$atmm; ## atomic_m number per dma transaction +//: my $F = $atmm/$tp; ## how many fifo contribute to one atomic_m +//: +//: +//: foreach my $i (0..$M-1){ +//: print " assign ro${i}_wr_pvld = lat_rd_pvld & (lat_rd_mask[${i}] & ro${i}_wr_rdy) \n"; +//: foreach my $s (0..$msk-1) { +//: if($s != $i) { +//: print " & ( ~lat_rd_mask[${s}] | (lat_rd_mask[${s}] & ro${s}_wr_rdy)) \n"; +//: } +//: } +//: print " ; \n"; +//: } +//: +//: +//: foreach my $m (0..$M-1) { +//: print " assign ro${m}_wr_rdy = &ro${m}_wr_rdys; \n"; +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_wr_pd = lat_rd_data[${tp}*${r}+${tp}-1:${tp}*${r}]; \n"; +//: print " NV_NVDLA_CDP_RDMA_ro_fifo u_ro${r}_fifo( \n"; +//: print " .nvdla_core_clk (nvdla_core_clk) \n"; +//: print " ,.nvdla_core_rstn (nvdla_core_rstn) \n"; +//: print " ,.ro_wr_prdy (ro${m}_wr_rdys[$f]) \n"; +//: print " ,.ro_wr_pvld (ro${m}_wr_pvld) \n"; +//: print " ,.ro_wr_pd (ro${r}_wr_pd) \n"; +//: print " ,.ro_rd_prdy (ro${r}_rd_prdy) \n"; +//: print " ,.ro_rd_pvld (ro${r}_rd_pvld) \n"; +//: print " ,.ro_rd_pd (ro${r}_rd_pd) \n"; +//: print " ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) \n"; +//: print " ); \n"; +//: } +//: } +//: +//: +//: my $Fbit = int( log($F)/log(2) ); +//: if($M > 1) { +//: print " assign fifo_sel[5:0] = tran_cnt_idle ? 6'd0 : ((6'd${F}-tran_cnt) + {beat_align,{${Fbit}{1'b0}}}); \n"; +//: } else { +//: print " assign fifo_sel[5:0] = tran_cnt_idle ? 6'd0 : ((6'd${F}-tran_cnt)); \n"; +//: } +//: +//: +//: print " // DATA MUX out \n"; +//: print " always @(*) begin \n"; +//: print " case(fifo_sel) \n"; +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " 6'd$r: begin \n"; +//: print " dp_vld = ro${r}_rd_pvld & (~tran_cnt_idle); \n"; +//: print " end \n"; +//: } +//: } +//: print "default: begin \n"; +//: print " dp_vld = 1'b0; \n"; +//: print "end \n"; +//: print "endcase \n"; +//: print "end \n"; +//: +//: +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_rd_prdy = dp_rdy & (fifo_sel==$r) & (~tran_cnt_idle); \n"; +//: } +//: } +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: print "always @(*) \n"; +//: print "begin \n"; +//: print "case(fifo_sel) \n"; +//: foreach my $r (0..$k-1) { +//: print " 6'd$r: begin \n"; +//: print " dp_data = ro${r}_rd_pd[${kx}-1:0]; \n"; +//: print " end \n"; +//: } +//: print "default: dp_data = {${kx}{1'b0}}; \n"; +//: print "endcase \n"; +//: print "end \n"; +////////////////////// +//replacd by 0 value in invalid position +////////////////////// +//: my $tp = 1; +//: my $atmm = 8; +//: my $tt_fifo_num = 64/8/$tp; +//: my $M = 64/8/$atmm; +//: my $F = $atmm/$tp; +//: +//: my $tpbw = int(log($tp)/log(2)); +//: my $atmmbw = int(log($atmm)/log(2)); +//: print " assign ele_in_channel = {{(5-${atmmbw}){1'b0}},reg2dp_channel[${atmmbw}-1:0]}; \n"; +//: print " assign rest_channel=(6'd${F}-ele_in_channel[${atmmbw}-1:${tpbw}]); \n"; +//: +//: ## if(1 == 8) { +//: print " always @(*) begin \n"; +//: print " case(fifo_sel) \n"; +//: foreach my $r (0..$tt_fifo_num-1) { +//: print " 6'd$r: begin \n"; +//: print " if(is_last_c) begin \n"; +//: print " if({2'd0,tran_cnt} < rest_channel) \n"; +//: print " invalid_flag = {${tp}{1'b1}}; \n"; +//: print " else if({2'd0,tran_cnt} > rest_channel) \n"; +//: print " invalid_flag = {${tp}{1'b0}}; \n"; +//: print " else \n"; +//: +//: if($tp == 1) { +//: print " invalid_flag = {${tp}{1'b0}}; \n"; +//: } else { +//: print " invalid_flag = {${tp}{ele_in_channel[${tpbw}-1:0]==${tpbw}'d0}} & {{(${tp}-1){1'b1}},1'b0} \n"; +//: foreach my $i (0..$tp-2) { +//: my $j = $i + 1; +//: print " | {${tp}{ele_in_channel[${tpbw}-1:0]==${tpbw}'d${j}}} & {{(${tp}-${j}){1'b1}},${j}'b0} \n"; +//: } +//: print " ; \n"; +//: } +//: print " end else \n"; +//: print " invalid_flag = {${tp}{1'b0}}; \n"; +//: print " end \n"; +//: } +//: print "default: invalid_flag = {${tp}{1'b0}}; \n"; +//: print "endcase \n"; +//: print "end \n"; +//: ## } +//: ## elsif(1 == 1) { +//: ## print " always @(*) \n"; +//: ## print " begin \n"; +//: ## print " case(fifo_sel) \n"; +//: ## foreach my $r (0..$tt_fifo_num-1) { +//: ## print " 6'd$r: begin \n"; +//: ## print " if(is_last_c) begin \n"; +//: ## print " if(tran_cnt <= rest_channel) +//: ## print " invalid_flag = 1'h1; \n"; +//: ## print " else \n"; +//: ## print " invalid_flag = 1'h0; \n"; +//: ## print " end else \n"; +//: ## print " invalid_flag = 1'h0; \n"; +//: ## print " end \n"; +//: ## } +//: ## print "default: invalid_flag = 1'h0; \n"; +//: ## print "endcase \n"; +//: ## print "end; \n"; +//: ## } +//============== +// Return Data Counting +//============== +// unpack from rd_pd, which should be the same order as wr_pd +assign cq_rd_prdy = tran_rdy; +assign tran_vld = cq_rd_pvld; +assign ig2eg_width[2:0] = cq_rd_pd[2:0]; +assign ig2eg_align = cq_rd_pd[3]; +assign ig2eg_last_w = cq_rd_pd[4]; +assign ig2eg_last_h = cq_rd_pd[5]; +assign ig2eg_last_c = cq_rd_pd[6]; +assign tran_num[3:0] = ig2eg_width + 1; +assign tran_cnt_idle = (tran_cnt==0); +assign is_last_tran = (tran_cnt==1); +assign is_last_beat = (beat_cnt==1); +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $r (0..$k-1) { +//: print " assign fifo_rd_pvld[$r] = (fifo_sel==${r}) & ro${r}_rd_pvld; \n"; +//: } +wire tran_accept; +//the first cq_rd_prdy should start when fifo have data to be read +assign tran_rdy = (tran_cnt_idle & (|fifo_rd_pvld)) || (is_last_tran & is_last_beat & dp_rdy); +assign tran_accept = tran_vld & tran_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_cnt <= 0; + beat_cnt <= 0; + end else begin + if(is_cube_end & tran_rdy) begin + tran_cnt <= 0; + beat_cnt <= 0; + end else if(tran_rdy) begin + if (tran_vld) begin +//: my $tp = 1*8; +//: my $atmm = 8*8; +//: my $F = $atmm/$tp; +//: print " tran_cnt <= 4'd${F}; \n"; + beat_cnt <= tran_num; + end else begin + tran_cnt <= 0; + beat_cnt <= 0; + end + end else if (dp_rdy & (|fifo_rd_pvld)) begin + beat_cnt <= (beat_cnt==1)? width_cnt : beat_cnt - 1; + if (is_last_beat) begin + tran_cnt <= tran_cnt - 1; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_align <= 0; + end else begin + if (tran_rdy) begin + beat_align <= 0; + end else if (dp_rdy & |fifo_rd_pvld) begin + if (is_last_beat) begin + beat_align <= 0; + end else begin + beat_align <= beat_align + 1'b1; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cnt <= {4{1'b0}}; + end else begin + if ((tran_accept) == 1'b1) begin + width_cnt <= tran_num; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + width_cnt <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_last_w <= 1'b0; + is_last_h <= 1'b0; + is_last_c <= 1'b0; + end else begin + if(is_cube_end & tran_rdy) begin + is_last_w <= 1'b0; + is_last_h <= 1'b0; + is_last_c <= 1'b0; + end else if(tran_accept) begin + is_last_w <= ig2eg_last_w; + is_last_h <= ig2eg_last_h; + is_last_c <= ig2eg_last_c; + end + end +end +assign is_b_sync = is_last_beat; +assign dp_pos_w[3:0] = width_cnt - beat_cnt; //spyglass disable W484 +assign dp_width[3:0] = width_cnt; //spyglass disable W484 +wire mon_dp_pos_c; +//: my $tp = 1*8; +//: my $atmm = 8*8; +//: my $F = $atmm/$tp; +//: print " assign {mon_dp_pos_c,dp_pos_c[2:0]} = 4'd${F} - tran_cnt; \n"; +assign dp_b_sync = is_b_sync; +assign dp_last_w = is_last_w; +assign dp_last_h = is_last_h; +assign dp_last_c = is_last_c; +assign is_cube_end = is_last_w & is_last_h & is_last_c; +assign dp2reg_done_f = is_cube_end & tran_rdy; +assign eg2ig_done_f = is_cube_end & tran_rdy; +//============== +// OUTPUT PACK and PIPE: To Data Processor +//============== +// PD Pack +assign dp_invalid = {{(8-1){1'b0}},invalid_flag}; +// PKT_PACK_WIRE( cdp_rdma2dp , dp_ , dp_pd ) +assign dp_pd[1*8 -1:0] = dp_data[1*8 -1:0]; +assign dp_pd[1*8 +3:1*8] = dp_pos_w[3:0]; +assign dp_pd[1*8 +7:1*8 +4] = dp_width[3:0]; +assign dp_pd[1*8 +10:1*8 +8] = dp_pos_c[2:0]; +assign dp_pd[1*8 +11] = dp_b_sync ; +assign dp_pd[1*8 +12] = dp_last_w ; +assign dp_pd[1*8 +13] = dp_last_h ; +assign dp_pd[1*8 +14] = dp_last_c ; +assign dp_pd[1*8 +22:1*8 +15] = dp_invalid[7:0]; +////////::pipe -bc -is {cdp_rdma2dp_pd,dp2reg_done_flag,eg2ig_done_flag} (cdp_rdma2dp_valid_f,cdp_rdma2dp_ready) <= {dp_pd,dp2reg_done_f,eg2ig_done_f} (dp_vld, dp_rdy); +wire [1*8 +25-1:0] cdp_rdma2dp_pd_i; +assign cdp_rdma2dp_pd_i = {dp_pd,dp2reg_done_f,eg2ig_done_f}; +//assign {cdp_rdma2dp_pd,dp2reg_done_flag,eg2ig_done_flag} = cdp_rdma2dp_pd_o; +//: my $k=1*8 +25; +//: &eperl::pipe(" -wid $k -is -do cdp_rdma2dp_pd_o -vo cdp_rdma2dp_valid_f -ri cdp_rdma2dp_ready -di cdp_rdma2dp_pd_i -vi dp_vld -ro dp_rdy_f "); +assign dp_rdy = dp_rdy_f; +assign {cdp_rdma2dp_pd,dp2reg_done_flag,eg2ig_done_flag} = cdp_rdma2dp_pd_o; +assign cdp_rdma2dp_valid = cdp_rdma2dp_valid_f; +assign dp2reg_done = (cdp_rdma2dp_valid_f & cdp_rdma2dp_ready & dp2reg_done_flag) ? 1'b1 : 1'b0; +assign eg2ig_done = (cdp_rdma2dp_valid_f & cdp_rdma2dp_ready & eg2ig_done_flag) ? 1'b1 : 1'b0; +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_RDMA_eg__bsync_end_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_b_sync & (~dp_rdy); + endproperty +// Cover 0 : "is_b_sync & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__bsync_end_stall__0_COV : cover property (CDP_RDMA_eg__bsync_end_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg__widthe_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_w & (~dp_rdy); + endproperty +// Cover 1 : "is_last_w & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__widthe_end_stall__1_COV : cover property (CDP_RDMA_eg__widthe_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg__cube_end_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_h & (~dp_rdy); + endproperty +// Cover 2 : "is_last_h & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__cube_end_stall__2_COV : cover property (CDP_RDMA_eg__cube_end_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg__channel_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_c & (~dp_rdy); + endproperty +// Cover 3 : "is_last_c & (~dp_rdy)" + FUNCPOINT_CDP_RDMA_eg__channel_end_stall__3_COV : cover property (CDP_RDMA_eg__channel_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_eg_backpressure_cq__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + tran_rdy & (~tran_vld) & (~is_cube_end); + endproperty +// Cover 4 : "tran_rdy & (~tran_vld) & (~is_cube_end)" + FUNCPOINT_CDP_RDMA_eg_backpressure_cq__4_COV : cover property (CDP_RDMA_eg_backpressure_cq__4_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_RDMA_eg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_RDMA_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 61 -w 514 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] lat_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_61 = ( wr_count_next_no_wr_popping == 6'd61 ); +wire wr_count_next_is_61 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_61; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 6'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [5:0] lat_wr_adr; // current write address +wire [5:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_61x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [5:0] wr_adr_next = (lat_wr_adr == 6'd60) ? 6'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 6'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [5:0] lat_rd_adr; // current read address +// next read address +wire [5:0] rd_adr_next = (lat_rd_adr == 6'd60) ? 6'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 6'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [5:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 6'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd61 : wr_limit_reg} ) + , .curr ( {26'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_RDMA_lat_fifo +// Re-Order Data +// if we have rd_reg, then depth = required - 1 ,so depth=4-1=3 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_RDMA_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -rd_reg -rand_none -ram_bypass -d 4 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +input [7:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [7:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [3:0] ro_wr_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 4'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [2:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [2:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 4'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 4'd8 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [2:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int && !ro_rd_prdy); +reg [3:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 4'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] ro_rd_pd; // output data register +wire rd_req_next = (ro_rd_pvld_p || (ro_rd_pvld_int && !ro_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + end else begin + ro_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ro_rd_pd <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ro_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_RDMA_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_RDMA_ro_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDP_RDMA_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [2:0] wa; +input [3:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [2:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[2:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 8) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +reg [7:0] ram_ff4; +reg [7:0] ram_ff5; +reg [7:0] ram_ff6; +reg [7:0] ram_ff7; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 3'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 3'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 3'd7 ) begin + ram_ff7 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [2:0] Wa0; +input we0; +input [7:0] Di0; +input [2:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[7:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +wire [7:0] Q4 = mem[4]; +wire [7:0] Q5 = mem[5]; +wire [7:0] Q6 = mem[6]; +wire [7:0] Q7 = mem[7]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8] } +endmodule // vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +//vmw: Memory vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +//vmw: Address-size 3 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_RDMA_ro_fifo_flopram_rwsa_8x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v new file mode 100644 index 0000000..625dbd8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v @@ -0,0 +1,1061 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_ig.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp2mcif_rd_req_ready //|< i + ,cq_wr_prdy //|< i + ,eg2ig_done //|< i + ,reg2dp_channel //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_height //|< i + ,reg2dp_input_data //|< i + ,reg2dp_op_en //|< i + ,reg2dp_src_base_addr_high //|< i + ,reg2dp_src_base_addr_low //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_src_surface_stride //|< i + ,reg2dp_width //|< i + ,cdp2mcif_rd_req_pd //|> o + ,cdp2mcif_rd_req_valid //|> o + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,dp2reg_d0_perf_read_stall //|> o + ,dp2reg_d1_perf_read_stall //|> o + ); +////////////////////////////////////////////////////////////////////////////////// +input [12:0] reg2dp_channel; +input reg2dp_dma_en; +input [12:0] reg2dp_height; +input [1:0] reg2dp_input_data; +input reg2dp_op_en; +input [31:0] reg2dp_src_base_addr_high; +input [31:0] reg2dp_src_base_addr_low; +input [31:0] reg2dp_src_line_stride; +input reg2dp_src_ram_type; +input [31:0] reg2dp_src_surface_stride; +input [12:0] reg2dp_width; +output [31:0] dp2reg_d0_perf_read_stall; +output [31:0] dp2reg_d1_perf_read_stall; +input eg2ig_done; +// +input nvdla_core_clk; +input nvdla_core_rstn; +output cdp2mcif_rd_req_valid; /* data valid */ +input cdp2mcif_rd_req_ready; /* data return handshake */ +output [47 -1:0] cdp2mcif_rd_req_pd; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [6:0] cq_wr_pd; +////////////////////////////////////////////////////////////////////////////////// +reg after_op_done; +reg [63:0] base_addr_c; +reg [63:0] base_addr_w; +reg [31:0] cdp_rd_stall_count; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: reg [12-${k}:0] channel_count; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [12-3:0] channel_count; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [63:0] dma_req_addr; +reg [31:0] dp2reg_d0_perf_read_stall; +reg [31:0] dp2reg_d1_perf_read_stall; +reg [12:0] height_count; +reg layer_flag; +reg mon_base_addr_c_c; +reg mon_base_addr_w_c; +reg mon_dma_req_addr_c; +reg [31:0] mon_gap_between_layers; +reg mon_layer_end_flg; +reg mon_op_en_dly; +reg mon_size_of_32x1_in_first_block_in_width_c; +wire [10:0] number_of_total_trans_in_width; +reg [2:0] req_size; +reg [2:0] size_of_32x1_in_first_block_in_width; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg tran_vld; +reg [10:0] width_count; +wire cdp_rd_stall_count_dec; +wire cmd_accept; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +wire cv_dma_rd_req_rdy; +wire cv_dma_rd_req_vld; +wire [78:0] cv_int_rd_req_pd; +wire [78:0] cv_int_rd_req_pd_d0; +wire cv_int_rd_req_ready; +wire cv_int_rd_req_ready_d0; +wire cv_int_rd_req_valid; +wire cv_int_rd_req_valid_d0; +wire cv_rd_req_rdyi; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_ram_type; +wire dma_rd_req_rdy; +wire dma_rd_req_vld; +wire [14:0] dma_req_size; +wire ig2eg_align; +wire ig2eg_last_c; +wire ig2eg_last_h; +wire ig2eg_last_w; +wire [14:0] ig2eg_width; +wire is_chn_end; +wire is_cube_end; +wire is_first_w; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_slice_end; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire mc_rd_req_rdyi; +wire mon_number_of_32x1_block_in_channel_c; +wire mon_op_en_neg; +wire mon_op_en_pos; +wire op_done; +wire op_load; +wire rd_req_rdyi; +wire [63:0] reg2dp_base_addr; +wire [31:0] reg2dp_line_stride; +wire [63:0] reg2dp_src_base_addr; +wire [31:0] reg2dp_surf_stride; +wire [13:0] reg2dp_width_use; +wire [2:0] size_of_32x1_in_last_block_in_width; +wire [2:0] width_size; +wire [3:0] width_size_use; +//////////////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +// one bubble between operation on two layers to let ARREG to switch to the next configration group +assign op_load = reg2dp_op_en & !tran_vld; +assign op_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_vld <= 1'b0; + end else begin + if (op_done) begin + tran_vld <= 1'b0; + end else if (after_op_done) begin + tran_vld <= 1'b0; + end else if (op_load) begin + tran_vld <= 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + after_op_done <= 1'b0; + end else begin + if (op_done) begin + after_op_done <= 1'b1; + end else if (eg2ig_done) begin + after_op_done <= 1'b0; + end + end +end +//NOTE!!! assert begin +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !tran_vld && op_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//NOTE!!! assert end +//============== +// Address catenate and offset calc +//============== +assign reg2dp_src_base_addr = {reg2dp_src_base_addr_high,reg2dp_src_base_addr_low}; +assign reg2dp_width_use[13:0] = reg2dp_width + 1'b1; +//============== +//============== +// WIDTH Direction +// calculate how many atomic_m x8 blocks in width direction, also get the first and last block, which may be less than 8 +//============== +wire mon_number_of_total_trans_in_width; +assign {mon_number_of_total_trans_in_width,number_of_total_trans_in_width[10:0]} = reg2dp_width_use[13:3] + {10'd0,(|reg2dp_width_use[2:0])}; +//============== +// Positioning +//============== +assign is_first_w = (width_count==0); +assign is_chn_end = is_last_c; +assign is_slice_end = is_last_w & is_last_c; +assign is_cube_end = is_last_w & is_last_h & is_last_c; +//============== +// CHANNEL Count: with inital value of total number in C direction, and will count-- when moving in chn direction +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_count <= 0; + end else begin + if (cmd_accept) begin + if (is_last_c) begin + channel_count <= 0; + end else begin + channel_count <= channel_count + 1'b1; + end + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign is_last_c = (channel_count==reg2dp_channel[12:${k}]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign is_last_c = (channel_count==reg2dp_channel[12:3]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// assign is_last_c = (channel_count==number_of_block_in_channel-1); +//============== +// WID Count: with inital value of total number in W direction, and will count-- when moving in wid direction +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_count <= {11{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_slice_end) begin + width_count <= 0; + end else if (is_chn_end) begin + width_count <= width_count + 1'b1; + end + end + end +end +assign is_last_w = (width_count==number_of_total_trans_in_width-1); +//============== +// HEIGHT Count: move to next line after one wx1xc plane done +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + height_count <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_cube_end) begin + height_count <= 0; + end else if (is_slice_end) begin + height_count <= height_count + 1'b1; + end + end + end +end +assign is_last_h = (height_count==reg2dp_height); +//========================================== +// DMA: addr | size +//========================================== +assign reg2dp_base_addr = reg2dp_src_base_addr; +assign reg2dp_line_stride = reg2dp_src_line_stride; +assign reg2dp_surf_stride = reg2dp_src_surface_stride; +//============== +// DMA Req : ADDR : Prepration +// DMA Req: go through the CUBE: W8->C->H +//============== +// Width: need be updated when move to next line +// Trigger Condition: (is_last_c & is_last_w) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_w <= {64{1'b0}}; + {mon_base_addr_w_c,base_addr_w} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_w <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c && is_last_w) begin + {mon_base_addr_w_c,base_addr_w} <= base_addr_w + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_w_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// base_Chn: need be updated when move to next w.group +// Trigger Condition: (is_last_c) +// 1, jump to next line when is_last_w +// 2, jump to next w.group when !is_last_w +assign width_size_use[3:0] = width_size + 1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_c <= {64{1'b0}}; + {mon_base_addr_c_c,base_addr_c} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_c <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_base_addr_c_c,base_addr_c} <= base_addr_w + reg2dp_line_stride; + end else begin +//: my $atm = 8; +//: my $atmbw = int(log($atm)/log(2)); +//: print " {mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,${atmbw}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_c_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : ADDR : Generation +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_req_addr <= {64{1'b0}}; + {mon_dma_req_addr_c,dma_req_addr} <= {65{1'b0}}; + end else begin + if (op_load) begin + dma_req_addr <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_dma_req_addr_c,dma_req_addr} <= base_addr_w + reg2dp_line_stride; + end else begin +//: my $atm = 8; +//: my $atmbw = int(log($atm)/log(2)); +//: print " {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,${atmbw}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else begin + {mon_dma_req_addr_c,dma_req_addr} <= dma_req_addr + reg2dp_surf_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_dma_req_addr_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////============== +// DMA Req : SIZE : Prepration +//============== +// if there is only trans in total width, this one will be counted into the first trans, so is_first_w should take prior to is_last_w +always @(*) begin + mon_size_of_32x1_in_first_block_in_width_c = 1'b0; + if (number_of_total_trans_in_width==1) begin + size_of_32x1_in_first_block_in_width[2:0] = reg2dp_width[2:0]; + end else begin + {mon_size_of_32x1_in_first_block_in_width_c,size_of_32x1_in_first_block_in_width[2:0]} = 3'd7; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & mon_size_of_32x1_in_first_block_in_width_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// when there is no L trans, still need calc the size for last trans which belongs to middle trans +// end_addr: 0 1 2 3 4 5 6 7 +// size : 0 1 2 3 4 5 6 7 +assign size_of_32x1_in_last_block_in_width[2:0] = reg2dp_width[2:0]; +//============== +// DMA Req : SIZE : Generation +//============== +always @(*) begin + if (is_first_w) begin + req_size = size_of_32x1_in_first_block_in_width; + end else if (is_last_w) begin + req_size = size_of_32x1_in_last_block_in_width; + end else begin + req_size = 3'd7; + end +end +assign width_size = req_size; // 1~8 +assign dma_req_size = {{12{1'b0}}, req_size}; +//============== +// Context Qeueu : Beats +//============== +//assign dma_req_align = (dma_req_addr[5]==0); +assign ig2eg_width = dma_req_size; +assign ig2eg_align = 1'b0;//dma_req_align; +assign ig2eg_last_w = is_last_w; +assign ig2eg_last_h = is_last_h; +assign ig2eg_last_c = is_last_c; +assign cq_wr_pd[2:0] = ig2eg_width[2:0]; +assign cq_wr_pd[3] = ig2eg_align ; +assign cq_wr_pd[4] = ig2eg_last_w ; +assign cq_wr_pd[5] = ig2eg_last_h ; +assign cq_wr_pd[6] = ig2eg_last_c ; +assign cq_wr_pvld = tran_vld & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (cq_wr_pvld & cq_wr_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = tran_vld & cq_wr_prdy; +// PayLoad +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_req_size[14:0]; +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// reading stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = is_cube_end & cmd_accept; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_rd_req_vld & (~dma_rd_req_rdy)); + assign cdp_rd_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or cdp_rd_stall_count_dec + ) begin + stl_adv = cnt_inc ^ cdp_rd_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or cdp_rd_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !cdp_rd_stall_count_dec)? stl_cnt_inc : (!cnt_inc && cdp_rd_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + cdp_rd_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; +// VCS coverage off + end else if ((cnt_clr) == 1'b0) begin + end else begin + layer_flag <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_read_stall <= cdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & (~layer_flag)) == 1'b0) begin + end else begin + dp2reg_d0_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & (~layer_flag)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_read_stall <= cdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & layer_flag ) == 1'b0) begin + end else begin + dp2reg_d1_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & layer_flag ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Interface +//============== +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.mcif_rd_req_pd (cdp2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (cdp2mcif_rd_req_valid) + ,.mcif_rd_req_ready (cdp2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +////============== +////OBS signals +////============== +//assign obs_bus_cdp_rdma_proc_en = tran_vld; +//============== +//function point +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_RDMA_ig__dma_IF_reading_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (((dma_rd_req_vld)) && nvdla_core_rstn) |-> ((~dma_rd_req_rdy & reg2dp_op_en)); + endproperty +// Cover 0 : "(~dma_rd_req_rdy & reg2dp_op_en)" + FUNCPOINT_CDP_RDMA_ig__dma_IF_reading_stall__0_COV : cover property (CDP_RDMA_ig__dma_IF_reading_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__width_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_w & (~dma_rd_req_rdy); + endproperty +// Cover 1 : "is_last_w & (~dma_rd_req_rdy)" + FUNCPOINT_CDP_RDMA_ig__width_end_stall__1_COV : cover property (CDP_RDMA_ig__width_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__last_slice_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_h & (~dma_rd_req_rdy); + endproperty +// Cover 2 : "is_last_h & (~dma_rd_req_rdy)" + FUNCPOINT_CDP_RDMA_ig__last_slice_stall__2_COV : cover property (CDP_RDMA_ig__last_slice_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__channnel_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_c & (~dma_rd_req_rdy); + endproperty +// Cover 3 : "is_last_c & (~dma_rd_req_rdy)" + FUNCPOINT_CDP_RDMA_ig__channnel_end_stall__3_COV : cover property (CDP_RDMA_ig__channnel_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__ig2eg_stall__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cq_wr_pvld) && nvdla_core_rstn) |-> ((~cq_wr_prdy & reg2dp_op_en)); + endproperty +// Cover 4 : "(~cq_wr_prdy & reg2dp_op_en)" + FUNCPOINT_CDP_RDMA_ig__ig2eg_stall__4_COV : cover property (CDP_RDMA_ig__ig2eg_stall__4_cov); + `endif +`endif +//VCS coverage on +//two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_two_continuous_layer__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 5 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_CDP_RDMA_two_continuous_layer__5_COV : cover property (CDP_RDMA_two_continuous_layer__5_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +//============== +// Context Queue Interface +//============== +endmodule // NV_NVDLA_CDP_RDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v.vcp new file mode 100644 index 0000000..5ca684d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v.vcp @@ -0,0 +1,1043 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_ig.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp2mcif_rd_req_ready //|< i + ,cq_wr_prdy //|< i + ,eg2ig_done //|< i + ,reg2dp_channel //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_height //|< i + ,reg2dp_input_data //|< i + ,reg2dp_op_en //|< i + ,reg2dp_src_base_addr_high //|< i + ,reg2dp_src_base_addr_low //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_src_surface_stride //|< i + ,reg2dp_width //|< i + ,cdp2mcif_rd_req_pd //|> o + ,cdp2mcif_rd_req_valid //|> o + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,dp2reg_d0_perf_read_stall //|> o + ,dp2reg_d1_perf_read_stall //|> o + ); +////////////////////////////////////////////////////////////////////////////////// +input [12:0] reg2dp_channel; +input reg2dp_dma_en; +input [12:0] reg2dp_height; +input [1:0] reg2dp_input_data; +input reg2dp_op_en; +input [31:0] reg2dp_src_base_addr_high; +input [31:0] reg2dp_src_base_addr_low; +input [31:0] reg2dp_src_line_stride; +input reg2dp_src_ram_type; +input [31:0] reg2dp_src_surface_stride; +input [12:0] reg2dp_width; +output [31:0] dp2reg_d0_perf_read_stall; +output [31:0] dp2reg_d1_perf_read_stall; +input eg2ig_done; +// +input nvdla_core_clk; +input nvdla_core_rstn; +output cdp2mcif_rd_req_valid; /* data valid */ +input cdp2mcif_rd_req_ready; /* data return handshake */ +output [47 -1:0] cdp2mcif_rd_req_pd; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [6:0] cq_wr_pd; +////////////////////////////////////////////////////////////////////////////////// +reg after_op_done; +reg [63:0] base_addr_c; +reg [63:0] base_addr_w; +reg [31:0] cdp_rd_stall_count; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: reg [12-${k}:0] channel_count; +//: ); +reg [63:0] dma_req_addr; +reg [31:0] dp2reg_d0_perf_read_stall; +reg [31:0] dp2reg_d1_perf_read_stall; +reg [12:0] height_count; +reg layer_flag; +reg mon_base_addr_c_c; +reg mon_base_addr_w_c; +reg mon_dma_req_addr_c; +reg [31:0] mon_gap_between_layers; +reg mon_layer_end_flg; +reg mon_op_en_dly; +reg mon_size_of_32x1_in_first_block_in_width_c; +wire [10:0] number_of_total_trans_in_width; +reg [2:0] req_size; +reg [2:0] size_of_32x1_in_first_block_in_width; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg tran_vld; +reg [10:0] width_count; +wire cdp_rd_stall_count_dec; +wire cmd_accept; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +wire cv_dma_rd_req_rdy; +wire cv_dma_rd_req_vld; +wire [78:0] cv_int_rd_req_pd; +wire [78:0] cv_int_rd_req_pd_d0; +wire cv_int_rd_req_ready; +wire cv_int_rd_req_ready_d0; +wire cv_int_rd_req_valid; +wire cv_int_rd_req_valid_d0; +wire cv_rd_req_rdyi; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_ram_type; +wire dma_rd_req_rdy; +wire dma_rd_req_vld; +wire [14:0] dma_req_size; +wire ig2eg_align; +wire ig2eg_last_c; +wire ig2eg_last_h; +wire ig2eg_last_w; +wire [14:0] ig2eg_width; +wire is_chn_end; +wire is_cube_end; +wire is_first_w; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_slice_end; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire mc_rd_req_rdyi; +wire mon_number_of_32x1_block_in_channel_c; +wire mon_op_en_neg; +wire mon_op_en_pos; +wire op_done; +wire op_load; +wire rd_req_rdyi; +wire [63:0] reg2dp_base_addr; +wire [31:0] reg2dp_line_stride; +wire [63:0] reg2dp_src_base_addr; +wire [31:0] reg2dp_surf_stride; +wire [13:0] reg2dp_width_use; +wire [2:0] size_of_32x1_in_last_block_in_width; +wire [2:0] width_size; +wire [3:0] width_size_use; +//////////////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +// one bubble between operation on two layers to let ARREG to switch to the next configration group +assign op_load = reg2dp_op_en & !tran_vld; +assign op_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_vld <= 1'b0; + end else begin + if (op_done) begin + tran_vld <= 1'b0; + end else if (after_op_done) begin + tran_vld <= 1'b0; + end else if (op_load) begin + tran_vld <= 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + after_op_done <= 1'b0; + end else begin + if (op_done) begin + after_op_done <= 1'b1; + end else if (eg2ig_done) begin + after_op_done <= 1'b0; + end + end +end +//NOTE!!! assert begin +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !tran_vld && op_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//NOTE!!! assert end +//============== +// Address catenate and offset calc +//============== +assign reg2dp_src_base_addr = {reg2dp_src_base_addr_high,reg2dp_src_base_addr_low}; +assign reg2dp_width_use[13:0] = reg2dp_width + 1'b1; +//============== +//============== +// WIDTH Direction +// calculate how many atomic_m x8 blocks in width direction, also get the first and last block, which may be less than 8 +//============== +wire mon_number_of_total_trans_in_width; +assign {mon_number_of_total_trans_in_width,number_of_total_trans_in_width[10:0]} = reg2dp_width_use[13:3] + {10'd0,(|reg2dp_width_use[2:0])}; +//============== +// Positioning +//============== +assign is_first_w = (width_count==0); +assign is_chn_end = is_last_c; +assign is_slice_end = is_last_w & is_last_c; +assign is_cube_end = is_last_w & is_last_h & is_last_c; +//============== +// CHANNEL Count: with inital value of total number in C direction, and will count-- when moving in chn direction +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_count <= 0; + end else begin + if (cmd_accept) begin + if (is_last_c) begin + channel_count <= 0; + end else begin + channel_count <= channel_count + 1'b1; + end + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign is_last_c = (channel_count==reg2dp_channel[12:${k}]); +//: ); +// assign is_last_c = (channel_count==number_of_block_in_channel-1); +//============== +// WID Count: with inital value of total number in W direction, and will count-- when moving in wid direction +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_count <= {11{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_slice_end) begin + width_count <= 0; + end else if (is_chn_end) begin + width_count <= width_count + 1'b1; + end + end + end +end +assign is_last_w = (width_count==number_of_total_trans_in_width-1); +//============== +// HEIGHT Count: move to next line after one wx1xc plane done +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + height_count <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_cube_end) begin + height_count <= 0; + end else if (is_slice_end) begin + height_count <= height_count + 1'b1; + end + end + end +end +assign is_last_h = (height_count==reg2dp_height); +//========================================== +// DMA: addr | size +//========================================== +assign reg2dp_base_addr = reg2dp_src_base_addr; +assign reg2dp_line_stride = reg2dp_src_line_stride; +assign reg2dp_surf_stride = reg2dp_src_surface_stride; +//============== +// DMA Req : ADDR : Prepration +// DMA Req: go through the CUBE: W8->C->H +//============== +// Width: need be updated when move to next line +// Trigger Condition: (is_last_c & is_last_w) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_w <= {64{1'b0}}; + {mon_base_addr_w_c,base_addr_w} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_w <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c && is_last_w) begin + {mon_base_addr_w_c,base_addr_w} <= base_addr_w + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_w_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// base_Chn: need be updated when move to next w.group +// Trigger Condition: (is_last_c) +// 1, jump to next line when is_last_w +// 2, jump to next w.group when !is_last_w +assign width_size_use[3:0] = width_size + 1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_c <= {64{1'b0}}; + {mon_base_addr_c_c,base_addr_c} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_c <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_base_addr_c_c,base_addr_c} <= base_addr_w + reg2dp_line_stride; + end else begin +//: my $atm = 8; +//: my $atmbw = int(log($atm)/log(2)); +//: print " {mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,${atmbw}'d0}; \n"; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_c_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : ADDR : Generation +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_req_addr <= {64{1'b0}}; + {mon_dma_req_addr_c,dma_req_addr} <= {65{1'b0}}; + end else begin + if (op_load) begin + dma_req_addr <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_dma_req_addr_c,dma_req_addr} <= base_addr_w + reg2dp_line_stride; + end else begin +//: my $atm = 8; +//: my $atmbw = int(log($atm)/log(2)); +//: print " {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,${atmbw}'d0}; \n"; + end + end else begin + {mon_dma_req_addr_c,dma_req_addr} <= dma_req_addr + reg2dp_surf_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_dma_req_addr_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////============== +// DMA Req : SIZE : Prepration +//============== +// if there is only trans in total width, this one will be counted into the first trans, so is_first_w should take prior to is_last_w +always @(*) begin + mon_size_of_32x1_in_first_block_in_width_c = 1'b0; + if (number_of_total_trans_in_width==1) begin + size_of_32x1_in_first_block_in_width[2:0] = reg2dp_width[2:0]; + end else begin + {mon_size_of_32x1_in_first_block_in_width_c,size_of_32x1_in_first_block_in_width[2:0]} = 3'd7; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & mon_size_of_32x1_in_first_block_in_width_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// when there is no L trans, still need calc the size for last trans which belongs to middle trans +// end_addr: 0 1 2 3 4 5 6 7 +// size : 0 1 2 3 4 5 6 7 +assign size_of_32x1_in_last_block_in_width[2:0] = reg2dp_width[2:0]; +//============== +// DMA Req : SIZE : Generation +//============== +always @(*) begin + if (is_first_w) begin + req_size = size_of_32x1_in_first_block_in_width; + end else if (is_last_w) begin + req_size = size_of_32x1_in_last_block_in_width; + end else begin + req_size = 3'd7; + end +end +assign width_size = req_size; // 1~8 +assign dma_req_size = {{12{1'b0}}, req_size}; +//============== +// Context Qeueu : Beats +//============== +//assign dma_req_align = (dma_req_addr[5]==0); +assign ig2eg_width = dma_req_size; +assign ig2eg_align = 1'b0;//dma_req_align; +assign ig2eg_last_w = is_last_w; +assign ig2eg_last_h = is_last_h; +assign ig2eg_last_c = is_last_c; +assign cq_wr_pd[2:0] = ig2eg_width[2:0]; +assign cq_wr_pd[3] = ig2eg_align ; +assign cq_wr_pd[4] = ig2eg_last_w ; +assign cq_wr_pd[5] = ig2eg_last_h ; +assign cq_wr_pd[6] = ig2eg_last_c ; +assign cq_wr_pvld = tran_vld & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (cq_wr_pvld & cq_wr_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = tran_vld & cq_wr_prdy; +// PayLoad +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_req_size[14:0]; +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// reading stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = is_cube_end & cmd_accept; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_rd_req_vld & (~dma_rd_req_rdy)); + assign cdp_rd_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or cdp_rd_stall_count_dec + ) begin + stl_adv = cnt_inc ^ cdp_rd_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or cdp_rd_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !cdp_rd_stall_count_dec)? stl_cnt_inc : (!cnt_inc && cdp_rd_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + cdp_rd_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; +// VCS coverage off + end else if ((cnt_clr) == 1'b0) begin + end else begin + layer_flag <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_read_stall <= cdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & (~layer_flag)) == 1'b0) begin + end else begin + dp2reg_d0_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & (~layer_flag)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_read_stall <= cdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & layer_flag ) == 1'b0) begin + end else begin + dp2reg_d1_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & layer_flag ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Interface +//============== +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.mcif_rd_req_pd (cdp2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (cdp2mcif_rd_req_valid) + ,.mcif_rd_req_ready (cdp2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +////============== +////OBS signals +////============== +//assign obs_bus_cdp_rdma_proc_en = tran_vld; +//============== +//function point +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_RDMA_ig__dma_IF_reading_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (((dma_rd_req_vld)) && nvdla_core_rstn) |-> ((~dma_rd_req_rdy & reg2dp_op_en)); + endproperty +// Cover 0 : "(~dma_rd_req_rdy & reg2dp_op_en)" + FUNCPOINT_CDP_RDMA_ig__dma_IF_reading_stall__0_COV : cover property (CDP_RDMA_ig__dma_IF_reading_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__width_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_w & (~dma_rd_req_rdy); + endproperty +// Cover 1 : "is_last_w & (~dma_rd_req_rdy)" + FUNCPOINT_CDP_RDMA_ig__width_end_stall__1_COV : cover property (CDP_RDMA_ig__width_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__last_slice_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_h & (~dma_rd_req_rdy); + endproperty +// Cover 2 : "is_last_h & (~dma_rd_req_rdy)" + FUNCPOINT_CDP_RDMA_ig__last_slice_stall__2_COV : cover property (CDP_RDMA_ig__last_slice_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__channnel_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_c & (~dma_rd_req_rdy); + endproperty +// Cover 3 : "is_last_c & (~dma_rd_req_rdy)" + FUNCPOINT_CDP_RDMA_ig__channnel_end_stall__3_COV : cover property (CDP_RDMA_ig__channnel_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_ig__ig2eg_stall__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cq_wr_pvld) && nvdla_core_rstn) |-> ((~cq_wr_prdy & reg2dp_op_en)); + endproperty +// Cover 4 : "(~cq_wr_prdy & reg2dp_op_en)" + FUNCPOINT_CDP_RDMA_ig__ig2eg_stall__4_COV : cover property (CDP_RDMA_ig__ig2eg_stall__4_cov); + `endif +`endif +//VCS coverage on +//two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_RDMA_two_continuous_layer__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 5 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_CDP_RDMA_two_continuous_layer__5_COV : cover property (CDP_RDMA_two_continuous_layer__5_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +//============== +// Context Queue Interface +//============== +endmodule // NV_NVDLA_CDP_RDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v new file mode 100644 index 0000000..fa22e0c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v @@ -0,0 +1,696 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cdp_rdma_req_pd //|< i + ,csb2cdp_rdma_req_pvld //|< i + ,dp2reg_d0_perf_read_stall //|< i + ,dp2reg_d1_perf_read_stall //|< i + ,dp2reg_done //|< i + ,cdp_rdma2csb_resp_pd //|> o + ,cdp_rdma2csb_resp_valid //|> o + ,csb2cdp_rdma_req_prdy //|> o + ,reg2dp_channel //|> o + ,reg2dp_cya //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_height //|> o + ,reg2dp_input_data //|> o + ,reg2dp_op_en //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_ram_type //|> o + ,reg2dp_src_surface_stride //|> o + ,reg2dp_width //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cdp_rdma_req_pd; +input csb2cdp_rdma_req_pvld; +input [31:0] dp2reg_d0_perf_read_stall; +input [31:0] dp2reg_d1_perf_read_stall; +input dp2reg_done; +output [33:0] cdp_rdma2csb_resp_pd; +output cdp_rdma2csb_resp_valid; +output csb2cdp_rdma_req_prdy; +output [12:0] reg2dp_channel; +output [31:0] reg2dp_cya; +output reg2dp_dma_en; +output [12:0] reg2dp_height; +output [1:0] reg2dp_input_data; +output reg2dp_op_en; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output reg2dp_src_ram_type; +output [31:0] reg2dp_src_surface_stride; +output [12:0] reg2dp_width; +output slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [12:0] reg2dp_d0_channel; +wire [31:0] reg2dp_d0_cya; +wire reg2dp_d0_dma_en; +wire [12:0] reg2dp_d0_height; +wire [1:0] reg2dp_d0_input_data; +wire reg2dp_d0_op_en_trigger; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire reg2dp_d0_src_ram_type; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d0_width; +wire [12:0] reg2dp_d1_channel; +wire [31:0] reg2dp_d1_cya; +wire reg2dp_d1_dma_en; +wire [12:0] reg2dp_d1_height; +wire [1:0] reg2dp_d1_input_data; +wire reg2dp_d1_op_en_trigger; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire reg2dp_d1_src_ram_type; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [12:0] reg2dp_d1_width; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire slcg_op_en_d0; +reg [33:0] cdp_rdma2csb_resp_pd; +reg cdp_rdma2csb_resp_valid; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [12:0] reg2dp_channel; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_dma_en; +reg [12:0] reg2dp_height; +reg [1:0] reg2dp_input_data; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg reg2dp_src_ram_type; +reg [31:0] reg2dp_src_surface_stride; +reg [12:0] reg2dp_width; +reg [62:0] req_pd; +reg req_pvld; +reg slcg_op_en_d1; +reg slcg_op_en_d2; +reg slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CDP_RDMA_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CDP_RDMA_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.channel (reg2dp_d0_channel[12:0]) //|> w + ,.height (reg2dp_d0_height[12:0]) //|> w + ,.width (reg2dp_d0_width[12:0]) //|> w + ,.input_data (reg2dp_d0_input_data[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d0_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|< i + ); +NV_NVDLA_CDP_RDMA_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.channel (reg2dp_d1_channel[12:0]) //|> w + ,.height (reg2dp_d1_height[12:0]) //|> w + ,.width (reg2dp_d1_width[12:0]) //|> w + ,.input_data (reg2dp_d1_input_data[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d1_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {1{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= 1'b0; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= 1'b0; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= 1'b0; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'he008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'he008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'he008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cdp_rdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cdp_rdma_req_pvld) == 1'b1) begin + req_pd <= csb2cdp_rdma_req_pd; +// VCS coverage off + end else if ((csb2cdp_rdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cdp_rdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cdp_rdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cdp_rdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cdp_rdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma2csb_resp_valid <= 1'b0; + end else begin + cdp_rdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_channel + or reg2dp_d0_channel + ) begin + reg2dp_channel = dp2reg_consumer ? reg2dp_d1_channel : reg2dp_d0_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_height + or reg2dp_d0_height + ) begin + reg2dp_height = dp2reg_consumer ? reg2dp_d1_height : reg2dp_d0_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_width + or reg2dp_d0_width + ) begin + reg2dp_width = dp2reg_consumer ? reg2dp_d1_width : reg2dp_d0_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data + or reg2dp_d0_input_data + ) begin + reg2dp_input_data = dp2reg_consumer ? reg2dp_d1_input_data : reg2dp_d0_input_data; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_ram_type + or reg2dp_d0_src_ram_type + ) begin + reg2dp_src_ram_type = dp2reg_consumer ? reg2dp_d1_src_ram_type : reg2dp_d0_src_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_CDP_RDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v.vcp new file mode 100644 index 0000000..fa22e0c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v.vcp @@ -0,0 +1,696 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_RDMA_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_RDMA_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cdp_rdma_req_pd //|< i + ,csb2cdp_rdma_req_pvld //|< i + ,dp2reg_d0_perf_read_stall //|< i + ,dp2reg_d1_perf_read_stall //|< i + ,dp2reg_done //|< i + ,cdp_rdma2csb_resp_pd //|> o + ,cdp_rdma2csb_resp_valid //|> o + ,csb2cdp_rdma_req_prdy //|> o + ,reg2dp_channel //|> o + ,reg2dp_cya //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_height //|> o + ,reg2dp_input_data //|> o + ,reg2dp_op_en //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_ram_type //|> o + ,reg2dp_src_surface_stride //|> o + ,reg2dp_width //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cdp_rdma_req_pd; +input csb2cdp_rdma_req_pvld; +input [31:0] dp2reg_d0_perf_read_stall; +input [31:0] dp2reg_d1_perf_read_stall; +input dp2reg_done; +output [33:0] cdp_rdma2csb_resp_pd; +output cdp_rdma2csb_resp_valid; +output csb2cdp_rdma_req_prdy; +output [12:0] reg2dp_channel; +output [31:0] reg2dp_cya; +output reg2dp_dma_en; +output [12:0] reg2dp_height; +output [1:0] reg2dp_input_data; +output reg2dp_op_en; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output reg2dp_src_ram_type; +output [31:0] reg2dp_src_surface_stride; +output [12:0] reg2dp_width; +output slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [12:0] reg2dp_d0_channel; +wire [31:0] reg2dp_d0_cya; +wire reg2dp_d0_dma_en; +wire [12:0] reg2dp_d0_height; +wire [1:0] reg2dp_d0_input_data; +wire reg2dp_d0_op_en_trigger; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire reg2dp_d0_src_ram_type; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d0_width; +wire [12:0] reg2dp_d1_channel; +wire [31:0] reg2dp_d1_cya; +wire reg2dp_d1_dma_en; +wire [12:0] reg2dp_d1_height; +wire [1:0] reg2dp_d1_input_data; +wire reg2dp_d1_op_en_trigger; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire reg2dp_d1_src_ram_type; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [12:0] reg2dp_d1_width; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire slcg_op_en_d0; +reg [33:0] cdp_rdma2csb_resp_pd; +reg cdp_rdma2csb_resp_valid; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [12:0] reg2dp_channel; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_dma_en; +reg [12:0] reg2dp_height; +reg [1:0] reg2dp_input_data; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg reg2dp_src_ram_type; +reg [31:0] reg2dp_src_surface_stride; +reg [12:0] reg2dp_width; +reg [62:0] req_pd; +reg req_pvld; +reg slcg_op_en_d1; +reg slcg_op_en_d2; +reg slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CDP_RDMA_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CDP_RDMA_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.channel (reg2dp_d0_channel[12:0]) //|> w + ,.height (reg2dp_d0_height[12:0]) //|> w + ,.width (reg2dp_d0_width[12:0]) //|> w + ,.input_data (reg2dp_d0_input_data[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d0_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|< i + ); +NV_NVDLA_CDP_RDMA_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.channel (reg2dp_d1_channel[12:0]) //|> w + ,.height (reg2dp_d1_height[12:0]) //|> w + ,.width (reg2dp_d1_width[12:0]) //|> w + ,.input_data (reg2dp_d1_input_data[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d1_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {1{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= 1'b0; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= 1'b0; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= 1'b0; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'he008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'he008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'he008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cdp_rdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cdp_rdma_req_pvld) == 1'b1) begin + req_pd <= csb2cdp_rdma_req_pd; +// VCS coverage off + end else if ((csb2cdp_rdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cdp_rdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cdp_rdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cdp_rdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cdp_rdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma2csb_resp_valid <= 1'b0; + end else begin + cdp_rdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_channel + or reg2dp_d0_channel + ) begin + reg2dp_channel = dp2reg_consumer ? reg2dp_d1_channel : reg2dp_d0_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_height + or reg2dp_d0_height + ) begin + reg2dp_height = dp2reg_consumer ? reg2dp_d1_height : reg2dp_d0_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_width + or reg2dp_d0_width + ) begin + reg2dp_width = dp2reg_consumer ? reg2dp_d1_width : reg2dp_d0_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data + or reg2dp_d0_input_data + ) begin + reg2dp_input_data = dp2reg_consumer ? reg2dp_d1_input_data : reg2dp_d0_input_data; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_ram_type + or reg2dp_d0_src_ram_type + ) begin + reg2dp_src_ram_type = dp2reg_consumer ? reg2dp_d1_src_ram_type : reg2dp_d0_src_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_CDP_RDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v new file mode 100644 index 0000000..3789f0d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v @@ -0,0 +1,541 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_REG_dual.v +module NV_NVDLA_CDP_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,input_data_type + ,datin_offset + ,datin_scale + ,datin_shifter + ,datout_offset + ,datout_scale + ,datout_shifter + ,dst_base_addr_high + ,dst_base_addr_low + ,dst_ram_type + ,dst_line_stride + ,dst_surface_stride + ,mul_bypass + ,sqsum_bypass + ,normalz_len + ,nan_to_zero + ,op_en_trigger + ,dma_en + ,lut_en + ,inf_input_num + ,nan_input_num + ,nan_output_num + ,op_en + ,out_saturation + ,perf_lut_hybrid + ,perf_lut_le_hit + ,perf_lut_lo_hit + ,perf_lut_oflow + ,perf_lut_uflow + ,perf_write_stall + ); +wire dst_compression_en; +wire [31:0] nvdla_cdp_d_cya_0_out; +wire [31:0] nvdla_cdp_d_data_format_0_out; +wire [31:0] nvdla_cdp_d_datin_offset_0_out; +wire [31:0] nvdla_cdp_d_datin_scale_0_out; +wire [31:0] nvdla_cdp_d_datin_shifter_0_out; +wire [31:0] nvdla_cdp_d_datout_offset_0_out; +wire [31:0] nvdla_cdp_d_datout_scale_0_out; +wire [31:0] nvdla_cdp_d_datout_shifter_0_out; +wire [31:0] nvdla_cdp_d_dst_base_addr_high_0_out; +wire [31:0] nvdla_cdp_d_dst_base_addr_low_0_out; +wire [31:0] nvdla_cdp_d_dst_compression_en_0_out; +wire [31:0] nvdla_cdp_d_dst_dma_cfg_0_out; +wire [31:0] nvdla_cdp_d_dst_line_stride_0_out; +wire [31:0] nvdla_cdp_d_dst_surface_stride_0_out; +wire [31:0] nvdla_cdp_d_func_bypass_0_out; +wire [31:0] nvdla_cdp_d_inf_input_num_0_out; +wire [31:0] nvdla_cdp_d_lrn_cfg_0_out; +wire [31:0] nvdla_cdp_d_nan_flush_to_zero_0_out; +wire [31:0] nvdla_cdp_d_nan_input_num_0_out; +wire [31:0] nvdla_cdp_d_nan_output_num_0_out; +wire [31:0] nvdla_cdp_d_op_enable_0_out; +wire [31:0] nvdla_cdp_d_out_saturation_0_out; +wire [31:0] nvdla_cdp_d_perf_enable_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_hybrid_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_le_hit_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_lo_hit_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_oflow_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_uflow_0_out; +wire [31:0] nvdla_cdp_d_perf_write_stall_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [1:0] input_data_type; +output [15:0] datin_offset; +output [15:0] datin_scale; +output [4:0] datin_shifter; +output [31:0] datout_offset; +output [15:0] datout_scale; +output [5:0] datout_shifter; +output [31:0] dst_base_addr_high; +output [31:0] dst_base_addr_low; +output dst_ram_type; +output [31:0] dst_line_stride; +output [31:0] dst_surface_stride; +output mul_bypass; +output sqsum_bypass; +output [1:0] normalz_len; +output nan_to_zero; +output op_en_trigger; +output dma_en; +output lut_en; +// Read-only register inputs +input [31:0] inf_input_num; +input [31:0] nan_input_num; +input [31:0] nan_output_num; +input op_en; +input [31:0] out_saturation; +input [31:0] perf_lut_hybrid; +input [31:0] perf_lut_le_hit; +input [31:0] perf_lut_lo_hit; +input [31:0] perf_lut_oflow; +input [31:0] perf_lut_uflow; +input [31:0] perf_write_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [31:0] cya; +reg [15:0] datin_offset; +reg [15:0] datin_scale; +reg [4:0] datin_shifter; +reg [31:0] datout_offset; +reg [15:0] datout_scale; +reg [5:0] datout_shifter; +reg dma_en; +reg [31:0] dst_base_addr_high; +reg [31:0] dst_base_addr_low; +reg [31:0] dst_line_stride; +reg dst_ram_type; +reg [31:0] dst_surface_stride; +reg [1:0] input_data_type; +reg lut_en; +reg mul_bypass; +reg nan_to_zero; +reg [1:0] normalz_len; +reg [31:0] reg_rd_data; +reg sqsum_bypass; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_d_cya_0_wren = (reg_offset_wr == (32'hf0b8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_data_format_0_wren = (reg_offset_wr == (32'hf068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datin_offset_0_wren = (reg_offset_wr == (32'hf074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datin_scale_0_wren = (reg_offset_wr == (32'hf078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datin_shifter_0_wren = (reg_offset_wr == (32'hf07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datout_offset_0_wren = (reg_offset_wr == (32'hf080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datout_scale_0_wren = (reg_offset_wr == (32'hf084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datout_shifter_0_wren = (reg_offset_wr == (32'hf088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_base_addr_high_0_wren = (reg_offset_wr == (32'hf054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_base_addr_low_0_wren = (reg_offset_wr == (32'hf050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_compression_en_0_wren = (reg_offset_wr == (32'hf064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_dma_cfg_0_wren = (reg_offset_wr == (32'hf060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_line_stride_0_wren = (reg_offset_wr == (32'hf058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_surface_stride_0_wren = (reg_offset_wr == (32'hf05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_func_bypass_0_wren = (reg_offset_wr == (32'hf04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_inf_input_num_0_wren = (reg_offset_wr == (32'hf090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_lrn_cfg_0_wren = (reg_offset_wr == (32'hf070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_nan_flush_to_zero_0_wren = (reg_offset_wr == (32'hf06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_nan_input_num_0_wren = (reg_offset_wr == (32'hf08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_nan_output_num_0_wren = (reg_offset_wr == (32'hf094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_op_enable_0_wren = (reg_offset_wr == (32'hf048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_out_saturation_0_wren = (reg_offset_wr == (32'hf098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_enable_0_wren = (reg_offset_wr == (32'hf09c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_hybrid_0_wren = (reg_offset_wr == (32'hf0ac & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_le_hit_0_wren = (reg_offset_wr == (32'hf0b0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_lo_hit_0_wren = (reg_offset_wr == (32'hf0b4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_oflow_0_wren = (reg_offset_wr == (32'hf0a8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_uflow_0_wren = (reg_offset_wr == (32'hf0a4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_write_stall_0_wren = (reg_offset_wr == (32'hf0a0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign dst_compression_en = 1'h0; +assign nvdla_cdp_d_cya_0_out[31:0] = { cya }; +assign nvdla_cdp_d_data_format_0_out[31:0] = { 30'b0, input_data_type }; +assign nvdla_cdp_d_datin_offset_0_out[31:0] = { 16'b0, datin_offset }; +assign nvdla_cdp_d_datin_scale_0_out[31:0] = { 16'b0, datin_scale }; +assign nvdla_cdp_d_datin_shifter_0_out[31:0] = { 27'b0, datin_shifter }; +assign nvdla_cdp_d_datout_offset_0_out[31:0] = { datout_offset }; +assign nvdla_cdp_d_datout_scale_0_out[31:0] = { 16'b0, datout_scale }; +assign nvdla_cdp_d_datout_shifter_0_out[31:0] = { 26'b0, datout_shifter }; +assign nvdla_cdp_d_dst_base_addr_high_0_out[31:0] = { dst_base_addr_high }; +assign nvdla_cdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low }; +assign nvdla_cdp_d_dst_compression_en_0_out[31:0] = { 31'b0, dst_compression_en }; +assign nvdla_cdp_d_dst_dma_cfg_0_out[31:0] = { 31'b0, dst_ram_type }; +assign nvdla_cdp_d_dst_line_stride_0_out[31:0] = { dst_line_stride }; +assign nvdla_cdp_d_dst_surface_stride_0_out[31:0] = { dst_surface_stride }; +assign nvdla_cdp_d_func_bypass_0_out[31:0] = { 30'b0, mul_bypass, sqsum_bypass }; +assign nvdla_cdp_d_inf_input_num_0_out[31:0] = { inf_input_num }; +assign nvdla_cdp_d_lrn_cfg_0_out[31:0] = { 30'b0, normalz_len }; +assign nvdla_cdp_d_nan_flush_to_zero_0_out[31:0] = { 31'b0, nan_to_zero }; +assign nvdla_cdp_d_nan_input_num_0_out[31:0] = { nan_input_num }; +assign nvdla_cdp_d_nan_output_num_0_out[31:0] = { nan_output_num }; +assign nvdla_cdp_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cdp_d_out_saturation_0_out[31:0] = { out_saturation }; +assign nvdla_cdp_d_perf_enable_0_out[31:0] = { 30'b0, lut_en, dma_en }; +assign nvdla_cdp_d_perf_lut_hybrid_0_out[31:0] = { perf_lut_hybrid }; +assign nvdla_cdp_d_perf_lut_le_hit_0_out[31:0] = { perf_lut_le_hit }; +assign nvdla_cdp_d_perf_lut_lo_hit_0_out[31:0] = { perf_lut_lo_hit }; +assign nvdla_cdp_d_perf_lut_oflow_0_out[31:0] = { perf_lut_oflow }; +assign nvdla_cdp_d_perf_lut_uflow_0_out[31:0] = { perf_lut_uflow }; +assign nvdla_cdp_d_perf_write_stall_0_out[31:0] = { perf_write_stall }; +assign op_en_trigger = nvdla_cdp_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_d_cya_0_out + or nvdla_cdp_d_data_format_0_out + or nvdla_cdp_d_datin_offset_0_out + or nvdla_cdp_d_datin_scale_0_out + or nvdla_cdp_d_datin_shifter_0_out + or nvdla_cdp_d_datout_offset_0_out + or nvdla_cdp_d_datout_scale_0_out + or nvdla_cdp_d_datout_shifter_0_out + or nvdla_cdp_d_dst_base_addr_high_0_out + or nvdla_cdp_d_dst_base_addr_low_0_out + or nvdla_cdp_d_dst_compression_en_0_out + or nvdla_cdp_d_dst_dma_cfg_0_out + or nvdla_cdp_d_dst_line_stride_0_out + or nvdla_cdp_d_dst_surface_stride_0_out + or nvdla_cdp_d_func_bypass_0_out + or nvdla_cdp_d_inf_input_num_0_out + or nvdla_cdp_d_lrn_cfg_0_out + or nvdla_cdp_d_nan_flush_to_zero_0_out + or nvdla_cdp_d_nan_input_num_0_out + or nvdla_cdp_d_nan_output_num_0_out + or nvdla_cdp_d_op_enable_0_out + or nvdla_cdp_d_out_saturation_0_out + or nvdla_cdp_d_perf_enable_0_out + or nvdla_cdp_d_perf_lut_hybrid_0_out + or nvdla_cdp_d_perf_lut_le_hit_0_out + or nvdla_cdp_d_perf_lut_lo_hit_0_out + or nvdla_cdp_d_perf_lut_oflow_0_out + or nvdla_cdp_d_perf_lut_uflow_0_out + or nvdla_cdp_d_perf_write_stall_0_out + ) begin + case (reg_offset_rd_int) + (32'hf0b8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_cya_0_out ; + end + (32'hf068 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_data_format_0_out ; + end + (32'hf074 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datin_offset_0_out ; + end + (32'hf078 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datin_scale_0_out ; + end + (32'hf07c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datin_shifter_0_out ; + end + (32'hf080 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datout_offset_0_out ; + end + (32'hf084 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datout_scale_0_out ; + end + (32'hf088 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datout_shifter_0_out ; + end + (32'hf054 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_base_addr_high_0_out ; + end + (32'hf050 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_base_addr_low_0_out ; + end + (32'hf064 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_compression_en_0_out ; + end + (32'hf060 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_dma_cfg_0_out ; + end + (32'hf058 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_line_stride_0_out ; + end + (32'hf05c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_surface_stride_0_out ; + end + (32'hf04c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_func_bypass_0_out ; + end + (32'hf090 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_inf_input_num_0_out ; + end + (32'hf070 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_lrn_cfg_0_out ; + end + (32'hf06c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_nan_flush_to_zero_0_out ; + end + (32'hf08c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_nan_input_num_0_out ; + end + (32'hf094 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_nan_output_num_0_out ; + end + (32'hf048 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_op_enable_0_out ; + end + (32'hf098 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_out_saturation_0_out ; + end + (32'hf09c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_enable_0_out ; + end + (32'hf0ac & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_hybrid_0_out ; + end + (32'hf0b0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_le_hit_0_out ; + end + (32'hf0b4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_lo_hit_0_out ; + end + (32'hf0a8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_oflow_0_out ; + end + (32'hf0a4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_uflow_0_out ; + end + (32'hf0a0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_write_stall_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + input_data_type[1:0] <= 2'b01; + datin_offset[15:0] <= 16'b0000000000000000; + datin_scale[15:0] <= 16'b0000000000000001; + datin_shifter[4:0] <= 5'b00000; + datout_offset[31:0] <= 32'b00000000000000000000000000000000; + datout_scale[15:0] <= 16'b0000000000000001; + datout_shifter[5:0] <= 6'b000000; + dst_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + dst_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + dst_ram_type <= 1'b0; + dst_line_stride[31:0] <= 32'b00000000000000000000000000000000; + dst_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + mul_bypass <= 1'b0; + sqsum_bypass <= 1'b0; + normalz_len[1:0] <= 2'b00; + nan_to_zero <= 1'b0; + dma_en <= 1'b0; + lut_en <= 1'b0; + end else begin +// Register: NVDLA_CDP_D_CYA_0 Field: cya + if (nvdla_cdp_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DATA_FORMAT_0 Field: input_data_type + if (nvdla_cdp_d_data_format_0_wren) begin + input_data_type[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CDP_D_DATIN_OFFSET_0 Field: datin_offset + if (nvdla_cdp_d_datin_offset_0_wren) begin + datin_offset[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_D_DATIN_SCALE_0 Field: datin_scale + if (nvdla_cdp_d_datin_scale_0_wren) begin + datin_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_D_DATIN_SHIFTER_0 Field: datin_shifter + if (nvdla_cdp_d_datin_shifter_0_wren) begin + datin_shifter[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDP_D_DATOUT_OFFSET_0 Field: datout_offset + if (nvdla_cdp_d_datout_offset_0_wren) begin + datout_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DATOUT_SCALE_0 Field: datout_scale + if (nvdla_cdp_d_datout_scale_0_wren) begin + datout_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_D_DATOUT_SHIFTER_0 Field: datout_shifter + if (nvdla_cdp_d_datout_shifter_0_wren) begin + datout_shifter[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_D_DST_BASE_ADDR_HIGH_0 Field: dst_base_addr_high + if (nvdla_cdp_d_dst_base_addr_high_0_wren) begin + dst_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DST_BASE_ADDR_LOW_0 Field: dst_base_addr_low + if (nvdla_cdp_d_dst_base_addr_low_0_wren) begin + dst_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for constant field NVDLA_CDP_D_DST_COMPRESSION_EN_0::dst_compression_en +// Register: NVDLA_CDP_D_DST_DMA_CFG_0 Field: dst_ram_type + if (nvdla_cdp_d_dst_dma_cfg_0_wren) begin + dst_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_D_DST_LINE_STRIDE_0 Field: dst_line_stride + if (nvdla_cdp_d_dst_line_stride_0_wren) begin + dst_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DST_SURFACE_STRIDE_0 Field: dst_surface_stride + if (nvdla_cdp_d_dst_surface_stride_0_wren) begin + dst_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_FUNC_BYPASS_0 Field: mul_bypass + if (nvdla_cdp_d_func_bypass_0_wren) begin + mul_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_CDP_D_FUNC_BYPASS_0 Field: sqsum_bypass + if (nvdla_cdp_d_func_bypass_0_wren) begin + sqsum_bypass <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_D_INF_INPUT_NUM_0::inf_input_num +// Register: NVDLA_CDP_D_LRN_CFG_0 Field: normalz_len + if (nvdla_cdp_d_lrn_cfg_0_wren) begin + normalz_len[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CDP_D_NAN_FLUSH_TO_ZERO_0 Field: nan_to_zero + if (nvdla_cdp_d_nan_flush_to_zero_0_wren) begin + nan_to_zero <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_D_NAN_INPUT_NUM_0::nan_input_num +// Not generating flops for read-only field NVDLA_CDP_D_NAN_OUTPUT_NUM_0::nan_output_num +// Not generating flops for field NVDLA_CDP_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_CDP_D_OUT_SATURATION_0::out_saturation +// Register: NVDLA_CDP_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_cdp_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_D_PERF_ENABLE_0 Field: lut_en + if (nvdla_cdp_d_perf_enable_0_wren) begin + lut_en <= reg_wr_data[1]; + end +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_HYBRID_0::perf_lut_hybrid +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_LE_HIT_0::perf_lut_le_hit +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_LO_HIT_0::perf_lut_lo_hit +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_OFLOW_0::perf_lut_oflow +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_UFLOW_0::perf_lut_uflow +// Not generating flops for read-only field NVDLA_CDP_D_PERF_WRITE_STALL_0::perf_write_stall + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hf0b8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_cya_0_out, nvdla_cdp_d_cya_0_out); + (32'hf068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_data_format_0_out, nvdla_cdp_d_data_format_0_out); + (32'hf074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATIN_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datin_offset_0_out, nvdla_cdp_d_datin_offset_0_out); + (32'hf078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATIN_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datin_scale_0_out, nvdla_cdp_d_datin_scale_0_out); + (32'hf07c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATIN_SHIFTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datin_shifter_0_out, nvdla_cdp_d_datin_shifter_0_out); + (32'hf080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATOUT_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datout_offset_0_out, nvdla_cdp_d_datout_offset_0_out); + (32'hf084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATOUT_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datout_scale_0_out, nvdla_cdp_d_datout_scale_0_out); + (32'hf088 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATOUT_SHIFTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datout_shifter_0_out, nvdla_cdp_d_datout_shifter_0_out); + (32'hf054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_base_addr_high_0_out, nvdla_cdp_d_dst_base_addr_high_0_out); + (32'hf050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_base_addr_low_0_out, nvdla_cdp_d_dst_base_addr_low_0_out); + (32'hf064 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_DST_COMPRESSION_EN_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_dma_cfg_0_out, nvdla_cdp_d_dst_dma_cfg_0_out); + (32'hf058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_line_stride_0_out, nvdla_cdp_d_dst_line_stride_0_out); + (32'hf05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_surface_stride_0_out, nvdla_cdp_d_dst_surface_stride_0_out); + (32'hf04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_FUNC_BYPASS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_func_bypass_0_out, nvdla_cdp_d_func_bypass_0_out); + (32'hf090 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_LRN_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_lrn_cfg_0_out, nvdla_cdp_d_lrn_cfg_0_out); + (32'hf06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_NAN_FLUSH_TO_ZERO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_nan_flush_to_zero_0_out, nvdla_cdp_d_nan_flush_to_zero_0_out); + (32'hf08c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf094 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_NAN_OUTPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_op_enable_0_out, nvdla_cdp_d_op_enable_0_out); + (32'hf098 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_OUT_SATURATION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf09c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_perf_enable_0_out, nvdla_cdp_d_perf_enable_0_out); + (32'hf0ac & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_HYBRID_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0b0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_LE_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0b4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_LO_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0a8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_OFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0a4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_UFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0a0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v.vcp new file mode 100644 index 0000000..3789f0d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v.vcp @@ -0,0 +1,541 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_REG_dual.v +module NV_NVDLA_CDP_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,input_data_type + ,datin_offset + ,datin_scale + ,datin_shifter + ,datout_offset + ,datout_scale + ,datout_shifter + ,dst_base_addr_high + ,dst_base_addr_low + ,dst_ram_type + ,dst_line_stride + ,dst_surface_stride + ,mul_bypass + ,sqsum_bypass + ,normalz_len + ,nan_to_zero + ,op_en_trigger + ,dma_en + ,lut_en + ,inf_input_num + ,nan_input_num + ,nan_output_num + ,op_en + ,out_saturation + ,perf_lut_hybrid + ,perf_lut_le_hit + ,perf_lut_lo_hit + ,perf_lut_oflow + ,perf_lut_uflow + ,perf_write_stall + ); +wire dst_compression_en; +wire [31:0] nvdla_cdp_d_cya_0_out; +wire [31:0] nvdla_cdp_d_data_format_0_out; +wire [31:0] nvdla_cdp_d_datin_offset_0_out; +wire [31:0] nvdla_cdp_d_datin_scale_0_out; +wire [31:0] nvdla_cdp_d_datin_shifter_0_out; +wire [31:0] nvdla_cdp_d_datout_offset_0_out; +wire [31:0] nvdla_cdp_d_datout_scale_0_out; +wire [31:0] nvdla_cdp_d_datout_shifter_0_out; +wire [31:0] nvdla_cdp_d_dst_base_addr_high_0_out; +wire [31:0] nvdla_cdp_d_dst_base_addr_low_0_out; +wire [31:0] nvdla_cdp_d_dst_compression_en_0_out; +wire [31:0] nvdla_cdp_d_dst_dma_cfg_0_out; +wire [31:0] nvdla_cdp_d_dst_line_stride_0_out; +wire [31:0] nvdla_cdp_d_dst_surface_stride_0_out; +wire [31:0] nvdla_cdp_d_func_bypass_0_out; +wire [31:0] nvdla_cdp_d_inf_input_num_0_out; +wire [31:0] nvdla_cdp_d_lrn_cfg_0_out; +wire [31:0] nvdla_cdp_d_nan_flush_to_zero_0_out; +wire [31:0] nvdla_cdp_d_nan_input_num_0_out; +wire [31:0] nvdla_cdp_d_nan_output_num_0_out; +wire [31:0] nvdla_cdp_d_op_enable_0_out; +wire [31:0] nvdla_cdp_d_out_saturation_0_out; +wire [31:0] nvdla_cdp_d_perf_enable_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_hybrid_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_le_hit_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_lo_hit_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_oflow_0_out; +wire [31:0] nvdla_cdp_d_perf_lut_uflow_0_out; +wire [31:0] nvdla_cdp_d_perf_write_stall_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [1:0] input_data_type; +output [15:0] datin_offset; +output [15:0] datin_scale; +output [4:0] datin_shifter; +output [31:0] datout_offset; +output [15:0] datout_scale; +output [5:0] datout_shifter; +output [31:0] dst_base_addr_high; +output [31:0] dst_base_addr_low; +output dst_ram_type; +output [31:0] dst_line_stride; +output [31:0] dst_surface_stride; +output mul_bypass; +output sqsum_bypass; +output [1:0] normalz_len; +output nan_to_zero; +output op_en_trigger; +output dma_en; +output lut_en; +// Read-only register inputs +input [31:0] inf_input_num; +input [31:0] nan_input_num; +input [31:0] nan_output_num; +input op_en; +input [31:0] out_saturation; +input [31:0] perf_lut_hybrid; +input [31:0] perf_lut_le_hit; +input [31:0] perf_lut_lo_hit; +input [31:0] perf_lut_oflow; +input [31:0] perf_lut_uflow; +input [31:0] perf_write_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [31:0] cya; +reg [15:0] datin_offset; +reg [15:0] datin_scale; +reg [4:0] datin_shifter; +reg [31:0] datout_offset; +reg [15:0] datout_scale; +reg [5:0] datout_shifter; +reg dma_en; +reg [31:0] dst_base_addr_high; +reg [31:0] dst_base_addr_low; +reg [31:0] dst_line_stride; +reg dst_ram_type; +reg [31:0] dst_surface_stride; +reg [1:0] input_data_type; +reg lut_en; +reg mul_bypass; +reg nan_to_zero; +reg [1:0] normalz_len; +reg [31:0] reg_rd_data; +reg sqsum_bypass; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_d_cya_0_wren = (reg_offset_wr == (32'hf0b8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_data_format_0_wren = (reg_offset_wr == (32'hf068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datin_offset_0_wren = (reg_offset_wr == (32'hf074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datin_scale_0_wren = (reg_offset_wr == (32'hf078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datin_shifter_0_wren = (reg_offset_wr == (32'hf07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datout_offset_0_wren = (reg_offset_wr == (32'hf080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datout_scale_0_wren = (reg_offset_wr == (32'hf084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_datout_shifter_0_wren = (reg_offset_wr == (32'hf088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_base_addr_high_0_wren = (reg_offset_wr == (32'hf054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_base_addr_low_0_wren = (reg_offset_wr == (32'hf050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_compression_en_0_wren = (reg_offset_wr == (32'hf064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_dma_cfg_0_wren = (reg_offset_wr == (32'hf060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_line_stride_0_wren = (reg_offset_wr == (32'hf058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_dst_surface_stride_0_wren = (reg_offset_wr == (32'hf05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_func_bypass_0_wren = (reg_offset_wr == (32'hf04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_inf_input_num_0_wren = (reg_offset_wr == (32'hf090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_lrn_cfg_0_wren = (reg_offset_wr == (32'hf070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_nan_flush_to_zero_0_wren = (reg_offset_wr == (32'hf06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_nan_input_num_0_wren = (reg_offset_wr == (32'hf08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_nan_output_num_0_wren = (reg_offset_wr == (32'hf094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_op_enable_0_wren = (reg_offset_wr == (32'hf048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_out_saturation_0_wren = (reg_offset_wr == (32'hf098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_enable_0_wren = (reg_offset_wr == (32'hf09c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_hybrid_0_wren = (reg_offset_wr == (32'hf0ac & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_le_hit_0_wren = (reg_offset_wr == (32'hf0b0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_lo_hit_0_wren = (reg_offset_wr == (32'hf0b4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_oflow_0_wren = (reg_offset_wr == (32'hf0a8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_lut_uflow_0_wren = (reg_offset_wr == (32'hf0a4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_d_perf_write_stall_0_wren = (reg_offset_wr == (32'hf0a0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign dst_compression_en = 1'h0; +assign nvdla_cdp_d_cya_0_out[31:0] = { cya }; +assign nvdla_cdp_d_data_format_0_out[31:0] = { 30'b0, input_data_type }; +assign nvdla_cdp_d_datin_offset_0_out[31:0] = { 16'b0, datin_offset }; +assign nvdla_cdp_d_datin_scale_0_out[31:0] = { 16'b0, datin_scale }; +assign nvdla_cdp_d_datin_shifter_0_out[31:0] = { 27'b0, datin_shifter }; +assign nvdla_cdp_d_datout_offset_0_out[31:0] = { datout_offset }; +assign nvdla_cdp_d_datout_scale_0_out[31:0] = { 16'b0, datout_scale }; +assign nvdla_cdp_d_datout_shifter_0_out[31:0] = { 26'b0, datout_shifter }; +assign nvdla_cdp_d_dst_base_addr_high_0_out[31:0] = { dst_base_addr_high }; +assign nvdla_cdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low }; +assign nvdla_cdp_d_dst_compression_en_0_out[31:0] = { 31'b0, dst_compression_en }; +assign nvdla_cdp_d_dst_dma_cfg_0_out[31:0] = { 31'b0, dst_ram_type }; +assign nvdla_cdp_d_dst_line_stride_0_out[31:0] = { dst_line_stride }; +assign nvdla_cdp_d_dst_surface_stride_0_out[31:0] = { dst_surface_stride }; +assign nvdla_cdp_d_func_bypass_0_out[31:0] = { 30'b0, mul_bypass, sqsum_bypass }; +assign nvdla_cdp_d_inf_input_num_0_out[31:0] = { inf_input_num }; +assign nvdla_cdp_d_lrn_cfg_0_out[31:0] = { 30'b0, normalz_len }; +assign nvdla_cdp_d_nan_flush_to_zero_0_out[31:0] = { 31'b0, nan_to_zero }; +assign nvdla_cdp_d_nan_input_num_0_out[31:0] = { nan_input_num }; +assign nvdla_cdp_d_nan_output_num_0_out[31:0] = { nan_output_num }; +assign nvdla_cdp_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_cdp_d_out_saturation_0_out[31:0] = { out_saturation }; +assign nvdla_cdp_d_perf_enable_0_out[31:0] = { 30'b0, lut_en, dma_en }; +assign nvdla_cdp_d_perf_lut_hybrid_0_out[31:0] = { perf_lut_hybrid }; +assign nvdla_cdp_d_perf_lut_le_hit_0_out[31:0] = { perf_lut_le_hit }; +assign nvdla_cdp_d_perf_lut_lo_hit_0_out[31:0] = { perf_lut_lo_hit }; +assign nvdla_cdp_d_perf_lut_oflow_0_out[31:0] = { perf_lut_oflow }; +assign nvdla_cdp_d_perf_lut_uflow_0_out[31:0] = { perf_lut_uflow }; +assign nvdla_cdp_d_perf_write_stall_0_out[31:0] = { perf_write_stall }; +assign op_en_trigger = nvdla_cdp_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_d_cya_0_out + or nvdla_cdp_d_data_format_0_out + or nvdla_cdp_d_datin_offset_0_out + or nvdla_cdp_d_datin_scale_0_out + or nvdla_cdp_d_datin_shifter_0_out + or nvdla_cdp_d_datout_offset_0_out + or nvdla_cdp_d_datout_scale_0_out + or nvdla_cdp_d_datout_shifter_0_out + or nvdla_cdp_d_dst_base_addr_high_0_out + or nvdla_cdp_d_dst_base_addr_low_0_out + or nvdla_cdp_d_dst_compression_en_0_out + or nvdla_cdp_d_dst_dma_cfg_0_out + or nvdla_cdp_d_dst_line_stride_0_out + or nvdla_cdp_d_dst_surface_stride_0_out + or nvdla_cdp_d_func_bypass_0_out + or nvdla_cdp_d_inf_input_num_0_out + or nvdla_cdp_d_lrn_cfg_0_out + or nvdla_cdp_d_nan_flush_to_zero_0_out + or nvdla_cdp_d_nan_input_num_0_out + or nvdla_cdp_d_nan_output_num_0_out + or nvdla_cdp_d_op_enable_0_out + or nvdla_cdp_d_out_saturation_0_out + or nvdla_cdp_d_perf_enable_0_out + or nvdla_cdp_d_perf_lut_hybrid_0_out + or nvdla_cdp_d_perf_lut_le_hit_0_out + or nvdla_cdp_d_perf_lut_lo_hit_0_out + or nvdla_cdp_d_perf_lut_oflow_0_out + or nvdla_cdp_d_perf_lut_uflow_0_out + or nvdla_cdp_d_perf_write_stall_0_out + ) begin + case (reg_offset_rd_int) + (32'hf0b8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_cya_0_out ; + end + (32'hf068 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_data_format_0_out ; + end + (32'hf074 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datin_offset_0_out ; + end + (32'hf078 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datin_scale_0_out ; + end + (32'hf07c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datin_shifter_0_out ; + end + (32'hf080 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datout_offset_0_out ; + end + (32'hf084 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datout_scale_0_out ; + end + (32'hf088 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_datout_shifter_0_out ; + end + (32'hf054 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_base_addr_high_0_out ; + end + (32'hf050 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_base_addr_low_0_out ; + end + (32'hf064 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_compression_en_0_out ; + end + (32'hf060 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_dma_cfg_0_out ; + end + (32'hf058 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_line_stride_0_out ; + end + (32'hf05c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_dst_surface_stride_0_out ; + end + (32'hf04c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_func_bypass_0_out ; + end + (32'hf090 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_inf_input_num_0_out ; + end + (32'hf070 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_lrn_cfg_0_out ; + end + (32'hf06c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_nan_flush_to_zero_0_out ; + end + (32'hf08c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_nan_input_num_0_out ; + end + (32'hf094 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_nan_output_num_0_out ; + end + (32'hf048 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_op_enable_0_out ; + end + (32'hf098 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_out_saturation_0_out ; + end + (32'hf09c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_enable_0_out ; + end + (32'hf0ac & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_hybrid_0_out ; + end + (32'hf0b0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_le_hit_0_out ; + end + (32'hf0b4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_lo_hit_0_out ; + end + (32'hf0a8 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_oflow_0_out ; + end + (32'hf0a4 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_lut_uflow_0_out ; + end + (32'hf0a0 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_d_perf_write_stall_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + input_data_type[1:0] <= 2'b01; + datin_offset[15:0] <= 16'b0000000000000000; + datin_scale[15:0] <= 16'b0000000000000001; + datin_shifter[4:0] <= 5'b00000; + datout_offset[31:0] <= 32'b00000000000000000000000000000000; + datout_scale[15:0] <= 16'b0000000000000001; + datout_shifter[5:0] <= 6'b000000; + dst_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + dst_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + dst_ram_type <= 1'b0; + dst_line_stride[31:0] <= 32'b00000000000000000000000000000000; + dst_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + mul_bypass <= 1'b0; + sqsum_bypass <= 1'b0; + normalz_len[1:0] <= 2'b00; + nan_to_zero <= 1'b0; + dma_en <= 1'b0; + lut_en <= 1'b0; + end else begin +// Register: NVDLA_CDP_D_CYA_0 Field: cya + if (nvdla_cdp_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DATA_FORMAT_0 Field: input_data_type + if (nvdla_cdp_d_data_format_0_wren) begin + input_data_type[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CDP_D_DATIN_OFFSET_0 Field: datin_offset + if (nvdla_cdp_d_datin_offset_0_wren) begin + datin_offset[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_D_DATIN_SCALE_0 Field: datin_scale + if (nvdla_cdp_d_datin_scale_0_wren) begin + datin_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_D_DATIN_SHIFTER_0 Field: datin_shifter + if (nvdla_cdp_d_datin_shifter_0_wren) begin + datin_shifter[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDP_D_DATOUT_OFFSET_0 Field: datout_offset + if (nvdla_cdp_d_datout_offset_0_wren) begin + datout_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DATOUT_SCALE_0 Field: datout_scale + if (nvdla_cdp_d_datout_scale_0_wren) begin + datout_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_D_DATOUT_SHIFTER_0 Field: datout_shifter + if (nvdla_cdp_d_datout_shifter_0_wren) begin + datout_shifter[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_D_DST_BASE_ADDR_HIGH_0 Field: dst_base_addr_high + if (nvdla_cdp_d_dst_base_addr_high_0_wren) begin + dst_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DST_BASE_ADDR_LOW_0 Field: dst_base_addr_low + if (nvdla_cdp_d_dst_base_addr_low_0_wren) begin + dst_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for constant field NVDLA_CDP_D_DST_COMPRESSION_EN_0::dst_compression_en +// Register: NVDLA_CDP_D_DST_DMA_CFG_0 Field: dst_ram_type + if (nvdla_cdp_d_dst_dma_cfg_0_wren) begin + dst_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_D_DST_LINE_STRIDE_0 Field: dst_line_stride + if (nvdla_cdp_d_dst_line_stride_0_wren) begin + dst_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_DST_SURFACE_STRIDE_0 Field: dst_surface_stride + if (nvdla_cdp_d_dst_surface_stride_0_wren) begin + dst_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_D_FUNC_BYPASS_0 Field: mul_bypass + if (nvdla_cdp_d_func_bypass_0_wren) begin + mul_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_CDP_D_FUNC_BYPASS_0 Field: sqsum_bypass + if (nvdla_cdp_d_func_bypass_0_wren) begin + sqsum_bypass <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_D_INF_INPUT_NUM_0::inf_input_num +// Register: NVDLA_CDP_D_LRN_CFG_0 Field: normalz_len + if (nvdla_cdp_d_lrn_cfg_0_wren) begin + normalz_len[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CDP_D_NAN_FLUSH_TO_ZERO_0 Field: nan_to_zero + if (nvdla_cdp_d_nan_flush_to_zero_0_wren) begin + nan_to_zero <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_D_NAN_INPUT_NUM_0::nan_input_num +// Not generating flops for read-only field NVDLA_CDP_D_NAN_OUTPUT_NUM_0::nan_output_num +// Not generating flops for field NVDLA_CDP_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_CDP_D_OUT_SATURATION_0::out_saturation +// Register: NVDLA_CDP_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_cdp_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_D_PERF_ENABLE_0 Field: lut_en + if (nvdla_cdp_d_perf_enable_0_wren) begin + lut_en <= reg_wr_data[1]; + end +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_HYBRID_0::perf_lut_hybrid +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_LE_HIT_0::perf_lut_le_hit +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_LO_HIT_0::perf_lut_lo_hit +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_OFLOW_0::perf_lut_oflow +// Not generating flops for read-only field NVDLA_CDP_D_PERF_LUT_UFLOW_0::perf_lut_uflow +// Not generating flops for read-only field NVDLA_CDP_D_PERF_WRITE_STALL_0::perf_write_stall + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hf0b8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_cya_0_out, nvdla_cdp_d_cya_0_out); + (32'hf068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_data_format_0_out, nvdla_cdp_d_data_format_0_out); + (32'hf074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATIN_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datin_offset_0_out, nvdla_cdp_d_datin_offset_0_out); + (32'hf078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATIN_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datin_scale_0_out, nvdla_cdp_d_datin_scale_0_out); + (32'hf07c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATIN_SHIFTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datin_shifter_0_out, nvdla_cdp_d_datin_shifter_0_out); + (32'hf080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATOUT_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datout_offset_0_out, nvdla_cdp_d_datout_offset_0_out); + (32'hf084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATOUT_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datout_scale_0_out, nvdla_cdp_d_datout_scale_0_out); + (32'hf088 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DATOUT_SHIFTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_datout_shifter_0_out, nvdla_cdp_d_datout_shifter_0_out); + (32'hf054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_base_addr_high_0_out, nvdla_cdp_d_dst_base_addr_high_0_out); + (32'hf050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_base_addr_low_0_out, nvdla_cdp_d_dst_base_addr_low_0_out); + (32'hf064 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_DST_COMPRESSION_EN_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_dma_cfg_0_out, nvdla_cdp_d_dst_dma_cfg_0_out); + (32'hf058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_line_stride_0_out, nvdla_cdp_d_dst_line_stride_0_out); + (32'hf05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_DST_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_dst_surface_stride_0_out, nvdla_cdp_d_dst_surface_stride_0_out); + (32'hf04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_FUNC_BYPASS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_func_bypass_0_out, nvdla_cdp_d_func_bypass_0_out); + (32'hf090 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_LRN_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_lrn_cfg_0_out, nvdla_cdp_d_lrn_cfg_0_out); + (32'hf06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_NAN_FLUSH_TO_ZERO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_nan_flush_to_zero_0_out, nvdla_cdp_d_nan_flush_to_zero_0_out); + (32'hf08c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf094 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_NAN_OUTPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_op_enable_0_out, nvdla_cdp_d_op_enable_0_out); + (32'hf098 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_OUT_SATURATION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf09c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_d_perf_enable_0_out, nvdla_cdp_d_perf_enable_0_out); + (32'hf0ac & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_HYBRID_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0b0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_LE_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0b4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_LO_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0a8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_OFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0a4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_LUT_UFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hf0a0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_D_PERF_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v new file mode 100644 index 0000000..f6e2b56 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v @@ -0,0 +1,461 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_REG_single.v +module NV_NVDLA_CDP_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,lut_access_type + ,lut_addr_trigger + ,lut_table_id + ,lut_data_trigger + ,lut_hybrid_priority + ,lut_le_function + ,lut_oflow_priority + ,lut_uflow_priority + ,lut_le_index_offset + ,lut_le_index_select + ,lut_lo_index_select + ,lut_le_end_high + ,lut_le_end_low + ,lut_le_slope_oflow_scale + ,lut_le_slope_uflow_scale + ,lut_le_slope_oflow_shift + ,lut_le_slope_uflow_shift + ,lut_le_start_high + ,lut_le_start_low + ,lut_lo_end_high + ,lut_lo_end_low + ,lut_lo_slope_oflow_scale + ,lut_lo_slope_uflow_scale + ,lut_lo_slope_oflow_shift + ,lut_lo_slope_uflow_shift + ,lut_lo_start_high + ,lut_lo_start_low + ,producer + ,lut_addr + ,lut_data + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cdp_s_lut_access_cfg_0_out; +wire [31:0] nvdla_cdp_s_lut_access_data_0_out; +wire [31:0] nvdla_cdp_s_lut_cfg_0_out; +wire [31:0] nvdla_cdp_s_lut_info_0_out; +wire [31:0] nvdla_cdp_s_lut_le_end_high_0_out; +wire [31:0] nvdla_cdp_s_lut_le_end_low_0_out; +wire [31:0] nvdla_cdp_s_lut_le_slope_scale_0_out; +wire [31:0] nvdla_cdp_s_lut_le_slope_shift_0_out; +wire [31:0] nvdla_cdp_s_lut_le_start_high_0_out; +wire [31:0] nvdla_cdp_s_lut_le_start_low_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_end_high_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_end_low_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_slope_scale_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_slope_shift_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_start_high_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_start_low_0_out; +wire [31:0] nvdla_cdp_s_pointer_0_out; +wire [31:0] nvdla_cdp_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output lut_access_type; +output lut_addr_trigger; +output lut_table_id; +output lut_data_trigger; +output lut_hybrid_priority; +output lut_le_function; +output lut_oflow_priority; +output lut_uflow_priority; +output [7:0] lut_le_index_offset; +output [7:0] lut_le_index_select; +output [7:0] lut_lo_index_select; +output [5:0] lut_le_end_high; +output [31:0] lut_le_end_low; +output [15:0] lut_le_slope_oflow_scale; +output [15:0] lut_le_slope_uflow_scale; +output [4:0] lut_le_slope_oflow_shift; +output [4:0] lut_le_slope_uflow_shift; +output [5:0] lut_le_start_high; +output [31:0] lut_le_start_low; +output [5:0] lut_lo_end_high; +output [31:0] lut_lo_end_low; +output [15:0] lut_lo_slope_oflow_scale; +output [15:0] lut_lo_slope_uflow_scale; +output [4:0] lut_lo_slope_oflow_shift; +output [4:0] lut_lo_slope_uflow_shift; +output [5:0] lut_lo_start_high; +output [31:0] lut_lo_start_low; +output producer; +// Read-only register inputs +input [9:0] lut_addr; +input [15:0] lut_data; +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg lut_access_type; +reg lut_hybrid_priority; +reg [5:0] lut_le_end_high; +reg [31:0] lut_le_end_low; +reg lut_le_function; +reg [7:0] lut_le_index_offset; +reg [7:0] lut_le_index_select; +reg [15:0] lut_le_slope_oflow_scale; +reg [4:0] lut_le_slope_oflow_shift; +reg [15:0] lut_le_slope_uflow_scale; +reg [4:0] lut_le_slope_uflow_shift; +reg [5:0] lut_le_start_high; +reg [31:0] lut_le_start_low; +reg [5:0] lut_lo_end_high; +reg [31:0] lut_lo_end_low; +reg [7:0] lut_lo_index_select; +reg [15:0] lut_lo_slope_oflow_scale; +reg [4:0] lut_lo_slope_oflow_shift; +reg [15:0] lut_lo_slope_uflow_scale; +reg [4:0] lut_lo_slope_uflow_shift; +reg [5:0] lut_lo_start_high; +reg [31:0] lut_lo_start_low; +reg lut_oflow_priority; +reg lut_table_id; +reg lut_uflow_priority; +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_s_lut_access_cfg_0_wren = (reg_offset_wr == (32'hf008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_access_data_0_wren = (reg_offset_wr == (32'hf00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_cfg_0_wren = (reg_offset_wr == (32'hf010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_info_0_wren = (reg_offset_wr == (32'hf014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_end_high_0_wren = (reg_offset_wr == (32'hf024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_end_low_0_wren = (reg_offset_wr == (32'hf020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_slope_scale_0_wren = (reg_offset_wr == (32'hf038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_slope_shift_0_wren = (reg_offset_wr == (32'hf03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_start_high_0_wren = (reg_offset_wr == (32'hf01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_start_low_0_wren = (reg_offset_wr == (32'hf018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_end_high_0_wren = (reg_offset_wr == (32'hf034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_end_low_0_wren = (reg_offset_wr == (32'hf030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_slope_scale_0_wren = (reg_offset_wr == (32'hf040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_slope_shift_0_wren = (reg_offset_wr == (32'hf044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_start_high_0_wren = (reg_offset_wr == (32'hf02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_start_low_0_wren = (reg_offset_wr == (32'hf028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_pointer_0_wren = (reg_offset_wr == (32'hf004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_status_0_wren = (reg_offset_wr == (32'hf000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdp_s_lut_access_cfg_0_out[31:0] = { 14'b0, lut_access_type, lut_table_id, 6'b0, lut_addr }; +assign nvdla_cdp_s_lut_access_data_0_out[31:0] = { 16'b0, lut_data }; +assign nvdla_cdp_s_lut_cfg_0_out[31:0] = { 25'b0, lut_hybrid_priority, lut_oflow_priority, lut_uflow_priority, 3'b0, lut_le_function }; +assign nvdla_cdp_s_lut_info_0_out[31:0] = { 8'b0, lut_lo_index_select, lut_le_index_select, lut_le_index_offset }; +assign nvdla_cdp_s_lut_le_end_high_0_out[31:0] = { 26'b0, lut_le_end_high }; +assign nvdla_cdp_s_lut_le_end_low_0_out[31:0] = { lut_le_end_low }; +assign nvdla_cdp_s_lut_le_slope_scale_0_out[31:0] = { lut_le_slope_oflow_scale, lut_le_slope_uflow_scale }; +assign nvdla_cdp_s_lut_le_slope_shift_0_out[31:0] = { 22'b0, lut_le_slope_oflow_shift, lut_le_slope_uflow_shift }; +assign nvdla_cdp_s_lut_le_start_high_0_out[31:0] = { 26'b0, lut_le_start_high }; +assign nvdla_cdp_s_lut_le_start_low_0_out[31:0] = { lut_le_start_low }; +assign nvdla_cdp_s_lut_lo_end_high_0_out[31:0] = { 26'b0, lut_lo_end_high }; +assign nvdla_cdp_s_lut_lo_end_low_0_out[31:0] = { lut_lo_end_low }; +assign nvdla_cdp_s_lut_lo_slope_scale_0_out[31:0] = { lut_lo_slope_oflow_scale, lut_lo_slope_uflow_scale }; +assign nvdla_cdp_s_lut_lo_slope_shift_0_out[31:0] = { 22'b0, lut_lo_slope_oflow_shift, lut_lo_slope_uflow_shift }; +assign nvdla_cdp_s_lut_lo_start_high_0_out[31:0] = { 26'b0, lut_lo_start_high }; +assign nvdla_cdp_s_lut_lo_start_low_0_out[31:0] = { lut_lo_start_low }; +assign nvdla_cdp_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cdp_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign lut_addr_trigger = nvdla_cdp_s_lut_access_cfg_0_wren; //(W563) +assign lut_data_trigger = nvdla_cdp_s_lut_access_data_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_s_lut_access_cfg_0_out + or nvdla_cdp_s_lut_access_data_0_out + or nvdla_cdp_s_lut_cfg_0_out + or nvdla_cdp_s_lut_info_0_out + or nvdla_cdp_s_lut_le_end_high_0_out + or nvdla_cdp_s_lut_le_end_low_0_out + or nvdla_cdp_s_lut_le_slope_scale_0_out + or nvdla_cdp_s_lut_le_slope_shift_0_out + or nvdla_cdp_s_lut_le_start_high_0_out + or nvdla_cdp_s_lut_le_start_low_0_out + or nvdla_cdp_s_lut_lo_end_high_0_out + or nvdla_cdp_s_lut_lo_end_low_0_out + or nvdla_cdp_s_lut_lo_slope_scale_0_out + or nvdla_cdp_s_lut_lo_slope_shift_0_out + or nvdla_cdp_s_lut_lo_start_high_0_out + or nvdla_cdp_s_lut_lo_start_low_0_out + or nvdla_cdp_s_pointer_0_out + or nvdla_cdp_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hf008 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_access_cfg_0_out ; + end + (32'hf00c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_access_data_0_out ; + end + (32'hf010 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_cfg_0_out ; + end + (32'hf014 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_info_0_out ; + end + (32'hf024 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_end_high_0_out ; + end + (32'hf020 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_end_low_0_out ; + end + (32'hf038 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_slope_scale_0_out ; + end + (32'hf03c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_slope_shift_0_out ; + end + (32'hf01c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_start_high_0_out ; + end + (32'hf018 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_start_low_0_out ; + end + (32'hf034 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_end_high_0_out ; + end + (32'hf030 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_end_low_0_out ; + end + (32'hf040 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_slope_scale_0_out ; + end + (32'hf044 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_slope_shift_0_out ; + end + (32'hf02c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_start_high_0_out ; + end + (32'hf028 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_start_low_0_out ; + end + (32'hf004 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_pointer_0_out ; + end + (32'hf000 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_access_type <= 1'b0; + lut_table_id <= 1'b0; + lut_hybrid_priority <= 1'b0; + lut_le_function <= 1'b0; + lut_oflow_priority <= 1'b0; + lut_uflow_priority <= 1'b0; + lut_le_index_offset[7:0] <= 8'b00000000; + lut_le_index_select[7:0] <= 8'b00000000; + lut_lo_index_select[7:0] <= 8'b00000000; + lut_le_end_high[5:0] <= 6'b000000; + lut_le_end_low[31:0] <= 32'b00000000000000000000000000000000; + lut_le_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_oflow_shift[4:0] <= 5'b00000; + lut_le_slope_uflow_shift[4:0] <= 5'b00000; + lut_le_start_high[5:0] <= 6'b000000; + lut_le_start_low[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_end_high[5:0] <= 6'b000000; + lut_lo_end_low[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_oflow_shift[4:0] <= 5'b00000; + lut_lo_slope_uflow_shift[4:0] <= 5'b00000; + lut_lo_start_high[5:0] <= 6'b000000; + lut_lo_start_low[31:0] <= 32'b00000000000000000000000000000000; + producer <= 1'b0; + end else begin +// Register: NVDLA_CDP_S_LUT_ACCESS_CFG_0 Field: lut_access_type + if (nvdla_cdp_s_lut_access_cfg_0_wren) begin + lut_access_type <= reg_wr_data[17]; + end +// Not generating flops for field NVDLA_CDP_S_LUT_ACCESS_CFG_0::lut_addr (to be implemented outside) +// Register: NVDLA_CDP_S_LUT_ACCESS_CFG_0 Field: lut_table_id + if (nvdla_cdp_s_lut_access_cfg_0_wren) begin + lut_table_id <= reg_wr_data[16]; + end +// Not generating flops for field NVDLA_CDP_S_LUT_ACCESS_DATA_0::lut_data (to be implemented outside) +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_hybrid_priority + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_hybrid_priority <= reg_wr_data[6]; + end +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_le_function + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_le_function <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_oflow_priority + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_oflow_priority <= reg_wr_data[5]; + end +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_uflow_priority + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_uflow_priority <= reg_wr_data[4]; + end +// Register: NVDLA_CDP_S_LUT_INFO_0 Field: lut_le_index_offset + if (nvdla_cdp_s_lut_info_0_wren) begin + lut_le_index_offset[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_CDP_S_LUT_INFO_0 Field: lut_le_index_select + if (nvdla_cdp_s_lut_info_0_wren) begin + lut_le_index_select[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_CDP_S_LUT_INFO_0 Field: lut_lo_index_select + if (nvdla_cdp_s_lut_info_0_wren) begin + lut_lo_index_select[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_CDP_S_LUT_LE_END_HIGH_0 Field: lut_le_end_high + if (nvdla_cdp_s_lut_le_end_high_0_wren) begin + lut_le_end_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_END_LOW_0 Field: lut_le_end_low + if (nvdla_cdp_s_lut_le_end_low_0_wren) begin + lut_le_end_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_oflow_scale + if (nvdla_cdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_uflow_scale + if (nvdla_cdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_oflow_shift + if (nvdla_cdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_uflow_shift + if (nvdla_cdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_START_HIGH_0 Field: lut_le_start_high + if (nvdla_cdp_s_lut_le_start_high_0_wren) begin + lut_le_start_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_START_LOW_0 Field: lut_le_start_low + if (nvdla_cdp_s_lut_le_start_low_0_wren) begin + lut_le_start_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_END_HIGH_0 Field: lut_lo_end_high + if (nvdla_cdp_s_lut_lo_end_high_0_wren) begin + lut_lo_end_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_END_LOW_0 Field: lut_lo_end_low + if (nvdla_cdp_s_lut_lo_end_low_0_wren) begin + lut_lo_end_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_oflow_scale + if (nvdla_cdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_uflow_scale + if (nvdla_cdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_oflow_shift + if (nvdla_cdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_uflow_shift + if (nvdla_cdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_START_HIGH_0 Field: lut_lo_start_high + if (nvdla_cdp_s_lut_lo_start_high_0_wren) begin + lut_lo_start_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_START_LOW_0 Field: lut_lo_start_low + if (nvdla_cdp_s_lut_lo_start_low_0_wren) begin + lut_lo_start_low[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_CDP_S_POINTER_0::consumer +// Register: NVDLA_CDP_S_POINTER_0 Field: producer + if (nvdla_cdp_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CDP_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hf008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_ACCESS_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_access_cfg_0_out, nvdla_cdp_s_lut_access_cfg_0_out); + (32'hf00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_ACCESS_DATA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_access_data_0_out, nvdla_cdp_s_lut_access_data_0_out); + (32'hf010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_cfg_0_out, nvdla_cdp_s_lut_cfg_0_out); + (32'hf014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_INFO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_info_0_out, nvdla_cdp_s_lut_info_0_out); + (32'hf024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_END_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_end_high_0_out, nvdla_cdp_s_lut_le_end_high_0_out); + (32'hf020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_END_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_end_low_0_out, nvdla_cdp_s_lut_le_end_low_0_out); + (32'hf038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_slope_scale_0_out, nvdla_cdp_s_lut_le_slope_scale_0_out); + (32'hf03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_slope_shift_0_out, nvdla_cdp_s_lut_le_slope_shift_0_out); + (32'hf01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_START_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_start_high_0_out, nvdla_cdp_s_lut_le_start_high_0_out); + (32'hf018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_START_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_start_low_0_out, nvdla_cdp_s_lut_le_start_low_0_out); + (32'hf034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_END_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_end_high_0_out, nvdla_cdp_s_lut_lo_end_high_0_out); + (32'hf030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_END_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_end_low_0_out, nvdla_cdp_s_lut_lo_end_low_0_out); + (32'hf040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_slope_scale_0_out, nvdla_cdp_s_lut_lo_slope_scale_0_out); + (32'hf044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_slope_shift_0_out, nvdla_cdp_s_lut_lo_slope_shift_0_out); + (32'hf02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_START_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_start_high_0_out, nvdla_cdp_s_lut_lo_start_high_0_out); + (32'hf028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_START_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_start_low_0_out, nvdla_cdp_s_lut_lo_start_low_0_out); + (32'hf004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_pointer_0_out, nvdla_cdp_s_pointer_0_out); + (32'hf000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v.vcp new file mode 100644 index 0000000..f6e2b56 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v.vcp @@ -0,0 +1,461 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_REG_single.v +module NV_NVDLA_CDP_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,lut_access_type + ,lut_addr_trigger + ,lut_table_id + ,lut_data_trigger + ,lut_hybrid_priority + ,lut_le_function + ,lut_oflow_priority + ,lut_uflow_priority + ,lut_le_index_offset + ,lut_le_index_select + ,lut_lo_index_select + ,lut_le_end_high + ,lut_le_end_low + ,lut_le_slope_oflow_scale + ,lut_le_slope_uflow_scale + ,lut_le_slope_oflow_shift + ,lut_le_slope_uflow_shift + ,lut_le_start_high + ,lut_le_start_low + ,lut_lo_end_high + ,lut_lo_end_low + ,lut_lo_slope_oflow_scale + ,lut_lo_slope_uflow_scale + ,lut_lo_slope_oflow_shift + ,lut_lo_slope_uflow_shift + ,lut_lo_start_high + ,lut_lo_start_low + ,producer + ,lut_addr + ,lut_data + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cdp_s_lut_access_cfg_0_out; +wire [31:0] nvdla_cdp_s_lut_access_data_0_out; +wire [31:0] nvdla_cdp_s_lut_cfg_0_out; +wire [31:0] nvdla_cdp_s_lut_info_0_out; +wire [31:0] nvdla_cdp_s_lut_le_end_high_0_out; +wire [31:0] nvdla_cdp_s_lut_le_end_low_0_out; +wire [31:0] nvdla_cdp_s_lut_le_slope_scale_0_out; +wire [31:0] nvdla_cdp_s_lut_le_slope_shift_0_out; +wire [31:0] nvdla_cdp_s_lut_le_start_high_0_out; +wire [31:0] nvdla_cdp_s_lut_le_start_low_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_end_high_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_end_low_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_slope_scale_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_slope_shift_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_start_high_0_out; +wire [31:0] nvdla_cdp_s_lut_lo_start_low_0_out; +wire [31:0] nvdla_cdp_s_pointer_0_out; +wire [31:0] nvdla_cdp_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output lut_access_type; +output lut_addr_trigger; +output lut_table_id; +output lut_data_trigger; +output lut_hybrid_priority; +output lut_le_function; +output lut_oflow_priority; +output lut_uflow_priority; +output [7:0] lut_le_index_offset; +output [7:0] lut_le_index_select; +output [7:0] lut_lo_index_select; +output [5:0] lut_le_end_high; +output [31:0] lut_le_end_low; +output [15:0] lut_le_slope_oflow_scale; +output [15:0] lut_le_slope_uflow_scale; +output [4:0] lut_le_slope_oflow_shift; +output [4:0] lut_le_slope_uflow_shift; +output [5:0] lut_le_start_high; +output [31:0] lut_le_start_low; +output [5:0] lut_lo_end_high; +output [31:0] lut_lo_end_low; +output [15:0] lut_lo_slope_oflow_scale; +output [15:0] lut_lo_slope_uflow_scale; +output [4:0] lut_lo_slope_oflow_shift; +output [4:0] lut_lo_slope_uflow_shift; +output [5:0] lut_lo_start_high; +output [31:0] lut_lo_start_low; +output producer; +// Read-only register inputs +input [9:0] lut_addr; +input [15:0] lut_data; +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg lut_access_type; +reg lut_hybrid_priority; +reg [5:0] lut_le_end_high; +reg [31:0] lut_le_end_low; +reg lut_le_function; +reg [7:0] lut_le_index_offset; +reg [7:0] lut_le_index_select; +reg [15:0] lut_le_slope_oflow_scale; +reg [4:0] lut_le_slope_oflow_shift; +reg [15:0] lut_le_slope_uflow_scale; +reg [4:0] lut_le_slope_uflow_shift; +reg [5:0] lut_le_start_high; +reg [31:0] lut_le_start_low; +reg [5:0] lut_lo_end_high; +reg [31:0] lut_lo_end_low; +reg [7:0] lut_lo_index_select; +reg [15:0] lut_lo_slope_oflow_scale; +reg [4:0] lut_lo_slope_oflow_shift; +reg [15:0] lut_lo_slope_uflow_scale; +reg [4:0] lut_lo_slope_uflow_shift; +reg [5:0] lut_lo_start_high; +reg [31:0] lut_lo_start_low; +reg lut_oflow_priority; +reg lut_table_id; +reg lut_uflow_priority; +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cdp_s_lut_access_cfg_0_wren = (reg_offset_wr == (32'hf008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_access_data_0_wren = (reg_offset_wr == (32'hf00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_cfg_0_wren = (reg_offset_wr == (32'hf010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_info_0_wren = (reg_offset_wr == (32'hf014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_end_high_0_wren = (reg_offset_wr == (32'hf024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_end_low_0_wren = (reg_offset_wr == (32'hf020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_slope_scale_0_wren = (reg_offset_wr == (32'hf038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_slope_shift_0_wren = (reg_offset_wr == (32'hf03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_start_high_0_wren = (reg_offset_wr == (32'hf01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_le_start_low_0_wren = (reg_offset_wr == (32'hf018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_end_high_0_wren = (reg_offset_wr == (32'hf034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_end_low_0_wren = (reg_offset_wr == (32'hf030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_slope_scale_0_wren = (reg_offset_wr == (32'hf040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_slope_shift_0_wren = (reg_offset_wr == (32'hf044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_start_high_0_wren = (reg_offset_wr == (32'hf02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_lut_lo_start_low_0_wren = (reg_offset_wr == (32'hf028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_pointer_0_wren = (reg_offset_wr == (32'hf004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cdp_s_status_0_wren = (reg_offset_wr == (32'hf000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cdp_s_lut_access_cfg_0_out[31:0] = { 14'b0, lut_access_type, lut_table_id, 6'b0, lut_addr }; +assign nvdla_cdp_s_lut_access_data_0_out[31:0] = { 16'b0, lut_data }; +assign nvdla_cdp_s_lut_cfg_0_out[31:0] = { 25'b0, lut_hybrid_priority, lut_oflow_priority, lut_uflow_priority, 3'b0, lut_le_function }; +assign nvdla_cdp_s_lut_info_0_out[31:0] = { 8'b0, lut_lo_index_select, lut_le_index_select, lut_le_index_offset }; +assign nvdla_cdp_s_lut_le_end_high_0_out[31:0] = { 26'b0, lut_le_end_high }; +assign nvdla_cdp_s_lut_le_end_low_0_out[31:0] = { lut_le_end_low }; +assign nvdla_cdp_s_lut_le_slope_scale_0_out[31:0] = { lut_le_slope_oflow_scale, lut_le_slope_uflow_scale }; +assign nvdla_cdp_s_lut_le_slope_shift_0_out[31:0] = { 22'b0, lut_le_slope_oflow_shift, lut_le_slope_uflow_shift }; +assign nvdla_cdp_s_lut_le_start_high_0_out[31:0] = { 26'b0, lut_le_start_high }; +assign nvdla_cdp_s_lut_le_start_low_0_out[31:0] = { lut_le_start_low }; +assign nvdla_cdp_s_lut_lo_end_high_0_out[31:0] = { 26'b0, lut_lo_end_high }; +assign nvdla_cdp_s_lut_lo_end_low_0_out[31:0] = { lut_lo_end_low }; +assign nvdla_cdp_s_lut_lo_slope_scale_0_out[31:0] = { lut_lo_slope_oflow_scale, lut_lo_slope_uflow_scale }; +assign nvdla_cdp_s_lut_lo_slope_shift_0_out[31:0] = { 22'b0, lut_lo_slope_oflow_shift, lut_lo_slope_uflow_shift }; +assign nvdla_cdp_s_lut_lo_start_high_0_out[31:0] = { 26'b0, lut_lo_start_high }; +assign nvdla_cdp_s_lut_lo_start_low_0_out[31:0] = { lut_lo_start_low }; +assign nvdla_cdp_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cdp_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign lut_addr_trigger = nvdla_cdp_s_lut_access_cfg_0_wren; //(W563) +assign lut_data_trigger = nvdla_cdp_s_lut_access_data_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cdp_s_lut_access_cfg_0_out + or nvdla_cdp_s_lut_access_data_0_out + or nvdla_cdp_s_lut_cfg_0_out + or nvdla_cdp_s_lut_info_0_out + or nvdla_cdp_s_lut_le_end_high_0_out + or nvdla_cdp_s_lut_le_end_low_0_out + or nvdla_cdp_s_lut_le_slope_scale_0_out + or nvdla_cdp_s_lut_le_slope_shift_0_out + or nvdla_cdp_s_lut_le_start_high_0_out + or nvdla_cdp_s_lut_le_start_low_0_out + or nvdla_cdp_s_lut_lo_end_high_0_out + or nvdla_cdp_s_lut_lo_end_low_0_out + or nvdla_cdp_s_lut_lo_slope_scale_0_out + or nvdla_cdp_s_lut_lo_slope_shift_0_out + or nvdla_cdp_s_lut_lo_start_high_0_out + or nvdla_cdp_s_lut_lo_start_low_0_out + or nvdla_cdp_s_pointer_0_out + or nvdla_cdp_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hf008 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_access_cfg_0_out ; + end + (32'hf00c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_access_data_0_out ; + end + (32'hf010 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_cfg_0_out ; + end + (32'hf014 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_info_0_out ; + end + (32'hf024 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_end_high_0_out ; + end + (32'hf020 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_end_low_0_out ; + end + (32'hf038 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_slope_scale_0_out ; + end + (32'hf03c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_slope_shift_0_out ; + end + (32'hf01c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_start_high_0_out ; + end + (32'hf018 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_le_start_low_0_out ; + end + (32'hf034 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_end_high_0_out ; + end + (32'hf030 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_end_low_0_out ; + end + (32'hf040 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_slope_scale_0_out ; + end + (32'hf044 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_slope_shift_0_out ; + end + (32'hf02c & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_start_high_0_out ; + end + (32'hf028 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_lut_lo_start_low_0_out ; + end + (32'hf004 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_pointer_0_out ; + end + (32'hf000 & 32'h00000fff): begin + reg_rd_data = nvdla_cdp_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_access_type <= 1'b0; + lut_table_id <= 1'b0; + lut_hybrid_priority <= 1'b0; + lut_le_function <= 1'b0; + lut_oflow_priority <= 1'b0; + lut_uflow_priority <= 1'b0; + lut_le_index_offset[7:0] <= 8'b00000000; + lut_le_index_select[7:0] <= 8'b00000000; + lut_lo_index_select[7:0] <= 8'b00000000; + lut_le_end_high[5:0] <= 6'b000000; + lut_le_end_low[31:0] <= 32'b00000000000000000000000000000000; + lut_le_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_oflow_shift[4:0] <= 5'b00000; + lut_le_slope_uflow_shift[4:0] <= 5'b00000; + lut_le_start_high[5:0] <= 6'b000000; + lut_le_start_low[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_end_high[5:0] <= 6'b000000; + lut_lo_end_low[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_oflow_shift[4:0] <= 5'b00000; + lut_lo_slope_uflow_shift[4:0] <= 5'b00000; + lut_lo_start_high[5:0] <= 6'b000000; + lut_lo_start_low[31:0] <= 32'b00000000000000000000000000000000; + producer <= 1'b0; + end else begin +// Register: NVDLA_CDP_S_LUT_ACCESS_CFG_0 Field: lut_access_type + if (nvdla_cdp_s_lut_access_cfg_0_wren) begin + lut_access_type <= reg_wr_data[17]; + end +// Not generating flops for field NVDLA_CDP_S_LUT_ACCESS_CFG_0::lut_addr (to be implemented outside) +// Register: NVDLA_CDP_S_LUT_ACCESS_CFG_0 Field: lut_table_id + if (nvdla_cdp_s_lut_access_cfg_0_wren) begin + lut_table_id <= reg_wr_data[16]; + end +// Not generating flops for field NVDLA_CDP_S_LUT_ACCESS_DATA_0::lut_data (to be implemented outside) +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_hybrid_priority + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_hybrid_priority <= reg_wr_data[6]; + end +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_le_function + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_le_function <= reg_wr_data[0]; + end +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_oflow_priority + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_oflow_priority <= reg_wr_data[5]; + end +// Register: NVDLA_CDP_S_LUT_CFG_0 Field: lut_uflow_priority + if (nvdla_cdp_s_lut_cfg_0_wren) begin + lut_uflow_priority <= reg_wr_data[4]; + end +// Register: NVDLA_CDP_S_LUT_INFO_0 Field: lut_le_index_offset + if (nvdla_cdp_s_lut_info_0_wren) begin + lut_le_index_offset[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_CDP_S_LUT_INFO_0 Field: lut_le_index_select + if (nvdla_cdp_s_lut_info_0_wren) begin + lut_le_index_select[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_CDP_S_LUT_INFO_0 Field: lut_lo_index_select + if (nvdla_cdp_s_lut_info_0_wren) begin + lut_lo_index_select[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_CDP_S_LUT_LE_END_HIGH_0 Field: lut_le_end_high + if (nvdla_cdp_s_lut_le_end_high_0_wren) begin + lut_le_end_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_END_LOW_0 Field: lut_le_end_low + if (nvdla_cdp_s_lut_le_end_low_0_wren) begin + lut_le_end_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_oflow_scale + if (nvdla_cdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_uflow_scale + if (nvdla_cdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_oflow_shift + if (nvdla_cdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_CDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_uflow_shift + if (nvdla_cdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_START_HIGH_0 Field: lut_le_start_high + if (nvdla_cdp_s_lut_le_start_high_0_wren) begin + lut_le_start_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LE_START_LOW_0 Field: lut_le_start_low + if (nvdla_cdp_s_lut_le_start_low_0_wren) begin + lut_le_start_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_END_HIGH_0 Field: lut_lo_end_high + if (nvdla_cdp_s_lut_lo_end_high_0_wren) begin + lut_lo_end_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_END_LOW_0 Field: lut_lo_end_low + if (nvdla_cdp_s_lut_lo_end_low_0_wren) begin + lut_lo_end_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_oflow_scale + if (nvdla_cdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_uflow_scale + if (nvdla_cdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_oflow_shift + if (nvdla_cdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_CDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_uflow_shift + if (nvdla_cdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_START_HIGH_0 Field: lut_lo_start_high + if (nvdla_cdp_s_lut_lo_start_high_0_wren) begin + lut_lo_start_high[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_CDP_S_LUT_LO_START_LOW_0 Field: lut_lo_start_low + if (nvdla_cdp_s_lut_lo_start_low_0_wren) begin + lut_lo_start_low[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_CDP_S_POINTER_0::consumer +// Register: NVDLA_CDP_S_POINTER_0 Field: producer + if (nvdla_cdp_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CDP_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CDP_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hf008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_ACCESS_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_access_cfg_0_out, nvdla_cdp_s_lut_access_cfg_0_out); + (32'hf00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_ACCESS_DATA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_access_data_0_out, nvdla_cdp_s_lut_access_data_0_out); + (32'hf010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_cfg_0_out, nvdla_cdp_s_lut_cfg_0_out); + (32'hf014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_INFO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_info_0_out, nvdla_cdp_s_lut_info_0_out); + (32'hf024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_END_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_end_high_0_out, nvdla_cdp_s_lut_le_end_high_0_out); + (32'hf020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_END_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_end_low_0_out, nvdla_cdp_s_lut_le_end_low_0_out); + (32'hf038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_slope_scale_0_out, nvdla_cdp_s_lut_le_slope_scale_0_out); + (32'hf03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_slope_shift_0_out, nvdla_cdp_s_lut_le_slope_shift_0_out); + (32'hf01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_START_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_start_high_0_out, nvdla_cdp_s_lut_le_start_high_0_out); + (32'hf018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LE_START_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_le_start_low_0_out, nvdla_cdp_s_lut_le_start_low_0_out); + (32'hf034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_END_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_end_high_0_out, nvdla_cdp_s_lut_lo_end_high_0_out); + (32'hf030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_END_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_end_low_0_out, nvdla_cdp_s_lut_lo_end_low_0_out); + (32'hf040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_slope_scale_0_out, nvdla_cdp_s_lut_lo_slope_scale_0_out); + (32'hf044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_slope_shift_0_out, nvdla_cdp_s_lut_lo_slope_shift_0_out); + (32'hf02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_START_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_start_high_0_out, nvdla_cdp_s_lut_lo_start_high_0_out); + (32'hf028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_LUT_LO_START_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_lut_lo_start_low_0_out, nvdla_cdp_s_lut_lo_start_low_0_out); + (32'hf004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CDP_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cdp_s_pointer_0_out, nvdla_cdp_s_pointer_0_out); + (32'hf000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CDP_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CDP_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v new file mode 100644 index 0000000..8f3d72e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v @@ -0,0 +1,617 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_dp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_dp ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp_dp2wdma_ready //|< i + ,cdp_rdma2dp_pd //|< i + ,cdp_rdma2dp_valid //|< i + ,dp2reg_done //|< i + ,nvdla_core_clk_orig //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_datin_offset //|< i + ,reg2dp_datin_scale //|< i + ,reg2dp_datin_shifter //|< i + ,reg2dp_datout_offset //|< i + ,reg2dp_datout_scale //|< i + ,reg2dp_datout_shifter //|< i + ,reg2dp_lut_access_type //|< i + ,reg2dp_lut_addr //|< i + ,reg2dp_lut_data //|< i + ,reg2dp_lut_data_trigger //|< i + ,reg2dp_lut_hybrid_priority //|< i + ,reg2dp_lut_le_end_high //|< i + ,reg2dp_lut_le_end_low //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_index_select //|< i + ,reg2dp_lut_le_slope_oflow_scale //|< i + ,reg2dp_lut_le_slope_oflow_shift //|< i + ,reg2dp_lut_le_slope_uflow_scale //|< i + ,reg2dp_lut_le_slope_uflow_shift //|< i + ,reg2dp_lut_le_start_high //|< i + ,reg2dp_lut_le_start_low //|< i + ,reg2dp_lut_lo_end_high //|< i + ,reg2dp_lut_lo_end_low //|< i + ,reg2dp_lut_lo_index_select //|< i + ,reg2dp_lut_lo_slope_oflow_scale //|< i + ,reg2dp_lut_lo_slope_oflow_shift //|< i + ,reg2dp_lut_lo_slope_uflow_scale //|< i + ,reg2dp_lut_lo_slope_uflow_shift //|< i + ,reg2dp_lut_lo_start_high //|< i + ,reg2dp_lut_lo_start_low //|< i + ,reg2dp_lut_oflow_priority //|< i + ,reg2dp_lut_table_id //|< i + ,reg2dp_lut_uflow_priority //|< i + ,reg2dp_mul_bypass //|< i + ,reg2dp_normalz_len //|< i + ,reg2dp_sqsum_bypass //|< i + ,cdp_dp2wdma_pd //|> o + ,cdp_dp2wdma_valid //|> o + ,cdp_rdma2dp_ready //|> o + ,dp2reg_d0_out_saturation //|> o + ,dp2reg_d0_perf_lut_hybrid //|> o + ,dp2reg_d0_perf_lut_le_hit //|> o + ,dp2reg_d0_perf_lut_lo_hit //|> o + ,dp2reg_d0_perf_lut_oflow //|> o + ,dp2reg_d0_perf_lut_uflow //|> o + ,dp2reg_d1_out_saturation //|> o + ,dp2reg_d1_perf_lut_hybrid //|> o + ,dp2reg_d1_perf_lut_le_hit //|> o + ,dp2reg_d1_perf_lut_lo_hit //|> o + ,dp2reg_d1_perf_lut_oflow //|> o + ,dp2reg_d1_perf_lut_uflow //|> o + ,dp2reg_lut_data //|> o + ); +/////////////////////////////////////////////////////// +/////////////////////////////////////////////////////// +//&Clock nvdla_core_clk; +//&Reset nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dp2reg_done; +input [15:0] reg2dp_datin_offset; +input [15:0] reg2dp_datin_scale; +input [4:0] reg2dp_datin_shifter; +input [31:0] reg2dp_datout_offset; +input [15:0] reg2dp_datout_scale; +input [5:0] reg2dp_datout_shifter; +input reg2dp_lut_access_type; +input [9:0] reg2dp_lut_addr; +input [15:0] reg2dp_lut_data; +input reg2dp_lut_data_trigger; +input reg2dp_lut_hybrid_priority; +input [5:0] reg2dp_lut_le_end_high; +input [31:0] reg2dp_lut_le_end_low; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [7:0] reg2dp_lut_le_index_select; +input [15:0] reg2dp_lut_le_slope_oflow_scale; +input [4:0] reg2dp_lut_le_slope_oflow_shift; +input [15:0] reg2dp_lut_le_slope_uflow_scale; +input [4:0] reg2dp_lut_le_slope_uflow_shift; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [5:0] reg2dp_lut_lo_end_high; +input [31:0] reg2dp_lut_lo_end_low; +input [7:0] reg2dp_lut_lo_index_select; +input [15:0] reg2dp_lut_lo_slope_oflow_scale; +input [4:0] reg2dp_lut_lo_slope_oflow_shift; +input [15:0] reg2dp_lut_lo_slope_uflow_scale; +input [4:0] reg2dp_lut_lo_slope_uflow_shift; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_lut_oflow_priority; +input reg2dp_lut_table_id; +input reg2dp_lut_uflow_priority; +input reg2dp_mul_bypass; +input [1:0] reg2dp_normalz_len; +input reg2dp_sqsum_bypass; +output [31:0] dp2reg_d0_out_saturation; +output [31:0] dp2reg_d0_perf_lut_hybrid; +output [31:0] dp2reg_d0_perf_lut_le_hit; +output [31:0] dp2reg_d0_perf_lut_lo_hit; +output [31:0] dp2reg_d0_perf_lut_oflow; +output [31:0] dp2reg_d0_perf_lut_uflow; +output [31:0] dp2reg_d1_out_saturation; +output [31:0] dp2reg_d1_perf_lut_hybrid; +output [31:0] dp2reg_d1_perf_lut_le_hit; +output [31:0] dp2reg_d1_perf_lut_lo_hit; +output [31:0] dp2reg_d1_perf_lut_oflow; +output [31:0] dp2reg_d1_perf_lut_uflow; +output [15:0] dp2reg_lut_data; +// +// NV_NVDLA_CDP_core_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input cdp_rdma2dp_valid; /* data valid */ +output cdp_rdma2dp_ready; /* data return handshake */ +input [1*8 +22:0] cdp_rdma2dp_pd; +output cdp_dp2wdma_valid; /* data valid */ +input cdp_dp2wdma_ready; /* data return handshake */ +output [1*8 +14:0] cdp_dp2wdma_pd; +input nvdla_core_clk_orig; +/////////////////////////////////////////////////////////////////// +reg sqsum_bypass_en; +//: my $icvto = (8 +1); +//: my $k = 1; +//: print qq( +//: wire [${k}*${icvto}+14:0] bufin_pd; +//: wire [${k}*${icvto}+14:0] cvt2buf_pd; +//: wire [${k}*${icvto}+14:0] cvt2sync_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] cvtin_out_int8_ext; +//: wire [${k}*(${icvto}*2+3)-1:0] lutctrl_in_pd; +//: wire [${k}*(${icvto}+16)-1:0] mul2ocvt_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] sum2itp_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] sum2sync_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] sync2itp_pd; +//: wire [${k}*${icvto}-1:0] sync2mul_pd; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [1*9+14:0] bufin_pd; +wire [1*9+14:0] cvt2buf_pd; +wire [1*9+14:0] cvt2sync_pd; +wire [1*(9*2+3)-1:0] cvtin_out_int8_ext; +wire [1*(9*2+3)-1:0] lutctrl_in_pd; +wire [1*(9+16)-1:0] mul2ocvt_pd; +wire [1*(9*2+3)-1:0] sum2itp_pd; +wire [1*(9*2+3)-1:0] sum2sync_pd; +wire [1*(9*2+3)-1:0] sync2itp_pd; +wire [1*9-1:0] sync2mul_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire bufin_prdy; +wire bufin_pvld; +wire cvt2buf_prdy; +wire cvt2buf_pvld; +wire cvt2sync_prdy; +wire cvt2sync_pvld; +//: my $k = 1; +//: my $icvto = (8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${icvto}-1:0] cvtin_out_int8_$m; +//: wire [9:0] dp2lut_X_entry_${m} ; +//: wire [17:0] dp2lut_Xinfo_${m} ; +//: wire [9:0] dp2lut_Y_entry_${m} ; +//: wire [17:0] dp2lut_Yinfo_${m} ; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [9-1:0] cvtin_out_int8_0; +wire [9:0] dp2lut_X_entry_0 ; +wire [17:0] dp2lut_Xinfo_0 ; +wire [9:0] dp2lut_Y_entry_0 ; +wire [17:0] dp2lut_Yinfo_0 ; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire dp2lut_prdy; +wire dp2lut_pvld; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [16:0] intp2mul_pd_$m; +//: wire [31:0] lut2intp_X_data_${m}0; +//: wire [16:0] lut2intp_X_data_${m}0_17b; +//: wire [31:0] lut2intp_X_data_${m}1; +//: wire [19:0] lut2intp_X_info_${m}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [16:0] intp2mul_pd_0; +wire [31:0] lut2intp_X_data_00; +wire [16:0] lut2intp_X_data_00_17b; +wire [31:0] lut2intp_X_data_01; +wire [19:0] lut2intp_X_info_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire intp2mul_prdy; +wire intp2mul_pvld; +wire [1 -1:0] lut2intp_X_sel; +wire [1 -1:0] lut2intp_Y_sel; +wire lut2intp_prdy; +wire lut2intp_pvld; +wire lutctrl_in_pvld; +wire mul2ocvt_prdy; +wire mul2ocvt_pvld; +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: print "wire [${k}-1:0] normalz_buf_data; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [96-1:0] normalz_buf_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire normalz_buf_data_prdy; +wire normalz_buf_data_pvld; +wire sum2itp_prdy; +wire sum2itp_pvld; +wire sum2sync_prdy; +wire sum2sync_pvld; +wire sync2itp_prdy; +wire sync2itp_pvld; +wire sync2mul_prdy; +wire sync2mul_pvld; +wire [14:0] sync2ocvt_pd; +wire sync2ocvt_prdy; +wire sync2ocvt_pvld; +/////////////////////////////////////////////////////// +assign dp2reg_d0_out_saturation = 32'd0;//for spyglass +assign dp2reg_d1_out_saturation = 32'd0;//for spyglass +///////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sqsum_bypass_en <= 1'b0; + end else begin + sqsum_bypass_en <= reg2dp_sqsum_bypass == 1'h1; + end +end +//===== convertor_in Instance======== +assign cvt2buf_prdy = sqsum_bypass_en ? sum2itp_prdy : bufin_prdy; +NV_NVDLA_CDP_DP_cvtin u_NV_NVDLA_CDP_DP_cvtin ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) + ,.cvt2buf_prdy (cvt2buf_prdy) + ,.cvt2sync_prdy (cvt2sync_prdy) + ,.reg2dp_datin_offset (reg2dp_datin_offset[15:0]) + ,.reg2dp_datin_scale (reg2dp_datin_scale[15:0]) + ,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0]) + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) + ,.cvt2buf_pd (cvt2buf_pd) + ,.cvt2buf_pvld (cvt2buf_pvld) + ,.cvt2sync_pd (cvt2sync_pd) + ,.cvt2sync_pvld (cvt2sync_pvld) + ); +//===== sync fifo Instance======== +NV_NVDLA_CDP_DP_syncfifo u_NV_NVDLA_CDP_DP_syncfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cvt2sync_pd (cvt2sync_pd) + ,.cvt2sync_pvld (cvt2sync_pvld) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.sum2sync_pd (sum2sync_pd) + ,.sum2sync_pvld (sum2sync_pvld) + ,.sync2itp_prdy (sync2itp_prdy) + ,.sync2mul_prdy (sync2mul_prdy) + ,.sync2ocvt_prdy (sync2ocvt_prdy) + ,.cvt2sync_prdy (cvt2sync_prdy) + ,.sum2sync_prdy (sum2sync_prdy) + ,.sync2itp_pd (sync2itp_pd) + ,.sync2itp_pvld (sync2itp_pvld) + ,.sync2mul_pd (sync2mul_pd) + ,.sync2mul_pvld (sync2mul_pvld) + ,.sync2ocvt_pd (sync2ocvt_pd[14:0]) + ,.sync2ocvt_pvld (sync2ocvt_pvld) + ); +//===== Buffer_in Instance======== +assign bufin_pd = sqsum_bypass_en ? 0 : cvt2buf_pd; +assign bufin_pvld = sqsum_bypass_en ? 0 : cvt2buf_pvld; +//: if(1 >= 4) { +//: print qq( +//: NV_NVDLA_CDP_DP_bufferin u_NV_NVDLA_CDP_DP_bufferin ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cdp_rdma2dp_pd (bufin_pd) +//: ,.cdp_rdma2dp_valid (bufin_pvld) +//: ,.normalz_buf_data_prdy (normalz_buf_data_prdy) +//: ,.cdp_rdma2dp_ready (bufin_prdy) +//: ,.normalz_buf_data (normalz_buf_data) +//: ,.normalz_buf_data_pvld (normalz_buf_data_pvld) +//: ); +//: ); +//: } elsif(1 < 4) { +//: print qq( +//: NV_NVDLA_CDP_DP_bufferin_tp1 u_NV_NVDLA_CDP_DP_bufferin ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cdp_rdma2dp_pd (bufin_pd) +//: ,.cdp_rdma2dp_valid (bufin_pvld) +//: ,.normalz_buf_data_prdy (normalz_buf_data_prdy) +//: ,.cdp_rdma2dp_ready (bufin_prdy) +//: ,.normalz_buf_data (normalz_buf_data) +//: ,.normalz_buf_data_pvld (normalz_buf_data_pvld) +//: ); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +NV_NVDLA_CDP_DP_bufferin_tp1 u_NV_NVDLA_CDP_DP_bufferin ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.cdp_rdma2dp_pd (bufin_pd) +,.cdp_rdma2dp_valid (bufin_pvld) +,.normalz_buf_data_prdy (normalz_buf_data_prdy) +,.cdp_rdma2dp_ready (bufin_prdy) +,.normalz_buf_data (normalz_buf_data) +,.normalz_buf_data_pvld (normalz_buf_data_pvld) +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//===== sigma squre Instance======== +NV_NVDLA_CDP_DP_sum u_NV_NVDLA_CDP_DP_sum ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.normalz_buf_data (normalz_buf_data) + ,.normalz_buf_data_pvld (normalz_buf_data_pvld) + ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.sum2itp_prdy (sum2itp_prdy) + ,.normalz_buf_data_prdy (normalz_buf_data_prdy) + ,.sum2itp_pd (sum2itp_pd) + ,.sum2itp_pvld (sum2itp_pvld) + ); +//===== LUT controller Instance======== +//: my $icvto = (8 +1); +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign cvtin_out_int8_$m = cvt2buf_pd[${m}*${icvto}+${icvto}-1:${m}*${icvto}]; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign cvtin_out_int8_0 = cvt2buf_pd[0*9+9-1:0*9]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvtin_out_int8_ext = { +//: my $k = 1; +//: my $icvto = (8 +1); +//: if($k > 1) { +//: foreach my $m (0..$k-1) { +//: print qq( +//: {{(${icvto}+3){cvtin_out_int8_${m}[${icvto}-1]}}, cvtin_out_int8_${m}}, +//: ); +//: } +//: } +//: print "{{(${icvto}+3){cvtin_out_int8_0[${icvto}-1]}}, cvtin_out_int8_0}}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +{{(9+3){cvtin_out_int8_0[9-1]}}, cvtin_out_int8_0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign lutctrl_in_pd = sqsum_bypass_en ? cvtin_out_int8_ext : sum2itp_pd; +assign lutctrl_in_pvld = sqsum_bypass_en ? cvt2buf_pvld : sum2itp_pvld; +NV_NVDLA_CDP_DP_LUT_ctrl u_NV_NVDLA_CDP_DP_LUT_ctrl ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2lut_prdy (dp2lut_prdy) //|< w + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i + ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|< i + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|< i + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|< i + ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|< i + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|< i + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|< i + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) //|< i + ,.sum2itp_pd (lutctrl_in_pd) //|< w + ,.sum2itp_pvld (lutctrl_in_pvld) //|< w + ,.sum2sync_prdy (sum2sync_prdy) //|< w +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.dp2lut_X_entry_${m} (dp2lut_X_entry_${m} ) +//: ,.dp2lut_Xinfo_${m} (dp2lut_Xinfo_${m} ) +//: ,.dp2lut_Y_entry_${m} (dp2lut_Y_entry_${m} ) +//: ,.dp2lut_Yinfo_${m} (dp2lut_Yinfo_${m} ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dp2lut_X_entry_0 (dp2lut_X_entry_0 ) +,.dp2lut_Xinfo_0 (dp2lut_Xinfo_0 ) +,.dp2lut_Y_entry_0 (dp2lut_Y_entry_0 ) +,.dp2lut_Yinfo_0 (dp2lut_Yinfo_0 ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.dp2lut_pvld (dp2lut_pvld) //|> w + ,.sum2itp_prdy (sum2itp_prdy) //|> w + ,.sum2sync_pd (sum2sync_pd) //|> w + ,.sum2sync_pvld (sum2sync_pvld) //|> w + ); +//===== LUT Instance======== +NV_NVDLA_CDP_DP_lut u_NV_NVDLA_CDP_DP_lut ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_clk_orig (nvdla_core_clk_orig) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.dp2lut_X_entry_${m} (dp2lut_X_entry_${m} ) +//: ,.dp2lut_Xinfo_${m} (dp2lut_Xinfo_${m} ) +//: ,.dp2lut_Y_entry_${m} (dp2lut_Y_entry_${m} ) +//: ,.dp2lut_Yinfo_${m} (dp2lut_Yinfo_${m} ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dp2lut_X_entry_0 (dp2lut_X_entry_0 ) +,.dp2lut_Xinfo_0 (dp2lut_Xinfo_0 ) +,.dp2lut_Y_entry_0 (dp2lut_Y_entry_0 ) +,.dp2lut_Yinfo_0 (dp2lut_Yinfo_0 ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.dp2lut_pvld (dp2lut_pvld) //|< w + ,.lut2intp_prdy (lut2intp_prdy) //|< w + ,.reg2dp_lut_access_type (reg2dp_lut_access_type) //|< i + ,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) //|< i + ,.reg2dp_lut_data (reg2dp_lut_data[15:0]) //|< i + ,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) //|< i + ,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|< i + ,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) //|< i + ,.reg2dp_lut_table_id (reg2dp_lut_table_id) //|< i + ,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) //|< i + ,.dp2lut_prdy (dp2lut_prdy) //|> w + ,.dp2reg_lut_data (dp2reg_lut_data[15:0]) //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.lut2intp_X_data_${m}0 (lut2intp_X_data_${m}0 ) +//: ,.lut2intp_X_data_${m}0_17b (lut2intp_X_data_${m}0_17b ) +//: ,.lut2intp_X_data_${m}1 (lut2intp_X_data_${m}1 ) +//: ,.lut2intp_X_info_${m} (lut2intp_X_info_${m} ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.lut2intp_X_data_00 (lut2intp_X_data_00 ) +,.lut2intp_X_data_00_17b (lut2intp_X_data_00_17b ) +,.lut2intp_X_data_01 (lut2intp_X_data_01 ) +,.lut2intp_X_info_0 (lut2intp_X_info_0 ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.lut2intp_X_sel (lut2intp_X_sel) //|> w + ,.lut2intp_Y_sel (lut2intp_Y_sel) //|> w + ,.lut2intp_pvld (lut2intp_pvld) //|> w + ); +//===== interpolator Instance======== +NV_NVDLA_CDP_DP_intp u_NV_NVDLA_CDP_DP_intp ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_done (dp2reg_done) //|< i + ,.intp2mul_prdy (intp2mul_prdy) //|< w +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.lut2intp_X_data_${m}0 (lut2intp_X_data_${m}0 ) +//: ,.lut2intp_X_data_${m}0_17b (lut2intp_X_data_${m}0_17b ) +//: ,.lut2intp_X_data_${m}1 (lut2intp_X_data_${m}1 ) +//: ,.lut2intp_X_info_${m} (lut2intp_X_info_${m} ) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.lut2intp_X_data_00 (lut2intp_X_data_00 ) +,.lut2intp_X_data_00_17b (lut2intp_X_data_00_17b ) +,.lut2intp_X_data_01 (lut2intp_X_data_01 ) +,.lut2intp_X_info_0 (lut2intp_X_info_0 ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.lut2intp_X_sel (lut2intp_X_sel) //|< w + ,.lut2intp_Y_sel (lut2intp_Y_sel) //|< w + ,.lut2intp_pvld (lut2intp_pvld) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) //|< i + ,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) //|< i + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i + ,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|< i + ,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|< i + ,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|< i + ,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|< i + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|< i + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|< i + ,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) //|< i + ,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) //|< i + ,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|< i + ,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|< i + ,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|< i + ,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|< i + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|< i + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|< i + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) //|< i + ,.sync2itp_pd (sync2itp_pd ) //|< w + ,.sync2itp_pvld (sync2itp_pvld) //|< w + ,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) //|> o + ,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) //|> o + ,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) //|> o + ,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) //|> o + ,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) //|> o + ,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) //|> o + ,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) //|> o + ,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) //|> o + ,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) //|> o + ,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.intp2mul_pd_$m (intp2mul_pd_${m}[16:0]) //|> w +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.intp2mul_pd_0 (intp2mul_pd_0[16:0]) //|> w + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.intp2mul_pvld (intp2mul_pvld) //|> w + ,.lut2intp_prdy (lut2intp_prdy) //|> w + ,.sync2itp_prdy (sync2itp_prdy) //|> w + ); +//===== DP multiple Instance======== +NV_NVDLA_CDP_DP_mul u_NV_NVDLA_CDP_DP_mul ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.intp2mul_pd_$m (intp2mul_pd_${m}[16:0]) //|> w +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.intp2mul_pd_0 (intp2mul_pd_0[16:0]) //|> w + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.intp2mul_pvld (intp2mul_pvld) //|< w + ,.mul2ocvt_prdy (mul2ocvt_prdy) //|< w + ,.reg2dp_mul_bypass (reg2dp_mul_bypass) //|< i + ,.sync2mul_pd (sync2mul_pd) //|< w + ,.sync2mul_pvld (sync2mul_pvld) //|< w + ,.intp2mul_prdy (intp2mul_prdy) //|> w + ,.mul2ocvt_pd (mul2ocvt_pd) //|> w + ,.mul2ocvt_pvld (mul2ocvt_pvld) //|> w + ,.sync2mul_prdy (sync2mul_prdy) //|> w + ); +//===== convertor_out Instance======== +NV_NVDLA_CDP_DP_cvtout u_NV_NVDLA_CDP_DP_cvtout ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvtout_prdy (cdp_dp2wdma_ready) //|< i + ,.mul2ocvt_pd (mul2ocvt_pd) //|< w + ,.mul2ocvt_pvld (mul2ocvt_pvld) //|< w + ,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) //|< i + ,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) //|< i + ,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) //|< i + ,.sync2ocvt_pd (sync2ocvt_pd[14:0]) //|< w + ,.sync2ocvt_pvld (sync2ocvt_pvld) //|< w + ,.cvtout_pd (cdp_dp2wdma_pd) //|> o + ,.cvtout_pvld (cdp_dp2wdma_valid) //|> o + ,.mul2ocvt_prdy (mul2ocvt_prdy) //|> w + ,.sync2ocvt_prdy (sync2ocvt_prdy) //|> w + ); +////============== +////OBS signals +////============== +//assign obs_bus_cdp_rdma2dp_vld = cdp_rdma2dp_valid; +//assign obs_bus_cdp_rdma2dp_rdy = cdp_rdma2dp_ready; +//assign obs_bus_cdp_icvt_vld = cvt2buf_pvld; +//assign obs_bus_cdp_icvt_rdy = cvt2buf_prdy; +//assign obs_bus_cdp_buf_vld = normalz_buf_data_pvld; +//assign obs_bus_cdp_buf_rdy = normalz_buf_data_prdy; +//assign obs_bus_cdp_sum_vld = sum2itp_pvld; +//assign obs_bus_cdp_sum_rdy = sum2itp_prdy; +//assign obs_bus_cdp_lutctrl_vld = dp2lut_pvld; +//assign obs_bus_cdp_lutctrl_rdy = dp2lut_prdy; +//assign obs_bus_cdp_intp_vld = intp2mul_pvld; +//assign obs_bus_cdp_intp_rdy = intp2mul_prdy; +//assign obs_bus_cdp_ocvt_vld = cdp_dp2wdma_valid; +//assign obs_bus_cdp_ocvt_rdy = cdp_dp2wdma_ready; +endmodule // NV_NVDLA_CDP_dp diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v.vcp new file mode 100644 index 0000000..93a624b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v.vcp @@ -0,0 +1,516 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_dp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +module NV_NVDLA_CDP_dp ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp_dp2wdma_ready //|< i + ,cdp_rdma2dp_pd //|< i + ,cdp_rdma2dp_valid //|< i + ,dp2reg_done //|< i + ,nvdla_core_clk_orig //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_datin_offset //|< i + ,reg2dp_datin_scale //|< i + ,reg2dp_datin_shifter //|< i + ,reg2dp_datout_offset //|< i + ,reg2dp_datout_scale //|< i + ,reg2dp_datout_shifter //|< i + ,reg2dp_lut_access_type //|< i + ,reg2dp_lut_addr //|< i + ,reg2dp_lut_data //|< i + ,reg2dp_lut_data_trigger //|< i + ,reg2dp_lut_hybrid_priority //|< i + ,reg2dp_lut_le_end_high //|< i + ,reg2dp_lut_le_end_low //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_index_select //|< i + ,reg2dp_lut_le_slope_oflow_scale //|< i + ,reg2dp_lut_le_slope_oflow_shift //|< i + ,reg2dp_lut_le_slope_uflow_scale //|< i + ,reg2dp_lut_le_slope_uflow_shift //|< i + ,reg2dp_lut_le_start_high //|< i + ,reg2dp_lut_le_start_low //|< i + ,reg2dp_lut_lo_end_high //|< i + ,reg2dp_lut_lo_end_low //|< i + ,reg2dp_lut_lo_index_select //|< i + ,reg2dp_lut_lo_slope_oflow_scale //|< i + ,reg2dp_lut_lo_slope_oflow_shift //|< i + ,reg2dp_lut_lo_slope_uflow_scale //|< i + ,reg2dp_lut_lo_slope_uflow_shift //|< i + ,reg2dp_lut_lo_start_high //|< i + ,reg2dp_lut_lo_start_low //|< i + ,reg2dp_lut_oflow_priority //|< i + ,reg2dp_lut_table_id //|< i + ,reg2dp_lut_uflow_priority //|< i + ,reg2dp_mul_bypass //|< i + ,reg2dp_normalz_len //|< i + ,reg2dp_sqsum_bypass //|< i + ,cdp_dp2wdma_pd //|> o + ,cdp_dp2wdma_valid //|> o + ,cdp_rdma2dp_ready //|> o + ,dp2reg_d0_out_saturation //|> o + ,dp2reg_d0_perf_lut_hybrid //|> o + ,dp2reg_d0_perf_lut_le_hit //|> o + ,dp2reg_d0_perf_lut_lo_hit //|> o + ,dp2reg_d0_perf_lut_oflow //|> o + ,dp2reg_d0_perf_lut_uflow //|> o + ,dp2reg_d1_out_saturation //|> o + ,dp2reg_d1_perf_lut_hybrid //|> o + ,dp2reg_d1_perf_lut_le_hit //|> o + ,dp2reg_d1_perf_lut_lo_hit //|> o + ,dp2reg_d1_perf_lut_oflow //|> o + ,dp2reg_d1_perf_lut_uflow //|> o + ,dp2reg_lut_data //|> o + ); +/////////////////////////////////////////////////////// +/////////////////////////////////////////////////////// +//&Clock nvdla_core_clk; +//&Reset nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dp2reg_done; +input [15:0] reg2dp_datin_offset; +input [15:0] reg2dp_datin_scale; +input [4:0] reg2dp_datin_shifter; +input [31:0] reg2dp_datout_offset; +input [15:0] reg2dp_datout_scale; +input [5:0] reg2dp_datout_shifter; +input reg2dp_lut_access_type; +input [9:0] reg2dp_lut_addr; +input [15:0] reg2dp_lut_data; +input reg2dp_lut_data_trigger; +input reg2dp_lut_hybrid_priority; +input [5:0] reg2dp_lut_le_end_high; +input [31:0] reg2dp_lut_le_end_low; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [7:0] reg2dp_lut_le_index_select; +input [15:0] reg2dp_lut_le_slope_oflow_scale; +input [4:0] reg2dp_lut_le_slope_oflow_shift; +input [15:0] reg2dp_lut_le_slope_uflow_scale; +input [4:0] reg2dp_lut_le_slope_uflow_shift; +input [5:0] reg2dp_lut_le_start_high; +input [31:0] reg2dp_lut_le_start_low; +input [5:0] reg2dp_lut_lo_end_high; +input [31:0] reg2dp_lut_lo_end_low; +input [7:0] reg2dp_lut_lo_index_select; +input [15:0] reg2dp_lut_lo_slope_oflow_scale; +input [4:0] reg2dp_lut_lo_slope_oflow_shift; +input [15:0] reg2dp_lut_lo_slope_uflow_scale; +input [4:0] reg2dp_lut_lo_slope_uflow_shift; +input [5:0] reg2dp_lut_lo_start_high; +input [31:0] reg2dp_lut_lo_start_low; +input reg2dp_lut_oflow_priority; +input reg2dp_lut_table_id; +input reg2dp_lut_uflow_priority; +input reg2dp_mul_bypass; +input [1:0] reg2dp_normalz_len; +input reg2dp_sqsum_bypass; +output [31:0] dp2reg_d0_out_saturation; +output [31:0] dp2reg_d0_perf_lut_hybrid; +output [31:0] dp2reg_d0_perf_lut_le_hit; +output [31:0] dp2reg_d0_perf_lut_lo_hit; +output [31:0] dp2reg_d0_perf_lut_oflow; +output [31:0] dp2reg_d0_perf_lut_uflow; +output [31:0] dp2reg_d1_out_saturation; +output [31:0] dp2reg_d1_perf_lut_hybrid; +output [31:0] dp2reg_d1_perf_lut_le_hit; +output [31:0] dp2reg_d1_perf_lut_lo_hit; +output [31:0] dp2reg_d1_perf_lut_oflow; +output [31:0] dp2reg_d1_perf_lut_uflow; +output [15:0] dp2reg_lut_data; +// +// NV_NVDLA_CDP_core_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input cdp_rdma2dp_valid; /* data valid */ +output cdp_rdma2dp_ready; /* data return handshake */ +input [1*8 +22:0] cdp_rdma2dp_pd; +output cdp_dp2wdma_valid; /* data valid */ +input cdp_dp2wdma_ready; /* data return handshake */ +output [1*8 +14:0] cdp_dp2wdma_pd; +input nvdla_core_clk_orig; +/////////////////////////////////////////////////////////////////// +reg sqsum_bypass_en; +//: my $icvto = (8 +1); +//: my $k = 1; +//: print qq( +//: wire [${k}*${icvto}+14:0] bufin_pd; +//: wire [${k}*${icvto}+14:0] cvt2buf_pd; +//: wire [${k}*${icvto}+14:0] cvt2sync_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] cvtin_out_int8_ext; +//: wire [${k}*(${icvto}*2+3)-1:0] lutctrl_in_pd; +//: wire [${k}*(${icvto}+16)-1:0] mul2ocvt_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] sum2itp_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] sum2sync_pd; +//: wire [${k}*(${icvto}*2+3)-1:0] sync2itp_pd; +//: wire [${k}*${icvto}-1:0] sync2mul_pd; +//: ); +wire bufin_prdy; +wire bufin_pvld; +wire cvt2buf_prdy; +wire cvt2buf_pvld; +wire cvt2sync_prdy; +wire cvt2sync_pvld; +//: my $k = 1; +//: my $icvto = (8 +1); +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${icvto}-1:0] cvtin_out_int8_$m; +//: wire [9:0] dp2lut_X_entry_${m} ; +//: wire [17:0] dp2lut_Xinfo_${m} ; +//: wire [9:0] dp2lut_Y_entry_${m} ; +//: wire [17:0] dp2lut_Yinfo_${m} ; +//: ); +//: } +wire dp2lut_prdy; +wire dp2lut_pvld; +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [16:0] intp2mul_pd_$m; +//: wire [31:0] lut2intp_X_data_${m}0; +//: wire [16:0] lut2intp_X_data_${m}0_17b; +//: wire [31:0] lut2intp_X_data_${m}1; +//: wire [19:0] lut2intp_X_info_${m}; +//: ); +//: } +wire intp2mul_prdy; +wire intp2mul_pvld; +wire [1 -1:0] lut2intp_X_sel; +wire [1 -1:0] lut2intp_Y_sel; +wire lut2intp_prdy; +wire lut2intp_pvld; +wire lutctrl_in_pvld; +wire mul2ocvt_prdy; +wire mul2ocvt_pvld; +//: my $icvto = (8 +1); +//: my $tp = 1; +//: my $k = (${tp}+8)*${icvto}+15; +//: print "wire [${k}-1:0] normalz_buf_data; \n"; +wire normalz_buf_data_prdy; +wire normalz_buf_data_pvld; +wire sum2itp_prdy; +wire sum2itp_pvld; +wire sum2sync_prdy; +wire sum2sync_pvld; +wire sync2itp_prdy; +wire sync2itp_pvld; +wire sync2mul_prdy; +wire sync2mul_pvld; +wire [14:0] sync2ocvt_pd; +wire sync2ocvt_prdy; +wire sync2ocvt_pvld; +/////////////////////////////////////////////////////// +assign dp2reg_d0_out_saturation = 32'd0;//for spyglass +assign dp2reg_d1_out_saturation = 32'd0;//for spyglass +///////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sqsum_bypass_en <= 1'b0; + end else begin + sqsum_bypass_en <= reg2dp_sqsum_bypass == 1'h1; + end +end +//===== convertor_in Instance======== +assign cvt2buf_prdy = sqsum_bypass_en ? sum2itp_prdy : bufin_prdy; +NV_NVDLA_CDP_DP_cvtin u_NV_NVDLA_CDP_DP_cvtin ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) + ,.cvt2buf_prdy (cvt2buf_prdy) + ,.cvt2sync_prdy (cvt2sync_prdy) + ,.reg2dp_datin_offset (reg2dp_datin_offset[15:0]) + ,.reg2dp_datin_scale (reg2dp_datin_scale[15:0]) + ,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0]) + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) + ,.cvt2buf_pd (cvt2buf_pd) + ,.cvt2buf_pvld (cvt2buf_pvld) + ,.cvt2sync_pd (cvt2sync_pd) + ,.cvt2sync_pvld (cvt2sync_pvld) + ); +//===== sync fifo Instance======== +NV_NVDLA_CDP_DP_syncfifo u_NV_NVDLA_CDP_DP_syncfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cvt2sync_pd (cvt2sync_pd) + ,.cvt2sync_pvld (cvt2sync_pvld) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.sum2sync_pd (sum2sync_pd) + ,.sum2sync_pvld (sum2sync_pvld) + ,.sync2itp_prdy (sync2itp_prdy) + ,.sync2mul_prdy (sync2mul_prdy) + ,.sync2ocvt_prdy (sync2ocvt_prdy) + ,.cvt2sync_prdy (cvt2sync_prdy) + ,.sum2sync_prdy (sum2sync_prdy) + ,.sync2itp_pd (sync2itp_pd) + ,.sync2itp_pvld (sync2itp_pvld) + ,.sync2mul_pd (sync2mul_pd) + ,.sync2mul_pvld (sync2mul_pvld) + ,.sync2ocvt_pd (sync2ocvt_pd[14:0]) + ,.sync2ocvt_pvld (sync2ocvt_pvld) + ); +//===== Buffer_in Instance======== +assign bufin_pd = sqsum_bypass_en ? 0 : cvt2buf_pd; +assign bufin_pvld = sqsum_bypass_en ? 0 : cvt2buf_pvld; +//: if(1 >= 4) { +//: print qq( +//: NV_NVDLA_CDP_DP_bufferin u_NV_NVDLA_CDP_DP_bufferin ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cdp_rdma2dp_pd (bufin_pd) +//: ,.cdp_rdma2dp_valid (bufin_pvld) +//: ,.normalz_buf_data_prdy (normalz_buf_data_prdy) +//: ,.cdp_rdma2dp_ready (bufin_prdy) +//: ,.normalz_buf_data (normalz_buf_data) +//: ,.normalz_buf_data_pvld (normalz_buf_data_pvld) +//: ); +//: ); +//: } elsif(1 < 4) { +//: print qq( +//: NV_NVDLA_CDP_DP_bufferin_tp1 u_NV_NVDLA_CDP_DP_bufferin ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cdp_rdma2dp_pd (bufin_pd) +//: ,.cdp_rdma2dp_valid (bufin_pvld) +//: ,.normalz_buf_data_prdy (normalz_buf_data_prdy) +//: ,.cdp_rdma2dp_ready (bufin_prdy) +//: ,.normalz_buf_data (normalz_buf_data) +//: ,.normalz_buf_data_pvld (normalz_buf_data_pvld) +//: ); +//: ); +//: } +//===== sigma squre Instance======== +NV_NVDLA_CDP_DP_sum u_NV_NVDLA_CDP_DP_sum ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.normalz_buf_data (normalz_buf_data) + ,.normalz_buf_data_pvld (normalz_buf_data_pvld) + ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.sum2itp_prdy (sum2itp_prdy) + ,.normalz_buf_data_prdy (normalz_buf_data_prdy) + ,.sum2itp_pd (sum2itp_pd) + ,.sum2itp_pvld (sum2itp_pvld) + ); +//===== LUT controller Instance======== +//: my $icvto = (8 +1); +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign cvtin_out_int8_$m = cvt2buf_pd[${m}*${icvto}+${icvto}-1:${m}*${icvto}]; +//: ); +//: } +assign cvtin_out_int8_ext = { +//: my $k = 1; +//: my $icvto = (8 +1); +//: if($k > 1) { +//: foreach my $m (0..$k-1) { +//: print qq( +//: {{(${icvto}+3){cvtin_out_int8_${m}[${icvto}-1]}}, cvtin_out_int8_${m}}, +//: ); +//: } +//: } +//: print "{{(${icvto}+3){cvtin_out_int8_0[${icvto}-1]}}, cvtin_out_int8_0}}; \n"; +assign lutctrl_in_pd = sqsum_bypass_en ? cvtin_out_int8_ext : sum2itp_pd; +assign lutctrl_in_pvld = sqsum_bypass_en ? cvt2buf_pvld : sum2itp_pvld; +NV_NVDLA_CDP_DP_LUT_ctrl u_NV_NVDLA_CDP_DP_LUT_ctrl ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2lut_prdy (dp2lut_prdy) //|< w + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i + ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|< i + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|< i + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|< i + ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|< i + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|< i + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|< i + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) //|< i + ,.sum2itp_pd (lutctrl_in_pd) //|< w + ,.sum2itp_pvld (lutctrl_in_pvld) //|< w + ,.sum2sync_prdy (sum2sync_prdy) //|< w +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.dp2lut_X_entry_${m} (dp2lut_X_entry_${m} ) +//: ,.dp2lut_Xinfo_${m} (dp2lut_Xinfo_${m} ) +//: ,.dp2lut_Y_entry_${m} (dp2lut_Y_entry_${m} ) +//: ,.dp2lut_Yinfo_${m} (dp2lut_Yinfo_${m} ) +//: ); +//: } + ,.dp2lut_pvld (dp2lut_pvld) //|> w + ,.sum2itp_prdy (sum2itp_prdy) //|> w + ,.sum2sync_pd (sum2sync_pd) //|> w + ,.sum2sync_pvld (sum2sync_pvld) //|> w + ); +//===== LUT Instance======== +NV_NVDLA_CDP_DP_lut u_NV_NVDLA_CDP_DP_lut ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_clk_orig (nvdla_core_clk_orig) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.dp2lut_X_entry_${m} (dp2lut_X_entry_${m} ) +//: ,.dp2lut_Xinfo_${m} (dp2lut_Xinfo_${m} ) +//: ,.dp2lut_Y_entry_${m} (dp2lut_Y_entry_${m} ) +//: ,.dp2lut_Yinfo_${m} (dp2lut_Yinfo_${m} ) +//: ); +//: } + ,.dp2lut_pvld (dp2lut_pvld) //|< w + ,.lut2intp_prdy (lut2intp_prdy) //|< w + ,.reg2dp_lut_access_type (reg2dp_lut_access_type) //|< i + ,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) //|< i + ,.reg2dp_lut_data (reg2dp_lut_data[15:0]) //|< i + ,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) //|< i + ,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|< i + ,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) //|< i + ,.reg2dp_lut_table_id (reg2dp_lut_table_id) //|< i + ,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) //|< i + ,.dp2lut_prdy (dp2lut_prdy) //|> w + ,.dp2reg_lut_data (dp2reg_lut_data[15:0]) //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.lut2intp_X_data_${m}0 (lut2intp_X_data_${m}0 ) +//: ,.lut2intp_X_data_${m}0_17b (lut2intp_X_data_${m}0_17b ) +//: ,.lut2intp_X_data_${m}1 (lut2intp_X_data_${m}1 ) +//: ,.lut2intp_X_info_${m} (lut2intp_X_info_${m} ) +//: ); +//: } + ,.lut2intp_X_sel (lut2intp_X_sel) //|> w + ,.lut2intp_Y_sel (lut2intp_Y_sel) //|> w + ,.lut2intp_pvld (lut2intp_pvld) //|> w + ); +//===== interpolator Instance======== +NV_NVDLA_CDP_DP_intp u_NV_NVDLA_CDP_DP_intp ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_done (dp2reg_done) //|< i + ,.intp2mul_prdy (intp2mul_prdy) //|< w +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.lut2intp_X_data_${m}0 (lut2intp_X_data_${m}0 ) +//: ,.lut2intp_X_data_${m}0_17b (lut2intp_X_data_${m}0_17b ) +//: ,.lut2intp_X_data_${m}1 (lut2intp_X_data_${m}1 ) +//: ,.lut2intp_X_info_${m} (lut2intp_X_info_${m} ) +//: ); +//: } + ,.lut2intp_X_sel (lut2intp_X_sel) //|< w + ,.lut2intp_Y_sel (lut2intp_Y_sel) //|< w + ,.lut2intp_pvld (lut2intp_pvld) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) //|< i + ,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) //|< i + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) //|< i + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|< i + ,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|< i + ,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|< i + ,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|< i + ,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|< i + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|< i + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|< i + ,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) //|< i + ,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) //|< i + ,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|< i + ,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|< i + ,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|< i + ,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|< i + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|< i + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|< i + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) //|< i + ,.sync2itp_pd (sync2itp_pd ) //|< w + ,.sync2itp_pvld (sync2itp_pvld) //|< w + ,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) //|> o + ,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) //|> o + ,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) //|> o + ,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) //|> o + ,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) //|> o + ,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) //|> o + ,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) //|> o + ,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) //|> o + ,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) //|> o + ,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) //|> o +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.intp2mul_pd_$m (intp2mul_pd_${m}[16:0]) //|> w +//: ); +//: } + ,.intp2mul_pvld (intp2mul_pvld) //|> w + ,.lut2intp_prdy (lut2intp_prdy) //|> w + ,.sync2itp_prdy (sync2itp_prdy) //|> w + ); +//===== DP multiple Instance======== +NV_NVDLA_CDP_DP_mul u_NV_NVDLA_CDP_DP_mul ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: my $k = 1; +//: foreach my $m (0..$k-1) { +//: print qq( +//: ,.intp2mul_pd_$m (intp2mul_pd_${m}[16:0]) //|> w +//: ); +//: } + ,.intp2mul_pvld (intp2mul_pvld) //|< w + ,.mul2ocvt_prdy (mul2ocvt_prdy) //|< w + ,.reg2dp_mul_bypass (reg2dp_mul_bypass) //|< i + ,.sync2mul_pd (sync2mul_pd) //|< w + ,.sync2mul_pvld (sync2mul_pvld) //|< w + ,.intp2mul_prdy (intp2mul_prdy) //|> w + ,.mul2ocvt_pd (mul2ocvt_pd) //|> w + ,.mul2ocvt_pvld (mul2ocvt_pvld) //|> w + ,.sync2mul_prdy (sync2mul_prdy) //|> w + ); +//===== convertor_out Instance======== +NV_NVDLA_CDP_DP_cvtout u_NV_NVDLA_CDP_DP_cvtout ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvtout_prdy (cdp_dp2wdma_ready) //|< i + ,.mul2ocvt_pd (mul2ocvt_pd) //|< w + ,.mul2ocvt_pvld (mul2ocvt_pvld) //|< w + ,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) //|< i + ,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) //|< i + ,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) //|< i + ,.sync2ocvt_pd (sync2ocvt_pd[14:0]) //|< w + ,.sync2ocvt_pvld (sync2ocvt_pvld) //|< w + ,.cvtout_pd (cdp_dp2wdma_pd) //|> o + ,.cvtout_pvld (cdp_dp2wdma_valid) //|> o + ,.mul2ocvt_prdy (mul2ocvt_prdy) //|> w + ,.sync2ocvt_prdy (sync2ocvt_prdy) //|> w + ); +////============== +////OBS signals +////============== +//assign obs_bus_cdp_rdma2dp_vld = cdp_rdma2dp_valid; +//assign obs_bus_cdp_rdma2dp_rdy = cdp_rdma2dp_ready; +//assign obs_bus_cdp_icvt_vld = cvt2buf_pvld; +//assign obs_bus_cdp_icvt_rdy = cvt2buf_prdy; +//assign obs_bus_cdp_buf_vld = normalz_buf_data_pvld; +//assign obs_bus_cdp_buf_rdy = normalz_buf_data_prdy; +//assign obs_bus_cdp_sum_vld = sum2itp_pvld; +//assign obs_bus_cdp_sum_rdy = sum2itp_prdy; +//assign obs_bus_cdp_lutctrl_vld = dp2lut_pvld; +//assign obs_bus_cdp_lutctrl_rdy = dp2lut_prdy; +//assign obs_bus_cdp_intp_vld = intp2mul_pvld; +//assign obs_bus_cdp_intp_rdy = intp2mul_prdy; +//assign obs_bus_cdp_ocvt_vld = cdp_dp2wdma_valid; +//assign obs_bus_cdp_ocvt_rdy = cdp_dp2wdma_ready; +endmodule // NV_NVDLA_CDP_dp diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v new file mode 100644 index 0000000..5879ea6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v @@ -0,0 +1,184 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_rdma.v +module NV_NVDLA_CDP_rdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,cdp2mcif_rd_req_valid //|> o + ,cdp2mcif_rd_req_ready //|< i + ,cdp2mcif_rd_req_pd //|> o + ,cdp_rdma2csb_resp_valid //|> o + ,cdp_rdma2csb_resp_pd //|> o + ,cdp_rdma2dp_valid //|> o + ,cdp_rdma2dp_ready //|< i + ,cdp_rdma2dp_pd //|> o + ,csb2cdp_rdma_req_pvld //|< i + ,csb2cdp_rdma_req_prdy //|> o + ,csb2cdp_rdma_req_pd //|< i + ,mcif2cdp_rd_rsp_valid //|< i + ,mcif2cdp_rd_rsp_ready //|> o + ,mcif2cdp_rd_rsp_pd //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ); +// +// NV_NVDLA_CDP_rdma_ports.v +// + input nvdla_core_clk; /* cdp2cvif_rd_cdt, cdp2cvif_rd_req, cdp2mcif_rd_cdt, cdp2mcif_rd_req, cdp_rdma2csb_resp, cdp_rdma2dp, csb2cdp_rdma_req, cvif2cdp_rd_rsp, mcif2cdp_rd_rsp */ + input nvdla_core_rstn; /* cdp2cvif_rd_cdt, cdp2cvif_rd_req, cdp2mcif_rd_cdt, cdp2mcif_rd_req, cdp_rdma2csb_resp, cdp_rdma2dp, csb2cdp_rdma_req, cvif2cdp_rd_rsp, mcif2cdp_rd_rsp */ + output cdp2mcif_rd_cdt_lat_fifo_pop; + output cdp2mcif_rd_req_valid; /* data valid */ + input cdp2mcif_rd_req_ready; /* data return handshake */ + output [47 -1:0] cdp2mcif_rd_req_pd; + output cdp_rdma2csb_resp_valid; /* data valid */ + output [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + output cdp_rdma2dp_valid; /* data valid */ + input cdp_rdma2dp_ready; /* data return handshake */ + output [1*8 +22:0] cdp_rdma2dp_pd; + input csb2cdp_rdma_req_pvld; /* data valid */ + output csb2cdp_rdma_req_prdy; /* data return handshake */ + input [62:0] csb2cdp_rdma_req_pd; + input mcif2cdp_rd_rsp_valid; /* data valid */ + output mcif2cdp_rd_rsp_ready; /* data return handshake */ + input [65 -1:0] mcif2cdp_rd_rsp_pd; + input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire [6:0] cq_rd_pd; +wire cq_rd_prdy; +wire cq_rd_pvld; +wire [6:0] cq_wr_pd; +wire cq_wr_prdy; +wire cq_wr_pvld; +wire [31:0] dp2reg_d0_perf_read_stall; +wire [31:0] dp2reg_d1_perf_read_stall; +wire dp2reg_done; +wire eg2ig_done; +wire nvdla_op_gated_clk; +wire [12:0] reg2dp_channel; +wire [31:0] reg2dp_cya; +wire [0:0] reg2dp_dma_en; +wire [12:0] reg2dp_height; +wire [1:0] reg2dp_input_data; +wire [0:0] reg2dp_op_en; +wire [31:0] reg2dp_src_base_addr_high; +wire [31:0] reg2dp_src_base_addr_low; +wire [31:0] reg2dp_src_line_stride; +wire [0:0] reg2dp_src_ram_type; +wire [31:0] reg2dp_src_surface_stride; +wire [12:0] reg2dp_width; +wire slcg_op_en; +//======================================= +// SLCG gen unit +//--------------------------------------- +NV_NVDLA_CDP_slcg u_slcg ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src (slcg_op_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk) //|> w + ); +//======================================= +// Ingress: send read request to external mem +//--------------------------------------- + NV_NVDLA_CDP_RDMA_ig u_ig ( + .reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_dma_en (reg2dp_dma_en[0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_input_data (reg2dp_input_data[1:0]) //|< w + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type[0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|> w + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|> w + ,.eg2ig_done (eg2ig_done) //|< w + ,.nvdla_core_clk (nvdla_op_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid) //|> o + ,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready) //|< i + ,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd) //|> o + ,.cq_wr_pvld (cq_wr_pvld) //|> w + ,.cq_wr_prdy (cq_wr_prdy) //|< w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|> w + ); +//======================================= +// Context Queue: trace outstanding req, and pass info from Ig to Eg +//--------------------------------------- + NV_NVDLA_CDP_RDMA_cq u_cq ( + .nvdla_core_clk (nvdla_op_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cq_wr_prdy (cq_wr_prdy) //|> w + ,.cq_wr_pvld (cq_wr_pvld) //|< w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|< w + ,.cq_rd_prdy (cq_rd_prdy) //|< w + ,.cq_rd_pvld (cq_rd_pvld) //|> w + ,.cq_rd_pd (cq_rd_pd[6:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//======================================= +// Egress: get return data from external mem +//--------------------------------------- + NV_NVDLA_CDP_RDMA_eg u_eg ( + .reg2dp_channel (reg2dp_channel[4:0]) //|< w + ,.reg2dp_input_data (reg2dp_input_data[1:0]) //|< w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< w + ,.dp2reg_done (dp2reg_done) //|> w + ,.eg2ig_done (eg2ig_done) //|> w + ,.nvdla_core_clk (nvdla_op_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid) //|< i + ,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready) //|> o + ,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd) //|< i + ,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) //|> o + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) //|< i + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) //|> o + ,.cq_rd_pvld (cq_rd_pvld) //|< w + ,.cq_rd_prdy (cq_rd_prdy) //|> w + ,.cq_rd_pd (cq_rd_pd[6:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//======================================== +//CFG: Configure Registers +//---------------------------------------- + NV_NVDLA_CDP_RDMA_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd[62:0]) //|< i + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) //|< i + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|< w + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd[33:0]) //|> o + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) //|> o + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) //|> o + ,.reg2dp_channel (reg2dp_channel[12:0]) //|> w + ,.reg2dp_cya (reg2dp_cya[31:0]) //|> w * + ,.reg2dp_dma_en (reg2dp_dma_en) //|> w + ,.reg2dp_height (reg2dp_height[12:0]) //|> w + ,.reg2dp_input_data (reg2dp_input_data[1:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|> w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) //|> w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) //|> w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|> w + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) //|> w + ,.reg2dp_width (reg2dp_width[12:0]) //|> w + ,.slcg_op_en (slcg_op_en) //|> w + ); +endmodule // NV_NVDLA_CDP_rdma diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v.vcp new file mode 100644 index 0000000..5879ea6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v.vcp @@ -0,0 +1,184 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_rdma.v +module NV_NVDLA_CDP_rdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,cdp2mcif_rd_req_valid //|> o + ,cdp2mcif_rd_req_ready //|< i + ,cdp2mcif_rd_req_pd //|> o + ,cdp_rdma2csb_resp_valid //|> o + ,cdp_rdma2csb_resp_pd //|> o + ,cdp_rdma2dp_valid //|> o + ,cdp_rdma2dp_ready //|< i + ,cdp_rdma2dp_pd //|> o + ,csb2cdp_rdma_req_pvld //|< i + ,csb2cdp_rdma_req_prdy //|> o + ,csb2cdp_rdma_req_pd //|< i + ,mcif2cdp_rd_rsp_valid //|< i + ,mcif2cdp_rd_rsp_ready //|> o + ,mcif2cdp_rd_rsp_pd //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ); +// +// NV_NVDLA_CDP_rdma_ports.v +// + input nvdla_core_clk; /* cdp2cvif_rd_cdt, cdp2cvif_rd_req, cdp2mcif_rd_cdt, cdp2mcif_rd_req, cdp_rdma2csb_resp, cdp_rdma2dp, csb2cdp_rdma_req, cvif2cdp_rd_rsp, mcif2cdp_rd_rsp */ + input nvdla_core_rstn; /* cdp2cvif_rd_cdt, cdp2cvif_rd_req, cdp2mcif_rd_cdt, cdp2mcif_rd_req, cdp_rdma2csb_resp, cdp_rdma2dp, csb2cdp_rdma_req, cvif2cdp_rd_rsp, mcif2cdp_rd_rsp */ + output cdp2mcif_rd_cdt_lat_fifo_pop; + output cdp2mcif_rd_req_valid; /* data valid */ + input cdp2mcif_rd_req_ready; /* data return handshake */ + output [47 -1:0] cdp2mcif_rd_req_pd; + output cdp_rdma2csb_resp_valid; /* data valid */ + output [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + output cdp_rdma2dp_valid; /* data valid */ + input cdp_rdma2dp_ready; /* data return handshake */ + output [1*8 +22:0] cdp_rdma2dp_pd; + input csb2cdp_rdma_req_pvld; /* data valid */ + output csb2cdp_rdma_req_prdy; /* data return handshake */ + input [62:0] csb2cdp_rdma_req_pd; + input mcif2cdp_rd_rsp_valid; /* data valid */ + output mcif2cdp_rd_rsp_ready; /* data return handshake */ + input [65 -1:0] mcif2cdp_rd_rsp_pd; + input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire [6:0] cq_rd_pd; +wire cq_rd_prdy; +wire cq_rd_pvld; +wire [6:0] cq_wr_pd; +wire cq_wr_prdy; +wire cq_wr_pvld; +wire [31:0] dp2reg_d0_perf_read_stall; +wire [31:0] dp2reg_d1_perf_read_stall; +wire dp2reg_done; +wire eg2ig_done; +wire nvdla_op_gated_clk; +wire [12:0] reg2dp_channel; +wire [31:0] reg2dp_cya; +wire [0:0] reg2dp_dma_en; +wire [12:0] reg2dp_height; +wire [1:0] reg2dp_input_data; +wire [0:0] reg2dp_op_en; +wire [31:0] reg2dp_src_base_addr_high; +wire [31:0] reg2dp_src_base_addr_low; +wire [31:0] reg2dp_src_line_stride; +wire [0:0] reg2dp_src_ram_type; +wire [31:0] reg2dp_src_surface_stride; +wire [12:0] reg2dp_width; +wire slcg_op_en; +//======================================= +// SLCG gen unit +//--------------------------------------- +NV_NVDLA_CDP_slcg u_slcg ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src (slcg_op_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk) //|> w + ); +//======================================= +// Ingress: send read request to external mem +//--------------------------------------- + NV_NVDLA_CDP_RDMA_ig u_ig ( + .reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_dma_en (reg2dp_dma_en[0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_input_data (reg2dp_input_data[1:0]) //|< w + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type[0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|> w + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|> w + ,.eg2ig_done (eg2ig_done) //|< w + ,.nvdla_core_clk (nvdla_op_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid) //|> o + ,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready) //|< i + ,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd) //|> o + ,.cq_wr_pvld (cq_wr_pvld) //|> w + ,.cq_wr_prdy (cq_wr_prdy) //|< w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|> w + ); +//======================================= +// Context Queue: trace outstanding req, and pass info from Ig to Eg +//--------------------------------------- + NV_NVDLA_CDP_RDMA_cq u_cq ( + .nvdla_core_clk (nvdla_op_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cq_wr_prdy (cq_wr_prdy) //|> w + ,.cq_wr_pvld (cq_wr_pvld) //|< w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|< w + ,.cq_rd_prdy (cq_rd_prdy) //|< w + ,.cq_rd_pvld (cq_rd_pvld) //|> w + ,.cq_rd_pd (cq_rd_pd[6:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//======================================= +// Egress: get return data from external mem +//--------------------------------------- + NV_NVDLA_CDP_RDMA_eg u_eg ( + .reg2dp_channel (reg2dp_channel[4:0]) //|< w + ,.reg2dp_input_data (reg2dp_input_data[1:0]) //|< w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< w + ,.dp2reg_done (dp2reg_done) //|> w + ,.eg2ig_done (eg2ig_done) //|> w + ,.nvdla_core_clk (nvdla_op_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid) //|< i + ,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready) //|> o + ,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd) //|< i + ,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) //|> o + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) //|< i + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) //|> o + ,.cq_rd_pvld (cq_rd_pvld) //|< w + ,.cq_rd_prdy (cq_rd_prdy) //|> w + ,.cq_rd_pd (cq_rd_pd[6:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//======================================== +//CFG: Configure Registers +//---------------------------------------- + NV_NVDLA_CDP_RDMA_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd[62:0]) //|< i + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) //|< i + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|< w + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd[33:0]) //|> o + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) //|> o + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) //|> o + ,.reg2dp_channel (reg2dp_channel[12:0]) //|> w + ,.reg2dp_cya (reg2dp_cya[31:0]) //|> w * + ,.reg2dp_dma_en (reg2dp_dma_en) //|> w + ,.reg2dp_height (reg2dp_height[12:0]) //|> w + ,.reg2dp_input_data (reg2dp_input_data[1:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|> w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) //|> w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) //|> w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|> w + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) //|> w + ,.reg2dp_width (reg2dp_width[12:0]) //|> w + ,.slcg_op_en (slcg_op_en) //|> w + ); +endmodule // NV_NVDLA_CDP_rdma diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v new file mode 100644 index 0000000..8f22249 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v @@ -0,0 +1,1448 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cdp_req_pd //|< i + ,csb2cdp_req_pvld //|< i + ,dp2reg_d0_out_saturation //|< i + ,dp2reg_d0_perf_lut_hybrid //|< i + ,dp2reg_d0_perf_lut_le_hit //|< i + ,dp2reg_d0_perf_lut_lo_hit //|< i + ,dp2reg_d0_perf_lut_oflow //|< i + ,dp2reg_d0_perf_lut_uflow //|< i + ,dp2reg_d0_perf_write_stall //|< i + ,dp2reg_d1_out_saturation //|< i + ,dp2reg_d1_perf_lut_hybrid //|< i + ,dp2reg_d1_perf_lut_le_hit //|< i + ,dp2reg_d1_perf_lut_lo_hit //|< i + ,dp2reg_d1_perf_lut_oflow //|< i + ,dp2reg_d1_perf_lut_uflow //|< i + ,dp2reg_d1_perf_write_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_inf_input_num //|< i + ,dp2reg_lut_data //|< i + ,dp2reg_nan_input_num //|< i + ,dp2reg_nan_output_num //|< i + ,cdp2csb_resp_pd //|> o + ,cdp2csb_resp_valid //|> o + ,csb2cdp_req_prdy //|> o + ,reg2dp_cya //|> o + ,reg2dp_datin_offset //|> o + ,reg2dp_datin_scale //|> o + ,reg2dp_datin_shifter //|> o + ,reg2dp_datout_offset //|> o + ,reg2dp_datout_scale //|> o + ,reg2dp_datout_shifter //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_dst_base_addr_high //|> o + ,reg2dp_dst_base_addr_low //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_ram_type //|> o + ,reg2dp_dst_surface_stride //|> o + ,reg2dp_input_data_type //|> o + ,reg2dp_interrupt_ptr //|> o + ,reg2dp_lut_access_type //|> o + ,reg2dp_lut_addr //|> o + ,reg2dp_lut_data //|> o + ,reg2dp_lut_data_trigger //|> o + ,reg2dp_lut_en //|> o + ,reg2dp_lut_hybrid_priority //|> o + ,reg2dp_lut_le_end_high //|> o + ,reg2dp_lut_le_end_low //|> o + ,reg2dp_lut_le_function //|> o + ,reg2dp_lut_le_index_offset //|> o + ,reg2dp_lut_le_index_select //|> o + ,reg2dp_lut_le_slope_oflow_scale //|> o + ,reg2dp_lut_le_slope_oflow_shift //|> o + ,reg2dp_lut_le_slope_uflow_scale //|> o + ,reg2dp_lut_le_slope_uflow_shift //|> o + ,reg2dp_lut_le_start_high //|> o + ,reg2dp_lut_le_start_low //|> o + ,reg2dp_lut_lo_end_high //|> o + ,reg2dp_lut_lo_end_low //|> o + ,reg2dp_lut_lo_index_select //|> o + ,reg2dp_lut_lo_slope_oflow_scale //|> o + ,reg2dp_lut_lo_slope_oflow_shift //|> o + ,reg2dp_lut_lo_slope_uflow_scale //|> o + ,reg2dp_lut_lo_slope_uflow_shift //|> o + ,reg2dp_lut_lo_start_high //|> o + ,reg2dp_lut_lo_start_low //|> o + ,reg2dp_lut_oflow_priority //|> o + ,reg2dp_lut_table_id //|> o + ,reg2dp_lut_uflow_priority //|> o + ,reg2dp_mul_bypass //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_normalz_len //|> o + ,reg2dp_op_en //|> o + ,reg2dp_sqsum_bypass //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cdp_req_pd; +input csb2cdp_req_pvld; +input [31:0] dp2reg_d0_out_saturation; +input [31:0] dp2reg_d0_perf_lut_hybrid; +input [31:0] dp2reg_d0_perf_lut_le_hit; +input [31:0] dp2reg_d0_perf_lut_lo_hit; +input [31:0] dp2reg_d0_perf_lut_oflow; +input [31:0] dp2reg_d0_perf_lut_uflow; +input [31:0] dp2reg_d0_perf_write_stall; +input [31:0] dp2reg_d1_out_saturation; +input [31:0] dp2reg_d1_perf_lut_hybrid; +input [31:0] dp2reg_d1_perf_lut_le_hit; +input [31:0] dp2reg_d1_perf_lut_lo_hit; +input [31:0] dp2reg_d1_perf_lut_oflow; +input [31:0] dp2reg_d1_perf_lut_uflow; +input [31:0] dp2reg_d1_perf_write_stall; +input dp2reg_done; +input [31:0] dp2reg_inf_input_num; +input [15:0] dp2reg_lut_data; +input [31:0] dp2reg_nan_input_num; +input [31:0] dp2reg_nan_output_num; +output [33:0] cdp2csb_resp_pd; +output cdp2csb_resp_valid; +output csb2cdp_req_prdy; +output [31:0] reg2dp_cya; +output [15:0] reg2dp_datin_offset; +output [15:0] reg2dp_datin_scale; +output [4:0] reg2dp_datin_shifter; +output [31:0] reg2dp_datout_offset; +output [15:0] reg2dp_datout_scale; +output [5:0] reg2dp_datout_shifter; +output reg2dp_dma_en; +output [31:0] reg2dp_dst_base_addr_high; +output [31:0] reg2dp_dst_base_addr_low; +output [31:0] reg2dp_dst_line_stride; +output reg2dp_dst_ram_type; +output [31:0] reg2dp_dst_surface_stride; +output [1:0] reg2dp_input_data_type; +output reg2dp_interrupt_ptr; +output reg2dp_lut_access_type; +output [9:0] reg2dp_lut_addr; +output [15:0] reg2dp_lut_data; +output reg2dp_lut_data_trigger; +output reg2dp_lut_en; +output reg2dp_lut_hybrid_priority; +output [5:0] reg2dp_lut_le_end_high; +output [31:0] reg2dp_lut_le_end_low; +output reg2dp_lut_le_function; +output [7:0] reg2dp_lut_le_index_offset; +output [7:0] reg2dp_lut_le_index_select; +output [15:0] reg2dp_lut_le_slope_oflow_scale; +output [4:0] reg2dp_lut_le_slope_oflow_shift; +output [15:0] reg2dp_lut_le_slope_uflow_scale; +output [4:0] reg2dp_lut_le_slope_uflow_shift; +output [5:0] reg2dp_lut_le_start_high; +output [31:0] reg2dp_lut_le_start_low; +output [5:0] reg2dp_lut_lo_end_high; +output [31:0] reg2dp_lut_lo_end_low; +output [7:0] reg2dp_lut_lo_index_select; +output [15:0] reg2dp_lut_lo_slope_oflow_scale; +output [4:0] reg2dp_lut_lo_slope_oflow_shift; +output [15:0] reg2dp_lut_lo_slope_uflow_scale; +output [4:0] reg2dp_lut_lo_slope_uflow_shift; +output [5:0] reg2dp_lut_lo_start_high; +output [31:0] reg2dp_lut_lo_start_low; +output reg2dp_lut_oflow_priority; +output reg2dp_lut_table_id; +output reg2dp_lut_uflow_priority; +output reg2dp_mul_bypass; +output reg2dp_nan_to_zero; +output [1:0] reg2dp_normalz_len; +output reg2dp_op_en; +output reg2dp_sqsum_bypass; +output [3:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire lut_end; +wire [31:0] reg2dp_d0_cya; +wire [15:0] reg2dp_d0_datin_offset; +wire [15:0] reg2dp_d0_datin_scale; +wire [4:0] reg2dp_d0_datin_shifter; +wire [31:0] reg2dp_d0_datout_offset; +wire [15:0] reg2dp_d0_datout_scale; +wire [5:0] reg2dp_d0_datout_shifter; +wire reg2dp_d0_dma_en; +wire [31:0] reg2dp_d0_dst_base_addr_high; +wire [31:0] reg2dp_d0_dst_base_addr_low; +wire [31:0] reg2dp_d0_dst_line_stride; +wire reg2dp_d0_dst_ram_type; +wire [31:0] reg2dp_d0_dst_surface_stride; +wire [1:0] reg2dp_d0_input_data_type; +wire reg2dp_d0_lut_en; +wire reg2dp_d0_mul_bypass; +wire reg2dp_d0_nan_to_zero; +wire [1:0] reg2dp_d0_normalz_len; +wire reg2dp_d0_op_en_trigger; +wire reg2dp_d0_sqsum_bypass; +wire [31:0] reg2dp_d1_cya; +wire [15:0] reg2dp_d1_datin_offset; +wire [15:0] reg2dp_d1_datin_scale; +wire [4:0] reg2dp_d1_datin_shifter; +wire [31:0] reg2dp_d1_datout_offset; +wire [15:0] reg2dp_d1_datout_scale; +wire [5:0] reg2dp_d1_datout_shifter; +wire reg2dp_d1_dma_en; +wire [31:0] reg2dp_d1_dst_base_addr_high; +wire [31:0] reg2dp_d1_dst_base_addr_low; +wire [31:0] reg2dp_d1_dst_line_stride; +wire reg2dp_d1_dst_ram_type; +wire [31:0] reg2dp_d1_dst_surface_stride; +wire [1:0] reg2dp_d1_input_data_type; +wire reg2dp_d1_lut_en; +wire reg2dp_d1_mul_bypass; +wire reg2dp_d1_nan_to_zero; +wire [1:0] reg2dp_d1_normalz_len; +wire reg2dp_d1_op_en_trigger; +wire reg2dp_d1_sqsum_bypass; +wire reg2dp_lut_addr_trigger; +wire reg2dp_lut_data_rd_trigger; +wire reg2dp_lut_data_wr_trigger; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_offset_wr; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en_d0; +reg [33:0] cdp2csb_resp_pd; +reg cdp2csb_resp_valid; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_inf_input_num; +reg [31:0] dp2reg_d0_inf_input_num_w; +reg [31:0] dp2reg_d0_nan_input_num; +reg [31:0] dp2reg_d0_nan_input_num_w; +reg [31:0] dp2reg_d0_nan_output_num; +reg [31:0] dp2reg_d0_nan_output_num_w; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_inf_input_num; +reg [31:0] dp2reg_d1_inf_input_num_w; +reg [31:0] dp2reg_d1_nan_input_num; +reg [31:0] dp2reg_d1_nan_input_num_w; +reg [31:0] dp2reg_d1_nan_output_num; +reg [31:0] dp2reg_d1_nan_output_num_w; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [9:0] dp2reg_lut_addr; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [15:0] reg2dp_datin_offset; +reg [15:0] reg2dp_datin_scale; +reg [4:0] reg2dp_datin_shifter; +reg [31:0] reg2dp_datout_offset; +reg [15:0] reg2dp_datout_scale; +reg [5:0] reg2dp_datout_shifter; +reg reg2dp_dma_en; +reg [31:0] reg2dp_dst_base_addr_high; +reg [31:0] reg2dp_dst_base_addr_low; +reg [31:0] reg2dp_dst_line_stride; +reg reg2dp_dst_ram_type; +reg [31:0] reg2dp_dst_surface_stride; +reg [1:0] reg2dp_input_data_type; +reg reg2dp_lut_en; +reg reg2dp_mul_bypass; +reg reg2dp_nan_to_zero; +reg [1:0] reg2dp_normalz_len; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg reg2dp_sqsum_bypass; +reg [62:0] req_pd; +reg req_pvld; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CDP_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_access_type (reg2dp_lut_access_type) //|> o + ,.lut_addr_trigger (reg2dp_lut_addr_trigger) //|> w + ,.lut_table_id (reg2dp_lut_table_id) //|> o + ,.lut_data_trigger (reg2dp_lut_data_trigger) //|> o + ,.lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|> o + ,.lut_le_function (reg2dp_lut_le_function) //|> o + ,.lut_oflow_priority (reg2dp_lut_oflow_priority) //|> o + ,.lut_uflow_priority (reg2dp_lut_uflow_priority) //|> o + ,.lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|> o + ,.lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|> o + ,.lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|> o + ,.lut_le_end_high (reg2dp_lut_le_end_high[5:0]) //|> o + ,.lut_le_end_low (reg2dp_lut_le_end_low[31:0]) //|> o + ,.lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|> o + ,.lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|> o + ,.lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|> o + ,.lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|> o + ,.lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|> o + ,.lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|> o + ,.lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) //|> o + ,.lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) //|> o + ,.lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|> o + ,.lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|> o + ,.lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|> o + ,.lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|> o + ,.lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|> o + ,.lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|> o + ,.producer (reg2dp_producer) //|> w + ,.lut_addr (dp2reg_lut_addr[9:0]) //|< r + ,.lut_data (dp2reg_lut_data[15:0]) //|< i + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CDP_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.input_data_type (reg2dp_d0_input_data_type[1:0]) //|> w + ,.datin_offset (reg2dp_d0_datin_offset[15:0]) //|> w + ,.datin_scale (reg2dp_d0_datin_scale[15:0]) //|> w + ,.datin_shifter (reg2dp_d0_datin_shifter[4:0]) //|> w + ,.datout_offset (reg2dp_d0_datout_offset[31:0]) //|> w + ,.datout_scale (reg2dp_d0_datout_scale[15:0]) //|> w + ,.datout_shifter (reg2dp_d0_datout_shifter[5:0]) //|> w + ,.dst_base_addr_high (reg2dp_d0_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d0_dst_base_addr_low[31:0]) //|> w + ,.dst_ram_type (reg2dp_d0_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d0_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d0_dst_surface_stride[31:0]) //|> w + ,.mul_bypass (reg2dp_d0_mul_bypass) //|> w + ,.sqsum_bypass (reg2dp_d0_sqsum_bypass) //|> w + ,.normalz_len (reg2dp_d0_normalz_len[1:0]) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.lut_en (reg2dp_d0_lut_en) //|> w + ,.inf_input_num (dp2reg_d0_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d0_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d0_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d0_op_en) //|< r + ,.out_saturation (dp2reg_d0_out_saturation[31:0]) //|< i + ,.perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) //|< i + ,.perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) //|< i + ,.perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) //|< i + ,.perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) //|< i + ,.perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) //|< i + ,.perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) //|< i + ); +NV_NVDLA_CDP_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.input_data_type (reg2dp_d1_input_data_type[1:0]) //|> w + ,.datin_offset (reg2dp_d1_datin_offset[15:0]) //|> w + ,.datin_scale (reg2dp_d1_datin_scale[15:0]) //|> w + ,.datin_shifter (reg2dp_d1_datin_shifter[4:0]) //|> w + ,.datout_offset (reg2dp_d1_datout_offset[31:0]) //|> w + ,.datout_scale (reg2dp_d1_datout_scale[15:0]) //|> w + ,.datout_shifter (reg2dp_d1_datout_shifter[5:0]) //|> w + ,.dst_base_addr_high (reg2dp_d1_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d1_dst_base_addr_low[31:0]) //|> w + ,.dst_ram_type (reg2dp_d1_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d1_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d1_dst_surface_stride[31:0]) //|> w + ,.mul_bypass (reg2dp_d1_mul_bypass) //|> w + ,.sqsum_bypass (reg2dp_d1_sqsum_bypass) //|> w + ,.normalz_len (reg2dp_d1_normalz_len[1:0]) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.lut_en (reg2dp_d1_lut_en) //|> w + ,.inf_input_num (dp2reg_d1_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d1_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d1_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d1_op_en) //|< r + ,.out_saturation (dp2reg_d1_out_saturation[31:0]) //|< i + ,.perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) //|< i + ,.perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) //|< i + ,.perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) //|< i + ,.perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) //|< i + ,.perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) //|< i + ,.perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hf048 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hf048 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hf048 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cdp_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cdp_req_pvld) == 1'b1) begin + req_pd <= csb2cdp_req_pd; +// VCS coverage off + end else if ((csb2cdp_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cdp_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cdp_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cdp2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cdp2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2csb_resp_valid <= 1'b0; + end else begin + cdp2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data_type + or reg2dp_d0_input_data_type + ) begin + reg2dp_input_data_type = dp2reg_consumer ? reg2dp_d1_input_data_type : reg2dp_d0_input_data_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_datin_offset + or reg2dp_d0_datin_offset + ) begin + reg2dp_datin_offset = dp2reg_consumer ? reg2dp_d1_datin_offset : reg2dp_d0_datin_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_datin_scale + or reg2dp_d0_datin_scale + ) begin + reg2dp_datin_scale = dp2reg_consumer ? reg2dp_d1_datin_scale : reg2dp_d0_datin_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_datin_shifter + or reg2dp_d0_datin_shifter + ) begin + reg2dp_datin_shifter = dp2reg_consumer ? reg2dp_d1_datin_shifter : reg2dp_d0_datin_shifter; +end +always @( + dp2reg_consumer + or reg2dp_d1_datout_offset + or reg2dp_d0_datout_offset + ) begin + reg2dp_datout_offset = dp2reg_consumer ? reg2dp_d1_datout_offset : reg2dp_d0_datout_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_datout_scale + or reg2dp_d0_datout_scale + ) begin + reg2dp_datout_scale = dp2reg_consumer ? reg2dp_d1_datout_scale : reg2dp_d0_datout_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_datout_shifter + or reg2dp_d0_datout_shifter + ) begin + reg2dp_datout_shifter = dp2reg_consumer ? reg2dp_d1_datout_shifter : reg2dp_d0_datout_shifter; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_high + or reg2dp_d0_dst_base_addr_high + ) begin + reg2dp_dst_base_addr_high = dp2reg_consumer ? reg2dp_d1_dst_base_addr_high : reg2dp_d0_dst_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_low + or reg2dp_d0_dst_base_addr_low + ) begin + reg2dp_dst_base_addr_low = dp2reg_consumer ? reg2dp_d1_dst_base_addr_low : reg2dp_d0_dst_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_ram_type + or reg2dp_d0_dst_ram_type + ) begin + reg2dp_dst_ram_type = dp2reg_consumer ? reg2dp_d1_dst_ram_type : reg2dp_d0_dst_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_line_stride + or reg2dp_d0_dst_line_stride + ) begin + reg2dp_dst_line_stride = dp2reg_consumer ? reg2dp_d1_dst_line_stride : reg2dp_d0_dst_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_surface_stride + or reg2dp_d0_dst_surface_stride + ) begin + reg2dp_dst_surface_stride = dp2reg_consumer ? reg2dp_d1_dst_surface_stride : reg2dp_d0_dst_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_mul_bypass + or reg2dp_d0_mul_bypass + ) begin + reg2dp_mul_bypass = dp2reg_consumer ? reg2dp_d1_mul_bypass : reg2dp_d0_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_sqsum_bypass + or reg2dp_d0_sqsum_bypass + ) begin + reg2dp_sqsum_bypass = dp2reg_consumer ? reg2dp_d1_sqsum_bypass : reg2dp_d0_sqsum_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_normalz_len + or reg2dp_d0_normalz_len + ) begin + reg2dp_normalz_len = dp2reg_consumer ? reg2dp_d1_normalz_len : reg2dp_d0_normalz_len; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_lut_en + or reg2dp_d0_lut_en + ) begin + reg2dp_lut_en = dp2reg_consumer ? reg2dp_d1_lut_en : reg2dp_d0_lut_en; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +assign reg2dp_lut_data = reg_wr_data[15:0]; +assign reg2dp_interrupt_ptr = dp2reg_consumer; +//lut_addr generate logic +// .reg_rd_data (s_reg_rd_data[31:0]) //|> w +// ,.reg_offset (s_reg_offset[11:0]) //|< w +// ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w +// ,.reg_wr_en (s_reg_wr_en) //|< w +//&Always posedge; +// if(reg2dp_lut_addr_trigger) +// reg2dp_lut_addr[9:0] <0= s_reg_wr_data[31:0]; +// else if(reg2dp_lut_data_trigger | reg2dp_lut_data_rd_trigger) +// reg2dp_lut_addr[9:0] <0= reg2dp_lut_addr[9:0] + 1'b1; +//&End; +assign reg_offset_wr = {20'b0 , s_reg_offset[11:0]}; +//assign reg2dp_lut_data_wr_trigger = (reg_offset_wr == (32'h1000c & 32'h00000fff)) & s_reg_wr_en & reg2dp_lut_access_type; //spyglass disable UnloadedNet-ML //(W528) +assign reg2dp_lut_data_wr_trigger = (reg_offset_wr == (32'h1000c & 32'h00000fff)) & s_reg_wr_en & (reg2dp_lut_access_type == 1'h1 ); //spyglass disable UnloadedNet-ML //(W528) +//assign reg2dp_lut_data_rd_trigger = (reg_offset_wr == (NVDLA_CDP_S_LUT_ACCESS_DATA_0 & 32'h00000fff)) & (!s_reg_wr_en) & (reg2dp_lut_access_type == NVDLA_CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ); //spyglass disable UnloadedNet-ML //(W528) +assign reg2dp_lut_data_rd_trigger = (reg_offset_wr == (32'hf00c & 32'h00000fff)) & (reg_rd_en & select_s) & (reg2dp_lut_access_type == 1'h0 ); //spyglass disable UnloadedNet-ML //(W528) +assign lut_end = (dp2reg_lut_addr == ((reg2dp_lut_table_id)? 10'd256 : 10'd64)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_lut_addr[9:0] <= {10{1'b0}}; + end else begin + if(reg2dp_lut_addr_trigger) + dp2reg_lut_addr[9:0] <= s_reg_wr_data[9:0]; + else if(reg2dp_lut_data_wr_trigger | reg2dp_lut_data_rd_trigger) begin + if(lut_end) + dp2reg_lut_addr[9:0] <= dp2reg_lut_addr[9:0]; + else + dp2reg_lut_addr[9:0] <= dp2reg_lut_addr[9:0] + 1'b1; + end + end +end +assign reg2dp_lut_addr[9:0] = dp2reg_lut_addr[9:0]; +//////// for general counting register //////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for NaN and infinity counting registers //////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_nan_input_num + or dp2reg_d0_clr + or dp2reg_d0_nan_input_num + ) begin + dp2reg_d0_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_nan_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_input_num + or dp2reg_d0_clr + or dp2reg_d0_inf_input_num + ) begin + dp2reg_d0_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_inf_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_nan_output_num + or dp2reg_d0_clr + or dp2reg_d0_nan_output_num + ) begin + dp2reg_d0_nan_output_num_w = (dp2reg_d0_set) ? dp2reg_nan_output_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_input_num <= dp2reg_d0_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_input_num <= dp2reg_d0_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_output_num <= dp2reg_d0_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_nan_input_num + or dp2reg_d1_clr + or dp2reg_d1_nan_input_num + ) begin + dp2reg_d1_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_nan_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_input_num + or dp2reg_d1_clr + or dp2reg_d1_inf_input_num + ) begin + dp2reg_d1_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_inf_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_nan_output_num + or dp2reg_d1_clr + or dp2reg_d1_nan_output_num + ) begin + dp2reg_d1_nan_output_num_w = (dp2reg_d1_set) ? dp2reg_nan_output_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_input_num <= dp2reg_d1_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_input_num <= dp2reg_d1_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_output_num <= dp2reg_d1_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDP_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v.vcp new file mode 100644 index 0000000..8f22249 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v.vcp @@ -0,0 +1,1448 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cdp_req_pd //|< i + ,csb2cdp_req_pvld //|< i + ,dp2reg_d0_out_saturation //|< i + ,dp2reg_d0_perf_lut_hybrid //|< i + ,dp2reg_d0_perf_lut_le_hit //|< i + ,dp2reg_d0_perf_lut_lo_hit //|< i + ,dp2reg_d0_perf_lut_oflow //|< i + ,dp2reg_d0_perf_lut_uflow //|< i + ,dp2reg_d0_perf_write_stall //|< i + ,dp2reg_d1_out_saturation //|< i + ,dp2reg_d1_perf_lut_hybrid //|< i + ,dp2reg_d1_perf_lut_le_hit //|< i + ,dp2reg_d1_perf_lut_lo_hit //|< i + ,dp2reg_d1_perf_lut_oflow //|< i + ,dp2reg_d1_perf_lut_uflow //|< i + ,dp2reg_d1_perf_write_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_inf_input_num //|< i + ,dp2reg_lut_data //|< i + ,dp2reg_nan_input_num //|< i + ,dp2reg_nan_output_num //|< i + ,cdp2csb_resp_pd //|> o + ,cdp2csb_resp_valid //|> o + ,csb2cdp_req_prdy //|> o + ,reg2dp_cya //|> o + ,reg2dp_datin_offset //|> o + ,reg2dp_datin_scale //|> o + ,reg2dp_datin_shifter //|> o + ,reg2dp_datout_offset //|> o + ,reg2dp_datout_scale //|> o + ,reg2dp_datout_shifter //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_dst_base_addr_high //|> o + ,reg2dp_dst_base_addr_low //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_ram_type //|> o + ,reg2dp_dst_surface_stride //|> o + ,reg2dp_input_data_type //|> o + ,reg2dp_interrupt_ptr //|> o + ,reg2dp_lut_access_type //|> o + ,reg2dp_lut_addr //|> o + ,reg2dp_lut_data //|> o + ,reg2dp_lut_data_trigger //|> o + ,reg2dp_lut_en //|> o + ,reg2dp_lut_hybrid_priority //|> o + ,reg2dp_lut_le_end_high //|> o + ,reg2dp_lut_le_end_low //|> o + ,reg2dp_lut_le_function //|> o + ,reg2dp_lut_le_index_offset //|> o + ,reg2dp_lut_le_index_select //|> o + ,reg2dp_lut_le_slope_oflow_scale //|> o + ,reg2dp_lut_le_slope_oflow_shift //|> o + ,reg2dp_lut_le_slope_uflow_scale //|> o + ,reg2dp_lut_le_slope_uflow_shift //|> o + ,reg2dp_lut_le_start_high //|> o + ,reg2dp_lut_le_start_low //|> o + ,reg2dp_lut_lo_end_high //|> o + ,reg2dp_lut_lo_end_low //|> o + ,reg2dp_lut_lo_index_select //|> o + ,reg2dp_lut_lo_slope_oflow_scale //|> o + ,reg2dp_lut_lo_slope_oflow_shift //|> o + ,reg2dp_lut_lo_slope_uflow_scale //|> o + ,reg2dp_lut_lo_slope_uflow_shift //|> o + ,reg2dp_lut_lo_start_high //|> o + ,reg2dp_lut_lo_start_low //|> o + ,reg2dp_lut_oflow_priority //|> o + ,reg2dp_lut_table_id //|> o + ,reg2dp_lut_uflow_priority //|> o + ,reg2dp_mul_bypass //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_normalz_len //|> o + ,reg2dp_op_en //|> o + ,reg2dp_sqsum_bypass //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cdp_req_pd; +input csb2cdp_req_pvld; +input [31:0] dp2reg_d0_out_saturation; +input [31:0] dp2reg_d0_perf_lut_hybrid; +input [31:0] dp2reg_d0_perf_lut_le_hit; +input [31:0] dp2reg_d0_perf_lut_lo_hit; +input [31:0] dp2reg_d0_perf_lut_oflow; +input [31:0] dp2reg_d0_perf_lut_uflow; +input [31:0] dp2reg_d0_perf_write_stall; +input [31:0] dp2reg_d1_out_saturation; +input [31:0] dp2reg_d1_perf_lut_hybrid; +input [31:0] dp2reg_d1_perf_lut_le_hit; +input [31:0] dp2reg_d1_perf_lut_lo_hit; +input [31:0] dp2reg_d1_perf_lut_oflow; +input [31:0] dp2reg_d1_perf_lut_uflow; +input [31:0] dp2reg_d1_perf_write_stall; +input dp2reg_done; +input [31:0] dp2reg_inf_input_num; +input [15:0] dp2reg_lut_data; +input [31:0] dp2reg_nan_input_num; +input [31:0] dp2reg_nan_output_num; +output [33:0] cdp2csb_resp_pd; +output cdp2csb_resp_valid; +output csb2cdp_req_prdy; +output [31:0] reg2dp_cya; +output [15:0] reg2dp_datin_offset; +output [15:0] reg2dp_datin_scale; +output [4:0] reg2dp_datin_shifter; +output [31:0] reg2dp_datout_offset; +output [15:0] reg2dp_datout_scale; +output [5:0] reg2dp_datout_shifter; +output reg2dp_dma_en; +output [31:0] reg2dp_dst_base_addr_high; +output [31:0] reg2dp_dst_base_addr_low; +output [31:0] reg2dp_dst_line_stride; +output reg2dp_dst_ram_type; +output [31:0] reg2dp_dst_surface_stride; +output [1:0] reg2dp_input_data_type; +output reg2dp_interrupt_ptr; +output reg2dp_lut_access_type; +output [9:0] reg2dp_lut_addr; +output [15:0] reg2dp_lut_data; +output reg2dp_lut_data_trigger; +output reg2dp_lut_en; +output reg2dp_lut_hybrid_priority; +output [5:0] reg2dp_lut_le_end_high; +output [31:0] reg2dp_lut_le_end_low; +output reg2dp_lut_le_function; +output [7:0] reg2dp_lut_le_index_offset; +output [7:0] reg2dp_lut_le_index_select; +output [15:0] reg2dp_lut_le_slope_oflow_scale; +output [4:0] reg2dp_lut_le_slope_oflow_shift; +output [15:0] reg2dp_lut_le_slope_uflow_scale; +output [4:0] reg2dp_lut_le_slope_uflow_shift; +output [5:0] reg2dp_lut_le_start_high; +output [31:0] reg2dp_lut_le_start_low; +output [5:0] reg2dp_lut_lo_end_high; +output [31:0] reg2dp_lut_lo_end_low; +output [7:0] reg2dp_lut_lo_index_select; +output [15:0] reg2dp_lut_lo_slope_oflow_scale; +output [4:0] reg2dp_lut_lo_slope_oflow_shift; +output [15:0] reg2dp_lut_lo_slope_uflow_scale; +output [4:0] reg2dp_lut_lo_slope_uflow_shift; +output [5:0] reg2dp_lut_lo_start_high; +output [31:0] reg2dp_lut_lo_start_low; +output reg2dp_lut_oflow_priority; +output reg2dp_lut_table_id; +output reg2dp_lut_uflow_priority; +output reg2dp_mul_bypass; +output reg2dp_nan_to_zero; +output [1:0] reg2dp_normalz_len; +output reg2dp_op_en; +output reg2dp_sqsum_bypass; +output [3:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire lut_end; +wire [31:0] reg2dp_d0_cya; +wire [15:0] reg2dp_d0_datin_offset; +wire [15:0] reg2dp_d0_datin_scale; +wire [4:0] reg2dp_d0_datin_shifter; +wire [31:0] reg2dp_d0_datout_offset; +wire [15:0] reg2dp_d0_datout_scale; +wire [5:0] reg2dp_d0_datout_shifter; +wire reg2dp_d0_dma_en; +wire [31:0] reg2dp_d0_dst_base_addr_high; +wire [31:0] reg2dp_d0_dst_base_addr_low; +wire [31:0] reg2dp_d0_dst_line_stride; +wire reg2dp_d0_dst_ram_type; +wire [31:0] reg2dp_d0_dst_surface_stride; +wire [1:0] reg2dp_d0_input_data_type; +wire reg2dp_d0_lut_en; +wire reg2dp_d0_mul_bypass; +wire reg2dp_d0_nan_to_zero; +wire [1:0] reg2dp_d0_normalz_len; +wire reg2dp_d0_op_en_trigger; +wire reg2dp_d0_sqsum_bypass; +wire [31:0] reg2dp_d1_cya; +wire [15:0] reg2dp_d1_datin_offset; +wire [15:0] reg2dp_d1_datin_scale; +wire [4:0] reg2dp_d1_datin_shifter; +wire [31:0] reg2dp_d1_datout_offset; +wire [15:0] reg2dp_d1_datout_scale; +wire [5:0] reg2dp_d1_datout_shifter; +wire reg2dp_d1_dma_en; +wire [31:0] reg2dp_d1_dst_base_addr_high; +wire [31:0] reg2dp_d1_dst_base_addr_low; +wire [31:0] reg2dp_d1_dst_line_stride; +wire reg2dp_d1_dst_ram_type; +wire [31:0] reg2dp_d1_dst_surface_stride; +wire [1:0] reg2dp_d1_input_data_type; +wire reg2dp_d1_lut_en; +wire reg2dp_d1_mul_bypass; +wire reg2dp_d1_nan_to_zero; +wire [1:0] reg2dp_d1_normalz_len; +wire reg2dp_d1_op_en_trigger; +wire reg2dp_d1_sqsum_bypass; +wire reg2dp_lut_addr_trigger; +wire reg2dp_lut_data_rd_trigger; +wire reg2dp_lut_data_wr_trigger; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_offset_wr; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en_d0; +reg [33:0] cdp2csb_resp_pd; +reg cdp2csb_resp_valid; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_inf_input_num; +reg [31:0] dp2reg_d0_inf_input_num_w; +reg [31:0] dp2reg_d0_nan_input_num; +reg [31:0] dp2reg_d0_nan_input_num_w; +reg [31:0] dp2reg_d0_nan_output_num; +reg [31:0] dp2reg_d0_nan_output_num_w; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_inf_input_num; +reg [31:0] dp2reg_d1_inf_input_num_w; +reg [31:0] dp2reg_d1_nan_input_num; +reg [31:0] dp2reg_d1_nan_input_num_w; +reg [31:0] dp2reg_d1_nan_output_num; +reg [31:0] dp2reg_d1_nan_output_num_w; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [9:0] dp2reg_lut_addr; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [15:0] reg2dp_datin_offset; +reg [15:0] reg2dp_datin_scale; +reg [4:0] reg2dp_datin_shifter; +reg [31:0] reg2dp_datout_offset; +reg [15:0] reg2dp_datout_scale; +reg [5:0] reg2dp_datout_shifter; +reg reg2dp_dma_en; +reg [31:0] reg2dp_dst_base_addr_high; +reg [31:0] reg2dp_dst_base_addr_low; +reg [31:0] reg2dp_dst_line_stride; +reg reg2dp_dst_ram_type; +reg [31:0] reg2dp_dst_surface_stride; +reg [1:0] reg2dp_input_data_type; +reg reg2dp_lut_en; +reg reg2dp_mul_bypass; +reg reg2dp_nan_to_zero; +reg [1:0] reg2dp_normalz_len; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg reg2dp_sqsum_bypass; +reg [62:0] req_pd; +reg req_pvld; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CDP_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_access_type (reg2dp_lut_access_type) //|> o + ,.lut_addr_trigger (reg2dp_lut_addr_trigger) //|> w + ,.lut_table_id (reg2dp_lut_table_id) //|> o + ,.lut_data_trigger (reg2dp_lut_data_trigger) //|> o + ,.lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|> o + ,.lut_le_function (reg2dp_lut_le_function) //|> o + ,.lut_oflow_priority (reg2dp_lut_oflow_priority) //|> o + ,.lut_uflow_priority (reg2dp_lut_uflow_priority) //|> o + ,.lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|> o + ,.lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|> o + ,.lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|> o + ,.lut_le_end_high (reg2dp_lut_le_end_high[5:0]) //|> o + ,.lut_le_end_low (reg2dp_lut_le_end_low[31:0]) //|> o + ,.lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|> o + ,.lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|> o + ,.lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|> o + ,.lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|> o + ,.lut_le_start_high (reg2dp_lut_le_start_high[5:0]) //|> o + ,.lut_le_start_low (reg2dp_lut_le_start_low[31:0]) //|> o + ,.lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) //|> o + ,.lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) //|> o + ,.lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|> o + ,.lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|> o + ,.lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|> o + ,.lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|> o + ,.lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) //|> o + ,.lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) //|> o + ,.producer (reg2dp_producer) //|> w + ,.lut_addr (dp2reg_lut_addr[9:0]) //|< r + ,.lut_data (dp2reg_lut_data[15:0]) //|< i + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CDP_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.input_data_type (reg2dp_d0_input_data_type[1:0]) //|> w + ,.datin_offset (reg2dp_d0_datin_offset[15:0]) //|> w + ,.datin_scale (reg2dp_d0_datin_scale[15:0]) //|> w + ,.datin_shifter (reg2dp_d0_datin_shifter[4:0]) //|> w + ,.datout_offset (reg2dp_d0_datout_offset[31:0]) //|> w + ,.datout_scale (reg2dp_d0_datout_scale[15:0]) //|> w + ,.datout_shifter (reg2dp_d0_datout_shifter[5:0]) //|> w + ,.dst_base_addr_high (reg2dp_d0_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d0_dst_base_addr_low[31:0]) //|> w + ,.dst_ram_type (reg2dp_d0_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d0_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d0_dst_surface_stride[31:0]) //|> w + ,.mul_bypass (reg2dp_d0_mul_bypass) //|> w + ,.sqsum_bypass (reg2dp_d0_sqsum_bypass) //|> w + ,.normalz_len (reg2dp_d0_normalz_len[1:0]) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.lut_en (reg2dp_d0_lut_en) //|> w + ,.inf_input_num (dp2reg_d0_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d0_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d0_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d0_op_en) //|< r + ,.out_saturation (dp2reg_d0_out_saturation[31:0]) //|< i + ,.perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) //|< i + ,.perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) //|< i + ,.perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) //|< i + ,.perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) //|< i + ,.perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) //|< i + ,.perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) //|< i + ); +NV_NVDLA_CDP_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.input_data_type (reg2dp_d1_input_data_type[1:0]) //|> w + ,.datin_offset (reg2dp_d1_datin_offset[15:0]) //|> w + ,.datin_scale (reg2dp_d1_datin_scale[15:0]) //|> w + ,.datin_shifter (reg2dp_d1_datin_shifter[4:0]) //|> w + ,.datout_offset (reg2dp_d1_datout_offset[31:0]) //|> w + ,.datout_scale (reg2dp_d1_datout_scale[15:0]) //|> w + ,.datout_shifter (reg2dp_d1_datout_shifter[5:0]) //|> w + ,.dst_base_addr_high (reg2dp_d1_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d1_dst_base_addr_low[31:0]) //|> w + ,.dst_ram_type (reg2dp_d1_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d1_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d1_dst_surface_stride[31:0]) //|> w + ,.mul_bypass (reg2dp_d1_mul_bypass) //|> w + ,.sqsum_bypass (reg2dp_d1_sqsum_bypass) //|> w + ,.normalz_len (reg2dp_d1_normalz_len[1:0]) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.lut_en (reg2dp_d1_lut_en) //|> w + ,.inf_input_num (dp2reg_d1_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d1_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d1_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d1_op_en) //|< r + ,.out_saturation (dp2reg_d1_out_saturation[31:0]) //|< i + ,.perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) //|< i + ,.perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) //|< i + ,.perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) //|< i + ,.perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) //|< i + ,.perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) //|< i + ,.perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hf048 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hf048 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hf048 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cdp_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cdp_req_pvld) == 1'b1) begin + req_pd <= csb2cdp_req_pd; +// VCS coverage off + end else if ((csb2cdp_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cdp_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cdp_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cdp2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cdp2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2csb_resp_valid <= 1'b0; + end else begin + cdp2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data_type + or reg2dp_d0_input_data_type + ) begin + reg2dp_input_data_type = dp2reg_consumer ? reg2dp_d1_input_data_type : reg2dp_d0_input_data_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_datin_offset + or reg2dp_d0_datin_offset + ) begin + reg2dp_datin_offset = dp2reg_consumer ? reg2dp_d1_datin_offset : reg2dp_d0_datin_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_datin_scale + or reg2dp_d0_datin_scale + ) begin + reg2dp_datin_scale = dp2reg_consumer ? reg2dp_d1_datin_scale : reg2dp_d0_datin_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_datin_shifter + or reg2dp_d0_datin_shifter + ) begin + reg2dp_datin_shifter = dp2reg_consumer ? reg2dp_d1_datin_shifter : reg2dp_d0_datin_shifter; +end +always @( + dp2reg_consumer + or reg2dp_d1_datout_offset + or reg2dp_d0_datout_offset + ) begin + reg2dp_datout_offset = dp2reg_consumer ? reg2dp_d1_datout_offset : reg2dp_d0_datout_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_datout_scale + or reg2dp_d0_datout_scale + ) begin + reg2dp_datout_scale = dp2reg_consumer ? reg2dp_d1_datout_scale : reg2dp_d0_datout_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_datout_shifter + or reg2dp_d0_datout_shifter + ) begin + reg2dp_datout_shifter = dp2reg_consumer ? reg2dp_d1_datout_shifter : reg2dp_d0_datout_shifter; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_high + or reg2dp_d0_dst_base_addr_high + ) begin + reg2dp_dst_base_addr_high = dp2reg_consumer ? reg2dp_d1_dst_base_addr_high : reg2dp_d0_dst_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_low + or reg2dp_d0_dst_base_addr_low + ) begin + reg2dp_dst_base_addr_low = dp2reg_consumer ? reg2dp_d1_dst_base_addr_low : reg2dp_d0_dst_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_ram_type + or reg2dp_d0_dst_ram_type + ) begin + reg2dp_dst_ram_type = dp2reg_consumer ? reg2dp_d1_dst_ram_type : reg2dp_d0_dst_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_line_stride + or reg2dp_d0_dst_line_stride + ) begin + reg2dp_dst_line_stride = dp2reg_consumer ? reg2dp_d1_dst_line_stride : reg2dp_d0_dst_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_surface_stride + or reg2dp_d0_dst_surface_stride + ) begin + reg2dp_dst_surface_stride = dp2reg_consumer ? reg2dp_d1_dst_surface_stride : reg2dp_d0_dst_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_mul_bypass + or reg2dp_d0_mul_bypass + ) begin + reg2dp_mul_bypass = dp2reg_consumer ? reg2dp_d1_mul_bypass : reg2dp_d0_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_sqsum_bypass + or reg2dp_d0_sqsum_bypass + ) begin + reg2dp_sqsum_bypass = dp2reg_consumer ? reg2dp_d1_sqsum_bypass : reg2dp_d0_sqsum_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_normalz_len + or reg2dp_d0_normalz_len + ) begin + reg2dp_normalz_len = dp2reg_consumer ? reg2dp_d1_normalz_len : reg2dp_d0_normalz_len; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_lut_en + or reg2dp_d0_lut_en + ) begin + reg2dp_lut_en = dp2reg_consumer ? reg2dp_d1_lut_en : reg2dp_d0_lut_en; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +assign reg2dp_lut_data = reg_wr_data[15:0]; +assign reg2dp_interrupt_ptr = dp2reg_consumer; +//lut_addr generate logic +// .reg_rd_data (s_reg_rd_data[31:0]) //|> w +// ,.reg_offset (s_reg_offset[11:0]) //|< w +// ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w +// ,.reg_wr_en (s_reg_wr_en) //|< w +//&Always posedge; +// if(reg2dp_lut_addr_trigger) +// reg2dp_lut_addr[9:0] <0= s_reg_wr_data[31:0]; +// else if(reg2dp_lut_data_trigger | reg2dp_lut_data_rd_trigger) +// reg2dp_lut_addr[9:0] <0= reg2dp_lut_addr[9:0] + 1'b1; +//&End; +assign reg_offset_wr = {20'b0 , s_reg_offset[11:0]}; +//assign reg2dp_lut_data_wr_trigger = (reg_offset_wr == (32'h1000c & 32'h00000fff)) & s_reg_wr_en & reg2dp_lut_access_type; //spyglass disable UnloadedNet-ML //(W528) +assign reg2dp_lut_data_wr_trigger = (reg_offset_wr == (32'h1000c & 32'h00000fff)) & s_reg_wr_en & (reg2dp_lut_access_type == 1'h1 ); //spyglass disable UnloadedNet-ML //(W528) +//assign reg2dp_lut_data_rd_trigger = (reg_offset_wr == (NVDLA_CDP_S_LUT_ACCESS_DATA_0 & 32'h00000fff)) & (!s_reg_wr_en) & (reg2dp_lut_access_type == NVDLA_CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ); //spyglass disable UnloadedNet-ML //(W528) +assign reg2dp_lut_data_rd_trigger = (reg_offset_wr == (32'hf00c & 32'h00000fff)) & (reg_rd_en & select_s) & (reg2dp_lut_access_type == 1'h0 ); //spyglass disable UnloadedNet-ML //(W528) +assign lut_end = (dp2reg_lut_addr == ((reg2dp_lut_table_id)? 10'd256 : 10'd64)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_lut_addr[9:0] <= {10{1'b0}}; + end else begin + if(reg2dp_lut_addr_trigger) + dp2reg_lut_addr[9:0] <= s_reg_wr_data[9:0]; + else if(reg2dp_lut_data_wr_trigger | reg2dp_lut_data_rd_trigger) begin + if(lut_end) + dp2reg_lut_addr[9:0] <= dp2reg_lut_addr[9:0]; + else + dp2reg_lut_addr[9:0] <= dp2reg_lut_addr[9:0] + 1'b1; + end + end +end +assign reg2dp_lut_addr[9:0] = dp2reg_lut_addr[9:0]; +//////// for general counting register //////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for NaN and infinity counting registers //////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_nan_input_num + or dp2reg_d0_clr + or dp2reg_d0_nan_input_num + ) begin + dp2reg_d0_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_nan_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_input_num + or dp2reg_d0_clr + or dp2reg_d0_inf_input_num + ) begin + dp2reg_d0_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_inf_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_nan_output_num + or dp2reg_d0_clr + or dp2reg_d0_nan_output_num + ) begin + dp2reg_d0_nan_output_num_w = (dp2reg_d0_set) ? dp2reg_nan_output_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_input_num <= dp2reg_d0_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_input_num <= dp2reg_d0_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_output_num <= dp2reg_d0_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_nan_input_num + or dp2reg_d1_clr + or dp2reg_d1_nan_input_num + ) begin + dp2reg_d1_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_nan_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_input_num + or dp2reg_d1_clr + or dp2reg_d1_inf_input_num + ) begin + dp2reg_d1_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_inf_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_nan_output_num + or dp2reg_d1_clr + or dp2reg_d1_nan_output_num + ) begin + dp2reg_d1_nan_output_num_w = (dp2reg_d1_set) ? dp2reg_nan_output_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_input_num <= dp2reg_d1_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_input_num <= dp2reg_d1_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_output_num <= dp2reg_d1_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_CDP_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v new file mode 100644 index 0000000..31381af --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v @@ -0,0 +1,389 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_slcg.v +module NV_NVDLA_CDP_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CDP_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v.vcp new file mode 100644 index 0000000..31381af --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v.vcp @@ -0,0 +1,389 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_slcg.v +module NV_NVDLA_CDP_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CDP_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v new file mode 100644 index 0000000..6bc63cd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v @@ -0,0 +1,3090 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_wdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_wdma ( + nvdla_core_clk + ,nvdla_core_clk_orig + ,nvdla_core_rstn + ,cdp2mcif_wr_req_ready + ,cdp_dp2wdma_pd + ,cdp_dp2wdma_valid + ,mcif2cdp_wr_rsp_complete + ,pwrbus_ram_pd + ,reg2dp_dma_en + ,reg2dp_dst_base_addr_high + ,reg2dp_dst_base_addr_low + ,reg2dp_dst_line_stride + ,reg2dp_dst_ram_type + ,reg2dp_dst_surface_stride + ,reg2dp_interrupt_ptr + ,reg2dp_op_en + ,cdp2glb_done_intr_pd + ,cdp2mcif_wr_req_pd + ,cdp2mcif_wr_req_valid + ,cdp_dp2wdma_ready + ,dp2reg_d0_perf_write_stall + ,dp2reg_d1_perf_write_stall + ,dp2reg_done + ); +//////////////////////////////////////////////////////////////////////////// +// +input nvdla_core_clk; +input nvdla_core_rstn; +output cdp2mcif_wr_req_valid; +input cdp2mcif_wr_req_ready; +output [66 -1:0] cdp2mcif_wr_req_pd; +input mcif2cdp_wr_rsp_complete; +input cdp_dp2wdma_valid; +output cdp_dp2wdma_ready; +input [1*8 +14:0] cdp_dp2wdma_pd; +output [1:0] cdp2glb_done_intr_pd; +input nvdla_core_clk_orig; +input [31:0] pwrbus_ram_pd; +input reg2dp_dma_en; +input [31:0] reg2dp_dst_base_addr_high; +input [31:0] reg2dp_dst_base_addr_low; +input [31:0] reg2dp_dst_line_stride; +input reg2dp_dst_ram_type; +input [31:0] reg2dp_dst_surface_stride; +input reg2dp_interrupt_ptr; +input reg2dp_op_en; +output [31:0] dp2reg_d0_perf_write_stall; +output [31:0] dp2reg_d1_perf_write_stall; +output dp2reg_done; +//////////////////////////////////////////////////////////////////////////// +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg [63:0] base_addr_c; +reg [63:0] base_addr_w; +reg [2:0] beat_cnt; +reg [1:0] cdp2glb_done_intr_pd; +reg [31:0] cdp_wr_stall_count; +reg cmd_en; +reg [2:0] cmd_fifo_rd_pos_w_reg; +reg cv_dma_wr_rsp_complete; +reg cv_pending; +reg dat_en; +reg [63:0] dma_req_addr; +wire dma_wr_rsp_complete; +reg [31:0] dp2reg_d0_perf_write_stall; +reg [31:0] dp2reg_d1_perf_write_stall; +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "reg is_beat_num_odd; \n"; +//: print "wire [0:0] dma_wr_dat_mask; \n";} +//: if($M == 2) { print "reg is_beat_num_odd; \n"; +//: print "wire [1:0] dma_wr_dat_mask; \n";} +//: if($M == 4) { print "reg [1:0] is_beat_num_odd; \n"; +//: print "wire [3:0] dma_wr_dat_mask; \n";} +//: if($M == 8) { print "reg [2:0] is_beat_num_odd; \n"; +//: print "wire [7:0] dma_wr_dat_mask; \n";} +//: if($M == 16) { print "reg [3:0] is_beat_num_odd; \n"; +//: print "wire [15:0] dma_wr_dat_mask; \n";} +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg is_beat_num_odd; +wire [0:0] dma_wr_dat_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//reg is_beat_num_odd; +reg layer_flag; +reg mc_dma_wr_rsp_complete; +reg mc_pending; +reg mon_base_addr_c_c; +reg mon_base_addr_w_c; +reg mon_dma_req_addr_c; +reg mon_nan_in_count; +reg op_prcess; +reg reg_cube_last; +reg [2:0] req_chn_size; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire cdp_wr_stall_count_dec; +wire cmd_accept; +wire cmd_fifo_rd_b_sync; +wire cmd_fifo_rd_b_sync_NC; +wire cmd_fifo_rd_last_c; +wire cmd_fifo_rd_last_h; +wire cmd_fifo_rd_last_w; +wire [14:0] cmd_fifo_rd_pd; +wire [2:0] cmd_fifo_rd_pos_c; +wire [3:0] cmd_fifo_rd_pos_w; +wire cmd_fifo_rd_prdy; +wire cmd_fifo_rd_pvld; +wire [3:0] cmd_fifo_rd_width; +wire [14:0] cmd_fifo_wr_pd; +wire cmd_fifo_wr_prdy; +wire cmd_fifo_wr_pvld; +wire cmd_rdy; +wire cmd_vld; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +wire dat_accept; +wire [64 -1:0] dat_data; +wire dat_fifo_wr_rdy; +wire dat_rdy; +wire dat_vld; +wire [63:0] dma_wr_cmd_addr; +wire [32 +13:0] dma_wr_cmd_pd; +wire dma_wr_cmd_require_ack; +wire [12:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [64 -1:0] dma_wr_dat_data; +wire [66 -2:0] dma_wr_dat_pd; +reg [66 -1:0] dma_wr_req_pd; +wire dma_wr_dat_vld; +wire dma_wr_req_rdy; +wire dma_wr_req_type; +wire dma_wr_req_vld; +wire dp2wdma_b_sync; +wire [14:0] dp2wdma_cmd_pd; +wire [1*8 -1:0] dp2wdma_data; +wire dp2wdma_last_c; +wire dp2wdma_last_h; +wire dp2wdma_last_w; +wire [2:0] dp2wdma_pos_c; +wire [3:0] dp2wdma_pos_w; +wire dp2wdma_pos_w_bit0; +wire dp2wdma_rdy; +wire [3:0] dp2wdma_width; +wire intr_fifo_rd_pd; +wire intr_fifo_rd_prdy; +wire intr_fifo_rd_pvld; +wire intr_fifo_wr_pd; +wire intr_fifo_wr_pvld; +wire is_cube_last; +wire is_last_beat; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire op_done; +wire op_load; +wire [63:0] reg2dp_base_addr; +wire [31:0] reg2dp_line_stride; +wire [31:0] reg2dp_surf_stride; +wire releasing; +wire require_ack; +wire [3:0] width_size; +wire [3:0] width_size_use; +wire wr_req_rdyi; +//////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +assign op_load = reg2dp_op_en & !op_prcess; +assign op_done = reg_cube_last & is_last_beat & dat_accept; +assign dp2reg_done = op_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_prcess <= 1'b0; + end else begin + if (op_load) begin + op_prcess <= 1'b1; + end else if (op_done) begin + op_prcess <= 1'b0; + end + end +end +//============== +// Data INPUT pipe and Unpack +//============== +//: my $k=1*8 +15; +//: &eperl::pipe(" -wid $k -is -do dp2wdma_pd -vo dp2wdma_vld -ri dp2wdma_rdy -di cdp_dp2wdma_pd -vi cdp_dp2wdma_valid -ro cdp_dp2wdma_ready "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg cdp_dp2wdma_ready; +reg skid_flop_cdp_dp2wdma_ready; +reg skid_flop_cdp_dp2wdma_valid; +reg [23-1:0] skid_flop_cdp_dp2wdma_pd; +reg pipe_skid_cdp_dp2wdma_valid; +reg [23-1:0] pipe_skid_cdp_dp2wdma_pd; +// Wire +wire skid_cdp_dp2wdma_valid; +wire [23-1:0] skid_cdp_dp2wdma_pd; +wire skid_cdp_dp2wdma_ready; +wire pipe_skid_cdp_dp2wdma_ready; +wire dp2wdma_vld; +wire [23-1:0] dp2wdma_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_dp2wdma_ready <= 1'b1; + skid_flop_cdp_dp2wdma_ready <= 1'b1; + end else begin + cdp_dp2wdma_ready <= skid_cdp_dp2wdma_ready; + skid_flop_cdp_dp2wdma_ready <= skid_cdp_dp2wdma_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_cdp_dp2wdma_valid <= 1'b0; + end else begin + if (skid_flop_cdp_dp2wdma_ready) begin + skid_flop_cdp_dp2wdma_valid <= cdp_dp2wdma_valid; + end + end +end +assign skid_cdp_dp2wdma_valid = (skid_flop_cdp_dp2wdma_ready) ? cdp_dp2wdma_valid : skid_flop_cdp_dp2wdma_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_cdp_dp2wdma_ready & cdp_dp2wdma_valid) begin + skid_flop_cdp_dp2wdma_pd[23-1:0] <= cdp_dp2wdma_pd[23-1:0]; + end +end +assign skid_cdp_dp2wdma_pd[23-1:0] = (skid_flop_cdp_dp2wdma_ready) ? cdp_dp2wdma_pd[23-1:0] : skid_flop_cdp_dp2wdma_pd[23-1:0]; + + +// PIPE READY +assign skid_cdp_dp2wdma_ready = pipe_skid_cdp_dp2wdma_ready || !pipe_skid_cdp_dp2wdma_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_cdp_dp2wdma_valid <= 1'b0; + end else begin + if (skid_cdp_dp2wdma_ready) begin + pipe_skid_cdp_dp2wdma_valid <= skid_cdp_dp2wdma_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_cdp_dp2wdma_ready && skid_cdp_dp2wdma_valid) begin + pipe_skid_cdp_dp2wdma_pd[23-1:0] <= skid_cdp_dp2wdma_pd[23-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_cdp_dp2wdma_ready = dp2wdma_rdy; +assign dp2wdma_vld = pipe_skid_cdp_dp2wdma_valid; +assign dp2wdma_pd = pipe_skid_cdp_dp2wdma_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp2wdma_data[1*8 -1:0] = dp2wdma_pd[1*8 -1:0]; +assign dp2wdma_pos_w[3:0] = dp2wdma_pd[1*8 +3:1*8]; +assign dp2wdma_width[3:0] = dp2wdma_pd[1*8 +7:1*8 +4]; +assign dp2wdma_pos_c[2:0] = dp2wdma_pd[1*8 +10:1*8 +8]; +assign dp2wdma_b_sync = dp2wdma_pd[1*8 +11]; +assign dp2wdma_last_w = dp2wdma_pd[1*8 +12]; +assign dp2wdma_last_h = dp2wdma_pd[1*8 +13]; +assign dp2wdma_last_c = dp2wdma_pd[1*8 +14]; +assign dp2wdma_cmd_pd[3:0] = dp2wdma_pos_w[3:0]; +assign dp2wdma_cmd_pd[7:4] = dp2wdma_width[3:0]; +assign dp2wdma_cmd_pd[10:8] = dp2wdma_pos_c[2:0]; +assign dp2wdma_cmd_pd[11] = dp2wdma_b_sync ; +assign dp2wdma_cmd_pd[12] = dp2wdma_last_w ; +assign dp2wdma_cmd_pd[13] = dp2wdma_last_h ; +assign dp2wdma_cmd_pd[14] = dp2wdma_last_c ; +/////////////////////////////////////////////////////// +// when b_sync, both cmd.fifo and dat.fifo need be ready, when !b_sync, only dat.fifo need be ready +assign dp2wdma_rdy = dp2wdma_vld & (dp2wdma_b_sync ? (dat_fifo_wr_rdy & cmd_fifo_wr_prdy) : dat_fifo_wr_rdy); +//============== +// Input FIFO : DATA and its swizzle +//============== +//: my $tp = 1*8; +//: my $atmm = 8*8; +//: my $k = 64/$tp; +//: my $M = 64/$atmm; +//: my $F = $atmm/$tp; +//: if($M == 1) { +//: print qq( assign dp2wdma_pos_w_bit0 = 1'b0; ); +//: } elsif($M == 2) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[0]; ); +//: } elsif($M == 4) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[1:0]; ); +//: } elsif($M == 8) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[2:0]; ); +//: } elsif($M == 16) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[3:0]; ); +//: } +//: foreach my $i (0..$M-1) { +//: print "wire dat${i}_rdy; \n"; +//: } +//: my @dat_wr_rdys; +//: foreach my $m (0..$k-1) { +//: my $chn = $m % $F; +//: my $pos = int($m / $F); +//: print qq( +//: wire dat${pos}_fifo${chn}_wr_pvld; +//: wire dat${pos}_fifo${chn}_wr_prdy; +//: wire [$tp-1:0] dat${pos}_fifo${chn}_wr_pd; +//: wire [$tp-1:0] dat${pos}_fifo${chn}_rd_pd; +//: wire dat${pos}_fifo${chn}_rd_prdy; +//: wire dat${pos}_fifo${chn}_rd_pvld; +//: assign dat${pos}_fifo${chn}_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==$chn) & (dp2wdma_pos_w_bit0==$pos); +//: assign dat${pos}_fifo${chn}_wr_pd = dp2wdma_data; +//: NV_NVDLA_CDP_WDMA_dat_fifo u_dat${pos}_fifo${chn} ( +//: .nvdla_core_clk (nvdla_core_clk ) +//: ,.nvdla_core_rstn (nvdla_core_rstn ) +//: ,.dat_fifo_wr_prdy (dat${pos}_fifo${chn}_wr_prdy ) +//: ,.dat_fifo_wr_pvld (dat${pos}_fifo${chn}_wr_pvld ) +//: ,.dat_fifo_wr_pd (dat${pos}_fifo${chn}_wr_pd ) +//: ,.dat_fifo_rd_prdy (dat${pos}_fifo${chn}_rd_prdy ) +//: ,.dat_fifo_rd_pvld (dat${pos}_fifo${chn}_rd_pvld ) +//: ,.dat_fifo_rd_pd (dat${pos}_fifo${chn}_rd_pd ) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +//: ); +//: +//: assign dat${pos}_fifo${chn}_rd_prdy = dat${pos}_rdy & (${chn} <= req_chn_size); +//: ); +//: push @dat_wr_rdys, "(dat${pos}_fifo${chn}_wr_prdy & (dp2wdma_pos_c==$chn) & (dp2wdma_pos_w_bit0==$pos))"; +//: } +//: my $dat_wr_rdys_str = join(" \n| ",@dat_wr_rdys); +//: print "assign dat_fifo_wr_rdy = $dat_wr_rdys_str; "; +//: my $kx = 1*8; ##throughput BW in int8 +//: my $jx = 8*8; ##atomic_m BW in int8 +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$M-1) { +//: print "wire dat${m}_fifo_rd_pvld; \n"; +//: my @dat_vlds_s; +//: foreach my $f (0..$F-1) { +//: push @dat_vlds_s, "dat${m}_fifo${f}_rd_pvld"; +//: } +//: my $dat_vlds_str = join(" \n& ",@dat_vlds_s); +//: print "assign dat${m}_fifo_rd_pvld = $dat_vlds_str; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign dp2wdma_pos_w_bit0 = 1'b0; wire dat0_rdy; + +wire dat0_fifo0_wr_pvld; +wire dat0_fifo0_wr_prdy; +wire [8-1:0] dat0_fifo0_wr_pd; +wire [8-1:0] dat0_fifo0_rd_pd; +wire dat0_fifo0_rd_prdy; +wire dat0_fifo0_rd_pvld; +assign dat0_fifo0_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==0) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo0_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo0 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo0_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo0_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo0_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo0_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo0_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo0_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo0_rd_prdy = dat0_rdy & (0 <= req_chn_size); + +wire dat0_fifo1_wr_pvld; +wire dat0_fifo1_wr_prdy; +wire [8-1:0] dat0_fifo1_wr_pd; +wire [8-1:0] dat0_fifo1_rd_pd; +wire dat0_fifo1_rd_prdy; +wire dat0_fifo1_rd_pvld; +assign dat0_fifo1_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==1) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo1_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo1 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo1_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo1_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo1_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo1_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo1_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo1_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo1_rd_prdy = dat0_rdy & (1 <= req_chn_size); + +wire dat0_fifo2_wr_pvld; +wire dat0_fifo2_wr_prdy; +wire [8-1:0] dat0_fifo2_wr_pd; +wire [8-1:0] dat0_fifo2_rd_pd; +wire dat0_fifo2_rd_prdy; +wire dat0_fifo2_rd_pvld; +assign dat0_fifo2_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==2) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo2_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo2 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo2_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo2_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo2_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo2_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo2_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo2_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo2_rd_prdy = dat0_rdy & (2 <= req_chn_size); + +wire dat0_fifo3_wr_pvld; +wire dat0_fifo3_wr_prdy; +wire [8-1:0] dat0_fifo3_wr_pd; +wire [8-1:0] dat0_fifo3_rd_pd; +wire dat0_fifo3_rd_prdy; +wire dat0_fifo3_rd_pvld; +assign dat0_fifo3_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==3) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo3_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo3 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo3_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo3_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo3_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo3_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo3_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo3_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo3_rd_prdy = dat0_rdy & (3 <= req_chn_size); + +wire dat0_fifo4_wr_pvld; +wire dat0_fifo4_wr_prdy; +wire [8-1:0] dat0_fifo4_wr_pd; +wire [8-1:0] dat0_fifo4_rd_pd; +wire dat0_fifo4_rd_prdy; +wire dat0_fifo4_rd_pvld; +assign dat0_fifo4_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==4) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo4_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo4 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo4_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo4_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo4_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo4_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo4_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo4_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo4_rd_prdy = dat0_rdy & (4 <= req_chn_size); + +wire dat0_fifo5_wr_pvld; +wire dat0_fifo5_wr_prdy; +wire [8-1:0] dat0_fifo5_wr_pd; +wire [8-1:0] dat0_fifo5_rd_pd; +wire dat0_fifo5_rd_prdy; +wire dat0_fifo5_rd_pvld; +assign dat0_fifo5_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==5) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo5_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo5 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo5_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo5_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo5_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo5_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo5_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo5_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo5_rd_prdy = dat0_rdy & (5 <= req_chn_size); + +wire dat0_fifo6_wr_pvld; +wire dat0_fifo6_wr_prdy; +wire [8-1:0] dat0_fifo6_wr_pd; +wire [8-1:0] dat0_fifo6_rd_pd; +wire dat0_fifo6_rd_prdy; +wire dat0_fifo6_rd_pvld; +assign dat0_fifo6_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==6) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo6_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo6 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo6_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo6_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo6_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo6_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo6_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo6_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo6_rd_prdy = dat0_rdy & (6 <= req_chn_size); + +wire dat0_fifo7_wr_pvld; +wire dat0_fifo7_wr_prdy; +wire [8-1:0] dat0_fifo7_wr_pd; +wire [8-1:0] dat0_fifo7_rd_pd; +wire dat0_fifo7_rd_prdy; +wire dat0_fifo7_rd_pvld; +assign dat0_fifo7_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==7) & (dp2wdma_pos_w_bit0==0); +assign dat0_fifo7_wr_pd = dp2wdma_data; +NV_NVDLA_CDP_WDMA_dat_fifo u_dat0_fifo7 ( +.nvdla_core_clk (nvdla_core_clk ) +,.nvdla_core_rstn (nvdla_core_rstn ) +,.dat_fifo_wr_prdy (dat0_fifo7_wr_prdy ) +,.dat_fifo_wr_pvld (dat0_fifo7_wr_pvld ) +,.dat_fifo_wr_pd (dat0_fifo7_wr_pd ) +,.dat_fifo_rd_prdy (dat0_fifo7_rd_prdy ) +,.dat_fifo_rd_pvld (dat0_fifo7_rd_pvld ) +,.dat_fifo_rd_pd (dat0_fifo7_rd_pd ) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +); + +assign dat0_fifo7_rd_prdy = dat0_rdy & (7 <= req_chn_size); +assign dat_fifo_wr_rdy = (dat0_fifo0_wr_prdy & (dp2wdma_pos_c==0) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo1_wr_prdy & (dp2wdma_pos_c==1) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo2_wr_prdy & (dp2wdma_pos_c==2) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo3_wr_prdy & (dp2wdma_pos_c==3) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo4_wr_prdy & (dp2wdma_pos_c==4) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo5_wr_prdy & (dp2wdma_pos_c==5) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo6_wr_prdy & (dp2wdma_pos_c==6) & (dp2wdma_pos_w_bit0==0)) +| (dat0_fifo7_wr_prdy & (dp2wdma_pos_c==7) & (dp2wdma_pos_w_bit0==0)); wire dat0_fifo_rd_pvld; +assign dat0_fifo_rd_pvld = dat0_fifo0_rd_pvld +& dat0_fifo1_rd_pvld +& dat0_fifo2_rd_pvld +& dat0_fifo3_rd_pvld +& dat0_fifo4_rd_pvld +& dat0_fifo5_rd_pvld +& dat0_fifo6_rd_pvld +& dat0_fifo7_rd_pvld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// +// //: my $kx = NVDLA_CDP_THROUGHPUT*NVDLA_CDP_BWPE; ##throughput BW in int8 +// //: my $jx = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_CDP_BWPE; ##atomic_m BW in int8 +// //: my $k = NVDLA_CDP_DMAIF_BW/$kx; ##total fifo num +// //: my $M = NVDLA_CDP_DMAIF_BW/$jx; ##atomic_m number per dma transaction +// //: my $F = $k/$M; ##how many fifo contribute to one atomic_m +// //: foreach my $m (0..$M-1) { +// //: print "&eperl::assert -type never -desc 'CDP-WDMA: dat$m rdys should be all 1 or all 0' -expr ( "; +// // if($F > 1) { +// //: foreach my $f (0..$F-2) { +// //: my $k = $F - $f -1; +// //: print "dat${m}_fifo${k}_rd_prdy & "; +// //: } +// //: } +// //: print "dat${m}_fifo0_rd_prdy)!=("; +// // if($F > 1) { +// //: foreach my $f (0..$F-2) { +// //: my $k = $F - $f -1; +// //: print "dat${m}_fifo${k}_rd_prdy | "; +// //: } +// //: } +// //: print "dat${m}_fifo0_rd_prdy) -clk nvdla_core_clk -rst nvdla_core_rstn; \n"; +// //: } +//DorisLei +//&eperl::assert -type never -desc 'CDP-WDMA: dat0 rdys should be all 1 or all 0' -expr (dat0_fifo0_rd_prdy & dat0_fifo1_rd_prdy & dat0_fifo2_rd_prdy & dat0_fifo3_rd_prdy)!=(dat0_fifo0_rd_prdy | dat0_fifo1_rd_prdy | dat0_fifo2_rd_prdy | dat0_fifo3_rd_prdy) -clk nvdla_core_clk -rst nvdla_core_rstn; +//&eperl::assert -type never -desc 'CDP-WDMA: dat1 rdys should be all 1 or all 0' -expr (dat1_fifo0_rd_prdy & dat1_fifo1_rd_prdy & dat1_fifo2_rd_prdy & dat1_fifo3_rd_prdy)!=(dat1_fifo0_rd_prdy | dat1_fifo1_rd_prdy | dat1_fifo2_rd_prdy | dat1_fifo3_rd_prdy) -clk nvdla_core_clk -rst nvdla_core_rstn; +//: my $kx = 1*8; ##throughput BW in int8 +//: my $jx = 8*8; ##atomic_m BW in int8 +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$M-1) { +//: print "wire [$jx-1:0] dat${m}_data; \n"; +//: print "assign dat${m}_data= { \n"; +//: if($F > 1) { +//: foreach my $k (0..$F-2) { +//: my $j = $F - $k -1; +//: print "dat${m}_fifo${j}_rd_pd,"; +//: } +//: } +//: print "dat${m}_fifo0_rd_pd}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [64-1:0] dat0_data; +assign dat0_data= { +dat0_fifo7_rd_pd,dat0_fifo6_rd_pd,dat0_fifo5_rd_pd,dat0_fifo4_rd_pd,dat0_fifo3_rd_pd,dat0_fifo2_rd_pd,dat0_fifo1_rd_pd,dat0_fifo0_rd_pd}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_data = { +//: my $kx = 1*8; ##throughput BW in int8 +//: my $jx = 8*8; ##atomic_m BW in int8 +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: if($M > 1) { +//: foreach my $k (0..$M-2) { +//: my $j = $M - $k -1; +//: print "dat${j}_data,"; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +dat0_data}; +//============== +// Input FIFO: CMD +//============== +// cmd-fifo control +// if b_sync, need push into both dat_fifo and cmd_fifo +// FIFO:Write side +//assign cmd_fifo_wr_pvld = dp2wdma_vld & (dp2wdma_b_sync & (dp2wdma_pos_c==3'd3)) & dat_fifo_wr_rdy; +assign cmd_fifo_wr_pvld = dp2wdma_vld & (dp2wdma_b_sync & (dp2wdma_pos_c==(8/1 -1))) & dat_fifo_wr_rdy; +assign cmd_fifo_wr_pd = dp2wdma_cmd_pd; +// CMD FIFO:Instance +NV_NVDLA_CDP_WDMA_cmd_fifo u_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_fifo_wr_prdy (cmd_fifo_wr_prdy) //|> w + ,.cmd_fifo_wr_pvld (cmd_fifo_wr_pvld) //|< w + ,.cmd_fifo_wr_pd (cmd_fifo_wr_pd[14:0]) //|< w + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) //|< w + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) //|> w + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[14:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +// CMD FIFO:Read side +assign cmd_fifo_rd_prdy = cmd_en & cmd_rdy; +// Unpack cmd & data together +assign cmd_fifo_rd_pos_w[3:0] = cmd_fifo_rd_pd[3:0]; +assign cmd_fifo_rd_width[3:0] = cmd_fifo_rd_pd[7:4]; +assign cmd_fifo_rd_pos_c[2:0] = cmd_fifo_rd_pd[10:8]; +assign cmd_fifo_rd_b_sync = cmd_fifo_rd_pd[11]; +assign cmd_fifo_rd_last_w = cmd_fifo_rd_pd[12]; +assign cmd_fifo_rd_last_h = cmd_fifo_rd_pd[13]; +assign cmd_fifo_rd_last_c = cmd_fifo_rd_pd[14]; +assign cmd_fifo_rd_b_sync_NC = cmd_fifo_rd_b_sync; +assign is_last_w = cmd_fifo_rd_last_w; +assign is_last_h = cmd_fifo_rd_last_h; +assign is_last_c = cmd_fifo_rd_last_c; +assign is_cube_last = is_last_w & is_last_h & is_last_c; +//============== +// BLOCK Operation +//============== +assign cmd_vld = cmd_en & cmd_fifo_rd_pvld; +assign cmd_rdy = dma_wr_req_rdy; +assign cmd_accept = cmd_vld & cmd_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "is_beat_num_odd <= 1'b0; \n";} +//: if($M == 2) { print "is_beat_num_odd <= 1'b0; \n";} +//: if($M == 4) { print "is_beat_num_odd <= 2'd0; \n";} +//: if($M == 8) { print "is_beat_num_odd <= 3'd0; \n";} +//: if($M == 16) { print "is_beat_num_odd <= 4'd0; \n";} +//| eperl: generated_beg (DO NOT EDIT BELOW) +is_beat_num_odd <= 1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else if ((cmd_accept) == 1'b1) begin +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "is_beat_num_odd <= 1'b0; \n";} +//: if($M == 2) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[0]); \n";} +//: if($M == 4) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[1:0]); \n";} +//: if($M == 8) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[2:0]); \n";} +//: if($M == 16) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[3:0]); \n";} +//| eperl: generated_beg (DO NOT EDIT BELOW) +is_beat_num_odd <= 1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// is_beat_num_odd <= (cmd_fifo_rd_pos_w[0]==0); + end +end +//: my $kx = 1*8; +//: my $jx = 8*8; +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$M-1) { +//: print "wire dat${m}_vld; \n"; +//: print "//wire dat${m}_rdy; \n"; +//: print "assign dat${m}_vld = dat_en & dat${m}_fifo_rd_pvld & !(is_last_beat & (is_beat_num_odd < $m)); \n"; +//: print "assign dat${m}_rdy = dat_en & dat_rdy & !(is_last_beat & (is_beat_num_odd < $m)); \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire dat0_vld; +//wire dat0_rdy; +assign dat0_vld = dat_en & dat0_fifo_rd_pvld & !(is_last_beat & (is_beat_num_odd < 0)); +assign dat0_rdy = dat_en & dat_rdy & !(is_last_beat & (is_beat_num_odd < 0)); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_vld = dat_en & (//dat0_vld | dat1_vld; +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M > 1) { +//: foreach my $m (0..$M-2) { +//: my $k = $M - $m -1; +//: print "dat${k}_vld | "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +dat0_vld); +assign dat_rdy = dat_en & dma_wr_req_rdy; +assign dat_accept = dat_vld & dat_rdy; +// Req.cmd +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (is_last_beat & dat_accept) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else if (cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_cube_last <= 1'b0; + end else if ((cmd_accept) == 1'b1) begin + reg_cube_last <= is_cube_last; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_chn_size <= {3{1'b0}}; + end else if ((cmd_accept) == 1'b1) begin + req_chn_size <= cmd_fifo_rd_pos_c; + end +end +assign width_size = cmd_fifo_rd_pos_w; +// Beat CNT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_cnt <= {3{1'b0}}; + end else begin + if (cmd_accept) begin + beat_cnt <= 0; + end else if (dat_accept) begin + beat_cnt <= beat_cnt + 1; + end + end +end +reg mon_cmd_fifo_rd_pos_w_reg; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_fifo_rd_pos_w_reg <= {3{1'b0}}; + end else if ((cmd_fifo_rd_pvld & cmd_fifo_rd_prdy) == 1'b1) begin +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $Mnum = int( log( $dmaif/$atmm )/log(2)); +//: print " {mon_cmd_fifo_rd_pos_w_reg,cmd_fifo_rd_pos_w_reg} <= cmd_fifo_rd_pos_w[3:${Mnum}]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_cmd_fifo_rd_pos_w_reg,cmd_fifo_rd_pos_w_reg} <= cmd_fifo_rd_pos_w[3:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +end +assign is_last_beat = (beat_cnt==cmd_fifo_rd_pos_w_reg); +//============== +// DMA REQ: DATA +//============== +//------------------------------------ +// mode: 64 || mode: 32 +// clk : 0 0 1 1 || clk : 0 0 1 1 +// - - - - - - - -|| - - - - - - - +// fifo: 0 4 0 4 || fifo: 0 4 0 4 +// fifo: 1 5 1 5 || fifo: 1 5 1 5 +// fifo: 2 6 2 6 || fifo: 2 6 2 6 +// fifo: 3 7 3 7 || fifo: 3 7 3 7 +// - - - - - - - -|| - - - - - - - +// bus : L-H L-H || bus : L H-L H +//------------------------------------ +//============== +// DMA REQ: ADDR +//============== +// rename for reuse between rdma and wdma +assign reg2dp_base_addr = {reg2dp_dst_base_addr_high,reg2dp_dst_base_addr_low}; +assign reg2dp_line_stride = reg2dp_dst_line_stride; +assign reg2dp_surf_stride = reg2dp_dst_surface_stride; +//============== +// DMA Req : ADDR : Prepration +// DMA Req: go through the CUBE: W8->C->H +//============== +// Width: need be updated when move to next line +// Trigger Condition: (is_last_c & is_last_w) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_w <= {64{1'b0}}; + {mon_base_addr_w_c,base_addr_w} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_w <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c && is_last_w) begin + {mon_base_addr_w_c,base_addr_w} <= base_addr_w + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_w_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// base_Chn: need be updated when move to next w.group +// Trigger Condition: (is_last_c) +// 1, jump to next line when is_last_w +// 2, jump to next w.group when !is_last_w +assign width_size_use[3:0] = width_size + 1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_c <= {64{1'b0}}; + {mon_base_addr_c_c,base_addr_c} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_c <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_base_addr_c_c,base_addr_c} <= base_addr_w + reg2dp_line_stride; + end else begin +//{mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,5'd0}; +//: my $atmm_bw = int( log(8)/log(2)) ; +//: print qq( +//: {mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,${atmm_bw}'d0}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +{mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_10x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_c_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : ADDR : Generation +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_req_addr <= {64{1'b0}}; + {mon_dma_req_addr_c,dma_req_addr} <= {65{1'b0}}; + end else begin + if (op_load) begin + dma_req_addr <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_dma_req_addr_c,dma_req_addr} <= base_addr_w + reg2dp_line_stride; + end else begin +//: my $atmm_bw = int( log(8)/log(2)) ; +//: print qq( +//: {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,${atmm_bw}'d0}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +{mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,5'd0}; + end + end else begin + {mon_dma_req_addr_c,dma_req_addr} <= dma_req_addr + reg2dp_surf_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_11x (nvdla_core_clk, `ASSERT_RESET, mon_dma_req_addr_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////============== +//============== +// DMA REQ: Size +//============== +// packet: cmd +assign dma_wr_cmd_vld = cmd_vld; +assign dma_wr_cmd_addr = dma_req_addr; +assign dma_wr_cmd_size = {{9{1'b0}}, cmd_fifo_rd_pos_w}; +assign dma_wr_cmd_require_ack = is_cube_last; +// PKT_PACK_WIRE( dma_write_cmd , dma_wr_cmd_ , dma_wr_cmd_pd ) +assign dma_wr_cmd_pd[32 -1:0] = dma_wr_cmd_addr[32 -1:0]; +assign dma_wr_cmd_pd[32 +12:32] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[32 +13] = dma_wr_cmd_require_ack ; +// packet: data +assign dma_wr_dat_vld = dat_vld; +assign dma_wr_dat_data = dat_data; +//: my $k = 64; +//: my $jx = 8*8; +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "assign dma_wr_dat_mask = 1'b1; \n"; } +//: if($M == 2) { print "assign dma_wr_dat_mask = ((is_beat_num_odd == 1'b0) && is_last_beat) ? 2'b01 : 2'b11; \n"; } +//: if($M == 4) { print "assign dma_wr_dat_mask = ((is_beat_num_odd == 2'd0) && is_last_beat) ? 4'b0001 : (((is_beat_num_odd == 2'd1) && is_last_beat) ? 4'b0011 : (((is_beat_num_odd == 2'd2) && is_last_beat) ? 4'b0111 : 4'b1111)); \n"; } +//: if($M == 8) { +//: print qq( +//: assign dma_wr_dat_mask = ((is_beat_num_odd == 3'd0) && is_last_beat) ? 8'b00000001 : +//: ((is_beat_num_odd == 3'd1) && is_last_beat) ? 8'b00000011 : +//: ((is_beat_num_odd == 3'd2) && is_last_beat) ? 8'b00000111 : +//: ((is_beat_num_odd == 3'd3) && is_last_beat) ? 8'b00001111 : +//: ((is_beat_num_odd == 3'd4) && is_last_beat) ? 8'b00011111 : +//: ((is_beat_num_odd == 3'd5) && is_last_beat) ? 8'b00111111 : +//: ((is_beat_num_odd == 3'd6) && is_last_beat) ? 8'b01111111 : 8'b11111111; +//: ); +//: } +//: if($M == 16) { +//: print qq( +//: assign dma_wr_dat_mask = ((is_beat_num_odd == 4'h0) && is_last_beat) ? 16'b0000_0000_0000_0001 : +//: ((is_beat_num_odd == 4'h1) && is_last_beat) ? 16'b0000_0000_0000_0011 : +//: ((is_beat_num_odd == 4'h2) && is_last_beat) ? 16'b0000_0000_0000_0111 : +//: ((is_beat_num_odd == 4'h3) && is_last_beat) ? 16'b0000_0000_0000_1111 : +//: ((is_beat_num_odd == 4'h4) && is_last_beat) ? 16'b0000_0000_0001_1111 : +//: ((is_beat_num_odd == 4'h5) && is_last_beat) ? 16'b0000_0000_0011_1111 : +//: ((is_beat_num_odd == 4'h6) && is_last_beat) ? 16'b0000_0000_0111_1111 : +//: ((is_beat_num_odd == 4'h7) && is_last_beat) ? 16'b0000_0000_1111_1111 : +//: ((is_beat_num_odd == 4'h8) && is_last_beat) ? 16'b0000_0001_1111_1111 : +//: ((is_beat_num_odd == 4'h9) && is_last_beat) ? 16'b0000_0011_1111_1111 : +//: ((is_beat_num_odd == 4'ha) && is_last_beat) ? 16'b0000_0111_1111_1111 : +//: ((is_beat_num_odd == 4'hb) && is_last_beat) ? 16'b0000_1111_1111_1111 : +//: ((is_beat_num_odd == 4'hc) && is_last_beat) ? 16'b0001_1111_1111_1111 : +//: ((is_beat_num_odd == 4'hd) && is_last_beat) ? 16'b0011_1111_1111_1111 : +//: ((is_beat_num_odd == 4'he) && is_last_beat) ? 16'b0111_1111_1111_1111 : 8'b11111111_11111111; +//: ); +//: } +//: print "assign dma_wr_dat_pd[${k}-1:0] = dma_wr_dat_data[${k}-1:0]; \n"; +//: print "assign dma_wr_dat_pd[${k}+$M-1:${k}] = dma_wr_dat_mask[${M}-1:0]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dma_wr_dat_mask = 1'b1; +assign dma_wr_dat_pd[64-1:0] = dma_wr_dat_data[64-1:0]; +assign dma_wr_dat_pd[64+1-1:64] = dma_wr_dat_mask[1-1:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============================ +// pack cmd & dat +assign dma_wr_req_vld = dma_wr_cmd_vld | dma_wr_dat_vld; +//: my $k = 64; +//: my $jx = 8*8; +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(*) begin +// init to 0 + dma_wr_req_pd = 0; +// cmd or dat + if (cmd_en) begin + dma_wr_req_pd = {{(66 -32 -14){1'b0}},dma_wr_cmd_pd}; + end else begin + dma_wr_req_pd = {1'b0,dma_wr_dat_pd}; + end +//: my $k = 64; +//: my $jx = 8*8; +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: print" dma_wr_req_pd[${k}+${M}] = cmd_en ? 1'd0 : 1'd1 ; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + dma_wr_req_pd[64+1] = cmd_en ? 1'd0 : 1'd1 ; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +end +//============== +// writting stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = op_done; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_wr_req_vld & (~dma_wr_req_rdy)); + assign cdp_wr_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or cdp_wr_stall_count_dec + ) begin + stl_adv = cnt_inc ^ cdp_wr_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or cdp_wr_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !cdp_wr_stall_count_dec)? stl_cnt_inc : (!cnt_inc && cdp_wr_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + cdp_wr_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_write_stall <= cdp_wr_stall_count[31:0]; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_write_stall <= cdp_wr_stall_count[31:0]; + end + end +end +//============== +// DMA Interface +//============== +NV_NVDLA_DMAIF_wr NV_NVDLA_CDP_WDMA_wr( + .nvdla_core_clk (nvdla_core_clk_orig ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type ) + ,.mcif_wr_req_pd (cdp2mcif_wr_req_pd ) + ,.mcif_wr_req_valid (cdp2mcif_wr_req_valid ) + ,.mcif_wr_req_ready (cdp2mcif_wr_req_ready ) + ,.mcif_wr_rsp_complete (mcif2cdp_wr_rsp_complete) + ,.dmaif_wr_req_pd (dma_wr_req_pd ) + ,.dmaif_wr_req_pvld (dma_wr_req_vld ) + ,.dmaif_wr_req_prdy (dma_wr_req_rdy ) + ,.dmaif_wr_rsp_complete (dma_wr_rsp_complete ) +); +//////////////////////////////////////////////////////// +NV_NVDLA_CDP_WDMA_intr_fifo u_intr_fifo ( + .nvdla_core_clk (nvdla_core_clk_orig) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intr_fifo_wr_pvld (intr_fifo_wr_pvld) //|< w + ,.intr_fifo_wr_pd (intr_fifo_wr_pd) //|< w + ,.intr_fifo_rd_prdy (intr_fifo_rd_prdy) //|< w + ,.intr_fifo_rd_pvld (intr_fifo_rd_pvld) //|> w + ,.intr_fifo_rd_pd (intr_fifo_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign intr_fifo_wr_pd = reg2dp_interrupt_ptr; +assign intr_fifo_wr_pvld = op_done; +assign intr_fifo_rd_prdy = dma_wr_rsp_complete; +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2glb_done_intr_pd[0] <= 1'b0; + end else begin + cdp2glb_done_intr_pd[0] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==0); + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2glb_done_intr_pd[1] <= 1'b0; + end else begin + cdp2glb_done_intr_pd[1] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==1); + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when write complete, intr_ptr should be already in the head of intr_fifo read side") zzz_assert_never_25x (nvdla_core_clk_orig, `ASSERT_RESET, !intr_fifo_rd_pvld & dma_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////============== +//============== +//function polint +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_WDMA__dma_writing_stall__7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_req_vld & (~dma_wr_req_rdy); + endproperty +// Cover 7 : "dma_wr_req_vld & (~dma_wr_req_rdy)" + FUNCPOINT_CDP_WDMA__dma_writing_stall__7_COV : cover property (CDP_WDMA__dma_writing_stall__7_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_WDMA__dp2wdma_stall__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + cdp_dp2wdma_valid & (~cdp_dp2wdma_ready); + endproperty +// Cover 8 : "cdp_dp2wdma_valid & (~cdp_dp2wdma_ready)" + FUNCPOINT_CDP_WDMA__dp2wdma_stall__8_COV : cover property (CDP_WDMA__dp2wdma_stall__8_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_wdma +// -w 64, 8byte each fifo +// -d 3, depth=4 as we have rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_WDMA_dat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dat_fifo_wr -rd_pipebus dat_fifo_rd -rd_reg -ram_bypass -d 3 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_WDMA_dat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , dat_fifo_wr_prdy + , dat_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , dat_fifo_wr_pause +`endif + , dat_fifo_wr_pd + , dat_fifo_rd_prdy + , dat_fifo_rd_pvld + , dat_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dat_fifo_wr_prdy; +input dat_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input dat_fifo_wr_pause; +`endif +input [7:0] dat_fifo_wr_pd; +input dat_fifo_rd_prdy; +output dat_fifo_rd_pvld; +output [7:0] dat_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg dat_fifo_wr_busy_int; // copy for internal use +assign dat_fifo_wr_prdy = !dat_fifo_wr_busy_int; +assign wr_reserving = dat_fifo_wr_pvld && !dat_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [3:0] dat_fifo_wr_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? dat_fifo_wr_count : (dat_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (dat_fifo_wr_count + 1'd1) : dat_fifo_wr_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire dat_fifo_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check dat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || dat_fifo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire dat_fifo_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check dat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_busy_int <= 1'b0; + dat_fifo_wr_count <= 4'd0; + end else begin + dat_fifo_wr_busy_int <= dat_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dat_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dat_fifo_wr_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dat_fifo_wr_pvld +// +// RAM +// +reg [2:0] dat_fifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + dat_fifo_wr_adr <= dat_fifo_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [2:0] dat_fifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (dat_fifo_wr_count > 4'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] dat_fifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dat_fifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dat_fifo_wr_adr ) + , .ra ( (dat_fifo_wr_count == 0) ? 4'd8 : {1'b0,dat_fifo_rd_adr} ) + , .dout ( dat_fifo_rd_pd_p ) + ); +wire [2:0] rd_adr_next_popping = dat_fifo_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + dat_fifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dat_fifo_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire dat_fifo_rd_pvld_p; // data out of fifo is valid +reg dat_fifo_rd_pvld_int; // internal copy of dat_fifo_rd_pvld +assign dat_fifo_rd_pvld = dat_fifo_rd_pvld_int; +assign rd_popping = dat_fifo_rd_pvld_p && !(dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy); +reg [3:0] dat_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? dat_fifo_rd_count_p : + (dat_fifo_rd_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (dat_fifo_rd_count_p + 1'd1) : + dat_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign dat_fifo_rd_pvld_p = dat_fifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_count_p <= 4'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + dat_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dat_fifo_rd_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] dat_fifo_rd_pd; // output data register +wire rd_req_next = (dat_fifo_rd_pvld_p || (dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_pvld_int <= 1'b0; + end else begin + dat_fifo_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + dat_fifo_rd_pd <= dat_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + dat_fifo_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dat_fifo_wr_pvld && !dat_fifo_wr_busy_int) || (dat_fifo_wr_busy_int != dat_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (dat_fifo_rd_pvld_int && dat_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( dat_fifo_wr_pvld && !(!dat_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, dat_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_WDMA_dat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_WDMA_dat_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [2:0] wa; +input [3:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [2:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[2:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 8) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +reg [7:0] ram_ff4; +reg [7:0] ram_ff5; +reg [7:0] ram_ff6; +reg [7:0] ram_ff7; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 3'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 3'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 3'd7 ) begin + ram_ff7 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [2:0] Wa0; +input we0; +input [7:0] Di0; +input [2:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[7:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +wire [7:0] Q4 = mem[4]; +wire [7:0] Q5 = mem[5]; +wire [7:0] Q6 = mem[6]; +wire [7:0] Q7 = mem[7]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8] } +endmodule // vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +//vmw: Memory vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +//vmw: Address-size 3 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// swizzle: 0: start from fifo_0; start from fifo_4 +// width: 0~7, 32x1 in each 32x8 +// -d 3, depth=4 as we have rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_WDMA_cmd_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus cmd_fifo_wr -rd_pipebus cmd_fifo_rd -rd_reg -ram_bypass -d 3 -w 15 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_WDMA_cmd_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , cmd_fifo_wr_prdy + , cmd_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , cmd_fifo_wr_pause +`endif + , cmd_fifo_wr_pd + , cmd_fifo_rd_prdy + , cmd_fifo_rd_pvld + , cmd_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cmd_fifo_wr_prdy; +input cmd_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input cmd_fifo_wr_pause; +`endif +input [14:0] cmd_fifo_wr_pd; +input cmd_fifo_rd_prdy; +output cmd_fifo_rd_pvld; +output [14:0] cmd_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cmd_fifo_wr_busy_int; // copy for internal use +assign cmd_fifo_wr_prdy = !cmd_fifo_wr_busy_int; +assign wr_reserving = cmd_fifo_wr_pvld && !cmd_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [1:0] cmd_fifo_wr_count; // write-side count +wire [1:0] wr_count_next_wr_popping = wr_reserving ? cmd_fifo_wr_count : (cmd_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [1:0] wr_count_next_no_wr_popping = wr_reserving ? (cmd_fifo_wr_count + 1'd1) : cmd_fifo_wr_count; // spyglass disable W164a W484 +wire [1:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_3 = ( wr_count_next_no_wr_popping == 2'd3 ); +wire wr_count_next_is_3 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_3; +wire [1:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [1:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire cmd_fifo_wr_busy_next = wr_count_next_is_3 || // busy next cycle? + (wr_limit_reg != 2'd0 && // check cmd_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || cmd_fifo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire cmd_fifo_wr_busy_next = wr_count_next_is_3 || // busy next cycle? + (wr_limit_reg != 2'd0 && // check cmd_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_busy_int <= 1'b0; + cmd_fifo_wr_count <= 2'd0; + end else begin + cmd_fifo_wr_busy_int <= cmd_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + cmd_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + cmd_fifo_wr_count <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as cmd_fifo_wr_pvld +// +// RAM +// +reg [1:0] cmd_fifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + cmd_fifo_wr_adr <= (cmd_fifo_wr_adr == 2'd2) ? 2'd0 : (cmd_fifo_wr_adr + 1'd1); + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd_fifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (cmd_fifo_wr_count > 2'd0 || !rd_popping); // note: write occurs next cycle +wire [14:0] cmd_fifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( cmd_fifo_wr_pd ) + , .we ( ram_we ) + , .wa ( cmd_fifo_wr_adr ) + , .ra ( (cmd_fifo_wr_count == 0) ? 2'd3 : cmd_fifo_rd_adr ) + , .dout ( cmd_fifo_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = (cmd_fifo_rd_adr == 2'd2) ? 2'd0 : (cmd_fifo_rd_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd_fifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd_fifo_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd_fifo_rd_pvld_p; // data out of fifo is valid +reg cmd_fifo_rd_pvld_int; // internal copy of cmd_fifo_rd_pvld +assign cmd_fifo_rd_pvld = cmd_fifo_rd_pvld_int; +assign rd_popping = cmd_fifo_rd_pvld_p && !(cmd_fifo_rd_pvld_int && !cmd_fifo_rd_prdy); +reg [1:0] cmd_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [1:0] rd_count_p_next_rd_popping = rd_pushing ? cmd_fifo_rd_count_p : + (cmd_fifo_rd_count_p - 1'd1); +wire [1:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cmd_fifo_rd_count_p + 1'd1) : + cmd_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [1:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign cmd_fifo_rd_pvld_p = cmd_fifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_count_p <= 2'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd_fifo_rd_count_p <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [14:0] cmd_fifo_rd_pd; // output data register +wire rd_req_next = (cmd_fifo_rd_pvld_p || (cmd_fifo_rd_pvld_int && !cmd_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_pvld_int <= 1'b0; + end else begin + cmd_fifo_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + cmd_fifo_rd_pd <= cmd_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + cmd_fifo_rd_pd <= {15{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cmd_fifo_wr_pvld && !cmd_fifo_wr_busy_int) || (cmd_fifo_wr_busy_int != cmd_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (cmd_fifo_rd_pvld_int && cmd_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit : 2'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 2'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 2'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 2'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [1:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 2'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cmd_fifo_wr_pvld && !(!cmd_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {30'd0, (wr_limit_reg == 2'd0) ? 2'd3 : wr_limit_reg} ) + , .curr ( {30'd0, cmd_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_WDMA_cmd_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_WDMA_cmd_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [14:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [14:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [14:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [14:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout_p ) + ); +assign dout = (ra == 3) ? di : dout_p; +`else +reg [14:0] ram_ff0; +reg [14:0] ram_ff1; +reg [14:0] ram_ff2; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end +end +reg [14:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = di; +//VCS coverage off + default: dout = {15{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [14:0] Di0; +input [1:0] Ra0; +output [14:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 15'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [14:0] mem[2:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [14:0] Q0 = mem[0]; +wire [14:0] Q1 = mem[1]; +wire [14:0] Q2 = mem[2]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15] } +endmodule // vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +//vmw: Memory vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +//vmw: Address-size 2 +//vmw: Data-size 15 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[14:0] data0[14:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[14:0] data1[14:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +//interrupt fifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_WDMA_intr_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus intr_fifo_wr -rd_pipebus intr_fifo_rd -ram_bypass -d 0 -rd_reg -rd_busy_reg -no_wr_busy -w 1 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_WDMA_intr_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intr_fifo_wr_pvld + , intr_fifo_wr_pd + , intr_fifo_rd_prdy + , intr_fifo_rd_pvld + , intr_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +input intr_fifo_wr_pvld; +input intr_fifo_wr_pd; +input intr_fifo_rd_prdy; +output intr_fifo_rd_pvld; +output intr_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] intr_fifo_rd_pd_p = intr_fifo_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg intr_fifo_rd_prdy_d; // intr_fifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_prdy_d <= 1'b1; + end else begin + intr_fifo_rd_prdy_d <= intr_fifo_rd_prdy; + end +end +wire intr_fifo_rd_prdy_d_o; // combinatorial rd_busy +reg intr_fifo_rd_pvld_int; // internal copy of intr_fifo_rd_pvld +assign intr_fifo_rd_pvld = intr_fifo_rd_pvld_int; +wire intr_fifo_rd_pvld_p = intr_fifo_wr_pvld ; // no real fifo, take from write-side input +reg intr_fifo_rd_pvld_int_o; // internal copy of intr_fifo_rd_pvld_o +wire intr_fifo_rd_pvld_o = intr_fifo_rd_pvld_int_o; +wire rd_popping = intr_fifo_rd_pvld_p && !(intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg intr_fifo_rd_pd_o; // output data register +wire rd_req_next_o = (intr_fifo_rd_pvld_p || (intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int_o <= 1'b0; + end else begin + intr_fifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + intr_fifo_rd_pd_o <= intr_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + intr_fifo_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg intr_fifo_rd_pd; // output data register +reg intr_fifo_rd_pvld_int_d; // so we can bubble-collapse intr_fifo_rd_prdy_d +assign intr_fifo_rd_prdy_d_o = !((intr_fifo_rd_pvld_o && intr_fifo_rd_pvld_int_d && !intr_fifo_rd_prdy_d ) ); +wire rd_req_next = (!intr_fifo_rd_prdy_d_o ? intr_fifo_rd_pvld_o : intr_fifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int <= 1'b0; + intr_fifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) begin + intr_fifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy) ) begin + end else begin + intr_fifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + intr_fifo_rd_pvld_int_d <= intr_fifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) ) begin + case (!intr_fifo_rd_prdy_d_o) + 1'b0: intr_fifo_rd_pd <= intr_fifo_rd_pd_p; + 1'b1: intr_fifo_rd_pd <= intr_fifo_rd_pd_o; +//VCS coverage off + default: intr_fifo_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy)) ) begin + end else begin + intr_fifo_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (intr_fifo_wr_pvld || (intr_fifo_rd_pvld_int && intr_fifo_rd_prdy_d) || (intr_fifo_rd_pvld_int_o && intr_fifo_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_WDMA_intr_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDP_WDMA_intr_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v.vcp new file mode 100644 index 0000000..30fbe4f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v.vcp @@ -0,0 +1,2759 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_wdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_define.h +/////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_wdma ( + nvdla_core_clk + ,nvdla_core_clk_orig + ,nvdla_core_rstn + ,cdp2mcif_wr_req_ready + ,cdp_dp2wdma_pd + ,cdp_dp2wdma_valid + ,mcif2cdp_wr_rsp_complete + ,pwrbus_ram_pd + ,reg2dp_dma_en + ,reg2dp_dst_base_addr_high + ,reg2dp_dst_base_addr_low + ,reg2dp_dst_line_stride + ,reg2dp_dst_ram_type + ,reg2dp_dst_surface_stride + ,reg2dp_interrupt_ptr + ,reg2dp_op_en + ,cdp2glb_done_intr_pd + ,cdp2mcif_wr_req_pd + ,cdp2mcif_wr_req_valid + ,cdp_dp2wdma_ready + ,dp2reg_d0_perf_write_stall + ,dp2reg_d1_perf_write_stall + ,dp2reg_done + ); +//////////////////////////////////////////////////////////////////////////// +// +input nvdla_core_clk; +input nvdla_core_rstn; +output cdp2mcif_wr_req_valid; +input cdp2mcif_wr_req_ready; +output [66 -1:0] cdp2mcif_wr_req_pd; +input mcif2cdp_wr_rsp_complete; +input cdp_dp2wdma_valid; +output cdp_dp2wdma_ready; +input [1*8 +14:0] cdp_dp2wdma_pd; +output [1:0] cdp2glb_done_intr_pd; +input nvdla_core_clk_orig; +input [31:0] pwrbus_ram_pd; +input reg2dp_dma_en; +input [31:0] reg2dp_dst_base_addr_high; +input [31:0] reg2dp_dst_base_addr_low; +input [31:0] reg2dp_dst_line_stride; +input reg2dp_dst_ram_type; +input [31:0] reg2dp_dst_surface_stride; +input reg2dp_interrupt_ptr; +input reg2dp_op_en; +output [31:0] dp2reg_d0_perf_write_stall; +output [31:0] dp2reg_d1_perf_write_stall; +output dp2reg_done; +//////////////////////////////////////////////////////////////////////////// +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg [63:0] base_addr_c; +reg [63:0] base_addr_w; +reg [2:0] beat_cnt; +reg [1:0] cdp2glb_done_intr_pd; +reg [31:0] cdp_wr_stall_count; +reg cmd_en; +reg [2:0] cmd_fifo_rd_pos_w_reg; +reg cv_dma_wr_rsp_complete; +reg cv_pending; +reg dat_en; +reg [63:0] dma_req_addr; +wire dma_wr_rsp_complete; +reg [31:0] dp2reg_d0_perf_write_stall; +reg [31:0] dp2reg_d1_perf_write_stall; +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "reg is_beat_num_odd; \n"; +//: print "wire [0:0] dma_wr_dat_mask; \n";} +//: if($M == 2) { print "reg is_beat_num_odd; \n"; +//: print "wire [1:0] dma_wr_dat_mask; \n";} +//: if($M == 4) { print "reg [1:0] is_beat_num_odd; \n"; +//: print "wire [3:0] dma_wr_dat_mask; \n";} +//: if($M == 8) { print "reg [2:0] is_beat_num_odd; \n"; +//: print "wire [7:0] dma_wr_dat_mask; \n";} +//: if($M == 16) { print "reg [3:0] is_beat_num_odd; \n"; +//: print "wire [15:0] dma_wr_dat_mask; \n";} +//reg is_beat_num_odd; +reg layer_flag; +reg mc_dma_wr_rsp_complete; +reg mc_pending; +reg mon_base_addr_c_c; +reg mon_base_addr_w_c; +reg mon_dma_req_addr_c; +reg mon_nan_in_count; +reg op_prcess; +reg reg_cube_last; +reg [2:0] req_chn_size; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire cdp_wr_stall_count_dec; +wire cmd_accept; +wire cmd_fifo_rd_b_sync; +wire cmd_fifo_rd_b_sync_NC; +wire cmd_fifo_rd_last_c; +wire cmd_fifo_rd_last_h; +wire cmd_fifo_rd_last_w; +wire [14:0] cmd_fifo_rd_pd; +wire [2:0] cmd_fifo_rd_pos_c; +wire [3:0] cmd_fifo_rd_pos_w; +wire cmd_fifo_rd_prdy; +wire cmd_fifo_rd_pvld; +wire [3:0] cmd_fifo_rd_width; +wire [14:0] cmd_fifo_wr_pd; +wire cmd_fifo_wr_prdy; +wire cmd_fifo_wr_pvld; +wire cmd_rdy; +wire cmd_vld; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +wire dat_accept; +wire [64 -1:0] dat_data; +wire dat_fifo_wr_rdy; +wire dat_rdy; +wire dat_vld; +wire [63:0] dma_wr_cmd_addr; +wire [32 +13:0] dma_wr_cmd_pd; +wire dma_wr_cmd_require_ack; +wire [12:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [64 -1:0] dma_wr_dat_data; +wire [66 -2:0] dma_wr_dat_pd; +reg [66 -1:0] dma_wr_req_pd; +wire dma_wr_dat_vld; +wire dma_wr_req_rdy; +wire dma_wr_req_type; +wire dma_wr_req_vld; +wire dp2wdma_b_sync; +wire [14:0] dp2wdma_cmd_pd; +wire [1*8 -1:0] dp2wdma_data; +wire dp2wdma_last_c; +wire dp2wdma_last_h; +wire dp2wdma_last_w; +wire [2:0] dp2wdma_pos_c; +wire [3:0] dp2wdma_pos_w; +wire dp2wdma_pos_w_bit0; +wire dp2wdma_rdy; +wire [3:0] dp2wdma_width; +wire intr_fifo_rd_pd; +wire intr_fifo_rd_prdy; +wire intr_fifo_rd_pvld; +wire intr_fifo_wr_pd; +wire intr_fifo_wr_pvld; +wire is_cube_last; +wire is_last_beat; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire op_done; +wire op_load; +wire [63:0] reg2dp_base_addr; +wire [31:0] reg2dp_line_stride; +wire [31:0] reg2dp_surf_stride; +wire releasing; +wire require_ack; +wire [3:0] width_size; +wire [3:0] width_size_use; +wire wr_req_rdyi; +//////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +assign op_load = reg2dp_op_en & !op_prcess; +assign op_done = reg_cube_last & is_last_beat & dat_accept; +assign dp2reg_done = op_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_prcess <= 1'b0; + end else begin + if (op_load) begin + op_prcess <= 1'b1; + end else if (op_done) begin + op_prcess <= 1'b0; + end + end +end +//============== +// Data INPUT pipe and Unpack +//============== +//: my $k=1*8 +15; +//: &eperl::pipe(" -wid $k -is -do dp2wdma_pd -vo dp2wdma_vld -ri dp2wdma_rdy -di cdp_dp2wdma_pd -vi cdp_dp2wdma_valid -ro cdp_dp2wdma_ready "); +assign dp2wdma_data[1*8 -1:0] = dp2wdma_pd[1*8 -1:0]; +assign dp2wdma_pos_w[3:0] = dp2wdma_pd[1*8 +3:1*8]; +assign dp2wdma_width[3:0] = dp2wdma_pd[1*8 +7:1*8 +4]; +assign dp2wdma_pos_c[2:0] = dp2wdma_pd[1*8 +10:1*8 +8]; +assign dp2wdma_b_sync = dp2wdma_pd[1*8 +11]; +assign dp2wdma_last_w = dp2wdma_pd[1*8 +12]; +assign dp2wdma_last_h = dp2wdma_pd[1*8 +13]; +assign dp2wdma_last_c = dp2wdma_pd[1*8 +14]; +assign dp2wdma_cmd_pd[3:0] = dp2wdma_pos_w[3:0]; +assign dp2wdma_cmd_pd[7:4] = dp2wdma_width[3:0]; +assign dp2wdma_cmd_pd[10:8] = dp2wdma_pos_c[2:0]; +assign dp2wdma_cmd_pd[11] = dp2wdma_b_sync ; +assign dp2wdma_cmd_pd[12] = dp2wdma_last_w ; +assign dp2wdma_cmd_pd[13] = dp2wdma_last_h ; +assign dp2wdma_cmd_pd[14] = dp2wdma_last_c ; +/////////////////////////////////////////////////////// +// when b_sync, both cmd.fifo and dat.fifo need be ready, when !b_sync, only dat.fifo need be ready +assign dp2wdma_rdy = dp2wdma_vld & (dp2wdma_b_sync ? (dat_fifo_wr_rdy & cmd_fifo_wr_prdy) : dat_fifo_wr_rdy); +//============== +// Input FIFO : DATA and its swizzle +//============== +//: my $tp = 1*8; +//: my $atmm = 8*8; +//: my $k = 64/$tp; +//: my $M = 64/$atmm; +//: my $F = $atmm/$tp; +//: if($M == 1) { +//: print qq( assign dp2wdma_pos_w_bit0 = 1'b0; ); +//: } elsif($M == 2) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[0]; ); +//: } elsif($M == 4) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[1:0]; ); +//: } elsif($M == 8) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[2:0]; ); +//: } elsif($M == 16) { +//: print qq( assign dp2wdma_pos_w_bit0 = dp2wdma_pos_w[3:0]; ); +//: } +//: foreach my $i (0..$M-1) { +//: print "wire dat${i}_rdy; \n"; +//: } +//: my @dat_wr_rdys; +//: foreach my $m (0..$k-1) { +//: my $chn = $m % $F; +//: my $pos = int($m / $F); +//: print qq( +//: wire dat${pos}_fifo${chn}_wr_pvld; +//: wire dat${pos}_fifo${chn}_wr_prdy; +//: wire [$tp-1:0] dat${pos}_fifo${chn}_wr_pd; +//: wire [$tp-1:0] dat${pos}_fifo${chn}_rd_pd; +//: wire dat${pos}_fifo${chn}_rd_prdy; +//: wire dat${pos}_fifo${chn}_rd_pvld; +//: assign dat${pos}_fifo${chn}_wr_pvld = ((!dp2wdma_b_sync) || (dp2wdma_b_sync & cmd_fifo_wr_prdy)) & dp2wdma_vld & (dp2wdma_pos_c==$chn) & (dp2wdma_pos_w_bit0==$pos); +//: assign dat${pos}_fifo${chn}_wr_pd = dp2wdma_data; +//: NV_NVDLA_CDP_WDMA_dat_fifo u_dat${pos}_fifo${chn} ( +//: .nvdla_core_clk (nvdla_core_clk ) +//: ,.nvdla_core_rstn (nvdla_core_rstn ) +//: ,.dat_fifo_wr_prdy (dat${pos}_fifo${chn}_wr_prdy ) +//: ,.dat_fifo_wr_pvld (dat${pos}_fifo${chn}_wr_pvld ) +//: ,.dat_fifo_wr_pd (dat${pos}_fifo${chn}_wr_pd ) +//: ,.dat_fifo_rd_prdy (dat${pos}_fifo${chn}_rd_prdy ) +//: ,.dat_fifo_rd_pvld (dat${pos}_fifo${chn}_rd_pvld ) +//: ,.dat_fifo_rd_pd (dat${pos}_fifo${chn}_rd_pd ) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0] ) +//: ); +//: +//: assign dat${pos}_fifo${chn}_rd_prdy = dat${pos}_rdy & (${chn} <= req_chn_size); +//: ); +//: push @dat_wr_rdys, "(dat${pos}_fifo${chn}_wr_prdy & (dp2wdma_pos_c==$chn) & (dp2wdma_pos_w_bit0==$pos))"; +//: } +//: my $dat_wr_rdys_str = join(" \n| ",@dat_wr_rdys); +//: print "assign dat_fifo_wr_rdy = $dat_wr_rdys_str; "; +//: my $kx = 1*8; ##throughput BW in int8 +//: my $jx = 8*8; ##atomic_m BW in int8 +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$M-1) { +//: print "wire dat${m}_fifo_rd_pvld; \n"; +//: my @dat_vlds_s; +//: foreach my $f (0..$F-1) { +//: push @dat_vlds_s, "dat${m}_fifo${f}_rd_pvld"; +//: } +//: my $dat_vlds_str = join(" \n& ",@dat_vlds_s); +//: print "assign dat${m}_fifo_rd_pvld = $dat_vlds_str; \n"; +//: } +// +// //: my $kx = NVDLA_CDP_THROUGHPUT*NVDLA_CDP_BWPE; ##throughput BW in int8 +// //: my $jx = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_CDP_BWPE; ##atomic_m BW in int8 +// //: my $k = NVDLA_CDP_DMAIF_BW/$kx; ##total fifo num +// //: my $M = NVDLA_CDP_DMAIF_BW/$jx; ##atomic_m number per dma transaction +// //: my $F = $k/$M; ##how many fifo contribute to one atomic_m +// //: foreach my $m (0..$M-1) { +// //: print "&eperl::assert -type never -desc 'CDP-WDMA: dat$m rdys should be all 1 or all 0' -expr ( "; +// // if($F > 1) { +// //: foreach my $f (0..$F-2) { +// //: my $k = $F - $f -1; +// //: print "dat${m}_fifo${k}_rd_prdy & "; +// //: } +// //: } +// //: print "dat${m}_fifo0_rd_prdy)!=("; +// // if($F > 1) { +// //: foreach my $f (0..$F-2) { +// //: my $k = $F - $f -1; +// //: print "dat${m}_fifo${k}_rd_prdy | "; +// //: } +// //: } +// //: print "dat${m}_fifo0_rd_prdy) -clk nvdla_core_clk -rst nvdla_core_rstn; \n"; +// //: } +//DorisLei +//&eperl::assert -type never -desc 'CDP-WDMA: dat0 rdys should be all 1 or all 0' -expr (dat0_fifo0_rd_prdy & dat0_fifo1_rd_prdy & dat0_fifo2_rd_prdy & dat0_fifo3_rd_prdy)!=(dat0_fifo0_rd_prdy | dat0_fifo1_rd_prdy | dat0_fifo2_rd_prdy | dat0_fifo3_rd_prdy) -clk nvdla_core_clk -rst nvdla_core_rstn; +//&eperl::assert -type never -desc 'CDP-WDMA: dat1 rdys should be all 1 or all 0' -expr (dat1_fifo0_rd_prdy & dat1_fifo1_rd_prdy & dat1_fifo2_rd_prdy & dat1_fifo3_rd_prdy)!=(dat1_fifo0_rd_prdy | dat1_fifo1_rd_prdy | dat1_fifo2_rd_prdy | dat1_fifo3_rd_prdy) -clk nvdla_core_clk -rst nvdla_core_rstn; +//: my $kx = 1*8; ##throughput BW in int8 +//: my $jx = 8*8; ##atomic_m BW in int8 +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$M-1) { +//: print "wire [$jx-1:0] dat${m}_data; \n"; +//: print "assign dat${m}_data= { \n"; +//: if($F > 1) { +//: foreach my $k (0..$F-2) { +//: my $j = $F - $k -1; +//: print "dat${m}_fifo${j}_rd_pd,"; +//: } +//: } +//: print "dat${m}_fifo0_rd_pd}; \n"; +//: } +assign dat_data = { +//: my $kx = 1*8; ##throughput BW in int8 +//: my $jx = 8*8; ##atomic_m BW in int8 +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: if($M > 1) { +//: foreach my $k (0..$M-2) { +//: my $j = $M - $k -1; +//: print "dat${j}_data,"; +//: } +//: } +dat0_data}; +//============== +// Input FIFO: CMD +//============== +// cmd-fifo control +// if b_sync, need push into both dat_fifo and cmd_fifo +// FIFO:Write side +//assign cmd_fifo_wr_pvld = dp2wdma_vld & (dp2wdma_b_sync & (dp2wdma_pos_c==3'd3)) & dat_fifo_wr_rdy; +assign cmd_fifo_wr_pvld = dp2wdma_vld & (dp2wdma_b_sync & (dp2wdma_pos_c==(8/1 -1))) & dat_fifo_wr_rdy; +assign cmd_fifo_wr_pd = dp2wdma_cmd_pd; +// CMD FIFO:Instance +NV_NVDLA_CDP_WDMA_cmd_fifo u_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_fifo_wr_prdy (cmd_fifo_wr_prdy) //|> w + ,.cmd_fifo_wr_pvld (cmd_fifo_wr_pvld) //|< w + ,.cmd_fifo_wr_pd (cmd_fifo_wr_pd[14:0]) //|< w + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) //|< w + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) //|> w + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[14:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +// CMD FIFO:Read side +assign cmd_fifo_rd_prdy = cmd_en & cmd_rdy; +// Unpack cmd & data together +assign cmd_fifo_rd_pos_w[3:0] = cmd_fifo_rd_pd[3:0]; +assign cmd_fifo_rd_width[3:0] = cmd_fifo_rd_pd[7:4]; +assign cmd_fifo_rd_pos_c[2:0] = cmd_fifo_rd_pd[10:8]; +assign cmd_fifo_rd_b_sync = cmd_fifo_rd_pd[11]; +assign cmd_fifo_rd_last_w = cmd_fifo_rd_pd[12]; +assign cmd_fifo_rd_last_h = cmd_fifo_rd_pd[13]; +assign cmd_fifo_rd_last_c = cmd_fifo_rd_pd[14]; +assign cmd_fifo_rd_b_sync_NC = cmd_fifo_rd_b_sync; +assign is_last_w = cmd_fifo_rd_last_w; +assign is_last_h = cmd_fifo_rd_last_h; +assign is_last_c = cmd_fifo_rd_last_c; +assign is_cube_last = is_last_w & is_last_h & is_last_c; +//============== +// BLOCK Operation +//============== +assign cmd_vld = cmd_en & cmd_fifo_rd_pvld; +assign cmd_rdy = dma_wr_req_rdy; +assign cmd_accept = cmd_vld & cmd_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "is_beat_num_odd <= 1'b0; \n";} +//: if($M == 2) { print "is_beat_num_odd <= 1'b0; \n";} +//: if($M == 4) { print "is_beat_num_odd <= 2'd0; \n";} +//: if($M == 8) { print "is_beat_num_odd <= 3'd0; \n";} +//: if($M == 16) { print "is_beat_num_odd <= 4'd0; \n";} + end else if ((cmd_accept) == 1'b1) begin +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "is_beat_num_odd <= 1'b0; \n";} +//: if($M == 2) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[0]); \n";} +//: if($M == 4) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[1:0]); \n";} +//: if($M == 8) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[2:0]); \n";} +//: if($M == 16) { print "is_beat_num_odd <= (cmd_fifo_rd_pos_w[3:0]); \n";} +// is_beat_num_odd <= (cmd_fifo_rd_pos_w[0]==0); + end +end +//: my $kx = 1*8; +//: my $jx = 8*8; +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$M-1) { +//: print "wire dat${m}_vld; \n"; +//: print "//wire dat${m}_rdy; \n"; +//: print "assign dat${m}_vld = dat_en & dat${m}_fifo_rd_pvld & !(is_last_beat & (is_beat_num_odd < $m)); \n"; +//: print "assign dat${m}_rdy = dat_en & dat_rdy & !(is_last_beat & (is_beat_num_odd < $m)); \n"; +//: } +assign dat_vld = dat_en & (//dat0_vld | dat1_vld; +//: my $jx = 8*8; +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: if($M > 1) { +//: foreach my $m (0..$M-2) { +//: my $k = $M - $m -1; +//: print "dat${k}_vld | "; +//: } +//: } +dat0_vld); +assign dat_rdy = dat_en & dma_wr_req_rdy; +assign dat_accept = dat_vld & dat_rdy; +// Req.cmd +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (is_last_beat & dat_accept) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else if (cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_cube_last <= 1'b0; + end else if ((cmd_accept) == 1'b1) begin + reg_cube_last <= is_cube_last; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_chn_size <= {3{1'b0}}; + end else if ((cmd_accept) == 1'b1) begin + req_chn_size <= cmd_fifo_rd_pos_c; + end +end +assign width_size = cmd_fifo_rd_pos_w; +// Beat CNT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_cnt <= {3{1'b0}}; + end else begin + if (cmd_accept) begin + beat_cnt <= 0; + end else if (dat_accept) begin + beat_cnt <= beat_cnt + 1; + end + end +end +reg mon_cmd_fifo_rd_pos_w_reg; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_fifo_rd_pos_w_reg <= {3{1'b0}}; + end else if ((cmd_fifo_rd_pvld & cmd_fifo_rd_prdy) == 1'b1) begin +//: my $dmaif = 64/8; +//: my $atmm = 8; +//: my $Mnum = int( log( $dmaif/$atmm )/log(2)); +//: print " {mon_cmd_fifo_rd_pos_w_reg,cmd_fifo_rd_pos_w_reg} <= cmd_fifo_rd_pos_w[3:${Mnum}]; \n"; + end +end +assign is_last_beat = (beat_cnt==cmd_fifo_rd_pos_w_reg); +//============== +// DMA REQ: DATA +//============== +//------------------------------------ +// mode: 64 || mode: 32 +// clk : 0 0 1 1 || clk : 0 0 1 1 +// - - - - - - - -|| - - - - - - - +// fifo: 0 4 0 4 || fifo: 0 4 0 4 +// fifo: 1 5 1 5 || fifo: 1 5 1 5 +// fifo: 2 6 2 6 || fifo: 2 6 2 6 +// fifo: 3 7 3 7 || fifo: 3 7 3 7 +// - - - - - - - -|| - - - - - - - +// bus : L-H L-H || bus : L H-L H +//------------------------------------ +//============== +// DMA REQ: ADDR +//============== +// rename for reuse between rdma and wdma +assign reg2dp_base_addr = {reg2dp_dst_base_addr_high,reg2dp_dst_base_addr_low}; +assign reg2dp_line_stride = reg2dp_dst_line_stride; +assign reg2dp_surf_stride = reg2dp_dst_surface_stride; +//============== +// DMA Req : ADDR : Prepration +// DMA Req: go through the CUBE: W8->C->H +//============== +// Width: need be updated when move to next line +// Trigger Condition: (is_last_c & is_last_w) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_w <= {64{1'b0}}; + {mon_base_addr_w_c,base_addr_w} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_w <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c && is_last_w) begin + {mon_base_addr_w_c,base_addr_w} <= base_addr_w + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_w_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// base_Chn: need be updated when move to next w.group +// Trigger Condition: (is_last_c) +// 1, jump to next line when is_last_w +// 2, jump to next w.group when !is_last_w +assign width_size_use[3:0] = width_size + 1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_c <= {64{1'b0}}; + {mon_base_addr_c_c,base_addr_c} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_c <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_base_addr_c_c,base_addr_c} <= base_addr_w + reg2dp_line_stride; + end else begin +//{mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,5'd0}; +//: my $atmm_bw = int( log(8)/log(2)) ; +//: print qq( +//: {mon_base_addr_c_c,base_addr_c} <= base_addr_c + {width_size_use,${atmm_bw}'d0}; +//: ); + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_10x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_c_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : ADDR : Generation +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_req_addr <= {64{1'b0}}; + {mon_dma_req_addr_c,dma_req_addr} <= {65{1'b0}}; + end else begin + if (op_load) begin + dma_req_addr <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_last_c) begin + if (is_last_w) begin + {mon_dma_req_addr_c,dma_req_addr} <= base_addr_w + reg2dp_line_stride; + end else begin +//: my $atmm_bw = int( log(8)/log(2)) ; +//: print qq( +//: {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,${atmm_bw}'d0}; +//: ); +// {mon_dma_req_addr_c,dma_req_addr} <= base_addr_c + {width_size_use,5'd0}; + end + end else begin + {mon_dma_req_addr_c,dma_req_addr} <= dma_req_addr + reg2dp_surf_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP_RDMA: no overflow is allowed") zzz_assert_never_11x (nvdla_core_clk, `ASSERT_RESET, mon_dma_req_addr_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////============== +//============== +// DMA REQ: Size +//============== +// packet: cmd +assign dma_wr_cmd_vld = cmd_vld; +assign dma_wr_cmd_addr = dma_req_addr; +assign dma_wr_cmd_size = {{9{1'b0}}, cmd_fifo_rd_pos_w}; +assign dma_wr_cmd_require_ack = is_cube_last; +// PKT_PACK_WIRE( dma_write_cmd , dma_wr_cmd_ , dma_wr_cmd_pd ) +assign dma_wr_cmd_pd[32 -1:0] = dma_wr_cmd_addr[32 -1:0]; +assign dma_wr_cmd_pd[32 +12:32] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[32 +13] = dma_wr_cmd_require_ack ; +// packet: data +assign dma_wr_dat_vld = dat_vld; +assign dma_wr_dat_data = dat_data; +//: my $k = 64; +//: my $jx = 8*8; +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: if($M == 1) { print "assign dma_wr_dat_mask = 1'b1; \n"; } +//: if($M == 2) { print "assign dma_wr_dat_mask = ((is_beat_num_odd == 1'b0) && is_last_beat) ? 2'b01 : 2'b11; \n"; } +//: if($M == 4) { print "assign dma_wr_dat_mask = ((is_beat_num_odd == 2'd0) && is_last_beat) ? 4'b0001 : (((is_beat_num_odd == 2'd1) && is_last_beat) ? 4'b0011 : (((is_beat_num_odd == 2'd2) && is_last_beat) ? 4'b0111 : 4'b1111)); \n"; } +//: if($M == 8) { +//: print qq( +//: assign dma_wr_dat_mask = ((is_beat_num_odd == 3'd0) && is_last_beat) ? 8'b00000001 : +//: ((is_beat_num_odd == 3'd1) && is_last_beat) ? 8'b00000011 : +//: ((is_beat_num_odd == 3'd2) && is_last_beat) ? 8'b00000111 : +//: ((is_beat_num_odd == 3'd3) && is_last_beat) ? 8'b00001111 : +//: ((is_beat_num_odd == 3'd4) && is_last_beat) ? 8'b00011111 : +//: ((is_beat_num_odd == 3'd5) && is_last_beat) ? 8'b00111111 : +//: ((is_beat_num_odd == 3'd6) && is_last_beat) ? 8'b01111111 : 8'b11111111; +//: ); +//: } +//: if($M == 16) { +//: print qq( +//: assign dma_wr_dat_mask = ((is_beat_num_odd == 4'h0) && is_last_beat) ? 16'b0000_0000_0000_0001 : +//: ((is_beat_num_odd == 4'h1) && is_last_beat) ? 16'b0000_0000_0000_0011 : +//: ((is_beat_num_odd == 4'h2) && is_last_beat) ? 16'b0000_0000_0000_0111 : +//: ((is_beat_num_odd == 4'h3) && is_last_beat) ? 16'b0000_0000_0000_1111 : +//: ((is_beat_num_odd == 4'h4) && is_last_beat) ? 16'b0000_0000_0001_1111 : +//: ((is_beat_num_odd == 4'h5) && is_last_beat) ? 16'b0000_0000_0011_1111 : +//: ((is_beat_num_odd == 4'h6) && is_last_beat) ? 16'b0000_0000_0111_1111 : +//: ((is_beat_num_odd == 4'h7) && is_last_beat) ? 16'b0000_0000_1111_1111 : +//: ((is_beat_num_odd == 4'h8) && is_last_beat) ? 16'b0000_0001_1111_1111 : +//: ((is_beat_num_odd == 4'h9) && is_last_beat) ? 16'b0000_0011_1111_1111 : +//: ((is_beat_num_odd == 4'ha) && is_last_beat) ? 16'b0000_0111_1111_1111 : +//: ((is_beat_num_odd == 4'hb) && is_last_beat) ? 16'b0000_1111_1111_1111 : +//: ((is_beat_num_odd == 4'hc) && is_last_beat) ? 16'b0001_1111_1111_1111 : +//: ((is_beat_num_odd == 4'hd) && is_last_beat) ? 16'b0011_1111_1111_1111 : +//: ((is_beat_num_odd == 4'he) && is_last_beat) ? 16'b0111_1111_1111_1111 : 8'b11111111_11111111; +//: ); +//: } +//: print "assign dma_wr_dat_pd[${k}-1:0] = dma_wr_dat_data[${k}-1:0]; \n"; +//: print "assign dma_wr_dat_pd[${k}+$M-1:${k}] = dma_wr_dat_mask[${M}-1:0]; \n"; +//============================ +// pack cmd & dat +assign dma_wr_req_vld = dma_wr_cmd_vld | dma_wr_dat_vld; +//: my $k = 64; +//: my $jx = 8*8; +//: my $M = $k/$jx; ##atomic_m number per dma transaction +always @(*) begin +// init to 0 + dma_wr_req_pd = 0; +// cmd or dat + if (cmd_en) begin + dma_wr_req_pd = {{(66 -32 -14){1'b0}},dma_wr_cmd_pd}; + end else begin + dma_wr_req_pd = {1'b0,dma_wr_dat_pd}; + end +//: my $k = 64; +//: my $jx = 8*8; +//: my $M = $k/$jx; ##atomic_m number per dma transaction +//: print" dma_wr_req_pd[${k}+${M}] = cmd_en ? 1'd0 : 1'd1 ; \n"; +end +//============== +// writting stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = op_done; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_wr_req_vld & (~dma_wr_req_rdy)); + assign cdp_wr_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or cdp_wr_stall_count_dec + ) begin + stl_adv = cnt_inc ^ cdp_wr_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or cdp_wr_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !cdp_wr_stall_count_dec)? stl_cnt_inc : (!cnt_inc && cdp_wr_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + cdp_wr_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_write_stall <= cdp_wr_stall_count[31:0]; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_write_stall <= cdp_wr_stall_count[31:0]; + end + end +end +//============== +// DMA Interface +//============== +NV_NVDLA_DMAIF_wr NV_NVDLA_CDP_WDMA_wr( + .nvdla_core_clk (nvdla_core_clk_orig ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type ) + ,.mcif_wr_req_pd (cdp2mcif_wr_req_pd ) + ,.mcif_wr_req_valid (cdp2mcif_wr_req_valid ) + ,.mcif_wr_req_ready (cdp2mcif_wr_req_ready ) + ,.mcif_wr_rsp_complete (mcif2cdp_wr_rsp_complete) + ,.dmaif_wr_req_pd (dma_wr_req_pd ) + ,.dmaif_wr_req_pvld (dma_wr_req_vld ) + ,.dmaif_wr_req_prdy (dma_wr_req_rdy ) + ,.dmaif_wr_rsp_complete (dma_wr_rsp_complete ) +); +//////////////////////////////////////////////////////// +NV_NVDLA_CDP_WDMA_intr_fifo u_intr_fifo ( + .nvdla_core_clk (nvdla_core_clk_orig) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intr_fifo_wr_pvld (intr_fifo_wr_pvld) //|< w + ,.intr_fifo_wr_pd (intr_fifo_wr_pd) //|< w + ,.intr_fifo_rd_prdy (intr_fifo_rd_prdy) //|< w + ,.intr_fifo_rd_pvld (intr_fifo_rd_pvld) //|> w + ,.intr_fifo_rd_pd (intr_fifo_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign intr_fifo_wr_pd = reg2dp_interrupt_ptr; +assign intr_fifo_wr_pvld = op_done; +assign intr_fifo_rd_prdy = dma_wr_rsp_complete; +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2glb_done_intr_pd[0] <= 1'b0; + end else begin + cdp2glb_done_intr_pd[0] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==0); + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp2glb_done_intr_pd[1] <= 1'b0; + end else begin + cdp2glb_done_intr_pd[1] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==1); + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when write complete, intr_ptr should be already in the head of intr_fifo read side") zzz_assert_never_25x (nvdla_core_clk_orig, `ASSERT_RESET, !intr_fifo_rd_pvld & dma_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////============== +//============== +//function polint +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_WDMA__dma_writing_stall__7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_req_vld & (~dma_wr_req_rdy); + endproperty +// Cover 7 : "dma_wr_req_vld & (~dma_wr_req_rdy)" + FUNCPOINT_CDP_WDMA__dma_writing_stall__7_COV : cover property (CDP_WDMA__dma_writing_stall__7_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_WDMA__dp2wdma_stall__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + cdp_dp2wdma_valid & (~cdp_dp2wdma_ready); + endproperty +// Cover 8 : "cdp_dp2wdma_valid & (~cdp_dp2wdma_ready)" + FUNCPOINT_CDP_WDMA__dp2wdma_stall__8_COV : cover property (CDP_WDMA__dp2wdma_stall__8_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_CDP_wdma +// -w 64, 8byte each fifo +// -d 3, depth=4 as we have rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_WDMA_dat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dat_fifo_wr -rd_pipebus dat_fifo_rd -rd_reg -ram_bypass -d 3 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_WDMA_dat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , dat_fifo_wr_prdy + , dat_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , dat_fifo_wr_pause +`endif + , dat_fifo_wr_pd + , dat_fifo_rd_prdy + , dat_fifo_rd_pvld + , dat_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dat_fifo_wr_prdy; +input dat_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input dat_fifo_wr_pause; +`endif +input [7:0] dat_fifo_wr_pd; +input dat_fifo_rd_prdy; +output dat_fifo_rd_pvld; +output [7:0] dat_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg dat_fifo_wr_busy_int; // copy for internal use +assign dat_fifo_wr_prdy = !dat_fifo_wr_busy_int; +assign wr_reserving = dat_fifo_wr_pvld && !dat_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [3:0] dat_fifo_wr_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? dat_fifo_wr_count : (dat_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (dat_fifo_wr_count + 1'd1) : dat_fifo_wr_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire dat_fifo_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check dat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || dat_fifo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire dat_fifo_wr_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check dat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_busy_int <= 1'b0; + dat_fifo_wr_count <= 4'd0; + end else begin + dat_fifo_wr_busy_int <= dat_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dat_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dat_fifo_wr_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dat_fifo_wr_pvld +// +// RAM +// +reg [2:0] dat_fifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + dat_fifo_wr_adr <= dat_fifo_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [2:0] dat_fifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (dat_fifo_wr_count > 4'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] dat_fifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dat_fifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dat_fifo_wr_adr ) + , .ra ( (dat_fifo_wr_count == 0) ? 4'd8 : {1'b0,dat_fifo_rd_adr} ) + , .dout ( dat_fifo_rd_pd_p ) + ); +wire [2:0] rd_adr_next_popping = dat_fifo_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + dat_fifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dat_fifo_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire dat_fifo_rd_pvld_p; // data out of fifo is valid +reg dat_fifo_rd_pvld_int; // internal copy of dat_fifo_rd_pvld +assign dat_fifo_rd_pvld = dat_fifo_rd_pvld_int; +assign rd_popping = dat_fifo_rd_pvld_p && !(dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy); +reg [3:0] dat_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? dat_fifo_rd_count_p : + (dat_fifo_rd_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (dat_fifo_rd_count_p + 1'd1) : + dat_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign dat_fifo_rd_pvld_p = dat_fifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_count_p <= 4'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + dat_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dat_fifo_rd_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] dat_fifo_rd_pd; // output data register +wire rd_req_next = (dat_fifo_rd_pvld_p || (dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_pvld_int <= 1'b0; + end else begin + dat_fifo_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + dat_fifo_rd_pd <= dat_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + dat_fifo_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dat_fifo_wr_pvld && !dat_fifo_wr_busy_int) || (dat_fifo_wr_busy_int != dat_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (dat_fifo_rd_pvld_int && dat_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_dat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( dat_fifo_wr_pvld && !(!dat_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, dat_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_WDMA_dat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_WDMA_dat_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [2:0] wa; +input [3:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [2:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[2:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 8) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +reg [7:0] ram_ff4; +reg [7:0] ram_ff5; +reg [7:0] ram_ff6; +reg [7:0] ram_ff7; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 3'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 3'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 3'd7 ) begin + ram_ff7 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [2:0] Wa0; +input we0; +input [7:0] Di0; +input [2:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[7:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +wire [7:0] Q4 = mem[4]; +wire [7:0] Q5 = mem[5]; +wire [7:0] Q6 = mem[6]; +wire [7:0] Q7 = mem[7]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8] } +endmodule // vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +//vmw: Memory vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +//vmw: Address-size 3 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_WDMA_dat_fifo_flopram_rwsa_8x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// swizzle: 0: start from fifo_0; start from fifo_4 +// width: 0~7, 32x1 in each 32x8 +// -d 3, depth=4 as we have rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_WDMA_cmd_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus cmd_fifo_wr -rd_pipebus cmd_fifo_rd -rd_reg -ram_bypass -d 3 -w 15 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_WDMA_cmd_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , cmd_fifo_wr_prdy + , cmd_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , cmd_fifo_wr_pause +`endif + , cmd_fifo_wr_pd + , cmd_fifo_rd_prdy + , cmd_fifo_rd_pvld + , cmd_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cmd_fifo_wr_prdy; +input cmd_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input cmd_fifo_wr_pause; +`endif +input [14:0] cmd_fifo_wr_pd; +input cmd_fifo_rd_prdy; +output cmd_fifo_rd_pvld; +output [14:0] cmd_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cmd_fifo_wr_busy_int; // copy for internal use +assign cmd_fifo_wr_prdy = !cmd_fifo_wr_busy_int; +assign wr_reserving = cmd_fifo_wr_pvld && !cmd_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [1:0] cmd_fifo_wr_count; // write-side count +wire [1:0] wr_count_next_wr_popping = wr_reserving ? cmd_fifo_wr_count : (cmd_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [1:0] wr_count_next_no_wr_popping = wr_reserving ? (cmd_fifo_wr_count + 1'd1) : cmd_fifo_wr_count; // spyglass disable W164a W484 +wire [1:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_3 = ( wr_count_next_no_wr_popping == 2'd3 ); +wire wr_count_next_is_3 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_3; +wire [1:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [1:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire cmd_fifo_wr_busy_next = wr_count_next_is_3 || // busy next cycle? + (wr_limit_reg != 2'd0 && // check cmd_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || cmd_fifo_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire cmd_fifo_wr_busy_next = wr_count_next_is_3 || // busy next cycle? + (wr_limit_reg != 2'd0 && // check cmd_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_busy_int <= 1'b0; + cmd_fifo_wr_count <= 2'd0; + end else begin + cmd_fifo_wr_busy_int <= cmd_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + cmd_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + cmd_fifo_wr_count <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as cmd_fifo_wr_pvld +// +// RAM +// +reg [1:0] cmd_fifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + cmd_fifo_wr_adr <= (cmd_fifo_wr_adr == 2'd2) ? 2'd0 : (cmd_fifo_wr_adr + 1'd1); + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd_fifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (cmd_fifo_wr_count > 2'd0 || !rd_popping); // note: write occurs next cycle +wire [14:0] cmd_fifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( cmd_fifo_wr_pd ) + , .we ( ram_we ) + , .wa ( cmd_fifo_wr_adr ) + , .ra ( (cmd_fifo_wr_count == 0) ? 2'd3 : cmd_fifo_rd_adr ) + , .dout ( cmd_fifo_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = (cmd_fifo_rd_adr == 2'd2) ? 2'd0 : (cmd_fifo_rd_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd_fifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd_fifo_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd_fifo_rd_pvld_p; // data out of fifo is valid +reg cmd_fifo_rd_pvld_int; // internal copy of cmd_fifo_rd_pvld +assign cmd_fifo_rd_pvld = cmd_fifo_rd_pvld_int; +assign rd_popping = cmd_fifo_rd_pvld_p && !(cmd_fifo_rd_pvld_int && !cmd_fifo_rd_prdy); +reg [1:0] cmd_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [1:0] rd_count_p_next_rd_popping = rd_pushing ? cmd_fifo_rd_count_p : + (cmd_fifo_rd_count_p - 1'd1); +wire [1:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cmd_fifo_rd_count_p + 1'd1) : + cmd_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [1:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign cmd_fifo_rd_pvld_p = cmd_fifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_count_p <= 2'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd_fifo_rd_count_p <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [14:0] cmd_fifo_rd_pd; // output data register +wire rd_req_next = (cmd_fifo_rd_pvld_p || (cmd_fifo_rd_pvld_int && !cmd_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_pvld_int <= 1'b0; + end else begin + cmd_fifo_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + cmd_fifo_rd_pd <= cmd_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + cmd_fifo_rd_pd <= {15{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cmd_fifo_wr_pvld && !cmd_fifo_wr_busy_int) || (cmd_fifo_wr_busy_int != cmd_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (cmd_fifo_rd_pvld_int && cmd_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit : 2'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 2'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 2'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 2'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [1:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 2'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CDP_WDMA_cmd_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cmd_fifo_wr_pvld && !(!cmd_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {30'd0, (wr_limit_reg == 2'd0) ? 2'd3 : wr_limit_reg} ) + , .curr ( {30'd0, cmd_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_WDMA_cmd_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CDP_WDMA_cmd_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [14:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [14:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [14:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [14:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout_p ) + ); +assign dout = (ra == 3) ? di : dout_p; +`else +reg [14:0] ram_ff0; +reg [14:0] ram_ff1; +reg [14:0] ram_ff2; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end +end +reg [14:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = di; +//VCS coverage off + default: dout = {15{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [14:0] Di0; +input [1:0] Ra0; +output [14:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 15'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [14:0] mem[2:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [14:0] Q0 = mem[0]; +wire [14:0] Q1 = mem[1]; +wire [14:0] Q2 = mem[2]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15] } +endmodule // vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +//vmw: Memory vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +//vmw: Address-size 2 +//vmw: Data-size 15 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[14:0] data0[14:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[14:0] data1[14:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_3x15 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +//interrupt fifo +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_CDP_WDMA_intr_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus intr_fifo_wr -rd_pipebus intr_fifo_rd -ram_bypass -d 0 -rd_reg -rd_busy_reg -no_wr_busy -w 1 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CDP_WDMA_intr_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intr_fifo_wr_pvld + , intr_fifo_wr_pd + , intr_fifo_rd_prdy + , intr_fifo_rd_pvld + , intr_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +input intr_fifo_wr_pvld; +input intr_fifo_wr_pd; +input intr_fifo_rd_prdy; +output intr_fifo_rd_pvld; +output intr_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] intr_fifo_rd_pd_p = intr_fifo_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg intr_fifo_rd_prdy_d; // intr_fifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_prdy_d <= 1'b1; + end else begin + intr_fifo_rd_prdy_d <= intr_fifo_rd_prdy; + end +end +wire intr_fifo_rd_prdy_d_o; // combinatorial rd_busy +reg intr_fifo_rd_pvld_int; // internal copy of intr_fifo_rd_pvld +assign intr_fifo_rd_pvld = intr_fifo_rd_pvld_int; +wire intr_fifo_rd_pvld_p = intr_fifo_wr_pvld ; // no real fifo, take from write-side input +reg intr_fifo_rd_pvld_int_o; // internal copy of intr_fifo_rd_pvld_o +wire intr_fifo_rd_pvld_o = intr_fifo_rd_pvld_int_o; +wire rd_popping = intr_fifo_rd_pvld_p && !(intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg intr_fifo_rd_pd_o; // output data register +wire rd_req_next_o = (intr_fifo_rd_pvld_p || (intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int_o <= 1'b0; + end else begin + intr_fifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + intr_fifo_rd_pd_o <= intr_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + intr_fifo_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg intr_fifo_rd_pd; // output data register +reg intr_fifo_rd_pvld_int_d; // so we can bubble-collapse intr_fifo_rd_prdy_d +assign intr_fifo_rd_prdy_d_o = !((intr_fifo_rd_pvld_o && intr_fifo_rd_pvld_int_d && !intr_fifo_rd_prdy_d ) ); +wire rd_req_next = (!intr_fifo_rd_prdy_d_o ? intr_fifo_rd_pvld_o : intr_fifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int <= 1'b0; + intr_fifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) begin + intr_fifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy) ) begin + end else begin + intr_fifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + intr_fifo_rd_pvld_int_d <= intr_fifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) ) begin + case (!intr_fifo_rd_prdy_d_o) + 1'b0: intr_fifo_rd_pd <= intr_fifo_rd_pd_p; + 1'b1: intr_fifo_rd_pd <= intr_fifo_rd_pd_o; +//VCS coverage off + default: intr_fifo_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy)) ) begin + end else begin + intr_fifo_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (intr_fifo_wr_pvld || (intr_fifo_rd_pvld_int && intr_fifo_rd_prdy_d) || (intr_fifo_rd_pvld_int_o && intr_fifo_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CDP_WDMA_intr_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CDP_WDMA_intr_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_cdp.v b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_cdp.v new file mode 100644 index 0000000..fe80048 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_cdp.v @@ -0,0 +1,1280 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cdp.v +module NV_NVDLA_cdp ( + dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp2csb_resp_valid //|> o + ,cdp2csb_resp_pd //|> o + ,cdp2glb_done_intr_pd //|> o + ,cdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,cdp2mcif_rd_req_valid //|> o + ,cdp2mcif_rd_req_ready //|< i + ,cdp2mcif_rd_req_pd //|> o + ,cdp2mcif_wr_req_valid //|> o + ,cdp2mcif_wr_req_ready //|< i + ,cdp2mcif_wr_req_pd //|> o + ,cdp_rdma2csb_resp_valid //|> o + ,cdp_rdma2csb_resp_pd //|> o + ,csb2cdp_rdma_req_pvld //|< i + ,csb2cdp_rdma_req_prdy //|> o + ,csb2cdp_rdma_req_pd //|< i + ,csb2cdp_req_pvld //|< i + ,csb2cdp_req_prdy //|> o + ,csb2cdp_req_pd //|< i + ,mcif2cdp_rd_rsp_valid //|< i + ,mcif2cdp_rd_rsp_ready //|> o + ,mcif2cdp_rd_rsp_pd //|< i + ,mcif2cdp_wr_rsp_complete //|< i + ,pwrbus_ram_pd //|< i + ); +////////////////////////////////////////////////////////////////// +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +// +// NV_NVDLA_cdp_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + output cdp2csb_resp_valid; /* data valid */ + output [33:0] cdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + output [1:0] cdp2glb_done_intr_pd; + output cdp2mcif_rd_cdt_lat_fifo_pop; + output cdp2mcif_rd_req_valid; /* data valid */ + input cdp2mcif_rd_req_ready; /* data return handshake */ + output [47 -1:0] cdp2mcif_rd_req_pd; + output cdp2mcif_wr_req_valid; /* data valid */ + input cdp2mcif_wr_req_ready; /* data return handshake */ + output [66 -1:0] cdp2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ + output cdp_rdma2csb_resp_valid; /* data valid */ + output [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + input csb2cdp_rdma_req_pvld; /* data valid */ + output csb2cdp_rdma_req_prdy; /* data return handshake */ + input [62:0] csb2cdp_rdma_req_pd; + input csb2cdp_req_pvld; /* data valid */ + output csb2cdp_req_prdy; /* data return handshake */ + input [62:0] csb2cdp_req_pd; + input mcif2cdp_rd_rsp_valid; /* data valid */ + output mcif2cdp_rd_rsp_ready; /* data return handshake */ + input [65 -1:0] mcif2cdp_rd_rsp_pd; + input mcif2cdp_wr_rsp_complete; + input [31:0] pwrbus_ram_pd; +////////////////////////////////////////////////////////////////// + wire [1*8 +14:0] cdp_dp2wdma_pd; + wire cdp_dp2wdma_ready; + wire cdp_dp2wdma_valid; + wire [1*8 +22:0] cdp_rdma2dp_pd; + wire cdp_rdma2dp_ready; + wire cdp_rdma2dp_valid; + wire [31:0] dp2reg_d0_out_saturation; + wire [31:0] dp2reg_d0_perf_lut_hybrid; + wire [31:0] dp2reg_d0_perf_lut_le_hit; + wire [31:0] dp2reg_d0_perf_lut_lo_hit; + wire [31:0] dp2reg_d0_perf_lut_oflow; + wire [31:0] dp2reg_d0_perf_lut_uflow; + wire [31:0] dp2reg_d0_perf_write_stall; + wire [31:0] dp2reg_d1_out_saturation; + wire [31:0] dp2reg_d1_perf_lut_hybrid; + wire [31:0] dp2reg_d1_perf_lut_le_hit; + wire [31:0] dp2reg_d1_perf_lut_lo_hit; + wire [31:0] dp2reg_d1_perf_lut_oflow; + wire [31:0] dp2reg_d1_perf_lut_uflow; + wire [31:0] dp2reg_d1_perf_write_stall; + wire dp2reg_done; + wire [31:0] dp2reg_inf_input_num; + wire [15:0] dp2reg_lut_data; + wire [31:0] dp2reg_nan_input_num; + wire mon_op_en_neg; + wire mon_op_en_pos; + wire [1*8 +22:0] nan_preproc_pd; + wire nan_preproc_prdy; + wire nan_preproc_pvld; + wire nvdla_op_gated_clk_core; + wire nvdla_op_gated_clk_wdma; + wire [31:0] reg2dp_cya; + wire [15:0] reg2dp_datin_offset; + wire [15:0] reg2dp_datin_scale; + wire [4:0] reg2dp_datin_shifter; + wire [31:0] reg2dp_datout_offset; + wire [15:0] reg2dp_datout_scale; + wire [5:0] reg2dp_datout_shifter; + wire reg2dp_dma_en; + wire [31:0] reg2dp_dst_base_addr_high; + wire [31:0] reg2dp_dst_base_addr_low; + wire [31:0] reg2dp_dst_line_stride; + wire reg2dp_dst_ram_type; + wire [31:0] reg2dp_dst_surface_stride; + wire reg2dp_interrupt_ptr; + wire reg2dp_lut_access_type; + wire [9:0] reg2dp_lut_addr; + wire [15:0] reg2dp_lut_data; + wire reg2dp_lut_data_trigger; + wire reg2dp_lut_en; + wire reg2dp_lut_hybrid_priority; + wire [5:0] reg2dp_lut_le_end_high; + wire [31:0] reg2dp_lut_le_end_low; + wire reg2dp_lut_le_function; + wire [7:0] reg2dp_lut_le_index_offset; + wire [7:0] reg2dp_lut_le_index_select; + wire [15:0] reg2dp_lut_le_slope_oflow_scale; + wire [4:0] reg2dp_lut_le_slope_oflow_shift; + wire [15:0] reg2dp_lut_le_slope_uflow_scale; + wire [4:0] reg2dp_lut_le_slope_uflow_shift; + wire [5:0] reg2dp_lut_le_start_high; + wire [31:0] reg2dp_lut_le_start_low; + wire [5:0] reg2dp_lut_lo_end_high; + wire [31:0] reg2dp_lut_lo_end_low; + wire [7:0] reg2dp_lut_lo_index_select; + wire [15:0] reg2dp_lut_lo_slope_oflow_scale; + wire [4:0] reg2dp_lut_lo_slope_oflow_shift; + wire [15:0] reg2dp_lut_lo_slope_uflow_scale; + wire [4:0] reg2dp_lut_lo_slope_uflow_shift; + wire [5:0] reg2dp_lut_lo_start_high; + wire [31:0] reg2dp_lut_lo_start_low; + wire reg2dp_lut_oflow_priority; + wire reg2dp_lut_table_id; + wire reg2dp_lut_uflow_priority; + wire reg2dp_mul_bypass; + wire reg2dp_nan_to_zero; + wire [1:0] reg2dp_normalz_len; + wire reg2dp_op_en; + wire reg2dp_sqsum_bypass; + wire [3:0] slcg_op_en; + reg [31:0] mon_gap_between_layers; + reg mon_layer_end_flg; + reg mon_op_en_dly; + reg mon_reg2dp_lut_le_function; + reg mon_reg2dp_mul_bypass; + reg mon_reg2dp_nan_to_zero; + reg [1:0] mon_reg2dp_normalz_len; + reg mon_reg2dp_sqsum_bypass; +////////////////////////////////////////////////////////////////// +//======================================= +//RDMA +//--------------------------------------- + NV_NVDLA_CDP_rdma u_rdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop) + ,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid) + ,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready) + ,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd) + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd[33:0]) + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd[62:0]) + ,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid) + ,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready) + ,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//======================================= +// SLCG gen unit +//--------------------------------------- + NV_NVDLA_CDP_slcg u_slcg_core ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[0]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_core) + ); + NV_NVDLA_CDP_slcg u_slcg_wdma ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[1]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_wdma) + ); +//======================================= +//NaN preproc +//--------------------------------------- + NV_NVDLA_CDP_DP_nan u_DP_nan ( + .nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) + ,.dp2reg_done (dp2reg_done) + ,.nan_preproc_prdy (nan_preproc_prdy) +//,.reg2dp_input_data_type (reg2dp_input_data_type[1:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) + ,.dp2reg_inf_input_num (dp2reg_inf_input_num[31:0]) + ,.dp2reg_nan_input_num (dp2reg_nan_input_num[31:0]) + ,.nan_preproc_pd (nan_preproc_pd) + ,.nan_preproc_pvld (nan_preproc_pvld) + ); +//assign nan_preproc_pd = cdp_rdma2dp_pd; +//assign nan_preproc_pvld = cdp_rdma2dp_valid; +//assign cdp_rdma2dp_ready = nan_preproc_prdy; +//assign dp2reg_inf_input_num = 32'd0; +//assign dp2reg_nan_input_num = 32'd0; +//======================================= +//WDMA +//--------------------------------------- + NV_NVDLA_CDP_wdma u_wdma ( + .nvdla_core_clk (nvdla_op_gated_clk_wdma) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid) + ,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready) + ,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd) + ,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete) + ,.cdp_dp2wdma_valid (cdp_dp2wdma_valid) + ,.cdp_dp2wdma_ready (cdp_dp2wdma_ready) + ,.cdp_dp2wdma_pd (cdp_dp2wdma_pd) + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) + ,.nvdla_core_clk_orig (nvdla_core_clk) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0] ) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0] ) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_op_en (reg2dp_op_en) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ); +//======================================== +//CDP core instance +//---------------------------------------- + NV_NVDLA_CDP_dp u_dp ( + .pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.reg2dp_datin_offset (reg2dp_datin_offset[15:0]) + ,.reg2dp_datin_scale (reg2dp_datin_scale[15:0]) + ,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0]) + ,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) + ,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) + ,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) + ,.reg2dp_lut_access_type (reg2dp_lut_access_type) + ,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) + ,.reg2dp_lut_data (reg2dp_lut_data[15:0]) + ,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) + ,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) + ,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) + ,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) + ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) + ,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) + ,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) + ,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) + ,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) + ,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) + ,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) + ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) + ,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) + ,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) + ,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) + ,.reg2dp_lut_table_id (reg2dp_lut_table_id) + ,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) + ,.reg2dp_mul_bypass (reg2dp_mul_bypass) + ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) + ,.dp2reg_d0_out_saturation (dp2reg_d0_out_saturation[31:0]) + ,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) + ,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) + ,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) + ,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) + ,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) + ,.dp2reg_d1_out_saturation (dp2reg_d1_out_saturation[31:0]) + ,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) + ,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) + ,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) + ,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) + ,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) + ,.dp2reg_lut_data (dp2reg_lut_data[15:0]) + ,.nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp_rdma2dp_valid (nan_preproc_pvld) + ,.cdp_rdma2dp_ready (nan_preproc_prdy) + ,.cdp_rdma2dp_pd (nan_preproc_pd) + ,.cdp_dp2wdma_valid (cdp_dp2wdma_valid) + ,.cdp_dp2wdma_ready (cdp_dp2wdma_ready) + ,.cdp_dp2wdma_pd (cdp_dp2wdma_pd) + ,.nvdla_core_clk_orig (nvdla_core_clk) + ); +//======================================= +//CONFIG instance +//rdma has seperate config register, while wdma share with core +//--------------------------------------- + NV_NVDLA_CDP_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2cdp_req_pd (csb2cdp_req_pd[62:0]) + ,.csb2cdp_req_pvld (csb2cdp_req_pvld) + ,.dp2reg_d0_out_saturation (dp2reg_d0_out_saturation[31:0]) + ,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) + ,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) + ,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) + ,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) + ,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_out_saturation (dp2reg_d1_out_saturation[31:0]) + ,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) + ,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) + ,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) + ,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) + ,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_inf_input_num (dp2reg_inf_input_num[31:0]) + ,.dp2reg_lut_data (dp2reg_lut_data[15:0]) + ,.dp2reg_nan_input_num (dp2reg_nan_input_num[31:0]) + ,.dp2reg_nan_output_num (32'd0) + ,.cdp2csb_resp_pd (cdp2csb_resp_pd[33:0]) + ,.cdp2csb_resp_valid (cdp2csb_resp_valid) + ,.csb2cdp_req_prdy (csb2cdp_req_prdy) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_datin_offset (reg2dp_datin_offset[15:0]) + ,.reg2dp_datin_scale (reg2dp_datin_scale[15:0]) + ,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0]) + ,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) + ,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) + ,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_input_data_type () + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_lut_access_type (reg2dp_lut_access_type) + ,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) + ,.reg2dp_lut_data (reg2dp_lut_data[15:0]) + ,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) + ,.reg2dp_lut_en (reg2dp_lut_en) + ,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) + ,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) + ,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) + ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) + ,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) + ,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) + ,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) + ,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) + ,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) + ,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) + ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) + ,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) + ,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) + ,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) + ,.reg2dp_lut_table_id (reg2dp_lut_table_id) + ,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) + ,.reg2dp_mul_bypass (reg2dp_mul_bypass) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) + ,.slcg_op_en (slcg_op_en[3:0]) + ); +// //============== +// //OBS signals +// //============== +// //assign obs_bus_cdp_core_clk = nvdla_core_clk; +// //assign obs_bus_cdp_core_rstn = nvdla_core_rstn; +// assign obs_bus_cdp_csb_req_vld = csb2cdp_req_pvld; +// assign obs_bus_cdp_csb_req_rdy = csb2cdp_req_prdy; +// assign obs_bus_cdp_rdma_mc_rd_req_vld = cdp2mcif_rd_req_valid; +// assign obs_bus_cdp_rdma_mc_rd_req_rdy = cdp2mcif_rd_req_ready; +// assign obs_bus_cdp_rdma_cv_rd_req_vld = cdp2cvif_rd_req_valid; +// assign obs_bus_cdp_rdma_cv_rd_req_rdy = cdp2cvif_rd_req_ready; +// assign obs_bus_cdp_rdma_mc_rd_rsp_vld = mcif2cdp_rd_rsp_valid; +// assign obs_bus_cdp_rdma_mc_rd_rsp_rdy = mcif2cdp_rd_rsp_ready; +// assign obs_bus_cdp_rdma_cv_rd_rsp_vld = cvif2cdp_rd_rsp_valid; +// assign obs_bus_cdp_rdma_cv_rd_rsp_rdy = cvif2cdp_rd_rsp_ready; +// assign obs_bus_cdp_wdma_mc_wr_vld = cdp2mcif_wr_req_valid; +// assign obs_bus_cdp_wdma_mc_wr_rdy = cdp2mcif_wr_req_ready; +// assign obs_bus_cdp_wdma_cv_wr_vld = cdp2cvif_wr_req_valid; +// assign obs_bus_cdp_wdma_cv_wr_rdy = cdp2cvif_wr_req_ready; +//============== +//============== +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_datin_offset not sign extend") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_datin_offset[15:7]) != (®2dp_datin_offset[15:7]))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_datout_offset not sign extend") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_datout_offset[31:24]) != (®2dp_datout_offset[31:24]))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_le_end not sign extend") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_le_end_high[5:0],reg2dp_lut_le_end_low[31:21]}) != (&{reg2dp_lut_le_end_high[5:0],reg2dp_lut_le_end_low[31:21]}))) )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_lo_end not sign extend") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_lo_end_high[5:0],reg2dp_lut_lo_end_low[31:21]}) != (&{reg2dp_lut_lo_end_high[5:0],reg2dp_lut_lo_end_low[31:21]}))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_le_index_select not sign extend") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_lut_le_index_select[7:5]) != (®2dp_lut_le_index_select[7:5]))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_lo_index_select not sign extend") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_lut_lo_index_select[7:5]) != (®2dp_lut_lo_index_select[7:5]))) )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_le_start not sign extend") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:21]}) != (&{reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:21]}))) )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_lo_start not sign extend") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:21]}) != (&{reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:21]}))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +//function polint +//============== +//cdp core two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_CORE_two_continuous_layer__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 0 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_CDP_CORE_two_continuous_layer__0_COV : cover property (CDP_CORE_two_continuous_layer__0_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_lut_le_function <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_lut_le_function <= reg2dp_lut_le_function; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_lut_le_function <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_mul_bypass <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_mul_bypass <= reg2dp_mul_bypass; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_mul_bypass <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_nan_to_zero <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_nan_to_zero <= reg2dp_nan_to_zero; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_nan_to_zero <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_normalz_len <= {2{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_normalz_len <= reg2dp_normalz_len; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_normalz_len <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_sqsum_bypass <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_sqsum_bypass <= reg2dp_sqsum_bypass; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_sqsum_bypass <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_le_func__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_lut_le_function!=reg2dp_lut_le_function)); + endproperty +// Cover 2 : "(mon_reg2dp_lut_le_function!=reg2dp_lut_le_function)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_le_func__2_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_le_func__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_mul_bypass__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_mul_bypass!=reg2dp_mul_bypass)); + endproperty +// Cover 3 : "(mon_reg2dp_mul_bypass!=reg2dp_mul_bypass)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_mul_bypass__3_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_mul_bypass__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_sqsum_bypass__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_sqsum_bypass!=reg2dp_sqsum_bypass)); + endproperty +// Cover 4 : "(mon_reg2dp_sqsum_bypass!=reg2dp_sqsum_bypass)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_sqsum_bypass__4_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_sqsum_bypass__4_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_nan2zero__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)); + endproperty +// Cover 5 : "(mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_nan2zero__5_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_nan2zero__5_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_lrn_len__6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_normalz_len!=reg2dp_normalz_len)); + endproperty +// Cover 6 : "(mon_reg2dp_normalz_len!=reg2dp_normalz_len)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_lrn_len__6_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_lrn_len__6_cov); + `endif +`endif +//VCS coverage on +//============== +//============== +//&Force internal /^dp2reg/; +endmodule // NV_NVDLA_cdp diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_cdp.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_cdp.v.vcp new file mode 100644 index 0000000..fe80048 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/NV_NVDLA_cdp.v.vcp @@ -0,0 +1,1280 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cdp.v +module NV_NVDLA_cdp ( + dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cdp2csb_resp_valid //|> o + ,cdp2csb_resp_pd //|> o + ,cdp2glb_done_intr_pd //|> o + ,cdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,cdp2mcif_rd_req_valid //|> o + ,cdp2mcif_rd_req_ready //|< i + ,cdp2mcif_rd_req_pd //|> o + ,cdp2mcif_wr_req_valid //|> o + ,cdp2mcif_wr_req_ready //|< i + ,cdp2mcif_wr_req_pd //|> o + ,cdp_rdma2csb_resp_valid //|> o + ,cdp_rdma2csb_resp_pd //|> o + ,csb2cdp_rdma_req_pvld //|< i + ,csb2cdp_rdma_req_prdy //|> o + ,csb2cdp_rdma_req_pd //|< i + ,csb2cdp_req_pvld //|< i + ,csb2cdp_req_prdy //|> o + ,csb2cdp_req_pd //|< i + ,mcif2cdp_rd_rsp_valid //|< i + ,mcif2cdp_rd_rsp_ready //|> o + ,mcif2cdp_rd_rsp_pd //|< i + ,mcif2cdp_wr_rsp_complete //|< i + ,pwrbus_ram_pd //|< i + ); +////////////////////////////////////////////////////////////////// +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +// +// NV_NVDLA_cdp_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + output cdp2csb_resp_valid; /* data valid */ + output [33:0] cdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + output [1:0] cdp2glb_done_intr_pd; + output cdp2mcif_rd_cdt_lat_fifo_pop; + output cdp2mcif_rd_req_valid; /* data valid */ + input cdp2mcif_rd_req_ready; /* data return handshake */ + output [47 -1:0] cdp2mcif_rd_req_pd; + output cdp2mcif_wr_req_valid; /* data valid */ + input cdp2mcif_wr_req_ready; /* data return handshake */ + output [66 -1:0] cdp2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ + output cdp_rdma2csb_resp_valid; /* data valid */ + output [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + input csb2cdp_rdma_req_pvld; /* data valid */ + output csb2cdp_rdma_req_prdy; /* data return handshake */ + input [62:0] csb2cdp_rdma_req_pd; + input csb2cdp_req_pvld; /* data valid */ + output csb2cdp_req_prdy; /* data return handshake */ + input [62:0] csb2cdp_req_pd; + input mcif2cdp_rd_rsp_valid; /* data valid */ + output mcif2cdp_rd_rsp_ready; /* data return handshake */ + input [65 -1:0] mcif2cdp_rd_rsp_pd; + input mcif2cdp_wr_rsp_complete; + input [31:0] pwrbus_ram_pd; +////////////////////////////////////////////////////////////////// + wire [1*8 +14:0] cdp_dp2wdma_pd; + wire cdp_dp2wdma_ready; + wire cdp_dp2wdma_valid; + wire [1*8 +22:0] cdp_rdma2dp_pd; + wire cdp_rdma2dp_ready; + wire cdp_rdma2dp_valid; + wire [31:0] dp2reg_d0_out_saturation; + wire [31:0] dp2reg_d0_perf_lut_hybrid; + wire [31:0] dp2reg_d0_perf_lut_le_hit; + wire [31:0] dp2reg_d0_perf_lut_lo_hit; + wire [31:0] dp2reg_d0_perf_lut_oflow; + wire [31:0] dp2reg_d0_perf_lut_uflow; + wire [31:0] dp2reg_d0_perf_write_stall; + wire [31:0] dp2reg_d1_out_saturation; + wire [31:0] dp2reg_d1_perf_lut_hybrid; + wire [31:0] dp2reg_d1_perf_lut_le_hit; + wire [31:0] dp2reg_d1_perf_lut_lo_hit; + wire [31:0] dp2reg_d1_perf_lut_oflow; + wire [31:0] dp2reg_d1_perf_lut_uflow; + wire [31:0] dp2reg_d1_perf_write_stall; + wire dp2reg_done; + wire [31:0] dp2reg_inf_input_num; + wire [15:0] dp2reg_lut_data; + wire [31:0] dp2reg_nan_input_num; + wire mon_op_en_neg; + wire mon_op_en_pos; + wire [1*8 +22:0] nan_preproc_pd; + wire nan_preproc_prdy; + wire nan_preproc_pvld; + wire nvdla_op_gated_clk_core; + wire nvdla_op_gated_clk_wdma; + wire [31:0] reg2dp_cya; + wire [15:0] reg2dp_datin_offset; + wire [15:0] reg2dp_datin_scale; + wire [4:0] reg2dp_datin_shifter; + wire [31:0] reg2dp_datout_offset; + wire [15:0] reg2dp_datout_scale; + wire [5:0] reg2dp_datout_shifter; + wire reg2dp_dma_en; + wire [31:0] reg2dp_dst_base_addr_high; + wire [31:0] reg2dp_dst_base_addr_low; + wire [31:0] reg2dp_dst_line_stride; + wire reg2dp_dst_ram_type; + wire [31:0] reg2dp_dst_surface_stride; + wire reg2dp_interrupt_ptr; + wire reg2dp_lut_access_type; + wire [9:0] reg2dp_lut_addr; + wire [15:0] reg2dp_lut_data; + wire reg2dp_lut_data_trigger; + wire reg2dp_lut_en; + wire reg2dp_lut_hybrid_priority; + wire [5:0] reg2dp_lut_le_end_high; + wire [31:0] reg2dp_lut_le_end_low; + wire reg2dp_lut_le_function; + wire [7:0] reg2dp_lut_le_index_offset; + wire [7:0] reg2dp_lut_le_index_select; + wire [15:0] reg2dp_lut_le_slope_oflow_scale; + wire [4:0] reg2dp_lut_le_slope_oflow_shift; + wire [15:0] reg2dp_lut_le_slope_uflow_scale; + wire [4:0] reg2dp_lut_le_slope_uflow_shift; + wire [5:0] reg2dp_lut_le_start_high; + wire [31:0] reg2dp_lut_le_start_low; + wire [5:0] reg2dp_lut_lo_end_high; + wire [31:0] reg2dp_lut_lo_end_low; + wire [7:0] reg2dp_lut_lo_index_select; + wire [15:0] reg2dp_lut_lo_slope_oflow_scale; + wire [4:0] reg2dp_lut_lo_slope_oflow_shift; + wire [15:0] reg2dp_lut_lo_slope_uflow_scale; + wire [4:0] reg2dp_lut_lo_slope_uflow_shift; + wire [5:0] reg2dp_lut_lo_start_high; + wire [31:0] reg2dp_lut_lo_start_low; + wire reg2dp_lut_oflow_priority; + wire reg2dp_lut_table_id; + wire reg2dp_lut_uflow_priority; + wire reg2dp_mul_bypass; + wire reg2dp_nan_to_zero; + wire [1:0] reg2dp_normalz_len; + wire reg2dp_op_en; + wire reg2dp_sqsum_bypass; + wire [3:0] slcg_op_en; + reg [31:0] mon_gap_between_layers; + reg mon_layer_end_flg; + reg mon_op_en_dly; + reg mon_reg2dp_lut_le_function; + reg mon_reg2dp_mul_bypass; + reg mon_reg2dp_nan_to_zero; + reg [1:0] mon_reg2dp_normalz_len; + reg mon_reg2dp_sqsum_bypass; +////////////////////////////////////////////////////////////////// +//======================================= +//RDMA +//--------------------------------------- + NV_NVDLA_CDP_rdma u_rdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop) + ,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid) + ,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready) + ,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd) + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd[33:0]) + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd[62:0]) + ,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid) + ,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready) + ,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//======================================= +// SLCG gen unit +//--------------------------------------- + NV_NVDLA_CDP_slcg u_slcg_core ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[0]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_core) + ); + NV_NVDLA_CDP_slcg u_slcg_wdma ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[1]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_wdma) + ); +//======================================= +//NaN preproc +//--------------------------------------- + NV_NVDLA_CDP_DP_nan u_DP_nan ( + .nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp_rdma2dp_pd (cdp_rdma2dp_pd) + ,.cdp_rdma2dp_valid (cdp_rdma2dp_valid) + ,.dp2reg_done (dp2reg_done) + ,.nan_preproc_prdy (nan_preproc_prdy) +//,.reg2dp_input_data_type (reg2dp_input_data_type[1:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.cdp_rdma2dp_ready (cdp_rdma2dp_ready) + ,.dp2reg_inf_input_num (dp2reg_inf_input_num[31:0]) + ,.dp2reg_nan_input_num (dp2reg_nan_input_num[31:0]) + ,.nan_preproc_pd (nan_preproc_pd) + ,.nan_preproc_pvld (nan_preproc_pvld) + ); +//assign nan_preproc_pd = cdp_rdma2dp_pd; +//assign nan_preproc_pvld = cdp_rdma2dp_valid; +//assign cdp_rdma2dp_ready = nan_preproc_prdy; +//assign dp2reg_inf_input_num = 32'd0; +//assign dp2reg_nan_input_num = 32'd0; +//======================================= +//WDMA +//--------------------------------------- + NV_NVDLA_CDP_wdma u_wdma ( + .nvdla_core_clk (nvdla_op_gated_clk_wdma) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid) + ,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready) + ,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd) + ,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete) + ,.cdp_dp2wdma_valid (cdp_dp2wdma_valid) + ,.cdp_dp2wdma_ready (cdp_dp2wdma_ready) + ,.cdp_dp2wdma_pd (cdp_dp2wdma_pd) + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) + ,.nvdla_core_clk_orig (nvdla_core_clk) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0] ) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0] ) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_op_en (reg2dp_op_en) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ); +//======================================== +//CDP core instance +//---------------------------------------- + NV_NVDLA_CDP_dp u_dp ( + .pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.reg2dp_datin_offset (reg2dp_datin_offset[15:0]) + ,.reg2dp_datin_scale (reg2dp_datin_scale[15:0]) + ,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0]) + ,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) + ,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) + ,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) + ,.reg2dp_lut_access_type (reg2dp_lut_access_type) + ,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) + ,.reg2dp_lut_data (reg2dp_lut_data[15:0]) + ,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) + ,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) + ,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) + ,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) + ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) + ,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) + ,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) + ,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) + ,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) + ,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) + ,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) + ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) + ,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) + ,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) + ,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) + ,.reg2dp_lut_table_id (reg2dp_lut_table_id) + ,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) + ,.reg2dp_mul_bypass (reg2dp_mul_bypass) + ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) + ,.dp2reg_d0_out_saturation (dp2reg_d0_out_saturation[31:0]) + ,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) + ,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) + ,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) + ,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) + ,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) + ,.dp2reg_d1_out_saturation (dp2reg_d1_out_saturation[31:0]) + ,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) + ,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) + ,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) + ,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) + ,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) + ,.dp2reg_lut_data (dp2reg_lut_data[15:0]) + ,.nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdp_rdma2dp_valid (nan_preproc_pvld) + ,.cdp_rdma2dp_ready (nan_preproc_prdy) + ,.cdp_rdma2dp_pd (nan_preproc_pd) + ,.cdp_dp2wdma_valid (cdp_dp2wdma_valid) + ,.cdp_dp2wdma_ready (cdp_dp2wdma_ready) + ,.cdp_dp2wdma_pd (cdp_dp2wdma_pd) + ,.nvdla_core_clk_orig (nvdla_core_clk) + ); +//======================================= +//CONFIG instance +//rdma has seperate config register, while wdma share with core +//--------------------------------------- + NV_NVDLA_CDP_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2cdp_req_pd (csb2cdp_req_pd[62:0]) + ,.csb2cdp_req_pvld (csb2cdp_req_pvld) + ,.dp2reg_d0_out_saturation (dp2reg_d0_out_saturation[31:0]) + ,.dp2reg_d0_perf_lut_hybrid (dp2reg_d0_perf_lut_hybrid[31:0]) + ,.dp2reg_d0_perf_lut_le_hit (dp2reg_d0_perf_lut_le_hit[31:0]) + ,.dp2reg_d0_perf_lut_lo_hit (dp2reg_d0_perf_lut_lo_hit[31:0]) + ,.dp2reg_d0_perf_lut_oflow (dp2reg_d0_perf_lut_oflow[31:0]) + ,.dp2reg_d0_perf_lut_uflow (dp2reg_d0_perf_lut_uflow[31:0]) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_out_saturation (dp2reg_d1_out_saturation[31:0]) + ,.dp2reg_d1_perf_lut_hybrid (dp2reg_d1_perf_lut_hybrid[31:0]) + ,.dp2reg_d1_perf_lut_le_hit (dp2reg_d1_perf_lut_le_hit[31:0]) + ,.dp2reg_d1_perf_lut_lo_hit (dp2reg_d1_perf_lut_lo_hit[31:0]) + ,.dp2reg_d1_perf_lut_oflow (dp2reg_d1_perf_lut_oflow[31:0]) + ,.dp2reg_d1_perf_lut_uflow (dp2reg_d1_perf_lut_uflow[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_inf_input_num (dp2reg_inf_input_num[31:0]) + ,.dp2reg_lut_data (dp2reg_lut_data[15:0]) + ,.dp2reg_nan_input_num (dp2reg_nan_input_num[31:0]) + ,.dp2reg_nan_output_num (32'd0) + ,.cdp2csb_resp_pd (cdp2csb_resp_pd[33:0]) + ,.cdp2csb_resp_valid (cdp2csb_resp_valid) + ,.csb2cdp_req_prdy (csb2cdp_req_prdy) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_datin_offset (reg2dp_datin_offset[15:0]) + ,.reg2dp_datin_scale (reg2dp_datin_scale[15:0]) + ,.reg2dp_datin_shifter (reg2dp_datin_shifter[4:0]) + ,.reg2dp_datout_offset (reg2dp_datout_offset[31:0]) + ,.reg2dp_datout_scale (reg2dp_datout_scale[15:0]) + ,.reg2dp_datout_shifter (reg2dp_datout_shifter[5:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_input_data_type () + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_lut_access_type (reg2dp_lut_access_type) + ,.reg2dp_lut_addr (reg2dp_lut_addr[9:0]) + ,.reg2dp_lut_data (reg2dp_lut_data[15:0]) + ,.reg2dp_lut_data_trigger (reg2dp_lut_data_trigger) + ,.reg2dp_lut_en (reg2dp_lut_en) + ,.reg2dp_lut_hybrid_priority (reg2dp_lut_hybrid_priority) + ,.reg2dp_lut_le_end_high (reg2dp_lut_le_end_high[5:0]) + ,.reg2dp_lut_le_end_low (reg2dp_lut_le_end_low[31:0]) + ,.reg2dp_lut_le_function (reg2dp_lut_le_function) + ,.reg2dp_lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) + ,.reg2dp_lut_le_index_select (reg2dp_lut_le_index_select[7:0]) + ,.reg2dp_lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) + ,.reg2dp_lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) + ,.reg2dp_lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) + ,.reg2dp_lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) + ,.reg2dp_lut_le_start_high (reg2dp_lut_le_start_high[5:0]) + ,.reg2dp_lut_le_start_low (reg2dp_lut_le_start_low[31:0]) + ,.reg2dp_lut_lo_end_high (reg2dp_lut_lo_end_high[5:0]) + ,.reg2dp_lut_lo_end_low (reg2dp_lut_lo_end_low[31:0]) + ,.reg2dp_lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) + ,.reg2dp_lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) + ,.reg2dp_lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) + ,.reg2dp_lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) + ,.reg2dp_lut_lo_start_high (reg2dp_lut_lo_start_high[5:0]) + ,.reg2dp_lut_lo_start_low (reg2dp_lut_lo_start_low[31:0]) + ,.reg2dp_lut_oflow_priority (reg2dp_lut_oflow_priority) + ,.reg2dp_lut_table_id (reg2dp_lut_table_id) + ,.reg2dp_lut_uflow_priority (reg2dp_lut_uflow_priority) + ,.reg2dp_mul_bypass (reg2dp_mul_bypass) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_normalz_len (reg2dp_normalz_len[1:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_sqsum_bypass (reg2dp_sqsum_bypass) + ,.slcg_op_en (slcg_op_en[3:0]) + ); +// //============== +// //OBS signals +// //============== +// //assign obs_bus_cdp_core_clk = nvdla_core_clk; +// //assign obs_bus_cdp_core_rstn = nvdla_core_rstn; +// assign obs_bus_cdp_csb_req_vld = csb2cdp_req_pvld; +// assign obs_bus_cdp_csb_req_rdy = csb2cdp_req_prdy; +// assign obs_bus_cdp_rdma_mc_rd_req_vld = cdp2mcif_rd_req_valid; +// assign obs_bus_cdp_rdma_mc_rd_req_rdy = cdp2mcif_rd_req_ready; +// assign obs_bus_cdp_rdma_cv_rd_req_vld = cdp2cvif_rd_req_valid; +// assign obs_bus_cdp_rdma_cv_rd_req_rdy = cdp2cvif_rd_req_ready; +// assign obs_bus_cdp_rdma_mc_rd_rsp_vld = mcif2cdp_rd_rsp_valid; +// assign obs_bus_cdp_rdma_mc_rd_rsp_rdy = mcif2cdp_rd_rsp_ready; +// assign obs_bus_cdp_rdma_cv_rd_rsp_vld = cvif2cdp_rd_rsp_valid; +// assign obs_bus_cdp_rdma_cv_rd_rsp_rdy = cvif2cdp_rd_rsp_ready; +// assign obs_bus_cdp_wdma_mc_wr_vld = cdp2mcif_wr_req_valid; +// assign obs_bus_cdp_wdma_mc_wr_rdy = cdp2mcif_wr_req_ready; +// assign obs_bus_cdp_wdma_cv_wr_vld = cdp2cvif_wr_req_valid; +// assign obs_bus_cdp_wdma_cv_wr_rdy = cdp2cvif_wr_req_ready; +//============== +//============== +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_datin_offset not sign extend") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_datin_offset[15:7]) != (®2dp_datin_offset[15:7]))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_datout_offset not sign extend") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_datout_offset[31:24]) != (®2dp_datout_offset[31:24]))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_le_end not sign extend") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_le_end_high[5:0],reg2dp_lut_le_end_low[31:21]}) != (&{reg2dp_lut_le_end_high[5:0],reg2dp_lut_le_end_low[31:21]}))) )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_lo_end not sign extend") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_lo_end_high[5:0],reg2dp_lut_lo_end_low[31:21]}) != (&{reg2dp_lut_lo_end_high[5:0],reg2dp_lut_lo_end_low[31:21]}))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_le_index_select not sign extend") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_lut_le_index_select[7:5]) != (®2dp_lut_le_index_select[7:5]))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_lo_index_select not sign extend") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|reg2dp_lut_lo_index_select[7:5]) != (®2dp_lut_lo_index_select[7:5]))) )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_le_start not sign extend") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:21]}) != (&{reg2dp_lut_le_start_high[5:0],reg2dp_lut_le_start_low[31:21]}))) )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CDP reg2dp_lut_lo_start not sign extend") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & ((((|{reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:21]}) != (&{reg2dp_lut_lo_start_high[5:0],reg2dp_lut_lo_start_low[31:21]}))))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +//function polint +//============== +//cdp core two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property CDP_CORE_two_continuous_layer__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 0 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_CDP_CORE_two_continuous_layer__0_COV : cover property (CDP_CORE_two_continuous_layer__0_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_lut_le_function <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_lut_le_function <= reg2dp_lut_le_function; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_lut_le_function <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_mul_bypass <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_mul_bypass <= reg2dp_mul_bypass; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_mul_bypass <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_nan_to_zero <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_nan_to_zero <= reg2dp_nan_to_zero; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_nan_to_zero <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_normalz_len <= {2{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_normalz_len <= reg2dp_normalz_len; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_normalz_len <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_sqsum_bypass <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_sqsum_bypass <= reg2dp_sqsum_bypass; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_sqsum_bypass <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_le_func__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_lut_le_function!=reg2dp_lut_le_function)); + endproperty +// Cover 2 : "(mon_reg2dp_lut_le_function!=reg2dp_lut_le_function)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_le_func__2_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_le_func__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_mul_bypass__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_mul_bypass!=reg2dp_mul_bypass)); + endproperty +// Cover 3 : "(mon_reg2dp_mul_bypass!=reg2dp_mul_bypass)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_mul_bypass__3_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_mul_bypass__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_sqsum_bypass__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_sqsum_bypass!=reg2dp_sqsum_bypass)); + endproperty +// Cover 4 : "(mon_reg2dp_sqsum_bypass!=reg2dp_sqsum_bypass)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_sqsum_bypass__4_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_sqsum_bypass__4_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_nan2zero__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)); + endproperty +// Cover 5 : "(mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_nan2zero__5_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_nan2zero__5_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property CDP_CORE_two_continuous_changed_layer__change_lrn_len__6_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_normalz_len!=reg2dp_normalz_len)); + endproperty +// Cover 6 : "(mon_reg2dp_normalz_len!=reg2dp_normalz_len)" + FUNCPOINT_CDP_CORE_two_continuous_changed_layer__change_lrn_len__6_COV : cover property (CDP_CORE_two_continuous_changed_layer__change_lrn_len__6_cov); + `endif +`endif +//VCS coverage on +//============== +//============== +//&Force internal /^dp2reg/; +endmodule // NV_NVDLA_cdp diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/fp_format_cvt.v b/designs/src/NVDLA/vmod/nvdla/cdp/fp_format_cvt.v new file mode 100644 index 0000000..05cffc9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/fp_format_cvt.v @@ -0,0 +1,413 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: fp_format_cvt.v +module fp_format_cvt ( + FMcvt_in_vld //|< i + ,FMcvt_out_rdy //|< i + ,fp16to17_in_X0 //|< i + ,fp16to32_in_X0 //|< i + ,fp16to32_in_X1 //|< i + ,lut_X_info_in //|< i + ,lut_X_sel_in //|< i + ,lut_Y_info_in //|< i + ,lut_Y_sel_in //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,uint16tofp17_Xin //|< i + ,FMcvt_in_rdy //|> o + ,FMcvt_out_vld //|> o + ,fp16to17_out_X0 //|> o + ,fp16to32_out_X0 //|> o + ,fp16to32_out_X1 //|> o + ,lut_X_info_out //|> o + ,lut_X_sel_out //|> o + ,lut_Y_info_out //|> o + ,lut_Y_sel_out //|> o + ,uint16tofp17_Xout //|> o + ); +input FMcvt_in_vld; +input FMcvt_out_rdy; +input [15:0] fp16to17_in_X0; +input [15:0] fp16to32_in_X0; +input [15:0] fp16to32_in_X1; +input [1:0] lut_X_info_in; +input [0:0] lut_X_sel_in; +input [1:0] lut_Y_info_in; +input [0:0] lut_Y_sel_in; +input nvdla_core_clk; +input nvdla_core_rstn; +input [15:0] uint16tofp17_Xin; +output FMcvt_in_rdy; +output FMcvt_out_vld; +output [16:0] fp16to17_out_X0; +output [31:0] fp16to32_out_X0; +output [31:0] fp16to32_out_X1; +output [1:0] lut_X_info_out; +output [0:0] lut_X_sel_out; +output [1:0] lut_Y_info_out; +output [0:0] lut_Y_sel_out; +output [16:0] uint16tofp17_Xout; +wire fp16to17_in_X0_prdy; +wire fp16to17_in_X0_pvld; +wire fp16to17_out_X0_prdy; +wire fp16to17_out_X0_pvld; +wire fp16to32_in_X0_prdy; +wire fp16to32_in_X0_pvld; +wire fp16to32_in_X1_prdy; +wire fp16to32_in_X1_pvld; +wire fp16to32_out_X0_prdy; +wire fp16to32_out_X0_pvld; +wire fp16to32_out_X1_prdy; +wire fp16to32_out_X1_pvld; +wire [5:0] info_pipe_in_pd; +wire [5:0] info_pipe_in_pd_d0; +wire [5:0] info_pipe_in_pd_d1; +wire info_pipe_in_rdy; +wire info_pipe_in_rdy_d0; +wire info_pipe_in_rdy_d1; +wire info_pipe_in_vld; +wire info_pipe_in_vld_d0; +wire info_pipe_in_vld_d1; +wire [5:0] info_pipe_out_pd; +wire info_pipe_out_rdy; +wire info_pipe_out_vld; +wire [4:0] rdys_in; +wire uint16tofp17_Xin_prdy; +wire uint16tofp17_Xin_pvld; +wire uint16tofp17_Xout_prdy; +wire uint16tofp17_Xout_pvld; +wire [4:0] vlds_out; +/////////////////////////////////// +/////////////////////////////////// +assign FMcvt_in_rdy = &rdys_in; +/////////////////////////////////// +assign fp16to32_in_X0_pvld = FMcvt_in_vld & (&rdys_in[3:0]); +assign fp16to32_in_X1_pvld = FMcvt_in_vld & (&{rdys_in[4] ,rdys_in[2:0]}); +assign fp16to17_in_X0_pvld = FMcvt_in_vld & (&{rdys_in[4:3],rdys_in[1:0]}); +assign uint16tofp17_Xin_pvld = FMcvt_in_vld & (&{rdys_in[4:2],rdys_in[0]}); +//assign fp16to32_in_Y0_pvld = FMcvt_in_vld & (&{rdys_in[8:5],rdys_in[3:0]}); +//assign fp16to32_in_Y1_pvld = FMcvt_in_vld & (&{rdys_in[8:4],rdys_in[2:0]}); +//assign fp16to17_in_Y0_pvld = FMcvt_in_vld & (&{rdys_in[8:3],rdys_in[1:0]}); +//assign uint16tofp17_Yin_pvld = FMcvt_in_vld & (&{rdys_in[8:2],rdys_in[ 0]}); +assign info_pipe_in_vld = FMcvt_in_vld & (&rdys_in[4:1]); +assign rdys_in = {fp16to32_in_X0_prdy, fp16to32_in_X1_prdy, fp16to17_in_X0_prdy, uint16tofp17_Xin_prdy, +//fp16to32_in_Y0_prdy, fp16to32_in_Y1_prdy, fp16to17_in_Y0_prdy, uint16tofp17_Yin_prdy, + info_pipe_in_rdy}; +/////////////////////////////////////////////// +HLS_fp16_to_fp32 u_X_fp16_to_fp32_0 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16to32_in_X0[15:0]) //|< i + ,.chn_a_rsc_vz (fp16to32_in_X0_pvld) //|< w + ,.chn_a_rsc_lz (fp16to32_in_X0_prdy) //|> w + ,.chn_o_rsc_z (fp16to32_out_X0[31:0]) //|> o + ,.chn_o_rsc_vz (fp16to32_out_X0_prdy) //|< w + ,.chn_o_rsc_lz (fp16to32_out_X0_pvld) //|> w + ); +HLS_fp16_to_fp32 u_X_fp16_to_fp32_1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16to32_in_X1[15:0]) //|< i + ,.chn_a_rsc_vz (fp16to32_in_X1_pvld) //|< w + ,.chn_a_rsc_lz (fp16to32_in_X1_prdy) //|> w + ,.chn_o_rsc_z (fp16to32_out_X1[31:0]) //|> o + ,.chn_o_rsc_vz (fp16to32_out_X1_prdy) //|< w + ,.chn_o_rsc_lz (fp16to32_out_X1_pvld) //|> w + ); +HLS_fp16_to_fp17 u_X_fp16_to_fp17 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16to17_in_X0[15:0]) //|< i + ,.chn_a_rsc_vz (fp16to17_in_X0_pvld) //|< w + ,.chn_a_rsc_lz (fp16to17_in_X0_prdy) //|> w + ,.chn_o_rsc_z (fp16to17_out_X0[16:0]) //|> o + ,.chn_o_rsc_vz (fp16to17_out_X0_prdy) //|< w + ,.chn_o_rsc_lz (fp16to17_out_X0_pvld) //|> w + ); +HLS_uint16_to_fp17 u_X_uint16_to_fp17 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (uint16tofp17_Xin[15:0]) //|< i + ,.chn_a_rsc_vz (uint16tofp17_Xin_pvld) //|< w + ,.chn_a_rsc_lz (uint16tofp17_Xin_prdy) //|> w + ,.chn_o_rsc_z (uint16tofp17_Xout[16:0]) //|> o + ,.chn_o_rsc_vz (uint16tofp17_Xout_prdy) //|< w + ,.chn_o_rsc_lz (uint16tofp17_Xout_pvld) //|> w + ); +///////////////////////////////////////////////////// +//&Instance HLS_fp16_to_fp32 u_Y_fp16_to_fp32_0; +//&Connect chn_a_rsc_z fp16to32_in_Y0[15:0]; +//&Connect chn_a_rsc_vz fp16to32_in_Y0_pvld; +//&Connect chn_a_rsc_lz fp16to32_in_Y0_prdy; +//&Connect chn_o_rsc_z fp16to32_out_Y0; +//&Connect chn_o_rsc_vz fp16to32_out_Y0_prdy; +//&Connect chn_o_rsc_lz fp16to32_out_Y0_pvld; +// +//&Instance HLS_fp16_to_fp32 u_Y_fp16_to_fp32_1; +//&Connect chn_a_rsc_z fp16to32_in_Y1[15:0]; +//&Connect chn_a_rsc_vz fp16to32_in_Y1_pvld; +//&Connect chn_a_rsc_lz fp16to32_in_Y1_prdy; +//&Connect chn_o_rsc_z fp16to32_out_Y1; +//&Connect chn_o_rsc_vz fp16to32_out_Y1_prdy; +//&Connect chn_o_rsc_lz fp16to32_out_Y1_pvld; +// +//&Instance HLS_fp16_to_fp17 u_Y_fp16_to_fp17; +//&Connect chn_a_rsc_z fp16to17_in_Y0[15:0]; +//&Connect chn_a_rsc_vz fp16to17_in_Y0_pvld; +//&Connect chn_a_rsc_lz fp16to17_in_Y0_prdy; +//&Connect chn_o_rsc_z fp16to17_out_Y0; +//&Connect chn_o_rsc_vz fp16to17_out_Y0_prdy; +//&Connect chn_o_rsc_lz fp16to17_out_Y0_pvld; +// +//&Instance HLS_uint16_to_fp17 u_Y_uint16_to_fp17; +//&Connect chn_a_rsc_z uint16tofp17_Yin[15:0]; +//&Connect chn_a_rsc_vz uint16tofp17_Yin_pvld; +//&Connect chn_a_rsc_lz uint16tofp17_Yin_prdy; +//&Connect chn_o_rsc_z uint16tofp17_Yout; +//&Connect chn_o_rsc_vz uint16tofp17_Yout_prdy; +//&Connect chn_o_rsc_lz uint16tofp17_Yout_pvld; +//////////////////////////////////////////////////// +assign info_pipe_in_pd = {lut_Y_sel_in[0],lut_X_sel_in[0],lut_Y_info_in[1:0],lut_X_info_in[1:0]}; +// need update if NVDLA_HLS_FP16TO32_LATENCY != NVDLA_HLS_FP16TO17_LATENCY +assign info_pipe_in_vld_d0 = info_pipe_in_vld; +assign info_pipe_in_rdy = info_pipe_in_rdy_d0; +assign info_pipe_in_pd_d0[5:0] = info_pipe_in_pd[5:0]; +FP_FORMAT_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.info_pipe_in_pd_d0 (info_pipe_in_pd_d0[5:0]) //|< w + ,.info_pipe_in_rdy_d1 (info_pipe_in_rdy_d1) //|< w + ,.info_pipe_in_vld_d0 (info_pipe_in_vld_d0) //|< w + ,.info_pipe_in_pd_d1 (info_pipe_in_pd_d1[5:0]) //|> w + ,.info_pipe_in_rdy_d0 (info_pipe_in_rdy_d0) //|> w + ,.info_pipe_in_vld_d1 (info_pipe_in_vld_d1) //|> w + ); +assign info_pipe_out_vld = info_pipe_in_vld_d1; +assign info_pipe_in_rdy_d1 = info_pipe_out_rdy; +assign info_pipe_out_pd[5:0] = info_pipe_in_pd_d1[5:0]; +assign {lut_Y_sel_out[0],lut_X_sel_out[0],lut_Y_info_out[1:0],lut_X_info_out[1:0]} = info_pipe_out_pd; +//NVDLA_HLS_FP16TO32_LATENCY and NVDLA_HLS_FP16TO17_LATENCY must equal +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"NVDLA_HLS_FP16TO32_LATENCY and NVDLA_HLS_FP16TO17_LATENCY must be same value") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, 1 != 1); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////// +assign vlds_out = {fp16to32_out_X0_pvld,fp16to32_out_X1_pvld,fp16to17_out_X0_pvld,uint16tofp17_Xout_pvld, + /*fp16to32_out_Y0_pvld,fp16to32_out_Y1_pvld,fp16to17_out_Y0_pvld,uint16tofp17_Yout_pvld,*/info_pipe_out_vld}; +assign fp16to32_out_X0_prdy = FMcvt_out_rdy & (&vlds_out[3:0]); +assign fp16to32_out_X1_prdy = FMcvt_out_rdy & (&{vlds_out[4],vlds_out[2:0]}); +assign fp16to17_out_X0_prdy = FMcvt_out_rdy & (&{vlds_out[4:3],vlds_out[1:0]}); +assign uint16tofp17_Xout_prdy = FMcvt_out_rdy & (&{vlds_out[4:2],vlds_out[0]}); +//assign fp16to32_out_Y0_prdy = FMcvt_out_rdy & (&{vlds_out[8:5],vlds_out[3:0]}); +//assign fp16to32_out_Y1_prdy = FMcvt_out_rdy & (&{vlds_out[8:4],vlds_out[2:0]}); +//assign fp16to17_out_Y0_prdy = FMcvt_out_rdy & (&{vlds_out[8:3],vlds_out[1:0]}); +//assign uint16tofp17_Yout_prdy = FMcvt_out_rdy & (&{vlds_out[8:2],vlds_out[ 0]}); +assign info_pipe_out_rdy = FMcvt_out_rdy & (&vlds_out[4:1]); +assign FMcvt_out_vld = &vlds_out; +//////////////////////////// +endmodule // fp_format_cvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none info_pipe_in_pd_d1[5:0] (info_pipe_in_vld_d1,info_pipe_in_rdy_d1) <= info_pipe_in_pd_d0[5:0] (info_pipe_in_vld_d0,info_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_FORMAT_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,info_pipe_in_pd_d0 + ,info_pipe_in_rdy_d1 + ,info_pipe_in_vld_d0 + ,info_pipe_in_pd_d1 + ,info_pipe_in_rdy_d0 + ,info_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [5:0] info_pipe_in_pd_d0; +input info_pipe_in_rdy_d1; +input info_pipe_in_vld_d0; +output [5:0] info_pipe_in_pd_d1; +output info_pipe_in_rdy_d0; +output info_pipe_in_vld_d1; +reg [5:0] info_pipe_in_pd_d1; +reg info_pipe_in_rdy_d0; +reg info_pipe_in_vld_d1; +reg [5:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? info_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && info_pipe_in_vld_d0)? info_pipe_in_pd_d0[5:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + info_pipe_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or info_pipe_in_rdy_d1 + or p1_pipe_data + ) begin + info_pipe_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = info_pipe_in_rdy_d1; + info_pipe_in_pd_d1[5:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (info_pipe_in_vld_d1^info_pipe_in_rdy_d1^info_pipe_in_vld_d0^info_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_3x (nvdla_core_clk, `ASSERT_RESET, (info_pipe_in_vld_d0 && !info_pipe_in_rdy_d0), (info_pipe_in_vld_d0), (info_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_FORMAT_CVT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/fp_format_cvt.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/fp_format_cvt.v.vcp new file mode 100644 index 0000000..05cffc9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/fp_format_cvt.v.vcp @@ -0,0 +1,413 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: fp_format_cvt.v +module fp_format_cvt ( + FMcvt_in_vld //|< i + ,FMcvt_out_rdy //|< i + ,fp16to17_in_X0 //|< i + ,fp16to32_in_X0 //|< i + ,fp16to32_in_X1 //|< i + ,lut_X_info_in //|< i + ,lut_X_sel_in //|< i + ,lut_Y_info_in //|< i + ,lut_Y_sel_in //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,uint16tofp17_Xin //|< i + ,FMcvt_in_rdy //|> o + ,FMcvt_out_vld //|> o + ,fp16to17_out_X0 //|> o + ,fp16to32_out_X0 //|> o + ,fp16to32_out_X1 //|> o + ,lut_X_info_out //|> o + ,lut_X_sel_out //|> o + ,lut_Y_info_out //|> o + ,lut_Y_sel_out //|> o + ,uint16tofp17_Xout //|> o + ); +input FMcvt_in_vld; +input FMcvt_out_rdy; +input [15:0] fp16to17_in_X0; +input [15:0] fp16to32_in_X0; +input [15:0] fp16to32_in_X1; +input [1:0] lut_X_info_in; +input [0:0] lut_X_sel_in; +input [1:0] lut_Y_info_in; +input [0:0] lut_Y_sel_in; +input nvdla_core_clk; +input nvdla_core_rstn; +input [15:0] uint16tofp17_Xin; +output FMcvt_in_rdy; +output FMcvt_out_vld; +output [16:0] fp16to17_out_X0; +output [31:0] fp16to32_out_X0; +output [31:0] fp16to32_out_X1; +output [1:0] lut_X_info_out; +output [0:0] lut_X_sel_out; +output [1:0] lut_Y_info_out; +output [0:0] lut_Y_sel_out; +output [16:0] uint16tofp17_Xout; +wire fp16to17_in_X0_prdy; +wire fp16to17_in_X0_pvld; +wire fp16to17_out_X0_prdy; +wire fp16to17_out_X0_pvld; +wire fp16to32_in_X0_prdy; +wire fp16to32_in_X0_pvld; +wire fp16to32_in_X1_prdy; +wire fp16to32_in_X1_pvld; +wire fp16to32_out_X0_prdy; +wire fp16to32_out_X0_pvld; +wire fp16to32_out_X1_prdy; +wire fp16to32_out_X1_pvld; +wire [5:0] info_pipe_in_pd; +wire [5:0] info_pipe_in_pd_d0; +wire [5:0] info_pipe_in_pd_d1; +wire info_pipe_in_rdy; +wire info_pipe_in_rdy_d0; +wire info_pipe_in_rdy_d1; +wire info_pipe_in_vld; +wire info_pipe_in_vld_d0; +wire info_pipe_in_vld_d1; +wire [5:0] info_pipe_out_pd; +wire info_pipe_out_rdy; +wire info_pipe_out_vld; +wire [4:0] rdys_in; +wire uint16tofp17_Xin_prdy; +wire uint16tofp17_Xin_pvld; +wire uint16tofp17_Xout_prdy; +wire uint16tofp17_Xout_pvld; +wire [4:0] vlds_out; +/////////////////////////////////// +/////////////////////////////////// +assign FMcvt_in_rdy = &rdys_in; +/////////////////////////////////// +assign fp16to32_in_X0_pvld = FMcvt_in_vld & (&rdys_in[3:0]); +assign fp16to32_in_X1_pvld = FMcvt_in_vld & (&{rdys_in[4] ,rdys_in[2:0]}); +assign fp16to17_in_X0_pvld = FMcvt_in_vld & (&{rdys_in[4:3],rdys_in[1:0]}); +assign uint16tofp17_Xin_pvld = FMcvt_in_vld & (&{rdys_in[4:2],rdys_in[0]}); +//assign fp16to32_in_Y0_pvld = FMcvt_in_vld & (&{rdys_in[8:5],rdys_in[3:0]}); +//assign fp16to32_in_Y1_pvld = FMcvt_in_vld & (&{rdys_in[8:4],rdys_in[2:0]}); +//assign fp16to17_in_Y0_pvld = FMcvt_in_vld & (&{rdys_in[8:3],rdys_in[1:0]}); +//assign uint16tofp17_Yin_pvld = FMcvt_in_vld & (&{rdys_in[8:2],rdys_in[ 0]}); +assign info_pipe_in_vld = FMcvt_in_vld & (&rdys_in[4:1]); +assign rdys_in = {fp16to32_in_X0_prdy, fp16to32_in_X1_prdy, fp16to17_in_X0_prdy, uint16tofp17_Xin_prdy, +//fp16to32_in_Y0_prdy, fp16to32_in_Y1_prdy, fp16to17_in_Y0_prdy, uint16tofp17_Yin_prdy, + info_pipe_in_rdy}; +/////////////////////////////////////////////// +HLS_fp16_to_fp32 u_X_fp16_to_fp32_0 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16to32_in_X0[15:0]) //|< i + ,.chn_a_rsc_vz (fp16to32_in_X0_pvld) //|< w + ,.chn_a_rsc_lz (fp16to32_in_X0_prdy) //|> w + ,.chn_o_rsc_z (fp16to32_out_X0[31:0]) //|> o + ,.chn_o_rsc_vz (fp16to32_out_X0_prdy) //|< w + ,.chn_o_rsc_lz (fp16to32_out_X0_pvld) //|> w + ); +HLS_fp16_to_fp32 u_X_fp16_to_fp32_1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16to32_in_X1[15:0]) //|< i + ,.chn_a_rsc_vz (fp16to32_in_X1_pvld) //|< w + ,.chn_a_rsc_lz (fp16to32_in_X1_prdy) //|> w + ,.chn_o_rsc_z (fp16to32_out_X1[31:0]) //|> o + ,.chn_o_rsc_vz (fp16to32_out_X1_prdy) //|< w + ,.chn_o_rsc_lz (fp16to32_out_X1_pvld) //|> w + ); +HLS_fp16_to_fp17 u_X_fp16_to_fp17 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16to17_in_X0[15:0]) //|< i + ,.chn_a_rsc_vz (fp16to17_in_X0_pvld) //|< w + ,.chn_a_rsc_lz (fp16to17_in_X0_prdy) //|> w + ,.chn_o_rsc_z (fp16to17_out_X0[16:0]) //|> o + ,.chn_o_rsc_vz (fp16to17_out_X0_prdy) //|< w + ,.chn_o_rsc_lz (fp16to17_out_X0_pvld) //|> w + ); +HLS_uint16_to_fp17 u_X_uint16_to_fp17 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (uint16tofp17_Xin[15:0]) //|< i + ,.chn_a_rsc_vz (uint16tofp17_Xin_pvld) //|< w + ,.chn_a_rsc_lz (uint16tofp17_Xin_prdy) //|> w + ,.chn_o_rsc_z (uint16tofp17_Xout[16:0]) //|> o + ,.chn_o_rsc_vz (uint16tofp17_Xout_prdy) //|< w + ,.chn_o_rsc_lz (uint16tofp17_Xout_pvld) //|> w + ); +///////////////////////////////////////////////////// +//&Instance HLS_fp16_to_fp32 u_Y_fp16_to_fp32_0; +//&Connect chn_a_rsc_z fp16to32_in_Y0[15:0]; +//&Connect chn_a_rsc_vz fp16to32_in_Y0_pvld; +//&Connect chn_a_rsc_lz fp16to32_in_Y0_prdy; +//&Connect chn_o_rsc_z fp16to32_out_Y0; +//&Connect chn_o_rsc_vz fp16to32_out_Y0_prdy; +//&Connect chn_o_rsc_lz fp16to32_out_Y0_pvld; +// +//&Instance HLS_fp16_to_fp32 u_Y_fp16_to_fp32_1; +//&Connect chn_a_rsc_z fp16to32_in_Y1[15:0]; +//&Connect chn_a_rsc_vz fp16to32_in_Y1_pvld; +//&Connect chn_a_rsc_lz fp16to32_in_Y1_prdy; +//&Connect chn_o_rsc_z fp16to32_out_Y1; +//&Connect chn_o_rsc_vz fp16to32_out_Y1_prdy; +//&Connect chn_o_rsc_lz fp16to32_out_Y1_pvld; +// +//&Instance HLS_fp16_to_fp17 u_Y_fp16_to_fp17; +//&Connect chn_a_rsc_z fp16to17_in_Y0[15:0]; +//&Connect chn_a_rsc_vz fp16to17_in_Y0_pvld; +//&Connect chn_a_rsc_lz fp16to17_in_Y0_prdy; +//&Connect chn_o_rsc_z fp16to17_out_Y0; +//&Connect chn_o_rsc_vz fp16to17_out_Y0_prdy; +//&Connect chn_o_rsc_lz fp16to17_out_Y0_pvld; +// +//&Instance HLS_uint16_to_fp17 u_Y_uint16_to_fp17; +//&Connect chn_a_rsc_z uint16tofp17_Yin[15:0]; +//&Connect chn_a_rsc_vz uint16tofp17_Yin_pvld; +//&Connect chn_a_rsc_lz uint16tofp17_Yin_prdy; +//&Connect chn_o_rsc_z uint16tofp17_Yout; +//&Connect chn_o_rsc_vz uint16tofp17_Yout_prdy; +//&Connect chn_o_rsc_lz uint16tofp17_Yout_pvld; +//////////////////////////////////////////////////// +assign info_pipe_in_pd = {lut_Y_sel_in[0],lut_X_sel_in[0],lut_Y_info_in[1:0],lut_X_info_in[1:0]}; +// need update if NVDLA_HLS_FP16TO32_LATENCY != NVDLA_HLS_FP16TO17_LATENCY +assign info_pipe_in_vld_d0 = info_pipe_in_vld; +assign info_pipe_in_rdy = info_pipe_in_rdy_d0; +assign info_pipe_in_pd_d0[5:0] = info_pipe_in_pd[5:0]; +FP_FORMAT_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.info_pipe_in_pd_d0 (info_pipe_in_pd_d0[5:0]) //|< w + ,.info_pipe_in_rdy_d1 (info_pipe_in_rdy_d1) //|< w + ,.info_pipe_in_vld_d0 (info_pipe_in_vld_d0) //|< w + ,.info_pipe_in_pd_d1 (info_pipe_in_pd_d1[5:0]) //|> w + ,.info_pipe_in_rdy_d0 (info_pipe_in_rdy_d0) //|> w + ,.info_pipe_in_vld_d1 (info_pipe_in_vld_d1) //|> w + ); +assign info_pipe_out_vld = info_pipe_in_vld_d1; +assign info_pipe_in_rdy_d1 = info_pipe_out_rdy; +assign info_pipe_out_pd[5:0] = info_pipe_in_pd_d1[5:0]; +assign {lut_Y_sel_out[0],lut_X_sel_out[0],lut_Y_info_out[1:0],lut_X_info_out[1:0]} = info_pipe_out_pd; +//NVDLA_HLS_FP16TO32_LATENCY and NVDLA_HLS_FP16TO17_LATENCY must equal +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"NVDLA_HLS_FP16TO32_LATENCY and NVDLA_HLS_FP16TO17_LATENCY must be same value") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, 1 != 1); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////// +assign vlds_out = {fp16to32_out_X0_pvld,fp16to32_out_X1_pvld,fp16to17_out_X0_pvld,uint16tofp17_Xout_pvld, + /*fp16to32_out_Y0_pvld,fp16to32_out_Y1_pvld,fp16to17_out_Y0_pvld,uint16tofp17_Yout_pvld,*/info_pipe_out_vld}; +assign fp16to32_out_X0_prdy = FMcvt_out_rdy & (&vlds_out[3:0]); +assign fp16to32_out_X1_prdy = FMcvt_out_rdy & (&{vlds_out[4],vlds_out[2:0]}); +assign fp16to17_out_X0_prdy = FMcvt_out_rdy & (&{vlds_out[4:3],vlds_out[1:0]}); +assign uint16tofp17_Xout_prdy = FMcvt_out_rdy & (&{vlds_out[4:2],vlds_out[0]}); +//assign fp16to32_out_Y0_prdy = FMcvt_out_rdy & (&{vlds_out[8:5],vlds_out[3:0]}); +//assign fp16to32_out_Y1_prdy = FMcvt_out_rdy & (&{vlds_out[8:4],vlds_out[2:0]}); +//assign fp16to17_out_Y0_prdy = FMcvt_out_rdy & (&{vlds_out[8:3],vlds_out[1:0]}); +//assign uint16tofp17_Yout_prdy = FMcvt_out_rdy & (&{vlds_out[8:2],vlds_out[ 0]}); +assign info_pipe_out_rdy = FMcvt_out_rdy & (&vlds_out[4:1]); +assign FMcvt_out_vld = &vlds_out; +//////////////////////////// +endmodule // fp_format_cvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none info_pipe_in_pd_d1[5:0] (info_pipe_in_vld_d1,info_pipe_in_rdy_d1) <= info_pipe_in_pd_d0[5:0] (info_pipe_in_vld_d0,info_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_FORMAT_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,info_pipe_in_pd_d0 + ,info_pipe_in_rdy_d1 + ,info_pipe_in_vld_d0 + ,info_pipe_in_pd_d1 + ,info_pipe_in_rdy_d0 + ,info_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [5:0] info_pipe_in_pd_d0; +input info_pipe_in_rdy_d1; +input info_pipe_in_vld_d0; +output [5:0] info_pipe_in_pd_d1; +output info_pipe_in_rdy_d0; +output info_pipe_in_vld_d1; +reg [5:0] info_pipe_in_pd_d1; +reg info_pipe_in_rdy_d0; +reg info_pipe_in_vld_d1; +reg [5:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? info_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && info_pipe_in_vld_d0)? info_pipe_in_pd_d0[5:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + info_pipe_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or info_pipe_in_rdy_d1 + or p1_pipe_data + ) begin + info_pipe_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = info_pipe_in_rdy_d1; + info_pipe_in_pd_d1[5:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (info_pipe_in_vld_d1^info_pipe_in_rdy_d1^info_pipe_in_vld_d0^info_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_3x (nvdla_core_clk, `ASSERT_RESET, (info_pipe_in_vld_d0 && !info_pipe_in_rdy_d0), (info_pipe_in_vld_d0), (info_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_FORMAT_CVT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/fp_sum_block.v b/designs/src/NVDLA/vmod/nvdla/cdp/fp_sum_block.v new file mode 100644 index 0000000..f2f15bf --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/fp_sum_block.v @@ -0,0 +1,3121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: fp_sum_block.v +module fp_sum_block ( + fp16_dout_0 //|< i + ,fp16_dout_1 //|< i + ,fp16_dout_2 //|< i + ,fp16_dout_3 //|< i + ,fp16_dout_4 //|< i + ,fp16_dout_5 //|< i + ,fp16_dout_6 //|< i + ,fp16_dout_7 //|< i + ,fp16_dout_8 //|< i + ,fp16_sum_rdy //|< i + ,fp_sq_out_vld //|< i + ,len3 //|< i + ,len5 //|< i + ,len7 //|< i + ,len9 //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,reg2dp_normalz_len //|< i + ,fp16_sum //|> o + ,fp16_sum_vld //|> o + ,fp_sq_out_rdy //|> o + ); +input [31:0] fp16_dout_0; +input [31:0] fp16_dout_1; +input [31:0] fp16_dout_2; +input [31:0] fp16_dout_3; +input [31:0] fp16_dout_4; +input [31:0] fp16_dout_5; +input [31:0] fp16_dout_6; +input [31:0] fp16_dout_7; +input [31:0] fp16_dout_8; +input fp16_sum_rdy; +input fp_sq_out_vld; +input len3; +input len5; +input len7; +input len9; +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] reg2dp_normalz_len; +output [31:0] fp16_sum; +output fp16_sum_vld; +output fp_sq_out_rdy; +reg [31:0] fp16_sum; +reg fp16_sum_vld; +wire [31:0] fp16_dout_4_in_pd; +wire [31:0] fp16_dout_4_in_pd_d0; +wire [31:0] fp16_dout_4_in_pd_d1; +wire [31:0] fp16_dout_4_in_pd_d2; +wire [31:0] fp16_dout_4_in_pd_d3; +wire [31:0] fp16_dout_4_in_pd_d4; +wire fp16_dout_4_in_rdy; +wire fp16_dout_4_in_rdy_d0; +wire fp16_dout_4_in_rdy_d1; +wire fp16_dout_4_in_rdy_d2; +wire fp16_dout_4_in_rdy_d3; +wire fp16_dout_4_in_rdy_d4; +wire fp16_dout_4_in_vld; +wire fp16_dout_4_in_vld_d0; +wire fp16_dout_4_in_vld_d1; +wire fp16_dout_4_in_vld_d2; +wire fp16_dout_4_in_vld_d3; +wire fp16_dout_4_in_vld_d4; +wire [31:0] fp16_dout_4_out_pd; +wire fp16_dout_4_out_rdy; +wire fp16_dout_4_out_vld; +wire [31:0] fp16_sum3; +wire fp16_sum35_rdy; +wire fp16_sum35_vld; +wire fp16_sum3_rdy; +wire fp16_sum3_vld; +wire fp16_sum4_rdy; +wire fp16_sum4_vld; +wire [31:0] fp16_sum5; +wire fp16_sum5_rdy; +wire fp16_sum5_vld; +wire [31:0] fp16_sum7; +wire fp16_sum7_rdy; +wire fp16_sum7_vld; +wire [31:0] fp16_sum9; +wire fp16_sum9_rdy; +wire fp16_sum9_vld; +wire [31:0] fp16_sum_0_8; +wire fp16_sum_0_8_rdy; +wire fp16_sum_0_8_vld; +wire [31:0] fp16_sum_1_7; +wire fp16_sum_1_7_rdy; +wire fp16_sum_1_7_vld; +wire [31:0] fp16_sum_2_6; +wire fp16_sum_2_6_rdy; +wire fp16_sum_2_6_vld; +wire [31:0] fp16_sum_3_5; +wire fp16_sum_3_5_rdy; +wire fp16_sum_3_5_vld; +wire fp16_sum_stage0_rdy; +wire fp16_sum_stage0_vld; +wire fp16_sum_stage1_rdy; +wire fp16_sum_stage1_vld; +wire fp16_sum_stage2_rdy; +wire fp16_sum_stage2_vld; +wire fp16_sum_stage3_rdy; +wire fp16_sum_stage3_vld; +wire [8:0] fp_sq_vld; +wire [8:0] fp_sum_in_rdy; +wire [95:0] stage1_pipe_in_pd; +wire [95:0] stage1_pipe_in_pd_d0; +wire [95:0] stage1_pipe_in_pd_d1; +wire [95:0] stage1_pipe_in_pd_d2; +wire [95:0] stage1_pipe_in_pd_d3; +wire [95:0] stage1_pipe_in_pd_d4; +wire stage1_pipe_in_rdy; +wire stage1_pipe_in_rdy_d0; +wire stage1_pipe_in_rdy_d1; +wire stage1_pipe_in_rdy_d2; +wire stage1_pipe_in_rdy_d3; +wire stage1_pipe_in_rdy_d4; +wire stage1_pipe_in_vld; +wire stage1_pipe_in_vld_d0; +wire stage1_pipe_in_vld_d1; +wire stage1_pipe_in_vld_d2; +wire stage1_pipe_in_vld_d3; +wire stage1_pipe_in_vld_d4; +wire [95:0] stage1_pipe_out_pd; +wire stage1_pipe_out_rdy; +wire stage1_pipe_out_vld; +wire [63:0] stage2_pipe_in_pd; +wire [63:0] stage2_pipe_in_pd_d0; +wire [63:0] stage2_pipe_in_pd_d1; +wire [63:0] stage2_pipe_in_pd_d2; +wire [63:0] stage2_pipe_in_pd_d3; +wire [63:0] stage2_pipe_in_pd_d4; +wire stage2_pipe_in_rdy; +wire stage2_pipe_in_rdy_d0; +wire stage2_pipe_in_rdy_d1; +wire stage2_pipe_in_rdy_d2; +wire stage2_pipe_in_rdy_d3; +wire stage2_pipe_in_rdy_d4; +wire stage2_pipe_in_vld; +wire stage2_pipe_in_vld_d0; +wire stage2_pipe_in_vld_d1; +wire stage2_pipe_in_vld_d2; +wire stage2_pipe_in_vld_d3; +wire stage2_pipe_in_vld_d4; +wire [63:0] stage2_pipe_out_pd; +wire stage2_pipe_out_rdy; +wire stage2_pipe_out_vld; +wire stage2_sum26_rdy; +wire stage2_sum26_vld; +wire stage2_sum3_rdy; +wire stage2_sum3_vld; +wire [31:0] stage3_pipe_in_pd; +wire [31:0] stage3_pipe_in_pd_d0; +wire [31:0] stage3_pipe_in_pd_d1; +wire [31:0] stage3_pipe_in_pd_d2; +wire [31:0] stage3_pipe_in_pd_d3; +wire [31:0] stage3_pipe_in_pd_d4; +wire stage3_pipe_in_rdy; +wire stage3_pipe_in_rdy_d0; +wire stage3_pipe_in_rdy_d1; +wire stage3_pipe_in_rdy_d2; +wire stage3_pipe_in_rdy_d3; +wire stage3_pipe_in_rdy_d4; +wire stage3_pipe_in_vld; +wire stage3_pipe_in_vld_d0; +wire stage3_pipe_in_vld_d1; +wire stage3_pipe_in_vld_d2; +wire stage3_pipe_in_vld_d3; +wire stage3_pipe_in_vld_d4; +wire [31:0] stage3_pipe_out_pd; +wire stage3_pipe_out_rdy; +wire stage3_pipe_out_vld; +wire stage3_sum17_rdy; +wire stage3_sum17_vld; +wire stage3_sum5_rdy; +wire stage3_sum5_vld; +wire stage4_sum08_rdy; +wire stage4_sum08_vld; +wire stage4_sum7_rdy; +wire stage4_sum7_vld; +/////////////////////////////////// +//assign len3_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3); +//assign len5_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5); +//assign len7_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7); +//assign len9_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9); +/////////////////////////////////// +assign fp_sq_out_rdy = &fp_sum_in_rdy[8:0]; +assign fp_sq_vld[0] = (len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:1]) ) : 1'b0; +assign fp_sq_vld[1] = (len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:2]) & ( fp_sum_in_rdy[ 0])) : 1'b0; +assign fp_sq_vld[2] = (len5 | len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:3]) & (&fp_sum_in_rdy[1:0])) : 1'b0; +assign fp_sq_vld[3] = (fp_sq_out_vld & (&fp_sum_in_rdy[8:4]) & (&fp_sum_in_rdy[2:0])); +assign fp_sq_vld[4] = (fp_sq_out_vld & (&fp_sum_in_rdy[8:5]) & (&fp_sum_in_rdy[3:0])); +assign fp_sq_vld[5] = (fp_sq_out_vld & (&fp_sum_in_rdy[8:6]) & (&fp_sum_in_rdy[4:0])); +assign fp_sq_vld[6] = (len5 | len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:7]) & (&fp_sum_in_rdy[5:0])) : 1'b0; +assign fp_sq_vld[7] = (len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8 ]) & (&fp_sum_in_rdy[6:0])) : 1'b0; +assign fp_sq_vld[8] = (len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[7:0])) : 1'b0; +/////////////////////////////////// +HLS_fp32_add u_HLS_fp32_add_3_5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_3[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[3]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[3]) //|> w + ,.chn_b_rsc_z (fp16_dout_5[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[5]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[5]) //|> w + ,.chn_o_rsc_z (fp16_sum_3_5[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_3_5_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_3_5_vld) //|> w + ); +HLS_fp32_add u_HLS_fp32_add_2_6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_2[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[2]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[2]) //|> w + ,.chn_b_rsc_z (fp16_dout_6[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[6]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[6]) //|> w + ,.chn_o_rsc_z (fp16_sum_2_6[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_2_6_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_2_6_vld) //|> w + ); +HLS_fp32_add u_HLS_fp32_add_1_7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_1[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[1]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[1]) //|> w + ,.chn_b_rsc_z (fp16_dout_7[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[7]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[7]) //|> w + ,.chn_o_rsc_z (fp16_sum_1_7[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_1_7_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_1_7_vld) //|> w + ); +HLS_fp32_add u_HLS_fp32_add_0_8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_0[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[0]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[0]) //|> w + ,.chn_b_rsc_z (fp16_dout_8[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[8]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[8]) //|> w + ,.chn_o_rsc_z (fp16_sum_0_8[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_0_8_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_0_8_vld) //|> w + ); +//assign fp16_sum_3_5_rdy = fp16_sum_stage0_rdy & fp16_sum_2_6_vld & fp16_sum_1_7_vld & fp16_sum_0_8_vld & fp16_dout_4_out_vld; +//assign fp16_sum_2_6_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & fp16_sum_1_7_vld & fp16_sum_0_8_vld & fp16_dout_4_out_vld; +//assign fp16_sum_1_7_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & fp16_sum_2_6_vld & fp16_sum_0_8_vld & fp16_dout_4_out_vld; +//assign fp16_sum_0_8_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & fp16_sum_2_6_vld & fp16_sum_1_7_vld & fp16_dout_4_out_vld; +assign fp16_sum_3_5_rdy = fp16_sum_stage0_rdy & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +assign fp16_sum_2_6_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +assign fp16_sum_1_7_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +assign fp16_sum_0_8_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & fp16_dout_4_out_vld; +//fp16_dout_4 sync process +assign fp16_dout_4_in_pd = fp16_dout_4[31:0]; +assign fp16_dout_4_in_vld = fp_sq_vld[4]; +assign fp_sum_in_rdy[4] = fp16_dout_4_in_rdy; +assign fp16_dout_4_in_vld_d0 = fp16_dout_4_in_vld; +assign fp16_dout_4_in_rdy = fp16_dout_4_in_rdy_d0; +assign fp16_dout_4_in_pd_d0[31:0] = fp16_dout_4_in_pd[31:0]; +FP_SUM_BLOCK_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d0 (fp16_dout_4_in_pd_d0[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d1 (fp16_dout_4_in_rdy_d1) //|< w + ,.fp16_dout_4_in_vld_d0 (fp16_dout_4_in_vld_d0) //|< w + ,.fp16_dout_4_in_pd_d1 (fp16_dout_4_in_pd_d1[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d0 (fp16_dout_4_in_rdy_d0) //|> w + ,.fp16_dout_4_in_vld_d1 (fp16_dout_4_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d1 (fp16_dout_4_in_pd_d1[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d2 (fp16_dout_4_in_rdy_d2) //|< w + ,.fp16_dout_4_in_vld_d1 (fp16_dout_4_in_vld_d1) //|< w + ,.fp16_dout_4_in_pd_d2 (fp16_dout_4_in_pd_d2[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d1 (fp16_dout_4_in_rdy_d1) //|> w + ,.fp16_dout_4_in_vld_d2 (fp16_dout_4_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d2 (fp16_dout_4_in_pd_d2[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d3 (fp16_dout_4_in_rdy_d3) //|< w + ,.fp16_dout_4_in_vld_d2 (fp16_dout_4_in_vld_d2) //|< w + ,.fp16_dout_4_in_pd_d3 (fp16_dout_4_in_pd_d3[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d2 (fp16_dout_4_in_rdy_d2) //|> w + ,.fp16_dout_4_in_vld_d3 (fp16_dout_4_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d3 (fp16_dout_4_in_pd_d3[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d4 (fp16_dout_4_in_rdy_d4) //|< w + ,.fp16_dout_4_in_vld_d3 (fp16_dout_4_in_vld_d3) //|< w + ,.fp16_dout_4_in_pd_d4 (fp16_dout_4_in_pd_d4[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d3 (fp16_dout_4_in_rdy_d3) //|> w + ,.fp16_dout_4_in_vld_d4 (fp16_dout_4_in_vld_d4) //|> w + ); +assign fp16_dout_4_out_vld = fp16_dout_4_in_vld_d4; +assign fp16_dout_4_in_rdy_d4 = fp16_dout_4_out_rdy; +assign fp16_dout_4_out_pd[31:0] = fp16_dout_4_in_pd_d4[31:0]; +assign fp16_dout_4_out_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1); +//sum stage0 output valid +assign fp16_sum_stage0_vld = fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +/////////////////////////////////// +assign fp16_sum_stage0_rdy = len3 ? (fp16_sum35_rdy & fp16_sum4_rdy) : (fp16_sum35_rdy & fp16_sum4_rdy & stage1_pipe_in_rdy); +assign fp16_sum35_vld = len3 ? (fp16_sum_stage0_vld & fp16_sum4_rdy) : (fp16_sum_stage0_vld & fp16_sum4_rdy & stage1_pipe_in_rdy); +assign fp16_sum4_vld = len3 ? (fp16_sum_stage0_vld & fp16_sum35_rdy) : (fp16_sum_stage0_vld & fp16_sum35_rdy & stage1_pipe_in_rdy); +assign stage1_pipe_in_vld = (len5 | len7 | len9)? (fp16_sum_stage0_vld & fp16_sum35_rdy & fp16_sum4_rdy) : 1'b0; +HLS_fp32_add u_HLS_fp32_add_sum3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum_3_5[31:0]) //|< w + ,.chn_a_rsc_vz (fp16_sum35_vld) //|< w + ,.chn_a_rsc_lz (fp16_sum35_rdy) //|> w + ,.chn_b_rsc_z (fp16_dout_4_out_pd[31:0]) //|< w + ,.chn_b_rsc_vz (fp16_sum4_vld) //|< w + ,.chn_b_rsc_lz (fp16_sum4_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum3[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum3_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum3_vld) //|> w + ); +assign fp16_sum3_rdy = len3 ? fp16_sum_rdy : (fp16_sum_stage1_rdy & stage1_pipe_out_vld); +assign stage1_pipe_out_rdy = len3 ? 1'b1 : (fp16_sum_stage1_rdy & fp16_sum3_vld); +assign stage1_pipe_in_pd = {fp16_sum_2_6,fp16_sum_1_7,fp16_sum_0_8}; +assign stage1_pipe_in_vld_d0 = stage1_pipe_in_vld; +assign stage1_pipe_in_rdy = stage1_pipe_in_rdy_d0; +assign stage1_pipe_in_pd_d0[95:0] = stage1_pipe_in_pd[95:0]; +FP_SUM_BLOCK_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d0 (stage1_pipe_in_pd_d0[95:0]) //|< w + ,.stage1_pipe_in_rdy_d1 (stage1_pipe_in_rdy_d1) //|< w + ,.stage1_pipe_in_vld_d0 (stage1_pipe_in_vld_d0) //|< w + ,.stage1_pipe_in_pd_d1 (stage1_pipe_in_pd_d1[95:0]) //|> w + ,.stage1_pipe_in_rdy_d0 (stage1_pipe_in_rdy_d0) //|> w + ,.stage1_pipe_in_vld_d1 (stage1_pipe_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d1 (stage1_pipe_in_pd_d1[95:0]) //|< w + ,.stage1_pipe_in_rdy_d2 (stage1_pipe_in_rdy_d2) //|< w + ,.stage1_pipe_in_vld_d1 (stage1_pipe_in_vld_d1) //|< w + ,.stage1_pipe_in_pd_d2 (stage1_pipe_in_pd_d2[95:0]) //|> w + ,.stage1_pipe_in_rdy_d1 (stage1_pipe_in_rdy_d1) //|> w + ,.stage1_pipe_in_vld_d2 (stage1_pipe_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d2 (stage1_pipe_in_pd_d2[95:0]) //|< w + ,.stage1_pipe_in_rdy_d3 (stage1_pipe_in_rdy_d3) //|< w + ,.stage1_pipe_in_vld_d2 (stage1_pipe_in_vld_d2) //|< w + ,.stage1_pipe_in_pd_d3 (stage1_pipe_in_pd_d3[95:0]) //|> w + ,.stage1_pipe_in_rdy_d2 (stage1_pipe_in_rdy_d2) //|> w + ,.stage1_pipe_in_vld_d3 (stage1_pipe_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p8 pipe_p8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d3 (stage1_pipe_in_pd_d3[95:0]) //|< w + ,.stage1_pipe_in_rdy_d4 (stage1_pipe_in_rdy_d4) //|< w + ,.stage1_pipe_in_vld_d3 (stage1_pipe_in_vld_d3) //|< w + ,.stage1_pipe_in_pd_d4 (stage1_pipe_in_pd_d4[95:0]) //|> w + ,.stage1_pipe_in_rdy_d3 (stage1_pipe_in_rdy_d3) //|> w + ,.stage1_pipe_in_vld_d4 (stage1_pipe_in_vld_d4) //|> w + ); +assign stage1_pipe_out_vld = stage1_pipe_in_vld_d4; +assign stage1_pipe_in_rdy_d4 = stage1_pipe_out_rdy; +assign stage1_pipe_out_pd[95:0] = stage1_pipe_in_pd_d4[95:0]; +assign fp16_sum_stage1_vld = len3 ? 1'b0 : (fp16_sum3_vld & stage1_pipe_out_vld); +////////////////////////////////////// +assign fp16_sum_stage1_rdy = (len7 | len9) ? (stage2_sum3_rdy & stage2_sum26_rdy & stage2_pipe_in_rdy) : (stage2_sum3_rdy & stage2_sum26_rdy); +assign stage2_sum3_vld = (len7 | len9) ? (fp16_sum_stage1_vld & stage2_sum26_rdy & stage2_pipe_in_rdy) : (fp16_sum_stage1_vld & stage2_sum26_rdy); +assign stage2_sum26_vld = (len7 | len9) ? (fp16_sum_stage1_vld & stage2_sum3_rdy & stage2_pipe_in_rdy) : (fp16_sum_stage1_vld & stage2_sum3_rdy); +assign stage2_pipe_in_vld = (len7 | len9)? (fp16_sum_stage1_vld & stage2_sum26_rdy & stage2_sum3_rdy) : 1'b0; +HLS_fp32_add u_HLS_fp32_add_sum5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum3[31:0]) //|< w + ,.chn_a_rsc_vz (stage2_sum3_vld) //|< w + ,.chn_a_rsc_lz (stage2_sum3_rdy) //|> w + ,.chn_b_rsc_z (stage1_pipe_out_pd[95:64]) //|< w + ,.chn_b_rsc_vz (stage2_sum26_vld) //|< w + ,.chn_b_rsc_lz (stage2_sum26_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum5[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum5_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum5_vld) //|> w + ); +//fp16_sum_2_6 ; +assign fp16_sum5_rdy = len5 ? fp16_sum_rdy : (fp16_sum_stage2_rdy & stage2_pipe_out_vld); +assign stage2_pipe_out_rdy = (len7 | len9) ? (fp16_sum_stage2_rdy & fp16_sum5_vld) : 1'b1; +assign stage2_pipe_in_pd = stage1_pipe_out_pd[63:0];//{fp16_sum_1_7,fp16_sum_0_8}; +assign stage2_pipe_in_vld_d0 = stage2_pipe_in_vld; +assign stage2_pipe_in_rdy = stage2_pipe_in_rdy_d0; +assign stage2_pipe_in_pd_d0[63:0] = stage2_pipe_in_pd[63:0]; +FP_SUM_BLOCK_pipe_p9 pipe_p9 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d0 (stage2_pipe_in_pd_d0[63:0]) //|< w + ,.stage2_pipe_in_rdy_d1 (stage2_pipe_in_rdy_d1) //|< w + ,.stage2_pipe_in_vld_d0 (stage2_pipe_in_vld_d0) //|< w + ,.stage2_pipe_in_pd_d1 (stage2_pipe_in_pd_d1[63:0]) //|> w + ,.stage2_pipe_in_rdy_d0 (stage2_pipe_in_rdy_d0) //|> w + ,.stage2_pipe_in_vld_d1 (stage2_pipe_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p10 pipe_p10 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d1 (stage2_pipe_in_pd_d1[63:0]) //|< w + ,.stage2_pipe_in_rdy_d2 (stage2_pipe_in_rdy_d2) //|< w + ,.stage2_pipe_in_vld_d1 (stage2_pipe_in_vld_d1) //|< w + ,.stage2_pipe_in_pd_d2 (stage2_pipe_in_pd_d2[63:0]) //|> w + ,.stage2_pipe_in_rdy_d1 (stage2_pipe_in_rdy_d1) //|> w + ,.stage2_pipe_in_vld_d2 (stage2_pipe_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p11 pipe_p11 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d2 (stage2_pipe_in_pd_d2[63:0]) //|< w + ,.stage2_pipe_in_rdy_d3 (stage2_pipe_in_rdy_d3) //|< w + ,.stage2_pipe_in_vld_d2 (stage2_pipe_in_vld_d2) //|< w + ,.stage2_pipe_in_pd_d3 (stage2_pipe_in_pd_d3[63:0]) //|> w + ,.stage2_pipe_in_rdy_d2 (stage2_pipe_in_rdy_d2) //|> w + ,.stage2_pipe_in_vld_d3 (stage2_pipe_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p12 pipe_p12 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d3 (stage2_pipe_in_pd_d3[63:0]) //|< w + ,.stage2_pipe_in_rdy_d4 (stage2_pipe_in_rdy_d4) //|< w + ,.stage2_pipe_in_vld_d3 (stage2_pipe_in_vld_d3) //|< w + ,.stage2_pipe_in_pd_d4 (stage2_pipe_in_pd_d4[63:0]) //|> w + ,.stage2_pipe_in_rdy_d3 (stage2_pipe_in_rdy_d3) //|> w + ,.stage2_pipe_in_vld_d4 (stage2_pipe_in_vld_d4) //|> w + ); +assign stage2_pipe_out_vld = stage2_pipe_in_vld_d4; +assign stage2_pipe_in_rdy_d4 = stage2_pipe_out_rdy; +assign stage2_pipe_out_pd[63:0] = stage2_pipe_in_pd_d4[63:0]; +assign fp16_sum_stage2_vld = (len3 | len5) ? 1'b0 : (fp16_sum5_vld & stage2_pipe_out_vld); +////////////////////////////////////// +assign fp16_sum_stage2_rdy = len9 ? (stage3_sum5_rdy & stage3_sum17_rdy & stage3_pipe_in_rdy) : (stage3_sum5_rdy & stage3_sum17_rdy); +assign stage3_sum5_vld = len9 ? (fp16_sum_stage2_vld & stage3_sum17_rdy & stage3_pipe_in_rdy) : (fp16_sum_stage2_vld & stage3_sum17_rdy); +assign stage3_sum17_vld = len9 ? (fp16_sum_stage2_vld & stage3_sum5_rdy & stage3_pipe_in_rdy) : (fp16_sum_stage2_vld & stage3_sum5_rdy); +assign stage3_pipe_in_vld = len9 ? (fp16_sum_stage2_vld & stage3_sum17_rdy & stage3_sum5_rdy) : 1'b0; +HLS_fp32_add u_HLS_fp32_add_sum7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum5[31:0]) //|< w + ,.chn_a_rsc_vz (stage3_sum5_vld) //|< w + ,.chn_a_rsc_lz (stage3_sum5_rdy) //|> w + ,.chn_b_rsc_z (stage2_pipe_out_pd[63:32]) //|< w + ,.chn_b_rsc_vz (stage3_sum17_vld) //|< w + ,.chn_b_rsc_lz (stage3_sum17_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum7[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum7_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum7_vld) //|> w + ); +//fp16_sum_1_7 ; +assign fp16_sum7_rdy = len7 ? fp16_sum_rdy : (fp16_sum_stage3_rdy & stage3_pipe_out_vld); +assign stage3_pipe_out_rdy = len9 ? (fp16_sum_stage3_rdy & fp16_sum7_vld) : 1'b1; +assign stage3_pipe_in_pd = stage2_pipe_out_pd[31:0]; +assign stage3_pipe_in_vld_d0 = stage3_pipe_in_vld; +assign stage3_pipe_in_rdy = stage3_pipe_in_rdy_d0; +assign stage3_pipe_in_pd_d0[31:0] = stage3_pipe_in_pd[31:0]; +FP_SUM_BLOCK_pipe_p13 pipe_p13 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d0 (stage3_pipe_in_pd_d0[31:0]) //|< w + ,.stage3_pipe_in_rdy_d1 (stage3_pipe_in_rdy_d1) //|< w + ,.stage3_pipe_in_vld_d0 (stage3_pipe_in_vld_d0) //|< w + ,.stage3_pipe_in_pd_d1 (stage3_pipe_in_pd_d1[31:0]) //|> w + ,.stage3_pipe_in_rdy_d0 (stage3_pipe_in_rdy_d0) //|> w + ,.stage3_pipe_in_vld_d1 (stage3_pipe_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p14 pipe_p14 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d1 (stage3_pipe_in_pd_d1[31:0]) //|< w + ,.stage3_pipe_in_rdy_d2 (stage3_pipe_in_rdy_d2) //|< w + ,.stage3_pipe_in_vld_d1 (stage3_pipe_in_vld_d1) //|< w + ,.stage3_pipe_in_pd_d2 (stage3_pipe_in_pd_d2[31:0]) //|> w + ,.stage3_pipe_in_rdy_d1 (stage3_pipe_in_rdy_d1) //|> w + ,.stage3_pipe_in_vld_d2 (stage3_pipe_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p15 pipe_p15 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d2 (stage3_pipe_in_pd_d2[31:0]) //|< w + ,.stage3_pipe_in_rdy_d3 (stage3_pipe_in_rdy_d3) //|< w + ,.stage3_pipe_in_vld_d2 (stage3_pipe_in_vld_d2) //|< w + ,.stage3_pipe_in_pd_d3 (stage3_pipe_in_pd_d3[31:0]) //|> w + ,.stage3_pipe_in_rdy_d2 (stage3_pipe_in_rdy_d2) //|> w + ,.stage3_pipe_in_vld_d3 (stage3_pipe_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p16 pipe_p16 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d3 (stage3_pipe_in_pd_d3[31:0]) //|< w + ,.stage3_pipe_in_rdy_d4 (stage3_pipe_in_rdy_d4) //|< w + ,.stage3_pipe_in_vld_d3 (stage3_pipe_in_vld_d3) //|< w + ,.stage3_pipe_in_pd_d4 (stage3_pipe_in_pd_d4[31:0]) //|> w + ,.stage3_pipe_in_rdy_d3 (stage3_pipe_in_rdy_d3) //|> w + ,.stage3_pipe_in_vld_d4 (stage3_pipe_in_vld_d4) //|> w + ); +assign stage3_pipe_out_vld = stage3_pipe_in_vld_d4; +assign stage3_pipe_in_rdy_d4 = stage3_pipe_out_rdy; +assign stage3_pipe_out_pd[31:0] = stage3_pipe_in_pd_d4[31:0]; +assign fp16_sum_stage3_vld = (len3 | len5 | len7) ? 1'b0 : (fp16_sum7_vld & stage3_pipe_out_vld); +////////////////////////////////////// +assign fp16_sum_stage3_rdy = stage4_sum7_rdy & stage4_sum08_rdy; +assign stage4_sum7_vld = fp16_sum_stage3_vld & stage4_sum08_rdy; +assign stage4_sum08_vld = fp16_sum_stage3_vld & stage4_sum7_rdy; +HLS_fp32_add u_HLS_fp32_add_sum9 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum7[31:0]) //|< w + ,.chn_a_rsc_vz (stage4_sum7_vld) //|< w + ,.chn_a_rsc_lz (stage4_sum7_rdy) //|> w + ,.chn_b_rsc_z (stage3_pipe_out_pd[31:0]) //|< w + ,.chn_b_rsc_vz (stage4_sum08_vld) //|< w + ,.chn_b_rsc_lz (stage4_sum08_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum9[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum9_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum9_vld) //|> w + ); +//fp16_sum_0_8 ; +assign fp16_sum9_rdy = fp16_sum_rdy; +////////////////////////////////////// +always @( + reg2dp_normalz_len + or fp16_sum3 + or fp16_sum3_vld + or fp16_sum5 + or fp16_sum5_vld + or fp16_sum7 + or fp16_sum7_vld + or fp16_sum9 + or fp16_sum9_vld + ) begin + case(reg2dp_normalz_len[1:0]) + 2'h0 : begin + fp16_sum = fp16_sum3; + fp16_sum_vld = fp16_sum3_vld; + end + 2'h1 : begin + fp16_sum = fp16_sum5; + fp16_sum_vld = fp16_sum5_vld; + end + 2'h2 : begin + fp16_sum = fp16_sum7; + fp16_sum_vld = fp16_sum7_vld; + end + default: begin +//NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9: begin + fp16_sum = fp16_sum9; + fp16_sum_vld = fp16_sum9_vld; + end + endcase +end +//fp16_sum_rdy +endmodule // fp_sum_block +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d1[31:0] (fp16_dout_4_in_vld_d1,fp16_dout_4_in_rdy_d1) <= fp16_dout_4_in_pd_d0[31:0] (fp16_dout_4_in_vld_d0,fp16_dout_4_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d0 + ,fp16_dout_4_in_rdy_d1 + ,fp16_dout_4_in_vld_d0 + ,fp16_dout_4_in_pd_d1 + ,fp16_dout_4_in_rdy_d0 + ,fp16_dout_4_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d0; +input fp16_dout_4_in_rdy_d1; +input fp16_dout_4_in_vld_d0; +output [31:0] fp16_dout_4_in_pd_d1; +output fp16_dout_4_in_rdy_d0; +output fp16_dout_4_in_vld_d1; +reg [31:0] fp16_dout_4_in_pd_d1; +reg fp16_dout_4_in_rdy_d0; +reg fp16_dout_4_in_vld_d1; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? fp16_dout_4_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && fp16_dout_4_in_vld_d0)? fp16_dout_4_in_pd_d0[31:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or fp16_dout_4_in_rdy_d1 + or p1_pipe_data + ) begin + fp16_dout_4_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = fp16_dout_4_in_rdy_d1; + fp16_dout_4_in_pd_d1[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d1^fp16_dout_4_in_rdy_d1^fp16_dout_4_in_vld_d0^fp16_dout_4_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d0 && !fp16_dout_4_in_rdy_d0), (fp16_dout_4_in_vld_d0), (fp16_dout_4_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d2[31:0] (fp16_dout_4_in_vld_d2,fp16_dout_4_in_rdy_d2) <= fp16_dout_4_in_pd_d1[31:0] (fp16_dout_4_in_vld_d1,fp16_dout_4_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d1 + ,fp16_dout_4_in_rdy_d2 + ,fp16_dout_4_in_vld_d1 + ,fp16_dout_4_in_pd_d2 + ,fp16_dout_4_in_rdy_d1 + ,fp16_dout_4_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d1; +input fp16_dout_4_in_rdy_d2; +input fp16_dout_4_in_vld_d1; +output [31:0] fp16_dout_4_in_pd_d2; +output fp16_dout_4_in_rdy_d1; +output fp16_dout_4_in_vld_d2; +reg [31:0] fp16_dout_4_in_pd_d2; +reg fp16_dout_4_in_rdy_d1; +reg fp16_dout_4_in_vld_d2; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? fp16_dout_4_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && fp16_dout_4_in_vld_d1)? fp16_dout_4_in_pd_d1[31:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d1 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or fp16_dout_4_in_rdy_d2 + or p2_pipe_data + ) begin + fp16_dout_4_in_vld_d2 = p2_pipe_valid; + p2_pipe_ready = fp16_dout_4_in_rdy_d2; + fp16_dout_4_in_pd_d2[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d2^fp16_dout_4_in_rdy_d2^fp16_dout_4_in_vld_d1^fp16_dout_4_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d1 && !fp16_dout_4_in_rdy_d1), (fp16_dout_4_in_vld_d1), (fp16_dout_4_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d3[31:0] (fp16_dout_4_in_vld_d3,fp16_dout_4_in_rdy_d3) <= fp16_dout_4_in_pd_d2[31:0] (fp16_dout_4_in_vld_d2,fp16_dout_4_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d2 + ,fp16_dout_4_in_rdy_d3 + ,fp16_dout_4_in_vld_d2 + ,fp16_dout_4_in_pd_d3 + ,fp16_dout_4_in_rdy_d2 + ,fp16_dout_4_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d2; +input fp16_dout_4_in_rdy_d3; +input fp16_dout_4_in_vld_d2; +output [31:0] fp16_dout_4_in_pd_d3; +output fp16_dout_4_in_rdy_d2; +output fp16_dout_4_in_vld_d3; +reg [31:0] fp16_dout_4_in_pd_d3; +reg fp16_dout_4_in_rdy_d2; +reg fp16_dout_4_in_vld_d3; +reg [31:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? fp16_dout_4_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && fp16_dout_4_in_vld_d2)? fp16_dout_4_in_pd_d2[31:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d2 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or fp16_dout_4_in_rdy_d3 + or p3_pipe_data + ) begin + fp16_dout_4_in_vld_d3 = p3_pipe_valid; + p3_pipe_ready = fp16_dout_4_in_rdy_d3; + fp16_dout_4_in_pd_d3[31:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d3^fp16_dout_4_in_rdy_d3^fp16_dout_4_in_vld_d2^fp16_dout_4_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d2 && !fp16_dout_4_in_rdy_d2), (fp16_dout_4_in_vld_d2), (fp16_dout_4_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d4[31:0] (fp16_dout_4_in_vld_d4,fp16_dout_4_in_rdy_d4) <= fp16_dout_4_in_pd_d3[31:0] (fp16_dout_4_in_vld_d3,fp16_dout_4_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d3 + ,fp16_dout_4_in_rdy_d4 + ,fp16_dout_4_in_vld_d3 + ,fp16_dout_4_in_pd_d4 + ,fp16_dout_4_in_rdy_d3 + ,fp16_dout_4_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d3; +input fp16_dout_4_in_rdy_d4; +input fp16_dout_4_in_vld_d3; +output [31:0] fp16_dout_4_in_pd_d4; +output fp16_dout_4_in_rdy_d3; +output fp16_dout_4_in_vld_d4; +reg [31:0] fp16_dout_4_in_pd_d4; +reg fp16_dout_4_in_rdy_d3; +reg fp16_dout_4_in_vld_d4; +reg [31:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? fp16_dout_4_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && fp16_dout_4_in_vld_d3)? fp16_dout_4_in_pd_d3[31:0] : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d3 = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or fp16_dout_4_in_rdy_d4 + or p4_pipe_data + ) begin + fp16_dout_4_in_vld_d4 = p4_pipe_valid; + p4_pipe_ready = fp16_dout_4_in_rdy_d4; + fp16_dout_4_in_pd_d4[31:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d4^fp16_dout_4_in_rdy_d4^fp16_dout_4_in_vld_d3^fp16_dout_4_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d3 && !fp16_dout_4_in_rdy_d3), (fp16_dout_4_in_vld_d3), (fp16_dout_4_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d1[95:0] (stage1_pipe_in_vld_d1,stage1_pipe_in_rdy_d1) <= stage1_pipe_in_pd_d0[95:0] (stage1_pipe_in_vld_d0,stage1_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d0 + ,stage1_pipe_in_rdy_d1 + ,stage1_pipe_in_vld_d0 + ,stage1_pipe_in_pd_d1 + ,stage1_pipe_in_rdy_d0 + ,stage1_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d0; +input stage1_pipe_in_rdy_d1; +input stage1_pipe_in_vld_d0; +output [95:0] stage1_pipe_in_pd_d1; +output stage1_pipe_in_rdy_d0; +output stage1_pipe_in_vld_d1; +reg [95:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d1; +reg stage1_pipe_in_rdy_d0; +reg stage1_pipe_in_vld_d1; +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? stage1_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && stage1_pipe_in_vld_d0)? stage1_pipe_in_pd_d0[95:0] : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d0 = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or stage1_pipe_in_rdy_d1 + or p5_pipe_data + ) begin + stage1_pipe_in_vld_d1 = p5_pipe_valid; + p5_pipe_ready = stage1_pipe_in_rdy_d1; + stage1_pipe_in_pd_d1[95:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d1^stage1_pipe_in_rdy_d1^stage1_pipe_in_vld_d0^stage1_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d0 && !stage1_pipe_in_rdy_d0), (stage1_pipe_in_vld_d0), (stage1_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d2[95:0] (stage1_pipe_in_vld_d2,stage1_pipe_in_rdy_d2) <= stage1_pipe_in_pd_d1[95:0] (stage1_pipe_in_vld_d1,stage1_pipe_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d1 + ,stage1_pipe_in_rdy_d2 + ,stage1_pipe_in_vld_d1 + ,stage1_pipe_in_pd_d2 + ,stage1_pipe_in_rdy_d1 + ,stage1_pipe_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d1; +input stage1_pipe_in_rdy_d2; +input stage1_pipe_in_vld_d1; +output [95:0] stage1_pipe_in_pd_d2; +output stage1_pipe_in_rdy_d1; +output stage1_pipe_in_vld_d2; +reg [95:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d2; +reg stage1_pipe_in_rdy_d1; +reg stage1_pipe_in_vld_d2; +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? stage1_pipe_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && stage1_pipe_in_vld_d1)? stage1_pipe_in_pd_d1[95:0] : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d1 = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or stage1_pipe_in_rdy_d2 + or p6_pipe_data + ) begin + stage1_pipe_in_vld_d2 = p6_pipe_valid; + p6_pipe_ready = stage1_pipe_in_rdy_d2; + stage1_pipe_in_pd_d2[95:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d2^stage1_pipe_in_rdy_d2^stage1_pipe_in_vld_d1^stage1_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d1 && !stage1_pipe_in_rdy_d1), (stage1_pipe_in_vld_d1), (stage1_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d3[95:0] (stage1_pipe_in_vld_d3,stage1_pipe_in_rdy_d3) <= stage1_pipe_in_pd_d2[95:0] (stage1_pipe_in_vld_d2,stage1_pipe_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d2 + ,stage1_pipe_in_rdy_d3 + ,stage1_pipe_in_vld_d2 + ,stage1_pipe_in_pd_d3 + ,stage1_pipe_in_rdy_d2 + ,stage1_pipe_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d2; +input stage1_pipe_in_rdy_d3; +input stage1_pipe_in_vld_d2; +output [95:0] stage1_pipe_in_pd_d3; +output stage1_pipe_in_rdy_d2; +output stage1_pipe_in_vld_d3; +reg [95:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d3; +reg stage1_pipe_in_rdy_d2; +reg stage1_pipe_in_vld_d3; +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? stage1_pipe_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && stage1_pipe_in_vld_d2)? stage1_pipe_in_pd_d2[95:0] : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d2 = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or stage1_pipe_in_rdy_d3 + or p7_pipe_data + ) begin + stage1_pipe_in_vld_d3 = p7_pipe_valid; + p7_pipe_ready = stage1_pipe_in_rdy_d3; + stage1_pipe_in_pd_d3[95:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d3^stage1_pipe_in_rdy_d3^stage1_pipe_in_vld_d2^stage1_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d2 && !stage1_pipe_in_rdy_d2), (stage1_pipe_in_vld_d2), (stage1_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p7 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d4[95:0] (stage1_pipe_in_vld_d4,stage1_pipe_in_rdy_d4) <= stage1_pipe_in_pd_d3[95:0] (stage1_pipe_in_vld_d3,stage1_pipe_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d3 + ,stage1_pipe_in_rdy_d4 + ,stage1_pipe_in_vld_d3 + ,stage1_pipe_in_pd_d4 + ,stage1_pipe_in_rdy_d3 + ,stage1_pipe_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d3; +input stage1_pipe_in_rdy_d4; +input stage1_pipe_in_vld_d3; +output [95:0] stage1_pipe_in_pd_d4; +output stage1_pipe_in_rdy_d3; +output stage1_pipe_in_vld_d4; +reg [95:0] p8_pipe_data; +reg p8_pipe_ready; +reg p8_pipe_ready_bc; +reg p8_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d4; +reg stage1_pipe_in_rdy_d3; +reg stage1_pipe_in_vld_d4; +//## pipe (8) valid-ready-bubble-collapse +always @( + p8_pipe_ready + or p8_pipe_valid + ) begin + p8_pipe_ready_bc = p8_pipe_ready || !p8_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_pipe_valid <= 1'b0; + end else begin + p8_pipe_valid <= (p8_pipe_ready_bc)? stage1_pipe_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_pipe_data <= (p8_pipe_ready_bc && stage1_pipe_in_vld_d3)? stage1_pipe_in_pd_d3[95:0] : p8_pipe_data; +// VCS sop_coverage_off end +end +always @( + p8_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d3 = p8_pipe_ready_bc; +end +//## pipe (8) output +always @( + p8_pipe_valid + or stage1_pipe_in_rdy_d4 + or p8_pipe_data + ) begin + stage1_pipe_in_vld_d4 = p8_pipe_valid; + p8_pipe_ready = stage1_pipe_in_rdy_d4; + stage1_pipe_in_pd_d4[95:0] = p8_pipe_data; +end +//## pipe (8) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p8_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d4^stage1_pipe_in_rdy_d4^stage1_pipe_in_vld_d3^stage1_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d3 && !stage1_pipe_in_rdy_d3), (stage1_pipe_in_vld_d3), (stage1_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p8 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d1[63:0] (stage2_pipe_in_vld_d1,stage2_pipe_in_rdy_d1) <= stage2_pipe_in_pd_d0[63:0] (stage2_pipe_in_vld_d0,stage2_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p9 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d0 + ,stage2_pipe_in_rdy_d1 + ,stage2_pipe_in_vld_d0 + ,stage2_pipe_in_pd_d1 + ,stage2_pipe_in_rdy_d0 + ,stage2_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d0; +input stage2_pipe_in_rdy_d1; +input stage2_pipe_in_vld_d0; +output [63:0] stage2_pipe_in_pd_d1; +output stage2_pipe_in_rdy_d0; +output stage2_pipe_in_vld_d1; +reg [63:0] p9_pipe_data; +reg p9_pipe_ready; +reg p9_pipe_ready_bc; +reg p9_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d1; +reg stage2_pipe_in_rdy_d0; +reg stage2_pipe_in_vld_d1; +//## pipe (9) valid-ready-bubble-collapse +always @( + p9_pipe_ready + or p9_pipe_valid + ) begin + p9_pipe_ready_bc = p9_pipe_ready || !p9_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p9_pipe_valid <= 1'b0; + end else begin + p9_pipe_valid <= (p9_pipe_ready_bc)? stage2_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p9_pipe_data <= (p9_pipe_ready_bc && stage2_pipe_in_vld_d0)? stage2_pipe_in_pd_d0[63:0] : p9_pipe_data; +// VCS sop_coverage_off end +end +always @( + p9_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d0 = p9_pipe_ready_bc; +end +//## pipe (9) output +always @( + p9_pipe_valid + or stage2_pipe_in_rdy_d1 + or p9_pipe_data + ) begin + stage2_pipe_in_vld_d1 = p9_pipe_valid; + p9_pipe_ready = stage2_pipe_in_rdy_d1; + stage2_pipe_in_pd_d1[63:0] = p9_pipe_data; +end +//## pipe (9) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p9_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d1^stage2_pipe_in_rdy_d1^stage2_pipe_in_vld_d0^stage2_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_18x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d0 && !stage2_pipe_in_rdy_d0), (stage2_pipe_in_vld_d0), (stage2_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p9 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d2[63:0] (stage2_pipe_in_vld_d2,stage2_pipe_in_rdy_d2) <= stage2_pipe_in_pd_d1[63:0] (stage2_pipe_in_vld_d1,stage2_pipe_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p10 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d1 + ,stage2_pipe_in_rdy_d2 + ,stage2_pipe_in_vld_d1 + ,stage2_pipe_in_pd_d2 + ,stage2_pipe_in_rdy_d1 + ,stage2_pipe_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d1; +input stage2_pipe_in_rdy_d2; +input stage2_pipe_in_vld_d1; +output [63:0] stage2_pipe_in_pd_d2; +output stage2_pipe_in_rdy_d1; +output stage2_pipe_in_vld_d2; +reg [63:0] p10_pipe_data; +reg p10_pipe_ready; +reg p10_pipe_ready_bc; +reg p10_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d2; +reg stage2_pipe_in_rdy_d1; +reg stage2_pipe_in_vld_d2; +//## pipe (10) valid-ready-bubble-collapse +always @( + p10_pipe_ready + or p10_pipe_valid + ) begin + p10_pipe_ready_bc = p10_pipe_ready || !p10_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p10_pipe_valid <= 1'b0; + end else begin + p10_pipe_valid <= (p10_pipe_ready_bc)? stage2_pipe_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p10_pipe_data <= (p10_pipe_ready_bc && stage2_pipe_in_vld_d1)? stage2_pipe_in_pd_d1[63:0] : p10_pipe_data; +// VCS sop_coverage_off end +end +always @( + p10_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d1 = p10_pipe_ready_bc; +end +//## pipe (10) output +always @( + p10_pipe_valid + or stage2_pipe_in_rdy_d2 + or p10_pipe_data + ) begin + stage2_pipe_in_vld_d2 = p10_pipe_valid; + p10_pipe_ready = stage2_pipe_in_rdy_d2; + stage2_pipe_in_pd_d2[63:0] = p10_pipe_data; +end +//## pipe (10) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p10_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d2^stage2_pipe_in_rdy_d2^stage2_pipe_in_vld_d1^stage2_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_20x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d1 && !stage2_pipe_in_rdy_d1), (stage2_pipe_in_vld_d1), (stage2_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p10 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d3[63:0] (stage2_pipe_in_vld_d3,stage2_pipe_in_rdy_d3) <= stage2_pipe_in_pd_d2[63:0] (stage2_pipe_in_vld_d2,stage2_pipe_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p11 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d2 + ,stage2_pipe_in_rdy_d3 + ,stage2_pipe_in_vld_d2 + ,stage2_pipe_in_pd_d3 + ,stage2_pipe_in_rdy_d2 + ,stage2_pipe_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d2; +input stage2_pipe_in_rdy_d3; +input stage2_pipe_in_vld_d2; +output [63:0] stage2_pipe_in_pd_d3; +output stage2_pipe_in_rdy_d2; +output stage2_pipe_in_vld_d3; +reg [63:0] p11_pipe_data; +reg p11_pipe_ready; +reg p11_pipe_ready_bc; +reg p11_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d3; +reg stage2_pipe_in_rdy_d2; +reg stage2_pipe_in_vld_d3; +//## pipe (11) valid-ready-bubble-collapse +always @( + p11_pipe_ready + or p11_pipe_valid + ) begin + p11_pipe_ready_bc = p11_pipe_ready || !p11_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p11_pipe_valid <= 1'b0; + end else begin + p11_pipe_valid <= (p11_pipe_ready_bc)? stage2_pipe_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p11_pipe_data <= (p11_pipe_ready_bc && stage2_pipe_in_vld_d2)? stage2_pipe_in_pd_d2[63:0] : p11_pipe_data; +// VCS sop_coverage_off end +end +always @( + p11_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d2 = p11_pipe_ready_bc; +end +//## pipe (11) output +always @( + p11_pipe_valid + or stage2_pipe_in_rdy_d3 + or p11_pipe_data + ) begin + stage2_pipe_in_vld_d3 = p11_pipe_valid; + p11_pipe_ready = stage2_pipe_in_rdy_d3; + stage2_pipe_in_pd_d3[63:0] = p11_pipe_data; +end +//## pipe (11) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p11_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d3^stage2_pipe_in_rdy_d3^stage2_pipe_in_vld_d2^stage2_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_22x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d2 && !stage2_pipe_in_rdy_d2), (stage2_pipe_in_vld_d2), (stage2_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p11 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d4[63:0] (stage2_pipe_in_vld_d4,stage2_pipe_in_rdy_d4) <= stage2_pipe_in_pd_d3[63:0] (stage2_pipe_in_vld_d3,stage2_pipe_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p12 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d3 + ,stage2_pipe_in_rdy_d4 + ,stage2_pipe_in_vld_d3 + ,stage2_pipe_in_pd_d4 + ,stage2_pipe_in_rdy_d3 + ,stage2_pipe_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d3; +input stage2_pipe_in_rdy_d4; +input stage2_pipe_in_vld_d3; +output [63:0] stage2_pipe_in_pd_d4; +output stage2_pipe_in_rdy_d3; +output stage2_pipe_in_vld_d4; +reg [63:0] p12_pipe_data; +reg p12_pipe_ready; +reg p12_pipe_ready_bc; +reg p12_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d4; +reg stage2_pipe_in_rdy_d3; +reg stage2_pipe_in_vld_d4; +//## pipe (12) valid-ready-bubble-collapse +always @( + p12_pipe_ready + or p12_pipe_valid + ) begin + p12_pipe_ready_bc = p12_pipe_ready || !p12_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p12_pipe_valid <= 1'b0; + end else begin + p12_pipe_valid <= (p12_pipe_ready_bc)? stage2_pipe_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p12_pipe_data <= (p12_pipe_ready_bc && stage2_pipe_in_vld_d3)? stage2_pipe_in_pd_d3[63:0] : p12_pipe_data; +// VCS sop_coverage_off end +end +always @( + p12_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d3 = p12_pipe_ready_bc; +end +//## pipe (12) output +always @( + p12_pipe_valid + or stage2_pipe_in_rdy_d4 + or p12_pipe_data + ) begin + stage2_pipe_in_vld_d4 = p12_pipe_valid; + p12_pipe_ready = stage2_pipe_in_rdy_d4; + stage2_pipe_in_pd_d4[63:0] = p12_pipe_data; +end +//## pipe (12) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p12_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d4^stage2_pipe_in_rdy_d4^stage2_pipe_in_vld_d3^stage2_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_24x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d3 && !stage2_pipe_in_rdy_d3), (stage2_pipe_in_vld_d3), (stage2_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p12 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d1[31:0] (stage3_pipe_in_vld_d1,stage3_pipe_in_rdy_d1) <= stage3_pipe_in_pd_d0[31:0] (stage3_pipe_in_vld_d0,stage3_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p13 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d0 + ,stage3_pipe_in_rdy_d1 + ,stage3_pipe_in_vld_d0 + ,stage3_pipe_in_pd_d1 + ,stage3_pipe_in_rdy_d0 + ,stage3_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d0; +input stage3_pipe_in_rdy_d1; +input stage3_pipe_in_vld_d0; +output [31:0] stage3_pipe_in_pd_d1; +output stage3_pipe_in_rdy_d0; +output stage3_pipe_in_vld_d1; +reg [31:0] p13_pipe_data; +reg p13_pipe_ready; +reg p13_pipe_ready_bc; +reg p13_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d1; +reg stage3_pipe_in_rdy_d0; +reg stage3_pipe_in_vld_d1; +//## pipe (13) valid-ready-bubble-collapse +always @( + p13_pipe_ready + or p13_pipe_valid + ) begin + p13_pipe_ready_bc = p13_pipe_ready || !p13_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p13_pipe_valid <= 1'b0; + end else begin + p13_pipe_valid <= (p13_pipe_ready_bc)? stage3_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p13_pipe_data <= (p13_pipe_ready_bc && stage3_pipe_in_vld_d0)? stage3_pipe_in_pd_d0[31:0] : p13_pipe_data; +// VCS sop_coverage_off end +end +always @( + p13_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d0 = p13_pipe_ready_bc; +end +//## pipe (13) output +always @( + p13_pipe_valid + or stage3_pipe_in_rdy_d1 + or p13_pipe_data + ) begin + stage3_pipe_in_vld_d1 = p13_pipe_valid; + p13_pipe_ready = stage3_pipe_in_rdy_d1; + stage3_pipe_in_pd_d1[31:0] = p13_pipe_data; +end +//## pipe (13) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p13_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d1^stage3_pipe_in_rdy_d1^stage3_pipe_in_vld_d0^stage3_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_26x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d0 && !stage3_pipe_in_rdy_d0), (stage3_pipe_in_vld_d0), (stage3_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p13 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d2[31:0] (stage3_pipe_in_vld_d2,stage3_pipe_in_rdy_d2) <= stage3_pipe_in_pd_d1[31:0] (stage3_pipe_in_vld_d1,stage3_pipe_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p14 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d1 + ,stage3_pipe_in_rdy_d2 + ,stage3_pipe_in_vld_d1 + ,stage3_pipe_in_pd_d2 + ,stage3_pipe_in_rdy_d1 + ,stage3_pipe_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d1; +input stage3_pipe_in_rdy_d2; +input stage3_pipe_in_vld_d1; +output [31:0] stage3_pipe_in_pd_d2; +output stage3_pipe_in_rdy_d1; +output stage3_pipe_in_vld_d2; +reg [31:0] p14_pipe_data; +reg p14_pipe_ready; +reg p14_pipe_ready_bc; +reg p14_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d2; +reg stage3_pipe_in_rdy_d1; +reg stage3_pipe_in_vld_d2; +//## pipe (14) valid-ready-bubble-collapse +always @( + p14_pipe_ready + or p14_pipe_valid + ) begin + p14_pipe_ready_bc = p14_pipe_ready || !p14_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p14_pipe_valid <= 1'b0; + end else begin + p14_pipe_valid <= (p14_pipe_ready_bc)? stage3_pipe_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p14_pipe_data <= (p14_pipe_ready_bc && stage3_pipe_in_vld_d1)? stage3_pipe_in_pd_d1[31:0] : p14_pipe_data; +// VCS sop_coverage_off end +end +always @( + p14_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d1 = p14_pipe_ready_bc; +end +//## pipe (14) output +always @( + p14_pipe_valid + or stage3_pipe_in_rdy_d2 + or p14_pipe_data + ) begin + stage3_pipe_in_vld_d2 = p14_pipe_valid; + p14_pipe_ready = stage3_pipe_in_rdy_d2; + stage3_pipe_in_pd_d2[31:0] = p14_pipe_data; +end +//## pipe (14) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p14_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d2^stage3_pipe_in_rdy_d2^stage3_pipe_in_vld_d1^stage3_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_28x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d1 && !stage3_pipe_in_rdy_d1), (stage3_pipe_in_vld_d1), (stage3_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p14 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d3[31:0] (stage3_pipe_in_vld_d3,stage3_pipe_in_rdy_d3) <= stage3_pipe_in_pd_d2[31:0] (stage3_pipe_in_vld_d2,stage3_pipe_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p15 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d2 + ,stage3_pipe_in_rdy_d3 + ,stage3_pipe_in_vld_d2 + ,stage3_pipe_in_pd_d3 + ,stage3_pipe_in_rdy_d2 + ,stage3_pipe_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d2; +input stage3_pipe_in_rdy_d3; +input stage3_pipe_in_vld_d2; +output [31:0] stage3_pipe_in_pd_d3; +output stage3_pipe_in_rdy_d2; +output stage3_pipe_in_vld_d3; +reg [31:0] p15_pipe_data; +reg p15_pipe_ready; +reg p15_pipe_ready_bc; +reg p15_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d3; +reg stage3_pipe_in_rdy_d2; +reg stage3_pipe_in_vld_d3; +//## pipe (15) valid-ready-bubble-collapse +always @( + p15_pipe_ready + or p15_pipe_valid + ) begin + p15_pipe_ready_bc = p15_pipe_ready || !p15_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p15_pipe_valid <= 1'b0; + end else begin + p15_pipe_valid <= (p15_pipe_ready_bc)? stage3_pipe_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p15_pipe_data <= (p15_pipe_ready_bc && stage3_pipe_in_vld_d2)? stage3_pipe_in_pd_d2[31:0] : p15_pipe_data; +// VCS sop_coverage_off end +end +always @( + p15_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d2 = p15_pipe_ready_bc; +end +//## pipe (15) output +always @( + p15_pipe_valid + or stage3_pipe_in_rdy_d3 + or p15_pipe_data + ) begin + stage3_pipe_in_vld_d3 = p15_pipe_valid; + p15_pipe_ready = stage3_pipe_in_rdy_d3; + stage3_pipe_in_pd_d3[31:0] = p15_pipe_data; +end +//## pipe (15) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p15_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d3^stage3_pipe_in_rdy_d3^stage3_pipe_in_vld_d2^stage3_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_30x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d2 && !stage3_pipe_in_rdy_d2), (stage3_pipe_in_vld_d2), (stage3_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p15 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d4[31:0] (stage3_pipe_in_vld_d4,stage3_pipe_in_rdy_d4) <= stage3_pipe_in_pd_d3[31:0] (stage3_pipe_in_vld_d3,stage3_pipe_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p16 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d3 + ,stage3_pipe_in_rdy_d4 + ,stage3_pipe_in_vld_d3 + ,stage3_pipe_in_pd_d4 + ,stage3_pipe_in_rdy_d3 + ,stage3_pipe_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d3; +input stage3_pipe_in_rdy_d4; +input stage3_pipe_in_vld_d3; +output [31:0] stage3_pipe_in_pd_d4; +output stage3_pipe_in_rdy_d3; +output stage3_pipe_in_vld_d4; +reg [31:0] p16_pipe_data; +reg p16_pipe_ready; +reg p16_pipe_ready_bc; +reg p16_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d4; +reg stage3_pipe_in_rdy_d3; +reg stage3_pipe_in_vld_d4; +//## pipe (16) valid-ready-bubble-collapse +always @( + p16_pipe_ready + or p16_pipe_valid + ) begin + p16_pipe_ready_bc = p16_pipe_ready || !p16_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p16_pipe_valid <= 1'b0; + end else begin + p16_pipe_valid <= (p16_pipe_ready_bc)? stage3_pipe_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p16_pipe_data <= (p16_pipe_ready_bc && stage3_pipe_in_vld_d3)? stage3_pipe_in_pd_d3[31:0] : p16_pipe_data; +// VCS sop_coverage_off end +end +always @( + p16_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d3 = p16_pipe_ready_bc; +end +//## pipe (16) output +always @( + p16_pipe_valid + or stage3_pipe_in_rdy_d4 + or p16_pipe_data + ) begin + stage3_pipe_in_vld_d4 = p16_pipe_valid; + p16_pipe_ready = stage3_pipe_in_rdy_d4; + stage3_pipe_in_pd_d4[31:0] = p16_pipe_data; +end +//## pipe (16) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p16_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d4^stage3_pipe_in_rdy_d4^stage3_pipe_in_vld_d3^stage3_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_32x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d3 && !stage3_pipe_in_rdy_d3), (stage3_pipe_in_vld_d3), (stage3_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p16 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/fp_sum_block.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/fp_sum_block.v.vcp new file mode 100644 index 0000000..f2f15bf --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/fp_sum_block.v.vcp @@ -0,0 +1,3121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: fp_sum_block.v +module fp_sum_block ( + fp16_dout_0 //|< i + ,fp16_dout_1 //|< i + ,fp16_dout_2 //|< i + ,fp16_dout_3 //|< i + ,fp16_dout_4 //|< i + ,fp16_dout_5 //|< i + ,fp16_dout_6 //|< i + ,fp16_dout_7 //|< i + ,fp16_dout_8 //|< i + ,fp16_sum_rdy //|< i + ,fp_sq_out_vld //|< i + ,len3 //|< i + ,len5 //|< i + ,len7 //|< i + ,len9 //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,reg2dp_normalz_len //|< i + ,fp16_sum //|> o + ,fp16_sum_vld //|> o + ,fp_sq_out_rdy //|> o + ); +input [31:0] fp16_dout_0; +input [31:0] fp16_dout_1; +input [31:0] fp16_dout_2; +input [31:0] fp16_dout_3; +input [31:0] fp16_dout_4; +input [31:0] fp16_dout_5; +input [31:0] fp16_dout_6; +input [31:0] fp16_dout_7; +input [31:0] fp16_dout_8; +input fp16_sum_rdy; +input fp_sq_out_vld; +input len3; +input len5; +input len7; +input len9; +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] reg2dp_normalz_len; +output [31:0] fp16_sum; +output fp16_sum_vld; +output fp_sq_out_rdy; +reg [31:0] fp16_sum; +reg fp16_sum_vld; +wire [31:0] fp16_dout_4_in_pd; +wire [31:0] fp16_dout_4_in_pd_d0; +wire [31:0] fp16_dout_4_in_pd_d1; +wire [31:0] fp16_dout_4_in_pd_d2; +wire [31:0] fp16_dout_4_in_pd_d3; +wire [31:0] fp16_dout_4_in_pd_d4; +wire fp16_dout_4_in_rdy; +wire fp16_dout_4_in_rdy_d0; +wire fp16_dout_4_in_rdy_d1; +wire fp16_dout_4_in_rdy_d2; +wire fp16_dout_4_in_rdy_d3; +wire fp16_dout_4_in_rdy_d4; +wire fp16_dout_4_in_vld; +wire fp16_dout_4_in_vld_d0; +wire fp16_dout_4_in_vld_d1; +wire fp16_dout_4_in_vld_d2; +wire fp16_dout_4_in_vld_d3; +wire fp16_dout_4_in_vld_d4; +wire [31:0] fp16_dout_4_out_pd; +wire fp16_dout_4_out_rdy; +wire fp16_dout_4_out_vld; +wire [31:0] fp16_sum3; +wire fp16_sum35_rdy; +wire fp16_sum35_vld; +wire fp16_sum3_rdy; +wire fp16_sum3_vld; +wire fp16_sum4_rdy; +wire fp16_sum4_vld; +wire [31:0] fp16_sum5; +wire fp16_sum5_rdy; +wire fp16_sum5_vld; +wire [31:0] fp16_sum7; +wire fp16_sum7_rdy; +wire fp16_sum7_vld; +wire [31:0] fp16_sum9; +wire fp16_sum9_rdy; +wire fp16_sum9_vld; +wire [31:0] fp16_sum_0_8; +wire fp16_sum_0_8_rdy; +wire fp16_sum_0_8_vld; +wire [31:0] fp16_sum_1_7; +wire fp16_sum_1_7_rdy; +wire fp16_sum_1_7_vld; +wire [31:0] fp16_sum_2_6; +wire fp16_sum_2_6_rdy; +wire fp16_sum_2_6_vld; +wire [31:0] fp16_sum_3_5; +wire fp16_sum_3_5_rdy; +wire fp16_sum_3_5_vld; +wire fp16_sum_stage0_rdy; +wire fp16_sum_stage0_vld; +wire fp16_sum_stage1_rdy; +wire fp16_sum_stage1_vld; +wire fp16_sum_stage2_rdy; +wire fp16_sum_stage2_vld; +wire fp16_sum_stage3_rdy; +wire fp16_sum_stage3_vld; +wire [8:0] fp_sq_vld; +wire [8:0] fp_sum_in_rdy; +wire [95:0] stage1_pipe_in_pd; +wire [95:0] stage1_pipe_in_pd_d0; +wire [95:0] stage1_pipe_in_pd_d1; +wire [95:0] stage1_pipe_in_pd_d2; +wire [95:0] stage1_pipe_in_pd_d3; +wire [95:0] stage1_pipe_in_pd_d4; +wire stage1_pipe_in_rdy; +wire stage1_pipe_in_rdy_d0; +wire stage1_pipe_in_rdy_d1; +wire stage1_pipe_in_rdy_d2; +wire stage1_pipe_in_rdy_d3; +wire stage1_pipe_in_rdy_d4; +wire stage1_pipe_in_vld; +wire stage1_pipe_in_vld_d0; +wire stage1_pipe_in_vld_d1; +wire stage1_pipe_in_vld_d2; +wire stage1_pipe_in_vld_d3; +wire stage1_pipe_in_vld_d4; +wire [95:0] stage1_pipe_out_pd; +wire stage1_pipe_out_rdy; +wire stage1_pipe_out_vld; +wire [63:0] stage2_pipe_in_pd; +wire [63:0] stage2_pipe_in_pd_d0; +wire [63:0] stage2_pipe_in_pd_d1; +wire [63:0] stage2_pipe_in_pd_d2; +wire [63:0] stage2_pipe_in_pd_d3; +wire [63:0] stage2_pipe_in_pd_d4; +wire stage2_pipe_in_rdy; +wire stage2_pipe_in_rdy_d0; +wire stage2_pipe_in_rdy_d1; +wire stage2_pipe_in_rdy_d2; +wire stage2_pipe_in_rdy_d3; +wire stage2_pipe_in_rdy_d4; +wire stage2_pipe_in_vld; +wire stage2_pipe_in_vld_d0; +wire stage2_pipe_in_vld_d1; +wire stage2_pipe_in_vld_d2; +wire stage2_pipe_in_vld_d3; +wire stage2_pipe_in_vld_d4; +wire [63:0] stage2_pipe_out_pd; +wire stage2_pipe_out_rdy; +wire stage2_pipe_out_vld; +wire stage2_sum26_rdy; +wire stage2_sum26_vld; +wire stage2_sum3_rdy; +wire stage2_sum3_vld; +wire [31:0] stage3_pipe_in_pd; +wire [31:0] stage3_pipe_in_pd_d0; +wire [31:0] stage3_pipe_in_pd_d1; +wire [31:0] stage3_pipe_in_pd_d2; +wire [31:0] stage3_pipe_in_pd_d3; +wire [31:0] stage3_pipe_in_pd_d4; +wire stage3_pipe_in_rdy; +wire stage3_pipe_in_rdy_d0; +wire stage3_pipe_in_rdy_d1; +wire stage3_pipe_in_rdy_d2; +wire stage3_pipe_in_rdy_d3; +wire stage3_pipe_in_rdy_d4; +wire stage3_pipe_in_vld; +wire stage3_pipe_in_vld_d0; +wire stage3_pipe_in_vld_d1; +wire stage3_pipe_in_vld_d2; +wire stage3_pipe_in_vld_d3; +wire stage3_pipe_in_vld_d4; +wire [31:0] stage3_pipe_out_pd; +wire stage3_pipe_out_rdy; +wire stage3_pipe_out_vld; +wire stage3_sum17_rdy; +wire stage3_sum17_vld; +wire stage3_sum5_rdy; +wire stage3_sum5_vld; +wire stage4_sum08_rdy; +wire stage4_sum08_vld; +wire stage4_sum7_rdy; +wire stage4_sum7_vld; +/////////////////////////////////// +//assign len3_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3); +//assign len5_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5); +//assign len7_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7); +//assign len9_en = (reg2dp_normalz_len == NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9); +/////////////////////////////////// +assign fp_sq_out_rdy = &fp_sum_in_rdy[8:0]; +assign fp_sq_vld[0] = (len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:1]) ) : 1'b0; +assign fp_sq_vld[1] = (len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:2]) & ( fp_sum_in_rdy[ 0])) : 1'b0; +assign fp_sq_vld[2] = (len5 | len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:3]) & (&fp_sum_in_rdy[1:0])) : 1'b0; +assign fp_sq_vld[3] = (fp_sq_out_vld & (&fp_sum_in_rdy[8:4]) & (&fp_sum_in_rdy[2:0])); +assign fp_sq_vld[4] = (fp_sq_out_vld & (&fp_sum_in_rdy[8:5]) & (&fp_sum_in_rdy[3:0])); +assign fp_sq_vld[5] = (fp_sq_out_vld & (&fp_sum_in_rdy[8:6]) & (&fp_sum_in_rdy[4:0])); +assign fp_sq_vld[6] = (len5 | len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8:7]) & (&fp_sum_in_rdy[5:0])) : 1'b0; +assign fp_sq_vld[7] = (len7 | len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[8 ]) & (&fp_sum_in_rdy[6:0])) : 1'b0; +assign fp_sq_vld[8] = (len9) ? (fp_sq_out_vld & (&fp_sum_in_rdy[7:0])) : 1'b0; +/////////////////////////////////// +HLS_fp32_add u_HLS_fp32_add_3_5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_3[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[3]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[3]) //|> w + ,.chn_b_rsc_z (fp16_dout_5[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[5]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[5]) //|> w + ,.chn_o_rsc_z (fp16_sum_3_5[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_3_5_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_3_5_vld) //|> w + ); +HLS_fp32_add u_HLS_fp32_add_2_6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_2[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[2]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[2]) //|> w + ,.chn_b_rsc_z (fp16_dout_6[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[6]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[6]) //|> w + ,.chn_o_rsc_z (fp16_sum_2_6[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_2_6_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_2_6_vld) //|> w + ); +HLS_fp32_add u_HLS_fp32_add_1_7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_1[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[1]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[1]) //|> w + ,.chn_b_rsc_z (fp16_dout_7[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[7]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[7]) //|> w + ,.chn_o_rsc_z (fp16_sum_1_7[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_1_7_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_1_7_vld) //|> w + ); +HLS_fp32_add u_HLS_fp32_add_0_8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_dout_0[31:0]) //|< i + ,.chn_a_rsc_vz (fp_sq_vld[0]) //|< w + ,.chn_a_rsc_lz (fp_sum_in_rdy[0]) //|> w + ,.chn_b_rsc_z (fp16_dout_8[31:0]) //|< i + ,.chn_b_rsc_vz (fp_sq_vld[8]) //|< w + ,.chn_b_rsc_lz (fp_sum_in_rdy[8]) //|> w + ,.chn_o_rsc_z (fp16_sum_0_8[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum_0_8_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum_0_8_vld) //|> w + ); +//assign fp16_sum_3_5_rdy = fp16_sum_stage0_rdy & fp16_sum_2_6_vld & fp16_sum_1_7_vld & fp16_sum_0_8_vld & fp16_dout_4_out_vld; +//assign fp16_sum_2_6_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & fp16_sum_1_7_vld & fp16_sum_0_8_vld & fp16_dout_4_out_vld; +//assign fp16_sum_1_7_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & fp16_sum_2_6_vld & fp16_sum_0_8_vld & fp16_dout_4_out_vld; +//assign fp16_sum_0_8_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & fp16_sum_2_6_vld & fp16_sum_1_7_vld & fp16_dout_4_out_vld; +assign fp16_sum_3_5_rdy = fp16_sum_stage0_rdy & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +assign fp16_sum_2_6_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +assign fp16_sum_1_7_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +assign fp16_sum_0_8_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & fp16_dout_4_out_vld; +//fp16_dout_4 sync process +assign fp16_dout_4_in_pd = fp16_dout_4[31:0]; +assign fp16_dout_4_in_vld = fp_sq_vld[4]; +assign fp_sum_in_rdy[4] = fp16_dout_4_in_rdy; +assign fp16_dout_4_in_vld_d0 = fp16_dout_4_in_vld; +assign fp16_dout_4_in_rdy = fp16_dout_4_in_rdy_d0; +assign fp16_dout_4_in_pd_d0[31:0] = fp16_dout_4_in_pd[31:0]; +FP_SUM_BLOCK_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d0 (fp16_dout_4_in_pd_d0[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d1 (fp16_dout_4_in_rdy_d1) //|< w + ,.fp16_dout_4_in_vld_d0 (fp16_dout_4_in_vld_d0) //|< w + ,.fp16_dout_4_in_pd_d1 (fp16_dout_4_in_pd_d1[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d0 (fp16_dout_4_in_rdy_d0) //|> w + ,.fp16_dout_4_in_vld_d1 (fp16_dout_4_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d1 (fp16_dout_4_in_pd_d1[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d2 (fp16_dout_4_in_rdy_d2) //|< w + ,.fp16_dout_4_in_vld_d1 (fp16_dout_4_in_vld_d1) //|< w + ,.fp16_dout_4_in_pd_d2 (fp16_dout_4_in_pd_d2[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d1 (fp16_dout_4_in_rdy_d1) //|> w + ,.fp16_dout_4_in_vld_d2 (fp16_dout_4_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d2 (fp16_dout_4_in_pd_d2[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d3 (fp16_dout_4_in_rdy_d3) //|< w + ,.fp16_dout_4_in_vld_d2 (fp16_dout_4_in_vld_d2) //|< w + ,.fp16_dout_4_in_pd_d3 (fp16_dout_4_in_pd_d3[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d2 (fp16_dout_4_in_rdy_d2) //|> w + ,.fp16_dout_4_in_vld_d3 (fp16_dout_4_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.fp16_dout_4_in_pd_d3 (fp16_dout_4_in_pd_d3[31:0]) //|< w + ,.fp16_dout_4_in_rdy_d4 (fp16_dout_4_in_rdy_d4) //|< w + ,.fp16_dout_4_in_vld_d3 (fp16_dout_4_in_vld_d3) //|< w + ,.fp16_dout_4_in_pd_d4 (fp16_dout_4_in_pd_d4[31:0]) //|> w + ,.fp16_dout_4_in_rdy_d3 (fp16_dout_4_in_rdy_d3) //|> w + ,.fp16_dout_4_in_vld_d4 (fp16_dout_4_in_vld_d4) //|> w + ); +assign fp16_dout_4_out_vld = fp16_dout_4_in_vld_d4; +assign fp16_dout_4_in_rdy_d4 = fp16_dout_4_out_rdy; +assign fp16_dout_4_out_pd[31:0] = fp16_dout_4_in_pd_d4[31:0]; +assign fp16_dout_4_out_rdy = fp16_sum_stage0_rdy & fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1); +//sum stage0 output valid +assign fp16_sum_stage0_vld = fp16_sum_3_5_vld & (len3 ? 1'b1 : fp16_sum_2_6_vld) & ((len7 | len9) ? fp16_sum_1_7_vld : 1'b1) & (len9 ? fp16_sum_0_8_vld : 1'b1) & fp16_dout_4_out_vld; +/////////////////////////////////// +assign fp16_sum_stage0_rdy = len3 ? (fp16_sum35_rdy & fp16_sum4_rdy) : (fp16_sum35_rdy & fp16_sum4_rdy & stage1_pipe_in_rdy); +assign fp16_sum35_vld = len3 ? (fp16_sum_stage0_vld & fp16_sum4_rdy) : (fp16_sum_stage0_vld & fp16_sum4_rdy & stage1_pipe_in_rdy); +assign fp16_sum4_vld = len3 ? (fp16_sum_stage0_vld & fp16_sum35_rdy) : (fp16_sum_stage0_vld & fp16_sum35_rdy & stage1_pipe_in_rdy); +assign stage1_pipe_in_vld = (len5 | len7 | len9)? (fp16_sum_stage0_vld & fp16_sum35_rdy & fp16_sum4_rdy) : 1'b0; +HLS_fp32_add u_HLS_fp32_add_sum3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum_3_5[31:0]) //|< w + ,.chn_a_rsc_vz (fp16_sum35_vld) //|< w + ,.chn_a_rsc_lz (fp16_sum35_rdy) //|> w + ,.chn_b_rsc_z (fp16_dout_4_out_pd[31:0]) //|< w + ,.chn_b_rsc_vz (fp16_sum4_vld) //|< w + ,.chn_b_rsc_lz (fp16_sum4_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum3[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum3_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum3_vld) //|> w + ); +assign fp16_sum3_rdy = len3 ? fp16_sum_rdy : (fp16_sum_stage1_rdy & stage1_pipe_out_vld); +assign stage1_pipe_out_rdy = len3 ? 1'b1 : (fp16_sum_stage1_rdy & fp16_sum3_vld); +assign stage1_pipe_in_pd = {fp16_sum_2_6,fp16_sum_1_7,fp16_sum_0_8}; +assign stage1_pipe_in_vld_d0 = stage1_pipe_in_vld; +assign stage1_pipe_in_rdy = stage1_pipe_in_rdy_d0; +assign stage1_pipe_in_pd_d0[95:0] = stage1_pipe_in_pd[95:0]; +FP_SUM_BLOCK_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d0 (stage1_pipe_in_pd_d0[95:0]) //|< w + ,.stage1_pipe_in_rdy_d1 (stage1_pipe_in_rdy_d1) //|< w + ,.stage1_pipe_in_vld_d0 (stage1_pipe_in_vld_d0) //|< w + ,.stage1_pipe_in_pd_d1 (stage1_pipe_in_pd_d1[95:0]) //|> w + ,.stage1_pipe_in_rdy_d0 (stage1_pipe_in_rdy_d0) //|> w + ,.stage1_pipe_in_vld_d1 (stage1_pipe_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d1 (stage1_pipe_in_pd_d1[95:0]) //|< w + ,.stage1_pipe_in_rdy_d2 (stage1_pipe_in_rdy_d2) //|< w + ,.stage1_pipe_in_vld_d1 (stage1_pipe_in_vld_d1) //|< w + ,.stage1_pipe_in_pd_d2 (stage1_pipe_in_pd_d2[95:0]) //|> w + ,.stage1_pipe_in_rdy_d1 (stage1_pipe_in_rdy_d1) //|> w + ,.stage1_pipe_in_vld_d2 (stage1_pipe_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d2 (stage1_pipe_in_pd_d2[95:0]) //|< w + ,.stage1_pipe_in_rdy_d3 (stage1_pipe_in_rdy_d3) //|< w + ,.stage1_pipe_in_vld_d2 (stage1_pipe_in_vld_d2) //|< w + ,.stage1_pipe_in_pd_d3 (stage1_pipe_in_pd_d3[95:0]) //|> w + ,.stage1_pipe_in_rdy_d2 (stage1_pipe_in_rdy_d2) //|> w + ,.stage1_pipe_in_vld_d3 (stage1_pipe_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p8 pipe_p8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage1_pipe_in_pd_d3 (stage1_pipe_in_pd_d3[95:0]) //|< w + ,.stage1_pipe_in_rdy_d4 (stage1_pipe_in_rdy_d4) //|< w + ,.stage1_pipe_in_vld_d3 (stage1_pipe_in_vld_d3) //|< w + ,.stage1_pipe_in_pd_d4 (stage1_pipe_in_pd_d4[95:0]) //|> w + ,.stage1_pipe_in_rdy_d3 (stage1_pipe_in_rdy_d3) //|> w + ,.stage1_pipe_in_vld_d4 (stage1_pipe_in_vld_d4) //|> w + ); +assign stage1_pipe_out_vld = stage1_pipe_in_vld_d4; +assign stage1_pipe_in_rdy_d4 = stage1_pipe_out_rdy; +assign stage1_pipe_out_pd[95:0] = stage1_pipe_in_pd_d4[95:0]; +assign fp16_sum_stage1_vld = len3 ? 1'b0 : (fp16_sum3_vld & stage1_pipe_out_vld); +////////////////////////////////////// +assign fp16_sum_stage1_rdy = (len7 | len9) ? (stage2_sum3_rdy & stage2_sum26_rdy & stage2_pipe_in_rdy) : (stage2_sum3_rdy & stage2_sum26_rdy); +assign stage2_sum3_vld = (len7 | len9) ? (fp16_sum_stage1_vld & stage2_sum26_rdy & stage2_pipe_in_rdy) : (fp16_sum_stage1_vld & stage2_sum26_rdy); +assign stage2_sum26_vld = (len7 | len9) ? (fp16_sum_stage1_vld & stage2_sum3_rdy & stage2_pipe_in_rdy) : (fp16_sum_stage1_vld & stage2_sum3_rdy); +assign stage2_pipe_in_vld = (len7 | len9)? (fp16_sum_stage1_vld & stage2_sum26_rdy & stage2_sum3_rdy) : 1'b0; +HLS_fp32_add u_HLS_fp32_add_sum5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum3[31:0]) //|< w + ,.chn_a_rsc_vz (stage2_sum3_vld) //|< w + ,.chn_a_rsc_lz (stage2_sum3_rdy) //|> w + ,.chn_b_rsc_z (stage1_pipe_out_pd[95:64]) //|< w + ,.chn_b_rsc_vz (stage2_sum26_vld) //|< w + ,.chn_b_rsc_lz (stage2_sum26_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum5[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum5_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum5_vld) //|> w + ); +//fp16_sum_2_6 ; +assign fp16_sum5_rdy = len5 ? fp16_sum_rdy : (fp16_sum_stage2_rdy & stage2_pipe_out_vld); +assign stage2_pipe_out_rdy = (len7 | len9) ? (fp16_sum_stage2_rdy & fp16_sum5_vld) : 1'b1; +assign stage2_pipe_in_pd = stage1_pipe_out_pd[63:0];//{fp16_sum_1_7,fp16_sum_0_8}; +assign stage2_pipe_in_vld_d0 = stage2_pipe_in_vld; +assign stage2_pipe_in_rdy = stage2_pipe_in_rdy_d0; +assign stage2_pipe_in_pd_d0[63:0] = stage2_pipe_in_pd[63:0]; +FP_SUM_BLOCK_pipe_p9 pipe_p9 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d0 (stage2_pipe_in_pd_d0[63:0]) //|< w + ,.stage2_pipe_in_rdy_d1 (stage2_pipe_in_rdy_d1) //|< w + ,.stage2_pipe_in_vld_d0 (stage2_pipe_in_vld_d0) //|< w + ,.stage2_pipe_in_pd_d1 (stage2_pipe_in_pd_d1[63:0]) //|> w + ,.stage2_pipe_in_rdy_d0 (stage2_pipe_in_rdy_d0) //|> w + ,.stage2_pipe_in_vld_d1 (stage2_pipe_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p10 pipe_p10 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d1 (stage2_pipe_in_pd_d1[63:0]) //|< w + ,.stage2_pipe_in_rdy_d2 (stage2_pipe_in_rdy_d2) //|< w + ,.stage2_pipe_in_vld_d1 (stage2_pipe_in_vld_d1) //|< w + ,.stage2_pipe_in_pd_d2 (stage2_pipe_in_pd_d2[63:0]) //|> w + ,.stage2_pipe_in_rdy_d1 (stage2_pipe_in_rdy_d1) //|> w + ,.stage2_pipe_in_vld_d2 (stage2_pipe_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p11 pipe_p11 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d2 (stage2_pipe_in_pd_d2[63:0]) //|< w + ,.stage2_pipe_in_rdy_d3 (stage2_pipe_in_rdy_d3) //|< w + ,.stage2_pipe_in_vld_d2 (stage2_pipe_in_vld_d2) //|< w + ,.stage2_pipe_in_pd_d3 (stage2_pipe_in_pd_d3[63:0]) //|> w + ,.stage2_pipe_in_rdy_d2 (stage2_pipe_in_rdy_d2) //|> w + ,.stage2_pipe_in_vld_d3 (stage2_pipe_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p12 pipe_p12 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage2_pipe_in_pd_d3 (stage2_pipe_in_pd_d3[63:0]) //|< w + ,.stage2_pipe_in_rdy_d4 (stage2_pipe_in_rdy_d4) //|< w + ,.stage2_pipe_in_vld_d3 (stage2_pipe_in_vld_d3) //|< w + ,.stage2_pipe_in_pd_d4 (stage2_pipe_in_pd_d4[63:0]) //|> w + ,.stage2_pipe_in_rdy_d3 (stage2_pipe_in_rdy_d3) //|> w + ,.stage2_pipe_in_vld_d4 (stage2_pipe_in_vld_d4) //|> w + ); +assign stage2_pipe_out_vld = stage2_pipe_in_vld_d4; +assign stage2_pipe_in_rdy_d4 = stage2_pipe_out_rdy; +assign stage2_pipe_out_pd[63:0] = stage2_pipe_in_pd_d4[63:0]; +assign fp16_sum_stage2_vld = (len3 | len5) ? 1'b0 : (fp16_sum5_vld & stage2_pipe_out_vld); +////////////////////////////////////// +assign fp16_sum_stage2_rdy = len9 ? (stage3_sum5_rdy & stage3_sum17_rdy & stage3_pipe_in_rdy) : (stage3_sum5_rdy & stage3_sum17_rdy); +assign stage3_sum5_vld = len9 ? (fp16_sum_stage2_vld & stage3_sum17_rdy & stage3_pipe_in_rdy) : (fp16_sum_stage2_vld & stage3_sum17_rdy); +assign stage3_sum17_vld = len9 ? (fp16_sum_stage2_vld & stage3_sum5_rdy & stage3_pipe_in_rdy) : (fp16_sum_stage2_vld & stage3_sum5_rdy); +assign stage3_pipe_in_vld = len9 ? (fp16_sum_stage2_vld & stage3_sum17_rdy & stage3_sum5_rdy) : 1'b0; +HLS_fp32_add u_HLS_fp32_add_sum7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum5[31:0]) //|< w + ,.chn_a_rsc_vz (stage3_sum5_vld) //|< w + ,.chn_a_rsc_lz (stage3_sum5_rdy) //|> w + ,.chn_b_rsc_z (stage2_pipe_out_pd[63:32]) //|< w + ,.chn_b_rsc_vz (stage3_sum17_vld) //|< w + ,.chn_b_rsc_lz (stage3_sum17_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum7[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum7_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum7_vld) //|> w + ); +//fp16_sum_1_7 ; +assign fp16_sum7_rdy = len7 ? fp16_sum_rdy : (fp16_sum_stage3_rdy & stage3_pipe_out_vld); +assign stage3_pipe_out_rdy = len9 ? (fp16_sum_stage3_rdy & fp16_sum7_vld) : 1'b1; +assign stage3_pipe_in_pd = stage2_pipe_out_pd[31:0]; +assign stage3_pipe_in_vld_d0 = stage3_pipe_in_vld; +assign stage3_pipe_in_rdy = stage3_pipe_in_rdy_d0; +assign stage3_pipe_in_pd_d0[31:0] = stage3_pipe_in_pd[31:0]; +FP_SUM_BLOCK_pipe_p13 pipe_p13 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d0 (stage3_pipe_in_pd_d0[31:0]) //|< w + ,.stage3_pipe_in_rdy_d1 (stage3_pipe_in_rdy_d1) //|< w + ,.stage3_pipe_in_vld_d0 (stage3_pipe_in_vld_d0) //|< w + ,.stage3_pipe_in_pd_d1 (stage3_pipe_in_pd_d1[31:0]) //|> w + ,.stage3_pipe_in_rdy_d0 (stage3_pipe_in_rdy_d0) //|> w + ,.stage3_pipe_in_vld_d1 (stage3_pipe_in_vld_d1) //|> w + ); +FP_SUM_BLOCK_pipe_p14 pipe_p14 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d1 (stage3_pipe_in_pd_d1[31:0]) //|< w + ,.stage3_pipe_in_rdy_d2 (stage3_pipe_in_rdy_d2) //|< w + ,.stage3_pipe_in_vld_d1 (stage3_pipe_in_vld_d1) //|< w + ,.stage3_pipe_in_pd_d2 (stage3_pipe_in_pd_d2[31:0]) //|> w + ,.stage3_pipe_in_rdy_d1 (stage3_pipe_in_rdy_d1) //|> w + ,.stage3_pipe_in_vld_d2 (stage3_pipe_in_vld_d2) //|> w + ); +FP_SUM_BLOCK_pipe_p15 pipe_p15 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d2 (stage3_pipe_in_pd_d2[31:0]) //|< w + ,.stage3_pipe_in_rdy_d3 (stage3_pipe_in_rdy_d3) //|< w + ,.stage3_pipe_in_vld_d2 (stage3_pipe_in_vld_d2) //|< w + ,.stage3_pipe_in_pd_d3 (stage3_pipe_in_pd_d3[31:0]) //|> w + ,.stage3_pipe_in_rdy_d2 (stage3_pipe_in_rdy_d2) //|> w + ,.stage3_pipe_in_vld_d3 (stage3_pipe_in_vld_d3) //|> w + ); +FP_SUM_BLOCK_pipe_p16 pipe_p16 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.stage3_pipe_in_pd_d3 (stage3_pipe_in_pd_d3[31:0]) //|< w + ,.stage3_pipe_in_rdy_d4 (stage3_pipe_in_rdy_d4) //|< w + ,.stage3_pipe_in_vld_d3 (stage3_pipe_in_vld_d3) //|< w + ,.stage3_pipe_in_pd_d4 (stage3_pipe_in_pd_d4[31:0]) //|> w + ,.stage3_pipe_in_rdy_d3 (stage3_pipe_in_rdy_d3) //|> w + ,.stage3_pipe_in_vld_d4 (stage3_pipe_in_vld_d4) //|> w + ); +assign stage3_pipe_out_vld = stage3_pipe_in_vld_d4; +assign stage3_pipe_in_rdy_d4 = stage3_pipe_out_rdy; +assign stage3_pipe_out_pd[31:0] = stage3_pipe_in_pd_d4[31:0]; +assign fp16_sum_stage3_vld = (len3 | len5 | len7) ? 1'b0 : (fp16_sum7_vld & stage3_pipe_out_vld); +////////////////////////////////////// +assign fp16_sum_stage3_rdy = stage4_sum7_rdy & stage4_sum08_rdy; +assign stage4_sum7_vld = fp16_sum_stage3_vld & stage4_sum08_rdy; +assign stage4_sum08_vld = fp16_sum_stage3_vld & stage4_sum7_rdy; +HLS_fp32_add u_HLS_fp32_add_sum9 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_sum7[31:0]) //|< w + ,.chn_a_rsc_vz (stage4_sum7_vld) //|< w + ,.chn_a_rsc_lz (stage4_sum7_rdy) //|> w + ,.chn_b_rsc_z (stage3_pipe_out_pd[31:0]) //|< w + ,.chn_b_rsc_vz (stage4_sum08_vld) //|< w + ,.chn_b_rsc_lz (stage4_sum08_rdy) //|> w + ,.chn_o_rsc_z (fp16_sum9[31:0]) //|> w + ,.chn_o_rsc_vz (fp16_sum9_rdy) //|< w + ,.chn_o_rsc_lz (fp16_sum9_vld) //|> w + ); +//fp16_sum_0_8 ; +assign fp16_sum9_rdy = fp16_sum_rdy; +////////////////////////////////////// +always @( + reg2dp_normalz_len + or fp16_sum3 + or fp16_sum3_vld + or fp16_sum5 + or fp16_sum5_vld + or fp16_sum7 + or fp16_sum7_vld + or fp16_sum9 + or fp16_sum9_vld + ) begin + case(reg2dp_normalz_len[1:0]) + 2'h0 : begin + fp16_sum = fp16_sum3; + fp16_sum_vld = fp16_sum3_vld; + end + 2'h1 : begin + fp16_sum = fp16_sum5; + fp16_sum_vld = fp16_sum5_vld; + end + 2'h2 : begin + fp16_sum = fp16_sum7; + fp16_sum_vld = fp16_sum7_vld; + end + default: begin +//NVDLA_CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9: begin + fp16_sum = fp16_sum9; + fp16_sum_vld = fp16_sum9_vld; + end + endcase +end +//fp16_sum_rdy +endmodule // fp_sum_block +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d1[31:0] (fp16_dout_4_in_vld_d1,fp16_dout_4_in_rdy_d1) <= fp16_dout_4_in_pd_d0[31:0] (fp16_dout_4_in_vld_d0,fp16_dout_4_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d0 + ,fp16_dout_4_in_rdy_d1 + ,fp16_dout_4_in_vld_d0 + ,fp16_dout_4_in_pd_d1 + ,fp16_dout_4_in_rdy_d0 + ,fp16_dout_4_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d0; +input fp16_dout_4_in_rdy_d1; +input fp16_dout_4_in_vld_d0; +output [31:0] fp16_dout_4_in_pd_d1; +output fp16_dout_4_in_rdy_d0; +output fp16_dout_4_in_vld_d1; +reg [31:0] fp16_dout_4_in_pd_d1; +reg fp16_dout_4_in_rdy_d0; +reg fp16_dout_4_in_vld_d1; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? fp16_dout_4_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && fp16_dout_4_in_vld_d0)? fp16_dout_4_in_pd_d0[31:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or fp16_dout_4_in_rdy_d1 + or p1_pipe_data + ) begin + fp16_dout_4_in_vld_d1 = p1_pipe_valid; + p1_pipe_ready = fp16_dout_4_in_rdy_d1; + fp16_dout_4_in_pd_d1[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d1^fp16_dout_4_in_rdy_d1^fp16_dout_4_in_vld_d0^fp16_dout_4_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d0 && !fp16_dout_4_in_rdy_d0), (fp16_dout_4_in_vld_d0), (fp16_dout_4_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d2[31:0] (fp16_dout_4_in_vld_d2,fp16_dout_4_in_rdy_d2) <= fp16_dout_4_in_pd_d1[31:0] (fp16_dout_4_in_vld_d1,fp16_dout_4_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d1 + ,fp16_dout_4_in_rdy_d2 + ,fp16_dout_4_in_vld_d1 + ,fp16_dout_4_in_pd_d2 + ,fp16_dout_4_in_rdy_d1 + ,fp16_dout_4_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d1; +input fp16_dout_4_in_rdy_d2; +input fp16_dout_4_in_vld_d1; +output [31:0] fp16_dout_4_in_pd_d2; +output fp16_dout_4_in_rdy_d1; +output fp16_dout_4_in_vld_d2; +reg [31:0] fp16_dout_4_in_pd_d2; +reg fp16_dout_4_in_rdy_d1; +reg fp16_dout_4_in_vld_d2; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? fp16_dout_4_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && fp16_dout_4_in_vld_d1)? fp16_dout_4_in_pd_d1[31:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d1 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or fp16_dout_4_in_rdy_d2 + or p2_pipe_data + ) begin + fp16_dout_4_in_vld_d2 = p2_pipe_valid; + p2_pipe_ready = fp16_dout_4_in_rdy_d2; + fp16_dout_4_in_pd_d2[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d2^fp16_dout_4_in_rdy_d2^fp16_dout_4_in_vld_d1^fp16_dout_4_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d1 && !fp16_dout_4_in_rdy_d1), (fp16_dout_4_in_vld_d1), (fp16_dout_4_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d3[31:0] (fp16_dout_4_in_vld_d3,fp16_dout_4_in_rdy_d3) <= fp16_dout_4_in_pd_d2[31:0] (fp16_dout_4_in_vld_d2,fp16_dout_4_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d2 + ,fp16_dout_4_in_rdy_d3 + ,fp16_dout_4_in_vld_d2 + ,fp16_dout_4_in_pd_d3 + ,fp16_dout_4_in_rdy_d2 + ,fp16_dout_4_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d2; +input fp16_dout_4_in_rdy_d3; +input fp16_dout_4_in_vld_d2; +output [31:0] fp16_dout_4_in_pd_d3; +output fp16_dout_4_in_rdy_d2; +output fp16_dout_4_in_vld_d3; +reg [31:0] fp16_dout_4_in_pd_d3; +reg fp16_dout_4_in_rdy_d2; +reg fp16_dout_4_in_vld_d3; +reg [31:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? fp16_dout_4_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && fp16_dout_4_in_vld_d2)? fp16_dout_4_in_pd_d2[31:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d2 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or fp16_dout_4_in_rdy_d3 + or p3_pipe_data + ) begin + fp16_dout_4_in_vld_d3 = p3_pipe_valid; + p3_pipe_ready = fp16_dout_4_in_rdy_d3; + fp16_dout_4_in_pd_d3[31:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d3^fp16_dout_4_in_rdy_d3^fp16_dout_4_in_vld_d2^fp16_dout_4_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d2 && !fp16_dout_4_in_rdy_d2), (fp16_dout_4_in_vld_d2), (fp16_dout_4_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none fp16_dout_4_in_pd_d4[31:0] (fp16_dout_4_in_vld_d4,fp16_dout_4_in_rdy_d4) <= fp16_dout_4_in_pd_d3[31:0] (fp16_dout_4_in_vld_d3,fp16_dout_4_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,fp16_dout_4_in_pd_d3 + ,fp16_dout_4_in_rdy_d4 + ,fp16_dout_4_in_vld_d3 + ,fp16_dout_4_in_pd_d4 + ,fp16_dout_4_in_rdy_d3 + ,fp16_dout_4_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] fp16_dout_4_in_pd_d3; +input fp16_dout_4_in_rdy_d4; +input fp16_dout_4_in_vld_d3; +output [31:0] fp16_dout_4_in_pd_d4; +output fp16_dout_4_in_rdy_d3; +output fp16_dout_4_in_vld_d4; +reg [31:0] fp16_dout_4_in_pd_d4; +reg fp16_dout_4_in_rdy_d3; +reg fp16_dout_4_in_vld_d4; +reg [31:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? fp16_dout_4_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && fp16_dout_4_in_vld_d3)? fp16_dout_4_in_pd_d3[31:0] : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + fp16_dout_4_in_rdy_d3 = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or fp16_dout_4_in_rdy_d4 + or p4_pipe_data + ) begin + fp16_dout_4_in_vld_d4 = p4_pipe_valid; + p4_pipe_ready = fp16_dout_4_in_rdy_d4; + fp16_dout_4_in_pd_d4[31:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (fp16_dout_4_in_vld_d4^fp16_dout_4_in_rdy_d4^fp16_dout_4_in_vld_d3^fp16_dout_4_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (fp16_dout_4_in_vld_d3 && !fp16_dout_4_in_rdy_d3), (fp16_dout_4_in_vld_d3), (fp16_dout_4_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d1[95:0] (stage1_pipe_in_vld_d1,stage1_pipe_in_rdy_d1) <= stage1_pipe_in_pd_d0[95:0] (stage1_pipe_in_vld_d0,stage1_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d0 + ,stage1_pipe_in_rdy_d1 + ,stage1_pipe_in_vld_d0 + ,stage1_pipe_in_pd_d1 + ,stage1_pipe_in_rdy_d0 + ,stage1_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d0; +input stage1_pipe_in_rdy_d1; +input stage1_pipe_in_vld_d0; +output [95:0] stage1_pipe_in_pd_d1; +output stage1_pipe_in_rdy_d0; +output stage1_pipe_in_vld_d1; +reg [95:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d1; +reg stage1_pipe_in_rdy_d0; +reg stage1_pipe_in_vld_d1; +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? stage1_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && stage1_pipe_in_vld_d0)? stage1_pipe_in_pd_d0[95:0] : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d0 = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or stage1_pipe_in_rdy_d1 + or p5_pipe_data + ) begin + stage1_pipe_in_vld_d1 = p5_pipe_valid; + p5_pipe_ready = stage1_pipe_in_rdy_d1; + stage1_pipe_in_pd_d1[95:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d1^stage1_pipe_in_rdy_d1^stage1_pipe_in_vld_d0^stage1_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d0 && !stage1_pipe_in_rdy_d0), (stage1_pipe_in_vld_d0), (stage1_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d2[95:0] (stage1_pipe_in_vld_d2,stage1_pipe_in_rdy_d2) <= stage1_pipe_in_pd_d1[95:0] (stage1_pipe_in_vld_d1,stage1_pipe_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d1 + ,stage1_pipe_in_rdy_d2 + ,stage1_pipe_in_vld_d1 + ,stage1_pipe_in_pd_d2 + ,stage1_pipe_in_rdy_d1 + ,stage1_pipe_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d1; +input stage1_pipe_in_rdy_d2; +input stage1_pipe_in_vld_d1; +output [95:0] stage1_pipe_in_pd_d2; +output stage1_pipe_in_rdy_d1; +output stage1_pipe_in_vld_d2; +reg [95:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d2; +reg stage1_pipe_in_rdy_d1; +reg stage1_pipe_in_vld_d2; +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? stage1_pipe_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && stage1_pipe_in_vld_d1)? stage1_pipe_in_pd_d1[95:0] : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d1 = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or stage1_pipe_in_rdy_d2 + or p6_pipe_data + ) begin + stage1_pipe_in_vld_d2 = p6_pipe_valid; + p6_pipe_ready = stage1_pipe_in_rdy_d2; + stage1_pipe_in_pd_d2[95:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d2^stage1_pipe_in_rdy_d2^stage1_pipe_in_vld_d1^stage1_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d1 && !stage1_pipe_in_rdy_d1), (stage1_pipe_in_vld_d1), (stage1_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d3[95:0] (stage1_pipe_in_vld_d3,stage1_pipe_in_rdy_d3) <= stage1_pipe_in_pd_d2[95:0] (stage1_pipe_in_vld_d2,stage1_pipe_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d2 + ,stage1_pipe_in_rdy_d3 + ,stage1_pipe_in_vld_d2 + ,stage1_pipe_in_pd_d3 + ,stage1_pipe_in_rdy_d2 + ,stage1_pipe_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d2; +input stage1_pipe_in_rdy_d3; +input stage1_pipe_in_vld_d2; +output [95:0] stage1_pipe_in_pd_d3; +output stage1_pipe_in_rdy_d2; +output stage1_pipe_in_vld_d3; +reg [95:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d3; +reg stage1_pipe_in_rdy_d2; +reg stage1_pipe_in_vld_d3; +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? stage1_pipe_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && stage1_pipe_in_vld_d2)? stage1_pipe_in_pd_d2[95:0] : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d2 = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or stage1_pipe_in_rdy_d3 + or p7_pipe_data + ) begin + stage1_pipe_in_vld_d3 = p7_pipe_valid; + p7_pipe_ready = stage1_pipe_in_rdy_d3; + stage1_pipe_in_pd_d3[95:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d3^stage1_pipe_in_rdy_d3^stage1_pipe_in_vld_d2^stage1_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d2 && !stage1_pipe_in_rdy_d2), (stage1_pipe_in_vld_d2), (stage1_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p7 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage1_pipe_in_pd_d4[95:0] (stage1_pipe_in_vld_d4,stage1_pipe_in_rdy_d4) <= stage1_pipe_in_pd_d3[95:0] (stage1_pipe_in_vld_d3,stage1_pipe_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage1_pipe_in_pd_d3 + ,stage1_pipe_in_rdy_d4 + ,stage1_pipe_in_vld_d3 + ,stage1_pipe_in_pd_d4 + ,stage1_pipe_in_rdy_d3 + ,stage1_pipe_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [95:0] stage1_pipe_in_pd_d3; +input stage1_pipe_in_rdy_d4; +input stage1_pipe_in_vld_d3; +output [95:0] stage1_pipe_in_pd_d4; +output stage1_pipe_in_rdy_d3; +output stage1_pipe_in_vld_d4; +reg [95:0] p8_pipe_data; +reg p8_pipe_ready; +reg p8_pipe_ready_bc; +reg p8_pipe_valid; +reg [95:0] stage1_pipe_in_pd_d4; +reg stage1_pipe_in_rdy_d3; +reg stage1_pipe_in_vld_d4; +//## pipe (8) valid-ready-bubble-collapse +always @( + p8_pipe_ready + or p8_pipe_valid + ) begin + p8_pipe_ready_bc = p8_pipe_ready || !p8_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_pipe_valid <= 1'b0; + end else begin + p8_pipe_valid <= (p8_pipe_ready_bc)? stage1_pipe_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_pipe_data <= (p8_pipe_ready_bc && stage1_pipe_in_vld_d3)? stage1_pipe_in_pd_d3[95:0] : p8_pipe_data; +// VCS sop_coverage_off end +end +always @( + p8_pipe_ready_bc + ) begin + stage1_pipe_in_rdy_d3 = p8_pipe_ready_bc; +end +//## pipe (8) output +always @( + p8_pipe_valid + or stage1_pipe_in_rdy_d4 + or p8_pipe_data + ) begin + stage1_pipe_in_vld_d4 = p8_pipe_valid; + p8_pipe_ready = stage1_pipe_in_rdy_d4; + stage1_pipe_in_pd_d4[95:0] = p8_pipe_data; +end +//## pipe (8) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p8_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage1_pipe_in_vld_d4^stage1_pipe_in_rdy_d4^stage1_pipe_in_vld_d3^stage1_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (stage1_pipe_in_vld_d3 && !stage1_pipe_in_rdy_d3), (stage1_pipe_in_vld_d3), (stage1_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p8 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d1[63:0] (stage2_pipe_in_vld_d1,stage2_pipe_in_rdy_d1) <= stage2_pipe_in_pd_d0[63:0] (stage2_pipe_in_vld_d0,stage2_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p9 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d0 + ,stage2_pipe_in_rdy_d1 + ,stage2_pipe_in_vld_d0 + ,stage2_pipe_in_pd_d1 + ,stage2_pipe_in_rdy_d0 + ,stage2_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d0; +input stage2_pipe_in_rdy_d1; +input stage2_pipe_in_vld_d0; +output [63:0] stage2_pipe_in_pd_d1; +output stage2_pipe_in_rdy_d0; +output stage2_pipe_in_vld_d1; +reg [63:0] p9_pipe_data; +reg p9_pipe_ready; +reg p9_pipe_ready_bc; +reg p9_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d1; +reg stage2_pipe_in_rdy_d0; +reg stage2_pipe_in_vld_d1; +//## pipe (9) valid-ready-bubble-collapse +always @( + p9_pipe_ready + or p9_pipe_valid + ) begin + p9_pipe_ready_bc = p9_pipe_ready || !p9_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p9_pipe_valid <= 1'b0; + end else begin + p9_pipe_valid <= (p9_pipe_ready_bc)? stage2_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p9_pipe_data <= (p9_pipe_ready_bc && stage2_pipe_in_vld_d0)? stage2_pipe_in_pd_d0[63:0] : p9_pipe_data; +// VCS sop_coverage_off end +end +always @( + p9_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d0 = p9_pipe_ready_bc; +end +//## pipe (9) output +always @( + p9_pipe_valid + or stage2_pipe_in_rdy_d1 + or p9_pipe_data + ) begin + stage2_pipe_in_vld_d1 = p9_pipe_valid; + p9_pipe_ready = stage2_pipe_in_rdy_d1; + stage2_pipe_in_pd_d1[63:0] = p9_pipe_data; +end +//## pipe (9) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p9_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d1^stage2_pipe_in_rdy_d1^stage2_pipe_in_vld_d0^stage2_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_18x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d0 && !stage2_pipe_in_rdy_d0), (stage2_pipe_in_vld_d0), (stage2_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p9 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d2[63:0] (stage2_pipe_in_vld_d2,stage2_pipe_in_rdy_d2) <= stage2_pipe_in_pd_d1[63:0] (stage2_pipe_in_vld_d1,stage2_pipe_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p10 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d1 + ,stage2_pipe_in_rdy_d2 + ,stage2_pipe_in_vld_d1 + ,stage2_pipe_in_pd_d2 + ,stage2_pipe_in_rdy_d1 + ,stage2_pipe_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d1; +input stage2_pipe_in_rdy_d2; +input stage2_pipe_in_vld_d1; +output [63:0] stage2_pipe_in_pd_d2; +output stage2_pipe_in_rdy_d1; +output stage2_pipe_in_vld_d2; +reg [63:0] p10_pipe_data; +reg p10_pipe_ready; +reg p10_pipe_ready_bc; +reg p10_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d2; +reg stage2_pipe_in_rdy_d1; +reg stage2_pipe_in_vld_d2; +//## pipe (10) valid-ready-bubble-collapse +always @( + p10_pipe_ready + or p10_pipe_valid + ) begin + p10_pipe_ready_bc = p10_pipe_ready || !p10_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p10_pipe_valid <= 1'b0; + end else begin + p10_pipe_valid <= (p10_pipe_ready_bc)? stage2_pipe_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p10_pipe_data <= (p10_pipe_ready_bc && stage2_pipe_in_vld_d1)? stage2_pipe_in_pd_d1[63:0] : p10_pipe_data; +// VCS sop_coverage_off end +end +always @( + p10_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d1 = p10_pipe_ready_bc; +end +//## pipe (10) output +always @( + p10_pipe_valid + or stage2_pipe_in_rdy_d2 + or p10_pipe_data + ) begin + stage2_pipe_in_vld_d2 = p10_pipe_valid; + p10_pipe_ready = stage2_pipe_in_rdy_d2; + stage2_pipe_in_pd_d2[63:0] = p10_pipe_data; +end +//## pipe (10) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p10_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d2^stage2_pipe_in_rdy_d2^stage2_pipe_in_vld_d1^stage2_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_20x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d1 && !stage2_pipe_in_rdy_d1), (stage2_pipe_in_vld_d1), (stage2_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p10 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d3[63:0] (stage2_pipe_in_vld_d3,stage2_pipe_in_rdy_d3) <= stage2_pipe_in_pd_d2[63:0] (stage2_pipe_in_vld_d2,stage2_pipe_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p11 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d2 + ,stage2_pipe_in_rdy_d3 + ,stage2_pipe_in_vld_d2 + ,stage2_pipe_in_pd_d3 + ,stage2_pipe_in_rdy_d2 + ,stage2_pipe_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d2; +input stage2_pipe_in_rdy_d3; +input stage2_pipe_in_vld_d2; +output [63:0] stage2_pipe_in_pd_d3; +output stage2_pipe_in_rdy_d2; +output stage2_pipe_in_vld_d3; +reg [63:0] p11_pipe_data; +reg p11_pipe_ready; +reg p11_pipe_ready_bc; +reg p11_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d3; +reg stage2_pipe_in_rdy_d2; +reg stage2_pipe_in_vld_d3; +//## pipe (11) valid-ready-bubble-collapse +always @( + p11_pipe_ready + or p11_pipe_valid + ) begin + p11_pipe_ready_bc = p11_pipe_ready || !p11_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p11_pipe_valid <= 1'b0; + end else begin + p11_pipe_valid <= (p11_pipe_ready_bc)? stage2_pipe_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p11_pipe_data <= (p11_pipe_ready_bc && stage2_pipe_in_vld_d2)? stage2_pipe_in_pd_d2[63:0] : p11_pipe_data; +// VCS sop_coverage_off end +end +always @( + p11_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d2 = p11_pipe_ready_bc; +end +//## pipe (11) output +always @( + p11_pipe_valid + or stage2_pipe_in_rdy_d3 + or p11_pipe_data + ) begin + stage2_pipe_in_vld_d3 = p11_pipe_valid; + p11_pipe_ready = stage2_pipe_in_rdy_d3; + stage2_pipe_in_pd_d3[63:0] = p11_pipe_data; +end +//## pipe (11) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p11_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d3^stage2_pipe_in_rdy_d3^stage2_pipe_in_vld_d2^stage2_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_22x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d2 && !stage2_pipe_in_rdy_d2), (stage2_pipe_in_vld_d2), (stage2_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p11 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage2_pipe_in_pd_d4[63:0] (stage2_pipe_in_vld_d4,stage2_pipe_in_rdy_d4) <= stage2_pipe_in_pd_d3[63:0] (stage2_pipe_in_vld_d3,stage2_pipe_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p12 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage2_pipe_in_pd_d3 + ,stage2_pipe_in_rdy_d4 + ,stage2_pipe_in_vld_d3 + ,stage2_pipe_in_pd_d4 + ,stage2_pipe_in_rdy_d3 + ,stage2_pipe_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [63:0] stage2_pipe_in_pd_d3; +input stage2_pipe_in_rdy_d4; +input stage2_pipe_in_vld_d3; +output [63:0] stage2_pipe_in_pd_d4; +output stage2_pipe_in_rdy_d3; +output stage2_pipe_in_vld_d4; +reg [63:0] p12_pipe_data; +reg p12_pipe_ready; +reg p12_pipe_ready_bc; +reg p12_pipe_valid; +reg [63:0] stage2_pipe_in_pd_d4; +reg stage2_pipe_in_rdy_d3; +reg stage2_pipe_in_vld_d4; +//## pipe (12) valid-ready-bubble-collapse +always @( + p12_pipe_ready + or p12_pipe_valid + ) begin + p12_pipe_ready_bc = p12_pipe_ready || !p12_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p12_pipe_valid <= 1'b0; + end else begin + p12_pipe_valid <= (p12_pipe_ready_bc)? stage2_pipe_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p12_pipe_data <= (p12_pipe_ready_bc && stage2_pipe_in_vld_d3)? stage2_pipe_in_pd_d3[63:0] : p12_pipe_data; +// VCS sop_coverage_off end +end +always @( + p12_pipe_ready_bc + ) begin + stage2_pipe_in_rdy_d3 = p12_pipe_ready_bc; +end +//## pipe (12) output +always @( + p12_pipe_valid + or stage2_pipe_in_rdy_d4 + or p12_pipe_data + ) begin + stage2_pipe_in_vld_d4 = p12_pipe_valid; + p12_pipe_ready = stage2_pipe_in_rdy_d4; + stage2_pipe_in_pd_d4[63:0] = p12_pipe_data; +end +//## pipe (12) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p12_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage2_pipe_in_vld_d4^stage2_pipe_in_rdy_d4^stage2_pipe_in_vld_d3^stage2_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_24x (nvdla_core_clk, `ASSERT_RESET, (stage2_pipe_in_vld_d3 && !stage2_pipe_in_rdy_d3), (stage2_pipe_in_vld_d3), (stage2_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p12 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d1[31:0] (stage3_pipe_in_vld_d1,stage3_pipe_in_rdy_d1) <= stage3_pipe_in_pd_d0[31:0] (stage3_pipe_in_vld_d0,stage3_pipe_in_rdy_d0) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p13 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d0 + ,stage3_pipe_in_rdy_d1 + ,stage3_pipe_in_vld_d0 + ,stage3_pipe_in_pd_d1 + ,stage3_pipe_in_rdy_d0 + ,stage3_pipe_in_vld_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d0; +input stage3_pipe_in_rdy_d1; +input stage3_pipe_in_vld_d0; +output [31:0] stage3_pipe_in_pd_d1; +output stage3_pipe_in_rdy_d0; +output stage3_pipe_in_vld_d1; +reg [31:0] p13_pipe_data; +reg p13_pipe_ready; +reg p13_pipe_ready_bc; +reg p13_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d1; +reg stage3_pipe_in_rdy_d0; +reg stage3_pipe_in_vld_d1; +//## pipe (13) valid-ready-bubble-collapse +always @( + p13_pipe_ready + or p13_pipe_valid + ) begin + p13_pipe_ready_bc = p13_pipe_ready || !p13_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p13_pipe_valid <= 1'b0; + end else begin + p13_pipe_valid <= (p13_pipe_ready_bc)? stage3_pipe_in_vld_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p13_pipe_data <= (p13_pipe_ready_bc && stage3_pipe_in_vld_d0)? stage3_pipe_in_pd_d0[31:0] : p13_pipe_data; +// VCS sop_coverage_off end +end +always @( + p13_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d0 = p13_pipe_ready_bc; +end +//## pipe (13) output +always @( + p13_pipe_valid + or stage3_pipe_in_rdy_d1 + or p13_pipe_data + ) begin + stage3_pipe_in_vld_d1 = p13_pipe_valid; + p13_pipe_ready = stage3_pipe_in_rdy_d1; + stage3_pipe_in_pd_d1[31:0] = p13_pipe_data; +end +//## pipe (13) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p13_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d1^stage3_pipe_in_rdy_d1^stage3_pipe_in_vld_d0^stage3_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_26x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d0 && !stage3_pipe_in_rdy_d0), (stage3_pipe_in_vld_d0), (stage3_pipe_in_rdy_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p13 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d2[31:0] (stage3_pipe_in_vld_d2,stage3_pipe_in_rdy_d2) <= stage3_pipe_in_pd_d1[31:0] (stage3_pipe_in_vld_d1,stage3_pipe_in_rdy_d1) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p14 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d1 + ,stage3_pipe_in_rdy_d2 + ,stage3_pipe_in_vld_d1 + ,stage3_pipe_in_pd_d2 + ,stage3_pipe_in_rdy_d1 + ,stage3_pipe_in_vld_d2 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d1; +input stage3_pipe_in_rdy_d2; +input stage3_pipe_in_vld_d1; +output [31:0] stage3_pipe_in_pd_d2; +output stage3_pipe_in_rdy_d1; +output stage3_pipe_in_vld_d2; +reg [31:0] p14_pipe_data; +reg p14_pipe_ready; +reg p14_pipe_ready_bc; +reg p14_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d2; +reg stage3_pipe_in_rdy_d1; +reg stage3_pipe_in_vld_d2; +//## pipe (14) valid-ready-bubble-collapse +always @( + p14_pipe_ready + or p14_pipe_valid + ) begin + p14_pipe_ready_bc = p14_pipe_ready || !p14_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p14_pipe_valid <= 1'b0; + end else begin + p14_pipe_valid <= (p14_pipe_ready_bc)? stage3_pipe_in_vld_d1 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p14_pipe_data <= (p14_pipe_ready_bc && stage3_pipe_in_vld_d1)? stage3_pipe_in_pd_d1[31:0] : p14_pipe_data; +// VCS sop_coverage_off end +end +always @( + p14_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d1 = p14_pipe_ready_bc; +end +//## pipe (14) output +always @( + p14_pipe_valid + or stage3_pipe_in_rdy_d2 + or p14_pipe_data + ) begin + stage3_pipe_in_vld_d2 = p14_pipe_valid; + p14_pipe_ready = stage3_pipe_in_rdy_d2; + stage3_pipe_in_pd_d2[31:0] = p14_pipe_data; +end +//## pipe (14) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p14_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d2^stage3_pipe_in_rdy_d2^stage3_pipe_in_vld_d1^stage3_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_28x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d1 && !stage3_pipe_in_rdy_d1), (stage3_pipe_in_vld_d1), (stage3_pipe_in_rdy_d1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p14 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d3[31:0] (stage3_pipe_in_vld_d3,stage3_pipe_in_rdy_d3) <= stage3_pipe_in_pd_d2[31:0] (stage3_pipe_in_vld_d2,stage3_pipe_in_rdy_d2) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p15 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d2 + ,stage3_pipe_in_rdy_d3 + ,stage3_pipe_in_vld_d2 + ,stage3_pipe_in_pd_d3 + ,stage3_pipe_in_rdy_d2 + ,stage3_pipe_in_vld_d3 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d2; +input stage3_pipe_in_rdy_d3; +input stage3_pipe_in_vld_d2; +output [31:0] stage3_pipe_in_pd_d3; +output stage3_pipe_in_rdy_d2; +output stage3_pipe_in_vld_d3; +reg [31:0] p15_pipe_data; +reg p15_pipe_ready; +reg p15_pipe_ready_bc; +reg p15_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d3; +reg stage3_pipe_in_rdy_d2; +reg stage3_pipe_in_vld_d3; +//## pipe (15) valid-ready-bubble-collapse +always @( + p15_pipe_ready + or p15_pipe_valid + ) begin + p15_pipe_ready_bc = p15_pipe_ready || !p15_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p15_pipe_valid <= 1'b0; + end else begin + p15_pipe_valid <= (p15_pipe_ready_bc)? stage3_pipe_in_vld_d2 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p15_pipe_data <= (p15_pipe_ready_bc && stage3_pipe_in_vld_d2)? stage3_pipe_in_pd_d2[31:0] : p15_pipe_data; +// VCS sop_coverage_off end +end +always @( + p15_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d2 = p15_pipe_ready_bc; +end +//## pipe (15) output +always @( + p15_pipe_valid + or stage3_pipe_in_rdy_d3 + or p15_pipe_data + ) begin + stage3_pipe_in_vld_d3 = p15_pipe_valid; + p15_pipe_ready = stage3_pipe_in_rdy_d3; + stage3_pipe_in_pd_d3[31:0] = p15_pipe_data; +end +//## pipe (15) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p15_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d3^stage3_pipe_in_rdy_d3^stage3_pipe_in_vld_d2^stage3_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_30x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d2 && !stage3_pipe_in_rdy_d2), (stage3_pipe_in_vld_d2), (stage3_pipe_in_rdy_d2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p15 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none stage3_pipe_in_pd_d4[31:0] (stage3_pipe_in_vld_d4,stage3_pipe_in_rdy_d4) <= stage3_pipe_in_pd_d3[31:0] (stage3_pipe_in_vld_d3,stage3_pipe_in_rdy_d3) +// ************************************************************************************************************** +module FP_SUM_BLOCK_pipe_p16 ( + nvdla_core_clk + ,nvdla_core_rstn + ,stage3_pipe_in_pd_d3 + ,stage3_pipe_in_rdy_d4 + ,stage3_pipe_in_vld_d3 + ,stage3_pipe_in_pd_d4 + ,stage3_pipe_in_rdy_d3 + ,stage3_pipe_in_vld_d4 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] stage3_pipe_in_pd_d3; +input stage3_pipe_in_rdy_d4; +input stage3_pipe_in_vld_d3; +output [31:0] stage3_pipe_in_pd_d4; +output stage3_pipe_in_rdy_d3; +output stage3_pipe_in_vld_d4; +reg [31:0] p16_pipe_data; +reg p16_pipe_ready; +reg p16_pipe_ready_bc; +reg p16_pipe_valid; +reg [31:0] stage3_pipe_in_pd_d4; +reg stage3_pipe_in_rdy_d3; +reg stage3_pipe_in_vld_d4; +//## pipe (16) valid-ready-bubble-collapse +always @( + p16_pipe_ready + or p16_pipe_valid + ) begin + p16_pipe_ready_bc = p16_pipe_ready || !p16_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p16_pipe_valid <= 1'b0; + end else begin + p16_pipe_valid <= (p16_pipe_ready_bc)? stage3_pipe_in_vld_d3 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p16_pipe_data <= (p16_pipe_ready_bc && stage3_pipe_in_vld_d3)? stage3_pipe_in_pd_d3[31:0] : p16_pipe_data; +// VCS sop_coverage_off end +end +always @( + p16_pipe_ready_bc + ) begin + stage3_pipe_in_rdy_d3 = p16_pipe_ready_bc; +end +//## pipe (16) output +always @( + p16_pipe_valid + or stage3_pipe_in_rdy_d4 + or p16_pipe_data + ) begin + stage3_pipe_in_vld_d4 = p16_pipe_valid; + p16_pipe_ready = stage3_pipe_in_rdy_d4; + stage3_pipe_in_pd_d4[31:0] = p16_pipe_data; +end +//## pipe (16) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p16_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (stage3_pipe_in_vld_d4^stage3_pipe_in_rdy_d4^stage3_pipe_in_vld_d3^stage3_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_32x (nvdla_core_clk, `ASSERT_RESET, (stage3_pipe_in_vld_d3 && !stage3_pipe_in_rdy_d3), (stage3_pipe_in_vld_d3), (stage3_pipe_in_rdy_d3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // FP_SUM_BLOCK_pipe_p16 diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block.v b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block.v new file mode 100644 index 0000000..c25a08a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block.v @@ -0,0 +1,1243 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: int_sum_block.v +module int_sum_block ( + nvdla_core_clk + ,nvdla_core_rstn + ,len5 + ,len7 + ,len9 + ,load_din_2d + ,load_din_d + ,reg2dp_normalz_len + ,sq_pd_int8_lsb_0 + ,sq_pd_int8_lsb_1 + ,sq_pd_int8_lsb_2 + ,sq_pd_int8_lsb_3 + ,sq_pd_int8_lsb_4 + ,sq_pd_int8_lsb_5 + ,sq_pd_int8_lsb_6 + ,sq_pd_int8_lsb_7 + ,sq_pd_int8_lsb_8 + ,sq_pd_int8_msb_0 + ,sq_pd_int8_msb_1 + ,sq_pd_int8_msb_2 + ,sq_pd_int8_msb_3 + ,sq_pd_int8_msb_4 + ,sq_pd_int8_msb_5 + ,sq_pd_int8_msb_6 + ,sq_pd_int8_msb_7 + ,sq_pd_int8_msb_8 + ,int8_sum + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input len5; +input len7; +input len9; +input load_din_2d; +input load_din_d; +input [1:0] reg2dp_normalz_len; +input [16:0] sq_pd_int8_lsb_0; +input [16:0] sq_pd_int8_lsb_1; +input [16:0] sq_pd_int8_lsb_2; +input [16:0] sq_pd_int8_lsb_3; +input [16:0] sq_pd_int8_lsb_4; +input [16:0] sq_pd_int8_lsb_5; +input [16:0] sq_pd_int8_lsb_6; +input [16:0] sq_pd_int8_lsb_7; +input [16:0] sq_pd_int8_lsb_8; +input [16:0] sq_pd_int8_msb_0; +input [16:0] sq_pd_int8_msb_1; +input [16:0] sq_pd_int8_msb_2; +input [16:0] sq_pd_int8_msb_3; +input [16:0] sq_pd_int8_msb_4; +input [16:0] sq_pd_int8_msb_5; +input [16:0] sq_pd_int8_msb_6; +input [16:0] sq_pd_int8_msb_7; +input [16:0] sq_pd_int8_msb_8; +output [41:0] int8_sum; +reg [34:0] int16_sum3; +reg [35:0] int16_sum5; +reg [35:0] int16_sum7; +reg [36:0] int16_sum9; +reg [33:0] int16_sum_0_8; +reg [33:0] int16_sum_1_7; +reg [33:0] int16_sum_2_6; +reg [33:0] int16_sum_3_5; +reg [20:0] int8_lsb_sum; +reg [20:0] int8_msb_sum; +reg [18:0] int8_msb_sum3; +reg [19:0] int8_msb_sum5; +reg [19:0] int8_msb_sum7; +reg [20:0] int8_msb_sum9; +reg [17:0] int8_msb_sum_0_8; +reg [17:0] int8_msb_sum_1_7; +reg [17:0] int8_msb_sum_2_6; +reg [17:0] int8_msb_sum_3_5; +reg [32:0] sq4_d; +reg [16:0] sq_pd_int8_msb_4_d; +wire [18:0] int8_lsb_sum3; +wire [19:0] int8_lsb_sum5; +wire [19:0] int8_lsb_sum7; +wire [20:0] int8_lsb_sum9; +wire [32:0] sq0; +wire [32:0] sq1; +wire [32:0] sq2; +wire [32:0] sq3; +wire [32:0] sq5; +wire [32:0] sq6; +wire [32:0] sq7; +wire [32:0] sq8; +assign sq3[32:0] = {16'd0,sq_pd_int8_lsb_3[16:0]}; +assign sq5[32:0] = {16'd0,sq_pd_int8_lsb_5[16:0]}; +assign sq2[32:0] = {16'd0,sq_pd_int8_lsb_2[16:0]}; +assign sq6[32:0] = {16'd0,sq_pd_int8_lsb_6[16:0]}; +assign sq1[32:0] = {16'd0,sq_pd_int8_lsb_1[16:0]}; +assign sq7[32:0] = {16'd0,sq_pd_int8_lsb_7[16:0]}; +assign sq0[32:0] = {16'd0,sq_pd_int8_lsb_0[16:0]}; +assign sq8[32:0] = {16'd0,sq_pd_int8_lsb_8[16:0]}; +//sum process +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_3_5 <= {18{1'b0}}; + end else begin + if ((load_din_d ) == 1'b1) begin + int8_msb_sum_3_5 <= (sq_pd_int8_msb_3[16:0] + sq_pd_int8_msb_5[16:0]); +// VCS coverage off + end else if ((load_din_d ) == 1'b0) begin + end else begin + int8_msb_sum_3_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_2_6 <= {18{1'b0}}; + end else begin + if ((load_din_d & (len5|len7|len9)) == 1'b1) begin + int8_msb_sum_2_6 <= (sq_pd_int8_msb_2[16:0] + sq_pd_int8_msb_6[16:0]); +// VCS coverage off + end else if ((load_din_d & (len5|len7|len9)) == 1'b0) begin + end else begin + int8_msb_sum_2_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_1_7 <= {18{1'b0}}; + end else begin + if ((load_din_d & (len7|len9) ) == 1'b1) begin + int8_msb_sum_1_7 <= (sq_pd_int8_msb_1[16:0] + sq_pd_int8_msb_7[16:0]); +// VCS coverage off + end else if ((load_din_d & (len7|len9) ) == 1'b0) begin + end else begin + int8_msb_sum_1_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_0_8 <= {18{1'b0}}; + end else begin + if ((load_din_d & (len9) ) == 1'b1) begin + int8_msb_sum_0_8 <= (sq_pd_int8_msb_0[16:0] + sq_pd_int8_msb_8[16:0]); +// VCS coverage off + end else if ((load_din_d & (len9) ) == 1'b0) begin + end else begin + int8_msb_sum_0_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_3_5 <= {34{1'b0}}; + end else begin + if ((load_din_d ) == 1'b1) begin + int16_sum_3_5 <= (sq3[32:0] + sq5[32:0]); +// VCS coverage off + end else if ((load_din_d ) == 1'b0) begin + end else begin + int16_sum_3_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_2_6 <= {34{1'b0}}; + end else begin + if ((load_din_d & (len5|len7|len9)) == 1'b1) begin + int16_sum_2_6 <= (sq2[32:0] + sq6[32:0]); +// VCS coverage off + end else if ((load_din_d & (len5|len7|len9)) == 1'b0) begin + end else begin + int16_sum_2_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_1_7 <= {34{1'b0}}; + end else begin + if ((load_din_d & (len7|len9) ) == 1'b1) begin + int16_sum_1_7 <= (sq1[32:0] + sq7[32:0]); +// VCS coverage off + end else if ((load_din_d & (len7|len9) ) == 1'b0) begin + end else begin + int16_sum_1_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_0_8 <= {34{1'b0}}; + end else begin + if ((load_din_d & (len9) ) == 1'b1) begin + int16_sum_0_8 <= (sq0[32:0] + sq8[32:0]); +// VCS coverage off + end else if ((load_din_d & (len9) ) == 1'b0) begin + end else begin + int16_sum_0_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sq4_d[32:0] <= {33{1'b0}}; + end else begin + if ((load_din_d) == 1'b1) begin + sq4_d[32:0] <= {16'd0,sq_pd_int8_lsb_4[16:0]}; +// VCS coverage off + end else if ((load_din_d) == 1'b0) begin + end else begin + sq4_d[32:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sq_pd_int8_msb_4_d[16:0] <= {17{1'b0}}; + end else begin + if ((load_din_d) == 1'b1) begin + sq_pd_int8_msb_4_d[16:0] <= sq_pd_int8_msb_4[16:0]; +// VCS coverage off + end else if ((load_din_d) == 1'b0) begin + end else begin + sq_pd_int8_msb_4_d[16:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign int8_lsb_sum3 = int16_sum3[18:0]; +assign int8_lsb_sum5 = int16_sum5[19:0]; +assign int8_lsb_sum7 = int16_sum7[19:0]; +assign int8_lsb_sum9 = int16_sum9[20:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum3[18:0] <= {19{1'b0}}; + end else begin + if ((load_din_2d ) == 1'b1) begin + int8_msb_sum3[18:0] <= (int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}); +// VCS coverage off + end else if ((load_din_2d ) == 1'b0) begin + end else begin + int8_msb_sum3[18:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum5[19:0] <= {20{1'b0}}; + end else begin + if ((load_din_2d &(len5|len7|len9)) == 1'b1) begin + int8_msb_sum5[19:0] <= ((int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}) + {1'b0,int8_msb_sum_2_6[17:0]}); +// VCS coverage off + end else if ((load_din_2d &(len5|len7|len9)) == 1'b0) begin + end else begin + int8_msb_sum5[19:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum7[19:0] <= {20{1'b0}}; + end else begin + if ((load_din_2d &(len7|len9) ) == 1'b1) begin + int8_msb_sum7[19:0] <= ((int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}) + (int8_msb_sum_2_6[17:0] + int8_msb_sum_1_7[17:0])); +// VCS coverage off + end else if ((load_din_2d &(len7|len9) ) == 1'b0) begin + end else begin + int8_msb_sum7[19:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum9[20:0] <= {21{1'b0}}; + end else begin + if ((load_din_2d &(len9) ) == 1'b1) begin + int8_msb_sum9[20:0] <= (((int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}) + (int8_msb_sum_2_6[17:0] + int8_msb_sum_1_7[17:0])) + {2'd0,int8_msb_sum_0_8[17:0]}); +// VCS coverage off + end else if ((load_din_2d &(len9) ) == 1'b0) begin + end else begin + int8_msb_sum9[20:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum3[34:0] <= {35{1'b0}}; + end else begin + if ((load_din_2d ) == 1'b1) begin + int16_sum3[34:0] <= (int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}); +// VCS coverage off + end else if ((load_din_2d ) == 1'b0) begin + end else begin + int16_sum3[34:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum5[35:0] <= {36{1'b0}}; + end else begin + if ((load_din_2d &(len5|len7|len9)) == 1'b1) begin + int16_sum5[35:0] <= ((int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}) + {1'b0,int16_sum_2_6[33:0]}); +// VCS coverage off + end else if ((load_din_2d &(len5|len7|len9)) == 1'b0) begin + end else begin + int16_sum5[35:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum7[35:0] <= {36{1'b0}}; + end else begin + if ((load_din_2d &(len7|len9) ) == 1'b1) begin + int16_sum7[35:0] <= ((int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}) + (int16_sum_2_6[33:0] + int16_sum_1_7[33:0])); +// VCS coverage off + end else if ((load_din_2d &(len7|len9) ) == 1'b0) begin + end else begin + int16_sum7[35:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum9[36:0] <= {37{1'b0}}; + end else begin + if ((load_din_2d &(len9) ) == 1'b1) begin + int16_sum9[36:0] <= (((int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}) + (int16_sum_2_6[33:0] + int16_sum_1_7[33:0])) + {2'd0,int16_sum_0_8[33:0]}); +// VCS coverage off + end else if ((load_din_2d &(len9) ) == 1'b0) begin + end else begin + int16_sum9[36:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + reg2dp_normalz_len + or int8_lsb_sum3 + or int8_msb_sum3 + or int16_sum3 + or int8_lsb_sum5 + or int8_msb_sum5 + or int16_sum5 + or int8_lsb_sum7 + or int8_msb_sum7 + or int16_sum7 + or int8_lsb_sum9 + or int8_msb_sum9 + or int16_sum9 + ) begin + case(reg2dp_normalz_len[1:0]) + 2'h0 : begin + int8_lsb_sum = {2'd0,int8_lsb_sum3}; + int8_msb_sum = {2'd0,int8_msb_sum3}; + end + 2'h1 : begin + int8_lsb_sum = {1'd0,int8_lsb_sum5}; + int8_msb_sum = {1'd0,int8_msb_sum5}; + end + 2'h2 : begin + int8_lsb_sum = {1'b0,int8_lsb_sum7}; + int8_msb_sum = {1'b0,int8_msb_sum7}; + end + default: begin + int8_lsb_sum = int8_lsb_sum9[20:0]; + int8_msb_sum = int8_msb_sum9[20:0]; + end + endcase +end +assign int8_sum = {int8_msb_sum,int8_lsb_sum}; +endmodule // int_sum_block diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block.v.vcp new file mode 100644 index 0000000..c25a08a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block.v.vcp @@ -0,0 +1,1243 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: int_sum_block.v +module int_sum_block ( + nvdla_core_clk + ,nvdla_core_rstn + ,len5 + ,len7 + ,len9 + ,load_din_2d + ,load_din_d + ,reg2dp_normalz_len + ,sq_pd_int8_lsb_0 + ,sq_pd_int8_lsb_1 + ,sq_pd_int8_lsb_2 + ,sq_pd_int8_lsb_3 + ,sq_pd_int8_lsb_4 + ,sq_pd_int8_lsb_5 + ,sq_pd_int8_lsb_6 + ,sq_pd_int8_lsb_7 + ,sq_pd_int8_lsb_8 + ,sq_pd_int8_msb_0 + ,sq_pd_int8_msb_1 + ,sq_pd_int8_msb_2 + ,sq_pd_int8_msb_3 + ,sq_pd_int8_msb_4 + ,sq_pd_int8_msb_5 + ,sq_pd_int8_msb_6 + ,sq_pd_int8_msb_7 + ,sq_pd_int8_msb_8 + ,int8_sum + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input len5; +input len7; +input len9; +input load_din_2d; +input load_din_d; +input [1:0] reg2dp_normalz_len; +input [16:0] sq_pd_int8_lsb_0; +input [16:0] sq_pd_int8_lsb_1; +input [16:0] sq_pd_int8_lsb_2; +input [16:0] sq_pd_int8_lsb_3; +input [16:0] sq_pd_int8_lsb_4; +input [16:0] sq_pd_int8_lsb_5; +input [16:0] sq_pd_int8_lsb_6; +input [16:0] sq_pd_int8_lsb_7; +input [16:0] sq_pd_int8_lsb_8; +input [16:0] sq_pd_int8_msb_0; +input [16:0] sq_pd_int8_msb_1; +input [16:0] sq_pd_int8_msb_2; +input [16:0] sq_pd_int8_msb_3; +input [16:0] sq_pd_int8_msb_4; +input [16:0] sq_pd_int8_msb_5; +input [16:0] sq_pd_int8_msb_6; +input [16:0] sq_pd_int8_msb_7; +input [16:0] sq_pd_int8_msb_8; +output [41:0] int8_sum; +reg [34:0] int16_sum3; +reg [35:0] int16_sum5; +reg [35:0] int16_sum7; +reg [36:0] int16_sum9; +reg [33:0] int16_sum_0_8; +reg [33:0] int16_sum_1_7; +reg [33:0] int16_sum_2_6; +reg [33:0] int16_sum_3_5; +reg [20:0] int8_lsb_sum; +reg [20:0] int8_msb_sum; +reg [18:0] int8_msb_sum3; +reg [19:0] int8_msb_sum5; +reg [19:0] int8_msb_sum7; +reg [20:0] int8_msb_sum9; +reg [17:0] int8_msb_sum_0_8; +reg [17:0] int8_msb_sum_1_7; +reg [17:0] int8_msb_sum_2_6; +reg [17:0] int8_msb_sum_3_5; +reg [32:0] sq4_d; +reg [16:0] sq_pd_int8_msb_4_d; +wire [18:0] int8_lsb_sum3; +wire [19:0] int8_lsb_sum5; +wire [19:0] int8_lsb_sum7; +wire [20:0] int8_lsb_sum9; +wire [32:0] sq0; +wire [32:0] sq1; +wire [32:0] sq2; +wire [32:0] sq3; +wire [32:0] sq5; +wire [32:0] sq6; +wire [32:0] sq7; +wire [32:0] sq8; +assign sq3[32:0] = {16'd0,sq_pd_int8_lsb_3[16:0]}; +assign sq5[32:0] = {16'd0,sq_pd_int8_lsb_5[16:0]}; +assign sq2[32:0] = {16'd0,sq_pd_int8_lsb_2[16:0]}; +assign sq6[32:0] = {16'd0,sq_pd_int8_lsb_6[16:0]}; +assign sq1[32:0] = {16'd0,sq_pd_int8_lsb_1[16:0]}; +assign sq7[32:0] = {16'd0,sq_pd_int8_lsb_7[16:0]}; +assign sq0[32:0] = {16'd0,sq_pd_int8_lsb_0[16:0]}; +assign sq8[32:0] = {16'd0,sq_pd_int8_lsb_8[16:0]}; +//sum process +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_3_5 <= {18{1'b0}}; + end else begin + if ((load_din_d ) == 1'b1) begin + int8_msb_sum_3_5 <= (sq_pd_int8_msb_3[16:0] + sq_pd_int8_msb_5[16:0]); +// VCS coverage off + end else if ((load_din_d ) == 1'b0) begin + end else begin + int8_msb_sum_3_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_2_6 <= {18{1'b0}}; + end else begin + if ((load_din_d & (len5|len7|len9)) == 1'b1) begin + int8_msb_sum_2_6 <= (sq_pd_int8_msb_2[16:0] + sq_pd_int8_msb_6[16:0]); +// VCS coverage off + end else if ((load_din_d & (len5|len7|len9)) == 1'b0) begin + end else begin + int8_msb_sum_2_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_1_7 <= {18{1'b0}}; + end else begin + if ((load_din_d & (len7|len9) ) == 1'b1) begin + int8_msb_sum_1_7 <= (sq_pd_int8_msb_1[16:0] + sq_pd_int8_msb_7[16:0]); +// VCS coverage off + end else if ((load_din_d & (len7|len9) ) == 1'b0) begin + end else begin + int8_msb_sum_1_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum_0_8 <= {18{1'b0}}; + end else begin + if ((load_din_d & (len9) ) == 1'b1) begin + int8_msb_sum_0_8 <= (sq_pd_int8_msb_0[16:0] + sq_pd_int8_msb_8[16:0]); +// VCS coverage off + end else if ((load_din_d & (len9) ) == 1'b0) begin + end else begin + int8_msb_sum_0_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_3_5 <= {34{1'b0}}; + end else begin + if ((load_din_d ) == 1'b1) begin + int16_sum_3_5 <= (sq3[32:0] + sq5[32:0]); +// VCS coverage off + end else if ((load_din_d ) == 1'b0) begin + end else begin + int16_sum_3_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_2_6 <= {34{1'b0}}; + end else begin + if ((load_din_d & (len5|len7|len9)) == 1'b1) begin + int16_sum_2_6 <= (sq2[32:0] + sq6[32:0]); +// VCS coverage off + end else if ((load_din_d & (len5|len7|len9)) == 1'b0) begin + end else begin + int16_sum_2_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_1_7 <= {34{1'b0}}; + end else begin + if ((load_din_d & (len7|len9) ) == 1'b1) begin + int16_sum_1_7 <= (sq1[32:0] + sq7[32:0]); +// VCS coverage off + end else if ((load_din_d & (len7|len9) ) == 1'b0) begin + end else begin + int16_sum_1_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum_0_8 <= {34{1'b0}}; + end else begin + if ((load_din_d & (len9) ) == 1'b1) begin + int16_sum_0_8 <= (sq0[32:0] + sq8[32:0]); +// VCS coverage off + end else if ((load_din_d & (len9) ) == 1'b0) begin + end else begin + int16_sum_0_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d & (len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sq4_d[32:0] <= {33{1'b0}}; + end else begin + if ((load_din_d) == 1'b1) begin + sq4_d[32:0] <= {16'd0,sq_pd_int8_lsb_4[16:0]}; +// VCS coverage off + end else if ((load_din_d) == 1'b0) begin + end else begin + sq4_d[32:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sq_pd_int8_msb_4_d[16:0] <= {17{1'b0}}; + end else begin + if ((load_din_d) == 1'b1) begin + sq_pd_int8_msb_4_d[16:0] <= sq_pd_int8_msb_4[16:0]; +// VCS coverage off + end else if ((load_din_d) == 1'b0) begin + end else begin + sq_pd_int8_msb_4_d[16:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_d))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign int8_lsb_sum3 = int16_sum3[18:0]; +assign int8_lsb_sum5 = int16_sum5[19:0]; +assign int8_lsb_sum7 = int16_sum7[19:0]; +assign int8_lsb_sum9 = int16_sum9[20:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum3[18:0] <= {19{1'b0}}; + end else begin + if ((load_din_2d ) == 1'b1) begin + int8_msb_sum3[18:0] <= (int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}); +// VCS coverage off + end else if ((load_din_2d ) == 1'b0) begin + end else begin + int8_msb_sum3[18:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum5[19:0] <= {20{1'b0}}; + end else begin + if ((load_din_2d &(len5|len7|len9)) == 1'b1) begin + int8_msb_sum5[19:0] <= ((int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}) + {1'b0,int8_msb_sum_2_6[17:0]}); +// VCS coverage off + end else if ((load_din_2d &(len5|len7|len9)) == 1'b0) begin + end else begin + int8_msb_sum5[19:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum7[19:0] <= {20{1'b0}}; + end else begin + if ((load_din_2d &(len7|len9) ) == 1'b1) begin + int8_msb_sum7[19:0] <= ((int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}) + (int8_msb_sum_2_6[17:0] + int8_msb_sum_1_7[17:0])); +// VCS coverage off + end else if ((load_din_2d &(len7|len9) ) == 1'b0) begin + end else begin + int8_msb_sum7[19:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_msb_sum9[20:0] <= {21{1'b0}}; + end else begin + if ((load_din_2d &(len9) ) == 1'b1) begin + int8_msb_sum9[20:0] <= (((int8_msb_sum_3_5[17:0] + {1'b0,sq_pd_int8_msb_4_d[16:0]}) + (int8_msb_sum_2_6[17:0] + int8_msb_sum_1_7[17:0])) + {2'd0,int8_msb_sum_0_8[17:0]}); +// VCS coverage off + end else if ((load_din_2d &(len9) ) == 1'b0) begin + end else begin + int8_msb_sum9[20:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum3[34:0] <= {35{1'b0}}; + end else begin + if ((load_din_2d ) == 1'b1) begin + int16_sum3[34:0] <= (int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}); +// VCS coverage off + end else if ((load_din_2d ) == 1'b0) begin + end else begin + int16_sum3[34:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum5[35:0] <= {36{1'b0}}; + end else begin + if ((load_din_2d &(len5|len7|len9)) == 1'b1) begin + int16_sum5[35:0] <= ((int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}) + {1'b0,int16_sum_2_6[33:0]}); +// VCS coverage off + end else if ((load_din_2d &(len5|len7|len9)) == 1'b0) begin + end else begin + int16_sum5[35:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len5|len7|len9)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum7[35:0] <= {36{1'b0}}; + end else begin + if ((load_din_2d &(len7|len9) ) == 1'b1) begin + int16_sum7[35:0] <= ((int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}) + (int16_sum_2_6[33:0] + int16_sum_1_7[33:0])); +// VCS coverage off + end else if ((load_din_2d &(len7|len9) ) == 1'b0) begin + end else begin + int16_sum7[35:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len7|len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int16_sum9[36:0] <= {37{1'b0}}; + end else begin + if ((load_din_2d &(len9) ) == 1'b1) begin + int16_sum9[36:0] <= (((int16_sum_3_5[33:0] + {1'b0,sq4_d[32:0]}) + (int16_sum_2_6[33:0] + int16_sum_1_7[33:0])) + {2'd0,int16_sum_0_8[33:0]}); +// VCS coverage off + end else if ((load_din_2d &(len9) ) == 1'b0) begin + end else begin + int16_sum9[36:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_2d &(len9) ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + reg2dp_normalz_len + or int8_lsb_sum3 + or int8_msb_sum3 + or int16_sum3 + or int8_lsb_sum5 + or int8_msb_sum5 + or int16_sum5 + or int8_lsb_sum7 + or int8_msb_sum7 + or int16_sum7 + or int8_lsb_sum9 + or int8_msb_sum9 + or int16_sum9 + ) begin + case(reg2dp_normalz_len[1:0]) + 2'h0 : begin + int8_lsb_sum = {2'd0,int8_lsb_sum3}; + int8_msb_sum = {2'd0,int8_msb_sum3}; + end + 2'h1 : begin + int8_lsb_sum = {1'd0,int8_lsb_sum5}; + int8_msb_sum = {1'd0,int8_msb_sum5}; + end + 2'h2 : begin + int8_lsb_sum = {1'b0,int8_lsb_sum7}; + int8_msb_sum = {1'b0,int8_msb_sum7}; + end + default: begin + int8_lsb_sum = int8_lsb_sum9[20:0]; + int8_msb_sum = int8_msb_sum9[20:0]; + end + endcase +end +assign int8_sum = {int8_msb_sum,int8_lsb_sum}; +endmodule // int_sum_block diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block_tp1.v b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block_tp1.v new file mode 100644 index 0000000..d986f17 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block_tp1.v @@ -0,0 +1,158 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: int_sum_block_tp1.v +module int_sum_block_tp1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,len5 + ,len7 + ,len9 + ,load_din_2d + ,load_din_d + ,reg2dp_normalz_len + ,sq_pd_int8_0 + ,sq_pd_int8_1 + ,sq_pd_int8_2 + ,sq_pd_int8_3 + ,sq_pd_int8_4 + ,sq_pd_int8_5 + ,sq_pd_int8_6 + ,sq_pd_int8_7 + ,sq_pd_int8_8 + ,int8_sum + ); +///////////////////////////////////////////// +parameter pINT8_BW = 9; +///////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input len5; +input len7; +input len9; +input load_din_2d; +input load_din_d; +input [1:0] reg2dp_normalz_len; +input [pINT8_BW*2-2:0] sq_pd_int8_0; +input [pINT8_BW*2-2:0] sq_pd_int8_1; +input [pINT8_BW*2-2:0] sq_pd_int8_2; +input [pINT8_BW*2-2:0] sq_pd_int8_3; +input [pINT8_BW*2-2:0] sq_pd_int8_4; +input [pINT8_BW*2-2:0] sq_pd_int8_5; +input [pINT8_BW*2-2:0] sq_pd_int8_6; +input [pINT8_BW*2-2:0] sq_pd_int8_7; +input [pINT8_BW*2-2:0] sq_pd_int8_8; +output [pINT8_BW*2+2:0] int8_sum; +///////////////////////////////////////////// +reg [pINT8_BW*2+2:0] int8_sum; +reg [pINT8_BW*2:0] int8_sum3; +reg [pINT8_BW*2+1:0] int8_sum5; +reg [pINT8_BW*2+1:0] int8_sum7; +reg [pINT8_BW*2+2:0] int8_sum9; +reg [pINT8_BW*2-1:0] int8_sum_0_8; +reg [pINT8_BW*2-1:0] int8_sum_1_7; +reg [pINT8_BW*2-1:0] int8_sum_2_6; +reg [pINT8_BW*2-1:0] int8_sum_3_5; +reg [pINT8_BW*2-2:0] sq_pd_int8_4_d; +wire [pINT8_BW*2-2:0] sq0; +wire [pINT8_BW*2-2:0] sq1; +wire [pINT8_BW*2-2:0] sq2; +wire [pINT8_BW*2-2:0] sq3; +wire [pINT8_BW*2-2:0] sq5; +wire [pINT8_BW*2-2:0] sq6; +wire [pINT8_BW*2-2:0] sq7; +wire [pINT8_BW*2-2:0] sq8; +///////////////////////////////////////////// +assign sq3 = sq_pd_int8_3; +assign sq5 = sq_pd_int8_5; +assign sq2 = sq_pd_int8_2; +assign sq6 = sq_pd_int8_6; +assign sq1 = sq_pd_int8_1; +assign sq7 = sq_pd_int8_7; +assign sq0 = sq_pd_int8_0; +assign sq8 = sq_pd_int8_8; +//sum process +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_3_5 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d) begin + int8_sum_3_5 <= (sq3 + sq5); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_2_6 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d & (len5|len7|len9)) begin + int8_sum_2_6 <= (sq2 + sq6); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_1_7 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d & (len7|len9)) begin + int8_sum_1_7 <= (sq1 + sq7); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_0_8 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d & (len9)) begin + int8_sum_0_8 <= (sq0 + sq8); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sq_pd_int8_4_d <= {(pINT8_BW*2-1){1'b0}}; + end else if (load_din_d) begin + sq_pd_int8_4_d <= sq_pd_int8_4; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum3 <= {(pINT8_BW*2+1){1'b0}}; + end else if (load_din_2d ) begin + int8_sum3 <= (int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum5 <= {(pINT8_BW*2+2){1'b0}}; + end else if (load_din_2d &(len5|len7|len9)) begin + int8_sum5 <= ((int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}) + {1'b0,int8_sum_2_6}); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum7 <= {(pINT8_BW*2+2){1'b0}}; + end else if (load_din_2d &(len7|len9)) begin + int8_sum7 <= ((int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}) + (int8_sum_2_6 + int8_sum_1_7)); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum9 <= {(pINT8_BW*2+3){1'b0}}; + end else if (load_din_2d &(len9)) begin + int8_sum9 <= (((int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}) + (int8_sum_2_6 + int8_sum_1_7)) + {2'd0,int8_sum_0_8}); + end +end +always @(*) begin + case(reg2dp_normalz_len[1:0]) + 2'h0 : begin + int8_sum = {2'd0,int8_sum3}; + end + 2'h1 : begin + int8_sum = {1'd0,int8_sum5}; + end + 2'h2 : begin + int8_sum = {1'b0,int8_sum7}; + end + default: begin + int8_sum = int8_sum9; + end + endcase +end +endmodule // int_sum_block diff --git a/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block_tp1.v.vcp b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block_tp1.v.vcp new file mode 100644 index 0000000..d986f17 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cdp/int_sum_block_tp1.v.vcp @@ -0,0 +1,158 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: int_sum_block_tp1.v +module int_sum_block_tp1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,len5 + ,len7 + ,len9 + ,load_din_2d + ,load_din_d + ,reg2dp_normalz_len + ,sq_pd_int8_0 + ,sq_pd_int8_1 + ,sq_pd_int8_2 + ,sq_pd_int8_3 + ,sq_pd_int8_4 + ,sq_pd_int8_5 + ,sq_pd_int8_6 + ,sq_pd_int8_7 + ,sq_pd_int8_8 + ,int8_sum + ); +///////////////////////////////////////////// +parameter pINT8_BW = 9; +///////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input len5; +input len7; +input len9; +input load_din_2d; +input load_din_d; +input [1:0] reg2dp_normalz_len; +input [pINT8_BW*2-2:0] sq_pd_int8_0; +input [pINT8_BW*2-2:0] sq_pd_int8_1; +input [pINT8_BW*2-2:0] sq_pd_int8_2; +input [pINT8_BW*2-2:0] sq_pd_int8_3; +input [pINT8_BW*2-2:0] sq_pd_int8_4; +input [pINT8_BW*2-2:0] sq_pd_int8_5; +input [pINT8_BW*2-2:0] sq_pd_int8_6; +input [pINT8_BW*2-2:0] sq_pd_int8_7; +input [pINT8_BW*2-2:0] sq_pd_int8_8; +output [pINT8_BW*2+2:0] int8_sum; +///////////////////////////////////////////// +reg [pINT8_BW*2+2:0] int8_sum; +reg [pINT8_BW*2:0] int8_sum3; +reg [pINT8_BW*2+1:0] int8_sum5; +reg [pINT8_BW*2+1:0] int8_sum7; +reg [pINT8_BW*2+2:0] int8_sum9; +reg [pINT8_BW*2-1:0] int8_sum_0_8; +reg [pINT8_BW*2-1:0] int8_sum_1_7; +reg [pINT8_BW*2-1:0] int8_sum_2_6; +reg [pINT8_BW*2-1:0] int8_sum_3_5; +reg [pINT8_BW*2-2:0] sq_pd_int8_4_d; +wire [pINT8_BW*2-2:0] sq0; +wire [pINT8_BW*2-2:0] sq1; +wire [pINT8_BW*2-2:0] sq2; +wire [pINT8_BW*2-2:0] sq3; +wire [pINT8_BW*2-2:0] sq5; +wire [pINT8_BW*2-2:0] sq6; +wire [pINT8_BW*2-2:0] sq7; +wire [pINT8_BW*2-2:0] sq8; +///////////////////////////////////////////// +assign sq3 = sq_pd_int8_3; +assign sq5 = sq_pd_int8_5; +assign sq2 = sq_pd_int8_2; +assign sq6 = sq_pd_int8_6; +assign sq1 = sq_pd_int8_1; +assign sq7 = sq_pd_int8_7; +assign sq0 = sq_pd_int8_0; +assign sq8 = sq_pd_int8_8; +//sum process +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_3_5 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d) begin + int8_sum_3_5 <= (sq3 + sq5); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_2_6 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d & (len5|len7|len9)) begin + int8_sum_2_6 <= (sq2 + sq6); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_1_7 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d & (len7|len9)) begin + int8_sum_1_7 <= (sq1 + sq7); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum_0_8 <= {(pINT8_BW*2){1'b0}}; + end else if (load_din_d & (len9)) begin + int8_sum_0_8 <= (sq0 + sq8); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sq_pd_int8_4_d <= {(pINT8_BW*2-1){1'b0}}; + end else if (load_din_d) begin + sq_pd_int8_4_d <= sq_pd_int8_4; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum3 <= {(pINT8_BW*2+1){1'b0}}; + end else if (load_din_2d ) begin + int8_sum3 <= (int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum5 <= {(pINT8_BW*2+2){1'b0}}; + end else if (load_din_2d &(len5|len7|len9)) begin + int8_sum5 <= ((int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}) + {1'b0,int8_sum_2_6}); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum7 <= {(pINT8_BW*2+2){1'b0}}; + end else if (load_din_2d &(len7|len9)) begin + int8_sum7 <= ((int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}) + (int8_sum_2_6 + int8_sum_1_7)); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int8_sum9 <= {(pINT8_BW*2+3){1'b0}}; + end else if (load_din_2d &(len9)) begin + int8_sum9 <= (((int8_sum_3_5 + {1'b0,sq_pd_int8_4_d}) + (int8_sum_2_6 + int8_sum_1_7)) + {2'd0,int8_sum_0_8}); + end +end +always @(*) begin + case(reg2dp_normalz_len[1:0]) + 2'h0 : begin + int8_sum = {2'd0,int8_sum3}; + end + 2'h1 : begin + int8_sum = {1'd0,int8_sum5}; + end + 2'h2 : begin + int8_sum = {1'b0,int8_sum7}; + end + default: begin + int8_sum = int8_sum9; + end + endcase +end +endmodule // int_sum_block diff --git a/designs/src/NVDLA/vmod/nvdla/cfgrom/NV_NVDLA_cfgrom.v b/designs/src/NVDLA/vmod/nvdla/cfgrom/NV_NVDLA_cfgrom.v new file mode 100644 index 0000000..eec8059 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cfgrom/NV_NVDLA_cfgrom.v @@ -0,0 +1,162 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ + +// File Name: NV_NVDLA_cfgrom.v + +`include "simulate_x_tick.vh" +module NV_NVDLA_cfgrom ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2cfgrom_req_pd + ,csb2cfgrom_req_pvld + ,csb2cfgrom_req_prdy + ,cfgrom2csb_resp_pd + ,cfgrom2csb_resp_valid + ); + +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cfgrom_req_pd; +input csb2cfgrom_req_pvld; +output csb2cfgrom_req_prdy; +output [33:0] cfgrom2csb_resp_pd; +output cfgrom2csb_resp_valid; +///////////////////////////////////////////// +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +reg [33:0] cfgrom2csb_resp_pd; +reg cfgrom2csb_resp_valid; +reg [62:0] req_pd; +reg req_pvld; +// One-cycle pipeline to align response with fakeram read latency +reg reg_rd_en_d1; +reg reg_wr_en_nposted_d1; +//////////////////////////////////////////////////////////////////////// + +fakeram_32x128_1r1w u_NV_NVDLA_CFGROM_rom ( + .r0_clk (nvdla_core_clk) + ,.r0_ce_in (reg_rd_en) + ,.r0_addr_in (reg_offset[8:2]) // 7-bit word address from byte offset + ,.r0_rd_out (reg_rd_data[31:0]) + ,.w0_clk (nvdla_core_clk) + ,.w0_ce_in (1'b1) + ,.w0_we_in (1'b0) // ROM — write port permanently disabled + ,.w0_addr_in (7'b0) + ,.w0_wd_in (32'b0) + ); + +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cfgrom_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cfgrom_req_pvld) == 1'b1) begin + req_pd <= csb2cfgrom_req_pd; + end + end +end + + +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; + +assign csb2cfgrom_req_prdy = 1'b1; + + +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; + + +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; + +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; + +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; + +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; + +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; + +// Delay rd/wr enables by 1 cycle to match fakeram registered output +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_rd_en_d1 <= 1'b0; + reg_wr_en_nposted_d1 <= 1'b0; + end else begin + reg_rd_en_d1 <= reg_rd_en; + reg_wr_en_nposted_d1 <= reg_wr_en & req_nposted; + end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en_d1) + begin + cfgrom2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en_nposted_d1) + begin + cfgrom2csb_resp_pd <= csb_wresp_pd_w; + end + end +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom2csb_resp_valid <= 1'b0; + end else begin + cfgrom2csb_resp_valid <= reg_wr_en_nposted_d1 | reg_rd_en_d1; + end +end + + +endmodule \ No newline at end of file diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v new file mode 100644 index 0000000..9f30296 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v @@ -0,0 +1,2019 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_active.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_active ( + nvdla_core_clk + ,nvdla_core_rstn +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_dat_data${i}) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,in_dat_data0 +,in_dat_data1 +,in_dat_data2 +,in_dat_data3 +,in_dat_data4 +,in_dat_data5 +,in_dat_data6 +,in_dat_data7 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,in_dat_mask + ,in_dat_pvld + ,in_dat_stripe_end + ,in_dat_stripe_st +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_wt_data${i}) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,in_wt_data0 +,in_wt_data1 +,in_wt_data2 +,in_wt_data3 +,in_wt_data4 +,in_wt_data5 +,in_wt_data6 +,in_wt_data7 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,in_wt_mask + ,in_wt_pvld + ,in_wt_sel +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,dat${i}_actv_data +//: ,dat${i}_actv_nz +//: ,dat${i}_actv_pvld +//: ,dat${i}_pre_mask +//: ,dat${i}_pre_pvld +//: ,dat${i}_pre_stripe_end +//: ,dat${i}_pre_stripe_st +//: ) +//: } +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,wt${i}_actv_data +//: ,wt${i}_actv_nz +//: ,wt${i}_actv_pvld +//: ,wt${i}_sd_mask +//: ,wt${i}_sd_pvld +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,dat0_actv_data +,dat0_actv_nz +,dat0_actv_pvld +,dat0_pre_mask +,dat0_pre_pvld +,dat0_pre_stripe_end +,dat0_pre_stripe_st + +,dat1_actv_data +,dat1_actv_nz +,dat1_actv_pvld +,dat1_pre_mask +,dat1_pre_pvld +,dat1_pre_stripe_end +,dat1_pre_stripe_st + +,dat2_actv_data +,dat2_actv_nz +,dat2_actv_pvld +,dat2_pre_mask +,dat2_pre_pvld +,dat2_pre_stripe_end +,dat2_pre_stripe_st + +,dat3_actv_data +,dat3_actv_nz +,dat3_actv_pvld +,dat3_pre_mask +,dat3_pre_pvld +,dat3_pre_stripe_end +,dat3_pre_stripe_st + +,wt0_actv_data +,wt0_actv_nz +,wt0_actv_pvld +,wt0_sd_mask +,wt0_sd_pvld + +,wt1_actv_data +,wt1_actv_nz +,wt1_actv_pvld +,wt1_sd_mask +,wt1_sd_pvld + +,wt2_actv_data +,wt2_actv_nz +,wt2_actv_pvld +,wt2_sd_mask +,wt2_sd_pvld + +,wt3_actv_data +,wt3_actv_nz +,wt3_actv_pvld +,wt3_sd_mask +,wt3_sd_pvld + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ); +input nvdla_core_clk; +input nvdla_core_rstn; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] in_dat_data${i};) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] in_dat_data0; +input [8 -1:0] in_dat_data1; +input [8 -1:0] in_dat_data2; +input [8 -1:0] in_dat_data3; +input [8 -1:0] in_dat_data4; +input [8 -1:0] in_dat_data5; +input [8 -1:0] in_dat_data6; +input [8 -1:0] in_dat_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8 -1:0] in_dat_mask; +input in_dat_pvld; +input in_dat_stripe_end; +input in_dat_stripe_st; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] in_wt_data${i};) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] in_wt_data0; +input [8 -1:0] in_wt_data1; +input [8 -1:0] in_wt_data2; +input [8 -1:0] in_wt_data3; +input [8 -1:0] in_wt_data4; +input [8 -1:0] in_wt_data5; +input [8 -1:0] in_wt_data6; +input [8 -1:0] in_wt_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8 -1:0] in_wt_mask; +input in_wt_pvld; +input [8/2 -1:0] in_wt_sel; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [8*8 -1:0] dat${i}_actv_data; +//: output [8 -1:0] dat${i}_actv_nz; +//: output [8 -1:0] dat${i}_actv_pvld; +//: output [8 -1:0] dat${i}_pre_mask; +//: output dat${i}_pre_pvld; +//: output dat${i}_pre_stripe_end; +//: output dat${i}_pre_stripe_st; +//: ) +//: } +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [8*8 -1:0] wt${i}_actv_data; +//: output [8 -1:0] wt${i}_actv_nz; +//: output [8 -1:0] wt${i}_actv_pvld; +//: output [8 -1:0] wt${i}_sd_mask; +//: output wt${i}_sd_pvld; +//: ) +//: } +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: reg [8*8 -1:0] dat_actv_data_reg${i}; +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8*8 -1:0] dat0_actv_data; +output [8 -1:0] dat0_actv_nz; +output [8 -1:0] dat0_actv_pvld; +output [8 -1:0] dat0_pre_mask; +output dat0_pre_pvld; +output dat0_pre_stripe_end; +output dat0_pre_stripe_st; + +output [8*8 -1:0] dat1_actv_data; +output [8 -1:0] dat1_actv_nz; +output [8 -1:0] dat1_actv_pvld; +output [8 -1:0] dat1_pre_mask; +output dat1_pre_pvld; +output dat1_pre_stripe_end; +output dat1_pre_stripe_st; + +output [8*8 -1:0] dat2_actv_data; +output [8 -1:0] dat2_actv_nz; +output [8 -1:0] dat2_actv_pvld; +output [8 -1:0] dat2_pre_mask; +output dat2_pre_pvld; +output dat2_pre_stripe_end; +output dat2_pre_stripe_st; + +output [8*8 -1:0] dat3_actv_data; +output [8 -1:0] dat3_actv_nz; +output [8 -1:0] dat3_actv_pvld; +output [8 -1:0] dat3_pre_mask; +output dat3_pre_pvld; +output dat3_pre_stripe_end; +output dat3_pre_stripe_st; + +output [8*8 -1:0] wt0_actv_data; +output [8 -1:0] wt0_actv_nz; +output [8 -1:0] wt0_actv_pvld; +output [8 -1:0] wt0_sd_mask; +output wt0_sd_pvld; + +output [8*8 -1:0] wt1_actv_data; +output [8 -1:0] wt1_actv_nz; +output [8 -1:0] wt1_actv_pvld; +output [8 -1:0] wt1_sd_mask; +output wt1_sd_pvld; + +output [8*8 -1:0] wt2_actv_data; +output [8 -1:0] wt2_actv_nz; +output [8 -1:0] wt2_actv_pvld; +output [8 -1:0] wt2_sd_mask; +output wt2_sd_pvld; + +output [8*8 -1:0] wt3_actv_data; +output [8 -1:0] wt3_actv_nz; +output [8 -1:0] wt3_actv_pvld; +output [8 -1:0] wt3_sd_mask; +output wt3_sd_pvld; + +reg [8*8 -1:0] dat_actv_data_reg0; + +reg [8*8 -1:0] dat_actv_data_reg1; + +reg [8*8 -1:0] dat_actv_data_reg2; + +reg [8*8 -1:0] dat_actv_data_reg3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8*8 -1:0] dat_pre_data_w; +wire [8 -1:0] dat_pre_mask_w; +reg [8 -1:0] dat_pre_nz_w; +reg dat_pre_stripe_end; +reg dat_pre_stripe_st; +reg [8*8 -1:0] wt_pre_data; +wire [8*8 -1:0] wt_pre_data_w; +reg [8 -1:0] wt_pre_mask; +wire [8 -1:0] wt_pre_mask_w; +reg [8 -1:0] wt_pre_nz_w; +//: my $kk=8; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: wire [${kk}-1:0] wt${i}_sd_mask={${kk}{1'b0}}; +//: wire [${kk}-1:0] dat${i}_pre_mask={${kk}{1'b0}}; +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8-1:0] wt0_sd_mask={8{1'b0}}; +wire [8-1:0] dat0_pre_mask={8{1'b0}}; + +wire [8-1:0] wt1_sd_mask={8{1'b0}}; +wire [8-1:0] dat1_pre_mask={8{1'b0}}; + +wire [8-1:0] wt2_sd_mask={8{1'b0}}; +wire [8-1:0] dat2_pre_mask={8{1'b0}}; + +wire [8-1:0] wt3_sd_mask={8{1'b0}}; +wire [8-1:0] dat3_pre_mask={8{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////////////////////////// handle weight /////////////////////// +// weight pack +//: print "assign wt_pre_data_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_wt_data${i}"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign wt_pre_data_w = {in_wt_data7, in_wt_data6, in_wt_data5, in_wt_data4, in_wt_data3, in_wt_data2, in_wt_data1, in_wt_data0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// weight mask pack +//: print "assign wt_pre_mask_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_wt_mask[${i}]"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign wt_pre_mask_w = {in_wt_mask[7], in_wt_mask[6], in_wt_mask[5], in_wt_mask[4], in_wt_mask[3], in_wt_mask[2], in_wt_mask[1], in_wt_mask[0]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// 1 pipe for input +//: my $i=8; +//: my $j=8/2; +//: &eperl::flop(" -q wt_pre_nz -en in_wt_pvld -d wt_pre_mask_w -wid ${i} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: &eperl::flop(" -q wt_pre_sel -d \"in_wt_sel&{${j}{in_wt_pvld}}\" -wid ${j} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: +//: for (my $i = 0; $i < 8; $i ++) { +//: my $b0 = $i * 8; +//: my $b1 = $i * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q wt_pre_data[${b1}:${b0}] -en \"in_wt_pvld & wt_pre_mask_w[${i}]\" -d \"wt_pre_data_w[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [7:0] wt_pre_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pre_nz <= 'b0; + end else begin + if ((in_wt_pvld) == 1'b1) begin + wt_pre_nz <= wt_pre_mask_w; + // VCS coverage off + end else if ((in_wt_pvld) == 1'b0) begin + end else begin + wt_pre_nz <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] wt_pre_sel; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pre_sel <= 'b0; + end else begin + wt_pre_sel <= in_wt_sel&{4{in_wt_pvld}}; + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[0]) == 1'b1) begin + wt_pre_data[7:0] <= wt_pre_data_w[7:0]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[0]) == 1'b0) begin + end else begin + wt_pre_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[1]) == 1'b1) begin + wt_pre_data[15:8] <= wt_pre_data_w[15:8]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[1]) == 1'b0) begin + end else begin + wt_pre_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[2]) == 1'b1) begin + wt_pre_data[23:16] <= wt_pre_data_w[23:16]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[2]) == 1'b0) begin + end else begin + wt_pre_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[3]) == 1'b1) begin + wt_pre_data[31:24] <= wt_pre_data_w[31:24]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[3]) == 1'b0) begin + end else begin + wt_pre_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[4]) == 1'b1) begin + wt_pre_data[39:32] <= wt_pre_data_w[39:32]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[4]) == 1'b0) begin + end else begin + wt_pre_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[5]) == 1'b1) begin + wt_pre_data[47:40] <= wt_pre_data_w[47:40]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[5]) == 1'b0) begin + end else begin + wt_pre_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[6]) == 1'b1) begin + wt_pre_data[55:48] <= wt_pre_data_w[55:48]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[6]) == 1'b0) begin + end else begin + wt_pre_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_wt_pvld & wt_pre_mask_w[7]) == 1'b1) begin + wt_pre_data[63:56] <= wt_pre_data_w[63:56]; + // VCS coverage off + end else if ((in_wt_pvld & wt_pre_mask_w[7]) == 1'b0) begin + end else begin + wt_pre_data[63:56] <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// put input weight into shadow. +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq ( +//: reg wt${i}_sd_pvld; +//: wire wt${i}_sd_pvld_w = wt_pre_sel[${i}] ? 1'b1 : dat_pre_stripe_st ? 1'b0 : wt${i}_sd_pvld; ); +//: my $kk=8; +//: &eperl::flop("-nodeclare -q wt${i}_sd_pvld -d \"wt${i}_sd_pvld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q wt${i}_sd_nz -en wt_pre_sel[${i}] -d \"wt_pre_nz\" -wid ${kk} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: +//: print qq( +//: reg [8*8 -1:0] wt${i}_sd_data; ); +//: for(my $k = 0; $k < 8; $k ++) { +//: my $b0 = $k * 8; +//: my $b1 = $k * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q wt${i}_sd_data[${b1}:${b0}] -en \"wt_pre_sel[${i}] & wt_pre_nz[${k}]\" -d \"wt_pre_data[${b1}:${b0}] \" -clk nvdla_core_clk"); +//: } +//: } +//: &eperl::flop(" -q dat_actv_stripe_end -d \"dat_pre_stripe_end\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg wt0_sd_pvld; +wire wt0_sd_pvld_w = wt_pre_sel[0] ? 1'b1 : dat_pre_stripe_st ? 1'b0 : wt0_sd_pvld; always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt0_sd_pvld <= 'b0; + end else begin + wt0_sd_pvld <= wt0_sd_pvld_w; + end +end +reg [7:0] wt0_sd_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt0_sd_nz <= 'b0; + end else begin + if ((wt_pre_sel[0]) == 1'b1) begin + wt0_sd_nz <= wt_pre_nz; + // VCS coverage off + end else if ((wt_pre_sel[0]) == 1'b0) begin + end else begin + wt0_sd_nz <= 'bx; + // VCS coverage on + end + end +end + +reg [8*8 -1:0] wt0_sd_data; always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[0]) == 1'b1) begin + wt0_sd_data[7:0] <= wt_pre_data[7:0] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[0]) == 1'b0) begin + end else begin + wt0_sd_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[1]) == 1'b1) begin + wt0_sd_data[15:8] <= wt_pre_data[15:8] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[1]) == 1'b0) begin + end else begin + wt0_sd_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[2]) == 1'b1) begin + wt0_sd_data[23:16] <= wt_pre_data[23:16] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[2]) == 1'b0) begin + end else begin + wt0_sd_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[3]) == 1'b1) begin + wt0_sd_data[31:24] <= wt_pre_data[31:24] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[3]) == 1'b0) begin + end else begin + wt0_sd_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[4]) == 1'b1) begin + wt0_sd_data[39:32] <= wt_pre_data[39:32] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[4]) == 1'b0) begin + end else begin + wt0_sd_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[5]) == 1'b1) begin + wt0_sd_data[47:40] <= wt_pre_data[47:40] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[5]) == 1'b0) begin + end else begin + wt0_sd_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[6]) == 1'b1) begin + wt0_sd_data[55:48] <= wt_pre_data[55:48] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[6]) == 1'b0) begin + end else begin + wt0_sd_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[0] & wt_pre_nz[7]) == 1'b1) begin + wt0_sd_data[63:56] <= wt_pre_data[63:56] ; + // VCS coverage off + end else if ((wt_pre_sel[0] & wt_pre_nz[7]) == 1'b0) begin + end else begin + wt0_sd_data[63:56] <= 'bx; + // VCS coverage on + end +end + +reg wt1_sd_pvld; +wire wt1_sd_pvld_w = wt_pre_sel[1] ? 1'b1 : dat_pre_stripe_st ? 1'b0 : wt1_sd_pvld; always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt1_sd_pvld <= 'b0; + end else begin + wt1_sd_pvld <= wt1_sd_pvld_w; + end +end +reg [7:0] wt1_sd_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt1_sd_nz <= 'b0; + end else begin + if ((wt_pre_sel[1]) == 1'b1) begin + wt1_sd_nz <= wt_pre_nz; + // VCS coverage off + end else if ((wt_pre_sel[1]) == 1'b0) begin + end else begin + wt1_sd_nz <= 'bx; + // VCS coverage on + end + end +end + +reg [8*8 -1:0] wt1_sd_data; always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[0]) == 1'b1) begin + wt1_sd_data[7:0] <= wt_pre_data[7:0] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[0]) == 1'b0) begin + end else begin + wt1_sd_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[1]) == 1'b1) begin + wt1_sd_data[15:8] <= wt_pre_data[15:8] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[1]) == 1'b0) begin + end else begin + wt1_sd_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[2]) == 1'b1) begin + wt1_sd_data[23:16] <= wt_pre_data[23:16] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[2]) == 1'b0) begin + end else begin + wt1_sd_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[3]) == 1'b1) begin + wt1_sd_data[31:24] <= wt_pre_data[31:24] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[3]) == 1'b0) begin + end else begin + wt1_sd_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[4]) == 1'b1) begin + wt1_sd_data[39:32] <= wt_pre_data[39:32] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[4]) == 1'b0) begin + end else begin + wt1_sd_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[5]) == 1'b1) begin + wt1_sd_data[47:40] <= wt_pre_data[47:40] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[5]) == 1'b0) begin + end else begin + wt1_sd_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[6]) == 1'b1) begin + wt1_sd_data[55:48] <= wt_pre_data[55:48] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[6]) == 1'b0) begin + end else begin + wt1_sd_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[1] & wt_pre_nz[7]) == 1'b1) begin + wt1_sd_data[63:56] <= wt_pre_data[63:56] ; + // VCS coverage off + end else if ((wt_pre_sel[1] & wt_pre_nz[7]) == 1'b0) begin + end else begin + wt1_sd_data[63:56] <= 'bx; + // VCS coverage on + end +end + +reg wt2_sd_pvld; +wire wt2_sd_pvld_w = wt_pre_sel[2] ? 1'b1 : dat_pre_stripe_st ? 1'b0 : wt2_sd_pvld; always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2_sd_pvld <= 'b0; + end else begin + wt2_sd_pvld <= wt2_sd_pvld_w; + end +end +reg [7:0] wt2_sd_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2_sd_nz <= 'b0; + end else begin + if ((wt_pre_sel[2]) == 1'b1) begin + wt2_sd_nz <= wt_pre_nz; + // VCS coverage off + end else if ((wt_pre_sel[2]) == 1'b0) begin + end else begin + wt2_sd_nz <= 'bx; + // VCS coverage on + end + end +end + +reg [8*8 -1:0] wt2_sd_data; always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[0]) == 1'b1) begin + wt2_sd_data[7:0] <= wt_pre_data[7:0] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[0]) == 1'b0) begin + end else begin + wt2_sd_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[1]) == 1'b1) begin + wt2_sd_data[15:8] <= wt_pre_data[15:8] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[1]) == 1'b0) begin + end else begin + wt2_sd_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[2]) == 1'b1) begin + wt2_sd_data[23:16] <= wt_pre_data[23:16] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[2]) == 1'b0) begin + end else begin + wt2_sd_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[3]) == 1'b1) begin + wt2_sd_data[31:24] <= wt_pre_data[31:24] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[3]) == 1'b0) begin + end else begin + wt2_sd_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[4]) == 1'b1) begin + wt2_sd_data[39:32] <= wt_pre_data[39:32] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[4]) == 1'b0) begin + end else begin + wt2_sd_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[5]) == 1'b1) begin + wt2_sd_data[47:40] <= wt_pre_data[47:40] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[5]) == 1'b0) begin + end else begin + wt2_sd_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[6]) == 1'b1) begin + wt2_sd_data[55:48] <= wt_pre_data[55:48] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[6]) == 1'b0) begin + end else begin + wt2_sd_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[2] & wt_pre_nz[7]) == 1'b1) begin + wt2_sd_data[63:56] <= wt_pre_data[63:56] ; + // VCS coverage off + end else if ((wt_pre_sel[2] & wt_pre_nz[7]) == 1'b0) begin + end else begin + wt2_sd_data[63:56] <= 'bx; + // VCS coverage on + end +end + +reg wt3_sd_pvld; +wire wt3_sd_pvld_w = wt_pre_sel[3] ? 1'b1 : dat_pre_stripe_st ? 1'b0 : wt3_sd_pvld; always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt3_sd_pvld <= 'b0; + end else begin + wt3_sd_pvld <= wt3_sd_pvld_w; + end +end +reg [7:0] wt3_sd_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt3_sd_nz <= 'b0; + end else begin + if ((wt_pre_sel[3]) == 1'b1) begin + wt3_sd_nz <= wt_pre_nz; + // VCS coverage off + end else if ((wt_pre_sel[3]) == 1'b0) begin + end else begin + wt3_sd_nz <= 'bx; + // VCS coverage on + end + end +end + +reg [8*8 -1:0] wt3_sd_data; always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[0]) == 1'b1) begin + wt3_sd_data[7:0] <= wt_pre_data[7:0] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[0]) == 1'b0) begin + end else begin + wt3_sd_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[1]) == 1'b1) begin + wt3_sd_data[15:8] <= wt_pre_data[15:8] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[1]) == 1'b0) begin + end else begin + wt3_sd_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[2]) == 1'b1) begin + wt3_sd_data[23:16] <= wt_pre_data[23:16] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[2]) == 1'b0) begin + end else begin + wt3_sd_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[3]) == 1'b1) begin + wt3_sd_data[31:24] <= wt_pre_data[31:24] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[3]) == 1'b0) begin + end else begin + wt3_sd_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[4]) == 1'b1) begin + wt3_sd_data[39:32] <= wt_pre_data[39:32] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[4]) == 1'b0) begin + end else begin + wt3_sd_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[5]) == 1'b1) begin + wt3_sd_data[47:40] <= wt_pre_data[47:40] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[5]) == 1'b0) begin + end else begin + wt3_sd_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[6]) == 1'b1) begin + wt3_sd_data[55:48] <= wt_pre_data[55:48] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[6]) == 1'b0) begin + end else begin + wt3_sd_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_pre_sel[3] & wt_pre_nz[7]) == 1'b1) begin + wt3_sd_data[63:56] <= wt_pre_data[63:56] ; + // VCS coverage off + end else if ((wt_pre_sel[3] & wt_pre_nz[7]) == 1'b0) begin + end else begin + wt3_sd_data[63:56] <= 'bx; + // VCS coverage on + end +end +reg dat_actv_stripe_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_stripe_end <= 'b0; + end else begin + dat_actv_stripe_end <= dat_pre_stripe_end; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// pop weight from shadow when new stripe begin. +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq { +//: reg wt${i}_actv_vld; +//: reg [8*8 -1:0] wt${i}_actv_data; +//: wire wt${i}_actv_pvld_w = dat_pre_stripe_st ? wt${i}_sd_pvld : dat_actv_stripe_end ? 1'b0 : wt${i}_actv_vld; +//: }; +//: my $cmac_atomc = 8; +//: &eperl::flop(" -q wt${i}_actv_vld -d \"wt${i}_actv_pvld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -nodeclare"); +//: &eperl::flop(" -q wt${i}_actv_pvld -d \"{${cmac_atomc}{wt${i}_actv_pvld_w}}\" -clk nvdla_core_clk -rst nvdla_core_rstn -wid ${cmac_atomc}"); +//: &eperl::flop(" -q wt${i}_actv_nz -en \"dat_pre_stripe_st & wt${i}_actv_pvld_w\" -d \"wt${i}_sd_nz\" -clk nvdla_core_clk -rst nvdla_core_rstn -wid ${cmac_atomc}"); +//: +//: for(my $k = 0; $k < 8; $k ++) { +//: my $b0 = $k * 8; +//: my $b1 = $k * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q wt${i}_actv_data[${b1}:${b0}] -en \"dat_pre_stripe_st & wt${i}_actv_pvld_w\" -d \"{8{wt${i}_sd_nz[${k}]}} & wt${i}_sd_data[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg wt0_actv_vld; +reg [8*8 -1:0] wt0_actv_data; +wire wt0_actv_pvld_w = dat_pre_stripe_st ? wt0_sd_pvld : dat_actv_stripe_end ? 1'b0 : wt0_actv_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt0_actv_vld <= 'b0; + end else begin + wt0_actv_vld <= wt0_actv_pvld_w; + end +end +reg [7:0] wt0_actv_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt0_actv_pvld <= 'b0; + end else begin + wt0_actv_pvld <= {8{wt0_actv_pvld_w}}; + end +end +reg [7:0] wt0_actv_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt0_actv_nz <= 'b0; + end else begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_nz <= wt0_sd_nz; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_nz <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[7:0] <= {8{wt0_sd_nz[0]}} & wt0_sd_data[7:0]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[15:8] <= {8{wt0_sd_nz[1]}} & wt0_sd_data[15:8]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[23:16] <= {8{wt0_sd_nz[2]}} & wt0_sd_data[23:16]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[31:24] <= {8{wt0_sd_nz[3]}} & wt0_sd_data[31:24]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[39:32] <= {8{wt0_sd_nz[4]}} & wt0_sd_data[39:32]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[47:40] <= {8{wt0_sd_nz[5]}} & wt0_sd_data[47:40]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[55:48] <= {8{wt0_sd_nz[6]}} & wt0_sd_data[55:48]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b1) begin + wt0_actv_data[63:56] <= {8{wt0_sd_nz[7]}} & wt0_sd_data[63:56]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt0_actv_pvld_w) == 1'b0) begin + end else begin + wt0_actv_data[63:56] <= 'bx; + // VCS coverage on + end +end + +reg wt1_actv_vld; +reg [8*8 -1:0] wt1_actv_data; +wire wt1_actv_pvld_w = dat_pre_stripe_st ? wt1_sd_pvld : dat_actv_stripe_end ? 1'b0 : wt1_actv_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt1_actv_vld <= 'b0; + end else begin + wt1_actv_vld <= wt1_actv_pvld_w; + end +end +reg [7:0] wt1_actv_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt1_actv_pvld <= 'b0; + end else begin + wt1_actv_pvld <= {8{wt1_actv_pvld_w}}; + end +end +reg [7:0] wt1_actv_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt1_actv_nz <= 'b0; + end else begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_nz <= wt1_sd_nz; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_nz <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[7:0] <= {8{wt1_sd_nz[0]}} & wt1_sd_data[7:0]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[15:8] <= {8{wt1_sd_nz[1]}} & wt1_sd_data[15:8]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[23:16] <= {8{wt1_sd_nz[2]}} & wt1_sd_data[23:16]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[31:24] <= {8{wt1_sd_nz[3]}} & wt1_sd_data[31:24]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[39:32] <= {8{wt1_sd_nz[4]}} & wt1_sd_data[39:32]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[47:40] <= {8{wt1_sd_nz[5]}} & wt1_sd_data[47:40]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[55:48] <= {8{wt1_sd_nz[6]}} & wt1_sd_data[55:48]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b1) begin + wt1_actv_data[63:56] <= {8{wt1_sd_nz[7]}} & wt1_sd_data[63:56]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt1_actv_pvld_w) == 1'b0) begin + end else begin + wt1_actv_data[63:56] <= 'bx; + // VCS coverage on + end +end + +reg wt2_actv_vld; +reg [8*8 -1:0] wt2_actv_data; +wire wt2_actv_pvld_w = dat_pre_stripe_st ? wt2_sd_pvld : dat_actv_stripe_end ? 1'b0 : wt2_actv_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2_actv_vld <= 'b0; + end else begin + wt2_actv_vld <= wt2_actv_pvld_w; + end +end +reg [7:0] wt2_actv_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2_actv_pvld <= 'b0; + end else begin + wt2_actv_pvld <= {8{wt2_actv_pvld_w}}; + end +end +reg [7:0] wt2_actv_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt2_actv_nz <= 'b0; + end else begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_nz <= wt2_sd_nz; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_nz <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[7:0] <= {8{wt2_sd_nz[0]}} & wt2_sd_data[7:0]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[15:8] <= {8{wt2_sd_nz[1]}} & wt2_sd_data[15:8]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[23:16] <= {8{wt2_sd_nz[2]}} & wt2_sd_data[23:16]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[31:24] <= {8{wt2_sd_nz[3]}} & wt2_sd_data[31:24]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[39:32] <= {8{wt2_sd_nz[4]}} & wt2_sd_data[39:32]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[47:40] <= {8{wt2_sd_nz[5]}} & wt2_sd_data[47:40]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[55:48] <= {8{wt2_sd_nz[6]}} & wt2_sd_data[55:48]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b1) begin + wt2_actv_data[63:56] <= {8{wt2_sd_nz[7]}} & wt2_sd_data[63:56]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt2_actv_pvld_w) == 1'b0) begin + end else begin + wt2_actv_data[63:56] <= 'bx; + // VCS coverage on + end +end + +reg wt3_actv_vld; +reg [8*8 -1:0] wt3_actv_data; +wire wt3_actv_pvld_w = dat_pre_stripe_st ? wt3_sd_pvld : dat_actv_stripe_end ? 1'b0 : wt3_actv_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt3_actv_vld <= 'b0; + end else begin + wt3_actv_vld <= wt3_actv_pvld_w; + end +end +reg [7:0] wt3_actv_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt3_actv_pvld <= 'b0; + end else begin + wt3_actv_pvld <= {8{wt3_actv_pvld_w}}; + end +end +reg [7:0] wt3_actv_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt3_actv_nz <= 'b0; + end else begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_nz <= wt3_sd_nz; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_nz <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[7:0] <= {8{wt3_sd_nz[0]}} & wt3_sd_data[7:0]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[15:8] <= {8{wt3_sd_nz[1]}} & wt3_sd_data[15:8]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[23:16] <= {8{wt3_sd_nz[2]}} & wt3_sd_data[23:16]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[31:24] <= {8{wt3_sd_nz[3]}} & wt3_sd_data[31:24]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[39:32] <= {8{wt3_sd_nz[4]}} & wt3_sd_data[39:32]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[47:40] <= {8{wt3_sd_nz[5]}} & wt3_sd_data[47:40]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[55:48] <= {8{wt3_sd_nz[6]}} & wt3_sd_data[55:48]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b1) begin + wt3_actv_data[63:56] <= {8{wt3_sd_nz[7]}} & wt3_sd_data[63:56]; + // VCS coverage off + end else if ((dat_pre_stripe_st & wt3_actv_pvld_w) == 1'b0) begin + end else begin + wt3_actv_data[63:56] <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////// handle data /////////////// +// data pack +//: print "assign dat_pre_data_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_dat_data${i}"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_pre_data_w = {in_dat_data7, in_dat_data6, in_dat_data5, in_dat_data4, in_dat_data3, in_dat_data2, in_dat_data1, in_dat_data0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// data mask pack +//: print "assign dat_pre_mask_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_dat_mask[${i}]"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_pre_mask_w = {in_dat_mask[7], in_dat_mask[6], in_dat_mask[5], in_dat_mask[4], in_dat_mask[3], in_dat_mask[2], in_dat_mask[1], in_dat_mask[0]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// 1 pipe for input data +//: my $kk= 8; +//: &eperl::flop(" -q dat_pre_pvld -d \"in_dat_pvld\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q dat_pre_nz -en \"in_dat_pvld\" -d \"dat_pre_mask_w\" -wid ${kk} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg dat_pre_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pre_pvld <= 'b0; + end else begin + dat_pre_pvld <= in_dat_pvld; + end +end +reg [7:0] dat_pre_nz; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pre_nz <= 'b0; + end else begin + if ((in_dat_pvld) == 1'b1) begin + dat_pre_nz <= dat_pre_mask_w; + // VCS coverage off + end else if ((in_dat_pvld) == 1'b0) begin + end else begin + dat_pre_nz <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [8*8 -1:0] dat_pre_data; +//: for (my $i = 0; $i < 8; $i ++) { +//: my $b0 = $i * 8; +//: my $b1 = $i * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q dat_pre_data[${b1}:${b0}] -en \"in_dat_pvld & dat_pre_mask_w[${i}]\" -d \"dat_pre_data_w[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//: &eperl::flop("-nodeclare -q dat_pre_stripe_st -d \"in_dat_stripe_st & in_dat_pvld\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q dat_pre_stripe_end -d \"in_dat_stripe_end & in_dat_pvld \" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq { +//: assign dat${i}_pre_pvld = dat_pre_pvld; +//: assign dat${i}_pre_stripe_st = dat_pre_stripe_st; +//: assign dat${i}_pre_stripe_end = dat_pre_stripe_end; +//: }; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[0]) == 1'b1) begin + dat_pre_data[7:0] <= dat_pre_data_w[7:0]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[0]) == 1'b0) begin + end else begin + dat_pre_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[1]) == 1'b1) begin + dat_pre_data[15:8] <= dat_pre_data_w[15:8]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[1]) == 1'b0) begin + end else begin + dat_pre_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[2]) == 1'b1) begin + dat_pre_data[23:16] <= dat_pre_data_w[23:16]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[2]) == 1'b0) begin + end else begin + dat_pre_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[3]) == 1'b1) begin + dat_pre_data[31:24] <= dat_pre_data_w[31:24]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[3]) == 1'b0) begin + end else begin + dat_pre_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[4]) == 1'b1) begin + dat_pre_data[39:32] <= dat_pre_data_w[39:32]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[4]) == 1'b0) begin + end else begin + dat_pre_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[5]) == 1'b1) begin + dat_pre_data[47:40] <= dat_pre_data_w[47:40]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[5]) == 1'b0) begin + end else begin + dat_pre_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[6]) == 1'b1) begin + dat_pre_data[55:48] <= dat_pre_data_w[55:48]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[6]) == 1'b0) begin + end else begin + dat_pre_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld & dat_pre_mask_w[7]) == 1'b1) begin + dat_pre_data[63:56] <= dat_pre_data_w[63:56]; + // VCS coverage off + end else if ((in_dat_pvld & dat_pre_mask_w[7]) == 1'b0) begin + end else begin + dat_pre_data[63:56] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pre_stripe_st <= 'b0; + end else begin + dat_pre_stripe_st <= in_dat_stripe_st & in_dat_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pre_stripe_end <= 'b0; + end else begin + dat_pre_stripe_end <= in_dat_stripe_end & in_dat_pvld ; + end +end + +assign dat0_pre_pvld = dat_pre_pvld; +assign dat0_pre_stripe_st = dat_pre_stripe_st; +assign dat0_pre_stripe_end = dat_pre_stripe_end; + +assign dat1_pre_pvld = dat_pre_pvld; +assign dat1_pre_stripe_st = dat_pre_stripe_st; +assign dat1_pre_stripe_end = dat_pre_stripe_end; + +assign dat2_pre_pvld = dat_pre_pvld; +assign dat2_pre_stripe_st = dat_pre_stripe_st; +assign dat2_pre_stripe_end = dat_pre_stripe_end; + +assign dat3_pre_pvld = dat_pre_pvld; +assign dat3_pre_stripe_st = dat_pre_stripe_st; +assign dat3_pre_stripe_end = dat_pre_stripe_end; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// get data for cmac, 1 pipe. +//: my $atomc= 8; +//: for(my $i = 0; $i < 8/2; $i ++) { +//: my $l = $i + 8; +//: &eperl::flop(" -q dat_actv_pvld_reg${i} -d \"{${atomc}{dat_pre_pvld}}\" -wid ${atomc} -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q dat_actv_nz_reg${i} -en dat_pre_pvld -d dat_pre_nz -wid $atomc -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: for(my $k = 0; $k < 8; $k ++) { +//: my $j = int($k/2); +//: my $b0 = $k * 8; +//: my $b1 = $k * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q dat_actv_data_reg${i}[${b1}:${b0}] -en \"dat_pre_pvld & dat_pre_nz[${k}]\" -d \"dat_pre_data[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//: } +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq { +//: assign dat${i}_actv_pvld = dat_actv_pvld_reg${i}; +//: assign dat${i}_actv_data = dat_actv_data_reg${i}; +//: assign dat${i}_actv_nz = dat_actv_nz_reg${i}; +//: }; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [7:0] dat_actv_pvld_reg0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_pvld_reg0 <= 'b0; + end else begin + dat_actv_pvld_reg0 <= {8{dat_pre_pvld}}; + end +end +reg [7:0] dat_actv_nz_reg0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_nz_reg0 <= 'b0; + end else begin + if ((dat_pre_pvld) == 1'b1) begin + dat_actv_nz_reg0 <= dat_pre_nz; + // VCS coverage off + end else if ((dat_pre_pvld) == 1'b0) begin + end else begin + dat_actv_nz_reg0 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b1) begin + dat_actv_data_reg0[7:0] <= dat_pre_data[7:0]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b0) begin + end else begin + dat_actv_data_reg0[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b1) begin + dat_actv_data_reg0[15:8] <= dat_pre_data[15:8]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b0) begin + end else begin + dat_actv_data_reg0[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b1) begin + dat_actv_data_reg0[23:16] <= dat_pre_data[23:16]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b0) begin + end else begin + dat_actv_data_reg0[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b1) begin + dat_actv_data_reg0[31:24] <= dat_pre_data[31:24]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b0) begin + end else begin + dat_actv_data_reg0[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b1) begin + dat_actv_data_reg0[39:32] <= dat_pre_data[39:32]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b0) begin + end else begin + dat_actv_data_reg0[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b1) begin + dat_actv_data_reg0[47:40] <= dat_pre_data[47:40]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b0) begin + end else begin + dat_actv_data_reg0[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b1) begin + dat_actv_data_reg0[55:48] <= dat_pre_data[55:48]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b0) begin + end else begin + dat_actv_data_reg0[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b1) begin + dat_actv_data_reg0[63:56] <= dat_pre_data[63:56]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b0) begin + end else begin + dat_actv_data_reg0[63:56] <= 'bx; + // VCS coverage on + end +end +reg [7:0] dat_actv_pvld_reg1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_pvld_reg1 <= 'b0; + end else begin + dat_actv_pvld_reg1 <= {8{dat_pre_pvld}}; + end +end +reg [7:0] dat_actv_nz_reg1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_nz_reg1 <= 'b0; + end else begin + if ((dat_pre_pvld) == 1'b1) begin + dat_actv_nz_reg1 <= dat_pre_nz; + // VCS coverage off + end else if ((dat_pre_pvld) == 1'b0) begin + end else begin + dat_actv_nz_reg1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b1) begin + dat_actv_data_reg1[7:0] <= dat_pre_data[7:0]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b0) begin + end else begin + dat_actv_data_reg1[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b1) begin + dat_actv_data_reg1[15:8] <= dat_pre_data[15:8]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b0) begin + end else begin + dat_actv_data_reg1[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b1) begin + dat_actv_data_reg1[23:16] <= dat_pre_data[23:16]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b0) begin + end else begin + dat_actv_data_reg1[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b1) begin + dat_actv_data_reg1[31:24] <= dat_pre_data[31:24]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b0) begin + end else begin + dat_actv_data_reg1[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b1) begin + dat_actv_data_reg1[39:32] <= dat_pre_data[39:32]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b0) begin + end else begin + dat_actv_data_reg1[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b1) begin + dat_actv_data_reg1[47:40] <= dat_pre_data[47:40]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b0) begin + end else begin + dat_actv_data_reg1[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b1) begin + dat_actv_data_reg1[55:48] <= dat_pre_data[55:48]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b0) begin + end else begin + dat_actv_data_reg1[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b1) begin + dat_actv_data_reg1[63:56] <= dat_pre_data[63:56]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b0) begin + end else begin + dat_actv_data_reg1[63:56] <= 'bx; + // VCS coverage on + end +end +reg [7:0] dat_actv_pvld_reg2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_pvld_reg2 <= 'b0; + end else begin + dat_actv_pvld_reg2 <= {8{dat_pre_pvld}}; + end +end +reg [7:0] dat_actv_nz_reg2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_nz_reg2 <= 'b0; + end else begin + if ((dat_pre_pvld) == 1'b1) begin + dat_actv_nz_reg2 <= dat_pre_nz; + // VCS coverage off + end else if ((dat_pre_pvld) == 1'b0) begin + end else begin + dat_actv_nz_reg2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b1) begin + dat_actv_data_reg2[7:0] <= dat_pre_data[7:0]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b0) begin + end else begin + dat_actv_data_reg2[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b1) begin + dat_actv_data_reg2[15:8] <= dat_pre_data[15:8]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b0) begin + end else begin + dat_actv_data_reg2[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b1) begin + dat_actv_data_reg2[23:16] <= dat_pre_data[23:16]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b0) begin + end else begin + dat_actv_data_reg2[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b1) begin + dat_actv_data_reg2[31:24] <= dat_pre_data[31:24]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b0) begin + end else begin + dat_actv_data_reg2[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b1) begin + dat_actv_data_reg2[39:32] <= dat_pre_data[39:32]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b0) begin + end else begin + dat_actv_data_reg2[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b1) begin + dat_actv_data_reg2[47:40] <= dat_pre_data[47:40]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b0) begin + end else begin + dat_actv_data_reg2[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b1) begin + dat_actv_data_reg2[55:48] <= dat_pre_data[55:48]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b0) begin + end else begin + dat_actv_data_reg2[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b1) begin + dat_actv_data_reg2[63:56] <= dat_pre_data[63:56]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b0) begin + end else begin + dat_actv_data_reg2[63:56] <= 'bx; + // VCS coverage on + end +end +reg [7:0] dat_actv_pvld_reg3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_pvld_reg3 <= 'b0; + end else begin + dat_actv_pvld_reg3 <= {8{dat_pre_pvld}}; + end +end +reg [7:0] dat_actv_nz_reg3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_actv_nz_reg3 <= 'b0; + end else begin + if ((dat_pre_pvld) == 1'b1) begin + dat_actv_nz_reg3 <= dat_pre_nz; + // VCS coverage off + end else if ((dat_pre_pvld) == 1'b0) begin + end else begin + dat_actv_nz_reg3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b1) begin + dat_actv_data_reg3[7:0] <= dat_pre_data[7:0]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[0]) == 1'b0) begin + end else begin + dat_actv_data_reg3[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b1) begin + dat_actv_data_reg3[15:8] <= dat_pre_data[15:8]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[1]) == 1'b0) begin + end else begin + dat_actv_data_reg3[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b1) begin + dat_actv_data_reg3[23:16] <= dat_pre_data[23:16]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[2]) == 1'b0) begin + end else begin + dat_actv_data_reg3[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b1) begin + dat_actv_data_reg3[31:24] <= dat_pre_data[31:24]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[3]) == 1'b0) begin + end else begin + dat_actv_data_reg3[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b1) begin + dat_actv_data_reg3[39:32] <= dat_pre_data[39:32]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[4]) == 1'b0) begin + end else begin + dat_actv_data_reg3[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b1) begin + dat_actv_data_reg3[47:40] <= dat_pre_data[47:40]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[5]) == 1'b0) begin + end else begin + dat_actv_data_reg3[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b1) begin + dat_actv_data_reg3[55:48] <= dat_pre_data[55:48]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[6]) == 1'b0) begin + end else begin + dat_actv_data_reg3[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b1) begin + dat_actv_data_reg3[63:56] <= dat_pre_data[63:56]; + // VCS coverage off + end else if ((dat_pre_pvld & dat_pre_nz[7]) == 1'b0) begin + end else begin + dat_actv_data_reg3[63:56] <= 'bx; + // VCS coverage on + end +end + +assign dat0_actv_pvld = dat_actv_pvld_reg0; +assign dat0_actv_data = dat_actv_data_reg0; +assign dat0_actv_nz = dat_actv_nz_reg0; + +assign dat1_actv_pvld = dat_actv_pvld_reg1; +assign dat1_actv_data = dat_actv_data_reg1; +assign dat1_actv_nz = dat_actv_nz_reg1; + +assign dat2_actv_pvld = dat_actv_pvld_reg2; +assign dat2_actv_data = dat_actv_data_reg2; +assign dat2_actv_nz = dat_actv_nz_reg2; + +assign dat3_actv_pvld = dat_actv_pvld_reg3; +assign dat3_actv_data = dat_actv_data_reg3; +assign dat3_actv_nz = dat_actv_nz_reg3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v.vcp new file mode 100644 index 0000000..5d5d6f6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v.vcp @@ -0,0 +1,252 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_active.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_active ( + nvdla_core_clk + ,nvdla_core_rstn +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_dat_data${i}) +//: } + ,in_dat_mask + ,in_dat_pvld + ,in_dat_stripe_end + ,in_dat_stripe_st +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_wt_data${i}) +//: } + ,in_wt_mask + ,in_wt_pvld + ,in_wt_sel +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,dat${i}_actv_data +//: ,dat${i}_actv_nz +//: ,dat${i}_actv_pvld +//: ,dat${i}_pre_mask +//: ,dat${i}_pre_pvld +//: ,dat${i}_pre_stripe_end +//: ,dat${i}_pre_stripe_st +//: ) +//: } +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,wt${i}_actv_data +//: ,wt${i}_actv_nz +//: ,wt${i}_actv_pvld +//: ,wt${i}_sd_mask +//: ,wt${i}_sd_pvld +//: ) +//: } + ); +input nvdla_core_clk; +input nvdla_core_rstn; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] in_dat_data${i};) +//: } +input [8 -1:0] in_dat_mask; +input in_dat_pvld; +input in_dat_stripe_end; +input in_dat_stripe_st; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] in_wt_data${i};) +//: } +input [8 -1:0] in_wt_mask; +input in_wt_pvld; +input [8/2 -1:0] in_wt_sel; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [8*8 -1:0] dat${i}_actv_data; +//: output [8 -1:0] dat${i}_actv_nz; +//: output [8 -1:0] dat${i}_actv_pvld; +//: output [8 -1:0] dat${i}_pre_mask; +//: output dat${i}_pre_pvld; +//: output dat${i}_pre_stripe_end; +//: output dat${i}_pre_stripe_st; +//: ) +//: } +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [8*8 -1:0] wt${i}_actv_data; +//: output [8 -1:0] wt${i}_actv_nz; +//: output [8 -1:0] wt${i}_actv_pvld; +//: output [8 -1:0] wt${i}_sd_mask; +//: output wt${i}_sd_pvld; +//: ) +//: } +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: reg [8*8 -1:0] dat_actv_data_reg${i}; +//: ) +//: } +wire [8*8 -1:0] dat_pre_data_w; +wire [8 -1:0] dat_pre_mask_w; +reg [8 -1:0] dat_pre_nz_w; +reg dat_pre_stripe_end; +reg dat_pre_stripe_st; +reg [8*8 -1:0] wt_pre_data; +wire [8*8 -1:0] wt_pre_data_w; +reg [8 -1:0] wt_pre_mask; +wire [8 -1:0] wt_pre_mask_w; +reg [8 -1:0] wt_pre_nz_w; +//: my $kk=8; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: wire [${kk}-1:0] wt${i}_sd_mask={${kk}{1'b0}}; +//: wire [${kk}-1:0] dat${i}_pre_mask={${kk}{1'b0}}; +//: ) +//: } +/////////////////////////////////////// handle weight /////////////////////// +// weight pack +//: print "assign wt_pre_data_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_wt_data${i}"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +// weight mask pack +//: print "assign wt_pre_mask_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_wt_mask[${i}]"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +// 1 pipe for input +//: my $i=8; +//: my $j=8/2; +//: &eperl::flop(" -q wt_pre_nz -en in_wt_pvld -d wt_pre_mask_w -wid ${i} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: &eperl::flop(" -q wt_pre_sel -d \"in_wt_sel&{${j}{in_wt_pvld}}\" -wid ${j} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: +//: for (my $i = 0; $i < 8; $i ++) { +//: my $b0 = $i * 8; +//: my $b1 = $i * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q wt_pre_data[${b1}:${b0}] -en \"in_wt_pvld & wt_pre_mask_w[${i}]\" -d \"wt_pre_data_w[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +// put input weight into shadow. +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq ( +//: reg wt${i}_sd_pvld; +//: wire wt${i}_sd_pvld_w = wt_pre_sel[${i}] ? 1'b1 : dat_pre_stripe_st ? 1'b0 : wt${i}_sd_pvld; ); +//: my $kk=8; +//: &eperl::flop("-nodeclare -q wt${i}_sd_pvld -d \"wt${i}_sd_pvld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q wt${i}_sd_nz -en wt_pre_sel[${i}] -d \"wt_pre_nz\" -wid ${kk} -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: +//: print qq( +//: reg [8*8 -1:0] wt${i}_sd_data; ); +//: for(my $k = 0; $k < 8; $k ++) { +//: my $b0 = $k * 8; +//: my $b1 = $k * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q wt${i}_sd_data[${b1}:${b0}] -en \"wt_pre_sel[${i}] & wt_pre_nz[${k}]\" -d \"wt_pre_data[${b1}:${b0}] \" -clk nvdla_core_clk"); +//: } +//: } +//: &eperl::flop(" -q dat_actv_stripe_end -d \"dat_pre_stripe_end\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +// pop weight from shadow when new stripe begin. +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq { +//: reg wt${i}_actv_vld; +//: reg [8*8 -1:0] wt${i}_actv_data; +//: wire wt${i}_actv_pvld_w = dat_pre_stripe_st ? wt${i}_sd_pvld : dat_actv_stripe_end ? 1'b0 : wt${i}_actv_vld; +//: }; +//: my $cmac_atomc = 8; +//: &eperl::flop(" -q wt${i}_actv_vld -d \"wt${i}_actv_pvld_w\" -clk nvdla_core_clk -rst nvdla_core_rstn -nodeclare"); +//: &eperl::flop(" -q wt${i}_actv_pvld -d \"{${cmac_atomc}{wt${i}_actv_pvld_w}}\" -clk nvdla_core_clk -rst nvdla_core_rstn -wid ${cmac_atomc}"); +//: &eperl::flop(" -q wt${i}_actv_nz -en \"dat_pre_stripe_st & wt${i}_actv_pvld_w\" -d \"wt${i}_sd_nz\" -clk nvdla_core_clk -rst nvdla_core_rstn -wid ${cmac_atomc}"); +//: +//: for(my $k = 0; $k < 8; $k ++) { +//: my $b0 = $k * 8; +//: my $b1 = $k * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q wt${i}_actv_data[${b1}:${b0}] -en \"dat_pre_stripe_st & wt${i}_actv_pvld_w\" -d \"{8{wt${i}_sd_nz[${k}]}} & wt${i}_sd_data[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//: } +////////////////////////////////// handle data /////////////// +// data pack +//: print "assign dat_pre_data_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_dat_data${i}"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +// data mask pack +//: print "assign dat_pre_mask_w = {"; +//: for(my $i = 8 -1; $i >= 0; $i --) { +//: print "in_dat_mask[${i}]"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +// 1 pipe for input data +//: my $kk= 8; +//: &eperl::flop(" -q dat_pre_pvld -d \"in_dat_pvld\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q dat_pre_nz -en \"in_dat_pvld\" -d \"dat_pre_mask_w\" -wid ${kk} -clk nvdla_core_clk -rst nvdla_core_rstn"); +reg [8*8 -1:0] dat_pre_data; +//: for (my $i = 0; $i < 8; $i ++) { +//: my $b0 = $i * 8; +//: my $b1 = $i * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q dat_pre_data[${b1}:${b0}] -en \"in_dat_pvld & dat_pre_mask_w[${i}]\" -d \"dat_pre_data_w[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//: &eperl::flop("-nodeclare -q dat_pre_stripe_st -d \"in_dat_stripe_st & in_dat_pvld\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q dat_pre_stripe_end -d \"in_dat_stripe_end & in_dat_pvld \" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq { +//: assign dat${i}_pre_pvld = dat_pre_pvld; +//: assign dat${i}_pre_stripe_st = dat_pre_stripe_st; +//: assign dat${i}_pre_stripe_end = dat_pre_stripe_end; +//: }; +//: } +// get data for cmac, 1 pipe. +//: my $atomc= 8; +//: for(my $i = 0; $i < 8/2; $i ++) { +//: my $l = $i + 8; +//: &eperl::flop(" -q dat_actv_pvld_reg${i} -d \"{${atomc}{dat_pre_pvld}}\" -wid ${atomc} -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q dat_actv_nz_reg${i} -en dat_pre_pvld -d dat_pre_nz -wid $atomc -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: for(my $k = 0; $k < 8; $k ++) { +//: my $j = int($k/2); +//: my $b0 = $k * 8; +//: my $b1 = $k * 8 + 7; +//: &eperl::flop("-nodeclare -norst -q dat_actv_data_reg${i}[${b1}:${b0}] -en \"dat_pre_pvld & dat_pre_nz[${k}]\" -d \"dat_pre_data[${b1}:${b0}]\" -clk nvdla_core_clk"); +//: } +//: } +//: for(my $i = 0; $i < 8/2; $i ++) { +//: print qq { +//: assign dat${i}_actv_pvld = dat_actv_pvld_reg${i}; +//: assign dat${i}_actv_data = dat_actv_data_reg${i}; +//: assign dat${i}_actv_nz = dat_actv_nz_reg${i}; +//: }; +//: } +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v new file mode 100644 index 0000000..5e26c07 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v @@ -0,0 +1,77 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_cfg.v +module NV_NVDLA_CMAC_CORE_cfg ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2reg_done + ,reg2dp_conv_mode + ,reg2dp_op_en + ,cfg_is_wg + ,cfg_reg_en + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input reg2dp_conv_mode; +input reg2dp_op_en; +output cfg_is_wg; +output cfg_reg_en; +wire cfg_is_wg_w; +wire cfg_reg_en_w; +//: &eperl::flop(" -q op_en_d1 -d \"reg2dp_op_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q op_done_d1 -d \"dp2reg_done\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cfg_reg_en -d \"cfg_reg_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cfg_is_wg -d \"cfg_is_wg_w\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cfg_reg_en_d1 -d \"cfg_reg_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg op_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +reg op_done_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_done_d1 <= 'b0; + end else begin + op_done_d1 <= dp2reg_done; + end +end +reg cfg_reg_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_reg_en <= 'b0; + end else begin + cfg_reg_en <= cfg_reg_en_w; + end +end +reg cfg_is_wg; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_is_wg <= 'b0; + end else begin + cfg_is_wg <= cfg_is_wg_w; + end +end +reg cfg_reg_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_reg_en_d1 <= 'b0; + end else begin + cfg_reg_en_d1 <= cfg_reg_en; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cfg_reg_en_w = (~op_en_d1 | op_done_d1) & reg2dp_op_en; +assign cfg_is_wg_w = 1'b0; +endmodule // NV_NVDLA_CMAC_CORE_cfg diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v.vcp new file mode 100644 index 0000000..aa3eabe --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v.vcp @@ -0,0 +1,34 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_cfg.v +module NV_NVDLA_CMAC_CORE_cfg ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2reg_done + ,reg2dp_conv_mode + ,reg2dp_op_en + ,cfg_is_wg + ,cfg_reg_en + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input reg2dp_conv_mode; +input reg2dp_op_en; +output cfg_is_wg; +output cfg_reg_en; +wire cfg_is_wg_w; +wire cfg_reg_en_w; +//: &eperl::flop(" -q op_en_d1 -d \"reg2dp_op_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q op_done_d1 -d \"dp2reg_done\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cfg_reg_en -d \"cfg_reg_en_w\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cfg_is_wg -d \"cfg_is_wg_w\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q cfg_reg_en_d1 -d \"cfg_reg_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +assign cfg_reg_en_w = (~op_en_d1 | op_done_d1) & reg2dp_op_en; +assign cfg_is_wg_w = 1'b0; +endmodule // NV_NVDLA_CMAC_CORE_cfg diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v new file mode 100644 index 0000000..c2ee349 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v @@ -0,0 +1,344 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_mac.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_mac ( + nvdla_core_clk //|< i + ,nvdla_wg_clk //|< i + ,nvdla_core_rstn //|< i + ,cfg_is_wg //|< i + ,cfg_reg_en //|< i + ,dat_actv_data //|< i + ,dat_actv_nz //|< i + ,dat_actv_pvld //|< i + ,wt_actv_data //|< i + ,wt_actv_nz //|< i + ,wt_actv_pvld //|< i + ,mac_out_data //|> o + ,mac_out_pvld //|> o + ); +input nvdla_core_clk; +input nvdla_wg_clk; +input nvdla_core_rstn; +input cfg_is_wg; +input cfg_reg_en; +input [8*8 -1:0] dat_actv_data; +input [8 -1:0] dat_actv_nz; +input [8 -1:0] dat_actv_pvld; +input [8*8 -1:0] wt_actv_data; +input [8 -1:0] wt_actv_nz; +input [8 -1:0] wt_actv_pvld; +output [19 -1:0] mac_out_data; +output mac_out_pvld; +////////////////// unpack data&nz ////////////// +//: for(my $i=0; $i<8; $i++){ +//: my $bpe = 8; +//: my $data_msb = ($i+1) * $bpe - 1; +//: my $data_lsb = $i * $bpe; +//: print qq( +//: wire [${bpe}-1:0] wt_actv_data${i} = wt_actv_data[${data_msb}:${data_lsb}]; +//: wire [${bpe}-1:0] dat_actv_data${i} = dat_actv_data[${data_msb}:${data_lsb}]; +//: wire wt_actv_nz${i} = wt_actv_nz[${i}]; +//: wire dat_actv_nz${i} = dat_actv_nz[${i}]; +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8-1:0] wt_actv_data0 = wt_actv_data[7:0]; +wire [8-1:0] dat_actv_data0 = dat_actv_data[7:0]; +wire wt_actv_nz0 = wt_actv_nz[0]; +wire dat_actv_nz0 = dat_actv_nz[0]; + +wire [8-1:0] wt_actv_data1 = wt_actv_data[15:8]; +wire [8-1:0] dat_actv_data1 = dat_actv_data[15:8]; +wire wt_actv_nz1 = wt_actv_nz[1]; +wire dat_actv_nz1 = dat_actv_nz[1]; + +wire [8-1:0] wt_actv_data2 = wt_actv_data[23:16]; +wire [8-1:0] dat_actv_data2 = dat_actv_data[23:16]; +wire wt_actv_nz2 = wt_actv_nz[2]; +wire dat_actv_nz2 = dat_actv_nz[2]; + +wire [8-1:0] wt_actv_data3 = wt_actv_data[31:24]; +wire [8-1:0] dat_actv_data3 = dat_actv_data[31:24]; +wire wt_actv_nz3 = wt_actv_nz[3]; +wire dat_actv_nz3 = dat_actv_nz[3]; + +wire [8-1:0] wt_actv_data4 = wt_actv_data[39:32]; +wire [8-1:0] dat_actv_data4 = dat_actv_data[39:32]; +wire wt_actv_nz4 = wt_actv_nz[4]; +wire dat_actv_nz4 = dat_actv_nz[4]; + +wire [8-1:0] wt_actv_data5 = wt_actv_data[47:40]; +wire [8-1:0] dat_actv_data5 = dat_actv_data[47:40]; +wire wt_actv_nz5 = wt_actv_nz[5]; +wire dat_actv_nz5 = dat_actv_nz[5]; + +wire [8-1:0] wt_actv_data6 = wt_actv_data[55:48]; +wire [8-1:0] dat_actv_data6 = dat_actv_data[55:48]; +wire wt_actv_nz6 = wt_actv_nz[6]; +wire dat_actv_nz6 = dat_actv_nz[6]; + +wire [8-1:0] wt_actv_data7 = wt_actv_data[63:56]; +wire [8-1:0] dat_actv_data7 = dat_actv_data[63:56]; +wire wt_actv_nz7 = wt_actv_nz[7]; +wire dat_actv_nz7 = dat_actv_nz[7]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef DESIGNWARE_NOEXIST +wire signed [19 -1:0] sum_out; +wire [8 -1:0] op_out_pvld; +//: my $mul_result_width = 18; +//: my $bpe = 8; +//: my $rwidth = 19; +//: my $result_width = $rwidth * 8 * 2; +//: for (my $i=0; $i < 8; ++$i) { +//: print "assign op_out_pvld[${i}] = wt_actv_pvld[${i}] & dat_actv_pvld[${i}] & wt_actv_nz${i} & dat_actv_nz${i};\n"; +//: print "wire signed [${mul_result_width}-1:0] mout_$i = (\$signed(wt_actv_data${i}) * \$signed(dat_actv_data${i})) & \$signed({${mul_result_width}{op_out_pvld[${i}]}});\n"; +//: } +//: +//: print "assign sum_out = \n"; +//: for (my $i=0; $i < 8; ++$i) { +//: print " "; +//: print "+ " if ($i != 0); +//: print "mout_$i\n"; +//: } +//: print "; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign op_out_pvld[0] = wt_actv_pvld[0] & dat_actv_pvld[0] & wt_actv_nz0 & dat_actv_nz0; +wire signed [18-1:0] mout_0 = ($signed(wt_actv_data0) * $signed(dat_actv_data0)) & $signed({18{op_out_pvld[0]}}); +assign op_out_pvld[1] = wt_actv_pvld[1] & dat_actv_pvld[1] & wt_actv_nz1 & dat_actv_nz1; +wire signed [18-1:0] mout_1 = ($signed(wt_actv_data1) * $signed(dat_actv_data1)) & $signed({18{op_out_pvld[1]}}); +assign op_out_pvld[2] = wt_actv_pvld[2] & dat_actv_pvld[2] & wt_actv_nz2 & dat_actv_nz2; +wire signed [18-1:0] mout_2 = ($signed(wt_actv_data2) * $signed(dat_actv_data2)) & $signed({18{op_out_pvld[2]}}); +assign op_out_pvld[3] = wt_actv_pvld[3] & dat_actv_pvld[3] & wt_actv_nz3 & dat_actv_nz3; +wire signed [18-1:0] mout_3 = ($signed(wt_actv_data3) * $signed(dat_actv_data3)) & $signed({18{op_out_pvld[3]}}); +assign op_out_pvld[4] = wt_actv_pvld[4] & dat_actv_pvld[4] & wt_actv_nz4 & dat_actv_nz4; +wire signed [18-1:0] mout_4 = ($signed(wt_actv_data4) * $signed(dat_actv_data4)) & $signed({18{op_out_pvld[4]}}); +assign op_out_pvld[5] = wt_actv_pvld[5] & dat_actv_pvld[5] & wt_actv_nz5 & dat_actv_nz5; +wire signed [18-1:0] mout_5 = ($signed(wt_actv_data5) * $signed(dat_actv_data5)) & $signed({18{op_out_pvld[5]}}); +assign op_out_pvld[6] = wt_actv_pvld[6] & dat_actv_pvld[6] & wt_actv_nz6 & dat_actv_nz6; +wire signed [18-1:0] mout_6 = ($signed(wt_actv_data6) * $signed(dat_actv_data6)) & $signed({18{op_out_pvld[6]}}); +assign op_out_pvld[7] = wt_actv_pvld[7] & dat_actv_pvld[7] & wt_actv_nz7 & dat_actv_nz7; +wire signed [18-1:0] mout_7 = ($signed(wt_actv_data7) * $signed(dat_actv_data7)) & $signed({18{op_out_pvld[7]}}); +assign sum_out = + mout_0 + + mout_1 + + mout_2 + + mout_3 + + mout_4 + + mout_5 + + mout_6 + + mout_7 +; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`endif +`ifndef DESIGNWARE_NOEXIST +wire [19 -1:0] sum_out; +wire [19*8*2-1:0] full_mul_result; +wire [8 -1:0] op_out_pvld; +//: my $mul_result_width = 18; +//: my $bpe = 8; +//: my $rwidth = 19; +//: for (my $i=0; $i < 8; ++$i) { +//: my $j = $i * 2; +//: my $k = $i * 2 + 1; +//: print qq( +//: wire [$mul_result_width-1:0] mout_$j; +//: wire [$mul_result_width-1:0] mout_$k; +//: DW02_multp #(${bpe}, ${bpe}, $mul_result_width) mul$i ( +//: .a(wt_actv_data${i}), +//: .b(dat_actv_data${i}), +//: .tc(1'b1), +//: .out0(mout_${j}), +//: .out1(mout_${k}) +//: ); +//: assign op_out_pvld[${i}] = wt_actv_pvld[${i}] & dat_actv_pvld[${i}] & wt_actv_nz${i} & dat_actv_nz${i}; +//: ); +//: +//: my $offset = $j * $rwidth; +//: my $sign_extend_bits = 19 - $mul_result_width; +//: print qq( +//: assign full_mul_result[$offset + $rwidth - 1 : $offset] = {{${sign_extend_bits}{mout_${j}[${mul_result_width}-1]}}, mout_$j} & {${rwidth}{op_out_pvld[$i]}}; ); +//: $offset = $k * $rwidth; +//: print qq( +//: assign full_mul_result[$offset + $rwidth - 1 : $offset] = {{${sign_extend_bits}{mout_${k}[${mul_result_width}-1]}}, mout_$k} & {${rwidth}{op_out_pvld[$i]}}; ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [18-1:0] mout_0; +wire [18-1:0] mout_1; +DW02_multp #(8, 8, 18) mul0 ( +.a(wt_actv_data0), +.b(dat_actv_data0), +.tc(1'b1), +.out0(mout_0), +.out1(mout_1) +); +assign op_out_pvld[0] = wt_actv_pvld[0] & dat_actv_pvld[0] & wt_actv_nz0 & dat_actv_nz0; + +assign full_mul_result[0 + 19 - 1 : 0] = {{1{mout_0[18-1]}}, mout_0} & {19{op_out_pvld[0]}}; +assign full_mul_result[19 + 19 - 1 : 19] = {{1{mout_1[18-1]}}, mout_1} & {19{op_out_pvld[0]}}; +wire [18-1:0] mout_2; +wire [18-1:0] mout_3; +DW02_multp #(8, 8, 18) mul1 ( +.a(wt_actv_data1), +.b(dat_actv_data1), +.tc(1'b1), +.out0(mout_2), +.out1(mout_3) +); +assign op_out_pvld[1] = wt_actv_pvld[1] & dat_actv_pvld[1] & wt_actv_nz1 & dat_actv_nz1; + +assign full_mul_result[38 + 19 - 1 : 38] = {{1{mout_2[18-1]}}, mout_2} & {19{op_out_pvld[1]}}; +assign full_mul_result[57 + 19 - 1 : 57] = {{1{mout_3[18-1]}}, mout_3} & {19{op_out_pvld[1]}}; +wire [18-1:0] mout_4; +wire [18-1:0] mout_5; +DW02_multp #(8, 8, 18) mul2 ( +.a(wt_actv_data2), +.b(dat_actv_data2), +.tc(1'b1), +.out0(mout_4), +.out1(mout_5) +); +assign op_out_pvld[2] = wt_actv_pvld[2] & dat_actv_pvld[2] & wt_actv_nz2 & dat_actv_nz2; + +assign full_mul_result[76 + 19 - 1 : 76] = {{1{mout_4[18-1]}}, mout_4} & {19{op_out_pvld[2]}}; +assign full_mul_result[95 + 19 - 1 : 95] = {{1{mout_5[18-1]}}, mout_5} & {19{op_out_pvld[2]}}; +wire [18-1:0] mout_6; +wire [18-1:0] mout_7; +DW02_multp #(8, 8, 18) mul3 ( +.a(wt_actv_data3), +.b(dat_actv_data3), +.tc(1'b1), +.out0(mout_6), +.out1(mout_7) +); +assign op_out_pvld[3] = wt_actv_pvld[3] & dat_actv_pvld[3] & wt_actv_nz3 & dat_actv_nz3; + +assign full_mul_result[114 + 19 - 1 : 114] = {{1{mout_6[18-1]}}, mout_6} & {19{op_out_pvld[3]}}; +assign full_mul_result[133 + 19 - 1 : 133] = {{1{mout_7[18-1]}}, mout_7} & {19{op_out_pvld[3]}}; +wire [18-1:0] mout_8; +wire [18-1:0] mout_9; +DW02_multp #(8, 8, 18) mul4 ( +.a(wt_actv_data4), +.b(dat_actv_data4), +.tc(1'b1), +.out0(mout_8), +.out1(mout_9) +); +assign op_out_pvld[4] = wt_actv_pvld[4] & dat_actv_pvld[4] & wt_actv_nz4 & dat_actv_nz4; + +assign full_mul_result[152 + 19 - 1 : 152] = {{1{mout_8[18-1]}}, mout_8} & {19{op_out_pvld[4]}}; +assign full_mul_result[171 + 19 - 1 : 171] = {{1{mout_9[18-1]}}, mout_9} & {19{op_out_pvld[4]}}; +wire [18-1:0] mout_10; +wire [18-1:0] mout_11; +DW02_multp #(8, 8, 18) mul5 ( +.a(wt_actv_data5), +.b(dat_actv_data5), +.tc(1'b1), +.out0(mout_10), +.out1(mout_11) +); +assign op_out_pvld[5] = wt_actv_pvld[5] & dat_actv_pvld[5] & wt_actv_nz5 & dat_actv_nz5; + +assign full_mul_result[190 + 19 - 1 : 190] = {{1{mout_10[18-1]}}, mout_10} & {19{op_out_pvld[5]}}; +assign full_mul_result[209 + 19 - 1 : 209] = {{1{mout_11[18-1]}}, mout_11} & {19{op_out_pvld[5]}}; +wire [18-1:0] mout_12; +wire [18-1:0] mout_13; +DW02_multp #(8, 8, 18) mul6 ( +.a(wt_actv_data6), +.b(dat_actv_data6), +.tc(1'b1), +.out0(mout_12), +.out1(mout_13) +); +assign op_out_pvld[6] = wt_actv_pvld[6] & dat_actv_pvld[6] & wt_actv_nz6 & dat_actv_nz6; + +assign full_mul_result[228 + 19 - 1 : 228] = {{1{mout_12[18-1]}}, mout_12} & {19{op_out_pvld[6]}}; +assign full_mul_result[247 + 19 - 1 : 247] = {{1{mout_13[18-1]}}, mout_13} & {19{op_out_pvld[6]}}; +wire [18-1:0] mout_14; +wire [18-1:0] mout_15; +DW02_multp #(8, 8, 18) mul7 ( +.a(wt_actv_data7), +.b(dat_actv_data7), +.tc(1'b1), +.out0(mout_14), +.out1(mout_15) +); +assign op_out_pvld[7] = wt_actv_pvld[7] & dat_actv_pvld[7] & wt_actv_nz7 & dat_actv_nz7; + +assign full_mul_result[266 + 19 - 1 : 266] = {{1{mout_14[18-1]}}, mout_14} & {19{op_out_pvld[7]}}; +assign full_mul_result[285 + 19 - 1 : 285] = {{1{mout_15[18-1]}}, mout_15} & {19{op_out_pvld[7]}}; +//| eperl: generated_end (DO NOT EDIT ABOVE) +DW02_sum #(8*2, 19) fsum (.INPUT(full_mul_result), .SUM(sum_out)); +`endif +//add pipeline for retiming +wire pp_pvld_d0 = (dat_actv_pvld[0] & wt_actv_pvld[0]); +//wire [19 -1:0] sum_out_d0 = $unsigned(sum_out); +wire [19 -1:0] sum_out_d0 = sum_out; +//: my $rwidth = 19; +//: my $rr=3; +//: &eperl::retime("-stage ${rr} -o sum_out_dd -i sum_out_d0 -cg_en_i pp_pvld_d0 -cg_en_o pp_pvld_dd -cg_en_rtm -wid $rwidth"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [19-1:0] sum_out_d0_d1; +always @(posedge nvdla_core_clk) begin + if ((pp_pvld_d0)) begin + sum_out_d0_d1[19-1:0] <= sum_out_d0[19-1:0]; + end +end + +reg pp_pvld_d0_d1; +always @(posedge nvdla_core_clk) begin + pp_pvld_d0_d1 <= pp_pvld_d0; +end + +reg [19-1:0] sum_out_d0_d2; +always @(posedge nvdla_core_clk) begin + if ((pp_pvld_d0_d1)) begin + sum_out_d0_d2[19-1:0] <= sum_out_d0_d1[19-1:0]; + end +end + +reg pp_pvld_d0_d2; +always @(posedge nvdla_core_clk) begin + pp_pvld_d0_d2 <= pp_pvld_d0_d1; +end + +reg [19-1:0] sum_out_d0_d3; +always @(posedge nvdla_core_clk) begin + if ((pp_pvld_d0_d2)) begin + sum_out_d0_d3[19-1:0] <= sum_out_d0_d2[19-1:0]; + end +end + +reg pp_pvld_d0_d3; +always @(posedge nvdla_core_clk) begin + pp_pvld_d0_d3 <= pp_pvld_d0_d2; +end + +wire [19-1:0] sum_out_dd; +assign sum_out_dd = sum_out_d0_d3; + +wire pp_pvld_dd; +assign pp_pvld_dd = pp_pvld_d0_d3; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign mac_out_pvld=pp_pvld_dd; +assign mac_out_data=sum_out_dd; +endmodule // NV_NVDLA_CMAC_CORE_mac diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v.vcp new file mode 100644 index 0000000..ac7d1b7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v.vcp @@ -0,0 +1,120 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_mac.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_mac ( + nvdla_core_clk //|< i + ,nvdla_wg_clk //|< i + ,nvdla_core_rstn //|< i + ,cfg_is_wg //|< i + ,cfg_reg_en //|< i + ,dat_actv_data //|< i + ,dat_actv_nz //|< i + ,dat_actv_pvld //|< i + ,wt_actv_data //|< i + ,wt_actv_nz //|< i + ,wt_actv_pvld //|< i + ,mac_out_data //|> o + ,mac_out_pvld //|> o + ); +input nvdla_core_clk; +input nvdla_wg_clk; +input nvdla_core_rstn; +input cfg_is_wg; +input cfg_reg_en; +input [8*8 -1:0] dat_actv_data; +input [8 -1:0] dat_actv_nz; +input [8 -1:0] dat_actv_pvld; +input [8*8 -1:0] wt_actv_data; +input [8 -1:0] wt_actv_nz; +input [8 -1:0] wt_actv_pvld; +output [19 -1:0] mac_out_data; +output mac_out_pvld; +////////////////// unpack data&nz ////////////// +//: for(my $i=0; $i<8; $i++){ +//: my $bpe = 8; +//: my $data_msb = ($i+1) * $bpe - 1; +//: my $data_lsb = $i * $bpe; +//: print qq( +//: wire [${bpe}-1:0] wt_actv_data${i} = wt_actv_data[${data_msb}:${data_lsb}]; +//: wire [${bpe}-1:0] dat_actv_data${i} = dat_actv_data[${data_msb}:${data_lsb}]; +//: wire wt_actv_nz${i} = wt_actv_nz[${i}]; +//: wire dat_actv_nz${i} = dat_actv_nz[${i}]; +//: ) +//: } +`ifdef DESIGNWARE_NOEXIST +wire signed [19 -1:0] sum_out; +wire [8 -1:0] op_out_pvld; +//: my $mul_result_width = 18; +//: my $bpe = 8; +//: my $rwidth = 19; +//: my $result_width = $rwidth * 8 * 2; +//: for (my $i=0; $i < 8; ++$i) { +//: print "assign op_out_pvld[${i}] = wt_actv_pvld[${i}] & dat_actv_pvld[${i}] & wt_actv_nz${i} & dat_actv_nz${i};\n"; +//: print "wire signed [${mul_result_width}-1:0] mout_$i = (\$signed(wt_actv_data${i}) * \$signed(dat_actv_data${i})) & \$signed({${mul_result_width}{op_out_pvld[${i}]}});\n"; +//: } +//: +//: print "assign sum_out = \n"; +//: for (my $i=0; $i < 8; ++$i) { +//: print " "; +//: print "+ " if ($i != 0); +//: print "mout_$i\n"; +//: } +//: print "; \n"; +`endif +`ifndef DESIGNWARE_NOEXIST +wire [19 -1:0] sum_out; +wire [19*8*2-1:0] full_mul_result; +wire [8 -1:0] op_out_pvld; +//: my $mul_result_width = 18; +//: my $bpe = 8; +//: my $rwidth = 19; +//: for (my $i=0; $i < 8; ++$i) { +//: my $j = $i * 2; +//: my $k = $i * 2 + 1; +//: print qq( +//: wire [$mul_result_width-1:0] mout_$j; +//: wire [$mul_result_width-1:0] mout_$k; +//: DW02_multp #(${bpe}, ${bpe}, $mul_result_width) mul$i ( +//: .a(wt_actv_data${i}), +//: .b(dat_actv_data${i}), +//: .tc(1'b1), +//: .out0(mout_${j}), +//: .out1(mout_${k}) +//: ); +//: assign op_out_pvld[${i}] = wt_actv_pvld[${i}] & dat_actv_pvld[${i}] & wt_actv_nz${i} & dat_actv_nz${i}; +//: ); +//: +//: my $offset = $j * $rwidth; +//: my $sign_extend_bits = 19 - $mul_result_width; +//: print qq( +//: assign full_mul_result[$offset + $rwidth - 1 : $offset] = {{${sign_extend_bits}{mout_${j}[${mul_result_width}-1]}}, mout_$j} & {${rwidth}{op_out_pvld[$i]}}; ); +//: $offset = $k * $rwidth; +//: print qq( +//: assign full_mul_result[$offset + $rwidth - 1 : $offset] = {{${sign_extend_bits}{mout_${k}[${mul_result_width}-1]}}, mout_$k} & {${rwidth}{op_out_pvld[$i]}}; ); +//: } +DW02_sum #(8*2, 19) fsum (.INPUT(full_mul_result), .SUM(sum_out)); +`endif +//add pipeline for retiming +wire pp_pvld_d0 = (dat_actv_pvld[0] & wt_actv_pvld[0]); +//wire [19 -1:0] sum_out_d0 = $unsigned(sum_out); +wire [19 -1:0] sum_out_d0 = sum_out; +//: my $rwidth = 19; +//: my $rr=3; +//: &eperl::retime("-stage ${rr} -o sum_out_dd -i sum_out_d0 -cg_en_i pp_pvld_d0 -cg_en_o pp_pvld_dd -cg_en_rtm -wid $rwidth"); +assign mac_out_pvld=pp_pvld_dd; +assign mac_out_data=sum_out_dd; +endmodule // NV_NVDLA_CMAC_CORE_mac diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v new file mode 100644 index 0000000..1090a00 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v @@ -0,0 +1,836 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_rt_in.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_rt_in ( + nvdla_core_clk + ,nvdla_core_rstn +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i}); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_dat_data${i}); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_data0 +,sc2mac_dat_data1 +,sc2mac_dat_data2 +,sc2mac_dat_data3 +,sc2mac_dat_data4 +,sc2mac_dat_data5 +,sc2mac_dat_data6 +,sc2mac_dat_data7 +,in_dat_data0 +,in_dat_data1 +,in_dat_data2 +,in_dat_data3 +,in_dat_data4 +,in_dat_data5 +,in_dat_data6 +,in_dat_data7 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_mask + ,sc2mac_dat_pd + ,sc2mac_dat_pvld +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i}); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_wt_data${i}); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_data0 +,sc2mac_wt_data1 +,sc2mac_wt_data2 +,sc2mac_wt_data3 +,sc2mac_wt_data4 +,sc2mac_wt_data5 +,sc2mac_wt_data6 +,sc2mac_wt_data7 +,in_wt_data0 +,in_wt_data1 +,in_wt_data2 +,in_wt_data3 +,in_wt_data4 +,in_wt_data5 +,in_wt_data6 +,in_wt_data7 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_mask + ,sc2mac_wt_pvld + ,sc2mac_wt_sel + ,in_dat_mask + ,in_dat_pd + ,in_dat_pvld + ,in_dat_stripe_end + ,in_dat_stripe_st + ,in_wt_mask + ,in_wt_pvld + ,in_wt_sel + ); +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i};); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: output [8 -1:0] in_dat_data${i};); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i};); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: output [8 -1:0] in_wt_data${i};); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_dat_data0; +input [8 -1:0] sc2mac_dat_data1; +input [8 -1:0] sc2mac_dat_data2; +input [8 -1:0] sc2mac_dat_data3; +input [8 -1:0] sc2mac_dat_data4; +input [8 -1:0] sc2mac_dat_data5; +input [8 -1:0] sc2mac_dat_data6; +input [8 -1:0] sc2mac_dat_data7; +output [8 -1:0] in_dat_data0; +output [8 -1:0] in_dat_data1; +output [8 -1:0] in_dat_data2; +output [8 -1:0] in_dat_data3; +output [8 -1:0] in_dat_data4; +output [8 -1:0] in_dat_data5; +output [8 -1:0] in_dat_data6; +output [8 -1:0] in_dat_data7; +input [8 -1:0] sc2mac_wt_data0; +input [8 -1:0] sc2mac_wt_data1; +input [8 -1:0] sc2mac_wt_data2; +input [8 -1:0] sc2mac_wt_data3; +input [8 -1:0] sc2mac_wt_data4; +input [8 -1:0] sc2mac_wt_data5; +input [8 -1:0] sc2mac_wt_data6; +input [8 -1:0] sc2mac_wt_data7; +output [8 -1:0] in_wt_data0; +output [8 -1:0] in_wt_data1; +output [8 -1:0] in_wt_data2; +output [8 -1:0] in_wt_data3; +output [8 -1:0] in_wt_data4; +output [8 -1:0] in_wt_data5; +output [8 -1:0] in_wt_data6; +output [8 -1:0] in_wt_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; +input [8 -1:0] sc2mac_dat_mask; +input [8:0] sc2mac_dat_pd; +input sc2mac_dat_pvld; +input [8 -1:0] sc2mac_wt_mask; +input sc2mac_wt_pvld; +input [8/2 -1:0] sc2mac_wt_sel; +output [8 -1:0] in_dat_mask; +output [8:0] in_dat_pd; +output in_dat_pvld; +output in_dat_stripe_end; +output in_dat_stripe_st; +output [8 -1:0] in_wt_mask; +output in_wt_pvld; +output [8/2 -1:0] in_wt_sel; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: wire [8 -1:0] in_dat_data${i}; +//: wire [8 -1:0] in_wt_data${i};) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8 -1:0] in_dat_data0; +wire [8 -1:0] in_wt_data0; +wire [8 -1:0] in_dat_data1; +wire [8 -1:0] in_wt_data1; +wire [8 -1:0] in_dat_data2; +wire [8 -1:0] in_wt_data2; +wire [8 -1:0] in_dat_data3; +wire [8 -1:0] in_wt_data3; +wire [8 -1:0] in_dat_data4; +wire [8 -1:0] in_wt_data4; +wire [8 -1:0] in_dat_data5; +wire [8 -1:0] in_wt_data5; +wire [8 -1:0] in_dat_data6; +wire [8 -1:0] in_wt_data6; +wire [8 -1:0] in_dat_data7; +wire [8 -1:0] in_wt_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8 -1:0] in_dat_mask; +wire [8:0] in_dat_pd; +wire in_dat_pvld; +wire in_dat_stripe_end; +wire in_dat_stripe_st; +wire [8 -1:0] in_wt_mask; +wire in_wt_pvld; +wire [8/2 -1:0] in_wt_sel; +wire in_rt_dat_pvld_d0; +wire [8 -1:0] in_rt_dat_mask_d0; +wire [8:0] in_rt_dat_pd_d0; +wire [8*8 -1:0] in_rt_dat_data_d0; +//: for(my $i=1; $i<2 +1; $i++){ +//: print qq( +//: reg in_rt_dat_pvld_d${i}; +//: reg [8 -1:0] in_rt_dat_mask_d${i}; +//: reg [8:0] in_rt_dat_pd_d${i}; +//: reg [8*8 -1:0] in_rt_dat_data_d${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg in_rt_dat_pvld_d1; +reg [8 -1:0] in_rt_dat_mask_d1; +reg [8:0] in_rt_dat_pd_d1; +reg [8*8 -1:0] in_rt_dat_data_d1; + +reg in_rt_dat_pvld_d2; +reg [8 -1:0] in_rt_dat_mask_d2; +reg [8:0] in_rt_dat_pd_d2; +reg [8*8 -1:0] in_rt_dat_data_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8*8 -1:0] in_rt_wt_data_d0; +wire [8 -1:0] in_rt_wt_mask_d0; +wire in_rt_wt_pvld_d0; +wire [8/2 -1:0] in_rt_wt_sel_d0; +//: for(my $i=1; $i<2 +1; $i++){ +//: print qq( +//: reg [8*8 -1:0] in_rt_wt_data_d${i}; +//: reg [8 -1:0] in_rt_wt_mask_d${i}; +//: reg in_rt_wt_pvld_d${i}; +//: reg [8/2 -1:0] in_rt_wt_sel_d${i}; +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [8*8 -1:0] in_rt_wt_data_d1; +reg [8 -1:0] in_rt_wt_mask_d1; +reg in_rt_wt_pvld_d1; +reg [8/2 -1:0] in_rt_wt_sel_d1; + +reg [8*8 -1:0] in_rt_wt_data_d2; +reg [8 -1:0] in_rt_wt_mask_d2; +reg in_rt_wt_pvld_d2; +reg [8/2 -1:0] in_rt_wt_sel_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign in_rt_dat_pvld_d0 = sc2mac_dat_pvld; +assign in_rt_dat_mask_d0 = sc2mac_dat_mask; +assign in_rt_dat_pd_d0 = sc2mac_dat_pd; +assign in_rt_wt_pvld_d0 = sc2mac_wt_pvld; +assign in_rt_wt_mask_d0 = sc2mac_wt_mask; +assign in_rt_wt_sel_d0 = sc2mac_wt_sel; +//: my $kk=8; +//: for(my $k = 0; $k <8; $k ++) { +//: print "wire [$kk-1:0] in_rt_dat_data${k}_d0 = sc2mac_dat_data${k}; \n"; +//: } +//: for(my $k = 0; $k <8; $k ++) { +//: print "wire [$kk-1:0] in_rt_wt_data${k}_d0 = sc2mac_wt_data${k}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8-1:0] in_rt_dat_data0_d0 = sc2mac_dat_data0; +wire [8-1:0] in_rt_dat_data1_d0 = sc2mac_dat_data1; +wire [8-1:0] in_rt_dat_data2_d0 = sc2mac_dat_data2; +wire [8-1:0] in_rt_dat_data3_d0 = sc2mac_dat_data3; +wire [8-1:0] in_rt_dat_data4_d0 = sc2mac_dat_data4; +wire [8-1:0] in_rt_dat_data5_d0 = sc2mac_dat_data5; +wire [8-1:0] in_rt_dat_data6_d0 = sc2mac_dat_data6; +wire [8-1:0] in_rt_dat_data7_d0 = sc2mac_dat_data7; +wire [8-1:0] in_rt_wt_data0_d0 = sc2mac_wt_data0; +wire [8-1:0] in_rt_wt_data1_d0 = sc2mac_wt_data1; +wire [8-1:0] in_rt_wt_data2_d0 = sc2mac_wt_data2; +wire [8-1:0] in_rt_wt_data3_d0 = sc2mac_wt_data3; +wire [8-1:0] in_rt_wt_data4_d0 = sc2mac_wt_data4; +wire [8-1:0] in_rt_wt_data5_d0 = sc2mac_wt_data5; +wire [8-1:0] in_rt_wt_data6_d0 = sc2mac_wt_data6; +wire [8-1:0] in_rt_wt_data7_d0 = sc2mac_wt_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//========================================================== +// Retiming flops,add latency. +//========================================================== +//: my $latency = 2; +//: my $bpe=8; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-nodeclare -q in_rt_dat_pvld_d${j} -d \"in_rt_dat_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_dat_mask_d${j} -en \"in_rt_dat_pvld_d${i} | in_rt_dat_pvld_d${j}\" -d \"in_rt_dat_mask_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_dat_pd_d${j} -en \"in_rt_dat_pvld_d${i} | in_rt_dat_pvld_d${j}\" -d \"in_rt_dat_pd_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: for(my $k = 0; $k <8; $k ++) { +//: &eperl::flop("-norst -wid $bpe -q in_rt_dat_data${k}_d${j} -en \"in_rt_dat_mask_d${i}[${k}]\" -d \"in_rt_dat_data${k}_d${i}\" -clk nvdla_core_clk"); +//: } +//: +//: &eperl::flop("-nodeclare -q in_rt_wt_pvld_d${j} -d \"in_rt_wt_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_wt_mask_d${j} -en \"in_rt_wt_pvld_d${i} | in_rt_wt_pvld_d${j}\" -d \"in_rt_wt_mask_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_wt_sel_d${j} -en \"in_rt_wt_pvld_d${i} | in_rt_wt_pvld_d${j}\" -d \"in_rt_wt_sel_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: +//: my $bpe = 8; +//: for(my $k = 0; $k <8; $k ++) { +//: &eperl::flop("-norst -wid $bpe -q in_rt_wt_data${k}_d${j} -en \"in_rt_wt_mask_d${i}[${k}]\" -d \"in_rt_wt_data${k}_d${i}\" -clk nvdla_core_clk"); +//: } +//: } +//: +//: my $i = $latency; +//: print "assign in_dat_pvld = in_rt_dat_pvld_d${i};\n"; +//: print "assign in_dat_mask = in_rt_dat_mask_d${i};\n"; +//: print "assign in_dat_pd = in_rt_dat_pd_d${i};\n"; +//: print "assign in_wt_pvld = in_rt_wt_pvld_d${i};\n"; +//: print "assign in_wt_mask = in_rt_wt_mask_d${i};\n"; +//: print "assign in_wt_sel = in_rt_wt_sel_d${i};\n"; +//: +//: my $k=$latency; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: assign in_dat_data${i} = in_rt_dat_data${i}_d${k}; ) +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: assign in_wt_data${i} = in_rt_wt_data${i}_d${k};) +//: } +//: my $i= 5; +//: my $j= 6; +//: print qq( +//: assign in_dat_stripe_st = in_dat_pd[${i}]; +//: assign in_dat_stripe_end = in_dat_pd[${j}]; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_dat_pvld_d1 <= 'b0; + end else begin + in_rt_dat_pvld_d1 <= in_rt_dat_pvld_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_dat_mask_d1 <= 'b0; + end else begin + if ((in_rt_dat_pvld_d0 | in_rt_dat_pvld_d1) == 1'b1) begin + in_rt_dat_mask_d1 <= in_rt_dat_mask_d0; + // VCS coverage off + end else if ((in_rt_dat_pvld_d0 | in_rt_dat_pvld_d1) == 1'b0) begin + end else begin + in_rt_dat_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_dat_pd_d1 <= 'b0; + end else begin + if ((in_rt_dat_pvld_d0 | in_rt_dat_pvld_d1) == 1'b1) begin + in_rt_dat_pd_d1 <= in_rt_dat_pd_d0; + // VCS coverage off + end else if ((in_rt_dat_pvld_d0 | in_rt_dat_pvld_d1) == 1'b0) begin + end else begin + in_rt_dat_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] in_rt_dat_data0_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[0]) == 1'b1) begin + in_rt_dat_data0_d1 <= in_rt_dat_data0_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[0]) == 1'b0) begin + end else begin + in_rt_dat_data0_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data1_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[1]) == 1'b1) begin + in_rt_dat_data1_d1 <= in_rt_dat_data1_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[1]) == 1'b0) begin + end else begin + in_rt_dat_data1_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data2_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[2]) == 1'b1) begin + in_rt_dat_data2_d1 <= in_rt_dat_data2_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[2]) == 1'b0) begin + end else begin + in_rt_dat_data2_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data3_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[3]) == 1'b1) begin + in_rt_dat_data3_d1 <= in_rt_dat_data3_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[3]) == 1'b0) begin + end else begin + in_rt_dat_data3_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data4_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[4]) == 1'b1) begin + in_rt_dat_data4_d1 <= in_rt_dat_data4_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[4]) == 1'b0) begin + end else begin + in_rt_dat_data4_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data5_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[5]) == 1'b1) begin + in_rt_dat_data5_d1 <= in_rt_dat_data5_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[5]) == 1'b0) begin + end else begin + in_rt_dat_data5_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data6_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[6]) == 1'b1) begin + in_rt_dat_data6_d1 <= in_rt_dat_data6_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[6]) == 1'b0) begin + end else begin + in_rt_dat_data6_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data7_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d0[7]) == 1'b1) begin + in_rt_dat_data7_d1 <= in_rt_dat_data7_d0; + // VCS coverage off + end else if ((in_rt_dat_mask_d0[7]) == 1'b0) begin + end else begin + in_rt_dat_data7_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_wt_pvld_d1 <= 'b0; + end else begin + in_rt_wt_pvld_d1 <= in_rt_wt_pvld_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_wt_mask_d1 <= 'b0; + end else begin + if ((in_rt_wt_pvld_d0 | in_rt_wt_pvld_d1) == 1'b1) begin + in_rt_wt_mask_d1 <= in_rt_wt_mask_d0; + // VCS coverage off + end else if ((in_rt_wt_pvld_d0 | in_rt_wt_pvld_d1) == 1'b0) begin + end else begin + in_rt_wt_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_wt_sel_d1 <= 'b0; + end else begin + if ((in_rt_wt_pvld_d0 | in_rt_wt_pvld_d1) == 1'b1) begin + in_rt_wt_sel_d1 <= in_rt_wt_sel_d0; + // VCS coverage off + end else if ((in_rt_wt_pvld_d0 | in_rt_wt_pvld_d1) == 1'b0) begin + end else begin + in_rt_wt_sel_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] in_rt_wt_data0_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[0]) == 1'b1) begin + in_rt_wt_data0_d1 <= in_rt_wt_data0_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[0]) == 1'b0) begin + end else begin + in_rt_wt_data0_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data1_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[1]) == 1'b1) begin + in_rt_wt_data1_d1 <= in_rt_wt_data1_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[1]) == 1'b0) begin + end else begin + in_rt_wt_data1_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data2_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[2]) == 1'b1) begin + in_rt_wt_data2_d1 <= in_rt_wt_data2_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[2]) == 1'b0) begin + end else begin + in_rt_wt_data2_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data3_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[3]) == 1'b1) begin + in_rt_wt_data3_d1 <= in_rt_wt_data3_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[3]) == 1'b0) begin + end else begin + in_rt_wt_data3_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data4_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[4]) == 1'b1) begin + in_rt_wt_data4_d1 <= in_rt_wt_data4_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[4]) == 1'b0) begin + end else begin + in_rt_wt_data4_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data5_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[5]) == 1'b1) begin + in_rt_wt_data5_d1 <= in_rt_wt_data5_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[5]) == 1'b0) begin + end else begin + in_rt_wt_data5_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data6_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[6]) == 1'b1) begin + in_rt_wt_data6_d1 <= in_rt_wt_data6_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[6]) == 1'b0) begin + end else begin + in_rt_wt_data6_d1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data7_d1; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d0[7]) == 1'b1) begin + in_rt_wt_data7_d1 <= in_rt_wt_data7_d0; + // VCS coverage off + end else if ((in_rt_wt_mask_d0[7]) == 1'b0) begin + end else begin + in_rt_wt_data7_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_dat_pvld_d2 <= 'b0; + end else begin + in_rt_dat_pvld_d2 <= in_rt_dat_pvld_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_dat_mask_d2 <= 'b0; + end else begin + if ((in_rt_dat_pvld_d1 | in_rt_dat_pvld_d2) == 1'b1) begin + in_rt_dat_mask_d2 <= in_rt_dat_mask_d1; + // VCS coverage off + end else if ((in_rt_dat_pvld_d1 | in_rt_dat_pvld_d2) == 1'b0) begin + end else begin + in_rt_dat_mask_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_dat_pd_d2 <= 'b0; + end else begin + if ((in_rt_dat_pvld_d1 | in_rt_dat_pvld_d2) == 1'b1) begin + in_rt_dat_pd_d2 <= in_rt_dat_pd_d1; + // VCS coverage off + end else if ((in_rt_dat_pvld_d1 | in_rt_dat_pvld_d2) == 1'b0) begin + end else begin + in_rt_dat_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] in_rt_dat_data0_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[0]) == 1'b1) begin + in_rt_dat_data0_d2 <= in_rt_dat_data0_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[0]) == 1'b0) begin + end else begin + in_rt_dat_data0_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data1_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[1]) == 1'b1) begin + in_rt_dat_data1_d2 <= in_rt_dat_data1_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[1]) == 1'b0) begin + end else begin + in_rt_dat_data1_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data2_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[2]) == 1'b1) begin + in_rt_dat_data2_d2 <= in_rt_dat_data2_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[2]) == 1'b0) begin + end else begin + in_rt_dat_data2_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data3_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[3]) == 1'b1) begin + in_rt_dat_data3_d2 <= in_rt_dat_data3_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[3]) == 1'b0) begin + end else begin + in_rt_dat_data3_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data4_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[4]) == 1'b1) begin + in_rt_dat_data4_d2 <= in_rt_dat_data4_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[4]) == 1'b0) begin + end else begin + in_rt_dat_data4_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data5_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[5]) == 1'b1) begin + in_rt_dat_data5_d2 <= in_rt_dat_data5_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[5]) == 1'b0) begin + end else begin + in_rt_dat_data5_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data6_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[6]) == 1'b1) begin + in_rt_dat_data6_d2 <= in_rt_dat_data6_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[6]) == 1'b0) begin + end else begin + in_rt_dat_data6_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_dat_data7_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_dat_mask_d1[7]) == 1'b1) begin + in_rt_dat_data7_d2 <= in_rt_dat_data7_d1; + // VCS coverage off + end else if ((in_rt_dat_mask_d1[7]) == 1'b0) begin + end else begin + in_rt_dat_data7_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_wt_pvld_d2 <= 'b0; + end else begin + in_rt_wt_pvld_d2 <= in_rt_wt_pvld_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_wt_mask_d2 <= 'b0; + end else begin + if ((in_rt_wt_pvld_d1 | in_rt_wt_pvld_d2) == 1'b1) begin + in_rt_wt_mask_d2 <= in_rt_wt_mask_d1; + // VCS coverage off + end else if ((in_rt_wt_pvld_d1 | in_rt_wt_pvld_d2) == 1'b0) begin + end else begin + in_rt_wt_mask_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + in_rt_wt_sel_d2 <= 'b0; + end else begin + if ((in_rt_wt_pvld_d1 | in_rt_wt_pvld_d2) == 1'b1) begin + in_rt_wt_sel_d2 <= in_rt_wt_sel_d1; + // VCS coverage off + end else if ((in_rt_wt_pvld_d1 | in_rt_wt_pvld_d2) == 1'b0) begin + end else begin + in_rt_wt_sel_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] in_rt_wt_data0_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[0]) == 1'b1) begin + in_rt_wt_data0_d2 <= in_rt_wt_data0_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[0]) == 1'b0) begin + end else begin + in_rt_wt_data0_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data1_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[1]) == 1'b1) begin + in_rt_wt_data1_d2 <= in_rt_wt_data1_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[1]) == 1'b0) begin + end else begin + in_rt_wt_data1_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data2_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[2]) == 1'b1) begin + in_rt_wt_data2_d2 <= in_rt_wt_data2_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[2]) == 1'b0) begin + end else begin + in_rt_wt_data2_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data3_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[3]) == 1'b1) begin + in_rt_wt_data3_d2 <= in_rt_wt_data3_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[3]) == 1'b0) begin + end else begin + in_rt_wt_data3_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data4_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[4]) == 1'b1) begin + in_rt_wt_data4_d2 <= in_rt_wt_data4_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[4]) == 1'b0) begin + end else begin + in_rt_wt_data4_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data5_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[5]) == 1'b1) begin + in_rt_wt_data5_d2 <= in_rt_wt_data5_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[5]) == 1'b0) begin + end else begin + in_rt_wt_data5_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data6_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[6]) == 1'b1) begin + in_rt_wt_data6_d2 <= in_rt_wt_data6_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[6]) == 1'b0) begin + end else begin + in_rt_wt_data6_d2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] in_rt_wt_data7_d2; +always @(posedge nvdla_core_clk) begin + if ((in_rt_wt_mask_d1[7]) == 1'b1) begin + in_rt_wt_data7_d2 <= in_rt_wt_data7_d1; + // VCS coverage off + end else if ((in_rt_wt_mask_d1[7]) == 1'b0) begin + end else begin + in_rt_wt_data7_d2 <= 'bx; + // VCS coverage on + end +end +assign in_dat_pvld = in_rt_dat_pvld_d2; +assign in_dat_mask = in_rt_dat_mask_d2; +assign in_dat_pd = in_rt_dat_pd_d2; +assign in_wt_pvld = in_rt_wt_pvld_d2; +assign in_wt_mask = in_rt_wt_mask_d2; +assign in_wt_sel = in_rt_wt_sel_d2; + +assign in_dat_data0 = in_rt_dat_data0_d2; +assign in_dat_data1 = in_rt_dat_data1_d2; +assign in_dat_data2 = in_rt_dat_data2_d2; +assign in_dat_data3 = in_rt_dat_data3_d2; +assign in_dat_data4 = in_rt_dat_data4_d2; +assign in_dat_data5 = in_rt_dat_data5_d2; +assign in_dat_data6 = in_rt_dat_data6_d2; +assign in_dat_data7 = in_rt_dat_data7_d2; +assign in_wt_data0 = in_rt_wt_data0_d2; +assign in_wt_data1 = in_rt_wt_data1_d2; +assign in_wt_data2 = in_rt_wt_data2_d2; +assign in_wt_data3 = in_rt_wt_data3_d2; +assign in_wt_data4 = in_rt_wt_data4_d2; +assign in_wt_data5 = in_rt_wt_data5_d2; +assign in_wt_data6 = in_rt_wt_data6_d2; +assign in_wt_data7 = in_rt_wt_data7_d2; +assign in_dat_stripe_st = in_dat_pd[5]; +assign in_dat_stripe_end = in_dat_pd[6]; +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v.vcp new file mode 100644 index 0000000..93e6707 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v.vcp @@ -0,0 +1,180 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_rt_in.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_rt_in ( + nvdla_core_clk + ,nvdla_core_rstn +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i}); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_dat_data${i}); +//: } + ,sc2mac_dat_mask + ,sc2mac_dat_pd + ,sc2mac_dat_pvld +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i}); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,in_wt_data${i}); +//: } + ,sc2mac_wt_mask + ,sc2mac_wt_pvld + ,sc2mac_wt_sel + ,in_dat_mask + ,in_dat_pd + ,in_dat_pvld + ,in_dat_stripe_end + ,in_dat_stripe_st + ,in_wt_mask + ,in_wt_pvld + ,in_wt_sel + ); +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i};); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: output [8 -1:0] in_dat_data${i};); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i};); +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: output [8 -1:0] in_wt_data${i};); +//: } +input nvdla_core_clk; +input nvdla_core_rstn; +input [8 -1:0] sc2mac_dat_mask; +input [8:0] sc2mac_dat_pd; +input sc2mac_dat_pvld; +input [8 -1:0] sc2mac_wt_mask; +input sc2mac_wt_pvld; +input [8/2 -1:0] sc2mac_wt_sel; +output [8 -1:0] in_dat_mask; +output [8:0] in_dat_pd; +output in_dat_pvld; +output in_dat_stripe_end; +output in_dat_stripe_st; +output [8 -1:0] in_wt_mask; +output in_wt_pvld; +output [8/2 -1:0] in_wt_sel; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: wire [8 -1:0] in_dat_data${i}; +//: wire [8 -1:0] in_wt_data${i};) +//: } +wire [8 -1:0] in_dat_mask; +wire [8:0] in_dat_pd; +wire in_dat_pvld; +wire in_dat_stripe_end; +wire in_dat_stripe_st; +wire [8 -1:0] in_wt_mask; +wire in_wt_pvld; +wire [8/2 -1:0] in_wt_sel; +wire in_rt_dat_pvld_d0; +wire [8 -1:0] in_rt_dat_mask_d0; +wire [8:0] in_rt_dat_pd_d0; +wire [8*8 -1:0] in_rt_dat_data_d0; +//: for(my $i=1; $i<2 +1; $i++){ +//: print qq( +//: reg in_rt_dat_pvld_d${i}; +//: reg [8 -1:0] in_rt_dat_mask_d${i}; +//: reg [8:0] in_rt_dat_pd_d${i}; +//: reg [8*8 -1:0] in_rt_dat_data_d${i}; +//: ); +//: } +wire [8*8 -1:0] in_rt_wt_data_d0; +wire [8 -1:0] in_rt_wt_mask_d0; +wire in_rt_wt_pvld_d0; +wire [8/2 -1:0] in_rt_wt_sel_d0; +//: for(my $i=1; $i<2 +1; $i++){ +//: print qq( +//: reg [8*8 -1:0] in_rt_wt_data_d${i}; +//: reg [8 -1:0] in_rt_wt_mask_d${i}; +//: reg in_rt_wt_pvld_d${i}; +//: reg [8/2 -1:0] in_rt_wt_sel_d${i}; +//: ) +//: } +assign in_rt_dat_pvld_d0 = sc2mac_dat_pvld; +assign in_rt_dat_mask_d0 = sc2mac_dat_mask; +assign in_rt_dat_pd_d0 = sc2mac_dat_pd; +assign in_rt_wt_pvld_d0 = sc2mac_wt_pvld; +assign in_rt_wt_mask_d0 = sc2mac_wt_mask; +assign in_rt_wt_sel_d0 = sc2mac_wt_sel; +//: my $kk=8; +//: for(my $k = 0; $k <8; $k ++) { +//: print "wire [$kk-1:0] in_rt_dat_data${k}_d0 = sc2mac_dat_data${k}; \n"; +//: } +//: for(my $k = 0; $k <8; $k ++) { +//: print "wire [$kk-1:0] in_rt_wt_data${k}_d0 = sc2mac_wt_data${k}; \n"; +//: } +//========================================================== +// Retiming flops,add latency. +//========================================================== +//: my $latency = 2; +//: my $bpe=8; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-nodeclare -q in_rt_dat_pvld_d${j} -d \"in_rt_dat_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_dat_mask_d${j} -en \"in_rt_dat_pvld_d${i} | in_rt_dat_pvld_d${j}\" -d \"in_rt_dat_mask_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_dat_pd_d${j} -en \"in_rt_dat_pvld_d${i} | in_rt_dat_pvld_d${j}\" -d \"in_rt_dat_pd_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: for(my $k = 0; $k <8; $k ++) { +//: &eperl::flop("-norst -wid $bpe -q in_rt_dat_data${k}_d${j} -en \"in_rt_dat_mask_d${i}[${k}]\" -d \"in_rt_dat_data${k}_d${i}\" -clk nvdla_core_clk"); +//: } +//: +//: &eperl::flop("-nodeclare -q in_rt_wt_pvld_d${j} -d \"in_rt_wt_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_wt_mask_d${j} -en \"in_rt_wt_pvld_d${i} | in_rt_wt_pvld_d${j}\" -d \"in_rt_wt_mask_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-nodeclare -q in_rt_wt_sel_d${j} -en \"in_rt_wt_pvld_d${i} | in_rt_wt_pvld_d${j}\" -d \"in_rt_wt_sel_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: +//: my $bpe = 8; +//: for(my $k = 0; $k <8; $k ++) { +//: &eperl::flop("-norst -wid $bpe -q in_rt_wt_data${k}_d${j} -en \"in_rt_wt_mask_d${i}[${k}]\" -d \"in_rt_wt_data${k}_d${i}\" -clk nvdla_core_clk"); +//: } +//: } +//: +//: my $i = $latency; +//: print "assign in_dat_pvld = in_rt_dat_pvld_d${i};\n"; +//: print "assign in_dat_mask = in_rt_dat_mask_d${i};\n"; +//: print "assign in_dat_pd = in_rt_dat_pd_d${i};\n"; +//: print "assign in_wt_pvld = in_rt_wt_pvld_d${i};\n"; +//: print "assign in_wt_mask = in_rt_wt_mask_d${i};\n"; +//: print "assign in_wt_sel = in_rt_wt_sel_d${i};\n"; +//: +//: my $k=$latency; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: assign in_dat_data${i} = in_rt_dat_data${i}_d${k}; ) +//: } +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: assign in_wt_data${i} = in_rt_wt_data${i}_d${k};) +//: } +//: my $i= 5; +//: my $j= 6; +//: print qq( +//: assign in_dat_stripe_st = in_dat_pd[${i}]; +//: assign in_dat_stripe_end = in_dat_pd[${j}]; ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v new file mode 100644 index 0000000..263e0be --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v @@ -0,0 +1,364 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_rt_out.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_rt_out ( + nvdla_core_clk + ,nvdla_wg_clk + ,nvdla_core_rstn + ,cfg_is_wg + ,cfg_reg_en +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,out_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,out_data0 +,out_data1 +,out_data2 +,out_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,out_mask + ,out_pd + ,out_pvld + ,dp2reg_done +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_data0 +,mac2accu_data1 +,mac2accu_data2 +,mac2accu_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_mask + ,mac2accu_pd + ,mac2accu_pvld + ); +input nvdla_core_clk; +input nvdla_wg_clk; +input nvdla_core_rstn; +input cfg_is_wg; +input cfg_reg_en; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: input[19 -1:0] out_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input[19 -1:0] out_data0; +input[19 -1:0] out_data1; +input[19 -1:0] out_data2; +input[19 -1:0] out_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2 -1:0] out_mask; +input [8:0] out_pd; +input out_pvld; +output dp2reg_done; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output[19 -1:0] mac2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output[19 -1:0] mac2accu_data0; +output[19 -1:0] mac2accu_data1; +output[19 -1:0] mac2accu_data2; +output[19 -1:0] mac2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8/2 -1:0] mac2accu_mask; +output [8:0] mac2accu_pd; +output mac2accu_pvld; +wire [8/2 -1:0] mac2accu_mask; +wire [8:0] mac2accu_pd; +wire mac2accu_pvld; +wire out_layer_done; +wire out_rt_done_d0; +//========================================================== +// Config logic +//========================================================== +//: &eperl::flop(" -q \"cfg_reg_en_d1\" -d \"cfg_reg_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q \"cfg_is_wg_d1\" -en \"cfg_reg_en\" -d \"cfg_is_wg\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg cfg_reg_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_reg_en_d1 <= 'b0; + end else begin + cfg_reg_en_d1 <= cfg_reg_en; + end +end +reg cfg_is_wg_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_is_wg_d1 <= 'b0; + end else begin + if ((cfg_reg_en) == 1'b1) begin + cfg_is_wg_d1 <= cfg_is_wg; + // VCS coverage off + end else if ((cfg_reg_en) == 1'b0) begin + end else begin + cfg_is_wg_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//========================================================== +// Output retiming +//========================================================== +assign out_layer_done = out_pd[8] & + out_pd[6] & + out_pvld; +//: my $kk = 8/2; +//: my $jj = 19; +//: print "wire out_rt_pvld_d0 = out_pvld;\n"; +//: print "wire [$kk-1:0] out_rt_mask_d0 = out_mask;\n"; +//: print "wire [8:0] out_rt_pd_d0 = out_pd;\n"; +//: for(my $k = 0; $k < $kk; $k ++) { +//: print "wire [${jj}-1:0] out_rt_data${k}_d0 = out_data${k};\n"; +//: } +//: my $latency = 2; +//: my $kk = 8/2; +//: my $res_width = 19; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q out_rt_pvld_d${j} -d \"out_rt_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q out_rt_mask_d${j} -d \"out_rt_mask_d${i}\" -wid $kk -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-wid 9 -q out_rt_pd_d${j} -en \"out_rt_pvld_d${i}\" -d \"out_rt_pd_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: for(my $k = 0; $k < $kk; $k ++) { +//: &eperl::flop("-norst -wid $res_width -q out_rt_data${k}_d${j} -en \"out_rt_mask_d${i}[${k}]\" -d \"out_rt_data${k}_d${i}\" -clk nvdla_core_clk"); +//: } +//: } +//: +//: my $i = $latency; +//: print "assign mac2accu_pvld = out_rt_pvld_d${i};\n"; +//: print "assign mac2accu_mask = out_rt_mask_d${i};\n"; +//: print "assign mac2accu_pd = out_rt_pd_d${i};\n"; +//: my $kk = 8/2; +//: for(my $k = 0; $k < $kk; $k ++) { +//: print "assign mac2accu_data${k} = out_rt_data${k}_d${i};\n"; +//: } +//: +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire out_rt_pvld_d0 = out_pvld; +wire [4-1:0] out_rt_mask_d0 = out_mask; +wire [8:0] out_rt_pd_d0 = out_pd; +wire [19-1:0] out_rt_data0_d0 = out_data0; +wire [19-1:0] out_rt_data1_d0 = out_data1; +wire [19-1:0] out_rt_data2_d0 = out_data2; +wire [19-1:0] out_rt_data3_d0 = out_data3; +reg out_rt_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_pvld_d1 <= 'b0; + end else begin + out_rt_pvld_d1 <= out_rt_pvld_d0; + end +end +reg [3:0] out_rt_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_mask_d1 <= 'b0; + end else begin + out_rt_mask_d1 <= out_rt_mask_d0; + end +end +reg [8:0] out_rt_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_pd_d1 <= 'b0; + end else begin + if ((out_rt_pvld_d0) == 1'b1) begin + out_rt_pd_d1 <= out_rt_pd_d0; + // VCS coverage off + end else if ((out_rt_pvld_d0) == 1'b0) begin + end else begin + out_rt_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] out_rt_data0_d1; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d0[0]) == 1'b1) begin + out_rt_data0_d1 <= out_rt_data0_d0; + // VCS coverage off + end else if ((out_rt_mask_d0[0]) == 1'b0) begin + end else begin + out_rt_data0_d1 <= 'bx; + // VCS coverage on + end +end +reg [18:0] out_rt_data1_d1; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d0[1]) == 1'b1) begin + out_rt_data1_d1 <= out_rt_data1_d0; + // VCS coverage off + end else if ((out_rt_mask_d0[1]) == 1'b0) begin + end else begin + out_rt_data1_d1 <= 'bx; + // VCS coverage on + end +end +reg [18:0] out_rt_data2_d1; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d0[2]) == 1'b1) begin + out_rt_data2_d1 <= out_rt_data2_d0; + // VCS coverage off + end else if ((out_rt_mask_d0[2]) == 1'b0) begin + end else begin + out_rt_data2_d1 <= 'bx; + // VCS coverage on + end +end +reg [18:0] out_rt_data3_d1; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d0[3]) == 1'b1) begin + out_rt_data3_d1 <= out_rt_data3_d0; + // VCS coverage off + end else if ((out_rt_mask_d0[3]) == 1'b0) begin + end else begin + out_rt_data3_d1 <= 'bx; + // VCS coverage on + end +end +reg out_rt_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_pvld_d2 <= 'b0; + end else begin + out_rt_pvld_d2 <= out_rt_pvld_d1; + end +end +reg [3:0] out_rt_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_mask_d2 <= 'b0; + end else begin + out_rt_mask_d2 <= out_rt_mask_d1; + end +end +reg [8:0] out_rt_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_pd_d2 <= 'b0; + end else begin + if ((out_rt_pvld_d1) == 1'b1) begin + out_rt_pd_d2 <= out_rt_pd_d1; + // VCS coverage off + end else if ((out_rt_pvld_d1) == 1'b0) begin + end else begin + out_rt_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] out_rt_data0_d2; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d1[0]) == 1'b1) begin + out_rt_data0_d2 <= out_rt_data0_d1; + // VCS coverage off + end else if ((out_rt_mask_d1[0]) == 1'b0) begin + end else begin + out_rt_data0_d2 <= 'bx; + // VCS coverage on + end +end +reg [18:0] out_rt_data1_d2; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d1[1]) == 1'b1) begin + out_rt_data1_d2 <= out_rt_data1_d1; + // VCS coverage off + end else if ((out_rt_mask_d1[1]) == 1'b0) begin + end else begin + out_rt_data1_d2 <= 'bx; + // VCS coverage on + end +end +reg [18:0] out_rt_data2_d2; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d1[2]) == 1'b1) begin + out_rt_data2_d2 <= out_rt_data2_d1; + // VCS coverage off + end else if ((out_rt_mask_d1[2]) == 1'b0) begin + end else begin + out_rt_data2_d2 <= 'bx; + // VCS coverage on + end +end +reg [18:0] out_rt_data3_d2; +always @(posedge nvdla_core_clk) begin + if ((out_rt_mask_d1[3]) == 1'b1) begin + out_rt_data3_d2 <= out_rt_data3_d1; + // VCS coverage off + end else if ((out_rt_mask_d1[3]) == 1'b0) begin + end else begin + out_rt_data3_d2 <= 'bx; + // VCS coverage on + end +end +assign mac2accu_pvld = out_rt_pvld_d2; +assign mac2accu_mask = out_rt_mask_d2; +assign mac2accu_pd = out_rt_pd_d2; +assign mac2accu_data0 = out_rt_data0_d2; +assign mac2accu_data1 = out_rt_data1_d2; +assign mac2accu_data2 = out_rt_data2_d2; +assign mac2accu_data3 = out_rt_data3_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// get layer done signal +assign out_rt_done_d0 = out_layer_done; +//: my $latency = 2 + 1; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q out_rt_done_d${j} -d \"out_rt_done_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: }; +//: my $h = $latency; +//: print "assign dp2reg_done = out_rt_done_d${h};\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg out_rt_done_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_done_d1 <= 'b0; + end else begin + out_rt_done_d1 <= out_rt_done_d0; + end +end +reg out_rt_done_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_done_d2 <= 'b0; + end else begin + out_rt_done_d2 <= out_rt_done_d1; + end +end +reg out_rt_done_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rt_done_d3 <= 'b0; + end else begin + out_rt_done_d3 <= out_rt_done_d2; + end +end +assign dp2reg_done = out_rt_done_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v.vcp new file mode 100644 index 0000000..2c4dd3b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v.vcp @@ -0,0 +1,115 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_rt_out.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_CORE_rt_out ( + nvdla_core_clk + ,nvdla_wg_clk + ,nvdla_core_rstn + ,cfg_is_wg + ,cfg_reg_en +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,out_data${i} ) +//: } + ,out_mask + ,out_pd + ,out_pvld + ,dp2reg_done +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_data${i} ) +//: } + ,mac2accu_mask + ,mac2accu_pd + ,mac2accu_pvld + ); +input nvdla_core_clk; +input nvdla_wg_clk; +input nvdla_core_rstn; +input cfg_is_wg; +input cfg_reg_en; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: input[19 -1:0] out_data${i}; ) +//: } +input [8/2 -1:0] out_mask; +input [8:0] out_pd; +input out_pvld; +output dp2reg_done; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output[19 -1:0] mac2accu_data${i}; ) +//: } +output [8/2 -1:0] mac2accu_mask; +output [8:0] mac2accu_pd; +output mac2accu_pvld; +wire [8/2 -1:0] mac2accu_mask; +wire [8:0] mac2accu_pd; +wire mac2accu_pvld; +wire out_layer_done; +wire out_rt_done_d0; +//========================================================== +// Config logic +//========================================================== +//: &eperl::flop(" -q \"cfg_reg_en_d1\" -d \"cfg_reg_en\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q \"cfg_is_wg_d1\" -en \"cfg_reg_en\" -d \"cfg_is_wg\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//========================================================== +// Output retiming +//========================================================== +assign out_layer_done = out_pd[8] & + out_pd[6] & + out_pvld; +//: my $kk = 8/2; +//: my $jj = 19; +//: print "wire out_rt_pvld_d0 = out_pvld;\n"; +//: print "wire [$kk-1:0] out_rt_mask_d0 = out_mask;\n"; +//: print "wire [8:0] out_rt_pd_d0 = out_pd;\n"; +//: for(my $k = 0; $k < $kk; $k ++) { +//: print "wire [${jj}-1:0] out_rt_data${k}_d0 = out_data${k};\n"; +//: } +//: my $latency = 2; +//: my $kk = 8/2; +//: my $res_width = 19; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q out_rt_pvld_d${j} -d \"out_rt_pvld_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop(" -q out_rt_mask_d${j} -d \"out_rt_mask_d${i}\" -wid $kk -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: &eperl::flop("-wid 9 -q out_rt_pd_d${j} -en \"out_rt_pvld_d${i}\" -d \"out_rt_pd_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn"); +//: for(my $k = 0; $k < $kk; $k ++) { +//: &eperl::flop("-norst -wid $res_width -q out_rt_data${k}_d${j} -en \"out_rt_mask_d${i}[${k}]\" -d \"out_rt_data${k}_d${i}\" -clk nvdla_core_clk"); +//: } +//: } +//: +//: my $i = $latency; +//: print "assign mac2accu_pvld = out_rt_pvld_d${i};\n"; +//: print "assign mac2accu_mask = out_rt_mask_d${i};\n"; +//: print "assign mac2accu_pd = out_rt_pd_d${i};\n"; +//: my $kk = 8/2; +//: for(my $k = 0; $k < $kk; $k ++) { +//: print "assign mac2accu_data${k} = out_rt_data${k}_d${i};\n"; +//: } +//: +// get layer done signal +assign out_rt_done_d0 = out_layer_done; +//: my $latency = 2 + 1; +//: for(my $i = 0; $i < $latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop(" -q out_rt_done_d${j} -d \"out_rt_done_d${i}\" -clk nvdla_core_clk -rst nvdla_core_rstn "); +//: }; +//: my $h = $latency; +//: print "assign dp2reg_done = out_rt_done_d${h};\n"; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v new file mode 100644 index 0000000..a8241f4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_slcg.v +module NV_NVDLA_CMAC_CORE_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CMAC_CORE_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v.vcp new file mode 100644 index 0000000..a8241f4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v.vcp @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_CORE_slcg.v +module NV_NVDLA_CMAC_CORE_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CMAC_CORE_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CMAC_CORE_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v new file mode 100644 index 0000000..f863cb3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v @@ -0,0 +1,123 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_REG_dual.v +module NV_NVDLA_CMAC_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,conv_mode + ,proc_precision + ,op_en_trigger + ,op_en + ); +wire [31:0] nvdla_cmac_a_d_misc_cfg_0_out; +wire [31:0] nvdla_cmac_a_d_op_enable_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output conv_mode; +output [1:0] proc_precision; +output op_en_trigger; +// Read-only register inputs +input op_en; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg conv_mode; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cmac_a_d_misc_cfg_0_wren = (reg_offset_wr == (32'h700c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cmac_a_d_op_enable_0_wren = (reg_offset_wr == (32'h7008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cmac_a_d_misc_cfg_0_out[31:0] = { 18'b0, proc_precision, 11'b0, conv_mode }; +assign nvdla_cmac_a_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign op_en_trigger = nvdla_cmac_a_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cmac_a_d_misc_cfg_0_out + or nvdla_cmac_a_d_op_enable_0_out + ) begin + case (reg_offset_rd_int) + (32'h700c & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_d_misc_cfg_0_out ; + end + (32'h7008 & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_d_op_enable_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_mode <= 1'b0; + proc_precision[1:0] <= 2'b01; + end else begin +// Register: NVDLA_CMAC_A_D_MISC_CFG_0 Field: conv_mode + if (nvdla_cmac_a_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CMAC_A_D_MISC_CFG_0 Field: proc_precision + if (nvdla_cmac_a_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Not generating flops for field NVDLA_CMAC_A_D_OP_ENABLE_0::op_en (to be implemented outside) + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h700c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_misc_cfg_0_out, nvdla_cmac_a_d_misc_cfg_0_out); + (32'h7008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_op_enable_0_out, nvdla_cmac_a_d_op_enable_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CMAC_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v.vcp new file mode 100644 index 0000000..f863cb3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v.vcp @@ -0,0 +1,123 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_REG_dual.v +module NV_NVDLA_CMAC_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,conv_mode + ,proc_precision + ,op_en_trigger + ,op_en + ); +wire [31:0] nvdla_cmac_a_d_misc_cfg_0_out; +wire [31:0] nvdla_cmac_a_d_op_enable_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output conv_mode; +output [1:0] proc_precision; +output op_en_trigger; +// Read-only register inputs +input op_en; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg conv_mode; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cmac_a_d_misc_cfg_0_wren = (reg_offset_wr == (32'h700c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cmac_a_d_op_enable_0_wren = (reg_offset_wr == (32'h7008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cmac_a_d_misc_cfg_0_out[31:0] = { 18'b0, proc_precision, 11'b0, conv_mode }; +assign nvdla_cmac_a_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign op_en_trigger = nvdla_cmac_a_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cmac_a_d_misc_cfg_0_out + or nvdla_cmac_a_d_op_enable_0_out + ) begin + case (reg_offset_rd_int) + (32'h700c & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_d_misc_cfg_0_out ; + end + (32'h7008 & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_d_op_enable_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_mode <= 1'b0; + proc_precision[1:0] <= 2'b01; + end else begin +// Register: NVDLA_CMAC_A_D_MISC_CFG_0 Field: conv_mode + if (nvdla_cmac_a_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CMAC_A_D_MISC_CFG_0 Field: proc_precision + if (nvdla_cmac_a_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Not generating flops for field NVDLA_CMAC_A_D_OP_ENABLE_0::op_en (to be implemented outside) + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h700c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_misc_cfg_0_out, nvdla_cmac_a_d_misc_cfg_0_out); + (32'h7008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_d_op_enable_0_out, nvdla_cmac_a_d_op_enable_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CMAC_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v new file mode 100644 index 0000000..d5b13ac --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_REG_single.v +module NV_NVDLA_CMAC_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cmac_a_s_pointer_0_out; +wire [31:0] nvdla_cmac_a_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cmac_a_s_pointer_0_wren = (reg_offset_wr == (32'h7004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cmac_a_s_status_0_wren = (reg_offset_wr == (32'h7000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cmac_a_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cmac_a_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cmac_a_s_pointer_0_out + or nvdla_cmac_a_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h7004 & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_s_pointer_0_out ; + end + (32'h7000 & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CMAC_A_S_POINTER_0::consumer +// Register: NVDLA_CMAC_A_S_POINTER_0 Field: producer + if (nvdla_cmac_a_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CMAC_A_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CMAC_A_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h7004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_s_pointer_0_out, nvdla_cmac_a_s_pointer_0_out); + (32'h7000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CMAC_A_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CMAC_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v.vcp new file mode 100644 index 0000000..d5b13ac --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_REG_single.v +module NV_NVDLA_CMAC_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_cmac_a_s_pointer_0_out; +wire [31:0] nvdla_cmac_a_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_cmac_a_s_pointer_0_wren = (reg_offset_wr == (32'h7004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_cmac_a_s_status_0_wren = (reg_offset_wr == (32'h7000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_cmac_a_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_cmac_a_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_cmac_a_s_pointer_0_out + or nvdla_cmac_a_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h7004 & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_s_pointer_0_out ; + end + (32'h7000 & 32'h00000fff): begin + reg_rd_data = nvdla_cmac_a_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CMAC_A_S_POINTER_0::consumer +// Register: NVDLA_CMAC_A_S_POINTER_0 Field: producer + if (nvdla_cmac_a_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CMAC_A_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CMAC_A_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h7004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CMAC_A_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_cmac_a_s_pointer_0_out, nvdla_cmac_a_s_pointer_0_out); + (32'h7000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CMAC_A_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CMAC_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v new file mode 100644 index 0000000..c46c455 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v @@ -0,0 +1,939 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_op_en //|< i +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i} //|< i) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_data0 //|< i +,sc2mac_dat_data1 //|< i +,sc2mac_dat_data2 //|< i +,sc2mac_dat_data3 //|< i +,sc2mac_dat_data4 //|< i +,sc2mac_dat_data5 //|< i +,sc2mac_dat_data6 //|< i +,sc2mac_dat_data7 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_mask //|< i + ,sc2mac_dat_pd //|< i + ,sc2mac_dat_pvld //|< i +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i} //|< i) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_data0 //|< i +,sc2mac_wt_data1 //|< i +,sc2mac_wt_data2 //|< i +,sc2mac_wt_data3 //|< i +,sc2mac_wt_data4 //|< i +,sc2mac_wt_data5 //|< i +,sc2mac_wt_data6 //|< i +,sc2mac_wt_data7 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_mask //|< i + ,sc2mac_wt_pvld //|< i + ,sc2mac_wt_sel //|< i + ,slcg_op_en //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,dp2reg_done //|> o +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_data0 //|< i +,mac2accu_data1 //|< i +,mac2accu_data2 //|< i +,mac2accu_data3 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_mask //|> o + ,mac2accu_mode //|> o + ,mac2accu_pd //|> o + ,mac2accu_pvld //|> o + ); +// +// NV_NVDLA_CMAC_core_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sc2mac_dat_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_mask; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_dat_data0; +input [8 -1:0] sc2mac_dat_data1; +input [8 -1:0] sc2mac_dat_data2; +input [8 -1:0] sc2mac_dat_data3; +input [8 -1:0] sc2mac_dat_data4; +input [8 -1:0] sc2mac_dat_data5; +input [8 -1:0] sc2mac_dat_data6; +input [8 -1:0] sc2mac_dat_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] sc2mac_dat_pd; +input sc2mac_wt_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_mask; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_wt_data0; +input [8 -1:0] sc2mac_wt_data1; +input [8 -1:0] sc2mac_wt_data2; +input [8 -1:0] sc2mac_wt_data3; +input [8 -1:0] sc2mac_wt_data4; +input [8 -1:0] sc2mac_wt_data5; +input [8 -1:0] sc2mac_wt_data6; +input [8 -1:0] sc2mac_wt_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2 -1:0] sc2mac_wt_sel; +output mac2accu_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_mask; +output mac2accu_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_data${i}; //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [19 -1:0] mac2accu_data0; //|< i +output [19 -1:0] mac2accu_data1; //|< i +output [19 -1:0] mac2accu_data2; //|< i +output [19 -1:0] mac2accu_data3; //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] mac2accu_pd; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +output dp2reg_done; +//Port for SLCG +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +input [3+8/2 -1:0] slcg_op_en; +wire cfg_is_wg; +wire cfg_reg_en; +// interface with register config +//========================================================== +//: my $i=8/2; +//: print qq( +//: wire nvdla_op_gated_clk_${i}; ); +//: print qq( +//: NV_NVDLA_CMAC_CORE_cfg u_cfg ( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.dp2reg_done (dp2reg_done) //|< o +//: ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< i +//: ,.reg2dp_op_en (reg2dp_op_en) //|< i +//: ,.cfg_is_wg (cfg_is_wg) //|> w +//: ,.cfg_reg_en (cfg_reg_en) //|> w +//: ); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire nvdla_op_gated_clk_4; +NV_NVDLA_CMAC_CORE_cfg u_cfg ( +.nvdla_core_clk (nvdla_op_gated_clk_4) //|< w +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.dp2reg_done (dp2reg_done) //|< o +,.reg2dp_conv_mode (reg2dp_conv_mode) //|< i +,.reg2dp_op_en (reg2dp_op_en) //|< i +,.cfg_is_wg (cfg_is_wg) //|> w +,.cfg_reg_en (cfg_reg_en) //|> w +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire in_dat_pvld; +assign mac2accu_mode = 1'b0; +wire [8:0] in_dat_pd; +wire [8 -1:0] in_wt_mask; +wire in_wt_pvld; +wire [8/2 -1:0] in_wt_sel; +wire [8 -1:0] in_dat_mask; +wire in_dat_stripe_end; +wire in_dat_stripe_st; +wire [8/2 -1:0] out_mask; +//: for (my $i=0; $i < 8; ++$i) { +//: print qq( +//: wire [8 -1:0] in_dat_data${i}; +//: wire [8 -1:0] in_wt_data${i}; ); +//: } +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: wire [8*8 -1:0] dat${i}_actv_data; +//: wire [8 -1:0] dat${i}_actv_nz; +//: wire [8 -1:0] dat${i}_actv_pvld; +//: wire [8 -1:0] dat${i}_pre_mask; +//: wire dat${i}_pre_pvld; +//: wire dat${i}_pre_stripe_end; +//: wire dat${i}_pre_stripe_st; +//: wire [8*8 -1:0] wt${i}_actv_data; +//: wire [8 -1:0] wt${i}_actv_nz; +//: wire [8 -1:0] wt${i}_actv_pvld; +//: wire [8 -1:0] wt${i}_sd_mask; +//: wire wt${i}_sd_pvld; +//: ); +//: } +//: my $i=(3 +2 -3); +//: &eperl::retime("-stage ${i} -wid 9 -i in_dat_pd -o out_pd -cg_en_i in_dat_pvld -cg_en_o out_pvld -cg_en_rtm"); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8 -1:0] in_dat_data0; +wire [8 -1:0] in_wt_data0; +wire [8 -1:0] in_dat_data1; +wire [8 -1:0] in_wt_data1; +wire [8 -1:0] in_dat_data2; +wire [8 -1:0] in_wt_data2; +wire [8 -1:0] in_dat_data3; +wire [8 -1:0] in_wt_data3; +wire [8 -1:0] in_dat_data4; +wire [8 -1:0] in_wt_data4; +wire [8 -1:0] in_dat_data5; +wire [8 -1:0] in_wt_data5; +wire [8 -1:0] in_dat_data6; +wire [8 -1:0] in_wt_data6; +wire [8 -1:0] in_dat_data7; +wire [8 -1:0] in_wt_data7; +wire [8*8 -1:0] dat0_actv_data; +wire [8 -1:0] dat0_actv_nz; +wire [8 -1:0] dat0_actv_pvld; +wire [8 -1:0] dat0_pre_mask; +wire dat0_pre_pvld; +wire dat0_pre_stripe_end; +wire dat0_pre_stripe_st; +wire [8*8 -1:0] wt0_actv_data; +wire [8 -1:0] wt0_actv_nz; +wire [8 -1:0] wt0_actv_pvld; +wire [8 -1:0] wt0_sd_mask; +wire wt0_sd_pvld; + +wire [8*8 -1:0] dat1_actv_data; +wire [8 -1:0] dat1_actv_nz; +wire [8 -1:0] dat1_actv_pvld; +wire [8 -1:0] dat1_pre_mask; +wire dat1_pre_pvld; +wire dat1_pre_stripe_end; +wire dat1_pre_stripe_st; +wire [8*8 -1:0] wt1_actv_data; +wire [8 -1:0] wt1_actv_nz; +wire [8 -1:0] wt1_actv_pvld; +wire [8 -1:0] wt1_sd_mask; +wire wt1_sd_pvld; + +wire [8*8 -1:0] dat2_actv_data; +wire [8 -1:0] dat2_actv_nz; +wire [8 -1:0] dat2_actv_pvld; +wire [8 -1:0] dat2_pre_mask; +wire dat2_pre_pvld; +wire dat2_pre_stripe_end; +wire dat2_pre_stripe_st; +wire [8*8 -1:0] wt2_actv_data; +wire [8 -1:0] wt2_actv_nz; +wire [8 -1:0] wt2_actv_pvld; +wire [8 -1:0] wt2_sd_mask; +wire wt2_sd_pvld; + +wire [8*8 -1:0] dat3_actv_data; +wire [8 -1:0] dat3_actv_nz; +wire [8 -1:0] dat3_actv_pvld; +wire [8 -1:0] dat3_pre_mask; +wire dat3_pre_pvld; +wire dat3_pre_stripe_end; +wire dat3_pre_stripe_st; +wire [8*8 -1:0] wt3_actv_data; +wire [8 -1:0] wt3_actv_nz; +wire [8 -1:0] wt3_actv_pvld; +wire [8 -1:0] wt3_sd_mask; +wire wt3_sd_pvld; +reg [9-1:0] in_dat_pd_d1; +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld)) begin + in_dat_pd_d1[9-1:0] <= in_dat_pd[9-1:0]; + end +end + +reg in_dat_pvld_d1; +always @(posedge nvdla_core_clk) begin + in_dat_pvld_d1 <= in_dat_pvld; +end + +reg [9-1:0] in_dat_pd_d2; +always @(posedge nvdla_core_clk) begin + if ((in_dat_pvld_d1)) begin + in_dat_pd_d2[9-1:0] <= in_dat_pd_d1[9-1:0]; + end +end + +reg in_dat_pvld_d2; +always @(posedge nvdla_core_clk) begin + in_dat_pvld_d2 <= in_dat_pvld_d1; +end + +wire [9-1:0] out_pd; +assign out_pd = in_dat_pd_d2; + +wire out_pvld; +assign out_pvld = in_dat_pvld_d2; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//========================================================== +// input retiming logic +//========================================================== + NV_NVDLA_CMAC_CORE_rt_in u_rt_in ( +//: my $i= 8/2; +//: print qq( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +.nvdla_core_clk (nvdla_op_gated_clk_4) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_data0 (sc2mac_dat_data0) //|< i +,.sc2mac_dat_data1 (sc2mac_dat_data1) //|< i +,.sc2mac_dat_data2 (sc2mac_dat_data2) //|< i +,.sc2mac_dat_data3 (sc2mac_dat_data3) //|< i +,.sc2mac_dat_data4 (sc2mac_dat_data4) //|< i +,.sc2mac_dat_data5 (sc2mac_dat_data5) //|< i +,.sc2mac_dat_data6 (sc2mac_dat_data6) //|< i +,.sc2mac_dat_data7 (sc2mac_dat_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i + ,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i + ,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_data0 (sc2mac_wt_data0) //|< i +,.sc2mac_wt_data1 (sc2mac_wt_data1) //|< i +,.sc2mac_wt_data2 (sc2mac_wt_data2) //|< i +,.sc2mac_wt_data3 (sc2mac_wt_data3) //|< i +,.sc2mac_wt_data4 (sc2mac_wt_data4) //|< i +,.sc2mac_wt_data5 (sc2mac_wt_data5) //|< i +,.sc2mac_wt_data6 (sc2mac_wt_data6) //|< i +,.sc2mac_wt_data7 (sc2mac_wt_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i + ,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i + ,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_dat_data${i} (in_dat_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.in_dat_data0 (in_dat_data0) //|< i +,.in_dat_data1 (in_dat_data1) //|< i +,.in_dat_data2 (in_dat_data2) //|< i +,.in_dat_data3 (in_dat_data3) //|< i +,.in_dat_data4 (in_dat_data4) //|< i +,.in_dat_data5 (in_dat_data5) //|< i +,.in_dat_data6 (in_dat_data6) //|< i +,.in_dat_data7 (in_dat_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.in_dat_mask (in_dat_mask) //|> w + ,.in_dat_pd (in_dat_pd) //|> w + ,.in_dat_pvld (in_dat_pvld) //|> w + ,.in_dat_stripe_end (in_dat_stripe_end) //|> w + ,.in_dat_stripe_st (in_dat_stripe_st) //|> w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_wt_data${i} (in_wt_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.in_wt_data0 (in_wt_data0) //|< i +,.in_wt_data1 (in_wt_data1) //|< i +,.in_wt_data2 (in_wt_data2) //|< i +,.in_wt_data3 (in_wt_data3) //|< i +,.in_wt_data4 (in_wt_data4) //|< i +,.in_wt_data5 (in_wt_data5) //|< i +,.in_wt_data6 (in_wt_data6) //|< i +,.in_wt_data7 (in_wt_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.in_wt_mask (in_wt_mask) //|> w + ,.in_wt_pvld (in_wt_pvld) //|> w + ,.in_wt_sel (in_wt_sel) //|> w + ); +//========================================================== +// input shadow and active pipeline +//========================================================== +//: my $i = 8/2 +1; +//: print qq( +//: wire nvdla_op_gated_clk_${i}; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire nvdla_op_gated_clk_5; +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_CMAC_CORE_active u_active ( +//: my $i=8/2 +1; +//: print qq( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +.nvdla_core_clk (nvdla_op_gated_clk_5) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_dat_data${i} (in_dat_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.in_dat_data0 (in_dat_data0) //|< i +,.in_dat_data1 (in_dat_data1) //|< i +,.in_dat_data2 (in_dat_data2) //|< i +,.in_dat_data3 (in_dat_data3) //|< i +,.in_dat_data4 (in_dat_data4) //|< i +,.in_dat_data5 (in_dat_data5) //|< i +,.in_dat_data6 (in_dat_data6) //|< i +,.in_dat_data7 (in_dat_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.in_dat_mask (in_dat_mask) //|< w + ,.in_dat_pvld (in_dat_pvld) //|< w + ,.in_dat_stripe_end (in_dat_stripe_end) //|< w + ,.in_dat_stripe_st (in_dat_stripe_st) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_wt_data${i} (in_wt_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.in_wt_data0 (in_wt_data0) //|< i +,.in_wt_data1 (in_wt_data1) //|< i +,.in_wt_data2 (in_wt_data2) //|< i +,.in_wt_data3 (in_wt_data3) //|< i +,.in_wt_data4 (in_wt_data4) //|< i +,.in_wt_data5 (in_wt_data5) //|< i +,.in_wt_data6 (in_wt_data6) //|< i +,.in_wt_data7 (in_wt_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.in_wt_mask (in_wt_mask) //|< w + ,.in_wt_pvld (in_wt_pvld) //|< w + ,.in_wt_sel (in_wt_sel) //|< w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.dat${i}_actv_data (dat${i}_actv_data) //|> w +//: ,.dat${i}_actv_nz (dat${i}_actv_nz) //|> w +//: ,.dat${i}_actv_pvld (dat${i}_actv_pvld) //|> w +//: ,.dat${i}_pre_mask (dat${i}_pre_mask) //|> w +//: ,.dat${i}_pre_pvld (dat${i}_pre_pvld) //|> w +//: ,.dat${i}_pre_stripe_end (dat${i}_pre_stripe_end) //|> w +//: ,.dat${i}_pre_stripe_st (dat${i}_pre_stripe_st) //|> w +//: ) +//: } +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.wt${i}_actv_data (wt${i}_actv_data) //|> w +//: ,.wt${i}_actv_nz (wt${i}_actv_nz) //|> w +//: ,.wt${i}_actv_pvld (wt${i}_actv_pvld) //|> w +//: ,.wt${i}_sd_mask (wt${i}_sd_mask) //|> w +//: ,.wt${i}_sd_pvld (wt${i}_sd_pvld) //|> w +//: ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dat0_actv_data (dat0_actv_data) //|> w +,.dat0_actv_nz (dat0_actv_nz) //|> w +,.dat0_actv_pvld (dat0_actv_pvld) //|> w +,.dat0_pre_mask (dat0_pre_mask) //|> w +,.dat0_pre_pvld (dat0_pre_pvld) //|> w +,.dat0_pre_stripe_end (dat0_pre_stripe_end) //|> w +,.dat0_pre_stripe_st (dat0_pre_stripe_st) //|> w + +,.dat1_actv_data (dat1_actv_data) //|> w +,.dat1_actv_nz (dat1_actv_nz) //|> w +,.dat1_actv_pvld (dat1_actv_pvld) //|> w +,.dat1_pre_mask (dat1_pre_mask) //|> w +,.dat1_pre_pvld (dat1_pre_pvld) //|> w +,.dat1_pre_stripe_end (dat1_pre_stripe_end) //|> w +,.dat1_pre_stripe_st (dat1_pre_stripe_st) //|> w + +,.dat2_actv_data (dat2_actv_data) //|> w +,.dat2_actv_nz (dat2_actv_nz) //|> w +,.dat2_actv_pvld (dat2_actv_pvld) //|> w +,.dat2_pre_mask (dat2_pre_mask) //|> w +,.dat2_pre_pvld (dat2_pre_pvld) //|> w +,.dat2_pre_stripe_end (dat2_pre_stripe_end) //|> w +,.dat2_pre_stripe_st (dat2_pre_stripe_st) //|> w + +,.dat3_actv_data (dat3_actv_data) //|> w +,.dat3_actv_nz (dat3_actv_nz) //|> w +,.dat3_actv_pvld (dat3_actv_pvld) //|> w +,.dat3_pre_mask (dat3_pre_mask) //|> w +,.dat3_pre_pvld (dat3_pre_pvld) //|> w +,.dat3_pre_stripe_end (dat3_pre_stripe_end) //|> w +,.dat3_pre_stripe_st (dat3_pre_stripe_st) //|> w + +,.wt0_actv_data (wt0_actv_data) //|> w +,.wt0_actv_nz (wt0_actv_nz) //|> w +,.wt0_actv_pvld (wt0_actv_pvld) //|> w +,.wt0_sd_mask (wt0_sd_mask) //|> w +,.wt0_sd_pvld (wt0_sd_pvld) //|> w + +,.wt1_actv_data (wt1_actv_data) //|> w +,.wt1_actv_nz (wt1_actv_nz) //|> w +,.wt1_actv_pvld (wt1_actv_pvld) //|> w +,.wt1_sd_mask (wt1_sd_mask) //|> w +,.wt1_sd_pvld (wt1_sd_pvld) //|> w + +,.wt2_actv_data (wt2_actv_data) //|> w +,.wt2_actv_nz (wt2_actv_nz) //|> w +,.wt2_actv_pvld (wt2_actv_pvld) //|> w +,.wt2_sd_mask (wt2_sd_mask) //|> w +,.wt2_sd_pvld (wt2_sd_pvld) //|> w + +,.wt3_actv_data (wt3_actv_data) //|> w +,.wt3_actv_nz (wt3_actv_nz) //|> w +,.wt3_actv_pvld (wt3_actv_pvld) //|> w +,.wt3_sd_mask (wt3_sd_mask) //|> w +,.wt3_sd_pvld (wt3_sd_pvld) //|> w + +//| eperl: generated_end (DO NOT EDIT ABOVE) +); +//========================================================== +// MAC CELLs +//========================================================== +//: my $total_num = 8/2; +//: for(my $i = 0; $i < $total_num; $i ++) { +//: print qq { +//: wire nvdla_op_gated_clk_${i}; +//: wire nvdla_wg_gated_clk_${i}; +//: wire [19 -1:0] out_data${i}; +//: NV_NVDLA_CMAC_CORE_mac u_mac_${i} ( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w +//: ,.nvdla_wg_clk (nvdla_op_gated_clk_${i}) //|< w , need update for winograd +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.cfg_is_wg (cfg_is_wg) //|< w +//: ,.cfg_reg_en (cfg_reg_en) //|< w +//: ,.dat_actv_data (dat${i}_actv_data) //|< w +//: ,.dat_actv_nz (dat${i}_actv_nz) //|< w +//: ,.dat_actv_pvld (dat${i}_actv_pvld) //|< w +//: ,.wt_actv_data (wt${i}_actv_data) //|< w +//: ,.wt_actv_nz (wt${i}_actv_nz) //|< w +//: ,.wt_actv_pvld (wt${i}_actv_pvld) //|< w +//: ,.mac_out_data (out_data${i}) //|> w +//: ,.mac_out_pvld (out_mask[${i}]) //|> w +//: ); +//: } +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire nvdla_op_gated_clk_0; +wire nvdla_wg_gated_clk_0; +wire [19 -1:0] out_data0; +NV_NVDLA_CMAC_CORE_mac u_mac_0 ( +.nvdla_core_clk (nvdla_op_gated_clk_0) //|< w +,.nvdla_wg_clk (nvdla_op_gated_clk_0) //|< w , need update for winograd +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.cfg_is_wg (cfg_is_wg) //|< w +,.cfg_reg_en (cfg_reg_en) //|< w +,.dat_actv_data (dat0_actv_data) //|< w +,.dat_actv_nz (dat0_actv_nz) //|< w +,.dat_actv_pvld (dat0_actv_pvld) //|< w +,.wt_actv_data (wt0_actv_data) //|< w +,.wt_actv_nz (wt0_actv_nz) //|< w +,.wt_actv_pvld (wt0_actv_pvld) //|< w +,.mac_out_data (out_data0) //|> w +,.mac_out_pvld (out_mask[0]) //|> w +); + +wire nvdla_op_gated_clk_1; +wire nvdla_wg_gated_clk_1; +wire [19 -1:0] out_data1; +NV_NVDLA_CMAC_CORE_mac u_mac_1 ( +.nvdla_core_clk (nvdla_op_gated_clk_1) //|< w +,.nvdla_wg_clk (nvdla_op_gated_clk_1) //|< w , need update for winograd +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.cfg_is_wg (cfg_is_wg) //|< w +,.cfg_reg_en (cfg_reg_en) //|< w +,.dat_actv_data (dat1_actv_data) //|< w +,.dat_actv_nz (dat1_actv_nz) //|< w +,.dat_actv_pvld (dat1_actv_pvld) //|< w +,.wt_actv_data (wt1_actv_data) //|< w +,.wt_actv_nz (wt1_actv_nz) //|< w +,.wt_actv_pvld (wt1_actv_pvld) //|< w +,.mac_out_data (out_data1) //|> w +,.mac_out_pvld (out_mask[1]) //|> w +); + +wire nvdla_op_gated_clk_2; +wire nvdla_wg_gated_clk_2; +wire [19 -1:0] out_data2; +NV_NVDLA_CMAC_CORE_mac u_mac_2 ( +.nvdla_core_clk (nvdla_op_gated_clk_2) //|< w +,.nvdla_wg_clk (nvdla_op_gated_clk_2) //|< w , need update for winograd +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.cfg_is_wg (cfg_is_wg) //|< w +,.cfg_reg_en (cfg_reg_en) //|< w +,.dat_actv_data (dat2_actv_data) //|< w +,.dat_actv_nz (dat2_actv_nz) //|< w +,.dat_actv_pvld (dat2_actv_pvld) //|< w +,.wt_actv_data (wt2_actv_data) //|< w +,.wt_actv_nz (wt2_actv_nz) //|< w +,.wt_actv_pvld (wt2_actv_pvld) //|< w +,.mac_out_data (out_data2) //|> w +,.mac_out_pvld (out_mask[2]) //|> w +); + +wire nvdla_op_gated_clk_3; +wire nvdla_wg_gated_clk_3; +wire [19 -1:0] out_data3; +NV_NVDLA_CMAC_CORE_mac u_mac_3 ( +.nvdla_core_clk (nvdla_op_gated_clk_3) //|< w +,.nvdla_wg_clk (nvdla_op_gated_clk_3) //|< w , need update for winograd +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.cfg_is_wg (cfg_is_wg) //|< w +,.cfg_reg_en (cfg_reg_en) //|< w +,.dat_actv_data (dat3_actv_data) //|< w +,.dat_actv_nz (dat3_actv_nz) //|< w +,.dat_actv_pvld (dat3_actv_pvld) //|< w +,.wt_actv_data (wt3_actv_data) //|< w +,.wt_actv_nz (wt3_actv_nz) //|< w +,.wt_actv_pvld (wt3_actv_pvld) //|< w +,.mac_out_data (out_data3) //|> w +,.mac_out_pvld (out_mask[3]) //|> w +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//========================================================== +// output retiming logic +//========================================================== +//: my $i = 8/2 +2; +//: print qq( +//: wire nvdla_op_gated_clk_${i}; ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire nvdla_op_gated_clk_6; +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_CMAC_CORE_rt_out u_rt_out ( +//: my $i=8/2 +2; +//: print qq( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w +//: ,.nvdla_wg_clk (nvdla_op_gated_clk_${i}) //|< w ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +.nvdla_core_clk (nvdla_op_gated_clk_6) //|< w +,.nvdla_wg_clk (nvdla_op_gated_clk_6) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_is_wg (cfg_is_wg) //|< w + ,.cfg_reg_en (cfg_reg_en) //|< w +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,.out_data${i} (out_data${i}) //|< w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.out_data0 (out_data0) //|< w +,.out_data1 (out_data1) //|< w +,.out_data2 (out_data2) //|< w +,.out_data3 (out_data3) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.out_mask (out_mask) //|< w + ,.out_pd (out_pd) //|< w + ,.out_pvld (out_pvld) //|< w + ,.dp2reg_done (dp2reg_done) //|> o +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac2accu_data0 (mac2accu_data0) //|> o +,.mac2accu_data1 (mac2accu_data1) //|> o +,.mac2accu_data2 (mac2accu_data2) //|> o +,.mac2accu_data3 (mac2accu_data3) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac2accu_mask (mac2accu_mask) //|> o + ,.mac2accu_pd (mac2accu_pd) //|> o + ,.mac2accu_pvld (mac2accu_pvld) //|> o + ); +//========================================================== +// SLCG groups +//========================================================== +//: for(my $i = 0; $i < 3+8/2; $i ++) { +//: print qq { +//: NV_NVDLA_CMAC_CORE_slcg u_slcg_op_${i} ( +//: .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +//: ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.slcg_en_src_0 (slcg_op_en[${i}]) //|< i +//: ,.slcg_en_src_1 (1'b1) //|< ? +//: ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +//: ,.nvdla_core_gated_clk (nvdla_op_gated_clk_${i}) //|> w +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_0 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[0]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w +); + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_1 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[1]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w +); + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_2 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[2]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w +); + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_3 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[3]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_3) //|> w +); + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_4 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[4]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_4) //|> w +); + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_5 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[5]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_5) //|> w +); + +NV_NVDLA_CMAC_CORE_slcg u_slcg_op_6 ( +.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +,.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.slcg_en_src_0 (slcg_op_en[6]) //|< i +,.slcg_en_src_1 (1'b1) //|< ? +,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +,.nvdla_core_gated_clk (nvdla_op_gated_clk_6) //|> w +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifndef SYNTHESIS +wire [8:0] dbg_mac2accu_pd; +wire dbg_mac2accu_pvld; +wire [8:0] dbg_out_pd_d0; +wire dbg_out_pvld_d0; +`endif +//////// for valid forwarding /////// +`ifndef SYNTHESIS +//: print qq ( +//: assign dbg_out_pvld_d0 = out_pvld; +//: assign dbg_out_pd_d0 = out_pd; +//: ); +//: +//: my $delay = (2 +2 +3 +2)-2 -(3 +2 -3); +//: my $i; +//: +//: for($i = 0; $i < $delay; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-q dbg_out_pvld_d${j} -d dbg_out_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q dbg_out_pd_d${j} -en dbg_out_pvld_d${i} -d dbg_out_pd_d${i}"); +//: } +//: +//: print qq ( +//: assign dbg_mac2accu_pvld = dbg_out_pvld_d${delay}; +//: assign dbg_mac2accu_pd = dbg_out_pd_d${delay}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dbg_out_pvld_d0 = out_pvld; +assign dbg_out_pd_d0 = out_pd; +reg dbg_out_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pvld_d1 <= 'b0; + end else begin + dbg_out_pvld_d1 <= dbg_out_pvld_d0; + end +end +reg [8:0] dbg_out_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pd_d1 <= 'b0; + end else begin + if ((dbg_out_pvld_d0) == 1'b1) begin + dbg_out_pd_d1 <= dbg_out_pd_d0; + // VCS coverage off + end else if ((dbg_out_pvld_d0) == 1'b0) begin + end else begin + dbg_out_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg dbg_out_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pvld_d2 <= 'b0; + end else begin + dbg_out_pvld_d2 <= dbg_out_pvld_d1; + end +end +reg [8:0] dbg_out_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pd_d2 <= 'b0; + end else begin + if ((dbg_out_pvld_d1) == 1'b1) begin + dbg_out_pd_d2 <= dbg_out_pd_d1; + // VCS coverage off + end else if ((dbg_out_pvld_d1) == 1'b0) begin + end else begin + dbg_out_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg dbg_out_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pvld_d3 <= 'b0; + end else begin + dbg_out_pvld_d3 <= dbg_out_pvld_d2; + end +end +reg [8:0] dbg_out_pd_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pd_d3 <= 'b0; + end else begin + if ((dbg_out_pvld_d2) == 1'b1) begin + dbg_out_pd_d3 <= dbg_out_pd_d2; + // VCS coverage off + end else if ((dbg_out_pvld_d2) == 1'b0) begin + end else begin + dbg_out_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +reg dbg_out_pvld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pvld_d4 <= 'b0; + end else begin + dbg_out_pvld_d4 <= dbg_out_pvld_d3; + end +end +reg [8:0] dbg_out_pd_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pd_d4 <= 'b0; + end else begin + if ((dbg_out_pvld_d3) == 1'b1) begin + dbg_out_pd_d4 <= dbg_out_pd_d3; + // VCS coverage off + end else if ((dbg_out_pvld_d3) == 1'b0) begin + end else begin + dbg_out_pd_d4 <= 'bx; + // VCS coverage on + end + end +end +reg dbg_out_pvld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pvld_d5 <= 'b0; + end else begin + dbg_out_pvld_d5 <= dbg_out_pvld_d4; + end +end +reg [8:0] dbg_out_pd_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_out_pd_d5 <= 'b0; + end else begin + if ((dbg_out_pvld_d4) == 1'b1) begin + dbg_out_pd_d5 <= dbg_out_pd_d4; + // VCS coverage off + end else if ((dbg_out_pvld_d4) == 1'b0) begin + end else begin + dbg_out_pd_d5 <= 'bx; + // VCS coverage on + end + end +end + +assign dbg_mac2accu_pvld = dbg_out_pvld_d5; +assign dbg_mac2accu_pd = dbg_out_pd_d5; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v.vcp new file mode 100644 index 0000000..b328799 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v.vcp @@ -0,0 +1,323 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_op_en //|< i +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i} //|< i) +//: } + ,sc2mac_dat_mask //|< i + ,sc2mac_dat_pd //|< i + ,sc2mac_dat_pvld //|< i +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i} //|< i) +//: } + ,sc2mac_wt_mask //|< i + ,sc2mac_wt_pvld //|< i + ,sc2mac_wt_sel //|< i + ,slcg_op_en //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,dp2reg_done //|> o +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_data${i} //|< i ) +//: } + ,mac2accu_mask //|> o + ,mac2accu_mode //|> o + ,mac2accu_pd //|> o + ,mac2accu_pvld //|> o + ); +// +// NV_NVDLA_CMAC_core_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sc2mac_dat_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_mask; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i}; ) +//: } +input [8:0] sc2mac_dat_pd; +input sc2mac_wt_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_mask; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i}; ) +//: } +input [8/2 -1:0] sc2mac_wt_sel; +output mac2accu_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_mask; +output mac2accu_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_data${i}; //|< i ) +//: } +output [8:0] mac2accu_pd; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +output dp2reg_done; +//Port for SLCG +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +input [3+8/2 -1:0] slcg_op_en; +wire cfg_is_wg; +wire cfg_reg_en; +// interface with register config +//========================================================== +//: my $i=8/2; +//: print qq( +//: wire nvdla_op_gated_clk_${i}; ); +//: print qq( +//: NV_NVDLA_CMAC_CORE_cfg u_cfg ( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.dp2reg_done (dp2reg_done) //|< o +//: ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< i +//: ,.reg2dp_op_en (reg2dp_op_en) //|< i +//: ,.cfg_is_wg (cfg_is_wg) //|> w +//: ,.cfg_reg_en (cfg_reg_en) //|> w +//: ); +//: ); +wire in_dat_pvld; +assign mac2accu_mode = 1'b0; +wire [8:0] in_dat_pd; +wire [8 -1:0] in_wt_mask; +wire in_wt_pvld; +wire [8/2 -1:0] in_wt_sel; +wire [8 -1:0] in_dat_mask; +wire in_dat_stripe_end; +wire in_dat_stripe_st; +wire [8/2 -1:0] out_mask; +//: for (my $i=0; $i < 8; ++$i) { +//: print qq( +//: wire [8 -1:0] in_dat_data${i}; +//: wire [8 -1:0] in_wt_data${i}; ); +//: } +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: wire [8*8 -1:0] dat${i}_actv_data; +//: wire [8 -1:0] dat${i}_actv_nz; +//: wire [8 -1:0] dat${i}_actv_pvld; +//: wire [8 -1:0] dat${i}_pre_mask; +//: wire dat${i}_pre_pvld; +//: wire dat${i}_pre_stripe_end; +//: wire dat${i}_pre_stripe_st; +//: wire [8*8 -1:0] wt${i}_actv_data; +//: wire [8 -1:0] wt${i}_actv_nz; +//: wire [8 -1:0] wt${i}_actv_pvld; +//: wire [8 -1:0] wt${i}_sd_mask; +//: wire wt${i}_sd_pvld; +//: ); +//: } +//: my $i=(3 +2 -3); +//: &eperl::retime("-stage ${i} -wid 9 -i in_dat_pd -o out_pd -cg_en_i in_dat_pvld -cg_en_o out_pvld -cg_en_rtm"); +//========================================================== +// input retiming logic +//========================================================== + NV_NVDLA_CMAC_CORE_rt_in u_rt_in ( +//: my $i= 8/2; +//: print qq( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w ); + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i ) +//: } + ,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i + ,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i + ,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i ) +//: } + ,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i + ,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i + ,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_dat_data${i} (in_dat_data${i}) //|< i ) +//: } + ,.in_dat_mask (in_dat_mask) //|> w + ,.in_dat_pd (in_dat_pd) //|> w + ,.in_dat_pvld (in_dat_pvld) //|> w + ,.in_dat_stripe_end (in_dat_stripe_end) //|> w + ,.in_dat_stripe_st (in_dat_stripe_st) //|> w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_wt_data${i} (in_wt_data${i}) //|< i ) +//: } + ,.in_wt_mask (in_wt_mask) //|> w + ,.in_wt_pvld (in_wt_pvld) //|> w + ,.in_wt_sel (in_wt_sel) //|> w + ); +//========================================================== +// input shadow and active pipeline +//========================================================== +//: my $i = 8/2 +1; +//: print qq( +//: wire nvdla_op_gated_clk_${i}; ); +NV_NVDLA_CMAC_CORE_active u_active ( +//: my $i=8/2 +1; +//: print qq( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w ); + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_dat_data${i} (in_dat_data${i}) //|< i ) +//: } + ,.in_dat_mask (in_dat_mask) //|< w + ,.in_dat_pvld (in_dat_pvld) //|< w + ,.in_dat_stripe_end (in_dat_stripe_end) //|< w + ,.in_dat_stripe_st (in_dat_stripe_st) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.in_wt_data${i} (in_wt_data${i}) //|< i ) +//: } + ,.in_wt_mask (in_wt_mask) //|< w + ,.in_wt_pvld (in_wt_pvld) //|< w + ,.in_wt_sel (in_wt_sel) //|< w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.dat${i}_actv_data (dat${i}_actv_data) //|> w +//: ,.dat${i}_actv_nz (dat${i}_actv_nz) //|> w +//: ,.dat${i}_actv_pvld (dat${i}_actv_pvld) //|> w +//: ,.dat${i}_pre_mask (dat${i}_pre_mask) //|> w +//: ,.dat${i}_pre_pvld (dat${i}_pre_pvld) //|> w +//: ,.dat${i}_pre_stripe_end (dat${i}_pre_stripe_end) //|> w +//: ,.dat${i}_pre_stripe_st (dat${i}_pre_stripe_st) //|> w +//: ) +//: } +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.wt${i}_actv_data (wt${i}_actv_data) //|> w +//: ,.wt${i}_actv_nz (wt${i}_actv_nz) //|> w +//: ,.wt${i}_actv_pvld (wt${i}_actv_pvld) //|> w +//: ,.wt${i}_sd_mask (wt${i}_sd_mask) //|> w +//: ,.wt${i}_sd_pvld (wt${i}_sd_pvld) //|> w +//: ) +//: } +); +//========================================================== +// MAC CELLs +//========================================================== +//: my $total_num = 8/2; +//: for(my $i = 0; $i < $total_num; $i ++) { +//: print qq { +//: wire nvdla_op_gated_clk_${i}; +//: wire nvdla_wg_gated_clk_${i}; +//: wire [19 -1:0] out_data${i}; +//: NV_NVDLA_CMAC_CORE_mac u_mac_${i} ( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w +//: ,.nvdla_wg_clk (nvdla_op_gated_clk_${i}) //|< w , need update for winograd +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.cfg_is_wg (cfg_is_wg) //|< w +//: ,.cfg_reg_en (cfg_reg_en) //|< w +//: ,.dat_actv_data (dat${i}_actv_data) //|< w +//: ,.dat_actv_nz (dat${i}_actv_nz) //|< w +//: ,.dat_actv_pvld (dat${i}_actv_pvld) //|< w +//: ,.wt_actv_data (wt${i}_actv_data) //|< w +//: ,.wt_actv_nz (wt${i}_actv_nz) //|< w +//: ,.wt_actv_pvld (wt${i}_actv_pvld) //|< w +//: ,.mac_out_data (out_data${i}) //|> w +//: ,.mac_out_pvld (out_mask[${i}]) //|> w +//: ); +//: } +//:} +//========================================================== +// output retiming logic +//========================================================== +//: my $i = 8/2 +2; +//: print qq( +//: wire nvdla_op_gated_clk_${i}; ); +NV_NVDLA_CMAC_CORE_rt_out u_rt_out ( +//: my $i=8/2 +2; +//: print qq( +//: .nvdla_core_clk (nvdla_op_gated_clk_${i}) //|< w +//: ,.nvdla_wg_clk (nvdla_op_gated_clk_${i}) //|< w ); + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_is_wg (cfg_is_wg) //|< w + ,.cfg_reg_en (cfg_reg_en) //|< w +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,.out_data${i} (out_data${i}) //|< w ) +//: } + ,.out_mask (out_mask) //|< w + ,.out_pd (out_pd) //|< w + ,.out_pvld (out_pvld) //|< w + ,.dp2reg_done (dp2reg_done) //|> o +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o ) +//: } + ,.mac2accu_mask (mac2accu_mask) //|> o + ,.mac2accu_pd (mac2accu_pd) //|> o + ,.mac2accu_pvld (mac2accu_pvld) //|> o + ); +//========================================================== +// SLCG groups +//========================================================== +//: for(my $i = 0; $i < 3+8/2; $i ++) { +//: print qq { +//: NV_NVDLA_CMAC_CORE_slcg u_slcg_op_${i} ( +//: .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i +//: ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.slcg_en_src_0 (slcg_op_en[${i}]) //|< i +//: ,.slcg_en_src_1 (1'b1) //|< ? +//: ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i +//: ,.nvdla_core_gated_clk (nvdla_op_gated_clk_${i}) //|> w +//: ); +//: } +//: } +`ifndef SYNTHESIS +wire [8:0] dbg_mac2accu_pd; +wire dbg_mac2accu_pvld; +wire [8:0] dbg_out_pd_d0; +wire dbg_out_pvld_d0; +`endif +//////// for valid forwarding /////// +`ifndef SYNTHESIS +//: print qq ( +//: assign dbg_out_pvld_d0 = out_pvld; +//: assign dbg_out_pd_d0 = out_pd; +//: ); +//: +//: my $delay = (2 +2 +3 +2)-2 -(3 +2 -3); +//: my $i; +//: +//: for($i = 0; $i < $delay; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-q dbg_out_pvld_d${j} -d dbg_out_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q dbg_out_pd_d${j} -en dbg_out_pvld_d${i} -d dbg_out_pd_d${i}"); +//: } +//: +//: print qq ( +//: assign dbg_mac2accu_pvld = dbg_out_pvld_d${delay}; +//: assign dbg_mac2accu_pd = dbg_out_pd_d${delay}; +//: ); +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v new file mode 100644 index 0000000..fa5bf1b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v @@ -0,0 +1,612 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_reg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: simulate_x_tick.vh +`ifdef _SIMULATE_X_VH_ +`else +`define _SIMULATE_X_VH_ +`ifndef SYNTHESIS +`define SIMULATION_ONLY +`endif +// deprecated tick defines +`ifdef SIMULATION_ONLY +`define x_or_0 1'bx +`define x_or_1 1'bx +`else +`define x_or_0 1'b0 +`define x_or_1 1'b1 +`endif +// formerly recommended tick defines +`ifdef SIMULATION_ONLY +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +// newly recommended tick defines +// (-sv parsing is enabled everywhere now, and explicit widths are no longer needed) +`ifdef SIMULATION_ONLY +`define sv_x_or_0 'x +`define sv_x_or_1 'x +`else +`define sv_x_or_0 '0 +`define sv_x_or_1 '1 +`endif +`endif +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cmac_a_req_pd //|< i + ,csb2cmac_a_req_pvld //|< i + ,dp2reg_done //|< i + ,cmac_a2csb_resp_pd //|> o + ,cmac_a2csb_resp_valid //|> o + ,csb2cmac_a_req_prdy //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_op_en //|> o + ,reg2dp_proc_precision //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cmac_a_req_pd; +input csb2cmac_a_req_pvld; +input dp2reg_done; +output [33:0] cmac_a2csb_resp_pd; +output cmac_a2csb_resp_valid; +output csb2cmac_a_req_prdy; +output reg2dp_conv_mode; +output reg2dp_op_en; +output [1:0] reg2dp_proc_precision; +output [3+8/2 -1:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire reg2dp_d0_conv_mode; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_proc_precision; +wire reg2dp_d1_conv_mode; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_proc_precision; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3+8/2 -1:0] slcg_op_en_d0; +reg [33:0] cmac_a2csb_resp_pd; +reg cmac_a2csb_resp_valid; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg reg2dp_conv_mode; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_proc_precision; +reg [62:0] req_pd; +reg req_pvld; +reg [3+8/2 -1:0] slcg_op_en_d1; +reg [3+8/2 -1:0] slcg_op_en_d2; +reg [3+8/2 -1:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CMAC_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CMAC_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ); +NV_NVDLA_CMAC_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {3+8/2{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {3+8/2{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {3+8/2{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {3+8/2{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h7008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h7008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h7008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cmac_a_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cmac_a_req_pvld) == 1'b1) begin + req_pd <= csb2cmac_a_req_pd; +// VCS coverage off + end else if ((csb2cmac_a_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cmac_a_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cmac_a_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cmac_a2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cmac_a2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a2csb_resp_valid <= 1'b0; + end else begin + cmac_a2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_CMAC_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v.vcp new file mode 100644 index 0000000..fa5bf1b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v.vcp @@ -0,0 +1,612 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC_reg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: simulate_x_tick.vh +`ifdef _SIMULATE_X_VH_ +`else +`define _SIMULATE_X_VH_ +`ifndef SYNTHESIS +`define SIMULATION_ONLY +`endif +// deprecated tick defines +`ifdef SIMULATION_ONLY +`define x_or_0 1'bx +`define x_or_1 1'bx +`else +`define x_or_0 1'b0 +`define x_or_1 1'b1 +`endif +// formerly recommended tick defines +`ifdef SIMULATION_ONLY +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +// newly recommended tick defines +// (-sv parsing is enabled everywhere now, and explicit widths are no longer needed) +`ifdef SIMULATION_ONLY +`define sv_x_or_0 'x +`define sv_x_or_1 'x +`else +`define sv_x_or_0 '0 +`define sv_x_or_1 '1 +`endif +`endif +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_CMAC_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2cmac_a_req_pd //|< i + ,csb2cmac_a_req_pvld //|< i + ,dp2reg_done //|< i + ,cmac_a2csb_resp_pd //|> o + ,cmac_a2csb_resp_valid //|> o + ,csb2cmac_a_req_prdy //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_op_en //|> o + ,reg2dp_proc_precision //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2cmac_a_req_pd; +input csb2cmac_a_req_pvld; +input dp2reg_done; +output [33:0] cmac_a2csb_resp_pd; +output cmac_a2csb_resp_valid; +output csb2cmac_a_req_prdy; +output reg2dp_conv_mode; +output reg2dp_op_en; +output [1:0] reg2dp_proc_precision; +output [3+8/2 -1:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire reg2dp_d0_conv_mode; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_proc_precision; +wire reg2dp_d1_conv_mode; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_proc_precision; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3+8/2 -1:0] slcg_op_en_d0; +reg [33:0] cmac_a2csb_resp_pd; +reg cmac_a2csb_resp_valid; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg reg2dp_conv_mode; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_proc_precision; +reg [62:0] req_pd; +reg req_pvld; +reg [3+8/2 -1:0] slcg_op_en_d1; +reg [3+8/2 -1:0] slcg_op_en_d2; +reg [3+8/2 -1:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CMAC_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CMAC_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ); +NV_NVDLA_CMAC_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {3+8/2{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {3+8/2{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {3+8/2{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {3+8/2{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h7008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h7008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h7008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2cmac_a_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2cmac_a_req_pvld) == 1'b1) begin + req_pd <= csb2cmac_a_req_pd; +// VCS coverage off + end else if ((csb2cmac_a_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2cmac_a_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2cmac_a_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + cmac_a2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + cmac_a2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a2csb_resp_valid <= 1'b0; + end else begin + cmac_a2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_CMAC_reg diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_cmac.v b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_cmac.v new file mode 100644 index 0000000..b6f450c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_cmac.v @@ -0,0 +1,233 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cmac.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_cmac ( + csb2cmac_a_req_pd //|< i + ,csb2cmac_a_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_data0 //|< i +,sc2mac_dat_data1 //|< i +,sc2mac_dat_data2 //|< i +,sc2mac_dat_data3 //|< i +,sc2mac_dat_data4 //|< i +,sc2mac_dat_data5 //|< i +,sc2mac_dat_data6 //|< i +,sc2mac_dat_data7 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_mask //|< i + ,sc2mac_dat_pd //|< i + ,sc2mac_dat_pvld //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_data0 //|< i +,sc2mac_wt_data1 //|< i +,sc2mac_wt_data2 //|< i +,sc2mac_wt_data3 //|< i +,sc2mac_wt_data4 //|< i +,sc2mac_wt_data5 //|< i +,sc2mac_wt_data6 //|< i +,sc2mac_wt_data7 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_mask //|< i + ,sc2mac_wt_pvld //|< i + ,sc2mac_wt_sel //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cmac_a2csb_resp_pd //|> o + ,cmac_a2csb_resp_valid //|> o + ,csb2cmac_a_req_prdy //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac2accu_data${i} //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_data0 //|> o +,mac2accu_data1 //|> o +,mac2accu_data2 //|> o +,mac2accu_data3 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_mask //|> o + ,mac2accu_mode //|> o + ,mac2accu_pd //|> o + ,mac2accu_pvld //|> o + ); +// +// NV_NVDLA_cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output cmac_a2csb_resp_valid; /* data valid */ +output [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input csb2cmac_a_req_pvld; /* data valid */ +output csb2cmac_a_req_prdy; /* data return handshake */ +input [62:0] csb2cmac_a_req_pd; +output mac2accu_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_mask; +output mac2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_data${i}; //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [19 -1:0] mac2accu_data0; //|> o +output [19 -1:0] mac2accu_data1; //|> o +output [19 -1:0] mac2accu_data2; //|> o +output [19 -1:0] mac2accu_data3; //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] mac2accu_pd; +input sc2mac_dat_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i}; //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_dat_data0; //|< i +input [8 -1:0] sc2mac_dat_data1; //|< i +input [8 -1:0] sc2mac_dat_data2; //|< i +input [8 -1:0] sc2mac_dat_data3; //|< i +input [8 -1:0] sc2mac_dat_data4; //|< i +input [8 -1:0] sc2mac_dat_data5; //|< i +input [8 -1:0] sc2mac_dat_data6; //|< i +input [8 -1:0] sc2mac_dat_data7; //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] sc2mac_dat_pd; +input sc2mac_wt_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i}; //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_wt_data0; //|< i +input [8 -1:0] sc2mac_wt_data1; //|< i +input [8 -1:0] sc2mac_wt_data2; //|< i +input [8 -1:0] sc2mac_wt_data3; //|< i +input [8 -1:0] sc2mac_wt_data4; //|< i +input [8 -1:0] sc2mac_wt_data5; //|< i +input [8 -1:0] sc2mac_wt_data6; //|< i +input [8 -1:0] sc2mac_wt_data7; //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2 -1:0] sc2mac_wt_sel; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire dp2reg_done; +wire [0:0] reg2dp_conv_mode; +wire [0:0] reg2dp_op_en; +wire [1:0] reg2dp_proc_precision=2'b0; +wire [3+8/2 -1:0] slcg_op_en; +//========================================================== +// core +//========================================================== +NV_NVDLA_CMAC_core u_core ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i + ,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_data0 (sc2mac_dat_data0) //|< i +,.sc2mac_dat_data1 (sc2mac_dat_data1) //|< i +,.sc2mac_dat_data2 (sc2mac_dat_data2) //|< i +,.sc2mac_dat_data3 (sc2mac_dat_data3) //|< i +,.sc2mac_dat_data4 (sc2mac_dat_data4) //|< i +,.sc2mac_dat_data5 (sc2mac_dat_data5) //|< i +,.sc2mac_dat_data6 (sc2mac_dat_data6) //|< i +,.sc2mac_dat_data7 (sc2mac_dat_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i + ,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i + ,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_data0 (sc2mac_wt_data0) //|< i +,.sc2mac_wt_data1 (sc2mac_wt_data1) //|< i +,.sc2mac_wt_data2 (sc2mac_wt_data2) //|< i +,.sc2mac_wt_data3 (sc2mac_wt_data3) //|< i +,.sc2mac_wt_data4 (sc2mac_wt_data4) //|< i +,.sc2mac_wt_data5 (sc2mac_wt_data5) //|< i +,.sc2mac_wt_data6 (sc2mac_wt_data6) //|< i +,.sc2mac_wt_data7 (sc2mac_wt_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i + ,.mac2accu_pvld (mac2accu_pvld) //|> o + ,.mac2accu_mask (mac2accu_mask) //|> o + ,.mac2accu_mode (mac2accu_mode) //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac2accu_data0 (mac2accu_data0) //|> o +,.mac2accu_data1 (mac2accu_data1) //|> o +,.mac2accu_data2 (mac2accu_data2) //|> o +,.mac2accu_data3 (mac2accu_data3) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac2accu_pd (mac2accu_pd) //|> o + ,.reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w + ,.dp2reg_done (dp2reg_done) //|> w + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.slcg_op_en (slcg_op_en) //|< w + ); +//========================================================== +// reg +//========================================================== +wire [1:0] reg2dp_proc_precision_NC; +NV_NVDLA_CMAC_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< i + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> o + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> o + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> o + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision_NC) //|> w //dangle + ,.slcg_op_en (slcg_op_en) //|> w + ); +endmodule // NV_NVDLA_cmac diff --git a/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_cmac.v.vcp b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_cmac.v.vcp new file mode 100644 index 0000000..6820c64 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/cmac/NV_NVDLA_cmac.v.vcp @@ -0,0 +1,146 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_cmac.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_cmac ( + csb2cmac_a_req_pd //|< i + ,csb2cmac_a_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i} //|< i ) +//: } + ,sc2mac_dat_mask //|< i + ,sc2mac_dat_pd //|< i + ,sc2mac_dat_pvld //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i} //|< i ) +//: } + ,sc2mac_wt_mask //|< i + ,sc2mac_wt_pvld //|< i + ,sc2mac_wt_sel //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cmac_a2csb_resp_pd //|> o + ,cmac_a2csb_resp_valid //|> o + ,csb2cmac_a_req_prdy //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac2accu_data${i} //|> o ) +//: } + ,mac2accu_mask //|> o + ,mac2accu_mode //|> o + ,mac2accu_pd //|> o + ,mac2accu_pvld //|> o + ); +// +// NV_NVDLA_cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output cmac_a2csb_resp_valid; /* data valid */ +output [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input csb2cmac_a_req_pvld; /* data valid */ +output csb2cmac_a_req_prdy; /* data return handshake */ +input [62:0] csb2cmac_a_req_pd; +output mac2accu_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_mask; +output mac2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_data${i}; //|> o ) +//: } +output [8:0] mac2accu_pd; +input sc2mac_dat_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i}; //|< i ) +//: } +input [8:0] sc2mac_dat_pd; +input sc2mac_wt_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i}; //|< i ) +//: } +input [8/2 -1:0] sc2mac_wt_sel; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire dp2reg_done; +wire [0:0] reg2dp_conv_mode; +wire [0:0] reg2dp_op_en; +wire [1:0] reg2dp_proc_precision=2'b0; +wire [3+8/2 -1:0] slcg_op_en; +//========================================================== +// core +//========================================================== +NV_NVDLA_CMAC_core u_core ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i + ,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i ) +//: } + ,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i + ,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i + ,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i ) +//: } + ,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i + ,.mac2accu_pvld (mac2accu_pvld) //|> o + ,.mac2accu_mask (mac2accu_mask) //|> o + ,.mac2accu_mode (mac2accu_mode) //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o ) +//: } + ,.mac2accu_pd (mac2accu_pd) //|> o + ,.reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|< w + ,.dp2reg_done (dp2reg_done) //|> w + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.slcg_op_en (slcg_op_en) //|< w + ); +//========================================================== +// reg +//========================================================== +wire [1:0] reg2dp_proc_precision_NC; +NV_NVDLA_CMAC_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< i + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> o + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> o + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> o + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision_NC) //|> w //dangle + ,.slcg_op_en (slcg_op_en) //|> w + ); +endmodule // NV_NVDLA_cmac diff --git a/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v new file mode 100644 index 0000000..eff2111 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v @@ -0,0 +1,763 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo ( + wr_clk + , wr_reset_ + , wr_ready + , wr_req + , wr_data + , rd_clk + , rd_reset_ + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input wr_clk; +input wr_reset_; +output wr_ready; +input wr_req; +input [33:0] wr_data; +input rd_clk; +input rd_reset_; +input rd_ready; +output rd_req; +output [33:0] rd_data; +input [31:0] pwrbus_ram_pd; +// +// DFT clock gate enable qualifier +// +// Write side +wire dft_qualifier_wr_enable; +oneHotClk_async_write_clock fifogenDFTWrQual ( .enable_w( dft_qualifier_wr_enable ) ); +wire wr_clk_dft_mgated; +NV_CLK_gate_power wr_clk_wr_dft_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable), .clk_gated(wr_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_wr_clkgate_sink (.A( wr_clk_dft_mgated ) ); +`endif +// Read side +wire dft_qualifier_rd_enable; +oneHotClk_async_read_clock fifogenDFTRdQual ( .enable_r( dft_qualifier_rd_enable ) ); +wire rd_clk_dft_mgated; +NV_CLK_gate_power rd_clk_rd_dft_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable), .clk_gated(rd_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_rd_clkgate_sink (.A( rd_clk_dft_mgated ) ); +`endif +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire wr_clk_wr_mgated_enable; // assigned by code at end of this module +wire wr_clk_wr_mgated; +NV_CLK_gate_power wr_clk_wr_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(wr_clk_wr_mgated_enable), .clk_gated(wr_clk_wr_mgated) ); +wire rd_clk_rd_mgated_enable; // assigned by code at end of this module +wire rd_clk_rd_mgated; +NV_CLK_gate_power rd_clk_rd_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(rd_clk_rd_mgated_enable), .clk_gated(rd_clk_rd_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [1:0] wr_count; // write-side count +wire [1:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [1:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [1:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_2 = ( wr_count_next_no_wr_popping == 2'd2 ); +wire wr_count_next_is_2 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_2; +wire [1:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [1:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_2 || // busy next cycle? + (wr_limit_reg != 2'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 2'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_adr <= 1'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +reg rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [33:0] rd_data_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 ram ( + .clk( wr_clk_dft_mgated ) + , .clk_mgated( wr_clk_wr_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( rd_adr ) + , .dout ( rd_data_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [0:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_adr <= 1'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// ASYNCHRONOUS BOUNDARY USING TRADITIONAL SYNCHRONIZERS +// +// Our goal here is to translate wr_pushing pulses into rd_pushing +// pulses on the read side and, conversely, to translate rd_popping +// pulses to wr_popping pulses on the write side. +// +// We don't try to optimize the case where the async fifo depth is +// a power of two. We handle the general case using one scheme to +// avoid maintaining different implementations. We may use a couple +// more counters, but they are quite cheap in the grand scheme of things. +// This wr_pushing/rd_pushing/rd_popping/wr_popping centric scheme also +// fits in well with the case where there is no asynchronous boundary. +// +// The scheme works as follows. For the wr_pushing -> rd_pushing translation, +// we keep an 2-bit gray counter on the write and read sides. +// This counter is initialized to 0 on both sides. When wr_pushing +// is pulsed, the write side gray-increments its counter, registers it, +// then sends it through an 2-bit synchronizer to the other side. +// Whenever the read side sees the new gray counter not equal to its +// copy of the gray counter, it gray-increments its counter and pulses +// rd_pushing=1. The actual value of the gray counter is irrelevant. +// It must be a power-of-2 to make the gray code work. Otherwise, +// we're just looking for changes in the gray value. +// +// The same technique is used for the rd_popping -> wr_popping translation. +// +// The gray counter algorithm uses a 1-bit polarity register that starts +// off as 0 and is inverted whenever the gray counter is incremented. +// +// In plain English, the next gray counter is determined as follows: +// if the current polarity register is 0, invert bit 0 (the lsb); otherwise, +// find the rightmost one bit and invert the bit to the left of the one bit +// if the one bit is not the msb else invert the msb one bit. The +// general expression is thus: +// +// { gray[n-1] ^ (polarity & ~gray[n-3] & ~gray[n-4] & ... ), +// gray[n-2] ^ (polarity & gray[n-3] & ~gray[n-4] & ~gray[n-5] & ... ), +// gray[n-3] ^ (polarity & gray[n-4] & ~gray[n-5] & ~gray[n-6] & ... ), +// ... +// gray[0] ^ (~polarity) } +// +// For n == 1, the next gray value is obviously just ~gray. +// +// The wr_pushing/rd_popping signal does not affect the registered +// gray counter until the next cycle. However, for non-FF-type rams, +// the write will not complete until the end of the next cycle, so +// we must delay wr_pushing yet another more cycle, +// unless the -rd_clk_le_2x_wr_clk option was given +// (or the -rd_clk_le_2x_wr_clk_dynamic option was given +// and the rd_clk_le_2x_wr_clk signal is 1). +// +// clk gating of strict synchronizers +// +wire wr_clk_wr_mgated_strict_snd_gated; +NV_CLK_gate_power wr_clk_wr_mgated_snd_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_pushing)), .clk_gated(wr_clk_wr_mgated_strict_snd_gated) ); +// +// wr_pushing -> rd_pushing translation +// +wire [1:0] wr_pushing_gray_cntr; +wire [1:0] wr_pushing_gray_cntr_next; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict wr_pushing_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( wr_pushing ) , +`endif + .gray ( wr_pushing_gray_cntr ) + , .gray_next ( wr_pushing_gray_cntr_next ) + ); +wire [1:0] wr_pushing_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync0 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[0] ) + , .SRC_D ( wr_pushing_gray_cntr[0] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync1 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[1] ) + , .SRC_D ( wr_pushing_gray_cntr[1] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [1:0] rd_pushing_gray_cntr; +wire rd_pushing = wr_pushing_gray_cntr_sync != rd_pushing_gray_cntr; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr rd_pushing_gray ( + .clk ( rd_clk_rd_mgated ) + , .reset_ ( rd_reset_ ) + , .inc ( rd_pushing ) + , .gray ( rd_pushing_gray_cntr ) + ); +// clk gating of strict synchronizers +// +wire rd_clk_rd_mgated_strict_snd_gated; +NV_CLK_gate_power rd_clk_rd_mgated_snd_gate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable && (rd_popping)), .clk_gated(rd_clk_rd_mgated_strict_snd_gated) ); +wire wr_clk_strict_rcv_gated; +NV_CLK_gate_power wr_clk_rcv_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_count_next_no_wr_popping != 2'd0)), .clk_gated(wr_clk_strict_rcv_gated) ); +// +// rd_popping -> wr_popping translation +// +wire [1:0] rd_popping_gray_cntr; +wire [1:0] rd_popping_gray_cntr_next; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict rd_popping_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( rd_popping ) , +`endif + .gray ( rd_popping_gray_cntr ) + , .gray_next ( rd_popping_gray_cntr_next ) + ); +wire [1:0] rd_popping_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync0 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[0] ) + , .SRC_D ( rd_popping_gray_cntr[0] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync1 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[1] ) + , .SRC_D ( rd_popping_gray_cntr[1] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [1:0] wr_popping_gray_cntr; +assign wr_popping = rd_popping_gray_cntr_sync != wr_popping_gray_cntr; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr wr_popping_gray ( + .clk ( wr_clk_wr_mgated ) + , .reset_ ( wr_reset_ ) + , .inc ( wr_popping ) + , .gray ( wr_popping_gray_cntr ) + ); +// +// READ SIDE +// +wire rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [1:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [1:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [1:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [1:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign rd_req_p = rd_count_p != 0 || rd_pushing; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_count_p <= 2'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [33:0] NV_AFIFO_rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge rd_clk_rd_mgated ) begin + if ( (rd_popping) ) begin + NV_AFIFO_rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + NV_AFIFO_rd_data <= {34{`x_or_0}}; + end +//synopsys translate_on +end +assign rd_data = NV_AFIFO_rd_data; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign wr_clk_wr_mgated_enable = dft_qualifier_wr_enable && (wr_reserving || wr_pushing || wr_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +assign rd_clk_rd_mgated_enable = dft_qualifier_rd_enable && ((rd_pushing || rd_popping || (rd_req_int && rd_ready))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit : 2'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 2'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 2'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 2'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [1:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 2'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( wr_clk ) + , .max ( {30'd0, (wr_limit_reg == 2'd0) ? 2'd2 : wr_limit_reg} ) + , .curr ( {30'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSB_MASTER_csb2falcon_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [33:0] di; +input iwe; +input we; +input [0:0] wa; +input [0:0] ra; +output [33:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [33:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [0:0] Wa0_vmw; +reg we0_vmw; +reg [33:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [33:0] ram_ff0; +reg [33:0] ram_ff1; +always @( posedge clk_mgated ) begin + if ( we && wa == 1'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 1'd1 ) begin + ram_ff1 <= di_d; + end +end +reg [33:0] dout; +always @(*) begin + case( ra ) // synopsys infer_mux_override + 1'd0: dout = ram_ff0; + 1'd1: dout = ram_ff1; +//VCS coverage off + default: dout = {34{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [0:0] Wa0; +input we0; +input [33:0] Di0; +input [0:0] Ra0; +output [33:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 34'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [33:0] mem[1:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [33:0] Q0 = mem[0]; +wire [33:0] Q1 = mem[1]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34] } +endmodule // vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +//vmw: Memory vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +//vmw: Address-size 1 +//vmw: Data-size 34 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[33:0] data0[33:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[33:0] data1[33:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// See the ASYNCHONROUS BOUNDARY section above for details on the +// gray counter implementation. +// +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict ( +`ifdef NV_FPGA_FIFOGEN + inc , +`endif + gray + , gray_next + ); +`ifdef NV_FPGA_FIFOGEN +input inc; +`endif +input [1:0] gray; +output [1:0] gray_next; +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1]; +assign gray_next = +`ifdef NV_FPGA_FIFOGEN + (~inc) ? gray : +`endif + { gray[1]^(polarity ), + gray[0]^(~polarity) }; +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr ( + clk + , reset_ + , inc + , gray + ); +input clk; +input reset_; +input inc; +output [1:0] gray; +reg [1:0] gray; // gray counter +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1]; + always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + gray <= 2'd0; + end else if ( inc ) begin + gray <= { gray[1]^(polarity ), + gray[0]^(~polarity) }; + end +end +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr diff --git a/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v.vcp new file mode 100644 index 0000000..eff2111 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v.vcp @@ -0,0 +1,763 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo ( + wr_clk + , wr_reset_ + , wr_ready + , wr_req + , wr_data + , rd_clk + , rd_reset_ + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input wr_clk; +input wr_reset_; +output wr_ready; +input wr_req; +input [33:0] wr_data; +input rd_clk; +input rd_reset_; +input rd_ready; +output rd_req; +output [33:0] rd_data; +input [31:0] pwrbus_ram_pd; +// +// DFT clock gate enable qualifier +// +// Write side +wire dft_qualifier_wr_enable; +oneHotClk_async_write_clock fifogenDFTWrQual ( .enable_w( dft_qualifier_wr_enable ) ); +wire wr_clk_dft_mgated; +NV_CLK_gate_power wr_clk_wr_dft_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable), .clk_gated(wr_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_wr_clkgate_sink (.A( wr_clk_dft_mgated ) ); +`endif +// Read side +wire dft_qualifier_rd_enable; +oneHotClk_async_read_clock fifogenDFTRdQual ( .enable_r( dft_qualifier_rd_enable ) ); +wire rd_clk_dft_mgated; +NV_CLK_gate_power rd_clk_rd_dft_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable), .clk_gated(rd_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_rd_clkgate_sink (.A( rd_clk_dft_mgated ) ); +`endif +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire wr_clk_wr_mgated_enable; // assigned by code at end of this module +wire wr_clk_wr_mgated; +NV_CLK_gate_power wr_clk_wr_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(wr_clk_wr_mgated_enable), .clk_gated(wr_clk_wr_mgated) ); +wire rd_clk_rd_mgated_enable; // assigned by code at end of this module +wire rd_clk_rd_mgated; +NV_CLK_gate_power rd_clk_rd_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(rd_clk_rd_mgated_enable), .clk_gated(rd_clk_rd_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [1:0] wr_count; // write-side count +wire [1:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [1:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [1:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_2 = ( wr_count_next_no_wr_popping == 2'd2 ); +wire wr_count_next_is_2 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_2; +wire [1:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [1:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_2 || // busy next cycle? + (wr_limit_reg != 2'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 2'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_adr <= 1'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +reg rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [33:0] rd_data_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 ram ( + .clk( wr_clk_dft_mgated ) + , .clk_mgated( wr_clk_wr_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( rd_adr ) + , .dout ( rd_data_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [0:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_adr <= 1'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// ASYNCHRONOUS BOUNDARY USING TRADITIONAL SYNCHRONIZERS +// +// Our goal here is to translate wr_pushing pulses into rd_pushing +// pulses on the read side and, conversely, to translate rd_popping +// pulses to wr_popping pulses on the write side. +// +// We don't try to optimize the case where the async fifo depth is +// a power of two. We handle the general case using one scheme to +// avoid maintaining different implementations. We may use a couple +// more counters, but they are quite cheap in the grand scheme of things. +// This wr_pushing/rd_pushing/rd_popping/wr_popping centric scheme also +// fits in well with the case where there is no asynchronous boundary. +// +// The scheme works as follows. For the wr_pushing -> rd_pushing translation, +// we keep an 2-bit gray counter on the write and read sides. +// This counter is initialized to 0 on both sides. When wr_pushing +// is pulsed, the write side gray-increments its counter, registers it, +// then sends it through an 2-bit synchronizer to the other side. +// Whenever the read side sees the new gray counter not equal to its +// copy of the gray counter, it gray-increments its counter and pulses +// rd_pushing=1. The actual value of the gray counter is irrelevant. +// It must be a power-of-2 to make the gray code work. Otherwise, +// we're just looking for changes in the gray value. +// +// The same technique is used for the rd_popping -> wr_popping translation. +// +// The gray counter algorithm uses a 1-bit polarity register that starts +// off as 0 and is inverted whenever the gray counter is incremented. +// +// In plain English, the next gray counter is determined as follows: +// if the current polarity register is 0, invert bit 0 (the lsb); otherwise, +// find the rightmost one bit and invert the bit to the left of the one bit +// if the one bit is not the msb else invert the msb one bit. The +// general expression is thus: +// +// { gray[n-1] ^ (polarity & ~gray[n-3] & ~gray[n-4] & ... ), +// gray[n-2] ^ (polarity & gray[n-3] & ~gray[n-4] & ~gray[n-5] & ... ), +// gray[n-3] ^ (polarity & gray[n-4] & ~gray[n-5] & ~gray[n-6] & ... ), +// ... +// gray[0] ^ (~polarity) } +// +// For n == 1, the next gray value is obviously just ~gray. +// +// The wr_pushing/rd_popping signal does not affect the registered +// gray counter until the next cycle. However, for non-FF-type rams, +// the write will not complete until the end of the next cycle, so +// we must delay wr_pushing yet another more cycle, +// unless the -rd_clk_le_2x_wr_clk option was given +// (or the -rd_clk_le_2x_wr_clk_dynamic option was given +// and the rd_clk_le_2x_wr_clk signal is 1). +// +// clk gating of strict synchronizers +// +wire wr_clk_wr_mgated_strict_snd_gated; +NV_CLK_gate_power wr_clk_wr_mgated_snd_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_pushing)), .clk_gated(wr_clk_wr_mgated_strict_snd_gated) ); +// +// wr_pushing -> rd_pushing translation +// +wire [1:0] wr_pushing_gray_cntr; +wire [1:0] wr_pushing_gray_cntr_next; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict wr_pushing_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( wr_pushing ) , +`endif + .gray ( wr_pushing_gray_cntr ) + , .gray_next ( wr_pushing_gray_cntr_next ) + ); +wire [1:0] wr_pushing_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync0 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[0] ) + , .SRC_D ( wr_pushing_gray_cntr[0] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync1 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[1] ) + , .SRC_D ( wr_pushing_gray_cntr[1] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [1:0] rd_pushing_gray_cntr; +wire rd_pushing = wr_pushing_gray_cntr_sync != rd_pushing_gray_cntr; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr rd_pushing_gray ( + .clk ( rd_clk_rd_mgated ) + , .reset_ ( rd_reset_ ) + , .inc ( rd_pushing ) + , .gray ( rd_pushing_gray_cntr ) + ); +// clk gating of strict synchronizers +// +wire rd_clk_rd_mgated_strict_snd_gated; +NV_CLK_gate_power rd_clk_rd_mgated_snd_gate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable && (rd_popping)), .clk_gated(rd_clk_rd_mgated_strict_snd_gated) ); +wire wr_clk_strict_rcv_gated; +NV_CLK_gate_power wr_clk_rcv_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_count_next_no_wr_popping != 2'd0)), .clk_gated(wr_clk_strict_rcv_gated) ); +// +// rd_popping -> wr_popping translation +// +wire [1:0] rd_popping_gray_cntr; +wire [1:0] rd_popping_gray_cntr_next; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict rd_popping_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( rd_popping ) , +`endif + .gray ( rd_popping_gray_cntr ) + , .gray_next ( rd_popping_gray_cntr_next ) + ); +wire [1:0] rd_popping_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync0 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[0] ) + , .SRC_D ( rd_popping_gray_cntr[0] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync1 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[1] ) + , .SRC_D ( rd_popping_gray_cntr[1] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [1:0] wr_popping_gray_cntr; +assign wr_popping = rd_popping_gray_cntr_sync != wr_popping_gray_cntr; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr wr_popping_gray ( + .clk ( wr_clk_wr_mgated ) + , .reset_ ( wr_reset_ ) + , .inc ( wr_popping ) + , .gray ( wr_popping_gray_cntr ) + ); +// +// READ SIDE +// +wire rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [1:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [1:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [1:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [1:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign rd_req_p = rd_count_p != 0 || rd_pushing; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_count_p <= 2'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [33:0] NV_AFIFO_rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge rd_clk_rd_mgated ) begin + if ( (rd_popping) ) begin + NV_AFIFO_rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + NV_AFIFO_rd_data <= {34{`x_or_0}}; + end +//synopsys translate_on +end +assign rd_data = NV_AFIFO_rd_data; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign wr_clk_wr_mgated_enable = dft_qualifier_wr_enable && (wr_reserving || wr_pushing || wr_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +assign rd_clk_rd_mgated_enable = dft_qualifier_rd_enable && ((rd_pushing || rd_popping || (rd_req_int && rd_ready))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit : 2'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 2'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 2'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 2'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [1:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 2'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSB_MASTER_csb2falcon_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( wr_clk ) + , .max ( {30'd0, (wr_limit_reg == 2'd0) ? 2'd2 : wr_limit_reg} ) + , .curr ( {30'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSB_MASTER_csb2falcon_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [33:0] di; +input iwe; +input we; +input [0:0] wa; +input [0:0] ra; +output [33:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [33:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [0:0] Wa0_vmw; +reg we0_vmw; +reg [33:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [33:0] ram_ff0; +reg [33:0] ram_ff1; +always @( posedge clk_mgated ) begin + if ( we && wa == 1'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 1'd1 ) begin + ram_ff1 <= di_d; + end +end +reg [33:0] dout; +always @(*) begin + case( ra ) // synopsys infer_mux_override + 1'd0: dout = ram_ff0; + 1'd1: dout = ram_ff1; +//VCS coverage off + default: dout = {34{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [0:0] Wa0; +input we0; +input [33:0] Di0; +input [0:0] Ra0; +output [33:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 34'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [33:0] mem[1:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [33:0] Q0 = mem[0]; +wire [33:0] Q1 = mem[1]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34] } +endmodule // vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +//vmw: Memory vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +//vmw: Address-size 1 +//vmw: Data-size 34 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[33:0] data0[33:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[33:0] data1[33:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSB_MASTER_csb2falcon_fifo_flopram_rwa_2x34 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// See the ASYNCHONROUS BOUNDARY section above for details on the +// gray counter implementation. +// +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict ( +`ifdef NV_FPGA_FIFOGEN + inc , +`endif + gray + , gray_next + ); +`ifdef NV_FPGA_FIFOGEN +input inc; +`endif +input [1:0] gray; +output [1:0] gray_next; +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1]; +assign gray_next = +`ifdef NV_FPGA_FIFOGEN + (~inc) ? gray : +`endif + { gray[1]^(polarity ), + gray[0]^(~polarity) }; +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr_strict +module NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr ( + clk + , reset_ + , inc + , gray + ); +input clk; +input reset_; +input inc; +output [1:0] gray; +reg [1:0] gray; // gray counter +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1]; + always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + gray <= 2'd0; + end else if ( inc ) begin + gray <= { gray[1]^(polarity ), + gray[0]^(~polarity) }; + end +end +endmodule // NV_NVDLA_CSB_MASTER_csb2falcon_fifo_gray_cntr diff --git a/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v new file mode 100644 index 0000000..17c639e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v @@ -0,0 +1,1035 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo ( + wr_clk + , wr_reset_ + , wr_ready + , wr_req +`ifdef FV_RAND_WR_PAUSE + , wr_pause +`endif + , wr_data + , rd_clk + , rd_reset_ + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input wr_clk; +input wr_reset_; +output wr_ready; +input wr_req; +`ifdef FV_RAND_WR_PAUSE +input wr_pause; +`endif +input [49:0] wr_data; +input rd_clk; +input rd_reset_; +input rd_ready; +output rd_req; +output [49:0] rd_data; +input [31:0] pwrbus_ram_pd; +// +// DFT clock gate enable qualifier +// +// Write side +wire dft_qualifier_wr_enable; +oneHotClk_async_write_clock fifogenDFTWrQual ( .enable_w( dft_qualifier_wr_enable ) ); +wire wr_clk_dft_mgated; +NV_CLK_gate_power wr_clk_wr_dft_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable), .clk_gated(wr_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_wr_clkgate_sink (.A( wr_clk_dft_mgated ) ); +`endif +// Read side +wire dft_qualifier_rd_enable; +oneHotClk_async_read_clock fifogenDFTRdQual ( .enable_r( dft_qualifier_rd_enable ) ); +wire rd_clk_dft_mgated; +NV_CLK_gate_power rd_clk_rd_dft_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable), .clk_gated(rd_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_rd_clkgate_sink (.A( rd_clk_dft_mgated ) ); +`endif +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire wr_clk_wr_mgated_enable; // assigned by code at end of this module +wire wr_clk_wr_mgated; +NV_CLK_gate_power wr_clk_wr_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(wr_clk_wr_mgated_enable), .clk_gated(wr_clk_wr_mgated) ); +wire rd_clk_rd_mgated_enable; // assigned by code at end of this module +wire rd_clk_rd_mgated; +NV_CLK_gate_power rd_clk_rd_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(rd_clk_rd_mgated_enable), .clk_gated(rd_clk_rd_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || wr_pause ; +`else +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 3'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [1:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [1:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +reg [1:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [49:0] rd_data_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 ram ( + .clk( wr_clk_dft_mgated ) + , .clk_mgated( wr_clk_wr_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( rd_adr ) + , .dout ( rd_data_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// ASYNCHRONOUS BOUNDARY USING TRADITIONAL SYNCHRONIZERS +// +// Our goal here is to translate wr_pushing pulses into rd_pushing +// pulses on the read side and, conversely, to translate rd_popping +// pulses to wr_popping pulses on the write side. +// +// We don't try to optimize the case where the async fifo depth is +// a power of two. We handle the general case using one scheme to +// avoid maintaining different implementations. We may use a couple +// more counters, but they are quite cheap in the grand scheme of things. +// This wr_pushing/rd_pushing/rd_popping/wr_popping centric scheme also +// fits in well with the case where there is no asynchronous boundary. +// +// The scheme works as follows. For the wr_pushing -> rd_pushing translation, +// we keep an 3-bit gray counter on the write and read sides. +// This counter is initialized to 0 on both sides. When wr_pushing +// is pulsed, the write side gray-increments its counter, registers it, +// then sends it through an 3-bit synchronizer to the other side. +// Whenever the read side sees the new gray counter not equal to its +// copy of the gray counter, it gray-increments its counter and pulses +// rd_pushing=1. The actual value of the gray counter is irrelevant. +// It must be a power-of-2 to make the gray code work. Otherwise, +// we're just looking for changes in the gray value. +// +// The same technique is used for the rd_popping -> wr_popping translation. +// +// The gray counter algorithm uses a 1-bit polarity register that starts +// off as 0 and is inverted whenever the gray counter is incremented. +// +// In plain English, the next gray counter is determined as follows: +// if the current polarity register is 0, invert bit 0 (the lsb); otherwise, +// find the rightmost one bit and invert the bit to the left of the one bit +// if the one bit is not the msb else invert the msb one bit. The +// general expression is thus: +// +// { gray[n-1] ^ (polarity & ~gray[n-3] & ~gray[n-4] & ... ), +// gray[n-2] ^ (polarity & gray[n-3] & ~gray[n-4] & ~gray[n-5] & ... ), +// gray[n-3] ^ (polarity & gray[n-4] & ~gray[n-5] & ~gray[n-6] & ... ), +// ... +// gray[0] ^ (~polarity) } +// +// For n == 1, the next gray value is obviously just ~gray. +// +// The wr_pushing/rd_popping signal does not affect the registered +// gray counter until the next cycle. However, for non-FF-type rams, +// the write will not complete until the end of the next cycle, so +// we must delay wr_pushing yet another more cycle, +// unless the -rd_clk_le_2x_wr_clk option was given +// (or the -rd_clk_le_2x_wr_clk_dynamic option was given +// and the rd_clk_le_2x_wr_clk signal is 1). +// +// clk gating of strict synchronizers +// +wire wr_clk_wr_mgated_strict_snd_gated; +NV_CLK_gate_power wr_clk_wr_mgated_snd_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_pushing)), .clk_gated(wr_clk_wr_mgated_strict_snd_gated) ); +// +// wr_pushing -> rd_pushing translation +// +wire [2:0] wr_pushing_gray_cntr; +wire [2:0] wr_pushing_gray_cntr_next; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict wr_pushing_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( wr_pushing ) , +`endif + .gray ( wr_pushing_gray_cntr ) + , .gray_next ( wr_pushing_gray_cntr_next ) + ); +wire [2:0] wr_pushing_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync0 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[0] ) + , .SRC_D ( wr_pushing_gray_cntr[0] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync1 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[1] ) + , .SRC_D ( wr_pushing_gray_cntr[1] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync2 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[2] ) + , .SRC_D ( wr_pushing_gray_cntr[2] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[2] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [2:0] rd_pushing_gray_cntr; +wire rd_pushing = wr_pushing_gray_cntr_sync != rd_pushing_gray_cntr; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr rd_pushing_gray ( + .clk ( rd_clk_rd_mgated ) + , .reset_ ( rd_reset_ ) + , .inc ( rd_pushing ) + , .gray ( rd_pushing_gray_cntr ) + ); +// clk gating of strict synchronizers +// +wire rd_clk_rd_mgated_strict_snd_gated; +NV_CLK_gate_power rd_clk_rd_mgated_snd_gate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable && (rd_popping)), .clk_gated(rd_clk_rd_mgated_strict_snd_gated) ); +wire wr_clk_strict_rcv_gated; +NV_CLK_gate_power wr_clk_rcv_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_count_next_no_wr_popping != 3'd0)), .clk_gated(wr_clk_strict_rcv_gated) ); +// +// rd_popping -> wr_popping translation +// +wire [2:0] rd_popping_gray_cntr; +wire [2:0] rd_popping_gray_cntr_next; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict rd_popping_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( rd_popping ) , +`endif + .gray ( rd_popping_gray_cntr ) + , .gray_next ( rd_popping_gray_cntr_next ) + ); +wire [2:0] rd_popping_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync0 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[0] ) + , .SRC_D ( rd_popping_gray_cntr[0] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync1 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[1] ) + , .SRC_D ( rd_popping_gray_cntr[1] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync2 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[2] ) + , .SRC_D ( rd_popping_gray_cntr[2] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[2] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [2:0] wr_popping_gray_cntr; +assign wr_popping = rd_popping_gray_cntr_sync != wr_popping_gray_cntr; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr wr_popping_gray ( + .clk ( wr_clk_wr_mgated ) + , .reset_ ( wr_reset_ ) + , .inc ( wr_popping ) + , .gray ( wr_popping_gray_cntr ) + ); +// +// READ SIDE +// +wire rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [2:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign rd_req_p = rd_count_p != 0 || rd_pushing; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [49:0] NV_AFIFO_rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge rd_clk_rd_mgated ) begin + if ( (rd_popping) ) begin + NV_AFIFO_rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + NV_AFIFO_rd_data <= {50{`x_or_0}}; + end +//synopsys translate_on +end +assign rd_data = NV_AFIFO_rd_data; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign wr_clk_wr_mgated_enable = dft_qualifier_wr_enable && (wr_reserving || wr_pushing || wr_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +assign rd_clk_rd_mgated_enable = dft_qualifier_rd_enable && ((rd_pushing || rd_popping || (rd_req_int && rd_ready))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( wr_req && !(!wr_ready) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( wr_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSB_MASTER_falcon2csb_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [49:0] di; +input iwe; +input we; +input [1:0] wa; +input [1:0] ra; +output [49:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [49:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [49:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [49:0] ram_ff0; +reg [49:0] ram_ff1; +reg [49:0] ram_ff2; +reg [49:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [49:0] dout; +always @(*) begin + case( ra ) // synopsys infer_mux_override + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {50{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [49:0] Di0; +input [1:0] Ra0; +output [49:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 50'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [49:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [49:0] Q0 = mem[0]; +wire [49:0] Q1 = mem[1]; +wire [49:0] Q2 = mem[2]; +wire [49:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50] } +endmodule // vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +//vmw: Memory vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +//vmw: Address-size 2 +//vmw: Data-size 50 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[49:0] data0[49:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[49:0] data1[49:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// See the ASYNCHONROUS BOUNDARY section above for details on the +// gray counter implementation. +// +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict ( +`ifdef NV_FPGA_FIFOGEN + inc , +`endif + gray + , gray_next + ); +`ifdef NV_FPGA_FIFOGEN +input inc; +`endif +input [2:0] gray; +output [2:0] gray_next; +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1] ^ gray[2]; +assign gray_next = +`ifdef NV_FPGA_FIFOGEN + (~inc) ? gray : +`endif + { gray[2]^(polarity &~gray[0]), + gray[1]^(polarity&gray[0]), + gray[0]^(~polarity) }; +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr ( + clk + , reset_ + , inc + , gray + ); +input clk; +input reset_; +input inc; +output [2:0] gray; +reg [2:0] gray; // gray counter +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1] ^ gray[2]; + always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + gray <= 3'd0; + end else if ( inc ) begin + gray <= { gray[2]^(polarity &~gray[0]), + gray[1]^(polarity&gray[0]), + gray[0]^(~polarity) }; + end +end +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr diff --git a/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v.vcp new file mode 100644 index 0000000..17c639e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v.vcp @@ -0,0 +1,1035 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo ( + wr_clk + , wr_reset_ + , wr_ready + , wr_req +`ifdef FV_RAND_WR_PAUSE + , wr_pause +`endif + , wr_data + , rd_clk + , rd_reset_ + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input wr_clk; +input wr_reset_; +output wr_ready; +input wr_req; +`ifdef FV_RAND_WR_PAUSE +input wr_pause; +`endif +input [49:0] wr_data; +input rd_clk; +input rd_reset_; +input rd_ready; +output rd_req; +output [49:0] rd_data; +input [31:0] pwrbus_ram_pd; +// +// DFT clock gate enable qualifier +// +// Write side +wire dft_qualifier_wr_enable; +oneHotClk_async_write_clock fifogenDFTWrQual ( .enable_w( dft_qualifier_wr_enable ) ); +wire wr_clk_dft_mgated; +NV_CLK_gate_power wr_clk_wr_dft_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable), .clk_gated(wr_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_wr_clkgate_sink (.A( wr_clk_dft_mgated ) ); +`endif +// Read side +wire dft_qualifier_rd_enable; +oneHotClk_async_read_clock fifogenDFTRdQual ( .enable_r( dft_qualifier_rd_enable ) ); +wire rd_clk_dft_mgated; +NV_CLK_gate_power rd_clk_rd_dft_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable), .clk_gated(rd_clk_dft_mgated) ); +`ifndef FPGA +// Add a dummy sink to prevent issue related to no fanout on this clock gate +NV_BLKBOX_SINK UJ_BLKBOX_UNUSED_FIFOGEN_dft_rd_clkgate_sink (.A( rd_clk_dft_mgated ) ); +`endif +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire wr_clk_wr_mgated_enable; // assigned by code at end of this module +wire wr_clk_wr_mgated; +NV_CLK_gate_power wr_clk_wr_mgate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(wr_clk_wr_mgated_enable), .clk_gated(wr_clk_wr_mgated) ); +wire rd_clk_rd_mgated_enable; // assigned by code at end of this module +wire rd_clk_rd_mgated; +NV_CLK_gate_power rd_clk_rd_mgate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(rd_clk_rd_mgated_enable), .clk_gated(rd_clk_rd_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || wr_pause ; +`else +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 3'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [1:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [1:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge wr_clk_wr_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +reg [1:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [49:0] rd_data_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 ram ( + .clk( wr_clk_dft_mgated ) + , .clk_mgated( wr_clk_wr_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( rd_adr ) + , .dout ( rd_data_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// ASYNCHRONOUS BOUNDARY USING TRADITIONAL SYNCHRONIZERS +// +// Our goal here is to translate wr_pushing pulses into rd_pushing +// pulses on the read side and, conversely, to translate rd_popping +// pulses to wr_popping pulses on the write side. +// +// We don't try to optimize the case where the async fifo depth is +// a power of two. We handle the general case using one scheme to +// avoid maintaining different implementations. We may use a couple +// more counters, but they are quite cheap in the grand scheme of things. +// This wr_pushing/rd_pushing/rd_popping/wr_popping centric scheme also +// fits in well with the case where there is no asynchronous boundary. +// +// The scheme works as follows. For the wr_pushing -> rd_pushing translation, +// we keep an 3-bit gray counter on the write and read sides. +// This counter is initialized to 0 on both sides. When wr_pushing +// is pulsed, the write side gray-increments its counter, registers it, +// then sends it through an 3-bit synchronizer to the other side. +// Whenever the read side sees the new gray counter not equal to its +// copy of the gray counter, it gray-increments its counter and pulses +// rd_pushing=1. The actual value of the gray counter is irrelevant. +// It must be a power-of-2 to make the gray code work. Otherwise, +// we're just looking for changes in the gray value. +// +// The same technique is used for the rd_popping -> wr_popping translation. +// +// The gray counter algorithm uses a 1-bit polarity register that starts +// off as 0 and is inverted whenever the gray counter is incremented. +// +// In plain English, the next gray counter is determined as follows: +// if the current polarity register is 0, invert bit 0 (the lsb); otherwise, +// find the rightmost one bit and invert the bit to the left of the one bit +// if the one bit is not the msb else invert the msb one bit. The +// general expression is thus: +// +// { gray[n-1] ^ (polarity & ~gray[n-3] & ~gray[n-4] & ... ), +// gray[n-2] ^ (polarity & gray[n-3] & ~gray[n-4] & ~gray[n-5] & ... ), +// gray[n-3] ^ (polarity & gray[n-4] & ~gray[n-5] & ~gray[n-6] & ... ), +// ... +// gray[0] ^ (~polarity) } +// +// For n == 1, the next gray value is obviously just ~gray. +// +// The wr_pushing/rd_popping signal does not affect the registered +// gray counter until the next cycle. However, for non-FF-type rams, +// the write will not complete until the end of the next cycle, so +// we must delay wr_pushing yet another more cycle, +// unless the -rd_clk_le_2x_wr_clk option was given +// (or the -rd_clk_le_2x_wr_clk_dynamic option was given +// and the rd_clk_le_2x_wr_clk signal is 1). +// +// clk gating of strict synchronizers +// +wire wr_clk_wr_mgated_strict_snd_gated; +NV_CLK_gate_power wr_clk_wr_mgated_snd_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_pushing)), .clk_gated(wr_clk_wr_mgated_strict_snd_gated) ); +// +// wr_pushing -> rd_pushing translation +// +wire [2:0] wr_pushing_gray_cntr; +wire [2:0] wr_pushing_gray_cntr_next; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict wr_pushing_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( wr_pushing ) , +`endif + .gray ( wr_pushing_gray_cntr ) + , .gray_next ( wr_pushing_gray_cntr_next ) + ); +wire [2:0] wr_pushing_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync0 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[0] ) + , .SRC_D ( wr_pushing_gray_cntr[0] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync1 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[1] ) + , .SRC_D ( wr_pushing_gray_cntr[1] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_wr_pushing_sync2 ( + .SRC_CLK ( wr_clk_wr_mgated_strict_snd_gated ) + , .SRC_CLRN ( wr_reset_ ) + , .SRC_D_NEXT ( wr_pushing_gray_cntr_next[2] ) + , .SRC_D ( wr_pushing_gray_cntr[2] ) + , .DST_CLK ( rd_clk_dft_mgated ) + , .DST_CLRN ( rd_reset_ ) + , .DST_Q ( wr_pushing_gray_cntr_sync[2] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [2:0] rd_pushing_gray_cntr; +wire rd_pushing = wr_pushing_gray_cntr_sync != rd_pushing_gray_cntr; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr rd_pushing_gray ( + .clk ( rd_clk_rd_mgated ) + , .reset_ ( rd_reset_ ) + , .inc ( rd_pushing ) + , .gray ( rd_pushing_gray_cntr ) + ); +// clk gating of strict synchronizers +// +wire rd_clk_rd_mgated_strict_snd_gated; +NV_CLK_gate_power rd_clk_rd_mgated_snd_gate( .clk(rd_clk), .reset_(rd_reset_), .clk_en(dft_qualifier_rd_enable && (rd_popping)), .clk_gated(rd_clk_rd_mgated_strict_snd_gated) ); +wire wr_clk_strict_rcv_gated; +NV_CLK_gate_power wr_clk_rcv_gate( .clk(wr_clk), .reset_(wr_reset_), .clk_en(dft_qualifier_wr_enable && (wr_count_next_no_wr_popping != 3'd0)), .clk_gated(wr_clk_strict_rcv_gated) ); +// +// rd_popping -> wr_popping translation +// +wire [2:0] rd_popping_gray_cntr; +wire [2:0] rd_popping_gray_cntr_next; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict rd_popping_gray ( +`ifdef NV_FPGA_FIFOGEN + .inc ( rd_popping ) , +`endif + .gray ( rd_popping_gray_cntr ) + , .gray_next ( rd_popping_gray_cntr_next ) + ); +wire [2:0] rd_popping_gray_cntr_sync; +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync0 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[0] ) + , .SRC_D ( rd_popping_gray_cntr[0] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[0] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync1 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[1] ) + , .SRC_D ( rd_popping_gray_cntr[1] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[1] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +p_STRICTSYNC3DOTM_C_PPP NV_AFIFO_rd_popping_sync2 ( + .SRC_CLK ( rd_clk_rd_mgated_strict_snd_gated ) + , .SRC_CLRN ( rd_reset_ ) + , .SRC_D_NEXT ( rd_popping_gray_cntr_next[2] ) + , .SRC_D ( rd_popping_gray_cntr[2] ) + , .DST_CLK ( wr_clk_strict_rcv_gated ) + , .DST_CLRN ( wr_reset_ ) + , .DST_Q ( rd_popping_gray_cntr_sync[2] ) + , .ATPG_CTL ( 1'b0 ) + , .TEST_MODE ( 1'b0 ) + ); +wire [2:0] wr_popping_gray_cntr; +assign wr_popping = rd_popping_gray_cntr_sync != wr_popping_gray_cntr; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr wr_popping_gray ( + .clk ( wr_clk_wr_mgated ) + , .reset_ ( wr_reset_ ) + , .inc ( wr_popping ) + , .gray ( wr_popping_gray_cntr ) + ); +// +// READ SIDE +// +wire rd_req_p; // data out of fifo is valid +reg rd_req_int; // internal copy of rd_req +assign rd_req = rd_req_int; +assign rd_popping = rd_req_p && !(rd_req_int && !rd_ready); +reg [2:0] rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? rd_count_p : + (rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (rd_count_p + 1'd1) : + rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign rd_req_p = rd_count_p != 0 || rd_pushing; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [49:0] NV_AFIFO_rd_data; // output data register +wire rd_req_next = (rd_req_p || (rd_req_int && !rd_ready)) ; +always @( posedge rd_clk_rd_mgated or negedge rd_reset_ ) begin + if ( !rd_reset_ ) begin + rd_req_int <= 1'b0; + end else begin + rd_req_int <= rd_req_next; + end +end +always @( posedge rd_clk_rd_mgated ) begin + if ( (rd_popping) ) begin + NV_AFIFO_rd_data <= rd_data_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + NV_AFIFO_rd_data <= {50{`x_or_0}}; + end +//synopsys translate_on +end +assign rd_data = NV_AFIFO_rd_data; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign wr_clk_wr_mgated_enable = dft_qualifier_wr_enable && (wr_reserving || wr_pushing || wr_popping || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +assign rd_clk_rd_mgated_enable = dft_qualifier_rd_enable && ((rd_pushing || rd_popping || (rd_req_int && rd_ready))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CSB_MASTER_falcon2csb_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge wr_clk_dft_mgated or negedge wr_reset_ ) begin + if ( !wr_reset_ ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( wr_req && !(!wr_ready) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( wr_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSB_MASTER_falcon2csb_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [49:0] di; +input iwe; +input we; +input [1:0] wa; +input [1:0] ra; +output [49:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [49:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [49:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [49:0] ram_ff0; +reg [49:0] ram_ff1; +reg [49:0] ram_ff2; +reg [49:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [49:0] dout; +always @(*) begin + case( ra ) // synopsys infer_mux_override + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {50{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [49:0] Di0; +input [1:0] Ra0; +output [49:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 50'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [49:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [49:0] Q0 = mem[0]; +wire [49:0] Q1 = mem[1]; +wire [49:0] Q2 = mem[2]; +wire [49:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50] } +endmodule // vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +//vmw: Memory vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +//vmw: Address-size 2 +//vmw: Data-size 50 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[49:0] data0[49:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[49:0] data1[49:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSB_MASTER_falcon2csb_fifo_flopram_rwa_4x50 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// See the ASYNCHONROUS BOUNDARY section above for details on the +// gray counter implementation. +// +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict ( +`ifdef NV_FPGA_FIFOGEN + inc , +`endif + gray + , gray_next + ); +`ifdef NV_FPGA_FIFOGEN +input inc; +`endif +input [2:0] gray; +output [2:0] gray_next; +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1] ^ gray[2]; +assign gray_next = +`ifdef NV_FPGA_FIFOGEN + (~inc) ? gray : +`endif + { gray[2]^(polarity &~gray[0]), + gray[1]^(polarity&gray[0]), + gray[0]^(~polarity) }; +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr_strict +module NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr ( + clk + , reset_ + , inc + , gray + ); +input clk; +input reset_; +input inc; +output [2:0] gray; +reg [2:0] gray; // gray counter +wire polarity; // polarity of gray counter bits +assign polarity = gray[0] ^ gray[1] ^ gray[2]; + always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + gray <= 3'd0; + end else if ( inc ) begin + gray <= { gray[2]^(polarity &~gray[0]), + gray[1]^(polarity&gray[0]), + gray[0]^(~polarity) }; + end +end +endmodule // NV_NVDLA_CSB_MASTER_falcon2csb_fifo_gray_cntr diff --git a/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_csb_master.v b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_csb_master.v new file mode 100644 index 0000000..b2e11a3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_csb_master.v @@ -0,0 +1,1210 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_csb_master.v +`include "simulate_x_tick.vh" +module NV_NVDLA_csb_master ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,nvdla_falcon_clk //|< i + ,nvdla_falcon_rstn //|< i + ,pwrbus_ram_pd //|< i + ,csb2nvdla_valid //|< i + ,csb2nvdla_ready //|> o + ,csb2nvdla_addr //|< i + ,csb2nvdla_wdat //|< i + ,csb2nvdla_write //|< i + ,csb2nvdla_nposted //|< i + ,nvdla2csb_valid //|> o + ,nvdla2csb_data //|> o + ,nvdla2csb_wr_complete //|> o + ,csb2cfgrom_req_pvld //|> o + ,csb2cfgrom_req_prdy //|< i + ,csb2cfgrom_req_pd //|> o + ,cfgrom2csb_resp_valid //|< i + ,cfgrom2csb_resp_pd //|< i + ,csb2glb_req_pvld //|> o + ,csb2glb_req_prdy //|< i + ,csb2glb_req_pd //|> o + ,glb2csb_resp_valid //|< i + ,glb2csb_resp_pd //|< i + ,csb2mcif_req_pvld //|> o + ,csb2mcif_req_prdy //|< i + ,csb2mcif_req_pd //|> o + ,mcif2csb_resp_valid //|< i + ,mcif2csb_resp_pd //|< i + ,csb2cdma_req_pvld //|> o + ,csb2cdma_req_prdy //|< i + ,csb2cdma_req_pd //|> o + ,cdma2csb_resp_valid //|< i + ,cdma2csb_resp_pd //|< i + ,csb2csc_req_pvld //|> o + ,csb2csc_req_prdy //|< i + ,csb2csc_req_pd //|> o + ,csc2csb_resp_valid //|< i + ,csc2csb_resp_pd //|< i + ,csb2cmac_a_req_pvld //|> o + ,csb2cmac_a_req_prdy //|< i + ,csb2cmac_a_req_pd //|> o + ,cmac_a2csb_resp_valid //|< i + ,cmac_a2csb_resp_pd //|< i + ,csb2cmac_b_req_pvld //|> o + ,csb2cmac_b_req_prdy //|< i + ,csb2cmac_b_req_pd //|> o + ,cmac_b2csb_resp_valid //|< i + ,cmac_b2csb_resp_pd //|< i + ,csb2cacc_req_pvld //|> o + ,csb2cacc_req_prdy //|< i + ,csb2cacc_req_pd //|> o + ,cacc2csb_resp_valid //|< i + ,cacc2csb_resp_pd //|< i + ,csb2sdp_rdma_req_pvld //|> o + ,csb2sdp_rdma_req_prdy //|< i + ,csb2sdp_rdma_req_pd //|> o + ,sdp_rdma2csb_resp_valid //|< i + ,sdp_rdma2csb_resp_pd //|< i + ,csb2sdp_req_pvld //|> o + ,csb2sdp_req_prdy //|< i + ,csb2sdp_req_pd //|> o + ,sdp2csb_resp_valid //|< i + ,sdp2csb_resp_pd //|< i + ,csb2pdp_rdma_req_pvld //|> o + ,csb2pdp_rdma_req_prdy //|< i + ,csb2pdp_rdma_req_pd //|> o + ,pdp_rdma2csb_resp_valid //|< i + ,pdp_rdma2csb_resp_pd //|< i + ,csb2pdp_req_pvld //|> o + ,csb2pdp_req_prdy //|< i + ,csb2pdp_req_pd //|> o + ,pdp2csb_resp_valid //|< i + ,pdp2csb_resp_pd //|< i + ,csb2cdp_rdma_req_pvld //|> o + ,csb2cdp_rdma_req_prdy //|< i + ,csb2cdp_rdma_req_pd //|> o + ,cdp_rdma2csb_resp_valid //|< i + ,cdp_rdma2csb_resp_pd //|< i + ,csb2cdp_req_pvld //|> o + ,csb2cdp_req_prdy //|< i + ,csb2cdp_req_pd //|> o + ,cdp2csb_resp_valid //|< i + ,cdp2csb_resp_pd //|< i + ); +// +// NV_NVDLA_csb_master_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input nvdla_falcon_clk; /* csb2nvdla, nvdla2csb, nvdla2csb_wr */ +input nvdla_falcon_rstn; /* csb2nvdla, nvdla2csb, nvdla2csb_wr */ +input [31:0] pwrbus_ram_pd; +input csb2nvdla_valid; /* data valid */ +output csb2nvdla_ready; /* data return handshake */ +input [15:0] csb2nvdla_addr; +input [31:0] csb2nvdla_wdat; +input csb2nvdla_write; +input csb2nvdla_nposted; +output nvdla2csb_valid; /* data valid */ +output [31:0] nvdla2csb_data; +output nvdla2csb_wr_complete; +output csb2cfgrom_req_pvld; /* data valid */ +input csb2cfgrom_req_prdy; /* data return handshake */ +output [62:0] csb2cfgrom_req_pd; +input cfgrom2csb_resp_valid; /* data valid */ +input [33:0] cfgrom2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2glb_req_pvld; /* data valid */ +input csb2glb_req_prdy; /* data return handshake */ +output [62:0] csb2glb_req_pd; +input glb2csb_resp_valid; /* data valid */ +input [33:0] glb2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2mcif_req_pvld; /* data valid */ +input csb2mcif_req_prdy; /* data return handshake */ +output [62:0] csb2mcif_req_pd; +input mcif2csb_resp_valid; /* data valid */ +input [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cdma_req_pvld; /* data valid */ +input csb2cdma_req_prdy; /* data return handshake */ +output [62:0] csb2cdma_req_pd; +input cdma2csb_resp_valid; /* data valid */ +input [33:0] cdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2csc_req_pvld; /* data valid */ +input csb2csc_req_prdy; /* data return handshake */ +output [62:0] csb2csc_req_pd; +input csc2csb_resp_valid; /* data valid */ +input [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_a_req_pvld; /* data valid */ +input csb2cmac_a_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_a_req_pd; +input cmac_a2csb_resp_valid; /* data valid */ +input [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_b_req_pvld; /* data valid */ +input csb2cmac_b_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_b_req_pd; +input cmac_b2csb_resp_valid; /* data valid */ +input [33:0] cmac_b2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cacc_req_pvld; /* data valid */ +input csb2cacc_req_prdy; /* data return handshake */ +output [62:0] csb2cacc_req_pd; +input cacc2csb_resp_valid; /* data valid */ +input [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2sdp_rdma_req_pvld; /* data valid */ +input csb2sdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_rdma_req_pd; +input sdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] sdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2sdp_req_pvld; /* data valid */ +input csb2sdp_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_req_pd; +input sdp2csb_resp_valid; /* data valid */ +input [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2pdp_rdma_req_pvld; /* data valid */ +input csb2pdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2pdp_rdma_req_pd; +input pdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] pdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2pdp_req_pvld; /* data valid */ +input csb2pdp_req_prdy; /* data return handshake */ +output [62:0] csb2pdp_req_pd; +input pdp2csb_resp_valid; /* data valid */ +input [33:0] pdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cdp_rdma_req_pvld; /* data valid */ +input csb2cdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2cdp_rdma_req_pd; +input cdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cdp_req_pvld; /* data valid */ +input csb2cdp_req_prdy; /* data return handshake */ +output [62:0] csb2cdp_req_pd; +input cdp2csb_resp_valid; /* data valid */ +input [33:0] cdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +///////////////////////////////////////////////////////////////// +reg [49:0] csb2cfgrom_req_pd_tmp; +reg csb2cfgrom_req_pvld; +reg cfgrom_req_pvld; +reg [33:0] cfgrom_resp_pd; +reg cfgrom_resp_valid; +wire csb2cfgrom_req_en; +wire csb2cfgrom_req_pvld_w; +wire cfgrom_req_pvld_w; +reg [49:0] csb2glb_req_pd_tmp; +reg csb2glb_req_pvld; +reg glb_req_pvld; +reg [33:0] glb_resp_pd; +reg glb_resp_valid; +wire csb2glb_req_en; +wire csb2glb_req_pvld_w; +wire glb_req_pvld_w; +reg [49:0] csb2mcif_req_pd_tmp; +reg csb2mcif_req_pvld; +reg mcif_req_pvld; +reg [33:0] mcif_resp_pd; +reg mcif_resp_valid; +wire csb2mcif_req_en; +wire csb2mcif_req_pvld_w; +wire mcif_req_pvld_w; +reg [49:0] csb2cdma_req_pd_tmp; +reg csb2cdma_req_pvld; +reg cdma_req_pvld; +reg [33:0] cdma_resp_pd; +reg cdma_resp_valid; +wire csb2cdma_req_en; +wire csb2cdma_req_pvld_w; +wire cdma_req_pvld_w; +reg [49:0] csb2csc_req_pd_tmp; +reg csb2csc_req_pvld; +reg csc_req_pvld; +reg [33:0] csc_resp_pd; +reg csc_resp_valid; +wire csb2csc_req_en; +wire csb2csc_req_pvld_w; +wire csc_req_pvld_w; +reg [49:0] csb2cmac_a_req_pd_tmp; +reg csb2cmac_a_req_pvld; +reg cmac_a_req_pvld; +reg [33:0] cmac_a_resp_pd; +reg cmac_a_resp_valid; +wire csb2cmac_a_req_en; +wire csb2cmac_a_req_pvld_w; +wire cmac_a_req_pvld_w; +reg [49:0] csb2cmac_b_req_pd_tmp; +reg csb2cmac_b_req_pvld; +reg cmac_b_req_pvld; +reg [33:0] cmac_b_resp_pd; +reg cmac_b_resp_valid; +wire csb2cmac_b_req_en; +wire csb2cmac_b_req_pvld_w; +wire cmac_b_req_pvld_w; +reg [49:0] csb2cacc_req_pd_tmp; +reg csb2cacc_req_pvld; +reg cacc_req_pvld; +reg [33:0] cacc_resp_pd; +reg cacc_resp_valid; +wire csb2cacc_req_en; +wire csb2cacc_req_pvld_w; +wire cacc_req_pvld_w; +reg [49:0] csb2sdp_rdma_req_pd_tmp; +reg csb2sdp_rdma_req_pvld; +reg sdp_rdma_req_pvld; +reg [33:0] sdp_rdma_resp_pd; +reg sdp_rdma_resp_valid; +wire csb2sdp_rdma_req_en; +wire csb2sdp_rdma_req_pvld_w; +wire sdp_rdma_req_pvld_w; +reg [49:0] csb2sdp_req_pd_tmp; +reg csb2sdp_req_pvld; +reg sdp_req_pvld; +reg [33:0] sdp_resp_pd; +reg sdp_resp_valid; +wire csb2sdp_req_en; +wire csb2sdp_req_pvld_w; +wire sdp_req_pvld_w; +reg [49:0] csb2pdp_rdma_req_pd_tmp; +reg csb2pdp_rdma_req_pvld; +reg pdp_rdma_req_pvld; +reg [33:0] pdp_rdma_resp_pd; +reg pdp_rdma_resp_valid; +wire csb2pdp_rdma_req_en; +wire csb2pdp_rdma_req_pvld_w; +wire pdp_rdma_req_pvld_w; +reg [49:0] csb2pdp_req_pd_tmp; +reg csb2pdp_req_pvld; +reg pdp_req_pvld; +reg [33:0] pdp_resp_pd; +reg pdp_resp_valid; +wire csb2pdp_req_en; +wire csb2pdp_req_pvld_w; +wire pdp_req_pvld_w; +reg [49:0] csb2cdp_rdma_req_pd_tmp; +reg csb2cdp_rdma_req_pvld; +reg cdp_rdma_req_pvld; +reg [33:0] cdp_rdma_resp_pd; +reg cdp_rdma_resp_valid; +wire csb2cdp_rdma_req_en; +wire csb2cdp_rdma_req_pvld_w; +wire cdp_rdma_req_pvld_w; +reg [49:0] csb2cdp_req_pd_tmp; +reg csb2cdp_req_pvld; +reg cdp_req_pvld; +reg [33:0] cdp_resp_pd; +reg cdp_resp_valid; +wire csb2cdp_req_en; +wire csb2cdp_req_pvld_w; +wire cdp_req_pvld_w; +reg csb2dummy_req_nposted; +reg csb2dummy_req_pvld; +reg csb2dummy_req_read; +reg dummy_resp_type; +reg dummy_resp_valid; +wire dummy_req_pvld_w; +wire dummy_resp_error; +wire [33:0] dummy_resp_pd; +wire [31:0] dummy_resp_rdat; +wire dummy_resp_type_w; +wire dummy_resp_valid_w; +wire [33:0] dummy_rresp_pd; +wire [33:0] dummy_wresp_pd; +reg [49:0] core_req_pd_d1; +reg [31:0] nvdla2csb_data; +reg nvdla2csb_valid; +reg nvdla2csb_wr_complete; +wire [17:0] addr_mask; +wire [17:0] core_byte_addr; +wire [15:0] core_req_addr; +wire core_req_nposted; +wire [49:0] core_req_pd; +wire core_req_pop_valid; +wire core_req_prdy; +wire core_req_pvld; +wire core_req_write; +wire [33:0] core_resp_pd; +wire core_resp_prdy; +wire core_resp_pvld; +wire [49:0] csb2nvdla_pd; +wire [33:0] nvdla2csb_resp_pd; +wire nvdla2csb_resp_pvld; +wire nvdla2csb_rresp_is_valid; +wire [31:0] nvdla2csb_rresp_rdat; +wire nvdla2csb_wresp_is_valid; +wire select_cfgrom; +wire select_glb; +wire select_mcif; +wire select_cvif; +wire select_bdma; +wire select_cacc; +wire select_cdma; +wire select_cdp; +wire select_cdp_rdma; +wire select_cmac_a; +wire select_cmac_b; +wire select_csc; +wire select_dummy; +wire select_pdp; +wire select_pdp_rdma; +wire select_rbk; +wire select_sdp; +wire select_sdp_rdma; +//////////////////////////////////////////////////////////////////////// +// CSB interface to async FIFO // +//////////////////////////////////////////////////////////////////////// +assign csb2nvdla_pd[49:0] = {csb2nvdla_nposted,csb2nvdla_write,csb2nvdla_wdat,csb2nvdla_addr}; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo u_fifo_csb2nvdla ( + .wr_clk (nvdla_falcon_clk) //|< i + ,.wr_reset_ (nvdla_falcon_rstn) //|< i + ,.wr_ready (csb2nvdla_ready) //|> o + ,.wr_req (csb2nvdla_valid) //|< i + ,.wr_data (csb2nvdla_pd[49:0]) //|< w + ,.rd_clk (nvdla_core_clk) //|< i + ,.rd_reset_ (nvdla_core_rstn) //|< i + ,.rd_ready (core_req_prdy) //|< w + ,.rd_req (core_req_pvld) //|> w + ,.rd_data (core_req_pd[49:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); +assign core_req_prdy = 1'b1; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo u_fifo_nvdla2csb ( + .wr_clk (nvdla_core_clk) //|< i + ,.wr_reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (core_resp_prdy) //|> w * + ,.wr_req (core_resp_pvld) //|< w + ,.wr_data (core_resp_pd[33:0]) //|< w + ,.rd_clk (nvdla_falcon_clk) //|< i + ,.rd_reset_ (nvdla_falcon_rstn) //|< i + ,.rd_ready (1'b1) //|< ? + ,.rd_req (nvdla2csb_resp_pvld) //|> w + ,.rd_data (nvdla2csb_resp_pd[33:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); +assign nvdla2csb_rresp_rdat[31:0] = nvdla2csb_resp_pd[31:0]; +assign nvdla2csb_rresp_is_valid = (nvdla2csb_resp_pvld && (nvdla2csb_resp_pd[33:33] == 1'd0)); +assign nvdla2csb_wresp_is_valid = (nvdla2csb_resp_pvld && (nvdla2csb_resp_pd[33:33] == 1'd1)); +always @(posedge nvdla_falcon_clk or negedge nvdla_falcon_rstn) begin + if (!nvdla_falcon_rstn) begin + nvdla2csb_valid <= 1'b0; + end else begin + nvdla2csb_valid <= nvdla2csb_rresp_is_valid; + end +end +always @(posedge nvdla_falcon_clk or negedge nvdla_falcon_rstn) begin + if (!nvdla_falcon_rstn) begin + nvdla2csb_data <= {32{1'b0}}; + end else begin + if(nvdla2csb_rresp_is_valid) + begin + nvdla2csb_data <= nvdla2csb_rresp_rdat; + end + end +end +always @(posedge nvdla_falcon_clk or negedge nvdla_falcon_rstn) begin + if (!nvdla_falcon_rstn) begin + nvdla2csb_wr_complete <= 1'b0; + end else begin + nvdla2csb_wr_complete <= nvdla2csb_wresp_is_valid; + end +end +//////////////////////////////////////////////////////////////////////// +// Distribute request and gather response // +//////////////////////////////////////////////////////////////////////// +assign core_req_addr = core_req_pd[15:0]; +assign core_req_write = core_req_pd[48]; +assign core_req_nposted = core_req_pd[49]; +assign core_req_pop_valid = core_req_pvld & core_req_prdy; +//core_req_addr is word aligned while address from arnvdla is byte aligned. +assign core_byte_addr = {core_req_addr, 2'b0}; +always @(posedge nvdla_core_clk) begin + if ((core_req_pvld & core_req_prdy) == 1'b1) begin + core_req_pd_d1 <= core_req_pd; + end +end +assign addr_mask = {{16 -10{1'b1}},{12{1'b0}}}; +//////////////// for CFGROM //////////////// +assign select_cfgrom = ((core_byte_addr & addr_mask) == 32'h00000000); +assign cfgrom_req_pvld_w = (core_req_pop_valid & select_cfgrom) ? 1'b1 : + (csb2cfgrom_req_prdy | ~csb2cfgrom_req_pvld) ? 1'b0 : + cfgrom_req_pvld; +assign csb2cfgrom_req_pvld_w = cfgrom_req_pvld ? 1'b1 : + csb2cfgrom_req_prdy ? 1'b0 : + csb2cfgrom_req_pvld; +assign csb2cfgrom_req_en = cfgrom_req_pvld & (csb2cfgrom_req_prdy | ~csb2cfgrom_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom_req_pvld <= 1'b0; + end else begin + cfgrom_req_pvld <= cfgrom_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cfgrom_req_pvld <= 1'b0; + end else begin + csb2cfgrom_req_pvld <= csb2cfgrom_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cfgrom_req_en) == 1'b1) begin + csb2cfgrom_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cfgrom_req_pd ={7'h0,csb2cfgrom_req_pd_tmp[49:16],6'h0,csb2cfgrom_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom_resp_valid <= 1'b0; + end else begin + cfgrom_resp_valid <= cfgrom2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cfgrom2csb_resp_valid) == 1'b1) begin + cfgrom_resp_pd <= cfgrom2csb_resp_pd; + end +end +//////////////// for GLB //////////////// +assign select_glb = ((core_byte_addr & addr_mask) == 32'h00001000); +assign glb_req_pvld_w = (core_req_pop_valid & select_glb) ? 1'b1 : + (csb2glb_req_prdy | ~csb2glb_req_pvld) ? 1'b0 : + glb_req_pvld; +assign csb2glb_req_pvld_w = glb_req_pvld ? 1'b1 : + csb2glb_req_prdy ? 1'b0 : + csb2glb_req_pvld; +assign csb2glb_req_en = glb_req_pvld & (csb2glb_req_prdy | ~csb2glb_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + glb_req_pvld <= 1'b0; + end else begin + glb_req_pvld <= glb_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2glb_req_pvld <= 1'b0; + end else begin + csb2glb_req_pvld <= csb2glb_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2glb_req_en) == 1'b1) begin + csb2glb_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2glb_req_pd ={7'h0,csb2glb_req_pd_tmp[49:16],6'h0,csb2glb_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + glb_resp_valid <= 1'b0; + end else begin + glb_resp_valid <= glb2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((glb2csb_resp_valid) == 1'b1) begin + glb_resp_pd <= glb2csb_resp_pd; + end +end +//////////////// for MCIF //////////////// +assign select_mcif = ((core_byte_addr & addr_mask) == 32'h00002000); +assign mcif_req_pvld_w = (core_req_pop_valid & select_mcif) ? 1'b1 : + (csb2mcif_req_prdy | ~csb2mcif_req_pvld) ? 1'b0 : + mcif_req_pvld; +assign csb2mcif_req_pvld_w = mcif_req_pvld ? 1'b1 : + csb2mcif_req_prdy ? 1'b0 : + csb2mcif_req_pvld; +assign csb2mcif_req_en = mcif_req_pvld & (csb2mcif_req_prdy | ~csb2mcif_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif_req_pvld <= 1'b0; + end else begin + mcif_req_pvld <= mcif_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2mcif_req_pvld <= 1'b0; + end else begin + csb2mcif_req_pvld <= csb2mcif_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2mcif_req_en) == 1'b1) begin + csb2mcif_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2mcif_req_pd ={7'h0,csb2mcif_req_pd_tmp[49:16],6'h0,csb2mcif_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif_resp_valid <= 1'b0; + end else begin + mcif_resp_valid <= mcif2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((mcif2csb_resp_valid) == 1'b1) begin + mcif_resp_pd <= mcif2csb_resp_pd; + end +end +assign select_bdma = 1'b0; +//////////////// for CDMA //////////////// +assign select_cdma = ((core_byte_addr & addr_mask) == 32'h00003000); +assign cdma_req_pvld_w = (core_req_pop_valid & select_cdma) ? 1'b1 : + (csb2cdma_req_prdy | ~csb2cdma_req_pvld) ? 1'b0 : + cdma_req_pvld; +assign csb2cdma_req_pvld_w = cdma_req_pvld ? 1'b1 : + csb2cdma_req_prdy ? 1'b0 : + csb2cdma_req_pvld; +assign csb2cdma_req_en = cdma_req_pvld & (csb2cdma_req_prdy | ~csb2cdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_req_pvld <= 1'b0; + end else begin + cdma_req_pvld <= cdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cdma_req_pvld <= 1'b0; + end else begin + csb2cdma_req_pvld <= csb2cdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cdma_req_en) == 1'b1) begin + csb2cdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cdma_req_pd ={7'h0,csb2cdma_req_pd_tmp[49:16],6'h0,csb2cdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_resp_valid <= 1'b0; + end else begin + cdma_resp_valid <= cdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cdma2csb_resp_valid) == 1'b1) begin + cdma_resp_pd <= cdma2csb_resp_pd; + end +end +//////////////// for CSC //////////////// +assign select_csc = ((core_byte_addr & addr_mask) == 32'h00004000); +assign csc_req_pvld_w = (core_req_pop_valid & select_csc) ? 1'b1 : + (csb2csc_req_prdy | ~csb2csc_req_pvld) ? 1'b0 : + csc_req_pvld; +assign csb2csc_req_pvld_w = csc_req_pvld ? 1'b1 : + csb2csc_req_prdy ? 1'b0 : + csb2csc_req_pvld; +assign csb2csc_req_en = csc_req_pvld & (csb2csc_req_prdy | ~csb2csc_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc_req_pvld <= 1'b0; + end else begin + csc_req_pvld <= csc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2csc_req_pvld <= 1'b0; + end else begin + csb2csc_req_pvld <= csb2csc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2csc_req_en) == 1'b1) begin + csb2csc_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2csc_req_pd ={7'h0,csb2csc_req_pd_tmp[49:16],6'h0,csb2csc_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc_resp_valid <= 1'b0; + end else begin + csc_resp_valid <= csc2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((csc2csb_resp_valid) == 1'b1) begin + csc_resp_pd <= csc2csb_resp_pd; + end +end +//////////////// for CMAC_A //////////////// +assign select_cmac_a = ((core_byte_addr & addr_mask) == 32'h00005000); +assign cmac_a_req_pvld_w = (core_req_pop_valid & select_cmac_a) ? 1'b1 : + (csb2cmac_a_req_prdy | ~csb2cmac_a_req_pvld) ? 1'b0 : + cmac_a_req_pvld; +assign csb2cmac_a_req_pvld_w = cmac_a_req_pvld ? 1'b1 : + csb2cmac_a_req_prdy ? 1'b0 : + csb2cmac_a_req_pvld; +assign csb2cmac_a_req_en = cmac_a_req_pvld & (csb2cmac_a_req_prdy | ~csb2cmac_a_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a_req_pvld <= 1'b0; + end else begin + cmac_a_req_pvld <= cmac_a_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_a_req_pvld <= 1'b0; + end else begin + csb2cmac_a_req_pvld <= csb2cmac_a_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_a_req_en) == 1'b1) begin + csb2cmac_a_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cmac_a_req_pd ={7'h0,csb2cmac_a_req_pd_tmp[49:16],6'h0,csb2cmac_a_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a_resp_valid <= 1'b0; + end else begin + cmac_a_resp_valid <= cmac_a2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac_a2csb_resp_valid) == 1'b1) begin + cmac_a_resp_pd <= cmac_a2csb_resp_pd; + end +end +//////////////// for CMAC_B //////////////// +assign select_cmac_b = ((core_byte_addr & addr_mask) == 32'h00006000); +assign cmac_b_req_pvld_w = (core_req_pop_valid & select_cmac_b) ? 1'b1 : + (csb2cmac_b_req_prdy | ~csb2cmac_b_req_pvld) ? 1'b0 : + cmac_b_req_pvld; +assign csb2cmac_b_req_pvld_w = cmac_b_req_pvld ? 1'b1 : + csb2cmac_b_req_prdy ? 1'b0 : + csb2cmac_b_req_pvld; +assign csb2cmac_b_req_en = cmac_b_req_pvld & (csb2cmac_b_req_prdy | ~csb2cmac_b_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_b_req_pvld <= 1'b0; + end else begin + cmac_b_req_pvld <= cmac_b_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_b_req_pvld <= 1'b0; + end else begin + csb2cmac_b_req_pvld <= csb2cmac_b_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_b_req_en) == 1'b1) begin + csb2cmac_b_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cmac_b_req_pd ={7'h0,csb2cmac_b_req_pd_tmp[49:16],6'h0,csb2cmac_b_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_b_resp_valid <= 1'b0; + end else begin + cmac_b_resp_valid <= cmac_b2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac_b2csb_resp_valid) == 1'b1) begin + cmac_b_resp_pd <= cmac_b2csb_resp_pd; + end +end +//////////////// for CACC //////////////// +assign select_cacc = ((core_byte_addr & addr_mask) == 32'h00007000); +assign cacc_req_pvld_w = (core_req_pop_valid & select_cacc) ? 1'b1 : + (csb2cacc_req_prdy | ~csb2cacc_req_pvld) ? 1'b0 : + cacc_req_pvld; +assign csb2cacc_req_pvld_w = cacc_req_pvld ? 1'b1 : + csb2cacc_req_prdy ? 1'b0 : + csb2cacc_req_pvld; +assign csb2cacc_req_en = cacc_req_pvld & (csb2cacc_req_prdy | ~csb2cacc_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_req_pvld <= 1'b0; + end else begin + cacc_req_pvld <= cacc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld <= 1'b0; + end else begin + csb2cacc_req_pvld <= csb2cacc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_en) == 1'b1) begin + csb2cacc_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cacc_req_pd ={7'h0,csb2cacc_req_pd_tmp[49:16],6'h0,csb2cacc_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_resp_valid <= 1'b0; + end else begin + cacc_resp_valid <= cacc2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid) == 1'b1) begin + cacc_resp_pd <= cacc2csb_resp_pd; + end +end +//////////////// for SDP_RDMA //////////////// +assign select_sdp_rdma = ((core_byte_addr & addr_mask) == 32'h00008000); +assign sdp_rdma_req_pvld_w = (core_req_pop_valid & select_sdp_rdma) ? 1'b1 : + (csb2sdp_rdma_req_prdy | ~csb2sdp_rdma_req_pvld) ? 1'b0 : + sdp_rdma_req_pvld; +assign csb2sdp_rdma_req_pvld_w = sdp_rdma_req_pvld ? 1'b1 : + csb2sdp_rdma_req_prdy ? 1'b0 : + csb2sdp_rdma_req_pvld; +assign csb2sdp_rdma_req_en = sdp_rdma_req_pvld & (csb2sdp_rdma_req_prdy | ~csb2sdp_rdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma_req_pvld <= 1'b0; + end else begin + sdp_rdma_req_pvld <= sdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2sdp_rdma_req_pvld <= 1'b0; + end else begin + csb2sdp_rdma_req_pvld <= csb2sdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2sdp_rdma_req_en) == 1'b1) begin + csb2sdp_rdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2sdp_rdma_req_pd ={7'h0,csb2sdp_rdma_req_pd_tmp[49:16],6'h0,csb2sdp_rdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma_resp_valid <= 1'b0; + end else begin + sdp_rdma_resp_valid <= sdp_rdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((sdp_rdma2csb_resp_valid) == 1'b1) begin + sdp_rdma_resp_pd <= sdp_rdma2csb_resp_pd; + end +end +//////////////// for SDP //////////////// +assign select_sdp = ((core_byte_addr & addr_mask) == 32'h00009000); +assign sdp_req_pvld_w = (core_req_pop_valid & select_sdp) ? 1'b1 : + (csb2sdp_req_prdy | ~csb2sdp_req_pvld) ? 1'b0 : + sdp_req_pvld; +assign csb2sdp_req_pvld_w = sdp_req_pvld ? 1'b1 : + csb2sdp_req_prdy ? 1'b0 : + csb2sdp_req_pvld; +assign csb2sdp_req_en = sdp_req_pvld & (csb2sdp_req_prdy | ~csb2sdp_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_req_pvld <= 1'b0; + end else begin + sdp_req_pvld <= sdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2sdp_req_pvld <= 1'b0; + end else begin + csb2sdp_req_pvld <= csb2sdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2sdp_req_en) == 1'b1) begin + csb2sdp_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2sdp_req_pd ={7'h0,csb2sdp_req_pd_tmp[49:16],6'h0,csb2sdp_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_resp_valid <= 1'b0; + end else begin + sdp_resp_valid <= sdp2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((sdp2csb_resp_valid) == 1'b1) begin + sdp_resp_pd <= sdp2csb_resp_pd; + end +end +//////////////// for PDP_RDMA //////////////// +assign select_pdp_rdma = ((core_byte_addr & addr_mask) == 32'h0000a000); +assign pdp_rdma_req_pvld_w = (core_req_pop_valid & select_pdp_rdma) ? 1'b1 : + (csb2pdp_rdma_req_prdy | ~csb2pdp_rdma_req_pvld) ? 1'b0 : + pdp_rdma_req_pvld; +assign csb2pdp_rdma_req_pvld_w = pdp_rdma_req_pvld ? 1'b1 : + csb2pdp_rdma_req_prdy ? 1'b0 : + csb2pdp_rdma_req_pvld; +assign csb2pdp_rdma_req_en = pdp_rdma_req_pvld & (csb2pdp_rdma_req_prdy | ~csb2pdp_rdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma_req_pvld <= 1'b0; + end else begin + pdp_rdma_req_pvld <= pdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2pdp_rdma_req_pvld <= 1'b0; + end else begin + csb2pdp_rdma_req_pvld <= csb2pdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2pdp_rdma_req_en) == 1'b1) begin + csb2pdp_rdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2pdp_rdma_req_pd ={7'h0,csb2pdp_rdma_req_pd_tmp[49:16],6'h0,csb2pdp_rdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma_resp_valid <= 1'b0; + end else begin + pdp_rdma_resp_valid <= pdp_rdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((pdp_rdma2csb_resp_valid) == 1'b1) begin + pdp_rdma_resp_pd <= pdp_rdma2csb_resp_pd; + end +end +//////////////// for PDP //////////////// +assign select_pdp = ((core_byte_addr & addr_mask) == 32'h0000b000); +assign pdp_req_pvld_w = (core_req_pop_valid & select_pdp) ? 1'b1 : + (csb2pdp_req_prdy | ~csb2pdp_req_pvld) ? 1'b0 : + pdp_req_pvld; +assign csb2pdp_req_pvld_w = pdp_req_pvld ? 1'b1 : + csb2pdp_req_prdy ? 1'b0 : + csb2pdp_req_pvld; +assign csb2pdp_req_en = pdp_req_pvld & (csb2pdp_req_prdy | ~csb2pdp_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_req_pvld <= 1'b0; + end else begin + pdp_req_pvld <= pdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2pdp_req_pvld <= 1'b0; + end else begin + csb2pdp_req_pvld <= csb2pdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2pdp_req_en) == 1'b1) begin + csb2pdp_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2pdp_req_pd ={7'h0,csb2pdp_req_pd_tmp[49:16],6'h0,csb2pdp_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_resp_valid <= 1'b0; + end else begin + pdp_resp_valid <= pdp2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((pdp2csb_resp_valid) == 1'b1) begin + pdp_resp_pd <= pdp2csb_resp_pd; + end +end +//////////////// for CDP_RDMA //////////////// +assign select_cdp_rdma = ((core_byte_addr & addr_mask) == 32'h0000c000); +assign cdp_rdma_req_pvld_w = (core_req_pop_valid & select_cdp_rdma) ? 1'b1 : + (csb2cdp_rdma_req_prdy | ~csb2cdp_rdma_req_pvld) ? 1'b0 : + cdp_rdma_req_pvld; +assign csb2cdp_rdma_req_pvld_w = cdp_rdma_req_pvld ? 1'b1 : + csb2cdp_rdma_req_prdy ? 1'b0 : + csb2cdp_rdma_req_pvld; +assign csb2cdp_rdma_req_en = cdp_rdma_req_pvld & (csb2cdp_rdma_req_prdy | ~csb2cdp_rdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma_req_pvld <= 1'b0; + end else begin + cdp_rdma_req_pvld <= cdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cdp_rdma_req_pvld <= 1'b0; + end else begin + csb2cdp_rdma_req_pvld <= csb2cdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cdp_rdma_req_en) == 1'b1) begin + csb2cdp_rdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cdp_rdma_req_pd ={7'h0,csb2cdp_rdma_req_pd_tmp[49:16],6'h0,csb2cdp_rdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma_resp_valid <= 1'b0; + end else begin + cdp_rdma_resp_valid <= cdp_rdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cdp_rdma2csb_resp_valid) == 1'b1) begin + cdp_rdma_resp_pd <= cdp_rdma2csb_resp_pd; + end +end +//////////////// for CDP //////////////// +assign select_cdp = ((core_byte_addr & addr_mask) == 32'h0000d000); +assign cdp_req_pvld_w = (core_req_pop_valid & select_cdp) ? 1'b1 : + (csb2cdp_req_prdy | ~csb2cdp_req_pvld) ? 1'b0 : + cdp_req_pvld; +assign csb2cdp_req_pvld_w = cdp_req_pvld ? 1'b1 : + csb2cdp_req_prdy ? 1'b0 : + csb2cdp_req_pvld; +assign csb2cdp_req_en = cdp_req_pvld & (csb2cdp_req_prdy | ~csb2cdp_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_req_pvld <= 1'b0; + end else begin + cdp_req_pvld <= cdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cdp_req_pvld <= 1'b0; + end else begin + csb2cdp_req_pvld <= csb2cdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cdp_req_en) == 1'b1) begin + csb2cdp_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cdp_req_pd ={7'h0,csb2cdp_req_pd_tmp[49:16],6'h0,csb2cdp_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_resp_valid <= 1'b0; + end else begin + cdp_resp_valid <= cdp2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cdp2csb_resp_valid) == 1'b1) begin + cdp_resp_pd <= cdp2csb_resp_pd; + end +end +assign select_rbk = 1'b0; +//////////////// for DUMMY //////////////// +////////////////// dummy client ////////////////////// +assign select_dummy = ~(select_cfgrom + | select_glb + | select_mcif + | select_bdma + | select_cdma + | select_csc + | select_cmac_a + | select_cmac_b + | select_cacc + | select_sdp_rdma + | select_sdp + | select_pdp_rdma + | select_pdp + | select_cdp + | select_cdp_rdma + | select_rbk); +assign dummy_req_pvld_w = (core_req_pop_valid & select_dummy); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2dummy_req_pvld <= 1'b0; + end else begin + csb2dummy_req_pvld <= dummy_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((dummy_req_pvld_w) == 1'b1) begin + csb2dummy_req_nposted <= core_req_nposted; + end +end +always @(posedge nvdla_core_clk) begin + if ((dummy_req_pvld_w) == 1'b1) begin + csb2dummy_req_read <= ~core_req_write; + end +end +assign dummy_rresp_pd[31:0] = dummy_resp_rdat[31:0]; +assign dummy_rresp_pd[32] = dummy_resp_error ; +assign dummy_rresp_pd[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +assign dummy_wresp_pd[31:0] = dummy_resp_rdat[31:0]; +assign dummy_wresp_pd[32] = dummy_resp_error ; +assign dummy_wresp_pd[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign dummy_resp_rdat = {32 {1'b0}}; +assign dummy_resp_error = 1'b0; +assign dummy_resp_valid_w = csb2dummy_req_pvld & (csb2dummy_req_nposted | csb2dummy_req_read); +assign dummy_resp_type_w = ~csb2dummy_req_read & csb2dummy_req_nposted; +assign dummy_resp_pd = dummy_resp_type ? dummy_wresp_pd : dummy_rresp_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dummy_resp_valid <= 1'b0; + end else begin + dummy_resp_valid <= dummy_resp_valid_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dummy_resp_type <= 1'b0; + end else begin + if ((dummy_resp_valid_w) == 1'b1) begin + dummy_resp_type <= dummy_resp_type_w; + end + end +end +//////////////// assimble //////////////// +assign core_resp_pd = ( ({34 {cfgrom_resp_valid}} & cfgrom_resp_pd) + | ({34 {glb_resp_valid}} & glb_resp_pd) + | ({34 {mcif_resp_valid}} & mcif_resp_pd) + | ({34 {cdma_resp_valid}} & cdma_resp_pd) + | ({34 {csc_resp_valid}} & csc_resp_pd) + | ({34 {cmac_a_resp_valid}} & cmac_a_resp_pd) + | ({34 {cmac_b_resp_valid}} & cmac_b_resp_pd) + | ({34 {cacc_resp_valid}} & cacc_resp_pd) + | ({34 {sdp_rdma_resp_valid}} & sdp_rdma_resp_pd) + | ({34 {sdp_resp_valid}} & sdp_resp_pd) + | ({34 {pdp_rdma_resp_valid}} & pdp_rdma_resp_pd) + | ({34 {pdp_resp_valid}} & pdp_resp_pd) + | ({34 {cdp_resp_valid}} & cdp_resp_pd) + | ({34 {cdp_rdma_resp_valid}} & cdp_rdma_resp_pd) + | ({34 {dummy_resp_valid}} & dummy_resp_pd)); +assign core_resp_pvld = cfgrom_resp_valid | + glb_resp_valid | + mcif_resp_valid | + cdma_resp_valid | + csc_resp_valid | + cmac_a_resp_valid | + cmac_b_resp_valid | + cacc_resp_valid | + sdp_rdma_resp_valid | + sdp_resp_valid | + pdp_rdma_resp_valid | + pdp_resp_valid | + cdp_rdma_resp_valid | + cdp_resp_valid | + dummy_resp_valid; +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property csb_master__read_dummy_client__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (core_req_pop_valid & ~core_req_write & select_dummy); + endproperty +// Cover 0 : "(core_req_pop_valid & ~core_req_write & select_dummy)" + FUNCPOINT_csb_master__read_dummy_client__0_COV : cover property (csb_master__read_dummy_client__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property csb_master__posted_write_dummy_client__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (core_req_pop_valid & core_req_write & ~core_req_nposted & select_dummy); + endproperty +// Cover 1 : "(core_req_pop_valid & core_req_write & ~core_req_nposted & select_dummy)" + FUNCPOINT_csb_master__posted_write_dummy_client__1_COV : cover property (csb_master__posted_write_dummy_client__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property csb_master__non_posted_dummy_client__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (core_req_pop_valid & core_req_write & core_req_nposted & select_dummy); + endproperty +// Cover 2 : "(core_req_pop_valid & core_req_write & core_req_nposted & select_dummy)" + FUNCPOINT_csb_master__non_posted_dummy_client__2_COV : cover property (csb_master__non_posted_dummy_client__2_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dummy_resp_valid_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! core response fifo block!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (core_resp_pvld & ~core_resp_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,19,0,"Error! Multiple response!") zzz_assert_zero_one_hot_3x (nvdla_core_clk, `ASSERT_RESET, {cfgrom2csb_resp_valid, + glb2csb_resp_valid, + mcif2csb_resp_valid, + bdma2csb_resp_valid, + cdma2csb_resp_valid, + csc2csb_resp_valid, + cmac_a2csb_resp_valid, + cmac_b2csb_resp_valid, + cacc2csb_resp_valid, + sdp_rdma2csb_resp_valid, + sdp2csb_resp_valid, + pdp_rdma2csb_resp_valid, + pdp2csb_resp_valid, + cdp_rdma2csb_resp_valid, + cdp2csb_resp_valid, + rbk2csb_resp_valid, + dummy_resp_valid}); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_csb_master diff --git a/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_csb_master.v.vcp b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_csb_master.v.vcp new file mode 100644 index 0000000..b2e11a3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csb_master/NV_NVDLA_csb_master.v.vcp @@ -0,0 +1,1210 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_csb_master.v +`include "simulate_x_tick.vh" +module NV_NVDLA_csb_master ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,nvdla_falcon_clk //|< i + ,nvdla_falcon_rstn //|< i + ,pwrbus_ram_pd //|< i + ,csb2nvdla_valid //|< i + ,csb2nvdla_ready //|> o + ,csb2nvdla_addr //|< i + ,csb2nvdla_wdat //|< i + ,csb2nvdla_write //|< i + ,csb2nvdla_nposted //|< i + ,nvdla2csb_valid //|> o + ,nvdla2csb_data //|> o + ,nvdla2csb_wr_complete //|> o + ,csb2cfgrom_req_pvld //|> o + ,csb2cfgrom_req_prdy //|< i + ,csb2cfgrom_req_pd //|> o + ,cfgrom2csb_resp_valid //|< i + ,cfgrom2csb_resp_pd //|< i + ,csb2glb_req_pvld //|> o + ,csb2glb_req_prdy //|< i + ,csb2glb_req_pd //|> o + ,glb2csb_resp_valid //|< i + ,glb2csb_resp_pd //|< i + ,csb2mcif_req_pvld //|> o + ,csb2mcif_req_prdy //|< i + ,csb2mcif_req_pd //|> o + ,mcif2csb_resp_valid //|< i + ,mcif2csb_resp_pd //|< i + ,csb2cdma_req_pvld //|> o + ,csb2cdma_req_prdy //|< i + ,csb2cdma_req_pd //|> o + ,cdma2csb_resp_valid //|< i + ,cdma2csb_resp_pd //|< i + ,csb2csc_req_pvld //|> o + ,csb2csc_req_prdy //|< i + ,csb2csc_req_pd //|> o + ,csc2csb_resp_valid //|< i + ,csc2csb_resp_pd //|< i + ,csb2cmac_a_req_pvld //|> o + ,csb2cmac_a_req_prdy //|< i + ,csb2cmac_a_req_pd //|> o + ,cmac_a2csb_resp_valid //|< i + ,cmac_a2csb_resp_pd //|< i + ,csb2cmac_b_req_pvld //|> o + ,csb2cmac_b_req_prdy //|< i + ,csb2cmac_b_req_pd //|> o + ,cmac_b2csb_resp_valid //|< i + ,cmac_b2csb_resp_pd //|< i + ,csb2cacc_req_pvld //|> o + ,csb2cacc_req_prdy //|< i + ,csb2cacc_req_pd //|> o + ,cacc2csb_resp_valid //|< i + ,cacc2csb_resp_pd //|< i + ,csb2sdp_rdma_req_pvld //|> o + ,csb2sdp_rdma_req_prdy //|< i + ,csb2sdp_rdma_req_pd //|> o + ,sdp_rdma2csb_resp_valid //|< i + ,sdp_rdma2csb_resp_pd //|< i + ,csb2sdp_req_pvld //|> o + ,csb2sdp_req_prdy //|< i + ,csb2sdp_req_pd //|> o + ,sdp2csb_resp_valid //|< i + ,sdp2csb_resp_pd //|< i + ,csb2pdp_rdma_req_pvld //|> o + ,csb2pdp_rdma_req_prdy //|< i + ,csb2pdp_rdma_req_pd //|> o + ,pdp_rdma2csb_resp_valid //|< i + ,pdp_rdma2csb_resp_pd //|< i + ,csb2pdp_req_pvld //|> o + ,csb2pdp_req_prdy //|< i + ,csb2pdp_req_pd //|> o + ,pdp2csb_resp_valid //|< i + ,pdp2csb_resp_pd //|< i + ,csb2cdp_rdma_req_pvld //|> o + ,csb2cdp_rdma_req_prdy //|< i + ,csb2cdp_rdma_req_pd //|> o + ,cdp_rdma2csb_resp_valid //|< i + ,cdp_rdma2csb_resp_pd //|< i + ,csb2cdp_req_pvld //|> o + ,csb2cdp_req_prdy //|< i + ,csb2cdp_req_pd //|> o + ,cdp2csb_resp_valid //|< i + ,cdp2csb_resp_pd //|< i + ); +// +// NV_NVDLA_csb_master_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input nvdla_falcon_clk; /* csb2nvdla, nvdla2csb, nvdla2csb_wr */ +input nvdla_falcon_rstn; /* csb2nvdla, nvdla2csb, nvdla2csb_wr */ +input [31:0] pwrbus_ram_pd; +input csb2nvdla_valid; /* data valid */ +output csb2nvdla_ready; /* data return handshake */ +input [15:0] csb2nvdla_addr; +input [31:0] csb2nvdla_wdat; +input csb2nvdla_write; +input csb2nvdla_nposted; +output nvdla2csb_valid; /* data valid */ +output [31:0] nvdla2csb_data; +output nvdla2csb_wr_complete; +output csb2cfgrom_req_pvld; /* data valid */ +input csb2cfgrom_req_prdy; /* data return handshake */ +output [62:0] csb2cfgrom_req_pd; +input cfgrom2csb_resp_valid; /* data valid */ +input [33:0] cfgrom2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2glb_req_pvld; /* data valid */ +input csb2glb_req_prdy; /* data return handshake */ +output [62:0] csb2glb_req_pd; +input glb2csb_resp_valid; /* data valid */ +input [33:0] glb2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2mcif_req_pvld; /* data valid */ +input csb2mcif_req_prdy; /* data return handshake */ +output [62:0] csb2mcif_req_pd; +input mcif2csb_resp_valid; /* data valid */ +input [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cdma_req_pvld; /* data valid */ +input csb2cdma_req_prdy; /* data return handshake */ +output [62:0] csb2cdma_req_pd; +input cdma2csb_resp_valid; /* data valid */ +input [33:0] cdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2csc_req_pvld; /* data valid */ +input csb2csc_req_prdy; /* data return handshake */ +output [62:0] csb2csc_req_pd; +input csc2csb_resp_valid; /* data valid */ +input [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_a_req_pvld; /* data valid */ +input csb2cmac_a_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_a_req_pd; +input cmac_a2csb_resp_valid; /* data valid */ +input [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_b_req_pvld; /* data valid */ +input csb2cmac_b_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_b_req_pd; +input cmac_b2csb_resp_valid; /* data valid */ +input [33:0] cmac_b2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cacc_req_pvld; /* data valid */ +input csb2cacc_req_prdy; /* data return handshake */ +output [62:0] csb2cacc_req_pd; +input cacc2csb_resp_valid; /* data valid */ +input [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2sdp_rdma_req_pvld; /* data valid */ +input csb2sdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_rdma_req_pd; +input sdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] sdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2sdp_req_pvld; /* data valid */ +input csb2sdp_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_req_pd; +input sdp2csb_resp_valid; /* data valid */ +input [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2pdp_rdma_req_pvld; /* data valid */ +input csb2pdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2pdp_rdma_req_pd; +input pdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] pdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2pdp_req_pvld; /* data valid */ +input csb2pdp_req_prdy; /* data return handshake */ +output [62:0] csb2pdp_req_pd; +input pdp2csb_resp_valid; /* data valid */ +input [33:0] pdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cdp_rdma_req_pvld; /* data valid */ +input csb2cdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2cdp_rdma_req_pd; +input cdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] cdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cdp_req_pvld; /* data valid */ +input csb2cdp_req_prdy; /* data return handshake */ +output [62:0] csb2cdp_req_pd; +input cdp2csb_resp_valid; /* data valid */ +input [33:0] cdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +///////////////////////////////////////////////////////////////// +reg [49:0] csb2cfgrom_req_pd_tmp; +reg csb2cfgrom_req_pvld; +reg cfgrom_req_pvld; +reg [33:0] cfgrom_resp_pd; +reg cfgrom_resp_valid; +wire csb2cfgrom_req_en; +wire csb2cfgrom_req_pvld_w; +wire cfgrom_req_pvld_w; +reg [49:0] csb2glb_req_pd_tmp; +reg csb2glb_req_pvld; +reg glb_req_pvld; +reg [33:0] glb_resp_pd; +reg glb_resp_valid; +wire csb2glb_req_en; +wire csb2glb_req_pvld_w; +wire glb_req_pvld_w; +reg [49:0] csb2mcif_req_pd_tmp; +reg csb2mcif_req_pvld; +reg mcif_req_pvld; +reg [33:0] mcif_resp_pd; +reg mcif_resp_valid; +wire csb2mcif_req_en; +wire csb2mcif_req_pvld_w; +wire mcif_req_pvld_w; +reg [49:0] csb2cdma_req_pd_tmp; +reg csb2cdma_req_pvld; +reg cdma_req_pvld; +reg [33:0] cdma_resp_pd; +reg cdma_resp_valid; +wire csb2cdma_req_en; +wire csb2cdma_req_pvld_w; +wire cdma_req_pvld_w; +reg [49:0] csb2csc_req_pd_tmp; +reg csb2csc_req_pvld; +reg csc_req_pvld; +reg [33:0] csc_resp_pd; +reg csc_resp_valid; +wire csb2csc_req_en; +wire csb2csc_req_pvld_w; +wire csc_req_pvld_w; +reg [49:0] csb2cmac_a_req_pd_tmp; +reg csb2cmac_a_req_pvld; +reg cmac_a_req_pvld; +reg [33:0] cmac_a_resp_pd; +reg cmac_a_resp_valid; +wire csb2cmac_a_req_en; +wire csb2cmac_a_req_pvld_w; +wire cmac_a_req_pvld_w; +reg [49:0] csb2cmac_b_req_pd_tmp; +reg csb2cmac_b_req_pvld; +reg cmac_b_req_pvld; +reg [33:0] cmac_b_resp_pd; +reg cmac_b_resp_valid; +wire csb2cmac_b_req_en; +wire csb2cmac_b_req_pvld_w; +wire cmac_b_req_pvld_w; +reg [49:0] csb2cacc_req_pd_tmp; +reg csb2cacc_req_pvld; +reg cacc_req_pvld; +reg [33:0] cacc_resp_pd; +reg cacc_resp_valid; +wire csb2cacc_req_en; +wire csb2cacc_req_pvld_w; +wire cacc_req_pvld_w; +reg [49:0] csb2sdp_rdma_req_pd_tmp; +reg csb2sdp_rdma_req_pvld; +reg sdp_rdma_req_pvld; +reg [33:0] sdp_rdma_resp_pd; +reg sdp_rdma_resp_valid; +wire csb2sdp_rdma_req_en; +wire csb2sdp_rdma_req_pvld_w; +wire sdp_rdma_req_pvld_w; +reg [49:0] csb2sdp_req_pd_tmp; +reg csb2sdp_req_pvld; +reg sdp_req_pvld; +reg [33:0] sdp_resp_pd; +reg sdp_resp_valid; +wire csb2sdp_req_en; +wire csb2sdp_req_pvld_w; +wire sdp_req_pvld_w; +reg [49:0] csb2pdp_rdma_req_pd_tmp; +reg csb2pdp_rdma_req_pvld; +reg pdp_rdma_req_pvld; +reg [33:0] pdp_rdma_resp_pd; +reg pdp_rdma_resp_valid; +wire csb2pdp_rdma_req_en; +wire csb2pdp_rdma_req_pvld_w; +wire pdp_rdma_req_pvld_w; +reg [49:0] csb2pdp_req_pd_tmp; +reg csb2pdp_req_pvld; +reg pdp_req_pvld; +reg [33:0] pdp_resp_pd; +reg pdp_resp_valid; +wire csb2pdp_req_en; +wire csb2pdp_req_pvld_w; +wire pdp_req_pvld_w; +reg [49:0] csb2cdp_rdma_req_pd_tmp; +reg csb2cdp_rdma_req_pvld; +reg cdp_rdma_req_pvld; +reg [33:0] cdp_rdma_resp_pd; +reg cdp_rdma_resp_valid; +wire csb2cdp_rdma_req_en; +wire csb2cdp_rdma_req_pvld_w; +wire cdp_rdma_req_pvld_w; +reg [49:0] csb2cdp_req_pd_tmp; +reg csb2cdp_req_pvld; +reg cdp_req_pvld; +reg [33:0] cdp_resp_pd; +reg cdp_resp_valid; +wire csb2cdp_req_en; +wire csb2cdp_req_pvld_w; +wire cdp_req_pvld_w; +reg csb2dummy_req_nposted; +reg csb2dummy_req_pvld; +reg csb2dummy_req_read; +reg dummy_resp_type; +reg dummy_resp_valid; +wire dummy_req_pvld_w; +wire dummy_resp_error; +wire [33:0] dummy_resp_pd; +wire [31:0] dummy_resp_rdat; +wire dummy_resp_type_w; +wire dummy_resp_valid_w; +wire [33:0] dummy_rresp_pd; +wire [33:0] dummy_wresp_pd; +reg [49:0] core_req_pd_d1; +reg [31:0] nvdla2csb_data; +reg nvdla2csb_valid; +reg nvdla2csb_wr_complete; +wire [17:0] addr_mask; +wire [17:0] core_byte_addr; +wire [15:0] core_req_addr; +wire core_req_nposted; +wire [49:0] core_req_pd; +wire core_req_pop_valid; +wire core_req_prdy; +wire core_req_pvld; +wire core_req_write; +wire [33:0] core_resp_pd; +wire core_resp_prdy; +wire core_resp_pvld; +wire [49:0] csb2nvdla_pd; +wire [33:0] nvdla2csb_resp_pd; +wire nvdla2csb_resp_pvld; +wire nvdla2csb_rresp_is_valid; +wire [31:0] nvdla2csb_rresp_rdat; +wire nvdla2csb_wresp_is_valid; +wire select_cfgrom; +wire select_glb; +wire select_mcif; +wire select_cvif; +wire select_bdma; +wire select_cacc; +wire select_cdma; +wire select_cdp; +wire select_cdp_rdma; +wire select_cmac_a; +wire select_cmac_b; +wire select_csc; +wire select_dummy; +wire select_pdp; +wire select_pdp_rdma; +wire select_rbk; +wire select_sdp; +wire select_sdp_rdma; +//////////////////////////////////////////////////////////////////////// +// CSB interface to async FIFO // +//////////////////////////////////////////////////////////////////////// +assign csb2nvdla_pd[49:0] = {csb2nvdla_nposted,csb2nvdla_write,csb2nvdla_wdat,csb2nvdla_addr}; +NV_NVDLA_CSB_MASTER_falcon2csb_fifo u_fifo_csb2nvdla ( + .wr_clk (nvdla_falcon_clk) //|< i + ,.wr_reset_ (nvdla_falcon_rstn) //|< i + ,.wr_ready (csb2nvdla_ready) //|> o + ,.wr_req (csb2nvdla_valid) //|< i + ,.wr_data (csb2nvdla_pd[49:0]) //|< w + ,.rd_clk (nvdla_core_clk) //|< i + ,.rd_reset_ (nvdla_core_rstn) //|< i + ,.rd_ready (core_req_prdy) //|< w + ,.rd_req (core_req_pvld) //|> w + ,.rd_data (core_req_pd[49:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); +assign core_req_prdy = 1'b1; +NV_NVDLA_CSB_MASTER_csb2falcon_fifo u_fifo_nvdla2csb ( + .wr_clk (nvdla_core_clk) //|< i + ,.wr_reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (core_resp_prdy) //|> w * + ,.wr_req (core_resp_pvld) //|< w + ,.wr_data (core_resp_pd[33:0]) //|< w + ,.rd_clk (nvdla_falcon_clk) //|< i + ,.rd_reset_ (nvdla_falcon_rstn) //|< i + ,.rd_ready (1'b1) //|< ? + ,.rd_req (nvdla2csb_resp_pvld) //|> w + ,.rd_data (nvdla2csb_resp_pd[33:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i +); +assign nvdla2csb_rresp_rdat[31:0] = nvdla2csb_resp_pd[31:0]; +assign nvdla2csb_rresp_is_valid = (nvdla2csb_resp_pvld && (nvdla2csb_resp_pd[33:33] == 1'd0)); +assign nvdla2csb_wresp_is_valid = (nvdla2csb_resp_pvld && (nvdla2csb_resp_pd[33:33] == 1'd1)); +always @(posedge nvdla_falcon_clk or negedge nvdla_falcon_rstn) begin + if (!nvdla_falcon_rstn) begin + nvdla2csb_valid <= 1'b0; + end else begin + nvdla2csb_valid <= nvdla2csb_rresp_is_valid; + end +end +always @(posedge nvdla_falcon_clk or negedge nvdla_falcon_rstn) begin + if (!nvdla_falcon_rstn) begin + nvdla2csb_data <= {32{1'b0}}; + end else begin + if(nvdla2csb_rresp_is_valid) + begin + nvdla2csb_data <= nvdla2csb_rresp_rdat; + end + end +end +always @(posedge nvdla_falcon_clk or negedge nvdla_falcon_rstn) begin + if (!nvdla_falcon_rstn) begin + nvdla2csb_wr_complete <= 1'b0; + end else begin + nvdla2csb_wr_complete <= nvdla2csb_wresp_is_valid; + end +end +//////////////////////////////////////////////////////////////////////// +// Distribute request and gather response // +//////////////////////////////////////////////////////////////////////// +assign core_req_addr = core_req_pd[15:0]; +assign core_req_write = core_req_pd[48]; +assign core_req_nposted = core_req_pd[49]; +assign core_req_pop_valid = core_req_pvld & core_req_prdy; +//core_req_addr is word aligned while address from arnvdla is byte aligned. +assign core_byte_addr = {core_req_addr, 2'b0}; +always @(posedge nvdla_core_clk) begin + if ((core_req_pvld & core_req_prdy) == 1'b1) begin + core_req_pd_d1 <= core_req_pd; + end +end +assign addr_mask = {{16 -10{1'b1}},{12{1'b0}}}; +//////////////// for CFGROM //////////////// +assign select_cfgrom = ((core_byte_addr & addr_mask) == 32'h00000000); +assign cfgrom_req_pvld_w = (core_req_pop_valid & select_cfgrom) ? 1'b1 : + (csb2cfgrom_req_prdy | ~csb2cfgrom_req_pvld) ? 1'b0 : + cfgrom_req_pvld; +assign csb2cfgrom_req_pvld_w = cfgrom_req_pvld ? 1'b1 : + csb2cfgrom_req_prdy ? 1'b0 : + csb2cfgrom_req_pvld; +assign csb2cfgrom_req_en = cfgrom_req_pvld & (csb2cfgrom_req_prdy | ~csb2cfgrom_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom_req_pvld <= 1'b0; + end else begin + cfgrom_req_pvld <= cfgrom_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cfgrom_req_pvld <= 1'b0; + end else begin + csb2cfgrom_req_pvld <= csb2cfgrom_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cfgrom_req_en) == 1'b1) begin + csb2cfgrom_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cfgrom_req_pd ={7'h0,csb2cfgrom_req_pd_tmp[49:16],6'h0,csb2cfgrom_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfgrom_resp_valid <= 1'b0; + end else begin + cfgrom_resp_valid <= cfgrom2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cfgrom2csb_resp_valid) == 1'b1) begin + cfgrom_resp_pd <= cfgrom2csb_resp_pd; + end +end +//////////////// for GLB //////////////// +assign select_glb = ((core_byte_addr & addr_mask) == 32'h00001000); +assign glb_req_pvld_w = (core_req_pop_valid & select_glb) ? 1'b1 : + (csb2glb_req_prdy | ~csb2glb_req_pvld) ? 1'b0 : + glb_req_pvld; +assign csb2glb_req_pvld_w = glb_req_pvld ? 1'b1 : + csb2glb_req_prdy ? 1'b0 : + csb2glb_req_pvld; +assign csb2glb_req_en = glb_req_pvld & (csb2glb_req_prdy | ~csb2glb_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + glb_req_pvld <= 1'b0; + end else begin + glb_req_pvld <= glb_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2glb_req_pvld <= 1'b0; + end else begin + csb2glb_req_pvld <= csb2glb_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2glb_req_en) == 1'b1) begin + csb2glb_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2glb_req_pd ={7'h0,csb2glb_req_pd_tmp[49:16],6'h0,csb2glb_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + glb_resp_valid <= 1'b0; + end else begin + glb_resp_valid <= glb2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((glb2csb_resp_valid) == 1'b1) begin + glb_resp_pd <= glb2csb_resp_pd; + end +end +//////////////// for MCIF //////////////// +assign select_mcif = ((core_byte_addr & addr_mask) == 32'h00002000); +assign mcif_req_pvld_w = (core_req_pop_valid & select_mcif) ? 1'b1 : + (csb2mcif_req_prdy | ~csb2mcif_req_pvld) ? 1'b0 : + mcif_req_pvld; +assign csb2mcif_req_pvld_w = mcif_req_pvld ? 1'b1 : + csb2mcif_req_prdy ? 1'b0 : + csb2mcif_req_pvld; +assign csb2mcif_req_en = mcif_req_pvld & (csb2mcif_req_prdy | ~csb2mcif_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif_req_pvld <= 1'b0; + end else begin + mcif_req_pvld <= mcif_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2mcif_req_pvld <= 1'b0; + end else begin + csb2mcif_req_pvld <= csb2mcif_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2mcif_req_en) == 1'b1) begin + csb2mcif_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2mcif_req_pd ={7'h0,csb2mcif_req_pd_tmp[49:16],6'h0,csb2mcif_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif_resp_valid <= 1'b0; + end else begin + mcif_resp_valid <= mcif2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((mcif2csb_resp_valid) == 1'b1) begin + mcif_resp_pd <= mcif2csb_resp_pd; + end +end +assign select_bdma = 1'b0; +//////////////// for CDMA //////////////// +assign select_cdma = ((core_byte_addr & addr_mask) == 32'h00003000); +assign cdma_req_pvld_w = (core_req_pop_valid & select_cdma) ? 1'b1 : + (csb2cdma_req_prdy | ~csb2cdma_req_pvld) ? 1'b0 : + cdma_req_pvld; +assign csb2cdma_req_pvld_w = cdma_req_pvld ? 1'b1 : + csb2cdma_req_prdy ? 1'b0 : + csb2cdma_req_pvld; +assign csb2cdma_req_en = cdma_req_pvld & (csb2cdma_req_prdy | ~csb2cdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_req_pvld <= 1'b0; + end else begin + cdma_req_pvld <= cdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cdma_req_pvld <= 1'b0; + end else begin + csb2cdma_req_pvld <= csb2cdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cdma_req_en) == 1'b1) begin + csb2cdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cdma_req_pd ={7'h0,csb2cdma_req_pd_tmp[49:16],6'h0,csb2cdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_resp_valid <= 1'b0; + end else begin + cdma_resp_valid <= cdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cdma2csb_resp_valid) == 1'b1) begin + cdma_resp_pd <= cdma2csb_resp_pd; + end +end +//////////////// for CSC //////////////// +assign select_csc = ((core_byte_addr & addr_mask) == 32'h00004000); +assign csc_req_pvld_w = (core_req_pop_valid & select_csc) ? 1'b1 : + (csb2csc_req_prdy | ~csb2csc_req_pvld) ? 1'b0 : + csc_req_pvld; +assign csb2csc_req_pvld_w = csc_req_pvld ? 1'b1 : + csb2csc_req_prdy ? 1'b0 : + csb2csc_req_pvld; +assign csb2csc_req_en = csc_req_pvld & (csb2csc_req_prdy | ~csb2csc_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc_req_pvld <= 1'b0; + end else begin + csc_req_pvld <= csc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2csc_req_pvld <= 1'b0; + end else begin + csb2csc_req_pvld <= csb2csc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2csc_req_en) == 1'b1) begin + csb2csc_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2csc_req_pd ={7'h0,csb2csc_req_pd_tmp[49:16],6'h0,csb2csc_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc_resp_valid <= 1'b0; + end else begin + csc_resp_valid <= csc2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((csc2csb_resp_valid) == 1'b1) begin + csc_resp_pd <= csc2csb_resp_pd; + end +end +//////////////// for CMAC_A //////////////// +assign select_cmac_a = ((core_byte_addr & addr_mask) == 32'h00005000); +assign cmac_a_req_pvld_w = (core_req_pop_valid & select_cmac_a) ? 1'b1 : + (csb2cmac_a_req_prdy | ~csb2cmac_a_req_pvld) ? 1'b0 : + cmac_a_req_pvld; +assign csb2cmac_a_req_pvld_w = cmac_a_req_pvld ? 1'b1 : + csb2cmac_a_req_prdy ? 1'b0 : + csb2cmac_a_req_pvld; +assign csb2cmac_a_req_en = cmac_a_req_pvld & (csb2cmac_a_req_prdy | ~csb2cmac_a_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a_req_pvld <= 1'b0; + end else begin + cmac_a_req_pvld <= cmac_a_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_a_req_pvld <= 1'b0; + end else begin + csb2cmac_a_req_pvld <= csb2cmac_a_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_a_req_en) == 1'b1) begin + csb2cmac_a_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cmac_a_req_pd ={7'h0,csb2cmac_a_req_pd_tmp[49:16],6'h0,csb2cmac_a_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_a_resp_valid <= 1'b0; + end else begin + cmac_a_resp_valid <= cmac_a2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac_a2csb_resp_valid) == 1'b1) begin + cmac_a_resp_pd <= cmac_a2csb_resp_pd; + end +end +//////////////// for CMAC_B //////////////// +assign select_cmac_b = ((core_byte_addr & addr_mask) == 32'h00006000); +assign cmac_b_req_pvld_w = (core_req_pop_valid & select_cmac_b) ? 1'b1 : + (csb2cmac_b_req_prdy | ~csb2cmac_b_req_pvld) ? 1'b0 : + cmac_b_req_pvld; +assign csb2cmac_b_req_pvld_w = cmac_b_req_pvld ? 1'b1 : + csb2cmac_b_req_prdy ? 1'b0 : + csb2cmac_b_req_pvld; +assign csb2cmac_b_req_en = cmac_b_req_pvld & (csb2cmac_b_req_prdy | ~csb2cmac_b_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_b_req_pvld <= 1'b0; + end else begin + cmac_b_req_pvld <= cmac_b_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_b_req_pvld <= 1'b0; + end else begin + csb2cmac_b_req_pvld <= csb2cmac_b_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_b_req_en) == 1'b1) begin + csb2cmac_b_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cmac_b_req_pd ={7'h0,csb2cmac_b_req_pd_tmp[49:16],6'h0,csb2cmac_b_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac_b_resp_valid <= 1'b0; + end else begin + cmac_b_resp_valid <= cmac_b2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac_b2csb_resp_valid) == 1'b1) begin + cmac_b_resp_pd <= cmac_b2csb_resp_pd; + end +end +//////////////// for CACC //////////////// +assign select_cacc = ((core_byte_addr & addr_mask) == 32'h00007000); +assign cacc_req_pvld_w = (core_req_pop_valid & select_cacc) ? 1'b1 : + (csb2cacc_req_prdy | ~csb2cacc_req_pvld) ? 1'b0 : + cacc_req_pvld; +assign csb2cacc_req_pvld_w = cacc_req_pvld ? 1'b1 : + csb2cacc_req_prdy ? 1'b0 : + csb2cacc_req_pvld; +assign csb2cacc_req_en = cacc_req_pvld & (csb2cacc_req_prdy | ~csb2cacc_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_req_pvld <= 1'b0; + end else begin + cacc_req_pvld <= cacc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld <= 1'b0; + end else begin + csb2cacc_req_pvld <= csb2cacc_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_en) == 1'b1) begin + csb2cacc_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cacc_req_pd ={7'h0,csb2cacc_req_pd_tmp[49:16],6'h0,csb2cacc_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_resp_valid <= 1'b0; + end else begin + cacc_resp_valid <= cacc2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid) == 1'b1) begin + cacc_resp_pd <= cacc2csb_resp_pd; + end +end +//////////////// for SDP_RDMA //////////////// +assign select_sdp_rdma = ((core_byte_addr & addr_mask) == 32'h00008000); +assign sdp_rdma_req_pvld_w = (core_req_pop_valid & select_sdp_rdma) ? 1'b1 : + (csb2sdp_rdma_req_prdy | ~csb2sdp_rdma_req_pvld) ? 1'b0 : + sdp_rdma_req_pvld; +assign csb2sdp_rdma_req_pvld_w = sdp_rdma_req_pvld ? 1'b1 : + csb2sdp_rdma_req_prdy ? 1'b0 : + csb2sdp_rdma_req_pvld; +assign csb2sdp_rdma_req_en = sdp_rdma_req_pvld & (csb2sdp_rdma_req_prdy | ~csb2sdp_rdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma_req_pvld <= 1'b0; + end else begin + sdp_rdma_req_pvld <= sdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2sdp_rdma_req_pvld <= 1'b0; + end else begin + csb2sdp_rdma_req_pvld <= csb2sdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2sdp_rdma_req_en) == 1'b1) begin + csb2sdp_rdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2sdp_rdma_req_pd ={7'h0,csb2sdp_rdma_req_pd_tmp[49:16],6'h0,csb2sdp_rdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma_resp_valid <= 1'b0; + end else begin + sdp_rdma_resp_valid <= sdp_rdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((sdp_rdma2csb_resp_valid) == 1'b1) begin + sdp_rdma_resp_pd <= sdp_rdma2csb_resp_pd; + end +end +//////////////// for SDP //////////////// +assign select_sdp = ((core_byte_addr & addr_mask) == 32'h00009000); +assign sdp_req_pvld_w = (core_req_pop_valid & select_sdp) ? 1'b1 : + (csb2sdp_req_prdy | ~csb2sdp_req_pvld) ? 1'b0 : + sdp_req_pvld; +assign csb2sdp_req_pvld_w = sdp_req_pvld ? 1'b1 : + csb2sdp_req_prdy ? 1'b0 : + csb2sdp_req_pvld; +assign csb2sdp_req_en = sdp_req_pvld & (csb2sdp_req_prdy | ~csb2sdp_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_req_pvld <= 1'b0; + end else begin + sdp_req_pvld <= sdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2sdp_req_pvld <= 1'b0; + end else begin + csb2sdp_req_pvld <= csb2sdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2sdp_req_en) == 1'b1) begin + csb2sdp_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2sdp_req_pd ={7'h0,csb2sdp_req_pd_tmp[49:16],6'h0,csb2sdp_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_resp_valid <= 1'b0; + end else begin + sdp_resp_valid <= sdp2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((sdp2csb_resp_valid) == 1'b1) begin + sdp_resp_pd <= sdp2csb_resp_pd; + end +end +//////////////// for PDP_RDMA //////////////// +assign select_pdp_rdma = ((core_byte_addr & addr_mask) == 32'h0000a000); +assign pdp_rdma_req_pvld_w = (core_req_pop_valid & select_pdp_rdma) ? 1'b1 : + (csb2pdp_rdma_req_prdy | ~csb2pdp_rdma_req_pvld) ? 1'b0 : + pdp_rdma_req_pvld; +assign csb2pdp_rdma_req_pvld_w = pdp_rdma_req_pvld ? 1'b1 : + csb2pdp_rdma_req_prdy ? 1'b0 : + csb2pdp_rdma_req_pvld; +assign csb2pdp_rdma_req_en = pdp_rdma_req_pvld & (csb2pdp_rdma_req_prdy | ~csb2pdp_rdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma_req_pvld <= 1'b0; + end else begin + pdp_rdma_req_pvld <= pdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2pdp_rdma_req_pvld <= 1'b0; + end else begin + csb2pdp_rdma_req_pvld <= csb2pdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2pdp_rdma_req_en) == 1'b1) begin + csb2pdp_rdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2pdp_rdma_req_pd ={7'h0,csb2pdp_rdma_req_pd_tmp[49:16],6'h0,csb2pdp_rdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma_resp_valid <= 1'b0; + end else begin + pdp_rdma_resp_valid <= pdp_rdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((pdp_rdma2csb_resp_valid) == 1'b1) begin + pdp_rdma_resp_pd <= pdp_rdma2csb_resp_pd; + end +end +//////////////// for PDP //////////////// +assign select_pdp = ((core_byte_addr & addr_mask) == 32'h0000b000); +assign pdp_req_pvld_w = (core_req_pop_valid & select_pdp) ? 1'b1 : + (csb2pdp_req_prdy | ~csb2pdp_req_pvld) ? 1'b0 : + pdp_req_pvld; +assign csb2pdp_req_pvld_w = pdp_req_pvld ? 1'b1 : + csb2pdp_req_prdy ? 1'b0 : + csb2pdp_req_pvld; +assign csb2pdp_req_en = pdp_req_pvld & (csb2pdp_req_prdy | ~csb2pdp_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_req_pvld <= 1'b0; + end else begin + pdp_req_pvld <= pdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2pdp_req_pvld <= 1'b0; + end else begin + csb2pdp_req_pvld <= csb2pdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2pdp_req_en) == 1'b1) begin + csb2pdp_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2pdp_req_pd ={7'h0,csb2pdp_req_pd_tmp[49:16],6'h0,csb2pdp_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_resp_valid <= 1'b0; + end else begin + pdp_resp_valid <= pdp2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((pdp2csb_resp_valid) == 1'b1) begin + pdp_resp_pd <= pdp2csb_resp_pd; + end +end +//////////////// for CDP_RDMA //////////////// +assign select_cdp_rdma = ((core_byte_addr & addr_mask) == 32'h0000c000); +assign cdp_rdma_req_pvld_w = (core_req_pop_valid & select_cdp_rdma) ? 1'b1 : + (csb2cdp_rdma_req_prdy | ~csb2cdp_rdma_req_pvld) ? 1'b0 : + cdp_rdma_req_pvld; +assign csb2cdp_rdma_req_pvld_w = cdp_rdma_req_pvld ? 1'b1 : + csb2cdp_rdma_req_prdy ? 1'b0 : + csb2cdp_rdma_req_pvld; +assign csb2cdp_rdma_req_en = cdp_rdma_req_pvld & (csb2cdp_rdma_req_prdy | ~csb2cdp_rdma_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma_req_pvld <= 1'b0; + end else begin + cdp_rdma_req_pvld <= cdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cdp_rdma_req_pvld <= 1'b0; + end else begin + csb2cdp_rdma_req_pvld <= csb2cdp_rdma_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cdp_rdma_req_en) == 1'b1) begin + csb2cdp_rdma_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cdp_rdma_req_pd ={7'h0,csb2cdp_rdma_req_pd_tmp[49:16],6'h0,csb2cdp_rdma_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_rdma_resp_valid <= 1'b0; + end else begin + cdp_rdma_resp_valid <= cdp_rdma2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cdp_rdma2csb_resp_valid) == 1'b1) begin + cdp_rdma_resp_pd <= cdp_rdma2csb_resp_pd; + end +end +//////////////// for CDP //////////////// +assign select_cdp = ((core_byte_addr & addr_mask) == 32'h0000d000); +assign cdp_req_pvld_w = (core_req_pop_valid & select_cdp) ? 1'b1 : + (csb2cdp_req_prdy | ~csb2cdp_req_pvld) ? 1'b0 : + cdp_req_pvld; +assign csb2cdp_req_pvld_w = cdp_req_pvld ? 1'b1 : + csb2cdp_req_prdy ? 1'b0 : + csb2cdp_req_pvld; +assign csb2cdp_req_en = cdp_req_pvld & (csb2cdp_req_prdy | ~csb2cdp_req_pvld); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_req_pvld <= 1'b0; + end else begin + cdp_req_pvld <= cdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cdp_req_pvld <= 1'b0; + end else begin + csb2cdp_req_pvld <= csb2cdp_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cdp_req_en) == 1'b1) begin + csb2cdp_req_pd_tmp <= core_req_pd_d1; + end +end +assign csb2cdp_req_pd ={7'h0,csb2cdp_req_pd_tmp[49:16],6'h0,csb2cdp_req_pd_tmp[15:0]}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_resp_valid <= 1'b0; + end else begin + cdp_resp_valid <= cdp2csb_resp_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((cdp2csb_resp_valid) == 1'b1) begin + cdp_resp_pd <= cdp2csb_resp_pd; + end +end +assign select_rbk = 1'b0; +//////////////// for DUMMY //////////////// +////////////////// dummy client ////////////////////// +assign select_dummy = ~(select_cfgrom + | select_glb + | select_mcif + | select_bdma + | select_cdma + | select_csc + | select_cmac_a + | select_cmac_b + | select_cacc + | select_sdp_rdma + | select_sdp + | select_pdp_rdma + | select_pdp + | select_cdp + | select_cdp_rdma + | select_rbk); +assign dummy_req_pvld_w = (core_req_pop_valid & select_dummy); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2dummy_req_pvld <= 1'b0; + end else begin + csb2dummy_req_pvld <= dummy_req_pvld_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((dummy_req_pvld_w) == 1'b1) begin + csb2dummy_req_nposted <= core_req_nposted; + end +end +always @(posedge nvdla_core_clk) begin + if ((dummy_req_pvld_w) == 1'b1) begin + csb2dummy_req_read <= ~core_req_write; + end +end +assign dummy_rresp_pd[31:0] = dummy_resp_rdat[31:0]; +assign dummy_rresp_pd[32] = dummy_resp_error ; +assign dummy_rresp_pd[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +assign dummy_wresp_pd[31:0] = dummy_resp_rdat[31:0]; +assign dummy_wresp_pd[32] = dummy_resp_error ; +assign dummy_wresp_pd[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign dummy_resp_rdat = {32 {1'b0}}; +assign dummy_resp_error = 1'b0; +assign dummy_resp_valid_w = csb2dummy_req_pvld & (csb2dummy_req_nposted | csb2dummy_req_read); +assign dummy_resp_type_w = ~csb2dummy_req_read & csb2dummy_req_nposted; +assign dummy_resp_pd = dummy_resp_type ? dummy_wresp_pd : dummy_rresp_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dummy_resp_valid <= 1'b0; + end else begin + dummy_resp_valid <= dummy_resp_valid_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dummy_resp_type <= 1'b0; + end else begin + if ((dummy_resp_valid_w) == 1'b1) begin + dummy_resp_type <= dummy_resp_type_w; + end + end +end +//////////////// assimble //////////////// +assign core_resp_pd = ( ({34 {cfgrom_resp_valid}} & cfgrom_resp_pd) + | ({34 {glb_resp_valid}} & glb_resp_pd) + | ({34 {mcif_resp_valid}} & mcif_resp_pd) + | ({34 {cdma_resp_valid}} & cdma_resp_pd) + | ({34 {csc_resp_valid}} & csc_resp_pd) + | ({34 {cmac_a_resp_valid}} & cmac_a_resp_pd) + | ({34 {cmac_b_resp_valid}} & cmac_b_resp_pd) + | ({34 {cacc_resp_valid}} & cacc_resp_pd) + | ({34 {sdp_rdma_resp_valid}} & sdp_rdma_resp_pd) + | ({34 {sdp_resp_valid}} & sdp_resp_pd) + | ({34 {pdp_rdma_resp_valid}} & pdp_rdma_resp_pd) + | ({34 {pdp_resp_valid}} & pdp_resp_pd) + | ({34 {cdp_resp_valid}} & cdp_resp_pd) + | ({34 {cdp_rdma_resp_valid}} & cdp_rdma_resp_pd) + | ({34 {dummy_resp_valid}} & dummy_resp_pd)); +assign core_resp_pvld = cfgrom_resp_valid | + glb_resp_valid | + mcif_resp_valid | + cdma_resp_valid | + csc_resp_valid | + cmac_a_resp_valid | + cmac_b_resp_valid | + cacc_resp_valid | + sdp_rdma_resp_valid | + sdp_resp_valid | + pdp_rdma_resp_valid | + pdp_resp_valid | + cdp_rdma_resp_valid | + cdp_resp_valid | + dummy_resp_valid; +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property csb_master__read_dummy_client__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (core_req_pop_valid & ~core_req_write & select_dummy); + endproperty +// Cover 0 : "(core_req_pop_valid & ~core_req_write & select_dummy)" + FUNCPOINT_csb_master__read_dummy_client__0_COV : cover property (csb_master__read_dummy_client__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property csb_master__posted_write_dummy_client__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (core_req_pop_valid & core_req_write & ~core_req_nposted & select_dummy); + endproperty +// Cover 1 : "(core_req_pop_valid & core_req_write & ~core_req_nposted & select_dummy)" + FUNCPOINT_csb_master__posted_write_dummy_client__1_COV : cover property (csb_master__posted_write_dummy_client__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property csb_master__non_posted_dummy_client__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (core_req_pop_valid & core_req_write & core_req_nposted & select_dummy); + endproperty +// Cover 2 : "(core_req_pop_valid & core_req_write & core_req_nposted & select_dummy)" + FUNCPOINT_csb_master__non_posted_dummy_client__2_COV : cover property (csb_master__non_posted_dummy_client__2_cov); + `endif +`endif +//VCS coverage on +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dummy_resp_valid_w))); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! core response fifo block!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (core_resp_pvld & ~core_resp_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_zero_one_hot #(0,19,0,"Error! Multiple response!") zzz_assert_zero_one_hot_3x (nvdla_core_clk, `ASSERT_RESET, {cfgrom2csb_resp_valid, + glb2csb_resp_valid, + mcif2csb_resp_valid, + bdma2csb_resp_valid, + cdma2csb_resp_valid, + csc2csb_resp_valid, + cmac_a2csb_resp_valid, + cmac_b2csb_resp_valid, + cacc2csb_resp_valid, + sdp_rdma2csb_resp_valid, + sdp2csb_resp_valid, + pdp_rdma2csb_resp_valid, + pdp2csb_resp_valid, + cdp_rdma2csb_resp_valid, + cdp2csb_resp_valid, + rbk2csb_resp_valid, + dummy_resp_valid}); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_csb_master diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v new file mode 100644 index 0000000..9ee30a7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v @@ -0,0 +1,535 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_SG_dat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSC_SG_dat_fifo ( + clk + , reset_ + , wr_ready + , wr_empty + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +output wr_empty; +input wr_req; +input [32:0] wr_data; +input rd_ready; +output rd_req; +output [32:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +reg wr_empty; // empty? +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 3'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_empty <= 1'b1; + end else begin + wr_empty <= wr_count_next == 3'd0 && !wr_req ; + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [1:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [1:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing && (wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [32:0] rd_data; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 ram ( + .clk( clk ) + , .clk_mgated( clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( (wr_count == 0) ? 3'd4 : {1'b0,rd_adr} ) + , .dout ( rd_data ) + ); +wire [1:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire rd_req; // data out of fifo is valid +assign rd_popping = rd_req && rd_ready; +reg [2:0] rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? rd_count : + (rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (rd_count + 1'd1) : + rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign rd_req = rd_count != 0 || rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req && rd_ready)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_dat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_dat_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSC_SG_dat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSC_SG_dat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSC_SG_dat_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CSC_SG_dat_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [32:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [32:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [32:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [32:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [32:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [32:0] ram_ff0; +reg [32:0] ram_ff1; +reg [32:0] ram_ff2; +reg [32:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [32:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {33{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [32:0] Di0; +input [1:0] Ra0; +output [32:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 33'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [32:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [32:0] Q0 = mem[0]; +wire [32:0] Q1 = mem[1]; +wire [32:0] Q2 = mem[2]; +wire [32:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33] } +endmodule // vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +//vmw: Memory vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +//vmw: Address-size 2 +//vmw: Data-size 33 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[32:0] data0[32:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[32:0] data1[32:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v.vcp new file mode 100644 index 0000000..9ee30a7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v.vcp @@ -0,0 +1,535 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_SG_dat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSC_SG_dat_fifo ( + clk + , reset_ + , wr_ready + , wr_empty + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +output wr_empty; +input wr_req; +input [32:0] wr_data; +input rd_ready; +output rd_req; +output [32:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +reg wr_empty; // empty? +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 3'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_empty <= 1'b1; + end else begin + wr_empty <= wr_count_next == 3'd0 && !wr_req ; + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [1:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [1:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing && (wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [32:0] rd_data; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 ram ( + .clk( clk ) + , .clk_mgated( clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( (wr_count == 0) ? 3'd4 : {1'b0,rd_adr} ) + , .dout ( rd_data ) + ); +wire [1:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire rd_req; // data out of fifo is valid +assign rd_popping = rd_req && rd_ready; +reg [2:0] rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? rd_count : + (rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (rd_count + 1'd1) : + rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign rd_req = rd_count != 0 || rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req && rd_ready)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_dat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_dat_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSC_SG_dat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSC_SG_dat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSC_SG_dat_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CSC_SG_dat_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [32:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [32:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [32:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [32:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [32:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [32:0] ram_ff0; +reg [32:0] ram_ff1; +reg [32:0] ram_ff2; +reg [32:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [32:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {33{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [32:0] Di0; +input [1:0] Ra0; +output [32:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 33'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [32:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [32:0] Q0 = mem[0]; +wire [32:0] Q1 = mem[1]; +wire [32:0] Q2 = mem[2]; +wire [32:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33] } +endmodule // vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +//vmw: Memory vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +//vmw: Address-size 2 +//vmw: Data-size 33 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[32:0] data0[32:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[32:0] data1[32:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v new file mode 100644 index 0000000..a81f295 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v @@ -0,0 +1,535 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_SG_wt_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSC_SG_wt_fifo ( + clk + , reset_ + , wr_ready + , wr_empty + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +output wr_empty; +input wr_req; +input [19:0] wr_data; +input rd_ready; +output rd_req; +output [19:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +reg wr_empty; // empty? +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 3'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_empty <= 1'b1; + end else begin + wr_empty <= wr_count_next == 3'd0 && !wr_req ; + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [1:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [1:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing && (wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [19:0] rd_data; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 ram ( + .clk( clk ) + , .clk_mgated( clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( (wr_count == 0) ? 3'd4 : {1'b0,rd_adr} ) + , .dout ( rd_data ) + ); +wire [1:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire rd_req; // data out of fifo is valid +assign rd_popping = rd_req && rd_ready; +reg [2:0] rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? rd_count : + (rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (rd_count + 1'd1) : + rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign rd_req = rd_count != 0 || rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req && rd_ready)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_wt_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_wt_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSC_SG_wt_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSC_SG_wt_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSC_SG_wt_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CSC_SG_wt_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [19:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [19:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [19:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [19:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [19:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [19:0] ram_ff0; +reg [19:0] ram_ff1; +reg [19:0] ram_ff2; +reg [19:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [19:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {20{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [19:0] Di0; +input [1:0] Ra0; +output [19:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 20'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [19:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [19:0] Q0 = mem[0]; +wire [19:0] Q1 = mem[1]; +wire [19:0] Q2 = mem[2]; +wire [19:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20] } +endmodule // vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +//vmw: Memory vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +//vmw: Address-size 2 +//vmw: Data-size 20 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[19:0] data0[19:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[19:0] data1[19:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v.vcp new file mode 100644 index 0000000..a81f295 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v.vcp @@ -0,0 +1,535 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_SG_wt_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_CSC_SG_wt_fifo ( + clk + , reset_ + , wr_ready + , wr_empty + , wr_req + , wr_data + , rd_ready + , rd_req + , rd_data + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input clk; +input reset_; +output wr_ready; +output wr_empty; +input wr_req; +input [19:0] wr_data; +input rd_ready; +output rd_req; +output [19:0] rd_data; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire clk_mgated_enable; // assigned by code at end of this module +wire clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power clk_mgate( .clk(clk), .reset_(reset_), .clk_en(clk_mgated_enable), .clk_gated(clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg wr_req_in; // registered wr_req +reg wr_busy_in; // inputs being held this cycle? +assign wr_ready = !wr_busy_in; +wire wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant wr_req signal +wire wr_busy_in_next_wr_req_eq_1 = wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (wr_req_in && wr_busy_next) && !wr_reserving; +wire wr_busy_in_next = (wr_req? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_req_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + wr_req_in <= wr_req && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + wr_req_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg wr_busy_int; // copy for internal use +assign wr_reserving = wr_req_in && !wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? wr_count : (wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (wr_count + 1'd1) : wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = wr_req_in && wr_busy_int; +reg wr_empty; // empty? +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_busy_int <= 1'b0; + wr_count <= 3'd0; + end else begin + wr_busy_int <= wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +always @( posedge clk or negedge reset_ ) begin + if ( !reset_ ) begin + wr_empty <= 1'b1; + end else begin + wr_empty <= wr_count_next == 3'd0 && !wr_req ; + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as wr_req_in +// +// RAM +// +reg [1:0] wr_adr; // current write address +// spyglass disable_block W484 +// next wr_adr if wr_pushing=1 +wire [1:0] wr_adr_next = wr_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + wr_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] rd_adr; // read address this cycle +wire ram_we = wr_pushing && (wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && wr_req; +wire [19:0] rd_data; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 ram ( + .clk( clk ) + , .clk_mgated( clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( wr_data ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( wr_adr ) + , .ra ( (wr_count == 0) ? 3'd4 : {1'b0,rd_adr} ) + , .dout ( rd_data ) + ); +wire [1:0] rd_adr_next_popping = rd_adr + 1'd1; // spyglass disable W484 +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire rd_req; // data out of fifo is valid +assign rd_popping = rd_req && rd_ready; +reg [2:0] rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? rd_count : + (rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (rd_count + 1'd1) : + rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign rd_req = rd_count != 0 || rd_pushing; +always @( posedge clk_mgated or negedge reset_ ) begin + if ( !reset_ ) begin + rd_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (wr_req_in && !wr_busy_int) || (wr_busy_int != wr_busy_next)) || (rd_pushing || rd_popping || (rd_req && rd_ready)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_wt_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_CSC_SG_wt_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_CSC_SG_wt_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_CSC_SG_wt_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_CSC_SG_wt_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_CSC_SG_wt_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [19:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [19:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [19:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [19:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [19:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [19:0] ram_ff0; +reg [19:0] ram_ff1; +reg [19:0] ram_ff2; +reg [19:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [19:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {20{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [19:0] Di0; +input [1:0] Ra0; +output [19:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 20'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [19:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [19:0] Q0 = mem[0]; +wire [19:0] Q1 = mem[1]; +wire [19:0] Q2 = mem[2]; +wire [19:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20] } +endmodule // vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +//vmw: Memory vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +//vmw: Address-size 2 +//vmw: Data-size 20 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[19:0] data0[19:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[19:0] data1[19:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v new file mode 100644 index 0000000..2519be8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v @@ -0,0 +1,857 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_WL_dec.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_CSC_WL_dec ( + nvdla_core_clk + ,nvdla_core_rstn + ,input_data + ,input_mask + ,input_mask_en + ,input_pipe_valid + ,input_sel + ,is_fp16 + ,is_int8 +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( ,output_data${i}\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,output_data0 + ,output_data1 + ,output_data2 + ,output_data3 + ,output_data4 + ,output_data5 + ,output_data6 + ,output_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,output_mask + ,output_pvld + ,output_sel + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [8*8 -1:0] input_data; +input [8 -1:0] input_mask; +input [9:0] input_mask_en; +input input_pipe_valid; +input [8 -1:0] input_sel; +input is_fp16; +input is_int8; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(output [8 -1:0] output_data${i};\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8 -1:0] output_data0; +output [8 -1:0] output_data1; +output [8 -1:0] output_data2; +output [8 -1:0] output_data3; +output [8 -1:0] output_data4; +output [8 -1:0] output_data5; +output [8 -1:0] output_data6; +output [8 -1:0] output_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8 -1:0] output_mask; +output output_pvld; +output [8 -1:0] output_sel; +wire [8 -1:0] input_mask_gated; +reg [8*8 -1:0] data_d1; +reg [8 -1:0] mask_d1; +//reg [8 -1:0] mask_d2_fp16_w; +//reg [8 -1:0] mask_d2_int16_w; +wire [8 -1:0] mask_d2_int8_w; +wire [8 -1:0] mask_d2_w; +reg [8 -1:0] mask_d3; +reg [8 -1:0] sel_d1; +reg [8 -1:0] sel_d2; +reg [8 -1:0] sel_d3; +reg valid_d1; +reg valid_d2; +reg valid_d3; +//: my $kk=8; +//: for(my $i = 0; $i < 8; $i ++) { +//: my $series_no = sprintf("%02d", $i); +//: print qq(reg [8 -1:0] vec_data_${series_no};\n); +//: print qq(reg [8 -1:0] vec_data_${series_no}_d2;\n); +//: print qq(reg [8 -1:0] vec_data_${series_no}_d3;\n); +//: } +//: for(my $i = 0; $i < 8; $i ++) { +//: my $j = 1; +//: while(2**$j <= ($i + 1)) { +//: $j ++; +//: } +//: my $k = $j - 1; +//: my $series_no = sprintf("%02d", $i); +//: print qq(wire [${k}:0] vec_sum_${series_no};\n); +//: print qq(reg [${k}:0] vec_sum_${series_no}_d1;\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [8 -1:0] vec_data_00; +reg [8 -1:0] vec_data_00_d2; +reg [8 -1:0] vec_data_00_d3; +reg [8 -1:0] vec_data_01; +reg [8 -1:0] vec_data_01_d2; +reg [8 -1:0] vec_data_01_d3; +reg [8 -1:0] vec_data_02; +reg [8 -1:0] vec_data_02_d2; +reg [8 -1:0] vec_data_02_d3; +reg [8 -1:0] vec_data_03; +reg [8 -1:0] vec_data_03_d2; +reg [8 -1:0] vec_data_03_d3; +reg [8 -1:0] vec_data_04; +reg [8 -1:0] vec_data_04_d2; +reg [8 -1:0] vec_data_04_d3; +reg [8 -1:0] vec_data_05; +reg [8 -1:0] vec_data_05_d2; +reg [8 -1:0] vec_data_05_d3; +reg [8 -1:0] vec_data_06; +reg [8 -1:0] vec_data_06_d2; +reg [8 -1:0] vec_data_06_d3; +reg [8 -1:0] vec_data_07; +reg [8 -1:0] vec_data_07_d2; +reg [8 -1:0] vec_data_07_d3; +wire [0:0] vec_sum_00; +reg [0:0] vec_sum_00_d1; +wire [1:0] vec_sum_01; +reg [1:0] vec_sum_01_d1; +wire [1:0] vec_sum_02; +reg [1:0] vec_sum_02_d1; +wire [2:0] vec_sum_03; +reg [2:0] vec_sum_03_d1; +wire [2:0] vec_sum_04; +reg [2:0] vec_sum_04_d1; +wire [2:0] vec_sum_05; +reg [2:0] vec_sum_05_d1; +wire [2:0] vec_sum_06; +reg [2:0] vec_sum_06_d1; +wire [3:0] vec_sum_07; +reg [3:0] vec_sum_07_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +///////////////////////////////////////////////////////////////////////////////////////////// +// Decoder of compressed weight +// +// data_mask input_data mac_sel +// | | | +// sums_for_sel register register +// | | | +// ------------------> mux register +// | | +// output_data output_sel +// +///////////////////////////////////////////////////////////////////////////////////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $series_no; +//: my $series_no_1; +//: my $name; +//: my $name_1; +//: my $width; +//: my $st; +//: my $end; +//: my @bit_width_list; +//: $width = 8; +//: for($i = 0; $i < 8; $i ++) { +//: $j = 0; +//: while(2**$j <= ($i + 1)) { +//: $j ++; +//: } +//: $bit_width_list[$i] = $j; +//: } +//: print "////////////////////////////////// phase I: calculate sums for mux //////////////////////////////////\n"; +//: print "assign input_mask_gated = ~input_mask_en[8] ? {${width}{1'b0}} : input_mask;\n\n"; +//: +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: print "assign vec_sum_${series_no} = "; +//: for($j = 0; $j < $i + 1; $j ++) { +//: print "input_mask_gated[${j}]"; +//: if($j == $i) { +//: print ";\n"; +//: } elsif ($j % 8 == 7) { +//: print "\n + "; +//: } else { +//: print " + "; +//: } +//: } +//: print "\n\n"; +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase I: registers //////////////////////////////////\n"; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -q valid_d1 -d input_pipe_valid "); +//: &eperl::flop("-nodeclare -norst -q data_d1 -en input_pipe_valid -d input_data "); +//: &eperl::flop("-nodeclare -norst -q mask_d1 -en input_pipe_valid -d input_mask "); +//: &eperl::flop("-nodeclare -q sel_d1 -en input_pipe_valid -d input_sel "); +//: +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: my $j = int($i / 8); +//: my $wid = $bit_width_list[$i]; +//: &eperl::flop("-nodeclare -rval \"{${wid}{1'b0}}\" -q vec_sum_${series_no}_d1 -en \"(input_pipe_valid & input_mask_en[${j}])\" -d vec_sum_${series_no} "); +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase II: mux //////////////////////////////////\n"; +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: $k = $bit_width_list[$i]; +//: +//: print "always @ (*) begin\n"; +//: print " case(vec_sum_${series_no}_d1)\n"; +//: +//: for($j = 1; $j <= $i + 1; $j ++) { +//: $st = $j * $width - 1; +//: $end = ($j - 1) * $width; +//: print " ${k}'d${j}: $name = data_d1[${st}:${end}];\n"; +//: } +//: print " default: $name= ${width}'b0;\n"; +//: print " endcase\n"; +//: print "end\n\n"; +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase II: registers //////////////////////////////////\n"; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -q valid_d2 -d valid_d1 "); +//: &eperl::flop("-nodeclare -q sel_d2 -en valid_d1 -d sel_d1 "); +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: &eperl::flop("-nodeclare -norst -q ${name}_d2 -en \"valid_d1\" -d \"(${name} & {${width}{mask_d1[${i}]}})\" "); +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase III: registers //////////////////////////////////\n"; +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}_d2"; +//: print "assign mask_d2_int8_w[${i}] = (|${name});\n"; +//: } +//: print "\n\n\n"; +//: +//: #for($i = 0; $i < 8; $i += 2) { +//: # $j = $i + 1; +//: # $series_no = sprintf("%02d", $i); +//: # $series_no_1 = sprintf("%02d", $j); +//: # $name = "vec_data_${series_no}_d2"; +//: # $name_1 = "vec_data_${series_no_1}_d2"; +//: # print "assign mask_d2_int16_w[${j}:${i}] = {2{(|{${name_1}, ${name}})}};\n"; +//: #} +//: #print "\n\n\n"; +//: +//: #for($i = 0; $i < 8; $i += 2) { +//: # $j = $i + 1; +//: # $series_no = sprintf("%02d", $i); +//: # $series_no_1 = sprintf("%02d", $j); +//: # $name = "vec_data_${series_no}_d2"; +//: # $name_1 = "vec_data_${series_no_1}_d2"; +//: # print "assign mask_d2_fp16_w[${j}:${i}] = {2{(|{${name_1}[6:0], ${name}})}};\n"; +//: #} +//: #print "\n\n\n"; +//: +//: #print "assign mask_d2_w = is_int8 ? mask_d2_int8_w :\n"; +//: #print " is_fp16 ? mask_d2_fp16_w :\n"; +//: #print " mask_d2_int16_w;\n"; +//: #print "\n\n\n"; +//: print "assign mask_d2_w = mask_d2_int8_w ;\n"; #only for int8 +//: +//: &eperl::flop("-nodeclare -rval \"1'b0\" -q valid_d3 -d valid_d2 "); +//: &eperl::flop("-nodeclare -norst -q mask_d3 -en valid_d2 -d mask_d2_w "); +//: &eperl::flop("-nodeclare -q sel_d3 -en valid_d2 -d sel_d2 "); +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: &eperl::flop("-nodeclare -q ${name}_d3 -en valid_d2 -d ${name}_d2 "); +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// output: rename //////////////////////////////////\n"; +//: print "assign output_pvld = valid_d3;\n"; +//: print "assign output_mask = mask_d3;\n"; +//: print "assign output_sel = sel_d3;\n"; +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: print "assign output_data${i} = ${name}_d3;\n"; +//: } +//: print "\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +////////////////////////////////// phase I: calculate sums for mux ////////////////////////////////// +assign input_mask_gated = ~input_mask_en[8] ? {8{1'b0}} : input_mask; + +assign vec_sum_00 = input_mask_gated[0]; + + +assign vec_sum_01 = input_mask_gated[0] + input_mask_gated[1]; + + +assign vec_sum_02 = input_mask_gated[0] + input_mask_gated[1] + input_mask_gated[2]; + + +assign vec_sum_03 = input_mask_gated[0] + input_mask_gated[1] + input_mask_gated[2] + input_mask_gated[3]; + + +assign vec_sum_04 = input_mask_gated[0] + input_mask_gated[1] + input_mask_gated[2] + input_mask_gated[3] + input_mask_gated[4]; + + +assign vec_sum_05 = input_mask_gated[0] + input_mask_gated[1] + input_mask_gated[2] + input_mask_gated[3] + input_mask_gated[4] + input_mask_gated[5]; + + +assign vec_sum_06 = input_mask_gated[0] + input_mask_gated[1] + input_mask_gated[2] + input_mask_gated[3] + input_mask_gated[4] + input_mask_gated[5] + input_mask_gated[6]; + + +assign vec_sum_07 = input_mask_gated[0] + input_mask_gated[1] + input_mask_gated[2] + input_mask_gated[3] + input_mask_gated[4] + input_mask_gated[5] + input_mask_gated[6] + input_mask_gated[7]; + + + + +////////////////////////////////// phase I: registers ////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + valid_d1 <= 1'b0; + end else begin + valid_d1 <= input_pipe_valid; + end +end +always @(posedge nvdla_core_clk) begin + if ((input_pipe_valid) == 1'b1) begin + data_d1 <= input_data; + // VCS coverage off + end else if ((input_pipe_valid) == 1'b0) begin + end else begin + data_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((input_pipe_valid) == 1'b1) begin + mask_d1 <= input_mask; + // VCS coverage off + end else if ((input_pipe_valid) == 1'b0) begin + end else begin + mask_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sel_d1 <= 'b0; + end else begin + if ((input_pipe_valid) == 1'b1) begin + sel_d1 <= input_sel; + // VCS coverage off + end else if ((input_pipe_valid) == 1'b0) begin + end else begin + sel_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_00_d1 <= {1{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_00_d1 <= vec_sum_00; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_00_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_01_d1 <= {2{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_01_d1 <= vec_sum_01; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_01_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_02_d1 <= {2{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_02_d1 <= vec_sum_02; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_02_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_03_d1 <= {3{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_03_d1 <= vec_sum_03; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_03_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_04_d1 <= {3{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_04_d1 <= vec_sum_04; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_04_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_05_d1 <= {3{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_05_d1 <= vec_sum_05; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_05_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_06_d1 <= {3{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_06_d1 <= vec_sum_06; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_06_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_sum_07_d1 <= {4{1'b0}}; + end else begin + if (((input_pipe_valid & input_mask_en[0])) == 1'b1) begin + vec_sum_07_d1 <= vec_sum_07; + // VCS coverage off + end else if (((input_pipe_valid & input_mask_en[0])) == 1'b0) begin + end else begin + vec_sum_07_d1 <= 'bx; + // VCS coverage on + end + end +end + + +////////////////////////////////// phase II: mux ////////////////////////////////// +always @ (*) begin + case(vec_sum_00_d1) + 1'd1: vec_data_00 = data_d1[7:0]; + default: vec_data_00= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_01_d1) + 2'd1: vec_data_01 = data_d1[7:0]; + 2'd2: vec_data_01 = data_d1[15:8]; + default: vec_data_01= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_02_d1) + 2'd1: vec_data_02 = data_d1[7:0]; + 2'd2: vec_data_02 = data_d1[15:8]; + 2'd3: vec_data_02 = data_d1[23:16]; + default: vec_data_02= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_03_d1) + 3'd1: vec_data_03 = data_d1[7:0]; + 3'd2: vec_data_03 = data_d1[15:8]; + 3'd3: vec_data_03 = data_d1[23:16]; + 3'd4: vec_data_03 = data_d1[31:24]; + default: vec_data_03= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_04_d1) + 3'd1: vec_data_04 = data_d1[7:0]; + 3'd2: vec_data_04 = data_d1[15:8]; + 3'd3: vec_data_04 = data_d1[23:16]; + 3'd4: vec_data_04 = data_d1[31:24]; + 3'd5: vec_data_04 = data_d1[39:32]; + default: vec_data_04= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_05_d1) + 3'd1: vec_data_05 = data_d1[7:0]; + 3'd2: vec_data_05 = data_d1[15:8]; + 3'd3: vec_data_05 = data_d1[23:16]; + 3'd4: vec_data_05 = data_d1[31:24]; + 3'd5: vec_data_05 = data_d1[39:32]; + 3'd6: vec_data_05 = data_d1[47:40]; + default: vec_data_05= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_06_d1) + 3'd1: vec_data_06 = data_d1[7:0]; + 3'd2: vec_data_06 = data_d1[15:8]; + 3'd3: vec_data_06 = data_d1[23:16]; + 3'd4: vec_data_06 = data_d1[31:24]; + 3'd5: vec_data_06 = data_d1[39:32]; + 3'd6: vec_data_06 = data_d1[47:40]; + 3'd7: vec_data_06 = data_d1[55:48]; + default: vec_data_06= 8'b0; + endcase +end + +always @ (*) begin + case(vec_sum_07_d1) + 4'd1: vec_data_07 = data_d1[7:0]; + 4'd2: vec_data_07 = data_d1[15:8]; + 4'd3: vec_data_07 = data_d1[23:16]; + 4'd4: vec_data_07 = data_d1[31:24]; + 4'd5: vec_data_07 = data_d1[39:32]; + 4'd6: vec_data_07 = data_d1[47:40]; + 4'd7: vec_data_07 = data_d1[55:48]; + 4'd8: vec_data_07 = data_d1[63:56]; + default: vec_data_07= 8'b0; + endcase +end + + + +////////////////////////////////// phase II: registers ////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + valid_d2 <= 1'b0; + end else begin + valid_d2 <= valid_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sel_d2 <= 'b0; + end else begin + if ((valid_d1) == 1'b1) begin + sel_d2 <= sel_d1; + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + sel_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_00_d2 <= (vec_data_00 & {8{mask_d1[0]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_00_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_01_d2 <= (vec_data_01 & {8{mask_d1[1]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_01_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_02_d2 <= (vec_data_02 & {8{mask_d1[2]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_02_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_03_d2 <= (vec_data_03 & {8{mask_d1[3]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_03_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_04_d2 <= (vec_data_04 & {8{mask_d1[4]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_04_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_05_d2 <= (vec_data_05 & {8{mask_d1[5]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_05_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_06_d2 <= (vec_data_06 & {8{mask_d1[6]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_06_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d1) == 1'b1) begin + vec_data_07_d2 <= (vec_data_07 & {8{mask_d1[7]}}); + // VCS coverage off + end else if ((valid_d1) == 1'b0) begin + end else begin + vec_data_07_d2 <= 'bx; + // VCS coverage on + end +end + + +////////////////////////////////// phase III: registers ////////////////////////////////// +assign mask_d2_int8_w[0] = (|vec_data_00_d2); +assign mask_d2_int8_w[1] = (|vec_data_01_d2); +assign mask_d2_int8_w[2] = (|vec_data_02_d2); +assign mask_d2_int8_w[3] = (|vec_data_03_d2); +assign mask_d2_int8_w[4] = (|vec_data_04_d2); +assign mask_d2_int8_w[5] = (|vec_data_05_d2); +assign mask_d2_int8_w[6] = (|vec_data_06_d2); +assign mask_d2_int8_w[7] = (|vec_data_07_d2); + + + +assign mask_d2_w = mask_d2_int8_w ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + valid_d3 <= 1'b0; + end else begin + valid_d3 <= valid_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((valid_d2) == 1'b1) begin + mask_d3 <= mask_d2_w; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + mask_d3 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sel_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + sel_d3 <= sel_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + sel_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_00_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_00_d3 <= vec_data_00_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_00_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_01_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_01_d3 <= vec_data_01_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_01_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_02_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_02_d3 <= vec_data_02_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_02_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_03_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_03_d3 <= vec_data_03_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_03_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_04_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_04_d3 <= vec_data_04_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_04_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_05_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_05_d3 <= vec_data_05_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_05_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_06_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_06_d3 <= vec_data_06_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_06_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + vec_data_07_d3 <= 'b0; + end else begin + if ((valid_d2) == 1'b1) begin + vec_data_07_d3 <= vec_data_07_d2; + // VCS coverage off + end else if ((valid_d2) == 1'b0) begin + end else begin + vec_data_07_d3 <= 'bx; + // VCS coverage on + end + end +end + + +////////////////////////////////// output: rename ////////////////////////////////// +assign output_pvld = valid_d3; +assign output_mask = mask_d3; +assign output_sel = sel_d3; +assign output_data0 = vec_data_00_d3; +assign output_data1 = vec_data_01_d3; +assign output_data2 = vec_data_02_d3; +assign output_data3 = vec_data_03_d3; +assign output_data4 = vec_data_04_d3; +assign output_data5 = vec_data_05_d3; +assign output_data6 = vec_data_06_d3; +assign output_data7 = vec_data_07_d3; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_CSC_WL_dec diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v.vcp new file mode 100644 index 0000000..f9b0e2e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v.vcp @@ -0,0 +1,241 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_WL_dec.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_CSC_WL_dec ( + nvdla_core_clk + ,nvdla_core_rstn + ,input_data + ,input_mask + ,input_mask_en + ,input_pipe_valid + ,input_sel + ,is_fp16 + ,is_int8 +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( ,output_data${i}\n); +//: } + ,output_mask + ,output_pvld + ,output_sel + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [8*8 -1:0] input_data; +input [8 -1:0] input_mask; +input [9:0] input_mask_en; +input input_pipe_valid; +input [8 -1:0] input_sel; +input is_fp16; +input is_int8; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(output [8 -1:0] output_data${i};\n); +//: } +output [8 -1:0] output_mask; +output output_pvld; +output [8 -1:0] output_sel; +wire [8 -1:0] input_mask_gated; +reg [8*8 -1:0] data_d1; +reg [8 -1:0] mask_d1; +//reg [8 -1:0] mask_d2_fp16_w; +//reg [8 -1:0] mask_d2_int16_w; +wire [8 -1:0] mask_d2_int8_w; +wire [8 -1:0] mask_d2_w; +reg [8 -1:0] mask_d3; +reg [8 -1:0] sel_d1; +reg [8 -1:0] sel_d2; +reg [8 -1:0] sel_d3; +reg valid_d1; +reg valid_d2; +reg valid_d3; +//: my $kk=8; +//: for(my $i = 0; $i < 8; $i ++) { +//: my $series_no = sprintf("%02d", $i); +//: print qq(reg [8 -1:0] vec_data_${series_no};\n); +//: print qq(reg [8 -1:0] vec_data_${series_no}_d2;\n); +//: print qq(reg [8 -1:0] vec_data_${series_no}_d3;\n); +//: } +//: for(my $i = 0; $i < 8; $i ++) { +//: my $j = 1; +//: while(2**$j <= ($i + 1)) { +//: $j ++; +//: } +//: my $k = $j - 1; +//: my $series_no = sprintf("%02d", $i); +//: print qq(wire [${k}:0] vec_sum_${series_no};\n); +//: print qq(reg [${k}:0] vec_sum_${series_no}_d1;\n); +//: } +///////////////////////////////////////////////////////////////////////////////////////////// +// Decoder of compressed weight +// +// data_mask input_data mac_sel +// | | | +// sums_for_sel register register +// | | | +// ------------------> mux register +// | | +// output_data output_sel +// +///////////////////////////////////////////////////////////////////////////////////////////// +//: my $i; +//: my $j; +//: my $k; +//: my $series_no; +//: my $series_no_1; +//: my $name; +//: my $name_1; +//: my $width; +//: my $st; +//: my $end; +//: my @bit_width_list; +//: $width = 8; +//: for($i = 0; $i < 8; $i ++) { +//: $j = 0; +//: while(2**$j <= ($i + 1)) { +//: $j ++; +//: } +//: $bit_width_list[$i] = $j; +//: } +//: print "////////////////////////////////// phase I: calculate sums for mux //////////////////////////////////\n"; +//: print "assign input_mask_gated = ~input_mask_en[8] ? {${width}{1'b0}} : input_mask;\n\n"; +//: +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: print "assign vec_sum_${series_no} = "; +//: for($j = 0; $j < $i + 1; $j ++) { +//: print "input_mask_gated[${j}]"; +//: if($j == $i) { +//: print ";\n"; +//: } elsif ($j % 8 == 7) { +//: print "\n + "; +//: } else { +//: print " + "; +//: } +//: } +//: print "\n\n"; +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase I: registers //////////////////////////////////\n"; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -q valid_d1 -d input_pipe_valid "); +//: &eperl::flop("-nodeclare -norst -q data_d1 -en input_pipe_valid -d input_data "); +//: &eperl::flop("-nodeclare -norst -q mask_d1 -en input_pipe_valid -d input_mask "); +//: &eperl::flop("-nodeclare -q sel_d1 -en input_pipe_valid -d input_sel "); +//: +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: my $j = int($i / 8); +//: my $wid = $bit_width_list[$i]; +//: &eperl::flop("-nodeclare -rval \"{${wid}{1'b0}}\" -q vec_sum_${series_no}_d1 -en \"(input_pipe_valid & input_mask_en[${j}])\" -d vec_sum_${series_no} "); +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase II: mux //////////////////////////////////\n"; +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: $k = $bit_width_list[$i]; +//: +//: print "always @ (*) begin\n"; +//: print " case(vec_sum_${series_no}_d1)\n"; +//: +//: for($j = 1; $j <= $i + 1; $j ++) { +//: $st = $j * $width - 1; +//: $end = ($j - 1) * $width; +//: print " ${k}'d${j}: $name = data_d1[${st}:${end}];\n"; +//: } +//: print " default: $name= ${width}'b0;\n"; +//: print " endcase\n"; +//: print "end\n\n"; +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase II: registers //////////////////////////////////\n"; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -q valid_d2 -d valid_d1 "); +//: &eperl::flop("-nodeclare -q sel_d2 -en valid_d1 -d sel_d1 "); +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: &eperl::flop("-nodeclare -norst -q ${name}_d2 -en \"valid_d1\" -d \"(${name} & {${width}{mask_d1[${i}]}})\" "); +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// phase III: registers //////////////////////////////////\n"; +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}_d2"; +//: print "assign mask_d2_int8_w[${i}] = (|${name});\n"; +//: } +//: print "\n\n\n"; +//: +//: #for($i = 0; $i < 8; $i += 2) { +//: # $j = $i + 1; +//: # $series_no = sprintf("%02d", $i); +//: # $series_no_1 = sprintf("%02d", $j); +//: # $name = "vec_data_${series_no}_d2"; +//: # $name_1 = "vec_data_${series_no_1}_d2"; +//: # print "assign mask_d2_int16_w[${j}:${i}] = {2{(|{${name_1}, ${name}})}};\n"; +//: #} +//: #print "\n\n\n"; +//: +//: #for($i = 0; $i < 8; $i += 2) { +//: # $j = $i + 1; +//: # $series_no = sprintf("%02d", $i); +//: # $series_no_1 = sprintf("%02d", $j); +//: # $name = "vec_data_${series_no}_d2"; +//: # $name_1 = "vec_data_${series_no_1}_d2"; +//: # print "assign mask_d2_fp16_w[${j}:${i}] = {2{(|{${name_1}[6:0], ${name}})}};\n"; +//: #} +//: #print "\n\n\n"; +//: +//: #print "assign mask_d2_w = is_int8 ? mask_d2_int8_w :\n"; +//: #print " is_fp16 ? mask_d2_fp16_w :\n"; +//: #print " mask_d2_int16_w;\n"; +//: #print "\n\n\n"; +//: print "assign mask_d2_w = mask_d2_int8_w ;\n"; #only for int8 +//: +//: &eperl::flop("-nodeclare -rval \"1'b0\" -q valid_d3 -d valid_d2 "); +//: &eperl::flop("-nodeclare -norst -q mask_d3 -en valid_d2 -d mask_d2_w "); +//: &eperl::flop("-nodeclare -q sel_d3 -en valid_d2 -d sel_d2 "); +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: &eperl::flop("-nodeclare -q ${name}_d3 -en valid_d2 -d ${name}_d2 "); +//: } +//: print "\n\n"; +//: +//: print "////////////////////////////////// output: rename //////////////////////////////////\n"; +//: print "assign output_pvld = valid_d3;\n"; +//: print "assign output_mask = mask_d3;\n"; +//: print "assign output_sel = sel_d3;\n"; +//: for($i = 0; $i < 8; $i ++) { +//: $series_no = sprintf("%02d", $i); +//: $name = "vec_data_${series_no}"; +//: print "assign output_data${i} = ${name}_d3;\n"; +//: } +//: print "\n\n"; +endmodule // NV_NVDLA_CSC_WL_dec diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v new file mode 100644 index 0000000..25a5f62 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v @@ -0,0 +1,5330 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_dl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +module NV_NVDLA_CSC_dl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sg2dl_pvld //|< i + ,sg2dl_pd //|< i + ,sc_state //|< i + ,sg2dl_reuse_rls //|< i + ,sc2cdma_dat_pending_req //|< i + ,cdma2sc_dat_updt //|< i + ,cdma2sc_dat_entries //|< i + ,cdma2sc_dat_slices //|< i + ,sc2cdma_dat_updt //|> o + ,sc2cdma_dat_entries //|> o + ,sc2cdma_dat_slices //|> o + ,sc2buf_dat_rd_en //|> o + ,sc2buf_dat_rd_addr //|> o + ,sc2buf_dat_rd_valid //|< i + ,sc2buf_dat_rd_data //|< i + ,sc2buf_dat_rd_shift //|> o + ,sc2buf_dat_rd_next1_en //|> o + ,sc2buf_dat_rd_next1_addr //|> o + ,sc2mac_dat_a_pvld //|> o + ,sc2mac_dat_a_mask //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_a_data${i} //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_a_data0 //|> o +,sc2mac_dat_a_data1 //|> o +,sc2mac_dat_a_data2 //|> o +,sc2mac_dat_a_data3 //|> o +,sc2mac_dat_a_data4 //|> o +,sc2mac_dat_a_data5 //|> o +,sc2mac_dat_a_data6 //|> o +,sc2mac_dat_a_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_a_pd //|> o + ,sc2mac_dat_b_pvld //|> o + ,sc2mac_dat_b_mask //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_b_data${i} //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_b_data0 //|> o +,sc2mac_dat_b_data1 //|> o +,sc2mac_dat_b_data2 //|> o +,sc2mac_dat_b_data3 //|> o +,sc2mac_dat_b_data4 //|> o +,sc2mac_dat_b_data5 //|> o +,sc2mac_dat_b_data6 //|> o +,sc2mac_dat_b_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_b_pd //|> o + ,nvdla_core_ng_clk //|< i + ,nvdla_wg_clk //|< i + ,reg2dp_op_en //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_batches //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_skip_data_rls //|< i + ,reg2dp_datain_channel_ext //|< i + ,reg2dp_datain_height_ext //|< i + ,reg2dp_datain_width_ext //|< i + ,reg2dp_y_extension //|< i + ,reg2dp_weight_channel_ext //|< i + ,reg2dp_entries //|< i + ,reg2dp_dataout_width //|< i + ,reg2dp_rls_slices //|< i + ,reg2dp_conv_x_stride_ext //|< i + ,reg2dp_conv_y_stride_ext //|< i + ,reg2dp_x_dilation_ext //|< i + ,reg2dp_y_dilation_ext //|< i + ,reg2dp_pad_left //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_pra_truncate //|< i + ,slcg_wg_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input sg2dl_pvld; /* data valid */ +input [30:0] sg2dl_pd; +input [1:0] sc_state; +input sg2dl_reuse_rls; +input sc2cdma_dat_pending_req; +input cdma2sc_dat_updt; /* data valid */ +input [15 -1:0] cdma2sc_dat_entries; +input [13:0] cdma2sc_dat_slices; +output sc2cdma_dat_updt; /* data valid */ +output [15 -1:0] sc2cdma_dat_entries; +output [13:0] sc2cdma_dat_slices; +output sc2buf_dat_rd_en; /* data valid */ +output [14 -1:0] sc2buf_dat_rd_addr; +input sc2buf_dat_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_dat_rd_data; +output [7 -1:0] sc2buf_dat_rd_shift; +output sc2buf_dat_rd_next1_en; +output [14 -1:0] sc2buf_dat_rd_next1_addr; +output sc2mac_dat_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_a_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_a_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_dat_a_data0; +output [8 -1:0] sc2mac_dat_a_data1; +output [8 -1:0] sc2mac_dat_a_data2; +output [8 -1:0] sc2mac_dat_a_data3; +output [8 -1:0] sc2mac_dat_a_data4; +output [8 -1:0] sc2mac_dat_a_data5; +output [8 -1:0] sc2mac_dat_a_data6; +output [8 -1:0] sc2mac_dat_a_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] sc2mac_dat_a_pd; +output sc2mac_dat_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_b_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_b_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_dat_b_data0; +output [8 -1:0] sc2mac_dat_b_data1; +output [8 -1:0] sc2mac_dat_b_data2; +output [8 -1:0] sc2mac_dat_b_data3; +output [8 -1:0] sc2mac_dat_b_data4; +output [8 -1:0] sc2mac_dat_b_data5; +output [8 -1:0] sc2mac_dat_b_data6; +output [8 -1:0] sc2mac_dat_b_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] sc2mac_dat_b_pd; +input nvdla_core_ng_clk; +input nvdla_wg_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [4:0] reg2dp_batches; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_datain_format; +input [0:0] reg2dp_skip_data_rls; +input [12:0] reg2dp_datain_channel_ext; +input [12:0] reg2dp_datain_height_ext; +input [12:0] reg2dp_datain_width_ext; +input [1:0] reg2dp_y_extension; +input [12:0] reg2dp_weight_channel_ext; +input [13:0] reg2dp_entries; +input [12:0] reg2dp_dataout_width; +input [11:0] reg2dp_rls_slices; +input [2:0] reg2dp_conv_x_stride_ext; +input [2:0] reg2dp_conv_y_stride_ext; +input [4:0] reg2dp_x_dilation_ext; +input [4:0] reg2dp_y_dilation_ext; +input [4:0] reg2dp_pad_left; +input [4:0] reg2dp_pad_top; +input [15:0] reg2dp_pad_value; +input [4:0] reg2dp_data_bank; +input [1:0] reg2dp_pra_truncate; +output slcg_wg_en; +reg [4:0] batch_cmp; +reg [4:0] batch_cnt; +reg [14 -1:0] c_bias; +reg [14 -1:0] c_bias_d1; +reg [3:0] conv_x_stride; +reg [3:0] conv_y_stride; +reg [15 -1:0] dat_entry_avl; +reg [15 -1:0] dat_entry_end; +reg [15 -1:0] dat_entry_st; +reg dat_exec_valid_d1; +reg dat_exec_valid_d2; +reg dat_l0c0_dummy; +reg [64 -1:0] dat_l0c0; +reg dat_l0c1_dummy; +reg [64 -1:0] dat_l0c1; +reg dat_l1c0_dummy; +reg [64 -1:0] dat_l1c0; +reg dat_l1c1_dummy; +reg [64 -1:0] dat_l1c1; +reg dat_l2c0_dummy; +reg [64 -1:0] dat_l2c0; +reg dat_l2c1_dummy; +reg [64 -1:0] dat_l2c1; +reg dat_l3c0_dummy; +reg [64 -1:0] dat_l3c0; +reg dat_l3c1_dummy; +reg [64 -1:0] dat_l3c1; +reg [64 -1:0] dat_out_bypass_data; +reg [8 -1:0] dat_out_bypass_mask; +reg [8:0] dat_out_flag; +reg dat_out_pvld; +reg dat_pipe_local_valid; +reg dat_pipe_valid_d1; +reg dat_pipe_valid_d2; +reg [7:0] dat_req_bytes_d1; +reg [7:0] dat_req_bytes_d2; +reg dat_req_ch_end_d1; +reg dat_req_ch_end_d2; +reg [1:0] dat_req_cur_sub_h_d1; +reg [1:0] dat_req_cur_sub_h_d2; +reg dat_req_dummy_d1; +reg dat_req_dummy_d2; +reg [8:0] dat_req_flag_d1; +reg [8:0] dat_req_flag_d2; +reg dat_req_rls_d1; +reg dat_req_rls_d2; +reg dat_req_sub_c_d1; +reg dat_req_sub_c_d2; +reg [14 -1:0] dat_req_sub_h_0_addr; +reg [14 -1:0] dat_req_sub_h_1_addr; +reg [14 -1:0] dat_req_sub_h_2_addr; +reg [14 -1:0] dat_req_sub_h_3_addr; +reg [1:0] dat_req_sub_h_d1; +reg [1:0] dat_req_sub_h_d2; +reg [1:0] dat_req_sub_w_d1; +reg [1:0] dat_req_sub_w_d2; +reg dat_req_sub_w_st_d1; +reg dat_req_sub_w_st_d2; +reg dat_req_valid_d1; +wire [64 -1:0] dat_rsp_l0_sft; +reg [64 -1:0] dat_rsp_l0_sft_d1; +reg [64 -1:0] dat_rsp_l0_sft_d2; +reg [64 -1:0] dat_rsp_l0_sft_d3; +wire [64 -1:0] dat_rsp_l1_sft; +reg [64 -1:0] dat_rsp_l1_sft_d2; +reg [64 -1:0] dat_rsp_l1_sft_d3; +wire [64 -1:0] dat_rsp_l2_sft; +reg [64 -1:0] dat_rsp_l2_sft_d3; +wire [64 -1:0] dat_rsp_l3_sft; +reg [26:0] dat_rsp_pd_d1; +reg [26:0] dat_rsp_pd_d2; +reg [26:0] dat_rsp_pd_d3; +reg [26:0] dat_rsp_pd_d4; +reg [3:0] dat_rsp_pra_en_d1; +reg dat_rsp_pvld_d1; +reg dat_rsp_pvld_d2; +reg dat_rsp_pvld_d3; +reg dat_rsp_pvld_d4; +reg [255:0] dat_rsp_wg_ch0_d1; +reg [255:0] dat_rsp_wg_ch1_d1; +reg [255:0] dat_rsp_wg_ch2_d1; +reg [255:0] dat_rsp_wg_ch3_d1; +reg [13:0] dat_slice_avl; +reg [4:0] data_bank; +reg [5:0] data_batch; +reg [10:0] datain_c_cnt; +reg [10:0] datain_channel_cmp; +reg [13:0] datain_h_cnt; +reg [13:0] datain_h_ori; +reg [12:0] datain_height_cmp; +reg [13:0] datain_w_cnt; +reg [13:0] datain_w_ori; +reg [13:0] datain_width; +reg [12:0] datain_width_cmp; +reg [12:0] dataout_w_cnt; +reg [12:0] dataout_w_ori; +reg [12:0] dataout_width_cmp; +reg [8:0] dl_out_flag; +reg [8 -1:0] dl_out_mask; +reg dl_out_pvld; +reg dl_out_pvld_d1; +reg [30:0] dl_pd_d1; +reg [30:0] dl_pd_d2; +reg [30:0] dl_pd_d3; +reg [30:0] dl_pd_d4; +reg dl_pvld_d1; +reg dl_pvld_d2; +reg dl_pvld_d3; +reg dl_pvld_d4; +reg [15 -1:0] entries; +reg [15 -1:0] entries_batch; +reg [15 -1:0] entries_cmp; +reg [14 -1:0] h_bias_0_d1; +reg [14 -1:0] h_bias_0_stride; +reg [14 -1:0] h_bias_1_d1; +reg [14 -1:0] h_bias_1_stride; +reg [14 -1:0] h_bias_2_d1; +reg [14 -1:0] h_bias_2_stride; +reg [14 -1:0] h_bias_3_d1; +reg [14 -1:0] h_bias_3_stride; +reg [13:0] h_offset_slice; +reg [33:0] is_img_d1; +reg is_sg_running_d1; +reg [21:0] is_winograd_d1; +reg [15 -1:0] last_entries; +reg [13:0] last_slices; +reg layer_st_d1; +reg [15:0] pad_value; +reg [11:0] pixel_ch_stride; +reg pixel_force_clr_d1; +reg pixel_force_fetch_d1; +reg [15:0] pixel_w_ch_ori; +reg [15:0] pixel_w_cnt; +reg [15:0] pixel_w_ori; +reg [6:0] pixel_x_add; +reg [6:0] pixel_x_byte_stride; +reg [5:0] pixel_x_init; +reg [6:0] pixel_x_init_offset; +reg pixel_x_stride_odd; +reg [7:0] pra_precision; +reg [7:0] pra_truncate; +reg [15 -1:0] rls_entries; +reg [13:0] rls_slices; +reg [7:0] rsp_sft_cnt_l0; +reg [7:0] rsp_sft_cnt_l0_ori; +reg [7:0] rsp_sft_cnt_l1; +reg [7:0] rsp_sft_cnt_l1_ori; +reg [7:0] rsp_sft_cnt_l2; +reg [7:0] rsp_sft_cnt_l2_ori; +reg [7:0] rsp_sft_cnt_l3; +reg [7:0] rsp_sft_cnt_l3_ori; +reg [14 -1:0] sc2buf_dat_rd_addr; +reg [14 -1:0] sc2buf_dat_rd_next1_addr; +reg sc2buf_dat_rd_en; +reg [15 -1:0] sc2cdma_dat_entries; +reg [13:0] sc2cdma_dat_slices; +reg sc2cdma_dat_updt; +reg [8 -1:0] sc2mac_dat_a_mask; +reg [8:0] sc2mac_dat_a_pd; +reg sc2mac_dat_a_pvld; +reg [8 -1:0] sc2mac_dat_b_mask; +reg [8:0] sc2mac_dat_b_pd; +reg sc2mac_dat_b_pvld; +reg slcg_wg_en_d1; +reg slcg_wg_en_d2; +reg slcg_wg_en_d3; +reg [13:0] slice_left; +reg [6:0] stripe_cnt; +reg [2:0] sub_h_cmp_g0; +reg [2:0] sub_h_cmp_g1; +reg [1:0] sub_h_cnt; +reg [2:0] sub_h_total_g0; +reg [2:0] sub_h_total_g1; +reg [2:0] sub_h_total_g10; +reg [2:0] sub_h_total_g11; +reg [1:0] sub_h_total_g2; +reg [2:0] sub_h_total_g3; +reg [2:0] sub_h_total_g4; +reg [2:0] sub_h_total_g5; +reg [2:0] sub_h_total_g6; +reg [2:0] sub_h_total_g7; +reg [2:0] sub_h_total_g8; +reg [2:0] sub_h_total_g9; +reg [14 -1:0] w_bias_d1; +reg [5:0] x_dilate; +reg [5:0] y_dilate; +wire [4:0] batch_cmp_w; +wire [4:0] batch_cnt_w; +wire [14 -1:0] c_bias_add; +wire c_bias_d1_reg_en; +wire c_bias_reg_en; +wire [14 -1:0] c_bias_w; +wire cbuf_reset; +wire [3:0] conv_x_stride_w; +wire [3:0] conv_y_stride_w; +wire dat_conv_req_dummy; +wire dat_dummy_l0_en; +wire dat_dummy_l1_en; +wire dat_dummy_l2_en; +wire dat_dummy_l3_en; +wire [15 -1:0] dat_entry_avl_add; +wire [15 -1:0] dat_entry_avl_sub; +wire [15 -1:0] dat_entry_avl_w; +wire [15 -1:0] dat_entry_end_inc; +wire [15 -1:0] dat_entry_end_inc_wrap; +wire [15 -1:0] dat_entry_end_w; +wire [15 -1:0] dat_entry_st_inc; +wire [15 -1:0] dat_entry_st_inc_wrap; +wire [15 -1:0] dat_entry_st_w; +wire mon_dat_entry_end_inc; +wire mon_dat_entry_st_inc; +wire dat_exec_valid; +wire dat_img_req_dummy; +wire dat_img_req_skip; +wire dat_l0_set; +wire dat_l0c0_dummy_w; +wire dat_l0c0_en; +wire dat_l0c1_dummy_w; +wire dat_l0c1_en; +wire dat_l1_set; +wire dat_l1c0_dummy_w; +wire dat_l1c0_en; +wire dat_l1c0_hi_en; +wire dat_l1c1_dummy_w; +wire dat_l1c1_en; +wire dat_l1c1_hi_en; +wire dat_l2_set; +wire dat_l2c0_dummy_w; +wire dat_l2c0_en; +wire dat_l2c1_dummy_w; +wire dat_l2c1_en; +wire dat_l3_set; +wire dat_l3c0_dummy_w; +wire dat_l3c0_en; +wire dat_l3c1_dummy_w; +wire dat_l3c1_en; +wire [64 -1:0] dat_out_bypass_data_w; +wire [8 -1:0] dat_out_bypass_mask_w; +wire dat_out_bypass_p0_vld_w; +wire [64 -1:0] dat_out_data; +wire [8:0] dat_out_flag_l0; +wire [8:0] dat_out_flag_w; +wire [8 -1:0] dat_out_mask; +wire dat_out_pvld_l0; +wire dat_out_pvld_w; +wire [64 -1:0] dat_out_wg_8b; +wire [64 -1:0] dat_out_wg_data; +wire [8 -1:0] dat_out_wg_mask; +wire [8 -1:0] dat_out_wg_mask_int8; +wire dat_pipe_local_valid_w; +wire dat_pipe_valid; +wire [64 -1:0] dat_pra_dat; +wire [255:0] dat_pra_dat_ch0; +wire [255:0] dat_pra_dat_ch1; +wire [255:0] dat_pra_dat_ch2; +wire [255:0] dat_pra_dat_ch3; +wire [14 -1:0] dat_req_addr_last; +wire [14:0] dat_req_addr_sum; +wire [14 -1:0] dat_req_addr_w; +wire [14 -1:0] dat_req_addr_wrap; +wire [14 -1:0] dat_req_base_d1; +wire mon_dat_req_addr_sum; +wire [4:0] dat_req_batch_index; +wire [7:0] dat_req_bytes; +wire dat_req_channel_end; +wire dat_req_dummy; +wire dat_req_exec_dummy; +wire dat_req_exec_pvld; +wire [1:0] dat_req_exec_sub_h; +wire [8:0] dat_req_flag_w; +wire dat_req_layer_end; +wire [7:0] dat_req_pipe_bytes; +wire dat_req_pipe_ch_end; +wire [1:0] dat_req_pipe_cur_sub_h; +wire dat_req_pipe_dummy; +wire [8:0] dat_req_pipe_flag; +wire [28:0] dat_req_pipe_pd; +wire dat_req_pipe_pvld; +wire dat_req_pipe_rls; +wire dat_req_pipe_sub_c; +wire [1:0] dat_req_pipe_sub_h; +wire [1:0] dat_req_pipe_sub_w; +wire dat_req_pipe_sub_w_st; +wire dat_req_skip; +wire dat_req_stripe_end; +wire dat_req_stripe_st; +wire dat_req_sub_c_w; +wire dat_req_sub_h_0_addr_en; +wire dat_req_sub_h_1_addr_en; +wire dat_req_sub_h_2_addr_en; +wire dat_req_sub_h_3_addr_en; +wire dat_req_sub_w_st_en; +wire [1:0] dat_req_sub_w_w; +wire dat_req_valid; +wire dat_rls; +wire [4:0] dat_rsp_batch_index; +wire [7:0] dat_rsp_bytes; +wire dat_rsp_ch_end; +wire dat_rsp_channel_end; +wire [64 -1:0] dat_rsp_conv; +wire [64 -1:0] dat_rsp_conv_8b; +wire [8 -1:0] dat_rsp_cur_h_e2_mask_8b; +wire [8 -1:0] dat_rsp_cur_h_e4_mask_8b; +wire [8 -1:0] dat_rsp_cur_h_mask_p1; +wire [31:0] dat_rsp_cur_h_mask_p2; +wire [31:0] dat_rsp_cur_h_mask_p3; +wire [1:0] dat_rsp_cur_sub_h; +wire [64 -1:0] dat_rsp_data_w; +wire dat_rsp_exec_dummy; +wire dat_rsp_exec_dummy_d0; +wire dat_rsp_exec_pvld; +wire dat_rsp_exec_pvld_d0; +wire [1:0] dat_rsp_exec_sub_h; +wire [1:0] dat_rsp_exec_sub_h_d0; +wire [8:0] dat_rsp_flag; +wire [64 -1:0] dat_rsp_img; +wire [64 -1:0] dat_rsp_img_8b; +wire dat_rsp_l0_block_end; +wire [8:0] dat_rsp_l0_flag; +wire dat_rsp_l0_pvld; +wire [64*2 -1:0] dat_rsp_l0_sft_in; +wire dat_rsp_l0_stripe_end; +wire dat_rsp_l0_sub_c; +wire [64 -1:0] dat_rsp_l0c0; +wire [64 -1:0] dat_rsp_l0c1; +wire dat_rsp_l1_block_end; +wire [8:0] dat_rsp_l1_flag; +wire dat_rsp_l1_pvld; +wire [64*2 -1:0] dat_rsp_l1_sft_in; +wire dat_rsp_l1_stripe_end; +wire dat_rsp_l1_sub_c; +wire [64 -1:0] dat_rsp_l1c0; +wire [64 -1:0] dat_rsp_l1c1; +wire dat_rsp_l2_block_end; +wire [8:0] dat_rsp_l2_flag; +wire dat_rsp_l2_pvld; +wire [64*2 -1:0] dat_rsp_l2_sft_in; +wire dat_rsp_l2_stripe_end; +wire dat_rsp_l2_sub_c; +wire [64 -1:0] dat_rsp_l2c0; +wire [64 -1:0] dat_rsp_l2c1; +wire dat_rsp_l3_block_end; +wire [8:0] dat_rsp_l3_flag; +wire dat_rsp_l3_pvld; +wire [64*2 -1:0] dat_rsp_l3_sft_in; +wire dat_rsp_l3_stripe_end; +wire dat_rsp_l3_sub_c; +wire [64 -1:0] dat_rsp_l3c0; +wire [64 -1:0] dat_rsp_l3c1; +wire dat_rsp_layer_end; +wire [8 -1:0] dat_rsp_mask_8b; +wire [8 -1:0] dat_rsp_mask_val_int8; +wire [8 -1:0] dat_rsp_mask_w; +wire [8 -1:0] dat_rsp_ori_mask; +wire dat_rsp_p0_vld_w; +wire dat_rsp_p1_vld_w; +wire [64 -1:0] dat_rsp_pad_value; +wire [26:0] dat_rsp_pd; +wire [26:0] dat_rsp_pd_d0; +wire [7:0] dat_rsp_pipe_bytes; +wire dat_rsp_pipe_ch_end; +wire [1:0] dat_rsp_pipe_cur_sub_h; +wire dat_rsp_pipe_dummy; +wire [8:0] dat_rsp_pipe_flag; +wire [28:0] dat_rsp_pipe_pd; +wire [28:0] dat_rsp_pipe_pd_d0; +wire dat_rsp_pipe_pvld; +wire dat_rsp_pipe_pvld_d0; +wire dat_rsp_pipe_rls; +wire dat_rsp_pipe_sub_c; +wire [1:0] dat_rsp_pipe_sub_h; +wire [1:0] dat_rsp_pipe_sub_w; +wire dat_rsp_pipe_sub_w_st; +wire dat_rsp_pra_en; +wire dat_rsp_pvld; +wire dat_rsp_pvld_d0; +wire dat_rsp_rls; +wire dat_rsp_stripe_end; +wire dat_rsp_stripe_st; +wire dat_rsp_sub_c; +wire [1:0] dat_rsp_sub_h; +wire [1:0] dat_rsp_sub_w; +wire [64 -1:0] dat_rsp_wg; +wire [255:0] dat_rsp_wg_ch0; +wire [255:0] dat_rsp_wg_ch1; +wire [255:0] dat_rsp_wg_ch2; +wire [255:0] dat_rsp_wg_ch3; +wire [64 -1:0] dat_rsp_wg_lb; +wire [64 -1:0] dat_rsp_wg_lt; +wire [64 -1:0] dat_rsp_wg_rb; +wire [64 -1:0] dat_rsp_wg_rt; +wire dat_rsp_wg_sel_8b_hi; +wire dat_rsp_wg_sel_8b_lo; +wire dat_rsp_wg_sel_lb; +wire dat_rsp_wg_sel_lt; +wire dat_rsp_wg_sel_rb; +wire dat_rsp_wg_sel_rt; +wire [13:0] dat_slice_avl_add; +wire [13:0] dat_slice_avl_sub; +wire [13:0] dat_slice_avl_w; +wire [2303:0] dat_wg; +wire [255:0] dat_wg_8b_ch0; +wire [255:0] dat_wg_8b_ch1; +wire [255:0] dat_wg_8b_ch2; +wire [255:0] dat_wg_8b_ch3; +wire [255:0] dat_wg_8b_ch4; +wire [255:0] dat_wg_8b_ch5; +wire [255:0] dat_wg_8b_ch6; +wire [255:0] dat_wg_8b_ch7; +wire dat_wg_adv; +wire dat_wg_req_dummy; +wire dat_wg_req_skip; +wire [4:0] data_bank_w; +wire [5:0] data_batch_w; +wire [10:0] datain_c_cnt_inc; +wire datain_c_cnt_reg_en; +wire [10:0] datain_c_cnt_w; +wire [10:0] datain_channel_cmp_w; +wire [13:0] datain_h_cnt_inc; +wire datain_h_cnt_reg_en; +wire [13:0] datain_h_cnt_st; +wire [13:0] datain_h_cnt_w; +wire [13:0] datain_h_cur; +wire datain_h_ori_reg_en; +wire [12:0] datain_height_cmp_w; +wire [13:0] datain_w_cnt_inc; +wire datain_w_cnt_reg_en; +wire [13:0] datain_w_cnt_st; +wire [13:0] datain_w_cnt_w; +wire [13:0] datain_w_cur; +wire datain_w_ori_reg_en; +wire [12:0] datain_width_cmp_w; +wire [13:0] datain_width_w; +wire [2:0] dataout_w_add; +wire [12:0] dataout_w_cnt_inc; +wire dataout_w_cnt_reg_en; +wire [12:0] dataout_w_cnt_w; +wire [12:0] dataout_w_init; +wire dataout_w_ori_reg_en; +wire [12:0] dataout_width_cmp_w; +wire [64 -1:0] dbg_csc_dat; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: wire [8 -1:0] dbg_csc_dat_${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8 -1:0] dbg_csc_dat_0; +wire [8 -1:0] dbg_csc_dat_1; +wire [8 -1:0] dbg_csc_dat_2; +wire [8 -1:0] dbg_csc_dat_3; +wire [8 -1:0] dbg_csc_dat_4; +wire [8 -1:0] dbg_csc_dat_5; +wire [8 -1:0] dbg_csc_dat_6; +wire [8 -1:0] dbg_csc_dat_7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire dl_block_end; +wire dl_channel_end; +wire [6:0] dl_channel_size; +wire [1:0] dl_cur_sub_h; +wire dl_dat_release; +wire dl_group_end; +wire [4:0] dl_h_offset; +wire [9:0] dl_h_offset_ext; +wire [30:0] dl_in_pd; +wire [30:0] dl_in_pd_d0; +wire dl_in_pvld; +wire dl_in_pvld_d0; +wire dl_layer_end; +wire [30:0] dl_pd; +wire [30:0] dl_pd_d0; +wire dl_pvld; +wire dl_pvld_d0; +wire [6:0] dl_stripe_length; +wire [4:0] dl_w_offset; +wire [9:0] dl_w_offset_ext; +wire [15 -1:0] entries_batch_w; +wire [15 -1:0] entries_single_w; +wire [15 -1:0] entries_w; +wire [14 -1:0] h_bias_0_stride_w; +wire [14 -1:0] h_bias_0_w; +wire [14 -1:0] h_bias_1_stride_w; +wire [14 -1:0] h_bias_1_w; +wire [14 -1:0] h_bias_2_w; +wire [14 -1:0] h_bias_3_w; +wire [14 -1:0] h_bias_d1; +wire [1:0] h_bias_reg_en; +wire [13:0] h_offset_slice_w; +wire is_batch_end; +wire is_conv; +wire is_dat_entry_end_wrap; +wire is_dat_entry_st_wrap; +wire is_dat_req_addr_wrap; +wire is_img; +wire is_last_channel; +wire is_pixel; +wire is_running_first; +wire is_sg_done; +wire is_sg_idle; +wire is_sg_running; +wire is_stripe_end; +wire is_stripe_equal; +wire is_sub_h_end; +wire is_w_end; +wire is_w_end_ahead; +wire is_winograd; +wire layer_st; +wire mon_batch_cnt_w; +wire mon_c_bias_w; +wire mon_dat_entry_avl_w; +wire mon_dat_entry_end_inc_wrap; +wire mon_dat_entry_st_inc_wrap; +wire [3:0] mon_dat_out_pra_vld; +wire [1:0] mon_dat_req_addr_wrap; +wire [64 -1:0] mon_dat_rsp_l0_sft; +wire [64 -1:0] mon_dat_rsp_l1_sft; +wire [64 -1:0] mon_dat_rsp_l2_sft; +wire [64 -1:0] mon_dat_rsp_l3_sft; +wire [3:0] mon_dat_rsp_pra_rdy; +wire mon_dat_slice_avl_w; +wire mon_data_bank_w; +wire mon_datain_c_cnt_inc; +wire mon_datain_h_cnt_inc; +wire mon_datain_h_cur; +wire mon_datain_w_cnt_inc; +wire mon_datain_w_cur; +wire mon_dataout_w_cnt_inc; +wire [5:0] mon_entries_batch_w; +wire mon_entries_single_w; +wire mon_entries_w; +wire [5:0] mon_h_bias_0_stride_w; +wire [14 -1:0] mon_h_bias_0_w; +wire [12:0] mon_h_bias_1_stride_w; +wire [4:0] mon_h_bias_1_w; +wire [4:0] mon_h_bias_2_w; +wire [1:0] mon_h_bias_3_w; +wire mon_h_bias_d1; +wire mon_pixel_w_cnt_w; +wire [1:0] mon_pixel_x_init_w; +wire mon_rls_slices_w; +wire mon_rsp_sft_cnt_l0_w; +wire mon_rsp_sft_cnt_l1_w; +wire mon_rsp_sft_cnt_l2_w; +wire mon_rsp_sft_cnt_l3_w; +wire [13:0] mon_slice_entries_w; +wire [1:0] mon_slice_left_w; +wire mon_stripe_cnt_inc; +wire [2:0] mon_sub_h_total_w; +wire pixel_ch_ori_reg_en; +wire [11:0] pixel_ch_stride_w; +wire pixel_force_clr; +wire pixel_force_fetch; +wire pixel_w_cnt_reg_en; +wire [15:0] pixel_w_cnt_w; +wire [14:0] pixel_w_cur; +wire pixel_w_ori_reg_en; +wire [7:0] pixel_x_add_w; +wire [6:0] pixel_x_byte_stride_w; +wire [6:0] pixel_x_cnt_add; +wire [6:0] pixel_x_init_offset_w; +wire [5:0] pixel_x_init_w; +wire [5:0] pixel_x_stride_w; +wire [1:0] pra_precision_0; +wire [1:0] pra_precision_1; +wire [1:0] pra_precision_2; +wire [1:0] pra_precision_3; +wire [1:0] pra_truncate_0; +wire [1:0] pra_truncate_1; +wire [1:0] pra_truncate_2; +wire [1:0] pra_truncate_3; +wire [1:0] pra_truncate_w; +wire reuse_rls; +wire [13:0] rls_slices_w; +wire rsp_sft_cnt_l0_en; +wire [7:0] rsp_sft_cnt_l0_inc; +wire rsp_sft_cnt_l0_ori_en; +wire [7:0] rsp_sft_cnt_l0_sub; +wire [7:0] rsp_sft_cnt_l0_w; +wire rsp_sft_cnt_l1_en; +wire [7:0] rsp_sft_cnt_l1_inc; +wire rsp_sft_cnt_l1_ori_en; +wire [7:0] rsp_sft_cnt_l1_sub; +wire [7:0] rsp_sft_cnt_l1_w; +wire rsp_sft_cnt_l2_en; +wire [7:0] rsp_sft_cnt_l2_inc; +wire rsp_sft_cnt_l2_ori_en; +wire [7:0] rsp_sft_cnt_l2_sub; +wire [7:0] rsp_sft_cnt_l2_w; +wire rsp_sft_cnt_l3_en; +wire [7:0] rsp_sft_cnt_l3_inc; +wire rsp_sft_cnt_l3_ori_en; +wire [7:0] rsp_sft_cnt_l3_sub; +wire [7:0] rsp_sft_cnt_l3_w; +wire rsp_sft_l1_sel_1; +wire rsp_sft_l1_sel_2; +wire rsp_sft_l1_sel_3; +wire rsp_sft_l2_sel_1; +wire rsp_sft_l2_sel_2; +wire rsp_sft_l2_sel_3; +wire rsp_sft_l3_sel_1; +wire rsp_sft_l3_sel_2; +wire rsp_sft_l3_sel_3; +wire sc2buf_dat_rd_en_w; +wire [15 -1:0] sc2cdma_dat_entries_w; +wire [13:0] sc2cdma_dat_slices_w; +wire [8:0] sc2mac_dat_pd_w; +wire slcg_wg_en_w; +wire [15 -1:0] slice_entries_w; +wire [13:0] slice_left_w; +wire [13:0] slices_oprand; +wire [6:0] stripe_cnt_inc; +wire stripe_cnt_reg_en; +wire [6:0] stripe_cnt_w; +wire [2:0] sub_h_cmp_w; +wire [2:0] sub_h_cnt_inc; +wire sub_h_cnt_reg_en; +wire [1:0] sub_h_cnt_w; +wire [2:0] sub_h_total_w; +wire sub_rls; +wire [14:0] w_bias_int8; +wire w_bias_reg_en; +wire [13:0] w_bias_w; +wire [5:0] x_dilate_w; +wire [5:0] y_dilate_w; +///////////////////////////////////////////////////////////////////////////////////////////// +// Pipeline of Weight loader, for both compressed weight and uncompressed weight +// +// input_package +// | +// data request +// | +// conv_buffer +// | +// feature data---> data relase +// | | +// REG PRA +// | | +// REGISTER +// | +// MAC +// +///////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///// status from sequence generator ///// +////////////////////////////////////////////////////////////// +assign is_sg_idle = (sc_state == 0 ); +assign is_sg_running = (sc_state == 2 ); +assign is_sg_done = (sc_state == 3 ); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_sg_running\" -q is_sg_running_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_sg_running_d1 <= 1'b0; + end else begin + is_sg_running_d1 <= is_sg_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// input signals from registers ///// +////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en & is_sg_idle; +assign is_pixel = (reg2dp_datain_format == 1'h1 ); +`ifdef NVDLA_WINOGRAD_ENABLE +assign is_winograd = (reg2dp_conv_mode == 1'h1 ); +`else +assign is_winograd = 1'b0; +`endif +assign is_conv = (reg2dp_conv_mode == 1'h0 ); +assign is_img = is_conv & is_pixel; +assign {mon_data_bank_w, data_bank_w} = reg2dp_data_bank + 1'b1; +`ifdef NVDLA_BATCH_ENABLE +assign data_batch_w = (is_winograd | is_img) ? 6'b1 : reg2dp_batches + 1'b1; +assign batch_cmp_w = (is_winograd | is_img) ? 5'b0 : reg2dp_batches; +`else +assign data_batch_w = 6'b1; +assign batch_cmp_w = 5'b0; +`endif +//assign is_int8 = (reg2dp_proc_precision == 2'h0 ); +//assign is_fp16 = (reg2dp_proc_precision == 2'h2 ); +assign datain_width_w = is_winograd ? ({2'b0, reg2dp_datain_width_ext[12:2]} + 1'b1) : reg2dp_datain_width_ext + 1'b1; +assign datain_width_cmp_w = reg2dp_datain_width_ext; +assign datain_height_cmp_w = reg2dp_datain_height_ext; +assign datain_channel_cmp_w = is_winograd ? reg2dp_weight_channel_ext[12:2] : {{3 -2{1'b0}}, reg2dp_weight_channel_ext[12:3]}; +//y_ex=0,sub_h_total=1;y_ex=1,sub_h_total=2; y_ext=2,sub_h_total=4; non_image, sub_h_total=1; +//sub_h_total means how many h lines are used in post-extention +assign {sub_h_total_w, mon_sub_h_total_w} = is_img ? (6'h9 << reg2dp_y_extension) : 6'h8; +assign sub_h_cmp_w = is_img ? sub_h_total_w : is_winograd ? 3'h2 : 3'h1; +assign dataout_w_init[12:0] = sub_h_cmp_w - 1'b1; +assign conv_x_stride_w = (is_winograd) ? 4'b1 : reg2dp_conv_x_stride_ext + 1'b1; +assign pixel_x_stride_w = (reg2dp_datain_channel_ext[1:0] == 2'h3) ? {conv_x_stride_w, 2'b0} : //*4, after pre_extension + (reg2dp_datain_channel_ext[1:0] == 2'h2) ? ({conv_x_stride_w, 1'b0} + conv_x_stride_w) : //*3 + {2'b0, conv_x_stride_w}; //*1 +assign {mon_pixel_x_init_w,pixel_x_init_w} = (reg2dp_y_extension == 2'h2) ? ({pixel_x_stride_w, 1'b0} + pixel_x_stride_w + reg2dp_weight_channel_ext[5:0]) : + (reg2dp_y_extension == 2'h1) ? (pixel_x_stride_w + reg2dp_weight_channel_ext[5:0]): + (reg2dp_weight_channel_ext >= 7'h08) ? {3{1'b1}}: //cut by atomC + {{6-3{1'b0}},reg2dp_weight_channel_ext[3 -1:0]}; +assign pixel_x_init_offset_w = (reg2dp_weight_channel_ext[3 -1:0] + 1'b1); +assign pixel_x_add_w = (reg2dp_y_extension == 2'h2) ? {pixel_x_stride_w, 2'b0} : //*4, after post_extension + (reg2dp_y_extension == 2'h1) ? {1'b0, pixel_x_stride_w, 1'b0} : //*2 + {2'b0, pixel_x_stride_w}; +assign pixel_x_byte_stride_w = {1'b0, pixel_x_stride_w}; +assign pixel_ch_stride_w = {{5-3{1'b0}},pixel_x_stride_w, {3 +1{1'b0}}}; //stick to 2*atomK no matter which config. +assign conv_y_stride_w = (is_winograd) ? 4'b1 : reg2dp_conv_y_stride_ext + 1'b1; +assign x_dilate_w = (is_winograd | is_img) ? 6'b1 : reg2dp_x_dilation_ext + 1'b1; +assign y_dilate_w = (is_winograd | is_img) ? 6'b1 : reg2dp_y_dilation_ext + 1'b1; +//reg2dp_entries means entry per slice +assign {mon_entries_single_w,entries_single_w} = (reg2dp_entries + 1'b1); +assign {mon_entries_batch_w,entries_batch_w} = entries_single_w * data_batch_w; +assign {mon_entries_w,entries_w} = (is_winograd) ? ({reg2dp_entries[12:0], 2'b0} + 3'h4) : entries_single_w; +assign h_offset_slice_w[11:0] = data_batch_w * y_dilate_w; +assign h_offset_slice_w[13:12] = 2'b0; +assign {mon_h_bias_0_stride_w,h_bias_0_stride_w} = entries * data_batch; +assign {mon_h_bias_1_stride_w,h_bias_1_stride_w} = entries * h_offset_slice; +assign {mon_rls_slices_w,rls_slices_w} = reg2dp_rls_slices + 1'b1; +assign {mon_slice_left_w,slice_left_w} = reg2dp_skip_data_rls ? (reg2dp_datain_height_ext + 1'b1) : reg2dp_datain_height_ext - reg2dp_rls_slices; +assign slices_oprand = layer_st_d1 ? rls_slices : slice_left; +assign {mon_slice_entries_w,slice_entries_w} = entries_batch * slices_oprand; +assign dataout_width_cmp_w = reg2dp_dataout_width; +assign pra_truncate_w = (reg2dp_pra_truncate == 2'h3) ? 2'h2 : reg2dp_pra_truncate; +//: my $kk=15; +//: my $jj=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"layer_st\" -q layer_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{22{1'b0}}\" -en \"layer_st\" -d \"{22{is_winograd}}\" -q is_winograd_d1"); +//: &eperl::flop("-nodeclare -rval \"{34{1'b0}}\" -en \"layer_st\" -d \"{34{is_img}}\" -q is_img_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"data_bank_w\" -q data_bank"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"datain_width_w\" -q datain_width"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"datain_width_cmp_w\" -q datain_width_cmp"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"datain_height_cmp_w\" -q datain_height_cmp"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"datain_channel_cmp_w\" -q datain_channel_cmp"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g0"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g1"); +//: &eperl::flop("-nodeclare -rval \"2'h1\" -en \"layer_st\" -d \"sub_h_total_w[2:1]\" -q sub_h_total_g2"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g3"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g4"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g5"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g6"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g7"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g8"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g9"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g10"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g11"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_cmp_w\" -q sub_h_cmp_g0"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_cmp_w\" -q sub_h_cmp_g1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_x_stride_w\" -q conv_x_stride"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_y_stride_w\" -q conv_y_stride"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_x_stride_w[0]\" -q pixel_x_stride_odd"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"data_batch_w\" -q data_batch"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"batch_cmp_w\" -q batch_cmp"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"pixel_x_init_w\" -q pixel_x_init"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"layer_st\" -d \"pixel_x_init_offset_w\" -q pixel_x_init_offset"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"layer_st\" -d \"pixel_x_add_w[6:0]\" -q pixel_x_add"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"layer_st\" -d \"pixel_x_byte_stride_w\" -q pixel_x_byte_stride"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st\" -d \"pixel_ch_stride_w\" -q pixel_ch_stride"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"x_dilate_w\" -q x_dilate"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"y_dilate_w\" -q y_dilate"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"layer_st\" -d \"reg2dp_pad_value\" -q pad_value"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st\" -d \"entries_w\" -q entries"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st\" -d \"entries_batch_w\" -q entries_batch"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st\" -d \"{1'h0,reg2dp_entries}\" -q entries_cmp"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"h_offset_slice_w\" -q h_offset_slice"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st_d1\" -d \"h_bias_0_stride_w\" -q h_bias_0_stride"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st_d1\" -d \"h_bias_1_stride_w\" -q h_bias_1_stride"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"layer_st_d1\" -d \"entries[${jj}-1:0]\" -q h_bias_2_stride"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"layer_st_d1\" -d \"entries[${jj}-1:0]\" -q h_bias_3_stride"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"rls_slices_w\" -q rls_slices"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st_d1\" -d \"slice_entries_w\" -q rls_entries"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"slice_left_w[13:0]\" -q slice_left"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"is_sg_done\" -d \"slice_left\" -q last_slices"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"is_sg_done\" -d \"slice_entries_w\" -q last_entries"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"dataout_width_cmp_w\" -q dataout_width_cmp"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"layer_st\" -d \"{4{pra_truncate_w}}\" -q pra_truncate"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"layer_st\" -d \"{4{reg2dp_proc_precision}}\" -q pra_precision"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_st_d1 <= 1'b0; + end else begin + layer_st_d1 <= layer_st; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_winograd_d1 <= {22{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + is_winograd_d1 <= {22{is_winograd}}; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + is_winograd_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_img_d1 <= {34{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + is_img_d1 <= {34{is_img}}; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + is_img_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_bank <= data_bank_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_width <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + datain_width <= datain_width_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + datain_width <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_width_cmp <= {13{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + datain_width_cmp <= datain_width_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + datain_width_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_height_cmp <= {13{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + datain_height_cmp <= datain_height_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + datain_height_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_channel_cmp <= {11{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + datain_channel_cmp <= datain_channel_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + datain_channel_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g0 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g0 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g0 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g1 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g1 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g2 <= 2'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g2 <= sub_h_total_w[2:1]; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g3 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g3 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g4 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g4 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g4 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g5 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g5 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g5 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g6 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g6 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g6 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g7 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g7 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g7 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g8 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g8 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g8 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g9 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g9 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g9 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g10 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g10 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g10 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total_g11 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total_g11 <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total_g11 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_cmp_g0 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_cmp_g0 <= sub_h_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_cmp_g0 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_cmp_g1 <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_cmp_g1 <= sub_h_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_cmp_g1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_x_stride <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + conv_x_stride <= conv_x_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + conv_x_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + conv_y_stride <= {4{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + conv_y_stride <= conv_y_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + conv_y_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_x_stride_odd <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + pixel_x_stride_odd <= pixel_x_stride_w[0]; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_x_stride_odd <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_batch <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_batch <= data_batch_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_batch <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + batch_cmp <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + batch_cmp <= batch_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + batch_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_x_init <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_x_init <= pixel_x_init_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_x_init <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_x_init_offset <= {7{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_x_init_offset <= pixel_x_init_offset_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_x_init_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_x_add <= {7{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_x_add <= pixel_x_add_w[6:0]; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_x_add <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_x_byte_stride <= {7{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_x_byte_stride <= pixel_x_byte_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_x_byte_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_ch_stride <= {12{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pixel_ch_stride <= pixel_ch_stride_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pixel_ch_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + x_dilate <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + x_dilate <= x_dilate_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + x_dilate <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + y_dilate <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + y_dilate <= y_dilate_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + y_dilate <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pad_value <= {16{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pad_value <= reg2dp_pad_value; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pad_value <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + entries <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + entries <= entries_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + entries_batch <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + entries_batch <= entries_batch_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + entries_batch <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + entries_cmp <= {15{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + entries_cmp <= {1'h0,reg2dp_entries}; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + entries_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_offset_slice <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + h_offset_slice <= h_offset_slice_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + h_offset_slice <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_bias_0_stride <= {12{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + h_bias_0_stride <= h_bias_0_stride_w; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + h_bias_0_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_bias_1_stride <= {12{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + h_bias_1_stride <= h_bias_1_stride_w; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + h_bias_1_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_bias_2_stride <= {14{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + h_bias_2_stride <= entries[14-1:0]; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + h_bias_2_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + h_bias_3_stride <= {14{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + h_bias_3_stride <= entries[14-1:0]; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + h_bias_3_stride <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rls_slices <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + rls_slices <= rls_slices_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + rls_slices <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rls_entries <= {15{1'b0}}; + end else begin + if ((layer_st_d1) == 1'b1) begin + rls_entries <= slice_entries_w; + // VCS coverage off + end else if ((layer_st_d1) == 1'b0) begin + end else begin + rls_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slice_left <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + slice_left <= slice_left_w[13:0]; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + slice_left <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_slices <= {14{1'b0}}; + end else begin + if ((is_sg_done) == 1'b1) begin + last_slices <= slice_left; + // VCS coverage off + end else if ((is_sg_done) == 1'b0) begin + end else begin + last_slices <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_entries <= {15{1'b0}}; + end else begin + if ((is_sg_done) == 1'b1) begin + last_entries <= slice_entries_w; + // VCS coverage off + end else if ((is_sg_done) == 1'b0) begin + end else begin + last_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dataout_width_cmp <= {13{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + dataout_width_cmp <= dataout_width_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + dataout_width_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pra_truncate <= {8{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pra_truncate <= {4{pra_truncate_w}}; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pra_truncate <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pra_precision <= {8{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + pra_precision <= {4{reg2dp_proc_precision}}; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + pra_precision <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_wg_en_w = reg2dp_op_en & is_winograd; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_wg_en_w\" -q slcg_wg_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_wg_en_d1\" -q slcg_wg_en_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_wg_en_d2\" -q slcg_wg_en_d3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_wg_en_d1 <= 1'b0; + end else begin + slcg_wg_en_d1 <= slcg_wg_en_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_wg_en_d2 <= 1'b0; + end else begin + slcg_wg_en_d2 <= slcg_wg_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_wg_en_d3 <= 1'b0; + end else begin + slcg_wg_en_d3 <= slcg_wg_en_d2; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign slcg_wg_en = slcg_wg_en_d3; +////////////////////////////////////////////////////////////// +///// cbuf status management ///// +////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +assign cbuf_reset = sc2cdma_dat_pending_req; +assign is_running_first = is_sg_running & ~is_sg_running_d1; +//////////////////////////////////// calculate how many avaliable dat slices in cbuf//////////////////////////////////// +assign dat_slice_avl_add = cdma2sc_dat_updt ? cdma2sc_dat_slices : 14'b0; +assign dat_slice_avl_sub = dat_rls ? sc2cdma_dat_slices_w : 14'b0; +assign {mon_dat_slice_avl_w, dat_slice_avl_w} = (cbuf_reset) ? 14'b0 : dat_slice_avl + dat_slice_avl_add - dat_slice_avl_sub; +//////////////////////////////////// calculate how many avaliable dat entries in cbuf//////////////////////////////////// +assign dat_entry_avl_add = cdma2sc_dat_updt ? cdma2sc_dat_entries :{15{1'b0}}; +assign dat_entry_avl_sub = dat_rls ? sc2cdma_dat_entries_w : {15{1'b0}}; +assign {mon_dat_entry_avl_w,dat_entry_avl_w} = (cbuf_reset) ? {15{1'b0}} : dat_entry_avl + dat_entry_avl_add - dat_entry_avl_sub; +//////////////////////////////////// calculate avilable data entries start offset in cbuf banks //////////////////////////////////// +// data_bank is the highest bank for storing data +assign {mon_dat_entry_st_inc,dat_entry_st_inc} = dat_entry_st + dat_entry_avl_sub; +assign {mon_dat_entry_st_inc_wrap, dat_entry_st_inc_wrap} = dat_entry_st_inc - {data_bank, {9{1'b0}} }; +assign is_dat_entry_st_wrap = (dat_entry_st_inc >= {1'b0, data_bank, {9{1'b0}} }); +assign dat_entry_st_w = (cbuf_reset) ? {15{1'b0}} : is_dat_entry_st_wrap ? dat_entry_st_inc_wrap : dat_entry_st_inc[15 -1:0]; +//////////////////////////////////// calculate avilable data entries end offset in cbuf banks//////////////////////////////////// +assign {mon_dat_entry_end_inc,dat_entry_end_inc} = dat_entry_end + dat_entry_avl_add; +assign {mon_dat_entry_end_inc_wrap,dat_entry_end_inc_wrap} = dat_entry_end_inc - {data_bank, {9{1'b0}} }; +assign is_dat_entry_end_wrap = (dat_entry_end_inc >= {1'b0, data_bank, {9{1'b0}} }); +assign dat_entry_end_w = (cbuf_reset) ? {15{1'b0}} : is_dat_entry_end_wrap ? dat_entry_end_inc_wrap : dat_entry_end_inc[15 -1:0]; +//////////////////////////////////// registers and assertions //////////////////////////////////// +//: my $kk= 15; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{14{1'b0}}\" -en \"cdma2sc_dat_updt | dat_rls | cbuf_reset\" -d \"dat_slice_avl_w\" -q dat_slice_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{${kk}{1'b0}}\" -en \"cdma2sc_dat_updt | dat_rls | cbuf_reset\" -d \"dat_entry_avl_w\" -q dat_entry_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{${kk}{1'b0}}\" -en \"cbuf_reset | dat_rls\" -d \"dat_entry_st_w\" -q dat_entry_st"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{${kk}{1'b0}}\" -en \"cbuf_reset | cdma2sc_dat_updt\" -d \"dat_entry_end_w\" -q dat_entry_end"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_slice_avl <= {14{1'b0}}; + end else begin + if ((cdma2sc_dat_updt | dat_rls | cbuf_reset) == 1'b1) begin + dat_slice_avl <= dat_slice_avl_w; + // VCS coverage off + end else if ((cdma2sc_dat_updt | dat_rls | cbuf_reset) == 1'b0) begin + end else begin + dat_slice_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entry_avl <= {15{1'b0}}; + end else begin + if ((cdma2sc_dat_updt | dat_rls | cbuf_reset) == 1'b1) begin + dat_entry_avl <= dat_entry_avl_w; + // VCS coverage off + end else if ((cdma2sc_dat_updt | dat_rls | cbuf_reset) == 1'b0) begin + end else begin + dat_entry_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entry_st <= {15{1'b0}}; + end else begin + if ((cbuf_reset | dat_rls) == 1'b1) begin + dat_entry_st <= dat_entry_st_w; + // VCS coverage off + end else if ((cbuf_reset | dat_rls) == 1'b0) begin + end else begin + dat_entry_st <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_entry_end <= {15{1'b0}}; + end else begin + if ((cbuf_reset | cdma2sc_dat_updt) == 1'b1) begin + dat_entry_end <= dat_entry_end_w; + // VCS coverage off + end else if ((cbuf_reset | cdma2sc_dat_updt) == 1'b0) begin + end else begin + dat_entry_end <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//================ Non-SLCG clock domain end ================// +////////////////////////////////////////////////////////////// +///// cbuf status update ///// +////////////////////////////////////////////////////////////// +assign sub_rls = (dat_rsp_pvld & dat_rsp_rls); +assign reuse_rls = sg2dl_reuse_rls; +assign dat_rls = (reuse_rls & (|last_slices)) | (sub_rls & (|rls_slices)); +assign sc2cdma_dat_slices_w = sub_rls ? rls_slices : last_slices; +assign sc2cdma_dat_entries_w = sub_rls ? rls_entries : last_entries; +//: my $kk=15; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_rls\" -q sc2cdma_dat_updt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dat_rls\" -d \"sc2cdma_dat_slices_w[13:0]\" -q sc2cdma_dat_slices"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dat_rls\" -d \"sc2cdma_dat_entries_w\" -q sc2cdma_dat_entries"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2cdma_dat_updt <= 1'b0; + end else begin + sc2cdma_dat_updt <= dat_rls; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2cdma_dat_slices <= {14{1'b0}}; + end else begin + if ((dat_rls) == 1'b1) begin + sc2cdma_dat_slices <= sc2cdma_dat_slices_w[13:0]; + // VCS coverage off + end else if ((dat_rls) == 1'b0) begin + end else begin + sc2cdma_dat_slices <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2cdma_dat_entries <= {15{1'b0}}; + end else begin + if ((dat_rls) == 1'b1) begin + sc2cdma_dat_entries <= sc2cdma_dat_entries_w; + // VCS coverage off + end else if ((dat_rls) == 1'b0) begin + end else begin + sc2cdma_dat_entries <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// input sg2dl package ///// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///// generate data read sequence ///// +////////////////////////////////////////////////////////////// +//: my $total_depth = 0 + 5; +//: my $wg_depth = 0; +//: +//: print "assign dl_in_pvld_d0 = sg2dl_pvld;\n"; +//: print "assign dl_in_pd_d0 = sg2dl_pd;\n\n"; +//: +//: for(my $i = 0; $i < $total_depth; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dl_in_pvld_d${i}\" -q dl_in_pvld_d${j}"); +//: &eperl::flop("-wid 31 -rval \"{31{1'b0}}\" -en \"dl_in_pvld_d${i}\" -d \"dl_in_pd_d${i}\" -q dl_in_pd_d${j}"); +//: } +//: +//: my $d0 = $total_depth; +//: my $d1 = $wg_depth; +//: +//: print "assign dl_in_pvld = (is_winograd_d1[0]) ? dl_in_pvld_d${d1} : dl_in_pvld_d${d0};\n"; +//: print "assign dl_in_pd = (is_winograd_d1[1]) ? dl_in_pd_d${d1} : dl_in_pd_d${d0};\n\n"; +//: my $pipe_depth = 4; +//: my $i; +//: my $j; +//: print "assign dl_pvld_d0 = dl_in_pvld;\n"; +//: print "assign dl_pd_d0 = dl_in_pd;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_pvld_d${i}\" -q dl_pvld_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{31{1'b0}}\" -en \"dl_pvld_d${i}\" -d \"dl_pd_d${i}\" -q dl_pd_d${j}"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dl_in_pvld_d0 = sg2dl_pvld; +assign dl_in_pd_d0 = sg2dl_pd; + +reg dl_in_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pvld_d1 <= 1'b0; + end else begin + dl_in_pvld_d1 <= dl_in_pvld_d0; + end +end +reg [30:0] dl_in_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pd_d1 <= {31{1'b0}}; + end else begin + if ((dl_in_pvld_d0) == 1'b1) begin + dl_in_pd_d1 <= dl_in_pd_d0; + // VCS coverage off + end else if ((dl_in_pvld_d0) == 1'b0) begin + end else begin + dl_in_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg dl_in_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pvld_d2 <= 1'b0; + end else begin + dl_in_pvld_d2 <= dl_in_pvld_d1; + end +end +reg [30:0] dl_in_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pd_d2 <= {31{1'b0}}; + end else begin + if ((dl_in_pvld_d1) == 1'b1) begin + dl_in_pd_d2 <= dl_in_pd_d1; + // VCS coverage off + end else if ((dl_in_pvld_d1) == 1'b0) begin + end else begin + dl_in_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg dl_in_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pvld_d3 <= 1'b0; + end else begin + dl_in_pvld_d3 <= dl_in_pvld_d2; + end +end +reg [30:0] dl_in_pd_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pd_d3 <= {31{1'b0}}; + end else begin + if ((dl_in_pvld_d2) == 1'b1) begin + dl_in_pd_d3 <= dl_in_pd_d2; + // VCS coverage off + end else if ((dl_in_pvld_d2) == 1'b0) begin + end else begin + dl_in_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +reg dl_in_pvld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pvld_d4 <= 1'b0; + end else begin + dl_in_pvld_d4 <= dl_in_pvld_d3; + end +end +reg [30:0] dl_in_pd_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pd_d4 <= {31{1'b0}}; + end else begin + if ((dl_in_pvld_d3) == 1'b1) begin + dl_in_pd_d4 <= dl_in_pd_d3; + // VCS coverage off + end else if ((dl_in_pvld_d3) == 1'b0) begin + end else begin + dl_in_pd_d4 <= 'bx; + // VCS coverage on + end + end +end +reg dl_in_pvld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pvld_d5 <= 1'b0; + end else begin + dl_in_pvld_d5 <= dl_in_pvld_d4; + end +end +reg [30:0] dl_in_pd_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_in_pd_d5 <= {31{1'b0}}; + end else begin + if ((dl_in_pvld_d4) == 1'b1) begin + dl_in_pd_d5 <= dl_in_pd_d4; + // VCS coverage off + end else if ((dl_in_pvld_d4) == 1'b0) begin + end else begin + dl_in_pd_d5 <= 'bx; + // VCS coverage on + end + end +end +assign dl_in_pvld = (is_winograd_d1[0]) ? dl_in_pvld_d0 : dl_in_pvld_d5; +assign dl_in_pd = (is_winograd_d1[1]) ? dl_in_pd_d0 : dl_in_pd_d5; + +assign dl_pvld_d0 = dl_in_pvld; +assign dl_pd_d0 = dl_in_pd; + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pvld_d1 <= 1'b0; + end else begin + dl_pvld_d1 <= dl_pvld_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pd_d1 <= {31{1'b0}}; + end else begin + if ((dl_pvld_d0) == 1'b1) begin + dl_pd_d1 <= dl_pd_d0; + // VCS coverage off + end else if ((dl_pvld_d0) == 1'b0) begin + end else begin + dl_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pvld_d2 <= 1'b0; + end else begin + dl_pvld_d2 <= dl_pvld_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pd_d2 <= {31{1'b0}}; + end else begin + if ((dl_pvld_d1) == 1'b1) begin + dl_pd_d2 <= dl_pd_d1; + // VCS coverage off + end else if ((dl_pvld_d1) == 1'b0) begin + end else begin + dl_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pvld_d3 <= 1'b0; + end else begin + dl_pvld_d3 <= dl_pvld_d2; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pd_d3 <= {31{1'b0}}; + end else begin + if ((dl_pvld_d2) == 1'b1) begin + dl_pd_d3 <= dl_pd_d2; + // VCS coverage off + end else if ((dl_pvld_d2) == 1'b0) begin + end else begin + dl_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pvld_d4 <= 1'b0; + end else begin + dl_pvld_d4 <= dl_pvld_d3; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_pd_d4 <= {31{1'b0}}; + end else begin + if ((dl_pvld_d3) == 1'b1) begin + dl_pd_d4 <= dl_pd_d3; + // VCS coverage off + end else if ((dl_pvld_d3) == 1'b0) begin + end else begin + dl_pd_d4 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dl_pvld = (sub_h_total_g0[2] & dl_pvld_d1) | + (sub_h_total_g0[1] & dl_pvld_d3) | + (sub_h_total_g0[0] & dl_pvld_d4); +assign dl_pd = ({31 {sub_h_total_g1[2]}} & dl_pd_d1) | + ({31 {sub_h_total_g1[1]}} & dl_pd_d3) | + ({31 {sub_h_total_g1[0]}} & dl_pd_d4); +// PKT_UNPACK_WIRE( csc_dat_pkg , dl_ , dl_pd ) +assign dl_w_offset[4:0] = dl_pd[4:0]; //this is weight offset +assign dl_h_offset[4:0] = dl_pd[9:5]; //weight offset +assign dl_channel_size[6:0] = dl_pd[16:10]; +assign dl_stripe_length[6:0]= dl_pd[23:17]; +assign dl_cur_sub_h[1:0] = dl_pd[25:24]; +assign dl_block_end = dl_pd[26]; +assign dl_channel_end = dl_pd[27]; +assign dl_group_end = dl_pd[28]; +assign dl_layer_end = dl_pd[29]; +assign dl_dat_release = dl_pd[30]; +////////////////////////// batch up counter ////////////////////////// +assign {mon_batch_cnt_w,batch_cnt_w} = layer_st ? 6'b0 : is_batch_end ? 6'b0 : batch_cnt + 1'b1; +assign is_batch_end = (batch_cnt == batch_cmp); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st | dat_exec_valid\" -d \"batch_cnt_w\" -q batch_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + batch_cnt <= {5{1'b0}}; + end else begin + if ((layer_st | dat_exec_valid) == 1'b1) begin + batch_cnt <= batch_cnt_w; + // VCS coverage off + end else if ((layer_st | dat_exec_valid) == 1'b0) begin + end else begin + batch_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// sub height up counter ////////////////////////// +assign sub_h_cnt_inc = sub_h_cnt + 1'b1; +assign sub_h_cnt_w = (layer_st | is_sub_h_end) ? 2'b0 : sub_h_cnt_inc[1:0]; +assign is_sub_h_end = (sub_h_cnt_inc == sub_h_cmp_g0); +assign sub_h_cnt_reg_en = layer_st | ((is_winograd_d1[2] | (|reg2dp_y_extension)) & dat_exec_valid); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sub_h_cnt_reg_en\" -d \"sub_h_cnt_w\" -q sub_h_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_cnt <= {2{1'b0}}; + end else begin + if ((sub_h_cnt_reg_en) == 1'b1) begin + sub_h_cnt <= sub_h_cnt_w; + // VCS coverage off + end else if ((sub_h_cnt_reg_en) == 1'b0) begin + end else begin + sub_h_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// stripe up counter ////////////////////////// +assign {mon_stripe_cnt_inc,stripe_cnt_inc} = stripe_cnt + 1'b1; +assign stripe_cnt_w = layer_st ? 7'b0 : + (is_stripe_equal & ~is_sub_h_end) ? stripe_cnt : + is_stripe_end ? 7'b0 : + stripe_cnt_inc; +assign is_stripe_equal = is_batch_end & (stripe_cnt_inc == dl_stripe_length); +assign is_stripe_end = is_stripe_equal & is_sub_h_end; +assign stripe_cnt_reg_en = layer_st | (dat_exec_valid & is_batch_end); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"stripe_cnt_reg_en\" -d \"stripe_cnt_w\" -q stripe_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stripe_cnt <= {7{1'b0}}; + end else begin + if ((stripe_cnt_reg_en) == 1'b1) begin + stripe_cnt <= stripe_cnt_w; + // VCS coverage off + end else if ((stripe_cnt_reg_en) == 1'b0) begin + end else begin + stripe_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// pipe valid generator ////////////////////////// +assign dat_pipe_local_valid_w = (dat_pipe_valid & is_stripe_equal) ? 1'b0 : dl_pvld ? 1'b1 : dat_pipe_local_valid; +assign dat_pipe_valid = dl_pvld | dat_pipe_local_valid; +assign dat_exec_valid = dl_pvld ? 1'b1 : (~(|stripe_cnt) & ~(|sub_h_cnt) & ~(|batch_cnt)) ? 1'b0 : dat_exec_valid_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pipe_local_valid_w\" -q dat_pipe_local_valid"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pipe_valid\" -q dat_pipe_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_exec_valid\" -q dat_exec_valid_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pipe_local_valid <= 1'b0; + end else begin + dat_pipe_local_valid <= dat_pipe_local_valid_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pipe_valid_d1 <= 1'b0; + end else begin + dat_pipe_valid_d1 <= dat_pipe_valid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_exec_valid_d1 <= 1'b0; + end else begin + dat_exec_valid_d1 <= dat_exec_valid; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// request bytes ////////////////////////// +assign dat_req_bytes = {1'b0, dl_channel_size}; +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"dat_exec_valid\" -d \"dat_req_bytes\" -q dat_req_bytes_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_bytes_d1 <= {8{1'b0}}; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_bytes_d1 <= dat_req_bytes; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_bytes_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// output width coordinate counter ////////////////////////// +// sub_h T, output will compute sub_h point in w direction +assign dataout_w_add = sub_h_cmp_g1; +assign {mon_dataout_w_cnt_inc,dataout_w_cnt_inc} = dataout_w_cnt + dataout_w_add; +assign is_w_end = is_batch_end & is_sub_h_end & (dataout_w_cnt >= dataout_width_cmp); +assign is_w_end_ahead = is_batch_end & (dataout_w_cnt >= dataout_width_cmp); +assign dataout_w_cnt_w = layer_st ? dataout_w_init : + (is_stripe_end & ~dl_channel_end) ? dataout_w_ori : + is_w_end ? dataout_w_init : + dataout_w_cnt_inc; +assign dataout_w_cnt_reg_en = layer_st | (dat_exec_valid & is_batch_end & is_sub_h_end); +assign dataout_w_ori_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_channel_end); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"dataout_w_cnt_reg_en\" -d \"dataout_w_cnt_w\" -q dataout_w_cnt"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"dataout_w_ori_reg_en\" -d \"dataout_w_cnt_w\" -q dataout_w_ori"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dataout_w_cnt <= {13{1'b0}}; + end else begin + if ((dataout_w_cnt_reg_en) == 1'b1) begin + dataout_w_cnt <= dataout_w_cnt_w; + // VCS coverage off + end else if ((dataout_w_cnt_reg_en) == 1'b0) begin + end else begin + dataout_w_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dataout_w_ori <= {13{1'b0}}; + end else begin + if ((dataout_w_ori_reg_en) == 1'b1) begin + dataout_w_ori <= dataout_w_cnt_w; + // VCS coverage off + end else if ((dataout_w_ori_reg_en) == 1'b0) begin + end else begin + dataout_w_ori <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// input channel coordinate counter, only feature ////////////////////////// +assign {mon_datain_c_cnt_inc,datain_c_cnt_inc} = datain_c_cnt + 1'b1; +assign is_last_channel = (datain_c_cnt == datain_channel_cmp); +assign datain_c_cnt_w = layer_st ? 11'b0 : dl_channel_end ? 11'b0 : datain_c_cnt_inc; +assign datain_c_cnt_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_block_end); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"datain_c_cnt_reg_en\" -d \"datain_c_cnt_w\" -q datain_c_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_c_cnt <= {11{1'b0}}; + end else begin + if ((datain_c_cnt_reg_en) == 1'b1) begin + datain_c_cnt <= datain_c_cnt_w; + // VCS coverage off + end else if ((datain_c_cnt_reg_en) == 1'b0) begin + end else begin + datain_c_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// input width coordinate counter, feature/image dedicated counter ////////////////////////// +assign datain_w_cnt_st = (is_img) ? 14'b0 : (is_winograd) ? 14'h2 : 13'b0 - reg2dp_pad_left; +assign {mon_datain_w_cnt_inc,datain_w_cnt_inc} = (is_winograd_d1[3]) ? (datain_w_cnt + 2'h2) : (datain_w_cnt + conv_x_stride); +//full data cube w counter,start form negtive, only for feature data. non-image, by element +assign datain_w_cnt_w = layer_st ? datain_w_cnt_st : + (is_stripe_end & ~dl_channel_end) ? datain_w_ori : + is_w_end ? datain_w_cnt_st : + datain_w_cnt_inc; +assign dl_w_offset_ext = dl_w_offset * x_dilate; +assign {mon_datain_w_cur,datain_w_cur} = datain_w_cnt + dl_w_offset_ext; //by element +assign datain_w_cnt_reg_en = layer_st | (dat_exec_valid & is_batch_end & is_sub_h_end & ~is_img_d1[0]); +assign datain_w_ori_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_channel_end & ~is_img_d1[1]); +//notice:after sub_h T, pixel_x_add elements in W direction is used by CMAC +assign pixel_x_cnt_add = (is_sub_h_end) ? pixel_x_add : 6'b0; +//assign {mon_pixel_w_cnt_w,pixel_w_cnt_w} = (layer_st_d1) ? {{11{1'b0}}, pixel_x_init} : +// (is_stripe_end & dl_block_end & dl_channel_end & is_w_end) ? {{11{1'b0}}, pixel_x_init} : +// (is_stripe_end & dl_block_end & dl_channel_end & ~is_w_end) ? (pixel_w_ch_ori + pixel_ch_stride) : +// (is_stripe_end & dl_block_end & ~dl_channel_end) ? (pixel_w_ch_ori + pixel_x_init_offset) : +// (is_stripe_end & ~dl_block_end) ? {1'b0, pixel_w_ori} : +// (pixel_w_cnt + pixel_x_cnt_add); +//channel count. +wire [12:0] total_channel_op = (reg2dp_weight_channel_ext[3 -1:0]=={3{1'b0}}) ? + reg2dp_weight_channel_ext[12:3] : reg2dp_weight_channel_ext[12:3]+1'b1; +reg [12:0] channel_op_cnt; +wire mon_channel_op_cnt_nxt; +wire [12:0] channel_op_cnt_nxt; +assign {mon_channel_op_cnt_nxt, channel_op_cnt_nxt} = dl_channel_end&is_stripe_end ? 13'h2 : + dl_block_end&is_stripe_end ? channel_op_cnt + 1'b1 : + channel_op_cnt; +//: &eperl::flop("-q channel_op_cnt -d \"channel_op_cnt_nxt\" -wid 13 -rval \"13'h2\" -nodeclare "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_op_cnt <= 13'h2; + end else begin + channel_op_cnt <= channel_op_cnt_nxt; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire next_is_last_channel = (channel_op_cnt >= total_channel_op); +//notice, after pre-extention, image weight w_total <=128 +assign {mon_pixel_w_cnt_w,pixel_w_cnt_w} = (layer_st_d1) ? {{11{1'b0}}, pixel_x_init} : + (is_stripe_end & dl_block_end & dl_channel_end & is_w_end) ? {{11{1'b0}}, pixel_x_init} : + (is_stripe_end & dl_block_end & dl_channel_end & ~is_w_end) ? (pixel_w_ch_ori + pixel_ch_stride) : +//(is_stripe_end & dl_block_end & ~dl_channel_end) ? (pixel_w_ori + dl_in_pd_d0[16:10]) : + (is_stripe_end & dl_block_end & next_is_last_channel) ? (pixel_w_ori + pixel_x_init_offset) : + (is_stripe_end & dl_block_end & ~next_is_last_channel) ? (pixel_w_ori + 8'h08 ) : + (is_stripe_end & ~dl_block_end) ? {1'b0, pixel_w_ori} : + (pixel_w_cnt + pixel_x_cnt_add); +assign pixel_w_cur = {{3 -1{1'b0}},pixel_w_cnt[15:3]}; //by entry +assign pixel_w_cnt_reg_en = layer_st_d1 | (dat_exec_valid & is_img_d1[2] & (is_sub_h_end | is_w_end)); +assign pixel_w_ori_reg_en = layer_st_d1 | (dat_exec_valid & is_img_d1[3] & is_stripe_end & dl_block_end); +assign pixel_ch_ori_reg_en = layer_st_d1 | (dat_exec_valid & is_img_d1[4] & is_stripe_end & dl_block_end & dl_channel_end); +assign pixel_force_fetch = (is_img_d1[0] & dat_req_stripe_st) ? 1'b1 : (pixel_force_clr_d1) ? 1'b0 : pixel_force_fetch_d1; +assign pixel_force_clr = is_img_d1[0] & is_sub_h_end & (pixel_force_fetch | pixel_force_fetch_d1); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_w_cnt_reg_en\" -d \"datain_w_cnt_w\" -q datain_w_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_w_ori_reg_en\" -d \"datain_w_cnt_w\" -q datain_w_ori"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"pixel_w_cnt_reg_en\" -d \"pixel_w_cnt_w\" -q pixel_w_cnt"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"pixel_w_ori_reg_en\" -d \"pixel_w_cnt_w\" -q pixel_w_ori"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"pixel_ch_ori_reg_en\" -d \"pixel_w_cnt_w\" -q pixel_w_ch_ori"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_w_cnt <= {14{1'b0}}; + end else begin + if ((datain_w_cnt_reg_en) == 1'b1) begin + datain_w_cnt <= datain_w_cnt_w; + // VCS coverage off + end else if ((datain_w_cnt_reg_en) == 1'b0) begin + end else begin + datain_w_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_w_ori <= {14{1'b0}}; + end else begin + if ((datain_w_ori_reg_en) == 1'b1) begin + datain_w_ori <= datain_w_cnt_w; + // VCS coverage off + end else if ((datain_w_ori_reg_en) == 1'b0) begin + end else begin + datain_w_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_w_cnt <= {16{1'b0}}; + end else begin + if ((pixel_w_cnt_reg_en) == 1'b1) begin + pixel_w_cnt <= pixel_w_cnt_w; + // VCS coverage off + end else if ((pixel_w_cnt_reg_en) == 1'b0) begin + end else begin + pixel_w_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_w_ori <= {16{1'b0}}; + end else begin + if ((pixel_w_ori_reg_en) == 1'b1) begin + pixel_w_ori <= pixel_w_cnt_w; + // VCS coverage off + end else if ((pixel_w_ori_reg_en) == 1'b0) begin + end else begin + pixel_w_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_w_ch_ori <= {16{1'b0}}; + end else begin + if ((pixel_ch_ori_reg_en) == 1'b1) begin + pixel_w_ch_ori <= pixel_w_cnt_w; + // VCS coverage off + end else if ((pixel_ch_ori_reg_en) == 1'b0) begin + end else begin + pixel_w_ch_ori <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// input height coordinate counter, feature/image both ////////////////////////// +// full data cube h counter, start form negative +assign datain_h_cnt_st = (is_winograd) ? 14'b0 : 14'b0 - reg2dp_pad_top; +assign {mon_datain_h_cnt_inc, datain_h_cnt_inc} = datain_h_cnt + conv_y_stride; +assign datain_h_cnt_w = (layer_st | (is_stripe_end & dl_group_end)) ? datain_h_cnt_st : + (is_stripe_end & ~dl_channel_end) ? datain_h_ori : + is_w_end ? datain_h_cnt_inc : + datain_h_cnt; +assign datain_h_cnt_reg_en = layer_st | (dat_exec_valid & ((is_stripe_end & ~dl_channel_end) | is_w_end)); +assign datain_h_ori_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_channel_end); +assign dl_h_offset_ext = dl_h_offset * y_dilate; +assign {mon_datain_h_cur,datain_h_cur} = datain_h_cnt + dl_h_offset_ext + sub_h_cnt; +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_h_cnt_reg_en\" -d \"datain_h_cnt_w\" -q datain_h_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_h_ori_reg_en\" -d \"datain_h_cnt_w\" -q datain_h_ori"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_h_cnt <= {14{1'b0}}; + end else begin + if ((datain_h_cnt_reg_en) == 1'b1) begin + datain_h_cnt <= datain_h_cnt_w; + // VCS coverage off + end else if ((datain_h_cnt_reg_en) == 1'b0) begin + end else begin + datain_h_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datain_h_ori <= {14{1'b0}}; + end else begin + if ((datain_h_ori_reg_en) == 1'b1) begin + datain_h_ori <= datain_h_cnt_w; + // VCS coverage off + end else if ((datain_h_ori_reg_en) == 1'b0) begin + end else begin + datain_h_ori <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////// fetch valid generate ////////////////////////// +assign dat_conv_req_dummy = (datain_w_cur[13 ]) | (datain_w_cur > {1'b0, datain_width_cmp}) + | (datain_h_cur[13 ]) | (datain_h_cur > {1'b0, datain_height_cmp}); +assign dat_wg_req_dummy = 1'b0; +assign dat_wg_req_skip = ((|datain_w_cur[13:2]) & datain_w_cur[1] & (|stripe_cnt[6:1])); +assign dat_img_req_dummy = (datain_h_cur[13]) | (datain_h_cur > {1'b0, datain_height_cmp}); +//w address(in entry) is bigger than avilable entrys +assign dat_img_req_skip = ({{15 -12{1'b0}},w_bias_w[13:2]} > entries_cmp[15 -1:0]); +assign dat_req_dummy = is_img_d1[5] ? dat_img_req_dummy : is_winograd_d1[4] ? dat_wg_req_dummy : dat_conv_req_dummy; +assign dat_req_skip = (is_winograd_d1[5] & dat_wg_req_skip) | (is_img_d1[6] & dat_img_req_skip); +assign dat_req_valid = (dat_exec_valid & ~dat_req_dummy & ~dat_req_skip); +//Add corner case +assign dat_req_sub_c_w = ~is_img_d1[7] ? datain_c_cnt[0] : dl_block_end; +assign dat_req_sub_w_w = is_winograd_d1[6] ? {1'b0, ~datain_w_cur[1]} : datain_w_cur[1:0]; +assign dat_req_sub_w_st_en = dat_exec_valid & (sub_h_cnt == 2'h0); +assign dat_req_batch_index = batch_cnt; +assign dat_req_stripe_st = dl_pvld; +assign dat_req_stripe_end = is_stripe_equal & dat_pipe_valid; +assign dat_req_channel_end = dl_channel_end; +assign dat_req_layer_end = dl_layer_end; +// PKT_PACK_WIRE( nvdla_stripe_info , dat_req_ , dat_req_flag_w ) +assign dat_req_flag_w[4:0] = dat_req_batch_index[4:0]; +assign dat_req_flag_w[5] = dat_req_stripe_st ; +assign dat_req_flag_w[6] = dat_req_stripe_end ; +assign dat_req_flag_w[7] = dat_req_channel_end ; +assign dat_req_flag_w[8] = dat_req_layer_end ; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_req_valid\" -q dat_req_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid\" -d \"dat_req_sub_w_w\" -q dat_req_sub_w_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid\" -d \"sub_h_cnt\" -q dat_req_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"dat_req_sub_c_w\" -q dat_req_sub_c_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"is_last_channel\" -q dat_req_ch_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"dat_req_dummy\" -q dat_req_dummy_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid\" -d \"dl_cur_sub_h\" -q dat_req_cur_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_req_sub_w_st_en\" -d \"dat_req_stripe_st\" -q dat_req_sub_w_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_exec_valid\" -d \"dat_req_flag_w\" -q dat_req_flag_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"dl_dat_release & is_stripe_equal & dat_pipe_valid\" -q dat_req_rls_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"pixel_force_fetch\" -q pixel_force_fetch_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"pixel_force_clr\" -q pixel_force_clr_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_valid_d1 <= 1'b0; + end else begin + dat_req_valid_d1 <= dat_req_valid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_w_d1 <= {2{1'b0}}; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_sub_w_d1 <= dat_req_sub_w_w; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_sub_w_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_h_d1 <= {2{1'b0}}; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_sub_h_d1 <= sub_h_cnt; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_sub_h_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_c_d1 <= 1'b0; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_sub_c_d1 <= dat_req_sub_c_w; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_sub_c_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_ch_end_d1 <= 1'b0; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_ch_end_d1 <= is_last_channel; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_ch_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_dummy_d1 <= 1'b0; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_dummy_d1 <= dat_req_dummy; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_dummy_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_cur_sub_h_d1 <= {2{1'b0}}; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_cur_sub_h_d1 <= dl_cur_sub_h; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_cur_sub_h_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_w_st_d1 <= 1'b0; + end else begin + if ((dat_req_sub_w_st_en) == 1'b1) begin + dat_req_sub_w_st_d1 <= dat_req_stripe_st; + // VCS coverage off + end else if ((dat_req_sub_w_st_en) == 1'b0) begin + end else begin + dat_req_sub_w_st_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_flag_d1 <= {9{1'b0}}; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_flag_d1 <= dat_req_flag_w; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_flag_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_rls_d1 <= 1'b0; + end else begin + if ((dat_exec_valid) == 1'b1) begin + dat_req_rls_d1 <= dl_dat_release & is_stripe_equal & dat_pipe_valid; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + dat_req_rls_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_force_fetch_d1 <= 1'b0; + end else begin + if ((dat_exec_valid) == 1'b1) begin + pixel_force_fetch_d1 <= pixel_force_fetch; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + pixel_force_fetch_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_force_clr_d1 <= 1'b0; + end else begin + if ((dat_exec_valid) == 1'b1) begin + pixel_force_clr_d1 <= pixel_force_clr; + // VCS coverage off + end else if ((dat_exec_valid) == 1'b0) begin + end else begin + pixel_force_clr_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// generate data read address ///// +////////////////////////////////////////////////////////////// +////////////////////////// data read index generator: 1st stage ////////////////////////// +//channel bias, by w_in element +//assign c_bias_add = (~is_img_d1[8] & datain_c_cnt[0]) ? datain_width[12 -1:0] : 12'b0; +assign c_bias_add = (~is_img_d1[8]) ? datain_width[12 -1:0] : 12'b0; +assign {mon_c_bias_w, c_bias_w} = layer_st ? 13'b0 : (is_stripe_end & dl_channel_end) ? 13'b0 : c_bias + c_bias_add; +assign c_bias_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_block_end); +assign c_bias_d1_reg_en = (c_bias != c_bias_d1); +//height bias, by element +assign {mon_h_bias_0_w,h_bias_0_w} = datain_h_cnt[13:0] * h_bias_0_stride; +assign {mon_h_bias_1_w,h_bias_1_w} = dl_h_offset * h_bias_1_stride; +assign {mon_h_bias_2_w,h_bias_2_w} = batch_cnt * h_bias_2_stride; +assign {mon_h_bias_3_w,h_bias_3_w} = layer_st ? 13'b0 :sub_h_cnt * h_bias_3_stride; +assign h_bias_reg_en[0] = dat_exec_valid; +assign h_bias_reg_en[1] = layer_st | (dat_exec_valid & (is_winograd_d1[7] | is_img_d1[9])); +//width bias, by entry in image, by element in feature data +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_1 +assign w_bias_int8 = is_img_d1[10] ? {pixel_w_cur} : //by entry in image + is_winograd_d1[8] ? {1'b0, datain_w_cnt} : + (~is_last_channel | datain_c_cnt[0] | is_winograd_d1[8]) ? {2'b0,datain_w_cur[12:0]} ://by element + {2'b0, datain_w_cur[12:0]}; //by element, last channel and current c is even, atomC=atomM +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_2 +assign w_bias_int8 = is_img_d1[10] ? {pixel_w_cur} : //by entry in image + is_winograd_d1[8] ? {1'b0, datain_w_cnt} : + (~is_last_channel | is_winograd_d1[8]) ? {2'b0,datain_w_cur[12:0]} ://not last channel, by element + (dat_req_bytes > 8'h04) ? {2'b0,datain_w_cur[12:0]} : //last channel & request >1/2*entry + {3'b0, datain_w_cur[12:1]}; //last channel & request<=1/2*entry +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_4 +assign w_bias_int8 = is_img_d1[10] ? {pixel_w_cur} : //by entry in image + is_winograd_d1[8] ? {1'b0, datain_w_cnt} : + (~is_last_channel | is_winograd_d1[8]) ? {2'b0,datain_w_cur[12:0]} ://not last channel, by element + (dat_req_bytes > 8'h04) ? {2'b0,datain_w_cur[12:0]} : //last channel & request >1/2*entry + (dat_req_bytes <= 8'h2) ? {4'b0, datain_w_cur[12:2]} : //last channel & request <=1/4*entry + {3'b0, datain_w_cur[12:1]}; //last channel & (1/4*entry= {1'b0,data_bank, {9{1'b0}}}); //only one case: 0-1=ffff would introduce wrap +assign dat_req_addr_minus1_wrap = {1'b0,data_bank, {9{1'b1}}}; +assign dat_req_addr_minus1_real = is_dat_req_addr_minus1_wrap ? dat_req_addr_minus1_wrap : dat_req_addr_minus1; +assign sc2buf_dat_rd_en_w = dat_req_valid_d1 & ((dat_req_addr_last != dat_req_addr_w) | pixel_force_fetch_d1); +assign dat_req_addr_last = (dat_req_sub_h_d1 == 2'h0) ? dat_req_sub_h_0_addr : + (dat_req_sub_h_d1 == 2'h1) ? dat_req_sub_h_1_addr : + (dat_req_sub_h_d1 == 2'h2) ? dat_req_sub_h_2_addr : + dat_req_sub_h_3_addr; +assign dat_req_sub_h_0_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h0)); +assign dat_req_sub_h_1_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h1)); +assign dat_req_sub_h_2_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h2)); +assign dat_req_sub_h_3_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h3)); +`ifdef CBUF_BANK_RAM_CASE0 +wire sc2buf_dat_rd_next1_en = 1'b0; +`endif +`ifdef CBUF_BANK_RAM_CASE1 +wire sc2buf_dat_rd_next1_en = 1'b0; +`endif +`ifdef CBUF_BANK_RAM_CASE4 +wire sc2buf_dat_rd_next1_en = 1'b0; +`endif +`ifdef CBUF_BANK_RAM_CASE2 +wire [7 -1:0] sc2buf_dat_rd_shift_w; +wire mon_sc2buf_dat_rd_shift_w; +wire sc2buf_dat_rd_next1_en_w; +wire [14 -1:0] dat_req_addr_last_plus1; +wire [14 -1:0] dat_req_addr_last_plus1_real; +wire is_dat_req_addr_last_plus1_wrap; +wire [14 -1:0] dat_req_addr_last_plus1_wrap; +wire mon_dat_req_addr_last_plus1_wrap; +wire [3:0] pixel_w_cnt_plus1; +wire stripe_begin_disable_jump_w; +//every stripe will start form the head Byte of an entry, no need to jump +assign stripe_begin_disable_jump_w = sub_h_total_g0[2] ? (stripe_cnt[6:2]==5'b0) : //stripe_cnt = 0/1/2/3 + sub_h_total_g0[1] ? (stripe_cnt[6:1]==6'b0) : //stripe_cnt = 0/1 + stripe_cnt==7'b0; //stripe_cnt = 0 +//: my $kk= 3 +1; +//: &eperl::flop("-q stripe_begin_disable_jump -d stripe_begin_disable_jump_w"); +//: &eperl::flop("-wid ${kk} -q pixel_w_cnt_plus1_d1 -d pixel_w_cnt_plus1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg stripe_begin_disable_jump; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stripe_begin_disable_jump <= 'b0; + end else begin + stripe_begin_disable_jump <= stripe_begin_disable_jump_w; + end +end +reg [3:0] pixel_w_cnt_plus1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pixel_w_cnt_plus1_d1 <= 'b0; + end else begin + pixel_w_cnt_plus1_d1 <= pixel_w_cnt_plus1; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_req_addr_last_plus1 = dat_req_addr_last+1'b1; +assign is_dat_req_addr_last_plus1_wrap = (dat_req_addr_last_plus1 >= {data_bank, {9{1'b0}}}); +assign {mon_dat_req_addr_last_plus1_wrap,dat_req_addr_last_plus1_wrap} = dat_req_addr_last_plus1[14 -1:0] - {data_bank, {9{1'b0}}}; +assign dat_req_addr_last_plus1_real = is_dat_req_addr_last_plus1_wrap ? dat_req_addr_last_plus1_wrap : dat_req_addr_last_plus1; +//iamge data may encounter read jump, which happens when image data_read_address - last_rd_address >= 2 entries, and read form the middle of an entry. +//then csc need read 2 entries simultaneously, then shift out unneeded part. +//this address jump should not happened in the begining of a stripe OP. +//assign sc2buf_dat_rd_next1_en_w = is_img_d1[10]&&sc2buf_dat_rd_en_w&&(pixel_x_byte_stride > 8'h08 )&&(dat_req_addr_w != dat_req_addr_last_plus1_real) +// &&(pixel_w_cnt_plus1_d1 8'h08 ) + &&(pixel_w_cnt_plus1_d1 dat_req_pipe_bytes)&&(pixel_x_byte_stride > 8'h08 )? +// pixel_w_cnt_plus1_d1[3:0] - dat_req_pipe_bytes : +// is_img_d1[10]&&(pixel_w_cnt_plus1_d1[3:0]<= dat_req_pipe_bytes)? {7{1'd0}} : +// {7{1'd0}}; //read data, no need to shift +//only when pixel_stride>entry and fetched more data than needed, then need shift +assign {mon_sc2buf_dat_rd_shift_w, sc2buf_dat_rd_shift_w} = + sc2buf_dat_rd_next1_en_w ? pixel_w_cnt_plus1_d1[3 -1:0]+ 7'h08 - dat_req_pipe_bytes: //image read jump +//image read no jump, not image's start,fetch more than needed,not y_ext,then not all bytes are used,need shift out low bytes + is_img_d1[10]&&(pixel_w_cnt_plus1_d1[3:0]> dat_req_pipe_bytes[3:0])&&(~stripe_begin_disable_jump)&&(pixel_x_byte_stride > 8'h08 )? + pixel_w_cnt_plus1_d1[3:0] - dat_req_pipe_bytes[3:0] : {7{1'd0}}; +//: my $kk= 7; +//: &eperl::flop("-d sc2buf_dat_rd_next1_en_w -q sc2buf_dat_rd_next1_en"); +//: &eperl::flop("-d sc2buf_dat_rd_shift_w -q sc2buf_dat_rd_shift -wid ${kk}"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg sc2buf_dat_rd_next1_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_dat_rd_next1_en <= 'b0; + end else begin + sc2buf_dat_rd_next1_en <= sc2buf_dat_rd_next1_en_w; + end +end +reg [6:0] sc2buf_dat_rd_shift; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_dat_rd_shift <= 'b0; + end else begin + sc2buf_dat_rd_shift <= sc2buf_dat_rd_shift_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`endif +wire [14 -1:0] sc2buf_dat_rd_addr_w; +wire [14 -1:0] sc2buf_dat_rd_next1_addr_w; +assign sc2buf_dat_rd_addr_w = sc2buf_dat_rd_next1_en_w ? dat_req_addr_minus1_real : dat_req_addr_w; +assign sc2buf_dat_rd_next1_addr_w = sc2buf_dat_rd_next1_en_w ? dat_req_addr_w : {14{1'b0}}; +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_0_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_0_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_1_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_1_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_2_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_2_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_3_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_3_addr"); +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2buf_dat_rd_en_w\" -q sc2buf_dat_rd_en"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"layer_st | sc2buf_dat_rd_en_w\" -d \"sc2buf_dat_rd_addr_w\" -q sc2buf_dat_rd_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"layer_st | sc2buf_dat_rd_en_w\" -d \"sc2buf_dat_rd_next1_addr_w\" -q sc2buf_dat_rd_next1_addr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pipe_valid_d1\" -q dat_pipe_valid_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_exec_valid_d1\" -q dat_exec_valid_d2"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_w_d1\" -q dat_req_sub_w_d2"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_h_d1\" -q dat_req_sub_h_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_c_d1\" -q dat_req_sub_c_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_ch_end_d1\" -q dat_req_ch_end_d2"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_bytes_d1\" -q dat_req_bytes_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_dummy_d1\" -q dat_req_dummy_d2"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_cur_sub_h_d1\" -q dat_req_cur_sub_h_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_w_st_d1\" -q dat_req_sub_w_st_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_rls_d1\" -q dat_req_rls_d2"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_flag_d1\" -q dat_req_flag_d2"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_h_0_addr <= {14{1'b1}}; + end else begin + if ((dat_req_sub_h_0_addr_en) == 1'b1) begin + dat_req_sub_h_0_addr <= dat_req_addr_w; + // VCS coverage off + end else if ((dat_req_sub_h_0_addr_en) == 1'b0) begin + end else begin + dat_req_sub_h_0_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_h_1_addr <= {14{1'b1}}; + end else begin + if ((dat_req_sub_h_1_addr_en) == 1'b1) begin + dat_req_sub_h_1_addr <= dat_req_addr_w; + // VCS coverage off + end else if ((dat_req_sub_h_1_addr_en) == 1'b0) begin + end else begin + dat_req_sub_h_1_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_h_2_addr <= {14{1'b1}}; + end else begin + if ((dat_req_sub_h_2_addr_en) == 1'b1) begin + dat_req_sub_h_2_addr <= dat_req_addr_w; + // VCS coverage off + end else if ((dat_req_sub_h_2_addr_en) == 1'b0) begin + end else begin + dat_req_sub_h_2_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_h_3_addr <= {14{1'b1}}; + end else begin + if ((dat_req_sub_h_3_addr_en) == 1'b1) begin + dat_req_sub_h_3_addr <= dat_req_addr_w; + // VCS coverage off + end else if ((dat_req_sub_h_3_addr_en) == 1'b0) begin + end else begin + dat_req_sub_h_3_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_dat_rd_en <= 1'b0; + end else begin + sc2buf_dat_rd_en <= sc2buf_dat_rd_en_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_dat_rd_addr <= {14{1'b1}}; + end else begin + if ((layer_st | sc2buf_dat_rd_en_w) == 1'b1) begin + sc2buf_dat_rd_addr <= sc2buf_dat_rd_addr_w; + // VCS coverage off + end else if ((layer_st | sc2buf_dat_rd_en_w) == 1'b0) begin + end else begin + sc2buf_dat_rd_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_dat_rd_next1_addr <= {14{1'b1}}; + end else begin + if ((layer_st | sc2buf_dat_rd_en_w) == 1'b1) begin + sc2buf_dat_rd_next1_addr <= sc2buf_dat_rd_next1_addr_w; + // VCS coverage off + end else if ((layer_st | sc2buf_dat_rd_en_w) == 1'b0) begin + end else begin + sc2buf_dat_rd_next1_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pipe_valid_d2 <= 1'b0; + end else begin + dat_pipe_valid_d2 <= dat_pipe_valid_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_exec_valid_d2 <= 1'b0; + end else begin + dat_exec_valid_d2 <= dat_exec_valid_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_w_d2 <= {2{1'b0}}; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_sub_w_d2 <= dat_req_sub_w_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_sub_w_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_h_d2 <= {2{1'b0}}; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_sub_h_d2 <= dat_req_sub_h_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_sub_h_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_c_d2 <= 1'b0; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_sub_c_d2 <= dat_req_sub_c_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_sub_c_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_ch_end_d2 <= 1'b0; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_ch_end_d2 <= dat_req_ch_end_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_ch_end_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_bytes_d2 <= {8{1'b0}}; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_bytes_d2 <= dat_req_bytes_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_bytes_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_dummy_d2 <= 1'b0; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_dummy_d2 <= dat_req_dummy_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_dummy_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_cur_sub_h_d2 <= {2{1'b0}}; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_cur_sub_h_d2 <= dat_req_cur_sub_h_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_cur_sub_h_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_sub_w_st_d2 <= 1'b0; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_sub_w_st_d2 <= dat_req_sub_w_st_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_sub_w_st_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_rls_d2 <= 1'b0; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_rls_d2 <= dat_req_rls_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_rls_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_req_flag_d2 <= {9{1'b0}}; + end else begin + if ((dat_exec_valid_d1) == 1'b1) begin + dat_req_flag_d2 <= dat_req_flag_d1; + // VCS coverage off + end else if ((dat_exec_valid_d1) == 1'b0) begin + end else begin + dat_req_flag_d2 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// sideband pipeline ///// +////////////////////////////////////////////////////////////// +assign dat_req_pipe_pvld = dat_pipe_valid_d2; +assign dat_req_pipe_sub_w = dat_req_sub_w_d2; +assign dat_req_pipe_sub_h = dat_req_sub_h_d2; +assign dat_req_pipe_sub_c = dat_req_sub_c_d2; +assign dat_req_pipe_ch_end = dat_req_ch_end_d2; +assign dat_req_pipe_bytes = dat_req_bytes_d2; +assign dat_req_pipe_dummy = dat_req_dummy_d2; +assign dat_req_pipe_cur_sub_h = dat_req_cur_sub_h_d2; +assign dat_req_pipe_sub_w_st = dat_req_sub_w_st_d2; +assign dat_req_pipe_rls = dat_req_rls_d2; +assign dat_req_pipe_flag = dat_req_flag_d2; +assign dat_req_exec_pvld = dat_exec_valid_d2; +assign dat_req_exec_dummy = dat_req_dummy_d2; +assign dat_req_exec_sub_h = dat_req_sub_h_d2; +// PKT_PACK_WIRE( csc_dat_req_pkg , dat_req_pipe_ , dat_req_pipe_pd ) +assign dat_req_pipe_pd[1:0] = dat_req_pipe_sub_w[1:0]; +assign dat_req_pipe_pd[3:2] = dat_req_pipe_sub_h[1:0]; +assign dat_req_pipe_pd[4] = dat_req_pipe_sub_c ; +assign dat_req_pipe_pd[5] = dat_req_pipe_ch_end ; +assign dat_req_pipe_pd[6] = 1'b0 ; +assign dat_req_pipe_pd[14:7] = dat_req_pipe_bytes[7:0]; +assign dat_req_pipe_pd[16:15] = dat_req_pipe_cur_sub_h[1:0]; +assign dat_req_pipe_pd[17] = dat_req_pipe_dummy ; +assign dat_req_pipe_pd[18] = dat_req_pipe_sub_w_st ; +assign dat_req_pipe_pd[19] = dat_req_pipe_rls ; +assign dat_req_pipe_pd[28:20] = dat_req_pipe_flag[8:0]; +//add latency for data request contorl signal +//: my $pipe_depth = 6; +//: my $i; +//: my $j; +//: if($pipe_depth == 0) { +//: print "assign dat_rsp_pipe_pvld = dat_req_pipe_pvld;\n"; +//: print "assign dat_rsp_pipe_pd = dat_req_pipe_pd;\n"; +//: print "assign dat_rsp_exec_pvld = dat_req_exec_pvld;\n"; +//: print "assign dat_rsp_exec_dummy = dat_req_exec_dummy;\n"; +//: print "assign dat_rsp_exec_sub_h = dat_req_exec_sub_h;\n\n"; +//: } else { +//: print "assign dat_rsp_pipe_pvld_d0 = dat_req_pipe_pvld;\n"; +//: print "assign dat_rsp_pipe_pd_d0 = dat_req_pipe_pd;\n"; +//: print "assign dat_rsp_exec_pvld_d0 = dat_req_exec_pvld;\n"; +//: print "assign dat_rsp_exec_dummy_d0 = dat_req_exec_dummy;\n"; +//: print "assign dat_rsp_exec_sub_h_d0 = dat_req_exec_sub_h;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dat_rsp_pipe_pvld_d${i}\" -q dat_rsp_pipe_pvld_d${j}"); +//: &eperl::flop("-wid 29 -rval \"{29{1'b0}}\" -en \"dat_rsp_pipe_pvld_d${i}\" -d \"dat_rsp_pipe_pd_d${i}\" -q dat_rsp_pipe_pd_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dat_rsp_exec_pvld_d${i}\" -q dat_rsp_exec_pvld_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"dat_rsp_exec_pvld_d${i}\" -d \"dat_rsp_exec_dummy_d${i}\" -q dat_rsp_exec_dummy_d${j}"); +//: &eperl::flop("-wid 2 -rval \"{2{1'b0}}\" -en \"dat_rsp_exec_pvld_d${i}\" -d \"dat_rsp_exec_sub_h_d${i}\" -q dat_rsp_exec_sub_h_d${j}"); +//: } +//: print "assign dat_rsp_pipe_pvld = dat_rsp_pipe_pvld_d${i};\n"; +//: print "assign dat_rsp_pipe_pd = dat_rsp_pipe_pd_d${i};\n"; +//: print "assign dat_rsp_exec_pvld = dat_rsp_exec_pvld_d${i};\n"; +//: print "assign dat_rsp_exec_dummy = dat_rsp_exec_dummy_d${i};\n"; +//: print "assign dat_rsp_exec_sub_h = dat_rsp_exec_sub_h_d${i};\n\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_rsp_pipe_pvld_d0 = dat_req_pipe_pvld; +assign dat_rsp_pipe_pd_d0 = dat_req_pipe_pd; +assign dat_rsp_exec_pvld_d0 = dat_req_exec_pvld; +assign dat_rsp_exec_dummy_d0 = dat_req_exec_dummy; +assign dat_rsp_exec_sub_h_d0 = dat_req_exec_sub_h; + +reg dat_rsp_pipe_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pvld_d1 <= 1'b0; + end else begin + dat_rsp_pipe_pvld_d1 <= dat_rsp_pipe_pvld_d0; + end +end +reg [28:0] dat_rsp_pipe_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pd_d1 <= {29{1'b0}}; + end else begin + if ((dat_rsp_pipe_pvld_d0) == 1'b1) begin + dat_rsp_pipe_pd_d1 <= dat_rsp_pipe_pd_d0; + // VCS coverage off + end else if ((dat_rsp_pipe_pvld_d0) == 1'b0) begin + end else begin + dat_rsp_pipe_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_exec_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_pvld_d1 <= 1'b0; + end else begin + dat_rsp_exec_pvld_d1 <= dat_rsp_exec_pvld_d0; + end +end +reg dat_rsp_exec_dummy_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_dummy_d1 <= 1'b0; + end else begin + if ((dat_rsp_exec_pvld_d0) == 1'b1) begin + dat_rsp_exec_dummy_d1 <= dat_rsp_exec_dummy_d0; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d0) == 1'b0) begin + end else begin + dat_rsp_exec_dummy_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] dat_rsp_exec_sub_h_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_sub_h_d1 <= {2{1'b0}}; + end else begin + if ((dat_rsp_exec_pvld_d0) == 1'b1) begin + dat_rsp_exec_sub_h_d1 <= dat_rsp_exec_sub_h_d0; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d0) == 1'b0) begin + end else begin + dat_rsp_exec_sub_h_d1 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_pipe_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pvld_d2 <= 1'b0; + end else begin + dat_rsp_pipe_pvld_d2 <= dat_rsp_pipe_pvld_d1; + end +end +reg [28:0] dat_rsp_pipe_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pd_d2 <= {29{1'b0}}; + end else begin + if ((dat_rsp_pipe_pvld_d1) == 1'b1) begin + dat_rsp_pipe_pd_d2 <= dat_rsp_pipe_pd_d1; + // VCS coverage off + end else if ((dat_rsp_pipe_pvld_d1) == 1'b0) begin + end else begin + dat_rsp_pipe_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_exec_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_pvld_d2 <= 1'b0; + end else begin + dat_rsp_exec_pvld_d2 <= dat_rsp_exec_pvld_d1; + end +end +reg dat_rsp_exec_dummy_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_dummy_d2 <= 1'b0; + end else begin + if ((dat_rsp_exec_pvld_d1) == 1'b1) begin + dat_rsp_exec_dummy_d2 <= dat_rsp_exec_dummy_d1; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d1) == 1'b0) begin + end else begin + dat_rsp_exec_dummy_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] dat_rsp_exec_sub_h_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_sub_h_d2 <= {2{1'b0}}; + end else begin + if ((dat_rsp_exec_pvld_d1) == 1'b1) begin + dat_rsp_exec_sub_h_d2 <= dat_rsp_exec_sub_h_d1; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d1) == 1'b0) begin + end else begin + dat_rsp_exec_sub_h_d2 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_pipe_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pvld_d3 <= 1'b0; + end else begin + dat_rsp_pipe_pvld_d3 <= dat_rsp_pipe_pvld_d2; + end +end +reg [28:0] dat_rsp_pipe_pd_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pd_d3 <= {29{1'b0}}; + end else begin + if ((dat_rsp_pipe_pvld_d2) == 1'b1) begin + dat_rsp_pipe_pd_d3 <= dat_rsp_pipe_pd_d2; + // VCS coverage off + end else if ((dat_rsp_pipe_pvld_d2) == 1'b0) begin + end else begin + dat_rsp_pipe_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_exec_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_pvld_d3 <= 1'b0; + end else begin + dat_rsp_exec_pvld_d3 <= dat_rsp_exec_pvld_d2; + end +end +reg dat_rsp_exec_dummy_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_dummy_d3 <= 1'b0; + end else begin + if ((dat_rsp_exec_pvld_d2) == 1'b1) begin + dat_rsp_exec_dummy_d3 <= dat_rsp_exec_dummy_d2; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d2) == 1'b0) begin + end else begin + dat_rsp_exec_dummy_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] dat_rsp_exec_sub_h_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_sub_h_d3 <= {2{1'b0}}; + end else begin + if ((dat_rsp_exec_pvld_d2) == 1'b1) begin + dat_rsp_exec_sub_h_d3 <= dat_rsp_exec_sub_h_d2; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d2) == 1'b0) begin + end else begin + dat_rsp_exec_sub_h_d3 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_pipe_pvld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pvld_d4 <= 1'b0; + end else begin + dat_rsp_pipe_pvld_d4 <= dat_rsp_pipe_pvld_d3; + end +end +reg [28:0] dat_rsp_pipe_pd_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pd_d4 <= {29{1'b0}}; + end else begin + if ((dat_rsp_pipe_pvld_d3) == 1'b1) begin + dat_rsp_pipe_pd_d4 <= dat_rsp_pipe_pd_d3; + // VCS coverage off + end else if ((dat_rsp_pipe_pvld_d3) == 1'b0) begin + end else begin + dat_rsp_pipe_pd_d4 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_exec_pvld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_pvld_d4 <= 1'b0; + end else begin + dat_rsp_exec_pvld_d4 <= dat_rsp_exec_pvld_d3; + end +end +reg dat_rsp_exec_dummy_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_dummy_d4 <= 1'b0; + end else begin + if ((dat_rsp_exec_pvld_d3) == 1'b1) begin + dat_rsp_exec_dummy_d4 <= dat_rsp_exec_dummy_d3; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d3) == 1'b0) begin + end else begin + dat_rsp_exec_dummy_d4 <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] dat_rsp_exec_sub_h_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_sub_h_d4 <= {2{1'b0}}; + end else begin + if ((dat_rsp_exec_pvld_d3) == 1'b1) begin + dat_rsp_exec_sub_h_d4 <= dat_rsp_exec_sub_h_d3; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d3) == 1'b0) begin + end else begin + dat_rsp_exec_sub_h_d4 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_pipe_pvld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pvld_d5 <= 1'b0; + end else begin + dat_rsp_pipe_pvld_d5 <= dat_rsp_pipe_pvld_d4; + end +end +reg [28:0] dat_rsp_pipe_pd_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pd_d5 <= {29{1'b0}}; + end else begin + if ((dat_rsp_pipe_pvld_d4) == 1'b1) begin + dat_rsp_pipe_pd_d5 <= dat_rsp_pipe_pd_d4; + // VCS coverage off + end else if ((dat_rsp_pipe_pvld_d4) == 1'b0) begin + end else begin + dat_rsp_pipe_pd_d5 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_exec_pvld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_pvld_d5 <= 1'b0; + end else begin + dat_rsp_exec_pvld_d5 <= dat_rsp_exec_pvld_d4; + end +end +reg dat_rsp_exec_dummy_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_dummy_d5 <= 1'b0; + end else begin + if ((dat_rsp_exec_pvld_d4) == 1'b1) begin + dat_rsp_exec_dummy_d5 <= dat_rsp_exec_dummy_d4; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d4) == 1'b0) begin + end else begin + dat_rsp_exec_dummy_d5 <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] dat_rsp_exec_sub_h_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_sub_h_d5 <= {2{1'b0}}; + end else begin + if ((dat_rsp_exec_pvld_d4) == 1'b1) begin + dat_rsp_exec_sub_h_d5 <= dat_rsp_exec_sub_h_d4; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d4) == 1'b0) begin + end else begin + dat_rsp_exec_sub_h_d5 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_pipe_pvld_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pvld_d6 <= 1'b0; + end else begin + dat_rsp_pipe_pvld_d6 <= dat_rsp_pipe_pvld_d5; + end +end +reg [28:0] dat_rsp_pipe_pd_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pipe_pd_d6 <= {29{1'b0}}; + end else begin + if ((dat_rsp_pipe_pvld_d5) == 1'b1) begin + dat_rsp_pipe_pd_d6 <= dat_rsp_pipe_pd_d5; + // VCS coverage off + end else if ((dat_rsp_pipe_pvld_d5) == 1'b0) begin + end else begin + dat_rsp_pipe_pd_d6 <= 'bx; + // VCS coverage on + end + end +end +reg dat_rsp_exec_pvld_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_pvld_d6 <= 1'b0; + end else begin + dat_rsp_exec_pvld_d6 <= dat_rsp_exec_pvld_d5; + end +end +reg dat_rsp_exec_dummy_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_dummy_d6 <= 1'b0; + end else begin + if ((dat_rsp_exec_pvld_d5) == 1'b1) begin + dat_rsp_exec_dummy_d6 <= dat_rsp_exec_dummy_d5; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d5) == 1'b0) begin + end else begin + dat_rsp_exec_dummy_d6 <= 'bx; + // VCS coverage on + end + end +end +reg [1:0] dat_rsp_exec_sub_h_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_exec_sub_h_d6 <= {2{1'b0}}; + end else begin + if ((dat_rsp_exec_pvld_d5) == 1'b1) begin + dat_rsp_exec_sub_h_d6 <= dat_rsp_exec_sub_h_d5; + // VCS coverage off + end else if ((dat_rsp_exec_pvld_d5) == 1'b0) begin + end else begin + dat_rsp_exec_sub_h_d6 <= 'bx; + // VCS coverage on + end + end +end +assign dat_rsp_pipe_pvld = dat_rsp_pipe_pvld_d6; +assign dat_rsp_pipe_pd = dat_rsp_pipe_pd_d6; +assign dat_rsp_exec_pvld = dat_rsp_exec_pvld_d6; +assign dat_rsp_exec_dummy = dat_rsp_exec_dummy_d6; +assign dat_rsp_exec_sub_h = dat_rsp_exec_sub_h_d6; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// PKT_UNPACK_WIRE( csc_dat_req_pkg , dat_rsp_pipe_ , dat_rsp_pipe_pd ) +assign dat_rsp_pipe_sub_w[1:0] = dat_rsp_pipe_pd[1:0]; +assign dat_rsp_pipe_sub_h[1:0] = dat_rsp_pipe_pd[3:2]; +assign dat_rsp_pipe_sub_c = dat_rsp_pipe_pd[4]; +assign dat_rsp_pipe_ch_end = dat_rsp_pipe_pd[5]; +assign dat_rsp_pipe_bytes[7:0] = dat_rsp_pipe_pd[14:7]; +assign dat_rsp_pipe_cur_sub_h[1:0] = dat_rsp_pipe_pd[16:15]; +assign dat_rsp_pipe_dummy = dat_rsp_pipe_pd[17]; +assign dat_rsp_pipe_sub_w_st = dat_rsp_pipe_pd[18]; +assign dat_rsp_pipe_rls = dat_rsp_pipe_pd[19]; +assign dat_rsp_pipe_flag[8:0] = dat_rsp_pipe_pd[28:20]; +////////////////////////////////////////////////////////////// +///// dl data cache ///// +////////////////////////////////////////////////////////////// +assign dat_l0c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h0)); +assign dat_l1c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h1)); +assign dat_l2c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h2)); +assign dat_l3c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h3)); +//only winograd/image +assign dat_l0c1_en = (dat_wg_adv & ~dat_rsp_exec_sub_h[0]) | (is_img_d1[12] & dat_l0c0_en & ~dat_l0c0_dummy); +assign dat_l1c1_en = (dat_wg_adv & dat_rsp_exec_sub_h[0]) | (is_img_d1[13] & dat_l1c0_en & ~dat_l1c0_dummy); +assign dat_l2c1_en = (is_img_d1[15] & dat_l2c0_en & ~dat_l2c0_dummy); +assign dat_l3c1_en = (is_img_d1[16] & dat_l3c0_en & ~dat_l3c0_dummy); +assign dat_dummy_l0_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h0); +assign dat_dummy_l1_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h1); +assign dat_dummy_l2_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h2); +assign dat_dummy_l3_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h3); +assign dat_wg_adv = sc2buf_dat_rd_valid & is_winograd_d1[11] & ~dat_rsp_pipe_sub_w_st; +assign dat_l0c0_dummy_w = dat_l0c0_en ? 1'b0 : dat_dummy_l0_en ? 1'b1 : dat_l0c0_dummy; +assign dat_l1c0_dummy_w = dat_l1c0_en ? 1'b0 : dat_dummy_l1_en ? 1'b1 : dat_l1c0_dummy; +assign dat_l2c0_dummy_w = dat_l2c0_en ? 1'b0 : dat_dummy_l2_en ? 1'b1 : dat_l2c0_dummy; +assign dat_l3c0_dummy_w = dat_l3c0_en ? 1'b0 : dat_dummy_l3_en ? 1'b1 : dat_l3c0_dummy; +assign dat_l0c1_dummy_w = dat_l0c1_en ? 1'b0 : (dat_l0_set) ? dat_l0c0_dummy : dat_l0c1_dummy; +assign dat_l1c1_dummy_w = dat_l1c1_en ? 1'b0 : (dat_l1_set & (|sub_h_total_g2)) ? dat_l1c0_dummy : dat_l1c1_dummy; +assign dat_l2c1_dummy_w = dat_l2c1_en ? 1'b0 : (dat_l2_set & sub_h_total_g2[1]) ? dat_l2c0_dummy : dat_l2c1_dummy; +assign dat_l3c1_dummy_w = dat_l3c1_en ? 1'b0 : (dat_l3_set & sub_h_total_g2[1]) ? dat_l3c0_dummy : dat_l3c1_dummy; +assign dat_l0_set = dat_l0c0_en | dat_dummy_l0_en; +assign dat_l1_set = dat_l1c0_en | dat_dummy_l1_en; +assign dat_l2_set = dat_l2c0_en | dat_dummy_l2_en; +assign dat_l3_set = dat_l3c0_en | dat_dummy_l3_en; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l0c0_dummy_w\" -q dat_l0c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l1c0_dummy_w\" -q dat_l1c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l2c0_dummy_w\" -q dat_l2c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l3c0_dummy_w\" -q dat_l3c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l0c1_dummy_w\" -q dat_l0c1_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l1c1_dummy_w\" -q dat_l1c1_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l2c1_dummy_w\" -q dat_l2c1_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l3c1_dummy_w\" -q dat_l3c1_dummy"); +//: &eperl::flop("-nodeclare -norst -en \"dat_l0c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l0c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l1c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l1c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l2c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l2c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l3c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l3c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l0c1_en\" -d dat_l0c0 -q dat_l0c1 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l1c1_en\" -d dat_l1c0 -q dat_l1c1 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l2c1_en\" -d dat_l2c0 -q dat_l2c1 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l3c1_en\" -d dat_l3c0 -q dat_l3c1 "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l0c0_dummy <= 1'b1; + end else begin + dat_l0c0_dummy <= dat_l0c0_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l1c0_dummy <= 1'b1; + end else begin + dat_l1c0_dummy <= dat_l1c0_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l2c0_dummy <= 1'b1; + end else begin + dat_l2c0_dummy <= dat_l2c0_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l3c0_dummy <= 1'b1; + end else begin + dat_l3c0_dummy <= dat_l3c0_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l0c1_dummy <= 1'b1; + end else begin + dat_l0c1_dummy <= dat_l0c1_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l1c1_dummy <= 1'b1; + end else begin + dat_l1c1_dummy <= dat_l1c1_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l2c1_dummy <= 1'b1; + end else begin + dat_l2c1_dummy <= dat_l2c1_dummy_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_l3c1_dummy <= 1'b1; + end else begin + dat_l3c1_dummy <= dat_l3c1_dummy_w; + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l0c0_en) == 1'b1) begin + dat_l0c0 <= sc2buf_dat_rd_data; + // VCS coverage off + end else if ((dat_l0c0_en) == 1'b0) begin + end else begin + dat_l0c0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l1c0_en) == 1'b1) begin + dat_l1c0 <= sc2buf_dat_rd_data; + // VCS coverage off + end else if ((dat_l1c0_en) == 1'b0) begin + end else begin + dat_l1c0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l2c0_en) == 1'b1) begin + dat_l2c0 <= sc2buf_dat_rd_data; + // VCS coverage off + end else if ((dat_l2c0_en) == 1'b0) begin + end else begin + dat_l2c0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l3c0_en) == 1'b1) begin + dat_l3c0 <= sc2buf_dat_rd_data; + // VCS coverage off + end else if ((dat_l3c0_en) == 1'b0) begin + end else begin + dat_l3c0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l0c1_en) == 1'b1) begin + dat_l0c1 <= dat_l0c0; + // VCS coverage off + end else if ((dat_l0c1_en) == 1'b0) begin + end else begin + dat_l0c1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l1c1_en) == 1'b1) begin + dat_l1c1 <= dat_l1c0; + // VCS coverage off + end else if ((dat_l1c1_en) == 1'b0) begin + end else begin + dat_l1c1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l2c1_en) == 1'b1) begin + dat_l2c1 <= dat_l2c0; + // VCS coverage off + end else if ((dat_l2c1_en) == 1'b0) begin + end else begin + dat_l2c1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_l3c1_en) == 1'b1) begin + dat_l3c1 <= dat_l3c0; + // VCS coverage off + end else if ((dat_l3c1_en) == 1'b0) begin + end else begin + dat_l3c1 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// response contorl ///// +////////////////////////////////////////////////////////////// +// PKT_PACK_WIRE( csc_dat_rsp_pkg , dat_rsp_pipe_ , dat_rsp_pd_d0 ) +assign dat_rsp_pd_d0[1:0] = dat_rsp_pipe_sub_w[1:0]; +assign dat_rsp_pd_d0[3:2] = dat_rsp_pipe_sub_h[1:0]; +assign dat_rsp_pd_d0[4] = dat_rsp_pipe_sub_c ; +assign dat_rsp_pd_d0[5] = dat_rsp_pipe_ch_end ; +assign dat_rsp_pd_d0[6] = 1'b0 ; +assign dat_rsp_pd_d0[14:7] = dat_rsp_pipe_bytes[7:0]; +assign dat_rsp_pd_d0[16:15] = dat_rsp_pipe_cur_sub_h[1:0]; +assign dat_rsp_pd_d0[17] = dat_rsp_pipe_rls ; +assign dat_rsp_pd_d0[26:18] = dat_rsp_pipe_flag[8:0]; +//add latency +//: my $delay_depth = 4; +//: my $i; +//: my $j; +//: +//: print "assign dat_rsp_pvld_d0 = dat_rsp_pipe_pvld;\n"; +//: for($i = 0; $i < $delay_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_rsp_pvld_d${i}\" -q dat_rsp_pvld_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{27{1'b0}}\" -en \"dat_rsp_pvld_d${i}\" -d \"dat_rsp_pd_d${i}\" -q dat_rsp_pd_d${j}"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_rsp_pvld_d0 = dat_rsp_pipe_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pvld_d1 <= 1'b0; + end else begin + dat_rsp_pvld_d1 <= dat_rsp_pvld_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pd_d1 <= {27{1'b0}}; + end else begin + if ((dat_rsp_pvld_d0) == 1'b1) begin + dat_rsp_pd_d1 <= dat_rsp_pd_d0; + // VCS coverage off + end else if ((dat_rsp_pvld_d0) == 1'b0) begin + end else begin + dat_rsp_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pvld_d2 <= 1'b0; + end else begin + dat_rsp_pvld_d2 <= dat_rsp_pvld_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pd_d2 <= {27{1'b0}}; + end else begin + if ((dat_rsp_pvld_d1) == 1'b1) begin + dat_rsp_pd_d2 <= dat_rsp_pd_d1; + // VCS coverage off + end else if ((dat_rsp_pvld_d1) == 1'b0) begin + end else begin + dat_rsp_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pvld_d3 <= 1'b0; + end else begin + dat_rsp_pvld_d3 <= dat_rsp_pvld_d2; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pd_d3 <= {27{1'b0}}; + end else begin + if ((dat_rsp_pvld_d2) == 1'b1) begin + dat_rsp_pd_d3 <= dat_rsp_pd_d2; + // VCS coverage off + end else if ((dat_rsp_pvld_d2) == 1'b0) begin + end else begin + dat_rsp_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pvld_d4 <= 1'b0; + end else begin + dat_rsp_pvld_d4 <= dat_rsp_pvld_d3; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pd_d4 <= {27{1'b0}}; + end else begin + if ((dat_rsp_pvld_d3) == 1'b1) begin + dat_rsp_pd_d4 <= dat_rsp_pd_d3; + // VCS coverage off + end else if ((dat_rsp_pvld_d3) == 1'b0) begin + end else begin + dat_rsp_pd_d4 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_rsp_pvld = (sub_h_total_g3[2] & dat_rsp_pvld_d4) | + (sub_h_total_g3[1] & dat_rsp_pvld_d2) | + (sub_h_total_g3[0] & dat_rsp_pvld_d1); +assign dat_rsp_l0_pvld = dat_rsp_pvld_d1; +assign dat_rsp_l1_pvld = dat_rsp_pvld_d2; +assign dat_rsp_l2_pvld = dat_rsp_pvld_d3; +assign dat_rsp_l3_pvld = dat_rsp_pvld_d4; +assign dat_rsp_pd = ({27 {sub_h_total_g4[2]}} & dat_rsp_pd_d4) | + ({27 {sub_h_total_g4[1]}} & dat_rsp_pd_d2) | + ({27 {sub_h_total_g4[0]}} & dat_rsp_pd_d1); +assign dat_rsp_l0_sub_c = dat_rsp_pd_d1[4:4]; +assign dat_rsp_l1_sub_c = dat_rsp_pd_d2[4:4]; +assign dat_rsp_l2_sub_c = dat_rsp_pd_d3[4:4]; +assign dat_rsp_l3_sub_c = dat_rsp_pd_d4[4:4]; +assign dat_rsp_l0_flag = dat_rsp_pd_d1[26:18]; +assign dat_rsp_l1_flag = dat_rsp_pd_d2[26:18]; +assign dat_rsp_l2_flag = dat_rsp_pd_d3[26:18]; +assign dat_rsp_l3_flag = dat_rsp_pd_d4[26:18]; +assign dat_rsp_l0_stripe_end = dat_rsp_l0_flag[6:6]; +assign dat_rsp_l1_stripe_end = dat_rsp_l1_flag[6:6]; +assign dat_rsp_l2_stripe_end = dat_rsp_l2_flag[6:6]; +assign dat_rsp_l3_stripe_end = dat_rsp_l3_flag[6:6]; +// PKT_UNPACK_WIRE( csc_dat_rsp_pkg , dat_rsp_ , dat_rsp_pd ) +assign dat_rsp_sub_w[1:0] = dat_rsp_pd[1:0]; +assign dat_rsp_sub_h[1:0] = dat_rsp_pd[3:2]; +assign dat_rsp_sub_c = dat_rsp_pd[4]; +assign dat_rsp_ch_end = dat_rsp_pd[5]; +assign dat_rsp_bytes[7:0] = dat_rsp_pd[14:7]; +assign dat_rsp_cur_sub_h[1:0] = dat_rsp_pd[16:15]; +assign dat_rsp_rls = dat_rsp_pd[17]; +assign dat_rsp_flag[8:0] = dat_rsp_pd[26:18]; +// PKT_UNPACK_WIRE( nvdla_stripe_info , dat_rsp_ , dat_rsp_flag ) +assign dat_rsp_batch_index[4:0] = dat_rsp_flag[4:0]; +assign dat_rsp_stripe_st = dat_rsp_flag[5]; +assign dat_rsp_stripe_end = dat_rsp_flag[6]; +assign dat_rsp_channel_end = dat_rsp_flag[7]; +assign dat_rsp_layer_end = dat_rsp_flag[8]; +assign rsp_sft_cnt_l0_sub = dat_l0c0_en ? 8'h08 : 8'h0; +assign rsp_sft_cnt_l1_sub = dat_l1c0_en ? 8'h08 : 8'h0; +assign rsp_sft_cnt_l2_sub = dat_l2c0_en ? 8'h08 : 8'h0; +assign rsp_sft_cnt_l3_sub = dat_l3c0_en ? 8'h08 : 8'h0; +////: &eperl::retime("-O stripe_begin_disable_jump_7T -i stripe_begin_disable_jump -stage 8 -clk nvdla_core_clk"); +////: &eperl::flop("-q stripe_begin_disable_jump_8T -d stripe_begin_disable_jump_7T -clk nvdla_core_clk"); +assign {mon_rsp_sft_cnt_l0_w,rsp_sft_cnt_l0_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l0 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l0_sub); +assign {mon_rsp_sft_cnt_l1_w,rsp_sft_cnt_l1_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l1 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l1_sub); +assign {mon_rsp_sft_cnt_l2_w,rsp_sft_cnt_l2_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l2 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l2_sub); +assign {mon_rsp_sft_cnt_l3_w,rsp_sft_cnt_l3_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l3 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l3_sub); +//the data frm cbuf's low Bytes is always needed. High Bytes maybe unneeded. +assign dat_rsp_l0_block_end = dat_rsp_l0_sub_c; +assign dat_rsp_l1_block_end = dat_rsp_l1_sub_c; +assign dat_rsp_l2_block_end = dat_rsp_l2_sub_c; +assign dat_rsp_l3_block_end = dat_rsp_l3_sub_c; +assign rsp_sft_cnt_l0_w = (layer_st) ? 8'h08 : //begin from C0 + (dat_rsp_l0_stripe_end & ~dat_rsp_l0_block_end) ? rsp_sft_cnt_l0_ori : + (dat_rsp_l0_stripe_end & dat_rsp_l0_block_end) ? 8'h08 : + (dat_dummy_l0_en) ? (rsp_sft_cnt_l0_inc & 8'h07) : + rsp_sft_cnt_l0_inc; +assign rsp_sft_cnt_l1_w = (layer_st) ? 8'h08 : + (dat_rsp_l1_stripe_end & ~dat_rsp_l1_block_end) ? rsp_sft_cnt_l1_ori : + (dat_rsp_l1_stripe_end & dat_rsp_l1_block_end) ? 8'h08 : + (dat_dummy_l1_en) ? (rsp_sft_cnt_l1_inc & 8'h07) : + rsp_sft_cnt_l1_inc; +assign rsp_sft_cnt_l2_w = (layer_st) ? 8'h08 : + (dat_rsp_l2_stripe_end & ~dat_rsp_l2_block_end) ? rsp_sft_cnt_l2_ori : + (dat_rsp_l2_stripe_end & dat_rsp_l2_block_end) ? 8'h08 : + (dat_dummy_l2_en) ? (rsp_sft_cnt_l2_inc & 8'h07) : + rsp_sft_cnt_l2_inc; +assign rsp_sft_cnt_l3_w = (layer_st) ? 8'h08 : + (dat_rsp_l3_stripe_end & ~dat_rsp_l3_block_end) ? rsp_sft_cnt_l3_ori : + (dat_rsp_l3_stripe_end & dat_rsp_l3_block_end) ? 8'h08 : + (dat_dummy_l3_en) ? (rsp_sft_cnt_l3_inc & 8'h07) : + rsp_sft_cnt_l3_inc; +assign rsp_sft_cnt_l0_en = layer_st | (is_img_d1[17] & dat_rsp_l0_pvld); +assign rsp_sft_cnt_l1_en = layer_st | (is_img_d1[18] & dat_rsp_l1_pvld & (sub_h_total_g5 != 3'h1)); +assign rsp_sft_cnt_l2_en = layer_st | (is_img_d1[19] & dat_rsp_l2_pvld & (sub_h_total_g5 == 3'h4)); +assign rsp_sft_cnt_l3_en = layer_st | (is_img_d1[20] & dat_rsp_l3_pvld & (sub_h_total_g5 == 3'h4)); +assign rsp_sft_cnt_l0_ori_en = layer_st | (is_img_d1[21] & dat_rsp_l0_pvld & dat_rsp_l0_stripe_end & dat_rsp_l0_block_end); +assign rsp_sft_cnt_l1_ori_en = layer_st | (is_img_d1[22] & dat_rsp_l1_pvld & dat_rsp_l1_stripe_end & dat_rsp_l1_block_end & (sub_h_total_g6 != 3'h1)); +assign rsp_sft_cnt_l2_ori_en = layer_st | (is_img_d1[23] & dat_rsp_l2_pvld & dat_rsp_l2_stripe_end & dat_rsp_l2_block_end & (sub_h_total_g6 == 3'h4)); +assign rsp_sft_cnt_l3_ori_en = layer_st | (is_img_d1[24] & dat_rsp_l3_pvld & dat_rsp_l3_stripe_end & dat_rsp_l3_block_end & (sub_h_total_g6 == 3'h4)); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l0_en\" -d \"rsp_sft_cnt_l0_w\" -q rsp_sft_cnt_l0"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l1_en\" -d \"rsp_sft_cnt_l1_w\" -q rsp_sft_cnt_l1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l2_en\" -d \"rsp_sft_cnt_l2_w\" -q rsp_sft_cnt_l2"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l3_en\" -d \"rsp_sft_cnt_l3_w\" -q rsp_sft_cnt_l3"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l0_ori_en\" -d \"rsp_sft_cnt_l0_w\" -q rsp_sft_cnt_l0_ori"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l1_ori_en\" -d \"rsp_sft_cnt_l1_w\" -q rsp_sft_cnt_l1_ori"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l2_ori_en\" -d \"rsp_sft_cnt_l2_w\" -q rsp_sft_cnt_l2_ori"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l3_ori_en\" -d \"rsp_sft_cnt_l3_w\" -q rsp_sft_cnt_l3_ori"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l0 <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l0_en) == 1'b1) begin + rsp_sft_cnt_l0 <= rsp_sft_cnt_l0_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l0_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l0 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l1 <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l1_en) == 1'b1) begin + rsp_sft_cnt_l1 <= rsp_sft_cnt_l1_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l1_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l2 <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l2_en) == 1'b1) begin + rsp_sft_cnt_l2 <= rsp_sft_cnt_l2_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l2_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l2 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l3 <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l3_en) == 1'b1) begin + rsp_sft_cnt_l3 <= rsp_sft_cnt_l3_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l3_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l3 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l0_ori <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l0_ori_en) == 1'b1) begin + rsp_sft_cnt_l0_ori <= rsp_sft_cnt_l0_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l0_ori_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l0_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l1_ori <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l1_ori_en) == 1'b1) begin + rsp_sft_cnt_l1_ori <= rsp_sft_cnt_l1_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l1_ori_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l1_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l2_ori <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l2_ori_en) == 1'b1) begin + rsp_sft_cnt_l2_ori <= rsp_sft_cnt_l2_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l2_ori_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l2_ori <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rsp_sft_cnt_l3_ori <= {8{1'b0}}; + end else begin + if ((rsp_sft_cnt_l3_ori_en) == 1'b1) begin + rsp_sft_cnt_l3_ori <= rsp_sft_cnt_l3_w; + // VCS coverage off + end else if ((rsp_sft_cnt_l3_ori_en) == 1'b0) begin + end else begin + rsp_sft_cnt_l3_ori <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// response data ///// +////////////////////////////////////////////////////////////// +//////////////// data for winograd //////////////// +//winograd need future update +`ifdef NVDLA_WINOGRAD_ENABLE +//6x6x8byte matrix +assign dat_wg = ~is_winograd_d1[12] ? 2304'b0 : + {dat_l1c0[511:256], dat_l1c1[511:384], + dat_l1c0[255:0], dat_l1c1[255:128], + dat_l0c0[511:256], dat_l0c1[511:384], + dat_l0c0[255:0], dat_l0c1[255:128], + dat_l0c0[511:256], dat_l0c1[511:384], + dat_l0c0[255:0], dat_l0c1[255:128]}; +assign dat_rsp_wg_sel_lt = (~dat_rsp_sub_h[0] & ~dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_lb = (dat_rsp_sub_h[0] & ~dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_rt = (~dat_rsp_sub_h[0] & dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_rb = (dat_rsp_sub_h[0] & dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_8b_lo = ~dat_rsp_sub_c; +assign dat_rsp_wg_sel_8b_hi = dat_rsp_sub_c; +assign dat_rsp_wg_lt = {dat_wg[1535:1280], dat_wg[1151:896], dat_wg[767:512], dat_wg[383:128]}; +assign dat_rsp_wg_lb = {dat_wg[2303:2048], dat_wg[1919:1664], dat_wg[1535:1280], dat_wg[1151:896]}; +assign dat_rsp_wg_rt = {dat_wg[1407:1152], dat_wg[1023:768], dat_wg[639:384], dat_wg[255:0]}; +assign dat_rsp_wg_rb = {dat_wg[2175:1920], dat_wg[1791:1536], dat_wg[1407:1152], dat_wg[1023:768]}; +assign dat_rsp_wg = ({1024{dat_rsp_wg_sel_lt}} & dat_rsp_wg_lt) | + ({1024{dat_rsp_wg_sel_lb}} & dat_rsp_wg_lb) | + ({1024{dat_rsp_wg_sel_rt}} & dat_rsp_wg_rt) | + ({1024{dat_rsp_wg_sel_rb}} & dat_rsp_wg_rb); +`endif +`ifdef NVDLA_PRINT_WINOGRAD +always @ (posedge nvdla_core_clk) +begin + if(dat_rsp_pra_en) + begin + $display("[NVDLA WINOGRAD] data_pre_pra_remap = %01024h", dat_rsp_wg); + $display("[NVDLA WINOGRAD] data_post_pra_remap = %01024h", {dat_rsp_wg_ch3, dat_rsp_wg_ch2, dat_rsp_wg_ch1, dat_rsp_wg_ch0}); + end +end +always @ (posedge nvdla_core_clk) +begin + if(|mon_dat_out_pra_vld) + begin + $display("[NVDLA WINOGRAD] data_pra_out_ch0 = %0256h", dat_pra_dat_ch0); + $display("[NVDLA WINOGRAD] data_pra_out_ch1 = %0256h", dat_pra_dat_ch1); + $display("[NVDLA WINOGRAD] data_pra_out_ch2 = %0256h", dat_pra_dat_ch2); + $display("[NVDLA WINOGRAD] data_pra_out_ch3 = %0256h", dat_pra_dat_ch3); + end +end +assign dat_wg_8b_ch0 = {{8{dat_rsp_wg[15*64+ 7]}}, dat_rsp_wg[15*64+7:15*64], {8{dat_rsp_wg[14*64+ 7]}}, dat_rsp_wg[14*64+7:14*64], {8{dat_rsp_wg[13*64+ 7]}}, dat_rsp_wg[13*64+7:13*64], {8{dat_rsp_wg[12*64+ 7]}}, dat_rsp_wg[12*64+7:12*64], {8{dat_rsp_wg[11*64+ 7]}}, dat_rsp_wg[11*64+7:11*64], {8{dat_rsp_wg[10*64+ 7]}}, dat_rsp_wg[10*64+7:10*64], {8{dat_rsp_wg[9*64+ 7]}}, dat_rsp_wg[9*64+7:9*64], {8{dat_rsp_wg[8*64+ 7]}}, dat_rsp_wg[8*64+7:8*64], {8{dat_rsp_wg[7*64+ 7]}}, dat_rsp_wg[7*64+7:7*64], {8{dat_rsp_wg[6*64+ 7]}}, dat_rsp_wg[6*64+7:6*64], {8{dat_rsp_wg[5*64+ 7]}}, dat_rsp_wg[5*64+7:5*64], {8{dat_rsp_wg[4*64+ 7]}}, dat_rsp_wg[4*64+7:4*64], {8{dat_rsp_wg[3*64+ 7]}}, dat_rsp_wg[3*64+7:3*64], {8{dat_rsp_wg[2*64+ 7]}}, dat_rsp_wg[2*64+7:2*64], {8{dat_rsp_wg[1*64+ 7]}}, dat_rsp_wg[1*64+7:1*64], {8{dat_rsp_wg[0*64+ 7]}}, dat_rsp_wg[0*64+7:0*64]}; +assign dat_wg_8b_ch1 = {{8{dat_rsp_wg[15*64+15]}}, dat_rsp_wg[15*64+15:15*64+8], {8{dat_rsp_wg[14*64+15]}}, dat_rsp_wg[14*64+15:14*64+8], {8{dat_rsp_wg[13*64+15]}}, dat_rsp_wg[13*64+15:13*64+8], {8{dat_rsp_wg[12*64+15]}}, dat_rsp_wg[12*64+15:12*64+8], {8{dat_rsp_wg[11*64+15]}}, dat_rsp_wg[11*64+15:11*64+8], {8{dat_rsp_wg[10*64+15]}}, dat_rsp_wg[10*64+15:10*64+8], {8{dat_rsp_wg[9*64+15]}}, dat_rsp_wg[9*64+15:9*64+8], {8{dat_rsp_wg[8*64+15]}}, dat_rsp_wg[8*64+15:8*64+8], {8{dat_rsp_wg[7*64+15]}}, dat_rsp_wg[7*64+15:7*64+8], {8{dat_rsp_wg[6*64+15]}}, dat_rsp_wg[6*64+15:6*64+8], {8{dat_rsp_wg[5*64+15]}}, dat_rsp_wg[5*64+15:5*64+8], {8{dat_rsp_wg[4*64+15]}}, dat_rsp_wg[4*64+15:4*64+8], {8{dat_rsp_wg[3*64+15]}}, dat_rsp_wg[3*64+15:3*64+8], {8{dat_rsp_wg[2*64+15]}}, dat_rsp_wg[2*64+15:2*64+8], {8{dat_rsp_wg[1*64+15]}}, dat_rsp_wg[1*64+15:1*64+8], {8{dat_rsp_wg[0*64+15]}}, dat_rsp_wg[0*64+15:0*64+8]}; +assign dat_wg_8b_ch2 = {{8{dat_rsp_wg[15*64+23]}}, dat_rsp_wg[15*64+23:15*64+16], {8{dat_rsp_wg[14*64+23]}}, dat_rsp_wg[14*64+23:14*64+16], {8{dat_rsp_wg[13*64+23]}}, dat_rsp_wg[13*64+23:13*64+16], {8{dat_rsp_wg[12*64+23]}}, dat_rsp_wg[12*64+23:12*64+16], {8{dat_rsp_wg[11*64+23]}}, dat_rsp_wg[11*64+23:11*64+16], {8{dat_rsp_wg[10*64+23]}}, dat_rsp_wg[10*64+23:10*64+16], {8{dat_rsp_wg[9*64+23]}}, dat_rsp_wg[9*64+23:9*64+16], {8{dat_rsp_wg[8*64+23]}}, dat_rsp_wg[8*64+23:8*64+16], {8{dat_rsp_wg[7*64+23]}}, dat_rsp_wg[7*64+23:7*64+16], {8{dat_rsp_wg[6*64+23]}}, dat_rsp_wg[6*64+23:6*64+16], {8{dat_rsp_wg[5*64+23]}}, dat_rsp_wg[5*64+23:5*64+16], {8{dat_rsp_wg[4*64+23]}}, dat_rsp_wg[4*64+23:4*64+16], {8{dat_rsp_wg[3*64+23]}}, dat_rsp_wg[3*64+23:3*64+16], {8{dat_rsp_wg[2*64+23]}}, dat_rsp_wg[2*64+23:2*64+16], {8{dat_rsp_wg[1*64+23]}}, dat_rsp_wg[1*64+23:1*64+16], {8{dat_rsp_wg[0*64+23]}}, dat_rsp_wg[0*64+23:0*64+16]}; +assign dat_wg_8b_ch3 = {{8{dat_rsp_wg[15*64+31]}}, dat_rsp_wg[15*64+31:15*64+24], {8{dat_rsp_wg[14*64+31]}}, dat_rsp_wg[14*64+31:14*64+24], {8{dat_rsp_wg[13*64+31]}}, dat_rsp_wg[13*64+31:13*64+24], {8{dat_rsp_wg[12*64+31]}}, dat_rsp_wg[12*64+31:12*64+24], {8{dat_rsp_wg[11*64+31]}}, dat_rsp_wg[11*64+31:11*64+24], {8{dat_rsp_wg[10*64+31]}}, dat_rsp_wg[10*64+31:10*64+24], {8{dat_rsp_wg[9*64+31]}}, dat_rsp_wg[9*64+31:9*64+24], {8{dat_rsp_wg[8*64+31]}}, dat_rsp_wg[8*64+31:8*64+24], {8{dat_rsp_wg[7*64+31]}}, dat_rsp_wg[7*64+31:7*64+24], {8{dat_rsp_wg[6*64+31]}}, dat_rsp_wg[6*64+31:6*64+24], {8{dat_rsp_wg[5*64+31]}}, dat_rsp_wg[5*64+31:5*64+24], {8{dat_rsp_wg[4*64+31]}}, dat_rsp_wg[4*64+31:4*64+24], {8{dat_rsp_wg[3*64+31]}}, dat_rsp_wg[3*64+31:3*64+24], {8{dat_rsp_wg[2*64+31]}}, dat_rsp_wg[2*64+31:2*64+24], {8{dat_rsp_wg[1*64+31]}}, dat_rsp_wg[1*64+31:1*64+24], {8{dat_rsp_wg[0*64+31]}}, dat_rsp_wg[0*64+31:0*64+24]}; +assign dat_wg_8b_ch4 = {{8{dat_rsp_wg[15*64+39]}}, dat_rsp_wg[15*64+39:15*64+32], {8{dat_rsp_wg[14*64+39]}}, dat_rsp_wg[14*64+39:14*64+32], {8{dat_rsp_wg[13*64+39]}}, dat_rsp_wg[13*64+39:13*64+32], {8{dat_rsp_wg[12*64+39]}}, dat_rsp_wg[12*64+39:12*64+32], {8{dat_rsp_wg[11*64+39]}}, dat_rsp_wg[11*64+39:11*64+32], {8{dat_rsp_wg[10*64+39]}}, dat_rsp_wg[10*64+39:10*64+32], {8{dat_rsp_wg[9*64+39]}}, dat_rsp_wg[9*64+39:9*64+32], {8{dat_rsp_wg[8*64+39]}}, dat_rsp_wg[8*64+39:8*64+32], {8{dat_rsp_wg[7*64+39]}}, dat_rsp_wg[7*64+39:7*64+32], {8{dat_rsp_wg[6*64+39]}}, dat_rsp_wg[6*64+39:6*64+32], {8{dat_rsp_wg[5*64+39]}}, dat_rsp_wg[5*64+39:5*64+32], {8{dat_rsp_wg[4*64+39]}}, dat_rsp_wg[4*64+39:4*64+32], {8{dat_rsp_wg[3*64+39]}}, dat_rsp_wg[3*64+39:3*64+32], {8{dat_rsp_wg[2*64+39]}}, dat_rsp_wg[2*64+39:2*64+32], {8{dat_rsp_wg[1*64+39]}}, dat_rsp_wg[1*64+39:1*64+32], {8{dat_rsp_wg[0*64+39]}}, dat_rsp_wg[0*64+39:0*64+32]}; +assign dat_wg_8b_ch5 = {{8{dat_rsp_wg[15*64+47]}}, dat_rsp_wg[15*64+47:15*64+40], {8{dat_rsp_wg[14*64+47]}}, dat_rsp_wg[14*64+47:14*64+40], {8{dat_rsp_wg[13*64+47]}}, dat_rsp_wg[13*64+47:13*64+40], {8{dat_rsp_wg[12*64+47]}}, dat_rsp_wg[12*64+47:12*64+40], {8{dat_rsp_wg[11*64+47]}}, dat_rsp_wg[11*64+47:11*64+40], {8{dat_rsp_wg[10*64+47]}}, dat_rsp_wg[10*64+47:10*64+40], {8{dat_rsp_wg[9*64+47]}}, dat_rsp_wg[9*64+47:9*64+40], {8{dat_rsp_wg[8*64+47]}}, dat_rsp_wg[8*64+47:8*64+40], {8{dat_rsp_wg[7*64+47]}}, dat_rsp_wg[7*64+47:7*64+40], {8{dat_rsp_wg[6*64+47]}}, dat_rsp_wg[6*64+47:6*64+40], {8{dat_rsp_wg[5*64+47]}}, dat_rsp_wg[5*64+47:5*64+40], {8{dat_rsp_wg[4*64+47]}}, dat_rsp_wg[4*64+47:4*64+40], {8{dat_rsp_wg[3*64+47]}}, dat_rsp_wg[3*64+47:3*64+40], {8{dat_rsp_wg[2*64+47]}}, dat_rsp_wg[2*64+47:2*64+40], {8{dat_rsp_wg[1*64+47]}}, dat_rsp_wg[1*64+47:1*64+40], {8{dat_rsp_wg[0*64+47]}}, dat_rsp_wg[0*64+47:0*64+40]}; +assign dat_wg_8b_ch6 = {{8{dat_rsp_wg[15*64+55]}}, dat_rsp_wg[15*64+55:15*64+48], {8{dat_rsp_wg[14*64+55]}}, dat_rsp_wg[14*64+55:14*64+48], {8{dat_rsp_wg[13*64+55]}}, dat_rsp_wg[13*64+55:13*64+48], {8{dat_rsp_wg[12*64+55]}}, dat_rsp_wg[12*64+55:12*64+48], {8{dat_rsp_wg[11*64+55]}}, dat_rsp_wg[11*64+55:11*64+48], {8{dat_rsp_wg[10*64+55]}}, dat_rsp_wg[10*64+55:10*64+48], {8{dat_rsp_wg[9*64+55]}}, dat_rsp_wg[9*64+55:9*64+48], {8{dat_rsp_wg[8*64+55]}}, dat_rsp_wg[8*64+55:8*64+48], {8{dat_rsp_wg[7*64+55]}}, dat_rsp_wg[7*64+55:7*64+48], {8{dat_rsp_wg[6*64+55]}}, dat_rsp_wg[6*64+55:6*64+48], {8{dat_rsp_wg[5*64+55]}}, dat_rsp_wg[5*64+55:5*64+48], {8{dat_rsp_wg[4*64+55]}}, dat_rsp_wg[4*64+55:4*64+48], {8{dat_rsp_wg[3*64+55]}}, dat_rsp_wg[3*64+55:3*64+48], {8{dat_rsp_wg[2*64+55]}}, dat_rsp_wg[2*64+55:2*64+48], {8{dat_rsp_wg[1*64+55]}}, dat_rsp_wg[1*64+55:1*64+48], {8{dat_rsp_wg[0*64+55]}}, dat_rsp_wg[0*64+55:0*64+48]}; +assign dat_wg_8b_ch7 = {{8{dat_rsp_wg[15*64+63]}}, dat_rsp_wg[15*64+63:15*64+56], {8{dat_rsp_wg[14*64+63]}}, dat_rsp_wg[14*64+63:14*64+56], {8{dat_rsp_wg[13*64+63]}}, dat_rsp_wg[13*64+63:13*64+56], {8{dat_rsp_wg[12*64+63]}}, dat_rsp_wg[12*64+63:12*64+56], {8{dat_rsp_wg[11*64+63]}}, dat_rsp_wg[11*64+63:11*64+56], {8{dat_rsp_wg[10*64+63]}}, dat_rsp_wg[10*64+63:10*64+56], {8{dat_rsp_wg[9*64+63]}}, dat_rsp_wg[9*64+63:9*64+56], {8{dat_rsp_wg[8*64+63]}}, dat_rsp_wg[8*64+63:8*64+56], {8{dat_rsp_wg[7*64+63]}}, dat_rsp_wg[7*64+63:7*64+56], {8{dat_rsp_wg[6*64+63]}}, dat_rsp_wg[6*64+63:6*64+56], {8{dat_rsp_wg[5*64+63]}}, dat_rsp_wg[5*64+63:5*64+56], {8{dat_rsp_wg[4*64+63]}}, dat_rsp_wg[4*64+63:4*64+56], {8{dat_rsp_wg[3*64+63]}}, dat_rsp_wg[3*64+63:3*64+56], {8{dat_rsp_wg[2*64+63]}}, dat_rsp_wg[2*64+63:2*64+56], {8{dat_rsp_wg[1*64+63]}}, dat_rsp_wg[1*64+63:1*64+56], {8{dat_rsp_wg[0*64+63]}}, dat_rsp_wg[0*64+63:0*64+56]}; +//winograd need future update +assign dat_rsp_wg_ch0 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch0) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch4); +assign dat_rsp_wg_ch1 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch1) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch5); +assign dat_rsp_wg_ch2 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch2) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch6); +assign dat_rsp_wg_ch3 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch3) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch7); +`endif +//////////////// data for convlution //////////////// +assign dat_rsp_pad_value = {8{pad_value[7:0]}}; +assign dat_rsp_l0c0 = dat_l0c0_dummy ? dat_rsp_pad_value : dat_l0c0; +assign dat_rsp_l1c0 = dat_l1c0_dummy ? dat_rsp_pad_value : dat_l1c0; +assign dat_rsp_l2c0 = dat_l2c0_dummy ? dat_rsp_pad_value : dat_l2c0; +assign dat_rsp_l3c0 = dat_l3c0_dummy ? dat_rsp_pad_value : dat_l3c0; +assign dat_rsp_l0c1 = dat_l0c1_dummy ? dat_rsp_pad_value : dat_l0c1; +assign dat_rsp_l1c1 = dat_l1c1_dummy ? dat_rsp_pad_value : dat_l1c1; +assign dat_rsp_l2c1 = dat_l2c1_dummy ? dat_rsp_pad_value : dat_l2c1; +assign dat_rsp_l3c1 = dat_l3c1_dummy ? dat_rsp_pad_value : dat_l3c1; +//several atomM may combine together as an entry +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_1 +assign dat_rsp_conv_8b = (is_winograd_d1[14] | is_img_d1[26]) ? {64{1'b0}} : + dat_rsp_l0c0; +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_2 +assign dat_rsp_conv_8b = (is_winograd_d1[14] | is_img_d1[26]) ? {64{1'b0}} : +((dat_rsp_bytes <= 8'h04)&((dat_rsp_sub_w[0] == 1'h0))) ? {{64/2{1'b0}}, dat_rsp_l0c0[64/2 -1:0]} : +((dat_rsp_bytes <= 8'h04)&((dat_rsp_sub_w[0] == 1'h1))) ? {{64/2{1'b0}}, dat_rsp_l0c0[64 -1:64/2]} : + dat_rsp_l0c0; +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_4 +assign dat_rsp_conv_8b = (is_winograd_d1[14] | is_img_d1[26]) ? {64{1'b0}} : +((dat_rsp_bytes <= 8'h04)&(dat_rsp_bytes > 8'h2)&((dat_rsp_sub_w[0] == 1'h0))) ? + {{64/2{1'b0}}, dat_rsp_l0c0[64/2 -1:0]} : +((dat_rsp_bytes <= 8'h04)&(dat_rsp_bytes > 8'h2)&((dat_rsp_sub_w[0] == 1'h1))) ? + {{64/2{1'b0}}, dat_rsp_l0c0[64 -1:64/2]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h0)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64/4 -1:0]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h1)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64/2 -1:64/4]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h2)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64*3/4 -1:64/2]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h3)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64 -1:64*3/4]} : +dat_rsp_l0c0; +`endif +assign dat_rsp_conv = dat_rsp_conv_8b; +//////////////// data for image //////////////// +assign dat_rsp_l0_sft_in = ~is_img_d1[27] ? 'b0 : {dat_rsp_l0c0, dat_rsp_l0c1}; +assign dat_rsp_l1_sft_in = ~is_img_d1[28] ? 'b0 : {dat_rsp_l1c0, dat_rsp_l1c1}; +assign dat_rsp_l2_sft_in = ~is_img_d1[29] ? 'b0 : {dat_rsp_l2c0, dat_rsp_l2c1}; +assign dat_rsp_l3_sft_in = ~is_img_d1[30] ? 'b0 : {dat_rsp_l3c0, dat_rsp_l3c1}; +assign {mon_dat_rsp_l0_sft, dat_rsp_l0_sft} = dat_rsp_l0_sft_in >> {rsp_sft_cnt_l0, 3'b0}; +assign {mon_dat_rsp_l1_sft, dat_rsp_l1_sft} = dat_rsp_l1_sft_in >> {rsp_sft_cnt_l1, 3'b0}; +assign {mon_dat_rsp_l2_sft, dat_rsp_l2_sft} = dat_rsp_l2_sft_in >> {rsp_sft_cnt_l2, 3'b0}; +assign {mon_dat_rsp_l3_sft, dat_rsp_l3_sft} = dat_rsp_l3_sft_in >> {rsp_sft_cnt_l3, 3'b0}; +assign dat_rsp_img_8b = (~is_img_d1[32])? 'b0 : + (sub_h_total_g8 == 3'h4) ? {dat_rsp_l3_sft[64/4 -1:0], dat_rsp_l2_sft_d3[64/4 -1:0], dat_rsp_l1_sft_d3[64/4 -1:0], dat_rsp_l0_sft_d3[64/4 -1:0]} : + (sub_h_total_g8 == 3'h2) ? {dat_rsp_l1_sft[64/2 -1:0], dat_rsp_l0_sft_d1[64/2 -1:0]} : + dat_rsp_l0_sft[64 -1:0]; +assign dat_rsp_img = dat_rsp_img_8b; +wire dat_rsp_sft_d1_en = dat_rsp_l0_pvld & (sub_h_total_g9 != 3'h1); +wire dat_rsp_sft_d2_en = dat_rsp_l1_pvld & (sub_h_total_g9 == 3'h4); +wire dat_rsp_sft_d3_en = dat_rsp_l2_pvld & (sub_h_total_g9 == 3'h4); +//: my $half=64/2; +//: my $quat=64/4; +//: &eperl::flop("-nodeclare -wid ${half} -norst -en \"dat_rsp_sft_d1_en\" -d \"dat_rsp_l0_sft\" -q dat_rsp_l0_sft_d1"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d2_en\" -d \"dat_rsp_l0_sft_d1\" -q dat_rsp_l0_sft_d2"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d3_en\" -d \"dat_rsp_l0_sft_d2\" -q dat_rsp_l0_sft_d3"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d2_en\" -d \"dat_rsp_l1_sft\" -q dat_rsp_l1_sft_d2"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d3_en\" -d \"dat_rsp_l1_sft_d2\" -q dat_rsp_l1_sft_d3"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d3_en\" -d \"dat_rsp_l2_sft\" -q dat_rsp_l2_sft_d3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_sft_d1_en) == 1'b1) begin + dat_rsp_l0_sft_d1 <= dat_rsp_l0_sft; + // VCS coverage off + end else if ((dat_rsp_sft_d1_en) == 1'b0) begin + end else begin + dat_rsp_l0_sft_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_sft_d2_en) == 1'b1) begin + dat_rsp_l0_sft_d2 <= dat_rsp_l0_sft_d1; + // VCS coverage off + end else if ((dat_rsp_sft_d2_en) == 1'b0) begin + end else begin + dat_rsp_l0_sft_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_sft_d3_en) == 1'b1) begin + dat_rsp_l0_sft_d3 <= dat_rsp_l0_sft_d2; + // VCS coverage off + end else if ((dat_rsp_sft_d3_en) == 1'b0) begin + end else begin + dat_rsp_l0_sft_d3 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_sft_d2_en) == 1'b1) begin + dat_rsp_l1_sft_d2 <= dat_rsp_l1_sft; + // VCS coverage off + end else if ((dat_rsp_sft_d2_en) == 1'b0) begin + end else begin + dat_rsp_l1_sft_d2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_sft_d3_en) == 1'b1) begin + dat_rsp_l1_sft_d3 <= dat_rsp_l1_sft_d2; + // VCS coverage off + end else if ((dat_rsp_sft_d3_en) == 1'b0) begin + end else begin + dat_rsp_l1_sft_d3 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_sft_d3_en) == 1'b1) begin + dat_rsp_l2_sft_d3 <= dat_rsp_l2_sft; + // VCS coverage off + end else if ((dat_rsp_sft_d3_en) == 1'b0) begin + end else begin + dat_rsp_l2_sft_d3 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////// byte mask //////////////// +//sub_h_total=2, each sub_h align to 1/2 entry; +//sub_h_total=4, each sub_h align to 1/4 entry; +assign dat_rsp_ori_mask = ~({8{1'b1}} << dat_rsp_bytes); +assign dat_rsp_cur_h_mask_p1 = (dat_rsp_cur_sub_h >= 2'h1) ? {8{1'b1}} : 'b0; +assign dat_rsp_cur_h_mask_p2 = (dat_rsp_cur_sub_h >= 2'h2) ? {8/2{1'b1}} : 'b0; +assign dat_rsp_cur_h_mask_p3 = (dat_rsp_cur_sub_h == 2'h3) ? {8/2{1'b1}} : 'b0; +assign dat_rsp_cur_h_e2_mask_8b = {dat_rsp_cur_h_mask_p1[8/2 -1:0], {8/2{1'b1}}}; +assign dat_rsp_cur_h_e4_mask_8b = {dat_rsp_cur_h_mask_p3[8/4 -1:0], dat_rsp_cur_h_mask_p2[8/4 -1:0], dat_rsp_cur_h_mask_p1[8/4 -1:0], {8/4{1'b1}}}; +assign dat_rsp_mask_8b = (sub_h_total_g11 == 3'h4) ? ({4{dat_rsp_ori_mask[8/4 -1:0]}} & dat_rsp_cur_h_e4_mask_8b) : + (sub_h_total_g11 == 3'h2) ? ({2{dat_rsp_ori_mask[8/2 -1:0]}} & dat_rsp_cur_h_e2_mask_8b) : + dat_rsp_ori_mask[8 -1:0]; +assign dat_rsp_data_w = is_img_d1[33] ? dat_rsp_img : + dat_rsp_conv; +//: my $i; +//: my $b1; +//: my $b0; +//: my $kk=8 -1; +//: print "assign dat_rsp_mask_val_int8 = {"; +//: for($i = ${kk}; $i >= 0; $i --) { +//: $b0 = sprintf("%3d", $i * 8); +//: $b1 = sprintf("%3d", $i * 8 + 7); +//: print "(|dat_rsp_data_w[${b1}:${b0}])"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +//: print "\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_rsp_mask_val_int8 = {(|dat_rsp_data_w[ 63: 56]), (|dat_rsp_data_w[ 55: 48]), (|dat_rsp_data_w[ 47: 40]), (|dat_rsp_data_w[ 39: 32]), (|dat_rsp_data_w[ 31: 24]), (|dat_rsp_data_w[ 23: 16]), (|dat_rsp_data_w[ 15: 8]), (|dat_rsp_data_w[ 7: 0])}; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_rsp_mask_w = (dat_rsp_mask_8b & dat_rsp_mask_val_int8) ; +assign dat_rsp_p1_vld_w = 1'b0; +assign dat_rsp_p0_vld_w = dat_rsp_pvld & ~is_winograd_d1[16]; +////////////////////////////////////////////////////////////// +///// latency register to balance with PRA cell ///// +////////////////////////////////////////////////////////////// +//: my $total_latency = 5; +//: +//: print "assign dat_out_pvld_l0 = dat_rsp_pvld;\n"; +//: print "assign dat_out_flag_l0 = dat_rsp_flag;\n"; +//: for(my $i = 0; $i < $total_latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dat_out_pvld_l${i}\" -q dat_out_pvld_l${j}"); +//: &eperl::flop("-wid 9 -rval \"{9{1'b0}}\" -en \"dat_out_pvld_l${i}\" -d \"dat_out_flag_l${i}\" -q dat_out_flag_l${j}"); +//: } +//: +//: my $k = $total_latency; +//: print "assign dat_out_pvld_w = is_winograd_d1[17] ? dat_out_pvld_l${k} : dat_rsp_pvld;\n"; +//: print "assign dat_out_flag_w = is_winograd_d1[18] ? dat_out_flag_l${k} : dat_rsp_flag;\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat_out_pvld_l0 = dat_rsp_pvld; +assign dat_out_flag_l0 = dat_rsp_flag; +reg dat_out_pvld_l1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_pvld_l1 <= 1'b0; + end else begin + dat_out_pvld_l1 <= dat_out_pvld_l0; + end +end +reg [8:0] dat_out_flag_l1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_flag_l1 <= {9{1'b0}}; + end else begin + if ((dat_out_pvld_l0) == 1'b1) begin + dat_out_flag_l1 <= dat_out_flag_l0; + // VCS coverage off + end else if ((dat_out_pvld_l0) == 1'b0) begin + end else begin + dat_out_flag_l1 <= 'bx; + // VCS coverage on + end + end +end +reg dat_out_pvld_l2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_pvld_l2 <= 1'b0; + end else begin + dat_out_pvld_l2 <= dat_out_pvld_l1; + end +end +reg [8:0] dat_out_flag_l2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_flag_l2 <= {9{1'b0}}; + end else begin + if ((dat_out_pvld_l1) == 1'b1) begin + dat_out_flag_l2 <= dat_out_flag_l1; + // VCS coverage off + end else if ((dat_out_pvld_l1) == 1'b0) begin + end else begin + dat_out_flag_l2 <= 'bx; + // VCS coverage on + end + end +end +reg dat_out_pvld_l3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_pvld_l3 <= 1'b0; + end else begin + dat_out_pvld_l3 <= dat_out_pvld_l2; + end +end +reg [8:0] dat_out_flag_l3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_flag_l3 <= {9{1'b0}}; + end else begin + if ((dat_out_pvld_l2) == 1'b1) begin + dat_out_flag_l3 <= dat_out_flag_l2; + // VCS coverage off + end else if ((dat_out_pvld_l2) == 1'b0) begin + end else begin + dat_out_flag_l3 <= 'bx; + // VCS coverage on + end + end +end +reg dat_out_pvld_l4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_pvld_l4 <= 1'b0; + end else begin + dat_out_pvld_l4 <= dat_out_pvld_l3; + end +end +reg [8:0] dat_out_flag_l4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_flag_l4 <= {9{1'b0}}; + end else begin + if ((dat_out_pvld_l3) == 1'b1) begin + dat_out_flag_l4 <= dat_out_flag_l3; + // VCS coverage off + end else if ((dat_out_pvld_l3) == 1'b0) begin + end else begin + dat_out_flag_l4 <= 'bx; + // VCS coverage on + end + end +end +reg dat_out_pvld_l5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_pvld_l5 <= 1'b0; + end else begin + dat_out_pvld_l5 <= dat_out_pvld_l4; + end +end +reg [8:0] dat_out_flag_l5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_flag_l5 <= {9{1'b0}}; + end else begin + if ((dat_out_pvld_l4) == 1'b1) begin + dat_out_flag_l5 <= dat_out_flag_l4; + // VCS coverage off + end else if ((dat_out_pvld_l4) == 1'b0) begin + end else begin + dat_out_flag_l5 <= 'bx; + // VCS coverage on + end + end +end +assign dat_out_pvld_w = is_winograd_d1[17] ? dat_out_pvld_l5 : dat_rsp_pvld; +assign dat_out_flag_w = is_winograd_d1[18] ? dat_out_flag_l5 : dat_rsp_flag; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_out_bypass_p0_vld_w = dat_rsp_p0_vld_w; +assign dat_out_bypass_mask_w = dat_rsp_mask_w; +assign dat_out_bypass_data_w = dat_rsp_data_w; +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_out_pvld_w\" -q dat_out_pvld"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_out_pvld_w\" -d \"dat_out_flag_w\" -q dat_out_flag"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dat_out_bypass_p0_vld_w\" -d \"dat_out_bypass_mask_w\" -q dat_out_bypass_mask"); +//: for(my $i = 0; $i < 8; $i ++) { +//: my $b0 = $i * 8; +//: my $b1 = $i * 8 + 7; +//: &eperl::flop("-nodeclare -norst -en \"dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[${i}]\" -d \"dat_out_bypass_data_w[${b1}:${b0}]\" -q dat_out_bypass_data[${b1}:${b0}]"); +//: } +//: +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_pvld <= 1'b0; + end else begin + dat_out_pvld <= dat_out_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_flag <= {9{1'b0}}; + end else begin + if ((dat_out_pvld_w) == 1'b1) begin + dat_out_flag <= dat_out_flag_w; + // VCS coverage off + end else if ((dat_out_pvld_w) == 1'b0) begin + end else begin + dat_out_flag <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_out_bypass_mask <= {8{1'b0}}; + end else begin + if ((dat_out_bypass_p0_vld_w) == 1'b1) begin + dat_out_bypass_mask <= dat_out_bypass_mask_w; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w) == 1'b0) begin + end else begin + dat_out_bypass_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[0]) == 1'b1) begin + dat_out_bypass_data[7:0] <= dat_out_bypass_data_w[7:0]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[0]) == 1'b0) begin + end else begin + dat_out_bypass_data[7:0] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[1]) == 1'b1) begin + dat_out_bypass_data[15:8] <= dat_out_bypass_data_w[15:8]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[1]) == 1'b0) begin + end else begin + dat_out_bypass_data[15:8] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[2]) == 1'b1) begin + dat_out_bypass_data[23:16] <= dat_out_bypass_data_w[23:16]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[2]) == 1'b0) begin + end else begin + dat_out_bypass_data[23:16] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[3]) == 1'b1) begin + dat_out_bypass_data[31:24] <= dat_out_bypass_data_w[31:24]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[3]) == 1'b0) begin + end else begin + dat_out_bypass_data[31:24] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[4]) == 1'b1) begin + dat_out_bypass_data[39:32] <= dat_out_bypass_data_w[39:32]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[4]) == 1'b0) begin + end else begin + dat_out_bypass_data[39:32] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[5]) == 1'b1) begin + dat_out_bypass_data[47:40] <= dat_out_bypass_data_w[47:40]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[5]) == 1'b0) begin + end else begin + dat_out_bypass_data[47:40] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[6]) == 1'b1) begin + dat_out_bypass_data[55:48] <= dat_out_bypass_data_w[55:48]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[6]) == 1'b0) begin + end else begin + dat_out_bypass_data[55:48] <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[7]) == 1'b1) begin + dat_out_bypass_data[63:56] <= dat_out_bypass_data_w[63:56]; + // VCS coverage off + end else if ((dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[7]) == 1'b0) begin + end else begin + dat_out_bypass_data[63:56] <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef NVDLA_WINOGRAD_ENABLE +////////////////////////////////////////////////////////////// +///// PRA units instance ///// +////////////////////////////////////////////////////////////// +assign dat_rsp_pra_en = dat_rsp_pvld & is_winograd_d1[19]; +assign {pra_truncate_3, pra_truncate_2, pra_truncate_1, pra_truncate_0} = pra_truncate; +assign {pra_precision_3, pra_precision_2, pra_precision_1, pra_precision_0} = pra_precision; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -d \"{4{dat_rsp_pra_en}}\" -q dat_rsp_pra_en_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch0\" -q dat_rsp_wg_ch0_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch1\" -q dat_rsp_wg_ch1_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch2\" -q dat_rsp_wg_ch2_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch3\" -q dat_rsp_wg_ch3_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rsp_pra_en_d1 <= {4{1'b0}}; + end else begin + dat_rsp_pra_en_d1 <= {4{dat_rsp_pra_en}}; + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_pra_en) == 1'b1) begin + dat_rsp_wg_ch0_d1 <= dat_rsp_wg_ch0; + // VCS coverage off + end else if ((dat_rsp_pra_en) == 1'b0) begin + end else begin + dat_rsp_wg_ch0_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_pra_en) == 1'b1) begin + dat_rsp_wg_ch1_d1 <= dat_rsp_wg_ch1; + // VCS coverage off + end else if ((dat_rsp_pra_en) == 1'b0) begin + end else begin + dat_rsp_wg_ch1_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_pra_en) == 1'b1) begin + dat_rsp_wg_ch2_d1 <= dat_rsp_wg_ch2; + // VCS coverage off + end else if ((dat_rsp_pra_en) == 1'b0) begin + end else begin + dat_rsp_wg_ch2_d1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((dat_rsp_pra_en) == 1'b1) begin + dat_rsp_wg_ch3_d1 <= dat_rsp_wg_ch3; + // VCS coverage off + end else if ((dat_rsp_pra_en) == 1'b0) begin + end else begin + dat_rsp_wg_ch3_d1 <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_CSC_pra_cell u_pra_cell_0 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch0_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[0]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[0]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_0[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_0[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch0[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[0]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +NV_NVDLA_CSC_pra_cell u_pra_cell_1 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch1_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[1]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[1]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_1[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_1[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch1[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[1]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +NV_NVDLA_CSC_pra_cell u_pra_cell_2 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch2_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[2]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[2]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_2[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_2[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch2[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[2]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +NV_NVDLA_CSC_pra_cell u_pra_cell_3 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch3_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[3]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[3]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_3[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_3[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch3[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[3]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +assign dat_pra_dat = {dat_pra_dat_ch3, dat_pra_dat_ch2, dat_pra_dat_ch1, dat_pra_dat_ch0}; +assign dat_out_wg_8b = {dat_pra_dat[1015:1008], dat_pra_dat[ 759: 752], dat_pra_dat[ 503: 496], dat_pra_dat[ 247: 240], + dat_pra_dat[ 999: 992], dat_pra_dat[ 743: 736], dat_pra_dat[ 487: 480], dat_pra_dat[ 231: 224], + dat_pra_dat[ 983: 976], dat_pra_dat[ 727: 720], dat_pra_dat[ 471: 464], dat_pra_dat[ 215: 208], + dat_pra_dat[ 967: 960], dat_pra_dat[ 711: 704], dat_pra_dat[ 455: 448], dat_pra_dat[ 199: 192], + dat_pra_dat[ 951: 944], dat_pra_dat[ 695: 688], dat_pra_dat[ 439: 432], dat_pra_dat[ 183: 176], + dat_pra_dat[ 935: 928], dat_pra_dat[ 679: 672], dat_pra_dat[ 423: 416], dat_pra_dat[ 167: 160], + dat_pra_dat[ 919: 912], dat_pra_dat[ 663: 656], dat_pra_dat[ 407: 400], dat_pra_dat[ 151: 144], + dat_pra_dat[ 903: 896], dat_pra_dat[ 647: 640], dat_pra_dat[ 391: 384], dat_pra_dat[ 135: 128], + dat_pra_dat[ 887: 880], dat_pra_dat[ 631: 624], dat_pra_dat[ 375: 368], dat_pra_dat[ 119: 112], + dat_pra_dat[ 871: 864], dat_pra_dat[ 615: 608], dat_pra_dat[ 359: 352], dat_pra_dat[ 103: 96], + dat_pra_dat[ 855: 848], dat_pra_dat[ 599: 592], dat_pra_dat[ 343: 336], dat_pra_dat[ 87: 80], + dat_pra_dat[ 839: 832], dat_pra_dat[ 583: 576], dat_pra_dat[ 327: 320], dat_pra_dat[ 71: 64], + dat_pra_dat[ 823: 816], dat_pra_dat[ 567: 560], dat_pra_dat[ 311: 304], dat_pra_dat[ 55: 48], + dat_pra_dat[ 807: 800], dat_pra_dat[ 551: 544], dat_pra_dat[ 295: 288], dat_pra_dat[ 39: 32], + dat_pra_dat[ 791: 784], dat_pra_dat[ 535: 528], dat_pra_dat[ 279: 272], dat_pra_dat[ 23: 16], + dat_pra_dat[ 775: 768], dat_pra_dat[ 519: 512], dat_pra_dat[ 263: 256], dat_pra_dat[ 7: 0]}; +assign dat_out_wg_data = {2{dat_out_wg_8b}} ; +assign dat_out_wg_mask_int8 = {(|dat_out_wg_data[ 511: 504]), (|dat_out_wg_data[ 503: 496]), (|dat_out_wg_data[ 495: 488]), (|dat_out_wg_data[ 487: 480]), (|dat_out_wg_data[ 479: 472]), (|dat_out_wg_data[ 471: 464]), (|dat_out_wg_data[ 463: 456]), (|dat_out_wg_data[ 455: 448]), + (|dat_out_wg_data[ 447: 440]), (|dat_out_wg_data[ 439: 432]), (|dat_out_wg_data[ 431: 424]), (|dat_out_wg_data[ 423: 416]), (|dat_out_wg_data[ 415: 408]), (|dat_out_wg_data[ 407: 400]), (|dat_out_wg_data[ 399: 392]), (|dat_out_wg_data[ 391: 384]), + (|dat_out_wg_data[ 383: 376]), (|dat_out_wg_data[ 375: 368]), (|dat_out_wg_data[ 367: 360]), (|dat_out_wg_data[ 359: 352]), (|dat_out_wg_data[ 351: 344]), (|dat_out_wg_data[ 343: 336]), (|dat_out_wg_data[ 335: 328]), (|dat_out_wg_data[ 327: 320]), + (|dat_out_wg_data[ 319: 312]), (|dat_out_wg_data[ 311: 304]), (|dat_out_wg_data[ 303: 296]), (|dat_out_wg_data[ 295: 288]), (|dat_out_wg_data[ 287: 280]), (|dat_out_wg_data[ 279: 272]), (|dat_out_wg_data[ 271: 264]), (|dat_out_wg_data[ 263: 256]), + (|dat_out_wg_data[ 255: 248]), (|dat_out_wg_data[ 247: 240]), (|dat_out_wg_data[ 239: 232]), (|dat_out_wg_data[ 231: 224]), (|dat_out_wg_data[ 223: 216]), (|dat_out_wg_data[ 215: 208]), (|dat_out_wg_data[ 207: 200]), (|dat_out_wg_data[ 199: 192]), + (|dat_out_wg_data[ 191: 184]), (|dat_out_wg_data[ 183: 176]), (|dat_out_wg_data[ 175: 168]), (|dat_out_wg_data[ 167: 160]), (|dat_out_wg_data[ 159: 152]), (|dat_out_wg_data[ 151: 144]), (|dat_out_wg_data[ 143: 136]), (|dat_out_wg_data[ 135: 128]), + (|dat_out_wg_data[ 127: 120]), (|dat_out_wg_data[ 119: 112]), (|dat_out_wg_data[ 111: 104]), (|dat_out_wg_data[ 103: 96]), (|dat_out_wg_data[ 95: 88]), (|dat_out_wg_data[ 87: 80]), (|dat_out_wg_data[ 79: 72]), (|dat_out_wg_data[ 71: 64]), + (|dat_out_wg_data[ 63: 56]), (|dat_out_wg_data[ 55: 48]), (|dat_out_wg_data[ 47: 40]), (|dat_out_wg_data[ 39: 32]), (|dat_out_wg_data[ 31: 24]), (|dat_out_wg_data[ 23: 16]), (|dat_out_wg_data[ 15: 8]), (|dat_out_wg_data[ 7: 0])}; +assign dat_out_wg_mask = {2{dat_out_wg_mask_int8}}; +`else +assign dat_out_wg_data = {64{1'b0}}; +assign dat_out_wg_mask = {8{1'b0}}; +`endif +////////////////////////////////////////////////////////////// +///// finial registers ///// +////////////////////////////////////////////////////////////// +assign dat_out_data = is_winograd_d1[20] ? dat_out_wg_data : dat_out_bypass_data; +assign dat_out_mask = ~dat_out_pvld ? 'b0 : is_winograd_d1[21] ? dat_out_wg_mask : dat_out_bypass_mask; +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_out_pvld\" -q dl_out_pvld"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dat_out_pvld | dl_out_pvld\" -d \"dat_out_mask\" -q dl_out_mask"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_out_pvld\" -d \"dat_out_flag\" -q dl_out_flag"); +//: my $i; +//: my $b0; +//: my $b1; +//: my $kk= 8; +//: for($i = 0; $i < 8; $i ++) { +//: $b0 = $i * 8; +//: $b1 = $i * 8 + 7; +//: &eperl::flop("-wid ${kk} -norst -en \"dat_out_mask[$i]\" -d \"dat_out_data[${b1}:${b0}]\" -q dl_out_data${i}"); +//: } +//: print "\n\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_out_pvld <= 1'b0; + end else begin + dl_out_pvld <= dat_out_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_out_mask <= {8{1'b0}}; + end else begin + if ((dat_out_pvld | dl_out_pvld) == 1'b1) begin + dl_out_mask <= dat_out_mask; + // VCS coverage off + end else if ((dat_out_pvld | dl_out_pvld) == 1'b0) begin + end else begin + dl_out_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_out_flag <= {9{1'b0}}; + end else begin + if ((dat_out_pvld) == 1'b1) begin + dl_out_flag <= dat_out_flag; + // VCS coverage off + end else if ((dat_out_pvld) == 1'b0) begin + end else begin + dl_out_flag <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] dl_out_data0; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[0]) == 1'b1) begin + dl_out_data0 <= dat_out_data[7:0]; + // VCS coverage off + end else if ((dat_out_mask[0]) == 1'b0) begin + end else begin + dl_out_data0 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data1; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[1]) == 1'b1) begin + dl_out_data1 <= dat_out_data[15:8]; + // VCS coverage off + end else if ((dat_out_mask[1]) == 1'b0) begin + end else begin + dl_out_data1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data2; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[2]) == 1'b1) begin + dl_out_data2 <= dat_out_data[23:16]; + // VCS coverage off + end else if ((dat_out_mask[2]) == 1'b0) begin + end else begin + dl_out_data2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data3; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[3]) == 1'b1) begin + dl_out_data3 <= dat_out_data[31:24]; + // VCS coverage off + end else if ((dat_out_mask[3]) == 1'b0) begin + end else begin + dl_out_data3 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data4; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[4]) == 1'b1) begin + dl_out_data4 <= dat_out_data[39:32]; + // VCS coverage off + end else if ((dat_out_mask[4]) == 1'b0) begin + end else begin + dl_out_data4 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data5; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[5]) == 1'b1) begin + dl_out_data5 <= dat_out_data[47:40]; + // VCS coverage off + end else if ((dat_out_mask[5]) == 1'b0) begin + end else begin + dl_out_data5 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data6; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[6]) == 1'b1) begin + dl_out_data6 <= dat_out_data[55:48]; + // VCS coverage off + end else if ((dat_out_mask[6]) == 1'b0) begin + end else begin + dl_out_data6 <= 'bx; + // VCS coverage on + end +end +reg [7:0] dl_out_data7; +always @(posedge nvdla_core_clk) begin + if ((dat_out_mask[7]) == 1'b1) begin + dl_out_data7 <= dat_out_data[63:56]; + // VCS coverage off + end else if ((dat_out_mask[7]) == 1'b0) begin + end else begin + dl_out_data7 <= 'bx; + // VCS coverage on + end +end + + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// registers for retiming ///// +////////////////////////////////////////////////////////////// +assign sc2mac_dat_pd_w = ~dl_out_pvld ? 9'b0 : dl_out_flag; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_out_pvld\" -q dl_out_pvld_d1"); +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_out_pvld\" -q sc2mac_dat_a_pvld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_out_pvld\" -q sc2mac_dat_b_pvld"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"sc2mac_dat_pd_w\" -q sc2mac_dat_a_pd"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"sc2mac_dat_pd_w\" -q sc2mac_dat_b_pd"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"dl_out_mask\" -q sc2mac_dat_a_mask"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"dl_out_mask\" -q sc2mac_dat_b_mask"); +//: my $i; +//: for($i = 0; $i < 8; $i ++) { +//: &eperl::flop("-wid 8 -norst -en \"dl_out_mask[${i}]\" -d \"dl_out_data${i}\" -q sc2mac_dat_a_data${i}"); +//: } +//: print "\n\n"; +//: +//: for($i = 0; $i < 8; $i ++) { +//: &eperl::flop("-wid 8 -norst -en \"dl_out_mask[${i}]\" -d \"dl_out_data${i}\" -q sc2mac_dat_b_data${i}"); +//: } +//: print "\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dl_out_pvld_d1 <= 1'b0; + end else begin + dl_out_pvld_d1 <= dl_out_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_a_pvld <= 1'b0; + end else begin + sc2mac_dat_a_pvld <= dl_out_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_b_pvld <= 1'b0; + end else begin + sc2mac_dat_b_pvld <= dl_out_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_a_pd <= {9{1'b0}}; + end else begin + if ((dl_out_pvld | dl_out_pvld_d1) == 1'b1) begin + sc2mac_dat_a_pd <= sc2mac_dat_pd_w; + // VCS coverage off + end else if ((dl_out_pvld | dl_out_pvld_d1) == 1'b0) begin + end else begin + sc2mac_dat_a_pd <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_b_pd <= {9{1'b0}}; + end else begin + if ((dl_out_pvld | dl_out_pvld_d1) == 1'b1) begin + sc2mac_dat_b_pd <= sc2mac_dat_pd_w; + // VCS coverage off + end else if ((dl_out_pvld | dl_out_pvld_d1) == 1'b0) begin + end else begin + sc2mac_dat_b_pd <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_a_mask <= {8{1'b0}}; + end else begin + if ((dl_out_pvld | dl_out_pvld_d1) == 1'b1) begin + sc2mac_dat_a_mask <= dl_out_mask; + // VCS coverage off + end else if ((dl_out_pvld | dl_out_pvld_d1) == 1'b0) begin + end else begin + sc2mac_dat_a_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_b_mask <= {8{1'b0}}; + end else begin + if ((dl_out_pvld | dl_out_pvld_d1) == 1'b1) begin + sc2mac_dat_b_mask <= dl_out_mask; + // VCS coverage off + end else if ((dl_out_pvld | dl_out_pvld_d1) == 1'b0) begin + end else begin + sc2mac_dat_b_mask <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_a_data0; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[0]) == 1'b1) begin + sc2mac_dat_a_data0 <= dl_out_data0; + // VCS coverage off + end else if ((dl_out_mask[0]) == 1'b0) begin + end else begin + sc2mac_dat_a_data0 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data1; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[1]) == 1'b1) begin + sc2mac_dat_a_data1 <= dl_out_data1; + // VCS coverage off + end else if ((dl_out_mask[1]) == 1'b0) begin + end else begin + sc2mac_dat_a_data1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data2; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[2]) == 1'b1) begin + sc2mac_dat_a_data2 <= dl_out_data2; + // VCS coverage off + end else if ((dl_out_mask[2]) == 1'b0) begin + end else begin + sc2mac_dat_a_data2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data3; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[3]) == 1'b1) begin + sc2mac_dat_a_data3 <= dl_out_data3; + // VCS coverage off + end else if ((dl_out_mask[3]) == 1'b0) begin + end else begin + sc2mac_dat_a_data3 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data4; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[4]) == 1'b1) begin + sc2mac_dat_a_data4 <= dl_out_data4; + // VCS coverage off + end else if ((dl_out_mask[4]) == 1'b0) begin + end else begin + sc2mac_dat_a_data4 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data5; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[5]) == 1'b1) begin + sc2mac_dat_a_data5 <= dl_out_data5; + // VCS coverage off + end else if ((dl_out_mask[5]) == 1'b0) begin + end else begin + sc2mac_dat_a_data5 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data6; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[6]) == 1'b1) begin + sc2mac_dat_a_data6 <= dl_out_data6; + // VCS coverage off + end else if ((dl_out_mask[6]) == 1'b0) begin + end else begin + sc2mac_dat_a_data6 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_a_data7; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[7]) == 1'b1) begin + sc2mac_dat_a_data7 <= dl_out_data7; + // VCS coverage off + end else if ((dl_out_mask[7]) == 1'b0) begin + end else begin + sc2mac_dat_a_data7 <= 'bx; + // VCS coverage on + end +end + + +reg [7:0] sc2mac_dat_b_data0; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[0]) == 1'b1) begin + sc2mac_dat_b_data0 <= dl_out_data0; + // VCS coverage off + end else if ((dl_out_mask[0]) == 1'b0) begin + end else begin + sc2mac_dat_b_data0 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data1; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[1]) == 1'b1) begin + sc2mac_dat_b_data1 <= dl_out_data1; + // VCS coverage off + end else if ((dl_out_mask[1]) == 1'b0) begin + end else begin + sc2mac_dat_b_data1 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data2; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[2]) == 1'b1) begin + sc2mac_dat_b_data2 <= dl_out_data2; + // VCS coverage off + end else if ((dl_out_mask[2]) == 1'b0) begin + end else begin + sc2mac_dat_b_data2 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data3; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[3]) == 1'b1) begin + sc2mac_dat_b_data3 <= dl_out_data3; + // VCS coverage off + end else if ((dl_out_mask[3]) == 1'b0) begin + end else begin + sc2mac_dat_b_data3 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data4; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[4]) == 1'b1) begin + sc2mac_dat_b_data4 <= dl_out_data4; + // VCS coverage off + end else if ((dl_out_mask[4]) == 1'b0) begin + end else begin + sc2mac_dat_b_data4 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data5; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[5]) == 1'b1) begin + sc2mac_dat_b_data5 <= dl_out_data5; + // VCS coverage off + end else if ((dl_out_mask[5]) == 1'b0) begin + end else begin + sc2mac_dat_b_data5 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data6; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[6]) == 1'b1) begin + sc2mac_dat_b_data6 <= dl_out_data6; + // VCS coverage off + end else if ((dl_out_mask[6]) == 1'b0) begin + end else begin + sc2mac_dat_b_data6 <= 'bx; + // VCS coverage on + end +end +reg [7:0] sc2mac_dat_b_data7; +always @(posedge nvdla_core_clk) begin + if ((dl_out_mask[7]) == 1'b1) begin + sc2mac_dat_b_data7 <= dl_out_data7; + // VCS coverage off + end else if ((dl_out_mask[7]) == 1'b0) begin + end else begin + sc2mac_dat_b_data7 <= 'bx; + // VCS coverage on + end +end + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifndef SYNTHESIS +//: for(my $i = 0; $i < 8; $i ++) { +//: print "assign dbg_csc_dat_${i} = sc2mac_dat_a_mask[${i}] ? sc2mac_dat_a_data${i} : 8'h0;\n"; +//: } +//: print "\n\n\n\n"; +//: print "assign dbg_csc_dat = {"; +//: my $kk=8; +//: for(my $i = ${kk}-1; $i >= 0; $i --) { +//: print "dbg_csc_dat_${i}"; +//: if($i != 0) { +//: print ", "; +//: } else { +//: print "};\n\n\n"; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dbg_csc_dat_0 = sc2mac_dat_a_mask[0] ? sc2mac_dat_a_data0 : 8'h0; +assign dbg_csc_dat_1 = sc2mac_dat_a_mask[1] ? sc2mac_dat_a_data1 : 8'h0; +assign dbg_csc_dat_2 = sc2mac_dat_a_mask[2] ? sc2mac_dat_a_data2 : 8'h0; +assign dbg_csc_dat_3 = sc2mac_dat_a_mask[3] ? sc2mac_dat_a_data3 : 8'h0; +assign dbg_csc_dat_4 = sc2mac_dat_a_mask[4] ? sc2mac_dat_a_data4 : 8'h0; +assign dbg_csc_dat_5 = sc2mac_dat_a_mask[5] ? sc2mac_dat_a_data5 : 8'h0; +assign dbg_csc_dat_6 = sc2mac_dat_a_mask[6] ? sc2mac_dat_a_data6 : 8'h0; +assign dbg_csc_dat_7 = sc2mac_dat_a_mask[7] ? sc2mac_dat_a_data7 : 8'h0; + + + + +assign dbg_csc_dat = {dbg_csc_dat_7, dbg_csc_dat_6, dbg_csc_dat_5, dbg_csc_dat_4, dbg_csc_dat_3, dbg_csc_dat_2, dbg_csc_dat_1, dbg_csc_dat_0}; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef NVDLA_PRINT_DL +always @ (posedge nvdla_core_clk) +begin + if(layer_st) + begin + $display("[NVDLA DL] layer start"); + end +end +always @ (posedge nvdla_core_clk) +begin + if(sc2mac_dat_a_pvld) + begin + $display("[NVDLA DL] sc2mac_dat = %01024h", dbg_csc_dat); + end +end +`endif +`endif +endmodule // NV_NVDLA_CSC_dl diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v.vcp new file mode 100644 index 0000000..c850f1c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v.vcp @@ -0,0 +1,1929 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_dl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +module NV_NVDLA_CSC_dl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sg2dl_pvld //|< i + ,sg2dl_pd //|< i + ,sc_state //|< i + ,sg2dl_reuse_rls //|< i + ,sc2cdma_dat_pending_req //|< i + ,cdma2sc_dat_updt //|< i + ,cdma2sc_dat_entries //|< i + ,cdma2sc_dat_slices //|< i + ,sc2cdma_dat_updt //|> o + ,sc2cdma_dat_entries //|> o + ,sc2cdma_dat_slices //|> o + ,sc2buf_dat_rd_en //|> o + ,sc2buf_dat_rd_addr //|> o + ,sc2buf_dat_rd_valid //|< i + ,sc2buf_dat_rd_data //|< i + ,sc2buf_dat_rd_shift //|> o + ,sc2buf_dat_rd_next1_en //|> o + ,sc2buf_dat_rd_next1_addr //|> o + ,sc2mac_dat_a_pvld //|> o + ,sc2mac_dat_a_mask //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_a_data${i} //|> o ) +//: } + ,sc2mac_dat_a_pd //|> o + ,sc2mac_dat_b_pvld //|> o + ,sc2mac_dat_b_mask //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_b_data${i} //|> o ) +//: } + ,sc2mac_dat_b_pd //|> o + ,nvdla_core_ng_clk //|< i + ,nvdla_wg_clk //|< i + ,reg2dp_op_en //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_batches //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_skip_data_rls //|< i + ,reg2dp_datain_channel_ext //|< i + ,reg2dp_datain_height_ext //|< i + ,reg2dp_datain_width_ext //|< i + ,reg2dp_y_extension //|< i + ,reg2dp_weight_channel_ext //|< i + ,reg2dp_entries //|< i + ,reg2dp_dataout_width //|< i + ,reg2dp_rls_slices //|< i + ,reg2dp_conv_x_stride_ext //|< i + ,reg2dp_conv_y_stride_ext //|< i + ,reg2dp_x_dilation_ext //|< i + ,reg2dp_y_dilation_ext //|< i + ,reg2dp_pad_left //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_pra_truncate //|< i + ,slcg_wg_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input sg2dl_pvld; /* data valid */ +input [30:0] sg2dl_pd; +input [1:0] sc_state; +input sg2dl_reuse_rls; +input sc2cdma_dat_pending_req; +input cdma2sc_dat_updt; /* data valid */ +input [15 -1:0] cdma2sc_dat_entries; +input [13:0] cdma2sc_dat_slices; +output sc2cdma_dat_updt; /* data valid */ +output [15 -1:0] sc2cdma_dat_entries; +output [13:0] sc2cdma_dat_slices; +output sc2buf_dat_rd_en; /* data valid */ +output [14 -1:0] sc2buf_dat_rd_addr; +input sc2buf_dat_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_dat_rd_data; +output [7 -1:0] sc2buf_dat_rd_shift; +output sc2buf_dat_rd_next1_en; +output [14 -1:0] sc2buf_dat_rd_next1_addr; +output sc2mac_dat_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_a_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_a_data${i}; ) +//: } +output [8:0] sc2mac_dat_a_pd; +output sc2mac_dat_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_b_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_b_data${i}; ) +//: } +output [8:0] sc2mac_dat_b_pd; +input nvdla_core_ng_clk; +input nvdla_wg_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [4:0] reg2dp_batches; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_datain_format; +input [0:0] reg2dp_skip_data_rls; +input [12:0] reg2dp_datain_channel_ext; +input [12:0] reg2dp_datain_height_ext; +input [12:0] reg2dp_datain_width_ext; +input [1:0] reg2dp_y_extension; +input [12:0] reg2dp_weight_channel_ext; +input [13:0] reg2dp_entries; +input [12:0] reg2dp_dataout_width; +input [11:0] reg2dp_rls_slices; +input [2:0] reg2dp_conv_x_stride_ext; +input [2:0] reg2dp_conv_y_stride_ext; +input [4:0] reg2dp_x_dilation_ext; +input [4:0] reg2dp_y_dilation_ext; +input [4:0] reg2dp_pad_left; +input [4:0] reg2dp_pad_top; +input [15:0] reg2dp_pad_value; +input [4:0] reg2dp_data_bank; +input [1:0] reg2dp_pra_truncate; +output slcg_wg_en; +reg [4:0] batch_cmp; +reg [4:0] batch_cnt; +reg [14 -1:0] c_bias; +reg [14 -1:0] c_bias_d1; +reg [3:0] conv_x_stride; +reg [3:0] conv_y_stride; +reg [15 -1:0] dat_entry_avl; +reg [15 -1:0] dat_entry_end; +reg [15 -1:0] dat_entry_st; +reg dat_exec_valid_d1; +reg dat_exec_valid_d2; +reg dat_l0c0_dummy; +reg [64 -1:0] dat_l0c0; +reg dat_l0c1_dummy; +reg [64 -1:0] dat_l0c1; +reg dat_l1c0_dummy; +reg [64 -1:0] dat_l1c0; +reg dat_l1c1_dummy; +reg [64 -1:0] dat_l1c1; +reg dat_l2c0_dummy; +reg [64 -1:0] dat_l2c0; +reg dat_l2c1_dummy; +reg [64 -1:0] dat_l2c1; +reg dat_l3c0_dummy; +reg [64 -1:0] dat_l3c0; +reg dat_l3c1_dummy; +reg [64 -1:0] dat_l3c1; +reg [64 -1:0] dat_out_bypass_data; +reg [8 -1:0] dat_out_bypass_mask; +reg [8:0] dat_out_flag; +reg dat_out_pvld; +reg dat_pipe_local_valid; +reg dat_pipe_valid_d1; +reg dat_pipe_valid_d2; +reg [7:0] dat_req_bytes_d1; +reg [7:0] dat_req_bytes_d2; +reg dat_req_ch_end_d1; +reg dat_req_ch_end_d2; +reg [1:0] dat_req_cur_sub_h_d1; +reg [1:0] dat_req_cur_sub_h_d2; +reg dat_req_dummy_d1; +reg dat_req_dummy_d2; +reg [8:0] dat_req_flag_d1; +reg [8:0] dat_req_flag_d2; +reg dat_req_rls_d1; +reg dat_req_rls_d2; +reg dat_req_sub_c_d1; +reg dat_req_sub_c_d2; +reg [14 -1:0] dat_req_sub_h_0_addr; +reg [14 -1:0] dat_req_sub_h_1_addr; +reg [14 -1:0] dat_req_sub_h_2_addr; +reg [14 -1:0] dat_req_sub_h_3_addr; +reg [1:0] dat_req_sub_h_d1; +reg [1:0] dat_req_sub_h_d2; +reg [1:0] dat_req_sub_w_d1; +reg [1:0] dat_req_sub_w_d2; +reg dat_req_sub_w_st_d1; +reg dat_req_sub_w_st_d2; +reg dat_req_valid_d1; +wire [64 -1:0] dat_rsp_l0_sft; +reg [64 -1:0] dat_rsp_l0_sft_d1; +reg [64 -1:0] dat_rsp_l0_sft_d2; +reg [64 -1:0] dat_rsp_l0_sft_d3; +wire [64 -1:0] dat_rsp_l1_sft; +reg [64 -1:0] dat_rsp_l1_sft_d2; +reg [64 -1:0] dat_rsp_l1_sft_d3; +wire [64 -1:0] dat_rsp_l2_sft; +reg [64 -1:0] dat_rsp_l2_sft_d3; +wire [64 -1:0] dat_rsp_l3_sft; +reg [26:0] dat_rsp_pd_d1; +reg [26:0] dat_rsp_pd_d2; +reg [26:0] dat_rsp_pd_d3; +reg [26:0] dat_rsp_pd_d4; +reg [3:0] dat_rsp_pra_en_d1; +reg dat_rsp_pvld_d1; +reg dat_rsp_pvld_d2; +reg dat_rsp_pvld_d3; +reg dat_rsp_pvld_d4; +reg [255:0] dat_rsp_wg_ch0_d1; +reg [255:0] dat_rsp_wg_ch1_d1; +reg [255:0] dat_rsp_wg_ch2_d1; +reg [255:0] dat_rsp_wg_ch3_d1; +reg [13:0] dat_slice_avl; +reg [4:0] data_bank; +reg [5:0] data_batch; +reg [10:0] datain_c_cnt; +reg [10:0] datain_channel_cmp; +reg [13:0] datain_h_cnt; +reg [13:0] datain_h_ori; +reg [12:0] datain_height_cmp; +reg [13:0] datain_w_cnt; +reg [13:0] datain_w_ori; +reg [13:0] datain_width; +reg [12:0] datain_width_cmp; +reg [12:0] dataout_w_cnt; +reg [12:0] dataout_w_ori; +reg [12:0] dataout_width_cmp; +reg [8:0] dl_out_flag; +reg [8 -1:0] dl_out_mask; +reg dl_out_pvld; +reg dl_out_pvld_d1; +reg [30:0] dl_pd_d1; +reg [30:0] dl_pd_d2; +reg [30:0] dl_pd_d3; +reg [30:0] dl_pd_d4; +reg dl_pvld_d1; +reg dl_pvld_d2; +reg dl_pvld_d3; +reg dl_pvld_d4; +reg [15 -1:0] entries; +reg [15 -1:0] entries_batch; +reg [15 -1:0] entries_cmp; +reg [14 -1:0] h_bias_0_d1; +reg [14 -1:0] h_bias_0_stride; +reg [14 -1:0] h_bias_1_d1; +reg [14 -1:0] h_bias_1_stride; +reg [14 -1:0] h_bias_2_d1; +reg [14 -1:0] h_bias_2_stride; +reg [14 -1:0] h_bias_3_d1; +reg [14 -1:0] h_bias_3_stride; +reg [13:0] h_offset_slice; +reg [33:0] is_img_d1; +reg is_sg_running_d1; +reg [21:0] is_winograd_d1; +reg [15 -1:0] last_entries; +reg [13:0] last_slices; +reg layer_st_d1; +reg [15:0] pad_value; +reg [11:0] pixel_ch_stride; +reg pixel_force_clr_d1; +reg pixel_force_fetch_d1; +reg [15:0] pixel_w_ch_ori; +reg [15:0] pixel_w_cnt; +reg [15:0] pixel_w_ori; +reg [6:0] pixel_x_add; +reg [6:0] pixel_x_byte_stride; +reg [5:0] pixel_x_init; +reg [6:0] pixel_x_init_offset; +reg pixel_x_stride_odd; +reg [7:0] pra_precision; +reg [7:0] pra_truncate; +reg [15 -1:0] rls_entries; +reg [13:0] rls_slices; +reg [7:0] rsp_sft_cnt_l0; +reg [7:0] rsp_sft_cnt_l0_ori; +reg [7:0] rsp_sft_cnt_l1; +reg [7:0] rsp_sft_cnt_l1_ori; +reg [7:0] rsp_sft_cnt_l2; +reg [7:0] rsp_sft_cnt_l2_ori; +reg [7:0] rsp_sft_cnt_l3; +reg [7:0] rsp_sft_cnt_l3_ori; +reg [14 -1:0] sc2buf_dat_rd_addr; +reg [14 -1:0] sc2buf_dat_rd_next1_addr; +reg sc2buf_dat_rd_en; +reg [15 -1:0] sc2cdma_dat_entries; +reg [13:0] sc2cdma_dat_slices; +reg sc2cdma_dat_updt; +reg [8 -1:0] sc2mac_dat_a_mask; +reg [8:0] sc2mac_dat_a_pd; +reg sc2mac_dat_a_pvld; +reg [8 -1:0] sc2mac_dat_b_mask; +reg [8:0] sc2mac_dat_b_pd; +reg sc2mac_dat_b_pvld; +reg slcg_wg_en_d1; +reg slcg_wg_en_d2; +reg slcg_wg_en_d3; +reg [13:0] slice_left; +reg [6:0] stripe_cnt; +reg [2:0] sub_h_cmp_g0; +reg [2:0] sub_h_cmp_g1; +reg [1:0] sub_h_cnt; +reg [2:0] sub_h_total_g0; +reg [2:0] sub_h_total_g1; +reg [2:0] sub_h_total_g10; +reg [2:0] sub_h_total_g11; +reg [1:0] sub_h_total_g2; +reg [2:0] sub_h_total_g3; +reg [2:0] sub_h_total_g4; +reg [2:0] sub_h_total_g5; +reg [2:0] sub_h_total_g6; +reg [2:0] sub_h_total_g7; +reg [2:0] sub_h_total_g8; +reg [2:0] sub_h_total_g9; +reg [14 -1:0] w_bias_d1; +reg [5:0] x_dilate; +reg [5:0] y_dilate; +wire [4:0] batch_cmp_w; +wire [4:0] batch_cnt_w; +wire [14 -1:0] c_bias_add; +wire c_bias_d1_reg_en; +wire c_bias_reg_en; +wire [14 -1:0] c_bias_w; +wire cbuf_reset; +wire [3:0] conv_x_stride_w; +wire [3:0] conv_y_stride_w; +wire dat_conv_req_dummy; +wire dat_dummy_l0_en; +wire dat_dummy_l1_en; +wire dat_dummy_l2_en; +wire dat_dummy_l3_en; +wire [15 -1:0] dat_entry_avl_add; +wire [15 -1:0] dat_entry_avl_sub; +wire [15 -1:0] dat_entry_avl_w; +wire [15 -1:0] dat_entry_end_inc; +wire [15 -1:0] dat_entry_end_inc_wrap; +wire [15 -1:0] dat_entry_end_w; +wire [15 -1:0] dat_entry_st_inc; +wire [15 -1:0] dat_entry_st_inc_wrap; +wire [15 -1:0] dat_entry_st_w; +wire mon_dat_entry_end_inc; +wire mon_dat_entry_st_inc; +wire dat_exec_valid; +wire dat_img_req_dummy; +wire dat_img_req_skip; +wire dat_l0_set; +wire dat_l0c0_dummy_w; +wire dat_l0c0_en; +wire dat_l0c1_dummy_w; +wire dat_l0c1_en; +wire dat_l1_set; +wire dat_l1c0_dummy_w; +wire dat_l1c0_en; +wire dat_l1c0_hi_en; +wire dat_l1c1_dummy_w; +wire dat_l1c1_en; +wire dat_l1c1_hi_en; +wire dat_l2_set; +wire dat_l2c0_dummy_w; +wire dat_l2c0_en; +wire dat_l2c1_dummy_w; +wire dat_l2c1_en; +wire dat_l3_set; +wire dat_l3c0_dummy_w; +wire dat_l3c0_en; +wire dat_l3c1_dummy_w; +wire dat_l3c1_en; +wire [64 -1:0] dat_out_bypass_data_w; +wire [8 -1:0] dat_out_bypass_mask_w; +wire dat_out_bypass_p0_vld_w; +wire [64 -1:0] dat_out_data; +wire [8:0] dat_out_flag_l0; +wire [8:0] dat_out_flag_w; +wire [8 -1:0] dat_out_mask; +wire dat_out_pvld_l0; +wire dat_out_pvld_w; +wire [64 -1:0] dat_out_wg_8b; +wire [64 -1:0] dat_out_wg_data; +wire [8 -1:0] dat_out_wg_mask; +wire [8 -1:0] dat_out_wg_mask_int8; +wire dat_pipe_local_valid_w; +wire dat_pipe_valid; +wire [64 -1:0] dat_pra_dat; +wire [255:0] dat_pra_dat_ch0; +wire [255:0] dat_pra_dat_ch1; +wire [255:0] dat_pra_dat_ch2; +wire [255:0] dat_pra_dat_ch3; +wire [14 -1:0] dat_req_addr_last; +wire [14:0] dat_req_addr_sum; +wire [14 -1:0] dat_req_addr_w; +wire [14 -1:0] dat_req_addr_wrap; +wire [14 -1:0] dat_req_base_d1; +wire mon_dat_req_addr_sum; +wire [4:0] dat_req_batch_index; +wire [7:0] dat_req_bytes; +wire dat_req_channel_end; +wire dat_req_dummy; +wire dat_req_exec_dummy; +wire dat_req_exec_pvld; +wire [1:0] dat_req_exec_sub_h; +wire [8:0] dat_req_flag_w; +wire dat_req_layer_end; +wire [7:0] dat_req_pipe_bytes; +wire dat_req_pipe_ch_end; +wire [1:0] dat_req_pipe_cur_sub_h; +wire dat_req_pipe_dummy; +wire [8:0] dat_req_pipe_flag; +wire [28:0] dat_req_pipe_pd; +wire dat_req_pipe_pvld; +wire dat_req_pipe_rls; +wire dat_req_pipe_sub_c; +wire [1:0] dat_req_pipe_sub_h; +wire [1:0] dat_req_pipe_sub_w; +wire dat_req_pipe_sub_w_st; +wire dat_req_skip; +wire dat_req_stripe_end; +wire dat_req_stripe_st; +wire dat_req_sub_c_w; +wire dat_req_sub_h_0_addr_en; +wire dat_req_sub_h_1_addr_en; +wire dat_req_sub_h_2_addr_en; +wire dat_req_sub_h_3_addr_en; +wire dat_req_sub_w_st_en; +wire [1:0] dat_req_sub_w_w; +wire dat_req_valid; +wire dat_rls; +wire [4:0] dat_rsp_batch_index; +wire [7:0] dat_rsp_bytes; +wire dat_rsp_ch_end; +wire dat_rsp_channel_end; +wire [64 -1:0] dat_rsp_conv; +wire [64 -1:0] dat_rsp_conv_8b; +wire [8 -1:0] dat_rsp_cur_h_e2_mask_8b; +wire [8 -1:0] dat_rsp_cur_h_e4_mask_8b; +wire [8 -1:0] dat_rsp_cur_h_mask_p1; +wire [31:0] dat_rsp_cur_h_mask_p2; +wire [31:0] dat_rsp_cur_h_mask_p3; +wire [1:0] dat_rsp_cur_sub_h; +wire [64 -1:0] dat_rsp_data_w; +wire dat_rsp_exec_dummy; +wire dat_rsp_exec_dummy_d0; +wire dat_rsp_exec_pvld; +wire dat_rsp_exec_pvld_d0; +wire [1:0] dat_rsp_exec_sub_h; +wire [1:0] dat_rsp_exec_sub_h_d0; +wire [8:0] dat_rsp_flag; +wire [64 -1:0] dat_rsp_img; +wire [64 -1:0] dat_rsp_img_8b; +wire dat_rsp_l0_block_end; +wire [8:0] dat_rsp_l0_flag; +wire dat_rsp_l0_pvld; +wire [64*2 -1:0] dat_rsp_l0_sft_in; +wire dat_rsp_l0_stripe_end; +wire dat_rsp_l0_sub_c; +wire [64 -1:0] dat_rsp_l0c0; +wire [64 -1:0] dat_rsp_l0c1; +wire dat_rsp_l1_block_end; +wire [8:0] dat_rsp_l1_flag; +wire dat_rsp_l1_pvld; +wire [64*2 -1:0] dat_rsp_l1_sft_in; +wire dat_rsp_l1_stripe_end; +wire dat_rsp_l1_sub_c; +wire [64 -1:0] dat_rsp_l1c0; +wire [64 -1:0] dat_rsp_l1c1; +wire dat_rsp_l2_block_end; +wire [8:0] dat_rsp_l2_flag; +wire dat_rsp_l2_pvld; +wire [64*2 -1:0] dat_rsp_l2_sft_in; +wire dat_rsp_l2_stripe_end; +wire dat_rsp_l2_sub_c; +wire [64 -1:0] dat_rsp_l2c0; +wire [64 -1:0] dat_rsp_l2c1; +wire dat_rsp_l3_block_end; +wire [8:0] dat_rsp_l3_flag; +wire dat_rsp_l3_pvld; +wire [64*2 -1:0] dat_rsp_l3_sft_in; +wire dat_rsp_l3_stripe_end; +wire dat_rsp_l3_sub_c; +wire [64 -1:0] dat_rsp_l3c0; +wire [64 -1:0] dat_rsp_l3c1; +wire dat_rsp_layer_end; +wire [8 -1:0] dat_rsp_mask_8b; +wire [8 -1:0] dat_rsp_mask_val_int8; +wire [8 -1:0] dat_rsp_mask_w; +wire [8 -1:0] dat_rsp_ori_mask; +wire dat_rsp_p0_vld_w; +wire dat_rsp_p1_vld_w; +wire [64 -1:0] dat_rsp_pad_value; +wire [26:0] dat_rsp_pd; +wire [26:0] dat_rsp_pd_d0; +wire [7:0] dat_rsp_pipe_bytes; +wire dat_rsp_pipe_ch_end; +wire [1:0] dat_rsp_pipe_cur_sub_h; +wire dat_rsp_pipe_dummy; +wire [8:0] dat_rsp_pipe_flag; +wire [28:0] dat_rsp_pipe_pd; +wire [28:0] dat_rsp_pipe_pd_d0; +wire dat_rsp_pipe_pvld; +wire dat_rsp_pipe_pvld_d0; +wire dat_rsp_pipe_rls; +wire dat_rsp_pipe_sub_c; +wire [1:0] dat_rsp_pipe_sub_h; +wire [1:0] dat_rsp_pipe_sub_w; +wire dat_rsp_pipe_sub_w_st; +wire dat_rsp_pra_en; +wire dat_rsp_pvld; +wire dat_rsp_pvld_d0; +wire dat_rsp_rls; +wire dat_rsp_stripe_end; +wire dat_rsp_stripe_st; +wire dat_rsp_sub_c; +wire [1:0] dat_rsp_sub_h; +wire [1:0] dat_rsp_sub_w; +wire [64 -1:0] dat_rsp_wg; +wire [255:0] dat_rsp_wg_ch0; +wire [255:0] dat_rsp_wg_ch1; +wire [255:0] dat_rsp_wg_ch2; +wire [255:0] dat_rsp_wg_ch3; +wire [64 -1:0] dat_rsp_wg_lb; +wire [64 -1:0] dat_rsp_wg_lt; +wire [64 -1:0] dat_rsp_wg_rb; +wire [64 -1:0] dat_rsp_wg_rt; +wire dat_rsp_wg_sel_8b_hi; +wire dat_rsp_wg_sel_8b_lo; +wire dat_rsp_wg_sel_lb; +wire dat_rsp_wg_sel_lt; +wire dat_rsp_wg_sel_rb; +wire dat_rsp_wg_sel_rt; +wire [13:0] dat_slice_avl_add; +wire [13:0] dat_slice_avl_sub; +wire [13:0] dat_slice_avl_w; +wire [2303:0] dat_wg; +wire [255:0] dat_wg_8b_ch0; +wire [255:0] dat_wg_8b_ch1; +wire [255:0] dat_wg_8b_ch2; +wire [255:0] dat_wg_8b_ch3; +wire [255:0] dat_wg_8b_ch4; +wire [255:0] dat_wg_8b_ch5; +wire [255:0] dat_wg_8b_ch6; +wire [255:0] dat_wg_8b_ch7; +wire dat_wg_adv; +wire dat_wg_req_dummy; +wire dat_wg_req_skip; +wire [4:0] data_bank_w; +wire [5:0] data_batch_w; +wire [10:0] datain_c_cnt_inc; +wire datain_c_cnt_reg_en; +wire [10:0] datain_c_cnt_w; +wire [10:0] datain_channel_cmp_w; +wire [13:0] datain_h_cnt_inc; +wire datain_h_cnt_reg_en; +wire [13:0] datain_h_cnt_st; +wire [13:0] datain_h_cnt_w; +wire [13:0] datain_h_cur; +wire datain_h_ori_reg_en; +wire [12:0] datain_height_cmp_w; +wire [13:0] datain_w_cnt_inc; +wire datain_w_cnt_reg_en; +wire [13:0] datain_w_cnt_st; +wire [13:0] datain_w_cnt_w; +wire [13:0] datain_w_cur; +wire datain_w_ori_reg_en; +wire [12:0] datain_width_cmp_w; +wire [13:0] datain_width_w; +wire [2:0] dataout_w_add; +wire [12:0] dataout_w_cnt_inc; +wire dataout_w_cnt_reg_en; +wire [12:0] dataout_w_cnt_w; +wire [12:0] dataout_w_init; +wire dataout_w_ori_reg_en; +wire [12:0] dataout_width_cmp_w; +wire [64 -1:0] dbg_csc_dat; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: wire [8 -1:0] dbg_csc_dat_${i}; ) +//: } +wire dl_block_end; +wire dl_channel_end; +wire [6:0] dl_channel_size; +wire [1:0] dl_cur_sub_h; +wire dl_dat_release; +wire dl_group_end; +wire [4:0] dl_h_offset; +wire [9:0] dl_h_offset_ext; +wire [30:0] dl_in_pd; +wire [30:0] dl_in_pd_d0; +wire dl_in_pvld; +wire dl_in_pvld_d0; +wire dl_layer_end; +wire [30:0] dl_pd; +wire [30:0] dl_pd_d0; +wire dl_pvld; +wire dl_pvld_d0; +wire [6:0] dl_stripe_length; +wire [4:0] dl_w_offset; +wire [9:0] dl_w_offset_ext; +wire [15 -1:0] entries_batch_w; +wire [15 -1:0] entries_single_w; +wire [15 -1:0] entries_w; +wire [14 -1:0] h_bias_0_stride_w; +wire [14 -1:0] h_bias_0_w; +wire [14 -1:0] h_bias_1_stride_w; +wire [14 -1:0] h_bias_1_w; +wire [14 -1:0] h_bias_2_w; +wire [14 -1:0] h_bias_3_w; +wire [14 -1:0] h_bias_d1; +wire [1:0] h_bias_reg_en; +wire [13:0] h_offset_slice_w; +wire is_batch_end; +wire is_conv; +wire is_dat_entry_end_wrap; +wire is_dat_entry_st_wrap; +wire is_dat_req_addr_wrap; +wire is_img; +wire is_last_channel; +wire is_pixel; +wire is_running_first; +wire is_sg_done; +wire is_sg_idle; +wire is_sg_running; +wire is_stripe_end; +wire is_stripe_equal; +wire is_sub_h_end; +wire is_w_end; +wire is_w_end_ahead; +wire is_winograd; +wire layer_st; +wire mon_batch_cnt_w; +wire mon_c_bias_w; +wire mon_dat_entry_avl_w; +wire mon_dat_entry_end_inc_wrap; +wire mon_dat_entry_st_inc_wrap; +wire [3:0] mon_dat_out_pra_vld; +wire [1:0] mon_dat_req_addr_wrap; +wire [64 -1:0] mon_dat_rsp_l0_sft; +wire [64 -1:0] mon_dat_rsp_l1_sft; +wire [64 -1:0] mon_dat_rsp_l2_sft; +wire [64 -1:0] mon_dat_rsp_l3_sft; +wire [3:0] mon_dat_rsp_pra_rdy; +wire mon_dat_slice_avl_w; +wire mon_data_bank_w; +wire mon_datain_c_cnt_inc; +wire mon_datain_h_cnt_inc; +wire mon_datain_h_cur; +wire mon_datain_w_cnt_inc; +wire mon_datain_w_cur; +wire mon_dataout_w_cnt_inc; +wire [5:0] mon_entries_batch_w; +wire mon_entries_single_w; +wire mon_entries_w; +wire [5:0] mon_h_bias_0_stride_w; +wire [14 -1:0] mon_h_bias_0_w; +wire [12:0] mon_h_bias_1_stride_w; +wire [4:0] mon_h_bias_1_w; +wire [4:0] mon_h_bias_2_w; +wire [1:0] mon_h_bias_3_w; +wire mon_h_bias_d1; +wire mon_pixel_w_cnt_w; +wire [1:0] mon_pixel_x_init_w; +wire mon_rls_slices_w; +wire mon_rsp_sft_cnt_l0_w; +wire mon_rsp_sft_cnt_l1_w; +wire mon_rsp_sft_cnt_l2_w; +wire mon_rsp_sft_cnt_l3_w; +wire [13:0] mon_slice_entries_w; +wire [1:0] mon_slice_left_w; +wire mon_stripe_cnt_inc; +wire [2:0] mon_sub_h_total_w; +wire pixel_ch_ori_reg_en; +wire [11:0] pixel_ch_stride_w; +wire pixel_force_clr; +wire pixel_force_fetch; +wire pixel_w_cnt_reg_en; +wire [15:0] pixel_w_cnt_w; +wire [14:0] pixel_w_cur; +wire pixel_w_ori_reg_en; +wire [7:0] pixel_x_add_w; +wire [6:0] pixel_x_byte_stride_w; +wire [6:0] pixel_x_cnt_add; +wire [6:0] pixel_x_init_offset_w; +wire [5:0] pixel_x_init_w; +wire [5:0] pixel_x_stride_w; +wire [1:0] pra_precision_0; +wire [1:0] pra_precision_1; +wire [1:0] pra_precision_2; +wire [1:0] pra_precision_3; +wire [1:0] pra_truncate_0; +wire [1:0] pra_truncate_1; +wire [1:0] pra_truncate_2; +wire [1:0] pra_truncate_3; +wire [1:0] pra_truncate_w; +wire reuse_rls; +wire [13:0] rls_slices_w; +wire rsp_sft_cnt_l0_en; +wire [7:0] rsp_sft_cnt_l0_inc; +wire rsp_sft_cnt_l0_ori_en; +wire [7:0] rsp_sft_cnt_l0_sub; +wire [7:0] rsp_sft_cnt_l0_w; +wire rsp_sft_cnt_l1_en; +wire [7:0] rsp_sft_cnt_l1_inc; +wire rsp_sft_cnt_l1_ori_en; +wire [7:0] rsp_sft_cnt_l1_sub; +wire [7:0] rsp_sft_cnt_l1_w; +wire rsp_sft_cnt_l2_en; +wire [7:0] rsp_sft_cnt_l2_inc; +wire rsp_sft_cnt_l2_ori_en; +wire [7:0] rsp_sft_cnt_l2_sub; +wire [7:0] rsp_sft_cnt_l2_w; +wire rsp_sft_cnt_l3_en; +wire [7:0] rsp_sft_cnt_l3_inc; +wire rsp_sft_cnt_l3_ori_en; +wire [7:0] rsp_sft_cnt_l3_sub; +wire [7:0] rsp_sft_cnt_l3_w; +wire rsp_sft_l1_sel_1; +wire rsp_sft_l1_sel_2; +wire rsp_sft_l1_sel_3; +wire rsp_sft_l2_sel_1; +wire rsp_sft_l2_sel_2; +wire rsp_sft_l2_sel_3; +wire rsp_sft_l3_sel_1; +wire rsp_sft_l3_sel_2; +wire rsp_sft_l3_sel_3; +wire sc2buf_dat_rd_en_w; +wire [15 -1:0] sc2cdma_dat_entries_w; +wire [13:0] sc2cdma_dat_slices_w; +wire [8:0] sc2mac_dat_pd_w; +wire slcg_wg_en_w; +wire [15 -1:0] slice_entries_w; +wire [13:0] slice_left_w; +wire [13:0] slices_oprand; +wire [6:0] stripe_cnt_inc; +wire stripe_cnt_reg_en; +wire [6:0] stripe_cnt_w; +wire [2:0] sub_h_cmp_w; +wire [2:0] sub_h_cnt_inc; +wire sub_h_cnt_reg_en; +wire [1:0] sub_h_cnt_w; +wire [2:0] sub_h_total_w; +wire sub_rls; +wire [14:0] w_bias_int8; +wire w_bias_reg_en; +wire [13:0] w_bias_w; +wire [5:0] x_dilate_w; +wire [5:0] y_dilate_w; +///////////////////////////////////////////////////////////////////////////////////////////// +// Pipeline of Weight loader, for both compressed weight and uncompressed weight +// +// input_package +// | +// data request +// | +// conv_buffer +// | +// feature data---> data relase +// | | +// REG PRA +// | | +// REGISTER +// | +// MAC +// +///////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///// status from sequence generator ///// +////////////////////////////////////////////////////////////// +assign is_sg_idle = (sc_state == 0 ); +assign is_sg_running = (sc_state == 2 ); +assign is_sg_done = (sc_state == 3 ); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_sg_running\" -q is_sg_running_d1"); +////////////////////////////////////////////////////////////// +///// input signals from registers ///// +////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en & is_sg_idle; +assign is_pixel = (reg2dp_datain_format == 1'h1 ); +`ifdef NVDLA_WINOGRAD_ENABLE +assign is_winograd = (reg2dp_conv_mode == 1'h1 ); +`else +assign is_winograd = 1'b0; +`endif +assign is_conv = (reg2dp_conv_mode == 1'h0 ); +assign is_img = is_conv & is_pixel; +assign {mon_data_bank_w, data_bank_w} = reg2dp_data_bank + 1'b1; +`ifdef NVDLA_BATCH_ENABLE +assign data_batch_w = (is_winograd | is_img) ? 6'b1 : reg2dp_batches + 1'b1; +assign batch_cmp_w = (is_winograd | is_img) ? 5'b0 : reg2dp_batches; +`else +assign data_batch_w = 6'b1; +assign batch_cmp_w = 5'b0; +`endif +//assign is_int8 = (reg2dp_proc_precision == 2'h0 ); +//assign is_fp16 = (reg2dp_proc_precision == 2'h2 ); +assign datain_width_w = is_winograd ? ({2'b0, reg2dp_datain_width_ext[12:2]} + 1'b1) : reg2dp_datain_width_ext + 1'b1; +assign datain_width_cmp_w = reg2dp_datain_width_ext; +assign datain_height_cmp_w = reg2dp_datain_height_ext; +assign datain_channel_cmp_w = is_winograd ? reg2dp_weight_channel_ext[12:2] : {{3 -2{1'b0}}, reg2dp_weight_channel_ext[12:3]}; +//y_ex=0,sub_h_total=1;y_ex=1,sub_h_total=2; y_ext=2,sub_h_total=4; non_image, sub_h_total=1; +//sub_h_total means how many h lines are used in post-extention +assign {sub_h_total_w, mon_sub_h_total_w} = is_img ? (6'h9 << reg2dp_y_extension) : 6'h8; +assign sub_h_cmp_w = is_img ? sub_h_total_w : is_winograd ? 3'h2 : 3'h1; +assign dataout_w_init[12:0] = sub_h_cmp_w - 1'b1; +assign conv_x_stride_w = (is_winograd) ? 4'b1 : reg2dp_conv_x_stride_ext + 1'b1; +assign pixel_x_stride_w = (reg2dp_datain_channel_ext[1:0] == 2'h3) ? {conv_x_stride_w, 2'b0} : //*4, after pre_extension + (reg2dp_datain_channel_ext[1:0] == 2'h2) ? ({conv_x_stride_w, 1'b0} + conv_x_stride_w) : //*3 + {2'b0, conv_x_stride_w}; //*1 +assign {mon_pixel_x_init_w,pixel_x_init_w} = (reg2dp_y_extension == 2'h2) ? ({pixel_x_stride_w, 1'b0} + pixel_x_stride_w + reg2dp_weight_channel_ext[5:0]) : + (reg2dp_y_extension == 2'h1) ? (pixel_x_stride_w + reg2dp_weight_channel_ext[5:0]): + (reg2dp_weight_channel_ext >= 7'h08) ? {3{1'b1}}: //cut by atomC + {{6-3{1'b0}},reg2dp_weight_channel_ext[3 -1:0]}; +assign pixel_x_init_offset_w = (reg2dp_weight_channel_ext[3 -1:0] + 1'b1); +assign pixel_x_add_w = (reg2dp_y_extension == 2'h2) ? {pixel_x_stride_w, 2'b0} : //*4, after post_extension + (reg2dp_y_extension == 2'h1) ? {1'b0, pixel_x_stride_w, 1'b0} : //*2 + {2'b0, pixel_x_stride_w}; +assign pixel_x_byte_stride_w = {1'b0, pixel_x_stride_w}; +assign pixel_ch_stride_w = {{5-3{1'b0}},pixel_x_stride_w, {3 +1{1'b0}}}; //stick to 2*atomK no matter which config. +assign conv_y_stride_w = (is_winograd) ? 4'b1 : reg2dp_conv_y_stride_ext + 1'b1; +assign x_dilate_w = (is_winograd | is_img) ? 6'b1 : reg2dp_x_dilation_ext + 1'b1; +assign y_dilate_w = (is_winograd | is_img) ? 6'b1 : reg2dp_y_dilation_ext + 1'b1; +//reg2dp_entries means entry per slice +assign {mon_entries_single_w,entries_single_w} = (reg2dp_entries + 1'b1); +assign {mon_entries_batch_w,entries_batch_w} = entries_single_w * data_batch_w; +assign {mon_entries_w,entries_w} = (is_winograd) ? ({reg2dp_entries[12:0], 2'b0} + 3'h4) : entries_single_w; +assign h_offset_slice_w[11:0] = data_batch_w * y_dilate_w; +assign h_offset_slice_w[13:12] = 2'b0; +assign {mon_h_bias_0_stride_w,h_bias_0_stride_w} = entries * data_batch; +assign {mon_h_bias_1_stride_w,h_bias_1_stride_w} = entries * h_offset_slice; +assign {mon_rls_slices_w,rls_slices_w} = reg2dp_rls_slices + 1'b1; +assign {mon_slice_left_w,slice_left_w} = reg2dp_skip_data_rls ? (reg2dp_datain_height_ext + 1'b1) : reg2dp_datain_height_ext - reg2dp_rls_slices; +assign slices_oprand = layer_st_d1 ? rls_slices : slice_left; +assign {mon_slice_entries_w,slice_entries_w} = entries_batch * slices_oprand; +assign dataout_width_cmp_w = reg2dp_dataout_width; +assign pra_truncate_w = (reg2dp_pra_truncate == 2'h3) ? 2'h2 : reg2dp_pra_truncate; +//: my $kk=15; +//: my $jj=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"layer_st\" -q layer_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{22{1'b0}}\" -en \"layer_st\" -d \"{22{is_winograd}}\" -q is_winograd_d1"); +//: &eperl::flop("-nodeclare -rval \"{34{1'b0}}\" -en \"layer_st\" -d \"{34{is_img}}\" -q is_img_d1"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"data_bank_w\" -q data_bank"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"datain_width_w\" -q datain_width"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"datain_width_cmp_w\" -q datain_width_cmp"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"datain_height_cmp_w\" -q datain_height_cmp"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"layer_st\" -d \"datain_channel_cmp_w\" -q datain_channel_cmp"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g0"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g1"); +//: &eperl::flop("-nodeclare -rval \"2'h1\" -en \"layer_st\" -d \"sub_h_total_w[2:1]\" -q sub_h_total_g2"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g3"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g4"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g5"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g6"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g7"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g8"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g9"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g10"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total_g11"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_cmp_w\" -q sub_h_cmp_g0"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_cmp_w\" -q sub_h_cmp_g1"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_x_stride_w\" -q conv_x_stride"); +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -en \"layer_st\" -d \"conv_y_stride_w\" -q conv_y_stride"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"pixel_x_stride_w[0]\" -q pixel_x_stride_odd"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"data_batch_w\" -q data_batch"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"batch_cmp_w\" -q batch_cmp"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"pixel_x_init_w\" -q pixel_x_init"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"layer_st\" -d \"pixel_x_init_offset_w\" -q pixel_x_init_offset"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"layer_st\" -d \"pixel_x_add_w[6:0]\" -q pixel_x_add"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"layer_st\" -d \"pixel_x_byte_stride_w\" -q pixel_x_byte_stride"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st\" -d \"pixel_ch_stride_w\" -q pixel_ch_stride"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"x_dilate_w\" -q x_dilate"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"y_dilate_w\" -q y_dilate"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"layer_st\" -d \"reg2dp_pad_value\" -q pad_value"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st\" -d \"entries_w\" -q entries"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st\" -d \"entries_batch_w\" -q entries_batch"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st\" -d \"{1'h0,reg2dp_entries}\" -q entries_cmp"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"h_offset_slice_w\" -q h_offset_slice"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st_d1\" -d \"h_bias_0_stride_w\" -q h_bias_0_stride"); +//: &eperl::flop("-nodeclare -rval \"{12{1'b0}}\" -en \"layer_st_d1\" -d \"h_bias_1_stride_w\" -q h_bias_1_stride"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"layer_st_d1\" -d \"entries[${jj}-1:0]\" -q h_bias_2_stride"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"layer_st_d1\" -d \"entries[${jj}-1:0]\" -q h_bias_3_stride"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"rls_slices_w\" -q rls_slices"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st_d1\" -d \"slice_entries_w\" -q rls_entries"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"slice_left_w[13:0]\" -q slice_left"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"is_sg_done\" -d \"slice_left\" -q last_slices"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"is_sg_done\" -d \"slice_entries_w\" -q last_entries"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st\" -d \"dataout_width_cmp_w\" -q dataout_width_cmp"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"layer_st\" -d \"{4{pra_truncate_w}}\" -q pra_truncate"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"layer_st\" -d \"{4{reg2dp_proc_precision}}\" -q pra_precision"); +//////////////////////////////////////////////////////////////////////// +// SLCG control signal // +//////////////////////////////////////////////////////////////////////// +assign slcg_wg_en_w = reg2dp_op_en & is_winograd; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_wg_en_w\" -q slcg_wg_en_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_wg_en_d1\" -q slcg_wg_en_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"slcg_wg_en_d2\" -q slcg_wg_en_d3"); +assign slcg_wg_en = slcg_wg_en_d3; +////////////////////////////////////////////////////////////// +///// cbuf status management ///// +////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +assign cbuf_reset = sc2cdma_dat_pending_req; +assign is_running_first = is_sg_running & ~is_sg_running_d1; +//////////////////////////////////// calculate how many avaliable dat slices in cbuf//////////////////////////////////// +assign dat_slice_avl_add = cdma2sc_dat_updt ? cdma2sc_dat_slices : 14'b0; +assign dat_slice_avl_sub = dat_rls ? sc2cdma_dat_slices_w : 14'b0; +assign {mon_dat_slice_avl_w, dat_slice_avl_w} = (cbuf_reset) ? 14'b0 : dat_slice_avl + dat_slice_avl_add - dat_slice_avl_sub; +//////////////////////////////////// calculate how many avaliable dat entries in cbuf//////////////////////////////////// +assign dat_entry_avl_add = cdma2sc_dat_updt ? cdma2sc_dat_entries :{15{1'b0}}; +assign dat_entry_avl_sub = dat_rls ? sc2cdma_dat_entries_w : {15{1'b0}}; +assign {mon_dat_entry_avl_w,dat_entry_avl_w} = (cbuf_reset) ? {15{1'b0}} : dat_entry_avl + dat_entry_avl_add - dat_entry_avl_sub; +//////////////////////////////////// calculate avilable data entries start offset in cbuf banks //////////////////////////////////// +// data_bank is the highest bank for storing data +assign {mon_dat_entry_st_inc,dat_entry_st_inc} = dat_entry_st + dat_entry_avl_sub; +assign {mon_dat_entry_st_inc_wrap, dat_entry_st_inc_wrap} = dat_entry_st_inc - {data_bank, {9{1'b0}} }; +assign is_dat_entry_st_wrap = (dat_entry_st_inc >= {1'b0, data_bank, {9{1'b0}} }); +assign dat_entry_st_w = (cbuf_reset) ? {15{1'b0}} : is_dat_entry_st_wrap ? dat_entry_st_inc_wrap : dat_entry_st_inc[15 -1:0]; +//////////////////////////////////// calculate avilable data entries end offset in cbuf banks//////////////////////////////////// +assign {mon_dat_entry_end_inc,dat_entry_end_inc} = dat_entry_end + dat_entry_avl_add; +assign {mon_dat_entry_end_inc_wrap,dat_entry_end_inc_wrap} = dat_entry_end_inc - {data_bank, {9{1'b0}} }; +assign is_dat_entry_end_wrap = (dat_entry_end_inc >= {1'b0, data_bank, {9{1'b0}} }); +assign dat_entry_end_w = (cbuf_reset) ? {15{1'b0}} : is_dat_entry_end_wrap ? dat_entry_end_inc_wrap : dat_entry_end_inc[15 -1:0]; +//////////////////////////////////// registers and assertions //////////////////////////////////// +//: my $kk= 15; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{14{1'b0}}\" -en \"cdma2sc_dat_updt | dat_rls | cbuf_reset\" -d \"dat_slice_avl_w\" -q dat_slice_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{${kk}{1'b0}}\" -en \"cdma2sc_dat_updt | dat_rls | cbuf_reset\" -d \"dat_entry_avl_w\" -q dat_entry_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{${kk}{1'b0}}\" -en \"cbuf_reset | dat_rls\" -d \"dat_entry_st_w\" -q dat_entry_st"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{${kk}{1'b0}}\" -en \"cbuf_reset | cdma2sc_dat_updt\" -d \"dat_entry_end_w\" -q dat_entry_end"); +//================ Non-SLCG clock domain end ================// +////////////////////////////////////////////////////////////// +///// cbuf status update ///// +////////////////////////////////////////////////////////////// +assign sub_rls = (dat_rsp_pvld & dat_rsp_rls); +assign reuse_rls = sg2dl_reuse_rls; +assign dat_rls = (reuse_rls & (|last_slices)) | (sub_rls & (|rls_slices)); +assign sc2cdma_dat_slices_w = sub_rls ? rls_slices : last_slices; +assign sc2cdma_dat_entries_w = sub_rls ? rls_entries : last_entries; +//: my $kk=15; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_rls\" -q sc2cdma_dat_updt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dat_rls\" -d \"sc2cdma_dat_slices_w[13:0]\" -q sc2cdma_dat_slices"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dat_rls\" -d \"sc2cdma_dat_entries_w\" -q sc2cdma_dat_entries"); +////////////////////////////////////////////////////////////// +///// input sg2dl package ///// +////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///// generate data read sequence ///// +////////////////////////////////////////////////////////////// +//: my $total_depth = 0 + 5; +//: my $wg_depth = 0; +//: +//: print "assign dl_in_pvld_d0 = sg2dl_pvld;\n"; +//: print "assign dl_in_pd_d0 = sg2dl_pd;\n\n"; +//: +//: for(my $i = 0; $i < $total_depth; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dl_in_pvld_d${i}\" -q dl_in_pvld_d${j}"); +//: &eperl::flop("-wid 31 -rval \"{31{1'b0}}\" -en \"dl_in_pvld_d${i}\" -d \"dl_in_pd_d${i}\" -q dl_in_pd_d${j}"); +//: } +//: +//: my $d0 = $total_depth; +//: my $d1 = $wg_depth; +//: +//: print "assign dl_in_pvld = (is_winograd_d1[0]) ? dl_in_pvld_d${d1} : dl_in_pvld_d${d0};\n"; +//: print "assign dl_in_pd = (is_winograd_d1[1]) ? dl_in_pd_d${d1} : dl_in_pd_d${d0};\n\n"; +//: my $pipe_depth = 4; +//: my $i; +//: my $j; +//: print "assign dl_pvld_d0 = dl_in_pvld;\n"; +//: print "assign dl_pd_d0 = dl_in_pd;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_pvld_d${i}\" -q dl_pvld_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{31{1'b0}}\" -en \"dl_pvld_d${i}\" -d \"dl_pd_d${i}\" -q dl_pd_d${j}"); +//: } +assign dl_pvld = (sub_h_total_g0[2] & dl_pvld_d1) | + (sub_h_total_g0[1] & dl_pvld_d3) | + (sub_h_total_g0[0] & dl_pvld_d4); +assign dl_pd = ({31 {sub_h_total_g1[2]}} & dl_pd_d1) | + ({31 {sub_h_total_g1[1]}} & dl_pd_d3) | + ({31 {sub_h_total_g1[0]}} & dl_pd_d4); +// PKT_UNPACK_WIRE( csc_dat_pkg , dl_ , dl_pd ) +assign dl_w_offset[4:0] = dl_pd[4:0]; //this is weight offset +assign dl_h_offset[4:0] = dl_pd[9:5]; //weight offset +assign dl_channel_size[6:0] = dl_pd[16:10]; +assign dl_stripe_length[6:0]= dl_pd[23:17]; +assign dl_cur_sub_h[1:0] = dl_pd[25:24]; +assign dl_block_end = dl_pd[26]; +assign dl_channel_end = dl_pd[27]; +assign dl_group_end = dl_pd[28]; +assign dl_layer_end = dl_pd[29]; +assign dl_dat_release = dl_pd[30]; +////////////////////////// batch up counter ////////////////////////// +assign {mon_batch_cnt_w,batch_cnt_w} = layer_st ? 6'b0 : is_batch_end ? 6'b0 : batch_cnt + 1'b1; +assign is_batch_end = (batch_cnt == batch_cmp); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st | dat_exec_valid\" -d \"batch_cnt_w\" -q batch_cnt"); +////////////////////////// sub height up counter ////////////////////////// +assign sub_h_cnt_inc = sub_h_cnt + 1'b1; +assign sub_h_cnt_w = (layer_st | is_sub_h_end) ? 2'b0 : sub_h_cnt_inc[1:0]; +assign is_sub_h_end = (sub_h_cnt_inc == sub_h_cmp_g0); +assign sub_h_cnt_reg_en = layer_st | ((is_winograd_d1[2] | (|reg2dp_y_extension)) & dat_exec_valid); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"sub_h_cnt_reg_en\" -d \"sub_h_cnt_w\" -q sub_h_cnt"); +////////////////////////// stripe up counter ////////////////////////// +assign {mon_stripe_cnt_inc,stripe_cnt_inc} = stripe_cnt + 1'b1; +assign stripe_cnt_w = layer_st ? 7'b0 : + (is_stripe_equal & ~is_sub_h_end) ? stripe_cnt : + is_stripe_end ? 7'b0 : + stripe_cnt_inc; +assign is_stripe_equal = is_batch_end & (stripe_cnt_inc == dl_stripe_length); +assign is_stripe_end = is_stripe_equal & is_sub_h_end; +assign stripe_cnt_reg_en = layer_st | (dat_exec_valid & is_batch_end); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"stripe_cnt_reg_en\" -d \"stripe_cnt_w\" -q stripe_cnt"); +////////////////////////// pipe valid generator ////////////////////////// +assign dat_pipe_local_valid_w = (dat_pipe_valid & is_stripe_equal) ? 1'b0 : dl_pvld ? 1'b1 : dat_pipe_local_valid; +assign dat_pipe_valid = dl_pvld | dat_pipe_local_valid; +assign dat_exec_valid = dl_pvld ? 1'b1 : (~(|stripe_cnt) & ~(|sub_h_cnt) & ~(|batch_cnt)) ? 1'b0 : dat_exec_valid_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pipe_local_valid_w\" -q dat_pipe_local_valid"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pipe_valid\" -q dat_pipe_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_exec_valid\" -q dat_exec_valid_d1"); +////////////////////////// request bytes ////////////////////////// +assign dat_req_bytes = {1'b0, dl_channel_size}; +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"dat_exec_valid\" -d \"dat_req_bytes\" -q dat_req_bytes_d1"); +////////////////////////// output width coordinate counter ////////////////////////// +// sub_h T, output will compute sub_h point in w direction +assign dataout_w_add = sub_h_cmp_g1; +assign {mon_dataout_w_cnt_inc,dataout_w_cnt_inc} = dataout_w_cnt + dataout_w_add; +assign is_w_end = is_batch_end & is_sub_h_end & (dataout_w_cnt >= dataout_width_cmp); +assign is_w_end_ahead = is_batch_end & (dataout_w_cnt >= dataout_width_cmp); +assign dataout_w_cnt_w = layer_st ? dataout_w_init : + (is_stripe_end & ~dl_channel_end) ? dataout_w_ori : + is_w_end ? dataout_w_init : + dataout_w_cnt_inc; +assign dataout_w_cnt_reg_en = layer_st | (dat_exec_valid & is_batch_end & is_sub_h_end); +assign dataout_w_ori_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_channel_end); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"dataout_w_cnt_reg_en\" -d \"dataout_w_cnt_w\" -q dataout_w_cnt"); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"dataout_w_ori_reg_en\" -d \"dataout_w_cnt_w\" -q dataout_w_ori"); +////////////////////////// input channel coordinate counter, only feature ////////////////////////// +assign {mon_datain_c_cnt_inc,datain_c_cnt_inc} = datain_c_cnt + 1'b1; +assign is_last_channel = (datain_c_cnt == datain_channel_cmp); +assign datain_c_cnt_w = layer_st ? 11'b0 : dl_channel_end ? 11'b0 : datain_c_cnt_inc; +assign datain_c_cnt_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_block_end); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"datain_c_cnt_reg_en\" -d \"datain_c_cnt_w\" -q datain_c_cnt"); +////////////////////////// input width coordinate counter, feature/image dedicated counter ////////////////////////// +assign datain_w_cnt_st = (is_img) ? 14'b0 : (is_winograd) ? 14'h2 : 13'b0 - reg2dp_pad_left; +assign {mon_datain_w_cnt_inc,datain_w_cnt_inc} = (is_winograd_d1[3]) ? (datain_w_cnt + 2'h2) : (datain_w_cnt + conv_x_stride); +//full data cube w counter,start form negtive, only for feature data. non-image, by element +assign datain_w_cnt_w = layer_st ? datain_w_cnt_st : + (is_stripe_end & ~dl_channel_end) ? datain_w_ori : + is_w_end ? datain_w_cnt_st : + datain_w_cnt_inc; +assign dl_w_offset_ext = dl_w_offset * x_dilate; +assign {mon_datain_w_cur,datain_w_cur} = datain_w_cnt + dl_w_offset_ext; //by element +assign datain_w_cnt_reg_en = layer_st | (dat_exec_valid & is_batch_end & is_sub_h_end & ~is_img_d1[0]); +assign datain_w_ori_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_channel_end & ~is_img_d1[1]); +//notice:after sub_h T, pixel_x_add elements in W direction is used by CMAC +assign pixel_x_cnt_add = (is_sub_h_end) ? pixel_x_add : 6'b0; +//assign {mon_pixel_w_cnt_w,pixel_w_cnt_w} = (layer_st_d1) ? {{11{1'b0}}, pixel_x_init} : +// (is_stripe_end & dl_block_end & dl_channel_end & is_w_end) ? {{11{1'b0}}, pixel_x_init} : +// (is_stripe_end & dl_block_end & dl_channel_end & ~is_w_end) ? (pixel_w_ch_ori + pixel_ch_stride) : +// (is_stripe_end & dl_block_end & ~dl_channel_end) ? (pixel_w_ch_ori + pixel_x_init_offset) : +// (is_stripe_end & ~dl_block_end) ? {1'b0, pixel_w_ori} : +// (pixel_w_cnt + pixel_x_cnt_add); +//channel count. +wire [12:0] total_channel_op = (reg2dp_weight_channel_ext[3 -1:0]=={3{1'b0}}) ? + reg2dp_weight_channel_ext[12:3] : reg2dp_weight_channel_ext[12:3]+1'b1; +reg [12:0] channel_op_cnt; +wire mon_channel_op_cnt_nxt; +wire [12:0] channel_op_cnt_nxt; +assign {mon_channel_op_cnt_nxt, channel_op_cnt_nxt} = dl_channel_end&is_stripe_end ? 13'h2 : + dl_block_end&is_stripe_end ? channel_op_cnt + 1'b1 : + channel_op_cnt; +//: &eperl::flop("-q channel_op_cnt -d \"channel_op_cnt_nxt\" -wid 13 -rval \"13'h2\" -nodeclare "); +wire next_is_last_channel = (channel_op_cnt >= total_channel_op); +//notice, after pre-extention, image weight w_total <=128 +assign {mon_pixel_w_cnt_w,pixel_w_cnt_w} = (layer_st_d1) ? {{11{1'b0}}, pixel_x_init} : + (is_stripe_end & dl_block_end & dl_channel_end & is_w_end) ? {{11{1'b0}}, pixel_x_init} : + (is_stripe_end & dl_block_end & dl_channel_end & ~is_w_end) ? (pixel_w_ch_ori + pixel_ch_stride) : +//(is_stripe_end & dl_block_end & ~dl_channel_end) ? (pixel_w_ori + dl_in_pd_d0[16:10]) : + (is_stripe_end & dl_block_end & next_is_last_channel) ? (pixel_w_ori + pixel_x_init_offset) : + (is_stripe_end & dl_block_end & ~next_is_last_channel) ? (pixel_w_ori + 8'h08 ) : + (is_stripe_end & ~dl_block_end) ? {1'b0, pixel_w_ori} : + (pixel_w_cnt + pixel_x_cnt_add); +assign pixel_w_cur = {{3 -1{1'b0}},pixel_w_cnt[15:3]}; //by entry +assign pixel_w_cnt_reg_en = layer_st_d1 | (dat_exec_valid & is_img_d1[2] & (is_sub_h_end | is_w_end)); +assign pixel_w_ori_reg_en = layer_st_d1 | (dat_exec_valid & is_img_d1[3] & is_stripe_end & dl_block_end); +assign pixel_ch_ori_reg_en = layer_st_d1 | (dat_exec_valid & is_img_d1[4] & is_stripe_end & dl_block_end & dl_channel_end); +assign pixel_force_fetch = (is_img_d1[0] & dat_req_stripe_st) ? 1'b1 : (pixel_force_clr_d1) ? 1'b0 : pixel_force_fetch_d1; +assign pixel_force_clr = is_img_d1[0] & is_sub_h_end & (pixel_force_fetch | pixel_force_fetch_d1); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_w_cnt_reg_en\" -d \"datain_w_cnt_w\" -q datain_w_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_w_ori_reg_en\" -d \"datain_w_cnt_w\" -q datain_w_ori"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"pixel_w_cnt_reg_en\" -d \"pixel_w_cnt_w\" -q pixel_w_cnt"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"pixel_w_ori_reg_en\" -d \"pixel_w_cnt_w\" -q pixel_w_ori"); +//: &eperl::flop("-nodeclare -rval \"{16{1'b0}}\" -en \"pixel_ch_ori_reg_en\" -d \"pixel_w_cnt_w\" -q pixel_w_ch_ori"); +////////////////////////// input height coordinate counter, feature/image both ////////////////////////// +// full data cube h counter, start form negative +assign datain_h_cnt_st = (is_winograd) ? 14'b0 : 14'b0 - reg2dp_pad_top; +assign {mon_datain_h_cnt_inc, datain_h_cnt_inc} = datain_h_cnt + conv_y_stride; +assign datain_h_cnt_w = (layer_st | (is_stripe_end & dl_group_end)) ? datain_h_cnt_st : + (is_stripe_end & ~dl_channel_end) ? datain_h_ori : + is_w_end ? datain_h_cnt_inc : + datain_h_cnt; +assign datain_h_cnt_reg_en = layer_st | (dat_exec_valid & ((is_stripe_end & ~dl_channel_end) | is_w_end)); +assign datain_h_ori_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_channel_end); +assign dl_h_offset_ext = dl_h_offset * y_dilate; +assign {mon_datain_h_cur,datain_h_cur} = datain_h_cnt + dl_h_offset_ext + sub_h_cnt; +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_h_cnt_reg_en\" -d \"datain_h_cnt_w\" -q datain_h_cnt"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"datain_h_ori_reg_en\" -d \"datain_h_cnt_w\" -q datain_h_ori"); +////////////////////////// fetch valid generate ////////////////////////// +assign dat_conv_req_dummy = (datain_w_cur[13 ]) | (datain_w_cur > {1'b0, datain_width_cmp}) + | (datain_h_cur[13 ]) | (datain_h_cur > {1'b0, datain_height_cmp}); +assign dat_wg_req_dummy = 1'b0; +assign dat_wg_req_skip = ((|datain_w_cur[13:2]) & datain_w_cur[1] & (|stripe_cnt[6:1])); +assign dat_img_req_dummy = (datain_h_cur[13]) | (datain_h_cur > {1'b0, datain_height_cmp}); +//w address(in entry) is bigger than avilable entrys +assign dat_img_req_skip = ({{15 -12{1'b0}},w_bias_w[13:2]} > entries_cmp[15 -1:0]); +assign dat_req_dummy = is_img_d1[5] ? dat_img_req_dummy : is_winograd_d1[4] ? dat_wg_req_dummy : dat_conv_req_dummy; +assign dat_req_skip = (is_winograd_d1[5] & dat_wg_req_skip) | (is_img_d1[6] & dat_img_req_skip); +assign dat_req_valid = (dat_exec_valid & ~dat_req_dummy & ~dat_req_skip); +//Add corner case +assign dat_req_sub_c_w = ~is_img_d1[7] ? datain_c_cnt[0] : dl_block_end; +assign dat_req_sub_w_w = is_winograd_d1[6] ? {1'b0, ~datain_w_cur[1]} : datain_w_cur[1:0]; +assign dat_req_sub_w_st_en = dat_exec_valid & (sub_h_cnt == 2'h0); +assign dat_req_batch_index = batch_cnt; +assign dat_req_stripe_st = dl_pvld; +assign dat_req_stripe_end = is_stripe_equal & dat_pipe_valid; +assign dat_req_channel_end = dl_channel_end; +assign dat_req_layer_end = dl_layer_end; +// PKT_PACK_WIRE( nvdla_stripe_info , dat_req_ , dat_req_flag_w ) +assign dat_req_flag_w[4:0] = dat_req_batch_index[4:0]; +assign dat_req_flag_w[5] = dat_req_stripe_st ; +assign dat_req_flag_w[6] = dat_req_stripe_end ; +assign dat_req_flag_w[7] = dat_req_channel_end ; +assign dat_req_flag_w[8] = dat_req_layer_end ; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_req_valid\" -q dat_req_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid\" -d \"dat_req_sub_w_w\" -q dat_req_sub_w_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid\" -d \"sub_h_cnt\" -q dat_req_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"dat_req_sub_c_w\" -q dat_req_sub_c_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"is_last_channel\" -q dat_req_ch_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"dat_req_dummy\" -q dat_req_dummy_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid\" -d \"dl_cur_sub_h\" -q dat_req_cur_sub_h_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_req_sub_w_st_en\" -d \"dat_req_stripe_st\" -q dat_req_sub_w_st_d1"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_exec_valid\" -d \"dat_req_flag_w\" -q dat_req_flag_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"dl_dat_release & is_stripe_equal & dat_pipe_valid\" -q dat_req_rls_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"pixel_force_fetch\" -q pixel_force_fetch_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid\" -d \"pixel_force_clr\" -q pixel_force_clr_d1"); +////////////////////////////////////////////////////////////// +///// generate data read address ///// +////////////////////////////////////////////////////////////// +////////////////////////// data read index generator: 1st stage ////////////////////////// +//channel bias, by w_in element +//assign c_bias_add = (~is_img_d1[8] & datain_c_cnt[0]) ? datain_width[12 -1:0] : 12'b0; +assign c_bias_add = (~is_img_d1[8]) ? datain_width[12 -1:0] : 12'b0; +assign {mon_c_bias_w, c_bias_w} = layer_st ? 13'b0 : (is_stripe_end & dl_channel_end) ? 13'b0 : c_bias + c_bias_add; +assign c_bias_reg_en = layer_st | (dat_exec_valid & is_stripe_end & dl_block_end); +assign c_bias_d1_reg_en = (c_bias != c_bias_d1); +//height bias, by element +assign {mon_h_bias_0_w,h_bias_0_w} = datain_h_cnt[13:0] * h_bias_0_stride; +assign {mon_h_bias_1_w,h_bias_1_w} = dl_h_offset * h_bias_1_stride; +assign {mon_h_bias_2_w,h_bias_2_w} = batch_cnt * h_bias_2_stride; +assign {mon_h_bias_3_w,h_bias_3_w} = layer_st ? 13'b0 :sub_h_cnt * h_bias_3_stride; +assign h_bias_reg_en[0] = dat_exec_valid; +assign h_bias_reg_en[1] = layer_st | (dat_exec_valid & (is_winograd_d1[7] | is_img_d1[9])); +//width bias, by entry in image, by element in feature data +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_1 +assign w_bias_int8 = is_img_d1[10] ? {pixel_w_cur} : //by entry in image + is_winograd_d1[8] ? {1'b0, datain_w_cnt} : + (~is_last_channel | datain_c_cnt[0] | is_winograd_d1[8]) ? {2'b0,datain_w_cur[12:0]} ://by element + {2'b0, datain_w_cur[12:0]}; //by element, last channel and current c is even, atomC=atomM +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_2 +assign w_bias_int8 = is_img_d1[10] ? {pixel_w_cur} : //by entry in image + is_winograd_d1[8] ? {1'b0, datain_w_cnt} : + (~is_last_channel | is_winograd_d1[8]) ? {2'b0,datain_w_cur[12:0]} ://not last channel, by element + (dat_req_bytes > 8'h04) ? {2'b0,datain_w_cur[12:0]} : //last channel & request >1/2*entry + {3'b0, datain_w_cur[12:1]}; //last channel & request<=1/2*entry +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_4 +assign w_bias_int8 = is_img_d1[10] ? {pixel_w_cur} : //by entry in image + is_winograd_d1[8] ? {1'b0, datain_w_cnt} : + (~is_last_channel | is_winograd_d1[8]) ? {2'b0,datain_w_cur[12:0]} ://not last channel, by element + (dat_req_bytes > 8'h04) ? {2'b0,datain_w_cur[12:0]} : //last channel & request >1/2*entry + (dat_req_bytes <= 8'h2) ? {4'b0, datain_w_cur[12:2]} : //last channel & request <=1/4*entry + {3'b0, datain_w_cur[12:1]}; //last channel & (1/4*entry= {1'b0,data_bank, {9{1'b0}}}); +assign {mon_dat_req_addr_wrap,dat_req_addr_wrap} = dat_req_addr_sum[14:0] - {1'b0,data_bank, {9{1'b0}}}; +assign dat_req_addr_w = (layer_st | dat_req_dummy_d1) ? {14{1'b1}} : is_dat_req_addr_wrap ? dat_req_addr_wrap : dat_req_addr_sum[14 -1:0]; //get the adress sends to cbuf +assign {mon_dat_req_addr_minus1,dat_req_addr_minus1} = dat_req_addr_w-1'b1; +assign is_dat_req_addr_minus1_wrap = (dat_req_addr_minus1 >= {1'b0,data_bank, {9{1'b0}}}); //only one case: 0-1=ffff would introduce wrap +assign dat_req_addr_minus1_wrap = {1'b0,data_bank, {9{1'b1}}}; +assign dat_req_addr_minus1_real = is_dat_req_addr_minus1_wrap ? dat_req_addr_minus1_wrap : dat_req_addr_minus1; +assign sc2buf_dat_rd_en_w = dat_req_valid_d1 & ((dat_req_addr_last != dat_req_addr_w) | pixel_force_fetch_d1); +assign dat_req_addr_last = (dat_req_sub_h_d1 == 2'h0) ? dat_req_sub_h_0_addr : + (dat_req_sub_h_d1 == 2'h1) ? dat_req_sub_h_1_addr : + (dat_req_sub_h_d1 == 2'h2) ? dat_req_sub_h_2_addr : + dat_req_sub_h_3_addr; +assign dat_req_sub_h_0_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h0)); +assign dat_req_sub_h_1_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h1)); +assign dat_req_sub_h_2_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h2)); +assign dat_req_sub_h_3_addr_en = layer_st | ((dat_req_valid_d1 | dat_req_dummy_d1) & (dat_req_sub_h_d1 == 2'h3)); +`ifdef CBUF_BANK_RAM_CASE0 +wire sc2buf_dat_rd_next1_en = 1'b0; +`endif +`ifdef CBUF_BANK_RAM_CASE1 +wire sc2buf_dat_rd_next1_en = 1'b0; +`endif +`ifdef CBUF_BANK_RAM_CASE4 +wire sc2buf_dat_rd_next1_en = 1'b0; +`endif +`ifdef CBUF_BANK_RAM_CASE2 +wire [7 -1:0] sc2buf_dat_rd_shift_w; +wire mon_sc2buf_dat_rd_shift_w; +wire sc2buf_dat_rd_next1_en_w; +wire [14 -1:0] dat_req_addr_last_plus1; +wire [14 -1:0] dat_req_addr_last_plus1_real; +wire is_dat_req_addr_last_plus1_wrap; +wire [14 -1:0] dat_req_addr_last_plus1_wrap; +wire mon_dat_req_addr_last_plus1_wrap; +wire [3:0] pixel_w_cnt_plus1; +wire stripe_begin_disable_jump_w; +//every stripe will start form the head Byte of an entry, no need to jump +assign stripe_begin_disable_jump_w = sub_h_total_g0[2] ? (stripe_cnt[6:2]==5'b0) : //stripe_cnt = 0/1/2/3 + sub_h_total_g0[1] ? (stripe_cnt[6:1]==6'b0) : //stripe_cnt = 0/1 + stripe_cnt==7'b0; //stripe_cnt = 0 +//: my $kk= 3 +1; +//: &eperl::flop("-q stripe_begin_disable_jump -d stripe_begin_disable_jump_w"); +//: &eperl::flop("-wid ${kk} -q pixel_w_cnt_plus1_d1 -d pixel_w_cnt_plus1"); +assign dat_req_addr_last_plus1 = dat_req_addr_last+1'b1; +assign is_dat_req_addr_last_plus1_wrap = (dat_req_addr_last_plus1 >= {data_bank, {9{1'b0}}}); +assign {mon_dat_req_addr_last_plus1_wrap,dat_req_addr_last_plus1_wrap} = dat_req_addr_last_plus1[14 -1:0] - {data_bank, {9{1'b0}}}; +assign dat_req_addr_last_plus1_real = is_dat_req_addr_last_plus1_wrap ? dat_req_addr_last_plus1_wrap : dat_req_addr_last_plus1; +//iamge data may encounter read jump, which happens when image data_read_address - last_rd_address >= 2 entries, and read form the middle of an entry. +//then csc need read 2 entries simultaneously, then shift out unneeded part. +//this address jump should not happened in the begining of a stripe OP. +//assign sc2buf_dat_rd_next1_en_w = is_img_d1[10]&&sc2buf_dat_rd_en_w&&(pixel_x_byte_stride > 8'h08 )&&(dat_req_addr_w != dat_req_addr_last_plus1_real) +// &&(pixel_w_cnt_plus1_d1 8'h08 ) + &&(pixel_w_cnt_plus1_d1 dat_req_pipe_bytes)&&(pixel_x_byte_stride > 8'h08 )? +// pixel_w_cnt_plus1_d1[3:0] - dat_req_pipe_bytes : +// is_img_d1[10]&&(pixel_w_cnt_plus1_d1[3:0]<= dat_req_pipe_bytes)? {7{1'd0}} : +// {7{1'd0}}; //read data, no need to shift +//only when pixel_stride>entry and fetched more data than needed, then need shift +assign {mon_sc2buf_dat_rd_shift_w, sc2buf_dat_rd_shift_w} = + sc2buf_dat_rd_next1_en_w ? pixel_w_cnt_plus1_d1[3 -1:0]+ 7'h08 - dat_req_pipe_bytes: //image read jump +//image read no jump, not image's start,fetch more than needed,not y_ext,then not all bytes are used,need shift out low bytes + is_img_d1[10]&&(pixel_w_cnt_plus1_d1[3:0]> dat_req_pipe_bytes[3:0])&&(~stripe_begin_disable_jump)&&(pixel_x_byte_stride > 8'h08 )? + pixel_w_cnt_plus1_d1[3:0] - dat_req_pipe_bytes[3:0] : {7{1'd0}}; +//: my $kk= 7; +//: &eperl::flop("-d sc2buf_dat_rd_next1_en_w -q sc2buf_dat_rd_next1_en"); +//: &eperl::flop("-d sc2buf_dat_rd_shift_w -q sc2buf_dat_rd_shift -wid ${kk}"); +`endif +wire [14 -1:0] sc2buf_dat_rd_addr_w; +wire [14 -1:0] sc2buf_dat_rd_next1_addr_w; +assign sc2buf_dat_rd_addr_w = sc2buf_dat_rd_next1_en_w ? dat_req_addr_minus1_real : dat_req_addr_w; +assign sc2buf_dat_rd_next1_addr_w = sc2buf_dat_rd_next1_en_w ? dat_req_addr_w : {14{1'b0}}; +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_0_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_0_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_1_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_1_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_2_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_2_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"dat_req_sub_h_3_addr_en\" -d \"dat_req_addr_w\" -q dat_req_sub_h_3_addr"); +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2buf_dat_rd_en_w\" -q sc2buf_dat_rd_en"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"layer_st | sc2buf_dat_rd_en_w\" -d \"sc2buf_dat_rd_addr_w\" -q sc2buf_dat_rd_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b1}}\" -en \"layer_st | sc2buf_dat_rd_en_w\" -d \"sc2buf_dat_rd_next1_addr_w\" -q sc2buf_dat_rd_next1_addr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pipe_valid_d1\" -q dat_pipe_valid_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_exec_valid_d1\" -q dat_exec_valid_d2"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_w_d1\" -q dat_req_sub_w_d2"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_h_d1\" -q dat_req_sub_h_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_c_d1\" -q dat_req_sub_c_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_ch_end_d1\" -q dat_req_ch_end_d2"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_bytes_d1\" -q dat_req_bytes_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_dummy_d1\" -q dat_req_dummy_d2"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_cur_sub_h_d1\" -q dat_req_cur_sub_h_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_sub_w_st_d1\" -q dat_req_sub_w_st_d2"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dat_exec_valid_d1\" -d \"dat_req_rls_d1\" -q dat_req_rls_d2"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_exec_valid_d1\" -d \"dat_req_flag_d1\" -q dat_req_flag_d2"); +////////////////////////////////////////////////////////////// +///// sideband pipeline ///// +////////////////////////////////////////////////////////////// +assign dat_req_pipe_pvld = dat_pipe_valid_d2; +assign dat_req_pipe_sub_w = dat_req_sub_w_d2; +assign dat_req_pipe_sub_h = dat_req_sub_h_d2; +assign dat_req_pipe_sub_c = dat_req_sub_c_d2; +assign dat_req_pipe_ch_end = dat_req_ch_end_d2; +assign dat_req_pipe_bytes = dat_req_bytes_d2; +assign dat_req_pipe_dummy = dat_req_dummy_d2; +assign dat_req_pipe_cur_sub_h = dat_req_cur_sub_h_d2; +assign dat_req_pipe_sub_w_st = dat_req_sub_w_st_d2; +assign dat_req_pipe_rls = dat_req_rls_d2; +assign dat_req_pipe_flag = dat_req_flag_d2; +assign dat_req_exec_pvld = dat_exec_valid_d2; +assign dat_req_exec_dummy = dat_req_dummy_d2; +assign dat_req_exec_sub_h = dat_req_sub_h_d2; +// PKT_PACK_WIRE( csc_dat_req_pkg , dat_req_pipe_ , dat_req_pipe_pd ) +assign dat_req_pipe_pd[1:0] = dat_req_pipe_sub_w[1:0]; +assign dat_req_pipe_pd[3:2] = dat_req_pipe_sub_h[1:0]; +assign dat_req_pipe_pd[4] = dat_req_pipe_sub_c ; +assign dat_req_pipe_pd[5] = dat_req_pipe_ch_end ; +assign dat_req_pipe_pd[6] = 1'b0 ; +assign dat_req_pipe_pd[14:7] = dat_req_pipe_bytes[7:0]; +assign dat_req_pipe_pd[16:15] = dat_req_pipe_cur_sub_h[1:0]; +assign dat_req_pipe_pd[17] = dat_req_pipe_dummy ; +assign dat_req_pipe_pd[18] = dat_req_pipe_sub_w_st ; +assign dat_req_pipe_pd[19] = dat_req_pipe_rls ; +assign dat_req_pipe_pd[28:20] = dat_req_pipe_flag[8:0]; +//add latency for data request contorl signal +//: my $pipe_depth = 6; +//: my $i; +//: my $j; +//: if($pipe_depth == 0) { +//: print "assign dat_rsp_pipe_pvld = dat_req_pipe_pvld;\n"; +//: print "assign dat_rsp_pipe_pd = dat_req_pipe_pd;\n"; +//: print "assign dat_rsp_exec_pvld = dat_req_exec_pvld;\n"; +//: print "assign dat_rsp_exec_dummy = dat_req_exec_dummy;\n"; +//: print "assign dat_rsp_exec_sub_h = dat_req_exec_sub_h;\n\n"; +//: } else { +//: print "assign dat_rsp_pipe_pvld_d0 = dat_req_pipe_pvld;\n"; +//: print "assign dat_rsp_pipe_pd_d0 = dat_req_pipe_pd;\n"; +//: print "assign dat_rsp_exec_pvld_d0 = dat_req_exec_pvld;\n"; +//: print "assign dat_rsp_exec_dummy_d0 = dat_req_exec_dummy;\n"; +//: print "assign dat_rsp_exec_sub_h_d0 = dat_req_exec_sub_h;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dat_rsp_pipe_pvld_d${i}\" -q dat_rsp_pipe_pvld_d${j}"); +//: &eperl::flop("-wid 29 -rval \"{29{1'b0}}\" -en \"dat_rsp_pipe_pvld_d${i}\" -d \"dat_rsp_pipe_pd_d${i}\" -q dat_rsp_pipe_pd_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dat_rsp_exec_pvld_d${i}\" -q dat_rsp_exec_pvld_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -en \"dat_rsp_exec_pvld_d${i}\" -d \"dat_rsp_exec_dummy_d${i}\" -q dat_rsp_exec_dummy_d${j}"); +//: &eperl::flop("-wid 2 -rval \"{2{1'b0}}\" -en \"dat_rsp_exec_pvld_d${i}\" -d \"dat_rsp_exec_sub_h_d${i}\" -q dat_rsp_exec_sub_h_d${j}"); +//: } +//: print "assign dat_rsp_pipe_pvld = dat_rsp_pipe_pvld_d${i};\n"; +//: print "assign dat_rsp_pipe_pd = dat_rsp_pipe_pd_d${i};\n"; +//: print "assign dat_rsp_exec_pvld = dat_rsp_exec_pvld_d${i};\n"; +//: print "assign dat_rsp_exec_dummy = dat_rsp_exec_dummy_d${i};\n"; +//: print "assign dat_rsp_exec_sub_h = dat_rsp_exec_sub_h_d${i};\n\n"; +//: } +// PKT_UNPACK_WIRE( csc_dat_req_pkg , dat_rsp_pipe_ , dat_rsp_pipe_pd ) +assign dat_rsp_pipe_sub_w[1:0] = dat_rsp_pipe_pd[1:0]; +assign dat_rsp_pipe_sub_h[1:0] = dat_rsp_pipe_pd[3:2]; +assign dat_rsp_pipe_sub_c = dat_rsp_pipe_pd[4]; +assign dat_rsp_pipe_ch_end = dat_rsp_pipe_pd[5]; +assign dat_rsp_pipe_bytes[7:0] = dat_rsp_pipe_pd[14:7]; +assign dat_rsp_pipe_cur_sub_h[1:0] = dat_rsp_pipe_pd[16:15]; +assign dat_rsp_pipe_dummy = dat_rsp_pipe_pd[17]; +assign dat_rsp_pipe_sub_w_st = dat_rsp_pipe_pd[18]; +assign dat_rsp_pipe_rls = dat_rsp_pipe_pd[19]; +assign dat_rsp_pipe_flag[8:0] = dat_rsp_pipe_pd[28:20]; +////////////////////////////////////////////////////////////// +///// dl data cache ///// +////////////////////////////////////////////////////////////// +assign dat_l0c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h0)); +assign dat_l1c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h1)); +assign dat_l2c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h2)); +assign dat_l3c0_en = (sc2buf_dat_rd_valid & (dat_rsp_exec_sub_h == 2'h3)); +//only winograd/image +assign dat_l0c1_en = (dat_wg_adv & ~dat_rsp_exec_sub_h[0]) | (is_img_d1[12] & dat_l0c0_en & ~dat_l0c0_dummy); +assign dat_l1c1_en = (dat_wg_adv & dat_rsp_exec_sub_h[0]) | (is_img_d1[13] & dat_l1c0_en & ~dat_l1c0_dummy); +assign dat_l2c1_en = (is_img_d1[15] & dat_l2c0_en & ~dat_l2c0_dummy); +assign dat_l3c1_en = (is_img_d1[16] & dat_l3c0_en & ~dat_l3c0_dummy); +assign dat_dummy_l0_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h0); +assign dat_dummy_l1_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h1); +assign dat_dummy_l2_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h2); +assign dat_dummy_l3_en = dat_rsp_exec_pvld & dat_rsp_exec_dummy & (dat_rsp_exec_sub_h == 2'h3); +assign dat_wg_adv = sc2buf_dat_rd_valid & is_winograd_d1[11] & ~dat_rsp_pipe_sub_w_st; +assign dat_l0c0_dummy_w = dat_l0c0_en ? 1'b0 : dat_dummy_l0_en ? 1'b1 : dat_l0c0_dummy; +assign dat_l1c0_dummy_w = dat_l1c0_en ? 1'b0 : dat_dummy_l1_en ? 1'b1 : dat_l1c0_dummy; +assign dat_l2c0_dummy_w = dat_l2c0_en ? 1'b0 : dat_dummy_l2_en ? 1'b1 : dat_l2c0_dummy; +assign dat_l3c0_dummy_w = dat_l3c0_en ? 1'b0 : dat_dummy_l3_en ? 1'b1 : dat_l3c0_dummy; +assign dat_l0c1_dummy_w = dat_l0c1_en ? 1'b0 : (dat_l0_set) ? dat_l0c0_dummy : dat_l0c1_dummy; +assign dat_l1c1_dummy_w = dat_l1c1_en ? 1'b0 : (dat_l1_set & (|sub_h_total_g2)) ? dat_l1c0_dummy : dat_l1c1_dummy; +assign dat_l2c1_dummy_w = dat_l2c1_en ? 1'b0 : (dat_l2_set & sub_h_total_g2[1]) ? dat_l2c0_dummy : dat_l2c1_dummy; +assign dat_l3c1_dummy_w = dat_l3c1_en ? 1'b0 : (dat_l3_set & sub_h_total_g2[1]) ? dat_l3c0_dummy : dat_l3c1_dummy; +assign dat_l0_set = dat_l0c0_en | dat_dummy_l0_en; +assign dat_l1_set = dat_l1c0_en | dat_dummy_l1_en; +assign dat_l2_set = dat_l2c0_en | dat_dummy_l2_en; +assign dat_l3_set = dat_l3c0_en | dat_dummy_l3_en; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l0c0_dummy_w\" -q dat_l0c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l1c0_dummy_w\" -q dat_l1c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l2c0_dummy_w\" -q dat_l2c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l3c0_dummy_w\" -q dat_l3c0_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l0c1_dummy_w\" -q dat_l0c1_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l1c1_dummy_w\" -q dat_l1c1_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l2c1_dummy_w\" -q dat_l2c1_dummy"); +//: &eperl::flop("-nodeclare -rval \"1'b1\" -d \"dat_l3c1_dummy_w\" -q dat_l3c1_dummy"); +//: &eperl::flop("-nodeclare -norst -en \"dat_l0c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l0c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l1c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l1c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l2c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l2c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l3c0_en\" -d \"sc2buf_dat_rd_data\" -q dat_l3c0 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l0c1_en\" -d dat_l0c0 -q dat_l0c1 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l1c1_en\" -d dat_l1c0 -q dat_l1c1 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l2c1_en\" -d dat_l2c0 -q dat_l2c1 "); +//: &eperl::flop("-nodeclare -norst -en \"dat_l3c1_en\" -d dat_l3c0 -q dat_l3c1 "); +////////////////////////////////////////////////////////////// +///// response contorl ///// +////////////////////////////////////////////////////////////// +// PKT_PACK_WIRE( csc_dat_rsp_pkg , dat_rsp_pipe_ , dat_rsp_pd_d0 ) +assign dat_rsp_pd_d0[1:0] = dat_rsp_pipe_sub_w[1:0]; +assign dat_rsp_pd_d0[3:2] = dat_rsp_pipe_sub_h[1:0]; +assign dat_rsp_pd_d0[4] = dat_rsp_pipe_sub_c ; +assign dat_rsp_pd_d0[5] = dat_rsp_pipe_ch_end ; +assign dat_rsp_pd_d0[6] = 1'b0 ; +assign dat_rsp_pd_d0[14:7] = dat_rsp_pipe_bytes[7:0]; +assign dat_rsp_pd_d0[16:15] = dat_rsp_pipe_cur_sub_h[1:0]; +assign dat_rsp_pd_d0[17] = dat_rsp_pipe_rls ; +assign dat_rsp_pd_d0[26:18] = dat_rsp_pipe_flag[8:0]; +//add latency +//: my $delay_depth = 4; +//: my $i; +//: my $j; +//: +//: print "assign dat_rsp_pvld_d0 = dat_rsp_pipe_pvld;\n"; +//: for($i = 0; $i < $delay_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_rsp_pvld_d${i}\" -q dat_rsp_pvld_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{27{1'b0}}\" -en \"dat_rsp_pvld_d${i}\" -d \"dat_rsp_pd_d${i}\" -q dat_rsp_pd_d${j}"); +//: } +assign dat_rsp_pvld = (sub_h_total_g3[2] & dat_rsp_pvld_d4) | + (sub_h_total_g3[1] & dat_rsp_pvld_d2) | + (sub_h_total_g3[0] & dat_rsp_pvld_d1); +assign dat_rsp_l0_pvld = dat_rsp_pvld_d1; +assign dat_rsp_l1_pvld = dat_rsp_pvld_d2; +assign dat_rsp_l2_pvld = dat_rsp_pvld_d3; +assign dat_rsp_l3_pvld = dat_rsp_pvld_d4; +assign dat_rsp_pd = ({27 {sub_h_total_g4[2]}} & dat_rsp_pd_d4) | + ({27 {sub_h_total_g4[1]}} & dat_rsp_pd_d2) | + ({27 {sub_h_total_g4[0]}} & dat_rsp_pd_d1); +assign dat_rsp_l0_sub_c = dat_rsp_pd_d1[4:4]; +assign dat_rsp_l1_sub_c = dat_rsp_pd_d2[4:4]; +assign dat_rsp_l2_sub_c = dat_rsp_pd_d3[4:4]; +assign dat_rsp_l3_sub_c = dat_rsp_pd_d4[4:4]; +assign dat_rsp_l0_flag = dat_rsp_pd_d1[26:18]; +assign dat_rsp_l1_flag = dat_rsp_pd_d2[26:18]; +assign dat_rsp_l2_flag = dat_rsp_pd_d3[26:18]; +assign dat_rsp_l3_flag = dat_rsp_pd_d4[26:18]; +assign dat_rsp_l0_stripe_end = dat_rsp_l0_flag[6:6]; +assign dat_rsp_l1_stripe_end = dat_rsp_l1_flag[6:6]; +assign dat_rsp_l2_stripe_end = dat_rsp_l2_flag[6:6]; +assign dat_rsp_l3_stripe_end = dat_rsp_l3_flag[6:6]; +// PKT_UNPACK_WIRE( csc_dat_rsp_pkg , dat_rsp_ , dat_rsp_pd ) +assign dat_rsp_sub_w[1:0] = dat_rsp_pd[1:0]; +assign dat_rsp_sub_h[1:0] = dat_rsp_pd[3:2]; +assign dat_rsp_sub_c = dat_rsp_pd[4]; +assign dat_rsp_ch_end = dat_rsp_pd[5]; +assign dat_rsp_bytes[7:0] = dat_rsp_pd[14:7]; +assign dat_rsp_cur_sub_h[1:0] = dat_rsp_pd[16:15]; +assign dat_rsp_rls = dat_rsp_pd[17]; +assign dat_rsp_flag[8:0] = dat_rsp_pd[26:18]; +// PKT_UNPACK_WIRE( nvdla_stripe_info , dat_rsp_ , dat_rsp_flag ) +assign dat_rsp_batch_index[4:0] = dat_rsp_flag[4:0]; +assign dat_rsp_stripe_st = dat_rsp_flag[5]; +assign dat_rsp_stripe_end = dat_rsp_flag[6]; +assign dat_rsp_channel_end = dat_rsp_flag[7]; +assign dat_rsp_layer_end = dat_rsp_flag[8]; +assign rsp_sft_cnt_l0_sub = dat_l0c0_en ? 8'h08 : 8'h0; +assign rsp_sft_cnt_l1_sub = dat_l1c0_en ? 8'h08 : 8'h0; +assign rsp_sft_cnt_l2_sub = dat_l2c0_en ? 8'h08 : 8'h0; +assign rsp_sft_cnt_l3_sub = dat_l3c0_en ? 8'h08 : 8'h0; +////: &eperl::retime("-O stripe_begin_disable_jump_7T -i stripe_begin_disable_jump -stage 8 -clk nvdla_core_clk"); +////: &eperl::flop("-q stripe_begin_disable_jump_8T -d stripe_begin_disable_jump_7T -clk nvdla_core_clk"); +assign {mon_rsp_sft_cnt_l0_w,rsp_sft_cnt_l0_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l0 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l0_sub); +assign {mon_rsp_sft_cnt_l1_w,rsp_sft_cnt_l1_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l1 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l1_sub); +assign {mon_rsp_sft_cnt_l2_w,rsp_sft_cnt_l2_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l2 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l2_sub); +assign {mon_rsp_sft_cnt_l3_w,rsp_sft_cnt_l3_inc} = (pixel_x_byte_stride > 8'h08 ) ? 8'h08 : + (rsp_sft_cnt_l3 + pixel_x_byte_stride[3:0] - rsp_sft_cnt_l3_sub); +//the data frm cbuf's low Bytes is always needed. High Bytes maybe unneeded. +assign dat_rsp_l0_block_end = dat_rsp_l0_sub_c; +assign dat_rsp_l1_block_end = dat_rsp_l1_sub_c; +assign dat_rsp_l2_block_end = dat_rsp_l2_sub_c; +assign dat_rsp_l3_block_end = dat_rsp_l3_sub_c; +assign rsp_sft_cnt_l0_w = (layer_st) ? 8'h08 : //begin from C0 + (dat_rsp_l0_stripe_end & ~dat_rsp_l0_block_end) ? rsp_sft_cnt_l0_ori : + (dat_rsp_l0_stripe_end & dat_rsp_l0_block_end) ? 8'h08 : + (dat_dummy_l0_en) ? (rsp_sft_cnt_l0_inc & 8'h07) : + rsp_sft_cnt_l0_inc; +assign rsp_sft_cnt_l1_w = (layer_st) ? 8'h08 : + (dat_rsp_l1_stripe_end & ~dat_rsp_l1_block_end) ? rsp_sft_cnt_l1_ori : + (dat_rsp_l1_stripe_end & dat_rsp_l1_block_end) ? 8'h08 : + (dat_dummy_l1_en) ? (rsp_sft_cnt_l1_inc & 8'h07) : + rsp_sft_cnt_l1_inc; +assign rsp_sft_cnt_l2_w = (layer_st) ? 8'h08 : + (dat_rsp_l2_stripe_end & ~dat_rsp_l2_block_end) ? rsp_sft_cnt_l2_ori : + (dat_rsp_l2_stripe_end & dat_rsp_l2_block_end) ? 8'h08 : + (dat_dummy_l2_en) ? (rsp_sft_cnt_l2_inc & 8'h07) : + rsp_sft_cnt_l2_inc; +assign rsp_sft_cnt_l3_w = (layer_st) ? 8'h08 : + (dat_rsp_l3_stripe_end & ~dat_rsp_l3_block_end) ? rsp_sft_cnt_l3_ori : + (dat_rsp_l3_stripe_end & dat_rsp_l3_block_end) ? 8'h08 : + (dat_dummy_l3_en) ? (rsp_sft_cnt_l3_inc & 8'h07) : + rsp_sft_cnt_l3_inc; +assign rsp_sft_cnt_l0_en = layer_st | (is_img_d1[17] & dat_rsp_l0_pvld); +assign rsp_sft_cnt_l1_en = layer_st | (is_img_d1[18] & dat_rsp_l1_pvld & (sub_h_total_g5 != 3'h1)); +assign rsp_sft_cnt_l2_en = layer_st | (is_img_d1[19] & dat_rsp_l2_pvld & (sub_h_total_g5 == 3'h4)); +assign rsp_sft_cnt_l3_en = layer_st | (is_img_d1[20] & dat_rsp_l3_pvld & (sub_h_total_g5 == 3'h4)); +assign rsp_sft_cnt_l0_ori_en = layer_st | (is_img_d1[21] & dat_rsp_l0_pvld & dat_rsp_l0_stripe_end & dat_rsp_l0_block_end); +assign rsp_sft_cnt_l1_ori_en = layer_st | (is_img_d1[22] & dat_rsp_l1_pvld & dat_rsp_l1_stripe_end & dat_rsp_l1_block_end & (sub_h_total_g6 != 3'h1)); +assign rsp_sft_cnt_l2_ori_en = layer_st | (is_img_d1[23] & dat_rsp_l2_pvld & dat_rsp_l2_stripe_end & dat_rsp_l2_block_end & (sub_h_total_g6 == 3'h4)); +assign rsp_sft_cnt_l3_ori_en = layer_st | (is_img_d1[24] & dat_rsp_l3_pvld & dat_rsp_l3_stripe_end & dat_rsp_l3_block_end & (sub_h_total_g6 == 3'h4)); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l0_en\" -d \"rsp_sft_cnt_l0_w\" -q rsp_sft_cnt_l0"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l1_en\" -d \"rsp_sft_cnt_l1_w\" -q rsp_sft_cnt_l1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l2_en\" -d \"rsp_sft_cnt_l2_w\" -q rsp_sft_cnt_l2"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l3_en\" -d \"rsp_sft_cnt_l3_w\" -q rsp_sft_cnt_l3"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l0_ori_en\" -d \"rsp_sft_cnt_l0_w\" -q rsp_sft_cnt_l0_ori"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l1_ori_en\" -d \"rsp_sft_cnt_l1_w\" -q rsp_sft_cnt_l1_ori"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l2_ori_en\" -d \"rsp_sft_cnt_l2_w\" -q rsp_sft_cnt_l2_ori"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"rsp_sft_cnt_l3_ori_en\" -d \"rsp_sft_cnt_l3_w\" -q rsp_sft_cnt_l3_ori"); +////////////////////////////////////////////////////////////// +///// response data ///// +////////////////////////////////////////////////////////////// +//////////////// data for winograd //////////////// +//winograd need future update +`ifdef NVDLA_WINOGRAD_ENABLE +//6x6x8byte matrix +assign dat_wg = ~is_winograd_d1[12] ? 2304'b0 : + {dat_l1c0[511:256], dat_l1c1[511:384], + dat_l1c0[255:0], dat_l1c1[255:128], + dat_l0c0[511:256], dat_l0c1[511:384], + dat_l0c0[255:0], dat_l0c1[255:128], + dat_l0c0[511:256], dat_l0c1[511:384], + dat_l0c0[255:0], dat_l0c1[255:128]}; +assign dat_rsp_wg_sel_lt = (~dat_rsp_sub_h[0] & ~dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_lb = (dat_rsp_sub_h[0] & ~dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_rt = (~dat_rsp_sub_h[0] & dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_rb = (dat_rsp_sub_h[0] & dat_rsp_sub_w[0]); +assign dat_rsp_wg_sel_8b_lo = ~dat_rsp_sub_c; +assign dat_rsp_wg_sel_8b_hi = dat_rsp_sub_c; +assign dat_rsp_wg_lt = {dat_wg[1535:1280], dat_wg[1151:896], dat_wg[767:512], dat_wg[383:128]}; +assign dat_rsp_wg_lb = {dat_wg[2303:2048], dat_wg[1919:1664], dat_wg[1535:1280], dat_wg[1151:896]}; +assign dat_rsp_wg_rt = {dat_wg[1407:1152], dat_wg[1023:768], dat_wg[639:384], dat_wg[255:0]}; +assign dat_rsp_wg_rb = {dat_wg[2175:1920], dat_wg[1791:1536], dat_wg[1407:1152], dat_wg[1023:768]}; +assign dat_rsp_wg = ({1024{dat_rsp_wg_sel_lt}} & dat_rsp_wg_lt) | + ({1024{dat_rsp_wg_sel_lb}} & dat_rsp_wg_lb) | + ({1024{dat_rsp_wg_sel_rt}} & dat_rsp_wg_rt) | + ({1024{dat_rsp_wg_sel_rb}} & dat_rsp_wg_rb); +`endif +`ifdef NVDLA_PRINT_WINOGRAD +always @ (posedge nvdla_core_clk) +begin + if(dat_rsp_pra_en) + begin + $display("[NVDLA WINOGRAD] data_pre_pra_remap = %01024h", dat_rsp_wg); + $display("[NVDLA WINOGRAD] data_post_pra_remap = %01024h", {dat_rsp_wg_ch3, dat_rsp_wg_ch2, dat_rsp_wg_ch1, dat_rsp_wg_ch0}); + end +end +always @ (posedge nvdla_core_clk) +begin + if(|mon_dat_out_pra_vld) + begin + $display("[NVDLA WINOGRAD] data_pra_out_ch0 = %0256h", dat_pra_dat_ch0); + $display("[NVDLA WINOGRAD] data_pra_out_ch1 = %0256h", dat_pra_dat_ch1); + $display("[NVDLA WINOGRAD] data_pra_out_ch2 = %0256h", dat_pra_dat_ch2); + $display("[NVDLA WINOGRAD] data_pra_out_ch3 = %0256h", dat_pra_dat_ch3); + end +end +assign dat_wg_8b_ch0 = {{8{dat_rsp_wg[15*64+ 7]}}, dat_rsp_wg[15*64+7:15*64], {8{dat_rsp_wg[14*64+ 7]}}, dat_rsp_wg[14*64+7:14*64], {8{dat_rsp_wg[13*64+ 7]}}, dat_rsp_wg[13*64+7:13*64], {8{dat_rsp_wg[12*64+ 7]}}, dat_rsp_wg[12*64+7:12*64], {8{dat_rsp_wg[11*64+ 7]}}, dat_rsp_wg[11*64+7:11*64], {8{dat_rsp_wg[10*64+ 7]}}, dat_rsp_wg[10*64+7:10*64], {8{dat_rsp_wg[9*64+ 7]}}, dat_rsp_wg[9*64+7:9*64], {8{dat_rsp_wg[8*64+ 7]}}, dat_rsp_wg[8*64+7:8*64], {8{dat_rsp_wg[7*64+ 7]}}, dat_rsp_wg[7*64+7:7*64], {8{dat_rsp_wg[6*64+ 7]}}, dat_rsp_wg[6*64+7:6*64], {8{dat_rsp_wg[5*64+ 7]}}, dat_rsp_wg[5*64+7:5*64], {8{dat_rsp_wg[4*64+ 7]}}, dat_rsp_wg[4*64+7:4*64], {8{dat_rsp_wg[3*64+ 7]}}, dat_rsp_wg[3*64+7:3*64], {8{dat_rsp_wg[2*64+ 7]}}, dat_rsp_wg[2*64+7:2*64], {8{dat_rsp_wg[1*64+ 7]}}, dat_rsp_wg[1*64+7:1*64], {8{dat_rsp_wg[0*64+ 7]}}, dat_rsp_wg[0*64+7:0*64]}; +assign dat_wg_8b_ch1 = {{8{dat_rsp_wg[15*64+15]}}, dat_rsp_wg[15*64+15:15*64+8], {8{dat_rsp_wg[14*64+15]}}, dat_rsp_wg[14*64+15:14*64+8], {8{dat_rsp_wg[13*64+15]}}, dat_rsp_wg[13*64+15:13*64+8], {8{dat_rsp_wg[12*64+15]}}, dat_rsp_wg[12*64+15:12*64+8], {8{dat_rsp_wg[11*64+15]}}, dat_rsp_wg[11*64+15:11*64+8], {8{dat_rsp_wg[10*64+15]}}, dat_rsp_wg[10*64+15:10*64+8], {8{dat_rsp_wg[9*64+15]}}, dat_rsp_wg[9*64+15:9*64+8], {8{dat_rsp_wg[8*64+15]}}, dat_rsp_wg[8*64+15:8*64+8], {8{dat_rsp_wg[7*64+15]}}, dat_rsp_wg[7*64+15:7*64+8], {8{dat_rsp_wg[6*64+15]}}, dat_rsp_wg[6*64+15:6*64+8], {8{dat_rsp_wg[5*64+15]}}, dat_rsp_wg[5*64+15:5*64+8], {8{dat_rsp_wg[4*64+15]}}, dat_rsp_wg[4*64+15:4*64+8], {8{dat_rsp_wg[3*64+15]}}, dat_rsp_wg[3*64+15:3*64+8], {8{dat_rsp_wg[2*64+15]}}, dat_rsp_wg[2*64+15:2*64+8], {8{dat_rsp_wg[1*64+15]}}, dat_rsp_wg[1*64+15:1*64+8], {8{dat_rsp_wg[0*64+15]}}, dat_rsp_wg[0*64+15:0*64+8]}; +assign dat_wg_8b_ch2 = {{8{dat_rsp_wg[15*64+23]}}, dat_rsp_wg[15*64+23:15*64+16], {8{dat_rsp_wg[14*64+23]}}, dat_rsp_wg[14*64+23:14*64+16], {8{dat_rsp_wg[13*64+23]}}, dat_rsp_wg[13*64+23:13*64+16], {8{dat_rsp_wg[12*64+23]}}, dat_rsp_wg[12*64+23:12*64+16], {8{dat_rsp_wg[11*64+23]}}, dat_rsp_wg[11*64+23:11*64+16], {8{dat_rsp_wg[10*64+23]}}, dat_rsp_wg[10*64+23:10*64+16], {8{dat_rsp_wg[9*64+23]}}, dat_rsp_wg[9*64+23:9*64+16], {8{dat_rsp_wg[8*64+23]}}, dat_rsp_wg[8*64+23:8*64+16], {8{dat_rsp_wg[7*64+23]}}, dat_rsp_wg[7*64+23:7*64+16], {8{dat_rsp_wg[6*64+23]}}, dat_rsp_wg[6*64+23:6*64+16], {8{dat_rsp_wg[5*64+23]}}, dat_rsp_wg[5*64+23:5*64+16], {8{dat_rsp_wg[4*64+23]}}, dat_rsp_wg[4*64+23:4*64+16], {8{dat_rsp_wg[3*64+23]}}, dat_rsp_wg[3*64+23:3*64+16], {8{dat_rsp_wg[2*64+23]}}, dat_rsp_wg[2*64+23:2*64+16], {8{dat_rsp_wg[1*64+23]}}, dat_rsp_wg[1*64+23:1*64+16], {8{dat_rsp_wg[0*64+23]}}, dat_rsp_wg[0*64+23:0*64+16]}; +assign dat_wg_8b_ch3 = {{8{dat_rsp_wg[15*64+31]}}, dat_rsp_wg[15*64+31:15*64+24], {8{dat_rsp_wg[14*64+31]}}, dat_rsp_wg[14*64+31:14*64+24], {8{dat_rsp_wg[13*64+31]}}, dat_rsp_wg[13*64+31:13*64+24], {8{dat_rsp_wg[12*64+31]}}, dat_rsp_wg[12*64+31:12*64+24], {8{dat_rsp_wg[11*64+31]}}, dat_rsp_wg[11*64+31:11*64+24], {8{dat_rsp_wg[10*64+31]}}, dat_rsp_wg[10*64+31:10*64+24], {8{dat_rsp_wg[9*64+31]}}, dat_rsp_wg[9*64+31:9*64+24], {8{dat_rsp_wg[8*64+31]}}, dat_rsp_wg[8*64+31:8*64+24], {8{dat_rsp_wg[7*64+31]}}, dat_rsp_wg[7*64+31:7*64+24], {8{dat_rsp_wg[6*64+31]}}, dat_rsp_wg[6*64+31:6*64+24], {8{dat_rsp_wg[5*64+31]}}, dat_rsp_wg[5*64+31:5*64+24], {8{dat_rsp_wg[4*64+31]}}, dat_rsp_wg[4*64+31:4*64+24], {8{dat_rsp_wg[3*64+31]}}, dat_rsp_wg[3*64+31:3*64+24], {8{dat_rsp_wg[2*64+31]}}, dat_rsp_wg[2*64+31:2*64+24], {8{dat_rsp_wg[1*64+31]}}, dat_rsp_wg[1*64+31:1*64+24], {8{dat_rsp_wg[0*64+31]}}, dat_rsp_wg[0*64+31:0*64+24]}; +assign dat_wg_8b_ch4 = {{8{dat_rsp_wg[15*64+39]}}, dat_rsp_wg[15*64+39:15*64+32], {8{dat_rsp_wg[14*64+39]}}, dat_rsp_wg[14*64+39:14*64+32], {8{dat_rsp_wg[13*64+39]}}, dat_rsp_wg[13*64+39:13*64+32], {8{dat_rsp_wg[12*64+39]}}, dat_rsp_wg[12*64+39:12*64+32], {8{dat_rsp_wg[11*64+39]}}, dat_rsp_wg[11*64+39:11*64+32], {8{dat_rsp_wg[10*64+39]}}, dat_rsp_wg[10*64+39:10*64+32], {8{dat_rsp_wg[9*64+39]}}, dat_rsp_wg[9*64+39:9*64+32], {8{dat_rsp_wg[8*64+39]}}, dat_rsp_wg[8*64+39:8*64+32], {8{dat_rsp_wg[7*64+39]}}, dat_rsp_wg[7*64+39:7*64+32], {8{dat_rsp_wg[6*64+39]}}, dat_rsp_wg[6*64+39:6*64+32], {8{dat_rsp_wg[5*64+39]}}, dat_rsp_wg[5*64+39:5*64+32], {8{dat_rsp_wg[4*64+39]}}, dat_rsp_wg[4*64+39:4*64+32], {8{dat_rsp_wg[3*64+39]}}, dat_rsp_wg[3*64+39:3*64+32], {8{dat_rsp_wg[2*64+39]}}, dat_rsp_wg[2*64+39:2*64+32], {8{dat_rsp_wg[1*64+39]}}, dat_rsp_wg[1*64+39:1*64+32], {8{dat_rsp_wg[0*64+39]}}, dat_rsp_wg[0*64+39:0*64+32]}; +assign dat_wg_8b_ch5 = {{8{dat_rsp_wg[15*64+47]}}, dat_rsp_wg[15*64+47:15*64+40], {8{dat_rsp_wg[14*64+47]}}, dat_rsp_wg[14*64+47:14*64+40], {8{dat_rsp_wg[13*64+47]}}, dat_rsp_wg[13*64+47:13*64+40], {8{dat_rsp_wg[12*64+47]}}, dat_rsp_wg[12*64+47:12*64+40], {8{dat_rsp_wg[11*64+47]}}, dat_rsp_wg[11*64+47:11*64+40], {8{dat_rsp_wg[10*64+47]}}, dat_rsp_wg[10*64+47:10*64+40], {8{dat_rsp_wg[9*64+47]}}, dat_rsp_wg[9*64+47:9*64+40], {8{dat_rsp_wg[8*64+47]}}, dat_rsp_wg[8*64+47:8*64+40], {8{dat_rsp_wg[7*64+47]}}, dat_rsp_wg[7*64+47:7*64+40], {8{dat_rsp_wg[6*64+47]}}, dat_rsp_wg[6*64+47:6*64+40], {8{dat_rsp_wg[5*64+47]}}, dat_rsp_wg[5*64+47:5*64+40], {8{dat_rsp_wg[4*64+47]}}, dat_rsp_wg[4*64+47:4*64+40], {8{dat_rsp_wg[3*64+47]}}, dat_rsp_wg[3*64+47:3*64+40], {8{dat_rsp_wg[2*64+47]}}, dat_rsp_wg[2*64+47:2*64+40], {8{dat_rsp_wg[1*64+47]}}, dat_rsp_wg[1*64+47:1*64+40], {8{dat_rsp_wg[0*64+47]}}, dat_rsp_wg[0*64+47:0*64+40]}; +assign dat_wg_8b_ch6 = {{8{dat_rsp_wg[15*64+55]}}, dat_rsp_wg[15*64+55:15*64+48], {8{dat_rsp_wg[14*64+55]}}, dat_rsp_wg[14*64+55:14*64+48], {8{dat_rsp_wg[13*64+55]}}, dat_rsp_wg[13*64+55:13*64+48], {8{dat_rsp_wg[12*64+55]}}, dat_rsp_wg[12*64+55:12*64+48], {8{dat_rsp_wg[11*64+55]}}, dat_rsp_wg[11*64+55:11*64+48], {8{dat_rsp_wg[10*64+55]}}, dat_rsp_wg[10*64+55:10*64+48], {8{dat_rsp_wg[9*64+55]}}, dat_rsp_wg[9*64+55:9*64+48], {8{dat_rsp_wg[8*64+55]}}, dat_rsp_wg[8*64+55:8*64+48], {8{dat_rsp_wg[7*64+55]}}, dat_rsp_wg[7*64+55:7*64+48], {8{dat_rsp_wg[6*64+55]}}, dat_rsp_wg[6*64+55:6*64+48], {8{dat_rsp_wg[5*64+55]}}, dat_rsp_wg[5*64+55:5*64+48], {8{dat_rsp_wg[4*64+55]}}, dat_rsp_wg[4*64+55:4*64+48], {8{dat_rsp_wg[3*64+55]}}, dat_rsp_wg[3*64+55:3*64+48], {8{dat_rsp_wg[2*64+55]}}, dat_rsp_wg[2*64+55:2*64+48], {8{dat_rsp_wg[1*64+55]}}, dat_rsp_wg[1*64+55:1*64+48], {8{dat_rsp_wg[0*64+55]}}, dat_rsp_wg[0*64+55:0*64+48]}; +assign dat_wg_8b_ch7 = {{8{dat_rsp_wg[15*64+63]}}, dat_rsp_wg[15*64+63:15*64+56], {8{dat_rsp_wg[14*64+63]}}, dat_rsp_wg[14*64+63:14*64+56], {8{dat_rsp_wg[13*64+63]}}, dat_rsp_wg[13*64+63:13*64+56], {8{dat_rsp_wg[12*64+63]}}, dat_rsp_wg[12*64+63:12*64+56], {8{dat_rsp_wg[11*64+63]}}, dat_rsp_wg[11*64+63:11*64+56], {8{dat_rsp_wg[10*64+63]}}, dat_rsp_wg[10*64+63:10*64+56], {8{dat_rsp_wg[9*64+63]}}, dat_rsp_wg[9*64+63:9*64+56], {8{dat_rsp_wg[8*64+63]}}, dat_rsp_wg[8*64+63:8*64+56], {8{dat_rsp_wg[7*64+63]}}, dat_rsp_wg[7*64+63:7*64+56], {8{dat_rsp_wg[6*64+63]}}, dat_rsp_wg[6*64+63:6*64+56], {8{dat_rsp_wg[5*64+63]}}, dat_rsp_wg[5*64+63:5*64+56], {8{dat_rsp_wg[4*64+63]}}, dat_rsp_wg[4*64+63:4*64+56], {8{dat_rsp_wg[3*64+63]}}, dat_rsp_wg[3*64+63:3*64+56], {8{dat_rsp_wg[2*64+63]}}, dat_rsp_wg[2*64+63:2*64+56], {8{dat_rsp_wg[1*64+63]}}, dat_rsp_wg[1*64+63:1*64+56], {8{dat_rsp_wg[0*64+63]}}, dat_rsp_wg[0*64+63:0*64+56]}; +//winograd need future update +assign dat_rsp_wg_ch0 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch0) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch4); +assign dat_rsp_wg_ch1 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch1) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch5); +assign dat_rsp_wg_ch2 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch2) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch6); +assign dat_rsp_wg_ch3 = ({256{dat_rsp_wg_sel_8b_lo}} & dat_wg_8b_ch3) | + ({256{dat_rsp_wg_sel_8b_hi}} & dat_wg_8b_ch7); +`endif +//////////////// data for convlution //////////////// +assign dat_rsp_pad_value = {8{pad_value[7:0]}}; +assign dat_rsp_l0c0 = dat_l0c0_dummy ? dat_rsp_pad_value : dat_l0c0; +assign dat_rsp_l1c0 = dat_l1c0_dummy ? dat_rsp_pad_value : dat_l1c0; +assign dat_rsp_l2c0 = dat_l2c0_dummy ? dat_rsp_pad_value : dat_l2c0; +assign dat_rsp_l3c0 = dat_l3c0_dummy ? dat_rsp_pad_value : dat_l3c0; +assign dat_rsp_l0c1 = dat_l0c1_dummy ? dat_rsp_pad_value : dat_l0c1; +assign dat_rsp_l1c1 = dat_l1c1_dummy ? dat_rsp_pad_value : dat_l1c1; +assign dat_rsp_l2c1 = dat_l2c1_dummy ? dat_rsp_pad_value : dat_l2c1; +assign dat_rsp_l3c1 = dat_l3c1_dummy ? dat_rsp_pad_value : dat_l3c1; +//several atomM may combine together as an entry +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_1 +assign dat_rsp_conv_8b = (is_winograd_d1[14] | is_img_d1[26]) ? {64{1'b0}} : + dat_rsp_l0c0; +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_2 +assign dat_rsp_conv_8b = (is_winograd_d1[14] | is_img_d1[26]) ? {64{1'b0}} : +((dat_rsp_bytes <= 8'h04)&((dat_rsp_sub_w[0] == 1'h0))) ? {{64/2{1'b0}}, dat_rsp_l0c0[64/2 -1:0]} : +((dat_rsp_bytes <= 8'h04)&((dat_rsp_sub_w[0] == 1'h1))) ? {{64/2{1'b0}}, dat_rsp_l0c0[64 -1:64/2]} : + dat_rsp_l0c0; +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_4 +assign dat_rsp_conv_8b = (is_winograd_d1[14] | is_img_d1[26]) ? {64{1'b0}} : +((dat_rsp_bytes <= 8'h04)&(dat_rsp_bytes > 8'h2)&((dat_rsp_sub_w[0] == 1'h0))) ? + {{64/2{1'b0}}, dat_rsp_l0c0[64/2 -1:0]} : +((dat_rsp_bytes <= 8'h04)&(dat_rsp_bytes > 8'h2)&((dat_rsp_sub_w[0] == 1'h1))) ? + {{64/2{1'b0}}, dat_rsp_l0c0[64 -1:64/2]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h0)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64/4 -1:0]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h1)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64/2 -1:64/4]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h2)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64*3/4 -1:64/2]} : +((dat_rsp_bytes <= 8'h2) & (dat_rsp_sub_w == 2'h3)) ? {{64*3/4{1'b0}}, dat_rsp_l0c0[64 -1:64*3/4]} : +dat_rsp_l0c0; +`endif +assign dat_rsp_conv = dat_rsp_conv_8b; +//////////////// data for image //////////////// +assign dat_rsp_l0_sft_in = ~is_img_d1[27] ? 'b0 : {dat_rsp_l0c0, dat_rsp_l0c1}; +assign dat_rsp_l1_sft_in = ~is_img_d1[28] ? 'b0 : {dat_rsp_l1c0, dat_rsp_l1c1}; +assign dat_rsp_l2_sft_in = ~is_img_d1[29] ? 'b0 : {dat_rsp_l2c0, dat_rsp_l2c1}; +assign dat_rsp_l3_sft_in = ~is_img_d1[30] ? 'b0 : {dat_rsp_l3c0, dat_rsp_l3c1}; +assign {mon_dat_rsp_l0_sft, dat_rsp_l0_sft} = dat_rsp_l0_sft_in >> {rsp_sft_cnt_l0, 3'b0}; +assign {mon_dat_rsp_l1_sft, dat_rsp_l1_sft} = dat_rsp_l1_sft_in >> {rsp_sft_cnt_l1, 3'b0}; +assign {mon_dat_rsp_l2_sft, dat_rsp_l2_sft} = dat_rsp_l2_sft_in >> {rsp_sft_cnt_l2, 3'b0}; +assign {mon_dat_rsp_l3_sft, dat_rsp_l3_sft} = dat_rsp_l3_sft_in >> {rsp_sft_cnt_l3, 3'b0}; +assign dat_rsp_img_8b = (~is_img_d1[32])? 'b0 : + (sub_h_total_g8 == 3'h4) ? {dat_rsp_l3_sft[64/4 -1:0], dat_rsp_l2_sft_d3[64/4 -1:0], dat_rsp_l1_sft_d3[64/4 -1:0], dat_rsp_l0_sft_d3[64/4 -1:0]} : + (sub_h_total_g8 == 3'h2) ? {dat_rsp_l1_sft[64/2 -1:0], dat_rsp_l0_sft_d1[64/2 -1:0]} : + dat_rsp_l0_sft[64 -1:0]; +assign dat_rsp_img = dat_rsp_img_8b; +wire dat_rsp_sft_d1_en = dat_rsp_l0_pvld & (sub_h_total_g9 != 3'h1); +wire dat_rsp_sft_d2_en = dat_rsp_l1_pvld & (sub_h_total_g9 == 3'h4); +wire dat_rsp_sft_d3_en = dat_rsp_l2_pvld & (sub_h_total_g9 == 3'h4); +//: my $half=64/2; +//: my $quat=64/4; +//: &eperl::flop("-nodeclare -wid ${half} -norst -en \"dat_rsp_sft_d1_en\" -d \"dat_rsp_l0_sft\" -q dat_rsp_l0_sft_d1"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d2_en\" -d \"dat_rsp_l0_sft_d1\" -q dat_rsp_l0_sft_d2"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d3_en\" -d \"dat_rsp_l0_sft_d2\" -q dat_rsp_l0_sft_d3"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d2_en\" -d \"dat_rsp_l1_sft\" -q dat_rsp_l1_sft_d2"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d3_en\" -d \"dat_rsp_l1_sft_d2\" -q dat_rsp_l1_sft_d3"); +//: &eperl::flop("-nodeclare -wid ${quat} -norst -en \"dat_rsp_sft_d3_en\" -d \"dat_rsp_l2_sft\" -q dat_rsp_l2_sft_d3"); +//////////////// byte mask //////////////// +//sub_h_total=2, each sub_h align to 1/2 entry; +//sub_h_total=4, each sub_h align to 1/4 entry; +assign dat_rsp_ori_mask = ~({8{1'b1}} << dat_rsp_bytes); +assign dat_rsp_cur_h_mask_p1 = (dat_rsp_cur_sub_h >= 2'h1) ? {8{1'b1}} : 'b0; +assign dat_rsp_cur_h_mask_p2 = (dat_rsp_cur_sub_h >= 2'h2) ? {8/2{1'b1}} : 'b0; +assign dat_rsp_cur_h_mask_p3 = (dat_rsp_cur_sub_h == 2'h3) ? {8/2{1'b1}} : 'b0; +assign dat_rsp_cur_h_e2_mask_8b = {dat_rsp_cur_h_mask_p1[8/2 -1:0], {8/2{1'b1}}}; +assign dat_rsp_cur_h_e4_mask_8b = {dat_rsp_cur_h_mask_p3[8/4 -1:0], dat_rsp_cur_h_mask_p2[8/4 -1:0], dat_rsp_cur_h_mask_p1[8/4 -1:0], {8/4{1'b1}}}; +assign dat_rsp_mask_8b = (sub_h_total_g11 == 3'h4) ? ({4{dat_rsp_ori_mask[8/4 -1:0]}} & dat_rsp_cur_h_e4_mask_8b) : + (sub_h_total_g11 == 3'h2) ? ({2{dat_rsp_ori_mask[8/2 -1:0]}} & dat_rsp_cur_h_e2_mask_8b) : + dat_rsp_ori_mask[8 -1:0]; +assign dat_rsp_data_w = is_img_d1[33] ? dat_rsp_img : + dat_rsp_conv; +//: my $i; +//: my $b1; +//: my $b0; +//: my $kk=8 -1; +//: print "assign dat_rsp_mask_val_int8 = {"; +//: for($i = ${kk}; $i >= 0; $i --) { +//: $b0 = sprintf("%3d", $i * 8); +//: $b1 = sprintf("%3d", $i * 8 + 7); +//: print "(|dat_rsp_data_w[${b1}:${b0}])"; +//: if($i == 0) { +//: print "};\n"; +//: } elsif ($i % 8 == 0) { +//: print ",\n "; +//: } else { +//: print ", "; +//: } +//: } +//: print "\n\n"; +assign dat_rsp_mask_w = (dat_rsp_mask_8b & dat_rsp_mask_val_int8) ; +assign dat_rsp_p1_vld_w = 1'b0; +assign dat_rsp_p0_vld_w = dat_rsp_pvld & ~is_winograd_d1[16]; +////////////////////////////////////////////////////////////// +///// latency register to balance with PRA cell ///// +////////////////////////////////////////////////////////////// +//: my $total_latency = 5; +//: +//: print "assign dat_out_pvld_l0 = dat_rsp_pvld;\n"; +//: print "assign dat_out_flag_l0 = dat_rsp_flag;\n"; +//: for(my $i = 0; $i < $total_latency; $i ++) { +//: my $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"dat_out_pvld_l${i}\" -q dat_out_pvld_l${j}"); +//: &eperl::flop("-wid 9 -rval \"{9{1'b0}}\" -en \"dat_out_pvld_l${i}\" -d \"dat_out_flag_l${i}\" -q dat_out_flag_l${j}"); +//: } +//: +//: my $k = $total_latency; +//: print "assign dat_out_pvld_w = is_winograd_d1[17] ? dat_out_pvld_l${k} : dat_rsp_pvld;\n"; +//: print "assign dat_out_flag_w = is_winograd_d1[18] ? dat_out_flag_l${k} : dat_rsp_flag;\n"; +assign dat_out_bypass_p0_vld_w = dat_rsp_p0_vld_w; +assign dat_out_bypass_mask_w = dat_rsp_mask_w; +assign dat_out_bypass_data_w = dat_rsp_data_w; +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_out_pvld_w\" -q dat_out_pvld"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_out_pvld_w\" -d \"dat_out_flag_w\" -q dat_out_flag"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dat_out_bypass_p0_vld_w\" -d \"dat_out_bypass_mask_w\" -q dat_out_bypass_mask"); +//: for(my $i = 0; $i < 8; $i ++) { +//: my $b0 = $i * 8; +//: my $b1 = $i * 8 + 7; +//: &eperl::flop("-nodeclare -norst -en \"dat_out_bypass_p0_vld_w & dat_out_bypass_mask_w[${i}]\" -d \"dat_out_bypass_data_w[${b1}:${b0}]\" -q dat_out_bypass_data[${b1}:${b0}]"); +//: } +//: +`ifdef NVDLA_WINOGRAD_ENABLE +////////////////////////////////////////////////////////////// +///// PRA units instance ///// +////////////////////////////////////////////////////////////// +assign dat_rsp_pra_en = dat_rsp_pvld & is_winograd_d1[19]; +assign {pra_truncate_3, pra_truncate_2, pra_truncate_1, pra_truncate_0} = pra_truncate; +assign {pra_precision_3, pra_precision_2, pra_precision_1, pra_precision_0} = pra_precision; +//: &eperl::flop("-nodeclare -rval \"{4{1'b0}}\" -d \"{4{dat_rsp_pra_en}}\" -q dat_rsp_pra_en_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch0\" -q dat_rsp_wg_ch0_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch1\" -q dat_rsp_wg_ch1_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch2\" -q dat_rsp_wg_ch2_d1"); +//: &eperl::flop("-nodeclare -norst -en \"dat_rsp_pra_en\" -d \"dat_rsp_wg_ch3\" -q dat_rsp_wg_ch3_d1"); +NV_NVDLA_CSC_pra_cell u_pra_cell_0 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch0_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[0]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[0]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_0[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_0[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch0[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[0]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +NV_NVDLA_CSC_pra_cell u_pra_cell_1 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch1_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[1]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[1]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_1[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_1[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch1[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[1]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +NV_NVDLA_CSC_pra_cell u_pra_cell_2 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch2_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[2]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[2]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_2[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_2[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch2[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[2]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +NV_NVDLA_CSC_pra_cell u_pra_cell_3 ( + .nvdla_core_clk (nvdla_wg_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in_rsc_z (dat_rsp_wg_ch3_d1[255:0]) //|< r + ,.chn_data_in_rsc_vz (dat_rsp_pra_en_d1[3]) //|< r +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_in_rsc_lz (mon_dat_rsp_pra_rdy[3]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.cfg_precision (pra_precision_3[1:0]) //|< w + ,.cfg_truncate_rsc_z (pra_truncate_3[1:0]) //|< w + ,.chn_data_out_rsc_z (dat_pra_dat_ch3[255:0]) //|> w + ,.chn_data_out_rsc_vz (1'b1) //|< ? +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ,.chn_data_out_rsc_lz (mon_dat_out_pra_vld[3]) //|> w * +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + ); +assign dat_pra_dat = {dat_pra_dat_ch3, dat_pra_dat_ch2, dat_pra_dat_ch1, dat_pra_dat_ch0}; +assign dat_out_wg_8b = {dat_pra_dat[1015:1008], dat_pra_dat[ 759: 752], dat_pra_dat[ 503: 496], dat_pra_dat[ 247: 240], + dat_pra_dat[ 999: 992], dat_pra_dat[ 743: 736], dat_pra_dat[ 487: 480], dat_pra_dat[ 231: 224], + dat_pra_dat[ 983: 976], dat_pra_dat[ 727: 720], dat_pra_dat[ 471: 464], dat_pra_dat[ 215: 208], + dat_pra_dat[ 967: 960], dat_pra_dat[ 711: 704], dat_pra_dat[ 455: 448], dat_pra_dat[ 199: 192], + dat_pra_dat[ 951: 944], dat_pra_dat[ 695: 688], dat_pra_dat[ 439: 432], dat_pra_dat[ 183: 176], + dat_pra_dat[ 935: 928], dat_pra_dat[ 679: 672], dat_pra_dat[ 423: 416], dat_pra_dat[ 167: 160], + dat_pra_dat[ 919: 912], dat_pra_dat[ 663: 656], dat_pra_dat[ 407: 400], dat_pra_dat[ 151: 144], + dat_pra_dat[ 903: 896], dat_pra_dat[ 647: 640], dat_pra_dat[ 391: 384], dat_pra_dat[ 135: 128], + dat_pra_dat[ 887: 880], dat_pra_dat[ 631: 624], dat_pra_dat[ 375: 368], dat_pra_dat[ 119: 112], + dat_pra_dat[ 871: 864], dat_pra_dat[ 615: 608], dat_pra_dat[ 359: 352], dat_pra_dat[ 103: 96], + dat_pra_dat[ 855: 848], dat_pra_dat[ 599: 592], dat_pra_dat[ 343: 336], dat_pra_dat[ 87: 80], + dat_pra_dat[ 839: 832], dat_pra_dat[ 583: 576], dat_pra_dat[ 327: 320], dat_pra_dat[ 71: 64], + dat_pra_dat[ 823: 816], dat_pra_dat[ 567: 560], dat_pra_dat[ 311: 304], dat_pra_dat[ 55: 48], + dat_pra_dat[ 807: 800], dat_pra_dat[ 551: 544], dat_pra_dat[ 295: 288], dat_pra_dat[ 39: 32], + dat_pra_dat[ 791: 784], dat_pra_dat[ 535: 528], dat_pra_dat[ 279: 272], dat_pra_dat[ 23: 16], + dat_pra_dat[ 775: 768], dat_pra_dat[ 519: 512], dat_pra_dat[ 263: 256], dat_pra_dat[ 7: 0]}; +assign dat_out_wg_data = {2{dat_out_wg_8b}} ; +assign dat_out_wg_mask_int8 = {(|dat_out_wg_data[ 511: 504]), (|dat_out_wg_data[ 503: 496]), (|dat_out_wg_data[ 495: 488]), (|dat_out_wg_data[ 487: 480]), (|dat_out_wg_data[ 479: 472]), (|dat_out_wg_data[ 471: 464]), (|dat_out_wg_data[ 463: 456]), (|dat_out_wg_data[ 455: 448]), + (|dat_out_wg_data[ 447: 440]), (|dat_out_wg_data[ 439: 432]), (|dat_out_wg_data[ 431: 424]), (|dat_out_wg_data[ 423: 416]), (|dat_out_wg_data[ 415: 408]), (|dat_out_wg_data[ 407: 400]), (|dat_out_wg_data[ 399: 392]), (|dat_out_wg_data[ 391: 384]), + (|dat_out_wg_data[ 383: 376]), (|dat_out_wg_data[ 375: 368]), (|dat_out_wg_data[ 367: 360]), (|dat_out_wg_data[ 359: 352]), (|dat_out_wg_data[ 351: 344]), (|dat_out_wg_data[ 343: 336]), (|dat_out_wg_data[ 335: 328]), (|dat_out_wg_data[ 327: 320]), + (|dat_out_wg_data[ 319: 312]), (|dat_out_wg_data[ 311: 304]), (|dat_out_wg_data[ 303: 296]), (|dat_out_wg_data[ 295: 288]), (|dat_out_wg_data[ 287: 280]), (|dat_out_wg_data[ 279: 272]), (|dat_out_wg_data[ 271: 264]), (|dat_out_wg_data[ 263: 256]), + (|dat_out_wg_data[ 255: 248]), (|dat_out_wg_data[ 247: 240]), (|dat_out_wg_data[ 239: 232]), (|dat_out_wg_data[ 231: 224]), (|dat_out_wg_data[ 223: 216]), (|dat_out_wg_data[ 215: 208]), (|dat_out_wg_data[ 207: 200]), (|dat_out_wg_data[ 199: 192]), + (|dat_out_wg_data[ 191: 184]), (|dat_out_wg_data[ 183: 176]), (|dat_out_wg_data[ 175: 168]), (|dat_out_wg_data[ 167: 160]), (|dat_out_wg_data[ 159: 152]), (|dat_out_wg_data[ 151: 144]), (|dat_out_wg_data[ 143: 136]), (|dat_out_wg_data[ 135: 128]), + (|dat_out_wg_data[ 127: 120]), (|dat_out_wg_data[ 119: 112]), (|dat_out_wg_data[ 111: 104]), (|dat_out_wg_data[ 103: 96]), (|dat_out_wg_data[ 95: 88]), (|dat_out_wg_data[ 87: 80]), (|dat_out_wg_data[ 79: 72]), (|dat_out_wg_data[ 71: 64]), + (|dat_out_wg_data[ 63: 56]), (|dat_out_wg_data[ 55: 48]), (|dat_out_wg_data[ 47: 40]), (|dat_out_wg_data[ 39: 32]), (|dat_out_wg_data[ 31: 24]), (|dat_out_wg_data[ 23: 16]), (|dat_out_wg_data[ 15: 8]), (|dat_out_wg_data[ 7: 0])}; +assign dat_out_wg_mask = {2{dat_out_wg_mask_int8}}; +`else +assign dat_out_wg_data = {64{1'b0}}; +assign dat_out_wg_mask = {8{1'b0}}; +`endif +////////////////////////////////////////////////////////////// +///// finial registers ///// +////////////////////////////////////////////////////////////// +assign dat_out_data = is_winograd_d1[20] ? dat_out_wg_data : dat_out_bypass_data; +assign dat_out_mask = ~dat_out_pvld ? 'b0 : is_winograd_d1[21] ? dat_out_wg_mask : dat_out_bypass_mask; +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_out_pvld\" -q dl_out_pvld"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dat_out_pvld | dl_out_pvld\" -d \"dat_out_mask\" -q dl_out_mask"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dat_out_pvld\" -d \"dat_out_flag\" -q dl_out_flag"); +//: my $i; +//: my $b0; +//: my $b1; +//: my $kk= 8; +//: for($i = 0; $i < 8; $i ++) { +//: $b0 = $i * 8; +//: $b1 = $i * 8 + 7; +//: &eperl::flop("-wid ${kk} -norst -en \"dat_out_mask[$i]\" -d \"dat_out_data[${b1}:${b0}]\" -q dl_out_data${i}"); +//: } +//: print "\n\n\n"; +////////////////////////////////////////////////////////////// +///// registers for retiming ///// +////////////////////////////////////////////////////////////// +assign sc2mac_dat_pd_w = ~dl_out_pvld ? 9'b0 : dl_out_flag; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_out_pvld\" -q dl_out_pvld_d1"); +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_out_pvld\" -q sc2mac_dat_a_pvld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dl_out_pvld\" -q sc2mac_dat_b_pvld"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"sc2mac_dat_pd_w\" -q sc2mac_dat_a_pd"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"sc2mac_dat_pd_w\" -q sc2mac_dat_b_pd"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"dl_out_mask\" -q sc2mac_dat_a_mask"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"dl_out_pvld | dl_out_pvld_d1\" -d \"dl_out_mask\" -q sc2mac_dat_b_mask"); +//: my $i; +//: for($i = 0; $i < 8; $i ++) { +//: &eperl::flop("-wid 8 -norst -en \"dl_out_mask[${i}]\" -d \"dl_out_data${i}\" -q sc2mac_dat_a_data${i}"); +//: } +//: print "\n\n"; +//: +//: for($i = 0; $i < 8; $i ++) { +//: &eperl::flop("-wid 8 -norst -en \"dl_out_mask[${i}]\" -d \"dl_out_data${i}\" -q sc2mac_dat_b_data${i}"); +//: } +//: print "\n\n"; +`ifndef SYNTHESIS +//: for(my $i = 0; $i < 8; $i ++) { +//: print "assign dbg_csc_dat_${i} = sc2mac_dat_a_mask[${i}] ? sc2mac_dat_a_data${i} : 8'h0;\n"; +//: } +//: print "\n\n\n\n"; +//: print "assign dbg_csc_dat = {"; +//: my $kk=8; +//: for(my $i = ${kk}-1; $i >= 0; $i --) { +//: print "dbg_csc_dat_${i}"; +//: if($i != 0) { +//: print ", "; +//: } else { +//: print "};\n\n\n"; +//: } +//: } +`ifdef NVDLA_PRINT_DL +always @ (posedge nvdla_core_clk) +begin + if(layer_st) + begin + $display("[NVDLA DL] layer start"); + end +end +always @ (posedge nvdla_core_clk) +begin + if(sc2mac_dat_a_pvld) + begin + $display("[NVDLA DL] sc2mac_dat = %01024h", dbg_csc_dat); + end +end +`endif +`endif +endmodule // NV_NVDLA_CSC_dl diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v new file mode 100644 index 0000000..49b7bd7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v @@ -0,0 +1,579 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_dual_reg.v +module NV_NVDLA_CSC_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,atomics + ,data_bank + ,weight_bank + ,batches + ,conv_x_stride_ext + ,conv_y_stride_ext + ,cya + ,datain_format + ,datain_height_ext + ,datain_width_ext + ,datain_channel_ext + ,dataout_height + ,dataout_width + ,dataout_channel + ,x_dilation_ext + ,y_dilation_ext + ,entries + ,conv_mode + ,data_reuse + ,in_precision + ,proc_precision + ,skip_data_rls + ,skip_weight_rls + ,weight_reuse + ,op_en_trigger + ,y_extension + ,pra_truncate + ,rls_slices + ,weight_bytes + ,weight_format + ,weight_height_ext + ,weight_width_ext + ,weight_channel_ext + ,weight_kernel + ,wmb_bytes + ,pad_left + ,pad_top + ,pad_value + ,op_en + ); +wire [31:0] nvdla_csc_d_atomics_0_out; +wire [31:0] nvdla_csc_d_bank_0_out; +wire [31:0] nvdla_csc_d_batch_number_0_out; +wire [31:0] nvdla_csc_d_conv_stride_ext_0_out; +wire [31:0] nvdla_csc_d_cya_0_out; +wire [31:0] nvdla_csc_d_datain_format_0_out; +wire [31:0] nvdla_csc_d_datain_size_ext_0_0_out; +wire [31:0] nvdla_csc_d_datain_size_ext_1_0_out; +wire [31:0] nvdla_csc_d_dataout_size_0_0_out; +wire [31:0] nvdla_csc_d_dataout_size_1_0_out; +wire [31:0] nvdla_csc_d_dilation_ext_0_out; +wire [31:0] nvdla_csc_d_entry_per_slice_0_out; +wire [31:0] nvdla_csc_d_misc_cfg_0_out; +wire [31:0] nvdla_csc_d_op_enable_0_out; +wire [31:0] nvdla_csc_d_post_y_extension_0_out; +wire [31:0] nvdla_csc_d_pra_cfg_0_out; +wire [31:0] nvdla_csc_d_release_0_out; +wire [31:0] nvdla_csc_d_weight_bytes_0_out; +wire [31:0] nvdla_csc_d_weight_format_0_out; +wire [31:0] nvdla_csc_d_weight_size_ext_0_0_out; +wire [31:0] nvdla_csc_d_weight_size_ext_1_0_out; +wire [31:0] nvdla_csc_d_wmb_bytes_0_out; +wire [31:0] nvdla_csc_d_zero_padding_0_out; +wire [31:0] nvdla_csc_d_zero_padding_value_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [20:0] atomics; +output [4:0] data_bank; +output [4:0] weight_bank; +output [4:0] batches; +output [2:0] conv_x_stride_ext; +output [2:0] conv_y_stride_ext; +output [31:0] cya; +output datain_format; +output [12:0] datain_height_ext; +output [12:0] datain_width_ext; +output [12:0] datain_channel_ext; +output [12:0] dataout_height; +output [12:0] dataout_width; +output [12:0] dataout_channel; +output [4:0] x_dilation_ext; +output [4:0] y_dilation_ext; +output [13:0] entries; +output conv_mode; +output data_reuse; +output [1:0] in_precision; +output [1:0] proc_precision; +output skip_data_rls; +output skip_weight_rls; +output weight_reuse; +output op_en_trigger; +output [1:0] y_extension; +output [1:0] pra_truncate; +output [11:0] rls_slices; +output [31:0] weight_bytes; +output weight_format; +output [4:0] weight_height_ext; +output [4:0] weight_width_ext; +output [12:0] weight_channel_ext; +output [12:0] weight_kernel; +output [27:0] wmb_bytes; +output [4:0] pad_left; +output [4:0] pad_top; +output [15:0] pad_value; +// Read-only register inputs +input op_en; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [20:0] atomics; +reg [4:0] batches; +reg conv_mode; +reg [2:0] conv_x_stride_ext; +reg [2:0] conv_y_stride_ext; +reg [31:0] cya; +reg [4:0] data_bank; +reg data_reuse; +reg [12:0] datain_channel_ext; +reg datain_format; +reg [12:0] datain_height_ext; +reg [12:0] datain_width_ext; +reg [12:0] dataout_channel; +reg [12:0] dataout_height; +reg [12:0] dataout_width; +reg [13:0] entries; +reg [1:0] in_precision; +reg [4:0] pad_left; +reg [4:0] pad_top; +reg [15:0] pad_value; +reg [1:0] pra_truncate; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [11:0] rls_slices; +reg skip_data_rls; +reg skip_weight_rls; +reg [4:0] weight_bank; +reg [31:0] weight_bytes; +reg [12:0] weight_channel_ext; +reg weight_format; +reg [4:0] weight_height_ext; +reg [12:0] weight_kernel; +reg weight_reuse; +reg [4:0] weight_width_ext; +reg [27:0] wmb_bytes; +reg [4:0] x_dilation_ext; +reg [4:0] y_dilation_ext; +reg [1:0] y_extension; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_csc_d_atomics_0_wren = (reg_offset_wr == (32'h6044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_bank_0_wren = (reg_offset_wr == (32'h605c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_batch_number_0_wren = (reg_offset_wr == (32'h601c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_conv_stride_ext_0_wren = (reg_offset_wr == (32'h604c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_cya_0_wren = (reg_offset_wr == (32'h6064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_datain_format_0_wren = (reg_offset_wr == (32'h6010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_datain_size_ext_0_0_wren = (reg_offset_wr == (32'h6014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_datain_size_ext_1_0_wren = (reg_offset_wr == (32'h6018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_dataout_size_0_0_wren = (reg_offset_wr == (32'h603c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_dataout_size_1_0_wren = (reg_offset_wr == (32'h6040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_dilation_ext_0_wren = (reg_offset_wr == (32'h6050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_entry_per_slice_0_wren = (reg_offset_wr == (32'h6024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_misc_cfg_0_wren = (reg_offset_wr == (32'h600c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_op_enable_0_wren = (reg_offset_wr == (32'h6008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_post_y_extension_0_wren = (reg_offset_wr == (32'h6020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_pra_cfg_0_wren = (reg_offset_wr == (32'h6060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_release_0_wren = (reg_offset_wr == (32'h6048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_bytes_0_wren = (reg_offset_wr == (32'h6034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_format_0_wren = (reg_offset_wr == (32'h6028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_size_ext_0_0_wren = (reg_offset_wr == (32'h602c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_size_ext_1_0_wren = (reg_offset_wr == (32'h6030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_wmb_bytes_0_wren = (reg_offset_wr == (32'h6038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_zero_padding_0_wren = (reg_offset_wr == (32'h6054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_zero_padding_value_0_wren = (reg_offset_wr == (32'h6058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_csc_d_atomics_0_out[31:0] = { 11'b0, atomics }; +assign nvdla_csc_d_bank_0_out[31:0] = { 11'b0, weight_bank, 11'b0, data_bank }; +assign nvdla_csc_d_batch_number_0_out[31:0] = { 27'b0, batches }; +assign nvdla_csc_d_conv_stride_ext_0_out[31:0] = { 13'b0, conv_y_stride_ext, 13'b0, conv_x_stride_ext }; +assign nvdla_csc_d_cya_0_out[31:0] = { cya }; +assign nvdla_csc_d_datain_format_0_out[31:0] = { 31'b0, datain_format }; +assign nvdla_csc_d_datain_size_ext_0_0_out[31:0] = { 3'b0, datain_height_ext, 3'b0, datain_width_ext }; +assign nvdla_csc_d_datain_size_ext_1_0_out[31:0] = { 19'b0, datain_channel_ext }; +assign nvdla_csc_d_dataout_size_0_0_out[31:0] = { 3'b0, dataout_height, 3'b0, dataout_width }; +assign nvdla_csc_d_dataout_size_1_0_out[31:0] = { 19'b0, dataout_channel }; +assign nvdla_csc_d_dilation_ext_0_out[31:0] = { 11'b0, y_dilation_ext, 11'b0, x_dilation_ext }; +assign nvdla_csc_d_entry_per_slice_0_out[31:0] = { 18'b0, entries }; +assign nvdla_csc_d_misc_cfg_0_out[31:0] = { 3'b0, skip_weight_rls, 3'b0, skip_data_rls, 3'b0, weight_reuse, 3'b0, data_reuse, 2'b0, proc_precision, 2'b0, in_precision, 7'b0, conv_mode }; +assign nvdla_csc_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_csc_d_post_y_extension_0_out[31:0] = { 30'b0, y_extension }; +assign nvdla_csc_d_pra_cfg_0_out[31:0] = { 30'b0, pra_truncate }; +assign nvdla_csc_d_release_0_out[31:0] = { 20'b0, rls_slices }; +assign nvdla_csc_d_weight_bytes_0_out[31:0] = weight_bytes; +assign nvdla_csc_d_weight_format_0_out[31:0] = { 31'b0, weight_format }; +assign nvdla_csc_d_weight_size_ext_0_0_out[31:0] = { 11'b0, weight_height_ext, 11'b0, weight_width_ext }; +assign nvdla_csc_d_weight_size_ext_1_0_out[31:0] = { 3'b0, weight_kernel, 3'b0, weight_channel_ext }; +assign nvdla_csc_d_wmb_bytes_0_out[31:0] = { 4'b0, wmb_bytes}; +assign nvdla_csc_d_zero_padding_0_out[31:0] = { 11'b0, pad_top, 11'b0, pad_left }; +assign nvdla_csc_d_zero_padding_value_0_out[31:0] = { 16'b0, pad_value }; +assign op_en_trigger = nvdla_csc_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_csc_d_atomics_0_out + or nvdla_csc_d_bank_0_out + or nvdla_csc_d_batch_number_0_out + or nvdla_csc_d_conv_stride_ext_0_out + or nvdla_csc_d_cya_0_out + or nvdla_csc_d_datain_format_0_out + or nvdla_csc_d_datain_size_ext_0_0_out + or nvdla_csc_d_datain_size_ext_1_0_out + or nvdla_csc_d_dataout_size_0_0_out + or nvdla_csc_d_dataout_size_1_0_out + or nvdla_csc_d_dilation_ext_0_out + or nvdla_csc_d_entry_per_slice_0_out + or nvdla_csc_d_misc_cfg_0_out + or nvdla_csc_d_op_enable_0_out + or nvdla_csc_d_post_y_extension_0_out + or nvdla_csc_d_pra_cfg_0_out + or nvdla_csc_d_release_0_out + or nvdla_csc_d_weight_bytes_0_out + or nvdla_csc_d_weight_format_0_out + or nvdla_csc_d_weight_size_ext_0_0_out + or nvdla_csc_d_weight_size_ext_1_0_out + or nvdla_csc_d_wmb_bytes_0_out + or nvdla_csc_d_zero_padding_0_out + or nvdla_csc_d_zero_padding_value_0_out + ) begin + case (reg_offset_rd_int) + (32'h6044 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_atomics_0_out ; + end + (32'h605c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_bank_0_out ; + end + (32'h601c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_batch_number_0_out ; + end + (32'h604c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_conv_stride_ext_0_out ; + end + (32'h6064 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_cya_0_out ; + end + (32'h6010 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_datain_format_0_out ; + end + (32'h6014 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_datain_size_ext_0_0_out ; + end + (32'h6018 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_datain_size_ext_1_0_out ; + end + (32'h603c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_dataout_size_0_0_out ; + end + (32'h6040 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_dataout_size_1_0_out ; + end + (32'h6050 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_dilation_ext_0_out ; + end + (32'h6024 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_entry_per_slice_0_out ; + end + (32'h600c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_misc_cfg_0_out ; + end + (32'h6008 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_op_enable_0_out ; + end + (32'h6020 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_post_y_extension_0_out ; + end + (32'h6060 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_pra_cfg_0_out ; + end + (32'h6048 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_release_0_out ; + end + (32'h6034 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_bytes_0_out ; + end + (32'h6028 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_format_0_out ; + end + (32'h602c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_size_ext_0_0_out ; + end + (32'h6030 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_size_ext_1_0_out ; + end + (32'h6038 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_wmb_bytes_0_out ; + end + (32'h6054 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_zero_padding_0_out ; + end + (32'h6058 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_zero_padding_value_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + atomics[20:0] <= 21'b000000000000000000001; + data_bank[4:0] <= 5'b00000; + weight_bank[4:0] <= 5'b00000; + batches[4:0] <= 5'b00000; + conv_x_stride_ext[2:0] <= 3'b000; + conv_y_stride_ext[2:0] <= 3'b000; + cya[31:0] <= 32'b00000000000000000000000000000000; + datain_format <= 1'b0; + datain_height_ext[12:0] <= 13'b0000000000000; + datain_width_ext[12:0] <= 13'b0000000000000; + datain_channel_ext[12:0] <= 13'b0000000000000; + dataout_height[12:0] <= 13'b0000000000000; + dataout_width[12:0] <= 13'b0000000000000; + dataout_channel[12:0] <= 13'b0000000000000; + x_dilation_ext[4:0] <= 5'b00000; + y_dilation_ext[4:0] <= 5'b00000; + entries[13:0] <= 14'b00000000000000; + conv_mode <= 1'b0; + data_reuse <= 1'b0; + in_precision[1:0] <= 2'b01; + proc_precision[1:0] <= 2'b01; + skip_data_rls <= 1'b0; + skip_weight_rls <= 1'b0; + weight_reuse <= 1'b0; + y_extension[1:0] <= 2'b00; + pra_truncate[1:0] <= 2'b00; + rls_slices[11:0] <= 12'b000000000001; + weight_bytes[31:0] <= 32'b00000000000000000000000000000000; + weight_format <= 1'b0; + weight_height_ext[4:0] <= 5'b00000; + weight_width_ext[4:0] <= 5'b00000; + weight_channel_ext[12:0] <= 13'b0000000000000; + weight_kernel[12:0] <= 13'b0000000000000; + wmb_bytes[27:0] <= 28'b0000000000000000000000000000; + pad_left[4:0] <= 5'b00000; + pad_top[4:0] <= 5'b00000; + pad_value[15:0] <= 16'b0000000000000000; + end else begin +// Register: NVDLA_CSC_D_ATOMICS_0 Field: atomics + if (nvdla_csc_d_atomics_0_wren) begin + atomics[20:0] <= reg_wr_data[20:0]; + end +// Register: NVDLA_CSC_D_BANK_0 Field: data_bank + if (nvdla_csc_d_bank_0_wren) begin + data_bank[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_BANK_0 Field: weight_bank + if (nvdla_csc_d_bank_0_wren) begin + weight_bank[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_BATCH_NUMBER_0 Field: batches + if (nvdla_csc_d_batch_number_0_wren) begin + batches[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_CONV_STRIDE_EXT_0 Field: conv_x_stride_ext + if (nvdla_csc_d_conv_stride_ext_0_wren) begin + conv_x_stride_ext[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_CSC_D_CONV_STRIDE_EXT_0 Field: conv_y_stride_ext + if (nvdla_csc_d_conv_stride_ext_0_wren) begin + conv_y_stride_ext[2:0] <= reg_wr_data[18:16]; + end +// Register: NVDLA_CSC_D_CYA_0 Field: cya + if (nvdla_csc_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CSC_D_DATAIN_FORMAT_0 Field: datain_format + if (nvdla_csc_d_datain_format_0_wren) begin + datain_format <= reg_wr_data[0]; + end +// Register: NVDLA_CSC_D_DATAIN_SIZE_EXT_0_0 Field: datain_height_ext + if (nvdla_csc_d_datain_size_ext_0_0_wren) begin + datain_height_ext[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CSC_D_DATAIN_SIZE_EXT_0_0 Field: datain_width_ext + if (nvdla_csc_d_datain_size_ext_0_0_wren) begin + datain_width_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DATAIN_SIZE_EXT_1_0 Field: datain_channel_ext + if (nvdla_csc_d_datain_size_ext_1_0_wren) begin + datain_channel_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DATAOUT_SIZE_0_0 Field: dataout_height + if (nvdla_csc_d_dataout_size_0_0_wren) begin + dataout_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CSC_D_DATAOUT_SIZE_0_0 Field: dataout_width + if (nvdla_csc_d_dataout_size_0_0_wren) begin + dataout_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DATAOUT_SIZE_1_0 Field: dataout_channel + if (nvdla_csc_d_dataout_size_1_0_wren) begin + dataout_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DILATION_EXT_0 Field: x_dilation_ext + if (nvdla_csc_d_dilation_ext_0_wren) begin + x_dilation_ext[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_DILATION_EXT_0 Field: y_dilation_ext + if (nvdla_csc_d_dilation_ext_0_wren) begin + y_dilation_ext[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_ENTRY_PER_SLICE_0 Field: entries + if (nvdla_csc_d_entry_per_slice_0_wren) begin + entries[13:0] <= reg_wr_data[13:0]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: conv_mode + if (nvdla_csc_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: data_reuse + if (nvdla_csc_d_misc_cfg_0_wren) begin + data_reuse <= reg_wr_data[16]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: in_precision + if (nvdla_csc_d_misc_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[9:8]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: proc_precision + if (nvdla_csc_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: skip_data_rls + if (nvdla_csc_d_misc_cfg_0_wren) begin + skip_data_rls <= reg_wr_data[24]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: skip_weight_rls + if (nvdla_csc_d_misc_cfg_0_wren) begin + skip_weight_rls <= reg_wr_data[28]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: weight_reuse + if (nvdla_csc_d_misc_cfg_0_wren) begin + weight_reuse <= reg_wr_data[20]; + end +// Not generating flops for field NVDLA_CSC_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_CSC_D_POST_Y_EXTENSION_0 Field: y_extension + if (nvdla_csc_d_post_y_extension_0_wren) begin + y_extension[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CSC_D_PRA_CFG_0 Field: pra_truncate + if (nvdla_csc_d_pra_cfg_0_wren) begin + pra_truncate[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CSC_D_RELEASE_0 Field: rls_slices + if (nvdla_csc_d_release_0_wren) begin + rls_slices[11:0] <= reg_wr_data[11:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_BYTES_0 Field: weight_bytes + if (nvdla_csc_d_weight_bytes_0_wren) begin + weight_bytes[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_FORMAT_0 Field: weight_format + if (nvdla_csc_d_weight_format_0_wren) begin + weight_format <= reg_wr_data[0]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_0_0 Field: weight_height_ext + if (nvdla_csc_d_weight_size_ext_0_0_wren) begin + weight_height_ext[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_0_0 Field: weight_width_ext + if (nvdla_csc_d_weight_size_ext_0_0_wren) begin + weight_width_ext[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_1_0 Field: weight_channel_ext + if (nvdla_csc_d_weight_size_ext_1_0_wren) begin + weight_channel_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_1_0 Field: weight_kernel + if (nvdla_csc_d_weight_size_ext_1_0_wren) begin + weight_kernel[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CSC_D_WMB_BYTES_0 Field: wmb_bytes + if (nvdla_csc_d_wmb_bytes_0_wren) begin + wmb_bytes[27:0] <= reg_wr_data[27:0]; + end +// Register: NVDLA_CSC_D_ZERO_PADDING_0 Field: pad_left + if (nvdla_csc_d_zero_padding_0_wren) begin + pad_left[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_ZERO_PADDING_0 Field: pad_top + if (nvdla_csc_d_zero_padding_0_wren) begin + pad_top[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_ZERO_PADDING_VALUE_0 Field: pad_value + if (nvdla_csc_d_zero_padding_value_0_wren) begin + pad_value[15:0] <= reg_wr_data[15:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h6044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ATOMICS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_atomics_0_out, nvdla_csc_d_atomics_0_out); + (32'h605c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_BANK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_bank_0_out, nvdla_csc_d_bank_0_out); + (32'h601c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_BATCH_NUMBER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_batch_number_0_out, nvdla_csc_d_batch_number_0_out); + (32'h604c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_CONV_STRIDE_EXT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_conv_stride_ext_0_out, nvdla_csc_d_conv_stride_ext_0_out); + (32'h6064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_cya_0_out, nvdla_csc_d_cya_0_out); + (32'h6010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAIN_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_datain_format_0_out, nvdla_csc_d_datain_format_0_out); + (32'h6014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAIN_SIZE_EXT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_datain_size_ext_0_0_out, nvdla_csc_d_datain_size_ext_0_0_out); + (32'h6018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAIN_SIZE_EXT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_datain_size_ext_1_0_out, nvdla_csc_d_datain_size_ext_1_0_out); + (32'h603c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAOUT_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_dataout_size_0_0_out, nvdla_csc_d_dataout_size_0_0_out); + (32'h6040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAOUT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_dataout_size_1_0_out, nvdla_csc_d_dataout_size_1_0_out); + (32'h6050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DILATION_EXT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_dilation_ext_0_out, nvdla_csc_d_dilation_ext_0_out); + (32'h6024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ENTRY_PER_SLICE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_entry_per_slice_0_out, nvdla_csc_d_entry_per_slice_0_out); + (32'h600c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_misc_cfg_0_out, nvdla_csc_d_misc_cfg_0_out); + (32'h6008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_op_enable_0_out, nvdla_csc_d_op_enable_0_out); + (32'h6020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_POST_Y_EXTENSION_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_post_y_extension_0_out, nvdla_csc_d_post_y_extension_0_out); + (32'h6060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_PRA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_pra_cfg_0_out, nvdla_csc_d_pra_cfg_0_out); + (32'h6048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_RELEASE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_release_0_out, nvdla_csc_d_release_0_out); + (32'h6034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_bytes_0_out, nvdla_csc_d_weight_bytes_0_out); + (32'h6028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_format_0_out, nvdla_csc_d_weight_format_0_out); + (32'h602c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_SIZE_EXT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_size_ext_0_0_out, nvdla_csc_d_weight_size_ext_0_0_out); + (32'h6030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_SIZE_EXT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_size_ext_1_0_out, nvdla_csc_d_weight_size_ext_1_0_out); + (32'h6038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WMB_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_wmb_bytes_0_out, nvdla_csc_d_wmb_bytes_0_out); + (32'h6054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ZERO_PADDING_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_zero_padding_0_out, nvdla_csc_d_zero_padding_0_out); + (32'h6058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ZERO_PADDING_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_zero_padding_value_0_out, nvdla_csc_d_zero_padding_value_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CSC_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v.vcp new file mode 100644 index 0000000..49b7bd7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v.vcp @@ -0,0 +1,579 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_dual_reg.v +module NV_NVDLA_CSC_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,atomics + ,data_bank + ,weight_bank + ,batches + ,conv_x_stride_ext + ,conv_y_stride_ext + ,cya + ,datain_format + ,datain_height_ext + ,datain_width_ext + ,datain_channel_ext + ,dataout_height + ,dataout_width + ,dataout_channel + ,x_dilation_ext + ,y_dilation_ext + ,entries + ,conv_mode + ,data_reuse + ,in_precision + ,proc_precision + ,skip_data_rls + ,skip_weight_rls + ,weight_reuse + ,op_en_trigger + ,y_extension + ,pra_truncate + ,rls_slices + ,weight_bytes + ,weight_format + ,weight_height_ext + ,weight_width_ext + ,weight_channel_ext + ,weight_kernel + ,wmb_bytes + ,pad_left + ,pad_top + ,pad_value + ,op_en + ); +wire [31:0] nvdla_csc_d_atomics_0_out; +wire [31:0] nvdla_csc_d_bank_0_out; +wire [31:0] nvdla_csc_d_batch_number_0_out; +wire [31:0] nvdla_csc_d_conv_stride_ext_0_out; +wire [31:0] nvdla_csc_d_cya_0_out; +wire [31:0] nvdla_csc_d_datain_format_0_out; +wire [31:0] nvdla_csc_d_datain_size_ext_0_0_out; +wire [31:0] nvdla_csc_d_datain_size_ext_1_0_out; +wire [31:0] nvdla_csc_d_dataout_size_0_0_out; +wire [31:0] nvdla_csc_d_dataout_size_1_0_out; +wire [31:0] nvdla_csc_d_dilation_ext_0_out; +wire [31:0] nvdla_csc_d_entry_per_slice_0_out; +wire [31:0] nvdla_csc_d_misc_cfg_0_out; +wire [31:0] nvdla_csc_d_op_enable_0_out; +wire [31:0] nvdla_csc_d_post_y_extension_0_out; +wire [31:0] nvdla_csc_d_pra_cfg_0_out; +wire [31:0] nvdla_csc_d_release_0_out; +wire [31:0] nvdla_csc_d_weight_bytes_0_out; +wire [31:0] nvdla_csc_d_weight_format_0_out; +wire [31:0] nvdla_csc_d_weight_size_ext_0_0_out; +wire [31:0] nvdla_csc_d_weight_size_ext_1_0_out; +wire [31:0] nvdla_csc_d_wmb_bytes_0_out; +wire [31:0] nvdla_csc_d_zero_padding_0_out; +wire [31:0] nvdla_csc_d_zero_padding_value_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [20:0] atomics; +output [4:0] data_bank; +output [4:0] weight_bank; +output [4:0] batches; +output [2:0] conv_x_stride_ext; +output [2:0] conv_y_stride_ext; +output [31:0] cya; +output datain_format; +output [12:0] datain_height_ext; +output [12:0] datain_width_ext; +output [12:0] datain_channel_ext; +output [12:0] dataout_height; +output [12:0] dataout_width; +output [12:0] dataout_channel; +output [4:0] x_dilation_ext; +output [4:0] y_dilation_ext; +output [13:0] entries; +output conv_mode; +output data_reuse; +output [1:0] in_precision; +output [1:0] proc_precision; +output skip_data_rls; +output skip_weight_rls; +output weight_reuse; +output op_en_trigger; +output [1:0] y_extension; +output [1:0] pra_truncate; +output [11:0] rls_slices; +output [31:0] weight_bytes; +output weight_format; +output [4:0] weight_height_ext; +output [4:0] weight_width_ext; +output [12:0] weight_channel_ext; +output [12:0] weight_kernel; +output [27:0] wmb_bytes; +output [4:0] pad_left; +output [4:0] pad_top; +output [15:0] pad_value; +// Read-only register inputs +input op_en; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [20:0] atomics; +reg [4:0] batches; +reg conv_mode; +reg [2:0] conv_x_stride_ext; +reg [2:0] conv_y_stride_ext; +reg [31:0] cya; +reg [4:0] data_bank; +reg data_reuse; +reg [12:0] datain_channel_ext; +reg datain_format; +reg [12:0] datain_height_ext; +reg [12:0] datain_width_ext; +reg [12:0] dataout_channel; +reg [12:0] dataout_height; +reg [12:0] dataout_width; +reg [13:0] entries; +reg [1:0] in_precision; +reg [4:0] pad_left; +reg [4:0] pad_top; +reg [15:0] pad_value; +reg [1:0] pra_truncate; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [11:0] rls_slices; +reg skip_data_rls; +reg skip_weight_rls; +reg [4:0] weight_bank; +reg [31:0] weight_bytes; +reg [12:0] weight_channel_ext; +reg weight_format; +reg [4:0] weight_height_ext; +reg [12:0] weight_kernel; +reg weight_reuse; +reg [4:0] weight_width_ext; +reg [27:0] wmb_bytes; +reg [4:0] x_dilation_ext; +reg [4:0] y_dilation_ext; +reg [1:0] y_extension; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_csc_d_atomics_0_wren = (reg_offset_wr == (32'h6044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_bank_0_wren = (reg_offset_wr == (32'h605c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_batch_number_0_wren = (reg_offset_wr == (32'h601c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_conv_stride_ext_0_wren = (reg_offset_wr == (32'h604c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_cya_0_wren = (reg_offset_wr == (32'h6064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_datain_format_0_wren = (reg_offset_wr == (32'h6010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_datain_size_ext_0_0_wren = (reg_offset_wr == (32'h6014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_datain_size_ext_1_0_wren = (reg_offset_wr == (32'h6018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_dataout_size_0_0_wren = (reg_offset_wr == (32'h603c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_dataout_size_1_0_wren = (reg_offset_wr == (32'h6040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_dilation_ext_0_wren = (reg_offset_wr == (32'h6050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_entry_per_slice_0_wren = (reg_offset_wr == (32'h6024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_misc_cfg_0_wren = (reg_offset_wr == (32'h600c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_op_enable_0_wren = (reg_offset_wr == (32'h6008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_post_y_extension_0_wren = (reg_offset_wr == (32'h6020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_pra_cfg_0_wren = (reg_offset_wr == (32'h6060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_release_0_wren = (reg_offset_wr == (32'h6048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_bytes_0_wren = (reg_offset_wr == (32'h6034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_format_0_wren = (reg_offset_wr == (32'h6028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_size_ext_0_0_wren = (reg_offset_wr == (32'h602c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_weight_size_ext_1_0_wren = (reg_offset_wr == (32'h6030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_wmb_bytes_0_wren = (reg_offset_wr == (32'h6038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_zero_padding_0_wren = (reg_offset_wr == (32'h6054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_d_zero_padding_value_0_wren = (reg_offset_wr == (32'h6058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_csc_d_atomics_0_out[31:0] = { 11'b0, atomics }; +assign nvdla_csc_d_bank_0_out[31:0] = { 11'b0, weight_bank, 11'b0, data_bank }; +assign nvdla_csc_d_batch_number_0_out[31:0] = { 27'b0, batches }; +assign nvdla_csc_d_conv_stride_ext_0_out[31:0] = { 13'b0, conv_y_stride_ext, 13'b0, conv_x_stride_ext }; +assign nvdla_csc_d_cya_0_out[31:0] = { cya }; +assign nvdla_csc_d_datain_format_0_out[31:0] = { 31'b0, datain_format }; +assign nvdla_csc_d_datain_size_ext_0_0_out[31:0] = { 3'b0, datain_height_ext, 3'b0, datain_width_ext }; +assign nvdla_csc_d_datain_size_ext_1_0_out[31:0] = { 19'b0, datain_channel_ext }; +assign nvdla_csc_d_dataout_size_0_0_out[31:0] = { 3'b0, dataout_height, 3'b0, dataout_width }; +assign nvdla_csc_d_dataout_size_1_0_out[31:0] = { 19'b0, dataout_channel }; +assign nvdla_csc_d_dilation_ext_0_out[31:0] = { 11'b0, y_dilation_ext, 11'b0, x_dilation_ext }; +assign nvdla_csc_d_entry_per_slice_0_out[31:0] = { 18'b0, entries }; +assign nvdla_csc_d_misc_cfg_0_out[31:0] = { 3'b0, skip_weight_rls, 3'b0, skip_data_rls, 3'b0, weight_reuse, 3'b0, data_reuse, 2'b0, proc_precision, 2'b0, in_precision, 7'b0, conv_mode }; +assign nvdla_csc_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_csc_d_post_y_extension_0_out[31:0] = { 30'b0, y_extension }; +assign nvdla_csc_d_pra_cfg_0_out[31:0] = { 30'b0, pra_truncate }; +assign nvdla_csc_d_release_0_out[31:0] = { 20'b0, rls_slices }; +assign nvdla_csc_d_weight_bytes_0_out[31:0] = weight_bytes; +assign nvdla_csc_d_weight_format_0_out[31:0] = { 31'b0, weight_format }; +assign nvdla_csc_d_weight_size_ext_0_0_out[31:0] = { 11'b0, weight_height_ext, 11'b0, weight_width_ext }; +assign nvdla_csc_d_weight_size_ext_1_0_out[31:0] = { 3'b0, weight_kernel, 3'b0, weight_channel_ext }; +assign nvdla_csc_d_wmb_bytes_0_out[31:0] = { 4'b0, wmb_bytes}; +assign nvdla_csc_d_zero_padding_0_out[31:0] = { 11'b0, pad_top, 11'b0, pad_left }; +assign nvdla_csc_d_zero_padding_value_0_out[31:0] = { 16'b0, pad_value }; +assign op_en_trigger = nvdla_csc_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_csc_d_atomics_0_out + or nvdla_csc_d_bank_0_out + or nvdla_csc_d_batch_number_0_out + or nvdla_csc_d_conv_stride_ext_0_out + or nvdla_csc_d_cya_0_out + or nvdla_csc_d_datain_format_0_out + or nvdla_csc_d_datain_size_ext_0_0_out + or nvdla_csc_d_datain_size_ext_1_0_out + or nvdla_csc_d_dataout_size_0_0_out + or nvdla_csc_d_dataout_size_1_0_out + or nvdla_csc_d_dilation_ext_0_out + or nvdla_csc_d_entry_per_slice_0_out + or nvdla_csc_d_misc_cfg_0_out + or nvdla_csc_d_op_enable_0_out + or nvdla_csc_d_post_y_extension_0_out + or nvdla_csc_d_pra_cfg_0_out + or nvdla_csc_d_release_0_out + or nvdla_csc_d_weight_bytes_0_out + or nvdla_csc_d_weight_format_0_out + or nvdla_csc_d_weight_size_ext_0_0_out + or nvdla_csc_d_weight_size_ext_1_0_out + or nvdla_csc_d_wmb_bytes_0_out + or nvdla_csc_d_zero_padding_0_out + or nvdla_csc_d_zero_padding_value_0_out + ) begin + case (reg_offset_rd_int) + (32'h6044 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_atomics_0_out ; + end + (32'h605c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_bank_0_out ; + end + (32'h601c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_batch_number_0_out ; + end + (32'h604c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_conv_stride_ext_0_out ; + end + (32'h6064 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_cya_0_out ; + end + (32'h6010 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_datain_format_0_out ; + end + (32'h6014 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_datain_size_ext_0_0_out ; + end + (32'h6018 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_datain_size_ext_1_0_out ; + end + (32'h603c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_dataout_size_0_0_out ; + end + (32'h6040 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_dataout_size_1_0_out ; + end + (32'h6050 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_dilation_ext_0_out ; + end + (32'h6024 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_entry_per_slice_0_out ; + end + (32'h600c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_misc_cfg_0_out ; + end + (32'h6008 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_op_enable_0_out ; + end + (32'h6020 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_post_y_extension_0_out ; + end + (32'h6060 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_pra_cfg_0_out ; + end + (32'h6048 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_release_0_out ; + end + (32'h6034 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_bytes_0_out ; + end + (32'h6028 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_format_0_out ; + end + (32'h602c & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_size_ext_0_0_out ; + end + (32'h6030 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_weight_size_ext_1_0_out ; + end + (32'h6038 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_wmb_bytes_0_out ; + end + (32'h6054 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_zero_padding_0_out ; + end + (32'h6058 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_d_zero_padding_value_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + atomics[20:0] <= 21'b000000000000000000001; + data_bank[4:0] <= 5'b00000; + weight_bank[4:0] <= 5'b00000; + batches[4:0] <= 5'b00000; + conv_x_stride_ext[2:0] <= 3'b000; + conv_y_stride_ext[2:0] <= 3'b000; + cya[31:0] <= 32'b00000000000000000000000000000000; + datain_format <= 1'b0; + datain_height_ext[12:0] <= 13'b0000000000000; + datain_width_ext[12:0] <= 13'b0000000000000; + datain_channel_ext[12:0] <= 13'b0000000000000; + dataout_height[12:0] <= 13'b0000000000000; + dataout_width[12:0] <= 13'b0000000000000; + dataout_channel[12:0] <= 13'b0000000000000; + x_dilation_ext[4:0] <= 5'b00000; + y_dilation_ext[4:0] <= 5'b00000; + entries[13:0] <= 14'b00000000000000; + conv_mode <= 1'b0; + data_reuse <= 1'b0; + in_precision[1:0] <= 2'b01; + proc_precision[1:0] <= 2'b01; + skip_data_rls <= 1'b0; + skip_weight_rls <= 1'b0; + weight_reuse <= 1'b0; + y_extension[1:0] <= 2'b00; + pra_truncate[1:0] <= 2'b00; + rls_slices[11:0] <= 12'b000000000001; + weight_bytes[31:0] <= 32'b00000000000000000000000000000000; + weight_format <= 1'b0; + weight_height_ext[4:0] <= 5'b00000; + weight_width_ext[4:0] <= 5'b00000; + weight_channel_ext[12:0] <= 13'b0000000000000; + weight_kernel[12:0] <= 13'b0000000000000; + wmb_bytes[27:0] <= 28'b0000000000000000000000000000; + pad_left[4:0] <= 5'b00000; + pad_top[4:0] <= 5'b00000; + pad_value[15:0] <= 16'b0000000000000000; + end else begin +// Register: NVDLA_CSC_D_ATOMICS_0 Field: atomics + if (nvdla_csc_d_atomics_0_wren) begin + atomics[20:0] <= reg_wr_data[20:0]; + end +// Register: NVDLA_CSC_D_BANK_0 Field: data_bank + if (nvdla_csc_d_bank_0_wren) begin + data_bank[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_BANK_0 Field: weight_bank + if (nvdla_csc_d_bank_0_wren) begin + weight_bank[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_BATCH_NUMBER_0 Field: batches + if (nvdla_csc_d_batch_number_0_wren) begin + batches[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_CONV_STRIDE_EXT_0 Field: conv_x_stride_ext + if (nvdla_csc_d_conv_stride_ext_0_wren) begin + conv_x_stride_ext[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_CSC_D_CONV_STRIDE_EXT_0 Field: conv_y_stride_ext + if (nvdla_csc_d_conv_stride_ext_0_wren) begin + conv_y_stride_ext[2:0] <= reg_wr_data[18:16]; + end +// Register: NVDLA_CSC_D_CYA_0 Field: cya + if (nvdla_csc_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CSC_D_DATAIN_FORMAT_0 Field: datain_format + if (nvdla_csc_d_datain_format_0_wren) begin + datain_format <= reg_wr_data[0]; + end +// Register: NVDLA_CSC_D_DATAIN_SIZE_EXT_0_0 Field: datain_height_ext + if (nvdla_csc_d_datain_size_ext_0_0_wren) begin + datain_height_ext[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CSC_D_DATAIN_SIZE_EXT_0_0 Field: datain_width_ext + if (nvdla_csc_d_datain_size_ext_0_0_wren) begin + datain_width_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DATAIN_SIZE_EXT_1_0 Field: datain_channel_ext + if (nvdla_csc_d_datain_size_ext_1_0_wren) begin + datain_channel_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DATAOUT_SIZE_0_0 Field: dataout_height + if (nvdla_csc_d_dataout_size_0_0_wren) begin + dataout_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CSC_D_DATAOUT_SIZE_0_0 Field: dataout_width + if (nvdla_csc_d_dataout_size_0_0_wren) begin + dataout_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DATAOUT_SIZE_1_0 Field: dataout_channel + if (nvdla_csc_d_dataout_size_1_0_wren) begin + dataout_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_DILATION_EXT_0 Field: x_dilation_ext + if (nvdla_csc_d_dilation_ext_0_wren) begin + x_dilation_ext[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_DILATION_EXT_0 Field: y_dilation_ext + if (nvdla_csc_d_dilation_ext_0_wren) begin + y_dilation_ext[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_ENTRY_PER_SLICE_0 Field: entries + if (nvdla_csc_d_entry_per_slice_0_wren) begin + entries[13:0] <= reg_wr_data[13:0]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: conv_mode + if (nvdla_csc_d_misc_cfg_0_wren) begin + conv_mode <= reg_wr_data[0]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: data_reuse + if (nvdla_csc_d_misc_cfg_0_wren) begin + data_reuse <= reg_wr_data[16]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: in_precision + if (nvdla_csc_d_misc_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[9:8]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: proc_precision + if (nvdla_csc_d_misc_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[13:12]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: skip_data_rls + if (nvdla_csc_d_misc_cfg_0_wren) begin + skip_data_rls <= reg_wr_data[24]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: skip_weight_rls + if (nvdla_csc_d_misc_cfg_0_wren) begin + skip_weight_rls <= reg_wr_data[28]; + end +// Register: NVDLA_CSC_D_MISC_CFG_0 Field: weight_reuse + if (nvdla_csc_d_misc_cfg_0_wren) begin + weight_reuse <= reg_wr_data[20]; + end +// Not generating flops for field NVDLA_CSC_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_CSC_D_POST_Y_EXTENSION_0 Field: y_extension + if (nvdla_csc_d_post_y_extension_0_wren) begin + y_extension[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CSC_D_PRA_CFG_0 Field: pra_truncate + if (nvdla_csc_d_pra_cfg_0_wren) begin + pra_truncate[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_CSC_D_RELEASE_0 Field: rls_slices + if (nvdla_csc_d_release_0_wren) begin + rls_slices[11:0] <= reg_wr_data[11:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_BYTES_0 Field: weight_bytes + if (nvdla_csc_d_weight_bytes_0_wren) begin + weight_bytes[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_FORMAT_0 Field: weight_format + if (nvdla_csc_d_weight_format_0_wren) begin + weight_format <= reg_wr_data[0]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_0_0 Field: weight_height_ext + if (nvdla_csc_d_weight_size_ext_0_0_wren) begin + weight_height_ext[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_0_0 Field: weight_width_ext + if (nvdla_csc_d_weight_size_ext_0_0_wren) begin + weight_width_ext[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_1_0 Field: weight_channel_ext + if (nvdla_csc_d_weight_size_ext_1_0_wren) begin + weight_channel_ext[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_CSC_D_WEIGHT_SIZE_EXT_1_0 Field: weight_kernel + if (nvdla_csc_d_weight_size_ext_1_0_wren) begin + weight_kernel[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_CSC_D_WMB_BYTES_0 Field: wmb_bytes + if (nvdla_csc_d_wmb_bytes_0_wren) begin + wmb_bytes[27:0] <= reg_wr_data[27:0]; + end +// Register: NVDLA_CSC_D_ZERO_PADDING_0 Field: pad_left + if (nvdla_csc_d_zero_padding_0_wren) begin + pad_left[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_CSC_D_ZERO_PADDING_0 Field: pad_top + if (nvdla_csc_d_zero_padding_0_wren) begin + pad_top[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_CSC_D_ZERO_PADDING_VALUE_0 Field: pad_value + if (nvdla_csc_d_zero_padding_value_0_wren) begin + pad_value[15:0] <= reg_wr_data[15:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h6044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ATOMICS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_atomics_0_out, nvdla_csc_d_atomics_0_out); + (32'h605c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_BANK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_bank_0_out, nvdla_csc_d_bank_0_out); + (32'h601c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_BATCH_NUMBER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_batch_number_0_out, nvdla_csc_d_batch_number_0_out); + (32'h604c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_CONV_STRIDE_EXT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_conv_stride_ext_0_out, nvdla_csc_d_conv_stride_ext_0_out); + (32'h6064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_cya_0_out, nvdla_csc_d_cya_0_out); + (32'h6010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAIN_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_datain_format_0_out, nvdla_csc_d_datain_format_0_out); + (32'h6014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAIN_SIZE_EXT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_datain_size_ext_0_0_out, nvdla_csc_d_datain_size_ext_0_0_out); + (32'h6018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAIN_SIZE_EXT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_datain_size_ext_1_0_out, nvdla_csc_d_datain_size_ext_1_0_out); + (32'h603c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAOUT_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_dataout_size_0_0_out, nvdla_csc_d_dataout_size_0_0_out); + (32'h6040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DATAOUT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_dataout_size_1_0_out, nvdla_csc_d_dataout_size_1_0_out); + (32'h6050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_DILATION_EXT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_dilation_ext_0_out, nvdla_csc_d_dilation_ext_0_out); + (32'h6024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ENTRY_PER_SLICE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_entry_per_slice_0_out, nvdla_csc_d_entry_per_slice_0_out); + (32'h600c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_misc_cfg_0_out, nvdla_csc_d_misc_cfg_0_out); + (32'h6008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_op_enable_0_out, nvdla_csc_d_op_enable_0_out); + (32'h6020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_POST_Y_EXTENSION_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_post_y_extension_0_out, nvdla_csc_d_post_y_extension_0_out); + (32'h6060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_PRA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_pra_cfg_0_out, nvdla_csc_d_pra_cfg_0_out); + (32'h6048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_RELEASE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_release_0_out, nvdla_csc_d_release_0_out); + (32'h6034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_bytes_0_out, nvdla_csc_d_weight_bytes_0_out); + (32'h6028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_format_0_out, nvdla_csc_d_weight_format_0_out); + (32'h602c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_SIZE_EXT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_size_ext_0_0_out, nvdla_csc_d_weight_size_ext_0_0_out); + (32'h6030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WEIGHT_SIZE_EXT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_weight_size_ext_1_0_out, nvdla_csc_d_weight_size_ext_1_0_out); + (32'h6038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_WMB_BYTES_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_wmb_bytes_0_out, nvdla_csc_d_wmb_bytes_0_out); + (32'h6054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ZERO_PADDING_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_zero_padding_0_out, nvdla_csc_d_zero_padding_0_out); + (32'h6058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_D_ZERO_PADDING_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_d_zero_padding_value_0_out, nvdla_csc_d_zero_padding_value_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CSC_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v new file mode 100644 index 0000000..7e35a08 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v @@ -0,0 +1,1564 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_pra_cell.v +module NV_NVDLA_CSC_pra_cell ( + cfg_precision //|< i + ,cfg_truncate_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [1:0] cfg_precision; +input [1:0] cfg_truncate_rsc_z; +input chn_data_in_rsc_vz; +input [255:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [255:0] chn_data_out_rsc_z; +wire [1:0] cfg_truncate; +wire [255:0] chn_data_in; +wire [15:0] chn_data_in_0; +wire [15:0] chn_data_in_1; +wire [15:0] chn_data_in_10; +wire [15:0] chn_data_in_11; +wire [15:0] chn_data_in_12; +wire [15:0] chn_data_in_13; +wire [15:0] chn_data_in_14; +wire [15:0] chn_data_in_15; +wire [15:0] chn_data_in_2; +wire [15:0] chn_data_in_3; +wire [15:0] chn_data_in_4; +wire [15:0] chn_data_in_5; +wire [15:0] chn_data_in_6; +wire [15:0] chn_data_in_7; +wire [15:0] chn_data_in_8; +wire [15:0] chn_data_in_9; +wire [255:0] chn_data_out; +wire [255:0] chn_data_reg; +wire [255:0] chn_dout; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire din_prdy; +wire din_pvld; +wire final_out_prdy; +wire final_out_pvld; +wire [271:0] mdata_out; +wire [16:0] mdata_out_0; +wire [16:0] mdata_out_1; +wire [16:0] mdata_out_10; +wire [16:0] mdata_out_11; +wire [16:0] mdata_out_12; +wire [16:0] mdata_out_13; +wire [16:0] mdata_out_14; +wire [16:0] mdata_out_15; +wire [16:0] mdata_out_2; +wire [16:0] mdata_out_3; +wire [16:0] mdata_out_4; +wire [16:0] mdata_out_5; +wire [16:0] mdata_out_6; +wire [16:0] mdata_out_7; +wire [16:0] mdata_out_8; +wire [16:0] mdata_out_9; +wire [271:0] mdout; +wire [16:0] mdout_0; +wire [16:0] mdout_1; +wire [16:0] mdout_10; +wire [16:0] mdout_11; +wire [16:0] mdout_12; +wire [16:0] mdout_13; +wire [16:0] mdout_14; +wire [16:0] mdout_15; +wire [16:0] mdout_2; +wire [16:0] mdout_3; +wire [16:0] mdout_4; +wire [16:0] mdout_5; +wire [16:0] mdout_6; +wire [16:0] mdout_7; +wire [16:0] mdout_8; +wire [16:0] mdout_9; +wire mout_prdy; +wire mout_pvld; +wire [287:0] tdata_out; +wire [17:0] tdata_out_0; +wire [17:0] tdata_out_1; +wire [17:0] tdata_out_10; +wire [17:0] tdata_out_11; +wire [17:0] tdata_out_12; +wire [17:0] tdata_out_13; +wire [17:0] tdata_out_14; +wire [17:0] tdata_out_15; +wire [17:0] tdata_out_2; +wire [17:0] tdata_out_3; +wire [17:0] tdata_out_4; +wire [17:0] tdata_out_5; +wire [17:0] tdata_out_6; +wire [17:0] tdata_out_7; +wire [17:0] tdata_out_8; +wire [17:0] tdata_out_9; +wire [287:0] tdout; +wire [17:0] tdout_0; +wire [17:0] tdout_1; +wire [17:0] tdout_10; +wire [17:0] tdout_11; +wire [17:0] tdout_12; +wire [17:0] tdout_13; +wire [17:0] tdout_14; +wire [17:0] tdout_15; +wire [17:0] tdout_2; +wire [17:0] tdout_3; +wire [17:0] tdout_4; +wire [17:0] tdout_5; +wire [17:0] tdout_6; +wire [17:0] tdout_7; +wire [17:0] tdout_8; +wire [17:0] tdout_9; +wire tout_prdy; +wire tout_pvld; +wire [255:0] tru_data_out_int16; +wire [255:0] tru_data_out_int8; +wire [255:0] tru_dout_int16; +wire [15:0] tru_dout_int16_0; +wire [15:0] tru_dout_int16_1; +wire [15:0] tru_dout_int16_10; +wire [15:0] tru_dout_int16_11; +wire [15:0] tru_dout_int16_12; +wire [15:0] tru_dout_int16_13; +wire [15:0] tru_dout_int16_14; +wire [15:0] tru_dout_int16_15; +wire [15:0] tru_dout_int16_2; +wire [15:0] tru_dout_int16_3; +wire [15:0] tru_dout_int16_4; +wire [15:0] tru_dout_int16_5; +wire [15:0] tru_dout_int16_6; +wire [15:0] tru_dout_int16_7; +wire [15:0] tru_dout_int16_8; +wire [15:0] tru_dout_int16_9; +wire [7:0] tru_dout_int8_0; +wire [7:0] tru_dout_int8_1; +wire [7:0] tru_dout_int8_10; +wire [7:0] tru_dout_int8_11; +wire [7:0] tru_dout_int8_12; +wire [7:0] tru_dout_int8_13; +wire [7:0] tru_dout_int8_14; +wire [7:0] tru_dout_int8_15; +wire [7:0] tru_dout_int8_2; +wire [7:0] tru_dout_int8_3; +wire [7:0] tru_dout_int8_4; +wire [7:0] tru_dout_int8_5; +wire [7:0] tru_dout_int8_6; +wire [7:0] tru_dout_int8_7; +wire [7:0] tru_dout_int8_8; +wire [7:0] tru_dout_int8_9; +wire [255:0] tru_dout_int8_ext; +wire [15:0] tru_dout_int8_ext_0; +wire [15:0] tru_dout_int8_ext_1; +wire [15:0] tru_dout_int8_ext_10; +wire [15:0] tru_dout_int8_ext_11; +wire [15:0] tru_dout_int8_ext_12; +wire [15:0] tru_dout_int8_ext_13; +wire [15:0] tru_dout_int8_ext_14; +wire [15:0] tru_dout_int8_ext_15; +wire [15:0] tru_dout_int8_ext_2; +wire [15:0] tru_dout_int8_ext_3; +wire [15:0] tru_dout_int8_ext_4; +wire [15:0] tru_dout_int8_ext_5; +wire [15:0] tru_dout_int8_ext_6; +wire [15:0] tru_dout_int8_ext_7; +wire [15:0] tru_dout_int8_ext_8; +wire [15:0] tru_dout_int8_ext_9; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign cfg_truncate[1:0] = cfg_truncate_rsc_z[1:0]; +assign chn_data_in[255:0] = chn_data_in_rsc_z[255:0]; +assign chn_data_out_rsc_z[255:0] = chn_data_out[255:0]; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +NV_NVDLA_CSC_PRA_CELL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in (chn_data_in[255:0]) //|< w + ,.chn_in_pvld (chn_in_pvld) //|< w + ,.din_prdy (din_prdy) //|< w + ,.chn_data_reg (chn_data_reg[255:0]) //|> w + ,.chn_in_prdy (chn_in_prdy) //|> w + ,.din_pvld (din_pvld) //|> w + ); +assign {chn_data_in_15, chn_data_in_14, chn_data_in_13, chn_data_in_12, chn_data_in_11, chn_data_in_10, chn_data_in_9, chn_data_in_8, chn_data_in_7, chn_data_in_6, chn_data_in_5, chn_data_in_4, chn_data_in_3, chn_data_in_2, chn_data_in_1, chn_data_in_0} = chn_data_reg[255:0]; +assign mdout_0[16:0] = $signed(chn_data_in_0[15:0]) - $signed(chn_data_in_8[15:0]); +assign mdout_1[16:0] = $signed(chn_data_in_1[15:0]) - $signed(chn_data_in_9[15:0]); +assign mdout_2[16:0] = $signed(chn_data_in_2[15:0]) - $signed(chn_data_in_10[15:0]); +assign mdout_3[16:0] = $signed(chn_data_in_3[15:0]) - $signed(chn_data_in_11[15:0]); +assign mdout_4[16:0] = $signed(chn_data_in_4[15:0]) + $signed(chn_data_in_8[15:0]); +assign mdout_5[16:0] = $signed(chn_data_in_5[15:0]) + $signed(chn_data_in_9[15:0]); +assign mdout_6[16:0] = $signed(chn_data_in_6[15:0]) + $signed(chn_data_in_10[15:0]); +assign mdout_7[16:0] = $signed(chn_data_in_7[15:0]) + $signed(chn_data_in_11[15:0]); +assign mdout_8[16:0] = $signed(chn_data_in_8[15:0]) - $signed(chn_data_in_4[15:0]); +assign mdout_9[16:0] = $signed(chn_data_in_9[15:0]) - $signed(chn_data_in_5[15:0]); +assign mdout_10[16:0] = $signed(chn_data_in_10[15:0]) - $signed(chn_data_in_6[15:0]); +assign mdout_11[16:0] = $signed(chn_data_in_11[15:0]) - $signed(chn_data_in_7[15:0]); +assign mdout_12[16:0] = $signed(chn_data_in_4[15:0]) - $signed(chn_data_in_12[15:0]); +assign mdout_13[16:0] = $signed(chn_data_in_5[15:0]) - $signed(chn_data_in_13[15:0]); +assign mdout_14[16:0] = $signed(chn_data_in_6[15:0]) - $signed(chn_data_in_14[15:0]); +assign mdout_15[16:0] = $signed(chn_data_in_7[15:0]) - $signed(chn_data_in_15[15:0]); +assign tdout_0[17:0] = $signed(mdata_out_0[16:0]) - $signed(mdata_out_2[16:0]); +assign tdout_4[17:0] = $signed(mdata_out_4[16:0]) - $signed(mdata_out_6[16:0]); +assign tdout_8[17:0] = $signed(mdata_out_8[16:0]) - $signed(mdata_out_10[16:0]); +assign tdout_12[17:0] = $signed(mdata_out_12[16:0]) - $signed(mdata_out_14[16:0]); +assign tdout_1[17:0] = $signed(mdata_out_1[16:0]) + $signed(mdata_out_2[16:0]); +assign tdout_5[17:0] = $signed(mdata_out_5[16:0]) + $signed(mdata_out_6[16:0]); +assign tdout_9[17:0] = $signed(mdata_out_9[16:0]) + $signed(mdata_out_10[16:0]); +assign tdout_13[17:0] = $signed(mdata_out_13[16:0]) + $signed(mdata_out_14[16:0]); +assign tdout_2[17:0] = $signed(mdata_out_2[16:0]) - $signed(mdata_out_1[16:0]); +assign tdout_6[17:0] = $signed(mdata_out_6[16:0]) - $signed(mdata_out_5[16:0]); +assign tdout_10[17:0] = $signed(mdata_out_10[16:0]) - $signed(mdata_out_9[16:0]); +assign tdout_14[17:0] = $signed(mdata_out_14[16:0]) - $signed(mdata_out_13[16:0]); +assign tdout_3[17:0] = $signed(mdata_out_1[16:0]) - $signed(mdata_out_3[16:0]); +assign tdout_7[17:0] = $signed(mdata_out_5[16:0]) - $signed(mdata_out_7[16:0]); +assign tdout_11[17:0] = $signed(mdata_out_9[16:0]) - $signed(mdata_out_11[16:0]); +assign tdout_15[17:0] = $signed(mdata_out_13[16:0]) - $signed(mdata_out_15[16:0]); +//row +assign mdout[271:0] = { mdout_15, mdout_14, mdout_13, mdout_12, mdout_11, mdout_10, mdout_9, mdout_8, mdout_7, mdout_6, mdout_5, mdout_4, mdout_3, mdout_2, mdout_1, mdout_0}; +NV_NVDLA_CSC_PRA_CELL_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.din_pvld (din_pvld) //|< w + ,.mdout (mdout[271:0]) //|< w + ,.mout_prdy (mout_prdy) //|< w + ,.din_prdy (din_prdy) //|> w + ,.mdata_out (mdata_out[271:0]) //|> w + ,.mout_pvld (mout_pvld) //|> w + ); +assign {mdata_out_15, mdata_out_14, mdata_out_13, mdata_out_12, mdata_out_11, mdata_out_10, mdata_out_9, mdata_out_8, mdata_out_7, mdata_out_6, mdata_out_5, mdata_out_4, mdata_out_3, mdata_out_2, mdata_out_1, mdata_out_0} = mdata_out[271:0]; +//col +assign tdout[287:0] = { tdout_15, tdout_14, tdout_13, tdout_12, tdout_11, tdout_10, tdout_9, tdout_8, tdout_7, tdout_6, tdout_5, tdout_4, tdout_3, tdout_2, tdout_1, tdout_0}; +NV_NVDLA_CSC_PRA_CELL_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mout_pvld (mout_pvld) //|< w + ,.tdout (tdout[287:0]) //|< w + ,.tout_prdy (tout_prdy) //|< w + ,.mout_prdy (mout_prdy) //|> w + ,.tdata_out (tdata_out[287:0]) //|> w + ,.tout_pvld (tout_pvld) //|> w + ); +assign {tdata_out_15, tdata_out_14, tdata_out_13, tdata_out_12, tdata_out_11, tdata_out_10, tdata_out_9, tdata_out_8, tdata_out_7, tdata_out_6, tdata_out_5, tdata_out_4, tdata_out_3, tdata_out_2, tdata_out_1, tdata_out_0} = tdata_out[287:0]; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_0 ( + .data_in (tdata_out_0[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_0[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_0 ( + .data_in (tdata_out_0[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_0[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_0[15:0] = {{(16 - 8 ){tru_dout_int8_0[8 -1]}},tru_dout_int8_0[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_1 ( + .data_in (tdata_out_1[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_1[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_1 ( + .data_in (tdata_out_1[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_1[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_1[15:0] = {{(16 - 8 ){tru_dout_int8_1[8 -1]}},tru_dout_int8_1[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_2 ( + .data_in (tdata_out_2[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_2[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_2 ( + .data_in (tdata_out_2[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_2[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_2[15:0] = {{(16 - 8 ){tru_dout_int8_2[8 -1]}},tru_dout_int8_2[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_3 ( + .data_in (tdata_out_3[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_3[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_3 ( + .data_in (tdata_out_3[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_3[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_3[15:0] = {{(16 - 8 ){tru_dout_int8_3[8 -1]}},tru_dout_int8_3[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_4 ( + .data_in (tdata_out_4[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_4[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_4 ( + .data_in (tdata_out_4[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_4[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_4[15:0] = {{(16 - 8 ){tru_dout_int8_4[8 -1]}},tru_dout_int8_4[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_5 ( + .data_in (tdata_out_5[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_5[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_5 ( + .data_in (tdata_out_5[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_5[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_5[15:0] = {{(16 - 8 ){tru_dout_int8_5[8 -1]}},tru_dout_int8_5[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_6 ( + .data_in (tdata_out_6[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_6[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_6 ( + .data_in (tdata_out_6[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_6[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_6[15:0] = {{(16 - 8 ){tru_dout_int8_6[8 -1]}},tru_dout_int8_6[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_7 ( + .data_in (tdata_out_7[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_7[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_7 ( + .data_in (tdata_out_7[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_7[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_7[15:0] = {{(16 - 8 ){tru_dout_int8_7[8 -1]}},tru_dout_int8_7[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_8 ( + .data_in (tdata_out_8[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_8[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_8 ( + .data_in (tdata_out_8[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_8[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_8[15:0] = {{(16 - 8 ){tru_dout_int8_8[8 -1]}},tru_dout_int8_8[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_9 ( + .data_in (tdata_out_9[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_9[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_9 ( + .data_in (tdata_out_9[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_9[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_9[15:0] = {{(16 - 8 ){tru_dout_int8_9[8 -1]}},tru_dout_int8_9[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_10 ( + .data_in (tdata_out_10[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_10[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_10 ( + .data_in (tdata_out_10[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_10[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_10[15:0] = {{(16 - 8 ){tru_dout_int8_10[8 -1]}},tru_dout_int8_10[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_11 ( + .data_in (tdata_out_11[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_11[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_11 ( + .data_in (tdata_out_11[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_11[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_11[15:0] = {{(16 - 8 ){tru_dout_int8_11[8 -1]}},tru_dout_int8_11[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_12 ( + .data_in (tdata_out_12[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_12[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_12 ( + .data_in (tdata_out_12[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_12[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_12[15:0] = {{(16 - 8 ){tru_dout_int8_12[8 -1]}},tru_dout_int8_12[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_13 ( + .data_in (tdata_out_13[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_13[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_13 ( + .data_in (tdata_out_13[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_13[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_13[15:0] = {{(16 - 8 ){tru_dout_int8_13[8 -1]}},tru_dout_int8_13[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_14 ( + .data_in (tdata_out_14[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_14[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_14 ( + .data_in (tdata_out_14[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_14[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_14[15:0] = {{(16 - 8 ){tru_dout_int8_14[8 -1]}},tru_dout_int8_14[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_15 ( + .data_in (tdata_out_15[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_15[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_15 ( + .data_in (tdata_out_15[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_15[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_15[15:0] = {{(16 - 8 ){tru_dout_int8_15[8 -1]}},tru_dout_int8_15[7:0]}; +assign tru_dout_int16[255:0] = { tru_dout_int16_15, tru_dout_int16_14, tru_dout_int16_13, tru_dout_int16_12, tru_dout_int16_11, tru_dout_int16_10, tru_dout_int16_9, tru_dout_int16_8, tru_dout_int16_7, tru_dout_int16_6, tru_dout_int16_5, tru_dout_int16_4, tru_dout_int16_3, tru_dout_int16_2, tru_dout_int16_1, tru_dout_int16_0}; +assign tru_dout_int8_ext[255:0] = { tru_dout_int8_ext_15, tru_dout_int8_ext_14, tru_dout_int8_ext_13, tru_dout_int8_ext_12, tru_dout_int8_ext_11, tru_dout_int8_ext_10, tru_dout_int8_ext_9, tru_dout_int8_ext_8, tru_dout_int8_ext_7, tru_dout_int8_ext_6, tru_dout_int8_ext_5, tru_dout_int8_ext_4, tru_dout_int8_ext_3, tru_dout_int8_ext_2, tru_dout_int8_ext_1, tru_dout_int8_ext_0}; +NV_NVDLA_CSC_PRA_CELL_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.final_out_prdy (final_out_prdy) //|< w + ,.tout_pvld (tout_pvld) //|< w + ,.tru_dout_int16 (tru_dout_int16[255:0]) //|< w + ,.tru_dout_int8_ext (tru_dout_int8_ext[255:0]) //|< w + ,.final_out_pvld (final_out_pvld) //|> w + ,.tout_prdy (tout_prdy) //|> w + ,.tru_data_out_int16 (tru_data_out_int16[255:0]) //|> w + ,.tru_data_out_int8 (tru_data_out_int8[255:0]) //|> w + ); +assign chn_dout[255:0] = (cfg_precision[1:0] == 1 ) ? tru_data_out_int16[255:0] : tru_data_out_int8[255:0]; +NV_NVDLA_CSC_PRA_CELL_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_dout (chn_dout[255:0]) //|< w + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.final_out_pvld (final_out_pvld) //|< w + ,.chn_data_out (chn_data_out[255:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.final_out_prdy (final_out_prdy) //|> w + ); +endmodule // NV_NVDLA_CSC_pra_cell +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_reg[255:0] (din_pvld,din_prdy) <= chn_data_in[255:0] (chn_in_pvld,chn_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_data_in + ,chn_in_pvld + ,din_prdy + ,chn_data_reg + ,chn_in_prdy + ,din_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [255:0] chn_data_in; +input chn_in_pvld; +input din_prdy; +output [255:0] chn_data_reg; +output chn_in_prdy; +output din_pvld; +reg [255:0] chn_data_reg; +reg chn_in_prdy; +reg din_pvld; +reg [255:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [255:0] p1_skid_data; +reg [255:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + chn_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? chn_data_in[255:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_in_pvld + or p1_skid_valid + or chn_data_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? chn_data_in[255:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or din_prdy + or p1_pipe_data + ) begin + din_pvld = p1_pipe_valid; + p1_pipe_ready = din_prdy; + chn_data_reg[255:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (din_pvld^din_prdy^chn_in_pvld^chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_in_pvld && !chn_in_prdy), (chn_in_pvld), (chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mdata_out[271:0] (mout_pvld,mout_prdy) <= mdout[271:0] (din_pvld,din_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,din_pvld + ,mdout + ,mout_prdy + ,din_prdy + ,mdata_out + ,mout_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input din_pvld; +input [271:0] mdout; +input mout_prdy; +output din_prdy; +output [271:0] mdata_out; +output mout_pvld; +reg din_prdy; +reg [271:0] mdata_out; +reg mout_pvld; +reg [271:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [271:0] p2_skid_data; +reg [271:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + din_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = din_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + din_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + din_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mdout[271:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or din_pvld + or p2_skid_valid + or mdout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? din_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mdout[271:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mout_prdy + or p2_pipe_data + ) begin + mout_pvld = p2_pipe_valid; + p2_pipe_ready = mout_prdy; + mdata_out[271:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mout_pvld^mout_prdy^din_pvld^din_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (din_pvld && !din_prdy), (din_pvld), (din_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is tdata_out[287:0] (tout_pvld,tout_prdy) <= tdout[287:0] (mout_pvld,mout_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mout_pvld + ,tdout + ,tout_prdy + ,mout_prdy + ,tdata_out + ,tout_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mout_pvld; +input [287:0] tdout; +input tout_prdy; +output mout_prdy; +output [287:0] tdata_out; +output tout_pvld; +reg mout_prdy; +reg [287:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [287:0] p3_skid_data; +reg [287:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg [287:0] tdata_out; +reg tout_pvld; +//## pipe (3) skid buffer +always @( + mout_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mout_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mout_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mout_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? tdout[287:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mout_pvld + or p3_skid_valid + or tdout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mout_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? tdout[287:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tout_prdy + or p3_pipe_data + ) begin + tout_pvld = p3_pipe_valid; + p3_pipe_ready = tout_prdy; + tdata_out[287:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tout_pvld^tout_prdy^mout_pvld^mout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mout_pvld && !mout_prdy), (mout_pvld), (mout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {tru_data_out_int16[255:0],tru_data_out_int8[255:0]} (final_out_pvld,final_out_prdy) <= {tru_dout_int16[255:0],tru_dout_int8_ext[255:0]} (tout_pvld,tout_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,final_out_prdy + ,tout_pvld + ,tru_dout_int16 + ,tru_dout_int8_ext + ,final_out_pvld + ,tout_prdy + ,tru_data_out_int16 + ,tru_data_out_int8 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input final_out_prdy; +input tout_pvld; +input [255:0] tru_dout_int16; +input [255:0] tru_dout_int8_ext; +output final_out_pvld; +output tout_prdy; +output [255:0] tru_data_out_int16; +output [255:0] tru_data_out_int8; +reg final_out_pvld; +reg [511:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [511:0] p4_skid_data; +reg [511:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +reg tout_prdy; +reg [255:0] tru_data_out_int16; +reg [255:0] tru_data_out_int8; +//## pipe (4) skid buffer +always @( + tout_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = tout_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + tout_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + tout_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? {tru_dout_int16[255:0],tru_dout_int8_ext[255:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or tout_pvld + or p4_skid_valid + or tru_dout_int16 + or tru_dout_int8_ext + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? tout_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? {tru_dout_int16[255:0],tru_dout_int8_ext[255:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or final_out_prdy + or p4_pipe_data + ) begin + final_out_pvld = p4_pipe_valid; + p4_pipe_ready = final_out_prdy; + {tru_data_out_int16[255:0],tru_data_out_int8[255:0]} = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (final_out_pvld^final_out_prdy^tout_pvld^tout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (tout_pvld && !tout_prdy), (tout_pvld), (tout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[255:0] (chn_out_pvld,chn_out_prdy) <= chn_dout[255:0] (final_out_pvld,final_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_dout + ,chn_out_prdy + ,final_out_pvld + ,chn_data_out + ,chn_out_pvld + ,final_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [255:0] chn_dout; +input chn_out_prdy; +input final_out_pvld; +output [255:0] chn_data_out; +output chn_out_pvld; +output final_out_prdy; +reg [255:0] chn_data_out; +reg chn_out_pvld; +reg final_out_prdy; +reg [255:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [255:0] p5_skid_data; +reg [255:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +//## pipe (5) skid buffer +always @( + final_out_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = final_out_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + final_out_prdy <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + final_out_prdy <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? chn_dout[255:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or final_out_pvld + or p5_skid_valid + or chn_dout + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? final_out_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? chn_dout[255:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or chn_out_prdy + or p5_pipe_data + ) begin + chn_out_pvld = p5_pipe_valid; + p5_pipe_ready = chn_out_prdy; + chn_data_out[255:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^final_out_pvld^final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (final_out_pvld && !final_out_prdy), (final_out_pvld), (final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p5 diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v.vcp new file mode 100644 index 0000000..7e35a08 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v.vcp @@ -0,0 +1,1564 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_pra_cell.v +module NV_NVDLA_CSC_pra_cell ( + cfg_precision //|< i + ,cfg_truncate_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [1:0] cfg_precision; +input [1:0] cfg_truncate_rsc_z; +input chn_data_in_rsc_vz; +input [255:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [255:0] chn_data_out_rsc_z; +wire [1:0] cfg_truncate; +wire [255:0] chn_data_in; +wire [15:0] chn_data_in_0; +wire [15:0] chn_data_in_1; +wire [15:0] chn_data_in_10; +wire [15:0] chn_data_in_11; +wire [15:0] chn_data_in_12; +wire [15:0] chn_data_in_13; +wire [15:0] chn_data_in_14; +wire [15:0] chn_data_in_15; +wire [15:0] chn_data_in_2; +wire [15:0] chn_data_in_3; +wire [15:0] chn_data_in_4; +wire [15:0] chn_data_in_5; +wire [15:0] chn_data_in_6; +wire [15:0] chn_data_in_7; +wire [15:0] chn_data_in_8; +wire [15:0] chn_data_in_9; +wire [255:0] chn_data_out; +wire [255:0] chn_data_reg; +wire [255:0] chn_dout; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire din_prdy; +wire din_pvld; +wire final_out_prdy; +wire final_out_pvld; +wire [271:0] mdata_out; +wire [16:0] mdata_out_0; +wire [16:0] mdata_out_1; +wire [16:0] mdata_out_10; +wire [16:0] mdata_out_11; +wire [16:0] mdata_out_12; +wire [16:0] mdata_out_13; +wire [16:0] mdata_out_14; +wire [16:0] mdata_out_15; +wire [16:0] mdata_out_2; +wire [16:0] mdata_out_3; +wire [16:0] mdata_out_4; +wire [16:0] mdata_out_5; +wire [16:0] mdata_out_6; +wire [16:0] mdata_out_7; +wire [16:0] mdata_out_8; +wire [16:0] mdata_out_9; +wire [271:0] mdout; +wire [16:0] mdout_0; +wire [16:0] mdout_1; +wire [16:0] mdout_10; +wire [16:0] mdout_11; +wire [16:0] mdout_12; +wire [16:0] mdout_13; +wire [16:0] mdout_14; +wire [16:0] mdout_15; +wire [16:0] mdout_2; +wire [16:0] mdout_3; +wire [16:0] mdout_4; +wire [16:0] mdout_5; +wire [16:0] mdout_6; +wire [16:0] mdout_7; +wire [16:0] mdout_8; +wire [16:0] mdout_9; +wire mout_prdy; +wire mout_pvld; +wire [287:0] tdata_out; +wire [17:0] tdata_out_0; +wire [17:0] tdata_out_1; +wire [17:0] tdata_out_10; +wire [17:0] tdata_out_11; +wire [17:0] tdata_out_12; +wire [17:0] tdata_out_13; +wire [17:0] tdata_out_14; +wire [17:0] tdata_out_15; +wire [17:0] tdata_out_2; +wire [17:0] tdata_out_3; +wire [17:0] tdata_out_4; +wire [17:0] tdata_out_5; +wire [17:0] tdata_out_6; +wire [17:0] tdata_out_7; +wire [17:0] tdata_out_8; +wire [17:0] tdata_out_9; +wire [287:0] tdout; +wire [17:0] tdout_0; +wire [17:0] tdout_1; +wire [17:0] tdout_10; +wire [17:0] tdout_11; +wire [17:0] tdout_12; +wire [17:0] tdout_13; +wire [17:0] tdout_14; +wire [17:0] tdout_15; +wire [17:0] tdout_2; +wire [17:0] tdout_3; +wire [17:0] tdout_4; +wire [17:0] tdout_5; +wire [17:0] tdout_6; +wire [17:0] tdout_7; +wire [17:0] tdout_8; +wire [17:0] tdout_9; +wire tout_prdy; +wire tout_pvld; +wire [255:0] tru_data_out_int16; +wire [255:0] tru_data_out_int8; +wire [255:0] tru_dout_int16; +wire [15:0] tru_dout_int16_0; +wire [15:0] tru_dout_int16_1; +wire [15:0] tru_dout_int16_10; +wire [15:0] tru_dout_int16_11; +wire [15:0] tru_dout_int16_12; +wire [15:0] tru_dout_int16_13; +wire [15:0] tru_dout_int16_14; +wire [15:0] tru_dout_int16_15; +wire [15:0] tru_dout_int16_2; +wire [15:0] tru_dout_int16_3; +wire [15:0] tru_dout_int16_4; +wire [15:0] tru_dout_int16_5; +wire [15:0] tru_dout_int16_6; +wire [15:0] tru_dout_int16_7; +wire [15:0] tru_dout_int16_8; +wire [15:0] tru_dout_int16_9; +wire [7:0] tru_dout_int8_0; +wire [7:0] tru_dout_int8_1; +wire [7:0] tru_dout_int8_10; +wire [7:0] tru_dout_int8_11; +wire [7:0] tru_dout_int8_12; +wire [7:0] tru_dout_int8_13; +wire [7:0] tru_dout_int8_14; +wire [7:0] tru_dout_int8_15; +wire [7:0] tru_dout_int8_2; +wire [7:0] tru_dout_int8_3; +wire [7:0] tru_dout_int8_4; +wire [7:0] tru_dout_int8_5; +wire [7:0] tru_dout_int8_6; +wire [7:0] tru_dout_int8_7; +wire [7:0] tru_dout_int8_8; +wire [7:0] tru_dout_int8_9; +wire [255:0] tru_dout_int8_ext; +wire [15:0] tru_dout_int8_ext_0; +wire [15:0] tru_dout_int8_ext_1; +wire [15:0] tru_dout_int8_ext_10; +wire [15:0] tru_dout_int8_ext_11; +wire [15:0] tru_dout_int8_ext_12; +wire [15:0] tru_dout_int8_ext_13; +wire [15:0] tru_dout_int8_ext_14; +wire [15:0] tru_dout_int8_ext_15; +wire [15:0] tru_dout_int8_ext_2; +wire [15:0] tru_dout_int8_ext_3; +wire [15:0] tru_dout_int8_ext_4; +wire [15:0] tru_dout_int8_ext_5; +wire [15:0] tru_dout_int8_ext_6; +wire [15:0] tru_dout_int8_ext_7; +wire [15:0] tru_dout_int8_ext_8; +wire [15:0] tru_dout_int8_ext_9; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign cfg_truncate[1:0] = cfg_truncate_rsc_z[1:0]; +assign chn_data_in[255:0] = chn_data_in_rsc_z[255:0]; +assign chn_data_out_rsc_z[255:0] = chn_data_out[255:0]; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +NV_NVDLA_CSC_PRA_CELL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_data_in (chn_data_in[255:0]) //|< w + ,.chn_in_pvld (chn_in_pvld) //|< w + ,.din_prdy (din_prdy) //|< w + ,.chn_data_reg (chn_data_reg[255:0]) //|> w + ,.chn_in_prdy (chn_in_prdy) //|> w + ,.din_pvld (din_pvld) //|> w + ); +assign {chn_data_in_15, chn_data_in_14, chn_data_in_13, chn_data_in_12, chn_data_in_11, chn_data_in_10, chn_data_in_9, chn_data_in_8, chn_data_in_7, chn_data_in_6, chn_data_in_5, chn_data_in_4, chn_data_in_3, chn_data_in_2, chn_data_in_1, chn_data_in_0} = chn_data_reg[255:0]; +assign mdout_0[16:0] = $signed(chn_data_in_0[15:0]) - $signed(chn_data_in_8[15:0]); +assign mdout_1[16:0] = $signed(chn_data_in_1[15:0]) - $signed(chn_data_in_9[15:0]); +assign mdout_2[16:0] = $signed(chn_data_in_2[15:0]) - $signed(chn_data_in_10[15:0]); +assign mdout_3[16:0] = $signed(chn_data_in_3[15:0]) - $signed(chn_data_in_11[15:0]); +assign mdout_4[16:0] = $signed(chn_data_in_4[15:0]) + $signed(chn_data_in_8[15:0]); +assign mdout_5[16:0] = $signed(chn_data_in_5[15:0]) + $signed(chn_data_in_9[15:0]); +assign mdout_6[16:0] = $signed(chn_data_in_6[15:0]) + $signed(chn_data_in_10[15:0]); +assign mdout_7[16:0] = $signed(chn_data_in_7[15:0]) + $signed(chn_data_in_11[15:0]); +assign mdout_8[16:0] = $signed(chn_data_in_8[15:0]) - $signed(chn_data_in_4[15:0]); +assign mdout_9[16:0] = $signed(chn_data_in_9[15:0]) - $signed(chn_data_in_5[15:0]); +assign mdout_10[16:0] = $signed(chn_data_in_10[15:0]) - $signed(chn_data_in_6[15:0]); +assign mdout_11[16:0] = $signed(chn_data_in_11[15:0]) - $signed(chn_data_in_7[15:0]); +assign mdout_12[16:0] = $signed(chn_data_in_4[15:0]) - $signed(chn_data_in_12[15:0]); +assign mdout_13[16:0] = $signed(chn_data_in_5[15:0]) - $signed(chn_data_in_13[15:0]); +assign mdout_14[16:0] = $signed(chn_data_in_6[15:0]) - $signed(chn_data_in_14[15:0]); +assign mdout_15[16:0] = $signed(chn_data_in_7[15:0]) - $signed(chn_data_in_15[15:0]); +assign tdout_0[17:0] = $signed(mdata_out_0[16:0]) - $signed(mdata_out_2[16:0]); +assign tdout_4[17:0] = $signed(mdata_out_4[16:0]) - $signed(mdata_out_6[16:0]); +assign tdout_8[17:0] = $signed(mdata_out_8[16:0]) - $signed(mdata_out_10[16:0]); +assign tdout_12[17:0] = $signed(mdata_out_12[16:0]) - $signed(mdata_out_14[16:0]); +assign tdout_1[17:0] = $signed(mdata_out_1[16:0]) + $signed(mdata_out_2[16:0]); +assign tdout_5[17:0] = $signed(mdata_out_5[16:0]) + $signed(mdata_out_6[16:0]); +assign tdout_9[17:0] = $signed(mdata_out_9[16:0]) + $signed(mdata_out_10[16:0]); +assign tdout_13[17:0] = $signed(mdata_out_13[16:0]) + $signed(mdata_out_14[16:0]); +assign tdout_2[17:0] = $signed(mdata_out_2[16:0]) - $signed(mdata_out_1[16:0]); +assign tdout_6[17:0] = $signed(mdata_out_6[16:0]) - $signed(mdata_out_5[16:0]); +assign tdout_10[17:0] = $signed(mdata_out_10[16:0]) - $signed(mdata_out_9[16:0]); +assign tdout_14[17:0] = $signed(mdata_out_14[16:0]) - $signed(mdata_out_13[16:0]); +assign tdout_3[17:0] = $signed(mdata_out_1[16:0]) - $signed(mdata_out_3[16:0]); +assign tdout_7[17:0] = $signed(mdata_out_5[16:0]) - $signed(mdata_out_7[16:0]); +assign tdout_11[17:0] = $signed(mdata_out_9[16:0]) - $signed(mdata_out_11[16:0]); +assign tdout_15[17:0] = $signed(mdata_out_13[16:0]) - $signed(mdata_out_15[16:0]); +//row +assign mdout[271:0] = { mdout_15, mdout_14, mdout_13, mdout_12, mdout_11, mdout_10, mdout_9, mdout_8, mdout_7, mdout_6, mdout_5, mdout_4, mdout_3, mdout_2, mdout_1, mdout_0}; +NV_NVDLA_CSC_PRA_CELL_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.din_pvld (din_pvld) //|< w + ,.mdout (mdout[271:0]) //|< w + ,.mout_prdy (mout_prdy) //|< w + ,.din_prdy (din_prdy) //|> w + ,.mdata_out (mdata_out[271:0]) //|> w + ,.mout_pvld (mout_pvld) //|> w + ); +assign {mdata_out_15, mdata_out_14, mdata_out_13, mdata_out_12, mdata_out_11, mdata_out_10, mdata_out_9, mdata_out_8, mdata_out_7, mdata_out_6, mdata_out_5, mdata_out_4, mdata_out_3, mdata_out_2, mdata_out_1, mdata_out_0} = mdata_out[271:0]; +//col +assign tdout[287:0] = { tdout_15, tdout_14, tdout_13, tdout_12, tdout_11, tdout_10, tdout_9, tdout_8, tdout_7, tdout_6, tdout_5, tdout_4, tdout_3, tdout_2, tdout_1, tdout_0}; +NV_NVDLA_CSC_PRA_CELL_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mout_pvld (mout_pvld) //|< w + ,.tdout (tdout[287:0]) //|< w + ,.tout_prdy (tout_prdy) //|< w + ,.mout_prdy (mout_prdy) //|> w + ,.tdata_out (tdata_out[287:0]) //|> w + ,.tout_pvld (tout_pvld) //|> w + ); +assign {tdata_out_15, tdata_out_14, tdata_out_13, tdata_out_12, tdata_out_11, tdata_out_10, tdata_out_9, tdata_out_8, tdata_out_7, tdata_out_6, tdata_out_5, tdata_out_4, tdata_out_3, tdata_out_2, tdata_out_1, tdata_out_0} = tdata_out[287:0]; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_0 ( + .data_in (tdata_out_0[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_0[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_0 ( + .data_in (tdata_out_0[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_0[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_0[15:0] = {{(16 - 8 ){tru_dout_int8_0[8 -1]}},tru_dout_int8_0[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_1 ( + .data_in (tdata_out_1[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_1[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_1 ( + .data_in (tdata_out_1[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_1[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_1[15:0] = {{(16 - 8 ){tru_dout_int8_1[8 -1]}},tru_dout_int8_1[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_2 ( + .data_in (tdata_out_2[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_2[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_2 ( + .data_in (tdata_out_2[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_2[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_2[15:0] = {{(16 - 8 ){tru_dout_int8_2[8 -1]}},tru_dout_int8_2[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_3 ( + .data_in (tdata_out_3[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_3[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_3 ( + .data_in (tdata_out_3[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_3[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_3[15:0] = {{(16 - 8 ){tru_dout_int8_3[8 -1]}},tru_dout_int8_3[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_4 ( + .data_in (tdata_out_4[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_4[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_4 ( + .data_in (tdata_out_4[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_4[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_4[15:0] = {{(16 - 8 ){tru_dout_int8_4[8 -1]}},tru_dout_int8_4[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_5 ( + .data_in (tdata_out_5[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_5[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_5 ( + .data_in (tdata_out_5[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_5[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_5[15:0] = {{(16 - 8 ){tru_dout_int8_5[8 -1]}},tru_dout_int8_5[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_6 ( + .data_in (tdata_out_6[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_6[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_6 ( + .data_in (tdata_out_6[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_6[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_6[15:0] = {{(16 - 8 ){tru_dout_int8_6[8 -1]}},tru_dout_int8_6[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_7 ( + .data_in (tdata_out_7[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_7[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_7 ( + .data_in (tdata_out_7[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_7[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_7[15:0] = {{(16 - 8 ){tru_dout_int8_7[8 -1]}},tru_dout_int8_7[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_8 ( + .data_in (tdata_out_8[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_8[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_8 ( + .data_in (tdata_out_8[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_8[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_8[15:0] = {{(16 - 8 ){tru_dout_int8_8[8 -1]}},tru_dout_int8_8[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_9 ( + .data_in (tdata_out_9[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_9[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_9 ( + .data_in (tdata_out_9[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_9[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_9[15:0] = {{(16 - 8 ){tru_dout_int8_9[8 -1]}},tru_dout_int8_9[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_10 ( + .data_in (tdata_out_10[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_10[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_10 ( + .data_in (tdata_out_10[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_10[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_10[15:0] = {{(16 - 8 ){tru_dout_int8_10[8 -1]}},tru_dout_int8_10[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_11 ( + .data_in (tdata_out_11[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_11[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_11 ( + .data_in (tdata_out_11[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_11[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_11[15:0] = {{(16 - 8 ){tru_dout_int8_11[8 -1]}},tru_dout_int8_11[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_12 ( + .data_in (tdata_out_12[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_12[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_12 ( + .data_in (tdata_out_12[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_12[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_12[15:0] = {{(16 - 8 ){tru_dout_int8_12[8 -1]}},tru_dout_int8_12[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_13 ( + .data_in (tdata_out_13[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_13[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_13 ( + .data_in (tdata_out_13[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_13[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_13[15:0] = {{(16 - 8 ){tru_dout_int8_13[8 -1]}},tru_dout_int8_13[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_14 ( + .data_in (tdata_out_14[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_14[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_14 ( + .data_in (tdata_out_14[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_14[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_14[15:0] = {{(16 - 8 ){tru_dout_int8_14[8 -1]}},tru_dout_int8_14[7:0]}; +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(2 )) int16_shiftright_su_15 ( + .data_in (tdata_out_15[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int16_15[15:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(18 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(2 )) int8_shiftright_su_15 ( + .data_in (tdata_out_15[17:0]) //|< w + ,.shift_num (cfg_truncate[1:0]) //|< w + ,.data_out (tru_dout_int8_15[7:0]) //|> w + ); +//signed +//unsigned +assign tru_dout_int8_ext_15[15:0] = {{(16 - 8 ){tru_dout_int8_15[8 -1]}},tru_dout_int8_15[7:0]}; +assign tru_dout_int16[255:0] = { tru_dout_int16_15, tru_dout_int16_14, tru_dout_int16_13, tru_dout_int16_12, tru_dout_int16_11, tru_dout_int16_10, tru_dout_int16_9, tru_dout_int16_8, tru_dout_int16_7, tru_dout_int16_6, tru_dout_int16_5, tru_dout_int16_4, tru_dout_int16_3, tru_dout_int16_2, tru_dout_int16_1, tru_dout_int16_0}; +assign tru_dout_int8_ext[255:0] = { tru_dout_int8_ext_15, tru_dout_int8_ext_14, tru_dout_int8_ext_13, tru_dout_int8_ext_12, tru_dout_int8_ext_11, tru_dout_int8_ext_10, tru_dout_int8_ext_9, tru_dout_int8_ext_8, tru_dout_int8_ext_7, tru_dout_int8_ext_6, tru_dout_int8_ext_5, tru_dout_int8_ext_4, tru_dout_int8_ext_3, tru_dout_int8_ext_2, tru_dout_int8_ext_1, tru_dout_int8_ext_0}; +NV_NVDLA_CSC_PRA_CELL_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.final_out_prdy (final_out_prdy) //|< w + ,.tout_pvld (tout_pvld) //|< w + ,.tru_dout_int16 (tru_dout_int16[255:0]) //|< w + ,.tru_dout_int8_ext (tru_dout_int8_ext[255:0]) //|< w + ,.final_out_pvld (final_out_pvld) //|> w + ,.tout_prdy (tout_prdy) //|> w + ,.tru_data_out_int16 (tru_data_out_int16[255:0]) //|> w + ,.tru_data_out_int8 (tru_data_out_int8[255:0]) //|> w + ); +assign chn_dout[255:0] = (cfg_precision[1:0] == 1 ) ? tru_data_out_int16[255:0] : tru_data_out_int8[255:0]; +NV_NVDLA_CSC_PRA_CELL_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_dout (chn_dout[255:0]) //|< w + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.final_out_pvld (final_out_pvld) //|< w + ,.chn_data_out (chn_data_out[255:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.final_out_prdy (final_out_prdy) //|> w + ); +endmodule // NV_NVDLA_CSC_pra_cell +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_reg[255:0] (din_pvld,din_prdy) <= chn_data_in[255:0] (chn_in_pvld,chn_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_data_in + ,chn_in_pvld + ,din_prdy + ,chn_data_reg + ,chn_in_prdy + ,din_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [255:0] chn_data_in; +input chn_in_pvld; +input din_prdy; +output [255:0] chn_data_reg; +output chn_in_prdy; +output din_pvld; +reg [255:0] chn_data_reg; +reg chn_in_prdy; +reg din_pvld; +reg [255:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [255:0] p1_skid_data; +reg [255:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + chn_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? chn_data_in[255:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_in_pvld + or p1_skid_valid + or chn_data_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? chn_data_in[255:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or din_prdy + or p1_pipe_data + ) begin + din_pvld = p1_pipe_valid; + p1_pipe_ready = din_prdy; + chn_data_reg[255:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (din_pvld^din_prdy^chn_in_pvld^chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_in_pvld && !chn_in_prdy), (chn_in_pvld), (chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mdata_out[271:0] (mout_pvld,mout_prdy) <= mdout[271:0] (din_pvld,din_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,din_pvld + ,mdout + ,mout_prdy + ,din_prdy + ,mdata_out + ,mout_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input din_pvld; +input [271:0] mdout; +input mout_prdy; +output din_prdy; +output [271:0] mdata_out; +output mout_pvld; +reg din_prdy; +reg [271:0] mdata_out; +reg mout_pvld; +reg [271:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [271:0] p2_skid_data; +reg [271:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + din_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = din_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + din_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + din_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mdout[271:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or din_pvld + or p2_skid_valid + or mdout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? din_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mdout[271:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mout_prdy + or p2_pipe_data + ) begin + mout_pvld = p2_pipe_valid; + p2_pipe_ready = mout_prdy; + mdata_out[271:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mout_pvld^mout_prdy^din_pvld^din_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (din_pvld && !din_prdy), (din_pvld), (din_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is tdata_out[287:0] (tout_pvld,tout_prdy) <= tdout[287:0] (mout_pvld,mout_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mout_pvld + ,tdout + ,tout_prdy + ,mout_prdy + ,tdata_out + ,tout_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mout_pvld; +input [287:0] tdout; +input tout_prdy; +output mout_prdy; +output [287:0] tdata_out; +output tout_pvld; +reg mout_prdy; +reg [287:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [287:0] p3_skid_data; +reg [287:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg [287:0] tdata_out; +reg tout_pvld; +//## pipe (3) skid buffer +always @( + mout_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mout_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mout_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mout_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? tdout[287:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mout_pvld + or p3_skid_valid + or tdout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mout_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? tdout[287:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tout_prdy + or p3_pipe_data + ) begin + tout_pvld = p3_pipe_valid; + p3_pipe_ready = tout_prdy; + tdata_out[287:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tout_pvld^tout_prdy^mout_pvld^mout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mout_pvld && !mout_prdy), (mout_pvld), (mout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {tru_data_out_int16[255:0],tru_data_out_int8[255:0]} (final_out_pvld,final_out_prdy) <= {tru_dout_int16[255:0],tru_dout_int8_ext[255:0]} (tout_pvld,tout_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,final_out_prdy + ,tout_pvld + ,tru_dout_int16 + ,tru_dout_int8_ext + ,final_out_pvld + ,tout_prdy + ,tru_data_out_int16 + ,tru_data_out_int8 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input final_out_prdy; +input tout_pvld; +input [255:0] tru_dout_int16; +input [255:0] tru_dout_int8_ext; +output final_out_pvld; +output tout_prdy; +output [255:0] tru_data_out_int16; +output [255:0] tru_data_out_int8; +reg final_out_pvld; +reg [511:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [511:0] p4_skid_data; +reg [511:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +reg tout_prdy; +reg [255:0] tru_data_out_int16; +reg [255:0] tru_data_out_int8; +//## pipe (4) skid buffer +always @( + tout_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = tout_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + tout_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + tout_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? {tru_dout_int16[255:0],tru_dout_int8_ext[255:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or tout_pvld + or p4_skid_valid + or tru_dout_int16 + or tru_dout_int8_ext + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? tout_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? {tru_dout_int16[255:0],tru_dout_int8_ext[255:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or final_out_prdy + or p4_pipe_data + ) begin + final_out_pvld = p4_pipe_valid; + p4_pipe_ready = final_out_prdy; + {tru_data_out_int16[255:0],tru_data_out_int8[255:0]} = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (final_out_pvld^final_out_prdy^tout_pvld^tout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (tout_pvld && !tout_prdy), (tout_pvld), (tout_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[255:0] (chn_out_pvld,chn_out_prdy) <= chn_dout[255:0] (final_out_pvld,final_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CSC_PRA_CELL_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_dout + ,chn_out_prdy + ,final_out_pvld + ,chn_data_out + ,chn_out_pvld + ,final_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [255:0] chn_dout; +input chn_out_prdy; +input final_out_pvld; +output [255:0] chn_data_out; +output chn_out_pvld; +output final_out_prdy; +reg [255:0] chn_data_out; +reg chn_out_pvld; +reg final_out_prdy; +reg [255:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [255:0] p5_skid_data; +reg [255:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +//## pipe (5) skid buffer +always @( + final_out_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = final_out_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + final_out_prdy <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + final_out_prdy <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? chn_dout[255:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or final_out_pvld + or p5_skid_valid + or chn_dout + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? final_out_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? chn_dout[255:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or chn_out_prdy + or p5_pipe_data + ) begin + chn_out_pvld = p5_pipe_valid; + p5_pipe_ready = chn_out_prdy; + chn_data_out[255:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^final_out_pvld^final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (final_out_pvld && !final_out_prdy), (final_out_pvld), (final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CSC_PRA_CELL_pipe_p5 diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v new file mode 100644 index 0000000..7c199b5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v @@ -0,0 +1,1054 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CSC_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2csc_req_pd //|< i + ,csb2csc_req_pvld //|< i + ,dp2reg_done //|< i + ,csb2csc_req_prdy //|> o + ,csc2csb_resp_pd //|> o + ,csc2csb_resp_valid //|> o + ,reg2dp_atomics //|> o + ,reg2dp_batches //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_conv_x_stride_ext //|> o + ,reg2dp_conv_y_stride_ext //|> o + ,reg2dp_cya //|> o + ,reg2dp_data_bank //|> o + ,reg2dp_data_reuse //|> o + ,reg2dp_datain_channel_ext //|> o + ,reg2dp_datain_format //|> o + ,reg2dp_datain_height_ext //|> o + ,reg2dp_datain_width_ext //|> o + ,reg2dp_dataout_channel //|> o + ,reg2dp_dataout_height //|> o + ,reg2dp_dataout_width //|> o + ,reg2dp_entries //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_left //|> o + ,reg2dp_pad_top //|> o + ,reg2dp_pad_value //|> o + ,reg2dp_pra_truncate //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_rls_slices //|> o + ,reg2dp_skip_data_rls //|> o + ,reg2dp_skip_weight_rls //|> o + ,reg2dp_weight_bank //|> o + ,reg2dp_weight_bytes //|> o + ,reg2dp_weight_channel_ext //|> o + ,reg2dp_weight_format //|> o + ,reg2dp_weight_height_ext //|> o + ,reg2dp_weight_kernel //|> o + ,reg2dp_weight_reuse //|> o + ,reg2dp_weight_width_ext //|> o + ,reg2dp_wmb_bytes //|> o + ,reg2dp_x_dilation_ext //|> o + ,reg2dp_y_dilation_ext //|> o + ,reg2dp_y_extension //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2csc_req_pd; +input csb2csc_req_pvld; +input dp2reg_done; +output csb2csc_req_prdy; +output [33:0] csc2csb_resp_pd; +output csc2csb_resp_valid; +output [20:0] reg2dp_atomics; +output [4:0] reg2dp_batches; +output reg2dp_conv_mode; +output [2:0] reg2dp_conv_x_stride_ext; +output [2:0] reg2dp_conv_y_stride_ext; +output [31:0] reg2dp_cya; +output [4:0] reg2dp_data_bank; +output reg2dp_data_reuse; +output [12:0] reg2dp_datain_channel_ext; +output reg2dp_datain_format; +output [12:0] reg2dp_datain_height_ext; +output [12:0] reg2dp_datain_width_ext; +output [12:0] reg2dp_dataout_channel; +output [12:0] reg2dp_dataout_height; +output [12:0] reg2dp_dataout_width; +output [13:0] reg2dp_entries; +output [1:0] reg2dp_in_precision; +output reg2dp_op_en; +output [4:0] reg2dp_pad_left; +output [4:0] reg2dp_pad_top; +output [15:0] reg2dp_pad_value; +output [1:0] reg2dp_pra_truncate; +output [1:0] reg2dp_proc_precision; +output [11:0] reg2dp_rls_slices; +output reg2dp_skip_data_rls; +output reg2dp_skip_weight_rls; +output [4:0] reg2dp_weight_bank; +output [31:0] reg2dp_weight_bytes; +output [12:0] reg2dp_weight_channel_ext; +output reg2dp_weight_format; +output [4:0] reg2dp_weight_height_ext; +output [12:0] reg2dp_weight_kernel; +output reg2dp_weight_reuse; +output [4:0] reg2dp_weight_width_ext; +output [27:0] reg2dp_wmb_bytes; +output [4:0] reg2dp_x_dilation_ext; +output [4:0] reg2dp_y_dilation_ext; +output [1:0] reg2dp_y_extension; +output [3:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [20:0] reg2dp_d0_atomics; +wire [4:0] reg2dp_d0_batches; +wire reg2dp_d0_conv_mode; +wire [2:0] reg2dp_d0_conv_x_stride_ext; +wire [2:0] reg2dp_d0_conv_y_stride_ext; +wire [31:0] reg2dp_d0_cya; +wire [4:0] reg2dp_d0_data_bank; +wire reg2dp_d0_data_reuse; +wire [12:0] reg2dp_d0_datain_channel_ext; +wire reg2dp_d0_datain_format; +wire [12:0] reg2dp_d0_datain_height_ext; +wire [12:0] reg2dp_d0_datain_width_ext; +wire [12:0] reg2dp_d0_dataout_channel; +wire [12:0] reg2dp_d0_dataout_height; +wire [12:0] reg2dp_d0_dataout_width; +wire [13:0] reg2dp_d0_entries; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_op_en_trigger; +wire [4:0] reg2dp_d0_pad_left; +wire [4:0] reg2dp_d0_pad_top; +wire [15:0] reg2dp_d0_pad_value; +wire [1:0] reg2dp_d0_pra_truncate; +wire [1:0] reg2dp_d0_proc_precision; +wire [11:0] reg2dp_d0_rls_slices; +wire reg2dp_d0_skip_data_rls; +wire reg2dp_d0_skip_weight_rls; +wire [4:0] reg2dp_d0_weight_bank; +wire [31:0] reg2dp_d0_weight_bytes; +wire [12:0] reg2dp_d0_weight_channel_ext; +wire reg2dp_d0_weight_format; +wire [4:0] reg2dp_d0_weight_height_ext; +wire [12:0] reg2dp_d0_weight_kernel; +wire reg2dp_d0_weight_reuse; +wire [4:0] reg2dp_d0_weight_width_ext; +wire [27:0] reg2dp_d0_wmb_bytes; +wire [4:0] reg2dp_d0_x_dilation_ext; +wire [4:0] reg2dp_d0_y_dilation_ext; +wire [1:0] reg2dp_d0_y_extension; +wire [20:0] reg2dp_d1_atomics; +wire [4:0] reg2dp_d1_batches; +wire reg2dp_d1_conv_mode; +wire [2:0] reg2dp_d1_conv_x_stride_ext; +wire [2:0] reg2dp_d1_conv_y_stride_ext; +wire [31:0] reg2dp_d1_cya; +wire [4:0] reg2dp_d1_data_bank; +wire reg2dp_d1_data_reuse; +wire [12:0] reg2dp_d1_datain_channel_ext; +wire reg2dp_d1_datain_format; +wire [12:0] reg2dp_d1_datain_height_ext; +wire [12:0] reg2dp_d1_datain_width_ext; +wire [12:0] reg2dp_d1_dataout_channel; +wire [12:0] reg2dp_d1_dataout_height; +wire [12:0] reg2dp_d1_dataout_width; +wire [13:0] reg2dp_d1_entries; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_op_en_trigger; +wire [4:0] reg2dp_d1_pad_left; +wire [4:0] reg2dp_d1_pad_top; +wire [15:0] reg2dp_d1_pad_value; +wire [1:0] reg2dp_d1_pra_truncate; +wire [1:0] reg2dp_d1_proc_precision; +wire [11:0] reg2dp_d1_rls_slices; +wire reg2dp_d1_skip_data_rls; +wire reg2dp_d1_skip_weight_rls; +wire [4:0] reg2dp_d1_weight_bank; +wire [31:0] reg2dp_d1_weight_bytes; +wire [12:0] reg2dp_d1_weight_channel_ext; +wire reg2dp_d1_weight_format; +wire [4:0] reg2dp_d1_weight_height_ext; +wire [12:0] reg2dp_d1_weight_kernel; +wire reg2dp_d1_weight_reuse; +wire [4:0] reg2dp_d1_weight_width_ext; +wire [27:0] reg2dp_d1_wmb_bytes; +wire [4:0] reg2dp_d1_x_dilation_ext; +wire [4:0] reg2dp_d1_y_dilation_ext; +wire [1:0] reg2dp_d1_y_extension; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en_d0; +reg [33:0] csc2csb_resp_pd; +reg csc2csb_resp_valid; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [20:0] reg2dp_atomics; +reg [4:0] reg2dp_batches; +reg reg2dp_conv_mode; +reg [2:0] reg2dp_conv_x_stride_ext; +reg [2:0] reg2dp_conv_y_stride_ext; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [4:0] reg2dp_data_bank; +reg reg2dp_data_reuse; +reg [12:0] reg2dp_datain_channel_ext; +reg reg2dp_datain_format; +reg [12:0] reg2dp_datain_height_ext; +reg [12:0] reg2dp_datain_width_ext; +reg [12:0] reg2dp_dataout_channel; +reg [12:0] reg2dp_dataout_height; +reg [12:0] reg2dp_dataout_width; +reg [13:0] reg2dp_entries; +reg [1:0] reg2dp_in_precision; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [4:0] reg2dp_pad_left; +reg [4:0] reg2dp_pad_top; +reg [15:0] reg2dp_pad_value; +reg [1:0] reg2dp_pra_truncate; +reg [1:0] reg2dp_proc_precision; +reg [11:0] reg2dp_rls_slices; +reg reg2dp_skip_data_rls; +reg reg2dp_skip_weight_rls; +reg [4:0] reg2dp_weight_bank; +reg [31:0] reg2dp_weight_bytes; +reg [12:0] reg2dp_weight_channel_ext; +reg reg2dp_weight_format; +reg [4:0] reg2dp_weight_height_ext; +reg [12:0] reg2dp_weight_kernel; +reg reg2dp_weight_reuse; +reg [4:0] reg2dp_weight_width_ext; +reg [27:0] reg2dp_wmb_bytes; +reg [4:0] reg2dp_x_dilation_ext; +reg [4:0] reg2dp_y_dilation_ext; +reg [1:0] reg2dp_y_extension; +reg [62:0] req_pd; +reg req_pvld; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CSC_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CSC_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.atomics (reg2dp_d0_atomics[20:0]) //|> w + ,.data_bank (reg2dp_d0_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d0_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d0_batches[4:0]) //|> w + ,.conv_x_stride_ext (reg2dp_d0_conv_x_stride_ext[2:0]) //|> w + ,.conv_y_stride_ext (reg2dp_d0_conv_y_stride_ext[2:0]) //|> w + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.datain_format (reg2dp_d0_datain_format) //|> w + ,.datain_height_ext (reg2dp_d0_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d0_datain_width_ext[12:0]) //|> w + ,.datain_channel_ext (reg2dp_d0_datain_channel_ext[12:0]) //|> w + ,.dataout_height (reg2dp_d0_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d0_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d0_dataout_channel[12:0]) //|> w + ,.x_dilation_ext (reg2dp_d0_x_dilation_ext[4:0]) //|> w + ,.y_dilation_ext (reg2dp_d0_y_dilation_ext[4:0]) //|> w + ,.entries (reg2dp_d0_entries[13:0]) //|> w + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.data_reuse (reg2dp_d0_data_reuse) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d0_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d0_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d0_weight_reuse) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.y_extension (reg2dp_d0_y_extension[1:0]) //|> w + ,.pra_truncate (reg2dp_d0_pra_truncate[1:0]) //|> w + ,.rls_slices (reg2dp_d0_rls_slices[11:0]) //|> w + ,.weight_bytes (reg2dp_d0_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d0_weight_format) //|> w + ,.weight_height_ext (reg2dp_d0_weight_height_ext[4:0]) //|> w + ,.weight_width_ext (reg2dp_d0_weight_width_ext[4:0]) //|> w + ,.weight_channel_ext (reg2dp_d0_weight_channel_ext[12:0]) //|> w + ,.weight_kernel (reg2dp_d0_weight_kernel[12:0]) //|> w + ,.wmb_bytes (reg2dp_d0_wmb_bytes[27:0]) //|> w + ,.pad_left (reg2dp_d0_pad_left[4:0]) //|> w + ,.pad_top (reg2dp_d0_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d0_pad_value[15:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ); +NV_NVDLA_CSC_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.atomics (reg2dp_d1_atomics[20:0]) //|> w + ,.data_bank (reg2dp_d1_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d1_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d1_batches[4:0]) //|> w + ,.conv_x_stride_ext (reg2dp_d1_conv_x_stride_ext[2:0]) //|> w + ,.conv_y_stride_ext (reg2dp_d1_conv_y_stride_ext[2:0]) //|> w + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.datain_format (reg2dp_d1_datain_format) //|> w + ,.datain_height_ext (reg2dp_d1_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d1_datain_width_ext[12:0]) //|> w + ,.datain_channel_ext (reg2dp_d1_datain_channel_ext[12:0]) //|> w + ,.dataout_height (reg2dp_d1_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d1_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d1_dataout_channel[12:0]) //|> w + ,.x_dilation_ext (reg2dp_d1_x_dilation_ext[4:0]) //|> w + ,.y_dilation_ext (reg2dp_d1_y_dilation_ext[4:0]) //|> w + ,.entries (reg2dp_d1_entries[13:0]) //|> w + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.data_reuse (reg2dp_d1_data_reuse) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d1_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d1_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d1_weight_reuse) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.y_extension (reg2dp_d1_y_extension[1:0]) //|> w + ,.pra_truncate (reg2dp_d1_pra_truncate[1:0]) //|> w + ,.rls_slices (reg2dp_d1_rls_slices[11:0]) //|> w + ,.weight_bytes (reg2dp_d1_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d1_weight_format) //|> w + ,.weight_height_ext (reg2dp_d1_weight_height_ext[4:0]) //|> w + ,.weight_width_ext (reg2dp_d1_weight_width_ext[4:0]) //|> w + ,.weight_channel_ext (reg2dp_d1_weight_channel_ext[12:0]) //|> w + ,.weight_kernel (reg2dp_d1_weight_kernel[12:0]) //|> w + ,.wmb_bytes (reg2dp_d1_wmb_bytes[27:0]) //|> w + ,.pad_left (reg2dp_d1_pad_left[4:0]) //|> w + ,.pad_top (reg2dp_d1_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d1_pad_value[15:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h6008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h6008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h6008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2csc_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2csc_req_pvld) == 1'b1) begin + req_pd <= csb2csc_req_pd; +// VCS coverage off + end else if ((csb2csc_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2csc_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2csc_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + csc2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + csc2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc2csb_resp_valid <= 1'b0; + end else begin + csc2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_atomics + or reg2dp_d0_atomics + ) begin + reg2dp_atomics = dp2reg_consumer ? reg2dp_d1_atomics : reg2dp_d0_atomics; +end +always @( + dp2reg_consumer + or reg2dp_d1_data_bank + or reg2dp_d0_data_bank + ) begin + reg2dp_data_bank = dp2reg_consumer ? reg2dp_d1_data_bank : reg2dp_d0_data_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bank + or reg2dp_d0_weight_bank + ) begin + reg2dp_weight_bank = dp2reg_consumer ? reg2dp_d1_weight_bank : reg2dp_d0_weight_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_batches + or reg2dp_d0_batches + ) begin + reg2dp_batches = dp2reg_consumer ? reg2dp_d1_batches : reg2dp_d0_batches; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_x_stride_ext + or reg2dp_d0_conv_x_stride_ext + ) begin + reg2dp_conv_x_stride_ext = dp2reg_consumer ? reg2dp_d1_conv_x_stride_ext : reg2dp_d0_conv_x_stride_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_y_stride_ext + or reg2dp_d0_conv_y_stride_ext + ) begin + reg2dp_conv_y_stride_ext = dp2reg_consumer ? reg2dp_d1_conv_y_stride_ext : reg2dp_d0_conv_y_stride_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_format + or reg2dp_d0_datain_format + ) begin + reg2dp_datain_format = dp2reg_consumer ? reg2dp_d1_datain_format : reg2dp_d0_datain_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height_ext + or reg2dp_d0_datain_height_ext + ) begin + reg2dp_datain_height_ext = dp2reg_consumer ? reg2dp_d1_datain_height_ext : reg2dp_d0_datain_height_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width_ext + or reg2dp_d0_datain_width_ext + ) begin + reg2dp_datain_width_ext = dp2reg_consumer ? reg2dp_d1_datain_width_ext : reg2dp_d0_datain_width_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_channel_ext + or reg2dp_d0_datain_channel_ext + ) begin + reg2dp_datain_channel_ext = dp2reg_consumer ? reg2dp_d1_datain_channel_ext : reg2dp_d0_datain_channel_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_height + or reg2dp_d0_dataout_height + ) begin + reg2dp_dataout_height = dp2reg_consumer ? reg2dp_d1_dataout_height : reg2dp_d0_dataout_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_width + or reg2dp_d0_dataout_width + ) begin + reg2dp_dataout_width = dp2reg_consumer ? reg2dp_d1_dataout_width : reg2dp_d0_dataout_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_channel + or reg2dp_d0_dataout_channel + ) begin + reg2dp_dataout_channel = dp2reg_consumer ? reg2dp_d1_dataout_channel : reg2dp_d0_dataout_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_x_dilation_ext + or reg2dp_d0_x_dilation_ext + ) begin + reg2dp_x_dilation_ext = dp2reg_consumer ? reg2dp_d1_x_dilation_ext : reg2dp_d0_x_dilation_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_y_dilation_ext + or reg2dp_d0_y_dilation_ext + ) begin + reg2dp_y_dilation_ext = dp2reg_consumer ? reg2dp_d1_y_dilation_ext : reg2dp_d0_y_dilation_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_entries + or reg2dp_d0_entries + ) begin + reg2dp_entries = dp2reg_consumer ? reg2dp_d1_entries : reg2dp_d0_entries; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_data_reuse + or reg2dp_d0_data_reuse + ) begin + reg2dp_data_reuse = dp2reg_consumer ? reg2dp_d1_data_reuse : reg2dp_d0_data_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_data_rls + or reg2dp_d0_skip_data_rls + ) begin + reg2dp_skip_data_rls = dp2reg_consumer ? reg2dp_d1_skip_data_rls : reg2dp_d0_skip_data_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_weight_rls + or reg2dp_d0_skip_weight_rls + ) begin + reg2dp_skip_weight_rls = dp2reg_consumer ? reg2dp_d1_skip_weight_rls : reg2dp_d0_skip_weight_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_reuse + or reg2dp_d0_weight_reuse + ) begin + reg2dp_weight_reuse = dp2reg_consumer ? reg2dp_d1_weight_reuse : reg2dp_d0_weight_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_y_extension + or reg2dp_d0_y_extension + ) begin + reg2dp_y_extension = dp2reg_consumer ? reg2dp_d1_y_extension : reg2dp_d0_y_extension; +end +always @( + dp2reg_consumer + or reg2dp_d1_pra_truncate + or reg2dp_d0_pra_truncate + ) begin + reg2dp_pra_truncate = dp2reg_consumer ? reg2dp_d1_pra_truncate : reg2dp_d0_pra_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_rls_slices + or reg2dp_d0_rls_slices + ) begin + reg2dp_rls_slices = dp2reg_consumer ? reg2dp_d1_rls_slices : reg2dp_d0_rls_slices; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bytes + or reg2dp_d0_weight_bytes + ) begin + reg2dp_weight_bytes = dp2reg_consumer ? reg2dp_d1_weight_bytes : reg2dp_d0_weight_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_format + or reg2dp_d0_weight_format + ) begin + reg2dp_weight_format = dp2reg_consumer ? reg2dp_d1_weight_format : reg2dp_d0_weight_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_height_ext + or reg2dp_d0_weight_height_ext + ) begin + reg2dp_weight_height_ext = dp2reg_consumer ? reg2dp_d1_weight_height_ext : reg2dp_d0_weight_height_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_width_ext + or reg2dp_d0_weight_width_ext + ) begin + reg2dp_weight_width_ext = dp2reg_consumer ? reg2dp_d1_weight_width_ext : reg2dp_d0_weight_width_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_channel_ext + or reg2dp_d0_weight_channel_ext + ) begin + reg2dp_weight_channel_ext = dp2reg_consumer ? reg2dp_d1_weight_channel_ext : reg2dp_d0_weight_channel_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_kernel + or reg2dp_d0_weight_kernel + ) begin + reg2dp_weight_kernel = dp2reg_consumer ? reg2dp_d1_weight_kernel : reg2dp_d0_weight_kernel; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_bytes + or reg2dp_d0_wmb_bytes + ) begin + reg2dp_wmb_bytes = dp2reg_consumer ? reg2dp_d1_wmb_bytes : reg2dp_d0_wmb_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_left + or reg2dp_d0_pad_left + ) begin + reg2dp_pad_left = dp2reg_consumer ? reg2dp_d1_pad_left : reg2dp_d0_pad_left; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_top + or reg2dp_d0_pad_top + ) begin + reg2dp_pad_top = dp2reg_consumer ? reg2dp_d1_pad_top : reg2dp_d0_pad_top; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value + or reg2dp_d0_pad_value + ) begin + reg2dp_pad_value = dp2reg_consumer ? reg2dp_d1_pad_value : reg2dp_d0_pad_value; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_CSC_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v.vcp new file mode 100644 index 0000000..7c199b5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v.vcp @@ -0,0 +1,1054 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_CSC_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2csc_req_pd //|< i + ,csb2csc_req_pvld //|< i + ,dp2reg_done //|< i + ,csb2csc_req_prdy //|> o + ,csc2csb_resp_pd //|> o + ,csc2csb_resp_valid //|> o + ,reg2dp_atomics //|> o + ,reg2dp_batches //|> o + ,reg2dp_conv_mode //|> o + ,reg2dp_conv_x_stride_ext //|> o + ,reg2dp_conv_y_stride_ext //|> o + ,reg2dp_cya //|> o + ,reg2dp_data_bank //|> o + ,reg2dp_data_reuse //|> o + ,reg2dp_datain_channel_ext //|> o + ,reg2dp_datain_format //|> o + ,reg2dp_datain_height_ext //|> o + ,reg2dp_datain_width_ext //|> o + ,reg2dp_dataout_channel //|> o + ,reg2dp_dataout_height //|> o + ,reg2dp_dataout_width //|> o + ,reg2dp_entries //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_left //|> o + ,reg2dp_pad_top //|> o + ,reg2dp_pad_value //|> o + ,reg2dp_pra_truncate //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_rls_slices //|> o + ,reg2dp_skip_data_rls //|> o + ,reg2dp_skip_weight_rls //|> o + ,reg2dp_weight_bank //|> o + ,reg2dp_weight_bytes //|> o + ,reg2dp_weight_channel_ext //|> o + ,reg2dp_weight_format //|> o + ,reg2dp_weight_height_ext //|> o + ,reg2dp_weight_kernel //|> o + ,reg2dp_weight_reuse //|> o + ,reg2dp_weight_width_ext //|> o + ,reg2dp_wmb_bytes //|> o + ,reg2dp_x_dilation_ext //|> o + ,reg2dp_y_dilation_ext //|> o + ,reg2dp_y_extension //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2csc_req_pd; +input csb2csc_req_pvld; +input dp2reg_done; +output csb2csc_req_prdy; +output [33:0] csc2csb_resp_pd; +output csc2csb_resp_valid; +output [20:0] reg2dp_atomics; +output [4:0] reg2dp_batches; +output reg2dp_conv_mode; +output [2:0] reg2dp_conv_x_stride_ext; +output [2:0] reg2dp_conv_y_stride_ext; +output [31:0] reg2dp_cya; +output [4:0] reg2dp_data_bank; +output reg2dp_data_reuse; +output [12:0] reg2dp_datain_channel_ext; +output reg2dp_datain_format; +output [12:0] reg2dp_datain_height_ext; +output [12:0] reg2dp_datain_width_ext; +output [12:0] reg2dp_dataout_channel; +output [12:0] reg2dp_dataout_height; +output [12:0] reg2dp_dataout_width; +output [13:0] reg2dp_entries; +output [1:0] reg2dp_in_precision; +output reg2dp_op_en; +output [4:0] reg2dp_pad_left; +output [4:0] reg2dp_pad_top; +output [15:0] reg2dp_pad_value; +output [1:0] reg2dp_pra_truncate; +output [1:0] reg2dp_proc_precision; +output [11:0] reg2dp_rls_slices; +output reg2dp_skip_data_rls; +output reg2dp_skip_weight_rls; +output [4:0] reg2dp_weight_bank; +output [31:0] reg2dp_weight_bytes; +output [12:0] reg2dp_weight_channel_ext; +output reg2dp_weight_format; +output [4:0] reg2dp_weight_height_ext; +output [12:0] reg2dp_weight_kernel; +output reg2dp_weight_reuse; +output [4:0] reg2dp_weight_width_ext; +output [27:0] reg2dp_wmb_bytes; +output [4:0] reg2dp_x_dilation_ext; +output [4:0] reg2dp_y_dilation_ext; +output [1:0] reg2dp_y_extension; +output [3:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [20:0] reg2dp_d0_atomics; +wire [4:0] reg2dp_d0_batches; +wire reg2dp_d0_conv_mode; +wire [2:0] reg2dp_d0_conv_x_stride_ext; +wire [2:0] reg2dp_d0_conv_y_stride_ext; +wire [31:0] reg2dp_d0_cya; +wire [4:0] reg2dp_d0_data_bank; +wire reg2dp_d0_data_reuse; +wire [12:0] reg2dp_d0_datain_channel_ext; +wire reg2dp_d0_datain_format; +wire [12:0] reg2dp_d0_datain_height_ext; +wire [12:0] reg2dp_d0_datain_width_ext; +wire [12:0] reg2dp_d0_dataout_channel; +wire [12:0] reg2dp_d0_dataout_height; +wire [12:0] reg2dp_d0_dataout_width; +wire [13:0] reg2dp_d0_entries; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_op_en_trigger; +wire [4:0] reg2dp_d0_pad_left; +wire [4:0] reg2dp_d0_pad_top; +wire [15:0] reg2dp_d0_pad_value; +wire [1:0] reg2dp_d0_pra_truncate; +wire [1:0] reg2dp_d0_proc_precision; +wire [11:0] reg2dp_d0_rls_slices; +wire reg2dp_d0_skip_data_rls; +wire reg2dp_d0_skip_weight_rls; +wire [4:0] reg2dp_d0_weight_bank; +wire [31:0] reg2dp_d0_weight_bytes; +wire [12:0] reg2dp_d0_weight_channel_ext; +wire reg2dp_d0_weight_format; +wire [4:0] reg2dp_d0_weight_height_ext; +wire [12:0] reg2dp_d0_weight_kernel; +wire reg2dp_d0_weight_reuse; +wire [4:0] reg2dp_d0_weight_width_ext; +wire [27:0] reg2dp_d0_wmb_bytes; +wire [4:0] reg2dp_d0_x_dilation_ext; +wire [4:0] reg2dp_d0_y_dilation_ext; +wire [1:0] reg2dp_d0_y_extension; +wire [20:0] reg2dp_d1_atomics; +wire [4:0] reg2dp_d1_batches; +wire reg2dp_d1_conv_mode; +wire [2:0] reg2dp_d1_conv_x_stride_ext; +wire [2:0] reg2dp_d1_conv_y_stride_ext; +wire [31:0] reg2dp_d1_cya; +wire [4:0] reg2dp_d1_data_bank; +wire reg2dp_d1_data_reuse; +wire [12:0] reg2dp_d1_datain_channel_ext; +wire reg2dp_d1_datain_format; +wire [12:0] reg2dp_d1_datain_height_ext; +wire [12:0] reg2dp_d1_datain_width_ext; +wire [12:0] reg2dp_d1_dataout_channel; +wire [12:0] reg2dp_d1_dataout_height; +wire [12:0] reg2dp_d1_dataout_width; +wire [13:0] reg2dp_d1_entries; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_op_en_trigger; +wire [4:0] reg2dp_d1_pad_left; +wire [4:0] reg2dp_d1_pad_top; +wire [15:0] reg2dp_d1_pad_value; +wire [1:0] reg2dp_d1_pra_truncate; +wire [1:0] reg2dp_d1_proc_precision; +wire [11:0] reg2dp_d1_rls_slices; +wire reg2dp_d1_skip_data_rls; +wire reg2dp_d1_skip_weight_rls; +wire [4:0] reg2dp_d1_weight_bank; +wire [31:0] reg2dp_d1_weight_bytes; +wire [12:0] reg2dp_d1_weight_channel_ext; +wire reg2dp_d1_weight_format; +wire [4:0] reg2dp_d1_weight_height_ext; +wire [12:0] reg2dp_d1_weight_kernel; +wire reg2dp_d1_weight_reuse; +wire [4:0] reg2dp_d1_weight_width_ext; +wire [27:0] reg2dp_d1_wmb_bytes; +wire [4:0] reg2dp_d1_x_dilation_ext; +wire [4:0] reg2dp_d1_y_dilation_ext; +wire [1:0] reg2dp_d1_y_extension; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en_d0; +reg [33:0] csc2csb_resp_pd; +reg csc2csb_resp_valid; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [20:0] reg2dp_atomics; +reg [4:0] reg2dp_batches; +reg reg2dp_conv_mode; +reg [2:0] reg2dp_conv_x_stride_ext; +reg [2:0] reg2dp_conv_y_stride_ext; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [4:0] reg2dp_data_bank; +reg reg2dp_data_reuse; +reg [12:0] reg2dp_datain_channel_ext; +reg reg2dp_datain_format; +reg [12:0] reg2dp_datain_height_ext; +reg [12:0] reg2dp_datain_width_ext; +reg [12:0] reg2dp_dataout_channel; +reg [12:0] reg2dp_dataout_height; +reg [12:0] reg2dp_dataout_width; +reg [13:0] reg2dp_entries; +reg [1:0] reg2dp_in_precision; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [4:0] reg2dp_pad_left; +reg [4:0] reg2dp_pad_top; +reg [15:0] reg2dp_pad_value; +reg [1:0] reg2dp_pra_truncate; +reg [1:0] reg2dp_proc_precision; +reg [11:0] reg2dp_rls_slices; +reg reg2dp_skip_data_rls; +reg reg2dp_skip_weight_rls; +reg [4:0] reg2dp_weight_bank; +reg [31:0] reg2dp_weight_bytes; +reg [12:0] reg2dp_weight_channel_ext; +reg reg2dp_weight_format; +reg [4:0] reg2dp_weight_height_ext; +reg [12:0] reg2dp_weight_kernel; +reg reg2dp_weight_reuse; +reg [4:0] reg2dp_weight_width_ext; +reg [27:0] reg2dp_wmb_bytes; +reg [4:0] reg2dp_x_dilation_ext; +reg [4:0] reg2dp_y_dilation_ext; +reg [1:0] reg2dp_y_extension; +reg [62:0] req_pd; +reg req_pvld; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_CSC_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_CSC_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.atomics (reg2dp_d0_atomics[20:0]) //|> w + ,.data_bank (reg2dp_d0_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d0_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d0_batches[4:0]) //|> w + ,.conv_x_stride_ext (reg2dp_d0_conv_x_stride_ext[2:0]) //|> w + ,.conv_y_stride_ext (reg2dp_d0_conv_y_stride_ext[2:0]) //|> w + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.datain_format (reg2dp_d0_datain_format) //|> w + ,.datain_height_ext (reg2dp_d0_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d0_datain_width_ext[12:0]) //|> w + ,.datain_channel_ext (reg2dp_d0_datain_channel_ext[12:0]) //|> w + ,.dataout_height (reg2dp_d0_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d0_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d0_dataout_channel[12:0]) //|> w + ,.x_dilation_ext (reg2dp_d0_x_dilation_ext[4:0]) //|> w + ,.y_dilation_ext (reg2dp_d0_y_dilation_ext[4:0]) //|> w + ,.entries (reg2dp_d0_entries[13:0]) //|> w + ,.conv_mode (reg2dp_d0_conv_mode) //|> w + ,.data_reuse (reg2dp_d0_data_reuse) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d0_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d0_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d0_weight_reuse) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.y_extension (reg2dp_d0_y_extension[1:0]) //|> w + ,.pra_truncate (reg2dp_d0_pra_truncate[1:0]) //|> w + ,.rls_slices (reg2dp_d0_rls_slices[11:0]) //|> w + ,.weight_bytes (reg2dp_d0_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d0_weight_format) //|> w + ,.weight_height_ext (reg2dp_d0_weight_height_ext[4:0]) //|> w + ,.weight_width_ext (reg2dp_d0_weight_width_ext[4:0]) //|> w + ,.weight_channel_ext (reg2dp_d0_weight_channel_ext[12:0]) //|> w + ,.weight_kernel (reg2dp_d0_weight_kernel[12:0]) //|> w + ,.wmb_bytes (reg2dp_d0_wmb_bytes[27:0]) //|> w + ,.pad_left (reg2dp_d0_pad_left[4:0]) //|> w + ,.pad_top (reg2dp_d0_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d0_pad_value[15:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ); +NV_NVDLA_CSC_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.atomics (reg2dp_d1_atomics[20:0]) //|> w + ,.data_bank (reg2dp_d1_data_bank[4:0]) //|> w + ,.weight_bank (reg2dp_d1_weight_bank[4:0]) //|> w + ,.batches (reg2dp_d1_batches[4:0]) //|> w + ,.conv_x_stride_ext (reg2dp_d1_conv_x_stride_ext[2:0]) //|> w + ,.conv_y_stride_ext (reg2dp_d1_conv_y_stride_ext[2:0]) //|> w + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.datain_format (reg2dp_d1_datain_format) //|> w + ,.datain_height_ext (reg2dp_d1_datain_height_ext[12:0]) //|> w + ,.datain_width_ext (reg2dp_d1_datain_width_ext[12:0]) //|> w + ,.datain_channel_ext (reg2dp_d1_datain_channel_ext[12:0]) //|> w + ,.dataout_height (reg2dp_d1_dataout_height[12:0]) //|> w + ,.dataout_width (reg2dp_d1_dataout_width[12:0]) //|> w + ,.dataout_channel (reg2dp_d1_dataout_channel[12:0]) //|> w + ,.x_dilation_ext (reg2dp_d1_x_dilation_ext[4:0]) //|> w + ,.y_dilation_ext (reg2dp_d1_y_dilation_ext[4:0]) //|> w + ,.entries (reg2dp_d1_entries[13:0]) //|> w + ,.conv_mode (reg2dp_d1_conv_mode) //|> w + ,.data_reuse (reg2dp_d1_data_reuse) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.skip_data_rls (reg2dp_d1_skip_data_rls) //|> w + ,.skip_weight_rls (reg2dp_d1_skip_weight_rls) //|> w + ,.weight_reuse (reg2dp_d1_weight_reuse) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.y_extension (reg2dp_d1_y_extension[1:0]) //|> w + ,.pra_truncate (reg2dp_d1_pra_truncate[1:0]) //|> w + ,.rls_slices (reg2dp_d1_rls_slices[11:0]) //|> w + ,.weight_bytes (reg2dp_d1_weight_bytes[31:0]) //|> w + ,.weight_format (reg2dp_d1_weight_format) //|> w + ,.weight_height_ext (reg2dp_d1_weight_height_ext[4:0]) //|> w + ,.weight_width_ext (reg2dp_d1_weight_width_ext[4:0]) //|> w + ,.weight_channel_ext (reg2dp_d1_weight_channel_ext[12:0]) //|> w + ,.weight_kernel (reg2dp_d1_weight_kernel[12:0]) //|> w + ,.wmb_bytes (reg2dp_d1_wmb_bytes[27:0]) //|> w + ,.pad_left (reg2dp_d1_pad_left[4:0]) //|> w + ,.pad_top (reg2dp_d1_pad_top[4:0]) //|> w + ,.pad_value (reg2dp_d1_pad_value[15:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h6008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h6008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h6008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2csc_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2csc_req_pvld) == 1'b1) begin + req_pd <= csb2csc_req_pd; +// VCS coverage off + end else if ((csb2csc_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2csc_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2csc_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + csc2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + csc2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csc2csb_resp_valid <= 1'b0; + end else begin + csc2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_atomics + or reg2dp_d0_atomics + ) begin + reg2dp_atomics = dp2reg_consumer ? reg2dp_d1_atomics : reg2dp_d0_atomics; +end +always @( + dp2reg_consumer + or reg2dp_d1_data_bank + or reg2dp_d0_data_bank + ) begin + reg2dp_data_bank = dp2reg_consumer ? reg2dp_d1_data_bank : reg2dp_d0_data_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bank + or reg2dp_d0_weight_bank + ) begin + reg2dp_weight_bank = dp2reg_consumer ? reg2dp_d1_weight_bank : reg2dp_d0_weight_bank; +end +always @( + dp2reg_consumer + or reg2dp_d1_batches + or reg2dp_d0_batches + ) begin + reg2dp_batches = dp2reg_consumer ? reg2dp_d1_batches : reg2dp_d0_batches; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_x_stride_ext + or reg2dp_d0_conv_x_stride_ext + ) begin + reg2dp_conv_x_stride_ext = dp2reg_consumer ? reg2dp_d1_conv_x_stride_ext : reg2dp_d0_conv_x_stride_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_y_stride_ext + or reg2dp_d0_conv_y_stride_ext + ) begin + reg2dp_conv_y_stride_ext = dp2reg_consumer ? reg2dp_d1_conv_y_stride_ext : reg2dp_d0_conv_y_stride_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_format + or reg2dp_d0_datain_format + ) begin + reg2dp_datain_format = dp2reg_consumer ? reg2dp_d1_datain_format : reg2dp_d0_datain_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height_ext + or reg2dp_d0_datain_height_ext + ) begin + reg2dp_datain_height_ext = dp2reg_consumer ? reg2dp_d1_datain_height_ext : reg2dp_d0_datain_height_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width_ext + or reg2dp_d0_datain_width_ext + ) begin + reg2dp_datain_width_ext = dp2reg_consumer ? reg2dp_d1_datain_width_ext : reg2dp_d0_datain_width_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_channel_ext + or reg2dp_d0_datain_channel_ext + ) begin + reg2dp_datain_channel_ext = dp2reg_consumer ? reg2dp_d1_datain_channel_ext : reg2dp_d0_datain_channel_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_height + or reg2dp_d0_dataout_height + ) begin + reg2dp_dataout_height = dp2reg_consumer ? reg2dp_d1_dataout_height : reg2dp_d0_dataout_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_width + or reg2dp_d0_dataout_width + ) begin + reg2dp_dataout_width = dp2reg_consumer ? reg2dp_d1_dataout_width : reg2dp_d0_dataout_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_channel + or reg2dp_d0_dataout_channel + ) begin + reg2dp_dataout_channel = dp2reg_consumer ? reg2dp_d1_dataout_channel : reg2dp_d0_dataout_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_x_dilation_ext + or reg2dp_d0_x_dilation_ext + ) begin + reg2dp_x_dilation_ext = dp2reg_consumer ? reg2dp_d1_x_dilation_ext : reg2dp_d0_x_dilation_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_y_dilation_ext + or reg2dp_d0_y_dilation_ext + ) begin + reg2dp_y_dilation_ext = dp2reg_consumer ? reg2dp_d1_y_dilation_ext : reg2dp_d0_y_dilation_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_entries + or reg2dp_d0_entries + ) begin + reg2dp_entries = dp2reg_consumer ? reg2dp_d1_entries : reg2dp_d0_entries; +end +always @( + dp2reg_consumer + or reg2dp_d1_conv_mode + or reg2dp_d0_conv_mode + ) begin + reg2dp_conv_mode = dp2reg_consumer ? reg2dp_d1_conv_mode : reg2dp_d0_conv_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_data_reuse + or reg2dp_d0_data_reuse + ) begin + reg2dp_data_reuse = dp2reg_consumer ? reg2dp_d1_data_reuse : reg2dp_d0_data_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_data_rls + or reg2dp_d0_skip_data_rls + ) begin + reg2dp_skip_data_rls = dp2reg_consumer ? reg2dp_d1_skip_data_rls : reg2dp_d0_skip_data_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_skip_weight_rls + or reg2dp_d0_skip_weight_rls + ) begin + reg2dp_skip_weight_rls = dp2reg_consumer ? reg2dp_d1_skip_weight_rls : reg2dp_d0_skip_weight_rls; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_reuse + or reg2dp_d0_weight_reuse + ) begin + reg2dp_weight_reuse = dp2reg_consumer ? reg2dp_d1_weight_reuse : reg2dp_d0_weight_reuse; +end +always @( + dp2reg_consumer + or reg2dp_d1_y_extension + or reg2dp_d0_y_extension + ) begin + reg2dp_y_extension = dp2reg_consumer ? reg2dp_d1_y_extension : reg2dp_d0_y_extension; +end +always @( + dp2reg_consumer + or reg2dp_d1_pra_truncate + or reg2dp_d0_pra_truncate + ) begin + reg2dp_pra_truncate = dp2reg_consumer ? reg2dp_d1_pra_truncate : reg2dp_d0_pra_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_rls_slices + or reg2dp_d0_rls_slices + ) begin + reg2dp_rls_slices = dp2reg_consumer ? reg2dp_d1_rls_slices : reg2dp_d0_rls_slices; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_bytes + or reg2dp_d0_weight_bytes + ) begin + reg2dp_weight_bytes = dp2reg_consumer ? reg2dp_d1_weight_bytes : reg2dp_d0_weight_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_format + or reg2dp_d0_weight_format + ) begin + reg2dp_weight_format = dp2reg_consumer ? reg2dp_d1_weight_format : reg2dp_d0_weight_format; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_height_ext + or reg2dp_d0_weight_height_ext + ) begin + reg2dp_weight_height_ext = dp2reg_consumer ? reg2dp_d1_weight_height_ext : reg2dp_d0_weight_height_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_width_ext + or reg2dp_d0_weight_width_ext + ) begin + reg2dp_weight_width_ext = dp2reg_consumer ? reg2dp_d1_weight_width_ext : reg2dp_d0_weight_width_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_channel_ext + or reg2dp_d0_weight_channel_ext + ) begin + reg2dp_weight_channel_ext = dp2reg_consumer ? reg2dp_d1_weight_channel_ext : reg2dp_d0_weight_channel_ext; +end +always @( + dp2reg_consumer + or reg2dp_d1_weight_kernel + or reg2dp_d0_weight_kernel + ) begin + reg2dp_weight_kernel = dp2reg_consumer ? reg2dp_d1_weight_kernel : reg2dp_d0_weight_kernel; +end +always @( + dp2reg_consumer + or reg2dp_d1_wmb_bytes + or reg2dp_d0_wmb_bytes + ) begin + reg2dp_wmb_bytes = dp2reg_consumer ? reg2dp_d1_wmb_bytes : reg2dp_d0_wmb_bytes; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_left + or reg2dp_d0_pad_left + ) begin + reg2dp_pad_left = dp2reg_consumer ? reg2dp_d1_pad_left : reg2dp_d0_pad_left; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_top + or reg2dp_d0_pad_top + ) begin + reg2dp_pad_top = dp2reg_consumer ? reg2dp_d1_pad_top : reg2dp_d0_pad_top; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value + or reg2dp_d0_pad_value + ) begin + reg2dp_pad_value = dp2reg_consumer ? reg2dp_d1_pad_value : reg2dp_d0_pad_value; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_CSC_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v new file mode 100644 index 0000000..fa78c95 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v @@ -0,0 +1,1658 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_sg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_CSC_sg ( + nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,accu2sc_credit_size //|< i + ,accu2sc_credit_vld //|< i + ,cdma2sc_dat_entries //|< i * + ,cdma2sc_dat_pending_ack //|< i + ,cdma2sc_dat_slices //|< i + ,cdma2sc_dat_updt //|< i + ,cdma2sc_wmb_entries //|< i * + ,cdma2sc_wt_entries //|< i * + ,cdma2sc_wt_kernels //|< i + ,cdma2sc_wt_pending_ack //|< i + ,cdma2sc_wt_updt //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_atomics //|< i + ,reg2dp_batches //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_data_reuse //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_datain_height_ext //|< i + ,reg2dp_dataout_height //|< i + ,reg2dp_dataout_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_rls_slices //|< i + ,reg2dp_skip_data_rls //|< i + ,reg2dp_skip_weight_rls //|< i + ,reg2dp_weight_bank //|< i + ,reg2dp_weight_channel_ext //|< i + ,reg2dp_weight_height_ext //|< i + ,reg2dp_weight_kernel //|< i + ,reg2dp_weight_reuse //|< i + ,reg2dp_weight_width_ext //|< i + ,reg2dp_y_extension //|< i + ,dp2reg_done //|> o + ,sc2cdma_dat_pending_req //|> o + ,sc2cdma_wt_pending_req //|> o + ,sc_state //|> o + ,sg2dl_pd //|> o + ,sg2dl_pvld //|> o + ,sg2dl_reuse_rls //|> o + ,sg2wl_pd //|> o + ,sg2wl_pvld //|> o + ,sg2wl_reuse_rls //|> o + ); +input nvdla_core_clk; /* done_dp2reg, dat_up_cdma2sc, wt_up_cdma2sc, sg2dl_pkg, sg2wl_pkg, accu2sc_credit, sc_state, sc2cdma_dat_pending, sc2cdma_wt_pending, cdma2sc_dat_pending, cdma2sc_wt_pending, sg2dl_reuse, sg2wl_reuse */ +input nvdla_core_rstn; /* done_dp2reg, dat_up_cdma2sc, wt_up_cdma2sc, sg2dl_pkg, sg2wl_pkg, accu2sc_credit, sc_state, sc2cdma_dat_pending, sc2cdma_wt_pending, cdma2sc_dat_pending, cdma2sc_wt_pending, sg2dl_reuse, sg2wl_reuse */ +input [31:0] pwrbus_ram_pd; +output dp2reg_done; +input cdma2sc_dat_updt; /* data valid */ +input [15 -1:0] cdma2sc_dat_entries; +input [13:0] cdma2sc_dat_slices; +input cdma2sc_wt_updt; /* data valid */ +input [13:0] cdma2sc_wt_kernels; +input [15 -1:0] cdma2sc_wt_entries; +input [8:0] cdma2sc_wmb_entries; +output sg2dl_pvld; /* data valid */ +output [30:0] sg2dl_pd; +output sg2wl_pvld; /* data valid */ +output [17:0] sg2wl_pd; +input accu2sc_credit_vld; /* data valid */ +input [2:0] accu2sc_credit_size; +output [1:0] sc_state; +output sc2cdma_dat_pending_req; //send sg pending to cdma +output sc2cdma_wt_pending_req; +input cdma2sc_dat_pending_ack; //cdma tould sg to clr pending +input cdma2sc_wt_pending_ack; +output sg2dl_reuse_rls; +output sg2wl_reuse_rls; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [0:0] reg2dp_weight_reuse; +input [0:0] reg2dp_skip_weight_rls; +input [4:0] reg2dp_batches; +input [0:0] reg2dp_datain_format; +input [12:0] reg2dp_datain_height_ext; +input [1:0] reg2dp_y_extension; +input [4:0] reg2dp_weight_width_ext; +input [4:0] reg2dp_weight_height_ext; +input [12:0] reg2dp_weight_channel_ext; +input [12:0] reg2dp_weight_kernel; +input [12:0] reg2dp_dataout_width; +input [12:0] reg2dp_dataout_height; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_weight_bank; +input [20:0] reg2dp_atomics; +input [11:0] reg2dp_rls_slices; +reg [6:0] batch_delta; +reg [13:0] channel_up_cnt; +reg [8:0] credit_cnt; +reg [2:0] credit_size; +reg credit_vld; +reg [1:0] cur_state; +reg dat_pending_ack; +reg dat_pending_clr; +reg dat_pending_req; +reg dat_pkg_block_end; +reg dat_pkg_channel_end; +reg [6:0] dat_pkg_channel_size; +reg [2:0] dat_pkg_cur_sub_h; +reg dat_pkg_dat_release; +reg dat_pkg_group_end; +reg [4:0] dat_pkg_h_offset; +reg dat_pkg_layer_end; +reg [6:0] dat_pkg_stripe_length; +reg [4:0] dat_pkg_w_offset; +wire [30:0] dat_pop_pd; +reg [6:0] dat_stripe_length; +reg [6:0] dat_stripe_size; +reg [5:0] data_batch; +reg [13:0] data_in_height; +reg [21:0] data_out_atomic; +reg [12:0] dataout_h_up_cnt; +reg [1:0] dbg_pre_prec; +reg dp2reg_done; +reg [7:0] flush_cycles; +reg [9:0] group_up_cnt; +reg is_img_d1; +reg [14:0] kernels_avl; +reg [4:0] last_data_bank; +reg [13:0] last_kernels; +reg [2:0] last_mode; +reg last_skip_weight_rls; +reg [13:0] last_slices; +reg [4:0] last_weight_bank; +reg layer_done; +reg [6:0] lower_limit; +reg [1:0] nxt_state; +reg [1:0] pkg_idx; +reg pkg_vld; +reg [5:0] pop_cnt; +reg [13:0] required_kernels; +reg [13:0] rls_slices; +reg [30:0] sg2dl_pd; +reg sg2dl_pvld; +reg sg2dl_reuse_rls; +reg [17:0] sg2wl_pd; +reg sg2wl_pvld; +reg sg2wl_reuse_rls; +reg [7:0] sg_dn_cnt; +reg [13:0] slice_left; +reg [13:0] slices_avl; +reg [21:0] stripe_up_cnt; +reg [6:0] upper_limit; +reg [13:0] weight_channel; +reg [9:0] weight_groups; +reg [4:0] weight_height_cmp; +reg [2:0] weight_r_add; +reg [2:0] weight_r_last; +reg [4:0] weight_r_up_cnt; +reg [4:0] weight_s_up_cnt; +reg [4:0] weight_width_cmp; +reg wt_pending_ack; +reg wt_pending_clr; +reg wt_pending_req; +reg [2:0] wt_pkg_cur_sub_h; +reg [6:0] wt_pkg_kernel_size; +reg [6:0] wt_pkg_weight_size; +reg wt_pkg_wt_release; +wire [17:0] wt_pop_pd; +reg wt_pop_ready_d1; +wire [7:0] c_fetch_size; +wire cbuf_ready; +wire [13:0] channel_up_cnt_inc; +wire [13:0] channel_up_cnt_w; +wire [3:0] credit_cnt_add; +wire [8:0] credit_cnt_dec; +wire [8:0] credit_cnt_w; +wire credit_ready; +wire [8:0] credit_req_size; +wire [6:0] cur_channel; +wire [6:0] cur_kernel; +wire [2:0] cur_mode; +wire [2:0] cur_r; +wire [6:0] cur_stripe; +wire [6:0] cur_stripe_inc; +wire dat_bank_change; +wire dat_cbuf_ready; +wire [8:0] dat_impact_cnt; +wire [6:0] dat_max_cycles; +wire dat_pending_clr_w; +wire dat_pending_req_w; +wire [30:0] dat_pkg_pd; +wire [32:0] dat_pop_data; +wire [1:0] dat_pop_idx; +wire dat_pop_ready; +wire dat_pop_req; +wire [32:0] dat_push_data; +wire dat_push_empty; +wire dat_push_ready; +wire dat_push_req; +wire dat_release; +wire dat_reuse_release; +wire [5:0] dat_stripe_batch_size_w; +wire [6:0] dat_stripe_img_length_w; +wire [6:0] dat_stripe_img_size_w; +wire [6:0] dat_stripe_length_w; +wire [6:0] dat_stripe_size_w; +wire [5:0] data_batch_w; +wire [13:0] data_in_height_w; +wire [21:0] data_out_atomic_w; +wire [12:0] dataout_h_up_cnt_w; +wire [1:0] dbg_cur_prec; +wire fifo_is_clear; +wire fifo_push_ready; +wire [7:0] flush_cycles_w; +wire [9:0] group_up_cnt_inc; +wire [9:0] group_up_cnt_w; +wire is_conv; +wire is_dc; +wire is_done; +wire is_idle; +wire is_img; +wire is_last_block; +wire is_last_channel; +wire is_last_do_h; +wire is_last_group; +wire is_last_r; +wire is_last_s; +wire is_last_stripe; +wire is_mode_change; +wire is_nxt_done; +wire is_nxt_pending; +wire is_pending; +wire is_pixel; +wire is_running; +wire is_stripe_be_2x; +wire is_stripe_le_1x; +wire [13:0] kernels_avl_add; +wire [13:0] kernels_avl_sub; +wire [14:0] kernels_avl_w; +wire layer_done_w; +wire layer_st; +wire [6:0] lower_limit_w; +wire [5:0] max_cycles; +wire mon_channel_up_cnt_inc; +wire mon_credit_cnt_w; +wire [15:0] mon_cur_stripe_inc; +wire [5:0] mon_dat_stripe_batch_size_w; +wire mon_dat_stripe_img_length_w; +wire mon_dataout_h_up_cnt_w; +wire mon_group_up_cnt_inc; +wire [0:0] mon_kernels_avl_w; +wire [1:0] mon_max_cycles; +wire mon_pkg_idx_w; +wire mon_pop_cnt_dec; +wire mon_required_kernels_inc; +wire mon_rls_slices_w; +wire mon_sg2wt_kernel_size_inc; +wire mon_sg_dn_cnt_w; +wire [1:0] mon_slice_left_w; +wire [1:0] mon_slices_avl_w; +wire mon_stripe_up_cnt_2x_inc; +wire mon_stripe_up_cnt_1x_inc; +wire mon_stripe_up_cnt_w; +wire [2:0] mon_weight_r_add_w; +wire mon_weight_s_up_cnt_inc; +wire need_pending; +wire op_channel_en; +wire op_do_h_en; +wire op_group_en; +wire op_layer_en; +wire op_r_en; +wire op_s_en; +wire op_stripe_en; +wire pending_done; +wire pkg_adv; +wire pkg_block_end_w; +wire pkg_channel_end_w; +wire pkg_group_end_w; +wire [1:0] pkg_idx_w; +wire pkg_layer_end_w; +wire pkg_vld_w; +wire [6:0] pkg_weight_size_w; +wire [5:0] pop_cnt_dec; +wire [5:0] pop_cnt_w; +wire [13:0] required_kernels_inc; +wire [13:0] required_kernels_w; +wire [13:0] rls_slices_w; +wire [1:0] sc_state; +wire sg2dat_block_end; +wire sg2dat_channel_end; +wire [6:0] sg2dat_channel_size; +wire [1:0] sg2dat_cur_sub_h; +wire sg2dat_dat_release; +wire sg2dat_group_end; +wire [4:0] sg2dat_h_offset; +wire sg2dat_layer_end; +wire [6:0] sg2dat_stripe_length; +wire [4:0] sg2dat_w_offset; +wire sg2wt_channel_end; +wire [1:0] sg2wt_cur_sub_h; +wire sg2wt_group_end; +wire [5:0] sg2wt_kernel_size; +wire [5:0] sg2wt_kernel_size_inc; +wire [6:0] sg2wt_weight_size; +wire sg2wt_wt_release; +wire [7:0] sg_dn_cnt_w; +wire [13:0] slice_left_w; +wire [13:0] slices_avl_add; +wire [13:0] slices_avl_sub; +wire [13:0] slices_avl_w; +wire [6:0] stripe_length_w; +wire [21:0] stripe_up_cnt_2x_inc; +wire [21:0] stripe_up_cnt_1x_inc; +wire [21:0] stripe_up_cnt_w; +wire [6:0] upper_limit_w; +wire [13:0] weight_channel_w; +wire [9:0] weight_groups_w; +wire [4:0] weight_height_cmp_w; +wire [2:0] weight_r_add_w; +wire [2:0] weight_r_last_w; +wire [5:0] weight_r_up_cnt_inc; +wire [4:0] weight_r_up_cnt_w; +wire [4:0] weight_s_up_cnt_inc; +wire [4:0] weight_s_up_cnt_w; +wire [4:0] weight_width_cmp_w; +wire wt_bank_change; +wire wt_cbuf_ready; +wire [4:0] wt_cycles; +wire [5:0] wt_max_cycles; +wire wt_pending_clr_w; +wire wt_pending_req_w; +wire wt_pkg_channel_end; +wire wt_pkg_group_end; +wire [17:0] wt_pkg_pd; +wire [19:0] wt_pop_data; +wire [1:0] wt_pop_idx; +wire wt_pop_ready; +wire wt_pop_req; +wire [19:0] wt_push_data; +wire wt_push_empty; +wire wt_push_ready; +wire wt_push_req; +wire wt_release; +wire wt_reuse_release; +//////////////////////////////////////////////////////////////////////// +// CSC control FSM // +//////////////////////////////////////////////////////////////////////// +localparam SG_STATE_IDLE = 2'b00; +localparam SG_STATE_PEND = 2'b01; +localparam SG_STATE_BUSY = 2'b10; +localparam SG_STATE_DONE = 2'b11; +//## fsm (1) com block +always @ (*) begin + nxt_state = cur_state; + begin + casez (cur_state) + SG_STATE_IDLE: begin + if ((reg2dp_op_en & need_pending)) begin + nxt_state = SG_STATE_PEND; + end + else if (reg2dp_op_en) begin + nxt_state = SG_STATE_BUSY; + end + end + SG_STATE_PEND: begin + if (pending_done) begin + nxt_state = SG_STATE_BUSY; + end + end + SG_STATE_BUSY: begin + if (layer_done & fifo_is_clear & ~pkg_vld) begin + nxt_state = SG_STATE_DONE; + end + end + SG_STATE_DONE: begin + if (dp2reg_done) begin + nxt_state = SG_STATE_IDLE; + end + end + endcase + end +end +//: &eperl::flop("-nodeclare -rval \"SG_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_state <= SG_STATE_IDLE; + end else begin + cur_state <= nxt_state; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign fifo_is_clear = ~dat_pop_req & ~wt_pop_req & dat_push_empty & wt_push_empty; +assign dat_bank_change = (last_data_bank != reg2dp_data_bank); +assign wt_bank_change = (last_weight_bank != reg2dp_weight_bank); +assign need_pending = (dat_bank_change | wt_bank_change); +assign pending_done = is_pending & (dat_pending_clr ~^ dat_pending_req) & (wt_pending_clr ~^ wt_pending_req); +assign flush_cycles_w = dat_stripe_size + 6'h30 ; +assign {mon_sg_dn_cnt_w, sg_dn_cnt_w} = (~is_done & is_nxt_done) ? {1'b0, flush_cycles} : sg_dn_cnt - 1'b1; +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"is_nxt_done\" -d \"sg_dn_cnt_w\" -q sg_dn_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cdma2sc_dat_pending_ack\" -q dat_pending_ack"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cdma2sc_wt_pending_ack\" -q wt_pending_ack"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"dat_pop_req & dat_pop_ready & sg2dat_layer_end\" -d \"flush_cycles_w\" -q flush_cycles"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg_dn_cnt <= {8{1'b0}}; + end else begin + if ((is_nxt_done) == 1'b1) begin + sg_dn_cnt <= sg_dn_cnt_w; + // VCS coverage off + end else if ((is_nxt_done) == 1'b0) begin + end else begin + sg_dn_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pending_ack <= 1'b0; + end else begin + dat_pending_ack <= cdma2sc_dat_pending_ack; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pending_ack <= 1'b0; + end else begin + wt_pending_ack <= cdma2sc_wt_pending_ack; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + flush_cycles <= {8{1'b0}}; + end else begin + if ((dat_pop_req & dat_pop_ready & sg2dat_layer_end) == 1'b1) begin + flush_cycles <= flush_cycles_w; + // VCS coverage off + end else if ((dat_pop_req & dat_pop_ready & sg2dat_layer_end) == 1'b0) begin + end else begin + flush_cycles <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en && (cur_state == SG_STATE_IDLE); +assign is_idle = (cur_state == SG_STATE_IDLE); +assign is_pending = (cur_state == SG_STATE_PEND); +assign is_running = (cur_state == SG_STATE_BUSY); +assign is_done = (cur_state == SG_STATE_DONE); +assign is_nxt_done = (nxt_state == SG_STATE_DONE); +assign is_nxt_pending = (nxt_state == SG_STATE_PEND); +assign sc_state = is_idle ? 0 : is_pending ? 1 : is_running ? 2 : 3 ; +assign dat_pending_req_w= (is_nxt_pending & dat_bank_change) ? 1'b1 : (~is_nxt_pending) ? 1'b0 : dat_pending_req; +assign wt_pending_req_w = (is_nxt_pending) ? 1'b1 : (~is_nxt_pending) ? 1'b0 : wt_pending_req; +assign is_mode_change = (last_mode != cur_mode); +assign dat_pending_clr_w= (is_pending & dat_pending_ack) ? 1'b1 : ~is_nxt_pending ? 1'b0 : dat_pending_clr; +assign wt_pending_clr_w = (is_pending & wt_pending_ack) ? 1'b1 : ~is_nxt_pending ? 1'b0 : wt_pending_clr; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_done && (sg_dn_cnt == 6'b1)\" -q dp2reg_done"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pending_req_w\" -q dat_pending_req"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pending_req_w\" -q wt_pending_req"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pending_clr_w\" -q dat_pending_clr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pending_clr_w\" -q wt_pending_clr"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_done <= 1'b0; + end else begin + dp2reg_done <= is_done && (sg_dn_cnt == 6'b1); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pending_req <= 1'b0; + end else begin + dat_pending_req <= dat_pending_req_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pending_req <= 1'b0; + end else begin + wt_pending_req <= wt_pending_req_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pending_clr <= 1'b0; + end else begin + dat_pending_clr <= dat_pending_clr_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pending_clr <= 1'b0; + end else begin + wt_pending_clr <= wt_pending_clr_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// sg send pending status to cdma +assign sc2cdma_dat_pending_req = dat_pending_req; +assign sc2cdma_wt_pending_req = wt_pending_req; +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"dp2reg_done\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"dp2reg_done\" -d \"reg2dp_weight_bank\" -q last_weight_bank"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dp2reg_done\" -d \"slice_left\" -q last_slices"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dp2reg_done\" -d \"reg2dp_weight_kernel + 1'b1\" -q last_kernels"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dp2reg_done\" -d \"reg2dp_skip_weight_rls\" -q last_skip_weight_rls"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"dp2reg_done\" -d \"cur_mode\" -q last_mode"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_data_bank <= {5{1'b1}}; + end else begin + if ((dp2reg_done) == 1'b1) begin + last_data_bank <= reg2dp_data_bank; + // VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + last_data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_weight_bank <= {5{1'b1}}; + end else begin + if ((dp2reg_done) == 1'b1) begin + last_weight_bank <= reg2dp_weight_bank; + // VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + last_weight_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_slices <= {14{1'b0}}; + end else begin + if ((dp2reg_done) == 1'b1) begin + last_slices <= slice_left; + // VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + last_slices <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_kernels <= {14{1'b0}}; + end else begin + if ((dp2reg_done) == 1'b1) begin + last_kernels <= reg2dp_weight_kernel + 1'b1; + // VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + last_kernels <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_skip_weight_rls <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + last_skip_weight_rls <= reg2dp_skip_weight_rls; + // VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + last_skip_weight_rls <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_mode <= {3{1'b0}}; + end else begin + if ((dp2reg_done) == 1'b1) begin + last_mode <= cur_mode; + // VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + last_mode <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +//assign is_int8 = (reg2dp_proc_precision == 2'h0 ); +assign is_pixel = (reg2dp_datain_format == 1'h1 ); +assign is_conv = (reg2dp_conv_mode == 1'h0 ); +assign is_dc = is_conv & ~is_pixel; +assign cur_mode = {is_img, 1'b0, is_dc}; +assign data_out_atomic_w = is_img ? reg2dp_dataout_width + 1'b1 : reg2dp_atomics + 1'b1; +assign weight_width_cmp_w = (is_img) ? 5'b0 : reg2dp_weight_width_ext; +assign weight_height_cmp_w = reg2dp_weight_height_ext; +assign is_img = is_conv & is_pixel; +assign data_in_height_w = reg2dp_datain_height_ext + 1'b1; +assign weight_channel_w = reg2dp_weight_channel_ext + 1'b1; +assign weight_groups_w = reg2dp_weight_kernel[12:3] + 1'b1; +assign {weight_r_add_w, mon_weight_r_add_w} = (6'h9 << reg2dp_y_extension); +assign weight_r_last_w = weight_r_add_w[0] ? 2'b0 : + weight_r_add_w[1] ? {1'b0, reg2dp_weight_height_ext[0]} : + reg2dp_weight_height_ext[1:0]; +assign {mon_rls_slices_w, rls_slices_w} = reg2dp_rls_slices + 1'b1; +assign {mon_slice_left_w, slice_left_w} = reg2dp_skip_data_rls ? (reg2dp_datain_height_ext + 1'b1) : reg2dp_datain_height_ext - reg2dp_rls_slices; +//In opensource, DC batching only support fully connected layer. In this case stripe operation length is always 1 +//upper_limit = 2*lower_limit or upper_limit = lower_limit +assign lower_limit_w = is_img ? 7'h10 : + 7'h8; +assign upper_limit_w = is_img ? 7'h10 : + 7'h10; +assign c_fetch_size = 8'h08 ; +assign data_batch_w = 6'b0; +//: my $kk="\"7'h8\""; +//: my $jj="\"7'h10\""; +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_in_height_w\" -q data_in_height"); +//: &eperl::flop("-nodeclare -rval \"{22{1'b0}}\" -en \"layer_st\" -d \"data_out_atomic_w\" -q data_out_atomic"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"data_batch_w\" -q data_batch"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"weight_width_cmp_w\" -q weight_width_cmp"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"weight_height_cmp_w\" -q weight_height_cmp"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"weight_channel_w\" -q weight_channel"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st\" -d \"weight_groups_w\" -q weight_groups"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"weight_r_add_w\" -q weight_r_add"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"weight_r_last_w\" -q weight_r_last"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"rls_slices_w\" -q rls_slices"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"slice_left_w\" -q slice_left"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"is_img\" -q is_img_d1"); +//: &eperl::flop("-nodeclare -rval ${kk} -en \"layer_st\" -d \"lower_limit_w\" -q lower_limit"); +//: &eperl::flop("-nodeclare -rval ${jj} -en \"layer_st\" -d \"upper_limit_w\" -q upper_limit"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_in_height <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_in_height <= data_in_height_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_in_height <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_out_atomic <= {22{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_out_atomic <= data_out_atomic_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_out_atomic <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_batch <= {6{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_batch <= data_batch_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_batch <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_width_cmp <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_width_cmp <= weight_width_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_width_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_height_cmp <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_height_cmp <= weight_height_cmp_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_height_cmp <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_channel <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_channel <= weight_channel_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_channel <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_groups <= {10{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_groups <= weight_groups_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_groups <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_r_add <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + weight_r_add <= weight_r_add_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_r_add <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_r_last <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + weight_r_last <= weight_r_last_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_r_last <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rls_slices <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + rls_slices <= rls_slices_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + rls_slices <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slice_left <= {14{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + slice_left <= slice_left_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + slice_left <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_img_d1 <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + is_img_d1 <= is_img; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + is_img_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lower_limit <= 7'h8; + end else begin + if ((layer_st) == 1'b1) begin + lower_limit <= lower_limit_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + lower_limit <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + upper_limit <= 7'h10; + end else begin + if ((layer_st) == 1'b1) begin + upper_limit <= upper_limit_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + upper_limit <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// sequence generator for direct convolution // +//////////////////////////////////////////////////////////////////////// +//---------------------------layer count -----------------------------// +assign layer_done_w = layer_st ? 1'b0 : is_last_group ? 1'b1 : layer_done; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st | op_layer_en\" -d \"layer_done_w\" -q layer_done"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_done <= 1'b0; + end else begin + if ((layer_st | op_layer_en) == 1'b1) begin + layer_done <= layer_done_w; + // VCS coverage off + end else if ((layer_st | op_layer_en) == 1'b0) begin + end else begin + layer_done <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//---------------------------kernel group count -----------------------------// +assign {mon_group_up_cnt_inc, group_up_cnt_inc} = group_up_cnt + 1'b1; +assign is_last_group = (group_up_cnt_inc == weight_groups); +assign group_up_cnt_w = layer_st ? 10'b0 : group_up_cnt_inc; +assign cur_kernel = ~is_last_group ? 7'h8 : (reg2dp_weight_kernel[3 -1:0] + 1'b1) ; +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st | op_group_en\" -d \"group_up_cnt_w\" -q group_up_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + group_up_cnt <= {10{1'b0}}; + end else begin + if ((layer_st | op_group_en) == 1'b1) begin + group_up_cnt <= group_up_cnt_w; + // VCS coverage off + end else if ((layer_st | op_group_en) == 1'b0) begin + end else begin + group_up_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- output height count, for image case only -----------------------------// +assign is_last_do_h = ~is_img_d1 | (dataout_h_up_cnt == reg2dp_dataout_height); +assign {mon_dataout_h_up_cnt_w, dataout_h_up_cnt_w} = layer_st ? 14'b0 : + is_last_do_h ? 14'b0 : + (dataout_h_up_cnt + 1'b1); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st | op_do_h_en\" -d \"dataout_h_up_cnt_w\" -q dataout_h_up_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dataout_h_up_cnt <= {13{1'b0}}; + end else begin + if ((layer_st | op_do_h_en) == 1'b1) begin + dataout_h_up_cnt <= dataout_h_up_cnt_w; + // VCS coverage off + end else if ((layer_st | op_do_h_en) == 1'b0) begin + end else begin + dataout_h_up_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- output stripe count -----------------------------// +assign {mon_stripe_up_cnt_2x_inc, stripe_up_cnt_2x_inc} = stripe_up_cnt + {upper_limit, 1'b0}; +assign {mon_stripe_up_cnt_1x_inc, stripe_up_cnt_1x_inc} = stripe_up_cnt + upper_limit; +assign is_stripe_be_2x = (stripe_up_cnt_2x_inc <= data_out_atomic); +assign is_stripe_le_1x = (stripe_up_cnt_1x_inc >= data_out_atomic); +assign is_last_stripe = is_stripe_le_1x; +assign {mon_stripe_up_cnt_w, stripe_up_cnt_w} = layer_st ? 23'b0 : + is_last_stripe ? 23'b0 : + is_stripe_be_2x ? (stripe_up_cnt + upper_limit) : + (stripe_up_cnt + lower_limit); +assign {mon_cur_stripe_inc[15:0], cur_stripe_inc[6:0]} = data_out_atomic - stripe_up_cnt; +assign cur_stripe = is_stripe_be_2x ? upper_limit : is_stripe_le_1x ? cur_stripe_inc : lower_limit; +//: &eperl::flop("-nodeclare -rval \"{22{1'b0}}\" -en \"layer_st | op_stripe_en\" -d \"stripe_up_cnt_w\" -q stripe_up_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stripe_up_cnt <= {22{1'b0}}; + end else begin + if ((layer_st | op_stripe_en) == 1'b1) begin + stripe_up_cnt <= stripe_up_cnt_w; + // VCS coverage off + end else if ((layer_st | op_stripe_en) == 1'b0) begin + end else begin + stripe_up_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- channel count -----------------------------// +assign {mon_channel_up_cnt_inc, channel_up_cnt_inc} = channel_up_cnt + c_fetch_size[6:0]; +assign is_last_channel = (channel_up_cnt_inc >= weight_channel); +assign channel_up_cnt_w = layer_st ? 14'b0 : is_last_channel ? 14'b0 : channel_up_cnt_inc; +assign cur_channel = (~is_last_channel) ? c_fetch_size[6:0] : (reg2dp_weight_channel_ext[3 -1:0] + 1'b1); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st | op_channel_en\" -d \"channel_up_cnt_w\" -q channel_up_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_up_cnt <= {14{1'b0}}; + end else begin + if ((layer_st | op_channel_en) == 1'b1) begin + channel_up_cnt <= channel_up_cnt_w; + // VCS coverage off + end else if ((layer_st | op_channel_en) == 1'b0) begin + end else begin + channel_up_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- weight block count -----------------------------// +assign {mon_weight_s_up_cnt_inc, weight_s_up_cnt_inc} = weight_s_up_cnt + 1'b1; +assign weight_r_up_cnt_inc = weight_r_up_cnt + weight_r_add; +assign is_last_s = (weight_s_up_cnt == weight_width_cmp); +assign is_last_r = (weight_r_up_cnt_inc > {1'b0, weight_height_cmp}); +assign cur_r = is_last_r ? weight_r_last : + weight_r_add[2] ? 2'h3 : + weight_r_add[1] ? 2'h1 : + 2'h0; +assign is_last_block = is_last_s & is_last_r; +assign weight_s_up_cnt_w = layer_st ? 5'b0 : (is_last_s) ? 5'b0 : weight_s_up_cnt_inc; +assign weight_r_up_cnt_w = layer_st ? 5'b0 : (is_last_r) ? 5'b0 : weight_r_up_cnt_inc[4:0]; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st | op_s_en\" -d \"weight_s_up_cnt_w\" -q weight_s_up_cnt"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st | op_r_en\" -d \"weight_r_up_cnt_w\" -q weight_r_up_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_s_up_cnt <= {5{1'b0}}; + end else begin + if ((layer_st | op_s_en) == 1'b1) begin + weight_s_up_cnt <= weight_s_up_cnt_w; + // VCS coverage off + end else if ((layer_st | op_s_en) == 1'b0) begin + end else begin + weight_s_up_cnt <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_r_up_cnt <= {5{1'b0}}; + end else begin + if ((layer_st | op_r_en) == 1'b1) begin + weight_r_up_cnt <= weight_r_up_cnt_w; + // VCS coverage off + end else if ((layer_st | op_r_en) == 1'b0) begin + end else begin + weight_r_up_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- cbuf check logic -----------------------------// +assign dat_cbuf_ready = (slices_avl >= data_in_height[13:0]); +assign {mon_required_kernels_inc, required_kernels_inc} = required_kernels + cur_kernel; +assign required_kernels_w = (layer_st | is_last_group | ~reg2dp_skip_weight_rls) ? 14'b0 : required_kernels_inc; +assign wt_cbuf_ready = ({1'b0, required_kernels_inc} <= kernels_avl); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st | op_group_en\" -d \"required_kernels_w\" -q required_kernels"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + required_kernels <= {14{1'b0}}; + end else begin + if ((layer_st | op_group_en) == 1'b1) begin + required_kernels <= required_kernels_w; + // VCS coverage off + end else if ((layer_st | op_group_en) == 1'b0) begin + end else begin + required_kernels <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- register enable signal -----------------------------// +assign fifo_push_ready = dat_push_ready & wt_push_ready; +assign cbuf_ready = dat_cbuf_ready & wt_cbuf_ready; +assign pkg_adv = is_running & cbuf_ready & ~layer_done & (~pkg_vld | fifo_push_ready); +assign op_s_en = pkg_adv; +assign op_r_en = pkg_adv & is_last_s; +assign op_channel_en = pkg_adv & is_last_block; +assign op_stripe_en = pkg_adv & is_last_block & is_last_channel; +assign op_do_h_en = is_img_d1 & pkg_adv & is_last_block & is_last_channel & is_last_stripe; +assign op_group_en = pkg_adv & is_last_block & is_last_channel & is_last_stripe & is_last_do_h; +assign op_layer_en = pkg_adv & is_last_block & is_last_channel & is_last_stripe & is_last_do_h & is_last_group; +assign pkg_vld_w = ~is_running ? 1'b0 : + (cbuf_ready & ~layer_done) ? 1'b1 : + fifo_push_ready ? 1'b0 : + pkg_vld; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pkg_vld_w\" -q pkg_vld"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pkg_vld <= 1'b0; + end else begin + pkg_vld <= pkg_vld_w; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//--------------------------- package registers -----------------------------// +assign {mon_pkg_idx_w, pkg_idx_w} = layer_st ? 2'h3 : (pkg_idx + 2'b1); +assign pkg_weight_size_w = cur_channel; +assign stripe_length_w = cur_stripe; +assign pkg_block_end_w = is_last_block; +assign pkg_channel_end_w = is_last_block & is_last_channel; +assign pkg_group_end_w = is_last_block & is_last_channel & is_last_stripe & is_last_do_h; +assign pkg_layer_end_w = is_last_block & is_last_channel & is_last_stripe & is_last_do_h & is_last_group; +//: &eperl::flop("-nodeclare -rval \"{2{1'b1}}\" -en \"layer_st | pkg_adv\" -d \"pkg_idx_w\" -q pkg_idx"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"pkg_adv\" -d \"weight_s_up_cnt\" -q dat_pkg_w_offset"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"pkg_adv\" -d \"weight_r_up_cnt\" -q dat_pkg_h_offset"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"cur_channel\" -q dat_pkg_channel_size"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"stripe_length_w\" -q dat_pkg_stripe_length"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pkg_adv\" -d \"cur_r\" -q dat_pkg_cur_sub_h"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_block_end_w\" -q dat_pkg_block_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_channel_end_w\" -q dat_pkg_channel_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_group_end_w\" -q dat_pkg_group_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_layer_end_w\" -q dat_pkg_layer_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"~reg2dp_skip_data_rls & pkg_layer_end_w\" -q dat_pkg_dat_release"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pkg_idx <= {2{1'b1}}; + end else begin + if ((layer_st | pkg_adv) == 1'b1) begin + pkg_idx <= pkg_idx_w; + // VCS coverage off + end else if ((layer_st | pkg_adv) == 1'b0) begin + end else begin + pkg_idx <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_w_offset <= {5{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_w_offset <= weight_s_up_cnt; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_w_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_h_offset <= {5{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_h_offset <= weight_r_up_cnt; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_h_offset <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_channel_size <= {7{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_channel_size <= cur_channel; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_channel_size <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_stripe_length <= {7{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_stripe_length <= stripe_length_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_stripe_length <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_cur_sub_h <= {3{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_cur_sub_h <= cur_r; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_cur_sub_h <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_block_end <= 1'b0; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_block_end <= pkg_block_end_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_block_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_channel_end <= 1'b0; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_channel_end <= pkg_channel_end_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_channel_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_group_end <= 1'b0; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_group_end <= pkg_group_end_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_group_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_layer_end <= 1'b0; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_layer_end <= pkg_layer_end_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_layer_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_pkg_dat_release <= 1'b0; + end else begin + if ((pkg_adv) == 1'b1) begin + dat_pkg_dat_release <= ~reg2dp_skip_data_rls & pkg_layer_end_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + dat_pkg_dat_release <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// PKT_PACK_WIRE( csc_dat_pkg , dat_pkg_ , dat_pkg_pd ) +assign dat_pkg_pd[4:0] = dat_pkg_w_offset[4:0]; +assign dat_pkg_pd[9:5] = dat_pkg_h_offset[4:0]; +assign dat_pkg_pd[16:10] = dat_pkg_channel_size[6:0]; +assign dat_pkg_pd[23:17] = dat_pkg_stripe_length[6:0]; +assign dat_pkg_pd[25:24] = dat_pkg_cur_sub_h[1:0]; +assign dat_pkg_pd[26] = dat_pkg_block_end ; +assign dat_pkg_pd[27] = dat_pkg_channel_end ; +assign dat_pkg_pd[28] = dat_pkg_group_end ; +assign dat_pkg_pd[29] = dat_pkg_layer_end ; +assign dat_pkg_pd[30] = dat_pkg_dat_release ; +assign dat_push_data = {pkg_idx, dat_pkg_pd}; +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"cur_kernel\" -q wt_pkg_kernel_size"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"pkg_weight_size_w\" -q wt_pkg_weight_size"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pkg_adv\" -d \"cur_r\" -q wt_pkg_cur_sub_h"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"~reg2dp_skip_weight_rls & pkg_group_end_w\" -q wt_pkg_wt_release"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pkg_kernel_size <= {7{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + wt_pkg_kernel_size <= cur_kernel; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + wt_pkg_kernel_size <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pkg_weight_size <= {7{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + wt_pkg_weight_size <= pkg_weight_size_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + wt_pkg_weight_size <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pkg_cur_sub_h <= {3{1'b0}}; + end else begin + if ((pkg_adv) == 1'b1) begin + wt_pkg_cur_sub_h <= cur_r; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + wt_pkg_cur_sub_h <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pkg_wt_release <= 1'b0; + end else begin + if ((pkg_adv) == 1'b1) begin + wt_pkg_wt_release <= ~reg2dp_skip_weight_rls & pkg_group_end_w; + // VCS coverage off + end else if ((pkg_adv) == 1'b0) begin + end else begin + wt_pkg_wt_release <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wt_pkg_channel_end = dat_pkg_channel_end; +assign wt_pkg_group_end = dat_pkg_group_end; +// PKT_PACK_WIRE( csc_wt_pkg , wt_pkg_ , wt_pkg_pd ) +assign wt_pkg_pd[6:0] = wt_pkg_weight_size[6:0]; +assign wt_pkg_pd[12:7] = wt_pkg_kernel_size[5:0]; +assign wt_pkg_pd[14:13] = wt_pkg_cur_sub_h[1:0]; +assign wt_pkg_pd[15] = wt_pkg_channel_end ; +assign wt_pkg_pd[16] = wt_pkg_group_end ; +assign wt_pkg_pd[17] = wt_pkg_wt_release ; +assign wt_push_data = {pkg_idx, wt_pkg_pd}; +//////////////////////////////////////////////////////////////////////// +// package fifos // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_CSC_SG_dat_fifo u_dat_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dat_push_ready) //|> w + ,.wr_empty (dat_push_empty) //|> w + ,.wr_req (dat_push_req) //|< r + ,.wr_data (dat_push_data[32:0]) //|< r + ,.rd_ready (dat_pop_ready) //|< r + ,.rd_req (dat_pop_req) //|> w + ,.rd_data (dat_pop_data[32:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_CSC_SG_wt_fifo u_wt_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (wt_push_ready) //|> w + ,.wr_empty (wt_push_empty) //|> w + ,.wr_req (wt_push_req) //|< r + ,.wr_data (wt_push_data[19:0]) //|< r + ,.rd_ready (wt_pop_ready) //|< r + ,.rd_req (wt_pop_req) //|> w + ,.rd_data (wt_pop_data[19:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dat_push_req = pkg_vld & wt_push_ready; +assign wt_push_req = pkg_vld & dat_push_ready; +//////////////////////////////////////////////////////////////////////// +// issue control logic // +//////////////////////////////////////////////////////////////////////// +assign {dat_pop_idx, dat_pop_pd} = dat_pop_data; +assign {wt_pop_idx, wt_pop_pd} = wt_pop_data; +// PKT_UNPACK_WIRE( csc_dat_pkg , sg2dat_ , dat_pop_pd ) +assign sg2dat_w_offset[4:0] = dat_pop_pd[4:0]; +assign sg2dat_h_offset[4:0] = dat_pop_pd[9:5]; +assign sg2dat_channel_size[6:0] = dat_pop_pd[16:10]; +assign sg2dat_stripe_length[6:0] = dat_pop_pd[23:17]; +assign sg2dat_cur_sub_h[1:0] = dat_pop_pd[25:24]; +assign sg2dat_block_end = dat_pop_pd[26]; +assign sg2dat_channel_end = dat_pop_pd[27]; +assign sg2dat_group_end = dat_pop_pd[28]; +assign sg2dat_layer_end = dat_pop_pd[29]; +assign sg2dat_dat_release = dat_pop_pd[30]; +// PKT_UNPACK_WIRE( csc_wt_pkg , sg2wt_ , wt_pop_pd ) +assign sg2wt_weight_size[6:0] = wt_pop_pd[6:0]; +assign sg2wt_kernel_size[5:0] = wt_pop_pd[12:7]; +assign sg2wt_cur_sub_h[1:0] = wt_pop_pd[14:13]; +assign sg2wt_channel_end = wt_pop_pd[15]; +assign sg2wt_group_end = wt_pop_pd[16]; +assign sg2wt_wt_release = wt_pop_pd[17]; +assign {mon_sg2wt_kernel_size_inc, sg2wt_kernel_size_inc} = sg2wt_kernel_size + 1'b1; +assign {mon_dat_stripe_batch_size_w[0], dat_stripe_batch_size_w} = sg2dat_stripe_length; +assign dat_stripe_img_size_w = sg2dat_stripe_length; +assign dat_stripe_size_w = is_img_d1 ? dat_stripe_img_size_w : {1'b0, dat_stripe_batch_size_w}; +assign {mon_dat_stripe_img_length_w, + dat_stripe_img_length_w} = ~is_img_d1 ? 8'b0 : + (reg2dp_y_extension == 2'h2) ? ((sg2dat_stripe_length + 2'h3) & 8'hfc) : + (reg2dp_y_extension == 2'h1) ? ((sg2dat_stripe_length + 2'h1) & 8'hfe) : + {1'b0, sg2dat_stripe_length}; +assign dat_stripe_length_w = is_img_d1 ? dat_stripe_img_length_w : {1'b0, dat_stripe_batch_size_w}; +//delay for one cycle +assign dat_max_cycles = ~dat_pop_ready ? 7'b0 : + (dat_stripe_length < 7'd8 ) ? 7'd8 : + dat_stripe_length; +assign wt_cycles = sg2wt_kernel_size[4:0]; +assign wt_max_cycles = ~wt_pop_ready ? 6'b0 : + ((wt_cycles <= 5'b1) & (pop_cnt <= 6'b1)) ? 6'h2 : + ({1'b0, wt_cycles} > pop_cnt) ? {1'b0, wt_cycles} : + pop_cnt; +assign {mon_max_cycles, max_cycles} = (dat_max_cycles >= {1'b0, wt_max_cycles}) ? (dat_max_cycles - 1'b1) : ({1'b0, wt_max_cycles} - 1'b1); +assign {mon_pop_cnt_dec, pop_cnt_dec} = pop_cnt - 1'b1; +assign pop_cnt_w = (dat_pop_ready | wt_pop_ready) ? max_cycles : (pop_cnt == 6'h0) ? 6'h0 : pop_cnt_dec; +assign wt_pop_ready = wt_pop_req & (((pop_cnt == 6'b0) & credit_ready) | (dat_pop_idx == wt_pop_idx)); +assign dat_pop_ready = dat_pop_req & (pop_cnt == 6'b0) & credit_ready & ((dat_pop_idx != wt_pop_idx) | ~wt_pop_req); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pop_ready\" -q wt_pop_ready_d1"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_pop_ready_d1\" -d \"dat_stripe_size_w\" -q dat_stripe_size"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_pop_ready_d1\" -d \"dat_stripe_length_w\" -q dat_stripe_length"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -d \"pop_cnt_w\" -q pop_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pop_ready\" -q sg2dl_pvld"); +//: &eperl::flop("-nodeclare -rval \"{31{1'b0}}\" -en \"dat_pop_ready\" -d \"dat_pop_pd\" -q sg2dl_pd"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pop_ready\" -q sg2wl_pvld"); +//: &eperl::flop("-nodeclare -rval \"{18{1'b0}}\" -en \"wt_pop_ready\" -d \"wt_pop_pd\" -q sg2wl_pd"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_pop_ready_d1 <= 1'b0; + end else begin + wt_pop_ready_d1 <= wt_pop_ready; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_stripe_size <= {7{1'b0}}; + end else begin + if ((wt_pop_ready_d1) == 1'b1) begin + dat_stripe_size <= dat_stripe_size_w; + // VCS coverage off + end else if ((wt_pop_ready_d1) == 1'b0) begin + end else begin + dat_stripe_size <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_stripe_length <= {7{1'b0}}; + end else begin + if ((wt_pop_ready_d1) == 1'b1) begin + dat_stripe_length <= dat_stripe_length_w; + // VCS coverage off + end else if ((wt_pop_ready_d1) == 1'b0) begin + end else begin + dat_stripe_length <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pop_cnt <= {6{1'b0}}; + end else begin + pop_cnt <= pop_cnt_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg2dl_pvld <= 1'b0; + end else begin + sg2dl_pvld <= dat_pop_ready; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg2dl_pd <= {31{1'b0}}; + end else begin + if ((dat_pop_ready) == 1'b1) begin + sg2dl_pd <= dat_pop_pd; + // VCS coverage off + end else if ((dat_pop_ready) == 1'b0) begin + end else begin + sg2dl_pd <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg2wl_pvld <= 1'b0; + end else begin + sg2wl_pvld <= wt_pop_ready; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg2wl_pd <= {18{1'b0}}; + end else begin + if ((wt_pop_ready) == 1'b1) begin + sg2wl_pd <= wt_pop_pd; + // VCS coverage off + end else if ((wt_pop_ready) == 1'b0) begin + end else begin + sg2wl_pd <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////////////////////////////////////////// +// credit controll logic // +//////////////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +//flop credit signal because it cross partition boundary +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"accu2sc_credit_vld\" -q credit_vld"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -norst -en \"accu2sc_credit_vld\" -d \"accu2sc_credit_size\" -q credit_size"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + credit_vld <= 1'b0; + end else begin + credit_vld <= accu2sc_credit_vld; + end +end +always @(posedge nvdla_core_ng_clk) begin + if ((accu2sc_credit_vld) == 1'b1) begin + credit_size <= accu2sc_credit_size; + // VCS coverage off + end else if ((accu2sc_credit_vld) == 1'b0) begin + end else begin + credit_size <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dat_impact_cnt = {2'b0, dat_stripe_size}; +assign credit_req_size = dat_impact_cnt; +assign credit_cnt_add = credit_vld ? credit_size : 4'b0; +assign credit_cnt_dec = (dat_pop_ready & sg2dat_channel_end) ? dat_impact_cnt : 9'b0; +assign {mon_credit_cnt_w, credit_cnt_w} = credit_cnt + credit_cnt_add - credit_cnt_dec; +assign credit_ready = ~sg2dat_channel_end | (credit_cnt >= credit_req_size); +//: my $credit_size = 8*2; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval $credit_size -en \"dat_pop_ready | credit_vld\" -d \"credit_cnt_w\" -q credit_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + credit_cnt <= 16; + end else begin + if ((dat_pop_ready | credit_vld) == 1'b1) begin + credit_cnt <= credit_cnt_w; + // VCS coverage off + end else if ((dat_pop_ready | credit_vld) == 1'b0) begin + end else begin + credit_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// convolution buffer local status // +//////////////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +assign dat_release = pkg_adv & pkg_layer_end_w & ~reg2dp_skip_data_rls; +assign dat_reuse_release = is_idle & reg2dp_op_en & (~reg2dp_data_reuse | is_mode_change) & (|last_slices); +assign slices_avl_add = cdma2sc_dat_updt ? cdma2sc_dat_slices : 14'b0; +assign slices_avl_sub = dat_release ? rls_slices : dat_reuse_release ? last_slices[13:0] : 14'b0; +assign {mon_slices_avl_w, slices_avl_w} = (dat_pending_req) ? 14'b0 : (slices_avl + slices_avl_add - slices_avl_sub); +assign wt_release = pkg_adv & ~reg2dp_skip_weight_rls & pkg_group_end_w; +assign wt_reuse_release = is_idle & reg2dp_op_en & ~reg2dp_weight_reuse & last_skip_weight_rls; +assign kernels_avl_add = cdma2sc_wt_updt ? cdma2sc_wt_kernels : 14'b0; +assign kernels_avl_sub = wt_release ? {{7{1'b0}}, cur_kernel} : wt_reuse_release ? last_kernels[13:0] : 14'b0; +assign {mon_kernels_avl_w, kernels_avl_w} = (wt_pending_req) ? 15'b0 : kernels_avl + kernels_avl_add - kernels_avl_sub; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{14{1'b0}}\" -en \"dat_pending_req | dat_release | dat_reuse_release | cdma2sc_dat_updt\" -d \"slices_avl_w\" -q slices_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{15{1'b0}}\" -en \"wt_pending_req | wt_release | wt_reuse_release | cdma2sc_wt_updt\" -d \"kernels_avl_w\" -q kernels_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"dat_reuse_release\" -q sg2dl_reuse_rls"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"wt_reuse_release\" -q sg2wl_reuse_rls"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slices_avl <= {14{1'b0}}; + end else begin + if ((dat_pending_req | dat_release | dat_reuse_release | cdma2sc_dat_updt) == 1'b1) begin + slices_avl <= slices_avl_w; + // VCS coverage off + end else if ((dat_pending_req | dat_release | dat_reuse_release | cdma2sc_dat_updt) == 1'b0) begin + end else begin + slices_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + kernels_avl <= {15{1'b0}}; + end else begin + if ((wt_pending_req | wt_release | wt_reuse_release | cdma2sc_wt_updt) == 1'b1) begin + kernels_avl <= kernels_avl_w; + // VCS coverage off + end else if ((wt_pending_req | wt_release | wt_reuse_release | cdma2sc_wt_updt) == 1'b0) begin + end else begin + kernels_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg2dl_reuse_rls <= 1'b0; + end else begin + sg2dl_reuse_rls <= dat_reuse_release; + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sg2wl_reuse_rls <= 1'b0; + end else begin + sg2wl_reuse_rls <= wt_reuse_release; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//================ Non-SLCG clock domain end ================// +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +assign dbg_cur_prec = reg2dp_proc_precision; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_pre_prec <= {2{1'b1}}; + end else begin + dbg_pre_prec <= reg2dp_proc_precision; + end +end +endmodule // NV_NVDLA_CSC_sg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v.vcp new file mode 100644 index 0000000..1259825 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v.vcp @@ -0,0 +1,751 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_sg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_CSC_sg ( + nvdla_core_clk //|< i + ,nvdla_core_ng_clk //|< i + ,nvdla_core_rstn //|< i + ,accu2sc_credit_size //|< i + ,accu2sc_credit_vld //|< i + ,cdma2sc_dat_entries //|< i * + ,cdma2sc_dat_pending_ack //|< i + ,cdma2sc_dat_slices //|< i + ,cdma2sc_dat_updt //|< i + ,cdma2sc_wmb_entries //|< i * + ,cdma2sc_wt_entries //|< i * + ,cdma2sc_wt_kernels //|< i + ,cdma2sc_wt_pending_ack //|< i + ,cdma2sc_wt_updt //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_atomics //|< i + ,reg2dp_batches //|< i + ,reg2dp_conv_mode //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_data_reuse //|< i + ,reg2dp_datain_format //|< i + ,reg2dp_datain_height_ext //|< i + ,reg2dp_dataout_height //|< i + ,reg2dp_dataout_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_rls_slices //|< i + ,reg2dp_skip_data_rls //|< i + ,reg2dp_skip_weight_rls //|< i + ,reg2dp_weight_bank //|< i + ,reg2dp_weight_channel_ext //|< i + ,reg2dp_weight_height_ext //|< i + ,reg2dp_weight_kernel //|< i + ,reg2dp_weight_reuse //|< i + ,reg2dp_weight_width_ext //|< i + ,reg2dp_y_extension //|< i + ,dp2reg_done //|> o + ,sc2cdma_dat_pending_req //|> o + ,sc2cdma_wt_pending_req //|> o + ,sc_state //|> o + ,sg2dl_pd //|> o + ,sg2dl_pvld //|> o + ,sg2dl_reuse_rls //|> o + ,sg2wl_pd //|> o + ,sg2wl_pvld //|> o + ,sg2wl_reuse_rls //|> o + ); +input nvdla_core_clk; /* done_dp2reg, dat_up_cdma2sc, wt_up_cdma2sc, sg2dl_pkg, sg2wl_pkg, accu2sc_credit, sc_state, sc2cdma_dat_pending, sc2cdma_wt_pending, cdma2sc_dat_pending, cdma2sc_wt_pending, sg2dl_reuse, sg2wl_reuse */ +input nvdla_core_rstn; /* done_dp2reg, dat_up_cdma2sc, wt_up_cdma2sc, sg2dl_pkg, sg2wl_pkg, accu2sc_credit, sc_state, sc2cdma_dat_pending, sc2cdma_wt_pending, cdma2sc_dat_pending, cdma2sc_wt_pending, sg2dl_reuse, sg2wl_reuse */ +input [31:0] pwrbus_ram_pd; +output dp2reg_done; +input cdma2sc_dat_updt; /* data valid */ +input [15 -1:0] cdma2sc_dat_entries; +input [13:0] cdma2sc_dat_slices; +input cdma2sc_wt_updt; /* data valid */ +input [13:0] cdma2sc_wt_kernels; +input [15 -1:0] cdma2sc_wt_entries; +input [8:0] cdma2sc_wmb_entries; +output sg2dl_pvld; /* data valid */ +output [30:0] sg2dl_pd; +output sg2wl_pvld; /* data valid */ +output [17:0] sg2wl_pd; +input accu2sc_credit_vld; /* data valid */ +input [2:0] accu2sc_credit_size; +output [1:0] sc_state; +output sc2cdma_dat_pending_req; //send sg pending to cdma +output sc2cdma_wt_pending_req; +input cdma2sc_dat_pending_ack; //cdma tould sg to clr pending +input cdma2sc_wt_pending_ack; +output sg2dl_reuse_rls; +output sg2wl_reuse_rls; +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [0:0] reg2dp_conv_mode; +input [1:0] reg2dp_proc_precision; +input [0:0] reg2dp_data_reuse; +input [0:0] reg2dp_skip_data_rls; +input [0:0] reg2dp_weight_reuse; +input [0:0] reg2dp_skip_weight_rls; +input [4:0] reg2dp_batches; +input [0:0] reg2dp_datain_format; +input [12:0] reg2dp_datain_height_ext; +input [1:0] reg2dp_y_extension; +input [4:0] reg2dp_weight_width_ext; +input [4:0] reg2dp_weight_height_ext; +input [12:0] reg2dp_weight_channel_ext; +input [12:0] reg2dp_weight_kernel; +input [12:0] reg2dp_dataout_width; +input [12:0] reg2dp_dataout_height; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_weight_bank; +input [20:0] reg2dp_atomics; +input [11:0] reg2dp_rls_slices; +reg [6:0] batch_delta; +reg [13:0] channel_up_cnt; +reg [8:0] credit_cnt; +reg [2:0] credit_size; +reg credit_vld; +reg [1:0] cur_state; +reg dat_pending_ack; +reg dat_pending_clr; +reg dat_pending_req; +reg dat_pkg_block_end; +reg dat_pkg_channel_end; +reg [6:0] dat_pkg_channel_size; +reg [2:0] dat_pkg_cur_sub_h; +reg dat_pkg_dat_release; +reg dat_pkg_group_end; +reg [4:0] dat_pkg_h_offset; +reg dat_pkg_layer_end; +reg [6:0] dat_pkg_stripe_length; +reg [4:0] dat_pkg_w_offset; +wire [30:0] dat_pop_pd; +reg [6:0] dat_stripe_length; +reg [6:0] dat_stripe_size; +reg [5:0] data_batch; +reg [13:0] data_in_height; +reg [21:0] data_out_atomic; +reg [12:0] dataout_h_up_cnt; +reg [1:0] dbg_pre_prec; +reg dp2reg_done; +reg [7:0] flush_cycles; +reg [9:0] group_up_cnt; +reg is_img_d1; +reg [14:0] kernels_avl; +reg [4:0] last_data_bank; +reg [13:0] last_kernels; +reg [2:0] last_mode; +reg last_skip_weight_rls; +reg [13:0] last_slices; +reg [4:0] last_weight_bank; +reg layer_done; +reg [6:0] lower_limit; +reg [1:0] nxt_state; +reg [1:0] pkg_idx; +reg pkg_vld; +reg [5:0] pop_cnt; +reg [13:0] required_kernels; +reg [13:0] rls_slices; +reg [30:0] sg2dl_pd; +reg sg2dl_pvld; +reg sg2dl_reuse_rls; +reg [17:0] sg2wl_pd; +reg sg2wl_pvld; +reg sg2wl_reuse_rls; +reg [7:0] sg_dn_cnt; +reg [13:0] slice_left; +reg [13:0] slices_avl; +reg [21:0] stripe_up_cnt; +reg [6:0] upper_limit; +reg [13:0] weight_channel; +reg [9:0] weight_groups; +reg [4:0] weight_height_cmp; +reg [2:0] weight_r_add; +reg [2:0] weight_r_last; +reg [4:0] weight_r_up_cnt; +reg [4:0] weight_s_up_cnt; +reg [4:0] weight_width_cmp; +reg wt_pending_ack; +reg wt_pending_clr; +reg wt_pending_req; +reg [2:0] wt_pkg_cur_sub_h; +reg [6:0] wt_pkg_kernel_size; +reg [6:0] wt_pkg_weight_size; +reg wt_pkg_wt_release; +wire [17:0] wt_pop_pd; +reg wt_pop_ready_d1; +wire [7:0] c_fetch_size; +wire cbuf_ready; +wire [13:0] channel_up_cnt_inc; +wire [13:0] channel_up_cnt_w; +wire [3:0] credit_cnt_add; +wire [8:0] credit_cnt_dec; +wire [8:0] credit_cnt_w; +wire credit_ready; +wire [8:0] credit_req_size; +wire [6:0] cur_channel; +wire [6:0] cur_kernel; +wire [2:0] cur_mode; +wire [2:0] cur_r; +wire [6:0] cur_stripe; +wire [6:0] cur_stripe_inc; +wire dat_bank_change; +wire dat_cbuf_ready; +wire [8:0] dat_impact_cnt; +wire [6:0] dat_max_cycles; +wire dat_pending_clr_w; +wire dat_pending_req_w; +wire [30:0] dat_pkg_pd; +wire [32:0] dat_pop_data; +wire [1:0] dat_pop_idx; +wire dat_pop_ready; +wire dat_pop_req; +wire [32:0] dat_push_data; +wire dat_push_empty; +wire dat_push_ready; +wire dat_push_req; +wire dat_release; +wire dat_reuse_release; +wire [5:0] dat_stripe_batch_size_w; +wire [6:0] dat_stripe_img_length_w; +wire [6:0] dat_stripe_img_size_w; +wire [6:0] dat_stripe_length_w; +wire [6:0] dat_stripe_size_w; +wire [5:0] data_batch_w; +wire [13:0] data_in_height_w; +wire [21:0] data_out_atomic_w; +wire [12:0] dataout_h_up_cnt_w; +wire [1:0] dbg_cur_prec; +wire fifo_is_clear; +wire fifo_push_ready; +wire [7:0] flush_cycles_w; +wire [9:0] group_up_cnt_inc; +wire [9:0] group_up_cnt_w; +wire is_conv; +wire is_dc; +wire is_done; +wire is_idle; +wire is_img; +wire is_last_block; +wire is_last_channel; +wire is_last_do_h; +wire is_last_group; +wire is_last_r; +wire is_last_s; +wire is_last_stripe; +wire is_mode_change; +wire is_nxt_done; +wire is_nxt_pending; +wire is_pending; +wire is_pixel; +wire is_running; +wire is_stripe_be_2x; +wire is_stripe_le_1x; +wire [13:0] kernels_avl_add; +wire [13:0] kernels_avl_sub; +wire [14:0] kernels_avl_w; +wire layer_done_w; +wire layer_st; +wire [6:0] lower_limit_w; +wire [5:0] max_cycles; +wire mon_channel_up_cnt_inc; +wire mon_credit_cnt_w; +wire [15:0] mon_cur_stripe_inc; +wire [5:0] mon_dat_stripe_batch_size_w; +wire mon_dat_stripe_img_length_w; +wire mon_dataout_h_up_cnt_w; +wire mon_group_up_cnt_inc; +wire [0:0] mon_kernels_avl_w; +wire [1:0] mon_max_cycles; +wire mon_pkg_idx_w; +wire mon_pop_cnt_dec; +wire mon_required_kernels_inc; +wire mon_rls_slices_w; +wire mon_sg2wt_kernel_size_inc; +wire mon_sg_dn_cnt_w; +wire [1:0] mon_slice_left_w; +wire [1:0] mon_slices_avl_w; +wire mon_stripe_up_cnt_2x_inc; +wire mon_stripe_up_cnt_1x_inc; +wire mon_stripe_up_cnt_w; +wire [2:0] mon_weight_r_add_w; +wire mon_weight_s_up_cnt_inc; +wire need_pending; +wire op_channel_en; +wire op_do_h_en; +wire op_group_en; +wire op_layer_en; +wire op_r_en; +wire op_s_en; +wire op_stripe_en; +wire pending_done; +wire pkg_adv; +wire pkg_block_end_w; +wire pkg_channel_end_w; +wire pkg_group_end_w; +wire [1:0] pkg_idx_w; +wire pkg_layer_end_w; +wire pkg_vld_w; +wire [6:0] pkg_weight_size_w; +wire [5:0] pop_cnt_dec; +wire [5:0] pop_cnt_w; +wire [13:0] required_kernels_inc; +wire [13:0] required_kernels_w; +wire [13:0] rls_slices_w; +wire [1:0] sc_state; +wire sg2dat_block_end; +wire sg2dat_channel_end; +wire [6:0] sg2dat_channel_size; +wire [1:0] sg2dat_cur_sub_h; +wire sg2dat_dat_release; +wire sg2dat_group_end; +wire [4:0] sg2dat_h_offset; +wire sg2dat_layer_end; +wire [6:0] sg2dat_stripe_length; +wire [4:0] sg2dat_w_offset; +wire sg2wt_channel_end; +wire [1:0] sg2wt_cur_sub_h; +wire sg2wt_group_end; +wire [5:0] sg2wt_kernel_size; +wire [5:0] sg2wt_kernel_size_inc; +wire [6:0] sg2wt_weight_size; +wire sg2wt_wt_release; +wire [7:0] sg_dn_cnt_w; +wire [13:0] slice_left_w; +wire [13:0] slices_avl_add; +wire [13:0] slices_avl_sub; +wire [13:0] slices_avl_w; +wire [6:0] stripe_length_w; +wire [21:0] stripe_up_cnt_2x_inc; +wire [21:0] stripe_up_cnt_1x_inc; +wire [21:0] stripe_up_cnt_w; +wire [6:0] upper_limit_w; +wire [13:0] weight_channel_w; +wire [9:0] weight_groups_w; +wire [4:0] weight_height_cmp_w; +wire [2:0] weight_r_add_w; +wire [2:0] weight_r_last_w; +wire [5:0] weight_r_up_cnt_inc; +wire [4:0] weight_r_up_cnt_w; +wire [4:0] weight_s_up_cnt_inc; +wire [4:0] weight_s_up_cnt_w; +wire [4:0] weight_width_cmp_w; +wire wt_bank_change; +wire wt_cbuf_ready; +wire [4:0] wt_cycles; +wire [5:0] wt_max_cycles; +wire wt_pending_clr_w; +wire wt_pending_req_w; +wire wt_pkg_channel_end; +wire wt_pkg_group_end; +wire [17:0] wt_pkg_pd; +wire [19:0] wt_pop_data; +wire [1:0] wt_pop_idx; +wire wt_pop_ready; +wire wt_pop_req; +wire [19:0] wt_push_data; +wire wt_push_empty; +wire wt_push_ready; +wire wt_push_req; +wire wt_release; +wire wt_reuse_release; +//////////////////////////////////////////////////////////////////////// +// CSC control FSM // +//////////////////////////////////////////////////////////////////////// +localparam SG_STATE_IDLE = 2'b00; +localparam SG_STATE_PEND = 2'b01; +localparam SG_STATE_BUSY = 2'b10; +localparam SG_STATE_DONE = 2'b11; +//## fsm (1) com block +always @ (*) begin + nxt_state = cur_state; + begin + casez (cur_state) + SG_STATE_IDLE: begin + if ((reg2dp_op_en & need_pending)) begin + nxt_state = SG_STATE_PEND; + end + else if (reg2dp_op_en) begin + nxt_state = SG_STATE_BUSY; + end + end + SG_STATE_PEND: begin + if (pending_done) begin + nxt_state = SG_STATE_BUSY; + end + end + SG_STATE_BUSY: begin + if (layer_done & fifo_is_clear & ~pkg_vld) begin + nxt_state = SG_STATE_DONE; + end + end + SG_STATE_DONE: begin + if (dp2reg_done) begin + nxt_state = SG_STATE_IDLE; + end + end + endcase + end +end +//: &eperl::flop("-nodeclare -rval \"SG_STATE_IDLE\" -d \"nxt_state\" -q cur_state"); +//////////////////////////////////////////////////////////////////////// +// FSM input signals // +//////////////////////////////////////////////////////////////////////// +assign fifo_is_clear = ~dat_pop_req & ~wt_pop_req & dat_push_empty & wt_push_empty; +assign dat_bank_change = (last_data_bank != reg2dp_data_bank); +assign wt_bank_change = (last_weight_bank != reg2dp_weight_bank); +assign need_pending = (dat_bank_change | wt_bank_change); +assign pending_done = is_pending & (dat_pending_clr ~^ dat_pending_req) & (wt_pending_clr ~^ wt_pending_req); +assign flush_cycles_w = dat_stripe_size + 6'h30 ; +assign {mon_sg_dn_cnt_w, sg_dn_cnt_w} = (~is_done & is_nxt_done) ? {1'b0, flush_cycles} : sg_dn_cnt - 1'b1; +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"is_nxt_done\" -d \"sg_dn_cnt_w\" -q sg_dn_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cdma2sc_dat_pending_ack\" -q dat_pending_ack"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"cdma2sc_wt_pending_ack\" -q wt_pending_ack"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"dat_pop_req & dat_pop_ready & sg2dat_layer_end\" -d \"flush_cycles_w\" -q flush_cycles"); +//////////////////////////////////////////////////////////////////////// +// FSM output signals // +//////////////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en && (cur_state == SG_STATE_IDLE); +assign is_idle = (cur_state == SG_STATE_IDLE); +assign is_pending = (cur_state == SG_STATE_PEND); +assign is_running = (cur_state == SG_STATE_BUSY); +assign is_done = (cur_state == SG_STATE_DONE); +assign is_nxt_done = (nxt_state == SG_STATE_DONE); +assign is_nxt_pending = (nxt_state == SG_STATE_PEND); +assign sc_state = is_idle ? 0 : is_pending ? 1 : is_running ? 2 : 3 ; +assign dat_pending_req_w= (is_nxt_pending & dat_bank_change) ? 1'b1 : (~is_nxt_pending) ? 1'b0 : dat_pending_req; +assign wt_pending_req_w = (is_nxt_pending) ? 1'b1 : (~is_nxt_pending) ? 1'b0 : wt_pending_req; +assign is_mode_change = (last_mode != cur_mode); +assign dat_pending_clr_w= (is_pending & dat_pending_ack) ? 1'b1 : ~is_nxt_pending ? 1'b0 : dat_pending_clr; +assign wt_pending_clr_w = (is_pending & wt_pending_ack) ? 1'b1 : ~is_nxt_pending ? 1'b0 : wt_pending_clr; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_done && (sg_dn_cnt == 6'b1)\" -q dp2reg_done"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pending_req_w\" -q dat_pending_req"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pending_req_w\" -q wt_pending_req"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pending_clr_w\" -q dat_pending_clr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pending_clr_w\" -q wt_pending_clr"); +// sg send pending status to cdma +assign sc2cdma_dat_pending_req = dat_pending_req; +assign sc2cdma_wt_pending_req = wt_pending_req; +//////////////////////////////////////////////////////////////////////// +// registers to keep last layer status // +//////////////////////////////////////////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"dp2reg_done\" -d \"reg2dp_data_bank\" -q last_data_bank"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b1}}\" -en \"dp2reg_done\" -d \"reg2dp_weight_bank\" -q last_weight_bank"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dp2reg_done\" -d \"slice_left\" -q last_slices"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"dp2reg_done\" -d \"reg2dp_weight_kernel + 1'b1\" -q last_kernels"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"dp2reg_done\" -d \"reg2dp_skip_weight_rls\" -q last_skip_weight_rls"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"dp2reg_done\" -d \"cur_mode\" -q last_mode"); +//////////////////////////////////////////////////////////////////////// +// registers to calculate local values // +//////////////////////////////////////////////////////////////////////// +//assign is_int8 = (reg2dp_proc_precision == 2'h0 ); +assign is_pixel = (reg2dp_datain_format == 1'h1 ); +assign is_conv = (reg2dp_conv_mode == 1'h0 ); +assign is_dc = is_conv & ~is_pixel; +assign cur_mode = {is_img, 1'b0, is_dc}; +assign data_out_atomic_w = is_img ? reg2dp_dataout_width + 1'b1 : reg2dp_atomics + 1'b1; +assign weight_width_cmp_w = (is_img) ? 5'b0 : reg2dp_weight_width_ext; +assign weight_height_cmp_w = reg2dp_weight_height_ext; +assign is_img = is_conv & is_pixel; +assign data_in_height_w = reg2dp_datain_height_ext + 1'b1; +assign weight_channel_w = reg2dp_weight_channel_ext + 1'b1; +assign weight_groups_w = reg2dp_weight_kernel[12:3] + 1'b1; +assign {weight_r_add_w, mon_weight_r_add_w} = (6'h9 << reg2dp_y_extension); +assign weight_r_last_w = weight_r_add_w[0] ? 2'b0 : + weight_r_add_w[1] ? {1'b0, reg2dp_weight_height_ext[0]} : + reg2dp_weight_height_ext[1:0]; +assign {mon_rls_slices_w, rls_slices_w} = reg2dp_rls_slices + 1'b1; +assign {mon_slice_left_w, slice_left_w} = reg2dp_skip_data_rls ? (reg2dp_datain_height_ext + 1'b1) : reg2dp_datain_height_ext - reg2dp_rls_slices; +//In opensource, DC batching only support fully connected layer. In this case stripe operation length is always 1 +//upper_limit = 2*lower_limit or upper_limit = lower_limit +assign lower_limit_w = is_img ? 7'h10 : + 7'h8; +assign upper_limit_w = is_img ? 7'h10 : + 7'h10; +assign c_fetch_size = 8'h08 ; +assign data_batch_w = 6'b0; +//: my $kk="\"7'h8\""; +//: my $jj="\"7'h10\""; +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"data_in_height_w\" -q data_in_height"); +//: &eperl::flop("-nodeclare -rval \"{22{1'b0}}\" -en \"layer_st\" -d \"data_out_atomic_w\" -q data_out_atomic"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -en \"layer_st\" -d \"data_batch_w\" -q data_batch"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"weight_width_cmp_w\" -q weight_width_cmp"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"weight_height_cmp_w\" -q weight_height_cmp"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"weight_channel_w\" -q weight_channel"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st\" -d \"weight_groups_w\" -q weight_groups"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"weight_r_add_w\" -q weight_r_add"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"weight_r_last_w\" -q weight_r_last"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"rls_slices_w\" -q rls_slices"); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st\" -d \"slice_left_w\" -q slice_left"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"is_img\" -q is_img_d1"); +//: &eperl::flop("-nodeclare -rval ${kk} -en \"layer_st\" -d \"lower_limit_w\" -q lower_limit"); +//: &eperl::flop("-nodeclare -rval ${jj} -en \"layer_st\" -d \"upper_limit_w\" -q upper_limit"); +//////////////////////////////////////////////////////////////////////// +// sequence generator for direct convolution // +//////////////////////////////////////////////////////////////////////// +//---------------------------layer count -----------------------------// +assign layer_done_w = layer_st ? 1'b0 : is_last_group ? 1'b1 : layer_done; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st | op_layer_en\" -d \"layer_done_w\" -q layer_done"); +//---------------------------kernel group count -----------------------------// +assign {mon_group_up_cnt_inc, group_up_cnt_inc} = group_up_cnt + 1'b1; +assign is_last_group = (group_up_cnt_inc == weight_groups); +assign group_up_cnt_w = layer_st ? 10'b0 : group_up_cnt_inc; +assign cur_kernel = ~is_last_group ? 7'h8 : (reg2dp_weight_kernel[3 -1:0] + 1'b1) ; +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st | op_group_en\" -d \"group_up_cnt_w\" -q group_up_cnt"); +//--------------------------- output height count, for image case only -----------------------------// +assign is_last_do_h = ~is_img_d1 | (dataout_h_up_cnt == reg2dp_dataout_height); +assign {mon_dataout_h_up_cnt_w, dataout_h_up_cnt_w} = layer_st ? 14'b0 : + is_last_do_h ? 14'b0 : + (dataout_h_up_cnt + 1'b1); +//: &eperl::flop("-nodeclare -rval \"{13{1'b0}}\" -en \"layer_st | op_do_h_en\" -d \"dataout_h_up_cnt_w\" -q dataout_h_up_cnt"); +//--------------------------- output stripe count -----------------------------// +assign {mon_stripe_up_cnt_2x_inc, stripe_up_cnt_2x_inc} = stripe_up_cnt + {upper_limit, 1'b0}; +assign {mon_stripe_up_cnt_1x_inc, stripe_up_cnt_1x_inc} = stripe_up_cnt + upper_limit; +assign is_stripe_be_2x = (stripe_up_cnt_2x_inc <= data_out_atomic); +assign is_stripe_le_1x = (stripe_up_cnt_1x_inc >= data_out_atomic); +assign is_last_stripe = is_stripe_le_1x; +assign {mon_stripe_up_cnt_w, stripe_up_cnt_w} = layer_st ? 23'b0 : + is_last_stripe ? 23'b0 : + is_stripe_be_2x ? (stripe_up_cnt + upper_limit) : + (stripe_up_cnt + lower_limit); +assign {mon_cur_stripe_inc[15:0], cur_stripe_inc[6:0]} = data_out_atomic - stripe_up_cnt; +assign cur_stripe = is_stripe_be_2x ? upper_limit : is_stripe_le_1x ? cur_stripe_inc : lower_limit; +//: &eperl::flop("-nodeclare -rval \"{22{1'b0}}\" -en \"layer_st | op_stripe_en\" -d \"stripe_up_cnt_w\" -q stripe_up_cnt"); +//--------------------------- channel count -----------------------------// +assign {mon_channel_up_cnt_inc, channel_up_cnt_inc} = channel_up_cnt + c_fetch_size[6:0]; +assign is_last_channel = (channel_up_cnt_inc >= weight_channel); +assign channel_up_cnt_w = layer_st ? 14'b0 : is_last_channel ? 14'b0 : channel_up_cnt_inc; +assign cur_channel = (~is_last_channel) ? c_fetch_size[6:0] : (reg2dp_weight_channel_ext[3 -1:0] + 1'b1); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st | op_channel_en\" -d \"channel_up_cnt_w\" -q channel_up_cnt"); +//--------------------------- weight block count -----------------------------// +assign {mon_weight_s_up_cnt_inc, weight_s_up_cnt_inc} = weight_s_up_cnt + 1'b1; +assign weight_r_up_cnt_inc = weight_r_up_cnt + weight_r_add; +assign is_last_s = (weight_s_up_cnt == weight_width_cmp); +assign is_last_r = (weight_r_up_cnt_inc > {1'b0, weight_height_cmp}); +assign cur_r = is_last_r ? weight_r_last : + weight_r_add[2] ? 2'h3 : + weight_r_add[1] ? 2'h1 : + 2'h0; +assign is_last_block = is_last_s & is_last_r; +assign weight_s_up_cnt_w = layer_st ? 5'b0 : (is_last_s) ? 5'b0 : weight_s_up_cnt_inc; +assign weight_r_up_cnt_w = layer_st ? 5'b0 : (is_last_r) ? 5'b0 : weight_r_up_cnt_inc[4:0]; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st | op_s_en\" -d \"weight_s_up_cnt_w\" -q weight_s_up_cnt"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st | op_r_en\" -d \"weight_r_up_cnt_w\" -q weight_r_up_cnt"); +//--------------------------- cbuf check logic -----------------------------// +assign dat_cbuf_ready = (slices_avl >= data_in_height[13:0]); +assign {mon_required_kernels_inc, required_kernels_inc} = required_kernels + cur_kernel; +assign required_kernels_w = (layer_st | is_last_group | ~reg2dp_skip_weight_rls) ? 14'b0 : required_kernels_inc; +assign wt_cbuf_ready = ({1'b0, required_kernels_inc} <= kernels_avl); +//: &eperl::flop("-nodeclare -rval \"{14{1'b0}}\" -en \"layer_st | op_group_en\" -d \"required_kernels_w\" -q required_kernels"); +//--------------------------- register enable signal -----------------------------// +assign fifo_push_ready = dat_push_ready & wt_push_ready; +assign cbuf_ready = dat_cbuf_ready & wt_cbuf_ready; +assign pkg_adv = is_running & cbuf_ready & ~layer_done & (~pkg_vld | fifo_push_ready); +assign op_s_en = pkg_adv; +assign op_r_en = pkg_adv & is_last_s; +assign op_channel_en = pkg_adv & is_last_block; +assign op_stripe_en = pkg_adv & is_last_block & is_last_channel; +assign op_do_h_en = is_img_d1 & pkg_adv & is_last_block & is_last_channel & is_last_stripe; +assign op_group_en = pkg_adv & is_last_block & is_last_channel & is_last_stripe & is_last_do_h; +assign op_layer_en = pkg_adv & is_last_block & is_last_channel & is_last_stripe & is_last_do_h & is_last_group; +assign pkg_vld_w = ~is_running ? 1'b0 : + (cbuf_ready & ~layer_done) ? 1'b1 : + fifo_push_ready ? 1'b0 : + pkg_vld; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"pkg_vld_w\" -q pkg_vld"); +//--------------------------- package registers -----------------------------// +assign {mon_pkg_idx_w, pkg_idx_w} = layer_st ? 2'h3 : (pkg_idx + 2'b1); +assign pkg_weight_size_w = cur_channel; +assign stripe_length_w = cur_stripe; +assign pkg_block_end_w = is_last_block; +assign pkg_channel_end_w = is_last_block & is_last_channel; +assign pkg_group_end_w = is_last_block & is_last_channel & is_last_stripe & is_last_do_h; +assign pkg_layer_end_w = is_last_block & is_last_channel & is_last_stripe & is_last_do_h & is_last_group; +//: &eperl::flop("-nodeclare -rval \"{2{1'b1}}\" -en \"layer_st | pkg_adv\" -d \"pkg_idx_w\" -q pkg_idx"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"pkg_adv\" -d \"weight_s_up_cnt\" -q dat_pkg_w_offset"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"pkg_adv\" -d \"weight_r_up_cnt\" -q dat_pkg_h_offset"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"cur_channel\" -q dat_pkg_channel_size"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"stripe_length_w\" -q dat_pkg_stripe_length"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pkg_adv\" -d \"cur_r\" -q dat_pkg_cur_sub_h"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_block_end_w\" -q dat_pkg_block_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_channel_end_w\" -q dat_pkg_channel_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_group_end_w\" -q dat_pkg_group_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"pkg_layer_end_w\" -q dat_pkg_layer_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"~reg2dp_skip_data_rls & pkg_layer_end_w\" -q dat_pkg_dat_release"); +// PKT_PACK_WIRE( csc_dat_pkg , dat_pkg_ , dat_pkg_pd ) +assign dat_pkg_pd[4:0] = dat_pkg_w_offset[4:0]; +assign dat_pkg_pd[9:5] = dat_pkg_h_offset[4:0]; +assign dat_pkg_pd[16:10] = dat_pkg_channel_size[6:0]; +assign dat_pkg_pd[23:17] = dat_pkg_stripe_length[6:0]; +assign dat_pkg_pd[25:24] = dat_pkg_cur_sub_h[1:0]; +assign dat_pkg_pd[26] = dat_pkg_block_end ; +assign dat_pkg_pd[27] = dat_pkg_channel_end ; +assign dat_pkg_pd[28] = dat_pkg_group_end ; +assign dat_pkg_pd[29] = dat_pkg_layer_end ; +assign dat_pkg_pd[30] = dat_pkg_dat_release ; +assign dat_push_data = {pkg_idx, dat_pkg_pd}; +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"cur_kernel\" -q wt_pkg_kernel_size"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"pkg_adv\" -d \"pkg_weight_size_w\" -q wt_pkg_weight_size"); +//: &eperl::flop("-nodeclare -rval \"{3{1'b0}}\" -en \"pkg_adv\" -d \"cur_r\" -q wt_pkg_cur_sub_h"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"pkg_adv\" -d \"~reg2dp_skip_weight_rls & pkg_group_end_w\" -q wt_pkg_wt_release"); +assign wt_pkg_channel_end = dat_pkg_channel_end; +assign wt_pkg_group_end = dat_pkg_group_end; +// PKT_PACK_WIRE( csc_wt_pkg , wt_pkg_ , wt_pkg_pd ) +assign wt_pkg_pd[6:0] = wt_pkg_weight_size[6:0]; +assign wt_pkg_pd[12:7] = wt_pkg_kernel_size[5:0]; +assign wt_pkg_pd[14:13] = wt_pkg_cur_sub_h[1:0]; +assign wt_pkg_pd[15] = wt_pkg_channel_end ; +assign wt_pkg_pd[16] = wt_pkg_group_end ; +assign wt_pkg_pd[17] = wt_pkg_wt_release ; +assign wt_push_data = {pkg_idx, wt_pkg_pd}; +//////////////////////////////////////////////////////////////////////// +// package fifos // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_CSC_SG_dat_fifo u_dat_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (dat_push_ready) //|> w + ,.wr_empty (dat_push_empty) //|> w + ,.wr_req (dat_push_req) //|< r + ,.wr_data (dat_push_data[32:0]) //|< r + ,.rd_ready (dat_pop_ready) //|< r + ,.rd_req (dat_pop_req) //|> w + ,.rd_data (dat_pop_data[32:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_CSC_SG_wt_fifo u_wt_fifo ( + .clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.wr_ready (wt_push_ready) //|> w + ,.wr_empty (wt_push_empty) //|> w + ,.wr_req (wt_push_req) //|< r + ,.wr_data (wt_push_data[19:0]) //|< r + ,.rd_ready (wt_pop_ready) //|< r + ,.rd_req (wt_pop_req) //|> w + ,.rd_data (wt_pop_data[19:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign dat_push_req = pkg_vld & wt_push_ready; +assign wt_push_req = pkg_vld & dat_push_ready; +//////////////////////////////////////////////////////////////////////// +// issue control logic // +//////////////////////////////////////////////////////////////////////// +assign {dat_pop_idx, dat_pop_pd} = dat_pop_data; +assign {wt_pop_idx, wt_pop_pd} = wt_pop_data; +// PKT_UNPACK_WIRE( csc_dat_pkg , sg2dat_ , dat_pop_pd ) +assign sg2dat_w_offset[4:0] = dat_pop_pd[4:0]; +assign sg2dat_h_offset[4:0] = dat_pop_pd[9:5]; +assign sg2dat_channel_size[6:0] = dat_pop_pd[16:10]; +assign sg2dat_stripe_length[6:0] = dat_pop_pd[23:17]; +assign sg2dat_cur_sub_h[1:0] = dat_pop_pd[25:24]; +assign sg2dat_block_end = dat_pop_pd[26]; +assign sg2dat_channel_end = dat_pop_pd[27]; +assign sg2dat_group_end = dat_pop_pd[28]; +assign sg2dat_layer_end = dat_pop_pd[29]; +assign sg2dat_dat_release = dat_pop_pd[30]; +// PKT_UNPACK_WIRE( csc_wt_pkg , sg2wt_ , wt_pop_pd ) +assign sg2wt_weight_size[6:0] = wt_pop_pd[6:0]; +assign sg2wt_kernel_size[5:0] = wt_pop_pd[12:7]; +assign sg2wt_cur_sub_h[1:0] = wt_pop_pd[14:13]; +assign sg2wt_channel_end = wt_pop_pd[15]; +assign sg2wt_group_end = wt_pop_pd[16]; +assign sg2wt_wt_release = wt_pop_pd[17]; +assign {mon_sg2wt_kernel_size_inc, sg2wt_kernel_size_inc} = sg2wt_kernel_size + 1'b1; +assign {mon_dat_stripe_batch_size_w[0], dat_stripe_batch_size_w} = sg2dat_stripe_length; +assign dat_stripe_img_size_w = sg2dat_stripe_length; +assign dat_stripe_size_w = is_img_d1 ? dat_stripe_img_size_w : {1'b0, dat_stripe_batch_size_w}; +assign {mon_dat_stripe_img_length_w, + dat_stripe_img_length_w} = ~is_img_d1 ? 8'b0 : + (reg2dp_y_extension == 2'h2) ? ((sg2dat_stripe_length + 2'h3) & 8'hfc) : + (reg2dp_y_extension == 2'h1) ? ((sg2dat_stripe_length + 2'h1) & 8'hfe) : + {1'b0, sg2dat_stripe_length}; +assign dat_stripe_length_w = is_img_d1 ? dat_stripe_img_length_w : {1'b0, dat_stripe_batch_size_w}; +//delay for one cycle +assign dat_max_cycles = ~dat_pop_ready ? 7'b0 : + (dat_stripe_length < 7'd8 ) ? 7'd8 : + dat_stripe_length; +assign wt_cycles = sg2wt_kernel_size[4:0]; +assign wt_max_cycles = ~wt_pop_ready ? 6'b0 : + ((wt_cycles <= 5'b1) & (pop_cnt <= 6'b1)) ? 6'h2 : + ({1'b0, wt_cycles} > pop_cnt) ? {1'b0, wt_cycles} : + pop_cnt; +assign {mon_max_cycles, max_cycles} = (dat_max_cycles >= {1'b0, wt_max_cycles}) ? (dat_max_cycles - 1'b1) : ({1'b0, wt_max_cycles} - 1'b1); +assign {mon_pop_cnt_dec, pop_cnt_dec} = pop_cnt - 1'b1; +assign pop_cnt_w = (dat_pop_ready | wt_pop_ready) ? max_cycles : (pop_cnt == 6'h0) ? 6'h0 : pop_cnt_dec; +assign wt_pop_ready = wt_pop_req & (((pop_cnt == 6'b0) & credit_ready) | (dat_pop_idx == wt_pop_idx)); +assign dat_pop_ready = dat_pop_req & (pop_cnt == 6'b0) & credit_ready & ((dat_pop_idx != wt_pop_idx) | ~wt_pop_req); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pop_ready\" -q wt_pop_ready_d1"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_pop_ready_d1\" -d \"dat_stripe_size_w\" -q dat_stripe_size"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_pop_ready_d1\" -d \"dat_stripe_length_w\" -q dat_stripe_length"); +//: &eperl::flop("-nodeclare -rval \"{6{1'b0}}\" -d \"pop_cnt_w\" -q pop_cnt"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"dat_pop_ready\" -q sg2dl_pvld"); +//: &eperl::flop("-nodeclare -rval \"{31{1'b0}}\" -en \"dat_pop_ready\" -d \"dat_pop_pd\" -q sg2dl_pd"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_pop_ready\" -q sg2wl_pvld"); +//: &eperl::flop("-nodeclare -rval \"{18{1'b0}}\" -en \"wt_pop_ready\" -d \"wt_pop_pd\" -q sg2wl_pd"); +//////////////////////////////////////////////////////////////////////// +// credit controll logic // +//////////////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +//flop credit signal because it cross partition boundary +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"accu2sc_credit_vld\" -q credit_vld"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -norst -en \"accu2sc_credit_vld\" -d \"accu2sc_credit_size\" -q credit_size"); +assign dat_impact_cnt = {2'b0, dat_stripe_size}; +assign credit_req_size = dat_impact_cnt; +assign credit_cnt_add = credit_vld ? credit_size : 4'b0; +assign credit_cnt_dec = (dat_pop_ready & sg2dat_channel_end) ? dat_impact_cnt : 9'b0; +assign {mon_credit_cnt_w, credit_cnt_w} = credit_cnt + credit_cnt_add - credit_cnt_dec; +assign credit_ready = ~sg2dat_channel_end | (credit_cnt >= credit_req_size); +//: my $credit_size = 8*2; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval $credit_size -en \"dat_pop_ready | credit_vld\" -d \"credit_cnt_w\" -q credit_cnt"); +//================ Non-SLCG clock domain end ================// +//////////////////////////////////////////////////////////////////////// +// convolution buffer local status // +//////////////////////////////////////////////////////////////////////// +//================ Non-SLCG clock domain ================// +assign dat_release = pkg_adv & pkg_layer_end_w & ~reg2dp_skip_data_rls; +assign dat_reuse_release = is_idle & reg2dp_op_en & (~reg2dp_data_reuse | is_mode_change) & (|last_slices); +assign slices_avl_add = cdma2sc_dat_updt ? cdma2sc_dat_slices : 14'b0; +assign slices_avl_sub = dat_release ? rls_slices : dat_reuse_release ? last_slices[13:0] : 14'b0; +assign {mon_slices_avl_w, slices_avl_w} = (dat_pending_req) ? 14'b0 : (slices_avl + slices_avl_add - slices_avl_sub); +assign wt_release = pkg_adv & ~reg2dp_skip_weight_rls & pkg_group_end_w; +assign wt_reuse_release = is_idle & reg2dp_op_en & ~reg2dp_weight_reuse & last_skip_weight_rls; +assign kernels_avl_add = cdma2sc_wt_updt ? cdma2sc_wt_kernels : 14'b0; +assign kernels_avl_sub = wt_release ? {{7{1'b0}}, cur_kernel} : wt_reuse_release ? last_kernels[13:0] : 14'b0; +assign {mon_kernels_avl_w, kernels_avl_w} = (wt_pending_req) ? 15'b0 : kernels_avl + kernels_avl_add - kernels_avl_sub; +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{14{1'b0}}\" -en \"dat_pending_req | dat_release | dat_reuse_release | cdma2sc_dat_updt\" -d \"slices_avl_w\" -q slices_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{15{1'b0}}\" -en \"wt_pending_req | wt_release | wt_reuse_release | cdma2sc_wt_updt\" -d \"kernels_avl_w\" -q kernels_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"dat_reuse_release\" -q sg2dl_reuse_rls"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"1'b0\" -d \"wt_reuse_release\" -q sg2wl_reuse_rls"); +//================ Non-SLCG clock domain end ================// +////////////////////////////////////////////////////////////// +///// functional point ///// +////////////////////////////////////////////////////////////// +assign dbg_cur_prec = reg2dp_proc_precision; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dbg_pre_prec <= {2{1'b1}}; + end else begin + dbg_pre_prec <= reg2dp_proc_precision; + end +end +endmodule // NV_NVDLA_CSC_sg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v new file mode 100644 index 0000000..be6e95f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_single_reg.v +module NV_NVDLA_CSC_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_csc_s_pointer_0_out; +wire [31:0] nvdla_csc_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_csc_s_pointer_0_wren = (reg_offset_wr == (32'h6004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_s_status_0_wren = (reg_offset_wr == (32'h6000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_csc_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_csc_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_csc_s_pointer_0_out + or nvdla_csc_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h6004 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_s_pointer_0_out ; + end + (32'h6000 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CSC_S_POINTER_0::consumer +// Register: NVDLA_CSC_S_POINTER_0 Field: producer + if (nvdla_csc_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CSC_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CSC_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h6004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_s_pointer_0_out, nvdla_csc_s_pointer_0_out); + (32'h6000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CSC_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CSC_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v.vcp new file mode 100644 index 0000000..be6e95f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_single_reg.v +module NV_NVDLA_CSC_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_csc_s_pointer_0_out; +wire [31:0] nvdla_csc_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_csc_s_pointer_0_wren = (reg_offset_wr == (32'h6004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_csc_s_status_0_wren = (reg_offset_wr == (32'h6000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_csc_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_csc_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_csc_s_pointer_0_out + or nvdla_csc_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h6004 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_s_pointer_0_out ; + end + (32'h6000 & 32'h00000fff): begin + reg_rd_data = nvdla_csc_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_CSC_S_POINTER_0::consumer +// Register: NVDLA_CSC_S_POINTER_0 Field: producer + if (nvdla_csc_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_CSC_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_CSC_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h6004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_CSC_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_csc_s_pointer_0_out, nvdla_csc_s_pointer_0_out); + (32'h6000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_CSC_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_CSC_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v new file mode 100644 index 0000000..9af196e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_slcg.v +module NV_NVDLA_CSC_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CSC_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v.vcp new file mode 100644 index 0000000..9af196e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v.vcp @@ -0,0 +1,391 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_slcg.v +module NV_NVDLA_CSC_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src_0 + ,slcg_en_src_1 + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input slcg_en_src_0; +input slcg_en_src_1; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src_0 & slcg_en_src_1; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_CSC_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_CSC_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v new file mode 100644 index 0000000..e3c2c9f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v @@ -0,0 +1,2901 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_wl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_CSC_wl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sg2wl_pvld //|< i + ,sg2wl_pd //|< i + ,sc_state //|< i + ,sg2wl_reuse_rls //|< i + ,sc2cdma_wt_pending_req //|< i + ,cdma2sc_wt_updt //|< i + ,cdma2sc_wt_kernels //|< i * + ,cdma2sc_wt_entries //|< i + ,cdma2sc_wmb_entries //|< i + ,sc2cdma_wt_updt //|> o + ,sc2cdma_wt_kernels //|> o + ,sc2cdma_wt_entries //|> o + ,sc2cdma_wmb_entries //|> o + ,sc2buf_wt_rd_en //|> o + ,sc2buf_wt_rd_addr //|> o + ,sc2buf_wt_rd_valid //|< i + ,sc2buf_wt_rd_data //|< i + `ifdef CBUF_WEIGHT_COMPRESSED + ,sc2buf_wmb_rd_en //|> o + ,sc2buf_wmb_rd_addr //|> o + ,sc2buf_wmb_rd_valid //|< i + ,sc2buf_wmb_rd_data //|< i + `endif + ,sc2mac_wt_a_pvld //|> o + ,sc2mac_wt_a_mask //|> o +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( ,sc2mac_wt_a_data${i} //|> o\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,sc2mac_wt_a_data0 //|> o + ,sc2mac_wt_a_data1 //|> o + ,sc2mac_wt_a_data2 //|> o + ,sc2mac_wt_a_data3 //|> o + ,sc2mac_wt_a_data4 //|> o + ,sc2mac_wt_a_data5 //|> o + ,sc2mac_wt_a_data6 //|> o + ,sc2mac_wt_a_data7 //|> o + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_a_sel //|> o + ,sc2mac_wt_b_pvld //|> o + ,sc2mac_wt_b_mask //|> o +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( ,sc2mac_wt_b_data${i} //|> o\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,sc2mac_wt_b_data0 //|> o + ,sc2mac_wt_b_data1 //|> o + ,sc2mac_wt_b_data2 //|> o + ,sc2mac_wt_b_data3 //|> o + ,sc2mac_wt_b_data4 //|> o + ,sc2mac_wt_b_data5 //|> o + ,sc2mac_wt_b_data6 //|> o + ,sc2mac_wt_b_data7 //|> o + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_b_sel //|> o + ,nvdla_core_ng_clk //|< i + ,reg2dp_op_en //|< i + ,reg2dp_in_precision //|< i * + ,reg2dp_proc_precision //|< i + ,reg2dp_y_extension //|< i + ,reg2dp_weight_reuse //|< i * + ,reg2dp_skip_weight_rls //|< i + ,reg2dp_weight_format //|< i + ,reg2dp_weight_bytes //|< i + ,reg2dp_wmb_bytes //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_weight_bank //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input sg2wl_pvld; /* data valid */ +input [17:0] sg2wl_pd; +input [1:0] sc_state; +input sg2wl_reuse_rls; +input sc2cdma_wt_pending_req; +input cdma2sc_wt_updt; /* data valid */ +input [13:0] cdma2sc_wt_kernels; +input [15 -1:0] cdma2sc_wt_entries; +input [8:0] cdma2sc_wmb_entries; +output sc2cdma_wt_updt; /* data valid */ +output [13:0] sc2cdma_wt_kernels; +output [15 -1:0] sc2cdma_wt_entries; +output [8:0] sc2cdma_wmb_entries; +output sc2buf_wt_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wt_rd_addr; +input sc2buf_wt_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wt_rd_data; +`ifdef CBUF_WEIGHT_COMPRESSED +output sc2buf_wmb_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wmb_rd_addr; +input sc2buf_wmb_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wmb_rd_data; +`else +wire sc2buf_wmb_rd_valid=1'b0; +wire [64 -1:0] sc2buf_wmb_rd_data= {64{1'b0}}; +`endif +output sc2mac_wt_a_pvld; /* data valid */ +output sc2mac_wt_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_a_mask; +output [8 -1:0] sc2mac_wt_b_mask; +output [8/2 -1:0] sc2mac_wt_a_sel; +output [8/2 -1:0] sc2mac_wt_b_sel; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(output [8 -1:0] sc2mac_wt_a_data${i};\n); +//: print qq(output [8 -1:0] sc2mac_wt_b_data${i};\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8 -1:0] sc2mac_wt_a_data0; +output [8 -1:0] sc2mac_wt_b_data0; +output [8 -1:0] sc2mac_wt_a_data1; +output [8 -1:0] sc2mac_wt_b_data1; +output [8 -1:0] sc2mac_wt_a_data2; +output [8 -1:0] sc2mac_wt_b_data2; +output [8 -1:0] sc2mac_wt_a_data3; +output [8 -1:0] sc2mac_wt_b_data3; +output [8 -1:0] sc2mac_wt_a_data4; +output [8 -1:0] sc2mac_wt_b_data4; +output [8 -1:0] sc2mac_wt_a_data5; +output [8 -1:0] sc2mac_wt_b_data5; +output [8 -1:0] sc2mac_wt_a_data6; +output [8 -1:0] sc2mac_wt_b_data6; +output [8 -1:0] sc2mac_wt_a_data7; +output [8 -1:0] sc2mac_wt_b_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [1:0] reg2dp_y_extension; +input [0:0] reg2dp_weight_reuse; +input [0:0] reg2dp_skip_weight_rls; +input [0:0] reg2dp_weight_format; +input [31:0] reg2dp_weight_bytes; +input [27:0] reg2dp_wmb_bytes; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_weight_bank; +reg [4:0] data_bank; +reg [64 -1:0] dec_input_data; +reg [8 -1:0] dec_input_mask; +reg [9:0] dec_input_mask_en; +reg dec_input_pipe_valid; +reg is_compressed_d1; +reg is_sg_running_d1; +reg [15 -1:0] last_weight_entries; +reg [8:0] last_wmb_entries; +reg [14 -1:0] sc2buf_wmb_rd_addr; +reg sc2buf_wmb_rd_en; +reg [14 -1:0] sc2buf_wt_rd_addr; +reg sc2buf_wt_rd_en; +reg [8:0] sc2cdma_wmb_entries; +reg [15 -1:0] sc2cdma_wt_entries; +reg sc2cdma_wt_updt; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(reg [8 -1:0] sc2mac_wt_a_data${i};\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [8 -1:0] sc2mac_wt_a_data0; +reg [8 -1:0] sc2mac_wt_a_data1; +reg [8 -1:0] sc2mac_wt_a_data2; +reg [8 -1:0] sc2mac_wt_a_data3; +reg [8 -1:0] sc2mac_wt_a_data4; +reg [8 -1:0] sc2mac_wt_a_data5; +reg [8 -1:0] sc2mac_wt_a_data6; +reg [8 -1:0] sc2mac_wt_a_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [8 -1:0] sc2mac_wt_a_mask; +reg sc2mac_wt_a_pvld; +reg [8/2 -1:0] sc2mac_wt_a_sel; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(reg [7:0] sc2mac_wt_b_data${i};\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [7:0] sc2mac_wt_b_data0; +reg [7:0] sc2mac_wt_b_data1; +reg [7:0] sc2mac_wt_b_data2; +reg [7:0] sc2mac_wt_b_data3; +reg [7:0] sc2mac_wt_b_data4; +reg [7:0] sc2mac_wt_b_data5; +reg [7:0] sc2mac_wt_b_data6; +reg [7:0] sc2mac_wt_b_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [8 -1:0] sc2mac_wt_b_mask; +reg sc2mac_wt_b_pvld; +reg [8/2 -1:0] sc2mac_wt_b_sel; +reg [4:0] stripe_cnt; +reg [2:0] sub_h_total; +reg [4:0] weight_bank; +reg [17:0] wl_in_pd_d1; +reg wl_in_pvld_d1; +reg [10:0] wmb_element_avl; +reg [10:0] wmb_element_avl_last; +reg [64 -1:0] wmb_emask_remain; +reg [64 -1:0] wmb_emask_remain_last; +reg [8:0] wmb_entry_avl; +reg [8:0] wmb_entry_end; +reg [8:0] wmb_entry_st; +reg wmb_pipe_valid_d1; +reg [14 -1:0] wmb_req_addr; +reg [14 -1:0] wmb_req_addr_last; +reg wmb_req_channel_end_d1; +reg [1:0] wmb_req_cur_sub_h_d1; +reg [7:0] wmb_req_element_d1; +reg wmb_req_group_end_d1; +reg [6:0] wmb_req_ori_element_d1; +reg wmb_req_rls_d1; +reg [8:0] wmb_req_rls_entries_d1; +reg wmb_req_stripe_end_d1; +reg [8:0] wmb_rls_cnt; +reg wmb_rls_cnt_vld; +reg [9:0] wmb_rsp_bit_remain; +reg [9:0] wmb_rsp_bit_remain_last; +reg [7:0] wt_byte_avl; +reg [7:0] wt_byte_avl_last; +reg [64 -1:0] wt_data_remain; +reg [64 -1:0] wt_data_remain_last; +reg [15 -1:0] wt_entry_avl; +reg [15 -1:0] wt_entry_end; +reg [15 -1:0] wt_entry_st; +reg [14 -1:0] wt_req_addr; +reg [14 -1:0] wt_req_addr_last; +reg [7:0] wt_req_bytes_d1; +reg wt_req_channel_end; +reg wt_req_channel_end_d1; +reg [1:0] wt_req_cur_sub_h; +reg [8 -1:0] wt_req_emask; +reg wt_req_group_end; +reg wt_req_group_end_d1; +reg [8 -1:0] wt_req_mask_d1; +reg wt_req_mask_en_d1; +reg [6:0] wt_req_ori_element; +reg [6:0] wt_req_ori_sft_3; +reg wt_req_pipe_valid; +reg wt_req_pipe_valid_d1; +reg wt_req_rls; +reg wt_req_rls_d1; +reg wt_req_stripe_end; +reg wt_req_stripe_end_d1; +reg [8:0] wt_req_wmb_rls_entries; +reg [8:0] wt_req_wmb_rls_entries_d1; +reg [15 -1:0] wt_req_wt_rls_entries_d1; +reg [15 -1:0] wt_rls_cnt; +reg wt_rls_cnt_vld; +reg [6:0] wt_rsp_byte_remain; +reg [6:0] wt_rsp_byte_remain_last; +reg wt_rsp_last_stripe_end; +reg [8 -1:0] wt_rsp_sel_d1; +wire addr_init; +wire cbuf_reset; +wire [4:0] data_bank_w; +wire [64 -1:0] dbg_csc_wt_a; +wire [64 -1:0] dbg_csc_wt_b; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(wire [8 -1:0] dbg_csc_wt_a_${i};\n); +//: print qq(wire [8 -1:0] dbg_csc_wt_b_${i};\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8 -1:0] dbg_csc_wt_a_0; +wire [8 -1:0] dbg_csc_wt_b_0; +wire [8 -1:0] dbg_csc_wt_a_1; +wire [8 -1:0] dbg_csc_wt_b_1; +wire [8 -1:0] dbg_csc_wt_a_2; +wire [8 -1:0] dbg_csc_wt_b_2; +wire [8 -1:0] dbg_csc_wt_a_3; +wire [8 -1:0] dbg_csc_wt_b_3; +wire [8 -1:0] dbg_csc_wt_a_4; +wire [8 -1:0] dbg_csc_wt_b_4; +wire [8 -1:0] dbg_csc_wt_a_5; +wire [8 -1:0] dbg_csc_wt_b_5; +wire [8 -1:0] dbg_csc_wt_a_6; +wire [8 -1:0] dbg_csc_wt_b_6; +wire [8 -1:0] dbg_csc_wt_a_7; +wire [8 -1:0] dbg_csc_wt_b_7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8 -1:0] dec_input_sel; +wire is_compressed; +wire is_sg_done; +wire is_sg_idle; +wire is_sg_pending; +wire is_sg_running; +wire is_stripe_end; +wire is_wr_req_addr_wrap; +wire is_wt_entry_end_wrap; +wire is_wt_entry_st_wrap; +wire [8:0] last_wmb_entries_w; +wire layer_st; +wire mon_data_bank_w; +wire mon_stripe_cnt_inc; +wire mon_stripe_length; +wire [2:0] mon_sub_h_total_w; +wire mon_weight_bank_w; +wire mon_wmb_element_avl_inc; +wire mon_wmb_entry_avl_w; +wire mon_wmb_entry_end_inc; +wire mon_wmb_entry_st_inc; +wire mon_wmb_req_addr_inc; +wire mon_wmb_req_element; +wire mon_wmb_rls_cnt_inc; +wire [1:0] mon_wmb_rsp_bit_remain_w; +wire mon_wmb_shift_remain; +wire mon_wt_byte_avl_inc; +wire mon_wt_entry_avl_w; +wire mon_wt_entry_end_inc_wrap; +wire mon_wt_entry_st_inc_wrap; +wire mon_wt_req_addr_inc; +wire mon_wt_req_addr_out; +wire mon_wt_rls_cnt_inc; +wire [1:0] mon_wt_rsp_byte_remain_w; +wire mon_wt_shift_remain; +wire reuse_rls; +wire [8 -1:0] sc2mac_out_a_mask; +wire [8/2 -1:0] sc2mac_out_a_sel_w; +wire [8 -1:0] sc2mac_out_b_mask; +wire [8/2 -1:0] sc2mac_out_b_sel_w; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(wire [8 -1:0] sc2mac_out_data${i};\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8 -1:0] sc2mac_out_data0; +wire [8 -1:0] sc2mac_out_data1; +wire [8 -1:0] sc2mac_out_data2; +wire [8 -1:0] sc2mac_out_data3; +wire [8 -1:0] sc2mac_out_data4; +wire [8 -1:0] sc2mac_out_data5; +wire [8 -1:0] sc2mac_out_data6; +wire [8 -1:0] sc2mac_out_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8 -1:0] sc2mac_out_mask; +wire sc2mac_out_pvld; +wire [8 -1:0] sc2mac_out_sel; +wire sc2mac_wt_a_pvld_w; +wire sc2mac_wt_b_pvld_w; +wire [4:0] stripe_cnt_inc; +wire stripe_cnt_reg_en; +wire [4:0] stripe_cnt_w; +wire [4:0] stripe_length; +wire [8 -1:0] sub_h_mask_1; +wire [8 -1:0] sub_h_mask_2; +wire [8 -1:0] sub_h_mask_3; +wire [2:0] sub_h_total_w; +wire sub_rls; +wire [8:0] sub_rls_wmb_entries; +wire [15 -1:0] sub_rls_wt_entries; +wire [4:0] weight_bank_w; +wire wl_channel_end; +wire [1:0] wl_cur_sub_h; +wire wl_group_end; +wire [17:0] wl_in_pd; +wire [17:0] wl_in_pd_d0; +wire wl_in_pvld; +wire wl_in_pvld_d0; +wire [5:0] wl_kernel_size; +wire [17:0] wl_pd; +wire wl_pvld; +wire [6:0] wl_weight_size; +wire wl_wt_release; +wire [10:0] wmb_element_avl_add; +wire [10:0] wmb_element_avl_inc; +wire wmb_element_avl_last_reg_en; +wire wmb_element_avl_reg_en; +wire [7:0] wmb_element_avl_sub; +wire [10:0] wmb_element_avl_w; +wire [8 -1:0] wmb_emask_rd_ls; +wire [64 -1:0] wmb_emask_rd_rs; +wire wmb_emask_remain_last_reg_en; +wire wmb_emask_remain_reg_en; +wire [64 -1:0] wmb_emask_remain_rs; +wire [64 -1:0] wmb_emask_remain_w; +wire [8:0] wmb_entry_avl_add; +wire [8:0] wmb_entry_avl_sub; +wire [8:0] wmb_entry_avl_w; +wire [8:0] wmb_entry_end_inc; +wire [8:0] wmb_entry_end_w; +wire [8:0] wmb_entry_st_inc; +wire [8:0] wmb_entry_st_w; +wire wmb_pipe_valid; +wire [14 -1:0] wmb_req_addr_inc; +wire wmb_req_addr_last_reg_en; +wire wmb_req_addr_reg_en; +wire [14 -1:0] wmb_req_addr_w; +wire [7:0] wmb_req_cycle_element; +wire wmb_req_d1_channel_end; +wire [1:0] wmb_req_d1_cur_sub_h; +wire [7:0] wmb_req_d1_element; +wire wmb_req_d1_group_end; +wire [6:0] wmb_req_d1_ori_element; +wire wmb_req_d1_rls; +wire [8:0] wmb_req_d1_rls_entries; +wire wmb_req_d1_stripe_end; +wire [7:0] wmb_req_element; +wire [6:0] wmb_req_ori_element; +wire [30:0] wmb_req_pipe_pd; +wire wmb_req_pipe_pvld; +wire wmb_req_valid; +wire [8:0] wmb_rls_cnt_inc; +wire wmb_rls_cnt_reg_en; +wire wmb_rls_cnt_vld_w; +wire [8:0] wmb_rls_cnt_w; +wire [8:0] wmb_rls_entries; +wire [10:0] wmb_rsp_bit_remain_add; +wire wmb_rsp_bit_remain_last_reg_en; +wire [7:0] wmb_rsp_bit_remain_sub; +wire [9:0] wmb_rsp_bit_remain_w; +wire wmb_rsp_channel_end; +wire [1:0] wmb_rsp_cur_sub_h; +wire [7:0] wmb_rsp_element; +wire [8 -1:0] wmb_rsp_emask; +wire [8 -1:0] wmb_rsp_emask_in; +wire wmb_rsp_group_end; +wire [6:0] wmb_rsp_ori_element; +wire [6:0] wmb_rsp_ori_sft_3; +wire [30:0] wmb_rsp_pipe_pd; +wire [30:0] wmb_rsp_pipe_pd_d0; +wire wmb_rsp_pipe_pvld; +wire wmb_rsp_pipe_pvld_d0; +wire wmb_rsp_rls; +wire [8:0] wmb_rsp_rls_entries; +wire wmb_rsp_stripe_end; +wire [8 -1:0] wmb_rsp_vld_s; +wire [7:0] wmb_shift_remain; +wire [7:0] wt_byte_avl_add; +wire [7:0] wt_byte_avl_inc; +wire [7:0] wt_byte_avl_sub; +wire [7:0] wt_byte_avl_w; +wire wt_byte_last_reg_en; +wire [64 -1:0] wt_data_input_ls; +wire [64 -1:0] wt_data_input_rs; +wire [64 -1:0] wt_data_input_sft; +wire wt_data_remain_last_reg_en; +wire [64 -1:0] wt_data_remain_masked; +wire wt_data_remain_reg_en; +wire [64 -1:0] wt_data_remain_rs; +wire [64 -1:0] wt_data_remain_w; +wire [15 -1:0] wt_entry_avl_add; +wire [15 -1:0] wt_entry_avl_sub; +wire [15 -1:0] wt_entry_avl_w; +wire [15 -1:0] wt_entry_end_inc; +wire [15 -1:0] wt_entry_end_inc_wrap; +wire [15 -1:0] wt_entry_end_w; +wire [15 -1:0] wt_entry_st_inc; +wire [15 -1:0] wt_entry_st_inc_wrap; +wire [15 -1:0] wt_entry_st_w; +wire mon_wt_entry_end_inc; +wire mon_wt_entry_st_inc; +wire [14 -1:0] wt_req_addr_inc; +wire [14 -1:0] wt_req_addr_inc_wrap; +wire wt_req_addr_last_reg_en; +wire [14 -1:0] wt_req_addr_out; +wire wt_req_addr_reg_en; +wire [14 -1:0] wt_req_addr_w; +wire [8 -1:0] wt_req_bmask; +wire [7:0] wt_req_bytes; +wire [7:0] wt_req_d1_bytes; +wire wt_req_d1_channel_end; +wire wt_req_d1_group_end; +wire wt_req_d1_rls; +wire wt_req_d1_stripe_end; +wire [8:0] wt_req_d1_wmb_rls_entries; +wire [15 -1:0] wt_req_d1_wt_rls_entries; +wire [8 -1:0] wt_req_emask_p0; +wire [8 -1:0] wt_req_emask_p1; +wire [8 -1:0] wt_req_emask_p2; +wire [8 -1:0] wt_req_emask_p3; +wire wt_req_mask_en; +wire [8 -1:0] wt_req_mask_w; +wire [6:0] wt_req_ori_sft_1; +wire [6:0] wt_req_ori_sft_2; +wire [35:0] wt_req_pipe_pd; +wire wt_req_pipe_pvld; +wire wt_req_valid; +wire [8 -1:0] wt_req_vld_bit; +wire wt_rls; +wire [15 -1:0] wt_rls_cnt_inc; +wire wt_rls_cnt_reg_en; +wire wt_rls_cnt_vld_w; +wire [15 -1:0] wt_rls_cnt_w; +wire [15 -1:0] wt_rls_entries; +wire wt_rls_updt; +wire [8:0] wt_rls_wmb_entries; +wire [15 -1:0] wt_rls_wt_entries; +wire [7:0] wt_rsp_byte_remain_add; +wire wt_rsp_byte_remain_en; +wire wt_rsp_byte_remain_last_en; +wire [6:0] wt_rsp_byte_remain_w; +wire [7:0] wt_rsp_bytes; +wire wt_rsp_channel_end; +wire [64 -1:0] wt_rsp_data; +wire wt_rsp_group_end; +wire [8 -1:0] wt_rsp_mask; +wire [8 -1:0] wt_rsp_mask_d0; +wire [8 -1:0] wt_rsp_mask_d1_w; +wire wt_rsp_mask_en; +wire wt_rsp_mask_en_d0; +wire [35:0] wt_rsp_pipe_pd; +wire [35:0] wt_rsp_pipe_pd_d0; +wire wt_rsp_pipe_pvld; +wire wt_rsp_pipe_pvld_d0; +wire wt_rsp_rls; +wire [8 -1:0] wt_rsp_sel_w; +wire wt_rsp_stripe_end; +wire [8:0] wt_rsp_wmb_rls_entries; +wire [15 -1:0] wt_rsp_wt_rls_entries; +wire [7:0] wt_shift_remain; +///////////////////////////////////////////////////////////////////////////////////////////// +// Pipeline of Weight loader, for both compressed weight and uncompressed weight +// +// input_package-------------- +// | | +// WMB_request | +// | | +// conv_buffer | +// | | +// WMB_data ---------> weight_request +// | | +// | conv_buffer +// | | +// | weight_data +// | | +// | weight_data +// | | +// |------------> weight_decompressor +// | +// weight_to_MAC_cell +// +///////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///// status from sequence generator ///// +////////////////////////////////////////////////////////////// +assign is_sg_idle = (sc_state == 0 ); +assign is_sg_pending = (sc_state == 1 ); +assign is_sg_running = (sc_state == 2 ); +assign is_sg_done = (sc_state == 3 ); +assign addr_init = is_sg_running & ~is_sg_running_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_sg_running\" -q is_sg_running_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_sg_running_d1 <= 1'b0; + end else begin + is_sg_running_d1 <= is_sg_running; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// input signals from registers ///// +////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en & is_sg_idle; +assign {mon_data_bank_w,data_bank_w} = reg2dp_data_bank + 1'b1; +assign {mon_weight_bank_w,weight_bank_w} = reg2dp_weight_bank + 1'b1; +//assign is_int8 = (reg2dp_proc_precision == 2'h0 ); +assign is_compressed = (reg2dp_weight_format == 1'h1 ); +assign {sub_h_total_w,mon_sub_h_total_w} = (6'h9 << reg2dp_y_extension); +assign last_wmb_entries_w = is_compressed_d1 ? reg2dp_wmb_bytes[8+3 :3] : 9'b0; +//: my $kk=15; +//: my $jj=3; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"data_bank_w\" -q data_bank"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"weight_bank_w\" -q weight_bank"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"is_sg_done & reg2dp_skip_weight_rls\" -d \"reg2dp_weight_bytes[${kk}-1+${jj}:${jj}]\" -q last_weight_entries"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"is_sg_done & reg2dp_skip_weight_rls\" -d \"last_wmb_entries_w\" -q last_wmb_entries"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"is_compressed\" -q is_compressed_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + data_bank <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + data_bank <= data_bank_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + data_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + weight_bank <= {5{1'b0}}; + end else begin + if ((layer_st) == 1'b1) begin + weight_bank <= weight_bank_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + weight_bank <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_weight_entries <= {15{1'b0}}; + end else begin + if ((is_sg_done & reg2dp_skip_weight_rls) == 1'b1) begin + last_weight_entries <= reg2dp_weight_bytes[15-1+3:3]; + // VCS coverage off + end else if ((is_sg_done & reg2dp_skip_weight_rls) == 1'b0) begin + end else begin + last_weight_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_wmb_entries <= {9{1'b0}}; + end else begin + if ((is_sg_done & reg2dp_skip_weight_rls) == 1'b1) begin + last_wmb_entries <= last_wmb_entries_w; + // VCS coverage off + end else if ((is_sg_done & reg2dp_skip_weight_rls) == 1'b0) begin + end else begin + last_wmb_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_h_total <= 3'h1; + end else begin + if ((layer_st) == 1'b1) begin + sub_h_total <= sub_h_total_w; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + sub_h_total <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_compressed_d1 <= 1'b0; + end else begin + if ((layer_st) == 1'b1) begin + is_compressed_d1 <= is_compressed; + // VCS coverage off + end else if ((layer_st) == 1'b0) begin + end else begin + is_compressed_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//Now it's a valid test case +////////////////////////////////////////////////////////////// +///// cbuf status management ///// +////////////////////////////////////////////////////////////// +assign cbuf_reset = sc2cdma_wt_pending_req; +//////////////////////////////////// calculate avaliable kernels //////////////////////////////////// +//Avaliable kernel size is useless here. Discard the code +//////////////////////////////////// calculate avaliable weight entries //////////////////////////////////// +//================ Non-SLCG clock domain ================// +assign wt_entry_avl_add = cdma2sc_wt_updt ? cdma2sc_wt_entries : {15{1'b0}}; +assign wt_entry_avl_sub = wt_rls ? wt_rls_wt_entries : {15{1'b0}}; +assign {mon_wt_entry_avl_w,wt_entry_avl_w} = (cbuf_reset) ? {15{1'b0}} : wt_entry_avl + wt_entry_avl_add - wt_entry_avl_sub; +//////////////////////////////////// calculate avaliable wmb entries //////////////////////////////////// +assign wmb_entry_avl_add = cdma2sc_wt_updt ? cdma2sc_wmb_entries : 9'b0; +assign wmb_entry_avl_sub = wt_rls ? wt_rls_wmb_entries : 9'b0; +assign {mon_wmb_entry_avl_w,wmb_entry_avl_w} = (cbuf_reset) ? 10'b0 : wmb_entry_avl + wmb_entry_avl_add - wmb_entry_avl_sub; +//////////////////////////////////// calculate weight entries start offset //////////////////////////////////// +assign {mon_wt_entry_st_inc,wt_entry_st_inc} = wt_entry_st + wt_rls_wt_entries; +assign {mon_wt_entry_st_inc_wrap,wt_entry_st_inc_wrap} = wt_entry_st_inc[15 -1:0] - {weight_bank, {9{1'b0}}}; +assign is_wt_entry_st_wrap = (wt_entry_st_inc >= {1'b0, weight_bank, {9{1'b0}}}); +assign wt_entry_st_w = (cbuf_reset) ? {15{1'b0}} : + (~wt_rls) ? wt_entry_st : + is_wt_entry_st_wrap ? wt_entry_st_inc_wrap : + wt_entry_st_inc[15 -1:0]; +//////////////////////////////////// calculate weight entries end offset //////////////////////////////////// +assign {mon_wt_entry_end_inc,wt_entry_end_inc} = wt_entry_end + cdma2sc_wt_entries; +assign {mon_wt_entry_end_inc_wrap,wt_entry_end_inc_wrap} = wt_entry_end_inc[15 -1:0] - {weight_bank, {9{1'b0}}}; +assign is_wt_entry_end_wrap = (wt_entry_end_inc >= {1'b0, weight_bank, {9{1'b0}}}); +assign wt_entry_end_w = (cbuf_reset) ? {15{1'b0}} : is_wt_entry_end_wrap ? wt_entry_end_inc_wrap : wt_entry_end_inc[15 -1:0]; +//////////////////////////////////// calculate wmb entries start offset //////////////////////////////////// +assign {mon_wmb_entry_st_inc,wmb_entry_st_inc} = wmb_entry_st + wt_rls_wmb_entries; +assign wmb_entry_st_w = (cbuf_reset) ? 9'b0 : (~wt_rls) ? wmb_entry_st : wmb_entry_st_inc[8:0]; +//////////////////////////////////// calculate wmb entries end offset //////////////////////////////////// +assign {mon_wmb_entry_end_inc,wmb_entry_end_inc} = wmb_entry_end + cdma2sc_wmb_entries; +assign wmb_entry_end_w = (cbuf_reset) ? 9'b0 : wmb_entry_end_inc[8:0]; +//////////////////////////////////// registers and assertions //////////////////////////////////// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{12{1'b0}}\" -en \"cdma2sc_wt_updt | wt_rls | cbuf_reset\" -d \"wt_entry_avl_w\" -q wt_entry_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{9{1'b0}}\" -en \"cdma2sc_wt_updt | wt_rls | cbuf_reset\" -d \"wmb_entry_avl_w\" -q wmb_entry_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{12{1'b0}}\" -en \"cbuf_reset | wt_rls\" -d \"wt_entry_st_w\" -q wt_entry_st"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{12{1'b0}}\" -en \"cbuf_reset | cdma2sc_wt_updt\" -d \"wt_entry_end_w\" -q wt_entry_end"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{9{1'b0}}\" -en \"cbuf_reset | wt_rls\" -d \"wmb_entry_st_w\" -q wmb_entry_st"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{9{1'b0}}\" -en \"cbuf_reset | cdma2sc_wt_updt\" -d \"wmb_entry_end_w\" -q wmb_entry_end"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_entry_avl <= {12{1'b0}}; + end else begin + if ((cdma2sc_wt_updt | wt_rls | cbuf_reset) == 1'b1) begin + wt_entry_avl <= wt_entry_avl_w; + // VCS coverage off + end else if ((cdma2sc_wt_updt | wt_rls | cbuf_reset) == 1'b0) begin + end else begin + wt_entry_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_entry_avl <= {9{1'b0}}; + end else begin + if ((cdma2sc_wt_updt | wt_rls | cbuf_reset) == 1'b1) begin + wmb_entry_avl <= wmb_entry_avl_w; + // VCS coverage off + end else if ((cdma2sc_wt_updt | wt_rls | cbuf_reset) == 1'b0) begin + end else begin + wmb_entry_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_entry_st <= {12{1'b0}}; + end else begin + if ((cbuf_reset | wt_rls) == 1'b1) begin + wt_entry_st <= wt_entry_st_w; + // VCS coverage off + end else if ((cbuf_reset | wt_rls) == 1'b0) begin + end else begin + wt_entry_st <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_entry_end <= {12{1'b0}}; + end else begin + if ((cbuf_reset | cdma2sc_wt_updt) == 1'b1) begin + wt_entry_end <= wt_entry_end_w; + // VCS coverage off + end else if ((cbuf_reset | cdma2sc_wt_updt) == 1'b0) begin + end else begin + wt_entry_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_entry_st <= {9{1'b0}}; + end else begin + if ((cbuf_reset | wt_rls) == 1'b1) begin + wmb_entry_st <= wmb_entry_st_w; + // VCS coverage off + end else if ((cbuf_reset | wt_rls) == 1'b0) begin + end else begin + wmb_entry_st <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_ng_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_entry_end <= {9{1'b0}}; + end else begin + if ((cbuf_reset | cdma2sc_wt_updt) == 1'b1) begin + wmb_entry_end <= wmb_entry_end_w; + // VCS coverage off + end else if ((cbuf_reset | cdma2sc_wt_updt) == 1'b0) begin + end else begin + wmb_entry_end <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//================ Non-SLCG clock domain end ================// +////////////////////////////////////////////////////////////// +///// cbuf status update ///// +////////////////////////////////////////////////////////////// +assign sub_rls = (wt_rsp_pipe_pvld & wt_rsp_rls); +assign sub_rls_wt_entries = wt_rsp_wt_rls_entries; +assign sub_rls_wmb_entries = wt_rsp_wmb_rls_entries; +assign reuse_rls = sg2wl_reuse_rls; +assign wt_rls = reuse_rls | sub_rls; +assign wt_rls_wt_entries = reuse_rls ? last_weight_entries : sub_rls_wt_entries; +assign wt_rls_wmb_entries = reuse_rls ? last_wmb_entries : sub_rls_wmb_entries; +assign wt_rls_updt = wt_rls; +//: my $kk=15; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_rls_updt\" -q sc2cdma_wt_updt"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rls_updt\" -d \"wt_rls_wt_entries\" -q sc2cdma_wt_entries"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wt_rls_updt\" -d \"wt_rls_wmb_entries\" -q sc2cdma_wmb_entries"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2cdma_wt_updt <= 1'b0; + end else begin + sc2cdma_wt_updt <= wt_rls_updt; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2cdma_wt_entries <= {15{1'b0}}; + end else begin + if ((wt_rls_updt) == 1'b1) begin + sc2cdma_wt_entries <= wt_rls_wt_entries; + // VCS coverage off + end else if ((wt_rls_updt) == 1'b0) begin + end else begin + sc2cdma_wt_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2cdma_wmb_entries <= {9{1'b0}}; + end else begin + if ((wt_rls_updt) == 1'b1) begin + sc2cdma_wmb_entries <= wt_rls_wmb_entries; + // VCS coverage off + end else if ((wt_rls_updt) == 1'b0) begin + end else begin + sc2cdma_wmb_entries <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//sc2cmda_wt_kernels is useless +assign sc2cdma_wt_kernels = 14'b0; +////////////////////////////////////////////////////////////// +///// input data package ///// +////////////////////////////////////////////////////////////// +//: my $pipe_depth = 5 -4; +//: my $i; +//: my $j; +//: if($pipe_depth == 0) { +//: print "assign wl_in_pvld = sg2wl_pvld;\n"; +//: print "assign wl_in_pd = sg2wl_pd;\n"; +//: } else { +//: print "assign wl_in_pvld_d0 = sg2wl_pvld;\n"; +//: print "assign wl_in_pd_d0 = sg2wl_pd;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wl_in_pvld_d${i}\" -q wl_in_pvld_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{18{1'b0}}\" -en \"wl_in_pvld_d${i}\" -d \"wl_in_pd_d${i}\" -q wl_in_pd_d${j}"); +//: } +//: print "assign wl_in_pvld = wl_in_pvld_d${i};\n"; +//: print "assign wl_in_pd = wl_in_pd_d${i};\n\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign wl_in_pvld_d0 = sg2wl_pvld; +assign wl_in_pd_d0 = sg2wl_pd; + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wl_in_pvld_d1 <= 1'b0; + end else begin + wl_in_pvld_d1 <= wl_in_pvld_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wl_in_pd_d1 <= {18{1'b0}}; + end else begin + if ((wl_in_pvld_d0) == 1'b1) begin + wl_in_pd_d1 <= wl_in_pd_d0; + // VCS coverage off + end else if ((wl_in_pvld_d0) == 1'b0) begin + end else begin + wl_in_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +assign wl_in_pvld = wl_in_pvld_d1; +assign wl_in_pd = wl_in_pd_d1; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign wl_pvld = wl_in_pvld; +assign wl_pd = wl_in_pd; +// PKT_UNPACK_WIRE( csc_wt_pkg , wl_ , wl_pd ) +assign wl_weight_size[6:0] = wl_pd[6:0]; +assign wl_kernel_size[5:0] = wl_pd[12:7]; +assign wl_cur_sub_h[1:0] = wl_pd[14:13]; +assign wl_channel_end = wl_pd[15]; +assign wl_group_end = wl_pd[16]; +assign wl_wt_release = wl_pd[17]; +////////////////////////////////////////////////////////////// +///// generate wmb read request ///// +////////////////////////////////////////////////////////////// +//////////////////////////////////// generate wmb_pipe_valid siganal //////////////////////////////////// +assign {mon_stripe_cnt_inc,stripe_cnt_inc} = stripe_cnt + 1'b1; +assign stripe_cnt_w = layer_st ? 5'b0 : is_stripe_end ? 5'b0 : stripe_cnt_inc; +assign {mon_stripe_length,stripe_length} = wl_kernel_size[5:0]; +assign is_stripe_end = (stripe_cnt_inc == stripe_length); +//assign is_stripe_st = wl_pvld; +assign stripe_cnt_reg_en = layer_st | wmb_pipe_valid; +assign wmb_pipe_valid = wl_pvld ? 1'b1 : ~(|stripe_cnt) ? 1'b0 : wmb_pipe_valid_d1; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"stripe_cnt_reg_en\" -d \"stripe_cnt_w\" -q stripe_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stripe_cnt <= {5{1'b0}}; + end else begin + if ((stripe_cnt_reg_en) == 1'b1) begin + stripe_cnt <= stripe_cnt_w; + // VCS coverage off + end else if ((stripe_cnt_reg_en) == 1'b0) begin + end else begin + stripe_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate wmb_req_valid siganal //////////////////////////////////// +assign wmb_element_avl_add = ~wmb_req_valid ? 11'b0 : 11'h40; +assign wmb_element_avl_sub = wmb_pipe_valid ? wmb_req_element : 8'h0; +assign {mon_wmb_element_avl_inc,wmb_element_avl_inc} = wmb_element_avl + wmb_element_avl_add - wmb_element_avl_sub; +assign wmb_element_avl_w = layer_st ? 11'b0 : (is_stripe_end & ~wl_group_end & wl_channel_end) ? wmb_element_avl_last : wmb_element_avl_inc; +assign wmb_req_ori_element = wl_weight_size; +assign wmb_req_cycle_element = {1'b0, wl_weight_size}; +assign {mon_wmb_req_element,wmb_req_element} = (wl_cur_sub_h == 2'h0) ? {1'b0, wmb_req_cycle_element} : + (wl_cur_sub_h == 2'h1) ? {1'b0, wmb_req_cycle_element[6:0], 1'b0} : + (wl_cur_sub_h == 2'h2) ? ({wmb_req_cycle_element[6:0], 1'b0} + wmb_req_cycle_element): + {1'b0, wmb_req_cycle_element[5:0], 2'b0}; +assign wmb_req_valid = wmb_pipe_valid & is_compressed_d1 & (wmb_element_avl < {{3{1'b0}}, wmb_req_element}); +assign wmb_element_avl_reg_en = layer_st | (wmb_pipe_valid & is_compressed_d1); +assign wmb_element_avl_last_reg_en = layer_st | (wmb_pipe_valid & is_compressed_d1 & is_stripe_end & wl_group_end); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"wmb_element_avl_reg_en\" -d \"wmb_element_avl_w\" -q wmb_element_avl"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"wmb_element_avl_last_reg_en\" -d \"wmb_element_avl_w\" -q wmb_element_avl_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_element_avl <= {11{1'b0}}; + end else begin + if ((wmb_element_avl_reg_en) == 1'b1) begin + wmb_element_avl <= wmb_element_avl_w; + // VCS coverage off + end else if ((wmb_element_avl_reg_en) == 1'b0) begin + end else begin + wmb_element_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_element_avl_last <= {11{1'b0}}; + end else begin + if ((wmb_element_avl_last_reg_en) == 1'b1) begin + wmb_element_avl_last <= wmb_element_avl_w; + // VCS coverage off + end else if ((wmb_element_avl_last_reg_en) == 1'b0) begin + end else begin + wmb_element_avl_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate wmb read address //////////////////////////////////// +assign {mon_wmb_req_addr_inc,wmb_req_addr_inc} = wmb_req_addr + 1'b1; +assign wmb_req_addr_w = addr_init ? {{14 -9{1'b0}},wmb_entry_st_w} : + (is_stripe_end & wl_channel_end & ~wl_group_end) ? wmb_req_addr_last : + wmb_req_valid ? wmb_req_addr_inc : + wmb_req_addr; +assign wmb_req_addr_reg_en = is_compressed_d1 & (addr_init | wmb_req_valid | (wmb_pipe_valid & is_stripe_end & wl_channel_end)); +assign wmb_req_addr_last_reg_en = is_compressed_d1 & (addr_init | (wmb_pipe_valid & is_stripe_end & wl_group_end)); +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_req_addr_reg_en\" -d \"wmb_req_addr_w\" -q wmb_req_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_req_addr_last_reg_en\" -d \"wmb_req_addr_w\" -q wmb_req_addr_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_addr <= {14{1'b0}}; + end else begin + if ((wmb_req_addr_reg_en) == 1'b1) begin + wmb_req_addr <= wmb_req_addr_w; + // VCS coverage off + end else if ((wmb_req_addr_reg_en) == 1'b0) begin + end else begin + wmb_req_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_addr_last <= {14{1'b0}}; + end else begin + if ((wmb_req_addr_last_reg_en) == 1'b1) begin + wmb_req_addr_last <= wmb_req_addr_w; + // VCS coverage off + end else if ((wmb_req_addr_last_reg_en) == 1'b0) begin + end else begin + wmb_req_addr_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// wmb entries counter for release //////////////////////////////////// +assign wmb_rls_cnt_vld_w = (layer_st | (wl_group_end & is_stripe_end)) ? 1'b0 : (wl_channel_end & is_stripe_end) ? 1'b1 : wmb_rls_cnt_vld; +assign {mon_wmb_rls_cnt_inc,wmb_rls_cnt_inc} = wmb_rls_cnt + 1'b1; +assign wmb_rls_cnt_w = layer_st ? 9'b0 : (is_stripe_end & wl_group_end) ? 9'b0 : wmb_rls_cnt_inc; +assign wmb_rls_cnt_reg_en = layer_st | + (is_compressed_d1 & wmb_pipe_valid & is_stripe_end & wl_group_end) | + (is_compressed_d1 & wmb_req_valid & ~wmb_rls_cnt_vld); +assign wmb_rls_entries = (wmb_rls_cnt_vld | ~wmb_req_valid) ? wmb_rls_cnt : wmb_rls_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_rls_cnt_vld_w\" -q wmb_rls_cnt_vld"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wmb_rls_cnt_reg_en\" -d \"wmb_rls_cnt_w\" -q wmb_rls_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rls_cnt_vld <= 1'b0; + end else begin + wmb_rls_cnt_vld <= wmb_rls_cnt_vld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rls_cnt <= {9{1'b0}}; + end else begin + if ((wmb_rls_cnt_reg_en) == 1'b1) begin + wmb_rls_cnt <= wmb_rls_cnt_w; + // VCS coverage off + end else if ((wmb_rls_cnt_reg_en) == 1'b0) begin + end else begin + wmb_rls_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// send wmb read request //////////////////////////////////// +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_req_valid\" -q sc2buf_wmb_rd_en"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_req_valid\" -d \"wmb_req_addr\" -q sc2buf_wmb_rd_addr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_pipe_valid\" -q wmb_pipe_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wmb_pipe_valid\" -d \"wmb_req_ori_element\" -q wmb_req_ori_element_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"wmb_pipe_valid\" -d \"wmb_req_element\" -q wmb_req_element_d1"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wmb_pipe_valid & wl_wt_release & is_stripe_end\" -d \"wmb_rls_entries\" -q wmb_req_rls_entries_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"is_stripe_end\" -q wmb_req_stripe_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"wl_channel_end & is_stripe_end\" -q wmb_req_channel_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"wl_group_end & is_stripe_end\" -q wmb_req_group_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"wl_wt_release & is_stripe_end\" -q wmb_req_rls_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"wmb_pipe_valid\" -d \"wl_cur_sub_h\" -q wmb_req_cur_sub_h_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_wmb_rd_en <= 1'b0; + end else begin + sc2buf_wmb_rd_en <= wmb_req_valid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_wmb_rd_addr <= {14{1'b0}}; + end else begin + if ((wmb_req_valid) == 1'b1) begin + sc2buf_wmb_rd_addr <= wmb_req_addr; + // VCS coverage off + end else if ((wmb_req_valid) == 1'b0) begin + end else begin + sc2buf_wmb_rd_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_pipe_valid_d1 <= 1'b0; + end else begin + wmb_pipe_valid_d1 <= wmb_pipe_valid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_ori_element_d1 <= {7{1'b0}}; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_ori_element_d1 <= wmb_req_ori_element; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_ori_element_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_element_d1 <= {8{1'b0}}; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_element_d1 <= wmb_req_element; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_element_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_rls_entries_d1 <= {9{1'b0}}; + end else begin + if ((wmb_pipe_valid & wl_wt_release & is_stripe_end) == 1'b1) begin + wmb_req_rls_entries_d1 <= wmb_rls_entries; + // VCS coverage off + end else if ((wmb_pipe_valid & wl_wt_release & is_stripe_end) == 1'b0) begin + end else begin + wmb_req_rls_entries_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_stripe_end_d1 <= 1'b0; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_stripe_end_d1 <= is_stripe_end; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_stripe_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_channel_end_d1 <= 1'b0; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_channel_end_d1 <= wl_channel_end & is_stripe_end; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_channel_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_group_end_d1 <= 1'b0; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_group_end_d1 <= wl_group_end & is_stripe_end; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_group_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_rls_d1 <= 1'b0; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_rls_d1 <= wl_wt_release & is_stripe_end; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_rls_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_req_cur_sub_h_d1 <= {2{1'b0}}; + end else begin + if ((wmb_pipe_valid) == 1'b1) begin + wmb_req_cur_sub_h_d1 <= wl_cur_sub_h; + // VCS coverage off + end else if ((wmb_pipe_valid) == 1'b0) begin + end else begin + wmb_req_cur_sub_h_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// sideband pipeline for wmb read ///// +////////////////////////////////////////////////////////////// +assign wmb_req_pipe_pvld = wmb_pipe_valid_d1; +assign wmb_req_d1_stripe_end = wmb_req_stripe_end_d1; +assign wmb_req_d1_channel_end = wmb_req_channel_end_d1; +assign wmb_req_d1_group_end = wmb_req_group_end_d1; +assign wmb_req_d1_rls = wmb_req_rls_d1; +assign wmb_req_d1_cur_sub_h = wmb_req_cur_sub_h_d1; +assign wmb_req_d1_element = wmb_req_element_d1; +assign wmb_req_d1_ori_element = wmb_req_ori_element_d1; +assign wmb_req_d1_rls_entries = wmb_req_rls_entries_d1; +// PKT_PACK_WIRE( csc_wmb_req_pkg , wmb_req_d1_ , wmb_req_pipe_pd ) +assign wmb_req_pipe_pd[6:0] = wmb_req_d1_ori_element[6:0]; +assign wmb_req_pipe_pd[14:7] = wmb_req_d1_element[7:0]; +assign wmb_req_pipe_pd[23:15] = wmb_req_d1_rls_entries[8:0]; +assign wmb_req_pipe_pd[24] = wmb_req_d1_stripe_end ; +assign wmb_req_pipe_pd[25] = wmb_req_d1_channel_end ; +assign wmb_req_pipe_pd[26] = wmb_req_d1_group_end ; +assign wmb_req_pipe_pd[27] = wmb_req_d1_rls ; +assign wmb_req_pipe_pd[28] = 1'b0 ; +assign wmb_req_pipe_pd[30:29] = wmb_req_d1_cur_sub_h[1:0]; +//: my $pipe_depth = 6; +//: my $i; +//: my $j; +//: if($pipe_depth == 0) { +//: print "assign wmb_rsp_pipe_pvld = wmb_req_pipe_pvld;\n"; +//: print "assign wmb_rsp_pipe_pd = wmb_req_pipe_pd;\n\n"; +//: } else { +//: print "assign wmb_rsp_pipe_pvld_d0 = wmb_req_pipe_pvld;\n"; +//: print "assign wmb_rsp_pipe_pd_d0 = wmb_req_pipe_pd;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"wmb_rsp_pipe_pvld_d${i}\" -q wmb_rsp_pipe_pvld_d${j}"); +//: &eperl::flop("-wid 31 -rval \"{31{1'b0}}\" -en \"wmb_rsp_pipe_pvld_d${i}\" -d \"wmb_rsp_pipe_pd_d${i}\" -q wmb_rsp_pipe_pd_d${j}"); +//: } +//: print "assign wmb_rsp_pipe_pvld = wmb_rsp_pipe_pvld_d${i};\n"; +//: print "assign wmb_rsp_pipe_pd = wmb_rsp_pipe_pd_d${i};\n\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign wmb_rsp_pipe_pvld_d0 = wmb_req_pipe_pvld; +assign wmb_rsp_pipe_pd_d0 = wmb_req_pipe_pd; + +reg wmb_rsp_pipe_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pvld_d1 <= 1'b0; + end else begin + wmb_rsp_pipe_pvld_d1 <= wmb_rsp_pipe_pvld_d0; + end +end +reg [30:0] wmb_rsp_pipe_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pd_d1 <= {31{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld_d0) == 1'b1) begin + wmb_rsp_pipe_pd_d1 <= wmb_rsp_pipe_pd_d0; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld_d0) == 1'b0) begin + end else begin + wmb_rsp_pipe_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg wmb_rsp_pipe_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pvld_d2 <= 1'b0; + end else begin + wmb_rsp_pipe_pvld_d2 <= wmb_rsp_pipe_pvld_d1; + end +end +reg [30:0] wmb_rsp_pipe_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pd_d2 <= {31{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld_d1) == 1'b1) begin + wmb_rsp_pipe_pd_d2 <= wmb_rsp_pipe_pd_d1; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld_d1) == 1'b0) begin + end else begin + wmb_rsp_pipe_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg wmb_rsp_pipe_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pvld_d3 <= 1'b0; + end else begin + wmb_rsp_pipe_pvld_d3 <= wmb_rsp_pipe_pvld_d2; + end +end +reg [30:0] wmb_rsp_pipe_pd_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pd_d3 <= {31{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld_d2) == 1'b1) begin + wmb_rsp_pipe_pd_d3 <= wmb_rsp_pipe_pd_d2; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld_d2) == 1'b0) begin + end else begin + wmb_rsp_pipe_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +reg wmb_rsp_pipe_pvld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pvld_d4 <= 1'b0; + end else begin + wmb_rsp_pipe_pvld_d4 <= wmb_rsp_pipe_pvld_d3; + end +end +reg [30:0] wmb_rsp_pipe_pd_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pd_d4 <= {31{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld_d3) == 1'b1) begin + wmb_rsp_pipe_pd_d4 <= wmb_rsp_pipe_pd_d3; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld_d3) == 1'b0) begin + end else begin + wmb_rsp_pipe_pd_d4 <= 'bx; + // VCS coverage on + end + end +end +reg wmb_rsp_pipe_pvld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pvld_d5 <= 1'b0; + end else begin + wmb_rsp_pipe_pvld_d5 <= wmb_rsp_pipe_pvld_d4; + end +end +reg [30:0] wmb_rsp_pipe_pd_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pd_d5 <= {31{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld_d4) == 1'b1) begin + wmb_rsp_pipe_pd_d5 <= wmb_rsp_pipe_pd_d4; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld_d4) == 1'b0) begin + end else begin + wmb_rsp_pipe_pd_d5 <= 'bx; + // VCS coverage on + end + end +end +reg wmb_rsp_pipe_pvld_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pvld_d6 <= 1'b0; + end else begin + wmb_rsp_pipe_pvld_d6 <= wmb_rsp_pipe_pvld_d5; + end +end +reg [30:0] wmb_rsp_pipe_pd_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_pipe_pd_d6 <= {31{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld_d5) == 1'b1) begin + wmb_rsp_pipe_pd_d6 <= wmb_rsp_pipe_pd_d5; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld_d5) == 1'b0) begin + end else begin + wmb_rsp_pipe_pd_d6 <= 'bx; + // VCS coverage on + end + end +end +assign wmb_rsp_pipe_pvld = wmb_rsp_pipe_pvld_d6; +assign wmb_rsp_pipe_pd = wmb_rsp_pipe_pd_d6; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// wmb data process ///// +////////////////////////////////////////////////////////////// +// PKT_UNPACK_WIRE( csc_wmb_req_pkg , wmb_rsp_ , wmb_rsp_pipe_pd ) +assign wmb_rsp_ori_element[6:0] = wmb_rsp_pipe_pd[6:0]; +assign wmb_rsp_element[7:0] = wmb_rsp_pipe_pd[14:7]; +assign wmb_rsp_rls_entries[8:0] = wmb_rsp_pipe_pd[23:15]; +assign wmb_rsp_stripe_end = wmb_rsp_pipe_pd[24]; +assign wmb_rsp_channel_end = wmb_rsp_pipe_pd[25]; +assign wmb_rsp_group_end = wmb_rsp_pipe_pd[26]; +assign wmb_rsp_rls = wmb_rsp_pipe_pd[27]; +assign wmb_rsp_cur_sub_h[1:0] = wmb_rsp_pipe_pd[30:29]; +//////////////////////////////////// wmb remain counter //////////////////////////////////// +assign wmb_rsp_bit_remain_add = sc2buf_wmb_rd_valid ? 11'h40 : 11'h0; +assign wmb_rsp_bit_remain_sub = wmb_rsp_pipe_pvld ? wmb_rsp_element : 8'b0; +//how many mask bits is stored currently +assign {mon_wmb_rsp_bit_remain_w,wmb_rsp_bit_remain_w} = (layer_st) ? 11'b0 : + (wmb_rsp_channel_end & ~wmb_rsp_group_end) ? {2'b0, wmb_rsp_bit_remain_last} : + wmb_rsp_bit_remain + wmb_rsp_bit_remain_add - wmb_rsp_bit_remain_sub; +assign wmb_rsp_bit_remain_last_reg_en = layer_st | (wmb_rsp_pipe_pvld & wmb_rsp_group_end & is_compressed_d1); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st | (wmb_rsp_pipe_pvld & is_compressed_d1)\" -d \"wmb_rsp_bit_remain_w\" -q wmb_rsp_bit_remain"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"wmb_rsp_bit_remain_last_reg_en\" -d \"wmb_rsp_bit_remain_w\" -q wmb_rsp_bit_remain_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_bit_remain <= {10{1'b0}}; + end else begin + if ((layer_st | (wmb_rsp_pipe_pvld & is_compressed_d1)) == 1'b1) begin + wmb_rsp_bit_remain <= wmb_rsp_bit_remain_w; + // VCS coverage off + end else if ((layer_st | (wmb_rsp_pipe_pvld & is_compressed_d1)) == 1'b0) begin + end else begin + wmb_rsp_bit_remain <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_rsp_bit_remain_last <= {10{1'b0}}; + end else begin + if ((wmb_rsp_bit_remain_last_reg_en) == 1'b1) begin + wmb_rsp_bit_remain_last <= wmb_rsp_bit_remain_w; + // VCS coverage off + end else if ((wmb_rsp_bit_remain_last_reg_en) == 1'b0) begin + end else begin + wmb_rsp_bit_remain_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate element mask for both compressed and compressed case //////////////////////////////////// +//emask for element mask, NOT byte mask +assign wmb_emask_rd_ls = ~sc2buf_wmb_rd_valid ? {8{1'b0}} : (sc2buf_wmb_rd_data[8 -1:0] << wmb_rsp_bit_remain[6:0]); +assign wmb_rsp_emask_in = (wmb_emask_rd_ls | wmb_emask_remain[8 -1:0] | {8{~is_compressed_d1}}); //wmb for current atomic op +assign wmb_rsp_vld_s = ~({8{1'b1}} << wmb_rsp_element); +assign wmb_rsp_emask = wmb_rsp_emask_in[8 -1:0] & wmb_rsp_vld_s; //the mask needed +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_emask\" -q wt_req_emask"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_emask <= {8{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_emask <= wmb_rsp_emask; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_emask <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate local remain masks //////////////////////////////////// +assign {mon_wmb_shift_remain,wmb_shift_remain} = wmb_rsp_element - wmb_rsp_bit_remain[6:0]; +assign wmb_emask_rd_rs = (sc2buf_wmb_rd_data >> wmb_shift_remain); //read 1 entry wmb and be partial used +assign wmb_emask_remain_rs = (wmb_emask_remain >> wmb_rsp_element); //remain wmb and partial used +//all wmb remain, no more than 1 entry +assign wmb_emask_remain_w = layer_st ? {64{1'b0}} : + (wmb_rsp_channel_end & ~wmb_rsp_group_end) ? wmb_emask_remain_last : + sc2buf_wmb_rd_valid ? wmb_emask_rd_rs : + wmb_emask_remain_rs; +assign wmb_emask_remain_reg_en = layer_st | (wmb_rsp_pipe_pvld & is_compressed_d1); +assign wmb_emask_remain_last_reg_en = layer_st | (wmb_rsp_pipe_pvld & wmb_rsp_group_end & is_compressed_d1); +assign wmb_rsp_ori_sft_3 = {wmb_rsp_ori_element[4:0], 1'b0} + wmb_rsp_ori_element[4:0]; +//: my $kk=64; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_emask_remain_reg_en\" -d \"wmb_emask_remain_w\" -q wmb_emask_remain"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_emask_remain_last_reg_en\" -d \"wmb_emask_remain_w\" -q wmb_emask_remain_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_emask_remain <= {64{1'b0}}; + end else begin + if ((wmb_emask_remain_reg_en) == 1'b1) begin + wmb_emask_remain <= wmb_emask_remain_w; + // VCS coverage off + end else if ((wmb_emask_remain_reg_en) == 1'b0) begin + end else begin + wmb_emask_remain <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wmb_emask_remain_last <= {64{1'b0}}; + end else begin + if ((wmb_emask_remain_last_reg_en) == 1'b1) begin + wmb_emask_remain_last <= wmb_emask_remain_w; + // VCS coverage off + end else if ((wmb_emask_remain_last_reg_en) == 1'b0) begin + end else begin + wmb_emask_remain_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// registers for pipeline //////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_rsp_pipe_pvld\" -q wt_req_pipe_valid"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_ori_element\" -q wt_req_ori_element"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_stripe_end\" -q wt_req_stripe_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_channel_end\" -q wt_req_channel_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_group_end\" -q wt_req_group_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_rls\" -q wt_req_rls"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_rls_entries\" -q wt_req_wmb_rls_entries"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_cur_sub_h\" -q wt_req_cur_sub_h"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_ori_sft_3\" -q wt_req_ori_sft_3"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_pipe_valid <= 1'b0; + end else begin + wt_req_pipe_valid <= wmb_rsp_pipe_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_ori_element <= {7{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_ori_element <= wmb_rsp_ori_element; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_ori_element <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_stripe_end <= 1'b0; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_stripe_end <= wmb_rsp_stripe_end; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_stripe_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_channel_end <= 1'b0; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_channel_end <= wmb_rsp_channel_end; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_channel_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_group_end <= 1'b0; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_group_end <= wmb_rsp_group_end; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_group_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_rls <= 1'b0; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_rls <= wmb_rsp_rls; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_rls <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_wmb_rls_entries <= {9{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_wmb_rls_entries <= wmb_rsp_rls_entries; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_wmb_rls_entries <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_cur_sub_h <= {2{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_cur_sub_h <= wmb_rsp_cur_sub_h; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_cur_sub_h <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_ori_sft_3 <= {7{1'b0}}; + end else begin + if ((wmb_rsp_pipe_pvld) == 1'b1) begin + wt_req_ori_sft_3 <= wmb_rsp_ori_sft_3; + // VCS coverage off + end else if ((wmb_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_req_ori_sft_3 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// weight data request generate ///// +////////////////////////////////////////////////////////////// +//////////////////////////////////// generate mask sum //////////////////////////////////// +////CAUSION! wt_req_bmask is byte mask, not elemnet mask!//// +assign wt_req_bmask = wt_req_emask; +//: print "assign wt_req_bytes = \n"; +//: my $j=int(8/4); +//: for(my $i=0; $i<$j; $i++){ +//: print "wt_req_bmask[4*${i}+0] + wt_req_bmask[4*${i}+1] + wt_req_bmask[4*${i}+2] + wt_req_bmask[4*${i}+3] + \n"; +//: } +//: print "1'b0; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign wt_req_bytes = +wt_req_bmask[4*0+0] + wt_req_bmask[4*0+1] + wt_req_bmask[4*0+2] + wt_req_bmask[4*0+3] + +wt_req_bmask[4*1+0] + wt_req_bmask[4*1+1] + wt_req_bmask[4*1+2] + wt_req_bmask[4*1+3] + +1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate element mask for decoding//////////////////////////////////// +//valid bit for each sub h line +assign wt_req_vld_bit = ~({8{1'b1}} << wt_req_ori_element); +//valid bit to select sub h line +//: my $kk=8; +//: print qq( +//: assign sub_h_mask_1 = (wt_req_cur_sub_h >= 2'h1) ? {${kk}{1'b1}} : {${kk}{1'h0}}; +//: assign sub_h_mask_2 = (wt_req_cur_sub_h >= 2'h2) ? {${kk}{1'b1}} : {${kk}{1'h0}}; +//: assign sub_h_mask_3 = (wt_req_cur_sub_h == 2'h3) ? {${kk}{1'b1}} : {${kk}{1'h0}}; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign sub_h_mask_1 = (wt_req_cur_sub_h >= 2'h1) ? {8{1'b1}} : {8{1'h0}}; +assign sub_h_mask_2 = (wt_req_cur_sub_h >= 2'h2) ? {8{1'b1}} : {8{1'h0}}; +assign sub_h_mask_3 = (wt_req_cur_sub_h == 2'h3) ? {8{1'b1}} : {8{1'h0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//element number to be shifted +assign wt_req_ori_sft_1 = wt_req_ori_element; +assign wt_req_ori_sft_2 = {wt_req_ori_element[5:0], 1'b0}; +assign wt_req_emask_p0 = wt_req_emask[8 -1:0] & wt_req_vld_bit; +assign wt_req_emask_p1 = (wt_req_emask[8 -1:0] >> wt_req_ori_sft_1) & wt_req_vld_bit & sub_h_mask_1; +assign wt_req_emask_p2 = (wt_req_emask[8 -1:0] >> wt_req_ori_sft_2) & wt_req_vld_bit & sub_h_mask_2; +assign wt_req_emask_p3 = (wt_req_emask[8 -1:0] >> wt_req_ori_sft_3) & wt_req_vld_bit & sub_h_mask_3; +//Caution! Must reset wt_req_mask to all zero when layer started +//other width wt_req_mask_en may gate wt_rsp_mask_d1_w improperly! +assign wt_req_mask_w = layer_st ? {8{1'b0}} : + (sub_h_total == 3'h1) ? {wt_req_emask_p0} : + (sub_h_total == 3'h2) ? {wt_req_emask_p1[8/2-1:0], wt_req_emask_p0[8/2-1:0]} : + {wt_req_emask_p3[8/4-1:0], wt_req_emask_p2[8/4-1:0], wt_req_emask_p1[8/4-1:0], wt_req_emask_p0[8/4-1:0]}; +//assign wt_req_mask_w = layer_st ? {8{1'b0}} : wt_req_emask_p0; //need update for image +assign wt_req_mask_en = wt_req_pipe_valid & (wt_req_mask_w != wt_req_mask_d1); +//////////////////////////////////// generate weight read request //////////////////////////////////// +assign wt_req_valid = wt_req_pipe_valid & (wt_byte_avl < wt_req_bytes); +//////////////////////////////////// generate weight avaliable bytes //////////////////////////////////// +assign wt_byte_avl_add = ~wt_req_valid ? 8'b0 : 7'h8; +assign wt_byte_avl_sub = wt_req_bytes; +assign {mon_wt_byte_avl_inc,wt_byte_avl_inc} = wt_byte_avl + wt_byte_avl_add - wt_byte_avl_sub; +assign wt_byte_avl_w = layer_st ? 8'b0 : ( ~wt_req_group_end & wt_req_channel_end) ? wt_byte_avl_last : wt_byte_avl_inc; +assign wt_byte_last_reg_en = layer_st | (wt_req_pipe_valid & wt_req_stripe_end & wt_req_group_end); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"layer_st | wt_req_pipe_valid\" -d \"wt_byte_avl_w\" -q wt_byte_avl"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"wt_byte_last_reg_en\" -d \"wt_byte_avl_w\" -q wt_byte_avl_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_byte_avl <= {8{1'b0}}; + end else begin + if ((layer_st | wt_req_pipe_valid) == 1'b1) begin + wt_byte_avl <= wt_byte_avl_w; + // VCS coverage off + end else if ((layer_st | wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_byte_avl <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_byte_avl_last <= {8{1'b0}}; + end else begin + if ((wt_byte_last_reg_en) == 1'b1) begin + wt_byte_avl_last <= wt_byte_avl_w; + // VCS coverage off + end else if ((wt_byte_last_reg_en) == 1'b0) begin + end else begin + wt_byte_avl_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate weight read address //////////////////////////////////// +assign {mon_wt_req_addr_inc,wt_req_addr_inc} = wt_req_addr + 1'b1; +assign is_wr_req_addr_wrap = (wt_req_addr_inc == {weight_bank, {9{1'b0}}}); +assign wt_req_addr_inc_wrap = is_wr_req_addr_wrap ? {14{1'b0}} : wt_req_addr_inc; +assign wt_req_addr_w = addr_init ? wt_entry_st_w[14 -1:0] : + (wt_req_channel_end & ~wt_req_group_end) ? wt_req_addr_last : + wt_req_valid ? wt_req_addr_inc_wrap : + wt_req_addr; +assign wt_req_addr_reg_en = addr_init | wt_req_valid | (wt_req_pipe_valid & wt_req_channel_end); +assign wt_req_addr_last_reg_en = addr_init | (wt_req_pipe_valid & wt_req_pipe_valid & wt_req_group_end); +assign {mon_wt_req_addr_out,wt_req_addr_out} = wt_req_addr + {data_bank, {9{1'b0}}}; +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_req_addr_reg_en\" -d \"wt_req_addr_w\" -q wt_req_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_req_addr_last_reg_en\" -d \"wt_req_addr_w\" -q wt_req_addr_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_addr <= {14{1'b0}}; + end else begin + if ((wt_req_addr_reg_en) == 1'b1) begin + wt_req_addr <= wt_req_addr_w; + // VCS coverage off + end else if ((wt_req_addr_reg_en) == 1'b0) begin + end else begin + wt_req_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_addr_last <= {14{1'b0}}; + end else begin + if ((wt_req_addr_last_reg_en) == 1'b1) begin + wt_req_addr_last <= wt_req_addr_w; + // VCS coverage off + end else if ((wt_req_addr_last_reg_en) == 1'b0) begin + end else begin + wt_req_addr_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// weight entries counter for release //////////////////////////////////// +assign wt_rls_cnt_vld_w = (layer_st | wt_req_group_end) ? 1'b0 : wt_req_channel_end ? 1'b1 : wt_rls_cnt_vld; +assign {mon_wt_rls_cnt_inc,wt_rls_cnt_inc} = wt_rls_cnt + 1'b1; +assign wt_rls_cnt_w = layer_st ? {15{1'b0}} : wt_req_group_end ? {15{1'b0}} : wt_rls_cnt_inc; +assign wt_rls_cnt_reg_en = layer_st | (wt_req_pipe_valid & wt_req_group_end) | (~wt_rls_cnt_vld & wt_req_valid); +assign wt_rls_entries = (wt_rls_cnt_vld | ~wt_req_valid) ? wt_rls_cnt : wt_rls_cnt_inc; +//: my $kk=15; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_rls_cnt_vld_w\" -q wt_rls_cnt_vld"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rls_cnt_reg_en\" -d \"wt_rls_cnt_w\" -q wt_rls_cnt"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rls_cnt_vld <= 1'b0; + end else begin + wt_rls_cnt_vld <= wt_rls_cnt_vld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rls_cnt <= {15{1'b0}}; + end else begin + if ((wt_rls_cnt_reg_en) == 1'b1) begin + wt_rls_cnt <= wt_rls_cnt_w; + // VCS coverage off + end else if ((wt_rls_cnt_reg_en) == 1'b0) begin + end else begin + wt_rls_cnt <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// send weight read request //////////////////////////////////// +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_valid\" -q sc2buf_wt_rd_en"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_req_valid\" -d \"wt_req_addr_out\" -q sc2buf_wt_rd_addr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_pipe_valid\" -q wt_req_pipe_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_stripe_end\" -q wt_req_stripe_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_channel_end\" -q wt_req_channel_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_group_end\" -q wt_req_group_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_rls\" -q wt_req_rls_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"wt_req_pipe_valid\" -d \"wt_req_bytes\" -q wt_req_bytes_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_wt_rd_en <= 1'b0; + end else begin + sc2buf_wt_rd_en <= wt_req_valid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2buf_wt_rd_addr <= {14{1'b0}}; + end else begin + if ((wt_req_valid) == 1'b1) begin + sc2buf_wt_rd_addr <= wt_req_addr_out; + // VCS coverage off + end else if ((wt_req_valid) == 1'b0) begin + end else begin + sc2buf_wt_rd_addr <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_pipe_valid_d1 <= 1'b0; + end else begin + wt_req_pipe_valid_d1 <= wt_req_pipe_valid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_stripe_end_d1 <= 1'b0; + end else begin + if ((wt_req_pipe_valid) == 1'b1) begin + wt_req_stripe_end_d1 <= wt_req_stripe_end; + // VCS coverage off + end else if ((wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_stripe_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_channel_end_d1 <= 1'b0; + end else begin + if ((wt_req_pipe_valid) == 1'b1) begin + wt_req_channel_end_d1 <= wt_req_channel_end; + // VCS coverage off + end else if ((wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_channel_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_group_end_d1 <= 1'b0; + end else begin + if ((wt_req_pipe_valid) == 1'b1) begin + wt_req_group_end_d1 <= wt_req_group_end; + // VCS coverage off + end else if ((wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_group_end_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_rls_d1 <= 1'b0; + end else begin + if ((wt_req_pipe_valid) == 1'b1) begin + wt_req_rls_d1 <= wt_req_rls; + // VCS coverage off + end else if ((wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_rls_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_bytes_d1 <= {8{1'b0}}; + end else begin + if ((wt_req_pipe_valid) == 1'b1) begin + wt_req_bytes_d1 <= wt_req_bytes; + // VCS coverage off + end else if ((wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_bytes_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//Caution! Here wt_req_mask is still element mask +//: my $kk=8; +//: my $jj=15; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st | wt_req_pipe_valid\" -d \"wt_req_mask_w\" -q wt_req_mask_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_mask_en\" -q wt_req_mask_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wt_req_pipe_valid\" -d \"wt_req_wmb_rls_entries\" -q wt_req_wmb_rls_entries_d1"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"wt_req_pipe_valid & wt_req_rls\" -d \"wt_rls_entries\" -q wt_req_wt_rls_entries_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_mask_d1 <= {8{1'b0}}; + end else begin + if ((layer_st | wt_req_pipe_valid) == 1'b1) begin + wt_req_mask_d1 <= wt_req_mask_w; + // VCS coverage off + end else if ((layer_st | wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_mask_en_d1 <= 1'b0; + end else begin + wt_req_mask_en_d1 <= wt_req_mask_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_wmb_rls_entries_d1 <= {9{1'b0}}; + end else begin + if ((wt_req_pipe_valid) == 1'b1) begin + wt_req_wmb_rls_entries_d1 <= wt_req_wmb_rls_entries; + // VCS coverage off + end else if ((wt_req_pipe_valid) == 1'b0) begin + end else begin + wt_req_wmb_rls_entries_d1 <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_req_wt_rls_entries_d1 <= {15{1'b0}}; + end else begin + if ((wt_req_pipe_valid & wt_req_rls) == 1'b1) begin + wt_req_wt_rls_entries_d1 <= wt_rls_entries; + // VCS coverage off + end else if ((wt_req_pipe_valid & wt_req_rls) == 1'b0) begin + end else begin + wt_req_wt_rls_entries_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// sideband pipeline for wmb read ///// +////////////////////////////////////////////////////////////// +assign wt_req_pipe_pvld = wt_req_pipe_valid_d1; +assign wt_req_d1_stripe_end = wt_req_stripe_end_d1; +assign wt_req_d1_channel_end = wt_req_channel_end_d1; +assign wt_req_d1_group_end = wt_req_group_end_d1; +assign wt_req_d1_rls = wt_req_rls_d1; +assign wt_req_d1_bytes = wt_req_bytes_d1; +assign wt_req_d1_wmb_rls_entries = wt_req_wmb_rls_entries_d1; +assign wt_req_d1_wt_rls_entries = wt_req_wt_rls_entries_d1; +// PKT_PACK_WIRE( csc_wt_req_pkg , wt_req_d1_ , wt_req_pipe_pd ) +assign wt_req_pipe_pd[7:0] = wt_req_d1_bytes[7:0]; +assign wt_req_pipe_pd[16:8] = wt_req_d1_wmb_rls_entries[8:0]; +assign wt_req_pipe_pd[31:17] = wt_req_d1_wt_rls_entries[14:0]; +assign wt_req_pipe_pd[32] = wt_req_d1_stripe_end ; +assign wt_req_pipe_pd[33] = wt_req_d1_channel_end ; +assign wt_req_pipe_pd[34] = wt_req_d1_group_end ; +assign wt_req_pipe_pd[35] = wt_req_d1_rls ; +//: my $pipe_depth = 6; +//: my $i; +//: my $j; +//: my $kk=8; +//: if($pipe_depth == 0) { +//: print "assign wt_rsp_pipe_pvld = wt_req_pipe_pvld;\n"; +//: print "assign wt_rsp_pipe_pd = wt_req_pipe_pd;\n"; +//: print "assign wt_rsp_mask_en = wt_req_mask_en_d1;\n"; +//: print "assign wt_rsp_mask = wt_req_mask_d1;\n\n\n\n"; +//: } else { +//: print "assign wt_rsp_pipe_pvld_d0 = wt_req_pipe_pvld;\n"; +//: print "assign wt_rsp_pipe_pd_d0 = wt_req_pipe_pd;\n"; +//: print "assign wt_rsp_mask_en_d0 = wt_req_mask_en_d1;\n"; +//: print "assign wt_rsp_mask_d0 = wt_req_mask_d1;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"wt_rsp_pipe_pvld_d${i}\" -q wt_rsp_pipe_pvld_d${j}"); +//: &eperl::flop("-wid 36 -rval \"{36{1'b0}}\" -en \"wt_rsp_pipe_pvld_d${i}\" -d \"wt_rsp_pipe_pd_d${i}\" -q wt_rsp_pipe_pd_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"wt_rsp_mask_en_d${i}\" -q wt_rsp_mask_en_d${j}"); +//: &eperl::flop("-wid ${kk} -rval \"{${kk}{1'b0}}\" -en \"wt_rsp_mask_en_d${i}\" -d \"wt_rsp_mask_d${i}\" -q wt_rsp_mask_d${j}"); +//: } +//: print "assign wt_rsp_pipe_pvld = wt_rsp_pipe_pvld_d${i};\n"; +//: print "assign wt_rsp_pipe_pd = wt_rsp_pipe_pd_d${i};\n\n"; +//: print "assign wt_rsp_mask_en = wt_rsp_mask_en_d${i};\n"; +//: print "assign wt_rsp_mask = wt_rsp_mask_d${i};\n\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign wt_rsp_pipe_pvld_d0 = wt_req_pipe_pvld; +assign wt_rsp_pipe_pd_d0 = wt_req_pipe_pd; +assign wt_rsp_mask_en_d0 = wt_req_mask_en_d1; +assign wt_rsp_mask_d0 = wt_req_mask_d1; + +reg wt_rsp_pipe_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pvld_d1 <= 1'b0; + end else begin + wt_rsp_pipe_pvld_d1 <= wt_rsp_pipe_pvld_d0; + end +end +reg [35:0] wt_rsp_pipe_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pd_d1 <= {36{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld_d0) == 1'b1) begin + wt_rsp_pipe_pd_d1 <= wt_rsp_pipe_pd_d0; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld_d0) == 1'b0) begin + end else begin + wt_rsp_pipe_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_mask_en_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_en_d1 <= 1'b0; + end else begin + wt_rsp_mask_en_d1 <= wt_rsp_mask_en_d0; + end +end +reg [7:0] wt_rsp_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_d1 <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en_d0) == 1'b1) begin + wt_rsp_mask_d1 <= wt_rsp_mask_d0; + // VCS coverage off + end else if ((wt_rsp_mask_en_d0) == 1'b0) begin + end else begin + wt_rsp_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_pipe_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pvld_d2 <= 1'b0; + end else begin + wt_rsp_pipe_pvld_d2 <= wt_rsp_pipe_pvld_d1; + end +end +reg [35:0] wt_rsp_pipe_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pd_d2 <= {36{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld_d1) == 1'b1) begin + wt_rsp_pipe_pd_d2 <= wt_rsp_pipe_pd_d1; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld_d1) == 1'b0) begin + end else begin + wt_rsp_pipe_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_mask_en_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_en_d2 <= 1'b0; + end else begin + wt_rsp_mask_en_d2 <= wt_rsp_mask_en_d1; + end +end +reg [7:0] wt_rsp_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_d2 <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en_d1) == 1'b1) begin + wt_rsp_mask_d2 <= wt_rsp_mask_d1; + // VCS coverage off + end else if ((wt_rsp_mask_en_d1) == 1'b0) begin + end else begin + wt_rsp_mask_d2 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_pipe_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pvld_d3 <= 1'b0; + end else begin + wt_rsp_pipe_pvld_d3 <= wt_rsp_pipe_pvld_d2; + end +end +reg [35:0] wt_rsp_pipe_pd_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pd_d3 <= {36{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld_d2) == 1'b1) begin + wt_rsp_pipe_pd_d3 <= wt_rsp_pipe_pd_d2; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld_d2) == 1'b0) begin + end else begin + wt_rsp_pipe_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_mask_en_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_en_d3 <= 1'b0; + end else begin + wt_rsp_mask_en_d3 <= wt_rsp_mask_en_d2; + end +end +reg [7:0] wt_rsp_mask_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_d3 <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en_d2) == 1'b1) begin + wt_rsp_mask_d3 <= wt_rsp_mask_d2; + // VCS coverage off + end else if ((wt_rsp_mask_en_d2) == 1'b0) begin + end else begin + wt_rsp_mask_d3 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_pipe_pvld_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pvld_d4 <= 1'b0; + end else begin + wt_rsp_pipe_pvld_d4 <= wt_rsp_pipe_pvld_d3; + end +end +reg [35:0] wt_rsp_pipe_pd_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pd_d4 <= {36{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld_d3) == 1'b1) begin + wt_rsp_pipe_pd_d4 <= wt_rsp_pipe_pd_d3; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld_d3) == 1'b0) begin + end else begin + wt_rsp_pipe_pd_d4 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_mask_en_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_en_d4 <= 1'b0; + end else begin + wt_rsp_mask_en_d4 <= wt_rsp_mask_en_d3; + end +end +reg [7:0] wt_rsp_mask_d4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_d4 <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en_d3) == 1'b1) begin + wt_rsp_mask_d4 <= wt_rsp_mask_d3; + // VCS coverage off + end else if ((wt_rsp_mask_en_d3) == 1'b0) begin + end else begin + wt_rsp_mask_d4 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_pipe_pvld_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pvld_d5 <= 1'b0; + end else begin + wt_rsp_pipe_pvld_d5 <= wt_rsp_pipe_pvld_d4; + end +end +reg [35:0] wt_rsp_pipe_pd_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pd_d5 <= {36{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld_d4) == 1'b1) begin + wt_rsp_pipe_pd_d5 <= wt_rsp_pipe_pd_d4; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld_d4) == 1'b0) begin + end else begin + wt_rsp_pipe_pd_d5 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_mask_en_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_en_d5 <= 1'b0; + end else begin + wt_rsp_mask_en_d5 <= wt_rsp_mask_en_d4; + end +end +reg [7:0] wt_rsp_mask_d5; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_d5 <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en_d4) == 1'b1) begin + wt_rsp_mask_d5 <= wt_rsp_mask_d4; + // VCS coverage off + end else if ((wt_rsp_mask_en_d4) == 1'b0) begin + end else begin + wt_rsp_mask_d5 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_pipe_pvld_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pvld_d6 <= 1'b0; + end else begin + wt_rsp_pipe_pvld_d6 <= wt_rsp_pipe_pvld_d5; + end +end +reg [35:0] wt_rsp_pipe_pd_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_pipe_pd_d6 <= {36{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld_d5) == 1'b1) begin + wt_rsp_pipe_pd_d6 <= wt_rsp_pipe_pd_d5; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld_d5) == 1'b0) begin + end else begin + wt_rsp_pipe_pd_d6 <= 'bx; + // VCS coverage on + end + end +end +reg wt_rsp_mask_en_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_en_d6 <= 1'b0; + end else begin + wt_rsp_mask_en_d6 <= wt_rsp_mask_en_d5; + end +end +reg [7:0] wt_rsp_mask_d6; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_mask_d6 <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en_d5) == 1'b1) begin + wt_rsp_mask_d6 <= wt_rsp_mask_d5; + // VCS coverage off + end else if ((wt_rsp_mask_en_d5) == 1'b0) begin + end else begin + wt_rsp_mask_d6 <= 'bx; + // VCS coverage on + end + end +end +assign wt_rsp_pipe_pvld = wt_rsp_pipe_pvld_d6; +assign wt_rsp_pipe_pd = wt_rsp_pipe_pd_d6; + +assign wt_rsp_mask_en = wt_rsp_mask_en_d6; +assign wt_rsp_mask = wt_rsp_mask_d6; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////// +///// weight data process ///// +////////////////////////////////////////////////////////////// +// PKT_UNPACK_WIRE( csc_wt_req_pkg , wt_rsp_ , wt_rsp_pipe_pd ) +assign wt_rsp_bytes[7:0] = wt_rsp_pipe_pd[7:0]; +assign wt_rsp_wmb_rls_entries[8:0] = wt_rsp_pipe_pd[16:8]; +assign wt_rsp_wt_rls_entries[14:0] = wt_rsp_pipe_pd[31:17]; +assign wt_rsp_stripe_end = wt_rsp_pipe_pd[32]; +assign wt_rsp_channel_end = wt_rsp_pipe_pd[33]; +assign wt_rsp_group_end = wt_rsp_pipe_pd[34]; +assign wt_rsp_rls = wt_rsp_pipe_pd[35]; +//////////////////////////////////// generate byte mask for decoding //////////////////////////////////// +assign wt_rsp_mask_d1_w = wt_rsp_mask ; +//////////////////////////////////// weight remain counter //////////////////////////////////// +assign wt_rsp_byte_remain_add = sc2buf_wt_rd_valid ? 7'h8 : 8'h0; +assign {mon_wt_rsp_byte_remain_w,wt_rsp_byte_remain_w} = (layer_st) ? 8'b0 : + (wt_rsp_channel_end & ~wt_rsp_group_end) ? {2'b0, wt_rsp_byte_remain_last} : + wt_rsp_byte_remain + wt_rsp_byte_remain_add - wt_rsp_bytes; +assign wt_rsp_byte_remain_en = layer_st | wt_rsp_pipe_pvld; +assign wt_rsp_byte_remain_last_en = layer_st | (wt_rsp_pipe_pvld & wt_rsp_group_end); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_rsp_byte_remain_en\" -d \"wt_rsp_byte_remain_w\" -q wt_rsp_byte_remain"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_rsp_byte_remain_last_en\" -d \"wt_rsp_byte_remain_w\" -q wt_rsp_byte_remain_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_byte_remain <= {7{1'b0}}; + end else begin + if ((wt_rsp_byte_remain_en) == 1'b1) begin + wt_rsp_byte_remain <= wt_rsp_byte_remain_w; + // VCS coverage off + end else if ((wt_rsp_byte_remain_en) == 1'b0) begin + end else begin + wt_rsp_byte_remain <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_byte_remain_last <= {7{1'b0}}; + end else begin + if ((wt_rsp_byte_remain_last_en) == 1'b1) begin + wt_rsp_byte_remain_last <= wt_rsp_byte_remain_w; + // VCS coverage off + end else if ((wt_rsp_byte_remain_last_en) == 1'b0) begin + end else begin + wt_rsp_byte_remain_last <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate local remain bytes //////////////////////////////////// +assign {mon_wt_shift_remain,wt_shift_remain} = wt_rsp_bytes - wt_rsp_byte_remain[6:0]; +assign wt_data_input_rs = (sc2buf_wt_rd_data[64 -1:0] >> {wt_shift_remain, 3'b0}); +assign wt_data_remain_masked = ~(|wt_rsp_byte_remain) ? {64{1'b0}}: wt_data_remain; +assign wt_data_remain_rs = (wt_data_remain >> {wt_rsp_bytes, 3'b0}); +//weight data local remain, 1 entry at most +assign wt_data_remain_w = layer_st ? {64{1'b0}} : + (wt_rsp_channel_end & ~wt_rsp_group_end & (|wt_rsp_byte_remain_last)) ? wt_data_remain_last : + sc2buf_wt_rd_valid ? wt_data_input_rs : + wt_data_remain_rs; +assign wt_data_remain_reg_en = layer_st | (wt_rsp_pipe_pvld & (|wt_rsp_byte_remain_w)); +assign wt_data_remain_last_reg_en = layer_st | (wt_rsp_pipe_pvld & wt_rsp_group_end & (|wt_rsp_byte_remain_w)); +assign wt_data_input_ls = (sc2buf_wt_rd_data << {wt_rsp_byte_remain[6:0], 3'b0}); +assign wt_data_input_sft = (sc2buf_wt_rd_valid) ? wt_data_input_ls : {64{1'b0}}; +//: &eperl::flop("-nodeclare -norst -en \"wt_data_remain_reg_en\" -d \"wt_data_remain_w\" -q wt_data_remain"); +//: &eperl::flop("-nodeclare -norst -en \"wt_data_remain_last_reg_en\" -d \"wt_data_remain_w\" -q wt_data_remain_last"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk) begin + if ((wt_data_remain_reg_en) == 1'b1) begin + wt_data_remain <= wt_data_remain_w; + // VCS coverage off + end else if ((wt_data_remain_reg_en) == 1'b0) begin + end else begin + wt_data_remain <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((wt_data_remain_last_reg_en) == 1'b1) begin + wt_data_remain_last <= wt_data_remain_w; + // VCS coverage off + end else if ((wt_data_remain_last_reg_en) == 1'b0) begin + end else begin + wt_data_remain_last <= 'bx; + // VCS coverage on + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate bytes for decoding //////////////////////////////////// +assign wt_rsp_data = (wt_data_input_sft | wt_data_remain_masked); +//: my $kk=64; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rsp_pipe_pvld\" -d \"wt_rsp_data\" -q dec_input_data"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dec_input_data <= {64{1'b0}}; + end else begin + if ((wt_rsp_pipe_pvld) == 1'b1) begin + dec_input_data <= wt_rsp_data; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld) == 1'b0) begin + end else begin + dec_input_data <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//////////////////////////////////// generate select signal //////////////////////////////////// +assign wt_rsp_sel_w = wt_rsp_last_stripe_end ? {{(8 -1){1'h0}},1'h1} : {wt_rsp_sel_d1[8 -2:0], wt_rsp_sel_d1[8 -1]}; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"wt_rsp_pipe_pvld\" -d \"wt_rsp_stripe_end\" -q wt_rsp_last_stripe_end"); +//: &eperl::flop("-nodeclare -rval \"'h1\" -en \"wt_rsp_pipe_pvld\" -d \"wt_rsp_sel_w\" -q wt_rsp_sel_d1"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_last_stripe_end <= 1'b1; + end else begin + if ((wt_rsp_pipe_pvld) == 1'b1) begin + wt_rsp_last_stripe_end <= wt_rsp_stripe_end; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_rsp_last_stripe_end <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wt_rsp_sel_d1 <= 'h1; + end else begin + if ((wt_rsp_pipe_pvld) == 1'b1) begin + wt_rsp_sel_d1 <= wt_rsp_sel_w; + // VCS coverage off + end else if ((wt_rsp_pipe_pvld) == 1'b0) begin + end else begin + wt_rsp_sel_d1 <= 'bx; + // VCS coverage on + end + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dec_input_sel = wt_rsp_sel_d1; +//////////////////////////////////// prepare other signals //////////////////////////////////// +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_rsp_pipe_pvld\" -q dec_input_pipe_valid"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rsp_mask_en\" -d \"wt_rsp_mask_d1_w\" -q dec_input_mask"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -d \"{10{wt_rsp_mask_en}}\" -q dec_input_mask_en"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dec_input_pipe_valid <= 1'b0; + end else begin + dec_input_pipe_valid <= wt_rsp_pipe_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dec_input_mask <= {8{1'b0}}; + end else begin + if ((wt_rsp_mask_en) == 1'b1) begin + dec_input_mask <= wt_rsp_mask_d1_w; + // VCS coverage off + end else if ((wt_rsp_mask_en) == 1'b0) begin + end else begin + dec_input_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dec_input_mask_en <= {10{1'b0}}; + end else begin + dec_input_mask_en <= {10{wt_rsp_mask_en}}; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_CSC_WL_dec u_dec ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.input_data (dec_input_data[8*8 -1:0]) //|< r + ,.input_mask (dec_input_mask[8 -1:0]) //|< r + ,.input_mask_en (dec_input_mask_en[9:0]) //|< r + ,.input_pipe_valid (dec_input_pipe_valid) //|< r + ,.input_sel (dec_input_sel[8 -1:0]) //|< w +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(,.output_data${i} (sc2mac_out_data${i}) //|> w\n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.output_data0 (sc2mac_out_data0) //|> w +,.output_data1 (sc2mac_out_data1) //|> w +,.output_data2 (sc2mac_out_data2) //|> w +,.output_data3 (sc2mac_out_data3) //|> w +,.output_data4 (sc2mac_out_data4) //|> w +,.output_data5 (sc2mac_out_data5) //|> w +,.output_data6 (sc2mac_out_data6) //|> w +,.output_data7 (sc2mac_out_data7) //|> w + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.output_mask (sc2mac_out_mask[8 -1:0]) //|> w + ,.output_pvld (sc2mac_out_pvld) //|> w + ,.output_sel (sc2mac_out_sel[8 -1:0]) //|> w + ,.is_fp16 (1'b0) //|< i + ,.is_int8 (1'b1) //|< i + ); +////////////////////////////////////////////////////////////// +///// registers for retiming ///// +////////////////////////////////////////////////////////////// +assign sc2mac_out_a_sel_w = {8/2{sc2mac_out_pvld}} & sc2mac_out_sel[8/2 -1:0]; +assign sc2mac_out_b_sel_w = {8/2{sc2mac_out_pvld}} & sc2mac_out_sel[8 -1:8/2]; +assign sc2mac_wt_a_pvld_w = (|sc2mac_out_a_sel_w); +assign sc2mac_wt_b_pvld_w = (|sc2mac_out_b_sel_w); +assign sc2mac_out_a_mask = sc2mac_out_mask & {8{sc2mac_wt_a_pvld_w}}; +assign sc2mac_out_b_mask = sc2mac_out_mask & {8{sc2mac_wt_b_pvld_w}}; +//: my $kk=8; +//: my $jj=8/2; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2mac_wt_a_pvld_w\" -q sc2mac_wt_a_pvld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2mac_wt_b_pvld_w\" -q sc2mac_wt_b_pvld"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld\" -d \"sc2mac_out_a_mask\" -q sc2mac_wt_a_mask"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld\" -d \"sc2mac_out_b_mask\" -q sc2mac_wt_b_mask"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld\" -d \"sc2mac_out_a_sel_w\" -q sc2mac_wt_a_sel"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld\" -d \"sc2mac_out_b_sel_w\" -q sc2mac_wt_b_sel"); +//: for(my $i = 0; $i < 8; $i ++) { +//: &eperl::flop("-nodeclare -norst -en \"sc2mac_out_a_mask[${i}]\" -d \"sc2mac_out_data${i}\" -q sc2mac_wt_a_data${i}"); +//: } +//: print "\n\n"; +//: +//: for(my $i = 0; $i < 8; $i ++) { +//: &eperl::flop("-nodeclare -norst -en \"sc2mac_out_b_mask[${i}]\" -d \"sc2mac_out_data${i}\" -q sc2mac_wt_b_data${i}"); +//: } +//: print "\n\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_a_pvld <= 1'b0; + end else begin + sc2mac_wt_a_pvld <= sc2mac_wt_a_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_b_pvld <= 1'b0; + end else begin + sc2mac_wt_b_pvld <= sc2mac_wt_b_pvld_w; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_a_mask <= {8{1'b0}}; + end else begin + if ((sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld) == 1'b1) begin + sc2mac_wt_a_mask <= sc2mac_out_a_mask; + // VCS coverage off + end else if ((sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld) == 1'b0) begin + end else begin + sc2mac_wt_a_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_b_mask <= {8{1'b0}}; + end else begin + if ((sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld) == 1'b1) begin + sc2mac_wt_b_mask <= sc2mac_out_b_mask; + // VCS coverage off + end else if ((sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld) == 1'b0) begin + end else begin + sc2mac_wt_b_mask <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_a_sel <= {4{1'b0}}; + end else begin + if ((sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld) == 1'b1) begin + sc2mac_wt_a_sel <= sc2mac_out_a_sel_w; + // VCS coverage off + end else if ((sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld) == 1'b0) begin + end else begin + sc2mac_wt_a_sel <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_b_sel <= {4{1'b0}}; + end else begin + if ((sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld) == 1'b1) begin + sc2mac_wt_b_sel <= sc2mac_out_b_sel_w; + // VCS coverage off + end else if ((sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld) == 1'b0) begin + end else begin + sc2mac_wt_b_sel <= 'bx; + // VCS coverage on + end + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[0]) == 1'b1) begin + sc2mac_wt_a_data0 <= sc2mac_out_data0; + // VCS coverage off + end else if ((sc2mac_out_a_mask[0]) == 1'b0) begin + end else begin + sc2mac_wt_a_data0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[1]) == 1'b1) begin + sc2mac_wt_a_data1 <= sc2mac_out_data1; + // VCS coverage off + end else if ((sc2mac_out_a_mask[1]) == 1'b0) begin + end else begin + sc2mac_wt_a_data1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[2]) == 1'b1) begin + sc2mac_wt_a_data2 <= sc2mac_out_data2; + // VCS coverage off + end else if ((sc2mac_out_a_mask[2]) == 1'b0) begin + end else begin + sc2mac_wt_a_data2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[3]) == 1'b1) begin + sc2mac_wt_a_data3 <= sc2mac_out_data3; + // VCS coverage off + end else if ((sc2mac_out_a_mask[3]) == 1'b0) begin + end else begin + sc2mac_wt_a_data3 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[4]) == 1'b1) begin + sc2mac_wt_a_data4 <= sc2mac_out_data4; + // VCS coverage off + end else if ((sc2mac_out_a_mask[4]) == 1'b0) begin + end else begin + sc2mac_wt_a_data4 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[5]) == 1'b1) begin + sc2mac_wt_a_data5 <= sc2mac_out_data5; + // VCS coverage off + end else if ((sc2mac_out_a_mask[5]) == 1'b0) begin + end else begin + sc2mac_wt_a_data5 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[6]) == 1'b1) begin + sc2mac_wt_a_data6 <= sc2mac_out_data6; + // VCS coverage off + end else if ((sc2mac_out_a_mask[6]) == 1'b0) begin + end else begin + sc2mac_wt_a_data6 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_a_mask[7]) == 1'b1) begin + sc2mac_wt_a_data7 <= sc2mac_out_data7; + // VCS coverage off + end else if ((sc2mac_out_a_mask[7]) == 1'b0) begin + end else begin + sc2mac_wt_a_data7 <= 'bx; + // VCS coverage on + end +end + + +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[0]) == 1'b1) begin + sc2mac_wt_b_data0 <= sc2mac_out_data0; + // VCS coverage off + end else if ((sc2mac_out_b_mask[0]) == 1'b0) begin + end else begin + sc2mac_wt_b_data0 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[1]) == 1'b1) begin + sc2mac_wt_b_data1 <= sc2mac_out_data1; + // VCS coverage off + end else if ((sc2mac_out_b_mask[1]) == 1'b0) begin + end else begin + sc2mac_wt_b_data1 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[2]) == 1'b1) begin + sc2mac_wt_b_data2 <= sc2mac_out_data2; + // VCS coverage off + end else if ((sc2mac_out_b_mask[2]) == 1'b0) begin + end else begin + sc2mac_wt_b_data2 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[3]) == 1'b1) begin + sc2mac_wt_b_data3 <= sc2mac_out_data3; + // VCS coverage off + end else if ((sc2mac_out_b_mask[3]) == 1'b0) begin + end else begin + sc2mac_wt_b_data3 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[4]) == 1'b1) begin + sc2mac_wt_b_data4 <= sc2mac_out_data4; + // VCS coverage off + end else if ((sc2mac_out_b_mask[4]) == 1'b0) begin + end else begin + sc2mac_wt_b_data4 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[5]) == 1'b1) begin + sc2mac_wt_b_data5 <= sc2mac_out_data5; + // VCS coverage off + end else if ((sc2mac_out_b_mask[5]) == 1'b0) begin + end else begin + sc2mac_wt_b_data5 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[6]) == 1'b1) begin + sc2mac_wt_b_data6 <= sc2mac_out_data6; + // VCS coverage off + end else if ((sc2mac_out_b_mask[6]) == 1'b0) begin + end else begin + sc2mac_wt_b_data6 <= 'bx; + // VCS coverage on + end +end +always @(posedge nvdla_core_clk) begin + if ((sc2mac_out_b_mask[7]) == 1'b1) begin + sc2mac_wt_b_data7 <= sc2mac_out_data7; + // VCS coverage off + end else if ((sc2mac_out_b_mask[7]) == 1'b0) begin + end else begin + sc2mac_wt_b_data7 <= 'bx; + // VCS coverage on + end +end + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifndef SYNTHESIS +//: my $kk=8; +//: for(my $i = 0; $i < ${kk}; $i ++) { +//: print "assign dbg_csc_wt_a_${i} = sc2mac_wt_a_mask[${i}] ? sc2mac_wt_a_data${i} : 8'h0;\n"; +//: } +//: for(my $i = 0; $i < ${kk}; $i ++) { +//: print "assign dbg_csc_wt_b_${i} = sc2mac_wt_b_mask[${i}] ? sc2mac_wt_b_data${i} : 8'h0;\n"; +//: } +//: print "assign dbg_csc_wt_a = {"; +//: for(my $i = ${kk}-1; $i >= 0; $i --) { +//: print "dbg_csc_wt_a_${i}"; +//: if($i != 0) { +//: print ", "; +//: } else { +//: print "};\n"; +//: } +//: } +//: my $kk=8 -1; +//: print "assign dbg_csc_wt_b = {"; +//: for(my $i = ${kk}; $i >= 0; $i --) { +//: print "dbg_csc_wt_b_${i}"; +//: if($i != 0) { +//: print ", "; +//: } else { +//: print "};\n"; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dbg_csc_wt_a_0 = sc2mac_wt_a_mask[0] ? sc2mac_wt_a_data0 : 8'h0; +assign dbg_csc_wt_a_1 = sc2mac_wt_a_mask[1] ? sc2mac_wt_a_data1 : 8'h0; +assign dbg_csc_wt_a_2 = sc2mac_wt_a_mask[2] ? sc2mac_wt_a_data2 : 8'h0; +assign dbg_csc_wt_a_3 = sc2mac_wt_a_mask[3] ? sc2mac_wt_a_data3 : 8'h0; +assign dbg_csc_wt_a_4 = sc2mac_wt_a_mask[4] ? sc2mac_wt_a_data4 : 8'h0; +assign dbg_csc_wt_a_5 = sc2mac_wt_a_mask[5] ? sc2mac_wt_a_data5 : 8'h0; +assign dbg_csc_wt_a_6 = sc2mac_wt_a_mask[6] ? sc2mac_wt_a_data6 : 8'h0; +assign dbg_csc_wt_a_7 = sc2mac_wt_a_mask[7] ? sc2mac_wt_a_data7 : 8'h0; +assign dbg_csc_wt_b_0 = sc2mac_wt_b_mask[0] ? sc2mac_wt_b_data0 : 8'h0; +assign dbg_csc_wt_b_1 = sc2mac_wt_b_mask[1] ? sc2mac_wt_b_data1 : 8'h0; +assign dbg_csc_wt_b_2 = sc2mac_wt_b_mask[2] ? sc2mac_wt_b_data2 : 8'h0; +assign dbg_csc_wt_b_3 = sc2mac_wt_b_mask[3] ? sc2mac_wt_b_data3 : 8'h0; +assign dbg_csc_wt_b_4 = sc2mac_wt_b_mask[4] ? sc2mac_wt_b_data4 : 8'h0; +assign dbg_csc_wt_b_5 = sc2mac_wt_b_mask[5] ? sc2mac_wt_b_data5 : 8'h0; +assign dbg_csc_wt_b_6 = sc2mac_wt_b_mask[6] ? sc2mac_wt_b_data6 : 8'h0; +assign dbg_csc_wt_b_7 = sc2mac_wt_b_mask[7] ? sc2mac_wt_b_data7 : 8'h0; +assign dbg_csc_wt_a = {dbg_csc_wt_a_7, dbg_csc_wt_a_6, dbg_csc_wt_a_5, dbg_csc_wt_a_4, dbg_csc_wt_a_3, dbg_csc_wt_a_2, dbg_csc_wt_a_1, dbg_csc_wt_a_0}; +assign dbg_csc_wt_b = {dbg_csc_wt_b_7, dbg_csc_wt_b_6, dbg_csc_wt_b_5, dbg_csc_wt_b_4, dbg_csc_wt_b_3, dbg_csc_wt_b_2, dbg_csc_wt_b_1, dbg_csc_wt_b_0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef NVDLA_PRINT_WL +always @ (posedge nvdla_core_clk) +begin + if(layer_st) + begin + $display("[NVDLA WL] layer start"); + end +end +always @ (posedge nvdla_core_clk) +begin + if(sc2mac_wt_a_pvld) + begin + $display("[NVDLA WL] sc2mac_wt = %01024h", dbg_csc_wt_a); + end + else if (sc2mac_wt_b_pvld) + begin + $display("[NVDLA WL] sc2mac_wt = %01024h", dbg_csc_wt_b); + end +end +`endif +`endif +endmodule // NV_NVDLA_CSC_wl diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v.vcp new file mode 100644 index 0000000..2209c22 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v.vcp @@ -0,0 +1,1017 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC_wl.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_CSC_wl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sg2wl_pvld //|< i + ,sg2wl_pd //|< i + ,sc_state //|< i + ,sg2wl_reuse_rls //|< i + ,sc2cdma_wt_pending_req //|< i + ,cdma2sc_wt_updt //|< i + ,cdma2sc_wt_kernels //|< i * + ,cdma2sc_wt_entries //|< i + ,cdma2sc_wmb_entries //|< i + ,sc2cdma_wt_updt //|> o + ,sc2cdma_wt_kernels //|> o + ,sc2cdma_wt_entries //|> o + ,sc2cdma_wmb_entries //|> o + ,sc2buf_wt_rd_en //|> o + ,sc2buf_wt_rd_addr //|> o + ,sc2buf_wt_rd_valid //|< i + ,sc2buf_wt_rd_data //|< i + `ifdef CBUF_WEIGHT_COMPRESSED + ,sc2buf_wmb_rd_en //|> o + ,sc2buf_wmb_rd_addr //|> o + ,sc2buf_wmb_rd_valid //|< i + ,sc2buf_wmb_rd_data //|< i + `endif + ,sc2mac_wt_a_pvld //|> o + ,sc2mac_wt_a_mask //|> o +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( ,sc2mac_wt_a_data${i} //|> o\n); +//: } + ,sc2mac_wt_a_sel //|> o + ,sc2mac_wt_b_pvld //|> o + ,sc2mac_wt_b_mask //|> o +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq( ,sc2mac_wt_b_data${i} //|> o\n); +//: } + ,sc2mac_wt_b_sel //|> o + ,nvdla_core_ng_clk //|< i + ,reg2dp_op_en //|< i + ,reg2dp_in_precision //|< i * + ,reg2dp_proc_precision //|< i + ,reg2dp_y_extension //|< i + ,reg2dp_weight_reuse //|< i * + ,reg2dp_skip_weight_rls //|< i + ,reg2dp_weight_format //|< i + ,reg2dp_weight_bytes //|< i + ,reg2dp_wmb_bytes //|< i + ,reg2dp_data_bank //|< i + ,reg2dp_weight_bank //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input sg2wl_pvld; /* data valid */ +input [17:0] sg2wl_pd; +input [1:0] sc_state; +input sg2wl_reuse_rls; +input sc2cdma_wt_pending_req; +input cdma2sc_wt_updt; /* data valid */ +input [13:0] cdma2sc_wt_kernels; +input [15 -1:0] cdma2sc_wt_entries; +input [8:0] cdma2sc_wmb_entries; +output sc2cdma_wt_updt; /* data valid */ +output [13:0] sc2cdma_wt_kernels; +output [15 -1:0] sc2cdma_wt_entries; +output [8:0] sc2cdma_wmb_entries; +output sc2buf_wt_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wt_rd_addr; +input sc2buf_wt_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wt_rd_data; +`ifdef CBUF_WEIGHT_COMPRESSED +output sc2buf_wmb_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wmb_rd_addr; +input sc2buf_wmb_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wmb_rd_data; +`else +wire sc2buf_wmb_rd_valid=1'b0; +wire [64 -1:0] sc2buf_wmb_rd_data= {64{1'b0}}; +`endif +output sc2mac_wt_a_pvld; /* data valid */ +output sc2mac_wt_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_a_mask; +output [8 -1:0] sc2mac_wt_b_mask; +output [8/2 -1:0] sc2mac_wt_a_sel; +output [8/2 -1:0] sc2mac_wt_b_sel; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(output [8 -1:0] sc2mac_wt_a_data${i};\n); +//: print qq(output [8 -1:0] sc2mac_wt_b_data${i};\n); +//: } +input nvdla_core_ng_clk; +input [0:0] reg2dp_op_en; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [1:0] reg2dp_y_extension; +input [0:0] reg2dp_weight_reuse; +input [0:0] reg2dp_skip_weight_rls; +input [0:0] reg2dp_weight_format; +input [31:0] reg2dp_weight_bytes; +input [27:0] reg2dp_wmb_bytes; +input [4:0] reg2dp_data_bank; +input [4:0] reg2dp_weight_bank; +reg [4:0] data_bank; +reg [64 -1:0] dec_input_data; +reg [8 -1:0] dec_input_mask; +reg [9:0] dec_input_mask_en; +reg dec_input_pipe_valid; +reg is_compressed_d1; +reg is_sg_running_d1; +reg [15 -1:0] last_weight_entries; +reg [8:0] last_wmb_entries; +reg [14 -1:0] sc2buf_wmb_rd_addr; +reg sc2buf_wmb_rd_en; +reg [14 -1:0] sc2buf_wt_rd_addr; +reg sc2buf_wt_rd_en; +reg [8:0] sc2cdma_wmb_entries; +reg [15 -1:0] sc2cdma_wt_entries; +reg sc2cdma_wt_updt; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(reg [8 -1:0] sc2mac_wt_a_data${i};\n); +//: } +reg [8 -1:0] sc2mac_wt_a_mask; +reg sc2mac_wt_a_pvld; +reg [8/2 -1:0] sc2mac_wt_a_sel; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(reg [7:0] sc2mac_wt_b_data${i};\n); +//: } +reg [8 -1:0] sc2mac_wt_b_mask; +reg sc2mac_wt_b_pvld; +reg [8/2 -1:0] sc2mac_wt_b_sel; +reg [4:0] stripe_cnt; +reg [2:0] sub_h_total; +reg [4:0] weight_bank; +reg [17:0] wl_in_pd_d1; +reg wl_in_pvld_d1; +reg [10:0] wmb_element_avl; +reg [10:0] wmb_element_avl_last; +reg [64 -1:0] wmb_emask_remain; +reg [64 -1:0] wmb_emask_remain_last; +reg [8:0] wmb_entry_avl; +reg [8:0] wmb_entry_end; +reg [8:0] wmb_entry_st; +reg wmb_pipe_valid_d1; +reg [14 -1:0] wmb_req_addr; +reg [14 -1:0] wmb_req_addr_last; +reg wmb_req_channel_end_d1; +reg [1:0] wmb_req_cur_sub_h_d1; +reg [7:0] wmb_req_element_d1; +reg wmb_req_group_end_d1; +reg [6:0] wmb_req_ori_element_d1; +reg wmb_req_rls_d1; +reg [8:0] wmb_req_rls_entries_d1; +reg wmb_req_stripe_end_d1; +reg [8:0] wmb_rls_cnt; +reg wmb_rls_cnt_vld; +reg [9:0] wmb_rsp_bit_remain; +reg [9:0] wmb_rsp_bit_remain_last; +reg [7:0] wt_byte_avl; +reg [7:0] wt_byte_avl_last; +reg [64 -1:0] wt_data_remain; +reg [64 -1:0] wt_data_remain_last; +reg [15 -1:0] wt_entry_avl; +reg [15 -1:0] wt_entry_end; +reg [15 -1:0] wt_entry_st; +reg [14 -1:0] wt_req_addr; +reg [14 -1:0] wt_req_addr_last; +reg [7:0] wt_req_bytes_d1; +reg wt_req_channel_end; +reg wt_req_channel_end_d1; +reg [1:0] wt_req_cur_sub_h; +reg [8 -1:0] wt_req_emask; +reg wt_req_group_end; +reg wt_req_group_end_d1; +reg [8 -1:0] wt_req_mask_d1; +reg wt_req_mask_en_d1; +reg [6:0] wt_req_ori_element; +reg [6:0] wt_req_ori_sft_3; +reg wt_req_pipe_valid; +reg wt_req_pipe_valid_d1; +reg wt_req_rls; +reg wt_req_rls_d1; +reg wt_req_stripe_end; +reg wt_req_stripe_end_d1; +reg [8:0] wt_req_wmb_rls_entries; +reg [8:0] wt_req_wmb_rls_entries_d1; +reg [15 -1:0] wt_req_wt_rls_entries_d1; +reg [15 -1:0] wt_rls_cnt; +reg wt_rls_cnt_vld; +reg [6:0] wt_rsp_byte_remain; +reg [6:0] wt_rsp_byte_remain_last; +reg wt_rsp_last_stripe_end; +reg [8 -1:0] wt_rsp_sel_d1; +wire addr_init; +wire cbuf_reset; +wire [4:0] data_bank_w; +wire [64 -1:0] dbg_csc_wt_a; +wire [64 -1:0] dbg_csc_wt_b; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(wire [8 -1:0] dbg_csc_wt_a_${i};\n); +//: print qq(wire [8 -1:0] dbg_csc_wt_b_${i};\n); +//: } +wire [8 -1:0] dec_input_sel; +wire is_compressed; +wire is_sg_done; +wire is_sg_idle; +wire is_sg_pending; +wire is_sg_running; +wire is_stripe_end; +wire is_wr_req_addr_wrap; +wire is_wt_entry_end_wrap; +wire is_wt_entry_st_wrap; +wire [8:0] last_wmb_entries_w; +wire layer_st; +wire mon_data_bank_w; +wire mon_stripe_cnt_inc; +wire mon_stripe_length; +wire [2:0] mon_sub_h_total_w; +wire mon_weight_bank_w; +wire mon_wmb_element_avl_inc; +wire mon_wmb_entry_avl_w; +wire mon_wmb_entry_end_inc; +wire mon_wmb_entry_st_inc; +wire mon_wmb_req_addr_inc; +wire mon_wmb_req_element; +wire mon_wmb_rls_cnt_inc; +wire [1:0] mon_wmb_rsp_bit_remain_w; +wire mon_wmb_shift_remain; +wire mon_wt_byte_avl_inc; +wire mon_wt_entry_avl_w; +wire mon_wt_entry_end_inc_wrap; +wire mon_wt_entry_st_inc_wrap; +wire mon_wt_req_addr_inc; +wire mon_wt_req_addr_out; +wire mon_wt_rls_cnt_inc; +wire [1:0] mon_wt_rsp_byte_remain_w; +wire mon_wt_shift_remain; +wire reuse_rls; +wire [8 -1:0] sc2mac_out_a_mask; +wire [8/2 -1:0] sc2mac_out_a_sel_w; +wire [8 -1:0] sc2mac_out_b_mask; +wire [8/2 -1:0] sc2mac_out_b_sel_w; +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(wire [8 -1:0] sc2mac_out_data${i};\n); +//: } +wire [8 -1:0] sc2mac_out_mask; +wire sc2mac_out_pvld; +wire [8 -1:0] sc2mac_out_sel; +wire sc2mac_wt_a_pvld_w; +wire sc2mac_wt_b_pvld_w; +wire [4:0] stripe_cnt_inc; +wire stripe_cnt_reg_en; +wire [4:0] stripe_cnt_w; +wire [4:0] stripe_length; +wire [8 -1:0] sub_h_mask_1; +wire [8 -1:0] sub_h_mask_2; +wire [8 -1:0] sub_h_mask_3; +wire [2:0] sub_h_total_w; +wire sub_rls; +wire [8:0] sub_rls_wmb_entries; +wire [15 -1:0] sub_rls_wt_entries; +wire [4:0] weight_bank_w; +wire wl_channel_end; +wire [1:0] wl_cur_sub_h; +wire wl_group_end; +wire [17:0] wl_in_pd; +wire [17:0] wl_in_pd_d0; +wire wl_in_pvld; +wire wl_in_pvld_d0; +wire [5:0] wl_kernel_size; +wire [17:0] wl_pd; +wire wl_pvld; +wire [6:0] wl_weight_size; +wire wl_wt_release; +wire [10:0] wmb_element_avl_add; +wire [10:0] wmb_element_avl_inc; +wire wmb_element_avl_last_reg_en; +wire wmb_element_avl_reg_en; +wire [7:0] wmb_element_avl_sub; +wire [10:0] wmb_element_avl_w; +wire [8 -1:0] wmb_emask_rd_ls; +wire [64 -1:0] wmb_emask_rd_rs; +wire wmb_emask_remain_last_reg_en; +wire wmb_emask_remain_reg_en; +wire [64 -1:0] wmb_emask_remain_rs; +wire [64 -1:0] wmb_emask_remain_w; +wire [8:0] wmb_entry_avl_add; +wire [8:0] wmb_entry_avl_sub; +wire [8:0] wmb_entry_avl_w; +wire [8:0] wmb_entry_end_inc; +wire [8:0] wmb_entry_end_w; +wire [8:0] wmb_entry_st_inc; +wire [8:0] wmb_entry_st_w; +wire wmb_pipe_valid; +wire [14 -1:0] wmb_req_addr_inc; +wire wmb_req_addr_last_reg_en; +wire wmb_req_addr_reg_en; +wire [14 -1:0] wmb_req_addr_w; +wire [7:0] wmb_req_cycle_element; +wire wmb_req_d1_channel_end; +wire [1:0] wmb_req_d1_cur_sub_h; +wire [7:0] wmb_req_d1_element; +wire wmb_req_d1_group_end; +wire [6:0] wmb_req_d1_ori_element; +wire wmb_req_d1_rls; +wire [8:0] wmb_req_d1_rls_entries; +wire wmb_req_d1_stripe_end; +wire [7:0] wmb_req_element; +wire [6:0] wmb_req_ori_element; +wire [30:0] wmb_req_pipe_pd; +wire wmb_req_pipe_pvld; +wire wmb_req_valid; +wire [8:0] wmb_rls_cnt_inc; +wire wmb_rls_cnt_reg_en; +wire wmb_rls_cnt_vld_w; +wire [8:0] wmb_rls_cnt_w; +wire [8:0] wmb_rls_entries; +wire [10:0] wmb_rsp_bit_remain_add; +wire wmb_rsp_bit_remain_last_reg_en; +wire [7:0] wmb_rsp_bit_remain_sub; +wire [9:0] wmb_rsp_bit_remain_w; +wire wmb_rsp_channel_end; +wire [1:0] wmb_rsp_cur_sub_h; +wire [7:0] wmb_rsp_element; +wire [8 -1:0] wmb_rsp_emask; +wire [8 -1:0] wmb_rsp_emask_in; +wire wmb_rsp_group_end; +wire [6:0] wmb_rsp_ori_element; +wire [6:0] wmb_rsp_ori_sft_3; +wire [30:0] wmb_rsp_pipe_pd; +wire [30:0] wmb_rsp_pipe_pd_d0; +wire wmb_rsp_pipe_pvld; +wire wmb_rsp_pipe_pvld_d0; +wire wmb_rsp_rls; +wire [8:0] wmb_rsp_rls_entries; +wire wmb_rsp_stripe_end; +wire [8 -1:0] wmb_rsp_vld_s; +wire [7:0] wmb_shift_remain; +wire [7:0] wt_byte_avl_add; +wire [7:0] wt_byte_avl_inc; +wire [7:0] wt_byte_avl_sub; +wire [7:0] wt_byte_avl_w; +wire wt_byte_last_reg_en; +wire [64 -1:0] wt_data_input_ls; +wire [64 -1:0] wt_data_input_rs; +wire [64 -1:0] wt_data_input_sft; +wire wt_data_remain_last_reg_en; +wire [64 -1:0] wt_data_remain_masked; +wire wt_data_remain_reg_en; +wire [64 -1:0] wt_data_remain_rs; +wire [64 -1:0] wt_data_remain_w; +wire [15 -1:0] wt_entry_avl_add; +wire [15 -1:0] wt_entry_avl_sub; +wire [15 -1:0] wt_entry_avl_w; +wire [15 -1:0] wt_entry_end_inc; +wire [15 -1:0] wt_entry_end_inc_wrap; +wire [15 -1:0] wt_entry_end_w; +wire [15 -1:0] wt_entry_st_inc; +wire [15 -1:0] wt_entry_st_inc_wrap; +wire [15 -1:0] wt_entry_st_w; +wire mon_wt_entry_end_inc; +wire mon_wt_entry_st_inc; +wire [14 -1:0] wt_req_addr_inc; +wire [14 -1:0] wt_req_addr_inc_wrap; +wire wt_req_addr_last_reg_en; +wire [14 -1:0] wt_req_addr_out; +wire wt_req_addr_reg_en; +wire [14 -1:0] wt_req_addr_w; +wire [8 -1:0] wt_req_bmask; +wire [7:0] wt_req_bytes; +wire [7:0] wt_req_d1_bytes; +wire wt_req_d1_channel_end; +wire wt_req_d1_group_end; +wire wt_req_d1_rls; +wire wt_req_d1_stripe_end; +wire [8:0] wt_req_d1_wmb_rls_entries; +wire [15 -1:0] wt_req_d1_wt_rls_entries; +wire [8 -1:0] wt_req_emask_p0; +wire [8 -1:0] wt_req_emask_p1; +wire [8 -1:0] wt_req_emask_p2; +wire [8 -1:0] wt_req_emask_p3; +wire wt_req_mask_en; +wire [8 -1:0] wt_req_mask_w; +wire [6:0] wt_req_ori_sft_1; +wire [6:0] wt_req_ori_sft_2; +wire [35:0] wt_req_pipe_pd; +wire wt_req_pipe_pvld; +wire wt_req_valid; +wire [8 -1:0] wt_req_vld_bit; +wire wt_rls; +wire [15 -1:0] wt_rls_cnt_inc; +wire wt_rls_cnt_reg_en; +wire wt_rls_cnt_vld_w; +wire [15 -1:0] wt_rls_cnt_w; +wire [15 -1:0] wt_rls_entries; +wire wt_rls_updt; +wire [8:0] wt_rls_wmb_entries; +wire [15 -1:0] wt_rls_wt_entries; +wire [7:0] wt_rsp_byte_remain_add; +wire wt_rsp_byte_remain_en; +wire wt_rsp_byte_remain_last_en; +wire [6:0] wt_rsp_byte_remain_w; +wire [7:0] wt_rsp_bytes; +wire wt_rsp_channel_end; +wire [64 -1:0] wt_rsp_data; +wire wt_rsp_group_end; +wire [8 -1:0] wt_rsp_mask; +wire [8 -1:0] wt_rsp_mask_d0; +wire [8 -1:0] wt_rsp_mask_d1_w; +wire wt_rsp_mask_en; +wire wt_rsp_mask_en_d0; +wire [35:0] wt_rsp_pipe_pd; +wire [35:0] wt_rsp_pipe_pd_d0; +wire wt_rsp_pipe_pvld; +wire wt_rsp_pipe_pvld_d0; +wire wt_rsp_rls; +wire [8 -1:0] wt_rsp_sel_w; +wire wt_rsp_stripe_end; +wire [8:0] wt_rsp_wmb_rls_entries; +wire [15 -1:0] wt_rsp_wt_rls_entries; +wire [7:0] wt_shift_remain; +///////////////////////////////////////////////////////////////////////////////////////////// +// Pipeline of Weight loader, for both compressed weight and uncompressed weight +// +// input_package-------------- +// | | +// WMB_request | +// | | +// conv_buffer | +// | | +// WMB_data ---------> weight_request +// | | +// | conv_buffer +// | | +// | weight_data +// | | +// | weight_data +// | | +// |------------> weight_decompressor +// | +// weight_to_MAC_cell +// +///////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////// +///// status from sequence generator ///// +////////////////////////////////////////////////////////////// +assign is_sg_idle = (sc_state == 0 ); +assign is_sg_pending = (sc_state == 1 ); +assign is_sg_running = (sc_state == 2 ); +assign is_sg_done = (sc_state == 3 ); +assign addr_init = is_sg_running & ~is_sg_running_d1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"is_sg_running\" -q is_sg_running_d1"); +////////////////////////////////////////////////////////////// +///// input signals from registers ///// +////////////////////////////////////////////////////////////// +assign layer_st = reg2dp_op_en & is_sg_idle; +assign {mon_data_bank_w,data_bank_w} = reg2dp_data_bank + 1'b1; +assign {mon_weight_bank_w,weight_bank_w} = reg2dp_weight_bank + 1'b1; +//assign is_int8 = (reg2dp_proc_precision == 2'h0 ); +assign is_compressed = (reg2dp_weight_format == 1'h1 ); +assign {sub_h_total_w,mon_sub_h_total_w} = (6'h9 << reg2dp_y_extension); +assign last_wmb_entries_w = is_compressed_d1 ? reg2dp_wmb_bytes[8+3 :3] : 9'b0; +//: my $kk=15; +//: my $jj=3; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"data_bank_w\" -q data_bank"); +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"layer_st\" -d \"weight_bank_w\" -q weight_bank"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"is_sg_done & reg2dp_skip_weight_rls\" -d \"reg2dp_weight_bytes[${kk}-1+${jj}:${jj}]\" -q last_weight_entries"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"is_sg_done & reg2dp_skip_weight_rls\" -d \"last_wmb_entries_w\" -q last_wmb_entries"); +//: &eperl::flop("-nodeclare -rval \"3'h1\" -en \"layer_st\" -d \"sub_h_total_w\" -q sub_h_total"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"layer_st\" -d \"is_compressed\" -q is_compressed_d1"); +//Now it's a valid test case +////////////////////////////////////////////////////////////// +///// cbuf status management ///// +////////////////////////////////////////////////////////////// +assign cbuf_reset = sc2cdma_wt_pending_req; +//////////////////////////////////// calculate avaliable kernels //////////////////////////////////// +//Avaliable kernel size is useless here. Discard the code +//////////////////////////////////// calculate avaliable weight entries //////////////////////////////////// +//================ Non-SLCG clock domain ================// +assign wt_entry_avl_add = cdma2sc_wt_updt ? cdma2sc_wt_entries : {15{1'b0}}; +assign wt_entry_avl_sub = wt_rls ? wt_rls_wt_entries : {15{1'b0}}; +assign {mon_wt_entry_avl_w,wt_entry_avl_w} = (cbuf_reset) ? {15{1'b0}} : wt_entry_avl + wt_entry_avl_add - wt_entry_avl_sub; +//////////////////////////////////// calculate avaliable wmb entries //////////////////////////////////// +assign wmb_entry_avl_add = cdma2sc_wt_updt ? cdma2sc_wmb_entries : 9'b0; +assign wmb_entry_avl_sub = wt_rls ? wt_rls_wmb_entries : 9'b0; +assign {mon_wmb_entry_avl_w,wmb_entry_avl_w} = (cbuf_reset) ? 10'b0 : wmb_entry_avl + wmb_entry_avl_add - wmb_entry_avl_sub; +//////////////////////////////////// calculate weight entries start offset //////////////////////////////////// +assign {mon_wt_entry_st_inc,wt_entry_st_inc} = wt_entry_st + wt_rls_wt_entries; +assign {mon_wt_entry_st_inc_wrap,wt_entry_st_inc_wrap} = wt_entry_st_inc[15 -1:0] - {weight_bank, {9{1'b0}}}; +assign is_wt_entry_st_wrap = (wt_entry_st_inc >= {1'b0, weight_bank, {9{1'b0}}}); +assign wt_entry_st_w = (cbuf_reset) ? {15{1'b0}} : + (~wt_rls) ? wt_entry_st : + is_wt_entry_st_wrap ? wt_entry_st_inc_wrap : + wt_entry_st_inc[15 -1:0]; +//////////////////////////////////// calculate weight entries end offset //////////////////////////////////// +assign {mon_wt_entry_end_inc,wt_entry_end_inc} = wt_entry_end + cdma2sc_wt_entries; +assign {mon_wt_entry_end_inc_wrap,wt_entry_end_inc_wrap} = wt_entry_end_inc[15 -1:0] - {weight_bank, {9{1'b0}}}; +assign is_wt_entry_end_wrap = (wt_entry_end_inc >= {1'b0, weight_bank, {9{1'b0}}}); +assign wt_entry_end_w = (cbuf_reset) ? {15{1'b0}} : is_wt_entry_end_wrap ? wt_entry_end_inc_wrap : wt_entry_end_inc[15 -1:0]; +//////////////////////////////////// calculate wmb entries start offset //////////////////////////////////// +assign {mon_wmb_entry_st_inc,wmb_entry_st_inc} = wmb_entry_st + wt_rls_wmb_entries; +assign wmb_entry_st_w = (cbuf_reset) ? 9'b0 : (~wt_rls) ? wmb_entry_st : wmb_entry_st_inc[8:0]; +//////////////////////////////////// calculate wmb entries end offset //////////////////////////////////// +assign {mon_wmb_entry_end_inc,wmb_entry_end_inc} = wmb_entry_end + cdma2sc_wmb_entries; +assign wmb_entry_end_w = (cbuf_reset) ? 9'b0 : wmb_entry_end_inc[8:0]; +//////////////////////////////////// registers and assertions //////////////////////////////////// +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{12{1'b0}}\" -en \"cdma2sc_wt_updt | wt_rls | cbuf_reset\" -d \"wt_entry_avl_w\" -q wt_entry_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{9{1'b0}}\" -en \"cdma2sc_wt_updt | wt_rls | cbuf_reset\" -d \"wmb_entry_avl_w\" -q wmb_entry_avl"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{12{1'b0}}\" -en \"cbuf_reset | wt_rls\" -d \"wt_entry_st_w\" -q wt_entry_st"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{12{1'b0}}\" -en \"cbuf_reset | cdma2sc_wt_updt\" -d \"wt_entry_end_w\" -q wt_entry_end"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{9{1'b0}}\" -en \"cbuf_reset | wt_rls\" -d \"wmb_entry_st_w\" -q wmb_entry_st"); +//: &eperl::flop("-nodeclare -clk nvdla_core_ng_clk -rval \"{9{1'b0}}\" -en \"cbuf_reset | cdma2sc_wt_updt\" -d \"wmb_entry_end_w\" -q wmb_entry_end"); +//================ Non-SLCG clock domain end ================// +////////////////////////////////////////////////////////////// +///// cbuf status update ///// +////////////////////////////////////////////////////////////// +assign sub_rls = (wt_rsp_pipe_pvld & wt_rsp_rls); +assign sub_rls_wt_entries = wt_rsp_wt_rls_entries; +assign sub_rls_wmb_entries = wt_rsp_wmb_rls_entries; +assign reuse_rls = sg2wl_reuse_rls; +assign wt_rls = reuse_rls | sub_rls; +assign wt_rls_wt_entries = reuse_rls ? last_weight_entries : sub_rls_wt_entries; +assign wt_rls_wmb_entries = reuse_rls ? last_wmb_entries : sub_rls_wmb_entries; +assign wt_rls_updt = wt_rls; +//: my $kk=15; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_rls_updt\" -q sc2cdma_wt_updt"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rls_updt\" -d \"wt_rls_wt_entries\" -q sc2cdma_wt_entries"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wt_rls_updt\" -d \"wt_rls_wmb_entries\" -q sc2cdma_wmb_entries"); +//sc2cmda_wt_kernels is useless +assign sc2cdma_wt_kernels = 14'b0; +////////////////////////////////////////////////////////////// +///// input data package ///// +////////////////////////////////////////////////////////////// +//: my $pipe_depth = 5 -4; +//: my $i; +//: my $j; +//: if($pipe_depth == 0) { +//: print "assign wl_in_pvld = sg2wl_pvld;\n"; +//: print "assign wl_in_pd = sg2wl_pd;\n"; +//: } else { +//: print "assign wl_in_pvld_d0 = sg2wl_pvld;\n"; +//: print "assign wl_in_pd_d0 = sg2wl_pd;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wl_in_pvld_d${i}\" -q wl_in_pvld_d${j}"); +//: &eperl::flop("-nodeclare -rval \"{18{1'b0}}\" -en \"wl_in_pvld_d${i}\" -d \"wl_in_pd_d${i}\" -q wl_in_pd_d${j}"); +//: } +//: print "assign wl_in_pvld = wl_in_pvld_d${i};\n"; +//: print "assign wl_in_pd = wl_in_pd_d${i};\n\n"; +//: } +assign wl_pvld = wl_in_pvld; +assign wl_pd = wl_in_pd; +// PKT_UNPACK_WIRE( csc_wt_pkg , wl_ , wl_pd ) +assign wl_weight_size[6:0] = wl_pd[6:0]; +assign wl_kernel_size[5:0] = wl_pd[12:7]; +assign wl_cur_sub_h[1:0] = wl_pd[14:13]; +assign wl_channel_end = wl_pd[15]; +assign wl_group_end = wl_pd[16]; +assign wl_wt_release = wl_pd[17]; +////////////////////////////////////////////////////////////// +///// generate wmb read request ///// +////////////////////////////////////////////////////////////// +//////////////////////////////////// generate wmb_pipe_valid siganal //////////////////////////////////// +assign {mon_stripe_cnt_inc,stripe_cnt_inc} = stripe_cnt + 1'b1; +assign stripe_cnt_w = layer_st ? 5'b0 : is_stripe_end ? 5'b0 : stripe_cnt_inc; +assign {mon_stripe_length,stripe_length} = wl_kernel_size[5:0]; +assign is_stripe_end = (stripe_cnt_inc == stripe_length); +//assign is_stripe_st = wl_pvld; +assign stripe_cnt_reg_en = layer_st | wmb_pipe_valid; +assign wmb_pipe_valid = wl_pvld ? 1'b1 : ~(|stripe_cnt) ? 1'b0 : wmb_pipe_valid_d1; +//: &eperl::flop("-nodeclare -rval \"{5{1'b0}}\" -en \"stripe_cnt_reg_en\" -d \"stripe_cnt_w\" -q stripe_cnt"); +//////////////////////////////////// generate wmb_req_valid siganal //////////////////////////////////// +assign wmb_element_avl_add = ~wmb_req_valid ? 11'b0 : 11'h40; +assign wmb_element_avl_sub = wmb_pipe_valid ? wmb_req_element : 8'h0; +assign {mon_wmb_element_avl_inc,wmb_element_avl_inc} = wmb_element_avl + wmb_element_avl_add - wmb_element_avl_sub; +assign wmb_element_avl_w = layer_st ? 11'b0 : (is_stripe_end & ~wl_group_end & wl_channel_end) ? wmb_element_avl_last : wmb_element_avl_inc; +assign wmb_req_ori_element = wl_weight_size; +assign wmb_req_cycle_element = {1'b0, wl_weight_size}; +assign {mon_wmb_req_element,wmb_req_element} = (wl_cur_sub_h == 2'h0) ? {1'b0, wmb_req_cycle_element} : + (wl_cur_sub_h == 2'h1) ? {1'b0, wmb_req_cycle_element[6:0], 1'b0} : + (wl_cur_sub_h == 2'h2) ? ({wmb_req_cycle_element[6:0], 1'b0} + wmb_req_cycle_element): + {1'b0, wmb_req_cycle_element[5:0], 2'b0}; +assign wmb_req_valid = wmb_pipe_valid & is_compressed_d1 & (wmb_element_avl < {{3{1'b0}}, wmb_req_element}); +assign wmb_element_avl_reg_en = layer_st | (wmb_pipe_valid & is_compressed_d1); +assign wmb_element_avl_last_reg_en = layer_st | (wmb_pipe_valid & is_compressed_d1 & is_stripe_end & wl_group_end); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"wmb_element_avl_reg_en\" -d \"wmb_element_avl_w\" -q wmb_element_avl"); +//: &eperl::flop("-nodeclare -rval \"{11{1'b0}}\" -en \"wmb_element_avl_last_reg_en\" -d \"wmb_element_avl_w\" -q wmb_element_avl_last"); +//////////////////////////////////// generate wmb read address //////////////////////////////////// +assign {mon_wmb_req_addr_inc,wmb_req_addr_inc} = wmb_req_addr + 1'b1; +assign wmb_req_addr_w = addr_init ? {{14 -9{1'b0}},wmb_entry_st_w} : + (is_stripe_end & wl_channel_end & ~wl_group_end) ? wmb_req_addr_last : + wmb_req_valid ? wmb_req_addr_inc : + wmb_req_addr; +assign wmb_req_addr_reg_en = is_compressed_d1 & (addr_init | wmb_req_valid | (wmb_pipe_valid & is_stripe_end & wl_channel_end)); +assign wmb_req_addr_last_reg_en = is_compressed_d1 & (addr_init | (wmb_pipe_valid & is_stripe_end & wl_group_end)); +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_req_addr_reg_en\" -d \"wmb_req_addr_w\" -q wmb_req_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_req_addr_last_reg_en\" -d \"wmb_req_addr_w\" -q wmb_req_addr_last"); +//////////////////////////////////// wmb entries counter for release //////////////////////////////////// +assign wmb_rls_cnt_vld_w = (layer_st | (wl_group_end & is_stripe_end)) ? 1'b0 : (wl_channel_end & is_stripe_end) ? 1'b1 : wmb_rls_cnt_vld; +assign {mon_wmb_rls_cnt_inc,wmb_rls_cnt_inc} = wmb_rls_cnt + 1'b1; +assign wmb_rls_cnt_w = layer_st ? 9'b0 : (is_stripe_end & wl_group_end) ? 9'b0 : wmb_rls_cnt_inc; +assign wmb_rls_cnt_reg_en = layer_st | + (is_compressed_d1 & wmb_pipe_valid & is_stripe_end & wl_group_end) | + (is_compressed_d1 & wmb_req_valid & ~wmb_rls_cnt_vld); +assign wmb_rls_entries = (wmb_rls_cnt_vld | ~wmb_req_valid) ? wmb_rls_cnt : wmb_rls_cnt_inc; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_rls_cnt_vld_w\" -q wmb_rls_cnt_vld"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wmb_rls_cnt_reg_en\" -d \"wmb_rls_cnt_w\" -q wmb_rls_cnt"); +//////////////////////////////////// send wmb read request //////////////////////////////////// +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_req_valid\" -q sc2buf_wmb_rd_en"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_req_valid\" -d \"wmb_req_addr\" -q sc2buf_wmb_rd_addr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_pipe_valid\" -q wmb_pipe_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wmb_pipe_valid\" -d \"wmb_req_ori_element\" -q wmb_req_ori_element_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"wmb_pipe_valid\" -d \"wmb_req_element\" -q wmb_req_element_d1"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wmb_pipe_valid & wl_wt_release & is_stripe_end\" -d \"wmb_rls_entries\" -q wmb_req_rls_entries_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"is_stripe_end\" -q wmb_req_stripe_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"wl_channel_end & is_stripe_end\" -q wmb_req_channel_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"wl_group_end & is_stripe_end\" -q wmb_req_group_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_pipe_valid\" -d \"wl_wt_release & is_stripe_end\" -q wmb_req_rls_d1"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"wmb_pipe_valid\" -d \"wl_cur_sub_h\" -q wmb_req_cur_sub_h_d1"); +////////////////////////////////////////////////////////////// +///// sideband pipeline for wmb read ///// +////////////////////////////////////////////////////////////// +assign wmb_req_pipe_pvld = wmb_pipe_valid_d1; +assign wmb_req_d1_stripe_end = wmb_req_stripe_end_d1; +assign wmb_req_d1_channel_end = wmb_req_channel_end_d1; +assign wmb_req_d1_group_end = wmb_req_group_end_d1; +assign wmb_req_d1_rls = wmb_req_rls_d1; +assign wmb_req_d1_cur_sub_h = wmb_req_cur_sub_h_d1; +assign wmb_req_d1_element = wmb_req_element_d1; +assign wmb_req_d1_ori_element = wmb_req_ori_element_d1; +assign wmb_req_d1_rls_entries = wmb_req_rls_entries_d1; +// PKT_PACK_WIRE( csc_wmb_req_pkg , wmb_req_d1_ , wmb_req_pipe_pd ) +assign wmb_req_pipe_pd[6:0] = wmb_req_d1_ori_element[6:0]; +assign wmb_req_pipe_pd[14:7] = wmb_req_d1_element[7:0]; +assign wmb_req_pipe_pd[23:15] = wmb_req_d1_rls_entries[8:0]; +assign wmb_req_pipe_pd[24] = wmb_req_d1_stripe_end ; +assign wmb_req_pipe_pd[25] = wmb_req_d1_channel_end ; +assign wmb_req_pipe_pd[26] = wmb_req_d1_group_end ; +assign wmb_req_pipe_pd[27] = wmb_req_d1_rls ; +assign wmb_req_pipe_pd[28] = 1'b0 ; +assign wmb_req_pipe_pd[30:29] = wmb_req_d1_cur_sub_h[1:0]; +//: my $pipe_depth = 6; +//: my $i; +//: my $j; +//: if($pipe_depth == 0) { +//: print "assign wmb_rsp_pipe_pvld = wmb_req_pipe_pvld;\n"; +//: print "assign wmb_rsp_pipe_pd = wmb_req_pipe_pd;\n\n"; +//: } else { +//: print "assign wmb_rsp_pipe_pvld_d0 = wmb_req_pipe_pvld;\n"; +//: print "assign wmb_rsp_pipe_pd_d0 = wmb_req_pipe_pd;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"wmb_rsp_pipe_pvld_d${i}\" -q wmb_rsp_pipe_pvld_d${j}"); +//: &eperl::flop("-wid 31 -rval \"{31{1'b0}}\" -en \"wmb_rsp_pipe_pvld_d${i}\" -d \"wmb_rsp_pipe_pd_d${i}\" -q wmb_rsp_pipe_pd_d${j}"); +//: } +//: print "assign wmb_rsp_pipe_pvld = wmb_rsp_pipe_pvld_d${i};\n"; +//: print "assign wmb_rsp_pipe_pd = wmb_rsp_pipe_pd_d${i};\n\n"; +//: } +////////////////////////////////////////////////////////////// +///// wmb data process ///// +////////////////////////////////////////////////////////////// +// PKT_UNPACK_WIRE( csc_wmb_req_pkg , wmb_rsp_ , wmb_rsp_pipe_pd ) +assign wmb_rsp_ori_element[6:0] = wmb_rsp_pipe_pd[6:0]; +assign wmb_rsp_element[7:0] = wmb_rsp_pipe_pd[14:7]; +assign wmb_rsp_rls_entries[8:0] = wmb_rsp_pipe_pd[23:15]; +assign wmb_rsp_stripe_end = wmb_rsp_pipe_pd[24]; +assign wmb_rsp_channel_end = wmb_rsp_pipe_pd[25]; +assign wmb_rsp_group_end = wmb_rsp_pipe_pd[26]; +assign wmb_rsp_rls = wmb_rsp_pipe_pd[27]; +assign wmb_rsp_cur_sub_h[1:0] = wmb_rsp_pipe_pd[30:29]; +//////////////////////////////////// wmb remain counter //////////////////////////////////// +assign wmb_rsp_bit_remain_add = sc2buf_wmb_rd_valid ? 11'h40 : 11'h0; +assign wmb_rsp_bit_remain_sub = wmb_rsp_pipe_pvld ? wmb_rsp_element : 8'b0; +//how many mask bits is stored currently +assign {mon_wmb_rsp_bit_remain_w,wmb_rsp_bit_remain_w} = (layer_st) ? 11'b0 : + (wmb_rsp_channel_end & ~wmb_rsp_group_end) ? {2'b0, wmb_rsp_bit_remain_last} : + wmb_rsp_bit_remain + wmb_rsp_bit_remain_add - wmb_rsp_bit_remain_sub; +assign wmb_rsp_bit_remain_last_reg_en = layer_st | (wmb_rsp_pipe_pvld & wmb_rsp_group_end & is_compressed_d1); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"layer_st | (wmb_rsp_pipe_pvld & is_compressed_d1)\" -d \"wmb_rsp_bit_remain_w\" -q wmb_rsp_bit_remain"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -en \"wmb_rsp_bit_remain_last_reg_en\" -d \"wmb_rsp_bit_remain_w\" -q wmb_rsp_bit_remain_last"); +//////////////////////////////////// generate element mask for both compressed and compressed case //////////////////////////////////// +//emask for element mask, NOT byte mask +assign wmb_emask_rd_ls = ~sc2buf_wmb_rd_valid ? {8{1'b0}} : (sc2buf_wmb_rd_data[8 -1:0] << wmb_rsp_bit_remain[6:0]); +assign wmb_rsp_emask_in = (wmb_emask_rd_ls | wmb_emask_remain[8 -1:0] | {8{~is_compressed_d1}}); //wmb for current atomic op +assign wmb_rsp_vld_s = ~({8{1'b1}} << wmb_rsp_element); +assign wmb_rsp_emask = wmb_rsp_emask_in[8 -1:0] & wmb_rsp_vld_s; //the mask needed +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_emask\" -q wt_req_emask"); +//////////////////////////////////// generate local remain masks //////////////////////////////////// +assign {mon_wmb_shift_remain,wmb_shift_remain} = wmb_rsp_element - wmb_rsp_bit_remain[6:0]; +assign wmb_emask_rd_rs = (sc2buf_wmb_rd_data >> wmb_shift_remain); //read 1 entry wmb and be partial used +assign wmb_emask_remain_rs = (wmb_emask_remain >> wmb_rsp_element); //remain wmb and partial used +//all wmb remain, no more than 1 entry +assign wmb_emask_remain_w = layer_st ? {64{1'b0}} : + (wmb_rsp_channel_end & ~wmb_rsp_group_end) ? wmb_emask_remain_last : + sc2buf_wmb_rd_valid ? wmb_emask_rd_rs : + wmb_emask_remain_rs; +assign wmb_emask_remain_reg_en = layer_st | (wmb_rsp_pipe_pvld & is_compressed_d1); +assign wmb_emask_remain_last_reg_en = layer_st | (wmb_rsp_pipe_pvld & wmb_rsp_group_end & is_compressed_d1); +assign wmb_rsp_ori_sft_3 = {wmb_rsp_ori_element[4:0], 1'b0} + wmb_rsp_ori_element[4:0]; +//: my $kk=64; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_emask_remain_reg_en\" -d \"wmb_emask_remain_w\" -q wmb_emask_remain"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wmb_emask_remain_last_reg_en\" -d \"wmb_emask_remain_w\" -q wmb_emask_remain_last"); +//////////////////////////////////// registers for pipeline //////////////////////////////////// +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wmb_rsp_pipe_pvld\" -q wt_req_pipe_valid"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_ori_element\" -q wt_req_ori_element"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_stripe_end\" -q wt_req_stripe_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_channel_end\" -q wt_req_channel_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_group_end\" -q wt_req_group_end"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_rls\" -q wt_req_rls"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_rls_entries\" -q wt_req_wmb_rls_entries"); +//: &eperl::flop("-nodeclare -rval \"{2{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_cur_sub_h\" -q wt_req_cur_sub_h"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wmb_rsp_pipe_pvld\" -d \"wmb_rsp_ori_sft_3\" -q wt_req_ori_sft_3"); +////////////////////////////////////////////////////////////// +///// weight data request generate ///// +////////////////////////////////////////////////////////////// +//////////////////////////////////// generate mask sum //////////////////////////////////// +////CAUSION! wt_req_bmask is byte mask, not elemnet mask!//// +assign wt_req_bmask = wt_req_emask; +//: print "assign wt_req_bytes = \n"; +//: my $j=int(8/4); +//: for(my $i=0; $i<$j; $i++){ +//: print "wt_req_bmask[4*${i}+0] + wt_req_bmask[4*${i}+1] + wt_req_bmask[4*${i}+2] + wt_req_bmask[4*${i}+3] + \n"; +//: } +//: print "1'b0; \n"; +//////////////////////////////////// generate element mask for decoding//////////////////////////////////// +//valid bit for each sub h line +assign wt_req_vld_bit = ~({8{1'b1}} << wt_req_ori_element); +//valid bit to select sub h line +//: my $kk=8; +//: print qq( +//: assign sub_h_mask_1 = (wt_req_cur_sub_h >= 2'h1) ? {${kk}{1'b1}} : {${kk}{1'h0}}; +//: assign sub_h_mask_2 = (wt_req_cur_sub_h >= 2'h2) ? {${kk}{1'b1}} : {${kk}{1'h0}}; +//: assign sub_h_mask_3 = (wt_req_cur_sub_h == 2'h3) ? {${kk}{1'b1}} : {${kk}{1'h0}}; +//: ); +//element number to be shifted +assign wt_req_ori_sft_1 = wt_req_ori_element; +assign wt_req_ori_sft_2 = {wt_req_ori_element[5:0], 1'b0}; +assign wt_req_emask_p0 = wt_req_emask[8 -1:0] & wt_req_vld_bit; +assign wt_req_emask_p1 = (wt_req_emask[8 -1:0] >> wt_req_ori_sft_1) & wt_req_vld_bit & sub_h_mask_1; +assign wt_req_emask_p2 = (wt_req_emask[8 -1:0] >> wt_req_ori_sft_2) & wt_req_vld_bit & sub_h_mask_2; +assign wt_req_emask_p3 = (wt_req_emask[8 -1:0] >> wt_req_ori_sft_3) & wt_req_vld_bit & sub_h_mask_3; +//Caution! Must reset wt_req_mask to all zero when layer started +//other width wt_req_mask_en may gate wt_rsp_mask_d1_w improperly! +assign wt_req_mask_w = layer_st ? {8{1'b0}} : + (sub_h_total == 3'h1) ? {wt_req_emask_p0} : + (sub_h_total == 3'h2) ? {wt_req_emask_p1[8/2-1:0], wt_req_emask_p0[8/2-1:0]} : + {wt_req_emask_p3[8/4-1:0], wt_req_emask_p2[8/4-1:0], wt_req_emask_p1[8/4-1:0], wt_req_emask_p0[8/4-1:0]}; +//assign wt_req_mask_w = layer_st ? {8{1'b0}} : wt_req_emask_p0; //need update for image +assign wt_req_mask_en = wt_req_pipe_valid & (wt_req_mask_w != wt_req_mask_d1); +//////////////////////////////////// generate weight read request //////////////////////////////////// +assign wt_req_valid = wt_req_pipe_valid & (wt_byte_avl < wt_req_bytes); +//////////////////////////////////// generate weight avaliable bytes //////////////////////////////////// +assign wt_byte_avl_add = ~wt_req_valid ? 8'b0 : 7'h8; +assign wt_byte_avl_sub = wt_req_bytes; +assign {mon_wt_byte_avl_inc,wt_byte_avl_inc} = wt_byte_avl + wt_byte_avl_add - wt_byte_avl_sub; +assign wt_byte_avl_w = layer_st ? 8'b0 : ( ~wt_req_group_end & wt_req_channel_end) ? wt_byte_avl_last : wt_byte_avl_inc; +assign wt_byte_last_reg_en = layer_st | (wt_req_pipe_valid & wt_req_stripe_end & wt_req_group_end); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"layer_st | wt_req_pipe_valid\" -d \"wt_byte_avl_w\" -q wt_byte_avl"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"wt_byte_last_reg_en\" -d \"wt_byte_avl_w\" -q wt_byte_avl_last"); +//////////////////////////////////// generate weight read address //////////////////////////////////// +assign {mon_wt_req_addr_inc,wt_req_addr_inc} = wt_req_addr + 1'b1; +assign is_wr_req_addr_wrap = (wt_req_addr_inc == {weight_bank, {9{1'b0}}}); +assign wt_req_addr_inc_wrap = is_wr_req_addr_wrap ? {14{1'b0}} : wt_req_addr_inc; +assign wt_req_addr_w = addr_init ? wt_entry_st_w[14 -1:0] : + (wt_req_channel_end & ~wt_req_group_end) ? wt_req_addr_last : + wt_req_valid ? wt_req_addr_inc_wrap : + wt_req_addr; +assign wt_req_addr_reg_en = addr_init | wt_req_valid | (wt_req_pipe_valid & wt_req_channel_end); +assign wt_req_addr_last_reg_en = addr_init | (wt_req_pipe_valid & wt_req_pipe_valid & wt_req_group_end); +assign {mon_wt_req_addr_out,wt_req_addr_out} = wt_req_addr + {data_bank, {9{1'b0}}}; +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_req_addr_reg_en\" -d \"wt_req_addr_w\" -q wt_req_addr"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_req_addr_last_reg_en\" -d \"wt_req_addr_w\" -q wt_req_addr_last"); +//////////////////////////////////// weight entries counter for release //////////////////////////////////// +assign wt_rls_cnt_vld_w = (layer_st | wt_req_group_end) ? 1'b0 : wt_req_channel_end ? 1'b1 : wt_rls_cnt_vld; +assign {mon_wt_rls_cnt_inc,wt_rls_cnt_inc} = wt_rls_cnt + 1'b1; +assign wt_rls_cnt_w = layer_st ? {15{1'b0}} : wt_req_group_end ? {15{1'b0}} : wt_rls_cnt_inc; +assign wt_rls_cnt_reg_en = layer_st | (wt_req_pipe_valid & wt_req_group_end) | (~wt_rls_cnt_vld & wt_req_valid); +assign wt_rls_entries = (wt_rls_cnt_vld | ~wt_req_valid) ? wt_rls_cnt : wt_rls_cnt_inc; +//: my $kk=15; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_rls_cnt_vld_w\" -q wt_rls_cnt_vld"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rls_cnt_reg_en\" -d \"wt_rls_cnt_w\" -q wt_rls_cnt"); +//////////////////////////////////// send weight read request //////////////////////////////////// +//: my $kk=14; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_valid\" -q sc2buf_wt_rd_en"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_req_valid\" -d \"wt_req_addr_out\" -q sc2buf_wt_rd_addr"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_pipe_valid\" -q wt_req_pipe_valid_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_stripe_end\" -q wt_req_stripe_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_channel_end\" -q wt_req_channel_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_group_end\" -q wt_req_group_end_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -en \"wt_req_pipe_valid\" -d \"wt_req_rls\" -q wt_req_rls_d1"); +//: &eperl::flop("-nodeclare -rval \"{8{1'b0}}\" -en \"wt_req_pipe_valid\" -d \"wt_req_bytes\" -q wt_req_bytes_d1"); +//Caution! Here wt_req_mask is still element mask +//: my $kk=8; +//: my $jj=15; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"layer_st | wt_req_pipe_valid\" -d \"wt_req_mask_w\" -q wt_req_mask_d1"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_req_mask_en\" -q wt_req_mask_en_d1"); +//: &eperl::flop("-nodeclare -rval \"{9{1'b0}}\" -en \"wt_req_pipe_valid\" -d \"wt_req_wmb_rls_entries\" -q wt_req_wmb_rls_entries_d1"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"wt_req_pipe_valid & wt_req_rls\" -d \"wt_rls_entries\" -q wt_req_wt_rls_entries_d1"); +////////////////////////////////////////////////////////////// +///// sideband pipeline for wmb read ///// +////////////////////////////////////////////////////////////// +assign wt_req_pipe_pvld = wt_req_pipe_valid_d1; +assign wt_req_d1_stripe_end = wt_req_stripe_end_d1; +assign wt_req_d1_channel_end = wt_req_channel_end_d1; +assign wt_req_d1_group_end = wt_req_group_end_d1; +assign wt_req_d1_rls = wt_req_rls_d1; +assign wt_req_d1_bytes = wt_req_bytes_d1; +assign wt_req_d1_wmb_rls_entries = wt_req_wmb_rls_entries_d1; +assign wt_req_d1_wt_rls_entries = wt_req_wt_rls_entries_d1; +// PKT_PACK_WIRE( csc_wt_req_pkg , wt_req_d1_ , wt_req_pipe_pd ) +assign wt_req_pipe_pd[7:0] = wt_req_d1_bytes[7:0]; +assign wt_req_pipe_pd[16:8] = wt_req_d1_wmb_rls_entries[8:0]; +assign wt_req_pipe_pd[31:17] = wt_req_d1_wt_rls_entries[14:0]; +assign wt_req_pipe_pd[32] = wt_req_d1_stripe_end ; +assign wt_req_pipe_pd[33] = wt_req_d1_channel_end ; +assign wt_req_pipe_pd[34] = wt_req_d1_group_end ; +assign wt_req_pipe_pd[35] = wt_req_d1_rls ; +//: my $pipe_depth = 6; +//: my $i; +//: my $j; +//: my $kk=8; +//: if($pipe_depth == 0) { +//: print "assign wt_rsp_pipe_pvld = wt_req_pipe_pvld;\n"; +//: print "assign wt_rsp_pipe_pd = wt_req_pipe_pd;\n"; +//: print "assign wt_rsp_mask_en = wt_req_mask_en_d1;\n"; +//: print "assign wt_rsp_mask = wt_req_mask_d1;\n\n\n\n"; +//: } else { +//: print "assign wt_rsp_pipe_pvld_d0 = wt_req_pipe_pvld;\n"; +//: print "assign wt_rsp_pipe_pd_d0 = wt_req_pipe_pd;\n"; +//: print "assign wt_rsp_mask_en_d0 = wt_req_mask_en_d1;\n"; +//: print "assign wt_rsp_mask_d0 = wt_req_mask_d1;\n\n"; +//: for($i = 0; $i < $pipe_depth; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"wt_rsp_pipe_pvld_d${i}\" -q wt_rsp_pipe_pvld_d${j}"); +//: &eperl::flop("-wid 36 -rval \"{36{1'b0}}\" -en \"wt_rsp_pipe_pvld_d${i}\" -d \"wt_rsp_pipe_pd_d${i}\" -q wt_rsp_pipe_pd_d${j}"); +//: &eperl::flop("-wid 1 -rval \"1'b0\" -d \"wt_rsp_mask_en_d${i}\" -q wt_rsp_mask_en_d${j}"); +//: &eperl::flop("-wid ${kk} -rval \"{${kk}{1'b0}}\" -en \"wt_rsp_mask_en_d${i}\" -d \"wt_rsp_mask_d${i}\" -q wt_rsp_mask_d${j}"); +//: } +//: print "assign wt_rsp_pipe_pvld = wt_rsp_pipe_pvld_d${i};\n"; +//: print "assign wt_rsp_pipe_pd = wt_rsp_pipe_pd_d${i};\n\n"; +//: print "assign wt_rsp_mask_en = wt_rsp_mask_en_d${i};\n"; +//: print "assign wt_rsp_mask = wt_rsp_mask_d${i};\n\n"; +//: } +////////////////////////////////////////////////////////////// +///// weight data process ///// +////////////////////////////////////////////////////////////// +// PKT_UNPACK_WIRE( csc_wt_req_pkg , wt_rsp_ , wt_rsp_pipe_pd ) +assign wt_rsp_bytes[7:0] = wt_rsp_pipe_pd[7:0]; +assign wt_rsp_wmb_rls_entries[8:0] = wt_rsp_pipe_pd[16:8]; +assign wt_rsp_wt_rls_entries[14:0] = wt_rsp_pipe_pd[31:17]; +assign wt_rsp_stripe_end = wt_rsp_pipe_pd[32]; +assign wt_rsp_channel_end = wt_rsp_pipe_pd[33]; +assign wt_rsp_group_end = wt_rsp_pipe_pd[34]; +assign wt_rsp_rls = wt_rsp_pipe_pd[35]; +//////////////////////////////////// generate byte mask for decoding //////////////////////////////////// +assign wt_rsp_mask_d1_w = wt_rsp_mask ; +//////////////////////////////////// weight remain counter //////////////////////////////////// +assign wt_rsp_byte_remain_add = sc2buf_wt_rd_valid ? 7'h8 : 8'h0; +assign {mon_wt_rsp_byte_remain_w,wt_rsp_byte_remain_w} = (layer_st) ? 8'b0 : + (wt_rsp_channel_end & ~wt_rsp_group_end) ? {2'b0, wt_rsp_byte_remain_last} : + wt_rsp_byte_remain + wt_rsp_byte_remain_add - wt_rsp_bytes; +assign wt_rsp_byte_remain_en = layer_st | wt_rsp_pipe_pvld; +assign wt_rsp_byte_remain_last_en = layer_st | (wt_rsp_pipe_pvld & wt_rsp_group_end); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_rsp_byte_remain_en\" -d \"wt_rsp_byte_remain_w\" -q wt_rsp_byte_remain"); +//: &eperl::flop("-nodeclare -rval \"{7{1'b0}}\" -en \"wt_rsp_byte_remain_last_en\" -d \"wt_rsp_byte_remain_w\" -q wt_rsp_byte_remain_last"); +//////////////////////////////////// generate local remain bytes //////////////////////////////////// +assign {mon_wt_shift_remain,wt_shift_remain} = wt_rsp_bytes - wt_rsp_byte_remain[6:0]; +assign wt_data_input_rs = (sc2buf_wt_rd_data[64 -1:0] >> {wt_shift_remain, 3'b0}); +assign wt_data_remain_masked = ~(|wt_rsp_byte_remain) ? {64{1'b0}}: wt_data_remain; +assign wt_data_remain_rs = (wt_data_remain >> {wt_rsp_bytes, 3'b0}); +//weight data local remain, 1 entry at most +assign wt_data_remain_w = layer_st ? {64{1'b0}} : + (wt_rsp_channel_end & ~wt_rsp_group_end & (|wt_rsp_byte_remain_last)) ? wt_data_remain_last : + sc2buf_wt_rd_valid ? wt_data_input_rs : + wt_data_remain_rs; +assign wt_data_remain_reg_en = layer_st | (wt_rsp_pipe_pvld & (|wt_rsp_byte_remain_w)); +assign wt_data_remain_last_reg_en = layer_st | (wt_rsp_pipe_pvld & wt_rsp_group_end & (|wt_rsp_byte_remain_w)); +assign wt_data_input_ls = (sc2buf_wt_rd_data << {wt_rsp_byte_remain[6:0], 3'b0}); +assign wt_data_input_sft = (sc2buf_wt_rd_valid) ? wt_data_input_ls : {64{1'b0}}; +//: &eperl::flop("-nodeclare -norst -en \"wt_data_remain_reg_en\" -d \"wt_data_remain_w\" -q wt_data_remain"); +//: &eperl::flop("-nodeclare -norst -en \"wt_data_remain_last_reg_en\" -d \"wt_data_remain_w\" -q wt_data_remain_last"); +//////////////////////////////////// generate bytes for decoding //////////////////////////////////// +assign wt_rsp_data = (wt_data_input_sft | wt_data_remain_masked); +//: my $kk=64; +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rsp_pipe_pvld\" -d \"wt_rsp_data\" -q dec_input_data"); +//////////////////////////////////// generate select signal //////////////////////////////////// +assign wt_rsp_sel_w = wt_rsp_last_stripe_end ? {{(8 -1){1'h0}},1'h1} : {wt_rsp_sel_d1[8 -2:0], wt_rsp_sel_d1[8 -1]}; +//: &eperl::flop("-nodeclare -rval \"1'b1\" -en \"wt_rsp_pipe_pvld\" -d \"wt_rsp_stripe_end\" -q wt_rsp_last_stripe_end"); +//: &eperl::flop("-nodeclare -rval \"'h1\" -en \"wt_rsp_pipe_pvld\" -d \"wt_rsp_sel_w\" -q wt_rsp_sel_d1"); +assign dec_input_sel = wt_rsp_sel_d1; +//////////////////////////////////// prepare other signals //////////////////////////////////// +//: my $kk=8; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"wt_rsp_pipe_pvld\" -q dec_input_pipe_valid"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"wt_rsp_mask_en\" -d \"wt_rsp_mask_d1_w\" -q dec_input_mask"); +//: &eperl::flop("-nodeclare -rval \"{10{1'b0}}\" -d \"{10{wt_rsp_mask_en}}\" -q dec_input_mask_en"); +NV_NVDLA_CSC_WL_dec u_dec ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.input_data (dec_input_data[8*8 -1:0]) //|< r + ,.input_mask (dec_input_mask[8 -1:0]) //|< r + ,.input_mask_en (dec_input_mask_en[9:0]) //|< r + ,.input_pipe_valid (dec_input_pipe_valid) //|< r + ,.input_sel (dec_input_sel[8 -1:0]) //|< w +//: for(my $i = 0; $i < 8; $i ++) { +//: print qq(,.output_data${i} (sc2mac_out_data${i}) //|> w\n); +//: } + ,.output_mask (sc2mac_out_mask[8 -1:0]) //|> w + ,.output_pvld (sc2mac_out_pvld) //|> w + ,.output_sel (sc2mac_out_sel[8 -1:0]) //|> w + ,.is_fp16 (1'b0) //|< i + ,.is_int8 (1'b1) //|< i + ); +////////////////////////////////////////////////////////////// +///// registers for retiming ///// +////////////////////////////////////////////////////////////// +assign sc2mac_out_a_sel_w = {8/2{sc2mac_out_pvld}} & sc2mac_out_sel[8/2 -1:0]; +assign sc2mac_out_b_sel_w = {8/2{sc2mac_out_pvld}} & sc2mac_out_sel[8 -1:8/2]; +assign sc2mac_wt_a_pvld_w = (|sc2mac_out_a_sel_w); +assign sc2mac_wt_b_pvld_w = (|sc2mac_out_b_sel_w); +assign sc2mac_out_a_mask = sc2mac_out_mask & {8{sc2mac_wt_a_pvld_w}}; +assign sc2mac_out_b_mask = sc2mac_out_mask & {8{sc2mac_wt_b_pvld_w}}; +//: my $kk=8; +//: my $jj=8/2; +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2mac_wt_a_pvld_w\" -q sc2mac_wt_a_pvld"); +//: &eperl::flop("-nodeclare -rval \"1'b0\" -d \"sc2mac_wt_b_pvld_w\" -q sc2mac_wt_b_pvld"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld\" -d \"sc2mac_out_a_mask\" -q sc2mac_wt_a_mask"); +//: &eperl::flop("-nodeclare -rval \"{${kk}{1'b0}}\" -en \"sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld\" -d \"sc2mac_out_b_mask\" -q sc2mac_wt_b_mask"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"sc2mac_wt_a_pvld_w | sc2mac_wt_a_pvld\" -d \"sc2mac_out_a_sel_w\" -q sc2mac_wt_a_sel"); +//: &eperl::flop("-nodeclare -rval \"{${jj}{1'b0}}\" -en \"sc2mac_wt_b_pvld_w | sc2mac_wt_b_pvld\" -d \"sc2mac_out_b_sel_w\" -q sc2mac_wt_b_sel"); +//: for(my $i = 0; $i < 8; $i ++) { +//: &eperl::flop("-nodeclare -norst -en \"sc2mac_out_a_mask[${i}]\" -d \"sc2mac_out_data${i}\" -q sc2mac_wt_a_data${i}"); +//: } +//: print "\n\n"; +//: +//: for(my $i = 0; $i < 8; $i ++) { +//: &eperl::flop("-nodeclare -norst -en \"sc2mac_out_b_mask[${i}]\" -d \"sc2mac_out_data${i}\" -q sc2mac_wt_b_data${i}"); +//: } +//: print "\n\n"; +`ifndef SYNTHESIS +//: my $kk=8; +//: for(my $i = 0; $i < ${kk}; $i ++) { +//: print "assign dbg_csc_wt_a_${i} = sc2mac_wt_a_mask[${i}] ? sc2mac_wt_a_data${i} : 8'h0;\n"; +//: } +//: for(my $i = 0; $i < ${kk}; $i ++) { +//: print "assign dbg_csc_wt_b_${i} = sc2mac_wt_b_mask[${i}] ? sc2mac_wt_b_data${i} : 8'h0;\n"; +//: } +//: print "assign dbg_csc_wt_a = {"; +//: for(my $i = ${kk}-1; $i >= 0; $i --) { +//: print "dbg_csc_wt_a_${i}"; +//: if($i != 0) { +//: print ", "; +//: } else { +//: print "};\n"; +//: } +//: } +//: my $kk=8 -1; +//: print "assign dbg_csc_wt_b = {"; +//: for(my $i = ${kk}; $i >= 0; $i --) { +//: print "dbg_csc_wt_b_${i}"; +//: if($i != 0) { +//: print ", "; +//: } else { +//: print "};\n"; +//: } +//: } +`ifdef NVDLA_PRINT_WL +always @ (posedge nvdla_core_clk) +begin + if(layer_st) + begin + $display("[NVDLA WL] layer start"); + end +end +always @ (posedge nvdla_core_clk) +begin + if(sc2mac_wt_a_pvld) + begin + $display("[NVDLA WL] sc2mac_wt = %01024h", dbg_csc_wt_a); + end + else if (sc2mac_wt_b_pvld) + begin + $display("[NVDLA WL] sc2mac_wt = %01024h", dbg_csc_wt_b); + end +end +`endif +`endif +endmodule // NV_NVDLA_CSC_wl diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.swl b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.swl new file mode 100644 index 0000000..c6562c7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.swl @@ -0,0 +1,2 @@ +waive -regexp -file NV_NVDLA_CSC_dl.v -msg "LHS: 'dat_req_addr_minus1_wrap' width 14 is less than RHS.*" -rule W164a +waive -regexp -file NV_NVDLA_CSC_dl.v -msg "For operator (>=), left expression: "dat_req_addr_minus1" width 14 should match right expression.*" -rule W164a diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.swl.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.swl.vcp new file mode 100644 index 0000000..c6562c7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.swl.vcp @@ -0,0 +1,2 @@ +waive -regexp -file NV_NVDLA_CSC_dl.v -msg "LHS: 'dat_req_addr_minus1_wrap' width 14 is less than RHS.*" -rule W164a +waive -regexp -file NV_NVDLA_CSC_dl.v -msg "For operator (>=), left expression: "dat_req_addr_minus1" width 14 should match right expression.*" -rule W164a diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.v b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.v new file mode 100644 index 0000000..3ce8911 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.v @@ -0,0 +1,649 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_csc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +module NV_NVDLA_csc ( + accu2sc_credit_size //|< i + ,accu2sc_credit_vld //|< i + ,cdma2sc_dat_entries //|< i + ,cdma2sc_dat_pending_ack //|< i + ,cdma2sc_dat_slices //|< i + ,cdma2sc_dat_updt //|< i + ,cdma2sc_wmb_entries //|< i + ,cdma2sc_wt_entries //|< i + ,cdma2sc_wt_kernels //|< i + ,cdma2sc_wt_pending_ack //|< i + ,cdma2sc_wt_updt //|< i + ,csb2csc_req_pd //|< i + ,csb2csc_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,sc2buf_dat_rd_data //|< i + ,sc2buf_dat_rd_valid //|< i + ,sc2buf_dat_rd_shift //|> o + ,sc2buf_dat_rd_next1_en //|> o + ,sc2buf_dat_rd_next1_addr //|> o + ,sc2buf_wt_rd_data //|< i + ,sc2buf_wt_rd_valid //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,csb2csc_req_prdy //|> o + ,csc2csb_resp_pd //|> o + ,csc2csb_resp_valid //|> o + ,sc2buf_dat_rd_addr //|> o + ,sc2buf_dat_rd_en //|> o + ,sc2buf_wt_rd_addr //|> o + ,sc2buf_wt_rd_en //|> o + ,sc2cdma_dat_entries //|> o + ,sc2cdma_dat_pending_req //|> o + ,sc2cdma_dat_slices //|> o + ,sc2cdma_dat_updt //|> o + ,sc2cdma_wmb_entries //|> o + ,sc2cdma_wt_entries //|> o + ,sc2cdma_wt_kernels //|> o + ,sc2cdma_wt_pending_req //|> o + ,sc2cdma_wt_updt //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_a_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_a_data0 //|> o +,sc2mac_dat_a_data1 //|> o +,sc2mac_dat_a_data2 //|> o +,sc2mac_dat_a_data3 //|> o +,sc2mac_dat_a_data4 //|> o +,sc2mac_dat_a_data5 //|> o +,sc2mac_dat_a_data6 //|> o +,sc2mac_dat_a_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_a_mask //|> o + ,sc2mac_dat_a_pd //|> o + ,sc2mac_dat_a_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_b_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_b_data0 //|> o +,sc2mac_dat_b_data1 //|> o +,sc2mac_dat_b_data2 //|> o +,sc2mac_dat_b_data3 //|> o +,sc2mac_dat_b_data4 //|> o +,sc2mac_dat_b_data5 //|> o +,sc2mac_dat_b_data6 //|> o +,sc2mac_dat_b_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_b_mask //|> o + ,sc2mac_dat_b_pd //|> o + ,sc2mac_dat_b_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_a_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_a_data0 //|> o +,sc2mac_wt_a_data1 //|> o +,sc2mac_wt_a_data2 //|> o +,sc2mac_wt_a_data3 //|> o +,sc2mac_wt_a_data4 //|> o +,sc2mac_wt_a_data5 //|> o +,sc2mac_wt_a_data6 //|> o +,sc2mac_wt_a_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_a_mask //|> o + ,sc2mac_wt_a_pvld //|> o + ,sc2mac_wt_a_sel //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_b_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_b_data0 //|> o +,sc2mac_wt_b_data1 //|> o +,sc2mac_wt_b_data2 //|> o +,sc2mac_wt_b_data3 //|> o +,sc2mac_wt_b_data4 //|> o +,sc2mac_wt_b_data5 //|> o +,sc2mac_wt_b_data6 //|> o +,sc2mac_wt_b_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_b_mask //|> o + ,sc2mac_wt_b_pvld //|> o + ,sc2mac_wt_b_sel //|> o + `ifdef CBUF_WEIGHT_COMPRESSED + ,sc2buf_wmb_rd_addr //|> o + ,sc2buf_wmb_rd_en //|> o + ,sc2buf_wmb_rd_data //|< i + ,sc2buf_wmb_rd_valid //|< i + `endif + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output sc2cdma_dat_pending_req; +output sc2cdma_wt_pending_req; +input accu2sc_credit_vld; /* data valid */ +input [2:0] accu2sc_credit_size; +input cdma2sc_dat_pending_ack; +input cdma2sc_wt_pending_ack; +input csb2csc_req_pvld; /* data valid */ +output csb2csc_req_prdy; /* data return handshake */ +input [62:0] csb2csc_req_pd; +output csc2csb_resp_valid; /* data valid */ +output [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input cdma2sc_dat_updt; /* data valid */ +input [15 -1:0] cdma2sc_dat_entries; +input [13:0] cdma2sc_dat_slices; +output sc2cdma_dat_updt; /* data valid */ +output [15 -1:0] sc2cdma_dat_entries; +output [13:0] sc2cdma_dat_slices; +input [31:0] pwrbus_ram_pd; +output sc2buf_dat_rd_en; /* data valid */ +output [14 -1:0] sc2buf_dat_rd_addr; +input sc2buf_dat_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_dat_rd_data; +output [7 -1:0] sc2buf_dat_rd_shift; +output sc2buf_dat_rd_next1_en; +output [14 -1:0] sc2buf_dat_rd_next1_addr; +`ifdef CBUF_WEIGHT_COMPRESSED +output sc2buf_wmb_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wmb_rd_addr; +input sc2buf_wmb_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wmb_rd_data; +`endif +output sc2buf_wt_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wt_rd_addr; +input sc2buf_wt_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wt_rd_data; +output sc2mac_dat_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_a_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_a_data${i}; ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_dat_a_data0; +output [8 -1:0] sc2mac_dat_a_data1; +output [8 -1:0] sc2mac_dat_a_data2; +output [8 -1:0] sc2mac_dat_a_data3; +output [8 -1:0] sc2mac_dat_a_data4; +output [8 -1:0] sc2mac_dat_a_data5; +output [8 -1:0] sc2mac_dat_a_data6; +output [8 -1:0] sc2mac_dat_a_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] sc2mac_dat_a_pd; +output sc2mac_dat_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_b_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_b_data${i}; ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_dat_b_data0; +output [8 -1:0] sc2mac_dat_b_data1; +output [8 -1:0] sc2mac_dat_b_data2; +output [8 -1:0] sc2mac_dat_b_data3; +output [8 -1:0] sc2mac_dat_b_data4; +output [8 -1:0] sc2mac_dat_b_data5; +output [8 -1:0] sc2mac_dat_b_data6; +output [8 -1:0] sc2mac_dat_b_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] sc2mac_dat_b_pd; +output sc2mac_wt_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_a_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_wt_a_data${i}; ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_wt_a_data0; +output [8 -1:0] sc2mac_wt_a_data1; +output [8 -1:0] sc2mac_wt_a_data2; +output [8 -1:0] sc2mac_wt_a_data3; +output [8 -1:0] sc2mac_wt_a_data4; +output [8 -1:0] sc2mac_wt_a_data5; +output [8 -1:0] sc2mac_wt_a_data6; +output [8 -1:0] sc2mac_wt_a_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8/2 -1:0] sc2mac_wt_a_sel; +output sc2mac_wt_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_b_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_wt_b_data${i}; ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_wt_b_data0; +output [8 -1:0] sc2mac_wt_b_data1; +output [8 -1:0] sc2mac_wt_b_data2; +output [8 -1:0] sc2mac_wt_b_data3; +output [8 -1:0] sc2mac_wt_b_data4; +output [8 -1:0] sc2mac_wt_b_data5; +output [8 -1:0] sc2mac_wt_b_data6; +output [8 -1:0] sc2mac_wt_b_data7; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8/2 -1:0] sc2mac_wt_b_sel; +input cdma2sc_wt_updt; /* data valid */ +input [13:0] cdma2sc_wt_kernels; +input [15 -1:0] cdma2sc_wt_entries; +input [8:0] cdma2sc_wmb_entries; +output sc2cdma_wt_updt; /* data valid */ +output [13:0] sc2cdma_wt_kernels; +output [15 -1:0] sc2cdma_wt_entries; +output [8:0] sc2cdma_wmb_entries; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire dp2reg_done; +wire nvdla_op_gated_clk_0; +wire nvdla_op_gated_clk_1; +wire nvdla_op_gated_clk_2; +wire nvdla_wg_gated_clk; +wire [20:0] reg2dp_atomics; +wire [4:0] reg2dp_batches; +wire [0:0] reg2dp_conv_mode; +wire [2:0] reg2dp_conv_x_stride_ext; +wire [2:0] reg2dp_conv_y_stride_ext; +wire [31:0] reg2dp_cya; +wire [4:0] reg2dp_data_bank; +wire [0:0] reg2dp_data_reuse; +wire [12:0] reg2dp_datain_channel_ext; +wire [0:0] reg2dp_datain_format; +wire [12:0] reg2dp_datain_height_ext; +wire [12:0] reg2dp_datain_width_ext; +wire [12:0] reg2dp_dataout_channel; +wire [12:0] reg2dp_dataout_height; +wire [12:0] reg2dp_dataout_width; +wire [13:0] reg2dp_entries; +wire [1:0] reg2dp_in_precision; +wire [0:0] reg2dp_op_en; +wire [4:0] reg2dp_pad_left; +wire [4:0] reg2dp_pad_top; +wire [15:0] reg2dp_pad_value; +wire [1:0] reg2dp_pra_truncate; +wire [1:0] reg2dp_proc_precision; +wire [11:0] reg2dp_rls_slices; +wire [0:0] reg2dp_skip_data_rls; +wire [0:0] reg2dp_skip_weight_rls; +wire [4:0] reg2dp_weight_bank; +wire [31:0] reg2dp_weight_bytes; +wire [12:0] reg2dp_weight_channel_ext; +wire [0:0] reg2dp_weight_format; +wire [4:0] reg2dp_weight_height_ext; +wire [12:0] reg2dp_weight_kernel; +wire [0:0] reg2dp_weight_reuse; +wire [4:0] reg2dp_weight_width_ext; +wire [27:0] reg2dp_wmb_bytes; +wire [4:0] reg2dp_x_dilation_ext; +wire [4:0] reg2dp_y_dilation_ext; +wire [1:0] reg2dp_y_extension; +wire [1:0] sc_state; +wire [30:0] sg2dl_pd; +wire sg2dl_pvld; +wire sg2dl_reuse_rls; +wire [17:0] sg2wl_pd; +wire sg2wl_pvld; +wire sg2wl_reuse_rls; +wire [3:0] slcg_op_en; +wire slcg_wg_en; +//========================================================== +// Regfile +//========================================================== +NV_NVDLA_CSC_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) //|< i + ,.csb2csc_req_pvld (csb2csc_req_pvld) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.csb2csc_req_prdy (csb2csc_req_prdy) //|> o + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) //|> o + ,.csc2csb_resp_valid (csc2csb_resp_valid) //|> o + ,.reg2dp_atomics (reg2dp_atomics[20:0]) //|> w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|> w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w + ,.reg2dp_conv_x_stride_ext (reg2dp_conv_x_stride_ext[2:0]) //|> w + ,.reg2dp_conv_y_stride_ext (reg2dp_conv_y_stride_ext[2:0]) //|> w + ,.reg2dp_cya (reg2dp_cya[31:0]) //|> w * + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|> w + ,.reg2dp_data_reuse (reg2dp_data_reuse) //|> w + ,.reg2dp_datain_channel_ext (reg2dp_datain_channel_ext[12:0]) //|> w + ,.reg2dp_datain_format (reg2dp_datain_format) //|> w + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) //|> w + ,.reg2dp_datain_width_ext (reg2dp_datain_width_ext[12:0]) //|> w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel[12:0]) //|> w * + ,.reg2dp_dataout_height (reg2dp_dataout_height[12:0]) //|> w + ,.reg2dp_dataout_width (reg2dp_dataout_width[12:0]) //|> w + ,.reg2dp_entries (reg2dp_entries[13:0]) //|> w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) //|> w + ,.reg2dp_pad_top (reg2dp_pad_top[4:0]) //|> w + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) //|> w + ,.reg2dp_pra_truncate (reg2dp_pra_truncate[1:0]) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|> w + ,.reg2dp_rls_slices (reg2dp_rls_slices[11:0]) //|> w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls) //|> w + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls) //|> w + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) //|> w + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) //|> w + ,.reg2dp_weight_channel_ext (reg2dp_weight_channel_ext[12:0]) //|> w + ,.reg2dp_weight_format (reg2dp_weight_format) //|> w + ,.reg2dp_weight_height_ext (reg2dp_weight_height_ext[4:0]) //|> w + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) //|> w + ,.reg2dp_weight_reuse (reg2dp_weight_reuse) //|> w + ,.reg2dp_weight_width_ext (reg2dp_weight_width_ext[4:0]) //|> w + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) //|> w + ,.reg2dp_x_dilation_ext (reg2dp_x_dilation_ext[4:0]) //|> w + ,.reg2dp_y_dilation_ext (reg2dp_y_dilation_ext[4:0]) //|> w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|> w + ,.slcg_op_en (slcg_op_en[3:0]) //|> w + ); +//========================================================== +// Sequence generator +//========================================================== +NV_NVDLA_CSC_sg u_sg ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dp2reg_done (dp2reg_done) //|> w + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) //|< i + ,.cdma2sc_dat_entries (cdma2sc_dat_entries[15 -1:0]) //|< i + ,.cdma2sc_dat_slices (cdma2sc_dat_slices[13:0]) //|< i + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) //|< i + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels[13:0]) //|< i + ,.cdma2sc_wt_entries (cdma2sc_wt_entries[15 -1:0]) //|< i + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries[8:0]) //|< i + ,.sg2dl_pvld (sg2dl_pvld) //|> w + ,.sg2dl_pd (sg2dl_pd[30:0]) //|> w + ,.sg2wl_pvld (sg2wl_pvld) //|> w + ,.sg2wl_pd (sg2wl_pd[17:0]) //|> w + ,.accu2sc_credit_vld (accu2sc_credit_vld) //|< i + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) //|< i + ,.sc_state (sc_state[1:0]) //|> w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|> o + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) //|> o + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) //|< i + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) //|< i + ,.sg2dl_reuse_rls (sg2dl_reuse_rls) //|> w + ,.sg2wl_reuse_rls (sg2wl_reuse_rls) //|> w + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) //|< w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) //|< w + ,.reg2dp_weight_reuse (reg2dp_weight_reuse[0]) //|< w + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls[0]) //|< w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|< w + ,.reg2dp_datain_format (reg2dp_datain_format[0]) //|< w + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) //|< w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|< w + ,.reg2dp_weight_width_ext (reg2dp_weight_width_ext[4:0]) //|< w + ,.reg2dp_weight_height_ext (reg2dp_weight_height_ext[4:0]) //|< w + ,.reg2dp_weight_channel_ext (reg2dp_weight_channel_ext[12:0]) //|< w + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) //|< w + ,.reg2dp_dataout_width (reg2dp_dataout_width[12:0]) //|< w + ,.reg2dp_dataout_height (reg2dp_dataout_height[12:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) //|< w + ,.reg2dp_atomics (reg2dp_atomics[20:0]) //|< w + ,.reg2dp_rls_slices (reg2dp_rls_slices[11:0]) //|< w + ); +//========================================================== +// Weight loader +//========================================================== +NV_NVDLA_CSC_wl u_wl ( + .nvdla_core_clk (nvdla_op_gated_clk_1) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sg2wl_pvld (sg2wl_pvld) //|< w + ,.sg2wl_pd (sg2wl_pd[17:0]) //|< w + ,.sc_state (sc_state[1:0]) //|< w + ,.sg2wl_reuse_rls (sg2wl_reuse_rls) //|< w + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) //|< o + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) //|< i + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels[13:0]) //|< i + ,.cdma2sc_wt_entries (cdma2sc_wt_entries[15 -1:0]) //|< i + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries[8:0]) //|< i + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) //|> o + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels[13:0]) //|> o + ,.sc2cdma_wt_entries (sc2cdma_wt_entries[15 -1:0]) //|> o + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries[8:0]) //|> o + ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) //|> o + ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr[14 -1:0]) //|> o + ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) //|< i + ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data) //|< i + `ifdef CBUF_WEIGHT_COMPRESSED + ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) //|> o + ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr[14 -1:0]) //|> o + ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) //|< i + ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data) //|< i + `endif + ,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld) //|> o + ,.sc2mac_wt_a_mask (sc2mac_wt_a_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_wt_a_data${i} (sc2mac_wt_a_data${i}[${kk}:0]) ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_a_data0 (sc2mac_wt_a_data0[7:0]) +,.sc2mac_wt_a_data1 (sc2mac_wt_a_data1[7:0]) +,.sc2mac_wt_a_data2 (sc2mac_wt_a_data2[7:0]) +,.sc2mac_wt_a_data3 (sc2mac_wt_a_data3[7:0]) +,.sc2mac_wt_a_data4 (sc2mac_wt_a_data4[7:0]) +,.sc2mac_wt_a_data5 (sc2mac_wt_a_data5[7:0]) +,.sc2mac_wt_a_data6 (sc2mac_wt_a_data6[7:0]) +,.sc2mac_wt_a_data7 (sc2mac_wt_a_data7[7:0]) +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_a_sel (sc2mac_wt_a_sel[8/2 -1:0]) //|> o + ,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld) //|> o + ,.sc2mac_wt_b_mask (sc2mac_wt_b_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_wt_b_data${i} (sc2mac_wt_b_data${i}[${kk}:0]) ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_b_data0 (sc2mac_wt_b_data0[7:0]) +,.sc2mac_wt_b_data1 (sc2mac_wt_b_data1[7:0]) +,.sc2mac_wt_b_data2 (sc2mac_wt_b_data2[7:0]) +,.sc2mac_wt_b_data3 (sc2mac_wt_b_data3[7:0]) +,.sc2mac_wt_b_data4 (sc2mac_wt_b_data4[7:0]) +,.sc2mac_wt_b_data5 (sc2mac_wt_b_data5[7:0]) +,.sc2mac_wt_b_data6 (sc2mac_wt_b_data6[7:0]) +,.sc2mac_wt_b_data7 (sc2mac_wt_b_data7[7:0]) +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_b_sel (sc2mac_wt_b_sel[8/2 -1:0]) //|> o + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|< w + ,.reg2dp_weight_reuse (reg2dp_weight_reuse[0]) //|< w + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls[0]) //|< w + ,.reg2dp_weight_format (reg2dp_weight_format[0]) //|< w + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) //|< w + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) //|< w + ); +//========================================================== +// Data loader +//========================================================== +NV_NVDLA_CSC_dl u_dl ( + .nvdla_core_clk (nvdla_op_gated_clk_2) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sg2dl_pvld (sg2dl_pvld) //|< w + ,.sg2dl_pd (sg2dl_pd[30:0]) //|< w + ,.sc_state (sc_state[1:0]) //|< w + ,.sg2dl_reuse_rls (sg2dl_reuse_rls) //|< w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|< o + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) //|< i + ,.cdma2sc_dat_entries (cdma2sc_dat_entries[15 -1:0]) //|< i + ,.cdma2sc_dat_slices (cdma2sc_dat_slices[13:0]) //|< i + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) //|> o + ,.sc2cdma_dat_entries (sc2cdma_dat_entries[15 -1:0]) //|> o + ,.sc2cdma_dat_slices (sc2cdma_dat_slices[13:0]) //|> o + ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) //|> o + ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr[14 -1:0]) //|> o + ,.sc2buf_dat_rd_shift (sc2buf_dat_rd_shift) + ,.sc2buf_dat_rd_next1_en (sc2buf_dat_rd_next1_en) + ,.sc2buf_dat_rd_next1_addr (sc2buf_dat_rd_next1_addr) + ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) //|< i + ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data) //|< i + ,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld) //|> o + ,.sc2mac_dat_a_mask (sc2mac_dat_a_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_dat_a_data${i} (sc2mac_dat_a_data${i}[${kk}:0]) ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_a_data0 (sc2mac_dat_a_data0[7:0]) +,.sc2mac_dat_a_data1 (sc2mac_dat_a_data1[7:0]) +,.sc2mac_dat_a_data2 (sc2mac_dat_a_data2[7:0]) +,.sc2mac_dat_a_data3 (sc2mac_dat_a_data3[7:0]) +,.sc2mac_dat_a_data4 (sc2mac_dat_a_data4[7:0]) +,.sc2mac_dat_a_data5 (sc2mac_dat_a_data5[7:0]) +,.sc2mac_dat_a_data6 (sc2mac_dat_a_data6[7:0]) +,.sc2mac_dat_a_data7 (sc2mac_dat_a_data7[7:0]) +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_a_pd (sc2mac_dat_a_pd[8:0]) //|> o + ,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld) //|> o + ,.sc2mac_dat_b_mask (sc2mac_dat_b_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_dat_b_data${i} (sc2mac_dat_b_data${i}[${kk}:0]) ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_b_data0 (sc2mac_dat_b_data0[7:0]) +,.sc2mac_dat_b_data1 (sc2mac_dat_b_data1[7:0]) +,.sc2mac_dat_b_data2 (sc2mac_dat_b_data2[7:0]) +,.sc2mac_dat_b_data3 (sc2mac_dat_b_data3[7:0]) +,.sc2mac_dat_b_data4 (sc2mac_dat_b_data4[7:0]) +,.sc2mac_dat_b_data5 (sc2mac_dat_b_data5[7:0]) +,.sc2mac_dat_b_data6 (sc2mac_dat_b_data6[7:0]) +,.sc2mac_dat_b_data7 (sc2mac_dat_b_data7[7:0]) +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_b_pd (sc2mac_dat_b_pd[8:0]) //|> o + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.nvdla_wg_clk (nvdla_wg_gated_clk) //|< w + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) //|< w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_datain_format (reg2dp_datain_format[0]) //|< w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) //|< w + ,.reg2dp_datain_channel_ext (reg2dp_datain_channel_ext[12:0]) //|< w + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) //|< w + ,.reg2dp_datain_width_ext (reg2dp_datain_width_ext[12:0]) //|< w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|< w + ,.reg2dp_weight_channel_ext (reg2dp_weight_channel_ext[12:0]) //|< w + ,.reg2dp_entries (reg2dp_entries[13:0]) //|< w + ,.reg2dp_dataout_width (reg2dp_dataout_width[12:0]) //|< w + ,.reg2dp_rls_slices (reg2dp_rls_slices[11:0]) //|< w + ,.reg2dp_conv_x_stride_ext (reg2dp_conv_x_stride_ext[2:0]) //|< w + ,.reg2dp_conv_y_stride_ext (reg2dp_conv_y_stride_ext[2:0]) //|< w + ,.reg2dp_x_dilation_ext (reg2dp_x_dilation_ext[4:0]) //|< w + ,.reg2dp_y_dilation_ext (reg2dp_y_dilation_ext[4:0]) //|< w + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) //|< w + ,.reg2dp_pad_top (reg2dp_pad_top[4:0]) //|< w + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_pra_truncate (reg2dp_pra_truncate[1:0]) //|< w + ,.slcg_wg_en (slcg_wg_en) //|> w + ); +//========================================================== +// SLCG groups +//========================================================== +NV_NVDLA_CSC_slcg u_slcg_op_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[0]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w + ); +NV_NVDLA_CSC_slcg u_slcg_op_1 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[1]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w + ); +NV_NVDLA_CSC_slcg u_slcg_op_2 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[2]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w + ); +NV_NVDLA_CSC_slcg u_slcg_wg ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[3]) //|< w + ,.slcg_en_src_1 (slcg_wg_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_wg_gated_clk) //|> w + ); +endmodule // NV_NVDLA_csc diff --git a/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.v.vcp b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.v.vcp new file mode 100644 index 0000000..6b33b90 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/csc/NV_NVDLA_csc.v.vcp @@ -0,0 +1,517 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_csc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +module NV_NVDLA_csc ( + accu2sc_credit_size //|< i + ,accu2sc_credit_vld //|< i + ,cdma2sc_dat_entries //|< i + ,cdma2sc_dat_pending_ack //|< i + ,cdma2sc_dat_slices //|< i + ,cdma2sc_dat_updt //|< i + ,cdma2sc_wmb_entries //|< i + ,cdma2sc_wt_entries //|< i + ,cdma2sc_wt_kernels //|< i + ,cdma2sc_wt_pending_ack //|< i + ,cdma2sc_wt_updt //|< i + ,csb2csc_req_pd //|< i + ,csb2csc_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,sc2buf_dat_rd_data //|< i + ,sc2buf_dat_rd_valid //|< i + ,sc2buf_dat_rd_shift //|> o + ,sc2buf_dat_rd_next1_en //|> o + ,sc2buf_dat_rd_next1_addr //|> o + ,sc2buf_wt_rd_data //|< i + ,sc2buf_wt_rd_valid //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,csb2csc_req_prdy //|> o + ,csc2csb_resp_pd //|> o + ,csc2csb_resp_valid //|> o + ,sc2buf_dat_rd_addr //|> o + ,sc2buf_dat_rd_en //|> o + ,sc2buf_wt_rd_addr //|> o + ,sc2buf_wt_rd_en //|> o + ,sc2cdma_dat_entries //|> o + ,sc2cdma_dat_pending_req //|> o + ,sc2cdma_dat_slices //|> o + ,sc2cdma_dat_updt //|> o + ,sc2cdma_wmb_entries //|> o + ,sc2cdma_wt_entries //|> o + ,sc2cdma_wt_kernels //|> o + ,sc2cdma_wt_pending_req //|> o + ,sc2cdma_wt_updt //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_a_data${i} //|> o ); +//: } + ,sc2mac_dat_a_mask //|> o + ,sc2mac_dat_a_pd //|> o + ,sc2mac_dat_a_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_b_data${i} //|> o ); +//: } + ,sc2mac_dat_b_mask //|> o + ,sc2mac_dat_b_pd //|> o + ,sc2mac_dat_b_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_a_data${i} //|> o ); +//: } + ,sc2mac_wt_a_mask //|> o + ,sc2mac_wt_a_pvld //|> o + ,sc2mac_wt_a_sel //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_b_data${i} //|> o ); +//: } + ,sc2mac_wt_b_mask //|> o + ,sc2mac_wt_b_pvld //|> o + ,sc2mac_wt_b_sel //|> o + `ifdef CBUF_WEIGHT_COMPRESSED + ,sc2buf_wmb_rd_addr //|> o + ,sc2buf_wmb_rd_en //|> o + ,sc2buf_wmb_rd_data //|< i + ,sc2buf_wmb_rd_valid //|< i + `endif + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output sc2cdma_dat_pending_req; +output sc2cdma_wt_pending_req; +input accu2sc_credit_vld; /* data valid */ +input [2:0] accu2sc_credit_size; +input cdma2sc_dat_pending_ack; +input cdma2sc_wt_pending_ack; +input csb2csc_req_pvld; /* data valid */ +output csb2csc_req_prdy; /* data return handshake */ +input [62:0] csb2csc_req_pd; +output csc2csb_resp_valid; /* data valid */ +output [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input cdma2sc_dat_updt; /* data valid */ +input [15 -1:0] cdma2sc_dat_entries; +input [13:0] cdma2sc_dat_slices; +output sc2cdma_dat_updt; /* data valid */ +output [15 -1:0] sc2cdma_dat_entries; +output [13:0] sc2cdma_dat_slices; +input [31:0] pwrbus_ram_pd; +output sc2buf_dat_rd_en; /* data valid */ +output [14 -1:0] sc2buf_dat_rd_addr; +input sc2buf_dat_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_dat_rd_data; +output [7 -1:0] sc2buf_dat_rd_shift; +output sc2buf_dat_rd_next1_en; +output [14 -1:0] sc2buf_dat_rd_next1_addr; +`ifdef CBUF_WEIGHT_COMPRESSED +output sc2buf_wmb_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wmb_rd_addr; +input sc2buf_wmb_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wmb_rd_data; +`endif +output sc2buf_wt_rd_en; /* data valid */ +output [14 -1:0] sc2buf_wt_rd_addr; +input sc2buf_wt_rd_valid; /* data valid */ +input [64 -1:0] sc2buf_wt_rd_data; +output sc2mac_dat_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_a_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_a_data${i}; ); +//: } +output [8:0] sc2mac_dat_a_pd; +output sc2mac_dat_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_b_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_dat_b_data${i}; ); +//: } +output [8:0] sc2mac_dat_b_pd; +output sc2mac_wt_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_a_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_wt_a_data${i}; ); +//: } +output [8/2 -1:0] sc2mac_wt_a_sel; +output sc2mac_wt_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_b_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: output [8 -1:0] sc2mac_wt_b_data${i}; ); +//: } +output [8/2 -1:0] sc2mac_wt_b_sel; +input cdma2sc_wt_updt; /* data valid */ +input [13:0] cdma2sc_wt_kernels; +input [15 -1:0] cdma2sc_wt_entries; +input [8:0] cdma2sc_wmb_entries; +output sc2cdma_wt_updt; /* data valid */ +output [13:0] sc2cdma_wt_kernels; +output [15 -1:0] sc2cdma_wt_entries; +output [8:0] sc2cdma_wmb_entries; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire dp2reg_done; +wire nvdla_op_gated_clk_0; +wire nvdla_op_gated_clk_1; +wire nvdla_op_gated_clk_2; +wire nvdla_wg_gated_clk; +wire [20:0] reg2dp_atomics; +wire [4:0] reg2dp_batches; +wire [0:0] reg2dp_conv_mode; +wire [2:0] reg2dp_conv_x_stride_ext; +wire [2:0] reg2dp_conv_y_stride_ext; +wire [31:0] reg2dp_cya; +wire [4:0] reg2dp_data_bank; +wire [0:0] reg2dp_data_reuse; +wire [12:0] reg2dp_datain_channel_ext; +wire [0:0] reg2dp_datain_format; +wire [12:0] reg2dp_datain_height_ext; +wire [12:0] reg2dp_datain_width_ext; +wire [12:0] reg2dp_dataout_channel; +wire [12:0] reg2dp_dataout_height; +wire [12:0] reg2dp_dataout_width; +wire [13:0] reg2dp_entries; +wire [1:0] reg2dp_in_precision; +wire [0:0] reg2dp_op_en; +wire [4:0] reg2dp_pad_left; +wire [4:0] reg2dp_pad_top; +wire [15:0] reg2dp_pad_value; +wire [1:0] reg2dp_pra_truncate; +wire [1:0] reg2dp_proc_precision; +wire [11:0] reg2dp_rls_slices; +wire [0:0] reg2dp_skip_data_rls; +wire [0:0] reg2dp_skip_weight_rls; +wire [4:0] reg2dp_weight_bank; +wire [31:0] reg2dp_weight_bytes; +wire [12:0] reg2dp_weight_channel_ext; +wire [0:0] reg2dp_weight_format; +wire [4:0] reg2dp_weight_height_ext; +wire [12:0] reg2dp_weight_kernel; +wire [0:0] reg2dp_weight_reuse; +wire [4:0] reg2dp_weight_width_ext; +wire [27:0] reg2dp_wmb_bytes; +wire [4:0] reg2dp_x_dilation_ext; +wire [4:0] reg2dp_y_dilation_ext; +wire [1:0] reg2dp_y_extension; +wire [1:0] sc_state; +wire [30:0] sg2dl_pd; +wire sg2dl_pvld; +wire sg2dl_reuse_rls; +wire [17:0] sg2wl_pd; +wire sg2wl_pvld; +wire sg2wl_reuse_rls; +wire [3:0] slcg_op_en; +wire slcg_wg_en; +//========================================================== +// Regfile +//========================================================== +NV_NVDLA_CSC_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) //|< i + ,.csb2csc_req_pvld (csb2csc_req_pvld) //|< i + ,.dp2reg_done (dp2reg_done) //|< w + ,.csb2csc_req_prdy (csb2csc_req_prdy) //|> o + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) //|> o + ,.csc2csb_resp_valid (csc2csb_resp_valid) //|> o + ,.reg2dp_atomics (reg2dp_atomics[20:0]) //|> w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|> w + ,.reg2dp_conv_mode (reg2dp_conv_mode) //|> w + ,.reg2dp_conv_x_stride_ext (reg2dp_conv_x_stride_ext[2:0]) //|> w + ,.reg2dp_conv_y_stride_ext (reg2dp_conv_y_stride_ext[2:0]) //|> w + ,.reg2dp_cya (reg2dp_cya[31:0]) //|> w * + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|> w + ,.reg2dp_data_reuse (reg2dp_data_reuse) //|> w + ,.reg2dp_datain_channel_ext (reg2dp_datain_channel_ext[12:0]) //|> w + ,.reg2dp_datain_format (reg2dp_datain_format) //|> w + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) //|> w + ,.reg2dp_datain_width_ext (reg2dp_datain_width_ext[12:0]) //|> w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel[12:0]) //|> w * + ,.reg2dp_dataout_height (reg2dp_dataout_height[12:0]) //|> w + ,.reg2dp_dataout_width (reg2dp_dataout_width[12:0]) //|> w + ,.reg2dp_entries (reg2dp_entries[13:0]) //|> w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) //|> w + ,.reg2dp_pad_top (reg2dp_pad_top[4:0]) //|> w + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) //|> w + ,.reg2dp_pra_truncate (reg2dp_pra_truncate[1:0]) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|> w + ,.reg2dp_rls_slices (reg2dp_rls_slices[11:0]) //|> w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls) //|> w + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls) //|> w + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) //|> w + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) //|> w + ,.reg2dp_weight_channel_ext (reg2dp_weight_channel_ext[12:0]) //|> w + ,.reg2dp_weight_format (reg2dp_weight_format) //|> w + ,.reg2dp_weight_height_ext (reg2dp_weight_height_ext[4:0]) //|> w + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) //|> w + ,.reg2dp_weight_reuse (reg2dp_weight_reuse) //|> w + ,.reg2dp_weight_width_ext (reg2dp_weight_width_ext[4:0]) //|> w + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) //|> w + ,.reg2dp_x_dilation_ext (reg2dp_x_dilation_ext[4:0]) //|> w + ,.reg2dp_y_dilation_ext (reg2dp_y_dilation_ext[4:0]) //|> w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|> w + ,.slcg_op_en (slcg_op_en[3:0]) //|> w + ); +//========================================================== +// Sequence generator +//========================================================== +NV_NVDLA_CSC_sg u_sg ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dp2reg_done (dp2reg_done) //|> w + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) //|< i + ,.cdma2sc_dat_entries (cdma2sc_dat_entries[15 -1:0]) //|< i + ,.cdma2sc_dat_slices (cdma2sc_dat_slices[13:0]) //|< i + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) //|< i + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels[13:0]) //|< i + ,.cdma2sc_wt_entries (cdma2sc_wt_entries[15 -1:0]) //|< i + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries[8:0]) //|< i + ,.sg2dl_pvld (sg2dl_pvld) //|> w + ,.sg2dl_pd (sg2dl_pd[30:0]) //|> w + ,.sg2wl_pvld (sg2wl_pvld) //|> w + ,.sg2wl_pd (sg2wl_pd[17:0]) //|> w + ,.accu2sc_credit_vld (accu2sc_credit_vld) //|< i + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) //|< i + ,.sc_state (sc_state[1:0]) //|> w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|> o + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) //|> o + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) //|< i + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) //|< i + ,.sg2dl_reuse_rls (sg2dl_reuse_rls) //|> w + ,.sg2wl_reuse_rls (sg2wl_reuse_rls) //|> w + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_data_reuse (reg2dp_data_reuse[0]) //|< w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) //|< w + ,.reg2dp_weight_reuse (reg2dp_weight_reuse[0]) //|< w + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls[0]) //|< w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|< w + ,.reg2dp_datain_format (reg2dp_datain_format[0]) //|< w + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) //|< w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|< w + ,.reg2dp_weight_width_ext (reg2dp_weight_width_ext[4:0]) //|< w + ,.reg2dp_weight_height_ext (reg2dp_weight_height_ext[4:0]) //|< w + ,.reg2dp_weight_channel_ext (reg2dp_weight_channel_ext[12:0]) //|< w + ,.reg2dp_weight_kernel (reg2dp_weight_kernel[12:0]) //|< w + ,.reg2dp_dataout_width (reg2dp_dataout_width[12:0]) //|< w + ,.reg2dp_dataout_height (reg2dp_dataout_height[12:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) //|< w + ,.reg2dp_atomics (reg2dp_atomics[20:0]) //|< w + ,.reg2dp_rls_slices (reg2dp_rls_slices[11:0]) //|< w + ); +//========================================================== +// Weight loader +//========================================================== +NV_NVDLA_CSC_wl u_wl ( + .nvdla_core_clk (nvdla_op_gated_clk_1) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sg2wl_pvld (sg2wl_pvld) //|< w + ,.sg2wl_pd (sg2wl_pd[17:0]) //|< w + ,.sc_state (sc_state[1:0]) //|< w + ,.sg2wl_reuse_rls (sg2wl_reuse_rls) //|< w + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) //|< o + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) //|< i + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels[13:0]) //|< i + ,.cdma2sc_wt_entries (cdma2sc_wt_entries[15 -1:0]) //|< i + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries[8:0]) //|< i + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) //|> o + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels[13:0]) //|> o + ,.sc2cdma_wt_entries (sc2cdma_wt_entries[15 -1:0]) //|> o + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries[8:0]) //|> o + ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) //|> o + ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr[14 -1:0]) //|> o + ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) //|< i + ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data) //|< i + `ifdef CBUF_WEIGHT_COMPRESSED + ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) //|> o + ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr[14 -1:0]) //|> o + ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) //|< i + ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data) //|< i + `endif + ,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld) //|> o + ,.sc2mac_wt_a_mask (sc2mac_wt_a_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_wt_a_data${i} (sc2mac_wt_a_data${i}[${kk}:0]) ) +//: } + ,.sc2mac_wt_a_sel (sc2mac_wt_a_sel[8/2 -1:0]) //|> o + ,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld) //|> o + ,.sc2mac_wt_b_mask (sc2mac_wt_b_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_wt_b_data${i} (sc2mac_wt_b_data${i}[${kk}:0]) ) +//: } + ,.sc2mac_wt_b_sel (sc2mac_wt_b_sel[8/2 -1:0]) //|> o + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|< w + ,.reg2dp_weight_reuse (reg2dp_weight_reuse[0]) //|< w + ,.reg2dp_skip_weight_rls (reg2dp_skip_weight_rls[0]) //|< w + ,.reg2dp_weight_format (reg2dp_weight_format[0]) //|< w + ,.reg2dp_weight_bytes (reg2dp_weight_bytes[31:0]) //|< w + ,.reg2dp_wmb_bytes (reg2dp_wmb_bytes[27:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_weight_bank (reg2dp_weight_bank[4:0]) //|< w + ); +//========================================================== +// Data loader +//========================================================== +NV_NVDLA_CSC_dl u_dl ( + .nvdla_core_clk (nvdla_op_gated_clk_2) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sg2dl_pvld (sg2dl_pvld) //|< w + ,.sg2dl_pd (sg2dl_pd[30:0]) //|< w + ,.sc_state (sc_state[1:0]) //|< w + ,.sg2dl_reuse_rls (sg2dl_reuse_rls) //|< w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|< o + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) //|< i + ,.cdma2sc_dat_entries (cdma2sc_dat_entries[15 -1:0]) //|< i + ,.cdma2sc_dat_slices (cdma2sc_dat_slices[13:0]) //|< i + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) //|> o + ,.sc2cdma_dat_entries (sc2cdma_dat_entries[15 -1:0]) //|> o + ,.sc2cdma_dat_slices (sc2cdma_dat_slices[13:0]) //|> o + ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) //|> o + ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr[14 -1:0]) //|> o + ,.sc2buf_dat_rd_shift (sc2buf_dat_rd_shift) + ,.sc2buf_dat_rd_next1_en (sc2buf_dat_rd_next1_en) + ,.sc2buf_dat_rd_next1_addr (sc2buf_dat_rd_next1_addr) + ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) //|< i + ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data) //|< i + ,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld) //|> o + ,.sc2mac_dat_a_mask (sc2mac_dat_a_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_dat_a_data${i} (sc2mac_dat_a_data${i}[${kk}:0]) ) +//: } + ,.sc2mac_dat_a_pd (sc2mac_dat_a_pd[8:0]) //|> o + ,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld) //|> o + ,.sc2mac_dat_b_mask (sc2mac_dat_b_mask[8 -1:0]) //|> o +//: my $kk=8 -1; +//: for(my $i=0; $i<8; $i++){ +//: print qq( +//: ,.sc2mac_dat_b_data${i} (sc2mac_dat_b_data${i}[${kk}:0]) ) +//: } + ,.sc2mac_dat_b_pd (sc2mac_dat_b_pd[8:0]) //|> o + ,.nvdla_core_ng_clk (nvdla_core_clk) //|< i + ,.nvdla_wg_clk (nvdla_wg_gated_clk) //|< w + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_conv_mode (reg2dp_conv_mode[0]) //|< w + ,.reg2dp_batches (reg2dp_batches[4:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_datain_format (reg2dp_datain_format[0]) //|< w + ,.reg2dp_skip_data_rls (reg2dp_skip_data_rls[0]) //|< w + ,.reg2dp_datain_channel_ext (reg2dp_datain_channel_ext[12:0]) //|< w + ,.reg2dp_datain_height_ext (reg2dp_datain_height_ext[12:0]) //|< w + ,.reg2dp_datain_width_ext (reg2dp_datain_width_ext[12:0]) //|< w + ,.reg2dp_y_extension (reg2dp_y_extension[1:0]) //|< w + ,.reg2dp_weight_channel_ext (reg2dp_weight_channel_ext[12:0]) //|< w + ,.reg2dp_entries (reg2dp_entries[13:0]) //|< w + ,.reg2dp_dataout_width (reg2dp_dataout_width[12:0]) //|< w + ,.reg2dp_rls_slices (reg2dp_rls_slices[11:0]) //|< w + ,.reg2dp_conv_x_stride_ext (reg2dp_conv_x_stride_ext[2:0]) //|< w + ,.reg2dp_conv_y_stride_ext (reg2dp_conv_y_stride_ext[2:0]) //|< w + ,.reg2dp_x_dilation_ext (reg2dp_x_dilation_ext[4:0]) //|< w + ,.reg2dp_y_dilation_ext (reg2dp_y_dilation_ext[4:0]) //|< w + ,.reg2dp_pad_left (reg2dp_pad_left[4:0]) //|< w + ,.reg2dp_pad_top (reg2dp_pad_top[4:0]) //|< w + ,.reg2dp_pad_value (reg2dp_pad_value[15:0]) //|< w + ,.reg2dp_data_bank (reg2dp_data_bank[4:0]) //|< w + ,.reg2dp_pra_truncate (reg2dp_pra_truncate[1:0]) //|< w + ,.slcg_wg_en (slcg_wg_en) //|> w + ); +//========================================================== +// SLCG groups +//========================================================== +NV_NVDLA_CSC_slcg u_slcg_op_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[0]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w + ); +NV_NVDLA_CSC_slcg u_slcg_op_1 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[1]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w + ); +NV_NVDLA_CSC_slcg u_slcg_op_2 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[2]) //|< w + ,.slcg_en_src_1 (1'b1) //|< ? + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w + ); +NV_NVDLA_CSC_slcg u_slcg_wg ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src_0 (slcg_op_en[3]) //|< w + ,.slcg_en_src_1 (slcg_wg_en) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_wg_gated_clk) //|> w + ); +endmodule // NV_NVDLA_csc diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v new file mode 100644 index 0000000..b0a60ae --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v @@ -0,0 +1,321 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_CSB_reg.v +module NV_NVDLA_GLB_CSB_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cacc_done_mask0 + ,cacc_done_mask1 + ,cdma_dat_done_mask0 + ,cdma_dat_done_mask1 + ,cdma_wt_done_mask0 + ,cdma_wt_done_mask1 + ,cdp_done_mask0 + ,cdp_done_mask1 + ,pdp_done_mask0 + ,pdp_done_mask1 + ,sdp_done_mask0 + ,sdp_done_mask1 + ,sdp_done_set0_trigger + ,sdp_done_status0_trigger + ,cacc_done_set0 + ,cacc_done_set1 + ,cdma_dat_done_set0 + ,cdma_dat_done_set1 + ,cdma_wt_done_set0 + ,cdma_wt_done_set1 + ,cdp_done_set0 + ,cdp_done_set1 + ,pdp_done_set0 + ,pdp_done_set1 + ,sdp_done_set0 + ,sdp_done_set1 + ,cacc_done_status0 + ,cacc_done_status1 + ,cdma_dat_done_status0 + ,cdma_dat_done_status1 + ,cdma_wt_done_status0 + ,cdma_wt_done_status1 + ,cdp_done_status0 + ,cdp_done_status1 + ,pdp_done_status0 + ,pdp_done_status1 + ,sdp_done_status0 + ,sdp_done_status1 + ); +wire [7:0] major; +wire [15:0] minor; +wire [31:0] nvdla_glb_s_intr_mask_0_out; +wire [31:0] nvdla_glb_s_intr_set_0_out; +wire [31:0] nvdla_glb_s_intr_status_0_out; +wire [31:0] nvdla_glb_s_nvdla_hw_version_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output cacc_done_mask0; +output cacc_done_mask1; +output cdma_dat_done_mask0; +output cdma_dat_done_mask1; +output cdma_wt_done_mask0; +output cdma_wt_done_mask1; +output cdp_done_mask0; +output cdp_done_mask1; +output pdp_done_mask0; +output pdp_done_mask1; +output sdp_done_mask0; +output sdp_done_mask1; +output sdp_done_set0_trigger; +output sdp_done_status0_trigger; +// Read-only register inputs +input cacc_done_set0; +input cacc_done_set1; +input cdma_dat_done_set0; +input cdma_dat_done_set1; +input cdma_wt_done_set0; +input cdma_wt_done_set1; +input cdp_done_set0; +input cdp_done_set1; +input pdp_done_set0; +input pdp_done_set1; +input sdp_done_set0; +input sdp_done_set1; +input cacc_done_status0; +input cacc_done_status1; +input cdma_dat_done_status0; +input cdma_dat_done_status1; +input cdma_wt_done_status0; +input cdma_wt_done_status1; +input cdp_done_status0; +input cdp_done_status1; +input pdp_done_status0; +input pdp_done_status1; +input sdp_done_status0; +input sdp_done_status1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +wire bdma_done_mask0 = 1'b0 ; +wire bdma_done_mask1 = 1'b0 ; +reg cacc_done_mask0; +reg cacc_done_mask1; +reg cdma_dat_done_mask0; +reg cdma_dat_done_mask1; +reg cdma_wt_done_mask0; +reg cdma_wt_done_mask1; +reg cdp_done_mask0; +reg cdp_done_mask1; +reg pdp_done_mask0; +reg pdp_done_mask1; +reg [31:0] reg_rd_data; +wire rubik_done_mask0 = 1'b0 ; +wire rubik_done_mask1 = 1'b0; +reg sdp_done_mask0; +reg sdp_done_mask1; +wire rubik_done_set1 = 1'b0; +wire rubik_done_set0 = 1'b0; +wire rubik_done_status1 = 1'b0; +wire rubik_done_status0 = 1'b0; +wire bdma_done_set1 = 1'b0; +wire bdma_done_set0 = 1'b0; +wire bdma_done_status1 = 1'b0; +wire bdma_done_status0 = 1'b0; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_glb_s_intr_mask_0_wren = (reg_offset_wr == (32'h4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_glb_s_intr_set_0_wren = (reg_offset_wr == (32'h8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_glb_s_intr_status_0_wren = (reg_offset_wr == (32'hc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_glb_s_nvdla_hw_version_0_wren = (reg_offset_wr == (32'h0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign major = 8'h31; +assign minor = 16'h3030; +assign nvdla_glb_s_intr_mask_0_out[31:0] = { 10'b0, cacc_done_mask1, cacc_done_mask0, cdma_wt_done_mask1, cdma_wt_done_mask0, cdma_dat_done_mask1, cdma_dat_done_mask0, 6'b0, rubik_done_mask1, rubik_done_mask0, bdma_done_mask1, bdma_done_mask0, pdp_done_mask1, pdp_done_mask0, cdp_done_mask1, cdp_done_mask0, sdp_done_mask1, sdp_done_mask0 }; +assign nvdla_glb_s_intr_set_0_out[31:0] = { 10'b0, cacc_done_set1, cacc_done_set0, cdma_wt_done_set1, cdma_wt_done_set0, cdma_dat_done_set1, cdma_dat_done_set0, 6'b0, rubik_done_set1, rubik_done_set0, bdma_done_set1, bdma_done_set0, pdp_done_set1, pdp_done_set0, cdp_done_set1, cdp_done_set0, sdp_done_set1, sdp_done_set0 }; +assign nvdla_glb_s_intr_status_0_out[31:0] = { 10'b0, cacc_done_status1, cacc_done_status0, cdma_wt_done_status1, cdma_wt_done_status0, cdma_dat_done_status1, cdma_dat_done_status0, 6'b0, rubik_done_status1, rubik_done_status0, bdma_done_status1, bdma_done_status0, pdp_done_status1, pdp_done_status0, cdp_done_status1, cdp_done_status0, sdp_done_status1, sdp_done_status0 }; +assign nvdla_glb_s_nvdla_hw_version_0_out[31:0] = { 8'b0, minor, major }; +assign sdp_done_set0_trigger = nvdla_glb_s_intr_set_0_wren; //(W563) +assign sdp_done_status0_trigger = nvdla_glb_s_intr_status_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_glb_s_intr_mask_0_out + or nvdla_glb_s_intr_set_0_out + or nvdla_glb_s_intr_status_0_out + or nvdla_glb_s_nvdla_hw_version_0_out + ) begin + case (reg_offset_rd_int) + (32'h4 & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_intr_mask_0_out ; + end + (32'h8 & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_intr_set_0_out ; + end + (32'hc & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_intr_status_0_out ; + end + (32'h0 & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_nvdla_hw_version_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_mask0 <= 1'b0; + cacc_done_mask1 <= 1'b0; + cdma_dat_done_mask0 <= 1'b0; + cdma_dat_done_mask1 <= 1'b0; + cdma_wt_done_mask0 <= 1'b0; + cdma_wt_done_mask1 <= 1'b0; + cdp_done_mask0 <= 1'b0; + cdp_done_mask1 <= 1'b0; + pdp_done_mask0 <= 1'b0; + pdp_done_mask1 <= 1'b0; + sdp_done_mask0 <= 1'b0; + sdp_done_mask1 <= 1'b0; + end else begin +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: bdma_done_mask1 +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cacc_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cacc_done_mask0 <= reg_wr_data[20]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cacc_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cacc_done_mask1 <= reg_wr_data[21]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_dat_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_dat_done_mask0 <= reg_wr_data[16]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_dat_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_dat_done_mask1 <= reg_wr_data[17]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_wt_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_wt_done_mask0 <= reg_wr_data[18]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_wt_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_wt_done_mask1 <= reg_wr_data[19]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdp_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdp_done_mask0 <= reg_wr_data[2]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdp_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdp_done_mask1 <= reg_wr_data[3]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: pdp_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + pdp_done_mask0 <= reg_wr_data[4]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: pdp_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + pdp_done_mask1 <= reg_wr_data[5]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: sdp_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + sdp_done_mask0 <= reg_wr_data[0]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: sdp_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + sdp_done_mask1 <= reg_wr_data[1]; + end +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::bdma_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::bdma_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cacc_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cacc_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_dat_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_dat_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_wt_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_wt_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdp_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdp_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::pdp_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::pdp_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::rubik_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::rubik_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::sdp_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::sdp_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::bdma_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::bdma_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cacc_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cacc_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_dat_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_dat_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_wt_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_wt_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdp_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdp_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::pdp_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::pdp_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::rubik_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::rubik_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::sdp_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::sdp_done_status1 (to be implemented outside) +// Not generating flops for constant field NVDLA_GLB_S_NVDLA_HW_VERSION_0::major +// Not generating flops for constant field NVDLA_GLB_S_NVDLA_HW_VERSION_0::minor + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_MASK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_mask_0_out, nvdla_glb_s_intr_mask_0_out); + (32'h8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_SET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_set_0_out, nvdla_glb_s_intr_set_0_out); + (32'hc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_STATUS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_status_0_out, nvdla_glb_s_intr_status_0_out); + (32'h0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_GLB_S_NVDLA_HW_VERSION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_GLB_CSB_reg diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v.vcp new file mode 100644 index 0000000..b0a60ae --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v.vcp @@ -0,0 +1,321 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_CSB_reg.v +module NV_NVDLA_GLB_CSB_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cacc_done_mask0 + ,cacc_done_mask1 + ,cdma_dat_done_mask0 + ,cdma_dat_done_mask1 + ,cdma_wt_done_mask0 + ,cdma_wt_done_mask1 + ,cdp_done_mask0 + ,cdp_done_mask1 + ,pdp_done_mask0 + ,pdp_done_mask1 + ,sdp_done_mask0 + ,sdp_done_mask1 + ,sdp_done_set0_trigger + ,sdp_done_status0_trigger + ,cacc_done_set0 + ,cacc_done_set1 + ,cdma_dat_done_set0 + ,cdma_dat_done_set1 + ,cdma_wt_done_set0 + ,cdma_wt_done_set1 + ,cdp_done_set0 + ,cdp_done_set1 + ,pdp_done_set0 + ,pdp_done_set1 + ,sdp_done_set0 + ,sdp_done_set1 + ,cacc_done_status0 + ,cacc_done_status1 + ,cdma_dat_done_status0 + ,cdma_dat_done_status1 + ,cdma_wt_done_status0 + ,cdma_wt_done_status1 + ,cdp_done_status0 + ,cdp_done_status1 + ,pdp_done_status0 + ,pdp_done_status1 + ,sdp_done_status0 + ,sdp_done_status1 + ); +wire [7:0] major; +wire [15:0] minor; +wire [31:0] nvdla_glb_s_intr_mask_0_out; +wire [31:0] nvdla_glb_s_intr_set_0_out; +wire [31:0] nvdla_glb_s_intr_status_0_out; +wire [31:0] nvdla_glb_s_nvdla_hw_version_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output cacc_done_mask0; +output cacc_done_mask1; +output cdma_dat_done_mask0; +output cdma_dat_done_mask1; +output cdma_wt_done_mask0; +output cdma_wt_done_mask1; +output cdp_done_mask0; +output cdp_done_mask1; +output pdp_done_mask0; +output pdp_done_mask1; +output sdp_done_mask0; +output sdp_done_mask1; +output sdp_done_set0_trigger; +output sdp_done_status0_trigger; +// Read-only register inputs +input cacc_done_set0; +input cacc_done_set1; +input cdma_dat_done_set0; +input cdma_dat_done_set1; +input cdma_wt_done_set0; +input cdma_wt_done_set1; +input cdp_done_set0; +input cdp_done_set1; +input pdp_done_set0; +input pdp_done_set1; +input sdp_done_set0; +input sdp_done_set1; +input cacc_done_status0; +input cacc_done_status1; +input cdma_dat_done_status0; +input cdma_dat_done_status1; +input cdma_wt_done_status0; +input cdma_wt_done_status1; +input cdp_done_status0; +input cdp_done_status1; +input pdp_done_status0; +input pdp_done_status1; +input sdp_done_status0; +input sdp_done_status1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +wire bdma_done_mask0 = 1'b0 ; +wire bdma_done_mask1 = 1'b0 ; +reg cacc_done_mask0; +reg cacc_done_mask1; +reg cdma_dat_done_mask0; +reg cdma_dat_done_mask1; +reg cdma_wt_done_mask0; +reg cdma_wt_done_mask1; +reg cdp_done_mask0; +reg cdp_done_mask1; +reg pdp_done_mask0; +reg pdp_done_mask1; +reg [31:0] reg_rd_data; +wire rubik_done_mask0 = 1'b0 ; +wire rubik_done_mask1 = 1'b0; +reg sdp_done_mask0; +reg sdp_done_mask1; +wire rubik_done_set1 = 1'b0; +wire rubik_done_set0 = 1'b0; +wire rubik_done_status1 = 1'b0; +wire rubik_done_status0 = 1'b0; +wire bdma_done_set1 = 1'b0; +wire bdma_done_set0 = 1'b0; +wire bdma_done_status1 = 1'b0; +wire bdma_done_status0 = 1'b0; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_glb_s_intr_mask_0_wren = (reg_offset_wr == (32'h4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_glb_s_intr_set_0_wren = (reg_offset_wr == (32'h8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_glb_s_intr_status_0_wren = (reg_offset_wr == (32'hc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_glb_s_nvdla_hw_version_0_wren = (reg_offset_wr == (32'h0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign major = 8'h31; +assign minor = 16'h3030; +assign nvdla_glb_s_intr_mask_0_out[31:0] = { 10'b0, cacc_done_mask1, cacc_done_mask0, cdma_wt_done_mask1, cdma_wt_done_mask0, cdma_dat_done_mask1, cdma_dat_done_mask0, 6'b0, rubik_done_mask1, rubik_done_mask0, bdma_done_mask1, bdma_done_mask0, pdp_done_mask1, pdp_done_mask0, cdp_done_mask1, cdp_done_mask0, sdp_done_mask1, sdp_done_mask0 }; +assign nvdla_glb_s_intr_set_0_out[31:0] = { 10'b0, cacc_done_set1, cacc_done_set0, cdma_wt_done_set1, cdma_wt_done_set0, cdma_dat_done_set1, cdma_dat_done_set0, 6'b0, rubik_done_set1, rubik_done_set0, bdma_done_set1, bdma_done_set0, pdp_done_set1, pdp_done_set0, cdp_done_set1, cdp_done_set0, sdp_done_set1, sdp_done_set0 }; +assign nvdla_glb_s_intr_status_0_out[31:0] = { 10'b0, cacc_done_status1, cacc_done_status0, cdma_wt_done_status1, cdma_wt_done_status0, cdma_dat_done_status1, cdma_dat_done_status0, 6'b0, rubik_done_status1, rubik_done_status0, bdma_done_status1, bdma_done_status0, pdp_done_status1, pdp_done_status0, cdp_done_status1, cdp_done_status0, sdp_done_status1, sdp_done_status0 }; +assign nvdla_glb_s_nvdla_hw_version_0_out[31:0] = { 8'b0, minor, major }; +assign sdp_done_set0_trigger = nvdla_glb_s_intr_set_0_wren; //(W563) +assign sdp_done_status0_trigger = nvdla_glb_s_intr_status_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_glb_s_intr_mask_0_out + or nvdla_glb_s_intr_set_0_out + or nvdla_glb_s_intr_status_0_out + or nvdla_glb_s_nvdla_hw_version_0_out + ) begin + case (reg_offset_rd_int) + (32'h4 & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_intr_mask_0_out ; + end + (32'h8 & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_intr_set_0_out ; + end + (32'hc & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_intr_status_0_out ; + end + (32'h0 & 32'h00000fff): begin + reg_rd_data = nvdla_glb_s_nvdla_hw_version_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_mask0 <= 1'b0; + cacc_done_mask1 <= 1'b0; + cdma_dat_done_mask0 <= 1'b0; + cdma_dat_done_mask1 <= 1'b0; + cdma_wt_done_mask0 <= 1'b0; + cdma_wt_done_mask1 <= 1'b0; + cdp_done_mask0 <= 1'b0; + cdp_done_mask1 <= 1'b0; + pdp_done_mask0 <= 1'b0; + pdp_done_mask1 <= 1'b0; + sdp_done_mask0 <= 1'b0; + sdp_done_mask1 <= 1'b0; + end else begin +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: bdma_done_mask1 +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cacc_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cacc_done_mask0 <= reg_wr_data[20]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cacc_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cacc_done_mask1 <= reg_wr_data[21]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_dat_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_dat_done_mask0 <= reg_wr_data[16]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_dat_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_dat_done_mask1 <= reg_wr_data[17]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_wt_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_wt_done_mask0 <= reg_wr_data[18]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdma_wt_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdma_wt_done_mask1 <= reg_wr_data[19]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdp_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdp_done_mask0 <= reg_wr_data[2]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: cdp_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + cdp_done_mask1 <= reg_wr_data[3]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: pdp_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + pdp_done_mask0 <= reg_wr_data[4]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: pdp_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + pdp_done_mask1 <= reg_wr_data[5]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: sdp_done_mask0 + if (nvdla_glb_s_intr_mask_0_wren) begin + sdp_done_mask0 <= reg_wr_data[0]; + end +// Register: NVDLA_GLB_S_INTR_MASK_0 Field: sdp_done_mask1 + if (nvdla_glb_s_intr_mask_0_wren) begin + sdp_done_mask1 <= reg_wr_data[1]; + end +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::bdma_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::bdma_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cacc_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cacc_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_dat_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_dat_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_wt_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdma_wt_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdp_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::cdp_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::pdp_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::pdp_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::rubik_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::rubik_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::sdp_done_set0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_SET_0::sdp_done_set1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::bdma_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::bdma_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cacc_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cacc_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_dat_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_dat_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_wt_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdma_wt_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdp_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::cdp_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::pdp_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::pdp_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::rubik_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::rubik_done_status1 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::sdp_done_status0 (to be implemented outside) +// Not generating flops for field NVDLA_GLB_S_INTR_STATUS_0::sdp_done_status1 (to be implemented outside) +// Not generating flops for constant field NVDLA_GLB_S_NVDLA_HW_VERSION_0::major +// Not generating flops for constant field NVDLA_GLB_S_NVDLA_HW_VERSION_0::minor + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_MASK_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_mask_0_out, nvdla_glb_s_intr_mask_0_out); + (32'h8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_SET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_set_0_out, nvdla_glb_s_intr_set_0_out); + (32'hc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_GLB_S_INTR_STATUS_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_glb_s_intr_status_0_out, nvdla_glb_s_intr_status_0_out); + (32'h0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_GLB_S_NVDLA_HW_VERSION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_GLB_CSB_reg diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v new file mode 100644 index 0000000..b3cae2e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v @@ -0,0 +1,238 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_csb.v +module NV_NVDLA_GLB_csb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc_done_status0 //|< i + ,cacc_done_status1 //|< i + ,cdma_dat_done_status0 //|< i + ,cdma_dat_done_status1 //|< i + ,cdma_wt_done_status0 //|< i + ,cdma_wt_done_status1 //|< i + ,cdp_done_status0 //|< i + ,cdp_done_status1 //|< i + ,csb2glb_req_pd //|< i + ,csb2glb_req_pvld //|< i + ,pdp_done_status0 //|< i + ,pdp_done_status1 //|< i + ,sdp_done_status0 //|< i + ,sdp_done_status1 //|< i + ,cacc_done_mask0 //|> o + ,cacc_done_mask1 //|> o + ,cdma_dat_done_mask0 //|> o + ,cdma_dat_done_mask1 //|> o + ,cdma_wt_done_mask0 //|> o + ,cdma_wt_done_mask1 //|> o + ,cdp_done_mask0 //|> o + ,cdp_done_mask1 //|> o + ,csb2glb_req_prdy //|> o + ,glb2csb_resp_pd //|> o + ,glb2csb_resp_valid //|> o + ,pdp_done_mask0 //|> o + ,pdp_done_mask1 //|> o + ,req_wdat //|> o + ,sdp_done_mask0 //|> o + ,sdp_done_mask1 //|> o + ,sdp_done_set0_trigger //|> o + ,sdp_done_status0_trigger //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc_done_status0; +input cacc_done_status1; +input cdma_dat_done_status0; +input cdma_dat_done_status1; +input cdma_wt_done_status0; +input cdma_wt_done_status1; +input cdp_done_status0; +input cdp_done_status1; +input [62:0] csb2glb_req_pd; +input csb2glb_req_pvld; +input pdp_done_status0; +input pdp_done_status1; +input sdp_done_status0; +input sdp_done_status1; +output cacc_done_mask0; +output cacc_done_mask1; +output cdma_dat_done_mask0; +output cdma_dat_done_mask1; +output cdma_wt_done_mask0; +output cdma_wt_done_mask1; +output cdp_done_mask0; +output cdp_done_mask1; +output csb2glb_req_prdy; +output [33:0] glb2csb_resp_pd; +output glb2csb_resp_valid; +output pdp_done_mask0; +output pdp_done_mask1; +output [31:0] req_wdat; +output sdp_done_mask0; +output sdp_done_mask1; +output sdp_done_set0_trigger; +output sdp_done_status0_trigger; +reg [33:0] glb2csb_resp_pd; +reg glb2csb_resp_valid; +reg [62:0] req_pd; +reg req_vld; +wire cacc_done_set0; +wire cacc_done_set1; +wire cdma_dat_done_set0; +wire cdma_dat_done_set1; +wire cdma_wt_done_set0; +wire cdma_wt_done_set1; +wire cdp_done_set0; +wire cdp_done_set1; +wire pdp_done_set0; +wire pdp_done_set1; +wire [11:0] reg_offset; +wire [31:0] reg_rd_data; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level_NC; +wire req_nposted; +wire req_srcpriv_NC; +wire [3:0] req_wrbe_NC; +wire req_write; +wire [33:0] rsp_pd; +wire rsp_rd_error; +wire [32:0] rsp_rd_pd; +wire [31:0] rsp_rd_rdat; +wire rsp_rd_vld; +wire rsp_vld; +wire rsp_wr_error; +wire [32:0] rsp_wr_pd; +wire [31:0] rsp_wr_rdat; +wire rsp_wr_vld; +wire sdp_done_set0; +wire sdp_done_set1; +////////////////////////////////////////////////////////// +//// register +////////////////////////////////////////////////////////// +//tie 0 for wo type register read +assign cdp_done_set0 = 1'b0; +assign cdp_done_set1 = 1'b0; +assign pdp_done_set0 = 1'b0; +assign pdp_done_set1 = 1'b0; +assign sdp_done_set0 = 1'b0; +assign sdp_done_set1 = 1'b0; +assign cdma_dat_done_set0 = 1'b0; +assign cdma_dat_done_set1 = 1'b0; +assign cdma_wt_done_set0 = 1'b0; +assign cdma_wt_done_set1 = 1'b0; +assign cacc_done_set0 = 1'b0; +assign cacc_done_set1 = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_vld <= 1'b0; + end else begin + req_vld <= csb2glb_req_pvld; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2glb_req_pvld) == 1'b1) begin + req_pd <= csb2glb_req_pd; + end +end +assign csb2glb_req_prdy = 1'b1; +// ======== +// REQUEST +// ======== +// flow=pvld_prdy +assign req_level_NC = req_pd[62:61]; +assign req_nposted = req_pd[55:55]; +assign req_addr = req_pd[21:0]; +assign req_wrbe_NC = req_pd[60:57]; +assign req_srcpriv_NC = req_pd[56:56]; +assign req_write = req_pd[54:54]; +assign req_wdat = req_pd[53:22]; +// ======== +// RESPONSE +// ======== +// flow=valid +assign rsp_rd_pd[32:32] = rsp_rd_error; +assign rsp_rd_pd[31:0] = rsp_rd_rdat; +assign rsp_wr_pd[32:32] = rsp_wr_error; +assign rsp_wr_pd[31:0] = rsp_wr_rdat; +assign rsp_rd_vld = req_vld & ~req_write; +assign rsp_rd_rdat = {32{rsp_rd_vld}} & reg_rd_data; +assign rsp_rd_error = 1'b0; +assign rsp_wr_vld = req_vld & req_write & req_nposted; +assign rsp_wr_rdat = {32{1'b0}}; +assign rsp_wr_error = 1'b0; +// ======== +// REQUEST +// ======== +assign rsp_vld = rsp_rd_vld | rsp_wr_vld; +assign rsp_pd[33:33] = ({1{rsp_rd_vld}} & {1'h0}) + | ({1{rsp_wr_vld}} & {1'h1}); +assign rsp_pd[32:0] = ({33{rsp_rd_vld}} & rsp_rd_pd) + | ({33{rsp_wr_vld}} & rsp_wr_pd); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + glb2csb_resp_valid <= 1'b0; + end else begin + glb2csb_resp_valid <= rsp_vld; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_vld) == 1'b1) begin + glb2csb_resp_pd <= rsp_pd; + end +end +assign reg_offset = {req_addr[9:0],{2{1'b0}}}; +assign reg_wr_en = req_vld & req_write; +assign reg_wr_data = req_wdat; +NV_NVDLA_GLB_CSB_reg u_reg ( + .reg_rd_data (reg_rd_data[31:0]) //|> w + ,.reg_offset (reg_offset[11:0]) //|< w + ,.reg_wr_data (reg_wr_data[31:0]) //|< w + ,.reg_wr_en (reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc_done_mask0 (cacc_done_mask0) //|> o + ,.cacc_done_mask1 (cacc_done_mask1) //|> o + ,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|> o + ,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|> o + ,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|> o + ,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|> o + ,.cdp_done_mask0 (cdp_done_mask0) //|> o + ,.cdp_done_mask1 (cdp_done_mask1) //|> o + ,.pdp_done_mask0 (pdp_done_mask0) //|> o + ,.pdp_done_mask1 (pdp_done_mask1) //|> o + ,.sdp_done_mask0 (sdp_done_mask0) //|> o + ,.sdp_done_mask1 (sdp_done_mask1) //|> o + ,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|> o + ,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|> o + ,.cacc_done_set0 (cacc_done_set0) //|< w + ,.cacc_done_set1 (cacc_done_set1) //|< w + ,.cdma_dat_done_set0 (cdma_dat_done_set0) //|< w + ,.cdma_dat_done_set1 (cdma_dat_done_set1) //|< w + ,.cdma_wt_done_set0 (cdma_wt_done_set0) //|< w + ,.cdma_wt_done_set1 (cdma_wt_done_set1) //|< w + ,.cdp_done_set0 (cdp_done_set0) //|< w + ,.cdp_done_set1 (cdp_done_set1) //|< w + ,.pdp_done_set0 (pdp_done_set0) //|< w + ,.pdp_done_set1 (pdp_done_set1) //|< w + ,.sdp_done_set0 (sdp_done_set0) //|< w + ,.sdp_done_set1 (sdp_done_set1) //|< w + ,.cacc_done_status0 (cacc_done_status0) //|< i + ,.cacc_done_status1 (cacc_done_status1) //|< i + ,.cdma_dat_done_status0 (cdma_dat_done_status0) //|< i + ,.cdma_dat_done_status1 (cdma_dat_done_status1) //|< i + ,.cdma_wt_done_status0 (cdma_wt_done_status0) //|< i + ,.cdma_wt_done_status1 (cdma_wt_done_status1) //|< i + ,.cdp_done_status0 (cdp_done_status0) //|< i + ,.cdp_done_status1 (cdp_done_status1) //|< i + ,.pdp_done_status0 (pdp_done_status0) //|< i + ,.pdp_done_status1 (pdp_done_status1) //|< i + ,.sdp_done_status0 (sdp_done_status0) //|< i + ,.sdp_done_status1 (sdp_done_status1) //|< i +); +endmodule // NV_NVDLA_GLB_csb diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v.vcp b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v.vcp new file mode 100644 index 0000000..b3cae2e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v.vcp @@ -0,0 +1,238 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_csb.v +module NV_NVDLA_GLB_csb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc_done_status0 //|< i + ,cacc_done_status1 //|< i + ,cdma_dat_done_status0 //|< i + ,cdma_dat_done_status1 //|< i + ,cdma_wt_done_status0 //|< i + ,cdma_wt_done_status1 //|< i + ,cdp_done_status0 //|< i + ,cdp_done_status1 //|< i + ,csb2glb_req_pd //|< i + ,csb2glb_req_pvld //|< i + ,pdp_done_status0 //|< i + ,pdp_done_status1 //|< i + ,sdp_done_status0 //|< i + ,sdp_done_status1 //|< i + ,cacc_done_mask0 //|> o + ,cacc_done_mask1 //|> o + ,cdma_dat_done_mask0 //|> o + ,cdma_dat_done_mask1 //|> o + ,cdma_wt_done_mask0 //|> o + ,cdma_wt_done_mask1 //|> o + ,cdp_done_mask0 //|> o + ,cdp_done_mask1 //|> o + ,csb2glb_req_prdy //|> o + ,glb2csb_resp_pd //|> o + ,glb2csb_resp_valid //|> o + ,pdp_done_mask0 //|> o + ,pdp_done_mask1 //|> o + ,req_wdat //|> o + ,sdp_done_mask0 //|> o + ,sdp_done_mask1 //|> o + ,sdp_done_set0_trigger //|> o + ,sdp_done_status0_trigger //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc_done_status0; +input cacc_done_status1; +input cdma_dat_done_status0; +input cdma_dat_done_status1; +input cdma_wt_done_status0; +input cdma_wt_done_status1; +input cdp_done_status0; +input cdp_done_status1; +input [62:0] csb2glb_req_pd; +input csb2glb_req_pvld; +input pdp_done_status0; +input pdp_done_status1; +input sdp_done_status0; +input sdp_done_status1; +output cacc_done_mask0; +output cacc_done_mask1; +output cdma_dat_done_mask0; +output cdma_dat_done_mask1; +output cdma_wt_done_mask0; +output cdma_wt_done_mask1; +output cdp_done_mask0; +output cdp_done_mask1; +output csb2glb_req_prdy; +output [33:0] glb2csb_resp_pd; +output glb2csb_resp_valid; +output pdp_done_mask0; +output pdp_done_mask1; +output [31:0] req_wdat; +output sdp_done_mask0; +output sdp_done_mask1; +output sdp_done_set0_trigger; +output sdp_done_status0_trigger; +reg [33:0] glb2csb_resp_pd; +reg glb2csb_resp_valid; +reg [62:0] req_pd; +reg req_vld; +wire cacc_done_set0; +wire cacc_done_set1; +wire cdma_dat_done_set0; +wire cdma_dat_done_set1; +wire cdma_wt_done_set0; +wire cdma_wt_done_set1; +wire cdp_done_set0; +wire cdp_done_set1; +wire pdp_done_set0; +wire pdp_done_set1; +wire [11:0] reg_offset; +wire [31:0] reg_rd_data; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level_NC; +wire req_nposted; +wire req_srcpriv_NC; +wire [3:0] req_wrbe_NC; +wire req_write; +wire [33:0] rsp_pd; +wire rsp_rd_error; +wire [32:0] rsp_rd_pd; +wire [31:0] rsp_rd_rdat; +wire rsp_rd_vld; +wire rsp_vld; +wire rsp_wr_error; +wire [32:0] rsp_wr_pd; +wire [31:0] rsp_wr_rdat; +wire rsp_wr_vld; +wire sdp_done_set0; +wire sdp_done_set1; +////////////////////////////////////////////////////////// +//// register +////////////////////////////////////////////////////////// +//tie 0 for wo type register read +assign cdp_done_set0 = 1'b0; +assign cdp_done_set1 = 1'b0; +assign pdp_done_set0 = 1'b0; +assign pdp_done_set1 = 1'b0; +assign sdp_done_set0 = 1'b0; +assign sdp_done_set1 = 1'b0; +assign cdma_dat_done_set0 = 1'b0; +assign cdma_dat_done_set1 = 1'b0; +assign cdma_wt_done_set0 = 1'b0; +assign cdma_wt_done_set1 = 1'b0; +assign cacc_done_set0 = 1'b0; +assign cacc_done_set1 = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_vld <= 1'b0; + end else begin + req_vld <= csb2glb_req_pvld; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2glb_req_pvld) == 1'b1) begin + req_pd <= csb2glb_req_pd; + end +end +assign csb2glb_req_prdy = 1'b1; +// ======== +// REQUEST +// ======== +// flow=pvld_prdy +assign req_level_NC = req_pd[62:61]; +assign req_nposted = req_pd[55:55]; +assign req_addr = req_pd[21:0]; +assign req_wrbe_NC = req_pd[60:57]; +assign req_srcpriv_NC = req_pd[56:56]; +assign req_write = req_pd[54:54]; +assign req_wdat = req_pd[53:22]; +// ======== +// RESPONSE +// ======== +// flow=valid +assign rsp_rd_pd[32:32] = rsp_rd_error; +assign rsp_rd_pd[31:0] = rsp_rd_rdat; +assign rsp_wr_pd[32:32] = rsp_wr_error; +assign rsp_wr_pd[31:0] = rsp_wr_rdat; +assign rsp_rd_vld = req_vld & ~req_write; +assign rsp_rd_rdat = {32{rsp_rd_vld}} & reg_rd_data; +assign rsp_rd_error = 1'b0; +assign rsp_wr_vld = req_vld & req_write & req_nposted; +assign rsp_wr_rdat = {32{1'b0}}; +assign rsp_wr_error = 1'b0; +// ======== +// REQUEST +// ======== +assign rsp_vld = rsp_rd_vld | rsp_wr_vld; +assign rsp_pd[33:33] = ({1{rsp_rd_vld}} & {1'h0}) + | ({1{rsp_wr_vld}} & {1'h1}); +assign rsp_pd[32:0] = ({33{rsp_rd_vld}} & rsp_rd_pd) + | ({33{rsp_wr_vld}} & rsp_wr_pd); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + glb2csb_resp_valid <= 1'b0; + end else begin + glb2csb_resp_valid <= rsp_vld; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_vld) == 1'b1) begin + glb2csb_resp_pd <= rsp_pd; + end +end +assign reg_offset = {req_addr[9:0],{2{1'b0}}}; +assign reg_wr_en = req_vld & req_write; +assign reg_wr_data = req_wdat; +NV_NVDLA_GLB_CSB_reg u_reg ( + .reg_rd_data (reg_rd_data[31:0]) //|> w + ,.reg_offset (reg_offset[11:0]) //|< w + ,.reg_wr_data (reg_wr_data[31:0]) //|< w + ,.reg_wr_en (reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc_done_mask0 (cacc_done_mask0) //|> o + ,.cacc_done_mask1 (cacc_done_mask1) //|> o + ,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|> o + ,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|> o + ,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|> o + ,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|> o + ,.cdp_done_mask0 (cdp_done_mask0) //|> o + ,.cdp_done_mask1 (cdp_done_mask1) //|> o + ,.pdp_done_mask0 (pdp_done_mask0) //|> o + ,.pdp_done_mask1 (pdp_done_mask1) //|> o + ,.sdp_done_mask0 (sdp_done_mask0) //|> o + ,.sdp_done_mask1 (sdp_done_mask1) //|> o + ,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|> o + ,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|> o + ,.cacc_done_set0 (cacc_done_set0) //|< w + ,.cacc_done_set1 (cacc_done_set1) //|< w + ,.cdma_dat_done_set0 (cdma_dat_done_set0) //|< w + ,.cdma_dat_done_set1 (cdma_dat_done_set1) //|< w + ,.cdma_wt_done_set0 (cdma_wt_done_set0) //|< w + ,.cdma_wt_done_set1 (cdma_wt_done_set1) //|< w + ,.cdp_done_set0 (cdp_done_set0) //|< w + ,.cdp_done_set1 (cdp_done_set1) //|< w + ,.pdp_done_set0 (pdp_done_set0) //|< w + ,.pdp_done_set1 (pdp_done_set1) //|< w + ,.sdp_done_set0 (sdp_done_set0) //|< w + ,.sdp_done_set1 (sdp_done_set1) //|< w + ,.cacc_done_status0 (cacc_done_status0) //|< i + ,.cacc_done_status1 (cacc_done_status1) //|< i + ,.cdma_dat_done_status0 (cdma_dat_done_status0) //|< i + ,.cdma_dat_done_status1 (cdma_dat_done_status1) //|< i + ,.cdma_wt_done_status0 (cdma_wt_done_status0) //|< i + ,.cdma_wt_done_status1 (cdma_wt_done_status1) //|< i + ,.cdp_done_status0 (cdp_done_status0) //|< i + ,.cdp_done_status1 (cdp_done_status1) //|< i + ,.pdp_done_status0 (pdp_done_status0) //|< i + ,.pdp_done_status1 (pdp_done_status1) //|< i + ,.sdp_done_status0 (sdp_done_status0) //|< i + ,.sdp_done_status1 (sdp_done_status1) //|< i +); +endmodule // NV_NVDLA_GLB_csb diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v new file mode 100644 index 0000000..412e6ce --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v @@ -0,0 +1,148 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_fc.v +module NV_NVDLA_GLB_fc ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2gec_req_pd + ,csb2gec_req_pvld + ,direct_reset_ + ,nvdla_falcon_clk + ,nvdla_falcon_rstn + ,test_mode + ,csb2gec_req_prdy + ,gec2csb_resp_pd + ,gec2csb_resp_valid + ); +//call FC_PLUTIN here +input nvdla_falcon_clk; +input nvdla_core_clk; +input nvdla_core_rstn; +input nvdla_falcon_rstn; +input direct_reset_; +input test_mode; +input [62:0] csb2gec_req_pd; +input csb2gec_req_pvld; +output csb2gec_req_prdy; +output [33:0] gec2csb_resp_pd; +output gec2csb_resp_valid; +reg [33:0] gec2csb_resp_pd; +reg gec2csb_resp_valid; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_pvld; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire resp_en; +wire [33:0] resp_pd_w; +wire rresp_en; +wire rresp_error; +wire [33:0] rresp_pd_w; +wire [31:0] rresp_rdat; +wire wresp_en; +wire wresp_error; +wire [33:0] wresp_pd_w; +wire [31:0] wresp_rdat; +assign csb2gec_req_prdy = 1'b1; +assign req_pvld = csb2gec_req_pvld; +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , csb2gec_req_pd ) +assign req_addr[21:0] = csb2gec_req_pd[21:0]; +assign req_wdat[31:0] = csb2gec_req_pd[53:22]; +assign req_write = csb2gec_req_pd[54]; +assign req_nposted = csb2gec_req_pd[55]; +assign req_srcpriv = csb2gec_req_pd[56]; +assign req_wrbe[3:0] = csb2gec_req_pd[60:57]; +assign req_level[1:0] = csb2gec_req_pd[62:61]; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , rresp_ , rresp_pd_w ) +assign rresp_pd_w[31:0] = rresp_rdat[31:0]; +assign rresp_pd_w[32] = rresp_error ; +assign rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , wresp_ , wresp_pd_w ) +assign wresp_pd_w[31:0] = wresp_rdat[31:0]; +assign wresp_pd_w[32] = wresp_error ; +assign wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign rresp_rdat = 32'b0; +assign wresp_rdat = 32'b0; +assign rresp_error = 1'b0; +assign wresp_error = 1'b0; +assign wresp_en = req_pvld & req_write & req_nposted; +assign rresp_en = req_pvld & ~req_write; +assign resp_pd_w = wresp_en ? wresp_pd_w : rresp_pd_w; +assign resp_en = wresp_en | rresp_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gec2csb_resp_valid <= 1'b0; + end else begin + gec2csb_resp_valid <= resp_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gec2csb_resp_pd <= {34{1'b0}}; + end else begin + if ((resp_en) == 1'b1) begin + gec2csb_resp_pd <= resp_pd_w; +// VCS coverage off + end else if ((resp_en) == 1'b0) begin + end else begin + gec2csb_resp_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(resp_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_GLB_fc diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v.vcp b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v.vcp new file mode 100644 index 0000000..412e6ce --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v.vcp @@ -0,0 +1,148 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_fc.v +module NV_NVDLA_GLB_fc ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2gec_req_pd + ,csb2gec_req_pvld + ,direct_reset_ + ,nvdla_falcon_clk + ,nvdla_falcon_rstn + ,test_mode + ,csb2gec_req_prdy + ,gec2csb_resp_pd + ,gec2csb_resp_valid + ); +//call FC_PLUTIN here +input nvdla_falcon_clk; +input nvdla_core_clk; +input nvdla_core_rstn; +input nvdla_falcon_rstn; +input direct_reset_; +input test_mode; +input [62:0] csb2gec_req_pd; +input csb2gec_req_pvld; +output csb2gec_req_prdy; +output [33:0] gec2csb_resp_pd; +output gec2csb_resp_valid; +reg [33:0] gec2csb_resp_pd; +reg gec2csb_resp_valid; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_pvld; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire resp_en; +wire [33:0] resp_pd_w; +wire rresp_en; +wire rresp_error; +wire [33:0] rresp_pd_w; +wire [31:0] rresp_rdat; +wire wresp_en; +wire wresp_error; +wire [33:0] wresp_pd_w; +wire [31:0] wresp_rdat; +assign csb2gec_req_prdy = 1'b1; +assign req_pvld = csb2gec_req_pvld; +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , csb2gec_req_pd ) +assign req_addr[21:0] = csb2gec_req_pd[21:0]; +assign req_wdat[31:0] = csb2gec_req_pd[53:22]; +assign req_write = csb2gec_req_pd[54]; +assign req_nposted = csb2gec_req_pd[55]; +assign req_srcpriv = csb2gec_req_pd[56]; +assign req_wrbe[3:0] = csb2gec_req_pd[60:57]; +assign req_level[1:0] = csb2gec_req_pd[62:61]; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , rresp_ , rresp_pd_w ) +assign rresp_pd_w[31:0] = rresp_rdat[31:0]; +assign rresp_pd_w[32] = rresp_error ; +assign rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , wresp_ , wresp_pd_w ) +assign wresp_pd_w[31:0] = wresp_rdat[31:0]; +assign wresp_pd_w[32] = wresp_error ; +assign wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign rresp_rdat = 32'b0; +assign wresp_rdat = 32'b0; +assign rresp_error = 1'b0; +assign wresp_error = 1'b0; +assign wresp_en = req_pvld & req_write & req_nposted; +assign rresp_en = req_pvld & ~req_write; +assign resp_pd_w = wresp_en ? wresp_pd_w : rresp_pd_w; +assign resp_en = wresp_en | rresp_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gec2csb_resp_valid <= 1'b0; + end else begin + gec2csb_resp_valid <= resp_en; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gec2csb_resp_pd <= {34{1'b0}}; + end else begin + if ((resp_en) == 1'b1) begin + gec2csb_resp_pd <= resp_pd_w; +// VCS coverage off + end else if ((resp_en) == 1'b0) begin + end else begin + gec2csb_resp_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(resp_en))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_GLB_fc diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v new file mode 100644 index 0000000..aca0c79 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v @@ -0,0 +1,346 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_ic.v +module NV_NVDLA_GLB_ic ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2glb_done_intr_pd //|< i + ,cacc_done_mask0 //|< i + ,cacc_done_mask1 //|< i + ,cdma_dat2glb_done_intr_pd //|< i + ,cdma_dat_done_mask0 //|< i + ,cdma_dat_done_mask1 //|< i + ,cdma_wt2glb_done_intr_pd //|< i + ,cdma_wt_done_mask0 //|< i + ,cdma_wt_done_mask1 //|< i + ,cdp2glb_done_intr_pd //|< i + ,cdp_done_mask0 //|< i + ,cdp_done_mask1 //|< i + ,nvdla_falcon_clk //|< i + ,nvdla_falcon_rstn //|< i + ,pdp2glb_done_intr_pd //|< i + ,pdp_done_mask0 //|< i + ,pdp_done_mask1 //|< i + ,req_wdat //|< i + ,sdp2glb_done_intr_pd //|< i + ,sdp_done_mask0 //|< i + ,sdp_done_mask1 //|< i + ,sdp_done_set0_trigger //|< i + ,sdp_done_status0_trigger //|< i + ,cacc_done_status0 //|> o + ,cacc_done_status1 //|> o + ,cdma_dat_done_status0 //|> o + ,cdma_dat_done_status1 //|> o + ,cdma_wt_done_status0 //|> o + ,cdma_wt_done_status1 //|> o + ,cdp_done_status0 //|> o + ,cdp_done_status1 //|> o + ,core_intr //|> o + ,pdp_done_status0 //|> o + ,pdp_done_status1 //|> o + ,sdp_done_status0 //|> o + ,sdp_done_status1 //|> o + ); +//&Catenate "NV_NVDLA_GLB_ic_ports.v"; +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] cacc2glb_done_intr_pd; +input cacc_done_mask0; +input cacc_done_mask1; +input [1:0] cdma_dat2glb_done_intr_pd; +input cdma_dat_done_mask0; +input cdma_dat_done_mask1; +input [1:0] cdma_wt2glb_done_intr_pd; +input cdma_wt_done_mask0; +input cdma_wt_done_mask1; +input [1:0] cdp2glb_done_intr_pd; +input cdp_done_mask0; +input cdp_done_mask1; +input nvdla_falcon_clk; +input nvdla_falcon_rstn; +input [1:0] pdp2glb_done_intr_pd; +input pdp_done_mask0; +input pdp_done_mask1; +input [21:0] req_wdat; +input [1:0] sdp2glb_done_intr_pd; +input sdp_done_mask0; +input sdp_done_mask1; +input sdp_done_set0_trigger; +input sdp_done_status0_trigger; +output cacc_done_status0; +output cacc_done_status1; +output cdma_dat_done_status0; +output cdma_dat_done_status1; +output cdma_wt_done_status0; +output cdma_wt_done_status1; +output cdp_done_status0; +output cdp_done_status1; +output core_intr; +output pdp_done_status0; +output pdp_done_status1; +output sdp_done_status0; +output sdp_done_status1; +reg cacc_done_status0; +reg cacc_done_status1; +wire cacc_done_status0_w; +wire cacc_done_status1_w; +reg cdma_dat_done_status0; +reg cdma_dat_done_status1; +wire cdma_dat_done_status0_w; +wire cdma_dat_done_status1_w; +reg cdma_wt_done_status0; +reg cdma_wt_done_status1; +wire cdma_wt_done_status0_w; +wire cdma_wt_done_status1_w; +reg cdp_done_status0; +reg cdp_done_status1; +wire cdp_done_status0_w; +wire cdp_done_status1_w; +reg pdp_done_status0; +reg pdp_done_status1; +wire pdp_done_status0_w; +wire pdp_done_status1_w; +reg sdp_done_status0; +reg sdp_done_status1; +wire sdp_done_status0_w; +wire sdp_done_status1_w; +reg core_intr_d; +reg [15:0] done_source; +wire core_intr_w; +wire [15:0] done_set; +wire [15:0] done_wr_clr; +assign done_wr_clr = sdp_done_status0_trigger ? {req_wdat[21:16], req_wdat[9:0]} : 14'b0; +assign done_set = sdp_done_set0_trigger ? {req_wdat[21:16], req_wdat[9:0]} : 14'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + done_source <= {16{1'b0}}; + end else begin + done_source <= {cacc2glb_done_intr_pd[1:0], + cdma_wt2glb_done_intr_pd[1:0], + cdma_dat2glb_done_intr_pd[1:0], + 2'b0, + 2'b0, + pdp2glb_done_intr_pd[1:0], + cdp2glb_done_intr_pd[1:0], + sdp2glb_done_intr_pd[1:0]}; + end +end +//////// interrrupt status 0 for sdp //////// +assign sdp_done_status0_w = (done_set[0] | done_source[0]) ? 1'b1 : + (done_wr_clr[0]) ? 1'b0 : + sdp_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_done_status0 <= 1'b0; + end else begin + sdp_done_status0 <= sdp_done_status0_w; + end +end +//////// interrrupt status 1 for sdp //////// +assign sdp_done_status1_w = (done_set[1] | done_source[1]) ? 1'b1 : + (done_wr_clr[1]) ? 1'b0 : + sdp_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_done_status1 <= 1'b0; + end else begin + sdp_done_status1 <= sdp_done_status1_w; + end +end +//////// interrrupt status 0 for cdp //////// +assign cdp_done_status0_w = (done_set[2] | done_source[2]) ? 1'b1 : + (done_wr_clr[2]) ? 1'b0 : + cdp_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_done_status0 <= 1'b0; + end else begin + cdp_done_status0 <= cdp_done_status0_w; + end +end +//////// interrrupt status 1 for cdp //////// +assign cdp_done_status1_w = (done_set[3] | done_source[3]) ? 1'b1 : + (done_wr_clr[3]) ? 1'b0 : + cdp_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_done_status1 <= 1'b0; + end else begin + cdp_done_status1 <= cdp_done_status1_w; + end +end +//////// interrrupt status 0 for pdp //////// +assign pdp_done_status0_w = (done_set[4] | done_source[4]) ? 1'b1 : + (done_wr_clr[4]) ? 1'b0 : + pdp_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_done_status0 <= 1'b0; + end else begin + pdp_done_status0 <= pdp_done_status0_w; + end +end +//////// interrrupt status 1 for pdp //////// +assign pdp_done_status1_w = (done_set[5] | done_source[5]) ? 1'b1 : + (done_wr_clr[5]) ? 1'b0 : + pdp_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_done_status1 <= 1'b0; + end else begin + pdp_done_status1 <= pdp_done_status1_w; + end +end +//////// interrrupt status 0 for cdma_dat //////// +assign cdma_dat_done_status0_w = (done_set[10] | done_source[10]) ? 1'b1 : + (done_wr_clr[10]) ? 1'b0 : + cdma_dat_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_dat_done_status0 <= 1'b0; + end else begin + cdma_dat_done_status0 <= cdma_dat_done_status0_w; + end +end +//////// interrrupt status 1 for cdma_dat //////// +assign cdma_dat_done_status1_w = (done_set[11] | done_source[11]) ? 1'b1 : + (done_wr_clr[11]) ? 1'b0 : + cdma_dat_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_dat_done_status1 <= 1'b0; + end else begin + cdma_dat_done_status1 <= cdma_dat_done_status1_w; + end +end +//////// interrrupt status 0 for cdma_wt //////// +assign cdma_wt_done_status0_w = (done_set[12] | done_source[12]) ? 1'b1 : + (done_wr_clr[12]) ? 1'b0 : + cdma_wt_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_wt_done_status0 <= 1'b0; + end else begin + cdma_wt_done_status0 <= cdma_wt_done_status0_w; + end +end +//////// interrrupt status 1 for cdma_wt //////// +assign cdma_wt_done_status1_w = (done_set[13] | done_source[13]) ? 1'b1 : + (done_wr_clr[13]) ? 1'b0 : + cdma_wt_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_wt_done_status1 <= 1'b0; + end else begin + cdma_wt_done_status1 <= cdma_wt_done_status1_w; + end +end +//////// interrrupt status 0 for cacc //////// +assign cacc_done_status0_w = (done_set[14] | done_source[14]) ? 1'b1 : + (done_wr_clr[14]) ? 1'b0 : + cacc_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_status0 <= 1'b0; + end else begin + cacc_done_status0 <= cacc_done_status0_w; + end +end +//////// interrrupt status 1 for cacc //////// +assign cacc_done_status1_w = (done_set[15] | done_source[15]) ? 1'b1 : + (done_wr_clr[15]) ? 1'b0 : + cacc_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_status1 <= 1'b0; + end else begin + cacc_done_status1 <= cacc_done_status1_w; + end +end +assign core_intr_w = (~sdp_done_mask0 & sdp_done_status0) | + (~sdp_done_mask1 & sdp_done_status1) | + (~cdp_done_mask0 & cdp_done_status0) | + (~cdp_done_mask1 & cdp_done_status1) | + (~pdp_done_mask0 & pdp_done_status0) | + (~pdp_done_mask1 & pdp_done_status1) | + (~cdma_dat_done_mask0 & cdma_dat_done_status0) | + (~cdma_dat_done_mask1 & cdma_dat_done_status1) | + (~cdma_wt_done_mask0 & cdma_wt_done_status0) | + (~cdma_wt_done_mask1 & cdma_wt_done_status1) | + (~cacc_done_mask0 & cacc_done_status0) | + (~cacc_done_mask1 & cacc_done_status1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + core_intr_d <= 1'b0; + end else begin + core_intr_d <= core_intr_w; + end +end +NV_NVDLA_sync3d_c u_sync_core_intr ( + .clk (nvdla_falcon_clk) //|< i + ,.rst (nvdla_falcon_rstn) //|< i + ,.sync_i (core_intr_d) //|< r + ,.sync_o (core_intr) //|> o + ); +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Set and clear interrupt concurrently!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (sdp_done_status0_trigger & sdp_done_set0_trigger)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CDMA data sends two interrupts at same cycle!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (cdma_dat2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CDMA weight sends two interrupts at same cycle!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (cdma_wt2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CACC sends two interrupts at same cycle!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (cacc2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! SDP sends two interrupts at same cycle!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (sdp2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! PDP sends two interrupts at same cycle!") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (pdp2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CDP sends two interrupts at same cycle!") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (cdp2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_GLB_ic diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v.vcp b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v.vcp new file mode 100644 index 0000000..aca0c79 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v.vcp @@ -0,0 +1,346 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_GLB_ic.v +module NV_NVDLA_GLB_ic ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2glb_done_intr_pd //|< i + ,cacc_done_mask0 //|< i + ,cacc_done_mask1 //|< i + ,cdma_dat2glb_done_intr_pd //|< i + ,cdma_dat_done_mask0 //|< i + ,cdma_dat_done_mask1 //|< i + ,cdma_wt2glb_done_intr_pd //|< i + ,cdma_wt_done_mask0 //|< i + ,cdma_wt_done_mask1 //|< i + ,cdp2glb_done_intr_pd //|< i + ,cdp_done_mask0 //|< i + ,cdp_done_mask1 //|< i + ,nvdla_falcon_clk //|< i + ,nvdla_falcon_rstn //|< i + ,pdp2glb_done_intr_pd //|< i + ,pdp_done_mask0 //|< i + ,pdp_done_mask1 //|< i + ,req_wdat //|< i + ,sdp2glb_done_intr_pd //|< i + ,sdp_done_mask0 //|< i + ,sdp_done_mask1 //|< i + ,sdp_done_set0_trigger //|< i + ,sdp_done_status0_trigger //|< i + ,cacc_done_status0 //|> o + ,cacc_done_status1 //|> o + ,cdma_dat_done_status0 //|> o + ,cdma_dat_done_status1 //|> o + ,cdma_wt_done_status0 //|> o + ,cdma_wt_done_status1 //|> o + ,cdp_done_status0 //|> o + ,cdp_done_status1 //|> o + ,core_intr //|> o + ,pdp_done_status0 //|> o + ,pdp_done_status1 //|> o + ,sdp_done_status0 //|> o + ,sdp_done_status1 //|> o + ); +//&Catenate "NV_NVDLA_GLB_ic_ports.v"; +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] cacc2glb_done_intr_pd; +input cacc_done_mask0; +input cacc_done_mask1; +input [1:0] cdma_dat2glb_done_intr_pd; +input cdma_dat_done_mask0; +input cdma_dat_done_mask1; +input [1:0] cdma_wt2glb_done_intr_pd; +input cdma_wt_done_mask0; +input cdma_wt_done_mask1; +input [1:0] cdp2glb_done_intr_pd; +input cdp_done_mask0; +input cdp_done_mask1; +input nvdla_falcon_clk; +input nvdla_falcon_rstn; +input [1:0] pdp2glb_done_intr_pd; +input pdp_done_mask0; +input pdp_done_mask1; +input [21:0] req_wdat; +input [1:0] sdp2glb_done_intr_pd; +input sdp_done_mask0; +input sdp_done_mask1; +input sdp_done_set0_trigger; +input sdp_done_status0_trigger; +output cacc_done_status0; +output cacc_done_status1; +output cdma_dat_done_status0; +output cdma_dat_done_status1; +output cdma_wt_done_status0; +output cdma_wt_done_status1; +output cdp_done_status0; +output cdp_done_status1; +output core_intr; +output pdp_done_status0; +output pdp_done_status1; +output sdp_done_status0; +output sdp_done_status1; +reg cacc_done_status0; +reg cacc_done_status1; +wire cacc_done_status0_w; +wire cacc_done_status1_w; +reg cdma_dat_done_status0; +reg cdma_dat_done_status1; +wire cdma_dat_done_status0_w; +wire cdma_dat_done_status1_w; +reg cdma_wt_done_status0; +reg cdma_wt_done_status1; +wire cdma_wt_done_status0_w; +wire cdma_wt_done_status1_w; +reg cdp_done_status0; +reg cdp_done_status1; +wire cdp_done_status0_w; +wire cdp_done_status1_w; +reg pdp_done_status0; +reg pdp_done_status1; +wire pdp_done_status0_w; +wire pdp_done_status1_w; +reg sdp_done_status0; +reg sdp_done_status1; +wire sdp_done_status0_w; +wire sdp_done_status1_w; +reg core_intr_d; +reg [15:0] done_source; +wire core_intr_w; +wire [15:0] done_set; +wire [15:0] done_wr_clr; +assign done_wr_clr = sdp_done_status0_trigger ? {req_wdat[21:16], req_wdat[9:0]} : 14'b0; +assign done_set = sdp_done_set0_trigger ? {req_wdat[21:16], req_wdat[9:0]} : 14'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + done_source <= {16{1'b0}}; + end else begin + done_source <= {cacc2glb_done_intr_pd[1:0], + cdma_wt2glb_done_intr_pd[1:0], + cdma_dat2glb_done_intr_pd[1:0], + 2'b0, + 2'b0, + pdp2glb_done_intr_pd[1:0], + cdp2glb_done_intr_pd[1:0], + sdp2glb_done_intr_pd[1:0]}; + end +end +//////// interrrupt status 0 for sdp //////// +assign sdp_done_status0_w = (done_set[0] | done_source[0]) ? 1'b1 : + (done_wr_clr[0]) ? 1'b0 : + sdp_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_done_status0 <= 1'b0; + end else begin + sdp_done_status0 <= sdp_done_status0_w; + end +end +//////// interrrupt status 1 for sdp //////// +assign sdp_done_status1_w = (done_set[1] | done_source[1]) ? 1'b1 : + (done_wr_clr[1]) ? 1'b0 : + sdp_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_done_status1 <= 1'b0; + end else begin + sdp_done_status1 <= sdp_done_status1_w; + end +end +//////// interrrupt status 0 for cdp //////// +assign cdp_done_status0_w = (done_set[2] | done_source[2]) ? 1'b1 : + (done_wr_clr[2]) ? 1'b0 : + cdp_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_done_status0 <= 1'b0; + end else begin + cdp_done_status0 <= cdp_done_status0_w; + end +end +//////// interrrupt status 1 for cdp //////// +assign cdp_done_status1_w = (done_set[3] | done_source[3]) ? 1'b1 : + (done_wr_clr[3]) ? 1'b0 : + cdp_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdp_done_status1 <= 1'b0; + end else begin + cdp_done_status1 <= cdp_done_status1_w; + end +end +//////// interrrupt status 0 for pdp //////// +assign pdp_done_status0_w = (done_set[4] | done_source[4]) ? 1'b1 : + (done_wr_clr[4]) ? 1'b0 : + pdp_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_done_status0 <= 1'b0; + end else begin + pdp_done_status0 <= pdp_done_status0_w; + end +end +//////// interrrupt status 1 for pdp //////// +assign pdp_done_status1_w = (done_set[5] | done_source[5]) ? 1'b1 : + (done_wr_clr[5]) ? 1'b0 : + pdp_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_done_status1 <= 1'b0; + end else begin + pdp_done_status1 <= pdp_done_status1_w; + end +end +//////// interrrupt status 0 for cdma_dat //////// +assign cdma_dat_done_status0_w = (done_set[10] | done_source[10]) ? 1'b1 : + (done_wr_clr[10]) ? 1'b0 : + cdma_dat_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_dat_done_status0 <= 1'b0; + end else begin + cdma_dat_done_status0 <= cdma_dat_done_status0_w; + end +end +//////// interrrupt status 1 for cdma_dat //////// +assign cdma_dat_done_status1_w = (done_set[11] | done_source[11]) ? 1'b1 : + (done_wr_clr[11]) ? 1'b0 : + cdma_dat_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_dat_done_status1 <= 1'b0; + end else begin + cdma_dat_done_status1 <= cdma_dat_done_status1_w; + end +end +//////// interrrupt status 0 for cdma_wt //////// +assign cdma_wt_done_status0_w = (done_set[12] | done_source[12]) ? 1'b1 : + (done_wr_clr[12]) ? 1'b0 : + cdma_wt_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_wt_done_status0 <= 1'b0; + end else begin + cdma_wt_done_status0 <= cdma_wt_done_status0_w; + end +end +//////// interrrupt status 1 for cdma_wt //////// +assign cdma_wt_done_status1_w = (done_set[13] | done_source[13]) ? 1'b1 : + (done_wr_clr[13]) ? 1'b0 : + cdma_wt_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cdma_wt_done_status1 <= 1'b0; + end else begin + cdma_wt_done_status1 <= cdma_wt_done_status1_w; + end +end +//////// interrrupt status 0 for cacc //////// +assign cacc_done_status0_w = (done_set[14] | done_source[14]) ? 1'b1 : + (done_wr_clr[14]) ? 1'b0 : + cacc_done_status0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_status0 <= 1'b0; + end else begin + cacc_done_status0 <= cacc_done_status0_w; + end +end +//////// interrrupt status 1 for cacc //////// +assign cacc_done_status1_w = (done_set[15] | done_source[15]) ? 1'b1 : + (done_wr_clr[15]) ? 1'b0 : + cacc_done_status1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc_done_status1 <= 1'b0; + end else begin + cacc_done_status1 <= cacc_done_status1_w; + end +end +assign core_intr_w = (~sdp_done_mask0 & sdp_done_status0) | + (~sdp_done_mask1 & sdp_done_status1) | + (~cdp_done_mask0 & cdp_done_status0) | + (~cdp_done_mask1 & cdp_done_status1) | + (~pdp_done_mask0 & pdp_done_status0) | + (~pdp_done_mask1 & pdp_done_status1) | + (~cdma_dat_done_mask0 & cdma_dat_done_status0) | + (~cdma_dat_done_mask1 & cdma_dat_done_status1) | + (~cdma_wt_done_mask0 & cdma_wt_done_status0) | + (~cdma_wt_done_mask1 & cdma_wt_done_status1) | + (~cacc_done_mask0 & cacc_done_status0) | + (~cacc_done_mask1 & cacc_done_status1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + core_intr_d <= 1'b0; + end else begin + core_intr_d <= core_intr_w; + end +end +NV_NVDLA_sync3d_c u_sync_core_intr ( + .clk (nvdla_falcon_clk) //|< i + ,.rst (nvdla_falcon_rstn) //|< i + ,.sync_i (core_intr_d) //|< r + ,.sync_o (core_intr) //|> o + ); +//////////////////////////////////////////////////////////////////////// +// Assertion // +//////////////////////////////////////////////////////////////////////// +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Set and clear interrupt concurrently!") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (sdp_done_status0_trigger & sdp_done_set0_trigger)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CDMA data sends two interrupts at same cycle!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (cdma_dat2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CDMA weight sends two interrupts at same cycle!") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (cdma_wt2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CACC sends two interrupts at same cycle!") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, (cacc2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! SDP sends two interrupts at same cycle!") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (sdp2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! PDP sends two interrupts at same cycle!") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (pdp2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"Error! CDP sends two interrupts at same cycle!") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (cdp2glb_done_intr_pd == 3'h3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_GLB_ic diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_glb.v b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_glb.v new file mode 100644 index 0000000..36f9091 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_glb.v @@ -0,0 +1,162 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_glb.v +module NV_NVDLA_glb ( + cacc2glb_done_intr_pd //|< i + ,cdma_dat2glb_done_intr_pd //|< i + ,cdma_wt2glb_done_intr_pd //|< i + ,cdp2glb_done_intr_pd //|< i + ,csb2glb_req_pd //|< i + ,csb2glb_req_pvld //|< i + ,direct_reset_ //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,nvdla_falcon_clk //|< i + ,nvdla_falcon_rstn //|< i + ,pdp2glb_done_intr_pd //|< i + ,sdp2glb_done_intr_pd //|< i + ,test_mode //|< i + ,core_intr //|> o + ,csb2glb_req_prdy //|> o + ,glb2csb_resp_pd //|> o + ,glb2csb_resp_valid //|> o + ); +// +// NV_NVDLA_glb_io.v +// +input csb2glb_req_pvld; /* data valid */ +output csb2glb_req_prdy; /* data return handshake */ +input [62:0] csb2glb_req_pd; +output glb2csb_resp_valid; /* data valid */ +output [33:0] glb2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output core_intr; +input [1:0] sdp2glb_done_intr_pd; +input [1:0] cdp2glb_done_intr_pd; +input [1:0] pdp2glb_done_intr_pd; +input [1:0] cdma_wt2glb_done_intr_pd; +input [1:0] cdma_dat2glb_done_intr_pd; +input [1:0] cacc2glb_done_intr_pd; +input nvdla_core_clk; +input nvdla_falcon_clk; +input nvdla_core_rstn; +input nvdla_falcon_rstn; +input test_mode; +input direct_reset_; +wire cacc_done_mask0; +wire cacc_done_mask1; +wire cacc_done_status0; +wire cacc_done_status1; +wire cdma_dat_done_mask0; +wire cdma_dat_done_mask1; +wire cdma_dat_done_status0; +wire cdma_dat_done_status1; +wire cdma_wt_done_mask0; +wire cdma_wt_done_mask1; +wire cdma_wt_done_status0; +wire cdma_wt_done_status1; +wire cdp_done_mask0; +wire cdp_done_mask1; +wire cdp_done_status0; +wire cdp_done_status1; +wire pdp_done_mask0; +wire pdp_done_mask1; +wire pdp_done_status0; +wire pdp_done_status1; +wire sdp_done_mask0; +wire sdp_done_mask1; +wire sdp_done_set0_trigger; +wire sdp_done_status0; +wire sdp_done_status0_trigger; +wire sdp_done_status1; +wire [31:0] req_wdat; +//////////////////////////////////////////////////////// +// csb interface +//////////////////////////////////////////////////////// +NV_NVDLA_GLB_csb u_csb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc_done_status0 (cacc_done_status0) //|< w + ,.cacc_done_status1 (cacc_done_status1) //|< w + ,.cdma_dat_done_status0 (cdma_dat_done_status0) //|< w + ,.cdma_dat_done_status1 (cdma_dat_done_status1) //|< w + ,.cdma_wt_done_status0 (cdma_wt_done_status0) //|< w + ,.cdma_wt_done_status1 (cdma_wt_done_status1) //|< w + ,.cdp_done_status0 (cdp_done_status0) //|< w + ,.cdp_done_status1 (cdp_done_status1) //|< w + ,.csb2glb_req_pd (csb2glb_req_pd[62:0]) //|< i + ,.csb2glb_req_pvld (csb2glb_req_pvld) //|< i + ,.pdp_done_status0 (pdp_done_status0) //|< w + ,.pdp_done_status1 (pdp_done_status1) //|< w + ,.sdp_done_status0 (sdp_done_status0) //|< w + ,.sdp_done_status1 (sdp_done_status1) //|< w + ,.cacc_done_mask0 (cacc_done_mask0) //|> w + ,.cacc_done_mask1 (cacc_done_mask1) //|> w + ,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|> w + ,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|> w + ,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|> w + ,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|> w + ,.cdp_done_mask0 (cdp_done_mask0) //|> w + ,.cdp_done_mask1 (cdp_done_mask1) //|> w + ,.csb2glb_req_prdy (csb2glb_req_prdy) //|> o + ,.glb2csb_resp_pd (glb2csb_resp_pd[33:0]) //|> o + ,.glb2csb_resp_valid (glb2csb_resp_valid) //|> o + ,.pdp_done_mask0 (pdp_done_mask0) //|> w + ,.pdp_done_mask1 (pdp_done_mask1) //|> w + ,.sdp_done_mask0 (sdp_done_mask0) //|> w + ,.sdp_done_mask1 (sdp_done_mask1) //|> w + ,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|> w + ,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|> w + ,.req_wdat (req_wdat[31:0]) //|> w + ); +//////////////////////////////////////////////////////// +// interrupt controller +//////////////////////////////////////////////////////// +NV_NVDLA_GLB_ic u_ic ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) //|< i + ,.cacc_done_mask0 (cacc_done_mask0) //|< w + ,.cacc_done_mask1 (cacc_done_mask1) //|< w + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) //|< i + ,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|< w + ,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|< w + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) //|< i + ,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|< w + ,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|< w + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|< i + ,.cdp_done_mask0 (cdp_done_mask0) //|< w + ,.cdp_done_mask1 (cdp_done_mask1) //|< w + ,.nvdla_falcon_clk (nvdla_falcon_clk) //|< i + ,.nvdla_falcon_rstn (nvdla_falcon_rstn) //|< i + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|< i + ,.pdp_done_mask0 (pdp_done_mask0) //|< w + ,.pdp_done_mask1 (pdp_done_mask1) //|< w + ,.req_wdat (req_wdat[21:0]) //|< w + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) //|< i + ,.sdp_done_mask0 (sdp_done_mask0) //|< w + ,.sdp_done_mask1 (sdp_done_mask1) //|< w + ,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|< w + ,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|< w + ,.cacc_done_status0 (cacc_done_status0) //|> w + ,.cacc_done_status1 (cacc_done_status1) //|> w + ,.cdma_dat_done_status0 (cdma_dat_done_status0) //|> w + ,.cdma_dat_done_status1 (cdma_dat_done_status1) //|> w + ,.cdma_wt_done_status0 (cdma_wt_done_status0) //|> w + ,.cdma_wt_done_status1 (cdma_wt_done_status1) //|> w + ,.cdp_done_status0 (cdp_done_status0) //|> w + ,.cdp_done_status1 (cdp_done_status1) //|> w + ,.pdp_done_status0 (pdp_done_status0) //|> w + ,.pdp_done_status1 (pdp_done_status1) //|> w + ,.sdp_done_status0 (sdp_done_status0) //|> w + ,.sdp_done_status1 (sdp_done_status1) //|> w + ,.core_intr (core_intr) //|> o + ); +////////////////////////////////////////////////////////// +//// Dangles/Contenders report +////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_glb diff --git a/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_glb.v.vcp b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_glb.v.vcp new file mode 100644 index 0000000..36f9091 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/glb/NV_NVDLA_glb.v.vcp @@ -0,0 +1,162 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_glb.v +module NV_NVDLA_glb ( + cacc2glb_done_intr_pd //|< i + ,cdma_dat2glb_done_intr_pd //|< i + ,cdma_wt2glb_done_intr_pd //|< i + ,cdp2glb_done_intr_pd //|< i + ,csb2glb_req_pd //|< i + ,csb2glb_req_pvld //|< i + ,direct_reset_ //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,nvdla_falcon_clk //|< i + ,nvdla_falcon_rstn //|< i + ,pdp2glb_done_intr_pd //|< i + ,sdp2glb_done_intr_pd //|< i + ,test_mode //|< i + ,core_intr //|> o + ,csb2glb_req_prdy //|> o + ,glb2csb_resp_pd //|> o + ,glb2csb_resp_valid //|> o + ); +// +// NV_NVDLA_glb_io.v +// +input csb2glb_req_pvld; /* data valid */ +output csb2glb_req_prdy; /* data return handshake */ +input [62:0] csb2glb_req_pd; +output glb2csb_resp_valid; /* data valid */ +output [33:0] glb2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output core_intr; +input [1:0] sdp2glb_done_intr_pd; +input [1:0] cdp2glb_done_intr_pd; +input [1:0] pdp2glb_done_intr_pd; +input [1:0] cdma_wt2glb_done_intr_pd; +input [1:0] cdma_dat2glb_done_intr_pd; +input [1:0] cacc2glb_done_intr_pd; +input nvdla_core_clk; +input nvdla_falcon_clk; +input nvdla_core_rstn; +input nvdla_falcon_rstn; +input test_mode; +input direct_reset_; +wire cacc_done_mask0; +wire cacc_done_mask1; +wire cacc_done_status0; +wire cacc_done_status1; +wire cdma_dat_done_mask0; +wire cdma_dat_done_mask1; +wire cdma_dat_done_status0; +wire cdma_dat_done_status1; +wire cdma_wt_done_mask0; +wire cdma_wt_done_mask1; +wire cdma_wt_done_status0; +wire cdma_wt_done_status1; +wire cdp_done_mask0; +wire cdp_done_mask1; +wire cdp_done_status0; +wire cdp_done_status1; +wire pdp_done_mask0; +wire pdp_done_mask1; +wire pdp_done_status0; +wire pdp_done_status1; +wire sdp_done_mask0; +wire sdp_done_mask1; +wire sdp_done_set0_trigger; +wire sdp_done_status0; +wire sdp_done_status0_trigger; +wire sdp_done_status1; +wire [31:0] req_wdat; +//////////////////////////////////////////////////////// +// csb interface +//////////////////////////////////////////////////////// +NV_NVDLA_GLB_csb u_csb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc_done_status0 (cacc_done_status0) //|< w + ,.cacc_done_status1 (cacc_done_status1) //|< w + ,.cdma_dat_done_status0 (cdma_dat_done_status0) //|< w + ,.cdma_dat_done_status1 (cdma_dat_done_status1) //|< w + ,.cdma_wt_done_status0 (cdma_wt_done_status0) //|< w + ,.cdma_wt_done_status1 (cdma_wt_done_status1) //|< w + ,.cdp_done_status0 (cdp_done_status0) //|< w + ,.cdp_done_status1 (cdp_done_status1) //|< w + ,.csb2glb_req_pd (csb2glb_req_pd[62:0]) //|< i + ,.csb2glb_req_pvld (csb2glb_req_pvld) //|< i + ,.pdp_done_status0 (pdp_done_status0) //|< w + ,.pdp_done_status1 (pdp_done_status1) //|< w + ,.sdp_done_status0 (sdp_done_status0) //|< w + ,.sdp_done_status1 (sdp_done_status1) //|< w + ,.cacc_done_mask0 (cacc_done_mask0) //|> w + ,.cacc_done_mask1 (cacc_done_mask1) //|> w + ,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|> w + ,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|> w + ,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|> w + ,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|> w + ,.cdp_done_mask0 (cdp_done_mask0) //|> w + ,.cdp_done_mask1 (cdp_done_mask1) //|> w + ,.csb2glb_req_prdy (csb2glb_req_prdy) //|> o + ,.glb2csb_resp_pd (glb2csb_resp_pd[33:0]) //|> o + ,.glb2csb_resp_valid (glb2csb_resp_valid) //|> o + ,.pdp_done_mask0 (pdp_done_mask0) //|> w + ,.pdp_done_mask1 (pdp_done_mask1) //|> w + ,.sdp_done_mask0 (sdp_done_mask0) //|> w + ,.sdp_done_mask1 (sdp_done_mask1) //|> w + ,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|> w + ,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|> w + ,.req_wdat (req_wdat[31:0]) //|> w + ); +//////////////////////////////////////////////////////// +// interrupt controller +//////////////////////////////////////////////////////// +NV_NVDLA_GLB_ic u_ic ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) //|< i + ,.cacc_done_mask0 (cacc_done_mask0) //|< w + ,.cacc_done_mask1 (cacc_done_mask1) //|< w + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) //|< i + ,.cdma_dat_done_mask0 (cdma_dat_done_mask0) //|< w + ,.cdma_dat_done_mask1 (cdma_dat_done_mask1) //|< w + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) //|< i + ,.cdma_wt_done_mask0 (cdma_wt_done_mask0) //|< w + ,.cdma_wt_done_mask1 (cdma_wt_done_mask1) //|< w + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|< i + ,.cdp_done_mask0 (cdp_done_mask0) //|< w + ,.cdp_done_mask1 (cdp_done_mask1) //|< w + ,.nvdla_falcon_clk (nvdla_falcon_clk) //|< i + ,.nvdla_falcon_rstn (nvdla_falcon_rstn) //|< i + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|< i + ,.pdp_done_mask0 (pdp_done_mask0) //|< w + ,.pdp_done_mask1 (pdp_done_mask1) //|< w + ,.req_wdat (req_wdat[21:0]) //|< w + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) //|< i + ,.sdp_done_mask0 (sdp_done_mask0) //|< w + ,.sdp_done_mask1 (sdp_done_mask1) //|< w + ,.sdp_done_set0_trigger (sdp_done_set0_trigger) //|< w + ,.sdp_done_status0_trigger (sdp_done_status0_trigger) //|< w + ,.cacc_done_status0 (cacc_done_status0) //|> w + ,.cacc_done_status1 (cacc_done_status1) //|> w + ,.cdma_dat_done_status0 (cdma_dat_done_status0) //|> w + ,.cdma_dat_done_status1 (cdma_dat_done_status1) //|> w + ,.cdma_wt_done_status0 (cdma_wt_done_status0) //|> w + ,.cdma_wt_done_status1 (cdma_wt_done_status1) //|> w + ,.cdp_done_status0 (cdp_done_status0) //|> w + ,.cdp_done_status1 (cdp_done_status1) //|> w + ,.pdp_done_status0 (pdp_done_status0) //|> w + ,.pdp_done_status1 (pdp_done_status1) //|> w + ,.sdp_done_status0 (sdp_done_status0) //|> w + ,.sdp_done_status1 (sdp_done_status1) //|> w + ,.core_intr (core_intr) //|> o + ); +////////////////////////////////////////////////////////// +//// Dangles/Contenders report +////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_glb diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v new file mode 100644 index 0000000..2db9e16 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v @@ -0,0 +1,122 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_DMAIF_rdreq.v +`include "simulate_x_tick.vh" +module NV_NVDLA_DMAIF_rdreq ( + nvdla_core_clk + ,nvdla_core_rstn + ,reg2dp_src_ram_type + ,mcif_rd_req_pd + ,mcif_rd_req_valid + ,mcif_rd_req_ready + ,dmaif_rd_req_pd + ,dmaif_rd_req_vld + ,dmaif_rd_req_rdy +); +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_src_ram_type; +output [32 +14:0] mcif_rd_req_pd; +output mcif_rd_req_valid; +input mcif_rd_req_ready; +input [32 +14:0] dmaif_rd_req_pd; +input dmaif_rd_req_vld; +output dmaif_rd_req_rdy; +////////////////////////////////////////////// +wire mc_dma_rd_req_vld; +wire mc_dma_rd_req_rdy; +wire mc_rd_req_rdyi; +wire dma_rd_req_ram_type; +wire rd_req_rdyi; +////////////////////////////////////////////// +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +assign mc_dma_rd_req_vld = dmaif_rd_req_vld & (dma_rd_req_ram_type == 1'b1); +assign mc_rd_req_rdyi = mc_dma_rd_req_rdy & (dma_rd_req_ram_type == 1'b1); +assign dmaif_rd_req_rdy= rd_req_rdyi; +//: my $dmabw = ( 32 + 15 ); +//: &eperl::pipe(" -wid $dmabw -is -do mcif_rd_req_pd -vo mcif_rd_req_valid -ri mcif_rd_req_ready -di dmaif_rd_req_pd -vi mc_dma_rd_req_vld -ro mc_dma_rd_req_rdy_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg mc_dma_rd_req_rdy_f; +reg skid_flop_mc_dma_rd_req_rdy_f; +reg skid_flop_mc_dma_rd_req_vld; +reg [47-1:0] skid_flop_dmaif_rd_req_pd; +reg pipe_skid_mc_dma_rd_req_vld; +reg [47-1:0] pipe_skid_dmaif_rd_req_pd; +// Wire +wire skid_mc_dma_rd_req_vld; +wire [47-1:0] skid_dmaif_rd_req_pd; +wire skid_mc_dma_rd_req_rdy_f; +wire pipe_skid_mc_dma_rd_req_rdy_f; +wire mcif_rd_req_valid; +wire [47-1:0] mcif_rd_req_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_dma_rd_req_rdy_f <= 1'b1; + skid_flop_mc_dma_rd_req_rdy_f <= 1'b1; + end else begin + mc_dma_rd_req_rdy_f <= skid_mc_dma_rd_req_rdy_f; + skid_flop_mc_dma_rd_req_rdy_f <= skid_mc_dma_rd_req_rdy_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_mc_dma_rd_req_vld <= 1'b0; + end else begin + if (skid_flop_mc_dma_rd_req_rdy_f) begin + skid_flop_mc_dma_rd_req_vld <= mc_dma_rd_req_vld; + end + end +end +assign skid_mc_dma_rd_req_vld = (skid_flop_mc_dma_rd_req_rdy_f) ? mc_dma_rd_req_vld : skid_flop_mc_dma_rd_req_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_mc_dma_rd_req_rdy_f & mc_dma_rd_req_vld) begin + skid_flop_dmaif_rd_req_pd[47-1:0] <= dmaif_rd_req_pd[47-1:0]; + end +end +assign skid_dmaif_rd_req_pd[47-1:0] = (skid_flop_mc_dma_rd_req_rdy_f) ? dmaif_rd_req_pd[47-1:0] : skid_flop_dmaif_rd_req_pd[47-1:0]; + + +// PIPE READY +assign skid_mc_dma_rd_req_rdy_f = pipe_skid_mc_dma_rd_req_rdy_f || !pipe_skid_mc_dma_rd_req_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_mc_dma_rd_req_vld <= 1'b0; + end else begin + if (skid_mc_dma_rd_req_rdy_f) begin + pipe_skid_mc_dma_rd_req_vld <= skid_mc_dma_rd_req_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_mc_dma_rd_req_rdy_f && skid_mc_dma_rd_req_vld) begin + pipe_skid_dmaif_rd_req_pd[47-1:0] <= skid_dmaif_rd_req_pd[47-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_mc_dma_rd_req_rdy_f = mcif_rd_req_ready; +assign mcif_rd_req_valid = pipe_skid_mc_dma_rd_req_vld; +assign mcif_rd_req_pd = pipe_skid_dmaif_rd_req_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign mc_dma_rd_req_rdy = mc_dma_rd_req_rdy_f; +assign rd_req_rdyi = mc_rd_req_rdyi; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v.vcp new file mode 100644 index 0000000..b82f4b0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v.vcp @@ -0,0 +1,46 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_DMAIF_rdreq.v +`include "simulate_x_tick.vh" +module NV_NVDLA_DMAIF_rdreq ( + nvdla_core_clk + ,nvdla_core_rstn + ,reg2dp_src_ram_type + ,mcif_rd_req_pd + ,mcif_rd_req_valid + ,mcif_rd_req_ready + ,dmaif_rd_req_pd + ,dmaif_rd_req_vld + ,dmaif_rd_req_rdy +); +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_src_ram_type; +output [32 +14:0] mcif_rd_req_pd; +output mcif_rd_req_valid; +input mcif_rd_req_ready; +input [32 +14:0] dmaif_rd_req_pd; +input dmaif_rd_req_vld; +output dmaif_rd_req_rdy; +////////////////////////////////////////////// +wire mc_dma_rd_req_vld; +wire mc_dma_rd_req_rdy; +wire mc_rd_req_rdyi; +wire dma_rd_req_ram_type; +wire rd_req_rdyi; +////////////////////////////////////////////// +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +assign mc_dma_rd_req_vld = dmaif_rd_req_vld & (dma_rd_req_ram_type == 1'b1); +assign mc_rd_req_rdyi = mc_dma_rd_req_rdy & (dma_rd_req_ram_type == 1'b1); +assign dmaif_rd_req_rdy= rd_req_rdyi; +//: my $dmabw = ( 32 + 15 ); +//: &eperl::pipe(" -wid $dmabw -is -do mcif_rd_req_pd -vo mcif_rd_req_valid -ri mcif_rd_req_ready -di dmaif_rd_req_pd -vi mc_dma_rd_req_vld -ro mc_dma_rd_req_rdy_f "); +assign mc_dma_rd_req_rdy = mc_dma_rd_req_rdy_f; +assign rd_req_rdyi = mc_rd_req_rdyi; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v new file mode 100644 index 0000000..56ba109 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v @@ -0,0 +1,242 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_DMAIF_rdrsp.v +`include "simulate_x_tick.vh" +module NV_NVDLA_DMAIF_rdrsp ( + nvdla_core_clk + ,nvdla_core_rstn + ,mcif_rd_rsp_pd + ,mcif_rd_rsp_valid + ,mcif_rd_rsp_ready + ,dmaif_rd_rsp_pd + ,dmaif_rd_rsp_pvld + ,dmaif_rd_rsp_prdy +); +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: print qq( input [${dmabw}-1:0] mcif_rd_rsp_pd; \n); +//: print qq( output [${dmabw}-1:0] dmaif_rd_rsp_pd; \n); +//| eperl: generated_beg (DO NOT EDIT BELOW) + input [65-1:0] mcif_rd_rsp_pd; + output [65-1:0] dmaif_rd_rsp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input mcif_rd_rsp_valid; +output mcif_rd_rsp_ready; +output dmaif_rd_rsp_pvld; +input dmaif_rd_rsp_prdy; +////////////////////////////////////////////// +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: print qq( wire [${dmabw}-1:0] dma_rd_rsp_pd; \n); +//| eperl: generated_beg (DO NOT EDIT BELOW) + wire [65-1:0] dma_rd_rsp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////// +/////////////////////////////////////// +// pipe before mux +/////////////////////////////////////// +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: &eperl::pipe(" -wid $dmabw -is -do mcif_rd_rsp_pd_d0 -vo mcif_rd_rsp_valid_d0 -ri dma_rd_rsp_rdy -di mcif_rd_rsp_pd -vi mcif_rd_rsp_valid -ro mcif_rd_rsp_ready "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg mcif_rd_rsp_ready; +reg skid_flop_mcif_rd_rsp_ready; +reg skid_flop_mcif_rd_rsp_valid; +reg [65-1:0] skid_flop_mcif_rd_rsp_pd; +reg pipe_skid_mcif_rd_rsp_valid; +reg [65-1:0] pipe_skid_mcif_rd_rsp_pd; +// Wire +wire skid_mcif_rd_rsp_valid; +wire [65-1:0] skid_mcif_rd_rsp_pd; +wire skid_mcif_rd_rsp_ready; +wire pipe_skid_mcif_rd_rsp_ready; +wire mcif_rd_rsp_valid_d0; +wire [65-1:0] mcif_rd_rsp_pd_d0; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif_rd_rsp_ready <= 1'b1; + skid_flop_mcif_rd_rsp_ready <= 1'b1; + end else begin + mcif_rd_rsp_ready <= skid_mcif_rd_rsp_ready; + skid_flop_mcif_rd_rsp_ready <= skid_mcif_rd_rsp_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_mcif_rd_rsp_valid <= 1'b0; + end else begin + if (skid_flop_mcif_rd_rsp_ready) begin + skid_flop_mcif_rd_rsp_valid <= mcif_rd_rsp_valid; + end + end +end +assign skid_mcif_rd_rsp_valid = (skid_flop_mcif_rd_rsp_ready) ? mcif_rd_rsp_valid : skid_flop_mcif_rd_rsp_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_mcif_rd_rsp_ready & mcif_rd_rsp_valid) begin + skid_flop_mcif_rd_rsp_pd[65-1:0] <= mcif_rd_rsp_pd[65-1:0]; + end +end +assign skid_mcif_rd_rsp_pd[65-1:0] = (skid_flop_mcif_rd_rsp_ready) ? mcif_rd_rsp_pd[65-1:0] : skid_flop_mcif_rd_rsp_pd[65-1:0]; + + +// PIPE READY +assign skid_mcif_rd_rsp_ready = pipe_skid_mcif_rd_rsp_ready || !pipe_skid_mcif_rd_rsp_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_mcif_rd_rsp_valid <= 1'b0; + end else begin + if (skid_mcif_rd_rsp_ready) begin + pipe_skid_mcif_rd_rsp_valid <= skid_mcif_rd_rsp_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_mcif_rd_rsp_ready && skid_mcif_rd_rsp_valid) begin + pipe_skid_mcif_rd_rsp_pd[65-1:0] <= skid_mcif_rd_rsp_pd[65-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_mcif_rd_rsp_ready = dma_rd_rsp_rdy; +assign mcif_rd_rsp_valid_d0 = pipe_skid_mcif_rd_rsp_valid; +assign mcif_rd_rsp_pd_d0 = pipe_skid_mcif_rd_rsp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////////////////////////// +//mux +/////////////////////////////////////// +assign dma_rd_rsp_vld = mcif_rd_rsp_valid_d0; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: print qq( +//: assign dma_rd_rsp_pd = ({${dmabw}{mcif_rd_rsp_valid_d0}} & mcif_rd_rsp_pd_d0); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dma_rd_rsp_pd = ({65{mcif_rd_rsp_valid_d0}} & mcif_rd_rsp_pd_d0); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// //: &eperl::assert(" -type never -desc 'DMAIF: mcif and cvif should never return data both' -expr 'mcif_rd_rsp_valid_d0 & cvif_rd_rsp_valid_d0' "); +/////////////////////////////////////// +// pipe after mux +/////////////////////////////////////// +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: &eperl::pipe(" -wid $dmabw -is -do dmaif_rd_rsp_pd -vo dmaif_rd_rsp_pvld -ri dmaif_rd_rsp_prdy -di dma_rd_rsp_pd -vi dma_rd_rsp_vld -ro dma_rd_rsp_rdy_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg dma_rd_rsp_rdy_f; +reg skid_flop_dma_rd_rsp_rdy_f; +reg skid_flop_dma_rd_rsp_vld; +reg [65-1:0] skid_flop_dma_rd_rsp_pd; +reg pipe_skid_dma_rd_rsp_vld; +reg [65-1:0] pipe_skid_dma_rd_rsp_pd; +// Wire +wire skid_dma_rd_rsp_vld; +wire [65-1:0] skid_dma_rd_rsp_pd; +wire skid_dma_rd_rsp_rdy_f; +wire pipe_skid_dma_rd_rsp_rdy_f; +wire dmaif_rd_rsp_pvld; +wire [65-1:0] dmaif_rd_rsp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rd_rsp_rdy_f <= 1'b1; + skid_flop_dma_rd_rsp_rdy_f <= 1'b1; + end else begin + dma_rd_rsp_rdy_f <= skid_dma_rd_rsp_rdy_f; + skid_flop_dma_rd_rsp_rdy_f <= skid_dma_rd_rsp_rdy_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_dma_rd_rsp_vld <= 1'b0; + end else begin + if (skid_flop_dma_rd_rsp_rdy_f) begin + skid_flop_dma_rd_rsp_vld <= dma_rd_rsp_vld; + end + end +end +assign skid_dma_rd_rsp_vld = (skid_flop_dma_rd_rsp_rdy_f) ? dma_rd_rsp_vld : skid_flop_dma_rd_rsp_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_dma_rd_rsp_rdy_f & dma_rd_rsp_vld) begin + skid_flop_dma_rd_rsp_pd[65-1:0] <= dma_rd_rsp_pd[65-1:0]; + end +end +assign skid_dma_rd_rsp_pd[65-1:0] = (skid_flop_dma_rd_rsp_rdy_f) ? dma_rd_rsp_pd[65-1:0] : skid_flop_dma_rd_rsp_pd[65-1:0]; + + +// PIPE READY +assign skid_dma_rd_rsp_rdy_f = pipe_skid_dma_rd_rsp_rdy_f || !pipe_skid_dma_rd_rsp_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_dma_rd_rsp_vld <= 1'b0; + end else begin + if (skid_dma_rd_rsp_rdy_f) begin + pipe_skid_dma_rd_rsp_vld <= skid_dma_rd_rsp_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_dma_rd_rsp_rdy_f && skid_dma_rd_rsp_vld) begin + pipe_skid_dma_rd_rsp_pd[65-1:0] <= skid_dma_rd_rsp_pd[65-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_dma_rd_rsp_rdy_f = dmaif_rd_rsp_prdy; +assign dmaif_rd_rsp_pvld = pipe_skid_dma_rd_rsp_vld; +assign dmaif_rd_rsp_pd = pipe_skid_dma_rd_rsp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rd_rsp_rdy = dma_rd_rsp_rdy_f; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v.vcp new file mode 100644 index 0000000..18b06a4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v.vcp @@ -0,0 +1,76 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_DMAIF_rdrsp.v +`include "simulate_x_tick.vh" +module NV_NVDLA_DMAIF_rdrsp ( + nvdla_core_clk + ,nvdla_core_rstn + ,mcif_rd_rsp_pd + ,mcif_rd_rsp_valid + ,mcif_rd_rsp_ready + ,dmaif_rd_rsp_pd + ,dmaif_rd_rsp_pvld + ,dmaif_rd_rsp_prdy +); +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: print qq( input [${dmabw}-1:0] mcif_rd_rsp_pd; \n); +//: print qq( output [${dmabw}-1:0] dmaif_rd_rsp_pd; \n); +input mcif_rd_rsp_valid; +output mcif_rd_rsp_ready; +output dmaif_rd_rsp_pvld; +input dmaif_rd_rsp_prdy; +////////////////////////////////////////////// +wire dma_rd_rsp_rdy; +wire dma_rd_rsp_vld; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: print qq( wire [${dmabw}-1:0] dma_rd_rsp_pd; \n); +////////////////////////////////////////////// +/////////////////////////////////////// +// pipe before mux +/////////////////////////////////////// +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: &eperl::pipe(" -wid $dmabw -is -do mcif_rd_rsp_pd_d0 -vo mcif_rd_rsp_valid_d0 -ri dma_rd_rsp_rdy -di mcif_rd_rsp_pd -vi mcif_rd_rsp_valid -ro mcif_rd_rsp_ready "); +/////////////////////////////////////// +//mux +/////////////////////////////////////// +assign dma_rd_rsp_vld = mcif_rd_rsp_valid_d0; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: print qq( +//: assign dma_rd_rsp_pd = ({${dmabw}{mcif_rd_rsp_valid_d0}} & mcif_rd_rsp_pd_d0); +//: ); +// //: &eperl::assert(" -type never -desc 'DMAIF: mcif and cvif should never return data both' -expr 'mcif_rd_rsp_valid_d0 & cvif_rd_rsp_valid_d0' "); +/////////////////////////////////////// +// pipe after mux +/////////////////////////////////////// +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $maskbw; +//: $maskbw = $mask; +//: my $dmabw = ( $dmaif + $maskbw ); +//: &eperl::pipe(" -wid $dmabw -is -do dmaif_rd_rsp_pd -vo dmaif_rd_rsp_pvld -ri dmaif_rd_rsp_prdy -di dma_rd_rsp_pd -vi dma_rd_rsp_vld -ro dma_rd_rsp_rdy_f "); +assign dma_rd_rsp_rdy = dma_rd_rsp_rdy_f; +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v new file mode 100644 index 0000000..4f975db --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v @@ -0,0 +1,243 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_DMAIF_wr.v +`include "simulate_x_tick.vh" +module NV_NVDLA_DMAIF_wr ( + nvdla_core_clk + ,nvdla_core_rstn + ,reg2dp_dst_ram_type + ,mcif_wr_req_pd + ,mcif_wr_req_valid + ,mcif_wr_req_ready + ,mcif_wr_rsp_complete + ,dmaif_wr_req_pd + ,dmaif_wr_req_pvld + ,dmaif_wr_req_prdy + ,dmaif_wr_rsp_complete +); +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_dst_ram_type; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask ); +//: print qq( output [${dmabw}:0] mcif_wr_req_pd; \n); +//| eperl: generated_beg (DO NOT EDIT BELOW) + output [65:0] mcif_wr_req_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output mcif_wr_req_valid; +input mcif_wr_req_ready; +input mcif_wr_rsp_complete; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask ); +//: print qq( input [${dmabw}:0] dmaif_wr_req_pd; \n); +//| eperl: generated_beg (DO NOT EDIT BELOW) + input [65:0] dmaif_wr_req_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input dmaif_wr_req_pvld; +output dmaif_wr_req_prdy; +output dmaif_wr_rsp_complete; +////////////////////////////////////////////// +reg dmaif_wr_rsp_complete; +wire dma_wr_req_type; +wire mc_dma_wr_req_vld; +wire mc_dma_wr_req_rdy; +wire mc_wr_req_rdyi; +wire wr_req_rdyi; +//============== +// DMA Interface +//============== +assign dma_wr_req_type = reg2dp_dst_ram_type; +// wr Channel: Request +assign wr_req_rdyi = mc_wr_req_rdyi; +assign mc_dma_wr_req_vld = dmaif_wr_req_pvld & (dma_wr_req_type == 1'b1); +assign mc_wr_req_rdyi = mc_dma_wr_req_rdy & (dma_wr_req_type == 1'b1); +assign dmaif_wr_req_prdy= wr_req_rdyi; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask + 1 ); +//: &eperl::pipe(" -wid $dmabw -is -do mcif_wr_req_pd -vo mcif_wr_req_valid -ri mcif_wr_req_ready -di dmaif_wr_req_pd -vi mc_dma_wr_req_vld -ro mc_dma_wr_req_rdy_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg mc_dma_wr_req_rdy_f; +reg skid_flop_mc_dma_wr_req_rdy_f; +reg skid_flop_mc_dma_wr_req_vld; +reg [66-1:0] skid_flop_dmaif_wr_req_pd; +reg pipe_skid_mc_dma_wr_req_vld; +reg [66-1:0] pipe_skid_dmaif_wr_req_pd; +// Wire +wire skid_mc_dma_wr_req_vld; +wire [66-1:0] skid_dmaif_wr_req_pd; +wire skid_mc_dma_wr_req_rdy_f; +wire pipe_skid_mc_dma_wr_req_rdy_f; +wire mcif_wr_req_valid; +wire [66-1:0] mcif_wr_req_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_dma_wr_req_rdy_f <= 1'b1; + skid_flop_mc_dma_wr_req_rdy_f <= 1'b1; + end else begin + mc_dma_wr_req_rdy_f <= skid_mc_dma_wr_req_rdy_f; + skid_flop_mc_dma_wr_req_rdy_f <= skid_mc_dma_wr_req_rdy_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_mc_dma_wr_req_vld <= 1'b0; + end else begin + if (skid_flop_mc_dma_wr_req_rdy_f) begin + skid_flop_mc_dma_wr_req_vld <= mc_dma_wr_req_vld; + end + end +end +assign skid_mc_dma_wr_req_vld = (skid_flop_mc_dma_wr_req_rdy_f) ? mc_dma_wr_req_vld : skid_flop_mc_dma_wr_req_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_mc_dma_wr_req_rdy_f & mc_dma_wr_req_vld) begin + skid_flop_dmaif_wr_req_pd[66-1:0] <= dmaif_wr_req_pd[66-1:0]; + end +end +assign skid_dmaif_wr_req_pd[66-1:0] = (skid_flop_mc_dma_wr_req_rdy_f) ? dmaif_wr_req_pd[66-1:0] : skid_flop_dmaif_wr_req_pd[66-1:0]; + + +// PIPE READY +assign skid_mc_dma_wr_req_rdy_f = pipe_skid_mc_dma_wr_req_rdy_f || !pipe_skid_mc_dma_wr_req_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_mc_dma_wr_req_vld <= 1'b0; + end else begin + if (skid_mc_dma_wr_req_rdy_f) begin + pipe_skid_mc_dma_wr_req_vld <= skid_mc_dma_wr_req_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_mc_dma_wr_req_rdy_f && skid_mc_dma_wr_req_vld) begin + pipe_skid_dmaif_wr_req_pd[66-1:0] <= skid_dmaif_wr_req_pd[66-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_mc_dma_wr_req_rdy_f = mcif_wr_req_ready; +assign mcif_wr_req_valid = pipe_skid_mc_dma_wr_req_vld; +assign mcif_wr_req_pd = pipe_skid_dmaif_wr_req_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign mc_dma_wr_req_rdy = mc_dma_wr_req_rdy_f; +// wr Channel: Response +wire ack_top_rdy; +wire releasing; +reg ack_top_vld ; +reg ack_top_id ; +wire ack_bot_rdy; +reg ack_bot_vld ; +reg ack_bot_id ; +wire ack_raw_rdy; +wire ack_raw_id; +wire ack_raw_vld; +wire require_ack; +wire mc_int_wr_rsp_complete; +assign mc_int_wr_rsp_complete = mcif_wr_rsp_complete; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask + 1 ); +//: if($dmaif > 64) { +//: print qq( assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[77]==1); \n); +//: } else { +//: print qq( assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[45]==1); \n); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign require_ack = (dmaif_wr_req_pd[66-1]==0) & (dmaif_wr_req_pd[45]==1); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[77:77]==1); +assign ack_raw_vld = dmaif_wr_req_pvld & wr_req_rdyi & require_ack; +assign ack_raw_id = dma_wr_req_type; +// stage1: bot +assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld; +always @(posedge nvdla_core_clk) begin + if (ack_raw_vld & ack_raw_rdy) + ack_bot_id <= ack_raw_id; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_bot_vld <= 1'b0; + end else if (ack_raw_rdy) begin + ack_bot_vld <= ack_raw_vld; + end +end +////: &eperl::assert(" -type never -desc `dmaif bot never push back` -expr `ack_raw_vld & !ack_raw_rdy` "); +// stage2: top +assign ack_bot_rdy = ack_top_rdy || !ack_top_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_id <= 1'b0; + end else if (ack_bot_vld & ack_bot_rdy) begin + ack_top_id <= ack_bot_id; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_vld <= 1'b0; + end else if (ack_bot_rdy) begin + ack_top_vld <= ack_bot_vld; + end +end +assign ack_top_rdy = releasing; +reg mc_dma_wr_rsp_complete; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_dma_wr_rsp_complete <= 1'b0; + end else begin + mc_dma_wr_rsp_complete <= mc_int_wr_rsp_complete; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dmaif_wr_rsp_complete <= 1'b0; + end else begin + dmaif_wr_rsp_complete <= releasing; + end +end +reg mc_pending; +wire mc_releasing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_pending <= 1'b0; + end else begin + if (ack_top_id==0) begin + if (mc_dma_wr_rsp_complete) begin + mc_pending <= 1'b1; + end + end else if (ack_top_id==1) begin + if (mc_pending) begin + mc_pending <= 1'b0; + end + end + end +end +assign mc_releasing = ack_top_id==1'b1 & (mc_dma_wr_rsp_complete | mc_pending); +assign releasing = mc_releasing; +////: &eperl::assert(" -type never -desc 'no mc resp back and pending together' -expr 'mc_pending & mc_dma_wr_rsp_complete' ); +////: &eperl::assert(" -type never -desc 'no ack_top_vld when resp from mc' -expr '(mc_pending | mc_dma_wr_rsp_complete) & !ack_top_vld' ); +////////////////////////// +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v.vcp new file mode 100644 index 0000000..5ee1991 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v.vcp @@ -0,0 +1,155 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_DMAIF_wr.v +`include "simulate_x_tick.vh" +module NV_NVDLA_DMAIF_wr ( + nvdla_core_clk + ,nvdla_core_rstn + ,reg2dp_dst_ram_type + ,mcif_wr_req_pd + ,mcif_wr_req_valid + ,mcif_wr_req_ready + ,mcif_wr_rsp_complete + ,dmaif_wr_req_pd + ,dmaif_wr_req_pvld + ,dmaif_wr_req_prdy + ,dmaif_wr_rsp_complete +); +////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_dst_ram_type; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask ); +//: print qq( output [${dmabw}:0] mcif_wr_req_pd; \n); +output mcif_wr_req_valid; +input mcif_wr_req_ready; +input mcif_wr_rsp_complete; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask ); +//: print qq( input [${dmabw}:0] dmaif_wr_req_pd; \n); +input dmaif_wr_req_pvld; +output dmaif_wr_req_prdy; +output dmaif_wr_rsp_complete; +////////////////////////////////////////////// +reg dmaif_wr_rsp_complete; +wire dma_wr_req_type; +wire mc_dma_wr_req_vld; +wire mc_dma_wr_req_rdy; +wire mc_wr_req_rdyi; +wire wr_req_rdyi; +//============== +// DMA Interface +//============== +assign dma_wr_req_type = reg2dp_dst_ram_type; +// wr Channel: Request +assign wr_req_rdyi = mc_wr_req_rdyi; +assign mc_dma_wr_req_vld = dmaif_wr_req_pvld & (dma_wr_req_type == 1'b1); +assign mc_wr_req_rdyi = mc_dma_wr_req_rdy & (dma_wr_req_type == 1'b1); +assign dmaif_wr_req_prdy= wr_req_rdyi; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask + 1 ); +//: &eperl::pipe(" -wid $dmabw -is -do mcif_wr_req_pd -vo mcif_wr_req_valid -ri mcif_wr_req_ready -di dmaif_wr_req_pd -vi mc_dma_wr_req_vld -ro mc_dma_wr_req_rdy_f "); +assign mc_dma_wr_req_rdy = mc_dma_wr_req_rdy_f; +// wr Channel: Response +wire ack_top_rdy; +wire releasing; +reg ack_top_vld ; +reg ack_top_id ; +wire ack_bot_rdy; +reg ack_bot_vld ; +reg ack_bot_id ; +wire ack_raw_rdy; +wire ack_raw_id; +wire ack_raw_vld; +wire require_ack; +wire mc_int_wr_rsp_complete; +assign mc_int_wr_rsp_complete = mcif_wr_rsp_complete; +//: my $dmaif = 64; +//: my $mask = int($dmaif/8/8); +//: my $dmabw = ( $dmaif + $mask + 1 ); +//: if($dmaif > 64) { +//: print qq( assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[77]==1); \n); +//: } else { +//: print qq( assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[45]==1); \n); +//: } +// assign require_ack = (dmaif_wr_req_pd[${dmabw}-1]==0) & (dmaif_wr_req_pd[77:77]==1); +assign ack_raw_vld = dmaif_wr_req_pvld & wr_req_rdyi & require_ack; +assign ack_raw_id = dma_wr_req_type; +// stage1: bot +assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld; +always @(posedge nvdla_core_clk) begin + if (ack_raw_vld & ack_raw_rdy) + ack_bot_id <= ack_raw_id; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_bot_vld <= 1'b0; + end else if (ack_raw_rdy) begin + ack_bot_vld <= ack_raw_vld; + end +end +////: &eperl::assert(" -type never -desc `dmaif bot never push back` -expr `ack_raw_vld & !ack_raw_rdy` "); +// stage2: top +assign ack_bot_rdy = ack_top_rdy || !ack_top_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_id <= 1'b0; + end else if (ack_bot_vld & ack_bot_rdy) begin + ack_top_id <= ack_bot_id; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_vld <= 1'b0; + end else if (ack_bot_rdy) begin + ack_top_vld <= ack_bot_vld; + end +end +assign ack_top_rdy = releasing; +reg mc_dma_wr_rsp_complete; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_dma_wr_rsp_complete <= 1'b0; + end else begin + mc_dma_wr_rsp_complete <= mc_int_wr_rsp_complete; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dmaif_wr_rsp_complete <= 1'b0; + end else begin + dmaif_wr_rsp_complete <= releasing; + end +end +reg mc_pending; +wire mc_releasing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_pending <= 1'b0; + end else begin + if (ack_top_id==0) begin + if (mc_dma_wr_rsp_complete) begin + mc_pending <= 1'b1; + end + end else if (ack_top_id==1) begin + if (mc_pending) begin + mc_pending <= 1'b0; + end + end + end +end +assign mc_releasing = ack_top_id==1'b1 & (mc_dma_wr_rsp_complete | mc_pending); +assign releasing = mc_releasing; +////: &eperl::assert(" -type never -desc 'no mc resp back and pending together' -expr 'mc_pending & mc_dma_wr_rsp_complete' ); +////: &eperl::assert(" -type never -desc 'no ack_top_vld when resp from mc' -expr '(mc_pending | mc_dma_wr_rsp_complete) & !ack_top_vld' ); +////////////////////////// +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v new file mode 100644 index 0000000..970e368 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v @@ -0,0 +1,323 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_MCIF_CSB_reg.v +module NV_NVDLA_MCIF_CSB_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,rd_os_cnt + ,wr_os_cnt + ,rd_weight_bdma + ,rd_weight_cdp + ,rd_weight_pdp + ,rd_weight_sdp + ,rd_weight_cdma_dat + ,rd_weight_sdp_b + ,rd_weight_sdp_e + ,rd_weight_sdp_n + ,rd_weight_cdma_wt + ,rd_weight_rbk + ,rd_weight_rsv_0 + ,rd_weight_rsv_1 + ,wr_weight_bdma + ,wr_weight_cdp + ,wr_weight_pdp + ,wr_weight_sdp + ,wr_weight_rbk + ,wr_weight_rsv_0 + ,wr_weight_rsv_1 + ,wr_weight_rsv_2 + ,idle + ); +wire [31:0] nvdla_mcif_cfg_outstanding_cnt_0_out; +wire [31:0] nvdla_mcif_cfg_rd_weight_0_0_out; +wire [31:0] nvdla_mcif_cfg_rd_weight_1_0_out; +wire [31:0] nvdla_mcif_cfg_rd_weight_2_0_out; +wire [31:0] nvdla_mcif_cfg_wr_weight_0_0_out; +wire [31:0] nvdla_mcif_cfg_wr_weight_1_0_out; +wire [31:0] nvdla_mcif_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [7:0] rd_os_cnt; +output [7:0] wr_os_cnt; +output [7:0] rd_weight_bdma; +output [7:0] rd_weight_cdp; +output [7:0] rd_weight_pdp; +output [7:0] rd_weight_sdp; +output [7:0] rd_weight_cdma_dat; +output [7:0] rd_weight_sdp_b; +output [7:0] rd_weight_sdp_e; +output [7:0] rd_weight_sdp_n; +output [7:0] rd_weight_cdma_wt; +output [7:0] rd_weight_rbk; +output [7:0] rd_weight_rsv_0; +output [7:0] rd_weight_rsv_1; +output [7:0] wr_weight_bdma; +output [7:0] wr_weight_cdp; +output [7:0] wr_weight_pdp; +output [7:0] wr_weight_sdp; +output [7:0] wr_weight_rbk; +output [7:0] wr_weight_rsv_0; +output [7:0] wr_weight_rsv_1; +output [7:0] wr_weight_rsv_2; +// Read-only register inputs +input idle; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [7:0] rd_os_cnt; +reg [7:0] rd_weight_bdma; +reg [7:0] rd_weight_cdma_dat; +reg [7:0] rd_weight_cdma_wt; +reg [7:0] rd_weight_cdp; +reg [7:0] rd_weight_pdp; +reg [7:0] rd_weight_rbk; +reg [7:0] rd_weight_rsv_0; +reg [7:0] rd_weight_rsv_1; +reg [7:0] rd_weight_sdp; +reg [7:0] rd_weight_sdp_b; +reg [7:0] rd_weight_sdp_e; +reg [7:0] rd_weight_sdp_n; +reg [31:0] reg_rd_data; +reg [7:0] wr_os_cnt; +reg [7:0] wr_weight_bdma; +reg [7:0] wr_weight_cdp; +reg [7:0] wr_weight_pdp; +reg [7:0] wr_weight_rbk; +reg [7:0] wr_weight_rsv_0; +reg [7:0] wr_weight_rsv_1; +reg [7:0] wr_weight_rsv_2; +reg [7:0] wr_weight_sdp; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_mcif_cfg_outstanding_cnt_0_wren = (reg_offset_wr == (32'h2014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_rd_weight_0_0_wren = (reg_offset_wr == (32'h2000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_rd_weight_1_0_wren = (reg_offset_wr == (32'h2004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_rd_weight_2_0_wren = (reg_offset_wr == (32'h2008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_wr_weight_0_0_wren = (reg_offset_wr == (32'h200c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_wr_weight_1_0_wren = (reg_offset_wr == (32'h2010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_status_0_wren = (reg_offset_wr == (32'h2018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_mcif_cfg_outstanding_cnt_0_out[31:0] = { 16'b0, wr_os_cnt, rd_os_cnt }; +assign nvdla_mcif_cfg_rd_weight_0_0_out[31:0] = { rd_weight_cdp, rd_weight_pdp, rd_weight_sdp, rd_weight_bdma }; +assign nvdla_mcif_cfg_rd_weight_1_0_out[31:0] = { rd_weight_cdma_dat, rd_weight_sdp_e, rd_weight_sdp_n, rd_weight_sdp_b }; +assign nvdla_mcif_cfg_rd_weight_2_0_out[31:0] = { rd_weight_rsv_0, rd_weight_rsv_1, rd_weight_rbk, rd_weight_cdma_wt }; +assign nvdla_mcif_cfg_wr_weight_0_0_out[31:0] = { wr_weight_cdp, wr_weight_pdp, wr_weight_sdp, wr_weight_bdma }; +assign nvdla_mcif_cfg_wr_weight_1_0_out[31:0] = { wr_weight_rsv_0, wr_weight_rsv_1, wr_weight_rsv_2, wr_weight_rbk }; +assign nvdla_mcif_status_0_out[31:0] = { 23'b0, idle, 8'b0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_mcif_cfg_outstanding_cnt_0_out + or nvdla_mcif_cfg_rd_weight_0_0_out + or nvdla_mcif_cfg_rd_weight_1_0_out + or nvdla_mcif_cfg_rd_weight_2_0_out + or nvdla_mcif_cfg_wr_weight_0_0_out + or nvdla_mcif_cfg_wr_weight_1_0_out + or nvdla_mcif_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h2014 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_outstanding_cnt_0_out ; + end + (32'h2000 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_rd_weight_0_0_out ; + end + (32'h2004 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_rd_weight_1_0_out ; + end + (32'h2008 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_rd_weight_2_0_out ; + end + (32'h200c & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_wr_weight_0_0_out ; + end + (32'h2010 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_wr_weight_1_0_out ; + end + (32'h2018 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_os_cnt[7:0] <= 8'b11111111; + wr_os_cnt[7:0] <= 8'b11111111; + rd_weight_bdma[7:0] <= 8'b00000001; + rd_weight_cdp[7:0] <= 8'b00000001; + rd_weight_pdp[7:0] <= 8'b00000001; + rd_weight_sdp[7:0] <= 8'b00000001; + rd_weight_cdma_dat[7:0] <= 8'b00000001; + rd_weight_sdp_b[7:0] <= 8'b00000001; + rd_weight_sdp_e[7:0] <= 8'b00000001; + rd_weight_sdp_n[7:0] <= 8'b00000001; + rd_weight_cdma_wt[7:0] <= 8'b00000001; + rd_weight_rbk[7:0] <= 8'b00000001; + rd_weight_rsv_0[7:0] <= 8'b00000001; + rd_weight_rsv_1[7:0] <= 8'b00000001; + wr_weight_bdma[7:0] <= 8'b00000001; + wr_weight_cdp[7:0] <= 8'b00000001; + wr_weight_pdp[7:0] <= 8'b00000001; + wr_weight_sdp[7:0] <= 8'b00000001; + wr_weight_rbk[7:0] <= 8'b00000001; + wr_weight_rsv_0[7:0] <= 8'b00000001; + wr_weight_rsv_1[7:0] <= 8'b00000001; + wr_weight_rsv_2[7:0] <= 8'b00000001; + end else begin +// Register: NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 Field: rd_os_cnt + if (nvdla_mcif_cfg_outstanding_cnt_0_wren) begin + rd_os_cnt[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 Field: wr_os_cnt + if (nvdla_mcif_cfg_outstanding_cnt_0_wren) begin + wr_os_cnt[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_bdma + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_bdma[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_cdp + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_cdp[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_pdp + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_pdp[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_sdp + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_sdp[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_cdma_dat + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_cdma_dat[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_sdp_b + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_sdp_b[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_sdp_e + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_sdp_e[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_sdp_n + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_sdp_n[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_cdma_wt + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_cdma_wt[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_rbk + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_rbk[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_rsv_0 + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_rsv_0[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_rsv_1 + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_rsv_1[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_bdma + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_bdma[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_cdp + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_cdp[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_pdp + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_pdp[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_sdp + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_sdp[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rbk + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rbk[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rsv_0 + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rsv_0[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rsv_1 + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rsv_1[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rsv_2 + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rsv_2[7:0] <= reg_wr_data[15:8]; + end +// Not generating flops for read-only field NVDLA_MCIF_STATUS_0::idle + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h2014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_outstanding_cnt_0_out, nvdla_mcif_cfg_outstanding_cnt_0_out); + (32'h2000 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_rd_weight_0_0_out, nvdla_mcif_cfg_rd_weight_0_0_out); + (32'h2004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_rd_weight_1_0_out, nvdla_mcif_cfg_rd_weight_1_0_out); + (32'h2008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_rd_weight_2_0_out, nvdla_mcif_cfg_rd_weight_2_0_out); + (32'h200c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_wr_weight_0_0_out, nvdla_mcif_cfg_wr_weight_0_0_out); + (32'h2010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_wr_weight_1_0_out, nvdla_mcif_cfg_wr_weight_1_0_out); + (32'h2018 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_MCIF_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_MCIF_CSB_reg diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v.vcp new file mode 100644 index 0000000..970e368 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v.vcp @@ -0,0 +1,323 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_MCIF_CSB_reg.v +module NV_NVDLA_MCIF_CSB_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,rd_os_cnt + ,wr_os_cnt + ,rd_weight_bdma + ,rd_weight_cdp + ,rd_weight_pdp + ,rd_weight_sdp + ,rd_weight_cdma_dat + ,rd_weight_sdp_b + ,rd_weight_sdp_e + ,rd_weight_sdp_n + ,rd_weight_cdma_wt + ,rd_weight_rbk + ,rd_weight_rsv_0 + ,rd_weight_rsv_1 + ,wr_weight_bdma + ,wr_weight_cdp + ,wr_weight_pdp + ,wr_weight_sdp + ,wr_weight_rbk + ,wr_weight_rsv_0 + ,wr_weight_rsv_1 + ,wr_weight_rsv_2 + ,idle + ); +wire [31:0] nvdla_mcif_cfg_outstanding_cnt_0_out; +wire [31:0] nvdla_mcif_cfg_rd_weight_0_0_out; +wire [31:0] nvdla_mcif_cfg_rd_weight_1_0_out; +wire [31:0] nvdla_mcif_cfg_rd_weight_2_0_out; +wire [31:0] nvdla_mcif_cfg_wr_weight_0_0_out; +wire [31:0] nvdla_mcif_cfg_wr_weight_1_0_out; +wire [31:0] nvdla_mcif_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [7:0] rd_os_cnt; +output [7:0] wr_os_cnt; +output [7:0] rd_weight_bdma; +output [7:0] rd_weight_cdp; +output [7:0] rd_weight_pdp; +output [7:0] rd_weight_sdp; +output [7:0] rd_weight_cdma_dat; +output [7:0] rd_weight_sdp_b; +output [7:0] rd_weight_sdp_e; +output [7:0] rd_weight_sdp_n; +output [7:0] rd_weight_cdma_wt; +output [7:0] rd_weight_rbk; +output [7:0] rd_weight_rsv_0; +output [7:0] rd_weight_rsv_1; +output [7:0] wr_weight_bdma; +output [7:0] wr_weight_cdp; +output [7:0] wr_weight_pdp; +output [7:0] wr_weight_sdp; +output [7:0] wr_weight_rbk; +output [7:0] wr_weight_rsv_0; +output [7:0] wr_weight_rsv_1; +output [7:0] wr_weight_rsv_2; +// Read-only register inputs +input idle; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [7:0] rd_os_cnt; +reg [7:0] rd_weight_bdma; +reg [7:0] rd_weight_cdma_dat; +reg [7:0] rd_weight_cdma_wt; +reg [7:0] rd_weight_cdp; +reg [7:0] rd_weight_pdp; +reg [7:0] rd_weight_rbk; +reg [7:0] rd_weight_rsv_0; +reg [7:0] rd_weight_rsv_1; +reg [7:0] rd_weight_sdp; +reg [7:0] rd_weight_sdp_b; +reg [7:0] rd_weight_sdp_e; +reg [7:0] rd_weight_sdp_n; +reg [31:0] reg_rd_data; +reg [7:0] wr_os_cnt; +reg [7:0] wr_weight_bdma; +reg [7:0] wr_weight_cdp; +reg [7:0] wr_weight_pdp; +reg [7:0] wr_weight_rbk; +reg [7:0] wr_weight_rsv_0; +reg [7:0] wr_weight_rsv_1; +reg [7:0] wr_weight_rsv_2; +reg [7:0] wr_weight_sdp; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_mcif_cfg_outstanding_cnt_0_wren = (reg_offset_wr == (32'h2014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_rd_weight_0_0_wren = (reg_offset_wr == (32'h2000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_rd_weight_1_0_wren = (reg_offset_wr == (32'h2004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_rd_weight_2_0_wren = (reg_offset_wr == (32'h2008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_wr_weight_0_0_wren = (reg_offset_wr == (32'h200c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_cfg_wr_weight_1_0_wren = (reg_offset_wr == (32'h2010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_mcif_status_0_wren = (reg_offset_wr == (32'h2018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_mcif_cfg_outstanding_cnt_0_out[31:0] = { 16'b0, wr_os_cnt, rd_os_cnt }; +assign nvdla_mcif_cfg_rd_weight_0_0_out[31:0] = { rd_weight_cdp, rd_weight_pdp, rd_weight_sdp, rd_weight_bdma }; +assign nvdla_mcif_cfg_rd_weight_1_0_out[31:0] = { rd_weight_cdma_dat, rd_weight_sdp_e, rd_weight_sdp_n, rd_weight_sdp_b }; +assign nvdla_mcif_cfg_rd_weight_2_0_out[31:0] = { rd_weight_rsv_0, rd_weight_rsv_1, rd_weight_rbk, rd_weight_cdma_wt }; +assign nvdla_mcif_cfg_wr_weight_0_0_out[31:0] = { wr_weight_cdp, wr_weight_pdp, wr_weight_sdp, wr_weight_bdma }; +assign nvdla_mcif_cfg_wr_weight_1_0_out[31:0] = { wr_weight_rsv_0, wr_weight_rsv_1, wr_weight_rsv_2, wr_weight_rbk }; +assign nvdla_mcif_status_0_out[31:0] = { 23'b0, idle, 8'b0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_mcif_cfg_outstanding_cnt_0_out + or nvdla_mcif_cfg_rd_weight_0_0_out + or nvdla_mcif_cfg_rd_weight_1_0_out + or nvdla_mcif_cfg_rd_weight_2_0_out + or nvdla_mcif_cfg_wr_weight_0_0_out + or nvdla_mcif_cfg_wr_weight_1_0_out + or nvdla_mcif_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h2014 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_outstanding_cnt_0_out ; + end + (32'h2000 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_rd_weight_0_0_out ; + end + (32'h2004 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_rd_weight_1_0_out ; + end + (32'h2008 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_rd_weight_2_0_out ; + end + (32'h200c & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_wr_weight_0_0_out ; + end + (32'h2010 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_cfg_wr_weight_1_0_out ; + end + (32'h2018 & 32'h00000fff): begin + reg_rd_data = nvdla_mcif_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_os_cnt[7:0] <= 8'b11111111; + wr_os_cnt[7:0] <= 8'b11111111; + rd_weight_bdma[7:0] <= 8'b00000001; + rd_weight_cdp[7:0] <= 8'b00000001; + rd_weight_pdp[7:0] <= 8'b00000001; + rd_weight_sdp[7:0] <= 8'b00000001; + rd_weight_cdma_dat[7:0] <= 8'b00000001; + rd_weight_sdp_b[7:0] <= 8'b00000001; + rd_weight_sdp_e[7:0] <= 8'b00000001; + rd_weight_sdp_n[7:0] <= 8'b00000001; + rd_weight_cdma_wt[7:0] <= 8'b00000001; + rd_weight_rbk[7:0] <= 8'b00000001; + rd_weight_rsv_0[7:0] <= 8'b00000001; + rd_weight_rsv_1[7:0] <= 8'b00000001; + wr_weight_bdma[7:0] <= 8'b00000001; + wr_weight_cdp[7:0] <= 8'b00000001; + wr_weight_pdp[7:0] <= 8'b00000001; + wr_weight_sdp[7:0] <= 8'b00000001; + wr_weight_rbk[7:0] <= 8'b00000001; + wr_weight_rsv_0[7:0] <= 8'b00000001; + wr_weight_rsv_1[7:0] <= 8'b00000001; + wr_weight_rsv_2[7:0] <= 8'b00000001; + end else begin +// Register: NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 Field: rd_os_cnt + if (nvdla_mcif_cfg_outstanding_cnt_0_wren) begin + rd_os_cnt[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 Field: wr_os_cnt + if (nvdla_mcif_cfg_outstanding_cnt_0_wren) begin + wr_os_cnt[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_bdma + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_bdma[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_cdp + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_cdp[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_pdp + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_pdp[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 Field: rd_weight_sdp + if (nvdla_mcif_cfg_rd_weight_0_0_wren) begin + rd_weight_sdp[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_cdma_dat + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_cdma_dat[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_sdp_b + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_sdp_b[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_sdp_e + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_sdp_e[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 Field: rd_weight_sdp_n + if (nvdla_mcif_cfg_rd_weight_1_0_wren) begin + rd_weight_sdp_n[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_cdma_wt + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_cdma_wt[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_rbk + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_rbk[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_rsv_0 + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_rsv_0[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 Field: rd_weight_rsv_1 + if (nvdla_mcif_cfg_rd_weight_2_0_wren) begin + rd_weight_rsv_1[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_bdma + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_bdma[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_cdp + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_cdp[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_pdp + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_pdp[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 Field: wr_weight_sdp + if (nvdla_mcif_cfg_wr_weight_0_0_wren) begin + wr_weight_sdp[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rbk + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rbk[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rsv_0 + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rsv_0[7:0] <= reg_wr_data[31:24]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rsv_1 + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rsv_1[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 Field: wr_weight_rsv_2 + if (nvdla_mcif_cfg_wr_weight_1_0_wren) begin + wr_weight_rsv_2[7:0] <= reg_wr_data[15:8]; + end +// Not generating flops for read-only field NVDLA_MCIF_STATUS_0::idle + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h2014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_outstanding_cnt_0_out, nvdla_mcif_cfg_outstanding_cnt_0_out); + (32'h2000 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_RD_WEIGHT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_rd_weight_0_0_out, nvdla_mcif_cfg_rd_weight_0_0_out); + (32'h2004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_RD_WEIGHT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_rd_weight_1_0_out, nvdla_mcif_cfg_rd_weight_1_0_out); + (32'h2008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_RD_WEIGHT_2_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_rd_weight_2_0_out, nvdla_mcif_cfg_rd_weight_2_0_out); + (32'h200c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_WR_WEIGHT_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_wr_weight_0_0_out, nvdla_mcif_cfg_wr_weight_0_0_out); + (32'h2010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_MCIF_CFG_WR_WEIGHT_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_mcif_cfg_wr_weight_1_0_out, nvdla_mcif_cfg_wr_weight_1_0_out); + (32'h2018 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_MCIF_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_MCIF_CSB_reg diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v new file mode 100644 index 0000000..f17a5d9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v @@ -0,0 +1,213 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_MCIF_csb.v +module NV_NVDLA_MCIF_csb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2mcif_req_pd //|< i + ,csb2mcif_req_pvld //|< i + ,dp2reg_idle //|< i + ,csb2mcif_req_prdy //|> o + ,mcif2csb_resp_pd //|> o + ,mcif2csb_resp_valid //|> o + ,reg2dp_rd_os_cnt //|> o + ,reg2dp_rd_weight_bdma //|> o + ,reg2dp_rd_weight_cdma_dat //|> o + ,reg2dp_rd_weight_cdma_wt //|> o + ,reg2dp_rd_weight_cdp //|> o + ,reg2dp_rd_weight_pdp //|> o + ,reg2dp_rd_weight_rbk //|> o + ,reg2dp_rd_weight_rsv_0 //|> o + ,reg2dp_rd_weight_rsv_1 //|> o + ,reg2dp_rd_weight_sdp //|> o + ,reg2dp_rd_weight_sdp_b //|> o + ,reg2dp_rd_weight_sdp_e //|> o + ,reg2dp_rd_weight_sdp_n //|> o + ,reg2dp_wr_os_cnt //|> o + ,reg2dp_wr_weight_bdma //|> o + ,reg2dp_wr_weight_cdp //|> o + ,reg2dp_wr_weight_pdp //|> o + ,reg2dp_wr_weight_rbk //|> o + ,reg2dp_wr_weight_rsv_0 //|> o + ,reg2dp_wr_weight_rsv_1 //|> o + ,reg2dp_wr_weight_rsv_2 //|> o + ,reg2dp_wr_weight_sdp //|> o + ); +// +// NV_NVDLA_MCIF_csb_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input csb2mcif_req_pvld; /* data valid */ +output csb2mcif_req_prdy; /* data return handshake */ +input [62:0] csb2mcif_req_pd; +output mcif2csb_resp_valid; /* data valid */ +output [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input dp2reg_idle; +output [7:0] reg2dp_rd_os_cnt; +output [7:0] reg2dp_rd_weight_bdma; +output [7:0] reg2dp_rd_weight_cdma_dat; +output [7:0] reg2dp_rd_weight_cdma_wt; +output [7:0] reg2dp_rd_weight_cdp; +output [7:0] reg2dp_rd_weight_pdp; +output [7:0] reg2dp_rd_weight_rbk; +output [7:0] reg2dp_rd_weight_rsv_0; +output [7:0] reg2dp_rd_weight_rsv_1; +output [7:0] reg2dp_rd_weight_sdp; +output [7:0] reg2dp_rd_weight_sdp_b; +output [7:0] reg2dp_rd_weight_sdp_e; +output [7:0] reg2dp_rd_weight_sdp_n; +output [7:0] reg2dp_wr_os_cnt; +output [7:0] reg2dp_wr_weight_bdma; +output [7:0] reg2dp_wr_weight_cdp; +output [7:0] reg2dp_wr_weight_pdp; +output [7:0] reg2dp_wr_weight_rbk; +output [7:0] reg2dp_wr_weight_rsv_0; +output [7:0] reg2dp_wr_weight_rsv_1; +output [7:0] reg2dp_wr_weight_rsv_2; +output [7:0] reg2dp_wr_weight_sdp; +reg [33:0] mcif2csb_resp_pd; +reg mcif2csb_resp_valid; +reg [62:0] req_pd; +reg req_vld; +wire [11:0] reg_offset; +wire [31:0] reg_rd_data; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level_NC; +wire req_nposted; +wire req_srcpriv_NC; +wire [31:0] req_wdat; +wire [3:0] req_wrbe_NC; +wire req_write; +wire [33:0] rsp_pd; +wire rsp_rd_error; +wire [32:0] rsp_rd_pd; +wire [31:0] rsp_rd_rdat; +wire rsp_rd_vld; +wire rsp_vld; +wire rsp_wr_error; +wire [32:0] rsp_wr_pd; +wire [31:0] rsp_wr_rdat; +wire rsp_wr_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// &Viva width_learning_on; +// REQ INTERFACE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_vld <= 1'b0; + end else begin + req_vld <= csb2mcif_req_pvld; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2mcif_req_pvld) == 1'b1) begin + req_pd <= csb2mcif_req_pd; +// VCS coverage off + end else if ((csb2mcif_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2mcif_req_prdy = 1'b1; +// ======== +// REQUEST +// ======== +// flow=pvld_prdy +assign req_level_NC = req_pd[62:61]; +assign req_nposted = req_pd[55:55]; +assign req_addr = req_pd[21:0]; +assign req_wrbe_NC = req_pd[60:57]; +assign req_srcpriv_NC = req_pd[56:56]; +assign req_write = req_pd[54:54]; +assign req_wdat = req_pd[53:22]; +// ======== +// RESPONSE +// ======== +// flow=valid +// packet=dla_xx2csb_rd_erpt +assign rsp_rd_pd[32:32] = rsp_rd_error; +assign rsp_rd_pd[31:0] = rsp_rd_rdat; +// packet=dla_xx2csb_wr_erpt +assign rsp_wr_pd[32:32] = rsp_wr_error; +assign rsp_wr_pd[31:0] = rsp_wr_rdat; +assign rsp_rd_vld = req_vld & ~req_write; +assign rsp_rd_rdat = {32{rsp_rd_vld}} & reg_rd_data; +assign rsp_rd_error = 1'b0; +assign rsp_wr_vld = req_vld & req_write & req_nposted; +assign rsp_wr_rdat = {32{1'b0}}; +assign rsp_wr_error = 1'b0; +// ======== +// REQUEST +// ======== +assign rsp_vld = rsp_rd_vld | rsp_wr_vld; +assign rsp_pd[33:33] = ({1{rsp_rd_vld}} & {1'h0}) + | ({1{rsp_wr_vld}} & {1'h1}); +assign rsp_pd[32:0] = ({33{rsp_rd_vld}} & rsp_rd_pd) + | ({33{rsp_wr_vld}} & rsp_wr_pd); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif2csb_resp_valid <= 1'b0; + end else begin + mcif2csb_resp_valid <= rsp_vld; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_vld) == 1'b1) begin + mcif2csb_resp_pd <= rsp_pd; +// VCS coverage off + end else if ((rsp_vld) == 1'b0) begin + end else begin + mcif2csb_resp_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign reg_offset = {req_addr[9:0],{2{1'b0}}}; +assign reg_wr_en = req_vld & req_write; +assign reg_wr_data = req_wdat; +NV_NVDLA_MCIF_CSB_reg u_reg ( + .reg_rd_data (reg_rd_data[31:0]) //|> w + ,.reg_offset (reg_offset[11:0]) //|< w + ,.reg_wr_data (reg_wr_data[31:0]) //|< w + ,.reg_wr_en (reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|> o + ,.wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|> o + ,.rd_weight_bdma (reg2dp_rd_weight_bdma[7:0]) //|> o + ,.rd_weight_cdp (reg2dp_rd_weight_cdp[7:0]) //|> o + ,.rd_weight_pdp (reg2dp_rd_weight_pdp[7:0]) //|> o + ,.rd_weight_sdp (reg2dp_rd_weight_sdp[7:0]) //|> o + ,.rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0]) //|> o + ,.rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0]) //|> o + ,.rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0]) //|> o + ,.rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0]) //|> o + ,.rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0]) //|> o + ,.rd_weight_rbk (reg2dp_rd_weight_rbk[7:0]) //|> o + ,.rd_weight_rsv_0 (reg2dp_rd_weight_rsv_0[7:0]) //|> o + ,.rd_weight_rsv_1 (reg2dp_rd_weight_rsv_1[7:0]) //|> o + ,.wr_weight_bdma (reg2dp_wr_weight_bdma[7:0]) //|> o + ,.wr_weight_cdp (reg2dp_wr_weight_cdp[7:0]) //|> o + ,.wr_weight_pdp (reg2dp_wr_weight_pdp[7:0]) //|> o + ,.wr_weight_sdp (reg2dp_wr_weight_sdp[7:0]) //|> o + ,.wr_weight_rbk (reg2dp_wr_weight_rbk[7:0]) //|> o + ,.wr_weight_rsv_0 (reg2dp_wr_weight_rsv_0[7:0]) //|> o + ,.wr_weight_rsv_1 (reg2dp_wr_weight_rsv_1[7:0]) //|> o + ,.wr_weight_rsv_2 (reg2dp_wr_weight_rsv_2[7:0]) //|> o + ,.idle (dp2reg_idle) //|< i + ); +endmodule // NV_NVDLA_MCIF_csb diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v.vcp new file mode 100644 index 0000000..f17a5d9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v.vcp @@ -0,0 +1,213 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_MCIF_csb.v +module NV_NVDLA_MCIF_csb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2mcif_req_pd //|< i + ,csb2mcif_req_pvld //|< i + ,dp2reg_idle //|< i + ,csb2mcif_req_prdy //|> o + ,mcif2csb_resp_pd //|> o + ,mcif2csb_resp_valid //|> o + ,reg2dp_rd_os_cnt //|> o + ,reg2dp_rd_weight_bdma //|> o + ,reg2dp_rd_weight_cdma_dat //|> o + ,reg2dp_rd_weight_cdma_wt //|> o + ,reg2dp_rd_weight_cdp //|> o + ,reg2dp_rd_weight_pdp //|> o + ,reg2dp_rd_weight_rbk //|> o + ,reg2dp_rd_weight_rsv_0 //|> o + ,reg2dp_rd_weight_rsv_1 //|> o + ,reg2dp_rd_weight_sdp //|> o + ,reg2dp_rd_weight_sdp_b //|> o + ,reg2dp_rd_weight_sdp_e //|> o + ,reg2dp_rd_weight_sdp_n //|> o + ,reg2dp_wr_os_cnt //|> o + ,reg2dp_wr_weight_bdma //|> o + ,reg2dp_wr_weight_cdp //|> o + ,reg2dp_wr_weight_pdp //|> o + ,reg2dp_wr_weight_rbk //|> o + ,reg2dp_wr_weight_rsv_0 //|> o + ,reg2dp_wr_weight_rsv_1 //|> o + ,reg2dp_wr_weight_rsv_2 //|> o + ,reg2dp_wr_weight_sdp //|> o + ); +// +// NV_NVDLA_MCIF_csb_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input csb2mcif_req_pvld; /* data valid */ +output csb2mcif_req_prdy; /* data return handshake */ +input [62:0] csb2mcif_req_pd; +output mcif2csb_resp_valid; /* data valid */ +output [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input dp2reg_idle; +output [7:0] reg2dp_rd_os_cnt; +output [7:0] reg2dp_rd_weight_bdma; +output [7:0] reg2dp_rd_weight_cdma_dat; +output [7:0] reg2dp_rd_weight_cdma_wt; +output [7:0] reg2dp_rd_weight_cdp; +output [7:0] reg2dp_rd_weight_pdp; +output [7:0] reg2dp_rd_weight_rbk; +output [7:0] reg2dp_rd_weight_rsv_0; +output [7:0] reg2dp_rd_weight_rsv_1; +output [7:0] reg2dp_rd_weight_sdp; +output [7:0] reg2dp_rd_weight_sdp_b; +output [7:0] reg2dp_rd_weight_sdp_e; +output [7:0] reg2dp_rd_weight_sdp_n; +output [7:0] reg2dp_wr_os_cnt; +output [7:0] reg2dp_wr_weight_bdma; +output [7:0] reg2dp_wr_weight_cdp; +output [7:0] reg2dp_wr_weight_pdp; +output [7:0] reg2dp_wr_weight_rbk; +output [7:0] reg2dp_wr_weight_rsv_0; +output [7:0] reg2dp_wr_weight_rsv_1; +output [7:0] reg2dp_wr_weight_rsv_2; +output [7:0] reg2dp_wr_weight_sdp; +reg [33:0] mcif2csb_resp_pd; +reg mcif2csb_resp_valid; +reg [62:0] req_pd; +reg req_vld; +wire [11:0] reg_offset; +wire [31:0] reg_rd_data; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level_NC; +wire req_nposted; +wire req_srcpriv_NC; +wire [31:0] req_wdat; +wire [3:0] req_wrbe_NC; +wire req_write; +wire [33:0] rsp_pd; +wire rsp_rd_error; +wire [32:0] rsp_rd_pd; +wire [31:0] rsp_rd_rdat; +wire rsp_rd_vld; +wire rsp_vld; +wire rsp_wr_error; +wire [32:0] rsp_wr_pd; +wire [31:0] rsp_wr_rdat; +wire rsp_wr_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// &Viva width_learning_on; +// REQ INTERFACE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_vld <= 1'b0; + end else begin + req_vld <= csb2mcif_req_pvld; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2mcif_req_pvld) == 1'b1) begin + req_pd <= csb2mcif_req_pd; +// VCS coverage off + end else if ((csb2mcif_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2mcif_req_prdy = 1'b1; +// ======== +// REQUEST +// ======== +// flow=pvld_prdy +assign req_level_NC = req_pd[62:61]; +assign req_nposted = req_pd[55:55]; +assign req_addr = req_pd[21:0]; +assign req_wrbe_NC = req_pd[60:57]; +assign req_srcpriv_NC = req_pd[56:56]; +assign req_write = req_pd[54:54]; +assign req_wdat = req_pd[53:22]; +// ======== +// RESPONSE +// ======== +// flow=valid +// packet=dla_xx2csb_rd_erpt +assign rsp_rd_pd[32:32] = rsp_rd_error; +assign rsp_rd_pd[31:0] = rsp_rd_rdat; +// packet=dla_xx2csb_wr_erpt +assign rsp_wr_pd[32:32] = rsp_wr_error; +assign rsp_wr_pd[31:0] = rsp_wr_rdat; +assign rsp_rd_vld = req_vld & ~req_write; +assign rsp_rd_rdat = {32{rsp_rd_vld}} & reg_rd_data; +assign rsp_rd_error = 1'b0; +assign rsp_wr_vld = req_vld & req_write & req_nposted; +assign rsp_wr_rdat = {32{1'b0}}; +assign rsp_wr_error = 1'b0; +// ======== +// REQUEST +// ======== +assign rsp_vld = rsp_rd_vld | rsp_wr_vld; +assign rsp_pd[33:33] = ({1{rsp_rd_vld}} & {1'h0}) + | ({1{rsp_wr_vld}} & {1'h1}); +assign rsp_pd[32:0] = ({33{rsp_rd_vld}} & rsp_rd_pd) + | ({33{rsp_wr_vld}} & rsp_wr_pd); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mcif2csb_resp_valid <= 1'b0; + end else begin + mcif2csb_resp_valid <= rsp_vld; + end +end +always @(posedge nvdla_core_clk) begin + if ((rsp_vld) == 1'b1) begin + mcif2csb_resp_pd <= rsp_pd; +// VCS coverage off + end else if ((rsp_vld) == 1'b0) begin + end else begin + mcif2csb_resp_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign reg_offset = {req_addr[9:0],{2{1'b0}}}; +assign reg_wr_en = req_vld & req_write; +assign reg_wr_data = req_wdat; +NV_NVDLA_MCIF_CSB_reg u_reg ( + .reg_rd_data (reg_rd_data[31:0]) //|> w + ,.reg_offset (reg_offset[11:0]) //|< w + ,.reg_wr_data (reg_wr_data[31:0]) //|< w + ,.reg_wr_en (reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|> o + ,.wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|> o + ,.rd_weight_bdma (reg2dp_rd_weight_bdma[7:0]) //|> o + ,.rd_weight_cdp (reg2dp_rd_weight_cdp[7:0]) //|> o + ,.rd_weight_pdp (reg2dp_rd_weight_pdp[7:0]) //|> o + ,.rd_weight_sdp (reg2dp_rd_weight_sdp[7:0]) //|> o + ,.rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0]) //|> o + ,.rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0]) //|> o + ,.rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0]) //|> o + ,.rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0]) //|> o + ,.rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0]) //|> o + ,.rd_weight_rbk (reg2dp_rd_weight_rbk[7:0]) //|> o + ,.rd_weight_rsv_0 (reg2dp_rd_weight_rsv_0[7:0]) //|> o + ,.rd_weight_rsv_1 (reg2dp_rd_weight_rsv_1[7:0]) //|> o + ,.wr_weight_bdma (reg2dp_wr_weight_bdma[7:0]) //|> o + ,.wr_weight_cdp (reg2dp_wr_weight_cdp[7:0]) //|> o + ,.wr_weight_pdp (reg2dp_wr_weight_pdp[7:0]) //|> o + ,.wr_weight_sdp (reg2dp_wr_weight_sdp[7:0]) //|> o + ,.wr_weight_rbk (reg2dp_wr_weight_rbk[7:0]) //|> o + ,.wr_weight_rsv_0 (reg2dp_wr_weight_rsv_0[7:0]) //|> o + ,.wr_weight_rsv_1 (reg2dp_wr_weight_rsv_1[7:0]) //|> o + ,.wr_weight_rsv_2 (reg2dp_wr_weight_rsv_2[7:0]) //|> o + ,.idle (dp2reg_idle) //|< i + ); +endmodule // NV_NVDLA_MCIF_csb diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v new file mode 100644 index 0000000..069bfd8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v @@ -0,0 +1,679 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_arb ( + arb2spt_req_ready //|< i + ,arb2spt_req_valid + ,arb2spt_req_pd + ,nvdla_core_clk + ,nvdla_core_rstn +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:print(",bpt2arb_req${i}_pd\n"); +//:print(",bpt2arb_req${i}_valid\n"); +//:print(",bpt2arb_req${i}_ready\n"); +//:print(",client${i}2mcif_rd_wt\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +,bpt2arb_req0_pd +,bpt2arb_req0_valid +,bpt2arb_req0_ready +,client02mcif_rd_wt +,bpt2arb_req1_pd +,bpt2arb_req1_valid +,bpt2arb_req1_ready +,client12mcif_rd_wt +,bpt2arb_req2_pd +,bpt2arb_req2_valid +,bpt2arb_req2_ready +,client22mcif_rd_wt +,bpt2arb_req3_pd +,bpt2arb_req3_valid +,bpt2arb_req3_ready +,client32mcif_rd_wt +,bpt2arb_req4_pd +,bpt2arb_req4_valid +,bpt2arb_req4_ready +,client42mcif_rd_wt +,bpt2arb_req5_pd +,bpt2arb_req5_valid +,bpt2arb_req5_ready +,client52mcif_rd_wt +,bpt2arb_req6_pd +,bpt2arb_req6_valid +,bpt2arb_req6_ready +,client62mcif_rd_wt + +//| eperl: generated_end (DO NOT EDIT ABOVE) +); +input nvdla_core_clk; +input nvdla_core_rstn; +input arb2spt_req_ready; +output arb2spt_req_valid; +output [32 +10:0] arb2spt_req_pd; +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:print("input bpt2arb_req${i}_valid;\n"); +//:print("output bpt2arb_req${i}_ready;\n"); +//:print qq( +//:input [32 +10:0] bpt2arb_req${i}_pd; +//:); +//:print("input [7:0] client${i}2mcif_rd_wt;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +input bpt2arb_req0_valid; +output bpt2arb_req0_ready; + +input [32 +10:0] bpt2arb_req0_pd; +input [7:0] client02mcif_rd_wt; +input bpt2arb_req1_valid; +output bpt2arb_req1_ready; + +input [32 +10:0] bpt2arb_req1_pd; +input [7:0] client12mcif_rd_wt; +input bpt2arb_req2_valid; +output bpt2arb_req2_ready; + +input [32 +10:0] bpt2arb_req2_pd; +input [7:0] client22mcif_rd_wt; +input bpt2arb_req3_valid; +output bpt2arb_req3_ready; + +input [32 +10:0] bpt2arb_req3_pd; +input [7:0] client32mcif_rd_wt; +input bpt2arb_req4_valid; +output bpt2arb_req4_ready; + +input [32 +10:0] bpt2arb_req4_pd; +input [7:0] client42mcif_rd_wt; +input bpt2arb_req5_valid; +output bpt2arb_req5_ready; + +input [32 +10:0] bpt2arb_req5_pd; +input [7:0] client52mcif_rd_wt; +input bpt2arb_req6_valid; +output bpt2arb_req6_ready; + +input [32 +10:0] bpt2arb_req6_pd; +input [7:0] client62mcif_rd_wt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [32 +10:0] arb_pd; +wire [7 -1:0] arb_gnt; +wire gnt_busy; +//:my $k=7; +//:my $i; +//:my $w=eval(32 +10); +//:for ($i=0;$i<$k;$i++) { +//:print("wire src${i}_req;\n"); +//:print("wire src${i}_gnt;\n"); +//:print("wire [7:0] wt${i};\n"); +//: print("wire [$w:0] arb_src${i}_pd;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire src0_req; +wire src0_gnt; +wire [7:0] wt0; +wire [42:0] arb_src0_pd; +wire src1_req; +wire src1_gnt; +wire [7:0] wt1; +wire [42:0] arb_src1_pd; +wire src2_req; +wire src2_gnt; +wire [7:0] wt2; +wire [42:0] arb_src2_pd; +wire src3_req; +wire src3_gnt; +wire [7:0] wt3; +wire [42:0] arb_src3_pd; +wire src4_req; +wire src4_gnt; +wire [7:0] wt4; +wire [42:0] arb_src4_pd; +wire src5_req; +wire src5_gnt; +wire [7:0] wt5; +wire [42:0] arb_src5_pd; +wire src6_req; +wire src6_gnt; +wire [7:0] wt6; +wire [42:0] arb_src6_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// +//:my $k=7; +//:my $i; +//:my $w=eval(32 +10); +//:for ($i=7;$i<16;$i++) { +//: print("wire [$w:0] arb_src${i}_pd;\n"); +//: print("wire src${i}_req;\n"); +//: print("wire src${i}_gnt;\n"); +//:} +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:my $wid = 32 +11; +//:print qq( +//:wire arb_src${i}_rdy, arb_src${i}_vld; +//:NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_${i} ( +//: .nvdla_core_clk(nvdla_core_clk) +//: ,.nvdla_core_rstn(nvdla_core_rstn) +//: ,.arb_src0_rdy(arb_src${i}_rdy) +//: ,.bpt2arb_req0_pd(bpt2arb_req${i}_pd) +//: ,.bpt2arb_req0_valid(bpt2arb_req${i}_valid) +//: ,.arb_src0_pd(arb_src${i}_pd) +//: ,.arb_src0_vld(arb_src${i}_vld) +//: ,.bpt2arb_req0_ready(bpt2arb_req${i}_ready) +//:); +//:); +//:print qq( +//: assign src${i}_req = arb_src${i}_vld; +//: assign arb_src${i}_rdy = src${i}_gnt; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [42:0] arb_src7_pd; +wire src7_req; +wire src7_gnt; +wire [42:0] arb_src8_pd; +wire src8_req; +wire src8_gnt; +wire [42:0] arb_src9_pd; +wire src9_req; +wire src9_gnt; +wire [42:0] arb_src10_pd; +wire src10_req; +wire src10_gnt; +wire [42:0] arb_src11_pd; +wire src11_req; +wire src11_gnt; +wire [42:0] arb_src12_pd; +wire src12_req; +wire src12_gnt; +wire [42:0] arb_src13_pd; +wire src13_req; +wire src13_gnt; +wire [42:0] arb_src14_pd; +wire src14_req; +wire src14_gnt; +wire [42:0] arb_src15_pd; +wire src15_req; +wire src15_gnt; + +wire arb_src0_rdy, arb_src0_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src0_rdy) +,.bpt2arb_req0_pd(bpt2arb_req0_pd) +,.bpt2arb_req0_valid(bpt2arb_req0_valid) +,.arb_src0_pd(arb_src0_pd) +,.arb_src0_vld(arb_src0_vld) +,.bpt2arb_req0_ready(bpt2arb_req0_ready) +); + +assign src0_req = arb_src0_vld; +assign arb_src0_rdy = src0_gnt; + +wire arb_src1_rdy, arb_src1_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src1_rdy) +,.bpt2arb_req0_pd(bpt2arb_req1_pd) +,.bpt2arb_req0_valid(bpt2arb_req1_valid) +,.arb_src0_pd(arb_src1_pd) +,.arb_src0_vld(arb_src1_vld) +,.bpt2arb_req0_ready(bpt2arb_req1_ready) +); + +assign src1_req = arb_src1_vld; +assign arb_src1_rdy = src1_gnt; + +wire arb_src2_rdy, arb_src2_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_2 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src2_rdy) +,.bpt2arb_req0_pd(bpt2arb_req2_pd) +,.bpt2arb_req0_valid(bpt2arb_req2_valid) +,.arb_src0_pd(arb_src2_pd) +,.arb_src0_vld(arb_src2_vld) +,.bpt2arb_req0_ready(bpt2arb_req2_ready) +); + +assign src2_req = arb_src2_vld; +assign arb_src2_rdy = src2_gnt; + +wire arb_src3_rdy, arb_src3_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_3 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src3_rdy) +,.bpt2arb_req0_pd(bpt2arb_req3_pd) +,.bpt2arb_req0_valid(bpt2arb_req3_valid) +,.arb_src0_pd(arb_src3_pd) +,.arb_src0_vld(arb_src3_vld) +,.bpt2arb_req0_ready(bpt2arb_req3_ready) +); + +assign src3_req = arb_src3_vld; +assign arb_src3_rdy = src3_gnt; + +wire arb_src4_rdy, arb_src4_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_4 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src4_rdy) +,.bpt2arb_req0_pd(bpt2arb_req4_pd) +,.bpt2arb_req0_valid(bpt2arb_req4_valid) +,.arb_src0_pd(arb_src4_pd) +,.arb_src0_vld(arb_src4_vld) +,.bpt2arb_req0_ready(bpt2arb_req4_ready) +); + +assign src4_req = arb_src4_vld; +assign arb_src4_rdy = src4_gnt; + +wire arb_src5_rdy, arb_src5_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_5 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src5_rdy) +,.bpt2arb_req0_pd(bpt2arb_req5_pd) +,.bpt2arb_req0_valid(bpt2arb_req5_valid) +,.arb_src0_pd(arb_src5_pd) +,.arb_src0_vld(arb_src5_vld) +,.bpt2arb_req0_ready(bpt2arb_req5_ready) +); + +assign src5_req = arb_src5_vld; +assign arb_src5_rdy = src5_gnt; + +wire arb_src6_rdy, arb_src6_vld; +NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_6 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.arb_src0_rdy(arb_src6_rdy) +,.bpt2arb_req0_pd(bpt2arb_req6_pd) +,.bpt2arb_req0_valid(bpt2arb_req6_valid) +,.arb_src0_pd(arb_src6_pd) +,.arb_src0_vld(arb_src6_vld) +,.bpt2arb_req0_ready(bpt2arb_req6_ready) +); + +assign src6_req = arb_src6_vld; +assign arb_src6_rdy = src6_gnt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//&eperl::pipe("-is -wid 75 -do arb_src${i}_pd -vo arb_src${i}_vld -ri bpt2arb_req${i}_ready -di bpt2arb_req${i}_pd -vi bpt2arb_req${i}_valid -ro arc_src${i}_rdy"); +//:my $k=7; +//:my $i; +//:for($i=7;$i<10;$i++) { +//: print("assign src${i}_req = 1'b0;\n"); +//: print("wire [7:0] wt${i} = 0;\n"); +//:} +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:print("assign wt${i} = client${i}2mcif_rd_wt;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign src7_req = 1'b0; +wire [7:0] wt7 = 0; +assign src8_req = 1'b0; +wire [7:0] wt8 = 0; +assign src9_req = 1'b0; +wire [7:0] wt9 = 0; +assign wt0 = client02mcif_rd_wt; +assign wt1 = client12mcif_rd_wt; +assign wt2 = client22mcif_rd_wt; +assign wt3 = client32mcif_rd_wt; +assign wt4 = client42mcif_rd_wt; +assign wt5 = client52mcif_rd_wt; +assign wt6 = client62mcif_rd_wt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +read_ig_arb u_read_ig_arb ( + .req0 (src0_req) //|< w + ,.req1 (src1_req) //|< w + ,.req2 (src2_req) //|< w + ,.req3 (src3_req) //|< w + ,.req4 (src4_req) //|< w + ,.req5 (src5_req) //|< w + ,.req6 (src6_req) //|< w + ,.req7 (src7_req) //|< w + ,.req8 (src8_req) //|< w + ,.req9 (src9_req) //|< w +//,.req10 (src10_req) //|< w +//,.req11 (src11_req) //|< w +//,.req12 (src12_req) //|< w +//,.req13 (src13_req) //|< w +//,.req14 (src14_req) //|< w +//,.req15 (src15_req) //|< w + ,.wt0 (wt0[7:0]) //|< w + ,.wt1 (wt1[7:0]) //|< w + ,.wt2 (wt2[7:0]) //|< w + ,.wt3 (wt3[7:0]) //|< w + ,.wt4 (wt4[7:0]) //|< w + ,.wt5 (wt5[7:0]) //|< w + ,.wt6 (wt6[7:0]) //|< w + ,.wt7 (wt7[7:0]) //|< w + ,.wt8 (wt8[7:0]) //|< w + ,.wt9 (wt9[7:0]) //|< w +//,.wt10 (wt10[7:0]) //|< w +//,.wt11 (wt11[7:0]) //|< w +//,.wt12 (wt12[7:0]) //|< w +//,.wt13 (wt13[7:0]) //|< w +//,.wt14 (wt14[7:0]) //|< w +//,.wt15 (wt15[7:0]) //|< w + ,.gnt_busy (gnt_busy) //|< w + ,.clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.gnt0 (src0_gnt) //|> w + ,.gnt1 (src1_gnt) //|> w + ,.gnt2 (src2_gnt) //|> w + ,.gnt3 (src3_gnt) //|> w + ,.gnt4 (src4_gnt) //|> w + ,.gnt5 (src5_gnt) //|> w + ,.gnt6 (src6_gnt) //|> w + ,.gnt7 (src7_gnt) //|> w + ,.gnt8 (src8_gnt) //|> w + ,.gnt9 (src9_gnt) //|> w +//,.gnt10 (src10_gnt) //|> w +//,.gnt11 (src11_gnt) //|> w +//,.gnt12 (src12_gnt) //|> w +//,.gnt13 (src13_gnt) //|> w +//,.gnt14 (src14_gnt) //|> w +//,.gnt15 (src15_gnt) //|> w + ); +// MUX OUT +always @( + src0_gnt + or arb_src0_pd + or src1_gnt + or arb_src1_pd + or src2_gnt + or arb_src2_pd + or src3_gnt + or arb_src3_pd + or src4_gnt + or arb_src4_pd + or src5_gnt + or arb_src5_pd + or src6_gnt + or arb_src6_pd +//or src7_gnt +//or arb_src7_pd +//or src8_gnt +//or arb_src8_pd +//or src9_gnt +//or arb_src9_pd +//or src10_gnt +//or arb_src10_pd +//or src11_gnt +//or arb_src11_pd +//or src12_gnt +//or arb_src12_pd +//or src13_gnt +//or arb_src13_pd +//or src14_gnt +//or arb_src14_pd +//or src15_gnt +//or arb_src15_pd + ) begin +//spyglass disable_block W171 W226 + case (1'b1 ) + src0_gnt: arb_pd = arb_src0_pd; + src1_gnt: arb_pd = arb_src1_pd; + src2_gnt: arb_pd = arb_src2_pd; + src3_gnt: arb_pd = arb_src3_pd; + src4_gnt: arb_pd = arb_src4_pd; + src5_gnt: arb_pd = arb_src5_pd; + src6_gnt: arb_pd = arb_src6_pd; +//src7_gnt: arb_pd = arb_src7_pd; +//src8_gnt: arb_pd = arb_src8_pd; +//src9_gnt: arb_pd = arb_src9_pd; +//src10_gnt: arb_pd = arb_src10_pd; +//src11_gnt: arb_pd = arb_src11_pd; +//src12_gnt: arb_pd = arb_src12_pd; +//src13_gnt: arb_pd = arb_src13_pd; +//src14_gnt: arb_pd = arb_src14_pd; +//src15_gnt: arb_pd = arb_src15_pd; +//VCS coverage off + default : begin + arb_pd[32 +10:0] = {32 +11{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +assign arb_gnt = {/*src15_gnt, src14_gnt, src13_gnt, src12_gnt, src11_gnt, src10_gnt, src9_gnt, src8_gnt, src7_gnt,*/ src6_gnt, src5_gnt, src4_gnt, src3_gnt, src2_gnt, src1_gnt, src0_gnt}; +assign arb2spt_req_valid = |arb_gnt; +assign gnt_busy = !arb2spt_req_ready; +assign arb2spt_req_pd = arb_pd; +//========================================== +// OBS +//assign obs_bus_mcif_read_ig_arb_gnt_busy = gnt_busy; +endmodule +module NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,arb_src0_rdy + ,bpt2arb_req0_pd + ,bpt2arb_req0_valid + ,arb_src0_pd + ,arb_src0_vld + ,bpt2arb_req0_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input arb_src0_rdy; +input [32 +10:0] bpt2arb_req0_pd; +input bpt2arb_req0_valid; +output [32 +10:0] arb_src0_pd; +output arb_src0_vld; +output bpt2arb_req0_ready; +reg [32 +10:0] arb_src0_pd; +reg arb_src0_vld; +reg bpt2arb_req0_ready; +reg [32 +10:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [32 +10:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32 +10:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? bpt2arb_req0_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && bpt2arb_req0_valid)? bpt2arb_req0_pd[32 +10:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + bpt2arb_req0_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or arb_src0_rdy + or p1_pipe_skid_data + ) begin + arb_src0_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = arb_src0_rdy; + arb_src0_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (arb_src0_vld^arb_src0_rdy^bpt2arb_req0_valid^bpt2arb_req0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (bpt2arb_req0_valid && !bpt2arb_req0_ready), (bpt2arb_req0_valid), (bpt2arb_req0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v.vcp new file mode 100644 index 0000000..334c165 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v.vcp @@ -0,0 +1,428 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_arb ( + arb2spt_req_ready //|< i + ,arb2spt_req_valid + ,arb2spt_req_pd + ,nvdla_core_clk + ,nvdla_core_rstn +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:print(",bpt2arb_req${i}_pd\n"); +//:print(",bpt2arb_req${i}_valid\n"); +//:print(",bpt2arb_req${i}_ready\n"); +//:print(",client${i}2mcif_rd_wt\n"); +//:} +); +input nvdla_core_clk; +input nvdla_core_rstn; +input arb2spt_req_ready; +output arb2spt_req_valid; +output [32 +10:0] arb2spt_req_pd; +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:print("input bpt2arb_req${i}_valid;\n"); +//:print("output bpt2arb_req${i}_ready;\n"); +//:print qq( +//:input [32 +10:0] bpt2arb_req${i}_pd; +//:); +//:print("input [7:0] client${i}2mcif_rd_wt;\n"); +//:} +reg [32 +10:0] arb_pd; +wire [7 -1:0] arb_gnt; +wire gnt_busy; +//:my $k=7; +//:my $i; +//:my $w=eval(32 +10); +//:for ($i=0;$i<$k;$i++) { +//:print("wire src${i}_req;\n"); +//:print("wire src${i}_gnt;\n"); +//:print("wire [7:0] wt${i};\n"); +//: print("wire [$w:0] arb_src${i}_pd;\n"); +//:} +// +//:my $k=7; +//:my $i; +//:my $w=eval(32 +10); +//:for ($i=7;$i<16;$i++) { +//: print("wire [$w:0] arb_src${i}_pd;\n"); +//: print("wire src${i}_req;\n"); +//: print("wire src${i}_gnt;\n"); +//:} +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:my $wid = 32 +11; +//:print qq( +//:wire arb_src${i}_rdy, arb_src${i}_vld; +//:NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 pipe_p1_${i} ( +//: .nvdla_core_clk(nvdla_core_clk) +//: ,.nvdla_core_rstn(nvdla_core_rstn) +//: ,.arb_src0_rdy(arb_src${i}_rdy) +//: ,.bpt2arb_req0_pd(bpt2arb_req${i}_pd) +//: ,.bpt2arb_req0_valid(bpt2arb_req${i}_valid) +//: ,.arb_src0_pd(arb_src${i}_pd) +//: ,.arb_src0_vld(arb_src${i}_vld) +//: ,.bpt2arb_req0_ready(bpt2arb_req${i}_ready) +//:); +//:); +//:print qq( +//: assign src${i}_req = arb_src${i}_vld; +//: assign arb_src${i}_rdy = src${i}_gnt; +//:); +//:} +//&eperl::pipe("-is -wid 75 -do arb_src${i}_pd -vo arb_src${i}_vld -ri bpt2arb_req${i}_ready -di bpt2arb_req${i}_pd -vi bpt2arb_req${i}_valid -ro arc_src${i}_rdy"); +//:my $k=7; +//:my $i; +//:for($i=7;$i<10;$i++) { +//: print("assign src${i}_req = 1'b0;\n"); +//: print("wire [7:0] wt${i} = 0;\n"); +//:} +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//:print("assign wt${i} = client${i}2mcif_rd_wt;\n"); +//:} +read_ig_arb u_read_ig_arb ( + .req0 (src0_req) //|< w + ,.req1 (src1_req) //|< w + ,.req2 (src2_req) //|< w + ,.req3 (src3_req) //|< w + ,.req4 (src4_req) //|< w + ,.req5 (src5_req) //|< w + ,.req6 (src6_req) //|< w + ,.req7 (src7_req) //|< w + ,.req8 (src8_req) //|< w + ,.req9 (src9_req) //|< w +//,.req10 (src10_req) //|< w +//,.req11 (src11_req) //|< w +//,.req12 (src12_req) //|< w +//,.req13 (src13_req) //|< w +//,.req14 (src14_req) //|< w +//,.req15 (src15_req) //|< w + ,.wt0 (wt0[7:0]) //|< w + ,.wt1 (wt1[7:0]) //|< w + ,.wt2 (wt2[7:0]) //|< w + ,.wt3 (wt3[7:0]) //|< w + ,.wt4 (wt4[7:0]) //|< w + ,.wt5 (wt5[7:0]) //|< w + ,.wt6 (wt6[7:0]) //|< w + ,.wt7 (wt7[7:0]) //|< w + ,.wt8 (wt8[7:0]) //|< w + ,.wt9 (wt9[7:0]) //|< w +//,.wt10 (wt10[7:0]) //|< w +//,.wt11 (wt11[7:0]) //|< w +//,.wt12 (wt12[7:0]) //|< w +//,.wt13 (wt13[7:0]) //|< w +//,.wt14 (wt14[7:0]) //|< w +//,.wt15 (wt15[7:0]) //|< w + ,.gnt_busy (gnt_busy) //|< w + ,.clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.gnt0 (src0_gnt) //|> w + ,.gnt1 (src1_gnt) //|> w + ,.gnt2 (src2_gnt) //|> w + ,.gnt3 (src3_gnt) //|> w + ,.gnt4 (src4_gnt) //|> w + ,.gnt5 (src5_gnt) //|> w + ,.gnt6 (src6_gnt) //|> w + ,.gnt7 (src7_gnt) //|> w + ,.gnt8 (src8_gnt) //|> w + ,.gnt9 (src9_gnt) //|> w +//,.gnt10 (src10_gnt) //|> w +//,.gnt11 (src11_gnt) //|> w +//,.gnt12 (src12_gnt) //|> w +//,.gnt13 (src13_gnt) //|> w +//,.gnt14 (src14_gnt) //|> w +//,.gnt15 (src15_gnt) //|> w + ); +// MUX OUT +always @( + src0_gnt + or arb_src0_pd + or src1_gnt + or arb_src1_pd + or src2_gnt + or arb_src2_pd + or src3_gnt + or arb_src3_pd + or src4_gnt + or arb_src4_pd + or src5_gnt + or arb_src5_pd + or src6_gnt + or arb_src6_pd +//or src7_gnt +//or arb_src7_pd +//or src8_gnt +//or arb_src8_pd +//or src9_gnt +//or arb_src9_pd +//or src10_gnt +//or arb_src10_pd +//or src11_gnt +//or arb_src11_pd +//or src12_gnt +//or arb_src12_pd +//or src13_gnt +//or arb_src13_pd +//or src14_gnt +//or arb_src14_pd +//or src15_gnt +//or arb_src15_pd + ) begin +//spyglass disable_block W171 W226 + case (1'b1 ) + src0_gnt: arb_pd = arb_src0_pd; + src1_gnt: arb_pd = arb_src1_pd; + src2_gnt: arb_pd = arb_src2_pd; + src3_gnt: arb_pd = arb_src3_pd; + src4_gnt: arb_pd = arb_src4_pd; + src5_gnt: arb_pd = arb_src5_pd; + src6_gnt: arb_pd = arb_src6_pd; +//src7_gnt: arb_pd = arb_src7_pd; +//src8_gnt: arb_pd = arb_src8_pd; +//src9_gnt: arb_pd = arb_src9_pd; +//src10_gnt: arb_pd = arb_src10_pd; +//src11_gnt: arb_pd = arb_src11_pd; +//src12_gnt: arb_pd = arb_src12_pd; +//src13_gnt: arb_pd = arb_src13_pd; +//src14_gnt: arb_pd = arb_src14_pd; +//src15_gnt: arb_pd = arb_src15_pd; +//VCS coverage off + default : begin + arb_pd[32 +10:0] = {32 +11{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +assign arb_gnt = {/*src15_gnt, src14_gnt, src13_gnt, src12_gnt, src11_gnt, src10_gnt, src9_gnt, src8_gnt, src7_gnt,*/ src6_gnt, src5_gnt, src4_gnt, src3_gnt, src2_gnt, src1_gnt, src0_gnt}; +assign arb2spt_req_valid = |arb_gnt; +assign gnt_busy = !arb2spt_req_ready; +assign arb2spt_req_pd = arb_pd; +//========================================== +// OBS +//assign obs_bus_mcif_read_ig_arb_gnt_busy = gnt_busy; +endmodule +module NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,arb_src0_rdy + ,bpt2arb_req0_pd + ,bpt2arb_req0_valid + ,arb_src0_pd + ,arb_src0_vld + ,bpt2arb_req0_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input arb_src0_rdy; +input [32 +10:0] bpt2arb_req0_pd; +input bpt2arb_req0_valid; +output [32 +10:0] arb_src0_pd; +output arb_src0_vld; +output bpt2arb_req0_ready; +reg [32 +10:0] arb_src0_pd; +reg arb_src0_vld; +reg bpt2arb_req0_ready; +reg [32 +10:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [32 +10:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32 +10:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? bpt2arb_req0_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && bpt2arb_req0_valid)? bpt2arb_req0_pd[32 +10:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + bpt2arb_req0_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or arb_src0_rdy + or p1_pipe_skid_data + ) begin + arb_src0_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = arb_src0_rdy; + arb_src0_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (arb_src0_vld^arb_src0_rdy^bpt2arb_req0_valid^bpt2arb_req0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (bpt2arb_req0_valid && !bpt2arb_req0_ready), (bpt2arb_req0_valid), (bpt2arb_req0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v new file mode 100644 index 0000000..72bf28b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v @@ -0,0 +1,1252 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_bpt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,bpt2arb_req_ready //|< i + ,dma2bpt_cdt_lat_fifo_pop //|< i + ,dma2bpt_req_pd //|< i + ,dma2bpt_req_valid //|< i + ,tieoff_axid //|< i + ,tieoff_lat_fifo_depth //|< i + ,bpt2arb_req_pd //|> o + ,bpt2arb_req_valid //|> o + ,dma2bpt_req_ready //|> o + ); +// +// NV_NVDLA_NOCIF_DRAM_READ_IG_bpt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input dma2bpt_req_valid; /* data valid */ +output dma2bpt_req_ready; /* data return handshake */ +input [32 +14:0] dma2bpt_req_pd; +input dma2bpt_cdt_lat_fifo_pop; +output bpt2arb_req_valid; /* data valid */ +input bpt2arb_req_ready; /* data return handshake */ +output [32 +10:0] bpt2arb_req_pd; +input [3:0] tieoff_axid; +input [7:0] tieoff_lat_fifo_depth; +reg [15:0] count_req; +reg lat_adv; +reg [7:0] lat_cnt_cur; +reg [9:0] lat_cnt_ext; +reg [9:0] lat_cnt_mod; +reg [9:0] lat_cnt_new; +reg [9:0] lat_cnt_nxt; +reg [7:0] lat_count_cnt; +reg [0:0] lat_count_dec; +reg [32 -1:0] out_addr; +wire [2:0] out_size; +reg [15:0] req_num; +wire [2:0] slot_needed; +wire [1:0] beat_size_NC; +wire bpt2arb_accept; +wire [32 -1:0] bpt2arb_addr; +wire [3:0] bpt2arb_axid; +wire bpt2arb_ftran; +wire bpt2arb_ltran; +wire bpt2arb_odd; +wire [2:0] bpt2arb_size; +wire bpt2arb_swizzle; +wire [2:0] end_offset; +wire [3:0] ftran_num; +wire [2:0] ftran_size; +wire [32 -1:0] in_addr; +wire [32 +14:0] in_pd; +wire [32 +14:0] in_pd_p; +wire in_rdy; +wire in_rdy_p; +wire [14:0] in_size; +wire in_vld; +wire in_vld_p; +wire [32 +14:0] in_vld_pd; +wire is_ftran; +wire is_ltran; +wire is_mtran; +wire is_single_tran; +wire [2:0] lat_count_inc; +wire [7:0] lat_fifo_free_slot; +wire lat_fifo_stall_enable; +wire [3:0] ltran_num; +wire [2:0] ltran_size; +wire mon_end_offset_c; +wire mon_lat_fifo_free_slot_c; +wire mon_out_beats_c; +wire [14:0] mtran_num; +wire out_inc; +wire out_odd; +wire out_swizzle; +wire req_enable; +wire req_rdy; +wire req_vld; +wire [2:0] size_offset; +wire [2:0] stt_offset; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma2bpt_req_pd (dma2bpt_req_pd[32 +14:0]) //|< i + ,.dma2bpt_req_valid (dma2bpt_req_valid) //|< i + ,.dma2bpt_req_ready (dma2bpt_req_ready) //|> o + ,.in_pd_p (in_pd_p[32 +14:0]) //|> w + ,.in_vld_p (in_vld_p) //|> w + ,.in_rdy_p (in_rdy_p) //|< w + ); +NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.in_pd_p (in_pd_p[32 +14:0]) //|< w + ,.in_vld_p (in_vld_p) //|< w + ,.in_rdy_p (in_rdy_p) //|> w + ,.in_pd (in_pd[32 +14:0]) //|> w + ,.in_vld (in_vld) //|> w + ,.in_rdy (in_rdy) //|< w + ); +assign in_rdy = req_rdy & is_ltran; +assign in_vld_pd = {(32 +15){in_vld}} & in_pd; +// PKT_UNPACK_WIRE( dma_read_cmd , in_ , in_vld_pd ) +assign in_addr[32 -1:0] = in_vld_pd[32 -1:0]; +assign in_size[14:0] = in_vld_pd[32 +14:32]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + wire cond_zzz_assert_always_1x = (in_addr[4:0] == 0); + nv_assert_always #(0,0,"lower 5 LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//================ +// check the empty entry of lat.fifo +//================ +//dma2bpt_cdt_lat_fifo_pop +assign slot_needed = 1; +/*always @( + is_single_tran + or out_size + or is_ltran + or out_swizzle + or is_ftran + ) begin + if (NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) begin + slot_needed = 1; + end + else if (is_single_tran) begin + slot_needed = (out_size>>1) + 1; + end else if (is_ltran) begin + slot_needed = ((out_size+out_swizzle)>>1) + 1; //spyglass disable SelfDeterminedExpr-ML + end else if (is_ftran) begin + slot_needed = (out_size+1)>>1; + end else begin + slot_needed = 3'd4; + end +end*/ +assign lat_fifo_stall_enable = (tieoff_lat_fifo_depth!=0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lat_count_dec <= 1'b0; + end else begin + lat_count_dec <= dma2bpt_cdt_lat_fifo_pop; + end +end +assign lat_count_inc = (bpt2arb_accept && lat_fifo_stall_enable ) ? slot_needed : 0; +//&Vector LAT_FIFO_MAX_BITS lat_count_cnt; +//&Always posedge; +// if (|lat_count_inc || lat_count_dec) begin +// lat_count_cnt <0= lat_count_cnt + lat_count_inc - lat_count_dec; +// end +//&End; +// lat adv logic +always @( + lat_count_inc + or lat_count_dec + ) begin + lat_adv = lat_count_inc[2:0] != {{2{1'b0}}, lat_count_dec[0:0]}; +end +// lat cnt logic +always @( + lat_cnt_cur + or lat_count_inc + or lat_count_dec + or lat_adv + ) begin +// VCS sop_coverage_off start + lat_cnt_ext[9:0] = {1'b0, 1'b0, lat_cnt_cur}; + lat_cnt_mod[9:0] = lat_cnt_cur + lat_count_inc[2:0] - lat_count_dec[0:0]; // spyglass disable W164b + lat_cnt_new[9:0] = (lat_adv)? lat_cnt_mod[9:0] : lat_cnt_ext[9:0]; + lat_cnt_nxt[9:0] = lat_cnt_new[9:0]; +// VCS sop_coverage_off end +end +// lat flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lat_cnt_cur[7:0] <= 0; + end else begin + lat_cnt_cur[7:0] <= lat_cnt_nxt[7:0]; + end +end +// lat output logic +always @( + lat_cnt_cur + ) begin + lat_count_cnt[7:0] = lat_cnt_cur[7:0]; +end +// lat asserts +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"never: counter underflow below ") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (lat_cnt_nxt < 0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign {mon_lat_fifo_free_slot_c,lat_fifo_free_slot[7:0]} = tieoff_lat_fifo_depth - lat_count_cnt; +assign req_enable = (!lat_fifo_stall_enable) || ({{5{1'b0}}, slot_needed} <= lat_fifo_free_slot); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"should not over flow") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_lat_fifo_free_slot_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//================ +// bsp out: swizzle +//================ +assign out_swizzle = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) ? 1'b0 : (stt_offset[0]==1'b1); +assign out_odd = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) ? 0 : (in_size[0]==1'b0); +assign out_size = 3'b0; +/* +//================ +// bsp out: size +//================ +always @( + is_ftran + or ftran_size + or is_mtran + or is_ltran + or ltran_size + ) begin + out_size = {3{`tick_x_or_0}}; + if (NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) begin + out_size = 0; + end + else if (is_ftran) begin + out_size = ftran_size; + end else if (is_mtran) begin + out_size = 3'd7; + end else if (is_ltran) begin + out_size = ltran_size; + end +end +*/ +//================ +// bpt2arb: addr +//================ +always @(posedge nvdla_core_clk) begin + if (bpt2arb_accept) begin +//if (is_ftran) begin +// //out_addr <= in_addr + ((ftran_size+1)<<(NVDLA_MEMORY_ATOMIC_LOG2)); +//if (3 == 3) +// out_addr <= in_addr + ((1)<<(3)); +// else +// out_addr <= in_addr + ((ftran_size+1)<<(3)); +//end else begin +// //out_addr <= out_addr + (8<<(NVDLA_MEMORY_ATOMIC_LOG2-1)); +//if (3 == 3) +// out_addr <= out_addr + (1<<(3)); +// else +// out_addr <= out_addr + (8<<(3 -1)); +//end + if (is_ftran) begin + out_addr <= in_addr + 8; + end else begin + out_addr <= out_addr + 8; + end + end +end +//================ +// tran count +//================ +always @( +//is_single_tran +//or mtran_num + * + ) begin +//if (3 == 3) + req_num = in_size + 1; +//else if (is_single_tran) begin +// req_num = 1; +//end else if (mtran_num==0) begin +// req_num = 2; +//end else begin +// req_num = 2 + mtran_num[14:3]; +//end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_req <= {15{1'b0}}; + end else begin + if (bpt2arb_accept) begin + if (is_ltran) begin + count_req <= 0; + end else begin + count_req <= count_req + 1; + end + end + end +end +assign is_ftran = (count_req==0); +assign is_mtran = (count_req>0 && count_req= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_pipe_rand_valid)? p1_pipe_rand_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_pipe_rand_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or in_rdy_p + or p1_pipe_skid_data + ) begin + in_vld_p = p1_pipe_skid_valid; + p1_pipe_skid_ready = in_rdy_p; + in_pd_p = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (in_vld_p^in_rdy_p^dma2bpt_req_valid^dma2bpt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (dma2bpt_req_valid && !dma2bpt_req_ready), (dma2bpt_req_valid), (dma2bpt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_READ_IG_BPT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is in_pd (in_vld,in_rdy) <= in_pd_p[32 +14:0] (in_vld_p,in_rdy_p) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,in_pd_p + ,in_rdy + ,in_vld_p + ,in_pd + ,in_rdy_p + ,in_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +14:0] in_pd_p; +input in_rdy; +input in_vld_p; +output [32 +14:0] in_pd; +output in_rdy_p; +output in_vld; +reg [32 +14:0] in_pd; +reg in_rdy_p; +reg in_vld; +reg [32 +14:0] p2_pipe_data; +reg [32 +14:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32 +14:0] p2_skid_data; +reg [32 +14:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + in_vld_p + or p2_pipe_rand_ready + or in_pd_p + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = in_vld_p; + in_rdy_p = p2_pipe_rand_ready; + p2_pipe_rand_data = in_pd_p[32 +14:0]; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : in_vld_p; + in_rdy_p = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : in_pd_p[32 +14:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or in_vld_p + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && in_vld_p === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) skid buffer +always @( + p2_pipe_rand_valid + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_rand_valid && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_rand_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_rand_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_rand_valid + or p2_skid_valid + or p2_pipe_rand_data + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? p2_pipe_rand_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or in_rdy + or p2_pipe_data + ) begin + in_vld = p2_pipe_valid; + p2_pipe_ready = in_rdy; + in_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (in_vld^in_rdy^in_vld_p^in_rdy_p)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (in_vld_p && !in_rdy_p), (in_vld_p), (in_rdy_p)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_READ_IG_BPT_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v.vcp new file mode 100644 index 0000000..72bf28b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v.vcp @@ -0,0 +1,1252 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_bpt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,bpt2arb_req_ready //|< i + ,dma2bpt_cdt_lat_fifo_pop //|< i + ,dma2bpt_req_pd //|< i + ,dma2bpt_req_valid //|< i + ,tieoff_axid //|< i + ,tieoff_lat_fifo_depth //|< i + ,bpt2arb_req_pd //|> o + ,bpt2arb_req_valid //|> o + ,dma2bpt_req_ready //|> o + ); +// +// NV_NVDLA_NOCIF_DRAM_READ_IG_bpt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input dma2bpt_req_valid; /* data valid */ +output dma2bpt_req_ready; /* data return handshake */ +input [32 +14:0] dma2bpt_req_pd; +input dma2bpt_cdt_lat_fifo_pop; +output bpt2arb_req_valid; /* data valid */ +input bpt2arb_req_ready; /* data return handshake */ +output [32 +10:0] bpt2arb_req_pd; +input [3:0] tieoff_axid; +input [7:0] tieoff_lat_fifo_depth; +reg [15:0] count_req; +reg lat_adv; +reg [7:0] lat_cnt_cur; +reg [9:0] lat_cnt_ext; +reg [9:0] lat_cnt_mod; +reg [9:0] lat_cnt_new; +reg [9:0] lat_cnt_nxt; +reg [7:0] lat_count_cnt; +reg [0:0] lat_count_dec; +reg [32 -1:0] out_addr; +wire [2:0] out_size; +reg [15:0] req_num; +wire [2:0] slot_needed; +wire [1:0] beat_size_NC; +wire bpt2arb_accept; +wire [32 -1:0] bpt2arb_addr; +wire [3:0] bpt2arb_axid; +wire bpt2arb_ftran; +wire bpt2arb_ltran; +wire bpt2arb_odd; +wire [2:0] bpt2arb_size; +wire bpt2arb_swizzle; +wire [2:0] end_offset; +wire [3:0] ftran_num; +wire [2:0] ftran_size; +wire [32 -1:0] in_addr; +wire [32 +14:0] in_pd; +wire [32 +14:0] in_pd_p; +wire in_rdy; +wire in_rdy_p; +wire [14:0] in_size; +wire in_vld; +wire in_vld_p; +wire [32 +14:0] in_vld_pd; +wire is_ftran; +wire is_ltran; +wire is_mtran; +wire is_single_tran; +wire [2:0] lat_count_inc; +wire [7:0] lat_fifo_free_slot; +wire lat_fifo_stall_enable; +wire [3:0] ltran_num; +wire [2:0] ltran_size; +wire mon_end_offset_c; +wire mon_lat_fifo_free_slot_c; +wire mon_out_beats_c; +wire [14:0] mtran_num; +wire out_inc; +wire out_odd; +wire out_swizzle; +wire req_enable; +wire req_rdy; +wire req_vld; +wire [2:0] size_offset; +wire [2:0] stt_offset; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma2bpt_req_pd (dma2bpt_req_pd[32 +14:0]) //|< i + ,.dma2bpt_req_valid (dma2bpt_req_valid) //|< i + ,.dma2bpt_req_ready (dma2bpt_req_ready) //|> o + ,.in_pd_p (in_pd_p[32 +14:0]) //|> w + ,.in_vld_p (in_vld_p) //|> w + ,.in_rdy_p (in_rdy_p) //|< w + ); +NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.in_pd_p (in_pd_p[32 +14:0]) //|< w + ,.in_vld_p (in_vld_p) //|< w + ,.in_rdy_p (in_rdy_p) //|> w + ,.in_pd (in_pd[32 +14:0]) //|> w + ,.in_vld (in_vld) //|> w + ,.in_rdy (in_rdy) //|< w + ); +assign in_rdy = req_rdy & is_ltran; +assign in_vld_pd = {(32 +15){in_vld}} & in_pd; +// PKT_UNPACK_WIRE( dma_read_cmd , in_ , in_vld_pd ) +assign in_addr[32 -1:0] = in_vld_pd[32 -1:0]; +assign in_size[14:0] = in_vld_pd[32 +14:32]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + wire cond_zzz_assert_always_1x = (in_addr[4:0] == 0); + nv_assert_always #(0,0,"lower 5 LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//================ +// check the empty entry of lat.fifo +//================ +//dma2bpt_cdt_lat_fifo_pop +assign slot_needed = 1; +/*always @( + is_single_tran + or out_size + or is_ltran + or out_swizzle + or is_ftran + ) begin + if (NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) begin + slot_needed = 1; + end + else if (is_single_tran) begin + slot_needed = (out_size>>1) + 1; + end else if (is_ltran) begin + slot_needed = ((out_size+out_swizzle)>>1) + 1; //spyglass disable SelfDeterminedExpr-ML + end else if (is_ftran) begin + slot_needed = (out_size+1)>>1; + end else begin + slot_needed = 3'd4; + end +end*/ +assign lat_fifo_stall_enable = (tieoff_lat_fifo_depth!=0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lat_count_dec <= 1'b0; + end else begin + lat_count_dec <= dma2bpt_cdt_lat_fifo_pop; + end +end +assign lat_count_inc = (bpt2arb_accept && lat_fifo_stall_enable ) ? slot_needed : 0; +//&Vector LAT_FIFO_MAX_BITS lat_count_cnt; +//&Always posedge; +// if (|lat_count_inc || lat_count_dec) begin +// lat_count_cnt <0= lat_count_cnt + lat_count_inc - lat_count_dec; +// end +//&End; +// lat adv logic +always @( + lat_count_inc + or lat_count_dec + ) begin + lat_adv = lat_count_inc[2:0] != {{2{1'b0}}, lat_count_dec[0:0]}; +end +// lat cnt logic +always @( + lat_cnt_cur + or lat_count_inc + or lat_count_dec + or lat_adv + ) begin +// VCS sop_coverage_off start + lat_cnt_ext[9:0] = {1'b0, 1'b0, lat_cnt_cur}; + lat_cnt_mod[9:0] = lat_cnt_cur + lat_count_inc[2:0] - lat_count_dec[0:0]; // spyglass disable W164b + lat_cnt_new[9:0] = (lat_adv)? lat_cnt_mod[9:0] : lat_cnt_ext[9:0]; + lat_cnt_nxt[9:0] = lat_cnt_new[9:0]; +// VCS sop_coverage_off end +end +// lat flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lat_cnt_cur[7:0] <= 0; + end else begin + lat_cnt_cur[7:0] <= lat_cnt_nxt[7:0]; + end +end +// lat output logic +always @( + lat_cnt_cur + ) begin + lat_count_cnt[7:0] = lat_cnt_cur[7:0]; +end +// lat asserts +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"never: counter underflow below ") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (lat_cnt_nxt < 0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign {mon_lat_fifo_free_slot_c,lat_fifo_free_slot[7:0]} = tieoff_lat_fifo_depth - lat_count_cnt; +assign req_enable = (!lat_fifo_stall_enable) || ({{5{1'b0}}, slot_needed} <= lat_fifo_free_slot); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"should not over flow") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_lat_fifo_free_slot_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//================ +// bsp out: swizzle +//================ +assign out_swizzle = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) ? 1'b0 : (stt_offset[0]==1'b1); +assign out_odd = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) ? 0 : (in_size[0]==1'b0); +assign out_size = 3'b0; +/* +//================ +// bsp out: size +//================ +always @( + is_ftran + or ftran_size + or is_mtran + or is_ltran + or ltran_size + ) begin + out_size = {3{`tick_x_or_0}}; + if (NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) begin + out_size = 0; + end + else if (is_ftran) begin + out_size = ftran_size; + end else if (is_mtran) begin + out_size = 3'd7; + end else if (is_ltran) begin + out_size = ltran_size; + end +end +*/ +//================ +// bpt2arb: addr +//================ +always @(posedge nvdla_core_clk) begin + if (bpt2arb_accept) begin +//if (is_ftran) begin +// //out_addr <= in_addr + ((ftran_size+1)<<(NVDLA_MEMORY_ATOMIC_LOG2)); +//if (3 == 3) +// out_addr <= in_addr + ((1)<<(3)); +// else +// out_addr <= in_addr + ((ftran_size+1)<<(3)); +//end else begin +// //out_addr <= out_addr + (8<<(NVDLA_MEMORY_ATOMIC_LOG2-1)); +//if (3 == 3) +// out_addr <= out_addr + (1<<(3)); +// else +// out_addr <= out_addr + (8<<(3 -1)); +//end + if (is_ftran) begin + out_addr <= in_addr + 8; + end else begin + out_addr <= out_addr + 8; + end + end +end +//================ +// tran count +//================ +always @( +//is_single_tran +//or mtran_num + * + ) begin +//if (3 == 3) + req_num = in_size + 1; +//else if (is_single_tran) begin +// req_num = 1; +//end else if (mtran_num==0) begin +// req_num = 2; +//end else begin +// req_num = 2 + mtran_num[14:3]; +//end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_req <= {15{1'b0}}; + end else begin + if (bpt2arb_accept) begin + if (is_ltran) begin + count_req <= 0; + end else begin + count_req <= count_req + 1; + end + end + end +end +assign is_ftran = (count_req==0); +assign is_mtran = (count_req>0 && count_req= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_pipe_rand_valid)? p1_pipe_rand_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_pipe_rand_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or in_rdy_p + or p1_pipe_skid_data + ) begin + in_vld_p = p1_pipe_skid_valid; + p1_pipe_skid_ready = in_rdy_p; + in_pd_p = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (in_vld_p^in_rdy_p^dma2bpt_req_valid^dma2bpt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (dma2bpt_req_valid && !dma2bpt_req_ready), (dma2bpt_req_valid), (dma2bpt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_READ_IG_BPT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is in_pd (in_vld,in_rdy) <= in_pd_p[32 +14:0] (in_vld_p,in_rdy_p) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,in_pd_p + ,in_rdy + ,in_vld_p + ,in_pd + ,in_rdy_p + ,in_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +14:0] in_pd_p; +input in_rdy; +input in_vld_p; +output [32 +14:0] in_pd; +output in_rdy_p; +output in_vld; +reg [32 +14:0] in_pd; +reg in_rdy_p; +reg in_vld; +reg [32 +14:0] p2_pipe_data; +reg [32 +14:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32 +14:0] p2_skid_data; +reg [32 +14:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + in_vld_p + or p2_pipe_rand_ready + or in_pd_p + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = in_vld_p; + in_rdy_p = p2_pipe_rand_ready; + p2_pipe_rand_data = in_pd_p[32 +14:0]; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : in_vld_p; + in_rdy_p = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : in_pd_p[32 +14:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_CVIF_READ_IG_bpt_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or in_vld_p + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && in_vld_p === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) skid buffer +always @( + p2_pipe_rand_valid + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_rand_valid && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_rand_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_rand_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_rand_valid + or p2_skid_valid + or p2_pipe_rand_data + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? p2_pipe_rand_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or in_rdy + or p2_pipe_data + ) begin + in_vld = p2_pipe_valid; + p2_pipe_ready = in_rdy; + in_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (in_vld^in_rdy^in_vld_p^in_rdy_p)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (in_vld_p && !in_rdy_p), (in_vld_p), (in_rdy_p)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_READ_IG_BPT_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v new file mode 100644 index 0000000..92a88c8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v @@ -0,0 +1,716 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_cvt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cq_wr_prdy //|< i + ,mcif2noc_axi_ar_arready //|< i + ,eg2ig_axi_vld //|< i + ,reg2dp_rd_os_cnt //|< i + ,spt2cvt_req_pd //|< i + ,spt2cvt_req_valid //|< i + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,cq_wr_thread_id //|> o + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o + ,spt2cvt_req_ready //|> o + ); +// +// NV_NVDLA_NOCIF_READ_IG_cvt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input spt2cvt_req_valid; /* data valid */ +output spt2cvt_req_ready; /* data return handshake */ +input [32 +10:0] spt2cvt_req_pd; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [6:0] cq_wr_pd; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +//&Ports /streamid/; //stepheng,remove +input [7:0] reg2dp_rd_os_cnt; +input eg2ig_axi_vld; +reg eg2ig_axi_vld_d; +reg os_adv; +reg [8:0] os_cnt; +reg [8:0] os_cnt_cur; +reg [10:0] os_cnt_ext; +reg [10:0] os_cnt_mod; +reg [10:0] os_cnt_new; +reg [10:0] os_cnt_nxt; +wire [32 -1:0] axi_addr; +wire [3:0] axi_axid; +wire [32 +5:0] axi_cmd_pd; +wire axi_cmd_rdy; +wire axi_cmd_vld; +wire [1:0] axi_len; +wire [7:0] cfg_rd_os_cnt; +wire [32 -1:0] cmd_addr; +wire [3:0] cmd_axid; +wire cmd_ftran; +wire cmd_ltran; +wire cmd_odd; +wire cmd_rdy; +wire [2:0] cmd_size; +wire cmd_swizzle; +wire cmd_vld; +wire end_addr_is_32_align; +wire [2:0] end_offset; +wire [1:0] end_offset_2_1_NC; +wire ig2cq_fdrop; +wire ig2cq_ldrop; +wire [1:0] ig2cq_lens; +wire ig2cq_ltran; +wire ig2cq_odd; +wire ig2cq_swizzle; +wire inc; +wire mon_axi_len_c; +wire mon_end_offset_c; +wire [32 -1:0] opipe_axi_addr; +wire [3:0] opipe_axi_axid; +wire [1:0] opipe_axi_len; +wire [32 +5:0] opipe_axi_pd; +wire opipe_axi_rdy; +wire opipe_axi_vld; +wire [2:0] os_cnt_add; +wire os_cnt_add_en; +wire os_cnt_cen; +wire os_cnt_full; +wire [0:0] os_cnt_sub; +wire os_cnt_sub_en; +wire [2:0] os_inp_add_nxt; +wire [9:0] os_inp_nxt; +wire [0:0] os_inp_sub_nxt; +wire [8:0] rd_os_cnt_ext; +wire stt_addr_is_32_align; +wire [2:0] stt_offset; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// IG===UNPACK +assign cmd_vld = spt2cvt_req_valid; +assign spt2cvt_req_ready = cmd_rdy; +// PKT_UNPACK_WIRE( cvt_read_cmd , cmd_ , spt2cvt_req_pd ) +assign cmd_axid[3:0] = spt2cvt_req_pd[3:0]; +assign cmd_addr[32 -1:0] = spt2cvt_req_pd[32 +3:4]; +assign cmd_size[2:0] = spt2cvt_req_pd[32 +6:32 +4]; +assign cmd_swizzle = spt2cvt_req_pd[32 +7]; +assign cmd_odd = spt2cvt_req_pd[32 +8]; +assign cmd_ltran = spt2cvt_req_pd[32 +9]; +assign cmd_ftran = spt2cvt_req_pd[32 +10]; +// IG===address calculation +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"5 bit of addr LSB should always be 0") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (|cmd_addr[4:0]== 1'b1 )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign stt_offset = cmd_addr[7:5]; // start position within a 256B block +assign stt_addr_is_32_align = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) ? 1'b0 : (stt_offset[0]== 1'b1 ); +assign {mon_end_offset_c,end_offset[2:0]} = stt_offset + cmd_size; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"end address should never cross 256B address boundary") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_end_offset_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign end_offset_2_1_NC = end_offset[2:1]; // only need end_offset bit0 to know end addr alignment +assign end_addr_is_32_align = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2)? 1'b0 : (end_offset[0]== 1'b0 ); +// IG===AXI Trans GEN +assign axi_axid = cmd_axid; +//assign axi_addr = cmd_addr & 40'hff_ffff_ffc0; // make [5:0]=0 +//assign axi_addr = cmd_addr & 64'hffff_ffff_ffff_ffc0; // stepheng, ake [5:0]=0 +reg [32 -1:0] axi_addr_i; +//:print qq( +//:always @(cmd_addr) begin +//: axi_addr_i = cmd_addr; +//: axi_addr_i[3 -1:0] = 0; +//:end +//: assign axi_addr = axi_addr_i; +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(cmd_addr) begin +axi_addr_i = cmd_addr; +axi_addr_i[3 -1:0] = 0; +end +assign axi_addr = axi_addr_i; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign axi_size = AXSIZE_64; //stepheng. remove +assign inc = cmd_ftran & cmd_ltran & (cmd_size[0]==1) & cmd_swizzle; +//assign {mon_axi_len_c, axi_len[1:0]} = cmd_size[2:1] + inc; +assign axi_len[1:0] = cmd_size[1:0]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"Should not be overflow") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_axi_len_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//assign axi_user_size = cmd_user_size; //stepheng,remove +//assign axi_streamid = falcon2mcif_streamid; //stepheng,remove. +// IG===Context Queue +// ( Upp,Low) 10 11 00 01 +// Count +// 0: F 1M L +// 1: F+1M F+L 2M 1M+L +// 2: F+2M F+1M+L 3M 2M+L +// 3: F+3M F+2M+L 4M 3M+L +assign cq_wr_pvld = cmd_vld & axi_cmd_rdy & !os_cnt_full; // inter-lock with opipe +assign ig2cq_lens = axi_len; +assign ig2cq_swizzle = cmd_swizzle; +assign ig2cq_ltran = cmd_ltran; +assign ig2cq_odd = cmd_odd; +assign ig2cq_fdrop = cmd_ftran & stt_addr_is_32_align; +assign ig2cq_ldrop = cmd_ltran & end_addr_is_32_align; +//assign cq_wr_pd = {ig2cq_cnt,ig2cq_upp,ig2cq_low}; +// PKT_PACK_WIRE( nocif_read_ig2eg , ig2cq_ , cq_wr_pd ) +assign cq_wr_pd[1:0] = ig2cq_lens[1:0]; +assign cq_wr_pd[2] = ig2cq_swizzle ; +assign cq_wr_pd[3] = ig2cq_odd ; +assign cq_wr_pd[4] = ig2cq_ltran ; +assign cq_wr_pd[5] = ig2cq_fdrop ; +assign cq_wr_pd[6] = ig2cq_ldrop ; +//:my $k = 7; +//:my $i; +//:my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//:my @client_id = (0,8,9,3,2,4,1,5,7,6,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:print qq(assign cq_wr_thread_id = ); +//:for ($i=0;$i<$k;$i++) { +//: print qq((cmd_axid == $remap_clientid[$i]) ? $i :); +//:} +//: print qq(0;); +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cq_wr_thread_id = (cmd_axid == 8) ? 0 :(cmd_axid == 9) ? 1 :(cmd_axid == 3) ? 2 :(cmd_axid == 2) ? 3 :(cmd_axid == 1) ? 4 :(cmd_axid == 5) ? 5 :(cmd_axid == 6) ? 6 :0; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign cq_wr_thread_id = cmd_axid; +// IG===AXI OUT PIPE +assign axi_cmd_vld = cmd_vld & cq_wr_prdy & !os_cnt_full; // inter-lock with context-queue +assign cmd_rdy = axi_cmd_rdy & cq_wr_prdy & !os_cnt_full; +assign os_inp_add_nxt[2:0] = cmd_vld ? (axi_len + 1) : 3'd0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg2ig_axi_vld_d <= 1'b0; + end else begin + eg2ig_axi_vld_d <= eg2ig_axi_vld; + end +end +assign os_inp_sub_nxt[0:0] = eg2ig_axi_vld_d ? 1'd1 : 1'd0; +assign os_inp_nxt[9:0] = os_cnt + os_inp_add_nxt - os_inp_sub_nxt; +// 256 outstanding trans +assign os_cnt_add_en = axi_cmd_vld & axi_cmd_rdy; +assign os_cnt_sub_en = eg2ig_axi_vld_d; +assign os_cnt_cen = os_cnt_add_en | os_cnt_sub_en; +assign os_cnt_add = os_cnt_add_en ? (axi_len + 1) : 3'd0; +assign os_cnt_sub = os_cnt_sub_en ? 1'd1 : 1'd0; +assign cfg_rd_os_cnt = reg2dp_rd_os_cnt[7:0]; +assign rd_os_cnt_ext = {{1{1'b0}}, cfg_rd_os_cnt}; +assign os_cnt_full = os_inp_nxt > (rd_os_cnt_ext + 1); +// os adv logic +always @( + os_cnt_add + or os_cnt_sub + ) begin + os_adv = os_cnt_add[2:0] != {{2{1'b0}}, os_cnt_sub[0:0]}; +end +// os cnt logic +always @( + os_cnt_cur + or os_cnt_add + or os_cnt_sub + or os_adv + ) begin +// VCS sop_coverage_off start + os_cnt_ext[10:0] = {1'b0, 1'b0, os_cnt_cur}; + os_cnt_mod[10:0] = os_cnt_cur + os_cnt_add[2:0] - os_cnt_sub[0:0]; // spyglass disable W164b + os_cnt_new[10:0] = (os_adv)? os_cnt_mod[10:0] : os_cnt_ext[10:0]; + os_cnt_nxt[10:0] = os_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// os flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + os_cnt_cur[8:0] <= 0; + end else begin + if (os_cnt_cen) begin + os_cnt_cur[8:0] <= os_cnt_nxt[8:0]; + end + end +end +// os output logic +always @( + os_cnt_cur + ) begin + os_cnt[8:0] = os_cnt_cur[8:0]; +end +// os asserts +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (os_cnt_nxt > 256 && os_cnt_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//stepheng. +NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.axi_cmd_pd (axi_cmd_pd[32 +5:0]) //|< w + ,.axi_cmd_vld (axi_cmd_vld) //|< w + ,.opipe_axi_rdy (opipe_axi_rdy) //|< w + ,.axi_cmd_rdy (axi_cmd_rdy) //|> w + ,.opipe_axi_pd (opipe_axi_pd[32 +5:0]) //|> w + ,.opipe_axi_vld (opipe_axi_vld) //|> w + ); +//my $w = eval(32 +6); +// &eperl::pipe("-is -wid $w -do opipe_axi_pd -vo opipe_axi_vld -ri axi_cmd_rdy -di axi_cmd_pd -vi axi_cmd_vld -ro opipe_axi_rdy"); +//stepheng,remove streamid & user_size & axi_size +assign axi_cmd_pd = {axi_axid,axi_addr,axi_len}; +assign {opipe_axi_axid,opipe_axi_addr,opipe_axi_len} = opipe_axi_pd; +// IG===AXI OUT ZERO EXT +assign mcif2noc_axi_ar_arid = {{4{1'b0}}, opipe_axi_axid}; +assign mcif2noc_axi_ar_araddr = opipe_axi_addr; +assign mcif2noc_axi_ar_arlen = {{2{1'b0}}, opipe_axi_len};//stepheng +//assign mcif2noc_axi_ar_arsize = opipe_axi_size; +//stepheng,remove +//// USER BITS +//&Always; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_ALL_BITS] = 0; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_StreamID_FIELD] = opipe_axi_streamid; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_user_size_FIELD] = opipe_axi_user_size; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_vpr_rd_FIELD] = USER_VPR_RD; // vpr_rd +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_rsb_ns_FIELD] = USER_RSB_NS; // rsb_ns +//&End; +//stepheng,remove tie off. +//// IG===AXI OUT TIEOFF +//assign mcif2noc_axi_ar_arburst = AXBURST; +//assign mcif2noc_axi_ar_arlock = AXLOCK; +//assign mcif2noc_axi_ar_arcache = AXCACHE; +//assign mcif2noc_axi_ar_arprot = AXPROT; +//assign mcif2noc_axi_ar_arqos = AXQOS; +//assign mcif2noc_axi_ar_arregion = AXREGION; +// IG===AXI OUT valid/ready +assign mcif2noc_axi_ar_arvalid = opipe_axi_vld; +assign opipe_axi_rdy = mcif2noc_axi_ar_arready; +//========================================== +// OBS +//assign obs_bus_mcif_read_ig_cvt_axi_cmd_rdy = axi_cmd_rdy; +//assign obs_bus_mcif_read_ig_cvt_axi_cmd_vld = axi_cmd_vld; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_fdrop = ig2cq_fdrop; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_ldrop = ig2cq_ldrop; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_lens = ig2cq_lens; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_ltran = ig2cq_ltran; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_odd = ig2cq_odd; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_prdy = cq_wr_prdy; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_pvld = cq_wr_pvld; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_swizzle = ig2cq_swizzle; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_thread_id = cq_wr_thread_id; +`ifdef NVDLA_PRINT_AXI +reg [32 -1:0] mon_axi_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mon_axi_count <= 0; + end else begin + mon_axi_count <= mon_axi_count + 1'b1; + end + if (mcif2noc_axi_ar_arvalid & mcif2noc_axi_ar_arready) begin + $display("NVDLA NOCIF_DRAM READ ADDR:time=%0d:cycle=%0d:addr=0x%0h:id=%0d:cache=%0d:size=%0d:len=%0d:usid=%0d:usize=%0d",$stime,mon_axi_count,mcif2noc_axi_ar_araddr,mcif2noc_axi_ar_arid,mcif2noc_axi_ar_arcache,mcif2noc_axi_ar_arsize,mcif2noc_axi_ar_arlen,mcif2noc_axi_ar_aruser[7:0],mcif2noc_axi_ar_aruser[28:26]); + end +end +`endif +endmodule // NV_NVDLA_NOCIF_READ_IG_cvt +module NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,axi_cmd_pd + ,axi_cmd_vld + ,opipe_axi_rdy + ,axi_cmd_rdy + ,opipe_axi_pd + ,opipe_axi_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +5:0] axi_cmd_pd; +input axi_cmd_vld; +input opipe_axi_rdy; +output axi_cmd_rdy; +output [32 +5:0] opipe_axi_pd; +output opipe_axi_vld; +reg axi_cmd_rdy; +reg [32 +5:0] opipe_axi_pd; +reg opipe_axi_vld; +reg [32 +5:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32 +5:0] p1_skid_data; +reg [32 +5:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + axi_cmd_vld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = axi_cmd_vld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + axi_cmd_rdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + axi_cmd_rdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? axi_cmd_pd[32 +5:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or axi_cmd_vld + or p1_skid_valid + or axi_cmd_pd + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? axi_cmd_vld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? axi_cmd_pd[32 +5:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or opipe_axi_rdy + or p1_pipe_data + ) begin + opipe_axi_vld = p1_pipe_valid; + p1_pipe_ready = opipe_axi_rdy; + opipe_axi_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (opipe_axi_vld^opipe_axi_rdy^axi_cmd_vld^axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (axi_cmd_vld && !axi_cmd_rdy), (axi_cmd_vld), (axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v.vcp new file mode 100644 index 0000000..270aab0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v.vcp @@ -0,0 +1,704 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_cvt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cq_wr_prdy //|< i + ,mcif2noc_axi_ar_arready //|< i + ,eg2ig_axi_vld //|< i + ,reg2dp_rd_os_cnt //|< i + ,spt2cvt_req_pd //|< i + ,spt2cvt_req_valid //|< i + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,cq_wr_thread_id //|> o + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o + ,spt2cvt_req_ready //|> o + ); +// +// NV_NVDLA_NOCIF_READ_IG_cvt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input spt2cvt_req_valid; /* data valid */ +output spt2cvt_req_ready; /* data return handshake */ +input [32 +10:0] spt2cvt_req_pd; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [6:0] cq_wr_pd; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +//&Ports /streamid/; //stepheng,remove +input [7:0] reg2dp_rd_os_cnt; +input eg2ig_axi_vld; +reg eg2ig_axi_vld_d; +reg os_adv; +reg [8:0] os_cnt; +reg [8:0] os_cnt_cur; +reg [10:0] os_cnt_ext; +reg [10:0] os_cnt_mod; +reg [10:0] os_cnt_new; +reg [10:0] os_cnt_nxt; +wire [32 -1:0] axi_addr; +wire [3:0] axi_axid; +wire [32 +5:0] axi_cmd_pd; +wire axi_cmd_rdy; +wire axi_cmd_vld; +wire [1:0] axi_len; +wire [7:0] cfg_rd_os_cnt; +wire [32 -1:0] cmd_addr; +wire [3:0] cmd_axid; +wire cmd_ftran; +wire cmd_ltran; +wire cmd_odd; +wire cmd_rdy; +wire [2:0] cmd_size; +wire cmd_swizzle; +wire cmd_vld; +wire end_addr_is_32_align; +wire [2:0] end_offset; +wire [1:0] end_offset_2_1_NC; +wire ig2cq_fdrop; +wire ig2cq_ldrop; +wire [1:0] ig2cq_lens; +wire ig2cq_ltran; +wire ig2cq_odd; +wire ig2cq_swizzle; +wire inc; +wire mon_axi_len_c; +wire mon_end_offset_c; +wire [32 -1:0] opipe_axi_addr; +wire [3:0] opipe_axi_axid; +wire [1:0] opipe_axi_len; +wire [32 +5:0] opipe_axi_pd; +wire opipe_axi_rdy; +wire opipe_axi_vld; +wire [2:0] os_cnt_add; +wire os_cnt_add_en; +wire os_cnt_cen; +wire os_cnt_full; +wire [0:0] os_cnt_sub; +wire os_cnt_sub_en; +wire [2:0] os_inp_add_nxt; +wire [9:0] os_inp_nxt; +wire [0:0] os_inp_sub_nxt; +wire [8:0] rd_os_cnt_ext; +wire stt_addr_is_32_align; +wire [2:0] stt_offset; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// IG===UNPACK +assign cmd_vld = spt2cvt_req_valid; +assign spt2cvt_req_ready = cmd_rdy; +// PKT_UNPACK_WIRE( cvt_read_cmd , cmd_ , spt2cvt_req_pd ) +assign cmd_axid[3:0] = spt2cvt_req_pd[3:0]; +assign cmd_addr[32 -1:0] = spt2cvt_req_pd[32 +3:4]; +assign cmd_size[2:0] = spt2cvt_req_pd[32 +6:32 +4]; +assign cmd_swizzle = spt2cvt_req_pd[32 +7]; +assign cmd_odd = spt2cvt_req_pd[32 +8]; +assign cmd_ltran = spt2cvt_req_pd[32 +9]; +assign cmd_ftran = spt2cvt_req_pd[32 +10]; +// IG===address calculation +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"5 bit of addr LSB should always be 0") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, (|cmd_addr[4:0]== 1'b1 )); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign stt_offset = cmd_addr[7:5]; // start position within a 256B block +assign stt_addr_is_32_align = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) ? 1'b0 : (stt_offset[0]== 1'b1 ); +assign {mon_end_offset_c,end_offset[2:0]} = stt_offset + cmd_size; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"end address should never cross 256B address boundary") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_end_offset_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign end_offset_2_1_NC = end_offset[2:1]; // only need end_offset bit0 to know end addr alignment +assign end_addr_is_32_align = 1'b0; //(NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2)? 1'b0 : (end_offset[0]== 1'b0 ); +// IG===AXI Trans GEN +assign axi_axid = cmd_axid; +//assign axi_addr = cmd_addr & 40'hff_ffff_ffc0; // make [5:0]=0 +//assign axi_addr = cmd_addr & 64'hffff_ffff_ffff_ffc0; // stepheng, ake [5:0]=0 +reg [32 -1:0] axi_addr_i; +//:print qq( +//:always @(cmd_addr) begin +//: axi_addr_i = cmd_addr; +//: axi_addr_i[3 -1:0] = 0; +//:end +//: assign axi_addr = axi_addr_i; +//:); +//assign axi_size = AXSIZE_64; //stepheng. remove +assign inc = cmd_ftran & cmd_ltran & (cmd_size[0]==1) & cmd_swizzle; +//assign {mon_axi_len_c, axi_len[1:0]} = cmd_size[2:1] + inc; +assign axi_len[1:0] = cmd_size[1:0]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"Should not be overflow") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_axi_len_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//assign axi_user_size = cmd_user_size; //stepheng,remove +//assign axi_streamid = falcon2mcif_streamid; //stepheng,remove. +// IG===Context Queue +// ( Upp,Low) 10 11 00 01 +// Count +// 0: F 1M L +// 1: F+1M F+L 2M 1M+L +// 2: F+2M F+1M+L 3M 2M+L +// 3: F+3M F+2M+L 4M 3M+L +assign cq_wr_pvld = cmd_vld & axi_cmd_rdy & !os_cnt_full; // inter-lock with opipe +assign ig2cq_lens = axi_len; +assign ig2cq_swizzle = cmd_swizzle; +assign ig2cq_ltran = cmd_ltran; +assign ig2cq_odd = cmd_odd; +assign ig2cq_fdrop = cmd_ftran & stt_addr_is_32_align; +assign ig2cq_ldrop = cmd_ltran & end_addr_is_32_align; +//assign cq_wr_pd = {ig2cq_cnt,ig2cq_upp,ig2cq_low}; +// PKT_PACK_WIRE( nocif_read_ig2eg , ig2cq_ , cq_wr_pd ) +assign cq_wr_pd[1:0] = ig2cq_lens[1:0]; +assign cq_wr_pd[2] = ig2cq_swizzle ; +assign cq_wr_pd[3] = ig2cq_odd ; +assign cq_wr_pd[4] = ig2cq_ltran ; +assign cq_wr_pd[5] = ig2cq_fdrop ; +assign cq_wr_pd[6] = ig2cq_ldrop ; +//:my $k = 7; +//:my $i; +//:my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//:my @client_id = (0,8,9,3,2,4,1,5,7,6,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:print qq(assign cq_wr_thread_id = ); +//:for ($i=0;$i<$k;$i++) { +//: print qq((cmd_axid == $remap_clientid[$i]) ? $i :); +//:} +//: print qq(0;); +//assign cq_wr_thread_id = cmd_axid; +// IG===AXI OUT PIPE +assign axi_cmd_vld = cmd_vld & cq_wr_prdy & !os_cnt_full; // inter-lock with context-queue +assign cmd_rdy = axi_cmd_rdy & cq_wr_prdy & !os_cnt_full; +assign os_inp_add_nxt[2:0] = cmd_vld ? (axi_len + 1) : 3'd0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg2ig_axi_vld_d <= 1'b0; + end else begin + eg2ig_axi_vld_d <= eg2ig_axi_vld; + end +end +assign os_inp_sub_nxt[0:0] = eg2ig_axi_vld_d ? 1'd1 : 1'd0; +assign os_inp_nxt[9:0] = os_cnt + os_inp_add_nxt - os_inp_sub_nxt; +// 256 outstanding trans +assign os_cnt_add_en = axi_cmd_vld & axi_cmd_rdy; +assign os_cnt_sub_en = eg2ig_axi_vld_d; +assign os_cnt_cen = os_cnt_add_en | os_cnt_sub_en; +assign os_cnt_add = os_cnt_add_en ? (axi_len + 1) : 3'd0; +assign os_cnt_sub = os_cnt_sub_en ? 1'd1 : 1'd0; +assign cfg_rd_os_cnt = reg2dp_rd_os_cnt[7:0]; +assign rd_os_cnt_ext = {{1{1'b0}}, cfg_rd_os_cnt}; +assign os_cnt_full = os_inp_nxt > (rd_os_cnt_ext + 1); +// os adv logic +always @( + os_cnt_add + or os_cnt_sub + ) begin + os_adv = os_cnt_add[2:0] != {{2{1'b0}}, os_cnt_sub[0:0]}; +end +// os cnt logic +always @( + os_cnt_cur + or os_cnt_add + or os_cnt_sub + or os_adv + ) begin +// VCS sop_coverage_off start + os_cnt_ext[10:0] = {1'b0, 1'b0, os_cnt_cur}; + os_cnt_mod[10:0] = os_cnt_cur + os_cnt_add[2:0] - os_cnt_sub[0:0]; // spyglass disable W164b + os_cnt_new[10:0] = (os_adv)? os_cnt_mod[10:0] : os_cnt_ext[10:0]; + os_cnt_nxt[10:0] = os_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// os flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + os_cnt_cur[8:0] <= 0; + end else begin + if (os_cnt_cen) begin + os_cnt_cur[8:0] <= os_cnt_nxt[8:0]; + end + end +end +// os output logic +always @( + os_cnt_cur + ) begin + os_cnt[8:0] = os_cnt_cur[8:0]; +end +// os asserts +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (os_cnt_nxt > 256 && os_cnt_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//stepheng. +NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.axi_cmd_pd (axi_cmd_pd[32 +5:0]) //|< w + ,.axi_cmd_vld (axi_cmd_vld) //|< w + ,.opipe_axi_rdy (opipe_axi_rdy) //|< w + ,.axi_cmd_rdy (axi_cmd_rdy) //|> w + ,.opipe_axi_pd (opipe_axi_pd[32 +5:0]) //|> w + ,.opipe_axi_vld (opipe_axi_vld) //|> w + ); +//my $w = eval(32 +6); +// &eperl::pipe("-is -wid $w -do opipe_axi_pd -vo opipe_axi_vld -ri axi_cmd_rdy -di axi_cmd_pd -vi axi_cmd_vld -ro opipe_axi_rdy"); +//stepheng,remove streamid & user_size & axi_size +assign axi_cmd_pd = {axi_axid,axi_addr,axi_len}; +assign {opipe_axi_axid,opipe_axi_addr,opipe_axi_len} = opipe_axi_pd; +// IG===AXI OUT ZERO EXT +assign mcif2noc_axi_ar_arid = {{4{1'b0}}, opipe_axi_axid}; +assign mcif2noc_axi_ar_araddr = opipe_axi_addr; +assign mcif2noc_axi_ar_arlen = {{2{1'b0}}, opipe_axi_len};//stepheng +//assign mcif2noc_axi_ar_arsize = opipe_axi_size; +//stepheng,remove +//// USER BITS +//&Always; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_ALL_BITS] = 0; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_StreamID_FIELD] = opipe_axi_streamid; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_user_size_FIELD] = opipe_axi_user_size; +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_vpr_rd_FIELD] = USER_VPR_RD; // vpr_rd +// mcif2noc_axi_ar_aruser[PKT_arnv_user_t_rsb_ns_FIELD] = USER_RSB_NS; // rsb_ns +//&End; +//stepheng,remove tie off. +//// IG===AXI OUT TIEOFF +//assign mcif2noc_axi_ar_arburst = AXBURST; +//assign mcif2noc_axi_ar_arlock = AXLOCK; +//assign mcif2noc_axi_ar_arcache = AXCACHE; +//assign mcif2noc_axi_ar_arprot = AXPROT; +//assign mcif2noc_axi_ar_arqos = AXQOS; +//assign mcif2noc_axi_ar_arregion = AXREGION; +// IG===AXI OUT valid/ready +assign mcif2noc_axi_ar_arvalid = opipe_axi_vld; +assign opipe_axi_rdy = mcif2noc_axi_ar_arready; +//========================================== +// OBS +//assign obs_bus_mcif_read_ig_cvt_axi_cmd_rdy = axi_cmd_rdy; +//assign obs_bus_mcif_read_ig_cvt_axi_cmd_vld = axi_cmd_vld; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_fdrop = ig2cq_fdrop; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_ldrop = ig2cq_ldrop; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_lens = ig2cq_lens; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_ltran = ig2cq_ltran; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_odd = ig2cq_odd; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_prdy = cq_wr_prdy; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_pvld = cq_wr_pvld; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_swizzle = ig2cq_swizzle; +//assign obs_bus_mcif_read_ig_cvt_ig2cq_thread_id = cq_wr_thread_id; +`ifdef NVDLA_PRINT_AXI +reg [32 -1:0] mon_axi_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mon_axi_count <= 0; + end else begin + mon_axi_count <= mon_axi_count + 1'b1; + end + if (mcif2noc_axi_ar_arvalid & mcif2noc_axi_ar_arready) begin + $display("NVDLA NOCIF_DRAM READ ADDR:time=%0d:cycle=%0d:addr=0x%0h:id=%0d:cache=%0d:size=%0d:len=%0d:usid=%0d:usize=%0d",$stime,mon_axi_count,mcif2noc_axi_ar_araddr,mcif2noc_axi_ar_arid,mcif2noc_axi_ar_arcache,mcif2noc_axi_ar_arsize,mcif2noc_axi_ar_arlen,mcif2noc_axi_ar_aruser[7:0],mcif2noc_axi_ar_aruser[28:26]); + end +end +`endif +endmodule // NV_NVDLA_NOCIF_READ_IG_cvt +module NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,axi_cmd_pd + ,axi_cmd_vld + ,opipe_axi_rdy + ,axi_cmd_rdy + ,opipe_axi_pd + ,opipe_axi_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +5:0] axi_cmd_pd; +input axi_cmd_vld; +input opipe_axi_rdy; +output axi_cmd_rdy; +output [32 +5:0] opipe_axi_pd; +output opipe_axi_vld; +reg axi_cmd_rdy; +reg [32 +5:0] opipe_axi_pd; +reg opipe_axi_vld; +reg [32 +5:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32 +5:0] p1_skid_data; +reg [32 +5:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + axi_cmd_vld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = axi_cmd_vld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + axi_cmd_rdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + axi_cmd_rdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? axi_cmd_pd[32 +5:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or axi_cmd_vld + or p1_skid_valid + or axi_cmd_pd + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? axi_cmd_vld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? axi_cmd_pd[32 +5:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or opipe_axi_rdy + or p1_pipe_data + ) begin + opipe_axi_vld = p1_pipe_valid; + p1_pipe_ready = opipe_axi_rdy; + opipe_axi_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (opipe_axi_vld^opipe_axi_rdy^axi_cmd_vld^axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (axi_cmd_vld && !axi_cmd_rdy), (axi_cmd_vld), (axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v new file mode 100644 index 0000000..cac175a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v @@ -0,0 +1,943 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_spt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,arb2spt_req_valid //|< i + ,arb2spt_req_ready //|> o + ,arb2spt_req_pd //|< i + ,spt2cvt_req_valid //|> o + ,spt2cvt_req_ready //|< i + ,spt2cvt_req_pd //|> o + ); +// +// NV_NVDLA_NOCIF_DRAM_READ_IG_spt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input arb2spt_req_valid; /* data valid */ +output arb2spt_req_ready; /* data return handshake */ +input [32 +10:0] arb2spt_req_pd; +output spt2cvt_req_valid; /* data valid */ +input spt2cvt_req_ready; /* data return handshake */ +output [32 +10:0] spt2cvt_req_pd; +reg is_2nd_req; +reg [32 +10:0] p2_pipe_data; +reg [32 +10:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg [32 +10:0] p2_pipe_skid_data; +reg p2_pipe_skid_ready; +reg p2_pipe_skid_valid; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32 +10:0] p2_skid_data; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg [32 +10:0] spt2cvt_req_pd; +reg spt2cvt_req_valid; +reg spt_out_rdy; +wire [2:0] end_offset; +wire end_offset_c; +wire [32 -1:0] first_req_addr; +wire [2:0] first_req_size; +wire is_cross_256byte_boundary; +wire req_accept; +wire [32 -1:0] second_req_addr; +wire [2:0] second_req_size; +wire [32 -1:0] spt2cvt_addr; +wire [3:0] spt2cvt_axid; +wire spt2cvt_ftran; +wire spt2cvt_ltran; +wire spt2cvt_odd; +wire [2:0] spt2cvt_size; +wire spt2cvt_swizzle; +wire [32 +10:0] spt_out_pd; +wire spt_out_vld; +wire [32 -1:0] spt_req_addr; +wire [3:0] spt_req_axid; +wire spt_req_ftran; +wire spt_req_ltran; +wire spt_req_odd; +wire [2:0] spt_req_offset; +wire [32 +10:0] spt_req_pd; +wire spt_req_rdy; +wire [2:0] spt_req_size; +wire spt_req_swizzle; +wire spt_req_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_req_pd (arb2spt_req_pd[32 +10:0]) //|< i + ,.arb2spt_req_valid (arb2spt_req_valid) //|< i + ,.spt_req_rdy (spt_req_rdy) //|< w + ,.arb2spt_req_ready (arb2spt_req_ready) //|> o + ,.spt_req_pd (spt_req_pd[32 +10:0]) //|> w + ,.spt_req_vld (spt_req_vld) //|> w + ); +//my $wi = eval(32 +10+1); +//&eperl::pipe(" -wid $wi -vo spt_req_vld -do spt_req_pd -ri arb2spt_req_ready -di arb2spt_req_pd -vi arb2spt_req_valid -ro spt_req_rdy"); +assign spt_req_rdy = spt_out_rdy & (!is_cross_256byte_boundary || (is_cross_256byte_boundary & is_2nd_req)); +// PKT_UNPACK_WIRE( cvt_read_cmd , spt_req_ , spt_req_pd ) +assign spt_req_axid[3:0] = spt_req_pd[3:0]; +assign spt_req_addr[32 -1:0] = spt_req_pd[32 -1+4:4]; +assign spt_req_size[2:0] = spt_req_pd[32 +6:32 +4]; +assign spt_req_swizzle = spt_req_pd[32 +7]; +assign spt_req_odd = spt_req_pd[32 +8]; +assign spt_req_ltran = spt_req_pd[32 +9]; +assign spt_req_ftran = spt_req_pd[32 +10]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + wire cond_zzz_assert_always_1x = (spt_req_addr[4:0] == 0); + nv_assert_always #(0,0,"lower 5 LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign spt_req_offset = spt_req_addr[3 +2:3]; +assign {end_offset_c,end_offset[2:0]} = spt_req_offset + spt_req_size; +//:my $i = log(64/8)/log(2); +//:if ($i == 3) { +//: print qq( +//: assign is_cross_256byte_boundary = 1'b0; +//:); +//:} else { +//: print qq( +//: assign is_cross_256byte_boundary = spt_req_vld & end_offset_c; +//: ); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign is_cross_256byte_boundary = 1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign is_cross_256byte_boundary = spt_req_vld & end_offset_c; +assign first_req_size = (is_cross_256byte_boundary) ? (7 - spt_req_offset) : spt_req_size; +assign first_req_addr = spt_req_addr; +// second_* is useful only when is_2nd_req needed +//assign second_req_addr = {spt_req_addr[39:8],{8{1'b0}}}; +reg [32 -1:0] second_req_addr_i; +//: my $i; +//: $i = (log(64/8)/log(2)) + 1; +//:print qq( +//: always @(spt_req_addr) begin +//: second_req_addr_i = spt_req_addr; +//: second_req_addr_i[$i:0] = 0; +//: end +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(spt_req_addr) begin +second_req_addr_i = spt_req_addr; +second_req_addr_i[4:0] = 0; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign second_req_addr = {spt_req_addr[32 -1:8],{8{1'b0}}}; +assign second_req_addr = second_req_addr_i; +assign second_req_size = end_offset; // only usefull when 2nd req is needed +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_2nd_req <= 1'b0; + end else begin + if (req_accept) begin + if (is_2nd_req) begin + is_2nd_req <= 0; + end else if (is_cross_256byte_boundary) begin + is_2nd_req <= 1; + end + end + end +end +assign spt2cvt_addr = (is_2nd_req) ? second_req_addr : first_req_addr; +assign spt2cvt_size = (is_2nd_req) ? second_req_size : first_req_size; +assign spt2cvt_swizzle = spt_req_swizzle; +assign spt2cvt_odd = spt_req_odd; +assign spt2cvt_ltran = spt_req_ltran; +assign spt2cvt_ftran = spt_req_ftran; +//assign spt2cvt_user_size = spt_req_user_size; //stepheng,remove +assign spt2cvt_axid = spt_req_axid; +assign req_accept = spt_out_vld & spt_out_rdy; +assign spt_out_vld = spt_req_vld; +// PKT_PACK_WIRE( cvt_read_cmd , spt2cvt_ , spt_out_pd ) +assign spt_out_pd[3:0] = spt2cvt_axid[3:0]; +assign spt_out_pd[32 -1+4:4] = spt2cvt_addr[32 -1:0]; +assign spt_out_pd[32 +6:32 +4] = spt2cvt_size[2:0]; +assign spt_out_pd[32 +7] = spt2cvt_swizzle ; +assign spt_out_pd[32 +8] = spt2cvt_odd ; +assign spt_out_pd[32 +9] = spt2cvt_ltran ; +assign spt_out_pd[32 +10] = spt2cvt_ftran ; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + spt_out_vld + or p2_pipe_rand_ready + or spt_out_pd + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = spt_out_vld; + spt_out_rdy = p2_pipe_rand_ready; + p2_pipe_rand_data = spt_out_pd; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : spt_out_vld; + spt_out_rdy = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : spt_out_pd; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or spt_out_vld + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && spt_out_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_pipe_rand_valid)? p2_pipe_rand_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_pipe_rand_ready = p2_pipe_ready_bc; +end +//## pipe (2) skid buffer +always @( + p2_pipe_valid + or p2_skid_ready_flop + or p2_pipe_skid_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_valid && p2_skid_ready_flop && !p2_pipe_skid_ready; + p2_skid_ready = (p2_skid_valid)? p2_pipe_skid_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_pipe_skid_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_valid + or p2_skid_valid + or p2_pipe_data + or p2_skid_data + ) begin + p2_pipe_skid_valid = (p2_skid_ready_flop)? p2_pipe_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_pipe_skid_data = (p2_skid_ready_flop)? p2_pipe_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) output +always @( + p2_pipe_skid_valid + or spt2cvt_req_ready + or p2_pipe_skid_data + ) begin + spt2cvt_req_valid = p2_pipe_skid_valid; + p2_pipe_skid_ready = spt2cvt_req_ready; + spt2cvt_req_pd = p2_pipe_skid_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (spt2cvt_req_valid^spt2cvt_req_ready^spt_out_vld^spt_out_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_3x (nvdla_core_clk, `ASSERT_RESET, (spt_out_vld && !spt_out_rdy), (spt_out_vld), (spt_out_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_READ_IG_spt +module NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,arb2spt_req_pd + ,arb2spt_req_valid + ,spt_req_rdy + ,arb2spt_req_ready + ,spt_req_pd + ,spt_req_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +10:0] arb2spt_req_pd; +input arb2spt_req_valid; +input spt_req_rdy; +output arb2spt_req_ready; +output [32 +10:0] spt_req_pd; +output spt_req_vld; +reg arb2spt_req_ready; +reg [32 +10:0] p1_pipe_data; +reg [32 +10:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg [32 +10:0] spt_req_pd; +reg spt_req_vld; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + arb2spt_req_valid + or p1_pipe_rand_ready + or arb2spt_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = arb2spt_req_valid; + arb2spt_req_ready = p1_pipe_rand_ready; + p1_pipe_rand_data = arb2spt_req_pd[32 +10:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : arb2spt_req_valid; + arb2spt_req_ready = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : arb2spt_req_pd[32 +10:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or arb2spt_req_valid + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && arb2spt_req_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_pipe_rand_valid)? p1_pipe_rand_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_pipe_rand_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or spt_req_rdy + or p1_pipe_data + ) begin + spt_req_vld = p1_pipe_valid; + p1_pipe_ready = spt_req_rdy; + spt_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (spt_req_vld^spt_req_rdy^arb2spt_req_valid^arb2spt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_5x (nvdla_core_clk, `ASSERT_RESET, (arb2spt_req_valid && !arb2spt_req_ready), (arb2spt_req_valid), (arb2spt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v.vcp new file mode 100644 index 0000000..f5865e7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v.vcp @@ -0,0 +1,930 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_IG_spt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,arb2spt_req_valid //|< i + ,arb2spt_req_ready //|> o + ,arb2spt_req_pd //|< i + ,spt2cvt_req_valid //|> o + ,spt2cvt_req_ready //|< i + ,spt2cvt_req_pd //|> o + ); +// +// NV_NVDLA_NOCIF_DRAM_READ_IG_spt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input arb2spt_req_valid; /* data valid */ +output arb2spt_req_ready; /* data return handshake */ +input [32 +10:0] arb2spt_req_pd; +output spt2cvt_req_valid; /* data valid */ +input spt2cvt_req_ready; /* data return handshake */ +output [32 +10:0] spt2cvt_req_pd; +reg is_2nd_req; +reg [32 +10:0] p2_pipe_data; +reg [32 +10:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg [32 +10:0] p2_pipe_skid_data; +reg p2_pipe_skid_ready; +reg p2_pipe_skid_valid; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32 +10:0] p2_skid_data; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg [32 +10:0] spt2cvt_req_pd; +reg spt2cvt_req_valid; +reg spt_out_rdy; +wire [2:0] end_offset; +wire end_offset_c; +wire [32 -1:0] first_req_addr; +wire [2:0] first_req_size; +wire is_cross_256byte_boundary; +wire req_accept; +wire [32 -1:0] second_req_addr; +wire [2:0] second_req_size; +wire [32 -1:0] spt2cvt_addr; +wire [3:0] spt2cvt_axid; +wire spt2cvt_ftran; +wire spt2cvt_ltran; +wire spt2cvt_odd; +wire [2:0] spt2cvt_size; +wire spt2cvt_swizzle; +wire [32 +10:0] spt_out_pd; +wire spt_out_vld; +wire [32 -1:0] spt_req_addr; +wire [3:0] spt_req_axid; +wire spt_req_ftran; +wire spt_req_ltran; +wire spt_req_odd; +wire [2:0] spt_req_offset; +wire [32 +10:0] spt_req_pd; +wire spt_req_rdy; +wire [2:0] spt_req_size; +wire spt_req_swizzle; +wire spt_req_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_req_pd (arb2spt_req_pd[32 +10:0]) //|< i + ,.arb2spt_req_valid (arb2spt_req_valid) //|< i + ,.spt_req_rdy (spt_req_rdy) //|< w + ,.arb2spt_req_ready (arb2spt_req_ready) //|> o + ,.spt_req_pd (spt_req_pd[32 +10:0]) //|> w + ,.spt_req_vld (spt_req_vld) //|> w + ); +//my $wi = eval(32 +10+1); +//&eperl::pipe(" -wid $wi -vo spt_req_vld -do spt_req_pd -ri arb2spt_req_ready -di arb2spt_req_pd -vi arb2spt_req_valid -ro spt_req_rdy"); +assign spt_req_rdy = spt_out_rdy & (!is_cross_256byte_boundary || (is_cross_256byte_boundary & is_2nd_req)); +// PKT_UNPACK_WIRE( cvt_read_cmd , spt_req_ , spt_req_pd ) +assign spt_req_axid[3:0] = spt_req_pd[3:0]; +assign spt_req_addr[32 -1:0] = spt_req_pd[32 -1+4:4]; +assign spt_req_size[2:0] = spt_req_pd[32 +6:32 +4]; +assign spt_req_swizzle = spt_req_pd[32 +7]; +assign spt_req_odd = spt_req_pd[32 +8]; +assign spt_req_ltran = spt_req_pd[32 +9]; +assign spt_req_ftran = spt_req_pd[32 +10]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + wire cond_zzz_assert_always_1x = (spt_req_addr[4:0] == 0); + nv_assert_always #(0,0,"lower 5 LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign spt_req_offset = spt_req_addr[3 +2:3]; +assign {end_offset_c,end_offset[2:0]} = spt_req_offset + spt_req_size; +//:my $i = log(64/8)/log(2); +//:if ($i == 3) { +//: print qq( +//: assign is_cross_256byte_boundary = 1'b0; +//:); +//:} else { +//: print qq( +//: assign is_cross_256byte_boundary = spt_req_vld & end_offset_c; +//: ); +//:} +//assign is_cross_256byte_boundary = spt_req_vld & end_offset_c; +assign first_req_size = (is_cross_256byte_boundary) ? (7 - spt_req_offset) : spt_req_size; +assign first_req_addr = spt_req_addr; +// second_* is useful only when is_2nd_req needed +//assign second_req_addr = {spt_req_addr[39:8],{8{1'b0}}}; +reg [32 -1:0] second_req_addr_i; +//: my $i; +//: $i = (log(64/8)/log(2)) + 1; +//:print qq( +//: always @(spt_req_addr) begin +//: second_req_addr_i = spt_req_addr; +//: second_req_addr_i[$i:0] = 0; +//: end +//:); +//assign second_req_addr = {spt_req_addr[32 -1:8],{8{1'b0}}}; +assign second_req_addr = second_req_addr_i; +assign second_req_size = end_offset; // only usefull when 2nd req is needed +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_2nd_req <= 1'b0; + end else begin + if (req_accept) begin + if (is_2nd_req) begin + is_2nd_req <= 0; + end else if (is_cross_256byte_boundary) begin + is_2nd_req <= 1; + end + end + end +end +assign spt2cvt_addr = (is_2nd_req) ? second_req_addr : first_req_addr; +assign spt2cvt_size = (is_2nd_req) ? second_req_size : first_req_size; +assign spt2cvt_swizzle = spt_req_swizzle; +assign spt2cvt_odd = spt_req_odd; +assign spt2cvt_ltran = spt_req_ltran; +assign spt2cvt_ftran = spt_req_ftran; +//assign spt2cvt_user_size = spt_req_user_size; //stepheng,remove +assign spt2cvt_axid = spt_req_axid; +assign req_accept = spt_out_vld & spt_out_rdy; +assign spt_out_vld = spt_req_vld; +// PKT_PACK_WIRE( cvt_read_cmd , spt2cvt_ , spt_out_pd ) +assign spt_out_pd[3:0] = spt2cvt_axid[3:0]; +assign spt_out_pd[32 -1+4:4] = spt2cvt_addr[32 -1:0]; +assign spt_out_pd[32 +6:32 +4] = spt2cvt_size[2:0]; +assign spt_out_pd[32 +7] = spt2cvt_swizzle ; +assign spt_out_pd[32 +8] = spt2cvt_odd ; +assign spt_out_pd[32 +9] = spt2cvt_ltran ; +assign spt_out_pd[32 +10] = spt2cvt_ftran ; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + spt_out_vld + or p2_pipe_rand_ready + or spt_out_pd + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = spt_out_vld; + spt_out_rdy = p2_pipe_rand_ready; + p2_pipe_rand_data = spt_out_pd; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : spt_out_vld; + spt_out_rdy = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : spt_out_pd; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_READ_IG_spt_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or spt_out_vld + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && spt_out_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_pipe_rand_valid)? p2_pipe_rand_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_pipe_rand_ready = p2_pipe_ready_bc; +end +//## pipe (2) skid buffer +always @( + p2_pipe_valid + or p2_skid_ready_flop + or p2_pipe_skid_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_valid && p2_skid_ready_flop && !p2_pipe_skid_ready; + p2_skid_ready = (p2_skid_valid)? p2_pipe_skid_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_pipe_skid_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_valid + or p2_skid_valid + or p2_pipe_data + or p2_skid_data + ) begin + p2_pipe_skid_valid = (p2_skid_ready_flop)? p2_pipe_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_pipe_skid_data = (p2_skid_ready_flop)? p2_pipe_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) output +always @( + p2_pipe_skid_valid + or spt2cvt_req_ready + or p2_pipe_skid_data + ) begin + spt2cvt_req_valid = p2_pipe_skid_valid; + p2_pipe_skid_ready = spt2cvt_req_ready; + spt2cvt_req_pd = p2_pipe_skid_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (spt2cvt_req_valid^spt2cvt_req_ready^spt_out_vld^spt_out_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_3x (nvdla_core_clk, `ASSERT_RESET, (spt_out_vld && !spt_out_rdy), (spt_out_vld), (spt_out_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_READ_IG_spt +module NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,arb2spt_req_pd + ,arb2spt_req_valid + ,spt_req_rdy + ,arb2spt_req_ready + ,spt_req_pd + ,spt_req_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +10:0] arb2spt_req_pd; +input arb2spt_req_valid; +input spt_req_rdy; +output arb2spt_req_ready; +output [32 +10:0] spt_req_pd; +output spt_req_vld; +reg arb2spt_req_ready; +reg [32 +10:0] p1_pipe_data; +reg [32 +10:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg [32 +10:0] spt_req_pd; +reg spt_req_vld; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + arb2spt_req_valid + or p1_pipe_rand_ready + or arb2spt_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = arb2spt_req_valid; + arb2spt_req_ready = p1_pipe_rand_ready; + p1_pipe_rand_data = arb2spt_req_pd[32 +10:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : arb2spt_req_valid; + arb2spt_req_ready = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : arb2spt_req_pd[32 +10:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_IG_spt_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or arb2spt_req_valid + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && arb2spt_req_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_pipe_rand_valid)? p1_pipe_rand_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_pipe_rand_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or spt_req_rdy + or p1_pipe_data + ) begin + spt_req_vld = p1_pipe_valid; + p1_pipe_ready = spt_req_rdy; + spt_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (spt_req_vld^spt_req_rdy^arb2spt_req_valid^arb2spt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_5x (nvdla_core_clk, `ASSERT_RESET, (arb2spt_req_valid && !arb2spt_req_ready), (arb2spt_req_valid), (arb2spt_req_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v new file mode 100644 index 0000000..6e8dbc9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v @@ -0,0 +1,4094 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_READ_cq ( + nvdla_core_clk + , nvdla_core_rstn + , cq_wr_prdy + , cq_wr_pvld + , cq_wr_thread_id +`ifdef FV_RAND_WR_PAUSE + , cq_wr_pause +`endif + , cq_wr_pd + , cq_rd0_prdy + , cq_rd0_pvld + , cq_rd0_pd + , cq_rd1_prdy + , cq_rd1_pvld + , cq_rd1_pd + , cq_rd2_prdy + , cq_rd2_pvld + , cq_rd2_pd + , cq_rd3_prdy + , cq_rd3_pvld + , cq_rd3_pd + , cq_rd4_prdy + , cq_rd4_pvld + , cq_rd4_pd + , cq_rd5_prdy + , cq_rd5_pvld + , cq_rd5_pd + , cq_rd6_prdy + , cq_rd6_pvld + , cq_rd6_pd + , cq_rd7_prdy + , cq_rd7_pvld + , cq_rd7_pd + , cq_rd8_prdy + , cq_rd8_pvld + , cq_rd8_pd + , cq_rd9_prdy + , cq_rd9_pvld + , cq_rd9_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cq_wr_prdy; +input cq_wr_pvld; +input [3:0] cq_wr_thread_id; +`ifdef FV_RAND_WR_PAUSE +input cq_wr_pause; +`endif +input [6:0] cq_wr_pd; +input cq_rd0_prdy; +output cq_rd0_pvld; +output [6:0] cq_rd0_pd; +input cq_rd1_prdy; +output cq_rd1_pvld; +output [6:0] cq_rd1_pd; +input cq_rd2_prdy; +output cq_rd2_pvld; +output [6:0] cq_rd2_pd; +input cq_rd3_prdy; +output cq_rd3_pvld; +output [6:0] cq_rd3_pd; +input cq_rd4_prdy; +output cq_rd4_pvld; +output [6:0] cq_rd4_pd; +input cq_rd5_prdy; +output cq_rd5_pvld; +output [6:0] cq_rd5_pd; +input cq_rd6_prdy; +output cq_rd6_pvld; +output [6:0] cq_rd6_pd; +input cq_rd7_prdy; +output cq_rd7_pvld; +output [6:0] cq_rd7_pd; +input cq_rd8_prdy; +output cq_rd8_pvld; +output [6:0] cq_rd8_pd; +input cq_rd9_prdy; +output cq_rd9_pvld; +output [6:0] cq_rd9_pd; +input [31:0] pwrbus_ram_pd; +// -rd_take_to_rd_busy internal credit/take/data signals (which would have been ports) +// +//wire [9:0] cq_rd_credit; +wire cq_rd_take; +wire [6:0] cq_rd_pd_p; +wire [3:0] cq_rd_take_thread_id; +// We also declare some per-thread flags that indicate whether to have the write bypass the internal fifo. +// These per-class wr_bypassing* flags are set by the take-side logic. We basically pretend that we never pushed the fifo, +// but make sure we return a credit to the sender. +// +wire wr_bypassing; // any thread bypassed +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_skid; +wire nvdla_core_clk_mgated_skid_enable; +NV_CLK_gate_power nvdla_core_clk_rd_mgate_skid( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_skid_enable), .clk_gated(nvdla_core_clk_mgated_skid) ); +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cq_wr_busy_int; // copy for internal use +assign cq_wr_prdy = !cq_wr_busy_int; +assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [8:0] cq_wr_count; // write-side count +wire wr_reserving_and_not_bypassing = wr_reserving && !wr_bypassing; +wire [8:0] wr_count_next_wr_popping = wr_reserving_and_not_bypassing ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [8:0] wr_count_next_no_wr_popping = wr_reserving_and_not_bypassing ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484 +wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 ); +wire wr_count_next_is_256 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_256; +wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [8:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || cq_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_busy_int <= 1'b0; + cq_wr_count <= 9'd0; + end else begin + cq_wr_busy_int <= cq_wr_busy_next; + if ( wr_reserving_and_not_bypassing ^ wr_popping ) begin + cq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving_and_not_bypassing ^ wr_popping) ) begin + end else begin + cq_wr_count <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving && !wr_bypassing; // data pushed same cycle as cq_wr_pvld +wire [3:0] wr_pushing_thread_id = cq_wr_thread_id; // thread being written +// +// RAM +// +wire wr_adr_popping = wr_pushing; // pop free list when wr_pushing=1 +wire [7:0] cq_wr_adr; // current write address +reg [7:0] cq_rd_adr; +wire [7:0] cq_rd_adr_p = cq_rd_adr; // read address to use for ram +wire rd_enable; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rws_256x7 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( cq_wr_adr ) + , .we ( wr_pushing ) + , .di ( cq_wr_pd ) + , .ra ( cq_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( cq_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +// +// SYNCHRONOUS BOUNDARY +// +wire rd_pushing = wr_pushing; // let it be seen immediately +wire [3:0] rd_pushing_thread_id = wr_pushing_thread_id; +wire [7:0] rd_pushing_adr = cq_wr_adr; +// +// MULTITHREADED FREE LIST FIFO +// +// free list of cq_wr_adr's from read side to write side +// these are passed in a ff fifo when the fifo is popped +// +// there's an extra mux of the internal flops that is +// used to determine which address to use when +// rd_pushing is 1 if the fifo is async. +// +wire [7:0] rd_popping_adr; // cq_rd_adr to free up +wire [7:0] free_adr_index; +reg [255-1:0] free_adr_mask_next; +reg [255-1:0] free_adr_mask; +assign cq_wr_adr = free_adr_index; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + free_adr_mask <= {255{1'b1}}; + end else begin + if ( rd_popping || wr_adr_popping ) begin + free_adr_mask <= free_adr_mask_next; + end +//synopsys translate_off + else if ( !(rd_popping || wr_adr_popping) ) begin + end else begin + free_adr_mask <= {255{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(*) begin + free_adr_mask_next = free_adr_mask; + if ( rd_popping && rd_popping_adr == 8'd0 ) begin + free_adr_mask_next[0] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd0 ) begin + free_adr_mask_next[0] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd1 ) begin + free_adr_mask_next[1] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd1 ) begin + free_adr_mask_next[1] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd2 ) begin + free_adr_mask_next[2] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd2 ) begin + free_adr_mask_next[2] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd3 ) begin + free_adr_mask_next[3] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd3 ) begin + free_adr_mask_next[3] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd4 ) begin + free_adr_mask_next[4] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd4 ) begin + free_adr_mask_next[4] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd5 ) begin + free_adr_mask_next[5] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd5 ) begin + free_adr_mask_next[5] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd6 ) begin + free_adr_mask_next[6] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd6 ) begin + free_adr_mask_next[6] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd7 ) begin + free_adr_mask_next[7] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd7 ) begin + free_adr_mask_next[7] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd8 ) begin + free_adr_mask_next[8] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd8 ) begin + free_adr_mask_next[8] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd9 ) begin + free_adr_mask_next[9] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd9 ) begin + free_adr_mask_next[9] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd10 ) begin + free_adr_mask_next[10] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd10 ) begin + free_adr_mask_next[10] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd11 ) begin + free_adr_mask_next[11] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd11 ) begin + free_adr_mask_next[11] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd12 ) begin + free_adr_mask_next[12] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd12 ) begin + free_adr_mask_next[12] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd13 ) begin + free_adr_mask_next[13] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd13 ) begin + free_adr_mask_next[13] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd14 ) begin + free_adr_mask_next[14] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd14 ) begin + free_adr_mask_next[14] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd15 ) begin + free_adr_mask_next[15] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd15 ) begin + free_adr_mask_next[15] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd16 ) begin + free_adr_mask_next[16] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd16 ) begin + free_adr_mask_next[16] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd17 ) begin + free_adr_mask_next[17] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd17 ) begin + free_adr_mask_next[17] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd18 ) begin + free_adr_mask_next[18] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd18 ) begin + free_adr_mask_next[18] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd19 ) begin + free_adr_mask_next[19] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd19 ) begin + free_adr_mask_next[19] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd20 ) begin + free_adr_mask_next[20] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd20 ) begin + free_adr_mask_next[20] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd21 ) begin + free_adr_mask_next[21] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd21 ) begin + free_adr_mask_next[21] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd22 ) begin + free_adr_mask_next[22] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd22 ) begin + free_adr_mask_next[22] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd23 ) begin + free_adr_mask_next[23] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd23 ) begin + free_adr_mask_next[23] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd24 ) begin + free_adr_mask_next[24] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd24 ) begin + free_adr_mask_next[24] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd25 ) begin + free_adr_mask_next[25] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd25 ) begin + free_adr_mask_next[25] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd26 ) begin + free_adr_mask_next[26] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd26 ) begin + free_adr_mask_next[26] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd27 ) begin + free_adr_mask_next[27] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd27 ) begin + free_adr_mask_next[27] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd28 ) begin + free_adr_mask_next[28] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd28 ) begin + free_adr_mask_next[28] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd29 ) begin + free_adr_mask_next[29] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd29 ) begin + free_adr_mask_next[29] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd30 ) begin + free_adr_mask_next[30] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd30 ) begin + free_adr_mask_next[30] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd31 ) begin + free_adr_mask_next[31] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd31 ) begin + free_adr_mask_next[31] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd32 ) begin + free_adr_mask_next[32] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd32 ) begin + free_adr_mask_next[32] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd33 ) begin + free_adr_mask_next[33] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd33 ) begin + free_adr_mask_next[33] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd34 ) begin + free_adr_mask_next[34] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd34 ) begin + free_adr_mask_next[34] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd35 ) begin + free_adr_mask_next[35] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd35 ) begin + free_adr_mask_next[35] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd36 ) begin + free_adr_mask_next[36] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd36 ) begin + free_adr_mask_next[36] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd37 ) begin + free_adr_mask_next[37] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd37 ) begin + free_adr_mask_next[37] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd38 ) begin + free_adr_mask_next[38] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd38 ) begin + free_adr_mask_next[38] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd39 ) begin + free_adr_mask_next[39] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd39 ) begin + free_adr_mask_next[39] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd40 ) begin + free_adr_mask_next[40] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd40 ) begin + free_adr_mask_next[40] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd41 ) begin + free_adr_mask_next[41] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd41 ) begin + free_adr_mask_next[41] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd42 ) begin + free_adr_mask_next[42] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd42 ) begin + free_adr_mask_next[42] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd43 ) begin + free_adr_mask_next[43] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd43 ) begin + free_adr_mask_next[43] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd44 ) begin + free_adr_mask_next[44] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd44 ) begin + free_adr_mask_next[44] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd45 ) begin + free_adr_mask_next[45] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd45 ) begin + free_adr_mask_next[45] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd46 ) begin + free_adr_mask_next[46] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd46 ) begin + free_adr_mask_next[46] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd47 ) begin + free_adr_mask_next[47] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd47 ) begin + free_adr_mask_next[47] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd48 ) begin + free_adr_mask_next[48] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd48 ) begin + free_adr_mask_next[48] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd49 ) begin + free_adr_mask_next[49] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd49 ) begin + free_adr_mask_next[49] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd50 ) begin + free_adr_mask_next[50] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd50 ) begin + free_adr_mask_next[50] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd51 ) begin + free_adr_mask_next[51] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd51 ) begin + free_adr_mask_next[51] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd52 ) begin + free_adr_mask_next[52] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd52 ) begin + free_adr_mask_next[52] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd53 ) begin + free_adr_mask_next[53] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd53 ) begin + free_adr_mask_next[53] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd54 ) begin + free_adr_mask_next[54] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd54 ) begin + free_adr_mask_next[54] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd55 ) begin + free_adr_mask_next[55] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd55 ) begin + free_adr_mask_next[55] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd56 ) begin + free_adr_mask_next[56] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd56 ) begin + free_adr_mask_next[56] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd57 ) begin + free_adr_mask_next[57] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd57 ) begin + free_adr_mask_next[57] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd58 ) begin + free_adr_mask_next[58] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd58 ) begin + free_adr_mask_next[58] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd59 ) begin + free_adr_mask_next[59] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd59 ) begin + free_adr_mask_next[59] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd60 ) begin + free_adr_mask_next[60] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd60 ) begin + free_adr_mask_next[60] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd61 ) begin + free_adr_mask_next[61] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd61 ) begin + free_adr_mask_next[61] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd62 ) begin + free_adr_mask_next[62] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd62 ) begin + free_adr_mask_next[62] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd63 ) begin + free_adr_mask_next[63] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd63 ) begin + free_adr_mask_next[63] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd64 ) begin + free_adr_mask_next[64] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd64 ) begin + free_adr_mask_next[64] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd65 ) begin + free_adr_mask_next[65] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd65 ) begin + free_adr_mask_next[65] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd66 ) begin + free_adr_mask_next[66] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd66 ) begin + free_adr_mask_next[66] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd67 ) begin + free_adr_mask_next[67] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd67 ) begin + free_adr_mask_next[67] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd68 ) begin + free_adr_mask_next[68] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd68 ) begin + free_adr_mask_next[68] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd69 ) begin + free_adr_mask_next[69] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd69 ) begin + free_adr_mask_next[69] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd70 ) begin + free_adr_mask_next[70] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd70 ) begin + free_adr_mask_next[70] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd71 ) begin + free_adr_mask_next[71] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd71 ) begin + free_adr_mask_next[71] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd72 ) begin + free_adr_mask_next[72] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd72 ) begin + free_adr_mask_next[72] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd73 ) begin + free_adr_mask_next[73] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd73 ) begin + free_adr_mask_next[73] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd74 ) begin + free_adr_mask_next[74] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd74 ) begin + free_adr_mask_next[74] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd75 ) begin + free_adr_mask_next[75] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd75 ) begin + free_adr_mask_next[75] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd76 ) begin + free_adr_mask_next[76] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd76 ) begin + free_adr_mask_next[76] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd77 ) begin + free_adr_mask_next[77] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd77 ) begin + free_adr_mask_next[77] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd78 ) begin + free_adr_mask_next[78] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd78 ) begin + free_adr_mask_next[78] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd79 ) begin + free_adr_mask_next[79] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd79 ) begin + free_adr_mask_next[79] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd80 ) begin + free_adr_mask_next[80] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd80 ) begin + free_adr_mask_next[80] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd81 ) begin + free_adr_mask_next[81] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd81 ) begin + free_adr_mask_next[81] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd82 ) begin + free_adr_mask_next[82] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd82 ) begin + free_adr_mask_next[82] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd83 ) begin + free_adr_mask_next[83] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd83 ) begin + free_adr_mask_next[83] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd84 ) begin + free_adr_mask_next[84] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd84 ) begin + free_adr_mask_next[84] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd85 ) begin + free_adr_mask_next[85] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd85 ) begin + free_adr_mask_next[85] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd86 ) begin + free_adr_mask_next[86] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd86 ) begin + free_adr_mask_next[86] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd87 ) begin + free_adr_mask_next[87] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd87 ) begin + free_adr_mask_next[87] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd88 ) begin + free_adr_mask_next[88] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd88 ) begin + free_adr_mask_next[88] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd89 ) begin + free_adr_mask_next[89] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd89 ) begin + free_adr_mask_next[89] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd90 ) begin + free_adr_mask_next[90] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd90 ) begin + free_adr_mask_next[90] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd91 ) begin + free_adr_mask_next[91] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd91 ) begin + free_adr_mask_next[91] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd92 ) begin + free_adr_mask_next[92] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd92 ) begin + free_adr_mask_next[92] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd93 ) begin + free_adr_mask_next[93] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd93 ) begin + free_adr_mask_next[93] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd94 ) begin + free_adr_mask_next[94] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd94 ) begin + free_adr_mask_next[94] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd95 ) begin + free_adr_mask_next[95] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd95 ) begin + free_adr_mask_next[95] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd96 ) begin + free_adr_mask_next[96] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd96 ) begin + free_adr_mask_next[96] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd97 ) begin + free_adr_mask_next[97] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd97 ) begin + free_adr_mask_next[97] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd98 ) begin + free_adr_mask_next[98] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd98 ) begin + free_adr_mask_next[98] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd99 ) begin + free_adr_mask_next[99] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd99 ) begin + free_adr_mask_next[99] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd100 ) begin + free_adr_mask_next[100] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd100 ) begin + free_adr_mask_next[100] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd101 ) begin + free_adr_mask_next[101] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd101 ) begin + free_adr_mask_next[101] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd102 ) begin + free_adr_mask_next[102] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd102 ) begin + free_adr_mask_next[102] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd103 ) begin + free_adr_mask_next[103] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd103 ) begin + free_adr_mask_next[103] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd104 ) begin + free_adr_mask_next[104] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd104 ) begin + free_adr_mask_next[104] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd105 ) begin + free_adr_mask_next[105] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd105 ) begin + free_adr_mask_next[105] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd106 ) begin + free_adr_mask_next[106] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd106 ) begin + free_adr_mask_next[106] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd107 ) begin + free_adr_mask_next[107] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd107 ) begin + free_adr_mask_next[107] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd108 ) begin + free_adr_mask_next[108] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd108 ) begin + free_adr_mask_next[108] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd109 ) begin + free_adr_mask_next[109] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd109 ) begin + free_adr_mask_next[109] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd110 ) begin + free_adr_mask_next[110] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd110 ) begin + free_adr_mask_next[110] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd111 ) begin + free_adr_mask_next[111] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd111 ) begin + free_adr_mask_next[111] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd112 ) begin + free_adr_mask_next[112] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd112 ) begin + free_adr_mask_next[112] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd113 ) begin + free_adr_mask_next[113] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd113 ) begin + free_adr_mask_next[113] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd114 ) begin + free_adr_mask_next[114] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd114 ) begin + free_adr_mask_next[114] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd115 ) begin + free_adr_mask_next[115] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd115 ) begin + free_adr_mask_next[115] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd116 ) begin + free_adr_mask_next[116] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd116 ) begin + free_adr_mask_next[116] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd117 ) begin + free_adr_mask_next[117] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd117 ) begin + free_adr_mask_next[117] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd118 ) begin + free_adr_mask_next[118] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd118 ) begin + free_adr_mask_next[118] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd119 ) begin + free_adr_mask_next[119] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd119 ) begin + free_adr_mask_next[119] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd120 ) begin + free_adr_mask_next[120] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd120 ) begin + free_adr_mask_next[120] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd121 ) begin + free_adr_mask_next[121] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd121 ) begin + free_adr_mask_next[121] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd122 ) begin + free_adr_mask_next[122] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd122 ) begin + free_adr_mask_next[122] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd123 ) begin + free_adr_mask_next[123] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd123 ) begin + free_adr_mask_next[123] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd124 ) begin + free_adr_mask_next[124] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd124 ) begin + free_adr_mask_next[124] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd125 ) begin + free_adr_mask_next[125] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd125 ) begin + free_adr_mask_next[125] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd126 ) begin + free_adr_mask_next[126] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd126 ) begin + free_adr_mask_next[126] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd127 ) begin + free_adr_mask_next[127] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd127 ) begin + free_adr_mask_next[127] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd128 ) begin + free_adr_mask_next[128] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd128 ) begin + free_adr_mask_next[128] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd129 ) begin + free_adr_mask_next[129] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd129 ) begin + free_adr_mask_next[129] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd130 ) begin + free_adr_mask_next[130] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd130 ) begin + free_adr_mask_next[130] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd131 ) begin + free_adr_mask_next[131] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd131 ) begin + free_adr_mask_next[131] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd132 ) begin + free_adr_mask_next[132] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd132 ) begin + free_adr_mask_next[132] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd133 ) begin + free_adr_mask_next[133] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd133 ) begin + free_adr_mask_next[133] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd134 ) begin + free_adr_mask_next[134] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd134 ) begin + free_adr_mask_next[134] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd135 ) begin + free_adr_mask_next[135] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd135 ) begin + free_adr_mask_next[135] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd136 ) begin + free_adr_mask_next[136] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd136 ) begin + free_adr_mask_next[136] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd137 ) begin + free_adr_mask_next[137] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd137 ) begin + free_adr_mask_next[137] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd138 ) begin + free_adr_mask_next[138] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd138 ) begin + free_adr_mask_next[138] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd139 ) begin + free_adr_mask_next[139] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd139 ) begin + free_adr_mask_next[139] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd140 ) begin + free_adr_mask_next[140] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd140 ) begin + free_adr_mask_next[140] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd141 ) begin + free_adr_mask_next[141] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd141 ) begin + free_adr_mask_next[141] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd142 ) begin + free_adr_mask_next[142] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd142 ) begin + free_adr_mask_next[142] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd143 ) begin + free_adr_mask_next[143] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd143 ) begin + free_adr_mask_next[143] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd144 ) begin + free_adr_mask_next[144] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd144 ) begin + free_adr_mask_next[144] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd145 ) begin + free_adr_mask_next[145] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd145 ) begin + free_adr_mask_next[145] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd146 ) begin + free_adr_mask_next[146] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd146 ) begin + free_adr_mask_next[146] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd147 ) begin + free_adr_mask_next[147] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd147 ) begin + free_adr_mask_next[147] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd148 ) begin + free_adr_mask_next[148] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd148 ) begin + free_adr_mask_next[148] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd149 ) begin + free_adr_mask_next[149] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd149 ) begin + free_adr_mask_next[149] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd150 ) begin + free_adr_mask_next[150] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd150 ) begin + free_adr_mask_next[150] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd151 ) begin + free_adr_mask_next[151] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd151 ) begin + free_adr_mask_next[151] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd152 ) begin + free_adr_mask_next[152] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd152 ) begin + free_adr_mask_next[152] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd153 ) begin + free_adr_mask_next[153] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd153 ) begin + free_adr_mask_next[153] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd154 ) begin + free_adr_mask_next[154] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd154 ) begin + free_adr_mask_next[154] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd155 ) begin + free_adr_mask_next[155] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd155 ) begin + free_adr_mask_next[155] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd156 ) begin + free_adr_mask_next[156] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd156 ) begin + free_adr_mask_next[156] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd157 ) begin + free_adr_mask_next[157] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd157 ) begin + free_adr_mask_next[157] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd158 ) begin + free_adr_mask_next[158] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd158 ) begin + free_adr_mask_next[158] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd159 ) begin + free_adr_mask_next[159] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd159 ) begin + free_adr_mask_next[159] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd160 ) begin + free_adr_mask_next[160] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd160 ) begin + free_adr_mask_next[160] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd161 ) begin + free_adr_mask_next[161] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd161 ) begin + free_adr_mask_next[161] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd162 ) begin + free_adr_mask_next[162] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd162 ) begin + free_adr_mask_next[162] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd163 ) begin + free_adr_mask_next[163] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd163 ) begin + free_adr_mask_next[163] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd164 ) begin + free_adr_mask_next[164] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd164 ) begin + free_adr_mask_next[164] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd165 ) begin + free_adr_mask_next[165] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd165 ) begin + free_adr_mask_next[165] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd166 ) begin + free_adr_mask_next[166] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd166 ) begin + free_adr_mask_next[166] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd167 ) begin + free_adr_mask_next[167] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd167 ) begin + free_adr_mask_next[167] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd168 ) begin + free_adr_mask_next[168] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd168 ) begin + free_adr_mask_next[168] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd169 ) begin + free_adr_mask_next[169] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd169 ) begin + free_adr_mask_next[169] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd170 ) begin + free_adr_mask_next[170] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd170 ) begin + free_adr_mask_next[170] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd171 ) begin + free_adr_mask_next[171] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd171 ) begin + free_adr_mask_next[171] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd172 ) begin + free_adr_mask_next[172] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd172 ) begin + free_adr_mask_next[172] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd173 ) begin + free_adr_mask_next[173] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd173 ) begin + free_adr_mask_next[173] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd174 ) begin + free_adr_mask_next[174] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd174 ) begin + free_adr_mask_next[174] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd175 ) begin + free_adr_mask_next[175] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd175 ) begin + free_adr_mask_next[175] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd176 ) begin + free_adr_mask_next[176] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd176 ) begin + free_adr_mask_next[176] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd177 ) begin + free_adr_mask_next[177] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd177 ) begin + free_adr_mask_next[177] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd178 ) begin + free_adr_mask_next[178] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd178 ) begin + free_adr_mask_next[178] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd179 ) begin + free_adr_mask_next[179] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd179 ) begin + free_adr_mask_next[179] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd180 ) begin + free_adr_mask_next[180] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd180 ) begin + free_adr_mask_next[180] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd181 ) begin + free_adr_mask_next[181] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd181 ) begin + free_adr_mask_next[181] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd182 ) begin + free_adr_mask_next[182] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd182 ) begin + free_adr_mask_next[182] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd183 ) begin + free_adr_mask_next[183] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd183 ) begin + free_adr_mask_next[183] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd184 ) begin + free_adr_mask_next[184] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd184 ) begin + free_adr_mask_next[184] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd185 ) begin + free_adr_mask_next[185] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd185 ) begin + free_adr_mask_next[185] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd186 ) begin + free_adr_mask_next[186] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd186 ) begin + free_adr_mask_next[186] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd187 ) begin + free_adr_mask_next[187] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd187 ) begin + free_adr_mask_next[187] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd188 ) begin + free_adr_mask_next[188] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd188 ) begin + free_adr_mask_next[188] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd189 ) begin + free_adr_mask_next[189] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd189 ) begin + free_adr_mask_next[189] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd190 ) begin + free_adr_mask_next[190] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd190 ) begin + free_adr_mask_next[190] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd191 ) begin + free_adr_mask_next[191] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd191 ) begin + free_adr_mask_next[191] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd192 ) begin + free_adr_mask_next[192] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd192 ) begin + free_adr_mask_next[192] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd193 ) begin + free_adr_mask_next[193] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd193 ) begin + free_adr_mask_next[193] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd194 ) begin + free_adr_mask_next[194] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd194 ) begin + free_adr_mask_next[194] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd195 ) begin + free_adr_mask_next[195] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd195 ) begin + free_adr_mask_next[195] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd196 ) begin + free_adr_mask_next[196] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd196 ) begin + free_adr_mask_next[196] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd197 ) begin + free_adr_mask_next[197] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd197 ) begin + free_adr_mask_next[197] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd198 ) begin + free_adr_mask_next[198] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd198 ) begin + free_adr_mask_next[198] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd199 ) begin + free_adr_mask_next[199] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd199 ) begin + free_adr_mask_next[199] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd200 ) begin + free_adr_mask_next[200] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd200 ) begin + free_adr_mask_next[200] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd201 ) begin + free_adr_mask_next[201] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd201 ) begin + free_adr_mask_next[201] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd202 ) begin + free_adr_mask_next[202] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd202 ) begin + free_adr_mask_next[202] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd203 ) begin + free_adr_mask_next[203] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd203 ) begin + free_adr_mask_next[203] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd204 ) begin + free_adr_mask_next[204] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd204 ) begin + free_adr_mask_next[204] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd205 ) begin + free_adr_mask_next[205] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd205 ) begin + free_adr_mask_next[205] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd206 ) begin + free_adr_mask_next[206] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd206 ) begin + free_adr_mask_next[206] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd207 ) begin + free_adr_mask_next[207] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd207 ) begin + free_adr_mask_next[207] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd208 ) begin + free_adr_mask_next[208] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd208 ) begin + free_adr_mask_next[208] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd209 ) begin + free_adr_mask_next[209] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd209 ) begin + free_adr_mask_next[209] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd210 ) begin + free_adr_mask_next[210] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd210 ) begin + free_adr_mask_next[210] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd211 ) begin + free_adr_mask_next[211] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd211 ) begin + free_adr_mask_next[211] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd212 ) begin + free_adr_mask_next[212] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd212 ) begin + free_adr_mask_next[212] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd213 ) begin + free_adr_mask_next[213] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd213 ) begin + free_adr_mask_next[213] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd214 ) begin + free_adr_mask_next[214] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd214 ) begin + free_adr_mask_next[214] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd215 ) begin + free_adr_mask_next[215] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd215 ) begin + free_adr_mask_next[215] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd216 ) begin + free_adr_mask_next[216] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd216 ) begin + free_adr_mask_next[216] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd217 ) begin + free_adr_mask_next[217] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd217 ) begin + free_adr_mask_next[217] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd218 ) begin + free_adr_mask_next[218] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd218 ) begin + free_adr_mask_next[218] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd219 ) begin + free_adr_mask_next[219] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd219 ) begin + free_adr_mask_next[219] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd220 ) begin + free_adr_mask_next[220] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd220 ) begin + free_adr_mask_next[220] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd221 ) begin + free_adr_mask_next[221] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd221 ) begin + free_adr_mask_next[221] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd222 ) begin + free_adr_mask_next[222] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd222 ) begin + free_adr_mask_next[222] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd223 ) begin + free_adr_mask_next[223] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd223 ) begin + free_adr_mask_next[223] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd224 ) begin + free_adr_mask_next[224] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd224 ) begin + free_adr_mask_next[224] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd225 ) begin + free_adr_mask_next[225] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd225 ) begin + free_adr_mask_next[225] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd226 ) begin + free_adr_mask_next[226] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd226 ) begin + free_adr_mask_next[226] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd227 ) begin + free_adr_mask_next[227] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd227 ) begin + free_adr_mask_next[227] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd228 ) begin + free_adr_mask_next[228] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd228 ) begin + free_adr_mask_next[228] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd229 ) begin + free_adr_mask_next[229] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd229 ) begin + free_adr_mask_next[229] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd230 ) begin + free_adr_mask_next[230] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd230 ) begin + free_adr_mask_next[230] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd231 ) begin + free_adr_mask_next[231] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd231 ) begin + free_adr_mask_next[231] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd232 ) begin + free_adr_mask_next[232] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd232 ) begin + free_adr_mask_next[232] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd233 ) begin + free_adr_mask_next[233] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd233 ) begin + free_adr_mask_next[233] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd234 ) begin + free_adr_mask_next[234] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd234 ) begin + free_adr_mask_next[234] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd235 ) begin + free_adr_mask_next[235] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd235 ) begin + free_adr_mask_next[235] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd236 ) begin + free_adr_mask_next[236] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd236 ) begin + free_adr_mask_next[236] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd237 ) begin + free_adr_mask_next[237] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd237 ) begin + free_adr_mask_next[237] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd238 ) begin + free_adr_mask_next[238] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd238 ) begin + free_adr_mask_next[238] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd239 ) begin + free_adr_mask_next[239] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd239 ) begin + free_adr_mask_next[239] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd240 ) begin + free_adr_mask_next[240] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd240 ) begin + free_adr_mask_next[240] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd241 ) begin + free_adr_mask_next[241] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd241 ) begin + free_adr_mask_next[241] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd242 ) begin + free_adr_mask_next[242] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd242 ) begin + free_adr_mask_next[242] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd243 ) begin + free_adr_mask_next[243] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd243 ) begin + free_adr_mask_next[243] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd244 ) begin + free_adr_mask_next[244] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd244 ) begin + free_adr_mask_next[244] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd245 ) begin + free_adr_mask_next[245] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd245 ) begin + free_adr_mask_next[245] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd246 ) begin + free_adr_mask_next[246] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd246 ) begin + free_adr_mask_next[246] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd247 ) begin + free_adr_mask_next[247] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd247 ) begin + free_adr_mask_next[247] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd248 ) begin + free_adr_mask_next[248] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd248 ) begin + free_adr_mask_next[248] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd249 ) begin + free_adr_mask_next[249] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd249 ) begin + free_adr_mask_next[249] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd250 ) begin + free_adr_mask_next[250] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd250 ) begin + free_adr_mask_next[250] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd251 ) begin + free_adr_mask_next[251] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd251 ) begin + free_adr_mask_next[251] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd252 ) begin + free_adr_mask_next[252] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd252 ) begin + free_adr_mask_next[252] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd253 ) begin + free_adr_mask_next[253] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd253 ) begin + free_adr_mask_next[253] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd254 ) begin + free_adr_mask_next[254] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd254 ) begin + free_adr_mask_next[254] = 1'b0; + end +end +wire flag_l0_0 = free_adr_mask[1] | free_adr_mask[0]; +wire flag_l0_1 = free_adr_mask[3] | free_adr_mask[2]; +wire flag_l0_2 = free_adr_mask[5] | free_adr_mask[4]; +wire flag_l0_3 = free_adr_mask[7] | free_adr_mask[6]; +wire flag_l0_4 = free_adr_mask[9] | free_adr_mask[8]; +wire flag_l0_5 = free_adr_mask[11] | free_adr_mask[10]; +wire flag_l0_6 = free_adr_mask[13] | free_adr_mask[12]; +wire flag_l0_7 = free_adr_mask[15] | free_adr_mask[14]; +wire flag_l0_8 = free_adr_mask[17] | free_adr_mask[16]; +wire flag_l0_9 = free_adr_mask[19] | free_adr_mask[18]; +wire flag_l0_10 = free_adr_mask[21] | free_adr_mask[20]; +wire flag_l0_11 = free_adr_mask[23] | free_adr_mask[22]; +wire flag_l0_12 = free_adr_mask[25] | free_adr_mask[24]; +wire flag_l0_13 = free_adr_mask[27] | free_adr_mask[26]; +wire flag_l0_14 = free_adr_mask[29] | free_adr_mask[28]; +wire flag_l0_15 = free_adr_mask[31] | free_adr_mask[30]; +wire flag_l0_16 = free_adr_mask[33] | free_adr_mask[32]; +wire flag_l0_17 = free_adr_mask[35] | free_adr_mask[34]; +wire flag_l0_18 = free_adr_mask[37] | free_adr_mask[36]; +wire flag_l0_19 = free_adr_mask[39] | free_adr_mask[38]; +wire flag_l0_20 = free_adr_mask[41] | free_adr_mask[40]; +wire flag_l0_21 = free_adr_mask[43] | free_adr_mask[42]; +wire flag_l0_22 = free_adr_mask[45] | free_adr_mask[44]; +wire flag_l0_23 = free_adr_mask[47] | free_adr_mask[46]; +wire flag_l0_24 = free_adr_mask[49] | free_adr_mask[48]; +wire flag_l0_25 = free_adr_mask[51] | free_adr_mask[50]; +wire flag_l0_26 = free_adr_mask[53] | free_adr_mask[52]; +wire flag_l0_27 = free_adr_mask[55] | free_adr_mask[54]; +wire flag_l0_28 = free_adr_mask[57] | free_adr_mask[56]; +wire flag_l0_29 = free_adr_mask[59] | free_adr_mask[58]; +wire flag_l0_30 = free_adr_mask[61] | free_adr_mask[60]; +wire flag_l0_31 = free_adr_mask[63] | free_adr_mask[62]; +wire flag_l0_32 = free_adr_mask[65] | free_adr_mask[64]; +wire flag_l0_33 = free_adr_mask[67] | free_adr_mask[66]; +wire flag_l0_34 = free_adr_mask[69] | free_adr_mask[68]; +wire flag_l0_35 = free_adr_mask[71] | free_adr_mask[70]; +wire flag_l0_36 = free_adr_mask[73] | free_adr_mask[72]; +wire flag_l0_37 = free_adr_mask[75] | free_adr_mask[74]; +wire flag_l0_38 = free_adr_mask[77] | free_adr_mask[76]; +wire flag_l0_39 = free_adr_mask[79] | free_adr_mask[78]; +wire flag_l0_40 = free_adr_mask[81] | free_adr_mask[80]; +wire flag_l0_41 = free_adr_mask[83] | free_adr_mask[82]; +wire flag_l0_42 = free_adr_mask[85] | free_adr_mask[84]; +wire flag_l0_43 = free_adr_mask[87] | free_adr_mask[86]; +wire flag_l0_44 = free_adr_mask[89] | free_adr_mask[88]; +wire flag_l0_45 = free_adr_mask[91] | free_adr_mask[90]; +wire flag_l0_46 = free_adr_mask[93] | free_adr_mask[92]; +wire flag_l0_47 = free_adr_mask[95] | free_adr_mask[94]; +wire flag_l0_48 = free_adr_mask[97] | free_adr_mask[96]; +wire flag_l0_49 = free_adr_mask[99] | free_adr_mask[98]; +wire flag_l0_50 = free_adr_mask[101] | free_adr_mask[100]; +wire flag_l0_51 = free_adr_mask[103] | free_adr_mask[102]; +wire flag_l0_52 = free_adr_mask[105] | free_adr_mask[104]; +wire flag_l0_53 = free_adr_mask[107] | free_adr_mask[106]; +wire flag_l0_54 = free_adr_mask[109] | free_adr_mask[108]; +wire flag_l0_55 = free_adr_mask[111] | free_adr_mask[110]; +wire flag_l0_56 = free_adr_mask[113] | free_adr_mask[112]; +wire flag_l0_57 = free_adr_mask[115] | free_adr_mask[114]; +wire flag_l0_58 = free_adr_mask[117] | free_adr_mask[116]; +wire flag_l0_59 = free_adr_mask[119] | free_adr_mask[118]; +wire flag_l0_60 = free_adr_mask[121] | free_adr_mask[120]; +wire flag_l0_61 = free_adr_mask[123] | free_adr_mask[122]; +wire flag_l0_62 = free_adr_mask[125] | free_adr_mask[124]; +wire flag_l0_63 = free_adr_mask[127] | free_adr_mask[126]; +wire flag_l0_64 = free_adr_mask[129] | free_adr_mask[128]; +wire flag_l0_65 = free_adr_mask[131] | free_adr_mask[130]; +wire flag_l0_66 = free_adr_mask[133] | free_adr_mask[132]; +wire flag_l0_67 = free_adr_mask[135] | free_adr_mask[134]; +wire flag_l0_68 = free_adr_mask[137] | free_adr_mask[136]; +wire flag_l0_69 = free_adr_mask[139] | free_adr_mask[138]; +wire flag_l0_70 = free_adr_mask[141] | free_adr_mask[140]; +wire flag_l0_71 = free_adr_mask[143] | free_adr_mask[142]; +wire flag_l0_72 = free_adr_mask[145] | free_adr_mask[144]; +wire flag_l0_73 = free_adr_mask[147] | free_adr_mask[146]; +wire flag_l0_74 = free_adr_mask[149] | free_adr_mask[148]; +wire flag_l0_75 = free_adr_mask[151] | free_adr_mask[150]; +wire flag_l0_76 = free_adr_mask[153] | free_adr_mask[152]; +wire flag_l0_77 = free_adr_mask[155] | free_adr_mask[154]; +wire flag_l0_78 = free_adr_mask[157] | free_adr_mask[156]; +wire flag_l0_79 = free_adr_mask[159] | free_adr_mask[158]; +wire flag_l0_80 = free_adr_mask[161] | free_adr_mask[160]; +wire flag_l0_81 = free_adr_mask[163] | free_adr_mask[162]; +wire flag_l0_82 = free_adr_mask[165] | free_adr_mask[164]; +wire flag_l0_83 = free_adr_mask[167] | free_adr_mask[166]; +wire flag_l0_84 = free_adr_mask[169] | free_adr_mask[168]; +wire flag_l0_85 = free_adr_mask[171] | free_adr_mask[170]; +wire flag_l0_86 = free_adr_mask[173] | free_adr_mask[172]; +wire flag_l0_87 = free_adr_mask[175] | free_adr_mask[174]; +wire flag_l0_88 = free_adr_mask[177] | free_adr_mask[176]; +wire flag_l0_89 = free_adr_mask[179] | free_adr_mask[178]; +wire flag_l0_90 = free_adr_mask[181] | free_adr_mask[180]; +wire flag_l0_91 = free_adr_mask[183] | free_adr_mask[182]; +wire flag_l0_92 = free_adr_mask[185] | free_adr_mask[184]; +wire flag_l0_93 = free_adr_mask[187] | free_adr_mask[186]; +wire flag_l0_94 = free_adr_mask[189] | free_adr_mask[188]; +wire flag_l0_95 = free_adr_mask[191] | free_adr_mask[190]; +wire flag_l0_96 = free_adr_mask[193] | free_adr_mask[192]; +wire flag_l0_97 = free_adr_mask[195] | free_adr_mask[194]; +wire flag_l0_98 = free_adr_mask[197] | free_adr_mask[196]; +wire flag_l0_99 = free_adr_mask[199] | free_adr_mask[198]; +wire flag_l0_100 = free_adr_mask[201] | free_adr_mask[200]; +wire flag_l0_101 = free_adr_mask[203] | free_adr_mask[202]; +wire flag_l0_102 = free_adr_mask[205] | free_adr_mask[204]; +wire flag_l0_103 = free_adr_mask[207] | free_adr_mask[206]; +wire flag_l0_104 = free_adr_mask[209] | free_adr_mask[208]; +wire flag_l0_105 = free_adr_mask[211] | free_adr_mask[210]; +wire flag_l0_106 = free_adr_mask[213] | free_adr_mask[212]; +wire flag_l0_107 = free_adr_mask[215] | free_adr_mask[214]; +wire flag_l0_108 = free_adr_mask[217] | free_adr_mask[216]; +wire flag_l0_109 = free_adr_mask[219] | free_adr_mask[218]; +wire flag_l0_110 = free_adr_mask[221] | free_adr_mask[220]; +wire flag_l0_111 = free_adr_mask[223] | free_adr_mask[222]; +wire flag_l0_112 = free_adr_mask[225] | free_adr_mask[224]; +wire flag_l0_113 = free_adr_mask[227] | free_adr_mask[226]; +wire flag_l0_114 = free_adr_mask[229] | free_adr_mask[228]; +wire flag_l0_115 = free_adr_mask[231] | free_adr_mask[230]; +wire flag_l0_116 = free_adr_mask[233] | free_adr_mask[232]; +wire flag_l0_117 = free_adr_mask[235] | free_adr_mask[234]; +wire flag_l0_118 = free_adr_mask[237] | free_adr_mask[236]; +wire flag_l0_119 = free_adr_mask[239] | free_adr_mask[238]; +wire flag_l0_120 = free_adr_mask[241] | free_adr_mask[240]; +wire flag_l0_121 = free_adr_mask[243] | free_adr_mask[242]; +wire flag_l0_122 = free_adr_mask[245] | free_adr_mask[244]; +wire flag_l0_123 = free_adr_mask[247] | free_adr_mask[246]; +wire flag_l0_124 = free_adr_mask[249] | free_adr_mask[248]; +wire flag_l0_125 = free_adr_mask[251] | free_adr_mask[250]; +wire flag_l0_126 = free_adr_mask[253] | free_adr_mask[252]; +wire flag_l1_0 = flag_l0_1 | flag_l0_0; +wire flag_l1_1 = flag_l0_3 | flag_l0_2; +wire flag_l1_2 = flag_l0_5 | flag_l0_4; +wire flag_l1_3 = flag_l0_7 | flag_l0_6; +wire flag_l1_4 = flag_l0_9 | flag_l0_8; +wire flag_l1_5 = flag_l0_11 | flag_l0_10; +wire flag_l1_6 = flag_l0_13 | flag_l0_12; +wire flag_l1_7 = flag_l0_15 | flag_l0_14; +wire flag_l1_8 = flag_l0_17 | flag_l0_16; +wire flag_l1_9 = flag_l0_19 | flag_l0_18; +wire flag_l1_10 = flag_l0_21 | flag_l0_20; +wire flag_l1_11 = flag_l0_23 | flag_l0_22; +wire flag_l1_12 = flag_l0_25 | flag_l0_24; +wire flag_l1_13 = flag_l0_27 | flag_l0_26; +wire flag_l1_14 = flag_l0_29 | flag_l0_28; +wire flag_l1_15 = flag_l0_31 | flag_l0_30; +wire flag_l1_16 = flag_l0_33 | flag_l0_32; +wire flag_l1_17 = flag_l0_35 | flag_l0_34; +wire flag_l1_18 = flag_l0_37 | flag_l0_36; +wire flag_l1_19 = flag_l0_39 | flag_l0_38; +wire flag_l1_20 = flag_l0_41 | flag_l0_40; +wire flag_l1_21 = flag_l0_43 | flag_l0_42; +wire flag_l1_22 = flag_l0_45 | flag_l0_44; +wire flag_l1_23 = flag_l0_47 | flag_l0_46; +wire flag_l1_24 = flag_l0_49 | flag_l0_48; +wire flag_l1_25 = flag_l0_51 | flag_l0_50; +wire flag_l1_26 = flag_l0_53 | flag_l0_52; +wire flag_l1_27 = flag_l0_55 | flag_l0_54; +wire flag_l1_28 = flag_l0_57 | flag_l0_56; +wire flag_l1_29 = flag_l0_59 | flag_l0_58; +wire flag_l1_30 = flag_l0_61 | flag_l0_60; +wire flag_l1_31 = flag_l0_63 | flag_l0_62; +wire flag_l1_32 = flag_l0_65 | flag_l0_64; +wire flag_l1_33 = flag_l0_67 | flag_l0_66; +wire flag_l1_34 = flag_l0_69 | flag_l0_68; +wire flag_l1_35 = flag_l0_71 | flag_l0_70; +wire flag_l1_36 = flag_l0_73 | flag_l0_72; +wire flag_l1_37 = flag_l0_75 | flag_l0_74; +wire flag_l1_38 = flag_l0_77 | flag_l0_76; +wire flag_l1_39 = flag_l0_79 | flag_l0_78; +wire flag_l1_40 = flag_l0_81 | flag_l0_80; +wire flag_l1_41 = flag_l0_83 | flag_l0_82; +wire flag_l1_42 = flag_l0_85 | flag_l0_84; +wire flag_l1_43 = flag_l0_87 | flag_l0_86; +wire flag_l1_44 = flag_l0_89 | flag_l0_88; +wire flag_l1_45 = flag_l0_91 | flag_l0_90; +wire flag_l1_46 = flag_l0_93 | flag_l0_92; +wire flag_l1_47 = flag_l0_95 | flag_l0_94; +wire flag_l1_48 = flag_l0_97 | flag_l0_96; +wire flag_l1_49 = flag_l0_99 | flag_l0_98; +wire flag_l1_50 = flag_l0_101 | flag_l0_100; +wire flag_l1_51 = flag_l0_103 | flag_l0_102; +wire flag_l1_52 = flag_l0_105 | flag_l0_104; +wire flag_l1_53 = flag_l0_107 | flag_l0_106; +wire flag_l1_54 = flag_l0_109 | flag_l0_108; +wire flag_l1_55 = flag_l0_111 | flag_l0_110; +wire flag_l1_56 = flag_l0_113 | flag_l0_112; +wire flag_l1_57 = flag_l0_115 | flag_l0_114; +wire flag_l1_58 = flag_l0_117 | flag_l0_116; +wire flag_l1_59 = flag_l0_119 | flag_l0_118; +wire flag_l1_60 = flag_l0_121 | flag_l0_120; +wire flag_l1_61 = flag_l0_123 | flag_l0_122; +wire flag_l1_62 = flag_l0_125 | flag_l0_124; +wire flag_l2_0 = flag_l1_1 | flag_l1_0; +wire flag_l2_1 = flag_l1_3 | flag_l1_2; +wire flag_l2_2 = flag_l1_5 | flag_l1_4; +wire flag_l2_3 = flag_l1_7 | flag_l1_6; +wire flag_l2_4 = flag_l1_9 | flag_l1_8; +wire flag_l2_5 = flag_l1_11 | flag_l1_10; +wire flag_l2_6 = flag_l1_13 | flag_l1_12; +wire flag_l2_7 = flag_l1_15 | flag_l1_14; +wire flag_l2_8 = flag_l1_17 | flag_l1_16; +wire flag_l2_9 = flag_l1_19 | flag_l1_18; +wire flag_l2_10 = flag_l1_21 | flag_l1_20; +wire flag_l2_11 = flag_l1_23 | flag_l1_22; +wire flag_l2_12 = flag_l1_25 | flag_l1_24; +wire flag_l2_13 = flag_l1_27 | flag_l1_26; +wire flag_l2_14 = flag_l1_29 | flag_l1_28; +wire flag_l2_15 = flag_l1_31 | flag_l1_30; +wire flag_l2_16 = flag_l1_33 | flag_l1_32; +wire flag_l2_17 = flag_l1_35 | flag_l1_34; +wire flag_l2_18 = flag_l1_37 | flag_l1_36; +wire flag_l2_19 = flag_l1_39 | flag_l1_38; +wire flag_l2_20 = flag_l1_41 | flag_l1_40; +wire flag_l2_21 = flag_l1_43 | flag_l1_42; +wire flag_l2_22 = flag_l1_45 | flag_l1_44; +wire flag_l2_23 = flag_l1_47 | flag_l1_46; +wire flag_l2_24 = flag_l1_49 | flag_l1_48; +wire flag_l2_25 = flag_l1_51 | flag_l1_50; +wire flag_l2_26 = flag_l1_53 | flag_l1_52; +wire flag_l2_27 = flag_l1_55 | flag_l1_54; +wire flag_l2_28 = flag_l1_57 | flag_l1_56; +wire flag_l2_29 = flag_l1_59 | flag_l1_58; +wire flag_l2_30 = flag_l1_61 | flag_l1_60; +wire flag_l3_0 = flag_l2_1 | flag_l2_0; +wire flag_l3_1 = flag_l2_3 | flag_l2_2; +wire flag_l3_2 = flag_l2_5 | flag_l2_4; +wire flag_l3_3 = flag_l2_7 | flag_l2_6; +wire flag_l3_4 = flag_l2_9 | flag_l2_8; +wire flag_l3_5 = flag_l2_11 | flag_l2_10; +wire flag_l3_6 = flag_l2_13 | flag_l2_12; +wire flag_l3_7 = flag_l2_15 | flag_l2_14; +wire flag_l3_8 = flag_l2_17 | flag_l2_16; +wire flag_l3_9 = flag_l2_19 | flag_l2_18; +wire flag_l3_10 = flag_l2_21 | flag_l2_20; +wire flag_l3_11 = flag_l2_23 | flag_l2_22; +wire flag_l3_12 = flag_l2_25 | flag_l2_24; +wire flag_l3_13 = flag_l2_27 | flag_l2_26; +wire flag_l3_14 = flag_l2_29 | flag_l2_28; +wire flag_l4_0 = flag_l3_1 | flag_l3_0; +wire flag_l4_1 = flag_l3_3 | flag_l3_2; +wire flag_l4_2 = flag_l3_5 | flag_l3_4; +wire flag_l4_3 = flag_l3_7 | flag_l3_6; +wire flag_l4_4 = flag_l3_9 | flag_l3_8; +wire flag_l4_5 = flag_l3_11 | flag_l3_10; +wire flag_l4_6 = flag_l3_13 | flag_l3_12; +wire flag_l5_0 = flag_l4_1 | flag_l4_0; +wire flag_l5_1 = flag_l4_3 | flag_l4_2; +wire flag_l5_2 = flag_l4_5 | flag_l4_4; +wire flag_l6_0 = flag_l5_1 | flag_l5_0; +wire index_l0_0 = !free_adr_mask[0]; +wire index_l0_1 = !free_adr_mask[2]; +wire index_l0_2 = !free_adr_mask[4]; +wire index_l0_3 = !free_adr_mask[6]; +wire index_l0_4 = !free_adr_mask[8]; +wire index_l0_5 = !free_adr_mask[10]; +wire index_l0_6 = !free_adr_mask[12]; +wire index_l0_7 = !free_adr_mask[14]; +wire index_l0_8 = !free_adr_mask[16]; +wire index_l0_9 = !free_adr_mask[18]; +wire index_l0_10 = !free_adr_mask[20]; +wire index_l0_11 = !free_adr_mask[22]; +wire index_l0_12 = !free_adr_mask[24]; +wire index_l0_13 = !free_adr_mask[26]; +wire index_l0_14 = !free_adr_mask[28]; +wire index_l0_15 = !free_adr_mask[30]; +wire index_l0_16 = !free_adr_mask[32]; +wire index_l0_17 = !free_adr_mask[34]; +wire index_l0_18 = !free_adr_mask[36]; +wire index_l0_19 = !free_adr_mask[38]; +wire index_l0_20 = !free_adr_mask[40]; +wire index_l0_21 = !free_adr_mask[42]; +wire index_l0_22 = !free_adr_mask[44]; +wire index_l0_23 = !free_adr_mask[46]; +wire index_l0_24 = !free_adr_mask[48]; +wire index_l0_25 = !free_adr_mask[50]; +wire index_l0_26 = !free_adr_mask[52]; +wire index_l0_27 = !free_adr_mask[54]; +wire index_l0_28 = !free_adr_mask[56]; +wire index_l0_29 = !free_adr_mask[58]; +wire index_l0_30 = !free_adr_mask[60]; +wire index_l0_31 = !free_adr_mask[62]; +wire index_l0_32 = !free_adr_mask[64]; +wire index_l0_33 = !free_adr_mask[66]; +wire index_l0_34 = !free_adr_mask[68]; +wire index_l0_35 = !free_adr_mask[70]; +wire index_l0_36 = !free_adr_mask[72]; +wire index_l0_37 = !free_adr_mask[74]; +wire index_l0_38 = !free_adr_mask[76]; +wire index_l0_39 = !free_adr_mask[78]; +wire index_l0_40 = !free_adr_mask[80]; +wire index_l0_41 = !free_adr_mask[82]; +wire index_l0_42 = !free_adr_mask[84]; +wire index_l0_43 = !free_adr_mask[86]; +wire index_l0_44 = !free_adr_mask[88]; +wire index_l0_45 = !free_adr_mask[90]; +wire index_l0_46 = !free_adr_mask[92]; +wire index_l0_47 = !free_adr_mask[94]; +wire index_l0_48 = !free_adr_mask[96]; +wire index_l0_49 = !free_adr_mask[98]; +wire index_l0_50 = !free_adr_mask[100]; +wire index_l0_51 = !free_adr_mask[102]; +wire index_l0_52 = !free_adr_mask[104]; +wire index_l0_53 = !free_adr_mask[106]; +wire index_l0_54 = !free_adr_mask[108]; +wire index_l0_55 = !free_adr_mask[110]; +wire index_l0_56 = !free_adr_mask[112]; +wire index_l0_57 = !free_adr_mask[114]; +wire index_l0_58 = !free_adr_mask[116]; +wire index_l0_59 = !free_adr_mask[118]; +wire index_l0_60 = !free_adr_mask[120]; +wire index_l0_61 = !free_adr_mask[122]; +wire index_l0_62 = !free_adr_mask[124]; +wire index_l0_63 = !free_adr_mask[126]; +wire index_l0_64 = !free_adr_mask[128]; +wire index_l0_65 = !free_adr_mask[130]; +wire index_l0_66 = !free_adr_mask[132]; +wire index_l0_67 = !free_adr_mask[134]; +wire index_l0_68 = !free_adr_mask[136]; +wire index_l0_69 = !free_adr_mask[138]; +wire index_l0_70 = !free_adr_mask[140]; +wire index_l0_71 = !free_adr_mask[142]; +wire index_l0_72 = !free_adr_mask[144]; +wire index_l0_73 = !free_adr_mask[146]; +wire index_l0_74 = !free_adr_mask[148]; +wire index_l0_75 = !free_adr_mask[150]; +wire index_l0_76 = !free_adr_mask[152]; +wire index_l0_77 = !free_adr_mask[154]; +wire index_l0_78 = !free_adr_mask[156]; +wire index_l0_79 = !free_adr_mask[158]; +wire index_l0_80 = !free_adr_mask[160]; +wire index_l0_81 = !free_adr_mask[162]; +wire index_l0_82 = !free_adr_mask[164]; +wire index_l0_83 = !free_adr_mask[166]; +wire index_l0_84 = !free_adr_mask[168]; +wire index_l0_85 = !free_adr_mask[170]; +wire index_l0_86 = !free_adr_mask[172]; +wire index_l0_87 = !free_adr_mask[174]; +wire index_l0_88 = !free_adr_mask[176]; +wire index_l0_89 = !free_adr_mask[178]; +wire index_l0_90 = !free_adr_mask[180]; +wire index_l0_91 = !free_adr_mask[182]; +wire index_l0_92 = !free_adr_mask[184]; +wire index_l0_93 = !free_adr_mask[186]; +wire index_l0_94 = !free_adr_mask[188]; +wire index_l0_95 = !free_adr_mask[190]; +wire index_l0_96 = !free_adr_mask[192]; +wire index_l0_97 = !free_adr_mask[194]; +wire index_l0_98 = !free_adr_mask[196]; +wire index_l0_99 = !free_adr_mask[198]; +wire index_l0_100 = !free_adr_mask[200]; +wire index_l0_101 = !free_adr_mask[202]; +wire index_l0_102 = !free_adr_mask[204]; +wire index_l0_103 = !free_adr_mask[206]; +wire index_l0_104 = !free_adr_mask[208]; +wire index_l0_105 = !free_adr_mask[210]; +wire index_l0_106 = !free_adr_mask[212]; +wire index_l0_107 = !free_adr_mask[214]; +wire index_l0_108 = !free_adr_mask[216]; +wire index_l0_109 = !free_adr_mask[218]; +wire index_l0_110 = !free_adr_mask[220]; +wire index_l0_111 = !free_adr_mask[222]; +wire index_l0_112 = !free_adr_mask[224]; +wire index_l0_113 = !free_adr_mask[226]; +wire index_l0_114 = !free_adr_mask[228]; +wire index_l0_115 = !free_adr_mask[230]; +wire index_l0_116 = !free_adr_mask[232]; +wire index_l0_117 = !free_adr_mask[234]; +wire index_l0_118 = !free_adr_mask[236]; +wire index_l0_119 = !free_adr_mask[238]; +wire index_l0_120 = !free_adr_mask[240]; +wire index_l0_121 = !free_adr_mask[242]; +wire index_l0_122 = !free_adr_mask[244]; +wire index_l0_123 = !free_adr_mask[246]; +wire index_l0_124 = !free_adr_mask[248]; +wire index_l0_125 = !free_adr_mask[250]; +wire index_l0_126 = !free_adr_mask[252]; +wire index_l0_127 = !free_adr_mask[254]; +wire [1:0] index_l1_0 = {!flag_l0_0,(flag_l0_0?index_l0_0:index_l0_1)}; +wire [1:0] index_l1_1 = {!flag_l0_2,(flag_l0_2?index_l0_2:index_l0_3)}; +wire [1:0] index_l1_2 = {!flag_l0_4,(flag_l0_4?index_l0_4:index_l0_5)}; +wire [1:0] index_l1_3 = {!flag_l0_6,(flag_l0_6?index_l0_6:index_l0_7)}; +wire [1:0] index_l1_4 = {!flag_l0_8,(flag_l0_8?index_l0_8:index_l0_9)}; +wire [1:0] index_l1_5 = {!flag_l0_10,(flag_l0_10?index_l0_10:index_l0_11)}; +wire [1:0] index_l1_6 = {!flag_l0_12,(flag_l0_12?index_l0_12:index_l0_13)}; +wire [1:0] index_l1_7 = {!flag_l0_14,(flag_l0_14?index_l0_14:index_l0_15)}; +wire [1:0] index_l1_8 = {!flag_l0_16,(flag_l0_16?index_l0_16:index_l0_17)}; +wire [1:0] index_l1_9 = {!flag_l0_18,(flag_l0_18?index_l0_18:index_l0_19)}; +wire [1:0] index_l1_10 = {!flag_l0_20,(flag_l0_20?index_l0_20:index_l0_21)}; +wire [1:0] index_l1_11 = {!flag_l0_22,(flag_l0_22?index_l0_22:index_l0_23)}; +wire [1:0] index_l1_12 = {!flag_l0_24,(flag_l0_24?index_l0_24:index_l0_25)}; +wire [1:0] index_l1_13 = {!flag_l0_26,(flag_l0_26?index_l0_26:index_l0_27)}; +wire [1:0] index_l1_14 = {!flag_l0_28,(flag_l0_28?index_l0_28:index_l0_29)}; +wire [1:0] index_l1_15 = {!flag_l0_30,(flag_l0_30?index_l0_30:index_l0_31)}; +wire [1:0] index_l1_16 = {!flag_l0_32,(flag_l0_32?index_l0_32:index_l0_33)}; +wire [1:0] index_l1_17 = {!flag_l0_34,(flag_l0_34?index_l0_34:index_l0_35)}; +wire [1:0] index_l1_18 = {!flag_l0_36,(flag_l0_36?index_l0_36:index_l0_37)}; +wire [1:0] index_l1_19 = {!flag_l0_38,(flag_l0_38?index_l0_38:index_l0_39)}; +wire [1:0] index_l1_20 = {!flag_l0_40,(flag_l0_40?index_l0_40:index_l0_41)}; +wire [1:0] index_l1_21 = {!flag_l0_42,(flag_l0_42?index_l0_42:index_l0_43)}; +wire [1:0] index_l1_22 = {!flag_l0_44,(flag_l0_44?index_l0_44:index_l0_45)}; +wire [1:0] index_l1_23 = {!flag_l0_46,(flag_l0_46?index_l0_46:index_l0_47)}; +wire [1:0] index_l1_24 = {!flag_l0_48,(flag_l0_48?index_l0_48:index_l0_49)}; +wire [1:0] index_l1_25 = {!flag_l0_50,(flag_l0_50?index_l0_50:index_l0_51)}; +wire [1:0] index_l1_26 = {!flag_l0_52,(flag_l0_52?index_l0_52:index_l0_53)}; +wire [1:0] index_l1_27 = {!flag_l0_54,(flag_l0_54?index_l0_54:index_l0_55)}; +wire [1:0] index_l1_28 = {!flag_l0_56,(flag_l0_56?index_l0_56:index_l0_57)}; +wire [1:0] index_l1_29 = {!flag_l0_58,(flag_l0_58?index_l0_58:index_l0_59)}; +wire [1:0] index_l1_30 = {!flag_l0_60,(flag_l0_60?index_l0_60:index_l0_61)}; +wire [1:0] index_l1_31 = {!flag_l0_62,(flag_l0_62?index_l0_62:index_l0_63)}; +wire [1:0] index_l1_32 = {!flag_l0_64,(flag_l0_64?index_l0_64:index_l0_65)}; +wire [1:0] index_l1_33 = {!flag_l0_66,(flag_l0_66?index_l0_66:index_l0_67)}; +wire [1:0] index_l1_34 = {!flag_l0_68,(flag_l0_68?index_l0_68:index_l0_69)}; +wire [1:0] index_l1_35 = {!flag_l0_70,(flag_l0_70?index_l0_70:index_l0_71)}; +wire [1:0] index_l1_36 = {!flag_l0_72,(flag_l0_72?index_l0_72:index_l0_73)}; +wire [1:0] index_l1_37 = {!flag_l0_74,(flag_l0_74?index_l0_74:index_l0_75)}; +wire [1:0] index_l1_38 = {!flag_l0_76,(flag_l0_76?index_l0_76:index_l0_77)}; +wire [1:0] index_l1_39 = {!flag_l0_78,(flag_l0_78?index_l0_78:index_l0_79)}; +wire [1:0] index_l1_40 = {!flag_l0_80,(flag_l0_80?index_l0_80:index_l0_81)}; +wire [1:0] index_l1_41 = {!flag_l0_82,(flag_l0_82?index_l0_82:index_l0_83)}; +wire [1:0] index_l1_42 = {!flag_l0_84,(flag_l0_84?index_l0_84:index_l0_85)}; +wire [1:0] index_l1_43 = {!flag_l0_86,(flag_l0_86?index_l0_86:index_l0_87)}; +wire [1:0] index_l1_44 = {!flag_l0_88,(flag_l0_88?index_l0_88:index_l0_89)}; +wire [1:0] index_l1_45 = {!flag_l0_90,(flag_l0_90?index_l0_90:index_l0_91)}; +wire [1:0] index_l1_46 = {!flag_l0_92,(flag_l0_92?index_l0_92:index_l0_93)}; +wire [1:0] index_l1_47 = {!flag_l0_94,(flag_l0_94?index_l0_94:index_l0_95)}; +wire [1:0] index_l1_48 = {!flag_l0_96,(flag_l0_96?index_l0_96:index_l0_97)}; +wire [1:0] index_l1_49 = {!flag_l0_98,(flag_l0_98?index_l0_98:index_l0_99)}; +wire [1:0] index_l1_50 = {!flag_l0_100,(flag_l0_100?index_l0_100:index_l0_101)}; +wire [1:0] index_l1_51 = {!flag_l0_102,(flag_l0_102?index_l0_102:index_l0_103)}; +wire [1:0] index_l1_52 = {!flag_l0_104,(flag_l0_104?index_l0_104:index_l0_105)}; +wire [1:0] index_l1_53 = {!flag_l0_106,(flag_l0_106?index_l0_106:index_l0_107)}; +wire [1:0] index_l1_54 = {!flag_l0_108,(flag_l0_108?index_l0_108:index_l0_109)}; +wire [1:0] index_l1_55 = {!flag_l0_110,(flag_l0_110?index_l0_110:index_l0_111)}; +wire [1:0] index_l1_56 = {!flag_l0_112,(flag_l0_112?index_l0_112:index_l0_113)}; +wire [1:0] index_l1_57 = {!flag_l0_114,(flag_l0_114?index_l0_114:index_l0_115)}; +wire [1:0] index_l1_58 = {!flag_l0_116,(flag_l0_116?index_l0_116:index_l0_117)}; +wire [1:0] index_l1_59 = {!flag_l0_118,(flag_l0_118?index_l0_118:index_l0_119)}; +wire [1:0] index_l1_60 = {!flag_l0_120,(flag_l0_120?index_l0_120:index_l0_121)}; +wire [1:0] index_l1_61 = {!flag_l0_122,(flag_l0_122?index_l0_122:index_l0_123)}; +wire [1:0] index_l1_62 = {!flag_l0_124,(flag_l0_124?index_l0_124:index_l0_125)}; +wire [1:0] index_l1_63 = {!flag_l0_126,(flag_l0_126?index_l0_126:index_l0_127)}; +wire [2:0] index_l2_0 = {!flag_l1_0,(flag_l1_0?index_l1_0:index_l1_1)}; +wire [2:0] index_l2_1 = {!flag_l1_2,(flag_l1_2?index_l1_2:index_l1_3)}; +wire [2:0] index_l2_2 = {!flag_l1_4,(flag_l1_4?index_l1_4:index_l1_5)}; +wire [2:0] index_l2_3 = {!flag_l1_6,(flag_l1_6?index_l1_6:index_l1_7)}; +wire [2:0] index_l2_4 = {!flag_l1_8,(flag_l1_8?index_l1_8:index_l1_9)}; +wire [2:0] index_l2_5 = {!flag_l1_10,(flag_l1_10?index_l1_10:index_l1_11)}; +wire [2:0] index_l2_6 = {!flag_l1_12,(flag_l1_12?index_l1_12:index_l1_13)}; +wire [2:0] index_l2_7 = {!flag_l1_14,(flag_l1_14?index_l1_14:index_l1_15)}; +wire [2:0] index_l2_8 = {!flag_l1_16,(flag_l1_16?index_l1_16:index_l1_17)}; +wire [2:0] index_l2_9 = {!flag_l1_18,(flag_l1_18?index_l1_18:index_l1_19)}; +wire [2:0] index_l2_10 = {!flag_l1_20,(flag_l1_20?index_l1_20:index_l1_21)}; +wire [2:0] index_l2_11 = {!flag_l1_22,(flag_l1_22?index_l1_22:index_l1_23)}; +wire [2:0] index_l2_12 = {!flag_l1_24,(flag_l1_24?index_l1_24:index_l1_25)}; +wire [2:0] index_l2_13 = {!flag_l1_26,(flag_l1_26?index_l1_26:index_l1_27)}; +wire [2:0] index_l2_14 = {!flag_l1_28,(flag_l1_28?index_l1_28:index_l1_29)}; +wire [2:0] index_l2_15 = {!flag_l1_30,(flag_l1_30?index_l1_30:index_l1_31)}; +wire [2:0] index_l2_16 = {!flag_l1_32,(flag_l1_32?index_l1_32:index_l1_33)}; +wire [2:0] index_l2_17 = {!flag_l1_34,(flag_l1_34?index_l1_34:index_l1_35)}; +wire [2:0] index_l2_18 = {!flag_l1_36,(flag_l1_36?index_l1_36:index_l1_37)}; +wire [2:0] index_l2_19 = {!flag_l1_38,(flag_l1_38?index_l1_38:index_l1_39)}; +wire [2:0] index_l2_20 = {!flag_l1_40,(flag_l1_40?index_l1_40:index_l1_41)}; +wire [2:0] index_l2_21 = {!flag_l1_42,(flag_l1_42?index_l1_42:index_l1_43)}; +wire [2:0] index_l2_22 = {!flag_l1_44,(flag_l1_44?index_l1_44:index_l1_45)}; +wire [2:0] index_l2_23 = {!flag_l1_46,(flag_l1_46?index_l1_46:index_l1_47)}; +wire [2:0] index_l2_24 = {!flag_l1_48,(flag_l1_48?index_l1_48:index_l1_49)}; +wire [2:0] index_l2_25 = {!flag_l1_50,(flag_l1_50?index_l1_50:index_l1_51)}; +wire [2:0] index_l2_26 = {!flag_l1_52,(flag_l1_52?index_l1_52:index_l1_53)}; +wire [2:0] index_l2_27 = {!flag_l1_54,(flag_l1_54?index_l1_54:index_l1_55)}; +wire [2:0] index_l2_28 = {!flag_l1_56,(flag_l1_56?index_l1_56:index_l1_57)}; +wire [2:0] index_l2_29 = {!flag_l1_58,(flag_l1_58?index_l1_58:index_l1_59)}; +wire [2:0] index_l2_30 = {!flag_l1_60,(flag_l1_60?index_l1_60:index_l1_61)}; +wire [2:0] index_l2_31 = {!flag_l1_62,(flag_l1_62?index_l1_62:index_l1_63)}; +wire [3:0] index_l3_0 = {!flag_l2_0,(flag_l2_0?index_l2_0:index_l2_1)}; +wire [3:0] index_l3_1 = {!flag_l2_2,(flag_l2_2?index_l2_2:index_l2_3)}; +wire [3:0] index_l3_2 = {!flag_l2_4,(flag_l2_4?index_l2_4:index_l2_5)}; +wire [3:0] index_l3_3 = {!flag_l2_6,(flag_l2_6?index_l2_6:index_l2_7)}; +wire [3:0] index_l3_4 = {!flag_l2_8,(flag_l2_8?index_l2_8:index_l2_9)}; +wire [3:0] index_l3_5 = {!flag_l2_10,(flag_l2_10?index_l2_10:index_l2_11)}; +wire [3:0] index_l3_6 = {!flag_l2_12,(flag_l2_12?index_l2_12:index_l2_13)}; +wire [3:0] index_l3_7 = {!flag_l2_14,(flag_l2_14?index_l2_14:index_l2_15)}; +wire [3:0] index_l3_8 = {!flag_l2_16,(flag_l2_16?index_l2_16:index_l2_17)}; +wire [3:0] index_l3_9 = {!flag_l2_18,(flag_l2_18?index_l2_18:index_l2_19)}; +wire [3:0] index_l3_10 = {!flag_l2_20,(flag_l2_20?index_l2_20:index_l2_21)}; +wire [3:0] index_l3_11 = {!flag_l2_22,(flag_l2_22?index_l2_22:index_l2_23)}; +wire [3:0] index_l3_12 = {!flag_l2_24,(flag_l2_24?index_l2_24:index_l2_25)}; +wire [3:0] index_l3_13 = {!flag_l2_26,(flag_l2_26?index_l2_26:index_l2_27)}; +wire [3:0] index_l3_14 = {!flag_l2_28,(flag_l2_28?index_l2_28:index_l2_29)}; +wire [3:0] index_l3_15 = {!flag_l2_30,(flag_l2_30?index_l2_30:index_l2_31)}; +wire [4:0] index_l4_0 = {!flag_l3_0,(flag_l3_0?index_l3_0:index_l3_1)}; +wire [4:0] index_l4_1 = {!flag_l3_2,(flag_l3_2?index_l3_2:index_l3_3)}; +wire [4:0] index_l4_2 = {!flag_l3_4,(flag_l3_4?index_l3_4:index_l3_5)}; +wire [4:0] index_l4_3 = {!flag_l3_6,(flag_l3_6?index_l3_6:index_l3_7)}; +wire [4:0] index_l4_4 = {!flag_l3_8,(flag_l3_8?index_l3_8:index_l3_9)}; +wire [4:0] index_l4_5 = {!flag_l3_10,(flag_l3_10?index_l3_10:index_l3_11)}; +wire [4:0] index_l4_6 = {!flag_l3_12,(flag_l3_12?index_l3_12:index_l3_13)}; +wire [4:0] index_l4_7 = {!flag_l3_14,(flag_l3_14?index_l3_14:index_l3_15)}; +wire [5:0] index_l5_0 = {!flag_l4_0,(flag_l4_0?index_l4_0:index_l4_1)}; +wire [5:0] index_l5_1 = {!flag_l4_2,(flag_l4_2?index_l4_2:index_l4_3)}; +wire [5:0] index_l5_2 = {!flag_l4_4,(flag_l4_4?index_l4_4:index_l4_5)}; +wire [5:0] index_l5_3 = {!flag_l4_6,(flag_l4_6?index_l4_6:index_l4_7)}; +wire [6:0] index_l6_0 = {!flag_l5_0,(flag_l5_0?index_l5_0:index_l5_1)}; +wire [6:0] index_l6_1 = {!flag_l5_2,(flag_l5_2?index_l5_2:index_l5_3)}; +wire [7:0] index_l7_0 = {!flag_l6_0,(flag_l6_0?index_l6_0:index_l6_1)}; +assign free_adr_index[7:0] = index_l7_0[7:0]; +assign wr_popping = rd_popping; +// +// READ SIDE +// +// +// credits for taker are simply rd_pushing* +// +reg [9:0] cq_rd_credit; // registered out take credits +reg rd_pushing_q; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_credit <= 10'd0; + rd_pushing_q <= 1'b0; + end else begin + if ( rd_pushing || rd_pushing_q ) begin + cq_rd_credit[0] <= rd_pushing && rd_pushing_thread_id == 4'd0; + cq_rd_credit[1] <= rd_pushing && rd_pushing_thread_id == 4'd1; + cq_rd_credit[2] <= rd_pushing && rd_pushing_thread_id == 4'd2; + cq_rd_credit[3] <= rd_pushing && rd_pushing_thread_id == 4'd3; + cq_rd_credit[4] <= rd_pushing && rd_pushing_thread_id == 4'd4; + cq_rd_credit[5] <= rd_pushing && rd_pushing_thread_id == 4'd5; + cq_rd_credit[6] <= rd_pushing && rd_pushing_thread_id == 4'd6; + cq_rd_credit[7] <= rd_pushing && rd_pushing_thread_id == 4'd7; + cq_rd_credit[8] <= rd_pushing && rd_pushing_thread_id == 4'd8; + cq_rd_credit[9] <= rd_pushing && rd_pushing_thread_id == 4'd9; + rd_pushing_q <= rd_pushing; + end + end +end +wire rd_pushing0 = rd_pushing && rd_pushing_thread_id == 4'd0; +wire rd_pushing1 = rd_pushing && rd_pushing_thread_id == 4'd1; +wire rd_pushing2 = rd_pushing && rd_pushing_thread_id == 4'd2; +wire rd_pushing3 = rd_pushing && rd_pushing_thread_id == 4'd3; +wire rd_pushing4 = rd_pushing && rd_pushing_thread_id == 4'd4; +wire rd_pushing5 = rd_pushing && rd_pushing_thread_id == 4'd5; +wire rd_pushing6 = rd_pushing && rd_pushing_thread_id == 4'd6; +wire rd_pushing7 = rd_pushing && rd_pushing_thread_id == 4'd7; +wire rd_pushing8 = rd_pushing && rd_pushing_thread_id == 4'd8; +wire rd_pushing9 = rd_pushing && rd_pushing_thread_id == 4'd9; +wire rd_take0 = cq_rd_take && cq_rd_take_thread_id == 4'd0; +wire rd_take1 = cq_rd_take && cq_rd_take_thread_id == 4'd1; +wire rd_take2 = cq_rd_take && cq_rd_take_thread_id == 4'd2; +wire rd_take3 = cq_rd_take && cq_rd_take_thread_id == 4'd3; +wire rd_take4 = cq_rd_take && cq_rd_take_thread_id == 4'd4; +wire rd_take5 = cq_rd_take && cq_rd_take_thread_id == 4'd5; +wire rd_take6 = cq_rd_take && cq_rd_take_thread_id == 4'd6; +wire rd_take7 = cq_rd_take && cq_rd_take_thread_id == 4'd7; +wire rd_take8 = cq_rd_take && cq_rd_take_thread_id == 4'd8; +wire rd_take9 = cq_rd_take && cq_rd_take_thread_id == 4'd9; +reg [7:0] head0; // thread 0's head pointer +reg [7:0] tail0; // thread 0's tail pointer +reg [7:0] head1; // thread 1's head pointer +reg [7:0] tail1; // thread 1's tail pointer +reg [7:0] head2; // thread 2's head pointer +reg [7:0] tail2; // thread 2's tail pointer +reg [7:0] head3; // thread 3's head pointer +reg [7:0] tail3; // thread 3's tail pointer +reg [7:0] head4; // thread 4's head pointer +reg [7:0] tail4; // thread 4's tail pointer +reg [7:0] head5; // thread 5's head pointer +reg [7:0] tail5; // thread 5's tail pointer +reg [7:0] head6; // thread 6's head pointer +reg [7:0] tail6; // thread 6's tail pointer +reg [7:0] head7; // thread 7's head pointer +reg [7:0] tail7; // thread 7's tail pointer +reg [7:0] head8; // thread 8's head pointer +reg [7:0] tail8; // thread 8's tail pointer +reg [7:0] head9; // thread 9's head pointer +reg [7:0] tail9; // thread 9's tail pointer +reg [9:0] rd_take_n_dly; +reg rd_take_dly_cg; +wire update_rd_take_n_dly = cq_rd_take || rd_take_dly_cg; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly_cg <= 1'b0; + rd_take_n_dly <= {10{1'b0}}; + end else begin + rd_take_dly_cg <= cq_rd_take; + if ( update_rd_take_n_dly ) begin + rd_take_n_dly <= {rd_take9,rd_take8,rd_take7,rd_take6,rd_take5,rd_take4,rd_take3,rd_take2,rd_take1,rd_take0}; + end +//synopsys translate_off + else if ( !update_rd_take_n_dly) begin + end else begin + rd_take_n_dly <= {10{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] adr_ram_wr_adr; +wire [7:0] adr_ram_wr_data; +reg adr_ram_wr_enable; +reg [7:0] adr_ram_rd_adr; +wire [7:0] adr_ram_rd_data; +reg adr_ram_rd_enable; +reg [8:0] cq_rd_count0; +wire [8:0] rd_count0_next; +reg [8:0] cq_rd_count1; +wire [8:0] rd_count1_next; +reg [8:0] cq_rd_count2; +wire [8:0] rd_count2_next; +reg [8:0] cq_rd_count3; +wire [8:0] rd_count3_next; +reg [8:0] cq_rd_count4; +wire [8:0] rd_count4_next; +reg [8:0] cq_rd_count5; +wire [8:0] rd_count5_next; +reg [8:0] cq_rd_count6; +wire [8:0] rd_count6_next; +reg [8:0] cq_rd_count7; +wire [8:0] rd_count7_next; +reg [8:0] cq_rd_count8; +wire [8:0] rd_count8_next; +reg [8:0] cq_rd_count9; +wire [8:0] rd_count9_next; +assign rd_count0_next = + rd_pushing0 ? ( rd_take0 ? cq_rd_count0 : cq_rd_count0 + 1'd1 ) : + ( rd_take0 ? cq_rd_count0 - 1'd1 : cq_rd_count0 ); +assign rd_count1_next = + rd_pushing1 ? ( rd_take1 ? cq_rd_count1 : cq_rd_count1 + 1'd1 ) : + ( rd_take1 ? cq_rd_count1 - 1'd1 : cq_rd_count1 ); +assign rd_count2_next = + rd_pushing2 ? ( rd_take2 ? cq_rd_count2 : cq_rd_count2 + 1'd1 ) : + ( rd_take2 ? cq_rd_count2 - 1'd1 : cq_rd_count2 ); +assign rd_count3_next = + rd_pushing3 ? ( rd_take3 ? cq_rd_count3 : cq_rd_count3 + 1'd1 ) : + ( rd_take3 ? cq_rd_count3 - 1'd1 : cq_rd_count3 ); +assign rd_count4_next = + rd_pushing4 ? ( rd_take4 ? cq_rd_count4 : cq_rd_count4 + 1'd1 ) : + ( rd_take4 ? cq_rd_count4 - 1'd1 : cq_rd_count4 ); +assign rd_count5_next = + rd_pushing5 ? ( rd_take5 ? cq_rd_count5 : cq_rd_count5 + 1'd1 ) : + ( rd_take5 ? cq_rd_count5 - 1'd1 : cq_rd_count5 ); +assign rd_count6_next = + rd_pushing6 ? ( rd_take6 ? cq_rd_count6 : cq_rd_count6 + 1'd1 ) : + ( rd_take6 ? cq_rd_count6 - 1'd1 : cq_rd_count6 ); +assign rd_count7_next = + rd_pushing7 ? ( rd_take7 ? cq_rd_count7 : cq_rd_count7 + 1'd1 ) : + ( rd_take7 ? cq_rd_count7 - 1'd1 : cq_rd_count7 ); +assign rd_count8_next = + rd_pushing8 ? ( rd_take8 ? cq_rd_count8 : cq_rd_count8 + 1'd1 ) : + ( rd_take8 ? cq_rd_count8 - 1'd1 : cq_rd_count8 ); +assign rd_count9_next = + rd_pushing9 ? ( rd_take9 ? cq_rd_count9 : cq_rd_count9 + 1'd1 ) : + ( rd_take9 ? cq_rd_count9 - 1'd1 : cq_rd_count9 ); +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_count0 <= 9'd0; + cq_rd_count1 <= 9'd0; + cq_rd_count2 <= 9'd0; + cq_rd_count3 <= 9'd0; + cq_rd_count4 <= 9'd0; + cq_rd_count5 <= 9'd0; + cq_rd_count6 <= 9'd0; + cq_rd_count7 <= 9'd0; + cq_rd_count8 <= 9'd0; + cq_rd_count9 <= 9'd0; + end else begin + if ( rd_pushing0 ^ rd_take0 ) begin + cq_rd_count0 <= rd_count0_next; + end +//synopsys translate_off + else if ( !(rd_pushing0 ^ rd_take0) ) begin + end else begin + cq_rd_count0 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing1 ^ rd_take1 ) begin + cq_rd_count1 <= rd_count1_next; + end +//synopsys translate_off + else if ( !(rd_pushing1 ^ rd_take1) ) begin + end else begin + cq_rd_count1 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing2 ^ rd_take2 ) begin + cq_rd_count2 <= rd_count2_next; + end +//synopsys translate_off + else if ( !(rd_pushing2 ^ rd_take2) ) begin + end else begin + cq_rd_count2 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing3 ^ rd_take3 ) begin + cq_rd_count3 <= rd_count3_next; + end +//synopsys translate_off + else if ( !(rd_pushing3 ^ rd_take3) ) begin + end else begin + cq_rd_count3 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing4 ^ rd_take4 ) begin + cq_rd_count4 <= rd_count4_next; + end +//synopsys translate_off + else if ( !(rd_pushing4 ^ rd_take4) ) begin + end else begin + cq_rd_count4 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing5 ^ rd_take5 ) begin + cq_rd_count5 <= rd_count5_next; + end +//synopsys translate_off + else if ( !(rd_pushing5 ^ rd_take5) ) begin + end else begin + cq_rd_count5 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing6 ^ rd_take6 ) begin + cq_rd_count6 <= rd_count6_next; + end +//synopsys translate_off + else if ( !(rd_pushing6 ^ rd_take6) ) begin + end else begin + cq_rd_count6 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing7 ^ rd_take7 ) begin + cq_rd_count7 <= rd_count7_next; + end +//synopsys translate_off + else if ( !(rd_pushing7 ^ rd_take7) ) begin + end else begin + cq_rd_count7 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing8 ^ rd_take8 ) begin + cq_rd_count8 <= rd_count8_next; + end +//synopsys translate_off + else if ( !(rd_pushing8 ^ rd_take8) ) begin + end else begin + cq_rd_count8 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing9 ^ rd_take9 ) begin + cq_rd_count9 <= rd_count9_next; + end +//synopsys translate_off + else if ( !(rd_pushing9 ^ rd_take9) ) begin + end else begin + cq_rd_count9 <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [9:0] update_head; +wire [9:0] update_head_next; +assign update_head_next[0] = (rd_take0 && cq_rd_count0 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[1] = (rd_take1 && cq_rd_count1 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[2] = (rd_take2 && cq_rd_count2 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[3] = (rd_take3 && cq_rd_count3 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[4] = (rd_take4 && cq_rd_count4 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[5] = (rd_take5 && cq_rd_count5 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[6] = (rd_take6 && cq_rd_count6 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[7] = (rd_take7 && cq_rd_count7 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[8] = (rd_take8 && cq_rd_count8 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[9] = (rd_take9 && cq_rd_count9 > 9'd1) ? 1'b1 : 1'b0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + update_head <= 10'd0; + end else begin + if ( rd_pushing || cq_rd_take ) begin + update_head <= update_head_next; + end +//synopsys translate_off + else if ( !(rd_pushing || cq_rd_take) ) begin + end else begin + update_head <= {10{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(posedge nvdla_core_clk_mgated) begin + if ( rd_pushing0 ) begin + tail0 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing0 ) begin + end else begin + tail0 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing0 && cq_rd_count0 == 9'd0 ) || + (rd_pushing0 && rd_take0 && cq_rd_count0 == 9'd1) ) begin + head0 <= rd_pushing_adr; + end else if ( update_head[0] ) begin + head0 <= adr_ram_rd_data; + end + if ( rd_pushing1 ) begin + tail1 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing1 ) begin + end else begin + tail1 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing1 && cq_rd_count1 == 9'd0 ) || + (rd_pushing1 && rd_take1 && cq_rd_count1 == 9'd1) ) begin + head1 <= rd_pushing_adr; + end else if ( update_head[1] ) begin + head1 <= adr_ram_rd_data; + end + if ( rd_pushing2 ) begin + tail2 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing2 ) begin + end else begin + tail2 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing2 && cq_rd_count2 == 9'd0 ) || + (rd_pushing2 && rd_take2 && cq_rd_count2 == 9'd1) ) begin + head2 <= rd_pushing_adr; + end else if ( update_head[2] ) begin + head2 <= adr_ram_rd_data; + end + if ( rd_pushing3 ) begin + tail3 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing3 ) begin + end else begin + tail3 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing3 && cq_rd_count3 == 9'd0 ) || + (rd_pushing3 && rd_take3 && cq_rd_count3 == 9'd1) ) begin + head3 <= rd_pushing_adr; + end else if ( update_head[3] ) begin + head3 <= adr_ram_rd_data; + end + if ( rd_pushing4 ) begin + tail4 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing4 ) begin + end else begin + tail4 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing4 && cq_rd_count4 == 9'd0 ) || + (rd_pushing4 && rd_take4 && cq_rd_count4 == 9'd1) ) begin + head4 <= rd_pushing_adr; + end else if ( update_head[4] ) begin + head4 <= adr_ram_rd_data; + end + if ( rd_pushing5 ) begin + tail5 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing5 ) begin + end else begin + tail5 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing5 && cq_rd_count5 == 9'd0 ) || + (rd_pushing5 && rd_take5 && cq_rd_count5 == 9'd1) ) begin + head5 <= rd_pushing_adr; + end else if ( update_head[5] ) begin + head5 <= adr_ram_rd_data; + end + if ( rd_pushing6 ) begin + tail6 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing6 ) begin + end else begin + tail6 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing6 && cq_rd_count6 == 9'd0 ) || + (rd_pushing6 && rd_take6 && cq_rd_count6 == 9'd1) ) begin + head6 <= rd_pushing_adr; + end else if ( update_head[6] ) begin + head6 <= adr_ram_rd_data; + end + if ( rd_pushing7 ) begin + tail7 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing7 ) begin + end else begin + tail7 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing7 && cq_rd_count7 == 9'd0 ) || + (rd_pushing7 && rd_take7 && cq_rd_count7 == 9'd1) ) begin + head7 <= rd_pushing_adr; + end else if ( update_head[7] ) begin + head7 <= adr_ram_rd_data; + end + if ( rd_pushing8 ) begin + tail8 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing8 ) begin + end else begin + tail8 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing8 && cq_rd_count8 == 9'd0 ) || + (rd_pushing8 && rd_take8 && cq_rd_count8 == 9'd1) ) begin + head8 <= rd_pushing_adr; + end else if ( update_head[8] ) begin + head8 <= adr_ram_rd_data; + end + if ( rd_pushing9 ) begin + tail9 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing9 ) begin + end else begin + tail9 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing9 && cq_rd_count9 == 9'd0 ) || + (rd_pushing9 && rd_take9 && cq_rd_count9 == 9'd1) ) begin + head9 <= rd_pushing_adr; + end else if ( update_head[9] ) begin + head9 <= adr_ram_rd_data; + end +end +nv_ram_rwst_256x8 adr_ram ( + .clk ( nvdla_core_clk ) + , .wa ( adr_ram_wr_adr ) + , .we ( adr_ram_wr_enable ) + , .di ( adr_ram_wr_data ) + , .ra ( adr_ram_rd_adr ) + , .re ( adr_ram_rd_enable ) + , .dout ( adr_ram_rd_data ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + ); +assign adr_ram_wr_data = rd_pushing_adr; +always @(*) begin + case( rd_pushing_thread_id ) + 4'd0: adr_ram_wr_adr = tail0; + 4'd1: adr_ram_wr_adr = tail1; + 4'd2: adr_ram_wr_adr = tail2; + 4'd3: adr_ram_wr_adr = tail3; + 4'd4: adr_ram_wr_adr = tail4; + 4'd5: adr_ram_wr_adr = tail5; + 4'd6: adr_ram_wr_adr = tail6; + 4'd7: adr_ram_wr_adr = tail7; + 4'd8: adr_ram_wr_adr = tail8; + 4'd9: adr_ram_wr_adr = tail9; +//VCS coverage off + default: adr_ram_wr_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( rd_pushing_thread_id ) + 4'd0: adr_ram_wr_enable = rd_pushing && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 4'd1: adr_ram_wr_enable = rd_pushing && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 4'd2: adr_ram_wr_enable = rd_pushing && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 4'd3: adr_ram_wr_enable = rd_pushing && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 4'd4: adr_ram_wr_enable = rd_pushing && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; + 4'd5: adr_ram_wr_enable = rd_pushing && cq_rd_count5 != 9'd0 ? 1'b1 : 1'b0; + 4'd6: adr_ram_wr_enable = rd_pushing && cq_rd_count6 != 9'd0 ? 1'b1 : 1'b0; + 4'd7: adr_ram_wr_enable = rd_pushing && cq_rd_count7 != 9'd0 ? 1'b1 : 1'b0; + 4'd8: adr_ram_wr_enable = rd_pushing && cq_rd_count8 != 9'd0 ? 1'b1 : 1'b0; + 4'd9: adr_ram_wr_enable = rd_pushing && cq_rd_count9 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_wr_enable = !rd_pushing ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 4'd0: adr_ram_rd_enable = cq_rd_take && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 4'd1: adr_ram_rd_enable = cq_rd_take && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 4'd2: adr_ram_rd_enable = cq_rd_take && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 4'd3: adr_ram_rd_enable = cq_rd_take && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 4'd4: adr_ram_rd_enable = cq_rd_take && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; + 4'd5: adr_ram_rd_enable = cq_rd_take && cq_rd_count5 != 9'd0 ? 1'b1 : 1'b0; + 4'd6: adr_ram_rd_enable = cq_rd_take && cq_rd_count6 != 9'd0 ? 1'b1 : 1'b0; + 4'd7: adr_ram_rd_enable = cq_rd_take && cq_rd_count7 != 9'd0 ? 1'b1 : 1'b0; + 4'd8: adr_ram_rd_enable = cq_rd_take && cq_rd_count8 != 9'd0 ? 1'b1 : 1'b0; + 4'd9: adr_ram_rd_enable = cq_rd_take && cq_rd_count9 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_rd_enable = !cq_rd_take ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 4'd0: adr_ram_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 4'd1: adr_ram_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 4'd2: adr_ram_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 4'd3: adr_ram_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 4'd4: adr_ram_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; + 4'd5: adr_ram_rd_adr = rd_take_n_dly[5] && update_head[5] ? adr_ram_rd_data : head5; + 4'd6: adr_ram_rd_adr = rd_take_n_dly[6] && update_head[6] ? adr_ram_rd_data : head6; + 4'd7: adr_ram_rd_adr = rd_take_n_dly[7] && update_head[7] ? adr_ram_rd_data : head7; + 4'd8: adr_ram_rd_adr = rd_take_n_dly[8] && update_head[8] ? adr_ram_rd_data : head8; + 4'd9: adr_ram_rd_adr = rd_take_n_dly[9] && update_head[9] ? adr_ram_rd_data : head9; +//VCS coverage off + default: adr_ram_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 4'd0: cq_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 4'd1: cq_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 4'd2: cq_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 4'd3: cq_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 4'd4: cq_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; + 4'd5: cq_rd_adr = rd_take_n_dly[5] && update_head[5] ? adr_ram_rd_data : head5; + 4'd6: cq_rd_adr = rd_take_n_dly[6] && update_head[6] ? adr_ram_rd_data : head6; + 4'd7: cq_rd_adr = rd_take_n_dly[7] && update_head[7] ? adr_ram_rd_data : head7; + 4'd8: cq_rd_adr = rd_take_n_dly[8] && update_head[8] ? adr_ram_rd_data : head8; + 4'd9: cq_rd_adr = rd_take_n_dly[9] && update_head[9] ? adr_ram_rd_data : head9; +//VCS coverage off + default: cq_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +// +// take data comes out next cycle for non-ff rams. +// +reg rd_take_dly; +assign rd_popping = rd_take_dly; +reg [7:0] rd_adr_dly; +assign rd_popping_adr = rd_adr_dly; +assign rd_enable = cq_rd_take; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly <= 1'b0; + end else begin + rd_take_dly <= cq_rd_take; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( cq_rd_take ) begin + rd_adr_dly <= cq_rd_adr; + end +//synopsys translate_off + else if ( !(cq_rd_take) ) begin + end else begin + rd_adr_dly <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// +// -rd_take_to_rd_busy conversion (conceptually outside the fifo except for ra2 bypass) +// +wire [9:0] cq_rd_take_elig; // mask of threads that can do takes this cycle +wire rd_pre_bypassing0; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing0; // between cq_rd0_pvld and cq_rd0_prdy when doing full bypass +reg [6:0] rd_skid0_0; // head skid reg +reg [6:0] rd_skid0_1; // head+1 skid reg +reg [6:0] rd_skid0_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid0_0_vld; // head skid reg has valid data +reg rd_skid0_1_vld; // head+1 skid reg has valid data +reg rd_skid0_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd0_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_prdy_d <= 1'b1; + end else begin + cq_rd0_prdy_d <= cq_rd0_prdy; + end +end +assign cq_rd0_pvld = rd_skid0_0_vld || rd_pre_bypassing0; // full bypass for 0-latency +assign cq_rd0_pd = rd_skid0_0_vld ? rd_skid0_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld)) ) begin + rd_skid0_0 <= rd_take_n_dly[0] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld ) begin + rd_skid0_0 <= rd_skid0_1; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld) ) begin + end else begin + rd_skid0_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld)) ) begin + rd_skid0_1 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld ) begin + rd_skid0_1 <= rd_skid0_2; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld) ) begin + end else begin + rd_skid0_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy)) ) begin + rd_skid0_2 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy))) ) begin + end else begin + rd_skid0_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid0_0_vld <= 1'b0; + rd_skid0_1_vld <= 1'b0; + rd_skid0_2_vld <= 1'b0; + end else begin + rd_skid0_0_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_1_vld || (rd_bypassing0 && rd_skid0_0_vld) || rd_take_n_dly[0]) : (rd_skid0_0_vld || rd_bypassing0 || rd_take_n_dly[0]); + rd_skid0_1_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))) : (rd_skid0_1_vld || (rd_skid0_0_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage off + rd_skid0_2_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld && (rd_bypassing0 || rd_take_n_dly[0])) : (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd0_credits; // unused credits +reg cq_rd0_credits_ne0; +wire [8:0] cq_rd0_credits_w_take_next = cq_rd0_credits + cq_rd_credit[0] - 1'b1; +wire [8:0] cq_rd0_credits_wo_take_next = cq_rd0_credits + cq_rd_credit[0]; +wire [8:0] cq_rd0_credits_next = rd_take0 ? cq_rd0_credits_w_take_next : cq_rd0_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[0] = (cq_rd0_prdy_d || !rd_skid0_0_vld || !rd_skid0_1_vld || (!rd_skid0_2_vld && !rd_take_n_dly[0])) && (cq_rd_credit[0] || cq_rd0_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing0 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd0) && cq_rd0_credits == 0 && !cq_rd_credit[0] && (!rd_take_n_dly[0] || rd_skid0_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing0 = rd_pre_bypassing0 && (!rd_skid0_2_vld || !rd_skid0_1_vld || !(!cq_rd0_prdy_d && rd_skid0_0_vld && rd_skid0_1_vld)) && !rd_take_n_dly[0]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_credits <= 9'd0; + cq_rd0_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[0] | rd_take0 ) begin + cq_rd0_credits <= cq_rd0_credits_next; + cq_rd0_credits_ne0 <= rd_take0 ? (cq_rd0_credits_w_take_next != 0) : (cq_rd0_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[0] | rd_take0) ) begin + end else begin + cq_rd0_credits <= {9{`x_or_0}}; + cq_rd0_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing1; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing1; // between cq_rd1_pvld and cq_rd1_prdy when doing full bypass +reg [6:0] rd_skid1_0; // head skid reg +reg [6:0] rd_skid1_1; // head+1 skid reg +reg [6:0] rd_skid1_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid1_0_vld; // head skid reg has valid data +reg rd_skid1_1_vld; // head+1 skid reg has valid data +reg rd_skid1_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd1_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_prdy_d <= 1'b1; + end else begin + cq_rd1_prdy_d <= cq_rd1_prdy; + end +end +assign cq_rd1_pvld = rd_skid1_0_vld || rd_pre_bypassing1; // full bypass for 0-latency +assign cq_rd1_pd = rd_skid1_0_vld ? rd_skid1_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld)) ) begin + rd_skid1_0 <= rd_take_n_dly[1] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld ) begin + rd_skid1_0 <= rd_skid1_1; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld) ) begin + end else begin + rd_skid1_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld)) ) begin + rd_skid1_1 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld ) begin + rd_skid1_1 <= rd_skid1_2; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld) ) begin + end else begin + rd_skid1_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy)) ) begin + rd_skid1_2 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy))) ) begin + end else begin + rd_skid1_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid1_0_vld <= 1'b0; + rd_skid1_1_vld <= 1'b0; + rd_skid1_2_vld <= 1'b0; + end else begin + rd_skid1_0_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_1_vld || (rd_bypassing1 && rd_skid1_0_vld) || rd_take_n_dly[1]) : (rd_skid1_0_vld || rd_bypassing1 || rd_take_n_dly[1]); + rd_skid1_1_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))) : (rd_skid1_1_vld || (rd_skid1_0_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage off + rd_skid1_2_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld && (rd_bypassing1 || rd_take_n_dly[1])) : (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd1_credits; // unused credits +reg cq_rd1_credits_ne0; +wire [8:0] cq_rd1_credits_w_take_next = cq_rd1_credits + cq_rd_credit[1] - 1'b1; +wire [8:0] cq_rd1_credits_wo_take_next = cq_rd1_credits + cq_rd_credit[1]; +wire [8:0] cq_rd1_credits_next = rd_take1 ? cq_rd1_credits_w_take_next : cq_rd1_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[1] = (cq_rd1_prdy_d || !rd_skid1_0_vld || !rd_skid1_1_vld || (!rd_skid1_2_vld && !rd_take_n_dly[1])) && (cq_rd_credit[1] || cq_rd1_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing1 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd1) && cq_rd1_credits == 0 && !cq_rd_credit[1] && (!rd_take_n_dly[1] || rd_skid1_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing1 = rd_pre_bypassing1 && (!rd_skid1_2_vld || !rd_skid1_1_vld || !(!cq_rd1_prdy_d && rd_skid1_0_vld && rd_skid1_1_vld)) && !rd_take_n_dly[1]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_credits <= 9'd0; + cq_rd1_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[1] | rd_take1 ) begin + cq_rd1_credits <= cq_rd1_credits_next; + cq_rd1_credits_ne0 <= rd_take1 ? (cq_rd1_credits_w_take_next != 0) : (cq_rd1_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[1] | rd_take1) ) begin + end else begin + cq_rd1_credits <= {9{`x_or_0}}; + cq_rd1_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing2; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing2; // between cq_rd2_pvld and cq_rd2_prdy when doing full bypass +reg [6:0] rd_skid2_0; // head skid reg +reg [6:0] rd_skid2_1; // head+1 skid reg +reg [6:0] rd_skid2_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid2_0_vld; // head skid reg has valid data +reg rd_skid2_1_vld; // head+1 skid reg has valid data +reg rd_skid2_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd2_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_prdy_d <= 1'b1; + end else begin + cq_rd2_prdy_d <= cq_rd2_prdy; + end +end +assign cq_rd2_pvld = rd_skid2_0_vld || rd_pre_bypassing2; // full bypass for 0-latency +assign cq_rd2_pd = rd_skid2_0_vld ? rd_skid2_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld)) ) begin + rd_skid2_0 <= rd_take_n_dly[2] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld ) begin + rd_skid2_0 <= rd_skid2_1; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld) ) begin + end else begin + rd_skid2_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld)) ) begin + rd_skid2_1 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld ) begin + rd_skid2_1 <= rd_skid2_2; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld) ) begin + end else begin + rd_skid2_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy)) ) begin + rd_skid2_2 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy))) ) begin + end else begin + rd_skid2_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid2_0_vld <= 1'b0; + rd_skid2_1_vld <= 1'b0; + rd_skid2_2_vld <= 1'b0; + end else begin + rd_skid2_0_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_1_vld || (rd_bypassing2 && rd_skid2_0_vld) || rd_take_n_dly[2]) : (rd_skid2_0_vld || rd_bypassing2 || rd_take_n_dly[2]); + rd_skid2_1_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))) : (rd_skid2_1_vld || (rd_skid2_0_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage off + rd_skid2_2_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld && (rd_bypassing2 || rd_take_n_dly[2])) : (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd2_credits; // unused credits +reg cq_rd2_credits_ne0; +wire [8:0] cq_rd2_credits_w_take_next = cq_rd2_credits + cq_rd_credit[2] - 1'b1; +wire [8:0] cq_rd2_credits_wo_take_next = cq_rd2_credits + cq_rd_credit[2]; +wire [8:0] cq_rd2_credits_next = rd_take2 ? cq_rd2_credits_w_take_next : cq_rd2_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[2] = (cq_rd2_prdy_d || !rd_skid2_0_vld || !rd_skid2_1_vld || (!rd_skid2_2_vld && !rd_take_n_dly[2])) && (cq_rd_credit[2] || cq_rd2_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing2 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd2) && cq_rd2_credits == 0 && !cq_rd_credit[2] && (!rd_take_n_dly[2] || rd_skid2_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing2 = rd_pre_bypassing2 && (!rd_skid2_2_vld || !rd_skid2_1_vld || !(!cq_rd2_prdy_d && rd_skid2_0_vld && rd_skid2_1_vld)) && !rd_take_n_dly[2]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_credits <= 9'd0; + cq_rd2_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[2] | rd_take2 ) begin + cq_rd2_credits <= cq_rd2_credits_next; + cq_rd2_credits_ne0 <= rd_take2 ? (cq_rd2_credits_w_take_next != 0) : (cq_rd2_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[2] | rd_take2) ) begin + end else begin + cq_rd2_credits <= {9{`x_or_0}}; + cq_rd2_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing3; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing3; // between cq_rd3_pvld and cq_rd3_prdy when doing full bypass +reg [6:0] rd_skid3_0; // head skid reg +reg [6:0] rd_skid3_1; // head+1 skid reg +reg [6:0] rd_skid3_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid3_0_vld; // head skid reg has valid data +reg rd_skid3_1_vld; // head+1 skid reg has valid data +reg rd_skid3_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd3_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_prdy_d <= 1'b1; + end else begin + cq_rd3_prdy_d <= cq_rd3_prdy; + end +end +assign cq_rd3_pvld = rd_skid3_0_vld || rd_pre_bypassing3; // full bypass for 0-latency +assign cq_rd3_pd = rd_skid3_0_vld ? rd_skid3_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld)) ) begin + rd_skid3_0 <= rd_take_n_dly[3] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld ) begin + rd_skid3_0 <= rd_skid3_1; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld) ) begin + end else begin + rd_skid3_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld)) ) begin + rd_skid3_1 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld ) begin + rd_skid3_1 <= rd_skid3_2; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld) ) begin + end else begin + rd_skid3_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy)) ) begin + rd_skid3_2 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy))) ) begin + end else begin + rd_skid3_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid3_0_vld <= 1'b0; + rd_skid3_1_vld <= 1'b0; + rd_skid3_2_vld <= 1'b0; + end else begin + rd_skid3_0_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_1_vld || (rd_bypassing3 && rd_skid3_0_vld) || rd_take_n_dly[3]) : (rd_skid3_0_vld || rd_bypassing3 || rd_take_n_dly[3]); + rd_skid3_1_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))) : (rd_skid3_1_vld || (rd_skid3_0_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage off + rd_skid3_2_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld && (rd_bypassing3 || rd_take_n_dly[3])) : (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd3_credits; // unused credits +reg cq_rd3_credits_ne0; +wire [8:0] cq_rd3_credits_w_take_next = cq_rd3_credits + cq_rd_credit[3] - 1'b1; +wire [8:0] cq_rd3_credits_wo_take_next = cq_rd3_credits + cq_rd_credit[3]; +wire [8:0] cq_rd3_credits_next = rd_take3 ? cq_rd3_credits_w_take_next : cq_rd3_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[3] = (cq_rd3_prdy_d || !rd_skid3_0_vld || !rd_skid3_1_vld || (!rd_skid3_2_vld && !rd_take_n_dly[3])) && (cq_rd_credit[3] || cq_rd3_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing3 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd3) && cq_rd3_credits == 0 && !cq_rd_credit[3] && (!rd_take_n_dly[3] || rd_skid3_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing3 = rd_pre_bypassing3 && (!rd_skid3_2_vld || !rd_skid3_1_vld || !(!cq_rd3_prdy_d && rd_skid3_0_vld && rd_skid3_1_vld)) && !rd_take_n_dly[3]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_credits <= 9'd0; + cq_rd3_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[3] | rd_take3 ) begin + cq_rd3_credits <= cq_rd3_credits_next; + cq_rd3_credits_ne0 <= rd_take3 ? (cq_rd3_credits_w_take_next != 0) : (cq_rd3_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[3] | rd_take3) ) begin + end else begin + cq_rd3_credits <= {9{`x_or_0}}; + cq_rd3_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing4; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing4; // between cq_rd4_pvld and cq_rd4_prdy when doing full bypass +reg [6:0] rd_skid4_0; // head skid reg +reg [6:0] rd_skid4_1; // head+1 skid reg +reg [6:0] rd_skid4_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid4_0_vld; // head skid reg has valid data +reg rd_skid4_1_vld; // head+1 skid reg has valid data +reg rd_skid4_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd4_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_prdy_d <= 1'b1; + end else begin + cq_rd4_prdy_d <= cq_rd4_prdy; + end +end +assign cq_rd4_pvld = rd_skid4_0_vld || rd_pre_bypassing4; // full bypass for 0-latency +assign cq_rd4_pd = rd_skid4_0_vld ? rd_skid4_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld)) ) begin + rd_skid4_0 <= rd_take_n_dly[4] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld ) begin + rd_skid4_0 <= rd_skid4_1; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld) ) begin + end else begin + rd_skid4_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld)) ) begin + rd_skid4_1 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld ) begin + rd_skid4_1 <= rd_skid4_2; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld) ) begin + end else begin + rd_skid4_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy)) ) begin + rd_skid4_2 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy))) ) begin + end else begin + rd_skid4_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid4_0_vld <= 1'b0; + rd_skid4_1_vld <= 1'b0; + rd_skid4_2_vld <= 1'b0; + end else begin + rd_skid4_0_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_1_vld || (rd_bypassing4 && rd_skid4_0_vld) || rd_take_n_dly[4]) : (rd_skid4_0_vld || rd_bypassing4 || rd_take_n_dly[4]); + rd_skid4_1_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))) : (rd_skid4_1_vld || (rd_skid4_0_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage off + rd_skid4_2_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld && (rd_bypassing4 || rd_take_n_dly[4])) : (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd4_credits; // unused credits +reg cq_rd4_credits_ne0; +wire [8:0] cq_rd4_credits_w_take_next = cq_rd4_credits + cq_rd_credit[4] - 1'b1; +wire [8:0] cq_rd4_credits_wo_take_next = cq_rd4_credits + cq_rd_credit[4]; +wire [8:0] cq_rd4_credits_next = rd_take4 ? cq_rd4_credits_w_take_next : cq_rd4_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[4] = (cq_rd4_prdy_d || !rd_skid4_0_vld || !rd_skid4_1_vld || (!rd_skid4_2_vld && !rd_take_n_dly[4])) && (cq_rd_credit[4] || cq_rd4_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing4 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd4) && cq_rd4_credits == 0 && !cq_rd_credit[4] && (!rd_take_n_dly[4] || rd_skid4_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing4 = rd_pre_bypassing4 && (!rd_skid4_2_vld || !rd_skid4_1_vld || !(!cq_rd4_prdy_d && rd_skid4_0_vld && rd_skid4_1_vld)) && !rd_take_n_dly[4]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_credits <= 9'd0; + cq_rd4_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[4] | rd_take4 ) begin + cq_rd4_credits <= cq_rd4_credits_next; + cq_rd4_credits_ne0 <= rd_take4 ? (cq_rd4_credits_w_take_next != 0) : (cq_rd4_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[4] | rd_take4) ) begin + end else begin + cq_rd4_credits <= {9{`x_or_0}}; + cq_rd4_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing5; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing5; // between cq_rd5_pvld and cq_rd5_prdy when doing full bypass +reg [6:0] rd_skid5_0; // head skid reg +reg [6:0] rd_skid5_1; // head+1 skid reg +reg [6:0] rd_skid5_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid5_0_vld; // head skid reg has valid data +reg rd_skid5_1_vld; // head+1 skid reg has valid data +reg rd_skid5_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd5_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd5_prdy_d <= 1'b1; + end else begin + cq_rd5_prdy_d <= cq_rd5_prdy; + end +end +assign cq_rd5_pvld = rd_skid5_0_vld || rd_pre_bypassing5; // full bypass for 0-latency +assign cq_rd5_pd = rd_skid5_0_vld ? rd_skid5_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_0_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_1_vld)) ) begin + rd_skid5_0 <= rd_take_n_dly[5] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd5_pvld && cq_rd5_prdy && rd_skid5_1_vld ) begin + rd_skid5_0 <= rd_skid5_1; + end +//synopsys translate_off + else if ( !((rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_0_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_1_vld))) && + !(cq_rd5_pvld && cq_rd5_prdy && rd_skid5_1_vld) ) begin + end else begin + rd_skid5_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_1_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_2_vld)) ) begin + rd_skid5_1 <= rd_bypassing5 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd5_pvld && cq_rd5_prdy && rd_skid5_2_vld ) begin + rd_skid5_1 <= rd_skid5_2; + end +//synopsys translate_off + else if ( !((rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_1_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_2_vld))) && + !(cq_rd5_pvld && cq_rd5_prdy && rd_skid5_2_vld) ) begin + end else begin + rd_skid5_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing5 || rd_take_n_dly[5]) && rd_skid5_0_vld && rd_skid5_1_vld && (rd_skid5_2_vld || !(cq_rd5_pvld && cq_rd5_prdy)) ) begin + rd_skid5_2 <= rd_bypassing5 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing5 || rd_take_n_dly[5]) && rd_skid5_0_vld && rd_skid5_1_vld && (rd_skid5_2_vld || !(cq_rd5_pvld && cq_rd5_prdy))) ) begin + end else begin + rd_skid5_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid5_0_vld <= 1'b0; + rd_skid5_1_vld <= 1'b0; + rd_skid5_2_vld <= 1'b0; + end else begin + rd_skid5_0_vld <= (cq_rd5_pvld && cq_rd5_prdy) ? (rd_skid5_1_vld || (rd_bypassing5 && rd_skid5_0_vld) || rd_take_n_dly[5]) : (rd_skid5_0_vld || rd_bypassing5 || rd_take_n_dly[5]); + rd_skid5_1_vld <= (cq_rd5_pvld && cq_rd5_prdy) ? (rd_skid5_2_vld || (rd_skid5_1_vld && (rd_bypassing5 || rd_take_n_dly[5]))) : (rd_skid5_1_vld || (rd_skid5_0_vld && (rd_bypassing5 || rd_take_n_dly[5]))); +//VCS coverage off + rd_skid5_2_vld <= (cq_rd5_pvld && cq_rd5_prdy) ? (rd_skid5_2_vld && (rd_bypassing5 || rd_take_n_dly[5])) : (rd_skid5_2_vld || (rd_skid5_1_vld && (rd_bypassing5 || rd_take_n_dly[5]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd5_credits; // unused credits +reg cq_rd5_credits_ne0; +wire [8:0] cq_rd5_credits_w_take_next = cq_rd5_credits + cq_rd_credit[5] - 1'b1; +wire [8:0] cq_rd5_credits_wo_take_next = cq_rd5_credits + cq_rd_credit[5]; +wire [8:0] cq_rd5_credits_next = rd_take5 ? cq_rd5_credits_w_take_next : cq_rd5_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[5] = (cq_rd5_prdy_d || !rd_skid5_0_vld || !rd_skid5_1_vld || (!rd_skid5_2_vld && !rd_take_n_dly[5])) && (cq_rd_credit[5] || cq_rd5_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing5 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd5) && cq_rd5_credits == 0 && !cq_rd_credit[5] && (!rd_take_n_dly[5] || rd_skid5_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing5 = rd_pre_bypassing5 && (!rd_skid5_2_vld || !rd_skid5_1_vld || !(!cq_rd5_prdy_d && rd_skid5_0_vld && rd_skid5_1_vld)) && !rd_take_n_dly[5]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd5_credits <= 9'd0; + cq_rd5_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[5] | rd_take5 ) begin + cq_rd5_credits <= cq_rd5_credits_next; + cq_rd5_credits_ne0 <= rd_take5 ? (cq_rd5_credits_w_take_next != 0) : (cq_rd5_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[5] | rd_take5) ) begin + end else begin + cq_rd5_credits <= {9{`x_or_0}}; + cq_rd5_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing6; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing6; // between cq_rd6_pvld and cq_rd6_prdy when doing full bypass +reg [6:0] rd_skid6_0; // head skid reg +reg [6:0] rd_skid6_1; // head+1 skid reg +reg [6:0] rd_skid6_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid6_0_vld; // head skid reg has valid data +reg rd_skid6_1_vld; // head+1 skid reg has valid data +reg rd_skid6_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd6_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd6_prdy_d <= 1'b1; + end else begin + cq_rd6_prdy_d <= cq_rd6_prdy; + end +end +assign cq_rd6_pvld = rd_skid6_0_vld || rd_pre_bypassing6; // full bypass for 0-latency +assign cq_rd6_pd = rd_skid6_0_vld ? rd_skid6_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_0_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_1_vld)) ) begin + rd_skid6_0 <= rd_take_n_dly[6] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd6_pvld && cq_rd6_prdy && rd_skid6_1_vld ) begin + rd_skid6_0 <= rd_skid6_1; + end +//synopsys translate_off + else if ( !((rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_0_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_1_vld))) && + !(cq_rd6_pvld && cq_rd6_prdy && rd_skid6_1_vld) ) begin + end else begin + rd_skid6_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_1_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_2_vld)) ) begin + rd_skid6_1 <= rd_bypassing6 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd6_pvld && cq_rd6_prdy && rd_skid6_2_vld ) begin + rd_skid6_1 <= rd_skid6_2; + end +//synopsys translate_off + else if ( !((rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_1_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_2_vld))) && + !(cq_rd6_pvld && cq_rd6_prdy && rd_skid6_2_vld) ) begin + end else begin + rd_skid6_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing6 || rd_take_n_dly[6]) && rd_skid6_0_vld && rd_skid6_1_vld && (rd_skid6_2_vld || !(cq_rd6_pvld && cq_rd6_prdy)) ) begin + rd_skid6_2 <= rd_bypassing6 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing6 || rd_take_n_dly[6]) && rd_skid6_0_vld && rd_skid6_1_vld && (rd_skid6_2_vld || !(cq_rd6_pvld && cq_rd6_prdy))) ) begin + end else begin + rd_skid6_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid6_0_vld <= 1'b0; + rd_skid6_1_vld <= 1'b0; + rd_skid6_2_vld <= 1'b0; + end else begin + rd_skid6_0_vld <= (cq_rd6_pvld && cq_rd6_prdy) ? (rd_skid6_1_vld || (rd_bypassing6 && rd_skid6_0_vld) || rd_take_n_dly[6]) : (rd_skid6_0_vld || rd_bypassing6 || rd_take_n_dly[6]); + rd_skid6_1_vld <= (cq_rd6_pvld && cq_rd6_prdy) ? (rd_skid6_2_vld || (rd_skid6_1_vld && (rd_bypassing6 || rd_take_n_dly[6]))) : (rd_skid6_1_vld || (rd_skid6_0_vld && (rd_bypassing6 || rd_take_n_dly[6]))); +//VCS coverage off + rd_skid6_2_vld <= (cq_rd6_pvld && cq_rd6_prdy) ? (rd_skid6_2_vld && (rd_bypassing6 || rd_take_n_dly[6])) : (rd_skid6_2_vld || (rd_skid6_1_vld && (rd_bypassing6 || rd_take_n_dly[6]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd6_credits; // unused credits +reg cq_rd6_credits_ne0; +wire [8:0] cq_rd6_credits_w_take_next = cq_rd6_credits + cq_rd_credit[6] - 1'b1; +wire [8:0] cq_rd6_credits_wo_take_next = cq_rd6_credits + cq_rd_credit[6]; +wire [8:0] cq_rd6_credits_next = rd_take6 ? cq_rd6_credits_w_take_next : cq_rd6_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[6] = (cq_rd6_prdy_d || !rd_skid6_0_vld || !rd_skid6_1_vld || (!rd_skid6_2_vld && !rd_take_n_dly[6])) && (cq_rd_credit[6] || cq_rd6_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing6 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd6) && cq_rd6_credits == 0 && !cq_rd_credit[6] && (!rd_take_n_dly[6] || rd_skid6_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing6 = rd_pre_bypassing6 && (!rd_skid6_2_vld || !rd_skid6_1_vld || !(!cq_rd6_prdy_d && rd_skid6_0_vld && rd_skid6_1_vld)) && !rd_take_n_dly[6]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd6_credits <= 9'd0; + cq_rd6_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[6] | rd_take6 ) begin + cq_rd6_credits <= cq_rd6_credits_next; + cq_rd6_credits_ne0 <= rd_take6 ? (cq_rd6_credits_w_take_next != 0) : (cq_rd6_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[6] | rd_take6) ) begin + end else begin + cq_rd6_credits <= {9{`x_or_0}}; + cq_rd6_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing7; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing7; // between cq_rd7_pvld and cq_rd7_prdy when doing full bypass +reg [6:0] rd_skid7_0; // head skid reg +reg [6:0] rd_skid7_1; // head+1 skid reg +reg [6:0] rd_skid7_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid7_0_vld; // head skid reg has valid data +reg rd_skid7_1_vld; // head+1 skid reg has valid data +reg rd_skid7_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd7_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd7_prdy_d <= 1'b1; + end else begin + cq_rd7_prdy_d <= cq_rd7_prdy; + end +end +assign cq_rd7_pvld = rd_skid7_0_vld || rd_pre_bypassing7; // full bypass for 0-latency +assign cq_rd7_pd = rd_skid7_0_vld ? rd_skid7_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_0_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_1_vld)) ) begin + rd_skid7_0 <= rd_take_n_dly[7] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd7_pvld && cq_rd7_prdy && rd_skid7_1_vld ) begin + rd_skid7_0 <= rd_skid7_1; + end +//synopsys translate_off + else if ( !((rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_0_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_1_vld))) && + !(cq_rd7_pvld && cq_rd7_prdy && rd_skid7_1_vld) ) begin + end else begin + rd_skid7_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_1_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_2_vld)) ) begin + rd_skid7_1 <= rd_bypassing7 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd7_pvld && cq_rd7_prdy && rd_skid7_2_vld ) begin + rd_skid7_1 <= rd_skid7_2; + end +//synopsys translate_off + else if ( !((rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_1_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_2_vld))) && + !(cq_rd7_pvld && cq_rd7_prdy && rd_skid7_2_vld) ) begin + end else begin + rd_skid7_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing7 || rd_take_n_dly[7]) && rd_skid7_0_vld && rd_skid7_1_vld && (rd_skid7_2_vld || !(cq_rd7_pvld && cq_rd7_prdy)) ) begin + rd_skid7_2 <= rd_bypassing7 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing7 || rd_take_n_dly[7]) && rd_skid7_0_vld && rd_skid7_1_vld && (rd_skid7_2_vld || !(cq_rd7_pvld && cq_rd7_prdy))) ) begin + end else begin + rd_skid7_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid7_0_vld <= 1'b0; + rd_skid7_1_vld <= 1'b0; + rd_skid7_2_vld <= 1'b0; + end else begin + rd_skid7_0_vld <= (cq_rd7_pvld && cq_rd7_prdy) ? (rd_skid7_1_vld || (rd_bypassing7 && rd_skid7_0_vld) || rd_take_n_dly[7]) : (rd_skid7_0_vld || rd_bypassing7 || rd_take_n_dly[7]); + rd_skid7_1_vld <= (cq_rd7_pvld && cq_rd7_prdy) ? (rd_skid7_2_vld || (rd_skid7_1_vld && (rd_bypassing7 || rd_take_n_dly[7]))) : (rd_skid7_1_vld || (rd_skid7_0_vld && (rd_bypassing7 || rd_take_n_dly[7]))); +//VCS coverage off + rd_skid7_2_vld <= (cq_rd7_pvld && cq_rd7_prdy) ? (rd_skid7_2_vld && (rd_bypassing7 || rd_take_n_dly[7])) : (rd_skid7_2_vld || (rd_skid7_1_vld && (rd_bypassing7 || rd_take_n_dly[7]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd7_credits; // unused credits +reg cq_rd7_credits_ne0; +wire [8:0] cq_rd7_credits_w_take_next = cq_rd7_credits + cq_rd_credit[7] - 1'b1; +wire [8:0] cq_rd7_credits_wo_take_next = cq_rd7_credits + cq_rd_credit[7]; +wire [8:0] cq_rd7_credits_next = rd_take7 ? cq_rd7_credits_w_take_next : cq_rd7_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[7] = (cq_rd7_prdy_d || !rd_skid7_0_vld || !rd_skid7_1_vld || (!rd_skid7_2_vld && !rd_take_n_dly[7])) && (cq_rd_credit[7] || cq_rd7_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing7 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd7) && cq_rd7_credits == 0 && !cq_rd_credit[7] && (!rd_take_n_dly[7] || rd_skid7_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing7 = rd_pre_bypassing7 && (!rd_skid7_2_vld || !rd_skid7_1_vld || !(!cq_rd7_prdy_d && rd_skid7_0_vld && rd_skid7_1_vld)) && !rd_take_n_dly[7]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd7_credits <= 9'd0; + cq_rd7_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[7] | rd_take7 ) begin + cq_rd7_credits <= cq_rd7_credits_next; + cq_rd7_credits_ne0 <= rd_take7 ? (cq_rd7_credits_w_take_next != 0) : (cq_rd7_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[7] | rd_take7) ) begin + end else begin + cq_rd7_credits <= {9{`x_or_0}}; + cq_rd7_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing8; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing8; // between cq_rd8_pvld and cq_rd8_prdy when doing full bypass +reg [6:0] rd_skid8_0; // head skid reg +reg [6:0] rd_skid8_1; // head+1 skid reg +reg [6:0] rd_skid8_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid8_0_vld; // head skid reg has valid data +reg rd_skid8_1_vld; // head+1 skid reg has valid data +reg rd_skid8_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd8_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd8_prdy_d <= 1'b1; + end else begin + cq_rd8_prdy_d <= cq_rd8_prdy; + end +end +assign cq_rd8_pvld = rd_skid8_0_vld || rd_pre_bypassing8; // full bypass for 0-latency +assign cq_rd8_pd = rd_skid8_0_vld ? rd_skid8_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_0_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_1_vld)) ) begin + rd_skid8_0 <= rd_take_n_dly[8] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd8_pvld && cq_rd8_prdy && rd_skid8_1_vld ) begin + rd_skid8_0 <= rd_skid8_1; + end +//synopsys translate_off + else if ( !((rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_0_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_1_vld))) && + !(cq_rd8_pvld && cq_rd8_prdy && rd_skid8_1_vld) ) begin + end else begin + rd_skid8_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_1_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_2_vld)) ) begin + rd_skid8_1 <= rd_bypassing8 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd8_pvld && cq_rd8_prdy && rd_skid8_2_vld ) begin + rd_skid8_1 <= rd_skid8_2; + end +//synopsys translate_off + else if ( !((rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_1_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_2_vld))) && + !(cq_rd8_pvld && cq_rd8_prdy && rd_skid8_2_vld) ) begin + end else begin + rd_skid8_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing8 || rd_take_n_dly[8]) && rd_skid8_0_vld && rd_skid8_1_vld && (rd_skid8_2_vld || !(cq_rd8_pvld && cq_rd8_prdy)) ) begin + rd_skid8_2 <= rd_bypassing8 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing8 || rd_take_n_dly[8]) && rd_skid8_0_vld && rd_skid8_1_vld && (rd_skid8_2_vld || !(cq_rd8_pvld && cq_rd8_prdy))) ) begin + end else begin + rd_skid8_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid8_0_vld <= 1'b0; + rd_skid8_1_vld <= 1'b0; + rd_skid8_2_vld <= 1'b0; + end else begin + rd_skid8_0_vld <= (cq_rd8_pvld && cq_rd8_prdy) ? (rd_skid8_1_vld || (rd_bypassing8 && rd_skid8_0_vld) || rd_take_n_dly[8]) : (rd_skid8_0_vld || rd_bypassing8 || rd_take_n_dly[8]); + rd_skid8_1_vld <= (cq_rd8_pvld && cq_rd8_prdy) ? (rd_skid8_2_vld || (rd_skid8_1_vld && (rd_bypassing8 || rd_take_n_dly[8]))) : (rd_skid8_1_vld || (rd_skid8_0_vld && (rd_bypassing8 || rd_take_n_dly[8]))); +//VCS coverage off + rd_skid8_2_vld <= (cq_rd8_pvld && cq_rd8_prdy) ? (rd_skid8_2_vld && (rd_bypassing8 || rd_take_n_dly[8])) : (rd_skid8_2_vld || (rd_skid8_1_vld && (rd_bypassing8 || rd_take_n_dly[8]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd8_credits; // unused credits +reg cq_rd8_credits_ne0; +wire [8:0] cq_rd8_credits_w_take_next = cq_rd8_credits + cq_rd_credit[8] - 1'b1; +wire [8:0] cq_rd8_credits_wo_take_next = cq_rd8_credits + cq_rd_credit[8]; +wire [8:0] cq_rd8_credits_next = rd_take8 ? cq_rd8_credits_w_take_next : cq_rd8_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[8] = (cq_rd8_prdy_d || !rd_skid8_0_vld || !rd_skid8_1_vld || (!rd_skid8_2_vld && !rd_take_n_dly[8])) && (cq_rd_credit[8] || cq_rd8_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing8 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd8) && cq_rd8_credits == 0 && !cq_rd_credit[8] && (!rd_take_n_dly[8] || rd_skid8_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing8 = rd_pre_bypassing8 && (!rd_skid8_2_vld || !rd_skid8_1_vld || !(!cq_rd8_prdy_d && rd_skid8_0_vld && rd_skid8_1_vld)) && !rd_take_n_dly[8]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd8_credits <= 9'd0; + cq_rd8_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[8] | rd_take8 ) begin + cq_rd8_credits <= cq_rd8_credits_next; + cq_rd8_credits_ne0 <= rd_take8 ? (cq_rd8_credits_w_take_next != 0) : (cq_rd8_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[8] | rd_take8) ) begin + end else begin + cq_rd8_credits <= {9{`x_or_0}}; + cq_rd8_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing9; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing9; // between cq_rd9_pvld and cq_rd9_prdy when doing full bypass +reg [6:0] rd_skid9_0; // head skid reg +reg [6:0] rd_skid9_1; // head+1 skid reg +reg [6:0] rd_skid9_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid9_0_vld; // head skid reg has valid data +reg rd_skid9_1_vld; // head+1 skid reg has valid data +reg rd_skid9_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd9_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd9_prdy_d <= 1'b1; + end else begin + cq_rd9_prdy_d <= cq_rd9_prdy; + end +end +assign cq_rd9_pvld = rd_skid9_0_vld || rd_pre_bypassing9; // full bypass for 0-latency +assign cq_rd9_pd = rd_skid9_0_vld ? rd_skid9_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_0_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_1_vld)) ) begin + rd_skid9_0 <= rd_take_n_dly[9] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd9_pvld && cq_rd9_prdy && rd_skid9_1_vld ) begin + rd_skid9_0 <= rd_skid9_1; + end +//synopsys translate_off + else if ( !((rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_0_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_1_vld))) && + !(cq_rd9_pvld && cq_rd9_prdy && rd_skid9_1_vld) ) begin + end else begin + rd_skid9_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_1_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_2_vld)) ) begin + rd_skid9_1 <= rd_bypassing9 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd9_pvld && cq_rd9_prdy && rd_skid9_2_vld ) begin + rd_skid9_1 <= rd_skid9_2; + end +//synopsys translate_off + else if ( !((rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_1_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_2_vld))) && + !(cq_rd9_pvld && cq_rd9_prdy && rd_skid9_2_vld) ) begin + end else begin + rd_skid9_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing9 || rd_take_n_dly[9]) && rd_skid9_0_vld && rd_skid9_1_vld && (rd_skid9_2_vld || !(cq_rd9_pvld && cq_rd9_prdy)) ) begin + rd_skid9_2 <= rd_bypassing9 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing9 || rd_take_n_dly[9]) && rd_skid9_0_vld && rd_skid9_1_vld && (rd_skid9_2_vld || !(cq_rd9_pvld && cq_rd9_prdy))) ) begin + end else begin + rd_skid9_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid9_0_vld <= 1'b0; + rd_skid9_1_vld <= 1'b0; + rd_skid9_2_vld <= 1'b0; + end else begin + rd_skid9_0_vld <= (cq_rd9_pvld && cq_rd9_prdy) ? (rd_skid9_1_vld || (rd_bypassing9 && rd_skid9_0_vld) || rd_take_n_dly[9]) : (rd_skid9_0_vld || rd_bypassing9 || rd_take_n_dly[9]); + rd_skid9_1_vld <= (cq_rd9_pvld && cq_rd9_prdy) ? (rd_skid9_2_vld || (rd_skid9_1_vld && (rd_bypassing9 || rd_take_n_dly[9]))) : (rd_skid9_1_vld || (rd_skid9_0_vld && (rd_bypassing9 || rd_take_n_dly[9]))); +//VCS coverage off + rd_skid9_2_vld <= (cq_rd9_pvld && cq_rd9_prdy) ? (rd_skid9_2_vld && (rd_bypassing9 || rd_take_n_dly[9])) : (rd_skid9_2_vld || (rd_skid9_1_vld && (rd_bypassing9 || rd_take_n_dly[9]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd9_credits; // unused credits +reg cq_rd9_credits_ne0; +wire [8:0] cq_rd9_credits_w_take_next = cq_rd9_credits + cq_rd_credit[9] - 1'b1; +wire [8:0] cq_rd9_credits_wo_take_next = cq_rd9_credits + cq_rd_credit[9]; +wire [8:0] cq_rd9_credits_next = rd_take9 ? cq_rd9_credits_w_take_next : cq_rd9_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[9] = (cq_rd9_prdy_d || !rd_skid9_0_vld || !rd_skid9_1_vld || (!rd_skid9_2_vld && !rd_take_n_dly[9])) && (cq_rd_credit[9] || cq_rd9_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing9 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd9) && cq_rd9_credits == 0 && !cq_rd_credit[9] && (!rd_take_n_dly[9] || rd_skid9_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing9 = rd_pre_bypassing9 && (!rd_skid9_2_vld || !rd_skid9_1_vld || !(!cq_rd9_prdy_d && rd_skid9_0_vld && rd_skid9_1_vld)) && !rd_take_n_dly[9]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd9_credits <= 9'd0; + cq_rd9_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[9] | rd_take9 ) begin + cq_rd9_credits <= cq_rd9_credits_next; + cq_rd9_credits_ne0 <= rd_take9 ? (cq_rd9_credits_w_take_next != 0) : (cq_rd9_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[9] | rd_take9) ) begin + end else begin + cq_rd9_credits <= {9{`x_or_0}}; + cq_rd9_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +// rd_take round-robin arbiter (similar to arbgen output) +// +assign cq_rd_take = |cq_rd_take_elig; // any thread is eligible to take, so issue take +reg [3:0] cq_rd_take_thread_id_last; +wire [9:0] cq_rd_take_thread_id_is_1 = { + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd0}; +wire [9:0] cq_rd_take_thread_id_is_2 = { + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd1, + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1]}; +wire [9:0] cq_rd_take_thread_id_is_3 = { + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd2, + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2]}; +wire [9:0] cq_rd_take_thread_id_is_4 = { + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd3, + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3]}; +wire [9:0] cq_rd_take_thread_id_is_5 = { + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd4, + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4]}; +wire [9:0] cq_rd_take_thread_id_is_6 = { + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd5, + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5]}; +wire [9:0] cq_rd_take_thread_id_is_7 = { + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd6, + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6]}; +wire [9:0] cq_rd_take_thread_id_is_8 = { + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd7, + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7]}; +wire [9:0] cq_rd_take_thread_id_is_9 = { + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd8, + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8]}; +assign cq_rd_take_thread_id[0] = |{cq_rd_take_thread_id_is_1,cq_rd_take_thread_id_is_3,cq_rd_take_thread_id_is_5,cq_rd_take_thread_id_is_7,cq_rd_take_thread_id_is_9}; +assign cq_rd_take_thread_id[1] = |{cq_rd_take_thread_id_is_2,cq_rd_take_thread_id_is_3,cq_rd_take_thread_id_is_6,cq_rd_take_thread_id_is_7}; +assign cq_rd_take_thread_id[2] = |{cq_rd_take_thread_id_is_4,cq_rd_take_thread_id_is_5,cq_rd_take_thread_id_is_6,cq_rd_take_thread_id_is_7}; +assign cq_rd_take_thread_id[3] = |{cq_rd_take_thread_id_is_8,cq_rd_take_thread_id_is_9}; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_take_thread_id_last <= 4'd0; + end else begin + if ( cq_rd_take ) begin + cq_rd_take_thread_id_last <= cq_rd_take_thread_id; + end +//synopsys translate_off + else if ( !cq_rd_take ) begin + end else begin + cq_rd_take_thread_id_last <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +assign wr_bypassing = rd_bypassing0 || rd_bypassing1 || rd_bypassing2 || rd_bypassing3 || rd_bypassing4 || rd_bypassing5 || rd_bypassing6 || rd_bypassing7 || rd_bypassing8 || rd_bypassing9; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next) || rd_popping) || (rd_pushing || cq_rd_take || cq_rd_credit != 10'd0 || rd_take_dly)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +assign nvdla_core_clk_mgated_skid_enable = nvdla_core_clk_mgated_enable || ( cq_rd0_pvld && cq_rd0_prdy ) || rd_bypassing0 || ( cq_rd1_pvld && cq_rd1_prdy ) || rd_bypassing1 || ( cq_rd2_pvld && cq_rd2_prdy ) || rd_bypassing2 || ( cq_rd3_pvld && cq_rd3_prdy ) || rd_bypassing3 || ( cq_rd4_pvld && cq_rd4_prdy ) || rd_bypassing4 || ( cq_rd5_pvld && cq_rd5_prdy ) || rd_bypassing5 || ( cq_rd6_pvld && cq_rd6_prdy ) || rd_bypassing6 || ( cq_rd7_pvld && cq_rd7_prdy ) || rd_bypassing7 || ( cq_rd8_pvld && cq_rd8_prdy ) || rd_bypassing8 || ( cq_rd9_pvld && cq_rd9_prdy ) || rd_bypassing9 + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit : 9'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 9'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 9'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 9'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [8:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cq_wr_pvld && !(!cq_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} ) + , .curr ( {23'd0, cq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check0 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd0 ), + .credit ( cq_rd_credit[0] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check1 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd1 ), + .credit ( cq_rd_credit[1] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check2 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd2 ), + .credit ( cq_rd_credit[2] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check3 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd3 ), + .credit ( cq_rd_credit[3] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check4 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd4 ), + .credit ( cq_rd_credit[4] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check5 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd5 ), + .credit ( cq_rd_credit[5] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check6 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd6 ), + .credit ( cq_rd_credit[6] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check7 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd7 ), + .credit ( cq_rd_credit[7] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check8 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd8 ), + .credit ( cq_rd_credit[8] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check9 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd9 ), + .credit ( cq_rd_credit[9] ) + ); +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_READ_cq") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_READ_cq +// +// generate free list fifo for use from read side to write side +// diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v.vcp new file mode 100644 index 0000000..6e8dbc9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v.vcp @@ -0,0 +1,4094 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_READ_cq ( + nvdla_core_clk + , nvdla_core_rstn + , cq_wr_prdy + , cq_wr_pvld + , cq_wr_thread_id +`ifdef FV_RAND_WR_PAUSE + , cq_wr_pause +`endif + , cq_wr_pd + , cq_rd0_prdy + , cq_rd0_pvld + , cq_rd0_pd + , cq_rd1_prdy + , cq_rd1_pvld + , cq_rd1_pd + , cq_rd2_prdy + , cq_rd2_pvld + , cq_rd2_pd + , cq_rd3_prdy + , cq_rd3_pvld + , cq_rd3_pd + , cq_rd4_prdy + , cq_rd4_pvld + , cq_rd4_pd + , cq_rd5_prdy + , cq_rd5_pvld + , cq_rd5_pd + , cq_rd6_prdy + , cq_rd6_pvld + , cq_rd6_pd + , cq_rd7_prdy + , cq_rd7_pvld + , cq_rd7_pd + , cq_rd8_prdy + , cq_rd8_pvld + , cq_rd8_pd + , cq_rd9_prdy + , cq_rd9_pvld + , cq_rd9_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cq_wr_prdy; +input cq_wr_pvld; +input [3:0] cq_wr_thread_id; +`ifdef FV_RAND_WR_PAUSE +input cq_wr_pause; +`endif +input [6:0] cq_wr_pd; +input cq_rd0_prdy; +output cq_rd0_pvld; +output [6:0] cq_rd0_pd; +input cq_rd1_prdy; +output cq_rd1_pvld; +output [6:0] cq_rd1_pd; +input cq_rd2_prdy; +output cq_rd2_pvld; +output [6:0] cq_rd2_pd; +input cq_rd3_prdy; +output cq_rd3_pvld; +output [6:0] cq_rd3_pd; +input cq_rd4_prdy; +output cq_rd4_pvld; +output [6:0] cq_rd4_pd; +input cq_rd5_prdy; +output cq_rd5_pvld; +output [6:0] cq_rd5_pd; +input cq_rd6_prdy; +output cq_rd6_pvld; +output [6:0] cq_rd6_pd; +input cq_rd7_prdy; +output cq_rd7_pvld; +output [6:0] cq_rd7_pd; +input cq_rd8_prdy; +output cq_rd8_pvld; +output [6:0] cq_rd8_pd; +input cq_rd9_prdy; +output cq_rd9_pvld; +output [6:0] cq_rd9_pd; +input [31:0] pwrbus_ram_pd; +// -rd_take_to_rd_busy internal credit/take/data signals (which would have been ports) +// +//wire [9:0] cq_rd_credit; +wire cq_rd_take; +wire [6:0] cq_rd_pd_p; +wire [3:0] cq_rd_take_thread_id; +// We also declare some per-thread flags that indicate whether to have the write bypass the internal fifo. +// These per-class wr_bypassing* flags are set by the take-side logic. We basically pretend that we never pushed the fifo, +// but make sure we return a credit to the sender. +// +wire wr_bypassing; // any thread bypassed +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_skid; +wire nvdla_core_clk_mgated_skid_enable; +NV_CLK_gate_power nvdla_core_clk_rd_mgate_skid( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_skid_enable), .clk_gated(nvdla_core_clk_mgated_skid) ); +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cq_wr_busy_int; // copy for internal use +assign cq_wr_prdy = !cq_wr_busy_int; +assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [8:0] cq_wr_count; // write-side count +wire wr_reserving_and_not_bypassing = wr_reserving && !wr_bypassing; +wire [8:0] wr_count_next_wr_popping = wr_reserving_and_not_bypassing ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [8:0] wr_count_next_no_wr_popping = wr_reserving_and_not_bypassing ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484 +wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 ); +wire wr_count_next_is_256 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_256; +wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [8:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || cq_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_busy_int <= 1'b0; + cq_wr_count <= 9'd0; + end else begin + cq_wr_busy_int <= cq_wr_busy_next; + if ( wr_reserving_and_not_bypassing ^ wr_popping ) begin + cq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving_and_not_bypassing ^ wr_popping) ) begin + end else begin + cq_wr_count <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving && !wr_bypassing; // data pushed same cycle as cq_wr_pvld +wire [3:0] wr_pushing_thread_id = cq_wr_thread_id; // thread being written +// +// RAM +// +wire wr_adr_popping = wr_pushing; // pop free list when wr_pushing=1 +wire [7:0] cq_wr_adr; // current write address +reg [7:0] cq_rd_adr; +wire [7:0] cq_rd_adr_p = cq_rd_adr; // read address to use for ram +wire rd_enable; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rws_256x7 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( cq_wr_adr ) + , .we ( wr_pushing ) + , .di ( cq_wr_pd ) + , .ra ( cq_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( cq_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +// +// SYNCHRONOUS BOUNDARY +// +wire rd_pushing = wr_pushing; // let it be seen immediately +wire [3:0] rd_pushing_thread_id = wr_pushing_thread_id; +wire [7:0] rd_pushing_adr = cq_wr_adr; +// +// MULTITHREADED FREE LIST FIFO +// +// free list of cq_wr_adr's from read side to write side +// these are passed in a ff fifo when the fifo is popped +// +// there's an extra mux of the internal flops that is +// used to determine which address to use when +// rd_pushing is 1 if the fifo is async. +// +wire [7:0] rd_popping_adr; // cq_rd_adr to free up +wire [7:0] free_adr_index; +reg [255-1:0] free_adr_mask_next; +reg [255-1:0] free_adr_mask; +assign cq_wr_adr = free_adr_index; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + free_adr_mask <= {255{1'b1}}; + end else begin + if ( rd_popping || wr_adr_popping ) begin + free_adr_mask <= free_adr_mask_next; + end +//synopsys translate_off + else if ( !(rd_popping || wr_adr_popping) ) begin + end else begin + free_adr_mask <= {255{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(*) begin + free_adr_mask_next = free_adr_mask; + if ( rd_popping && rd_popping_adr == 8'd0 ) begin + free_adr_mask_next[0] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd0 ) begin + free_adr_mask_next[0] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd1 ) begin + free_adr_mask_next[1] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd1 ) begin + free_adr_mask_next[1] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd2 ) begin + free_adr_mask_next[2] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd2 ) begin + free_adr_mask_next[2] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd3 ) begin + free_adr_mask_next[3] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd3 ) begin + free_adr_mask_next[3] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd4 ) begin + free_adr_mask_next[4] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd4 ) begin + free_adr_mask_next[4] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd5 ) begin + free_adr_mask_next[5] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd5 ) begin + free_adr_mask_next[5] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd6 ) begin + free_adr_mask_next[6] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd6 ) begin + free_adr_mask_next[6] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd7 ) begin + free_adr_mask_next[7] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd7 ) begin + free_adr_mask_next[7] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd8 ) begin + free_adr_mask_next[8] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd8 ) begin + free_adr_mask_next[8] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd9 ) begin + free_adr_mask_next[9] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd9 ) begin + free_adr_mask_next[9] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd10 ) begin + free_adr_mask_next[10] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd10 ) begin + free_adr_mask_next[10] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd11 ) begin + free_adr_mask_next[11] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd11 ) begin + free_adr_mask_next[11] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd12 ) begin + free_adr_mask_next[12] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd12 ) begin + free_adr_mask_next[12] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd13 ) begin + free_adr_mask_next[13] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd13 ) begin + free_adr_mask_next[13] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd14 ) begin + free_adr_mask_next[14] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd14 ) begin + free_adr_mask_next[14] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd15 ) begin + free_adr_mask_next[15] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd15 ) begin + free_adr_mask_next[15] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd16 ) begin + free_adr_mask_next[16] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd16 ) begin + free_adr_mask_next[16] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd17 ) begin + free_adr_mask_next[17] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd17 ) begin + free_adr_mask_next[17] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd18 ) begin + free_adr_mask_next[18] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd18 ) begin + free_adr_mask_next[18] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd19 ) begin + free_adr_mask_next[19] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd19 ) begin + free_adr_mask_next[19] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd20 ) begin + free_adr_mask_next[20] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd20 ) begin + free_adr_mask_next[20] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd21 ) begin + free_adr_mask_next[21] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd21 ) begin + free_adr_mask_next[21] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd22 ) begin + free_adr_mask_next[22] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd22 ) begin + free_adr_mask_next[22] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd23 ) begin + free_adr_mask_next[23] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd23 ) begin + free_adr_mask_next[23] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd24 ) begin + free_adr_mask_next[24] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd24 ) begin + free_adr_mask_next[24] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd25 ) begin + free_adr_mask_next[25] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd25 ) begin + free_adr_mask_next[25] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd26 ) begin + free_adr_mask_next[26] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd26 ) begin + free_adr_mask_next[26] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd27 ) begin + free_adr_mask_next[27] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd27 ) begin + free_adr_mask_next[27] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd28 ) begin + free_adr_mask_next[28] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd28 ) begin + free_adr_mask_next[28] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd29 ) begin + free_adr_mask_next[29] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd29 ) begin + free_adr_mask_next[29] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd30 ) begin + free_adr_mask_next[30] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd30 ) begin + free_adr_mask_next[30] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd31 ) begin + free_adr_mask_next[31] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd31 ) begin + free_adr_mask_next[31] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd32 ) begin + free_adr_mask_next[32] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd32 ) begin + free_adr_mask_next[32] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd33 ) begin + free_adr_mask_next[33] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd33 ) begin + free_adr_mask_next[33] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd34 ) begin + free_adr_mask_next[34] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd34 ) begin + free_adr_mask_next[34] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd35 ) begin + free_adr_mask_next[35] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd35 ) begin + free_adr_mask_next[35] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd36 ) begin + free_adr_mask_next[36] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd36 ) begin + free_adr_mask_next[36] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd37 ) begin + free_adr_mask_next[37] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd37 ) begin + free_adr_mask_next[37] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd38 ) begin + free_adr_mask_next[38] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd38 ) begin + free_adr_mask_next[38] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd39 ) begin + free_adr_mask_next[39] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd39 ) begin + free_adr_mask_next[39] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd40 ) begin + free_adr_mask_next[40] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd40 ) begin + free_adr_mask_next[40] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd41 ) begin + free_adr_mask_next[41] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd41 ) begin + free_adr_mask_next[41] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd42 ) begin + free_adr_mask_next[42] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd42 ) begin + free_adr_mask_next[42] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd43 ) begin + free_adr_mask_next[43] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd43 ) begin + free_adr_mask_next[43] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd44 ) begin + free_adr_mask_next[44] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd44 ) begin + free_adr_mask_next[44] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd45 ) begin + free_adr_mask_next[45] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd45 ) begin + free_adr_mask_next[45] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd46 ) begin + free_adr_mask_next[46] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd46 ) begin + free_adr_mask_next[46] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd47 ) begin + free_adr_mask_next[47] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd47 ) begin + free_adr_mask_next[47] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd48 ) begin + free_adr_mask_next[48] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd48 ) begin + free_adr_mask_next[48] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd49 ) begin + free_adr_mask_next[49] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd49 ) begin + free_adr_mask_next[49] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd50 ) begin + free_adr_mask_next[50] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd50 ) begin + free_adr_mask_next[50] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd51 ) begin + free_adr_mask_next[51] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd51 ) begin + free_adr_mask_next[51] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd52 ) begin + free_adr_mask_next[52] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd52 ) begin + free_adr_mask_next[52] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd53 ) begin + free_adr_mask_next[53] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd53 ) begin + free_adr_mask_next[53] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd54 ) begin + free_adr_mask_next[54] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd54 ) begin + free_adr_mask_next[54] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd55 ) begin + free_adr_mask_next[55] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd55 ) begin + free_adr_mask_next[55] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd56 ) begin + free_adr_mask_next[56] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd56 ) begin + free_adr_mask_next[56] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd57 ) begin + free_adr_mask_next[57] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd57 ) begin + free_adr_mask_next[57] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd58 ) begin + free_adr_mask_next[58] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd58 ) begin + free_adr_mask_next[58] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd59 ) begin + free_adr_mask_next[59] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd59 ) begin + free_adr_mask_next[59] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd60 ) begin + free_adr_mask_next[60] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd60 ) begin + free_adr_mask_next[60] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd61 ) begin + free_adr_mask_next[61] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd61 ) begin + free_adr_mask_next[61] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd62 ) begin + free_adr_mask_next[62] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd62 ) begin + free_adr_mask_next[62] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd63 ) begin + free_adr_mask_next[63] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd63 ) begin + free_adr_mask_next[63] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd64 ) begin + free_adr_mask_next[64] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd64 ) begin + free_adr_mask_next[64] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd65 ) begin + free_adr_mask_next[65] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd65 ) begin + free_adr_mask_next[65] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd66 ) begin + free_adr_mask_next[66] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd66 ) begin + free_adr_mask_next[66] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd67 ) begin + free_adr_mask_next[67] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd67 ) begin + free_adr_mask_next[67] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd68 ) begin + free_adr_mask_next[68] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd68 ) begin + free_adr_mask_next[68] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd69 ) begin + free_adr_mask_next[69] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd69 ) begin + free_adr_mask_next[69] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd70 ) begin + free_adr_mask_next[70] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd70 ) begin + free_adr_mask_next[70] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd71 ) begin + free_adr_mask_next[71] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd71 ) begin + free_adr_mask_next[71] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd72 ) begin + free_adr_mask_next[72] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd72 ) begin + free_adr_mask_next[72] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd73 ) begin + free_adr_mask_next[73] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd73 ) begin + free_adr_mask_next[73] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd74 ) begin + free_adr_mask_next[74] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd74 ) begin + free_adr_mask_next[74] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd75 ) begin + free_adr_mask_next[75] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd75 ) begin + free_adr_mask_next[75] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd76 ) begin + free_adr_mask_next[76] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd76 ) begin + free_adr_mask_next[76] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd77 ) begin + free_adr_mask_next[77] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd77 ) begin + free_adr_mask_next[77] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd78 ) begin + free_adr_mask_next[78] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd78 ) begin + free_adr_mask_next[78] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd79 ) begin + free_adr_mask_next[79] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd79 ) begin + free_adr_mask_next[79] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd80 ) begin + free_adr_mask_next[80] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd80 ) begin + free_adr_mask_next[80] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd81 ) begin + free_adr_mask_next[81] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd81 ) begin + free_adr_mask_next[81] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd82 ) begin + free_adr_mask_next[82] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd82 ) begin + free_adr_mask_next[82] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd83 ) begin + free_adr_mask_next[83] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd83 ) begin + free_adr_mask_next[83] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd84 ) begin + free_adr_mask_next[84] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd84 ) begin + free_adr_mask_next[84] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd85 ) begin + free_adr_mask_next[85] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd85 ) begin + free_adr_mask_next[85] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd86 ) begin + free_adr_mask_next[86] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd86 ) begin + free_adr_mask_next[86] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd87 ) begin + free_adr_mask_next[87] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd87 ) begin + free_adr_mask_next[87] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd88 ) begin + free_adr_mask_next[88] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd88 ) begin + free_adr_mask_next[88] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd89 ) begin + free_adr_mask_next[89] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd89 ) begin + free_adr_mask_next[89] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd90 ) begin + free_adr_mask_next[90] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd90 ) begin + free_adr_mask_next[90] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd91 ) begin + free_adr_mask_next[91] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd91 ) begin + free_adr_mask_next[91] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd92 ) begin + free_adr_mask_next[92] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd92 ) begin + free_adr_mask_next[92] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd93 ) begin + free_adr_mask_next[93] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd93 ) begin + free_adr_mask_next[93] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd94 ) begin + free_adr_mask_next[94] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd94 ) begin + free_adr_mask_next[94] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd95 ) begin + free_adr_mask_next[95] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd95 ) begin + free_adr_mask_next[95] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd96 ) begin + free_adr_mask_next[96] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd96 ) begin + free_adr_mask_next[96] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd97 ) begin + free_adr_mask_next[97] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd97 ) begin + free_adr_mask_next[97] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd98 ) begin + free_adr_mask_next[98] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd98 ) begin + free_adr_mask_next[98] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd99 ) begin + free_adr_mask_next[99] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd99 ) begin + free_adr_mask_next[99] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd100 ) begin + free_adr_mask_next[100] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd100 ) begin + free_adr_mask_next[100] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd101 ) begin + free_adr_mask_next[101] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd101 ) begin + free_adr_mask_next[101] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd102 ) begin + free_adr_mask_next[102] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd102 ) begin + free_adr_mask_next[102] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd103 ) begin + free_adr_mask_next[103] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd103 ) begin + free_adr_mask_next[103] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd104 ) begin + free_adr_mask_next[104] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd104 ) begin + free_adr_mask_next[104] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd105 ) begin + free_adr_mask_next[105] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd105 ) begin + free_adr_mask_next[105] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd106 ) begin + free_adr_mask_next[106] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd106 ) begin + free_adr_mask_next[106] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd107 ) begin + free_adr_mask_next[107] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd107 ) begin + free_adr_mask_next[107] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd108 ) begin + free_adr_mask_next[108] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd108 ) begin + free_adr_mask_next[108] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd109 ) begin + free_adr_mask_next[109] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd109 ) begin + free_adr_mask_next[109] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd110 ) begin + free_adr_mask_next[110] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd110 ) begin + free_adr_mask_next[110] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd111 ) begin + free_adr_mask_next[111] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd111 ) begin + free_adr_mask_next[111] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd112 ) begin + free_adr_mask_next[112] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd112 ) begin + free_adr_mask_next[112] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd113 ) begin + free_adr_mask_next[113] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd113 ) begin + free_adr_mask_next[113] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd114 ) begin + free_adr_mask_next[114] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd114 ) begin + free_adr_mask_next[114] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd115 ) begin + free_adr_mask_next[115] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd115 ) begin + free_adr_mask_next[115] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd116 ) begin + free_adr_mask_next[116] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd116 ) begin + free_adr_mask_next[116] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd117 ) begin + free_adr_mask_next[117] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd117 ) begin + free_adr_mask_next[117] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd118 ) begin + free_adr_mask_next[118] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd118 ) begin + free_adr_mask_next[118] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd119 ) begin + free_adr_mask_next[119] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd119 ) begin + free_adr_mask_next[119] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd120 ) begin + free_adr_mask_next[120] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd120 ) begin + free_adr_mask_next[120] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd121 ) begin + free_adr_mask_next[121] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd121 ) begin + free_adr_mask_next[121] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd122 ) begin + free_adr_mask_next[122] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd122 ) begin + free_adr_mask_next[122] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd123 ) begin + free_adr_mask_next[123] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd123 ) begin + free_adr_mask_next[123] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd124 ) begin + free_adr_mask_next[124] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd124 ) begin + free_adr_mask_next[124] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd125 ) begin + free_adr_mask_next[125] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd125 ) begin + free_adr_mask_next[125] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd126 ) begin + free_adr_mask_next[126] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd126 ) begin + free_adr_mask_next[126] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd127 ) begin + free_adr_mask_next[127] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd127 ) begin + free_adr_mask_next[127] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd128 ) begin + free_adr_mask_next[128] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd128 ) begin + free_adr_mask_next[128] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd129 ) begin + free_adr_mask_next[129] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd129 ) begin + free_adr_mask_next[129] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd130 ) begin + free_adr_mask_next[130] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd130 ) begin + free_adr_mask_next[130] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd131 ) begin + free_adr_mask_next[131] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd131 ) begin + free_adr_mask_next[131] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd132 ) begin + free_adr_mask_next[132] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd132 ) begin + free_adr_mask_next[132] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd133 ) begin + free_adr_mask_next[133] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd133 ) begin + free_adr_mask_next[133] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd134 ) begin + free_adr_mask_next[134] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd134 ) begin + free_adr_mask_next[134] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd135 ) begin + free_adr_mask_next[135] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd135 ) begin + free_adr_mask_next[135] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd136 ) begin + free_adr_mask_next[136] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd136 ) begin + free_adr_mask_next[136] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd137 ) begin + free_adr_mask_next[137] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd137 ) begin + free_adr_mask_next[137] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd138 ) begin + free_adr_mask_next[138] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd138 ) begin + free_adr_mask_next[138] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd139 ) begin + free_adr_mask_next[139] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd139 ) begin + free_adr_mask_next[139] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd140 ) begin + free_adr_mask_next[140] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd140 ) begin + free_adr_mask_next[140] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd141 ) begin + free_adr_mask_next[141] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd141 ) begin + free_adr_mask_next[141] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd142 ) begin + free_adr_mask_next[142] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd142 ) begin + free_adr_mask_next[142] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd143 ) begin + free_adr_mask_next[143] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd143 ) begin + free_adr_mask_next[143] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd144 ) begin + free_adr_mask_next[144] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd144 ) begin + free_adr_mask_next[144] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd145 ) begin + free_adr_mask_next[145] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd145 ) begin + free_adr_mask_next[145] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd146 ) begin + free_adr_mask_next[146] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd146 ) begin + free_adr_mask_next[146] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd147 ) begin + free_adr_mask_next[147] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd147 ) begin + free_adr_mask_next[147] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd148 ) begin + free_adr_mask_next[148] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd148 ) begin + free_adr_mask_next[148] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd149 ) begin + free_adr_mask_next[149] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd149 ) begin + free_adr_mask_next[149] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd150 ) begin + free_adr_mask_next[150] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd150 ) begin + free_adr_mask_next[150] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd151 ) begin + free_adr_mask_next[151] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd151 ) begin + free_adr_mask_next[151] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd152 ) begin + free_adr_mask_next[152] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd152 ) begin + free_adr_mask_next[152] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd153 ) begin + free_adr_mask_next[153] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd153 ) begin + free_adr_mask_next[153] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd154 ) begin + free_adr_mask_next[154] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd154 ) begin + free_adr_mask_next[154] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd155 ) begin + free_adr_mask_next[155] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd155 ) begin + free_adr_mask_next[155] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd156 ) begin + free_adr_mask_next[156] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd156 ) begin + free_adr_mask_next[156] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd157 ) begin + free_adr_mask_next[157] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd157 ) begin + free_adr_mask_next[157] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd158 ) begin + free_adr_mask_next[158] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd158 ) begin + free_adr_mask_next[158] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd159 ) begin + free_adr_mask_next[159] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd159 ) begin + free_adr_mask_next[159] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd160 ) begin + free_adr_mask_next[160] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd160 ) begin + free_adr_mask_next[160] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd161 ) begin + free_adr_mask_next[161] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd161 ) begin + free_adr_mask_next[161] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd162 ) begin + free_adr_mask_next[162] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd162 ) begin + free_adr_mask_next[162] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd163 ) begin + free_adr_mask_next[163] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd163 ) begin + free_adr_mask_next[163] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd164 ) begin + free_adr_mask_next[164] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd164 ) begin + free_adr_mask_next[164] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd165 ) begin + free_adr_mask_next[165] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd165 ) begin + free_adr_mask_next[165] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd166 ) begin + free_adr_mask_next[166] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd166 ) begin + free_adr_mask_next[166] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd167 ) begin + free_adr_mask_next[167] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd167 ) begin + free_adr_mask_next[167] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd168 ) begin + free_adr_mask_next[168] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd168 ) begin + free_adr_mask_next[168] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd169 ) begin + free_adr_mask_next[169] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd169 ) begin + free_adr_mask_next[169] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd170 ) begin + free_adr_mask_next[170] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd170 ) begin + free_adr_mask_next[170] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd171 ) begin + free_adr_mask_next[171] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd171 ) begin + free_adr_mask_next[171] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd172 ) begin + free_adr_mask_next[172] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd172 ) begin + free_adr_mask_next[172] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd173 ) begin + free_adr_mask_next[173] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd173 ) begin + free_adr_mask_next[173] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd174 ) begin + free_adr_mask_next[174] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd174 ) begin + free_adr_mask_next[174] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd175 ) begin + free_adr_mask_next[175] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd175 ) begin + free_adr_mask_next[175] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd176 ) begin + free_adr_mask_next[176] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd176 ) begin + free_adr_mask_next[176] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd177 ) begin + free_adr_mask_next[177] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd177 ) begin + free_adr_mask_next[177] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd178 ) begin + free_adr_mask_next[178] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd178 ) begin + free_adr_mask_next[178] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd179 ) begin + free_adr_mask_next[179] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd179 ) begin + free_adr_mask_next[179] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd180 ) begin + free_adr_mask_next[180] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd180 ) begin + free_adr_mask_next[180] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd181 ) begin + free_adr_mask_next[181] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd181 ) begin + free_adr_mask_next[181] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd182 ) begin + free_adr_mask_next[182] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd182 ) begin + free_adr_mask_next[182] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd183 ) begin + free_adr_mask_next[183] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd183 ) begin + free_adr_mask_next[183] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd184 ) begin + free_adr_mask_next[184] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd184 ) begin + free_adr_mask_next[184] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd185 ) begin + free_adr_mask_next[185] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd185 ) begin + free_adr_mask_next[185] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd186 ) begin + free_adr_mask_next[186] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd186 ) begin + free_adr_mask_next[186] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd187 ) begin + free_adr_mask_next[187] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd187 ) begin + free_adr_mask_next[187] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd188 ) begin + free_adr_mask_next[188] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd188 ) begin + free_adr_mask_next[188] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd189 ) begin + free_adr_mask_next[189] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd189 ) begin + free_adr_mask_next[189] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd190 ) begin + free_adr_mask_next[190] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd190 ) begin + free_adr_mask_next[190] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd191 ) begin + free_adr_mask_next[191] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd191 ) begin + free_adr_mask_next[191] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd192 ) begin + free_adr_mask_next[192] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd192 ) begin + free_adr_mask_next[192] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd193 ) begin + free_adr_mask_next[193] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd193 ) begin + free_adr_mask_next[193] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd194 ) begin + free_adr_mask_next[194] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd194 ) begin + free_adr_mask_next[194] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd195 ) begin + free_adr_mask_next[195] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd195 ) begin + free_adr_mask_next[195] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd196 ) begin + free_adr_mask_next[196] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd196 ) begin + free_adr_mask_next[196] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd197 ) begin + free_adr_mask_next[197] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd197 ) begin + free_adr_mask_next[197] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd198 ) begin + free_adr_mask_next[198] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd198 ) begin + free_adr_mask_next[198] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd199 ) begin + free_adr_mask_next[199] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd199 ) begin + free_adr_mask_next[199] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd200 ) begin + free_adr_mask_next[200] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd200 ) begin + free_adr_mask_next[200] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd201 ) begin + free_adr_mask_next[201] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd201 ) begin + free_adr_mask_next[201] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd202 ) begin + free_adr_mask_next[202] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd202 ) begin + free_adr_mask_next[202] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd203 ) begin + free_adr_mask_next[203] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd203 ) begin + free_adr_mask_next[203] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd204 ) begin + free_adr_mask_next[204] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd204 ) begin + free_adr_mask_next[204] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd205 ) begin + free_adr_mask_next[205] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd205 ) begin + free_adr_mask_next[205] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd206 ) begin + free_adr_mask_next[206] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd206 ) begin + free_adr_mask_next[206] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd207 ) begin + free_adr_mask_next[207] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd207 ) begin + free_adr_mask_next[207] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd208 ) begin + free_adr_mask_next[208] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd208 ) begin + free_adr_mask_next[208] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd209 ) begin + free_adr_mask_next[209] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd209 ) begin + free_adr_mask_next[209] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd210 ) begin + free_adr_mask_next[210] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd210 ) begin + free_adr_mask_next[210] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd211 ) begin + free_adr_mask_next[211] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd211 ) begin + free_adr_mask_next[211] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd212 ) begin + free_adr_mask_next[212] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd212 ) begin + free_adr_mask_next[212] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd213 ) begin + free_adr_mask_next[213] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd213 ) begin + free_adr_mask_next[213] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd214 ) begin + free_adr_mask_next[214] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd214 ) begin + free_adr_mask_next[214] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd215 ) begin + free_adr_mask_next[215] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd215 ) begin + free_adr_mask_next[215] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd216 ) begin + free_adr_mask_next[216] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd216 ) begin + free_adr_mask_next[216] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd217 ) begin + free_adr_mask_next[217] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd217 ) begin + free_adr_mask_next[217] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd218 ) begin + free_adr_mask_next[218] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd218 ) begin + free_adr_mask_next[218] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd219 ) begin + free_adr_mask_next[219] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd219 ) begin + free_adr_mask_next[219] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd220 ) begin + free_adr_mask_next[220] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd220 ) begin + free_adr_mask_next[220] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd221 ) begin + free_adr_mask_next[221] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd221 ) begin + free_adr_mask_next[221] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd222 ) begin + free_adr_mask_next[222] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd222 ) begin + free_adr_mask_next[222] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd223 ) begin + free_adr_mask_next[223] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd223 ) begin + free_adr_mask_next[223] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd224 ) begin + free_adr_mask_next[224] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd224 ) begin + free_adr_mask_next[224] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd225 ) begin + free_adr_mask_next[225] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd225 ) begin + free_adr_mask_next[225] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd226 ) begin + free_adr_mask_next[226] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd226 ) begin + free_adr_mask_next[226] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd227 ) begin + free_adr_mask_next[227] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd227 ) begin + free_adr_mask_next[227] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd228 ) begin + free_adr_mask_next[228] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd228 ) begin + free_adr_mask_next[228] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd229 ) begin + free_adr_mask_next[229] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd229 ) begin + free_adr_mask_next[229] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd230 ) begin + free_adr_mask_next[230] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd230 ) begin + free_adr_mask_next[230] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd231 ) begin + free_adr_mask_next[231] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd231 ) begin + free_adr_mask_next[231] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd232 ) begin + free_adr_mask_next[232] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd232 ) begin + free_adr_mask_next[232] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd233 ) begin + free_adr_mask_next[233] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd233 ) begin + free_adr_mask_next[233] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd234 ) begin + free_adr_mask_next[234] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd234 ) begin + free_adr_mask_next[234] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd235 ) begin + free_adr_mask_next[235] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd235 ) begin + free_adr_mask_next[235] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd236 ) begin + free_adr_mask_next[236] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd236 ) begin + free_adr_mask_next[236] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd237 ) begin + free_adr_mask_next[237] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd237 ) begin + free_adr_mask_next[237] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd238 ) begin + free_adr_mask_next[238] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd238 ) begin + free_adr_mask_next[238] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd239 ) begin + free_adr_mask_next[239] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd239 ) begin + free_adr_mask_next[239] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd240 ) begin + free_adr_mask_next[240] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd240 ) begin + free_adr_mask_next[240] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd241 ) begin + free_adr_mask_next[241] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd241 ) begin + free_adr_mask_next[241] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd242 ) begin + free_adr_mask_next[242] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd242 ) begin + free_adr_mask_next[242] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd243 ) begin + free_adr_mask_next[243] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd243 ) begin + free_adr_mask_next[243] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd244 ) begin + free_adr_mask_next[244] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd244 ) begin + free_adr_mask_next[244] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd245 ) begin + free_adr_mask_next[245] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd245 ) begin + free_adr_mask_next[245] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd246 ) begin + free_adr_mask_next[246] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd246 ) begin + free_adr_mask_next[246] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd247 ) begin + free_adr_mask_next[247] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd247 ) begin + free_adr_mask_next[247] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd248 ) begin + free_adr_mask_next[248] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd248 ) begin + free_adr_mask_next[248] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd249 ) begin + free_adr_mask_next[249] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd249 ) begin + free_adr_mask_next[249] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd250 ) begin + free_adr_mask_next[250] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd250 ) begin + free_adr_mask_next[250] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd251 ) begin + free_adr_mask_next[251] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd251 ) begin + free_adr_mask_next[251] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd252 ) begin + free_adr_mask_next[252] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd252 ) begin + free_adr_mask_next[252] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd253 ) begin + free_adr_mask_next[253] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd253 ) begin + free_adr_mask_next[253] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd254 ) begin + free_adr_mask_next[254] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd254 ) begin + free_adr_mask_next[254] = 1'b0; + end +end +wire flag_l0_0 = free_adr_mask[1] | free_adr_mask[0]; +wire flag_l0_1 = free_adr_mask[3] | free_adr_mask[2]; +wire flag_l0_2 = free_adr_mask[5] | free_adr_mask[4]; +wire flag_l0_3 = free_adr_mask[7] | free_adr_mask[6]; +wire flag_l0_4 = free_adr_mask[9] | free_adr_mask[8]; +wire flag_l0_5 = free_adr_mask[11] | free_adr_mask[10]; +wire flag_l0_6 = free_adr_mask[13] | free_adr_mask[12]; +wire flag_l0_7 = free_adr_mask[15] | free_adr_mask[14]; +wire flag_l0_8 = free_adr_mask[17] | free_adr_mask[16]; +wire flag_l0_9 = free_adr_mask[19] | free_adr_mask[18]; +wire flag_l0_10 = free_adr_mask[21] | free_adr_mask[20]; +wire flag_l0_11 = free_adr_mask[23] | free_adr_mask[22]; +wire flag_l0_12 = free_adr_mask[25] | free_adr_mask[24]; +wire flag_l0_13 = free_adr_mask[27] | free_adr_mask[26]; +wire flag_l0_14 = free_adr_mask[29] | free_adr_mask[28]; +wire flag_l0_15 = free_adr_mask[31] | free_adr_mask[30]; +wire flag_l0_16 = free_adr_mask[33] | free_adr_mask[32]; +wire flag_l0_17 = free_adr_mask[35] | free_adr_mask[34]; +wire flag_l0_18 = free_adr_mask[37] | free_adr_mask[36]; +wire flag_l0_19 = free_adr_mask[39] | free_adr_mask[38]; +wire flag_l0_20 = free_adr_mask[41] | free_adr_mask[40]; +wire flag_l0_21 = free_adr_mask[43] | free_adr_mask[42]; +wire flag_l0_22 = free_adr_mask[45] | free_adr_mask[44]; +wire flag_l0_23 = free_adr_mask[47] | free_adr_mask[46]; +wire flag_l0_24 = free_adr_mask[49] | free_adr_mask[48]; +wire flag_l0_25 = free_adr_mask[51] | free_adr_mask[50]; +wire flag_l0_26 = free_adr_mask[53] | free_adr_mask[52]; +wire flag_l0_27 = free_adr_mask[55] | free_adr_mask[54]; +wire flag_l0_28 = free_adr_mask[57] | free_adr_mask[56]; +wire flag_l0_29 = free_adr_mask[59] | free_adr_mask[58]; +wire flag_l0_30 = free_adr_mask[61] | free_adr_mask[60]; +wire flag_l0_31 = free_adr_mask[63] | free_adr_mask[62]; +wire flag_l0_32 = free_adr_mask[65] | free_adr_mask[64]; +wire flag_l0_33 = free_adr_mask[67] | free_adr_mask[66]; +wire flag_l0_34 = free_adr_mask[69] | free_adr_mask[68]; +wire flag_l0_35 = free_adr_mask[71] | free_adr_mask[70]; +wire flag_l0_36 = free_adr_mask[73] | free_adr_mask[72]; +wire flag_l0_37 = free_adr_mask[75] | free_adr_mask[74]; +wire flag_l0_38 = free_adr_mask[77] | free_adr_mask[76]; +wire flag_l0_39 = free_adr_mask[79] | free_adr_mask[78]; +wire flag_l0_40 = free_adr_mask[81] | free_adr_mask[80]; +wire flag_l0_41 = free_adr_mask[83] | free_adr_mask[82]; +wire flag_l0_42 = free_adr_mask[85] | free_adr_mask[84]; +wire flag_l0_43 = free_adr_mask[87] | free_adr_mask[86]; +wire flag_l0_44 = free_adr_mask[89] | free_adr_mask[88]; +wire flag_l0_45 = free_adr_mask[91] | free_adr_mask[90]; +wire flag_l0_46 = free_adr_mask[93] | free_adr_mask[92]; +wire flag_l0_47 = free_adr_mask[95] | free_adr_mask[94]; +wire flag_l0_48 = free_adr_mask[97] | free_adr_mask[96]; +wire flag_l0_49 = free_adr_mask[99] | free_adr_mask[98]; +wire flag_l0_50 = free_adr_mask[101] | free_adr_mask[100]; +wire flag_l0_51 = free_adr_mask[103] | free_adr_mask[102]; +wire flag_l0_52 = free_adr_mask[105] | free_adr_mask[104]; +wire flag_l0_53 = free_adr_mask[107] | free_adr_mask[106]; +wire flag_l0_54 = free_adr_mask[109] | free_adr_mask[108]; +wire flag_l0_55 = free_adr_mask[111] | free_adr_mask[110]; +wire flag_l0_56 = free_adr_mask[113] | free_adr_mask[112]; +wire flag_l0_57 = free_adr_mask[115] | free_adr_mask[114]; +wire flag_l0_58 = free_adr_mask[117] | free_adr_mask[116]; +wire flag_l0_59 = free_adr_mask[119] | free_adr_mask[118]; +wire flag_l0_60 = free_adr_mask[121] | free_adr_mask[120]; +wire flag_l0_61 = free_adr_mask[123] | free_adr_mask[122]; +wire flag_l0_62 = free_adr_mask[125] | free_adr_mask[124]; +wire flag_l0_63 = free_adr_mask[127] | free_adr_mask[126]; +wire flag_l0_64 = free_adr_mask[129] | free_adr_mask[128]; +wire flag_l0_65 = free_adr_mask[131] | free_adr_mask[130]; +wire flag_l0_66 = free_adr_mask[133] | free_adr_mask[132]; +wire flag_l0_67 = free_adr_mask[135] | free_adr_mask[134]; +wire flag_l0_68 = free_adr_mask[137] | free_adr_mask[136]; +wire flag_l0_69 = free_adr_mask[139] | free_adr_mask[138]; +wire flag_l0_70 = free_adr_mask[141] | free_adr_mask[140]; +wire flag_l0_71 = free_adr_mask[143] | free_adr_mask[142]; +wire flag_l0_72 = free_adr_mask[145] | free_adr_mask[144]; +wire flag_l0_73 = free_adr_mask[147] | free_adr_mask[146]; +wire flag_l0_74 = free_adr_mask[149] | free_adr_mask[148]; +wire flag_l0_75 = free_adr_mask[151] | free_adr_mask[150]; +wire flag_l0_76 = free_adr_mask[153] | free_adr_mask[152]; +wire flag_l0_77 = free_adr_mask[155] | free_adr_mask[154]; +wire flag_l0_78 = free_adr_mask[157] | free_adr_mask[156]; +wire flag_l0_79 = free_adr_mask[159] | free_adr_mask[158]; +wire flag_l0_80 = free_adr_mask[161] | free_adr_mask[160]; +wire flag_l0_81 = free_adr_mask[163] | free_adr_mask[162]; +wire flag_l0_82 = free_adr_mask[165] | free_adr_mask[164]; +wire flag_l0_83 = free_adr_mask[167] | free_adr_mask[166]; +wire flag_l0_84 = free_adr_mask[169] | free_adr_mask[168]; +wire flag_l0_85 = free_adr_mask[171] | free_adr_mask[170]; +wire flag_l0_86 = free_adr_mask[173] | free_adr_mask[172]; +wire flag_l0_87 = free_adr_mask[175] | free_adr_mask[174]; +wire flag_l0_88 = free_adr_mask[177] | free_adr_mask[176]; +wire flag_l0_89 = free_adr_mask[179] | free_adr_mask[178]; +wire flag_l0_90 = free_adr_mask[181] | free_adr_mask[180]; +wire flag_l0_91 = free_adr_mask[183] | free_adr_mask[182]; +wire flag_l0_92 = free_adr_mask[185] | free_adr_mask[184]; +wire flag_l0_93 = free_adr_mask[187] | free_adr_mask[186]; +wire flag_l0_94 = free_adr_mask[189] | free_adr_mask[188]; +wire flag_l0_95 = free_adr_mask[191] | free_adr_mask[190]; +wire flag_l0_96 = free_adr_mask[193] | free_adr_mask[192]; +wire flag_l0_97 = free_adr_mask[195] | free_adr_mask[194]; +wire flag_l0_98 = free_adr_mask[197] | free_adr_mask[196]; +wire flag_l0_99 = free_adr_mask[199] | free_adr_mask[198]; +wire flag_l0_100 = free_adr_mask[201] | free_adr_mask[200]; +wire flag_l0_101 = free_adr_mask[203] | free_adr_mask[202]; +wire flag_l0_102 = free_adr_mask[205] | free_adr_mask[204]; +wire flag_l0_103 = free_adr_mask[207] | free_adr_mask[206]; +wire flag_l0_104 = free_adr_mask[209] | free_adr_mask[208]; +wire flag_l0_105 = free_adr_mask[211] | free_adr_mask[210]; +wire flag_l0_106 = free_adr_mask[213] | free_adr_mask[212]; +wire flag_l0_107 = free_adr_mask[215] | free_adr_mask[214]; +wire flag_l0_108 = free_adr_mask[217] | free_adr_mask[216]; +wire flag_l0_109 = free_adr_mask[219] | free_adr_mask[218]; +wire flag_l0_110 = free_adr_mask[221] | free_adr_mask[220]; +wire flag_l0_111 = free_adr_mask[223] | free_adr_mask[222]; +wire flag_l0_112 = free_adr_mask[225] | free_adr_mask[224]; +wire flag_l0_113 = free_adr_mask[227] | free_adr_mask[226]; +wire flag_l0_114 = free_adr_mask[229] | free_adr_mask[228]; +wire flag_l0_115 = free_adr_mask[231] | free_adr_mask[230]; +wire flag_l0_116 = free_adr_mask[233] | free_adr_mask[232]; +wire flag_l0_117 = free_adr_mask[235] | free_adr_mask[234]; +wire flag_l0_118 = free_adr_mask[237] | free_adr_mask[236]; +wire flag_l0_119 = free_adr_mask[239] | free_adr_mask[238]; +wire flag_l0_120 = free_adr_mask[241] | free_adr_mask[240]; +wire flag_l0_121 = free_adr_mask[243] | free_adr_mask[242]; +wire flag_l0_122 = free_adr_mask[245] | free_adr_mask[244]; +wire flag_l0_123 = free_adr_mask[247] | free_adr_mask[246]; +wire flag_l0_124 = free_adr_mask[249] | free_adr_mask[248]; +wire flag_l0_125 = free_adr_mask[251] | free_adr_mask[250]; +wire flag_l0_126 = free_adr_mask[253] | free_adr_mask[252]; +wire flag_l1_0 = flag_l0_1 | flag_l0_0; +wire flag_l1_1 = flag_l0_3 | flag_l0_2; +wire flag_l1_2 = flag_l0_5 | flag_l0_4; +wire flag_l1_3 = flag_l0_7 | flag_l0_6; +wire flag_l1_4 = flag_l0_9 | flag_l0_8; +wire flag_l1_5 = flag_l0_11 | flag_l0_10; +wire flag_l1_6 = flag_l0_13 | flag_l0_12; +wire flag_l1_7 = flag_l0_15 | flag_l0_14; +wire flag_l1_8 = flag_l0_17 | flag_l0_16; +wire flag_l1_9 = flag_l0_19 | flag_l0_18; +wire flag_l1_10 = flag_l0_21 | flag_l0_20; +wire flag_l1_11 = flag_l0_23 | flag_l0_22; +wire flag_l1_12 = flag_l0_25 | flag_l0_24; +wire flag_l1_13 = flag_l0_27 | flag_l0_26; +wire flag_l1_14 = flag_l0_29 | flag_l0_28; +wire flag_l1_15 = flag_l0_31 | flag_l0_30; +wire flag_l1_16 = flag_l0_33 | flag_l0_32; +wire flag_l1_17 = flag_l0_35 | flag_l0_34; +wire flag_l1_18 = flag_l0_37 | flag_l0_36; +wire flag_l1_19 = flag_l0_39 | flag_l0_38; +wire flag_l1_20 = flag_l0_41 | flag_l0_40; +wire flag_l1_21 = flag_l0_43 | flag_l0_42; +wire flag_l1_22 = flag_l0_45 | flag_l0_44; +wire flag_l1_23 = flag_l0_47 | flag_l0_46; +wire flag_l1_24 = flag_l0_49 | flag_l0_48; +wire flag_l1_25 = flag_l0_51 | flag_l0_50; +wire flag_l1_26 = flag_l0_53 | flag_l0_52; +wire flag_l1_27 = flag_l0_55 | flag_l0_54; +wire flag_l1_28 = flag_l0_57 | flag_l0_56; +wire flag_l1_29 = flag_l0_59 | flag_l0_58; +wire flag_l1_30 = flag_l0_61 | flag_l0_60; +wire flag_l1_31 = flag_l0_63 | flag_l0_62; +wire flag_l1_32 = flag_l0_65 | flag_l0_64; +wire flag_l1_33 = flag_l0_67 | flag_l0_66; +wire flag_l1_34 = flag_l0_69 | flag_l0_68; +wire flag_l1_35 = flag_l0_71 | flag_l0_70; +wire flag_l1_36 = flag_l0_73 | flag_l0_72; +wire flag_l1_37 = flag_l0_75 | flag_l0_74; +wire flag_l1_38 = flag_l0_77 | flag_l0_76; +wire flag_l1_39 = flag_l0_79 | flag_l0_78; +wire flag_l1_40 = flag_l0_81 | flag_l0_80; +wire flag_l1_41 = flag_l0_83 | flag_l0_82; +wire flag_l1_42 = flag_l0_85 | flag_l0_84; +wire flag_l1_43 = flag_l0_87 | flag_l0_86; +wire flag_l1_44 = flag_l0_89 | flag_l0_88; +wire flag_l1_45 = flag_l0_91 | flag_l0_90; +wire flag_l1_46 = flag_l0_93 | flag_l0_92; +wire flag_l1_47 = flag_l0_95 | flag_l0_94; +wire flag_l1_48 = flag_l0_97 | flag_l0_96; +wire flag_l1_49 = flag_l0_99 | flag_l0_98; +wire flag_l1_50 = flag_l0_101 | flag_l0_100; +wire flag_l1_51 = flag_l0_103 | flag_l0_102; +wire flag_l1_52 = flag_l0_105 | flag_l0_104; +wire flag_l1_53 = flag_l0_107 | flag_l0_106; +wire flag_l1_54 = flag_l0_109 | flag_l0_108; +wire flag_l1_55 = flag_l0_111 | flag_l0_110; +wire flag_l1_56 = flag_l0_113 | flag_l0_112; +wire flag_l1_57 = flag_l0_115 | flag_l0_114; +wire flag_l1_58 = flag_l0_117 | flag_l0_116; +wire flag_l1_59 = flag_l0_119 | flag_l0_118; +wire flag_l1_60 = flag_l0_121 | flag_l0_120; +wire flag_l1_61 = flag_l0_123 | flag_l0_122; +wire flag_l1_62 = flag_l0_125 | flag_l0_124; +wire flag_l2_0 = flag_l1_1 | flag_l1_0; +wire flag_l2_1 = flag_l1_3 | flag_l1_2; +wire flag_l2_2 = flag_l1_5 | flag_l1_4; +wire flag_l2_3 = flag_l1_7 | flag_l1_6; +wire flag_l2_4 = flag_l1_9 | flag_l1_8; +wire flag_l2_5 = flag_l1_11 | flag_l1_10; +wire flag_l2_6 = flag_l1_13 | flag_l1_12; +wire flag_l2_7 = flag_l1_15 | flag_l1_14; +wire flag_l2_8 = flag_l1_17 | flag_l1_16; +wire flag_l2_9 = flag_l1_19 | flag_l1_18; +wire flag_l2_10 = flag_l1_21 | flag_l1_20; +wire flag_l2_11 = flag_l1_23 | flag_l1_22; +wire flag_l2_12 = flag_l1_25 | flag_l1_24; +wire flag_l2_13 = flag_l1_27 | flag_l1_26; +wire flag_l2_14 = flag_l1_29 | flag_l1_28; +wire flag_l2_15 = flag_l1_31 | flag_l1_30; +wire flag_l2_16 = flag_l1_33 | flag_l1_32; +wire flag_l2_17 = flag_l1_35 | flag_l1_34; +wire flag_l2_18 = flag_l1_37 | flag_l1_36; +wire flag_l2_19 = flag_l1_39 | flag_l1_38; +wire flag_l2_20 = flag_l1_41 | flag_l1_40; +wire flag_l2_21 = flag_l1_43 | flag_l1_42; +wire flag_l2_22 = flag_l1_45 | flag_l1_44; +wire flag_l2_23 = flag_l1_47 | flag_l1_46; +wire flag_l2_24 = flag_l1_49 | flag_l1_48; +wire flag_l2_25 = flag_l1_51 | flag_l1_50; +wire flag_l2_26 = flag_l1_53 | flag_l1_52; +wire flag_l2_27 = flag_l1_55 | flag_l1_54; +wire flag_l2_28 = flag_l1_57 | flag_l1_56; +wire flag_l2_29 = flag_l1_59 | flag_l1_58; +wire flag_l2_30 = flag_l1_61 | flag_l1_60; +wire flag_l3_0 = flag_l2_1 | flag_l2_0; +wire flag_l3_1 = flag_l2_3 | flag_l2_2; +wire flag_l3_2 = flag_l2_5 | flag_l2_4; +wire flag_l3_3 = flag_l2_7 | flag_l2_6; +wire flag_l3_4 = flag_l2_9 | flag_l2_8; +wire flag_l3_5 = flag_l2_11 | flag_l2_10; +wire flag_l3_6 = flag_l2_13 | flag_l2_12; +wire flag_l3_7 = flag_l2_15 | flag_l2_14; +wire flag_l3_8 = flag_l2_17 | flag_l2_16; +wire flag_l3_9 = flag_l2_19 | flag_l2_18; +wire flag_l3_10 = flag_l2_21 | flag_l2_20; +wire flag_l3_11 = flag_l2_23 | flag_l2_22; +wire flag_l3_12 = flag_l2_25 | flag_l2_24; +wire flag_l3_13 = flag_l2_27 | flag_l2_26; +wire flag_l3_14 = flag_l2_29 | flag_l2_28; +wire flag_l4_0 = flag_l3_1 | flag_l3_0; +wire flag_l4_1 = flag_l3_3 | flag_l3_2; +wire flag_l4_2 = flag_l3_5 | flag_l3_4; +wire flag_l4_3 = flag_l3_7 | flag_l3_6; +wire flag_l4_4 = flag_l3_9 | flag_l3_8; +wire flag_l4_5 = flag_l3_11 | flag_l3_10; +wire flag_l4_6 = flag_l3_13 | flag_l3_12; +wire flag_l5_0 = flag_l4_1 | flag_l4_0; +wire flag_l5_1 = flag_l4_3 | flag_l4_2; +wire flag_l5_2 = flag_l4_5 | flag_l4_4; +wire flag_l6_0 = flag_l5_1 | flag_l5_0; +wire index_l0_0 = !free_adr_mask[0]; +wire index_l0_1 = !free_adr_mask[2]; +wire index_l0_2 = !free_adr_mask[4]; +wire index_l0_3 = !free_adr_mask[6]; +wire index_l0_4 = !free_adr_mask[8]; +wire index_l0_5 = !free_adr_mask[10]; +wire index_l0_6 = !free_adr_mask[12]; +wire index_l0_7 = !free_adr_mask[14]; +wire index_l0_8 = !free_adr_mask[16]; +wire index_l0_9 = !free_adr_mask[18]; +wire index_l0_10 = !free_adr_mask[20]; +wire index_l0_11 = !free_adr_mask[22]; +wire index_l0_12 = !free_adr_mask[24]; +wire index_l0_13 = !free_adr_mask[26]; +wire index_l0_14 = !free_adr_mask[28]; +wire index_l0_15 = !free_adr_mask[30]; +wire index_l0_16 = !free_adr_mask[32]; +wire index_l0_17 = !free_adr_mask[34]; +wire index_l0_18 = !free_adr_mask[36]; +wire index_l0_19 = !free_adr_mask[38]; +wire index_l0_20 = !free_adr_mask[40]; +wire index_l0_21 = !free_adr_mask[42]; +wire index_l0_22 = !free_adr_mask[44]; +wire index_l0_23 = !free_adr_mask[46]; +wire index_l0_24 = !free_adr_mask[48]; +wire index_l0_25 = !free_adr_mask[50]; +wire index_l0_26 = !free_adr_mask[52]; +wire index_l0_27 = !free_adr_mask[54]; +wire index_l0_28 = !free_adr_mask[56]; +wire index_l0_29 = !free_adr_mask[58]; +wire index_l0_30 = !free_adr_mask[60]; +wire index_l0_31 = !free_adr_mask[62]; +wire index_l0_32 = !free_adr_mask[64]; +wire index_l0_33 = !free_adr_mask[66]; +wire index_l0_34 = !free_adr_mask[68]; +wire index_l0_35 = !free_adr_mask[70]; +wire index_l0_36 = !free_adr_mask[72]; +wire index_l0_37 = !free_adr_mask[74]; +wire index_l0_38 = !free_adr_mask[76]; +wire index_l0_39 = !free_adr_mask[78]; +wire index_l0_40 = !free_adr_mask[80]; +wire index_l0_41 = !free_adr_mask[82]; +wire index_l0_42 = !free_adr_mask[84]; +wire index_l0_43 = !free_adr_mask[86]; +wire index_l0_44 = !free_adr_mask[88]; +wire index_l0_45 = !free_adr_mask[90]; +wire index_l0_46 = !free_adr_mask[92]; +wire index_l0_47 = !free_adr_mask[94]; +wire index_l0_48 = !free_adr_mask[96]; +wire index_l0_49 = !free_adr_mask[98]; +wire index_l0_50 = !free_adr_mask[100]; +wire index_l0_51 = !free_adr_mask[102]; +wire index_l0_52 = !free_adr_mask[104]; +wire index_l0_53 = !free_adr_mask[106]; +wire index_l0_54 = !free_adr_mask[108]; +wire index_l0_55 = !free_adr_mask[110]; +wire index_l0_56 = !free_adr_mask[112]; +wire index_l0_57 = !free_adr_mask[114]; +wire index_l0_58 = !free_adr_mask[116]; +wire index_l0_59 = !free_adr_mask[118]; +wire index_l0_60 = !free_adr_mask[120]; +wire index_l0_61 = !free_adr_mask[122]; +wire index_l0_62 = !free_adr_mask[124]; +wire index_l0_63 = !free_adr_mask[126]; +wire index_l0_64 = !free_adr_mask[128]; +wire index_l0_65 = !free_adr_mask[130]; +wire index_l0_66 = !free_adr_mask[132]; +wire index_l0_67 = !free_adr_mask[134]; +wire index_l0_68 = !free_adr_mask[136]; +wire index_l0_69 = !free_adr_mask[138]; +wire index_l0_70 = !free_adr_mask[140]; +wire index_l0_71 = !free_adr_mask[142]; +wire index_l0_72 = !free_adr_mask[144]; +wire index_l0_73 = !free_adr_mask[146]; +wire index_l0_74 = !free_adr_mask[148]; +wire index_l0_75 = !free_adr_mask[150]; +wire index_l0_76 = !free_adr_mask[152]; +wire index_l0_77 = !free_adr_mask[154]; +wire index_l0_78 = !free_adr_mask[156]; +wire index_l0_79 = !free_adr_mask[158]; +wire index_l0_80 = !free_adr_mask[160]; +wire index_l0_81 = !free_adr_mask[162]; +wire index_l0_82 = !free_adr_mask[164]; +wire index_l0_83 = !free_adr_mask[166]; +wire index_l0_84 = !free_adr_mask[168]; +wire index_l0_85 = !free_adr_mask[170]; +wire index_l0_86 = !free_adr_mask[172]; +wire index_l0_87 = !free_adr_mask[174]; +wire index_l0_88 = !free_adr_mask[176]; +wire index_l0_89 = !free_adr_mask[178]; +wire index_l0_90 = !free_adr_mask[180]; +wire index_l0_91 = !free_adr_mask[182]; +wire index_l0_92 = !free_adr_mask[184]; +wire index_l0_93 = !free_adr_mask[186]; +wire index_l0_94 = !free_adr_mask[188]; +wire index_l0_95 = !free_adr_mask[190]; +wire index_l0_96 = !free_adr_mask[192]; +wire index_l0_97 = !free_adr_mask[194]; +wire index_l0_98 = !free_adr_mask[196]; +wire index_l0_99 = !free_adr_mask[198]; +wire index_l0_100 = !free_adr_mask[200]; +wire index_l0_101 = !free_adr_mask[202]; +wire index_l0_102 = !free_adr_mask[204]; +wire index_l0_103 = !free_adr_mask[206]; +wire index_l0_104 = !free_adr_mask[208]; +wire index_l0_105 = !free_adr_mask[210]; +wire index_l0_106 = !free_adr_mask[212]; +wire index_l0_107 = !free_adr_mask[214]; +wire index_l0_108 = !free_adr_mask[216]; +wire index_l0_109 = !free_adr_mask[218]; +wire index_l0_110 = !free_adr_mask[220]; +wire index_l0_111 = !free_adr_mask[222]; +wire index_l0_112 = !free_adr_mask[224]; +wire index_l0_113 = !free_adr_mask[226]; +wire index_l0_114 = !free_adr_mask[228]; +wire index_l0_115 = !free_adr_mask[230]; +wire index_l0_116 = !free_adr_mask[232]; +wire index_l0_117 = !free_adr_mask[234]; +wire index_l0_118 = !free_adr_mask[236]; +wire index_l0_119 = !free_adr_mask[238]; +wire index_l0_120 = !free_adr_mask[240]; +wire index_l0_121 = !free_adr_mask[242]; +wire index_l0_122 = !free_adr_mask[244]; +wire index_l0_123 = !free_adr_mask[246]; +wire index_l0_124 = !free_adr_mask[248]; +wire index_l0_125 = !free_adr_mask[250]; +wire index_l0_126 = !free_adr_mask[252]; +wire index_l0_127 = !free_adr_mask[254]; +wire [1:0] index_l1_0 = {!flag_l0_0,(flag_l0_0?index_l0_0:index_l0_1)}; +wire [1:0] index_l1_1 = {!flag_l0_2,(flag_l0_2?index_l0_2:index_l0_3)}; +wire [1:0] index_l1_2 = {!flag_l0_4,(flag_l0_4?index_l0_4:index_l0_5)}; +wire [1:0] index_l1_3 = {!flag_l0_6,(flag_l0_6?index_l0_6:index_l0_7)}; +wire [1:0] index_l1_4 = {!flag_l0_8,(flag_l0_8?index_l0_8:index_l0_9)}; +wire [1:0] index_l1_5 = {!flag_l0_10,(flag_l0_10?index_l0_10:index_l0_11)}; +wire [1:0] index_l1_6 = {!flag_l0_12,(flag_l0_12?index_l0_12:index_l0_13)}; +wire [1:0] index_l1_7 = {!flag_l0_14,(flag_l0_14?index_l0_14:index_l0_15)}; +wire [1:0] index_l1_8 = {!flag_l0_16,(flag_l0_16?index_l0_16:index_l0_17)}; +wire [1:0] index_l1_9 = {!flag_l0_18,(flag_l0_18?index_l0_18:index_l0_19)}; +wire [1:0] index_l1_10 = {!flag_l0_20,(flag_l0_20?index_l0_20:index_l0_21)}; +wire [1:0] index_l1_11 = {!flag_l0_22,(flag_l0_22?index_l0_22:index_l0_23)}; +wire [1:0] index_l1_12 = {!flag_l0_24,(flag_l0_24?index_l0_24:index_l0_25)}; +wire [1:0] index_l1_13 = {!flag_l0_26,(flag_l0_26?index_l0_26:index_l0_27)}; +wire [1:0] index_l1_14 = {!flag_l0_28,(flag_l0_28?index_l0_28:index_l0_29)}; +wire [1:0] index_l1_15 = {!flag_l0_30,(flag_l0_30?index_l0_30:index_l0_31)}; +wire [1:0] index_l1_16 = {!flag_l0_32,(flag_l0_32?index_l0_32:index_l0_33)}; +wire [1:0] index_l1_17 = {!flag_l0_34,(flag_l0_34?index_l0_34:index_l0_35)}; +wire [1:0] index_l1_18 = {!flag_l0_36,(flag_l0_36?index_l0_36:index_l0_37)}; +wire [1:0] index_l1_19 = {!flag_l0_38,(flag_l0_38?index_l0_38:index_l0_39)}; +wire [1:0] index_l1_20 = {!flag_l0_40,(flag_l0_40?index_l0_40:index_l0_41)}; +wire [1:0] index_l1_21 = {!flag_l0_42,(flag_l0_42?index_l0_42:index_l0_43)}; +wire [1:0] index_l1_22 = {!flag_l0_44,(flag_l0_44?index_l0_44:index_l0_45)}; +wire [1:0] index_l1_23 = {!flag_l0_46,(flag_l0_46?index_l0_46:index_l0_47)}; +wire [1:0] index_l1_24 = {!flag_l0_48,(flag_l0_48?index_l0_48:index_l0_49)}; +wire [1:0] index_l1_25 = {!flag_l0_50,(flag_l0_50?index_l0_50:index_l0_51)}; +wire [1:0] index_l1_26 = {!flag_l0_52,(flag_l0_52?index_l0_52:index_l0_53)}; +wire [1:0] index_l1_27 = {!flag_l0_54,(flag_l0_54?index_l0_54:index_l0_55)}; +wire [1:0] index_l1_28 = {!flag_l0_56,(flag_l0_56?index_l0_56:index_l0_57)}; +wire [1:0] index_l1_29 = {!flag_l0_58,(flag_l0_58?index_l0_58:index_l0_59)}; +wire [1:0] index_l1_30 = {!flag_l0_60,(flag_l0_60?index_l0_60:index_l0_61)}; +wire [1:0] index_l1_31 = {!flag_l0_62,(flag_l0_62?index_l0_62:index_l0_63)}; +wire [1:0] index_l1_32 = {!flag_l0_64,(flag_l0_64?index_l0_64:index_l0_65)}; +wire [1:0] index_l1_33 = {!flag_l0_66,(flag_l0_66?index_l0_66:index_l0_67)}; +wire [1:0] index_l1_34 = {!flag_l0_68,(flag_l0_68?index_l0_68:index_l0_69)}; +wire [1:0] index_l1_35 = {!flag_l0_70,(flag_l0_70?index_l0_70:index_l0_71)}; +wire [1:0] index_l1_36 = {!flag_l0_72,(flag_l0_72?index_l0_72:index_l0_73)}; +wire [1:0] index_l1_37 = {!flag_l0_74,(flag_l0_74?index_l0_74:index_l0_75)}; +wire [1:0] index_l1_38 = {!flag_l0_76,(flag_l0_76?index_l0_76:index_l0_77)}; +wire [1:0] index_l1_39 = {!flag_l0_78,(flag_l0_78?index_l0_78:index_l0_79)}; +wire [1:0] index_l1_40 = {!flag_l0_80,(flag_l0_80?index_l0_80:index_l0_81)}; +wire [1:0] index_l1_41 = {!flag_l0_82,(flag_l0_82?index_l0_82:index_l0_83)}; +wire [1:0] index_l1_42 = {!flag_l0_84,(flag_l0_84?index_l0_84:index_l0_85)}; +wire [1:0] index_l1_43 = {!flag_l0_86,(flag_l0_86?index_l0_86:index_l0_87)}; +wire [1:0] index_l1_44 = {!flag_l0_88,(flag_l0_88?index_l0_88:index_l0_89)}; +wire [1:0] index_l1_45 = {!flag_l0_90,(flag_l0_90?index_l0_90:index_l0_91)}; +wire [1:0] index_l1_46 = {!flag_l0_92,(flag_l0_92?index_l0_92:index_l0_93)}; +wire [1:0] index_l1_47 = {!flag_l0_94,(flag_l0_94?index_l0_94:index_l0_95)}; +wire [1:0] index_l1_48 = {!flag_l0_96,(flag_l0_96?index_l0_96:index_l0_97)}; +wire [1:0] index_l1_49 = {!flag_l0_98,(flag_l0_98?index_l0_98:index_l0_99)}; +wire [1:0] index_l1_50 = {!flag_l0_100,(flag_l0_100?index_l0_100:index_l0_101)}; +wire [1:0] index_l1_51 = {!flag_l0_102,(flag_l0_102?index_l0_102:index_l0_103)}; +wire [1:0] index_l1_52 = {!flag_l0_104,(flag_l0_104?index_l0_104:index_l0_105)}; +wire [1:0] index_l1_53 = {!flag_l0_106,(flag_l0_106?index_l0_106:index_l0_107)}; +wire [1:0] index_l1_54 = {!flag_l0_108,(flag_l0_108?index_l0_108:index_l0_109)}; +wire [1:0] index_l1_55 = {!flag_l0_110,(flag_l0_110?index_l0_110:index_l0_111)}; +wire [1:0] index_l1_56 = {!flag_l0_112,(flag_l0_112?index_l0_112:index_l0_113)}; +wire [1:0] index_l1_57 = {!flag_l0_114,(flag_l0_114?index_l0_114:index_l0_115)}; +wire [1:0] index_l1_58 = {!flag_l0_116,(flag_l0_116?index_l0_116:index_l0_117)}; +wire [1:0] index_l1_59 = {!flag_l0_118,(flag_l0_118?index_l0_118:index_l0_119)}; +wire [1:0] index_l1_60 = {!flag_l0_120,(flag_l0_120?index_l0_120:index_l0_121)}; +wire [1:0] index_l1_61 = {!flag_l0_122,(flag_l0_122?index_l0_122:index_l0_123)}; +wire [1:0] index_l1_62 = {!flag_l0_124,(flag_l0_124?index_l0_124:index_l0_125)}; +wire [1:0] index_l1_63 = {!flag_l0_126,(flag_l0_126?index_l0_126:index_l0_127)}; +wire [2:0] index_l2_0 = {!flag_l1_0,(flag_l1_0?index_l1_0:index_l1_1)}; +wire [2:0] index_l2_1 = {!flag_l1_2,(flag_l1_2?index_l1_2:index_l1_3)}; +wire [2:0] index_l2_2 = {!flag_l1_4,(flag_l1_4?index_l1_4:index_l1_5)}; +wire [2:0] index_l2_3 = {!flag_l1_6,(flag_l1_6?index_l1_6:index_l1_7)}; +wire [2:0] index_l2_4 = {!flag_l1_8,(flag_l1_8?index_l1_8:index_l1_9)}; +wire [2:0] index_l2_5 = {!flag_l1_10,(flag_l1_10?index_l1_10:index_l1_11)}; +wire [2:0] index_l2_6 = {!flag_l1_12,(flag_l1_12?index_l1_12:index_l1_13)}; +wire [2:0] index_l2_7 = {!flag_l1_14,(flag_l1_14?index_l1_14:index_l1_15)}; +wire [2:0] index_l2_8 = {!flag_l1_16,(flag_l1_16?index_l1_16:index_l1_17)}; +wire [2:0] index_l2_9 = {!flag_l1_18,(flag_l1_18?index_l1_18:index_l1_19)}; +wire [2:0] index_l2_10 = {!flag_l1_20,(flag_l1_20?index_l1_20:index_l1_21)}; +wire [2:0] index_l2_11 = {!flag_l1_22,(flag_l1_22?index_l1_22:index_l1_23)}; +wire [2:0] index_l2_12 = {!flag_l1_24,(flag_l1_24?index_l1_24:index_l1_25)}; +wire [2:0] index_l2_13 = {!flag_l1_26,(flag_l1_26?index_l1_26:index_l1_27)}; +wire [2:0] index_l2_14 = {!flag_l1_28,(flag_l1_28?index_l1_28:index_l1_29)}; +wire [2:0] index_l2_15 = {!flag_l1_30,(flag_l1_30?index_l1_30:index_l1_31)}; +wire [2:0] index_l2_16 = {!flag_l1_32,(flag_l1_32?index_l1_32:index_l1_33)}; +wire [2:0] index_l2_17 = {!flag_l1_34,(flag_l1_34?index_l1_34:index_l1_35)}; +wire [2:0] index_l2_18 = {!flag_l1_36,(flag_l1_36?index_l1_36:index_l1_37)}; +wire [2:0] index_l2_19 = {!flag_l1_38,(flag_l1_38?index_l1_38:index_l1_39)}; +wire [2:0] index_l2_20 = {!flag_l1_40,(flag_l1_40?index_l1_40:index_l1_41)}; +wire [2:0] index_l2_21 = {!flag_l1_42,(flag_l1_42?index_l1_42:index_l1_43)}; +wire [2:0] index_l2_22 = {!flag_l1_44,(flag_l1_44?index_l1_44:index_l1_45)}; +wire [2:0] index_l2_23 = {!flag_l1_46,(flag_l1_46?index_l1_46:index_l1_47)}; +wire [2:0] index_l2_24 = {!flag_l1_48,(flag_l1_48?index_l1_48:index_l1_49)}; +wire [2:0] index_l2_25 = {!flag_l1_50,(flag_l1_50?index_l1_50:index_l1_51)}; +wire [2:0] index_l2_26 = {!flag_l1_52,(flag_l1_52?index_l1_52:index_l1_53)}; +wire [2:0] index_l2_27 = {!flag_l1_54,(flag_l1_54?index_l1_54:index_l1_55)}; +wire [2:0] index_l2_28 = {!flag_l1_56,(flag_l1_56?index_l1_56:index_l1_57)}; +wire [2:0] index_l2_29 = {!flag_l1_58,(flag_l1_58?index_l1_58:index_l1_59)}; +wire [2:0] index_l2_30 = {!flag_l1_60,(flag_l1_60?index_l1_60:index_l1_61)}; +wire [2:0] index_l2_31 = {!flag_l1_62,(flag_l1_62?index_l1_62:index_l1_63)}; +wire [3:0] index_l3_0 = {!flag_l2_0,(flag_l2_0?index_l2_0:index_l2_1)}; +wire [3:0] index_l3_1 = {!flag_l2_2,(flag_l2_2?index_l2_2:index_l2_3)}; +wire [3:0] index_l3_2 = {!flag_l2_4,(flag_l2_4?index_l2_4:index_l2_5)}; +wire [3:0] index_l3_3 = {!flag_l2_6,(flag_l2_6?index_l2_6:index_l2_7)}; +wire [3:0] index_l3_4 = {!flag_l2_8,(flag_l2_8?index_l2_8:index_l2_9)}; +wire [3:0] index_l3_5 = {!flag_l2_10,(flag_l2_10?index_l2_10:index_l2_11)}; +wire [3:0] index_l3_6 = {!flag_l2_12,(flag_l2_12?index_l2_12:index_l2_13)}; +wire [3:0] index_l3_7 = {!flag_l2_14,(flag_l2_14?index_l2_14:index_l2_15)}; +wire [3:0] index_l3_8 = {!flag_l2_16,(flag_l2_16?index_l2_16:index_l2_17)}; +wire [3:0] index_l3_9 = {!flag_l2_18,(flag_l2_18?index_l2_18:index_l2_19)}; +wire [3:0] index_l3_10 = {!flag_l2_20,(flag_l2_20?index_l2_20:index_l2_21)}; +wire [3:0] index_l3_11 = {!flag_l2_22,(flag_l2_22?index_l2_22:index_l2_23)}; +wire [3:0] index_l3_12 = {!flag_l2_24,(flag_l2_24?index_l2_24:index_l2_25)}; +wire [3:0] index_l3_13 = {!flag_l2_26,(flag_l2_26?index_l2_26:index_l2_27)}; +wire [3:0] index_l3_14 = {!flag_l2_28,(flag_l2_28?index_l2_28:index_l2_29)}; +wire [3:0] index_l3_15 = {!flag_l2_30,(flag_l2_30?index_l2_30:index_l2_31)}; +wire [4:0] index_l4_0 = {!flag_l3_0,(flag_l3_0?index_l3_0:index_l3_1)}; +wire [4:0] index_l4_1 = {!flag_l3_2,(flag_l3_2?index_l3_2:index_l3_3)}; +wire [4:0] index_l4_2 = {!flag_l3_4,(flag_l3_4?index_l3_4:index_l3_5)}; +wire [4:0] index_l4_3 = {!flag_l3_6,(flag_l3_6?index_l3_6:index_l3_7)}; +wire [4:0] index_l4_4 = {!flag_l3_8,(flag_l3_8?index_l3_8:index_l3_9)}; +wire [4:0] index_l4_5 = {!flag_l3_10,(flag_l3_10?index_l3_10:index_l3_11)}; +wire [4:0] index_l4_6 = {!flag_l3_12,(flag_l3_12?index_l3_12:index_l3_13)}; +wire [4:0] index_l4_7 = {!flag_l3_14,(flag_l3_14?index_l3_14:index_l3_15)}; +wire [5:0] index_l5_0 = {!flag_l4_0,(flag_l4_0?index_l4_0:index_l4_1)}; +wire [5:0] index_l5_1 = {!flag_l4_2,(flag_l4_2?index_l4_2:index_l4_3)}; +wire [5:0] index_l5_2 = {!flag_l4_4,(flag_l4_4?index_l4_4:index_l4_5)}; +wire [5:0] index_l5_3 = {!flag_l4_6,(flag_l4_6?index_l4_6:index_l4_7)}; +wire [6:0] index_l6_0 = {!flag_l5_0,(flag_l5_0?index_l5_0:index_l5_1)}; +wire [6:0] index_l6_1 = {!flag_l5_2,(flag_l5_2?index_l5_2:index_l5_3)}; +wire [7:0] index_l7_0 = {!flag_l6_0,(flag_l6_0?index_l6_0:index_l6_1)}; +assign free_adr_index[7:0] = index_l7_0[7:0]; +assign wr_popping = rd_popping; +// +// READ SIDE +// +// +// credits for taker are simply rd_pushing* +// +reg [9:0] cq_rd_credit; // registered out take credits +reg rd_pushing_q; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_credit <= 10'd0; + rd_pushing_q <= 1'b0; + end else begin + if ( rd_pushing || rd_pushing_q ) begin + cq_rd_credit[0] <= rd_pushing && rd_pushing_thread_id == 4'd0; + cq_rd_credit[1] <= rd_pushing && rd_pushing_thread_id == 4'd1; + cq_rd_credit[2] <= rd_pushing && rd_pushing_thread_id == 4'd2; + cq_rd_credit[3] <= rd_pushing && rd_pushing_thread_id == 4'd3; + cq_rd_credit[4] <= rd_pushing && rd_pushing_thread_id == 4'd4; + cq_rd_credit[5] <= rd_pushing && rd_pushing_thread_id == 4'd5; + cq_rd_credit[6] <= rd_pushing && rd_pushing_thread_id == 4'd6; + cq_rd_credit[7] <= rd_pushing && rd_pushing_thread_id == 4'd7; + cq_rd_credit[8] <= rd_pushing && rd_pushing_thread_id == 4'd8; + cq_rd_credit[9] <= rd_pushing && rd_pushing_thread_id == 4'd9; + rd_pushing_q <= rd_pushing; + end + end +end +wire rd_pushing0 = rd_pushing && rd_pushing_thread_id == 4'd0; +wire rd_pushing1 = rd_pushing && rd_pushing_thread_id == 4'd1; +wire rd_pushing2 = rd_pushing && rd_pushing_thread_id == 4'd2; +wire rd_pushing3 = rd_pushing && rd_pushing_thread_id == 4'd3; +wire rd_pushing4 = rd_pushing && rd_pushing_thread_id == 4'd4; +wire rd_pushing5 = rd_pushing && rd_pushing_thread_id == 4'd5; +wire rd_pushing6 = rd_pushing && rd_pushing_thread_id == 4'd6; +wire rd_pushing7 = rd_pushing && rd_pushing_thread_id == 4'd7; +wire rd_pushing8 = rd_pushing && rd_pushing_thread_id == 4'd8; +wire rd_pushing9 = rd_pushing && rd_pushing_thread_id == 4'd9; +wire rd_take0 = cq_rd_take && cq_rd_take_thread_id == 4'd0; +wire rd_take1 = cq_rd_take && cq_rd_take_thread_id == 4'd1; +wire rd_take2 = cq_rd_take && cq_rd_take_thread_id == 4'd2; +wire rd_take3 = cq_rd_take && cq_rd_take_thread_id == 4'd3; +wire rd_take4 = cq_rd_take && cq_rd_take_thread_id == 4'd4; +wire rd_take5 = cq_rd_take && cq_rd_take_thread_id == 4'd5; +wire rd_take6 = cq_rd_take && cq_rd_take_thread_id == 4'd6; +wire rd_take7 = cq_rd_take && cq_rd_take_thread_id == 4'd7; +wire rd_take8 = cq_rd_take && cq_rd_take_thread_id == 4'd8; +wire rd_take9 = cq_rd_take && cq_rd_take_thread_id == 4'd9; +reg [7:0] head0; // thread 0's head pointer +reg [7:0] tail0; // thread 0's tail pointer +reg [7:0] head1; // thread 1's head pointer +reg [7:0] tail1; // thread 1's tail pointer +reg [7:0] head2; // thread 2's head pointer +reg [7:0] tail2; // thread 2's tail pointer +reg [7:0] head3; // thread 3's head pointer +reg [7:0] tail3; // thread 3's tail pointer +reg [7:0] head4; // thread 4's head pointer +reg [7:0] tail4; // thread 4's tail pointer +reg [7:0] head5; // thread 5's head pointer +reg [7:0] tail5; // thread 5's tail pointer +reg [7:0] head6; // thread 6's head pointer +reg [7:0] tail6; // thread 6's tail pointer +reg [7:0] head7; // thread 7's head pointer +reg [7:0] tail7; // thread 7's tail pointer +reg [7:0] head8; // thread 8's head pointer +reg [7:0] tail8; // thread 8's tail pointer +reg [7:0] head9; // thread 9's head pointer +reg [7:0] tail9; // thread 9's tail pointer +reg [9:0] rd_take_n_dly; +reg rd_take_dly_cg; +wire update_rd_take_n_dly = cq_rd_take || rd_take_dly_cg; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly_cg <= 1'b0; + rd_take_n_dly <= {10{1'b0}}; + end else begin + rd_take_dly_cg <= cq_rd_take; + if ( update_rd_take_n_dly ) begin + rd_take_n_dly <= {rd_take9,rd_take8,rd_take7,rd_take6,rd_take5,rd_take4,rd_take3,rd_take2,rd_take1,rd_take0}; + end +//synopsys translate_off + else if ( !update_rd_take_n_dly) begin + end else begin + rd_take_n_dly <= {10{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] adr_ram_wr_adr; +wire [7:0] adr_ram_wr_data; +reg adr_ram_wr_enable; +reg [7:0] adr_ram_rd_adr; +wire [7:0] adr_ram_rd_data; +reg adr_ram_rd_enable; +reg [8:0] cq_rd_count0; +wire [8:0] rd_count0_next; +reg [8:0] cq_rd_count1; +wire [8:0] rd_count1_next; +reg [8:0] cq_rd_count2; +wire [8:0] rd_count2_next; +reg [8:0] cq_rd_count3; +wire [8:0] rd_count3_next; +reg [8:0] cq_rd_count4; +wire [8:0] rd_count4_next; +reg [8:0] cq_rd_count5; +wire [8:0] rd_count5_next; +reg [8:0] cq_rd_count6; +wire [8:0] rd_count6_next; +reg [8:0] cq_rd_count7; +wire [8:0] rd_count7_next; +reg [8:0] cq_rd_count8; +wire [8:0] rd_count8_next; +reg [8:0] cq_rd_count9; +wire [8:0] rd_count9_next; +assign rd_count0_next = + rd_pushing0 ? ( rd_take0 ? cq_rd_count0 : cq_rd_count0 + 1'd1 ) : + ( rd_take0 ? cq_rd_count0 - 1'd1 : cq_rd_count0 ); +assign rd_count1_next = + rd_pushing1 ? ( rd_take1 ? cq_rd_count1 : cq_rd_count1 + 1'd1 ) : + ( rd_take1 ? cq_rd_count1 - 1'd1 : cq_rd_count1 ); +assign rd_count2_next = + rd_pushing2 ? ( rd_take2 ? cq_rd_count2 : cq_rd_count2 + 1'd1 ) : + ( rd_take2 ? cq_rd_count2 - 1'd1 : cq_rd_count2 ); +assign rd_count3_next = + rd_pushing3 ? ( rd_take3 ? cq_rd_count3 : cq_rd_count3 + 1'd1 ) : + ( rd_take3 ? cq_rd_count3 - 1'd1 : cq_rd_count3 ); +assign rd_count4_next = + rd_pushing4 ? ( rd_take4 ? cq_rd_count4 : cq_rd_count4 + 1'd1 ) : + ( rd_take4 ? cq_rd_count4 - 1'd1 : cq_rd_count4 ); +assign rd_count5_next = + rd_pushing5 ? ( rd_take5 ? cq_rd_count5 : cq_rd_count5 + 1'd1 ) : + ( rd_take5 ? cq_rd_count5 - 1'd1 : cq_rd_count5 ); +assign rd_count6_next = + rd_pushing6 ? ( rd_take6 ? cq_rd_count6 : cq_rd_count6 + 1'd1 ) : + ( rd_take6 ? cq_rd_count6 - 1'd1 : cq_rd_count6 ); +assign rd_count7_next = + rd_pushing7 ? ( rd_take7 ? cq_rd_count7 : cq_rd_count7 + 1'd1 ) : + ( rd_take7 ? cq_rd_count7 - 1'd1 : cq_rd_count7 ); +assign rd_count8_next = + rd_pushing8 ? ( rd_take8 ? cq_rd_count8 : cq_rd_count8 + 1'd1 ) : + ( rd_take8 ? cq_rd_count8 - 1'd1 : cq_rd_count8 ); +assign rd_count9_next = + rd_pushing9 ? ( rd_take9 ? cq_rd_count9 : cq_rd_count9 + 1'd1 ) : + ( rd_take9 ? cq_rd_count9 - 1'd1 : cq_rd_count9 ); +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_count0 <= 9'd0; + cq_rd_count1 <= 9'd0; + cq_rd_count2 <= 9'd0; + cq_rd_count3 <= 9'd0; + cq_rd_count4 <= 9'd0; + cq_rd_count5 <= 9'd0; + cq_rd_count6 <= 9'd0; + cq_rd_count7 <= 9'd0; + cq_rd_count8 <= 9'd0; + cq_rd_count9 <= 9'd0; + end else begin + if ( rd_pushing0 ^ rd_take0 ) begin + cq_rd_count0 <= rd_count0_next; + end +//synopsys translate_off + else if ( !(rd_pushing0 ^ rd_take0) ) begin + end else begin + cq_rd_count0 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing1 ^ rd_take1 ) begin + cq_rd_count1 <= rd_count1_next; + end +//synopsys translate_off + else if ( !(rd_pushing1 ^ rd_take1) ) begin + end else begin + cq_rd_count1 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing2 ^ rd_take2 ) begin + cq_rd_count2 <= rd_count2_next; + end +//synopsys translate_off + else if ( !(rd_pushing2 ^ rd_take2) ) begin + end else begin + cq_rd_count2 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing3 ^ rd_take3 ) begin + cq_rd_count3 <= rd_count3_next; + end +//synopsys translate_off + else if ( !(rd_pushing3 ^ rd_take3) ) begin + end else begin + cq_rd_count3 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing4 ^ rd_take4 ) begin + cq_rd_count4 <= rd_count4_next; + end +//synopsys translate_off + else if ( !(rd_pushing4 ^ rd_take4) ) begin + end else begin + cq_rd_count4 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing5 ^ rd_take5 ) begin + cq_rd_count5 <= rd_count5_next; + end +//synopsys translate_off + else if ( !(rd_pushing5 ^ rd_take5) ) begin + end else begin + cq_rd_count5 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing6 ^ rd_take6 ) begin + cq_rd_count6 <= rd_count6_next; + end +//synopsys translate_off + else if ( !(rd_pushing6 ^ rd_take6) ) begin + end else begin + cq_rd_count6 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing7 ^ rd_take7 ) begin + cq_rd_count7 <= rd_count7_next; + end +//synopsys translate_off + else if ( !(rd_pushing7 ^ rd_take7) ) begin + end else begin + cq_rd_count7 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing8 ^ rd_take8 ) begin + cq_rd_count8 <= rd_count8_next; + end +//synopsys translate_off + else if ( !(rd_pushing8 ^ rd_take8) ) begin + end else begin + cq_rd_count8 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing9 ^ rd_take9 ) begin + cq_rd_count9 <= rd_count9_next; + end +//synopsys translate_off + else if ( !(rd_pushing9 ^ rd_take9) ) begin + end else begin + cq_rd_count9 <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [9:0] update_head; +wire [9:0] update_head_next; +assign update_head_next[0] = (rd_take0 && cq_rd_count0 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[1] = (rd_take1 && cq_rd_count1 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[2] = (rd_take2 && cq_rd_count2 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[3] = (rd_take3 && cq_rd_count3 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[4] = (rd_take4 && cq_rd_count4 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[5] = (rd_take5 && cq_rd_count5 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[6] = (rd_take6 && cq_rd_count6 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[7] = (rd_take7 && cq_rd_count7 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[8] = (rd_take8 && cq_rd_count8 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[9] = (rd_take9 && cq_rd_count9 > 9'd1) ? 1'b1 : 1'b0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + update_head <= 10'd0; + end else begin + if ( rd_pushing || cq_rd_take ) begin + update_head <= update_head_next; + end +//synopsys translate_off + else if ( !(rd_pushing || cq_rd_take) ) begin + end else begin + update_head <= {10{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(posedge nvdla_core_clk_mgated) begin + if ( rd_pushing0 ) begin + tail0 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing0 ) begin + end else begin + tail0 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing0 && cq_rd_count0 == 9'd0 ) || + (rd_pushing0 && rd_take0 && cq_rd_count0 == 9'd1) ) begin + head0 <= rd_pushing_adr; + end else if ( update_head[0] ) begin + head0 <= adr_ram_rd_data; + end + if ( rd_pushing1 ) begin + tail1 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing1 ) begin + end else begin + tail1 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing1 && cq_rd_count1 == 9'd0 ) || + (rd_pushing1 && rd_take1 && cq_rd_count1 == 9'd1) ) begin + head1 <= rd_pushing_adr; + end else if ( update_head[1] ) begin + head1 <= adr_ram_rd_data; + end + if ( rd_pushing2 ) begin + tail2 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing2 ) begin + end else begin + tail2 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing2 && cq_rd_count2 == 9'd0 ) || + (rd_pushing2 && rd_take2 && cq_rd_count2 == 9'd1) ) begin + head2 <= rd_pushing_adr; + end else if ( update_head[2] ) begin + head2 <= adr_ram_rd_data; + end + if ( rd_pushing3 ) begin + tail3 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing3 ) begin + end else begin + tail3 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing3 && cq_rd_count3 == 9'd0 ) || + (rd_pushing3 && rd_take3 && cq_rd_count3 == 9'd1) ) begin + head3 <= rd_pushing_adr; + end else if ( update_head[3] ) begin + head3 <= adr_ram_rd_data; + end + if ( rd_pushing4 ) begin + tail4 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing4 ) begin + end else begin + tail4 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing4 && cq_rd_count4 == 9'd0 ) || + (rd_pushing4 && rd_take4 && cq_rd_count4 == 9'd1) ) begin + head4 <= rd_pushing_adr; + end else if ( update_head[4] ) begin + head4 <= adr_ram_rd_data; + end + if ( rd_pushing5 ) begin + tail5 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing5 ) begin + end else begin + tail5 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing5 && cq_rd_count5 == 9'd0 ) || + (rd_pushing5 && rd_take5 && cq_rd_count5 == 9'd1) ) begin + head5 <= rd_pushing_adr; + end else if ( update_head[5] ) begin + head5 <= adr_ram_rd_data; + end + if ( rd_pushing6 ) begin + tail6 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing6 ) begin + end else begin + tail6 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing6 && cq_rd_count6 == 9'd0 ) || + (rd_pushing6 && rd_take6 && cq_rd_count6 == 9'd1) ) begin + head6 <= rd_pushing_adr; + end else if ( update_head[6] ) begin + head6 <= adr_ram_rd_data; + end + if ( rd_pushing7 ) begin + tail7 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing7 ) begin + end else begin + tail7 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing7 && cq_rd_count7 == 9'd0 ) || + (rd_pushing7 && rd_take7 && cq_rd_count7 == 9'd1) ) begin + head7 <= rd_pushing_adr; + end else if ( update_head[7] ) begin + head7 <= adr_ram_rd_data; + end + if ( rd_pushing8 ) begin + tail8 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing8 ) begin + end else begin + tail8 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing8 && cq_rd_count8 == 9'd0 ) || + (rd_pushing8 && rd_take8 && cq_rd_count8 == 9'd1) ) begin + head8 <= rd_pushing_adr; + end else if ( update_head[8] ) begin + head8 <= adr_ram_rd_data; + end + if ( rd_pushing9 ) begin + tail9 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing9 ) begin + end else begin + tail9 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing9 && cq_rd_count9 == 9'd0 ) || + (rd_pushing9 && rd_take9 && cq_rd_count9 == 9'd1) ) begin + head9 <= rd_pushing_adr; + end else if ( update_head[9] ) begin + head9 <= adr_ram_rd_data; + end +end +nv_ram_rwst_256x8 adr_ram ( + .clk ( nvdla_core_clk ) + , .wa ( adr_ram_wr_adr ) + , .we ( adr_ram_wr_enable ) + , .di ( adr_ram_wr_data ) + , .ra ( adr_ram_rd_adr ) + , .re ( adr_ram_rd_enable ) + , .dout ( adr_ram_rd_data ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + ); +assign adr_ram_wr_data = rd_pushing_adr; +always @(*) begin + case( rd_pushing_thread_id ) + 4'd0: adr_ram_wr_adr = tail0; + 4'd1: adr_ram_wr_adr = tail1; + 4'd2: adr_ram_wr_adr = tail2; + 4'd3: adr_ram_wr_adr = tail3; + 4'd4: adr_ram_wr_adr = tail4; + 4'd5: adr_ram_wr_adr = tail5; + 4'd6: adr_ram_wr_adr = tail6; + 4'd7: adr_ram_wr_adr = tail7; + 4'd8: adr_ram_wr_adr = tail8; + 4'd9: adr_ram_wr_adr = tail9; +//VCS coverage off + default: adr_ram_wr_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( rd_pushing_thread_id ) + 4'd0: adr_ram_wr_enable = rd_pushing && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 4'd1: adr_ram_wr_enable = rd_pushing && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 4'd2: adr_ram_wr_enable = rd_pushing && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 4'd3: adr_ram_wr_enable = rd_pushing && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 4'd4: adr_ram_wr_enable = rd_pushing && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; + 4'd5: adr_ram_wr_enable = rd_pushing && cq_rd_count5 != 9'd0 ? 1'b1 : 1'b0; + 4'd6: adr_ram_wr_enable = rd_pushing && cq_rd_count6 != 9'd0 ? 1'b1 : 1'b0; + 4'd7: adr_ram_wr_enable = rd_pushing && cq_rd_count7 != 9'd0 ? 1'b1 : 1'b0; + 4'd8: adr_ram_wr_enable = rd_pushing && cq_rd_count8 != 9'd0 ? 1'b1 : 1'b0; + 4'd9: adr_ram_wr_enable = rd_pushing && cq_rd_count9 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_wr_enable = !rd_pushing ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 4'd0: adr_ram_rd_enable = cq_rd_take && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 4'd1: adr_ram_rd_enable = cq_rd_take && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 4'd2: adr_ram_rd_enable = cq_rd_take && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 4'd3: adr_ram_rd_enable = cq_rd_take && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 4'd4: adr_ram_rd_enable = cq_rd_take && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; + 4'd5: adr_ram_rd_enable = cq_rd_take && cq_rd_count5 != 9'd0 ? 1'b1 : 1'b0; + 4'd6: adr_ram_rd_enable = cq_rd_take && cq_rd_count6 != 9'd0 ? 1'b1 : 1'b0; + 4'd7: adr_ram_rd_enable = cq_rd_take && cq_rd_count7 != 9'd0 ? 1'b1 : 1'b0; + 4'd8: adr_ram_rd_enable = cq_rd_take && cq_rd_count8 != 9'd0 ? 1'b1 : 1'b0; + 4'd9: adr_ram_rd_enable = cq_rd_take && cq_rd_count9 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_rd_enable = !cq_rd_take ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 4'd0: adr_ram_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 4'd1: adr_ram_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 4'd2: adr_ram_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 4'd3: adr_ram_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 4'd4: adr_ram_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; + 4'd5: adr_ram_rd_adr = rd_take_n_dly[5] && update_head[5] ? adr_ram_rd_data : head5; + 4'd6: adr_ram_rd_adr = rd_take_n_dly[6] && update_head[6] ? adr_ram_rd_data : head6; + 4'd7: adr_ram_rd_adr = rd_take_n_dly[7] && update_head[7] ? adr_ram_rd_data : head7; + 4'd8: adr_ram_rd_adr = rd_take_n_dly[8] && update_head[8] ? adr_ram_rd_data : head8; + 4'd9: adr_ram_rd_adr = rd_take_n_dly[9] && update_head[9] ? adr_ram_rd_data : head9; +//VCS coverage off + default: adr_ram_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 4'd0: cq_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 4'd1: cq_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 4'd2: cq_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 4'd3: cq_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 4'd4: cq_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; + 4'd5: cq_rd_adr = rd_take_n_dly[5] && update_head[5] ? adr_ram_rd_data : head5; + 4'd6: cq_rd_adr = rd_take_n_dly[6] && update_head[6] ? adr_ram_rd_data : head6; + 4'd7: cq_rd_adr = rd_take_n_dly[7] && update_head[7] ? adr_ram_rd_data : head7; + 4'd8: cq_rd_adr = rd_take_n_dly[8] && update_head[8] ? adr_ram_rd_data : head8; + 4'd9: cq_rd_adr = rd_take_n_dly[9] && update_head[9] ? adr_ram_rd_data : head9; +//VCS coverage off + default: cq_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +// +// take data comes out next cycle for non-ff rams. +// +reg rd_take_dly; +assign rd_popping = rd_take_dly; +reg [7:0] rd_adr_dly; +assign rd_popping_adr = rd_adr_dly; +assign rd_enable = cq_rd_take; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly <= 1'b0; + end else begin + rd_take_dly <= cq_rd_take; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( cq_rd_take ) begin + rd_adr_dly <= cq_rd_adr; + end +//synopsys translate_off + else if ( !(cq_rd_take) ) begin + end else begin + rd_adr_dly <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// +// -rd_take_to_rd_busy conversion (conceptually outside the fifo except for ra2 bypass) +// +wire [9:0] cq_rd_take_elig; // mask of threads that can do takes this cycle +wire rd_pre_bypassing0; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing0; // between cq_rd0_pvld and cq_rd0_prdy when doing full bypass +reg [6:0] rd_skid0_0; // head skid reg +reg [6:0] rd_skid0_1; // head+1 skid reg +reg [6:0] rd_skid0_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid0_0_vld; // head skid reg has valid data +reg rd_skid0_1_vld; // head+1 skid reg has valid data +reg rd_skid0_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd0_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_prdy_d <= 1'b1; + end else begin + cq_rd0_prdy_d <= cq_rd0_prdy; + end +end +assign cq_rd0_pvld = rd_skid0_0_vld || rd_pre_bypassing0; // full bypass for 0-latency +assign cq_rd0_pd = rd_skid0_0_vld ? rd_skid0_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld)) ) begin + rd_skid0_0 <= rd_take_n_dly[0] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld ) begin + rd_skid0_0 <= rd_skid0_1; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld) ) begin + end else begin + rd_skid0_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld)) ) begin + rd_skid0_1 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld ) begin + rd_skid0_1 <= rd_skid0_2; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld) ) begin + end else begin + rd_skid0_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy)) ) begin + rd_skid0_2 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy))) ) begin + end else begin + rd_skid0_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid0_0_vld <= 1'b0; + rd_skid0_1_vld <= 1'b0; + rd_skid0_2_vld <= 1'b0; + end else begin + rd_skid0_0_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_1_vld || (rd_bypassing0 && rd_skid0_0_vld) || rd_take_n_dly[0]) : (rd_skid0_0_vld || rd_bypassing0 || rd_take_n_dly[0]); + rd_skid0_1_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))) : (rd_skid0_1_vld || (rd_skid0_0_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage off + rd_skid0_2_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld && (rd_bypassing0 || rd_take_n_dly[0])) : (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd0_credits; // unused credits +reg cq_rd0_credits_ne0; +wire [8:0] cq_rd0_credits_w_take_next = cq_rd0_credits + cq_rd_credit[0] - 1'b1; +wire [8:0] cq_rd0_credits_wo_take_next = cq_rd0_credits + cq_rd_credit[0]; +wire [8:0] cq_rd0_credits_next = rd_take0 ? cq_rd0_credits_w_take_next : cq_rd0_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[0] = (cq_rd0_prdy_d || !rd_skid0_0_vld || !rd_skid0_1_vld || (!rd_skid0_2_vld && !rd_take_n_dly[0])) && (cq_rd_credit[0] || cq_rd0_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing0 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd0) && cq_rd0_credits == 0 && !cq_rd_credit[0] && (!rd_take_n_dly[0] || rd_skid0_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing0 = rd_pre_bypassing0 && (!rd_skid0_2_vld || !rd_skid0_1_vld || !(!cq_rd0_prdy_d && rd_skid0_0_vld && rd_skid0_1_vld)) && !rd_take_n_dly[0]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_credits <= 9'd0; + cq_rd0_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[0] | rd_take0 ) begin + cq_rd0_credits <= cq_rd0_credits_next; + cq_rd0_credits_ne0 <= rd_take0 ? (cq_rd0_credits_w_take_next != 0) : (cq_rd0_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[0] | rd_take0) ) begin + end else begin + cq_rd0_credits <= {9{`x_or_0}}; + cq_rd0_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing1; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing1; // between cq_rd1_pvld and cq_rd1_prdy when doing full bypass +reg [6:0] rd_skid1_0; // head skid reg +reg [6:0] rd_skid1_1; // head+1 skid reg +reg [6:0] rd_skid1_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid1_0_vld; // head skid reg has valid data +reg rd_skid1_1_vld; // head+1 skid reg has valid data +reg rd_skid1_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd1_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_prdy_d <= 1'b1; + end else begin + cq_rd1_prdy_d <= cq_rd1_prdy; + end +end +assign cq_rd1_pvld = rd_skid1_0_vld || rd_pre_bypassing1; // full bypass for 0-latency +assign cq_rd1_pd = rd_skid1_0_vld ? rd_skid1_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld)) ) begin + rd_skid1_0 <= rd_take_n_dly[1] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld ) begin + rd_skid1_0 <= rd_skid1_1; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld) ) begin + end else begin + rd_skid1_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld)) ) begin + rd_skid1_1 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld ) begin + rd_skid1_1 <= rd_skid1_2; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld) ) begin + end else begin + rd_skid1_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy)) ) begin + rd_skid1_2 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy))) ) begin + end else begin + rd_skid1_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid1_0_vld <= 1'b0; + rd_skid1_1_vld <= 1'b0; + rd_skid1_2_vld <= 1'b0; + end else begin + rd_skid1_0_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_1_vld || (rd_bypassing1 && rd_skid1_0_vld) || rd_take_n_dly[1]) : (rd_skid1_0_vld || rd_bypassing1 || rd_take_n_dly[1]); + rd_skid1_1_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))) : (rd_skid1_1_vld || (rd_skid1_0_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage off + rd_skid1_2_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld && (rd_bypassing1 || rd_take_n_dly[1])) : (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd1_credits; // unused credits +reg cq_rd1_credits_ne0; +wire [8:0] cq_rd1_credits_w_take_next = cq_rd1_credits + cq_rd_credit[1] - 1'b1; +wire [8:0] cq_rd1_credits_wo_take_next = cq_rd1_credits + cq_rd_credit[1]; +wire [8:0] cq_rd1_credits_next = rd_take1 ? cq_rd1_credits_w_take_next : cq_rd1_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[1] = (cq_rd1_prdy_d || !rd_skid1_0_vld || !rd_skid1_1_vld || (!rd_skid1_2_vld && !rd_take_n_dly[1])) && (cq_rd_credit[1] || cq_rd1_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing1 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd1) && cq_rd1_credits == 0 && !cq_rd_credit[1] && (!rd_take_n_dly[1] || rd_skid1_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing1 = rd_pre_bypassing1 && (!rd_skid1_2_vld || !rd_skid1_1_vld || !(!cq_rd1_prdy_d && rd_skid1_0_vld && rd_skid1_1_vld)) && !rd_take_n_dly[1]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_credits <= 9'd0; + cq_rd1_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[1] | rd_take1 ) begin + cq_rd1_credits <= cq_rd1_credits_next; + cq_rd1_credits_ne0 <= rd_take1 ? (cq_rd1_credits_w_take_next != 0) : (cq_rd1_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[1] | rd_take1) ) begin + end else begin + cq_rd1_credits <= {9{`x_or_0}}; + cq_rd1_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing2; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing2; // between cq_rd2_pvld and cq_rd2_prdy when doing full bypass +reg [6:0] rd_skid2_0; // head skid reg +reg [6:0] rd_skid2_1; // head+1 skid reg +reg [6:0] rd_skid2_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid2_0_vld; // head skid reg has valid data +reg rd_skid2_1_vld; // head+1 skid reg has valid data +reg rd_skid2_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd2_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_prdy_d <= 1'b1; + end else begin + cq_rd2_prdy_d <= cq_rd2_prdy; + end +end +assign cq_rd2_pvld = rd_skid2_0_vld || rd_pre_bypassing2; // full bypass for 0-latency +assign cq_rd2_pd = rd_skid2_0_vld ? rd_skid2_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld)) ) begin + rd_skid2_0 <= rd_take_n_dly[2] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld ) begin + rd_skid2_0 <= rd_skid2_1; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld) ) begin + end else begin + rd_skid2_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld)) ) begin + rd_skid2_1 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld ) begin + rd_skid2_1 <= rd_skid2_2; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld) ) begin + end else begin + rd_skid2_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy)) ) begin + rd_skid2_2 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy))) ) begin + end else begin + rd_skid2_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid2_0_vld <= 1'b0; + rd_skid2_1_vld <= 1'b0; + rd_skid2_2_vld <= 1'b0; + end else begin + rd_skid2_0_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_1_vld || (rd_bypassing2 && rd_skid2_0_vld) || rd_take_n_dly[2]) : (rd_skid2_0_vld || rd_bypassing2 || rd_take_n_dly[2]); + rd_skid2_1_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))) : (rd_skid2_1_vld || (rd_skid2_0_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage off + rd_skid2_2_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld && (rd_bypassing2 || rd_take_n_dly[2])) : (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd2_credits; // unused credits +reg cq_rd2_credits_ne0; +wire [8:0] cq_rd2_credits_w_take_next = cq_rd2_credits + cq_rd_credit[2] - 1'b1; +wire [8:0] cq_rd2_credits_wo_take_next = cq_rd2_credits + cq_rd_credit[2]; +wire [8:0] cq_rd2_credits_next = rd_take2 ? cq_rd2_credits_w_take_next : cq_rd2_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[2] = (cq_rd2_prdy_d || !rd_skid2_0_vld || !rd_skid2_1_vld || (!rd_skid2_2_vld && !rd_take_n_dly[2])) && (cq_rd_credit[2] || cq_rd2_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing2 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd2) && cq_rd2_credits == 0 && !cq_rd_credit[2] && (!rd_take_n_dly[2] || rd_skid2_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing2 = rd_pre_bypassing2 && (!rd_skid2_2_vld || !rd_skid2_1_vld || !(!cq_rd2_prdy_d && rd_skid2_0_vld && rd_skid2_1_vld)) && !rd_take_n_dly[2]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_credits <= 9'd0; + cq_rd2_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[2] | rd_take2 ) begin + cq_rd2_credits <= cq_rd2_credits_next; + cq_rd2_credits_ne0 <= rd_take2 ? (cq_rd2_credits_w_take_next != 0) : (cq_rd2_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[2] | rd_take2) ) begin + end else begin + cq_rd2_credits <= {9{`x_or_0}}; + cq_rd2_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing3; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing3; // between cq_rd3_pvld and cq_rd3_prdy when doing full bypass +reg [6:0] rd_skid3_0; // head skid reg +reg [6:0] rd_skid3_1; // head+1 skid reg +reg [6:0] rd_skid3_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid3_0_vld; // head skid reg has valid data +reg rd_skid3_1_vld; // head+1 skid reg has valid data +reg rd_skid3_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd3_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_prdy_d <= 1'b1; + end else begin + cq_rd3_prdy_d <= cq_rd3_prdy; + end +end +assign cq_rd3_pvld = rd_skid3_0_vld || rd_pre_bypassing3; // full bypass for 0-latency +assign cq_rd3_pd = rd_skid3_0_vld ? rd_skid3_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld)) ) begin + rd_skid3_0 <= rd_take_n_dly[3] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld ) begin + rd_skid3_0 <= rd_skid3_1; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld) ) begin + end else begin + rd_skid3_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld)) ) begin + rd_skid3_1 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld ) begin + rd_skid3_1 <= rd_skid3_2; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld) ) begin + end else begin + rd_skid3_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy)) ) begin + rd_skid3_2 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy))) ) begin + end else begin + rd_skid3_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid3_0_vld <= 1'b0; + rd_skid3_1_vld <= 1'b0; + rd_skid3_2_vld <= 1'b0; + end else begin + rd_skid3_0_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_1_vld || (rd_bypassing3 && rd_skid3_0_vld) || rd_take_n_dly[3]) : (rd_skid3_0_vld || rd_bypassing3 || rd_take_n_dly[3]); + rd_skid3_1_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))) : (rd_skid3_1_vld || (rd_skid3_0_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage off + rd_skid3_2_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld && (rd_bypassing3 || rd_take_n_dly[3])) : (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd3_credits; // unused credits +reg cq_rd3_credits_ne0; +wire [8:0] cq_rd3_credits_w_take_next = cq_rd3_credits + cq_rd_credit[3] - 1'b1; +wire [8:0] cq_rd3_credits_wo_take_next = cq_rd3_credits + cq_rd_credit[3]; +wire [8:0] cq_rd3_credits_next = rd_take3 ? cq_rd3_credits_w_take_next : cq_rd3_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[3] = (cq_rd3_prdy_d || !rd_skid3_0_vld || !rd_skid3_1_vld || (!rd_skid3_2_vld && !rd_take_n_dly[3])) && (cq_rd_credit[3] || cq_rd3_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing3 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd3) && cq_rd3_credits == 0 && !cq_rd_credit[3] && (!rd_take_n_dly[3] || rd_skid3_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing3 = rd_pre_bypassing3 && (!rd_skid3_2_vld || !rd_skid3_1_vld || !(!cq_rd3_prdy_d && rd_skid3_0_vld && rd_skid3_1_vld)) && !rd_take_n_dly[3]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_credits <= 9'd0; + cq_rd3_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[3] | rd_take3 ) begin + cq_rd3_credits <= cq_rd3_credits_next; + cq_rd3_credits_ne0 <= rd_take3 ? (cq_rd3_credits_w_take_next != 0) : (cq_rd3_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[3] | rd_take3) ) begin + end else begin + cq_rd3_credits <= {9{`x_or_0}}; + cq_rd3_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing4; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing4; // between cq_rd4_pvld and cq_rd4_prdy when doing full bypass +reg [6:0] rd_skid4_0; // head skid reg +reg [6:0] rd_skid4_1; // head+1 skid reg +reg [6:0] rd_skid4_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid4_0_vld; // head skid reg has valid data +reg rd_skid4_1_vld; // head+1 skid reg has valid data +reg rd_skid4_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd4_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_prdy_d <= 1'b1; + end else begin + cq_rd4_prdy_d <= cq_rd4_prdy; + end +end +assign cq_rd4_pvld = rd_skid4_0_vld || rd_pre_bypassing4; // full bypass for 0-latency +assign cq_rd4_pd = rd_skid4_0_vld ? rd_skid4_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld)) ) begin + rd_skid4_0 <= rd_take_n_dly[4] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld ) begin + rd_skid4_0 <= rd_skid4_1; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld) ) begin + end else begin + rd_skid4_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld)) ) begin + rd_skid4_1 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld ) begin + rd_skid4_1 <= rd_skid4_2; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld) ) begin + end else begin + rd_skid4_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy)) ) begin + rd_skid4_2 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy))) ) begin + end else begin + rd_skid4_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid4_0_vld <= 1'b0; + rd_skid4_1_vld <= 1'b0; + rd_skid4_2_vld <= 1'b0; + end else begin + rd_skid4_0_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_1_vld || (rd_bypassing4 && rd_skid4_0_vld) || rd_take_n_dly[4]) : (rd_skid4_0_vld || rd_bypassing4 || rd_take_n_dly[4]); + rd_skid4_1_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))) : (rd_skid4_1_vld || (rd_skid4_0_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage off + rd_skid4_2_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld && (rd_bypassing4 || rd_take_n_dly[4])) : (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd4_credits; // unused credits +reg cq_rd4_credits_ne0; +wire [8:0] cq_rd4_credits_w_take_next = cq_rd4_credits + cq_rd_credit[4] - 1'b1; +wire [8:0] cq_rd4_credits_wo_take_next = cq_rd4_credits + cq_rd_credit[4]; +wire [8:0] cq_rd4_credits_next = rd_take4 ? cq_rd4_credits_w_take_next : cq_rd4_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[4] = (cq_rd4_prdy_d || !rd_skid4_0_vld || !rd_skid4_1_vld || (!rd_skid4_2_vld && !rd_take_n_dly[4])) && (cq_rd_credit[4] || cq_rd4_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing4 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd4) && cq_rd4_credits == 0 && !cq_rd_credit[4] && (!rd_take_n_dly[4] || rd_skid4_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing4 = rd_pre_bypassing4 && (!rd_skid4_2_vld || !rd_skid4_1_vld || !(!cq_rd4_prdy_d && rd_skid4_0_vld && rd_skid4_1_vld)) && !rd_take_n_dly[4]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_credits <= 9'd0; + cq_rd4_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[4] | rd_take4 ) begin + cq_rd4_credits <= cq_rd4_credits_next; + cq_rd4_credits_ne0 <= rd_take4 ? (cq_rd4_credits_w_take_next != 0) : (cq_rd4_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[4] | rd_take4) ) begin + end else begin + cq_rd4_credits <= {9{`x_or_0}}; + cq_rd4_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing5; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing5; // between cq_rd5_pvld and cq_rd5_prdy when doing full bypass +reg [6:0] rd_skid5_0; // head skid reg +reg [6:0] rd_skid5_1; // head+1 skid reg +reg [6:0] rd_skid5_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid5_0_vld; // head skid reg has valid data +reg rd_skid5_1_vld; // head+1 skid reg has valid data +reg rd_skid5_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd5_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd5_prdy_d <= 1'b1; + end else begin + cq_rd5_prdy_d <= cq_rd5_prdy; + end +end +assign cq_rd5_pvld = rd_skid5_0_vld || rd_pre_bypassing5; // full bypass for 0-latency +assign cq_rd5_pd = rd_skid5_0_vld ? rd_skid5_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_0_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_1_vld)) ) begin + rd_skid5_0 <= rd_take_n_dly[5] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd5_pvld && cq_rd5_prdy && rd_skid5_1_vld ) begin + rd_skid5_0 <= rd_skid5_1; + end +//synopsys translate_off + else if ( !((rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_0_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_1_vld))) && + !(cq_rd5_pvld && cq_rd5_prdy && rd_skid5_1_vld) ) begin + end else begin + rd_skid5_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_1_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_2_vld)) ) begin + rd_skid5_1 <= rd_bypassing5 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd5_pvld && cq_rd5_prdy && rd_skid5_2_vld ) begin + rd_skid5_1 <= rd_skid5_2; + end +//synopsys translate_off + else if ( !((rd_bypassing5 || rd_take_n_dly[5]) && (!rd_skid5_1_vld || (cq_rd5_pvld && cq_rd5_prdy && !rd_skid5_2_vld))) && + !(cq_rd5_pvld && cq_rd5_prdy && rd_skid5_2_vld) ) begin + end else begin + rd_skid5_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing5 || rd_take_n_dly[5]) && rd_skid5_0_vld && rd_skid5_1_vld && (rd_skid5_2_vld || !(cq_rd5_pvld && cq_rd5_prdy)) ) begin + rd_skid5_2 <= rd_bypassing5 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing5 || rd_take_n_dly[5]) && rd_skid5_0_vld && rd_skid5_1_vld && (rd_skid5_2_vld || !(cq_rd5_pvld && cq_rd5_prdy))) ) begin + end else begin + rd_skid5_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid5_0_vld <= 1'b0; + rd_skid5_1_vld <= 1'b0; + rd_skid5_2_vld <= 1'b0; + end else begin + rd_skid5_0_vld <= (cq_rd5_pvld && cq_rd5_prdy) ? (rd_skid5_1_vld || (rd_bypassing5 && rd_skid5_0_vld) || rd_take_n_dly[5]) : (rd_skid5_0_vld || rd_bypassing5 || rd_take_n_dly[5]); + rd_skid5_1_vld <= (cq_rd5_pvld && cq_rd5_prdy) ? (rd_skid5_2_vld || (rd_skid5_1_vld && (rd_bypassing5 || rd_take_n_dly[5]))) : (rd_skid5_1_vld || (rd_skid5_0_vld && (rd_bypassing5 || rd_take_n_dly[5]))); +//VCS coverage off + rd_skid5_2_vld <= (cq_rd5_pvld && cq_rd5_prdy) ? (rd_skid5_2_vld && (rd_bypassing5 || rd_take_n_dly[5])) : (rd_skid5_2_vld || (rd_skid5_1_vld && (rd_bypassing5 || rd_take_n_dly[5]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd5_credits; // unused credits +reg cq_rd5_credits_ne0; +wire [8:0] cq_rd5_credits_w_take_next = cq_rd5_credits + cq_rd_credit[5] - 1'b1; +wire [8:0] cq_rd5_credits_wo_take_next = cq_rd5_credits + cq_rd_credit[5]; +wire [8:0] cq_rd5_credits_next = rd_take5 ? cq_rd5_credits_w_take_next : cq_rd5_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[5] = (cq_rd5_prdy_d || !rd_skid5_0_vld || !rd_skid5_1_vld || (!rd_skid5_2_vld && !rd_take_n_dly[5])) && (cq_rd_credit[5] || cq_rd5_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing5 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd5) && cq_rd5_credits == 0 && !cq_rd_credit[5] && (!rd_take_n_dly[5] || rd_skid5_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing5 = rd_pre_bypassing5 && (!rd_skid5_2_vld || !rd_skid5_1_vld || !(!cq_rd5_prdy_d && rd_skid5_0_vld && rd_skid5_1_vld)) && !rd_take_n_dly[5]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd5_credits <= 9'd0; + cq_rd5_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[5] | rd_take5 ) begin + cq_rd5_credits <= cq_rd5_credits_next; + cq_rd5_credits_ne0 <= rd_take5 ? (cq_rd5_credits_w_take_next != 0) : (cq_rd5_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[5] | rd_take5) ) begin + end else begin + cq_rd5_credits <= {9{`x_or_0}}; + cq_rd5_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing6; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing6; // between cq_rd6_pvld and cq_rd6_prdy when doing full bypass +reg [6:0] rd_skid6_0; // head skid reg +reg [6:0] rd_skid6_1; // head+1 skid reg +reg [6:0] rd_skid6_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid6_0_vld; // head skid reg has valid data +reg rd_skid6_1_vld; // head+1 skid reg has valid data +reg rd_skid6_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd6_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd6_prdy_d <= 1'b1; + end else begin + cq_rd6_prdy_d <= cq_rd6_prdy; + end +end +assign cq_rd6_pvld = rd_skid6_0_vld || rd_pre_bypassing6; // full bypass for 0-latency +assign cq_rd6_pd = rd_skid6_0_vld ? rd_skid6_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_0_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_1_vld)) ) begin + rd_skid6_0 <= rd_take_n_dly[6] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd6_pvld && cq_rd6_prdy && rd_skid6_1_vld ) begin + rd_skid6_0 <= rd_skid6_1; + end +//synopsys translate_off + else if ( !((rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_0_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_1_vld))) && + !(cq_rd6_pvld && cq_rd6_prdy && rd_skid6_1_vld) ) begin + end else begin + rd_skid6_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_1_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_2_vld)) ) begin + rd_skid6_1 <= rd_bypassing6 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd6_pvld && cq_rd6_prdy && rd_skid6_2_vld ) begin + rd_skid6_1 <= rd_skid6_2; + end +//synopsys translate_off + else if ( !((rd_bypassing6 || rd_take_n_dly[6]) && (!rd_skid6_1_vld || (cq_rd6_pvld && cq_rd6_prdy && !rd_skid6_2_vld))) && + !(cq_rd6_pvld && cq_rd6_prdy && rd_skid6_2_vld) ) begin + end else begin + rd_skid6_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing6 || rd_take_n_dly[6]) && rd_skid6_0_vld && rd_skid6_1_vld && (rd_skid6_2_vld || !(cq_rd6_pvld && cq_rd6_prdy)) ) begin + rd_skid6_2 <= rd_bypassing6 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing6 || rd_take_n_dly[6]) && rd_skid6_0_vld && rd_skid6_1_vld && (rd_skid6_2_vld || !(cq_rd6_pvld && cq_rd6_prdy))) ) begin + end else begin + rd_skid6_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid6_0_vld <= 1'b0; + rd_skid6_1_vld <= 1'b0; + rd_skid6_2_vld <= 1'b0; + end else begin + rd_skid6_0_vld <= (cq_rd6_pvld && cq_rd6_prdy) ? (rd_skid6_1_vld || (rd_bypassing6 && rd_skid6_0_vld) || rd_take_n_dly[6]) : (rd_skid6_0_vld || rd_bypassing6 || rd_take_n_dly[6]); + rd_skid6_1_vld <= (cq_rd6_pvld && cq_rd6_prdy) ? (rd_skid6_2_vld || (rd_skid6_1_vld && (rd_bypassing6 || rd_take_n_dly[6]))) : (rd_skid6_1_vld || (rd_skid6_0_vld && (rd_bypassing6 || rd_take_n_dly[6]))); +//VCS coverage off + rd_skid6_2_vld <= (cq_rd6_pvld && cq_rd6_prdy) ? (rd_skid6_2_vld && (rd_bypassing6 || rd_take_n_dly[6])) : (rd_skid6_2_vld || (rd_skid6_1_vld && (rd_bypassing6 || rd_take_n_dly[6]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd6_credits; // unused credits +reg cq_rd6_credits_ne0; +wire [8:0] cq_rd6_credits_w_take_next = cq_rd6_credits + cq_rd_credit[6] - 1'b1; +wire [8:0] cq_rd6_credits_wo_take_next = cq_rd6_credits + cq_rd_credit[6]; +wire [8:0] cq_rd6_credits_next = rd_take6 ? cq_rd6_credits_w_take_next : cq_rd6_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[6] = (cq_rd6_prdy_d || !rd_skid6_0_vld || !rd_skid6_1_vld || (!rd_skid6_2_vld && !rd_take_n_dly[6])) && (cq_rd_credit[6] || cq_rd6_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing6 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd6) && cq_rd6_credits == 0 && !cq_rd_credit[6] && (!rd_take_n_dly[6] || rd_skid6_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing6 = rd_pre_bypassing6 && (!rd_skid6_2_vld || !rd_skid6_1_vld || !(!cq_rd6_prdy_d && rd_skid6_0_vld && rd_skid6_1_vld)) && !rd_take_n_dly[6]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd6_credits <= 9'd0; + cq_rd6_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[6] | rd_take6 ) begin + cq_rd6_credits <= cq_rd6_credits_next; + cq_rd6_credits_ne0 <= rd_take6 ? (cq_rd6_credits_w_take_next != 0) : (cq_rd6_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[6] | rd_take6) ) begin + end else begin + cq_rd6_credits <= {9{`x_or_0}}; + cq_rd6_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing7; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing7; // between cq_rd7_pvld and cq_rd7_prdy when doing full bypass +reg [6:0] rd_skid7_0; // head skid reg +reg [6:0] rd_skid7_1; // head+1 skid reg +reg [6:0] rd_skid7_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid7_0_vld; // head skid reg has valid data +reg rd_skid7_1_vld; // head+1 skid reg has valid data +reg rd_skid7_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd7_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd7_prdy_d <= 1'b1; + end else begin + cq_rd7_prdy_d <= cq_rd7_prdy; + end +end +assign cq_rd7_pvld = rd_skid7_0_vld || rd_pre_bypassing7; // full bypass for 0-latency +assign cq_rd7_pd = rd_skid7_0_vld ? rd_skid7_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_0_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_1_vld)) ) begin + rd_skid7_0 <= rd_take_n_dly[7] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd7_pvld && cq_rd7_prdy && rd_skid7_1_vld ) begin + rd_skid7_0 <= rd_skid7_1; + end +//synopsys translate_off + else if ( !((rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_0_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_1_vld))) && + !(cq_rd7_pvld && cq_rd7_prdy && rd_skid7_1_vld) ) begin + end else begin + rd_skid7_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_1_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_2_vld)) ) begin + rd_skid7_1 <= rd_bypassing7 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd7_pvld && cq_rd7_prdy && rd_skid7_2_vld ) begin + rd_skid7_1 <= rd_skid7_2; + end +//synopsys translate_off + else if ( !((rd_bypassing7 || rd_take_n_dly[7]) && (!rd_skid7_1_vld || (cq_rd7_pvld && cq_rd7_prdy && !rd_skid7_2_vld))) && + !(cq_rd7_pvld && cq_rd7_prdy && rd_skid7_2_vld) ) begin + end else begin + rd_skid7_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing7 || rd_take_n_dly[7]) && rd_skid7_0_vld && rd_skid7_1_vld && (rd_skid7_2_vld || !(cq_rd7_pvld && cq_rd7_prdy)) ) begin + rd_skid7_2 <= rd_bypassing7 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing7 || rd_take_n_dly[7]) && rd_skid7_0_vld && rd_skid7_1_vld && (rd_skid7_2_vld || !(cq_rd7_pvld && cq_rd7_prdy))) ) begin + end else begin + rd_skid7_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid7_0_vld <= 1'b0; + rd_skid7_1_vld <= 1'b0; + rd_skid7_2_vld <= 1'b0; + end else begin + rd_skid7_0_vld <= (cq_rd7_pvld && cq_rd7_prdy) ? (rd_skid7_1_vld || (rd_bypassing7 && rd_skid7_0_vld) || rd_take_n_dly[7]) : (rd_skid7_0_vld || rd_bypassing7 || rd_take_n_dly[7]); + rd_skid7_1_vld <= (cq_rd7_pvld && cq_rd7_prdy) ? (rd_skid7_2_vld || (rd_skid7_1_vld && (rd_bypassing7 || rd_take_n_dly[7]))) : (rd_skid7_1_vld || (rd_skid7_0_vld && (rd_bypassing7 || rd_take_n_dly[7]))); +//VCS coverage off + rd_skid7_2_vld <= (cq_rd7_pvld && cq_rd7_prdy) ? (rd_skid7_2_vld && (rd_bypassing7 || rd_take_n_dly[7])) : (rd_skid7_2_vld || (rd_skid7_1_vld && (rd_bypassing7 || rd_take_n_dly[7]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd7_credits; // unused credits +reg cq_rd7_credits_ne0; +wire [8:0] cq_rd7_credits_w_take_next = cq_rd7_credits + cq_rd_credit[7] - 1'b1; +wire [8:0] cq_rd7_credits_wo_take_next = cq_rd7_credits + cq_rd_credit[7]; +wire [8:0] cq_rd7_credits_next = rd_take7 ? cq_rd7_credits_w_take_next : cq_rd7_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[7] = (cq_rd7_prdy_d || !rd_skid7_0_vld || !rd_skid7_1_vld || (!rd_skid7_2_vld && !rd_take_n_dly[7])) && (cq_rd_credit[7] || cq_rd7_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing7 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd7) && cq_rd7_credits == 0 && !cq_rd_credit[7] && (!rd_take_n_dly[7] || rd_skid7_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing7 = rd_pre_bypassing7 && (!rd_skid7_2_vld || !rd_skid7_1_vld || !(!cq_rd7_prdy_d && rd_skid7_0_vld && rd_skid7_1_vld)) && !rd_take_n_dly[7]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd7_credits <= 9'd0; + cq_rd7_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[7] | rd_take7 ) begin + cq_rd7_credits <= cq_rd7_credits_next; + cq_rd7_credits_ne0 <= rd_take7 ? (cq_rd7_credits_w_take_next != 0) : (cq_rd7_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[7] | rd_take7) ) begin + end else begin + cq_rd7_credits <= {9{`x_or_0}}; + cq_rd7_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing8; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing8; // between cq_rd8_pvld and cq_rd8_prdy when doing full bypass +reg [6:0] rd_skid8_0; // head skid reg +reg [6:0] rd_skid8_1; // head+1 skid reg +reg [6:0] rd_skid8_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid8_0_vld; // head skid reg has valid data +reg rd_skid8_1_vld; // head+1 skid reg has valid data +reg rd_skid8_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd8_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd8_prdy_d <= 1'b1; + end else begin + cq_rd8_prdy_d <= cq_rd8_prdy; + end +end +assign cq_rd8_pvld = rd_skid8_0_vld || rd_pre_bypassing8; // full bypass for 0-latency +assign cq_rd8_pd = rd_skid8_0_vld ? rd_skid8_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_0_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_1_vld)) ) begin + rd_skid8_0 <= rd_take_n_dly[8] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd8_pvld && cq_rd8_prdy && rd_skid8_1_vld ) begin + rd_skid8_0 <= rd_skid8_1; + end +//synopsys translate_off + else if ( !((rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_0_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_1_vld))) && + !(cq_rd8_pvld && cq_rd8_prdy && rd_skid8_1_vld) ) begin + end else begin + rd_skid8_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_1_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_2_vld)) ) begin + rd_skid8_1 <= rd_bypassing8 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd8_pvld && cq_rd8_prdy && rd_skid8_2_vld ) begin + rd_skid8_1 <= rd_skid8_2; + end +//synopsys translate_off + else if ( !((rd_bypassing8 || rd_take_n_dly[8]) && (!rd_skid8_1_vld || (cq_rd8_pvld && cq_rd8_prdy && !rd_skid8_2_vld))) && + !(cq_rd8_pvld && cq_rd8_prdy && rd_skid8_2_vld) ) begin + end else begin + rd_skid8_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing8 || rd_take_n_dly[8]) && rd_skid8_0_vld && rd_skid8_1_vld && (rd_skid8_2_vld || !(cq_rd8_pvld && cq_rd8_prdy)) ) begin + rd_skid8_2 <= rd_bypassing8 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing8 || rd_take_n_dly[8]) && rd_skid8_0_vld && rd_skid8_1_vld && (rd_skid8_2_vld || !(cq_rd8_pvld && cq_rd8_prdy))) ) begin + end else begin + rd_skid8_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid8_0_vld <= 1'b0; + rd_skid8_1_vld <= 1'b0; + rd_skid8_2_vld <= 1'b0; + end else begin + rd_skid8_0_vld <= (cq_rd8_pvld && cq_rd8_prdy) ? (rd_skid8_1_vld || (rd_bypassing8 && rd_skid8_0_vld) || rd_take_n_dly[8]) : (rd_skid8_0_vld || rd_bypassing8 || rd_take_n_dly[8]); + rd_skid8_1_vld <= (cq_rd8_pvld && cq_rd8_prdy) ? (rd_skid8_2_vld || (rd_skid8_1_vld && (rd_bypassing8 || rd_take_n_dly[8]))) : (rd_skid8_1_vld || (rd_skid8_0_vld && (rd_bypassing8 || rd_take_n_dly[8]))); +//VCS coverage off + rd_skid8_2_vld <= (cq_rd8_pvld && cq_rd8_prdy) ? (rd_skid8_2_vld && (rd_bypassing8 || rd_take_n_dly[8])) : (rd_skid8_2_vld || (rd_skid8_1_vld && (rd_bypassing8 || rd_take_n_dly[8]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd8_credits; // unused credits +reg cq_rd8_credits_ne0; +wire [8:0] cq_rd8_credits_w_take_next = cq_rd8_credits + cq_rd_credit[8] - 1'b1; +wire [8:0] cq_rd8_credits_wo_take_next = cq_rd8_credits + cq_rd_credit[8]; +wire [8:0] cq_rd8_credits_next = rd_take8 ? cq_rd8_credits_w_take_next : cq_rd8_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[8] = (cq_rd8_prdy_d || !rd_skid8_0_vld || !rd_skid8_1_vld || (!rd_skid8_2_vld && !rd_take_n_dly[8])) && (cq_rd_credit[8] || cq_rd8_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing8 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd8) && cq_rd8_credits == 0 && !cq_rd_credit[8] && (!rd_take_n_dly[8] || rd_skid8_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing8 = rd_pre_bypassing8 && (!rd_skid8_2_vld || !rd_skid8_1_vld || !(!cq_rd8_prdy_d && rd_skid8_0_vld && rd_skid8_1_vld)) && !rd_take_n_dly[8]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd8_credits <= 9'd0; + cq_rd8_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[8] | rd_take8 ) begin + cq_rd8_credits <= cq_rd8_credits_next; + cq_rd8_credits_ne0 <= rd_take8 ? (cq_rd8_credits_w_take_next != 0) : (cq_rd8_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[8] | rd_take8) ) begin + end else begin + cq_rd8_credits <= {9{`x_or_0}}; + cq_rd8_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing9; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing9; // between cq_rd9_pvld and cq_rd9_prdy when doing full bypass +reg [6:0] rd_skid9_0; // head skid reg +reg [6:0] rd_skid9_1; // head+1 skid reg +reg [6:0] rd_skid9_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid9_0_vld; // head skid reg has valid data +reg rd_skid9_1_vld; // head+1 skid reg has valid data +reg rd_skid9_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd9_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd9_prdy_d <= 1'b1; + end else begin + cq_rd9_prdy_d <= cq_rd9_prdy; + end +end +assign cq_rd9_pvld = rd_skid9_0_vld || rd_pre_bypassing9; // full bypass for 0-latency +assign cq_rd9_pd = rd_skid9_0_vld ? rd_skid9_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_0_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_1_vld)) ) begin + rd_skid9_0 <= rd_take_n_dly[9] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd9_pvld && cq_rd9_prdy && rd_skid9_1_vld ) begin + rd_skid9_0 <= rd_skid9_1; + end +//synopsys translate_off + else if ( !((rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_0_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_1_vld))) && + !(cq_rd9_pvld && cq_rd9_prdy && rd_skid9_1_vld) ) begin + end else begin + rd_skid9_0 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_1_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_2_vld)) ) begin + rd_skid9_1 <= rd_bypassing9 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd9_pvld && cq_rd9_prdy && rd_skid9_2_vld ) begin + rd_skid9_1 <= rd_skid9_2; + end +//synopsys translate_off + else if ( !((rd_bypassing9 || rd_take_n_dly[9]) && (!rd_skid9_1_vld || (cq_rd9_pvld && cq_rd9_prdy && !rd_skid9_2_vld))) && + !(cq_rd9_pvld && cq_rd9_prdy && rd_skid9_2_vld) ) begin + end else begin + rd_skid9_1 <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing9 || rd_take_n_dly[9]) && rd_skid9_0_vld && rd_skid9_1_vld && (rd_skid9_2_vld || !(cq_rd9_pvld && cq_rd9_prdy)) ) begin + rd_skid9_2 <= rd_bypassing9 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing9 || rd_take_n_dly[9]) && rd_skid9_0_vld && rd_skid9_1_vld && (rd_skid9_2_vld || !(cq_rd9_pvld && cq_rd9_prdy))) ) begin + end else begin + rd_skid9_2 <= {7{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid9_0_vld <= 1'b0; + rd_skid9_1_vld <= 1'b0; + rd_skid9_2_vld <= 1'b0; + end else begin + rd_skid9_0_vld <= (cq_rd9_pvld && cq_rd9_prdy) ? (rd_skid9_1_vld || (rd_bypassing9 && rd_skid9_0_vld) || rd_take_n_dly[9]) : (rd_skid9_0_vld || rd_bypassing9 || rd_take_n_dly[9]); + rd_skid9_1_vld <= (cq_rd9_pvld && cq_rd9_prdy) ? (rd_skid9_2_vld || (rd_skid9_1_vld && (rd_bypassing9 || rd_take_n_dly[9]))) : (rd_skid9_1_vld || (rd_skid9_0_vld && (rd_bypassing9 || rd_take_n_dly[9]))); +//VCS coverage off + rd_skid9_2_vld <= (cq_rd9_pvld && cq_rd9_prdy) ? (rd_skid9_2_vld && (rd_bypassing9 || rd_take_n_dly[9])) : (rd_skid9_2_vld || (rd_skid9_1_vld && (rd_bypassing9 || rd_take_n_dly[9]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd9_credits; // unused credits +reg cq_rd9_credits_ne0; +wire [8:0] cq_rd9_credits_w_take_next = cq_rd9_credits + cq_rd_credit[9] - 1'b1; +wire [8:0] cq_rd9_credits_wo_take_next = cq_rd9_credits + cq_rd_credit[9]; +wire [8:0] cq_rd9_credits_next = rd_take9 ? cq_rd9_credits_w_take_next : cq_rd9_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[9] = (cq_rd9_prdy_d || !rd_skid9_0_vld || !rd_skid9_1_vld || (!rd_skid9_2_vld && !rd_take_n_dly[9])) && (cq_rd_credit[9] || cq_rd9_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing9 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 4'd9) && cq_rd9_credits == 0 && !cq_rd_credit[9] && (!rd_take_n_dly[9] || rd_skid9_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing9 = rd_pre_bypassing9 && (!rd_skid9_2_vld || !rd_skid9_1_vld || !(!cq_rd9_prdy_d && rd_skid9_0_vld && rd_skid9_1_vld)) && !rd_take_n_dly[9]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd9_credits <= 9'd0; + cq_rd9_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[9] | rd_take9 ) begin + cq_rd9_credits <= cq_rd9_credits_next; + cq_rd9_credits_ne0 <= rd_take9 ? (cq_rd9_credits_w_take_next != 0) : (cq_rd9_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[9] | rd_take9) ) begin + end else begin + cq_rd9_credits <= {9{`x_or_0}}; + cq_rd9_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +// rd_take round-robin arbiter (similar to arbgen output) +// +assign cq_rd_take = |cq_rd_take_elig; // any thread is eligible to take, so issue take +reg [3:0] cq_rd_take_thread_id_last; +wire [9:0] cq_rd_take_thread_id_is_1 = { + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 4'd0}; +wire [9:0] cq_rd_take_thread_id_is_2 = { + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd1, + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1]}; +wire [9:0] cq_rd_take_thread_id_is_3 = { + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd2, + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2]}; +wire [9:0] cq_rd_take_thread_id_is_4 = { + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd3, + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3]}; +wire [9:0] cq_rd_take_thread_id_is_5 = { + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd4, + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4], + cq_rd_take_elig[5] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4]}; +wire [9:0] cq_rd_take_thread_id_is_6 = { + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd5, + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5], + cq_rd_take_elig[6] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5]}; +wire [9:0] cq_rd_take_thread_id_is_7 = { + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8] && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd6, + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6], + cq_rd_take_elig[7] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6]}; +wire [9:0] cq_rd_take_thread_id_is_8 = { + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd8 && !cq_rd_take_elig[9] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd7, + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7], + cq_rd_take_elig[8] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7]}; +wire [9:0] cq_rd_take_thread_id_is_9 = { + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd9 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd8, + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd7 && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd6 && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd5 && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd4 && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8], + cq_rd_take_elig[9] && cq_rd_take_thread_id_last == 4'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[5] && !cq_rd_take_elig[6] && !cq_rd_take_elig[7] && !cq_rd_take_elig[8]}; +assign cq_rd_take_thread_id[0] = |{cq_rd_take_thread_id_is_1,cq_rd_take_thread_id_is_3,cq_rd_take_thread_id_is_5,cq_rd_take_thread_id_is_7,cq_rd_take_thread_id_is_9}; +assign cq_rd_take_thread_id[1] = |{cq_rd_take_thread_id_is_2,cq_rd_take_thread_id_is_3,cq_rd_take_thread_id_is_6,cq_rd_take_thread_id_is_7}; +assign cq_rd_take_thread_id[2] = |{cq_rd_take_thread_id_is_4,cq_rd_take_thread_id_is_5,cq_rd_take_thread_id_is_6,cq_rd_take_thread_id_is_7}; +assign cq_rd_take_thread_id[3] = |{cq_rd_take_thread_id_is_8,cq_rd_take_thread_id_is_9}; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_take_thread_id_last <= 4'd0; + end else begin + if ( cq_rd_take ) begin + cq_rd_take_thread_id_last <= cq_rd_take_thread_id; + end +//synopsys translate_off + else if ( !cq_rd_take ) begin + end else begin + cq_rd_take_thread_id_last <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +assign wr_bypassing = rd_bypassing0 || rd_bypassing1 || rd_bypassing2 || rd_bypassing3 || rd_bypassing4 || rd_bypassing5 || rd_bypassing6 || rd_bypassing7 || rd_bypassing8 || rd_bypassing9; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next) || rd_popping) || (rd_pushing || cq_rd_take || cq_rd_credit != 10'd0 || rd_take_dly)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +assign nvdla_core_clk_mgated_skid_enable = nvdla_core_clk_mgated_enable || ( cq_rd0_pvld && cq_rd0_prdy ) || rd_bypassing0 || ( cq_rd1_pvld && cq_rd1_prdy ) || rd_bypassing1 || ( cq_rd2_pvld && cq_rd2_prdy ) || rd_bypassing2 || ( cq_rd3_pvld && cq_rd3_prdy ) || rd_bypassing3 || ( cq_rd4_pvld && cq_rd4_prdy ) || rd_bypassing4 || ( cq_rd5_pvld && cq_rd5_prdy ) || rd_bypassing5 || ( cq_rd6_pvld && cq_rd6_prdy ) || rd_bypassing6 || ( cq_rd7_pvld && cq_rd7_prdy ) || rd_bypassing7 || ( cq_rd8_pvld && cq_rd8_prdy ) || rd_bypassing8 || ( cq_rd9_pvld && cq_rd9_prdy ) || rd_bypassing9 + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit : 9'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 9'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 9'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 9'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [8:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_cq_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cq_wr_pvld && !(!cq_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} ) + , .curr ( {23'd0, cq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check0 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd0 ), + .credit ( cq_rd_credit[0] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check1 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd1 ), + .credit ( cq_rd_credit[1] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check2 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd2 ), + .credit ( cq_rd_credit[2] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check3 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd3 ), + .credit ( cq_rd_credit[3] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check4 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd4 ), + .credit ( cq_rd_credit[4] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check5 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd5 ), + .credit ( cq_rd_credit[5] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check6 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd6 ), + .credit ( cq_rd_credit[6] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check7 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd7 ), + .credit ( cq_rd_credit[7] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check8 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd8 ), + .credit ( cq_rd_credit[8] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check9 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 4'd9 ), + .credit ( cq_rd_credit[9] ) + ); +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_READ_cq") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_READ_cq +// +// generate free list fifo for use from read side to write side +// diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v new file mode 100644 index 0000000..bfe6f47 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v @@ -0,0 +1,3629 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_eg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print(",cq_rd${i}_pd\n"); +//:print(",cq_rd${i}_pvld\n"); +//:print(",cq_rd${i}_prdy\n"); +//:print(",mcif2client${i}_rd_rsp_ready\n"); +//:print(",mcif2client${i}_rd_rsp_pd\n"); +//:print(",mcif2client${i}_rd_rsp_valid\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +,cq_rd0_pd +,cq_rd0_pvld +,cq_rd0_prdy +,mcif2client0_rd_rsp_ready +,mcif2client0_rd_rsp_pd +,mcif2client0_rd_rsp_valid +,cq_rd1_pd +,cq_rd1_pvld +,cq_rd1_prdy +,mcif2client1_rd_rsp_ready +,mcif2client1_rd_rsp_pd +,mcif2client1_rd_rsp_valid +,cq_rd2_pd +,cq_rd2_pvld +,cq_rd2_prdy +,mcif2client2_rd_rsp_ready +,mcif2client2_rd_rsp_pd +,mcif2client2_rd_rsp_valid +,cq_rd3_pd +,cq_rd3_pvld +,cq_rd3_prdy +,mcif2client3_rd_rsp_ready +,mcif2client3_rd_rsp_pd +,mcif2client3_rd_rsp_valid +,cq_rd4_pd +,cq_rd4_pvld +,cq_rd4_prdy +,mcif2client4_rd_rsp_ready +,mcif2client4_rd_rsp_pd +,mcif2client4_rd_rsp_valid +,cq_rd5_pd +,cq_rd5_pvld +,cq_rd5_prdy +,mcif2client5_rd_rsp_ready +,mcif2client5_rd_rsp_pd +,mcif2client5_rd_rsp_valid +,cq_rd6_pd +,cq_rd6_pvld +,cq_rd6_prdy +,mcif2client6_rd_rsp_ready +,mcif2client6_rd_rsp_pd +,mcif2client6_rd_rsp_valid + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,noc2mcif_axi_r_rdata //|< i + ,noc2mcif_axi_r_rid //|< i + ,noc2mcif_axi_r_rlast //|< i + ,noc2mcif_axi_r_rvalid //|< i + ,pwrbus_ram_pd //|< i + ,eg2ig_axi_vld //|> o + ,noc2mcif_axi_r_rready //|> o +); +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("output mcif2client${i}_rd_rsp_valid;\n"); +//:print("input mcif2client${i}_rd_rsp_ready;\n"); +//:print qq( +//:output [64 +1 -1:0] mcif2client${i}_rd_rsp_pd; +//:); +//:print("input cq_rd${i}_pvld;\n"); +//:print("output cq_rd${i}_prdy;\n"); +//:print("input [6:0] cq_rd${i}_pd;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +output mcif2client0_rd_rsp_valid; +input mcif2client0_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client0_rd_rsp_pd; +input cq_rd0_pvld; +output cq_rd0_prdy; +input [6:0] cq_rd0_pd; +output mcif2client1_rd_rsp_valid; +input mcif2client1_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client1_rd_rsp_pd; +input cq_rd1_pvld; +output cq_rd1_prdy; +input [6:0] cq_rd1_pd; +output mcif2client2_rd_rsp_valid; +input mcif2client2_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client2_rd_rsp_pd; +input cq_rd2_pvld; +output cq_rd2_prdy; +input [6:0] cq_rd2_pd; +output mcif2client3_rd_rsp_valid; +input mcif2client3_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client3_rd_rsp_pd; +input cq_rd3_pvld; +output cq_rd3_prdy; +input [6:0] cq_rd3_pd; +output mcif2client4_rd_rsp_valid; +input mcif2client4_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client4_rd_rsp_pd; +input cq_rd4_pvld; +output cq_rd4_prdy; +input [6:0] cq_rd4_pd; +output mcif2client5_rd_rsp_valid; +input mcif2client5_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client5_rd_rsp_pd; +input cq_rd5_pvld; +output cq_rd5_prdy; +input [6:0] cq_rd5_pd; +output mcif2client6_rd_rsp_valid; +input mcif2client6_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client6_rd_rsp_pd; +input cq_rd6_pvld; +output cq_rd6_prdy; +input [6:0] cq_rd6_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +input [31:0] pwrbus_ram_pd; +output eg2ig_axi_vld; +reg [1:0] arb_cnt; +reg [6:0] arb_cq_pd; +reg [64 -1:0] arb_data; +reg [1:0] arb_wen; +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("reg [1:0] ctt${i}_cnt;\n"); +//:print("reg [6:0] ctt${i}_cq_pd;\n"); +//:print("reg ctt${i}_vld;\n"); +//:print("wire ctt${i}_accept;\n"); +//:print("wire ctt${i}_last_beat;\n"); +//:print("wire ctt${i}_rdy;\n"); +//:print qq( +//:wire [64 -1:0] dma${i}_data; +//:); +//:print qq( +//:wire [64/2-1:0] dma${i}_data0; +//:); +//:print qq( +//:wire [64/2-1:0] dma${i}_data1; +//:); +//:print("wire dma${i}_is_last_odd;\n"); +//:print("wire dma${i}_last_odd;\n"); +//:print("wire [1:0] dma${i}_mask;\n"); +//:print qq( +//:wire [64/2-1:0] dma${i}_mdata0; +//:); +//:print qq( +//:wire [64/2-1:0] dma${i}_mdata1; +//:); +//:print qq( +//:wire [64 +1 -1:0] dma${i}_pd; +//:); +//:print("wire dma${i}_rdy;\n"); +//:print("wire dma${i}_vld;\n"); +//:print("wire mon_dma${i}_lodd;\n"); +//:print qq(wire [64/2:0] ro${i}_rd0_pd;\n); +//:print qq(wire [64/2:0] ro${i}_rd1_pd;\n); +//:print("wire ro${i}_rd0_prdy;\n"); +//:print("wire ro${i}_rd0_pvld;\n"); +//:print("wire ro${i}_rd1_prdy;\n"); +//:print("wire ro${i}_rd1_pvld;\n"); +//:print("wire ro${i}_wr_rdy;\n"); +//:print("wire ro${i}_wr0_prdy;\n"); +//:print("wire ro${i}_wr1_prdy;\n"); +//:print qq(wire [64 -1:0] rq${i}_rd_pd;\n); +//:print("wire rq${i}_rd_prdy;\n"); +//:print("wire rq${i}_rd_pvld;\n"); +//:print("wire src${i}_gnt;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [1:0] ctt0_cnt; +reg [6:0] ctt0_cq_pd; +reg ctt0_vld; +wire ctt0_accept; +wire ctt0_last_beat; +wire ctt0_rdy; + +wire [64 -1:0] dma0_data; + +wire [64/2-1:0] dma0_data0; + +wire [64/2-1:0] dma0_data1; +wire dma0_is_last_odd; +wire dma0_last_odd; +wire [1:0] dma0_mask; + +wire [64/2-1:0] dma0_mdata0; + +wire [64/2-1:0] dma0_mdata1; + +wire [64 +1 -1:0] dma0_pd; +wire dma0_rdy; +wire dma0_vld; +wire mon_dma0_lodd; +wire [64/2:0] ro0_rd0_pd; +wire [64/2:0] ro0_rd1_pd; +wire ro0_rd0_prdy; +wire ro0_rd0_pvld; +wire ro0_rd1_prdy; +wire ro0_rd1_pvld; +wire ro0_wr_rdy; +wire ro0_wr0_prdy; +wire ro0_wr1_prdy; +wire [64 -1:0] rq0_rd_pd; +wire rq0_rd_prdy; +wire rq0_rd_pvld; +wire src0_gnt; +reg [1:0] ctt1_cnt; +reg [6:0] ctt1_cq_pd; +reg ctt1_vld; +wire ctt1_accept; +wire ctt1_last_beat; +wire ctt1_rdy; + +wire [64 -1:0] dma1_data; + +wire [64/2-1:0] dma1_data0; + +wire [64/2-1:0] dma1_data1; +wire dma1_is_last_odd; +wire dma1_last_odd; +wire [1:0] dma1_mask; + +wire [64/2-1:0] dma1_mdata0; + +wire [64/2-1:0] dma1_mdata1; + +wire [64 +1 -1:0] dma1_pd; +wire dma1_rdy; +wire dma1_vld; +wire mon_dma1_lodd; +wire [64/2:0] ro1_rd0_pd; +wire [64/2:0] ro1_rd1_pd; +wire ro1_rd0_prdy; +wire ro1_rd0_pvld; +wire ro1_rd1_prdy; +wire ro1_rd1_pvld; +wire ro1_wr_rdy; +wire ro1_wr0_prdy; +wire ro1_wr1_prdy; +wire [64 -1:0] rq1_rd_pd; +wire rq1_rd_prdy; +wire rq1_rd_pvld; +wire src1_gnt; +reg [1:0] ctt2_cnt; +reg [6:0] ctt2_cq_pd; +reg ctt2_vld; +wire ctt2_accept; +wire ctt2_last_beat; +wire ctt2_rdy; + +wire [64 -1:0] dma2_data; + +wire [64/2-1:0] dma2_data0; + +wire [64/2-1:0] dma2_data1; +wire dma2_is_last_odd; +wire dma2_last_odd; +wire [1:0] dma2_mask; + +wire [64/2-1:0] dma2_mdata0; + +wire [64/2-1:0] dma2_mdata1; + +wire [64 +1 -1:0] dma2_pd; +wire dma2_rdy; +wire dma2_vld; +wire mon_dma2_lodd; +wire [64/2:0] ro2_rd0_pd; +wire [64/2:0] ro2_rd1_pd; +wire ro2_rd0_prdy; +wire ro2_rd0_pvld; +wire ro2_rd1_prdy; +wire ro2_rd1_pvld; +wire ro2_wr_rdy; +wire ro2_wr0_prdy; +wire ro2_wr1_prdy; +wire [64 -1:0] rq2_rd_pd; +wire rq2_rd_prdy; +wire rq2_rd_pvld; +wire src2_gnt; +reg [1:0] ctt3_cnt; +reg [6:0] ctt3_cq_pd; +reg ctt3_vld; +wire ctt3_accept; +wire ctt3_last_beat; +wire ctt3_rdy; + +wire [64 -1:0] dma3_data; + +wire [64/2-1:0] dma3_data0; + +wire [64/2-1:0] dma3_data1; +wire dma3_is_last_odd; +wire dma3_last_odd; +wire [1:0] dma3_mask; + +wire [64/2-1:0] dma3_mdata0; + +wire [64/2-1:0] dma3_mdata1; + +wire [64 +1 -1:0] dma3_pd; +wire dma3_rdy; +wire dma3_vld; +wire mon_dma3_lodd; +wire [64/2:0] ro3_rd0_pd; +wire [64/2:0] ro3_rd1_pd; +wire ro3_rd0_prdy; +wire ro3_rd0_pvld; +wire ro3_rd1_prdy; +wire ro3_rd1_pvld; +wire ro3_wr_rdy; +wire ro3_wr0_prdy; +wire ro3_wr1_prdy; +wire [64 -1:0] rq3_rd_pd; +wire rq3_rd_prdy; +wire rq3_rd_pvld; +wire src3_gnt; +reg [1:0] ctt4_cnt; +reg [6:0] ctt4_cq_pd; +reg ctt4_vld; +wire ctt4_accept; +wire ctt4_last_beat; +wire ctt4_rdy; + +wire [64 -1:0] dma4_data; + +wire [64/2-1:0] dma4_data0; + +wire [64/2-1:0] dma4_data1; +wire dma4_is_last_odd; +wire dma4_last_odd; +wire [1:0] dma4_mask; + +wire [64/2-1:0] dma4_mdata0; + +wire [64/2-1:0] dma4_mdata1; + +wire [64 +1 -1:0] dma4_pd; +wire dma4_rdy; +wire dma4_vld; +wire mon_dma4_lodd; +wire [64/2:0] ro4_rd0_pd; +wire [64/2:0] ro4_rd1_pd; +wire ro4_rd0_prdy; +wire ro4_rd0_pvld; +wire ro4_rd1_prdy; +wire ro4_rd1_pvld; +wire ro4_wr_rdy; +wire ro4_wr0_prdy; +wire ro4_wr1_prdy; +wire [64 -1:0] rq4_rd_pd; +wire rq4_rd_prdy; +wire rq4_rd_pvld; +wire src4_gnt; +reg [1:0] ctt5_cnt; +reg [6:0] ctt5_cq_pd; +reg ctt5_vld; +wire ctt5_accept; +wire ctt5_last_beat; +wire ctt5_rdy; + +wire [64 -1:0] dma5_data; + +wire [64/2-1:0] dma5_data0; + +wire [64/2-1:0] dma5_data1; +wire dma5_is_last_odd; +wire dma5_last_odd; +wire [1:0] dma5_mask; + +wire [64/2-1:0] dma5_mdata0; + +wire [64/2-1:0] dma5_mdata1; + +wire [64 +1 -1:0] dma5_pd; +wire dma5_rdy; +wire dma5_vld; +wire mon_dma5_lodd; +wire [64/2:0] ro5_rd0_pd; +wire [64/2:0] ro5_rd1_pd; +wire ro5_rd0_prdy; +wire ro5_rd0_pvld; +wire ro5_rd1_prdy; +wire ro5_rd1_pvld; +wire ro5_wr_rdy; +wire ro5_wr0_prdy; +wire ro5_wr1_prdy; +wire [64 -1:0] rq5_rd_pd; +wire rq5_rd_prdy; +wire rq5_rd_pvld; +wire src5_gnt; +reg [1:0] ctt6_cnt; +reg [6:0] ctt6_cq_pd; +reg ctt6_vld; +wire ctt6_accept; +wire ctt6_last_beat; +wire ctt6_rdy; + +wire [64 -1:0] dma6_data; + +wire [64/2-1:0] dma6_data0; + +wire [64/2-1:0] dma6_data1; +wire dma6_is_last_odd; +wire dma6_last_odd; +wire [1:0] dma6_mask; + +wire [64/2-1:0] dma6_mdata0; + +wire [64/2-1:0] dma6_mdata1; + +wire [64 +1 -1:0] dma6_pd; +wire dma6_rdy; +wire dma6_vld; +wire mon_dma6_lodd; +wire [64/2:0] ro6_rd0_pd; +wire [64/2:0] ro6_rd1_pd; +wire ro6_rd0_prdy; +wire ro6_rd0_pvld; +wire ro6_rd1_prdy; +wire ro6_rd1_pvld; +wire ro6_wr_rdy; +wire ro6_wr0_prdy; +wire ro6_wr1_prdy; +wire [64 -1:0] rq6_rd_pd; +wire rq6_rd_prdy; +wire rq6_rd_pvld; +wire src6_gnt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [3:0] ipipe_axi_axid; +wire [64 -1:0] ipipe_axi_data; +wire [64 +3:0] ipipe_axi_pd; +wire ipipe_axi_rdy; +wire ipipe_axi_vld; +wire last_odd; +wire [64 +3:0] noc2mcif_axi_r_pd; +wire [4:0] noc2mcif_axi_r_rid_NC; +wire noc2mcif_axi_r_rlast_NC; +wire arb_cq_fdrop; +wire arb_cq_ldrop; +wire [1:0] arb_cq_lens; +wire arb_cq_ltran; +wire arb_cq_odd; +wire arb_cq_swizzle; +wire [(64/2)-1:0] arb_data0; +wire [(64/2)-1:0] arb_data0_swizzled; +wire [(64/2)-1:0] arb_data1; +wire [(64/2)-1:0] arb_data1_swizzled; +wire arb_first_beat; +wire arb_last_beat; +wire [(64/2):0] arb_pd0; +wire [(64/2):0] arb_pd1; +wire arb_wen0_swizzled; +wire arb_wen1_swizzled; +//stepheng,remove +//// TIE-OFFs +//assign noc2mcif_axi_r_rresp_NC = noc2mcif_axi_r_rresp; +assign noc2mcif_axi_r_rlast_NC = noc2mcif_axi_r_rlast; +//assign noc2mcif_axi_r_ruser_NC = noc2mcif_axi_r_ruser; +assign noc2mcif_axi_r_rid_NC = noc2mcif_axi_r_rid[7:3]; +assign noc2mcif_axi_r_pd = {noc2mcif_axi_r_rid[3:0],noc2mcif_axi_r_rdata}; +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ipipe_axi_rdy (ipipe_axi_rdy) //|< w + ,.noc2mcif_axi_r_pd (noc2mcif_axi_r_pd[64 +3:0]) //|< w + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.ipipe_axi_pd (ipipe_axi_pd[64 +3:0]) //|> w + ,.ipipe_axi_vld (ipipe_axi_vld) //|> w + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ); +//my $dw = eval(64 +4); +//&eperl::pipe(" -is -wid $dw -do ipipe_axi_pd -vo ipipe_axi_vld -ri noc2mcif_axi_r_rready -vi noc2mcif_axi_r_rvalid -di noc2mcif_axi_r_pd -ro ipipe_axi_rdy"); +wire [64 -1:0] rq_wr_pd; +assign eg2ig_axi_vld = ipipe_axi_vld & ipipe_axi_rdy; +assign {ipipe_axi_axid,ipipe_axi_data} = ipipe_axi_pd; +assign rq_wr_pd = ipipe_axi_data; +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print qq(wire rq${i}_wr_pvld, rq${i}_wr_prdy;\n); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire rq0_wr_pvld, rq0_wr_prdy; +wire rq1_wr_pvld, rq1_wr_prdy; +wire rq2_wr_pvld, rq2_wr_prdy; +wire rq3_wr_pvld, rq3_wr_prdy; +wire rq4_wr_pvld, rq4_wr_prdy; +wire rq5_wr_pvld, rq5_wr_prdy; +wire rq6_wr_pvld, rq6_wr_prdy; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign ipipe_axi_rdy = 0 +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print ("| (rq${i}_wr_pvld & rq${i}_wr_prdy)\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +| (rq0_wr_pvld & rq0_wr_prdy) +| (rq1_wr_pvld & rq1_wr_prdy) +| (rq2_wr_pvld & rq2_wr_prdy) +| (rq3_wr_pvld & rq3_wr_prdy) +| (rq4_wr_pvld & rq4_wr_prdy) +| (rq5_wr_pvld & rq5_wr_prdy) +| (rq6_wr_pvld & rq6_wr_prdy) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +; +//:my $k = 7; +//:my $i; +//:my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//:my @client_id = (0,8,9,3,2,4,1,5,7,6,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:for($i=0;$i<$k;$i++) { +//:print("assign rq${i}_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == $remap_clientid[$i]);\n"); +//:print qq(wire [64 -1:0] rq${i}_wr_pd = rq_wr_pd;\n); +//:print("NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo${i} (\n"); +//:print(".nvdla_core_clk(nvdla_core_clk)\n"); +//:print(",.nvdla_core_rstn(nvdla_core_rstn)\n"); +//:print(",.rq_wr_prdy(rq${i}_wr_prdy)\n"); +//:print(",.rq_wr_pvld(rq${i}_wr_pvld)\n"); +//:print(",.rq_wr_pd(rq${i}_wr_pd)\n"); +//:print(",.rq_rd_prdy(rq${i}_rd_prdy)\n"); +//:print(",.rq_rd_pvld(rq${i}_rd_pvld)\n"); +//:print(",.rq_rd_pd(rq${i}_rd_pd)\n"); +//:print(",.pwrbus_ram_pd(pwrbus_ram_pd)\n"); +//:print(");\n"); +//:} +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("wire src${i}_req = rq${i}_rd_pvld && ctt${i}_vld && ro${i}_wr_rdy;\n"); +//:print("assign ctt${i}_rdy = src${i}_gnt;\n"); +//:print("assign rq${i}_rd_prdy = src${i}_gnt;\n"); +//:} +//:my $k = 7; +//:my $i; +//:for ($i=$k; $i<10;$i++) { +//:print qq( +//: wire src${i}_req = 1'b0; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign rq0_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 8); +wire [64 -1:0] rq0_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq0_wr_prdy) +,.rq_wr_pvld(rq0_wr_pvld) +,.rq_wr_pd(rq0_wr_pd) +,.rq_rd_prdy(rq0_rd_prdy) +,.rq_rd_pvld(rq0_rd_pvld) +,.rq_rd_pd(rq0_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign rq1_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 9); +wire [64 -1:0] rq1_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq1_wr_prdy) +,.rq_wr_pvld(rq1_wr_pvld) +,.rq_wr_pd(rq1_wr_pd) +,.rq_rd_prdy(rq1_rd_prdy) +,.rq_rd_pvld(rq1_rd_pvld) +,.rq_rd_pd(rq1_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign rq2_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 3); +wire [64 -1:0] rq2_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo2 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq2_wr_prdy) +,.rq_wr_pvld(rq2_wr_pvld) +,.rq_wr_pd(rq2_wr_pd) +,.rq_rd_prdy(rq2_rd_prdy) +,.rq_rd_pvld(rq2_rd_pvld) +,.rq_rd_pd(rq2_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign rq3_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 2); +wire [64 -1:0] rq3_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo3 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq3_wr_prdy) +,.rq_wr_pvld(rq3_wr_pvld) +,.rq_wr_pd(rq3_wr_pd) +,.rq_rd_prdy(rq3_rd_prdy) +,.rq_rd_pvld(rq3_rd_pvld) +,.rq_rd_pd(rq3_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign rq4_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 1); +wire [64 -1:0] rq4_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo4 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq4_wr_prdy) +,.rq_wr_pvld(rq4_wr_pvld) +,.rq_wr_pd(rq4_wr_pd) +,.rq_rd_prdy(rq4_rd_prdy) +,.rq_rd_pvld(rq4_rd_pvld) +,.rq_rd_pd(rq4_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign rq5_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 5); +wire [64 -1:0] rq5_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo5 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq5_wr_prdy) +,.rq_wr_pvld(rq5_wr_pvld) +,.rq_wr_pd(rq5_wr_pd) +,.rq_rd_prdy(rq5_rd_prdy) +,.rq_rd_pvld(rq5_rd_pvld) +,.rq_rd_pd(rq5_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign rq6_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == 6); +wire [64 -1:0] rq6_wr_pd = rq_wr_pd; +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo6 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rq_wr_prdy(rq6_wr_prdy) +,.rq_wr_pvld(rq6_wr_pvld) +,.rq_wr_pd(rq6_wr_pd) +,.rq_rd_prdy(rq6_rd_prdy) +,.rq_rd_pvld(rq6_rd_pvld) +,.rq_rd_pd(rq6_rd_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire src0_req = rq0_rd_pvld && ctt0_vld && ro0_wr_rdy; +assign ctt0_rdy = src0_gnt; +assign rq0_rd_prdy = src0_gnt; +wire src1_req = rq1_rd_pvld && ctt1_vld && ro1_wr_rdy; +assign ctt1_rdy = src1_gnt; +assign rq1_rd_prdy = src1_gnt; +wire src2_req = rq2_rd_pvld && ctt2_vld && ro2_wr_rdy; +assign ctt2_rdy = src2_gnt; +assign rq2_rd_prdy = src2_gnt; +wire src3_req = rq3_rd_pvld && ctt3_vld && ro3_wr_rdy; +assign ctt3_rdy = src3_gnt; +assign rq3_rd_prdy = src3_gnt; +wire src4_req = rq4_rd_pvld && ctt4_vld && ro4_wr_rdy; +assign ctt4_rdy = src4_gnt; +assign rq4_rd_prdy = src4_gnt; +wire src5_req = rq5_rd_pvld && ctt5_vld && ro5_wr_rdy; +assign ctt5_rdy = src5_gnt; +assign rq5_rd_prdy = src5_gnt; +wire src6_req = rq6_rd_pvld && ctt6_vld && ro6_wr_rdy; +assign ctt6_rdy = src6_gnt; +assign rq6_rd_prdy = src6_gnt; + +wire src7_req = 1'b0; + +wire src8_req = 1'b0; + +wire src9_req = 1'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +read_eg_arb u_read_eg_arb ( + .req0 (src0_req) //|< w + ,.req1 (src1_req) //|< w + ,.req2 (src2_req) //|< w + ,.req3 (src3_req) //|< w + ,.req4 (src4_req) //|< w + ,.req5 (src5_req) //|< w + ,.req6 (src6_req) //|< w + ,.req7 (src7_req) //|< w + ,.req8 (src8_req) //|< w + ,.req9 (src9_req) //|< w + ,.wt0 ({8{1'b1}}) //|< ? + ,.wt1 ({8{1'b1}}) //|< ? + ,.wt2 ({8{1'b1}}) //|< ? + ,.wt3 ({8{1'b1}}) //|< ? + ,.wt4 ({8{1'b1}}) //|< ? + ,.wt5 ({8{1'b1}}) //|< ? + ,.wt6 ({8{1'b1}}) //|< ? + ,.wt7 ({8{1'b1}}) //|< ? + ,.wt8 ({8{1'b1}}) //|< ? + ,.wt9 ({8{1'b1}}) //|< ? + ,.clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.gnt0 (src0_gnt) //|> w + ,.gnt1 (src1_gnt) //|> w + ,.gnt2 (src2_gnt) //|> w + ,.gnt3 (src3_gnt) //|> w + ,.gnt4 (src4_gnt) //|> w + ,.gnt5 (src5_gnt) //|> w + ,.gnt6 (src6_gnt) //|> w + ); +always @(src0_gnt or rq0_rd_pd +//:my $k = 7; +//:my $i; +//:for($i=1;$i<$k;$i++) { +//:print("or src${i}_gnt or rq${i}_rd_pd\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +or src1_gnt or rq1_rd_pd +or src2_gnt or rq2_rd_pd +or src3_gnt or rq3_rd_pd +or src4_gnt or rq4_rd_pd +or src5_gnt or rq5_rd_pd +or src6_gnt or rq6_rd_pd + +//| eperl: generated_end (DO NOT EDIT ABOVE) +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print("src${i}_gnt: arb_data = rq${i}_rd_pd;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +src0_gnt: arb_data = rq0_rd_pd; +src1_gnt: arb_data = rq1_rd_pd; +src2_gnt: arb_data = rq2_rd_pd; +src3_gnt: arb_data = rq3_rd_pd; +src4_gnt: arb_data = rq4_rd_pd; +src5_gnt: arb_data = rq5_rd_pd; +src6_gnt: arb_data = rq6_rd_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default : begin + arb_data[64 -1:0] = {64{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +always @(src0_gnt or ctt0_cq_pd +//:my $k = 7; +//:my $i; +//:for($i=1;$i<$k;$i++) { +//:print("or src${i}_gnt or ctt${i}_cq_pd\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +or src1_gnt or ctt1_cq_pd +or src2_gnt or ctt2_cq_pd +or src3_gnt or ctt3_cq_pd +or src4_gnt or ctt4_cq_pd +or src5_gnt or ctt5_cq_pd +or src6_gnt or ctt6_cq_pd + +//| eperl: generated_end (DO NOT EDIT ABOVE) +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print("src${i}_gnt: arb_cq_pd = ctt${i}_cq_pd;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +src0_gnt: arb_cq_pd = ctt0_cq_pd; +src1_gnt: arb_cq_pd = ctt1_cq_pd; +src2_gnt: arb_cq_pd = ctt2_cq_pd; +src3_gnt: arb_cq_pd = ctt3_cq_pd; +src4_gnt: arb_cq_pd = ctt4_cq_pd; +src5_gnt: arb_cq_pd = ctt5_cq_pd; +src6_gnt: arb_cq_pd = ctt6_cq_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default : begin + arb_cq_pd = {7{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +always @(src0_gnt or ctt0_cnt +//:my $k = 7; +//:my $i; +//:for($i=1;$i<$k;$i++) { +//:print("or src${i}_gnt or ctt${i}_cnt\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +or src1_gnt or ctt1_cnt +or src2_gnt or ctt2_cnt +or src3_gnt or ctt3_cnt +or src4_gnt or ctt4_cnt +or src5_gnt or ctt5_cnt +or src6_gnt or ctt6_cnt + +//| eperl: generated_end (DO NOT EDIT ABOVE) +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print("src${i}_gnt: arb_cnt = ctt${i}_cnt;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +src0_gnt: arb_cnt = ctt0_cnt; +src1_gnt: arb_cnt = ctt1_cnt; +src2_gnt: arb_cnt = ctt2_cnt; +src3_gnt: arb_cnt = ctt3_cnt; +src4_gnt: arb_cnt = ctt4_cnt; +src5_gnt: arb_cnt = ctt5_cnt; +src6_gnt: arb_cnt = ctt6_cnt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default : begin + arb_cnt = {2{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +// PKT_UNPACK_WIRE( nocif_read_ig2eg , arb_cq_ , arb_cq_pd ) +assign arb_cq_lens[1:0] = arb_cq_pd[1:0]; +assign arb_cq_swizzle = arb_cq_pd[2]; +assign arb_cq_odd = arb_cq_pd[3]; +assign arb_cq_ltran = arb_cq_pd[4]; +assign arb_cq_fdrop = arb_cq_pd[5]; +assign arb_cq_ldrop = arb_cq_pd[6]; +always @( + arb_first_beat + or arb_cq_fdrop + or arb_last_beat + or arb_cq_ldrop + ) begin + if (arb_first_beat && arb_cq_fdrop) begin + arb_wen = 2'b10; + end else if (arb_last_beat && arb_cq_ldrop) begin + arb_wen = 2'b01; + end else begin + arb_wen = 2'b11; + end +end +assign last_odd = arb_last_beat && arb_cq_ltran && arb_cq_odd; +assign arb_data0 = {arb_data[(64/2)-1:0]}; +assign arb_data1 = {arb_data[64 -1:(64/2)]}; +assign arb_data0_swizzled = arb_cq_swizzle ? arb_data1 : arb_data0; +assign arb_data1_swizzled = arb_cq_swizzle ? arb_data0 : arb_data1; +assign arb_pd0 = {last_odd,arb_data0_swizzled}; +assign arb_pd1 = {1'b0 ,arb_data1_swizzled}; +assign arb_wen0_swizzled = arb_cq_swizzle ? arb_wen[1] : arb_wen[0]; +assign arb_wen1_swizzled = arb_cq_swizzle ? arb_wen[0] : arb_wen[1]; +assign arb_last_beat = (arb_cnt==arb_cq_lens); +assign arb_first_beat = (arb_cnt==0); +//:my $k = 7; +//:my $i; +//:my $j=1; +//:for($i=0;$i<$k;$i++) { +//:print qq( +//:assign ro${i}_wr_rdy = ro${i}_wr0_prdy & ro${i}_wr1_prdy; +//:wire ro${i}_wr0_pvld = src${i}_gnt & arb_wen0_swizzled & ro${i}_wr1_prdy; +//:wire [64/2:0] ro${i}_wr0_pd = arb_pd0; +//:NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro${i}_fifo0 ( +//:.nvdla_core_clk(nvdla_core_clk) +//:,.nvdla_core_rstn(nvdla_core_rstn) +//:,.ro_wr_prdy(ro${i}_wr0_prdy) +//:,.ro_wr_pvld(ro${i}_wr0_pvld) +//:,.ro_wr_pd(ro${i}_wr0_pd) +//:,.ro_rd_prdy(ro${i}_rd0_prdy) +//:,.ro_rd_pvld(ro${i}_rd0_pvld) +//:,.ro_rd_pd(ro${i}_rd0_pd) +//:,.pwrbus_ram_pd(pwrbus_ram_pd) +//:); +//:); +//:print("wire ro${i}_wr1_pvld = src${i}_gnt & arb_wen1_swizzled & ro${i}_wr0_prdy;\n"); +//:print qq(wire [64/2:0] ro${i}_wr1_pd = arb_pd1;\n); +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro${i}_fifo1 ( +//:.nvdla_core_clk(nvdla_core_clk) +//:,.nvdla_core_rstn(nvdla_core_rstn) +//:,.ro_wr_prdy(ro${i}_wr1_prdy) +//:,.ro_wr_pvld(ro${i}_wr1_pvld) +//:,.ro_wr_pd(ro${i}_wr1_pd) +//:,.ro_rd_prdy(ro${i}_rd1_prdy) +//:,.ro_rd_pvld(ro${i}_rd1_pvld) +//:,.ro_rd_pd(ro${i}_rd1_pd) +//:,.pwrbus_ram_pd(pwrbus_ram_pd) +//:); +//:); +//:print("assign dma${i}_vld = ro${i}_rd0_pvld & (dma${i}_last_odd ? 1'b1 : ro${i}_rd1_pvld);\n"); +//:print("assign {dma${i}_last_odd,dma${i}_data0} = ro${i}_rd0_pd;\n"); +//:print("assign {mon_dma${i}_lodd,dma${i}_data1} = ro${i}_rd1_pd;\n"); +//:print("assign dma${i}_is_last_odd = ro${i}_rd0_pvld & dma${i}_last_odd;\n"); +//:print("assign dma${i}_mask = dma${i}_is_last_odd ? 2'b01: 2'b11;\n"); +//:print qq(assign dma${i}_mdata0 = {64/2{dma${i}_mask[0]}} & dma${i}_data0;\n); +//:print qq(assign dma${i}_mdata1 = {64/2{dma${i}_mask[1]}} & dma${i}_data1;\n); +//:if ($j > 1) { +//: print("assign dma${i}_pd = {dma${i}_mask,dma${i}_data};\n"); +//:} elsif ($j == 1) { +//: print("assign dma${i}_pd = {1'b1,dma${i}_data};\n"); +//:} +//:print("assign dma${i}_data = {dma${i}_mdata1,dma${i}_mdata0};\n"); +//:print("assign ro${i}_rd0_prdy = dma${i}_rdy & (dma${i}_is_last_odd ? 1'b1: ro${i}_rd1_pvld);\n"); +//:print("assign ro${i}_rd1_prdy = dma${i}_rdy & (dma${i}_is_last_odd ? 1'b1: ro${i}_rd0_pvld);\n"); +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp${i} ( +//:.nvdla_core_clk(nvdla_core_clk) +//:,.nvdla_core_rstn(nvdla_core_rstn) +//:,.rd_rsp_rdy(mcif2client${i}_rd_rsp_ready) +//:,.dma_pd(dma${i}_pd) +//:,.dma_vld(dma${i}_vld) +//:,.rd_rsp_pd(mcif2client${i}_rd_rsp_pd) +//:,.rd_rsp_valid(mcif2client${i}_rd_rsp_valid) +//:,.dma_rdy(dma${i}_rdy) +//:); +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign ro0_wr_rdy = ro0_wr0_prdy & ro0_wr1_prdy; +wire ro0_wr0_pvld = src0_gnt & arb_wen0_swizzled & ro0_wr1_prdy; +wire [64/2:0] ro0_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro0_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro0_wr0_prdy) +,.ro_wr_pvld(ro0_wr0_pvld) +,.ro_wr_pd(ro0_wr0_pd) +,.ro_rd_prdy(ro0_rd0_prdy) +,.ro_rd_pvld(ro0_rd0_pvld) +,.ro_rd_pd(ro0_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro0_wr1_pvld = src0_gnt & arb_wen1_swizzled & ro0_wr0_prdy; +wire [64/2:0] ro0_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro0_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro0_wr1_prdy) +,.ro_wr_pvld(ro0_wr1_pvld) +,.ro_wr_pd(ro0_wr1_pd) +,.ro_rd_prdy(ro0_rd1_prdy) +,.ro_rd_pvld(ro0_rd1_pvld) +,.ro_rd_pd(ro0_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma0_vld = ro0_rd0_pvld & (dma0_last_odd ? 1'b1 : ro0_rd1_pvld); +assign {dma0_last_odd,dma0_data0} = ro0_rd0_pd; +assign {mon_dma0_lodd,dma0_data1} = ro0_rd1_pd; +assign dma0_is_last_odd = ro0_rd0_pvld & dma0_last_odd; +assign dma0_mask = dma0_is_last_odd ? 2'b01: 2'b11; +assign dma0_mdata0 = {64/2{dma0_mask[0]}} & dma0_data0; +assign dma0_mdata1 = {64/2{dma0_mask[1]}} & dma0_data1; +assign dma0_pd = {1'b1,dma0_data}; +assign dma0_data = {dma0_mdata1,dma0_mdata0}; +assign ro0_rd0_prdy = dma0_rdy & (dma0_is_last_odd ? 1'b1: ro0_rd1_pvld); +assign ro0_rd1_prdy = dma0_rdy & (dma0_is_last_odd ? 1'b1: ro0_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client0_rd_rsp_ready) +,.dma_pd(dma0_pd) +,.dma_vld(dma0_vld) +,.rd_rsp_pd(mcif2client0_rd_rsp_pd) +,.rd_rsp_valid(mcif2client0_rd_rsp_valid) +,.dma_rdy(dma0_rdy) +); + +assign ro1_wr_rdy = ro1_wr0_prdy & ro1_wr1_prdy; +wire ro1_wr0_pvld = src1_gnt & arb_wen0_swizzled & ro1_wr1_prdy; +wire [64/2:0] ro1_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro1_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro1_wr0_prdy) +,.ro_wr_pvld(ro1_wr0_pvld) +,.ro_wr_pd(ro1_wr0_pd) +,.ro_rd_prdy(ro1_rd0_prdy) +,.ro_rd_pvld(ro1_rd0_pvld) +,.ro_rd_pd(ro1_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro1_wr1_pvld = src1_gnt & arb_wen1_swizzled & ro1_wr0_prdy; +wire [64/2:0] ro1_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro1_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro1_wr1_prdy) +,.ro_wr_pvld(ro1_wr1_pvld) +,.ro_wr_pd(ro1_wr1_pd) +,.ro_rd_prdy(ro1_rd1_prdy) +,.ro_rd_pvld(ro1_rd1_pvld) +,.ro_rd_pd(ro1_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma1_vld = ro1_rd0_pvld & (dma1_last_odd ? 1'b1 : ro1_rd1_pvld); +assign {dma1_last_odd,dma1_data0} = ro1_rd0_pd; +assign {mon_dma1_lodd,dma1_data1} = ro1_rd1_pd; +assign dma1_is_last_odd = ro1_rd0_pvld & dma1_last_odd; +assign dma1_mask = dma1_is_last_odd ? 2'b01: 2'b11; +assign dma1_mdata0 = {64/2{dma1_mask[0]}} & dma1_data0; +assign dma1_mdata1 = {64/2{dma1_mask[1]}} & dma1_data1; +assign dma1_pd = {1'b1,dma1_data}; +assign dma1_data = {dma1_mdata1,dma1_mdata0}; +assign ro1_rd0_prdy = dma1_rdy & (dma1_is_last_odd ? 1'b1: ro1_rd1_pvld); +assign ro1_rd1_prdy = dma1_rdy & (dma1_is_last_odd ? 1'b1: ro1_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client1_rd_rsp_ready) +,.dma_pd(dma1_pd) +,.dma_vld(dma1_vld) +,.rd_rsp_pd(mcif2client1_rd_rsp_pd) +,.rd_rsp_valid(mcif2client1_rd_rsp_valid) +,.dma_rdy(dma1_rdy) +); + +assign ro2_wr_rdy = ro2_wr0_prdy & ro2_wr1_prdy; +wire ro2_wr0_pvld = src2_gnt & arb_wen0_swizzled & ro2_wr1_prdy; +wire [64/2:0] ro2_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro2_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro2_wr0_prdy) +,.ro_wr_pvld(ro2_wr0_pvld) +,.ro_wr_pd(ro2_wr0_pd) +,.ro_rd_prdy(ro2_rd0_prdy) +,.ro_rd_pvld(ro2_rd0_pvld) +,.ro_rd_pd(ro2_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro2_wr1_pvld = src2_gnt & arb_wen1_swizzled & ro2_wr0_prdy; +wire [64/2:0] ro2_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro2_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro2_wr1_prdy) +,.ro_wr_pvld(ro2_wr1_pvld) +,.ro_wr_pd(ro2_wr1_pd) +,.ro_rd_prdy(ro2_rd1_prdy) +,.ro_rd_pvld(ro2_rd1_pvld) +,.ro_rd_pd(ro2_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma2_vld = ro2_rd0_pvld & (dma2_last_odd ? 1'b1 : ro2_rd1_pvld); +assign {dma2_last_odd,dma2_data0} = ro2_rd0_pd; +assign {mon_dma2_lodd,dma2_data1} = ro2_rd1_pd; +assign dma2_is_last_odd = ro2_rd0_pvld & dma2_last_odd; +assign dma2_mask = dma2_is_last_odd ? 2'b01: 2'b11; +assign dma2_mdata0 = {64/2{dma2_mask[0]}} & dma2_data0; +assign dma2_mdata1 = {64/2{dma2_mask[1]}} & dma2_data1; +assign dma2_pd = {1'b1,dma2_data}; +assign dma2_data = {dma2_mdata1,dma2_mdata0}; +assign ro2_rd0_prdy = dma2_rdy & (dma2_is_last_odd ? 1'b1: ro2_rd1_pvld); +assign ro2_rd1_prdy = dma2_rdy & (dma2_is_last_odd ? 1'b1: ro2_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp2 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client2_rd_rsp_ready) +,.dma_pd(dma2_pd) +,.dma_vld(dma2_vld) +,.rd_rsp_pd(mcif2client2_rd_rsp_pd) +,.rd_rsp_valid(mcif2client2_rd_rsp_valid) +,.dma_rdy(dma2_rdy) +); + +assign ro3_wr_rdy = ro3_wr0_prdy & ro3_wr1_prdy; +wire ro3_wr0_pvld = src3_gnt & arb_wen0_swizzled & ro3_wr1_prdy; +wire [64/2:0] ro3_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro3_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro3_wr0_prdy) +,.ro_wr_pvld(ro3_wr0_pvld) +,.ro_wr_pd(ro3_wr0_pd) +,.ro_rd_prdy(ro3_rd0_prdy) +,.ro_rd_pvld(ro3_rd0_pvld) +,.ro_rd_pd(ro3_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro3_wr1_pvld = src3_gnt & arb_wen1_swizzled & ro3_wr0_prdy; +wire [64/2:0] ro3_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro3_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro3_wr1_prdy) +,.ro_wr_pvld(ro3_wr1_pvld) +,.ro_wr_pd(ro3_wr1_pd) +,.ro_rd_prdy(ro3_rd1_prdy) +,.ro_rd_pvld(ro3_rd1_pvld) +,.ro_rd_pd(ro3_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma3_vld = ro3_rd0_pvld & (dma3_last_odd ? 1'b1 : ro3_rd1_pvld); +assign {dma3_last_odd,dma3_data0} = ro3_rd0_pd; +assign {mon_dma3_lodd,dma3_data1} = ro3_rd1_pd; +assign dma3_is_last_odd = ro3_rd0_pvld & dma3_last_odd; +assign dma3_mask = dma3_is_last_odd ? 2'b01: 2'b11; +assign dma3_mdata0 = {64/2{dma3_mask[0]}} & dma3_data0; +assign dma3_mdata1 = {64/2{dma3_mask[1]}} & dma3_data1; +assign dma3_pd = {1'b1,dma3_data}; +assign dma3_data = {dma3_mdata1,dma3_mdata0}; +assign ro3_rd0_prdy = dma3_rdy & (dma3_is_last_odd ? 1'b1: ro3_rd1_pvld); +assign ro3_rd1_prdy = dma3_rdy & (dma3_is_last_odd ? 1'b1: ro3_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp3 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client3_rd_rsp_ready) +,.dma_pd(dma3_pd) +,.dma_vld(dma3_vld) +,.rd_rsp_pd(mcif2client3_rd_rsp_pd) +,.rd_rsp_valid(mcif2client3_rd_rsp_valid) +,.dma_rdy(dma3_rdy) +); + +assign ro4_wr_rdy = ro4_wr0_prdy & ro4_wr1_prdy; +wire ro4_wr0_pvld = src4_gnt & arb_wen0_swizzled & ro4_wr1_prdy; +wire [64/2:0] ro4_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro4_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro4_wr0_prdy) +,.ro_wr_pvld(ro4_wr0_pvld) +,.ro_wr_pd(ro4_wr0_pd) +,.ro_rd_prdy(ro4_rd0_prdy) +,.ro_rd_pvld(ro4_rd0_pvld) +,.ro_rd_pd(ro4_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro4_wr1_pvld = src4_gnt & arb_wen1_swizzled & ro4_wr0_prdy; +wire [64/2:0] ro4_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro4_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro4_wr1_prdy) +,.ro_wr_pvld(ro4_wr1_pvld) +,.ro_wr_pd(ro4_wr1_pd) +,.ro_rd_prdy(ro4_rd1_prdy) +,.ro_rd_pvld(ro4_rd1_pvld) +,.ro_rd_pd(ro4_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma4_vld = ro4_rd0_pvld & (dma4_last_odd ? 1'b1 : ro4_rd1_pvld); +assign {dma4_last_odd,dma4_data0} = ro4_rd0_pd; +assign {mon_dma4_lodd,dma4_data1} = ro4_rd1_pd; +assign dma4_is_last_odd = ro4_rd0_pvld & dma4_last_odd; +assign dma4_mask = dma4_is_last_odd ? 2'b01: 2'b11; +assign dma4_mdata0 = {64/2{dma4_mask[0]}} & dma4_data0; +assign dma4_mdata1 = {64/2{dma4_mask[1]}} & dma4_data1; +assign dma4_pd = {1'b1,dma4_data}; +assign dma4_data = {dma4_mdata1,dma4_mdata0}; +assign ro4_rd0_prdy = dma4_rdy & (dma4_is_last_odd ? 1'b1: ro4_rd1_pvld); +assign ro4_rd1_prdy = dma4_rdy & (dma4_is_last_odd ? 1'b1: ro4_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp4 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client4_rd_rsp_ready) +,.dma_pd(dma4_pd) +,.dma_vld(dma4_vld) +,.rd_rsp_pd(mcif2client4_rd_rsp_pd) +,.rd_rsp_valid(mcif2client4_rd_rsp_valid) +,.dma_rdy(dma4_rdy) +); + +assign ro5_wr_rdy = ro5_wr0_prdy & ro5_wr1_prdy; +wire ro5_wr0_pvld = src5_gnt & arb_wen0_swizzled & ro5_wr1_prdy; +wire [64/2:0] ro5_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro5_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro5_wr0_prdy) +,.ro_wr_pvld(ro5_wr0_pvld) +,.ro_wr_pd(ro5_wr0_pd) +,.ro_rd_prdy(ro5_rd0_prdy) +,.ro_rd_pvld(ro5_rd0_pvld) +,.ro_rd_pd(ro5_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro5_wr1_pvld = src5_gnt & arb_wen1_swizzled & ro5_wr0_prdy; +wire [64/2:0] ro5_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro5_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro5_wr1_prdy) +,.ro_wr_pvld(ro5_wr1_pvld) +,.ro_wr_pd(ro5_wr1_pd) +,.ro_rd_prdy(ro5_rd1_prdy) +,.ro_rd_pvld(ro5_rd1_pvld) +,.ro_rd_pd(ro5_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma5_vld = ro5_rd0_pvld & (dma5_last_odd ? 1'b1 : ro5_rd1_pvld); +assign {dma5_last_odd,dma5_data0} = ro5_rd0_pd; +assign {mon_dma5_lodd,dma5_data1} = ro5_rd1_pd; +assign dma5_is_last_odd = ro5_rd0_pvld & dma5_last_odd; +assign dma5_mask = dma5_is_last_odd ? 2'b01: 2'b11; +assign dma5_mdata0 = {64/2{dma5_mask[0]}} & dma5_data0; +assign dma5_mdata1 = {64/2{dma5_mask[1]}} & dma5_data1; +assign dma5_pd = {1'b1,dma5_data}; +assign dma5_data = {dma5_mdata1,dma5_mdata0}; +assign ro5_rd0_prdy = dma5_rdy & (dma5_is_last_odd ? 1'b1: ro5_rd1_pvld); +assign ro5_rd1_prdy = dma5_rdy & (dma5_is_last_odd ? 1'b1: ro5_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp5 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client5_rd_rsp_ready) +,.dma_pd(dma5_pd) +,.dma_vld(dma5_vld) +,.rd_rsp_pd(mcif2client5_rd_rsp_pd) +,.rd_rsp_valid(mcif2client5_rd_rsp_valid) +,.dma_rdy(dma5_rdy) +); + +assign ro6_wr_rdy = ro6_wr0_prdy & ro6_wr1_prdy; +wire ro6_wr0_pvld = src6_gnt & arb_wen0_swizzled & ro6_wr1_prdy; +wire [64/2:0] ro6_wr0_pd = arb_pd0; +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro6_fifo0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro6_wr0_prdy) +,.ro_wr_pvld(ro6_wr0_pvld) +,.ro_wr_pd(ro6_wr0_pd) +,.ro_rd_prdy(ro6_rd0_prdy) +,.ro_rd_pvld(ro6_rd0_pvld) +,.ro_rd_pd(ro6_rd0_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +wire ro6_wr1_pvld = src6_gnt & arb_wen1_swizzled & ro6_wr0_prdy; +wire [64/2:0] ro6_wr1_pd = arb_pd1; + +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro6_fifo1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.ro_wr_prdy(ro6_wr1_prdy) +,.ro_wr_pvld(ro6_wr1_pvld) +,.ro_wr_pd(ro6_wr1_pd) +,.ro_rd_prdy(ro6_rd1_prdy) +,.ro_rd_pvld(ro6_rd1_pvld) +,.ro_rd_pd(ro6_rd1_pd) +,.pwrbus_ram_pd(pwrbus_ram_pd) +); +assign dma6_vld = ro6_rd0_pvld & (dma6_last_odd ? 1'b1 : ro6_rd1_pvld); +assign {dma6_last_odd,dma6_data0} = ro6_rd0_pd; +assign {mon_dma6_lodd,dma6_data1} = ro6_rd1_pd; +assign dma6_is_last_odd = ro6_rd0_pvld & dma6_last_odd; +assign dma6_mask = dma6_is_last_odd ? 2'b01: 2'b11; +assign dma6_mdata0 = {64/2{dma6_mask[0]}} & dma6_data0; +assign dma6_mdata1 = {64/2{dma6_mask[1]}} & dma6_data1; +assign dma6_pd = {1'b1,dma6_data}; +assign dma6_data = {dma6_mdata1,dma6_mdata0}; +assign ro6_rd0_prdy = dma6_rdy & (dma6_is_last_odd ? 1'b1: ro6_rd1_pvld); +assign ro6_rd1_prdy = dma6_rdy & (dma6_is_last_odd ? 1'b1: ro6_rd0_pvld); + +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp6 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.rd_rsp_rdy(mcif2client6_rd_rsp_ready) +,.dma_pd(dma6_pd) +,.dma_vld(dma6_vld) +,.rd_rsp_pd(mcif2client6_rd_rsp_pd) +,.rd_rsp_valid(mcif2client6_rd_rsp_valid) +,.dma_rdy(dma6_rdy) +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//my $dw = eval(64 +2); +//&eperl::pipe("-is -wid $dw -vo mcif2client${i}_rd_rsp_valid -do mcif2client${i}_rd_rsp_pd -ro dma${i}_rdy -vi dma${i}_vld -di dma${i}_pd -ri mcif2client${i}_rd_rsp_ready"); +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("assign ctt${i}_last_beat = src${i}_gnt & arb_last_beat;\n"); +//:print("assign cq_rd${i}_prdy = (ctt${i}_rdy & ctt${i}_last_beat) || !ctt${i}_vld;\n"); +//:print("always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin\n"); +//:print(" if (!nvdla_core_rstn) begin\n"); +//:print(" ctt${i}_vld <= 1'b0;\n"); +//:print(" end else begin\n"); +//:print(" if ((cq_rd${i}_prdy) == 1'b1) begin\n"); +//:print(" ctt${i}_vld <= cq_rd${i}_pvld;\n"); +//:print(" end\n"); +//:print(" end\n"); +//:print("end\n"); +//:print("always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin\n"); +//:print(" if (!nvdla_core_rstn) begin\n"); +//:print(" ctt${i}_cnt <= {2{1'b0}};\n"); +//:print(" end else begin\n"); +//:print(" if (cq_rd${i}_pvld && cq_rd${i}_prdy) begin \n"); +//:print(" ctt${i}_cnt <= 0;\n"); +//:print(" end else if (ctt${i}_accept) begin\n"); +//:print(" ctt${i}_cnt <= ctt${i}_cnt + 1;\n"); +//:print(" end\n"); +//:print(" end\n"); +//:print("end\n"); +//:print("assign ctt${i}_accept = ctt${i}_vld & ctt${i}_rdy;\n"); +//:print("always @(posedge nvdla_core_clk) begin\n"); +//:print(" if (cq_rd${i}_pvld && cq_rd${i}_prdy) begin\n"); +//:print(" ctt${i}_cq_pd <= cq_rd${i}_pd;\n"); +//:print(" end\n"); +//:print("end\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign ctt0_last_beat = src0_gnt & arb_last_beat; +assign cq_rd0_prdy = (ctt0_rdy & ctt0_last_beat) || !ctt0_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt0_vld <= 1'b0; + end else begin + if ((cq_rd0_prdy) == 1'b1) begin + ctt0_vld <= cq_rd0_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt0_cnt <= {2{1'b0}}; + end else begin + if (cq_rd0_pvld && cq_rd0_prdy) begin + ctt0_cnt <= 0; + end else if (ctt0_accept) begin + ctt0_cnt <= ctt0_cnt + 1; + end + end +end +assign ctt0_accept = ctt0_vld & ctt0_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd0_pvld && cq_rd0_prdy) begin + ctt0_cq_pd <= cq_rd0_pd; + end +end +assign ctt1_last_beat = src1_gnt & arb_last_beat; +assign cq_rd1_prdy = (ctt1_rdy & ctt1_last_beat) || !ctt1_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt1_vld <= 1'b0; + end else begin + if ((cq_rd1_prdy) == 1'b1) begin + ctt1_vld <= cq_rd1_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt1_cnt <= {2{1'b0}}; + end else begin + if (cq_rd1_pvld && cq_rd1_prdy) begin + ctt1_cnt <= 0; + end else if (ctt1_accept) begin + ctt1_cnt <= ctt1_cnt + 1; + end + end +end +assign ctt1_accept = ctt1_vld & ctt1_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd1_pvld && cq_rd1_prdy) begin + ctt1_cq_pd <= cq_rd1_pd; + end +end +assign ctt2_last_beat = src2_gnt & arb_last_beat; +assign cq_rd2_prdy = (ctt2_rdy & ctt2_last_beat) || !ctt2_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt2_vld <= 1'b0; + end else begin + if ((cq_rd2_prdy) == 1'b1) begin + ctt2_vld <= cq_rd2_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt2_cnt <= {2{1'b0}}; + end else begin + if (cq_rd2_pvld && cq_rd2_prdy) begin + ctt2_cnt <= 0; + end else if (ctt2_accept) begin + ctt2_cnt <= ctt2_cnt + 1; + end + end +end +assign ctt2_accept = ctt2_vld & ctt2_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd2_pvld && cq_rd2_prdy) begin + ctt2_cq_pd <= cq_rd2_pd; + end +end +assign ctt3_last_beat = src3_gnt & arb_last_beat; +assign cq_rd3_prdy = (ctt3_rdy & ctt3_last_beat) || !ctt3_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt3_vld <= 1'b0; + end else begin + if ((cq_rd3_prdy) == 1'b1) begin + ctt3_vld <= cq_rd3_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt3_cnt <= {2{1'b0}}; + end else begin + if (cq_rd3_pvld && cq_rd3_prdy) begin + ctt3_cnt <= 0; + end else if (ctt3_accept) begin + ctt3_cnt <= ctt3_cnt + 1; + end + end +end +assign ctt3_accept = ctt3_vld & ctt3_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd3_pvld && cq_rd3_prdy) begin + ctt3_cq_pd <= cq_rd3_pd; + end +end +assign ctt4_last_beat = src4_gnt & arb_last_beat; +assign cq_rd4_prdy = (ctt4_rdy & ctt4_last_beat) || !ctt4_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt4_vld <= 1'b0; + end else begin + if ((cq_rd4_prdy) == 1'b1) begin + ctt4_vld <= cq_rd4_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt4_cnt <= {2{1'b0}}; + end else begin + if (cq_rd4_pvld && cq_rd4_prdy) begin + ctt4_cnt <= 0; + end else if (ctt4_accept) begin + ctt4_cnt <= ctt4_cnt + 1; + end + end +end +assign ctt4_accept = ctt4_vld & ctt4_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd4_pvld && cq_rd4_prdy) begin + ctt4_cq_pd <= cq_rd4_pd; + end +end +assign ctt5_last_beat = src5_gnt & arb_last_beat; +assign cq_rd5_prdy = (ctt5_rdy & ctt5_last_beat) || !ctt5_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt5_vld <= 1'b0; + end else begin + if ((cq_rd5_prdy) == 1'b1) begin + ctt5_vld <= cq_rd5_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt5_cnt <= {2{1'b0}}; + end else begin + if (cq_rd5_pvld && cq_rd5_prdy) begin + ctt5_cnt <= 0; + end else if (ctt5_accept) begin + ctt5_cnt <= ctt5_cnt + 1; + end + end +end +assign ctt5_accept = ctt5_vld & ctt5_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd5_pvld && cq_rd5_prdy) begin + ctt5_cq_pd <= cq_rd5_pd; + end +end +assign ctt6_last_beat = src6_gnt & arb_last_beat; +assign cq_rd6_prdy = (ctt6_rdy & ctt6_last_beat) || !ctt6_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt6_vld <= 1'b0; + end else begin + if ((cq_rd6_prdy) == 1'b1) begin + ctt6_vld <= cq_rd6_pvld; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ctt6_cnt <= {2{1'b0}}; + end else begin + if (cq_rd6_pvld && cq_rd6_prdy) begin + ctt6_cnt <= 0; + end else if (ctt6_accept) begin + ctt6_cnt <= ctt6_cnt + 1; + end + end +end +assign ctt6_accept = ctt6_vld & ctt6_rdy; +always @(posedge nvdla_core_clk) begin + if (cq_rd6_pvld && cq_rd6_prdy) begin + ctt6_cq_pd <= cq_rd6_pd; + end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule +module NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,ipipe_axi_rdy + ,noc2mcif_axi_r_pd + ,noc2mcif_axi_r_rvalid + ,ipipe_axi_pd + ,ipipe_axi_vld + ,noc2mcif_axi_r_rready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input ipipe_axi_rdy; +input [64 +3:0] noc2mcif_axi_r_pd; +input noc2mcif_axi_r_rvalid; +output [64 +3:0] ipipe_axi_pd; +output ipipe_axi_vld; +output noc2mcif_axi_r_rready; +reg [64 +3:0] ipipe_axi_pd; +reg ipipe_axi_vld; +reg noc2mcif_axi_r_rready; +reg [64 +3:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [64 +3:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [64 +3:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? noc2mcif_axi_r_rvalid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && noc2mcif_axi_r_rvalid)? noc2mcif_axi_r_pd[64 +3:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + noc2mcif_axi_r_rready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or ipipe_axi_rdy + or p1_pipe_skid_data + ) begin + ipipe_axi_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = ipipe_axi_rdy; + ipipe_axi_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (ipipe_axi_vld^ipipe_axi_rdy^noc2mcif_axi_r_rvalid^noc2mcif_axi_r_rready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (noc2mcif_axi_r_rvalid && !noc2mcif_axi_r_rready), (noc2mcif_axi_r_rvalid), (noc2mcif_axi_r_rready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule +module NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,rd_rsp_rdy + ,dma_pd + ,dma_vld + ,rd_rsp_pd + ,rd_rsp_valid + ,dma_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input rd_rsp_rdy; +input [64 +1 -1:0] dma_pd; +input dma_vld; +output [64 +1 -1:0] rd_rsp_pd; +output rd_rsp_valid; +output dma_rdy; +reg [64 +1 -1:0] rd_rsp_pd; +reg rd_rsp_valid; +reg dma_rdy; +reg [64 +1 -1:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [64 +1 -1:0] p2_skid_data; +reg [64 +1 -1:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + dma_vld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = dma_vld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + dma_rdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + dma_rdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? dma_pd[64 +1 -1:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or dma_vld + or p2_skid_valid + or dma_pd + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? dma_vld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? dma_pd[64 +1 -1:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or rd_rsp_rdy + or p2_pipe_data + ) begin + rd_rsp_valid = p2_pipe_valid; + p2_pipe_ready = rd_rsp_rdy; + rd_rsp_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rd_rsp_valid^rd_rsp_rdy^dma_vld^dma_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (dma_vld && !dma_rdy), (dma_vld), (dma_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus rq_wr -rd_pipebus rq_rd -d 4 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , rq_wr_prdy + , rq_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , rq_wr_pause +`endif + , rq_wr_pd + , rq_rd_prdy + , rq_rd_pvld + , rq_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output rq_wr_prdy; +input rq_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input rq_wr_pause; +`endif +input [64 -1:0] rq_wr_pd; +input rq_rd_prdy; +output rq_rd_pvld; +output [64 -1:0] rq_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg rq_wr_busy_int; // copy for internal use +assign rq_wr_prdy = !rq_wr_busy_int; +assign wr_reserving = rq_wr_pvld && !rq_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] rq_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? rq_wr_count : (rq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (rq_wr_count + 1'd1) : rq_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire rq_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check rq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || rq_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire rq_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check rq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_wr_busy_int <= 1'b0; + rq_wr_count <= 3'd0; + end else begin + rq_wr_busy_int <= rq_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + rq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + rq_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as rq_wr_pvld +// +// RAM +// +reg [1:0] rq_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + rq_wr_adr <= rq_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] rq_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [64 -1:0] rq_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( rq_wr_pd ) + , .we ( ram_we ) + , .wa ( rq_wr_adr ) + , .ra ( rq_rd_adr ) + , .dout ( rq_rd_pd ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = rq_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rq_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rq_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg rq_rd_pvld; // data out of fifo is valid +reg rq_rd_pvld_int; // internal copy of rq_rd_pvld +assign rd_popping = rq_rd_pvld_int && rq_rd_prdy; +reg [2:0] rq_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? rq_rd_count : + (rq_rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (rq_rd_count + 1'd1) : + rq_rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +wire rd_count_next_rd_popping_not_0 = rd_count_next_rd_popping != 0; +wire rd_count_next_no_rd_popping_not_0 = rd_count_next_no_rd_popping != 0; +wire rd_count_next_not_0 = rd_popping ? rd_count_next_rd_popping_not_0 : + rd_count_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_rd_count <= 3'd0; + rq_rd_pvld <= 1'b0; + rq_rd_pvld_int <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rq_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rq_rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rq_rd_pvld <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rq_rd_pvld <= `x_or_0; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rq_rd_pvld_int <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rq_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (rq_wr_pvld && !rq_wr_busy_int) || (rq_wr_busy_int != rq_wr_busy_next)) || (rd_pushing || rd_popping || (rq_rd_pvld && rq_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( rq_wr_pvld && !(!rq_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, rq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64 -1:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [64 -1:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [64 -1:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [64 -1:0] ram_ff0; +reg [64 -1:0] ram_ff1; +reg [64 -1:0] ram_ff2; +reg [64 -1:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [64 -1:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {64{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [64 -1:0] Di0; +input [1:0] Ra0; +output [64 -1:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = NVDLA_PRIMARY_MEMIF_WIDTH'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [64 -1:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [64 -1:0] Q0 = mem[0]; +wire [64 -1:0] Q1 = mem[1]; +wire [64 -1:0] Q2 = mem[2]; +wire [64 -1:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xPRIMARY_MEMIF_WIDTH] } +endmodule // vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +//vmw: Memory vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +//vmw: Address-size 2 +//vmw: Data-size 64 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[64 -1:0] data0[PRIMARY_MEMIF_WIDTH-1:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[64 -1:0] data1[PRIMARY_MEMIF_WIDTH-1:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -d 4 -ram_bypass -rd_reg -rd_busy_reg -w 257 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , ro_wr_pause +`endif + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input ro_wr_pause; +`endif +input [64/2:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [64/2:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] ro_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || ro_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 3'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [1:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [64/2:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 3'd4 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg ro_rd_prdy_d; // ro_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_prdy_d <= 1'b1; + end else begin + ro_rd_prdy_d <= ro_rd_prdy; + end +end +wire ro_rd_prdy_d_o; // combinatorial rd_busy +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int_o; // internal copy of ro_rd_pvld_o +wire ro_rd_pvld_o = ro_rd_pvld_int_o; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int_o && !ro_rd_prdy_d_o); +reg [2:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SKID for -rd_busy_reg +// +reg [64/2:0] ro_rd_pd_o; // output data register +wire rd_req_next_o = (ro_rd_pvld_p || (ro_rd_pvld_int_o && !ro_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int_o <= 1'b0; + end else begin + ro_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (ro_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + ro_rd_pd_o <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((ro_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + ro_rd_pd_o <= {257{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg [64/2:0] ro_rd_pd; // output data register +reg ro_rd_pvld_int_d; // so we can bubble-collapse ro_rd_prdy_d +assign ro_rd_prdy_d_o = !((ro_rd_pvld_o && ro_rd_pvld_int_d && !ro_rd_prdy_d ) ); +wire rd_req_next = (!ro_rd_prdy_d_o ? ro_rd_pvld_o : ro_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + ro_rd_pvld_int_d <= 1'b0; + end else begin + if ( !ro_rd_pvld_int || ro_rd_prdy ) begin + ro_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!ro_rd_pvld_int || ro_rd_prdy) ) begin + end else begin + ro_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + ro_rd_pvld_int_d <= ro_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!ro_rd_pvld_int || ro_rd_prdy ) ) begin + case (!ro_rd_prdy_d_o) + 1'b0: ro_rd_pd <= ro_rd_pd_p; + 1'b1: ro_rd_pd <= ro_rd_pd_o; +//VCS coverage off + default: ro_rd_pd <= {257{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!ro_rd_pvld_int || ro_rd_prdy)) ) begin + end else begin + ro_rd_pd <= {257{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy_d) || (ro_rd_pvld_int_o && ro_rd_prdy_d_o)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( ro_wr_pvld && !(!ro_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64/2:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [64/2:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [64/2:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [64/2:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [64/2:0] ram_ff0; +reg [64/2:0] ram_ff1; +reg [64/2:0] ram_ff2; +reg [64/2:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [64/2:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {257{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [64/2:0] Di0; +input [1:0] Ra0; +output [64/2:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 257'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [64/2:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [64/2:0] Q0 = mem[0]; +wire [64/2:0] Q1 = mem[1]; +wire [64/2:0] Q2 = mem[2]; +wire [64/2:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257] } +endmodule // vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +//vmw: Memory vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +//vmw: Address-size 2 +//vmw: Data-size 257 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[64/2:0] +//data0[64/2:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[64/2:0] +//data1[64/2:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v.vcp new file mode 100644 index 0000000..cc3dd59 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v.vcp @@ -0,0 +1,2513 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_eg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print(",cq_rd${i}_pd\n"); +//:print(",cq_rd${i}_pvld\n"); +//:print(",cq_rd${i}_prdy\n"); +//:print(",mcif2client${i}_rd_rsp_ready\n"); +//:print(",mcif2client${i}_rd_rsp_pd\n"); +//:print(",mcif2client${i}_rd_rsp_valid\n"); +//:} + ,noc2mcif_axi_r_rdata //|< i + ,noc2mcif_axi_r_rid //|< i + ,noc2mcif_axi_r_rlast //|< i + ,noc2mcif_axi_r_rvalid //|< i + ,pwrbus_ram_pd //|< i + ,eg2ig_axi_vld //|> o + ,noc2mcif_axi_r_rready //|> o +); +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("output mcif2client${i}_rd_rsp_valid;\n"); +//:print("input mcif2client${i}_rd_rsp_ready;\n"); +//:print qq( +//:output [64 +1 -1:0] mcif2client${i}_rd_rsp_pd; +//:); +//:print("input cq_rd${i}_pvld;\n"); +//:print("output cq_rd${i}_prdy;\n"); +//:print("input [6:0] cq_rd${i}_pd;\n"); +//:} +input nvdla_core_clk; +input nvdla_core_rstn; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +input [31:0] pwrbus_ram_pd; +output eg2ig_axi_vld; +reg [1:0] arb_cnt; +reg [6:0] arb_cq_pd; +reg [64 -1:0] arb_data; +reg [1:0] arb_wen; +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("reg [1:0] ctt${i}_cnt;\n"); +//:print("reg [6:0] ctt${i}_cq_pd;\n"); +//:print("reg ctt${i}_vld;\n"); +//:print("wire ctt${i}_accept;\n"); +//:print("wire ctt${i}_last_beat;\n"); +//:print("wire ctt${i}_rdy;\n"); +//:print qq( +//:wire [64 -1:0] dma${i}_data; +//:); +//:print qq( +//:wire [64/2-1:0] dma${i}_data0; +//:); +//:print qq( +//:wire [64/2-1:0] dma${i}_data1; +//:); +//:print("wire dma${i}_is_last_odd;\n"); +//:print("wire dma${i}_last_odd;\n"); +//:print("wire [1:0] dma${i}_mask;\n"); +//:print qq( +//:wire [64/2-1:0] dma${i}_mdata0; +//:); +//:print qq( +//:wire [64/2-1:0] dma${i}_mdata1; +//:); +//:print qq( +//:wire [64 +1 -1:0] dma${i}_pd; +//:); +//:print("wire dma${i}_rdy;\n"); +//:print("wire dma${i}_vld;\n"); +//:print("wire mon_dma${i}_lodd;\n"); +//:print qq(wire [64/2:0] ro${i}_rd0_pd;\n); +//:print qq(wire [64/2:0] ro${i}_rd1_pd;\n); +//:print("wire ro${i}_rd0_prdy;\n"); +//:print("wire ro${i}_rd0_pvld;\n"); +//:print("wire ro${i}_rd1_prdy;\n"); +//:print("wire ro${i}_rd1_pvld;\n"); +//:print("wire ro${i}_wr_rdy;\n"); +//:print("wire ro${i}_wr0_prdy;\n"); +//:print("wire ro${i}_wr1_prdy;\n"); +//:print qq(wire [64 -1:0] rq${i}_rd_pd;\n); +//:print("wire rq${i}_rd_prdy;\n"); +//:print("wire rq${i}_rd_pvld;\n"); +//:print("wire src${i}_gnt;\n"); +//:} +wire [3:0] ipipe_axi_axid; +wire [64 -1:0] ipipe_axi_data; +wire [64 +3:0] ipipe_axi_pd; +wire ipipe_axi_rdy; +wire ipipe_axi_vld; +wire last_odd; +wire [64 +3:0] noc2mcif_axi_r_pd; +wire [4:0] noc2mcif_axi_r_rid_NC; +wire noc2mcif_axi_r_rlast_NC; +wire arb_cq_fdrop; +wire arb_cq_ldrop; +wire [1:0] arb_cq_lens; +wire arb_cq_ltran; +wire arb_cq_odd; +wire arb_cq_swizzle; +wire [(64/2)-1:0] arb_data0; +wire [(64/2)-1:0] arb_data0_swizzled; +wire [(64/2)-1:0] arb_data1; +wire [(64/2)-1:0] arb_data1_swizzled; +wire arb_first_beat; +wire arb_last_beat; +wire [(64/2):0] arb_pd0; +wire [(64/2):0] arb_pd1; +wire arb_wen0_swizzled; +wire arb_wen1_swizzled; +//stepheng,remove +//// TIE-OFFs +//assign noc2mcif_axi_r_rresp_NC = noc2mcif_axi_r_rresp; +assign noc2mcif_axi_r_rlast_NC = noc2mcif_axi_r_rlast; +//assign noc2mcif_axi_r_ruser_NC = noc2mcif_axi_r_ruser; +assign noc2mcif_axi_r_rid_NC = noc2mcif_axi_r_rid[7:3]; +assign noc2mcif_axi_r_pd = {noc2mcif_axi_r_rid[3:0],noc2mcif_axi_r_rdata}; +NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ipipe_axi_rdy (ipipe_axi_rdy) //|< w + ,.noc2mcif_axi_r_pd (noc2mcif_axi_r_pd[64 +3:0]) //|< w + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.ipipe_axi_pd (ipipe_axi_pd[64 +3:0]) //|> w + ,.ipipe_axi_vld (ipipe_axi_vld) //|> w + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ); +//my $dw = eval(64 +4); +//&eperl::pipe(" -is -wid $dw -do ipipe_axi_pd -vo ipipe_axi_vld -ri noc2mcif_axi_r_rready -vi noc2mcif_axi_r_rvalid -di noc2mcif_axi_r_pd -ro ipipe_axi_rdy"); +wire [64 -1:0] rq_wr_pd; +assign eg2ig_axi_vld = ipipe_axi_vld & ipipe_axi_rdy; +assign {ipipe_axi_axid,ipipe_axi_data} = ipipe_axi_pd; +assign rq_wr_pd = ipipe_axi_data; +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print qq(wire rq${i}_wr_pvld, rq${i}_wr_prdy;\n); +//:} +assign ipipe_axi_rdy = 0 +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print ("| (rq${i}_wr_pvld & rq${i}_wr_prdy)\n"); +//:} +; +//:my $k = 7; +//:my $i; +//:my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//:my @client_id = (0,8,9,3,2,4,1,5,7,6,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:for($i=0;$i<$k;$i++) { +//:print("assign rq${i}_wr_pvld = ipipe_axi_vld & (ipipe_axi_axid == $remap_clientid[$i]);\n"); +//:print qq(wire [64 -1:0] rq${i}_wr_pd = rq_wr_pd;\n); +//:print("NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo lat_fifo${i} (\n"); +//:print(".nvdla_core_clk(nvdla_core_clk)\n"); +//:print(",.nvdla_core_rstn(nvdla_core_rstn)\n"); +//:print(",.rq_wr_prdy(rq${i}_wr_prdy)\n"); +//:print(",.rq_wr_pvld(rq${i}_wr_pvld)\n"); +//:print(",.rq_wr_pd(rq${i}_wr_pd)\n"); +//:print(",.rq_rd_prdy(rq${i}_rd_prdy)\n"); +//:print(",.rq_rd_pvld(rq${i}_rd_pvld)\n"); +//:print(",.rq_rd_pd(rq${i}_rd_pd)\n"); +//:print(",.pwrbus_ram_pd(pwrbus_ram_pd)\n"); +//:print(");\n"); +//:} +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("wire src${i}_req = rq${i}_rd_pvld && ctt${i}_vld && ro${i}_wr_rdy;\n"); +//:print("assign ctt${i}_rdy = src${i}_gnt;\n"); +//:print("assign rq${i}_rd_prdy = src${i}_gnt;\n"); +//:} +//:my $k = 7; +//:my $i; +//:for ($i=$k; $i<10;$i++) { +//:print qq( +//: wire src${i}_req = 1'b0; +//:); +//:} +read_eg_arb u_read_eg_arb ( + .req0 (src0_req) //|< w + ,.req1 (src1_req) //|< w + ,.req2 (src2_req) //|< w + ,.req3 (src3_req) //|< w + ,.req4 (src4_req) //|< w + ,.req5 (src5_req) //|< w + ,.req6 (src6_req) //|< w + ,.req7 (src7_req) //|< w + ,.req8 (src8_req) //|< w + ,.req9 (src9_req) //|< w + ,.wt0 ({8{1'b1}}) //|< ? + ,.wt1 ({8{1'b1}}) //|< ? + ,.wt2 ({8{1'b1}}) //|< ? + ,.wt3 ({8{1'b1}}) //|< ? + ,.wt4 ({8{1'b1}}) //|< ? + ,.wt5 ({8{1'b1}}) //|< ? + ,.wt6 ({8{1'b1}}) //|< ? + ,.wt7 ({8{1'b1}}) //|< ? + ,.wt8 ({8{1'b1}}) //|< ? + ,.wt9 ({8{1'b1}}) //|< ? + ,.clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.gnt0 (src0_gnt) //|> w + ,.gnt1 (src1_gnt) //|> w + ,.gnt2 (src2_gnt) //|> w + ,.gnt3 (src3_gnt) //|> w + ,.gnt4 (src4_gnt) //|> w + ,.gnt5 (src5_gnt) //|> w + ,.gnt6 (src6_gnt) //|> w + ); +always @(src0_gnt or rq0_rd_pd +//:my $k = 7; +//:my $i; +//:for($i=1;$i<$k;$i++) { +//:print("or src${i}_gnt or rq${i}_rd_pd\n"); +//:} +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print("src${i}_gnt: arb_data = rq${i}_rd_pd;\n"); +//:} + default : begin + arb_data[64 -1:0] = {64{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +always @(src0_gnt or ctt0_cq_pd +//:my $k = 7; +//:my $i; +//:for($i=1;$i<$k;$i++) { +//:print("or src${i}_gnt or ctt${i}_cq_pd\n"); +//:} +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print("src${i}_gnt: arb_cq_pd = ctt${i}_cq_pd;\n"); +//:} + default : begin + arb_cq_pd = {7{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +always @(src0_gnt or ctt0_cnt +//:my $k = 7; +//:my $i; +//:for($i=1;$i<$k;$i++) { +//:print("or src${i}_gnt or ctt${i}_cnt\n"); +//:} +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//: print("src${i}_gnt: arb_cnt = ctt${i}_cnt;\n"); +//:} + default : begin + arb_cnt = {2{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +// PKT_UNPACK_WIRE( nocif_read_ig2eg , arb_cq_ , arb_cq_pd ) +assign arb_cq_lens[1:0] = arb_cq_pd[1:0]; +assign arb_cq_swizzle = arb_cq_pd[2]; +assign arb_cq_odd = arb_cq_pd[3]; +assign arb_cq_ltran = arb_cq_pd[4]; +assign arb_cq_fdrop = arb_cq_pd[5]; +assign arb_cq_ldrop = arb_cq_pd[6]; +always @( + arb_first_beat + or arb_cq_fdrop + or arb_last_beat + or arb_cq_ldrop + ) begin + if (arb_first_beat && arb_cq_fdrop) begin + arb_wen = 2'b10; + end else if (arb_last_beat && arb_cq_ldrop) begin + arb_wen = 2'b01; + end else begin + arb_wen = 2'b11; + end +end +assign last_odd = arb_last_beat && arb_cq_ltran && arb_cq_odd; +assign arb_data0 = {arb_data[(64/2)-1:0]}; +assign arb_data1 = {arb_data[64 -1:(64/2)]}; +assign arb_data0_swizzled = arb_cq_swizzle ? arb_data1 : arb_data0; +assign arb_data1_swizzled = arb_cq_swizzle ? arb_data0 : arb_data1; +assign arb_pd0 = {last_odd,arb_data0_swizzled}; +assign arb_pd1 = {1'b0 ,arb_data1_swizzled}; +assign arb_wen0_swizzled = arb_cq_swizzle ? arb_wen[1] : arb_wen[0]; +assign arb_wen1_swizzled = arb_cq_swizzle ? arb_wen[0] : arb_wen[1]; +assign arb_last_beat = (arb_cnt==arb_cq_lens); +assign arb_first_beat = (arb_cnt==0); +//:my $k = 7; +//:my $i; +//:my $j=1; +//:for($i=0;$i<$k;$i++) { +//:print qq( +//:assign ro${i}_wr_rdy = ro${i}_wr0_prdy & ro${i}_wr1_prdy; +//:wire ro${i}_wr0_pvld = src${i}_gnt & arb_wen0_swizzled & ro${i}_wr1_prdy; +//:wire [64/2:0] ro${i}_wr0_pd = arb_pd0; +//:NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro${i}_fifo0 ( +//:.nvdla_core_clk(nvdla_core_clk) +//:,.nvdla_core_rstn(nvdla_core_rstn) +//:,.ro_wr_prdy(ro${i}_wr0_prdy) +//:,.ro_wr_pvld(ro${i}_wr0_pvld) +//:,.ro_wr_pd(ro${i}_wr0_pd) +//:,.ro_rd_prdy(ro${i}_rd0_prdy) +//:,.ro_rd_pvld(ro${i}_rd0_pvld) +//:,.ro_rd_pd(ro${i}_rd0_pd) +//:,.pwrbus_ram_pd(pwrbus_ram_pd) +//:); +//:); +//:print("wire ro${i}_wr1_pvld = src${i}_gnt & arb_wen1_swizzled & ro${i}_wr0_prdy;\n"); +//:print qq(wire [64/2:0] ro${i}_wr1_pd = arb_pd1;\n); +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ro${i}_fifo1 ( +//:.nvdla_core_clk(nvdla_core_clk) +//:,.nvdla_core_rstn(nvdla_core_rstn) +//:,.ro_wr_prdy(ro${i}_wr1_prdy) +//:,.ro_wr_pvld(ro${i}_wr1_pvld) +//:,.ro_wr_pd(ro${i}_wr1_pd) +//:,.ro_rd_prdy(ro${i}_rd1_prdy) +//:,.ro_rd_pvld(ro${i}_rd1_pvld) +//:,.ro_rd_pd(ro${i}_rd1_pd) +//:,.pwrbus_ram_pd(pwrbus_ram_pd) +//:); +//:); +//:print("assign dma${i}_vld = ro${i}_rd0_pvld & (dma${i}_last_odd ? 1'b1 : ro${i}_rd1_pvld);\n"); +//:print("assign {dma${i}_last_odd,dma${i}_data0} = ro${i}_rd0_pd;\n"); +//:print("assign {mon_dma${i}_lodd,dma${i}_data1} = ro${i}_rd1_pd;\n"); +//:print("assign dma${i}_is_last_odd = ro${i}_rd0_pvld & dma${i}_last_odd;\n"); +//:print("assign dma${i}_mask = dma${i}_is_last_odd ? 2'b01: 2'b11;\n"); +//:print qq(assign dma${i}_mdata0 = {64/2{dma${i}_mask[0]}} & dma${i}_data0;\n); +//:print qq(assign dma${i}_mdata1 = {64/2{dma${i}_mask[1]}} & dma${i}_data1;\n); +//:if ($j > 1) { +//: print("assign dma${i}_pd = {dma${i}_mask,dma${i}_data};\n"); +//:} elsif ($j == 1) { +//: print("assign dma${i}_pd = {1'b1,dma${i}_data};\n"); +//:} +//:print("assign dma${i}_data = {dma${i}_mdata1,dma${i}_mdata0};\n"); +//:print("assign ro${i}_rd0_prdy = dma${i}_rdy & (dma${i}_is_last_odd ? 1'b1: ro${i}_rd1_pvld);\n"); +//:print("assign ro${i}_rd1_prdy = dma${i}_rdy & (dma${i}_is_last_odd ? 1'b1: ro${i}_rd0_pvld);\n"); +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 pipe_pp${i} ( +//:.nvdla_core_clk(nvdla_core_clk) +//:,.nvdla_core_rstn(nvdla_core_rstn) +//:,.rd_rsp_rdy(mcif2client${i}_rd_rsp_ready) +//:,.dma_pd(dma${i}_pd) +//:,.dma_vld(dma${i}_vld) +//:,.rd_rsp_pd(mcif2client${i}_rd_rsp_pd) +//:,.rd_rsp_valid(mcif2client${i}_rd_rsp_valid) +//:,.dma_rdy(dma${i}_rdy) +//:); +//:); +//:} +//my $dw = eval(64 +2); +//&eperl::pipe("-is -wid $dw -vo mcif2client${i}_rd_rsp_valid -do mcif2client${i}_rd_rsp_pd -ro dma${i}_rdy -vi dma${i}_vld -di dma${i}_pd -ri mcif2client${i}_rd_rsp_ready"); +//:my $k = 7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print("assign ctt${i}_last_beat = src${i}_gnt & arb_last_beat;\n"); +//:print("assign cq_rd${i}_prdy = (ctt${i}_rdy & ctt${i}_last_beat) || !ctt${i}_vld;\n"); +//:print("always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin\n"); +//:print(" if (!nvdla_core_rstn) begin\n"); +//:print(" ctt${i}_vld <= 1'b0;\n"); +//:print(" end else begin\n"); +//:print(" if ((cq_rd${i}_prdy) == 1'b1) begin\n"); +//:print(" ctt${i}_vld <= cq_rd${i}_pvld;\n"); +//:print(" end\n"); +//:print(" end\n"); +//:print("end\n"); +//:print("always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin\n"); +//:print(" if (!nvdla_core_rstn) begin\n"); +//:print(" ctt${i}_cnt <= {2{1'b0}};\n"); +//:print(" end else begin\n"); +//:print(" if (cq_rd${i}_pvld && cq_rd${i}_prdy) begin \n"); +//:print(" ctt${i}_cnt <= 0;\n"); +//:print(" end else if (ctt${i}_accept) begin\n"); +//:print(" ctt${i}_cnt <= ctt${i}_cnt + 1;\n"); +//:print(" end\n"); +//:print(" end\n"); +//:print("end\n"); +//:print("assign ctt${i}_accept = ctt${i}_vld & ctt${i}_rdy;\n"); +//:print("always @(posedge nvdla_core_clk) begin\n"); +//:print(" if (cq_rd${i}_pvld && cq_rd${i}_prdy) begin\n"); +//:print(" ctt${i}_cq_pd <= cq_rd${i}_pd;\n"); +//:print(" end\n"); +//:print("end\n"); +//:} +endmodule +module NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,ipipe_axi_rdy + ,noc2mcif_axi_r_pd + ,noc2mcif_axi_r_rvalid + ,ipipe_axi_pd + ,ipipe_axi_vld + ,noc2mcif_axi_r_rready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input ipipe_axi_rdy; +input [64 +3:0] noc2mcif_axi_r_pd; +input noc2mcif_axi_r_rvalid; +output [64 +3:0] ipipe_axi_pd; +output ipipe_axi_vld; +output noc2mcif_axi_r_rready; +reg [64 +3:0] ipipe_axi_pd; +reg ipipe_axi_vld; +reg noc2mcif_axi_r_rready; +reg [64 +3:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [64 +3:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [64 +3:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? noc2mcif_axi_r_rvalid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && noc2mcif_axi_r_rvalid)? noc2mcif_axi_r_pd[64 +3:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + noc2mcif_axi_r_rready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or ipipe_axi_rdy + or p1_pipe_skid_data + ) begin + ipipe_axi_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = ipipe_axi_rdy; + ipipe_axi_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (ipipe_axi_vld^ipipe_axi_rdy^noc2mcif_axi_r_rvalid^noc2mcif_axi_r_rready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (noc2mcif_axi_r_rvalid && !noc2mcif_axi_r_rready), (noc2mcif_axi_r_rvalid), (noc2mcif_axi_r_rready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule +module NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,rd_rsp_rdy + ,dma_pd + ,dma_vld + ,rd_rsp_pd + ,rd_rsp_valid + ,dma_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input rd_rsp_rdy; +input [64 +1 -1:0] dma_pd; +input dma_vld; +output [64 +1 -1:0] rd_rsp_pd; +output rd_rsp_valid; +output dma_rdy; +reg [64 +1 -1:0] rd_rsp_pd; +reg rd_rsp_valid; +reg dma_rdy; +reg [64 +1 -1:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [64 +1 -1:0] p2_skid_data; +reg [64 +1 -1:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + dma_vld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = dma_vld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + dma_rdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + dma_rdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? dma_pd[64 +1 -1:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or dma_vld + or p2_skid_valid + or dma_pd + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? dma_vld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? dma_pd[64 +1 -1:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or rd_rsp_rdy + or p2_pipe_data + ) begin + rd_rsp_valid = p2_pipe_valid; + p2_pipe_ready = rd_rsp_rdy; + rd_rsp_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rd_rsp_valid^rd_rsp_rdy^dma_vld^dma_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (dma_vld && !dma_rdy), (dma_vld), (dma_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus rq_wr -rd_pipebus rq_rd -d 4 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , rq_wr_prdy + , rq_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , rq_wr_pause +`endif + , rq_wr_pd + , rq_rd_prdy + , rq_rd_pvld + , rq_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output rq_wr_prdy; +input rq_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input rq_wr_pause; +`endif +input [64 -1:0] rq_wr_pd; +input rq_rd_prdy; +output rq_rd_pvld; +output [64 -1:0] rq_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg rq_wr_busy_int; // copy for internal use +assign rq_wr_prdy = !rq_wr_busy_int; +assign wr_reserving = rq_wr_pvld && !rq_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] rq_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? rq_wr_count : (rq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (rq_wr_count + 1'd1) : rq_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire rq_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check rq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || rq_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire rq_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check rq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_wr_busy_int <= 1'b0; + rq_wr_count <= 3'd0; + end else begin + rq_wr_busy_int <= rq_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + rq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + rq_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as rq_wr_pvld +// +// RAM +// +reg [1:0] rq_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + rq_wr_adr <= rq_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] rq_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [64 -1:0] rq_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( rq_wr_pd ) + , .we ( ram_we ) + , .wa ( rq_wr_adr ) + , .ra ( rq_rd_adr ) + , .dout ( rq_rd_pd ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = rq_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + rq_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + rq_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg rq_rd_pvld; // data out of fifo is valid +reg rq_rd_pvld_int; // internal copy of rq_rd_pvld +assign rd_popping = rq_rd_pvld_int && rq_rd_prdy; +reg [2:0] rq_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? rq_rd_count : + (rq_rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (rq_rd_count + 1'd1) : + rq_rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +wire rd_count_next_rd_popping_not_0 = rd_count_next_rd_popping != 0; +wire rd_count_next_no_rd_popping_not_0 = rd_count_next_no_rd_popping != 0; +wire rd_count_next_not_0 = rd_popping ? rd_count_next_rd_popping_not_0 : + rd_count_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rq_rd_count <= 3'd0; + rq_rd_pvld <= 1'b0; + rq_rd_pvld_int <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + rq_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rq_rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rq_rd_pvld <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rq_rd_pvld <= `x_or_0; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + rq_rd_pvld_int <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + rq_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (rq_wr_pvld && !rq_wr_busy_int) || (rq_wr_busy_int != rq_wr_busy_next)) || (rd_pushing || rd_popping || (rq_rd_pvld && rq_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( rq_wr_pvld && !(!rq_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, rq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64 -1:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [64 -1:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [64 -1:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [64 -1:0] ram_ff0; +reg [64 -1:0] ram_ff1; +reg [64 -1:0] ram_ff2; +reg [64 -1:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [64 -1:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {64{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [64 -1:0] Di0; +input [1:0] Ra0; +output [64 -1:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = NVDLA_PRIMARY_MEMIF_WIDTH'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [64 -1:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [64 -1:0] Q0 = mem[0]; +wire [64 -1:0] Q1 = mem[1]; +wire [64 -1:0] Q2 = mem[2]; +wire [64 -1:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xPRIMARY_MEMIF_WIDTH] } +endmodule // vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +//vmw: Memory vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +//vmw: Address-size 2 +//vmw: Data-size 64 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[64 -1:0] data0[PRIMARY_MEMIF_WIDTH-1:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[64 -1:0] data1[PRIMARY_MEMIF_WIDTH-1:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -d 4 -ram_bypass -rd_reg -rd_busy_reg -w 257 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , ro_wr_pause +`endif + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input ro_wr_pause; +`endif +input [64/2:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [64/2:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] ro_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || ro_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 3'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [1:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [64/2:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 3'd4 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg ro_rd_prdy_d; // ro_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_prdy_d <= 1'b1; + end else begin + ro_rd_prdy_d <= ro_rd_prdy; + end +end +wire ro_rd_prdy_d_o; // combinatorial rd_busy +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int_o; // internal copy of ro_rd_pvld_o +wire ro_rd_pvld_o = ro_rd_pvld_int_o; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int_o && !ro_rd_prdy_d_o); +reg [2:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SKID for -rd_busy_reg +// +reg [64/2:0] ro_rd_pd_o; // output data register +wire rd_req_next_o = (ro_rd_pvld_p || (ro_rd_pvld_int_o && !ro_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int_o <= 1'b0; + end else begin + ro_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (ro_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + ro_rd_pd_o <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((ro_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + ro_rd_pd_o <= {257{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg [64/2:0] ro_rd_pd; // output data register +reg ro_rd_pvld_int_d; // so we can bubble-collapse ro_rd_prdy_d +assign ro_rd_prdy_d_o = !((ro_rd_pvld_o && ro_rd_pvld_int_d && !ro_rd_prdy_d ) ); +wire rd_req_next = (!ro_rd_prdy_d_o ? ro_rd_pvld_o : ro_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + ro_rd_pvld_int_d <= 1'b0; + end else begin + if ( !ro_rd_pvld_int || ro_rd_prdy ) begin + ro_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!ro_rd_pvld_int || ro_rd_prdy) ) begin + end else begin + ro_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + ro_rd_pvld_int_d <= ro_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!ro_rd_pvld_int || ro_rd_prdy ) ) begin + case (!ro_rd_prdy_d_o) + 1'b0: ro_rd_pd <= ro_rd_pd_p; + 1'b1: ro_rd_pd <= ro_rd_pd_o; +//VCS coverage off + default: ro_rd_pd <= {257{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!ro_rd_pvld_int || ro_rd_prdy)) ) begin + end else begin + ro_rd_pd <= {257{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy_d) || (ro_rd_pvld_int_o && ro_rd_prdy_d_o)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( ro_wr_pvld && !(!ro_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64/2:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [64/2:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [64/2:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [64/2:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [64/2:0] ram_ff0; +reg [64/2:0] ram_ff1; +reg [64/2:0] ram_ff2; +reg [64/2:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [64/2:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {257{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [64/2:0] Di0; +input [1:0] Ra0; +output [64/2:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 257'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [64/2:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [64/2:0] Q0 = mem[0]; +wire [64/2:0] Q1 = mem[1]; +wire [64/2:0] Q2 = mem[2]; +wire [64/2:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257] } +endmodule // vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +//vmw: Memory vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +//vmw: Address-size 2 +//vmw: Data-size 257 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[64/2:0] +//data0[64/2:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[64/2:0] +//data1[64/2:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v new file mode 100644 index 0000000..e9660d8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v @@ -0,0 +1,413 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_ig.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd + ,eg2ig_axi_vld +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print (",client${i}2mcif_lat_fifo_depth\n"); +//: print (",client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print (",client${i}2mcif_rd_req_valid\n"); +//: print (",client${i}2mcif_rd_req_ready\n"); +//: print (",client${i}2mcif_rd_req_pd\n"); +//: print (",client${i}2mcif_rd_wt\n"); +//: print (",client${i}2mcif_rd_axid\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +,client02mcif_lat_fifo_depth +,client02mcif_rd_cdt_lat_fifo_pop +,client02mcif_rd_req_valid +,client02mcif_rd_req_ready +,client02mcif_rd_req_pd +,client02mcif_rd_wt +,client02mcif_rd_axid +,client12mcif_lat_fifo_depth +,client12mcif_rd_cdt_lat_fifo_pop +,client12mcif_rd_req_valid +,client12mcif_rd_req_ready +,client12mcif_rd_req_pd +,client12mcif_rd_wt +,client12mcif_rd_axid +,client22mcif_lat_fifo_depth +,client22mcif_rd_cdt_lat_fifo_pop +,client22mcif_rd_req_valid +,client22mcif_rd_req_ready +,client22mcif_rd_req_pd +,client22mcif_rd_wt +,client22mcif_rd_axid +,client32mcif_lat_fifo_depth +,client32mcif_rd_cdt_lat_fifo_pop +,client32mcif_rd_req_valid +,client32mcif_rd_req_ready +,client32mcif_rd_req_pd +,client32mcif_rd_wt +,client32mcif_rd_axid +,client42mcif_lat_fifo_depth +,client42mcif_rd_cdt_lat_fifo_pop +,client42mcif_rd_req_valid +,client42mcif_rd_req_ready +,client42mcif_rd_req_pd +,client42mcif_rd_wt +,client42mcif_rd_axid +,client52mcif_lat_fifo_depth +,client52mcif_rd_cdt_lat_fifo_pop +,client52mcif_rd_req_valid +,client52mcif_rd_req_ready +,client52mcif_rd_req_pd +,client52mcif_rd_wt +,client52mcif_rd_axid +,client62mcif_lat_fifo_depth +,client62mcif_rd_cdt_lat_fifo_pop +,client62mcif_rd_req_valid +,client62mcif_rd_req_ready +,client62mcif_rd_req_pd +,client62mcif_rd_wt +,client62mcif_rd_axid + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,reg2dp_rd_os_cnt + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,cq_wr_prdy //|> o + ,cq_wr_thread_id //|> o + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arready //|< i + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o +); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print ("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print ("input client${i}2mcif_rd_req_valid;\n"); +//: print ("output client${i}2mcif_rd_req_ready;\n"); +//: print qq( +//: input [32 +14:0] client${i}2mcif_rd_req_pd; +//: ); +//: print ("input [7:0] client${i}2mcif_rd_wt;\n"); +//: print ("input [3:0] client${i}2mcif_rd_axid;\n"); +//: print ("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input client02mcif_rd_cdt_lat_fifo_pop; +input client02mcif_rd_req_valid; +output client02mcif_rd_req_ready; + +input [32 +14:0] client02mcif_rd_req_pd; +input [7:0] client02mcif_rd_wt; +input [3:0] client02mcif_rd_axid; +input [7:0] client02mcif_lat_fifo_depth; +input client12mcif_rd_cdt_lat_fifo_pop; +input client12mcif_rd_req_valid; +output client12mcif_rd_req_ready; + +input [32 +14:0] client12mcif_rd_req_pd; +input [7:0] client12mcif_rd_wt; +input [3:0] client12mcif_rd_axid; +input [7:0] client12mcif_lat_fifo_depth; +input client22mcif_rd_cdt_lat_fifo_pop; +input client22mcif_rd_req_valid; +output client22mcif_rd_req_ready; + +input [32 +14:0] client22mcif_rd_req_pd; +input [7:0] client22mcif_rd_wt; +input [3:0] client22mcif_rd_axid; +input [7:0] client22mcif_lat_fifo_depth; +input client32mcif_rd_cdt_lat_fifo_pop; +input client32mcif_rd_req_valid; +output client32mcif_rd_req_ready; + +input [32 +14:0] client32mcif_rd_req_pd; +input [7:0] client32mcif_rd_wt; +input [3:0] client32mcif_rd_axid; +input [7:0] client32mcif_lat_fifo_depth; +input client42mcif_rd_cdt_lat_fifo_pop; +input client42mcif_rd_req_valid; +output client42mcif_rd_req_ready; + +input [32 +14:0] client42mcif_rd_req_pd; +input [7:0] client42mcif_rd_wt; +input [3:0] client42mcif_rd_axid; +input [7:0] client42mcif_lat_fifo_depth; +input client52mcif_rd_cdt_lat_fifo_pop; +input client52mcif_rd_req_valid; +output client52mcif_rd_req_ready; + +input [32 +14:0] client52mcif_rd_req_pd; +input [7:0] client52mcif_rd_wt; +input [3:0] client52mcif_rd_axid; +input [7:0] client52mcif_lat_fifo_depth; +input client62mcif_rd_cdt_lat_fifo_pop; +input client62mcif_rd_req_valid; +output client62mcif_rd_req_ready; + +input [32 +14:0] client62mcif_rd_req_pd; +input [7:0] client62mcif_rd_wt; +input [3:0] client62mcif_rd_axid; +input [7:0] client62mcif_lat_fifo_depth; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [6:0] cq_wr_pd; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +input eg2ig_axi_vld; +input [7:0] reg2dp_rd_os_cnt; +wire [32 +10:0] arb2spt_req_pd; +wire arb2spt_req_ready; +wire arb2spt_req_valid; +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print qq( +//: wire [32 +10:0] bpt2arb_req${i}_pd; +//: ); +//: print ("wire bpt2arb_req${i}_ready;\n"); +//: print ("wire bpt2arb_req${i}_valid;\n"); +//:} +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print("NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt${i} (\n"); +//: print (".nvdla_core_clk(nvdla_core_clk)\n"); +//: print (",.nvdla_core_rstn(nvdla_core_rstn)\n"); +//: print (",.dma2bpt_req_valid(client${i}2mcif_rd_req_valid)\n"); +//: print (",.dma2bpt_req_ready(client${i}2mcif_rd_req_ready)\n"); +//: print (",.dma2bpt_req_pd(client${i}2mcif_rd_req_pd)\n"); +//: print (",.dma2bpt_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print (",.bpt2arb_req_valid(bpt2arb_req${i}_valid)\n"); +//: print (",.bpt2arb_req_ready(bpt2arb_req${i}_ready)\n"); +//: print (",.bpt2arb_req_pd(bpt2arb_req${i}_pd)\n"); +//: print (",.tieoff_axid(client${i}2mcif_rd_axid)\n"); +//: print (",.tieoff_lat_fifo_depth(client${i}2mcif_lat_fifo_depth)\n"); +//: print (");\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [32 +10:0] bpt2arb_req0_pd; +wire bpt2arb_req0_ready; +wire bpt2arb_req0_valid; + +wire [32 +10:0] bpt2arb_req1_pd; +wire bpt2arb_req1_ready; +wire bpt2arb_req1_valid; + +wire [32 +10:0] bpt2arb_req2_pd; +wire bpt2arb_req2_ready; +wire bpt2arb_req2_valid; + +wire [32 +10:0] bpt2arb_req3_pd; +wire bpt2arb_req3_ready; +wire bpt2arb_req3_valid; + +wire [32 +10:0] bpt2arb_req4_pd; +wire bpt2arb_req4_ready; +wire bpt2arb_req4_valid; + +wire [32 +10:0] bpt2arb_req5_pd; +wire bpt2arb_req5_ready; +wire bpt2arb_req5_valid; + +wire [32 +10:0] bpt2arb_req6_pd; +wire bpt2arb_req6_ready; +wire bpt2arb_req6_valid; +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt0 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client02mcif_rd_req_valid) +,.dma2bpt_req_ready(client02mcif_rd_req_ready) +,.dma2bpt_req_pd(client02mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client02mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req0_valid) +,.bpt2arb_req_ready(bpt2arb_req0_ready) +,.bpt2arb_req_pd(bpt2arb_req0_pd) +,.tieoff_axid(client02mcif_rd_axid) +,.tieoff_lat_fifo_depth(client02mcif_lat_fifo_depth) +); +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt1 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client12mcif_rd_req_valid) +,.dma2bpt_req_ready(client12mcif_rd_req_ready) +,.dma2bpt_req_pd(client12mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client12mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req1_valid) +,.bpt2arb_req_ready(bpt2arb_req1_ready) +,.bpt2arb_req_pd(bpt2arb_req1_pd) +,.tieoff_axid(client12mcif_rd_axid) +,.tieoff_lat_fifo_depth(client12mcif_lat_fifo_depth) +); +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt2 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client22mcif_rd_req_valid) +,.dma2bpt_req_ready(client22mcif_rd_req_ready) +,.dma2bpt_req_pd(client22mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client22mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req2_valid) +,.bpt2arb_req_ready(bpt2arb_req2_ready) +,.bpt2arb_req_pd(bpt2arb_req2_pd) +,.tieoff_axid(client22mcif_rd_axid) +,.tieoff_lat_fifo_depth(client22mcif_lat_fifo_depth) +); +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt3 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client32mcif_rd_req_valid) +,.dma2bpt_req_ready(client32mcif_rd_req_ready) +,.dma2bpt_req_pd(client32mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client32mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req3_valid) +,.bpt2arb_req_ready(bpt2arb_req3_ready) +,.bpt2arb_req_pd(bpt2arb_req3_pd) +,.tieoff_axid(client32mcif_rd_axid) +,.tieoff_lat_fifo_depth(client32mcif_lat_fifo_depth) +); +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt4 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client42mcif_rd_req_valid) +,.dma2bpt_req_ready(client42mcif_rd_req_ready) +,.dma2bpt_req_pd(client42mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client42mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req4_valid) +,.bpt2arb_req_ready(bpt2arb_req4_ready) +,.bpt2arb_req_pd(bpt2arb_req4_pd) +,.tieoff_axid(client42mcif_rd_axid) +,.tieoff_lat_fifo_depth(client42mcif_lat_fifo_depth) +); +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt5 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client52mcif_rd_req_valid) +,.dma2bpt_req_ready(client52mcif_rd_req_ready) +,.dma2bpt_req_pd(client52mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client52mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req5_valid) +,.bpt2arb_req_ready(bpt2arb_req5_ready) +,.bpt2arb_req_pd(bpt2arb_req5_pd) +,.tieoff_axid(client52mcif_rd_axid) +,.tieoff_lat_fifo_depth(client52mcif_lat_fifo_depth) +); +NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt6 ( +.nvdla_core_clk(nvdla_core_clk) +,.nvdla_core_rstn(nvdla_core_rstn) +,.dma2bpt_req_valid(client62mcif_rd_req_valid) +,.dma2bpt_req_ready(client62mcif_rd_req_ready) +,.dma2bpt_req_pd(client62mcif_rd_req_pd) +,.dma2bpt_cdt_lat_fifo_pop(client62mcif_rd_cdt_lat_fifo_pop) +,.bpt2arb_req_valid(bpt2arb_req6_valid) +,.bpt2arb_req_ready(bpt2arb_req6_ready) +,.bpt2arb_req_pd(bpt2arb_req6_pd) +,.tieoff_axid(client62mcif_rd_axid) +,.tieoff_lat_fifo_depth(client62mcif_lat_fifo_depth) +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [32 +10:0] spt2cvt_req_pd; +wire spt2cvt_req_valid; +wire spt2cvt_req_ready; +NV_NVDLA_NOCIF_DRAM_READ_IG_spt u_spt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_req_valid (arb2spt_req_valid) //|< w + ,.arb2spt_req_ready (arb2spt_req_ready) //|> w + ,.arb2spt_req_pd (arb2spt_req_pd[32 +10:0]) //|< w + ,.spt2cvt_req_valid (spt2cvt_req_valid) //|> w + ,.spt2cvt_req_ready (spt2cvt_req_ready) //|< w + ,.spt2cvt_req_pd (spt2cvt_req_pd[32 +10:0]) //|> w + ); +NV_NVDLA_NOCIF_DRAM_READ_IG_cvt u_cvt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.spt2cvt_req_valid (spt2cvt_req_valid) //|< w + ,.spt2cvt_req_ready (spt2cvt_req_ready) //|> w + ,.spt2cvt_req_pd (spt2cvt_req_pd[32 +10:0]) //|< w + ,.cq_wr_pvld (cq_wr_pvld) //|> o + ,.cq_wr_prdy (cq_wr_prdy) //|< i + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> o + ,.cq_wr_pd (cq_wr_pd[6:0]) //|> o + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr[32 -1:0]) //|> o + ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|< i + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i + ); +NV_NVDLA_NOCIF_DRAM_READ_IG_arb u_arb ( + .nvdla_core_clk(nvdla_core_clk) + ,.nvdla_core_rstn(nvdla_core_rstn) +//:my $k=7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print(",.bpt2arb_req${i}_valid (bpt2arb_req${i}_valid)\n"); +//:print(",.bpt2arb_req${i}_ready (bpt2arb_req${i}_ready)\n"); +//:print(",.bpt2arb_req${i}_pd (bpt2arb_req${i}_pd)\n"); +//:print(",.client${i}2mcif_rd_wt (client${i}2mcif_rd_wt)\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.bpt2arb_req0_valid (bpt2arb_req0_valid) +,.bpt2arb_req0_ready (bpt2arb_req0_ready) +,.bpt2arb_req0_pd (bpt2arb_req0_pd) +,.client02mcif_rd_wt (client02mcif_rd_wt) +,.bpt2arb_req1_valid (bpt2arb_req1_valid) +,.bpt2arb_req1_ready (bpt2arb_req1_ready) +,.bpt2arb_req1_pd (bpt2arb_req1_pd) +,.client12mcif_rd_wt (client12mcif_rd_wt) +,.bpt2arb_req2_valid (bpt2arb_req2_valid) +,.bpt2arb_req2_ready (bpt2arb_req2_ready) +,.bpt2arb_req2_pd (bpt2arb_req2_pd) +,.client22mcif_rd_wt (client22mcif_rd_wt) +,.bpt2arb_req3_valid (bpt2arb_req3_valid) +,.bpt2arb_req3_ready (bpt2arb_req3_ready) +,.bpt2arb_req3_pd (bpt2arb_req3_pd) +,.client32mcif_rd_wt (client32mcif_rd_wt) +,.bpt2arb_req4_valid (bpt2arb_req4_valid) +,.bpt2arb_req4_ready (bpt2arb_req4_ready) +,.bpt2arb_req4_pd (bpt2arb_req4_pd) +,.client42mcif_rd_wt (client42mcif_rd_wt) +,.bpt2arb_req5_valid (bpt2arb_req5_valid) +,.bpt2arb_req5_ready (bpt2arb_req5_ready) +,.bpt2arb_req5_pd (bpt2arb_req5_pd) +,.client52mcif_rd_wt (client52mcif_rd_wt) +,.bpt2arb_req6_valid (bpt2arb_req6_valid) +,.bpt2arb_req6_ready (bpt2arb_req6_ready) +,.bpt2arb_req6_pd (bpt2arb_req6_pd) +,.client62mcif_rd_wt (client62mcif_rd_wt) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.arb2spt_req_valid (arb2spt_req_valid) //|> w + ,.arb2spt_req_ready (arb2spt_req_ready) //|< w + ,.arb2spt_req_pd (arb2spt_req_pd[32 +10:0]) //|> w +); +endmodule // NV_NVDLA_NOCIF_READ_ig diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v.vcp new file mode 100644 index 0000000..d67bcd1 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v.vcp @@ -0,0 +1,149 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_READ_ig.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_READ_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd + ,eg2ig_axi_vld +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print (",client${i}2mcif_lat_fifo_depth\n"); +//: print (",client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print (",client${i}2mcif_rd_req_valid\n"); +//: print (",client${i}2mcif_rd_req_ready\n"); +//: print (",client${i}2mcif_rd_req_pd\n"); +//: print (",client${i}2mcif_rd_wt\n"); +//: print (",client${i}2mcif_rd_axid\n"); +//:} + ,reg2dp_rd_os_cnt + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,cq_wr_prdy //|> o + ,cq_wr_thread_id //|> o + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arready //|< i + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o +); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print ("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print ("input client${i}2mcif_rd_req_valid;\n"); +//: print ("output client${i}2mcif_rd_req_ready;\n"); +//: print qq( +//: input [32 +14:0] client${i}2mcif_rd_req_pd; +//: ); +//: print ("input [7:0] client${i}2mcif_rd_wt;\n"); +//: print ("input [3:0] client${i}2mcif_rd_axid;\n"); +//: print ("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: } +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [6:0] cq_wr_pd; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +input eg2ig_axi_vld; +input [7:0] reg2dp_rd_os_cnt; +wire [32 +10:0] arb2spt_req_pd; +wire arb2spt_req_ready; +wire arb2spt_req_valid; +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print qq( +//: wire [32 +10:0] bpt2arb_req${i}_pd; +//: ); +//: print ("wire bpt2arb_req${i}_ready;\n"); +//: print ("wire bpt2arb_req${i}_valid;\n"); +//:} +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print("NV_NVDLA_NOCIF_DRAM_READ_IG_bpt u_bpt${i} (\n"); +//: print (".nvdla_core_clk(nvdla_core_clk)\n"); +//: print (",.nvdla_core_rstn(nvdla_core_rstn)\n"); +//: print (",.dma2bpt_req_valid(client${i}2mcif_rd_req_valid)\n"); +//: print (",.dma2bpt_req_ready(client${i}2mcif_rd_req_ready)\n"); +//: print (",.dma2bpt_req_pd(client${i}2mcif_rd_req_pd)\n"); +//: print (",.dma2bpt_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print (",.bpt2arb_req_valid(bpt2arb_req${i}_valid)\n"); +//: print (",.bpt2arb_req_ready(bpt2arb_req${i}_ready)\n"); +//: print (",.bpt2arb_req_pd(bpt2arb_req${i}_pd)\n"); +//: print (",.tieoff_axid(client${i}2mcif_rd_axid)\n"); +//: print (",.tieoff_lat_fifo_depth(client${i}2mcif_lat_fifo_depth)\n"); +//: print (");\n"); +//:} +wire [32 +10:0] spt2cvt_req_pd; +wire spt2cvt_req_valid; +wire spt2cvt_req_ready; +NV_NVDLA_NOCIF_DRAM_READ_IG_spt u_spt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_req_valid (arb2spt_req_valid) //|< w + ,.arb2spt_req_ready (arb2spt_req_ready) //|> w + ,.arb2spt_req_pd (arb2spt_req_pd[32 +10:0]) //|< w + ,.spt2cvt_req_valid (spt2cvt_req_valid) //|> w + ,.spt2cvt_req_ready (spt2cvt_req_ready) //|< w + ,.spt2cvt_req_pd (spt2cvt_req_pd[32 +10:0]) //|> w + ); +NV_NVDLA_NOCIF_DRAM_READ_IG_cvt u_cvt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.spt2cvt_req_valid (spt2cvt_req_valid) //|< w + ,.spt2cvt_req_ready (spt2cvt_req_ready) //|> w + ,.spt2cvt_req_pd (spt2cvt_req_pd[32 +10:0]) //|< w + ,.cq_wr_pvld (cq_wr_pvld) //|> o + ,.cq_wr_prdy (cq_wr_prdy) //|< i + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> o + ,.cq_wr_pd (cq_wr_pd[6:0]) //|> o + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr[32 -1:0]) //|> o + ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|< i + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i + ); +NV_NVDLA_NOCIF_DRAM_READ_IG_arb u_arb ( + .nvdla_core_clk(nvdla_core_clk) + ,.nvdla_core_rstn(nvdla_core_rstn) +//:my $k=7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print(",.bpt2arb_req${i}_valid (bpt2arb_req${i}_valid)\n"); +//:print(",.bpt2arb_req${i}_ready (bpt2arb_req${i}_ready)\n"); +//:print(",.bpt2arb_req${i}_pd (bpt2arb_req${i}_pd)\n"); +//:print(",.client${i}2mcif_rd_wt (client${i}2mcif_rd_wt)\n"); +//:} + ,.arb2spt_req_valid (arb2spt_req_valid) //|> w + ,.arb2spt_req_ready (arb2spt_req_ready) //|< w + ,.arb2spt_req_pd (arb2spt_req_pd[32 +10:0]) //|> w +); +endmodule // NV_NVDLA_NOCIF_READ_ig diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v new file mode 100644 index 0000000..03b2756 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v @@ -0,0 +1,1275 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,arb2spt_cmd_ready //|< i + ,arb2spt_dat_ready //|< i + ,pwrbus_ram_pd + ,arb2spt_cmd_pd //|> o + ,arb2spt_cmd_valid //|> o + ,arb2spt_dat_pd //|> o + ,arb2spt_dat_valid //|> o +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: ,bpt2arb_cmd${i}_pd +//: ,bpt2arb_cmd${i}_valid +//: ,bpt2arb_cmd${i}_ready +//: ,bpt2arb_dat${i}_pd +//: ,bpt2arb_dat${i}_valid +//: ,bpt2arb_dat${i}_ready +//: ,client${i}2mcif_wr_wt +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,bpt2arb_cmd0_pd +,bpt2arb_cmd0_valid +,bpt2arb_cmd0_ready +,bpt2arb_dat0_pd +,bpt2arb_dat0_valid +,bpt2arb_dat0_ready +,client02mcif_wr_wt + +,bpt2arb_cmd1_pd +,bpt2arb_cmd1_valid +,bpt2arb_cmd1_ready +,bpt2arb_dat1_pd +,bpt2arb_dat1_valid +,bpt2arb_dat1_ready +,client12mcif_wr_wt + +,bpt2arb_cmd2_pd +,bpt2arb_cmd2_valid +,bpt2arb_cmd2_ready +,bpt2arb_dat2_pd +,bpt2arb_dat2_valid +,bpt2arb_dat2_ready +,client22mcif_wr_wt + +//| eperl: generated_end (DO NOT EDIT ABOVE) +); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:input bpt2arb_cmd${i}_valid; +//:output bpt2arb_cmd${i}_ready; +//:input [32 +12:0] bpt2arb_cmd${i}_pd; +//:input bpt2arb_dat${i}_valid; +//:output bpt2arb_dat${i}_ready; +//:input [64:0] bpt2arb_dat${i}_pd; +//:input [7:0] client${i}2mcif_wr_wt; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input bpt2arb_cmd0_valid; +output bpt2arb_cmd0_ready; +input [32 +12:0] bpt2arb_cmd0_pd; +input bpt2arb_dat0_valid; +output bpt2arb_dat0_ready; +input [64:0] bpt2arb_dat0_pd; +input [7:0] client02mcif_wr_wt; + +input bpt2arb_cmd1_valid; +output bpt2arb_cmd1_ready; +input [32 +12:0] bpt2arb_cmd1_pd; +input bpt2arb_dat1_valid; +output bpt2arb_dat1_ready; +input [64:0] bpt2arb_dat1_pd; +input [7:0] client12mcif_wr_wt; + +input bpt2arb_cmd2_valid; +output bpt2arb_cmd2_ready; +input [32 +12:0] bpt2arb_cmd2_pd; +input bpt2arb_dat2_valid; +output bpt2arb_dat2_ready; +input [64:0] bpt2arb_dat2_pd; +input [7:0] client22mcif_wr_wt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; +output arb2spt_cmd_valid; /* data valid */ +input arb2spt_cmd_ready; /* data return handshake */ +output [32 +12:0] arb2spt_cmd_pd; +output arb2spt_dat_valid; /* data valid */ +input arb2spt_dat_ready; /* data return handshake */ +output [64:0] arb2spt_dat_pd; +input [31:0] pwrbus_ram_pd; +reg [32 +12:0] arb_cmd_pd; +reg [64:0] arb_dat_pd; +reg [1:0] gnt_count; +reg [3 -1:0] stick_gnts; +reg sticky; +wire [3 -1:0] all_gnts; +wire any_arb_gnt; +wire [1:0] arb_cmd_beats; +wire arb_cmd_inc; +wire [2:0] arb_cmd_size; +wire arb_cmd_size_bit0_NC; +wire [3 -1:0] arb_gnts; +wire [4:0] arb_reqs; +wire gnt_busy; +wire is_last_beat; +wire mon_arb_cmd_beats_c; +wire spt_is_busy; +wire [3 -1:0] src_dat_vlds; +wire [3 -1:0] src_dat_gnts; +//NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_${i} ( +// .nvdla_core_clk (nvdla_core_clk) //|< i +// ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +// ,.bpt2arb_cmd0_pd (bpt2arb_cmd${i}_pd[32 +12:0]) //|< i +// ,.bpt2arb_cmd0_valid (bpt2arb_cmd${i}_valid) //|< i +// ,.src_cmd0_rdy (src_cmd${i}_rdy) //|< w +// ,.bpt2arb_cmd0_ready (bpt2arb_cmd${i}_ready) //|> o +// ,.src_cmd0_pd (src_cmd${i}_pd[32 +12:0]) //|> w +// ,.src_cmd0_vld (src_cmd${i}_vld) //|> w +// ); +//&eperl::pipe(" -is -wid $w -do src_cmd${i}_pd -vo src_cmd${i}_vld -ri bpt2arb_cmd${i}_ready -di bpt2arb_cmd${i}_pd -vi bpt2arb_cmd${i}_valid -ro src_cmd${i}_rdy"); +//:my $i; +//:my $w; +//:my $dbus_wid=64; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:wire [2:0] dfifo${i}_wr_count; +//:wire [1:0] src_cmd${i}_beats; +//:wire src_cmd${i}_beats_c; +//:wire src_cmd${i}_camp_vld; +//:wire src_cmd${i}_inc; +//:wire [2:0] src_cmd${i}_size; +//:wire src_cmd${i}_size_bit0_NC; +//:wire [$dbus_wid:0] src_dat${i}_pd; +//:wire [32 +12:0] src_cmd${i}_pd; +//:); +//:$w = eval(32 +13); +//:my $bus_wid = eval(32 +12); +//:print qq( +//:wire src_cmd${i}_rdy, src_cmd${i}_vld; +//:wire src_dat${i}_rdy, src_dat${i}_vld; +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.bpt2arb_cmd0_pd (bpt2arb_cmd${i}_pd[32 +12:0]) //|< i +//: ,.bpt2arb_cmd0_valid (bpt2arb_cmd${i}_valid) //|< i +//: ,.src_cmd0_rdy (src_cmd${i}_rdy) //|< w +//: ,.bpt2arb_cmd0_ready (bpt2arb_cmd${i}_ready) //|> o +//: ,.src_cmd0_pd (src_cmd${i}_pd[32 +12:0]) //|> w +//: ,.src_cmd0_vld (src_cmd${i}_vld) //|> w +//: ); +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo u_dfifo${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.dfifo_wr_count (dfifo${i}_wr_count[2:0]) +//: ,.dfifo_wr_prdy (bpt2arb_dat${i}_ready) +//: ,.dfifo_wr_pvld (bpt2arb_dat${i}_valid) +//: ,.dfifo_wr_pd (bpt2arb_dat${i}_pd) +//: ,.dfifo_rd_prdy (src_dat${i}_rdy) +//: ,.dfifo_rd_pvld (src_dat${i}_vld) +//: ,.dfifo_rd_pd (src_dat${i}_pd) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: ); +//: ); +//:} +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:assign src_cmd${i}_size= {3 {src_cmd${i}_vld}} & src_cmd${i}_pd[32 +7:32 +5]; +//:assign src_cmd${i}_inc = {1{src_cmd${i}_vld}} & src_cmd${i}_pd[32 +10:32 +10]; +//:assign src_cmd${i}_rdy = is_last_beat & src_dat_gnts[${i}]; +//:assign src_dat${i}_rdy = all_gnts[${i}]; +//:assign {src_cmd${i}_beats_c, src_cmd${i}_beats} = src_cmd${i}_size[2:1] + src_cmd${i}_inc; +//:assign src_cmd${i}_size_bit0_NC = src_cmd${i}_size[0]; // bit0 is not used +//:assign src_cmd${i}_camp_vld = src_cmd${i}_vld & (dfifo${i}_wr_count > {src_cmd${i}_beats_c,src_cmd${i}_beats}); +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [2:0] dfifo0_wr_count; +wire [1:0] src_cmd0_beats; +wire src_cmd0_beats_c; +wire src_cmd0_camp_vld; +wire src_cmd0_inc; +wire [2:0] src_cmd0_size; +wire src_cmd0_size_bit0_NC; +wire [64:0] src_dat0_pd; +wire [32 +12:0] src_cmd0_pd; + +wire src_cmd0_rdy, src_cmd0_vld; +wire src_dat0_rdy, src_dat0_vld; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_0 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.bpt2arb_cmd0_pd (bpt2arb_cmd0_pd[32 +12:0]) //|< i +,.bpt2arb_cmd0_valid (bpt2arb_cmd0_valid) //|< i +,.src_cmd0_rdy (src_cmd0_rdy) //|< w +,.bpt2arb_cmd0_ready (bpt2arb_cmd0_ready) //|> o +,.src_cmd0_pd (src_cmd0_pd[32 +12:0]) //|> w +,.src_cmd0_vld (src_cmd0_vld) //|> w +); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo u_dfifo0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dfifo_wr_count (dfifo0_wr_count[2:0]) +,.dfifo_wr_prdy (bpt2arb_dat0_ready) +,.dfifo_wr_pvld (bpt2arb_dat0_valid) +,.dfifo_wr_pd (bpt2arb_dat0_pd) +,.dfifo_rd_prdy (src_dat0_rdy) +,.dfifo_rd_pvld (src_dat0_vld) +,.dfifo_rd_pd (src_dat0_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +wire [2:0] dfifo1_wr_count; +wire [1:0] src_cmd1_beats; +wire src_cmd1_beats_c; +wire src_cmd1_camp_vld; +wire src_cmd1_inc; +wire [2:0] src_cmd1_size; +wire src_cmd1_size_bit0_NC; +wire [64:0] src_dat1_pd; +wire [32 +12:0] src_cmd1_pd; + +wire src_cmd1_rdy, src_cmd1_vld; +wire src_dat1_rdy, src_dat1_vld; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_1 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.bpt2arb_cmd0_pd (bpt2arb_cmd1_pd[32 +12:0]) //|< i +,.bpt2arb_cmd0_valid (bpt2arb_cmd1_valid) //|< i +,.src_cmd0_rdy (src_cmd1_rdy) //|< w +,.bpt2arb_cmd0_ready (bpt2arb_cmd1_ready) //|> o +,.src_cmd0_pd (src_cmd1_pd[32 +12:0]) //|> w +,.src_cmd0_vld (src_cmd1_vld) //|> w +); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo u_dfifo1 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dfifo_wr_count (dfifo1_wr_count[2:0]) +,.dfifo_wr_prdy (bpt2arb_dat1_ready) +,.dfifo_wr_pvld (bpt2arb_dat1_valid) +,.dfifo_wr_pd (bpt2arb_dat1_pd) +,.dfifo_rd_prdy (src_dat1_rdy) +,.dfifo_rd_pvld (src_dat1_vld) +,.dfifo_rd_pd (src_dat1_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +wire [2:0] dfifo2_wr_count; +wire [1:0] src_cmd2_beats; +wire src_cmd2_beats_c; +wire src_cmd2_camp_vld; +wire src_cmd2_inc; +wire [2:0] src_cmd2_size; +wire src_cmd2_size_bit0_NC; +wire [64:0] src_dat2_pd; +wire [32 +12:0] src_cmd2_pd; + +wire src_cmd2_rdy, src_cmd2_vld; +wire src_dat2_rdy, src_dat2_vld; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_2 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.bpt2arb_cmd0_pd (bpt2arb_cmd2_pd[32 +12:0]) //|< i +,.bpt2arb_cmd0_valid (bpt2arb_cmd2_valid) //|< i +,.src_cmd0_rdy (src_cmd2_rdy) //|< w +,.bpt2arb_cmd0_ready (bpt2arb_cmd2_ready) //|> o +,.src_cmd0_pd (src_cmd2_pd[32 +12:0]) //|> w +,.src_cmd0_vld (src_cmd2_vld) //|> w +); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo u_dfifo2 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dfifo_wr_count (dfifo2_wr_count[2:0]) +,.dfifo_wr_prdy (bpt2arb_dat2_ready) +,.dfifo_wr_pvld (bpt2arb_dat2_valid) +,.dfifo_wr_pd (bpt2arb_dat2_pd) +,.dfifo_rd_prdy (src_dat2_rdy) +,.dfifo_rd_pvld (src_dat2_vld) +,.dfifo_rd_pd (src_dat2_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +assign src_cmd0_size= {3 {src_cmd0_vld}} & src_cmd0_pd[32 +7:32 +5]; +assign src_cmd0_inc = {1{src_cmd0_vld}} & src_cmd0_pd[32 +10:32 +10]; +assign src_cmd0_rdy = is_last_beat & src_dat_gnts[0]; +assign src_dat0_rdy = all_gnts[0]; +assign {src_cmd0_beats_c, src_cmd0_beats} = src_cmd0_size[2:1] + src_cmd0_inc; +assign src_cmd0_size_bit0_NC = src_cmd0_size[0]; // bit0 is not used +assign src_cmd0_camp_vld = src_cmd0_vld & (dfifo0_wr_count > {src_cmd0_beats_c,src_cmd0_beats}); + +assign src_cmd1_size= {3 {src_cmd1_vld}} & src_cmd1_pd[32 +7:32 +5]; +assign src_cmd1_inc = {1{src_cmd1_vld}} & src_cmd1_pd[32 +10:32 +10]; +assign src_cmd1_rdy = is_last_beat & src_dat_gnts[1]; +assign src_dat1_rdy = all_gnts[1]; +assign {src_cmd1_beats_c, src_cmd1_beats} = src_cmd1_size[2:1] + src_cmd1_inc; +assign src_cmd1_size_bit0_NC = src_cmd1_size[0]; // bit0 is not used +assign src_cmd1_camp_vld = src_cmd1_vld & (dfifo1_wr_count > {src_cmd1_beats_c,src_cmd1_beats}); + +assign src_cmd2_size= {3 {src_cmd2_vld}} & src_cmd2_pd[32 +7:32 +5]; +assign src_cmd2_inc = {1{src_cmd2_vld}} & src_cmd2_pd[32 +10:32 +10]; +assign src_cmd2_rdy = is_last_beat & src_dat_gnts[2]; +assign src_dat2_rdy = all_gnts[2]; +assign {src_cmd2_beats_c, src_cmd2_beats} = src_cmd2_size[2:1] + src_cmd2_inc; +assign src_cmd2_size_bit0_NC = src_cmd2_size[0]; // bit0 is not used +assign src_cmd2_camp_vld = src_cmd2_vld & (dfifo2_wr_count > {src_cmd2_beats_c,src_cmd2_beats}); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [3 -1:0] src_cmd_vlds; +assign src_cmd_vlds = { +//:my $i; +//:for($i=3 -1;$i>=1;$i--) { +//:print qq( +//:src_cmd${i}_camp_vld, +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +src_cmd2_camp_vld, + +src_cmd1_camp_vld, + +//| eperl: generated_end (DO NOT EDIT ABOVE) + src_cmd0_camp_vld}; +assign src_dat_vlds = { +//:my $i; +//:for($i=3 -1;$i>=1;$i--) { +//:print qq( +//:src_dat${i}_vld, +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +src_dat2_vld, + +src_dat1_vld, + +//| eperl: generated_end (DO NOT EDIT ABOVE) + src_dat0_vld}; +// MUX out based on GNT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stick_gnts <= {3{1'b0}}; + end else begin + if ((any_arb_gnt) == 1'b1) begin + stick_gnts <= arb_gnts; +// VCS coverage off + end else if ((any_arb_gnt) == 1'b0) begin + end else begin + stick_gnts <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +assign src_dat_gnts = all_gnts & src_dat_vlds; +wire src_dat_vld = |src_dat_gnts; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gnt_count <= {2{1'b0}}; + end else begin + if (src_dat_vld) begin + if (is_last_beat) begin + gnt_count <= 0; + end else begin + gnt_count <= gnt_count + 1; + end + end + end +end +assign is_last_beat = (gnt_count==arb_cmd_beats); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sticky <= 1'b0; + end else begin + if (any_arb_gnt) begin + if (src_dat_vld & is_last_beat) begin + sticky <= 0; + end else begin + sticky <= 1; + end + end else if (src_dat_vld & is_last_beat) begin + sticky <= 0; + end + end +end +assign {mon_arb_cmd_beats_c,arb_cmd_beats} = arb_cmd_size[2:1] + arb_cmd_inc; +assign arb_cmd_size_bit0_NC = arb_cmd_size[0]; +assign all_gnts = (sticky) ? (stick_gnts) : arb_gnts; +assign gnt_busy = sticky || spt_is_busy; +assign arb_reqs = {2'b0,src_cmd_vlds}; +//:for(my $i=0;$i<3;$i++) { +//:print "wire [7:0] wt${i} = client${i}2mcif_wr_wt;\n"; +//:} +//:for(my $i=3;$i<5; $i++) { +//: print("wire [7:0] wt${i} = 0;\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [7:0] wt0 = client02mcif_wr_wt; +wire [7:0] wt1 = client12mcif_wr_wt; +wire [7:0] wt2 = client22mcif_wr_wt; +wire [7:0] wt3 = 0; +wire [7:0] wt4 = 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +write_ig_arb u_write_ig_arb ( + .req0 (arb_reqs[0]) //|< w + ,.req1 (arb_reqs[1]) //|< w + ,.req2 (arb_reqs[2]) //|< w + ,.req3 (arb_reqs[3]) //|< w + ,.req4 (arb_reqs[4]) //|< w + ,.wt0 (wt0[7:0]) //|< w + ,.wt1 (wt1[7:0]) //|< w + ,.wt2 (wt2[7:0]) //|< w + ,.wt3 (wt3[7:0]) //|< w + ,.wt4 (wt4[7:0]) //|< w + ,.gnt_busy (gnt_busy) //|< w + ,.clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.gnt0 (arb_gnts[0]) //|> w + ,.gnt1 (arb_gnts[1]) //|> w + ,.gnt2 (arb_gnts[2]) //|> w +//,.gnt3 (arb_gnts[3]) //|> w +//,.gnt4 (arb_gnts[4]) //|> w + ); +assign any_arb_gnt = |arb_gnts; +// ARB MUX +always @( + all_gnts +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: or src_cmd${i}_pd +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +or src_cmd0_pd + +or src_cmd1_pd + +or src_cmd2_pd + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ) begin +//spyglass disable_block W171 W226 + case (1'b1 ) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: all_gnts[${i}]: arb_cmd_pd = src_cmd${i}_pd; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +all_gnts[0]: arb_cmd_pd = src_cmd0_pd; + +all_gnts[1]: arb_cmd_pd = src_cmd1_pd; + +all_gnts[2]: arb_cmd_pd = src_cmd2_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//VCS coverage off + default : begin +//:my $w = eval(32 +13); +//:print qq( +//:arb_cmd_pd[$w-1:0] = 0; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +arb_cmd_pd[45-1:0] = 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +assign arb_cmd_size = arb_cmd_pd[32 +7:32 +5]; +assign arb_cmd_inc = arb_cmd_pd[32 +10:32 +10]; +always @( + all_gnts +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: or src_dat${i}_pd +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +or src_dat0_pd + +or src_dat1_pd + +or src_dat2_pd + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ) begin +//spyglass disable_block W171 W226 + case (1'b1 ) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: all_gnts[${i}]: arb_dat_pd = src_dat${i}_pd; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +all_gnts[0]: arb_dat_pd = src_dat0_pd; + +all_gnts[1]: arb_dat_pd = src_dat1_pd; + +all_gnts[2]: arb_dat_pd = src_dat2_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//VCS coverage off + default : begin +//:print qq( +//:arb_dat_pd[64:0] = 0; +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +arb_dat_pd[64:0] = 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +//PKT_PACK_WIRE(cvt_write_cmd, pkt_cmd_,arb2spt_cmd_pd) +assign arb2spt_cmd_pd = arb_cmd_pd; +//PKT_PACK_WIRE(cvt_write_data,pkt_dat_,arb2spt_dat_pd) +assign arb2spt_dat_pd = arb_dat_pd; +// arb2spt +assign arb2spt_cmd_valid = any_arb_gnt; +assign arb2spt_dat_valid = src_dat_vld; +assign spt_is_busy = !(arb2spt_cmd_ready & arb2spt_dat_ready); +//======================== +// OBS +//assign obs_bus_mcif_write_ig_arb_gnt_busy = gnt_busy; +endmodule // NV_NVDLA_NOCIF_WRITE_IG_arb +// when use wr_count, should be care full that no -rd_reg and -wr_reg should be used, as -wr_count does not count in the entry in wr|rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dfifo_wr -rd_pipebus dfifo_rd -d 4 -wr_count -rand_none -w 514 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dfifo_wr_count + , dfifo_wr_prdy + , dfifo_wr_pvld + , dfifo_wr_pd + , dfifo_rd_prdy + , dfifo_rd_pvld + , dfifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output [2:0] dfifo_wr_count; +output dfifo_wr_prdy; +input dfifo_wr_pvld; +input [64:0] dfifo_wr_pd; +input dfifo_rd_prdy; +output dfifo_rd_pvld; +output [64:0] dfifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dfifo_wr_busy_int; // copy for internal use +assign dfifo_wr_prdy = !dfifo_wr_busy_int; +assign wr_reserving = dfifo_wr_pvld && !dfifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dfifo_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dfifo_wr_count : (dfifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dfifo_wr_count + 1'd1) : dfifo_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dfifo_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dfifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_busy_int <= 1'b0; + dfifo_wr_count <= 3'd0; + end else begin + dfifo_wr_busy_int <= dfifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dfifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dfifo_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dfifo_wr_pvld +// +// RAM +// +reg [1:0] dfifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dfifo_wr_adr <= dfifo_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] dfifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [64:0] dfifo_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +//:my $w; +//:$w = 64 +2; +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x${w} ram +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x66 ram + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dfifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dfifo_wr_adr ) + , .ra ( dfifo_rd_adr ) + , .dout ( dfifo_rd_pd ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = dfifo_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + dfifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dfifo_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg dfifo_rd_pvld; // data out of fifo is valid +reg dfifo_rd_pvld_int; // internal copy of dfifo_rd_pvld +assign rd_popping = dfifo_rd_pvld_int && dfifo_rd_prdy; +reg [2:0] dfifo_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? dfifo_rd_count : + (dfifo_rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (dfifo_rd_count + 1'd1) : + dfifo_rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +wire rd_count_next_rd_popping_not_0 = rd_count_next_rd_popping != 0; +wire rd_count_next_no_rd_popping_not_0 = rd_count_next_no_rd_popping != 0; +wire rd_count_next_not_0 = rd_popping ? rd_count_next_rd_popping_not_0 : + rd_count_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_count <= 3'd0; + dfifo_rd_pvld <= 1'b0; + dfifo_rd_pvld_int <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + dfifo_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld <= `x_or_0; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld_int <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dfifo_wr_pvld && !dfifo_wr_busy_int) || (dfifo_wr_busy_int != dfifo_wr_busy_next)) || (rd_pushing || rd_popping || (dfifo_rd_pvld && dfifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dfifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo +// +// Flop-Based RAM +// +//:my $w; +//:$w=64 +2; +//:print qq( +//:module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x${w} +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x66 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [64:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [64:0] ram_ff0; +reg [64:0] ram_ff1; +reg [64:0] ram_ff2; +reg [64:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [64:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {64 +2{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,bpt2arb_cmd0_pd + ,bpt2arb_cmd0_valid + ,src_cmd0_rdy + ,bpt2arb_cmd0_ready + ,src_cmd0_pd + ,src_cmd0_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +12:0] bpt2arb_cmd0_pd; +input bpt2arb_cmd0_valid; +input src_cmd0_rdy; +output bpt2arb_cmd0_ready; +output [32 +12:0] src_cmd0_pd; +output src_cmd0_vld; +reg bpt2arb_cmd0_ready; +reg [32 +12:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [32 +12:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32 +12:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [32 +12:0] src_cmd0_pd; +reg src_cmd0_vld; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? bpt2arb_cmd0_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && bpt2arb_cmd0_valid)? bpt2arb_cmd0_pd[32 +12:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + bpt2arb_cmd0_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or src_cmd0_rdy + or p1_pipe_skid_data + ) begin + src_cmd0_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = src_cmd0_rdy; + src_cmd0_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (src_cmd0_vld^src_cmd0_rdy^bpt2arb_cmd0_valid^bpt2arb_cmd0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_9x (nvdla_core_clk, `ASSERT_RESET, (bpt2arb_cmd0_valid && !bpt2arb_cmd0_ready), (bpt2arb_cmd0_valid), (bpt2arb_cmd0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_ARB_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v.vcp new file mode 100644 index 0000000..0fa4a2f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v.vcp @@ -0,0 +1,1011 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,arb2spt_cmd_ready //|< i + ,arb2spt_dat_ready //|< i + ,pwrbus_ram_pd + ,arb2spt_cmd_pd //|> o + ,arb2spt_cmd_valid //|> o + ,arb2spt_dat_pd //|> o + ,arb2spt_dat_valid //|> o +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: ,bpt2arb_cmd${i}_pd +//: ,bpt2arb_cmd${i}_valid +//: ,bpt2arb_cmd${i}_ready +//: ,bpt2arb_dat${i}_pd +//: ,bpt2arb_dat${i}_valid +//: ,bpt2arb_dat${i}_ready +//: ,client${i}2mcif_wr_wt +//:); +//:} +); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:input bpt2arb_cmd${i}_valid; +//:output bpt2arb_cmd${i}_ready; +//:input [32 +12:0] bpt2arb_cmd${i}_pd; +//:input bpt2arb_dat${i}_valid; +//:output bpt2arb_dat${i}_ready; +//:input [64:0] bpt2arb_dat${i}_pd; +//:input [7:0] client${i}2mcif_wr_wt; +//:); +//:} +input nvdla_core_clk; +input nvdla_core_rstn; +output arb2spt_cmd_valid; /* data valid */ +input arb2spt_cmd_ready; /* data return handshake */ +output [32 +12:0] arb2spt_cmd_pd; +output arb2spt_dat_valid; /* data valid */ +input arb2spt_dat_ready; /* data return handshake */ +output [64:0] arb2spt_dat_pd; +input [31:0] pwrbus_ram_pd; +reg [32 +12:0] arb_cmd_pd; +reg [64:0] arb_dat_pd; +reg [1:0] gnt_count; +reg [3 -1:0] stick_gnts; +reg sticky; +wire [3 -1:0] all_gnts; +wire any_arb_gnt; +wire [1:0] arb_cmd_beats; +wire arb_cmd_inc; +wire [2:0] arb_cmd_size; +wire arb_cmd_size_bit0_NC; +wire [3 -1:0] arb_gnts; +wire [4:0] arb_reqs; +wire gnt_busy; +wire is_last_beat; +wire mon_arb_cmd_beats_c; +wire spt_is_busy; +wire [3 -1:0] src_dat_vlds; +wire [3 -1:0] src_dat_gnts; +//NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_${i} ( +// .nvdla_core_clk (nvdla_core_clk) //|< i +// ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +// ,.bpt2arb_cmd0_pd (bpt2arb_cmd${i}_pd[32 +12:0]) //|< i +// ,.bpt2arb_cmd0_valid (bpt2arb_cmd${i}_valid) //|< i +// ,.src_cmd0_rdy (src_cmd${i}_rdy) //|< w +// ,.bpt2arb_cmd0_ready (bpt2arb_cmd${i}_ready) //|> o +// ,.src_cmd0_pd (src_cmd${i}_pd[32 +12:0]) //|> w +// ,.src_cmd0_vld (src_cmd${i}_vld) //|> w +// ); +//&eperl::pipe(" -is -wid $w -do src_cmd${i}_pd -vo src_cmd${i}_vld -ri bpt2arb_cmd${i}_ready -di bpt2arb_cmd${i}_pd -vi bpt2arb_cmd${i}_valid -ro src_cmd${i}_rdy"); +//:my $i; +//:my $w; +//:my $dbus_wid=64; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:wire [2:0] dfifo${i}_wr_count; +//:wire [1:0] src_cmd${i}_beats; +//:wire src_cmd${i}_beats_c; +//:wire src_cmd${i}_camp_vld; +//:wire src_cmd${i}_inc; +//:wire [2:0] src_cmd${i}_size; +//:wire src_cmd${i}_size_bit0_NC; +//:wire [$dbus_wid:0] src_dat${i}_pd; +//:wire [32 +12:0] src_cmd${i}_pd; +//:); +//:$w = eval(32 +13); +//:my $bus_wid = eval(32 +12); +//:print qq( +//:wire src_cmd${i}_rdy, src_cmd${i}_vld; +//:wire src_dat${i}_rdy, src_dat${i}_vld; +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 pipe_p1_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.bpt2arb_cmd0_pd (bpt2arb_cmd${i}_pd[32 +12:0]) //|< i +//: ,.bpt2arb_cmd0_valid (bpt2arb_cmd${i}_valid) //|< i +//: ,.src_cmd0_rdy (src_cmd${i}_rdy) //|< w +//: ,.bpt2arb_cmd0_ready (bpt2arb_cmd${i}_ready) //|> o +//: ,.src_cmd0_pd (src_cmd${i}_pd[32 +12:0]) //|> w +//: ,.src_cmd0_vld (src_cmd${i}_vld) //|> w +//: ); +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo u_dfifo${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.dfifo_wr_count (dfifo${i}_wr_count[2:0]) +//: ,.dfifo_wr_prdy (bpt2arb_dat${i}_ready) +//: ,.dfifo_wr_pvld (bpt2arb_dat${i}_valid) +//: ,.dfifo_wr_pd (bpt2arb_dat${i}_pd) +//: ,.dfifo_rd_prdy (src_dat${i}_rdy) +//: ,.dfifo_rd_pvld (src_dat${i}_vld) +//: ,.dfifo_rd_pd (src_dat${i}_pd) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: ); +//: ); +//:} +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:assign src_cmd${i}_size= {3 {src_cmd${i}_vld}} & src_cmd${i}_pd[32 +7:32 +5]; +//:assign src_cmd${i}_inc = {1{src_cmd${i}_vld}} & src_cmd${i}_pd[32 +10:32 +10]; +//:assign src_cmd${i}_rdy = is_last_beat & src_dat_gnts[${i}]; +//:assign src_dat${i}_rdy = all_gnts[${i}]; +//:assign {src_cmd${i}_beats_c, src_cmd${i}_beats} = src_cmd${i}_size[2:1] + src_cmd${i}_inc; +//:assign src_cmd${i}_size_bit0_NC = src_cmd${i}_size[0]; // bit0 is not used +//:assign src_cmd${i}_camp_vld = src_cmd${i}_vld & (dfifo${i}_wr_count > {src_cmd${i}_beats_c,src_cmd${i}_beats}); +//:); +//:} +wire [3 -1:0] src_cmd_vlds; +assign src_cmd_vlds = { +//:my $i; +//:for($i=3 -1;$i>=1;$i--) { +//:print qq( +//:src_cmd${i}_camp_vld, +//:); +//:} + src_cmd0_camp_vld}; +assign src_dat_vlds = { +//:my $i; +//:for($i=3 -1;$i>=1;$i--) { +//:print qq( +//:src_dat${i}_vld, +//:); +//:} + src_dat0_vld}; +// MUX out based on GNT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stick_gnts <= {3{1'b0}}; + end else begin + if ((any_arb_gnt) == 1'b1) begin + stick_gnts <= arb_gnts; +// VCS coverage off + end else if ((any_arb_gnt) == 1'b0) begin + end else begin + stick_gnts <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +assign src_dat_gnts = all_gnts & src_dat_vlds; +wire src_dat_vld = |src_dat_gnts; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + gnt_count <= {2{1'b0}}; + end else begin + if (src_dat_vld) begin + if (is_last_beat) begin + gnt_count <= 0; + end else begin + gnt_count <= gnt_count + 1; + end + end + end +end +assign is_last_beat = (gnt_count==arb_cmd_beats); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sticky <= 1'b0; + end else begin + if (any_arb_gnt) begin + if (src_dat_vld & is_last_beat) begin + sticky <= 0; + end else begin + sticky <= 1; + end + end else if (src_dat_vld & is_last_beat) begin + sticky <= 0; + end + end +end +assign {mon_arb_cmd_beats_c,arb_cmd_beats} = arb_cmd_size[2:1] + arb_cmd_inc; +assign arb_cmd_size_bit0_NC = arb_cmd_size[0]; +assign all_gnts = (sticky) ? (stick_gnts) : arb_gnts; +assign gnt_busy = sticky || spt_is_busy; +assign arb_reqs = {2'b0,src_cmd_vlds}; +//:for(my $i=0;$i<3;$i++) { +//:print "wire [7:0] wt${i} = client${i}2mcif_wr_wt;\n"; +//:} +//:for(my $i=3;$i<5; $i++) { +//: print("wire [7:0] wt${i} = 0;\n"); +//:} +write_ig_arb u_write_ig_arb ( + .req0 (arb_reqs[0]) //|< w + ,.req1 (arb_reqs[1]) //|< w + ,.req2 (arb_reqs[2]) //|< w + ,.req3 (arb_reqs[3]) //|< w + ,.req4 (arb_reqs[4]) //|< w + ,.wt0 (wt0[7:0]) //|< w + ,.wt1 (wt1[7:0]) //|< w + ,.wt2 (wt2[7:0]) //|< w + ,.wt3 (wt3[7:0]) //|< w + ,.wt4 (wt4[7:0]) //|< w + ,.gnt_busy (gnt_busy) //|< w + ,.clk (nvdla_core_clk) //|< i + ,.reset_ (nvdla_core_rstn) //|< i + ,.gnt0 (arb_gnts[0]) //|> w + ,.gnt1 (arb_gnts[1]) //|> w + ,.gnt2 (arb_gnts[2]) //|> w +//,.gnt3 (arb_gnts[3]) //|> w +//,.gnt4 (arb_gnts[4]) //|> w + ); +assign any_arb_gnt = |arb_gnts; +// ARB MUX +always @( + all_gnts +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: or src_cmd${i}_pd +//:); +//:} + ) begin +//spyglass disable_block W171 W226 + case (1'b1 ) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: all_gnts[${i}]: arb_cmd_pd = src_cmd${i}_pd; +//:); +//:} +//VCS coverage off + default : begin +//:my $w = eval(32 +13); +//:print qq( +//:arb_cmd_pd[$w-1:0] = 0; +//: ); + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +assign arb_cmd_size = arb_cmd_pd[32 +7:32 +5]; +assign arb_cmd_inc = arb_cmd_pd[32 +10:32 +10]; +always @( + all_gnts +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: or src_dat${i}_pd +//:); +//:} + ) begin +//spyglass disable_block W171 W226 + case (1'b1 ) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: all_gnts[${i}]: arb_dat_pd = src_dat${i}_pd; +//:); +//:} +//VCS coverage off + default : begin +//:print qq( +//:arb_dat_pd[64:0] = 0; +//:); + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +//PKT_PACK_WIRE(cvt_write_cmd, pkt_cmd_,arb2spt_cmd_pd) +assign arb2spt_cmd_pd = arb_cmd_pd; +//PKT_PACK_WIRE(cvt_write_data,pkt_dat_,arb2spt_dat_pd) +assign arb2spt_dat_pd = arb_dat_pd; +// arb2spt +assign arb2spt_cmd_valid = any_arb_gnt; +assign arb2spt_dat_valid = src_dat_vld; +assign spt_is_busy = !(arb2spt_cmd_ready & arb2spt_dat_ready); +//======================== +// OBS +//assign obs_bus_mcif_write_ig_arb_gnt_busy = gnt_busy; +endmodule // NV_NVDLA_NOCIF_WRITE_IG_arb +// when use wr_count, should be care full that no -rd_reg and -wr_reg should be used, as -wr_count does not count in the entry in wr|rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dfifo_wr -rd_pipebus dfifo_rd -d 4 -wr_count -rand_none -w 514 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dfifo_wr_count + , dfifo_wr_prdy + , dfifo_wr_pvld + , dfifo_wr_pd + , dfifo_rd_prdy + , dfifo_rd_pvld + , dfifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output [2:0] dfifo_wr_count; +output dfifo_wr_prdy; +input dfifo_wr_pvld; +input [64:0] dfifo_wr_pd; +input dfifo_rd_prdy; +output dfifo_rd_pvld; +output [64:0] dfifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dfifo_wr_busy_int; // copy for internal use +assign dfifo_wr_prdy = !dfifo_wr_busy_int; +assign wr_reserving = dfifo_wr_pvld && !dfifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dfifo_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dfifo_wr_count : (dfifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dfifo_wr_count + 1'd1) : dfifo_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dfifo_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dfifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_busy_int <= 1'b0; + dfifo_wr_count <= 3'd0; + end else begin + dfifo_wr_busy_int <= dfifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dfifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dfifo_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dfifo_wr_pvld +// +// RAM +// +reg [1:0] dfifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dfifo_wr_adr <= dfifo_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] dfifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [64:0] dfifo_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +//:my $w; +//:$w = 64 +2; +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x${w} ram +//:); + ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dfifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dfifo_wr_adr ) + , .ra ( dfifo_rd_adr ) + , .dout ( dfifo_rd_pd ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = dfifo_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + dfifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dfifo_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg dfifo_rd_pvld; // data out of fifo is valid +reg dfifo_rd_pvld_int; // internal copy of dfifo_rd_pvld +assign rd_popping = dfifo_rd_pvld_int && dfifo_rd_prdy; +reg [2:0] dfifo_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? dfifo_rd_count : + (dfifo_rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (dfifo_rd_count + 1'd1) : + dfifo_rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +wire rd_count_next_rd_popping_not_0 = rd_count_next_rd_popping != 0; +wire rd_count_next_no_rd_popping_not_0 = rd_count_next_no_rd_popping != 0; +wire rd_count_next_not_0 = rd_popping ? rd_count_next_rd_popping_not_0 : + rd_count_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_count <= 3'd0; + dfifo_rd_pvld <= 1'b0; + dfifo_rd_pvld_int <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + dfifo_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld <= `x_or_0; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld_int <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dfifo_wr_pvld && !dfifo_wr_busy_int) || (dfifo_wr_busy_int != dfifo_wr_busy_next)) || (rd_pushing || rd_popping || (dfifo_rd_pvld && dfifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dfifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo +// +// Flop-Based RAM +// +//:my $w; +//:$w=64 +2; +//:print qq( +//:module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x${w} +//:); + ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [64:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [64:0] ram_ff0; +reg [64:0] ram_ff1; +reg [64:0] ram_ff2; +reg [64:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [64:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {64 +2{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,bpt2arb_cmd0_pd + ,bpt2arb_cmd0_valid + ,src_cmd0_rdy + ,bpt2arb_cmd0_ready + ,src_cmd0_pd + ,src_cmd0_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +12:0] bpt2arb_cmd0_pd; +input bpt2arb_cmd0_valid; +input src_cmd0_rdy; +output bpt2arb_cmd0_ready; +output [32 +12:0] src_cmd0_pd; +output src_cmd0_vld; +reg bpt2arb_cmd0_ready; +reg [32 +12:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg [32 +12:0] p1_pipe_skid_data; +reg p1_pipe_skid_ready; +reg p1_pipe_skid_valid; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32 +12:0] p1_skid_data; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [32 +12:0] src_cmd0_pd; +reg src_cmd0_vld; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? bpt2arb_cmd0_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && bpt2arb_cmd0_valid)? bpt2arb_cmd0_pd[32 +12:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + bpt2arb_cmd0_ready = p1_pipe_ready_bc; +end +//## pipe (1) skid buffer +always @( + p1_pipe_valid + or p1_skid_ready_flop + or p1_pipe_skid_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_valid && p1_skid_ready_flop && !p1_pipe_skid_ready; + p1_skid_ready = (p1_skid_valid)? p1_pipe_skid_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_pipe_skid_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_valid + or p1_skid_valid + or p1_pipe_data + or p1_skid_data + ) begin + p1_pipe_skid_valid = (p1_skid_ready_flop)? p1_pipe_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_pipe_skid_data = (p1_skid_ready_flop)? p1_pipe_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) output +always @( + p1_pipe_skid_valid + or src_cmd0_rdy + or p1_pipe_skid_data + ) begin + src_cmd0_vld = p1_pipe_skid_valid; + p1_pipe_skid_ready = src_cmd0_rdy; + src_cmd0_pd = p1_pipe_skid_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (src_cmd0_vld^src_cmd0_rdy^bpt2arb_cmd0_valid^bpt2arb_cmd0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_9x (nvdla_core_clk, `ASSERT_RESET, (bpt2arb_cmd0_valid && !bpt2arb_cmd0_ready), (bpt2arb_cmd0_valid), (bpt2arb_cmd0_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_ARB_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v new file mode 100644 index 0000000..e3002d5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v @@ -0,0 +1,1326 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dma2bpt_req_valid //|< i + ,dma2bpt_req_ready //|> o + ,dma2bpt_req_pd //|< i + ,bpt2arb_cmd_valid //|> o + ,bpt2arb_cmd_ready //|< i + ,bpt2arb_cmd_pd //|> o + ,bpt2arb_dat_valid //|> o + ,bpt2arb_dat_ready //|< i + ,bpt2arb_dat_pd //|> o + ,axid //|< i + ); +// +// NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input [3:0] axid; +input dma2bpt_req_valid; +output dma2bpt_req_ready; +input [66 -1:0] dma2bpt_req_pd; +output bpt2arb_cmd_valid; +input bpt2arb_cmd_ready; +output [32 +12:0] bpt2arb_cmd_pd; +output bpt2arb_dat_valid; +input bpt2arb_dat_ready; +output [66 -2:0] bpt2arb_dat_pd; +reg cmd_en; +reg dat_en; +wire [66 -1:0] ipipe_pd; +wire [66 -1:0] ipipe_pd_p; +wire ipipe_rdy; +wire ipipe_rdy_p; +wire ipipe_vld; +wire ipipe_vld_p; +wire [46 -1:0] ipipe_cmd_pd; +wire ipipe_cmd_vld; +wire ipipe_cmd_rdy; +wire [46 -1:0] in_cmd_pd; +wire [46 -1:0] in_cmd_vld_pd; +wire in_cmd_vld; +wire in_cmd_rdy; +wire [32 -1:0] in_cmd_addr; +wire [13 -1:0] in_cmd_size; +wire in_cmd_require_ack; +wire dfifo_wr_idle; +wire [1 -1:0] dfifo_wr_mask; +wire [64 -1:0] dfifo_wr_data; +wire dfifo_wr_prdy; +wire dfifo_wr_pvld; +wire [64 -1:0] dfifo_rd_data; +wire dfifo_rd_pvld; +wire dfifo_rd_prdy; +reg [32 -1:0] out_addr; +wire [2:0] out_size; +reg [13 -1:0] req_num; +reg [13 -1:0] req_count; +reg [2:0] beat_count; +wire [2:0] beat_size; +wire is_last_beat; +wire bpt2arb_cmd_accept; +wire bpt2arb_dat_accept; +wire [2:0] stt_offset; +wire [2:0] size_offset; +wire [2:0] end_offset; +wire [2:0] ftran_size; +wire [2:0] ltran_size; +wire [13 -1:0] mtran_num; +wire in_size_is_even; +wire in_size_is_odd; +wire is_ftran; +wire is_ltran; +wire is_mtran; +wire is_single_tran; +wire is_swizzle; +wire large_req_grow; +wire mon_end_offset_c; +wire [32 -1:0] out_cmd_addr; +wire [3:0] out_cmd_axid; +wire out_cmd_ftran; +wire out_cmd_inc; +wire out_cmd_ltran; +wire out_cmd_odd; +wire out_cmd_require_ack; +wire [2:0] out_cmd_size; +wire out_cmd_swizzle; +wire [2:0] out_cmd_user_size; +wire out_cmd_vld; +wire [64 -1:0] out_dat_data; +wire [1 -1:0] out_dat_mask; +wire out_dat_vld; +//================== +// 1st Stage: REQ PIPE +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma2bpt_req_pd (dma2bpt_req_pd) + ,.dma2bpt_req_valid (dma2bpt_req_valid) //|< i + ,.dma2bpt_req_ready (dma2bpt_req_ready) //|> o + ,.ipipe_pd_p (ipipe_pd_p) + ,.ipipe_vld_p (ipipe_vld_p) //|> w + ,.ipipe_rdy_p (ipipe_rdy_p) //|< w + ); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ipipe_pd_p (ipipe_pd_p) + ,.ipipe_vld_p (ipipe_vld_p) //|< w + ,.ipipe_rdy_p (ipipe_rdy_p) //|> w + ,.ipipe_pd (ipipe_pd) + ,.ipipe_vld (ipipe_vld) //|> w + ,.ipipe_rdy (ipipe_rdy) //|< w + ); +assign ipipe_cmd_vld = ipipe_vld && (ipipe_pd[66 -1]== 0); +assign dfifo_wr_pvld = ipipe_vld && (ipipe_pd[66 -1]== 1); +assign dfifo_wr_data = ipipe_pd[64 -1:0]; +assign dfifo_wr_mask = ipipe_pd[64 +1 -1:64]; +assign ipipe_rdy = (ipipe_cmd_vld & ipipe_cmd_rdy) || (dfifo_wr_pvld & dfifo_wr_prdy); +assign ipipe_cmd_pd[46 -1:0] = ipipe_pd[46 -1:0]; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ipipe_cmd_pd (ipipe_cmd_pd) + ,.ipipe_cmd_vld (ipipe_cmd_vld) //|< w + ,.ipipe_cmd_rdy (ipipe_cmd_rdy) //|> w + ,.in_cmd_pd (in_cmd_pd) + ,.in_cmd_vld (in_cmd_vld) //|> w + ,.in_cmd_rdy (in_cmd_rdy) //|< w + ); +assign in_cmd_rdy = is_ltran & is_last_beat & bpt2arb_dat_accept; +assign in_cmd_vld_pd = {46{in_cmd_vld}} & in_cmd_pd; +assign in_cmd_addr[32 -1:0] = in_cmd_vld_pd[32 -1:0]; +assign in_cmd_size[13 -1:0] = in_cmd_vld_pd[46 -2:32]; +assign in_cmd_require_ack = in_cmd_vld_pd[46 -1]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + wire cond_zzz_assert_always_1x = (in_cmd_addr[3 -1:0] == 0); + nv_assert_always #(0,0,"lower LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dfifo_wr_idle (dfifo_wr_idle) //|> w + ,.dfifo_wr_pvld (dfifo_wr_pvld) //|< w + ,.dfifo_wr_prdy (dfifo_wr_prdy) //|> w + ,.dfifo_wr_pd (dfifo_wr_data) + ,.dfifo_rd_prdy (dfifo_rd_prdy) //|< w + ,.dfifo_rd_pvld (dfifo_rd_pvld) //|> w + ,.dfifo_rd_pd (dfifo_rd_data) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ); +assign dfifo_rd_prdy = dat_en & bpt2arb_dat_ready; +// DATA FIFO read side: valid +assign out_dat_vld = dat_en & dfifo_rd_pvld; +assign out_dat_data = dfifo_rd_data; +assign out_dat_mask = dfifo_rd_pvld; //dfifo_rd_mask; +assign beat_size = out_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (bpt2arb_cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end else if (bpt2arb_dat_accept & is_last_beat) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end + end +end +//================ +// Beat Count: to count data per split req +//================ +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {2{1'b0}}; + end else begin + if (bpt2arb_dat_accept) begin + if (is_last_beat) begin + beat_count <= 0; + end else begin + beat_count <= beat_count + 1; + end + end + end +end +assign is_last_beat = (beat_count==beat_size); +//================ +// bsp out: size: this is in unit of 64B, including masked 32B data +//================ +assign out_size = 3'b0; +/*always @( + is_ftran + or ftran_size + or is_mtran + or is_ltran + or ltran_size + ) begin + out_size = {3{`tick_x_or_0}}; + if (NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) begin + out_size = 0; + end + else if (is_ftran) begin + out_size = ftran_size; + end else if (is_mtran) begin + out_size = 3'd7; + end else if (is_ltran) begin + out_size = ltran_size; + end +end*/ +//================ +// bpt2arb: addr +//================ +always @(posedge nvdla_core_clk) begin + if (bpt2arb_cmd_accept) begin +//if (is_ftran) begin +//if (3 == 3) +// out_addr <= in_cmd_addr + ((1)<<(3)); +//else +// out_addr <= in_cmd_addr + ((ftran_size+1)<<5); +//end else begin +//if (3 == 3) +// out_addr <= out_addr + ((1)<<(3)); +//else +// out_addr <= out_addr + 256; +//end + if (is_ftran) begin + out_addr <= in_cmd_addr + 8; + end else begin + out_addr <= out_addr + 8; + end + end +end +//================ +// tran count +//================ +always @( * +//is_single_tran +//or mtran_num + ) begin +//if (3 == 3) + req_num = in_cmd_size;// + 1; +//else if (is_single_tran) begin +// req_num = 1; +//end else if (mtran_num==0) begin +// req_num = 2; +//end else begin +// req_num = 2 + mtran_num[12:3]; +//end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_count <= {13{1'b0}}; + end else begin + if (bpt2arb_dat_accept & is_last_beat) begin + if (is_ltran) begin + req_count <= 0; + end else begin + req_count <= req_count + 1; + end + end + end +end +assign is_ftran = (req_count==0); +assign is_mtran = (req_count>0 && req_count= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = dfifo_wr_pvld_in && dfifo_wr_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_busy_int <= 1'b0; + dfifo_wr_count <= 1'd0; + end else begin + dfifo_wr_busy_int <= dfifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dfifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dfifo_wr_count <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dfifo_wr_pvld_in +// +// RAM +// +wire rd_popping; +wire ram_we = wr_pushing && (dfifo_wr_count > 1'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && dfifo_wr_pvld; +wire [63:0] dfifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_1x64 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dfifo_wr_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .ra ( (dfifo_wr_count == 0) ? 1'd1 : 1'b0 ) + , .dout ( dfifo_rd_pd_p ) + ); +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg dfifo_rd_prdy_d; // dfifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_prdy_d <= 1'b1; + end else begin + dfifo_rd_prdy_d <= dfifo_rd_prdy; + end +end +wire dfifo_rd_prdy_d_o; // combinatorial rd_busy +reg dfifo_rd_pvld_int; // internal copy of dfifo_rd_pvld +assign dfifo_rd_pvld = dfifo_rd_pvld_int; +wire dfifo_rd_pvld_p; // data out of fifo is valid +reg dfifo_rd_pvld_int_o; // internal copy of dfifo_rd_pvld_o +wire dfifo_rd_pvld_o = dfifo_rd_pvld_int_o; +assign rd_popping = dfifo_rd_pvld_p && !(dfifo_rd_pvld_int_o && !dfifo_rd_prdy_d_o); +reg dfifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire rd_count_p_next_rd_popping = rd_pushing ? dfifo_rd_count_p : + (dfifo_rd_count_p - 1'd1); +wire rd_count_p_next_no_rd_popping = rd_pushing ? (dfifo_rd_count_p + 1'd1) : + dfifo_rd_count_p; +// spyglass enable_block W164a W484 +wire rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign dfifo_rd_pvld_p = dfifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_count_p <= 1'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + dfifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_count_p <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SKID for -rd_busy_reg +// +reg [63:0] dfifo_rd_pd_o; // output data register +wire rd_req_next_o = (dfifo_rd_pvld_p || (dfifo_rd_pvld_int_o && !dfifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_pvld_int_o <= 1'b0; + end else begin + dfifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (dfifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + dfifo_rd_pd_o <= dfifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((dfifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + dfifo_rd_pd_o <= {64{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg [63:0] dfifo_rd_pd; // output data register +reg dfifo_rd_pvld_int_d; // so we can bubble-collapse dfifo_rd_prdy_d +assign dfifo_rd_prdy_d_o = !((dfifo_rd_pvld_o && dfifo_rd_pvld_int_d && !dfifo_rd_prdy_d ) ); +wire rd_req_next = (!dfifo_rd_prdy_d_o ? dfifo_rd_pvld_o : dfifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_pvld_int <= 1'b0; + dfifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !dfifo_rd_pvld_int || dfifo_rd_prdy ) begin + dfifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!dfifo_rd_pvld_int || dfifo_rd_prdy) ) begin + end else begin + dfifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + dfifo_rd_pvld_int_d <= dfifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!dfifo_rd_pvld_int || dfifo_rd_prdy ) ) begin + case (!dfifo_rd_prdy_d_o) + 1'b0: dfifo_rd_pd <= dfifo_rd_pd_p; + 1'b1: dfifo_rd_pd <= dfifo_rd_pd_o; +//VCS coverage off + default: dfifo_rd_pd <= {64{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!dfifo_rd_pvld_int || dfifo_rd_prdy)) ) begin + end else begin + dfifo_rd_pd <= {64{`x_or_0}}; + end +//synopsys translate_on +end +// +// Read-side Idle Calculation +// +wire rd_idle = !dfifo_rd_pvld_int_o && !dfifo_rd_pvld_int && !rd_pushing && dfifo_rd_count_p == 0; +// +// Write-Side Idle Calculation +// +wire dfifo_wr_idle_d0 = !dfifo_wr_pvld_in && rd_idle && !wr_pushing && dfifo_wr_count == 0 +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + && !wr_pause_rand_in + `endif + `endif +// synopsys translate_on +; +wire dfifo_wr_idle = dfifo_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dfifo_wr_pvld_in && !dfifo_wr_busy_int) || (dfifo_wr_busy_int != dfifo_wr_busy_next)) || (rd_pushing || rd_popping || (dfifo_rd_pvld_int && dfifo_rd_prdy_d) || (dfifo_rd_pvld_int_o && dfifo_rd_prdy_d_o)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit : 1'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 1'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 1'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 1'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 1'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( dfifo_wr_pvld && !(!dfifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_in <= 1'b0; + end else begin + wr_pause_rand_in <= wr_pause_rand; + end +end +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {31'd0, (wr_limit_reg == 1'd0) ? 1'd1 : wr_limit_reg} ) + , .curr ( {31'd0, dfifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_1x64 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [63:0] di; +input iwe; +input we; +input [0:0] ra; +output [63:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [63:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +reg [63:0] ram_ff0; +always @( posedge clk_mgated ) begin + if ( we ) begin + ram_ff0 <= di_d; + end +end +reg [63:0] dout; +always @(*) begin + case( ra ) + 1'd0: dout = ram_ff0; + 1'd1: dout = di_d; +//VCS coverage off + default: dout = {64{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_1x64 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v.vcp new file mode 100644 index 0000000..12af1cb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v.vcp @@ -0,0 +1,1212 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dma2bpt_req_valid //|< i + ,dma2bpt_req_ready //|> o + ,dma2bpt_req_pd //|< i + ,bpt2arb_cmd_valid //|> o + ,bpt2arb_cmd_ready //|< i + ,bpt2arb_cmd_pd //|> o + ,bpt2arb_dat_valid //|> o + ,bpt2arb_dat_ready //|< i + ,bpt2arb_dat_pd //|> o + ,axid //|< i + ); +// +// NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input [3:0] axid; +input dma2bpt_req_valid; +output dma2bpt_req_ready; +input [66 -1:0] dma2bpt_req_pd; +output bpt2arb_cmd_valid; +input bpt2arb_cmd_ready; +output [32 +12:0] bpt2arb_cmd_pd; +output bpt2arb_dat_valid; +input bpt2arb_dat_ready; +output [66 -2:0] bpt2arb_dat_pd; +reg cmd_en; +reg dat_en; +wire [66 -1:0] ipipe_pd; +wire [66 -1:0] ipipe_pd_p; +wire ipipe_rdy; +wire ipipe_rdy_p; +wire ipipe_vld; +wire ipipe_vld_p; +wire [46 -1:0] ipipe_cmd_pd; +wire ipipe_cmd_vld; +wire ipipe_cmd_rdy; +wire [46 -1:0] in_cmd_pd; +wire [46 -1:0] in_cmd_vld_pd; +wire in_cmd_vld; +wire in_cmd_rdy; +wire [32 -1:0] in_cmd_addr; +wire [13 -1:0] in_cmd_size; +wire in_cmd_require_ack; +wire dfifo_wr_idle; +wire [1 -1:0] dfifo_wr_mask; +wire [64 -1:0] dfifo_wr_data; +wire dfifo_wr_prdy; +wire dfifo_wr_pvld; +wire [64 -1:0] dfifo_rd_data; +wire dfifo_rd_pvld; +wire dfifo_rd_prdy; +reg [32 -1:0] out_addr; +wire [2:0] out_size; +reg [13 -1:0] req_num; +reg [13 -1:0] req_count; +reg [2:0] beat_count; +wire [2:0] beat_size; +wire is_last_beat; +wire bpt2arb_cmd_accept; +wire bpt2arb_dat_accept; +wire [2:0] stt_offset; +wire [2:0] size_offset; +wire [2:0] end_offset; +wire [2:0] ftran_size; +wire [2:0] ltran_size; +wire [13 -1:0] mtran_num; +wire in_size_is_even; +wire in_size_is_odd; +wire is_ftran; +wire is_ltran; +wire is_mtran; +wire is_single_tran; +wire is_swizzle; +wire large_req_grow; +wire mon_end_offset_c; +wire [32 -1:0] out_cmd_addr; +wire [3:0] out_cmd_axid; +wire out_cmd_ftran; +wire out_cmd_inc; +wire out_cmd_ltran; +wire out_cmd_odd; +wire out_cmd_require_ack; +wire [2:0] out_cmd_size; +wire out_cmd_swizzle; +wire [2:0] out_cmd_user_size; +wire out_cmd_vld; +wire [64 -1:0] out_dat_data; +wire [1 -1:0] out_dat_mask; +wire out_dat_vld; +//================== +// 1st Stage: REQ PIPE +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dma2bpt_req_pd (dma2bpt_req_pd) + ,.dma2bpt_req_valid (dma2bpt_req_valid) //|< i + ,.dma2bpt_req_ready (dma2bpt_req_ready) //|> o + ,.ipipe_pd_p (ipipe_pd_p) + ,.ipipe_vld_p (ipipe_vld_p) //|> w + ,.ipipe_rdy_p (ipipe_rdy_p) //|< w + ); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ipipe_pd_p (ipipe_pd_p) + ,.ipipe_vld_p (ipipe_vld_p) //|< w + ,.ipipe_rdy_p (ipipe_rdy_p) //|> w + ,.ipipe_pd (ipipe_pd) + ,.ipipe_vld (ipipe_vld) //|> w + ,.ipipe_rdy (ipipe_rdy) //|< w + ); +assign ipipe_cmd_vld = ipipe_vld && (ipipe_pd[66 -1]== 0); +assign dfifo_wr_pvld = ipipe_vld && (ipipe_pd[66 -1]== 1); +assign dfifo_wr_data = ipipe_pd[64 -1:0]; +assign dfifo_wr_mask = ipipe_pd[64 +1 -1:64]; +assign ipipe_rdy = (ipipe_cmd_vld & ipipe_cmd_rdy) || (dfifo_wr_pvld & dfifo_wr_prdy); +assign ipipe_cmd_pd[46 -1:0] = ipipe_pd[46 -1:0]; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.ipipe_cmd_pd (ipipe_cmd_pd) + ,.ipipe_cmd_vld (ipipe_cmd_vld) //|< w + ,.ipipe_cmd_rdy (ipipe_cmd_rdy) //|> w + ,.in_cmd_pd (in_cmd_pd) + ,.in_cmd_vld (in_cmd_vld) //|> w + ,.in_cmd_rdy (in_cmd_rdy) //|< w + ); +assign in_cmd_rdy = is_ltran & is_last_beat & bpt2arb_dat_accept; +assign in_cmd_vld_pd = {46{in_cmd_vld}} & in_cmd_pd; +assign in_cmd_addr[32 -1:0] = in_cmd_vld_pd[32 -1:0]; +assign in_cmd_size[13 -1:0] = in_cmd_vld_pd[46 -2:32]; +assign in_cmd_require_ack = in_cmd_vld_pd[46 -1]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + wire cond_zzz_assert_always_1x = (in_cmd_addr[3 -1:0] == 0); + nv_assert_always #(0,0,"lower LSB should always be 0") zzz_assert_always_1x (.clk(nvdla_core_clk), .reset_(`ASSERT_RESET), .test_expr(cond_zzz_assert_always_1x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dfifo_wr_idle (dfifo_wr_idle) //|> w + ,.dfifo_wr_pvld (dfifo_wr_pvld) //|< w + ,.dfifo_wr_prdy (dfifo_wr_prdy) //|> w + ,.dfifo_wr_pd (dfifo_wr_data) + ,.dfifo_rd_prdy (dfifo_rd_prdy) //|< w + ,.dfifo_rd_pvld (dfifo_rd_pvld) //|> w + ,.dfifo_rd_pd (dfifo_rd_data) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ); +assign dfifo_rd_prdy = dat_en & bpt2arb_dat_ready; +// DATA FIFO read side: valid +assign out_dat_vld = dat_en & dfifo_rd_pvld; +assign out_dat_data = dfifo_rd_data; +assign out_dat_mask = dfifo_rd_pvld; //dfifo_rd_mask; +assign beat_size = out_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (bpt2arb_cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end else if (bpt2arb_dat_accept & is_last_beat) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end + end +end +//================ +// Beat Count: to count data per split req +//================ +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {2{1'b0}}; + end else begin + if (bpt2arb_dat_accept) begin + if (is_last_beat) begin + beat_count <= 0; + end else begin + beat_count <= beat_count + 1; + end + end + end +end +assign is_last_beat = (beat_count==beat_size); +//================ +// bsp out: size: this is in unit of 64B, including masked 32B data +//================ +assign out_size = 3'b0; +/*always @( + is_ftran + or ftran_size + or is_mtran + or is_ltran + or ltran_size + ) begin + out_size = {3{`tick_x_or_0}}; + if (NVDLA_MEMORY_ATOMIC_LOG2 == NVDLA_PRIMARY_MEMIF_WIDTH_LOG2) begin + out_size = 0; + end + else if (is_ftran) begin + out_size = ftran_size; + end else if (is_mtran) begin + out_size = 3'd7; + end else if (is_ltran) begin + out_size = ltran_size; + end +end*/ +//================ +// bpt2arb: addr +//================ +always @(posedge nvdla_core_clk) begin + if (bpt2arb_cmd_accept) begin +//if (is_ftran) begin +//if (3 == 3) +// out_addr <= in_cmd_addr + ((1)<<(3)); +//else +// out_addr <= in_cmd_addr + ((ftran_size+1)<<5); +//end else begin +//if (3 == 3) +// out_addr <= out_addr + ((1)<<(3)); +//else +// out_addr <= out_addr + 256; +//end + if (is_ftran) begin + out_addr <= in_cmd_addr + 8; + end else begin + out_addr <= out_addr + 8; + end + end +end +//================ +// tran count +//================ +always @( * +//is_single_tran +//or mtran_num + ) begin +//if (3 == 3) + req_num = in_cmd_size;// + 1; +//else if (is_single_tran) begin +// req_num = 1; +//end else if (mtran_num==0) begin +// req_num = 2; +//end else begin +// req_num = 2 + mtran_num[12:3]; +//end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_count <= {13{1'b0}}; + end else begin + if (bpt2arb_dat_accept & is_last_beat) begin + if (is_ltran) begin + req_count <= 0; + end else begin + req_count <= req_count + 1; + end + end + end +end +assign is_ftran = (req_count==0); +assign is_mtran = (req_count>0 && req_count= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = dfifo_wr_pvld_in && dfifo_wr_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_busy_int <= 1'b0; + dfifo_wr_count <= 1'd0; + end else begin + dfifo_wr_busy_int <= dfifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dfifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dfifo_wr_count <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dfifo_wr_pvld_in +// +// RAM +// +wire rd_popping; +wire ram_we = wr_pushing && (dfifo_wr_count > 1'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && dfifo_wr_pvld; +wire [63:0] dfifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_1x64 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dfifo_wr_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .ra ( (dfifo_wr_count == 0) ? 1'd1 : 1'b0 ) + , .dout ( dfifo_rd_pd_p ) + ); +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg dfifo_rd_prdy_d; // dfifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_prdy_d <= 1'b1; + end else begin + dfifo_rd_prdy_d <= dfifo_rd_prdy; + end +end +wire dfifo_rd_prdy_d_o; // combinatorial rd_busy +reg dfifo_rd_pvld_int; // internal copy of dfifo_rd_pvld +assign dfifo_rd_pvld = dfifo_rd_pvld_int; +wire dfifo_rd_pvld_p; // data out of fifo is valid +reg dfifo_rd_pvld_int_o; // internal copy of dfifo_rd_pvld_o +wire dfifo_rd_pvld_o = dfifo_rd_pvld_int_o; +assign rd_popping = dfifo_rd_pvld_p && !(dfifo_rd_pvld_int_o && !dfifo_rd_prdy_d_o); +reg dfifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire rd_count_p_next_rd_popping = rd_pushing ? dfifo_rd_count_p : + (dfifo_rd_count_p - 1'd1); +wire rd_count_p_next_no_rd_popping = rd_pushing ? (dfifo_rd_count_p + 1'd1) : + dfifo_rd_count_p; +// spyglass enable_block W164a W484 +wire rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign dfifo_rd_pvld_p = dfifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_count_p <= 1'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + dfifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_count_p <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SKID for -rd_busy_reg +// +reg [63:0] dfifo_rd_pd_o; // output data register +wire rd_req_next_o = (dfifo_rd_pvld_p || (dfifo_rd_pvld_int_o && !dfifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_pvld_int_o <= 1'b0; + end else begin + dfifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (dfifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + dfifo_rd_pd_o <= dfifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((dfifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + dfifo_rd_pd_o <= {64{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg [63:0] dfifo_rd_pd; // output data register +reg dfifo_rd_pvld_int_d; // so we can bubble-collapse dfifo_rd_prdy_d +assign dfifo_rd_prdy_d_o = !((dfifo_rd_pvld_o && dfifo_rd_pvld_int_d && !dfifo_rd_prdy_d ) ); +wire rd_req_next = (!dfifo_rd_prdy_d_o ? dfifo_rd_pvld_o : dfifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_pvld_int <= 1'b0; + dfifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !dfifo_rd_pvld_int || dfifo_rd_prdy ) begin + dfifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!dfifo_rd_pvld_int || dfifo_rd_prdy) ) begin + end else begin + dfifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + dfifo_rd_pvld_int_d <= dfifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!dfifo_rd_pvld_int || dfifo_rd_prdy ) ) begin + case (!dfifo_rd_prdy_d_o) + 1'b0: dfifo_rd_pd <= dfifo_rd_pd_p; + 1'b1: dfifo_rd_pd <= dfifo_rd_pd_o; +//VCS coverage off + default: dfifo_rd_pd <= {64{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!dfifo_rd_pvld_int || dfifo_rd_prdy)) ) begin + end else begin + dfifo_rd_pd <= {64{`x_or_0}}; + end +//synopsys translate_on +end +// +// Read-side Idle Calculation +// +wire rd_idle = !dfifo_rd_pvld_int_o && !dfifo_rd_pvld_int && !rd_pushing && dfifo_rd_count_p == 0; +// +// Write-Side Idle Calculation +// +wire dfifo_wr_idle_d0 = !dfifo_wr_pvld_in && rd_idle && !wr_pushing && dfifo_wr_count == 0 +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + && !wr_pause_rand_in + `endif + `endif +// synopsys translate_on +; +wire dfifo_wr_idle = dfifo_wr_idle_d0; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dfifo_wr_pvld_in && !dfifo_wr_busy_int) || (dfifo_wr_busy_int != dfifo_wr_busy_next)) || (rd_pushing || rd_popping || (dfifo_rd_pvld_int && dfifo_rd_prdy_d) || (dfifo_rd_pvld_int_o && dfifo_rd_prdy_d_o)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit : 1'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 1'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 1'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 1'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 1'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( dfifo_wr_pvld && !(!dfifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_in <= 1'b0; + end else begin + wr_pause_rand_in <= wr_pause_rand; + end +end +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {31'd0, (wr_limit_reg == 1'd0) ? 1'd1 : wr_limit_reg} ) + , .curr ( {31'd0, dfifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_1x64 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [63:0] di; +input iwe; +input we; +input [0:0] ra; +output [63:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [63:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +reg [63:0] ram_ff0; +always @( posedge clk_mgated ) begin + if ( we ) begin + ram_ff0 <= di_d; + end +end +reg [63:0] dout; +always @(*) begin + case( ra ) + 1'd0: dout = ram_ff0; + 1'd1: dout = di_d; +//VCS coverage off + default: dout = {64{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_1x64 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v new file mode 100644 index 0000000..4df70c8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v @@ -0,0 +1,1382 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cq_wr_prdy //|< i + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,eg2ig_axi_len //|< i + ,eg2ig_axi_vld //|< i + ,reg2dp_wr_os_cnt //|< i + ,spt2cvt_cmd_pd //|< i + ,spt2cvt_cmd_valid //|< i + ,spt2cvt_dat_pd //|< i + ,spt2cvt_dat_valid //|< i + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,cq_wr_thread_id //|> o + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,spt2cvt_cmd_ready //|> o + ,spt2cvt_dat_ready //|> o + ); +// +// NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input spt2cvt_cmd_valid; /* data valid */ +output spt2cvt_cmd_ready; /* data return handshake */ +input [32 +12:0] spt2cvt_cmd_pd; +input spt2cvt_dat_valid; /* data valid */ +output spt2cvt_dat_ready; /* data return handshake */ +input [64:0] spt2cvt_dat_pd; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [2:0] cq_wr_pd; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +//&Ports /streamid/; //stepheng,remove +input [1:0] eg2ig_axi_len; +input eg2ig_axi_vld; +input [7:0] reg2dp_wr_os_cnt; +reg [1:0] beat_count; +reg [1:0] eg2ig_axi_len_d; +reg eg2ig_axi_vld_d; +reg os_adv; +reg [8:0] os_cnt; +reg [8:0] os_cnt_cur; +reg [10:0] os_cnt_ext; +reg [10:0] os_cnt_mod; +reg [10:0] os_cnt_new; +reg [10:0] os_cnt_nxt; +wire all_downs_rdy; +wire [32 -1:0] axi_addr; +wire [32 +5:0] axi_aw_pd; +wire [3:0] axi_axid; +wire axi_both_rdy; +wire [32 +5:0] axi_cmd_pd; +wire axi_cmd_rdy; +wire axi_cmd_vld; +wire axi_dat_rdy; +wire axi_dat_vld; +wire [64 -1:0] axi_data; +wire axi_last; +wire [1:0] axi_len; +wire [64/8-1:0] axi_strb; +//wire [32 +12:0] axi_w_pd; +wire [7:0] cfg_wr_os_cnt; +wire [32 -1:0] cmd_addr; +wire [3:0] cmd_axid; +wire cmd_ftran; +wire cmd_ftran_NC; +wire cmd_inc; +wire cmd_ltran; +wire cmd_odd; +wire cmd_odd_NC; +wire [32 +12:0] cmd_pd; +wire cmd_rdy; +wire cmd_require_ack; +wire [2:0] cmd_size; +wire cmd_swizzle; +wire cmd_swizzle_NC; +//wire cmd_vld; +wire [32 +12:0] cmd_vld_pd; +wire [1:0] cq_wr_len; +wire cq_wr_require_ack; +wire [64 -1:0] dat_data; +wire dat_mask; +wire [64:0] dat_pd; +wire dat_rdy; +wire dat_vld; +wire [2:0] end_offset; +wire [1:0] end_offset_bit_2_1_NC; +wire is_first_beat; +wire is_first_cmd_dat_vld; +wire is_last_beat; +wire is_single_beat; +wire mon_axi_len_c; +wire mon_end_pos_c; +wire [0:0] mon_thread_id_c; +wire [32 -1:0] opipe_axi_addr; +wire [3:0] opipe_axi_axid; +wire [64 -1:0] opipe_axi_data; +wire opipe_axi_last; +wire [1:0] opipe_axi_len; +wire [64/8-1:0] opipe_axi_strb; +wire os_cmd_vld; +wire [2:0] os_cnt_add; +wire os_cnt_add_en; +wire os_cnt_cen; +wire os_cnt_full; +wire [2:0] os_cnt_sub; +wire os_cnt_sub_en; +wire [2:0] os_inp_add_nxt; +wire [9:0] os_inp_nxt; +wire [2:0] os_inp_sub_nxt; +wire [2:0] stt_offset; +wire [8:0] wr_os_cnt_ext; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// AXI address channel signals +// IG_cvt===flop In first +//&Vector SIG_nvdla_dma_wr_req_pd_WIDTH /wr_req_pd/; +//&eperl::pipe(" -wid 77 -do cmd_pd -vo cmd_vld -ri spt2cvt_cmd_ready -di spt2cvt_cmd_pd -vi spt2cvt_cmd_valid -ro cmd_rdy"); +//IG_cvt===upack : none-flop-in +wire cmd_vld; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_rdy (cmd_rdy) //|< w + ,.spt2cvt_cmd_pd (spt2cvt_cmd_pd[32 +12:0]) //|< i + ,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|< i + ,.cmd_pd (cmd_pd[32 +12:0]) //|> w + ,.cmd_vld (cmd_vld) //|> w + ,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|> o + ); +//my $dw = eval(64 +2); +//&eperl::pipe(" -wid $dw -do dat_pd -vo dat_vld -ri spt2cvt_dat_ready -di spt2cvt_dat_pd -vi spt2cvt_dat_valid -ro dat_rdy"); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dat_rdy (dat_rdy) //|< w + ,.spt2cvt_dat_pd (spt2cvt_dat_pd[64:0]) //|< i + ,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|< i + ,.dat_pd (dat_pd[64:0]) //|> w + ,.dat_vld (dat_vld) //|> w + ,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|> o + ); +assign os_cmd_vld = cmd_vld & !os_cnt_full; +//IG_cvt=== push into the cq on first beat of data +assign dat_rdy = is_first_beat ? (os_cmd_vld & all_downs_rdy) : axi_dat_rdy; +//IG_cvt=== will release cmd on the acception of last beat of data +assign cmd_rdy = is_first_beat & dat_vld & all_downs_rdy & !os_cnt_full; +//IG_cvt===UNPACK after ipipe +assign cmd_vld_pd = {32 +13{cmd_vld}} & cmd_pd; +// PKT_UNPACK_WIRE( cvt_write_cmd , cmd_ , cmd_vld_pd ) +assign cmd_axid[3:0] = cmd_vld_pd[3:0]; +assign cmd_require_ack = cmd_vld_pd[4]; +assign cmd_addr[32 -1:0] = cmd_vld_pd[32 +4:5]; +assign cmd_size[2:0] = cmd_vld_pd[(32 +7):(32 +5)]; +assign cmd_swizzle = cmd_vld_pd[32 +8]; +assign cmd_odd = cmd_vld_pd[32 +9]; +assign cmd_inc = cmd_vld_pd[32 +10]; +assign cmd_ltran = cmd_vld_pd[32 +11]; +assign cmd_ftran = cmd_vld_pd[32 +12]; +assign cmd_ftran_NC = cmd_ftran; +assign cmd_swizzle_NC = cmd_swizzle; +assign cmd_odd_NC = cmd_odd; +// PKT_UNPACK_WIRE( cvt_write_data , dat_ , dat_pd ) +assign dat_data[64 -1:0] = dat_pd[64 -1:0]; +assign dat_mask = dat_pd[64:64]; +// NOTE: this is for write strobe +// IG_cvt===address calculation +assign stt_offset = cmd_addr[7:5]; // start position within a 256B block +//assign is_start_addr_32_align = (stt_offset[0]==1'b1); //stepheng +assign {mon_end_pos_c,end_offset[2:0]} = stt_offset + cmd_size; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CVT:end_offset can not cross 256B boundary, which should be split in IG_SPT") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mon_end_pos_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//assign is_end_addr_64_align = (end_offset[0]==1'b0); //stepheng. +assign end_offset_bit_2_1_NC = end_offset[2:1]; +//============== +// AXI: AXID +//============== +// Gen axi_ signals: size/len/axid/addr +assign axi_axid = cmd_axid[3:0]; +//============== +// AXI: USER: STREAMID +//============== +//assign axi_streamid = falcon2mcif_streamid; //stepheng. +//============== +// AXI: USER: SIZE +//============== +//assign axi_user_size = cmd_user_size; //stepheng +//============== +// AXI: SIZE +//============== +// NOTE: if no STOBE is allowed, will need split into single 32B transaction +//assign is_32_trans = 1'b0 & (is_start_addr_32_align || is_end_addr_64_align); //stepheng. +//assign axi_size = is_32_trans ? AXSIZE_32 : AXSIZE_64; //stepheng. +//============== +// AXI: ADDR +//============== +assign axi_addr = cmd_addr; +// CACHE +//assign axi_cache = (is_last_beat) ? AWCACHE_LAST : AXCACHE; //stepheng. +//========================================================================================= +// NOTICE +// each axi cmd need be sent together with the first beat of data in that transaction, +// and push "ack" into OQ in the same cycle +//========================================================================================= +// beat_count is to count the data per cmd +//============== +// AXI: LEN +//============== +assign {mon_axi_len_c,axi_len[1:0]} = cmd_size[2:1] + cmd_inc; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CVT: we can only send 4 burst at most in one AXI trans") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_axi_len_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign is_first_cmd_dat_vld = os_cmd_vld & dat_vld && is_first_beat; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {2{1'b0}}; + end else begin + if (is_first_cmd_dat_vld && all_downs_rdy) begin + beat_count <= axi_len; + end else if (beat_count!=0 && axi_dat_rdy) begin + beat_count <= beat_count - 1; + end + end +end +assign is_first_beat = (beat_count==0); +//assign is_not_first_beat = (beat_count!=0); +//assign is_not_first_beat_vld = dat_vld && is_not_first_beat; +assign is_single_beat = (axi_len==0); +assign is_last_beat = (beat_count==1 || (beat_count==0 && is_single_beat)); +// IG_cvt===W Channel : DATA +assign axi_data = dat_data; +// IG_cvt===W Channel : LAST +assign axi_last = is_last_beat; +assign axi_strb = {8{dat_mask}}; // {{32{dat_mask[1]}},{32{dat_mask[0]}}}; +//===================================== +// AXI Output Pipe +//===================================== +//stepheng, remove tie off. +//// IG_cvt===AXI OUT TIEOFF +//assign mcif2noc_axi_aw_awburst = AXBURST; +//assign mcif2noc_axi_aw_awlock = AXLOCK; +////assign mcif2noc_axi_aw_awcache = AXCACHE; +//assign mcif2noc_axi_aw_awprot = AXPROT; +//assign mcif2noc_axi_aw_awqos = AXQOS; +//assign mcif2noc_axi_aw_awregion = AXREGION; +assign os_inp_add_nxt[2:0] = cmd_vld ? (axi_len + 1) : 3'd0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg2ig_axi_vld_d <= 1'b0; + end else begin + eg2ig_axi_vld_d <= eg2ig_axi_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg2ig_axi_len_d <= {2{1'b0}}; + end else begin + if ((eg2ig_axi_vld) == 1'b1) begin + eg2ig_axi_len_d <= eg2ig_axi_len; +// VCS coverage off + end else if ((eg2ig_axi_vld) == 1'b0) begin + end else begin + eg2ig_axi_len_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(eg2ig_axi_vld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign os_inp_sub_nxt[2:0] = eg2ig_axi_vld_d ? (eg2ig_axi_len_d+1) : 3'd0; +assign os_inp_nxt[9:0] = os_cnt + os_inp_add_nxt - os_inp_sub_nxt; +// IG_cvt=== 256 outstanding trans +assign os_cnt_add_en = axi_cmd_vld & axi_cmd_rdy; +assign os_cnt_sub_en = eg2ig_axi_vld_d; +assign os_cnt_cen = os_cnt_add_en | os_cnt_sub_en; +assign os_cnt_add = os_cnt_add_en ? (axi_len + 1) : 3'd0; +assign os_cnt_sub = os_cnt_sub_en ? (eg2ig_axi_len_d+1) : 3'd0; +assign cfg_wr_os_cnt = reg2dp_wr_os_cnt[7:0]; +assign wr_os_cnt_ext = {{1{1'b0}}, cfg_wr_os_cnt}; +assign os_cnt_full = os_inp_nxt>(wr_os_cnt_ext+1); +// os adv logic +always @( + os_cnt_add + or os_cnt_sub + ) begin + os_adv = os_cnt_add[2:0] != os_cnt_sub[2:0]; +end +// os cnt logic +always @( + os_cnt_cur + or os_cnt_add + or os_cnt_sub + or os_adv + ) begin +// VCS sop_coverage_off start + os_cnt_ext[10:0] = {1'b0, 1'b0, os_cnt_cur}; + os_cnt_mod[10:0] = os_cnt_cur + os_cnt_add[2:0] - os_cnt_sub[2:0]; // spyglass disable W164b + os_cnt_new[10:0] = (os_adv)? os_cnt_mod[10:0] : os_cnt_ext[10:0]; + os_cnt_nxt[10:0] = os_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// os flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + os_cnt_cur[8:0] <= 0; + end else begin + if (os_cnt_cen) begin + os_cnt_cur[8:0] <= os_cnt_nxt[8:0]; + end + end +end +// os output logic +always @( + os_cnt_cur + ) begin + os_cnt[8:0] = os_cnt_cur[8:0]; +end +// os asserts +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (os_cnt_nxt > 256 && os_cnt_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//IG_cvt=== PIPE for $NOC ADDR Channel +// cmd will be pushed into pipe with the 1st beat of data in that cmd, +// and when *_beat_vld is high, *_cmd_vld should always be there. +// addr+streamid+user_size +//stepheng. +assign axi_cmd_vld = is_first_cmd_dat_vld & cq_wr_prdy & axi_dat_rdy; +//my $w = eval(32 +6); +//&eperl::pipe(" -wid $w -do axi_aw_pd -vo mcif2noc_axi_aw_awvalid -ri axi_cmd_rdy -di axi_cmd_pd -vi axi_cmd_vld -ro mcif2noc_axi_aw_awready"); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.axi_cmd_pd (axi_cmd_pd[32 +5:0]) //|< w + ,.axi_cmd_vld (axi_cmd_vld) //|< w + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.axi_aw_pd (axi_aw_pd[32 +5:0]) //|> w + ,.axi_cmd_rdy (axi_cmd_rdy) //|> w + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ); +//IG_cvt=== PIPE for $NOC DATA Channel +// first beat of data also need cq and cmd rdy, this is because we also need push ack/cmd into cq fifo and cmd pipe on first beat of data +assign axi_dat_vld = dat_vld & (!is_first_beat || (os_cmd_vld & cq_wr_prdy & axi_cmd_rdy)); +//my $dw = eval(64 +64/8+1); +//&eperl::pipe(" -wid $dw -do axi_w_pd -vo mcif2noc_axi_w_wvalid -ri axi_dat_rdy -di axi_dat_pd -vi axi_dat_vld -ro mcif2noc_axi_w_wready"); +wire [64 +64/8+1-1:0] axi_dat_pd, axi_w_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.axi_dat_pd (axi_dat_pd) //|< w + ,.axi_dat_vld (axi_dat_vld) //|< w + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.axi_dat_rdy (axi_dat_rdy) //|> w + ,.axi_w_pd (axi_w_pd) //|> w + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ); +//stepheng,remove user_size & streamid & awcache & size + assign axi_cmd_pd = {axi_axid,axi_addr,axi_len}; +assign {opipe_axi_axid,opipe_axi_addr,opipe_axi_len} = axi_aw_pd; + assign axi_dat_pd = {axi_data,axi_strb,axi_last}; +assign {opipe_axi_data,opipe_axi_strb,opipe_axi_last} = axi_w_pd; +// IG_cvt===AXI OUT ZERO EXT +assign mcif2noc_axi_aw_awid = {{4{1'b0}}, opipe_axi_axid}; +assign mcif2noc_axi_aw_awaddr = opipe_axi_addr; +assign mcif2noc_axi_aw_awlen = {{2{1'b0}}, opipe_axi_len}; //stepheng +//assign mcif2noc_axi_aw_awsize = opipe_axi_size; //stepheng. +//assign mcif2noc_axi_aw_awcache = opipe_axi_cache; //stepheng,remove +assign mcif2noc_axi_w_wlast = opipe_axi_last; +assign mcif2noc_axi_w_wdata = opipe_axi_data; +assign mcif2noc_axi_w_wstrb = opipe_axi_strb; +//stepheng,remove +////IG_cvt===axi trans variables : semi-static +//&Always; +// mcif2noc_axi_aw_awuser[SIG_axi4_aw_awuser_DECL] = {SIG_axi4_aw_awuser_WIDTH{BIT_LOW}}; +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_StreamID_FIELD] = opipe_axi_streamid; +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_user_size_FIELD] = opipe_axi_user_size; +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_vpr_wr_FIELD] = USER_VPR_WR; // vpr_wr +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_wsb_ns_FIELD] = USER_WSB_NS; // wsb_ns +//&End; +//===================================== +// DownStream readiness +//===================================== +assign axi_both_rdy = axi_cmd_rdy & axi_dat_rdy; +assign all_downs_rdy = cq_wr_prdy & axi_both_rdy; +//===================================== +// Outstanding Queue +//===================================== +// IG_cvt===valid for axi_cmd and oq, inter-lock +assign cq_wr_pvld = is_first_cmd_dat_vld & axi_both_rdy & !os_cnt_full; +assign cq_wr_require_ack = cmd_ltran & cmd_require_ack; +assign cq_wr_len = axi_len; +// PKT_PACK_WIRE( mcif_write_ig2eg , cq_wr_ , cq_wr_pd ) +assign cq_wr_pd[0] = cq_wr_require_ack ; +assign cq_wr_pd[2:1] = cq_wr_len[1:0]; +//:my $i; +//:my @dma_index = (0, 1,1, 1,0, 0, 0, 0, 0,0,0,0,0,0,0); +//:my @client_id = (0,1,2,3,4,0,0,0,0,0,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:print qq(assign cq_wr_thread_id = ); +//:for ($i=0;$i<3;$i++) { +//: print qq((cmd_axid == $remap_clientid[$i]) ? $i :); +//:} +//: print qq(0;); +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign cq_wr_thread_id = (cmd_axid == 1) ? 0 :(cmd_axid == 2) ? 1 :(cmd_axid == 3) ? 2 :0; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//assign cq_wr_thread_id = cmd_axid; +//==================================== +// OBS +//==================================== +//assign obs_bus_mcif_write_ig_cvt_axi_cmd_rdy = axi_cmd_rdy; +//assign obs_bus_mcif_write_ig_cvt_axi_cmd_vld = axi_cmd_vld; +//assign obs_bus_mcif_write_ig_cvt_ig2cq_pvld = cq_wr_pvld; +//assign obs_bus_mcif_write_ig_cvt_ig2cq_prdy = cq_wr_prdy; +//assign obs_bus_mcif_write_ig_cvt_ig2cq_require_ack = cq_wr_require_ack; +`ifdef NVDLA_PRINT_AXI +reg [63:0] mon_axi_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mon_axi_count <= 0; + end else begin + mon_axi_count <= mon_axi_count + 1'b1; + end + if (mcif2noc_axi_aw_awvalid & mcif2noc_axi_aw_awready) begin + $display("NVDLA NOCIF_DRAM WRITE ADDR:time=%0d:cycle=%0d:addr=0x%0h:id=%0d:cache=%0d:size=%0d:len=%0d:usid=%0d:usize=%0d",$stime,mon_axi_count,mcif2noc_axi_aw_awaddr,mcif2noc_axi_aw_awid,mcif2noc_axi_aw_awcache,mcif2noc_axi_aw_awsize,mcif2noc_axi_aw_awlen,mcif2noc_axi_aw_awuser[7:0],mcif2noc_axi_aw_awuser[28:26]); + end +end +//always @(posedge nvdla_core_clk) begin +// if (mcif2noc_axi_w_wvalid & mcif2noc_axi_w_wready) begin +// $display("NVDLA NOCIF_DRAM WRITE DATA:time=%0dns:data=%0h;strb=%0h;last=%0d;", $stime, mcif2noc_axi_w_wdata,mcif2noc_axi_w_wstrb,mcif2noc_axi_w_wlast); +// end +//end +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cmd_rdy + ,spt2cvt_cmd_pd + ,spt2cvt_cmd_valid + ,cmd_pd + ,cmd_vld + ,spt2cvt_cmd_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cmd_rdy; +input [32 +12:0] spt2cvt_cmd_pd; +input spt2cvt_cmd_valid; +output [32 +12:0] cmd_pd; +output cmd_vld; +output spt2cvt_cmd_ready; +reg [32 +12:0] cmd_pd; +reg cmd_vld; +reg [32 +12:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg spt2cvt_cmd_ready; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? spt2cvt_cmd_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && spt2cvt_cmd_valid)? spt2cvt_cmd_pd[32 +12:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + spt2cvt_cmd_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or cmd_rdy + or p1_pipe_data + ) begin + cmd_vld = p1_pipe_valid; + p1_pipe_ready = cmd_rdy; + cmd_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cmd_vld^cmd_rdy^spt2cvt_cmd_valid^spt2cvt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (spt2cvt_cmd_valid && !spt2cvt_cmd_ready), (spt2cvt_cmd_valid), (spt2cvt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc dat_pd (dat_vld,dat_rdy) <= spt2cvt_dat_pd[64:0] (spt2cvt_dat_valid,spt2cvt_dat_ready) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dat_rdy + ,spt2cvt_dat_pd + ,spt2cvt_dat_valid + ,dat_pd + ,dat_vld + ,spt2cvt_dat_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dat_rdy; +input [64:0] spt2cvt_dat_pd; +input spt2cvt_dat_valid; +output [64:0] dat_pd; +output dat_vld; +output spt2cvt_dat_ready; +reg [64:0] dat_pd; +reg dat_vld; +reg [64:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg spt2cvt_dat_ready; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? spt2cvt_dat_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && spt2cvt_dat_valid)? spt2cvt_dat_pd[64:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + spt2cvt_dat_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or dat_rdy + or p2_pipe_data + ) begin + dat_vld = p2_pipe_valid; + p2_pipe_ready = dat_rdy; + dat_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (dat_vld^dat_rdy^spt2cvt_dat_valid^spt2cvt_dat_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (spt2cvt_dat_valid && !spt2cvt_dat_ready), (spt2cvt_dat_valid), (spt2cvt_dat_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_CVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc -is axi_aw_pd (mcif2noc_axi_aw_awvalid,mcif2noc_axi_aw_awready) <= axi_cmd_pd[69:0] (axi_cmd_vld,axi_cmd_rdy) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,axi_cmd_pd + ,axi_cmd_vld + ,mcif2noc_axi_aw_awready + ,axi_aw_pd + ,axi_cmd_rdy + ,mcif2noc_axi_aw_awvalid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +5:0] axi_cmd_pd; +input axi_cmd_vld; +input mcif2noc_axi_aw_awready; +output [32 +5:0] axi_aw_pd; +output axi_cmd_rdy; +output mcif2noc_axi_aw_awvalid; +reg [32 +5:0] axi_aw_pd; +reg axi_cmd_rdy; +reg mcif2noc_axi_aw_awvalid; +reg [32 +5:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [32 +5:0] p3_skid_data; +reg [32 +5:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + axi_cmd_vld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = axi_cmd_vld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + axi_cmd_rdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + axi_cmd_rdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? axi_cmd_pd[32 +5:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or axi_cmd_vld + or p3_skid_valid + or axi_cmd_pd + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? axi_cmd_vld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? axi_cmd_pd[32 +5:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or mcif2noc_axi_aw_awready + or p3_pipe_data + ) begin + mcif2noc_axi_aw_awvalid = p3_pipe_valid; + p3_pipe_ready = mcif2noc_axi_aw_awready; + axi_aw_pd = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2noc_axi_aw_awvalid^mcif2noc_axi_aw_awready^axi_cmd_vld^axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (axi_cmd_vld && !axi_cmd_rdy), (axi_cmd_vld), (axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_CVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc -is axi_w_pd (mcif2noc_axi_w_wvalid,mcif2noc_axi_w_wready) <= axi_dat_pd[64 +64/8:0] (axi_dat_vld,axi_dat_rdy) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,axi_dat_pd + ,axi_dat_vld + ,mcif2noc_axi_w_wready + ,axi_dat_rdy + ,axi_w_pd + ,mcif2noc_axi_w_wvalid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [64 +64/8:0] axi_dat_pd; +input axi_dat_vld; +input mcif2noc_axi_w_wready; +output axi_dat_rdy; +output [64 +64/8:0] axi_w_pd; +output mcif2noc_axi_w_wvalid; +reg axi_dat_rdy; +reg [64 +64/8:0] axi_w_pd; +reg mcif2noc_axi_w_wvalid; +reg [64 +64/8:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [64 +64/8:0] p4_skid_data; +reg [64 +64/8:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + axi_dat_vld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = axi_dat_vld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + axi_dat_rdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + axi_dat_rdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? axi_dat_pd[64 +64/8:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or axi_dat_vld + or p4_skid_valid + or axi_dat_pd + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? axi_dat_vld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? axi_dat_pd[64 +64/8:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or mcif2noc_axi_w_wready + or p4_pipe_data + ) begin + mcif2noc_axi_w_wvalid = p4_pipe_valid; + p4_pipe_ready = mcif2noc_axi_w_wready; + axi_w_pd = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2noc_axi_w_wvalid^mcif2noc_axi_w_wready^axi_dat_vld^axi_dat_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (axi_dat_vld && !axi_dat_rdy), (axi_dat_vld), (axi_dat_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_CVT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v.vcp new file mode 100644 index 0000000..35f4814 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v.vcp @@ -0,0 +1,1379 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cq_wr_prdy //|< i + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,eg2ig_axi_len //|< i + ,eg2ig_axi_vld //|< i + ,reg2dp_wr_os_cnt //|< i + ,spt2cvt_cmd_pd //|< i + ,spt2cvt_cmd_valid //|< i + ,spt2cvt_dat_pd //|< i + ,spt2cvt_dat_valid //|< i + ,cq_wr_pd //|> o + ,cq_wr_pvld //|> o + ,cq_wr_thread_id //|> o + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,spt2cvt_cmd_ready //|> o + ,spt2cvt_dat_ready //|> o + ); +// +// NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input spt2cvt_cmd_valid; /* data valid */ +output spt2cvt_cmd_ready; /* data return handshake */ +input [32 +12:0] spt2cvt_cmd_pd; +input spt2cvt_dat_valid; /* data valid */ +output spt2cvt_dat_ready; /* data return handshake */ +input [64:0] spt2cvt_dat_pd; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [2:0] cq_wr_pd; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +//&Ports /streamid/; //stepheng,remove +input [1:0] eg2ig_axi_len; +input eg2ig_axi_vld; +input [7:0] reg2dp_wr_os_cnt; +reg [1:0] beat_count; +reg [1:0] eg2ig_axi_len_d; +reg eg2ig_axi_vld_d; +reg os_adv; +reg [8:0] os_cnt; +reg [8:0] os_cnt_cur; +reg [10:0] os_cnt_ext; +reg [10:0] os_cnt_mod; +reg [10:0] os_cnt_new; +reg [10:0] os_cnt_nxt; +wire all_downs_rdy; +wire [32 -1:0] axi_addr; +wire [32 +5:0] axi_aw_pd; +wire [3:0] axi_axid; +wire axi_both_rdy; +wire [32 +5:0] axi_cmd_pd; +wire axi_cmd_rdy; +wire axi_cmd_vld; +wire axi_dat_rdy; +wire axi_dat_vld; +wire [64 -1:0] axi_data; +wire axi_last; +wire [1:0] axi_len; +wire [64/8-1:0] axi_strb; +//wire [32 +12:0] axi_w_pd; +wire [7:0] cfg_wr_os_cnt; +wire [32 -1:0] cmd_addr; +wire [3:0] cmd_axid; +wire cmd_ftran; +wire cmd_ftran_NC; +wire cmd_inc; +wire cmd_ltran; +wire cmd_odd; +wire cmd_odd_NC; +wire [32 +12:0] cmd_pd; +wire cmd_rdy; +wire cmd_require_ack; +wire [2:0] cmd_size; +wire cmd_swizzle; +wire cmd_swizzle_NC; +//wire cmd_vld; +wire [32 +12:0] cmd_vld_pd; +wire [1:0] cq_wr_len; +wire cq_wr_require_ack; +wire [64 -1:0] dat_data; +wire dat_mask; +wire [64:0] dat_pd; +wire dat_rdy; +wire dat_vld; +wire [2:0] end_offset; +wire [1:0] end_offset_bit_2_1_NC; +wire is_first_beat; +wire is_first_cmd_dat_vld; +wire is_last_beat; +wire is_single_beat; +wire mon_axi_len_c; +wire mon_end_pos_c; +wire [0:0] mon_thread_id_c; +wire [32 -1:0] opipe_axi_addr; +wire [3:0] opipe_axi_axid; +wire [64 -1:0] opipe_axi_data; +wire opipe_axi_last; +wire [1:0] opipe_axi_len; +wire [64/8-1:0] opipe_axi_strb; +wire os_cmd_vld; +wire [2:0] os_cnt_add; +wire os_cnt_add_en; +wire os_cnt_cen; +wire os_cnt_full; +wire [2:0] os_cnt_sub; +wire os_cnt_sub_en; +wire [2:0] os_inp_add_nxt; +wire [9:0] os_inp_nxt; +wire [2:0] os_inp_sub_nxt; +wire [2:0] stt_offset; +wire [8:0] wr_os_cnt_ext; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// AXI address channel signals +// IG_cvt===flop In first +//&Vector SIG_nvdla_dma_wr_req_pd_WIDTH /wr_req_pd/; +//&eperl::pipe(" -wid 77 -do cmd_pd -vo cmd_vld -ri spt2cvt_cmd_ready -di spt2cvt_cmd_pd -vi spt2cvt_cmd_valid -ro cmd_rdy"); +//IG_cvt===upack : none-flop-in +wire cmd_vld; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_rdy (cmd_rdy) //|< w + ,.spt2cvt_cmd_pd (spt2cvt_cmd_pd[32 +12:0]) //|< i + ,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|< i + ,.cmd_pd (cmd_pd[32 +12:0]) //|> w + ,.cmd_vld (cmd_vld) //|> w + ,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|> o + ); +//my $dw = eval(64 +2); +//&eperl::pipe(" -wid $dw -do dat_pd -vo dat_vld -ri spt2cvt_dat_ready -di spt2cvt_dat_pd -vi spt2cvt_dat_valid -ro dat_rdy"); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dat_rdy (dat_rdy) //|< w + ,.spt2cvt_dat_pd (spt2cvt_dat_pd[64:0]) //|< i + ,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|< i + ,.dat_pd (dat_pd[64:0]) //|> w + ,.dat_vld (dat_vld) //|> w + ,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|> o + ); +assign os_cmd_vld = cmd_vld & !os_cnt_full; +//IG_cvt=== push into the cq on first beat of data +assign dat_rdy = is_first_beat ? (os_cmd_vld & all_downs_rdy) : axi_dat_rdy; +//IG_cvt=== will release cmd on the acception of last beat of data +assign cmd_rdy = is_first_beat & dat_vld & all_downs_rdy & !os_cnt_full; +//IG_cvt===UNPACK after ipipe +assign cmd_vld_pd = {32 +13{cmd_vld}} & cmd_pd; +// PKT_UNPACK_WIRE( cvt_write_cmd , cmd_ , cmd_vld_pd ) +assign cmd_axid[3:0] = cmd_vld_pd[3:0]; +assign cmd_require_ack = cmd_vld_pd[4]; +assign cmd_addr[32 -1:0] = cmd_vld_pd[32 +4:5]; +assign cmd_size[2:0] = cmd_vld_pd[(32 +7):(32 +5)]; +assign cmd_swizzle = cmd_vld_pd[32 +8]; +assign cmd_odd = cmd_vld_pd[32 +9]; +assign cmd_inc = cmd_vld_pd[32 +10]; +assign cmd_ltran = cmd_vld_pd[32 +11]; +assign cmd_ftran = cmd_vld_pd[32 +12]; +assign cmd_ftran_NC = cmd_ftran; +assign cmd_swizzle_NC = cmd_swizzle; +assign cmd_odd_NC = cmd_odd; +// PKT_UNPACK_WIRE( cvt_write_data , dat_ , dat_pd ) +assign dat_data[64 -1:0] = dat_pd[64 -1:0]; +assign dat_mask = dat_pd[64:64]; +// NOTE: this is for write strobe +// IG_cvt===address calculation +assign stt_offset = cmd_addr[7:5]; // start position within a 256B block +//assign is_start_addr_32_align = (stt_offset[0]==1'b1); //stepheng +assign {mon_end_pos_c,end_offset[2:0]} = stt_offset + cmd_size; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CVT:end_offset can not cross 256B boundary, which should be split in IG_SPT") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mon_end_pos_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//assign is_end_addr_64_align = (end_offset[0]==1'b0); //stepheng. +assign end_offset_bit_2_1_NC = end_offset[2:1]; +//============== +// AXI: AXID +//============== +// Gen axi_ signals: size/len/axid/addr +assign axi_axid = cmd_axid[3:0]; +//============== +// AXI: USER: STREAMID +//============== +//assign axi_streamid = falcon2mcif_streamid; //stepheng. +//============== +// AXI: USER: SIZE +//============== +//assign axi_user_size = cmd_user_size; //stepheng +//============== +// AXI: SIZE +//============== +// NOTE: if no STOBE is allowed, will need split into single 32B transaction +//assign is_32_trans = 1'b0 & (is_start_addr_32_align || is_end_addr_64_align); //stepheng. +//assign axi_size = is_32_trans ? AXSIZE_32 : AXSIZE_64; //stepheng. +//============== +// AXI: ADDR +//============== +assign axi_addr = cmd_addr; +// CACHE +//assign axi_cache = (is_last_beat) ? AWCACHE_LAST : AXCACHE; //stepheng. +//========================================================================================= +// NOTICE +// each axi cmd need be sent together with the first beat of data in that transaction, +// and push "ack" into OQ in the same cycle +//========================================================================================= +// beat_count is to count the data per cmd +//============== +// AXI: LEN +//============== +assign {mon_axi_len_c,axi_len[1:0]} = cmd_size[2:1] + cmd_inc; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"CVT: we can only send 4 burst at most in one AXI trans") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_axi_len_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign is_first_cmd_dat_vld = os_cmd_vld & dat_vld && is_first_beat; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {2{1'b0}}; + end else begin + if (is_first_cmd_dat_vld && all_downs_rdy) begin + beat_count <= axi_len; + end else if (beat_count!=0 && axi_dat_rdy) begin + beat_count <= beat_count - 1; + end + end +end +assign is_first_beat = (beat_count==0); +//assign is_not_first_beat = (beat_count!=0); +//assign is_not_first_beat_vld = dat_vld && is_not_first_beat; +assign is_single_beat = (axi_len==0); +assign is_last_beat = (beat_count==1 || (beat_count==0 && is_single_beat)); +// IG_cvt===W Channel : DATA +assign axi_data = dat_data; +// IG_cvt===W Channel : LAST +assign axi_last = is_last_beat; +assign axi_strb = {8{dat_mask}}; // {{32{dat_mask[1]}},{32{dat_mask[0]}}}; +//===================================== +// AXI Output Pipe +//===================================== +//stepheng, remove tie off. +//// IG_cvt===AXI OUT TIEOFF +//assign mcif2noc_axi_aw_awburst = AXBURST; +//assign mcif2noc_axi_aw_awlock = AXLOCK; +////assign mcif2noc_axi_aw_awcache = AXCACHE; +//assign mcif2noc_axi_aw_awprot = AXPROT; +//assign mcif2noc_axi_aw_awqos = AXQOS; +//assign mcif2noc_axi_aw_awregion = AXREGION; +assign os_inp_add_nxt[2:0] = cmd_vld ? (axi_len + 1) : 3'd0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg2ig_axi_vld_d <= 1'b0; + end else begin + eg2ig_axi_vld_d <= eg2ig_axi_vld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg2ig_axi_len_d <= {2{1'b0}}; + end else begin + if ((eg2ig_axi_vld) == 1'b1) begin + eg2ig_axi_len_d <= eg2ig_axi_len; +// VCS coverage off + end else if ((eg2ig_axi_vld) == 1'b0) begin + end else begin + eg2ig_axi_len_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(eg2ig_axi_vld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign os_inp_sub_nxt[2:0] = eg2ig_axi_vld_d ? (eg2ig_axi_len_d+1) : 3'd0; +assign os_inp_nxt[9:0] = os_cnt + os_inp_add_nxt - os_inp_sub_nxt; +// IG_cvt=== 256 outstanding trans +assign os_cnt_add_en = axi_cmd_vld & axi_cmd_rdy; +assign os_cnt_sub_en = eg2ig_axi_vld_d; +assign os_cnt_cen = os_cnt_add_en | os_cnt_sub_en; +assign os_cnt_add = os_cnt_add_en ? (axi_len + 1) : 3'd0; +assign os_cnt_sub = os_cnt_sub_en ? (eg2ig_axi_len_d+1) : 3'd0; +assign cfg_wr_os_cnt = reg2dp_wr_os_cnt[7:0]; +assign wr_os_cnt_ext = {{1{1'b0}}, cfg_wr_os_cnt}; +assign os_cnt_full = os_inp_nxt>(wr_os_cnt_ext+1); +// os adv logic +always @( + os_cnt_add + or os_cnt_sub + ) begin + os_adv = os_cnt_add[2:0] != os_cnt_sub[2:0]; +end +// os cnt logic +always @( + os_cnt_cur + or os_cnt_add + or os_cnt_sub + or os_adv + ) begin +// VCS sop_coverage_off start + os_cnt_ext[10:0] = {1'b0, 1'b0, os_cnt_cur}; + os_cnt_mod[10:0] = os_cnt_cur + os_cnt_add[2:0] - os_cnt_sub[2:0]; // spyglass disable W164b + os_cnt_new[10:0] = (os_adv)? os_cnt_mod[10:0] : os_cnt_ext[10:0]; + os_cnt_nxt[10:0] = os_cnt_new[10:0]; +// VCS sop_coverage_off end +end +// os flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + os_cnt_cur[8:0] <= 0; + end else begin + if (os_cnt_cen) begin + os_cnt_cur[8:0] <= os_cnt_nxt[8:0]; + end + end +end +// os output logic +always @( + os_cnt_cur + ) begin + os_cnt[8:0] = os_cnt_cur[8:0]; +end +// os asserts +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"never: counter overflow beyond ") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (os_cnt_nxt > 256 && os_cnt_cen)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//IG_cvt=== PIPE for $NOC ADDR Channel +// cmd will be pushed into pipe with the 1st beat of data in that cmd, +// and when *_beat_vld is high, *_cmd_vld should always be there. +// addr+streamid+user_size +//stepheng. +assign axi_cmd_vld = is_first_cmd_dat_vld & cq_wr_prdy & axi_dat_rdy; +//my $w = eval(32 +6); +//&eperl::pipe(" -wid $w -do axi_aw_pd -vo mcif2noc_axi_aw_awvalid -ri axi_cmd_rdy -di axi_cmd_pd -vi axi_cmd_vld -ro mcif2noc_axi_aw_awready"); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.axi_cmd_pd (axi_cmd_pd[32 +5:0]) //|< w + ,.axi_cmd_vld (axi_cmd_vld) //|< w + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.axi_aw_pd (axi_aw_pd[32 +5:0]) //|> w + ,.axi_cmd_rdy (axi_cmd_rdy) //|> w + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ); +//IG_cvt=== PIPE for $NOC DATA Channel +// first beat of data also need cq and cmd rdy, this is because we also need push ack/cmd into cq fifo and cmd pipe on first beat of data +assign axi_dat_vld = dat_vld & (!is_first_beat || (os_cmd_vld & cq_wr_prdy & axi_cmd_rdy)); +//my $dw = eval(64 +64/8+1); +//&eperl::pipe(" -wid $dw -do axi_w_pd -vo mcif2noc_axi_w_wvalid -ri axi_dat_rdy -di axi_dat_pd -vi axi_dat_vld -ro mcif2noc_axi_w_wready"); +wire [64 +64/8+1-1:0] axi_dat_pd, axi_w_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.axi_dat_pd (axi_dat_pd) //|< w + ,.axi_dat_vld (axi_dat_vld) //|< w + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.axi_dat_rdy (axi_dat_rdy) //|> w + ,.axi_w_pd (axi_w_pd) //|> w + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ); +//stepheng,remove user_size & streamid & awcache & size + assign axi_cmd_pd = {axi_axid,axi_addr,axi_len}; +assign {opipe_axi_axid,opipe_axi_addr,opipe_axi_len} = axi_aw_pd; + assign axi_dat_pd = {axi_data,axi_strb,axi_last}; +assign {opipe_axi_data,opipe_axi_strb,opipe_axi_last} = axi_w_pd; +// IG_cvt===AXI OUT ZERO EXT +assign mcif2noc_axi_aw_awid = {{4{1'b0}}, opipe_axi_axid}; +assign mcif2noc_axi_aw_awaddr = opipe_axi_addr; +assign mcif2noc_axi_aw_awlen = {{2{1'b0}}, opipe_axi_len}; //stepheng +//assign mcif2noc_axi_aw_awsize = opipe_axi_size; //stepheng. +//assign mcif2noc_axi_aw_awcache = opipe_axi_cache; //stepheng,remove +assign mcif2noc_axi_w_wlast = opipe_axi_last; +assign mcif2noc_axi_w_wdata = opipe_axi_data; +assign mcif2noc_axi_w_wstrb = opipe_axi_strb; +//stepheng,remove +////IG_cvt===axi trans variables : semi-static +//&Always; +// mcif2noc_axi_aw_awuser[SIG_axi4_aw_awuser_DECL] = {SIG_axi4_aw_awuser_WIDTH{BIT_LOW}}; +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_StreamID_FIELD] = opipe_axi_streamid; +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_user_size_FIELD] = opipe_axi_user_size; +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_vpr_wr_FIELD] = USER_VPR_WR; // vpr_wr +// mcif2noc_axi_aw_awuser[PKT_awnv_user_t_wsb_ns_FIELD] = USER_WSB_NS; // wsb_ns +//&End; +//===================================== +// DownStream readiness +//===================================== +assign axi_both_rdy = axi_cmd_rdy & axi_dat_rdy; +assign all_downs_rdy = cq_wr_prdy & axi_both_rdy; +//===================================== +// Outstanding Queue +//===================================== +// IG_cvt===valid for axi_cmd and oq, inter-lock +assign cq_wr_pvld = is_first_cmd_dat_vld & axi_both_rdy & !os_cnt_full; +assign cq_wr_require_ack = cmd_ltran & cmd_require_ack; +assign cq_wr_len = axi_len; +// PKT_PACK_WIRE( mcif_write_ig2eg , cq_wr_ , cq_wr_pd ) +assign cq_wr_pd[0] = cq_wr_require_ack ; +assign cq_wr_pd[2:1] = cq_wr_len[1:0]; +//:my $i; +//:my @dma_index = (0, 1,1, 1,0, 0, 0, 0, 0,0,0,0,0,0,0); +//:my @client_id = (0,1,2,3,4,0,0,0,0,0,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:print qq(assign cq_wr_thread_id = ); +//:for ($i=0;$i<3;$i++) { +//: print qq((cmd_axid == $remap_clientid[$i]) ? $i :); +//:} +//: print qq(0;); +//assign cq_wr_thread_id = cmd_axid; +//==================================== +// OBS +//==================================== +//assign obs_bus_mcif_write_ig_cvt_axi_cmd_rdy = axi_cmd_rdy; +//assign obs_bus_mcif_write_ig_cvt_axi_cmd_vld = axi_cmd_vld; +//assign obs_bus_mcif_write_ig_cvt_ig2cq_pvld = cq_wr_pvld; +//assign obs_bus_mcif_write_ig_cvt_ig2cq_prdy = cq_wr_prdy; +//assign obs_bus_mcif_write_ig_cvt_ig2cq_require_ack = cq_wr_require_ack; +`ifdef NVDLA_PRINT_AXI +reg [63:0] mon_axi_count; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mon_axi_count <= 0; + end else begin + mon_axi_count <= mon_axi_count + 1'b1; + end + if (mcif2noc_axi_aw_awvalid & mcif2noc_axi_aw_awready) begin + $display("NVDLA NOCIF_DRAM WRITE ADDR:time=%0d:cycle=%0d:addr=0x%0h:id=%0d:cache=%0d:size=%0d:len=%0d:usid=%0d:usize=%0d",$stime,mon_axi_count,mcif2noc_axi_aw_awaddr,mcif2noc_axi_aw_awid,mcif2noc_axi_aw_awcache,mcif2noc_axi_aw_awsize,mcif2noc_axi_aw_awlen,mcif2noc_axi_aw_awuser[7:0],mcif2noc_axi_aw_awuser[28:26]); + end +end +//always @(posedge nvdla_core_clk) begin +// if (mcif2noc_axi_w_wvalid & mcif2noc_axi_w_wready) begin +// $display("NVDLA NOCIF_DRAM WRITE DATA:time=%0dns:data=%0h;strb=%0h;last=%0d;", $stime, mcif2noc_axi_w_wdata,mcif2noc_axi_w_wstrb,mcif2noc_axi_w_wlast); +// end +//end +`endif +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cmd_rdy + ,spt2cvt_cmd_pd + ,spt2cvt_cmd_valid + ,cmd_pd + ,cmd_vld + ,spt2cvt_cmd_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input cmd_rdy; +input [32 +12:0] spt2cvt_cmd_pd; +input spt2cvt_cmd_valid; +output [32 +12:0] cmd_pd; +output cmd_vld; +output spt2cvt_cmd_ready; +reg [32 +12:0] cmd_pd; +reg cmd_vld; +reg [32 +12:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg spt2cvt_cmd_ready; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? spt2cvt_cmd_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && spt2cvt_cmd_valid)? spt2cvt_cmd_pd[32 +12:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + spt2cvt_cmd_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or cmd_rdy + or p1_pipe_data + ) begin + cmd_vld = p1_pipe_valid; + p1_pipe_ready = cmd_rdy; + cmd_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cmd_vld^cmd_rdy^spt2cvt_cmd_valid^spt2cvt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (spt2cvt_cmd_valid && !spt2cvt_cmd_ready), (spt2cvt_cmd_valid), (spt2cvt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc dat_pd (dat_vld,dat_rdy) <= spt2cvt_dat_pd[64:0] (spt2cvt_dat_valid,spt2cvt_dat_ready) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dat_rdy + ,spt2cvt_dat_pd + ,spt2cvt_dat_valid + ,dat_pd + ,dat_vld + ,spt2cvt_dat_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dat_rdy; +input [64:0] spt2cvt_dat_pd; +input spt2cvt_dat_valid; +output [64:0] dat_pd; +output dat_vld; +output spt2cvt_dat_ready; +reg [64:0] dat_pd; +reg dat_vld; +reg [64:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg spt2cvt_dat_ready; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? spt2cvt_dat_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && spt2cvt_dat_valid)? spt2cvt_dat_pd[64:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + spt2cvt_dat_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or dat_rdy + or p2_pipe_data + ) begin + dat_vld = p2_pipe_valid; + p2_pipe_ready = dat_rdy; + dat_pd = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (dat_vld^dat_rdy^spt2cvt_dat_valid^spt2cvt_dat_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (spt2cvt_dat_valid && !spt2cvt_dat_ready), (spt2cvt_dat_valid), (spt2cvt_dat_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_CVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc -is axi_aw_pd (mcif2noc_axi_aw_awvalid,mcif2noc_axi_aw_awready) <= axi_cmd_pd[69:0] (axi_cmd_vld,axi_cmd_rdy) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,axi_cmd_pd + ,axi_cmd_vld + ,mcif2noc_axi_aw_awready + ,axi_aw_pd + ,axi_cmd_rdy + ,mcif2noc_axi_aw_awvalid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +5:0] axi_cmd_pd; +input axi_cmd_vld; +input mcif2noc_axi_aw_awready; +output [32 +5:0] axi_aw_pd; +output axi_cmd_rdy; +output mcif2noc_axi_aw_awvalid; +reg [32 +5:0] axi_aw_pd; +reg axi_cmd_rdy; +reg mcif2noc_axi_aw_awvalid; +reg [32 +5:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [32 +5:0] p3_skid_data; +reg [32 +5:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + axi_cmd_vld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = axi_cmd_vld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + axi_cmd_rdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + axi_cmd_rdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? axi_cmd_pd[32 +5:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or axi_cmd_vld + or p3_skid_valid + or axi_cmd_pd + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? axi_cmd_vld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? axi_cmd_pd[32 +5:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or mcif2noc_axi_aw_awready + or p3_pipe_data + ) begin + mcif2noc_axi_aw_awvalid = p3_pipe_valid; + p3_pipe_ready = mcif2noc_axi_aw_awready; + axi_aw_pd = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2noc_axi_aw_awvalid^mcif2noc_axi_aw_awready^axi_cmd_vld^axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (axi_cmd_vld && !axi_cmd_rdy), (axi_cmd_vld), (axi_cmd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_CVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc -is axi_w_pd (mcif2noc_axi_w_wvalid,mcif2noc_axi_w_wready) <= axi_dat_pd[64 +64/8:0] (axi_dat_vld,axi_dat_rdy) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,axi_dat_pd + ,axi_dat_vld + ,mcif2noc_axi_w_wready + ,axi_dat_rdy + ,axi_w_pd + ,mcif2noc_axi_w_wvalid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [64 +64/8:0] axi_dat_pd; +input axi_dat_vld; +input mcif2noc_axi_w_wready; +output axi_dat_rdy; +output [64 +64/8:0] axi_w_pd; +output mcif2noc_axi_w_wvalid; +reg axi_dat_rdy; +reg [64 +64/8:0] axi_w_pd; +reg mcif2noc_axi_w_wvalid; +reg [64 +64/8:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [64 +64/8:0] p4_skid_data; +reg [64 +64/8:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + axi_dat_vld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = axi_dat_vld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + axi_dat_rdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + axi_dat_rdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? axi_dat_pd[64 +64/8:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or axi_dat_vld + or p4_skid_valid + or axi_dat_pd + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? axi_dat_vld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? axi_dat_pd[64 +64/8:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or mcif2noc_axi_w_wready + or p4_pipe_data + ) begin + mcif2noc_axi_w_wvalid = p4_pipe_valid; + p4_pipe_ready = mcif2noc_axi_w_wready; + axi_w_pd = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2noc_axi_w_wvalid^mcif2noc_axi_w_wready^axi_dat_vld^axi_dat_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (axi_dat_vld && !axi_dat_rdy), (axi_dat_vld), (axi_dat_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CVIF_WRITE_IG_CVT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v new file mode 100644 index 0000000..c7f1841 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v @@ -0,0 +1,778 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,arb2spt_cmd_valid //|< i + ,arb2spt_cmd_ready //|> o + ,arb2spt_cmd_pd //|< i + ,arb2spt_dat_valid //|< i + ,arb2spt_dat_ready //|> o + ,arb2spt_dat_pd //|< i + ,spt2cvt_cmd_valid //|> o + ,spt2cvt_cmd_ready //|< i + ,spt2cvt_cmd_pd //|> o + ,spt2cvt_dat_valid //|> o + ,spt2cvt_dat_ready //|< i + ,spt2cvt_dat_pd //|> o + ,pwrbus_ram_pd //|< i + ); +// +// NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt_ports.v +// +input nvdla_core_clk; /* arb2spt_cmd, arb2spt_dat, spt2cvt_cmd, spt2cvt_dat */ +input nvdla_core_rstn; /* arb2spt_cmd, arb2spt_dat, spt2cvt_cmd, spt2cvt_dat */ +input arb2spt_cmd_valid; /* data valid */ +output arb2spt_cmd_ready; /* data return handshake */ +input [32 +12:0] arb2spt_cmd_pd; +input arb2spt_dat_valid; /* data valid */ +output arb2spt_dat_ready; /* data return handshake */ +input [64:0] arb2spt_dat_pd; +output spt2cvt_cmd_valid; /* data valid */ +input spt2cvt_cmd_ready; /* data return handshake */ +output [32 +12:0] spt2cvt_cmd_pd; +output spt2cvt_dat_valid; /* data valid */ +input spt2cvt_dat_ready; /* data return handshake */ +output [64:0] spt2cvt_dat_pd; +input [31:0] pwrbus_ram_pd; +wire [2:0] arb2spt_dat_count; +wire [32 -1:0] cvt_cmd_addr; +wire [3:0] cvt_cmd_axid; +wire cvt_cmd_ftran; +wire cvt_cmd_inc; +wire cvt_cmd_ltran; +wire cvt_cmd_odd; +wire cvt_cmd_rdy; +wire cvt_cmd_require_ack; +wire [2:0] cvt_cmd_size; +wire cvt_cmd_swizzle; +wire [64 -1:0] cvt_dat_data; +wire [1 -1:0] cvt_dat_mask; +wire cvt_dat_rdy; +wire [32 -1:0] spt_cmd_addr; +wire [3:0] spt_cmd_axid; +wire spt_cmd_ftran; +wire spt_cmd_inc; +wire spt_cmd_ltran; +wire spt_cmd_odd; +wire [32 +12:0] spt_cmd_pd; +wire spt_cmd_rdy; +wire spt_cmd_require_ack; +wire [2:0] spt_cmd_size; +wire spt_cmd_swizzle; +wire spt_cmd_vld; +wire [64 -1:0] spt_dat_data; +wire [1 -1:0] spt_dat_mask; +wire [64:0] spt_dat_pd; +wire spt_dat_rdy; +wire spt_dat_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// CMD PIPE +NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_cmd_pd (arb2spt_cmd_pd[32 +12:0]) //|< i + ,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|< i + ,.spt_cmd_rdy (spt_cmd_rdy) //|< w + ,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|> o + ,.spt_cmd_pd (spt_cmd_pd[32 +12:0]) //|> w + ,.spt_cmd_vld (spt_cmd_vld) //|> w + ); +//assign mon_spt_cmd_vld = spt_cmd_vld; +// will release the cmd only when last beat in last tran is accepted by CVT +assign spt_cmd_rdy = cvt_cmd_rdy; +// Dat PIPE +assign arb2spt_dat_ready = (arb2spt_dat_count<=1); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dfifo_wr_count (arb2spt_dat_count[2:0]) //|> w + ,.dfifo_wr_pvld (arb2spt_dat_valid) //|< i + ,.dfifo_wr_pd (arb2spt_dat_pd[64:0]) //|< i + ,.dfifo_rd_prdy (spt_dat_rdy) //|< w + ,.dfifo_rd_pvld (spt_dat_vld) //|> w + ,.dfifo_rd_pd (spt_dat_pd[64:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//&Connect dfifo_wr_prdy ; +// first beat of data need be accepted together with cmd, and the rest data will just need accepted alone +assign spt_dat_rdy = cvt_dat_rdy; +//Unpack cmd/data +// PKT_UNPACK_WIRE( cvt_write_cmd , spt_cmd_ , spt_cmd_pd ) +assign spt_cmd_axid[3:0] = spt_cmd_pd[3:0]; +assign spt_cmd_require_ack = spt_cmd_pd[4]; +assign spt_cmd_addr[32 -1:0] = spt_cmd_pd[32 +4:5]; +assign spt_cmd_size[2:0] = spt_cmd_pd[32 +7:32 +5]; +assign spt_cmd_swizzle = spt_cmd_pd[32 +8]; +assign spt_cmd_odd = spt_cmd_pd[32 +9]; +assign spt_cmd_inc = spt_cmd_pd[32 +10]; +assign spt_cmd_ltran = spt_cmd_pd[32 +11]; +assign spt_cmd_ftran = spt_cmd_pd[32 +12]; +// PKT_UNPACK_WIRE( cvt_write_data , spt_dat_ , spt_dat_pd ) +assign spt_dat_data[64 -1:0] = spt_dat_pd[64 -1:0]; +assign spt_dat_mask = spt_dat_pd[64 +1 -1:64]; +//============== +//====OUTPUT==== +//============== +// Ready +assign cvt_cmd_rdy = spt2cvt_cmd_ready; +assign cvt_dat_rdy = spt2cvt_dat_ready; +// CMD/DATA +assign cvt_cmd_addr = spt_cmd_addr; +assign cvt_cmd_size = spt_cmd_size; +assign cvt_cmd_axid = spt_cmd_axid; +assign cvt_cmd_inc = spt_cmd_inc; +assign cvt_cmd_swizzle = spt_cmd_swizzle; +assign cvt_cmd_odd = spt_cmd_odd; +assign cvt_cmd_ftran = spt_cmd_ftran; +assign cvt_cmd_ltran = spt_cmd_ltran; +//assign cvt_cmd_user_size = spt_cmd_user_size; //stepheng +assign cvt_cmd_require_ack = spt_cmd_require_ack & spt_cmd_ltran; +assign spt2cvt_cmd_valid = spt_cmd_vld; +// PKT_PACK_WIRE( cvt_write_cmd , cvt_cmd_ , spt2cvt_cmd_pd ) +assign spt2cvt_cmd_pd[3:0] = cvt_cmd_axid[3:0]; +assign spt2cvt_cmd_pd[4] = cvt_cmd_require_ack ; +assign spt2cvt_cmd_pd[32 +4:5] = cvt_cmd_addr[32 -1:0]; +assign spt2cvt_cmd_pd[32 +7:32 +5] = cvt_cmd_size[2:0]; +assign spt2cvt_cmd_pd[32 +8] = cvt_cmd_swizzle ; +assign spt2cvt_cmd_pd[32 +9] = cvt_cmd_odd ; +assign spt2cvt_cmd_pd[32 +10] = cvt_cmd_inc ; +assign spt2cvt_cmd_pd[32 +11] = cvt_cmd_ltran ; +assign spt2cvt_cmd_pd[32 +12] = cvt_cmd_ftran ; +// TO CVT : data +assign cvt_dat_data = spt_dat_data; +assign cvt_dat_mask = spt_dat_mask; +assign spt2cvt_dat_valid = spt_dat_vld; +// PKT_PACK_WIRE( cvt_write_data , cvt_dat_ , spt2cvt_dat_pd ) +assign spt2cvt_dat_pd[64 -1:0] = cvt_dat_data[64 -1:0]; +assign spt2cvt_dat_pd[64 +1 -1:64] = cvt_dat_mask[1 -1:0]; +endmodule // NV_NVDLA_NOCIF_WRITE_IG_spt +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc spt_cmd_pd (spt_cmd_vld,spt_cmd_rdy) <= arb2spt_cmd_pd[32 +12:0] (arb2spt_cmd_valid,arb2spt_cmd_ready) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,arb2spt_cmd_pd + ,arb2spt_cmd_valid + ,spt_cmd_rdy + ,arb2spt_cmd_ready + ,spt_cmd_pd + ,spt_cmd_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +12:0] arb2spt_cmd_pd; +input arb2spt_cmd_valid; +input spt_cmd_rdy; +output arb2spt_cmd_ready; +output [32 +12:0] spt_cmd_pd; +output spt_cmd_vld; +reg arb2spt_cmd_ready; +reg [32 +12:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg [32 +12:0] spt_cmd_pd; +reg spt_cmd_vld; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? arb2spt_cmd_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && arb2spt_cmd_valid)? arb2spt_cmd_pd[32 +12:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + arb2spt_cmd_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or spt_cmd_rdy + or p1_pipe_data + ) begin + spt_cmd_vld = p1_pipe_valid; + p1_pipe_ready = spt_cmd_rdy; + spt_cmd_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (spt_cmd_vld^spt_cmd_rdy^arb2spt_cmd_valid^arb2spt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (arb2spt_cmd_valid && !arb2spt_cmd_ready), (arb2spt_cmd_valid), (arb2spt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_WRITE_IG_SPT_pipe_p1 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_WRITE_IG_SPT_dfifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dfifo_wr -rd_pipebus dfifo_rd -d 5 -wr_count -no_wr_busy -rand_none -w 514 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dfifo_wr_count + , dfifo_wr_pvld + , dfifo_wr_pd + , dfifo_rd_prdy + , dfifo_rd_pvld + , dfifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output [2:0] dfifo_wr_count; +input dfifo_wr_pvld; +input [64:0] dfifo_wr_pd; +input dfifo_rd_prdy; +output dfifo_rd_pvld; +output [64:0] dfifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +assign wr_reserving = dfifo_wr_pvld; +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dfifo_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dfifo_wr_count : (dfifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dfifo_wr_count + 1'd1) : dfifo_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_count <= 3'd0; + end else begin + if ( wr_reserving ^ wr_popping ) begin + dfifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dfifo_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dfifo_wr_pvld +// +// RAM +// +reg [2:0] dfifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + dfifo_wr_adr <= (dfifo_wr_adr == 3'd4) ? 3'd0 : (dfifo_wr_adr + 1'd1); + end + end +end +// spyglass enable_block W484 +reg [2:0] dfifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [64:0] dfifo_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +//:my $w = eval(64 +2); +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x${w} ram +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x66 ram + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dfifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dfifo_wr_adr ) + , .ra ( dfifo_rd_adr ) + , .dout ( dfifo_rd_pd ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [2:0] rd_adr_next_popping = (dfifo_rd_adr == 3'd4) ? 3'd0 : (dfifo_rd_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + dfifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dfifo_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg dfifo_rd_pvld; // data out of fifo is valid +reg dfifo_rd_pvld_int; // internal copy of dfifo_rd_pvld +assign rd_popping = dfifo_rd_pvld_int && dfifo_rd_prdy; +reg [2:0] dfifo_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? dfifo_rd_count : + (dfifo_rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (dfifo_rd_count + 1'd1) : + dfifo_rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +wire rd_count_next_rd_popping_not_0 = rd_count_next_rd_popping != 0; +wire rd_count_next_no_rd_popping_not_0 = rd_count_next_no_rd_popping != 0; +wire rd_count_next_not_0 = rd_popping ? rd_count_next_rd_popping_not_0 : + rd_count_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_count <= 3'd0; + dfifo_rd_pvld <= 1'b0; + dfifo_rd_pvld_int <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + dfifo_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld <= `x_or_0; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld_int <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || dfifo_wr_pvld) || (rd_pushing || rd_popping || (dfifo_rd_pvld && dfifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( 32'd5 ) + , .curr ( {29'd0, dfifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +nv_assert_fifo #(0, 5, 0, 0, "FIFOGEN_ASSERTION Fifo overflow or underflow") + fifogen_rd_fifo_check ( .clk ( nvdla_core_clk ), + .reset_ ( ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled === 1'bx ? 1'b0 : ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ) ), + .push ( rd_pushing ), + .pop ( rd_popping ) + ); +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo +// +// Flop-Based RAM +// +//:my $w=eval(64 +2); +//:print qq( +//:module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x${w} +//:); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x66 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64:0] di; +input we; +input [2:0] wa; +input [2:0] ra; +output [64:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [64:0] ram_ff0; +reg [64:0] ram_ff1; +reg [64:0] ram_ff2; +reg [64:0] ram_ff3; +reg [64:0] ram_ff4; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end +end +reg [64:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = ram_ff4; +//VCS coverage off + default: dout = {64 +2{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule // NV_NVDLA_NOCIF_WRITE_IG_SPT_dfifo_flopram_rwsa_5xNVDLA_MEMIF_WIDTH+2 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v.vcp new file mode 100644 index 0000000..28044ab --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v.vcp @@ -0,0 +1,768 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,arb2spt_cmd_valid //|< i + ,arb2spt_cmd_ready //|> o + ,arb2spt_cmd_pd //|< i + ,arb2spt_dat_valid //|< i + ,arb2spt_dat_ready //|> o + ,arb2spt_dat_pd //|< i + ,spt2cvt_cmd_valid //|> o + ,spt2cvt_cmd_ready //|< i + ,spt2cvt_cmd_pd //|> o + ,spt2cvt_dat_valid //|> o + ,spt2cvt_dat_ready //|< i + ,spt2cvt_dat_pd //|> o + ,pwrbus_ram_pd //|< i + ); +// +// NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt_ports.v +// +input nvdla_core_clk; /* arb2spt_cmd, arb2spt_dat, spt2cvt_cmd, spt2cvt_dat */ +input nvdla_core_rstn; /* arb2spt_cmd, arb2spt_dat, spt2cvt_cmd, spt2cvt_dat */ +input arb2spt_cmd_valid; /* data valid */ +output arb2spt_cmd_ready; /* data return handshake */ +input [32 +12:0] arb2spt_cmd_pd; +input arb2spt_dat_valid; /* data valid */ +output arb2spt_dat_ready; /* data return handshake */ +input [64:0] arb2spt_dat_pd; +output spt2cvt_cmd_valid; /* data valid */ +input spt2cvt_cmd_ready; /* data return handshake */ +output [32 +12:0] spt2cvt_cmd_pd; +output spt2cvt_dat_valid; /* data valid */ +input spt2cvt_dat_ready; /* data return handshake */ +output [64:0] spt2cvt_dat_pd; +input [31:0] pwrbus_ram_pd; +wire [2:0] arb2spt_dat_count; +wire [32 -1:0] cvt_cmd_addr; +wire [3:0] cvt_cmd_axid; +wire cvt_cmd_ftran; +wire cvt_cmd_inc; +wire cvt_cmd_ltran; +wire cvt_cmd_odd; +wire cvt_cmd_rdy; +wire cvt_cmd_require_ack; +wire [2:0] cvt_cmd_size; +wire cvt_cmd_swizzle; +wire [64 -1:0] cvt_dat_data; +wire [1 -1:0] cvt_dat_mask; +wire cvt_dat_rdy; +wire [32 -1:0] spt_cmd_addr; +wire [3:0] spt_cmd_axid; +wire spt_cmd_ftran; +wire spt_cmd_inc; +wire spt_cmd_ltran; +wire spt_cmd_odd; +wire [32 +12:0] spt_cmd_pd; +wire spt_cmd_rdy; +wire spt_cmd_require_ack; +wire [2:0] spt_cmd_size; +wire spt_cmd_swizzle; +wire spt_cmd_vld; +wire [64 -1:0] spt_dat_data; +wire [1 -1:0] spt_dat_mask; +wire [64:0] spt_dat_pd; +wire spt_dat_rdy; +wire spt_dat_vld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +// CMD PIPE +NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_cmd_pd (arb2spt_cmd_pd[32 +12:0]) //|< i + ,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|< i + ,.spt_cmd_rdy (spt_cmd_rdy) //|< w + ,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|> o + ,.spt_cmd_pd (spt_cmd_pd[32 +12:0]) //|> w + ,.spt_cmd_vld (spt_cmd_vld) //|> w + ); +//assign mon_spt_cmd_vld = spt_cmd_vld; +// will release the cmd only when last beat in last tran is accepted by CVT +assign spt_cmd_rdy = cvt_cmd_rdy; +// Dat PIPE +assign arb2spt_dat_ready = (arb2spt_dat_count<=1); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dfifo_wr_count (arb2spt_dat_count[2:0]) //|> w + ,.dfifo_wr_pvld (arb2spt_dat_valid) //|< i + ,.dfifo_wr_pd (arb2spt_dat_pd[64:0]) //|< i + ,.dfifo_rd_prdy (spt_dat_rdy) //|< w + ,.dfifo_rd_pvld (spt_dat_vld) //|> w + ,.dfifo_rd_pd (spt_dat_pd[64:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//&Connect dfifo_wr_prdy ; +// first beat of data need be accepted together with cmd, and the rest data will just need accepted alone +assign spt_dat_rdy = cvt_dat_rdy; +//Unpack cmd/data +// PKT_UNPACK_WIRE( cvt_write_cmd , spt_cmd_ , spt_cmd_pd ) +assign spt_cmd_axid[3:0] = spt_cmd_pd[3:0]; +assign spt_cmd_require_ack = spt_cmd_pd[4]; +assign spt_cmd_addr[32 -1:0] = spt_cmd_pd[32 +4:5]; +assign spt_cmd_size[2:0] = spt_cmd_pd[32 +7:32 +5]; +assign spt_cmd_swizzle = spt_cmd_pd[32 +8]; +assign spt_cmd_odd = spt_cmd_pd[32 +9]; +assign spt_cmd_inc = spt_cmd_pd[32 +10]; +assign spt_cmd_ltran = spt_cmd_pd[32 +11]; +assign spt_cmd_ftran = spt_cmd_pd[32 +12]; +// PKT_UNPACK_WIRE( cvt_write_data , spt_dat_ , spt_dat_pd ) +assign spt_dat_data[64 -1:0] = spt_dat_pd[64 -1:0]; +assign spt_dat_mask = spt_dat_pd[64 +1 -1:64]; +//============== +//====OUTPUT==== +//============== +// Ready +assign cvt_cmd_rdy = spt2cvt_cmd_ready; +assign cvt_dat_rdy = spt2cvt_dat_ready; +// CMD/DATA +assign cvt_cmd_addr = spt_cmd_addr; +assign cvt_cmd_size = spt_cmd_size; +assign cvt_cmd_axid = spt_cmd_axid; +assign cvt_cmd_inc = spt_cmd_inc; +assign cvt_cmd_swizzle = spt_cmd_swizzle; +assign cvt_cmd_odd = spt_cmd_odd; +assign cvt_cmd_ftran = spt_cmd_ftran; +assign cvt_cmd_ltran = spt_cmd_ltran; +//assign cvt_cmd_user_size = spt_cmd_user_size; //stepheng +assign cvt_cmd_require_ack = spt_cmd_require_ack & spt_cmd_ltran; +assign spt2cvt_cmd_valid = spt_cmd_vld; +// PKT_PACK_WIRE( cvt_write_cmd , cvt_cmd_ , spt2cvt_cmd_pd ) +assign spt2cvt_cmd_pd[3:0] = cvt_cmd_axid[3:0]; +assign spt2cvt_cmd_pd[4] = cvt_cmd_require_ack ; +assign spt2cvt_cmd_pd[32 +4:5] = cvt_cmd_addr[32 -1:0]; +assign spt2cvt_cmd_pd[32 +7:32 +5] = cvt_cmd_size[2:0]; +assign spt2cvt_cmd_pd[32 +8] = cvt_cmd_swizzle ; +assign spt2cvt_cmd_pd[32 +9] = cvt_cmd_odd ; +assign spt2cvt_cmd_pd[32 +10] = cvt_cmd_inc ; +assign spt2cvt_cmd_pd[32 +11] = cvt_cmd_ltran ; +assign spt2cvt_cmd_pd[32 +12] = cvt_cmd_ftran ; +// TO CVT : data +assign cvt_dat_data = spt_dat_data; +assign cvt_dat_mask = spt_dat_mask; +assign spt2cvt_dat_valid = spt_dat_vld; +// PKT_PACK_WIRE( cvt_write_data , cvt_dat_ , spt2cvt_dat_pd ) +assign spt2cvt_dat_pd[64 -1:0] = cvt_dat_data[64 -1:0]; +assign spt2cvt_dat_pd[64 +1 -1:64] = cvt_dat_mask[1 -1:0]; +endmodule // NV_NVDLA_NOCIF_WRITE_IG_spt +// ************************************************************************************************************** +// Generated by ::pipe -m -rand none -bc spt_cmd_pd (spt_cmd_vld,spt_cmd_rdy) <= arb2spt_cmd_pd[32 +12:0] (arb2spt_cmd_valid,arb2spt_cmd_ready) +// ************************************************************************************************************** +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,arb2spt_cmd_pd + ,arb2spt_cmd_valid + ,spt_cmd_rdy + ,arb2spt_cmd_ready + ,spt_cmd_pd + ,spt_cmd_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32 +12:0] arb2spt_cmd_pd; +input arb2spt_cmd_valid; +input spt_cmd_rdy; +output arb2spt_cmd_ready; +output [32 +12:0] spt_cmd_pd; +output spt_cmd_vld; +reg arb2spt_cmd_ready; +reg [32 +12:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg [32 +12:0] spt_cmd_pd; +reg spt_cmd_vld; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? arb2spt_cmd_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && arb2spt_cmd_valid)? arb2spt_cmd_pd[32 +12:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + arb2spt_cmd_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or spt_cmd_rdy + or p1_pipe_data + ) begin + spt_cmd_vld = p1_pipe_valid; + p1_pipe_ready = spt_cmd_rdy; + spt_cmd_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (spt_cmd_vld^spt_cmd_rdy^arb2spt_cmd_valid^arb2spt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (arb2spt_cmd_valid && !arb2spt_cmd_ready), (arb2spt_cmd_valid), (arb2spt_cmd_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_NOCIF_WRITE_IG_SPT_pipe_p1 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_NOCIF_WRITE_IG_SPT_dfifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dfifo_wr -rd_pipebus dfifo_rd -d 5 -wr_count -no_wr_busy -rand_none -w 514 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dfifo_wr_count + , dfifo_wr_pvld + , dfifo_wr_pd + , dfifo_rd_prdy + , dfifo_rd_pvld + , dfifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output [2:0] dfifo_wr_count; +input dfifo_wr_pvld; +input [64:0] dfifo_wr_pd; +input dfifo_rd_prdy; +output dfifo_rd_pvld; +output [64:0] dfifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +assign wr_reserving = dfifo_wr_pvld; +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dfifo_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dfifo_wr_count : (dfifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dfifo_wr_count + 1'd1) : dfifo_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_count <= 3'd0; + end else begin + if ( wr_reserving ^ wr_popping ) begin + dfifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dfifo_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dfifo_wr_pvld +// +// RAM +// +reg [2:0] dfifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_wr_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + dfifo_wr_adr <= (dfifo_wr_adr == 3'd4) ? 3'd0 : (dfifo_wr_adr + 1'd1); + end + end +end +// spyglass enable_block W484 +reg [2:0] dfifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [64:0] dfifo_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +//:my $w = eval(64 +2); +//:print qq( +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x${w} ram +//:); + ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dfifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dfifo_wr_adr ) + , .ra ( dfifo_rd_adr ) + , .dout ( dfifo_rd_pd ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [2:0] rd_adr_next_popping = (dfifo_rd_adr == 3'd4) ? 3'd0 : (dfifo_rd_adr + 1'd1); // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + dfifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dfifo_rd_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg dfifo_rd_pvld; // data out of fifo is valid +reg dfifo_rd_pvld_int; // internal copy of dfifo_rd_pvld +assign rd_popping = dfifo_rd_pvld_int && dfifo_rd_prdy; +reg [2:0] dfifo_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? dfifo_rd_count : + (dfifo_rd_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (dfifo_rd_count + 1'd1) : + dfifo_rd_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +wire rd_count_next_rd_popping_not_0 = rd_count_next_rd_popping != 0; +wire rd_count_next_no_rd_popping_not_0 = rd_count_next_no_rd_popping != 0; +wire rd_count_next_not_0 = rd_popping ? rd_count_next_rd_popping_not_0 : + rd_count_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dfifo_rd_count <= 3'd0; + dfifo_rd_pvld <= 1'b0; + dfifo_rd_pvld_int <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + dfifo_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_count <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld <= `x_or_0; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + dfifo_rd_pvld_int <= (rd_count_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dfifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || dfifo_wr_pvld) || (rd_pushing || rd_popping || (dfifo_rd_pvld && dfifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( 32'd5 ) + , .curr ( {29'd0, dfifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +nv_assert_fifo #(0, 5, 0, 0, "FIFOGEN_ASSERTION Fifo overflow or underflow") + fifogen_rd_fifo_check ( .clk ( nvdla_core_clk ), + .reset_ ( ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled === 1'bx ? 1'b0 : ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ) ), + .push ( rd_pushing ), + .pop ( rd_popping ) + ); +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo +// +// Flop-Based RAM +// +//:my $w=eval(64 +2); +//:print qq( +//:module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x${w} +//:); + ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [64:0] di; +input we; +input [2:0] wa; +input [2:0] ra; +output [64:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [64:0] ram_ff0; +reg [64:0] ram_ff1; +reg [64:0] ram_ff2; +reg [64:0] ram_ff3; +reg [64:0] ram_ff4; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end +end +reg [64:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = ram_ff4; +//VCS coverage off + default: dout = {64 +2{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule // NV_NVDLA_NOCIF_WRITE_IG_SPT_dfifo_flopram_rwsa_5xNVDLA_MEMIF_WIDTH+2 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v new file mode 100644 index 0000000..5d67bc3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v @@ -0,0 +1,3272 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_cq.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_cq ( + nvdla_core_clk + , nvdla_core_rstn + , cq_wr_prdy + , cq_wr_pvld + , cq_wr_thread_id +`ifdef FV_RAND_WR_PAUSE + , cq_wr_pause +`endif + , cq_wr_pd + , cq_rd0_prdy + , cq_rd0_pvld + , cq_rd0_pd + , cq_rd1_prdy + , cq_rd1_pvld + , cq_rd1_pd + , cq_rd2_prdy + , cq_rd2_pvld + , cq_rd2_pd + , cq_rd3_prdy + , cq_rd3_pvld + , cq_rd3_pd + , cq_rd4_prdy + , cq_rd4_pvld + , cq_rd4_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cq_wr_prdy; +input cq_wr_pvld; +input [2:0] cq_wr_thread_id; +`ifdef FV_RAND_WR_PAUSE +input cq_wr_pause; +`endif +input [2:0] cq_wr_pd; +input cq_rd0_prdy; +output cq_rd0_pvld; +output [2:0] cq_rd0_pd; +input cq_rd1_prdy; +output cq_rd1_pvld; +output [2:0] cq_rd1_pd; +input cq_rd2_prdy; +output cq_rd2_pvld; +output [2:0] cq_rd2_pd; +input cq_rd3_prdy; +output cq_rd3_pvld; +output [2:0] cq_rd3_pd; +input cq_rd4_prdy; +output cq_rd4_pvld; +output [2:0] cq_rd4_pd; +input [31:0] pwrbus_ram_pd; +// -rd_take_to_rd_busy internal credit/take/data signals (which would have been ports) +// +//wire [4:0] cq_rd_credit; +wire cq_rd_take; +wire [2:0] cq_rd_pd_p; +wire [2:0] cq_rd_take_thread_id; +// We also declare some per-thread flags that indicate whether to have the write bypass the internal fifo. +// These per-class wr_bypassing* flags are set by the take-side logic. We basically pretend that we never pushed the fifo, +// but make sure we return a credit to the sender. +// +wire wr_bypassing; // any thread bypassed +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_skid; +wire nvdla_core_clk_mgated_skid_enable; +NV_CLK_gate_power nvdla_core_clk_rd_mgate_skid( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_skid_enable), .clk_gated(nvdla_core_clk_mgated_skid) ); +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cq_wr_busy_int; // copy for internal use +assign cq_wr_prdy = !cq_wr_busy_int; +assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [8:0] cq_wr_count; // write-side count +wire wr_reserving_and_not_bypassing = wr_reserving && !wr_bypassing; +wire [8:0] wr_count_next_wr_popping = wr_reserving_and_not_bypassing ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [8:0] wr_count_next_no_wr_popping = wr_reserving_and_not_bypassing ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484 +wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 ); +wire wr_count_next_is_256 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_256; +wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [8:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || cq_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_busy_int <= 1'b0; + cq_wr_count <= 9'd0; + end else begin + cq_wr_busy_int <= cq_wr_busy_next; + if ( wr_reserving_and_not_bypassing ^ wr_popping ) begin + cq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving_and_not_bypassing ^ wr_popping) ) begin + end else begin + cq_wr_count <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving && !wr_bypassing; // data pushed same cycle as cq_wr_pvld +wire [2:0] wr_pushing_thread_id = cq_wr_thread_id; // thread being written +// +// RAM +// +wire wr_adr_popping = wr_pushing; // pop free list when wr_pushing=1 +wire [7:0] cq_wr_adr; // current write address +reg [7:0] cq_rd_adr; +wire [7:0] cq_rd_adr_p = cq_rd_adr; // read address to use for ram +wire rd_enable; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rws_256x3 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( cq_wr_adr ) + , .we ( wr_pushing ) + , .di ( cq_wr_pd ) + , .ra ( cq_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( cq_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +// +// SYNCHRONOUS BOUNDARY +// +wire rd_pushing = wr_pushing; // let it be seen immediately +wire [2:0] rd_pushing_thread_id = wr_pushing_thread_id; +wire [7:0] rd_pushing_adr = cq_wr_adr; +// +// MULTITHREADED FREE LIST FIFO +// +// free list of cq_wr_adr's from read side to write side +// these are passed in a ff fifo when the fifo is popped +// +// there's an extra mux of the internal flops that is +// used to determine which address to use when +// rd_pushing is 1 if the fifo is async. +// +wire [7:0] rd_popping_adr; // cq_rd_adr to free up +wire [7:0] free_adr_index; +reg [255-1:0] free_adr_mask_next; +reg [255-1:0] free_adr_mask; +assign cq_wr_adr = free_adr_index; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + free_adr_mask <= {255{1'b1}}; + end else begin + if ( rd_popping || wr_adr_popping ) begin + free_adr_mask <= free_adr_mask_next; + end +//synopsys translate_off + else if ( !(rd_popping || wr_adr_popping) ) begin + end else begin + free_adr_mask <= {255{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(*) begin + free_adr_mask_next = free_adr_mask; + if ( rd_popping && rd_popping_adr == 8'd0 ) begin + free_adr_mask_next[0] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd0 ) begin + free_adr_mask_next[0] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd1 ) begin + free_adr_mask_next[1] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd1 ) begin + free_adr_mask_next[1] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd2 ) begin + free_adr_mask_next[2] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd2 ) begin + free_adr_mask_next[2] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd3 ) begin + free_adr_mask_next[3] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd3 ) begin + free_adr_mask_next[3] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd4 ) begin + free_adr_mask_next[4] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd4 ) begin + free_adr_mask_next[4] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd5 ) begin + free_adr_mask_next[5] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd5 ) begin + free_adr_mask_next[5] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd6 ) begin + free_adr_mask_next[6] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd6 ) begin + free_adr_mask_next[6] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd7 ) begin + free_adr_mask_next[7] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd7 ) begin + free_adr_mask_next[7] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd8 ) begin + free_adr_mask_next[8] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd8 ) begin + free_adr_mask_next[8] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd9 ) begin + free_adr_mask_next[9] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd9 ) begin + free_adr_mask_next[9] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd10 ) begin + free_adr_mask_next[10] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd10 ) begin + free_adr_mask_next[10] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd11 ) begin + free_adr_mask_next[11] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd11 ) begin + free_adr_mask_next[11] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd12 ) begin + free_adr_mask_next[12] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd12 ) begin + free_adr_mask_next[12] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd13 ) begin + free_adr_mask_next[13] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd13 ) begin + free_adr_mask_next[13] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd14 ) begin + free_adr_mask_next[14] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd14 ) begin + free_adr_mask_next[14] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd15 ) begin + free_adr_mask_next[15] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd15 ) begin + free_adr_mask_next[15] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd16 ) begin + free_adr_mask_next[16] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd16 ) begin + free_adr_mask_next[16] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd17 ) begin + free_adr_mask_next[17] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd17 ) begin + free_adr_mask_next[17] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd18 ) begin + free_adr_mask_next[18] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd18 ) begin + free_adr_mask_next[18] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd19 ) begin + free_adr_mask_next[19] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd19 ) begin + free_adr_mask_next[19] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd20 ) begin + free_adr_mask_next[20] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd20 ) begin + free_adr_mask_next[20] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd21 ) begin + free_adr_mask_next[21] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd21 ) begin + free_adr_mask_next[21] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd22 ) begin + free_adr_mask_next[22] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd22 ) begin + free_adr_mask_next[22] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd23 ) begin + free_adr_mask_next[23] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd23 ) begin + free_adr_mask_next[23] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd24 ) begin + free_adr_mask_next[24] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd24 ) begin + free_adr_mask_next[24] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd25 ) begin + free_adr_mask_next[25] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd25 ) begin + free_adr_mask_next[25] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd26 ) begin + free_adr_mask_next[26] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd26 ) begin + free_adr_mask_next[26] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd27 ) begin + free_adr_mask_next[27] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd27 ) begin + free_adr_mask_next[27] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd28 ) begin + free_adr_mask_next[28] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd28 ) begin + free_adr_mask_next[28] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd29 ) begin + free_adr_mask_next[29] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd29 ) begin + free_adr_mask_next[29] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd30 ) begin + free_adr_mask_next[30] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd30 ) begin + free_adr_mask_next[30] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd31 ) begin + free_adr_mask_next[31] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd31 ) begin + free_adr_mask_next[31] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd32 ) begin + free_adr_mask_next[32] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd32 ) begin + free_adr_mask_next[32] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd33 ) begin + free_adr_mask_next[33] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd33 ) begin + free_adr_mask_next[33] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd34 ) begin + free_adr_mask_next[34] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd34 ) begin + free_adr_mask_next[34] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd35 ) begin + free_adr_mask_next[35] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd35 ) begin + free_adr_mask_next[35] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd36 ) begin + free_adr_mask_next[36] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd36 ) begin + free_adr_mask_next[36] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd37 ) begin + free_adr_mask_next[37] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd37 ) begin + free_adr_mask_next[37] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd38 ) begin + free_adr_mask_next[38] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd38 ) begin + free_adr_mask_next[38] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd39 ) begin + free_adr_mask_next[39] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd39 ) begin + free_adr_mask_next[39] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd40 ) begin + free_adr_mask_next[40] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd40 ) begin + free_adr_mask_next[40] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd41 ) begin + free_adr_mask_next[41] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd41 ) begin + free_adr_mask_next[41] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd42 ) begin + free_adr_mask_next[42] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd42 ) begin + free_adr_mask_next[42] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd43 ) begin + free_adr_mask_next[43] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd43 ) begin + free_adr_mask_next[43] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd44 ) begin + free_adr_mask_next[44] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd44 ) begin + free_adr_mask_next[44] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd45 ) begin + free_adr_mask_next[45] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd45 ) begin + free_adr_mask_next[45] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd46 ) begin + free_adr_mask_next[46] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd46 ) begin + free_adr_mask_next[46] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd47 ) begin + free_adr_mask_next[47] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd47 ) begin + free_adr_mask_next[47] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd48 ) begin + free_adr_mask_next[48] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd48 ) begin + free_adr_mask_next[48] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd49 ) begin + free_adr_mask_next[49] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd49 ) begin + free_adr_mask_next[49] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd50 ) begin + free_adr_mask_next[50] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd50 ) begin + free_adr_mask_next[50] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd51 ) begin + free_adr_mask_next[51] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd51 ) begin + free_adr_mask_next[51] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd52 ) begin + free_adr_mask_next[52] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd52 ) begin + free_adr_mask_next[52] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd53 ) begin + free_adr_mask_next[53] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd53 ) begin + free_adr_mask_next[53] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd54 ) begin + free_adr_mask_next[54] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd54 ) begin + free_adr_mask_next[54] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd55 ) begin + free_adr_mask_next[55] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd55 ) begin + free_adr_mask_next[55] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd56 ) begin + free_adr_mask_next[56] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd56 ) begin + free_adr_mask_next[56] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd57 ) begin + free_adr_mask_next[57] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd57 ) begin + free_adr_mask_next[57] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd58 ) begin + free_adr_mask_next[58] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd58 ) begin + free_adr_mask_next[58] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd59 ) begin + free_adr_mask_next[59] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd59 ) begin + free_adr_mask_next[59] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd60 ) begin + free_adr_mask_next[60] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd60 ) begin + free_adr_mask_next[60] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd61 ) begin + free_adr_mask_next[61] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd61 ) begin + free_adr_mask_next[61] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd62 ) begin + free_adr_mask_next[62] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd62 ) begin + free_adr_mask_next[62] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd63 ) begin + free_adr_mask_next[63] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd63 ) begin + free_adr_mask_next[63] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd64 ) begin + free_adr_mask_next[64] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd64 ) begin + free_adr_mask_next[64] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd65 ) begin + free_adr_mask_next[65] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd65 ) begin + free_adr_mask_next[65] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd66 ) begin + free_adr_mask_next[66] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd66 ) begin + free_adr_mask_next[66] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd67 ) begin + free_adr_mask_next[67] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd67 ) begin + free_adr_mask_next[67] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd68 ) begin + free_adr_mask_next[68] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd68 ) begin + free_adr_mask_next[68] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd69 ) begin + free_adr_mask_next[69] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd69 ) begin + free_adr_mask_next[69] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd70 ) begin + free_adr_mask_next[70] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd70 ) begin + free_adr_mask_next[70] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd71 ) begin + free_adr_mask_next[71] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd71 ) begin + free_adr_mask_next[71] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd72 ) begin + free_adr_mask_next[72] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd72 ) begin + free_adr_mask_next[72] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd73 ) begin + free_adr_mask_next[73] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd73 ) begin + free_adr_mask_next[73] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd74 ) begin + free_adr_mask_next[74] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd74 ) begin + free_adr_mask_next[74] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd75 ) begin + free_adr_mask_next[75] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd75 ) begin + free_adr_mask_next[75] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd76 ) begin + free_adr_mask_next[76] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd76 ) begin + free_adr_mask_next[76] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd77 ) begin + free_adr_mask_next[77] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd77 ) begin + free_adr_mask_next[77] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd78 ) begin + free_adr_mask_next[78] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd78 ) begin + free_adr_mask_next[78] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd79 ) begin + free_adr_mask_next[79] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd79 ) begin + free_adr_mask_next[79] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd80 ) begin + free_adr_mask_next[80] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd80 ) begin + free_adr_mask_next[80] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd81 ) begin + free_adr_mask_next[81] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd81 ) begin + free_adr_mask_next[81] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd82 ) begin + free_adr_mask_next[82] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd82 ) begin + free_adr_mask_next[82] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd83 ) begin + free_adr_mask_next[83] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd83 ) begin + free_adr_mask_next[83] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd84 ) begin + free_adr_mask_next[84] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd84 ) begin + free_adr_mask_next[84] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd85 ) begin + free_adr_mask_next[85] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd85 ) begin + free_adr_mask_next[85] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd86 ) begin + free_adr_mask_next[86] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd86 ) begin + free_adr_mask_next[86] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd87 ) begin + free_adr_mask_next[87] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd87 ) begin + free_adr_mask_next[87] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd88 ) begin + free_adr_mask_next[88] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd88 ) begin + free_adr_mask_next[88] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd89 ) begin + free_adr_mask_next[89] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd89 ) begin + free_adr_mask_next[89] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd90 ) begin + free_adr_mask_next[90] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd90 ) begin + free_adr_mask_next[90] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd91 ) begin + free_adr_mask_next[91] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd91 ) begin + free_adr_mask_next[91] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd92 ) begin + free_adr_mask_next[92] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd92 ) begin + free_adr_mask_next[92] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd93 ) begin + free_adr_mask_next[93] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd93 ) begin + free_adr_mask_next[93] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd94 ) begin + free_adr_mask_next[94] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd94 ) begin + free_adr_mask_next[94] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd95 ) begin + free_adr_mask_next[95] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd95 ) begin + free_adr_mask_next[95] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd96 ) begin + free_adr_mask_next[96] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd96 ) begin + free_adr_mask_next[96] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd97 ) begin + free_adr_mask_next[97] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd97 ) begin + free_adr_mask_next[97] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd98 ) begin + free_adr_mask_next[98] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd98 ) begin + free_adr_mask_next[98] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd99 ) begin + free_adr_mask_next[99] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd99 ) begin + free_adr_mask_next[99] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd100 ) begin + free_adr_mask_next[100] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd100 ) begin + free_adr_mask_next[100] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd101 ) begin + free_adr_mask_next[101] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd101 ) begin + free_adr_mask_next[101] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd102 ) begin + free_adr_mask_next[102] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd102 ) begin + free_adr_mask_next[102] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd103 ) begin + free_adr_mask_next[103] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd103 ) begin + free_adr_mask_next[103] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd104 ) begin + free_adr_mask_next[104] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd104 ) begin + free_adr_mask_next[104] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd105 ) begin + free_adr_mask_next[105] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd105 ) begin + free_adr_mask_next[105] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd106 ) begin + free_adr_mask_next[106] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd106 ) begin + free_adr_mask_next[106] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd107 ) begin + free_adr_mask_next[107] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd107 ) begin + free_adr_mask_next[107] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd108 ) begin + free_adr_mask_next[108] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd108 ) begin + free_adr_mask_next[108] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd109 ) begin + free_adr_mask_next[109] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd109 ) begin + free_adr_mask_next[109] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd110 ) begin + free_adr_mask_next[110] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd110 ) begin + free_adr_mask_next[110] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd111 ) begin + free_adr_mask_next[111] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd111 ) begin + free_adr_mask_next[111] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd112 ) begin + free_adr_mask_next[112] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd112 ) begin + free_adr_mask_next[112] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd113 ) begin + free_adr_mask_next[113] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd113 ) begin + free_adr_mask_next[113] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd114 ) begin + free_adr_mask_next[114] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd114 ) begin + free_adr_mask_next[114] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd115 ) begin + free_adr_mask_next[115] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd115 ) begin + free_adr_mask_next[115] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd116 ) begin + free_adr_mask_next[116] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd116 ) begin + free_adr_mask_next[116] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd117 ) begin + free_adr_mask_next[117] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd117 ) begin + free_adr_mask_next[117] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd118 ) begin + free_adr_mask_next[118] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd118 ) begin + free_adr_mask_next[118] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd119 ) begin + free_adr_mask_next[119] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd119 ) begin + free_adr_mask_next[119] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd120 ) begin + free_adr_mask_next[120] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd120 ) begin + free_adr_mask_next[120] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd121 ) begin + free_adr_mask_next[121] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd121 ) begin + free_adr_mask_next[121] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd122 ) begin + free_adr_mask_next[122] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd122 ) begin + free_adr_mask_next[122] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd123 ) begin + free_adr_mask_next[123] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd123 ) begin + free_adr_mask_next[123] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd124 ) begin + free_adr_mask_next[124] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd124 ) begin + free_adr_mask_next[124] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd125 ) begin + free_adr_mask_next[125] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd125 ) begin + free_adr_mask_next[125] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd126 ) begin + free_adr_mask_next[126] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd126 ) begin + free_adr_mask_next[126] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd127 ) begin + free_adr_mask_next[127] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd127 ) begin + free_adr_mask_next[127] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd128 ) begin + free_adr_mask_next[128] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd128 ) begin + free_adr_mask_next[128] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd129 ) begin + free_adr_mask_next[129] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd129 ) begin + free_adr_mask_next[129] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd130 ) begin + free_adr_mask_next[130] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd130 ) begin + free_adr_mask_next[130] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd131 ) begin + free_adr_mask_next[131] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd131 ) begin + free_adr_mask_next[131] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd132 ) begin + free_adr_mask_next[132] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd132 ) begin + free_adr_mask_next[132] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd133 ) begin + free_adr_mask_next[133] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd133 ) begin + free_adr_mask_next[133] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd134 ) begin + free_adr_mask_next[134] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd134 ) begin + free_adr_mask_next[134] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd135 ) begin + free_adr_mask_next[135] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd135 ) begin + free_adr_mask_next[135] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd136 ) begin + free_adr_mask_next[136] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd136 ) begin + free_adr_mask_next[136] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd137 ) begin + free_adr_mask_next[137] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd137 ) begin + free_adr_mask_next[137] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd138 ) begin + free_adr_mask_next[138] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd138 ) begin + free_adr_mask_next[138] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd139 ) begin + free_adr_mask_next[139] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd139 ) begin + free_adr_mask_next[139] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd140 ) begin + free_adr_mask_next[140] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd140 ) begin + free_adr_mask_next[140] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd141 ) begin + free_adr_mask_next[141] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd141 ) begin + free_adr_mask_next[141] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd142 ) begin + free_adr_mask_next[142] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd142 ) begin + free_adr_mask_next[142] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd143 ) begin + free_adr_mask_next[143] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd143 ) begin + free_adr_mask_next[143] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd144 ) begin + free_adr_mask_next[144] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd144 ) begin + free_adr_mask_next[144] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd145 ) begin + free_adr_mask_next[145] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd145 ) begin + free_adr_mask_next[145] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd146 ) begin + free_adr_mask_next[146] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd146 ) begin + free_adr_mask_next[146] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd147 ) begin + free_adr_mask_next[147] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd147 ) begin + free_adr_mask_next[147] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd148 ) begin + free_adr_mask_next[148] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd148 ) begin + free_adr_mask_next[148] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd149 ) begin + free_adr_mask_next[149] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd149 ) begin + free_adr_mask_next[149] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd150 ) begin + free_adr_mask_next[150] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd150 ) begin + free_adr_mask_next[150] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd151 ) begin + free_adr_mask_next[151] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd151 ) begin + free_adr_mask_next[151] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd152 ) begin + free_adr_mask_next[152] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd152 ) begin + free_adr_mask_next[152] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd153 ) begin + free_adr_mask_next[153] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd153 ) begin + free_adr_mask_next[153] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd154 ) begin + free_adr_mask_next[154] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd154 ) begin + free_adr_mask_next[154] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd155 ) begin + free_adr_mask_next[155] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd155 ) begin + free_adr_mask_next[155] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd156 ) begin + free_adr_mask_next[156] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd156 ) begin + free_adr_mask_next[156] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd157 ) begin + free_adr_mask_next[157] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd157 ) begin + free_adr_mask_next[157] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd158 ) begin + free_adr_mask_next[158] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd158 ) begin + free_adr_mask_next[158] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd159 ) begin + free_adr_mask_next[159] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd159 ) begin + free_adr_mask_next[159] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd160 ) begin + free_adr_mask_next[160] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd160 ) begin + free_adr_mask_next[160] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd161 ) begin + free_adr_mask_next[161] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd161 ) begin + free_adr_mask_next[161] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd162 ) begin + free_adr_mask_next[162] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd162 ) begin + free_adr_mask_next[162] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd163 ) begin + free_adr_mask_next[163] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd163 ) begin + free_adr_mask_next[163] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd164 ) begin + free_adr_mask_next[164] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd164 ) begin + free_adr_mask_next[164] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd165 ) begin + free_adr_mask_next[165] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd165 ) begin + free_adr_mask_next[165] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd166 ) begin + free_adr_mask_next[166] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd166 ) begin + free_adr_mask_next[166] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd167 ) begin + free_adr_mask_next[167] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd167 ) begin + free_adr_mask_next[167] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd168 ) begin + free_adr_mask_next[168] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd168 ) begin + free_adr_mask_next[168] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd169 ) begin + free_adr_mask_next[169] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd169 ) begin + free_adr_mask_next[169] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd170 ) begin + free_adr_mask_next[170] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd170 ) begin + free_adr_mask_next[170] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd171 ) begin + free_adr_mask_next[171] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd171 ) begin + free_adr_mask_next[171] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd172 ) begin + free_adr_mask_next[172] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd172 ) begin + free_adr_mask_next[172] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd173 ) begin + free_adr_mask_next[173] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd173 ) begin + free_adr_mask_next[173] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd174 ) begin + free_adr_mask_next[174] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd174 ) begin + free_adr_mask_next[174] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd175 ) begin + free_adr_mask_next[175] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd175 ) begin + free_adr_mask_next[175] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd176 ) begin + free_adr_mask_next[176] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd176 ) begin + free_adr_mask_next[176] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd177 ) begin + free_adr_mask_next[177] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd177 ) begin + free_adr_mask_next[177] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd178 ) begin + free_adr_mask_next[178] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd178 ) begin + free_adr_mask_next[178] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd179 ) begin + free_adr_mask_next[179] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd179 ) begin + free_adr_mask_next[179] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd180 ) begin + free_adr_mask_next[180] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd180 ) begin + free_adr_mask_next[180] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd181 ) begin + free_adr_mask_next[181] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd181 ) begin + free_adr_mask_next[181] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd182 ) begin + free_adr_mask_next[182] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd182 ) begin + free_adr_mask_next[182] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd183 ) begin + free_adr_mask_next[183] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd183 ) begin + free_adr_mask_next[183] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd184 ) begin + free_adr_mask_next[184] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd184 ) begin + free_adr_mask_next[184] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd185 ) begin + free_adr_mask_next[185] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd185 ) begin + free_adr_mask_next[185] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd186 ) begin + free_adr_mask_next[186] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd186 ) begin + free_adr_mask_next[186] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd187 ) begin + free_adr_mask_next[187] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd187 ) begin + free_adr_mask_next[187] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd188 ) begin + free_adr_mask_next[188] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd188 ) begin + free_adr_mask_next[188] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd189 ) begin + free_adr_mask_next[189] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd189 ) begin + free_adr_mask_next[189] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd190 ) begin + free_adr_mask_next[190] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd190 ) begin + free_adr_mask_next[190] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd191 ) begin + free_adr_mask_next[191] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd191 ) begin + free_adr_mask_next[191] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd192 ) begin + free_adr_mask_next[192] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd192 ) begin + free_adr_mask_next[192] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd193 ) begin + free_adr_mask_next[193] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd193 ) begin + free_adr_mask_next[193] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd194 ) begin + free_adr_mask_next[194] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd194 ) begin + free_adr_mask_next[194] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd195 ) begin + free_adr_mask_next[195] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd195 ) begin + free_adr_mask_next[195] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd196 ) begin + free_adr_mask_next[196] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd196 ) begin + free_adr_mask_next[196] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd197 ) begin + free_adr_mask_next[197] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd197 ) begin + free_adr_mask_next[197] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd198 ) begin + free_adr_mask_next[198] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd198 ) begin + free_adr_mask_next[198] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd199 ) begin + free_adr_mask_next[199] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd199 ) begin + free_adr_mask_next[199] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd200 ) begin + free_adr_mask_next[200] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd200 ) begin + free_adr_mask_next[200] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd201 ) begin + free_adr_mask_next[201] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd201 ) begin + free_adr_mask_next[201] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd202 ) begin + free_adr_mask_next[202] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd202 ) begin + free_adr_mask_next[202] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd203 ) begin + free_adr_mask_next[203] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd203 ) begin + free_adr_mask_next[203] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd204 ) begin + free_adr_mask_next[204] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd204 ) begin + free_adr_mask_next[204] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd205 ) begin + free_adr_mask_next[205] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd205 ) begin + free_adr_mask_next[205] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd206 ) begin + free_adr_mask_next[206] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd206 ) begin + free_adr_mask_next[206] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd207 ) begin + free_adr_mask_next[207] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd207 ) begin + free_adr_mask_next[207] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd208 ) begin + free_adr_mask_next[208] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd208 ) begin + free_adr_mask_next[208] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd209 ) begin + free_adr_mask_next[209] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd209 ) begin + free_adr_mask_next[209] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd210 ) begin + free_adr_mask_next[210] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd210 ) begin + free_adr_mask_next[210] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd211 ) begin + free_adr_mask_next[211] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd211 ) begin + free_adr_mask_next[211] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd212 ) begin + free_adr_mask_next[212] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd212 ) begin + free_adr_mask_next[212] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd213 ) begin + free_adr_mask_next[213] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd213 ) begin + free_adr_mask_next[213] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd214 ) begin + free_adr_mask_next[214] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd214 ) begin + free_adr_mask_next[214] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd215 ) begin + free_adr_mask_next[215] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd215 ) begin + free_adr_mask_next[215] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd216 ) begin + free_adr_mask_next[216] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd216 ) begin + free_adr_mask_next[216] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd217 ) begin + free_adr_mask_next[217] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd217 ) begin + free_adr_mask_next[217] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd218 ) begin + free_adr_mask_next[218] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd218 ) begin + free_adr_mask_next[218] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd219 ) begin + free_adr_mask_next[219] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd219 ) begin + free_adr_mask_next[219] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd220 ) begin + free_adr_mask_next[220] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd220 ) begin + free_adr_mask_next[220] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd221 ) begin + free_adr_mask_next[221] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd221 ) begin + free_adr_mask_next[221] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd222 ) begin + free_adr_mask_next[222] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd222 ) begin + free_adr_mask_next[222] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd223 ) begin + free_adr_mask_next[223] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd223 ) begin + free_adr_mask_next[223] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd224 ) begin + free_adr_mask_next[224] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd224 ) begin + free_adr_mask_next[224] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd225 ) begin + free_adr_mask_next[225] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd225 ) begin + free_adr_mask_next[225] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd226 ) begin + free_adr_mask_next[226] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd226 ) begin + free_adr_mask_next[226] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd227 ) begin + free_adr_mask_next[227] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd227 ) begin + free_adr_mask_next[227] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd228 ) begin + free_adr_mask_next[228] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd228 ) begin + free_adr_mask_next[228] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd229 ) begin + free_adr_mask_next[229] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd229 ) begin + free_adr_mask_next[229] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd230 ) begin + free_adr_mask_next[230] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd230 ) begin + free_adr_mask_next[230] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd231 ) begin + free_adr_mask_next[231] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd231 ) begin + free_adr_mask_next[231] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd232 ) begin + free_adr_mask_next[232] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd232 ) begin + free_adr_mask_next[232] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd233 ) begin + free_adr_mask_next[233] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd233 ) begin + free_adr_mask_next[233] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd234 ) begin + free_adr_mask_next[234] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd234 ) begin + free_adr_mask_next[234] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd235 ) begin + free_adr_mask_next[235] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd235 ) begin + free_adr_mask_next[235] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd236 ) begin + free_adr_mask_next[236] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd236 ) begin + free_adr_mask_next[236] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd237 ) begin + free_adr_mask_next[237] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd237 ) begin + free_adr_mask_next[237] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd238 ) begin + free_adr_mask_next[238] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd238 ) begin + free_adr_mask_next[238] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd239 ) begin + free_adr_mask_next[239] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd239 ) begin + free_adr_mask_next[239] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd240 ) begin + free_adr_mask_next[240] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd240 ) begin + free_adr_mask_next[240] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd241 ) begin + free_adr_mask_next[241] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd241 ) begin + free_adr_mask_next[241] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd242 ) begin + free_adr_mask_next[242] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd242 ) begin + free_adr_mask_next[242] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd243 ) begin + free_adr_mask_next[243] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd243 ) begin + free_adr_mask_next[243] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd244 ) begin + free_adr_mask_next[244] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd244 ) begin + free_adr_mask_next[244] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd245 ) begin + free_adr_mask_next[245] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd245 ) begin + free_adr_mask_next[245] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd246 ) begin + free_adr_mask_next[246] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd246 ) begin + free_adr_mask_next[246] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd247 ) begin + free_adr_mask_next[247] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd247 ) begin + free_adr_mask_next[247] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd248 ) begin + free_adr_mask_next[248] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd248 ) begin + free_adr_mask_next[248] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd249 ) begin + free_adr_mask_next[249] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd249 ) begin + free_adr_mask_next[249] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd250 ) begin + free_adr_mask_next[250] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd250 ) begin + free_adr_mask_next[250] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd251 ) begin + free_adr_mask_next[251] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd251 ) begin + free_adr_mask_next[251] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd252 ) begin + free_adr_mask_next[252] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd252 ) begin + free_adr_mask_next[252] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd253 ) begin + free_adr_mask_next[253] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd253 ) begin + free_adr_mask_next[253] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd254 ) begin + free_adr_mask_next[254] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd254 ) begin + free_adr_mask_next[254] = 1'b0; + end +end +wire flag_l0_0 = free_adr_mask[1] | free_adr_mask[0]; +wire flag_l0_1 = free_adr_mask[3] | free_adr_mask[2]; +wire flag_l0_2 = free_adr_mask[5] | free_adr_mask[4]; +wire flag_l0_3 = free_adr_mask[7] | free_adr_mask[6]; +wire flag_l0_4 = free_adr_mask[9] | free_adr_mask[8]; +wire flag_l0_5 = free_adr_mask[11] | free_adr_mask[10]; +wire flag_l0_6 = free_adr_mask[13] | free_adr_mask[12]; +wire flag_l0_7 = free_adr_mask[15] | free_adr_mask[14]; +wire flag_l0_8 = free_adr_mask[17] | free_adr_mask[16]; +wire flag_l0_9 = free_adr_mask[19] | free_adr_mask[18]; +wire flag_l0_10 = free_adr_mask[21] | free_adr_mask[20]; +wire flag_l0_11 = free_adr_mask[23] | free_adr_mask[22]; +wire flag_l0_12 = free_adr_mask[25] | free_adr_mask[24]; +wire flag_l0_13 = free_adr_mask[27] | free_adr_mask[26]; +wire flag_l0_14 = free_adr_mask[29] | free_adr_mask[28]; +wire flag_l0_15 = free_adr_mask[31] | free_adr_mask[30]; +wire flag_l0_16 = free_adr_mask[33] | free_adr_mask[32]; +wire flag_l0_17 = free_adr_mask[35] | free_adr_mask[34]; +wire flag_l0_18 = free_adr_mask[37] | free_adr_mask[36]; +wire flag_l0_19 = free_adr_mask[39] | free_adr_mask[38]; +wire flag_l0_20 = free_adr_mask[41] | free_adr_mask[40]; +wire flag_l0_21 = free_adr_mask[43] | free_adr_mask[42]; +wire flag_l0_22 = free_adr_mask[45] | free_adr_mask[44]; +wire flag_l0_23 = free_adr_mask[47] | free_adr_mask[46]; +wire flag_l0_24 = free_adr_mask[49] | free_adr_mask[48]; +wire flag_l0_25 = free_adr_mask[51] | free_adr_mask[50]; +wire flag_l0_26 = free_adr_mask[53] | free_adr_mask[52]; +wire flag_l0_27 = free_adr_mask[55] | free_adr_mask[54]; +wire flag_l0_28 = free_adr_mask[57] | free_adr_mask[56]; +wire flag_l0_29 = free_adr_mask[59] | free_adr_mask[58]; +wire flag_l0_30 = free_adr_mask[61] | free_adr_mask[60]; +wire flag_l0_31 = free_adr_mask[63] | free_adr_mask[62]; +wire flag_l0_32 = free_adr_mask[65] | free_adr_mask[64]; +wire flag_l0_33 = free_adr_mask[67] | free_adr_mask[66]; +wire flag_l0_34 = free_adr_mask[69] | free_adr_mask[68]; +wire flag_l0_35 = free_adr_mask[71] | free_adr_mask[70]; +wire flag_l0_36 = free_adr_mask[73] | free_adr_mask[72]; +wire flag_l0_37 = free_adr_mask[75] | free_adr_mask[74]; +wire flag_l0_38 = free_adr_mask[77] | free_adr_mask[76]; +wire flag_l0_39 = free_adr_mask[79] | free_adr_mask[78]; +wire flag_l0_40 = free_adr_mask[81] | free_adr_mask[80]; +wire flag_l0_41 = free_adr_mask[83] | free_adr_mask[82]; +wire flag_l0_42 = free_adr_mask[85] | free_adr_mask[84]; +wire flag_l0_43 = free_adr_mask[87] | free_adr_mask[86]; +wire flag_l0_44 = free_adr_mask[89] | free_adr_mask[88]; +wire flag_l0_45 = free_adr_mask[91] | free_adr_mask[90]; +wire flag_l0_46 = free_adr_mask[93] | free_adr_mask[92]; +wire flag_l0_47 = free_adr_mask[95] | free_adr_mask[94]; +wire flag_l0_48 = free_adr_mask[97] | free_adr_mask[96]; +wire flag_l0_49 = free_adr_mask[99] | free_adr_mask[98]; +wire flag_l0_50 = free_adr_mask[101] | free_adr_mask[100]; +wire flag_l0_51 = free_adr_mask[103] | free_adr_mask[102]; +wire flag_l0_52 = free_adr_mask[105] | free_adr_mask[104]; +wire flag_l0_53 = free_adr_mask[107] | free_adr_mask[106]; +wire flag_l0_54 = free_adr_mask[109] | free_adr_mask[108]; +wire flag_l0_55 = free_adr_mask[111] | free_adr_mask[110]; +wire flag_l0_56 = free_adr_mask[113] | free_adr_mask[112]; +wire flag_l0_57 = free_adr_mask[115] | free_adr_mask[114]; +wire flag_l0_58 = free_adr_mask[117] | free_adr_mask[116]; +wire flag_l0_59 = free_adr_mask[119] | free_adr_mask[118]; +wire flag_l0_60 = free_adr_mask[121] | free_adr_mask[120]; +wire flag_l0_61 = free_adr_mask[123] | free_adr_mask[122]; +wire flag_l0_62 = free_adr_mask[125] | free_adr_mask[124]; +wire flag_l0_63 = free_adr_mask[127] | free_adr_mask[126]; +wire flag_l0_64 = free_adr_mask[129] | free_adr_mask[128]; +wire flag_l0_65 = free_adr_mask[131] | free_adr_mask[130]; +wire flag_l0_66 = free_adr_mask[133] | free_adr_mask[132]; +wire flag_l0_67 = free_adr_mask[135] | free_adr_mask[134]; +wire flag_l0_68 = free_adr_mask[137] | free_adr_mask[136]; +wire flag_l0_69 = free_adr_mask[139] | free_adr_mask[138]; +wire flag_l0_70 = free_adr_mask[141] | free_adr_mask[140]; +wire flag_l0_71 = free_adr_mask[143] | free_adr_mask[142]; +wire flag_l0_72 = free_adr_mask[145] | free_adr_mask[144]; +wire flag_l0_73 = free_adr_mask[147] | free_adr_mask[146]; +wire flag_l0_74 = free_adr_mask[149] | free_adr_mask[148]; +wire flag_l0_75 = free_adr_mask[151] | free_adr_mask[150]; +wire flag_l0_76 = free_adr_mask[153] | free_adr_mask[152]; +wire flag_l0_77 = free_adr_mask[155] | free_adr_mask[154]; +wire flag_l0_78 = free_adr_mask[157] | free_adr_mask[156]; +wire flag_l0_79 = free_adr_mask[159] | free_adr_mask[158]; +wire flag_l0_80 = free_adr_mask[161] | free_adr_mask[160]; +wire flag_l0_81 = free_adr_mask[163] | free_adr_mask[162]; +wire flag_l0_82 = free_adr_mask[165] | free_adr_mask[164]; +wire flag_l0_83 = free_adr_mask[167] | free_adr_mask[166]; +wire flag_l0_84 = free_adr_mask[169] | free_adr_mask[168]; +wire flag_l0_85 = free_adr_mask[171] | free_adr_mask[170]; +wire flag_l0_86 = free_adr_mask[173] | free_adr_mask[172]; +wire flag_l0_87 = free_adr_mask[175] | free_adr_mask[174]; +wire flag_l0_88 = free_adr_mask[177] | free_adr_mask[176]; +wire flag_l0_89 = free_adr_mask[179] | free_adr_mask[178]; +wire flag_l0_90 = free_adr_mask[181] | free_adr_mask[180]; +wire flag_l0_91 = free_adr_mask[183] | free_adr_mask[182]; +wire flag_l0_92 = free_adr_mask[185] | free_adr_mask[184]; +wire flag_l0_93 = free_adr_mask[187] | free_adr_mask[186]; +wire flag_l0_94 = free_adr_mask[189] | free_adr_mask[188]; +wire flag_l0_95 = free_adr_mask[191] | free_adr_mask[190]; +wire flag_l0_96 = free_adr_mask[193] | free_adr_mask[192]; +wire flag_l0_97 = free_adr_mask[195] | free_adr_mask[194]; +wire flag_l0_98 = free_adr_mask[197] | free_adr_mask[196]; +wire flag_l0_99 = free_adr_mask[199] | free_adr_mask[198]; +wire flag_l0_100 = free_adr_mask[201] | free_adr_mask[200]; +wire flag_l0_101 = free_adr_mask[203] | free_adr_mask[202]; +wire flag_l0_102 = free_adr_mask[205] | free_adr_mask[204]; +wire flag_l0_103 = free_adr_mask[207] | free_adr_mask[206]; +wire flag_l0_104 = free_adr_mask[209] | free_adr_mask[208]; +wire flag_l0_105 = free_adr_mask[211] | free_adr_mask[210]; +wire flag_l0_106 = free_adr_mask[213] | free_adr_mask[212]; +wire flag_l0_107 = free_adr_mask[215] | free_adr_mask[214]; +wire flag_l0_108 = free_adr_mask[217] | free_adr_mask[216]; +wire flag_l0_109 = free_adr_mask[219] | free_adr_mask[218]; +wire flag_l0_110 = free_adr_mask[221] | free_adr_mask[220]; +wire flag_l0_111 = free_adr_mask[223] | free_adr_mask[222]; +wire flag_l0_112 = free_adr_mask[225] | free_adr_mask[224]; +wire flag_l0_113 = free_adr_mask[227] | free_adr_mask[226]; +wire flag_l0_114 = free_adr_mask[229] | free_adr_mask[228]; +wire flag_l0_115 = free_adr_mask[231] | free_adr_mask[230]; +wire flag_l0_116 = free_adr_mask[233] | free_adr_mask[232]; +wire flag_l0_117 = free_adr_mask[235] | free_adr_mask[234]; +wire flag_l0_118 = free_adr_mask[237] | free_adr_mask[236]; +wire flag_l0_119 = free_adr_mask[239] | free_adr_mask[238]; +wire flag_l0_120 = free_adr_mask[241] | free_adr_mask[240]; +wire flag_l0_121 = free_adr_mask[243] | free_adr_mask[242]; +wire flag_l0_122 = free_adr_mask[245] | free_adr_mask[244]; +wire flag_l0_123 = free_adr_mask[247] | free_adr_mask[246]; +wire flag_l0_124 = free_adr_mask[249] | free_adr_mask[248]; +wire flag_l0_125 = free_adr_mask[251] | free_adr_mask[250]; +wire flag_l0_126 = free_adr_mask[253] | free_adr_mask[252]; +wire flag_l1_0 = flag_l0_1 | flag_l0_0; +wire flag_l1_1 = flag_l0_3 | flag_l0_2; +wire flag_l1_2 = flag_l0_5 | flag_l0_4; +wire flag_l1_3 = flag_l0_7 | flag_l0_6; +wire flag_l1_4 = flag_l0_9 | flag_l0_8; +wire flag_l1_5 = flag_l0_11 | flag_l0_10; +wire flag_l1_6 = flag_l0_13 | flag_l0_12; +wire flag_l1_7 = flag_l0_15 | flag_l0_14; +wire flag_l1_8 = flag_l0_17 | flag_l0_16; +wire flag_l1_9 = flag_l0_19 | flag_l0_18; +wire flag_l1_10 = flag_l0_21 | flag_l0_20; +wire flag_l1_11 = flag_l0_23 | flag_l0_22; +wire flag_l1_12 = flag_l0_25 | flag_l0_24; +wire flag_l1_13 = flag_l0_27 | flag_l0_26; +wire flag_l1_14 = flag_l0_29 | flag_l0_28; +wire flag_l1_15 = flag_l0_31 | flag_l0_30; +wire flag_l1_16 = flag_l0_33 | flag_l0_32; +wire flag_l1_17 = flag_l0_35 | flag_l0_34; +wire flag_l1_18 = flag_l0_37 | flag_l0_36; +wire flag_l1_19 = flag_l0_39 | flag_l0_38; +wire flag_l1_20 = flag_l0_41 | flag_l0_40; +wire flag_l1_21 = flag_l0_43 | flag_l0_42; +wire flag_l1_22 = flag_l0_45 | flag_l0_44; +wire flag_l1_23 = flag_l0_47 | flag_l0_46; +wire flag_l1_24 = flag_l0_49 | flag_l0_48; +wire flag_l1_25 = flag_l0_51 | flag_l0_50; +wire flag_l1_26 = flag_l0_53 | flag_l0_52; +wire flag_l1_27 = flag_l0_55 | flag_l0_54; +wire flag_l1_28 = flag_l0_57 | flag_l0_56; +wire flag_l1_29 = flag_l0_59 | flag_l0_58; +wire flag_l1_30 = flag_l0_61 | flag_l0_60; +wire flag_l1_31 = flag_l0_63 | flag_l0_62; +wire flag_l1_32 = flag_l0_65 | flag_l0_64; +wire flag_l1_33 = flag_l0_67 | flag_l0_66; +wire flag_l1_34 = flag_l0_69 | flag_l0_68; +wire flag_l1_35 = flag_l0_71 | flag_l0_70; +wire flag_l1_36 = flag_l0_73 | flag_l0_72; +wire flag_l1_37 = flag_l0_75 | flag_l0_74; +wire flag_l1_38 = flag_l0_77 | flag_l0_76; +wire flag_l1_39 = flag_l0_79 | flag_l0_78; +wire flag_l1_40 = flag_l0_81 | flag_l0_80; +wire flag_l1_41 = flag_l0_83 | flag_l0_82; +wire flag_l1_42 = flag_l0_85 | flag_l0_84; +wire flag_l1_43 = flag_l0_87 | flag_l0_86; +wire flag_l1_44 = flag_l0_89 | flag_l0_88; +wire flag_l1_45 = flag_l0_91 | flag_l0_90; +wire flag_l1_46 = flag_l0_93 | flag_l0_92; +wire flag_l1_47 = flag_l0_95 | flag_l0_94; +wire flag_l1_48 = flag_l0_97 | flag_l0_96; +wire flag_l1_49 = flag_l0_99 | flag_l0_98; +wire flag_l1_50 = flag_l0_101 | flag_l0_100; +wire flag_l1_51 = flag_l0_103 | flag_l0_102; +wire flag_l1_52 = flag_l0_105 | flag_l0_104; +wire flag_l1_53 = flag_l0_107 | flag_l0_106; +wire flag_l1_54 = flag_l0_109 | flag_l0_108; +wire flag_l1_55 = flag_l0_111 | flag_l0_110; +wire flag_l1_56 = flag_l0_113 | flag_l0_112; +wire flag_l1_57 = flag_l0_115 | flag_l0_114; +wire flag_l1_58 = flag_l0_117 | flag_l0_116; +wire flag_l1_59 = flag_l0_119 | flag_l0_118; +wire flag_l1_60 = flag_l0_121 | flag_l0_120; +wire flag_l1_61 = flag_l0_123 | flag_l0_122; +wire flag_l1_62 = flag_l0_125 | flag_l0_124; +wire flag_l2_0 = flag_l1_1 | flag_l1_0; +wire flag_l2_1 = flag_l1_3 | flag_l1_2; +wire flag_l2_2 = flag_l1_5 | flag_l1_4; +wire flag_l2_3 = flag_l1_7 | flag_l1_6; +wire flag_l2_4 = flag_l1_9 | flag_l1_8; +wire flag_l2_5 = flag_l1_11 | flag_l1_10; +wire flag_l2_6 = flag_l1_13 | flag_l1_12; +wire flag_l2_7 = flag_l1_15 | flag_l1_14; +wire flag_l2_8 = flag_l1_17 | flag_l1_16; +wire flag_l2_9 = flag_l1_19 | flag_l1_18; +wire flag_l2_10 = flag_l1_21 | flag_l1_20; +wire flag_l2_11 = flag_l1_23 | flag_l1_22; +wire flag_l2_12 = flag_l1_25 | flag_l1_24; +wire flag_l2_13 = flag_l1_27 | flag_l1_26; +wire flag_l2_14 = flag_l1_29 | flag_l1_28; +wire flag_l2_15 = flag_l1_31 | flag_l1_30; +wire flag_l2_16 = flag_l1_33 | flag_l1_32; +wire flag_l2_17 = flag_l1_35 | flag_l1_34; +wire flag_l2_18 = flag_l1_37 | flag_l1_36; +wire flag_l2_19 = flag_l1_39 | flag_l1_38; +wire flag_l2_20 = flag_l1_41 | flag_l1_40; +wire flag_l2_21 = flag_l1_43 | flag_l1_42; +wire flag_l2_22 = flag_l1_45 | flag_l1_44; +wire flag_l2_23 = flag_l1_47 | flag_l1_46; +wire flag_l2_24 = flag_l1_49 | flag_l1_48; +wire flag_l2_25 = flag_l1_51 | flag_l1_50; +wire flag_l2_26 = flag_l1_53 | flag_l1_52; +wire flag_l2_27 = flag_l1_55 | flag_l1_54; +wire flag_l2_28 = flag_l1_57 | flag_l1_56; +wire flag_l2_29 = flag_l1_59 | flag_l1_58; +wire flag_l2_30 = flag_l1_61 | flag_l1_60; +wire flag_l3_0 = flag_l2_1 | flag_l2_0; +wire flag_l3_1 = flag_l2_3 | flag_l2_2; +wire flag_l3_2 = flag_l2_5 | flag_l2_4; +wire flag_l3_3 = flag_l2_7 | flag_l2_6; +wire flag_l3_4 = flag_l2_9 | flag_l2_8; +wire flag_l3_5 = flag_l2_11 | flag_l2_10; +wire flag_l3_6 = flag_l2_13 | flag_l2_12; +wire flag_l3_7 = flag_l2_15 | flag_l2_14; +wire flag_l3_8 = flag_l2_17 | flag_l2_16; +wire flag_l3_9 = flag_l2_19 | flag_l2_18; +wire flag_l3_10 = flag_l2_21 | flag_l2_20; +wire flag_l3_11 = flag_l2_23 | flag_l2_22; +wire flag_l3_12 = flag_l2_25 | flag_l2_24; +wire flag_l3_13 = flag_l2_27 | flag_l2_26; +wire flag_l3_14 = flag_l2_29 | flag_l2_28; +wire flag_l4_0 = flag_l3_1 | flag_l3_0; +wire flag_l4_1 = flag_l3_3 | flag_l3_2; +wire flag_l4_2 = flag_l3_5 | flag_l3_4; +wire flag_l4_3 = flag_l3_7 | flag_l3_6; +wire flag_l4_4 = flag_l3_9 | flag_l3_8; +wire flag_l4_5 = flag_l3_11 | flag_l3_10; +wire flag_l4_6 = flag_l3_13 | flag_l3_12; +wire flag_l5_0 = flag_l4_1 | flag_l4_0; +wire flag_l5_1 = flag_l4_3 | flag_l4_2; +wire flag_l5_2 = flag_l4_5 | flag_l4_4; +wire flag_l6_0 = flag_l5_1 | flag_l5_0; +wire index_l0_0 = !free_adr_mask[0]; +wire index_l0_1 = !free_adr_mask[2]; +wire index_l0_2 = !free_adr_mask[4]; +wire index_l0_3 = !free_adr_mask[6]; +wire index_l0_4 = !free_adr_mask[8]; +wire index_l0_5 = !free_adr_mask[10]; +wire index_l0_6 = !free_adr_mask[12]; +wire index_l0_7 = !free_adr_mask[14]; +wire index_l0_8 = !free_adr_mask[16]; +wire index_l0_9 = !free_adr_mask[18]; +wire index_l0_10 = !free_adr_mask[20]; +wire index_l0_11 = !free_adr_mask[22]; +wire index_l0_12 = !free_adr_mask[24]; +wire index_l0_13 = !free_adr_mask[26]; +wire index_l0_14 = !free_adr_mask[28]; +wire index_l0_15 = !free_adr_mask[30]; +wire index_l0_16 = !free_adr_mask[32]; +wire index_l0_17 = !free_adr_mask[34]; +wire index_l0_18 = !free_adr_mask[36]; +wire index_l0_19 = !free_adr_mask[38]; +wire index_l0_20 = !free_adr_mask[40]; +wire index_l0_21 = !free_adr_mask[42]; +wire index_l0_22 = !free_adr_mask[44]; +wire index_l0_23 = !free_adr_mask[46]; +wire index_l0_24 = !free_adr_mask[48]; +wire index_l0_25 = !free_adr_mask[50]; +wire index_l0_26 = !free_adr_mask[52]; +wire index_l0_27 = !free_adr_mask[54]; +wire index_l0_28 = !free_adr_mask[56]; +wire index_l0_29 = !free_adr_mask[58]; +wire index_l0_30 = !free_adr_mask[60]; +wire index_l0_31 = !free_adr_mask[62]; +wire index_l0_32 = !free_adr_mask[64]; +wire index_l0_33 = !free_adr_mask[66]; +wire index_l0_34 = !free_adr_mask[68]; +wire index_l0_35 = !free_adr_mask[70]; +wire index_l0_36 = !free_adr_mask[72]; +wire index_l0_37 = !free_adr_mask[74]; +wire index_l0_38 = !free_adr_mask[76]; +wire index_l0_39 = !free_adr_mask[78]; +wire index_l0_40 = !free_adr_mask[80]; +wire index_l0_41 = !free_adr_mask[82]; +wire index_l0_42 = !free_adr_mask[84]; +wire index_l0_43 = !free_adr_mask[86]; +wire index_l0_44 = !free_adr_mask[88]; +wire index_l0_45 = !free_adr_mask[90]; +wire index_l0_46 = !free_adr_mask[92]; +wire index_l0_47 = !free_adr_mask[94]; +wire index_l0_48 = !free_adr_mask[96]; +wire index_l0_49 = !free_adr_mask[98]; +wire index_l0_50 = !free_adr_mask[100]; +wire index_l0_51 = !free_adr_mask[102]; +wire index_l0_52 = !free_adr_mask[104]; +wire index_l0_53 = !free_adr_mask[106]; +wire index_l0_54 = !free_adr_mask[108]; +wire index_l0_55 = !free_adr_mask[110]; +wire index_l0_56 = !free_adr_mask[112]; +wire index_l0_57 = !free_adr_mask[114]; +wire index_l0_58 = !free_adr_mask[116]; +wire index_l0_59 = !free_adr_mask[118]; +wire index_l0_60 = !free_adr_mask[120]; +wire index_l0_61 = !free_adr_mask[122]; +wire index_l0_62 = !free_adr_mask[124]; +wire index_l0_63 = !free_adr_mask[126]; +wire index_l0_64 = !free_adr_mask[128]; +wire index_l0_65 = !free_adr_mask[130]; +wire index_l0_66 = !free_adr_mask[132]; +wire index_l0_67 = !free_adr_mask[134]; +wire index_l0_68 = !free_adr_mask[136]; +wire index_l0_69 = !free_adr_mask[138]; +wire index_l0_70 = !free_adr_mask[140]; +wire index_l0_71 = !free_adr_mask[142]; +wire index_l0_72 = !free_adr_mask[144]; +wire index_l0_73 = !free_adr_mask[146]; +wire index_l0_74 = !free_adr_mask[148]; +wire index_l0_75 = !free_adr_mask[150]; +wire index_l0_76 = !free_adr_mask[152]; +wire index_l0_77 = !free_adr_mask[154]; +wire index_l0_78 = !free_adr_mask[156]; +wire index_l0_79 = !free_adr_mask[158]; +wire index_l0_80 = !free_adr_mask[160]; +wire index_l0_81 = !free_adr_mask[162]; +wire index_l0_82 = !free_adr_mask[164]; +wire index_l0_83 = !free_adr_mask[166]; +wire index_l0_84 = !free_adr_mask[168]; +wire index_l0_85 = !free_adr_mask[170]; +wire index_l0_86 = !free_adr_mask[172]; +wire index_l0_87 = !free_adr_mask[174]; +wire index_l0_88 = !free_adr_mask[176]; +wire index_l0_89 = !free_adr_mask[178]; +wire index_l0_90 = !free_adr_mask[180]; +wire index_l0_91 = !free_adr_mask[182]; +wire index_l0_92 = !free_adr_mask[184]; +wire index_l0_93 = !free_adr_mask[186]; +wire index_l0_94 = !free_adr_mask[188]; +wire index_l0_95 = !free_adr_mask[190]; +wire index_l0_96 = !free_adr_mask[192]; +wire index_l0_97 = !free_adr_mask[194]; +wire index_l0_98 = !free_adr_mask[196]; +wire index_l0_99 = !free_adr_mask[198]; +wire index_l0_100 = !free_adr_mask[200]; +wire index_l0_101 = !free_adr_mask[202]; +wire index_l0_102 = !free_adr_mask[204]; +wire index_l0_103 = !free_adr_mask[206]; +wire index_l0_104 = !free_adr_mask[208]; +wire index_l0_105 = !free_adr_mask[210]; +wire index_l0_106 = !free_adr_mask[212]; +wire index_l0_107 = !free_adr_mask[214]; +wire index_l0_108 = !free_adr_mask[216]; +wire index_l0_109 = !free_adr_mask[218]; +wire index_l0_110 = !free_adr_mask[220]; +wire index_l0_111 = !free_adr_mask[222]; +wire index_l0_112 = !free_adr_mask[224]; +wire index_l0_113 = !free_adr_mask[226]; +wire index_l0_114 = !free_adr_mask[228]; +wire index_l0_115 = !free_adr_mask[230]; +wire index_l0_116 = !free_adr_mask[232]; +wire index_l0_117 = !free_adr_mask[234]; +wire index_l0_118 = !free_adr_mask[236]; +wire index_l0_119 = !free_adr_mask[238]; +wire index_l0_120 = !free_adr_mask[240]; +wire index_l0_121 = !free_adr_mask[242]; +wire index_l0_122 = !free_adr_mask[244]; +wire index_l0_123 = !free_adr_mask[246]; +wire index_l0_124 = !free_adr_mask[248]; +wire index_l0_125 = !free_adr_mask[250]; +wire index_l0_126 = !free_adr_mask[252]; +wire index_l0_127 = !free_adr_mask[254]; +wire [1:0] index_l1_0 = {!flag_l0_0,(flag_l0_0?index_l0_0:index_l0_1)}; +wire [1:0] index_l1_1 = {!flag_l0_2,(flag_l0_2?index_l0_2:index_l0_3)}; +wire [1:0] index_l1_2 = {!flag_l0_4,(flag_l0_4?index_l0_4:index_l0_5)}; +wire [1:0] index_l1_3 = {!flag_l0_6,(flag_l0_6?index_l0_6:index_l0_7)}; +wire [1:0] index_l1_4 = {!flag_l0_8,(flag_l0_8?index_l0_8:index_l0_9)}; +wire [1:0] index_l1_5 = {!flag_l0_10,(flag_l0_10?index_l0_10:index_l0_11)}; +wire [1:0] index_l1_6 = {!flag_l0_12,(flag_l0_12?index_l0_12:index_l0_13)}; +wire [1:0] index_l1_7 = {!flag_l0_14,(flag_l0_14?index_l0_14:index_l0_15)}; +wire [1:0] index_l1_8 = {!flag_l0_16,(flag_l0_16?index_l0_16:index_l0_17)}; +wire [1:0] index_l1_9 = {!flag_l0_18,(flag_l0_18?index_l0_18:index_l0_19)}; +wire [1:0] index_l1_10 = {!flag_l0_20,(flag_l0_20?index_l0_20:index_l0_21)}; +wire [1:0] index_l1_11 = {!flag_l0_22,(flag_l0_22?index_l0_22:index_l0_23)}; +wire [1:0] index_l1_12 = {!flag_l0_24,(flag_l0_24?index_l0_24:index_l0_25)}; +wire [1:0] index_l1_13 = {!flag_l0_26,(flag_l0_26?index_l0_26:index_l0_27)}; +wire [1:0] index_l1_14 = {!flag_l0_28,(flag_l0_28?index_l0_28:index_l0_29)}; +wire [1:0] index_l1_15 = {!flag_l0_30,(flag_l0_30?index_l0_30:index_l0_31)}; +wire [1:0] index_l1_16 = {!flag_l0_32,(flag_l0_32?index_l0_32:index_l0_33)}; +wire [1:0] index_l1_17 = {!flag_l0_34,(flag_l0_34?index_l0_34:index_l0_35)}; +wire [1:0] index_l1_18 = {!flag_l0_36,(flag_l0_36?index_l0_36:index_l0_37)}; +wire [1:0] index_l1_19 = {!flag_l0_38,(flag_l0_38?index_l0_38:index_l0_39)}; +wire [1:0] index_l1_20 = {!flag_l0_40,(flag_l0_40?index_l0_40:index_l0_41)}; +wire [1:0] index_l1_21 = {!flag_l0_42,(flag_l0_42?index_l0_42:index_l0_43)}; +wire [1:0] index_l1_22 = {!flag_l0_44,(flag_l0_44?index_l0_44:index_l0_45)}; +wire [1:0] index_l1_23 = {!flag_l0_46,(flag_l0_46?index_l0_46:index_l0_47)}; +wire [1:0] index_l1_24 = {!flag_l0_48,(flag_l0_48?index_l0_48:index_l0_49)}; +wire [1:0] index_l1_25 = {!flag_l0_50,(flag_l0_50?index_l0_50:index_l0_51)}; +wire [1:0] index_l1_26 = {!flag_l0_52,(flag_l0_52?index_l0_52:index_l0_53)}; +wire [1:0] index_l1_27 = {!flag_l0_54,(flag_l0_54?index_l0_54:index_l0_55)}; +wire [1:0] index_l1_28 = {!flag_l0_56,(flag_l0_56?index_l0_56:index_l0_57)}; +wire [1:0] index_l1_29 = {!flag_l0_58,(flag_l0_58?index_l0_58:index_l0_59)}; +wire [1:0] index_l1_30 = {!flag_l0_60,(flag_l0_60?index_l0_60:index_l0_61)}; +wire [1:0] index_l1_31 = {!flag_l0_62,(flag_l0_62?index_l0_62:index_l0_63)}; +wire [1:0] index_l1_32 = {!flag_l0_64,(flag_l0_64?index_l0_64:index_l0_65)}; +wire [1:0] index_l1_33 = {!flag_l0_66,(flag_l0_66?index_l0_66:index_l0_67)}; +wire [1:0] index_l1_34 = {!flag_l0_68,(flag_l0_68?index_l0_68:index_l0_69)}; +wire [1:0] index_l1_35 = {!flag_l0_70,(flag_l0_70?index_l0_70:index_l0_71)}; +wire [1:0] index_l1_36 = {!flag_l0_72,(flag_l0_72?index_l0_72:index_l0_73)}; +wire [1:0] index_l1_37 = {!flag_l0_74,(flag_l0_74?index_l0_74:index_l0_75)}; +wire [1:0] index_l1_38 = {!flag_l0_76,(flag_l0_76?index_l0_76:index_l0_77)}; +wire [1:0] index_l1_39 = {!flag_l0_78,(flag_l0_78?index_l0_78:index_l0_79)}; +wire [1:0] index_l1_40 = {!flag_l0_80,(flag_l0_80?index_l0_80:index_l0_81)}; +wire [1:0] index_l1_41 = {!flag_l0_82,(flag_l0_82?index_l0_82:index_l0_83)}; +wire [1:0] index_l1_42 = {!flag_l0_84,(flag_l0_84?index_l0_84:index_l0_85)}; +wire [1:0] index_l1_43 = {!flag_l0_86,(flag_l0_86?index_l0_86:index_l0_87)}; +wire [1:0] index_l1_44 = {!flag_l0_88,(flag_l0_88?index_l0_88:index_l0_89)}; +wire [1:0] index_l1_45 = {!flag_l0_90,(flag_l0_90?index_l0_90:index_l0_91)}; +wire [1:0] index_l1_46 = {!flag_l0_92,(flag_l0_92?index_l0_92:index_l0_93)}; +wire [1:0] index_l1_47 = {!flag_l0_94,(flag_l0_94?index_l0_94:index_l0_95)}; +wire [1:0] index_l1_48 = {!flag_l0_96,(flag_l0_96?index_l0_96:index_l0_97)}; +wire [1:0] index_l1_49 = {!flag_l0_98,(flag_l0_98?index_l0_98:index_l0_99)}; +wire [1:0] index_l1_50 = {!flag_l0_100,(flag_l0_100?index_l0_100:index_l0_101)}; +wire [1:0] index_l1_51 = {!flag_l0_102,(flag_l0_102?index_l0_102:index_l0_103)}; +wire [1:0] index_l1_52 = {!flag_l0_104,(flag_l0_104?index_l0_104:index_l0_105)}; +wire [1:0] index_l1_53 = {!flag_l0_106,(flag_l0_106?index_l0_106:index_l0_107)}; +wire [1:0] index_l1_54 = {!flag_l0_108,(flag_l0_108?index_l0_108:index_l0_109)}; +wire [1:0] index_l1_55 = {!flag_l0_110,(flag_l0_110?index_l0_110:index_l0_111)}; +wire [1:0] index_l1_56 = {!flag_l0_112,(flag_l0_112?index_l0_112:index_l0_113)}; +wire [1:0] index_l1_57 = {!flag_l0_114,(flag_l0_114?index_l0_114:index_l0_115)}; +wire [1:0] index_l1_58 = {!flag_l0_116,(flag_l0_116?index_l0_116:index_l0_117)}; +wire [1:0] index_l1_59 = {!flag_l0_118,(flag_l0_118?index_l0_118:index_l0_119)}; +wire [1:0] index_l1_60 = {!flag_l0_120,(flag_l0_120?index_l0_120:index_l0_121)}; +wire [1:0] index_l1_61 = {!flag_l0_122,(flag_l0_122?index_l0_122:index_l0_123)}; +wire [1:0] index_l1_62 = {!flag_l0_124,(flag_l0_124?index_l0_124:index_l0_125)}; +wire [1:0] index_l1_63 = {!flag_l0_126,(flag_l0_126?index_l0_126:index_l0_127)}; +wire [2:0] index_l2_0 = {!flag_l1_0,(flag_l1_0?index_l1_0:index_l1_1)}; +wire [2:0] index_l2_1 = {!flag_l1_2,(flag_l1_2?index_l1_2:index_l1_3)}; +wire [2:0] index_l2_2 = {!flag_l1_4,(flag_l1_4?index_l1_4:index_l1_5)}; +wire [2:0] index_l2_3 = {!flag_l1_6,(flag_l1_6?index_l1_6:index_l1_7)}; +wire [2:0] index_l2_4 = {!flag_l1_8,(flag_l1_8?index_l1_8:index_l1_9)}; +wire [2:0] index_l2_5 = {!flag_l1_10,(flag_l1_10?index_l1_10:index_l1_11)}; +wire [2:0] index_l2_6 = {!flag_l1_12,(flag_l1_12?index_l1_12:index_l1_13)}; +wire [2:0] index_l2_7 = {!flag_l1_14,(flag_l1_14?index_l1_14:index_l1_15)}; +wire [2:0] index_l2_8 = {!flag_l1_16,(flag_l1_16?index_l1_16:index_l1_17)}; +wire [2:0] index_l2_9 = {!flag_l1_18,(flag_l1_18?index_l1_18:index_l1_19)}; +wire [2:0] index_l2_10 = {!flag_l1_20,(flag_l1_20?index_l1_20:index_l1_21)}; +wire [2:0] index_l2_11 = {!flag_l1_22,(flag_l1_22?index_l1_22:index_l1_23)}; +wire [2:0] index_l2_12 = {!flag_l1_24,(flag_l1_24?index_l1_24:index_l1_25)}; +wire [2:0] index_l2_13 = {!flag_l1_26,(flag_l1_26?index_l1_26:index_l1_27)}; +wire [2:0] index_l2_14 = {!flag_l1_28,(flag_l1_28?index_l1_28:index_l1_29)}; +wire [2:0] index_l2_15 = {!flag_l1_30,(flag_l1_30?index_l1_30:index_l1_31)}; +wire [2:0] index_l2_16 = {!flag_l1_32,(flag_l1_32?index_l1_32:index_l1_33)}; +wire [2:0] index_l2_17 = {!flag_l1_34,(flag_l1_34?index_l1_34:index_l1_35)}; +wire [2:0] index_l2_18 = {!flag_l1_36,(flag_l1_36?index_l1_36:index_l1_37)}; +wire [2:0] index_l2_19 = {!flag_l1_38,(flag_l1_38?index_l1_38:index_l1_39)}; +wire [2:0] index_l2_20 = {!flag_l1_40,(flag_l1_40?index_l1_40:index_l1_41)}; +wire [2:0] index_l2_21 = {!flag_l1_42,(flag_l1_42?index_l1_42:index_l1_43)}; +wire [2:0] index_l2_22 = {!flag_l1_44,(flag_l1_44?index_l1_44:index_l1_45)}; +wire [2:0] index_l2_23 = {!flag_l1_46,(flag_l1_46?index_l1_46:index_l1_47)}; +wire [2:0] index_l2_24 = {!flag_l1_48,(flag_l1_48?index_l1_48:index_l1_49)}; +wire [2:0] index_l2_25 = {!flag_l1_50,(flag_l1_50?index_l1_50:index_l1_51)}; +wire [2:0] index_l2_26 = {!flag_l1_52,(flag_l1_52?index_l1_52:index_l1_53)}; +wire [2:0] index_l2_27 = {!flag_l1_54,(flag_l1_54?index_l1_54:index_l1_55)}; +wire [2:0] index_l2_28 = {!flag_l1_56,(flag_l1_56?index_l1_56:index_l1_57)}; +wire [2:0] index_l2_29 = {!flag_l1_58,(flag_l1_58?index_l1_58:index_l1_59)}; +wire [2:0] index_l2_30 = {!flag_l1_60,(flag_l1_60?index_l1_60:index_l1_61)}; +wire [2:0] index_l2_31 = {!flag_l1_62,(flag_l1_62?index_l1_62:index_l1_63)}; +wire [3:0] index_l3_0 = {!flag_l2_0,(flag_l2_0?index_l2_0:index_l2_1)}; +wire [3:0] index_l3_1 = {!flag_l2_2,(flag_l2_2?index_l2_2:index_l2_3)}; +wire [3:0] index_l3_2 = {!flag_l2_4,(flag_l2_4?index_l2_4:index_l2_5)}; +wire [3:0] index_l3_3 = {!flag_l2_6,(flag_l2_6?index_l2_6:index_l2_7)}; +wire [3:0] index_l3_4 = {!flag_l2_8,(flag_l2_8?index_l2_8:index_l2_9)}; +wire [3:0] index_l3_5 = {!flag_l2_10,(flag_l2_10?index_l2_10:index_l2_11)}; +wire [3:0] index_l3_6 = {!flag_l2_12,(flag_l2_12?index_l2_12:index_l2_13)}; +wire [3:0] index_l3_7 = {!flag_l2_14,(flag_l2_14?index_l2_14:index_l2_15)}; +wire [3:0] index_l3_8 = {!flag_l2_16,(flag_l2_16?index_l2_16:index_l2_17)}; +wire [3:0] index_l3_9 = {!flag_l2_18,(flag_l2_18?index_l2_18:index_l2_19)}; +wire [3:0] index_l3_10 = {!flag_l2_20,(flag_l2_20?index_l2_20:index_l2_21)}; +wire [3:0] index_l3_11 = {!flag_l2_22,(flag_l2_22?index_l2_22:index_l2_23)}; +wire [3:0] index_l3_12 = {!flag_l2_24,(flag_l2_24?index_l2_24:index_l2_25)}; +wire [3:0] index_l3_13 = {!flag_l2_26,(flag_l2_26?index_l2_26:index_l2_27)}; +wire [3:0] index_l3_14 = {!flag_l2_28,(flag_l2_28?index_l2_28:index_l2_29)}; +wire [3:0] index_l3_15 = {!flag_l2_30,(flag_l2_30?index_l2_30:index_l2_31)}; +wire [4:0] index_l4_0 = {!flag_l3_0,(flag_l3_0?index_l3_0:index_l3_1)}; +wire [4:0] index_l4_1 = {!flag_l3_2,(flag_l3_2?index_l3_2:index_l3_3)}; +wire [4:0] index_l4_2 = {!flag_l3_4,(flag_l3_4?index_l3_4:index_l3_5)}; +wire [4:0] index_l4_3 = {!flag_l3_6,(flag_l3_6?index_l3_6:index_l3_7)}; +wire [4:0] index_l4_4 = {!flag_l3_8,(flag_l3_8?index_l3_8:index_l3_9)}; +wire [4:0] index_l4_5 = {!flag_l3_10,(flag_l3_10?index_l3_10:index_l3_11)}; +wire [4:0] index_l4_6 = {!flag_l3_12,(flag_l3_12?index_l3_12:index_l3_13)}; +wire [4:0] index_l4_7 = {!flag_l3_14,(flag_l3_14?index_l3_14:index_l3_15)}; +wire [5:0] index_l5_0 = {!flag_l4_0,(flag_l4_0?index_l4_0:index_l4_1)}; +wire [5:0] index_l5_1 = {!flag_l4_2,(flag_l4_2?index_l4_2:index_l4_3)}; +wire [5:0] index_l5_2 = {!flag_l4_4,(flag_l4_4?index_l4_4:index_l4_5)}; +wire [5:0] index_l5_3 = {!flag_l4_6,(flag_l4_6?index_l4_6:index_l4_7)}; +wire [6:0] index_l6_0 = {!flag_l5_0,(flag_l5_0?index_l5_0:index_l5_1)}; +wire [6:0] index_l6_1 = {!flag_l5_2,(flag_l5_2?index_l5_2:index_l5_3)}; +wire [7:0] index_l7_0 = {!flag_l6_0,(flag_l6_0?index_l6_0:index_l6_1)}; +assign free_adr_index[7:0] = index_l7_0[7:0]; +assign wr_popping = rd_popping; +// +// READ SIDE +// +// +// credits for taker are simply rd_pushing* +// +reg [4:0] cq_rd_credit; // registered out take credits +reg rd_pushing_q; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_credit <= 5'd0; + rd_pushing_q <= 1'b0; + end else begin + if ( rd_pushing || rd_pushing_q ) begin + cq_rd_credit[0] <= rd_pushing && rd_pushing_thread_id == 3'd0; + cq_rd_credit[1] <= rd_pushing && rd_pushing_thread_id == 3'd1; + cq_rd_credit[2] <= rd_pushing && rd_pushing_thread_id == 3'd2; + cq_rd_credit[3] <= rd_pushing && rd_pushing_thread_id == 3'd3; + cq_rd_credit[4] <= rd_pushing && rd_pushing_thread_id == 3'd4; + rd_pushing_q <= rd_pushing; + end + end +end +wire rd_pushing0 = rd_pushing && rd_pushing_thread_id == 3'd0; +wire rd_pushing1 = rd_pushing && rd_pushing_thread_id == 3'd1; +wire rd_pushing2 = rd_pushing && rd_pushing_thread_id == 3'd2; +wire rd_pushing3 = rd_pushing && rd_pushing_thread_id == 3'd3; +wire rd_pushing4 = rd_pushing && rd_pushing_thread_id == 3'd4; +wire rd_take0 = cq_rd_take && cq_rd_take_thread_id == 3'd0; +wire rd_take1 = cq_rd_take && cq_rd_take_thread_id == 3'd1; +wire rd_take2 = cq_rd_take && cq_rd_take_thread_id == 3'd2; +wire rd_take3 = cq_rd_take && cq_rd_take_thread_id == 3'd3; +wire rd_take4 = cq_rd_take && cq_rd_take_thread_id == 3'd4; +reg [7:0] head0; // thread 0's head pointer +reg [7:0] tail0; // thread 0's tail pointer +reg [7:0] head1; // thread 1's head pointer +reg [7:0] tail1; // thread 1's tail pointer +reg [7:0] head2; // thread 2's head pointer +reg [7:0] tail2; // thread 2's tail pointer +reg [7:0] head3; // thread 3's head pointer +reg [7:0] tail3; // thread 3's tail pointer +reg [7:0] head4; // thread 4's head pointer +reg [7:0] tail4; // thread 4's tail pointer +reg [4:0] rd_take_n_dly; +reg rd_take_dly_cg; +wire update_rd_take_n_dly = cq_rd_take || rd_take_dly_cg; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly_cg <= 1'b0; + rd_take_n_dly <= {5{1'b0}}; + end else begin + rd_take_dly_cg <= cq_rd_take; + if ( update_rd_take_n_dly ) begin + rd_take_n_dly <= {rd_take4,rd_take3,rd_take2,rd_take1,rd_take0}; + end +//synopsys translate_off + else if ( !update_rd_take_n_dly) begin + end else begin + rd_take_n_dly <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] adr_ram_wr_adr; +wire [7:0] adr_ram_wr_data; +reg adr_ram_wr_enable; +reg [7:0] adr_ram_rd_adr; +wire [7:0] adr_ram_rd_data; +reg adr_ram_rd_enable; +reg [8:0] cq_rd_count0; +wire [8:0] rd_count0_next; +reg [8:0] cq_rd_count1; +wire [8:0] rd_count1_next; +reg [8:0] cq_rd_count2; +wire [8:0] rd_count2_next; +reg [8:0] cq_rd_count3; +wire [8:0] rd_count3_next; +reg [8:0] cq_rd_count4; +wire [8:0] rd_count4_next; +assign rd_count0_next = + rd_pushing0 ? ( rd_take0 ? cq_rd_count0 : cq_rd_count0 + 1'd1 ) : + ( rd_take0 ? cq_rd_count0 - 1'd1 : cq_rd_count0 ); +assign rd_count1_next = + rd_pushing1 ? ( rd_take1 ? cq_rd_count1 : cq_rd_count1 + 1'd1 ) : + ( rd_take1 ? cq_rd_count1 - 1'd1 : cq_rd_count1 ); +assign rd_count2_next = + rd_pushing2 ? ( rd_take2 ? cq_rd_count2 : cq_rd_count2 + 1'd1 ) : + ( rd_take2 ? cq_rd_count2 - 1'd1 : cq_rd_count2 ); +assign rd_count3_next = + rd_pushing3 ? ( rd_take3 ? cq_rd_count3 : cq_rd_count3 + 1'd1 ) : + ( rd_take3 ? cq_rd_count3 - 1'd1 : cq_rd_count3 ); +assign rd_count4_next = + rd_pushing4 ? ( rd_take4 ? cq_rd_count4 : cq_rd_count4 + 1'd1 ) : + ( rd_take4 ? cq_rd_count4 - 1'd1 : cq_rd_count4 ); +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_count0 <= 9'd0; + cq_rd_count1 <= 9'd0; + cq_rd_count2 <= 9'd0; + cq_rd_count3 <= 9'd0; + cq_rd_count4 <= 9'd0; + end else begin + if ( rd_pushing0 ^ rd_take0 ) begin + cq_rd_count0 <= rd_count0_next; + end +//synopsys translate_off + else if ( !(rd_pushing0 ^ rd_take0) ) begin + end else begin + cq_rd_count0 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing1 ^ rd_take1 ) begin + cq_rd_count1 <= rd_count1_next; + end +//synopsys translate_off + else if ( !(rd_pushing1 ^ rd_take1) ) begin + end else begin + cq_rd_count1 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing2 ^ rd_take2 ) begin + cq_rd_count2 <= rd_count2_next; + end +//synopsys translate_off + else if ( !(rd_pushing2 ^ rd_take2) ) begin + end else begin + cq_rd_count2 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing3 ^ rd_take3 ) begin + cq_rd_count3 <= rd_count3_next; + end +//synopsys translate_off + else if ( !(rd_pushing3 ^ rd_take3) ) begin + end else begin + cq_rd_count3 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing4 ^ rd_take4 ) begin + cq_rd_count4 <= rd_count4_next; + end +//synopsys translate_off + else if ( !(rd_pushing4 ^ rd_take4) ) begin + end else begin + cq_rd_count4 <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [4:0] update_head; +wire [4:0] update_head_next; +assign update_head_next[0] = (rd_take0 && cq_rd_count0 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[1] = (rd_take1 && cq_rd_count1 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[2] = (rd_take2 && cq_rd_count2 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[3] = (rd_take3 && cq_rd_count3 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[4] = (rd_take4 && cq_rd_count4 > 9'd1) ? 1'b1 : 1'b0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + update_head <= 5'd0; + end else begin + if ( rd_pushing || cq_rd_take ) begin + update_head <= update_head_next; + end +//synopsys translate_off + else if ( !(rd_pushing || cq_rd_take) ) begin + end else begin + update_head <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(posedge nvdla_core_clk_mgated) begin + if ( rd_pushing0 ) begin + tail0 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing0 ) begin + end else begin + tail0 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing0 && cq_rd_count0 == 9'd0 ) || + (rd_pushing0 && rd_take0 && cq_rd_count0 == 9'd1) ) begin + head0 <= rd_pushing_adr; + end else if ( update_head[0] ) begin + head0 <= adr_ram_rd_data; + end + if ( rd_pushing1 ) begin + tail1 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing1 ) begin + end else begin + tail1 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing1 && cq_rd_count1 == 9'd0 ) || + (rd_pushing1 && rd_take1 && cq_rd_count1 == 9'd1) ) begin + head1 <= rd_pushing_adr; + end else if ( update_head[1] ) begin + head1 <= adr_ram_rd_data; + end + if ( rd_pushing2 ) begin + tail2 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing2 ) begin + end else begin + tail2 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing2 && cq_rd_count2 == 9'd0 ) || + (rd_pushing2 && rd_take2 && cq_rd_count2 == 9'd1) ) begin + head2 <= rd_pushing_adr; + end else if ( update_head[2] ) begin + head2 <= adr_ram_rd_data; + end + if ( rd_pushing3 ) begin + tail3 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing3 ) begin + end else begin + tail3 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing3 && cq_rd_count3 == 9'd0 ) || + (rd_pushing3 && rd_take3 && cq_rd_count3 == 9'd1) ) begin + head3 <= rd_pushing_adr; + end else if ( update_head[3] ) begin + head3 <= adr_ram_rd_data; + end + if ( rd_pushing4 ) begin + tail4 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing4 ) begin + end else begin + tail4 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing4 && cq_rd_count4 == 9'd0 ) || + (rd_pushing4 && rd_take4 && cq_rd_count4 == 9'd1) ) begin + head4 <= rd_pushing_adr; + end else if ( update_head[4] ) begin + head4 <= adr_ram_rd_data; + end +end +nv_ram_rwst_256x8 adr_ram ( + .clk ( nvdla_core_clk ) + , .wa ( adr_ram_wr_adr ) + , .we ( adr_ram_wr_enable ) + , .di ( adr_ram_wr_data ) + , .ra ( adr_ram_rd_adr ) + , .re ( adr_ram_rd_enable ) + , .dout ( adr_ram_rd_data ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + ); +assign adr_ram_wr_data = rd_pushing_adr; +always @(*) begin + case( rd_pushing_thread_id ) + 3'd0: adr_ram_wr_adr = tail0; + 3'd1: adr_ram_wr_adr = tail1; + 3'd2: adr_ram_wr_adr = tail2; + 3'd3: adr_ram_wr_adr = tail3; + 3'd4: adr_ram_wr_adr = tail4; +//VCS coverage off + default: adr_ram_wr_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( rd_pushing_thread_id ) + 3'd0: adr_ram_wr_enable = rd_pushing && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 3'd1: adr_ram_wr_enable = rd_pushing && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 3'd2: adr_ram_wr_enable = rd_pushing && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 3'd3: adr_ram_wr_enable = rd_pushing && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 3'd4: adr_ram_wr_enable = rd_pushing && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_wr_enable = !rd_pushing ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 3'd0: adr_ram_rd_enable = cq_rd_take && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 3'd1: adr_ram_rd_enable = cq_rd_take && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 3'd2: adr_ram_rd_enable = cq_rd_take && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 3'd3: adr_ram_rd_enable = cq_rd_take && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 3'd4: adr_ram_rd_enable = cq_rd_take && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_rd_enable = !cq_rd_take ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 3'd0: adr_ram_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 3'd1: adr_ram_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 3'd2: adr_ram_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 3'd3: adr_ram_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 3'd4: adr_ram_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; +//VCS coverage off + default: adr_ram_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 3'd0: cq_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 3'd1: cq_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 3'd2: cq_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 3'd3: cq_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 3'd4: cq_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; +//VCS coverage off + default: cq_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +// +// take data comes out next cycle for non-ff rams. +// +reg rd_take_dly; +assign rd_popping = rd_take_dly; +reg [7:0] rd_adr_dly; +assign rd_popping_adr = rd_adr_dly; +assign rd_enable = cq_rd_take; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly <= 1'b0; + end else begin + rd_take_dly <= cq_rd_take; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( cq_rd_take ) begin + rd_adr_dly <= cq_rd_adr; + end +//synopsys translate_off + else if ( !(cq_rd_take) ) begin + end else begin + rd_adr_dly <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// +// -rd_take_to_rd_busy conversion (conceptually outside the fifo except for ra2 bypass) +// +wire [4:0] cq_rd_take_elig; // mask of threads that can do takes this cycle +wire rd_pre_bypassing0; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing0; // between cq_rd0_pvld and cq_rd0_prdy when doing full bypass +reg [2:0] rd_skid0_0; // head skid reg +reg [2:0] rd_skid0_1; // head+1 skid reg +reg [2:0] rd_skid0_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid0_0_vld; // head skid reg has valid data +reg rd_skid0_1_vld; // head+1 skid reg has valid data +reg rd_skid0_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd0_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_prdy_d <= 1'b1; + end else begin + cq_rd0_prdy_d <= cq_rd0_prdy; + end +end +assign cq_rd0_pvld = rd_skid0_0_vld || rd_pre_bypassing0; // full bypass for 0-latency +assign cq_rd0_pd = rd_skid0_0_vld ? rd_skid0_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld)) ) begin + rd_skid0_0 <= rd_take_n_dly[0] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld ) begin + rd_skid0_0 <= rd_skid0_1; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld) ) begin + end else begin + rd_skid0_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld)) ) begin + rd_skid0_1 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld ) begin + rd_skid0_1 <= rd_skid0_2; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld) ) begin + end else begin + rd_skid0_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy)) ) begin + rd_skid0_2 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy))) ) begin + end else begin + rd_skid0_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid0_0_vld <= 1'b0; + rd_skid0_1_vld <= 1'b0; + rd_skid0_2_vld <= 1'b0; + end else begin + rd_skid0_0_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_1_vld || (rd_bypassing0 && rd_skid0_0_vld) || rd_take_n_dly[0]) : (rd_skid0_0_vld || rd_bypassing0 || rd_take_n_dly[0]); + rd_skid0_1_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))) : (rd_skid0_1_vld || (rd_skid0_0_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage off + rd_skid0_2_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld && (rd_bypassing0 || rd_take_n_dly[0])) : (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd0_credits; // unused credits +reg cq_rd0_credits_ne0; +wire [8:0] cq_rd0_credits_w_take_next = cq_rd0_credits + cq_rd_credit[0] - 1'b1; +wire [8:0] cq_rd0_credits_wo_take_next = cq_rd0_credits + cq_rd_credit[0]; +wire [8:0] cq_rd0_credits_next = rd_take0 ? cq_rd0_credits_w_take_next : cq_rd0_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[0] = (cq_rd0_prdy_d || !rd_skid0_0_vld || !rd_skid0_1_vld || (!rd_skid0_2_vld && !rd_take_n_dly[0])) && (cq_rd_credit[0] || cq_rd0_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing0 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd0) && cq_rd0_credits == 0 && !cq_rd_credit[0] && (!rd_take_n_dly[0] || rd_skid0_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing0 = rd_pre_bypassing0 && (!rd_skid0_2_vld || !rd_skid0_1_vld || !(!cq_rd0_prdy_d && rd_skid0_0_vld && rd_skid0_1_vld)) && !rd_take_n_dly[0]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_credits <= 9'd0; + cq_rd0_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[0] | rd_take0 ) begin + cq_rd0_credits <= cq_rd0_credits_next; + cq_rd0_credits_ne0 <= rd_take0 ? (cq_rd0_credits_w_take_next != 0) : (cq_rd0_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[0] | rd_take0) ) begin + end else begin + cq_rd0_credits <= {9{`x_or_0}}; + cq_rd0_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing1; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing1; // between cq_rd1_pvld and cq_rd1_prdy when doing full bypass +reg [2:0] rd_skid1_0; // head skid reg +reg [2:0] rd_skid1_1; // head+1 skid reg +reg [2:0] rd_skid1_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid1_0_vld; // head skid reg has valid data +reg rd_skid1_1_vld; // head+1 skid reg has valid data +reg rd_skid1_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd1_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_prdy_d <= 1'b1; + end else begin + cq_rd1_prdy_d <= cq_rd1_prdy; + end +end +assign cq_rd1_pvld = rd_skid1_0_vld || rd_pre_bypassing1; // full bypass for 0-latency +assign cq_rd1_pd = rd_skid1_0_vld ? rd_skid1_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld)) ) begin + rd_skid1_0 <= rd_take_n_dly[1] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld ) begin + rd_skid1_0 <= rd_skid1_1; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld) ) begin + end else begin + rd_skid1_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld)) ) begin + rd_skid1_1 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld ) begin + rd_skid1_1 <= rd_skid1_2; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld) ) begin + end else begin + rd_skid1_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy)) ) begin + rd_skid1_2 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy))) ) begin + end else begin + rd_skid1_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid1_0_vld <= 1'b0; + rd_skid1_1_vld <= 1'b0; + rd_skid1_2_vld <= 1'b0; + end else begin + rd_skid1_0_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_1_vld || (rd_bypassing1 && rd_skid1_0_vld) || rd_take_n_dly[1]) : (rd_skid1_0_vld || rd_bypassing1 || rd_take_n_dly[1]); + rd_skid1_1_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))) : (rd_skid1_1_vld || (rd_skid1_0_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage off + rd_skid1_2_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld && (rd_bypassing1 || rd_take_n_dly[1])) : (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd1_credits; // unused credits +reg cq_rd1_credits_ne0; +wire [8:0] cq_rd1_credits_w_take_next = cq_rd1_credits + cq_rd_credit[1] - 1'b1; +wire [8:0] cq_rd1_credits_wo_take_next = cq_rd1_credits + cq_rd_credit[1]; +wire [8:0] cq_rd1_credits_next = rd_take1 ? cq_rd1_credits_w_take_next : cq_rd1_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[1] = (cq_rd1_prdy_d || !rd_skid1_0_vld || !rd_skid1_1_vld || (!rd_skid1_2_vld && !rd_take_n_dly[1])) && (cq_rd_credit[1] || cq_rd1_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing1 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd1) && cq_rd1_credits == 0 && !cq_rd_credit[1] && (!rd_take_n_dly[1] || rd_skid1_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing1 = rd_pre_bypassing1 && (!rd_skid1_2_vld || !rd_skid1_1_vld || !(!cq_rd1_prdy_d && rd_skid1_0_vld && rd_skid1_1_vld)) && !rd_take_n_dly[1]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_credits <= 9'd0; + cq_rd1_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[1] | rd_take1 ) begin + cq_rd1_credits <= cq_rd1_credits_next; + cq_rd1_credits_ne0 <= rd_take1 ? (cq_rd1_credits_w_take_next != 0) : (cq_rd1_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[1] | rd_take1) ) begin + end else begin + cq_rd1_credits <= {9{`x_or_0}}; + cq_rd1_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing2; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing2; // between cq_rd2_pvld and cq_rd2_prdy when doing full bypass +reg [2:0] rd_skid2_0; // head skid reg +reg [2:0] rd_skid2_1; // head+1 skid reg +reg [2:0] rd_skid2_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid2_0_vld; // head skid reg has valid data +reg rd_skid2_1_vld; // head+1 skid reg has valid data +reg rd_skid2_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd2_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_prdy_d <= 1'b1; + end else begin + cq_rd2_prdy_d <= cq_rd2_prdy; + end +end +assign cq_rd2_pvld = rd_skid2_0_vld || rd_pre_bypassing2; // full bypass for 0-latency +assign cq_rd2_pd = rd_skid2_0_vld ? rd_skid2_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld)) ) begin + rd_skid2_0 <= rd_take_n_dly[2] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld ) begin + rd_skid2_0 <= rd_skid2_1; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld) ) begin + end else begin + rd_skid2_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld)) ) begin + rd_skid2_1 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld ) begin + rd_skid2_1 <= rd_skid2_2; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld) ) begin + end else begin + rd_skid2_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy)) ) begin + rd_skid2_2 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy))) ) begin + end else begin + rd_skid2_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid2_0_vld <= 1'b0; + rd_skid2_1_vld <= 1'b0; + rd_skid2_2_vld <= 1'b0; + end else begin + rd_skid2_0_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_1_vld || (rd_bypassing2 && rd_skid2_0_vld) || rd_take_n_dly[2]) : (rd_skid2_0_vld || rd_bypassing2 || rd_take_n_dly[2]); + rd_skid2_1_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))) : (rd_skid2_1_vld || (rd_skid2_0_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage off + rd_skid2_2_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld && (rd_bypassing2 || rd_take_n_dly[2])) : (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd2_credits; // unused credits +reg cq_rd2_credits_ne0; +wire [8:0] cq_rd2_credits_w_take_next = cq_rd2_credits + cq_rd_credit[2] - 1'b1; +wire [8:0] cq_rd2_credits_wo_take_next = cq_rd2_credits + cq_rd_credit[2]; +wire [8:0] cq_rd2_credits_next = rd_take2 ? cq_rd2_credits_w_take_next : cq_rd2_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[2] = (cq_rd2_prdy_d || !rd_skid2_0_vld || !rd_skid2_1_vld || (!rd_skid2_2_vld && !rd_take_n_dly[2])) && (cq_rd_credit[2] || cq_rd2_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing2 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd2) && cq_rd2_credits == 0 && !cq_rd_credit[2] && (!rd_take_n_dly[2] || rd_skid2_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing2 = rd_pre_bypassing2 && (!rd_skid2_2_vld || !rd_skid2_1_vld || !(!cq_rd2_prdy_d && rd_skid2_0_vld && rd_skid2_1_vld)) && !rd_take_n_dly[2]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_credits <= 9'd0; + cq_rd2_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[2] | rd_take2 ) begin + cq_rd2_credits <= cq_rd2_credits_next; + cq_rd2_credits_ne0 <= rd_take2 ? (cq_rd2_credits_w_take_next != 0) : (cq_rd2_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[2] | rd_take2) ) begin + end else begin + cq_rd2_credits <= {9{`x_or_0}}; + cq_rd2_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing3; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing3; // between cq_rd3_pvld and cq_rd3_prdy when doing full bypass +reg [2:0] rd_skid3_0; // head skid reg +reg [2:0] rd_skid3_1; // head+1 skid reg +reg [2:0] rd_skid3_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid3_0_vld; // head skid reg has valid data +reg rd_skid3_1_vld; // head+1 skid reg has valid data +reg rd_skid3_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd3_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_prdy_d <= 1'b1; + end else begin + cq_rd3_prdy_d <= cq_rd3_prdy; + end +end +assign cq_rd3_pvld = rd_skid3_0_vld || rd_pre_bypassing3; // full bypass for 0-latency +assign cq_rd3_pd = rd_skid3_0_vld ? rd_skid3_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld)) ) begin + rd_skid3_0 <= rd_take_n_dly[3] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld ) begin + rd_skid3_0 <= rd_skid3_1; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld) ) begin + end else begin + rd_skid3_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld)) ) begin + rd_skid3_1 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld ) begin + rd_skid3_1 <= rd_skid3_2; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld) ) begin + end else begin + rd_skid3_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy)) ) begin + rd_skid3_2 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy))) ) begin + end else begin + rd_skid3_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid3_0_vld <= 1'b0; + rd_skid3_1_vld <= 1'b0; + rd_skid3_2_vld <= 1'b0; + end else begin + rd_skid3_0_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_1_vld || (rd_bypassing3 && rd_skid3_0_vld) || rd_take_n_dly[3]) : (rd_skid3_0_vld || rd_bypassing3 || rd_take_n_dly[3]); + rd_skid3_1_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))) : (rd_skid3_1_vld || (rd_skid3_0_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage off + rd_skid3_2_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld && (rd_bypassing3 || rd_take_n_dly[3])) : (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd3_credits; // unused credits +reg cq_rd3_credits_ne0; +wire [8:0] cq_rd3_credits_w_take_next = cq_rd3_credits + cq_rd_credit[3] - 1'b1; +wire [8:0] cq_rd3_credits_wo_take_next = cq_rd3_credits + cq_rd_credit[3]; +wire [8:0] cq_rd3_credits_next = rd_take3 ? cq_rd3_credits_w_take_next : cq_rd3_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[3] = (cq_rd3_prdy_d || !rd_skid3_0_vld || !rd_skid3_1_vld || (!rd_skid3_2_vld && !rd_take_n_dly[3])) && (cq_rd_credit[3] || cq_rd3_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing3 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd3) && cq_rd3_credits == 0 && !cq_rd_credit[3] && (!rd_take_n_dly[3] || rd_skid3_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing3 = rd_pre_bypassing3 && (!rd_skid3_2_vld || !rd_skid3_1_vld || !(!cq_rd3_prdy_d && rd_skid3_0_vld && rd_skid3_1_vld)) && !rd_take_n_dly[3]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_credits <= 9'd0; + cq_rd3_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[3] | rd_take3 ) begin + cq_rd3_credits <= cq_rd3_credits_next; + cq_rd3_credits_ne0 <= rd_take3 ? (cq_rd3_credits_w_take_next != 0) : (cq_rd3_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[3] | rd_take3) ) begin + end else begin + cq_rd3_credits <= {9{`x_or_0}}; + cq_rd3_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing4; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing4; // between cq_rd4_pvld and cq_rd4_prdy when doing full bypass +reg [2:0] rd_skid4_0; // head skid reg +reg [2:0] rd_skid4_1; // head+1 skid reg +reg [2:0] rd_skid4_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid4_0_vld; // head skid reg has valid data +reg rd_skid4_1_vld; // head+1 skid reg has valid data +reg rd_skid4_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd4_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_prdy_d <= 1'b1; + end else begin + cq_rd4_prdy_d <= cq_rd4_prdy; + end +end +assign cq_rd4_pvld = rd_skid4_0_vld || rd_pre_bypassing4; // full bypass for 0-latency +assign cq_rd4_pd = rd_skid4_0_vld ? rd_skid4_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld)) ) begin + rd_skid4_0 <= rd_take_n_dly[4] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld ) begin + rd_skid4_0 <= rd_skid4_1; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld) ) begin + end else begin + rd_skid4_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld)) ) begin + rd_skid4_1 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld ) begin + rd_skid4_1 <= rd_skid4_2; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld) ) begin + end else begin + rd_skid4_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy)) ) begin + rd_skid4_2 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy))) ) begin + end else begin + rd_skid4_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid4_0_vld <= 1'b0; + rd_skid4_1_vld <= 1'b0; + rd_skid4_2_vld <= 1'b0; + end else begin + rd_skid4_0_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_1_vld || (rd_bypassing4 && rd_skid4_0_vld) || rd_take_n_dly[4]) : (rd_skid4_0_vld || rd_bypassing4 || rd_take_n_dly[4]); + rd_skid4_1_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))) : (rd_skid4_1_vld || (rd_skid4_0_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage off + rd_skid4_2_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld && (rd_bypassing4 || rd_take_n_dly[4])) : (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd4_credits; // unused credits +reg cq_rd4_credits_ne0; +wire [8:0] cq_rd4_credits_w_take_next = cq_rd4_credits + cq_rd_credit[4] - 1'b1; +wire [8:0] cq_rd4_credits_wo_take_next = cq_rd4_credits + cq_rd_credit[4]; +wire [8:0] cq_rd4_credits_next = rd_take4 ? cq_rd4_credits_w_take_next : cq_rd4_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[4] = (cq_rd4_prdy_d || !rd_skid4_0_vld || !rd_skid4_1_vld || (!rd_skid4_2_vld && !rd_take_n_dly[4])) && (cq_rd_credit[4] || cq_rd4_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing4 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd4) && cq_rd4_credits == 0 && !cq_rd_credit[4] && (!rd_take_n_dly[4] || rd_skid4_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing4 = rd_pre_bypassing4 && (!rd_skid4_2_vld || !rd_skid4_1_vld || !(!cq_rd4_prdy_d && rd_skid4_0_vld && rd_skid4_1_vld)) && !rd_take_n_dly[4]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_credits <= 9'd0; + cq_rd4_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[4] | rd_take4 ) begin + cq_rd4_credits <= cq_rd4_credits_next; + cq_rd4_credits_ne0 <= rd_take4 ? (cq_rd4_credits_w_take_next != 0) : (cq_rd4_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[4] | rd_take4) ) begin + end else begin + cq_rd4_credits <= {9{`x_or_0}}; + cq_rd4_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +// rd_take round-robin arbiter (similar to arbgen output) +// +assign cq_rd_take = |cq_rd_take_elig; // any thread is eligible to take, so issue take +reg [2:0] cq_rd_take_thread_id_last; +wire [4:0] cq_rd_take_thread_id_is_1 = { + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd0}; +wire [4:0] cq_rd_take_thread_id_is_2 = { + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd1, + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd0 && !cq_rd_take_elig[1]}; +wire [4:0] cq_rd_take_thread_id_is_3 = { + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd2, + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd1 && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2]}; +wire [4:0] cq_rd_take_thread_id_is_4 = { + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd3, + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd2 && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3]}; +assign cq_rd_take_thread_id[0] = |{cq_rd_take_thread_id_is_1,cq_rd_take_thread_id_is_3}; +assign cq_rd_take_thread_id[1] = |{cq_rd_take_thread_id_is_2,cq_rd_take_thread_id_is_3}; +assign cq_rd_take_thread_id[2] = |{cq_rd_take_thread_id_is_4}; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_take_thread_id_last <= 3'd0; + end else begin + if ( cq_rd_take ) begin + cq_rd_take_thread_id_last <= cq_rd_take_thread_id; + end +//synopsys translate_off + else if ( !cq_rd_take ) begin + end else begin + cq_rd_take_thread_id_last <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +assign wr_bypassing = rd_bypassing0 || rd_bypassing1 || rd_bypassing2 || rd_bypassing3 || rd_bypassing4; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next) || rd_popping) || (rd_pushing || cq_rd_take || cq_rd_credit != 5'd0 || rd_take_dly)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +assign nvdla_core_clk_mgated_skid_enable = nvdla_core_clk_mgated_enable || ( cq_rd0_pvld && cq_rd0_prdy ) || rd_bypassing0 || ( cq_rd1_pvld && cq_rd1_prdy ) || rd_bypassing1 || ( cq_rd2_pvld && cq_rd2_prdy ) || rd_bypassing2 || ( cq_rd3_pvld && cq_rd3_prdy ) || rd_bypassing3 || ( cq_rd4_pvld && cq_rd4_prdy ) || rd_bypassing4 + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit : 9'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 9'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 9'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 9'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [8:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cq_wr_pvld && !(!cq_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} ) + , .curr ( {23'd0, cq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check0 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd0 ), + .credit ( cq_rd_credit[0] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check1 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd1 ), + .credit ( cq_rd_credit[1] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check2 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd2 ), + .credit ( cq_rd_credit[2] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check3 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd3 ), + .credit ( cq_rd_credit[3] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check4 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd4 ), + .credit ( cq_rd_credit[4] ) + ); +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_cq") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_cq +// +// generate free list fifo for use from read side to write side +// diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v.vcp new file mode 100644 index 0000000..5d67bc3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v.vcp @@ -0,0 +1,3272 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_cq.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_NOCIF_DRAM_WRITE_cq ( + nvdla_core_clk + , nvdla_core_rstn + , cq_wr_prdy + , cq_wr_pvld + , cq_wr_thread_id +`ifdef FV_RAND_WR_PAUSE + , cq_wr_pause +`endif + , cq_wr_pd + , cq_rd0_prdy + , cq_rd0_pvld + , cq_rd0_pd + , cq_rd1_prdy + , cq_rd1_pvld + , cq_rd1_pd + , cq_rd2_prdy + , cq_rd2_pvld + , cq_rd2_pd + , cq_rd3_prdy + , cq_rd3_pvld + , cq_rd3_pd + , cq_rd4_prdy + , cq_rd4_pvld + , cq_rd4_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cq_wr_prdy; +input cq_wr_pvld; +input [2:0] cq_wr_thread_id; +`ifdef FV_RAND_WR_PAUSE +input cq_wr_pause; +`endif +input [2:0] cq_wr_pd; +input cq_rd0_prdy; +output cq_rd0_pvld; +output [2:0] cq_rd0_pd; +input cq_rd1_prdy; +output cq_rd1_pvld; +output [2:0] cq_rd1_pd; +input cq_rd2_prdy; +output cq_rd2_pvld; +output [2:0] cq_rd2_pd; +input cq_rd3_prdy; +output cq_rd3_pvld; +output [2:0] cq_rd3_pd; +input cq_rd4_prdy; +output cq_rd4_pvld; +output [2:0] cq_rd4_pd; +input [31:0] pwrbus_ram_pd; +// -rd_take_to_rd_busy internal credit/take/data signals (which would have been ports) +// +//wire [4:0] cq_rd_credit; +wire cq_rd_take; +wire [2:0] cq_rd_pd_p; +wire [2:0] cq_rd_take_thread_id; +// We also declare some per-thread flags that indicate whether to have the write bypass the internal fifo. +// These per-class wr_bypassing* flags are set by the take-side logic. We basically pretend that we never pushed the fifo, +// but make sure we return a credit to the sender. +// +wire wr_bypassing; // any thread bypassed +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_skid; +wire nvdla_core_clk_mgated_skid_enable; +NV_CLK_gate_power nvdla_core_clk_rd_mgate_skid( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_skid_enable), .clk_gated(nvdla_core_clk_mgated_skid) ); +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cq_wr_busy_int; // copy for internal use +assign cq_wr_prdy = !cq_wr_busy_int; +assign wr_reserving = cq_wr_pvld && !cq_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [8:0] cq_wr_count; // write-side count +wire wr_reserving_and_not_bypassing = wr_reserving && !wr_bypassing; +wire [8:0] wr_count_next_wr_popping = wr_reserving_and_not_bypassing ? cq_wr_count : (cq_wr_count - 1'd1); // spyglass disable W164a W484 +wire [8:0] wr_count_next_no_wr_popping = wr_reserving_and_not_bypassing ? (cq_wr_count + 1'd1) : cq_wr_count; // spyglass disable W164a W484 +wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 ); +wire wr_count_next_is_256 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_256; +wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [8:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || cq_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire cq_wr_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check cq_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_wr_busy_int <= 1'b0; + cq_wr_count <= 9'd0; + end else begin + cq_wr_busy_int <= cq_wr_busy_next; + if ( wr_reserving_and_not_bypassing ^ wr_popping ) begin + cq_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving_and_not_bypassing ^ wr_popping) ) begin + end else begin + cq_wr_count <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving && !wr_bypassing; // data pushed same cycle as cq_wr_pvld +wire [2:0] wr_pushing_thread_id = cq_wr_thread_id; // thread being written +// +// RAM +// +wire wr_adr_popping = wr_pushing; // pop free list when wr_pushing=1 +wire [7:0] cq_wr_adr; // current write address +reg [7:0] cq_rd_adr; +wire [7:0] cq_rd_adr_p = cq_rd_adr; // read address to use for ram +wire rd_enable; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rws_256x3 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( cq_wr_adr ) + , .we ( wr_pushing ) + , .di ( cq_wr_pd ) + , .ra ( cq_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( cq_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +// +// SYNCHRONOUS BOUNDARY +// +wire rd_pushing = wr_pushing; // let it be seen immediately +wire [2:0] rd_pushing_thread_id = wr_pushing_thread_id; +wire [7:0] rd_pushing_adr = cq_wr_adr; +// +// MULTITHREADED FREE LIST FIFO +// +// free list of cq_wr_adr's from read side to write side +// these are passed in a ff fifo when the fifo is popped +// +// there's an extra mux of the internal flops that is +// used to determine which address to use when +// rd_pushing is 1 if the fifo is async. +// +wire [7:0] rd_popping_adr; // cq_rd_adr to free up +wire [7:0] free_adr_index; +reg [255-1:0] free_adr_mask_next; +reg [255-1:0] free_adr_mask; +assign cq_wr_adr = free_adr_index; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + free_adr_mask <= {255{1'b1}}; + end else begin + if ( rd_popping || wr_adr_popping ) begin + free_adr_mask <= free_adr_mask_next; + end +//synopsys translate_off + else if ( !(rd_popping || wr_adr_popping) ) begin + end else begin + free_adr_mask <= {255{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(*) begin + free_adr_mask_next = free_adr_mask; + if ( rd_popping && rd_popping_adr == 8'd0 ) begin + free_adr_mask_next[0] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd0 ) begin + free_adr_mask_next[0] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd1 ) begin + free_adr_mask_next[1] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd1 ) begin + free_adr_mask_next[1] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd2 ) begin + free_adr_mask_next[2] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd2 ) begin + free_adr_mask_next[2] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd3 ) begin + free_adr_mask_next[3] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd3 ) begin + free_adr_mask_next[3] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd4 ) begin + free_adr_mask_next[4] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd4 ) begin + free_adr_mask_next[4] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd5 ) begin + free_adr_mask_next[5] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd5 ) begin + free_adr_mask_next[5] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd6 ) begin + free_adr_mask_next[6] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd6 ) begin + free_adr_mask_next[6] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd7 ) begin + free_adr_mask_next[7] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd7 ) begin + free_adr_mask_next[7] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd8 ) begin + free_adr_mask_next[8] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd8 ) begin + free_adr_mask_next[8] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd9 ) begin + free_adr_mask_next[9] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd9 ) begin + free_adr_mask_next[9] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd10 ) begin + free_adr_mask_next[10] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd10 ) begin + free_adr_mask_next[10] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd11 ) begin + free_adr_mask_next[11] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd11 ) begin + free_adr_mask_next[11] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd12 ) begin + free_adr_mask_next[12] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd12 ) begin + free_adr_mask_next[12] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd13 ) begin + free_adr_mask_next[13] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd13 ) begin + free_adr_mask_next[13] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd14 ) begin + free_adr_mask_next[14] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd14 ) begin + free_adr_mask_next[14] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd15 ) begin + free_adr_mask_next[15] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd15 ) begin + free_adr_mask_next[15] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd16 ) begin + free_adr_mask_next[16] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd16 ) begin + free_adr_mask_next[16] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd17 ) begin + free_adr_mask_next[17] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd17 ) begin + free_adr_mask_next[17] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd18 ) begin + free_adr_mask_next[18] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd18 ) begin + free_adr_mask_next[18] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd19 ) begin + free_adr_mask_next[19] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd19 ) begin + free_adr_mask_next[19] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd20 ) begin + free_adr_mask_next[20] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd20 ) begin + free_adr_mask_next[20] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd21 ) begin + free_adr_mask_next[21] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd21 ) begin + free_adr_mask_next[21] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd22 ) begin + free_adr_mask_next[22] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd22 ) begin + free_adr_mask_next[22] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd23 ) begin + free_adr_mask_next[23] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd23 ) begin + free_adr_mask_next[23] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd24 ) begin + free_adr_mask_next[24] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd24 ) begin + free_adr_mask_next[24] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd25 ) begin + free_adr_mask_next[25] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd25 ) begin + free_adr_mask_next[25] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd26 ) begin + free_adr_mask_next[26] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd26 ) begin + free_adr_mask_next[26] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd27 ) begin + free_adr_mask_next[27] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd27 ) begin + free_adr_mask_next[27] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd28 ) begin + free_adr_mask_next[28] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd28 ) begin + free_adr_mask_next[28] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd29 ) begin + free_adr_mask_next[29] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd29 ) begin + free_adr_mask_next[29] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd30 ) begin + free_adr_mask_next[30] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd30 ) begin + free_adr_mask_next[30] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd31 ) begin + free_adr_mask_next[31] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd31 ) begin + free_adr_mask_next[31] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd32 ) begin + free_adr_mask_next[32] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd32 ) begin + free_adr_mask_next[32] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd33 ) begin + free_adr_mask_next[33] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd33 ) begin + free_adr_mask_next[33] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd34 ) begin + free_adr_mask_next[34] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd34 ) begin + free_adr_mask_next[34] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd35 ) begin + free_adr_mask_next[35] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd35 ) begin + free_adr_mask_next[35] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd36 ) begin + free_adr_mask_next[36] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd36 ) begin + free_adr_mask_next[36] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd37 ) begin + free_adr_mask_next[37] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd37 ) begin + free_adr_mask_next[37] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd38 ) begin + free_adr_mask_next[38] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd38 ) begin + free_adr_mask_next[38] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd39 ) begin + free_adr_mask_next[39] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd39 ) begin + free_adr_mask_next[39] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd40 ) begin + free_adr_mask_next[40] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd40 ) begin + free_adr_mask_next[40] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd41 ) begin + free_adr_mask_next[41] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd41 ) begin + free_adr_mask_next[41] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd42 ) begin + free_adr_mask_next[42] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd42 ) begin + free_adr_mask_next[42] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd43 ) begin + free_adr_mask_next[43] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd43 ) begin + free_adr_mask_next[43] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd44 ) begin + free_adr_mask_next[44] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd44 ) begin + free_adr_mask_next[44] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd45 ) begin + free_adr_mask_next[45] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd45 ) begin + free_adr_mask_next[45] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd46 ) begin + free_adr_mask_next[46] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd46 ) begin + free_adr_mask_next[46] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd47 ) begin + free_adr_mask_next[47] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd47 ) begin + free_adr_mask_next[47] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd48 ) begin + free_adr_mask_next[48] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd48 ) begin + free_adr_mask_next[48] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd49 ) begin + free_adr_mask_next[49] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd49 ) begin + free_adr_mask_next[49] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd50 ) begin + free_adr_mask_next[50] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd50 ) begin + free_adr_mask_next[50] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd51 ) begin + free_adr_mask_next[51] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd51 ) begin + free_adr_mask_next[51] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd52 ) begin + free_adr_mask_next[52] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd52 ) begin + free_adr_mask_next[52] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd53 ) begin + free_adr_mask_next[53] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd53 ) begin + free_adr_mask_next[53] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd54 ) begin + free_adr_mask_next[54] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd54 ) begin + free_adr_mask_next[54] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd55 ) begin + free_adr_mask_next[55] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd55 ) begin + free_adr_mask_next[55] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd56 ) begin + free_adr_mask_next[56] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd56 ) begin + free_adr_mask_next[56] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd57 ) begin + free_adr_mask_next[57] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd57 ) begin + free_adr_mask_next[57] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd58 ) begin + free_adr_mask_next[58] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd58 ) begin + free_adr_mask_next[58] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd59 ) begin + free_adr_mask_next[59] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd59 ) begin + free_adr_mask_next[59] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd60 ) begin + free_adr_mask_next[60] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd60 ) begin + free_adr_mask_next[60] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd61 ) begin + free_adr_mask_next[61] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd61 ) begin + free_adr_mask_next[61] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd62 ) begin + free_adr_mask_next[62] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd62 ) begin + free_adr_mask_next[62] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd63 ) begin + free_adr_mask_next[63] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd63 ) begin + free_adr_mask_next[63] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd64 ) begin + free_adr_mask_next[64] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd64 ) begin + free_adr_mask_next[64] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd65 ) begin + free_adr_mask_next[65] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd65 ) begin + free_adr_mask_next[65] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd66 ) begin + free_adr_mask_next[66] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd66 ) begin + free_adr_mask_next[66] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd67 ) begin + free_adr_mask_next[67] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd67 ) begin + free_adr_mask_next[67] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd68 ) begin + free_adr_mask_next[68] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd68 ) begin + free_adr_mask_next[68] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd69 ) begin + free_adr_mask_next[69] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd69 ) begin + free_adr_mask_next[69] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd70 ) begin + free_adr_mask_next[70] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd70 ) begin + free_adr_mask_next[70] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd71 ) begin + free_adr_mask_next[71] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd71 ) begin + free_adr_mask_next[71] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd72 ) begin + free_adr_mask_next[72] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd72 ) begin + free_adr_mask_next[72] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd73 ) begin + free_adr_mask_next[73] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd73 ) begin + free_adr_mask_next[73] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd74 ) begin + free_adr_mask_next[74] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd74 ) begin + free_adr_mask_next[74] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd75 ) begin + free_adr_mask_next[75] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd75 ) begin + free_adr_mask_next[75] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd76 ) begin + free_adr_mask_next[76] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd76 ) begin + free_adr_mask_next[76] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd77 ) begin + free_adr_mask_next[77] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd77 ) begin + free_adr_mask_next[77] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd78 ) begin + free_adr_mask_next[78] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd78 ) begin + free_adr_mask_next[78] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd79 ) begin + free_adr_mask_next[79] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd79 ) begin + free_adr_mask_next[79] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd80 ) begin + free_adr_mask_next[80] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd80 ) begin + free_adr_mask_next[80] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd81 ) begin + free_adr_mask_next[81] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd81 ) begin + free_adr_mask_next[81] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd82 ) begin + free_adr_mask_next[82] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd82 ) begin + free_adr_mask_next[82] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd83 ) begin + free_adr_mask_next[83] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd83 ) begin + free_adr_mask_next[83] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd84 ) begin + free_adr_mask_next[84] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd84 ) begin + free_adr_mask_next[84] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd85 ) begin + free_adr_mask_next[85] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd85 ) begin + free_adr_mask_next[85] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd86 ) begin + free_adr_mask_next[86] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd86 ) begin + free_adr_mask_next[86] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd87 ) begin + free_adr_mask_next[87] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd87 ) begin + free_adr_mask_next[87] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd88 ) begin + free_adr_mask_next[88] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd88 ) begin + free_adr_mask_next[88] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd89 ) begin + free_adr_mask_next[89] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd89 ) begin + free_adr_mask_next[89] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd90 ) begin + free_adr_mask_next[90] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd90 ) begin + free_adr_mask_next[90] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd91 ) begin + free_adr_mask_next[91] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd91 ) begin + free_adr_mask_next[91] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd92 ) begin + free_adr_mask_next[92] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd92 ) begin + free_adr_mask_next[92] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd93 ) begin + free_adr_mask_next[93] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd93 ) begin + free_adr_mask_next[93] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd94 ) begin + free_adr_mask_next[94] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd94 ) begin + free_adr_mask_next[94] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd95 ) begin + free_adr_mask_next[95] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd95 ) begin + free_adr_mask_next[95] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd96 ) begin + free_adr_mask_next[96] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd96 ) begin + free_adr_mask_next[96] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd97 ) begin + free_adr_mask_next[97] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd97 ) begin + free_adr_mask_next[97] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd98 ) begin + free_adr_mask_next[98] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd98 ) begin + free_adr_mask_next[98] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd99 ) begin + free_adr_mask_next[99] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd99 ) begin + free_adr_mask_next[99] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd100 ) begin + free_adr_mask_next[100] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd100 ) begin + free_adr_mask_next[100] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd101 ) begin + free_adr_mask_next[101] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd101 ) begin + free_adr_mask_next[101] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd102 ) begin + free_adr_mask_next[102] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd102 ) begin + free_adr_mask_next[102] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd103 ) begin + free_adr_mask_next[103] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd103 ) begin + free_adr_mask_next[103] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd104 ) begin + free_adr_mask_next[104] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd104 ) begin + free_adr_mask_next[104] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd105 ) begin + free_adr_mask_next[105] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd105 ) begin + free_adr_mask_next[105] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd106 ) begin + free_adr_mask_next[106] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd106 ) begin + free_adr_mask_next[106] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd107 ) begin + free_adr_mask_next[107] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd107 ) begin + free_adr_mask_next[107] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd108 ) begin + free_adr_mask_next[108] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd108 ) begin + free_adr_mask_next[108] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd109 ) begin + free_adr_mask_next[109] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd109 ) begin + free_adr_mask_next[109] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd110 ) begin + free_adr_mask_next[110] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd110 ) begin + free_adr_mask_next[110] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd111 ) begin + free_adr_mask_next[111] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd111 ) begin + free_adr_mask_next[111] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd112 ) begin + free_adr_mask_next[112] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd112 ) begin + free_adr_mask_next[112] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd113 ) begin + free_adr_mask_next[113] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd113 ) begin + free_adr_mask_next[113] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd114 ) begin + free_adr_mask_next[114] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd114 ) begin + free_adr_mask_next[114] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd115 ) begin + free_adr_mask_next[115] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd115 ) begin + free_adr_mask_next[115] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd116 ) begin + free_adr_mask_next[116] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd116 ) begin + free_adr_mask_next[116] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd117 ) begin + free_adr_mask_next[117] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd117 ) begin + free_adr_mask_next[117] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd118 ) begin + free_adr_mask_next[118] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd118 ) begin + free_adr_mask_next[118] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd119 ) begin + free_adr_mask_next[119] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd119 ) begin + free_adr_mask_next[119] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd120 ) begin + free_adr_mask_next[120] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd120 ) begin + free_adr_mask_next[120] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd121 ) begin + free_adr_mask_next[121] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd121 ) begin + free_adr_mask_next[121] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd122 ) begin + free_adr_mask_next[122] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd122 ) begin + free_adr_mask_next[122] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd123 ) begin + free_adr_mask_next[123] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd123 ) begin + free_adr_mask_next[123] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd124 ) begin + free_adr_mask_next[124] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd124 ) begin + free_adr_mask_next[124] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd125 ) begin + free_adr_mask_next[125] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd125 ) begin + free_adr_mask_next[125] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd126 ) begin + free_adr_mask_next[126] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd126 ) begin + free_adr_mask_next[126] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd127 ) begin + free_adr_mask_next[127] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd127 ) begin + free_adr_mask_next[127] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd128 ) begin + free_adr_mask_next[128] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd128 ) begin + free_adr_mask_next[128] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd129 ) begin + free_adr_mask_next[129] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd129 ) begin + free_adr_mask_next[129] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd130 ) begin + free_adr_mask_next[130] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd130 ) begin + free_adr_mask_next[130] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd131 ) begin + free_adr_mask_next[131] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd131 ) begin + free_adr_mask_next[131] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd132 ) begin + free_adr_mask_next[132] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd132 ) begin + free_adr_mask_next[132] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd133 ) begin + free_adr_mask_next[133] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd133 ) begin + free_adr_mask_next[133] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd134 ) begin + free_adr_mask_next[134] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd134 ) begin + free_adr_mask_next[134] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd135 ) begin + free_adr_mask_next[135] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd135 ) begin + free_adr_mask_next[135] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd136 ) begin + free_adr_mask_next[136] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd136 ) begin + free_adr_mask_next[136] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd137 ) begin + free_adr_mask_next[137] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd137 ) begin + free_adr_mask_next[137] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd138 ) begin + free_adr_mask_next[138] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd138 ) begin + free_adr_mask_next[138] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd139 ) begin + free_adr_mask_next[139] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd139 ) begin + free_adr_mask_next[139] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd140 ) begin + free_adr_mask_next[140] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd140 ) begin + free_adr_mask_next[140] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd141 ) begin + free_adr_mask_next[141] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd141 ) begin + free_adr_mask_next[141] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd142 ) begin + free_adr_mask_next[142] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd142 ) begin + free_adr_mask_next[142] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd143 ) begin + free_adr_mask_next[143] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd143 ) begin + free_adr_mask_next[143] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd144 ) begin + free_adr_mask_next[144] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd144 ) begin + free_adr_mask_next[144] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd145 ) begin + free_adr_mask_next[145] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd145 ) begin + free_adr_mask_next[145] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd146 ) begin + free_adr_mask_next[146] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd146 ) begin + free_adr_mask_next[146] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd147 ) begin + free_adr_mask_next[147] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd147 ) begin + free_adr_mask_next[147] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd148 ) begin + free_adr_mask_next[148] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd148 ) begin + free_adr_mask_next[148] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd149 ) begin + free_adr_mask_next[149] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd149 ) begin + free_adr_mask_next[149] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd150 ) begin + free_adr_mask_next[150] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd150 ) begin + free_adr_mask_next[150] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd151 ) begin + free_adr_mask_next[151] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd151 ) begin + free_adr_mask_next[151] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd152 ) begin + free_adr_mask_next[152] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd152 ) begin + free_adr_mask_next[152] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd153 ) begin + free_adr_mask_next[153] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd153 ) begin + free_adr_mask_next[153] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd154 ) begin + free_adr_mask_next[154] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd154 ) begin + free_adr_mask_next[154] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd155 ) begin + free_adr_mask_next[155] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd155 ) begin + free_adr_mask_next[155] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd156 ) begin + free_adr_mask_next[156] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd156 ) begin + free_adr_mask_next[156] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd157 ) begin + free_adr_mask_next[157] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd157 ) begin + free_adr_mask_next[157] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd158 ) begin + free_adr_mask_next[158] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd158 ) begin + free_adr_mask_next[158] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd159 ) begin + free_adr_mask_next[159] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd159 ) begin + free_adr_mask_next[159] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd160 ) begin + free_adr_mask_next[160] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd160 ) begin + free_adr_mask_next[160] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd161 ) begin + free_adr_mask_next[161] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd161 ) begin + free_adr_mask_next[161] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd162 ) begin + free_adr_mask_next[162] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd162 ) begin + free_adr_mask_next[162] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd163 ) begin + free_adr_mask_next[163] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd163 ) begin + free_adr_mask_next[163] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd164 ) begin + free_adr_mask_next[164] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd164 ) begin + free_adr_mask_next[164] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd165 ) begin + free_adr_mask_next[165] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd165 ) begin + free_adr_mask_next[165] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd166 ) begin + free_adr_mask_next[166] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd166 ) begin + free_adr_mask_next[166] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd167 ) begin + free_adr_mask_next[167] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd167 ) begin + free_adr_mask_next[167] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd168 ) begin + free_adr_mask_next[168] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd168 ) begin + free_adr_mask_next[168] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd169 ) begin + free_adr_mask_next[169] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd169 ) begin + free_adr_mask_next[169] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd170 ) begin + free_adr_mask_next[170] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd170 ) begin + free_adr_mask_next[170] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd171 ) begin + free_adr_mask_next[171] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd171 ) begin + free_adr_mask_next[171] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd172 ) begin + free_adr_mask_next[172] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd172 ) begin + free_adr_mask_next[172] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd173 ) begin + free_adr_mask_next[173] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd173 ) begin + free_adr_mask_next[173] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd174 ) begin + free_adr_mask_next[174] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd174 ) begin + free_adr_mask_next[174] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd175 ) begin + free_adr_mask_next[175] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd175 ) begin + free_adr_mask_next[175] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd176 ) begin + free_adr_mask_next[176] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd176 ) begin + free_adr_mask_next[176] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd177 ) begin + free_adr_mask_next[177] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd177 ) begin + free_adr_mask_next[177] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd178 ) begin + free_adr_mask_next[178] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd178 ) begin + free_adr_mask_next[178] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd179 ) begin + free_adr_mask_next[179] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd179 ) begin + free_adr_mask_next[179] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd180 ) begin + free_adr_mask_next[180] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd180 ) begin + free_adr_mask_next[180] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd181 ) begin + free_adr_mask_next[181] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd181 ) begin + free_adr_mask_next[181] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd182 ) begin + free_adr_mask_next[182] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd182 ) begin + free_adr_mask_next[182] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd183 ) begin + free_adr_mask_next[183] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd183 ) begin + free_adr_mask_next[183] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd184 ) begin + free_adr_mask_next[184] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd184 ) begin + free_adr_mask_next[184] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd185 ) begin + free_adr_mask_next[185] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd185 ) begin + free_adr_mask_next[185] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd186 ) begin + free_adr_mask_next[186] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd186 ) begin + free_adr_mask_next[186] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd187 ) begin + free_adr_mask_next[187] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd187 ) begin + free_adr_mask_next[187] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd188 ) begin + free_adr_mask_next[188] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd188 ) begin + free_adr_mask_next[188] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd189 ) begin + free_adr_mask_next[189] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd189 ) begin + free_adr_mask_next[189] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd190 ) begin + free_adr_mask_next[190] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd190 ) begin + free_adr_mask_next[190] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd191 ) begin + free_adr_mask_next[191] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd191 ) begin + free_adr_mask_next[191] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd192 ) begin + free_adr_mask_next[192] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd192 ) begin + free_adr_mask_next[192] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd193 ) begin + free_adr_mask_next[193] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd193 ) begin + free_adr_mask_next[193] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd194 ) begin + free_adr_mask_next[194] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd194 ) begin + free_adr_mask_next[194] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd195 ) begin + free_adr_mask_next[195] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd195 ) begin + free_adr_mask_next[195] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd196 ) begin + free_adr_mask_next[196] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd196 ) begin + free_adr_mask_next[196] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd197 ) begin + free_adr_mask_next[197] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd197 ) begin + free_adr_mask_next[197] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd198 ) begin + free_adr_mask_next[198] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd198 ) begin + free_adr_mask_next[198] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd199 ) begin + free_adr_mask_next[199] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd199 ) begin + free_adr_mask_next[199] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd200 ) begin + free_adr_mask_next[200] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd200 ) begin + free_adr_mask_next[200] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd201 ) begin + free_adr_mask_next[201] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd201 ) begin + free_adr_mask_next[201] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd202 ) begin + free_adr_mask_next[202] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd202 ) begin + free_adr_mask_next[202] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd203 ) begin + free_adr_mask_next[203] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd203 ) begin + free_adr_mask_next[203] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd204 ) begin + free_adr_mask_next[204] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd204 ) begin + free_adr_mask_next[204] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd205 ) begin + free_adr_mask_next[205] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd205 ) begin + free_adr_mask_next[205] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd206 ) begin + free_adr_mask_next[206] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd206 ) begin + free_adr_mask_next[206] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd207 ) begin + free_adr_mask_next[207] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd207 ) begin + free_adr_mask_next[207] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd208 ) begin + free_adr_mask_next[208] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd208 ) begin + free_adr_mask_next[208] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd209 ) begin + free_adr_mask_next[209] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd209 ) begin + free_adr_mask_next[209] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd210 ) begin + free_adr_mask_next[210] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd210 ) begin + free_adr_mask_next[210] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd211 ) begin + free_adr_mask_next[211] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd211 ) begin + free_adr_mask_next[211] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd212 ) begin + free_adr_mask_next[212] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd212 ) begin + free_adr_mask_next[212] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd213 ) begin + free_adr_mask_next[213] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd213 ) begin + free_adr_mask_next[213] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd214 ) begin + free_adr_mask_next[214] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd214 ) begin + free_adr_mask_next[214] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd215 ) begin + free_adr_mask_next[215] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd215 ) begin + free_adr_mask_next[215] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd216 ) begin + free_adr_mask_next[216] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd216 ) begin + free_adr_mask_next[216] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd217 ) begin + free_adr_mask_next[217] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd217 ) begin + free_adr_mask_next[217] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd218 ) begin + free_adr_mask_next[218] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd218 ) begin + free_adr_mask_next[218] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd219 ) begin + free_adr_mask_next[219] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd219 ) begin + free_adr_mask_next[219] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd220 ) begin + free_adr_mask_next[220] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd220 ) begin + free_adr_mask_next[220] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd221 ) begin + free_adr_mask_next[221] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd221 ) begin + free_adr_mask_next[221] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd222 ) begin + free_adr_mask_next[222] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd222 ) begin + free_adr_mask_next[222] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd223 ) begin + free_adr_mask_next[223] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd223 ) begin + free_adr_mask_next[223] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd224 ) begin + free_adr_mask_next[224] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd224 ) begin + free_adr_mask_next[224] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd225 ) begin + free_adr_mask_next[225] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd225 ) begin + free_adr_mask_next[225] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd226 ) begin + free_adr_mask_next[226] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd226 ) begin + free_adr_mask_next[226] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd227 ) begin + free_adr_mask_next[227] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd227 ) begin + free_adr_mask_next[227] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd228 ) begin + free_adr_mask_next[228] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd228 ) begin + free_adr_mask_next[228] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd229 ) begin + free_adr_mask_next[229] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd229 ) begin + free_adr_mask_next[229] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd230 ) begin + free_adr_mask_next[230] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd230 ) begin + free_adr_mask_next[230] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd231 ) begin + free_adr_mask_next[231] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd231 ) begin + free_adr_mask_next[231] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd232 ) begin + free_adr_mask_next[232] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd232 ) begin + free_adr_mask_next[232] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd233 ) begin + free_adr_mask_next[233] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd233 ) begin + free_adr_mask_next[233] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd234 ) begin + free_adr_mask_next[234] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd234 ) begin + free_adr_mask_next[234] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd235 ) begin + free_adr_mask_next[235] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd235 ) begin + free_adr_mask_next[235] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd236 ) begin + free_adr_mask_next[236] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd236 ) begin + free_adr_mask_next[236] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd237 ) begin + free_adr_mask_next[237] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd237 ) begin + free_adr_mask_next[237] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd238 ) begin + free_adr_mask_next[238] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd238 ) begin + free_adr_mask_next[238] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd239 ) begin + free_adr_mask_next[239] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd239 ) begin + free_adr_mask_next[239] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd240 ) begin + free_adr_mask_next[240] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd240 ) begin + free_adr_mask_next[240] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd241 ) begin + free_adr_mask_next[241] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd241 ) begin + free_adr_mask_next[241] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd242 ) begin + free_adr_mask_next[242] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd242 ) begin + free_adr_mask_next[242] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd243 ) begin + free_adr_mask_next[243] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd243 ) begin + free_adr_mask_next[243] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd244 ) begin + free_adr_mask_next[244] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd244 ) begin + free_adr_mask_next[244] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd245 ) begin + free_adr_mask_next[245] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd245 ) begin + free_adr_mask_next[245] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd246 ) begin + free_adr_mask_next[246] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd246 ) begin + free_adr_mask_next[246] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd247 ) begin + free_adr_mask_next[247] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd247 ) begin + free_adr_mask_next[247] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd248 ) begin + free_adr_mask_next[248] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd248 ) begin + free_adr_mask_next[248] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd249 ) begin + free_adr_mask_next[249] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd249 ) begin + free_adr_mask_next[249] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd250 ) begin + free_adr_mask_next[250] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd250 ) begin + free_adr_mask_next[250] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd251 ) begin + free_adr_mask_next[251] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd251 ) begin + free_adr_mask_next[251] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd252 ) begin + free_adr_mask_next[252] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd252 ) begin + free_adr_mask_next[252] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd253 ) begin + free_adr_mask_next[253] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd253 ) begin + free_adr_mask_next[253] = 1'b0; + end + if ( rd_popping && rd_popping_adr == 8'd254 ) begin + free_adr_mask_next[254] = 1'b1; + end else if ( wr_adr_popping && free_adr_index == 8'd254 ) begin + free_adr_mask_next[254] = 1'b0; + end +end +wire flag_l0_0 = free_adr_mask[1] | free_adr_mask[0]; +wire flag_l0_1 = free_adr_mask[3] | free_adr_mask[2]; +wire flag_l0_2 = free_adr_mask[5] | free_adr_mask[4]; +wire flag_l0_3 = free_adr_mask[7] | free_adr_mask[6]; +wire flag_l0_4 = free_adr_mask[9] | free_adr_mask[8]; +wire flag_l0_5 = free_adr_mask[11] | free_adr_mask[10]; +wire flag_l0_6 = free_adr_mask[13] | free_adr_mask[12]; +wire flag_l0_7 = free_adr_mask[15] | free_adr_mask[14]; +wire flag_l0_8 = free_adr_mask[17] | free_adr_mask[16]; +wire flag_l0_9 = free_adr_mask[19] | free_adr_mask[18]; +wire flag_l0_10 = free_adr_mask[21] | free_adr_mask[20]; +wire flag_l0_11 = free_adr_mask[23] | free_adr_mask[22]; +wire flag_l0_12 = free_adr_mask[25] | free_adr_mask[24]; +wire flag_l0_13 = free_adr_mask[27] | free_adr_mask[26]; +wire flag_l0_14 = free_adr_mask[29] | free_adr_mask[28]; +wire flag_l0_15 = free_adr_mask[31] | free_adr_mask[30]; +wire flag_l0_16 = free_adr_mask[33] | free_adr_mask[32]; +wire flag_l0_17 = free_adr_mask[35] | free_adr_mask[34]; +wire flag_l0_18 = free_adr_mask[37] | free_adr_mask[36]; +wire flag_l0_19 = free_adr_mask[39] | free_adr_mask[38]; +wire flag_l0_20 = free_adr_mask[41] | free_adr_mask[40]; +wire flag_l0_21 = free_adr_mask[43] | free_adr_mask[42]; +wire flag_l0_22 = free_adr_mask[45] | free_adr_mask[44]; +wire flag_l0_23 = free_adr_mask[47] | free_adr_mask[46]; +wire flag_l0_24 = free_adr_mask[49] | free_adr_mask[48]; +wire flag_l0_25 = free_adr_mask[51] | free_adr_mask[50]; +wire flag_l0_26 = free_adr_mask[53] | free_adr_mask[52]; +wire flag_l0_27 = free_adr_mask[55] | free_adr_mask[54]; +wire flag_l0_28 = free_adr_mask[57] | free_adr_mask[56]; +wire flag_l0_29 = free_adr_mask[59] | free_adr_mask[58]; +wire flag_l0_30 = free_adr_mask[61] | free_adr_mask[60]; +wire flag_l0_31 = free_adr_mask[63] | free_adr_mask[62]; +wire flag_l0_32 = free_adr_mask[65] | free_adr_mask[64]; +wire flag_l0_33 = free_adr_mask[67] | free_adr_mask[66]; +wire flag_l0_34 = free_adr_mask[69] | free_adr_mask[68]; +wire flag_l0_35 = free_adr_mask[71] | free_adr_mask[70]; +wire flag_l0_36 = free_adr_mask[73] | free_adr_mask[72]; +wire flag_l0_37 = free_adr_mask[75] | free_adr_mask[74]; +wire flag_l0_38 = free_adr_mask[77] | free_adr_mask[76]; +wire flag_l0_39 = free_adr_mask[79] | free_adr_mask[78]; +wire flag_l0_40 = free_adr_mask[81] | free_adr_mask[80]; +wire flag_l0_41 = free_adr_mask[83] | free_adr_mask[82]; +wire flag_l0_42 = free_adr_mask[85] | free_adr_mask[84]; +wire flag_l0_43 = free_adr_mask[87] | free_adr_mask[86]; +wire flag_l0_44 = free_adr_mask[89] | free_adr_mask[88]; +wire flag_l0_45 = free_adr_mask[91] | free_adr_mask[90]; +wire flag_l0_46 = free_adr_mask[93] | free_adr_mask[92]; +wire flag_l0_47 = free_adr_mask[95] | free_adr_mask[94]; +wire flag_l0_48 = free_adr_mask[97] | free_adr_mask[96]; +wire flag_l0_49 = free_adr_mask[99] | free_adr_mask[98]; +wire flag_l0_50 = free_adr_mask[101] | free_adr_mask[100]; +wire flag_l0_51 = free_adr_mask[103] | free_adr_mask[102]; +wire flag_l0_52 = free_adr_mask[105] | free_adr_mask[104]; +wire flag_l0_53 = free_adr_mask[107] | free_adr_mask[106]; +wire flag_l0_54 = free_adr_mask[109] | free_adr_mask[108]; +wire flag_l0_55 = free_adr_mask[111] | free_adr_mask[110]; +wire flag_l0_56 = free_adr_mask[113] | free_adr_mask[112]; +wire flag_l0_57 = free_adr_mask[115] | free_adr_mask[114]; +wire flag_l0_58 = free_adr_mask[117] | free_adr_mask[116]; +wire flag_l0_59 = free_adr_mask[119] | free_adr_mask[118]; +wire flag_l0_60 = free_adr_mask[121] | free_adr_mask[120]; +wire flag_l0_61 = free_adr_mask[123] | free_adr_mask[122]; +wire flag_l0_62 = free_adr_mask[125] | free_adr_mask[124]; +wire flag_l0_63 = free_adr_mask[127] | free_adr_mask[126]; +wire flag_l0_64 = free_adr_mask[129] | free_adr_mask[128]; +wire flag_l0_65 = free_adr_mask[131] | free_adr_mask[130]; +wire flag_l0_66 = free_adr_mask[133] | free_adr_mask[132]; +wire flag_l0_67 = free_adr_mask[135] | free_adr_mask[134]; +wire flag_l0_68 = free_adr_mask[137] | free_adr_mask[136]; +wire flag_l0_69 = free_adr_mask[139] | free_adr_mask[138]; +wire flag_l0_70 = free_adr_mask[141] | free_adr_mask[140]; +wire flag_l0_71 = free_adr_mask[143] | free_adr_mask[142]; +wire flag_l0_72 = free_adr_mask[145] | free_adr_mask[144]; +wire flag_l0_73 = free_adr_mask[147] | free_adr_mask[146]; +wire flag_l0_74 = free_adr_mask[149] | free_adr_mask[148]; +wire flag_l0_75 = free_adr_mask[151] | free_adr_mask[150]; +wire flag_l0_76 = free_adr_mask[153] | free_adr_mask[152]; +wire flag_l0_77 = free_adr_mask[155] | free_adr_mask[154]; +wire flag_l0_78 = free_adr_mask[157] | free_adr_mask[156]; +wire flag_l0_79 = free_adr_mask[159] | free_adr_mask[158]; +wire flag_l0_80 = free_adr_mask[161] | free_adr_mask[160]; +wire flag_l0_81 = free_adr_mask[163] | free_adr_mask[162]; +wire flag_l0_82 = free_adr_mask[165] | free_adr_mask[164]; +wire flag_l0_83 = free_adr_mask[167] | free_adr_mask[166]; +wire flag_l0_84 = free_adr_mask[169] | free_adr_mask[168]; +wire flag_l0_85 = free_adr_mask[171] | free_adr_mask[170]; +wire flag_l0_86 = free_adr_mask[173] | free_adr_mask[172]; +wire flag_l0_87 = free_adr_mask[175] | free_adr_mask[174]; +wire flag_l0_88 = free_adr_mask[177] | free_adr_mask[176]; +wire flag_l0_89 = free_adr_mask[179] | free_adr_mask[178]; +wire flag_l0_90 = free_adr_mask[181] | free_adr_mask[180]; +wire flag_l0_91 = free_adr_mask[183] | free_adr_mask[182]; +wire flag_l0_92 = free_adr_mask[185] | free_adr_mask[184]; +wire flag_l0_93 = free_adr_mask[187] | free_adr_mask[186]; +wire flag_l0_94 = free_adr_mask[189] | free_adr_mask[188]; +wire flag_l0_95 = free_adr_mask[191] | free_adr_mask[190]; +wire flag_l0_96 = free_adr_mask[193] | free_adr_mask[192]; +wire flag_l0_97 = free_adr_mask[195] | free_adr_mask[194]; +wire flag_l0_98 = free_adr_mask[197] | free_adr_mask[196]; +wire flag_l0_99 = free_adr_mask[199] | free_adr_mask[198]; +wire flag_l0_100 = free_adr_mask[201] | free_adr_mask[200]; +wire flag_l0_101 = free_adr_mask[203] | free_adr_mask[202]; +wire flag_l0_102 = free_adr_mask[205] | free_adr_mask[204]; +wire flag_l0_103 = free_adr_mask[207] | free_adr_mask[206]; +wire flag_l0_104 = free_adr_mask[209] | free_adr_mask[208]; +wire flag_l0_105 = free_adr_mask[211] | free_adr_mask[210]; +wire flag_l0_106 = free_adr_mask[213] | free_adr_mask[212]; +wire flag_l0_107 = free_adr_mask[215] | free_adr_mask[214]; +wire flag_l0_108 = free_adr_mask[217] | free_adr_mask[216]; +wire flag_l0_109 = free_adr_mask[219] | free_adr_mask[218]; +wire flag_l0_110 = free_adr_mask[221] | free_adr_mask[220]; +wire flag_l0_111 = free_adr_mask[223] | free_adr_mask[222]; +wire flag_l0_112 = free_adr_mask[225] | free_adr_mask[224]; +wire flag_l0_113 = free_adr_mask[227] | free_adr_mask[226]; +wire flag_l0_114 = free_adr_mask[229] | free_adr_mask[228]; +wire flag_l0_115 = free_adr_mask[231] | free_adr_mask[230]; +wire flag_l0_116 = free_adr_mask[233] | free_adr_mask[232]; +wire flag_l0_117 = free_adr_mask[235] | free_adr_mask[234]; +wire flag_l0_118 = free_adr_mask[237] | free_adr_mask[236]; +wire flag_l0_119 = free_adr_mask[239] | free_adr_mask[238]; +wire flag_l0_120 = free_adr_mask[241] | free_adr_mask[240]; +wire flag_l0_121 = free_adr_mask[243] | free_adr_mask[242]; +wire flag_l0_122 = free_adr_mask[245] | free_adr_mask[244]; +wire flag_l0_123 = free_adr_mask[247] | free_adr_mask[246]; +wire flag_l0_124 = free_adr_mask[249] | free_adr_mask[248]; +wire flag_l0_125 = free_adr_mask[251] | free_adr_mask[250]; +wire flag_l0_126 = free_adr_mask[253] | free_adr_mask[252]; +wire flag_l1_0 = flag_l0_1 | flag_l0_0; +wire flag_l1_1 = flag_l0_3 | flag_l0_2; +wire flag_l1_2 = flag_l0_5 | flag_l0_4; +wire flag_l1_3 = flag_l0_7 | flag_l0_6; +wire flag_l1_4 = flag_l0_9 | flag_l0_8; +wire flag_l1_5 = flag_l0_11 | flag_l0_10; +wire flag_l1_6 = flag_l0_13 | flag_l0_12; +wire flag_l1_7 = flag_l0_15 | flag_l0_14; +wire flag_l1_8 = flag_l0_17 | flag_l0_16; +wire flag_l1_9 = flag_l0_19 | flag_l0_18; +wire flag_l1_10 = flag_l0_21 | flag_l0_20; +wire flag_l1_11 = flag_l0_23 | flag_l0_22; +wire flag_l1_12 = flag_l0_25 | flag_l0_24; +wire flag_l1_13 = flag_l0_27 | flag_l0_26; +wire flag_l1_14 = flag_l0_29 | flag_l0_28; +wire flag_l1_15 = flag_l0_31 | flag_l0_30; +wire flag_l1_16 = flag_l0_33 | flag_l0_32; +wire flag_l1_17 = flag_l0_35 | flag_l0_34; +wire flag_l1_18 = flag_l0_37 | flag_l0_36; +wire flag_l1_19 = flag_l0_39 | flag_l0_38; +wire flag_l1_20 = flag_l0_41 | flag_l0_40; +wire flag_l1_21 = flag_l0_43 | flag_l0_42; +wire flag_l1_22 = flag_l0_45 | flag_l0_44; +wire flag_l1_23 = flag_l0_47 | flag_l0_46; +wire flag_l1_24 = flag_l0_49 | flag_l0_48; +wire flag_l1_25 = flag_l0_51 | flag_l0_50; +wire flag_l1_26 = flag_l0_53 | flag_l0_52; +wire flag_l1_27 = flag_l0_55 | flag_l0_54; +wire flag_l1_28 = flag_l0_57 | flag_l0_56; +wire flag_l1_29 = flag_l0_59 | flag_l0_58; +wire flag_l1_30 = flag_l0_61 | flag_l0_60; +wire flag_l1_31 = flag_l0_63 | flag_l0_62; +wire flag_l1_32 = flag_l0_65 | flag_l0_64; +wire flag_l1_33 = flag_l0_67 | flag_l0_66; +wire flag_l1_34 = flag_l0_69 | flag_l0_68; +wire flag_l1_35 = flag_l0_71 | flag_l0_70; +wire flag_l1_36 = flag_l0_73 | flag_l0_72; +wire flag_l1_37 = flag_l0_75 | flag_l0_74; +wire flag_l1_38 = flag_l0_77 | flag_l0_76; +wire flag_l1_39 = flag_l0_79 | flag_l0_78; +wire flag_l1_40 = flag_l0_81 | flag_l0_80; +wire flag_l1_41 = flag_l0_83 | flag_l0_82; +wire flag_l1_42 = flag_l0_85 | flag_l0_84; +wire flag_l1_43 = flag_l0_87 | flag_l0_86; +wire flag_l1_44 = flag_l0_89 | flag_l0_88; +wire flag_l1_45 = flag_l0_91 | flag_l0_90; +wire flag_l1_46 = flag_l0_93 | flag_l0_92; +wire flag_l1_47 = flag_l0_95 | flag_l0_94; +wire flag_l1_48 = flag_l0_97 | flag_l0_96; +wire flag_l1_49 = flag_l0_99 | flag_l0_98; +wire flag_l1_50 = flag_l0_101 | flag_l0_100; +wire flag_l1_51 = flag_l0_103 | flag_l0_102; +wire flag_l1_52 = flag_l0_105 | flag_l0_104; +wire flag_l1_53 = flag_l0_107 | flag_l0_106; +wire flag_l1_54 = flag_l0_109 | flag_l0_108; +wire flag_l1_55 = flag_l0_111 | flag_l0_110; +wire flag_l1_56 = flag_l0_113 | flag_l0_112; +wire flag_l1_57 = flag_l0_115 | flag_l0_114; +wire flag_l1_58 = flag_l0_117 | flag_l0_116; +wire flag_l1_59 = flag_l0_119 | flag_l0_118; +wire flag_l1_60 = flag_l0_121 | flag_l0_120; +wire flag_l1_61 = flag_l0_123 | flag_l0_122; +wire flag_l1_62 = flag_l0_125 | flag_l0_124; +wire flag_l2_0 = flag_l1_1 | flag_l1_0; +wire flag_l2_1 = flag_l1_3 | flag_l1_2; +wire flag_l2_2 = flag_l1_5 | flag_l1_4; +wire flag_l2_3 = flag_l1_7 | flag_l1_6; +wire flag_l2_4 = flag_l1_9 | flag_l1_8; +wire flag_l2_5 = flag_l1_11 | flag_l1_10; +wire flag_l2_6 = flag_l1_13 | flag_l1_12; +wire flag_l2_7 = flag_l1_15 | flag_l1_14; +wire flag_l2_8 = flag_l1_17 | flag_l1_16; +wire flag_l2_9 = flag_l1_19 | flag_l1_18; +wire flag_l2_10 = flag_l1_21 | flag_l1_20; +wire flag_l2_11 = flag_l1_23 | flag_l1_22; +wire flag_l2_12 = flag_l1_25 | flag_l1_24; +wire flag_l2_13 = flag_l1_27 | flag_l1_26; +wire flag_l2_14 = flag_l1_29 | flag_l1_28; +wire flag_l2_15 = flag_l1_31 | flag_l1_30; +wire flag_l2_16 = flag_l1_33 | flag_l1_32; +wire flag_l2_17 = flag_l1_35 | flag_l1_34; +wire flag_l2_18 = flag_l1_37 | flag_l1_36; +wire flag_l2_19 = flag_l1_39 | flag_l1_38; +wire flag_l2_20 = flag_l1_41 | flag_l1_40; +wire flag_l2_21 = flag_l1_43 | flag_l1_42; +wire flag_l2_22 = flag_l1_45 | flag_l1_44; +wire flag_l2_23 = flag_l1_47 | flag_l1_46; +wire flag_l2_24 = flag_l1_49 | flag_l1_48; +wire flag_l2_25 = flag_l1_51 | flag_l1_50; +wire flag_l2_26 = flag_l1_53 | flag_l1_52; +wire flag_l2_27 = flag_l1_55 | flag_l1_54; +wire flag_l2_28 = flag_l1_57 | flag_l1_56; +wire flag_l2_29 = flag_l1_59 | flag_l1_58; +wire flag_l2_30 = flag_l1_61 | flag_l1_60; +wire flag_l3_0 = flag_l2_1 | flag_l2_0; +wire flag_l3_1 = flag_l2_3 | flag_l2_2; +wire flag_l3_2 = flag_l2_5 | flag_l2_4; +wire flag_l3_3 = flag_l2_7 | flag_l2_6; +wire flag_l3_4 = flag_l2_9 | flag_l2_8; +wire flag_l3_5 = flag_l2_11 | flag_l2_10; +wire flag_l3_6 = flag_l2_13 | flag_l2_12; +wire flag_l3_7 = flag_l2_15 | flag_l2_14; +wire flag_l3_8 = flag_l2_17 | flag_l2_16; +wire flag_l3_9 = flag_l2_19 | flag_l2_18; +wire flag_l3_10 = flag_l2_21 | flag_l2_20; +wire flag_l3_11 = flag_l2_23 | flag_l2_22; +wire flag_l3_12 = flag_l2_25 | flag_l2_24; +wire flag_l3_13 = flag_l2_27 | flag_l2_26; +wire flag_l3_14 = flag_l2_29 | flag_l2_28; +wire flag_l4_0 = flag_l3_1 | flag_l3_0; +wire flag_l4_1 = flag_l3_3 | flag_l3_2; +wire flag_l4_2 = flag_l3_5 | flag_l3_4; +wire flag_l4_3 = flag_l3_7 | flag_l3_6; +wire flag_l4_4 = flag_l3_9 | flag_l3_8; +wire flag_l4_5 = flag_l3_11 | flag_l3_10; +wire flag_l4_6 = flag_l3_13 | flag_l3_12; +wire flag_l5_0 = flag_l4_1 | flag_l4_0; +wire flag_l5_1 = flag_l4_3 | flag_l4_2; +wire flag_l5_2 = flag_l4_5 | flag_l4_4; +wire flag_l6_0 = flag_l5_1 | flag_l5_0; +wire index_l0_0 = !free_adr_mask[0]; +wire index_l0_1 = !free_adr_mask[2]; +wire index_l0_2 = !free_adr_mask[4]; +wire index_l0_3 = !free_adr_mask[6]; +wire index_l0_4 = !free_adr_mask[8]; +wire index_l0_5 = !free_adr_mask[10]; +wire index_l0_6 = !free_adr_mask[12]; +wire index_l0_7 = !free_adr_mask[14]; +wire index_l0_8 = !free_adr_mask[16]; +wire index_l0_9 = !free_adr_mask[18]; +wire index_l0_10 = !free_adr_mask[20]; +wire index_l0_11 = !free_adr_mask[22]; +wire index_l0_12 = !free_adr_mask[24]; +wire index_l0_13 = !free_adr_mask[26]; +wire index_l0_14 = !free_adr_mask[28]; +wire index_l0_15 = !free_adr_mask[30]; +wire index_l0_16 = !free_adr_mask[32]; +wire index_l0_17 = !free_adr_mask[34]; +wire index_l0_18 = !free_adr_mask[36]; +wire index_l0_19 = !free_adr_mask[38]; +wire index_l0_20 = !free_adr_mask[40]; +wire index_l0_21 = !free_adr_mask[42]; +wire index_l0_22 = !free_adr_mask[44]; +wire index_l0_23 = !free_adr_mask[46]; +wire index_l0_24 = !free_adr_mask[48]; +wire index_l0_25 = !free_adr_mask[50]; +wire index_l0_26 = !free_adr_mask[52]; +wire index_l0_27 = !free_adr_mask[54]; +wire index_l0_28 = !free_adr_mask[56]; +wire index_l0_29 = !free_adr_mask[58]; +wire index_l0_30 = !free_adr_mask[60]; +wire index_l0_31 = !free_adr_mask[62]; +wire index_l0_32 = !free_adr_mask[64]; +wire index_l0_33 = !free_adr_mask[66]; +wire index_l0_34 = !free_adr_mask[68]; +wire index_l0_35 = !free_adr_mask[70]; +wire index_l0_36 = !free_adr_mask[72]; +wire index_l0_37 = !free_adr_mask[74]; +wire index_l0_38 = !free_adr_mask[76]; +wire index_l0_39 = !free_adr_mask[78]; +wire index_l0_40 = !free_adr_mask[80]; +wire index_l0_41 = !free_adr_mask[82]; +wire index_l0_42 = !free_adr_mask[84]; +wire index_l0_43 = !free_adr_mask[86]; +wire index_l0_44 = !free_adr_mask[88]; +wire index_l0_45 = !free_adr_mask[90]; +wire index_l0_46 = !free_adr_mask[92]; +wire index_l0_47 = !free_adr_mask[94]; +wire index_l0_48 = !free_adr_mask[96]; +wire index_l0_49 = !free_adr_mask[98]; +wire index_l0_50 = !free_adr_mask[100]; +wire index_l0_51 = !free_adr_mask[102]; +wire index_l0_52 = !free_adr_mask[104]; +wire index_l0_53 = !free_adr_mask[106]; +wire index_l0_54 = !free_adr_mask[108]; +wire index_l0_55 = !free_adr_mask[110]; +wire index_l0_56 = !free_adr_mask[112]; +wire index_l0_57 = !free_adr_mask[114]; +wire index_l0_58 = !free_adr_mask[116]; +wire index_l0_59 = !free_adr_mask[118]; +wire index_l0_60 = !free_adr_mask[120]; +wire index_l0_61 = !free_adr_mask[122]; +wire index_l0_62 = !free_adr_mask[124]; +wire index_l0_63 = !free_adr_mask[126]; +wire index_l0_64 = !free_adr_mask[128]; +wire index_l0_65 = !free_adr_mask[130]; +wire index_l0_66 = !free_adr_mask[132]; +wire index_l0_67 = !free_adr_mask[134]; +wire index_l0_68 = !free_adr_mask[136]; +wire index_l0_69 = !free_adr_mask[138]; +wire index_l0_70 = !free_adr_mask[140]; +wire index_l0_71 = !free_adr_mask[142]; +wire index_l0_72 = !free_adr_mask[144]; +wire index_l0_73 = !free_adr_mask[146]; +wire index_l0_74 = !free_adr_mask[148]; +wire index_l0_75 = !free_adr_mask[150]; +wire index_l0_76 = !free_adr_mask[152]; +wire index_l0_77 = !free_adr_mask[154]; +wire index_l0_78 = !free_adr_mask[156]; +wire index_l0_79 = !free_adr_mask[158]; +wire index_l0_80 = !free_adr_mask[160]; +wire index_l0_81 = !free_adr_mask[162]; +wire index_l0_82 = !free_adr_mask[164]; +wire index_l0_83 = !free_adr_mask[166]; +wire index_l0_84 = !free_adr_mask[168]; +wire index_l0_85 = !free_adr_mask[170]; +wire index_l0_86 = !free_adr_mask[172]; +wire index_l0_87 = !free_adr_mask[174]; +wire index_l0_88 = !free_adr_mask[176]; +wire index_l0_89 = !free_adr_mask[178]; +wire index_l0_90 = !free_adr_mask[180]; +wire index_l0_91 = !free_adr_mask[182]; +wire index_l0_92 = !free_adr_mask[184]; +wire index_l0_93 = !free_adr_mask[186]; +wire index_l0_94 = !free_adr_mask[188]; +wire index_l0_95 = !free_adr_mask[190]; +wire index_l0_96 = !free_adr_mask[192]; +wire index_l0_97 = !free_adr_mask[194]; +wire index_l0_98 = !free_adr_mask[196]; +wire index_l0_99 = !free_adr_mask[198]; +wire index_l0_100 = !free_adr_mask[200]; +wire index_l0_101 = !free_adr_mask[202]; +wire index_l0_102 = !free_adr_mask[204]; +wire index_l0_103 = !free_adr_mask[206]; +wire index_l0_104 = !free_adr_mask[208]; +wire index_l0_105 = !free_adr_mask[210]; +wire index_l0_106 = !free_adr_mask[212]; +wire index_l0_107 = !free_adr_mask[214]; +wire index_l0_108 = !free_adr_mask[216]; +wire index_l0_109 = !free_adr_mask[218]; +wire index_l0_110 = !free_adr_mask[220]; +wire index_l0_111 = !free_adr_mask[222]; +wire index_l0_112 = !free_adr_mask[224]; +wire index_l0_113 = !free_adr_mask[226]; +wire index_l0_114 = !free_adr_mask[228]; +wire index_l0_115 = !free_adr_mask[230]; +wire index_l0_116 = !free_adr_mask[232]; +wire index_l0_117 = !free_adr_mask[234]; +wire index_l0_118 = !free_adr_mask[236]; +wire index_l0_119 = !free_adr_mask[238]; +wire index_l0_120 = !free_adr_mask[240]; +wire index_l0_121 = !free_adr_mask[242]; +wire index_l0_122 = !free_adr_mask[244]; +wire index_l0_123 = !free_adr_mask[246]; +wire index_l0_124 = !free_adr_mask[248]; +wire index_l0_125 = !free_adr_mask[250]; +wire index_l0_126 = !free_adr_mask[252]; +wire index_l0_127 = !free_adr_mask[254]; +wire [1:0] index_l1_0 = {!flag_l0_0,(flag_l0_0?index_l0_0:index_l0_1)}; +wire [1:0] index_l1_1 = {!flag_l0_2,(flag_l0_2?index_l0_2:index_l0_3)}; +wire [1:0] index_l1_2 = {!flag_l0_4,(flag_l0_4?index_l0_4:index_l0_5)}; +wire [1:0] index_l1_3 = {!flag_l0_6,(flag_l0_6?index_l0_6:index_l0_7)}; +wire [1:0] index_l1_4 = {!flag_l0_8,(flag_l0_8?index_l0_8:index_l0_9)}; +wire [1:0] index_l1_5 = {!flag_l0_10,(flag_l0_10?index_l0_10:index_l0_11)}; +wire [1:0] index_l1_6 = {!flag_l0_12,(flag_l0_12?index_l0_12:index_l0_13)}; +wire [1:0] index_l1_7 = {!flag_l0_14,(flag_l0_14?index_l0_14:index_l0_15)}; +wire [1:0] index_l1_8 = {!flag_l0_16,(flag_l0_16?index_l0_16:index_l0_17)}; +wire [1:0] index_l1_9 = {!flag_l0_18,(flag_l0_18?index_l0_18:index_l0_19)}; +wire [1:0] index_l1_10 = {!flag_l0_20,(flag_l0_20?index_l0_20:index_l0_21)}; +wire [1:0] index_l1_11 = {!flag_l0_22,(flag_l0_22?index_l0_22:index_l0_23)}; +wire [1:0] index_l1_12 = {!flag_l0_24,(flag_l0_24?index_l0_24:index_l0_25)}; +wire [1:0] index_l1_13 = {!flag_l0_26,(flag_l0_26?index_l0_26:index_l0_27)}; +wire [1:0] index_l1_14 = {!flag_l0_28,(flag_l0_28?index_l0_28:index_l0_29)}; +wire [1:0] index_l1_15 = {!flag_l0_30,(flag_l0_30?index_l0_30:index_l0_31)}; +wire [1:0] index_l1_16 = {!flag_l0_32,(flag_l0_32?index_l0_32:index_l0_33)}; +wire [1:0] index_l1_17 = {!flag_l0_34,(flag_l0_34?index_l0_34:index_l0_35)}; +wire [1:0] index_l1_18 = {!flag_l0_36,(flag_l0_36?index_l0_36:index_l0_37)}; +wire [1:0] index_l1_19 = {!flag_l0_38,(flag_l0_38?index_l0_38:index_l0_39)}; +wire [1:0] index_l1_20 = {!flag_l0_40,(flag_l0_40?index_l0_40:index_l0_41)}; +wire [1:0] index_l1_21 = {!flag_l0_42,(flag_l0_42?index_l0_42:index_l0_43)}; +wire [1:0] index_l1_22 = {!flag_l0_44,(flag_l0_44?index_l0_44:index_l0_45)}; +wire [1:0] index_l1_23 = {!flag_l0_46,(flag_l0_46?index_l0_46:index_l0_47)}; +wire [1:0] index_l1_24 = {!flag_l0_48,(flag_l0_48?index_l0_48:index_l0_49)}; +wire [1:0] index_l1_25 = {!flag_l0_50,(flag_l0_50?index_l0_50:index_l0_51)}; +wire [1:0] index_l1_26 = {!flag_l0_52,(flag_l0_52?index_l0_52:index_l0_53)}; +wire [1:0] index_l1_27 = {!flag_l0_54,(flag_l0_54?index_l0_54:index_l0_55)}; +wire [1:0] index_l1_28 = {!flag_l0_56,(flag_l0_56?index_l0_56:index_l0_57)}; +wire [1:0] index_l1_29 = {!flag_l0_58,(flag_l0_58?index_l0_58:index_l0_59)}; +wire [1:0] index_l1_30 = {!flag_l0_60,(flag_l0_60?index_l0_60:index_l0_61)}; +wire [1:0] index_l1_31 = {!flag_l0_62,(flag_l0_62?index_l0_62:index_l0_63)}; +wire [1:0] index_l1_32 = {!flag_l0_64,(flag_l0_64?index_l0_64:index_l0_65)}; +wire [1:0] index_l1_33 = {!flag_l0_66,(flag_l0_66?index_l0_66:index_l0_67)}; +wire [1:0] index_l1_34 = {!flag_l0_68,(flag_l0_68?index_l0_68:index_l0_69)}; +wire [1:0] index_l1_35 = {!flag_l0_70,(flag_l0_70?index_l0_70:index_l0_71)}; +wire [1:0] index_l1_36 = {!flag_l0_72,(flag_l0_72?index_l0_72:index_l0_73)}; +wire [1:0] index_l1_37 = {!flag_l0_74,(flag_l0_74?index_l0_74:index_l0_75)}; +wire [1:0] index_l1_38 = {!flag_l0_76,(flag_l0_76?index_l0_76:index_l0_77)}; +wire [1:0] index_l1_39 = {!flag_l0_78,(flag_l0_78?index_l0_78:index_l0_79)}; +wire [1:0] index_l1_40 = {!flag_l0_80,(flag_l0_80?index_l0_80:index_l0_81)}; +wire [1:0] index_l1_41 = {!flag_l0_82,(flag_l0_82?index_l0_82:index_l0_83)}; +wire [1:0] index_l1_42 = {!flag_l0_84,(flag_l0_84?index_l0_84:index_l0_85)}; +wire [1:0] index_l1_43 = {!flag_l0_86,(flag_l0_86?index_l0_86:index_l0_87)}; +wire [1:0] index_l1_44 = {!flag_l0_88,(flag_l0_88?index_l0_88:index_l0_89)}; +wire [1:0] index_l1_45 = {!flag_l0_90,(flag_l0_90?index_l0_90:index_l0_91)}; +wire [1:0] index_l1_46 = {!flag_l0_92,(flag_l0_92?index_l0_92:index_l0_93)}; +wire [1:0] index_l1_47 = {!flag_l0_94,(flag_l0_94?index_l0_94:index_l0_95)}; +wire [1:0] index_l1_48 = {!flag_l0_96,(flag_l0_96?index_l0_96:index_l0_97)}; +wire [1:0] index_l1_49 = {!flag_l0_98,(flag_l0_98?index_l0_98:index_l0_99)}; +wire [1:0] index_l1_50 = {!flag_l0_100,(flag_l0_100?index_l0_100:index_l0_101)}; +wire [1:0] index_l1_51 = {!flag_l0_102,(flag_l0_102?index_l0_102:index_l0_103)}; +wire [1:0] index_l1_52 = {!flag_l0_104,(flag_l0_104?index_l0_104:index_l0_105)}; +wire [1:0] index_l1_53 = {!flag_l0_106,(flag_l0_106?index_l0_106:index_l0_107)}; +wire [1:0] index_l1_54 = {!flag_l0_108,(flag_l0_108?index_l0_108:index_l0_109)}; +wire [1:0] index_l1_55 = {!flag_l0_110,(flag_l0_110?index_l0_110:index_l0_111)}; +wire [1:0] index_l1_56 = {!flag_l0_112,(flag_l0_112?index_l0_112:index_l0_113)}; +wire [1:0] index_l1_57 = {!flag_l0_114,(flag_l0_114?index_l0_114:index_l0_115)}; +wire [1:0] index_l1_58 = {!flag_l0_116,(flag_l0_116?index_l0_116:index_l0_117)}; +wire [1:0] index_l1_59 = {!flag_l0_118,(flag_l0_118?index_l0_118:index_l0_119)}; +wire [1:0] index_l1_60 = {!flag_l0_120,(flag_l0_120?index_l0_120:index_l0_121)}; +wire [1:0] index_l1_61 = {!flag_l0_122,(flag_l0_122?index_l0_122:index_l0_123)}; +wire [1:0] index_l1_62 = {!flag_l0_124,(flag_l0_124?index_l0_124:index_l0_125)}; +wire [1:0] index_l1_63 = {!flag_l0_126,(flag_l0_126?index_l0_126:index_l0_127)}; +wire [2:0] index_l2_0 = {!flag_l1_0,(flag_l1_0?index_l1_0:index_l1_1)}; +wire [2:0] index_l2_1 = {!flag_l1_2,(flag_l1_2?index_l1_2:index_l1_3)}; +wire [2:0] index_l2_2 = {!flag_l1_4,(flag_l1_4?index_l1_4:index_l1_5)}; +wire [2:0] index_l2_3 = {!flag_l1_6,(flag_l1_6?index_l1_6:index_l1_7)}; +wire [2:0] index_l2_4 = {!flag_l1_8,(flag_l1_8?index_l1_8:index_l1_9)}; +wire [2:0] index_l2_5 = {!flag_l1_10,(flag_l1_10?index_l1_10:index_l1_11)}; +wire [2:0] index_l2_6 = {!flag_l1_12,(flag_l1_12?index_l1_12:index_l1_13)}; +wire [2:0] index_l2_7 = {!flag_l1_14,(flag_l1_14?index_l1_14:index_l1_15)}; +wire [2:0] index_l2_8 = {!flag_l1_16,(flag_l1_16?index_l1_16:index_l1_17)}; +wire [2:0] index_l2_9 = {!flag_l1_18,(flag_l1_18?index_l1_18:index_l1_19)}; +wire [2:0] index_l2_10 = {!flag_l1_20,(flag_l1_20?index_l1_20:index_l1_21)}; +wire [2:0] index_l2_11 = {!flag_l1_22,(flag_l1_22?index_l1_22:index_l1_23)}; +wire [2:0] index_l2_12 = {!flag_l1_24,(flag_l1_24?index_l1_24:index_l1_25)}; +wire [2:0] index_l2_13 = {!flag_l1_26,(flag_l1_26?index_l1_26:index_l1_27)}; +wire [2:0] index_l2_14 = {!flag_l1_28,(flag_l1_28?index_l1_28:index_l1_29)}; +wire [2:0] index_l2_15 = {!flag_l1_30,(flag_l1_30?index_l1_30:index_l1_31)}; +wire [2:0] index_l2_16 = {!flag_l1_32,(flag_l1_32?index_l1_32:index_l1_33)}; +wire [2:0] index_l2_17 = {!flag_l1_34,(flag_l1_34?index_l1_34:index_l1_35)}; +wire [2:0] index_l2_18 = {!flag_l1_36,(flag_l1_36?index_l1_36:index_l1_37)}; +wire [2:0] index_l2_19 = {!flag_l1_38,(flag_l1_38?index_l1_38:index_l1_39)}; +wire [2:0] index_l2_20 = {!flag_l1_40,(flag_l1_40?index_l1_40:index_l1_41)}; +wire [2:0] index_l2_21 = {!flag_l1_42,(flag_l1_42?index_l1_42:index_l1_43)}; +wire [2:0] index_l2_22 = {!flag_l1_44,(flag_l1_44?index_l1_44:index_l1_45)}; +wire [2:0] index_l2_23 = {!flag_l1_46,(flag_l1_46?index_l1_46:index_l1_47)}; +wire [2:0] index_l2_24 = {!flag_l1_48,(flag_l1_48?index_l1_48:index_l1_49)}; +wire [2:0] index_l2_25 = {!flag_l1_50,(flag_l1_50?index_l1_50:index_l1_51)}; +wire [2:0] index_l2_26 = {!flag_l1_52,(flag_l1_52?index_l1_52:index_l1_53)}; +wire [2:0] index_l2_27 = {!flag_l1_54,(flag_l1_54?index_l1_54:index_l1_55)}; +wire [2:0] index_l2_28 = {!flag_l1_56,(flag_l1_56?index_l1_56:index_l1_57)}; +wire [2:0] index_l2_29 = {!flag_l1_58,(flag_l1_58?index_l1_58:index_l1_59)}; +wire [2:0] index_l2_30 = {!flag_l1_60,(flag_l1_60?index_l1_60:index_l1_61)}; +wire [2:0] index_l2_31 = {!flag_l1_62,(flag_l1_62?index_l1_62:index_l1_63)}; +wire [3:0] index_l3_0 = {!flag_l2_0,(flag_l2_0?index_l2_0:index_l2_1)}; +wire [3:0] index_l3_1 = {!flag_l2_2,(flag_l2_2?index_l2_2:index_l2_3)}; +wire [3:0] index_l3_2 = {!flag_l2_4,(flag_l2_4?index_l2_4:index_l2_5)}; +wire [3:0] index_l3_3 = {!flag_l2_6,(flag_l2_6?index_l2_6:index_l2_7)}; +wire [3:0] index_l3_4 = {!flag_l2_8,(flag_l2_8?index_l2_8:index_l2_9)}; +wire [3:0] index_l3_5 = {!flag_l2_10,(flag_l2_10?index_l2_10:index_l2_11)}; +wire [3:0] index_l3_6 = {!flag_l2_12,(flag_l2_12?index_l2_12:index_l2_13)}; +wire [3:0] index_l3_7 = {!flag_l2_14,(flag_l2_14?index_l2_14:index_l2_15)}; +wire [3:0] index_l3_8 = {!flag_l2_16,(flag_l2_16?index_l2_16:index_l2_17)}; +wire [3:0] index_l3_9 = {!flag_l2_18,(flag_l2_18?index_l2_18:index_l2_19)}; +wire [3:0] index_l3_10 = {!flag_l2_20,(flag_l2_20?index_l2_20:index_l2_21)}; +wire [3:0] index_l3_11 = {!flag_l2_22,(flag_l2_22?index_l2_22:index_l2_23)}; +wire [3:0] index_l3_12 = {!flag_l2_24,(flag_l2_24?index_l2_24:index_l2_25)}; +wire [3:0] index_l3_13 = {!flag_l2_26,(flag_l2_26?index_l2_26:index_l2_27)}; +wire [3:0] index_l3_14 = {!flag_l2_28,(flag_l2_28?index_l2_28:index_l2_29)}; +wire [3:0] index_l3_15 = {!flag_l2_30,(flag_l2_30?index_l2_30:index_l2_31)}; +wire [4:0] index_l4_0 = {!flag_l3_0,(flag_l3_0?index_l3_0:index_l3_1)}; +wire [4:0] index_l4_1 = {!flag_l3_2,(flag_l3_2?index_l3_2:index_l3_3)}; +wire [4:0] index_l4_2 = {!flag_l3_4,(flag_l3_4?index_l3_4:index_l3_5)}; +wire [4:0] index_l4_3 = {!flag_l3_6,(flag_l3_6?index_l3_6:index_l3_7)}; +wire [4:0] index_l4_4 = {!flag_l3_8,(flag_l3_8?index_l3_8:index_l3_9)}; +wire [4:0] index_l4_5 = {!flag_l3_10,(flag_l3_10?index_l3_10:index_l3_11)}; +wire [4:0] index_l4_6 = {!flag_l3_12,(flag_l3_12?index_l3_12:index_l3_13)}; +wire [4:0] index_l4_7 = {!flag_l3_14,(flag_l3_14?index_l3_14:index_l3_15)}; +wire [5:0] index_l5_0 = {!flag_l4_0,(flag_l4_0?index_l4_0:index_l4_1)}; +wire [5:0] index_l5_1 = {!flag_l4_2,(flag_l4_2?index_l4_2:index_l4_3)}; +wire [5:0] index_l5_2 = {!flag_l4_4,(flag_l4_4?index_l4_4:index_l4_5)}; +wire [5:0] index_l5_3 = {!flag_l4_6,(flag_l4_6?index_l4_6:index_l4_7)}; +wire [6:0] index_l6_0 = {!flag_l5_0,(flag_l5_0?index_l5_0:index_l5_1)}; +wire [6:0] index_l6_1 = {!flag_l5_2,(flag_l5_2?index_l5_2:index_l5_3)}; +wire [7:0] index_l7_0 = {!flag_l6_0,(flag_l6_0?index_l6_0:index_l6_1)}; +assign free_adr_index[7:0] = index_l7_0[7:0]; +assign wr_popping = rd_popping; +// +// READ SIDE +// +// +// credits for taker are simply rd_pushing* +// +reg [4:0] cq_rd_credit; // registered out take credits +reg rd_pushing_q; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_credit <= 5'd0; + rd_pushing_q <= 1'b0; + end else begin + if ( rd_pushing || rd_pushing_q ) begin + cq_rd_credit[0] <= rd_pushing && rd_pushing_thread_id == 3'd0; + cq_rd_credit[1] <= rd_pushing && rd_pushing_thread_id == 3'd1; + cq_rd_credit[2] <= rd_pushing && rd_pushing_thread_id == 3'd2; + cq_rd_credit[3] <= rd_pushing && rd_pushing_thread_id == 3'd3; + cq_rd_credit[4] <= rd_pushing && rd_pushing_thread_id == 3'd4; + rd_pushing_q <= rd_pushing; + end + end +end +wire rd_pushing0 = rd_pushing && rd_pushing_thread_id == 3'd0; +wire rd_pushing1 = rd_pushing && rd_pushing_thread_id == 3'd1; +wire rd_pushing2 = rd_pushing && rd_pushing_thread_id == 3'd2; +wire rd_pushing3 = rd_pushing && rd_pushing_thread_id == 3'd3; +wire rd_pushing4 = rd_pushing && rd_pushing_thread_id == 3'd4; +wire rd_take0 = cq_rd_take && cq_rd_take_thread_id == 3'd0; +wire rd_take1 = cq_rd_take && cq_rd_take_thread_id == 3'd1; +wire rd_take2 = cq_rd_take && cq_rd_take_thread_id == 3'd2; +wire rd_take3 = cq_rd_take && cq_rd_take_thread_id == 3'd3; +wire rd_take4 = cq_rd_take && cq_rd_take_thread_id == 3'd4; +reg [7:0] head0; // thread 0's head pointer +reg [7:0] tail0; // thread 0's tail pointer +reg [7:0] head1; // thread 1's head pointer +reg [7:0] tail1; // thread 1's tail pointer +reg [7:0] head2; // thread 2's head pointer +reg [7:0] tail2; // thread 2's tail pointer +reg [7:0] head3; // thread 3's head pointer +reg [7:0] tail3; // thread 3's tail pointer +reg [7:0] head4; // thread 4's head pointer +reg [7:0] tail4; // thread 4's tail pointer +reg [4:0] rd_take_n_dly; +reg rd_take_dly_cg; +wire update_rd_take_n_dly = cq_rd_take || rd_take_dly_cg; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly_cg <= 1'b0; + rd_take_n_dly <= {5{1'b0}}; + end else begin + rd_take_dly_cg <= cq_rd_take; + if ( update_rd_take_n_dly ) begin + rd_take_n_dly <= {rd_take4,rd_take3,rd_take2,rd_take1,rd_take0}; + end +//synopsys translate_off + else if ( !update_rd_take_n_dly) begin + end else begin + rd_take_n_dly <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] adr_ram_wr_adr; +wire [7:0] adr_ram_wr_data; +reg adr_ram_wr_enable; +reg [7:0] adr_ram_rd_adr; +wire [7:0] adr_ram_rd_data; +reg adr_ram_rd_enable; +reg [8:0] cq_rd_count0; +wire [8:0] rd_count0_next; +reg [8:0] cq_rd_count1; +wire [8:0] rd_count1_next; +reg [8:0] cq_rd_count2; +wire [8:0] rd_count2_next; +reg [8:0] cq_rd_count3; +wire [8:0] rd_count3_next; +reg [8:0] cq_rd_count4; +wire [8:0] rd_count4_next; +assign rd_count0_next = + rd_pushing0 ? ( rd_take0 ? cq_rd_count0 : cq_rd_count0 + 1'd1 ) : + ( rd_take0 ? cq_rd_count0 - 1'd1 : cq_rd_count0 ); +assign rd_count1_next = + rd_pushing1 ? ( rd_take1 ? cq_rd_count1 : cq_rd_count1 + 1'd1 ) : + ( rd_take1 ? cq_rd_count1 - 1'd1 : cq_rd_count1 ); +assign rd_count2_next = + rd_pushing2 ? ( rd_take2 ? cq_rd_count2 : cq_rd_count2 + 1'd1 ) : + ( rd_take2 ? cq_rd_count2 - 1'd1 : cq_rd_count2 ); +assign rd_count3_next = + rd_pushing3 ? ( rd_take3 ? cq_rd_count3 : cq_rd_count3 + 1'd1 ) : + ( rd_take3 ? cq_rd_count3 - 1'd1 : cq_rd_count3 ); +assign rd_count4_next = + rd_pushing4 ? ( rd_take4 ? cq_rd_count4 : cq_rd_count4 + 1'd1 ) : + ( rd_take4 ? cq_rd_count4 - 1'd1 : cq_rd_count4 ); +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_count0 <= 9'd0; + cq_rd_count1 <= 9'd0; + cq_rd_count2 <= 9'd0; + cq_rd_count3 <= 9'd0; + cq_rd_count4 <= 9'd0; + end else begin + if ( rd_pushing0 ^ rd_take0 ) begin + cq_rd_count0 <= rd_count0_next; + end +//synopsys translate_off + else if ( !(rd_pushing0 ^ rd_take0) ) begin + end else begin + cq_rd_count0 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing1 ^ rd_take1 ) begin + cq_rd_count1 <= rd_count1_next; + end +//synopsys translate_off + else if ( !(rd_pushing1 ^ rd_take1) ) begin + end else begin + cq_rd_count1 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing2 ^ rd_take2 ) begin + cq_rd_count2 <= rd_count2_next; + end +//synopsys translate_off + else if ( !(rd_pushing2 ^ rd_take2) ) begin + end else begin + cq_rd_count2 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing3 ^ rd_take3 ) begin + cq_rd_count3 <= rd_count3_next; + end +//synopsys translate_off + else if ( !(rd_pushing3 ^ rd_take3) ) begin + end else begin + cq_rd_count3 <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing4 ^ rd_take4 ) begin + cq_rd_count4 <= rd_count4_next; + end +//synopsys translate_off + else if ( !(rd_pushing4 ^ rd_take4) ) begin + end else begin + cq_rd_count4 <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [4:0] update_head; +wire [4:0] update_head_next; +assign update_head_next[0] = (rd_take0 && cq_rd_count0 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[1] = (rd_take1 && cq_rd_count1 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[2] = (rd_take2 && cq_rd_count2 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[3] = (rd_take3 && cq_rd_count3 > 9'd1) ? 1'b1 : 1'b0; +assign update_head_next[4] = (rd_take4 && cq_rd_count4 > 9'd1) ? 1'b1 : 1'b0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + update_head <= 5'd0; + end else begin + if ( rd_pushing || cq_rd_take ) begin + update_head <= update_head_next; + end +//synopsys translate_off + else if ( !(rd_pushing || cq_rd_take) ) begin + end else begin + update_head <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +always @(posedge nvdla_core_clk_mgated) begin + if ( rd_pushing0 ) begin + tail0 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing0 ) begin + end else begin + tail0 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing0 && cq_rd_count0 == 9'd0 ) || + (rd_pushing0 && rd_take0 && cq_rd_count0 == 9'd1) ) begin + head0 <= rd_pushing_adr; + end else if ( update_head[0] ) begin + head0 <= adr_ram_rd_data; + end + if ( rd_pushing1 ) begin + tail1 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing1 ) begin + end else begin + tail1 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing1 && cq_rd_count1 == 9'd0 ) || + (rd_pushing1 && rd_take1 && cq_rd_count1 == 9'd1) ) begin + head1 <= rd_pushing_adr; + end else if ( update_head[1] ) begin + head1 <= adr_ram_rd_data; + end + if ( rd_pushing2 ) begin + tail2 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing2 ) begin + end else begin + tail2 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing2 && cq_rd_count2 == 9'd0 ) || + (rd_pushing2 && rd_take2 && cq_rd_count2 == 9'd1) ) begin + head2 <= rd_pushing_adr; + end else if ( update_head[2] ) begin + head2 <= adr_ram_rd_data; + end + if ( rd_pushing3 ) begin + tail3 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing3 ) begin + end else begin + tail3 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing3 && cq_rd_count3 == 9'd0 ) || + (rd_pushing3 && rd_take3 && cq_rd_count3 == 9'd1) ) begin + head3 <= rd_pushing_adr; + end else if ( update_head[3] ) begin + head3 <= adr_ram_rd_data; + end + if ( rd_pushing4 ) begin + tail4 <= rd_pushing_adr; + end +//synopsys translate_off + else if ( !rd_pushing4 ) begin + end else begin + tail4 <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_pushing4 && cq_rd_count4 == 9'd0 ) || + (rd_pushing4 && rd_take4 && cq_rd_count4 == 9'd1) ) begin + head4 <= rd_pushing_adr; + end else if ( update_head[4] ) begin + head4 <= adr_ram_rd_data; + end +end +nv_ram_rwst_256x8 adr_ram ( + .clk ( nvdla_core_clk ) + , .wa ( adr_ram_wr_adr ) + , .we ( adr_ram_wr_enable ) + , .di ( adr_ram_wr_data ) + , .ra ( adr_ram_rd_adr ) + , .re ( adr_ram_rd_enable ) + , .dout ( adr_ram_rd_data ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + ); +assign adr_ram_wr_data = rd_pushing_adr; +always @(*) begin + case( rd_pushing_thread_id ) + 3'd0: adr_ram_wr_adr = tail0; + 3'd1: adr_ram_wr_adr = tail1; + 3'd2: adr_ram_wr_adr = tail2; + 3'd3: adr_ram_wr_adr = tail3; + 3'd4: adr_ram_wr_adr = tail4; +//VCS coverage off + default: adr_ram_wr_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( rd_pushing_thread_id ) + 3'd0: adr_ram_wr_enable = rd_pushing && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 3'd1: adr_ram_wr_enable = rd_pushing && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 3'd2: adr_ram_wr_enable = rd_pushing && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 3'd3: adr_ram_wr_enable = rd_pushing && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 3'd4: adr_ram_wr_enable = rd_pushing && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_wr_enable = !rd_pushing ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 3'd0: adr_ram_rd_enable = cq_rd_take && cq_rd_count0 != 9'd0 ? 1'b1 : 1'b0; + 3'd1: adr_ram_rd_enable = cq_rd_take && cq_rd_count1 != 9'd0 ? 1'b1 : 1'b0; + 3'd2: adr_ram_rd_enable = cq_rd_take && cq_rd_count2 != 9'd0 ? 1'b1 : 1'b0; + 3'd3: adr_ram_rd_enable = cq_rd_take && cq_rd_count3 != 9'd0 ? 1'b1 : 1'b0; + 3'd4: adr_ram_rd_enable = cq_rd_take && cq_rd_count4 != 9'd0 ? 1'b1 : 1'b0; +//VCS coverage off + default: adr_ram_rd_enable = !cq_rd_take ? 1'b0 : `x_or_0; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 3'd0: adr_ram_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 3'd1: adr_ram_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 3'd2: adr_ram_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 3'd3: adr_ram_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 3'd4: adr_ram_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; +//VCS coverage off + default: adr_ram_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +always @(*) begin + case( cq_rd_take_thread_id ) + 3'd0: cq_rd_adr = rd_take_n_dly[0] && update_head[0] ? adr_ram_rd_data : head0; + 3'd1: cq_rd_adr = rd_take_n_dly[1] && update_head[1] ? adr_ram_rd_data : head1; + 3'd2: cq_rd_adr = rd_take_n_dly[2] && update_head[2] ? adr_ram_rd_data : head2; + 3'd3: cq_rd_adr = rd_take_n_dly[3] && update_head[3] ? adr_ram_rd_data : head3; + 3'd4: cq_rd_adr = rd_take_n_dly[4] && update_head[4] ? adr_ram_rd_data : head4; +//VCS coverage off + default: cq_rd_adr = {8{`x_or_0}}; +//VCS coverage on + endcase +end +// +// take data comes out next cycle for non-ff rams. +// +reg rd_take_dly; +assign rd_popping = rd_take_dly; +reg [7:0] rd_adr_dly; +assign rd_popping_adr = rd_adr_dly; +assign rd_enable = cq_rd_take; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_take_dly <= 1'b0; + end else begin + rd_take_dly <= cq_rd_take; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( cq_rd_take ) begin + rd_adr_dly <= cq_rd_adr; + end +//synopsys translate_off + else if ( !(cq_rd_take) ) begin + end else begin + rd_adr_dly <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// +// -rd_take_to_rd_busy conversion (conceptually outside the fifo except for ra2 bypass) +// +wire [4:0] cq_rd_take_elig; // mask of threads that can do takes this cycle +wire rd_pre_bypassing0; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing0; // between cq_rd0_pvld and cq_rd0_prdy when doing full bypass +reg [2:0] rd_skid0_0; // head skid reg +reg [2:0] rd_skid0_1; // head+1 skid reg +reg [2:0] rd_skid0_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid0_0_vld; // head skid reg has valid data +reg rd_skid0_1_vld; // head+1 skid reg has valid data +reg rd_skid0_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd0_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_prdy_d <= 1'b1; + end else begin + cq_rd0_prdy_d <= cq_rd0_prdy; + end +end +assign cq_rd0_pvld = rd_skid0_0_vld || rd_pre_bypassing0; // full bypass for 0-latency +assign cq_rd0_pd = rd_skid0_0_vld ? rd_skid0_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld)) ) begin + rd_skid0_0 <= rd_take_n_dly[0] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld ) begin + rd_skid0_0 <= rd_skid0_1; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_0_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_1_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_1_vld) ) begin + end else begin + rd_skid0_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld)) ) begin + rd_skid0_1 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld ) begin + rd_skid0_1 <= rd_skid0_2; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && (!rd_skid0_1_vld || (cq_rd0_pvld && cq_rd0_prdy && !rd_skid0_2_vld))) && + !(cq_rd0_pvld && cq_rd0_prdy && rd_skid0_2_vld) ) begin + end else begin + rd_skid0_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy)) ) begin + rd_skid0_2 <= rd_bypassing0 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing0 || rd_take_n_dly[0]) && rd_skid0_0_vld && rd_skid0_1_vld && (rd_skid0_2_vld || !(cq_rd0_pvld && cq_rd0_prdy))) ) begin + end else begin + rd_skid0_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid0_0_vld <= 1'b0; + rd_skid0_1_vld <= 1'b0; + rd_skid0_2_vld <= 1'b0; + end else begin + rd_skid0_0_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_1_vld || (rd_bypassing0 && rd_skid0_0_vld) || rd_take_n_dly[0]) : (rd_skid0_0_vld || rd_bypassing0 || rd_take_n_dly[0]); + rd_skid0_1_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))) : (rd_skid0_1_vld || (rd_skid0_0_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage off + rd_skid0_2_vld <= (cq_rd0_pvld && cq_rd0_prdy) ? (rd_skid0_2_vld && (rd_bypassing0 || rd_take_n_dly[0])) : (rd_skid0_2_vld || (rd_skid0_1_vld && (rd_bypassing0 || rd_take_n_dly[0]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd0_credits; // unused credits +reg cq_rd0_credits_ne0; +wire [8:0] cq_rd0_credits_w_take_next = cq_rd0_credits + cq_rd_credit[0] - 1'b1; +wire [8:0] cq_rd0_credits_wo_take_next = cq_rd0_credits + cq_rd_credit[0]; +wire [8:0] cq_rd0_credits_next = rd_take0 ? cq_rd0_credits_w_take_next : cq_rd0_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[0] = (cq_rd0_prdy_d || !rd_skid0_0_vld || !rd_skid0_1_vld || (!rd_skid0_2_vld && !rd_take_n_dly[0])) && (cq_rd_credit[0] || cq_rd0_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing0 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd0) && cq_rd0_credits == 0 && !cq_rd_credit[0] && (!rd_take_n_dly[0] || rd_skid0_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing0 = rd_pre_bypassing0 && (!rd_skid0_2_vld || !rd_skid0_1_vld || !(!cq_rd0_prdy_d && rd_skid0_0_vld && rd_skid0_1_vld)) && !rd_take_n_dly[0]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd0_credits <= 9'd0; + cq_rd0_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[0] | rd_take0 ) begin + cq_rd0_credits <= cq_rd0_credits_next; + cq_rd0_credits_ne0 <= rd_take0 ? (cq_rd0_credits_w_take_next != 0) : (cq_rd0_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[0] | rd_take0) ) begin + end else begin + cq_rd0_credits <= {9{`x_or_0}}; + cq_rd0_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing1; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing1; // between cq_rd1_pvld and cq_rd1_prdy when doing full bypass +reg [2:0] rd_skid1_0; // head skid reg +reg [2:0] rd_skid1_1; // head+1 skid reg +reg [2:0] rd_skid1_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid1_0_vld; // head skid reg has valid data +reg rd_skid1_1_vld; // head+1 skid reg has valid data +reg rd_skid1_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd1_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_prdy_d <= 1'b1; + end else begin + cq_rd1_prdy_d <= cq_rd1_prdy; + end +end +assign cq_rd1_pvld = rd_skid1_0_vld || rd_pre_bypassing1; // full bypass for 0-latency +assign cq_rd1_pd = rd_skid1_0_vld ? rd_skid1_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld)) ) begin + rd_skid1_0 <= rd_take_n_dly[1] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld ) begin + rd_skid1_0 <= rd_skid1_1; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_0_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_1_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_1_vld) ) begin + end else begin + rd_skid1_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld)) ) begin + rd_skid1_1 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld ) begin + rd_skid1_1 <= rd_skid1_2; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && (!rd_skid1_1_vld || (cq_rd1_pvld && cq_rd1_prdy && !rd_skid1_2_vld))) && + !(cq_rd1_pvld && cq_rd1_prdy && rd_skid1_2_vld) ) begin + end else begin + rd_skid1_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy)) ) begin + rd_skid1_2 <= rd_bypassing1 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing1 || rd_take_n_dly[1]) && rd_skid1_0_vld && rd_skid1_1_vld && (rd_skid1_2_vld || !(cq_rd1_pvld && cq_rd1_prdy))) ) begin + end else begin + rd_skid1_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid1_0_vld <= 1'b0; + rd_skid1_1_vld <= 1'b0; + rd_skid1_2_vld <= 1'b0; + end else begin + rd_skid1_0_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_1_vld || (rd_bypassing1 && rd_skid1_0_vld) || rd_take_n_dly[1]) : (rd_skid1_0_vld || rd_bypassing1 || rd_take_n_dly[1]); + rd_skid1_1_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))) : (rd_skid1_1_vld || (rd_skid1_0_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage off + rd_skid1_2_vld <= (cq_rd1_pvld && cq_rd1_prdy) ? (rd_skid1_2_vld && (rd_bypassing1 || rd_take_n_dly[1])) : (rd_skid1_2_vld || (rd_skid1_1_vld && (rd_bypassing1 || rd_take_n_dly[1]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd1_credits; // unused credits +reg cq_rd1_credits_ne0; +wire [8:0] cq_rd1_credits_w_take_next = cq_rd1_credits + cq_rd_credit[1] - 1'b1; +wire [8:0] cq_rd1_credits_wo_take_next = cq_rd1_credits + cq_rd_credit[1]; +wire [8:0] cq_rd1_credits_next = rd_take1 ? cq_rd1_credits_w_take_next : cq_rd1_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[1] = (cq_rd1_prdy_d || !rd_skid1_0_vld || !rd_skid1_1_vld || (!rd_skid1_2_vld && !rd_take_n_dly[1])) && (cq_rd_credit[1] || cq_rd1_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing1 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd1) && cq_rd1_credits == 0 && !cq_rd_credit[1] && (!rd_take_n_dly[1] || rd_skid1_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing1 = rd_pre_bypassing1 && (!rd_skid1_2_vld || !rd_skid1_1_vld || !(!cq_rd1_prdy_d && rd_skid1_0_vld && rd_skid1_1_vld)) && !rd_take_n_dly[1]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd1_credits <= 9'd0; + cq_rd1_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[1] | rd_take1 ) begin + cq_rd1_credits <= cq_rd1_credits_next; + cq_rd1_credits_ne0 <= rd_take1 ? (cq_rd1_credits_w_take_next != 0) : (cq_rd1_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[1] | rd_take1) ) begin + end else begin + cq_rd1_credits <= {9{`x_or_0}}; + cq_rd1_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing2; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing2; // between cq_rd2_pvld and cq_rd2_prdy when doing full bypass +reg [2:0] rd_skid2_0; // head skid reg +reg [2:0] rd_skid2_1; // head+1 skid reg +reg [2:0] rd_skid2_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid2_0_vld; // head skid reg has valid data +reg rd_skid2_1_vld; // head+1 skid reg has valid data +reg rd_skid2_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd2_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_prdy_d <= 1'b1; + end else begin + cq_rd2_prdy_d <= cq_rd2_prdy; + end +end +assign cq_rd2_pvld = rd_skid2_0_vld || rd_pre_bypassing2; // full bypass for 0-latency +assign cq_rd2_pd = rd_skid2_0_vld ? rd_skid2_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld)) ) begin + rd_skid2_0 <= rd_take_n_dly[2] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld ) begin + rd_skid2_0 <= rd_skid2_1; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_0_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_1_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_1_vld) ) begin + end else begin + rd_skid2_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld)) ) begin + rd_skid2_1 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld ) begin + rd_skid2_1 <= rd_skid2_2; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && (!rd_skid2_1_vld || (cq_rd2_pvld && cq_rd2_prdy && !rd_skid2_2_vld))) && + !(cq_rd2_pvld && cq_rd2_prdy && rd_skid2_2_vld) ) begin + end else begin + rd_skid2_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy)) ) begin + rd_skid2_2 <= rd_bypassing2 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing2 || rd_take_n_dly[2]) && rd_skid2_0_vld && rd_skid2_1_vld && (rd_skid2_2_vld || !(cq_rd2_pvld && cq_rd2_prdy))) ) begin + end else begin + rd_skid2_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid2_0_vld <= 1'b0; + rd_skid2_1_vld <= 1'b0; + rd_skid2_2_vld <= 1'b0; + end else begin + rd_skid2_0_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_1_vld || (rd_bypassing2 && rd_skid2_0_vld) || rd_take_n_dly[2]) : (rd_skid2_0_vld || rd_bypassing2 || rd_take_n_dly[2]); + rd_skid2_1_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))) : (rd_skid2_1_vld || (rd_skid2_0_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage off + rd_skid2_2_vld <= (cq_rd2_pvld && cq_rd2_prdy) ? (rd_skid2_2_vld && (rd_bypassing2 || rd_take_n_dly[2])) : (rd_skid2_2_vld || (rd_skid2_1_vld && (rd_bypassing2 || rd_take_n_dly[2]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd2_credits; // unused credits +reg cq_rd2_credits_ne0; +wire [8:0] cq_rd2_credits_w_take_next = cq_rd2_credits + cq_rd_credit[2] - 1'b1; +wire [8:0] cq_rd2_credits_wo_take_next = cq_rd2_credits + cq_rd_credit[2]; +wire [8:0] cq_rd2_credits_next = rd_take2 ? cq_rd2_credits_w_take_next : cq_rd2_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[2] = (cq_rd2_prdy_d || !rd_skid2_0_vld || !rd_skid2_1_vld || (!rd_skid2_2_vld && !rd_take_n_dly[2])) && (cq_rd_credit[2] || cq_rd2_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing2 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd2) && cq_rd2_credits == 0 && !cq_rd_credit[2] && (!rd_take_n_dly[2] || rd_skid2_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing2 = rd_pre_bypassing2 && (!rd_skid2_2_vld || !rd_skid2_1_vld || !(!cq_rd2_prdy_d && rd_skid2_0_vld && rd_skid2_1_vld)) && !rd_take_n_dly[2]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd2_credits <= 9'd0; + cq_rd2_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[2] | rd_take2 ) begin + cq_rd2_credits <= cq_rd2_credits_next; + cq_rd2_credits_ne0 <= rd_take2 ? (cq_rd2_credits_w_take_next != 0) : (cq_rd2_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[2] | rd_take2) ) begin + end else begin + cq_rd2_credits <= {9{`x_or_0}}; + cq_rd2_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing3; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing3; // between cq_rd3_pvld and cq_rd3_prdy when doing full bypass +reg [2:0] rd_skid3_0; // head skid reg +reg [2:0] rd_skid3_1; // head+1 skid reg +reg [2:0] rd_skid3_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid3_0_vld; // head skid reg has valid data +reg rd_skid3_1_vld; // head+1 skid reg has valid data +reg rd_skid3_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd3_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_prdy_d <= 1'b1; + end else begin + cq_rd3_prdy_d <= cq_rd3_prdy; + end +end +assign cq_rd3_pvld = rd_skid3_0_vld || rd_pre_bypassing3; // full bypass for 0-latency +assign cq_rd3_pd = rd_skid3_0_vld ? rd_skid3_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld)) ) begin + rd_skid3_0 <= rd_take_n_dly[3] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld ) begin + rd_skid3_0 <= rd_skid3_1; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_0_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_1_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_1_vld) ) begin + end else begin + rd_skid3_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld)) ) begin + rd_skid3_1 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld ) begin + rd_skid3_1 <= rd_skid3_2; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && (!rd_skid3_1_vld || (cq_rd3_pvld && cq_rd3_prdy && !rd_skid3_2_vld))) && + !(cq_rd3_pvld && cq_rd3_prdy && rd_skid3_2_vld) ) begin + end else begin + rd_skid3_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy)) ) begin + rd_skid3_2 <= rd_bypassing3 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing3 || rd_take_n_dly[3]) && rd_skid3_0_vld && rd_skid3_1_vld && (rd_skid3_2_vld || !(cq_rd3_pvld && cq_rd3_prdy))) ) begin + end else begin + rd_skid3_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid3_0_vld <= 1'b0; + rd_skid3_1_vld <= 1'b0; + rd_skid3_2_vld <= 1'b0; + end else begin + rd_skid3_0_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_1_vld || (rd_bypassing3 && rd_skid3_0_vld) || rd_take_n_dly[3]) : (rd_skid3_0_vld || rd_bypassing3 || rd_take_n_dly[3]); + rd_skid3_1_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))) : (rd_skid3_1_vld || (rd_skid3_0_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage off + rd_skid3_2_vld <= (cq_rd3_pvld && cq_rd3_prdy) ? (rd_skid3_2_vld && (rd_bypassing3 || rd_take_n_dly[3])) : (rd_skid3_2_vld || (rd_skid3_1_vld && (rd_bypassing3 || rd_take_n_dly[3]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd3_credits; // unused credits +reg cq_rd3_credits_ne0; +wire [8:0] cq_rd3_credits_w_take_next = cq_rd3_credits + cq_rd_credit[3] - 1'b1; +wire [8:0] cq_rd3_credits_wo_take_next = cq_rd3_credits + cq_rd_credit[3]; +wire [8:0] cq_rd3_credits_next = rd_take3 ? cq_rd3_credits_w_take_next : cq_rd3_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[3] = (cq_rd3_prdy_d || !rd_skid3_0_vld || !rd_skid3_1_vld || (!rd_skid3_2_vld && !rd_take_n_dly[3])) && (cq_rd_credit[3] || cq_rd3_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing3 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd3) && cq_rd3_credits == 0 && !cq_rd_credit[3] && (!rd_take_n_dly[3] || rd_skid3_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing3 = rd_pre_bypassing3 && (!rd_skid3_2_vld || !rd_skid3_1_vld || !(!cq_rd3_prdy_d && rd_skid3_0_vld && rd_skid3_1_vld)) && !rd_take_n_dly[3]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd3_credits <= 9'd0; + cq_rd3_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[3] | rd_take3 ) begin + cq_rd3_credits <= cq_rd3_credits_next; + cq_rd3_credits_ne0 <= rd_take3 ? (cq_rd3_credits_w_take_next != 0) : (cq_rd3_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[3] | rd_take3) ) begin + end else begin + cq_rd3_credits <= {9{`x_or_0}}; + cq_rd3_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_pre_bypassing4; // bypassing is split up into two parts to avoid combinatorial loop +wire rd_bypassing4; // between cq_rd4_pvld and cq_rd4_prdy when doing full bypass +reg [2:0] rd_skid4_0; // head skid reg +reg [2:0] rd_skid4_1; // head+1 skid reg +reg [2:0] rd_skid4_2; // head+2 skid reg (for -rd_take_reg) +reg rd_skid4_0_vld; // head skid reg has valid data +reg rd_skid4_1_vld; // head+1 skid reg has valid data +reg rd_skid4_2_vld; // head+2 skid reg has valid data (for -rd_take_reg) +reg cq_rd4_prdy_d; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_prdy_d <= 1'b1; + end else begin + cq_rd4_prdy_d <= cq_rd4_prdy; + end +end +assign cq_rd4_pvld = rd_skid4_0_vld || rd_pre_bypassing4; // full bypass for 0-latency +assign cq_rd4_pd = rd_skid4_0_vld ? rd_skid4_0 : cq_wr_pd; // full bypass for 0-latency +always @( posedge nvdla_core_clk_mgated_skid ) begin + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld)) ) begin + rd_skid4_0 <= rd_take_n_dly[4] ? cq_rd_pd_p : cq_wr_pd; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld ) begin + rd_skid4_0 <= rd_skid4_1; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_0_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_1_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_1_vld) ) begin + end else begin + rd_skid4_0 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld)) ) begin + rd_skid4_1 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end else if ( cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld ) begin + rd_skid4_1 <= rd_skid4_2; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && (!rd_skid4_1_vld || (cq_rd4_pvld && cq_rd4_prdy && !rd_skid4_2_vld))) && + !(cq_rd4_pvld && cq_rd4_prdy && rd_skid4_2_vld) ) begin + end else begin + rd_skid4_1 <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( (rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy)) ) begin + rd_skid4_2 <= rd_bypassing4 ? cq_wr_pd : cq_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_bypassing4 || rd_take_n_dly[4]) && rd_skid4_0_vld && rd_skid4_1_vld && (rd_skid4_2_vld || !(cq_rd4_pvld && cq_rd4_prdy))) ) begin + end else begin + rd_skid4_2 <= {3{`x_or_0}}; + end +//synopsys translate_on +end +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_skid4_0_vld <= 1'b0; + rd_skid4_1_vld <= 1'b0; + rd_skid4_2_vld <= 1'b0; + end else begin + rd_skid4_0_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_1_vld || (rd_bypassing4 && rd_skid4_0_vld) || rd_take_n_dly[4]) : (rd_skid4_0_vld || rd_bypassing4 || rd_take_n_dly[4]); + rd_skid4_1_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))) : (rd_skid4_1_vld || (rd_skid4_0_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage off + rd_skid4_2_vld <= (cq_rd4_pvld && cq_rd4_prdy) ? (rd_skid4_2_vld && (rd_bypassing4 || rd_take_n_dly[4])) : (rd_skid4_2_vld || (rd_skid4_1_vld && (rd_bypassing4 || rd_take_n_dly[4]))); +//VCS coverage on + end +end +// spyglass disable_block W164a W116 W484 +reg [8:0] cq_rd4_credits; // unused credits +reg cq_rd4_credits_ne0; +wire [8:0] cq_rd4_credits_w_take_next = cq_rd4_credits + cq_rd_credit[4] - 1'b1; +wire [8:0] cq_rd4_credits_wo_take_next = cq_rd4_credits + cq_rd_credit[4]; +wire [8:0] cq_rd4_credits_next = rd_take4 ? cq_rd4_credits_w_take_next : cq_rd4_credits_wo_take_next; +// spyglass enable_block W164a W116 W484 +//VCS coverage off +assign cq_rd_take_elig[4] = (cq_rd4_prdy_d || !rd_skid4_0_vld || !rd_skid4_1_vld || (!rd_skid4_2_vld && !rd_take_n_dly[4])) && (cq_rd_credit[4] || cq_rd4_credits_ne0); +//VCS coverage on +assign rd_pre_bypassing4 = cq_wr_pvld && !cq_wr_busy_int && (cq_wr_thread_id == 3'd4) && cq_rd4_credits == 0 && !cq_rd_credit[4] && (!rd_take_n_dly[4] || rd_skid4_0_vld); // split this up to avoid combinatorial loop when full bypass is in effect +assign rd_bypassing4 = rd_pre_bypassing4 && (!rd_skid4_2_vld || !rd_skid4_1_vld || !(!cq_rd4_prdy_d && rd_skid4_0_vld && rd_skid4_1_vld)) && !rd_take_n_dly[4]; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd4_credits <= 9'd0; + cq_rd4_credits_ne0 <= 1'b0; + end else begin + if ( cq_rd_credit[4] | rd_take4 ) begin + cq_rd4_credits <= cq_rd4_credits_next; + cq_rd4_credits_ne0 <= rd_take4 ? (cq_rd4_credits_w_take_next != 0) : (cq_rd4_credits_wo_take_next != 0); + end +//synopsys translate_off + else if ( ! (cq_rd_credit[4] | rd_take4) ) begin + end else begin + cq_rd4_credits <= {9{`x_or_0}}; + cq_rd4_credits_ne0 <= `x_or_0; + end +//synopsys translate_on + end +end +// rd_take round-robin arbiter (similar to arbgen output) +// +assign cq_rd_take = |cq_rd_take_elig; // any thread is eligible to take, so issue take +reg [2:0] cq_rd_take_thread_id_last; +wire [4:0] cq_rd_take_thread_id_is_1 = { + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[0], + cq_rd_take_elig[1] && cq_rd_take_thread_id_last == 3'd0}; +wire [4:0] cq_rd_take_thread_id_is_2 = { + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd2 && !cq_rd_take_elig[3] && !cq_rd_take_elig[4] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1], + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd1, + cq_rd_take_elig[2] && cq_rd_take_thread_id_last == 3'd0 && !cq_rd_take_elig[1]}; +wire [4:0] cq_rd_take_thread_id_is_3 = { + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd3 && !cq_rd_take_elig[4] && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd2, + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd1 && !cq_rd_take_elig[2], + cq_rd_take_elig[3] && cq_rd_take_thread_id_last == 3'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2]}; +wire [4:0] cq_rd_take_thread_id_is_4 = { + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd4 && !cq_rd_take_elig[0] && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd3, + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd2 && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd1 && !cq_rd_take_elig[2] && !cq_rd_take_elig[3], + cq_rd_take_elig[4] && cq_rd_take_thread_id_last == 3'd0 && !cq_rd_take_elig[1] && !cq_rd_take_elig[2] && !cq_rd_take_elig[3]}; +assign cq_rd_take_thread_id[0] = |{cq_rd_take_thread_id_is_1,cq_rd_take_thread_id_is_3}; +assign cq_rd_take_thread_id[1] = |{cq_rd_take_thread_id_is_2,cq_rd_take_thread_id_is_3}; +assign cq_rd_take_thread_id[2] = |{cq_rd_take_thread_id_is_4}; +always @( posedge nvdla_core_clk_mgated_skid or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq_rd_take_thread_id_last <= 3'd0; + end else begin + if ( cq_rd_take ) begin + cq_rd_take_thread_id_last <= cq_rd_take_thread_id; + end +//synopsys translate_off + else if ( !cq_rd_take ) begin + end else begin + cq_rd_take_thread_id_last <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +assign wr_bypassing = rd_bypassing0 || rd_bypassing1 || rd_bypassing2 || rd_bypassing3 || rd_bypassing4; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cq_wr_pvld && !cq_wr_busy_int) || (cq_wr_busy_int != cq_wr_busy_next) || rd_popping) || (rd_pushing || cq_rd_take || cq_rd_credit != 5'd0 || rd_take_dly)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +assign nvdla_core_clk_mgated_skid_enable = nvdla_core_clk_mgated_enable || ( cq_rd0_pvld && cq_rd0_prdy ) || rd_bypassing0 || ( cq_rd1_pvld && cq_rd1_prdy ) || rd_bypassing1 || ( cq_rd2_pvld && cq_rd2_prdy ) || rd_bypassing2 || ( cq_rd3_pvld && cq_rd3_prdy ) || rd_bypassing3 || ( cq_rd4_pvld && cq_rd4_prdy ) || rd_bypassing4 + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit : 9'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 9'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 9'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 9'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [8:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_NOCIF_DRAM_WRITE_cq_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cq_wr_pvld && !(!cq_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} ) + , .curr ( {23'd0, cq_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check0 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd0 ), + .credit ( cq_rd_credit[0] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check1 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd1 ), + .credit ( cq_rd_credit[1] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check2 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd2 ), + .credit ( cq_rd_credit[2] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check3 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd3 ), + .credit ( cq_rd_credit[3] ) + ); +nv_assert_vld_credit_max #(0, 0, 256, 0, "FIFOGEN_ASSERTION A take occurred without credits being available") + fifogen_rd_take_credit_check4 ( .clk ( nvdla_core_clk ), + .reset_ ( ( nvdla_core_rstn === 1'bx ? 1'b0 : nvdla_core_rstn ) & assert_enabled ), + .vld ( cq_rd_take && cq_rd_take_thread_id == 3'd4 ), + .credit ( cq_rd_credit[4] ) + ); +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_NOCIF_DRAM_WRITE_cq") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_NOCIF_DRAM_WRITE_cq +// +// generate free list fifo for use from read side to write side +// diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v new file mode 100644 index 0000000..8e6aa69 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v @@ -0,0 +1,326 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_eg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_eg ( + nvdla_core_clk + ,nvdla_core_rstn +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: ,cq_rd${i}_pvld +//: ,cq_rd${i}_pd +//: ,cq_rd${i}_prdy +//: ,mcif2client${i}_wr_rsp_complete +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,cq_rd0_pvld +,cq_rd0_pd +,cq_rd0_prdy +,mcif2client0_wr_rsp_complete + +,cq_rd1_pvld +,cq_rd1_pd +,cq_rd1_prdy +,mcif2client1_wr_rsp_complete + +,cq_rd2_pvld +,cq_rd2_pd +,cq_rd2_prdy +,mcif2client2_wr_rsp_complete + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,noc2mcif_axi_b_bid + ,noc2mcif_axi_b_bvalid + ,eg2ig_axi_len + ,eg2ig_axi_vld + ,noc2mcif_axi_b_bready +); +input nvdla_core_clk; +input nvdla_core_rstn; +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:output mcif2client${i}_wr_rsp_complete; +//:input cq_rd${i}_pvld; +//:output cq_rd${i}_prdy; +//:input [2:0] cq_rd${i}_pd; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output mcif2client0_wr_rsp_complete; +input cq_rd0_pvld; +output cq_rd0_prdy; +input [2:0] cq_rd0_pd; + +output mcif2client1_wr_rsp_complete; +input cq_rd1_pvld; +output cq_rd1_prdy; +input [2:0] cq_rd1_pd; + +output mcif2client2_wr_rsp_complete; +input cq_rd2_pvld; +output cq_rd2_prdy; +input [2:0] cq_rd2_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +output [1:0] eg2ig_axi_len; +output eg2ig_axi_vld; +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:reg mcif2client${i}_wr_rsp_complete; +//:wire [1:0] cq_rd${i}_len; +//:wire cq_rd${i}_require_ack; +//:wire dma${i}_vld; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg mcif2client0_wr_rsp_complete; +wire [1:0] cq_rd0_len; +wire cq_rd0_require_ack; +wire dma0_vld; + +reg mcif2client1_wr_rsp_complete; +wire [1:0] cq_rd1_len; +wire cq_rd1_require_ack; +wire dma1_vld; + +reg mcif2client2_wr_rsp_complete; +wire [1:0] cq_rd2_len; +wire cq_rd2_require_ack; +wire dma2_vld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [1:0] eg2ig_axi_len; +reg [2:0] iflop_axi_axid; +reg iflop_axi_vld; +//stepheng,remove for no loading. +// TIE-OFFs +//assign noc2mcif_axi_b_bresp_NC = noc2mcif_axi_b_bresp; +//assign noc2mcif_axi_b_buser_NC = noc2mcif_axi_b_buser; +//assign noc2mcif_axi_b_bid_NC = noc2mcif_axi_b_bid; +// +wire cq_vld = +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: (!cq_rd${i}_pvld & cq_rd${i}_prdy) | +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +(!cq_rd0_pvld & cq_rd0_prdy) | + +(!cq_rd1_pvld & cq_rd1_prdy) | + +(!cq_rd2_pvld & cq_rd2_prdy) | + +//| eperl: generated_end (DO NOT EDIT ABOVE) +0; +assign noc2mcif_axi_b_bready = !cq_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + iflop_axi_vld <= 1'b0; + end else begin + if (noc2mcif_axi_b_bready) + iflop_axi_vld <= noc2mcif_axi_b_bvalid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + iflop_axi_axid <= {3{1'b0}}; + end else begin + if ((noc2mcif_axi_b_bvalid & noc2mcif_axi_b_bready) == 1'b1) begin + iflop_axi_axid <= noc2mcif_axi_b_bid[2:0]; +// VCS coverage off + end else if ((noc2mcif_axi_b_bvalid) == 1'b0) begin + end else begin + iflop_axi_axid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(noc2mcif_axi_b_bvalid))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// EG===Contect Qeueu +//:my $i; +//:my @dma_index = (0, 1,1, 1,0, 0, 0, 0, 0,0,0,0,0,0,0); +//:my @client_id = (0,1,2,3,4,0,0,0,0,0,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:for($i=0;$i<3;$i++) { +//:print qq( +//:assign dma${i}_vld = iflop_axi_vld & (iflop_axi_axid == $remap_clientid[$i]); +//:assign cq_rd${i}_prdy = dma${i}_vld; +//:assign cq_rd${i}_require_ack = cq_rd${i}_pd[0:0]; +//:assign cq_rd${i}_len = cq_rd${i}_pd[2:1]; +//:always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: mcif2client${i}_wr_rsp_complete <= 1'b0; +//: end else begin +//: mcif2client${i}_wr_rsp_complete <= dma${i}_vld & cq_rd${i}_pvld & cq_rd${i}_require_ack; +//: end +//:end +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign dma0_vld = iflop_axi_vld & (iflop_axi_axid == 1); +assign cq_rd0_prdy = dma0_vld; +assign cq_rd0_require_ack = cq_rd0_pd[0:0]; +assign cq_rd0_len = cq_rd0_pd[2:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +mcif2client0_wr_rsp_complete <= 1'b0; +end else begin +mcif2client0_wr_rsp_complete <= dma0_vld & cq_rd0_pvld & cq_rd0_require_ack; +end +end + +assign dma1_vld = iflop_axi_vld & (iflop_axi_axid == 2); +assign cq_rd1_prdy = dma1_vld; +assign cq_rd1_require_ack = cq_rd1_pd[0:0]; +assign cq_rd1_len = cq_rd1_pd[2:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +mcif2client1_wr_rsp_complete <= 1'b0; +end else begin +mcif2client1_wr_rsp_complete <= dma1_vld & cq_rd1_pvld & cq_rd1_require_ack; +end +end + +assign dma2_vld = iflop_axi_vld & (iflop_axi_axid == 3); +assign cq_rd2_prdy = dma2_vld; +assign cq_rd2_require_ack = cq_rd2_pd[0:0]; +assign cq_rd2_len = cq_rd2_pd[2:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) begin +mcif2client2_wr_rsp_complete <= 1'b0; +end else begin +mcif2client2_wr_rsp_complete <= dma2_vld & cq_rd2_pvld & cq_rd2_require_ack; +end +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// EG2IG outstanding Counting +assign eg2ig_axi_vld = iflop_axi_vld & noc2mcif_axi_b_bready; +always @( +dma0_vld or +cq_rd0_len +//:my $i; +//:for($i=1;$i<3;$i++) { +//:print qq( +//:or dma${i}_vld +//:or cq_rd${i}_len +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +or dma1_vld +or cq_rd1_len + +or dma2_vld +or cq_rd2_len + +//| eperl: generated_end (DO NOT EDIT ABOVE) +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:dma${i}_vld: eg2ig_axi_len = cq_rd${i}_len; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +dma0_vld: eg2ig_axi_len = cq_rd0_len; + +dma1_vld: eg2ig_axi_len = cq_rd1_len; + +dma2_vld: eg2ig_axi_len = cq_rd2_len; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//VCS coverage off + default : begin + eg2ig_axi_len[1:0] = {2{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +endmodule // NV_NVDLA_CVIF_WRITE_eg diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v.vcp new file mode 100644 index 0000000..a8102aa --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v.vcp @@ -0,0 +1,206 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_eg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_eg ( + nvdla_core_clk + ,nvdla_core_rstn +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: ,cq_rd${i}_pvld +//: ,cq_rd${i}_pd +//: ,cq_rd${i}_prdy +//: ,mcif2client${i}_wr_rsp_complete +//:); +//:} + ,noc2mcif_axi_b_bid + ,noc2mcif_axi_b_bvalid + ,eg2ig_axi_len + ,eg2ig_axi_vld + ,noc2mcif_axi_b_bready +); +input nvdla_core_clk; +input nvdla_core_rstn; +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:output mcif2client${i}_wr_rsp_complete; +//:input cq_rd${i}_pvld; +//:output cq_rd${i}_prdy; +//:input [2:0] cq_rd${i}_pd; +//:); +//:} +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +output [1:0] eg2ig_axi_len; +output eg2ig_axi_vld; +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:reg mcif2client${i}_wr_rsp_complete; +//:wire [1:0] cq_rd${i}_len; +//:wire cq_rd${i}_require_ack; +//:wire dma${i}_vld; +//:); +//:} +reg [1:0] eg2ig_axi_len; +reg [2:0] iflop_axi_axid; +reg iflop_axi_vld; +//stepheng,remove for no loading. +// TIE-OFFs +//assign noc2mcif_axi_b_bresp_NC = noc2mcif_axi_b_bresp; +//assign noc2mcif_axi_b_buser_NC = noc2mcif_axi_b_buser; +//assign noc2mcif_axi_b_bid_NC = noc2mcif_axi_b_bid; +// +wire cq_vld = +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//: (!cq_rd${i}_pvld & cq_rd${i}_prdy) | +//:); +//:} +0; +assign noc2mcif_axi_b_bready = !cq_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + iflop_axi_vld <= 1'b0; + end else begin + if (noc2mcif_axi_b_bready) + iflop_axi_vld <= noc2mcif_axi_b_bvalid; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + iflop_axi_axid <= {3{1'b0}}; + end else begin + if ((noc2mcif_axi_b_bvalid & noc2mcif_axi_b_bready) == 1'b1) begin + iflop_axi_axid <= noc2mcif_axi_b_bid[2:0]; +// VCS coverage off + end else if ((noc2mcif_axi_b_bvalid) == 1'b0) begin + end else begin + iflop_axi_axid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(noc2mcif_axi_b_bvalid))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// EG===Contect Qeueu +//:my $i; +//:my @dma_index = (0, 1,1, 1,0, 0, 0, 0, 0,0,0,0,0,0,0); +//:my @client_id = (0,1,2,3,4,0,0,0,0,0,0,0,0,0,0,0); +//:my @remap_clientid = (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0); +//:my $nindex = 0; +//:for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i] != 0) { +//: $remap_clientid[$nindex] = $client_id[$i]; +//: $nindex++; +//: } +//:} +//:for($i=0;$i<3;$i++) { +//:print qq( +//:assign dma${i}_vld = iflop_axi_vld & (iflop_axi_axid == $remap_clientid[$i]); +//:assign cq_rd${i}_prdy = dma${i}_vld; +//:assign cq_rd${i}_require_ack = cq_rd${i}_pd[0:0]; +//:assign cq_rd${i}_len = cq_rd${i}_pd[2:1]; +//:always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: mcif2client${i}_wr_rsp_complete <= 1'b0; +//: end else begin +//: mcif2client${i}_wr_rsp_complete <= dma${i}_vld & cq_rd${i}_pvld & cq_rd${i}_require_ack; +//: end +//:end +//:); +//:} +// EG2IG outstanding Counting +assign eg2ig_axi_vld = iflop_axi_vld & noc2mcif_axi_b_bready; +always @( +dma0_vld or +cq_rd0_len +//:my $i; +//:for($i=1;$i<3;$i++) { +//:print qq( +//:or dma${i}_vld +//:or cq_rd${i}_len +//:); +//:} +) begin +//spyglass disable_block W171 W226 + case (1'b1) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:dma${i}_vld: eg2ig_axi_len = cq_rd${i}_len; +//:); +//:} +//VCS coverage off + default : begin + eg2ig_axi_len[1:0] = {2{`x_or_0}}; + end +//VCS coverage on + endcase +//spyglass enable_block W171 W226 +end +endmodule // NV_NVDLA_CVIF_WRITE_eg diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v new file mode 100644 index 0000000..6199491 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v @@ -0,0 +1,322 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_ig.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd + ,reg2dp_wr_os_cnt +//:my $k=3; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print qq( +//:,client${i}2mcif_wr_req_pd +//:,client${i}2mcif_wr_req_valid +//:,client${i}2mcif_wr_req_ready +//:,client${i}2mcif_wr_wt +//:,client${i}2mcif_wr_axid +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,client02mcif_wr_req_pd +,client02mcif_wr_req_valid +,client02mcif_wr_req_ready +,client02mcif_wr_wt +,client02mcif_wr_axid + +,client12mcif_wr_req_pd +,client12mcif_wr_req_valid +,client12mcif_wr_req_ready +,client12mcif_wr_wt +,client12mcif_wr_axid + +,client22mcif_wr_req_pd +,client22mcif_wr_req_valid +,client22mcif_wr_req_ready +,client22mcif_wr_wt +,client22mcif_wr_axid + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,cq_wr_pvld + ,cq_wr_prdy + ,cq_wr_thread_id + ,cq_wr_pd + ,mcif2noc_axi_aw_awvalid + ,mcif2noc_axi_aw_awready + ,mcif2noc_axi_aw_awid + ,mcif2noc_axi_aw_awlen + ,mcif2noc_axi_aw_awaddr + ,mcif2noc_axi_w_wvalid + ,mcif2noc_axi_w_wready + ,mcif2noc_axi_w_wdata + ,mcif2noc_axi_w_wstrb + ,mcif2noc_axi_w_wlast + ,eg2ig_axi_len + ,eg2ig_axi_vld + ); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:input client${i}2mcif_wr_req_valid; +//:output client${i}2mcif_wr_req_ready; +//:input [64 +1:0] client${i}2mcif_wr_req_pd; +//:input [7:0] client${i}2mcif_wr_wt; +//:input [3:0] client${i}2mcif_wr_axid; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input client02mcif_wr_req_valid; +output client02mcif_wr_req_ready; +input [64 +1:0] client02mcif_wr_req_pd; +input [7:0] client02mcif_wr_wt; +input [3:0] client02mcif_wr_axid; + +input client12mcif_wr_req_valid; +output client12mcif_wr_req_ready; +input [64 +1:0] client12mcif_wr_req_pd; +input [7:0] client12mcif_wr_wt; +input [3:0] client12mcif_wr_axid; + +input client22mcif_wr_req_valid; +output client22mcif_wr_req_ready; +input [64 +1:0] client22mcif_wr_req_pd; +input [7:0] client22mcif_wr_wt; +input [3:0] client22mcif_wr_axid; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input [7:0] reg2dp_wr_os_cnt; +input [1:0] eg2ig_axi_len; +input eg2ig_axi_vld; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [2:0] cq_wr_pd; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +wire arb2spt_dat_valid, arb2spt_dat_ready; +wire spt2cvt_dat_valid,spt2cvt_dat_ready; +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:wire bpt2arb_cmd${i}_valid; +//:wire bpt2arb_cmd${i}_ready; +//:wire [32 +12:0] bpt2arb_cmd${i}_pd; +//:wire bpt2arb_dat${i}_valid; +//:wire bpt2arb_dat${i}_ready; +//:wire [64:0] bpt2arb_dat${i}_pd; +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt u_bpt${i} ( +//:.nvdla_core_clk (nvdla_core_clk) +//:,.nvdla_core_rstn (nvdla_core_rstn) +//:,.dma2bpt_req_valid (client${i}2mcif_wr_req_valid) +//:,.dma2bpt_req_ready (client${i}2mcif_wr_req_ready) +//:,.dma2bpt_req_pd (client${i}2mcif_wr_req_pd) +//:,.bpt2arb_cmd_valid (bpt2arb_cmd${i}_valid) +//:,.bpt2arb_cmd_ready (bpt2arb_cmd${i}_ready) +//:,.bpt2arb_cmd_pd (bpt2arb_cmd${i}_pd) +//:,.bpt2arb_dat_valid (bpt2arb_dat${i}_valid) +//:,.bpt2arb_dat_ready (bpt2arb_dat${i}_ready) +//:,.bpt2arb_dat_pd (bpt2arb_dat${i}_pd) +//:,.pwrbus_ram_pd (pwrbus_ram_pd) +//:,.axid (client${i}2mcif_wr_axid) +//:); +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire bpt2arb_cmd0_valid; +wire bpt2arb_cmd0_ready; +wire [32 +12:0] bpt2arb_cmd0_pd; +wire bpt2arb_dat0_valid; +wire bpt2arb_dat0_ready; +wire [64:0] bpt2arb_dat0_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt u_bpt0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dma2bpt_req_valid (client02mcif_wr_req_valid) +,.dma2bpt_req_ready (client02mcif_wr_req_ready) +,.dma2bpt_req_pd (client02mcif_wr_req_pd) +,.bpt2arb_cmd_valid (bpt2arb_cmd0_valid) +,.bpt2arb_cmd_ready (bpt2arb_cmd0_ready) +,.bpt2arb_cmd_pd (bpt2arb_cmd0_pd) +,.bpt2arb_dat_valid (bpt2arb_dat0_valid) +,.bpt2arb_dat_ready (bpt2arb_dat0_ready) +,.bpt2arb_dat_pd (bpt2arb_dat0_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd) +,.axid (client02mcif_wr_axid) +); + +wire bpt2arb_cmd1_valid; +wire bpt2arb_cmd1_ready; +wire [32 +12:0] bpt2arb_cmd1_pd; +wire bpt2arb_dat1_valid; +wire bpt2arb_dat1_ready; +wire [64:0] bpt2arb_dat1_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt u_bpt1 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dma2bpt_req_valid (client12mcif_wr_req_valid) +,.dma2bpt_req_ready (client12mcif_wr_req_ready) +,.dma2bpt_req_pd (client12mcif_wr_req_pd) +,.bpt2arb_cmd_valid (bpt2arb_cmd1_valid) +,.bpt2arb_cmd_ready (bpt2arb_cmd1_ready) +,.bpt2arb_cmd_pd (bpt2arb_cmd1_pd) +,.bpt2arb_dat_valid (bpt2arb_dat1_valid) +,.bpt2arb_dat_ready (bpt2arb_dat1_ready) +,.bpt2arb_dat_pd (bpt2arb_dat1_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd) +,.axid (client12mcif_wr_axid) +); + +wire bpt2arb_cmd2_valid; +wire bpt2arb_cmd2_ready; +wire [32 +12:0] bpt2arb_cmd2_pd; +wire bpt2arb_dat2_valid; +wire bpt2arb_dat2_ready; +wire [64:0] bpt2arb_dat2_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt u_bpt2 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dma2bpt_req_valid (client22mcif_wr_req_valid) +,.dma2bpt_req_ready (client22mcif_wr_req_ready) +,.dma2bpt_req_pd (client22mcif_wr_req_pd) +,.bpt2arb_cmd_valid (bpt2arb_cmd2_valid) +,.bpt2arb_cmd_ready (bpt2arb_cmd2_ready) +,.bpt2arb_cmd_pd (bpt2arb_cmd2_pd) +,.bpt2arb_dat_valid (bpt2arb_dat2_valid) +,.bpt2arb_dat_ready (bpt2arb_dat2_ready) +,.bpt2arb_dat_pd (bpt2arb_dat2_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd) +,.axid (client22mcif_wr_axid) +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [32 +12:0] arb2spt_cmd_pd; +wire [64:0] arb2spt_dat_pd; +wire arb2spt_cmd_valid, arb2spt_cmd_ready; +wire spt2cvt_cmd_valid, spt2cvt_cmd_ready; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb u_arb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.bpt2arb_cmd${i}_valid (bpt2arb_cmd${i}_valid) +//:,.bpt2arb_cmd${i}_ready (bpt2arb_cmd${i}_ready) +//:,.bpt2arb_cmd${i}_pd (bpt2arb_cmd${i}_pd) +//:,.bpt2arb_dat${i}_valid (bpt2arb_dat${i}_valid) +//:,.bpt2arb_dat${i}_ready (bpt2arb_dat${i}_ready) +//:,.bpt2arb_dat${i}_pd (bpt2arb_dat${i}_pd) +//:,.client${i}2mcif_wr_wt (client${i}2mcif_wr_wt) +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.bpt2arb_cmd0_valid (bpt2arb_cmd0_valid) +,.bpt2arb_cmd0_ready (bpt2arb_cmd0_ready) +,.bpt2arb_cmd0_pd (bpt2arb_cmd0_pd) +,.bpt2arb_dat0_valid (bpt2arb_dat0_valid) +,.bpt2arb_dat0_ready (bpt2arb_dat0_ready) +,.bpt2arb_dat0_pd (bpt2arb_dat0_pd) +,.client02mcif_wr_wt (client02mcif_wr_wt) + +,.bpt2arb_cmd1_valid (bpt2arb_cmd1_valid) +,.bpt2arb_cmd1_ready (bpt2arb_cmd1_ready) +,.bpt2arb_cmd1_pd (bpt2arb_cmd1_pd) +,.bpt2arb_dat1_valid (bpt2arb_dat1_valid) +,.bpt2arb_dat1_ready (bpt2arb_dat1_ready) +,.bpt2arb_dat1_pd (bpt2arb_dat1_pd) +,.client12mcif_wr_wt (client12mcif_wr_wt) + +,.bpt2arb_cmd2_valid (bpt2arb_cmd2_valid) +,.bpt2arb_cmd2_ready (bpt2arb_cmd2_ready) +,.bpt2arb_cmd2_pd (bpt2arb_cmd2_pd) +,.bpt2arb_dat2_valid (bpt2arb_dat2_valid) +,.bpt2arb_dat2_ready (bpt2arb_dat2_ready) +,.bpt2arb_dat2_pd (bpt2arb_dat2_pd) +,.client22mcif_wr_wt (client22mcif_wr_wt) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|> w + ,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|< w + ,.arb2spt_cmd_pd (arb2spt_cmd_pd[32 +12:0]) //|> w + ,.arb2spt_dat_valid (arb2spt_dat_valid) //|> w + ,.arb2spt_dat_ready (arb2spt_dat_ready) //|< w + ,.arb2spt_dat_pd (arb2spt_dat_pd[64:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< +); +wire [32 +12:0] spt2cvt_cmd_pd; +wire [64:0] spt2cvt_dat_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt u_spt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|< w + ,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|> w + ,.arb2spt_cmd_pd (arb2spt_cmd_pd[32 +12:0]) //|< w + ,.arb2spt_dat_valid (arb2spt_dat_valid) //|< w + ,.arb2spt_dat_ready (arb2spt_dat_ready) //|> w + ,.arb2spt_dat_pd (arb2spt_dat_pd[64:0]) //|< w + ,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|> w + ,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|< w + ,.spt2cvt_cmd_pd (spt2cvt_cmd_pd[32 +12:0]) //|> w + ,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|> w + ,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|< w + ,.spt2cvt_dat_pd (spt2cvt_dat_pd[64:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt u_cvt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|< w + ,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|> w + ,.spt2cvt_cmd_pd (spt2cvt_cmd_pd[32 +12:0]) //|< w + ,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|< w + ,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|> w + ,.spt2cvt_dat_pd (spt2cvt_dat_pd[64:0]) //|< w + ,.cq_wr_pvld (cq_wr_pvld) //|> o + ,.cq_wr_prdy (cq_wr_prdy) //|< i + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> o + ,.cq_wr_pd (cq_wr_pd[2:0]) //|> o + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr[32 -1:0]) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata[64 -1:0]) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb[64/8-1:0]) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.eg2ig_axi_len (eg2ig_axi_len[1:0]) //|< i + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|< i + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v.vcp new file mode 100644 index 0000000..09d5336 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v.vcp @@ -0,0 +1,184 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_WRITE_ig.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_WRITE_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd + ,reg2dp_wr_os_cnt +//:my $k=3; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print qq( +//:,client${i}2mcif_wr_req_pd +//:,client${i}2mcif_wr_req_valid +//:,client${i}2mcif_wr_req_ready +//:,client${i}2mcif_wr_wt +//:,client${i}2mcif_wr_axid +//:); +//:} + ,cq_wr_pvld + ,cq_wr_prdy + ,cq_wr_thread_id + ,cq_wr_pd + ,mcif2noc_axi_aw_awvalid + ,mcif2noc_axi_aw_awready + ,mcif2noc_axi_aw_awid + ,mcif2noc_axi_aw_awlen + ,mcif2noc_axi_aw_awaddr + ,mcif2noc_axi_w_wvalid + ,mcif2noc_axi_w_wready + ,mcif2noc_axi_w_wdata + ,mcif2noc_axi_w_wstrb + ,mcif2noc_axi_w_wlast + ,eg2ig_axi_len + ,eg2ig_axi_vld + ); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:input client${i}2mcif_wr_req_valid; +//:output client${i}2mcif_wr_req_ready; +//:input [64 +1:0] client${i}2mcif_wr_req_pd; +//:input [7:0] client${i}2mcif_wr_wt; +//:input [3:0] client${i}2mcif_wr_axid; +//:); +//:} +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input [7:0] reg2dp_wr_os_cnt; +input [1:0] eg2ig_axi_len; +input eg2ig_axi_vld; +output cq_wr_pvld; /* data valid */ +input cq_wr_prdy; /* data return handshake */ +output [3:0] cq_wr_thread_id; +output [2:0] cq_wr_pd; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +wire arb2spt_dat_valid, arb2spt_dat_ready; +wire spt2cvt_dat_valid,spt2cvt_dat_ready; +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:wire bpt2arb_cmd${i}_valid; +//:wire bpt2arb_cmd${i}_ready; +//:wire [32 +12:0] bpt2arb_cmd${i}_pd; +//:wire bpt2arb_dat${i}_valid; +//:wire bpt2arb_dat${i}_ready; +//:wire [64:0] bpt2arb_dat${i}_pd; +//:NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt u_bpt${i} ( +//:.nvdla_core_clk (nvdla_core_clk) +//:,.nvdla_core_rstn (nvdla_core_rstn) +//:,.dma2bpt_req_valid (client${i}2mcif_wr_req_valid) +//:,.dma2bpt_req_ready (client${i}2mcif_wr_req_ready) +//:,.dma2bpt_req_pd (client${i}2mcif_wr_req_pd) +//:,.bpt2arb_cmd_valid (bpt2arb_cmd${i}_valid) +//:,.bpt2arb_cmd_ready (bpt2arb_cmd${i}_ready) +//:,.bpt2arb_cmd_pd (bpt2arb_cmd${i}_pd) +//:,.bpt2arb_dat_valid (bpt2arb_dat${i}_valid) +//:,.bpt2arb_dat_ready (bpt2arb_dat${i}_ready) +//:,.bpt2arb_dat_pd (bpt2arb_dat${i}_pd) +//:,.pwrbus_ram_pd (pwrbus_ram_pd) +//:,.axid (client${i}2mcif_wr_axid) +//:); +//:); +//:} +wire [32 +12:0] arb2spt_cmd_pd; +wire [64:0] arb2spt_dat_pd; +wire arb2spt_cmd_valid, arb2spt_cmd_ready; +wire spt2cvt_cmd_valid, spt2cvt_cmd_ready; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb u_arb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.bpt2arb_cmd${i}_valid (bpt2arb_cmd${i}_valid) +//:,.bpt2arb_cmd${i}_ready (bpt2arb_cmd${i}_ready) +//:,.bpt2arb_cmd${i}_pd (bpt2arb_cmd${i}_pd) +//:,.bpt2arb_dat${i}_valid (bpt2arb_dat${i}_valid) +//:,.bpt2arb_dat${i}_ready (bpt2arb_dat${i}_ready) +//:,.bpt2arb_dat${i}_pd (bpt2arb_dat${i}_pd) +//:,.client${i}2mcif_wr_wt (client${i}2mcif_wr_wt) +//:); +//:} + ,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|> w + ,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|< w + ,.arb2spt_cmd_pd (arb2spt_cmd_pd[32 +12:0]) //|> w + ,.arb2spt_dat_valid (arb2spt_dat_valid) //|> w + ,.arb2spt_dat_ready (arb2spt_dat_ready) //|< w + ,.arb2spt_dat_pd (arb2spt_dat_pd[64:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< +); +wire [32 +12:0] spt2cvt_cmd_pd; +wire [64:0] spt2cvt_dat_pd; +NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt u_spt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.arb2spt_cmd_valid (arb2spt_cmd_valid) //|< w + ,.arb2spt_cmd_ready (arb2spt_cmd_ready) //|> w + ,.arb2spt_cmd_pd (arb2spt_cmd_pd[32 +12:0]) //|< w + ,.arb2spt_dat_valid (arb2spt_dat_valid) //|< w + ,.arb2spt_dat_ready (arb2spt_dat_ready) //|> w + ,.arb2spt_dat_pd (arb2spt_dat_pd[64:0]) //|< w + ,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|> w + ,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|< w + ,.spt2cvt_cmd_pd (spt2cvt_cmd_pd[32 +12:0]) //|> w + ,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|> w + ,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|< w + ,.spt2cvt_dat_pd (spt2cvt_dat_pd[64:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt u_cvt ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.spt2cvt_cmd_valid (spt2cvt_cmd_valid) //|< w + ,.spt2cvt_cmd_ready (spt2cvt_cmd_ready) //|> w + ,.spt2cvt_cmd_pd (spt2cvt_cmd_pd[32 +12:0]) //|< w + ,.spt2cvt_dat_valid (spt2cvt_dat_valid) //|< w + ,.spt2cvt_dat_ready (spt2cvt_dat_ready) //|> w + ,.spt2cvt_dat_pd (spt2cvt_dat_pd[64:0]) //|< w + ,.cq_wr_pvld (cq_wr_pvld) //|> o + ,.cq_wr_prdy (cq_wr_prdy) //|< i + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> o + ,.cq_wr_pd (cq_wr_pd[2:0]) //|> o + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr[32 -1:0]) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata[64 -1:0]) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb[64/8-1:0]) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.eg2ig_axi_len (eg2ig_axi_len[1:0]) //|< i + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|< i + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|< i + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v new file mode 100644 index 0000000..4aeddfd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v @@ -0,0 +1,528 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_read.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_read ( + nvdla_core_clk + ,nvdla_core_rstn +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print(",client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print(",client${i}2mcif_rd_req_valid\n"); +//: print(",client${i}2mcif_rd_req_ready\n"); +//: print(",client${i}2mcif_rd_req_pd\n"); +//: print(",mcif2client${i}_rd_rsp_valid\n"); +//: print(",mcif2client${i}_rd_rsp_ready\n"); +//: print(",mcif2client${i}_rd_rsp_pd\n"), +//: print(",client${i}2mcif_rd_wt\n"), +//: print(",client${i}2mcif_rd_axid\n"), +//: print(",client${i}2mcif_lat_fifo_depth\n"), +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,client02mcif_rd_cdt_lat_fifo_pop +,client02mcif_rd_req_valid +,client02mcif_rd_req_ready +,client02mcif_rd_req_pd +,mcif2client0_rd_rsp_valid +,mcif2client0_rd_rsp_ready +,mcif2client0_rd_rsp_pd +,client02mcif_rd_wt +,client02mcif_rd_axid +,client02mcif_lat_fifo_depth +,client12mcif_rd_cdt_lat_fifo_pop +,client12mcif_rd_req_valid +,client12mcif_rd_req_ready +,client12mcif_rd_req_pd +,mcif2client1_rd_rsp_valid +,mcif2client1_rd_rsp_ready +,mcif2client1_rd_rsp_pd +,client12mcif_rd_wt +,client12mcif_rd_axid +,client12mcif_lat_fifo_depth +,client22mcif_rd_cdt_lat_fifo_pop +,client22mcif_rd_req_valid +,client22mcif_rd_req_ready +,client22mcif_rd_req_pd +,mcif2client2_rd_rsp_valid +,mcif2client2_rd_rsp_ready +,mcif2client2_rd_rsp_pd +,client22mcif_rd_wt +,client22mcif_rd_axid +,client22mcif_lat_fifo_depth +,client32mcif_rd_cdt_lat_fifo_pop +,client32mcif_rd_req_valid +,client32mcif_rd_req_ready +,client32mcif_rd_req_pd +,mcif2client3_rd_rsp_valid +,mcif2client3_rd_rsp_ready +,mcif2client3_rd_rsp_pd +,client32mcif_rd_wt +,client32mcif_rd_axid +,client32mcif_lat_fifo_depth +,client42mcif_rd_cdt_lat_fifo_pop +,client42mcif_rd_req_valid +,client42mcif_rd_req_ready +,client42mcif_rd_req_pd +,mcif2client4_rd_rsp_valid +,mcif2client4_rd_rsp_ready +,mcif2client4_rd_rsp_pd +,client42mcif_rd_wt +,client42mcif_rd_axid +,client42mcif_lat_fifo_depth +,client52mcif_rd_cdt_lat_fifo_pop +,client52mcif_rd_req_valid +,client52mcif_rd_req_ready +,client52mcif_rd_req_pd +,mcif2client5_rd_rsp_valid +,mcif2client5_rd_rsp_ready +,mcif2client5_rd_rsp_pd +,client52mcif_rd_wt +,client52mcif_rd_axid +,client52mcif_lat_fifo_depth +,client62mcif_rd_cdt_lat_fifo_pop +,client62mcif_rd_req_valid +,client62mcif_rd_req_ready +,client62mcif_rd_req_pd +,mcif2client6_rd_rsp_valid +,mcif2client6_rd_rsp_ready +,mcif2client6_rd_rsp_pd +,client62mcif_rd_wt +,client62mcif_rd_axid +,client62mcif_lat_fifo_depth + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,pwrbus_ram_pd + ,reg2dp_rd_os_cnt + ,mcif2noc_axi_ar_arvalid + ,mcif2noc_axi_ar_arready + ,mcif2noc_axi_ar_arid + ,mcif2noc_axi_ar_arlen + ,mcif2noc_axi_ar_araddr + ,noc2mcif_axi_r_rvalid + ,noc2mcif_axi_r_rready + ,noc2mcif_axi_r_rid + ,noc2mcif_axi_r_rlast + ,noc2mcif_axi_r_rdata +); +input nvdla_core_clk; +input nvdla_core_rstn; +//:my $k=7; +//:my $w = 64 +1 -1; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print("input client${i}2mcif_rd_req_valid;\n"); +//: print("output client${i}2mcif_rd_req_ready;\n"); +//: print qq( +//: input [32 +14:0] client${i}2mcif_rd_req_pd; +//: ); +//: print("output mcif2client${i}_rd_rsp_valid;\n"); +//: print("output [$w:0] mcif2client${i}_rd_rsp_pd;\n"); +//: print("input mcif2client${i}_rd_rsp_ready;\n"); +//: print("input [7:0] client${i}2mcif_rd_wt;\n"); +//: print("input [3:0] client${i}2mcif_rd_axid;\n"); +//: print("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: } +//:my $i; +//:for($i=0;$i<16;$i++) { +//: print qq( +//:wire [6:0] cq_rd${i}_pd; +//:wire cq_rd${i}_prdy; +//:wire cq_rd${i}_pvld; +//: ); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +input client02mcif_rd_cdt_lat_fifo_pop; +input client02mcif_rd_req_valid; +output client02mcif_rd_req_ready; + +input [32 +14:0] client02mcif_rd_req_pd; +output mcif2client0_rd_rsp_valid; +output [64:0] mcif2client0_rd_rsp_pd; +input mcif2client0_rd_rsp_ready; +input [7:0] client02mcif_rd_wt; +input [3:0] client02mcif_rd_axid; +input [7:0] client02mcif_lat_fifo_depth; +input client12mcif_rd_cdt_lat_fifo_pop; +input client12mcif_rd_req_valid; +output client12mcif_rd_req_ready; + +input [32 +14:0] client12mcif_rd_req_pd; +output mcif2client1_rd_rsp_valid; +output [64:0] mcif2client1_rd_rsp_pd; +input mcif2client1_rd_rsp_ready; +input [7:0] client12mcif_rd_wt; +input [3:0] client12mcif_rd_axid; +input [7:0] client12mcif_lat_fifo_depth; +input client22mcif_rd_cdt_lat_fifo_pop; +input client22mcif_rd_req_valid; +output client22mcif_rd_req_ready; + +input [32 +14:0] client22mcif_rd_req_pd; +output mcif2client2_rd_rsp_valid; +output [64:0] mcif2client2_rd_rsp_pd; +input mcif2client2_rd_rsp_ready; +input [7:0] client22mcif_rd_wt; +input [3:0] client22mcif_rd_axid; +input [7:0] client22mcif_lat_fifo_depth; +input client32mcif_rd_cdt_lat_fifo_pop; +input client32mcif_rd_req_valid; +output client32mcif_rd_req_ready; + +input [32 +14:0] client32mcif_rd_req_pd; +output mcif2client3_rd_rsp_valid; +output [64:0] mcif2client3_rd_rsp_pd; +input mcif2client3_rd_rsp_ready; +input [7:0] client32mcif_rd_wt; +input [3:0] client32mcif_rd_axid; +input [7:0] client32mcif_lat_fifo_depth; +input client42mcif_rd_cdt_lat_fifo_pop; +input client42mcif_rd_req_valid; +output client42mcif_rd_req_ready; + +input [32 +14:0] client42mcif_rd_req_pd; +output mcif2client4_rd_rsp_valid; +output [64:0] mcif2client4_rd_rsp_pd; +input mcif2client4_rd_rsp_ready; +input [7:0] client42mcif_rd_wt; +input [3:0] client42mcif_rd_axid; +input [7:0] client42mcif_lat_fifo_depth; +input client52mcif_rd_cdt_lat_fifo_pop; +input client52mcif_rd_req_valid; +output client52mcif_rd_req_ready; + +input [32 +14:0] client52mcif_rd_req_pd; +output mcif2client5_rd_rsp_valid; +output [64:0] mcif2client5_rd_rsp_pd; +input mcif2client5_rd_rsp_ready; +input [7:0] client52mcif_rd_wt; +input [3:0] client52mcif_rd_axid; +input [7:0] client52mcif_lat_fifo_depth; +input client62mcif_rd_cdt_lat_fifo_pop; +input client62mcif_rd_req_valid; +output client62mcif_rd_req_ready; + +input [32 +14:0] client62mcif_rd_req_pd; +output mcif2client6_rd_rsp_valid; +output [64:0] mcif2client6_rd_rsp_pd; +input mcif2client6_rd_rsp_ready; +input [7:0] client62mcif_rd_wt; +input [3:0] client62mcif_rd_axid; +input [7:0] client62mcif_lat_fifo_depth; + +wire [6:0] cq_rd0_pd; +wire cq_rd0_prdy; +wire cq_rd0_pvld; + +wire [6:0] cq_rd1_pd; +wire cq_rd1_prdy; +wire cq_rd1_pvld; + +wire [6:0] cq_rd2_pd; +wire cq_rd2_prdy; +wire cq_rd2_pvld; + +wire [6:0] cq_rd3_pd; +wire cq_rd3_prdy; +wire cq_rd3_pvld; + +wire [6:0] cq_rd4_pd; +wire cq_rd4_prdy; +wire cq_rd4_pvld; + +wire [6:0] cq_rd5_pd; +wire cq_rd5_prdy; +wire cq_rd5_pvld; + +wire [6:0] cq_rd6_pd; +wire cq_rd6_prdy; +wire cq_rd6_pvld; + +wire [6:0] cq_rd7_pd; +wire cq_rd7_prdy; +wire cq_rd7_pvld; + +wire [6:0] cq_rd8_pd; +wire cq_rd8_prdy; +wire cq_rd8_pvld; + +wire [6:0] cq_rd9_pd; +wire cq_rd9_prdy; +wire cq_rd9_pvld; + +wire [6:0] cq_rd10_pd; +wire cq_rd10_prdy; +wire cq_rd10_pvld; + +wire [6:0] cq_rd11_pd; +wire cq_rd11_prdy; +wire cq_rd11_pvld; + +wire [6:0] cq_rd12_pd; +wire cq_rd12_prdy; +wire cq_rd12_pvld; + +wire [6:0] cq_rd13_pd; +wire cq_rd13_prdy; +wire cq_rd13_pvld; + +wire [6:0] cq_rd14_pd; +wire cq_rd14_prdy; +wire cq_rd14_pvld; + +wire [6:0] cq_rd15_pd; +wire cq_rd15_prdy; +wire cq_rd15_pvld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [7:0] reg2dp_rd_os_cnt; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +input [31:0] pwrbus_ram_pd; +wire eg2ig_axi_vld; +wire [3:0] cq_wr_thread_id; +wire [6:0] cq_wr_pd; +wire cq_wr_pvld; +wire cq_wr_prdy; +NV_NVDLA_NOCIF_DRAM_READ_ig u_ig ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt) + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print (",.client${i}2mcif_rd_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print (",.client${i}2mcif_rd_req_valid(client${i}2mcif_rd_req_valid)\n"); +//: print (",.client${i}2mcif_rd_req_ready(client${i}2mcif_rd_req_ready)\n"); +//: print (",.client${i}2mcif_rd_req_pd(client${i}2mcif_rd_req_pd)\n"); +//: print (",.client${i}2mcif_rd_wt(client${i}2mcif_rd_wt)\n"); +//: print (",.client${i}2mcif_rd_axid(client${i}2mcif_rd_axid)\n"); +//: print (",.client${i}2mcif_lat_fifo_depth(client${i}2mcif_lat_fifo_depth)\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.client02mcif_rd_cdt_lat_fifo_pop(client02mcif_rd_cdt_lat_fifo_pop) +,.client02mcif_rd_req_valid(client02mcif_rd_req_valid) +,.client02mcif_rd_req_ready(client02mcif_rd_req_ready) +,.client02mcif_rd_req_pd(client02mcif_rd_req_pd) +,.client02mcif_rd_wt(client02mcif_rd_wt) +,.client02mcif_rd_axid(client02mcif_rd_axid) +,.client02mcif_lat_fifo_depth(client02mcif_lat_fifo_depth) +,.client12mcif_rd_cdt_lat_fifo_pop(client12mcif_rd_cdt_lat_fifo_pop) +,.client12mcif_rd_req_valid(client12mcif_rd_req_valid) +,.client12mcif_rd_req_ready(client12mcif_rd_req_ready) +,.client12mcif_rd_req_pd(client12mcif_rd_req_pd) +,.client12mcif_rd_wt(client12mcif_rd_wt) +,.client12mcif_rd_axid(client12mcif_rd_axid) +,.client12mcif_lat_fifo_depth(client12mcif_lat_fifo_depth) +,.client22mcif_rd_cdt_lat_fifo_pop(client22mcif_rd_cdt_lat_fifo_pop) +,.client22mcif_rd_req_valid(client22mcif_rd_req_valid) +,.client22mcif_rd_req_ready(client22mcif_rd_req_ready) +,.client22mcif_rd_req_pd(client22mcif_rd_req_pd) +,.client22mcif_rd_wt(client22mcif_rd_wt) +,.client22mcif_rd_axid(client22mcif_rd_axid) +,.client22mcif_lat_fifo_depth(client22mcif_lat_fifo_depth) +,.client32mcif_rd_cdt_lat_fifo_pop(client32mcif_rd_cdt_lat_fifo_pop) +,.client32mcif_rd_req_valid(client32mcif_rd_req_valid) +,.client32mcif_rd_req_ready(client32mcif_rd_req_ready) +,.client32mcif_rd_req_pd(client32mcif_rd_req_pd) +,.client32mcif_rd_wt(client32mcif_rd_wt) +,.client32mcif_rd_axid(client32mcif_rd_axid) +,.client32mcif_lat_fifo_depth(client32mcif_lat_fifo_depth) +,.client42mcif_rd_cdt_lat_fifo_pop(client42mcif_rd_cdt_lat_fifo_pop) +,.client42mcif_rd_req_valid(client42mcif_rd_req_valid) +,.client42mcif_rd_req_ready(client42mcif_rd_req_ready) +,.client42mcif_rd_req_pd(client42mcif_rd_req_pd) +,.client42mcif_rd_wt(client42mcif_rd_wt) +,.client42mcif_rd_axid(client42mcif_rd_axid) +,.client42mcif_lat_fifo_depth(client42mcif_lat_fifo_depth) +,.client52mcif_rd_cdt_lat_fifo_pop(client52mcif_rd_cdt_lat_fifo_pop) +,.client52mcif_rd_req_valid(client52mcif_rd_req_valid) +,.client52mcif_rd_req_ready(client52mcif_rd_req_ready) +,.client52mcif_rd_req_pd(client52mcif_rd_req_pd) +,.client52mcif_rd_wt(client52mcif_rd_wt) +,.client52mcif_rd_axid(client52mcif_rd_axid) +,.client52mcif_lat_fifo_depth(client52mcif_lat_fifo_depth) +,.client62mcif_rd_cdt_lat_fifo_pop(client62mcif_rd_cdt_lat_fifo_pop) +,.client62mcif_rd_req_valid(client62mcif_rd_req_valid) +,.client62mcif_rd_req_ready(client62mcif_rd_req_ready) +,.client62mcif_rd_req_pd(client62mcif_rd_req_pd) +,.client62mcif_rd_wt(client62mcif_rd_wt) +,.client62mcif_rd_axid(client62mcif_rd_axid) +,.client62mcif_lat_fifo_depth(client62mcif_lat_fifo_depth) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.cq_wr_pvld (cq_wr_pvld) //|> w + ,.cq_wr_prdy (cq_wr_prdy) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|> w + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr[32 -1:0]) //|> o +); +NV_NVDLA_NOCIF_DRAM_READ_eg u_eg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) +//:my $k=7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print(" ,.mcif2client${i}_rd_rsp_valid(mcif2client${i}_rd_rsp_valid)\n"); +//:print(" ,.mcif2client${i}_rd_rsp_ready(mcif2client${i}_rd_rsp_ready)\n"); +//:print(" ,.mcif2client${i}_rd_rsp_pd(mcif2client${i}_rd_rsp_pd)\n"); +//:} +//:my $i; +//:for($i=0;$i<7;$i++) { +//: print qq( +//: ,.cq_rd${i}_prdy(cq_rd${i}_prdy) +//: ,.cq_rd${i}_pvld(cq_rd${i}_pvld) +//: ,.cq_rd${i}_pd(cq_rd${i}_pd[6:0]) +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,.mcif2client0_rd_rsp_valid(mcif2client0_rd_rsp_valid) + ,.mcif2client0_rd_rsp_ready(mcif2client0_rd_rsp_ready) + ,.mcif2client0_rd_rsp_pd(mcif2client0_rd_rsp_pd) + ,.mcif2client1_rd_rsp_valid(mcif2client1_rd_rsp_valid) + ,.mcif2client1_rd_rsp_ready(mcif2client1_rd_rsp_ready) + ,.mcif2client1_rd_rsp_pd(mcif2client1_rd_rsp_pd) + ,.mcif2client2_rd_rsp_valid(mcif2client2_rd_rsp_valid) + ,.mcif2client2_rd_rsp_ready(mcif2client2_rd_rsp_ready) + ,.mcif2client2_rd_rsp_pd(mcif2client2_rd_rsp_pd) + ,.mcif2client3_rd_rsp_valid(mcif2client3_rd_rsp_valid) + ,.mcif2client3_rd_rsp_ready(mcif2client3_rd_rsp_ready) + ,.mcif2client3_rd_rsp_pd(mcif2client3_rd_rsp_pd) + ,.mcif2client4_rd_rsp_valid(mcif2client4_rd_rsp_valid) + ,.mcif2client4_rd_rsp_ready(mcif2client4_rd_rsp_ready) + ,.mcif2client4_rd_rsp_pd(mcif2client4_rd_rsp_pd) + ,.mcif2client5_rd_rsp_valid(mcif2client5_rd_rsp_valid) + ,.mcif2client5_rd_rsp_ready(mcif2client5_rd_rsp_ready) + ,.mcif2client5_rd_rsp_pd(mcif2client5_rd_rsp_pd) + ,.mcif2client6_rd_rsp_valid(mcif2client6_rd_rsp_valid) + ,.mcif2client6_rd_rsp_ready(mcif2client6_rd_rsp_ready) + ,.mcif2client6_rd_rsp_pd(mcif2client6_rd_rsp_pd) + +,.cq_rd0_prdy(cq_rd0_prdy) +,.cq_rd0_pvld(cq_rd0_pvld) +,.cq_rd0_pd(cq_rd0_pd[6:0]) + +,.cq_rd1_prdy(cq_rd1_prdy) +,.cq_rd1_pvld(cq_rd1_pvld) +,.cq_rd1_pd(cq_rd1_pd[6:0]) + +,.cq_rd2_prdy(cq_rd2_prdy) +,.cq_rd2_pvld(cq_rd2_pvld) +,.cq_rd2_pd(cq_rd2_pd[6:0]) + +,.cq_rd3_prdy(cq_rd3_prdy) +,.cq_rd3_pvld(cq_rd3_pvld) +,.cq_rd3_pd(cq_rd3_pd[6:0]) + +,.cq_rd4_prdy(cq_rd4_prdy) +,.cq_rd4_pvld(cq_rd4_pvld) +,.cq_rd4_pd(cq_rd4_pd[6:0]) + +,.cq_rd5_prdy(cq_rd5_prdy) +,.cq_rd5_pvld(cq_rd5_pvld) +,.cq_rd5_pd(cq_rd5_pd[6:0]) + +,.cq_rd6_prdy(cq_rd6_prdy) +,.cq_rd6_pvld(cq_rd6_pvld) +,.cq_rd6_pd(cq_rd6_pd[6:0]) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid[7:0]) //|< i + ,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i + ,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata[64 -1:0]) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w + ); +NV_NVDLA_NOCIF_DRAM_READ_cq u_cq ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cq_wr_prdy (cq_wr_prdy) //|> w + ,.cq_wr_pvld (cq_wr_pvld) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|< w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|< w +//:my $i; +//:for($i=0;$i<7;$i++) { +//: print qq( +//: ,.cq_rd${i}_prdy(cq_rd${i}_prdy) +//: ,.cq_rd${i}_pvld(cq_rd${i}_pvld) +//: ,.cq_rd${i}_pd(cq_rd${i}_pd[6:0]) +//: ); +//:} +//:my $i; +//:for($i=7;$i<10;$i++) { +//: print qq( +//: ,.cq_rd${i}_prdy(1'b1) +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.cq_rd0_prdy(cq_rd0_prdy) +,.cq_rd0_pvld(cq_rd0_pvld) +,.cq_rd0_pd(cq_rd0_pd[6:0]) + +,.cq_rd1_prdy(cq_rd1_prdy) +,.cq_rd1_pvld(cq_rd1_pvld) +,.cq_rd1_pd(cq_rd1_pd[6:0]) + +,.cq_rd2_prdy(cq_rd2_prdy) +,.cq_rd2_pvld(cq_rd2_pvld) +,.cq_rd2_pd(cq_rd2_pd[6:0]) + +,.cq_rd3_prdy(cq_rd3_prdy) +,.cq_rd3_pvld(cq_rd3_pvld) +,.cq_rd3_pd(cq_rd3_pd[6:0]) + +,.cq_rd4_prdy(cq_rd4_prdy) +,.cq_rd4_pvld(cq_rd4_pvld) +,.cq_rd4_pd(cq_rd4_pd[6:0]) + +,.cq_rd5_prdy(cq_rd5_prdy) +,.cq_rd5_pvld(cq_rd5_pvld) +,.cq_rd5_pd(cq_rd5_pd[6:0]) + +,.cq_rd6_prdy(cq_rd6_prdy) +,.cq_rd6_pvld(cq_rd6_pvld) +,.cq_rd6_pd(cq_rd6_pd[6:0]) + +,.cq_rd7_prdy(1'b1) + +,.cq_rd8_prdy(1'b1) + +,.cq_rd9_prdy(1'b1) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v.vcp new file mode 100644 index 0000000..14eeff3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v.vcp @@ -0,0 +1,170 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_read.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_read ( + nvdla_core_clk + ,nvdla_core_rstn +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print(",client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print(",client${i}2mcif_rd_req_valid\n"); +//: print(",client${i}2mcif_rd_req_ready\n"); +//: print(",client${i}2mcif_rd_req_pd\n"); +//: print(",mcif2client${i}_rd_rsp_valid\n"); +//: print(",mcif2client${i}_rd_rsp_ready\n"); +//: print(",mcif2client${i}_rd_rsp_pd\n"), +//: print(",client${i}2mcif_rd_wt\n"), +//: print(",client${i}2mcif_rd_axid\n"), +//: print(",client${i}2mcif_lat_fifo_depth\n"), +//: } + ,pwrbus_ram_pd + ,reg2dp_rd_os_cnt + ,mcif2noc_axi_ar_arvalid + ,mcif2noc_axi_ar_arready + ,mcif2noc_axi_ar_arid + ,mcif2noc_axi_ar_arlen + ,mcif2noc_axi_ar_araddr + ,noc2mcif_axi_r_rvalid + ,noc2mcif_axi_r_rready + ,noc2mcif_axi_r_rid + ,noc2mcif_axi_r_rlast + ,noc2mcif_axi_r_rdata +); +input nvdla_core_clk; +input nvdla_core_rstn; +//:my $k=7; +//:my $w = 64 +1 -1; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print("input client${i}2mcif_rd_req_valid;\n"); +//: print("output client${i}2mcif_rd_req_ready;\n"); +//: print qq( +//: input [32 +14:0] client${i}2mcif_rd_req_pd; +//: ); +//: print("output mcif2client${i}_rd_rsp_valid;\n"); +//: print("output [$w:0] mcif2client${i}_rd_rsp_pd;\n"); +//: print("input mcif2client${i}_rd_rsp_ready;\n"); +//: print("input [7:0] client${i}2mcif_rd_wt;\n"); +//: print("input [3:0] client${i}2mcif_rd_axid;\n"); +//: print("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: } +//:my $i; +//:for($i=0;$i<16;$i++) { +//: print qq( +//:wire [6:0] cq_rd${i}_pd; +//:wire cq_rd${i}_prdy; +//:wire cq_rd${i}_pvld; +//: ); +//:} +input [7:0] reg2dp_rd_os_cnt; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +input [31:0] pwrbus_ram_pd; +wire eg2ig_axi_vld; +wire [3:0] cq_wr_thread_id; +wire [6:0] cq_wr_pd; +wire cq_wr_pvld; +wire cq_wr_prdy; +NV_NVDLA_NOCIF_DRAM_READ_ig u_ig ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt) + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w +//:my $i; +//:my $k=7; +//:for ($i=0;$i<$k;$i++) { +//: print (",.client${i}2mcif_rd_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print (",.client${i}2mcif_rd_req_valid(client${i}2mcif_rd_req_valid)\n"); +//: print (",.client${i}2mcif_rd_req_ready(client${i}2mcif_rd_req_ready)\n"); +//: print (",.client${i}2mcif_rd_req_pd(client${i}2mcif_rd_req_pd)\n"); +//: print (",.client${i}2mcif_rd_wt(client${i}2mcif_rd_wt)\n"); +//: print (",.client${i}2mcif_rd_axid(client${i}2mcif_rd_axid)\n"); +//: print (",.client${i}2mcif_lat_fifo_depth(client${i}2mcif_lat_fifo_depth)\n"); +//:} + ,.cq_wr_pvld (cq_wr_pvld) //|> w + ,.cq_wr_prdy (cq_wr_prdy) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|> w + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr[32 -1:0]) //|> o +); +NV_NVDLA_NOCIF_DRAM_READ_eg u_eg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) +//:my $k=7; +//:my $i; +//:for($i=0;$i<$k;$i++) { +//:print(" ,.mcif2client${i}_rd_rsp_valid(mcif2client${i}_rd_rsp_valid)\n"); +//:print(" ,.mcif2client${i}_rd_rsp_ready(mcif2client${i}_rd_rsp_ready)\n"); +//:print(" ,.mcif2client${i}_rd_rsp_pd(mcif2client${i}_rd_rsp_pd)\n"); +//:} +//:my $i; +//:for($i=0;$i<7;$i++) { +//: print qq( +//: ,.cq_rd${i}_prdy(cq_rd${i}_prdy) +//: ,.cq_rd${i}_pvld(cq_rd${i}_pvld) +//: ,.cq_rd${i}_pd(cq_rd${i}_pd[6:0]) +//:); +//:} + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid[7:0]) //|< i + ,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i + ,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata[64 -1:0]) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w + ); +NV_NVDLA_NOCIF_DRAM_READ_cq u_cq ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cq_wr_prdy (cq_wr_prdy) //|> w + ,.cq_wr_pvld (cq_wr_pvld) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|< w + ,.cq_wr_pd (cq_wr_pd[6:0]) //|< w +//:my $i; +//:for($i=0;$i<7;$i++) { +//: print qq( +//: ,.cq_rd${i}_prdy(cq_rd${i}_prdy) +//: ,.cq_rd${i}_pvld(cq_rd${i}_pvld) +//: ,.cq_rd${i}_pd(cq_rd${i}_pd[6:0]) +//: ); +//:} +//:my $i; +//:for($i=7;$i<10;$i++) { +//: print qq( +//: ,.cq_rd${i}_prdy(1'b1) +//:); +//:} + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v new file mode 100644 index 0000000..6a98099 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v @@ -0,0 +1,292 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_write.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_write ( + nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,client${i}2mcif_wr_req_pd +//:,client${i}2mcif_wr_req_valid +//:,client${i}2mcif_wr_wt +//:,client${i}2mcif_wr_axid +//:,client${i}2mcif_wr_req_ready +//:,mcif2client${i}_wr_rsp_complete +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,client02mcif_wr_req_pd +,client02mcif_wr_req_valid +,client02mcif_wr_wt +,client02mcif_wr_axid +,client02mcif_wr_req_ready +,mcif2client0_wr_rsp_complete + +,client12mcif_wr_req_pd +,client12mcif_wr_req_valid +,client12mcif_wr_wt +,client12mcif_wr_axid +,client12mcif_wr_req_ready +,mcif2client1_wr_rsp_complete + +,client22mcif_wr_req_pd +,client22mcif_wr_req_valid +,client22mcif_wr_wt +,client22mcif_wr_axid +,client22mcif_wr_req_ready +,mcif2client2_wr_rsp_complete + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,reg2dp_wr_os_cnt + ,noc2mcif_axi_b_bid //|< i + ,noc2mcif_axi_b_bvalid //|< i + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,noc2mcif_axi_b_bready //|> o +); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:input [64 +1:0] client${i}2mcif_wr_req_pd; +//:input client${i}2mcif_wr_req_valid; +//:output client${i}2mcif_wr_req_ready; +//:input [7:0] client${i}2mcif_wr_wt; +//:input [3:0] client${i}2mcif_wr_axid; +//:output mcif2client${i}_wr_rsp_complete; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [64 +1:0] client02mcif_wr_req_pd; +input client02mcif_wr_req_valid; +output client02mcif_wr_req_ready; +input [7:0] client02mcif_wr_wt; +input [3:0] client02mcif_wr_axid; +output mcif2client0_wr_rsp_complete; + +input [64 +1:0] client12mcif_wr_req_pd; +input client12mcif_wr_req_valid; +output client12mcif_wr_req_ready; +input [7:0] client12mcif_wr_wt; +input [3:0] client12mcif_wr_axid; +output mcif2client1_wr_rsp_complete; + +input [64 +1:0] client22mcif_wr_req_pd; +input client22mcif_wr_req_valid; +output client22mcif_wr_req_ready; +input [7:0] client22mcif_wr_wt; +input [3:0] client22mcif_wr_axid; +output mcif2client2_wr_rsp_complete; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; + output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [(64/8)-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +input [7:0] reg2dp_wr_os_cnt; +input [31:0] pwrbus_ram_pd; +wire eg2ig_axi_vld; +wire [1:0] eg2ig_axi_len; +wire [3:0] cq_wr_thread_id; +wire [2:0] cq_wr_pd; +wire cq_wr_prdy; +wire cq_wr_pvld; +NV_NVDLA_NOCIF_DRAM_WRITE_ig u_ig ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.client${i}2mcif_wr_req_valid(client${i}2mcif_wr_req_valid) +//:,.client${i}2mcif_wr_req_ready(client${i}2mcif_wr_req_ready) +//:,.client${i}2mcif_wr_req_pd(client${i}2mcif_wr_req_pd) +//:,.client${i}2mcif_wr_wt(client${i}2mcif_wr_wt) +//:,.client${i}2mcif_wr_axid(client${i}2mcif_wr_axid) +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.client02mcif_wr_req_valid(client02mcif_wr_req_valid) +,.client02mcif_wr_req_ready(client02mcif_wr_req_ready) +,.client02mcif_wr_req_pd(client02mcif_wr_req_pd) +,.client02mcif_wr_wt(client02mcif_wr_wt) +,.client02mcif_wr_axid(client02mcif_wr_axid) + +,.client12mcif_wr_req_valid(client12mcif_wr_req_valid) +,.client12mcif_wr_req_ready(client12mcif_wr_req_ready) +,.client12mcif_wr_req_pd(client12mcif_wr_req_pd) +,.client12mcif_wr_wt(client12mcif_wr_wt) +,.client12mcif_wr_axid(client12mcif_wr_axid) + +,.client22mcif_wr_req_valid(client22mcif_wr_req_valid) +,.client22mcif_wr_req_ready(client22mcif_wr_req_ready) +,.client22mcif_wr_req_pd(client22mcif_wr_req_pd) +,.client22mcif_wr_wt(client22mcif_wr_wt) +,.client22mcif_wr_axid(client22mcif_wr_axid) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.cq_wr_pvld (cq_wr_pvld) //|> w + ,.cq_wr_prdy (cq_wr_prdy) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> w + ,.cq_wr_pd (cq_wr_pd[2:0]) //|> w + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr[32 -1:0]) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb[(64/8)-1:0]) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.eg2ig_axi_len (eg2ig_axi_len[1:0]) //|< w + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|< w +); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:wire [2:0] cq_rd${i}_pd; +//:wire cq_rd${i}_pvld; +//:wire cq_rd${i}_prdy; +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [2:0] cq_rd0_pd; +wire cq_rd0_pvld; +wire cq_rd0_prdy; + +wire [2:0] cq_rd1_pd; +wire cq_rd1_pvld; +wire cq_rd1_prdy; + +wire [2:0] cq_rd2_pd; +wire cq_rd2_pvld; +wire cq_rd2_prdy; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_NOCIF_DRAM_WRITE_eg u_eg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.mcif2client${i}_wr_rsp_complete(mcif2client${i}_wr_rsp_complete) +//:); +//:} +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.cq_rd${i}_pd (cq_rd${i}_pd) //|< w +//:,.cq_rd${i}_pvld (cq_rd${i}_pvld) //|< w +//:,.cq_rd${i}_prdy (cq_rd${i}_prdy) //|> w +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mcif2client0_wr_rsp_complete(mcif2client0_wr_rsp_complete) + +,.mcif2client1_wr_rsp_complete(mcif2client1_wr_rsp_complete) + +,.mcif2client2_wr_rsp_complete(mcif2client2_wr_rsp_complete) + +,.cq_rd0_pd (cq_rd0_pd) //|< w +,.cq_rd0_pvld (cq_rd0_pvld) //|< w +,.cq_rd0_prdy (cq_rd0_prdy) //|> w + +,.cq_rd1_pd (cq_rd1_pd) //|< w +,.cq_rd1_pvld (cq_rd1_pvld) //|< w +,.cq_rd1_prdy (cq_rd1_prdy) //|> w + +,.cq_rd2_pd (cq_rd2_pd) //|< w +,.cq_rd2_pvld (cq_rd2_pvld) //|< w +,.cq_rd2_prdy (cq_rd2_prdy) //|> w + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid) //|< i + ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready) //|> o + ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid[7:0]) //|< i + ,.eg2ig_axi_len (eg2ig_axi_len[1:0]) //|> w + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w + ); +NV_NVDLA_NOCIF_DRAM_WRITE_cq u_cq ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.cq_wr_prdy (cq_wr_prdy) //|> w + ,.cq_wr_pvld (cq_wr_pvld) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[2:0]) //|< w + ,.cq_wr_pd (cq_wr_pd[2:0]) //|< w +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.cq_rd${i}_pd (cq_rd${i}_pd) //|< w +//:,.cq_rd${i}_pvld (cq_rd${i}_pvld) //|< w +//:,.cq_rd${i}_prdy (cq_rd${i}_prdy) //|> w +//:); +//:} +//:my $i; +//:for($i=3;$i<5;$i++) { +//:print qq( +//:,.cq_rd${i}_prdy (1'b1) //|< w +//:); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.cq_rd0_pd (cq_rd0_pd) //|< w +,.cq_rd0_pvld (cq_rd0_pvld) //|< w +,.cq_rd0_prdy (cq_rd0_prdy) //|> w + +,.cq_rd1_pd (cq_rd1_pd) //|< w +,.cq_rd1_pvld (cq_rd1_pvld) //|< w +,.cq_rd1_prdy (cq_rd1_prdy) //|> w + +,.cq_rd2_pd (cq_rd2_pd) //|< w +,.cq_rd2_pvld (cq_rd2_pvld) //|< w +,.cq_rd2_prdy (cq_rd2_prdy) //|> w + +,.cq_rd3_prdy (1'b1) //|< w + +,.cq_rd4_prdy (1'b1) //|< w + +//| eperl: generated_end (DO NOT EDIT ABOVE) +); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v.vcp new file mode 100644 index 0000000..3c8a3a1 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v.vcp @@ -0,0 +1,168 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_DRAM_write.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_DRAM_write ( + nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,client${i}2mcif_wr_req_pd +//:,client${i}2mcif_wr_req_valid +//:,client${i}2mcif_wr_wt +//:,client${i}2mcif_wr_axid +//:,client${i}2mcif_wr_req_ready +//:,mcif2client${i}_wr_rsp_complete +//:); +//:} + ,reg2dp_wr_os_cnt + ,noc2mcif_axi_b_bid //|< i + ,noc2mcif_axi_b_bvalid //|< i + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,noc2mcif_axi_b_bready //|> o +); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:input [64 +1:0] client${i}2mcif_wr_req_pd; +//:input client${i}2mcif_wr_req_valid; +//:output client${i}2mcif_wr_req_ready; +//:input [7:0] client${i}2mcif_wr_wt; +//:input [3:0] client${i}2mcif_wr_axid; +//:output mcif2client${i}_wr_rsp_complete; +//:); +//:} +input nvdla_core_clk; +input nvdla_core_rstn; + output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [(64/8)-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +input [7:0] reg2dp_wr_os_cnt; +input [31:0] pwrbus_ram_pd; +wire eg2ig_axi_vld; +wire [1:0] eg2ig_axi_len; +wire [3:0] cq_wr_thread_id; +wire [2:0] cq_wr_pd; +wire cq_wr_prdy; +wire cq_wr_pvld; +NV_NVDLA_NOCIF_DRAM_WRITE_ig u_ig ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt) +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.client${i}2mcif_wr_req_valid(client${i}2mcif_wr_req_valid) +//:,.client${i}2mcif_wr_req_ready(client${i}2mcif_wr_req_ready) +//:,.client${i}2mcif_wr_req_pd(client${i}2mcif_wr_req_pd) +//:,.client${i}2mcif_wr_wt(client${i}2mcif_wr_wt) +//:,.client${i}2mcif_wr_axid(client${i}2mcif_wr_axid) +//:); +//:} + ,.cq_wr_pvld (cq_wr_pvld) //|> w + ,.cq_wr_prdy (cq_wr_prdy) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[3:0]) //|> w + ,.cq_wr_pd (cq_wr_pd[2:0]) //|> w + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr[32 -1:0]) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb[(64/8)-1:0]) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.eg2ig_axi_len (eg2ig_axi_len[1:0]) //|< w + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|< w +); +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:wire [2:0] cq_rd${i}_pd; +//:wire cq_rd${i}_pvld; +//:wire cq_rd${i}_prdy; +//:); +//:} +NV_NVDLA_NOCIF_DRAM_WRITE_eg u_eg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.mcif2client${i}_wr_rsp_complete(mcif2client${i}_wr_rsp_complete) +//:); +//:} +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.cq_rd${i}_pd (cq_rd${i}_pd) //|< w +//:,.cq_rd${i}_pvld (cq_rd${i}_pvld) //|< w +//:,.cq_rd${i}_prdy (cq_rd${i}_prdy) //|> w +//:); +//:} + ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid) //|< i + ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready) //|> o + ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid[7:0]) //|< i + ,.eg2ig_axi_len (eg2ig_axi_len[1:0]) //|> w + ,.eg2ig_axi_vld (eg2ig_axi_vld) //|> w + ); +NV_NVDLA_NOCIF_DRAM_WRITE_cq u_cq ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.cq_wr_prdy (cq_wr_prdy) //|> w + ,.cq_wr_pvld (cq_wr_pvld) //|< w + ,.cq_wr_thread_id (cq_wr_thread_id[2:0]) //|< w + ,.cq_wr_pd (cq_wr_pd[2:0]) //|< w +//:my $i; +//:for($i=0;$i<3;$i++) { +//:print qq( +//:,.cq_rd${i}_pd (cq_rd${i}_pd) //|< w +//:,.cq_rd${i}_pvld (cq_rd${i}_pvld) //|< w +//:,.cq_rd${i}_prdy (cq_rd${i}_prdy) //|> w +//:); +//:} +//:my $i; +//:for($i=3;$i<5;$i++) { +//:print qq( +//:,.cq_rd${i}_prdy (1'b1) //|< w +//:); +//:} +); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v new file mode 100644 index 0000000..cc6e1d9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v @@ -0,0 +1,568 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_dram.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_dram ( + nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd +//: my $k = 7; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print(" ,client${i}2mcif_rd_req_valid\n"); +//: print(" ,client${i}2mcif_rd_req_pd\n"); +//: print(" ,client${i}2mcif_rd_req_ready\n"); +//: print(" ,client${i}2mcif_rd_axid\n"); +//: print(" ,mcif2client${i}_rd_rsp_valid\n"); +//: print(" ,mcif2client${i}_rd_rsp_ready\n"); +//: print(" ,mcif2client${i}_rd_rsp_pd\n"); +//: print(" ,client${i}2mcif_lat_fifo_depth\n"); +//: } +//: my $k = 3; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_wr_req_pd\n"); +//: print(" ,client${i}2mcif_wr_req_valid\n"); +//: print(" ,client${i}2mcif_wr_req_ready\n"); +//: print(" ,client${i}2mcif_wr_axid\n"); +//: print(" ,mcif2client${i}_wr_rsp_complete\n"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,client02mcif_rd_cdt_lat_fifo_pop + ,client02mcif_rd_req_valid + ,client02mcif_rd_req_pd + ,client02mcif_rd_req_ready + ,client02mcif_rd_axid + ,mcif2client0_rd_rsp_valid + ,mcif2client0_rd_rsp_ready + ,mcif2client0_rd_rsp_pd + ,client02mcif_lat_fifo_depth + ,client12mcif_rd_cdt_lat_fifo_pop + ,client12mcif_rd_req_valid + ,client12mcif_rd_req_pd + ,client12mcif_rd_req_ready + ,client12mcif_rd_axid + ,mcif2client1_rd_rsp_valid + ,mcif2client1_rd_rsp_ready + ,mcif2client1_rd_rsp_pd + ,client12mcif_lat_fifo_depth + ,client22mcif_rd_cdt_lat_fifo_pop + ,client22mcif_rd_req_valid + ,client22mcif_rd_req_pd + ,client22mcif_rd_req_ready + ,client22mcif_rd_axid + ,mcif2client2_rd_rsp_valid + ,mcif2client2_rd_rsp_ready + ,mcif2client2_rd_rsp_pd + ,client22mcif_lat_fifo_depth + ,client32mcif_rd_cdt_lat_fifo_pop + ,client32mcif_rd_req_valid + ,client32mcif_rd_req_pd + ,client32mcif_rd_req_ready + ,client32mcif_rd_axid + ,mcif2client3_rd_rsp_valid + ,mcif2client3_rd_rsp_ready + ,mcif2client3_rd_rsp_pd + ,client32mcif_lat_fifo_depth + ,client42mcif_rd_cdt_lat_fifo_pop + ,client42mcif_rd_req_valid + ,client42mcif_rd_req_pd + ,client42mcif_rd_req_ready + ,client42mcif_rd_axid + ,mcif2client4_rd_rsp_valid + ,mcif2client4_rd_rsp_ready + ,mcif2client4_rd_rsp_pd + ,client42mcif_lat_fifo_depth + ,client52mcif_rd_cdt_lat_fifo_pop + ,client52mcif_rd_req_valid + ,client52mcif_rd_req_pd + ,client52mcif_rd_req_ready + ,client52mcif_rd_axid + ,mcif2client5_rd_rsp_valid + ,mcif2client5_rd_rsp_ready + ,mcif2client5_rd_rsp_pd + ,client52mcif_lat_fifo_depth + ,client62mcif_rd_cdt_lat_fifo_pop + ,client62mcif_rd_req_valid + ,client62mcif_rd_req_pd + ,client62mcif_rd_req_ready + ,client62mcif_rd_axid + ,mcif2client6_rd_rsp_valid + ,mcif2client6_rd_rsp_ready + ,mcif2client6_rd_rsp_pd + ,client62mcif_lat_fifo_depth + ,client02mcif_wr_req_pd + ,client02mcif_wr_req_valid + ,client02mcif_wr_req_ready + ,client02mcif_wr_axid + ,mcif2client0_wr_rsp_complete + ,client12mcif_wr_req_pd + ,client12mcif_wr_req_valid + ,client12mcif_wr_req_ready + ,client12mcif_wr_axid + ,mcif2client1_wr_rsp_complete + ,client22mcif_wr_req_pd + ,client22mcif_wr_req_valid + ,client22mcif_wr_req_ready + ,client22mcif_wr_axid + ,mcif2client2_wr_rsp_complete + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,csb2mcif_req_pd //|< i + ,csb2mcif_req_pvld //|< i + ,csb2mcif_req_prdy //|> o + ,noc2mcif_axi_b_bid //|< i + ,noc2mcif_axi_b_bvalid //|< i + ,noc2mcif_axi_r_rdata //|< i + ,noc2mcif_axi_r_rid //|< i + ,noc2mcif_axi_r_rlast //|< i + ,noc2mcif_axi_r_rvalid //|< i + ,mcif2noc_axi_ar_arready //|< i + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,mcif2csb_resp_pd //|> o + ,mcif2csb_resp_valid //|> o + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,noc2mcif_axi_b_bready //|> o + ,noc2mcif_axi_r_rready //|> o +); +//:my $k = 7; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print ("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print ("input [3:0] client${i}2mcif_rd_axid;\n"); +//: print("input client${i}2mcif_rd_req_valid;\n"); +//: print qq( +//: input [32 +14:0] client${i}2mcif_rd_req_pd; +//: ); +//: print("output client${i}2mcif_rd_req_ready;\n"); +//: print("output mcif2client${i}_rd_rsp_valid;\n"); +//: print("input mcif2client${i}_rd_rsp_ready;\n"); +//: print qq( +//: output [64 +1 -1:0] mcif2client${i}_rd_rsp_pd; +//: ); +//: print("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: } +//:my $k = 3; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print qq( +//: input [64 +1:0] client${i}2mcif_wr_req_pd; +//: ); +//: print ("input [3:0] client${i}2mcif_wr_axid;\n"); +//: print("input client${i}2mcif_wr_req_valid;\n"); +//: print("output client${i}2mcif_wr_req_ready;\n"); +//: print("output mcif2client${i}_wr_rsp_complete;\n"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input client02mcif_rd_cdt_lat_fifo_pop; +input [3:0] client02mcif_rd_axid; +input client02mcif_rd_req_valid; + +input [32 +14:0] client02mcif_rd_req_pd; +output client02mcif_rd_req_ready; +output mcif2client0_rd_rsp_valid; +input mcif2client0_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client0_rd_rsp_pd; +input [7:0] client02mcif_lat_fifo_depth; +input client12mcif_rd_cdt_lat_fifo_pop; +input [3:0] client12mcif_rd_axid; +input client12mcif_rd_req_valid; + +input [32 +14:0] client12mcif_rd_req_pd; +output client12mcif_rd_req_ready; +output mcif2client1_rd_rsp_valid; +input mcif2client1_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client1_rd_rsp_pd; +input [7:0] client12mcif_lat_fifo_depth; +input client22mcif_rd_cdt_lat_fifo_pop; +input [3:0] client22mcif_rd_axid; +input client22mcif_rd_req_valid; + +input [32 +14:0] client22mcif_rd_req_pd; +output client22mcif_rd_req_ready; +output mcif2client2_rd_rsp_valid; +input mcif2client2_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client2_rd_rsp_pd; +input [7:0] client22mcif_lat_fifo_depth; +input client32mcif_rd_cdt_lat_fifo_pop; +input [3:0] client32mcif_rd_axid; +input client32mcif_rd_req_valid; + +input [32 +14:0] client32mcif_rd_req_pd; +output client32mcif_rd_req_ready; +output mcif2client3_rd_rsp_valid; +input mcif2client3_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client3_rd_rsp_pd; +input [7:0] client32mcif_lat_fifo_depth; +input client42mcif_rd_cdt_lat_fifo_pop; +input [3:0] client42mcif_rd_axid; +input client42mcif_rd_req_valid; + +input [32 +14:0] client42mcif_rd_req_pd; +output client42mcif_rd_req_ready; +output mcif2client4_rd_rsp_valid; +input mcif2client4_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client4_rd_rsp_pd; +input [7:0] client42mcif_lat_fifo_depth; +input client52mcif_rd_cdt_lat_fifo_pop; +input [3:0] client52mcif_rd_axid; +input client52mcif_rd_req_valid; + +input [32 +14:0] client52mcif_rd_req_pd; +output client52mcif_rd_req_ready; +output mcif2client5_rd_rsp_valid; +input mcif2client5_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client5_rd_rsp_pd; +input [7:0] client52mcif_lat_fifo_depth; +input client62mcif_rd_cdt_lat_fifo_pop; +input [3:0] client62mcif_rd_axid; +input client62mcif_rd_req_valid; + +input [32 +14:0] client62mcif_rd_req_pd; +output client62mcif_rd_req_ready; +output mcif2client6_rd_rsp_valid; +input mcif2client6_rd_rsp_ready; + +output [64 +1 -1:0] mcif2client6_rd_rsp_pd; +input [7:0] client62mcif_lat_fifo_depth; + +input [64 +1:0] client02mcif_wr_req_pd; +input [3:0] client02mcif_wr_axid; +input client02mcif_wr_req_valid; +output client02mcif_wr_req_ready; +output mcif2client0_wr_rsp_complete; + +input [64 +1:0] client12mcif_wr_req_pd; +input [3:0] client12mcif_wr_axid; +input client12mcif_wr_req_valid; +output client12mcif_wr_req_ready; +output mcif2client1_wr_rsp_complete; + +input [64 +1:0] client22mcif_wr_req_pd; +input [3:0] client22mcif_wr_axid; +input client22mcif_wr_req_valid; +output client22mcif_wr_req_ready; +output mcif2client2_wr_rsp_complete; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input csb2mcif_req_pvld; /* data valid */ +output csb2mcif_req_prdy; /* data return handshake */ +input [62:0] csb2mcif_req_pd; +output mcif2csb_resp_valid; /* data valid */ +output [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//: my @dma_name = ("bdma","cdma_dat","cdma_wt","cdp","pdp","rbk","sdp","sdp_b","sdp_e","sdp_n","na","na","na","na","na","na"); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: wire [7:0] reg2dp_rd_weight_$dma_name[$i]; +//: wire [7:0] client${nindex}2mcif_rd_wt = reg2dp_rd_weight_$dma_name[$i]; +//:); +//:$nindex++; +//:} +//:else { +//: if ($dma_name[$i] ne "na") { +//: print qq(wire [7:0] reg2dp_rd_weight_$dma_name[$i];); +//: } +//:} +//:} +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1,1, 1, 0, 0,0,0,0,0,0); +//: my @dma_name=("bdma","sdp","cdp","pdp","rbk","na","na","na","na","na","na","na","na","na","na","na"); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: wire [7:0] reg2dp_wr_weight_$dma_name[$i]; +//: wire [7:0] client${nindex}2mcif_wr_wt = reg2dp_wr_weight_$dma_name[$i]; +//:); +//:$nindex++; +//:} +//:else { +//: if ($dma_name[$i] ne "na") { +//: print qq(wire [7:0] reg2dp_wr_weight_$dma_name[$i];); +//: } +//:} +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [7:0] reg2dp_rd_weight_bdma; +wire [7:0] reg2dp_rd_weight_cdma_dat; +wire [7:0] client02mcif_rd_wt = reg2dp_rd_weight_cdma_dat; + +wire [7:0] reg2dp_rd_weight_cdma_wt; +wire [7:0] client12mcif_rd_wt = reg2dp_rd_weight_cdma_wt; + +wire [7:0] reg2dp_rd_weight_cdp; +wire [7:0] client22mcif_rd_wt = reg2dp_rd_weight_cdp; + +wire [7:0] reg2dp_rd_weight_pdp; +wire [7:0] client32mcif_rd_wt = reg2dp_rd_weight_pdp; +wire [7:0] reg2dp_rd_weight_rbk; +wire [7:0] reg2dp_rd_weight_sdp; +wire [7:0] client42mcif_rd_wt = reg2dp_rd_weight_sdp; + +wire [7:0] reg2dp_rd_weight_sdp_b; +wire [7:0] client52mcif_rd_wt = reg2dp_rd_weight_sdp_b; +wire [7:0] reg2dp_rd_weight_sdp_e; +wire [7:0] reg2dp_rd_weight_sdp_n; +wire [7:0] client62mcif_rd_wt = reg2dp_rd_weight_sdp_n; +wire [7:0] reg2dp_wr_weight_bdma; +wire [7:0] reg2dp_wr_weight_sdp; +wire [7:0] client02mcif_wr_wt = reg2dp_wr_weight_sdp; + +wire [7:0] reg2dp_wr_weight_cdp; +wire [7:0] client12mcif_wr_wt = reg2dp_wr_weight_cdp; + +wire [7:0] reg2dp_wr_weight_pdp; +wire [7:0] client22mcif_wr_wt = reg2dp_wr_weight_pdp; +wire [7:0] reg2dp_wr_weight_rbk; +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [7:0] reg2dp_rd_os_cnt; +wire [7:0] reg2dp_wr_os_cnt; +NV_NVDLA_MCIF_csb u_csb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< i + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> o + ,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< i + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> o + ,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> o + ,.dp2reg_idle ({1{1'b1}}) //|< ? + ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|> w + ,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma[7:0]) //|> w + ,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0]) //|> w + ,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0]) //|> w + ,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp[7:0]) //|> w + ,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp[7:0]) //|> w + ,.reg2dp_rd_weight_rbk (reg2dp_rd_weight_rbk[7:0]) //|> w + ,.reg2dp_rd_weight_rsv_0 () //|> ? + ,.reg2dp_rd_weight_rsv_1 () //|> ? + ,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp[7:0]) //|> w + ,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0]) //|> w + ,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0]) //|> w + ,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0]) //|> w + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|> w + ,.reg2dp_wr_weight_bdma (reg2dp_wr_weight_bdma[7:0]) //|> w + ,.reg2dp_wr_weight_cdp (reg2dp_wr_weight_cdp[7:0]) //|> w + ,.reg2dp_wr_weight_pdp (reg2dp_wr_weight_pdp[7:0]) //|> w + ,.reg2dp_wr_weight_rbk (reg2dp_wr_weight_rbk[7:0]) //|> w + ,.reg2dp_wr_weight_rsv_0 () //|> ? + ,.reg2dp_wr_weight_rsv_1 () //|> ? + ,.reg2dp_wr_weight_rsv_2 () //|> ? + ,.reg2dp_wr_weight_sdp (reg2dp_wr_weight_sdp[7:0]) //|> w + ); +NV_NVDLA_NOCIF_DRAM_read u_read ( + .reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd) +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print(",.client${i}2mcif_rd_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print(",.client${i}2mcif_rd_req_valid (client${i}2mcif_rd_req_valid)\n"); +//: print(",.client${i}2mcif_rd_req_ready (client${i}2mcif_rd_req_ready)\n"); +//: print(",.client${i}2mcif_rd_req_pd (client${i}2mcif_rd_req_pd)\n"); +//: print(",.mcif2client${i}_rd_rsp_valid (mcif2client${i}_rd_rsp_valid)\n"); +//: print(",.mcif2client${i}_rd_rsp_ready (mcif2client${i}_rd_rsp_ready)\n"); +//: print(",.mcif2client${i}_rd_rsp_pd (mcif2client${i}_rd_rsp_pd)\n"), +//: print(",.client${i}2mcif_rd_wt (client${i}2mcif_rd_wt)\n"), +//: print(",.client${i}2mcif_rd_axid (client${i}2mcif_rd_axid)\n"), +//: print(",.client${i}2mcif_lat_fifo_depth (client${i}2mcif_lat_fifo_depth)\n"), +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.client02mcif_rd_cdt_lat_fifo_pop(client02mcif_rd_cdt_lat_fifo_pop) +,.client02mcif_rd_req_valid (client02mcif_rd_req_valid) +,.client02mcif_rd_req_ready (client02mcif_rd_req_ready) +,.client02mcif_rd_req_pd (client02mcif_rd_req_pd) +,.mcif2client0_rd_rsp_valid (mcif2client0_rd_rsp_valid) +,.mcif2client0_rd_rsp_ready (mcif2client0_rd_rsp_ready) +,.mcif2client0_rd_rsp_pd (mcif2client0_rd_rsp_pd) +,.client02mcif_rd_wt (client02mcif_rd_wt) +,.client02mcif_rd_axid (client02mcif_rd_axid) +,.client02mcif_lat_fifo_depth (client02mcif_lat_fifo_depth) +,.client12mcif_rd_cdt_lat_fifo_pop(client12mcif_rd_cdt_lat_fifo_pop) +,.client12mcif_rd_req_valid (client12mcif_rd_req_valid) +,.client12mcif_rd_req_ready (client12mcif_rd_req_ready) +,.client12mcif_rd_req_pd (client12mcif_rd_req_pd) +,.mcif2client1_rd_rsp_valid (mcif2client1_rd_rsp_valid) +,.mcif2client1_rd_rsp_ready (mcif2client1_rd_rsp_ready) +,.mcif2client1_rd_rsp_pd (mcif2client1_rd_rsp_pd) +,.client12mcif_rd_wt (client12mcif_rd_wt) +,.client12mcif_rd_axid (client12mcif_rd_axid) +,.client12mcif_lat_fifo_depth (client12mcif_lat_fifo_depth) +,.client22mcif_rd_cdt_lat_fifo_pop(client22mcif_rd_cdt_lat_fifo_pop) +,.client22mcif_rd_req_valid (client22mcif_rd_req_valid) +,.client22mcif_rd_req_ready (client22mcif_rd_req_ready) +,.client22mcif_rd_req_pd (client22mcif_rd_req_pd) +,.mcif2client2_rd_rsp_valid (mcif2client2_rd_rsp_valid) +,.mcif2client2_rd_rsp_ready (mcif2client2_rd_rsp_ready) +,.mcif2client2_rd_rsp_pd (mcif2client2_rd_rsp_pd) +,.client22mcif_rd_wt (client22mcif_rd_wt) +,.client22mcif_rd_axid (client22mcif_rd_axid) +,.client22mcif_lat_fifo_depth (client22mcif_lat_fifo_depth) +,.client32mcif_rd_cdt_lat_fifo_pop(client32mcif_rd_cdt_lat_fifo_pop) +,.client32mcif_rd_req_valid (client32mcif_rd_req_valid) +,.client32mcif_rd_req_ready (client32mcif_rd_req_ready) +,.client32mcif_rd_req_pd (client32mcif_rd_req_pd) +,.mcif2client3_rd_rsp_valid (mcif2client3_rd_rsp_valid) +,.mcif2client3_rd_rsp_ready (mcif2client3_rd_rsp_ready) +,.mcif2client3_rd_rsp_pd (mcif2client3_rd_rsp_pd) +,.client32mcif_rd_wt (client32mcif_rd_wt) +,.client32mcif_rd_axid (client32mcif_rd_axid) +,.client32mcif_lat_fifo_depth (client32mcif_lat_fifo_depth) +,.client42mcif_rd_cdt_lat_fifo_pop(client42mcif_rd_cdt_lat_fifo_pop) +,.client42mcif_rd_req_valid (client42mcif_rd_req_valid) +,.client42mcif_rd_req_ready (client42mcif_rd_req_ready) +,.client42mcif_rd_req_pd (client42mcif_rd_req_pd) +,.mcif2client4_rd_rsp_valid (mcif2client4_rd_rsp_valid) +,.mcif2client4_rd_rsp_ready (mcif2client4_rd_rsp_ready) +,.mcif2client4_rd_rsp_pd (mcif2client4_rd_rsp_pd) +,.client42mcif_rd_wt (client42mcif_rd_wt) +,.client42mcif_rd_axid (client42mcif_rd_axid) +,.client42mcif_lat_fifo_depth (client42mcif_lat_fifo_depth) +,.client52mcif_rd_cdt_lat_fifo_pop(client52mcif_rd_cdt_lat_fifo_pop) +,.client52mcif_rd_req_valid (client52mcif_rd_req_valid) +,.client52mcif_rd_req_ready (client52mcif_rd_req_ready) +,.client52mcif_rd_req_pd (client52mcif_rd_req_pd) +,.mcif2client5_rd_rsp_valid (mcif2client5_rd_rsp_valid) +,.mcif2client5_rd_rsp_ready (mcif2client5_rd_rsp_ready) +,.mcif2client5_rd_rsp_pd (mcif2client5_rd_rsp_pd) +,.client52mcif_rd_wt (client52mcif_rd_wt) +,.client52mcif_rd_axid (client52mcif_rd_axid) +,.client52mcif_lat_fifo_depth (client52mcif_lat_fifo_depth) +,.client62mcif_rd_cdt_lat_fifo_pop(client62mcif_rd_cdt_lat_fifo_pop) +,.client62mcif_rd_req_valid (client62mcif_rd_req_valid) +,.client62mcif_rd_req_ready (client62mcif_rd_req_ready) +,.client62mcif_rd_req_pd (client62mcif_rd_req_pd) +,.mcif2client6_rd_rsp_valid (mcif2client6_rd_rsp_valid) +,.mcif2client6_rd_rsp_ready (mcif2client6_rd_rsp_ready) +,.mcif2client6_rd_rsp_pd (mcif2client6_rd_rsp_pd) +,.client62mcif_rd_wt (client62mcif_rd_wt) +,.client62mcif_rd_axid (client62mcif_rd_axid) +,.client62mcif_lat_fifo_depth (client62mcif_lat_fifo_depth) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr) //|> o + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid) //|< i + ,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i + ,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata) //|< i +); +NV_NVDLA_NOCIF_DRAM_write u_write ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt) +//:my $k=3; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print(",.client${i}2mcif_wr_req_valid(client${i}2mcif_wr_req_valid)\n"); +//: print(",.client${i}2mcif_wr_req_ready(client${i}2mcif_wr_req_ready)\n"); +//: print(",.client${i}2mcif_wr_req_pd(client${i}2mcif_wr_req_pd)\n"); +//: print(",.client${i}2mcif_wr_wt(client${i}2mcif_wr_wt)\n"); +//: print(",.client${i}2mcif_wr_axid(client${i}2mcif_wr_axid)\n"); +//: print(",.mcif2client${i}_wr_rsp_complete(mcif2client${i}_wr_rsp_complete)\n"); +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.client02mcif_wr_req_valid(client02mcif_wr_req_valid) +,.client02mcif_wr_req_ready(client02mcif_wr_req_ready) +,.client02mcif_wr_req_pd(client02mcif_wr_req_pd) +,.client02mcif_wr_wt(client02mcif_wr_wt) +,.client02mcif_wr_axid(client02mcif_wr_axid) +,.mcif2client0_wr_rsp_complete(mcif2client0_wr_rsp_complete) +,.client12mcif_wr_req_valid(client12mcif_wr_req_valid) +,.client12mcif_wr_req_ready(client12mcif_wr_req_ready) +,.client12mcif_wr_req_pd(client12mcif_wr_req_pd) +,.client12mcif_wr_wt(client12mcif_wr_wt) +,.client12mcif_wr_axid(client12mcif_wr_axid) +,.mcif2client1_wr_rsp_complete(mcif2client1_wr_rsp_complete) +,.client22mcif_wr_req_valid(client22mcif_wr_req_valid) +,.client22mcif_wr_req_ready(client22mcif_wr_req_ready) +,.client22mcif_wr_req_pd(client22mcif_wr_req_pd) +,.client22mcif_wr_wt(client22mcif_wr_wt) +,.client22mcif_wr_axid(client22mcif_wr_axid) +,.mcif2client2_wr_rsp_complete(mcif2client2_wr_rsp_complete) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid) //|< i + ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready) //|> o + ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid) //|< i +); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v.vcp new file mode 100644 index 0000000..fffa23f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v.vcp @@ -0,0 +1,262 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_NOCIF_dram.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +module NV_NVDLA_NOCIF_dram ( + nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd +//: my $k = 7; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print(" ,client${i}2mcif_rd_req_valid\n"); +//: print(" ,client${i}2mcif_rd_req_pd\n"); +//: print(" ,client${i}2mcif_rd_req_ready\n"); +//: print(" ,client${i}2mcif_rd_axid\n"); +//: print(" ,mcif2client${i}_rd_rsp_valid\n"); +//: print(" ,mcif2client${i}_rd_rsp_ready\n"); +//: print(" ,mcif2client${i}_rd_rsp_pd\n"); +//: print(" ,client${i}2mcif_lat_fifo_depth\n"); +//: } +//: my $k = 3; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_wr_req_pd\n"); +//: print(" ,client${i}2mcif_wr_req_valid\n"); +//: print(" ,client${i}2mcif_wr_req_ready\n"); +//: print(" ,client${i}2mcif_wr_axid\n"); +//: print(" ,mcif2client${i}_wr_rsp_complete\n"); +//: } + ,csb2mcif_req_pd //|< i + ,csb2mcif_req_pvld //|< i + ,csb2mcif_req_prdy //|> o + ,noc2mcif_axi_b_bid //|< i + ,noc2mcif_axi_b_bvalid //|< i + ,noc2mcif_axi_r_rdata //|< i + ,noc2mcif_axi_r_rid //|< i + ,noc2mcif_axi_r_rlast //|< i + ,noc2mcif_axi_r_rvalid //|< i + ,mcif2noc_axi_ar_arready //|< i + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,mcif2csb_resp_pd //|> o + ,mcif2csb_resp_valid //|> o + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,noc2mcif_axi_b_bready //|> o + ,noc2mcif_axi_r_rready //|> o +); +//:my $k = 7; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print ("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print ("input [3:0] client${i}2mcif_rd_axid;\n"); +//: print("input client${i}2mcif_rd_req_valid;\n"); +//: print qq( +//: input [32 +14:0] client${i}2mcif_rd_req_pd; +//: ); +//: print("output client${i}2mcif_rd_req_ready;\n"); +//: print("output mcif2client${i}_rd_rsp_valid;\n"); +//: print("input mcif2client${i}_rd_rsp_ready;\n"); +//: print qq( +//: output [64 +1 -1:0] mcif2client${i}_rd_rsp_pd; +//: ); +//: print("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: } +//:my $k = 3; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print qq( +//: input [64 +1:0] client${i}2mcif_wr_req_pd; +//: ); +//: print ("input [3:0] client${i}2mcif_wr_axid;\n"); +//: print("input client${i}2mcif_wr_req_valid;\n"); +//: print("output client${i}2mcif_wr_req_ready;\n"); +//: print("output mcif2client${i}_wr_rsp_complete;\n"); +//: } +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input csb2mcif_req_pvld; /* data valid */ +output csb2mcif_req_prdy; /* data return handshake */ +input [62:0] csb2mcif_req_pd; +output mcif2csb_resp_valid; /* data valid */ +output [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//: my @dma_name = ("bdma","cdma_dat","cdma_wt","cdp","pdp","rbk","sdp","sdp_b","sdp_e","sdp_n","na","na","na","na","na","na"); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: wire [7:0] reg2dp_rd_weight_$dma_name[$i]; +//: wire [7:0] client${nindex}2mcif_rd_wt = reg2dp_rd_weight_$dma_name[$i]; +//:); +//:$nindex++; +//:} +//:else { +//: if ($dma_name[$i] ne "na") { +//: print qq(wire [7:0] reg2dp_rd_weight_$dma_name[$i];); +//: } +//:} +//:} +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1,1, 1, 0, 0,0,0,0,0,0); +//: my @dma_name=("bdma","sdp","cdp","pdp","rbk","na","na","na","na","na","na","na","na","na","na","na"); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: wire [7:0] reg2dp_wr_weight_$dma_name[$i]; +//: wire [7:0] client${nindex}2mcif_wr_wt = reg2dp_wr_weight_$dma_name[$i]; +//:); +//:$nindex++; +//:} +//:else { +//: if ($dma_name[$i] ne "na") { +//: print qq(wire [7:0] reg2dp_wr_weight_$dma_name[$i];); +//: } +//:} +//:} +wire [7:0] reg2dp_rd_os_cnt; +wire [7:0] reg2dp_wr_os_cnt; +NV_NVDLA_MCIF_csb u_csb ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< i + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> o + ,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< i + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> o + ,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> o + ,.dp2reg_idle ({1{1'b1}}) //|< ? + ,.reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|> w + ,.reg2dp_rd_weight_bdma (reg2dp_rd_weight_bdma[7:0]) //|> w + ,.reg2dp_rd_weight_cdma_dat (reg2dp_rd_weight_cdma_dat[7:0]) //|> w + ,.reg2dp_rd_weight_cdma_wt (reg2dp_rd_weight_cdma_wt[7:0]) //|> w + ,.reg2dp_rd_weight_cdp (reg2dp_rd_weight_cdp[7:0]) //|> w + ,.reg2dp_rd_weight_pdp (reg2dp_rd_weight_pdp[7:0]) //|> w + ,.reg2dp_rd_weight_rbk (reg2dp_rd_weight_rbk[7:0]) //|> w + ,.reg2dp_rd_weight_rsv_0 () //|> ? + ,.reg2dp_rd_weight_rsv_1 () //|> ? + ,.reg2dp_rd_weight_sdp (reg2dp_rd_weight_sdp[7:0]) //|> w + ,.reg2dp_rd_weight_sdp_b (reg2dp_rd_weight_sdp_b[7:0]) //|> w + ,.reg2dp_rd_weight_sdp_e (reg2dp_rd_weight_sdp_e[7:0]) //|> w + ,.reg2dp_rd_weight_sdp_n (reg2dp_rd_weight_sdp_n[7:0]) //|> w + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt[7:0]) //|> w + ,.reg2dp_wr_weight_bdma (reg2dp_wr_weight_bdma[7:0]) //|> w + ,.reg2dp_wr_weight_cdp (reg2dp_wr_weight_cdp[7:0]) //|> w + ,.reg2dp_wr_weight_pdp (reg2dp_wr_weight_pdp[7:0]) //|> w + ,.reg2dp_wr_weight_rbk (reg2dp_wr_weight_rbk[7:0]) //|> w + ,.reg2dp_wr_weight_rsv_0 () //|> ? + ,.reg2dp_wr_weight_rsv_1 () //|> ? + ,.reg2dp_wr_weight_rsv_2 () //|> ? + ,.reg2dp_wr_weight_sdp (reg2dp_wr_weight_sdp[7:0]) //|> w + ); +NV_NVDLA_NOCIF_DRAM_read u_read ( + .reg2dp_rd_os_cnt (reg2dp_rd_os_cnt[7:0]) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd) +//:my $k=7; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print(",.client${i}2mcif_rd_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print(",.client${i}2mcif_rd_req_valid (client${i}2mcif_rd_req_valid)\n"); +//: print(",.client${i}2mcif_rd_req_ready (client${i}2mcif_rd_req_ready)\n"); +//: print(",.client${i}2mcif_rd_req_pd (client${i}2mcif_rd_req_pd)\n"); +//: print(",.mcif2client${i}_rd_rsp_valid (mcif2client${i}_rd_rsp_valid)\n"); +//: print(",.mcif2client${i}_rd_rsp_ready (mcif2client${i}_rd_rsp_ready)\n"); +//: print(",.mcif2client${i}_rd_rsp_pd (mcif2client${i}_rd_rsp_pd)\n"), +//: print(",.client${i}2mcif_rd_wt (client${i}2mcif_rd_wt)\n"), +//: print(",.client${i}2mcif_rd_axid (client${i}2mcif_rd_axid)\n"), +//: print(",.client${i}2mcif_lat_fifo_depth (client${i}2mcif_lat_fifo_depth)\n"), +//: } + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr) //|> o + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid) //|< i + ,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i + ,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata) //|< i +); +NV_NVDLA_NOCIF_DRAM_write u_write ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.reg2dp_wr_os_cnt (reg2dp_wr_os_cnt) +//:my $k=3; +//:my $i; +//:for ($i=0;$i<$k;$i++) { +//: print(",.client${i}2mcif_wr_req_valid(client${i}2mcif_wr_req_valid)\n"); +//: print(",.client${i}2mcif_wr_req_ready(client${i}2mcif_wr_req_ready)\n"); +//: print(",.client${i}2mcif_wr_req_pd(client${i}2mcif_wr_req_pd)\n"); +//: print(",.client${i}2mcif_wr_wt(client${i}2mcif_wr_wt)\n"); +//: print(",.client${i}2mcif_wr_axid(client${i}2mcif_wr_axid)\n"); +//: print(",.mcif2client${i}_wr_rsp_complete(mcif2client${i}_wr_rsp_complete)\n"); +//:} + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid) //|< i + ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready) //|> o + ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid) //|< i +); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v new file mode 100644 index 0000000..8b7dc21 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v @@ -0,0 +1,5836 @@ +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| !!!!!!!!!!!! !!!!!!!!!!!! +//| !!!!!!!!!!!! DO NOT EDIT - GENERATED BY VIVA - DO NOT EDIT !!!!!!!!!!!! +//| !!!!!!!!!!!! !!!!!!!!!!!! +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| generated by viva: NV_NVDLA_XXIF_libs.vcp --> NV_NVDLA_XXIF_libs.v +//| /home/nvtools/engr/2017/05/16_10_02_50/nvtools/viva/viva -e 'vlib v sv svi svh vt gv bvrl vp defs NULL' -y '. /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/vlib ../../../../../../../../vlib /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c0 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c1 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c2 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c3 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c4 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c5 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c6 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c7 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c8 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c9 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c10 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c11 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c12 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c13 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c14 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c15 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c16 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c17 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c18 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c19 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c20 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c21 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c22 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c23 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c24 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c25 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c26 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c27 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c28 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c29 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c30 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c31 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c32 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c33 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c34 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/rams /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/misc /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/analog/common /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/analog/ism /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/analog/pll /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/common /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/mem /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/mipi /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/uphy /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/sdmem /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/usb /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync/nvstd /home/ip/shared/clock/clkgate/1.0/36067466/verilog ./rams/model' -i '. ../../../../include/private/collector/headers/tlit5 /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/include ../../../../../../../inf/sim_helpers/1.0/include/public/rtl /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions ../../../../../../../../vlib /home/ip/shared/inf/ness/2.0/38823533/include/verilog /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include ./rams/model' -p ' /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/shared /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/archive ../../../plugins' -pf /home/nvtools/engr/2017/06/26_10_09_38/nvtools/viva_plugins/mobile/unit_actmon.pl -d NV_BEHAVIORAL -d NVTOOLS_SYNC2D_GENERIC_CELL -d BEHAVIORAL_AUTOPD_DEFAULT -d JTAGREG_CONFIG=/error_get_source_dir_not_found_might_mean_missing_input_in_t_make_config_but_could_also_indicate_garbage_input_for/__TOP-ip/socd/ip_chip_tools/1.0/defs/public/jtagreg/golden/tlit5/jtagreg.yml NV_NVDLA_XXIF_libs.vcp -o NV_NVDLA_XXIF_libs.v +// +// nvdla_module_mcif_ness_defines.vh +// DO NOT EDIT, generated by ness version 2.0, backend=verilog +// +// Command: /home/ip/shared/inf/ness/2.0/38823533/bin/run_ispec_backend verilog nvdla_all.nessdb defs.touch-verilog -backend_opt '--nogenerate_io_capture' -backend_opt '--generate_ports' +// source file[s] : nvdla_module_mcif +// !defined(_nvdla_module_mcif_ness_defines_VH) +//INCR +// &PerlBeg; +// vprinti qq { +// | \&Shell \${ARBGEN2} -m -n 5 -stdout -t wrr -wt_width 4 ; +// }; +// &PerlEnd; +//| &Shell ${ARBGEN2} -m read_ig_arb -n 10 -stdout -gnt_busy -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m read_ig_arb -n 10 -stdout -gnt_busy -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module read_ig_arb; +module read_ig_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,req5 + ,req6 + ,req7 + ,req8 + ,req9 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,wt5 + ,wt6 + ,wt7 + ,wt8 + ,wt9 + ,gnt_busy + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ,gnt5 + ,gnt6 + ,gnt7 + ,gnt8 + ,gnt9 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input req5; +input req6; +input req7; +input req8; +input req9; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input [7:0] wt5; +input [7:0] wt6; +input [7:0] wt7; +input [7:0] wt8; +input [7:0] wt9; +input gnt_busy; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +output gnt5; +output gnt6; +output gnt7; +output gnt8; +output gnt9; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [9:0] gnt; +reg [9:0] gnt_pre; +reg [9:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [7:0] new_wt_left5; +wire [7:0] new_wt_left6; +wire [7:0] new_wt_left7; +wire [7:0] new_wt_left8; +wire [7:0] new_wt_left9; +wire [9:0] req; +//| &Vector 10 gnt; +//| &Vector 10 wrr_gnt; +//| &Vector 10 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 10 req; +assign req = { + (req9 & (|wt9)) +, (req8 & (|wt8)) +, (req7 & (|wt7)) +, (req6 & (|wt6)) +, (req5 & (|wt5)) +, (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt9 +,gnt8 +,gnt7 +,gnt6 +,gnt5 +,gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_0 +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {10{!gnt_busy}} & gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +assign new_wt_left5[7:0] = wt5 - 1'b1; +assign new_wt_left6[7:0] = wt6 - 1'b1; +assign new_wt_left7[7:0] = wt7 - 1'b1; +assign new_wt_left8[7:0] = wt8 - 1'b1; +assign new_wt_left9[7:0] = wt9 - 1'b1; +//| &Always; +//| _com_1 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + or new_wt_left5 + or new_wt_left6 + or new_wt_left7 + or new_wt_left8 + or new_wt_left9 + ) begin + gnt_pre = {10{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 10'b0000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end + 10'b0000000001 : begin + if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + end + 10'b0000000010 : begin + if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + end + 10'b0000000100 : begin + if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + end + 10'b0000001000 : begin + if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + end + 10'b0000010000 : begin + if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + end + 10'b0000100000 : begin + if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + end + 10'b0001000000 : begin + if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + end + 10'b0010000000 : begin + if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + end + 10'b0100000000 : begin + if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + end + 10'b1000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end +//| ::casedefault gnt_pre 10 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[9:0] = {10{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_0 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {10{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (!gnt_busy & req != {10{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=10) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,10,0,"gnt not zero one hot") zzz_grant_zero_one_hot_1x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_2x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (!gnt_busy & |(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_3x (clk, `ASSERT_RESET, (!gnt_busy & |(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=gnt_when_busy) "gnt when gnt_busy " (gnt_busy & |gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt when gnt_busy ") zzz_gnt_when_busy_4x (clk, `ASSERT_RESET, (gnt_busy & |gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_clk = clk; +wire testpoint_0_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_reset_ +// Clock signal: testpoint_0_internal_clk + reg testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk; + initial + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b0; + always @(posedge testpoint_0_internal_clk or negedge testpoint_0_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_reset_) + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 0 granted ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 0 granted ::: testpoint_0_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_clk = clk; +wire testpoint_1_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_reset_ +// Clock signal: testpoint_1_internal_clk + reg testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk; + initial + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b0; + always @(posedge testpoint_1_internal_clk or negedge testpoint_1_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_reset_) + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 1 granted ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 1 granted ::: testpoint_1_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_2_internal_clk = clk; +wire testpoint_2_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_2_internal_reset_ +// Clock signal: testpoint_2_internal_clk + reg testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk; + initial + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b0; + always @(posedge testpoint_2_internal_clk or negedge testpoint_2_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_2 + if (~testpoint_2_internal_reset_) + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_2_count_0; + reg testpoint_2_goal_0; + initial testpoint_2_goal_0 = 0; + initial testpoint_2_count_0 = 0; + always@(testpoint_2_count_0) begin + if(testpoint_2_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_2_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 2 granted ::: testpoint_2_goal_0 + testpoint_2_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_2_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_2_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2 + if (testpoint_2_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 2 granted ::: testpoint_2_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + testpoint_2_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) begin + `endif + testpoint_2_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_2_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_3_internal_clk = clk; +wire testpoint_3_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_3_internal_reset_ +// Clock signal: testpoint_3_internal_clk + reg testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk; + initial + testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk <= 1'b0; + always @(posedge testpoint_3_internal_clk or negedge testpoint_3_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_3 + if (~testpoint_3_internal_reset_) + testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_3_count_0; + reg testpoint_3_goal_0; + initial testpoint_3_goal_0 = 0; + initial testpoint_3_count_0 = 0; + always@(testpoint_3_count_0) begin + if(testpoint_3_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_3_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 3 granted ::: testpoint_3_goal_0 + testpoint_3_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_3_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_3_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_3 + if (testpoint_3_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 3 granted ::: testpoint_3_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk) + testpoint_3_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk) begin + `endif + testpoint_3_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_3_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_3_goal_0 (.clk (testpoint_3_internal_clk), .tp(testpoint_3_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_3_internal_clk), .tp(testpoint_3_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_4_internal_clk = clk; +wire testpoint_4_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_4_internal_reset_ +// Clock signal: testpoint_4_internal_clk + reg testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk; + initial + testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk <= 1'b0; + always @(posedge testpoint_4_internal_clk or negedge testpoint_4_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_4 + if (~testpoint_4_internal_reset_) + testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_4_count_0; + reg testpoint_4_goal_0; + initial testpoint_4_goal_0 = 0; + initial testpoint_4_count_0 = 0; + always@(testpoint_4_count_0) begin + if(testpoint_4_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_4_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 4 granted ::: testpoint_4_goal_0 + testpoint_4_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_4_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_4_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_4 + if (testpoint_4_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 4 granted ::: testpoint_4_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk) + testpoint_4_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk) begin + `endif + testpoint_4_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_4_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_4_goal_0 (.clk (testpoint_4_internal_clk), .tp(testpoint_4_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_4_internal_clk), .tp(testpoint_4_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 5 granted" -clk clk -reset reset_ (gnt[5]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_5_granted + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // TP__Client_5_granted +`ifdef COVER_OR_TP__Client_5_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 5 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_5_internal_clk = clk; +wire testpoint_5_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_5_internal_reset_ +// Clock signal: testpoint_5_internal_clk + reg testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk; + initial + testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk <= 1'b0; + always @(posedge testpoint_5_internal_clk or negedge testpoint_5_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_5 + if (~testpoint_5_internal_reset_) + testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_5_count_0; + reg testpoint_5_goal_0; + initial testpoint_5_goal_0 = 0; + initial testpoint_5_count_0 = 0; + always@(testpoint_5_count_0) begin + if(testpoint_5_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_5_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 5 granted ::: (gnt[5])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 5 granted ::: testpoint_5_goal_0 + testpoint_5_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_5_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_5_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_5 + if (testpoint_5_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[5])) && testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 5 granted ::: testpoint_5_goal_0"); + `endif + if (((gnt[5])) && testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk) + testpoint_5_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk) begin + `endif + testpoint_5_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_5_goal_0_active = (((gnt[5])) && testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_5_goal_0 (.clk (testpoint_5_internal_clk), .tp(testpoint_5_goal_0_active)); + `else + system_verilog_testpoint svt_Client_5_granted_0 (.clk (testpoint_5_internal_clk), .tp(testpoint_5_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_5_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 6 granted" -clk clk -reset reset_ (gnt[6]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_6_granted + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // TP__Client_6_granted +`ifdef COVER_OR_TP__Client_6_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 6 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_6_internal_clk = clk; +wire testpoint_6_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_6_internal_reset_ +// Clock signal: testpoint_6_internal_clk + reg testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk; + initial + testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk <= 1'b0; + always @(posedge testpoint_6_internal_clk or negedge testpoint_6_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_6 + if (~testpoint_6_internal_reset_) + testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_6_count_0; + reg testpoint_6_goal_0; + initial testpoint_6_goal_0 = 0; + initial testpoint_6_count_0 = 0; + always@(testpoint_6_count_0) begin + if(testpoint_6_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_6_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 6 granted ::: (gnt[6])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 6 granted ::: testpoint_6_goal_0 + testpoint_6_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_6_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_6_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_6 + if (testpoint_6_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[6])) && testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 6 granted ::: testpoint_6_goal_0"); + `endif + if (((gnt[6])) && testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk) + testpoint_6_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk) begin + `endif + testpoint_6_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_6_goal_0_active = (((gnt[6])) && testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_6_goal_0 (.clk (testpoint_6_internal_clk), .tp(testpoint_6_goal_0_active)); + `else + system_verilog_testpoint svt_Client_6_granted_0 (.clk (testpoint_6_internal_clk), .tp(testpoint_6_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_6_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 7 granted" -clk clk -reset reset_ (gnt[7]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_7_granted + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // TP__Client_7_granted +`ifdef COVER_OR_TP__Client_7_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 7 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_7_internal_clk = clk; +wire testpoint_7_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_7_internal_reset_ +// Clock signal: testpoint_7_internal_clk + reg testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk; + initial + testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk <= 1'b0; + always @(posedge testpoint_7_internal_clk or negedge testpoint_7_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_7 + if (~testpoint_7_internal_reset_) + testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_7_count_0; + reg testpoint_7_goal_0; + initial testpoint_7_goal_0 = 0; + initial testpoint_7_count_0 = 0; + always@(testpoint_7_count_0) begin + if(testpoint_7_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_7_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 7 granted ::: (gnt[7])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 7 granted ::: testpoint_7_goal_0 + testpoint_7_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_7_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_7_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_7 + if (testpoint_7_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[7])) && testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 7 granted ::: testpoint_7_goal_0"); + `endif + if (((gnt[7])) && testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk) + testpoint_7_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk) begin + `endif + testpoint_7_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_7_goal_0_active = (((gnt[7])) && testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_7_goal_0 (.clk (testpoint_7_internal_clk), .tp(testpoint_7_goal_0_active)); + `else + system_verilog_testpoint svt_Client_7_granted_0 (.clk (testpoint_7_internal_clk), .tp(testpoint_7_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_7_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 8 granted" -clk clk -reset reset_ (gnt[8]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_8_granted + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // TP__Client_8_granted +`ifdef COVER_OR_TP__Client_8_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 8 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_8_internal_clk = clk; +wire testpoint_8_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_8_internal_reset_ +// Clock signal: testpoint_8_internal_clk + reg testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk; + initial + testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk <= 1'b0; + always @(posedge testpoint_8_internal_clk or negedge testpoint_8_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_8 + if (~testpoint_8_internal_reset_) + testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_8_count_0; + reg testpoint_8_goal_0; + initial testpoint_8_goal_0 = 0; + initial testpoint_8_count_0 = 0; + always@(testpoint_8_count_0) begin + if(testpoint_8_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_8_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 8 granted ::: (gnt[8])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 8 granted ::: testpoint_8_goal_0 + testpoint_8_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_8_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_8_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_8 + if (testpoint_8_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[8])) && testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 8 granted ::: testpoint_8_goal_0"); + `endif + if (((gnt[8])) && testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk) + testpoint_8_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk) begin + `endif + testpoint_8_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_8_goal_0_active = (((gnt[8])) && testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_8_goal_0 (.clk (testpoint_8_internal_clk), .tp(testpoint_8_goal_0_active)); + `else + system_verilog_testpoint svt_Client_8_granted_0 (.clk (testpoint_8_internal_clk), .tp(testpoint_8_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_8_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 9 granted" -clk clk -reset reset_ (gnt[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_9_granted + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // TP__Client_9_granted +`ifdef COVER_OR_TP__Client_9_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 9 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_9_internal_clk = clk; +wire testpoint_9_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_9_internal_reset_ +// Clock signal: testpoint_9_internal_clk + reg testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk; + initial + testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk <= 1'b0; + always @(posedge testpoint_9_internal_clk or negedge testpoint_9_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_9 + if (~testpoint_9_internal_reset_) + testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_9_count_0; + reg testpoint_9_goal_0; + initial testpoint_9_goal_0 = 0; + initial testpoint_9_count_0 = 0; + always@(testpoint_9_count_0) begin + if(testpoint_9_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_9_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 9 granted ::: (gnt[9])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 9 granted ::: testpoint_9_goal_0 + testpoint_9_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_9_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_9_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_9 + if (testpoint_9_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[9])) && testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 9 granted ::: testpoint_9_goal_0"); + `endif + if (((gnt[9])) && testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk) + testpoint_9_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk) begin + `endif + testpoint_9_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_9_goal_0_active = (((gnt[9])) && testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_9_goal_0 (.clk (testpoint_9_internal_clk), .tp(testpoint_9_goal_0_active)); + `else + system_verilog_testpoint svt_Client_9_granted_0 (.clk (testpoint_9_internal_clk), .tp(testpoint_9_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_9_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_10_internal_clk = clk; +wire testpoint_10_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_10_internal_reset_ +// Clock signal: testpoint_10_internal_clk + reg testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk; + initial + testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk <= 1'b0; + always @(posedge testpoint_10_internal_clk or negedge testpoint_10_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_10 + if (~testpoint_10_internal_reset_) + testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_10_count_0; + reg testpoint_10_goal_0; + initial testpoint_10_goal_0 = 0; + initial testpoint_10_count_0 = 0; + always@(testpoint_10_count_0) begin + if(testpoint_10_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_10_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: All clients requesting at the same time ::: testpoint_10_goal_0 + testpoint_10_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_10_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_10_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_10 + if (testpoint_10_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: All clients requesting at the same time ::: testpoint_10_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk) + testpoint_10_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk) begin + `endif + testpoint_10_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_10_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_10_goal_0 (.clk (testpoint_10_internal_clk), .tp(testpoint_10_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_10_internal_clk), .tp(testpoint_10_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // read_ig_arb +//| &Viva pop dangle_checks_off; +//| &Shell ${ARBGEN2} -m read_eg_arb -n 10 -stdout -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m read_eg_arb -n 10 -stdout -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module read_eg_arb; +module read_eg_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,req5 + ,req6 + ,req7 + ,req8 + ,req9 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,wt5 + ,wt6 + ,wt7 + ,wt8 + ,wt9 + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ,gnt5 + ,gnt6 + ,gnt7 + ,gnt8 + ,gnt9 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input req5; +input req6; +input req7; +input req8; +input req9; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input [7:0] wt5; +input [7:0] wt6; +input [7:0] wt7; +input [7:0] wt8; +input [7:0] wt9; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +output gnt5; +output gnt6; +output gnt7; +output gnt8; +output gnt9; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [9:0] gnt; +reg [9:0] gnt_pre; +reg [9:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [7:0] new_wt_left5; +wire [7:0] new_wt_left6; +wire [7:0] new_wt_left7; +wire [7:0] new_wt_left8; +wire [7:0] new_wt_left9; +wire [9:0] req; +//| &Vector 10 gnt; +//| &Vector 10 wrr_gnt; +//| &Vector 10 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 10 req; +assign req = { + (req9 & (|wt9)) +, (req8 & (|wt8)) +, (req7 & (|wt7)) +, (req6 & (|wt6)) +, (req5 & (|wt5)) +, (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt9 +,gnt8 +,gnt7 +,gnt6 +,gnt5 +,gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_2 +always @( + gnt_pre + ) begin + gnt = gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +assign new_wt_left5[7:0] = wt5 - 1'b1; +assign new_wt_left6[7:0] = wt6 - 1'b1; +assign new_wt_left7[7:0] = wt7 - 1'b1; +assign new_wt_left8[7:0] = wt8 - 1'b1; +assign new_wt_left9[7:0] = wt9 - 1'b1; +//| &Always; +//| _com_3 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + or new_wt_left5 + or new_wt_left6 + or new_wt_left7 + or new_wt_left8 + or new_wt_left9 + ) begin + gnt_pre = {10{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 10'b0000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end + 10'b0000000001 : begin + if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + end + 10'b0000000010 : begin + if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + end + 10'b0000000100 : begin + if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + end + 10'b0000001000 : begin + if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + end + 10'b0000010000 : begin + if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + end + 10'b0000100000 : begin + if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + end + 10'b0001000000 : begin + if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + end + 10'b0010000000 : begin + if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + end + 10'b0100000000 : begin + if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + end + 10'b1000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end +//| ::casedefault gnt_pre 10 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[9:0] = {10{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_1 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {10{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (req != {10{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=10) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,10,0,"gnt not zero one hot") zzz_grant_zero_one_hot_5x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_6x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (|(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_7x (clk, `ASSERT_RESET, (|(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_11_internal_clk = clk; +wire testpoint_11_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_11_internal_reset_ +// Clock signal: testpoint_11_internal_clk + reg testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk; + initial + testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk <= 1'b0; + always @(posedge testpoint_11_internal_clk or negedge testpoint_11_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_11 + if (~testpoint_11_internal_reset_) + testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_11_count_0; + reg testpoint_11_goal_0; + initial testpoint_11_goal_0 = 0; + initial testpoint_11_count_0 = 0; + always@(testpoint_11_count_0) begin + if(testpoint_11_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_11_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 0 granted ::: testpoint_11_goal_0 + testpoint_11_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_11_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_11_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_11 + if (testpoint_11_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 0 granted ::: testpoint_11_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk) + testpoint_11_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk) begin + `endif + testpoint_11_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_11_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_11_goal_0 (.clk (testpoint_11_internal_clk), .tp(testpoint_11_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_11_internal_clk), .tp(testpoint_11_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_12_internal_clk = clk; +wire testpoint_12_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_12_internal_reset_ +// Clock signal: testpoint_12_internal_clk + reg testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk; + initial + testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk <= 1'b0; + always @(posedge testpoint_12_internal_clk or negedge testpoint_12_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_12 + if (~testpoint_12_internal_reset_) + testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_12_count_0; + reg testpoint_12_goal_0; + initial testpoint_12_goal_0 = 0; + initial testpoint_12_count_0 = 0; + always@(testpoint_12_count_0) begin + if(testpoint_12_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_12_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 1 granted ::: testpoint_12_goal_0 + testpoint_12_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_12_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_12_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_12 + if (testpoint_12_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 1 granted ::: testpoint_12_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk) + testpoint_12_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk) begin + `endif + testpoint_12_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_12_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_12_goal_0 (.clk (testpoint_12_internal_clk), .tp(testpoint_12_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_12_internal_clk), .tp(testpoint_12_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_13_internal_clk = clk; +wire testpoint_13_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_13_internal_reset_ +// Clock signal: testpoint_13_internal_clk + reg testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk; + initial + testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk <= 1'b0; + always @(posedge testpoint_13_internal_clk or negedge testpoint_13_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_13 + if (~testpoint_13_internal_reset_) + testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_13_count_0; + reg testpoint_13_goal_0; + initial testpoint_13_goal_0 = 0; + initial testpoint_13_count_0 = 0; + always@(testpoint_13_count_0) begin + if(testpoint_13_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_13_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 2 granted ::: testpoint_13_goal_0 + testpoint_13_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_13_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_13_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_13 + if (testpoint_13_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 2 granted ::: testpoint_13_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk) + testpoint_13_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk) begin + `endif + testpoint_13_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_13_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_13_goal_0 (.clk (testpoint_13_internal_clk), .tp(testpoint_13_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_13_internal_clk), .tp(testpoint_13_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_14_internal_clk = clk; +wire testpoint_14_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_14_internal_reset_ +// Clock signal: testpoint_14_internal_clk + reg testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk; + initial + testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk <= 1'b0; + always @(posedge testpoint_14_internal_clk or negedge testpoint_14_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_14 + if (~testpoint_14_internal_reset_) + testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_14_count_0; + reg testpoint_14_goal_0; + initial testpoint_14_goal_0 = 0; + initial testpoint_14_count_0 = 0; + always@(testpoint_14_count_0) begin + if(testpoint_14_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_14_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 3 granted ::: testpoint_14_goal_0 + testpoint_14_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_14_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_14_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_14 + if (testpoint_14_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 3 granted ::: testpoint_14_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk) + testpoint_14_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk) begin + `endif + testpoint_14_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_14_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_14_goal_0 (.clk (testpoint_14_internal_clk), .tp(testpoint_14_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_14_internal_clk), .tp(testpoint_14_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_15_internal_clk = clk; +wire testpoint_15_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_15_internal_reset_ +// Clock signal: testpoint_15_internal_clk + reg testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk; + initial + testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk <= 1'b0; + always @(posedge testpoint_15_internal_clk or negedge testpoint_15_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_15 + if (~testpoint_15_internal_reset_) + testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_15_count_0; + reg testpoint_15_goal_0; + initial testpoint_15_goal_0 = 0; + initial testpoint_15_count_0 = 0; + always@(testpoint_15_count_0) begin + if(testpoint_15_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_15_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 4 granted ::: testpoint_15_goal_0 + testpoint_15_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_15_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_15_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_15 + if (testpoint_15_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 4 granted ::: testpoint_15_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk) + testpoint_15_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk) begin + `endif + testpoint_15_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_15_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_15_goal_0 (.clk (testpoint_15_internal_clk), .tp(testpoint_15_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_15_internal_clk), .tp(testpoint_15_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 5 granted" -clk clk -reset reset_ (gnt[5]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_5_granted + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // TP__Client_5_granted +`ifdef COVER_OR_TP__Client_5_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 5 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_16_internal_clk = clk; +wire testpoint_16_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_16_internal_reset_ +// Clock signal: testpoint_16_internal_clk + reg testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk; + initial + testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk <= 1'b0; + always @(posedge testpoint_16_internal_clk or negedge testpoint_16_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_16 + if (~testpoint_16_internal_reset_) + testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_16_count_0; + reg testpoint_16_goal_0; + initial testpoint_16_goal_0 = 0; + initial testpoint_16_count_0 = 0; + always@(testpoint_16_count_0) begin + if(testpoint_16_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_16_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 5 granted ::: (gnt[5])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 5 granted ::: testpoint_16_goal_0 + testpoint_16_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_16_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_16_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_16 + if (testpoint_16_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[5])) && testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 5 granted ::: testpoint_16_goal_0"); + `endif + if (((gnt[5])) && testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk) + testpoint_16_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk) begin + `endif + testpoint_16_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_16_goal_0_active = (((gnt[5])) && testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_16_goal_0 (.clk (testpoint_16_internal_clk), .tp(testpoint_16_goal_0_active)); + `else + system_verilog_testpoint svt_Client_5_granted_0 (.clk (testpoint_16_internal_clk), .tp(testpoint_16_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_5_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 6 granted" -clk clk -reset reset_ (gnt[6]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_6_granted + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // TP__Client_6_granted +`ifdef COVER_OR_TP__Client_6_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 6 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_17_internal_clk = clk; +wire testpoint_17_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_17_internal_reset_ +// Clock signal: testpoint_17_internal_clk + reg testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk; + initial + testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk <= 1'b0; + always @(posedge testpoint_17_internal_clk or negedge testpoint_17_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_17 + if (~testpoint_17_internal_reset_) + testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_17_count_0; + reg testpoint_17_goal_0; + initial testpoint_17_goal_0 = 0; + initial testpoint_17_count_0 = 0; + always@(testpoint_17_count_0) begin + if(testpoint_17_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_17_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 6 granted ::: (gnt[6])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 6 granted ::: testpoint_17_goal_0 + testpoint_17_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_17_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_17_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_17 + if (testpoint_17_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[6])) && testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 6 granted ::: testpoint_17_goal_0"); + `endif + if (((gnt[6])) && testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk) + testpoint_17_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk) begin + `endif + testpoint_17_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_17_goal_0_active = (((gnt[6])) && testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_17_goal_0 (.clk (testpoint_17_internal_clk), .tp(testpoint_17_goal_0_active)); + `else + system_verilog_testpoint svt_Client_6_granted_0 (.clk (testpoint_17_internal_clk), .tp(testpoint_17_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_6_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 7 granted" -clk clk -reset reset_ (gnt[7]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_7_granted + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // TP__Client_7_granted +`ifdef COVER_OR_TP__Client_7_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 7 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_18_internal_clk = clk; +wire testpoint_18_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_18_internal_reset_ +// Clock signal: testpoint_18_internal_clk + reg testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk; + initial + testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk <= 1'b0; + always @(posedge testpoint_18_internal_clk or negedge testpoint_18_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_18 + if (~testpoint_18_internal_reset_) + testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_18_count_0; + reg testpoint_18_goal_0; + initial testpoint_18_goal_0 = 0; + initial testpoint_18_count_0 = 0; + always@(testpoint_18_count_0) begin + if(testpoint_18_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_18_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 7 granted ::: (gnt[7])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 7 granted ::: testpoint_18_goal_0 + testpoint_18_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_18_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_18_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_18 + if (testpoint_18_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[7])) && testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 7 granted ::: testpoint_18_goal_0"); + `endif + if (((gnt[7])) && testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk) + testpoint_18_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk) begin + `endif + testpoint_18_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_18_goal_0_active = (((gnt[7])) && testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_18_goal_0 (.clk (testpoint_18_internal_clk), .tp(testpoint_18_goal_0_active)); + `else + system_verilog_testpoint svt_Client_7_granted_0 (.clk (testpoint_18_internal_clk), .tp(testpoint_18_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_7_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 8 granted" -clk clk -reset reset_ (gnt[8]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_8_granted + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // TP__Client_8_granted +`ifdef COVER_OR_TP__Client_8_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 8 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_19_internal_clk = clk; +wire testpoint_19_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_19_internal_reset_ +// Clock signal: testpoint_19_internal_clk + reg testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk; + initial + testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk <= 1'b0; + always @(posedge testpoint_19_internal_clk or negedge testpoint_19_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_19 + if (~testpoint_19_internal_reset_) + testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_19_count_0; + reg testpoint_19_goal_0; + initial testpoint_19_goal_0 = 0; + initial testpoint_19_count_0 = 0; + always@(testpoint_19_count_0) begin + if(testpoint_19_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_19_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 8 granted ::: (gnt[8])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 8 granted ::: testpoint_19_goal_0 + testpoint_19_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_19_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_19_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_19 + if (testpoint_19_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[8])) && testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 8 granted ::: testpoint_19_goal_0"); + `endif + if (((gnt[8])) && testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk) + testpoint_19_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk) begin + `endif + testpoint_19_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_19_goal_0_active = (((gnt[8])) && testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_19_goal_0 (.clk (testpoint_19_internal_clk), .tp(testpoint_19_goal_0_active)); + `else + system_verilog_testpoint svt_Client_8_granted_0 (.clk (testpoint_19_internal_clk), .tp(testpoint_19_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_8_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 9 granted" -clk clk -reset reset_ (gnt[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_9_granted + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // TP__Client_9_granted +`ifdef COVER_OR_TP__Client_9_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 9 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_20_internal_clk = clk; +wire testpoint_20_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_20_internal_reset_ +// Clock signal: testpoint_20_internal_clk + reg testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk; + initial + testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk <= 1'b0; + always @(posedge testpoint_20_internal_clk or negedge testpoint_20_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_20 + if (~testpoint_20_internal_reset_) + testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_20_count_0; + reg testpoint_20_goal_0; + initial testpoint_20_goal_0 = 0; + initial testpoint_20_count_0 = 0; + always@(testpoint_20_count_0) begin + if(testpoint_20_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_20_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 9 granted ::: (gnt[9])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 9 granted ::: testpoint_20_goal_0 + testpoint_20_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_20_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_20_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_20 + if (testpoint_20_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[9])) && testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 9 granted ::: testpoint_20_goal_0"); + `endif + if (((gnt[9])) && testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk) + testpoint_20_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk) begin + `endif + testpoint_20_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_20_goal_0_active = (((gnt[9])) && testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_20_goal_0 (.clk (testpoint_20_internal_clk), .tp(testpoint_20_goal_0_active)); + `else + system_verilog_testpoint svt_Client_9_granted_0 (.clk (testpoint_20_internal_clk), .tp(testpoint_20_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_9_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_21_internal_clk = clk; +wire testpoint_21_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_21_internal_reset_ +// Clock signal: testpoint_21_internal_clk + reg testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk; + initial + testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk <= 1'b0; + always @(posedge testpoint_21_internal_clk or negedge testpoint_21_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_21 + if (~testpoint_21_internal_reset_) + testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_21_count_0; + reg testpoint_21_goal_0; + initial testpoint_21_goal_0 = 0; + initial testpoint_21_count_0 = 0; + always@(testpoint_21_count_0) begin + if(testpoint_21_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_21_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: All clients requesting at the same time ::: testpoint_21_goal_0 + testpoint_21_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_21_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_21_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_21 + if (testpoint_21_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: All clients requesting at the same time ::: testpoint_21_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk) + testpoint_21_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk) begin + `endif + testpoint_21_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_21_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_21_goal_0 (.clk (testpoint_21_internal_clk), .tp(testpoint_21_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_21_internal_clk), .tp(testpoint_21_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // read_eg_arb +//| &Viva pop dangle_checks_off; +//| &Shell ${ARBGEN2} -m write_ig_arb -n 5 -stdout -gnt_busy -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m write_ig_arb -n 5 -stdout -gnt_busy -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module write_ig_arb; +module write_ig_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,gnt_busy + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input gnt_busy; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [4:0] gnt; +reg [4:0] gnt_pre; +reg [4:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [4:0] req; +//| &Vector 5 gnt; +//| &Vector 5 wrr_gnt; +//| &Vector 5 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 5 req; +assign req = { + (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_4 +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {5{!gnt_busy}} & gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +//| &Always; +//| _com_5 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + ) begin + gnt_pre = {5{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 5'b00000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end + 5'b00001 : begin + if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + end + 5'b00010 : begin + if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + end + 5'b00100 : begin + if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + end + 5'b01000 : begin + if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + end + 5'b10000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end +//| ::casedefault gnt_pre 5 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[4:0] = {5{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_2 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {5{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (!gnt_busy & req != {5{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=5) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,5,0,"gnt not zero one hot") zzz_grant_zero_one_hot_8x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_9x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (!gnt_busy & |(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_10x (clk, `ASSERT_RESET, (!gnt_busy & |(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=gnt_when_busy) "gnt when gnt_busy " (gnt_busy & |gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt when gnt_busy ") zzz_gnt_when_busy_11x (clk, `ASSERT_RESET, (gnt_busy & |gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_22_internal_clk = clk; +wire testpoint_22_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_22_internal_reset_ +// Clock signal: testpoint_22_internal_clk + reg testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk; + initial + testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk <= 1'b0; + always @(posedge testpoint_22_internal_clk or negedge testpoint_22_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_22 + if (~testpoint_22_internal_reset_) + testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_22_count_0; + reg testpoint_22_goal_0; + initial testpoint_22_goal_0 = 0; + initial testpoint_22_count_0 = 0; + always@(testpoint_22_count_0) begin + if(testpoint_22_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_22_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 0 granted ::: testpoint_22_goal_0 + testpoint_22_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_22_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_22_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_22 + if (testpoint_22_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 0 granted ::: testpoint_22_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk) + testpoint_22_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk) begin + `endif + testpoint_22_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_22_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_22_goal_0 (.clk (testpoint_22_internal_clk), .tp(testpoint_22_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_22_internal_clk), .tp(testpoint_22_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_23_internal_clk = clk; +wire testpoint_23_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_23_internal_reset_ +// Clock signal: testpoint_23_internal_clk + reg testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk; + initial + testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk <= 1'b0; + always @(posedge testpoint_23_internal_clk or negedge testpoint_23_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_23 + if (~testpoint_23_internal_reset_) + testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_23_count_0; + reg testpoint_23_goal_0; + initial testpoint_23_goal_0 = 0; + initial testpoint_23_count_0 = 0; + always@(testpoint_23_count_0) begin + if(testpoint_23_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_23_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 1 granted ::: testpoint_23_goal_0 + testpoint_23_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_23_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_23_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_23 + if (testpoint_23_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 1 granted ::: testpoint_23_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk) + testpoint_23_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk) begin + `endif + testpoint_23_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_23_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_23_goal_0 (.clk (testpoint_23_internal_clk), .tp(testpoint_23_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_23_internal_clk), .tp(testpoint_23_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_24_internal_clk = clk; +wire testpoint_24_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_24_internal_reset_ +// Clock signal: testpoint_24_internal_clk + reg testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk; + initial + testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk <= 1'b0; + always @(posedge testpoint_24_internal_clk or negedge testpoint_24_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_24 + if (~testpoint_24_internal_reset_) + testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_24_count_0; + reg testpoint_24_goal_0; + initial testpoint_24_goal_0 = 0; + initial testpoint_24_count_0 = 0; + always@(testpoint_24_count_0) begin + if(testpoint_24_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_24_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 2 granted ::: testpoint_24_goal_0 + testpoint_24_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_24_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_24_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_24 + if (testpoint_24_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 2 granted ::: testpoint_24_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk) + testpoint_24_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk) begin + `endif + testpoint_24_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_24_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_24_goal_0 (.clk (testpoint_24_internal_clk), .tp(testpoint_24_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_24_internal_clk), .tp(testpoint_24_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_25_internal_clk = clk; +wire testpoint_25_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_25_internal_reset_ +// Clock signal: testpoint_25_internal_clk + reg testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk; + initial + testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk <= 1'b0; + always @(posedge testpoint_25_internal_clk or negedge testpoint_25_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_25 + if (~testpoint_25_internal_reset_) + testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_25_count_0; + reg testpoint_25_goal_0; + initial testpoint_25_goal_0 = 0; + initial testpoint_25_count_0 = 0; + always@(testpoint_25_count_0) begin + if(testpoint_25_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_25_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 3 granted ::: testpoint_25_goal_0 + testpoint_25_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_25_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_25_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_25 + if (testpoint_25_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 3 granted ::: testpoint_25_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk) + testpoint_25_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk) begin + `endif + testpoint_25_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_25_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_25_goal_0 (.clk (testpoint_25_internal_clk), .tp(testpoint_25_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_25_internal_clk), .tp(testpoint_25_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_26_internal_clk = clk; +wire testpoint_26_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_26_internal_reset_ +// Clock signal: testpoint_26_internal_clk + reg testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk; + initial + testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk <= 1'b0; + always @(posedge testpoint_26_internal_clk or negedge testpoint_26_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_26 + if (~testpoint_26_internal_reset_) + testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_26_count_0; + reg testpoint_26_goal_0; + initial testpoint_26_goal_0 = 0; + initial testpoint_26_count_0 = 0; + always@(testpoint_26_count_0) begin + if(testpoint_26_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_26_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 4 granted ::: testpoint_26_goal_0 + testpoint_26_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_26_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_26_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_26 + if (testpoint_26_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 4 granted ::: testpoint_26_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk) + testpoint_26_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk) begin + `endif + testpoint_26_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_26_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_26_goal_0 (.clk (testpoint_26_internal_clk), .tp(testpoint_26_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_26_internal_clk), .tp(testpoint_26_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_27_internal_clk = clk; +wire testpoint_27_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_27_internal_reset_ +// Clock signal: testpoint_27_internal_clk + reg testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk; + initial + testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk <= 1'b0; + always @(posedge testpoint_27_internal_clk or negedge testpoint_27_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_27 + if (~testpoint_27_internal_reset_) + testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_27_count_0; + reg testpoint_27_goal_0; + initial testpoint_27_goal_0 = 0; + initial testpoint_27_count_0 = 0; + always@(testpoint_27_count_0) begin + if(testpoint_27_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_27_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: All clients requesting at the same time ::: testpoint_27_goal_0 + testpoint_27_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_27_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_27_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_27 + if (testpoint_27_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: All clients requesting at the same time ::: testpoint_27_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk) + testpoint_27_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk) begin + `endif + testpoint_27_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_27_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_27_goal_0 (.clk (testpoint_27_internal_clk), .tp(testpoint_27_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_27_internal_clk), .tp(testpoint_27_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // write_ig_arb +//| &Viva pop dangle_checks_off; +//| &Shell ${ARBGEN2} -m write_eg_arb -n 5 -stdout -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m write_eg_arb -n 5 -stdout -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module write_eg_arb; +module write_eg_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [4:0] gnt; +reg [4:0] gnt_pre; +reg [4:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [4:0] req; +//| &Vector 5 gnt; +//| &Vector 5 wrr_gnt; +//| &Vector 5 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 5 req; +assign req = { + (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_6 +always @( + gnt_pre + ) begin + gnt = gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +//| &Always; +//| _com_7 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + ) begin + gnt_pre = {5{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 5'b00000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end + 5'b00001 : begin + if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + end + 5'b00010 : begin + if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + end + 5'b00100 : begin + if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + end + 5'b01000 : begin + if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + end + 5'b10000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end +//| ::casedefault gnt_pre 5 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[4:0] = {5{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_3 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {5{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (req != {5{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=5) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,5,0,"gnt not zero one hot") zzz_grant_zero_one_hot_12x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_13x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (|(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_14x (clk, `ASSERT_RESET, (|(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_28_internal_clk = clk; +wire testpoint_28_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_28_internal_reset_ +// Clock signal: testpoint_28_internal_clk + reg testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk; + initial + testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk <= 1'b0; + always @(posedge testpoint_28_internal_clk or negedge testpoint_28_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_28 + if (~testpoint_28_internal_reset_) + testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_28_count_0; + reg testpoint_28_goal_0; + initial testpoint_28_goal_0 = 0; + initial testpoint_28_count_0 = 0; + always@(testpoint_28_count_0) begin + if(testpoint_28_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_28_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 0 granted ::: testpoint_28_goal_0 + testpoint_28_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_28_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_28_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_28 + if (testpoint_28_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 0 granted ::: testpoint_28_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk) + testpoint_28_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk) begin + `endif + testpoint_28_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_28_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_28_goal_0 (.clk (testpoint_28_internal_clk), .tp(testpoint_28_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_28_internal_clk), .tp(testpoint_28_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_29_internal_clk = clk; +wire testpoint_29_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_29_internal_reset_ +// Clock signal: testpoint_29_internal_clk + reg testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk; + initial + testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk <= 1'b0; + always @(posedge testpoint_29_internal_clk or negedge testpoint_29_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_29 + if (~testpoint_29_internal_reset_) + testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_29_count_0; + reg testpoint_29_goal_0; + initial testpoint_29_goal_0 = 0; + initial testpoint_29_count_0 = 0; + always@(testpoint_29_count_0) begin + if(testpoint_29_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_29_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 1 granted ::: testpoint_29_goal_0 + testpoint_29_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_29_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_29_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_29 + if (testpoint_29_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 1 granted ::: testpoint_29_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk) + testpoint_29_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk) begin + `endif + testpoint_29_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_29_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_29_goal_0 (.clk (testpoint_29_internal_clk), .tp(testpoint_29_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_29_internal_clk), .tp(testpoint_29_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_30_internal_clk = clk; +wire testpoint_30_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_30_internal_reset_ +// Clock signal: testpoint_30_internal_clk + reg testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk; + initial + testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk <= 1'b0; + always @(posedge testpoint_30_internal_clk or negedge testpoint_30_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_30 + if (~testpoint_30_internal_reset_) + testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_30_count_0; + reg testpoint_30_goal_0; + initial testpoint_30_goal_0 = 0; + initial testpoint_30_count_0 = 0; + always@(testpoint_30_count_0) begin + if(testpoint_30_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_30_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 2 granted ::: testpoint_30_goal_0 + testpoint_30_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_30_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_30_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_30 + if (testpoint_30_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 2 granted ::: testpoint_30_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk) + testpoint_30_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk) begin + `endif + testpoint_30_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_30_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_30_goal_0 (.clk (testpoint_30_internal_clk), .tp(testpoint_30_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_30_internal_clk), .tp(testpoint_30_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_31_internal_clk = clk; +wire testpoint_31_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_31_internal_reset_ +// Clock signal: testpoint_31_internal_clk + reg testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk; + initial + testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk <= 1'b0; + always @(posedge testpoint_31_internal_clk or negedge testpoint_31_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_31 + if (~testpoint_31_internal_reset_) + testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_31_count_0; + reg testpoint_31_goal_0; + initial testpoint_31_goal_0 = 0; + initial testpoint_31_count_0 = 0; + always@(testpoint_31_count_0) begin + if(testpoint_31_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_31_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 3 granted ::: testpoint_31_goal_0 + testpoint_31_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_31_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_31_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_31 + if (testpoint_31_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 3 granted ::: testpoint_31_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk) + testpoint_31_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk) begin + `endif + testpoint_31_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_31_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_31_goal_0 (.clk (testpoint_31_internal_clk), .tp(testpoint_31_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_31_internal_clk), .tp(testpoint_31_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_32_internal_clk = clk; +wire testpoint_32_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_32_internal_reset_ +// Clock signal: testpoint_32_internal_clk + reg testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk; + initial + testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk <= 1'b0; + always @(posedge testpoint_32_internal_clk or negedge testpoint_32_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_32 + if (~testpoint_32_internal_reset_) + testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_32_count_0; + reg testpoint_32_goal_0; + initial testpoint_32_goal_0 = 0; + initial testpoint_32_count_0 = 0; + always@(testpoint_32_count_0) begin + if(testpoint_32_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_32_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 4 granted ::: testpoint_32_goal_0 + testpoint_32_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_32_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_32_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_32 + if (testpoint_32_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 4 granted ::: testpoint_32_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk) + testpoint_32_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk) begin + `endif + testpoint_32_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_32_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_32_goal_0 (.clk (testpoint_32_internal_clk), .tp(testpoint_32_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_32_internal_clk), .tp(testpoint_32_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_33_internal_clk = clk; +wire testpoint_33_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_33_internal_reset_ +// Clock signal: testpoint_33_internal_clk + reg testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk; + initial + testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk <= 1'b0; + always @(posedge testpoint_33_internal_clk or negedge testpoint_33_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_33 + if (~testpoint_33_internal_reset_) + testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_33_count_0; + reg testpoint_33_goal_0; + initial testpoint_33_goal_0 = 0; + initial testpoint_33_count_0 = 0; + always@(testpoint_33_count_0) begin + if(testpoint_33_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_33_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: All clients requesting at the same time ::: testpoint_33_goal_0 + testpoint_33_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_33_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_33_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_33 + if (testpoint_33_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: All clients requesting at the same time ::: testpoint_33_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk) + testpoint_33_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk) begin + `endif + testpoint_33_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_33_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_33_goal_0 (.clk (testpoint_33_internal_clk), .tp(testpoint_33_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_33_internal_clk), .tp(testpoint_33_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // write_eg_arb +//| &Viva pop dangle_checks_off; diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v.vcp new file mode 100644 index 0000000..8b7dc21 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v.vcp @@ -0,0 +1,5836 @@ +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| !!!!!!!!!!!! !!!!!!!!!!!! +//| !!!!!!!!!!!! DO NOT EDIT - GENERATED BY VIVA - DO NOT EDIT !!!!!!!!!!!! +//| !!!!!!!!!!!! !!!!!!!!!!!! +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +//| generated by viva: NV_NVDLA_XXIF_libs.vcp --> NV_NVDLA_XXIF_libs.v +//| /home/nvtools/engr/2017/05/16_10_02_50/nvtools/viva/viva -e 'vlib v sv svi svh vt gv bvrl vp defs NULL' -y '. /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/vlib ../../../../../../../../vlib /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c0 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c1 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c2 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c3 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c4 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c5 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c6 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c7 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c8 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c9 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c10 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c11 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c12 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c13 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c14 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c15 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c16 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c17 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c18 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c19 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c20 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c21 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c22 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c23 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c24 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c25 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c26 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c27 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c28 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c29 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c30 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c31 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c32 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c33 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/stdcell/c34 /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/rams /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/misc /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/analog/common /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/analog/ism /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/analog/pll /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/common /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/mem /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/mipi /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/uphy /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/sdmem /home/libs/tlit5_vlibcells/11649425_10252017/librarycells/pads/usb /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync /home/nvtools/engr/2017/05/25_05_01_38/nvtools/rtl/vlib/sync/nvstd /home/ip/shared/clock/clkgate/1.0/36067466/verilog ./rams/model' -i '. ../../../../include/private/collector/headers/tlit5 /home/nvtools/engr/2017/05/16_10_02_50/nvtools/rtl/include ../../../../../../../inf/sim_helpers/1.0/include/public/rtl /home/nvtools/engr/2017/03/07_07_35_45/nvtools/assertions ../../../../../../../../vlib /home/ip/shared/inf/ness/2.0/38823533/include/verilog /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include /home/ip/shared/fpga/shared_proto/1.0/38757645/vmod/include ./rams/model' -p ' /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/shared /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/mobile /home/nvtools/engr/2017/06/15_05_01_31/nvtools/viva_plugins/archive ../../../plugins' -pf /home/nvtools/engr/2017/06/26_10_09_38/nvtools/viva_plugins/mobile/unit_actmon.pl -d NV_BEHAVIORAL -d NVTOOLS_SYNC2D_GENERIC_CELL -d BEHAVIORAL_AUTOPD_DEFAULT -d JTAGREG_CONFIG=/error_get_source_dir_not_found_might_mean_missing_input_in_t_make_config_but_could_also_indicate_garbage_input_for/__TOP-ip/socd/ip_chip_tools/1.0/defs/public/jtagreg/golden/tlit5/jtagreg.yml NV_NVDLA_XXIF_libs.vcp -o NV_NVDLA_XXIF_libs.v +// +// nvdla_module_mcif_ness_defines.vh +// DO NOT EDIT, generated by ness version 2.0, backend=verilog +// +// Command: /home/ip/shared/inf/ness/2.0/38823533/bin/run_ispec_backend verilog nvdla_all.nessdb defs.touch-verilog -backend_opt '--nogenerate_io_capture' -backend_opt '--generate_ports' +// source file[s] : nvdla_module_mcif +// !defined(_nvdla_module_mcif_ness_defines_VH) +//INCR +// &PerlBeg; +// vprinti qq { +// | \&Shell \${ARBGEN2} -m -n 5 -stdout -t wrr -wt_width 4 ; +// }; +// &PerlEnd; +//| &Shell ${ARBGEN2} -m read_ig_arb -n 10 -stdout -gnt_busy -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m read_ig_arb -n 10 -stdout -gnt_busy -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module read_ig_arb; +module read_ig_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,req5 + ,req6 + ,req7 + ,req8 + ,req9 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,wt5 + ,wt6 + ,wt7 + ,wt8 + ,wt9 + ,gnt_busy + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ,gnt5 + ,gnt6 + ,gnt7 + ,gnt8 + ,gnt9 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input req5; +input req6; +input req7; +input req8; +input req9; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input [7:0] wt5; +input [7:0] wt6; +input [7:0] wt7; +input [7:0] wt8; +input [7:0] wt9; +input gnt_busy; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +output gnt5; +output gnt6; +output gnt7; +output gnt8; +output gnt9; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [9:0] gnt; +reg [9:0] gnt_pre; +reg [9:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [7:0] new_wt_left5; +wire [7:0] new_wt_left6; +wire [7:0] new_wt_left7; +wire [7:0] new_wt_left8; +wire [7:0] new_wt_left9; +wire [9:0] req; +//| &Vector 10 gnt; +//| &Vector 10 wrr_gnt; +//| &Vector 10 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 10 req; +assign req = { + (req9 & (|wt9)) +, (req8 & (|wt8)) +, (req7 & (|wt7)) +, (req6 & (|wt6)) +, (req5 & (|wt5)) +, (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt9 +,gnt8 +,gnt7 +,gnt6 +,gnt5 +,gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_0 +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {10{!gnt_busy}} & gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +assign new_wt_left5[7:0] = wt5 - 1'b1; +assign new_wt_left6[7:0] = wt6 - 1'b1; +assign new_wt_left7[7:0] = wt7 - 1'b1; +assign new_wt_left8[7:0] = wt8 - 1'b1; +assign new_wt_left9[7:0] = wt9 - 1'b1; +//| &Always; +//| _com_1 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + or new_wt_left5 + or new_wt_left6 + or new_wt_left7 + or new_wt_left8 + or new_wt_left9 + ) begin + gnt_pre = {10{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 10'b0000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end + 10'b0000000001 : begin + if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + end + 10'b0000000010 : begin + if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + end + 10'b0000000100 : begin + if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + end + 10'b0000001000 : begin + if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + end + 10'b0000010000 : begin + if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + end + 10'b0000100000 : begin + if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + end + 10'b0001000000 : begin + if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + end + 10'b0010000000 : begin + if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + end + 10'b0100000000 : begin + if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + end + 10'b1000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end +//| ::casedefault gnt_pre 10 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[9:0] = {10{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_0 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {10{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (!gnt_busy & req != {10{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=10) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,10,0,"gnt not zero one hot") zzz_grant_zero_one_hot_1x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_2x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (!gnt_busy & |(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_3x (clk, `ASSERT_RESET, (!gnt_busy & |(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=gnt_when_busy) "gnt when gnt_busy " (gnt_busy & |gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt when gnt_busy ") zzz_gnt_when_busy_4x (clk, `ASSERT_RESET, (gnt_busy & |gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_clk = clk; +wire testpoint_0_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_reset_ +// Clock signal: testpoint_0_internal_clk + reg testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk; + initial + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b0; + always @(posedge testpoint_0_internal_clk or negedge testpoint_0_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_reset_) + testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 0 granted ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 0 granted ::: testpoint_0_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_0_internal_reset__with_clock_testpoint_0_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_0_internal_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_clk = clk; +wire testpoint_1_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_reset_ +// Clock signal: testpoint_1_internal_clk + reg testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk; + initial + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b0; + always @(posedge testpoint_1_internal_clk or negedge testpoint_1_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_reset_) + testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 1 granted ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 1 granted ::: testpoint_1_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_1_internal_reset__with_clock_testpoint_1_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_1_internal_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_2_internal_clk = clk; +wire testpoint_2_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_2_internal_reset_ +// Clock signal: testpoint_2_internal_clk + reg testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk; + initial + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b0; + always @(posedge testpoint_2_internal_clk or negedge testpoint_2_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_2 + if (~testpoint_2_internal_reset_) + testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_2_count_0; + reg testpoint_2_goal_0; + initial testpoint_2_goal_0 = 0; + initial testpoint_2_count_0 = 0; + always@(testpoint_2_count_0) begin + if(testpoint_2_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_2_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 2 granted ::: testpoint_2_goal_0 + testpoint_2_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_2_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_2_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2 + if (testpoint_2_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 2 granted ::: testpoint_2_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) + testpoint_2_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk) begin + `endif + testpoint_2_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_2_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_2_internal_reset__with_clock_testpoint_2_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_2_internal_clk), .tp(testpoint_2_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_3_internal_clk = clk; +wire testpoint_3_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_3_internal_reset_ +// Clock signal: testpoint_3_internal_clk + reg testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk; + initial + testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk <= 1'b0; + always @(posedge testpoint_3_internal_clk or negedge testpoint_3_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_3 + if (~testpoint_3_internal_reset_) + testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_3_count_0; + reg testpoint_3_goal_0; + initial testpoint_3_goal_0 = 0; + initial testpoint_3_count_0 = 0; + always@(testpoint_3_count_0) begin + if(testpoint_3_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_3_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 3 granted ::: testpoint_3_goal_0 + testpoint_3_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_3_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_3_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_3 + if (testpoint_3_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 3 granted ::: testpoint_3_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk) + testpoint_3_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk) begin + `endif + testpoint_3_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_3_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_3_internal_reset__with_clock_testpoint_3_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_3_goal_0 (.clk (testpoint_3_internal_clk), .tp(testpoint_3_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_3_internal_clk), .tp(testpoint_3_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_4_internal_clk = clk; +wire testpoint_4_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_4_internal_reset_ +// Clock signal: testpoint_4_internal_clk + reg testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk; + initial + testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk <= 1'b0; + always @(posedge testpoint_4_internal_clk or negedge testpoint_4_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_4 + if (~testpoint_4_internal_reset_) + testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_4_count_0; + reg testpoint_4_goal_0; + initial testpoint_4_goal_0 = 0; + initial testpoint_4_count_0 = 0; + always@(testpoint_4_count_0) begin + if(testpoint_4_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_4_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 4 granted ::: testpoint_4_goal_0 + testpoint_4_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_4_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_4_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_4 + if (testpoint_4_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 4 granted ::: testpoint_4_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk) + testpoint_4_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk) begin + `endif + testpoint_4_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_4_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_4_internal_reset__with_clock_testpoint_4_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_4_goal_0 (.clk (testpoint_4_internal_clk), .tp(testpoint_4_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_4_internal_clk), .tp(testpoint_4_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 5 granted" -clk clk -reset reset_ (gnt[5]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_5_granted + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // TP__Client_5_granted +`ifdef COVER_OR_TP__Client_5_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 5 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_5_internal_clk = clk; +wire testpoint_5_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_5_internal_reset_ +// Clock signal: testpoint_5_internal_clk + reg testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk; + initial + testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk <= 1'b0; + always @(posedge testpoint_5_internal_clk or negedge testpoint_5_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_5 + if (~testpoint_5_internal_reset_) + testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_5_count_0; + reg testpoint_5_goal_0; + initial testpoint_5_goal_0 = 0; + initial testpoint_5_count_0 = 0; + always@(testpoint_5_count_0) begin + if(testpoint_5_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_5_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 5 granted ::: (gnt[5])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 5 granted ::: testpoint_5_goal_0 + testpoint_5_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_5_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_5_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_5 + if (testpoint_5_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[5])) && testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 5 granted ::: testpoint_5_goal_0"); + `endif + if (((gnt[5])) && testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk) + testpoint_5_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk) begin + `endif + testpoint_5_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_5_goal_0_active = (((gnt[5])) && testpoint_got_reset_testpoint_5_internal_reset__with_clock_testpoint_5_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_5_goal_0 (.clk (testpoint_5_internal_clk), .tp(testpoint_5_goal_0_active)); + `else + system_verilog_testpoint svt_Client_5_granted_0 (.clk (testpoint_5_internal_clk), .tp(testpoint_5_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_5_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 6 granted" -clk clk -reset reset_ (gnt[6]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_6_granted + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // TP__Client_6_granted +`ifdef COVER_OR_TP__Client_6_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 6 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_6_internal_clk = clk; +wire testpoint_6_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_6_internal_reset_ +// Clock signal: testpoint_6_internal_clk + reg testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk; + initial + testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk <= 1'b0; + always @(posedge testpoint_6_internal_clk or negedge testpoint_6_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_6 + if (~testpoint_6_internal_reset_) + testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_6_count_0; + reg testpoint_6_goal_0; + initial testpoint_6_goal_0 = 0; + initial testpoint_6_count_0 = 0; + always@(testpoint_6_count_0) begin + if(testpoint_6_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_6_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 6 granted ::: (gnt[6])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 6 granted ::: testpoint_6_goal_0 + testpoint_6_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_6_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_6_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_6 + if (testpoint_6_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[6])) && testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 6 granted ::: testpoint_6_goal_0"); + `endif + if (((gnt[6])) && testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk) + testpoint_6_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk) begin + `endif + testpoint_6_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_6_goal_0_active = (((gnt[6])) && testpoint_got_reset_testpoint_6_internal_reset__with_clock_testpoint_6_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_6_goal_0 (.clk (testpoint_6_internal_clk), .tp(testpoint_6_goal_0_active)); + `else + system_verilog_testpoint svt_Client_6_granted_0 (.clk (testpoint_6_internal_clk), .tp(testpoint_6_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_6_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 7 granted" -clk clk -reset reset_ (gnt[7]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_7_granted + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // TP__Client_7_granted +`ifdef COVER_OR_TP__Client_7_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 7 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_7_internal_clk = clk; +wire testpoint_7_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_7_internal_reset_ +// Clock signal: testpoint_7_internal_clk + reg testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk; + initial + testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk <= 1'b0; + always @(posedge testpoint_7_internal_clk or negedge testpoint_7_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_7 + if (~testpoint_7_internal_reset_) + testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_7_count_0; + reg testpoint_7_goal_0; + initial testpoint_7_goal_0 = 0; + initial testpoint_7_count_0 = 0; + always@(testpoint_7_count_0) begin + if(testpoint_7_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_7_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 7 granted ::: (gnt[7])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 7 granted ::: testpoint_7_goal_0 + testpoint_7_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_7_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_7_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_7 + if (testpoint_7_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[7])) && testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 7 granted ::: testpoint_7_goal_0"); + `endif + if (((gnt[7])) && testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk) + testpoint_7_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk) begin + `endif + testpoint_7_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_7_goal_0_active = (((gnt[7])) && testpoint_got_reset_testpoint_7_internal_reset__with_clock_testpoint_7_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_7_goal_0 (.clk (testpoint_7_internal_clk), .tp(testpoint_7_goal_0_active)); + `else + system_verilog_testpoint svt_Client_7_granted_0 (.clk (testpoint_7_internal_clk), .tp(testpoint_7_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_7_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 8 granted" -clk clk -reset reset_ (gnt[8]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_8_granted + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // TP__Client_8_granted +`ifdef COVER_OR_TP__Client_8_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 8 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_8_internal_clk = clk; +wire testpoint_8_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_8_internal_reset_ +// Clock signal: testpoint_8_internal_clk + reg testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk; + initial + testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk <= 1'b0; + always @(posedge testpoint_8_internal_clk or negedge testpoint_8_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_8 + if (~testpoint_8_internal_reset_) + testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_8_count_0; + reg testpoint_8_goal_0; + initial testpoint_8_goal_0 = 0; + initial testpoint_8_count_0 = 0; + always@(testpoint_8_count_0) begin + if(testpoint_8_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_8_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 8 granted ::: (gnt[8])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 8 granted ::: testpoint_8_goal_0 + testpoint_8_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_8_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_8_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_8 + if (testpoint_8_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[8])) && testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 8 granted ::: testpoint_8_goal_0"); + `endif + if (((gnt[8])) && testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk) + testpoint_8_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk) begin + `endif + testpoint_8_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_8_goal_0_active = (((gnt[8])) && testpoint_got_reset_testpoint_8_internal_reset__with_clock_testpoint_8_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_8_goal_0 (.clk (testpoint_8_internal_clk), .tp(testpoint_8_goal_0_active)); + `else + system_verilog_testpoint svt_Client_8_granted_0 (.clk (testpoint_8_internal_clk), .tp(testpoint_8_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_8_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 9 granted" -clk clk -reset reset_ (gnt[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_9_granted + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // TP__Client_9_granted +`ifdef COVER_OR_TP__Client_9_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 9 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_9_internal_clk = clk; +wire testpoint_9_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_9_internal_reset_ +// Clock signal: testpoint_9_internal_clk + reg testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk; + initial + testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk <= 1'b0; + always @(posedge testpoint_9_internal_clk or negedge testpoint_9_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_9 + if (~testpoint_9_internal_reset_) + testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_9_count_0; + reg testpoint_9_goal_0; + initial testpoint_9_goal_0 = 0; + initial testpoint_9_count_0 = 0; + always@(testpoint_9_count_0) begin + if(testpoint_9_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_9_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: Client 9 granted ::: (gnt[9])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: Client 9 granted ::: testpoint_9_goal_0 + testpoint_9_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_9_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_9_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_9 + if (testpoint_9_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[9])) && testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: Client 9 granted ::: testpoint_9_goal_0"); + `endif + if (((gnt[9])) && testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk) + testpoint_9_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk) begin + `endif + testpoint_9_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_9_goal_0_active = (((gnt[9])) && testpoint_got_reset_testpoint_9_internal_reset__with_clock_testpoint_9_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_9_goal_0 (.clk (testpoint_9_internal_clk), .tp(testpoint_9_goal_0_active)); + `else + system_verilog_testpoint svt_Client_9_granted_0 (.clk (testpoint_9_internal_clk), .tp(testpoint_9_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_9_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_10_internal_clk = clk; +wire testpoint_10_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_10_internal_reset_ +// Clock signal: testpoint_10_internal_clk + reg testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk; + initial + testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk <= 1'b0; + always @(posedge testpoint_10_internal_clk or negedge testpoint_10_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_10 + if (~testpoint_10_internal_reset_) + testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_10_count_0; + reg testpoint_10_goal_0; + initial testpoint_10_goal_0 = 0; + initial testpoint_10_count_0 = 0; + always@(testpoint_10_count_0) begin + if(testpoint_10_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_10_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_ig_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])"); + `endif +//VCS coverage on +//coverage name read_ig_arb ::: All clients requesting at the same time ::: testpoint_10_goal_0 + testpoint_10_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_10_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_10_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_10 + if (testpoint_10_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk) + $display("NVIDIA TESTPOINT: read_ig_arb ::: All clients requesting at the same time ::: testpoint_10_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk) + testpoint_10_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk) begin + `endif + testpoint_10_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_10_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_10_internal_reset__with_clock_testpoint_10_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_10_goal_0 (.clk (testpoint_10_internal_clk), .tp(testpoint_10_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_10_internal_clk), .tp(testpoint_10_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // read_ig_arb +//| &Viva pop dangle_checks_off; +//| &Shell ${ARBGEN2} -m read_eg_arb -n 10 -stdout -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m read_eg_arb -n 10 -stdout -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module read_eg_arb; +module read_eg_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,req5 + ,req6 + ,req7 + ,req8 + ,req9 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,wt5 + ,wt6 + ,wt7 + ,wt8 + ,wt9 + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ,gnt5 + ,gnt6 + ,gnt7 + ,gnt8 + ,gnt9 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input req5; +input req6; +input req7; +input req8; +input req9; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input [7:0] wt5; +input [7:0] wt6; +input [7:0] wt7; +input [7:0] wt8; +input [7:0] wt9; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +output gnt5; +output gnt6; +output gnt7; +output gnt8; +output gnt9; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [9:0] gnt; +reg [9:0] gnt_pre; +reg [9:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [7:0] new_wt_left5; +wire [7:0] new_wt_left6; +wire [7:0] new_wt_left7; +wire [7:0] new_wt_left8; +wire [7:0] new_wt_left9; +wire [9:0] req; +//| &Vector 10 gnt; +//| &Vector 10 wrr_gnt; +//| &Vector 10 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 10 req; +assign req = { + (req9 & (|wt9)) +, (req8 & (|wt8)) +, (req7 & (|wt7)) +, (req6 & (|wt6)) +, (req5 & (|wt5)) +, (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt9 +,gnt8 +,gnt7 +,gnt6 +,gnt5 +,gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_2 +always @( + gnt_pre + ) begin + gnt = gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +assign new_wt_left5[7:0] = wt5 - 1'b1; +assign new_wt_left6[7:0] = wt6 - 1'b1; +assign new_wt_left7[7:0] = wt7 - 1'b1; +assign new_wt_left8[7:0] = wt8 - 1'b1; +assign new_wt_left9[7:0] = wt9 - 1'b1; +//| &Always; +//| _com_3 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + or new_wt_left5 + or new_wt_left6 + or new_wt_left7 + or new_wt_left8 + or new_wt_left9 + ) begin + gnt_pre = {10{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 10'b0000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end + 10'b0000000001 : begin + if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + end + 10'b0000000010 : begin + if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + end + 10'b0000000100 : begin + if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + end + 10'b0000001000 : begin + if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + end + 10'b0000010000 : begin + if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + end + 10'b0000100000 : begin + if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + end + 10'b0001000000 : begin + if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + end + 10'b0010000000 : begin + if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + end + 10'b0100000000 : begin + if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + else if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + end + 10'b1000000000 : begin + if (req[0]) begin + gnt_pre = 10'b0000000001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 10'b0000000010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 10'b0000000100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 10'b0000001000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 10'b0000010000; + wt_left_nxt = new_wt_left4; + end + else if (req[5]) begin + gnt_pre = 10'b0000100000; + wt_left_nxt = new_wt_left5; + end + else if (req[6]) begin + gnt_pre = 10'b0001000000; + wt_left_nxt = new_wt_left6; + end + else if (req[7]) begin + gnt_pre = 10'b0010000000; + wt_left_nxt = new_wt_left7; + end + else if (req[8]) begin + gnt_pre = 10'b0100000000; + wt_left_nxt = new_wt_left8; + end + else if (req[9]) begin + gnt_pre = 10'b1000000000; + wt_left_nxt = new_wt_left9; + end + end +//| ::casedefault gnt_pre 10 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[9:0] = {10{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_1 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {10{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (req != {10{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=10) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,10,0,"gnt not zero one hot") zzz_grant_zero_one_hot_5x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_6x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (|(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_7x (clk, `ASSERT_RESET, (|(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_11_internal_clk = clk; +wire testpoint_11_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_11_internal_reset_ +// Clock signal: testpoint_11_internal_clk + reg testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk; + initial + testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk <= 1'b0; + always @(posedge testpoint_11_internal_clk or negedge testpoint_11_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_11 + if (~testpoint_11_internal_reset_) + testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_11_count_0; + reg testpoint_11_goal_0; + initial testpoint_11_goal_0 = 0; + initial testpoint_11_count_0 = 0; + always@(testpoint_11_count_0) begin + if(testpoint_11_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_11_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 0 granted ::: testpoint_11_goal_0 + testpoint_11_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_11_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_11_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_11 + if (testpoint_11_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 0 granted ::: testpoint_11_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk) + testpoint_11_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk) begin + `endif + testpoint_11_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_11_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_11_internal_reset__with_clock_testpoint_11_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_11_goal_0 (.clk (testpoint_11_internal_clk), .tp(testpoint_11_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_11_internal_clk), .tp(testpoint_11_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_12_internal_clk = clk; +wire testpoint_12_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_12_internal_reset_ +// Clock signal: testpoint_12_internal_clk + reg testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk; + initial + testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk <= 1'b0; + always @(posedge testpoint_12_internal_clk or negedge testpoint_12_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_12 + if (~testpoint_12_internal_reset_) + testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_12_count_0; + reg testpoint_12_goal_0; + initial testpoint_12_goal_0 = 0; + initial testpoint_12_count_0 = 0; + always@(testpoint_12_count_0) begin + if(testpoint_12_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_12_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 1 granted ::: testpoint_12_goal_0 + testpoint_12_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_12_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_12_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_12 + if (testpoint_12_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 1 granted ::: testpoint_12_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk) + testpoint_12_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk) begin + `endif + testpoint_12_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_12_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_12_internal_reset__with_clock_testpoint_12_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_12_goal_0 (.clk (testpoint_12_internal_clk), .tp(testpoint_12_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_12_internal_clk), .tp(testpoint_12_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_13_internal_clk = clk; +wire testpoint_13_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_13_internal_reset_ +// Clock signal: testpoint_13_internal_clk + reg testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk; + initial + testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk <= 1'b0; + always @(posedge testpoint_13_internal_clk or negedge testpoint_13_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_13 + if (~testpoint_13_internal_reset_) + testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_13_count_0; + reg testpoint_13_goal_0; + initial testpoint_13_goal_0 = 0; + initial testpoint_13_count_0 = 0; + always@(testpoint_13_count_0) begin + if(testpoint_13_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_13_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 2 granted ::: testpoint_13_goal_0 + testpoint_13_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_13_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_13_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_13 + if (testpoint_13_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 2 granted ::: testpoint_13_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk) + testpoint_13_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk) begin + `endif + testpoint_13_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_13_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_13_internal_reset__with_clock_testpoint_13_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_13_goal_0 (.clk (testpoint_13_internal_clk), .tp(testpoint_13_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_13_internal_clk), .tp(testpoint_13_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_14_internal_clk = clk; +wire testpoint_14_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_14_internal_reset_ +// Clock signal: testpoint_14_internal_clk + reg testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk; + initial + testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk <= 1'b0; + always @(posedge testpoint_14_internal_clk or negedge testpoint_14_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_14 + if (~testpoint_14_internal_reset_) + testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_14_count_0; + reg testpoint_14_goal_0; + initial testpoint_14_goal_0 = 0; + initial testpoint_14_count_0 = 0; + always@(testpoint_14_count_0) begin + if(testpoint_14_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_14_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 3 granted ::: testpoint_14_goal_0 + testpoint_14_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_14_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_14_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_14 + if (testpoint_14_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 3 granted ::: testpoint_14_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk) + testpoint_14_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk) begin + `endif + testpoint_14_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_14_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_14_internal_reset__with_clock_testpoint_14_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_14_goal_0 (.clk (testpoint_14_internal_clk), .tp(testpoint_14_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_14_internal_clk), .tp(testpoint_14_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_15_internal_clk = clk; +wire testpoint_15_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_15_internal_reset_ +// Clock signal: testpoint_15_internal_clk + reg testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk; + initial + testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk <= 1'b0; + always @(posedge testpoint_15_internal_clk or negedge testpoint_15_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_15 + if (~testpoint_15_internal_reset_) + testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_15_count_0; + reg testpoint_15_goal_0; + initial testpoint_15_goal_0 = 0; + initial testpoint_15_count_0 = 0; + always@(testpoint_15_count_0) begin + if(testpoint_15_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_15_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 4 granted ::: testpoint_15_goal_0 + testpoint_15_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_15_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_15_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_15 + if (testpoint_15_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 4 granted ::: testpoint_15_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk) + testpoint_15_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk) begin + `endif + testpoint_15_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_15_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_15_internal_reset__with_clock_testpoint_15_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_15_goal_0 (.clk (testpoint_15_internal_clk), .tp(testpoint_15_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_15_internal_clk), .tp(testpoint_15_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 5 granted" -clk clk -reset reset_ (gnt[5]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_5_granted + `define COVER_OR_TP__Client_5_granted_OR_COVER + `endif // TP__Client_5_granted +`ifdef COVER_OR_TP__Client_5_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 5 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_16_internal_clk = clk; +wire testpoint_16_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_16_internal_reset_ +// Clock signal: testpoint_16_internal_clk + reg testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk; + initial + testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk <= 1'b0; + always @(posedge testpoint_16_internal_clk or negedge testpoint_16_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_16 + if (~testpoint_16_internal_reset_) + testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_16_count_0; + reg testpoint_16_goal_0; + initial testpoint_16_goal_0 = 0; + initial testpoint_16_count_0 = 0; + always@(testpoint_16_count_0) begin + if(testpoint_16_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_16_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 5 granted ::: (gnt[5])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 5 granted ::: testpoint_16_goal_0 + testpoint_16_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_16_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_16_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_16 + if (testpoint_16_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[5])) && testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 5 granted ::: testpoint_16_goal_0"); + `endif + if (((gnt[5])) && testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk) + testpoint_16_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk) begin + `endif + testpoint_16_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_16_goal_0_active = (((gnt[5])) && testpoint_got_reset_testpoint_16_internal_reset__with_clock_testpoint_16_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_16_goal_0 (.clk (testpoint_16_internal_clk), .tp(testpoint_16_goal_0_active)); + `else + system_verilog_testpoint svt_Client_5_granted_0 (.clk (testpoint_16_internal_clk), .tp(testpoint_16_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_5_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 6 granted" -clk clk -reset reset_ (gnt[6]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_6_granted + `define COVER_OR_TP__Client_6_granted_OR_COVER + `endif // TP__Client_6_granted +`ifdef COVER_OR_TP__Client_6_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 6 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_17_internal_clk = clk; +wire testpoint_17_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_17_internal_reset_ +// Clock signal: testpoint_17_internal_clk + reg testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk; + initial + testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk <= 1'b0; + always @(posedge testpoint_17_internal_clk or negedge testpoint_17_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_17 + if (~testpoint_17_internal_reset_) + testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_17_count_0; + reg testpoint_17_goal_0; + initial testpoint_17_goal_0 = 0; + initial testpoint_17_count_0 = 0; + always@(testpoint_17_count_0) begin + if(testpoint_17_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_17_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 6 granted ::: (gnt[6])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 6 granted ::: testpoint_17_goal_0 + testpoint_17_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_17_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_17_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_17 + if (testpoint_17_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[6])) && testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 6 granted ::: testpoint_17_goal_0"); + `endif + if (((gnt[6])) && testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk) + testpoint_17_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk) begin + `endif + testpoint_17_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_17_goal_0_active = (((gnt[6])) && testpoint_got_reset_testpoint_17_internal_reset__with_clock_testpoint_17_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_17_goal_0 (.clk (testpoint_17_internal_clk), .tp(testpoint_17_goal_0_active)); + `else + system_verilog_testpoint svt_Client_6_granted_0 (.clk (testpoint_17_internal_clk), .tp(testpoint_17_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_6_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 7 granted" -clk clk -reset reset_ (gnt[7]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_7_granted + `define COVER_OR_TP__Client_7_granted_OR_COVER + `endif // TP__Client_7_granted +`ifdef COVER_OR_TP__Client_7_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 7 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_18_internal_clk = clk; +wire testpoint_18_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_18_internal_reset_ +// Clock signal: testpoint_18_internal_clk + reg testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk; + initial + testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk <= 1'b0; + always @(posedge testpoint_18_internal_clk or negedge testpoint_18_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_18 + if (~testpoint_18_internal_reset_) + testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_18_count_0; + reg testpoint_18_goal_0; + initial testpoint_18_goal_0 = 0; + initial testpoint_18_count_0 = 0; + always@(testpoint_18_count_0) begin + if(testpoint_18_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_18_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 7 granted ::: (gnt[7])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 7 granted ::: testpoint_18_goal_0 + testpoint_18_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_18_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_18_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_18 + if (testpoint_18_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[7])) && testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 7 granted ::: testpoint_18_goal_0"); + `endif + if (((gnt[7])) && testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk) + testpoint_18_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk) begin + `endif + testpoint_18_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_18_goal_0_active = (((gnt[7])) && testpoint_got_reset_testpoint_18_internal_reset__with_clock_testpoint_18_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_18_goal_0 (.clk (testpoint_18_internal_clk), .tp(testpoint_18_goal_0_active)); + `else + system_verilog_testpoint svt_Client_7_granted_0 (.clk (testpoint_18_internal_clk), .tp(testpoint_18_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_7_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 8 granted" -clk clk -reset reset_ (gnt[8]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_8_granted + `define COVER_OR_TP__Client_8_granted_OR_COVER + `endif // TP__Client_8_granted +`ifdef COVER_OR_TP__Client_8_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 8 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_19_internal_clk = clk; +wire testpoint_19_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_19_internal_reset_ +// Clock signal: testpoint_19_internal_clk + reg testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk; + initial + testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk <= 1'b0; + always @(posedge testpoint_19_internal_clk or negedge testpoint_19_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_19 + if (~testpoint_19_internal_reset_) + testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_19_count_0; + reg testpoint_19_goal_0; + initial testpoint_19_goal_0 = 0; + initial testpoint_19_count_0 = 0; + always@(testpoint_19_count_0) begin + if(testpoint_19_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_19_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 8 granted ::: (gnt[8])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 8 granted ::: testpoint_19_goal_0 + testpoint_19_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_19_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_19_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_19 + if (testpoint_19_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[8])) && testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 8 granted ::: testpoint_19_goal_0"); + `endif + if (((gnt[8])) && testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk) + testpoint_19_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk) begin + `endif + testpoint_19_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_19_goal_0_active = (((gnt[8])) && testpoint_got_reset_testpoint_19_internal_reset__with_clock_testpoint_19_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_19_goal_0 (.clk (testpoint_19_internal_clk), .tp(testpoint_19_goal_0_active)); + `else + system_verilog_testpoint svt_Client_8_granted_0 (.clk (testpoint_19_internal_clk), .tp(testpoint_19_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_8_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 9 granted" -clk clk -reset reset_ (gnt[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_9_granted + `define COVER_OR_TP__Client_9_granted_OR_COVER + `endif // TP__Client_9_granted +`ifdef COVER_OR_TP__Client_9_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 9 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_20_internal_clk = clk; +wire testpoint_20_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_20_internal_reset_ +// Clock signal: testpoint_20_internal_clk + reg testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk; + initial + testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk <= 1'b0; + always @(posedge testpoint_20_internal_clk or negedge testpoint_20_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_20 + if (~testpoint_20_internal_reset_) + testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_20_count_0; + reg testpoint_20_goal_0; + initial testpoint_20_goal_0 = 0; + initial testpoint_20_count_0 = 0; + always@(testpoint_20_count_0) begin + if(testpoint_20_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_20_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: Client 9 granted ::: (gnt[9])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: Client 9 granted ::: testpoint_20_goal_0 + testpoint_20_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_20_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_20_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_20 + if (testpoint_20_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[9])) && testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: Client 9 granted ::: testpoint_20_goal_0"); + `endif + if (((gnt[9])) && testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk) + testpoint_20_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk) begin + `endif + testpoint_20_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_20_goal_0_active = (((gnt[9])) && testpoint_got_reset_testpoint_20_internal_reset__with_clock_testpoint_20_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_20_goal_0 (.clk (testpoint_20_internal_clk), .tp(testpoint_20_goal_0_active)); + `else + system_verilog_testpoint svt_Client_9_granted_0 (.clk (testpoint_20_internal_clk), .tp(testpoint_20_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_9_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_21_internal_clk = clk; +wire testpoint_21_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_21_internal_reset_ +// Clock signal: testpoint_21_internal_clk + reg testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk; + initial + testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk <= 1'b0; + always @(posedge testpoint_21_internal_clk or negedge testpoint_21_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_21 + if (~testpoint_21_internal_reset_) + testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_21_count_0; + reg testpoint_21_goal_0; + initial testpoint_21_goal_0 = 0; + initial testpoint_21_count_0 = 0; + always@(testpoint_21_count_0) begin + if(testpoint_21_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_21_goal_0 != 1'b1) + $display("TESTPOINT_HIT: read_eg_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])"); + `endif +//VCS coverage on +//coverage name read_eg_arb ::: All clients requesting at the same time ::: testpoint_21_goal_0 + testpoint_21_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_21_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_21_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_21 + if (testpoint_21_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk) + $display("NVIDIA TESTPOINT: read_eg_arb ::: All clients requesting at the same time ::: testpoint_21_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk) + testpoint_21_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk) begin + `endif + testpoint_21_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_21_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4] && req[5] && req[6] && req[7] && req[8] && req[9])) && testpoint_got_reset_testpoint_21_internal_reset__with_clock_testpoint_21_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_21_goal_0 (.clk (testpoint_21_internal_clk), .tp(testpoint_21_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_21_internal_clk), .tp(testpoint_21_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // read_eg_arb +//| &Viva pop dangle_checks_off; +//| &Shell ${ARBGEN2} -m write_ig_arb -n 5 -stdout -gnt_busy -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m write_ig_arb -n 5 -stdout -gnt_busy -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module write_ig_arb; +module write_ig_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,gnt_busy + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input gnt_busy; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [4:0] gnt; +reg [4:0] gnt_pre; +reg [4:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [4:0] req; +//| &Vector 5 gnt; +//| &Vector 5 wrr_gnt; +//| &Vector 5 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 5 req; +assign req = { + (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_4 +always @( + gnt_busy + or gnt_pre + ) begin + gnt = {5{!gnt_busy}} & gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +//| &Always; +//| _com_5 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + ) begin + gnt_pre = {5{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 5'b00000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end + 5'b00001 : begin + if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + end + 5'b00010 : begin + if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + end + 5'b00100 : begin + if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + end + 5'b01000 : begin + if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + end + 5'b10000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end +//| ::casedefault gnt_pre 5 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[4:0] = {5{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_2 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {5{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (!gnt_busy & req != {5{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=5) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,5,0,"gnt not zero one hot") zzz_grant_zero_one_hot_8x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_9x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (!gnt_busy & |(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_10x (clk, `ASSERT_RESET, (!gnt_busy & |(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=gnt_when_busy) "gnt when gnt_busy " (gnt_busy & |gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt when gnt_busy ") zzz_gnt_when_busy_11x (clk, `ASSERT_RESET, (gnt_busy & |gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_22_internal_clk = clk; +wire testpoint_22_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_22_internal_reset_ +// Clock signal: testpoint_22_internal_clk + reg testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk; + initial + testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk <= 1'b0; + always @(posedge testpoint_22_internal_clk or negedge testpoint_22_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_22 + if (~testpoint_22_internal_reset_) + testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_22_count_0; + reg testpoint_22_goal_0; + initial testpoint_22_goal_0 = 0; + initial testpoint_22_count_0 = 0; + always@(testpoint_22_count_0) begin + if(testpoint_22_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_22_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 0 granted ::: testpoint_22_goal_0 + testpoint_22_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_22_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_22_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_22 + if (testpoint_22_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 0 granted ::: testpoint_22_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk) + testpoint_22_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk) begin + `endif + testpoint_22_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_22_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_22_internal_reset__with_clock_testpoint_22_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_22_goal_0 (.clk (testpoint_22_internal_clk), .tp(testpoint_22_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_22_internal_clk), .tp(testpoint_22_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_23_internal_clk = clk; +wire testpoint_23_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_23_internal_reset_ +// Clock signal: testpoint_23_internal_clk + reg testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk; + initial + testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk <= 1'b0; + always @(posedge testpoint_23_internal_clk or negedge testpoint_23_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_23 + if (~testpoint_23_internal_reset_) + testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_23_count_0; + reg testpoint_23_goal_0; + initial testpoint_23_goal_0 = 0; + initial testpoint_23_count_0 = 0; + always@(testpoint_23_count_0) begin + if(testpoint_23_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_23_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 1 granted ::: testpoint_23_goal_0 + testpoint_23_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_23_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_23_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_23 + if (testpoint_23_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 1 granted ::: testpoint_23_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk) + testpoint_23_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk) begin + `endif + testpoint_23_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_23_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_23_internal_reset__with_clock_testpoint_23_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_23_goal_0 (.clk (testpoint_23_internal_clk), .tp(testpoint_23_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_23_internal_clk), .tp(testpoint_23_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_24_internal_clk = clk; +wire testpoint_24_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_24_internal_reset_ +// Clock signal: testpoint_24_internal_clk + reg testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk; + initial + testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk <= 1'b0; + always @(posedge testpoint_24_internal_clk or negedge testpoint_24_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_24 + if (~testpoint_24_internal_reset_) + testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_24_count_0; + reg testpoint_24_goal_0; + initial testpoint_24_goal_0 = 0; + initial testpoint_24_count_0 = 0; + always@(testpoint_24_count_0) begin + if(testpoint_24_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_24_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 2 granted ::: testpoint_24_goal_0 + testpoint_24_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_24_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_24_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_24 + if (testpoint_24_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 2 granted ::: testpoint_24_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk) + testpoint_24_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk) begin + `endif + testpoint_24_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_24_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_24_internal_reset__with_clock_testpoint_24_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_24_goal_0 (.clk (testpoint_24_internal_clk), .tp(testpoint_24_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_24_internal_clk), .tp(testpoint_24_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_25_internal_clk = clk; +wire testpoint_25_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_25_internal_reset_ +// Clock signal: testpoint_25_internal_clk + reg testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk; + initial + testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk <= 1'b0; + always @(posedge testpoint_25_internal_clk or negedge testpoint_25_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_25 + if (~testpoint_25_internal_reset_) + testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_25_count_0; + reg testpoint_25_goal_0; + initial testpoint_25_goal_0 = 0; + initial testpoint_25_count_0 = 0; + always@(testpoint_25_count_0) begin + if(testpoint_25_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_25_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 3 granted ::: testpoint_25_goal_0 + testpoint_25_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_25_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_25_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_25 + if (testpoint_25_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 3 granted ::: testpoint_25_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk) + testpoint_25_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk) begin + `endif + testpoint_25_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_25_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_25_internal_reset__with_clock_testpoint_25_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_25_goal_0 (.clk (testpoint_25_internal_clk), .tp(testpoint_25_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_25_internal_clk), .tp(testpoint_25_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_26_internal_clk = clk; +wire testpoint_26_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_26_internal_reset_ +// Clock signal: testpoint_26_internal_clk + reg testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk; + initial + testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk <= 1'b0; + always @(posedge testpoint_26_internal_clk or negedge testpoint_26_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_26 + if (~testpoint_26_internal_reset_) + testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_26_count_0; + reg testpoint_26_goal_0; + initial testpoint_26_goal_0 = 0; + initial testpoint_26_count_0 = 0; + always@(testpoint_26_count_0) begin + if(testpoint_26_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_26_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: Client 4 granted ::: testpoint_26_goal_0 + testpoint_26_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_26_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_26_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_26 + if (testpoint_26_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: Client 4 granted ::: testpoint_26_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk) + testpoint_26_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk) begin + `endif + testpoint_26_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_26_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_26_internal_reset__with_clock_testpoint_26_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_26_goal_0 (.clk (testpoint_26_internal_clk), .tp(testpoint_26_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_26_internal_clk), .tp(testpoint_26_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_27_internal_clk = clk; +wire testpoint_27_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_27_internal_reset_ +// Clock signal: testpoint_27_internal_clk + reg testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk; + initial + testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk <= 1'b0; + always @(posedge testpoint_27_internal_clk or negedge testpoint_27_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_27 + if (~testpoint_27_internal_reset_) + testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_27_count_0; + reg testpoint_27_goal_0; + initial testpoint_27_goal_0 = 0; + initial testpoint_27_count_0 = 0; + always@(testpoint_27_count_0) begin + if(testpoint_27_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_27_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_ig_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4])"); + `endif +//VCS coverage on +//coverage name write_ig_arb ::: All clients requesting at the same time ::: testpoint_27_goal_0 + testpoint_27_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_27_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_27_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_27 + if (testpoint_27_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk) + $display("NVIDIA TESTPOINT: write_ig_arb ::: All clients requesting at the same time ::: testpoint_27_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk) + testpoint_27_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk) begin + `endif + testpoint_27_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_27_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_27_internal_reset__with_clock_testpoint_27_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_27_goal_0 (.clk (testpoint_27_internal_clk), .tp(testpoint_27_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_27_internal_clk), .tp(testpoint_27_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // write_ig_arb +//| &Viva pop dangle_checks_off; +//| &Shell ${ARBGEN2} -m write_eg_arb -n 5 -stdout -t wrr -wt_width 8 ; +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// arbgen2 -m write_eg_arb -n 5 -stdout -t wrr -wt_width 8 +// TYPE: wrr +`include "simulate_x_tick.vh" +//| &Viva push dangle_checks_off; +//| &Viva width_learning_on; +//| &Module write_eg_arb; +module write_eg_arb ( + req0 + ,req1 + ,req2 + ,req3 + ,req4 + ,wt0 + ,wt1 + ,wt2 + ,wt3 + ,wt4 + ,clk + ,reset_ + ,gnt0 + ,gnt1 + ,gnt2 + ,gnt3 + ,gnt4 + ); +//Declaring ports +input req0; +input req1; +input req2; +input req3; +input req4; +input [7:0] wt0; +input [7:0] wt1; +input [7:0] wt2; +input [7:0] wt3; +input [7:0] wt4; +input clk; +input reset_; +output gnt0; +output gnt1; +output gnt2; +output gnt3; +output gnt4; +//Declaring clock and reset +//| &Clock push clk; +//| &Reset push reset_; +//Declaring registers and wires +//| &Regs; +reg [4:0] gnt; +reg [4:0] gnt_pre; +reg [4:0] wrr_gnt; +reg [7:0] wt_left; +reg [7:0] wt_left_nxt; +//| &Wires; +wire [7:0] new_wt_left0; +wire [7:0] new_wt_left1; +wire [7:0] new_wt_left2; +wire [7:0] new_wt_left3; +wire [7:0] new_wt_left4; +wire [4:0] req; +//| &Vector 5 gnt; +//| &Vector 5 wrr_gnt; +//| &Vector 5 gnt_pre; +//| &Vector 8 wt_left; +//| &Vector 8 wt_left_nxt; +//| &Vector 5 req; +assign req = { + (req4 & (|wt4)) +, (req3 & (|wt3)) +, (req2 & (|wt2)) +, (req1 & (|wt1)) +, (req0 & (|wt0)) +}; +assign { + gnt4 +,gnt3 +,gnt2 +,gnt1 +,gnt0 +} = gnt; +//| &Always; +//| _com_6 +always @( + gnt_pre + ) begin + gnt = gnt_pre; +//| &End; +end +// verilint 69 off - Case statement without default clause, but all the cases are covered +// verilint 71 off - Case statement without default clause +// verilint 264 off - Not all possible cases covered +// verilint 484 off - Possible loss of carry/borrow in addition/subtraction +assign new_wt_left0[7:0] = wt0 - 1'b1; +assign new_wt_left1[7:0] = wt1 - 1'b1; +assign new_wt_left2[7:0] = wt2 - 1'b1; +assign new_wt_left3[7:0] = wt3 - 1'b1; +assign new_wt_left4[7:0] = wt4 - 1'b1; +//| &Always; +//| _com_7 +always @( + wt_left + or req + or wrr_gnt + or new_wt_left0 + or new_wt_left1 + or new_wt_left2 + or new_wt_left3 + or new_wt_left4 + ) begin + gnt_pre = {5{1'b0}}; + wt_left_nxt = wt_left; + if (wt_left == 0 | !(|(req & wrr_gnt)) ) begin + case (wrr_gnt) + 5'b00000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end + 5'b00001 : begin + if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + end + 5'b00010 : begin + if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + end + 5'b00100 : begin + if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + end + 5'b01000 : begin + if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + else if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + end + 5'b10000 : begin + if (req[0]) begin + gnt_pre = 5'b00001; + wt_left_nxt = new_wt_left0; + end + else if (req[1]) begin + gnt_pre = 5'b00010; + wt_left_nxt = new_wt_left1; + end + else if (req[2]) begin + gnt_pre = 5'b00100; + wt_left_nxt = new_wt_left2; + end + else if (req[3]) begin + gnt_pre = 5'b01000; + wt_left_nxt = new_wt_left3; + end + else if (req[4]) begin + gnt_pre = 5'b10000; + wt_left_nxt = new_wt_left4; + end + end +//| ::casedefault gnt_pre 5 wt_left_nxt 8; +//VCS coverage off + default : begin + gnt_pre[4:0] = {5{`x_or_0}}; + wt_left_nxt[7:0] = {8{`x_or_0}}; + end +//VCS coverage on + endcase + end else begin + gnt_pre = wrr_gnt; + wt_left_nxt = wt_left - 1'b1; + end +//| &End; +end +// verilint 69 on - Case statement without default clause, but all the cases are covered +// verilint 71 on - Case statement without default clause +// verilint 264 on - Not all possible cases covered +// verilint 484 on - Possible loss of carry/borrow in addition/subtraction +//| &Always posedge; +//| _seq_3 +always @(posedge clk or negedge reset_) begin + if (!reset_) begin + wrr_gnt <= {5{1'b0}}; + wt_left <= {8{1'b0}}; + end else begin + if (req != {5{1'b0}}) begin + wrr_gnt <= gnt; + wt_left <= wt_left_nxt; + end +//| &End; + end +end +//end of always block +//| ::assert zero_one_hot #(name=grant_zero_one_hot,width=5) "gnt not zero one hot" (gnt); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_zero_one_hot #(0,5,0,"gnt not zero one hot") zzz_grant_zero_one_hot_12x (clk, `ASSERT_RESET, (gnt)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=grant_to_no_req) "gnt to a non requesting client" (|(~req & gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"gnt to a non requesting client") zzz_grant_to_no_req_13x (clk, `ASSERT_RESET, (|(~req & gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| ::assert never #(name=no_gnt_when_expected) "no gnt even if at least 1 client requesting " (|(req) & !(|gnt)); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET reset_ +`else +`ifdef SYNTHESIS +`define ASSERT_RESET reset_ +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === reset_) ? 1'b0 : reset_) +`else +`define ASSERT_RESET ((1'bx === reset_) ? 1'b1 : reset_) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no gnt even if at least 1 client requesting ") zzz_no_gnt_when_expected_14x (clk, `ASSERT_RESET, (|(req) & !(|gnt))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//| &Viva push ifdef_ignore_on; +`ifdef COVER +//| ::testpoint -autogen true -name "Client 0 granted" -clk clk -reset reset_ (gnt[0]); +//| &Force internal /^testpoint_/; +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_0_granted + `define COVER_OR_TP__Client_0_granted_OR_COVER + `endif // TP__Client_0_granted +`ifdef COVER_OR_TP__Client_0_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 0 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_28_internal_clk = clk; +wire testpoint_28_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_28_internal_reset_ +// Clock signal: testpoint_28_internal_clk + reg testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk; + initial + testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk <= 1'b0; + always @(posedge testpoint_28_internal_clk or negedge testpoint_28_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_28 + if (~testpoint_28_internal_reset_) + testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_28_count_0; + reg testpoint_28_goal_0; + initial testpoint_28_goal_0 = 0; + initial testpoint_28_count_0 = 0; + always@(testpoint_28_count_0) begin + if(testpoint_28_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_28_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 0 granted ::: (gnt[0])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 0 granted ::: testpoint_28_goal_0 + testpoint_28_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_28_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_28_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_28 + if (testpoint_28_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[0])) && testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 0 granted ::: testpoint_28_goal_0"); + `endif + if (((gnt[0])) && testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk) + testpoint_28_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk) begin + `endif + testpoint_28_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_28_goal_0_active = (((gnt[0])) && testpoint_got_reset_testpoint_28_internal_reset__with_clock_testpoint_28_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_28_goal_0 (.clk (testpoint_28_internal_clk), .tp(testpoint_28_goal_0_active)); + `else + system_verilog_testpoint svt_Client_0_granted_0 (.clk (testpoint_28_internal_clk), .tp(testpoint_28_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_0_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 1 granted" -clk clk -reset reset_ (gnt[1]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_1_granted + `define COVER_OR_TP__Client_1_granted_OR_COVER + `endif // TP__Client_1_granted +`ifdef COVER_OR_TP__Client_1_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 1 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_29_internal_clk = clk; +wire testpoint_29_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_29_internal_reset_ +// Clock signal: testpoint_29_internal_clk + reg testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk; + initial + testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk <= 1'b0; + always @(posedge testpoint_29_internal_clk or negedge testpoint_29_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_29 + if (~testpoint_29_internal_reset_) + testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_29_count_0; + reg testpoint_29_goal_0; + initial testpoint_29_goal_0 = 0; + initial testpoint_29_count_0 = 0; + always@(testpoint_29_count_0) begin + if(testpoint_29_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_29_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 1 granted ::: (gnt[1])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 1 granted ::: testpoint_29_goal_0 + testpoint_29_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_29_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_29_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_29 + if (testpoint_29_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[1])) && testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 1 granted ::: testpoint_29_goal_0"); + `endif + if (((gnt[1])) && testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk) + testpoint_29_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk) begin + `endif + testpoint_29_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_29_goal_0_active = (((gnt[1])) && testpoint_got_reset_testpoint_29_internal_reset__with_clock_testpoint_29_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_29_goal_0 (.clk (testpoint_29_internal_clk), .tp(testpoint_29_goal_0_active)); + `else + system_verilog_testpoint svt_Client_1_granted_0 (.clk (testpoint_29_internal_clk), .tp(testpoint_29_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_1_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 2 granted" -clk clk -reset reset_ (gnt[2]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_2_granted + `define COVER_OR_TP__Client_2_granted_OR_COVER + `endif // TP__Client_2_granted +`ifdef COVER_OR_TP__Client_2_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 2 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_30_internal_clk = clk; +wire testpoint_30_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_30_internal_reset_ +// Clock signal: testpoint_30_internal_clk + reg testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk; + initial + testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk <= 1'b0; + always @(posedge testpoint_30_internal_clk or negedge testpoint_30_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_30 + if (~testpoint_30_internal_reset_) + testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_30_count_0; + reg testpoint_30_goal_0; + initial testpoint_30_goal_0 = 0; + initial testpoint_30_count_0 = 0; + always@(testpoint_30_count_0) begin + if(testpoint_30_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_30_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 2 granted ::: (gnt[2])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 2 granted ::: testpoint_30_goal_0 + testpoint_30_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_30_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_30_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_30 + if (testpoint_30_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[2])) && testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 2 granted ::: testpoint_30_goal_0"); + `endif + if (((gnt[2])) && testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk) + testpoint_30_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk) begin + `endif + testpoint_30_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_30_goal_0_active = (((gnt[2])) && testpoint_got_reset_testpoint_30_internal_reset__with_clock_testpoint_30_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_30_goal_0 (.clk (testpoint_30_internal_clk), .tp(testpoint_30_goal_0_active)); + `else + system_verilog_testpoint svt_Client_2_granted_0 (.clk (testpoint_30_internal_clk), .tp(testpoint_30_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_2_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 3 granted" -clk clk -reset reset_ (gnt[3]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_3_granted + `define COVER_OR_TP__Client_3_granted_OR_COVER + `endif // TP__Client_3_granted +`ifdef COVER_OR_TP__Client_3_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 3 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_31_internal_clk = clk; +wire testpoint_31_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_31_internal_reset_ +// Clock signal: testpoint_31_internal_clk + reg testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk; + initial + testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk <= 1'b0; + always @(posedge testpoint_31_internal_clk or negedge testpoint_31_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_31 + if (~testpoint_31_internal_reset_) + testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_31_count_0; + reg testpoint_31_goal_0; + initial testpoint_31_goal_0 = 0; + initial testpoint_31_count_0 = 0; + always@(testpoint_31_count_0) begin + if(testpoint_31_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_31_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 3 granted ::: (gnt[3])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 3 granted ::: testpoint_31_goal_0 + testpoint_31_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_31_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_31_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_31 + if (testpoint_31_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[3])) && testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 3 granted ::: testpoint_31_goal_0"); + `endif + if (((gnt[3])) && testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk) + testpoint_31_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk) begin + `endif + testpoint_31_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_31_goal_0_active = (((gnt[3])) && testpoint_got_reset_testpoint_31_internal_reset__with_clock_testpoint_31_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_31_goal_0 (.clk (testpoint_31_internal_clk), .tp(testpoint_31_goal_0_active)); + `else + system_verilog_testpoint svt_Client_3_granted_0 (.clk (testpoint_31_internal_clk), .tp(testpoint_31_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_3_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "Client 4 granted" -clk clk -reset reset_ (gnt[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // COVER + `ifdef TP__Client_4_granted + `define COVER_OR_TP__Client_4_granted_OR_COVER + `endif // TP__Client_4_granted +`ifdef COVER_OR_TP__Client_4_granted_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="Client 4 granted" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_32_internal_clk = clk; +wire testpoint_32_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_32_internal_reset_ +// Clock signal: testpoint_32_internal_clk + reg testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk; + initial + testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk <= 1'b0; + always @(posedge testpoint_32_internal_clk or negedge testpoint_32_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_32 + if (~testpoint_32_internal_reset_) + testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_32_count_0; + reg testpoint_32_goal_0; + initial testpoint_32_goal_0 = 0; + initial testpoint_32_count_0 = 0; + always@(testpoint_32_count_0) begin + if(testpoint_32_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_32_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: Client 4 granted ::: (gnt[4])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: Client 4 granted ::: testpoint_32_goal_0 + testpoint_32_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_32_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_32_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_32 + if (testpoint_32_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((gnt[4])) && testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: Client 4 granted ::: testpoint_32_goal_0"); + `endif + if (((gnt[4])) && testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk) + testpoint_32_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk) begin + `endif + testpoint_32_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_32_goal_0_active = (((gnt[4])) && testpoint_got_reset_testpoint_32_internal_reset__with_clock_testpoint_32_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_32_goal_0 (.clk (testpoint_32_internal_clk), .tp(testpoint_32_goal_0_active)); + `else + system_verilog_testpoint svt_Client_4_granted_0 (.clk (testpoint_32_internal_clk), .tp(testpoint_32_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__Client_4_granted_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +//| ::testpoint -autogen true -name "All clients requesting at the same time" -clk clk -reset reset_ ( req[0] && req[1] && req[2] && req[3] && req[4]); +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // COVER + `ifdef TP__All_clients_requesting_at_the_same_time + `define COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER + `endif // TP__All_clients_requesting_at_the_same_time +`ifdef COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME="All clients requesting at the same time" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_33_internal_clk = clk; +wire testpoint_33_internal_reset_ = reset_; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_33_internal_reset_ +// Clock signal: testpoint_33_internal_clk + reg testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk; + initial + testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk <= 1'b0; + always @(posedge testpoint_33_internal_clk or negedge testpoint_33_internal_reset_) begin: HAS_RETENTION_TESTPOINT_RESET_33 + if (~testpoint_33_internal_reset_) + testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_33_count_0; + reg testpoint_33_goal_0; + initial testpoint_33_goal_0 = 0; + initial testpoint_33_count_0 = 0; + always@(testpoint_33_count_0) begin + if(testpoint_33_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_33_goal_0 != 1'b1) + $display("TESTPOINT_HIT: write_eg_arb ::: All clients requesting at the same time ::: ( req[0] && req[1] && req[2] && req[3] && req[4])"); + `endif +//VCS coverage on +//coverage name write_eg_arb ::: All clients requesting at the same time ::: testpoint_33_goal_0 + testpoint_33_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_33_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_33_internal_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_33 + if (testpoint_33_internal_reset_) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk) + $display("NVIDIA TESTPOINT: write_eg_arb ::: All clients requesting at the same time ::: testpoint_33_goal_0"); + `endif + if ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk) + testpoint_33_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk) begin + `endif + testpoint_33_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_33_goal_0_active = ((( req[0] && req[1] && req[2] && req[3] && req[4])) && testpoint_got_reset_testpoint_33_internal_reset__with_clock_testpoint_33_internal_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_33_goal_0 (.clk (testpoint_33_internal_clk), .tp(testpoint_33_goal_0_active)); + `else + system_verilog_testpoint svt_All_clients_requesting_at_the_same_time_0 (.clk (testpoint_33_internal_clk), .tp(testpoint_33_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP__All_clients_requesting_at_the_same_time_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`endif +//| &Viva pop ifdef_ignore_on; +//| &Clock pop clk; +//| &Reset pop reset_; +endmodule // write_eg_arb +//| &Viva pop dangle_checks_off; diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.swl b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.swl new file mode 100644 index 0000000..2b30f4f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.swl @@ -0,0 +1,4 @@ +waive -regexp -file NV_NVDLA_NOCIF_DRAM_READ_eg.v -msg "Instance u_read_eg_arb(Master: read_eg_arb) has too few ports.*" -rule W210 +waive -regexp -file NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v -msg "Instance u_write_ig_arb(Master: write_ig_arb) has too few ports.*" -rule W210 +waive -regexp -file NV_NVDLA_NOCIF_DRAM_read.v -msg "Instance u_cq(Master: NV_NVDLA_NOCIF_DRAM_READ_cq) has too few ports.*" -rule W210 +waive -regexp -file NV_NVDLA_NOCIF_DRAM_write.v -msg "Instance u_cq(Master: NV_NVDLA_NOCIF_DRAM_WRITE_cq) has too few ports.*" -rule W210 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.swl.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.swl.vcp new file mode 100644 index 0000000..2b30f4f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.swl.vcp @@ -0,0 +1,4 @@ +waive -regexp -file NV_NVDLA_NOCIF_DRAM_READ_eg.v -msg "Instance u_read_eg_arb(Master: read_eg_arb) has too few ports.*" -rule W210 +waive -regexp -file NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v -msg "Instance u_write_ig_arb(Master: write_ig_arb) has too few ports.*" -rule W210 +waive -regexp -file NV_NVDLA_NOCIF_DRAM_read.v -msg "Instance u_cq(Master: NV_NVDLA_NOCIF_DRAM_READ_cq) has too few ports.*" -rule W210 +waive -regexp -file NV_NVDLA_NOCIF_DRAM_write.v -msg "Instance u_cq(Master: NV_NVDLA_NOCIF_DRAM_WRITE_cq) has too few ports.*" -rule W210 diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.v b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.v new file mode 100644 index 0000000..6dc6c3f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.v @@ -0,0 +1,415 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_nocif.v +module NV_NVDLA_nocif ( + nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd +//: my $k = 7; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print(" ,client${i}2mcif_rd_req_valid\n"); +//: print(" ,client${i}2mcif_rd_req_pd\n"); +//: print(" ,client${i}2mcif_rd_req_ready\n"); +//: print(" ,mcif2client${i}_rd_rsp_valid\n"); +//: print(" ,mcif2client${i}_rd_rsp_pd\n"); +//: print(" ,mcif2client${i}_rd_rsp_ready\n"); +//: print(" ,client${i}2mcif_lat_fifo_depth\n"); +//: print(" ,client${i}2mcif_rd_axid\n"); +//: } +//: my $k = 3; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_wr_req_pd\n"); +//: print(" ,client${i}2mcif_wr_req_valid\n"); +//: print(" ,client${i}2mcif_wr_req_ready\n"); +//: print(" ,mcif2client${i}_wr_rsp_complete\n"); +//: print(" ,client${i}2mcif_wr_axid\n"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,client02mcif_rd_cdt_lat_fifo_pop + ,client02mcif_rd_req_valid + ,client02mcif_rd_req_pd + ,client02mcif_rd_req_ready + ,mcif2client0_rd_rsp_valid + ,mcif2client0_rd_rsp_pd + ,mcif2client0_rd_rsp_ready + ,client02mcif_lat_fifo_depth + ,client02mcif_rd_axid + ,client12mcif_rd_cdt_lat_fifo_pop + ,client12mcif_rd_req_valid + ,client12mcif_rd_req_pd + ,client12mcif_rd_req_ready + ,mcif2client1_rd_rsp_valid + ,mcif2client1_rd_rsp_pd + ,mcif2client1_rd_rsp_ready + ,client12mcif_lat_fifo_depth + ,client12mcif_rd_axid + ,client22mcif_rd_cdt_lat_fifo_pop + ,client22mcif_rd_req_valid + ,client22mcif_rd_req_pd + ,client22mcif_rd_req_ready + ,mcif2client2_rd_rsp_valid + ,mcif2client2_rd_rsp_pd + ,mcif2client2_rd_rsp_ready + ,client22mcif_lat_fifo_depth + ,client22mcif_rd_axid + ,client32mcif_rd_cdt_lat_fifo_pop + ,client32mcif_rd_req_valid + ,client32mcif_rd_req_pd + ,client32mcif_rd_req_ready + ,mcif2client3_rd_rsp_valid + ,mcif2client3_rd_rsp_pd + ,mcif2client3_rd_rsp_ready + ,client32mcif_lat_fifo_depth + ,client32mcif_rd_axid + ,client42mcif_rd_cdt_lat_fifo_pop + ,client42mcif_rd_req_valid + ,client42mcif_rd_req_pd + ,client42mcif_rd_req_ready + ,mcif2client4_rd_rsp_valid + ,mcif2client4_rd_rsp_pd + ,mcif2client4_rd_rsp_ready + ,client42mcif_lat_fifo_depth + ,client42mcif_rd_axid + ,client52mcif_rd_cdt_lat_fifo_pop + ,client52mcif_rd_req_valid + ,client52mcif_rd_req_pd + ,client52mcif_rd_req_ready + ,mcif2client5_rd_rsp_valid + ,mcif2client5_rd_rsp_pd + ,mcif2client5_rd_rsp_ready + ,client52mcif_lat_fifo_depth + ,client52mcif_rd_axid + ,client62mcif_rd_cdt_lat_fifo_pop + ,client62mcif_rd_req_valid + ,client62mcif_rd_req_pd + ,client62mcif_rd_req_ready + ,mcif2client6_rd_rsp_valid + ,mcif2client6_rd_rsp_pd + ,mcif2client6_rd_rsp_ready + ,client62mcif_lat_fifo_depth + ,client62mcif_rd_axid + ,client02mcif_wr_req_pd + ,client02mcif_wr_req_valid + ,client02mcif_wr_req_ready + ,mcif2client0_wr_rsp_complete + ,client02mcif_wr_axid + ,client12mcif_wr_req_pd + ,client12mcif_wr_req_valid + ,client12mcif_wr_req_ready + ,mcif2client1_wr_rsp_complete + ,client12mcif_wr_axid + ,client22mcif_wr_req_pd + ,client22mcif_wr_req_valid + ,client22mcif_wr_req_ready + ,mcif2client2_wr_rsp_complete + ,client22mcif_wr_axid + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,csb2mcif_req_pd //|< i + ,csb2mcif_req_pvld //|< i + ,csb2mcif_req_prdy //|> o + ,mcif2csb_resp_pd //|> o + ,mcif2csb_resp_valid //|> o + ,noc2mcif_axi_b_bid //|< i + ,noc2mcif_axi_b_bvalid //|< i + ,noc2mcif_axi_r_rdata //|< i + ,noc2mcif_axi_r_rid //|< i + ,noc2mcif_axi_r_rlast //|< i + ,noc2mcif_axi_r_rvalid //|< i + ,mcif2noc_axi_ar_arready //|< i + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,noc2mcif_axi_b_bready //|> o + ,noc2mcif_axi_r_rready //|> o +); +//:my $k = 7; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print ("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print("input client${i}2mcif_rd_req_valid;\n"); +//: print qq(input [47 -1:0] client${i}2mcif_rd_req_pd;\n); +//: print("output client${i}2mcif_rd_req_ready;\n"); +//: print("output mcif2client${i}_rd_rsp_valid;\n"); +//: print("input mcif2client${i}_rd_rsp_ready;\n"); +//: print qq(output [65 -1:0] mcif2client${i}_rd_rsp_pd;\n); +//: print("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: print("input [3:0] client${i}2mcif_rd_axid;\n"); +//: } +//:my $k = 3; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print qq(input [66 -1:0] client${i}2mcif_wr_req_pd;\n); +//: print("input client${i}2mcif_wr_req_valid;\n"); +//: print("output client${i}2mcif_wr_req_ready;\n"); +//: print("output mcif2client${i}_wr_rsp_complete;\n"); +//: print("input [3:0] client${i}2mcif_wr_axid;\n"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input client02mcif_rd_cdt_lat_fifo_pop; +input client02mcif_rd_req_valid; +input [47 -1:0] client02mcif_rd_req_pd; +output client02mcif_rd_req_ready; +output mcif2client0_rd_rsp_valid; +input mcif2client0_rd_rsp_ready; +output [65 -1:0] mcif2client0_rd_rsp_pd; +input [7:0] client02mcif_lat_fifo_depth; +input [3:0] client02mcif_rd_axid; +input client12mcif_rd_cdt_lat_fifo_pop; +input client12mcif_rd_req_valid; +input [47 -1:0] client12mcif_rd_req_pd; +output client12mcif_rd_req_ready; +output mcif2client1_rd_rsp_valid; +input mcif2client1_rd_rsp_ready; +output [65 -1:0] mcif2client1_rd_rsp_pd; +input [7:0] client12mcif_lat_fifo_depth; +input [3:0] client12mcif_rd_axid; +input client22mcif_rd_cdt_lat_fifo_pop; +input client22mcif_rd_req_valid; +input [47 -1:0] client22mcif_rd_req_pd; +output client22mcif_rd_req_ready; +output mcif2client2_rd_rsp_valid; +input mcif2client2_rd_rsp_ready; +output [65 -1:0] mcif2client2_rd_rsp_pd; +input [7:0] client22mcif_lat_fifo_depth; +input [3:0] client22mcif_rd_axid; +input client32mcif_rd_cdt_lat_fifo_pop; +input client32mcif_rd_req_valid; +input [47 -1:0] client32mcif_rd_req_pd; +output client32mcif_rd_req_ready; +output mcif2client3_rd_rsp_valid; +input mcif2client3_rd_rsp_ready; +output [65 -1:0] mcif2client3_rd_rsp_pd; +input [7:0] client32mcif_lat_fifo_depth; +input [3:0] client32mcif_rd_axid; +input client42mcif_rd_cdt_lat_fifo_pop; +input client42mcif_rd_req_valid; +input [47 -1:0] client42mcif_rd_req_pd; +output client42mcif_rd_req_ready; +output mcif2client4_rd_rsp_valid; +input mcif2client4_rd_rsp_ready; +output [65 -1:0] mcif2client4_rd_rsp_pd; +input [7:0] client42mcif_lat_fifo_depth; +input [3:0] client42mcif_rd_axid; +input client52mcif_rd_cdt_lat_fifo_pop; +input client52mcif_rd_req_valid; +input [47 -1:0] client52mcif_rd_req_pd; +output client52mcif_rd_req_ready; +output mcif2client5_rd_rsp_valid; +input mcif2client5_rd_rsp_ready; +output [65 -1:0] mcif2client5_rd_rsp_pd; +input [7:0] client52mcif_lat_fifo_depth; +input [3:0] client52mcif_rd_axid; +input client62mcif_rd_cdt_lat_fifo_pop; +input client62mcif_rd_req_valid; +input [47 -1:0] client62mcif_rd_req_pd; +output client62mcif_rd_req_ready; +output mcif2client6_rd_rsp_valid; +input mcif2client6_rd_rsp_ready; +output [65 -1:0] mcif2client6_rd_rsp_pd; +input [7:0] client62mcif_lat_fifo_depth; +input [3:0] client62mcif_rd_axid; +input [66 -1:0] client02mcif_wr_req_pd; +input client02mcif_wr_req_valid; +output client02mcif_wr_req_ready; +output mcif2client0_wr_rsp_complete; +input [3:0] client02mcif_wr_axid; +input [66 -1:0] client12mcif_wr_req_pd; +input client12mcif_wr_req_valid; +output client12mcif_wr_req_ready; +output mcif2client1_wr_rsp_complete; +input [3:0] client12mcif_wr_axid; +input [66 -1:0] client22mcif_wr_req_pd; +input client22mcif_wr_req_valid; +output client22mcif_wr_req_ready; +output mcif2client2_wr_rsp_complete; +input [3:0] client22mcif_wr_axid; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +input csb2mcif_req_pvld; /* data valid */ +output csb2mcif_req_prdy; /* data return handshake */ +input [62:0] csb2mcif_req_pd; +output mcif2csb_resp_valid; /* data valid */ +output [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +NV_NVDLA_NOCIF_dram u_dram ( + .nvdla_core_clk(nvdla_core_clk) + ,.nvdla_core_rstn(nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< i + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> o + ,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< i + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> o + ,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> o +//: my $k = 7; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,.client${i}2mcif_rd_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print(" ,.client${i}2mcif_rd_req_valid(client${i}2mcif_rd_req_valid)\n"); +//: print(" ,.client${i}2mcif_rd_req_pd(client${i}2mcif_rd_req_pd)\n"); +//: print(" ,.client${i}2mcif_rd_req_ready(client${i}2mcif_rd_req_ready)\n"); +//: print(" ,.mcif2client${i}_rd_rsp_valid(mcif2client${i}_rd_rsp_valid)\n"); +//: print(" ,.mcif2client${i}_rd_rsp_ready(mcif2client${i}_rd_rsp_ready)\n"); +//: print(" ,.mcif2client${i}_rd_rsp_pd(mcif2client${i}_rd_rsp_pd)\n"); +//: print(" ,.client${i}2mcif_rd_axid(client${i}2mcif_rd_axid)\n"); +//: print(" ,.client${i}2mcif_lat_fifo_depth(client${i}2mcif_lat_fifo_depth)\n"); +//: } +//: my $k = 3; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,.client${i}2mcif_wr_req_pd(client${i}2mcif_wr_req_pd)\n"); +//: print(" ,.client${i}2mcif_wr_req_valid(client${i}2mcif_wr_req_valid)\n"); +//: print(" ,.client${i}2mcif_wr_req_ready(client${i}2mcif_wr_req_ready)\n"); +//: print(" ,.mcif2client${i}_wr_rsp_complete(mcif2client${i}_wr_rsp_complete)\n"); +//: print(" ,.client${i}2mcif_wr_axid(client${i}2mcif_wr_axid)\n"); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + ,.client02mcif_rd_cdt_lat_fifo_pop(client02mcif_rd_cdt_lat_fifo_pop) + ,.client02mcif_rd_req_valid(client02mcif_rd_req_valid) + ,.client02mcif_rd_req_pd(client02mcif_rd_req_pd) + ,.client02mcif_rd_req_ready(client02mcif_rd_req_ready) + ,.mcif2client0_rd_rsp_valid(mcif2client0_rd_rsp_valid) + ,.mcif2client0_rd_rsp_ready(mcif2client0_rd_rsp_ready) + ,.mcif2client0_rd_rsp_pd(mcif2client0_rd_rsp_pd) + ,.client02mcif_rd_axid(client02mcif_rd_axid) + ,.client02mcif_lat_fifo_depth(client02mcif_lat_fifo_depth) + ,.client12mcif_rd_cdt_lat_fifo_pop(client12mcif_rd_cdt_lat_fifo_pop) + ,.client12mcif_rd_req_valid(client12mcif_rd_req_valid) + ,.client12mcif_rd_req_pd(client12mcif_rd_req_pd) + ,.client12mcif_rd_req_ready(client12mcif_rd_req_ready) + ,.mcif2client1_rd_rsp_valid(mcif2client1_rd_rsp_valid) + ,.mcif2client1_rd_rsp_ready(mcif2client1_rd_rsp_ready) + ,.mcif2client1_rd_rsp_pd(mcif2client1_rd_rsp_pd) + ,.client12mcif_rd_axid(client12mcif_rd_axid) + ,.client12mcif_lat_fifo_depth(client12mcif_lat_fifo_depth) + ,.client22mcif_rd_cdt_lat_fifo_pop(client22mcif_rd_cdt_lat_fifo_pop) + ,.client22mcif_rd_req_valid(client22mcif_rd_req_valid) + ,.client22mcif_rd_req_pd(client22mcif_rd_req_pd) + ,.client22mcif_rd_req_ready(client22mcif_rd_req_ready) + ,.mcif2client2_rd_rsp_valid(mcif2client2_rd_rsp_valid) + ,.mcif2client2_rd_rsp_ready(mcif2client2_rd_rsp_ready) + ,.mcif2client2_rd_rsp_pd(mcif2client2_rd_rsp_pd) + ,.client22mcif_rd_axid(client22mcif_rd_axid) + ,.client22mcif_lat_fifo_depth(client22mcif_lat_fifo_depth) + ,.client32mcif_rd_cdt_lat_fifo_pop(client32mcif_rd_cdt_lat_fifo_pop) + ,.client32mcif_rd_req_valid(client32mcif_rd_req_valid) + ,.client32mcif_rd_req_pd(client32mcif_rd_req_pd) + ,.client32mcif_rd_req_ready(client32mcif_rd_req_ready) + ,.mcif2client3_rd_rsp_valid(mcif2client3_rd_rsp_valid) + ,.mcif2client3_rd_rsp_ready(mcif2client3_rd_rsp_ready) + ,.mcif2client3_rd_rsp_pd(mcif2client3_rd_rsp_pd) + ,.client32mcif_rd_axid(client32mcif_rd_axid) + ,.client32mcif_lat_fifo_depth(client32mcif_lat_fifo_depth) + ,.client42mcif_rd_cdt_lat_fifo_pop(client42mcif_rd_cdt_lat_fifo_pop) + ,.client42mcif_rd_req_valid(client42mcif_rd_req_valid) + ,.client42mcif_rd_req_pd(client42mcif_rd_req_pd) + ,.client42mcif_rd_req_ready(client42mcif_rd_req_ready) + ,.mcif2client4_rd_rsp_valid(mcif2client4_rd_rsp_valid) + ,.mcif2client4_rd_rsp_ready(mcif2client4_rd_rsp_ready) + ,.mcif2client4_rd_rsp_pd(mcif2client4_rd_rsp_pd) + ,.client42mcif_rd_axid(client42mcif_rd_axid) + ,.client42mcif_lat_fifo_depth(client42mcif_lat_fifo_depth) + ,.client52mcif_rd_cdt_lat_fifo_pop(client52mcif_rd_cdt_lat_fifo_pop) + ,.client52mcif_rd_req_valid(client52mcif_rd_req_valid) + ,.client52mcif_rd_req_pd(client52mcif_rd_req_pd) + ,.client52mcif_rd_req_ready(client52mcif_rd_req_ready) + ,.mcif2client5_rd_rsp_valid(mcif2client5_rd_rsp_valid) + ,.mcif2client5_rd_rsp_ready(mcif2client5_rd_rsp_ready) + ,.mcif2client5_rd_rsp_pd(mcif2client5_rd_rsp_pd) + ,.client52mcif_rd_axid(client52mcif_rd_axid) + ,.client52mcif_lat_fifo_depth(client52mcif_lat_fifo_depth) + ,.client62mcif_rd_cdt_lat_fifo_pop(client62mcif_rd_cdt_lat_fifo_pop) + ,.client62mcif_rd_req_valid(client62mcif_rd_req_valid) + ,.client62mcif_rd_req_pd(client62mcif_rd_req_pd) + ,.client62mcif_rd_req_ready(client62mcif_rd_req_ready) + ,.mcif2client6_rd_rsp_valid(mcif2client6_rd_rsp_valid) + ,.mcif2client6_rd_rsp_ready(mcif2client6_rd_rsp_ready) + ,.mcif2client6_rd_rsp_pd(mcif2client6_rd_rsp_pd) + ,.client62mcif_rd_axid(client62mcif_rd_axid) + ,.client62mcif_lat_fifo_depth(client62mcif_lat_fifo_depth) + ,.client02mcif_wr_req_pd(client02mcif_wr_req_pd) + ,.client02mcif_wr_req_valid(client02mcif_wr_req_valid) + ,.client02mcif_wr_req_ready(client02mcif_wr_req_ready) + ,.mcif2client0_wr_rsp_complete(mcif2client0_wr_rsp_complete) + ,.client02mcif_wr_axid(client02mcif_wr_axid) + ,.client12mcif_wr_req_pd(client12mcif_wr_req_pd) + ,.client12mcif_wr_req_valid(client12mcif_wr_req_valid) + ,.client12mcif_wr_req_ready(client12mcif_wr_req_ready) + ,.mcif2client1_wr_rsp_complete(mcif2client1_wr_rsp_complete) + ,.client12mcif_wr_axid(client12mcif_wr_axid) + ,.client22mcif_wr_req_pd(client22mcif_wr_req_pd) + ,.client22mcif_wr_req_valid(client22mcif_wr_req_valid) + ,.client22mcif_wr_req_ready(client22mcif_wr_req_ready) + ,.mcif2client2_wr_rsp_complete(mcif2client2_wr_rsp_complete) + ,.client22mcif_wr_axid(client22mcif_wr_axid) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.noc2mcif_axi_b_bid(noc2mcif_axi_b_bid ) //|< i + ,.noc2mcif_axi_b_bvalid(noc2mcif_axi_b_bvalid ) //|< i + ,.noc2mcif_axi_r_rdata(noc2mcif_axi_r_rdata ) //|< i + ,.noc2mcif_axi_r_rid(noc2mcif_axi_r_rid ) //|< i + ,.noc2mcif_axi_r_rlast(noc2mcif_axi_r_rlast ) //|< i + ,.noc2mcif_axi_r_rvalid(noc2mcif_axi_r_rvalid ) //|< i + ,.mcif2noc_axi_ar_arready(mcif2noc_axi_ar_arready ) //|< i + ,.mcif2noc_axi_aw_awready(mcif2noc_axi_aw_awready ) //|< i + ,.mcif2noc_axi_w_wready(mcif2noc_axi_w_wready ) //|< i + ,.mcif2noc_axi_ar_araddr(mcif2noc_axi_ar_araddr ) //|> o + ,.mcif2noc_axi_ar_arid(mcif2noc_axi_ar_arid ) //|> o + ,.mcif2noc_axi_ar_arlen(mcif2noc_axi_ar_arlen ) //|> o + ,.mcif2noc_axi_ar_arvalid(mcif2noc_axi_ar_arvalid ) //|> o + ,.mcif2noc_axi_aw_awaddr(mcif2noc_axi_aw_awaddr ) //|> o + ,.mcif2noc_axi_aw_awid(mcif2noc_axi_aw_awid ) //|> o + ,.mcif2noc_axi_aw_awlen(mcif2noc_axi_aw_awlen ) //|> o + ,.mcif2noc_axi_aw_awvalid(mcif2noc_axi_aw_awvalid ) //|> o + ,.mcif2noc_axi_w_wdata(mcif2noc_axi_w_wdata ) //|> o + ,.mcif2noc_axi_w_wlast(mcif2noc_axi_w_wlast ) //|> o + ,.mcif2noc_axi_w_wstrb(mcif2noc_axi_w_wstrb ) //|> o + ,.mcif2noc_axi_w_wvalid(mcif2noc_axi_w_wvalid ) //|> o + ,.noc2mcif_axi_b_bready(noc2mcif_axi_b_bready ) //|> o + ,.noc2mcif_axi_r_rready(noc2mcif_axi_r_rready ) //|> o +); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.v.vcp b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.v.vcp new file mode 100644 index 0000000..30c44ed --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/nocif/NV_NVDLA_nocif.v.vcp @@ -0,0 +1,172 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_nocif.v +module NV_NVDLA_nocif ( + nvdla_core_clk + ,nvdla_core_rstn + ,pwrbus_ram_pd +//: my $k = 7; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_rd_cdt_lat_fifo_pop\n"); +//: print(" ,client${i}2mcif_rd_req_valid\n"); +//: print(" ,client${i}2mcif_rd_req_pd\n"); +//: print(" ,client${i}2mcif_rd_req_ready\n"); +//: print(" ,mcif2client${i}_rd_rsp_valid\n"); +//: print(" ,mcif2client${i}_rd_rsp_pd\n"); +//: print(" ,mcif2client${i}_rd_rsp_ready\n"); +//: print(" ,client${i}2mcif_lat_fifo_depth\n"); +//: print(" ,client${i}2mcif_rd_axid\n"); +//: } +//: my $k = 3; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,client${i}2mcif_wr_req_pd\n"); +//: print(" ,client${i}2mcif_wr_req_valid\n"); +//: print(" ,client${i}2mcif_wr_req_ready\n"); +//: print(" ,mcif2client${i}_wr_rsp_complete\n"); +//: print(" ,client${i}2mcif_wr_axid\n"); +//: } + ,csb2mcif_req_pd //|< i + ,csb2mcif_req_pvld //|< i + ,csb2mcif_req_prdy //|> o + ,mcif2csb_resp_pd //|> o + ,mcif2csb_resp_valid //|> o + ,noc2mcif_axi_b_bid //|< i + ,noc2mcif_axi_b_bvalid //|< i + ,noc2mcif_axi_r_rdata //|< i + ,noc2mcif_axi_r_rid //|< i + ,noc2mcif_axi_r_rlast //|< i + ,noc2mcif_axi_r_rvalid //|< i + ,mcif2noc_axi_ar_arready //|< i + ,mcif2noc_axi_aw_awready //|< i + ,mcif2noc_axi_w_wready //|< i + ,mcif2noc_axi_ar_araddr //|> o + ,mcif2noc_axi_ar_arid //|> o + ,mcif2noc_axi_ar_arlen //|> o + ,mcif2noc_axi_ar_arvalid //|> o + ,mcif2noc_axi_aw_awaddr //|> o + ,mcif2noc_axi_aw_awid //|> o + ,mcif2noc_axi_aw_awlen //|> o + ,mcif2noc_axi_aw_awvalid //|> o + ,mcif2noc_axi_w_wdata //|> o + ,mcif2noc_axi_w_wlast //|> o + ,mcif2noc_axi_w_wstrb //|> o + ,mcif2noc_axi_w_wvalid //|> o + ,noc2mcif_axi_b_bready //|> o + ,noc2mcif_axi_r_rready //|> o +); +//:my $k = 7; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print ("input client${i}2mcif_rd_cdt_lat_fifo_pop;\n"); +//: print("input client${i}2mcif_rd_req_valid;\n"); +//: print qq(input [47 -1:0] client${i}2mcif_rd_req_pd;\n); +//: print("output client${i}2mcif_rd_req_ready;\n"); +//: print("output mcif2client${i}_rd_rsp_valid;\n"); +//: print("input mcif2client${i}_rd_rsp_ready;\n"); +//: print qq(output [65 -1:0] mcif2client${i}_rd_rsp_pd;\n); +//: print("input [7:0] client${i}2mcif_lat_fifo_depth;\n"); +//: print("input [3:0] client${i}2mcif_rd_axid;\n"); +//: } +//:my $k = 3; +//:my $i = 0; +//:for ($i=0;$i<$k;$i++) { +//: print qq(input [66 -1:0] client${i}2mcif_wr_req_pd;\n); +//: print("input client${i}2mcif_wr_req_valid;\n"); +//: print("output client${i}2mcif_wr_req_ready;\n"); +//: print("output mcif2client${i}_wr_rsp_complete;\n"); +//: print("input [3:0] client${i}2mcif_wr_axid;\n"); +//: } +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output mcif2noc_axi_ar_arvalid; /* data valid */ +input mcif2noc_axi_ar_arready; /* data return handshake */ +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +output mcif2noc_axi_aw_awvalid; /* data valid */ +input mcif2noc_axi_aw_awready; /* data return handshake */ +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; /* data valid */ +input mcif2noc_axi_w_wready; /* data return handshake */ +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; /* data valid */ +output noc2mcif_axi_b_bready; /* data return handshake */ +input [7:0] noc2mcif_axi_b_bid; +input noc2mcif_axi_r_rvalid; /* data valid */ +output noc2mcif_axi_r_rready; /* data return handshake */ +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +input csb2mcif_req_pvld; /* data valid */ +output csb2mcif_req_prdy; /* data return handshake */ +input [62:0] csb2mcif_req_pd; +output mcif2csb_resp_valid; /* data valid */ +output [33:0] mcif2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +NV_NVDLA_NOCIF_dram u_dram ( + .nvdla_core_clk(nvdla_core_clk) + ,.nvdla_core_rstn(nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< i + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> o + ,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< i + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> o + ,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> o +//: my $k = 7; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,.client${i}2mcif_rd_cdt_lat_fifo_pop(client${i}2mcif_rd_cdt_lat_fifo_pop)\n"); +//: print(" ,.client${i}2mcif_rd_req_valid(client${i}2mcif_rd_req_valid)\n"); +//: print(" ,.client${i}2mcif_rd_req_pd(client${i}2mcif_rd_req_pd)\n"); +//: print(" ,.client${i}2mcif_rd_req_ready(client${i}2mcif_rd_req_ready)\n"); +//: print(" ,.mcif2client${i}_rd_rsp_valid(mcif2client${i}_rd_rsp_valid)\n"); +//: print(" ,.mcif2client${i}_rd_rsp_ready(mcif2client${i}_rd_rsp_ready)\n"); +//: print(" ,.mcif2client${i}_rd_rsp_pd(mcif2client${i}_rd_rsp_pd)\n"); +//: print(" ,.client${i}2mcif_rd_axid(client${i}2mcif_rd_axid)\n"); +//: print(" ,.client${i}2mcif_lat_fifo_depth(client${i}2mcif_lat_fifo_depth)\n"); +//: } +//: my $k = 3; +//: my $i = 0; +//: for($i=0; $i<$k; $i++) { +//: print(" ,.client${i}2mcif_wr_req_pd(client${i}2mcif_wr_req_pd)\n"); +//: print(" ,.client${i}2mcif_wr_req_valid(client${i}2mcif_wr_req_valid)\n"); +//: print(" ,.client${i}2mcif_wr_req_ready(client${i}2mcif_wr_req_ready)\n"); +//: print(" ,.mcif2client${i}_wr_rsp_complete(mcif2client${i}_wr_rsp_complete)\n"); +//: print(" ,.client${i}2mcif_wr_axid(client${i}2mcif_wr_axid)\n"); +//: } + ,.noc2mcif_axi_b_bid(noc2mcif_axi_b_bid ) //|< i + ,.noc2mcif_axi_b_bvalid(noc2mcif_axi_b_bvalid ) //|< i + ,.noc2mcif_axi_r_rdata(noc2mcif_axi_r_rdata ) //|< i + ,.noc2mcif_axi_r_rid(noc2mcif_axi_r_rid ) //|< i + ,.noc2mcif_axi_r_rlast(noc2mcif_axi_r_rlast ) //|< i + ,.noc2mcif_axi_r_rvalid(noc2mcif_axi_r_rvalid ) //|< i + ,.mcif2noc_axi_ar_arready(mcif2noc_axi_ar_arready ) //|< i + ,.mcif2noc_axi_aw_awready(mcif2noc_axi_aw_awready ) //|< i + ,.mcif2noc_axi_w_wready(mcif2noc_axi_w_wready ) //|< i + ,.mcif2noc_axi_ar_araddr(mcif2noc_axi_ar_araddr ) //|> o + ,.mcif2noc_axi_ar_arid(mcif2noc_axi_ar_arid ) //|> o + ,.mcif2noc_axi_ar_arlen(mcif2noc_axi_ar_arlen ) //|> o + ,.mcif2noc_axi_ar_arvalid(mcif2noc_axi_ar_arvalid ) //|> o + ,.mcif2noc_axi_aw_awaddr(mcif2noc_axi_aw_awaddr ) //|> o + ,.mcif2noc_axi_aw_awid(mcif2noc_axi_aw_awid ) //|> o + ,.mcif2noc_axi_aw_awlen(mcif2noc_axi_aw_awlen ) //|> o + ,.mcif2noc_axi_aw_awvalid(mcif2noc_axi_aw_awvalid ) //|> o + ,.mcif2noc_axi_w_wdata(mcif2noc_axi_w_wdata ) //|> o + ,.mcif2noc_axi_w_wlast(mcif2noc_axi_w_wlast ) //|> o + ,.mcif2noc_axi_w_wstrb(mcif2noc_axi_w_wstrb ) //|> o + ,.mcif2noc_axi_w_wvalid(mcif2noc_axi_w_wvalid ) //|> o + ,.noc2mcif_axi_b_bready(noc2mcif_axi_b_bready ) //|> o + ,.noc2mcif_axi_r_rready(noc2mcif_axi_r_rready ) //|> o +); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v new file mode 100644 index 0000000..1df7ff7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v @@ -0,0 +1,3008 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_cal1d.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_cal1d ( + nvdla_core_clk + ,nvdla_core_rstn + ,datin_src_cfg + ,dp2reg_done + ,padding_h_cfg + ,pdp_rdma2dp_pd + ,pdp_rdma2dp_valid + ,pooling1d_prdy + ,pooling_channel_cfg + ,pooling_fwidth_cfg + ,pooling_lwidth_cfg + ,pooling_mwidth_cfg + ,pooling_out_fwidth_cfg + ,pooling_out_lwidth_cfg + ,pooling_out_mwidth_cfg + ,pooling_size_h_cfg + ,pooling_splitw_num_cfg + ,pooling_stride_h_cfg + ,pooling_type_cfg + ,pwrbus_ram_pd + ,reg2dp_cube_in_height + ,reg2dp_cube_in_width + ,reg2dp_cube_out_width +//,reg2dp_input_data +//,reg2dp_int16_en +//,reg2dp_int8_en + ,reg2dp_kernel_stride_width + ,reg2dp_kernel_width + ,reg2dp_op_en + ,reg2dp_pad_left + ,reg2dp_pad_right + ,reg2dp_pad_right_cfg + ,reg2dp_pad_value_1x_cfg + ,reg2dp_pad_value_2x_cfg + ,reg2dp_pad_value_3x_cfg + ,reg2dp_pad_value_4x_cfg + ,reg2dp_pad_value_5x_cfg + ,reg2dp_pad_value_6x_cfg + ,reg2dp_pad_value_7x_cfg + ,sdp2pdp_pd + ,sdp2pdp_valid + ,pdp_op_start + ,pdp_rdma2dp_ready + ,pooling1d_pd + ,pooling1d_pvld + ,sdp2pdp_ready + ); +////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input datin_src_cfg; +input dp2reg_done; +input [2:0] padding_h_cfg; +input [1*8 +11:0] pdp_rdma2dp_pd; +input pdp_rdma2dp_valid; +input pooling1d_prdy; +input [12:0] pooling_channel_cfg; +input [9:0] pooling_fwidth_cfg; +input [9:0] pooling_lwidth_cfg; +input [9:0] pooling_mwidth_cfg; +input [9:0] pooling_out_fwidth_cfg; +input [9:0] pooling_out_lwidth_cfg; +input [9:0] pooling_out_mwidth_cfg; +input [2:0] pooling_size_h_cfg; +input [7:0] pooling_splitw_num_cfg; +input [3:0] pooling_stride_h_cfg; +input [1:0] pooling_type_cfg; +input [31:0] pwrbus_ram_pd; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_in_width; +input [12:0] reg2dp_cube_out_width; +//input [1:0] reg2dp_input_data; +//input reg2dp_int16_en; +//input reg2dp_int8_en; +input [3:0] reg2dp_kernel_stride_width; +input [2:0] reg2dp_kernel_width; +input reg2dp_op_en; +input [2:0] reg2dp_pad_left; +input [2:0] reg2dp_pad_right; +input [2:0] reg2dp_pad_right_cfg; +input [18:0] reg2dp_pad_value_1x_cfg; +input [18:0] reg2dp_pad_value_2x_cfg; +input [18:0] reg2dp_pad_value_3x_cfg; +input [18:0] reg2dp_pad_value_4x_cfg; +input [18:0] reg2dp_pad_value_5x_cfg; +input [18:0] reg2dp_pad_value_6x_cfg; +input [18:0] reg2dp_pad_value_7x_cfg; +input [1*8 +11:0] sdp2pdp_pd; +input sdp2pdp_valid; +output pdp_op_start; +output pdp_rdma2dp_ready; +//: my $m = 1*(8 +6); +//: print " output [$m-1:0] pooling1d_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + output [14-1:0] pooling1d_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output pooling1d_pvld; +output sdp2pdp_ready; +////////////////////////////////////////////////////////////////////////// +//wire +wire average_pooling_en; +wire big_stride; +wire bsync; +wire bubble_en_end; +wire [2:0] bubble_num_dec; +wire [12:0] cube_out_channel; +wire [3:0] cube_width_in; +wire cur_datin_disable_sync; +wire [1*(8 +3)-1:0] datain_ext; +wire [1*(8 +3)+8:0] datin_buf; +wire [2:0] first_out_num_dec2; +wire first_splitw; +wire first_splitw_en; +wire init_cnt; +wire [7:0] init_unit1d_set; +wire [10:0] k_add_ks; +wire [4:0] kernel_padl; +wire [4:0] ks_width; +wire last_c; +wire last_c_sync; +wire last_line_in; +wire last_out_done; +wire last_out_en_sync; +wire last_pooling_flag; +wire last_splitw; +wire last_splitw_en; +wire line_last_stripe_done; +wire line_ldata_valid; +wire [2:0] line_regs_1; +wire [2:0] line_regs_2; +wire [2:0] line_regs_3; +wire [2:0] line_regs_4; +wire load_din; +wire loading_en; +wire [2:0] mon_first_out_num_dec2; +wire mon_overlap; +wire [1:0] mon_overlap_ff; +wire [0:0] mon_pad_table_index; +wire mon_rest_width; +wire [5:0] mon_strip_xcnt_offset; +//wire [0:0] mon_unit1d_actv_data_16bit_0; +//wire [0:0] mon_unit1d_actv_data_16bit_0_ff; +//wire [0:0] mon_unit1d_actv_data_16bit_1; +//wire [0:0] mon_unit1d_actv_data_16bit_1_ff; +//wire [0:0] mon_unit1d_actv_data_16bit_2; +//wire [0:0] mon_unit1d_actv_data_16bit_2_ff; +//wire [0:0] mon_unit1d_actv_data_16bit_3; +//wire [0:0] mon_unit1d_actv_data_16bit_3_ff; +wire non_split_small_active; +wire [3:0] non_split_w_pl; +wire [4:0] non_split_w_pl_pr; +wire non_splitw; +wire off_flying_en; +wire on_flying_en; +wire [3:0] overlap; +wire [2:0] overlap_ff; +wire [2:0] pad_l; +wire [2:0] pad_r; +wire [2:0] pad_table_index; +wire padding_here; +//wire padding_here_int16; +wire padding_here_int8; +wire [2:0] padding_stride1_num; +wire [2:0] padding_stride2_num; +wire [2:0] padding_stride3_num; +wire [2:0] padding_stride4_num; +wire [10:0] partial_w_last; +wire pdp_cube_end; +wire pdp_cube_sync; +wire [1*(8 +3) + 12:0] pdp_datin_pd; +wire [1*(8 +3) + 12:0] pdp_datin_pd_f0; +wire [1*8 +11:0] pdp_datin_pd_f_0; +wire [1*8 +11:0] pdp_datin_pd_f_mux0; +wire pdp_datin_prdy; +wire pdp_datin_prdy_0; +wire pdp_datin_prdy_1; +wire pdp_datin_prdy_f; +wire pdp_datin_prdy_mux0; +wire pdp_datin_pvld; +wire pdp_datin_pvld_f; +wire pdp_datin_pvld_mux0; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print "wire [$b+2:0] pdp_din_$m; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8+2:0] pdp_din_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire pdp_din_lc; +wire pdp_din_lc_sync; +wire pdp_full_pvld; +wire [11:0] pdp_info_in_pd; +wire pdp_info_in_prdy; +wire pdp_info_in_pvld; +wire [11:0] pdp_info_out_pd; +wire pdp_info_out_prdy; +wire pdp_info_out_pvld; +wire pooling1d_data_pad_rdy; +wire pooling1d_out_v; +wire pooling1d_out_v_disable; +wire pooling1d_out_v_lastout; +wire pooling1d_out_v_norm; +wire pooling_1d_rdy; +wire [7:0] pooling_din_last; +wire [7:0] pooling_din_last_sync; +wire [3:0] pooling_size; +wire [3:0] pooling_size_h; +wire [4:0] pooling_stride_h; +wire posc_last; +wire [12:0] pout_width_cur; +wire [12:0] rest_width; +wire [13:0] rest_width_use; +wire split_small_active; +wire [5:0] split_w_olap; +wire [6:0] split_w_olap_pr; +wire splitw_enable; +wire splitw_end; +wire splitw_end_sync; +wire splitw_start; +wire [4:0] stride; +wire [4:0] stride_1x; +wire [5:0] stride_2x; +wire [6:0] stride_3x; +wire [6:0] stride_4x; +wire [7:0] stride_5x; +wire [7:0] stride_6x; +wire [7:0] stride_7x; +wire stride_end; +wire strip_recieve_done; +wire strip_width_end; +wire [2:0] strip_xcnt_offset; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "wire [12-${k}:0] surface_num; \n"; +//: print "reg [12-${k}:0] surface_cnt_rd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [12-3:0] surface_num; +reg [12-3:0] surface_cnt_rd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire sync_switch_in_vld_d0; +wire sync_switch_in_vld_d1; +wire [11:0] sync_switch_out_pd; +wire sync_switch_out_rdy; +wire sync_switch_out_vld; +//wire [21:0] unit1d_actv_data_16bit_0; +//wire [21:0] unit1d_actv_data_16bit_0_ff; +//wire [21:0] unit1d_actv_data_16bit_1; +//wire [21:0] unit1d_actv_data_16bit_1_ff; +//wire [21:0] unit1d_actv_data_16bit_2; +//wire [21:0] unit1d_actv_data_16bit_2_ff; +//wire [21:0] unit1d_actv_data_16bit_3; +//wire [21:0] unit1d_actv_data_16bit_3_ff; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print "wire [$b+2:0] unit1d_actv_data_8bit_${m}; \n"; +//: print "wire [$b+2:0] unit1d_actv_data_8bit_${m}_ff; \n"; +//: print "wire [1:0] mon_unit1d_actv_data_8bit_${m}; \n"; +//: print "wire [1:0] mon_unit1d_actv_data_8bit_${m}_ff; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8+2:0] unit1d_actv_data_8bit_0; +wire [8+2:0] unit1d_actv_data_8bit_0_ff; +wire [1:0] mon_unit1d_actv_data_8bit_0; +wire [1:0] mon_unit1d_actv_data_8bit_0_ff; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [1*(8 +3)+3:0] unit1d_actv_out; +wire unit1d_actv_out_prdy; +wire unit1d_actv_out_pvld; +wire [7:0] unit1d_clr; +wire [1*(8 +3)+3:0] unit1d_out_0; +wire [1*(8 +3)+3:0] unit1d_out_1; +wire [1*(8 +3)+3:0] unit1d_out_2; +wire [1*(8 +3)+3:0] unit1d_out_3; +wire [1*(8 +3)+3:0] unit1d_out_4; +wire [1*(8 +3)+3:0] unit1d_out_5; +wire [1*(8 +3)+3:0] unit1d_out_6; +wire [1*(8 +3)+3:0] unit1d_out_7; +wire [7:0] unit1d_out_prdy; +wire unit1d_out_prdy_use; +wire [7:0] unit1d_out_pvld; +wire unit1d_out_pvld_use; +wire [7:0] unit1d_prdy; +wire [7:0] unit1d_pvld; +wire [7:0] unit1d_set; +wire [7:0] unit1d_set_trig; +wire wr_line_dat_done; +wire wr_subcube_dat_done; +wire wr_surface_dat_done; +wire wr_total_cube_done; +//reg +reg [2:0] bubble_cnt; +reg [2:0] bubble_num; +reg [4:0] channel_cnt; +reg cur_datin_disable; +reg [4:0] first_out_num; +reg [2:0] flush_num; +reg [2:0] flush_num_cal; +reg [2:0] last_out_cnt; +reg last_out_en; +reg [6:0] mon_first_out_num; +reg need_bubble; +reg [7:0] pad_r_remain; +reg [18:0] pad_table_out; +reg [2:0] padding_left; +reg [2:0] padding_stride_num; +//reg [1*(8 +3) + 12:0] pdp_datin_pd0; +//reg pdp_datin_prdy_f0; +//reg pdp_datin_pvld0; +reg pdp_op_pending; +reg pdpw_active_en; +reg [1*(8 +6)-1:0] pooling1d_data_pad; +reg pooling1d_data_pad_vld; +reg pooling_din_1st_0; +reg pooling_din_1st_1; +reg pooling_din_1st_2; +reg pooling_din_1st_3; +reg pooling_din_1st_4; +reg pooling_din_1st_5; +reg pooling_din_1st_6; +reg pooling_din_1st_7; +reg [2:0] pooling_out_cnt; +reg [12:0] pooling_pwidth; +reg [2:0] regs_num; +reg [2:0] samllW_flush_num; +reg [7:0] splitw_cnt; +reg [12:0] strip_cnt_total; +reg [2:0] strip_xcnt_psize; +reg [3:0] strip_xcnt_stride; +reg [3:0] strip_xcnt_stride_f; +reg subcube_end_flag; +reg [1*(8 +3)+3:0] unit1d_actv_out_f; +reg [2:0] unit1d_cnt_pooling; +reg [2:0] unit1d_cnt_stride; +reg [7:0] unit1d_en; +reg [12:0] wr_line_dat_cnt; +reg [7:0] wr_splitc_cnt; +reg [12:0] wr_surface_dat_cnt; +//////////////////////////////////////////////////////////////// +//============================================================== +//PDP start +// +//-------------------------------------------------------------- +assign pdp_op_start = ~pdp_op_pending & reg2dp_op_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_op_pending <= 1'b0; + end else begin + if(pdp_op_start) + pdp_op_pending <= 1'b1; + else if(dp2reg_done) + pdp_op_pending <= 1'b0; + end +end +//============================================================== +//input data source select +//-------------------------------------------------------------- +assign off_flying_en = (datin_src_cfg == 1'h1 ); +assign on_flying_en = (datin_src_cfg == 1'h0 ); +assign pdp_datin_pd_f_mux0 = off_flying_en? pdp_rdma2dp_pd : sdp2pdp_pd; +assign pdp_datin_pvld_mux0 = off_flying_en? pdp_rdma2dp_valid : sdp2pdp_valid; +assign pdp_rdma2dp_ready = pdp_datin_prdy_mux0 & off_flying_en; +assign sdp2pdp_ready = pdp_datin_prdy_mux0 & on_flying_en; +assign pdp_datin_prdy_mux0 = pdp_datin_prdy_f; +//--------------------------------------------------------------- +//--------------------------------------------------------------- +//data select after switch +assign pdp_datin_pd_f_0 = pdp_datin_pd_f_mux0; +assign pdp_datin_pvld_f = pdp_datin_pvld_mux0; +//=============================================================== +// 1 cycle pipeline for DW timing closure inside unit1d sub modudle +// DW has replaced by normal hls fp17 adder, this pipeline keep here +//--------------------------------------------------------------- +//: my $dbw = 1*8; +//: my $Enum = 8/1 -1; +//: print " assign posc_last = (pdp_datin_pd_f_0[${dbw}+6:${dbw}+4]==${Enum}); \n"; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign pdp_din_$m = {{3{pdp_datin_pd_f_0[${b}*${m}+${b}-1]}},pdp_datin_pd_f_0[${b}*${m}+${b}-1:${b}*${m}]}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign posc_last = (pdp_datin_pd_f_0[8+6:8+4]==7); + +assign pdp_din_0 = {{3{pdp_datin_pd_f_0[8*0+8-1]}},pdp_datin_pd_f_0[8*0+8-1:8*0]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign datain_ext = { +//: my $k = 1; +//: if($k>1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print "pdp_din_${i}, "; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +pdp_din_0}; +assign pdp_datin_pd_f0 = {posc_last,pdp_datin_pd_f_0[1*8 +11:1*8],datain_ext}; +//: my $k = 1*(8 +3) + 13; +//: &eperl::pipe(" -wid $k -is -do pdp_datin_pd0 -vo pdp_datin_pvld0 -ri pdp_datin_prdy -di pdp_datin_pd_f0 -vi pdp_datin_pvld_f -ro pdp_datin_prdy_f0 "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg pdp_datin_prdy_f0; +reg skid_flop_pdp_datin_prdy_f0; +reg skid_flop_pdp_datin_pvld_f; +reg [24-1:0] skid_flop_pdp_datin_pd_f0; +reg pipe_skid_pdp_datin_pvld_f; +reg [24-1:0] pipe_skid_pdp_datin_pd_f0; +// Wire +wire skid_pdp_datin_pvld_f; +wire [24-1:0] skid_pdp_datin_pd_f0; +wire skid_pdp_datin_prdy_f0; +wire pipe_skid_pdp_datin_prdy_f0; +wire pdp_datin_pvld0; +wire [24-1:0] pdp_datin_pd0; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_datin_prdy_f0 <= 1'b1; + skid_flop_pdp_datin_prdy_f0 <= 1'b1; + end else begin + pdp_datin_prdy_f0 <= skid_pdp_datin_prdy_f0; + skid_flop_pdp_datin_prdy_f0 <= skid_pdp_datin_prdy_f0; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_pdp_datin_pvld_f <= 1'b0; + end else begin + if (skid_flop_pdp_datin_prdy_f0) begin + skid_flop_pdp_datin_pvld_f <= pdp_datin_pvld_f; + end + end +end +assign skid_pdp_datin_pvld_f = (skid_flop_pdp_datin_prdy_f0) ? pdp_datin_pvld_f : skid_flop_pdp_datin_pvld_f; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_pdp_datin_prdy_f0 & pdp_datin_pvld_f) begin + skid_flop_pdp_datin_pd_f0[24-1:0] <= pdp_datin_pd_f0[24-1:0]; + end +end +assign skid_pdp_datin_pd_f0[24-1:0] = (skid_flop_pdp_datin_prdy_f0) ? pdp_datin_pd_f0[24-1:0] : skid_flop_pdp_datin_pd_f0[24-1:0]; + + +// PIPE READY +assign skid_pdp_datin_prdy_f0 = pipe_skid_pdp_datin_prdy_f0 || !pipe_skid_pdp_datin_pvld_f; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_pdp_datin_pvld_f <= 1'b0; + end else begin + if (skid_pdp_datin_prdy_f0) begin + pipe_skid_pdp_datin_pvld_f <= skid_pdp_datin_pvld_f; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_pdp_datin_prdy_f0 && skid_pdp_datin_pvld_f) begin + pipe_skid_pdp_datin_pd_f0[24-1:0] <= skid_pdp_datin_pd_f0[24-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_pdp_datin_prdy_f0 = pdp_datin_prdy; +assign pdp_datin_pvld0 = pipe_skid_pdp_datin_pvld_f; +assign pdp_datin_pd0 = pipe_skid_pdp_datin_pd_f0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pdp_datin_prdy_f = pdp_datin_prdy_f0; +assign pdp_datin_pvld = pdp_datin_pvld0; +assign pdp_datin_pd = pdp_datin_pd0; +assign pdp_datin_prdy = (pdp_datin_prdy_0 & pdp_datin_prdy_1) & pdpw_active_en; +assign pdp_datin_prdy_0 = ~ cur_datin_disable; +//============================================================== +//new splitw +//--------------------------------------------------------------- +//assign bsync = pdp_datin_pd[95]; +//assign splitw_end_sync = load_din ? pdp_datin_pd[98] : 1'b0; +//assign pdp_cube_sync = pdp_datin_pd[99]; +assign bsync = pdp_datin_pd[1*(8 +3)+7]; +assign splitw_end_sync = load_din ? pdp_datin_pd[1*(8 +3)+10] : 1'b0; +assign pdp_cube_sync = pdp_datin_pd[1*(8 +3)+11]; +assign pdp_cube_end = pdp_cube_sync & bsync & load_din; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + splitw_cnt[7:0] <= {8{1'b0}}; + end else begin + if(splitw_end & bsync & splitw_end_sync & load_din) + splitw_cnt[7:0] <= 8'd0; + else if(splitw_end_sync & bsync & load_din) + splitw_cnt[7:0] <= splitw_cnt + 1; + end +end +assign splitw_end = (splitw_cnt==pooling_splitw_num_cfg[7:0]); +assign splitw_start = (splitw_cnt==8'd0); +//=============================================================== +//config info +// +//--------------------------------------------------------------- +assign non_splitw = pooling_splitw_num_cfg[7:0]==8'd0 ; +assign first_splitw_en = ~non_splitw & splitw_start; +assign last_splitw_en = ~non_splitw & splitw_end; +assign {mon_overlap,overlap[3:0]} = ({1'b0,reg2dp_kernel_width} < reg2dp_kernel_stride_width) ? (reg2dp_kernel_stride_width[3:0] - {1'b0,reg2dp_kernel_width[2:0]}) : ({1'b0,reg2dp_kernel_width[2:0]} - reg2dp_kernel_stride_width[3:0]); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-CORE: should not overflow") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_overlap); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + non_splitw + or reg2dp_cube_in_width + or splitw_end + or reg2dp_kernel_stride_width + or reg2dp_kernel_width + or pooling_lwidth_cfg + or overlap + or splitw_start + or pooling_fwidth_cfg + or pooling_mwidth_cfg + ) begin + if(non_splitw) + pooling_pwidth = reg2dp_cube_in_width[12:0]; + else if(splitw_end) begin + if(reg2dp_kernel_stride_width > {1'b0,reg2dp_kernel_width}) + pooling_pwidth = {3'd0,pooling_lwidth_cfg[9:0]} - {8'd0,overlap[3:0]}; + else + pooling_pwidth = {3'd0,pooling_lwidth_cfg[9:0]} + {8'd0,overlap[3:0]}; + end else if(splitw_start) + pooling_pwidth = {3'd0,pooling_fwidth_cfg[9:0]}; + else begin + if(reg2dp_kernel_stride_width > {1'b0,reg2dp_kernel_width}) + pooling_pwidth = {3'd0,pooling_mwidth_cfg[9:0]} - {8'd0,overlap[3:0]}; + else + pooling_pwidth = {3'd0,pooling_mwidth_cfg[9:0]} + {8'd0,overlap[3:0]}; + end +end +//============================================================== +//enable pdp datapath +//-------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdpw_active_en <= 1'b0; + end else begin + if(pdp_op_start) + pdpw_active_en <= 1'b1; + else if(pdp_cube_end) + pdpw_active_en <= 1'b0; + end +end +//============================================================== +//stride count in padding bits +// +//-------------------------------------------------------------- +//assign padding_left = ((~pdp_op_pending) | (first_splitw_en & (~splitw_end_sync))) ? padding_h_cfg[2:0] : 3'd0; +always @( + non_splitw + or padding_h_cfg + or first_splitw_en + or splitw_end_sync + ) begin + if(non_splitw) + padding_left = padding_h_cfg[2:0]; + else if(first_splitw_en & (~splitw_end_sync)) + padding_left = padding_h_cfg[2:0]; + else + padding_left = 3'd0; +end +//stride ==1 +assign padding_stride1_num = padding_left[2:0]; +//stride ==2 +assign padding_stride2_num = {1'b0,padding_left[2:1]}; +//stride ==3 +assign padding_stride3_num= (padding_left[2:0]>=3'd6) ? 3'd2 : + (padding_left[2:0]>=3'd3) ? 3'd1 : 3'd0; +//stride==4 5 6 7 +assign pooling_stride_h[4:0] = pooling_stride_h_cfg[3:0] + 3'd1; +assign padding_stride4_num = ({1'b0,padding_left[2:0]} > pooling_stride_h_cfg[3:0]) ? 3'd1 : 3'd0; +//number needed for padding in horizental direction +always @( + pooling_stride_h_cfg + or padding_stride1_num + or padding_stride2_num + or padding_stride3_num + or padding_stride4_num + ) begin + case(pooling_stride_h_cfg) + 4'd0: padding_stride_num = padding_stride1_num; + 4'd1: padding_stride_num = padding_stride2_num; + 4'd2: padding_stride_num = padding_stride3_num; + default: padding_stride_num = padding_stride4_num; + endcase +end +assign {mon_strip_xcnt_offset[5:0],strip_xcnt_offset[2:0]} = {5'b0, padding_left} - padding_stride_num * pooling_stride_h; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal1d: shouldn't be overflow") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (|mon_strip_xcnt_offset)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////////////////////////////////////////////////// +// line reg use num calculation, "+1" +//------------------------------------------------ +//stride 1 +assign line_regs_1[2:0] = pooling_size_h_cfg[2:0]; +//stride 2 +assign line_regs_2[2:0] = {1'd0,pooling_size_h_cfg[2:1]}; +//stride 3 +assign line_regs_3[2:0] = (pooling_size_h_cfg[2:0]>3'd5)? 3'd2 : ((pooling_size_h_cfg[2:0]>3'd2)? 3'd1 : 3'd0); +//stride 4 5 6 7 +assign line_regs_4 = ({1'b0,pooling_size_h_cfg[2:0]}>pooling_stride_h_cfg)? 3'd1 : 3'd0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + regs_num[2:0] <= {3{1'b0}}; + end else begin + if(pdp_op_start) + case(pooling_stride_h_cfg) + 4'd0: regs_num[2:0] <= line_regs_1; + 4'd1: regs_num[2:0] <= line_regs_2; + 4'd2: regs_num[2:0] <= line_regs_3; + default: regs_num[2:0] <= line_regs_4; + endcase + end +end +////////////////////////////////////////////////// +//============================================================== +//1D pooling stride/size counter +// +//------------------------------------------------------------- +//stride start +assign load_din = pdp_datin_prdy & pdp_datin_pvld; +assign pooling_size_h[3:0] = pooling_size_h_cfg[2:0] + 3'd1; +assign strip_recieve_done = load_din & pdp_din_lc; +//assign pdp_din_lc = pdp_datin_pd[100]; +assign pdp_din_lc = pdp_datin_pd[1*(8 +3)+12]; +assign stride_end = strip_recieve_done & (strip_xcnt_stride==pooling_stride_h_cfg[3:0]); +assign init_cnt = line_last_stripe_done | pdp_op_start; +always @(*) begin + if(init_cnt) begin + strip_xcnt_stride_f[3:0] = {1'b0,strip_xcnt_offset}; + end else if(stride_end) + strip_xcnt_stride_f[3:0] = 4'd0; + else if(strip_recieve_done) + strip_xcnt_stride_f[3:0] = strip_xcnt_stride + 1; + else + strip_xcnt_stride_f[3:0] = strip_xcnt_stride; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_xcnt_stride[3:0] <= {4{1'b0}}; + end else begin + if ((init_cnt | stride_end | strip_recieve_done) == 1'b1) begin + strip_xcnt_stride[3:0] <= strip_xcnt_stride_f[3:0]; +// VCS coverage off + end else if ((init_cnt | stride_end | strip_recieve_done) == 1'b0) begin + end else begin + strip_xcnt_stride[3:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(init_cnt | stride_end | strip_recieve_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//pooling result ready +assign {mon_overlap_ff[1:0],overlap_ff[2:0]} = {1'b0,pooling_size_h_cfg} - pooling_stride_h_cfg; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_xcnt_psize <= {3{1'b0}}; + end else begin + if(init_cnt) + strip_xcnt_psize[2:0] <= padding_left[2:0]; + else if({1'b0,pooling_size_h_cfg} >= pooling_stride_h_cfg)begin // pooling_size >= stride + if(pooling_1d_rdy) + strip_xcnt_psize <= overlap_ff[2:0]; + else if(strip_recieve_done) + strip_xcnt_psize<= strip_xcnt_psize + 1; + end + else begin // pooling_size < stride + if(strip_xcnt_stride_f <= {1'b0,pooling_size_h_cfg[2:0]}) + strip_xcnt_psize <= strip_xcnt_stride_f[2:0]; + else + strip_xcnt_psize <= 3'd0; + end + end +end +///////////////////////////////////////////////////////// +//input data bubble control logic generation +//------------------------------------------------------- +assign pooling_size[3:0] = pooling_size_h; +assign stride[4:0] = pooling_stride_h; +assign pad_l[2:0] = padding_left; +assign pad_r = reg2dp_pad_right_cfg[2:0]; +//active_data_num_last_pooling = (pad_l + width) % stride; +//element/line num need flush at lint/surface end +always @( + pad_r + or stride_1x + or stride_2x + or stride_3x + or stride_4x + or stride_5x + or stride_6x + or stride_7x + ) begin + if({2'd0,pad_r} < stride_1x[4:0]) + flush_num_cal = 3'd0; + else if({3'd0,pad_r} < stride_2x[5:0]) + flush_num_cal = 3'd1; + else if({4'd0,pad_r} < stride_3x[6:0]) + flush_num_cal = 3'd2; + else if({4'd0,pad_r} < stride_4x[6:0]) + flush_num_cal = 3'd3; + else if({5'd0,pad_r} < stride_5x[7:0]) + flush_num_cal = 3'd4; + else if({5'd0,pad_r} < stride_6x[7:0]) + flush_num_cal = 3'd5; + else if({5'd0,pad_r} < stride_7x[7:0]) + flush_num_cal = 3'd6; + else// if({5'd0,pad_r} = stride_7x[7:0]) + flush_num_cal = 3'd7; +end +//small input detect +assign non_split_small_active = (non_splitw & (~(|reg2dp_cube_in_width[12:3])) & ((reg2dp_cube_in_width[2:0] + reg2dp_pad_left[2:0]) < {1'b0,reg2dp_kernel_width[2:0]})); +assign split_small_active = (~non_splitw) & ((big_stride & ((pooling_lwidth_cfg[9:0] - {6'd0,overlap[3:0]}) < {8'b0,reg2dp_kernel_width[2:0]})) + | ((~big_stride) & ((pooling_lwidth_cfg[9:0] + {6'd0,overlap[3:0]}) < {8'b0,reg2dp_kernel_width[2:0]}))); +//non-split mode cube_width + pad_left + pad_right +assign non_split_w_pl[3:0] = reg2dp_cube_in_width[2:0] + reg2dp_pad_left[2:0]; +assign non_split_w_pl_pr[4:0] = non_split_w_pl[3:0] + {1'b0,reg2dp_pad_right[2:0]}; +//split mode cube_width +/- overlap + pad_right +assign big_stride = (reg2dp_kernel_stride_width[3:0] >= {1'b0,reg2dp_kernel_width}); +assign split_w_olap[5:0] = big_stride ? (pooling_lwidth_cfg[4:0] - {1'd0,overlap[3:0]}) : (pooling_lwidth_cfg[4:0] + {1'd0,overlap[3:0]}); +assign split_w_olap_pr[6:0] = split_w_olap[5:0] + {3'd0,reg2dp_pad_right[2:0]}; +//pad_right remain afrer 1st kernel pooling +always @( + non_split_small_active + or non_split_w_pl_pr + or reg2dp_kernel_width + or split_small_active + or split_w_olap_pr + ) begin + if(non_split_small_active) + pad_r_remain[7:0] = {3'd0,non_split_w_pl_pr[4:0]} - {1'd0,reg2dp_kernel_width[2:0]} ; + else if(split_small_active) + pad_r_remain[7:0] = split_w_olap_pr[6:0] - {4'd0,reg2dp_kernel_width[2:0]} ; + else + pad_r_remain[7:0] = 8'd0 ; +end +//how many need bubble after 1st kernel pooling +always @( + pad_r_remain + or stride_6x + or stride_5x + or stride_4x + or stride_3x + or stride_2x + or stride_1x + ) begin + if(pad_r_remain == stride_6x[7:0]) + samllW_flush_num = 3'd6; + else if(pad_r_remain == stride_5x[7:0]) + samllW_flush_num = 3'd5; + else if(pad_r_remain == {1'd0,stride_4x[6:0]}) + samllW_flush_num = 3'd4; + else if(pad_r_remain == {1'd0,stride_3x[6:0]}) + samllW_flush_num = 3'd3; + else if(pad_r_remain == {2'd0,stride_2x[5:0]}) + samllW_flush_num = 3'd2; + else if(pad_r_remain == {3'd0,stride_1x[4:0]}) + samllW_flush_num = 3'd1; + else// if(pad_r_remain == 8'd0) + samllW_flush_num = 3'd0; +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP cal1d small width in: pad_r overflow") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (non_split_small_active|split_small_active) & (pad_r_remain == stride_7x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//flush num calc +always @( + flush_num_cal + or non_split_small_active + or split_small_active + or samllW_flush_num + ) begin + if(flush_num_cal==3'd0) + flush_num[2:0] = 3'd0; + else if(non_split_small_active | split_small_active) + flush_num[2:0] = samllW_flush_num; + else + flush_num[2:0] = flush_num_cal[2:0]; +end +assign stride_1x[4:0] = stride[4:0]; +assign stride_2x[5:0] = {stride[4:0],1'b0}; +assign stride_3x[6:0] = ( stride_2x+{1'b0,stride[4:0]}); +assign stride_4x[6:0] = {stride[4:0],2'b0}; +assign stride_5x[7:0] = ( stride_4x+{2'd0,stride[4:0]}); +assign stride_6x[7:0] = ( stride_3x+stride_3x); +assign stride_7x[7:0] = ( stride_4x+stride_3x); +//the 1st element/line num need output data +//&Always; +// if(non_splitw | first_splitw_en) +// {mon_first_out_num[0],first_out_num[3:0]} = pooling_size - pad_l; +// else +// {mon_first_out_num[0],first_out_num[3:0]} = {1'b0,pooling_size}; +//&End; +assign kernel_padl[4:0] = pooling_size[3:0] - {1'b0,pad_l[2:0]}; +assign partial_w_last[10:0] = pooling_lwidth_cfg[9:0] + 10'd1; +assign cube_width_in[3:0] = reg2dp_cube_in_width[2:0] + 3'd1; +assign ks_width[4:0] = reg2dp_kernel_stride_width[3:0] + 4'd1; +assign k_add_ks[10:0]= {7'd0,pooling_size[3:0]} + {6'd0,ks_width[4:0]}; +always @( + non_splitw + or non_split_small_active + or cube_width_in + or kernel_padl + or first_splitw_en + or last_splitw_en + or split_small_active + or big_stride + or partial_w_last + or overlap + or k_add_ks + or pooling_size + ) begin + if(non_splitw) begin + if(non_split_small_active) + {mon_first_out_num[6:0],first_out_num[4:0]} = {8'd0,cube_width_in[3:0]}; + else + {mon_first_out_num[6:0],first_out_num[4:0]} = {7'd0,kernel_padl[4:0]}; + end else begin + if(first_splitw_en) + {mon_first_out_num[6:0],first_out_num[4:0]} = {7'd0,kernel_padl[4:0]}; + else if(last_splitw_en & split_small_active) begin + if(big_stride) + {mon_first_out_num[6:0],first_out_num[4:0]} = {1'b0,partial_w_last[10:0]}; + else + {mon_first_out_num[6:0],first_out_num[4:0]} = partial_w_last[10:0] + {7'd0,overlap[3:0]}; + end else begin + if(big_stride) + {mon_first_out_num[6:0],first_out_num[4:0]} = {1'b0,k_add_ks};//{7'd0,pooling_size[3:0]} + {6'd0,ks_width[4:0]}; + else + {mon_first_out_num[6:0],first_out_num[4:0]} = {8'd0,pooling_size[3:0]}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + need_bubble <= 1'b0; + bubble_num[2:0] <= {3{1'b0}}; + end else begin + if(pdp_cube_end) begin + if(|flush_num) begin + need_bubble <= 1'b1; + bubble_num[2:0] <= flush_num; + end else begin + need_bubble <= 1'b0; + bubble_num[2:0] <= 3'd0; + end + end else if(non_splitw) begin + if(pdp_op_start) begin + if({2'd0,flush_num} >= first_out_num) begin + need_bubble <= 1'b1; + bubble_num[2:0] <= flush_num - first_out_num[2:0] + 1'b1; + end else begin + need_bubble <= 1'b0; + bubble_num[2:0] <= 3'd0; + end + end + end else begin//split mode + if(splitw_end) begin + if({2'd0,flush_num} >= first_out_num) begin + need_bubble <= 1'b1; + bubble_num[2:0] <= flush_num - first_out_num[2:0] + 1'b1; + end else begin + need_bubble <= 1'b0; + bubble_num[2:0] <= 3'd0; + end + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable <= 1'b0; + end else begin + if(pdp_cube_end & (|flush_num)) + cur_datin_disable <= 1'b1; + else if(non_splitw) begin + if(line_last_stripe_done & need_bubble) + cur_datin_disable <= 1'b1; + else if(bubble_en_end) + cur_datin_disable <= 1'b0; + end else begin + if(last_splitw_en & line_last_stripe_done & need_bubble) + cur_datin_disable <= 1'b1; + else if(bubble_en_end) + cur_datin_disable <= 1'b0; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_cnt <= {5{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(last_c) + channel_cnt <= 5'd0; + else if(pdp_datin_prdy_1) + channel_cnt <= channel_cnt + 1'b1; + end else + channel_cnt <= 5'd0; + end +end +//: my $Enum = 8/1 -1; +//: print " assign last_c = (channel_cnt==5'd${Enum}) & pdp_datin_prdy_1; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign last_c = (channel_cnt==5'd7) & pdp_datin_prdy_1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_cnt <= {3{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(bubble_en_end) + bubble_cnt <= 3'd0; + else if(last_c) + bubble_cnt <= bubble_cnt + 1'b1; + end else + bubble_cnt <= 3'd0; + end +end +//assign bubble_en_end = (bubble_cnt == (bubble_num-1'b1)) & last_c; +assign bubble_num_dec[2:0] = bubble_num[2:0]-1'b1; +assign bubble_en_end = (bubble_cnt == bubble_num_dec) & last_c; +////////////////////////////////////////////////////// +//last line element output en during cur line element comming +//---------------------------------------------------- +//subcube end flag for last_out_en control in the sub-cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + subcube_end_flag <= 1'b0; + end else begin + if(splitw_end_sync & bsync) + subcube_end_flag <= 1'b1; + else if(load_din) + subcube_end_flag <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_en <= 1'b0; + end else begin + if(last_out_done) + last_out_en <= 1'b0; + else if(pdp_cube_end) + last_out_en <= 1'b0; + else if((first_out_num != 5'd1) & (~subcube_end_flag)) begin + if(need_bubble) begin + if(bubble_en_end) + last_out_en <= 1'b1; + end else if(|flush_num) begin + if(non_splitw & line_last_stripe_done) + last_out_en <= 1'b1; + else if(~non_splitw & last_splitw_en & line_last_stripe_done) + last_out_en <= 1'b1; + end + end else + last_out_en <= 1'b0; + end +end +//assign {mon_first_out_num_dec2[1:0],first_out_num_dec2[2:0]} = first_out_num - 4'd2; +assign {mon_first_out_num_dec2[2:0],first_out_num_dec2[2:0]} = need_bubble ? (first_out_num - 5'd2) : ({2'b0,flush_num} - 5'd1); +//assign {mon_first_out_num_dec2[1:0],first_out_num_dec2[2:0]} = first_out_num - 4'd1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_cnt <= {3{1'b0}}; + end else begin + if(last_out_en) begin + if(strip_recieve_done) begin + if(last_out_done) + last_out_cnt <= 3'd0; + else + last_out_cnt <= last_out_cnt + 1'b1; + end + end else + last_out_cnt <= 3'd0; + end +end +assign last_out_done = (last_out_cnt[2:0] == first_out_num_dec2[2:0]) & strip_recieve_done & last_out_en; +assign pooling_1d_rdy = (strip_xcnt_psize== pooling_size_h_cfg[2:0]) & strip_recieve_done; +///////////////////////////////////////////////////////// +//strip count in total width +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_cnt_total[12:0] <= {13{1'b0}}; + end else begin + if(init_cnt) + strip_cnt_total[12:0] <= 13'd0; + else if(strip_recieve_done) + strip_cnt_total[12:0] <= strip_cnt_total + 1; + end +end +assign strip_width_end = (strip_cnt_total == pooling_pwidth); +assign line_last_stripe_done = (strip_width_end & strip_recieve_done); +//----------------------- +//flag the last one pooling in width direction +//----------------------- +assign {mon_rest_width,rest_width[12:0]} = pooling_pwidth - strip_cnt_total; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal1d: shouldn't be overflow") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, (pdp_op_pending & mon_rest_width)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign rest_width_use[13:0] = (non_splitw | splitw_end) ? (rest_width + {10'd0,reg2dp_pad_right_cfg}) : {1'b0,rest_width}; +assign last_pooling_flag = rest_width_use[13:0] <= {11'd0,pooling_size_h_cfg}; +//====================================================================== +//pooling 1D unit counter +// +//---------------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit1d_cnt_stride[2:0] <= {3{1'b0}}; + end else begin +//if(pdp_op_start) + if(init_cnt) begin + unit1d_cnt_stride[2:0] <= padding_stride_num; + end else if(stride_end) begin + if(unit1d_cnt_stride == regs_num) + unit1d_cnt_stride[2:0] <= 3'd0; + else + unit1d_cnt_stride[2:0] <= unit1d_cnt_stride +1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit1d_cnt_pooling[2:0] <= {3{1'b0}}; + end else begin +//if(pdp_op_start) + if(init_cnt) + unit1d_cnt_pooling[2:0] <= 0; + else if(pooling_1d_rdy | line_ldata_valid) begin + if(unit1d_cnt_pooling == regs_num) + unit1d_cnt_pooling[2:0] <= 0; + else + unit1d_cnt_pooling[2:0] <= unit1d_cnt_pooling + 1; + end + end +end +assign line_ldata_valid = line_last_stripe_done; +//: foreach my $i (0..7) { +//: my $j = $i -1; +//: print "assign init_unit1d_set[$i] = init_cnt & (padding_stride_num>=${i}) & (pout_width_cur >= 3'd${i}); \n"; +//: if($i==0){ +//: print "assign unit1d_set_trig[0] = stride_end & (unit1d_cnt_stride == regs_num) & (~last_pooling_flag);\n"; +//: } else { +//: print "assign unit1d_set_trig[${i}]= stride_end & (unit1d_cnt_stride == 3'd${j}) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag);\n"; +//: } +//: print qq( +//: assign unit1d_set[${i}] = unit1d_set_trig[${i}] | init_unit1d_set[${i}]; +//: assign unit1d_clr[${i}] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd${i})) | line_ldata_valid; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: if (!nvdla_core_rstn) begin +//: unit1d_en[$i] <= 1'b0; +//: end else begin +//: if(pdp_cube_end) +//: unit1d_en[$i] <= 1'b0; +//: else if(unit1d_set[${i}]) +//: unit1d_en[$i] <= 1'b1; +//: else if(unit1d_clr[${i}]) +//: unit1d_en[$i] <= 1'b0; +//: end +//: ); +//: } +//: foreach my $i (0..7) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: if (!nvdla_core_rstn) begin +//: pooling_din_1st_$i <= 1'b0; +//: end else begin +//: if(unit1d_set[${i}]) +//: pooling_din_1st_$i <= 1'b1; +//: else if(strip_recieve_done) +//: pooling_din_1st_$i <= 1'b0; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign init_unit1d_set[0] = init_cnt & (padding_stride_num>=0) & (pout_width_cur >= 3'd0); +assign unit1d_set_trig[0] = stride_end & (unit1d_cnt_stride == regs_num) & (~last_pooling_flag); + +assign unit1d_set[0] = unit1d_set_trig[0] | init_unit1d_set[0]; +assign unit1d_clr[0] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd0)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[0] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[0] <= 1'b0; +else if(unit1d_set[0]) +unit1d_en[0] <= 1'b1; +else if(unit1d_clr[0]) +unit1d_en[0] <= 1'b0; +end +assign init_unit1d_set[1] = init_cnt & (padding_stride_num>=1) & (pout_width_cur >= 3'd1); +assign unit1d_set_trig[1]= stride_end & (unit1d_cnt_stride == 3'd0) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[1] = unit1d_set_trig[1] | init_unit1d_set[1]; +assign unit1d_clr[1] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd1)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[1] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[1] <= 1'b0; +else if(unit1d_set[1]) +unit1d_en[1] <= 1'b1; +else if(unit1d_clr[1]) +unit1d_en[1] <= 1'b0; +end +assign init_unit1d_set[2] = init_cnt & (padding_stride_num>=2) & (pout_width_cur >= 3'd2); +assign unit1d_set_trig[2]= stride_end & (unit1d_cnt_stride == 3'd1) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[2] = unit1d_set_trig[2] | init_unit1d_set[2]; +assign unit1d_clr[2] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd2)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[2] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[2] <= 1'b0; +else if(unit1d_set[2]) +unit1d_en[2] <= 1'b1; +else if(unit1d_clr[2]) +unit1d_en[2] <= 1'b0; +end +assign init_unit1d_set[3] = init_cnt & (padding_stride_num>=3) & (pout_width_cur >= 3'd3); +assign unit1d_set_trig[3]= stride_end & (unit1d_cnt_stride == 3'd2) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[3] = unit1d_set_trig[3] | init_unit1d_set[3]; +assign unit1d_clr[3] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd3)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[3] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[3] <= 1'b0; +else if(unit1d_set[3]) +unit1d_en[3] <= 1'b1; +else if(unit1d_clr[3]) +unit1d_en[3] <= 1'b0; +end +assign init_unit1d_set[4] = init_cnt & (padding_stride_num>=4) & (pout_width_cur >= 3'd4); +assign unit1d_set_trig[4]= stride_end & (unit1d_cnt_stride == 3'd3) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[4] = unit1d_set_trig[4] | init_unit1d_set[4]; +assign unit1d_clr[4] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd4)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[4] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[4] <= 1'b0; +else if(unit1d_set[4]) +unit1d_en[4] <= 1'b1; +else if(unit1d_clr[4]) +unit1d_en[4] <= 1'b0; +end +assign init_unit1d_set[5] = init_cnt & (padding_stride_num>=5) & (pout_width_cur >= 3'd5); +assign unit1d_set_trig[5]= stride_end & (unit1d_cnt_stride == 3'd4) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[5] = unit1d_set_trig[5] | init_unit1d_set[5]; +assign unit1d_clr[5] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd5)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[5] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[5] <= 1'b0; +else if(unit1d_set[5]) +unit1d_en[5] <= 1'b1; +else if(unit1d_clr[5]) +unit1d_en[5] <= 1'b0; +end +assign init_unit1d_set[6] = init_cnt & (padding_stride_num>=6) & (pout_width_cur >= 3'd6); +assign unit1d_set_trig[6]= stride_end & (unit1d_cnt_stride == 3'd5) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[6] = unit1d_set_trig[6] | init_unit1d_set[6]; +assign unit1d_clr[6] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd6)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[6] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[6] <= 1'b0; +else if(unit1d_set[6]) +unit1d_en[6] <= 1'b1; +else if(unit1d_clr[6]) +unit1d_en[6] <= 1'b0; +end +assign init_unit1d_set[7] = init_cnt & (padding_stride_num>=7) & (pout_width_cur >= 3'd7); +assign unit1d_set_trig[7]= stride_end & (unit1d_cnt_stride == 3'd6) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag); + +assign unit1d_set[7] = unit1d_set_trig[7] | init_unit1d_set[7]; +assign unit1d_clr[7] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd7)) | line_ldata_valid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +unit1d_en[7] <= 1'b0; +end else begin +if(pdp_cube_end) +unit1d_en[7] <= 1'b0; +else if(unit1d_set[7]) +unit1d_en[7] <= 1'b1; +else if(unit1d_clr[7]) +unit1d_en[7] <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_0 <= 1'b0; +end else begin +if(unit1d_set[0]) +pooling_din_1st_0 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_0 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_1 <= 1'b0; +end else begin +if(unit1d_set[1]) +pooling_din_1st_1 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_1 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_2 <= 1'b0; +end else begin +if(unit1d_set[2]) +pooling_din_1st_2 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_2 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_3 <= 1'b0; +end else begin +if(unit1d_set[3]) +pooling_din_1st_3 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_3 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_4 <= 1'b0; +end else begin +if(unit1d_set[4]) +pooling_din_1st_4 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_4 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_5 <= 1'b0; +end else begin +if(unit1d_set[5]) +pooling_din_1st_5 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_5 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_6 <= 1'b0; +end else begin +if(unit1d_set[6]) +pooling_din_1st_6 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_6 <= 1'b0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +if (!nvdla_core_rstn) begin +pooling_din_1st_7 <= 1'b0; +end else begin +if(unit1d_set[7]) +pooling_din_1st_7 <= 1'b1; +else if(strip_recieve_done) +pooling_din_1st_7 <= 1'b0; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////////////////// +//assign datin_buf = pdp_datin_pd[96:0]; +//assign datin_buf_1 = {pdp_datin_pd[96:88],pdp_datin_pd0[87:0]}; +assign datin_buf = pdp_datin_pd[1*(8 +3)+8:0]; +assign pdp_datin_prdy_1 = &unit1d_prdy & pdp_info_in_prdy; +assign pdp_full_pvld = pdp_datin_pvld | cur_datin_disable; +assign unit1d_pvld[0] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:1]}); +assign unit1d_pvld[1] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:2],unit1d_prdy[0]}); +assign unit1d_pvld[2] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:3],unit1d_prdy[1:0]}); +assign unit1d_pvld[3] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:4],unit1d_prdy[2:0]}); +assign unit1d_pvld[4] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:5],unit1d_prdy[3:0]}); +assign unit1d_pvld[5] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:6],unit1d_prdy[4:0]}); +assign unit1d_pvld[6] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7 ],unit1d_prdy[5:0]}); +assign unit1d_pvld[7] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[6:0]}); +//============================================================ +//pdp info pipe +assign pdp_info_in_pvld = pdp_full_pvld & (&unit1d_prdy); +assign pdp_info_in_pd = {pdp_din_lc,last_c,last_out_en,cur_datin_disable,pooling_din_last[7:0]}; +NV_NVDLA_PDP_cal1d_info_fifo u_NV_NVDLA_PDP_cal1d_info_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pdp_info_in_prdy (pdp_info_in_prdy) //|> w + ,.pdp_info_in_pvld (pdp_info_in_pvld) //|< w + ,.pdp_info_in_pd (pdp_info_in_pd[11:0]) //|< w + ,.pdp_info_out_prdy (pdp_info_out_prdy) //|< w + ,.pdp_info_out_pvld (pdp_info_out_pvld) //|> w + ,.pdp_info_out_pd (pdp_info_out_pd[11:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign pdp_info_out_prdy = unit1d_out_prdy_use & (&unit1d_out_pvld); +assign {pdp_din_lc_sync,last_c_sync, last_out_en_sync,cur_datin_disable_sync,pooling_din_last_sync[7:0]} = pdp_info_out_pd[11:0]; +//============================================================ +// &Instance +// +//------------------------------------------------------------ +//assertion trace NVDLA_HLS_ADD17_LATENCY latency change from 4 +//: foreach my $i (0..7) { +//: print qq( +//: assign pooling_din_last[$i] = unit1d_en[$i] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd$i)) | strip_width_end) ; +//: +//: NV_NVDLA_PDP_CORE_unit1d unit1d_$i ( +//: .nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.average_pooling_en (average_pooling_en) //|< w +//: ,.cur_datin_disable (cur_datin_disable) //|< r +//: ,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +//: ,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +//: ,.pdma2pdp_pvld (unit1d_pvld[$i]) //|< w +//: ,.pdp_din_lc_f (pdp_din_lc) //|< w +//: ,.pooling_din_1st ((pooling_din_1st_$i )) //|< r +//: ,.pooling_din_last (pooling_din_last[$i]) //|< w +//: ,.pooling_out_prdy (unit1d_out_prdy[$i]) //|< w +//: ,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +//: ,.pooling_unit_en (unit1d_en[$i]) //|< r +//: //,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//: //,.reg2dp_int8_en (reg2dp_int8_en) //|< i +//: ,.pdma2pdp_prdy (unit1d_prdy[$i]) //|> w +//: ,.pooling_out (unit1d_out_$i) //|> w +//: ,.pooling_out_pvld (unit1d_out_pvld[$i]) //|> w +//: ); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pooling_din_last[0] = unit1d_en[0] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd0)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_0 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[0]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_0 )) //|< r +,.pooling_din_last (pooling_din_last[0]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[0]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[0]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[0]) //|> w +,.pooling_out (unit1d_out_0) //|> w +,.pooling_out_pvld (unit1d_out_pvld[0]) //|> w +); + +assign pooling_din_last[1] = unit1d_en[1] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd1)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_1 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[1]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_1 )) //|< r +,.pooling_din_last (pooling_din_last[1]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[1]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[1]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[1]) //|> w +,.pooling_out (unit1d_out_1) //|> w +,.pooling_out_pvld (unit1d_out_pvld[1]) //|> w +); + +assign pooling_din_last[2] = unit1d_en[2] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd2)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_2 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[2]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_2 )) //|< r +,.pooling_din_last (pooling_din_last[2]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[2]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[2]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[2]) //|> w +,.pooling_out (unit1d_out_2) //|> w +,.pooling_out_pvld (unit1d_out_pvld[2]) //|> w +); + +assign pooling_din_last[3] = unit1d_en[3] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd3)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_3 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[3]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_3 )) //|< r +,.pooling_din_last (pooling_din_last[3]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[3]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[3]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[3]) //|> w +,.pooling_out (unit1d_out_3) //|> w +,.pooling_out_pvld (unit1d_out_pvld[3]) //|> w +); + +assign pooling_din_last[4] = unit1d_en[4] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd4)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_4 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[4]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_4 )) //|< r +,.pooling_din_last (pooling_din_last[4]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[4]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[4]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[4]) //|> w +,.pooling_out (unit1d_out_4) //|> w +,.pooling_out_pvld (unit1d_out_pvld[4]) //|> w +); + +assign pooling_din_last[5] = unit1d_en[5] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd5)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_5 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[5]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_5 )) //|< r +,.pooling_din_last (pooling_din_last[5]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[5]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[5]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[5]) //|> w +,.pooling_out (unit1d_out_5) //|> w +,.pooling_out_pvld (unit1d_out_pvld[5]) //|> w +); + +assign pooling_din_last[6] = unit1d_en[6] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd6)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_6 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[6]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_6 )) //|< r +,.pooling_din_last (pooling_din_last[6]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[6]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[6]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[6]) //|> w +,.pooling_out (unit1d_out_6) //|> w +,.pooling_out_pvld (unit1d_out_pvld[6]) //|> w +); + +assign pooling_din_last[7] = unit1d_en[7] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd7)) | strip_width_end) ; + +NV_NVDLA_PDP_CORE_unit1d unit1d_7 ( +.nvdla_core_clk (nvdla_core_clk) //|< i +,.nvdla_core_rstn (nvdla_core_rstn) //|< i +,.average_pooling_en (average_pooling_en) //|< w +,.cur_datin_disable (cur_datin_disable) //|< r +,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +,.pdma2pdp_pvld (unit1d_pvld[7]) //|< w +,.pdp_din_lc_f (pdp_din_lc) //|< w +,.pooling_din_1st ((pooling_din_1st_7 )) //|< r +,.pooling_din_last (pooling_din_last[7]) //|< w +,.pooling_out_prdy (unit1d_out_prdy[7]) //|< w +,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +,.pooling_unit_en (unit1d_en[7]) //|< r +//,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//,.reg2dp_int8_en (reg2dp_int8_en) //|< i +,.pdma2pdp_prdy (unit1d_prdy[7]) //|> w +,.pooling_out (unit1d_out_7) //|> w +,.pooling_out_pvld (unit1d_out_pvld[7]) //|> w +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////////////////////// +assign unit1d_out_prdy[0] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:1]}); +assign unit1d_out_prdy[1] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:2],unit1d_out_pvld[0]}); +assign unit1d_out_prdy[2] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:3],unit1d_out_pvld[1:0]}); +assign unit1d_out_prdy[3] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:4],unit1d_out_pvld[2:0]}); +assign unit1d_out_prdy[4] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:5],unit1d_out_pvld[3:0]}); +assign unit1d_out_prdy[5] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:6],unit1d_out_pvld[4:0]}); +assign unit1d_out_prdy[6] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7 ],unit1d_out_pvld[5:0]}); +assign unit1d_out_prdy[7] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[6:0]}); +assign unit1d_out_pvld_use = &unit1d_out_pvld & pdp_info_out_pvld; +//========================================================= +//1d pooling output +// +//--------------------------------------------------------- +//unit1d count +assign pooling1d_out_v_norm = ((|pooling_din_last_sync) & pdp_din_lc_sync & (~cur_datin_disable_sync) & unit1d_out_pvld_use & unit1d_out_prdy_use); +assign pooling1d_out_v_disable = (cur_datin_disable_sync & last_c_sync) & unit1d_out_pvld_use & unit1d_out_prdy_use; +assign pooling1d_out_v_lastout = (last_out_en_sync & pdp_din_lc_sync & unit1d_out_pvld_use & unit1d_out_prdy_use); +assign pooling1d_out_v = pooling1d_out_v_norm | pooling1d_out_v_disable | pooling1d_out_v_lastout; +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// +//end of line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_dat_cnt[12:0] <= {13{1'b0}}; + end else begin + if(wr_line_dat_done) + wr_line_dat_cnt[12:0] <= 0; + else if(pooling1d_out_v) + wr_line_dat_cnt[12:0] <= wr_line_dat_cnt + 1; + end +end +assign wr_line_dat_done = (wr_line_dat_cnt==pout_width_cur) & pooling1d_out_v; +//end of surface +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_cnt <= {13{1'b0}}; + end else begin + if(wr_surface_dat_done) + wr_surface_dat_cnt <= 13'd0; + else if(wr_line_dat_done) + wr_surface_dat_cnt <= wr_surface_dat_cnt + 13'd1; + end +end +assign last_line_in = (wr_surface_dat_cnt==reg2dp_cube_in_height[12:0]); +assign wr_surface_dat_done = wr_line_dat_done & last_line_in; +//end of splitw +//assign cube_out_channel[13:0]= pooling_channel_cfg[12:0] + 1'b1; +assign cube_out_channel[12:0]= pooling_channel_cfg[12:0]; +////16bits: INT16 or FP16 +//assign {mon_surface_num_0,surface_num_0[9:0]} = cube_out_channel[13:4] + {9'd0,(|cube_out_channel[3:0])}; +////8bits: INT8 +//assign surface_num_1[9:0] = {1'b0,cube_out_channel[13:5]} + (|cube_out_channel[4:0]); +//assign surface_num = (reg2dp_input_data[1:0] == 2'h0 )? surface_num_1 : surface_num_0; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "assign surface_num = cube_out_channel[12:${k}]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign surface_num = cube_out_channel[12:3]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surface_cnt_rd <= 0; + end else begin + if(wr_subcube_dat_done) + surface_cnt_rd <= 0; + else if(wr_surface_dat_done) + surface_cnt_rd <= surface_cnt_rd + 1; + end +end +//assign wr_subcube_dat_done = ((surface_num-1)==surface_cnt_rd) & wr_surface_dat_done; +assign wr_subcube_dat_done = (surface_num==surface_cnt_rd) & wr_surface_dat_done; +//total cube done +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_splitc_cnt[7:0] <= {8{1'b0}}; + end else begin + if(wr_total_cube_done) + wr_splitc_cnt[7:0] <= 8'd0; + else if(wr_subcube_dat_done) + wr_splitc_cnt[7:0] <= wr_splitc_cnt + 1; + end +end +assign wr_total_cube_done = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & wr_subcube_dat_done; +//------------------------------------------------- +//split width selection +assign splitw_enable = (pooling_splitw_num_cfg!=8'd0); +assign last_splitw = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & splitw_enable; +assign first_splitw = (wr_splitc_cnt==8'd0) & splitw_enable; +assign pout_width_cur[12:0]= (~splitw_enable) ? reg2dp_cube_out_width[12:0] : + (last_splitw ? {3'd0,pooling_out_lwidth_cfg[9:0]} : + first_splitw ? {3'd0,pooling_out_fwidth_cfg[9:0]} : + {3'd0,pooling_out_mwidth_cfg[9:0]}); +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_out_cnt[2:0] <= {3{1'b0}}; + end else begin + if(pdp_op_start) + pooling_out_cnt[2:0] <= 3'd0; + else if(pooling1d_out_v) begin + if((pooling_out_cnt == regs_num) | wr_line_dat_done) + pooling_out_cnt[2:0] <= 3'd0; + else + pooling_out_cnt[2:0] <= pooling_out_cnt + 3'd1 ; + end + end +end +always @(*) begin + case(pooling_out_cnt) + 3'd0 : unit1d_actv_out_f = unit1d_out_0; + 3'd1 : unit1d_actv_out_f = unit1d_out_1; + 3'd2 : unit1d_actv_out_f = unit1d_out_2; + 3'd3 : unit1d_actv_out_f = unit1d_out_3; + 3'd4 : unit1d_actv_out_f = unit1d_out_4; + 3'd5 : unit1d_actv_out_f = unit1d_out_5; + 3'd6 : unit1d_actv_out_f = unit1d_out_6; + 3'd7 : unit1d_actv_out_f = unit1d_out_7; +//VCS coverage off +//default : unit1d_actv_out_f = 92'd0; + default : unit1d_actv_out_f = 0; +//VCS coverage on + endcase +end +assign unit1d_out_prdy_use = unit1d_actv_out_prdy; +assign unit1d_actv_out_pvld = unit1d_out_pvld_use & ((|pooling_din_last_sync) | cur_datin_disable_sync | last_out_en_sync); +assign unit1d_actv_out = unit1d_actv_out_f; +//================================= +//padding value in h direction under average mode +// +//---------------------------------- +//padding value 1x,2x,3x,4x,5x,6x,7x table +always @(*) begin + case(pad_table_index) + 3'd1: pad_table_out = reg2dp_pad_value_1x_cfg[18:0]; //1x + 3'd2: pad_table_out = reg2dp_pad_value_2x_cfg[18:0]; //2x + 3'd3: pad_table_out = reg2dp_pad_value_3x_cfg[18:0]; //3x + 3'd4: pad_table_out = reg2dp_pad_value_4x_cfg[18:0]; //4x + 3'd5: pad_table_out = reg2dp_pad_value_5x_cfg[18:0]; //5x + 3'd6: pad_table_out = reg2dp_pad_value_6x_cfg[18:0]; //6x + 3'd7: pad_table_out = reg2dp_pad_value_7x_cfg[18:0]; //7x + default:pad_table_out = 19'd0; + endcase +end +assign loading_en = unit1d_actv_out_pvld & unit1d_actv_out_prdy; +//: my $s = "\$signed"; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print "assign {mon_unit1d_actv_data_8bit_${m}_ff[1:0],unit1d_actv_data_8bit_${m}_ff} = $s({{1{unit1d_actv_out[(${b}+3)*${m}+(${b}+3)-1]}},unit1d_actv_out[(${b}+3)*${m}+(${b}+3)-1:(${b}+3)*${m}] }) + $s({pad_table_out[10], pad_table_out[10:0]}); \n"; +//: print "assign {mon_unit1d_actv_data_8bit_${m}[1:0],unit1d_actv_data_8bit_${m}} = padding_here_int8 ? {mon_unit1d_actv_data_8bit_${m}_ff[1:0],unit1d_actv_data_8bit_${m}_ff} : {2'd0,unit1d_actv_out[(${b}+3)*${m}+(${b}+3)-1:(${b}+3)*${m}] }; \n"; +//: } +//: print "assign padding_here = (pooling_type_cfg== 2'h0 ) & (unit1d_actv_out[${k}*(${b}+3)+2:${k}*(${b}+3)] != pooling_size_h_cfg); \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign {mon_unit1d_actv_data_8bit_0_ff[1:0],unit1d_actv_data_8bit_0_ff} = $signed({{1{unit1d_actv_out[(8+3)*0+(8+3)-1]}},unit1d_actv_out[(8+3)*0+(8+3)-1:(8+3)*0] }) + $signed({pad_table_out[10], pad_table_out[10:0]}); +assign {mon_unit1d_actv_data_8bit_0[1:0],unit1d_actv_data_8bit_0} = padding_here_int8 ? {mon_unit1d_actv_data_8bit_0_ff[1:0],unit1d_actv_data_8bit_0_ff} : {2'd0,unit1d_actv_out[(8+3)*0+(8+3)-1:(8+3)*0] }; +assign padding_here = (pooling_type_cfg== 2'h0 ) & (unit1d_actv_out[1*(8+3)+2:1*(8+3)] != pooling_size_h_cfg); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign padding_here_int8 = padding_here; +assign {mon_pad_table_index[0],pad_table_index[2:0]} = pooling_size_h_cfg - unit1d_actv_out[1*(8 +3)+2:1*(8 +3)]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal1d: pooling size should not less than active num") zzz_assert_never_11x (nvdla_core_clk, `ASSERT_RESET, (loading_en & mon_pad_table_index)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling1d_data_pad <= 0; + end else begin + if(loading_en) begin + pooling1d_data_pad <= { +//: my $k = 1; +//: my $b = 8; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print "{{3{unit1d_actv_data_8bit_${i}[${b}+2]}}, unit1d_actv_data_8bit_${i}[${b}+2:0]}, \n"; +//: } +//: } +//: print "{{3{unit1d_actv_data_8bit_0[${b}+2]}}, unit1d_actv_data_8bit_0[${b}+2:0]}}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +{{3{unit1d_actv_data_8bit_0[8+2]}}, unit1d_actv_data_8bit_0[8+2:0]}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling1d_data_pad_vld <= 1'b0; + end else begin + if(unit1d_actv_out_pvld) + pooling1d_data_pad_vld <= 1'b1; + else if(pooling1d_data_pad_rdy) + pooling1d_data_pad_vld <= 1'b0; + end +end +assign unit1d_actv_out_prdy = (~pooling1d_data_pad_vld | pooling1d_data_pad_rdy); +//================================= +//pad_value logic for fp16 average pooling +//---------------------------------- +assign average_pooling_en = (pooling_type_cfg== 2'h0 ); +///////////////////////////////////////////////////////////////////////////////////// +//================================= +//pooling output +// +//---------------------------------- +assign pooling1d_pd = pooling1d_data_pad; +assign pooling1d_pvld = pooling1d_data_pad_vld; +assign pooling1d_data_pad_rdy= pooling1d_prdy; +//============== +//function points +//============== +// max/min/average pooling +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_max_pooling__1_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ); +// endproperty +// // Cover 1 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 )" +// FUNCPOINT_PDP_feature__int16_max_pooling__1_COV : cover property (PDP_feature__int16_max_pooling__1_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_max_pooling__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h1 ); + endproperty +// Cover 2 : "pdp_op_start & (pooling_type_cfg== 2'h1 )" + FUNCPOINT_PDP_feature__int8_max_pooling__2_COV : cover property (PDP_feature__int8_max_pooling__2_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_min_pooling__4_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ); +// endproperty +// // Cover 4 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 )" +// FUNCPOINT_PDP_feature__int16_min_pooling__4_COV : cover property (PDP_feature__int16_min_pooling__4_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_min_pooling__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h2 ); + endproperty +// Cover 5 : "pdp_op_start & (pooling_type_cfg== 2'h2 )" + FUNCPOINT_PDP_feature__int8_min_pooling__5_COV : cover property (PDP_feature__int8_min_pooling__5_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_average_pooling__7_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h0 ); +// endproperty +// // Cover 7 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h0 )" +// FUNCPOINT_PDP_feature__int16_average_pooling__7_COV : cover property (PDP_feature__int16_average_pooling__7_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_average_pooling__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h0 ); + endproperty +// Cover 8 : "pdp_op_start & (pooling_type_cfg== 2'h0 )" + FUNCPOINT_PDP_feature__int8_average_pooling__8_COV : cover property (PDP_feature__int8_average_pooling__8_cov); + `endif +`endif +//VCS coverage on +////pooling in inactive channel +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_average_pooling_in_inactive_channel__11_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & average_pooling_en & reg2dp_int16_en & (~(&pooling_channel_cfg[4:0])); +// endproperty +// // Cover 11 : "pdp_op_start & average_pooling_en & reg2dp_int16_en & (~(&pooling_channel_cfg[4:0]))" +// FUNCPOINT_PDP_feature__int16_average_pooling_in_inactive_channel__11_COV : cover property (PDP_feature__int16_average_pooling_in_inactive_channel__11_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_average_pooling_in_inactive_channel__12_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & average_pooling_en & (~(&pooling_channel_cfg[4:0])); + endproperty +// Cover 12 : "pdp_op_start & average_pooling_en & (~(&pooling_channel_cfg[4:0]))" + FUNCPOINT_PDP_feature__int8_average_pooling_in_inactive_channel__12_COV : cover property (PDP_feature__int8_average_pooling_in_inactive_channel__12_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_max_pooling_in_inactive_channel__14_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0])); +// endproperty +// // Cover 14 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0]))" +// FUNCPOINT_PDP_feature__int16_max_pooling_in_inactive_channel__14_COV : cover property (PDP_feature__int16_max_pooling_in_inactive_channel__14_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_max_pooling_in_inactive_channel__15_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0])); + endproperty +// Cover 15 : "pdp_op_start & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0]))" + FUNCPOINT_PDP_feature__int8_max_pooling_in_inactive_channel__15_COV : cover property (PDP_feature__int8_max_pooling_in_inactive_channel__15_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_min_pooling_in_inactive_channel__17_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0])); +// endproperty +// // Cover 17 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0]))" +// FUNCPOINT_PDP_feature__int16_min_pooling_in_inactive_channel__17_COV : cover property (PDP_feature__int16_min_pooling_in_inactive_channel__17_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_min_pooling_in_inactive_channel__18_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0])); + endproperty +// Cover 18 : "pdp_op_start & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0]))" + FUNCPOINT_PDP_feature__int8_min_pooling_in_inactive_channel__18_COV : cover property (PDP_feature__int8_min_pooling_in_inactive_channel__18_cov); + `endif +`endif +//VCS coverage on +/////////////// +//1*1*1 cube input +/////////////// +////1*1*1 cube input for nonsplit mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_average_pooling__21_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & non_splitw & average_pooling_en & reg2dp_int16_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 21 : "pdp_op_start & non_splitw & average_pooling_en & reg2dp_int16_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_average_pooling__21_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_average_pooling__21_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_average_pooling__22_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & non_splitw & average_pooling_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 22 : "pdp_op_start & non_splitw & average_pooling_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_average_pooling__22_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_average_pooling__22_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_max_pooling__24_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 24 : "pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_max_pooling__24_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_max_pooling__24_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_max_pooling__25_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & non_splitw & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 25 : "pdp_op_start & non_splitw & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_max_pooling__25_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_max_pooling__25_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_min_pooling__27_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 27 : "pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_min_pooling__27_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_min_pooling__27_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_min_pooling__28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & non_splitw & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 28 : "pdp_op_start & non_splitw & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_min_pooling__28_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_min_pooling__28_cov); + `endif +`endif +//VCS coverage on +//1*1*1 cube input for split 2 mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split2_average_pooling__30_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 30 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split2_average_pooling__30_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split2_average_pooling__30_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split2_average_pooling__31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 31 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split2_average_pooling__31_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split2_average_pooling__31_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split2_max_pooling__33_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 33 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split2_max_pooling__33_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split2_max_pooling__33_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split2_max_pooling__34_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 34 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split2_max_pooling__34_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split2_max_pooling__34_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split2_min_pooling__36_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 36 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split2_min_pooling__36_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split2_min_pooling__36_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split2_min_pooling__37_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 37 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split2_min_pooling__37_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split2_min_pooling__37_cov); + `endif +`endif +//VCS coverage on +//1*1*1 cube input for split >2 mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split3_average_pooling__39_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 39 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split3_average_pooling__39_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split3_average_pooling__39_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split3_average_pooling__40_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 40 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split3_average_pooling__40_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split3_average_pooling__40_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split3_max_pooling__42_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 42 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split3_max_pooling__42_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split3_max_pooling__42_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split3_max_pooling__43_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 43 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split3_max_pooling__43_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split3_max_pooling__43_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split3_min_pooling__45_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 45 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split3_min_pooling__45_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split3_min_pooling__45_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split3_min_pooling__46_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 46 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split3_min_pooling__46_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split3_min_pooling__46_cov); + `endif +`endif +//VCS coverage on +////////////////////// +////============== +////OBS signals +////============== +//assign obs_bus_pdp_cal1d_unit_en = unit1d_en[7:0]; +//assign obs_bus_pdp_cal1d_bubble = cur_datin_disable; +endmodule // NV_NVDLA_PDP_CORE_cal1d +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_cal1d_info_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus pdp_info_in -rd_pipebus pdp_info_out -rd_reg -rand_none -ram_bypass -d 8 -w 12 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_cal1d_info_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , pdp_info_in_prdy + , pdp_info_in_pvld + , pdp_info_in_pd + , pdp_info_out_prdy + , pdp_info_out_pvld + , pdp_info_out_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output pdp_info_in_prdy; +input pdp_info_in_pvld; +input [11:0] pdp_info_in_pd; +input pdp_info_out_prdy; +output pdp_info_out_pvld; +output [11:0] pdp_info_out_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg pdp_info_in_busy_int; // copy for internal use +assign pdp_info_in_prdy = !pdp_info_in_busy_int; +assign wr_reserving = pdp_info_in_pvld && !pdp_info_in_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [3:0] pdp_info_in_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? pdp_info_in_count : (pdp_info_in_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (pdp_info_in_count + 1'd1) : pdp_info_in_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire pdp_info_in_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check pdp_info_in_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_in_busy_int <= 1'b0; + pdp_info_in_count <= 4'd0; + end else begin + pdp_info_in_busy_int <= pdp_info_in_busy_next; + if ( wr_reserving ^ wr_popping ) begin + pdp_info_in_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + pdp_info_in_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as pdp_info_in_pvld +// +// RAM +// +reg [2:0] pdp_info_in_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_in_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + pdp_info_in_adr <= pdp_info_in_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [2:0] pdp_info_out_adr; // read address this cycle +wire ram_we = wr_pushing && (pdp_info_in_count > 4'd0 || !rd_popping); // note: write occurs next cycle +wire [11:0] pdp_info_out_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( pdp_info_in_pd ) + , .we ( ram_we ) + , .wa ( pdp_info_in_adr ) + , .ra ( (pdp_info_in_count == 0) ? 4'd8 : {1'b0,pdp_info_out_adr} ) + , .dout ( pdp_info_out_pd_p ) + ); +wire [2:0] rd_adr_next_popping = pdp_info_out_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_out_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + pdp_info_out_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + pdp_info_out_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire pdp_info_out_pvld_p; // data out of fifo is valid +reg pdp_info_out_pvld_int; // internal copy of pdp_info_out_pvld +assign pdp_info_out_pvld = pdp_info_out_pvld_int; +assign rd_popping = pdp_info_out_pvld_p && !(pdp_info_out_pvld_int && !pdp_info_out_prdy); +reg [3:0] pdp_info_out_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? pdp_info_out_count_p : + (pdp_info_out_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (pdp_info_out_count_p + 1'd1) : + pdp_info_out_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign pdp_info_out_pvld_p = pdp_info_out_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_out_count_p <= 4'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + pdp_info_out_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + pdp_info_out_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [11:0] pdp_info_out_pd; // output data register +wire rd_req_next = (pdp_info_out_pvld_p || (pdp_info_out_pvld_int && !pdp_info_out_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_out_pvld_int <= 1'b0; + end else begin + pdp_info_out_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + pdp_info_out_pd <= pdp_info_out_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + pdp_info_out_pd <= {12{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (pdp_info_in_pvld && !pdp_info_in_busy_int) || (pdp_info_in_busy_int != pdp_info_in_busy_next)) || (rd_pushing || rd_popping || (pdp_info_out_pvld_int && pdp_info_out_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_cal1d_info_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_cal1d_info_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_cal1d_info_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_cal1d_info_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, pdp_info_in_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_cal1d_info_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_cal1d_info_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [11:0] di; +input we; +input [2:0] wa; +input [3:0] ra; +output [11:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [11:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [2:0] Wa0_vmw; +reg we0_vmw; +reg [11:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[2:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 8) ? di : dout_p; +`else +reg [11:0] ram_ff0; +reg [11:0] ram_ff1; +reg [11:0] ram_ff2; +reg [11:0] ram_ff3; +reg [11:0] ram_ff4; +reg [11:0] ram_ff5; +reg [11:0] ram_ff6; +reg [11:0] ram_ff7; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 3'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 3'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 3'd7 ) begin + ram_ff7 <= di; + end +end +reg [11:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = di; +//VCS coverage off + default: dout = {12{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [2:0] Wa0; +input we0; +input [11:0] Di0; +input [2:0] Ra0; +output [11:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 12'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [11:0] mem[7:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [11:0] Q0 = mem[0]; +wire [11:0] Q1 = mem[1]; +wire [11:0] Q2 = mem[2]; +wire [11:0] Q3 = mem[3]; +wire [11:0] Q4 = mem[4]; +wire [11:0] Q5 = mem[5]; +wire [11:0] Q6 = mem[6]; +wire [11:0] Q7 = mem[7]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12] } +endmodule // vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +//vmw: Memory vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +//vmw: Address-size 3 +//vmw: Data-size 12 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[11:0] data0[11:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[11:0] data1[11:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v.vcp new file mode 100644 index 0000000..f40e4b1 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v.vcp @@ -0,0 +1,2487 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_cal1d.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_cal1d ( + nvdla_core_clk + ,nvdla_core_rstn + ,datin_src_cfg + ,dp2reg_done + ,padding_h_cfg + ,pdp_rdma2dp_pd + ,pdp_rdma2dp_valid + ,pooling1d_prdy + ,pooling_channel_cfg + ,pooling_fwidth_cfg + ,pooling_lwidth_cfg + ,pooling_mwidth_cfg + ,pooling_out_fwidth_cfg + ,pooling_out_lwidth_cfg + ,pooling_out_mwidth_cfg + ,pooling_size_h_cfg + ,pooling_splitw_num_cfg + ,pooling_stride_h_cfg + ,pooling_type_cfg + ,pwrbus_ram_pd + ,reg2dp_cube_in_height + ,reg2dp_cube_in_width + ,reg2dp_cube_out_width +//,reg2dp_input_data +//,reg2dp_int16_en +//,reg2dp_int8_en + ,reg2dp_kernel_stride_width + ,reg2dp_kernel_width + ,reg2dp_op_en + ,reg2dp_pad_left + ,reg2dp_pad_right + ,reg2dp_pad_right_cfg + ,reg2dp_pad_value_1x_cfg + ,reg2dp_pad_value_2x_cfg + ,reg2dp_pad_value_3x_cfg + ,reg2dp_pad_value_4x_cfg + ,reg2dp_pad_value_5x_cfg + ,reg2dp_pad_value_6x_cfg + ,reg2dp_pad_value_7x_cfg + ,sdp2pdp_pd + ,sdp2pdp_valid + ,pdp_op_start + ,pdp_rdma2dp_ready + ,pooling1d_pd + ,pooling1d_pvld + ,sdp2pdp_ready + ); +////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input datin_src_cfg; +input dp2reg_done; +input [2:0] padding_h_cfg; +input [1*8 +11:0] pdp_rdma2dp_pd; +input pdp_rdma2dp_valid; +input pooling1d_prdy; +input [12:0] pooling_channel_cfg; +input [9:0] pooling_fwidth_cfg; +input [9:0] pooling_lwidth_cfg; +input [9:0] pooling_mwidth_cfg; +input [9:0] pooling_out_fwidth_cfg; +input [9:0] pooling_out_lwidth_cfg; +input [9:0] pooling_out_mwidth_cfg; +input [2:0] pooling_size_h_cfg; +input [7:0] pooling_splitw_num_cfg; +input [3:0] pooling_stride_h_cfg; +input [1:0] pooling_type_cfg; +input [31:0] pwrbus_ram_pd; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_in_width; +input [12:0] reg2dp_cube_out_width; +//input [1:0] reg2dp_input_data; +//input reg2dp_int16_en; +//input reg2dp_int8_en; +input [3:0] reg2dp_kernel_stride_width; +input [2:0] reg2dp_kernel_width; +input reg2dp_op_en; +input [2:0] reg2dp_pad_left; +input [2:0] reg2dp_pad_right; +input [2:0] reg2dp_pad_right_cfg; +input [18:0] reg2dp_pad_value_1x_cfg; +input [18:0] reg2dp_pad_value_2x_cfg; +input [18:0] reg2dp_pad_value_3x_cfg; +input [18:0] reg2dp_pad_value_4x_cfg; +input [18:0] reg2dp_pad_value_5x_cfg; +input [18:0] reg2dp_pad_value_6x_cfg; +input [18:0] reg2dp_pad_value_7x_cfg; +input [1*8 +11:0] sdp2pdp_pd; +input sdp2pdp_valid; +output pdp_op_start; +output pdp_rdma2dp_ready; +//: my $m = 1*(8 +6); +//: print " output [$m-1:0] pooling1d_pd; \n"; +output pooling1d_pvld; +output sdp2pdp_ready; +////////////////////////////////////////////////////////////////////////// +//wire +wire average_pooling_en; +wire big_stride; +wire bsync; +wire bubble_en_end; +wire [2:0] bubble_num_dec; +wire [12:0] cube_out_channel; +wire [3:0] cube_width_in; +wire cur_datin_disable_sync; +wire [1*(8 +3)-1:0] datain_ext; +wire [1*(8 +3)+8:0] datin_buf; +wire [2:0] first_out_num_dec2; +wire first_splitw; +wire first_splitw_en; +wire init_cnt; +wire [7:0] init_unit1d_set; +wire [10:0] k_add_ks; +wire [4:0] kernel_padl; +wire [4:0] ks_width; +wire last_c; +wire last_c_sync; +wire last_line_in; +wire last_out_done; +wire last_out_en_sync; +wire last_pooling_flag; +wire last_splitw; +wire last_splitw_en; +wire line_last_stripe_done; +wire line_ldata_valid; +wire [2:0] line_regs_1; +wire [2:0] line_regs_2; +wire [2:0] line_regs_3; +wire [2:0] line_regs_4; +wire load_din; +wire loading_en; +wire [2:0] mon_first_out_num_dec2; +wire mon_overlap; +wire [1:0] mon_overlap_ff; +wire [0:0] mon_pad_table_index; +wire mon_rest_width; +wire [5:0] mon_strip_xcnt_offset; +//wire [0:0] mon_unit1d_actv_data_16bit_0; +//wire [0:0] mon_unit1d_actv_data_16bit_0_ff; +//wire [0:0] mon_unit1d_actv_data_16bit_1; +//wire [0:0] mon_unit1d_actv_data_16bit_1_ff; +//wire [0:0] mon_unit1d_actv_data_16bit_2; +//wire [0:0] mon_unit1d_actv_data_16bit_2_ff; +//wire [0:0] mon_unit1d_actv_data_16bit_3; +//wire [0:0] mon_unit1d_actv_data_16bit_3_ff; +wire non_split_small_active; +wire [3:0] non_split_w_pl; +wire [4:0] non_split_w_pl_pr; +wire non_splitw; +wire off_flying_en; +wire on_flying_en; +wire [3:0] overlap; +wire [2:0] overlap_ff; +wire [2:0] pad_l; +wire [2:0] pad_r; +wire [2:0] pad_table_index; +wire padding_here; +//wire padding_here_int16; +wire padding_here_int8; +wire [2:0] padding_stride1_num; +wire [2:0] padding_stride2_num; +wire [2:0] padding_stride3_num; +wire [2:0] padding_stride4_num; +wire [10:0] partial_w_last; +wire pdp_cube_end; +wire pdp_cube_sync; +wire [1*(8 +3) + 12:0] pdp_datin_pd; +wire [1*(8 +3) + 12:0] pdp_datin_pd_f0; +wire [1*8 +11:0] pdp_datin_pd_f_0; +wire [1*8 +11:0] pdp_datin_pd_f_mux0; +wire pdp_datin_prdy; +wire pdp_datin_prdy_0; +wire pdp_datin_prdy_1; +wire pdp_datin_prdy_f; +wire pdp_datin_prdy_mux0; +wire pdp_datin_pvld; +wire pdp_datin_pvld_f; +wire pdp_datin_pvld_mux0; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print "wire [$b+2:0] pdp_din_$m; \n"; +//: } +wire pdp_din_lc; +wire pdp_din_lc_sync; +wire pdp_full_pvld; +wire [11:0] pdp_info_in_pd; +wire pdp_info_in_prdy; +wire pdp_info_in_pvld; +wire [11:0] pdp_info_out_pd; +wire pdp_info_out_prdy; +wire pdp_info_out_pvld; +wire pooling1d_data_pad_rdy; +wire pooling1d_out_v; +wire pooling1d_out_v_disable; +wire pooling1d_out_v_lastout; +wire pooling1d_out_v_norm; +wire pooling_1d_rdy; +wire [7:0] pooling_din_last; +wire [7:0] pooling_din_last_sync; +wire [3:0] pooling_size; +wire [3:0] pooling_size_h; +wire [4:0] pooling_stride_h; +wire posc_last; +wire [12:0] pout_width_cur; +wire [12:0] rest_width; +wire [13:0] rest_width_use; +wire split_small_active; +wire [5:0] split_w_olap; +wire [6:0] split_w_olap_pr; +wire splitw_enable; +wire splitw_end; +wire splitw_end_sync; +wire splitw_start; +wire [4:0] stride; +wire [4:0] stride_1x; +wire [5:0] stride_2x; +wire [6:0] stride_3x; +wire [6:0] stride_4x; +wire [7:0] stride_5x; +wire [7:0] stride_6x; +wire [7:0] stride_7x; +wire stride_end; +wire strip_recieve_done; +wire strip_width_end; +wire [2:0] strip_xcnt_offset; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "wire [12-${k}:0] surface_num; \n"; +//: print "reg [12-${k}:0] surface_cnt_rd; \n"; +wire sync_switch_in_vld_d0; +wire sync_switch_in_vld_d1; +wire [11:0] sync_switch_out_pd; +wire sync_switch_out_rdy; +wire sync_switch_out_vld; +//wire [21:0] unit1d_actv_data_16bit_0; +//wire [21:0] unit1d_actv_data_16bit_0_ff; +//wire [21:0] unit1d_actv_data_16bit_1; +//wire [21:0] unit1d_actv_data_16bit_1_ff; +//wire [21:0] unit1d_actv_data_16bit_2; +//wire [21:0] unit1d_actv_data_16bit_2_ff; +//wire [21:0] unit1d_actv_data_16bit_3; +//wire [21:0] unit1d_actv_data_16bit_3_ff; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print "wire [$b+2:0] unit1d_actv_data_8bit_${m}; \n"; +//: print "wire [$b+2:0] unit1d_actv_data_8bit_${m}_ff; \n"; +//: print "wire [1:0] mon_unit1d_actv_data_8bit_${m}; \n"; +//: print "wire [1:0] mon_unit1d_actv_data_8bit_${m}_ff; \n"; +//: } +wire [1*(8 +3)+3:0] unit1d_actv_out; +wire unit1d_actv_out_prdy; +wire unit1d_actv_out_pvld; +wire [7:0] unit1d_clr; +wire [1*(8 +3)+3:0] unit1d_out_0; +wire [1*(8 +3)+3:0] unit1d_out_1; +wire [1*(8 +3)+3:0] unit1d_out_2; +wire [1*(8 +3)+3:0] unit1d_out_3; +wire [1*(8 +3)+3:0] unit1d_out_4; +wire [1*(8 +3)+3:0] unit1d_out_5; +wire [1*(8 +3)+3:0] unit1d_out_6; +wire [1*(8 +3)+3:0] unit1d_out_7; +wire [7:0] unit1d_out_prdy; +wire unit1d_out_prdy_use; +wire [7:0] unit1d_out_pvld; +wire unit1d_out_pvld_use; +wire [7:0] unit1d_prdy; +wire [7:0] unit1d_pvld; +wire [7:0] unit1d_set; +wire [7:0] unit1d_set_trig; +wire wr_line_dat_done; +wire wr_subcube_dat_done; +wire wr_surface_dat_done; +wire wr_total_cube_done; +//reg +reg [2:0] bubble_cnt; +reg [2:0] bubble_num; +reg [4:0] channel_cnt; +reg cur_datin_disable; +reg [4:0] first_out_num; +reg [2:0] flush_num; +reg [2:0] flush_num_cal; +reg [2:0] last_out_cnt; +reg last_out_en; +reg [6:0] mon_first_out_num; +reg need_bubble; +reg [7:0] pad_r_remain; +reg [18:0] pad_table_out; +reg [2:0] padding_left; +reg [2:0] padding_stride_num; +//reg [1*(8 +3) + 12:0] pdp_datin_pd0; +//reg pdp_datin_prdy_f0; +//reg pdp_datin_pvld0; +reg pdp_op_pending; +reg pdpw_active_en; +reg [1*(8 +6)-1:0] pooling1d_data_pad; +reg pooling1d_data_pad_vld; +reg pooling_din_1st_0; +reg pooling_din_1st_1; +reg pooling_din_1st_2; +reg pooling_din_1st_3; +reg pooling_din_1st_4; +reg pooling_din_1st_5; +reg pooling_din_1st_6; +reg pooling_din_1st_7; +reg [2:0] pooling_out_cnt; +reg [12:0] pooling_pwidth; +reg [2:0] regs_num; +reg [2:0] samllW_flush_num; +reg [7:0] splitw_cnt; +reg [12:0] strip_cnt_total; +reg [2:0] strip_xcnt_psize; +reg [3:0] strip_xcnt_stride; +reg [3:0] strip_xcnt_stride_f; +reg subcube_end_flag; +reg [1*(8 +3)+3:0] unit1d_actv_out_f; +reg [2:0] unit1d_cnt_pooling; +reg [2:0] unit1d_cnt_stride; +reg [7:0] unit1d_en; +reg [12:0] wr_line_dat_cnt; +reg [7:0] wr_splitc_cnt; +reg [12:0] wr_surface_dat_cnt; +//////////////////////////////////////////////////////////////// +//============================================================== +//PDP start +// +//-------------------------------------------------------------- +assign pdp_op_start = ~pdp_op_pending & reg2dp_op_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_op_pending <= 1'b0; + end else begin + if(pdp_op_start) + pdp_op_pending <= 1'b1; + else if(dp2reg_done) + pdp_op_pending <= 1'b0; + end +end +//============================================================== +//input data source select +//-------------------------------------------------------------- +assign off_flying_en = (datin_src_cfg == 1'h1 ); +assign on_flying_en = (datin_src_cfg == 1'h0 ); +assign pdp_datin_pd_f_mux0 = off_flying_en? pdp_rdma2dp_pd : sdp2pdp_pd; +assign pdp_datin_pvld_mux0 = off_flying_en? pdp_rdma2dp_valid : sdp2pdp_valid; +assign pdp_rdma2dp_ready = pdp_datin_prdy_mux0 & off_flying_en; +assign sdp2pdp_ready = pdp_datin_prdy_mux0 & on_flying_en; +assign pdp_datin_prdy_mux0 = pdp_datin_prdy_f; +//--------------------------------------------------------------- +//--------------------------------------------------------------- +//data select after switch +assign pdp_datin_pd_f_0 = pdp_datin_pd_f_mux0; +assign pdp_datin_pvld_f = pdp_datin_pvld_mux0; +//=============================================================== +// 1 cycle pipeline for DW timing closure inside unit1d sub modudle +// DW has replaced by normal hls fp17 adder, this pipeline keep here +//--------------------------------------------------------------- +//: my $dbw = 1*8; +//: my $Enum = 8/1 -1; +//: print " assign posc_last = (pdp_datin_pd_f_0[${dbw}+6:${dbw}+4]==${Enum}); \n"; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print qq( +//: assign pdp_din_$m = {{3{pdp_datin_pd_f_0[${b}*${m}+${b}-1]}},pdp_datin_pd_f_0[${b}*${m}+${b}-1:${b}*${m}]}; +//: ); +//: } +assign datain_ext = { +//: my $k = 1; +//: if($k>1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print "pdp_din_${i}, "; +//: } +//: } +pdp_din_0}; +assign pdp_datin_pd_f0 = {posc_last,pdp_datin_pd_f_0[1*8 +11:1*8],datain_ext}; +//: my $k = 1*(8 +3) + 13; +//: &eperl::pipe(" -wid $k -is -do pdp_datin_pd0 -vo pdp_datin_pvld0 -ri pdp_datin_prdy -di pdp_datin_pd_f0 -vi pdp_datin_pvld_f -ro pdp_datin_prdy_f0 "); +assign pdp_datin_prdy_f = pdp_datin_prdy_f0; +assign pdp_datin_pvld = pdp_datin_pvld0; +assign pdp_datin_pd = pdp_datin_pd0; +assign pdp_datin_prdy = (pdp_datin_prdy_0 & pdp_datin_prdy_1) & pdpw_active_en; +assign pdp_datin_prdy_0 = ~ cur_datin_disable; +//============================================================== +//new splitw +//--------------------------------------------------------------- +//assign bsync = pdp_datin_pd[95]; +//assign splitw_end_sync = load_din ? pdp_datin_pd[98] : 1'b0; +//assign pdp_cube_sync = pdp_datin_pd[99]; +assign bsync = pdp_datin_pd[1*(8 +3)+7]; +assign splitw_end_sync = load_din ? pdp_datin_pd[1*(8 +3)+10] : 1'b0; +assign pdp_cube_sync = pdp_datin_pd[1*(8 +3)+11]; +assign pdp_cube_end = pdp_cube_sync & bsync & load_din; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + splitw_cnt[7:0] <= {8{1'b0}}; + end else begin + if(splitw_end & bsync & splitw_end_sync & load_din) + splitw_cnt[7:0] <= 8'd0; + else if(splitw_end_sync & bsync & load_din) + splitw_cnt[7:0] <= splitw_cnt + 1; + end +end +assign splitw_end = (splitw_cnt==pooling_splitw_num_cfg[7:0]); +assign splitw_start = (splitw_cnt==8'd0); +//=============================================================== +//config info +// +//--------------------------------------------------------------- +assign non_splitw = pooling_splitw_num_cfg[7:0]==8'd0 ; +assign first_splitw_en = ~non_splitw & splitw_start; +assign last_splitw_en = ~non_splitw & splitw_end; +assign {mon_overlap,overlap[3:0]} = ({1'b0,reg2dp_kernel_width} < reg2dp_kernel_stride_width) ? (reg2dp_kernel_stride_width[3:0] - {1'b0,reg2dp_kernel_width[2:0]}) : ({1'b0,reg2dp_kernel_width[2:0]} - reg2dp_kernel_stride_width[3:0]); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-CORE: should not overflow") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_overlap); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + non_splitw + or reg2dp_cube_in_width + or splitw_end + or reg2dp_kernel_stride_width + or reg2dp_kernel_width + or pooling_lwidth_cfg + or overlap + or splitw_start + or pooling_fwidth_cfg + or pooling_mwidth_cfg + ) begin + if(non_splitw) + pooling_pwidth = reg2dp_cube_in_width[12:0]; + else if(splitw_end) begin + if(reg2dp_kernel_stride_width > {1'b0,reg2dp_kernel_width}) + pooling_pwidth = {3'd0,pooling_lwidth_cfg[9:0]} - {8'd0,overlap[3:0]}; + else + pooling_pwidth = {3'd0,pooling_lwidth_cfg[9:0]} + {8'd0,overlap[3:0]}; + end else if(splitw_start) + pooling_pwidth = {3'd0,pooling_fwidth_cfg[9:0]}; + else begin + if(reg2dp_kernel_stride_width > {1'b0,reg2dp_kernel_width}) + pooling_pwidth = {3'd0,pooling_mwidth_cfg[9:0]} - {8'd0,overlap[3:0]}; + else + pooling_pwidth = {3'd0,pooling_mwidth_cfg[9:0]} + {8'd0,overlap[3:0]}; + end +end +//============================================================== +//enable pdp datapath +//-------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdpw_active_en <= 1'b0; + end else begin + if(pdp_op_start) + pdpw_active_en <= 1'b1; + else if(pdp_cube_end) + pdpw_active_en <= 1'b0; + end +end +//============================================================== +//stride count in padding bits +// +//-------------------------------------------------------------- +//assign padding_left = ((~pdp_op_pending) | (first_splitw_en & (~splitw_end_sync))) ? padding_h_cfg[2:0] : 3'd0; +always @( + non_splitw + or padding_h_cfg + or first_splitw_en + or splitw_end_sync + ) begin + if(non_splitw) + padding_left = padding_h_cfg[2:0]; + else if(first_splitw_en & (~splitw_end_sync)) + padding_left = padding_h_cfg[2:0]; + else + padding_left = 3'd0; +end +//stride ==1 +assign padding_stride1_num = padding_left[2:0]; +//stride ==2 +assign padding_stride2_num = {1'b0,padding_left[2:1]}; +//stride ==3 +assign padding_stride3_num= (padding_left[2:0]>=3'd6) ? 3'd2 : + (padding_left[2:0]>=3'd3) ? 3'd1 : 3'd0; +//stride==4 5 6 7 +assign pooling_stride_h[4:0] = pooling_stride_h_cfg[3:0] + 3'd1; +assign padding_stride4_num = ({1'b0,padding_left[2:0]} > pooling_stride_h_cfg[3:0]) ? 3'd1 : 3'd0; +//number needed for padding in horizental direction +always @( + pooling_stride_h_cfg + or padding_stride1_num + or padding_stride2_num + or padding_stride3_num + or padding_stride4_num + ) begin + case(pooling_stride_h_cfg) + 4'd0: padding_stride_num = padding_stride1_num; + 4'd1: padding_stride_num = padding_stride2_num; + 4'd2: padding_stride_num = padding_stride3_num; + default: padding_stride_num = padding_stride4_num; + endcase +end +assign {mon_strip_xcnt_offset[5:0],strip_xcnt_offset[2:0]} = {5'b0, padding_left} - padding_stride_num * pooling_stride_h; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal1d: shouldn't be overflow") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (|mon_strip_xcnt_offset)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +////////////////////////////////////////////////// +// line reg use num calculation, "+1" +//------------------------------------------------ +//stride 1 +assign line_regs_1[2:0] = pooling_size_h_cfg[2:0]; +//stride 2 +assign line_regs_2[2:0] = {1'd0,pooling_size_h_cfg[2:1]}; +//stride 3 +assign line_regs_3[2:0] = (pooling_size_h_cfg[2:0]>3'd5)? 3'd2 : ((pooling_size_h_cfg[2:0]>3'd2)? 3'd1 : 3'd0); +//stride 4 5 6 7 +assign line_regs_4 = ({1'b0,pooling_size_h_cfg[2:0]}>pooling_stride_h_cfg)? 3'd1 : 3'd0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + regs_num[2:0] <= {3{1'b0}}; + end else begin + if(pdp_op_start) + case(pooling_stride_h_cfg) + 4'd0: regs_num[2:0] <= line_regs_1; + 4'd1: regs_num[2:0] <= line_regs_2; + 4'd2: regs_num[2:0] <= line_regs_3; + default: regs_num[2:0] <= line_regs_4; + endcase + end +end +////////////////////////////////////////////////// +//============================================================== +//1D pooling stride/size counter +// +//------------------------------------------------------------- +//stride start +assign load_din = pdp_datin_prdy & pdp_datin_pvld; +assign pooling_size_h[3:0] = pooling_size_h_cfg[2:0] + 3'd1; +assign strip_recieve_done = load_din & pdp_din_lc; +//assign pdp_din_lc = pdp_datin_pd[100]; +assign pdp_din_lc = pdp_datin_pd[1*(8 +3)+12]; +assign stride_end = strip_recieve_done & (strip_xcnt_stride==pooling_stride_h_cfg[3:0]); +assign init_cnt = line_last_stripe_done | pdp_op_start; +always @(*) begin + if(init_cnt) begin + strip_xcnt_stride_f[3:0] = {1'b0,strip_xcnt_offset}; + end else if(stride_end) + strip_xcnt_stride_f[3:0] = 4'd0; + else if(strip_recieve_done) + strip_xcnt_stride_f[3:0] = strip_xcnt_stride + 1; + else + strip_xcnt_stride_f[3:0] = strip_xcnt_stride; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_xcnt_stride[3:0] <= {4{1'b0}}; + end else begin + if ((init_cnt | stride_end | strip_recieve_done) == 1'b1) begin + strip_xcnt_stride[3:0] <= strip_xcnt_stride_f[3:0]; +// VCS coverage off + end else if ((init_cnt | stride_end | strip_recieve_done) == 1'b0) begin + end else begin + strip_xcnt_stride[3:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(init_cnt | stride_end | strip_recieve_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//pooling result ready +assign {mon_overlap_ff[1:0],overlap_ff[2:0]} = {1'b0,pooling_size_h_cfg} - pooling_stride_h_cfg; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_xcnt_psize <= {3{1'b0}}; + end else begin + if(init_cnt) + strip_xcnt_psize[2:0] <= padding_left[2:0]; + else if({1'b0,pooling_size_h_cfg} >= pooling_stride_h_cfg)begin // pooling_size >= stride + if(pooling_1d_rdy) + strip_xcnt_psize <= overlap_ff[2:0]; + else if(strip_recieve_done) + strip_xcnt_psize<= strip_xcnt_psize + 1; + end + else begin // pooling_size < stride + if(strip_xcnt_stride_f <= {1'b0,pooling_size_h_cfg[2:0]}) + strip_xcnt_psize <= strip_xcnt_stride_f[2:0]; + else + strip_xcnt_psize <= 3'd0; + end + end +end +///////////////////////////////////////////////////////// +//input data bubble control logic generation +//------------------------------------------------------- +assign pooling_size[3:0] = pooling_size_h; +assign stride[4:0] = pooling_stride_h; +assign pad_l[2:0] = padding_left; +assign pad_r = reg2dp_pad_right_cfg[2:0]; +//active_data_num_last_pooling = (pad_l + width) % stride; +//element/line num need flush at lint/surface end +always @( + pad_r + or stride_1x + or stride_2x + or stride_3x + or stride_4x + or stride_5x + or stride_6x + or stride_7x + ) begin + if({2'd0,pad_r} < stride_1x[4:0]) + flush_num_cal = 3'd0; + else if({3'd0,pad_r} < stride_2x[5:0]) + flush_num_cal = 3'd1; + else if({4'd0,pad_r} < stride_3x[6:0]) + flush_num_cal = 3'd2; + else if({4'd0,pad_r} < stride_4x[6:0]) + flush_num_cal = 3'd3; + else if({5'd0,pad_r} < stride_5x[7:0]) + flush_num_cal = 3'd4; + else if({5'd0,pad_r} < stride_6x[7:0]) + flush_num_cal = 3'd5; + else if({5'd0,pad_r} < stride_7x[7:0]) + flush_num_cal = 3'd6; + else// if({5'd0,pad_r} = stride_7x[7:0]) + flush_num_cal = 3'd7; +end +//small input detect +assign non_split_small_active = (non_splitw & (~(|reg2dp_cube_in_width[12:3])) & ((reg2dp_cube_in_width[2:0] + reg2dp_pad_left[2:0]) < {1'b0,reg2dp_kernel_width[2:0]})); +assign split_small_active = (~non_splitw) & ((big_stride & ((pooling_lwidth_cfg[9:0] - {6'd0,overlap[3:0]}) < {8'b0,reg2dp_kernel_width[2:0]})) + | ((~big_stride) & ((pooling_lwidth_cfg[9:0] + {6'd0,overlap[3:0]}) < {8'b0,reg2dp_kernel_width[2:0]}))); +//non-split mode cube_width + pad_left + pad_right +assign non_split_w_pl[3:0] = reg2dp_cube_in_width[2:0] + reg2dp_pad_left[2:0]; +assign non_split_w_pl_pr[4:0] = non_split_w_pl[3:0] + {1'b0,reg2dp_pad_right[2:0]}; +//split mode cube_width +/- overlap + pad_right +assign big_stride = (reg2dp_kernel_stride_width[3:0] >= {1'b0,reg2dp_kernel_width}); +assign split_w_olap[5:0] = big_stride ? (pooling_lwidth_cfg[4:0] - {1'd0,overlap[3:0]}) : (pooling_lwidth_cfg[4:0] + {1'd0,overlap[3:0]}); +assign split_w_olap_pr[6:0] = split_w_olap[5:0] + {3'd0,reg2dp_pad_right[2:0]}; +//pad_right remain afrer 1st kernel pooling +always @( + non_split_small_active + or non_split_w_pl_pr + or reg2dp_kernel_width + or split_small_active + or split_w_olap_pr + ) begin + if(non_split_small_active) + pad_r_remain[7:0] = {3'd0,non_split_w_pl_pr[4:0]} - {1'd0,reg2dp_kernel_width[2:0]} ; + else if(split_small_active) + pad_r_remain[7:0] = split_w_olap_pr[6:0] - {4'd0,reg2dp_kernel_width[2:0]} ; + else + pad_r_remain[7:0] = 8'd0 ; +end +//how many need bubble after 1st kernel pooling +always @( + pad_r_remain + or stride_6x + or stride_5x + or stride_4x + or stride_3x + or stride_2x + or stride_1x + ) begin + if(pad_r_remain == stride_6x[7:0]) + samllW_flush_num = 3'd6; + else if(pad_r_remain == stride_5x[7:0]) + samllW_flush_num = 3'd5; + else if(pad_r_remain == {1'd0,stride_4x[6:0]}) + samllW_flush_num = 3'd4; + else if(pad_r_remain == {1'd0,stride_3x[6:0]}) + samllW_flush_num = 3'd3; + else if(pad_r_remain == {2'd0,stride_2x[5:0]}) + samllW_flush_num = 3'd2; + else if(pad_r_remain == {3'd0,stride_1x[4:0]}) + samllW_flush_num = 3'd1; + else// if(pad_r_remain == 8'd0) + samllW_flush_num = 3'd0; +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP cal1d small width in: pad_r overflow") zzz_assert_never_8x (nvdla_core_clk, `ASSERT_RESET, (non_split_small_active|split_small_active) & (pad_r_remain == stride_7x)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//flush num calc +always @( + flush_num_cal + or non_split_small_active + or split_small_active + or samllW_flush_num + ) begin + if(flush_num_cal==3'd0) + flush_num[2:0] = 3'd0; + else if(non_split_small_active | split_small_active) + flush_num[2:0] = samllW_flush_num; + else + flush_num[2:0] = flush_num_cal[2:0]; +end +assign stride_1x[4:0] = stride[4:0]; +assign stride_2x[5:0] = {stride[4:0],1'b0}; +assign stride_3x[6:0] = ( stride_2x+{1'b0,stride[4:0]}); +assign stride_4x[6:0] = {stride[4:0],2'b0}; +assign stride_5x[7:0] = ( stride_4x+{2'd0,stride[4:0]}); +assign stride_6x[7:0] = ( stride_3x+stride_3x); +assign stride_7x[7:0] = ( stride_4x+stride_3x); +//the 1st element/line num need output data +//&Always; +// if(non_splitw | first_splitw_en) +// {mon_first_out_num[0],first_out_num[3:0]} = pooling_size - pad_l; +// else +// {mon_first_out_num[0],first_out_num[3:0]} = {1'b0,pooling_size}; +//&End; +assign kernel_padl[4:0] = pooling_size[3:0] - {1'b0,pad_l[2:0]}; +assign partial_w_last[10:0] = pooling_lwidth_cfg[9:0] + 10'd1; +assign cube_width_in[3:0] = reg2dp_cube_in_width[2:0] + 3'd1; +assign ks_width[4:0] = reg2dp_kernel_stride_width[3:0] + 4'd1; +assign k_add_ks[10:0]= {7'd0,pooling_size[3:0]} + {6'd0,ks_width[4:0]}; +always @( + non_splitw + or non_split_small_active + or cube_width_in + or kernel_padl + or first_splitw_en + or last_splitw_en + or split_small_active + or big_stride + or partial_w_last + or overlap + or k_add_ks + or pooling_size + ) begin + if(non_splitw) begin + if(non_split_small_active) + {mon_first_out_num[6:0],first_out_num[4:0]} = {8'd0,cube_width_in[3:0]}; + else + {mon_first_out_num[6:0],first_out_num[4:0]} = {7'd0,kernel_padl[4:0]}; + end else begin + if(first_splitw_en) + {mon_first_out_num[6:0],first_out_num[4:0]} = {7'd0,kernel_padl[4:0]}; + else if(last_splitw_en & split_small_active) begin + if(big_stride) + {mon_first_out_num[6:0],first_out_num[4:0]} = {1'b0,partial_w_last[10:0]}; + else + {mon_first_out_num[6:0],first_out_num[4:0]} = partial_w_last[10:0] + {7'd0,overlap[3:0]}; + end else begin + if(big_stride) + {mon_first_out_num[6:0],first_out_num[4:0]} = {1'b0,k_add_ks};//{7'd0,pooling_size[3:0]} + {6'd0,ks_width[4:0]}; + else + {mon_first_out_num[6:0],first_out_num[4:0]} = {8'd0,pooling_size[3:0]}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + need_bubble <= 1'b0; + bubble_num[2:0] <= {3{1'b0}}; + end else begin + if(pdp_cube_end) begin + if(|flush_num) begin + need_bubble <= 1'b1; + bubble_num[2:0] <= flush_num; + end else begin + need_bubble <= 1'b0; + bubble_num[2:0] <= 3'd0; + end + end else if(non_splitw) begin + if(pdp_op_start) begin + if({2'd0,flush_num} >= first_out_num) begin + need_bubble <= 1'b1; + bubble_num[2:0] <= flush_num - first_out_num[2:0] + 1'b1; + end else begin + need_bubble <= 1'b0; + bubble_num[2:0] <= 3'd0; + end + end + end else begin//split mode + if(splitw_end) begin + if({2'd0,flush_num} >= first_out_num) begin + need_bubble <= 1'b1; + bubble_num[2:0] <= flush_num - first_out_num[2:0] + 1'b1; + end else begin + need_bubble <= 1'b0; + bubble_num[2:0] <= 3'd0; + end + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable <= 1'b0; + end else begin + if(pdp_cube_end & (|flush_num)) + cur_datin_disable <= 1'b1; + else if(non_splitw) begin + if(line_last_stripe_done & need_bubble) + cur_datin_disable <= 1'b1; + else if(bubble_en_end) + cur_datin_disable <= 1'b0; + end else begin + if(last_splitw_en & line_last_stripe_done & need_bubble) + cur_datin_disable <= 1'b1; + else if(bubble_en_end) + cur_datin_disable <= 1'b0; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_cnt <= {5{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(last_c) + channel_cnt <= 5'd0; + else if(pdp_datin_prdy_1) + channel_cnt <= channel_cnt + 1'b1; + end else + channel_cnt <= 5'd0; + end +end +//: my $Enum = 8/1 -1; +//: print " assign last_c = (channel_cnt==5'd${Enum}) & pdp_datin_prdy_1; \n"; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_cnt <= {3{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(bubble_en_end) + bubble_cnt <= 3'd0; + else if(last_c) + bubble_cnt <= bubble_cnt + 1'b1; + end else + bubble_cnt <= 3'd0; + end +end +//assign bubble_en_end = (bubble_cnt == (bubble_num-1'b1)) & last_c; +assign bubble_num_dec[2:0] = bubble_num[2:0]-1'b1; +assign bubble_en_end = (bubble_cnt == bubble_num_dec) & last_c; +////////////////////////////////////////////////////// +//last line element output en during cur line element comming +//---------------------------------------------------- +//subcube end flag for last_out_en control in the sub-cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + subcube_end_flag <= 1'b0; + end else begin + if(splitw_end_sync & bsync) + subcube_end_flag <= 1'b1; + else if(load_din) + subcube_end_flag <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_en <= 1'b0; + end else begin + if(last_out_done) + last_out_en <= 1'b0; + else if(pdp_cube_end) + last_out_en <= 1'b0; + else if((first_out_num != 5'd1) & (~subcube_end_flag)) begin + if(need_bubble) begin + if(bubble_en_end) + last_out_en <= 1'b1; + end else if(|flush_num) begin + if(non_splitw & line_last_stripe_done) + last_out_en <= 1'b1; + else if(~non_splitw & last_splitw_en & line_last_stripe_done) + last_out_en <= 1'b1; + end + end else + last_out_en <= 1'b0; + end +end +//assign {mon_first_out_num_dec2[1:0],first_out_num_dec2[2:0]} = first_out_num - 4'd2; +assign {mon_first_out_num_dec2[2:0],first_out_num_dec2[2:0]} = need_bubble ? (first_out_num - 5'd2) : ({2'b0,flush_num} - 5'd1); +//assign {mon_first_out_num_dec2[1:0],first_out_num_dec2[2:0]} = first_out_num - 4'd1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_cnt <= {3{1'b0}}; + end else begin + if(last_out_en) begin + if(strip_recieve_done) begin + if(last_out_done) + last_out_cnt <= 3'd0; + else + last_out_cnt <= last_out_cnt + 1'b1; + end + end else + last_out_cnt <= 3'd0; + end +end +assign last_out_done = (last_out_cnt[2:0] == first_out_num_dec2[2:0]) & strip_recieve_done & last_out_en; +assign pooling_1d_rdy = (strip_xcnt_psize== pooling_size_h_cfg[2:0]) & strip_recieve_done; +///////////////////////////////////////////////////////// +//strip count in total width +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_cnt_total[12:0] <= {13{1'b0}}; + end else begin + if(init_cnt) + strip_cnt_total[12:0] <= 13'd0; + else if(strip_recieve_done) + strip_cnt_total[12:0] <= strip_cnt_total + 1; + end +end +assign strip_width_end = (strip_cnt_total == pooling_pwidth); +assign line_last_stripe_done = (strip_width_end & strip_recieve_done); +//----------------------- +//flag the last one pooling in width direction +//----------------------- +assign {mon_rest_width,rest_width[12:0]} = pooling_pwidth - strip_cnt_total; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal1d: shouldn't be overflow") zzz_assert_never_9x (nvdla_core_clk, `ASSERT_RESET, (pdp_op_pending & mon_rest_width)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign rest_width_use[13:0] = (non_splitw | splitw_end) ? (rest_width + {10'd0,reg2dp_pad_right_cfg}) : {1'b0,rest_width}; +assign last_pooling_flag = rest_width_use[13:0] <= {11'd0,pooling_size_h_cfg}; +//====================================================================== +//pooling 1D unit counter +// +//---------------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit1d_cnt_stride[2:0] <= {3{1'b0}}; + end else begin +//if(pdp_op_start) + if(init_cnt) begin + unit1d_cnt_stride[2:0] <= padding_stride_num; + end else if(stride_end) begin + if(unit1d_cnt_stride == regs_num) + unit1d_cnt_stride[2:0] <= 3'd0; + else + unit1d_cnt_stride[2:0] <= unit1d_cnt_stride +1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit1d_cnt_pooling[2:0] <= {3{1'b0}}; + end else begin +//if(pdp_op_start) + if(init_cnt) + unit1d_cnt_pooling[2:0] <= 0; + else if(pooling_1d_rdy | line_ldata_valid) begin + if(unit1d_cnt_pooling == regs_num) + unit1d_cnt_pooling[2:0] <= 0; + else + unit1d_cnt_pooling[2:0] <= unit1d_cnt_pooling + 1; + end + end +end +assign line_ldata_valid = line_last_stripe_done; +//: foreach my $i (0..7) { +//: my $j = $i -1; +//: print "assign init_unit1d_set[$i] = init_cnt & (padding_stride_num>=${i}) & (pout_width_cur >= 3'd${i}); \n"; +//: if($i==0){ +//: print "assign unit1d_set_trig[0] = stride_end & (unit1d_cnt_stride == regs_num) & (~last_pooling_flag);\n"; +//: } else { +//: print "assign unit1d_set_trig[${i}]= stride_end & (unit1d_cnt_stride == 3'd${j}) & (unit1d_cnt_stride != regs_num) & (~last_pooling_flag);\n"; +//: } +//: print qq( +//: assign unit1d_set[${i}] = unit1d_set_trig[${i}] | init_unit1d_set[${i}]; +//: assign unit1d_clr[${i}] = (pooling_1d_rdy & (unit1d_cnt_pooling == 3'd${i})) | line_ldata_valid; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: if (!nvdla_core_rstn) begin +//: unit1d_en[$i] <= 1'b0; +//: end else begin +//: if(pdp_cube_end) +//: unit1d_en[$i] <= 1'b0; +//: else if(unit1d_set[${i}]) +//: unit1d_en[$i] <= 1'b1; +//: else if(unit1d_clr[${i}]) +//: unit1d_en[$i] <= 1'b0; +//: end +//: ); +//: } +//: foreach my $i (0..7) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: if (!nvdla_core_rstn) begin +//: pooling_din_1st_$i <= 1'b0; +//: end else begin +//: if(unit1d_set[${i}]) +//: pooling_din_1st_$i <= 1'b1; +//: else if(strip_recieve_done) +//: pooling_din_1st_$i <= 1'b0; +//: end +//: ); +//: } +////////////////////////////////////////////////////////////////////////////////////// +//assign datin_buf = pdp_datin_pd[96:0]; +//assign datin_buf_1 = {pdp_datin_pd[96:88],pdp_datin_pd0[87:0]}; +assign datin_buf = pdp_datin_pd[1*(8 +3)+8:0]; +assign pdp_datin_prdy_1 = &unit1d_prdy & pdp_info_in_prdy; +assign pdp_full_pvld = pdp_datin_pvld | cur_datin_disable; +assign unit1d_pvld[0] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:1]}); +assign unit1d_pvld[1] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:2],unit1d_prdy[0]}); +assign unit1d_pvld[2] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:3],unit1d_prdy[1:0]}); +assign unit1d_pvld[3] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:4],unit1d_prdy[2:0]}); +assign unit1d_pvld[4] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:5],unit1d_prdy[3:0]}); +assign unit1d_pvld[5] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7:6],unit1d_prdy[4:0]}); +assign unit1d_pvld[6] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[7 ],unit1d_prdy[5:0]}); +assign unit1d_pvld[7] = pdp_full_pvld & pdp_info_in_prdy & (&{unit1d_prdy[6:0]}); +//============================================================ +//pdp info pipe +assign pdp_info_in_pvld = pdp_full_pvld & (&unit1d_prdy); +assign pdp_info_in_pd = {pdp_din_lc,last_c,last_out_en,cur_datin_disable,pooling_din_last[7:0]}; +NV_NVDLA_PDP_cal1d_info_fifo u_NV_NVDLA_PDP_cal1d_info_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pdp_info_in_prdy (pdp_info_in_prdy) //|> w + ,.pdp_info_in_pvld (pdp_info_in_pvld) //|< w + ,.pdp_info_in_pd (pdp_info_in_pd[11:0]) //|< w + ,.pdp_info_out_prdy (pdp_info_out_prdy) //|< w + ,.pdp_info_out_pvld (pdp_info_out_pvld) //|> w + ,.pdp_info_out_pd (pdp_info_out_pd[11:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign pdp_info_out_prdy = unit1d_out_prdy_use & (&unit1d_out_pvld); +assign {pdp_din_lc_sync,last_c_sync, last_out_en_sync,cur_datin_disable_sync,pooling_din_last_sync[7:0]} = pdp_info_out_pd[11:0]; +//============================================================ +// &Instance +// +//------------------------------------------------------------ +//assertion trace NVDLA_HLS_ADD17_LATENCY latency change from 4 +//: foreach my $i (0..7) { +//: print qq( +//: assign pooling_din_last[$i] = unit1d_en[$i] & (((strip_xcnt_psize== pooling_size_h_cfg[2:0]) & (unit1d_cnt_pooling==3'd$i)) | strip_width_end) ; +//: +//: NV_NVDLA_PDP_CORE_unit1d unit1d_$i ( +//: .nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.average_pooling_en (average_pooling_en) //|< w +//: ,.cur_datin_disable (cur_datin_disable) //|< r +//: ,.last_out_en ((last_out_en_sync | cur_datin_disable_sync)) //|< ? +//: ,.pdma2pdp_pd (datin_buf[1*(8 +3)+6:0]) //|< w +//: ,.pdma2pdp_pvld (unit1d_pvld[$i]) //|< w +//: ,.pdp_din_lc_f (pdp_din_lc) //|< w +//: ,.pooling_din_1st ((pooling_din_1st_$i )) //|< r +//: ,.pooling_din_last (pooling_din_last[$i]) //|< w +//: ,.pooling_out_prdy (unit1d_out_prdy[$i]) //|< w +//: ,.pooling_type_cfg (pooling_type_cfg[1:0]) //|< i +//: ,.pooling_unit_en (unit1d_en[$i]) //|< r +//: //,.reg2dp_int16_en (reg2dp_int16_en) //|< i +//: //,.reg2dp_int8_en (reg2dp_int8_en) //|< i +//: ,.pdma2pdp_prdy (unit1d_prdy[$i]) //|> w +//: ,.pooling_out (unit1d_out_$i) //|> w +//: ,.pooling_out_pvld (unit1d_out_pvld[$i]) //|> w +//: ); +//: ); +//: } +////////////////////////////////////////////////////////////////////////////////////// +assign unit1d_out_prdy[0] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:1]}); +assign unit1d_out_prdy[1] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:2],unit1d_out_pvld[0]}); +assign unit1d_out_prdy[2] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:3],unit1d_out_pvld[1:0]}); +assign unit1d_out_prdy[3] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:4],unit1d_out_pvld[2:0]}); +assign unit1d_out_prdy[4] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:5],unit1d_out_pvld[3:0]}); +assign unit1d_out_prdy[5] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7:6],unit1d_out_pvld[4:0]}); +assign unit1d_out_prdy[6] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[7 ],unit1d_out_pvld[5:0]}); +assign unit1d_out_prdy[7] = unit1d_out_prdy_use & pdp_info_out_pvld & (&{unit1d_out_pvld[6:0]}); +assign unit1d_out_pvld_use = &unit1d_out_pvld & pdp_info_out_pvld; +//========================================================= +//1d pooling output +// +//--------------------------------------------------------- +//unit1d count +assign pooling1d_out_v_norm = ((|pooling_din_last_sync) & pdp_din_lc_sync & (~cur_datin_disable_sync) & unit1d_out_pvld_use & unit1d_out_prdy_use); +assign pooling1d_out_v_disable = (cur_datin_disable_sync & last_c_sync) & unit1d_out_pvld_use & unit1d_out_prdy_use; +assign pooling1d_out_v_lastout = (last_out_en_sync & pdp_din_lc_sync & unit1d_out_pvld_use & unit1d_out_prdy_use); +assign pooling1d_out_v = pooling1d_out_v_norm | pooling1d_out_v_disable | pooling1d_out_v_lastout; +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// +//end of line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_dat_cnt[12:0] <= {13{1'b0}}; + end else begin + if(wr_line_dat_done) + wr_line_dat_cnt[12:0] <= 0; + else if(pooling1d_out_v) + wr_line_dat_cnt[12:0] <= wr_line_dat_cnt + 1; + end +end +assign wr_line_dat_done = (wr_line_dat_cnt==pout_width_cur) & pooling1d_out_v; +//end of surface +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_cnt <= {13{1'b0}}; + end else begin + if(wr_surface_dat_done) + wr_surface_dat_cnt <= 13'd0; + else if(wr_line_dat_done) + wr_surface_dat_cnt <= wr_surface_dat_cnt + 13'd1; + end +end +assign last_line_in = (wr_surface_dat_cnt==reg2dp_cube_in_height[12:0]); +assign wr_surface_dat_done = wr_line_dat_done & last_line_in; +//end of splitw +//assign cube_out_channel[13:0]= pooling_channel_cfg[12:0] + 1'b1; +assign cube_out_channel[12:0]= pooling_channel_cfg[12:0]; +////16bits: INT16 or FP16 +//assign {mon_surface_num_0,surface_num_0[9:0]} = cube_out_channel[13:4] + {9'd0,(|cube_out_channel[3:0])}; +////8bits: INT8 +//assign surface_num_1[9:0] = {1'b0,cube_out_channel[13:5]} + (|cube_out_channel[4:0]); +//assign surface_num = (reg2dp_input_data[1:0] == 2'h0 )? surface_num_1 : surface_num_0; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "assign surface_num = cube_out_channel[12:${k}]; \n"; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surface_cnt_rd <= 0; + end else begin + if(wr_subcube_dat_done) + surface_cnt_rd <= 0; + else if(wr_surface_dat_done) + surface_cnt_rd <= surface_cnt_rd + 1; + end +end +//assign wr_subcube_dat_done = ((surface_num-1)==surface_cnt_rd) & wr_surface_dat_done; +assign wr_subcube_dat_done = (surface_num==surface_cnt_rd) & wr_surface_dat_done; +//total cube done +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_splitc_cnt[7:0] <= {8{1'b0}}; + end else begin + if(wr_total_cube_done) + wr_splitc_cnt[7:0] <= 8'd0; + else if(wr_subcube_dat_done) + wr_splitc_cnt[7:0] <= wr_splitc_cnt + 1; + end +end +assign wr_total_cube_done = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & wr_subcube_dat_done; +//------------------------------------------------- +//split width selection +assign splitw_enable = (pooling_splitw_num_cfg!=8'd0); +assign last_splitw = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & splitw_enable; +assign first_splitw = (wr_splitc_cnt==8'd0) & splitw_enable; +assign pout_width_cur[12:0]= (~splitw_enable) ? reg2dp_cube_out_width[12:0] : + (last_splitw ? {3'd0,pooling_out_lwidth_cfg[9:0]} : + first_splitw ? {3'd0,pooling_out_fwidth_cfg[9:0]} : + {3'd0,pooling_out_mwidth_cfg[9:0]}); +////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_out_cnt[2:0] <= {3{1'b0}}; + end else begin + if(pdp_op_start) + pooling_out_cnt[2:0] <= 3'd0; + else if(pooling1d_out_v) begin + if((pooling_out_cnt == regs_num) | wr_line_dat_done) + pooling_out_cnt[2:0] <= 3'd0; + else + pooling_out_cnt[2:0] <= pooling_out_cnt + 3'd1 ; + end + end +end +always @(*) begin + case(pooling_out_cnt) + 3'd0 : unit1d_actv_out_f = unit1d_out_0; + 3'd1 : unit1d_actv_out_f = unit1d_out_1; + 3'd2 : unit1d_actv_out_f = unit1d_out_2; + 3'd3 : unit1d_actv_out_f = unit1d_out_3; + 3'd4 : unit1d_actv_out_f = unit1d_out_4; + 3'd5 : unit1d_actv_out_f = unit1d_out_5; + 3'd6 : unit1d_actv_out_f = unit1d_out_6; + 3'd7 : unit1d_actv_out_f = unit1d_out_7; +//VCS coverage off +//default : unit1d_actv_out_f = 92'd0; + default : unit1d_actv_out_f = 0; +//VCS coverage on + endcase +end +assign unit1d_out_prdy_use = unit1d_actv_out_prdy; +assign unit1d_actv_out_pvld = unit1d_out_pvld_use & ((|pooling_din_last_sync) | cur_datin_disable_sync | last_out_en_sync); +assign unit1d_actv_out = unit1d_actv_out_f; +//================================= +//padding value in h direction under average mode +// +//---------------------------------- +//padding value 1x,2x,3x,4x,5x,6x,7x table +always @(*) begin + case(pad_table_index) + 3'd1: pad_table_out = reg2dp_pad_value_1x_cfg[18:0]; //1x + 3'd2: pad_table_out = reg2dp_pad_value_2x_cfg[18:0]; //2x + 3'd3: pad_table_out = reg2dp_pad_value_3x_cfg[18:0]; //3x + 3'd4: pad_table_out = reg2dp_pad_value_4x_cfg[18:0]; //4x + 3'd5: pad_table_out = reg2dp_pad_value_5x_cfg[18:0]; //5x + 3'd6: pad_table_out = reg2dp_pad_value_6x_cfg[18:0]; //6x + 3'd7: pad_table_out = reg2dp_pad_value_7x_cfg[18:0]; //7x + default:pad_table_out = 19'd0; + endcase +end +assign loading_en = unit1d_actv_out_pvld & unit1d_actv_out_prdy; +//: my $s = "\$signed"; +//: my $k = 1; +//: my $b = 8; +//: foreach my $m (0..$k-1) { +//: print "assign {mon_unit1d_actv_data_8bit_${m}_ff[1:0],unit1d_actv_data_8bit_${m}_ff} = $s({{1{unit1d_actv_out[(${b}+3)*${m}+(${b}+3)-1]}},unit1d_actv_out[(${b}+3)*${m}+(${b}+3)-1:(${b}+3)*${m}] }) + $s({pad_table_out[10], pad_table_out[10:0]}); \n"; +//: print "assign {mon_unit1d_actv_data_8bit_${m}[1:0],unit1d_actv_data_8bit_${m}} = padding_here_int8 ? {mon_unit1d_actv_data_8bit_${m}_ff[1:0],unit1d_actv_data_8bit_${m}_ff} : {2'd0,unit1d_actv_out[(${b}+3)*${m}+(${b}+3)-1:(${b}+3)*${m}] }; \n"; +//: } +//: print "assign padding_here = (pooling_type_cfg== 2'h0 ) & (unit1d_actv_out[${k}*(${b}+3)+2:${k}*(${b}+3)] != pooling_size_h_cfg); \n"; +assign padding_here_int8 = padding_here; +assign {mon_pad_table_index[0],pad_table_index[2:0]} = pooling_size_h_cfg - unit1d_actv_out[1*(8 +3)+2:1*(8 +3)]; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal1d: pooling size should not less than active num") zzz_assert_never_11x (nvdla_core_clk, `ASSERT_RESET, (loading_en & mon_pad_table_index)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling1d_data_pad <= 0; + end else begin + if(loading_en) begin + pooling1d_data_pad <= { +//: my $k = 1; +//: my $b = 8; +//: if($k > 1) { +//: foreach my $m (0..$k-2) { +//: my $i = $k - $m -1; +//: print "{{3{unit1d_actv_data_8bit_${i}[${b}+2]}}, unit1d_actv_data_8bit_${i}[${b}+2:0]}, \n"; +//: } +//: } +//: print "{{3{unit1d_actv_data_8bit_0[${b}+2]}}, unit1d_actv_data_8bit_0[${b}+2:0]}}; \n"; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling1d_data_pad_vld <= 1'b0; + end else begin + if(unit1d_actv_out_pvld) + pooling1d_data_pad_vld <= 1'b1; + else if(pooling1d_data_pad_rdy) + pooling1d_data_pad_vld <= 1'b0; + end +end +assign unit1d_actv_out_prdy = (~pooling1d_data_pad_vld | pooling1d_data_pad_rdy); +//================================= +//pad_value logic for fp16 average pooling +//---------------------------------- +assign average_pooling_en = (pooling_type_cfg== 2'h0 ); +///////////////////////////////////////////////////////////////////////////////////// +//================================= +//pooling output +// +//---------------------------------- +assign pooling1d_pd = pooling1d_data_pad; +assign pooling1d_pvld = pooling1d_data_pad_vld; +assign pooling1d_data_pad_rdy= pooling1d_prdy; +//============== +//function points +//============== +// max/min/average pooling +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_max_pooling__1_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ); +// endproperty +// // Cover 1 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 )" +// FUNCPOINT_PDP_feature__int16_max_pooling__1_COV : cover property (PDP_feature__int16_max_pooling__1_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_max_pooling__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h1 ); + endproperty +// Cover 2 : "pdp_op_start & (pooling_type_cfg== 2'h1 )" + FUNCPOINT_PDP_feature__int8_max_pooling__2_COV : cover property (PDP_feature__int8_max_pooling__2_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_min_pooling__4_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ); +// endproperty +// // Cover 4 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 )" +// FUNCPOINT_PDP_feature__int16_min_pooling__4_COV : cover property (PDP_feature__int16_min_pooling__4_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_min_pooling__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h2 ); + endproperty +// Cover 5 : "pdp_op_start & (pooling_type_cfg== 2'h2 )" + FUNCPOINT_PDP_feature__int8_min_pooling__5_COV : cover property (PDP_feature__int8_min_pooling__5_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_average_pooling__7_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h0 ); +// endproperty +// // Cover 7 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h0 )" +// FUNCPOINT_PDP_feature__int16_average_pooling__7_COV : cover property (PDP_feature__int16_average_pooling__7_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_average_pooling__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h0 ); + endproperty +// Cover 8 : "pdp_op_start & (pooling_type_cfg== 2'h0 )" + FUNCPOINT_PDP_feature__int8_average_pooling__8_COV : cover property (PDP_feature__int8_average_pooling__8_cov); + `endif +`endif +//VCS coverage on +////pooling in inactive channel +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_average_pooling_in_inactive_channel__11_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & average_pooling_en & reg2dp_int16_en & (~(&pooling_channel_cfg[4:0])); +// endproperty +// // Cover 11 : "pdp_op_start & average_pooling_en & reg2dp_int16_en & (~(&pooling_channel_cfg[4:0]))" +// FUNCPOINT_PDP_feature__int16_average_pooling_in_inactive_channel__11_COV : cover property (PDP_feature__int16_average_pooling_in_inactive_channel__11_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_average_pooling_in_inactive_channel__12_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & average_pooling_en & (~(&pooling_channel_cfg[4:0])); + endproperty +// Cover 12 : "pdp_op_start & average_pooling_en & (~(&pooling_channel_cfg[4:0]))" + FUNCPOINT_PDP_feature__int8_average_pooling_in_inactive_channel__12_COV : cover property (PDP_feature__int8_average_pooling_in_inactive_channel__12_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_max_pooling_in_inactive_channel__14_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0])); +// endproperty +// // Cover 14 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0]))" +// FUNCPOINT_PDP_feature__int16_max_pooling_in_inactive_channel__14_COV : cover property (PDP_feature__int16_max_pooling_in_inactive_channel__14_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_max_pooling_in_inactive_channel__15_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0])); + endproperty +// Cover 15 : "pdp_op_start & (pooling_type_cfg== 2'h1 ) & (~(&pooling_channel_cfg[4:0]))" + FUNCPOINT_PDP_feature__int8_max_pooling_in_inactive_channel__15_COV : cover property (PDP_feature__int8_max_pooling_in_inactive_channel__15_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_feature__int16_min_pooling_in_inactive_channel__17_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0])); +// endproperty +// // Cover 17 : "pdp_op_start & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0]))" +// FUNCPOINT_PDP_feature__int16_min_pooling_in_inactive_channel__17_COV : cover property (PDP_feature__int16_min_pooling_in_inactive_channel__17_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_feature__int8_min_pooling_in_inactive_channel__18_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0])); + endproperty +// Cover 18 : "pdp_op_start & (pooling_type_cfg== 2'h2 ) & (~(&pooling_channel_cfg[4:0]))" + FUNCPOINT_PDP_feature__int8_min_pooling_in_inactive_channel__18_COV : cover property (PDP_feature__int8_min_pooling_in_inactive_channel__18_cov); + `endif +`endif +//VCS coverage on +/////////////// +//1*1*1 cube input +/////////////// +////1*1*1 cube input for nonsplit mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_average_pooling__21_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & non_splitw & average_pooling_en & reg2dp_int16_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 21 : "pdp_op_start & non_splitw & average_pooling_en & reg2dp_int16_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_average_pooling__21_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_average_pooling__21_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_average_pooling__22_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & non_splitw & average_pooling_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 22 : "pdp_op_start & non_splitw & average_pooling_en & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_average_pooling__22_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_average_pooling__22_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_max_pooling__24_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 24 : "pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_max_pooling__24_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_max_pooling__24_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_max_pooling__25_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & non_splitw & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 25 : "pdp_op_start & non_splitw & (pooling_type_cfg== 2'h1 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_max_pooling__25_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_max_pooling__25_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_min_pooling__27_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 27 : "pdp_op_start & non_splitw & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_min_pooling__27_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_nonsplit_min_pooling__27_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_min_pooling__28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & non_splitw & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 28 : "pdp_op_start & non_splitw & (pooling_type_cfg== 2'h2 ) & (~(|reg2dp_cube_in_width)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_min_pooling__28_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_nonsplit_min_pooling__28_cov); + `endif +`endif +//VCS coverage on +//1*1*1 cube input for split 2 mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split2_average_pooling__30_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 30 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split2_average_pooling__30_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split2_average_pooling__30_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split2_average_pooling__31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 31 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split2_average_pooling__31_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split2_average_pooling__31_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split2_max_pooling__33_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 33 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split2_max_pooling__33_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split2_max_pooling__33_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split2_max_pooling__34_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 34 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split2_max_pooling__34_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split2_max_pooling__34_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split2_min_pooling__36_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 36 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split2_min_pooling__36_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split2_min_pooling__36_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split2_min_pooling__37_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 37 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]==8'd1) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split2_min_pooling__37_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split2_min_pooling__37_cov); + `endif +`endif +//VCS coverage on +//1*1*1 cube input for split >2 mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split3_average_pooling__39_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 39 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & reg2dp_int16_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split3_average_pooling__39_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split3_average_pooling__39_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split3_average_pooling__40_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 40 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & average_pooling_en & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split3_average_pooling__40_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split3_average_pooling__40_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split3_max_pooling__42_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 42 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split3_max_pooling__42_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split3_max_pooling__42_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split3_max_pooling__43_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 43 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h1 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split3_max_pooling__43_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split3_max_pooling__43_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_in__1_1_1_cube_in_int16_split3_min_pooling__45_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); +// endproperty +// // Cover 45 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & reg2dp_int16_en & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" +// FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int16_split3_min_pooling__45_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int16_split3_min_pooling__45_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_in__1_1_1_cube_in_int8_split3_min_pooling__46_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg)); + endproperty +// Cover 46 : "pdp_op_start & (pooling_splitw_num_cfg[7:0]>=8'd2) & (pooling_type_cfg== 2'h2 ) & (~(|pooling_fwidth_cfg)) & (~(|pooling_lwidth_cfg)) & (~(|pooling_mwidth_cfg)) & (~(|reg2dp_cube_in_height)) & (~(|pooling_channel_cfg))" + FUNCPOINT_PDP_min_cube_in__1_1_1_cube_in_int8_split3_min_pooling__46_COV : cover property (PDP_min_cube_in__1_1_1_cube_in_int8_split3_min_pooling__46_cov); + `endif +`endif +//VCS coverage on +////////////////////// +////============== +////OBS signals +////============== +//assign obs_bus_pdp_cal1d_unit_en = unit1d_en[7:0]; +//assign obs_bus_pdp_cal1d_bubble = cur_datin_disable; +endmodule // NV_NVDLA_PDP_CORE_cal1d +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_cal1d_info_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus pdp_info_in -rd_pipebus pdp_info_out -rd_reg -rand_none -ram_bypass -d 8 -w 12 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_cal1d_info_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , pdp_info_in_prdy + , pdp_info_in_pvld + , pdp_info_in_pd + , pdp_info_out_prdy + , pdp_info_out_pvld + , pdp_info_out_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output pdp_info_in_prdy; +input pdp_info_in_pvld; +input [11:0] pdp_info_in_pd; +input pdp_info_out_prdy; +output pdp_info_out_pvld; +output [11:0] pdp_info_out_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg pdp_info_in_busy_int; // copy for internal use +assign pdp_info_in_prdy = !pdp_info_in_busy_int; +assign wr_reserving = pdp_info_in_pvld && !pdp_info_in_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [3:0] pdp_info_in_count; // write-side count +wire [3:0] wr_count_next_wr_popping = wr_reserving ? pdp_info_in_count : (pdp_info_in_count - 1'd1); // spyglass disable W164a W484 +wire [3:0] wr_count_next_no_wr_popping = wr_reserving ? (pdp_info_in_count + 1'd1) : pdp_info_in_count; // spyglass disable W164a W484 +wire [3:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_8 = ( wr_count_next_no_wr_popping == 4'd8 ); +wire wr_count_next_is_8 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_8; +wire [3:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [3:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire pdp_info_in_busy_next = wr_count_next_is_8 || // busy next cycle? + (wr_limit_reg != 4'd0 && // check pdp_info_in_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_in_busy_int <= 1'b0; + pdp_info_in_count <= 4'd0; + end else begin + pdp_info_in_busy_int <= pdp_info_in_busy_next; + if ( wr_reserving ^ wr_popping ) begin + pdp_info_in_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + pdp_info_in_count <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as pdp_info_in_pvld +// +// RAM +// +reg [2:0] pdp_info_in_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_in_adr <= 3'd0; + end else begin + if ( wr_pushing ) begin + pdp_info_in_adr <= pdp_info_in_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [2:0] pdp_info_out_adr; // read address this cycle +wire ram_we = wr_pushing && (pdp_info_in_count > 4'd0 || !rd_popping); // note: write occurs next cycle +wire [11:0] pdp_info_out_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( pdp_info_in_pd ) + , .we ( ram_we ) + , .wa ( pdp_info_in_adr ) + , .ra ( (pdp_info_in_count == 0) ? 4'd8 : {1'b0,pdp_info_out_adr} ) + , .dout ( pdp_info_out_pd_p ) + ); +wire [2:0] rd_adr_next_popping = pdp_info_out_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_out_adr <= 3'd0; + end else begin + if ( rd_popping ) begin + pdp_info_out_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + pdp_info_out_adr <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire pdp_info_out_pvld_p; // data out of fifo is valid +reg pdp_info_out_pvld_int; // internal copy of pdp_info_out_pvld +assign pdp_info_out_pvld = pdp_info_out_pvld_int; +assign rd_popping = pdp_info_out_pvld_p && !(pdp_info_out_pvld_int && !pdp_info_out_prdy); +reg [3:0] pdp_info_out_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [3:0] rd_count_p_next_rd_popping = rd_pushing ? pdp_info_out_count_p : + (pdp_info_out_count_p - 1'd1); +wire [3:0] rd_count_p_next_no_rd_popping = rd_pushing ? (pdp_info_out_count_p + 1'd1) : + pdp_info_out_count_p; +// spyglass enable_block W164a W484 +wire [3:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign pdp_info_out_pvld_p = pdp_info_out_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_out_count_p <= 4'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + pdp_info_out_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + pdp_info_out_count_p <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [11:0] pdp_info_out_pd; // output data register +wire rd_req_next = (pdp_info_out_pvld_p || (pdp_info_out_pvld_int && !pdp_info_out_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + pdp_info_out_pvld_int <= 1'b0; + end else begin + pdp_info_out_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + pdp_info_out_pd <= pdp_info_out_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + pdp_info_out_pd <= {12{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (pdp_info_in_pvld && !pdp_info_in_busy_int) || (pdp_info_in_busy_int != pdp_info_in_busy_next)) || (rd_pushing || rd_popping || (pdp_info_out_pvld_int && pdp_info_out_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_cal1d_info_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_cal1d_info_fifo_wr_limit : 4'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 4'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 4'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 4'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [3:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 4'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_cal1d_info_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_cal1d_info_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {28'd0, (wr_limit_reg == 4'd0) ? 4'd8 : wr_limit_reg} ) + , .curr ( {28'd0, pdp_info_in_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_cal1d_info_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_cal1d_info_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [11:0] di; +input we; +input [2:0] wa; +input [3:0] ra; +output [11:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [11:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [2:0] Wa0_vmw; +reg we0_vmw; +reg [11:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[2:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 8) ? di : dout_p; +`else +reg [11:0] ram_ff0; +reg [11:0] ram_ff1; +reg [11:0] ram_ff2; +reg [11:0] ram_ff3; +reg [11:0] ram_ff4; +reg [11:0] ram_ff5; +reg [11:0] ram_ff6; +reg [11:0] ram_ff7; +always @( posedge clk ) begin + if ( we && wa == 3'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 3'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 3'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 3'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 3'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 3'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 3'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 3'd7 ) begin + ram_ff7 <= di; + end +end +reg [11:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = di; +//VCS coverage off + default: dout = {12{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [2:0] Wa0; +input we0; +input [11:0] Di0; +input [2:0] Ra0; +output [11:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 12'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [11:0] mem[7:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [11:0] Q0 = mem[0]; +wire [11:0] Q1 = mem[1]; +wire [11:0] Q2 = mem[2]; +wire [11:0] Q3 = mem[3]; +wire [11:0] Q4 = mem[4]; +wire [11:0] Q5 = mem[5]; +wire [11:0] Q6 = mem[6]; +wire [11:0] Q7 = mem[7]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12] } +endmodule // vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +//vmw: Memory vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +//vmw: Address-size 3 +//vmw: Data-size 12 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[11:0] data0[11:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[11:0] data1[11:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v new file mode 100644 index 0000000..5d038d3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v @@ -0,0 +1,5343 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_cal2d.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_cal2d ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,padding_v_cfg //|< i + ,pdp_dp2wdma_ready //|< i + ,pdp_op_start //|< i + ,pooling1d_pd //|< i + ,pooling1d_pvld //|< i + ,pooling_channel_cfg //|< i + ,pooling_out_fwidth_cfg //|< i + ,pooling_out_lwidth_cfg //|< i + ,pooling_out_mwidth_cfg //|< i + ,pooling_size_v_cfg //|< i + ,pooling_splitw_num_cfg //|< i + ,pooling_stride_v_cfg //|< i + ,pooling_type_cfg //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_out_width //|< i +//,reg2dp_input_data //|< i +//,reg2dp_int16_en //|< i +//,reg2dp_int8_en //|< i + ,reg2dp_kernel_height //|< i + ,reg2dp_kernel_width //|< i + ,reg2dp_pad_bottom_cfg //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value_1x_cfg //|< i + ,reg2dp_pad_value_2x_cfg //|< i + ,reg2dp_pad_value_3x_cfg //|< i + ,reg2dp_pad_value_4x_cfg //|< i + ,reg2dp_pad_value_5x_cfg //|< i + ,reg2dp_pad_value_6x_cfg //|< i + ,reg2dp_pad_value_7x_cfg //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_recip_height_cfg //|< i + ,reg2dp_recip_width_cfg //|< i + ,pdp_dp2wdma_pd //|> o + ,pdp_dp2wdma_valid //|> o + ,pooling1d_prdy //|> o + ); +///////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [2:0] padding_v_cfg; +input pdp_dp2wdma_ready; +input pdp_op_start; +//: my $m = 1*(8 +6); +//: print " input [$m-1:0] pooling1d_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + input [14-1:0] pooling1d_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input pooling1d_pvld; +input [12:0] pooling_channel_cfg; +input [9:0] pooling_out_fwidth_cfg; +input [9:0] pooling_out_lwidth_cfg; +input [9:0] pooling_out_mwidth_cfg; +input [2:0] pooling_size_v_cfg; +input [7:0] pooling_splitw_num_cfg; +input [3:0] pooling_stride_v_cfg; +input [1:0] pooling_type_cfg; +input [31:0] pwrbus_ram_pd; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_out_width; +//input [1:0] reg2dp_input_data; +//input reg2dp_int16_en; +//input reg2dp_int8_en; +input [2:0] reg2dp_kernel_height; +input [2:0] reg2dp_kernel_width; +input [2:0] reg2dp_pad_bottom_cfg; +input [2:0] reg2dp_pad_top; +input [18:0] reg2dp_pad_value_1x_cfg; +input [18:0] reg2dp_pad_value_2x_cfg; +input [18:0] reg2dp_pad_value_3x_cfg; +input [18:0] reg2dp_pad_value_4x_cfg; +input [18:0] reg2dp_pad_value_5x_cfg; +input [18:0] reg2dp_pad_value_6x_cfg; +input [18:0] reg2dp_pad_value_7x_cfg; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [16:0] reg2dp_recip_height_cfg; +input [16:0] reg2dp_recip_width_cfg; +//: my $m = 1*8; +//: print "output [${m}-1:0] pdp_dp2wdma_pd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8-1:0] pdp_dp2wdma_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output pdp_dp2wdma_valid; +output pooling1d_prdy; +///////////////////////////////////////////////////////////////////////// +wire [8:0] BANK_DEPTH; +wire active_last_line; +wire average_pooling_en; +wire bubble_en_end; +wire [2:0] bubble_num_dec; +wire [3:0] buffer_lines_0; +wire [3:0] buffer_lines_1; +wire [3:0] buffer_lines_2; +wire [3:0] buffer_lines_3; +wire [3:0] cube_in_height_cfg; +wire cur_datin_disable_2d_sync; +wire data_c_end; +wire [3:0] first_out_num; +wire [2:0] first_out_num_dec2; +wire first_splitw; +wire [2:0] flush_in_next_surf; +wire [2:0] flush_num_dec1; +wire flush_read_en; +wire [3:0] h_pt; +wire [4:0] h_pt_pb; +wire init_cnt; +wire [7:0] init_unit2d_set; +wire [1*8 -1:0] int_dp2wdma_pd; +wire int_dp2wdma_valid; +wire [1*(8 +6)+2:0] int_pout_mem_data; +wire [3:0] kernel_width_cfg; +wire last_c; +wire last_line_in; +wire last_out_done; +wire last_pooling_flag; +wire last_splitw; +wire last_sub_lbuf_done; +wire line_end; +wire load_din; +wire load_din_all; +wire load_wr_stage1; +wire load_wr_stage1_all; +wire load_wr_stage2; +wire load_wr_stage2_all; +wire load_wr_stage3; +wire load_wr_stage3_all; +wire [7:0] mem_data_valid; +wire [8:0] mem_raddr; +wire [5:0] mem_raddr_2d_sync; +wire [1*(8 +6)+3:0] mem_rdata_0; +wire [1*(8 +6)+3:0] mem_rdata_1; +wire [1*(8 +6)+3:0] mem_rdata_2; +wire [1*(8 +6)+3:0] mem_rdata_3; +wire [1*(8 +6)+3:0] mem_rdata_4; +wire [1*(8 +6)+3:0] mem_rdata_5; +wire [1*(8 +6)+3:0] mem_rdata_6; +wire [1*(8 +6)+3:0] mem_rdata_7; +wire [7:0] mem_re; +wire [7:0] mem_re1; +wire [7:0] mem_re1_1st; +wire [7:0] mem_re2; +wire [7:0] mem_re2_1st; +wire [7:0] mem_re2_last; +wire [7:0] mem_re3; +wire [7:0] mem_re3_1st; +wire [7:0] mem_re3_last; +wire [7:0] mem_re4; +wire [7:0] mem_re4_1st; +wire [7:0] mem_re4_last; +wire [7:0] mem_re_1st; +wire [7:0] mem_re_1st_2d_sync; +wire [7:0] mem_re_2d_sync; +wire [7:0] mem_re_last; +wire [8:0] mem_waddr_0; +wire [8:0] mem_waddr_1; +wire [8:0] mem_waddr_2; +wire [8:0] mem_waddr_3; +wire [8:0] mem_waddr_4; +wire [8:0] mem_waddr_5; +wire [8:0] mem_waddr_6; +wire [8:0] mem_waddr_7; +wire [1*(8 +6)+3:0] mem_wdata_0; +wire [1*(8 +6)+3:0] mem_wdata_1; +wire [1*(8 +6)+3:0] mem_wdata_2; +wire [1*(8 +6)+3:0] mem_wdata_3; +wire [1*(8 +6)+3:0] mem_wdata_4; +wire [1*(8 +6)+3:0] mem_wdata_5; +wire [1*(8 +6)+3:0] mem_wdata_6; +wire [1*(8 +6)+3:0] mem_wdata_7; +wire [7:0] mem_we; +wire middle_surface_trig; +wire [0:0] mon_first_out_num; +wire mon_flush_in_next_surf; +wire mon_flush_num_dec1; +wire [0:0] mon_pad_table_index; +wire mon_pad_value; +wire [1:0] mon_pooling_size_minus_sride; +wire mon_rest_height; +wire [5:0] mon_strip_ycnt_offset; +wire [1:0] mon_unit2d_cnt_pooling_max; +wire need_flush; +wire one_width_bubble_end; +wire one_width_disable_2d_sync; +wire one_width_norm_rdy; +wire [2:0] pad_l; +wire [16:0] pad_line_sum; +wire pad_line_sum_prdy; +wire pad_line_sum_pvld; +wire [2:0] pad_r; +wire [2:0] pad_table_index; +wire [21:0] pad_value; +wire padding_here; +wire [2:0] padding_stride1_num; +wire [2:0] padding_stride2_num; +wire [2:0] padding_stride3_num; +wire [2:0] padding_stride4_num; +wire pooling1d_norm_rdy; +wire [1*(8 +6)-1:0] pooling1d_pd_use; +wire pooling1d_prdy_use; +wire pooling1d_pvld_use; +wire pooling1d_vld_rebuild; +wire [31:0] pooling_2d_info; +wire [3:0] pooling_2d_info_0; +wire [3:0] pooling_2d_info_1; +wire [3:0] pooling_2d_info_2; +wire [3:0] pooling_2d_info_3; +wire [3:0] pooling_2d_info_4; +wire [3:0] pooling_2d_info_5; +wire [3:0] pooling_2d_info_6; +wire [3:0] pooling_2d_info_7; +wire [31:0] pooling_2d_info_sync; +wire pooling_2d_rdy; +wire [1*(8 +6)-1:0] pooling_2d_result_0; +wire [1*(8 +6)-1:0] pooling_2d_result_1; +wire [1*(8 +6)-1:0] pooling_2d_result_2; +wire [1*(8 +6)-1:0] pooling_2d_result_3; +wire [1*(8 +6)-1:0] pooling_2d_result_4; +wire [1*(8 +6)-1:0] pooling_2d_result_5; +wire [1*(8 +6)-1:0] pooling_2d_result_6; +wire [1*(8 +6)-1:0] pooling_2d_result_7; +wire [1*(8 +6)-1:0] pooling_datin; +wire [1*(8 +6)-1:0] pooling_datin_ext; +wire [3:0] pooling_size; +wire [2:0] pooling_size_minus_sride; +wire [3:0] pooling_size_v; +wire pooling_stride_big; +wire [4:0] pooling_stride_v; +wire pout_data_stage0_prdy; +wire pout_data_stage1_prdy; +wire pout_data_stage2_prdy; +wire pout_data_stage3_prdy; +wire [1*(8 +6)+2:0] pout_mem_data; +wire [1*(8 +6)+2:0] pout_mem_data_last; +wire [1*(8 +6)+2:0] pout_mem_data_last_sync; +wire [7:0] pout_mem_data_sel; +wire [7:0] pout_mem_data_sel_0; +wire [7:0] pout_mem_data_sel_1; +wire [7:0] pout_mem_data_sel_1_last; +wire [7:0] pout_mem_data_sel_2; +wire [7:0] pout_mem_data_sel_2_last; +wire [7:0] pout_mem_data_sel_3; +wire [7:0] pout_mem_data_sel_3_last; +wire [7:0] pout_mem_data_sel_last; +wire [7:0] pout_mem_data_sel_last_sync; +wire [7:0] pout_mem_data_sel_sync; +wire [2:0] pout_mem_size_v_use; +wire [12:0] pout_width_cur; +wire rd_comb_lbuf_end; +wire rd_lbuf_end; +wire rd_line_out; +wire rd_line_out_done; +wire rd_pout_data_en; +wire rd_pout_data_stage0; +wire rd_pout_data_stage1; +wire rd_pout_data_stage1_all; +wire rd_pout_data_stage2; +wire rd_pout_data_stage2_all; +wire rd_sub_lbuf_end; +wire [12:0] rest_height; +wire [13:0] rest_height_use; +wire small_active; +wire splitw_enable; +wire [4:0] stride; +wire [4:0] stride_1x; +wire [5:0] stride_2x; +wire [6:0] stride_3x; +wire [6:0] stride_4x; +wire [7:0] stride_5x; +wire [7:0] stride_6x; +wire [7:0] stride_7x; +wire stride_end; +wire stride_trig_end; +wire [2:0] strip_ycnt_offset; +wire stripe_receive_done; +wire sub_lbuf_dout_done; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "wire [12-${k}:0] surface_num; \n"; +//: print "reg [12-${k}:0] surface_cnt_rd; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [12-3:0] surface_num; +reg [12-3:0] surface_cnt_rd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [9:0] surface_num_0; +//wire [9:0] surface_num_1; +wire [7:0] unit2d_clr; +wire [3:0] unit2d_cnt_pooling_a1; +wire [3:0] unit2d_cnt_pooling_a2; +wire [3:0] unit2d_cnt_pooling_a3; +wire [3:0] unit2d_cnt_pooling_a4; +wire [3:0] unit2d_cnt_pooling_a5; +wire [3:0] unit2d_cnt_pooling_a6; +wire [3:0] unit2d_cnt_pooling_a7; +wire unit2d_cnt_pooling_end; +wire unit2d_cnt_pooling_last_end; +wire [2:0] unit2d_cnt_pooling_max; +wire [7:0] unit2d_en_last; +wire [7:0] unit2d_set; +wire [7:0] unit2d_set_trig; +wire [2:0] unit2d_vsize1_0; +wire [2:0] unit2d_vsize1_1; +wire [2:0] unit2d_vsize1_2; +wire [2:0] unit2d_vsize1_3; +wire [2:0] unit2d_vsize1_4; +wire [2:0] unit2d_vsize1_5; +wire [2:0] unit2d_vsize1_6; +wire [2:0] unit2d_vsize1_7; +wire [2:0] unit2d_vsize2_0; +wire [2:0] unit2d_vsize2_1; +wire [2:0] unit2d_vsize2_2; +wire [2:0] unit2d_vsize2_3; +wire [2:0] unit2d_vsize2_4; +wire [2:0] unit2d_vsize2_5; +wire [2:0] unit2d_vsize2_6; +wire [2:0] unit2d_vsize2_7; +wire [2:0] unit2d_vsize3_0; +wire [2:0] unit2d_vsize3_1; +wire [2:0] unit2d_vsize3_2; +wire [2:0] unit2d_vsize3_3; +wire [2:0] unit2d_vsize3_4; +wire [2:0] unit2d_vsize3_5; +wire [2:0] unit2d_vsize3_6; +wire [2:0] unit2d_vsize3_7; +wire [2:0] unit2d_vsize4_0; +wire [2:0] unit2d_vsize4_1; +wire [2:0] unit2d_vsize4_2; +wire [2:0] unit2d_vsize4_3; +wire [2:0] unit2d_vsize4_4; +wire [2:0] unit2d_vsize4_5; +wire [2:0] unit2d_vsize4_6; +wire [2:0] unit2d_vsize4_7; +wire [2:0] unit2d_vsize_0; +wire [2:0] unit2d_vsize_1; +wire [2:0] unit2d_vsize_2; +wire [2:0] unit2d_vsize_3; +wire [2:0] unit2d_vsize_4; +wire [2:0] unit2d_vsize_5; +wire [2:0] unit2d_vsize_6; +wire [2:0] unit2d_vsize_7; +wire [2:0] up_pnum0; +wire wr_data_stage0_prdy; +wire wr_data_stage1_prdy; +wire wr_line_dat_done; +wire wr_subcube_dat_done; +wire wr_surface_dat_done; +wire wr_total_cube_done; +reg [3:0] bank_merge_num; +reg [2:0] bubble_add; +reg [2:0] bubble_cnt; +reg [2:0] bubble_num; +reg [2:0] bubble_num_use; +reg [3:0] buffer_lines_num; +reg [4:0] c_cnt; +reg [4:0] channel_cnt; +reg cube_end_flag; +reg cur_datin_disable; +reg cur_datin_disable_2d; +reg cur_datin_disable_3d; +reg cur_datin_disable_d; +reg [1*(8 +6)-1:0] datin_buf; +reg [1*(8 +6)-1:0] datin_buf_2d; +reg [2:0] flush_num; +reg [2:0] flush_num_cal; +reg flush_read_en_d; +reg [8:0] int_mem_waddr; +reg [1*(8 +6)+3:0] int_mem_wdata_0; +reg [1*(8 +6)+3:0] int_mem_wdata_1; +reg [1*(8 +6)+3:0] int_mem_wdata_2; +reg [1*(8 +6)+3:0] int_mem_wdata_3; +reg [1*(8 +6)+3:0] int_mem_wdata_4; +reg [1*(8 +6)+3:0] int_mem_wdata_5; +reg [1*(8 +6)+3:0] int_mem_wdata_6; +reg [1*(8 +6)+3:0] int_mem_wdata_7; +reg [7:0] int_mem_we; +reg is_one_width_in; +reg last_active_line_2d; +reg last_active_line_d; +reg [2:0] last_out_cnt; +reg last_out_en; +reg [12:0] line_cnt; +reg [1*(8 +6)+2:0] mem_data0; +reg [1*(8 +6)+2:0] mem_data0_lst; +reg [1*(8 +6)+2:0] mem_data1; +reg [1*(8 +6)+2:0] mem_data1_lst; +reg [1*(8 +6)+2:0] mem_data2; +reg [1*(8 +6)+2:0] mem_data2_lst; +reg [1*(8 +6)+2:0] mem_data3; +reg [1*(8 +6)+2:0] mem_data3_lst; +reg [1*(8 +6)+2:0] mem_data4; +reg [1*(8 +6)+2:0] mem_data4_lst; +reg [1*(8 +6)+2:0] mem_data5; +reg [1*(8 +6)+2:0] mem_data5_lst; +reg [1*(8 +6)+2:0] mem_data6; +reg [1*(8 +6)+2:0] mem_data6_lst; +reg [1*(8 +6)+2:0] mem_data7; +reg [1*(8 +6)+2:0] mem_data7_lst; +reg [8:0] mem_raddr_2d; +reg [8:0] mem_raddr_d; +reg mem_re1_sel; +reg mem_re2_sel; +reg mem_re2_sel_last; +reg mem_re3_sel; +reg mem_re3_sel_last; +reg mem_re4_sel; +reg mem_re4_sel_last; +reg [7:0] mem_re_1st_2d; +reg [7:0] mem_re_1st_d; +reg [7:0] mem_re_2d; +reg [7:0] mem_re_d; +reg [7:0] mem_re_last_2d; +reg [7:0] mem_re_last_d; +reg need_bubble; +reg [2:0] next2_0; +reg [2:0] next2_1; +reg [2:0] next3_0; +reg [2:0] next3_1; +reg [2:0] next3_2; +reg [2:0] next4_0; +reg [2:0] next4_1; +reg [2:0] next4_2; +reg [2:0] next4_3; +reg [2:0] next5_0; +reg [2:0] next5_1; +reg [2:0] next5_2; +reg [2:0] next5_3; +reg [2:0] next5_4; +reg [2:0] next6_0; +reg [2:0] next6_1; +reg [2:0] next6_2; +reg [2:0] next6_3; +reg [2:0] next6_4; +reg [2:0] next6_5; +reg [2:0] next7_0; +reg [2:0] next7_1; +reg [2:0] next7_2; +reg [2:0] next7_3; +reg [2:0] next7_4; +reg [2:0] next7_5; +reg [2:0] next7_6; +reg [2:0] one_width_bubble_cnt; +reg one_width_disable; +reg one_width_disable_2d; +reg one_width_disable_3d; +reg one_width_disable_d; +reg [5:0] pad_r_remain; +reg [18:0] pad_table_out; +reg [2:0] padding_stride_num; +reg [2:0] pnum_flush0; +reg [2:0] pnum_flush1; +reg [2:0] pnum_flush2; +reg [2:0] pnum_flush3; +reg [2:0] pnum_flush4; +reg [2:0] pnum_flush5; +reg [2:0] pnum_flush6; +reg pout_data_stage1_vld; +reg pout_data_stage2_vld; +reg pout_data_stage3_vld; +//: my $k = 1; +//: my $x = 8; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: reg [${m}-1:0] pout_mem_data_$i; +//: // wire [${m}-1:0] pout_mem_data$i; +//: wire [${m}:0] data_8bit_${i}; +//: wire [${m}:0] data_8bit_${i}_ff; +//: wire mon_data_8bit_${i}; +//: wire mon_data_8bit_${i}_ff; +//: reg [${m}:0] pout_data_0_${i}; +//: wire [${m}+16:0] data_hmult_8bit_${i}_ext_ff; +//: wire [${m}+16:0] data_hmult_8bit_${i}_ext; +//: wire i8_less_neg_0_5_${i}; +//: wire i8_more_neg_0_5_${i}; +//: wire mon_i8_neg_add1_${i}; +//: wire [${j}-1:0] i8_neg_add1_${i}; +//: wire [${j}-1:0] hmult_8bit_${i}; +//: wire [${j}-1:0] data_hmult_8bit_${i}; +//: wire [${j}-1:0] data_hmult_stage0_in$i; +//: reg [${j}-1:0] pout_data_stage0_$i; +//: wire [${j}+16:0] data_vmult_8bit_${i}_ext_ff; +//: wire [${j}+16:0] data_vmult_8bit_${i}_ext; +//: wire i8_vless_neg_0_5_${i}; +//: wire i8_vmore_neg_0_5_${i}; +//: wire mon_i8_neg_vadd1_${i}; +//: wire [${x}-1:0] i8_neg_vadd1_${i}; +//: wire [${x}-1:0] vmult_8bit_${i}; +//: wire [${x}-1:0] data_vmult_8bit_${i}; +//: wire [${x}-1:0] data_mult_stage1_in${i}; +//: reg [${x}-1:0] pout_data_stage1_${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +reg [14-1:0] pout_mem_data_0; +// wire [14-1:0] pout_mem_data0; +wire [14:0] data_8bit_0; +wire [14:0] data_8bit_0_ff; +wire mon_data_8bit_0; +wire mon_data_8bit_0_ff; +reg [14:0] pout_data_0_0; +wire [14+16:0] data_hmult_8bit_0_ext_ff; +wire [14+16:0] data_hmult_8bit_0_ext; +wire i8_less_neg_0_5_0; +wire i8_more_neg_0_5_0; +wire mon_i8_neg_add1_0; +wire [11-1:0] i8_neg_add1_0; +wire [11-1:0] hmult_8bit_0; +wire [11-1:0] data_hmult_8bit_0; +wire [11-1:0] data_hmult_stage0_in0; +reg [11-1:0] pout_data_stage0_0; +wire [11+16:0] data_vmult_8bit_0_ext_ff; +wire [11+16:0] data_vmult_8bit_0_ext; +wire i8_vless_neg_0_5_0; +wire i8_vmore_neg_0_5_0; +wire mon_i8_neg_vadd1_0; +wire [8-1:0] i8_neg_vadd1_0; +wire [8-1:0] vmult_8bit_0; +wire [8-1:0] data_vmult_8bit_0; +wire [8-1:0] data_mult_stage1_in0; +reg [8-1:0] pout_data_stage1_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [1*(8 +6)+2:0] pout_mem_data_act; +reg [2:0] pout_mem_size_v; +reg [12:0] pout_width_cur_latch; +reg [2:0] rd_comb_lbuf_cnt; +reg [8:0] rd_line_out_cnt; +reg rd_pout_data_en_2d; +reg rd_pout_data_en_3d; +reg rd_pout_data_en_4d; +reg rd_pout_data_en_d; +reg [2:0] rd_sub_lbuf_cnt; +reg [16:0] reg2dp_recip_height_use; +reg [16:0] reg2dp_recip_width_use; +reg [2:0] samllH_flush_num; +reg [2:0] strip_ycnt_psize; +reg [3:0] strip_ycnt_stride; +reg [3:0] strip_ycnt_stride_f; +reg [8:0] sub_lbuf_dout_cnt; +reg subend_need_flush_flg; +reg surfend_need_bubble_flg; +reg [2:0] unit2d_cnt_pooling; +reg [2:0] unit2d_cnt_pooling_last; +reg [2:0] unit2d_cnt_pooling_last_2d; +reg [2:0] unit2d_cnt_pooling_last_d; +reg [2:0] unit2d_cnt_stride; +reg [7:0] unit2d_en; +reg [7:0] unit2d_mem_1strd; +reg [2:0] unit2d_vsize_cnt_0; +reg [2:0] unit2d_vsize_cnt_0_d; +reg [2:0] unit2d_vsize_cnt_1; +reg [2:0] unit2d_vsize_cnt_1_d; +reg [2:0] unit2d_vsize_cnt_2; +reg [2:0] unit2d_vsize_cnt_2_d; +reg [2:0] unit2d_vsize_cnt_3; +reg [2:0] unit2d_vsize_cnt_3_d; +reg [2:0] unit2d_vsize_cnt_4; +reg [2:0] unit2d_vsize_cnt_4_d; +reg [2:0] unit2d_vsize_cnt_5; +reg [2:0] unit2d_vsize_cnt_5_d; +reg [2:0] unit2d_vsize_cnt_6; +reg [2:0] unit2d_vsize_cnt_6_d; +reg [2:0] unit2d_vsize_cnt_7; +reg [2:0] unit2d_vsize_cnt_7_d; +reg up_pnum1; +reg [1:0] up_pnum2; +reg [1:0] up_pnum3; +reg [2:0] up_pnum4; +reg [2:0] up_pnum5; +reg wr_data_stage0_vld; +reg wr_data_stage1_vld; +reg wr_data_stage2_vld; +reg [12:0] wr_line_dat_cnt; +reg wr_line_end_2d; +reg wr_line_end_buf; +reg [7:0] wr_splitc_cnt; +reg [2:0] wr_sub_lbuf_cnt; +reg [12:0] wr_surface_dat_cnt; +reg wr_surface_dat_done_2d; +reg wr_surface_dat_done_buf; +///////////////////////////////////////////////////////////////////////////////////////// +//============================================================== +////pdp cube_out_width setting +////////////////////////////// +//pdp cube_out_width setting, limited by line buffer size +////////////////////////////// +//non-split mode +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd127) & (bank_merge_num==4'd8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd63) & (bank_merge_num==4'd4)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd31) & (bank_merge_num==4'd2)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd15) & (bank_merge_num==4'd1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============================================================== +//bank depth follows rule of 16 elements in width in worst case +//it's 64 in t194 +//-------------------------------------------------------------- +//: my $depth = (8/1)*16-1; +//: print " assign BANK_DEPTH = 9'd${depth}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign BANK_DEPTH = 9'd127; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============================================================== +// buffer the input data from pooling 1D unit +// calculate the data postion in input-data-cube +// +//-------------------------------------------------------------- +assign pooling1d_prdy = pooling1d_prdy_use; +assign pooling1d_pvld_use = pooling1d_pvld; +assign pooling1d_pd_use = pooling1d_pd; +assign pooling1d_prdy_use = one_width_norm_rdy & (~cur_datin_disable); +assign one_width_norm_rdy = pooling1d_norm_rdy & (~one_width_disable); +////////////////////////////////////////////////////////////////////////////////////// +assign load_din = pooling1d_prdy_use & pooling1d_pvld_use; +assign stripe_receive_done = load_din & data_c_end; +assign average_pooling_en = (pooling_type_cfg== 2'h0 ); +//assign int8_en = (reg2dp_input_data[1:0] == 2'h0 ); +//assign int16_en = (reg2dp_input_data[1:0] == 2'h1 ); +////////////////////////////////////////////////////////////////////////////////////// +//: my $m = 8; +//: my $k = 1; +//: my $j = int($m / $k); +//: print "assign data_c_end = (c_cnt == 5'd${j}-1); \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign data_c_end = (c_cnt == 5'd8-1); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + c_cnt[4:0] <= 0; + end else if(load_din) begin + if(data_c_end) + c_cnt[4:0] <= 0; + else + c_cnt[4:0] <= c_cnt + 1'b1; + end +end +//end of line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_dat_cnt[12:0] <= {13{1'b0}}; + end else begin + if(wr_line_dat_done) + wr_line_dat_cnt[12:0] <= 0; + else if(stripe_receive_done) + wr_line_dat_cnt[12:0] <= wr_line_dat_cnt + 1; + end +end +assign wr_line_dat_done = (wr_line_dat_cnt==pout_width_cur) & stripe_receive_done; +//end of surface +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_cnt <= {13{1'b0}}; + end else begin + if(wr_surface_dat_done) + wr_surface_dat_cnt <= 13'd0; + else if(wr_line_dat_done) + wr_surface_dat_cnt <= wr_surface_dat_cnt + 13'd1; + end +end +assign last_line_in = ( wr_surface_dat_cnt==reg2dp_cube_in_height[12:0]); +assign wr_surface_dat_done = wr_line_dat_done & last_line_in; +//end of splitw +//assign cube_out_channel[13:0]= pooling_channel_cfg[12:0] + 1'b1; +//////16bits: INT16 or FP16 +////assign {mon_surface_num_0,surface_num_0[9:0]} = cube_out_channel[13:4] + {9'd0,(|cube_out_channel[3:0])}; +//////8bits: INT8 +////assign surface_num_1[9:0] = {1'b0,cube_out_channel[13:5]} + (|cube_out_channel[4:0]); +////assign surface_num = int8_en ? surface_num_1 : surface_num_0; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "assign surface_num = pooling_channel_cfg[12:${k}]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign surface_num = pooling_channel_cfg[12:3]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surface_cnt_rd <= 0; + end else begin + if(wr_subcube_dat_done) + surface_cnt_rd <= 0; + else if(wr_surface_dat_done) + surface_cnt_rd <= surface_cnt_rd + 1; + end +end +assign wr_subcube_dat_done = (surface_num==surface_cnt_rd) & wr_surface_dat_done; +//total cube done +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_splitc_cnt[7:0] <= {8{1'b0}}; + end else begin + if(wr_total_cube_done) + wr_splitc_cnt[7:0] <= 8'd0; + else if(wr_subcube_dat_done) + wr_splitc_cnt[7:0] <= wr_splitc_cnt + 1; + end +end +assign wr_total_cube_done = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & wr_subcube_dat_done; +////////////////////////////////////////////////////////////////////////////////////// +//split width selection +assign splitw_enable = (pooling_splitw_num_cfg!=8'd0); +assign last_splitw = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & splitw_enable; +assign first_splitw = (wr_splitc_cnt==8'd0) & splitw_enable; +assign pout_width_cur[12:0]= (~splitw_enable) ? reg2dp_cube_out_width[12:0] : + (last_splitw ? {3'd0,pooling_out_lwidth_cfg[9:0]} : + first_splitw ? {3'd0,pooling_out_fwidth_cfg[9:0]} : + {3'd0,pooling_out_mwidth_cfg[9:0]}); +///////////////////////////////////////////////////////////////////////////////////// +// assign data_posinfo = wr_line_dat_done; +//============================================================= +// physical memory bank 8 +// 8 memory banks are used to load maximum 8 pooling output lines +// +//------------------------------------------------------------- +//maximum pooling output lines need to be buffer +//stride 1 +assign buffer_lines_0[3:0] = pooling_size_v[3:0]; +//stride 2 +assign buffer_lines_1[3:0] = {1'd0,pooling_size_v[3:1]} + pooling_size_v[0]; +//stride 3 +assign buffer_lines_2[3:0] = (3'd5>= pooling_size_v_cfg[2:0] ) ? 4'd2: 4'd3; +//stride 4 5 6 7 +assign buffer_lines_3 = 4'd2; +assign pooling_stride_big = (pooling_stride_v_cfg>={1'b0,pooling_size_v_cfg[2:0]}); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_lines_num <= {4{1'b0}}; + end else begin + if(pdp_op_start) begin + if(pooling_stride_big) + buffer_lines_num <= 4'd1; + else begin + case(pooling_stride_v_cfg) + 4'd0: buffer_lines_num <= buffer_lines_0; + 4'd1: buffer_lines_num <= buffer_lines_1; + 4'd2: buffer_lines_num <= buffer_lines_2; + default: buffer_lines_num <= buffer_lines_3; + endcase + end + end + end +end +//memory bank merge num +always @( + buffer_lines_num + ) begin + case(buffer_lines_num) + 4'd1: bank_merge_num = 4'd8; + 4'd2: bank_merge_num = 4'd4; + 4'd4,4'd3: bank_merge_num = 4'd2; + default : bank_merge_num = 4'd1; + endcase +end +//========================================================== +//bank active enable signal +// +//---------------------------------------------------------- +//stride intial data +//stride ==1 +assign padding_stride1_num[2:0] = padding_v_cfg[2:0]; +//stride ==2 +assign padding_stride2_num[2:0] = {1'b0,padding_v_cfg[2:1]}; +//stride ==3 +assign padding_stride3_num[2:0]= (padding_v_cfg[2:0]>=3'd6) ? 3'd2 : + (padding_v_cfg[2:0]>=3'd3) ? 3'd1 : 3'd0; +//stride==4 5 6 7 +assign padding_stride4_num[2:0]= ({1'b0,padding_v_cfg[2:0]}>pooling_stride_v_cfg) ? 3'd1:3'd0; +assign pooling_stride_v[4:0] = pooling_stride_v_cfg[3:0] + 1; +//real num-1 +always @( + pooling_stride_v_cfg + or padding_stride1_num + or padding_stride2_num + or padding_stride3_num + or padding_stride4_num + ) begin + case(pooling_stride_v_cfg[3:0]) + 4'd0: padding_stride_num = padding_stride1_num; + 4'd1: padding_stride_num = padding_stride2_num; + 4'd2: padding_stride_num = padding_stride3_num; + default:padding_stride_num=padding_stride4_num; + endcase +end +assign {mon_strip_ycnt_offset[5:0],strip_ycnt_offset[2:0]} = {5'd0,padding_v_cfg} - padding_stride_num * pooling_stride_v; +///////////////////////////////////////////////////////////////////////////////// +assign middle_surface_trig = wr_surface_dat_done & (~wr_total_cube_done); +assign stride_end = wr_line_dat_done & (strip_ycnt_stride== pooling_stride_v_cfg); +assign init_cnt = middle_surface_trig | pdp_op_start; +//pooling stride in vertical direction +always @( + init_cnt + or strip_ycnt_offset + or stride_end + or wr_line_dat_done + or strip_ycnt_stride + ) begin + if(init_cnt) + strip_ycnt_stride_f[3:0] = {1'b0,strip_ycnt_offset}; + else if(stride_end) + strip_ycnt_stride_f[3:0] = 4'd0; + else if(wr_line_dat_done) + strip_ycnt_stride_f[3:0] = strip_ycnt_stride + 1; + else + strip_ycnt_stride_f[3:0] = strip_ycnt_stride; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_ycnt_stride[3:0] <= {4{1'b0}}; + end else begin + if ((init_cnt | stride_end | wr_line_dat_done) == 1'b1) begin + strip_ycnt_stride[3:0] <= strip_ycnt_stride_f; +// VCS coverage off + end else if ((init_cnt | stride_end | wr_line_dat_done) == 1'b0) begin + end else begin + strip_ycnt_stride[3:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(init_cnt | stride_end | wr_line_dat_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//2D pooling result ready +assign {mon_pooling_size_minus_sride[1:0],pooling_size_minus_sride[2:0]} = {1'b0,pooling_size_v_cfg[2:0]} - pooling_stride_v_cfg[3:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_ycnt_psize <= {3{1'b0}}; + end else begin + if(init_cnt) + strip_ycnt_psize[2:0] <= padding_v_cfg[2:0]; + else if({1'b0,pooling_size_v_cfg} >= pooling_stride_v_cfg) begin + if(pooling_2d_rdy) + strip_ycnt_psize <= pooling_size_minus_sride[2:0]; + else if(wr_line_dat_done) + strip_ycnt_psize <= strip_ycnt_psize + 1; + end else begin // pooling_size < stride + if(strip_ycnt_stride_f <= {1'b0,pooling_size_v_cfg}) + strip_ycnt_psize <= strip_ycnt_stride_f[2:0]; + else + strip_ycnt_psize <= 3'd0; + end + end +end +//===================================================================== +assign pooling_size_v[3:0] = pooling_size_v_cfg[2:0] + 1; +assign pooling_size[3:0] = pooling_size_v; +assign stride[4:0] = pooling_stride_v; +assign pad_l[2:0] = padding_v_cfg; +assign pad_r = reg2dp_pad_bottom_cfg[2:0];//3'd1; +//active_data_num_last_pooling = (pad_l + width) % stride; +//assign {mon_active_data_num_last_pooling[1:0],active_data_num_last_pooling[2:0]} = pooling_size - pad_r; +//line num need flush at surface end +always @( + pad_r + or stride_1x + or stride_2x + or stride_3x + or stride_4x + or stride_5x + or stride_6x + or stride_7x + ) begin + if({2'd0,pad_r} < stride_1x[4:0]) + flush_num_cal = 3'd0; + else if({3'd0,pad_r} < stride_2x[5:0]) + flush_num_cal = 3'd1; + else if({4'd0,pad_r} < stride_3x[6:0]) + flush_num_cal = 3'd2; + else if({4'd0,pad_r} < stride_4x[6:0]) + flush_num_cal = 3'd3; + else if({5'd0,pad_r} < stride_5x[7:0]) + flush_num_cal = 3'd4; + else if({5'd0,pad_r} < stride_6x[7:0]) + flush_num_cal = 3'd5; + else if({5'd0,pad_r} < stride_7x[7:0]) + flush_num_cal = 3'd6; + else// if({5'd0,pad_r} = stride_7x[7:0]) + flush_num_cal = 3'd7; +end +//small input detect +assign small_active = ((~(|reg2dp_cube_in_height[12:3])) & ((reg2dp_cube_in_height[2:0] + reg2dp_pad_top[2:0]) < {1'b0,reg2dp_kernel_height[2:0]})); +//non-split mode cube_width + pad_left + pad_right +assign h_pt[3:0] = reg2dp_cube_in_height[2:0] + reg2dp_pad_top[2:0]; +assign h_pt_pb[4:0] = h_pt[3:0] + {1'b0,pad_r}; +//pad_right remain afrer 1st kernel pooling +always @( + small_active + or h_pt_pb + or reg2dp_kernel_height + ) begin + if(small_active) + pad_r_remain[5:0] = h_pt_pb[4:0] - {2'd0,reg2dp_kernel_height[2:0]} ; + else + pad_r_remain[5:0] = 6'd0 ; +end +//how many need bubble after 1st kernel pooling +always @( + pad_r_remain + or stride_6x + or stride_5x + or stride_4x + or stride_3x + or stride_2x + or stride_1x + ) begin + if({2'd0,pad_r_remain} == stride_6x[7:0]) + samllH_flush_num = 3'd6; + else if({2'd0,pad_r_remain} == stride_5x[7:0]) + samllH_flush_num = 3'd5; + else if({1'b0,pad_r_remain} == stride_4x[6:0]) + samllH_flush_num = 3'd4; + else if({1'b0,pad_r_remain} == stride_3x[6:0]) + samllH_flush_num = 3'd3; + else if(pad_r_remain == stride_2x[5:0]) + samllH_flush_num = 3'd2; + else if(pad_r_remain == {1'b0,stride_1x[4:0]}) + samllH_flush_num = 3'd1; + else// if(pad_r_remain == 8'd0) + samllH_flush_num = 3'd0; +end +//flush num calc +always @( + flush_num_cal + or small_active + or samllH_flush_num + ) begin + if(flush_num_cal==3'd0) + flush_num[2:0] = 3'd0; + else if(small_active) + flush_num[2:0] = samllH_flush_num; + else + flush_num[2:0] = flush_num_cal[2:0]; +end +assign need_flush = (flush_num != 3'd0); +assign stride_1x[4:0] = stride[4:0]; +assign stride_2x[5:0] = {stride[4:0],1'b0}; +assign stride_3x[6:0] = ( stride_2x+{1'b0,stride[4:0]}); +assign stride_4x[6:0] = {stride[4:0],2'b0}; +assign stride_5x[7:0] = ( stride_4x+{2'd0,stride[4:0]}); +assign stride_6x[7:0] = ( stride_3x+stride_3x); +assign stride_7x[7:0] = ( stride_4x+stride_3x); +//the 1st element/line num need output data +//assign {mon_first_out_num[0],first_out_num[3:0]} = small_active ? {2'd0,reg2dp_cube_in_height[2:0]} : (pooling_size - pad_l); +assign cube_in_height_cfg[3:0] = reg2dp_cube_in_height[2:0] + 3'd1; +assign {mon_first_out_num[0],first_out_num[3:0]} = small_active ? {1'd0,cube_in_height_cfg[3:0]} : (pooling_size - pad_l); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + need_bubble <= 1'b0; + bubble_num_use[2:0] <= {3{1'b0}}; + end else begin +//if(wr_total_cube_done) begin + if(wr_subcube_dat_done) begin + if(need_flush) begin + need_bubble <= 1'b1; + bubble_num_use[2:0] <= flush_num; + end else begin + need_bubble <= 1'b0; + bubble_num_use[2:0] <= 3'd0; + end + end else if(last_line_in) begin + if({1'b0,flush_num} >= first_out_num) begin + need_bubble <= 1'b1; + bubble_num_use[2:0] <= flush_num - first_out_num[2:0] + 1'b1 + bubble_add; + end else if(|bubble_add) begin + need_bubble <= 1'b1; + bubble_num_use[2:0] <= bubble_add; + end else begin + need_bubble <= 1'b0; + bubble_num_use[2:0] <= 3'd0; + end + end + end +end +/////////////////////////////////////////////////////////////////////// +//bubble control when next surface comming . Beginning +/////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_num[2:0] <= {3{1'b0}}; + end else begin + if(pdp_op_start) begin + if({1'b0,flush_num} >= first_out_num) begin + bubble_num[2:0] <= flush_num - first_out_num[2:0] + 1'b1; + end else begin + bubble_num[2:0] <= 3'd0; + end + end + end +end +assign {mon_flush_in_next_surf,flush_in_next_surf[2:0]} = flush_num[2:0] - bubble_num[2:0]; +/////////////// +always @( + flush_in_next_surf + or bubble_num + or pnum_flush1 + or pnum_flush0 + or pnum_flush2 + or pnum_flush3 + or pnum_flush4 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd2) begin + if(bubble_num == 3'd0) begin + next2_1 = pnum_flush1; + next2_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next2_1 = pnum_flush2; + next2_0 = pnum_flush1; + end else if(bubble_num == 3'd2) begin + next2_1 = pnum_flush3; + next2_0 = pnum_flush2; + end else if(bubble_num == 3'd3) begin + next2_1 = pnum_flush4; + next2_0 = pnum_flush3; + end else if(bubble_num == 3'd4) begin + next2_1 = pnum_flush5; + next2_0 = pnum_flush4; + end else begin// else if(bubble_num == 3'd4) begin + next2_1 = pnum_flush6; + next2_0 = pnum_flush5; + end + end else begin + next2_1 = 3'd0; + next2_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush3 + or pnum_flush4 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd3) begin + if(bubble_num == 3'd0) begin + next3_2 = pnum_flush2; + next3_1 = pnum_flush1; + next3_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next3_2 = pnum_flush3; + next3_1 = pnum_flush2; + next3_0 = pnum_flush1; + end else if(bubble_num == 3'd2) begin + next3_2 = pnum_flush4; + next3_1 = pnum_flush3; + next3_0 = pnum_flush2; + end else if(bubble_num == 3'd3) begin + next3_2 = pnum_flush5; + next3_1 = pnum_flush4; + next3_0 = pnum_flush3; + end else begin// else if(bubble_num == 3'd4) begin + next3_2 = pnum_flush6; + next3_1 = pnum_flush5; + next3_0 = pnum_flush4; + end + end else begin + next3_2 = 3'd0; + next3_1 = 3'd0; + next3_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush4 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd4) begin + if(bubble_num == 3'd0) begin + next4_3 = pnum_flush3; + next4_2 = pnum_flush2; + next4_1 = pnum_flush1; + next4_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next4_3 = pnum_flush4; + next4_2 = pnum_flush3; + next4_1 = pnum_flush2; + next4_0 = pnum_flush1; + end else if(bubble_num == 3'd2) begin + next4_3 = pnum_flush5; + next4_2 = pnum_flush4; + next4_1 = pnum_flush3; + next4_0 = pnum_flush2; + end else begin//else if(bubble_num == 3'd3) begin + next4_3 = pnum_flush6; + next4_2 = pnum_flush5; + next4_1 = pnum_flush4; + next4_0 = pnum_flush3; + end + end else begin + next4_3 = 3'd0; + next4_2 = 3'd0; + next4_1 = 3'd0; + next4_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush4 + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd5) begin + if(bubble_num == 3'd0) begin + next5_4 = pnum_flush4; + next5_3 = pnum_flush3; + next5_2 = pnum_flush2; + next5_1 = pnum_flush1; + next5_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next5_4 = pnum_flush5; + next5_3 = pnum_flush4; + next5_2 = pnum_flush3; + next5_1 = pnum_flush2; + next5_0 = pnum_flush1; + end else begin //else if(bubble_num == 3'd2) begin + next5_4 = pnum_flush6; + next5_3 = pnum_flush5; + next5_2 = pnum_flush4; + next5_1 = pnum_flush3; + next5_0 = pnum_flush2; + end + end else begin + next5_4 = 3'd0; + next5_3 = 3'd0; + next5_2 = 3'd0; + next5_1 = 3'd0; + next5_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush5 + or pnum_flush4 + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd6) begin + if(bubble_num == 3'd0) begin + next6_5 = pnum_flush5; + next6_4 = pnum_flush4; + next6_3 = pnum_flush3; + next6_2 = pnum_flush2; + next6_1 = pnum_flush1; + next6_0 = pnum_flush0; + end else begin//else if(bubble_num == 3'd1) begin + next6_5 = pnum_flush6; + next6_4 = pnum_flush5; + next6_3 = pnum_flush4; + next6_2 = pnum_flush3; + next6_1 = pnum_flush2; + next6_0 = pnum_flush1; + end + end else begin + next6_5 = 3'd0; + next6_4 = 3'd0; + next6_3 = 3'd0; + next6_2 = 3'd0; + next6_1 = 3'd0; + next6_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or pnum_flush6 + or pnum_flush5 + or pnum_flush4 + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + ) begin + if(flush_in_next_surf == 4'd7) begin + next7_6 = pnum_flush6; + next7_5 = pnum_flush5; + next7_4 = pnum_flush4; + next7_3 = pnum_flush3; + next7_2 = pnum_flush2; + next7_1 = pnum_flush1; + next7_0 = pnum_flush0; + end else begin + next7_6 = 3'd0; + next7_5 = 3'd0; + next7_4 = 3'd0; + next7_3 = 3'd0; + next7_2 = 3'd0; + next7_1 = 3'd0; + next7_0 = 3'd0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_add <= {3{1'b0}}; + end else begin + if(flush_in_next_surf == 4'd2) begin + if((up_pnum0 == next2_1)|({2'd0,up_pnum1} == next2_1)|({1'b0,up_pnum2} == next2_1)|({1'b0,up_pnum3} == next2_1)|(up_pnum4 == next2_1)|(up_pnum5 == next2_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next2_0)|({2'd0,up_pnum1} == next2_0)|({1'b0,up_pnum2} == next2_0)|({1'b0,up_pnum3} == next2_0)|(up_pnum4 == next2_0)|(up_pnum5 == next2_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd3) begin + if( (up_pnum0 == next3_2)|({2'd0,up_pnum1} == next3_2)|({1'b0,up_pnum2} == next3_2)|({1'b0,up_pnum3} == next3_2)|(up_pnum4 == next3_2)|(up_pnum5 == next3_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next3_1)|({2'd0,up_pnum1} == next3_1)|({1'b0,up_pnum2} == next3_1)|({1'b0,up_pnum3} == next3_1)|(up_pnum4 == next3_1)|(up_pnum5 == next3_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next3_0)|({2'd0,up_pnum1} == next3_0)|({1'b0,up_pnum2} == next3_0)|({1'b0,up_pnum3} == next3_0)|(up_pnum4 == next3_0)|(up_pnum5 == next3_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd4) begin + if( (up_pnum0 == next4_3)|({2'd0,up_pnum1} == next4_3)|({1'b0,up_pnum2} == next4_3)|({1'b0,up_pnum3} == next4_3)|(up_pnum4 == next4_3)|(up_pnum5 == next4_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next4_2)|({2'd0,up_pnum1} == next4_2)|({1'b0,up_pnum2} == next4_2)|({1'b0,up_pnum3} == next4_2)|(up_pnum4 == next4_2)|(up_pnum5 == next4_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next4_1)|({2'd0,up_pnum1} == next4_1)|({1'b0,up_pnum2} == next4_1)|({1'b0,up_pnum3} == next4_1)|(up_pnum4 == next4_1)|(up_pnum5 == next4_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next4_0)|({2'd0,up_pnum1} == next4_0)|({1'b0,up_pnum2} == next4_0)|({1'b0,up_pnum3} == next4_0)|(up_pnum4 == next4_0)|(up_pnum5 == next4_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd5) begin + if( (up_pnum0 == next5_4)|({2'd0,up_pnum1} == next5_4)|({1'b0,up_pnum2} == next5_4)|({1'b0,up_pnum3} == next5_4)|(up_pnum4 == next5_4)|(up_pnum5 == next5_4)) + bubble_add <= 3'd5; + else if((up_pnum0 == next5_3)|({2'd0,up_pnum1} == next5_3)|({1'b0,up_pnum2} == next5_3)|({1'b0,up_pnum3} == next5_3)|(up_pnum4 == next5_3)|(up_pnum5 == next5_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next5_2)|({2'd0,up_pnum1} == next5_2)|({1'b0,up_pnum2} == next5_2)|({1'b0,up_pnum3} == next5_2)|(up_pnum4 == next5_2)|(up_pnum5 == next5_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next5_1)|({2'd0,up_pnum1} == next5_1)|({1'b0,up_pnum2} == next5_1)|({1'b0,up_pnum3} == next5_1)|(up_pnum4 == next5_1)|(up_pnum5 == next5_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next5_0)|({2'd0,up_pnum1} == next5_0)|({1'b0,up_pnum2} == next5_0)|({1'b0,up_pnum3} == next5_0)|(up_pnum4 == next5_0)|(up_pnum5 == next5_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd6) begin + if( (up_pnum0 == next6_5)|({2'd0,up_pnum1} == next6_5)|({1'b0,up_pnum2} == next6_5)|({1'b0,up_pnum3} == next6_5)|(up_pnum4 == next6_5)|(up_pnum5 == next6_5)) + bubble_add <= 3'd6; + else if((up_pnum0 == next6_4)|({2'd0,up_pnum1} == next6_4)|({1'b0,up_pnum2} == next6_4)|({1'b0,up_pnum3} == next6_4)|(up_pnum4 == next6_4)|(up_pnum5 == next6_4)) + bubble_add <= 3'd5; + else if((up_pnum0 == next6_3)|({2'd0,up_pnum1} == next6_3)|({1'b0,up_pnum2} == next6_3)|({1'b0,up_pnum3} == next6_3)|(up_pnum4 == next6_3)|(up_pnum5 == next6_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next6_2)|({2'd0,up_pnum1} == next6_2)|({1'b0,up_pnum2} == next6_2)|({1'b0,up_pnum3} == next6_2)|(up_pnum4 == next6_2)|(up_pnum5 == next6_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next6_1)|({2'd0,up_pnum1} == next6_1)|({1'b0,up_pnum2} == next6_1)|({1'b0,up_pnum3} == next6_1)|(up_pnum4 == next6_1)|(up_pnum5 == next6_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next6_0)|({2'd0,up_pnum1} == next6_0)|({1'b0,up_pnum2} == next6_0)|({1'b0,up_pnum3} == next6_0)|(up_pnum4 == next6_0)|(up_pnum5 == next6_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd7) begin + if( (up_pnum0 == next7_6)|({2'd0,up_pnum1} == next7_6)|({1'b0,up_pnum2} == next7_6)|({1'b0,up_pnum3} == next7_6)|(up_pnum4 == next7_6)|(up_pnum5 == next7_6)) + bubble_add <= 3'd7; + else if((up_pnum0 == next7_5)|({2'd0,up_pnum1} == next7_5)|({1'b0,up_pnum2} == next7_5)|({1'b0,up_pnum3} == next7_5)|(up_pnum4 == next7_5)|(up_pnum5 == next7_5)) + bubble_add <= 3'd6; + else if((up_pnum0 == next7_4)|({2'd0,up_pnum1} == next7_4)|({1'b0,up_pnum2} == next7_4)|({1'b0,up_pnum3} == next7_4)|(up_pnum4 == next7_4)|(up_pnum5 == next7_4)) + bubble_add <= 3'd5; + else if((up_pnum0 == next7_3)|({2'd0,up_pnum1} == next7_3)|({1'b0,up_pnum2} == next7_3)|({1'b0,up_pnum3} == next7_3)|(up_pnum4 == next7_3)|(up_pnum5 == next7_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next7_2)|({2'd0,up_pnum1} == next7_2)|({1'b0,up_pnum2} == next7_2)|({1'b0,up_pnum3} == next7_2)|(up_pnum4 == next7_2)|(up_pnum5 == next7_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next7_1)|({2'd0,up_pnum1} == next7_1)|({1'b0,up_pnum2} == next7_1)|({1'b0,up_pnum3} == next7_1)|(up_pnum4 == next7_1)|(up_pnum5 == next7_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next7_0)|({2'd0,up_pnum1} == next7_0)|({1'b0,up_pnum2} == next7_0)|({1'b0,up_pnum3} == next7_0)|(up_pnum4 == next7_0)|(up_pnum5 == next7_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else begin + bubble_add <= 3'd0; + end + end +end +//------------------------- +assign unit2d_cnt_pooling_a1[3:0] = unit2d_cnt_pooling[2:0] + 3'd1; +assign unit2d_cnt_pooling_a2[3:0] = unit2d_cnt_pooling[2:0] + 3'd2; +assign unit2d_cnt_pooling_a3[3:0] = unit2d_cnt_pooling[2:0] + 3'd3; +assign unit2d_cnt_pooling_a4[3:0] = unit2d_cnt_pooling[2:0] + 3'd4; +assign unit2d_cnt_pooling_a5[3:0] = unit2d_cnt_pooling[2:0] + 3'd5; +assign unit2d_cnt_pooling_a6[3:0] = unit2d_cnt_pooling[2:0] + 3'd6; +assign unit2d_cnt_pooling_a7[3:0] = unit2d_cnt_pooling[2:0] + 3'd7; +//pooling No. in flush time +always @(posedge nvdla_core_clk) begin +//if(wr_surface_dat_done) begin + if(last_line_in) begin + if(unit2d_cnt_pooling[2:0] == unit2d_cnt_pooling_max) begin + pnum_flush0 <= 3'd0; + pnum_flush1 <= 3'd1; + pnum_flush2 <= 3'd2; + pnum_flush3 <= 3'd3; + pnum_flush4 <= 3'd4; + pnum_flush5 <= 3'd5; + pnum_flush6 <= 3'd6; + end else if(unit2d_cnt_pooling_a1 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling_max; + pnum_flush1 <= 3'd0; + pnum_flush2 <= 3'd1; + pnum_flush3 <= 3'd2; + pnum_flush4 <= 3'd3; + pnum_flush5 <= 3'd4; + pnum_flush6 <= 3'd5; + end else if(unit2d_cnt_pooling_a2 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'b1; + pnum_flush1 <= unit2d_cnt_pooling_max; + pnum_flush2 <= 3'd0; + pnum_flush3 <= 3'd1; + pnum_flush4 <= 3'd2; + pnum_flush5 <= 3'd3; + pnum_flush6 <= 3'd4; + end else if(unit2d_cnt_pooling_a3 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling_max; + pnum_flush3 <= 3'd0; + pnum_flush4 <= 3'd1; + pnum_flush5 <= 3'd2; + pnum_flush6 <= 3'd3; + end else if(unit2d_cnt_pooling_a4 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling_max; + pnum_flush4 <= 3'd0; + pnum_flush5 <= 3'd1; + pnum_flush6 <= 3'd2; + end else if(unit2d_cnt_pooling_a5 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling + 3'd4; + pnum_flush4 <= unit2d_cnt_pooling_max; + pnum_flush5 <= 3'd0; + pnum_flush6 <= 3'd1; + end else if(unit2d_cnt_pooling_a6 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling + 3'd4; + pnum_flush4 <= unit2d_cnt_pooling + 3'd5; + pnum_flush5 <= unit2d_cnt_pooling_max; + pnum_flush6 <= 3'd0; + end else if(unit2d_cnt_pooling_a7 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling + 3'd4; + pnum_flush4 <= unit2d_cnt_pooling + 3'd5; + pnum_flush5 <= unit2d_cnt_pooling + 3'd6; + pnum_flush6 <= unit2d_cnt_pooling_max; + end + end +end +//------------------------- +//update pooling No. in line2 of next surface +//------------------------- +assign up_pnum0 = 3'd0; +always @(posedge nvdla_core_clk) begin + if(padding_v_cfg[2:0] == 3'd0) begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if(padding_v_cfg[2:0] == 3'd1) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd2) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if(stride[4:0]==5'd2) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd3) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd3; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if((stride[4:0]==5'd2)|(stride[4:0]==5'd3)) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd4) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd3; + up_pnum4 <= 3'd4; + up_pnum5 <= 3'd0; + end else if(stride[4:0]==5'd2) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if((stride[4:0]==5'd3)|(stride[4:0]==5'd4)) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd5) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd3; + up_pnum4 <= 3'd4; + up_pnum5 <= 3'd5; + end else if(stride[4:0]==5'd2) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if((stride[4:0]==5'd3)|(stride[4:0]==5'd4)|(stride[4:0]==5'd5)) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end +end +/////////////////////////////////////////////////////////////////////// +//bubble control when next surface comming . Ending +/////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + subend_need_flush_flg <= 1'b0; + end else begin + if(wr_subcube_dat_done & need_flush & is_one_width_in) + subend_need_flush_flg <= 1'b1; + else if(one_width_bubble_end) + subend_need_flush_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surfend_need_bubble_flg <= 1'b0; + end else begin + if(wr_surface_dat_done & need_bubble & is_one_width_in) + surfend_need_bubble_flg <= 1'b1; + else if(one_width_bubble_end) + surfend_need_bubble_flg <= 1'b0; + end +end +///////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable <= 1'b0; + end else begin + if((wr_subcube_dat_done & need_flush & (~is_one_width_in)) | (subend_need_flush_flg & one_width_bubble_end)) + cur_datin_disable <= 1'b1; + else if((wr_surface_dat_done & need_bubble & (~is_one_width_in)) | (surfend_need_bubble_flg & one_width_bubble_end)) + cur_datin_disable <= 1'b1; + else if(bubble_en_end) + cur_datin_disable <= 1'b0; + end +end +///////////////////////////////////////// +//&Always posedge; +// if(wr_subcube_dat_done & need_flush) +// cur_datin_disable <0= 1'b1; +// else if(wr_surface_dat_done & need_bubble) +// cur_datin_disable <0= 1'b1; +// else if(bubble_en_end) +// cur_datin_disable <0= 1'b0; +//&End; +/////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_width_cur_latch <= {13{1'b0}}; + end else begin + if((wr_subcube_dat_done & need_flush) || (wr_surface_dat_done & need_bubble)) + pout_width_cur_latch <= pout_width_cur; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_cnt <= 0; + end else begin + if(cur_datin_disable) begin + if(last_c) + channel_cnt <= 0; + else if(one_width_norm_rdy) + channel_cnt <= channel_cnt + 1'b1; + end else + channel_cnt <= 0; + end +end +//: my $m = 8; +//: my $k = 1; +//: my $j = int($m / $k); +//: print "assign last_c = (channel_cnt==5'd${j}-1) & one_width_norm_rdy; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign last_c = (channel_cnt==5'd8-1) & one_width_norm_rdy; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_cnt <= {13{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(line_end) + line_cnt <= 13'd0; + else if(last_c) + line_cnt <= line_cnt + 1'b1; + end else + line_cnt <= 13'd0; + end +end +assign line_end = (line_cnt==pout_width_cur_latch) & last_c; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_cnt <= {3{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(bubble_en_end) + bubble_cnt <= 3'd0; + else if(line_end) + bubble_cnt <= bubble_cnt + 1'b1; + end else + bubble_cnt <= 3'd0; + end +end +assign bubble_en_end = (bubble_cnt == bubble_num_dec) & line_end; +assign bubble_num_dec[2:0] = (bubble_num_use-1'b1); +////////////////////////////////////////////////////// +//last lines output en during new lines comming +//---------------------------------------------------- +//cube end flag for last_out_en control in the cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_flag <= 1'b0; + end else begin + if(wr_subcube_dat_done) + cube_end_flag <= 1'b1; + else if(load_din) + cube_end_flag <= 1'b0; + end +end +//assign {mon_first_out_num_dec1[1:0],first_out_num_dec1[2:0]} = first_out_num - 4'd1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_en <= 1'b0; + end else begin + if(first_out_num != 3'd1) begin + if((need_bubble & bubble_en_end & (~cube_end_flag) & (bubble_add < flush_in_next_surf)) | (~need_bubble & need_flush & wr_surface_dat_done & (~wr_subcube_dat_done))) + last_out_en <= 1'b1; + else if(last_out_done) + last_out_en <= 1'b0; + end else + last_out_en <= 1'b0; + end +end +assign first_out_num_dec2[2:0] = flush_num - bubble_num_use - 1'b1;//first_out_num - 2'd2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_cnt <= {3{1'b0}}; + end else begin + if(last_out_en) begin + if(wr_line_dat_done) begin + if(((last_out_cnt == first_out_num_dec2) & need_bubble) | (~need_bubble & (last_out_cnt == flush_num_dec1))) + last_out_cnt <= 3'd0; + else + last_out_cnt <= last_out_cnt + 1'b1; + end + end else + last_out_cnt <= 3'd0; + end +end +assign {mon_flush_num_dec1,flush_num_dec1[2:0]} = flush_num - 3'd1; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP cal2d datin_disable: no overflow is allowed") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, mon_flush_num_dec1 & wr_line_dat_done & last_out_en); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign last_out_done = (((last_out_cnt == first_out_num_dec2) & need_bubble) | (~need_bubble & (last_out_cnt == flush_num_dec1))) & wr_line_dat_done & last_out_en; +/////////////////////////////////////////////////////////////////////// +//bubble control when input width is only 1 element in width +/////////////////////////////////////////////////////////////////////// +always @( + splitw_enable + or reg2dp_cube_out_width + or first_splitw + or reg2dp_partial_width_out_first + or last_splitw + or reg2dp_partial_width_out_last + or pooling_splitw_num_cfg + or reg2dp_partial_width_out_mid + ) begin + if(~splitw_enable) + is_one_width_in = (reg2dp_cube_out_width[12:0] == 13'd0); + else if(first_splitw) + is_one_width_in = (reg2dp_partial_width_out_first[9:0] == 10'd0); + else if(last_splitw) + is_one_width_in = (reg2dp_partial_width_out_last[9:0] == 10'd0); + else + is_one_width_in = (pooling_splitw_num_cfg > 8'd1)? (reg2dp_partial_width_out_mid[9:0] == 10'd0) : 1'b0; +end +///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable <= 1'b0; + end else begin + if(wr_line_dat_done & is_one_width_in) + one_width_disable <= 1'b1; + else if(one_width_bubble_end) + one_width_disable <= 1'b0; + end +end +///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_bubble_cnt <= {3{1'b0}}; + end else begin + if(one_width_disable) begin + if(one_width_bubble_end) + one_width_bubble_cnt <= 3'd0; + else if(pooling1d_norm_rdy) + one_width_bubble_cnt <= one_width_bubble_cnt + 1'b1; + end else + one_width_bubble_cnt <= 3'd0; + end +end +assign one_width_bubble_end = (one_width_bubble_cnt == (4 -2'd2)) & pooling1d_norm_rdy; +////////////////////////////////////////////////////// +assign pooling_2d_rdy = wr_line_dat_done & (strip_ycnt_psize ==pooling_size_v_cfg[2:0]) ; +//===================================================================== +//pooling 2D unit counter +// +//--------------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_stride[2:0] <= {3{1'b0}}; + end else begin + if(init_cnt) + unit2d_cnt_stride[2:0] <= padding_stride_num; + else if(stride_end) begin + if(stride_trig_end) + unit2d_cnt_stride[2:0] <= 3'd0; + else + unit2d_cnt_stride[2:0] <= unit2d_cnt_stride + 1; + end + end +end +assign stride_trig_end = (unit2d_cnt_pooling_max==unit2d_cnt_stride); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling <= {3{1'b0}}; + end else begin + if(init_cnt) + unit2d_cnt_pooling <= 3'd0; + else if(pooling_2d_rdy | wr_surface_dat_done) begin + if(unit2d_cnt_pooling_end) + unit2d_cnt_pooling <= 3'd0; + else + unit2d_cnt_pooling[2:0] <= unit2d_cnt_pooling + 1; + end + end +end +assign unit2d_cnt_pooling_end = (unit2d_cnt_pooling == unit2d_cnt_pooling_max); +assign {mon_unit2d_cnt_pooling_max[1:0],unit2d_cnt_pooling_max[2:0]} = buffer_lines_num - 4'd1; +//------------------------- +//flag the last one pooling in height direction +//------------------------- +assign {mon_rest_height,rest_height[12:0]} = reg2dp_cube_in_height - wr_surface_dat_cnt; +assign rest_height_use[13:0] = rest_height + {10'd0,reg2dp_pad_bottom_cfg}; +assign last_pooling_flag = rest_height_use[13:0] <= {11'd0,pooling_size_v_cfg}; +//====================================================================== +//unit2d pooling enable +//: foreach my $i (0..7) { +//: my $j=$i-1; +//: print "assign init_unit2d_set[$i] = init_cnt & (padding_stride_num>=${i}); \n"; +//: if($i == 0) { +//: print "assign unit2d_set_trig[${i}] = stride_end & stride_trig_end & (~last_pooling_flag);\n"; +//: } else { +//: print "assign unit2d_set_trig[${i}] = stride_end & (unit2d_cnt_stride == 3'd${j}) & (~stride_trig_end) & (~last_pooling_flag);\n"; +//: } +//: print qq( +//: assign unit2d_set[${i}] = unit2d_set_trig[${i}] | init_unit2d_set[${i}]; +//: assign unit2d_clr[${i}] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd${i})) | wr_surface_dat_done; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: unit2d_en[$i] <= 1'b0; +//: else if(wr_total_cube_done) +//: unit2d_en[$i] <= 1'b0; +//: else if(unit2d_set[${i}]) +//: unit2d_en[$i] <= 1'b1; +//: else if(unit2d_clr[${i}]) +//: unit2d_en[$i] <= 1'b0; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign init_unit2d_set[0] = init_cnt & (padding_stride_num>=0); +assign unit2d_set_trig[0] = stride_end & stride_trig_end & (~last_pooling_flag); + +assign unit2d_set[0] = unit2d_set_trig[0] | init_unit2d_set[0]; +assign unit2d_clr[0] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd0)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[0] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[0] <= 1'b0; +else if(unit2d_set[0]) +unit2d_en[0] <= 1'b1; +else if(unit2d_clr[0]) +unit2d_en[0] <= 1'b0; +end +assign init_unit2d_set[1] = init_cnt & (padding_stride_num>=1); +assign unit2d_set_trig[1] = stride_end & (unit2d_cnt_stride == 3'd0) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[1] = unit2d_set_trig[1] | init_unit2d_set[1]; +assign unit2d_clr[1] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd1)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[1] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[1] <= 1'b0; +else if(unit2d_set[1]) +unit2d_en[1] <= 1'b1; +else if(unit2d_clr[1]) +unit2d_en[1] <= 1'b0; +end +assign init_unit2d_set[2] = init_cnt & (padding_stride_num>=2); +assign unit2d_set_trig[2] = stride_end & (unit2d_cnt_stride == 3'd1) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[2] = unit2d_set_trig[2] | init_unit2d_set[2]; +assign unit2d_clr[2] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd2)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[2] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[2] <= 1'b0; +else if(unit2d_set[2]) +unit2d_en[2] <= 1'b1; +else if(unit2d_clr[2]) +unit2d_en[2] <= 1'b0; +end +assign init_unit2d_set[3] = init_cnt & (padding_stride_num>=3); +assign unit2d_set_trig[3] = stride_end & (unit2d_cnt_stride == 3'd2) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[3] = unit2d_set_trig[3] | init_unit2d_set[3]; +assign unit2d_clr[3] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd3)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[3] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[3] <= 1'b0; +else if(unit2d_set[3]) +unit2d_en[3] <= 1'b1; +else if(unit2d_clr[3]) +unit2d_en[3] <= 1'b0; +end +assign init_unit2d_set[4] = init_cnt & (padding_stride_num>=4); +assign unit2d_set_trig[4] = stride_end & (unit2d_cnt_stride == 3'd3) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[4] = unit2d_set_trig[4] | init_unit2d_set[4]; +assign unit2d_clr[4] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd4)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[4] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[4] <= 1'b0; +else if(unit2d_set[4]) +unit2d_en[4] <= 1'b1; +else if(unit2d_clr[4]) +unit2d_en[4] <= 1'b0; +end +assign init_unit2d_set[5] = init_cnt & (padding_stride_num>=5); +assign unit2d_set_trig[5] = stride_end & (unit2d_cnt_stride == 3'd4) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[5] = unit2d_set_trig[5] | init_unit2d_set[5]; +assign unit2d_clr[5] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd5)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[5] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[5] <= 1'b0; +else if(unit2d_set[5]) +unit2d_en[5] <= 1'b1; +else if(unit2d_clr[5]) +unit2d_en[5] <= 1'b0; +end +assign init_unit2d_set[6] = init_cnt & (padding_stride_num>=6); +assign unit2d_set_trig[6] = stride_end & (unit2d_cnt_stride == 3'd5) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[6] = unit2d_set_trig[6] | init_unit2d_set[6]; +assign unit2d_clr[6] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd6)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[6] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[6] <= 1'b0; +else if(unit2d_set[6]) +unit2d_en[6] <= 1'b1; +else if(unit2d_clr[6]) +unit2d_en[6] <= 1'b0; +end +assign init_unit2d_set[7] = init_cnt & (padding_stride_num>=7); +assign unit2d_set_trig[7] = stride_end & (unit2d_cnt_stride == 3'd6) & (~stride_trig_end) & (~last_pooling_flag); + +assign unit2d_set[7] = unit2d_set_trig[7] | init_unit2d_set[7]; +assign unit2d_clr[7] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd7)) | wr_surface_dat_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_en[7] <= 1'b0; +else if(wr_total_cube_done) +unit2d_en[7] <= 1'b0; +else if(unit2d_set[7]) +unit2d_en[7] <= 1'b1; +else if(unit2d_clr[7]) +unit2d_en[7] <= 1'b0; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +/////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_buf <= 0; + end else begin + if ((load_din) == 1'b1) begin + datin_buf <= pooling1d_pd_use; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_end_buf <= 1'b0; + end else begin + if ((load_din) == 1'b1) begin + wr_line_end_buf <= wr_line_dat_done; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_done_buf <= 1'b0; + end else begin + if ((load_din) == 1'b1) begin + wr_surface_dat_done_buf <= wr_surface_dat_done; + end + end +end +////////////////////////////////////////////////////////////////////// +//calculate the real pooling size within one poooling +//PerBeg +//: foreach my $i (0..7){ +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: unit2d_vsize_cnt_$i <= {3{1'b0}}; +//: else if(unit2d_set[$i]) +//: unit2d_vsize_cnt_${i}[2:0] <= 3'd0; +//: else if(unit2d_en[$i] & wr_line_dat_done) +//: unit2d_vsize_cnt_${i}[2:0] <= unit2d_vsize_cnt_${i}[2:0] + 3'd1; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_0 <= {3{1'b0}}; +else if(unit2d_set[0]) +unit2d_vsize_cnt_0[2:0] <= 3'd0; +else if(unit2d_en[0] & wr_line_dat_done) +unit2d_vsize_cnt_0[2:0] <= unit2d_vsize_cnt_0[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_1 <= {3{1'b0}}; +else if(unit2d_set[1]) +unit2d_vsize_cnt_1[2:0] <= 3'd0; +else if(unit2d_en[1] & wr_line_dat_done) +unit2d_vsize_cnt_1[2:0] <= unit2d_vsize_cnt_1[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_2 <= {3{1'b0}}; +else if(unit2d_set[2]) +unit2d_vsize_cnt_2[2:0] <= 3'd0; +else if(unit2d_en[2] & wr_line_dat_done) +unit2d_vsize_cnt_2[2:0] <= unit2d_vsize_cnt_2[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_3 <= {3{1'b0}}; +else if(unit2d_set[3]) +unit2d_vsize_cnt_3[2:0] <= 3'd0; +else if(unit2d_en[3] & wr_line_dat_done) +unit2d_vsize_cnt_3[2:0] <= unit2d_vsize_cnt_3[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_4 <= {3{1'b0}}; +else if(unit2d_set[4]) +unit2d_vsize_cnt_4[2:0] <= 3'd0; +else if(unit2d_en[4] & wr_line_dat_done) +unit2d_vsize_cnt_4[2:0] <= unit2d_vsize_cnt_4[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_5 <= {3{1'b0}}; +else if(unit2d_set[5]) +unit2d_vsize_cnt_5[2:0] <= 3'd0; +else if(unit2d_en[5] & wr_line_dat_done) +unit2d_vsize_cnt_5[2:0] <= unit2d_vsize_cnt_5[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_6 <= {3{1'b0}}; +else if(unit2d_set[6]) +unit2d_vsize_cnt_6[2:0] <= 3'd0; +else if(unit2d_en[6] & wr_line_dat_done) +unit2d_vsize_cnt_6[2:0] <= unit2d_vsize_cnt_6[2:0] + 3'd1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_7 <= {3{1'b0}}; +else if(unit2d_set[7]) +unit2d_vsize_cnt_7[2:0] <= 3'd0; +else if(unit2d_en[7] & wr_line_dat_done) +unit2d_vsize_cnt_7[2:0] <= unit2d_vsize_cnt_7[2:0] + 3'd1; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//line buffer number 1 +assign unit2d_vsize1_0 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_1 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_2 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_3 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_4 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_5 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_6 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_7 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +//line buffer number 2 +assign unit2d_vsize2_0 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_1 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_2 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_3 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_4 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize2_5 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize2_6 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize2_7 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +//line buffer number 3 4 +assign unit2d_vsize3_0 = mem_re3_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize3_1 = mem_re3_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize3_2 = mem_re3_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize3_3 = mem_re3_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize3_4 = mem_re3_sel? unit2d_vsize_cnt_2 : 3'd0; +assign unit2d_vsize3_5 = mem_re3_sel? unit2d_vsize_cnt_2 : 3'd0; +assign unit2d_vsize3_6 = mem_re3_sel? unit2d_vsize_cnt_3 : 3'd0; +assign unit2d_vsize3_7 = mem_re3_sel? unit2d_vsize_cnt_3 : 3'd0; +//line buffer 5 6 7 8 +assign unit2d_vsize4_0 = mem_re4_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize4_1 = mem_re4_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize4_2 = mem_re4_sel? unit2d_vsize_cnt_2 : 3'd0; +assign unit2d_vsize4_3 = mem_re4_sel? unit2d_vsize_cnt_3 : 3'd0; +assign unit2d_vsize4_4 = mem_re4_sel? unit2d_vsize_cnt_4 : 3'd0; +assign unit2d_vsize4_5 = mem_re4_sel? unit2d_vsize_cnt_5 : 3'd0; +assign unit2d_vsize4_6 = mem_re4_sel? unit2d_vsize_cnt_6 : 3'd0; +assign unit2d_vsize4_7 = mem_re4_sel? unit2d_vsize_cnt_7 : 3'd0; +assign unit2d_vsize_0 = unit2d_vsize1_0 | unit2d_vsize2_0 | unit2d_vsize3_0 | unit2d_vsize4_0; +assign unit2d_vsize_1 = unit2d_vsize1_1 | unit2d_vsize2_1 | unit2d_vsize3_1 | unit2d_vsize4_1; +assign unit2d_vsize_2 = unit2d_vsize1_2 | unit2d_vsize2_2 | unit2d_vsize3_2 | unit2d_vsize4_2; +assign unit2d_vsize_3 = unit2d_vsize1_3 | unit2d_vsize2_3 | unit2d_vsize3_3 | unit2d_vsize4_3; +assign unit2d_vsize_4 = unit2d_vsize1_4 | unit2d_vsize2_4 | unit2d_vsize3_4 | unit2d_vsize4_4; +assign unit2d_vsize_5 = unit2d_vsize1_5 | unit2d_vsize2_5 | unit2d_vsize3_5 | unit2d_vsize4_5; +assign unit2d_vsize_6 = unit2d_vsize1_6 | unit2d_vsize2_6 | unit2d_vsize3_6 | unit2d_vsize4_6; +assign unit2d_vsize_7 = unit2d_vsize1_7 | unit2d_vsize2_7 | unit2d_vsize3_7 | unit2d_vsize4_7; +//: foreach my $i (0..7) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: unit2d_vsize_cnt_${i}_d <= {3{1'b0}}; +//: else if (load_din) +//: unit2d_vsize_cnt_${i}_d <= unit2d_vsize_$i; +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_0_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_0_d <= unit2d_vsize_0; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_1_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_1_d <= unit2d_vsize_1; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_2_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_2_d <= unit2d_vsize_2; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_3_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_3_d <= unit2d_vsize_3; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_4_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_4_d <= unit2d_vsize_4; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_5_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_5_d <= unit2d_vsize_5; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_6_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_6_d <= unit2d_vsize_6; +end + +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +if (!nvdla_core_rstn) +unit2d_vsize_cnt_7_d <= {3{1'b0}}; +else if (load_din) +unit2d_vsize_cnt_7_d <= unit2d_vsize_7; +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============================================================ +assign active_last_line = (strip_ycnt_psize == pooling_size_v_cfg) | last_line_in; +//============================================================ +//memory bank read/write controller +// +//------------------------------------------------------------ +//memory read +//mem bank0 enable +// +//memory first read +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[0] <= 1'b0; + end else begin + unit2d_mem_1strd[0] <= unit2d_set[0] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[0]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[1] <= 1'b0; + end else begin + unit2d_mem_1strd[1] <= unit2d_set[1] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[1]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[2] <= 1'b0; + end else begin + unit2d_mem_1strd[2] <= unit2d_set[2] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[2]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[3] <= 1'b0; + end else begin + unit2d_mem_1strd[3] <= unit2d_set[3] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[3]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[4] <= 1'b0; + end else begin + unit2d_mem_1strd[4] <= unit2d_set[4] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[4]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[5] <= 1'b0; + end else begin + unit2d_mem_1strd[5] <= unit2d_set[5] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[5]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[6] <= 1'b0; + end else begin + unit2d_mem_1strd[6] <= unit2d_set[6] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[6]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[7] <= 1'b0; + end else begin + unit2d_mem_1strd[7] <= unit2d_set[7] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[7]); + end +end +//line buffer number 1 +assign mem_re1[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re1_sel; +assign mem_re1[1] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re1_sel; +assign mem_re1[2] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd2) & mem_re1_sel; +assign mem_re1[3] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd3) & mem_re1_sel; +assign mem_re1[4] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd4) & mem_re1_sel; +assign mem_re1[5] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd5) & mem_re1_sel; +assign mem_re1[6] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd6) & mem_re1_sel; +assign mem_re1[7] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd7) & mem_re1_sel; +assign mem_re1_1st[0] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[1] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[2] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[3] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[4] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[5] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[6] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[7] = unit2d_mem_1strd[0] & mem_re1_sel; +//line buffer number 2 +//4 bank read enable +//mem_read +assign mem_re2[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel; +assign mem_re2[1] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel; +assign mem_re2[2] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel; +assign mem_re2[3] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel; +assign mem_re2[4] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel; +assign mem_re2[5] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel; +assign mem_re2[6] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel; +assign mem_re2[7] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel; +assign mem_re2_1st[0] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[1] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[2] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[3] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[4] = unit2d_mem_1strd[1] & mem_re2_sel; +assign mem_re2_1st[5] = unit2d_mem_1strd[1] & mem_re2_sel; +assign mem_re2_1st[6] = unit2d_mem_1strd[1] & mem_re2_sel; +assign mem_re2_1st[7] = unit2d_mem_1strd[1] & mem_re2_sel; +//line buffer number 3 4 +assign mem_re3[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[1] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3[2] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[3] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3[4] = unit2d_en[2] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[5] = unit2d_en[2] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3[6] = unit2d_en[3] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[7] = unit2d_en[3] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3_1st[0] = unit2d_mem_1strd[0] & mem_re3_sel; +assign mem_re3_1st[1] = unit2d_mem_1strd[0] & mem_re3_sel; +assign mem_re3_1st[2] = unit2d_mem_1strd[1] & mem_re3_sel; +assign mem_re3_1st[3] = unit2d_mem_1strd[1] & mem_re3_sel; +assign mem_re3_1st[4] = unit2d_mem_1strd[2] & mem_re3_sel; +assign mem_re3_1st[5] = unit2d_mem_1strd[2] & mem_re3_sel; +assign mem_re3_1st[6] = unit2d_mem_1strd[3] & mem_re3_sel; +assign mem_re3_1st[7] = unit2d_mem_1strd[3] & mem_re3_sel; +//line buffer 5 6 7 8 +assign mem_re4[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[1] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[2] = unit2d_en[2] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[3] = unit2d_en[3] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[4] = unit2d_en[4] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[5] = unit2d_en[5] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[6] = unit2d_en[6] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[7] = unit2d_en[7] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4_1st[0] = unit2d_mem_1strd[0] & mem_re4_sel; +assign mem_re4_1st[1] = unit2d_mem_1strd[1] & mem_re4_sel; +assign mem_re4_1st[2] = unit2d_mem_1strd[2] & mem_re4_sel; +assign mem_re4_1st[3] = unit2d_mem_1strd[3] & mem_re4_sel; +assign mem_re4_1st[4] = unit2d_mem_1strd[4] & mem_re4_sel; +assign mem_re4_1st[5] = unit2d_mem_1strd[5] & mem_re4_sel; +assign mem_re4_1st[6] = unit2d_mem_1strd[6] & mem_re4_sel; +assign mem_re4_1st[7] = unit2d_mem_1strd[7] & mem_re4_sel; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re1_sel <= 1'b0; + mem_re2_sel <= 1'b0; + mem_re3_sel <= 1'b0; + mem_re4_sel <= 1'b0; + end else begin + mem_re1_sel <= (buffer_lines_num==4'd1); + mem_re2_sel <= (buffer_lines_num==4'd2); + mem_re3_sel <= (buffer_lines_num==4'd3) | (buffer_lines_num==4'd4); + mem_re4_sel <= (buffer_lines_num >=4'd5); + end +end +/////////////////////////// +//shouldn't read data from mem for the first pooling line +/////////////////////////// +assign mem_re = mem_re1 | mem_re2 | mem_re3 | mem_re4; +assign mem_re_1st = mem_re1_1st | mem_re2_1st | mem_re3_1st | mem_re4_1st; +assign mem_raddr = sub_lbuf_dout_cnt; +//line buffer counter +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_sub_lbuf_cnt[2:0] <= {3{1'b0}}; + end else begin + if(wr_line_dat_done | last_sub_lbuf_done | line_end) + wr_sub_lbuf_cnt[2:0] <= 3'd0; + else if(sub_lbuf_dout_done) + wr_sub_lbuf_cnt[2:0] <= wr_sub_lbuf_cnt + 1; + end +end +assign last_sub_lbuf_done = ((bank_merge_num-1) =={2'd0,wr_sub_lbuf_cnt}) & sub_lbuf_dout_done; +//-------------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_lbuf_dout_cnt <= {9{1'b0}}; + end else begin + if(sub_lbuf_dout_done | wr_line_dat_done | line_end) + sub_lbuf_dout_cnt <= 9'd0; + else if(load_din | (cur_datin_disable & one_width_norm_rdy)) + sub_lbuf_dout_cnt <= sub_lbuf_dout_cnt+ 1'd1; + end +end +assign sub_lbuf_dout_done = (sub_lbuf_dout_cnt==BANK_DEPTH) & (load_din | (cur_datin_disable & one_width_norm_rdy)); +//============================================================================================== +//buffer the data from memory and from UNIT1D +// +//---------------------------------------------------------------------------------------------- +//========================================================= +//POOLING FUNCTION DEFINITION +// +//---- ----------------------------------------------------- +//: my $m = (8 +6); +//: print qq( +//: function[${m}-1:0] pooling_MIN; +//: input data0_valid; +//: input[${m}-1:0] data0; +//: input[${m}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function[14-1:0] pooling_MIN; +input data0_valid; +input[14-1:0] data0; +input[14-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + reg min_int_ff; + begin + min_int_ff = ($signed(data1)> $signed(data0)) ; + pooling_MIN = (min_int_ff & data0_valid) ? data0 : data1; + end + endfunction +//: my $m = (8 +6); +//: print qq( +//: function[${m}-1:0] pooling_MAX; +//: input data0_valid; +//: input[${m}-1:0] data0; +//: input[${m}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function[14-1:0] pooling_MAX; +input data0_valid; +input[14-1:0] data0; +input[14-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + reg max_int_ff; + begin + max_int_ff = ($signed(data0)> $signed(data1)) ; + pooling_MAX = (max_int_ff & data0_valid) ? data0 : data1; + end + endfunction +//: my $m = (8 +6); +//: print qq( +//: function[${m}-1:0] pooling_SUM; +//: input data0_valid; +//: input[${m}-1:0] data0; +//: input[${m}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function[14-1:0] pooling_SUM; +input data0_valid; +input[14-1:0] data0; +input[14-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + begin +//spyglass disable_block W484 + pooling_SUM = ($signed(data1) + $signed(data0)) ; +//spyglass enable_block W484 + end + endfunction +//pooling result +//: my $m = 1*(8 +6); +//: print qq( +//: function[${m}-1:0] pooling_fun; +//: input[1:0] pooling_type; +//: input data0_valid; +//: input[${m}-1:0] data0_in; +//: input[${m}-1:0] data1_in; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function[14-1:0] pooling_fun; +input[1:0] pooling_type; +input data0_valid; +input[14-1:0] data0_in; +input[14-1:0] data1_in; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + reg min_pooling; + reg max_pooling; + reg mean_pooling; + begin + min_pooling = (pooling_type== 2'h2 ); + max_pooling = (pooling_type== 2'h1 ); + mean_pooling = (pooling_type== 2'h0 ); +//: my $k = 1; +//: my $m = (8 +6); +//: foreach my $i (0..$k-1) { +//: print qq( +//: pooling_fun[${m}*${i}+${m}-1:${m}*${i}] = mean_pooling? pooling_SUM(data0_valid,data0_in[${m}*${i}+${m}-1:${m}*${i}],data1_in[${m}*${i}+${m}-1:${m}*${i}]) : +//: min_pooling ? (pooling_MIN(data0_valid,data0_in[${m}*${i}+${m}-1:${m}*${i}],data1_in[${m}*${i}+${m}-1:${m}*${i}])) : +//: max_pooling ? (pooling_MAX(data0_valid,data0_in[${m}*${i}+${m}-1:${m}*${i}],data1_in[${m}*${i}+${m}-1:${m}*${i}])) : 0; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +pooling_fun[14*0+14-1:14*0] = mean_pooling? pooling_SUM(data0_valid,data0_in[14*0+14-1:14*0],data1_in[14*0+14-1:14*0]) : +min_pooling ? (pooling_MIN(data0_valid,data0_in[14*0+14-1:14*0],data1_in[14*0+14-1:14*0])) : +max_pooling ? (pooling_MAX(data0_valid,data0_in[14*0+14-1:14*0],data1_in[14*0+14-1:14*0])) : 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +endfunction +//write memory +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_data0_lst <= 0; + mem_data1_lst <= 0; + mem_data2_lst <= 0; + mem_data3_lst <= 0; + mem_data4_lst <= 0; + mem_data5_lst <= 0; + mem_data6_lst <= 0; + mem_data7_lst <= 0; + end else begin + if(flush_read_en_d & wr_data_stage0_prdy) begin + mem_data0_lst <= {mem_rdata_0[1*(8 +6)+2:0]}; + mem_data1_lst <= {mem_rdata_1[1*(8 +6)+2:0]}; + mem_data2_lst <= {mem_rdata_2[1*(8 +6)+2:0]}; + mem_data3_lst <= {mem_rdata_3[1*(8 +6)+2:0]}; + mem_data4_lst <= {mem_rdata_4[1*(8 +6)+2:0]}; + mem_data5_lst <= {mem_rdata_5[1*(8 +6)+2:0]}; + mem_data6_lst <= {mem_rdata_6[1*(8 +6)+2:0]}; + mem_data7_lst <= {mem_rdata_7[1*(8 +6)+2:0]}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_data0 <= 0; + mem_data1 <= 0; + mem_data2 <= 0; + mem_data3 <= 0; + mem_data4 <= 0; + mem_data5 <= 0; + mem_data6 <= 0; + mem_data7 <= 0; + end else begin + if(load_wr_stage1) begin//one cycle delay than pooling1d input + mem_data0 <= mem_re_1st_d[0]? {unit2d_vsize_cnt_0_d, datin_buf}: { unit2d_vsize_cnt_0_d,mem_rdata_0[1*(8 +6)-1:0]}; + mem_data1 <= mem_re_1st_d[1]? {unit2d_vsize_cnt_1_d, datin_buf}: { unit2d_vsize_cnt_1_d,mem_rdata_1[1*(8 +6)-1:0]}; + mem_data2 <= mem_re_1st_d[2]? {unit2d_vsize_cnt_2_d, datin_buf}: { unit2d_vsize_cnt_2_d,mem_rdata_2[1*(8 +6)-1:0]}; + mem_data3 <= mem_re_1st_d[3]? {unit2d_vsize_cnt_3_d, datin_buf}: { unit2d_vsize_cnt_3_d,mem_rdata_3[1*(8 +6)-1:0]}; + mem_data4 <= mem_re_1st_d[4]? {unit2d_vsize_cnt_4_d, datin_buf}: { unit2d_vsize_cnt_4_d,mem_rdata_4[1*(8 +6)-1:0]}; + mem_data5 <= mem_re_1st_d[5]? {unit2d_vsize_cnt_5_d, datin_buf}: { unit2d_vsize_cnt_5_d,mem_rdata_5[1*(8 +6)-1:0]}; + mem_data6 <= mem_re_1st_d[6]? {unit2d_vsize_cnt_6_d, datin_buf}: { unit2d_vsize_cnt_6_d,mem_rdata_6[1*(8 +6)-1:0]}; + mem_data7 <= mem_re_1st_d[7]? {unit2d_vsize_cnt_7_d, datin_buf}: { unit2d_vsize_cnt_7_d,mem_rdata_7[1*(8 +6)-1:0]}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_buf_2d <= 0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + datin_buf_2d <= datin_buf; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + datin_buf_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_end_2d <= 1'b0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + wr_line_end_2d <= wr_line_end_buf; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + wr_line_end_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_raddr_2d <= {9{1'b0}}; + end else begin + if ((load_wr_stage1) == 1'b1) begin + mem_raddr_2d <= mem_raddr_d; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_done_2d <= 1'b0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + wr_surface_dat_done_2d <= wr_surface_dat_done_buf; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + wr_surface_dat_done_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_active_line_d <= 1'b0; + end else begin + if ((load_din) == 1'b1) begin + last_active_line_d <= active_last_line; +// VCS coverage off + end else if ((load_din) == 1'b0) begin + end else begin + last_active_line_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_active_line_2d <= 1'b0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + last_active_line_2d <= last_active_line_d; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + last_active_line_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_1st_d <= {8{1'b0}}; + end else begin + if ((load_din) == 1'b1) begin + mem_re_1st_d <= mem_re_1st; +// VCS coverage off + end else if ((load_din) == 1'b0) begin + end else begin + mem_re_1st_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_1st_2d <= {8{1'b0}}; + end else begin + if ((load_wr_stage1) == 1'b1) begin + mem_re_1st_2d <= mem_re_1st_d; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + mem_re_1st_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_raddr_d <= {9{1'b0}}; + end else begin + if (((|mem_re) | (flush_read_en & one_width_norm_rdy)) == 1'b1) begin + mem_raddr_d <= mem_raddr; + end + end +end +//=========================== +//8bits mem_re two cycle delay +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_d <= {8{1'b0}}; + end else begin + if ((load_din) == 1'b1) begin + mem_re_d <= mem_re; +// VCS coverage off + end else if ((load_din) == 1'b0) begin + end else begin + mem_re_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_2d <= {8{1'b0}}; + end else begin + if ((load_wr_stage1) == 1'b1) begin + mem_re_2d <= mem_re_d; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + mem_re_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//write stage0 +assign pooling1d_norm_rdy = ~wr_data_stage0_vld | wr_data_stage0_prdy; +//rebuild valid signal with cur_datin_disable control +//assign pooling1d_vld_rebuild = cur_datin_disable ? 1'b1 : pooling1d_pvld_use; +assign pooling1d_vld_rebuild = (one_width_disable | cur_datin_disable) ? 1'b1 : pooling1d_pvld_use; +assign load_din_all = pooling1d_norm_rdy & pooling1d_vld_rebuild; +//pipe delay +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_stage0_vld <= 1'b0; + end else begin +//if(|mem_re) + if(pooling1d_vld_rebuild) + wr_data_stage0_vld <= 1'b1; + else if(wr_data_stage0_prdy) + wr_data_stage0_vld <= 1'b0; + end +end +assign wr_data_stage0_prdy = ~wr_data_stage1_vld | wr_data_stage1_prdy; +//write stage1 +assign load_wr_stage1_all = wr_data_stage0_vld & wr_data_stage0_prdy; +//assign load_wr_stage1 = wr_data_stage0_vld & wr_data_stage0_prdy & (~cur_datin_disable_d); +assign load_wr_stage1 = wr_data_stage0_vld & wr_data_stage0_prdy & (~cur_datin_disable_d) & (~one_width_disable_d); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_stage1_vld <= 1'b0; + end else begin + if(wr_data_stage0_vld) + wr_data_stage1_vld <= 1'b1; + else if(wr_data_stage1_prdy) + wr_data_stage1_vld <= 1'b0; + end +end +//write stage2 +assign load_wr_stage2_all = wr_data_stage1_vld & wr_data_stage1_prdy; +assign load_wr_stage2 = wr_data_stage1_vld & wr_data_stage1_prdy & (~cur_datin_disable_2d) & (~one_width_disable_2d); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_stage2_vld <= 1'b0; + end else begin +//if(wr_data_stage1_vld) + if(wr_data_stage1_vld ) + wr_data_stage2_vld <= 1'b1; + else if(pout_data_stage0_prdy) + wr_data_stage2_vld <= 1'b0; + end +end +assign load_wr_stage3_all = wr_data_stage2_vld & pout_data_stage0_prdy; +assign load_wr_stage3 = wr_data_stage2_vld & pout_data_stage0_prdy & (~cur_datin_disable_3d) & (~one_width_disable_3d); +//==================================================================== +// pooling data calculation and write back +// +//-------------------------------------------------------------------- +assign pooling_datin = datin_buf_2d; +//read from memory +assign mem_data_valid = load_wr_stage2 ? mem_re_2d : 8'h00; +assign pooling_2d_result_0 = mem_re_1st_2d[0] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[0],pooling_datin,mem_data0[1*(8 +6)-1:0]); +assign pooling_2d_result_1 = mem_re_1st_2d[1] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[1],pooling_datin,mem_data1[1*(8 +6)-1:0]); +assign pooling_2d_result_2 = mem_re_1st_2d[2] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[2],pooling_datin,mem_data2[1*(8 +6)-1:0]); +assign pooling_2d_result_3 = mem_re_1st_2d[3] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[3],pooling_datin,mem_data3[1*(8 +6)-1:0]); +assign pooling_2d_result_4 = mem_re_1st_2d[4] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[4],pooling_datin,mem_data4[1*(8 +6)-1:0]); +assign pooling_2d_result_5 = mem_re_1st_2d[5] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[5],pooling_datin,mem_data5[1*(8 +6)-1:0]); +assign pooling_2d_result_6 = mem_re_1st_2d[6] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[6],pooling_datin,mem_data6[1*(8 +6)-1:0]); +assign pooling_2d_result_7 = mem_re_1st_2d[7] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[7],pooling_datin,mem_data7[1*(8 +6)-1:0]); +assign pooling_2d_info_0 = {wr_line_end_2d,mem_data0[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_1 = {wr_line_end_2d,mem_data1[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_2 = {wr_line_end_2d,mem_data2[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_3 = {wr_line_end_2d,mem_data3[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_4 = {wr_line_end_2d,mem_data4[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_5 = {wr_line_end_2d,mem_data5[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_6 = {wr_line_end_2d,mem_data6[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_7 = {wr_line_end_2d,mem_data7[1*(8 +6)+2:1*(8 +6)]}; +//memory write data +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1*(8 +6)+4; +//: foreach my $i (0..7){ +//: print " int_mem_wdata_$i <= ${k}'d0; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + int_mem_wdata_0 <= 18'd0; + int_mem_wdata_1 <= 18'd0; + int_mem_wdata_2 <= 18'd0; + int_mem_wdata_3 <= 18'd0; + int_mem_wdata_4 <= 18'd0; + int_mem_wdata_5 <= 18'd0; + int_mem_wdata_6 <= 18'd0; + int_mem_wdata_7 <= 18'd0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if(load_wr_stage2) begin +//: my $k = 1*(8 +6)+4; +//: foreach my $i (0..7){ +//: print " int_mem_wdata_$i <= {pooling_2d_info_${i},pooling_2d_result_$i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + int_mem_wdata_0 <= {pooling_2d_info_0,pooling_2d_result_0}; + int_mem_wdata_1 <= {pooling_2d_info_1,pooling_2d_result_1}; + int_mem_wdata_2 <= {pooling_2d_info_2,pooling_2d_result_2}; + int_mem_wdata_3 <= {pooling_2d_info_3,pooling_2d_result_3}; + int_mem_wdata_4 <= {pooling_2d_info_4,pooling_2d_result_4}; + int_mem_wdata_5 <= {pooling_2d_info_5,pooling_2d_result_5}; + int_mem_wdata_6 <= {pooling_2d_info_6,pooling_2d_result_6}; + int_mem_wdata_7 <= {pooling_2d_info_7,pooling_2d_result_7}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +//write enabel signal +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_mem_we <= {8{1'b0}}; + end else begin + if ((load_wr_stage2) == 1'b1) begin + int_mem_we <= mem_re_2d; +// VCS coverage off + end else if ((load_wr_stage2) == 1'b0) begin + end else begin + int_mem_we <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage2))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_mem_waddr <= {9{1'b0}}; + end else begin + if ((load_wr_stage2) == 1'b1) begin + int_mem_waddr <= mem_raddr_2d; + end + end +end +//memory write select +assign mem_wdata_0 = int_mem_wdata_0; +assign mem_wdata_1 = int_mem_wdata_1; +assign mem_wdata_2 = int_mem_wdata_2; +assign mem_wdata_3 = int_mem_wdata_3; +assign mem_wdata_4 = int_mem_wdata_4; +assign mem_wdata_5 = int_mem_wdata_5; +assign mem_wdata_6 = int_mem_wdata_6; +assign mem_wdata_7 = int_mem_wdata_7; +assign mem_we = (int_mem_we & {8{load_wr_stage3}}); +assign mem_waddr_0 = int_mem_waddr; +assign mem_waddr_1 = int_mem_waddr; +assign mem_waddr_2 = int_mem_waddr; +assign mem_waddr_3 = int_mem_waddr; +assign mem_waddr_4 = int_mem_waddr; +assign mem_waddr_5 = int_mem_waddr; +assign mem_waddr_6 = int_mem_waddr; +assign mem_waddr_7 = int_mem_waddr; +//============================================================================= +//memory line buffer instance +// +//----------------------------------------------------------------------------- +//: my $depth = int(16*(8/1)); +//: my $depth_bw = int( log($depth)/log(2) ); +//: my $width = (1*(8 +6)+4); +//: foreach my $i (0..7) { +//: print qq( +//: nv_ram_rws_${depth}x${width} bank${i}_uram_0 ( +//: .clk (nvdla_core_clk) +//: ,.ra (mem_raddr[${depth_bw}-1:0]) +//: ,.re (mem_re[$i] | mem_re_last[$i]) +//: ,.dout (mem_rdata_$i) +//: ,.wa (mem_waddr_${i}[${depth_bw}-1:0]) +//: ,.we (mem_we[$i]) +//: ,.di (mem_wdata_$i) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd) +//: ); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +nv_ram_rws_128x18 bank0_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[0] | mem_re_last[0]) +,.dout (mem_rdata_0) +,.wa (mem_waddr_0[7-1:0]) +,.we (mem_we[0]) +,.di (mem_wdata_0) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank1_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[1] | mem_re_last[1]) +,.dout (mem_rdata_1) +,.wa (mem_waddr_1[7-1:0]) +,.we (mem_we[1]) +,.di (mem_wdata_1) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank2_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[2] | mem_re_last[2]) +,.dout (mem_rdata_2) +,.wa (mem_waddr_2[7-1:0]) +,.we (mem_we[2]) +,.di (mem_wdata_2) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank3_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[3] | mem_re_last[3]) +,.dout (mem_rdata_3) +,.wa (mem_waddr_3[7-1:0]) +,.we (mem_we[3]) +,.di (mem_wdata_3) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank4_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[4] | mem_re_last[4]) +,.dout (mem_rdata_4) +,.wa (mem_waddr_4[7-1:0]) +,.we (mem_we[4]) +,.di (mem_wdata_4) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank5_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[5] | mem_re_last[5]) +,.dout (mem_rdata_5) +,.wa (mem_waddr_5[7-1:0]) +,.we (mem_we[5]) +,.di (mem_wdata_5) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank6_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[6] | mem_re_last[6]) +,.dout (mem_rdata_6) +,.wa (mem_waddr_6[7-1:0]) +,.we (mem_we[6]) +,.di (mem_wdata_6) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +nv_ram_rws_128x18 bank7_uram_0 ( +.clk (nvdla_core_clk) +,.ra (mem_raddr[7-1:0]) +,.re (mem_re[7] | mem_re_last[7]) +,.dout (mem_rdata_7) +,.wa (mem_waddr_7[7-1:0]) +,.we (mem_we[7]) +,.di (mem_wdata_7) +,.pwrbus_ram_pd (pwrbus_ram_pd) +); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram0 read and write same addr simultaneously") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, (mem_we[0] & ( mem_re[0] | mem_re_last[0])) & (mem_raddr == mem_waddr_0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram1 read and write same addr simultaneously") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (mem_we[1] & ( mem_re[1] | mem_re_last[1])) & (mem_raddr == mem_waddr_1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram2 read and write same addr simultaneously") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (mem_we[2] & ( mem_re[2] | mem_re_last[2])) & (mem_raddr == mem_waddr_2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram3 read and write same addr simultaneously") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (mem_we[3] & ( mem_re[3] | mem_re_last[3])) & (mem_raddr == mem_waddr_3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram4 read and write same addr simultaneously") zzz_assert_never_35x (nvdla_core_clk, `ASSERT_RESET, (mem_we[4] & ( mem_re[4] | mem_re_last[4])) & (mem_raddr == mem_waddr_4)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram5 read and write same addr simultaneously") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (mem_we[5] & ( mem_re[5] | mem_re_last[5])) & (mem_raddr == mem_waddr_5)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram6 read and write same addr simultaneously") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (mem_we[6] & ( mem_re[6] | mem_re_last[6])) & (mem_raddr == mem_waddr_6)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram7 read and write same addr simultaneously") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (mem_we[7] & ( mem_re[7] | mem_re_last[7])) & (mem_raddr == mem_waddr_7)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============================================================================== +//data reading control during datin_disable time +// +///////////////////////////////////////////////////////////////////////////////////////////////////// +//data reading from buffer for datin_disable bubble part and last_out during the next surface coming +//cur_datin_disable means bubble part, need disable input data prdy +//in the end of total layer, if have data need flushed, will also bubble input +//last_out_en flush the last lines during the next surface data coming +///////////////////////////////////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling_last <= {3{1'b0}}; + mem_re2_sel_last <= 1'b0; + mem_re3_sel_last <= 1'b0; + mem_re4_sel_last <= 1'b0; + end else begin + if(wr_surface_dat_done) begin + unit2d_cnt_pooling_last <= (unit2d_cnt_pooling == unit2d_cnt_pooling_max) ? 3'd0 : (unit2d_cnt_pooling + 1'b1); + mem_re2_sel_last <= mem_re2_sel; + mem_re3_sel_last <= mem_re3_sel; + mem_re4_sel_last <= mem_re4_sel; + end else if(((line_end & cur_datin_disable) | (wr_line_dat_done & last_out_en)) & one_width_norm_rdy) begin + if(unit2d_cnt_pooling_last_end) + unit2d_cnt_pooling_last <= 3'd0; + else + unit2d_cnt_pooling_last <= unit2d_cnt_pooling_last + 1'b1; + end + end +end +assign unit2d_cnt_pooling_last_end = (unit2d_cnt_pooling_last == unit2d_cnt_pooling_max); +assign flush_read_en = (cur_datin_disable | last_out_en) & one_width_norm_rdy; +assign unit2d_en_last[0] = flush_read_en & (unit2d_cnt_pooling_last == 3'd0); +assign unit2d_en_last[1] = flush_read_en & (unit2d_cnt_pooling_last == 3'd1); +assign unit2d_en_last[2] = flush_read_en & (unit2d_cnt_pooling_last == 3'd2); +assign unit2d_en_last[3] = flush_read_en & (unit2d_cnt_pooling_last == 3'd3); +assign unit2d_en_last[4] = flush_read_en & (unit2d_cnt_pooling_last == 3'd4); +assign unit2d_en_last[5] = flush_read_en & (unit2d_cnt_pooling_last == 3'd5); +assign unit2d_en_last[6] = flush_read_en & (unit2d_cnt_pooling_last == 3'd6); +assign unit2d_en_last[7] = flush_read_en & (unit2d_cnt_pooling_last == 3'd7); +assign mem_re2_last[0] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel_last; +assign mem_re2_last[1] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel_last; +assign mem_re2_last[2] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel_last; +assign mem_re2_last[3] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel_last; +assign mem_re2_last[4] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel_last; +assign mem_re2_last[5] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel_last; +assign mem_re2_last[6] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel_last; +assign mem_re2_last[7] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel_last; +assign mem_re3_last[0] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[1] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re3_last[2] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[3] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re3_last[4] = unit2d_en_last[2] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[5] = unit2d_en_last[2] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re3_last[6] = unit2d_en_last[3] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[7] = unit2d_en_last[3] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re4_last[0] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[1] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[2] = unit2d_en_last[2] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[3] = unit2d_en_last[3] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[4] = unit2d_en_last[4] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[5] = unit2d_en_last[5] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[6] = unit2d_en_last[6] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[7] = unit2d_en_last[7] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re_last = mem_re2_last | mem_re3_last | mem_re4_last; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + flush_read_en_d <= 1'b0; + end else begin + if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b1) begin + flush_read_en_d <= flush_read_en; +// VCS coverage off + end else if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b0) begin + end else begin + flush_read_en_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy )))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_last_d <= {8{1'b0}}; + end else begin + if (((load_din ) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b1) begin + mem_re_last_d <= mem_re_last; +// VCS coverage off + end else if (((load_din ) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b0) begin + end else begin + mem_re_last_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_din ) | (cur_datin_disable & one_width_norm_rdy )))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling_last_d <= {3{1'b0}}; + end else begin + if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b1) begin + unit2d_cnt_pooling_last_d <= unit2d_cnt_pooling_last; +// VCS coverage off + end else if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b0) begin + end else begin + unit2d_cnt_pooling_last_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy )))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable_d <= 1'b0; + end else begin + if ((load_din_all) == 1'b1) begin + cur_datin_disable_d <= cur_datin_disable; +// VCS coverage off + end else if ((load_din_all) == 1'b0) begin + end else begin + cur_datin_disable_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable_d <= 1'b0; + end else begin + if ((load_din_all) == 1'b1) begin + one_width_disable_d <= one_width_disable; +// VCS coverage off + end else if ((load_din_all) == 1'b0) begin + end else begin + one_width_disable_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_last_2d <= {8{1'b0}}; + end else begin + if (( load_wr_stage1 | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b1) begin + mem_re_last_2d <= mem_re_last_d; +// VCS coverage off + end else if (( load_wr_stage1 | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b0) begin + end else begin + mem_re_last_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^( load_wr_stage1 | (cur_datin_disable_d & wr_data_stage0_prdy)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling_last_2d <= {3{1'b0}}; + end else begin + if (((load_wr_stage1 & (|mem_re_last_d)) | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b1) begin + unit2d_cnt_pooling_last_2d <= unit2d_cnt_pooling_last_d; +// VCS coverage off + end else if (((load_wr_stage1 & (|mem_re_last_d)) | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b0) begin + end else begin + unit2d_cnt_pooling_last_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_45x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_wr_stage1 & (|mem_re_last_d)) | (cur_datin_disable_d & wr_data_stage0_prdy)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//&Always posedge; +// if(cur_datin_disable_d) +// cur_datin_disable_2d <0= 1'b1; +// else if(wr_data_stage1_prdy) +// cur_datin_disable_2d <0= 1'b0; +//&End; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable_2d <= 1'b0; + end else begin + if ((load_wr_stage1_all) == 1'b1) begin + cur_datin_disable_2d <= cur_datin_disable_d; +// VCS coverage off + end else if ((load_wr_stage1_all) == 1'b0) begin + end else begin + cur_datin_disable_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_46x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable_2d <= 1'b0; + end else begin + if ((load_wr_stage1_all) == 1'b1) begin + one_width_disable_2d <= one_width_disable_d; +// VCS coverage off + end else if ((load_wr_stage1_all) == 1'b0) begin + end else begin + one_width_disable_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_47x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable_3d <= 1'b0; + end else begin + if ((load_wr_stage2_all) == 1'b1) begin + cur_datin_disable_3d <= cur_datin_disable_2d; +// VCS coverage off + end else if ((load_wr_stage2_all) == 1'b0) begin + end else begin + cur_datin_disable_3d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_48x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage2_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable_3d <= 1'b0; + end else begin + if ((load_wr_stage2_all) == 1'b1) begin + one_width_disable_3d <= one_width_disable_2d; +// VCS coverage off + end else if ((load_wr_stage2_all) == 1'b0) begin + end else begin + one_width_disable_3d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_49x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage2_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//line buffer2 +assign pout_mem_data_sel_1_last[0] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[0] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[1] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[1] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[2] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[2] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[3] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[3] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[4] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[4] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +assign pout_mem_data_sel_1_last[5] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[5] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +assign pout_mem_data_sel_1_last[6] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[6] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +assign pout_mem_data_sel_1_last[7] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[7] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +//line buffer3,4 +assign pout_mem_data_sel_2_last[0] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[0] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re3_sel; +assign pout_mem_data_sel_2_last[1] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[1] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re3_sel; +assign pout_mem_data_sel_2_last[2] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[2] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re3_sel; +assign pout_mem_data_sel_2_last[3] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[3] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re3_sel; +assign pout_mem_data_sel_2_last[4] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[4] & (unit2d_cnt_pooling_last_2d==3'd2) & mem_re3_sel; +assign pout_mem_data_sel_2_last[5] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[5] & (unit2d_cnt_pooling_last_2d==3'd2) & mem_re3_sel; +assign pout_mem_data_sel_2_last[6] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[6] & (unit2d_cnt_pooling_last_2d==3'd3) & mem_re3_sel; +assign pout_mem_data_sel_2_last[7] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[7] & (unit2d_cnt_pooling_last_2d==3'd3) & mem_re3_sel; +//line buffer 5,6,7,8 +assign pout_mem_data_sel_3_last[0] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[0] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re4_sel; +assign pout_mem_data_sel_3_last[1] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[1] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re4_sel; +assign pout_mem_data_sel_3_last[2] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[2] & (unit2d_cnt_pooling_last_2d==3'd2) & mem_re4_sel; +assign pout_mem_data_sel_3_last[3] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[3] & (unit2d_cnt_pooling_last_2d==3'd3) & mem_re4_sel; +assign pout_mem_data_sel_3_last[4] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[4] & (unit2d_cnt_pooling_last_2d==3'd4) & mem_re4_sel; +assign pout_mem_data_sel_3_last[5] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[5] & (unit2d_cnt_pooling_last_2d==3'd5) & mem_re4_sel; +assign pout_mem_data_sel_3_last[6] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[6] & (unit2d_cnt_pooling_last_2d==3'd6) & mem_re4_sel; +assign pout_mem_data_sel_3_last[7] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[7] & (unit2d_cnt_pooling_last_2d==3'd7) & mem_re4_sel; +assign pout_mem_data_sel_last = pout_mem_data_sel_3_last | pout_mem_data_sel_2_last | pout_mem_data_sel_1_last; +//: my $k=1*(8 +6)+3; +//: print qq( +//: assign pout_mem_data_last = (mem_data0_lst & {${k}{pout_mem_data_sel_last[0]}}) | +//: (mem_data1_lst & {${k}{pout_mem_data_sel_last[1]}}) | +//: (mem_data2_lst & {${k}{pout_mem_data_sel_last[2]}}) | +//: (mem_data3_lst & {${k}{pout_mem_data_sel_last[3]}}) | +//: (mem_data4_lst & {${k}{pout_mem_data_sel_last[4]}}) | +//: (mem_data5_lst & {${k}{pout_mem_data_sel_last[5]}}) | +//: (mem_data6_lst & {${k}{pout_mem_data_sel_last[6]}}) | +//: (mem_data7_lst & {${k}{pout_mem_data_sel_last[7]}}) ; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign pout_mem_data_last = (mem_data0_lst & {17{pout_mem_data_sel_last[0]}}) | +(mem_data1_lst & {17{pout_mem_data_sel_last[1]}}) | +(mem_data2_lst & {17{pout_mem_data_sel_last[2]}}) | +(mem_data3_lst & {17{pout_mem_data_sel_last[3]}}) | +(mem_data4_lst & {17{pout_mem_data_sel_last[4]}}) | +(mem_data5_lst & {17{pout_mem_data_sel_last[5]}}) | +(mem_data6_lst & {17{pout_mem_data_sel_last[6]}}) | +(mem_data7_lst & {17{pout_mem_data_sel_last[7]}}) ; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============================================================================== +//unit2d pooling data read out +// +// +//------------------------------------------------------------------------------ +//data count in sub line +assign rd_line_out_done = wr_line_end_2d & rd_line_out; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_line_out_cnt <= {9{1'b0}}; + end else begin + if(rd_line_out_done | rd_sub_lbuf_end) + rd_line_out_cnt <= 9'd0; + else if(rd_line_out) + rd_line_out_cnt <= rd_line_out_cnt + 1'd1; + end +end +assign rd_sub_lbuf_end =((rd_line_out & (rd_line_out_cnt==BANK_DEPTH)) | rd_line_out_done); +//sub line buffer counter +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_lbuf_cnt[2:0] <= {3{1'b0}}; + end else begin + if(rd_comb_lbuf_end) + rd_sub_lbuf_cnt[2:0] <= 3'd0; + else if(rd_sub_lbuf_end) + rd_sub_lbuf_cnt[2:0] <= rd_sub_lbuf_cnt +1; + end +end +assign rd_comb_lbuf_end = (rd_sub_lbuf_end & ({2'd0,rd_sub_lbuf_cnt}==(bank_merge_num -1))) | rd_line_out_done; +//combine line buffer counter +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_comb_lbuf_cnt[2:0] <= {3{1'b0}}; + end else begin +//if(rd_lbuf_end | wr_surface_dat_done_2d) + if(rd_lbuf_end | (wr_surface_dat_done_2d & load_wr_stage2)) + rd_comb_lbuf_cnt[2:0] <= 3'd0; + else if(rd_comb_lbuf_end & last_active_line_2d) + rd_comb_lbuf_cnt[2:0] <= rd_comb_lbuf_cnt + 1; + end +end +assign rd_lbuf_end = ({2'd0,rd_comb_lbuf_cnt}==(buffer_lines_num-1)) & rd_comb_lbuf_end & last_active_line_2d; +//////////////////////////////////////////////////////////////////////////////////////////////////// +//unit2d_data_rdy need two active delays as load_wr_stage2 +assign rd_line_out = |pout_mem_data_sel; +assign rd_pout_data_en = (rd_line_out | ((load_wr_stage2 & (|mem_re_last_2d))| (cur_datin_disable_2d & wr_data_stage1_prdy))); +//read output stage +assign wr_data_stage1_prdy = (~wr_data_stage2_vld | pout_data_stage0_prdy); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_d <= 1'b0; + end else begin + if ((load_wr_stage2_all) == 1'b1) begin + rd_pout_data_en_d <= rd_pout_data_en; + end + end +end +assign rd_pout_data_stage0 = load_wr_stage3_all & rd_pout_data_en_d; +assign pout_data_stage0_prdy = ~pout_data_stage1_vld | pout_data_stage1_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_data_stage1_vld <= 1'b0; + end else begin + if(wr_data_stage2_vld) + pout_data_stage1_vld <= 1'b1; + else if(pout_data_stage1_prdy) + pout_data_stage1_vld <= 1'b0; + end +end +assign pout_data_stage1_prdy = ~pout_data_stage2_vld | pout_data_stage2_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_2d <= 1'b0; + end else begin + if ((load_wr_stage3_all) == 1'b1) begin + rd_pout_data_en_2d <= rd_pout_data_en_d; +// VCS coverage off + end else if ((load_wr_stage3_all) == 1'b0) begin + end else begin + rd_pout_data_en_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage3_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign rd_pout_data_stage1_all = pout_data_stage1_vld & pout_data_stage1_prdy; +assign rd_pout_data_stage1 = pout_data_stage1_vld & pout_data_stage1_prdy & rd_pout_data_en_2d; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_data_stage2_vld <= 1'b0; + end else begin + if(pout_data_stage1_vld) + pout_data_stage2_vld <= 1'b1; + else if(pout_data_stage2_prdy) + pout_data_stage2_vld <= 1'b0; + end +end +assign pout_data_stage2_prdy = ~pout_data_stage3_vld | pout_data_stage3_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_3d <= 1'b0; + end else begin + if ((rd_pout_data_stage1_all) == 1'b1) begin + rd_pout_data_en_3d <= rd_pout_data_en_2d; +// VCS coverage off + end else if ((rd_pout_data_stage1_all) == 1'b0) begin + end else begin + rd_pout_data_en_3d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_pout_data_stage1_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign rd_pout_data_stage2_all = pout_data_stage2_vld & pout_data_stage2_prdy; +assign rd_pout_data_stage2 = pout_data_stage2_vld & pout_data_stage2_prdy & rd_pout_data_en_3d; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_4d <= 1'b0; + end else begin + if ((rd_pout_data_stage2_all) == 1'b1) begin + rd_pout_data_en_4d <= rd_pout_data_en_3d; +// VCS coverage off + end else if ((rd_pout_data_stage2_all) == 1'b0) begin + end else begin + rd_pout_data_en_4d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_pout_data_stage2_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_data_stage3_vld <= 1'b0; + end else begin + if(pout_data_stage2_vld) + pout_data_stage3_vld <= 1'b1; + else if(pout_data_stage3_prdy) + pout_data_stage3_vld <= 1'b0; + end +end +///////////////////////////////////////////////////////// +//line buffer1 +assign pout_mem_data_sel_0 = mem_re_2d & {8{load_wr_stage2}} & {8{ mem_re1_sel}} & {8{last_active_line_2d}}; +//line buffer2 +assign pout_mem_data_sel_1[0] = mem_re_2d[0] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[1] = mem_re_2d[1] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[2] = mem_re_2d[2] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[3] = mem_re_2d[3] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[4] = mem_re_2d[4] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[5] = mem_re_2d[5] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[6] = mem_re_2d[6] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[7] = mem_re_2d[7] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +//line buffer3,4 +assign pout_mem_data_sel_2[0] = mem_re_2d[0] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[1] = mem_re_2d[1] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[2] = mem_re_2d[2] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[3] = mem_re_2d[3] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[4] = mem_re_2d[4] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd2) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[5] = mem_re_2d[5] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd2) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[6] = mem_re_2d[6] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd3) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[7] = mem_re_2d[7] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd3) & last_active_line_2d & mem_re3_sel; +//line buffer 5,6,7,8 +assign pout_mem_data_sel_3[0] = mem_re_2d[0] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[1] = mem_re_2d[1] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[2] = mem_re_2d[2] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd2) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[3] = mem_re_2d[3] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd3) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[4] = mem_re_2d[4] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd4) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[5] = mem_re_2d[5] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd5) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[6] = mem_re_2d[6] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd6) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[7] = mem_re_2d[7] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd7) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel = (pout_mem_data_sel_3 | pout_mem_data_sel_2 | pout_mem_data_sel_1 | pout_mem_data_sel_0); +always @(*) begin + case(pout_mem_data_sel[7:0]) + 8'h01: pout_mem_data_act = {pooling_2d_info_0[2:0],pooling_2d_result_0}; + 8'h02: pout_mem_data_act = {pooling_2d_info_1[2:0],pooling_2d_result_1}; + 8'h04: pout_mem_data_act = {pooling_2d_info_2[2:0],pooling_2d_result_2}; + 8'h08: pout_mem_data_act = {pooling_2d_info_3[2:0],pooling_2d_result_3}; + 8'h10: pout_mem_data_act = {pooling_2d_info_4[2:0],pooling_2d_result_4}; + 8'h20: pout_mem_data_act = {pooling_2d_info_5[2:0],pooling_2d_result_5}; + 8'h40: pout_mem_data_act = {pooling_2d_info_6[2:0],pooling_2d_result_6}; + 8'h80: pout_mem_data_act = {pooling_2d_info_7[2:0],pooling_2d_result_7}; + default: pout_mem_data_act = {(1*(8 +6)+3){1'd0}}; + endcase +end +assign int_pout_mem_data = pout_mem_data_act | pout_mem_data_last; +assign pout_mem_data = int_pout_mem_data; +//============================================================= +//pooling output data to DMA +// +//------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_mem_data_$i <= {${m}{1'b0}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_mem_data_0 <= {14{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + pout_mem_size_v <= {3{1'b0}}; + end else begin + if(rd_pout_data_en) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_mem_data_$i <= pout_mem_data[${m}*${i}+${m}-1:${m}*$i]; \n"; +//: } +//: print " pout_mem_size_v <= pout_mem_data[${k}*${m}+2:${k}*${m}]; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_mem_data_0 <= pout_mem_data[14*0+14-1:14*0]; + pout_mem_size_v <= pout_mem_data[1*14+2:1*14]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +//=========================================================== +//adding pad value in v direction +//----------------------------------------------------------- +//padding value 1x,2x,3x,4x,5x,6x,7x table +assign pout_mem_size_v_use = pout_mem_size_v; +assign padding_here = average_pooling_en & (pout_mem_size_v_use != pooling_size_v_cfg); +assign {mon_pad_table_index[0],pad_table_index[2:0]} = pooling_size_v_cfg - pout_mem_size_v_use; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal2d: pooling size should not less than active num") zzz_assert_never_54x (nvdla_core_clk, `ASSERT_RESET, ((rd_pout_data_stage0) & mon_pad_table_index & reg2dp_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(*) begin + case(pad_table_index) + 3'd1: pad_table_out = reg2dp_pad_value_1x_cfg[18:0]; //1x + 3'd2: pad_table_out = reg2dp_pad_value_2x_cfg[18:0]; //2x + 3'd3: pad_table_out = reg2dp_pad_value_3x_cfg[18:0]; //3x + 3'd4: pad_table_out = reg2dp_pad_value_4x_cfg[18:0]; //4x + 3'd5: pad_table_out = reg2dp_pad_value_5x_cfg[18:0]; //5x + 3'd6: pad_table_out = reg2dp_pad_value_6x_cfg[18:0]; //6x + 3'd7: pad_table_out = reg2dp_pad_value_7x_cfg[18:0]; //7x + default:pad_table_out = 19'd0; //1x; + endcase +end +assign kernel_width_cfg[3:0] = reg2dp_kernel_width[2:0]+3'd1; +assign {mon_pad_value,pad_value[21:0]} = $signed(pad_table_out) * $signed({{1{1'b0}}, kernel_width_cfg}); +// //: my $k = NVDLA_PDP_THROUGHPUT; +// //: foreach my $i (0..$k-1) { +// //: print qq( +// //: assign pout_mem_data$i = pout_mem_data_$i; +// //: ); +// //: } +//: my $s = "\$signed"; +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign {mon_data_8bit_${i}_ff ,data_8bit_${i}_ff} = $s({pout_mem_data_${i}[${m}-1],pout_mem_data_$i}) + $s({pad_value[${m}-1], pad_value[${m}-1:0]}); +//: assign {mon_data_8bit_${i} ,data_8bit_${i}} = padding_here ? {mon_data_8bit_${i}_ff ,data_8bit_${i}_ff} : {{2{pout_mem_data_${i}[${m}-1]}},pout_mem_data_${i}[${m}-1:0] }; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign {mon_data_8bit_0_ff ,data_8bit_0_ff} = $signed({pout_mem_data_0[14-1],pout_mem_data_0}) + $signed({pad_value[14-1], pad_value[14-1:0]}); +assign {mon_data_8bit_0 ,data_8bit_0} = padding_here ? {mon_data_8bit_0_ff ,data_8bit_0_ff} : {{2{pout_mem_data_0[14-1]}},pout_mem_data_0[14-1:0] }; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_0_$i <= {${m}{1'b0}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_0_0 <= {14{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if(average_pooling_en) begin + if(rd_pout_data_stage0) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_0_$i <= data_8bit_$i; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_0_0 <= data_8bit_0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else if(rd_pout_data_stage0)begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_0_$i <= {pout_mem_data_${i}[${m}-1],pout_mem_data_${i}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_0_0 <= {pout_mem_data_0[14-1],pout_mem_data_0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +//=========================================================== +//stage1: (* /kernel_width) +//stage1 : calcate pooling data based on real pooling size --- (* 1/kernel_width) +//----------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_recip_width_use[16:0] <= {17{1'b0}}; + end else begin + reg2dp_recip_width_use[16:0] <= reg2dp_recip_width_cfg[16:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_recip_height_use[16:0] <= {17{1'b0}}; + end else begin + reg2dp_recip_height_use[16:0] <= reg2dp_recip_height_cfg[16:0]; + end +end +//8bits +//: my $s = "\$signed"; +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign data_hmult_8bit_${i}_ext_ff = $s(pout_data_0_${i})* $s({1'b0,reg2dp_recip_width_use[16:0]}); +//: assign data_hmult_8bit_${i}_ext = average_pooling_en ? data_hmult_8bit_${i}_ext_ff : {pout_data_0_${i}[${m}-1],pout_data_0_${i}[${m}-1:0] ,16'd0}; +//: assign i8_less_neg_0_5_${i} = data_hmult_8bit_${i}_ext[${m}+16] & ((data_hmult_8bit_${i}_ext[15] & (~(|data_hmult_8bit_${i}_ext[14:0]))) | (~data_hmult_8bit_${i}_ext[15])); +//: assign i8_more_neg_0_5_${i} = data_hmult_8bit_${i}_ext[${m}+16] & data_hmult_8bit_${i}_ext[15] & (|data_hmult_8bit_${i}_ext[14:0]); +//: assign {mon_i8_neg_add1_${i},i8_neg_add1_${i}} = data_hmult_8bit_${i}_ext[$j+16-1:16]+${j}'d1; +//: assign hmult_8bit_${i} = (i8_less_neg_0_5_${i})? data_hmult_8bit_${i}_ext[$j+16-1:16] : (i8_more_neg_0_5_${i})? i8_neg_add1_${i} : (data_hmult_8bit_${i}_ext[$j+16-2:16]+data_hmult_8bit_${i}_ext[15]);//rounding 0.5=1, -0.5=-1 +//: assign data_hmult_8bit_$i = hmult_8bit_$i; +//: assign data_hmult_stage0_in${i} = data_hmult_8bit_$i; +//: ); +//: print qq( +//: // &eperl::assert("-type never -desc 'PDPCore cal2d: the MSB bits should be all same as signed bit' -expr '(rd_pout_data_stage1 & ((&data_hmult_8bit_${i}_ext[${m}+16:$j+16]) != (|data_hmult_8bit_0_ext[${m}+16:$j+16])))' "); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign data_hmult_8bit_0_ext_ff = $signed(pout_data_0_0)* $signed({1'b0,reg2dp_recip_width_use[16:0]}); +assign data_hmult_8bit_0_ext = average_pooling_en ? data_hmult_8bit_0_ext_ff : {pout_data_0_0[14-1],pout_data_0_0[14-1:0] ,16'd0}; +assign i8_less_neg_0_5_0 = data_hmult_8bit_0_ext[14+16] & ((data_hmult_8bit_0_ext[15] & (~(|data_hmult_8bit_0_ext[14:0]))) | (~data_hmult_8bit_0_ext[15])); +assign i8_more_neg_0_5_0 = data_hmult_8bit_0_ext[14+16] & data_hmult_8bit_0_ext[15] & (|data_hmult_8bit_0_ext[14:0]); +assign {mon_i8_neg_add1_0,i8_neg_add1_0} = data_hmult_8bit_0_ext[11+16-1:16]+11'd1; +assign hmult_8bit_0 = (i8_less_neg_0_5_0)? data_hmult_8bit_0_ext[11+16-1:16] : (i8_more_neg_0_5_0)? i8_neg_add1_0 : (data_hmult_8bit_0_ext[11+16-2:16]+data_hmult_8bit_0_ext[15]);//rounding 0.5=1, -0.5=-1 +assign data_hmult_8bit_0 = hmult_8bit_0; +assign data_hmult_stage0_in0 = data_hmult_8bit_0; + +// &eperl::assert("-type never -desc 'PDPCore cal2d: the MSB bits should be all same as signed bit' -expr '(rd_pout_data_stage1 & ((&data_hmult_8bit_0_ext[14+16:11+16]) != (|data_hmult_8bit_0_ext[14+16:11+16])))' "); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//load data to stage0 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage0_$i <= {${j}{1'b0}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_stage0_0 <= {11{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if(average_pooling_en) begin + if(rd_pout_data_stage1) begin +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage0_$i <= data_hmult_stage0_in$i; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_stage0_0 <= data_hmult_stage0_in0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else if(rd_pout_data_stage1)begin +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage0_$i <= pout_data_0_${i}[${j}-1:0]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_stage0_0 <= pout_data_0_0[11-1:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +//=========================================================== +//stage1: (* /kernel_height) +//8bits +//: my $s = "\$signed"; +//: my $k = 1; +//: my $x = 8; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign data_vmult_8bit_${i}_ext_ff = $s(pout_data_stage0_${i}) * $s({1'b0,reg2dp_recip_height_use[16:0]}); +//: assign data_vmult_8bit_${i}_ext = average_pooling_en ? data_vmult_8bit_${i}_ext_ff : {pout_data_stage0_${i}[${j}-1],pout_data_stage0_${i} ,16'd0}; +//: assign i8_vless_neg_0_5_$i = data_vmult_8bit_${i}_ext[${j}+16] & ((data_vmult_8bit_${i}_ext[15] & (~(|data_vmult_8bit_${i}_ext[14:0]))) | (~data_vmult_8bit_${i}_ext[15])); +//: assign i8_vmore_neg_0_5_$i = data_vmult_8bit_${i}_ext[${j}+16] & data_vmult_8bit_${i}_ext[15] & (|data_vmult_8bit_${i}_ext[14:0]); +//: assign {mon_i8_neg_vadd1_${i},i8_neg_vadd1_${i}[${x}-1:0]} = data_vmult_8bit_${i}_ext[${x}+16-1:16]+ ${x}'d1; +//: assign vmult_8bit_${i} = (i8_vless_neg_0_5_$i)? data_vmult_8bit_${i}_ext[${x}+16-1:16] : (i8_vmore_neg_0_5_$i)? i8_neg_vadd1_$i : (data_vmult_8bit_${i}_ext[${x}+16-2:16]+data_vmult_8bit_${i}_ext[15]);//rounding 0.5=1, -0.5=-1 +//: assign data_vmult_8bit_$i = vmult_8bit_$i; +//: assign data_mult_stage1_in$i = data_vmult_8bit_$i; +//: ); +//: print qq( +//: // &eperl::assert("-type never -desc 'PDPCore cal2d: the MSB 4bits should be all same as signed bit' -expr '(rd_pout_data_stage1 & ((&data_vmult_8bit_${i}_ext[${j}+16:${x}+16-1]) != (|data_vmult_8bit_${i}_ext[${j}+16:${x}+16-1])))' "); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign data_vmult_8bit_0_ext_ff = $signed(pout_data_stage0_0) * $signed({1'b0,reg2dp_recip_height_use[16:0]}); +assign data_vmult_8bit_0_ext = average_pooling_en ? data_vmult_8bit_0_ext_ff : {pout_data_stage0_0[11-1],pout_data_stage0_0 ,16'd0}; +assign i8_vless_neg_0_5_0 = data_vmult_8bit_0_ext[11+16] & ((data_vmult_8bit_0_ext[15] & (~(|data_vmult_8bit_0_ext[14:0]))) | (~data_vmult_8bit_0_ext[15])); +assign i8_vmore_neg_0_5_0 = data_vmult_8bit_0_ext[11+16] & data_vmult_8bit_0_ext[15] & (|data_vmult_8bit_0_ext[14:0]); +assign {mon_i8_neg_vadd1_0,i8_neg_vadd1_0[8-1:0]} = data_vmult_8bit_0_ext[8+16-1:16]+ 8'd1; +assign vmult_8bit_0 = (i8_vless_neg_0_5_0)? data_vmult_8bit_0_ext[8+16-1:16] : (i8_vmore_neg_0_5_0)? i8_neg_vadd1_0 : (data_vmult_8bit_0_ext[8+16-2:16]+data_vmult_8bit_0_ext[15]);//rounding 0.5=1, -0.5=-1 +assign data_vmult_8bit_0 = vmult_8bit_0; +assign data_mult_stage1_in0 = data_vmult_8bit_0; + +// &eperl::assert("-type never -desc 'PDPCore cal2d: the MSB 4bits should be all same as signed bit' -expr '(rd_pout_data_stage1 & ((&data_vmult_8bit_0_ext[11+16:8+16-1]) != (|data_vmult_8bit_0_ext[11+16:8+16-1])))' "); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $x = 8; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage1_$i <= {${x}{1'b0}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_stage1_0 <= {8{1'b0}}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if(average_pooling_en) begin + if(rd_pout_data_stage2) begin +//: my $k = 1; +//: my $x = 8; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage1_$i <= data_mult_stage1_in$i; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_stage1_0 <= data_mult_stage1_in0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else if(rd_pout_data_stage2) begin +//: my $k = 1; +//: my $x = 8; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage1_$i <= pout_data_stage0_${i}[${x}-1:0]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + pout_data_stage1_0 <= pout_data_stage0_0[8-1:0]; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +assign int_dp2wdma_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $i (0..$k-2) { +//: my $j = $k -$i -1; +//: print "pout_data_stage1_${j}, \n"; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +pout_data_stage1_0}; +assign int_dp2wdma_valid = pout_data_stage3_vld & rd_pout_data_en_4d; +assign pout_data_stage3_prdy = pdp_dp2wdma_ready; +//============================= +//====================================== +//interface between POOLING data and DMA +assign pdp_dp2wdma_pd = int_dp2wdma_pd; +assign pdp_dp2wdma_valid = int_dp2wdma_valid; +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property PDP_line_buf_busy__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + &unit2d_en & (pout_width_cur==13'hf); + endproperty +// Cover 0 : "&unit2d_en & (pout_width_cur==13'hf)" + FUNCPOINT_PDP_line_buf_busy__0_COV : cover property (PDP_line_buf_busy__0_cov); + `endif +`endif +//VCS coverage on +////============== +////OBS signals +////============== +//assign obs_bus_pdp_cal2d_unit_en = unit2d_en[7:0]; +//assign obs_bus_pdp_cal2d_bank_we = mem_we[7:0]; +//assign obs_bus_pdp_cal2d_bank_re = mem_re[7:0] | mem_re_last[7:0]; +//assign obs_bus_pdp_cal2d_bubble = cur_datin_disable; +endmodule // NV_NVDLA_PDP_CORE_cal2d diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v.vcp new file mode 100644 index 0000000..977c8fd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v.vcp @@ -0,0 +1,4779 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_cal2d.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_cal2d ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,padding_v_cfg //|< i + ,pdp_dp2wdma_ready //|< i + ,pdp_op_start //|< i + ,pooling1d_pd //|< i + ,pooling1d_pvld //|< i + ,pooling_channel_cfg //|< i + ,pooling_out_fwidth_cfg //|< i + ,pooling_out_lwidth_cfg //|< i + ,pooling_out_mwidth_cfg //|< i + ,pooling_size_v_cfg //|< i + ,pooling_splitw_num_cfg //|< i + ,pooling_stride_v_cfg //|< i + ,pooling_type_cfg //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_out_width //|< i +//,reg2dp_input_data //|< i +//,reg2dp_int16_en //|< i +//,reg2dp_int8_en //|< i + ,reg2dp_kernel_height //|< i + ,reg2dp_kernel_width //|< i + ,reg2dp_pad_bottom_cfg //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value_1x_cfg //|< i + ,reg2dp_pad_value_2x_cfg //|< i + ,reg2dp_pad_value_3x_cfg //|< i + ,reg2dp_pad_value_4x_cfg //|< i + ,reg2dp_pad_value_5x_cfg //|< i + ,reg2dp_pad_value_6x_cfg //|< i + ,reg2dp_pad_value_7x_cfg //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_recip_height_cfg //|< i + ,reg2dp_recip_width_cfg //|< i + ,pdp_dp2wdma_pd //|> o + ,pdp_dp2wdma_valid //|> o + ,pooling1d_prdy //|> o + ); +///////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input [2:0] padding_v_cfg; +input pdp_dp2wdma_ready; +input pdp_op_start; +//: my $m = 1*(8 +6); +//: print " input [$m-1:0] pooling1d_pd; \n"; +input pooling1d_pvld; +input [12:0] pooling_channel_cfg; +input [9:0] pooling_out_fwidth_cfg; +input [9:0] pooling_out_lwidth_cfg; +input [9:0] pooling_out_mwidth_cfg; +input [2:0] pooling_size_v_cfg; +input [7:0] pooling_splitw_num_cfg; +input [3:0] pooling_stride_v_cfg; +input [1:0] pooling_type_cfg; +input [31:0] pwrbus_ram_pd; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_out_width; +//input [1:0] reg2dp_input_data; +//input reg2dp_int16_en; +//input reg2dp_int8_en; +input [2:0] reg2dp_kernel_height; +input [2:0] reg2dp_kernel_width; +input [2:0] reg2dp_pad_bottom_cfg; +input [2:0] reg2dp_pad_top; +input [18:0] reg2dp_pad_value_1x_cfg; +input [18:0] reg2dp_pad_value_2x_cfg; +input [18:0] reg2dp_pad_value_3x_cfg; +input [18:0] reg2dp_pad_value_4x_cfg; +input [18:0] reg2dp_pad_value_5x_cfg; +input [18:0] reg2dp_pad_value_6x_cfg; +input [18:0] reg2dp_pad_value_7x_cfg; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [16:0] reg2dp_recip_height_cfg; +input [16:0] reg2dp_recip_width_cfg; +//: my $m = 1*8; +//: print "output [${m}-1:0] pdp_dp2wdma_pd; \n"; +output pdp_dp2wdma_valid; +output pooling1d_prdy; +///////////////////////////////////////////////////////////////////////// +wire [8:0] BANK_DEPTH; +wire active_last_line; +wire average_pooling_en; +wire bubble_en_end; +wire [2:0] bubble_num_dec; +wire [3:0] buffer_lines_0; +wire [3:0] buffer_lines_1; +wire [3:0] buffer_lines_2; +wire [3:0] buffer_lines_3; +wire [3:0] cube_in_height_cfg; +wire cur_datin_disable_2d_sync; +wire data_c_end; +wire [3:0] first_out_num; +wire [2:0] first_out_num_dec2; +wire first_splitw; +wire [2:0] flush_in_next_surf; +wire [2:0] flush_num_dec1; +wire flush_read_en; +wire [3:0] h_pt; +wire [4:0] h_pt_pb; +wire init_cnt; +wire [7:0] init_unit2d_set; +wire [1*8 -1:0] int_dp2wdma_pd; +wire int_dp2wdma_valid; +wire [1*(8 +6)+2:0] int_pout_mem_data; +wire [3:0] kernel_width_cfg; +wire last_c; +wire last_line_in; +wire last_out_done; +wire last_pooling_flag; +wire last_splitw; +wire last_sub_lbuf_done; +wire line_end; +wire load_din; +wire load_din_all; +wire load_wr_stage1; +wire load_wr_stage1_all; +wire load_wr_stage2; +wire load_wr_stage2_all; +wire load_wr_stage3; +wire load_wr_stage3_all; +wire [7:0] mem_data_valid; +wire [8:0] mem_raddr; +wire [5:0] mem_raddr_2d_sync; +wire [1*(8 +6)+3:0] mem_rdata_0; +wire [1*(8 +6)+3:0] mem_rdata_1; +wire [1*(8 +6)+3:0] mem_rdata_2; +wire [1*(8 +6)+3:0] mem_rdata_3; +wire [1*(8 +6)+3:0] mem_rdata_4; +wire [1*(8 +6)+3:0] mem_rdata_5; +wire [1*(8 +6)+3:0] mem_rdata_6; +wire [1*(8 +6)+3:0] mem_rdata_7; +wire [7:0] mem_re; +wire [7:0] mem_re1; +wire [7:0] mem_re1_1st; +wire [7:0] mem_re2; +wire [7:0] mem_re2_1st; +wire [7:0] mem_re2_last; +wire [7:0] mem_re3; +wire [7:0] mem_re3_1st; +wire [7:0] mem_re3_last; +wire [7:0] mem_re4; +wire [7:0] mem_re4_1st; +wire [7:0] mem_re4_last; +wire [7:0] mem_re_1st; +wire [7:0] mem_re_1st_2d_sync; +wire [7:0] mem_re_2d_sync; +wire [7:0] mem_re_last; +wire [8:0] mem_waddr_0; +wire [8:0] mem_waddr_1; +wire [8:0] mem_waddr_2; +wire [8:0] mem_waddr_3; +wire [8:0] mem_waddr_4; +wire [8:0] mem_waddr_5; +wire [8:0] mem_waddr_6; +wire [8:0] mem_waddr_7; +wire [1*(8 +6)+3:0] mem_wdata_0; +wire [1*(8 +6)+3:0] mem_wdata_1; +wire [1*(8 +6)+3:0] mem_wdata_2; +wire [1*(8 +6)+3:0] mem_wdata_3; +wire [1*(8 +6)+3:0] mem_wdata_4; +wire [1*(8 +6)+3:0] mem_wdata_5; +wire [1*(8 +6)+3:0] mem_wdata_6; +wire [1*(8 +6)+3:0] mem_wdata_7; +wire [7:0] mem_we; +wire middle_surface_trig; +wire [0:0] mon_first_out_num; +wire mon_flush_in_next_surf; +wire mon_flush_num_dec1; +wire [0:0] mon_pad_table_index; +wire mon_pad_value; +wire [1:0] mon_pooling_size_minus_sride; +wire mon_rest_height; +wire [5:0] mon_strip_ycnt_offset; +wire [1:0] mon_unit2d_cnt_pooling_max; +wire need_flush; +wire one_width_bubble_end; +wire one_width_disable_2d_sync; +wire one_width_norm_rdy; +wire [2:0] pad_l; +wire [16:0] pad_line_sum; +wire pad_line_sum_prdy; +wire pad_line_sum_pvld; +wire [2:0] pad_r; +wire [2:0] pad_table_index; +wire [21:0] pad_value; +wire padding_here; +wire [2:0] padding_stride1_num; +wire [2:0] padding_stride2_num; +wire [2:0] padding_stride3_num; +wire [2:0] padding_stride4_num; +wire pooling1d_norm_rdy; +wire [1*(8 +6)-1:0] pooling1d_pd_use; +wire pooling1d_prdy_use; +wire pooling1d_pvld_use; +wire pooling1d_vld_rebuild; +wire [31:0] pooling_2d_info; +wire [3:0] pooling_2d_info_0; +wire [3:0] pooling_2d_info_1; +wire [3:0] pooling_2d_info_2; +wire [3:0] pooling_2d_info_3; +wire [3:0] pooling_2d_info_4; +wire [3:0] pooling_2d_info_5; +wire [3:0] pooling_2d_info_6; +wire [3:0] pooling_2d_info_7; +wire [31:0] pooling_2d_info_sync; +wire pooling_2d_rdy; +wire [1*(8 +6)-1:0] pooling_2d_result_0; +wire [1*(8 +6)-1:0] pooling_2d_result_1; +wire [1*(8 +6)-1:0] pooling_2d_result_2; +wire [1*(8 +6)-1:0] pooling_2d_result_3; +wire [1*(8 +6)-1:0] pooling_2d_result_4; +wire [1*(8 +6)-1:0] pooling_2d_result_5; +wire [1*(8 +6)-1:0] pooling_2d_result_6; +wire [1*(8 +6)-1:0] pooling_2d_result_7; +wire [1*(8 +6)-1:0] pooling_datin; +wire [1*(8 +6)-1:0] pooling_datin_ext; +wire [3:0] pooling_size; +wire [2:0] pooling_size_minus_sride; +wire [3:0] pooling_size_v; +wire pooling_stride_big; +wire [4:0] pooling_stride_v; +wire pout_data_stage0_prdy; +wire pout_data_stage1_prdy; +wire pout_data_stage2_prdy; +wire pout_data_stage3_prdy; +wire [1*(8 +6)+2:0] pout_mem_data; +wire [1*(8 +6)+2:0] pout_mem_data_last; +wire [1*(8 +6)+2:0] pout_mem_data_last_sync; +wire [7:0] pout_mem_data_sel; +wire [7:0] pout_mem_data_sel_0; +wire [7:0] pout_mem_data_sel_1; +wire [7:0] pout_mem_data_sel_1_last; +wire [7:0] pout_mem_data_sel_2; +wire [7:0] pout_mem_data_sel_2_last; +wire [7:0] pout_mem_data_sel_3; +wire [7:0] pout_mem_data_sel_3_last; +wire [7:0] pout_mem_data_sel_last; +wire [7:0] pout_mem_data_sel_last_sync; +wire [7:0] pout_mem_data_sel_sync; +wire [2:0] pout_mem_size_v_use; +wire [12:0] pout_width_cur; +wire rd_comb_lbuf_end; +wire rd_lbuf_end; +wire rd_line_out; +wire rd_line_out_done; +wire rd_pout_data_en; +wire rd_pout_data_stage0; +wire rd_pout_data_stage1; +wire rd_pout_data_stage1_all; +wire rd_pout_data_stage2; +wire rd_pout_data_stage2_all; +wire rd_sub_lbuf_end; +wire [12:0] rest_height; +wire [13:0] rest_height_use; +wire small_active; +wire splitw_enable; +wire [4:0] stride; +wire [4:0] stride_1x; +wire [5:0] stride_2x; +wire [6:0] stride_3x; +wire [6:0] stride_4x; +wire [7:0] stride_5x; +wire [7:0] stride_6x; +wire [7:0] stride_7x; +wire stride_end; +wire stride_trig_end; +wire [2:0] strip_ycnt_offset; +wire stripe_receive_done; +wire sub_lbuf_dout_done; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "wire [12-${k}:0] surface_num; \n"; +//: print "reg [12-${k}:0] surface_cnt_rd; \n"; +//wire [9:0] surface_num_0; +//wire [9:0] surface_num_1; +wire [7:0] unit2d_clr; +wire [3:0] unit2d_cnt_pooling_a1; +wire [3:0] unit2d_cnt_pooling_a2; +wire [3:0] unit2d_cnt_pooling_a3; +wire [3:0] unit2d_cnt_pooling_a4; +wire [3:0] unit2d_cnt_pooling_a5; +wire [3:0] unit2d_cnt_pooling_a6; +wire [3:0] unit2d_cnt_pooling_a7; +wire unit2d_cnt_pooling_end; +wire unit2d_cnt_pooling_last_end; +wire [2:0] unit2d_cnt_pooling_max; +wire [7:0] unit2d_en_last; +wire [7:0] unit2d_set; +wire [7:0] unit2d_set_trig; +wire [2:0] unit2d_vsize1_0; +wire [2:0] unit2d_vsize1_1; +wire [2:0] unit2d_vsize1_2; +wire [2:0] unit2d_vsize1_3; +wire [2:0] unit2d_vsize1_4; +wire [2:0] unit2d_vsize1_5; +wire [2:0] unit2d_vsize1_6; +wire [2:0] unit2d_vsize1_7; +wire [2:0] unit2d_vsize2_0; +wire [2:0] unit2d_vsize2_1; +wire [2:0] unit2d_vsize2_2; +wire [2:0] unit2d_vsize2_3; +wire [2:0] unit2d_vsize2_4; +wire [2:0] unit2d_vsize2_5; +wire [2:0] unit2d_vsize2_6; +wire [2:0] unit2d_vsize2_7; +wire [2:0] unit2d_vsize3_0; +wire [2:0] unit2d_vsize3_1; +wire [2:0] unit2d_vsize3_2; +wire [2:0] unit2d_vsize3_3; +wire [2:0] unit2d_vsize3_4; +wire [2:0] unit2d_vsize3_5; +wire [2:0] unit2d_vsize3_6; +wire [2:0] unit2d_vsize3_7; +wire [2:0] unit2d_vsize4_0; +wire [2:0] unit2d_vsize4_1; +wire [2:0] unit2d_vsize4_2; +wire [2:0] unit2d_vsize4_3; +wire [2:0] unit2d_vsize4_4; +wire [2:0] unit2d_vsize4_5; +wire [2:0] unit2d_vsize4_6; +wire [2:0] unit2d_vsize4_7; +wire [2:0] unit2d_vsize_0; +wire [2:0] unit2d_vsize_1; +wire [2:0] unit2d_vsize_2; +wire [2:0] unit2d_vsize_3; +wire [2:0] unit2d_vsize_4; +wire [2:0] unit2d_vsize_5; +wire [2:0] unit2d_vsize_6; +wire [2:0] unit2d_vsize_7; +wire [2:0] up_pnum0; +wire wr_data_stage0_prdy; +wire wr_data_stage1_prdy; +wire wr_line_dat_done; +wire wr_subcube_dat_done; +wire wr_surface_dat_done; +wire wr_total_cube_done; +reg [3:0] bank_merge_num; +reg [2:0] bubble_add; +reg [2:0] bubble_cnt; +reg [2:0] bubble_num; +reg [2:0] bubble_num_use; +reg [3:0] buffer_lines_num; +reg [4:0] c_cnt; +reg [4:0] channel_cnt; +reg cube_end_flag; +reg cur_datin_disable; +reg cur_datin_disable_2d; +reg cur_datin_disable_3d; +reg cur_datin_disable_d; +reg [1*(8 +6)-1:0] datin_buf; +reg [1*(8 +6)-1:0] datin_buf_2d; +reg [2:0] flush_num; +reg [2:0] flush_num_cal; +reg flush_read_en_d; +reg [8:0] int_mem_waddr; +reg [1*(8 +6)+3:0] int_mem_wdata_0; +reg [1*(8 +6)+3:0] int_mem_wdata_1; +reg [1*(8 +6)+3:0] int_mem_wdata_2; +reg [1*(8 +6)+3:0] int_mem_wdata_3; +reg [1*(8 +6)+3:0] int_mem_wdata_4; +reg [1*(8 +6)+3:0] int_mem_wdata_5; +reg [1*(8 +6)+3:0] int_mem_wdata_6; +reg [1*(8 +6)+3:0] int_mem_wdata_7; +reg [7:0] int_mem_we; +reg is_one_width_in; +reg last_active_line_2d; +reg last_active_line_d; +reg [2:0] last_out_cnt; +reg last_out_en; +reg [12:0] line_cnt; +reg [1*(8 +6)+2:0] mem_data0; +reg [1*(8 +6)+2:0] mem_data0_lst; +reg [1*(8 +6)+2:0] mem_data1; +reg [1*(8 +6)+2:0] mem_data1_lst; +reg [1*(8 +6)+2:0] mem_data2; +reg [1*(8 +6)+2:0] mem_data2_lst; +reg [1*(8 +6)+2:0] mem_data3; +reg [1*(8 +6)+2:0] mem_data3_lst; +reg [1*(8 +6)+2:0] mem_data4; +reg [1*(8 +6)+2:0] mem_data4_lst; +reg [1*(8 +6)+2:0] mem_data5; +reg [1*(8 +6)+2:0] mem_data5_lst; +reg [1*(8 +6)+2:0] mem_data6; +reg [1*(8 +6)+2:0] mem_data6_lst; +reg [1*(8 +6)+2:0] mem_data7; +reg [1*(8 +6)+2:0] mem_data7_lst; +reg [8:0] mem_raddr_2d; +reg [8:0] mem_raddr_d; +reg mem_re1_sel; +reg mem_re2_sel; +reg mem_re2_sel_last; +reg mem_re3_sel; +reg mem_re3_sel_last; +reg mem_re4_sel; +reg mem_re4_sel_last; +reg [7:0] mem_re_1st_2d; +reg [7:0] mem_re_1st_d; +reg [7:0] mem_re_2d; +reg [7:0] mem_re_d; +reg [7:0] mem_re_last_2d; +reg [7:0] mem_re_last_d; +reg need_bubble; +reg [2:0] next2_0; +reg [2:0] next2_1; +reg [2:0] next3_0; +reg [2:0] next3_1; +reg [2:0] next3_2; +reg [2:0] next4_0; +reg [2:0] next4_1; +reg [2:0] next4_2; +reg [2:0] next4_3; +reg [2:0] next5_0; +reg [2:0] next5_1; +reg [2:0] next5_2; +reg [2:0] next5_3; +reg [2:0] next5_4; +reg [2:0] next6_0; +reg [2:0] next6_1; +reg [2:0] next6_2; +reg [2:0] next6_3; +reg [2:0] next6_4; +reg [2:0] next6_5; +reg [2:0] next7_0; +reg [2:0] next7_1; +reg [2:0] next7_2; +reg [2:0] next7_3; +reg [2:0] next7_4; +reg [2:0] next7_5; +reg [2:0] next7_6; +reg [2:0] one_width_bubble_cnt; +reg one_width_disable; +reg one_width_disable_2d; +reg one_width_disable_3d; +reg one_width_disable_d; +reg [5:0] pad_r_remain; +reg [18:0] pad_table_out; +reg [2:0] padding_stride_num; +reg [2:0] pnum_flush0; +reg [2:0] pnum_flush1; +reg [2:0] pnum_flush2; +reg [2:0] pnum_flush3; +reg [2:0] pnum_flush4; +reg [2:0] pnum_flush5; +reg [2:0] pnum_flush6; +reg pout_data_stage1_vld; +reg pout_data_stage2_vld; +reg pout_data_stage3_vld; +//: my $k = 1; +//: my $x = 8; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: reg [${m}-1:0] pout_mem_data_$i; +//: // wire [${m}-1:0] pout_mem_data$i; +//: wire [${m}:0] data_8bit_${i}; +//: wire [${m}:0] data_8bit_${i}_ff; +//: wire mon_data_8bit_${i}; +//: wire mon_data_8bit_${i}_ff; +//: reg [${m}:0] pout_data_0_${i}; +//: wire [${m}+16:0] data_hmult_8bit_${i}_ext_ff; +//: wire [${m}+16:0] data_hmult_8bit_${i}_ext; +//: wire i8_less_neg_0_5_${i}; +//: wire i8_more_neg_0_5_${i}; +//: wire mon_i8_neg_add1_${i}; +//: wire [${j}-1:0] i8_neg_add1_${i}; +//: wire [${j}-1:0] hmult_8bit_${i}; +//: wire [${j}-1:0] data_hmult_8bit_${i}; +//: wire [${j}-1:0] data_hmult_stage0_in$i; +//: reg [${j}-1:0] pout_data_stage0_$i; +//: wire [${j}+16:0] data_vmult_8bit_${i}_ext_ff; +//: wire [${j}+16:0] data_vmult_8bit_${i}_ext; +//: wire i8_vless_neg_0_5_${i}; +//: wire i8_vmore_neg_0_5_${i}; +//: wire mon_i8_neg_vadd1_${i}; +//: wire [${x}-1:0] i8_neg_vadd1_${i}; +//: wire [${x}-1:0] vmult_8bit_${i}; +//: wire [${x}-1:0] data_vmult_8bit_${i}; +//: wire [${x}-1:0] data_mult_stage1_in${i}; +//: reg [${x}-1:0] pout_data_stage1_${i}; +//: ); +//: } +reg [1*(8 +6)+2:0] pout_mem_data_act; +reg [2:0] pout_mem_size_v; +reg [12:0] pout_width_cur_latch; +reg [2:0] rd_comb_lbuf_cnt; +reg [8:0] rd_line_out_cnt; +reg rd_pout_data_en_2d; +reg rd_pout_data_en_3d; +reg rd_pout_data_en_4d; +reg rd_pout_data_en_d; +reg [2:0] rd_sub_lbuf_cnt; +reg [16:0] reg2dp_recip_height_use; +reg [16:0] reg2dp_recip_width_use; +reg [2:0] samllH_flush_num; +reg [2:0] strip_ycnt_psize; +reg [3:0] strip_ycnt_stride; +reg [3:0] strip_ycnt_stride_f; +reg [8:0] sub_lbuf_dout_cnt; +reg subend_need_flush_flg; +reg surfend_need_bubble_flg; +reg [2:0] unit2d_cnt_pooling; +reg [2:0] unit2d_cnt_pooling_last; +reg [2:0] unit2d_cnt_pooling_last_2d; +reg [2:0] unit2d_cnt_pooling_last_d; +reg [2:0] unit2d_cnt_stride; +reg [7:0] unit2d_en; +reg [7:0] unit2d_mem_1strd; +reg [2:0] unit2d_vsize_cnt_0; +reg [2:0] unit2d_vsize_cnt_0_d; +reg [2:0] unit2d_vsize_cnt_1; +reg [2:0] unit2d_vsize_cnt_1_d; +reg [2:0] unit2d_vsize_cnt_2; +reg [2:0] unit2d_vsize_cnt_2_d; +reg [2:0] unit2d_vsize_cnt_3; +reg [2:0] unit2d_vsize_cnt_3_d; +reg [2:0] unit2d_vsize_cnt_4; +reg [2:0] unit2d_vsize_cnt_4_d; +reg [2:0] unit2d_vsize_cnt_5; +reg [2:0] unit2d_vsize_cnt_5_d; +reg [2:0] unit2d_vsize_cnt_6; +reg [2:0] unit2d_vsize_cnt_6_d; +reg [2:0] unit2d_vsize_cnt_7; +reg [2:0] unit2d_vsize_cnt_7_d; +reg up_pnum1; +reg [1:0] up_pnum2; +reg [1:0] up_pnum3; +reg [2:0] up_pnum4; +reg [2:0] up_pnum5; +reg wr_data_stage0_vld; +reg wr_data_stage1_vld; +reg wr_data_stage2_vld; +reg [12:0] wr_line_dat_cnt; +reg wr_line_end_2d; +reg wr_line_end_buf; +reg [7:0] wr_splitc_cnt; +reg [2:0] wr_sub_lbuf_cnt; +reg [12:0] wr_surface_dat_cnt; +reg wr_surface_dat_done_2d; +reg wr_surface_dat_done_buf; +///////////////////////////////////////////////////////////////////////////////////////// +//============================================================== +////pdp cube_out_width setting +////////////////////////////// +//pdp cube_out_width setting, limited by line buffer size +////////////////////////////// +//non-split mode +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd127) & (bank_merge_num==4'd8)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd63) & (bank_merge_num==4'd4)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd31) & (bank_merge_num==4'd2)); // spyglass disable W504 SelfDeterminedExpr-ML + nv_assert_never #(0,0,"PDP cube_out_width setting out of range") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, load_din &(pout_width_cur > 13'd15) & (bank_merge_num==4'd1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============================================================== +//bank depth follows rule of 16 elements in width in worst case +//it's 64 in t194 +//-------------------------------------------------------------- +//: my $depth = (8/1)*16-1; +//: print " assign BANK_DEPTH = 9'd${depth}; \n"; +//============================================================== +// buffer the input data from pooling 1D unit +// calculate the data postion in input-data-cube +// +//-------------------------------------------------------------- +assign pooling1d_prdy = pooling1d_prdy_use; +assign pooling1d_pvld_use = pooling1d_pvld; +assign pooling1d_pd_use = pooling1d_pd; +assign pooling1d_prdy_use = one_width_norm_rdy & (~cur_datin_disable); +assign one_width_norm_rdy = pooling1d_norm_rdy & (~one_width_disable); +////////////////////////////////////////////////////////////////////////////////////// +assign load_din = pooling1d_prdy_use & pooling1d_pvld_use; +assign stripe_receive_done = load_din & data_c_end; +assign average_pooling_en = (pooling_type_cfg== 2'h0 ); +//assign int8_en = (reg2dp_input_data[1:0] == 2'h0 ); +//assign int16_en = (reg2dp_input_data[1:0] == 2'h1 ); +////////////////////////////////////////////////////////////////////////////////////// +//: my $m = 8; +//: my $k = 1; +//: my $j = int($m / $k); +//: print "assign data_c_end = (c_cnt == 5'd${j}-1); \n"; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + c_cnt[4:0] <= 0; + end else if(load_din) begin + if(data_c_end) + c_cnt[4:0] <= 0; + else + c_cnt[4:0] <= c_cnt + 1'b1; + end +end +//end of line +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_dat_cnt[12:0] <= {13{1'b0}}; + end else begin + if(wr_line_dat_done) + wr_line_dat_cnt[12:0] <= 0; + else if(stripe_receive_done) + wr_line_dat_cnt[12:0] <= wr_line_dat_cnt + 1; + end +end +assign wr_line_dat_done = (wr_line_dat_cnt==pout_width_cur) & stripe_receive_done; +//end of surface +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_cnt <= {13{1'b0}}; + end else begin + if(wr_surface_dat_done) + wr_surface_dat_cnt <= 13'd0; + else if(wr_line_dat_done) + wr_surface_dat_cnt <= wr_surface_dat_cnt + 13'd1; + end +end +assign last_line_in = ( wr_surface_dat_cnt==reg2dp_cube_in_height[12:0]); +assign wr_surface_dat_done = wr_line_dat_done & last_line_in; +//end of splitw +//assign cube_out_channel[13:0]= pooling_channel_cfg[12:0] + 1'b1; +//////16bits: INT16 or FP16 +////assign {mon_surface_num_0,surface_num_0[9:0]} = cube_out_channel[13:4] + {9'd0,(|cube_out_channel[3:0])}; +//////8bits: INT8 +////assign surface_num_1[9:0] = {1'b0,cube_out_channel[13:5]} + (|cube_out_channel[4:0]); +////assign surface_num = int8_en ? surface_num_1 : surface_num_0; +//: my $m = 8; +//: my $k = int(log($m)/log(2)); +//: print "assign surface_num = pooling_channel_cfg[12:${k}]; \n"; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surface_cnt_rd <= 0; + end else begin + if(wr_subcube_dat_done) + surface_cnt_rd <= 0; + else if(wr_surface_dat_done) + surface_cnt_rd <= surface_cnt_rd + 1; + end +end +assign wr_subcube_dat_done = (surface_num==surface_cnt_rd) & wr_surface_dat_done; +//total cube done +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_splitc_cnt[7:0] <= {8{1'b0}}; + end else begin + if(wr_total_cube_done) + wr_splitc_cnt[7:0] <= 8'd0; + else if(wr_subcube_dat_done) + wr_splitc_cnt[7:0] <= wr_splitc_cnt + 1; + end +end +assign wr_total_cube_done = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & wr_subcube_dat_done; +////////////////////////////////////////////////////////////////////////////////////// +//split width selection +assign splitw_enable = (pooling_splitw_num_cfg!=8'd0); +assign last_splitw = (wr_splitc_cnt==pooling_splitw_num_cfg[7:0]) & splitw_enable; +assign first_splitw = (wr_splitc_cnt==8'd0) & splitw_enable; +assign pout_width_cur[12:0]= (~splitw_enable) ? reg2dp_cube_out_width[12:0] : + (last_splitw ? {3'd0,pooling_out_lwidth_cfg[9:0]} : + first_splitw ? {3'd0,pooling_out_fwidth_cfg[9:0]} : + {3'd0,pooling_out_mwidth_cfg[9:0]}); +///////////////////////////////////////////////////////////////////////////////////// +// assign data_posinfo = wr_line_dat_done; +//============================================================= +// physical memory bank 8 +// 8 memory banks are used to load maximum 8 pooling output lines +// +//------------------------------------------------------------- +//maximum pooling output lines need to be buffer +//stride 1 +assign buffer_lines_0[3:0] = pooling_size_v[3:0]; +//stride 2 +assign buffer_lines_1[3:0] = {1'd0,pooling_size_v[3:1]} + pooling_size_v[0]; +//stride 3 +assign buffer_lines_2[3:0] = (3'd5>= pooling_size_v_cfg[2:0] ) ? 4'd2: 4'd3; +//stride 4 5 6 7 +assign buffer_lines_3 = 4'd2; +assign pooling_stride_big = (pooling_stride_v_cfg>={1'b0,pooling_size_v_cfg[2:0]}); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + buffer_lines_num <= {4{1'b0}}; + end else begin + if(pdp_op_start) begin + if(pooling_stride_big) + buffer_lines_num <= 4'd1; + else begin + case(pooling_stride_v_cfg) + 4'd0: buffer_lines_num <= buffer_lines_0; + 4'd1: buffer_lines_num <= buffer_lines_1; + 4'd2: buffer_lines_num <= buffer_lines_2; + default: buffer_lines_num <= buffer_lines_3; + endcase + end + end + end +end +//memory bank merge num +always @( + buffer_lines_num + ) begin + case(buffer_lines_num) + 4'd1: bank_merge_num = 4'd8; + 4'd2: bank_merge_num = 4'd4; + 4'd4,4'd3: bank_merge_num = 4'd2; + default : bank_merge_num = 4'd1; + endcase +end +//========================================================== +//bank active enable signal +// +//---------------------------------------------------------- +//stride intial data +//stride ==1 +assign padding_stride1_num[2:0] = padding_v_cfg[2:0]; +//stride ==2 +assign padding_stride2_num[2:0] = {1'b0,padding_v_cfg[2:1]}; +//stride ==3 +assign padding_stride3_num[2:0]= (padding_v_cfg[2:0]>=3'd6) ? 3'd2 : + (padding_v_cfg[2:0]>=3'd3) ? 3'd1 : 3'd0; +//stride==4 5 6 7 +assign padding_stride4_num[2:0]= ({1'b0,padding_v_cfg[2:0]}>pooling_stride_v_cfg) ? 3'd1:3'd0; +assign pooling_stride_v[4:0] = pooling_stride_v_cfg[3:0] + 1; +//real num-1 +always @( + pooling_stride_v_cfg + or padding_stride1_num + or padding_stride2_num + or padding_stride3_num + or padding_stride4_num + ) begin + case(pooling_stride_v_cfg[3:0]) + 4'd0: padding_stride_num = padding_stride1_num; + 4'd1: padding_stride_num = padding_stride2_num; + 4'd2: padding_stride_num = padding_stride3_num; + default:padding_stride_num=padding_stride4_num; + endcase +end +assign {mon_strip_ycnt_offset[5:0],strip_ycnt_offset[2:0]} = {5'd0,padding_v_cfg} - padding_stride_num * pooling_stride_v; +///////////////////////////////////////////////////////////////////////////////// +assign middle_surface_trig = wr_surface_dat_done & (~wr_total_cube_done); +assign stride_end = wr_line_dat_done & (strip_ycnt_stride== pooling_stride_v_cfg); +assign init_cnt = middle_surface_trig | pdp_op_start; +//pooling stride in vertical direction +always @( + init_cnt + or strip_ycnt_offset + or stride_end + or wr_line_dat_done + or strip_ycnt_stride + ) begin + if(init_cnt) + strip_ycnt_stride_f[3:0] = {1'b0,strip_ycnt_offset}; + else if(stride_end) + strip_ycnt_stride_f[3:0] = 4'd0; + else if(wr_line_dat_done) + strip_ycnt_stride_f[3:0] = strip_ycnt_stride + 1; + else + strip_ycnt_stride_f[3:0] = strip_ycnt_stride; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_ycnt_stride[3:0] <= {4{1'b0}}; + end else begin + if ((init_cnt | stride_end | wr_line_dat_done) == 1'b1) begin + strip_ycnt_stride[3:0] <= strip_ycnt_stride_f; +// VCS coverage off + end else if ((init_cnt | stride_end | wr_line_dat_done) == 1'b0) begin + end else begin + strip_ycnt_stride[3:0] <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(init_cnt | stride_end | wr_line_dat_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//2D pooling result ready +assign {mon_pooling_size_minus_sride[1:0],pooling_size_minus_sride[2:0]} = {1'b0,pooling_size_v_cfg[2:0]} - pooling_stride_v_cfg[3:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + strip_ycnt_psize <= {3{1'b0}}; + end else begin + if(init_cnt) + strip_ycnt_psize[2:0] <= padding_v_cfg[2:0]; + else if({1'b0,pooling_size_v_cfg} >= pooling_stride_v_cfg) begin + if(pooling_2d_rdy) + strip_ycnt_psize <= pooling_size_minus_sride[2:0]; + else if(wr_line_dat_done) + strip_ycnt_psize <= strip_ycnt_psize + 1; + end else begin // pooling_size < stride + if(strip_ycnt_stride_f <= {1'b0,pooling_size_v_cfg}) + strip_ycnt_psize <= strip_ycnt_stride_f[2:0]; + else + strip_ycnt_psize <= 3'd0; + end + end +end +//===================================================================== +assign pooling_size_v[3:0] = pooling_size_v_cfg[2:0] + 1; +assign pooling_size[3:0] = pooling_size_v; +assign stride[4:0] = pooling_stride_v; +assign pad_l[2:0] = padding_v_cfg; +assign pad_r = reg2dp_pad_bottom_cfg[2:0];//3'd1; +//active_data_num_last_pooling = (pad_l + width) % stride; +//assign {mon_active_data_num_last_pooling[1:0],active_data_num_last_pooling[2:0]} = pooling_size - pad_r; +//line num need flush at surface end +always @( + pad_r + or stride_1x + or stride_2x + or stride_3x + or stride_4x + or stride_5x + or stride_6x + or stride_7x + ) begin + if({2'd0,pad_r} < stride_1x[4:0]) + flush_num_cal = 3'd0; + else if({3'd0,pad_r} < stride_2x[5:0]) + flush_num_cal = 3'd1; + else if({4'd0,pad_r} < stride_3x[6:0]) + flush_num_cal = 3'd2; + else if({4'd0,pad_r} < stride_4x[6:0]) + flush_num_cal = 3'd3; + else if({5'd0,pad_r} < stride_5x[7:0]) + flush_num_cal = 3'd4; + else if({5'd0,pad_r} < stride_6x[7:0]) + flush_num_cal = 3'd5; + else if({5'd0,pad_r} < stride_7x[7:0]) + flush_num_cal = 3'd6; + else// if({5'd0,pad_r} = stride_7x[7:0]) + flush_num_cal = 3'd7; +end +//small input detect +assign small_active = ((~(|reg2dp_cube_in_height[12:3])) & ((reg2dp_cube_in_height[2:0] + reg2dp_pad_top[2:0]) < {1'b0,reg2dp_kernel_height[2:0]})); +//non-split mode cube_width + pad_left + pad_right +assign h_pt[3:0] = reg2dp_cube_in_height[2:0] + reg2dp_pad_top[2:0]; +assign h_pt_pb[4:0] = h_pt[3:0] + {1'b0,pad_r}; +//pad_right remain afrer 1st kernel pooling +always @( + small_active + or h_pt_pb + or reg2dp_kernel_height + ) begin + if(small_active) + pad_r_remain[5:0] = h_pt_pb[4:0] - {2'd0,reg2dp_kernel_height[2:0]} ; + else + pad_r_remain[5:0] = 6'd0 ; +end +//how many need bubble after 1st kernel pooling +always @( + pad_r_remain + or stride_6x + or stride_5x + or stride_4x + or stride_3x + or stride_2x + or stride_1x + ) begin + if({2'd0,pad_r_remain} == stride_6x[7:0]) + samllH_flush_num = 3'd6; + else if({2'd0,pad_r_remain} == stride_5x[7:0]) + samllH_flush_num = 3'd5; + else if({1'b0,pad_r_remain} == stride_4x[6:0]) + samllH_flush_num = 3'd4; + else if({1'b0,pad_r_remain} == stride_3x[6:0]) + samllH_flush_num = 3'd3; + else if(pad_r_remain == stride_2x[5:0]) + samllH_flush_num = 3'd2; + else if(pad_r_remain == {1'b0,stride_1x[4:0]}) + samllH_flush_num = 3'd1; + else// if(pad_r_remain == 8'd0) + samllH_flush_num = 3'd0; +end +//flush num calc +always @( + flush_num_cal + or small_active + or samllH_flush_num + ) begin + if(flush_num_cal==3'd0) + flush_num[2:0] = 3'd0; + else if(small_active) + flush_num[2:0] = samllH_flush_num; + else + flush_num[2:0] = flush_num_cal[2:0]; +end +assign need_flush = (flush_num != 3'd0); +assign stride_1x[4:0] = stride[4:0]; +assign stride_2x[5:0] = {stride[4:0],1'b0}; +assign stride_3x[6:0] = ( stride_2x+{1'b0,stride[4:0]}); +assign stride_4x[6:0] = {stride[4:0],2'b0}; +assign stride_5x[7:0] = ( stride_4x+{2'd0,stride[4:0]}); +assign stride_6x[7:0] = ( stride_3x+stride_3x); +assign stride_7x[7:0] = ( stride_4x+stride_3x); +//the 1st element/line num need output data +//assign {mon_first_out_num[0],first_out_num[3:0]} = small_active ? {2'd0,reg2dp_cube_in_height[2:0]} : (pooling_size - pad_l); +assign cube_in_height_cfg[3:0] = reg2dp_cube_in_height[2:0] + 3'd1; +assign {mon_first_out_num[0],first_out_num[3:0]} = small_active ? {1'd0,cube_in_height_cfg[3:0]} : (pooling_size - pad_l); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + need_bubble <= 1'b0; + bubble_num_use[2:0] <= {3{1'b0}}; + end else begin +//if(wr_total_cube_done) begin + if(wr_subcube_dat_done) begin + if(need_flush) begin + need_bubble <= 1'b1; + bubble_num_use[2:0] <= flush_num; + end else begin + need_bubble <= 1'b0; + bubble_num_use[2:0] <= 3'd0; + end + end else if(last_line_in) begin + if({1'b0,flush_num} >= first_out_num) begin + need_bubble <= 1'b1; + bubble_num_use[2:0] <= flush_num - first_out_num[2:0] + 1'b1 + bubble_add; + end else if(|bubble_add) begin + need_bubble <= 1'b1; + bubble_num_use[2:0] <= bubble_add; + end else begin + need_bubble <= 1'b0; + bubble_num_use[2:0] <= 3'd0; + end + end + end +end +/////////////////////////////////////////////////////////////////////// +//bubble control when next surface comming . Beginning +/////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_num[2:0] <= {3{1'b0}}; + end else begin + if(pdp_op_start) begin + if({1'b0,flush_num} >= first_out_num) begin + bubble_num[2:0] <= flush_num - first_out_num[2:0] + 1'b1; + end else begin + bubble_num[2:0] <= 3'd0; + end + end + end +end +assign {mon_flush_in_next_surf,flush_in_next_surf[2:0]} = flush_num[2:0] - bubble_num[2:0]; +/////////////// +always @( + flush_in_next_surf + or bubble_num + or pnum_flush1 + or pnum_flush0 + or pnum_flush2 + or pnum_flush3 + or pnum_flush4 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd2) begin + if(bubble_num == 3'd0) begin + next2_1 = pnum_flush1; + next2_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next2_1 = pnum_flush2; + next2_0 = pnum_flush1; + end else if(bubble_num == 3'd2) begin + next2_1 = pnum_flush3; + next2_0 = pnum_flush2; + end else if(bubble_num == 3'd3) begin + next2_1 = pnum_flush4; + next2_0 = pnum_flush3; + end else if(bubble_num == 3'd4) begin + next2_1 = pnum_flush5; + next2_0 = pnum_flush4; + end else begin// else if(bubble_num == 3'd4) begin + next2_1 = pnum_flush6; + next2_0 = pnum_flush5; + end + end else begin + next2_1 = 3'd0; + next2_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush3 + or pnum_flush4 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd3) begin + if(bubble_num == 3'd0) begin + next3_2 = pnum_flush2; + next3_1 = pnum_flush1; + next3_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next3_2 = pnum_flush3; + next3_1 = pnum_flush2; + next3_0 = pnum_flush1; + end else if(bubble_num == 3'd2) begin + next3_2 = pnum_flush4; + next3_1 = pnum_flush3; + next3_0 = pnum_flush2; + end else if(bubble_num == 3'd3) begin + next3_2 = pnum_flush5; + next3_1 = pnum_flush4; + next3_0 = pnum_flush3; + end else begin// else if(bubble_num == 3'd4) begin + next3_2 = pnum_flush6; + next3_1 = pnum_flush5; + next3_0 = pnum_flush4; + end + end else begin + next3_2 = 3'd0; + next3_1 = 3'd0; + next3_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush4 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd4) begin + if(bubble_num == 3'd0) begin + next4_3 = pnum_flush3; + next4_2 = pnum_flush2; + next4_1 = pnum_flush1; + next4_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next4_3 = pnum_flush4; + next4_2 = pnum_flush3; + next4_1 = pnum_flush2; + next4_0 = pnum_flush1; + end else if(bubble_num == 3'd2) begin + next4_3 = pnum_flush5; + next4_2 = pnum_flush4; + next4_1 = pnum_flush3; + next4_0 = pnum_flush2; + end else begin//else if(bubble_num == 3'd3) begin + next4_3 = pnum_flush6; + next4_2 = pnum_flush5; + next4_1 = pnum_flush4; + next4_0 = pnum_flush3; + end + end else begin + next4_3 = 3'd0; + next4_2 = 3'd0; + next4_1 = 3'd0; + next4_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush4 + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush5 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd5) begin + if(bubble_num == 3'd0) begin + next5_4 = pnum_flush4; + next5_3 = pnum_flush3; + next5_2 = pnum_flush2; + next5_1 = pnum_flush1; + next5_0 = pnum_flush0; + end else if(bubble_num == 3'd1) begin + next5_4 = pnum_flush5; + next5_3 = pnum_flush4; + next5_2 = pnum_flush3; + next5_1 = pnum_flush2; + next5_0 = pnum_flush1; + end else begin //else if(bubble_num == 3'd2) begin + next5_4 = pnum_flush6; + next5_3 = pnum_flush5; + next5_2 = pnum_flush4; + next5_1 = pnum_flush3; + next5_0 = pnum_flush2; + end + end else begin + next5_4 = 3'd0; + next5_3 = 3'd0; + next5_2 = 3'd0; + next5_1 = 3'd0; + next5_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or bubble_num + or pnum_flush5 + or pnum_flush4 + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + or pnum_flush6 + ) begin + if(flush_in_next_surf == 4'd6) begin + if(bubble_num == 3'd0) begin + next6_5 = pnum_flush5; + next6_4 = pnum_flush4; + next6_3 = pnum_flush3; + next6_2 = pnum_flush2; + next6_1 = pnum_flush1; + next6_0 = pnum_flush0; + end else begin//else if(bubble_num == 3'd1) begin + next6_5 = pnum_flush6; + next6_4 = pnum_flush5; + next6_3 = pnum_flush4; + next6_2 = pnum_flush3; + next6_1 = pnum_flush2; + next6_0 = pnum_flush1; + end + end else begin + next6_5 = 3'd0; + next6_4 = 3'd0; + next6_3 = 3'd0; + next6_2 = 3'd0; + next6_1 = 3'd0; + next6_0 = 3'd0; + end +end +always @( + flush_in_next_surf + or pnum_flush6 + or pnum_flush5 + or pnum_flush4 + or pnum_flush3 + or pnum_flush2 + or pnum_flush1 + or pnum_flush0 + ) begin + if(flush_in_next_surf == 4'd7) begin + next7_6 = pnum_flush6; + next7_5 = pnum_flush5; + next7_4 = pnum_flush4; + next7_3 = pnum_flush3; + next7_2 = pnum_flush2; + next7_1 = pnum_flush1; + next7_0 = pnum_flush0; + end else begin + next7_6 = 3'd0; + next7_5 = 3'd0; + next7_4 = 3'd0; + next7_3 = 3'd0; + next7_2 = 3'd0; + next7_1 = 3'd0; + next7_0 = 3'd0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_add <= {3{1'b0}}; + end else begin + if(flush_in_next_surf == 4'd2) begin + if((up_pnum0 == next2_1)|({2'd0,up_pnum1} == next2_1)|({1'b0,up_pnum2} == next2_1)|({1'b0,up_pnum3} == next2_1)|(up_pnum4 == next2_1)|(up_pnum5 == next2_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next2_0)|({2'd0,up_pnum1} == next2_0)|({1'b0,up_pnum2} == next2_0)|({1'b0,up_pnum3} == next2_0)|(up_pnum4 == next2_0)|(up_pnum5 == next2_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd3) begin + if( (up_pnum0 == next3_2)|({2'd0,up_pnum1} == next3_2)|({1'b0,up_pnum2} == next3_2)|({1'b0,up_pnum3} == next3_2)|(up_pnum4 == next3_2)|(up_pnum5 == next3_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next3_1)|({2'd0,up_pnum1} == next3_1)|({1'b0,up_pnum2} == next3_1)|({1'b0,up_pnum3} == next3_1)|(up_pnum4 == next3_1)|(up_pnum5 == next3_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next3_0)|({2'd0,up_pnum1} == next3_0)|({1'b0,up_pnum2} == next3_0)|({1'b0,up_pnum3} == next3_0)|(up_pnum4 == next3_0)|(up_pnum5 == next3_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd4) begin + if( (up_pnum0 == next4_3)|({2'd0,up_pnum1} == next4_3)|({1'b0,up_pnum2} == next4_3)|({1'b0,up_pnum3} == next4_3)|(up_pnum4 == next4_3)|(up_pnum5 == next4_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next4_2)|({2'd0,up_pnum1} == next4_2)|({1'b0,up_pnum2} == next4_2)|({1'b0,up_pnum3} == next4_2)|(up_pnum4 == next4_2)|(up_pnum5 == next4_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next4_1)|({2'd0,up_pnum1} == next4_1)|({1'b0,up_pnum2} == next4_1)|({1'b0,up_pnum3} == next4_1)|(up_pnum4 == next4_1)|(up_pnum5 == next4_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next4_0)|({2'd0,up_pnum1} == next4_0)|({1'b0,up_pnum2} == next4_0)|({1'b0,up_pnum3} == next4_0)|(up_pnum4 == next4_0)|(up_pnum5 == next4_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd5) begin + if( (up_pnum0 == next5_4)|({2'd0,up_pnum1} == next5_4)|({1'b0,up_pnum2} == next5_4)|({1'b0,up_pnum3} == next5_4)|(up_pnum4 == next5_4)|(up_pnum5 == next5_4)) + bubble_add <= 3'd5; + else if((up_pnum0 == next5_3)|({2'd0,up_pnum1} == next5_3)|({1'b0,up_pnum2} == next5_3)|({1'b0,up_pnum3} == next5_3)|(up_pnum4 == next5_3)|(up_pnum5 == next5_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next5_2)|({2'd0,up_pnum1} == next5_2)|({1'b0,up_pnum2} == next5_2)|({1'b0,up_pnum3} == next5_2)|(up_pnum4 == next5_2)|(up_pnum5 == next5_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next5_1)|({2'd0,up_pnum1} == next5_1)|({1'b0,up_pnum2} == next5_1)|({1'b0,up_pnum3} == next5_1)|(up_pnum4 == next5_1)|(up_pnum5 == next5_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next5_0)|({2'd0,up_pnum1} == next5_0)|({1'b0,up_pnum2} == next5_0)|({1'b0,up_pnum3} == next5_0)|(up_pnum4 == next5_0)|(up_pnum5 == next5_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd6) begin + if( (up_pnum0 == next6_5)|({2'd0,up_pnum1} == next6_5)|({1'b0,up_pnum2} == next6_5)|({1'b0,up_pnum3} == next6_5)|(up_pnum4 == next6_5)|(up_pnum5 == next6_5)) + bubble_add <= 3'd6; + else if((up_pnum0 == next6_4)|({2'd0,up_pnum1} == next6_4)|({1'b0,up_pnum2} == next6_4)|({1'b0,up_pnum3} == next6_4)|(up_pnum4 == next6_4)|(up_pnum5 == next6_4)) + bubble_add <= 3'd5; + else if((up_pnum0 == next6_3)|({2'd0,up_pnum1} == next6_3)|({1'b0,up_pnum2} == next6_3)|({1'b0,up_pnum3} == next6_3)|(up_pnum4 == next6_3)|(up_pnum5 == next6_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next6_2)|({2'd0,up_pnum1} == next6_2)|({1'b0,up_pnum2} == next6_2)|({1'b0,up_pnum3} == next6_2)|(up_pnum4 == next6_2)|(up_pnum5 == next6_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next6_1)|({2'd0,up_pnum1} == next6_1)|({1'b0,up_pnum2} == next6_1)|({1'b0,up_pnum3} == next6_1)|(up_pnum4 == next6_1)|(up_pnum5 == next6_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next6_0)|({2'd0,up_pnum1} == next6_0)|({1'b0,up_pnum2} == next6_0)|({1'b0,up_pnum3} == next6_0)|(up_pnum4 == next6_0)|(up_pnum5 == next6_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else if(flush_in_next_surf == 4'd7) begin + if( (up_pnum0 == next7_6)|({2'd0,up_pnum1} == next7_6)|({1'b0,up_pnum2} == next7_6)|({1'b0,up_pnum3} == next7_6)|(up_pnum4 == next7_6)|(up_pnum5 == next7_6)) + bubble_add <= 3'd7; + else if((up_pnum0 == next7_5)|({2'd0,up_pnum1} == next7_5)|({1'b0,up_pnum2} == next7_5)|({1'b0,up_pnum3} == next7_5)|(up_pnum4 == next7_5)|(up_pnum5 == next7_5)) + bubble_add <= 3'd6; + else if((up_pnum0 == next7_4)|({2'd0,up_pnum1} == next7_4)|({1'b0,up_pnum2} == next7_4)|({1'b0,up_pnum3} == next7_4)|(up_pnum4 == next7_4)|(up_pnum5 == next7_4)) + bubble_add <= 3'd5; + else if((up_pnum0 == next7_3)|({2'd0,up_pnum1} == next7_3)|({1'b0,up_pnum2} == next7_3)|({1'b0,up_pnum3} == next7_3)|(up_pnum4 == next7_3)|(up_pnum5 == next7_3)) + bubble_add <= 3'd4; + else if((up_pnum0 == next7_2)|({2'd0,up_pnum1} == next7_2)|({1'b0,up_pnum2} == next7_2)|({1'b0,up_pnum3} == next7_2)|(up_pnum4 == next7_2)|(up_pnum5 == next7_2)) + bubble_add <= 3'd3; + else if((up_pnum0 == next7_1)|({2'd0,up_pnum1} == next7_1)|({1'b0,up_pnum2} == next7_1)|({1'b0,up_pnum3} == next7_1)|(up_pnum4 == next7_1)|(up_pnum5 == next7_1)) + bubble_add <= 3'd2; + else if((up_pnum0 == next7_0)|({2'd0,up_pnum1} == next7_0)|({1'b0,up_pnum2} == next7_0)|({1'b0,up_pnum3} == next7_0)|(up_pnum4 == next7_0)|(up_pnum5 == next7_0)) + bubble_add <= 3'd1; + else + bubble_add <= 3'd0; + end else begin + bubble_add <= 3'd0; + end + end +end +//------------------------- +assign unit2d_cnt_pooling_a1[3:0] = unit2d_cnt_pooling[2:0] + 3'd1; +assign unit2d_cnt_pooling_a2[3:0] = unit2d_cnt_pooling[2:0] + 3'd2; +assign unit2d_cnt_pooling_a3[3:0] = unit2d_cnt_pooling[2:0] + 3'd3; +assign unit2d_cnt_pooling_a4[3:0] = unit2d_cnt_pooling[2:0] + 3'd4; +assign unit2d_cnt_pooling_a5[3:0] = unit2d_cnt_pooling[2:0] + 3'd5; +assign unit2d_cnt_pooling_a6[3:0] = unit2d_cnt_pooling[2:0] + 3'd6; +assign unit2d_cnt_pooling_a7[3:0] = unit2d_cnt_pooling[2:0] + 3'd7; +//pooling No. in flush time +always @(posedge nvdla_core_clk) begin +//if(wr_surface_dat_done) begin + if(last_line_in) begin + if(unit2d_cnt_pooling[2:0] == unit2d_cnt_pooling_max) begin + pnum_flush0 <= 3'd0; + pnum_flush1 <= 3'd1; + pnum_flush2 <= 3'd2; + pnum_flush3 <= 3'd3; + pnum_flush4 <= 3'd4; + pnum_flush5 <= 3'd5; + pnum_flush6 <= 3'd6; + end else if(unit2d_cnt_pooling_a1 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling_max; + pnum_flush1 <= 3'd0; + pnum_flush2 <= 3'd1; + pnum_flush3 <= 3'd2; + pnum_flush4 <= 3'd3; + pnum_flush5 <= 3'd4; + pnum_flush6 <= 3'd5; + end else if(unit2d_cnt_pooling_a2 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'b1; + pnum_flush1 <= unit2d_cnt_pooling_max; + pnum_flush2 <= 3'd0; + pnum_flush3 <= 3'd1; + pnum_flush4 <= 3'd2; + pnum_flush5 <= 3'd3; + pnum_flush6 <= 3'd4; + end else if(unit2d_cnt_pooling_a3 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling_max; + pnum_flush3 <= 3'd0; + pnum_flush4 <= 3'd1; + pnum_flush5 <= 3'd2; + pnum_flush6 <= 3'd3; + end else if(unit2d_cnt_pooling_a4 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling_max; + pnum_flush4 <= 3'd0; + pnum_flush5 <= 3'd1; + pnum_flush6 <= 3'd2; + end else if(unit2d_cnt_pooling_a5 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling + 3'd4; + pnum_flush4 <= unit2d_cnt_pooling_max; + pnum_flush5 <= 3'd0; + pnum_flush6 <= 3'd1; + end else if(unit2d_cnt_pooling_a6 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling + 3'd4; + pnum_flush4 <= unit2d_cnt_pooling + 3'd5; + pnum_flush5 <= unit2d_cnt_pooling_max; + pnum_flush6 <= 3'd0; + end else if(unit2d_cnt_pooling_a7 == {1'b0,unit2d_cnt_pooling_max}) begin + pnum_flush0 <= unit2d_cnt_pooling + 1'd1; + pnum_flush1 <= unit2d_cnt_pooling + 2'd2; + pnum_flush2 <= unit2d_cnt_pooling + 2'd3; + pnum_flush3 <= unit2d_cnt_pooling + 3'd4; + pnum_flush4 <= unit2d_cnt_pooling + 3'd5; + pnum_flush5 <= unit2d_cnt_pooling + 3'd6; + pnum_flush6 <= unit2d_cnt_pooling_max; + end + end +end +//------------------------- +//update pooling No. in line2 of next surface +//------------------------- +assign up_pnum0 = 3'd0; +always @(posedge nvdla_core_clk) begin + if(padding_v_cfg[2:0] == 3'd0) begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if(padding_v_cfg[2:0] == 3'd1) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd2) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if(stride[4:0]==5'd2) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd3) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd3; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if((stride[4:0]==5'd2)|(stride[4:0]==5'd3)) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd4) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd3; + up_pnum4 <= 3'd4; + up_pnum5 <= 3'd0; + end else if(stride[4:0]==5'd2) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if((stride[4:0]==5'd3)|(stride[4:0]==5'd4)) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end else if(padding_v_cfg[2:0] == 3'd5) begin + if(stride[4:0]==5'd1) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd3; + up_pnum4 <= 3'd4; + up_pnum5 <= 3'd5; + end else if(stride[4:0]==5'd2) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd2; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else if((stride[4:0]==5'd3)|(stride[4:0]==5'd4)|(stride[4:0]==5'd5)) begin + up_pnum1 <= 1'd1; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end else begin + up_pnum1 <= 1'd0; + up_pnum2 <= 2'd0; + up_pnum3 <= 2'd0; + up_pnum4 <= 3'd0; + up_pnum5 <= 3'd0; + end + end +end +/////////////////////////////////////////////////////////////////////// +//bubble control when next surface comming . Ending +/////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + subend_need_flush_flg <= 1'b0; + end else begin + if(wr_subcube_dat_done & need_flush & is_one_width_in) + subend_need_flush_flg <= 1'b1; + else if(one_width_bubble_end) + subend_need_flush_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surfend_need_bubble_flg <= 1'b0; + end else begin + if(wr_surface_dat_done & need_bubble & is_one_width_in) + surfend_need_bubble_flg <= 1'b1; + else if(one_width_bubble_end) + surfend_need_bubble_flg <= 1'b0; + end +end +///////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable <= 1'b0; + end else begin + if((wr_subcube_dat_done & need_flush & (~is_one_width_in)) | (subend_need_flush_flg & one_width_bubble_end)) + cur_datin_disable <= 1'b1; + else if((wr_surface_dat_done & need_bubble & (~is_one_width_in)) | (surfend_need_bubble_flg & one_width_bubble_end)) + cur_datin_disable <= 1'b1; + else if(bubble_en_end) + cur_datin_disable <= 1'b0; + end +end +///////////////////////////////////////// +//&Always posedge; +// if(wr_subcube_dat_done & need_flush) +// cur_datin_disable <0= 1'b1; +// else if(wr_surface_dat_done & need_bubble) +// cur_datin_disable <0= 1'b1; +// else if(bubble_en_end) +// cur_datin_disable <0= 1'b0; +//&End; +/////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_width_cur_latch <= {13{1'b0}}; + end else begin + if((wr_subcube_dat_done & need_flush) || (wr_surface_dat_done & need_bubble)) + pout_width_cur_latch <= pout_width_cur; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + channel_cnt <= 0; + end else begin + if(cur_datin_disable) begin + if(last_c) + channel_cnt <= 0; + else if(one_width_norm_rdy) + channel_cnt <= channel_cnt + 1'b1; + end else + channel_cnt <= 0; + end +end +//: my $m = 8; +//: my $k = 1; +//: my $j = int($m / $k); +//: print "assign last_c = (channel_cnt==5'd${j}-1) & one_width_norm_rdy; \n"; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_cnt <= {13{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(line_end) + line_cnt <= 13'd0; + else if(last_c) + line_cnt <= line_cnt + 1'b1; + end else + line_cnt <= 13'd0; + end +end +assign line_end = (line_cnt==pout_width_cur_latch) & last_c; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bubble_cnt <= {3{1'b0}}; + end else begin + if(cur_datin_disable) begin + if(bubble_en_end) + bubble_cnt <= 3'd0; + else if(line_end) + bubble_cnt <= bubble_cnt + 1'b1; + end else + bubble_cnt <= 3'd0; + end +end +assign bubble_en_end = (bubble_cnt == bubble_num_dec) & line_end; +assign bubble_num_dec[2:0] = (bubble_num_use-1'b1); +////////////////////////////////////////////////////// +//last lines output en during new lines comming +//---------------------------------------------------- +//cube end flag for last_out_en control in the cube end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cube_end_flag <= 1'b0; + end else begin + if(wr_subcube_dat_done) + cube_end_flag <= 1'b1; + else if(load_din) + cube_end_flag <= 1'b0; + end +end +//assign {mon_first_out_num_dec1[1:0],first_out_num_dec1[2:0]} = first_out_num - 4'd1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_en <= 1'b0; + end else begin + if(first_out_num != 3'd1) begin + if((need_bubble & bubble_en_end & (~cube_end_flag) & (bubble_add < flush_in_next_surf)) | (~need_bubble & need_flush & wr_surface_dat_done & (~wr_subcube_dat_done))) + last_out_en <= 1'b1; + else if(last_out_done) + last_out_en <= 1'b0; + end else + last_out_en <= 1'b0; + end +end +assign first_out_num_dec2[2:0] = flush_num - bubble_num_use - 1'b1;//first_out_num - 2'd2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_out_cnt <= {3{1'b0}}; + end else begin + if(last_out_en) begin + if(wr_line_dat_done) begin + if(((last_out_cnt == first_out_num_dec2) & need_bubble) | (~need_bubble & (last_out_cnt == flush_num_dec1))) + last_out_cnt <= 3'd0; + else + last_out_cnt <= last_out_cnt + 1'b1; + end + end else + last_out_cnt <= 3'd0; + end +end +assign {mon_flush_num_dec1,flush_num_dec1[2:0]} = flush_num - 3'd1; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP cal2d datin_disable: no overflow is allowed") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, mon_flush_num_dec1 & wr_line_dat_done & last_out_en); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign last_out_done = (((last_out_cnt == first_out_num_dec2) & need_bubble) | (~need_bubble & (last_out_cnt == flush_num_dec1))) & wr_line_dat_done & last_out_en; +/////////////////////////////////////////////////////////////////////// +//bubble control when input width is only 1 element in width +/////////////////////////////////////////////////////////////////////// +always @( + splitw_enable + or reg2dp_cube_out_width + or first_splitw + or reg2dp_partial_width_out_first + or last_splitw + or reg2dp_partial_width_out_last + or pooling_splitw_num_cfg + or reg2dp_partial_width_out_mid + ) begin + if(~splitw_enable) + is_one_width_in = (reg2dp_cube_out_width[12:0] == 13'd0); + else if(first_splitw) + is_one_width_in = (reg2dp_partial_width_out_first[9:0] == 10'd0); + else if(last_splitw) + is_one_width_in = (reg2dp_partial_width_out_last[9:0] == 10'd0); + else + is_one_width_in = (pooling_splitw_num_cfg > 8'd1)? (reg2dp_partial_width_out_mid[9:0] == 10'd0) : 1'b0; +end +///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable <= 1'b0; + end else begin + if(wr_line_dat_done & is_one_width_in) + one_width_disable <= 1'b1; + else if(one_width_bubble_end) + one_width_disable <= 1'b0; + end +end +///////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_bubble_cnt <= {3{1'b0}}; + end else begin + if(one_width_disable) begin + if(one_width_bubble_end) + one_width_bubble_cnt <= 3'd0; + else if(pooling1d_norm_rdy) + one_width_bubble_cnt <= one_width_bubble_cnt + 1'b1; + end else + one_width_bubble_cnt <= 3'd0; + end +end +assign one_width_bubble_end = (one_width_bubble_cnt == (4 -2'd2)) & pooling1d_norm_rdy; +////////////////////////////////////////////////////// +assign pooling_2d_rdy = wr_line_dat_done & (strip_ycnt_psize ==pooling_size_v_cfg[2:0]) ; +//===================================================================== +//pooling 2D unit counter +// +//--------------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_stride[2:0] <= {3{1'b0}}; + end else begin + if(init_cnt) + unit2d_cnt_stride[2:0] <= padding_stride_num; + else if(stride_end) begin + if(stride_trig_end) + unit2d_cnt_stride[2:0] <= 3'd0; + else + unit2d_cnt_stride[2:0] <= unit2d_cnt_stride + 1; + end + end +end +assign stride_trig_end = (unit2d_cnt_pooling_max==unit2d_cnt_stride); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling <= {3{1'b0}}; + end else begin + if(init_cnt) + unit2d_cnt_pooling <= 3'd0; + else if(pooling_2d_rdy | wr_surface_dat_done) begin + if(unit2d_cnt_pooling_end) + unit2d_cnt_pooling <= 3'd0; + else + unit2d_cnt_pooling[2:0] <= unit2d_cnt_pooling + 1; + end + end +end +assign unit2d_cnt_pooling_end = (unit2d_cnt_pooling == unit2d_cnt_pooling_max); +assign {mon_unit2d_cnt_pooling_max[1:0],unit2d_cnt_pooling_max[2:0]} = buffer_lines_num - 4'd1; +//------------------------- +//flag the last one pooling in height direction +//------------------------- +assign {mon_rest_height,rest_height[12:0]} = reg2dp_cube_in_height - wr_surface_dat_cnt; +assign rest_height_use[13:0] = rest_height + {10'd0,reg2dp_pad_bottom_cfg}; +assign last_pooling_flag = rest_height_use[13:0] <= {11'd0,pooling_size_v_cfg}; +//====================================================================== +//unit2d pooling enable +//: foreach my $i (0..7) { +//: my $j=$i-1; +//: print "assign init_unit2d_set[$i] = init_cnt & (padding_stride_num>=${i}); \n"; +//: if($i == 0) { +//: print "assign unit2d_set_trig[${i}] = stride_end & stride_trig_end & (~last_pooling_flag);\n"; +//: } else { +//: print "assign unit2d_set_trig[${i}] = stride_end & (unit2d_cnt_stride == 3'd${j}) & (~stride_trig_end) & (~last_pooling_flag);\n"; +//: } +//: print qq( +//: assign unit2d_set[${i}] = unit2d_set_trig[${i}] | init_unit2d_set[${i}]; +//: assign unit2d_clr[${i}] = (pooling_2d_rdy & (unit2d_cnt_pooling == 3'd${i})) | wr_surface_dat_done; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: unit2d_en[$i] <= 1'b0; +//: else if(wr_total_cube_done) +//: unit2d_en[$i] <= 1'b0; +//: else if(unit2d_set[${i}]) +//: unit2d_en[$i] <= 1'b1; +//: else if(unit2d_clr[${i}]) +//: unit2d_en[$i] <= 1'b0; +//: end +//: ); +//: } +/////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_buf <= 0; + end else begin + if ((load_din) == 1'b1) begin + datin_buf <= pooling1d_pd_use; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_end_buf <= 1'b0; + end else begin + if ((load_din) == 1'b1) begin + wr_line_end_buf <= wr_line_dat_done; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_done_buf <= 1'b0; + end else begin + if ((load_din) == 1'b1) begin + wr_surface_dat_done_buf <= wr_surface_dat_done; + end + end +end +////////////////////////////////////////////////////////////////////// +//calculate the real pooling size within one poooling +//PerBeg +//: foreach my $i (0..7){ +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: unit2d_vsize_cnt_$i <= {3{1'b0}}; +//: else if(unit2d_set[$i]) +//: unit2d_vsize_cnt_${i}[2:0] <= 3'd0; +//: else if(unit2d_en[$i] & wr_line_dat_done) +//: unit2d_vsize_cnt_${i}[2:0] <= unit2d_vsize_cnt_${i}[2:0] + 3'd1; +//: end +//: ); +//: } +//line buffer number 1 +assign unit2d_vsize1_0 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_1 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_2 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_3 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_4 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_5 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_6 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize1_7 = mem_re1_sel? unit2d_vsize_cnt_0 : 3'd0; +//line buffer number 2 +assign unit2d_vsize2_0 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_1 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_2 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_3 = mem_re2_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize2_4 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize2_5 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize2_6 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize2_7 = mem_re2_sel? unit2d_vsize_cnt_1 : 3'd0; +//line buffer number 3 4 +assign unit2d_vsize3_0 = mem_re3_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize3_1 = mem_re3_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize3_2 = mem_re3_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize3_3 = mem_re3_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize3_4 = mem_re3_sel? unit2d_vsize_cnt_2 : 3'd0; +assign unit2d_vsize3_5 = mem_re3_sel? unit2d_vsize_cnt_2 : 3'd0; +assign unit2d_vsize3_6 = mem_re3_sel? unit2d_vsize_cnt_3 : 3'd0; +assign unit2d_vsize3_7 = mem_re3_sel? unit2d_vsize_cnt_3 : 3'd0; +//line buffer 5 6 7 8 +assign unit2d_vsize4_0 = mem_re4_sel? unit2d_vsize_cnt_0 : 3'd0; +assign unit2d_vsize4_1 = mem_re4_sel? unit2d_vsize_cnt_1 : 3'd0; +assign unit2d_vsize4_2 = mem_re4_sel? unit2d_vsize_cnt_2 : 3'd0; +assign unit2d_vsize4_3 = mem_re4_sel? unit2d_vsize_cnt_3 : 3'd0; +assign unit2d_vsize4_4 = mem_re4_sel? unit2d_vsize_cnt_4 : 3'd0; +assign unit2d_vsize4_5 = mem_re4_sel? unit2d_vsize_cnt_5 : 3'd0; +assign unit2d_vsize4_6 = mem_re4_sel? unit2d_vsize_cnt_6 : 3'd0; +assign unit2d_vsize4_7 = mem_re4_sel? unit2d_vsize_cnt_7 : 3'd0; +assign unit2d_vsize_0 = unit2d_vsize1_0 | unit2d_vsize2_0 | unit2d_vsize3_0 | unit2d_vsize4_0; +assign unit2d_vsize_1 = unit2d_vsize1_1 | unit2d_vsize2_1 | unit2d_vsize3_1 | unit2d_vsize4_1; +assign unit2d_vsize_2 = unit2d_vsize1_2 | unit2d_vsize2_2 | unit2d_vsize3_2 | unit2d_vsize4_2; +assign unit2d_vsize_3 = unit2d_vsize1_3 | unit2d_vsize2_3 | unit2d_vsize3_3 | unit2d_vsize4_3; +assign unit2d_vsize_4 = unit2d_vsize1_4 | unit2d_vsize2_4 | unit2d_vsize3_4 | unit2d_vsize4_4; +assign unit2d_vsize_5 = unit2d_vsize1_5 | unit2d_vsize2_5 | unit2d_vsize3_5 | unit2d_vsize4_5; +assign unit2d_vsize_6 = unit2d_vsize1_6 | unit2d_vsize2_6 | unit2d_vsize3_6 | unit2d_vsize4_6; +assign unit2d_vsize_7 = unit2d_vsize1_7 | unit2d_vsize2_7 | unit2d_vsize3_7 | unit2d_vsize4_7; +//: foreach my $i (0..7) { +//: print qq( +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: unit2d_vsize_cnt_${i}_d <= {3{1'b0}}; +//: else if (load_din) +//: unit2d_vsize_cnt_${i}_d <= unit2d_vsize_$i; +//: end +//: ); +//: } +//============================================================ +assign active_last_line = (strip_ycnt_psize == pooling_size_v_cfg) | last_line_in; +//============================================================ +//memory bank read/write controller +// +//------------------------------------------------------------ +//memory read +//mem bank0 enable +// +//memory first read +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[0] <= 1'b0; + end else begin + unit2d_mem_1strd[0] <= unit2d_set[0] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[0]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[1] <= 1'b0; + end else begin + unit2d_mem_1strd[1] <= unit2d_set[1] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[1]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[2] <= 1'b0; + end else begin + unit2d_mem_1strd[2] <= unit2d_set[2] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[2]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[3] <= 1'b0; + end else begin + unit2d_mem_1strd[3] <= unit2d_set[3] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[3]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[4] <= 1'b0; + end else begin + unit2d_mem_1strd[4] <= unit2d_set[4] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[4]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[5] <= 1'b0; + end else begin + unit2d_mem_1strd[5] <= unit2d_set[5] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[5]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[6] <= 1'b0; + end else begin + unit2d_mem_1strd[6] <= unit2d_set[6] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[6]); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_mem_1strd[7] <= 1'b0; + end else begin + unit2d_mem_1strd[7] <= unit2d_set[7] ? 1'b1 : (wr_line_dat_done ? 1'b0 : unit2d_mem_1strd[7]); + end +end +//line buffer number 1 +assign mem_re1[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re1_sel; +assign mem_re1[1] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re1_sel; +assign mem_re1[2] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd2) & mem_re1_sel; +assign mem_re1[3] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd3) & mem_re1_sel; +assign mem_re1[4] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd4) & mem_re1_sel; +assign mem_re1[5] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd5) & mem_re1_sel; +assign mem_re1[6] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd6) & mem_re1_sel; +assign mem_re1[7] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd7) & mem_re1_sel; +assign mem_re1_1st[0] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[1] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[2] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[3] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[4] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[5] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[6] = unit2d_mem_1strd[0] & mem_re1_sel; +assign mem_re1_1st[7] = unit2d_mem_1strd[0] & mem_re1_sel; +//line buffer number 2 +//4 bank read enable +//mem_read +assign mem_re2[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel; +assign mem_re2[1] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel; +assign mem_re2[2] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel; +assign mem_re2[3] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel; +assign mem_re2[4] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel; +assign mem_re2[5] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel; +assign mem_re2[6] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel; +assign mem_re2[7] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel; +assign mem_re2_1st[0] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[1] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[2] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[3] = unit2d_mem_1strd[0] & mem_re2_sel; +assign mem_re2_1st[4] = unit2d_mem_1strd[1] & mem_re2_sel; +assign mem_re2_1st[5] = unit2d_mem_1strd[1] & mem_re2_sel; +assign mem_re2_1st[6] = unit2d_mem_1strd[1] & mem_re2_sel; +assign mem_re2_1st[7] = unit2d_mem_1strd[1] & mem_re2_sel; +//line buffer number 3 4 +assign mem_re3[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[1] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3[2] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[3] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3[4] = unit2d_en[2] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[5] = unit2d_en[2] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3[6] = unit2d_en[3] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel; +assign mem_re3[7] = unit2d_en[3] & load_din & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel; +assign mem_re3_1st[0] = unit2d_mem_1strd[0] & mem_re3_sel; +assign mem_re3_1st[1] = unit2d_mem_1strd[0] & mem_re3_sel; +assign mem_re3_1st[2] = unit2d_mem_1strd[1] & mem_re3_sel; +assign mem_re3_1st[3] = unit2d_mem_1strd[1] & mem_re3_sel; +assign mem_re3_1st[4] = unit2d_mem_1strd[2] & mem_re3_sel; +assign mem_re3_1st[5] = unit2d_mem_1strd[2] & mem_re3_sel; +assign mem_re3_1st[6] = unit2d_mem_1strd[3] & mem_re3_sel; +assign mem_re3_1st[7] = unit2d_mem_1strd[3] & mem_re3_sel; +//line buffer 5 6 7 8 +assign mem_re4[0] = unit2d_en[0] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[1] = unit2d_en[1] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[2] = unit2d_en[2] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[3] = unit2d_en[3] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[4] = unit2d_en[4] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[5] = unit2d_en[5] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[6] = unit2d_en[6] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4[7] = unit2d_en[7] & load_din & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel; +assign mem_re4_1st[0] = unit2d_mem_1strd[0] & mem_re4_sel; +assign mem_re4_1st[1] = unit2d_mem_1strd[1] & mem_re4_sel; +assign mem_re4_1st[2] = unit2d_mem_1strd[2] & mem_re4_sel; +assign mem_re4_1st[3] = unit2d_mem_1strd[3] & mem_re4_sel; +assign mem_re4_1st[4] = unit2d_mem_1strd[4] & mem_re4_sel; +assign mem_re4_1st[5] = unit2d_mem_1strd[5] & mem_re4_sel; +assign mem_re4_1st[6] = unit2d_mem_1strd[6] & mem_re4_sel; +assign mem_re4_1st[7] = unit2d_mem_1strd[7] & mem_re4_sel; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re1_sel <= 1'b0; + mem_re2_sel <= 1'b0; + mem_re3_sel <= 1'b0; + mem_re4_sel <= 1'b0; + end else begin + mem_re1_sel <= (buffer_lines_num==4'd1); + mem_re2_sel <= (buffer_lines_num==4'd2); + mem_re3_sel <= (buffer_lines_num==4'd3) | (buffer_lines_num==4'd4); + mem_re4_sel <= (buffer_lines_num >=4'd5); + end +end +/////////////////////////// +//shouldn't read data from mem for the first pooling line +/////////////////////////// +assign mem_re = mem_re1 | mem_re2 | mem_re3 | mem_re4; +assign mem_re_1st = mem_re1_1st | mem_re2_1st | mem_re3_1st | mem_re4_1st; +assign mem_raddr = sub_lbuf_dout_cnt; +//line buffer counter +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_sub_lbuf_cnt[2:0] <= {3{1'b0}}; + end else begin + if(wr_line_dat_done | last_sub_lbuf_done | line_end) + wr_sub_lbuf_cnt[2:0] <= 3'd0; + else if(sub_lbuf_dout_done) + wr_sub_lbuf_cnt[2:0] <= wr_sub_lbuf_cnt + 1; + end +end +assign last_sub_lbuf_done = ((bank_merge_num-1) =={2'd0,wr_sub_lbuf_cnt}) & sub_lbuf_dout_done; +//-------------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sub_lbuf_dout_cnt <= {9{1'b0}}; + end else begin + if(sub_lbuf_dout_done | wr_line_dat_done | line_end) + sub_lbuf_dout_cnt <= 9'd0; + else if(load_din | (cur_datin_disable & one_width_norm_rdy)) + sub_lbuf_dout_cnt <= sub_lbuf_dout_cnt+ 1'd1; + end +end +assign sub_lbuf_dout_done = (sub_lbuf_dout_cnt==BANK_DEPTH) & (load_din | (cur_datin_disable & one_width_norm_rdy)); +//============================================================================================== +//buffer the data from memory and from UNIT1D +// +//---------------------------------------------------------------------------------------------- +//========================================================= +//POOLING FUNCTION DEFINITION +// +//---- ----------------------------------------------------- +//: my $m = (8 +6); +//: print qq( +//: function[${m}-1:0] pooling_MIN; +//: input data0_valid; +//: input[${m}-1:0] data0; +//: input[${m}-1:0] data1; +//: ); + reg min_int_ff; + begin + min_int_ff = ($signed(data1)> $signed(data0)) ; + pooling_MIN = (min_int_ff & data0_valid) ? data0 : data1; + end + endfunction +//: my $m = (8 +6); +//: print qq( +//: function[${m}-1:0] pooling_MAX; +//: input data0_valid; +//: input[${m}-1:0] data0; +//: input[${m}-1:0] data1; +//: ); + reg max_int_ff; + begin + max_int_ff = ($signed(data0)> $signed(data1)) ; + pooling_MAX = (max_int_ff & data0_valid) ? data0 : data1; + end + endfunction +//: my $m = (8 +6); +//: print qq( +//: function[${m}-1:0] pooling_SUM; +//: input data0_valid; +//: input[${m}-1:0] data0; +//: input[${m}-1:0] data1; +//: ); + begin +//spyglass disable_block W484 + pooling_SUM = ($signed(data1) + $signed(data0)) ; +//spyglass enable_block W484 + end + endfunction +//pooling result +//: my $m = 1*(8 +6); +//: print qq( +//: function[${m}-1:0] pooling_fun; +//: input[1:0] pooling_type; +//: input data0_valid; +//: input[${m}-1:0] data0_in; +//: input[${m}-1:0] data1_in; +//: ); + reg min_pooling; + reg max_pooling; + reg mean_pooling; + begin + min_pooling = (pooling_type== 2'h2 ); + max_pooling = (pooling_type== 2'h1 ); + mean_pooling = (pooling_type== 2'h0 ); +//: my $k = 1; +//: my $m = (8 +6); +//: foreach my $i (0..$k-1) { +//: print qq( +//: pooling_fun[${m}*${i}+${m}-1:${m}*${i}] = mean_pooling? pooling_SUM(data0_valid,data0_in[${m}*${i}+${m}-1:${m}*${i}],data1_in[${m}*${i}+${m}-1:${m}*${i}]) : +//: min_pooling ? (pooling_MIN(data0_valid,data0_in[${m}*${i}+${m}-1:${m}*${i}],data1_in[${m}*${i}+${m}-1:${m}*${i}])) : +//: max_pooling ? (pooling_MAX(data0_valid,data0_in[${m}*${i}+${m}-1:${m}*${i}],data1_in[${m}*${i}+${m}-1:${m}*${i}])) : 0; +//: ); +//: } + end +endfunction +//write memory +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_data0_lst <= 0; + mem_data1_lst <= 0; + mem_data2_lst <= 0; + mem_data3_lst <= 0; + mem_data4_lst <= 0; + mem_data5_lst <= 0; + mem_data6_lst <= 0; + mem_data7_lst <= 0; + end else begin + if(flush_read_en_d & wr_data_stage0_prdy) begin + mem_data0_lst <= {mem_rdata_0[1*(8 +6)+2:0]}; + mem_data1_lst <= {mem_rdata_1[1*(8 +6)+2:0]}; + mem_data2_lst <= {mem_rdata_2[1*(8 +6)+2:0]}; + mem_data3_lst <= {mem_rdata_3[1*(8 +6)+2:0]}; + mem_data4_lst <= {mem_rdata_4[1*(8 +6)+2:0]}; + mem_data5_lst <= {mem_rdata_5[1*(8 +6)+2:0]}; + mem_data6_lst <= {mem_rdata_6[1*(8 +6)+2:0]}; + mem_data7_lst <= {mem_rdata_7[1*(8 +6)+2:0]}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_data0 <= 0; + mem_data1 <= 0; + mem_data2 <= 0; + mem_data3 <= 0; + mem_data4 <= 0; + mem_data5 <= 0; + mem_data6 <= 0; + mem_data7 <= 0; + end else begin + if(load_wr_stage1) begin//one cycle delay than pooling1d input + mem_data0 <= mem_re_1st_d[0]? {unit2d_vsize_cnt_0_d, datin_buf}: { unit2d_vsize_cnt_0_d,mem_rdata_0[1*(8 +6)-1:0]}; + mem_data1 <= mem_re_1st_d[1]? {unit2d_vsize_cnt_1_d, datin_buf}: { unit2d_vsize_cnt_1_d,mem_rdata_1[1*(8 +6)-1:0]}; + mem_data2 <= mem_re_1st_d[2]? {unit2d_vsize_cnt_2_d, datin_buf}: { unit2d_vsize_cnt_2_d,mem_rdata_2[1*(8 +6)-1:0]}; + mem_data3 <= mem_re_1st_d[3]? {unit2d_vsize_cnt_3_d, datin_buf}: { unit2d_vsize_cnt_3_d,mem_rdata_3[1*(8 +6)-1:0]}; + mem_data4 <= mem_re_1st_d[4]? {unit2d_vsize_cnt_4_d, datin_buf}: { unit2d_vsize_cnt_4_d,mem_rdata_4[1*(8 +6)-1:0]}; + mem_data5 <= mem_re_1st_d[5]? {unit2d_vsize_cnt_5_d, datin_buf}: { unit2d_vsize_cnt_5_d,mem_rdata_5[1*(8 +6)-1:0]}; + mem_data6 <= mem_re_1st_d[6]? {unit2d_vsize_cnt_6_d, datin_buf}: { unit2d_vsize_cnt_6_d,mem_rdata_6[1*(8 +6)-1:0]}; + mem_data7 <= mem_re_1st_d[7]? {unit2d_vsize_cnt_7_d, datin_buf}: { unit2d_vsize_cnt_7_d,mem_rdata_7[1*(8 +6)-1:0]}; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_buf_2d <= 0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + datin_buf_2d <= datin_buf; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + datin_buf_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_end_2d <= 1'b0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + wr_line_end_2d <= wr_line_end_buf; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + wr_line_end_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_raddr_2d <= {9{1'b0}}; + end else begin + if ((load_wr_stage1) == 1'b1) begin + mem_raddr_2d <= mem_raddr_d; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_surface_dat_done_2d <= 1'b0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + wr_surface_dat_done_2d <= wr_surface_dat_done_buf; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + wr_surface_dat_done_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_active_line_d <= 1'b0; + end else begin + if ((load_din) == 1'b1) begin + last_active_line_d <= active_last_line; +// VCS coverage off + end else if ((load_din) == 1'b0) begin + end else begin + last_active_line_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_active_line_2d <= 1'b0; + end else begin + if ((load_wr_stage1) == 1'b1) begin + last_active_line_2d <= last_active_line_d; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + last_active_line_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_1st_d <= {8{1'b0}}; + end else begin + if ((load_din) == 1'b1) begin + mem_re_1st_d <= mem_re_1st; +// VCS coverage off + end else if ((load_din) == 1'b0) begin + end else begin + mem_re_1st_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_1st_2d <= {8{1'b0}}; + end else begin + if ((load_wr_stage1) == 1'b1) begin + mem_re_1st_2d <= mem_re_1st_d; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + mem_re_1st_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_raddr_d <= {9{1'b0}}; + end else begin + if (((|mem_re) | (flush_read_en & one_width_norm_rdy)) == 1'b1) begin + mem_raddr_d <= mem_raddr; + end + end +end +//=========================== +//8bits mem_re two cycle delay +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_d <= {8{1'b0}}; + end else begin + if ((load_din) == 1'b1) begin + mem_re_d <= mem_re; +// VCS coverage off + end else if ((load_din) == 1'b0) begin + end else begin + mem_re_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_2d <= {8{1'b0}}; + end else begin + if ((load_wr_stage1) == 1'b1) begin + mem_re_2d <= mem_re_d; +// VCS coverage off + end else if ((load_wr_stage1) == 1'b0) begin + end else begin + mem_re_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//write stage0 +assign pooling1d_norm_rdy = ~wr_data_stage0_vld | wr_data_stage0_prdy; +//rebuild valid signal with cur_datin_disable control +//assign pooling1d_vld_rebuild = cur_datin_disable ? 1'b1 : pooling1d_pvld_use; +assign pooling1d_vld_rebuild = (one_width_disable | cur_datin_disable) ? 1'b1 : pooling1d_pvld_use; +assign load_din_all = pooling1d_norm_rdy & pooling1d_vld_rebuild; +//pipe delay +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_stage0_vld <= 1'b0; + end else begin +//if(|mem_re) + if(pooling1d_vld_rebuild) + wr_data_stage0_vld <= 1'b1; + else if(wr_data_stage0_prdy) + wr_data_stage0_vld <= 1'b0; + end +end +assign wr_data_stage0_prdy = ~wr_data_stage1_vld | wr_data_stage1_prdy; +//write stage1 +assign load_wr_stage1_all = wr_data_stage0_vld & wr_data_stage0_prdy; +//assign load_wr_stage1 = wr_data_stage0_vld & wr_data_stage0_prdy & (~cur_datin_disable_d); +assign load_wr_stage1 = wr_data_stage0_vld & wr_data_stage0_prdy & (~cur_datin_disable_d) & (~one_width_disable_d); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_stage1_vld <= 1'b0; + end else begin + if(wr_data_stage0_vld) + wr_data_stage1_vld <= 1'b1; + else if(wr_data_stage1_prdy) + wr_data_stage1_vld <= 1'b0; + end +end +//write stage2 +assign load_wr_stage2_all = wr_data_stage1_vld & wr_data_stage1_prdy; +assign load_wr_stage2 = wr_data_stage1_vld & wr_data_stage1_prdy & (~cur_datin_disable_2d) & (~one_width_disable_2d); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_stage2_vld <= 1'b0; + end else begin +//if(wr_data_stage1_vld) + if(wr_data_stage1_vld ) + wr_data_stage2_vld <= 1'b1; + else if(pout_data_stage0_prdy) + wr_data_stage2_vld <= 1'b0; + end +end +assign load_wr_stage3_all = wr_data_stage2_vld & pout_data_stage0_prdy; +assign load_wr_stage3 = wr_data_stage2_vld & pout_data_stage0_prdy & (~cur_datin_disable_3d) & (~one_width_disable_3d); +//==================================================================== +// pooling data calculation and write back +// +//-------------------------------------------------------------------- +assign pooling_datin = datin_buf_2d; +//read from memory +assign mem_data_valid = load_wr_stage2 ? mem_re_2d : 8'h00; +assign pooling_2d_result_0 = mem_re_1st_2d[0] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[0],pooling_datin,mem_data0[1*(8 +6)-1:0]); +assign pooling_2d_result_1 = mem_re_1st_2d[1] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[1],pooling_datin,mem_data1[1*(8 +6)-1:0]); +assign pooling_2d_result_2 = mem_re_1st_2d[2] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[2],pooling_datin,mem_data2[1*(8 +6)-1:0]); +assign pooling_2d_result_3 = mem_re_1st_2d[3] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[3],pooling_datin,mem_data3[1*(8 +6)-1:0]); +assign pooling_2d_result_4 = mem_re_1st_2d[4] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[4],pooling_datin,mem_data4[1*(8 +6)-1:0]); +assign pooling_2d_result_5 = mem_re_1st_2d[5] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[5],pooling_datin,mem_data5[1*(8 +6)-1:0]); +assign pooling_2d_result_6 = mem_re_1st_2d[6] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[6],pooling_datin,mem_data6[1*(8 +6)-1:0]); +assign pooling_2d_result_7 = mem_re_1st_2d[7] ? pooling_datin : pooling_fun(pooling_type_cfg[1:0],mem_data_valid[7],pooling_datin,mem_data7[1*(8 +6)-1:0]); +assign pooling_2d_info_0 = {wr_line_end_2d,mem_data0[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_1 = {wr_line_end_2d,mem_data1[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_2 = {wr_line_end_2d,mem_data2[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_3 = {wr_line_end_2d,mem_data3[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_4 = {wr_line_end_2d,mem_data4[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_5 = {wr_line_end_2d,mem_data5[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_6 = {wr_line_end_2d,mem_data6[1*(8 +6)+2:1*(8 +6)]}; +assign pooling_2d_info_7 = {wr_line_end_2d,mem_data7[1*(8 +6)+2:1*(8 +6)]}; +//memory write data +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1*(8 +6)+4; +//: foreach my $i (0..7){ +//: print " int_mem_wdata_$i <= ${k}'d0; \n"; +//: } + end else begin + if(load_wr_stage2) begin +//: my $k = 1*(8 +6)+4; +//: foreach my $i (0..7){ +//: print " int_mem_wdata_$i <= {pooling_2d_info_${i},pooling_2d_result_$i}; \n"; +//: } + end + end +end +//write enabel signal +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_mem_we <= {8{1'b0}}; + end else begin + if ((load_wr_stage2) == 1'b1) begin + int_mem_we <= mem_re_2d; +// VCS coverage off + end else if ((load_wr_stage2) == 1'b0) begin + end else begin + int_mem_we <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage2))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + int_mem_waddr <= {9{1'b0}}; + end else begin + if ((load_wr_stage2) == 1'b1) begin + int_mem_waddr <= mem_raddr_2d; + end + end +end +//memory write select +assign mem_wdata_0 = int_mem_wdata_0; +assign mem_wdata_1 = int_mem_wdata_1; +assign mem_wdata_2 = int_mem_wdata_2; +assign mem_wdata_3 = int_mem_wdata_3; +assign mem_wdata_4 = int_mem_wdata_4; +assign mem_wdata_5 = int_mem_wdata_5; +assign mem_wdata_6 = int_mem_wdata_6; +assign mem_wdata_7 = int_mem_wdata_7; +assign mem_we = (int_mem_we & {8{load_wr_stage3}}); +assign mem_waddr_0 = int_mem_waddr; +assign mem_waddr_1 = int_mem_waddr; +assign mem_waddr_2 = int_mem_waddr; +assign mem_waddr_3 = int_mem_waddr; +assign mem_waddr_4 = int_mem_waddr; +assign mem_waddr_5 = int_mem_waddr; +assign mem_waddr_6 = int_mem_waddr; +assign mem_waddr_7 = int_mem_waddr; +//============================================================================= +//memory line buffer instance +// +//----------------------------------------------------------------------------- +//: my $depth = int(16*(8/1)); +//: my $depth_bw = int( log($depth)/log(2) ); +//: my $width = (1*(8 +6)+4); +//: foreach my $i (0..7) { +//: print qq( +//: nv_ram_rws_${depth}x${width} bank${i}_uram_0 ( +//: .clk (nvdla_core_clk) +//: ,.ra (mem_raddr[${depth_bw}-1:0]) +//: ,.re (mem_re[$i] | mem_re_last[$i]) +//: ,.dout (mem_rdata_$i) +//: ,.wa (mem_waddr_${i}[${depth_bw}-1:0]) +//: ,.we (mem_we[$i]) +//: ,.di (mem_wdata_$i) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd) +//: ); +//: ); +//: } +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram0 read and write same addr simultaneously") zzz_assert_never_31x (nvdla_core_clk, `ASSERT_RESET, (mem_we[0] & ( mem_re[0] | mem_re_last[0])) & (mem_raddr == mem_waddr_0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram1 read and write same addr simultaneously") zzz_assert_never_32x (nvdla_core_clk, `ASSERT_RESET, (mem_we[1] & ( mem_re[1] | mem_re_last[1])) & (mem_raddr == mem_waddr_1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram2 read and write same addr simultaneously") zzz_assert_never_33x (nvdla_core_clk, `ASSERT_RESET, (mem_we[2] & ( mem_re[2] | mem_re_last[2])) & (mem_raddr == mem_waddr_2)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram3 read and write same addr simultaneously") zzz_assert_never_34x (nvdla_core_clk, `ASSERT_RESET, (mem_we[3] & ( mem_re[3] | mem_re_last[3])) & (mem_raddr == mem_waddr_3)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram4 read and write same addr simultaneously") zzz_assert_never_35x (nvdla_core_clk, `ASSERT_RESET, (mem_we[4] & ( mem_re[4] | mem_re_last[4])) & (mem_raddr == mem_waddr_4)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram5 read and write same addr simultaneously") zzz_assert_never_36x (nvdla_core_clk, `ASSERT_RESET, (mem_we[5] & ( mem_re[5] | mem_re_last[5])) & (mem_raddr == mem_waddr_5)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram6 read and write same addr simultaneously") zzz_assert_never_37x (nvdla_core_clk, `ASSERT_RESET, (mem_we[6] & ( mem_re[6] | mem_re_last[6])) & (mem_raddr == mem_waddr_6)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP Cal2d line buffer 2port-ram7 read and write same addr simultaneously") zzz_assert_never_38x (nvdla_core_clk, `ASSERT_RESET, (mem_we[7] & ( mem_re[7] | mem_re_last[7])) & (mem_raddr == mem_waddr_7)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============================================================================== +//data reading control during datin_disable time +// +///////////////////////////////////////////////////////////////////////////////////////////////////// +//data reading from buffer for datin_disable bubble part and last_out during the next surface coming +//cur_datin_disable means bubble part, need disable input data prdy +//in the end of total layer, if have data need flushed, will also bubble input +//last_out_en flush the last lines during the next surface data coming +///////////////////////////////////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling_last <= {3{1'b0}}; + mem_re2_sel_last <= 1'b0; + mem_re3_sel_last <= 1'b0; + mem_re4_sel_last <= 1'b0; + end else begin + if(wr_surface_dat_done) begin + unit2d_cnt_pooling_last <= (unit2d_cnt_pooling == unit2d_cnt_pooling_max) ? 3'd0 : (unit2d_cnt_pooling + 1'b1); + mem_re2_sel_last <= mem_re2_sel; + mem_re3_sel_last <= mem_re3_sel; + mem_re4_sel_last <= mem_re4_sel; + end else if(((line_end & cur_datin_disable) | (wr_line_dat_done & last_out_en)) & one_width_norm_rdy) begin + if(unit2d_cnt_pooling_last_end) + unit2d_cnt_pooling_last <= 3'd0; + else + unit2d_cnt_pooling_last <= unit2d_cnt_pooling_last + 1'b1; + end + end +end +assign unit2d_cnt_pooling_last_end = (unit2d_cnt_pooling_last == unit2d_cnt_pooling_max); +assign flush_read_en = (cur_datin_disable | last_out_en) & one_width_norm_rdy; +assign unit2d_en_last[0] = flush_read_en & (unit2d_cnt_pooling_last == 3'd0); +assign unit2d_en_last[1] = flush_read_en & (unit2d_cnt_pooling_last == 3'd1); +assign unit2d_en_last[2] = flush_read_en & (unit2d_cnt_pooling_last == 3'd2); +assign unit2d_en_last[3] = flush_read_en & (unit2d_cnt_pooling_last == 3'd3); +assign unit2d_en_last[4] = flush_read_en & (unit2d_cnt_pooling_last == 3'd4); +assign unit2d_en_last[5] = flush_read_en & (unit2d_cnt_pooling_last == 3'd5); +assign unit2d_en_last[6] = flush_read_en & (unit2d_cnt_pooling_last == 3'd6); +assign unit2d_en_last[7] = flush_read_en & (unit2d_cnt_pooling_last == 3'd7); +assign mem_re2_last[0] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel_last; +assign mem_re2_last[1] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel_last; +assign mem_re2_last[2] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel_last; +assign mem_re2_last[3] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel_last; +assign mem_re2_last[4] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd0) & mem_re2_sel_last; +assign mem_re2_last[5] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd1) & mem_re2_sel_last; +assign mem_re2_last[6] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd2) & mem_re2_sel_last; +assign mem_re2_last[7] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd3) & mem_re2_sel_last; +assign mem_re3_last[0] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[1] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re3_last[2] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[3] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re3_last[4] = unit2d_en_last[2] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[5] = unit2d_en_last[2] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re3_last[6] = unit2d_en_last[3] & (wr_sub_lbuf_cnt==3'd0) & mem_re3_sel_last; +assign mem_re3_last[7] = unit2d_en_last[3] & (wr_sub_lbuf_cnt==3'd1) & mem_re3_sel_last; +assign mem_re4_last[0] = unit2d_en_last[0] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[1] = unit2d_en_last[1] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[2] = unit2d_en_last[2] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[3] = unit2d_en_last[3] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[4] = unit2d_en_last[4] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[5] = unit2d_en_last[5] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[6] = unit2d_en_last[6] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re4_last[7] = unit2d_en_last[7] & (wr_sub_lbuf_cnt==3'd0) & mem_re4_sel_last; +assign mem_re_last = mem_re2_last | mem_re3_last | mem_re4_last; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + flush_read_en_d <= 1'b0; + end else begin + if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b1) begin + flush_read_en_d <= flush_read_en; +// VCS coverage off + end else if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b0) begin + end else begin + flush_read_en_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy )))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_last_d <= {8{1'b0}}; + end else begin + if (((load_din ) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b1) begin + mem_re_last_d <= mem_re_last; +// VCS coverage off + end else if (((load_din ) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b0) begin + end else begin + mem_re_last_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_din ) | (cur_datin_disable & one_width_norm_rdy )))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling_last_d <= {3{1'b0}}; + end else begin + if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b1) begin + unit2d_cnt_pooling_last_d <= unit2d_cnt_pooling_last; +// VCS coverage off + end else if (((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy/*pooling1d_norm_rdy*/)) == 1'b0) begin + end else begin + unit2d_cnt_pooling_last_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_din & (|mem_re_last)) | (cur_datin_disable & one_width_norm_rdy )))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable_d <= 1'b0; + end else begin + if ((load_din_all) == 1'b1) begin + cur_datin_disable_d <= cur_datin_disable; +// VCS coverage off + end else if ((load_din_all) == 1'b0) begin + end else begin + cur_datin_disable_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable_d <= 1'b0; + end else begin + if ((load_din_all) == 1'b1) begin + one_width_disable_d <= one_width_disable; +// VCS coverage off + end else if ((load_din_all) == 1'b0) begin + end else begin + one_width_disable_d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_din_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mem_re_last_2d <= {8{1'b0}}; + end else begin + if (( load_wr_stage1 | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b1) begin + mem_re_last_2d <= mem_re_last_d; +// VCS coverage off + end else if (( load_wr_stage1 | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b0) begin + end else begin + mem_re_last_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^( load_wr_stage1 | (cur_datin_disable_d & wr_data_stage0_prdy)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + unit2d_cnt_pooling_last_2d <= {3{1'b0}}; + end else begin + if (((load_wr_stage1 & (|mem_re_last_d)) | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b1) begin + unit2d_cnt_pooling_last_2d <= unit2d_cnt_pooling_last_d; +// VCS coverage off + end else if (((load_wr_stage1 & (|mem_re_last_d)) | (cur_datin_disable_d & wr_data_stage0_prdy)) == 1'b0) begin + end else begin + unit2d_cnt_pooling_last_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_45x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^((load_wr_stage1 & (|mem_re_last_d)) | (cur_datin_disable_d & wr_data_stage0_prdy)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//&Always posedge; +// if(cur_datin_disable_d) +// cur_datin_disable_2d <0= 1'b1; +// else if(wr_data_stage1_prdy) +// cur_datin_disable_2d <0= 1'b0; +//&End; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable_2d <= 1'b0; + end else begin + if ((load_wr_stage1_all) == 1'b1) begin + cur_datin_disable_2d <= cur_datin_disable_d; +// VCS coverage off + end else if ((load_wr_stage1_all) == 1'b0) begin + end else begin + cur_datin_disable_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_46x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable_2d <= 1'b0; + end else begin + if ((load_wr_stage1_all) == 1'b1) begin + one_width_disable_2d <= one_width_disable_d; +// VCS coverage off + end else if ((load_wr_stage1_all) == 1'b0) begin + end else begin + one_width_disable_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_47x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage1_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cur_datin_disable_3d <= 1'b0; + end else begin + if ((load_wr_stage2_all) == 1'b1) begin + cur_datin_disable_3d <= cur_datin_disable_2d; +// VCS coverage off + end else if ((load_wr_stage2_all) == 1'b0) begin + end else begin + cur_datin_disable_3d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_48x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage2_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + one_width_disable_3d <= 1'b0; + end else begin + if ((load_wr_stage2_all) == 1'b1) begin + one_width_disable_3d <= one_width_disable_2d; +// VCS coverage off + end else if ((load_wr_stage2_all) == 1'b0) begin + end else begin + one_width_disable_3d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_49x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage2_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//line buffer2 +assign pout_mem_data_sel_1_last[0] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[0] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[1] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[1] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[2] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[2] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[3] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[3] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re2_sel; +assign pout_mem_data_sel_1_last[4] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[4] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +assign pout_mem_data_sel_1_last[5] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[5] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +assign pout_mem_data_sel_1_last[6] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[6] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +assign pout_mem_data_sel_1_last[7] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[7] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re2_sel; +//line buffer3,4 +assign pout_mem_data_sel_2_last[0] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[0] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re3_sel; +assign pout_mem_data_sel_2_last[1] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[1] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re3_sel; +assign pout_mem_data_sel_2_last[2] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[2] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re3_sel; +assign pout_mem_data_sel_2_last[3] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[3] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re3_sel; +assign pout_mem_data_sel_2_last[4] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[4] & (unit2d_cnt_pooling_last_2d==3'd2) & mem_re3_sel; +assign pout_mem_data_sel_2_last[5] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[5] & (unit2d_cnt_pooling_last_2d==3'd2) & mem_re3_sel; +assign pout_mem_data_sel_2_last[6] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[6] & (unit2d_cnt_pooling_last_2d==3'd3) & mem_re3_sel; +assign pout_mem_data_sel_2_last[7] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[7] & (unit2d_cnt_pooling_last_2d==3'd3) & mem_re3_sel; +//line buffer 5,6,7,8 +assign pout_mem_data_sel_3_last[0] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[0] & (unit2d_cnt_pooling_last_2d==3'd0) & mem_re4_sel; +assign pout_mem_data_sel_3_last[1] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[1] & (unit2d_cnt_pooling_last_2d==3'd1) & mem_re4_sel; +assign pout_mem_data_sel_3_last[2] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[2] & (unit2d_cnt_pooling_last_2d==3'd2) & mem_re4_sel; +assign pout_mem_data_sel_3_last[3] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[3] & (unit2d_cnt_pooling_last_2d==3'd3) & mem_re4_sel; +assign pout_mem_data_sel_3_last[4] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[4] & (unit2d_cnt_pooling_last_2d==3'd4) & mem_re4_sel; +assign pout_mem_data_sel_3_last[5] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[5] & (unit2d_cnt_pooling_last_2d==3'd5) & mem_re4_sel; +assign pout_mem_data_sel_3_last[6] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[6] & (unit2d_cnt_pooling_last_2d==3'd6) & mem_re4_sel; +assign pout_mem_data_sel_3_last[7] = (load_wr_stage2 | (cur_datin_disable_2d & wr_data_stage1_prdy)) & mem_re_last_2d[7] & (unit2d_cnt_pooling_last_2d==3'd7) & mem_re4_sel; +assign pout_mem_data_sel_last = pout_mem_data_sel_3_last | pout_mem_data_sel_2_last | pout_mem_data_sel_1_last; +//: my $k=1*(8 +6)+3; +//: print qq( +//: assign pout_mem_data_last = (mem_data0_lst & {${k}{pout_mem_data_sel_last[0]}}) | +//: (mem_data1_lst & {${k}{pout_mem_data_sel_last[1]}}) | +//: (mem_data2_lst & {${k}{pout_mem_data_sel_last[2]}}) | +//: (mem_data3_lst & {${k}{pout_mem_data_sel_last[3]}}) | +//: (mem_data4_lst & {${k}{pout_mem_data_sel_last[4]}}) | +//: (mem_data5_lst & {${k}{pout_mem_data_sel_last[5]}}) | +//: (mem_data6_lst & {${k}{pout_mem_data_sel_last[6]}}) | +//: (mem_data7_lst & {${k}{pout_mem_data_sel_last[7]}}) ; +//: ); +//============================================================================== +//unit2d pooling data read out +// +// +//------------------------------------------------------------------------------ +//data count in sub line +assign rd_line_out_done = wr_line_end_2d & rd_line_out; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_line_out_cnt <= {9{1'b0}}; + end else begin + if(rd_line_out_done | rd_sub_lbuf_end) + rd_line_out_cnt <= 9'd0; + else if(rd_line_out) + rd_line_out_cnt <= rd_line_out_cnt + 1'd1; + end +end +assign rd_sub_lbuf_end =((rd_line_out & (rd_line_out_cnt==BANK_DEPTH)) | rd_line_out_done); +//sub line buffer counter +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_sub_lbuf_cnt[2:0] <= {3{1'b0}}; + end else begin + if(rd_comb_lbuf_end) + rd_sub_lbuf_cnt[2:0] <= 3'd0; + else if(rd_sub_lbuf_end) + rd_sub_lbuf_cnt[2:0] <= rd_sub_lbuf_cnt +1; + end +end +assign rd_comb_lbuf_end = (rd_sub_lbuf_end & ({2'd0,rd_sub_lbuf_cnt}==(bank_merge_num -1))) | rd_line_out_done; +//combine line buffer counter +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_comb_lbuf_cnt[2:0] <= {3{1'b0}}; + end else begin +//if(rd_lbuf_end | wr_surface_dat_done_2d) + if(rd_lbuf_end | (wr_surface_dat_done_2d & load_wr_stage2)) + rd_comb_lbuf_cnt[2:0] <= 3'd0; + else if(rd_comb_lbuf_end & last_active_line_2d) + rd_comb_lbuf_cnt[2:0] <= rd_comb_lbuf_cnt + 1; + end +end +assign rd_lbuf_end = ({2'd0,rd_comb_lbuf_cnt}==(buffer_lines_num-1)) & rd_comb_lbuf_end & last_active_line_2d; +//////////////////////////////////////////////////////////////////////////////////////////////////// +//unit2d_data_rdy need two active delays as load_wr_stage2 +assign rd_line_out = |pout_mem_data_sel; +assign rd_pout_data_en = (rd_line_out | ((load_wr_stage2 & (|mem_re_last_2d))| (cur_datin_disable_2d & wr_data_stage1_prdy))); +//read output stage +assign wr_data_stage1_prdy = (~wr_data_stage2_vld | pout_data_stage0_prdy); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_d <= 1'b0; + end else begin + if ((load_wr_stage2_all) == 1'b1) begin + rd_pout_data_en_d <= rd_pout_data_en; + end + end +end +assign rd_pout_data_stage0 = load_wr_stage3_all & rd_pout_data_en_d; +assign pout_data_stage0_prdy = ~pout_data_stage1_vld | pout_data_stage1_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_data_stage1_vld <= 1'b0; + end else begin + if(wr_data_stage2_vld) + pout_data_stage1_vld <= 1'b1; + else if(pout_data_stage1_prdy) + pout_data_stage1_vld <= 1'b0; + end +end +assign pout_data_stage1_prdy = ~pout_data_stage2_vld | pout_data_stage2_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_2d <= 1'b0; + end else begin + if ((load_wr_stage3_all) == 1'b1) begin + rd_pout_data_en_2d <= rd_pout_data_en_d; +// VCS coverage off + end else if ((load_wr_stage3_all) == 1'b0) begin + end else begin + rd_pout_data_en_2d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(load_wr_stage3_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign rd_pout_data_stage1_all = pout_data_stage1_vld & pout_data_stage1_prdy; +assign rd_pout_data_stage1 = pout_data_stage1_vld & pout_data_stage1_prdy & rd_pout_data_en_2d; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_data_stage2_vld <= 1'b0; + end else begin + if(pout_data_stage1_vld) + pout_data_stage2_vld <= 1'b1; + else if(pout_data_stage2_prdy) + pout_data_stage2_vld <= 1'b0; + end +end +assign pout_data_stage2_prdy = ~pout_data_stage3_vld | pout_data_stage3_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_3d <= 1'b0; + end else begin + if ((rd_pout_data_stage1_all) == 1'b1) begin + rd_pout_data_en_3d <= rd_pout_data_en_2d; +// VCS coverage off + end else if ((rd_pout_data_stage1_all) == 1'b0) begin + end else begin + rd_pout_data_en_3d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_pout_data_stage1_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign rd_pout_data_stage2_all = pout_data_stage2_vld & pout_data_stage2_prdy; +assign rd_pout_data_stage2 = pout_data_stage2_vld & pout_data_stage2_prdy & rd_pout_data_en_3d; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_pout_data_en_4d <= 1'b0; + end else begin + if ((rd_pout_data_stage2_all) == 1'b1) begin + rd_pout_data_en_4d <= rd_pout_data_en_3d; +// VCS coverage off + end else if ((rd_pout_data_stage2_all) == 1'b0) begin + end else begin + rd_pout_data_en_4d <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(rd_pout_data_stage2_all))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pout_data_stage3_vld <= 1'b0; + end else begin + if(pout_data_stage2_vld) + pout_data_stage3_vld <= 1'b1; + else if(pout_data_stage3_prdy) + pout_data_stage3_vld <= 1'b0; + end +end +///////////////////////////////////////////////////////// +//line buffer1 +assign pout_mem_data_sel_0 = mem_re_2d & {8{load_wr_stage2}} & {8{ mem_re1_sel}} & {8{last_active_line_2d}}; +//line buffer2 +assign pout_mem_data_sel_1[0] = mem_re_2d[0] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[1] = mem_re_2d[1] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[2] = mem_re_2d[2] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[3] = mem_re_2d[3] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[4] = mem_re_2d[4] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[5] = mem_re_2d[5] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[6] = mem_re_2d[6] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +assign pout_mem_data_sel_1[7] = mem_re_2d[7] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re2_sel; +//line buffer3,4 +assign pout_mem_data_sel_2[0] = mem_re_2d[0] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[1] = mem_re_2d[1] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[2] = mem_re_2d[2] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[3] = mem_re_2d[3] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[4] = mem_re_2d[4] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd2) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[5] = mem_re_2d[5] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd2) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[6] = mem_re_2d[6] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd3) & last_active_line_2d & mem_re3_sel; +assign pout_mem_data_sel_2[7] = mem_re_2d[7] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd3) & last_active_line_2d & mem_re3_sel; +//line buffer 5,6,7,8 +assign pout_mem_data_sel_3[0] = mem_re_2d[0] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd0) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[1] = mem_re_2d[1] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd1) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[2] = mem_re_2d[2] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd2) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[3] = mem_re_2d[3] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd3) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[4] = mem_re_2d[4] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd4) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[5] = mem_re_2d[5] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd5) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[6] = mem_re_2d[6] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd6) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel_3[7] = mem_re_2d[7] & load_wr_stage2 & (rd_comb_lbuf_cnt==3'd7) & last_active_line_2d & mem_re4_sel; +assign pout_mem_data_sel = (pout_mem_data_sel_3 | pout_mem_data_sel_2 | pout_mem_data_sel_1 | pout_mem_data_sel_0); +always @(*) begin + case(pout_mem_data_sel[7:0]) + 8'h01: pout_mem_data_act = {pooling_2d_info_0[2:0],pooling_2d_result_0}; + 8'h02: pout_mem_data_act = {pooling_2d_info_1[2:0],pooling_2d_result_1}; + 8'h04: pout_mem_data_act = {pooling_2d_info_2[2:0],pooling_2d_result_2}; + 8'h08: pout_mem_data_act = {pooling_2d_info_3[2:0],pooling_2d_result_3}; + 8'h10: pout_mem_data_act = {pooling_2d_info_4[2:0],pooling_2d_result_4}; + 8'h20: pout_mem_data_act = {pooling_2d_info_5[2:0],pooling_2d_result_5}; + 8'h40: pout_mem_data_act = {pooling_2d_info_6[2:0],pooling_2d_result_6}; + 8'h80: pout_mem_data_act = {pooling_2d_info_7[2:0],pooling_2d_result_7}; + default: pout_mem_data_act = {(1*(8 +6)+3){1'd0}}; + endcase +end +assign int_pout_mem_data = pout_mem_data_act | pout_mem_data_last; +assign pout_mem_data = int_pout_mem_data; +//============================================================= +//pooling output data to DMA +// +//------------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_mem_data_$i <= {${m}{1'b0}}; \n"; +//: } + pout_mem_size_v <= {3{1'b0}}; + end else begin + if(rd_pout_data_en) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_mem_data_$i <= pout_mem_data[${m}*${i}+${m}-1:${m}*$i]; \n"; +//: } +//: print " pout_mem_size_v <= pout_mem_data[${k}*${m}+2:${k}*${m}]; \n"; + end + end +end +//=========================================================== +//adding pad value in v direction +//----------------------------------------------------------- +//padding value 1x,2x,3x,4x,5x,6x,7x table +assign pout_mem_size_v_use = pout_mem_size_v; +assign padding_here = average_pooling_en & (pout_mem_size_v_use != pooling_size_v_cfg); +assign {mon_pad_table_index[0],pad_table_index[2:0]} = pooling_size_v_cfg - pout_mem_size_v_use; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore cal2d: pooling size should not less than active num") zzz_assert_never_54x (nvdla_core_clk, `ASSERT_RESET, ((rd_pout_data_stage0) & mon_pad_table_index & reg2dp_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(*) begin + case(pad_table_index) + 3'd1: pad_table_out = reg2dp_pad_value_1x_cfg[18:0]; //1x + 3'd2: pad_table_out = reg2dp_pad_value_2x_cfg[18:0]; //2x + 3'd3: pad_table_out = reg2dp_pad_value_3x_cfg[18:0]; //3x + 3'd4: pad_table_out = reg2dp_pad_value_4x_cfg[18:0]; //4x + 3'd5: pad_table_out = reg2dp_pad_value_5x_cfg[18:0]; //5x + 3'd6: pad_table_out = reg2dp_pad_value_6x_cfg[18:0]; //6x + 3'd7: pad_table_out = reg2dp_pad_value_7x_cfg[18:0]; //7x + default:pad_table_out = 19'd0; //1x; + endcase +end +assign kernel_width_cfg[3:0] = reg2dp_kernel_width[2:0]+3'd1; +assign {mon_pad_value,pad_value[21:0]} = $signed(pad_table_out) * $signed({{1{1'b0}}, kernel_width_cfg}); +// //: my $k = NVDLA_PDP_THROUGHPUT; +// //: foreach my $i (0..$k-1) { +// //: print qq( +// //: assign pout_mem_data$i = pout_mem_data_$i; +// //: ); +// //: } +//: my $s = "\$signed"; +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign {mon_data_8bit_${i}_ff ,data_8bit_${i}_ff} = $s({pout_mem_data_${i}[${m}-1],pout_mem_data_$i}) + $s({pad_value[${m}-1], pad_value[${m}-1:0]}); +//: assign {mon_data_8bit_${i} ,data_8bit_${i}} = padding_here ? {mon_data_8bit_${i}_ff ,data_8bit_${i}_ff} : {{2{pout_mem_data_${i}[${m}-1]}},pout_mem_data_${i}[${m}-1:0] }; +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_0_$i <= {${m}{1'b0}}; \n"; +//: } + end else begin + if(average_pooling_en) begin + if(rd_pout_data_stage0) begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_0_$i <= data_8bit_$i; \n"; +//: } + end + end else if(rd_pout_data_stage0)begin +//: my $k = 1; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_0_$i <= {pout_mem_data_${i}[${m}-1],pout_mem_data_${i}}; \n"; +//: } + end + end +end +//=========================================================== +//stage1: (* /kernel_width) +//stage1 : calcate pooling data based on real pooling size --- (* 1/kernel_width) +//----------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_recip_width_use[16:0] <= {17{1'b0}}; + end else begin + reg2dp_recip_width_use[16:0] <= reg2dp_recip_width_cfg[16:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_recip_height_use[16:0] <= {17{1'b0}}; + end else begin + reg2dp_recip_height_use[16:0] <= reg2dp_recip_height_cfg[16:0]; + end +end +//8bits +//: my $s = "\$signed"; +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign data_hmult_8bit_${i}_ext_ff = $s(pout_data_0_${i})* $s({1'b0,reg2dp_recip_width_use[16:0]}); +//: assign data_hmult_8bit_${i}_ext = average_pooling_en ? data_hmult_8bit_${i}_ext_ff : {pout_data_0_${i}[${m}-1],pout_data_0_${i}[${m}-1:0] ,16'd0}; +//: assign i8_less_neg_0_5_${i} = data_hmult_8bit_${i}_ext[${m}+16] & ((data_hmult_8bit_${i}_ext[15] & (~(|data_hmult_8bit_${i}_ext[14:0]))) | (~data_hmult_8bit_${i}_ext[15])); +//: assign i8_more_neg_0_5_${i} = data_hmult_8bit_${i}_ext[${m}+16] & data_hmult_8bit_${i}_ext[15] & (|data_hmult_8bit_${i}_ext[14:0]); +//: assign {mon_i8_neg_add1_${i},i8_neg_add1_${i}} = data_hmult_8bit_${i}_ext[$j+16-1:16]+${j}'d1; +//: assign hmult_8bit_${i} = (i8_less_neg_0_5_${i})? data_hmult_8bit_${i}_ext[$j+16-1:16] : (i8_more_neg_0_5_${i})? i8_neg_add1_${i} : (data_hmult_8bit_${i}_ext[$j+16-2:16]+data_hmult_8bit_${i}_ext[15]);//rounding 0.5=1, -0.5=-1 +//: assign data_hmult_8bit_$i = hmult_8bit_$i; +//: assign data_hmult_stage0_in${i} = data_hmult_8bit_$i; +//: ); +//: print qq( +//: // &eperl::assert("-type never -desc 'PDPCore cal2d: the MSB bits should be all same as signed bit' -expr '(rd_pout_data_stage1 & ((&data_hmult_8bit_${i}_ext[${m}+16:$j+16]) != (|data_hmult_8bit_0_ext[${m}+16:$j+16])))' "); +//: ); +//: } +//load data to stage0 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage0_$i <= {${j}{1'b0}}; \n"; +//: } + end else begin + if(average_pooling_en) begin + if(rd_pout_data_stage1) begin +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage0_$i <= data_hmult_stage0_in$i; \n"; +//: } + end + end else if(rd_pout_data_stage1)begin +//: my $k = 1; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage0_$i <= pout_data_0_${i}[${j}-1:0]; \n"; +//: } + end + end +end +//=========================================================== +//stage1: (* /kernel_height) +//8bits +//: my $s = "\$signed"; +//: my $k = 1; +//: my $x = 8; +//: my $j = 8 +3; +//: my $m = 8 +6; +//: foreach my $i (0..$k-1) { +//: print qq( +//: assign data_vmult_8bit_${i}_ext_ff = $s(pout_data_stage0_${i}) * $s({1'b0,reg2dp_recip_height_use[16:0]}); +//: assign data_vmult_8bit_${i}_ext = average_pooling_en ? data_vmult_8bit_${i}_ext_ff : {pout_data_stage0_${i}[${j}-1],pout_data_stage0_${i} ,16'd0}; +//: assign i8_vless_neg_0_5_$i = data_vmult_8bit_${i}_ext[${j}+16] & ((data_vmult_8bit_${i}_ext[15] & (~(|data_vmult_8bit_${i}_ext[14:0]))) | (~data_vmult_8bit_${i}_ext[15])); +//: assign i8_vmore_neg_0_5_$i = data_vmult_8bit_${i}_ext[${j}+16] & data_vmult_8bit_${i}_ext[15] & (|data_vmult_8bit_${i}_ext[14:0]); +//: assign {mon_i8_neg_vadd1_${i},i8_neg_vadd1_${i}[${x}-1:0]} = data_vmult_8bit_${i}_ext[${x}+16-1:16]+ ${x}'d1; +//: assign vmult_8bit_${i} = (i8_vless_neg_0_5_$i)? data_vmult_8bit_${i}_ext[${x}+16-1:16] : (i8_vmore_neg_0_5_$i)? i8_neg_vadd1_$i : (data_vmult_8bit_${i}_ext[${x}+16-2:16]+data_vmult_8bit_${i}_ext[15]);//rounding 0.5=1, -0.5=-1 +//: assign data_vmult_8bit_$i = vmult_8bit_$i; +//: assign data_mult_stage1_in$i = data_vmult_8bit_$i; +//: ); +//: print qq( +//: // &eperl::assert("-type never -desc 'PDPCore cal2d: the MSB 4bits should be all same as signed bit' -expr '(rd_pout_data_stage1 & ((&data_vmult_8bit_${i}_ext[${j}+16:${x}+16-1]) != (|data_vmult_8bit_${i}_ext[${j}+16:${x}+16-1])))' "); +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = 1; +//: my $x = 8; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage1_$i <= {${x}{1'b0}}; \n"; +//: } + end else begin + if(average_pooling_en) begin + if(rd_pout_data_stage2) begin +//: my $k = 1; +//: my $x = 8; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage1_$i <= data_mult_stage1_in$i; \n"; +//: } + end + end else if(rd_pout_data_stage2) begin +//: my $k = 1; +//: my $x = 8; +//: foreach my $i (0..$k-1) { +//: print " pout_data_stage1_$i <= pout_data_stage0_${i}[${x}-1:0]; \n"; +//: } + end + end +end +assign int_dp2wdma_pd = { +//: my $k = 1; +//: if($k > 1) { +//: foreach my $i (0..$k-2) { +//: my $j = $k -$i -1; +//: print "pout_data_stage1_${j}, \n"; +//: } +//: } +pout_data_stage1_0}; +assign int_dp2wdma_valid = pout_data_stage3_vld & rd_pout_data_en_4d; +assign pout_data_stage3_prdy = pdp_dp2wdma_ready; +//============================= +//====================================== +//interface between POOLING data and DMA +assign pdp_dp2wdma_pd = int_dp2wdma_pd; +assign pdp_dp2wdma_valid = int_dp2wdma_valid; +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property PDP_line_buf_busy__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + &unit2d_en & (pout_width_cur==13'hf); + endproperty +// Cover 0 : "&unit2d_en & (pout_width_cur==13'hf)" + FUNCPOINT_PDP_line_buf_busy__0_COV : cover property (PDP_line_buf_busy__0_cov); + `endif +`endif +//VCS coverage on +////============== +////OBS signals +////============== +//assign obs_bus_pdp_cal2d_unit_en = unit2d_en[7:0]; +//assign obs_bus_pdp_cal2d_bank_we = mem_we[7:0]; +//assign obs_bus_pdp_cal2d_bank_re = mem_re[7:0] | mem_re_last[7:0]; +//assign obs_bus_pdp_cal2d_bubble = cur_datin_disable; +endmodule // NV_NVDLA_PDP_CORE_cal2d diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v new file mode 100644 index 0000000..75c8834 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v @@ -0,0 +1,1044 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_preproc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_preproc ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pre2cal1d_prdy //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_in_channel //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_in_width //|< i + ,reg2dp_flying_mode //|< i + ,reg2dp_op_en //|< i + ,sdp2pdp_pd //|< i + ,sdp2pdp_valid //|< i + ,pre2cal1d_pd //|> o + ,pre2cal1d_pvld //|> o + ,sdp2pdp_ready //|> o + ); +///////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input pre2cal1d_prdy; +input [31:0] pwrbus_ram_pd; +input [12:0] reg2dp_cube_in_channel; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_in_width; +input reg2dp_flying_mode; +input reg2dp_op_en; +input [8*1 -1:0] sdp2pdp_pd; +input sdp2pdp_valid; +output [1*8 +11:0] pre2cal1d_pd; +output pre2cal1d_pvld; +output sdp2pdp_ready; +///////////////////////////////////////////////////////////////// +wire b_sync; +wire cube_end; +wire last_c; +wire layer_end; +wire line_end; +wire load_din; +wire onfly_en; +wire op_en_load; +wire [11:0] pre2cal1d_info; +wire pre2cal1d_pvld_f; +wire sdp2pdp_c_end; +wire sdp2pdp_cube_end; +wire sdp2pdp_en; +wire sdp2pdp_line_end; +wire sdp2pdp_ready_use; +wire sdp2pdp_surf_end; +wire sdp2pdp_valid_use; +wire split_end; +wire surf_end; +reg [12:0] line_cnt; +reg op_en_d1; +reg [4:0] pos_c; +reg [4:0] sdp2pdp_c_cnt; +wire sdp2pdp_en_sync; +reg [12:0] sdp2pdp_height_cnt; +wire [8*1 -1:0] sdp2pdp_pd_use; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print "reg [12-${k}:0] sdp2pdp_surf_cnt; \n"; +//: print "reg [12-${k}:0] surf_cnt; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [12-3:0] sdp2pdp_surf_cnt; +reg [12-3:0] surf_cnt; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [12:0] sdp2pdp_width_cnt; +reg [12:0] w_cnt; +reg waiting_for_op_en; +///////////////////////////////////////////////////////////////// +//Data path pre process +//-------------------------------------------------------------- +assign onfly_en = (reg2dp_flying_mode == 1'h0 ); +//////////////////////////////////////////////////////////////// +//assign load_din = (sdp2pdp_valid & sdp2pdp_ready_f & sdp2pdp_en); +////////////////////////////// +//sdp to pdp layer end info +////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + sdp2pdp_c_cnt <= 5'd0; + else if(load_din) begin + if(sdp2pdp_c_end) + sdp2pdp_c_cnt <= 5'd0; + else + sdp2pdp_c_cnt <= sdp2pdp_c_cnt + 1'b1; + end +end +//: my $sdpth = 1; +//: my $atomicm = 8; +//: my $k = int( $atomicm/$sdpth ) -1; +//: print qq( +//: assign sdp2pdp_c_end = (load_din & (sdp2pdp_c_cnt == 5'd${k})); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign sdp2pdp_c_end = (load_din & (sdp2pdp_c_cnt == 5'd7)); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_width_cnt <= {13{1'b0}}; + end else begin + if(sdp2pdp_c_end) begin + if(sdp2pdp_line_end) + sdp2pdp_width_cnt <= 13'd0; + else + sdp2pdp_width_cnt <= sdp2pdp_width_cnt + 1'b1; + end + end +end +assign sdp2pdp_line_end = sdp2pdp_c_end & (sdp2pdp_width_cnt == reg2dp_cube_in_width[12:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_height_cnt <= {13{1'b0}}; + end else begin + if(sdp2pdp_line_end) begin + if(sdp2pdp_surf_end) + sdp2pdp_height_cnt <= 13'd0; + else + sdp2pdp_height_cnt <= sdp2pdp_height_cnt + 1'b1; + end + end +end +assign sdp2pdp_surf_end = sdp2pdp_line_end & (sdp2pdp_height_cnt == reg2dp_cube_in_height[12:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_surf_cnt <= 0; + end else begin + if(sdp2pdp_surf_end) begin + if(sdp2pdp_cube_end) + sdp2pdp_surf_cnt <= 0; + else + sdp2pdp_surf_cnt <= sdp2pdp_surf_cnt + 1'b1; + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign sdp2pdp_cube_end = sdp2pdp_surf_end & (sdp2pdp_surf_cnt == reg2dp_cube_in_channel[12:${k}]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign sdp2pdp_cube_end = sdp2pdp_surf_end & (sdp2pdp_surf_cnt == reg2dp_cube_in_channel[12:3]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////////////////////////////////////////////////////////////////////// +//waiting for op_en +////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 1'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +assign op_en_load = reg2dp_op_en & (~op_en_d1); +assign layer_end = sdp2pdp_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_for_op_en <= 1'b1; + end else begin + if(layer_end & onfly_en) + waiting_for_op_en <= 1'b1; + else if(op_en_load) begin + if(~onfly_en) + waiting_for_op_en <= 1'b1; + else if(onfly_en) + waiting_for_op_en <= 1'b0; + end + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property SDP_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & sdp2pdp_valid; + endproperty +// Cover 0 : "waiting_for_op_en & sdp2pdp_valid" + FUNCPOINT_SDP_NewLayer_out_req_And_core_CurLayer_not_finish__0_COV : cover property (SDP_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov); + `endif +`endif +//VCS coverage on +/////////////////////////// +assign sdp2pdp_en = (onfly_en & (~waiting_for_op_en)); +//assign sdp2pdp_ready = sdp2pdp_ready_f & sdp2pdp_en; +wire [8*1:0] pipe0_i; +assign pipe0_i = {sdp2pdp_pd,sdp2pdp_en}; +//: my $k = 8*1 + 1; +//: &eperl::pipe(" -is -wid $k -do pipe0_o -vo sdp2pdp_valid_use_f -ri sdp2pdp_ready_use -di pipe0_i -vi sdp2pdp_valid -ro sdp2pdp_ready_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg sdp2pdp_ready_f; +reg skid_flop_sdp2pdp_ready_f; +reg skid_flop_sdp2pdp_valid; +reg [9-1:0] skid_flop_pipe0_i; +reg pipe_skid_sdp2pdp_valid; +reg [9-1:0] pipe_skid_pipe0_i; +// Wire +wire skid_sdp2pdp_valid; +wire [9-1:0] skid_pipe0_i; +wire skid_sdp2pdp_ready_f; +wire pipe_skid_sdp2pdp_ready_f; +wire sdp2pdp_valid_use_f; +wire [9-1:0] pipe0_o; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_ready_f <= 1'b1; + skid_flop_sdp2pdp_ready_f <= 1'b1; + end else begin + sdp2pdp_ready_f <= skid_sdp2pdp_ready_f; + skid_flop_sdp2pdp_ready_f <= skid_sdp2pdp_ready_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_sdp2pdp_valid <= 1'b0; + end else begin + if (skid_flop_sdp2pdp_ready_f) begin + skid_flop_sdp2pdp_valid <= sdp2pdp_valid; + end + end +end +assign skid_sdp2pdp_valid = (skid_flop_sdp2pdp_ready_f) ? sdp2pdp_valid : skid_flop_sdp2pdp_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_sdp2pdp_ready_f & sdp2pdp_valid) begin + skid_flop_pipe0_i[9-1:0] <= pipe0_i[9-1:0]; + end +end +assign skid_pipe0_i[9-1:0] = (skid_flop_sdp2pdp_ready_f) ? pipe0_i[9-1:0] : skid_flop_pipe0_i[9-1:0]; + + +// PIPE READY +assign skid_sdp2pdp_ready_f = pipe_skid_sdp2pdp_ready_f || !pipe_skid_sdp2pdp_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_sdp2pdp_valid <= 1'b0; + end else begin + if (skid_sdp2pdp_ready_f) begin + pipe_skid_sdp2pdp_valid <= skid_sdp2pdp_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_sdp2pdp_ready_f && skid_sdp2pdp_valid) begin + pipe_skid_pipe0_i[9-1:0] <= skid_pipe0_i[9-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_sdp2pdp_ready_f = sdp2pdp_ready_use; +assign sdp2pdp_valid_use_f = pipe_skid_sdp2pdp_valid; +assign pipe0_o = pipe_skid_pipe0_i; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign {sdp2pdp_pd_use,sdp2pdp_en_sync} = pipe0_o; +//// +assign load_din = (sdp2pdp_valid & sdp2pdp_ready_f & sdp2pdp_en); +assign sdp2pdp_ready = sdp2pdp_ready_f & sdp2pdp_en; +//// +assign sdp2pdp_valid_use = sdp2pdp_valid_use_f & sdp2pdp_en_sync; +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//: my $sdpth = 1; +//: my $pdpth = 1; +//: my $sdpbw = $sdpth * 8; +//: my $pdpbw = $pdpth * 8; +//: if($sdpth > $pdpth) { +//: my $k = int($sdpth/$pdpth); +//: my $selbw = int(log(${k})/log(2)); +//: my $ks = ${k}-1; +//: print "reg [${pdpbw}-1:0] pre2cal1d_data; \n"; +//: print "reg [$selbw-1:0] fifo_sel_cnt; \n"; +//: print "wire [${k}-1:0] ro_rd_rdy; \n"; +//: print "wire [${k}-1:0] ro_rd_vld; \n"; +//: print "wire [${k}-1:0] ro_wr_rdy; \n"; +//: print "wire [${k}-1:0] ro_wr_vld; \n"; +//: print "assign sdp2pdp_ready_use = &ro_wr_rdy; \n"; +//: foreach my $i (0..$k-1){ +//: print "wire [${pdpbw}-1:0] ro_rd_pd_$i; \n"; +//: print "wire [${pdpbw}-1:0] ro_wr_pd_$i; \n"; +//: print "assign ro_wr_vld[$i] = sdp2pdp_valid_use "; +//: foreach my $j (0..$k-1){ +//: if($i != $j) { +//: print " & ro_wr_rdy[$j] "; +//: } +//: } +//: print "; \n"; +//: print qq( +//: assign ro_wr_pd_$i = sdp2pdp_pd_use[${pdpbw}*${i}+${pdpbw}-1:${pdpbw}*${i}]; +//: NV_NVDLA_PDP_SDPIN_ro_fifo u_ro_fifo_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.ro_wr_prdy (ro_wr_rdy[$i]) +//: ,.ro_wr_pvld (ro_wr_vld[$i]) +//: ,.ro_wr_pd (ro_wr_pd_${i}) +//: ,.ro_rd_prdy (ro_rd_rdy[$i]) +//: ,.ro_rd_pvld (ro_rd_vld[$i]) +//: ,.ro_rd_pd (ro_rd_pd_${i}) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: ); +//: assign ro_rd_rdy[$i] = pre2cal1d_prdy & (fifo_sel_cnt == $i); +//: ); +//: } +//: print qq( +//: assign pre2cal1d_pvld_f = |ro_rd_vld; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: fifo_sel_cnt <= 0; +//: end else begin +//: if(pre2cal1d_pvld_f) begin +//: if(pre2cal1d_prdy) begin +//: if(fifo_sel_cnt == ${selbw}'d${ks}) +//: fifo_sel_cnt <= 0; +//: else +//: fifo_sel_cnt <= fifo_sel_cnt + 1'b1; +//: end +//: end +//: end +//: end +//: always @(*) begin +//: case(fifo_sel_cnt) +//: ); +//: foreach my $i (0..$k-1){ +//: print "${selbw}'d${i}: pre2cal1d_data = ro_rd_pd_$i; \n"; +//: } +//: print qq( +//: default: pre2cal1d_data = ${pdpbw}'d0; +//: endcase +//: end +//: assign pre2cal1d_pvld = pre2cal1d_pvld_f; +//: ); +//: } +//: elsif($sdpth < $pdpth) { +//: my $k = int($pdpth/$sdpth); +//: my $selbw = int(log(${k})/log(2)); +//: print qq( +//: reg [$selbw-1:0] input_sel_cnt; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: input_sel_cnt <= 0; +//: else if(sdp2pdp_valid_use & sdp2pdp_ready_use) begin +//: if(input_sel_cnt == (${k}-1)) +//: input_sel_cnt <= 0; +//: else +//: input_sel_cnt <= input_sel_cnt + 1'b1; +//: end +//: end +//: ); +//: +//: foreach my $i (0..$k-1) { +//: print qq( +//: reg [$sdpbw-1:0] sdp2pdp_dp_$i; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: sdp2pdp_dp_$i <= 0; +//: else if((sdp2pdp_valid_use & sdp2pdp_ready_use) & (input_sel_cnt == $i)) +//: sdp2pdp_dp_$i <= sdp2pdp_pd_use; +//: end +//: ); +//: } +//: +//: print qq( +//: reg [${pdpbw}-1:0] pre2cal1d_data; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: pre2cal1d_data <= ${pdpbw}'d0; +//: else if((sdp2pdp_valid_use & sdp2pdp_ready_use) & (input_sel_cnt == ${k}-1)) +//: pre2cal1d_data <= { +//: ); +//: if($k > 1) { +//: foreach my $i(0..$k-2){ +//: my $j = $k -$i -1; +//: print " sdp2pdp_dp_$j, "; +//: } +//: } +//: print qq( +//: sdp2pdp_dp_0}; +//: end +//: ); +//: +//: print qq( +//: reg sdp2pdp_vld_f; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: sdp2pdp_vld_f <= 1'b0; +//: else if((sdp2pdp_valid_use & sdp2pdp_ready_use) & (input_sel_cnt == ${k}-1)) +//: sdp2pdp_vld_f <= 1'b1; +//: else if(pre2cal1d_prdy) +//: sdp2pdp_vld_f <= 1'b0; +//: end +//: assign pre2cal1d_pvld = sdp2pdp_vld_f; +//: ); +//: } +//: elsif($sdpth == $pdpth) { +//: print qq( +//: wire [${pdpbw}-1:0] pre2cal1d_data; +//: assign sdp2pdp_ready_use = pre2cal1d_prdy; +//: assign pre2cal1d_pvld = sdp2pdp_valid_use; +//: assign pre2cal1d_data = sdp2pdp_pd_use; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8-1:0] pre2cal1d_data; +assign sdp2pdp_ready_use = pre2cal1d_prdy; +assign pre2cal1d_pvld = sdp2pdp_valid_use; +assign pre2cal1d_data = sdp2pdp_pd_use; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============================================================== +//Data info path pre process +//-------------------------------------------------------------- +wire pre2cal1d_load; +assign pre2cal1d_load = pre2cal1d_pvld & pre2cal1d_prdy; +//pos_c, 8B data position within 32B +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_c <= 0; + end else begin + if(pre2cal1d_load) begin + if(last_c) + pos_c <= 0; + else + pos_c <= pos_c + 1'b1; + end + end +end +//: my $pdpth = 1; +//: my $atomicm = 8; +//: my $k = int( $atomicm/$pdpth ) -1; +//: print qq( +//: assign last_c = pre2cal1d_load & (pos_c == 5'd${k}); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign last_c = pre2cal1d_load & (pos_c == 5'd7); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//width direction +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + w_cnt[12:0] <= {13{1'b0}}; + end else begin + if(last_c) begin + if(line_end) + w_cnt[12:0] <= 13'd0; + else + w_cnt[12:0] <= w_cnt[12:0] + 1'b1; + end + end +end +assign line_end = last_c & (w_cnt[12:0] == reg2dp_cube_in_width[12:0]); +//height direction +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_cnt[12:0] <= {13{1'b0}}; + end else begin + if(line_end) begin + if(surf_end) + line_cnt[12:0] <= 13'd0; + else + line_cnt[12:0] <= line_cnt[12:0] + 1'b1; + end + end +end +assign surf_end = line_end & (line_cnt[12:0] == reg2dp_cube_in_height[12:0]); +//surface/Channel direction +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_cnt <= 0; + end else begin + if(surf_end) begin + if(split_end) + surf_cnt <= 0; + else + surf_cnt <= surf_cnt + 1'b1; + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign split_end = surf_end & (surf_cnt == reg2dp_cube_in_channel[12:${k}]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign split_end = surf_end & (surf_cnt == reg2dp_cube_in_channel[12:3]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cube_end = split_end ; +assign b_sync = line_end; +assign pre2cal1d_info = {cube_end,split_end,surf_end,line_end,b_sync,pos_c[2:0],4'd0};// need update pos_c width into 5bits at final +assign pre2cal1d_pd = {pre2cal1d_info,pre2cal1d_data}; +//////////////////////////// +//////////////////////////// +endmodule // NV_NVDLA_PDP_CORE_preproc +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_SDPIN_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -rd_reg -rand_none -ram_bypass -d 4 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_SDPIN_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +input [7:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [7:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] ro_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 3'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [1:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 3'd4 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int && !ro_rd_prdy); +reg [2:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] ro_rd_pd; // output data register +wire rd_req_next = (ro_rd_pvld_p || (ro_rd_pvld_int && !ro_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + end else begin + ro_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ro_rd_pd <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ro_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_SDPIN_ro_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_SDPIN_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [7:0] Di0; +input [1:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8] } +endmodule // vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +//vmw: Memory vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +//vmw: Address-size 2 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v.vcp new file mode 100644 index 0000000..a2ddb20 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v.vcp @@ -0,0 +1,935 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_preproc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_preproc ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pre2cal1d_prdy //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_in_channel //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_in_width //|< i + ,reg2dp_flying_mode //|< i + ,reg2dp_op_en //|< i + ,sdp2pdp_pd //|< i + ,sdp2pdp_valid //|< i + ,pre2cal1d_pd //|> o + ,pre2cal1d_pvld //|> o + ,sdp2pdp_ready //|> o + ); +///////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input pre2cal1d_prdy; +input [31:0] pwrbus_ram_pd; +input [12:0] reg2dp_cube_in_channel; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_in_width; +input reg2dp_flying_mode; +input reg2dp_op_en; +input [8*1 -1:0] sdp2pdp_pd; +input sdp2pdp_valid; +output [1*8 +11:0] pre2cal1d_pd; +output pre2cal1d_pvld; +output sdp2pdp_ready; +///////////////////////////////////////////////////////////////// +wire b_sync; +wire cube_end; +wire last_c; +wire layer_end; +wire line_end; +wire load_din; +wire onfly_en; +wire op_en_load; +wire [11:0] pre2cal1d_info; +wire pre2cal1d_pvld_f; +wire sdp2pdp_c_end; +wire sdp2pdp_cube_end; +wire sdp2pdp_en; +wire sdp2pdp_line_end; +wire sdp2pdp_ready_use; +wire sdp2pdp_surf_end; +wire sdp2pdp_valid_use; +wire split_end; +wire surf_end; +reg [12:0] line_cnt; +reg op_en_d1; +reg [4:0] pos_c; +reg [4:0] sdp2pdp_c_cnt; +wire sdp2pdp_en_sync; +reg [12:0] sdp2pdp_height_cnt; +wire [8*1 -1:0] sdp2pdp_pd_use; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print "reg [12-${k}:0] sdp2pdp_surf_cnt; \n"; +//: print "reg [12-${k}:0] surf_cnt; \n"; +reg [12:0] sdp2pdp_width_cnt; +reg [12:0] w_cnt; +reg waiting_for_op_en; +///////////////////////////////////////////////////////////////// +//Data path pre process +//-------------------------------------------------------------- +assign onfly_en = (reg2dp_flying_mode == 1'h0 ); +//////////////////////////////////////////////////////////////// +//assign load_din = (sdp2pdp_valid & sdp2pdp_ready_f & sdp2pdp_en); +////////////////////////////// +//sdp to pdp layer end info +////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + sdp2pdp_c_cnt <= 5'd0; + else if(load_din) begin + if(sdp2pdp_c_end) + sdp2pdp_c_cnt <= 5'd0; + else + sdp2pdp_c_cnt <= sdp2pdp_c_cnt + 1'b1; + end +end +//: my $sdpth = 1; +//: my $atomicm = 8; +//: my $k = int( $atomicm/$sdpth ) -1; +//: print qq( +//: assign sdp2pdp_c_end = (load_din & (sdp2pdp_c_cnt == 5'd${k})); +//: ); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_width_cnt <= {13{1'b0}}; + end else begin + if(sdp2pdp_c_end) begin + if(sdp2pdp_line_end) + sdp2pdp_width_cnt <= 13'd0; + else + sdp2pdp_width_cnt <= sdp2pdp_width_cnt + 1'b1; + end + end +end +assign sdp2pdp_line_end = sdp2pdp_c_end & (sdp2pdp_width_cnt == reg2dp_cube_in_width[12:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_height_cnt <= {13{1'b0}}; + end else begin + if(sdp2pdp_line_end) begin + if(sdp2pdp_surf_end) + sdp2pdp_height_cnt <= 13'd0; + else + sdp2pdp_height_cnt <= sdp2pdp_height_cnt + 1'b1; + end + end +end +assign sdp2pdp_surf_end = sdp2pdp_line_end & (sdp2pdp_height_cnt == reg2dp_cube_in_height[12:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2pdp_surf_cnt <= 0; + end else begin + if(sdp2pdp_surf_end) begin + if(sdp2pdp_cube_end) + sdp2pdp_surf_cnt <= 0; + else + sdp2pdp_surf_cnt <= sdp2pdp_surf_cnt + 1'b1; + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign sdp2pdp_cube_end = sdp2pdp_surf_end & (sdp2pdp_surf_cnt == reg2dp_cube_in_channel[12:${k}]); +//: ); +////////////////////////////////////////////////////////////////////// +//waiting for op_en +////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 1'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +assign op_en_load = reg2dp_op_en & (~op_en_d1); +assign layer_end = sdp2pdp_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_for_op_en <= 1'b1; + end else begin + if(layer_end & onfly_en) + waiting_for_op_en <= 1'b1; + else if(op_en_load) begin + if(~onfly_en) + waiting_for_op_en <= 1'b1; + else if(onfly_en) + waiting_for_op_en <= 1'b0; + end + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property SDP_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & sdp2pdp_valid; + endproperty +// Cover 0 : "waiting_for_op_en & sdp2pdp_valid" + FUNCPOINT_SDP_NewLayer_out_req_And_core_CurLayer_not_finish__0_COV : cover property (SDP_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov); + `endif +`endif +//VCS coverage on +/////////////////////////// +assign sdp2pdp_en = (onfly_en & (~waiting_for_op_en)); +//assign sdp2pdp_ready = sdp2pdp_ready_f & sdp2pdp_en; +wire [8*1:0] pipe0_i; +assign pipe0_i = {sdp2pdp_pd,sdp2pdp_en}; +//: my $k = 8*1 + 1; +//: &eperl::pipe(" -is -wid $k -do pipe0_o -vo sdp2pdp_valid_use_f -ri sdp2pdp_ready_use -di pipe0_i -vi sdp2pdp_valid -ro sdp2pdp_ready_f "); +assign {sdp2pdp_pd_use,sdp2pdp_en_sync} = pipe0_o; +//// +assign load_din = (sdp2pdp_valid & sdp2pdp_ready_f & sdp2pdp_en); +assign sdp2pdp_ready = sdp2pdp_ready_f & sdp2pdp_en; +//// +assign sdp2pdp_valid_use = sdp2pdp_valid_use_f & sdp2pdp_en_sync; +//////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////// +//: my $sdpth = 1; +//: my $pdpth = 1; +//: my $sdpbw = $sdpth * 8; +//: my $pdpbw = $pdpth * 8; +//: if($sdpth > $pdpth) { +//: my $k = int($sdpth/$pdpth); +//: my $selbw = int(log(${k})/log(2)); +//: my $ks = ${k}-1; +//: print "reg [${pdpbw}-1:0] pre2cal1d_data; \n"; +//: print "reg [$selbw-1:0] fifo_sel_cnt; \n"; +//: print "wire [${k}-1:0] ro_rd_rdy; \n"; +//: print "wire [${k}-1:0] ro_rd_vld; \n"; +//: print "wire [${k}-1:0] ro_wr_rdy; \n"; +//: print "wire [${k}-1:0] ro_wr_vld; \n"; +//: print "assign sdp2pdp_ready_use = &ro_wr_rdy; \n"; +//: foreach my $i (0..$k-1){ +//: print "wire [${pdpbw}-1:0] ro_rd_pd_$i; \n"; +//: print "wire [${pdpbw}-1:0] ro_wr_pd_$i; \n"; +//: print "assign ro_wr_vld[$i] = sdp2pdp_valid_use "; +//: foreach my $j (0..$k-1){ +//: if($i != $j) { +//: print " & ro_wr_rdy[$j] "; +//: } +//: } +//: print "; \n"; +//: print qq( +//: assign ro_wr_pd_$i = sdp2pdp_pd_use[${pdpbw}*${i}+${pdpbw}-1:${pdpbw}*${i}]; +//: NV_NVDLA_PDP_SDPIN_ro_fifo u_ro_fifo_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.ro_wr_prdy (ro_wr_rdy[$i]) +//: ,.ro_wr_pvld (ro_wr_vld[$i]) +//: ,.ro_wr_pd (ro_wr_pd_${i}) +//: ,.ro_rd_prdy (ro_rd_rdy[$i]) +//: ,.ro_rd_pvld (ro_rd_vld[$i]) +//: ,.ro_rd_pd (ro_rd_pd_${i}) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: ); +//: assign ro_rd_rdy[$i] = pre2cal1d_prdy & (fifo_sel_cnt == $i); +//: ); +//: } +//: print qq( +//: assign pre2cal1d_pvld_f = |ro_rd_vld; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) begin +//: fifo_sel_cnt <= 0; +//: end else begin +//: if(pre2cal1d_pvld_f) begin +//: if(pre2cal1d_prdy) begin +//: if(fifo_sel_cnt == ${selbw}'d${ks}) +//: fifo_sel_cnt <= 0; +//: else +//: fifo_sel_cnt <= fifo_sel_cnt + 1'b1; +//: end +//: end +//: end +//: end +//: always @(*) begin +//: case(fifo_sel_cnt) +//: ); +//: foreach my $i (0..$k-1){ +//: print "${selbw}'d${i}: pre2cal1d_data = ro_rd_pd_$i; \n"; +//: } +//: print qq( +//: default: pre2cal1d_data = ${pdpbw}'d0; +//: endcase +//: end +//: assign pre2cal1d_pvld = pre2cal1d_pvld_f; +//: ); +//: } +//: elsif($sdpth < $pdpth) { +//: my $k = int($pdpth/$sdpth); +//: my $selbw = int(log(${k})/log(2)); +//: print qq( +//: reg [$selbw-1:0] input_sel_cnt; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: input_sel_cnt <= 0; +//: else if(sdp2pdp_valid_use & sdp2pdp_ready_use) begin +//: if(input_sel_cnt == (${k}-1)) +//: input_sel_cnt <= 0; +//: else +//: input_sel_cnt <= input_sel_cnt + 1'b1; +//: end +//: end +//: ); +//: +//: foreach my $i (0..$k-1) { +//: print qq( +//: reg [$sdpbw-1:0] sdp2pdp_dp_$i; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: sdp2pdp_dp_$i <= 0; +//: else if((sdp2pdp_valid_use & sdp2pdp_ready_use) & (input_sel_cnt == $i)) +//: sdp2pdp_dp_$i <= sdp2pdp_pd_use; +//: end +//: ); +//: } +//: +//: print qq( +//: reg [${pdpbw}-1:0] pre2cal1d_data; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: pre2cal1d_data <= ${pdpbw}'d0; +//: else if((sdp2pdp_valid_use & sdp2pdp_ready_use) & (input_sel_cnt == ${k}-1)) +//: pre2cal1d_data <= { +//: ); +//: if($k > 1) { +//: foreach my $i(0..$k-2){ +//: my $j = $k -$i -1; +//: print " sdp2pdp_dp_$j, "; +//: } +//: } +//: print qq( +//: sdp2pdp_dp_0}; +//: end +//: ); +//: +//: print qq( +//: reg sdp2pdp_vld_f; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +//: if (!nvdla_core_rstn) +//: sdp2pdp_vld_f <= 1'b0; +//: else if((sdp2pdp_valid_use & sdp2pdp_ready_use) & (input_sel_cnt == ${k}-1)) +//: sdp2pdp_vld_f <= 1'b1; +//: else if(pre2cal1d_prdy) +//: sdp2pdp_vld_f <= 1'b0; +//: end +//: assign pre2cal1d_pvld = sdp2pdp_vld_f; +//: ); +//: } +//: elsif($sdpth == $pdpth) { +//: print qq( +//: wire [${pdpbw}-1:0] pre2cal1d_data; +//: assign sdp2pdp_ready_use = pre2cal1d_prdy; +//: assign pre2cal1d_pvld = sdp2pdp_valid_use; +//: assign pre2cal1d_data = sdp2pdp_pd_use; +//: ); +//: } +//============================================================== +//Data info path pre process +//-------------------------------------------------------------- +wire pre2cal1d_load; +assign pre2cal1d_load = pre2cal1d_pvld & pre2cal1d_prdy; +//pos_c, 8B data position within 32B +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pos_c <= 0; + end else begin + if(pre2cal1d_load) begin + if(last_c) + pos_c <= 0; + else + pos_c <= pos_c + 1'b1; + end + end +end +//: my $pdpth = 1; +//: my $atomicm = 8; +//: my $k = int( $atomicm/$pdpth ) -1; +//: print qq( +//: assign last_c = pre2cal1d_load & (pos_c == 5'd${k}); +//: ); +//width direction +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + w_cnt[12:0] <= {13{1'b0}}; + end else begin + if(last_c) begin + if(line_end) + w_cnt[12:0] <= 13'd0; + else + w_cnt[12:0] <= w_cnt[12:0] + 1'b1; + end + end +end +assign line_end = last_c & (w_cnt[12:0] == reg2dp_cube_in_width[12:0]); +//height direction +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + line_cnt[12:0] <= {13{1'b0}}; + end else begin + if(line_end) begin + if(surf_end) + line_cnt[12:0] <= 13'd0; + else + line_cnt[12:0] <= line_cnt[12:0] + 1'b1; + end + end +end +assign surf_end = line_end & (line_cnt[12:0] == reg2dp_cube_in_height[12:0]); +//surface/Channel direction +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + surf_cnt <= 0; + end else begin + if(surf_end) begin + if(split_end) + surf_cnt <= 0; + else + surf_cnt <= surf_cnt + 1'b1; + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign split_end = surf_end & (surf_cnt == reg2dp_cube_in_channel[12:${k}]); +//: ); +assign cube_end = split_end ; +assign b_sync = line_end; +assign pre2cal1d_info = {cube_end,split_end,surf_end,line_end,b_sync,pos_c[2:0],4'd0};// need update pos_c width into 5bits at final +assign pre2cal1d_pd = {pre2cal1d_info,pre2cal1d_data}; +//////////////////////////// +//////////////////////////// +endmodule // NV_NVDLA_PDP_CORE_preproc +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_SDPIN_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -rd_reg -rand_none -ram_bypass -d 4 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_SDPIN_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +input [7:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [7:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] ro_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 3'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [1:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 3'd4 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int && !ro_rd_prdy); +reg [2:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] ro_rd_pd; // output data register +wire rd_req_next = (ro_rd_pvld_p || (ro_rd_pvld_int && !ro_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + end else begin + ro_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ro_rd_pd <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ro_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_SDPIN_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_SDPIN_ro_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_SDPIN_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [7:0] Di0; +input [1:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8] } +endmodule // vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +//vmw: Memory vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +//vmw: Address-size 2 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_SDPIN_ro_fifo_flopram_rwsa_4x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v new file mode 100644 index 0000000..4377f08 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v @@ -0,0 +1,852 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_unit1d.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_unit1d ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,average_pooling_en //|< i + ,cur_datin_disable //|< i + ,last_out_en //|< i + ,pdma2pdp_pd //|< i + ,pdma2pdp_pvld //|< i + ,pdp_din_lc_f //|< i + ,pooling_din_1st //|< i + ,pooling_din_last //|< i + ,pooling_out_prdy //|< i + ,pooling_type_cfg //|< i + ,pooling_unit_en //|< i +// ,reg2dp_int16_en //|< i +// ,reg2dp_int8_en //|< i + ,pdma2pdp_prdy //|> o + ,pooling_out //|> o + ,pooling_out_pvld //|> o + ); +////////////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input average_pooling_en; +input cur_datin_disable; +input last_out_en; +input [1*(8 +3)+6:0] pdma2pdp_pd; +input pdma2pdp_pvld; +input pdp_din_lc_f; +input pooling_din_1st; +input pooling_din_last; +input pooling_out_prdy; +input [1:0] pooling_type_cfg; +input pooling_unit_en; +//input reg2dp_int16_en; +//input reg2dp_int8_en; +output pdma2pdp_prdy; +output [1*(8 +3)+3:0] pooling_out; +output pooling_out_pvld; +////////////////////////////////////////////////////////////////////////////////// +wire add_out_rdy; +wire add_out_vld; +wire [4:0] buf_sel; +wire [4:0] buf_sel_sync; +wire [4:0] buf_sel_sync_use; +wire [4:0] buf_sel_sync_use_d4; +wire cur_datin_disable_sync; +wire cur_datin_disable_sync_use; +wire cur_datin_disable_sync_use_d4; +wire data_buf_lc; +wire data_buf_lc_d4; +wire [1*(8 +3)-1:0] datain_ext; +wire [1*(8 +3)-1:0] datain_ext_sync; +//wire [16:0] fp16_pool_sum_0; +//wire [16:0] fp16_pool_sum_1; +//wire [16:0] fp16_pool_sum_2; +//wire [16:0] fp16_pool_sum_3; +//wire fp16_pool_sum_prdy; +//wire fp16_pool_sum_pvld; +//wire fp_addin_rdy; +//wire fp_addin_vld; +//wire [87:0] fp_cur_pooling_dat; +//wire [87:0] fp_datain_ext; +//wire fp_mean_pool_cfg; +//wire [67:0] fp_pool_sum; +//wire [67:0] fp_pool_sum_result0; +//wire [67:0] fp_pool_sum_result1; +//wire [67:0] fp_pool_sum_result2; +//wire [67:0] fp_pool_sum_result3; +//wire [87:0] fp_pool_sum_use0; +//wire [87:0] fp_pool_sum_use1; +//wire [87:0] fp_pool_sum_use2; +//wire [87:0] fp_pool_sum_use3; +wire [1*(8 +3)-1:0] int_pool_cur_dat; +wire [1*(8 +3)-1:0] int_pool_datin_ext; +wire [1*(8 +3)-1:0] int_pooling; +wire [1*(8 +3)-1:0] int_pooling_sync; +wire load_din; +wire pdma2pdp_prdy_f; +wire [4:0] pdp_din_cpos; +wire pdp_din_lc_f_sync; +wire [3:0] pdp_din_wpos; +wire pipe_in_rdy; +wire pipe_out_rdy; +wire pipe_out_vld; +wire pool_fun_vld; +wire pooling_din_1st_sync; +wire pooling_din_last_sync; +wire pooling_din_last_sync_use; +wire pooling_din_last_sync_use_d4; +wire [2:0] pooling_out_size; +wire [2:0] pooling_out_size_sync; +wire [2:0] pooling_out_size_sync_use; +wire [2:0] pooling_out_size_sync_use_d4; +wire pooling_out_vld; +wire [1*(8 +3)-1:0] pooling_result; +reg [1*(8 +3)-1:0] cur_pooling_dat; +//reg [67:0] fp_pool_sum_result0_d3; +//reg [67:0] fp_pool_sum_result0_d4; +//reg [67:0] fp_pool_sum_result1_d3; +//reg [67:0] fp_pool_sum_result1_d4; +//reg [67:0] fp_pool_sum_result2_d3; +//reg [67:0] fp_pool_sum_result2_d4; +//reg [67:0] fp_pool_sum_result3_d3; +//reg [67:0] fp_pool_sum_result3_d4; +//: my $bw = 1*(8 +3); +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "reg [${bw}-1:0] latch_result${m}_d3; \n"; +//: print "reg [${bw}+3:0] flush_out${m}; \n"; +//: print "wire [${bw}-1:0] data_buf${m}; \n"; +//: print "wire [${bw}-1:0] latch_result${m}; \n"; +//: print "wire [${bw}-1:0] latch_result${m}_d4; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [11-1:0] latch_result0_d3; +reg [11+3:0] flush_out0; +wire [11-1:0] data_buf0; +wire [11-1:0] latch_result0; +wire [11-1:0] latch_result0_d4; +reg [11-1:0] latch_result1_d3; +reg [11+3:0] flush_out1; +wire [11-1:0] data_buf1; +wire [11-1:0] latch_result1; +wire [11-1:0] latch_result1_d4; +reg [11-1:0] latch_result2_d3; +reg [11+3:0] flush_out2; +wire [11-1:0] data_buf2; +wire [11-1:0] latch_result2; +wire [11-1:0] latch_result2_d4; +reg [11-1:0] latch_result3_d3; +reg [11+3:0] flush_out3; +wire [11-1:0] data_buf3; +wire [11-1:0] latch_result3; +wire [11-1:0] latch_result3_d4; +reg [11-1:0] latch_result4_d3; +reg [11+3:0] flush_out4; +wire [11-1:0] data_buf4; +wire [11-1:0] latch_result4; +wire [11-1:0] latch_result4_d4; +reg [11-1:0] latch_result5_d3; +reg [11+3:0] flush_out5; +wire [11-1:0] data_buf5; +wire [11-1:0] latch_result5; +wire [11-1:0] latch_result5_d4; +reg [11-1:0] latch_result6_d3; +reg [11+3:0] flush_out6; +wire [11-1:0] data_buf6; +wire [11-1:0] latch_result6; +wire [11-1:0] latch_result6_d4; +reg [11-1:0] latch_result7_d3; +reg [11+3:0] flush_out7; +wire [11-1:0] data_buf7; +wire [11-1:0] latch_result7; +wire [11-1:0] latch_result7_d4; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [4:0] pooling_cnt; +reg [1*(8 +3)+3:0] pooling_out; +reg [2:0] pooling_size; +////////////////////////////////////////////////////////////////////////////////// +//======================================================= +//1D pooling unit +//------------------------------------------------------- +//assign fp_mean_pool_cfg = (reg2dp_fp16_en & average_pooling_en); +// interface +assign pdp_din_wpos = pdma2pdp_pd[1*(8 +3)+3:1*(8 +3)]; +assign pdp_din_cpos = {2'd0,pdma2pdp_pd[1*(8 +3)+6:1*(8 +3)+4]}; +assign buf_sel = pdp_din_cpos; +assign load_din = pdma2pdp_pvld & pdma2pdp_prdy_f & (~cur_datin_disable) & pooling_unit_en; +assign pdma2pdp_prdy_f = pipe_in_rdy; +assign pdma2pdp_prdy = pdma2pdp_prdy_f; +//========================================================= +//POOLING FUNCTION DEFINITION +// +//---- ----------------------------------------------------- +//: my $k = 8 +3; +//: print qq( +//: function [${k}-1:0] pooling_MIN; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function [11-1:0] pooling_MIN; +input[11-1:0] data0; +input[11-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + reg min_int_ff; + begin + min_int_ff = ($signed(data1)> $signed(data0)) ; + pooling_MIN = (min_int_ff ) ? data0 : data1; + end + endfunction +//: my $k = 8 +3; +//: print qq( +//: function [${k}-1:0] pooling_MAX; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function [11-1:0] pooling_MAX; +input[11-1:0] data0; +input[11-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + reg max_int_ff; + begin + max_int_ff = ($signed(data0)> $signed(data1)) ; + pooling_MAX = (max_int_ff ) ? data0 : data1; + end + endfunction +//: my $k = 8 +3; +//: print qq( +//: function [${k}-1:0] pooling_SUM; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function [11-1:0] pooling_SUM; +input[11-1:0] data0; +input[11-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + begin +//spyglass disable_block W484 + pooling_SUM = $signed(data1) + $signed(data0); +//spyglass enable_block W484 + end + endfunction +//pooling result +//: my $k = 1*(8 +3); +//: print qq( +//: function [${k}-1:0] pooling_fun; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +function [11-1:0] pooling_fun; +input[11-1:0] data0; +input[11-1:0] data1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + input[1:0] pooling_type; + reg min_pooling; + reg max_pooling; + reg mean_pooling; + begin + min_pooling = (pooling_type== 2'h2 ); + max_pooling = (pooling_type== 2'h1 ); + mean_pooling = (pooling_type== 2'h0 ); +//: my $K = 1; +//: my $P = (8 +3); +//: foreach my $m (0..$K-1) { +//: print qq( +//: pooling_fun[${P}*${m}+${P}-1:${P}*${m}] = mean_pooling? pooling_SUM(data0[${P}*${m}+${P}-1:${P}*${m}],data1[${P}*${m}+${P}-1:${P}*${m}]) : +//: min_pooling ? (pooling_MIN(data0[${P}*${m}+${P}-1:${P}*${m}],data1[${P}*${m}+${P}-1:${P}*${m}])) : +//: max_pooling ? (pooling_MAX(data0[${P}*${m}+${P}-1:${P}*${m}],data1[${P}*${m}+${P}-1:${P}*${m}])) : 0; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +pooling_fun[11*0+11-1:11*0] = mean_pooling? pooling_SUM(data0[11*0+11-1:11*0],data1[11*0+11-1:11*0]) : +min_pooling ? (pooling_MIN(data0[11*0+11-1:11*0],data1[11*0+11-1:11*0])) : +max_pooling ? (pooling_MAX(data0[11*0+11-1:11*0],data1[11*0+11-1:11*0])) : 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +endfunction +//========================================================= +// pooling real size +// +//--------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_size[2:0] <= {3{1'b0}}; + end else begin + if(load_din & pdp_din_lc_f) begin + if(pooling_din_last) + pooling_size[2:0] <= 3'd0; + else + pooling_size[2:0] <= pooling_size + 1; + end + end +end +assign pooling_out_size = pooling_size; +////==================================================================== +//// pooling data +//// +////-------------------------------------------------------------------- +assign datain_ext = pdma2pdp_pd[1*(8 +3)-1:0]; +always @(*) begin + case(buf_sel) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: cur_pooling_dat = data_buf${m}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +5'd0: cur_pooling_dat = data_buf0; +5'd1: cur_pooling_dat = data_buf1; +5'd2: cur_pooling_dat = data_buf2; +5'd3: cur_pooling_dat = data_buf3; +5'd4: cur_pooling_dat = data_buf4; +5'd5: cur_pooling_dat = data_buf5; +5'd6: cur_pooling_dat = data_buf6; +5'd7: cur_pooling_dat = data_buf7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//VCS coverage off + default: cur_pooling_dat = 0; +//VCS coverage on + endcase +end +//-------------------------------------------------------------------- +//pooling function for fp16 average mode +//assign fp_datain_ext = datain_ext[87:0] ; +//assign fp_cur_pooling_dat = cur_pooling_dat[87:0]; +// +//assign fp_addin_vld = pdma2pdp_pvld & pipe_in_rdy & fp_mean_pool_cfg; +//cal1d_fp16_pool_sum u_cal1d_fp16_pool_sum ( +// .inp_a_0 (fp_cur_pooling_dat[16:0]) //|< w +// ,.inp_a_1 (fp_cur_pooling_dat[38:22]) //|< w +// ,.inp_a_2 (fp_cur_pooling_dat[60:44]) //|< w +// ,.inp_a_3 (fp_cur_pooling_dat[82:66]) //|< w +// ,.inp_b_0 (fp_datain_ext[16:0]) //|< w +// ,.inp_b_1 (fp_datain_ext[38:22]) //|< w +// ,.inp_b_2 (fp_datain_ext[60:44]) //|< w +// ,.inp_b_3 (fp_datain_ext[82:66]) //|< w +// ,.inp_in_pvld (fp_addin_vld) //|< w +// ,.inp_out_prdy (fp16_pool_sum_prdy) //|< w +// ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +// ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16) //|< i +// ,.inp_in_prdy (fp_addin_rdy) //|> w +// ,.inp_out_pvld (fp16_pool_sum_pvld) //|> w +// ,.out_z_0 (fp16_pool_sum_0[16:0]) //|> w +// ,.out_z_1 (fp16_pool_sum_1[16:0]) //|> w +// ,.out_z_2 (fp16_pool_sum_2[16:0]) //|> w +// ,.out_z_3 (fp16_pool_sum_3[16:0]) //|> w +// ); +//assign fp_pool_sum = {fp16_pool_sum_3,fp16_pool_sum_2,fp16_pool_sum_1,fp16_pool_sum_0}; +//////////////////// +//below value 4 means NVDLA_HLS_ADD17_LATENCY +//: my $STAGE = 4; +//: my $WID = 1*(8 +3)*2 + 12; +//: print qq( +//: wire [${WID}-1:0] pipe_out_pd; +//: wire [${WID}-1:0] pipe_dp_0; +//: wire pipe_vld_0; +//: wire pipe_rdy_$STAGE; +//: assign pipe_vld_0 = pdma2pdp_pvld; +//: assign pipe_dp_0 = {pooling_din_last,pooling_out_size[2:0],cur_datin_disable,buf_sel[4:0],pdp_din_lc_f,pooling_din_1st,datain_ext,int_pooling}; +//: ); +//: foreach my $m (0..$STAGE-1) { +//: my $n = $m+1; +//: print qq( +//: wire pipe_rdy_$m; +//: reg pipe_vld_$n; +//: reg [$WID-1:0] pipe_dp_$n; +//: ); +//: } +//: foreach my $m (0..$STAGE-1) { +//: my $n = $m+1; +//: print qq( +//: assign pipe_rdy_$m = ~pipe_vld_$n || pipe_rdy_$n; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: begin +//: if (!nvdla_core_rstn) +//: pipe_vld_$n <= 1'b0; +//: else if(pipe_vld_$m) +//: pipe_vld_$n <= 1'b1; +//: else if(pipe_rdy_$n) +//: pipe_vld_$n <= 1'b0; +//: end +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: begin +//: if (!nvdla_core_rstn) +//: pipe_dp_$n <= ${WID}'d0; +//: else if(pipe_vld_${m} & pipe_rdy_${m}) +//: pipe_dp_$n <= pipe_dp_$m; +//: end +//: ); +//: } +//: print qq( +//: assign pipe_rdy_$STAGE = pipe_out_rdy; +//: assign pipe_out_vld = pipe_vld_$STAGE; +//: assign pipe_out_pd = pipe_dp_$STAGE; +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [34-1:0] pipe_out_pd; +wire [34-1:0] pipe_dp_0; +wire pipe_vld_0; +wire pipe_rdy_4; +assign pipe_vld_0 = pdma2pdp_pvld; +assign pipe_dp_0 = {pooling_din_last,pooling_out_size[2:0],cur_datin_disable,buf_sel[4:0],pdp_din_lc_f,pooling_din_1st,datain_ext,int_pooling}; + +wire pipe_rdy_0; +reg pipe_vld_1; +reg [34-1:0] pipe_dp_1; + +wire pipe_rdy_1; +reg pipe_vld_2; +reg [34-1:0] pipe_dp_2; + +wire pipe_rdy_2; +reg pipe_vld_3; +reg [34-1:0] pipe_dp_3; + +wire pipe_rdy_3; +reg pipe_vld_4; +reg [34-1:0] pipe_dp_4; + +assign pipe_rdy_0 = ~pipe_vld_1 || pipe_rdy_1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_vld_1 <= 1'b0; +else if(pipe_vld_0) +pipe_vld_1 <= 1'b1; +else if(pipe_rdy_1) +pipe_vld_1 <= 1'b0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_dp_1 <= 34'd0; +else if(pipe_vld_0 & pipe_rdy_0) +pipe_dp_1 <= pipe_dp_0; +end + +assign pipe_rdy_1 = ~pipe_vld_2 || pipe_rdy_2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_vld_2 <= 1'b0; +else if(pipe_vld_1) +pipe_vld_2 <= 1'b1; +else if(pipe_rdy_2) +pipe_vld_2 <= 1'b0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_dp_2 <= 34'd0; +else if(pipe_vld_1 & pipe_rdy_1) +pipe_dp_2 <= pipe_dp_1; +end + +assign pipe_rdy_2 = ~pipe_vld_3 || pipe_rdy_3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_vld_3 <= 1'b0; +else if(pipe_vld_2) +pipe_vld_3 <= 1'b1; +else if(pipe_rdy_3) +pipe_vld_3 <= 1'b0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_dp_3 <= 34'd0; +else if(pipe_vld_2 & pipe_rdy_2) +pipe_dp_3 <= pipe_dp_2; +end + +assign pipe_rdy_3 = ~pipe_vld_4 || pipe_rdy_4; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_vld_4 <= 1'b0; +else if(pipe_vld_3) +pipe_vld_4 <= 1'b1; +else if(pipe_rdy_4) +pipe_vld_4 <= 1'b0; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +begin +if (!nvdla_core_rstn) +pipe_dp_4 <= 34'd0; +else if(pipe_vld_3 & pipe_rdy_3) +pipe_dp_4 <= pipe_dp_3; +end + +assign pipe_rdy_4 = pipe_out_rdy; +assign pipe_out_vld = pipe_vld_4; +assign pipe_out_pd = pipe_dp_4; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pipe_in_rdy = pipe_rdy_0; +//////::dla_pipe -stages NVDLA_HLS_ADD17_LATENCY -i pipe_in -o pipe_out -width 185; +assign pipe_out_rdy = add_out_rdy; +//assign fp16_pool_sum_prdy = fp_mean_pool_cfg & add_out_rdy & pipe_out_vld; +assign add_out_vld = pipe_out_vld; +assign add_out_rdy = ~pooling_out_vld | pooling_out_prdy; +//////////////////// +assign int_pooling_sync = pipe_out_pd[1*(8 +3)-1:0]; +assign datain_ext_sync = pipe_out_pd[1*(8 +3)*2-1:1*(8 +3)]; +assign pooling_din_1st_sync = pipe_out_pd[1*(8 +3)*2]; +assign pdp_din_lc_f_sync = pipe_out_pd[1*(8 +3)*2+1]; +assign buf_sel_sync = pipe_out_pd[1*(8 +3)*2+6:1*(8 +3)*2+2]; +assign cur_datin_disable_sync= pipe_out_pd[1*(8 +3)*2+7]; +assign pooling_out_size_sync = pipe_out_pd[1*(8 +3)*2+10:1*(8 +3)*2+8]; +assign pooling_din_last_sync = pipe_out_pd[1*(8 +3)*2+11]; +//////////////////// +////for NVDLA_HLS_ADD17_LATENCY==3 +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// fp_pool_sum_result0_d3 <= {68{1'b0}}; +// fp_pool_sum_result1_d3 <= {68{1'b0}}; +// fp_pool_sum_result2_d3 <= {68{1'b0}}; +// fp_pool_sum_result3_d3 <= {68{1'b0}}; +// end else begin +// if(add_out_vld & add_out_rdy) begin +// if(pooling_din_1st_sync) begin +// case(buf_sel_sync) +// 2'd0: fp_pool_sum_result0_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// 2'd1: fp_pool_sum_result1_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// 2'd2: fp_pool_sum_result2_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// 2'd3: fp_pool_sum_result3_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// //VCS coverage off +// default: begin +// fp_pool_sum_result0_d3 <= fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d3 <= fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d3 <= fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d3 <= fp_pool_sum_result3_d3; +// end +// //VCS coverage on +// endcase +// end else begin +// case(buf_sel_sync) +// 2'd0: fp_pool_sum_result0_d3 <= fp_pool_sum; +// 2'd1: fp_pool_sum_result1_d3 <= fp_pool_sum; +// 2'd2: fp_pool_sum_result2_d3 <= fp_pool_sum; +// 2'd3: fp_pool_sum_result3_d3 <= fp_pool_sum; +// //VCS coverage off +// default: begin +// fp_pool_sum_result0_d3 <= fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d3 <= fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d3 <= fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d3 <= fp_pool_sum_result3_d3; +// end +// //VCS coverage on +// endcase +// end +// end +// end +//end +// +////for NVDLA_HLS_ADD17_LATENCY==4 +//always @( +// pooling_din_1st_sync +// or buf_sel_sync +// or datain_ext_sync +// or fp_pool_sum_result0_d3 +// or fp_pool_sum_result1_d3 +// or fp_pool_sum_result2_d3 +// or fp_pool_sum_result3_d3 +// or fp_pool_sum +// ) begin +// if(pooling_din_1st_sync) begin +// fp_pool_sum_result0_d4 = (buf_sel_sync==2'd0)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d4 = (buf_sel_sync==2'd1)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d4 = (buf_sel_sync==2'd2)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d4 = (buf_sel_sync==2'd3)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result3_d3; +// end else begin +// fp_pool_sum_result0_d4 = (buf_sel_sync==2'd0)? fp_pool_sum : fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d4 = (buf_sel_sync==2'd1)? fp_pool_sum : fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d4 = (buf_sel_sync==2'd2)? fp_pool_sum : fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d4 = (buf_sel_sync==2'd3)? fp_pool_sum : fp_pool_sum_result3_d3; +// end +//end +// +//assign fp_pool_sum_result0 = fp_pool_sum_result0_d4; +//assign fp_pool_sum_result1 = fp_pool_sum_result1_d4; +//assign fp_pool_sum_result2 = fp_pool_sum_result2_d4; +//assign fp_pool_sum_result3 = fp_pool_sum_result3_d4; +// +//assign fp_pool_sum_use0 = {5'd0,fp_pool_sum_result0[67:51],5'd0,fp_pool_sum_result0[50:34],5'd0,fp_pool_sum_result0[33:17],5'd0,fp_pool_sum_result0[16:0]}; +//assign fp_pool_sum_use1 = {5'd0,fp_pool_sum_result1[67:51],5'd0,fp_pool_sum_result1[50:34],5'd0,fp_pool_sum_result1[33:17],5'd0,fp_pool_sum_result1[16:0]}; +//assign fp_pool_sum_use2 = {5'd0,fp_pool_sum_result2[67:51],5'd0,fp_pool_sum_result2[50:34],5'd0,fp_pool_sum_result2[33:17],5'd0,fp_pool_sum_result2[16:0]}; +//assign fp_pool_sum_use3 = {5'd0,fp_pool_sum_result3[67:51],5'd0,fp_pool_sum_result3[50:34],5'd0,fp_pool_sum_result3[33:17],5'd0,fp_pool_sum_result3[16:0]}; +////////////////////////// +assign pool_fun_vld = load_din; +assign int_pool_datin_ext = pool_fun_vld ? datain_ext : 0; +assign int_pool_cur_dat = pool_fun_vld ? cur_pooling_dat : 0; +assign int_pooling = pooling_fun(int_pool_cur_dat, int_pool_datin_ext,pooling_type_cfg[1:0]); +assign pooling_result = (pooling_din_1st_sync ? datain_ext_sync : int_pooling_sync); +//-------------------------------------------------------------------- +//for NVDLA_HLS_ADD17_LATENCY==3 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "latch_result${m}_d3 <= 0; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +latch_result0_d3 <= 0; +latch_result1_d3 <= 0; +latch_result2_d3 <= 0; +latch_result3_d3 <= 0; +latch_result4_d3 <= 0; +latch_result5_d3 <= 0; +latch_result6_d3 <= 0; +latch_result7_d3 <= 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if(add_out_vld & add_out_rdy) begin + case(buf_sel_sync) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: latch_result${m}_d3 <= pooling_result; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +5'd0: latch_result0_d3 <= pooling_result; +5'd1: latch_result1_d3 <= pooling_result; +5'd2: latch_result2_d3 <= pooling_result; +5'd3: latch_result3_d3 <= pooling_result; +5'd4: latch_result4_d3 <= pooling_result; +5'd5: latch_result5_d3 <= pooling_result; +5'd6: latch_result6_d3 <= pooling_result; +5'd7: latch_result7_d3 <= pooling_result; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//VCS coverage off + default: begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "latch_result${m}_d3 <= latch_result${m}_d3; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +latch_result0_d3 <= latch_result0_d3; +latch_result1_d3 <= latch_result1_d3; +latch_result2_d3 <= latch_result2_d3; +latch_result3_d3 <= latch_result3_d3; +latch_result4_d3 <= latch_result4_d3; +latch_result5_d3 <= latch_result5_d3; +latch_result6_d3 <= latch_result6_d3; +latch_result7_d3 <= latch_result7_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +//VCS coverage on + endcase + end + end +end +//for NVDLA_HLS_ADD17_LATENCY==4 +assign pooling_out_size_sync_use_d4 = pooling_out_size_sync; +assign pooling_din_last_sync_use_d4 = pooling_din_last_sync; +assign buf_sel_sync_use_d4 = buf_sel_sync; +assign cur_datin_disable_sync_use_d4 = cur_datin_disable_sync; +assign data_buf_lc_d4 = pdp_din_lc_f_sync; +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "assign latch_result${m}_d4 = (buf_sel_sync==5'd$m)? pooling_result : latch_result${m}_d3; \n"; +//: print "assign latch_result$m = latch_result${m}_d4; \n"; +//: print "assign data_buf$m = latch_result$m ; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign latch_result0_d4 = (buf_sel_sync==5'd0)? pooling_result : latch_result0_d3; +assign latch_result0 = latch_result0_d4; +assign data_buf0 = latch_result0 ; +assign latch_result1_d4 = (buf_sel_sync==5'd1)? pooling_result : latch_result1_d3; +assign latch_result1 = latch_result1_d4; +assign data_buf1 = latch_result1 ; +assign latch_result2_d4 = (buf_sel_sync==5'd2)? pooling_result : latch_result2_d3; +assign latch_result2 = latch_result2_d4; +assign data_buf2 = latch_result2 ; +assign latch_result3_d4 = (buf_sel_sync==5'd3)? pooling_result : latch_result3_d3; +assign latch_result3 = latch_result3_d4; +assign data_buf3 = latch_result3 ; +assign latch_result4_d4 = (buf_sel_sync==5'd4)? pooling_result : latch_result4_d3; +assign latch_result4 = latch_result4_d4; +assign data_buf4 = latch_result4 ; +assign latch_result5_d4 = (buf_sel_sync==5'd5)? pooling_result : latch_result5_d3; +assign latch_result5 = latch_result5_d4; +assign data_buf5 = latch_result5 ; +assign latch_result6_d4 = (buf_sel_sync==5'd6)? pooling_result : latch_result6_d3; +assign latch_result6 = latch_result6_d4; +assign data_buf6 = latch_result6 ; +assign latch_result7_d4 = (buf_sel_sync==5'd7)? pooling_result : latch_result7_d3; +assign latch_result7 = latch_result7_d4; +assign data_buf7 = latch_result7 ; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//========== +//info select +assign pooling_out_size_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ pooling_out_size_sync_use_d4 /* : pooling_out_size_sync_use_d3 */; +assign pooling_din_last_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ pooling_din_last_sync_use_d4 /* : pooling_din_last_sync_use_d3 */; +assign buf_sel_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ buf_sel_sync_use_d4 /* : buf_sel_sync_use_d3 */; +assign cur_datin_disable_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ cur_datin_disable_sync_use_d4/* : cur_datin_disable_sync_use_d3*/; +assign data_buf_lc = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ data_buf_lc_d4 /* : data_buf_lc_d3 */; +//============================================================ +//pooling send out +// +//------------------------------------------------------------ +//for NVDLA_HLS_ADD17_LATENCY==3 +//&Always posedge; +// if(add_out_vld) +// pooling_out_vld_d3 <0=1'b1; +// else if(pooling_out_prdy) +// pooling_out_vld_d3 <0= 1'b0; +//&End; +assign pooling_out_vld = /*(NVDLA_HLS_ADD17_LATENCY == 4) ? */add_out_vld/* : pooling_out_vld_d3*/; +assign pooling_out_pvld = pooling_out_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_cnt <= 0; + end else begin + if(pooling_out_vld & pooling_out_prdy & ((pooling_din_last_sync_use & (~cur_datin_disable_sync_use)) | last_out_en))begin +//: my $k = int(8 / 1); +//: print qq( +//: if(pooling_cnt==(5'd${k} -1)) +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +if(pooling_cnt==(5'd8 -1)) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + pooling_cnt <= 0; + else + pooling_cnt <= pooling_cnt +1'd1; + end + end + end +always @(*) begin + if(last_out_en) begin + case(pooling_cnt) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: pooling_out = flush_out$m; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +5'd0: pooling_out = flush_out0; +5'd1: pooling_out = flush_out1; +5'd2: pooling_out = flush_out2; +5'd3: pooling_out = flush_out3; +5'd4: pooling_out = flush_out4; +5'd5: pooling_out = flush_out5; +5'd6: pooling_out = flush_out6; +5'd7: pooling_out = flush_out7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default: pooling_out = 0; + endcase + end else begin + case(pooling_cnt) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf${m}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +5'd0: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf0}; +5'd1: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf1}; +5'd2: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf2}; +5'd3: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf3}; +5'd4: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf4}; +5'd5: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf5}; +5'd6: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf6}; +5'd7: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf7}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + default: pooling_out = 0; + endcase + end +end +////////////////////////////////////////////// +//output latch in line end for flush +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "flush_out$m <= 0; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +flush_out0 <= 0; +flush_out1 <= 0; +flush_out2 <= 0; +flush_out3 <= 0; +flush_out4 <= 0; +flush_out5 <= 0; +flush_out6 <= 0; +flush_out7 <= 0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if(pooling_din_last_sync_use & (~cur_datin_disable_sync_use)) begin + case(buf_sel_sync_use) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: flush_out$m <= {data_buf_lc,pooling_out_size_sync_use,data_buf${m}}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +5'd0: flush_out0 <= {data_buf_lc,pooling_out_size_sync_use,data_buf0}; +5'd1: flush_out1 <= {data_buf_lc,pooling_out_size_sync_use,data_buf1}; +5'd2: flush_out2 <= {data_buf_lc,pooling_out_size_sync_use,data_buf2}; +5'd3: flush_out3 <= {data_buf_lc,pooling_out_size_sync_use,data_buf3}; +5'd4: flush_out4 <= {data_buf_lc,pooling_out_size_sync_use,data_buf4}; +5'd5: flush_out5 <= {data_buf_lc,pooling_out_size_sync_use,data_buf5}; +5'd6: flush_out6 <= {data_buf_lc,pooling_out_size_sync_use,data_buf6}; +5'd7: flush_out7 <= {data_buf_lc,pooling_out_size_sync_use,data_buf7}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//VCS coverage off + default: begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "flush_out$m <= flush_out${m}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +flush_out0 <= flush_out0; +flush_out1 <= flush_out1; +flush_out2 <= flush_out2; +flush_out3 <= flush_out3; +flush_out4 <= flush_out4; +flush_out5 <= flush_out5; +flush_out6 <= flush_out6; +flush_out7 <= flush_out7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +//VCS coverage on + endcase + end + end +end +////////////////////////////////////////////// +endmodule // NV_NVDLA_PDP_CORE_unit1d diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v.vcp new file mode 100644 index 0000000..5998248 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v.vcp @@ -0,0 +1,541 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_CORE_unit1d.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_CORE_unit1d ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,average_pooling_en //|< i + ,cur_datin_disable //|< i + ,last_out_en //|< i + ,pdma2pdp_pd //|< i + ,pdma2pdp_pvld //|< i + ,pdp_din_lc_f //|< i + ,pooling_din_1st //|< i + ,pooling_din_last //|< i + ,pooling_out_prdy //|< i + ,pooling_type_cfg //|< i + ,pooling_unit_en //|< i +// ,reg2dp_int16_en //|< i +// ,reg2dp_int8_en //|< i + ,pdma2pdp_prdy //|> o + ,pooling_out //|> o + ,pooling_out_pvld //|> o + ); +////////////////////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input average_pooling_en; +input cur_datin_disable; +input last_out_en; +input [1*(8 +3)+6:0] pdma2pdp_pd; +input pdma2pdp_pvld; +input pdp_din_lc_f; +input pooling_din_1st; +input pooling_din_last; +input pooling_out_prdy; +input [1:0] pooling_type_cfg; +input pooling_unit_en; +//input reg2dp_int16_en; +//input reg2dp_int8_en; +output pdma2pdp_prdy; +output [1*(8 +3)+3:0] pooling_out; +output pooling_out_pvld; +////////////////////////////////////////////////////////////////////////////////// +wire add_out_rdy; +wire add_out_vld; +wire [4:0] buf_sel; +wire [4:0] buf_sel_sync; +wire [4:0] buf_sel_sync_use; +wire [4:0] buf_sel_sync_use_d4; +wire cur_datin_disable_sync; +wire cur_datin_disable_sync_use; +wire cur_datin_disable_sync_use_d4; +wire data_buf_lc; +wire data_buf_lc_d4; +wire [1*(8 +3)-1:0] datain_ext; +wire [1*(8 +3)-1:0] datain_ext_sync; +//wire [16:0] fp16_pool_sum_0; +//wire [16:0] fp16_pool_sum_1; +//wire [16:0] fp16_pool_sum_2; +//wire [16:0] fp16_pool_sum_3; +//wire fp16_pool_sum_prdy; +//wire fp16_pool_sum_pvld; +//wire fp_addin_rdy; +//wire fp_addin_vld; +//wire [87:0] fp_cur_pooling_dat; +//wire [87:0] fp_datain_ext; +//wire fp_mean_pool_cfg; +//wire [67:0] fp_pool_sum; +//wire [67:0] fp_pool_sum_result0; +//wire [67:0] fp_pool_sum_result1; +//wire [67:0] fp_pool_sum_result2; +//wire [67:0] fp_pool_sum_result3; +//wire [87:0] fp_pool_sum_use0; +//wire [87:0] fp_pool_sum_use1; +//wire [87:0] fp_pool_sum_use2; +//wire [87:0] fp_pool_sum_use3; +wire [1*(8 +3)-1:0] int_pool_cur_dat; +wire [1*(8 +3)-1:0] int_pool_datin_ext; +wire [1*(8 +3)-1:0] int_pooling; +wire [1*(8 +3)-1:0] int_pooling_sync; +wire load_din; +wire pdma2pdp_prdy_f; +wire [4:0] pdp_din_cpos; +wire pdp_din_lc_f_sync; +wire [3:0] pdp_din_wpos; +wire pipe_in_rdy; +wire pipe_out_rdy; +wire pipe_out_vld; +wire pool_fun_vld; +wire pooling_din_1st_sync; +wire pooling_din_last_sync; +wire pooling_din_last_sync_use; +wire pooling_din_last_sync_use_d4; +wire [2:0] pooling_out_size; +wire [2:0] pooling_out_size_sync; +wire [2:0] pooling_out_size_sync_use; +wire [2:0] pooling_out_size_sync_use_d4; +wire pooling_out_vld; +wire [1*(8 +3)-1:0] pooling_result; +reg [1*(8 +3)-1:0] cur_pooling_dat; +//reg [67:0] fp_pool_sum_result0_d3; +//reg [67:0] fp_pool_sum_result0_d4; +//reg [67:0] fp_pool_sum_result1_d3; +//reg [67:0] fp_pool_sum_result1_d4; +//reg [67:0] fp_pool_sum_result2_d3; +//reg [67:0] fp_pool_sum_result2_d4; +//reg [67:0] fp_pool_sum_result3_d3; +//reg [67:0] fp_pool_sum_result3_d4; +//: my $bw = 1*(8 +3); +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "reg [${bw}-1:0] latch_result${m}_d3; \n"; +//: print "reg [${bw}+3:0] flush_out${m}; \n"; +//: print "wire [${bw}-1:0] data_buf${m}; \n"; +//: print "wire [${bw}-1:0] latch_result${m}; \n"; +//: print "wire [${bw}-1:0] latch_result${m}_d4; \n"; +//: } +reg [4:0] pooling_cnt; +reg [1*(8 +3)+3:0] pooling_out; +reg [2:0] pooling_size; +////////////////////////////////////////////////////////////////////////////////// +//======================================================= +//1D pooling unit +//------------------------------------------------------- +//assign fp_mean_pool_cfg = (reg2dp_fp16_en & average_pooling_en); +// interface +assign pdp_din_wpos = pdma2pdp_pd[1*(8 +3)+3:1*(8 +3)]; +assign pdp_din_cpos = {2'd0,pdma2pdp_pd[1*(8 +3)+6:1*(8 +3)+4]}; +assign buf_sel = pdp_din_cpos; +assign load_din = pdma2pdp_pvld & pdma2pdp_prdy_f & (~cur_datin_disable) & pooling_unit_en; +assign pdma2pdp_prdy_f = pipe_in_rdy; +assign pdma2pdp_prdy = pdma2pdp_prdy_f; +//========================================================= +//POOLING FUNCTION DEFINITION +// +//---- ----------------------------------------------------- +//: my $k = 8 +3; +//: print qq( +//: function [${k}-1:0] pooling_MIN; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); + reg min_int_ff; + begin + min_int_ff = ($signed(data1)> $signed(data0)) ; + pooling_MIN = (min_int_ff ) ? data0 : data1; + end + endfunction +//: my $k = 8 +3; +//: print qq( +//: function [${k}-1:0] pooling_MAX; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); + reg max_int_ff; + begin + max_int_ff = ($signed(data0)> $signed(data1)) ; + pooling_MAX = (max_int_ff ) ? data0 : data1; + end + endfunction +//: my $k = 8 +3; +//: print qq( +//: function [${k}-1:0] pooling_SUM; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); + begin +//spyglass disable_block W484 + pooling_SUM = $signed(data1) + $signed(data0); +//spyglass enable_block W484 + end + endfunction +//pooling result +//: my $k = 1*(8 +3); +//: print qq( +//: function [${k}-1:0] pooling_fun; +//: input[${k}-1:0] data0; +//: input[${k}-1:0] data1; +//: ); + input[1:0] pooling_type; + reg min_pooling; + reg max_pooling; + reg mean_pooling; + begin + min_pooling = (pooling_type== 2'h2 ); + max_pooling = (pooling_type== 2'h1 ); + mean_pooling = (pooling_type== 2'h0 ); +//: my $K = 1; +//: my $P = (8 +3); +//: foreach my $m (0..$K-1) { +//: print qq( +//: pooling_fun[${P}*${m}+${P}-1:${P}*${m}] = mean_pooling? pooling_SUM(data0[${P}*${m}+${P}-1:${P}*${m}],data1[${P}*${m}+${P}-1:${P}*${m}]) : +//: min_pooling ? (pooling_MIN(data0[${P}*${m}+${P}-1:${P}*${m}],data1[${P}*${m}+${P}-1:${P}*${m}])) : +//: max_pooling ? (pooling_MAX(data0[${P}*${m}+${P}-1:${P}*${m}],data1[${P}*${m}+${P}-1:${P}*${m}])) : 0; +//: ); +//: } + end +endfunction +//========================================================= +// pooling real size +// +//--------------------------------------------------------- +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_size[2:0] <= {3{1'b0}}; + end else begin + if(load_din & pdp_din_lc_f) begin + if(pooling_din_last) + pooling_size[2:0] <= 3'd0; + else + pooling_size[2:0] <= pooling_size + 1; + end + end +end +assign pooling_out_size = pooling_size; +////==================================================================== +//// pooling data +//// +////-------------------------------------------------------------------- +assign datain_ext = pdma2pdp_pd[1*(8 +3)-1:0]; +always @(*) begin + case(buf_sel) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: cur_pooling_dat = data_buf${m}; \n"; +//: } +//VCS coverage off + default: cur_pooling_dat = 0; +//VCS coverage on + endcase +end +//-------------------------------------------------------------------- +//pooling function for fp16 average mode +//assign fp_datain_ext = datain_ext[87:0] ; +//assign fp_cur_pooling_dat = cur_pooling_dat[87:0]; +// +//assign fp_addin_vld = pdma2pdp_pvld & pipe_in_rdy & fp_mean_pool_cfg; +//cal1d_fp16_pool_sum u_cal1d_fp16_pool_sum ( +// .inp_a_0 (fp_cur_pooling_dat[16:0]) //|< w +// ,.inp_a_1 (fp_cur_pooling_dat[38:22]) //|< w +// ,.inp_a_2 (fp_cur_pooling_dat[60:44]) //|< w +// ,.inp_a_3 (fp_cur_pooling_dat[82:66]) //|< w +// ,.inp_b_0 (fp_datain_ext[16:0]) //|< w +// ,.inp_b_1 (fp_datain_ext[38:22]) //|< w +// ,.inp_b_2 (fp_datain_ext[60:44]) //|< w +// ,.inp_b_3 (fp_datain_ext[82:66]) //|< w +// ,.inp_in_pvld (fp_addin_vld) //|< w +// ,.inp_out_prdy (fp16_pool_sum_prdy) //|< w +// ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +// ,.nvdla_op_gated_clk_fp16 (nvdla_op_gated_clk_fp16) //|< i +// ,.inp_in_prdy (fp_addin_rdy) //|> w +// ,.inp_out_pvld (fp16_pool_sum_pvld) //|> w +// ,.out_z_0 (fp16_pool_sum_0[16:0]) //|> w +// ,.out_z_1 (fp16_pool_sum_1[16:0]) //|> w +// ,.out_z_2 (fp16_pool_sum_2[16:0]) //|> w +// ,.out_z_3 (fp16_pool_sum_3[16:0]) //|> w +// ); +//assign fp_pool_sum = {fp16_pool_sum_3,fp16_pool_sum_2,fp16_pool_sum_1,fp16_pool_sum_0}; +//////////////////// +//below value 4 means NVDLA_HLS_ADD17_LATENCY +//: my $STAGE = 4; +//: my $WID = 1*(8 +3)*2 + 12; +//: print qq( +//: wire [${WID}-1:0] pipe_out_pd; +//: wire [${WID}-1:0] pipe_dp_0; +//: wire pipe_vld_0; +//: wire pipe_rdy_$STAGE; +//: assign pipe_vld_0 = pdma2pdp_pvld; +//: assign pipe_dp_0 = {pooling_din_last,pooling_out_size[2:0],cur_datin_disable,buf_sel[4:0],pdp_din_lc_f,pooling_din_1st,datain_ext,int_pooling}; +//: ); +//: foreach my $m (0..$STAGE-1) { +//: my $n = $m+1; +//: print qq( +//: wire pipe_rdy_$m; +//: reg pipe_vld_$n; +//: reg [$WID-1:0] pipe_dp_$n; +//: ); +//: } +//: foreach my $m (0..$STAGE-1) { +//: my $n = $m+1; +//: print qq( +//: assign pipe_rdy_$m = ~pipe_vld_$n || pipe_rdy_$n; +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: begin +//: if (!nvdla_core_rstn) +//: pipe_vld_$n <= 1'b0; +//: else if(pipe_vld_$m) +//: pipe_vld_$n <= 1'b1; +//: else if(pipe_rdy_$n) +//: pipe_vld_$n <= 1'b0; +//: end +//: always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) +//: begin +//: if (!nvdla_core_rstn) +//: pipe_dp_$n <= ${WID}'d0; +//: else if(pipe_vld_${m} & pipe_rdy_${m}) +//: pipe_dp_$n <= pipe_dp_$m; +//: end +//: ); +//: } +//: print qq( +//: assign pipe_rdy_$STAGE = pipe_out_rdy; +//: assign pipe_out_vld = pipe_vld_$STAGE; +//: assign pipe_out_pd = pipe_dp_$STAGE; +//: ); +assign pipe_in_rdy = pipe_rdy_0; +//////::dla_pipe -stages NVDLA_HLS_ADD17_LATENCY -i pipe_in -o pipe_out -width 185; +assign pipe_out_rdy = add_out_rdy; +//assign fp16_pool_sum_prdy = fp_mean_pool_cfg & add_out_rdy & pipe_out_vld; +assign add_out_vld = pipe_out_vld; +assign add_out_rdy = ~pooling_out_vld | pooling_out_prdy; +//////////////////// +assign int_pooling_sync = pipe_out_pd[1*(8 +3)-1:0]; +assign datain_ext_sync = pipe_out_pd[1*(8 +3)*2-1:1*(8 +3)]; +assign pooling_din_1st_sync = pipe_out_pd[1*(8 +3)*2]; +assign pdp_din_lc_f_sync = pipe_out_pd[1*(8 +3)*2+1]; +assign buf_sel_sync = pipe_out_pd[1*(8 +3)*2+6:1*(8 +3)*2+2]; +assign cur_datin_disable_sync= pipe_out_pd[1*(8 +3)*2+7]; +assign pooling_out_size_sync = pipe_out_pd[1*(8 +3)*2+10:1*(8 +3)*2+8]; +assign pooling_din_last_sync = pipe_out_pd[1*(8 +3)*2+11]; +//////////////////// +////for NVDLA_HLS_ADD17_LATENCY==3 +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// fp_pool_sum_result0_d3 <= {68{1'b0}}; +// fp_pool_sum_result1_d3 <= {68{1'b0}}; +// fp_pool_sum_result2_d3 <= {68{1'b0}}; +// fp_pool_sum_result3_d3 <= {68{1'b0}}; +// end else begin +// if(add_out_vld & add_out_rdy) begin +// if(pooling_din_1st_sync) begin +// case(buf_sel_sync) +// 2'd0: fp_pool_sum_result0_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// 2'd1: fp_pool_sum_result1_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// 2'd2: fp_pool_sum_result2_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// 2'd3: fp_pool_sum_result3_d3 <= {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]}; +// //VCS coverage off +// default: begin +// fp_pool_sum_result0_d3 <= fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d3 <= fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d3 <= fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d3 <= fp_pool_sum_result3_d3; +// end +// //VCS coverage on +// endcase +// end else begin +// case(buf_sel_sync) +// 2'd0: fp_pool_sum_result0_d3 <= fp_pool_sum; +// 2'd1: fp_pool_sum_result1_d3 <= fp_pool_sum; +// 2'd2: fp_pool_sum_result2_d3 <= fp_pool_sum; +// 2'd3: fp_pool_sum_result3_d3 <= fp_pool_sum; +// //VCS coverage off +// default: begin +// fp_pool_sum_result0_d3 <= fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d3 <= fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d3 <= fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d3 <= fp_pool_sum_result3_d3; +// end +// //VCS coverage on +// endcase +// end +// end +// end +//end +// +////for NVDLA_HLS_ADD17_LATENCY==4 +//always @( +// pooling_din_1st_sync +// or buf_sel_sync +// or datain_ext_sync +// or fp_pool_sum_result0_d3 +// or fp_pool_sum_result1_d3 +// or fp_pool_sum_result2_d3 +// or fp_pool_sum_result3_d3 +// or fp_pool_sum +// ) begin +// if(pooling_din_1st_sync) begin +// fp_pool_sum_result0_d4 = (buf_sel_sync==2'd0)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d4 = (buf_sel_sync==2'd1)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d4 = (buf_sel_sync==2'd2)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d4 = (buf_sel_sync==2'd3)? {datain_ext_sync[82:66],datain_ext_sync[60:44],datain_ext_sync[38:22],datain_ext_sync[16:0]} : fp_pool_sum_result3_d3; +// end else begin +// fp_pool_sum_result0_d4 = (buf_sel_sync==2'd0)? fp_pool_sum : fp_pool_sum_result0_d3; +// fp_pool_sum_result1_d4 = (buf_sel_sync==2'd1)? fp_pool_sum : fp_pool_sum_result1_d3; +// fp_pool_sum_result2_d4 = (buf_sel_sync==2'd2)? fp_pool_sum : fp_pool_sum_result2_d3; +// fp_pool_sum_result3_d4 = (buf_sel_sync==2'd3)? fp_pool_sum : fp_pool_sum_result3_d3; +// end +//end +// +//assign fp_pool_sum_result0 = fp_pool_sum_result0_d4; +//assign fp_pool_sum_result1 = fp_pool_sum_result1_d4; +//assign fp_pool_sum_result2 = fp_pool_sum_result2_d4; +//assign fp_pool_sum_result3 = fp_pool_sum_result3_d4; +// +//assign fp_pool_sum_use0 = {5'd0,fp_pool_sum_result0[67:51],5'd0,fp_pool_sum_result0[50:34],5'd0,fp_pool_sum_result0[33:17],5'd0,fp_pool_sum_result0[16:0]}; +//assign fp_pool_sum_use1 = {5'd0,fp_pool_sum_result1[67:51],5'd0,fp_pool_sum_result1[50:34],5'd0,fp_pool_sum_result1[33:17],5'd0,fp_pool_sum_result1[16:0]}; +//assign fp_pool_sum_use2 = {5'd0,fp_pool_sum_result2[67:51],5'd0,fp_pool_sum_result2[50:34],5'd0,fp_pool_sum_result2[33:17],5'd0,fp_pool_sum_result2[16:0]}; +//assign fp_pool_sum_use3 = {5'd0,fp_pool_sum_result3[67:51],5'd0,fp_pool_sum_result3[50:34],5'd0,fp_pool_sum_result3[33:17],5'd0,fp_pool_sum_result3[16:0]}; +////////////////////////// +assign pool_fun_vld = load_din; +assign int_pool_datin_ext = pool_fun_vld ? datain_ext : 0; +assign int_pool_cur_dat = pool_fun_vld ? cur_pooling_dat : 0; +assign int_pooling = pooling_fun(int_pool_cur_dat, int_pool_datin_ext,pooling_type_cfg[1:0]); +assign pooling_result = (pooling_din_1st_sync ? datain_ext_sync : int_pooling_sync); +//-------------------------------------------------------------------- +//for NVDLA_HLS_ADD17_LATENCY==3 +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "latch_result${m}_d3 <= 0; \n"; +//: } + end else begin + if(add_out_vld & add_out_rdy) begin + case(buf_sel_sync) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: latch_result${m}_d3 <= pooling_result; \n"; +//: } +//VCS coverage off + default: begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "latch_result${m}_d3 <= latch_result${m}_d3; \n"; +//: } + end +//VCS coverage on + endcase + end + end +end +//for NVDLA_HLS_ADD17_LATENCY==4 +assign pooling_out_size_sync_use_d4 = pooling_out_size_sync; +assign pooling_din_last_sync_use_d4 = pooling_din_last_sync; +assign buf_sel_sync_use_d4 = buf_sel_sync; +assign cur_datin_disable_sync_use_d4 = cur_datin_disable_sync; +assign data_buf_lc_d4 = pdp_din_lc_f_sync; +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "assign latch_result${m}_d4 = (buf_sel_sync==5'd$m)? pooling_result : latch_result${m}_d3; \n"; +//: print "assign latch_result$m = latch_result${m}_d4; \n"; +//: print "assign data_buf$m = latch_result$m ; \n"; +//: } +//========== +//info select +assign pooling_out_size_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ pooling_out_size_sync_use_d4 /* : pooling_out_size_sync_use_d3 */; +assign pooling_din_last_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ pooling_din_last_sync_use_d4 /* : pooling_din_last_sync_use_d3 */; +assign buf_sel_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ buf_sel_sync_use_d4 /* : buf_sel_sync_use_d3 */; +assign cur_datin_disable_sync_use = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ cur_datin_disable_sync_use_d4/* : cur_datin_disable_sync_use_d3*/; +assign data_buf_lc = /*(NVDLA_HLS_ADD17_LATENCY == 4) ?*/ data_buf_lc_d4 /* : data_buf_lc_d3 */; +//============================================================ +//pooling send out +// +//------------------------------------------------------------ +//for NVDLA_HLS_ADD17_LATENCY==3 +//&Always posedge; +// if(add_out_vld) +// pooling_out_vld_d3 <0=1'b1; +// else if(pooling_out_prdy) +// pooling_out_vld_d3 <0= 1'b0; +//&End; +assign pooling_out_vld = /*(NVDLA_HLS_ADD17_LATENCY == 4) ? */add_out_vld/* : pooling_out_vld_d3*/; +assign pooling_out_pvld = pooling_out_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_cnt <= 0; + end else begin + if(pooling_out_vld & pooling_out_prdy & ((pooling_din_last_sync_use & (~cur_datin_disable_sync_use)) | last_out_en))begin +//: my $k = int(8 / 1); +//: print qq( +//: if(pooling_cnt==(5'd${k} -1)) +//: ); + pooling_cnt <= 0; + else + pooling_cnt <= pooling_cnt +1'd1; + end + end + end +always @(*) begin + if(last_out_en) begin + case(pooling_cnt) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: pooling_out = flush_out$m; \n"; +//: } + default: pooling_out = 0; + endcase + end else begin + case(pooling_cnt) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: pooling_out = {data_buf_lc,pooling_out_size_sync_use,data_buf${m}}; \n"; +//: } + default: pooling_out = 0; + endcase + end +end +////////////////////////////////////////////// +//output latch in line end for flush +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "flush_out$m <= 0; \n"; +//: } + end else begin + if(pooling_din_last_sync_use & (~cur_datin_disable_sync_use)) begin + case(buf_sel_sync_use) +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "5'd${m}: flush_out$m <= {data_buf_lc,pooling_out_size_sync_use,data_buf${m}}; \n"; +//: } +//VCS coverage off + default: begin +//: my $k = int(8 / 1); +//: foreach my $m (0..$k-1) { +//: print "flush_out$m <= flush_out${m}; \n"; +//: } + end +//VCS coverage on + endcase + end + end +end +////////////////////////////////////////////// +endmodule // NV_NVDLA_PDP_CORE_unit1d diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v new file mode 100644 index 0000000..4c5125c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v @@ -0,0 +1,393 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_REG_dual.v +module NV_NVDLA_PDP_RDMA_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,cube_in_channel + ,cube_in_height + ,cube_in_width + ,input_data + ,flying_mode + ,split_num + ,op_en_trigger + ,partial_width_in_first + ,partial_width_in_last + ,partial_width_in_mid + ,dma_en + ,kernel_stride_width + ,kernel_width + ,pad_width + ,src_base_addr_high + ,src_base_addr_low + ,src_line_stride + ,src_ram_type + ,src_surface_stride + ,op_en + ,perf_read_stall + ); +wire [31:0] nvdla_pdp_rdma_d_cya_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_cube_in_channel_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_cube_in_height_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_cube_in_width_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_format_0_out; +wire [31:0] nvdla_pdp_rdma_d_flying_mode_0_out; +wire [31:0] nvdla_pdp_rdma_d_op_enable_0_out; +wire [31:0] nvdla_pdp_rdma_d_operation_mode_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_partial_width_in_0_out; +wire [31:0] nvdla_pdp_rdma_d_perf_enable_0_out; +wire [31:0] nvdla_pdp_rdma_d_perf_read_stall_0_out; +wire [31:0] nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_pooling_padding_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_base_addr_high_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_base_addr_low_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_line_stride_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_ram_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_surface_stride_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [12:0] cube_in_channel; +output [12:0] cube_in_height; +output [12:0] cube_in_width; +output [1:0] input_data; +output flying_mode; +output [7:0] split_num; +output op_en_trigger; +output [9:0] partial_width_in_first; +output [9:0] partial_width_in_last; +output [9:0] partial_width_in_mid; +output dma_en; +output [3:0] kernel_stride_width; +output [3:0] kernel_width; +output [3:0] pad_width; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output [31:0] src_line_stride; +output src_ram_type; +output [31:0] src_surface_stride; +// Read-only register inputs +input op_en; +input [31:0] perf_read_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [12:0] cube_in_channel; +reg [12:0] cube_in_height; +reg [12:0] cube_in_width; +reg [31:0] cya; +reg dma_en; +reg flying_mode; +reg [1:0] input_data; +reg [3:0] kernel_stride_width; +reg [3:0] kernel_width; +reg [3:0] pad_width; +reg [9:0] partial_width_in_first; +reg [9:0] partial_width_in_last; +reg [9:0] partial_width_in_mid; +reg [31:0] reg_rd_data; +reg [7:0] split_num; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg src_ram_type; +reg [31:0] src_surface_stride; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_rdma_d_cya_0_wren = (reg_offset_wr == (32'hc04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_cube_in_channel_0_wren = (reg_offset_wr == (32'hc014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_cube_in_height_0_wren = (reg_offset_wr == (32'hc010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_cube_in_width_0_wren = (reg_offset_wr == (32'hc00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_format_0_wren = (reg_offset_wr == (32'hc030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_flying_mode_0_wren = (reg_offset_wr == (32'hc018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_operation_mode_cfg_0_wren = (reg_offset_wr == (32'hc034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_op_enable_0_wren = (reg_offset_wr == (32'hc008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_partial_width_in_0_wren = (reg_offset_wr == (32'hc040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_perf_enable_0_wren = (reg_offset_wr == (32'hc044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_perf_read_stall_0_wren = (reg_offset_wr == (32'hc048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_pooling_kernel_cfg_0_wren = (reg_offset_wr == (32'hc038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_pooling_padding_cfg_0_wren = (reg_offset_wr == (32'hc03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'hc020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'hc01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_line_stride_0_wren = (reg_offset_wr == (32'hc024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_ram_cfg_0_wren = (reg_offset_wr == (32'hc02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_surface_stride_0_wren = (reg_offset_wr == (32'hc028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_rdma_d_cya_0_out[31:0] = { cya }; +assign nvdla_pdp_rdma_d_data_cube_in_channel_0_out[31:0] = { 19'b0, cube_in_channel }; +assign nvdla_pdp_rdma_d_data_cube_in_height_0_out[31:0] = { 19'b0, cube_in_height }; +assign nvdla_pdp_rdma_d_data_cube_in_width_0_out[31:0] = { 19'b0, cube_in_width }; +assign nvdla_pdp_rdma_d_data_format_0_out[31:0] = { 30'b0, input_data }; +assign nvdla_pdp_rdma_d_flying_mode_0_out[31:0] = { 31'b0, flying_mode }; +assign nvdla_pdp_rdma_d_operation_mode_cfg_0_out[31:0] = { 24'b0, split_num }; +assign nvdla_pdp_rdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_pdp_rdma_d_partial_width_in_0_out[31:0] = { 2'b0, partial_width_in_mid, partial_width_in_last, partial_width_in_first }; +assign nvdla_pdp_rdma_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_pdp_rdma_d_perf_read_stall_0_out[31:0] = { perf_read_stall }; +assign nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out[31:0] = { 24'b0, kernel_stride_width, kernel_width }; +assign nvdla_pdp_rdma_d_pooling_padding_cfg_0_out[31:0] = { 28'b0, pad_width }; +assign nvdla_pdp_rdma_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_pdp_rdma_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low }; +assign nvdla_pdp_rdma_d_src_line_stride_0_out[31:0] = { src_line_stride }; +assign nvdla_pdp_rdma_d_src_ram_cfg_0_out[31:0] = { 31'b0, src_ram_type }; +assign nvdla_pdp_rdma_d_src_surface_stride_0_out[31:0] = { src_surface_stride }; +assign op_en_trigger = nvdla_pdp_rdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_rdma_d_cya_0_out + or nvdla_pdp_rdma_d_data_cube_in_channel_0_out + or nvdla_pdp_rdma_d_data_cube_in_height_0_out + or nvdla_pdp_rdma_d_data_cube_in_width_0_out + or nvdla_pdp_rdma_d_data_format_0_out + or nvdla_pdp_rdma_d_flying_mode_0_out + or nvdla_pdp_rdma_d_operation_mode_cfg_0_out + or nvdla_pdp_rdma_d_op_enable_0_out + or nvdla_pdp_rdma_d_partial_width_in_0_out + or nvdla_pdp_rdma_d_perf_enable_0_out + or nvdla_pdp_rdma_d_perf_read_stall_0_out + or nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out + or nvdla_pdp_rdma_d_pooling_padding_cfg_0_out + or nvdla_pdp_rdma_d_src_base_addr_high_0_out + or nvdla_pdp_rdma_d_src_base_addr_low_0_out + or nvdla_pdp_rdma_d_src_line_stride_0_out + or nvdla_pdp_rdma_d_src_ram_cfg_0_out + or nvdla_pdp_rdma_d_src_surface_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'hc04c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_cya_0_out ; + end + (32'hc014 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_cube_in_channel_0_out ; + end + (32'hc010 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_cube_in_height_0_out ; + end + (32'hc00c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_cube_in_width_0_out ; + end + (32'hc030 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_format_0_out ; + end + (32'hc018 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_flying_mode_0_out ; + end + (32'hc034 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_operation_mode_cfg_0_out ; + end + (32'hc008 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_op_enable_0_out ; + end + (32'hc040 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_partial_width_in_0_out ; + end + (32'hc044 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_perf_enable_0_out ; + end + (32'hc048 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_perf_read_stall_0_out ; + end + (32'hc038 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out ; + end + (32'hc03c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_pooling_padding_cfg_0_out ; + end + (32'hc020 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_base_addr_high_0_out ; + end + (32'hc01c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_base_addr_low_0_out ; + end + (32'hc024 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_line_stride_0_out ; + end + (32'hc02c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_ram_cfg_0_out ; + end + (32'hc028 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_surface_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + cube_in_channel[12:0] <= 13'b0000000000000; + cube_in_height[12:0] <= 13'b0000000000000; + cube_in_width[12:0] <= 13'b0000000000000; + input_data[1:0] <= 2'b00; + flying_mode <= 1'b0; + split_num[7:0] <= 8'b00000000; + partial_width_in_first[9:0] <= 10'b0000000000; + partial_width_in_last[9:0] <= 10'b0000000000; + partial_width_in_mid[9:0] <= 10'b0000000000; + dma_en <= 1'b0; + kernel_stride_width[3:0] <= 4'b0000; + kernel_width[3:0] <= 4'b0000; + pad_width[3:0] <= 4'b0000; + src_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + src_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + src_line_stride[31:0] <= 32'b00000000000000000000000000000000; + src_ram_type <= 1'b0; + src_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + end else begin +// Register: NVDLA_PDP_RDMA_D_CYA_0 Field: cya + if (nvdla_pdp_rdma_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 Field: cube_in_channel + if (nvdla_pdp_rdma_d_data_cube_in_channel_0_wren) begin + cube_in_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 Field: cube_in_height + if (nvdla_pdp_rdma_d_data_cube_in_height_0_wren) begin + cube_in_height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 Field: cube_in_width + if (nvdla_pdp_rdma_d_data_cube_in_width_0_wren) begin + cube_in_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_FORMAT_0 Field: input_data + if (nvdla_pdp_rdma_d_data_format_0_wren) begin + input_data[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_PDP_RDMA_D_FLYING_MODE_0 Field: flying_mode + if (nvdla_pdp_rdma_d_flying_mode_0_wren) begin + flying_mode <= reg_wr_data[0]; + end +// Register: NVDLA_PDP_RDMA_D_OPERATION_MODE_CFG_0 Field: split_num + if (nvdla_pdp_rdma_d_operation_mode_cfg_0_wren) begin + split_num[7:0] <= reg_wr_data[7:0]; + end +// Not generating flops for field NVDLA_PDP_RDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_first + if (nvdla_pdp_rdma_d_partial_width_in_0_wren) begin + partial_width_in_first[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_last + if (nvdla_pdp_rdma_d_partial_width_in_0_wren) begin + partial_width_in_last[9:0] <= reg_wr_data[19:10]; + end +// Register: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_mid + if (nvdla_pdp_rdma_d_partial_width_in_0_wren) begin + partial_width_in_mid[9:0] <= reg_wr_data[29:20]; + end +// Register: NVDLA_PDP_RDMA_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_pdp_rdma_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_RDMA_D_PERF_READ_STALL_0::perf_read_stall +// Register: NVDLA_PDP_RDMA_D_POOLING_KERNEL_CFG_0 Field: kernel_stride_width + if (nvdla_pdp_rdma_d_pooling_kernel_cfg_0_wren) begin + kernel_stride_width[3:0] <= reg_wr_data[7:4]; + end +// Register: NVDLA_PDP_RDMA_D_POOLING_KERNEL_CFG_0 Field: kernel_width + if (nvdla_pdp_rdma_d_pooling_kernel_cfg_0_wren) begin + kernel_width[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_PDP_RDMA_D_POOLING_PADDING_CFG_0 Field: pad_width + if (nvdla_pdp_rdma_d_pooling_padding_cfg_0_wren) begin + pad_width[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_pdp_rdma_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_pdp_rdma_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_pdp_rdma_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_RAM_CFG_0 Field: src_ram_type + if (nvdla_pdp_rdma_d_src_ram_cfg_0_wren) begin + src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_pdp_rdma_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hc04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_cya_0_out, nvdla_pdp_rdma_d_cya_0_out); + (32'hc014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_cube_in_channel_0_out, nvdla_pdp_rdma_d_data_cube_in_channel_0_out); + (32'hc010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_cube_in_height_0_out, nvdla_pdp_rdma_d_data_cube_in_height_0_out); + (32'hc00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_cube_in_width_0_out, nvdla_pdp_rdma_d_data_cube_in_width_0_out); + (32'hc030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_format_0_out, nvdla_pdp_rdma_d_data_format_0_out); + (32'hc018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_FLYING_MODE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_flying_mode_0_out, nvdla_pdp_rdma_d_flying_mode_0_out); + (32'hc034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_OPERATION_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_operation_mode_cfg_0_out, nvdla_pdp_rdma_d_operation_mode_cfg_0_out); + (32'hc008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_op_enable_0_out, nvdla_pdp_rdma_d_op_enable_0_out); + (32'hc040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_partial_width_in_0_out, nvdla_pdp_rdma_d_partial_width_in_0_out); + (32'hc044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_perf_enable_0_out, nvdla_pdp_rdma_d_perf_enable_0_out); + (32'hc048 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_RDMA_D_PERF_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hc038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_POOLING_KERNEL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out, nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out); + (32'hc03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_POOLING_PADDING_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_pooling_padding_cfg_0_out, nvdla_pdp_rdma_d_pooling_padding_cfg_0_out); + (32'hc020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_base_addr_high_0_out, nvdla_pdp_rdma_d_src_base_addr_high_0_out); + (32'hc01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_base_addr_low_0_out, nvdla_pdp_rdma_d_src_base_addr_low_0_out); + (32'hc024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_line_stride_0_out, nvdla_pdp_rdma_d_src_line_stride_0_out); + (32'hc02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_RAM_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_ram_cfg_0_out, nvdla_pdp_rdma_d_src_ram_cfg_0_out); + (32'hc028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_surface_stride_0_out, nvdla_pdp_rdma_d_src_surface_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_RDMA_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v.vcp new file mode 100644 index 0000000..4c5125c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v.vcp @@ -0,0 +1,393 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_REG_dual.v +module NV_NVDLA_PDP_RDMA_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,cube_in_channel + ,cube_in_height + ,cube_in_width + ,input_data + ,flying_mode + ,split_num + ,op_en_trigger + ,partial_width_in_first + ,partial_width_in_last + ,partial_width_in_mid + ,dma_en + ,kernel_stride_width + ,kernel_width + ,pad_width + ,src_base_addr_high + ,src_base_addr_low + ,src_line_stride + ,src_ram_type + ,src_surface_stride + ,op_en + ,perf_read_stall + ); +wire [31:0] nvdla_pdp_rdma_d_cya_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_cube_in_channel_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_cube_in_height_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_cube_in_width_0_out; +wire [31:0] nvdla_pdp_rdma_d_data_format_0_out; +wire [31:0] nvdla_pdp_rdma_d_flying_mode_0_out; +wire [31:0] nvdla_pdp_rdma_d_op_enable_0_out; +wire [31:0] nvdla_pdp_rdma_d_operation_mode_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_partial_width_in_0_out; +wire [31:0] nvdla_pdp_rdma_d_perf_enable_0_out; +wire [31:0] nvdla_pdp_rdma_d_perf_read_stall_0_out; +wire [31:0] nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_pooling_padding_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_base_addr_high_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_base_addr_low_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_line_stride_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_ram_cfg_0_out; +wire [31:0] nvdla_pdp_rdma_d_src_surface_stride_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [12:0] cube_in_channel; +output [12:0] cube_in_height; +output [12:0] cube_in_width; +output [1:0] input_data; +output flying_mode; +output [7:0] split_num; +output op_en_trigger; +output [9:0] partial_width_in_first; +output [9:0] partial_width_in_last; +output [9:0] partial_width_in_mid; +output dma_en; +output [3:0] kernel_stride_width; +output [3:0] kernel_width; +output [3:0] pad_width; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output [31:0] src_line_stride; +output src_ram_type; +output [31:0] src_surface_stride; +// Read-only register inputs +input op_en; +input [31:0] perf_read_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [12:0] cube_in_channel; +reg [12:0] cube_in_height; +reg [12:0] cube_in_width; +reg [31:0] cya; +reg dma_en; +reg flying_mode; +reg [1:0] input_data; +reg [3:0] kernel_stride_width; +reg [3:0] kernel_width; +reg [3:0] pad_width; +reg [9:0] partial_width_in_first; +reg [9:0] partial_width_in_last; +reg [9:0] partial_width_in_mid; +reg [31:0] reg_rd_data; +reg [7:0] split_num; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg src_ram_type; +reg [31:0] src_surface_stride; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_rdma_d_cya_0_wren = (reg_offset_wr == (32'hc04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_cube_in_channel_0_wren = (reg_offset_wr == (32'hc014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_cube_in_height_0_wren = (reg_offset_wr == (32'hc010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_cube_in_width_0_wren = (reg_offset_wr == (32'hc00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_data_format_0_wren = (reg_offset_wr == (32'hc030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_flying_mode_0_wren = (reg_offset_wr == (32'hc018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_operation_mode_cfg_0_wren = (reg_offset_wr == (32'hc034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_op_enable_0_wren = (reg_offset_wr == (32'hc008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_partial_width_in_0_wren = (reg_offset_wr == (32'hc040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_perf_enable_0_wren = (reg_offset_wr == (32'hc044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_perf_read_stall_0_wren = (reg_offset_wr == (32'hc048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_pooling_kernel_cfg_0_wren = (reg_offset_wr == (32'hc038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_pooling_padding_cfg_0_wren = (reg_offset_wr == (32'hc03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'hc020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'hc01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_line_stride_0_wren = (reg_offset_wr == (32'hc024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_ram_cfg_0_wren = (reg_offset_wr == (32'hc02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_d_src_surface_stride_0_wren = (reg_offset_wr == (32'hc028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_rdma_d_cya_0_out[31:0] = { cya }; +assign nvdla_pdp_rdma_d_data_cube_in_channel_0_out[31:0] = { 19'b0, cube_in_channel }; +assign nvdla_pdp_rdma_d_data_cube_in_height_0_out[31:0] = { 19'b0, cube_in_height }; +assign nvdla_pdp_rdma_d_data_cube_in_width_0_out[31:0] = { 19'b0, cube_in_width }; +assign nvdla_pdp_rdma_d_data_format_0_out[31:0] = { 30'b0, input_data }; +assign nvdla_pdp_rdma_d_flying_mode_0_out[31:0] = { 31'b0, flying_mode }; +assign nvdla_pdp_rdma_d_operation_mode_cfg_0_out[31:0] = { 24'b0, split_num }; +assign nvdla_pdp_rdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_pdp_rdma_d_partial_width_in_0_out[31:0] = { 2'b0, partial_width_in_mid, partial_width_in_last, partial_width_in_first }; +assign nvdla_pdp_rdma_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_pdp_rdma_d_perf_read_stall_0_out[31:0] = { perf_read_stall }; +assign nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out[31:0] = { 24'b0, kernel_stride_width, kernel_width }; +assign nvdla_pdp_rdma_d_pooling_padding_cfg_0_out[31:0] = { 28'b0, pad_width }; +assign nvdla_pdp_rdma_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_pdp_rdma_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low }; +assign nvdla_pdp_rdma_d_src_line_stride_0_out[31:0] = { src_line_stride }; +assign nvdla_pdp_rdma_d_src_ram_cfg_0_out[31:0] = { 31'b0, src_ram_type }; +assign nvdla_pdp_rdma_d_src_surface_stride_0_out[31:0] = { src_surface_stride }; +assign op_en_trigger = nvdla_pdp_rdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_rdma_d_cya_0_out + or nvdla_pdp_rdma_d_data_cube_in_channel_0_out + or nvdla_pdp_rdma_d_data_cube_in_height_0_out + or nvdla_pdp_rdma_d_data_cube_in_width_0_out + or nvdla_pdp_rdma_d_data_format_0_out + or nvdla_pdp_rdma_d_flying_mode_0_out + or nvdla_pdp_rdma_d_operation_mode_cfg_0_out + or nvdla_pdp_rdma_d_op_enable_0_out + or nvdla_pdp_rdma_d_partial_width_in_0_out + or nvdla_pdp_rdma_d_perf_enable_0_out + or nvdla_pdp_rdma_d_perf_read_stall_0_out + or nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out + or nvdla_pdp_rdma_d_pooling_padding_cfg_0_out + or nvdla_pdp_rdma_d_src_base_addr_high_0_out + or nvdla_pdp_rdma_d_src_base_addr_low_0_out + or nvdla_pdp_rdma_d_src_line_stride_0_out + or nvdla_pdp_rdma_d_src_ram_cfg_0_out + or nvdla_pdp_rdma_d_src_surface_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'hc04c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_cya_0_out ; + end + (32'hc014 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_cube_in_channel_0_out ; + end + (32'hc010 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_cube_in_height_0_out ; + end + (32'hc00c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_cube_in_width_0_out ; + end + (32'hc030 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_data_format_0_out ; + end + (32'hc018 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_flying_mode_0_out ; + end + (32'hc034 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_operation_mode_cfg_0_out ; + end + (32'hc008 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_op_enable_0_out ; + end + (32'hc040 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_partial_width_in_0_out ; + end + (32'hc044 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_perf_enable_0_out ; + end + (32'hc048 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_perf_read_stall_0_out ; + end + (32'hc038 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out ; + end + (32'hc03c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_pooling_padding_cfg_0_out ; + end + (32'hc020 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_base_addr_high_0_out ; + end + (32'hc01c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_base_addr_low_0_out ; + end + (32'hc024 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_line_stride_0_out ; + end + (32'hc02c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_ram_cfg_0_out ; + end + (32'hc028 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_d_src_surface_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + cube_in_channel[12:0] <= 13'b0000000000000; + cube_in_height[12:0] <= 13'b0000000000000; + cube_in_width[12:0] <= 13'b0000000000000; + input_data[1:0] <= 2'b00; + flying_mode <= 1'b0; + split_num[7:0] <= 8'b00000000; + partial_width_in_first[9:0] <= 10'b0000000000; + partial_width_in_last[9:0] <= 10'b0000000000; + partial_width_in_mid[9:0] <= 10'b0000000000; + dma_en <= 1'b0; + kernel_stride_width[3:0] <= 4'b0000; + kernel_width[3:0] <= 4'b0000; + pad_width[3:0] <= 4'b0000; + src_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + src_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + src_line_stride[31:0] <= 32'b00000000000000000000000000000000; + src_ram_type <= 1'b0; + src_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + end else begin +// Register: NVDLA_PDP_RDMA_D_CYA_0 Field: cya + if (nvdla_pdp_rdma_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 Field: cube_in_channel + if (nvdla_pdp_rdma_d_data_cube_in_channel_0_wren) begin + cube_in_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 Field: cube_in_height + if (nvdla_pdp_rdma_d_data_cube_in_height_0_wren) begin + cube_in_height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 Field: cube_in_width + if (nvdla_pdp_rdma_d_data_cube_in_width_0_wren) begin + cube_in_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_RDMA_D_DATA_FORMAT_0 Field: input_data + if (nvdla_pdp_rdma_d_data_format_0_wren) begin + input_data[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_PDP_RDMA_D_FLYING_MODE_0 Field: flying_mode + if (nvdla_pdp_rdma_d_flying_mode_0_wren) begin + flying_mode <= reg_wr_data[0]; + end +// Register: NVDLA_PDP_RDMA_D_OPERATION_MODE_CFG_0 Field: split_num + if (nvdla_pdp_rdma_d_operation_mode_cfg_0_wren) begin + split_num[7:0] <= reg_wr_data[7:0]; + end +// Not generating flops for field NVDLA_PDP_RDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_first + if (nvdla_pdp_rdma_d_partial_width_in_0_wren) begin + partial_width_in_first[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_last + if (nvdla_pdp_rdma_d_partial_width_in_0_wren) begin + partial_width_in_last[9:0] <= reg_wr_data[19:10]; + end +// Register: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_mid + if (nvdla_pdp_rdma_d_partial_width_in_0_wren) begin + partial_width_in_mid[9:0] <= reg_wr_data[29:20]; + end +// Register: NVDLA_PDP_RDMA_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_pdp_rdma_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_RDMA_D_PERF_READ_STALL_0::perf_read_stall +// Register: NVDLA_PDP_RDMA_D_POOLING_KERNEL_CFG_0 Field: kernel_stride_width + if (nvdla_pdp_rdma_d_pooling_kernel_cfg_0_wren) begin + kernel_stride_width[3:0] <= reg_wr_data[7:4]; + end +// Register: NVDLA_PDP_RDMA_D_POOLING_KERNEL_CFG_0 Field: kernel_width + if (nvdla_pdp_rdma_d_pooling_kernel_cfg_0_wren) begin + kernel_width[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_PDP_RDMA_D_POOLING_PADDING_CFG_0 Field: pad_width + if (nvdla_pdp_rdma_d_pooling_padding_cfg_0_wren) begin + pad_width[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_pdp_rdma_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_pdp_rdma_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_pdp_rdma_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_RAM_CFG_0 Field: src_ram_type + if (nvdla_pdp_rdma_d_src_ram_cfg_0_wren) begin + src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_PDP_RDMA_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_pdp_rdma_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hc04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_cya_0_out, nvdla_pdp_rdma_d_cya_0_out); + (32'hc014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_cube_in_channel_0_out, nvdla_pdp_rdma_d_data_cube_in_channel_0_out); + (32'hc010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_cube_in_height_0_out, nvdla_pdp_rdma_d_data_cube_in_height_0_out); + (32'hc00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_cube_in_width_0_out, nvdla_pdp_rdma_d_data_cube_in_width_0_out); + (32'hc030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_data_format_0_out, nvdla_pdp_rdma_d_data_format_0_out); + (32'hc018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_FLYING_MODE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_flying_mode_0_out, nvdla_pdp_rdma_d_flying_mode_0_out); + (32'hc034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_OPERATION_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_operation_mode_cfg_0_out, nvdla_pdp_rdma_d_operation_mode_cfg_0_out); + (32'hc008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_op_enable_0_out, nvdla_pdp_rdma_d_op_enable_0_out); + (32'hc040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_PARTIAL_WIDTH_IN_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_partial_width_in_0_out, nvdla_pdp_rdma_d_partial_width_in_0_out); + (32'hc044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_perf_enable_0_out, nvdla_pdp_rdma_d_perf_enable_0_out); + (32'hc048 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_RDMA_D_PERF_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hc038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_POOLING_KERNEL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out, nvdla_pdp_rdma_d_pooling_kernel_cfg_0_out); + (32'hc03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_POOLING_PADDING_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_pooling_padding_cfg_0_out, nvdla_pdp_rdma_d_pooling_padding_cfg_0_out); + (32'hc020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_base_addr_high_0_out, nvdla_pdp_rdma_d_src_base_addr_high_0_out); + (32'hc01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_base_addr_low_0_out, nvdla_pdp_rdma_d_src_base_addr_low_0_out); + (32'hc024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_line_stride_0_out, nvdla_pdp_rdma_d_src_line_stride_0_out); + (32'hc02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_RAM_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_ram_cfg_0_out, nvdla_pdp_rdma_d_src_ram_cfg_0_out); + (32'hc028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_d_src_surface_stride_0_out, nvdla_pdp_rdma_d_src_surface_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_RDMA_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v new file mode 100644 index 0000000..6006723 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_REG_single.v +module NV_NVDLA_PDP_RDMA_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_pdp_rdma_s_pointer_0_out; +wire [31:0] nvdla_pdp_rdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_rdma_s_pointer_0_wren = (reg_offset_wr == (32'hc004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_s_status_0_wren = (reg_offset_wr == (32'hc000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_rdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_pdp_rdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_rdma_s_pointer_0_out + or nvdla_pdp_rdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hc004 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_s_pointer_0_out ; + end + (32'hc000 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_PDP_RDMA_S_POINTER_0::consumer +// Register: NVDLA_PDP_RDMA_S_POINTER_0 Field: producer + if (nvdla_pdp_rdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_RDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_PDP_RDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hc004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_s_pointer_0_out, nvdla_pdp_rdma_s_pointer_0_out); + (32'hc000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_RDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_RDMA_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v.vcp new file mode 100644 index 0000000..6006723 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_REG_single.v +module NV_NVDLA_PDP_RDMA_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_pdp_rdma_s_pointer_0_out; +wire [31:0] nvdla_pdp_rdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_rdma_s_pointer_0_wren = (reg_offset_wr == (32'hc004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_rdma_s_status_0_wren = (reg_offset_wr == (32'hc000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_rdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_pdp_rdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_rdma_s_pointer_0_out + or nvdla_pdp_rdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hc004 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_s_pointer_0_out ; + end + (32'hc000 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_rdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_PDP_RDMA_S_POINTER_0::consumer +// Register: NVDLA_PDP_RDMA_S_POINTER_0 Field: producer + if (nvdla_pdp_rdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_RDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_PDP_RDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hc004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_RDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_rdma_s_pointer_0_out, nvdla_pdp_rdma_s_pointer_0_out); + (32'hc000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_RDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_RDMA_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v new file mode 100644 index 0000000..99c7ead --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v @@ -0,0 +1,594 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [17:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [17:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [4:0] ig2cq_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_16 = ( wr_count_next_no_wr_popping == 5'd16 ); +wire wr_count_next_is_16 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_16; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_16 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 5'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [3:0] ig2cq_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 4'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= ig2cq_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [3:0] cq2eg_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [17:0] cq2eg_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ig2cq_pd ) + , .we ( ram_we ) + , .wa ( ig2cq_adr ) + , .ra ( cq2eg_adr ) + , .dout ( cq2eg_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [3:0] rd_adr_next_popping = cq2eg_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 4'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [4:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 5'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [17:0] cq2eg_pd; // output data register +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + cq2eg_pd <= cq2eg_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + cq2eg_pd <= {18{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd16 : wr_limit_reg} ) + , .curr ( {27'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_RDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_RDMA_cq +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [17:0] di; +input we; +input [3:0] wa; +input [3:0] ra; +output [17:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [3:0] Wa0_vmw; +reg we0_vmw; +reg [17:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [17:0] ram_ff0; +reg [17:0] ram_ff1; +reg [17:0] ram_ff2; +reg [17:0] ram_ff3; +reg [17:0] ram_ff4; +reg [17:0] ram_ff5; +reg [17:0] ram_ff6; +reg [17:0] ram_ff7; +reg [17:0] ram_ff8; +reg [17:0] ram_ff9; +reg [17:0] ram_ff10; +reg [17:0] ram_ff11; +reg [17:0] ram_ff12; +reg [17:0] ram_ff13; +reg [17:0] ram_ff14; +reg [17:0] ram_ff15; +always @( posedge clk ) begin + if ( we && wa == 4'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 4'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 4'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 4'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 4'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 4'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 4'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 4'd7 ) begin + ram_ff7 <= di; + end + if ( we && wa == 4'd8 ) begin + ram_ff8 <= di; + end + if ( we && wa == 4'd9 ) begin + ram_ff9 <= di; + end + if ( we && wa == 4'd10 ) begin + ram_ff10 <= di; + end + if ( we && wa == 4'd11 ) begin + ram_ff11 <= di; + end + if ( we && wa == 4'd12 ) begin + ram_ff12 <= di; + end + if ( we && wa == 4'd13 ) begin + ram_ff13 <= di; + end + if ( we && wa == 4'd14 ) begin + ram_ff14 <= di; + end + if ( we && wa == 4'd15 ) begin + ram_ff15 <= di; + end +end +reg [17:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = ram_ff8; + 4'd9: dout = ram_ff9; + 4'd10: dout = ram_ff10; + 4'd11: dout = ram_ff11; + 4'd12: dout = ram_ff12; + 4'd13: dout = ram_ff13; + 4'd14: dout = ram_ff14; + 4'd15: dout = ram_ff15; +//VCS coverage off + default: dout = {18{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [3:0] Wa0; +input we0; +input [17:0] Di0; +input [3:0] Ra0; +output [17:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 18'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [17:0] mem[15:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [17:0] Q0 = mem[0]; +wire [17:0] Q1 = mem[1]; +wire [17:0] Q2 = mem[2]; +wire [17:0] Q3 = mem[3]; +wire [17:0] Q4 = mem[4]; +wire [17:0] Q5 = mem[5]; +wire [17:0] Q6 = mem[6]; +wire [17:0] Q7 = mem[7]; +wire [17:0] Q8 = mem[8]; +wire [17:0] Q9 = mem[9]; +wire [17:0] Q10 = mem[10]; +wire [17:0] Q11 = mem[11]; +wire [17:0] Q12 = mem[12]; +wire [17:0] Q13 = mem[13]; +wire [17:0] Q14 = mem[14]; +wire [17:0] Q15 = mem[15]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18] } +endmodule // vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +//vmw: Memory vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +//vmw: Address-size 4 +//vmw: Data-size 18 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[17:0] data0[17:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[17:0] data1[17:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v.vcp new file mode 100644 index 0000000..99c7ead --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v.vcp @@ -0,0 +1,594 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [17:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [17:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [4:0] ig2cq_count; // write-side count +wire [4:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [4:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [4:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_16 = ( wr_count_next_no_wr_popping == 5'd16 ); +wire wr_count_next_is_16 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_16; +wire [4:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [4:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_16 || // busy next cycle? + (wr_limit_reg != 5'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 5'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {5{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [3:0] ig2cq_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 4'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= ig2cq_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [3:0] cq2eg_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire [17:0] cq2eg_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ig2cq_pd ) + , .we ( ram_we ) + , .wa ( ig2cq_adr ) + , .ra ( cq2eg_adr ) + , .dout ( cq2eg_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [3:0] rd_adr_next_popping = cq2eg_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 4'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {4{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [4:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [4:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [4:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [4:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 5'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {5{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg [17:0] cq2eg_pd; // output data register +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + cq2eg_pd <= cq2eg_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + cq2eg_pd <= {18{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_cq_wr_limit : 5'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 5'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 5'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 5'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [4:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 5'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_RDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {27'd0, (wr_limit_reg == 5'd0) ? 5'd16 : wr_limit_reg} ) + , .curr ( {27'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_RDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_RDMA_cq +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [17:0] di; +input we; +input [3:0] wa; +input [3:0] ra; +output [17:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [3:0] Wa0_vmw; +reg we0_vmw; +reg [17:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [17:0] ram_ff0; +reg [17:0] ram_ff1; +reg [17:0] ram_ff2; +reg [17:0] ram_ff3; +reg [17:0] ram_ff4; +reg [17:0] ram_ff5; +reg [17:0] ram_ff6; +reg [17:0] ram_ff7; +reg [17:0] ram_ff8; +reg [17:0] ram_ff9; +reg [17:0] ram_ff10; +reg [17:0] ram_ff11; +reg [17:0] ram_ff12; +reg [17:0] ram_ff13; +reg [17:0] ram_ff14; +reg [17:0] ram_ff15; +always @( posedge clk ) begin + if ( we && wa == 4'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 4'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 4'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 4'd3 ) begin + ram_ff3 <= di; + end + if ( we && wa == 4'd4 ) begin + ram_ff4 <= di; + end + if ( we && wa == 4'd5 ) begin + ram_ff5 <= di; + end + if ( we && wa == 4'd6 ) begin + ram_ff6 <= di; + end + if ( we && wa == 4'd7 ) begin + ram_ff7 <= di; + end + if ( we && wa == 4'd8 ) begin + ram_ff8 <= di; + end + if ( we && wa == 4'd9 ) begin + ram_ff9 <= di; + end + if ( we && wa == 4'd10 ) begin + ram_ff10 <= di; + end + if ( we && wa == 4'd11 ) begin + ram_ff11 <= di; + end + if ( we && wa == 4'd12 ) begin + ram_ff12 <= di; + end + if ( we && wa == 4'd13 ) begin + ram_ff13 <= di; + end + if ( we && wa == 4'd14 ) begin + ram_ff14 <= di; + end + if ( we && wa == 4'd15 ) begin + ram_ff15 <= di; + end +end +reg [17:0] dout; +always @(*) begin + case( ra ) + 4'd0: dout = ram_ff0; + 4'd1: dout = ram_ff1; + 4'd2: dout = ram_ff2; + 4'd3: dout = ram_ff3; + 4'd4: dout = ram_ff4; + 4'd5: dout = ram_ff5; + 4'd6: dout = ram_ff6; + 4'd7: dout = ram_ff7; + 4'd8: dout = ram_ff8; + 4'd9: dout = ram_ff9; + 4'd10: dout = ram_ff10; + 4'd11: dout = ram_ff11; + 4'd12: dout = ram_ff12; + 4'd13: dout = ram_ff13; + 4'd14: dout = ram_ff14; + 4'd15: dout = ram_ff15; +//VCS coverage off + default: dout = {18{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [3:0] Wa0; +input we0; +input [17:0] Di0; +input [3:0] Ra0; +output [17:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 18'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [17:0] mem[15:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [17:0] Q0 = mem[0]; +wire [17:0] Q1 = mem[1]; +wire [17:0] Q2 = mem[2]; +wire [17:0] Q3 = mem[3]; +wire [17:0] Q4 = mem[4]; +wire [17:0] Q5 = mem[5]; +wire [17:0] Q6 = mem[6]; +wire [17:0] Q7 = mem[7]; +wire [17:0] Q8 = mem[8]; +wire [17:0] Q9 = mem[9]; +wire [17:0] Q10 = mem[10]; +wire [17:0] Q11 = mem[11]; +wire [17:0] Q12 = mem[12]; +wire [17:0] Q13 = mem[13]; +wire [17:0] Q14 = mem[14]; +wire [17:0] Q15 = mem[15]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18] } +endmodule // vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +//vmw: Memory vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +//vmw: Address-size 4 +//vmw: Data-size 18 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[17:0] data0[17:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[17:0] data1[17:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_16x18 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v new file mode 100644 index 0000000..f4e6d1e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v @@ -0,0 +1,2300 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,mcif2pdp_rd_rsp_pd //|< i + ,mcif2pdp_rd_rsp_valid //|< i + ,pdp_rdma2dp_ready //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_src_ram_type //|< i + ,cq2eg_prdy //|> o + ,dp2reg_done //|> o + ,eg2ig_done //|> o + ,mcif2pdp_rd_rsp_ready //|> o + ,pdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,pdp_rdma2dp_pd //|> o + ,pdp_rdma2dp_valid //|> o + ,rdma2wdma_done //|> o + ); +/////////////////////////////////////////////////////////////////////////////////////////// +input reg2dp_src_ram_type; +output dp2reg_done; +output eg2ig_done; +output rdma2wdma_done; +// +input nvdla_core_clk; +input nvdla_core_rstn; +input mcif2pdp_rd_rsp_valid; +output mcif2pdp_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd; +output pdp2mcif_rd_cdt_lat_fifo_pop; +output pdp_rdma2dp_valid; +input pdp_rdma2dp_ready; +output [8*1 +11:0] pdp_rdma2dp_pd; +input cq2eg_pvld; +output cq2eg_prdy; +input [17:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +/////////////////////////////////////////////////////////////////////////////////////////// +reg [13:0] beat_cnt; +wire dma_rd_rsp_rdy; +wire dp2reg_done_flag; +reg [8*1 -1:0] dp_data; +wire dp_rdy; +reg dp_vld; +wire eg2ig_done_flag; +reg [5:0] fifo_sel_cnt; +reg is_cube_end; +reg is_line_end; +reg is_split_end; +reg is_surf_end; +reg pdp2cvif_rd_cdt_lat_fifo_pop; +reg pdp2mcif_rd_cdt_lat_fifo_pop; +wire [8*1 +11:0] pdp_rdma2dp_pd; +wire rdma2wdma_done_flag; +reg [3:0] tran_cnt; +reg [13:0] width_cnt; +wire [( 64 + (64/8/8) )-1:0] cv_dma_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] cv_int_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] cvif2pdp_rd_rsp_pd_d0; +wire [( 64 + (64/8/8) )-1:0] cvif2pdp_rd_rsp_pd_d1; +wire [( 64 + (64/8/8) )-1:0] dma_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] lat_rd_pd; +wire [( 64 + (64/8/8) )-1:0] mc_dma_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] mc_int_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd_d0; +wire [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd_d1; +wire cv_dma_rd_rsp_vld; +wire cv_int_rd_rsp_ready; +wire cv_int_rd_rsp_valid; +wire cvif2pdp_rd_rsp_ready_d0; +wire cvif2pdp_rd_rsp_ready_d1; +wire cvif2pdp_rd_rsp_valid_d0; +wire cvif2pdp_rd_rsp_valid_d1; +wire dma_rd_cdt_lat_fifo_pop; +wire dma_rd_rsp_ram_type; +wire dma_rd_rsp_vld; +wire dp2reg_done_f; +wire dp_b_sync; +wire dp_cube_end; +wire dp_line_end; +wire [8*1 +11:0] dp_pd; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire dp_split_end; +wire dp_surf_end; +wire eccg_dma_rd_rsp_rdy; +wire eg2ig_done_f; +wire [7:0] fifo_rd_pvld; +wire [5:0] fifo_sel; +wire ig2eg_align; +wire ig2eg_cube_end; +wire ig2eg_line_end; +wire [12:0] ig2eg_size; +wire ig2eg_split_end; +wire ig2eg_surf_end; +wire is_b_sync; +wire is_last_beat; +wire is_last_tran; +wire [64 -1:0] lat_rd_data; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: print "wire [${M}-1:0] lat_rd_mask; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [1-1:0] lat_rd_mask; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire lat_rd_prdy; +wire lat_rd_pvld; +wire mc_dma_rd_rsp_vld; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire mcif2pdp_rd_rsp_ready_d0; +wire mcif2pdp_rd_rsp_ready_d1; +wire mcif2pdp_rd_rsp_valid_d0; +wire mcif2pdp_rd_rsp_valid_d1; +wire [10:0] mon_dp_pos_w; +wire rdma2wdma_done_f; +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${kx}-1:0] ro${m}_rd_pd; +//: wire ro${m}_rd_prdy; +//: wire ro${m}_rd_pvld; +//: wire [${kx}-1:0] ro${m}_wr_pd; +//: ); +//: } +//: foreach my $m (0..$M-1) { +//: print qq( +//: wire ro${m}_wr_pvld; +//: wire ro${m}_wr_rdy; +//: ); +//: } +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire [${F}-1:0] ro${i}_wr_rdys; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8-1:0] ro0_rd_pd; +wire ro0_rd_prdy; +wire ro0_rd_pvld; +wire [8-1:0] ro0_wr_pd; + +wire [8-1:0] ro1_rd_pd; +wire ro1_rd_prdy; +wire ro1_rd_pvld; +wire [8-1:0] ro1_wr_pd; + +wire [8-1:0] ro2_rd_pd; +wire ro2_rd_prdy; +wire ro2_rd_pvld; +wire [8-1:0] ro2_wr_pd; + +wire [8-1:0] ro3_rd_pd; +wire ro3_rd_prdy; +wire ro3_rd_pvld; +wire [8-1:0] ro3_wr_pd; + +wire [8-1:0] ro4_rd_pd; +wire ro4_rd_prdy; +wire ro4_rd_pvld; +wire [8-1:0] ro4_wr_pd; + +wire [8-1:0] ro5_rd_pd; +wire ro5_rd_prdy; +wire ro5_rd_pvld; +wire [8-1:0] ro5_wr_pd; + +wire [8-1:0] ro6_rd_pd; +wire ro6_rd_prdy; +wire ro6_rd_pvld; +wire [8-1:0] ro6_wr_pd; + +wire [8-1:0] ro7_rd_pd; +wire ro7_rd_prdy; +wire ro7_rd_pvld; +wire [8-1:0] ro7_wr_pd; + +wire ro0_wr_pvld; +wire ro0_wr_rdy; + +wire [8-1:0] ro0_wr_rdys; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire tran_accept; +wire tran_cnt_idle; +wire [13:0] tran_num; +wire tran_rdy; +wire tran_vld; +/////////////////////////////////////////////////////////////////////////////////// +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2pdp_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2pdp_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2pdp_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +//////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + pdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2cvif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + pdp2cvif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b0); + end +end +assign dma_rd_rsp_ram_type = reg2dp_src_ram_type; +//pipe for timing closure +//: my $s = ( 64 + (64/8/8) ); +//: &eperl::pipe("-is -wid $s -do eccg_dma_rd_rsp_pd -vo eccg_dma_rd_rsp_vld -ri eccg_dma_rd_rsp_rdy -di dma_rd_rsp_pd -vi dma_rd_rsp_vld -ro dma_rd_rsp_rdy_f "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg dma_rd_rsp_rdy_f; +reg skid_flop_dma_rd_rsp_rdy_f; +reg skid_flop_dma_rd_rsp_vld; +reg [65-1:0] skid_flop_dma_rd_rsp_pd; +reg pipe_skid_dma_rd_rsp_vld; +reg [65-1:0] pipe_skid_dma_rd_rsp_pd; +// Wire +wire skid_dma_rd_rsp_vld; +wire [65-1:0] skid_dma_rd_rsp_pd; +wire skid_dma_rd_rsp_rdy_f; +wire pipe_skid_dma_rd_rsp_rdy_f; +wire eccg_dma_rd_rsp_vld; +wire [65-1:0] eccg_dma_rd_rsp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_rd_rsp_rdy_f <= 1'b1; + skid_flop_dma_rd_rsp_rdy_f <= 1'b1; + end else begin + dma_rd_rsp_rdy_f <= skid_dma_rd_rsp_rdy_f; + skid_flop_dma_rd_rsp_rdy_f <= skid_dma_rd_rsp_rdy_f; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_dma_rd_rsp_vld <= 1'b0; + end else begin + if (skid_flop_dma_rd_rsp_rdy_f) begin + skid_flop_dma_rd_rsp_vld <= dma_rd_rsp_vld; + end + end +end +assign skid_dma_rd_rsp_vld = (skid_flop_dma_rd_rsp_rdy_f) ? dma_rd_rsp_vld : skid_flop_dma_rd_rsp_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_dma_rd_rsp_rdy_f & dma_rd_rsp_vld) begin + skid_flop_dma_rd_rsp_pd[65-1:0] <= dma_rd_rsp_pd[65-1:0]; + end +end +assign skid_dma_rd_rsp_pd[65-1:0] = (skid_flop_dma_rd_rsp_rdy_f) ? dma_rd_rsp_pd[65-1:0] : skid_flop_dma_rd_rsp_pd[65-1:0]; + + +// PIPE READY +assign skid_dma_rd_rsp_rdy_f = pipe_skid_dma_rd_rsp_rdy_f || !pipe_skid_dma_rd_rsp_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_dma_rd_rsp_vld <= 1'b0; + end else begin + if (skid_dma_rd_rsp_rdy_f) begin + pipe_skid_dma_rd_rsp_vld <= skid_dma_rd_rsp_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_dma_rd_rsp_rdy_f && skid_dma_rd_rsp_vld) begin + pipe_skid_dma_rd_rsp_pd[65-1:0] <= skid_dma_rd_rsp_pd[65-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_dma_rd_rsp_rdy_f = eccg_dma_rd_rsp_rdy; +assign eccg_dma_rd_rsp_vld = pipe_skid_dma_rd_rsp_vld; +assign eccg_dma_rd_rsp_pd = pipe_skid_dma_rd_rsp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dma_rd_rsp_rdy = dma_rd_rsp_rdy_f; +//============== +// Latency FIFO to buffer return DATA +//============== +NV_NVDLA_PDP_RDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lat_wr_prdy (eccg_dma_rd_rsp_rdy) //|> w + ,.lat_wr_pvld (eccg_dma_rd_rsp_vld) //|< r + ,.lat_wr_pd (eccg_dma_rd_rsp_pd) //|< r + ,.lat_rd_prdy (lat_rd_prdy) //|< w + ,.lat_rd_pvld (lat_rd_pvld) //|> w + ,.lat_rd_pd (lat_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign lat_rd_data[64 -1:0] = lat_rd_pd[64 -1:0]; +assign lat_rd_mask[1 -1:0] = lat_rd_pd[65 -1: 64]; +////: my $k = NVDLA_PDP_DMAIF_BW; +////: my $jx = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_PDP_BWPE; ##atomic_m BW +////: my $M = $k/$jx; ##atomic_m number per dma transaction +////: if($M > 1) { +////: print "assign lat_rd_mask[${M}-1:0] = lat_rd_pd[${k}+${M}-1:${k}]; \n"; +////: } +assign dma_rd_cdt_lat_fifo_pop = lat_rd_pvld & lat_rd_prdy; +// only care the rdy of ro-fifo which mask bit indidates +assign lat_rd_prdy = lat_rd_pvld +//: my $msk = 1; +//: foreach my $k (0..$msk-1) { +//: print " & (~lat_rd_mask[$k] | (lat_rd_mask[$k] & ro${k}_wr_rdy)) \n"; +//: } +//: print " ; \n"; +//: +//: +//: my $tp = 1*8; ##throughput BW +//: my $atmm = 8*8; ##atomic_m BW +//: my $k = 64/$tp; ##total fifo num +//: my $M = 64/$atmm; ##atomic_m number per dma transaction +//: my $F = $atmm/$tp; ##how many fifo contribute to one atomic_m +//: +//: +//: print " // when also need send to other group of ro-fif, need clamp the vld if others are not ready \n"; +//: foreach my $i (0..$M-1){ +//: print " assign ro${i}_wr_pvld = lat_rd_pvld & (lat_rd_mask[${i}] & ro${i}_wr_rdy) \n"; +//: foreach my $s (0..$msk-1) { +//: if($s != $i) { +//: print " & ( ~lat_rd_mask[${s}] | (lat_rd_mask[${s}] & ro${s}_wr_rdy)) \n"; +//: } +//: } +//: print " ; \n"; +//: } +//: +//: +//: foreach my $m (0..$M-1) { +//: print " assign ro${m}_wr_rdy = &ro${m}_wr_rdys; \n"; +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_wr_pd = lat_rd_data[${tp}*${r}+${tp}-1:${tp}*${r}]; \n"; +//: print " NV_NVDLA_PDP_RDMA_ro_fifo u_ro${r}_fifo( \n"; +//: print " .nvdla_core_clk (nvdla_core_clk) \n"; +//: print " ,.nvdla_core_rstn (nvdla_core_rstn) \n"; +//: print " ,.ro_wr_prdy (ro${m}_wr_rdys[$f]) \n"; +//: print " ,.ro_wr_pvld (ro${m}_wr_pvld) \n"; +//: print " ,.ro_wr_pd (ro${r}_wr_pd) \n"; +//: print " ,.ro_rd_prdy (ro${r}_rd_prdy) \n"; +//: print " ,.ro_rd_pvld (ro${r}_rd_pvld) \n"; +//: print " ,.ro_rd_pd (ro${r}_rd_pd) \n"; +//: print " ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) \n"; +//: print " ); \n"; +//: } +//: } +//: +//: +//: print " // DATA MUX out \n"; +//: print " assign fifo_sel = fifo_sel_cnt; \n"; +//: print " always @(*) begin \n"; +//: print " case(fifo_sel) \n"; +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " 6'd$r: begin \n"; +//: print " dp_vld = ro${r}_rd_pvld & (~tran_cnt_idle); \n"; +//: print " dp_data = ro${r}_rd_pd; \n"; +//: print " end \n"; +//: } +//: } +//: print "default: begin \n"; +//: print " dp_vld = 1'b0; \n"; +//: print " dp_data = ${tp}'d0; \n"; +//: print "end \n"; +//: print "endcase \n"; +//: print "end \n"; +//: +//: +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_rd_prdy = dp_rdy & (fifo_sel==$r) & (~tran_cnt_idle); \n"; +//: } +//: } +//: +//| eperl: generated_beg (DO NOT EDIT BELOW) + & (~lat_rd_mask[0] | (lat_rd_mask[0] & ro0_wr_rdy)) + ; + // when also need send to other group of ro-fif, need clamp the vld if others are not ready + assign ro0_wr_pvld = lat_rd_pvld & (lat_rd_mask[0] & ro0_wr_rdy) + ; + assign ro0_wr_rdy = &ro0_wr_rdys; + assign ro0_wr_pd = lat_rd_data[8*0+8-1:8*0]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro0_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[0]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro0_wr_pd) + ,.ro_rd_prdy (ro0_rd_prdy) + ,.ro_rd_pvld (ro0_rd_pvld) + ,.ro_rd_pd (ro0_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro1_wr_pd = lat_rd_data[8*1+8-1:8*1]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro1_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[1]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro1_wr_pd) + ,.ro_rd_prdy (ro1_rd_prdy) + ,.ro_rd_pvld (ro1_rd_pvld) + ,.ro_rd_pd (ro1_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro2_wr_pd = lat_rd_data[8*2+8-1:8*2]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro2_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[2]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro2_wr_pd) + ,.ro_rd_prdy (ro2_rd_prdy) + ,.ro_rd_pvld (ro2_rd_pvld) + ,.ro_rd_pd (ro2_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro3_wr_pd = lat_rd_data[8*3+8-1:8*3]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro3_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[3]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro3_wr_pd) + ,.ro_rd_prdy (ro3_rd_prdy) + ,.ro_rd_pvld (ro3_rd_pvld) + ,.ro_rd_pd (ro3_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro4_wr_pd = lat_rd_data[8*4+8-1:8*4]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro4_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[4]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro4_wr_pd) + ,.ro_rd_prdy (ro4_rd_prdy) + ,.ro_rd_pvld (ro4_rd_pvld) + ,.ro_rd_pd (ro4_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro5_wr_pd = lat_rd_data[8*5+8-1:8*5]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro5_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[5]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro5_wr_pd) + ,.ro_rd_prdy (ro5_rd_prdy) + ,.ro_rd_pvld (ro5_rd_pvld) + ,.ro_rd_pd (ro5_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro6_wr_pd = lat_rd_data[8*6+8-1:8*6]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro6_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[6]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro6_wr_pd) + ,.ro_rd_prdy (ro6_rd_prdy) + ,.ro_rd_pvld (ro6_rd_pvld) + ,.ro_rd_pd (ro6_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + assign ro7_wr_pd = lat_rd_data[8*7+8-1:8*7]; + NV_NVDLA_PDP_RDMA_ro_fifo u_ro7_fifo( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ro_wr_prdy (ro0_wr_rdys[7]) + ,.ro_wr_pvld (ro0_wr_pvld) + ,.ro_wr_pd (ro7_wr_pd) + ,.ro_rd_prdy (ro7_rd_prdy) + ,.ro_rd_pvld (ro7_rd_pvld) + ,.ro_rd_pd (ro7_rd_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); + // DATA MUX out + assign fifo_sel = fifo_sel_cnt; + always @(*) begin + case(fifo_sel) + 6'd0: begin + dp_vld = ro0_rd_pvld & (~tran_cnt_idle); + dp_data = ro0_rd_pd; + end + 6'd1: begin + dp_vld = ro1_rd_pvld & (~tran_cnt_idle); + dp_data = ro1_rd_pd; + end + 6'd2: begin + dp_vld = ro2_rd_pvld & (~tran_cnt_idle); + dp_data = ro2_rd_pd; + end + 6'd3: begin + dp_vld = ro3_rd_pvld & (~tran_cnt_idle); + dp_data = ro3_rd_pd; + end + 6'd4: begin + dp_vld = ro4_rd_pvld & (~tran_cnt_idle); + dp_data = ro4_rd_pd; + end + 6'd5: begin + dp_vld = ro5_rd_pvld & (~tran_cnt_idle); + dp_data = ro5_rd_pd; + end + 6'd6: begin + dp_vld = ro6_rd_pvld & (~tran_cnt_idle); + dp_data = ro6_rd_pd; + end + 6'd7: begin + dp_vld = ro7_rd_pvld & (~tran_cnt_idle); + dp_data = ro7_rd_pd; + end +default: begin + dp_vld = 1'b0; + dp_data = 8'd0; +end +endcase +end + assign ro0_rd_prdy = dp_rdy & (fifo_sel==0) & (~tran_cnt_idle); + assign ro1_rd_prdy = dp_rdy & (fifo_sel==1) & (~tran_cnt_idle); + assign ro2_rd_prdy = dp_rdy & (fifo_sel==2) & (~tran_cnt_idle); + assign ro3_rd_prdy = dp_rdy & (fifo_sel==3) & (~tran_cnt_idle); + assign ro4_rd_prdy = dp_rdy & (fifo_sel==4) & (~tran_cnt_idle); + assign ro5_rd_prdy = dp_rdy & (fifo_sel==5) & (~tran_cnt_idle); + assign ro6_rd_prdy = dp_rdy & (fifo_sel==6) & (~tran_cnt_idle); + assign ro7_rd_prdy = dp_rdy & (fifo_sel==7) & (~tran_cnt_idle); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// Context Queue: read +//============== +//============== +// Return Data Counting +//============== +// unpack from rd_pd, which should be the same order as wr_pd +assign cq2eg_prdy = tran_rdy; +assign tran_vld = cq2eg_pvld; +// PKT_UNPACK_WIRE( pdp_rdma_ig2eg , ig2eg_ , cq2eg_pd ) +assign ig2eg_size[12:0] = cq2eg_pd[12:0]; +assign ig2eg_align = cq2eg_pd[13]; +assign ig2eg_line_end = cq2eg_pd[14]; +assign ig2eg_surf_end = cq2eg_pd[15]; +assign ig2eg_split_end = cq2eg_pd[16]; +assign ig2eg_cube_end = cq2eg_pd[17]; +assign tran_num[13:0] = cq2eg_pvld ? (ig2eg_size + 1) : 14'b0; +assign tran_cnt_idle = (tran_cnt==0); +assign is_last_tran = (tran_cnt==1); +assign is_last_beat = (beat_cnt==1); +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $r (0..$k-1) { +//: print " assign fifo_rd_pvld[$r] = (fifo_sel==${r}) & ro${r}_rd_pvld; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign fifo_rd_pvld[0] = (fifo_sel==0) & ro0_rd_pvld; + assign fifo_rd_pvld[1] = (fifo_sel==1) & ro1_rd_pvld; + assign fifo_rd_pvld[2] = (fifo_sel==2) & ro2_rd_pvld; + assign fifo_rd_pvld[3] = (fifo_sel==3) & ro3_rd_pvld; + assign fifo_rd_pvld[4] = (fifo_sel==4) & ro4_rd_pvld; + assign fifo_rd_pvld[5] = (fifo_sel==5) & ro5_rd_pvld; + assign fifo_rd_pvld[6] = (fifo_sel==6) & ro6_rd_pvld; + assign fifo_rd_pvld[7] = (fifo_sel==7) & ro7_rd_pvld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign tran_rdy = (tran_cnt_idle & (|fifo_rd_pvld)) || (is_last_tran & is_last_beat & dp_rdy); +assign tran_accept = tran_vld & tran_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + fifo_sel_cnt <= {6{1'b0}}; + end else begin + if(is_cube_end & is_b_sync) begin + fifo_sel_cnt <= 6'd0; + end else if (tran_rdy) begin + fifo_sel_cnt <= 6'd0; + end else if (dp_rdy & |fifo_rd_pvld) +//: my $kx = 1*8; ##throughput BW +//: my $k = 64/$kx; ##total fifo num +//: print " fifo_sel_cnt <= (fifo_sel_cnt==(6'd${k}-1))? 6'd0 : fifo_sel_cnt + 1; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + fifo_sel_cnt <= (fifo_sel_cnt==(6'd8-1))? 6'd0 : fifo_sel_cnt + 1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_cnt <= {4{1'b0}}; + beat_cnt <= {14{1'b0}}; + end else begin + if(is_cube_end & is_b_sync) begin + tran_cnt <= 4'd0; + beat_cnt <= 4'd0; + end if (tran_rdy) begin + if (tran_vld) begin +//: my $txnum = 8/1; +//: print " tran_cnt <= 4'd${txnum}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + tran_cnt <= 4'd8; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + beat_cnt <= tran_num; + end else begin + tran_cnt <= 0; + beat_cnt <= 0; + end + end else if (dp_rdy & |fifo_rd_pvld) begin + beat_cnt <= (beat_cnt==1)? width_cnt : beat_cnt - 1; + if (is_last_beat) begin + tran_cnt <= tran_cnt - 1; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cnt <= {14{1'b0}}; + end else begin + if ((tran_accept) == 1'b1) begin + width_cnt <= tran_num; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + width_cnt <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_line_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_line_end <= ig2eg_line_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_line_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_surf_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_surf_end <= ig2eg_surf_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_surf_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_split_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_split_end <= ig2eg_split_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_split_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_cube_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_cube_end <= ig2eg_cube_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_cube_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign is_b_sync = is_last_beat & is_last_tran & dp_rdy; +assign {mon_dp_pos_w[10:0],dp_pos_w[3:0]} = width_cnt - beat_cnt; +//: my $pdpbw = 1*8; ##throughput BW +//: my $atmbw = 8*8; ##atomic_m BW +//: my $k = 64/$pdpbw; ##total fifo num +//: my $M = 64/$atmbw; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: my $cmax = int( log($F)/log(2)); +//: print " assign dp_pos_c[2:0] = fifo_sel[${cmax}-1:0];//need update to 5bits when configurable \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign dp_pos_c[2:0] = fifo_sel[3-1:0];//need update to 5bits when configurable + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp_b_sync = is_b_sync; +assign dp_line_end = is_line_end; +assign dp_surf_end = is_surf_end; +assign dp_split_end = is_split_end; +assign dp_cube_end = is_cube_end; +assign dp2reg_done_f = is_cube_end & is_b_sync; +assign eg2ig_done_f = is_cube_end & is_b_sync; +assign rdma2wdma_done_f = is_cube_end & is_b_sync; +//============== +// OUTPUT PACK and PIPE: To Data Processor +//============== +// PD Pack +// PKT_PACK_WIRE( pdp_rdma2dp , dp_ , dp_pd ) +assign dp_pd[8*1 -1:0] = dp_data[8*1 -1:0]; +assign dp_pd[8*1 +3:8*1] = dp_pos_w[3:0]; +assign dp_pd[8*1 +6:8*1 +4] = dp_pos_c[2:0]; +assign dp_pd[8*1 +7] = dp_b_sync ; +assign dp_pd[8*1 +8] = dp_line_end ; +assign dp_pd[8*1 +9] = dp_surf_end ; +assign dp_pd[8*1 +10] = dp_split_end ; +assign dp_pd[8*1 +11] = dp_cube_end ; +wire [8*1 +14:0] eg_out_pipe0_di; +assign eg_out_pipe0_di = {dp_pd,rdma2wdma_done_f,eg2ig_done_f,dp2reg_done_f}; +//: my $k = 8*1 +15; +//: &eperl::pipe("-is -wid $k -do eg_out_pipe0_do -vo pdp_rdma2dp_valid_f -ri pdp_rdma2dp_ready -di eg_out_pipe0_di -vi dp_vld -ro dp_rdy_ff "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg dp_rdy_ff; +reg skid_flop_dp_rdy_ff; +reg skid_flop_dp_vld; +reg [23-1:0] skid_flop_eg_out_pipe0_di; +reg pipe_skid_dp_vld; +reg [23-1:0] pipe_skid_eg_out_pipe0_di; +// Wire +wire skid_dp_vld; +wire [23-1:0] skid_eg_out_pipe0_di; +wire skid_dp_rdy_ff; +wire pipe_skid_dp_rdy_ff; +wire pdp_rdma2dp_valid_f; +wire [23-1:0] eg_out_pipe0_do; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp_rdy_ff <= 1'b1; + skid_flop_dp_rdy_ff <= 1'b1; + end else begin + dp_rdy_ff <= skid_dp_rdy_ff; + skid_flop_dp_rdy_ff <= skid_dp_rdy_ff; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_dp_vld <= 1'b0; + end else begin + if (skid_flop_dp_rdy_ff) begin + skid_flop_dp_vld <= dp_vld; + end + end +end +assign skid_dp_vld = (skid_flop_dp_rdy_ff) ? dp_vld : skid_flop_dp_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_dp_rdy_ff & dp_vld) begin + skid_flop_eg_out_pipe0_di[23-1:0] <= eg_out_pipe0_di[23-1:0]; + end +end +assign skid_eg_out_pipe0_di[23-1:0] = (skid_flop_dp_rdy_ff) ? eg_out_pipe0_di[23-1:0] : skid_flop_eg_out_pipe0_di[23-1:0]; + + +// PIPE READY +assign skid_dp_rdy_ff = pipe_skid_dp_rdy_ff || !pipe_skid_dp_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_dp_vld <= 1'b0; + end else begin + if (skid_dp_rdy_ff) begin + pipe_skid_dp_vld <= skid_dp_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_dp_rdy_ff && skid_dp_vld) begin + pipe_skid_eg_out_pipe0_di[23-1:0] <= skid_eg_out_pipe0_di[23-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_dp_rdy_ff = pdp_rdma2dp_ready; +assign pdp_rdma2dp_valid_f = pipe_skid_dp_vld; +assign eg_out_pipe0_do = pipe_skid_eg_out_pipe0_di; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign dp_rdy = dp_rdy_ff; +assign {pdp_rdma2dp_pd,rdma2wdma_done_flag,eg2ig_done_flag,dp2reg_done_flag} = eg_out_pipe0_do; +assign pdp_rdma2dp_valid = pdp_rdma2dp_valid_f; +assign rdma2wdma_done = (pdp_rdma2dp_valid_f & pdp_rdma2dp_ready & rdma2wdma_done_flag) ? 1'b1 : 1'b0; +assign eg2ig_done = (pdp_rdma2dp_valid_f & pdp_rdma2dp_ready & eg2ig_done_flag) ? 1'b1 : 1'b0; +assign dp2reg_done = (pdp_rdma2dp_valid_f & pdp_rdma2dp_ready & dp2reg_done_flag) ? 1'b1 : 1'b0; +////============== +////OBS signals +////============== +//assign obs_bus_pdp_rdma_wr_0x_vld = ro0_wr_pvld; +//assign obs_bus_pdp_rdma_wr_1x_vld = ro1_wr_pvld; +//assign obs_bus_pdp_rdma_rd_00_rdy = ro0_rd_prdy; +//assign obs_bus_pdp_rdma_rd_10_rdy = ro4_rd_prdy; +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property PDP_RDMA_eg__bsync_end_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_beat & is_last_tran & (~dp_rdy); + endproperty +// Cover 0 : "is_last_beat & is_last_tran & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__bsync_end_stall__0_COV : cover property (PDP_RDMA_eg__bsync_end_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__line_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_line_end & (~dp_rdy); + endproperty +// Cover 1 : "is_line_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__line_end_stall__1_COV : cover property (PDP_RDMA_eg__line_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__surf_end_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_surf_end & (~dp_rdy); + endproperty +// Cover 2 : "is_surf_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__surf_end_stall__2_COV : cover property (PDP_RDMA_eg__surf_end_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__split_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_split_end & (~dp_rdy); + endproperty +// Cover 3 : "is_split_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__split_end_stall__3_COV : cover property (PDP_RDMA_eg__split_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__cube_end_stall__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_cube_end & (~dp_rdy); + endproperty +// Cover 4 : "is_cube_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__cube_end_stall__4_COV : cover property (PDP_RDMA_eg__cube_end_stall__4_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg_backpressure_cq__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + tran_rdy & (~tran_vld) & (~is_cube_end); + endproperty +// Cover 5 : "tran_rdy & (~tran_vld) & (~is_cube_end)" + FUNCPOINT_PDP_RDMA_eg_backpressure_cq__5_COV : cover property (PDP_RDMA_eg_backpressure_cq__5_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_PDP_RDMA_eg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_RDMA_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 61 -w 514 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] lat_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_61 = ( wr_count_next_no_wr_popping == 6'd61 ); +wire wr_count_next_is_61 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_61; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 6'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [5:0] lat_wr_adr; // current write address +wire [5:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_61x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [5:0] wr_adr_next = (lat_wr_adr == 6'd60) ? 6'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 6'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [5:0] lat_rd_adr; // current read address +// next read address +wire [5:0] rd_adr_next = (lat_rd_adr == 6'd60) ? 6'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 6'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [5:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 6'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd61 : wr_limit_reg} ) + , .curr ( {26'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_RDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_PDP_RDMA_lat_fifo +// Re-Order Data +// if we have rd_reg, then depth = required - 1 ,so depth=4-1=3 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_RDMA_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -rd_reg -rand_none -ram_bypass -d 3 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +input [7:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [7:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] ro_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 3'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [1:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 3'd4 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int && !ro_rd_prdy); +reg [2:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] ro_rd_pd; // output data register +wire rd_req_next = (ro_rd_pvld_p || (ro_rd_pvld_int && !ro_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + end else begin + ro_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ro_rd_pd <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ro_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_RDMA_ro_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_RDMA_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [7:0] Di0; +input [1:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8] } +endmodule // vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +//vmw: Memory vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +//vmw: Address-size 2 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v.vcp new file mode 100644 index 0000000..b3fd8b8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v.vcp @@ -0,0 +1,1918 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,mcif2pdp_rd_rsp_pd //|< i + ,mcif2pdp_rd_rsp_valid //|< i + ,pdp_rdma2dp_ready //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_src_ram_type //|< i + ,cq2eg_prdy //|> o + ,dp2reg_done //|> o + ,eg2ig_done //|> o + ,mcif2pdp_rd_rsp_ready //|> o + ,pdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,pdp_rdma2dp_pd //|> o + ,pdp_rdma2dp_valid //|> o + ,rdma2wdma_done //|> o + ); +/////////////////////////////////////////////////////////////////////////////////////////// +input reg2dp_src_ram_type; +output dp2reg_done; +output eg2ig_done; +output rdma2wdma_done; +// +input nvdla_core_clk; +input nvdla_core_rstn; +input mcif2pdp_rd_rsp_valid; +output mcif2pdp_rd_rsp_ready; +input [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd; +output pdp2mcif_rd_cdt_lat_fifo_pop; +output pdp_rdma2dp_valid; +input pdp_rdma2dp_ready; +output [8*1 +11:0] pdp_rdma2dp_pd; +input cq2eg_pvld; +output cq2eg_prdy; +input [17:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +/////////////////////////////////////////////////////////////////////////////////////////// +reg [13:0] beat_cnt; +wire dma_rd_rsp_rdy; +wire dp2reg_done_flag; +reg [8*1 -1:0] dp_data; +wire dp_rdy; +reg dp_vld; +wire eg2ig_done_flag; +reg [5:0] fifo_sel_cnt; +reg is_cube_end; +reg is_line_end; +reg is_split_end; +reg is_surf_end; +reg pdp2cvif_rd_cdt_lat_fifo_pop; +reg pdp2mcif_rd_cdt_lat_fifo_pop; +wire [8*1 +11:0] pdp_rdma2dp_pd; +wire rdma2wdma_done_flag; +reg [3:0] tran_cnt; +reg [13:0] width_cnt; +wire [( 64 + (64/8/8) )-1:0] cv_dma_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] cv_int_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] cvif2pdp_rd_rsp_pd_d0; +wire [( 64 + (64/8/8) )-1:0] cvif2pdp_rd_rsp_pd_d1; +wire [( 64 + (64/8/8) )-1:0] dma_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] lat_rd_pd; +wire [( 64 + (64/8/8) )-1:0] mc_dma_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] mc_int_rd_rsp_pd; +wire [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd_d0; +wire [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd_d1; +wire cv_dma_rd_rsp_vld; +wire cv_int_rd_rsp_ready; +wire cv_int_rd_rsp_valid; +wire cvif2pdp_rd_rsp_ready_d0; +wire cvif2pdp_rd_rsp_ready_d1; +wire cvif2pdp_rd_rsp_valid_d0; +wire cvif2pdp_rd_rsp_valid_d1; +wire dma_rd_cdt_lat_fifo_pop; +wire dma_rd_rsp_ram_type; +wire dma_rd_rsp_vld; +wire dp2reg_done_f; +wire dp_b_sync; +wire dp_cube_end; +wire dp_line_end; +wire [8*1 +11:0] dp_pd; +wire [2:0] dp_pos_c; +wire [3:0] dp_pos_w; +wire dp_split_end; +wire dp_surf_end; +wire eccg_dma_rd_rsp_rdy; +wire eg2ig_done_f; +wire [7:0] fifo_rd_pvld; +wire [5:0] fifo_sel; +wire ig2eg_align; +wire ig2eg_cube_end; +wire ig2eg_line_end; +wire [12:0] ig2eg_size; +wire ig2eg_split_end; +wire ig2eg_surf_end; +wire is_b_sync; +wire is_last_beat; +wire is_last_tran; +wire [64 -1:0] lat_rd_data; +//: my $jx = 8*8; ##atomic_m BW +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: print "wire [${M}-1:0] lat_rd_mask; \n"; +wire lat_rd_prdy; +wire lat_rd_pvld; +wire mc_dma_rd_rsp_vld; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire mcif2pdp_rd_rsp_ready_d0; +wire mcif2pdp_rd_rsp_ready_d1; +wire mcif2pdp_rd_rsp_valid_d0; +wire mcif2pdp_rd_rsp_valid_d1; +wire [10:0] mon_dp_pos_w; +wire rdma2wdma_done_f; +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma transaction +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $m (0..$k-1) { +//: print qq( +//: wire [${kx}-1:0] ro${m}_rd_pd; +//: wire ro${m}_rd_prdy; +//: wire ro${m}_rd_pvld; +//: wire [${kx}-1:0] ro${m}_wr_pd; +//: ); +//: } +//: foreach my $m (0..$M-1) { +//: print qq( +//: wire ro${m}_wr_pvld; +//: wire ro${m}_wr_rdy; +//: ); +//: } +//: foreach my $i (0..$M-1) { +//: print qq( +//: wire [${F}-1:0] ro${i}_wr_rdys; +//: ); +//: } +wire tran_accept; +wire tran_cnt_idle; +wire [13:0] tran_num; +wire tran_rdy; +wire tran_vld; +/////////////////////////////////////////////////////////////////////////////////// +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_PDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2pdp_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2pdp_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2pdp_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +//////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + pdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2cvif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + pdp2cvif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b0); + end +end +assign dma_rd_rsp_ram_type = reg2dp_src_ram_type; +//pipe for timing closure +//: my $s = ( 64 + (64/8/8) ); +//: &eperl::pipe("-is -wid $s -do eccg_dma_rd_rsp_pd -vo eccg_dma_rd_rsp_vld -ri eccg_dma_rd_rsp_rdy -di dma_rd_rsp_pd -vi dma_rd_rsp_vld -ro dma_rd_rsp_rdy_f "); +assign dma_rd_rsp_rdy = dma_rd_rsp_rdy_f; +//============== +// Latency FIFO to buffer return DATA +//============== +NV_NVDLA_PDP_RDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lat_wr_prdy (eccg_dma_rd_rsp_rdy) //|> w + ,.lat_wr_pvld (eccg_dma_rd_rsp_vld) //|< r + ,.lat_wr_pd (eccg_dma_rd_rsp_pd) //|< r + ,.lat_rd_prdy (lat_rd_prdy) //|< w + ,.lat_rd_pvld (lat_rd_pvld) //|> w + ,.lat_rd_pd (lat_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign lat_rd_data[64 -1:0] = lat_rd_pd[64 -1:0]; +assign lat_rd_mask[1 -1:0] = lat_rd_pd[65 -1: 64]; +////: my $k = NVDLA_PDP_DMAIF_BW; +////: my $jx = NVDLA_MEMORY_ATOMIC_SIZE*NVDLA_PDP_BWPE; ##atomic_m BW +////: my $M = $k/$jx; ##atomic_m number per dma transaction +////: if($M > 1) { +////: print "assign lat_rd_mask[${M}-1:0] = lat_rd_pd[${k}+${M}-1:${k}]; \n"; +////: } +assign dma_rd_cdt_lat_fifo_pop = lat_rd_pvld & lat_rd_prdy; +// only care the rdy of ro-fifo which mask bit indidates +assign lat_rd_prdy = lat_rd_pvld +//: my $msk = 1; +//: foreach my $k (0..$msk-1) { +//: print " & (~lat_rd_mask[$k] | (lat_rd_mask[$k] & ro${k}_wr_rdy)) \n"; +//: } +//: print " ; \n"; +//: +//: +//: my $tp = 1*8; ##throughput BW +//: my $atmm = 8*8; ##atomic_m BW +//: my $k = 64/$tp; ##total fifo num +//: my $M = 64/$atmm; ##atomic_m number per dma transaction +//: my $F = $atmm/$tp; ##how many fifo contribute to one atomic_m +//: +//: +//: print " // when also need send to other group of ro-fif, need clamp the vld if others are not ready \n"; +//: foreach my $i (0..$M-1){ +//: print " assign ro${i}_wr_pvld = lat_rd_pvld & (lat_rd_mask[${i}] & ro${i}_wr_rdy) \n"; +//: foreach my $s (0..$msk-1) { +//: if($s != $i) { +//: print " & ( ~lat_rd_mask[${s}] | (lat_rd_mask[${s}] & ro${s}_wr_rdy)) \n"; +//: } +//: } +//: print " ; \n"; +//: } +//: +//: +//: foreach my $m (0..$M-1) { +//: print " assign ro${m}_wr_rdy = &ro${m}_wr_rdys; \n"; +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_wr_pd = lat_rd_data[${tp}*${r}+${tp}-1:${tp}*${r}]; \n"; +//: print " NV_NVDLA_PDP_RDMA_ro_fifo u_ro${r}_fifo( \n"; +//: print " .nvdla_core_clk (nvdla_core_clk) \n"; +//: print " ,.nvdla_core_rstn (nvdla_core_rstn) \n"; +//: print " ,.ro_wr_prdy (ro${m}_wr_rdys[$f]) \n"; +//: print " ,.ro_wr_pvld (ro${m}_wr_pvld) \n"; +//: print " ,.ro_wr_pd (ro${r}_wr_pd) \n"; +//: print " ,.ro_rd_prdy (ro${r}_rd_prdy) \n"; +//: print " ,.ro_rd_pvld (ro${r}_rd_pvld) \n"; +//: print " ,.ro_rd_pd (ro${r}_rd_pd) \n"; +//: print " ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) \n"; +//: print " ); \n"; +//: } +//: } +//: +//: +//: print " // DATA MUX out \n"; +//: print " assign fifo_sel = fifo_sel_cnt; \n"; +//: print " always @(*) begin \n"; +//: print " case(fifo_sel) \n"; +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " 6'd$r: begin \n"; +//: print " dp_vld = ro${r}_rd_pvld & (~tran_cnt_idle); \n"; +//: print " dp_data = ro${r}_rd_pd; \n"; +//: print " end \n"; +//: } +//: } +//: print "default: begin \n"; +//: print " dp_vld = 1'b0; \n"; +//: print " dp_data = ${tp}'d0; \n"; +//: print "end \n"; +//: print "endcase \n"; +//: print "end \n"; +//: +//: +//: foreach my $m (0..$M-1) { +//: foreach my $f (0..$F-1) { +//: my $r = $F * $m + $f; +//: print " assign ro${r}_rd_prdy = dp_rdy & (fifo_sel==$r) & (~tran_cnt_idle); \n"; +//: } +//: } +//: +//============== +// Context Queue: read +//============== +//============== +// Return Data Counting +//============== +// unpack from rd_pd, which should be the same order as wr_pd +assign cq2eg_prdy = tran_rdy; +assign tran_vld = cq2eg_pvld; +// PKT_UNPACK_WIRE( pdp_rdma_ig2eg , ig2eg_ , cq2eg_pd ) +assign ig2eg_size[12:0] = cq2eg_pd[12:0]; +assign ig2eg_align = cq2eg_pd[13]; +assign ig2eg_line_end = cq2eg_pd[14]; +assign ig2eg_surf_end = cq2eg_pd[15]; +assign ig2eg_split_end = cq2eg_pd[16]; +assign ig2eg_cube_end = cq2eg_pd[17]; +assign tran_num[13:0] = cq2eg_pvld ? (ig2eg_size + 1) : 14'b0; +assign tran_cnt_idle = (tran_cnt==0); +assign is_last_tran = (tran_cnt==1); +assign is_last_beat = (beat_cnt==1); +//: my $kx = 1*8; ##throughput BW +//: my $jx = 8*8; ##atomic_m BW +//: my $k = 64/$kx; ##total fifo num +//: my $M = 64/$jx; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: foreach my $r (0..$k-1) { +//: print " assign fifo_rd_pvld[$r] = (fifo_sel==${r}) & ro${r}_rd_pvld; \n"; +//: } +assign tran_rdy = (tran_cnt_idle & (|fifo_rd_pvld)) || (is_last_tran & is_last_beat & dp_rdy); +assign tran_accept = tran_vld & tran_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + fifo_sel_cnt <= {6{1'b0}}; + end else begin + if(is_cube_end & is_b_sync) begin + fifo_sel_cnt <= 6'd0; + end else if (tran_rdy) begin + fifo_sel_cnt <= 6'd0; + end else if (dp_rdy & |fifo_rd_pvld) +//: my $kx = 1*8; ##throughput BW +//: my $k = 64/$kx; ##total fifo num +//: print " fifo_sel_cnt <= (fifo_sel_cnt==(6'd${k}-1))? 6'd0 : fifo_sel_cnt + 1; \n"; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + tran_cnt <= {4{1'b0}}; + beat_cnt <= {14{1'b0}}; + end else begin + if(is_cube_end & is_b_sync) begin + tran_cnt <= 4'd0; + beat_cnt <= 4'd0; + end if (tran_rdy) begin + if (tran_vld) begin +//: my $txnum = 8/1; +//: print " tran_cnt <= 4'd${txnum}; \n"; + beat_cnt <= tran_num; + end else begin + tran_cnt <= 0; + beat_cnt <= 0; + end + end else if (dp_rdy & |fifo_rd_pvld) begin + beat_cnt <= (beat_cnt==1)? width_cnt : beat_cnt - 1; + if (is_last_beat) begin + tran_cnt <= tran_cnt - 1; + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_cnt <= {14{1'b0}}; + end else begin + if ((tran_accept) == 1'b1) begin + width_cnt <= tran_num; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + width_cnt <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_line_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_line_end <= ig2eg_line_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_line_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_surf_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_surf_end <= ig2eg_surf_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_surf_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_split_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_split_end <= ig2eg_split_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_split_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + is_cube_end <= 1'b0; + end else begin + if ((tran_accept) == 1'b1) begin + is_cube_end <= ig2eg_cube_end; +// VCS coverage off + end else if ((tran_accept) == 1'b0) begin + end else begin + is_cube_end <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(tran_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign is_b_sync = is_last_beat & is_last_tran & dp_rdy; +assign {mon_dp_pos_w[10:0],dp_pos_w[3:0]} = width_cnt - beat_cnt; +//: my $pdpbw = 1*8; ##throughput BW +//: my $atmbw = 8*8; ##atomic_m BW +//: my $k = 64/$pdpbw; ##total fifo num +//: my $M = 64/$atmbw; ##atomic_m number per dma trans +//: my $F = $k/$M; ##how many fifo contribute to one atomic_m +//: my $cmax = int( log($F)/log(2)); +//: print " assign dp_pos_c[2:0] = fifo_sel[${cmax}-1:0];//need update to 5bits when configurable \n"; +assign dp_b_sync = is_b_sync; +assign dp_line_end = is_line_end; +assign dp_surf_end = is_surf_end; +assign dp_split_end = is_split_end; +assign dp_cube_end = is_cube_end; +assign dp2reg_done_f = is_cube_end & is_b_sync; +assign eg2ig_done_f = is_cube_end & is_b_sync; +assign rdma2wdma_done_f = is_cube_end & is_b_sync; +//============== +// OUTPUT PACK and PIPE: To Data Processor +//============== +// PD Pack +// PKT_PACK_WIRE( pdp_rdma2dp , dp_ , dp_pd ) +assign dp_pd[8*1 -1:0] = dp_data[8*1 -1:0]; +assign dp_pd[8*1 +3:8*1] = dp_pos_w[3:0]; +assign dp_pd[8*1 +6:8*1 +4] = dp_pos_c[2:0]; +assign dp_pd[8*1 +7] = dp_b_sync ; +assign dp_pd[8*1 +8] = dp_line_end ; +assign dp_pd[8*1 +9] = dp_surf_end ; +assign dp_pd[8*1 +10] = dp_split_end ; +assign dp_pd[8*1 +11] = dp_cube_end ; +wire [8*1 +14:0] eg_out_pipe0_di; +assign eg_out_pipe0_di = {dp_pd,rdma2wdma_done_f,eg2ig_done_f,dp2reg_done_f}; +//: my $k = 8*1 +15; +//: &eperl::pipe("-is -wid $k -do eg_out_pipe0_do -vo pdp_rdma2dp_valid_f -ri pdp_rdma2dp_ready -di eg_out_pipe0_di -vi dp_vld -ro dp_rdy_ff "); +assign dp_rdy = dp_rdy_ff; +assign {pdp_rdma2dp_pd,rdma2wdma_done_flag,eg2ig_done_flag,dp2reg_done_flag} = eg_out_pipe0_do; +assign pdp_rdma2dp_valid = pdp_rdma2dp_valid_f; +assign rdma2wdma_done = (pdp_rdma2dp_valid_f & pdp_rdma2dp_ready & rdma2wdma_done_flag) ? 1'b1 : 1'b0; +assign eg2ig_done = (pdp_rdma2dp_valid_f & pdp_rdma2dp_ready & eg2ig_done_flag) ? 1'b1 : 1'b0; +assign dp2reg_done = (pdp_rdma2dp_valid_f & pdp_rdma2dp_ready & dp2reg_done_flag) ? 1'b1 : 1'b0; +////============== +////OBS signals +////============== +//assign obs_bus_pdp_rdma_wr_0x_vld = ro0_wr_pvld; +//assign obs_bus_pdp_rdma_wr_1x_vld = ro1_wr_pvld; +//assign obs_bus_pdp_rdma_rd_00_rdy = ro0_rd_prdy; +//assign obs_bus_pdp_rdma_rd_10_rdy = ro4_rd_prdy; +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property PDP_RDMA_eg__bsync_end_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_last_beat & is_last_tran & (~dp_rdy); + endproperty +// Cover 0 : "is_last_beat & is_last_tran & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__bsync_end_stall__0_COV : cover property (PDP_RDMA_eg__bsync_end_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__line_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_line_end & (~dp_rdy); + endproperty +// Cover 1 : "is_line_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__line_end_stall__1_COV : cover property (PDP_RDMA_eg__line_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__surf_end_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_surf_end & (~dp_rdy); + endproperty +// Cover 2 : "is_surf_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__surf_end_stall__2_COV : cover property (PDP_RDMA_eg__surf_end_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__split_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_split_end & (~dp_rdy); + endproperty +// Cover 3 : "is_split_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__split_end_stall__3_COV : cover property (PDP_RDMA_eg__split_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg__cube_end_stall__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_cube_end & (~dp_rdy); + endproperty +// Cover 4 : "is_cube_end & (~dp_rdy)" + FUNCPOINT_PDP_RDMA_eg__cube_end_stall__4_COV : cover property (PDP_RDMA_eg__cube_end_stall__4_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_eg_backpressure_cq__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + tran_rdy & (~tran_vld) & (~is_cube_end); + endproperty +// Cover 5 : "tran_rdy & (~tran_vld) & (~is_cube_end)" + FUNCPOINT_PDP_RDMA_eg_backpressure_cq__5_COV : cover property (PDP_RDMA_eg_backpressure_cq__5_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_PDP_RDMA_eg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_RDMA_lat_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus lat_wr -rd_pipebus lat_rd -rd_reg -d 61 -w 514 -ram ra2 [Chosen ram type: ra2 - ramgen_generic (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [5:0] lat_wr_count; // write-side count +wire [5:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [5:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [5:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_61 = ( wr_count_next_no_wr_popping == 6'd61 ); +wire wr_count_next_is_61 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_61; +wire [5:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [5:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_61 || // busy next cycle? + (wr_limit_reg != 6'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 6'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [5:0] lat_wr_adr; // current write address +wire [5:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_61x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [5:0] wr_adr_next = (lat_wr_adr == 6'd60) ? 6'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 6'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [5:0] lat_rd_adr; // current read address +// next read address +wire [5:0] rd_adr_next = (lat_rd_adr == 6'd60) ? 6'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 6'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {6{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [5:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [5:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [5:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [5:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 6'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {6{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit : 6'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 6'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 6'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 6'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [5:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 6'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_PDP_RDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {26'd0, (wr_limit_reg == 6'd0) ? 6'd61 : wr_limit_reg} ) + , .curr ( {26'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_RDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_PDP_RDMA_lat_fifo +// Re-Order Data +// if we have rd_reg, then depth = required - 1 ,so depth=4-1=3 +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_RDMA_ro_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus ro_wr -rd_pipebus ro_rd -rd_reg -rand_none -ram_bypass -d 3 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_ro_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , ro_wr_prdy + , ro_wr_pvld + , ro_wr_pd + , ro_rd_prdy + , ro_rd_pvld + , ro_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ro_wr_prdy; +input ro_wr_pvld; +input [7:0] ro_wr_pd; +input ro_rd_prdy; +output ro_rd_pvld; +output [7:0] ro_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ro_wr_busy_int; // copy for internal use +assign ro_wr_prdy = !ro_wr_busy_int; +assign wr_reserving = ro_wr_pvld && !ro_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] ro_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? ro_wr_count : (ro_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (ro_wr_count + 1'd1) : ro_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ro_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check ro_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_busy_int <= 1'b0; + ro_wr_count <= 3'd0; + end else begin + ro_wr_busy_int <= ro_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ro_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ro_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ro_wr_pvld +// +// RAM +// +reg [1:0] ro_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + ro_wr_adr <= ro_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] ro_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (ro_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] ro_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( ro_wr_pd ) + , .we ( ram_we ) + , .wa ( ro_wr_adr ) + , .ra ( (ro_wr_count == 0) ? 3'd4 : {1'b0,ro_rd_adr} ) + , .dout ( ro_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = ro_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + ro_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + ro_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire ro_rd_pvld_p; // data out of fifo is valid +reg ro_rd_pvld_int; // internal copy of ro_rd_pvld +assign ro_rd_pvld = ro_rd_pvld_int; +assign rd_popping = ro_rd_pvld_p && !(ro_rd_pvld_int && !ro_rd_prdy); +reg [2:0] ro_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? ro_rd_count_p : + (ro_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (ro_rd_count_p + 1'd1) : + ro_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign ro_rd_pvld_p = ro_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + ro_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + ro_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] ro_rd_pd; // output data register +wire rd_req_next = (ro_rd_pvld_p || (ro_rd_pvld_int && !ro_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ro_rd_pvld_int <= 1'b0; + end else begin + ro_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + ro_rd_pd <= ro_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + ro_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (ro_wr_pvld && !ro_wr_busy_int) || (ro_wr_busy_int != ro_wr_busy_next)) || (rd_pushing || rd_popping || (ro_rd_pvld_int && ro_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_RDMA_ro_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, ro_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_RDMA_ro_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_RDMA_ro_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [7:0] Di0; +input [1:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8] } +endmodule // vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +//vmw: Memory vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +//vmw: Address-size 2 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_RDMA_ro_fifo_flopram_rwsa_4x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v new file mode 100644 index 0000000..d2c06c0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v @@ -0,0 +1,1328 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_ig.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,eg2ig_done //|< i + ,ig2cq_prdy //|< i + ,pdp2mcif_rd_req_ready //|< i + ,reg2dp_cube_in_channel //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_in_width //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_kernel_stride_width //|< i + ,reg2dp_kernel_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_partial_width_in_first //|< i + ,reg2dp_partial_width_in_last //|< i + ,reg2dp_partial_width_in_mid //|< i + ,reg2dp_split_num //|< i + ,reg2dp_src_base_addr_high //|< i + ,reg2dp_src_base_addr_low //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_src_surface_stride //|< i + ,dp2reg_d0_perf_read_stall //|> o + ,dp2reg_d1_perf_read_stall //|> o + ,ig2cq_pd //|> o + ,ig2cq_pvld //|> o + ,pdp2mcif_rd_req_pd //|> o + ,pdp2mcif_rd_req_valid //|> o + ,reg2dp_surf_stride //|> o + ); +/////////////////////////////////////////////////////////////////////////////// +input [12:0] reg2dp_cube_in_channel; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_in_width; +input [0:0] reg2dp_dma_en; +input [3:0] reg2dp_kernel_stride_width; +input [3:0] reg2dp_kernel_width; +input [0:0] reg2dp_op_en; +input [9:0] reg2dp_partial_width_in_first; +input [9:0] reg2dp_partial_width_in_last; +input [9:0] reg2dp_partial_width_in_mid; +input [7:0] reg2dp_split_num; +input [31:0] reg2dp_src_base_addr_high; +input [31:0] reg2dp_src_base_addr_low; +input [31:0] reg2dp_src_line_stride; +input [0:0] reg2dp_src_ram_type; +input [31:0] reg2dp_src_surface_stride; +output [31:0] dp2reg_d0_perf_read_stall; +output [31:0] dp2reg_d1_perf_read_stall; +output [31:0] reg2dp_surf_stride; +input eg2ig_done; +// +input nvdla_core_clk; +input nvdla_core_rstn; +output pdp2mcif_rd_req_valid; /* data valid */ +input pdp2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] pdp2mcif_rd_req_pd; +output ig2cq_pvld; /* data valid */ +input ig2cq_prdy; /* data return handshake */ +output [17:0] ig2cq_pd; +/////////////////////////////////////////////////////////////////////////////// +reg after_op_done; +reg [63:0] base_addr_esurf; +reg [63:0] base_addr_line; +reg [63:0] base_addr_split; +reg [63:0] base_addr_width; +reg [10:0] count_c; +reg [12:0] count_h; +reg [9:0] count_wg; +reg [31:0] dp2reg_d0_perf_read_stall; +reg [31:0] dp2reg_d1_perf_read_stall; +reg layer_flag; +reg mon_base_addr_line_c; +reg mon_base_addr_split_c; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +reg [31:0] mon_gap_between_layers; +reg mon_layer_end_flg; +reg mon_op_en_dly; +wire [14:0] number_of_byte_in_c; +reg op_process; +reg [31:0] pdp_rd_stall_count; +reg [12:0] req_size; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [13:0] width_stride; +wire [13:0] cfg_channel; +wire [9:0] cfg_fspt_width; +wire [10:0] cfg_fspt_width_use; +wire [9:0] cfg_lspt_width; +wire [10:0] cfg_lspt_width_use; +wire cfg_mode_split; +wire [9:0] cfg_mspt_width; +wire [10:0] cfg_mspt_width_use; +wire [8:0] cfg_split_num; +wire [13:0] cfg_width; +wire cmd_accept; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +wire cv_dma_rd_req_rdy; +wire cv_dma_rd_req_vld; +wire [78:0] cv_int_rd_req_pd; +wire [78:0] cv_int_rd_req_pd_d0; +wire [78:0] cv_int_rd_req_pd_d1; +wire cv_int_rd_req_ready; +wire cv_int_rd_req_ready_d0; +wire cv_int_rd_req_ready_d1; +wire cv_int_rd_req_valid; +wire cv_int_rd_req_valid_d0; +wire cv_int_rd_req_valid_d1; +wire cv_rd_req_rdyi; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_ram_type; +wire dma_rd_req_rdy; +wire dma_rd_req_vld; +wire [63:0] dma_req_addr; +wire [14:0] dma_req_size; +wire ig2eg_align; +wire ig2eg_cube_end; +wire ig2eg_line_end; +wire [12:0] ig2eg_size; +wire ig2eg_split_end; +wire ig2eg_surf_end; +wire is_cube_end; +wire is_fspt; +wire is_last_c; +wire is_last_h; +wire is_line_end; +wire is_lspt; +wire is_split_end; +wire is_surf_end; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire [78:0] mc_int_rd_req_pd_d1; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_ready_d1; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire mc_int_rd_req_valid_d1; +wire mc_rd_req_rdyi; +wire [1:0] mon_number_of_block_in_c; +wire mon_op_en_neg; +wire mon_op_en_pos; +wire mon_overlap; +//: my $k=8; +//: if($k==32) { +//: print " wire [9:0] number_of_block_in_c; \n"; +//: } +//: elsif($k==8) { +//: print " wire [10:0] number_of_block_in_c; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + wire [10:0] number_of_block_in_c; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire op_done; +wire op_load; +wire [3:0] overlap; +wire pdp_rd_stall_count_dec; +wire rd_req_rdyi; +wire [63:0] reg2dp_base_addr; +wire [31:0] reg2dp_esurf_stride; +wire [31:0] reg2dp_line_stride; +wire [63:0] reg2dp_src_base_addr; +wire [8:0] wg_num; +/////////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +// one bubble between operation on two layers to let ARREG to switch to the next configration group +assign op_load = reg2dp_op_en & !op_process; +assign op_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_process <= 1'b0; + end else begin + if (op_done) begin + op_process <= 1'b0; + end else if (after_op_done) begin + op_process <= 1'b0; + end else if (op_load) begin + op_process <= 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + after_op_done <= 1'b0; + end else begin + if (op_done) begin + after_op_done <= 1'b1; + end else if (eg2ig_done) begin + after_op_done <= 1'b0; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !reg2dp_op_en && op_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// Address catenate and offset calc +//============== +assign reg2dp_src_base_addr = {reg2dp_src_base_addr_high,reg2dp_src_base_addr_low}; +//============== +// CFG: +//============== +assign cfg_width = reg2dp_cube_in_width + 1'b1; +assign cfg_channel = reg2dp_cube_in_channel + 1'b1; +assign cfg_fspt_width = reg2dp_partial_width_in_first; +assign cfg_mspt_width = reg2dp_partial_width_in_mid; +assign cfg_lspt_width = reg2dp_partial_width_in_last; +assign cfg_fspt_width_use[10:0] = reg2dp_partial_width_in_first[9:0] + 1'b1; +assign cfg_mspt_width_use[10:0] = reg2dp_partial_width_in_mid[9:0] + 1'b1; +assign cfg_lspt_width_use[10:0] = reg2dp_partial_width_in_last[9:0] + 1'b1; +assign cfg_mode_split = (reg2dp_split_num != 8'd0); +assign cfg_split_num = reg2dp_split_num + 1'b1; +//============== +// CHANNEL Direction +// calculate how many 32x8 blocks in channel direction +//============== +assign number_of_byte_in_c = {1'b0,cfg_channel}; +//: my $k=8; +//: if($k == 32) { +//: print " assign {mon_number_of_block_in_c,number_of_block_in_c[9:0]} = number_of_byte_in_c[14:5] + (|number_of_byte_in_c[4:0]); \n"; +//: } +//: elsif($k == 8) { +//: print " assign {mon_number_of_block_in_c[1:0],number_of_block_in_c[10:0]} = number_of_byte_in_c[14:3] + {11'd0,(|number_of_byte_in_c[2:0])}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign {mon_number_of_block_in_c[1:0],number_of_block_in_c[10:0]} = number_of_byte_in_c[14:3] + {11'd0,(|number_of_byte_in_c[2:0])}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// WIDTH calculation +// Always has FTRAN with size 0~7 +// then will LTRAN with size 0~7 +// then will have MTEAN with fixed size 7 +//============== +always @( + cfg_mode_split + or is_fspt + or cfg_fspt_width_use + or is_lspt + or cfg_lspt_width_use + or cfg_mspt_width_use + or cfg_width + ) begin + if (cfg_mode_split) begin + if (is_fspt) begin + width_stride = {{3{1'b0}}, cfg_fspt_width_use}; + end else if (is_lspt) begin + width_stride = {{3{1'b0}}, cfg_lspt_width_use}; + end else begin + width_stride = {{3{1'b0}}, cfg_mspt_width_use}; + end + end else begin + width_stride = cfg_width[13:0]; + end +end +//============== +// ENDing of line/surf/split/cube +//============== +assign is_line_end = 1'b1;//is_last_w; +assign is_surf_end = is_line_end & is_last_h; +assign is_split_end = is_surf_end & is_last_c; +assign is_cube_end = cfg_mode_split? (is_split_end & is_lspt) : is_split_end; +//============== +// WGROUP Count: width group: number of window after split-w. equal to 1 in non-split-w mode +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_wg <= {10{1'b0}}; + end else begin + if (cmd_accept & is_split_end & cfg_mode_split) begin + if(count_wg == wg_num-1) + count_wg <= 0; + else + count_wg <= count_wg + 1'b1; + end + end +end +assign wg_num = cfg_mode_split ? cfg_split_num : 1; +assign is_fspt = cfg_mode_split & (count_wg==0); +assign is_lspt = cfg_mode_split & (count_wg==wg_num-1); +//============== +// CHANNEL Count: with inital value of total number in C direction, and will count-- when moving in chn direction +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {11{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_split_end) begin + count_c <= 11'd0; + end else if (is_surf_end) begin + count_c <= count_c + 1'b1; + end + end + end +end +assign is_last_c = (count_c==number_of_block_in_c - 1); +//============== +// HEIGHT Count: move to next line after one line is done +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (op_load) begin + count_h <= 13'd0; + end else if (cmd_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1'b1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_cube_in_height); +//========================================== +// DMA Req : ADDR +//========================================== +assign reg2dp_base_addr = reg2dp_src_base_addr; +assign reg2dp_line_stride = reg2dp_src_line_stride; +assign reg2dp_surf_stride = reg2dp_src_surface_stride; +assign reg2dp_esurf_stride = reg2dp_src_surface_stride; +//============== +// DMA Req : ADDR : Prepration +// DMA Req: go through the CUBE: W8->C->H +//============== +// ELEMENT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_width <= {64{1'b0}}; + {mon_base_addr_width_c,base_addr_width} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_width <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,3'd0} + {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,3'd0} - {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else if (is_surf_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_esurf + reg2dp_esurf_stride; + end else if (is_line_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_line + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_width_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {64{1'b0}}; + {mon_base_addr_line_c,base_addr_line} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_line <= reg2dp_base_addr; + end else if (cmd_accept) begin + if(is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,3'd0} + {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,3'd0} - {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print" {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else if(is_surf_end) + {mon_base_addr_line_c,base_addr_line} <= base_addr_esurf + reg2dp_esurf_stride; + else if(is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_esurf <= {64{1'b0}}; + {mon_base_addr_surf_c,base_addr_esurf} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_esurf <= reg2dp_base_addr; + end else if (cmd_accept) begin + if(is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,3'd0} + {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,3'd0} - {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end else if (is_surf_end) + {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_esurf + reg2dp_esurf_stride; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SPLIT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_split <= {64{1'b0}}; + {mon_base_addr_split_c,base_addr_split} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_split <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,3'd0} + {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print "{mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +{mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,3'd0} - {overlap[3:0],3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,3'd0}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_split_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dma_req_addr = base_addr_width; +//============== +// DMA Req : SIZE : Generation +//============== +assign {mon_overlap,overlap[3:0]} = (reg2dp_kernel_width < reg2dp_kernel_stride_width) ? (reg2dp_kernel_stride_width[3:0] - {1'b0,reg2dp_kernel_width[2:0]}) : ({1'b0,reg2dp_kernel_width[2:0]} - reg2dp_kernel_stride_width[3:0]); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-CORE: should not overflow") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, mon_overlap); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + cfg_mode_split + or is_fspt + or cfg_fspt_width + or is_lspt + or reg2dp_kernel_width + or reg2dp_kernel_stride_width + or cfg_lspt_width + or overlap + or cfg_mspt_width + or reg2dp_cube_in_width + ) begin + if(cfg_mode_split) begin + if (is_fspt) + req_size = {{3{1'b0}}, cfg_fspt_width}; + else if (is_lspt) begin + if(reg2dp_kernel_width < reg2dp_kernel_stride_width) + req_size = {{3{1'b0}}, cfg_lspt_width} - {8'd0,overlap[3:0]}; + else + req_size = {{3{1'b0}}, cfg_lspt_width} + {8'd0,overlap[3:0]}; + end else begin + if(reg2dp_kernel_width < reg2dp_kernel_stride_width) + req_size = {{3{1'b0}}, cfg_mspt_width} - {8'd0,overlap[3:0]}; + else + req_size = {{3{1'b0}}, cfg_mspt_width} + {8'd0,overlap[3:0]}; + end + end else + req_size = reg2dp_cube_in_width[12:0];//cfg_width; +end +assign dma_req_size = {{2{1'b0}}, req_size}; +//============== +// Context Qeueu : Beats +//============== +//{s,e}-> 11 10 01 00 +// -------------- +//size | +// 0: | x 0 0 x +// 1: | 1 x x 0 +// 2: | x 1 1 x +// 3: | 2 x x 1 +// 4: | x 2 2 x +// 5: | 3 x x 2 +// 6: | x 3 3 x +// 7: | 4 x x 3 +// 64.size = ((32.size>>1) + &mask) +// 64.cnt = 64.size + 1 +assign ig2eg_size = dma_req_size[12:0]; +assign ig2eg_align = 1'b0; // can be elimnated after mcif update for re-alignment +assign ig2eg_line_end = is_line_end; +assign ig2eg_surf_end = is_surf_end; +assign ig2eg_split_end = is_split_end; +assign ig2eg_cube_end = is_cube_end; +// PKT_PACK_WIRE( pdp_rdma_ig2eg , ig2eg_ , ig2cq_pd ) +assign ig2cq_pd[12:0] = ig2eg_size[12:0]; +assign ig2cq_pd[13] = ig2eg_align ; +assign ig2cq_pd[14] = ig2eg_line_end ; +assign ig2cq_pd[15] = ig2eg_surf_end ; +assign ig2cq_pd[16] = ig2eg_split_end ; +assign ig2cq_pd[17] = ig2eg_cube_end ; +assign ig2cq_pvld = op_process & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (ig2cq_pvld & ig2cq_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = op_process & ig2cq_prdy; +// PayLoad +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_req_size[14:0]; +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// reading stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = cmd_accept & is_cube_end; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_rd_req_vld & (~dma_rd_req_rdy)); + assign pdp_rd_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or pdp_rd_stall_count_dec + ) begin + stl_adv = cnt_inc ^ pdp_rd_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or pdp_rd_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !pdp_rd_stall_count_dec)? stl_cnt_inc : (!cnt_inc && pdp_rd_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + pdp_rd_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; +// VCS coverage off + end else if ((cnt_clr) == 1'b0) begin + end else begin + layer_flag <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_read_stall <= pdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & (~layer_flag)) == 1'b0) begin + end else begin + dp2reg_d0_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & (~layer_flag)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_read_stall <= pdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & layer_flag ) == 1'b0) begin + end else begin + dp2reg_d1_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & layer_flag ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.mcif_rd_req_pd (pdp2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (pdp2mcif_rd_req_valid) + ,.mcif_rd_req_ready (pdp2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +////============== +////OBS signals +////============== +//assign obs_bus_pdp_rdma_proc_en = op_process; +//============== +//function point +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property PDP_RDMA_ig__dma_IF_reading_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (((dma_rd_req_vld)) && nvdla_core_rstn) |-> ((~dma_rd_req_rdy & reg2dp_op_en)); + endproperty +// Cover 0 : "(~dma_rd_req_rdy & reg2dp_op_en)" + FUNCPOINT_PDP_RDMA_ig__dma_IF_reading_stall__0_COV : cover property (PDP_RDMA_ig__dma_IF_reading_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__surf_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_surf_end & (~dma_rd_req_rdy); + endproperty +// Cover 1 : "is_surf_end & (~dma_rd_req_rdy)" + FUNCPOINT_PDP_RDMA_ig__surf_end_stall__1_COV : cover property (PDP_RDMA_ig__surf_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__split_end_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_split_end & (~dma_rd_req_rdy); + endproperty +// Cover 2 : "is_split_end & (~dma_rd_req_rdy)" + FUNCPOINT_PDP_RDMA_ig__split_end_stall__2_COV : cover property (PDP_RDMA_ig__split_end_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__cube_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_cube_end & (~dma_rd_req_rdy); + endproperty +// Cover 3 : "is_cube_end & (~dma_rd_req_rdy)" + FUNCPOINT_PDP_RDMA_ig__cube_end_stall__3_COV : cover property (PDP_RDMA_ig__cube_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__ig2eg_stall__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((ig2cq_pvld) && nvdla_core_rstn) |-> ((~ig2cq_prdy & reg2dp_op_en)); + endproperty +// Cover 4 : "(~ig2cq_prdy & reg2dp_op_en)" + FUNCPOINT_PDP_RDMA_ig__ig2eg_stall__4_COV : cover property (PDP_RDMA_ig__ig2eg_stall__4_cov); + `endif +`endif +//VCS coverage on +//two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_two_continuous_layer__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 5 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_PDP_RDMA_two_continuous_layer__5_COV : cover property (PDP_RDMA_two_continuous_layer__5_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +//============== +// Context Queue Interface +//============== +endmodule // NV_NVDLA_PDP_RDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v.vcp new file mode 100644 index 0000000..130ab76 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v.vcp @@ -0,0 +1,1256 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_ig.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_ig ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,eg2ig_done //|< i + ,ig2cq_prdy //|< i + ,pdp2mcif_rd_req_ready //|< i + ,reg2dp_cube_in_channel //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_in_width //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_kernel_stride_width //|< i + ,reg2dp_kernel_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_partial_width_in_first //|< i + ,reg2dp_partial_width_in_last //|< i + ,reg2dp_partial_width_in_mid //|< i + ,reg2dp_split_num //|< i + ,reg2dp_src_base_addr_high //|< i + ,reg2dp_src_base_addr_low //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_src_surface_stride //|< i + ,dp2reg_d0_perf_read_stall //|> o + ,dp2reg_d1_perf_read_stall //|> o + ,ig2cq_pd //|> o + ,ig2cq_pvld //|> o + ,pdp2mcif_rd_req_pd //|> o + ,pdp2mcif_rd_req_valid //|> o + ,reg2dp_surf_stride //|> o + ); +/////////////////////////////////////////////////////////////////////////////// +input [12:0] reg2dp_cube_in_channel; +input [12:0] reg2dp_cube_in_height; +input [12:0] reg2dp_cube_in_width; +input [0:0] reg2dp_dma_en; +input [3:0] reg2dp_kernel_stride_width; +input [3:0] reg2dp_kernel_width; +input [0:0] reg2dp_op_en; +input [9:0] reg2dp_partial_width_in_first; +input [9:0] reg2dp_partial_width_in_last; +input [9:0] reg2dp_partial_width_in_mid; +input [7:0] reg2dp_split_num; +input [31:0] reg2dp_src_base_addr_high; +input [31:0] reg2dp_src_base_addr_low; +input [31:0] reg2dp_src_line_stride; +input [0:0] reg2dp_src_ram_type; +input [31:0] reg2dp_src_surface_stride; +output [31:0] dp2reg_d0_perf_read_stall; +output [31:0] dp2reg_d1_perf_read_stall; +output [31:0] reg2dp_surf_stride; +input eg2ig_done; +// +input nvdla_core_clk; +input nvdla_core_rstn; +output pdp2mcif_rd_req_valid; /* data valid */ +input pdp2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] pdp2mcif_rd_req_pd; +output ig2cq_pvld; /* data valid */ +input ig2cq_prdy; /* data return handshake */ +output [17:0] ig2cq_pd; +/////////////////////////////////////////////////////////////////////////////// +reg after_op_done; +reg [63:0] base_addr_esurf; +reg [63:0] base_addr_line; +reg [63:0] base_addr_split; +reg [63:0] base_addr_width; +reg [10:0] count_c; +reg [12:0] count_h; +reg [9:0] count_wg; +reg [31:0] dp2reg_d0_perf_read_stall; +reg [31:0] dp2reg_d1_perf_read_stall; +reg layer_flag; +reg mon_base_addr_line_c; +reg mon_base_addr_split_c; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +reg [31:0] mon_gap_between_layers; +reg mon_layer_end_flg; +reg mon_op_en_dly; +wire [14:0] number_of_byte_in_c; +reg op_process; +reg [31:0] pdp_rd_stall_count; +reg [12:0] req_size; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [13:0] width_stride; +wire [13:0] cfg_channel; +wire [9:0] cfg_fspt_width; +wire [10:0] cfg_fspt_width_use; +wire [9:0] cfg_lspt_width; +wire [10:0] cfg_lspt_width_use; +wire cfg_mode_split; +wire [9:0] cfg_mspt_width; +wire [10:0] cfg_mspt_width_use; +wire [8:0] cfg_split_num; +wire [13:0] cfg_width; +wire cmd_accept; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +wire cv_dma_rd_req_rdy; +wire cv_dma_rd_req_vld; +wire [78:0] cv_int_rd_req_pd; +wire [78:0] cv_int_rd_req_pd_d0; +wire [78:0] cv_int_rd_req_pd_d1; +wire cv_int_rd_req_ready; +wire cv_int_rd_req_ready_d0; +wire cv_int_rd_req_ready_d1; +wire cv_int_rd_req_valid; +wire cv_int_rd_req_valid_d0; +wire cv_int_rd_req_valid_d1; +wire cv_rd_req_rdyi; +wire [32 +14:0] dma_rd_req_pd; +wire dma_rd_req_ram_type; +wire dma_rd_req_rdy; +wire dma_rd_req_vld; +wire [63:0] dma_req_addr; +wire [14:0] dma_req_size; +wire ig2eg_align; +wire ig2eg_cube_end; +wire ig2eg_line_end; +wire [12:0] ig2eg_size; +wire ig2eg_split_end; +wire ig2eg_surf_end; +wire is_cube_end; +wire is_fspt; +wire is_last_c; +wire is_last_h; +wire is_line_end; +wire is_lspt; +wire is_split_end; +wire is_surf_end; +wire mc_dma_rd_req_rdy; +wire mc_dma_rd_req_vld; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire [78:0] mc_int_rd_req_pd_d1; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_ready_d1; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire mc_int_rd_req_valid_d1; +wire mc_rd_req_rdyi; +wire [1:0] mon_number_of_block_in_c; +wire mon_op_en_neg; +wire mon_op_en_pos; +wire mon_overlap; +//: my $k=8; +//: if($k==32) { +//: print " wire [9:0] number_of_block_in_c; \n"; +//: } +//: elsif($k==8) { +//: print " wire [10:0] number_of_block_in_c; \n"; +//: } +wire op_done; +wire op_load; +wire [3:0] overlap; +wire pdp_rd_stall_count_dec; +wire rd_req_rdyi; +wire [63:0] reg2dp_base_addr; +wire [31:0] reg2dp_esurf_stride; +wire [31:0] reg2dp_line_stride; +wire [63:0] reg2dp_src_base_addr; +wire [8:0] wg_num; +/////////////////////////////////////////////////////////////////////////////// +//============== +// Work Processing +//============== +// one bubble between operation on two layers to let ARREG to switch to the next configration group +assign op_load = reg2dp_op_en & !op_process; +assign op_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_process <= 1'b0; + end else begin + if (op_done) begin + op_process <= 1'b0; + end else if (after_op_done) begin + op_process <= 1'b0; + end else if (op_load) begin + op_process <= 1'b1; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + after_op_done <= 1'b0; + end else begin + if (op_done) begin + after_op_done <= 1'b1; + end else if (eg2ig_done) begin + after_op_done <= 1'b0; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !reg2dp_op_en && op_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// Address catenate and offset calc +//============== +assign reg2dp_src_base_addr = {reg2dp_src_base_addr_high,reg2dp_src_base_addr_low}; +//============== +// CFG: +//============== +assign cfg_width = reg2dp_cube_in_width + 1'b1; +assign cfg_channel = reg2dp_cube_in_channel + 1'b1; +assign cfg_fspt_width = reg2dp_partial_width_in_first; +assign cfg_mspt_width = reg2dp_partial_width_in_mid; +assign cfg_lspt_width = reg2dp_partial_width_in_last; +assign cfg_fspt_width_use[10:0] = reg2dp_partial_width_in_first[9:0] + 1'b1; +assign cfg_mspt_width_use[10:0] = reg2dp_partial_width_in_mid[9:0] + 1'b1; +assign cfg_lspt_width_use[10:0] = reg2dp_partial_width_in_last[9:0] + 1'b1; +assign cfg_mode_split = (reg2dp_split_num != 8'd0); +assign cfg_split_num = reg2dp_split_num + 1'b1; +//============== +// CHANNEL Direction +// calculate how many 32x8 blocks in channel direction +//============== +assign number_of_byte_in_c = {1'b0,cfg_channel}; +//: my $k=8; +//: if($k == 32) { +//: print " assign {mon_number_of_block_in_c,number_of_block_in_c[9:0]} = number_of_byte_in_c[14:5] + (|number_of_byte_in_c[4:0]); \n"; +//: } +//: elsif($k == 8) { +//: print " assign {mon_number_of_block_in_c[1:0],number_of_block_in_c[10:0]} = number_of_byte_in_c[14:3] + {11'd0,(|number_of_byte_in_c[2:0])}; \n"; +//: } +//============== +// WIDTH calculation +// Always has FTRAN with size 0~7 +// then will LTRAN with size 0~7 +// then will have MTEAN with fixed size 7 +//============== +always @( + cfg_mode_split + or is_fspt + or cfg_fspt_width_use + or is_lspt + or cfg_lspt_width_use + or cfg_mspt_width_use + or cfg_width + ) begin + if (cfg_mode_split) begin + if (is_fspt) begin + width_stride = {{3{1'b0}}, cfg_fspt_width_use}; + end else if (is_lspt) begin + width_stride = {{3{1'b0}}, cfg_lspt_width_use}; + end else begin + width_stride = {{3{1'b0}}, cfg_mspt_width_use}; + end + end else begin + width_stride = cfg_width[13:0]; + end +end +//============== +// ENDing of line/surf/split/cube +//============== +assign is_line_end = 1'b1;//is_last_w; +assign is_surf_end = is_line_end & is_last_h; +assign is_split_end = is_surf_end & is_last_c; +assign is_cube_end = cfg_mode_split? (is_split_end & is_lspt) : is_split_end; +//============== +// WGROUP Count: width group: number of window after split-w. equal to 1 in non-split-w mode +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_wg <= {10{1'b0}}; + end else begin + if (cmd_accept & is_split_end & cfg_mode_split) begin + if(count_wg == wg_num-1) + count_wg <= 0; + else + count_wg <= count_wg + 1'b1; + end + end +end +assign wg_num = cfg_mode_split ? cfg_split_num : 1; +assign is_fspt = cfg_mode_split & (count_wg==0); +assign is_lspt = cfg_mode_split & (count_wg==wg_num-1); +//============== +// CHANNEL Count: with inital value of total number in C direction, and will count-- when moving in chn direction +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {11{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_split_end) begin + count_c <= 11'd0; + end else if (is_surf_end) begin + count_c <= count_c + 1'b1; + end + end + end +end +assign is_last_c = (count_c==number_of_block_in_c - 1); +//============== +// HEIGHT Count: move to next line after one line is done +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (op_load) begin + count_h <= 13'd0; + end else if (cmd_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1'b1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_cube_in_height); +//========================================== +// DMA Req : ADDR +//========================================== +assign reg2dp_base_addr = reg2dp_src_base_addr; +assign reg2dp_line_stride = reg2dp_src_line_stride; +assign reg2dp_surf_stride = reg2dp_src_surface_stride; +assign reg2dp_esurf_stride = reg2dp_src_surface_stride; +//============== +// DMA Req : ADDR : Prepration +// DMA Req: go through the CUBE: W8->C->H +//============== +// ELEMENT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_width <= {64{1'b0}}; + {mon_base_addr_width_c,base_addr_width} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_width <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_width_c,base_addr_width} <= base_addr_split + {width_stride,${m}'d0}; \n"; + end + end else if (is_surf_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_esurf + reg2dp_esurf_stride; + end else if (is_line_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_line + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_width_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {64{1'b0}}; + {mon_base_addr_line_c,base_addr_line} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_line <= reg2dp_base_addr; + end else if (cmd_accept) begin + if(is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print" {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_line_c,base_addr_line} <= base_addr_split + {width_stride,${m}'d0}; \n"; + end + end else if(is_surf_end) + {mon_base_addr_line_c,base_addr_line} <= base_addr_esurf + reg2dp_esurf_stride; + else if(is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + reg2dp_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_esurf <= {64{1'b0}}; + {mon_base_addr_surf_c,base_addr_esurf} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_esurf <= reg2dp_base_addr; + end else if (cmd_accept) begin + if(is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_split + {width_stride,${m}'d0}; \n"; + end + end else if (is_surf_end) + {mon_base_addr_surf_c,base_addr_esurf} <= base_addr_esurf + reg2dp_esurf_stride; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SPLIT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_split <= {64{1'b0}}; + {mon_base_addr_split_c,base_addr_split} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_split <= reg2dp_base_addr; + end else if (cmd_accept) begin + if (is_split_end & (~is_cube_end)) begin + if(is_fspt) begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0} + {overlap[3:0],${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print "{mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0} - {overlap[3:0],${m}'d0}; \n"; + end else begin + if({1'b0,reg2dp_kernel_width[2:0]} < reg2dp_kernel_stride_width) +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0}; \n"; + else +//: my $k=8; +//: my $m = int(log($k)/log(2)); +//: print " {mon_base_addr_split_c,base_addr_split} <= base_addr_split + {width_stride,${m}'d0}; \n"; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_RDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_split_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dma_req_addr = base_addr_width; +//============== +// DMA Req : SIZE : Generation +//============== +assign {mon_overlap,overlap[3:0]} = (reg2dp_kernel_width < reg2dp_kernel_stride_width) ? (reg2dp_kernel_stride_width[3:0] - {1'b0,reg2dp_kernel_width[2:0]}) : ({1'b0,reg2dp_kernel_width[2:0]} - reg2dp_kernel_stride_width[3:0]); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-CORE: should not overflow") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, mon_overlap); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + cfg_mode_split + or is_fspt + or cfg_fspt_width + or is_lspt + or reg2dp_kernel_width + or reg2dp_kernel_stride_width + or cfg_lspt_width + or overlap + or cfg_mspt_width + or reg2dp_cube_in_width + ) begin + if(cfg_mode_split) begin + if (is_fspt) + req_size = {{3{1'b0}}, cfg_fspt_width}; + else if (is_lspt) begin + if(reg2dp_kernel_width < reg2dp_kernel_stride_width) + req_size = {{3{1'b0}}, cfg_lspt_width} - {8'd0,overlap[3:0]}; + else + req_size = {{3{1'b0}}, cfg_lspt_width} + {8'd0,overlap[3:0]}; + end else begin + if(reg2dp_kernel_width < reg2dp_kernel_stride_width) + req_size = {{3{1'b0}}, cfg_mspt_width} - {8'd0,overlap[3:0]}; + else + req_size = {{3{1'b0}}, cfg_mspt_width} + {8'd0,overlap[3:0]}; + end + end else + req_size = reg2dp_cube_in_width[12:0];//cfg_width; +end +assign dma_req_size = {{2{1'b0}}, req_size}; +//============== +// Context Qeueu : Beats +//============== +//{s,e}-> 11 10 01 00 +// -------------- +//size | +// 0: | x 0 0 x +// 1: | 1 x x 0 +// 2: | x 1 1 x +// 3: | 2 x x 1 +// 4: | x 2 2 x +// 5: | 3 x x 2 +// 6: | x 3 3 x +// 7: | 4 x x 3 +// 64.size = ((32.size>>1) + &mask) +// 64.cnt = 64.size + 1 +assign ig2eg_size = dma_req_size[12:0]; +assign ig2eg_align = 1'b0; // can be elimnated after mcif update for re-alignment +assign ig2eg_line_end = is_line_end; +assign ig2eg_surf_end = is_surf_end; +assign ig2eg_split_end = is_split_end; +assign ig2eg_cube_end = is_cube_end; +// PKT_PACK_WIRE( pdp_rdma_ig2eg , ig2eg_ , ig2cq_pd ) +assign ig2cq_pd[12:0] = ig2eg_size[12:0]; +assign ig2cq_pd[13] = ig2eg_align ; +assign ig2cq_pd[14] = ig2eg_line_end ; +assign ig2cq_pd[15] = ig2eg_surf_end ; +assign ig2cq_pd[16] = ig2eg_split_end ; +assign ig2cq_pd[17] = ig2eg_cube_end ; +assign ig2cq_pvld = op_process & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (ig2cq_pvld & ig2cq_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = op_process & ig2cq_prdy; +// PayLoad +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[32 +14:32] = dma_req_size[14:0]; +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// reading stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = cmd_accept & is_cube_end; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_rd_req_vld & (~dma_rd_req_rdy)); + assign pdp_rd_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or pdp_rd_stall_count_dec + ) begin + stl_adv = cnt_inc ^ pdp_rd_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or pdp_rd_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !pdp_rd_stall_count_dec)? stl_cnt_inc : (!cnt_inc && pdp_rd_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + pdp_rd_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; +// VCS coverage off + end else if ((cnt_clr) == 1'b0) begin + end else begin + layer_flag <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_read_stall <= pdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & (~layer_flag)) == 1'b0) begin + end else begin + dp2reg_d0_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & (~layer_flag)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_read_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_read_stall <= pdp_rd_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & layer_flag ) == 1'b0) begin + end else begin + dp2reg_d1_perf_read_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & layer_flag ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +NV_NVDLA_DMAIF_rdreq NV_NVDLA_PDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.mcif_rd_req_pd (pdp2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (pdp2mcif_rd_req_valid) + ,.mcif_rd_req_ready (pdp2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +////============== +////OBS signals +////============== +//assign obs_bus_pdp_rdma_proc_en = op_process; +//============== +//function point +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property PDP_RDMA_ig__dma_IF_reading_stall__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (((dma_rd_req_vld)) && nvdla_core_rstn) |-> ((~dma_rd_req_rdy & reg2dp_op_en)); + endproperty +// Cover 0 : "(~dma_rd_req_rdy & reg2dp_op_en)" + FUNCPOINT_PDP_RDMA_ig__dma_IF_reading_stall__0_COV : cover property (PDP_RDMA_ig__dma_IF_reading_stall__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__surf_end_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_surf_end & (~dma_rd_req_rdy); + endproperty +// Cover 1 : "is_surf_end & (~dma_rd_req_rdy)" + FUNCPOINT_PDP_RDMA_ig__surf_end_stall__1_COV : cover property (PDP_RDMA_ig__surf_end_stall__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__split_end_stall__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_split_end & (~dma_rd_req_rdy); + endproperty +// Cover 2 : "is_split_end & (~dma_rd_req_rdy)" + FUNCPOINT_PDP_RDMA_ig__split_end_stall__2_COV : cover property (PDP_RDMA_ig__split_end_stall__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__cube_end_stall__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + is_cube_end & (~dma_rd_req_rdy); + endproperty +// Cover 3 : "is_cube_end & (~dma_rd_req_rdy)" + FUNCPOINT_PDP_RDMA_ig__cube_end_stall__3_COV : cover property (PDP_RDMA_ig__cube_end_stall__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_ig__ig2eg_stall__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((ig2cq_pvld) && nvdla_core_rstn) |-> ((~ig2cq_prdy & reg2dp_op_en)); + endproperty +// Cover 4 : "(~ig2cq_prdy & reg2dp_op_en)" + FUNCPOINT_PDP_RDMA_ig__ig2eg_stall__4_COV : cover property (PDP_RDMA_ig__ig2eg_stall__4_cov); + `endif +`endif +//VCS coverage on +//two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA_two_continuous_layer__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 5 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_PDP_RDMA_two_continuous_layer__5_COV : cover property (PDP_RDMA_two_continuous_layer__5_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +//============== +// Context Queue Interface +//============== +endmodule // NV_NVDLA_PDP_RDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v new file mode 100644 index 0000000..0f93a2c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v @@ -0,0 +1,808 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2pdp_rdma_req_pd //|< i + ,csb2pdp_rdma_req_pvld //|< i + ,dp2reg_d0_perf_read_stall //|< i + ,dp2reg_d1_perf_read_stall //|< i + ,dp2reg_done //|< i + ,csb2pdp_rdma_req_prdy //|> o + ,pdp_rdma2csb_resp_pd //|> o + ,pdp_rdma2csb_resp_valid //|> o + ,reg2dp_cube_in_channel //|> o + ,reg2dp_cube_in_height //|> o + ,reg2dp_cube_in_width //|> o + ,reg2dp_cya //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_input_data //|> o + ,reg2dp_kernel_stride_width //|> o + ,reg2dp_kernel_width //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_width //|> o + ,reg2dp_partial_width_in_first //|> o + ,reg2dp_partial_width_in_last //|> o + ,reg2dp_partial_width_in_mid //|> o + ,reg2dp_split_num //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_ram_type //|> o + ,reg2dp_src_surface_stride //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2pdp_rdma_req_pd; +input csb2pdp_rdma_req_pvld; +input [31:0] dp2reg_d0_perf_read_stall; +input [31:0] dp2reg_d1_perf_read_stall; +input dp2reg_done; +output csb2pdp_rdma_req_prdy; +output [33:0] pdp_rdma2csb_resp_pd; +output pdp_rdma2csb_resp_valid; +output [12:0] reg2dp_cube_in_channel; +output [12:0] reg2dp_cube_in_height; +output [12:0] reg2dp_cube_in_width; +output [31:0] reg2dp_cya; +output reg2dp_dma_en; +output reg2dp_flying_mode; +output [1:0] reg2dp_input_data; +output [3:0] reg2dp_kernel_stride_width; +output [3:0] reg2dp_kernel_width; +output reg2dp_op_en; +output [3:0] reg2dp_pad_width; +output [9:0] reg2dp_partial_width_in_first; +output [9:0] reg2dp_partial_width_in_last; +output [9:0] reg2dp_partial_width_in_mid; +output [7:0] reg2dp_split_num; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output reg2dp_src_ram_type; +output [31:0] reg2dp_src_surface_stride; +output slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [12:0] reg2dp_d0_cube_in_channel; +wire [12:0] reg2dp_d0_cube_in_height; +wire [12:0] reg2dp_d0_cube_in_width; +wire [31:0] reg2dp_d0_cya; +wire reg2dp_d0_dma_en; +wire reg2dp_d0_flying_mode; +wire [1:0] reg2dp_d0_input_data; +wire [3:0] reg2dp_d0_kernel_stride_width; +wire [3:0] reg2dp_d0_kernel_width; +wire reg2dp_d0_op_en_trigger; +wire [3:0] reg2dp_d0_pad_width; +wire [9:0] reg2dp_d0_partial_width_in_first; +wire [9:0] reg2dp_d0_partial_width_in_last; +wire [9:0] reg2dp_d0_partial_width_in_mid; +wire [7:0] reg2dp_d0_split_num; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire reg2dp_d0_src_ram_type; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d1_cube_in_channel; +wire [12:0] reg2dp_d1_cube_in_height; +wire [12:0] reg2dp_d1_cube_in_width; +wire [31:0] reg2dp_d1_cya; +wire reg2dp_d1_dma_en; +wire reg2dp_d1_flying_mode; +wire [1:0] reg2dp_d1_input_data; +wire [3:0] reg2dp_d1_kernel_stride_width; +wire [3:0] reg2dp_d1_kernel_width; +wire reg2dp_d1_op_en_trigger; +wire [3:0] reg2dp_d1_pad_width; +wire [9:0] reg2dp_d1_partial_width_in_first; +wire [9:0] reg2dp_d1_partial_width_in_last; +wire [9:0] reg2dp_d1_partial_width_in_mid; +wire [7:0] reg2dp_d1_split_num; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire reg2dp_d1_src_ram_type; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire slcg_op_en_d0; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [33:0] pdp_rdma2csb_resp_pd; +reg pdp_rdma2csb_resp_valid; +reg [12:0] reg2dp_cube_in_channel; +reg [12:0] reg2dp_cube_in_height; +reg [12:0] reg2dp_cube_in_width; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_dma_en; +reg reg2dp_flying_mode; +reg [1:0] reg2dp_input_data; +reg [3:0] reg2dp_kernel_stride_width; +reg [3:0] reg2dp_kernel_width; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [3:0] reg2dp_pad_width; +reg [9:0] reg2dp_partial_width_in_first; +reg [9:0] reg2dp_partial_width_in_last; +reg [9:0] reg2dp_partial_width_in_mid; +reg [7:0] reg2dp_split_num; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg reg2dp_src_ram_type; +reg [31:0] reg2dp_src_surface_stride; +reg [62:0] req_pd; +reg req_pvld; +reg slcg_op_en_d1; +reg slcg_op_en_d2; +reg slcg_op_en_d3; +//Instance single register group +NV_NVDLA_PDP_RDMA_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_PDP_RDMA_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d0_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d0_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d0_cube_in_width[12:0]) //|> w + ,.input_data (reg2dp_d0_input_data[1:0]) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.split_num (reg2dp_d0_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d0_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d0_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d0_partial_width_in_mid[9:0]) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.kernel_stride_width (reg2dp_d0_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d0_kernel_width[3:0]) //|> w + ,.pad_width (reg2dp_d0_pad_width[3:0]) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_ram_type (reg2dp_d0_src_ram_type) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|< i + ); +NV_NVDLA_PDP_RDMA_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d1_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d1_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d1_cube_in_width[12:0]) //|> w + ,.input_data (reg2dp_d1_input_data[1:0]) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.split_num (reg2dp_d1_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d1_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d1_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d1_partial_width_in_mid[9:0]) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.kernel_stride_width (reg2dp_d1_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d1_kernel_width[3:0]) //|> w + ,.pad_width (reg2dp_d1_pad_width[3:0]) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_ram_type (reg2dp_d1_src_ram_type) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {1{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= 1'b0; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= 1'b0; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= 1'b0; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hc008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hc008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hc008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2pdp_rdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2pdp_rdma_req_pvld) == 1'b1) begin + req_pd <= csb2pdp_rdma_req_pd; +// VCS coverage off + end else if ((csb2pdp_rdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2pdp_rdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2pdp_rdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + pdp_rdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + pdp_rdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma2csb_resp_valid <= 1'b0; + end else begin + pdp_rdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_channel + or reg2dp_d0_cube_in_channel + ) begin + reg2dp_cube_in_channel = dp2reg_consumer ? reg2dp_d1_cube_in_channel : reg2dp_d0_cube_in_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_height + or reg2dp_d0_cube_in_height + ) begin + reg2dp_cube_in_height = dp2reg_consumer ? reg2dp_d1_cube_in_height : reg2dp_d0_cube_in_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_width + or reg2dp_d0_cube_in_width + ) begin + reg2dp_cube_in_width = dp2reg_consumer ? reg2dp_d1_cube_in_width : reg2dp_d0_cube_in_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data + or reg2dp_d0_input_data + ) begin + reg2dp_input_data = dp2reg_consumer ? reg2dp_d1_input_data : reg2dp_d0_input_data; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_split_num + or reg2dp_d0_split_num + ) begin + reg2dp_split_num = dp2reg_consumer ? reg2dp_d1_split_num : reg2dp_d0_split_num; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_first + or reg2dp_d0_partial_width_in_first + ) begin + reg2dp_partial_width_in_first = dp2reg_consumer ? reg2dp_d1_partial_width_in_first : reg2dp_d0_partial_width_in_first; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_last + or reg2dp_d0_partial_width_in_last + ) begin + reg2dp_partial_width_in_last = dp2reg_consumer ? reg2dp_d1_partial_width_in_last : reg2dp_d0_partial_width_in_last; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_mid + or reg2dp_d0_partial_width_in_mid + ) begin + reg2dp_partial_width_in_mid = dp2reg_consumer ? reg2dp_d1_partial_width_in_mid : reg2dp_d0_partial_width_in_mid; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_stride_width + or reg2dp_d0_kernel_stride_width + ) begin + reg2dp_kernel_stride_width = dp2reg_consumer ? reg2dp_d1_kernel_stride_width : reg2dp_d0_kernel_stride_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_width + or reg2dp_d0_kernel_width + ) begin + reg2dp_kernel_width = dp2reg_consumer ? reg2dp_d1_kernel_width : reg2dp_d0_kernel_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_width + or reg2dp_d0_pad_width + ) begin + reg2dp_pad_width = dp2reg_consumer ? reg2dp_d1_pad_width : reg2dp_d0_pad_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_ram_type + or reg2dp_d0_src_ram_type + ) begin + reg2dp_src_ram_type = dp2reg_consumer ? reg2dp_d1_src_ram_type : reg2dp_d0_src_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_PDP_RDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v.vcp new file mode 100644 index 0000000..0f93a2c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v.vcp @@ -0,0 +1,808 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_RDMA_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_RDMA_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2pdp_rdma_req_pd //|< i + ,csb2pdp_rdma_req_pvld //|< i + ,dp2reg_d0_perf_read_stall //|< i + ,dp2reg_d1_perf_read_stall //|< i + ,dp2reg_done //|< i + ,csb2pdp_rdma_req_prdy //|> o + ,pdp_rdma2csb_resp_pd //|> o + ,pdp_rdma2csb_resp_valid //|> o + ,reg2dp_cube_in_channel //|> o + ,reg2dp_cube_in_height //|> o + ,reg2dp_cube_in_width //|> o + ,reg2dp_cya //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_input_data //|> o + ,reg2dp_kernel_stride_width //|> o + ,reg2dp_kernel_width //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_width //|> o + ,reg2dp_partial_width_in_first //|> o + ,reg2dp_partial_width_in_last //|> o + ,reg2dp_partial_width_in_mid //|> o + ,reg2dp_split_num //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_ram_type //|> o + ,reg2dp_src_surface_stride //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2pdp_rdma_req_pd; +input csb2pdp_rdma_req_pvld; +input [31:0] dp2reg_d0_perf_read_stall; +input [31:0] dp2reg_d1_perf_read_stall; +input dp2reg_done; +output csb2pdp_rdma_req_prdy; +output [33:0] pdp_rdma2csb_resp_pd; +output pdp_rdma2csb_resp_valid; +output [12:0] reg2dp_cube_in_channel; +output [12:0] reg2dp_cube_in_height; +output [12:0] reg2dp_cube_in_width; +output [31:0] reg2dp_cya; +output reg2dp_dma_en; +output reg2dp_flying_mode; +output [1:0] reg2dp_input_data; +output [3:0] reg2dp_kernel_stride_width; +output [3:0] reg2dp_kernel_width; +output reg2dp_op_en; +output [3:0] reg2dp_pad_width; +output [9:0] reg2dp_partial_width_in_first; +output [9:0] reg2dp_partial_width_in_last; +output [9:0] reg2dp_partial_width_in_mid; +output [7:0] reg2dp_split_num; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output reg2dp_src_ram_type; +output [31:0] reg2dp_src_surface_stride; +output slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [12:0] reg2dp_d0_cube_in_channel; +wire [12:0] reg2dp_d0_cube_in_height; +wire [12:0] reg2dp_d0_cube_in_width; +wire [31:0] reg2dp_d0_cya; +wire reg2dp_d0_dma_en; +wire reg2dp_d0_flying_mode; +wire [1:0] reg2dp_d0_input_data; +wire [3:0] reg2dp_d0_kernel_stride_width; +wire [3:0] reg2dp_d0_kernel_width; +wire reg2dp_d0_op_en_trigger; +wire [3:0] reg2dp_d0_pad_width; +wire [9:0] reg2dp_d0_partial_width_in_first; +wire [9:0] reg2dp_d0_partial_width_in_last; +wire [9:0] reg2dp_d0_partial_width_in_mid; +wire [7:0] reg2dp_d0_split_num; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire reg2dp_d0_src_ram_type; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d1_cube_in_channel; +wire [12:0] reg2dp_d1_cube_in_height; +wire [12:0] reg2dp_d1_cube_in_width; +wire [31:0] reg2dp_d1_cya; +wire reg2dp_d1_dma_en; +wire reg2dp_d1_flying_mode; +wire [1:0] reg2dp_d1_input_data; +wire [3:0] reg2dp_d1_kernel_stride_width; +wire [3:0] reg2dp_d1_kernel_width; +wire reg2dp_d1_op_en_trigger; +wire [3:0] reg2dp_d1_pad_width; +wire [9:0] reg2dp_d1_partial_width_in_first; +wire [9:0] reg2dp_d1_partial_width_in_last; +wire [9:0] reg2dp_d1_partial_width_in_mid; +wire [7:0] reg2dp_d1_split_num; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire reg2dp_d1_src_ram_type; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire slcg_op_en_d0; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [33:0] pdp_rdma2csb_resp_pd; +reg pdp_rdma2csb_resp_valid; +reg [12:0] reg2dp_cube_in_channel; +reg [12:0] reg2dp_cube_in_height; +reg [12:0] reg2dp_cube_in_width; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_dma_en; +reg reg2dp_flying_mode; +reg [1:0] reg2dp_input_data; +reg [3:0] reg2dp_kernel_stride_width; +reg [3:0] reg2dp_kernel_width; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [3:0] reg2dp_pad_width; +reg [9:0] reg2dp_partial_width_in_first; +reg [9:0] reg2dp_partial_width_in_last; +reg [9:0] reg2dp_partial_width_in_mid; +reg [7:0] reg2dp_split_num; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg reg2dp_src_ram_type; +reg [31:0] reg2dp_src_surface_stride; +reg [62:0] req_pd; +reg req_pvld; +reg slcg_op_en_d1; +reg slcg_op_en_d2; +reg slcg_op_en_d3; +//Instance single register group +NV_NVDLA_PDP_RDMA_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_PDP_RDMA_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d0_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d0_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d0_cube_in_width[12:0]) //|> w + ,.input_data (reg2dp_d0_input_data[1:0]) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.split_num (reg2dp_d0_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d0_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d0_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d0_partial_width_in_mid[9:0]) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.kernel_stride_width (reg2dp_d0_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d0_kernel_width[3:0]) //|> w + ,.pad_width (reg2dp_d0_pad_width[3:0]) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_ram_type (reg2dp_d0_src_ram_type) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) //|< i + ); +NV_NVDLA_PDP_RDMA_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d1_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d1_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d1_cube_in_width[12:0]) //|> w + ,.input_data (reg2dp_d1_input_data[1:0]) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.split_num (reg2dp_d1_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d1_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d1_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d1_partial_width_in_mid[9:0]) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.kernel_stride_width (reg2dp_d1_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d1_kernel_width[3:0]) //|> w + ,.pad_width (reg2dp_d1_pad_width[3:0]) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_ram_type (reg2dp_d1_src_ram_type) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {1{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= 1'b0; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= 1'b0; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= 1'b0; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hc008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hc008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hc008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2pdp_rdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2pdp_rdma_req_pvld) == 1'b1) begin + req_pd <= csb2pdp_rdma_req_pd; +// VCS coverage off + end else if ((csb2pdp_rdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2pdp_rdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2pdp_rdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + pdp_rdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + pdp_rdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_rdma2csb_resp_valid <= 1'b0; + end else begin + pdp_rdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_channel + or reg2dp_d0_cube_in_channel + ) begin + reg2dp_cube_in_channel = dp2reg_consumer ? reg2dp_d1_cube_in_channel : reg2dp_d0_cube_in_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_height + or reg2dp_d0_cube_in_height + ) begin + reg2dp_cube_in_height = dp2reg_consumer ? reg2dp_d1_cube_in_height : reg2dp_d0_cube_in_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_width + or reg2dp_d0_cube_in_width + ) begin + reg2dp_cube_in_width = dp2reg_consumer ? reg2dp_d1_cube_in_width : reg2dp_d0_cube_in_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data + or reg2dp_d0_input_data + ) begin + reg2dp_input_data = dp2reg_consumer ? reg2dp_d1_input_data : reg2dp_d0_input_data; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_split_num + or reg2dp_d0_split_num + ) begin + reg2dp_split_num = dp2reg_consumer ? reg2dp_d1_split_num : reg2dp_d0_split_num; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_first + or reg2dp_d0_partial_width_in_first + ) begin + reg2dp_partial_width_in_first = dp2reg_consumer ? reg2dp_d1_partial_width_in_first : reg2dp_d0_partial_width_in_first; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_last + or reg2dp_d0_partial_width_in_last + ) begin + reg2dp_partial_width_in_last = dp2reg_consumer ? reg2dp_d1_partial_width_in_last : reg2dp_d0_partial_width_in_last; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_mid + or reg2dp_d0_partial_width_in_mid + ) begin + reg2dp_partial_width_in_mid = dp2reg_consumer ? reg2dp_d1_partial_width_in_mid : reg2dp_d0_partial_width_in_mid; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_stride_width + or reg2dp_d0_kernel_stride_width + ) begin + reg2dp_kernel_stride_width = dp2reg_consumer ? reg2dp_d1_kernel_stride_width : reg2dp_d0_kernel_stride_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_width + or reg2dp_d0_kernel_width + ) begin + reg2dp_kernel_width = dp2reg_consumer ? reg2dp_d1_kernel_width : reg2dp_d0_kernel_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_width + or reg2dp_d0_pad_width + ) begin + reg2dp_pad_width = dp2reg_consumer ? reg2dp_d1_pad_width : reg2dp_d0_pad_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_ram_type + or reg2dp_d0_src_ram_type + ) begin + reg2dp_src_ram_type = dp2reg_consumer ? reg2dp_d1_src_ram_type : reg2dp_d0_src_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//No extra logic +endmodule // NV_NVDLA_PDP_RDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v new file mode 100644 index 0000000..aea2c45 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v @@ -0,0 +1,780 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_REG_dual.v +module NV_NVDLA_PDP_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,cube_in_channel + ,cube_in_height + ,cube_in_width + ,cube_out_channel + ,cube_out_height + ,cube_out_width + ,input_data + ,dst_base_addr_high + ,dst_base_addr_low + ,dst_line_stride + ,dst_ram_type + ,dst_surface_stride + ,nan_to_zero + ,flying_mode + ,pooling_method + ,split_num + ,op_en_trigger + ,partial_width_in_first + ,partial_width_in_last + ,partial_width_in_mid + ,partial_width_out_first + ,partial_width_out_last + ,partial_width_out_mid + ,dma_en + ,kernel_height + ,kernel_stride_height + ,kernel_stride_width + ,kernel_width + ,pad_bottom + ,pad_left + ,pad_right + ,pad_top + ,pad_value_1x + ,pad_value_2x + ,pad_value_3x + ,pad_value_4x + ,pad_value_5x + ,pad_value_6x + ,pad_value_7x + ,recip_kernel_height + ,recip_kernel_width + ,src_base_addr_high + ,src_base_addr_low + ,src_line_stride + ,src_surface_stride + ,inf_input_num + ,nan_input_num + ,nan_output_num + ,op_en + ,perf_write_stall + ); +wire [31:0] nvdla_pdp_d_cya_0_out; +wire [31:0] nvdla_pdp_d_data_cube_in_channel_0_out; +wire [31:0] nvdla_pdp_d_data_cube_in_height_0_out; +wire [31:0] nvdla_pdp_d_data_cube_in_width_0_out; +wire [31:0] nvdla_pdp_d_data_cube_out_channel_0_out; +wire [31:0] nvdla_pdp_d_data_cube_out_height_0_out; +wire [31:0] nvdla_pdp_d_data_cube_out_width_0_out; +wire [31:0] nvdla_pdp_d_data_format_0_out; +wire [31:0] nvdla_pdp_d_dst_base_addr_high_0_out; +wire [31:0] nvdla_pdp_d_dst_base_addr_low_0_out; +wire [31:0] nvdla_pdp_d_dst_line_stride_0_out; +wire [31:0] nvdla_pdp_d_dst_ram_cfg_0_out; +wire [31:0] nvdla_pdp_d_dst_surface_stride_0_out; +wire [31:0] nvdla_pdp_d_inf_input_num_0_out; +wire [31:0] nvdla_pdp_d_nan_flush_to_zero_0_out; +wire [31:0] nvdla_pdp_d_nan_input_num_0_out; +wire [31:0] nvdla_pdp_d_nan_output_num_0_out; +wire [31:0] nvdla_pdp_d_op_enable_0_out; +wire [31:0] nvdla_pdp_d_operation_mode_cfg_0_out; +wire [31:0] nvdla_pdp_d_partial_width_in_0_out; +wire [31:0] nvdla_pdp_d_partial_width_out_0_out; +wire [31:0] nvdla_pdp_d_perf_enable_0_out; +wire [31:0] nvdla_pdp_d_perf_write_stall_0_out; +wire [31:0] nvdla_pdp_d_pooling_kernel_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_1_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_2_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_3_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_4_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_5_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_6_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_7_cfg_0_out; +wire [31:0] nvdla_pdp_d_recip_kernel_height_0_out; +wire [31:0] nvdla_pdp_d_recip_kernel_width_0_out; +wire [31:0] nvdla_pdp_d_src_base_addr_high_0_out; +wire [31:0] nvdla_pdp_d_src_base_addr_low_0_out; +wire [31:0] nvdla_pdp_d_src_line_stride_0_out; +wire [31:0] nvdla_pdp_d_src_surface_stride_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [12:0] cube_in_channel; +output [12:0] cube_in_height; +output [12:0] cube_in_width; +output [12:0] cube_out_channel; +output [12:0] cube_out_height; +output [12:0] cube_out_width; +output [1:0] input_data; +output [31:0] dst_base_addr_high; +output [31:0] dst_base_addr_low; +output [31:0] dst_line_stride; +output dst_ram_type; +output [31:0] dst_surface_stride; +output nan_to_zero; +output flying_mode; +output [1:0] pooling_method; +output [7:0] split_num; +output op_en_trigger; +output [9:0] partial_width_in_first; +output [9:0] partial_width_in_last; +output [9:0] partial_width_in_mid; +output [9:0] partial_width_out_first; +output [9:0] partial_width_out_last; +output [9:0] partial_width_out_mid; +output dma_en; +output [3:0] kernel_height; +output [3:0] kernel_stride_height; +output [3:0] kernel_stride_width; +output [3:0] kernel_width; +output [2:0] pad_bottom; +output [2:0] pad_left; +output [2:0] pad_right; +output [2:0] pad_top; +output [18:0] pad_value_1x; +output [18:0] pad_value_2x; +output [18:0] pad_value_3x; +output [18:0] pad_value_4x; +output [18:0] pad_value_5x; +output [18:0] pad_value_6x; +output [18:0] pad_value_7x; +output [16:0] recip_kernel_height; +output [16:0] recip_kernel_width; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output [31:0] src_line_stride; +output [31:0] src_surface_stride; +// Read-only register inputs +input [31:0] inf_input_num; +input [31:0] nan_input_num; +input [31:0] nan_output_num; +input op_en; +input [31:0] perf_write_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [12:0] cube_in_channel; +reg [12:0] cube_in_height; +reg [12:0] cube_in_width; +reg [12:0] cube_out_channel; +reg [12:0] cube_out_height; +reg [12:0] cube_out_width; +reg [31:0] cya; +reg dma_en; +reg [31:0] dst_base_addr_high; +reg [31:0] dst_base_addr_low; +reg [31:0] dst_line_stride; +reg dst_ram_type; +reg [31:0] dst_surface_stride; +reg flying_mode; +reg [1:0] input_data; +reg [3:0] kernel_height; +reg [3:0] kernel_stride_height; +reg [3:0] kernel_stride_width; +reg [3:0] kernel_width; +reg nan_to_zero; +reg [2:0] pad_bottom; +reg [2:0] pad_left; +reg [2:0] pad_right; +reg [2:0] pad_top; +reg [18:0] pad_value_1x; +reg [18:0] pad_value_2x; +reg [18:0] pad_value_3x; +reg [18:0] pad_value_4x; +reg [18:0] pad_value_5x; +reg [18:0] pad_value_6x; +reg [18:0] pad_value_7x; +reg [9:0] partial_width_in_first; +reg [9:0] partial_width_in_last; +reg [9:0] partial_width_in_mid; +reg [9:0] partial_width_out_first; +reg [9:0] partial_width_out_last; +reg [9:0] partial_width_out_mid; +reg [1:0] pooling_method; +reg [16:0] recip_kernel_height; +reg [16:0] recip_kernel_width; +reg [31:0] reg_rd_data; +reg [7:0] split_num; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg [31:0] src_surface_stride; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_d_cya_0_wren = (reg_offset_wr == (32'hd09c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_in_channel_0_wren = (reg_offset_wr == (32'hd014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_in_height_0_wren = (reg_offset_wr == (32'hd010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_in_width_0_wren = (reg_offset_wr == (32'hd00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_out_channel_0_wren = (reg_offset_wr == (32'hd020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_out_height_0_wren = (reg_offset_wr == (32'hd01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_out_width_0_wren = (reg_offset_wr == (32'hd018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_format_0_wren = (reg_offset_wr == (32'hd084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_base_addr_high_0_wren = (reg_offset_wr == (32'hd074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_base_addr_low_0_wren = (reg_offset_wr == (32'hd070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_line_stride_0_wren = (reg_offset_wr == (32'hd078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_ram_cfg_0_wren = (reg_offset_wr == (32'hd080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_surface_stride_0_wren = (reg_offset_wr == (32'hd07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_inf_input_num_0_wren = (reg_offset_wr == (32'hd088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_nan_flush_to_zero_0_wren = (reg_offset_wr == (32'hd028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_nan_input_num_0_wren = (reg_offset_wr == (32'hd08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_nan_output_num_0_wren = (reg_offset_wr == (32'hd090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_operation_mode_cfg_0_wren = (reg_offset_wr == (32'hd024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_op_enable_0_wren = (reg_offset_wr == (32'hd008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_partial_width_in_0_wren = (reg_offset_wr == (32'hd02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_partial_width_out_0_wren = (reg_offset_wr == (32'hd030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_perf_enable_0_wren = (reg_offset_wr == (32'hd094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_perf_write_stall_0_wren = (reg_offset_wr == (32'hd098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_kernel_cfg_0_wren = (reg_offset_wr == (32'hd034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_cfg_0_wren = (reg_offset_wr == (32'hd040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_1_cfg_0_wren = (reg_offset_wr == (32'hd044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_2_cfg_0_wren = (reg_offset_wr == (32'hd048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_3_cfg_0_wren = (reg_offset_wr == (32'hd04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_4_cfg_0_wren = (reg_offset_wr == (32'hd050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_5_cfg_0_wren = (reg_offset_wr == (32'hd054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_6_cfg_0_wren = (reg_offset_wr == (32'hd058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_7_cfg_0_wren = (reg_offset_wr == (32'hd05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_recip_kernel_height_0_wren = (reg_offset_wr == (32'hd03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_recip_kernel_width_0_wren = (reg_offset_wr == (32'hd038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'hd064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'hd060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_line_stride_0_wren = (reg_offset_wr == (32'hd068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_surface_stride_0_wren = (reg_offset_wr == (32'hd06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_d_cya_0_out[31:0] = { cya }; +assign nvdla_pdp_d_data_cube_in_channel_0_out[31:0] = { 19'b0, cube_in_channel }; +assign nvdla_pdp_d_data_cube_in_height_0_out[31:0] = { 19'b0, cube_in_height }; +assign nvdla_pdp_d_data_cube_in_width_0_out[31:0] = { 19'b0, cube_in_width }; +assign nvdla_pdp_d_data_cube_out_channel_0_out[31:0] = { 19'b0, cube_out_channel }; +assign nvdla_pdp_d_data_cube_out_height_0_out[31:0] = { 19'b0, cube_out_height }; +assign nvdla_pdp_d_data_cube_out_width_0_out[31:0] = { 19'b0, cube_out_width }; +assign nvdla_pdp_d_data_format_0_out[31:0] = { 30'b0, input_data }; +assign nvdla_pdp_d_dst_base_addr_high_0_out[31:0] = { dst_base_addr_high }; +//assign nvdla_pdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low, 5'b0 }; +assign nvdla_pdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low }; +assign nvdla_pdp_d_dst_line_stride_0_out[31:0] = { dst_line_stride }; +assign nvdla_pdp_d_dst_ram_cfg_0_out[31:0] = { 31'b0, dst_ram_type }; +assign nvdla_pdp_d_dst_surface_stride_0_out[31:0] = { dst_surface_stride }; +assign nvdla_pdp_d_inf_input_num_0_out[31:0] = { inf_input_num }; +assign nvdla_pdp_d_nan_flush_to_zero_0_out[31:0] = { 31'b0, nan_to_zero }; +assign nvdla_pdp_d_nan_input_num_0_out[31:0] = { nan_input_num }; +assign nvdla_pdp_d_nan_output_num_0_out[31:0] = { nan_output_num }; +assign nvdla_pdp_d_operation_mode_cfg_0_out[31:0] = { 16'b0, split_num, 3'b0, flying_mode, 2'b0, pooling_method }; +assign nvdla_pdp_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_pdp_d_partial_width_in_0_out[31:0] = { 2'b0, partial_width_in_mid, partial_width_in_last, partial_width_in_first }; +assign nvdla_pdp_d_partial_width_out_0_out[31:0] = { 2'b0, partial_width_out_mid, partial_width_out_last, partial_width_out_first }; +assign nvdla_pdp_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_pdp_d_perf_write_stall_0_out[31:0] = { perf_write_stall }; +assign nvdla_pdp_d_pooling_kernel_cfg_0_out[31:0] = { 8'b0, kernel_stride_height, kernel_stride_width, 4'b0, kernel_height, 4'b0, kernel_width }; +assign nvdla_pdp_d_pooling_padding_cfg_0_out[31:0] = { 17'b0, pad_bottom, 1'b0, pad_right, 1'b0, pad_top, 1'b0, pad_left }; +assign nvdla_pdp_d_pooling_padding_value_1_cfg_0_out[31:0] = { 13'b0, pad_value_1x }; +assign nvdla_pdp_d_pooling_padding_value_2_cfg_0_out[31:0] = { 13'b0, pad_value_2x }; +assign nvdla_pdp_d_pooling_padding_value_3_cfg_0_out[31:0] = { 13'b0, pad_value_3x }; +assign nvdla_pdp_d_pooling_padding_value_4_cfg_0_out[31:0] = { 13'b0, pad_value_4x }; +assign nvdla_pdp_d_pooling_padding_value_5_cfg_0_out[31:0] = { 13'b0, pad_value_5x }; +assign nvdla_pdp_d_pooling_padding_value_6_cfg_0_out[31:0] = { 13'b0, pad_value_6x }; +assign nvdla_pdp_d_pooling_padding_value_7_cfg_0_out[31:0] = { 13'b0, pad_value_7x }; +assign nvdla_pdp_d_recip_kernel_height_0_out[31:0] = { 15'b0, recip_kernel_height }; +assign nvdla_pdp_d_recip_kernel_width_0_out[31:0] = { 15'b0, recip_kernel_width }; +assign nvdla_pdp_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_pdp_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low }; +assign nvdla_pdp_d_src_line_stride_0_out[31:0] = { src_line_stride }; +assign nvdla_pdp_d_src_surface_stride_0_out[31:0] = { src_surface_stride }; +assign op_en_trigger = nvdla_pdp_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_d_cya_0_out + or nvdla_pdp_d_data_cube_in_channel_0_out + or nvdla_pdp_d_data_cube_in_height_0_out + or nvdla_pdp_d_data_cube_in_width_0_out + or nvdla_pdp_d_data_cube_out_channel_0_out + or nvdla_pdp_d_data_cube_out_height_0_out + or nvdla_pdp_d_data_cube_out_width_0_out + or nvdla_pdp_d_data_format_0_out + or nvdla_pdp_d_dst_base_addr_high_0_out + or nvdla_pdp_d_dst_base_addr_low_0_out + or nvdla_pdp_d_dst_line_stride_0_out + or nvdla_pdp_d_dst_ram_cfg_0_out + or nvdla_pdp_d_dst_surface_stride_0_out + or nvdla_pdp_d_inf_input_num_0_out + or nvdla_pdp_d_nan_flush_to_zero_0_out + or nvdla_pdp_d_nan_input_num_0_out + or nvdla_pdp_d_nan_output_num_0_out + or nvdla_pdp_d_operation_mode_cfg_0_out + or nvdla_pdp_d_op_enable_0_out + or nvdla_pdp_d_partial_width_in_0_out + or nvdla_pdp_d_partial_width_out_0_out + or nvdla_pdp_d_perf_enable_0_out + or nvdla_pdp_d_perf_write_stall_0_out + or nvdla_pdp_d_pooling_kernel_cfg_0_out + or nvdla_pdp_d_pooling_padding_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_1_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_2_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_3_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_4_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_5_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_6_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_7_cfg_0_out + or nvdla_pdp_d_recip_kernel_height_0_out + or nvdla_pdp_d_recip_kernel_width_0_out + or nvdla_pdp_d_src_base_addr_high_0_out + or nvdla_pdp_d_src_base_addr_low_0_out + or nvdla_pdp_d_src_line_stride_0_out + or nvdla_pdp_d_src_surface_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'hd09c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_cya_0_out ; + end + (32'hd014 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_in_channel_0_out ; + end + (32'hd010 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_in_height_0_out ; + end + (32'hd00c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_in_width_0_out ; + end + (32'hd020 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_out_channel_0_out ; + end + (32'hd01c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_out_height_0_out ; + end + (32'hd018 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_out_width_0_out ; + end + (32'hd084 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_format_0_out ; + end + (32'hd074 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_base_addr_high_0_out ; + end + (32'hd070 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_base_addr_low_0_out ; + end + (32'hd078 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_line_stride_0_out ; + end + (32'hd080 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_ram_cfg_0_out ; + end + (32'hd07c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_surface_stride_0_out ; + end + (32'hd088 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_inf_input_num_0_out ; + end + (32'hd028 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_nan_flush_to_zero_0_out ; + end + (32'hd08c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_nan_input_num_0_out ; + end + (32'hd090 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_nan_output_num_0_out ; + end + (32'hd024 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_operation_mode_cfg_0_out ; + end + (32'hd008 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_op_enable_0_out ; + end + (32'hd02c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_partial_width_in_0_out ; + end + (32'hd030 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_partial_width_out_0_out ; + end + (32'hd094 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_perf_enable_0_out ; + end + (32'hd098 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_perf_write_stall_0_out ; + end + (32'hd034 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_kernel_cfg_0_out ; + end + (32'hd040 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_cfg_0_out ; + end + (32'hd044 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_1_cfg_0_out ; + end + (32'hd048 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_2_cfg_0_out ; + end + (32'hd04c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_3_cfg_0_out ; + end + (32'hd050 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_4_cfg_0_out ; + end + (32'hd054 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_5_cfg_0_out ; + end + (32'hd058 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_6_cfg_0_out ; + end + (32'hd05c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_7_cfg_0_out ; + end + (32'hd03c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_recip_kernel_height_0_out ; + end + (32'hd038 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_recip_kernel_width_0_out ; + end + (32'hd064 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_base_addr_high_0_out ; + end + (32'hd060 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_base_addr_low_0_out ; + end + (32'hd068 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_line_stride_0_out ; + end + (32'hd06c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_surface_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + cube_in_channel[12:0] <= 13'b0000000000000; + cube_in_height[12:0] <= 13'b0000000000000; + cube_in_width[12:0] <= 13'b0000000000000; + cube_out_channel[12:0] <= 13'b0000000000000; + cube_out_height[12:0] <= 13'b0000000000000; + cube_out_width[12:0] <= 13'b0000000000000; + input_data[1:0] <= 2'b00; + dst_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + dst_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + dst_line_stride[31:0] <= 32'b00000000000000000000000000000000; + dst_ram_type <= 1'b0; + dst_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + nan_to_zero <= 1'b0; + flying_mode <= 1'b0; + pooling_method[1:0] <= 2'b00; + split_num[7:0] <= 8'b00000000; + partial_width_in_first[9:0] <= 10'b0000000000; + partial_width_in_last[9:0] <= 10'b0000000000; + partial_width_in_mid[9:0] <= 10'b0000000000; + partial_width_out_first[9:0] <= 10'b0000000000; + partial_width_out_last[9:0] <= 10'b0000000000; + partial_width_out_mid[9:0] <= 10'b0000000000; + dma_en <= 1'b0; + kernel_height[3:0] <= 4'b0000; + kernel_stride_height[3:0] <= 4'b0000; + kernel_stride_width[3:0] <= 4'b0000; + kernel_width[3:0] <= 4'b0000; + pad_bottom[2:0] <= 3'b000; + pad_left[2:0] <= 3'b000; + pad_right[2:0] <= 3'b000; + pad_top[2:0] <= 3'b000; + pad_value_1x[18:0] <= 19'b0000000000000000000; + pad_value_2x[18:0] <= 19'b0000000000000000000; + pad_value_3x[18:0] <= 19'b0000000000000000000; + pad_value_4x[18:0] <= 19'b0000000000000000000; + pad_value_5x[18:0] <= 19'b0000000000000000000; + pad_value_6x[18:0] <= 19'b0000000000000000000; + pad_value_7x[18:0] <= 19'b0000000000000000000; + recip_kernel_height[16:0] <= 17'b00000000000000000; + recip_kernel_width[16:0] <= 17'b00000000000000000; + src_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + src_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + src_line_stride[31:0] <= 32'b00000000000000000000000000000000; + src_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + end else begin +// Register: NVDLA_PDP_D_CYA_0 Field: cya + if (nvdla_pdp_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_IN_CHANNEL_0 Field: cube_in_channel + if (nvdla_pdp_d_data_cube_in_channel_0_wren) begin + cube_in_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_IN_HEIGHT_0 Field: cube_in_height + if (nvdla_pdp_d_data_cube_in_height_0_wren) begin + cube_in_height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_IN_WIDTH_0 Field: cube_in_width + if (nvdla_pdp_d_data_cube_in_width_0_wren) begin + cube_in_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_OUT_CHANNEL_0 Field: cube_out_channel + if (nvdla_pdp_d_data_cube_out_channel_0_wren) begin + cube_out_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_OUT_HEIGHT_0 Field: cube_out_height + if (nvdla_pdp_d_data_cube_out_height_0_wren) begin + cube_out_height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_OUT_WIDTH_0 Field: cube_out_width + if (nvdla_pdp_d_data_cube_out_width_0_wren) begin + cube_out_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_FORMAT_0 Field: input_data + if (nvdla_pdp_d_data_format_0_wren) begin + input_data[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_PDP_D_DST_BASE_ADDR_HIGH_0 Field: dst_base_addr_high + if (nvdla_pdp_d_dst_base_addr_high_0_wren) begin + dst_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DST_BASE_ADDR_LOW_0 Field: dst_base_addr_low + if (nvdla_pdp_d_dst_base_addr_low_0_wren) begin + dst_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DST_LINE_STRIDE_0 Field: dst_line_stride + if (nvdla_pdp_d_dst_line_stride_0_wren) begin + dst_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DST_RAM_CFG_0 Field: dst_ram_type + if (nvdla_pdp_d_dst_ram_cfg_0_wren) begin + dst_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_PDP_D_DST_SURFACE_STRIDE_0 Field: dst_surface_stride + if (nvdla_pdp_d_dst_surface_stride_0_wren) begin + dst_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_PDP_D_INF_INPUT_NUM_0::inf_input_num +// Register: NVDLA_PDP_D_NAN_FLUSH_TO_ZERO_0 Field: nan_to_zero + if (nvdla_pdp_d_nan_flush_to_zero_0_wren) begin + nan_to_zero <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_D_NAN_INPUT_NUM_0::nan_input_num +// Not generating flops for read-only field NVDLA_PDP_D_NAN_OUTPUT_NUM_0::nan_output_num +// Register: NVDLA_PDP_D_OPERATION_MODE_CFG_0 Field: flying_mode + if (nvdla_pdp_d_operation_mode_cfg_0_wren) begin + flying_mode <= reg_wr_data[4]; + end +// Register: NVDLA_PDP_D_OPERATION_MODE_CFG_0 Field: pooling_method + if (nvdla_pdp_d_operation_mode_cfg_0_wren) begin + pooling_method[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_PDP_D_OPERATION_MODE_CFG_0 Field: split_num + if (nvdla_pdp_d_operation_mode_cfg_0_wren) begin + split_num[7:0] <= reg_wr_data[15:8]; + end +// Not generating flops for field NVDLA_PDP_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_first + if (nvdla_pdp_d_partial_width_in_0_wren) begin + partial_width_in_first[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_last + if (nvdla_pdp_d_partial_width_in_0_wren) begin + partial_width_in_last[9:0] <= reg_wr_data[19:10]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_mid + if (nvdla_pdp_d_partial_width_in_0_wren) begin + partial_width_in_mid[9:0] <= reg_wr_data[29:20]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 Field: partial_width_out_first + if (nvdla_pdp_d_partial_width_out_0_wren) begin + partial_width_out_first[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 Field: partial_width_out_last + if (nvdla_pdp_d_partial_width_out_0_wren) begin + partial_width_out_last[9:0] <= reg_wr_data[19:10]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 Field: partial_width_out_mid + if (nvdla_pdp_d_partial_width_out_0_wren) begin + partial_width_out_mid[9:0] <= reg_wr_data[29:20]; + end +// Register: NVDLA_PDP_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_pdp_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_D_PERF_WRITE_STALL_0::perf_write_stall +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_height + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_height[3:0] <= reg_wr_data[11:8]; + end +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_stride_height + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_stride_height[3:0] <= reg_wr_data[23:20]; + end +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_stride_width + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_stride_width[3:0] <= reg_wr_data[19:16]; + end +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_width + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_width[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_bottom + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_bottom[2:0] <= reg_wr_data[14:12]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_left + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_left[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_right + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_right[2:0] <= reg_wr_data[10:8]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_top + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_top[2:0] <= reg_wr_data[6:4]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_1_CFG_0 Field: pad_value_1x + if (nvdla_pdp_d_pooling_padding_value_1_cfg_0_wren) begin + pad_value_1x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_2_CFG_0 Field: pad_value_2x + if (nvdla_pdp_d_pooling_padding_value_2_cfg_0_wren) begin + pad_value_2x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_3_CFG_0 Field: pad_value_3x + if (nvdla_pdp_d_pooling_padding_value_3_cfg_0_wren) begin + pad_value_3x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_4_CFG_0 Field: pad_value_4x + if (nvdla_pdp_d_pooling_padding_value_4_cfg_0_wren) begin + pad_value_4x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_5_CFG_0 Field: pad_value_5x + if (nvdla_pdp_d_pooling_padding_value_5_cfg_0_wren) begin + pad_value_5x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_6_CFG_0 Field: pad_value_6x + if (nvdla_pdp_d_pooling_padding_value_6_cfg_0_wren) begin + pad_value_6x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_7_CFG_0 Field: pad_value_7x + if (nvdla_pdp_d_pooling_padding_value_7_cfg_0_wren) begin + pad_value_7x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_RECIP_KERNEL_HEIGHT_0 Field: recip_kernel_height + if (nvdla_pdp_d_recip_kernel_height_0_wren) begin + recip_kernel_height[16:0] <= reg_wr_data[16:0]; + end +// Register: NVDLA_PDP_D_RECIP_KERNEL_WIDTH_0 Field: recip_kernel_width + if (nvdla_pdp_d_recip_kernel_width_0_wren) begin + recip_kernel_width[16:0] <= reg_wr_data[16:0]; + end +// Register: NVDLA_PDP_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_pdp_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_pdp_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_pdp_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_pdp_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hd09c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_cya_0_out, nvdla_pdp_d_cya_0_out); + (32'hd014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_IN_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_in_channel_0_out, nvdla_pdp_d_data_cube_in_channel_0_out); + (32'hd010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_IN_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_in_height_0_out, nvdla_pdp_d_data_cube_in_height_0_out); + (32'hd00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_IN_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_in_width_0_out, nvdla_pdp_d_data_cube_in_width_0_out); + (32'hd020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_OUT_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_out_channel_0_out, nvdla_pdp_d_data_cube_out_channel_0_out); + (32'hd01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_OUT_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_out_height_0_out, nvdla_pdp_d_data_cube_out_height_0_out); + (32'hd018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_OUT_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_out_width_0_out, nvdla_pdp_d_data_cube_out_width_0_out); + (32'hd084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_format_0_out, nvdla_pdp_d_data_format_0_out); + (32'hd074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_base_addr_high_0_out, nvdla_pdp_d_dst_base_addr_high_0_out); + (32'hd070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_base_addr_low_0_out, nvdla_pdp_d_dst_base_addr_low_0_out); + (32'hd078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_line_stride_0_out, nvdla_pdp_d_dst_line_stride_0_out); + (32'hd080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_RAM_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_ram_cfg_0_out, nvdla_pdp_d_dst_ram_cfg_0_out); + (32'hd07c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_surface_stride_0_out, nvdla_pdp_d_dst_surface_stride_0_out); + (32'hd088 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_NAN_FLUSH_TO_ZERO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_nan_flush_to_zero_0_out, nvdla_pdp_d_nan_flush_to_zero_0_out); + (32'hd08c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd090 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_NAN_OUTPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_OPERATION_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_operation_mode_cfg_0_out, nvdla_pdp_d_operation_mode_cfg_0_out); + (32'hd008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_op_enable_0_out, nvdla_pdp_d_op_enable_0_out); + (32'hd02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_partial_width_in_0_out, nvdla_pdp_d_partial_width_in_0_out); + (32'hd030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_partial_width_out_0_out, nvdla_pdp_d_partial_width_out_0_out); + (32'hd094 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_perf_enable_0_out, nvdla_pdp_d_perf_enable_0_out); + (32'hd098 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_PERF_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_kernel_cfg_0_out, nvdla_pdp_d_pooling_kernel_cfg_0_out); + (32'hd040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_cfg_0_out, nvdla_pdp_d_pooling_padding_cfg_0_out); + (32'hd044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_1_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_1_cfg_0_out, nvdla_pdp_d_pooling_padding_value_1_cfg_0_out); + (32'hd048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_2_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_2_cfg_0_out, nvdla_pdp_d_pooling_padding_value_2_cfg_0_out); + (32'hd04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_3_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_3_cfg_0_out, nvdla_pdp_d_pooling_padding_value_3_cfg_0_out); + (32'hd050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_4_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_4_cfg_0_out, nvdla_pdp_d_pooling_padding_value_4_cfg_0_out); + (32'hd054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_5_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_5_cfg_0_out, nvdla_pdp_d_pooling_padding_value_5_cfg_0_out); + (32'hd058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_6_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_6_cfg_0_out, nvdla_pdp_d_pooling_padding_value_6_cfg_0_out); + (32'hd05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_7_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_7_cfg_0_out, nvdla_pdp_d_pooling_padding_value_7_cfg_0_out); + (32'hd03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_RECIP_KERNEL_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_recip_kernel_height_0_out, nvdla_pdp_d_recip_kernel_height_0_out); + (32'hd038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_RECIP_KERNEL_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_recip_kernel_width_0_out, nvdla_pdp_d_recip_kernel_width_0_out); + (32'hd064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_base_addr_high_0_out, nvdla_pdp_d_src_base_addr_high_0_out); + (32'hd060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_base_addr_low_0_out, nvdla_pdp_d_src_base_addr_low_0_out); + (32'hd068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_line_stride_0_out, nvdla_pdp_d_src_line_stride_0_out); + (32'hd06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_surface_stride_0_out, nvdla_pdp_d_src_surface_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v.vcp new file mode 100644 index 0000000..aea2c45 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v.vcp @@ -0,0 +1,780 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_REG_dual.v +module NV_NVDLA_PDP_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cya + ,cube_in_channel + ,cube_in_height + ,cube_in_width + ,cube_out_channel + ,cube_out_height + ,cube_out_width + ,input_data + ,dst_base_addr_high + ,dst_base_addr_low + ,dst_line_stride + ,dst_ram_type + ,dst_surface_stride + ,nan_to_zero + ,flying_mode + ,pooling_method + ,split_num + ,op_en_trigger + ,partial_width_in_first + ,partial_width_in_last + ,partial_width_in_mid + ,partial_width_out_first + ,partial_width_out_last + ,partial_width_out_mid + ,dma_en + ,kernel_height + ,kernel_stride_height + ,kernel_stride_width + ,kernel_width + ,pad_bottom + ,pad_left + ,pad_right + ,pad_top + ,pad_value_1x + ,pad_value_2x + ,pad_value_3x + ,pad_value_4x + ,pad_value_5x + ,pad_value_6x + ,pad_value_7x + ,recip_kernel_height + ,recip_kernel_width + ,src_base_addr_high + ,src_base_addr_low + ,src_line_stride + ,src_surface_stride + ,inf_input_num + ,nan_input_num + ,nan_output_num + ,op_en + ,perf_write_stall + ); +wire [31:0] nvdla_pdp_d_cya_0_out; +wire [31:0] nvdla_pdp_d_data_cube_in_channel_0_out; +wire [31:0] nvdla_pdp_d_data_cube_in_height_0_out; +wire [31:0] nvdla_pdp_d_data_cube_in_width_0_out; +wire [31:0] nvdla_pdp_d_data_cube_out_channel_0_out; +wire [31:0] nvdla_pdp_d_data_cube_out_height_0_out; +wire [31:0] nvdla_pdp_d_data_cube_out_width_0_out; +wire [31:0] nvdla_pdp_d_data_format_0_out; +wire [31:0] nvdla_pdp_d_dst_base_addr_high_0_out; +wire [31:0] nvdla_pdp_d_dst_base_addr_low_0_out; +wire [31:0] nvdla_pdp_d_dst_line_stride_0_out; +wire [31:0] nvdla_pdp_d_dst_ram_cfg_0_out; +wire [31:0] nvdla_pdp_d_dst_surface_stride_0_out; +wire [31:0] nvdla_pdp_d_inf_input_num_0_out; +wire [31:0] nvdla_pdp_d_nan_flush_to_zero_0_out; +wire [31:0] nvdla_pdp_d_nan_input_num_0_out; +wire [31:0] nvdla_pdp_d_nan_output_num_0_out; +wire [31:0] nvdla_pdp_d_op_enable_0_out; +wire [31:0] nvdla_pdp_d_operation_mode_cfg_0_out; +wire [31:0] nvdla_pdp_d_partial_width_in_0_out; +wire [31:0] nvdla_pdp_d_partial_width_out_0_out; +wire [31:0] nvdla_pdp_d_perf_enable_0_out; +wire [31:0] nvdla_pdp_d_perf_write_stall_0_out; +wire [31:0] nvdla_pdp_d_pooling_kernel_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_1_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_2_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_3_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_4_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_5_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_6_cfg_0_out; +wire [31:0] nvdla_pdp_d_pooling_padding_value_7_cfg_0_out; +wire [31:0] nvdla_pdp_d_recip_kernel_height_0_out; +wire [31:0] nvdla_pdp_d_recip_kernel_width_0_out; +wire [31:0] nvdla_pdp_d_src_base_addr_high_0_out; +wire [31:0] nvdla_pdp_d_src_base_addr_low_0_out; +wire [31:0] nvdla_pdp_d_src_line_stride_0_out; +wire [31:0] nvdla_pdp_d_src_surface_stride_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cya; +output [12:0] cube_in_channel; +output [12:0] cube_in_height; +output [12:0] cube_in_width; +output [12:0] cube_out_channel; +output [12:0] cube_out_height; +output [12:0] cube_out_width; +output [1:0] input_data; +output [31:0] dst_base_addr_high; +output [31:0] dst_base_addr_low; +output [31:0] dst_line_stride; +output dst_ram_type; +output [31:0] dst_surface_stride; +output nan_to_zero; +output flying_mode; +output [1:0] pooling_method; +output [7:0] split_num; +output op_en_trigger; +output [9:0] partial_width_in_first; +output [9:0] partial_width_in_last; +output [9:0] partial_width_in_mid; +output [9:0] partial_width_out_first; +output [9:0] partial_width_out_last; +output [9:0] partial_width_out_mid; +output dma_en; +output [3:0] kernel_height; +output [3:0] kernel_stride_height; +output [3:0] kernel_stride_width; +output [3:0] kernel_width; +output [2:0] pad_bottom; +output [2:0] pad_left; +output [2:0] pad_right; +output [2:0] pad_top; +output [18:0] pad_value_1x; +output [18:0] pad_value_2x; +output [18:0] pad_value_3x; +output [18:0] pad_value_4x; +output [18:0] pad_value_5x; +output [18:0] pad_value_6x; +output [18:0] pad_value_7x; +output [16:0] recip_kernel_height; +output [16:0] recip_kernel_width; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output [31:0] src_line_stride; +output [31:0] src_surface_stride; +// Read-only register inputs +input [31:0] inf_input_num; +input [31:0] nan_input_num; +input [31:0] nan_output_num; +input op_en; +input [31:0] perf_write_stall; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [12:0] cube_in_channel; +reg [12:0] cube_in_height; +reg [12:0] cube_in_width; +reg [12:0] cube_out_channel; +reg [12:0] cube_out_height; +reg [12:0] cube_out_width; +reg [31:0] cya; +reg dma_en; +reg [31:0] dst_base_addr_high; +reg [31:0] dst_base_addr_low; +reg [31:0] dst_line_stride; +reg dst_ram_type; +reg [31:0] dst_surface_stride; +reg flying_mode; +reg [1:0] input_data; +reg [3:0] kernel_height; +reg [3:0] kernel_stride_height; +reg [3:0] kernel_stride_width; +reg [3:0] kernel_width; +reg nan_to_zero; +reg [2:0] pad_bottom; +reg [2:0] pad_left; +reg [2:0] pad_right; +reg [2:0] pad_top; +reg [18:0] pad_value_1x; +reg [18:0] pad_value_2x; +reg [18:0] pad_value_3x; +reg [18:0] pad_value_4x; +reg [18:0] pad_value_5x; +reg [18:0] pad_value_6x; +reg [18:0] pad_value_7x; +reg [9:0] partial_width_in_first; +reg [9:0] partial_width_in_last; +reg [9:0] partial_width_in_mid; +reg [9:0] partial_width_out_first; +reg [9:0] partial_width_out_last; +reg [9:0] partial_width_out_mid; +reg [1:0] pooling_method; +reg [16:0] recip_kernel_height; +reg [16:0] recip_kernel_width; +reg [31:0] reg_rd_data; +reg [7:0] split_num; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg [31:0] src_surface_stride; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_d_cya_0_wren = (reg_offset_wr == (32'hd09c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_in_channel_0_wren = (reg_offset_wr == (32'hd014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_in_height_0_wren = (reg_offset_wr == (32'hd010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_in_width_0_wren = (reg_offset_wr == (32'hd00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_out_channel_0_wren = (reg_offset_wr == (32'hd020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_out_height_0_wren = (reg_offset_wr == (32'hd01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_cube_out_width_0_wren = (reg_offset_wr == (32'hd018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_data_format_0_wren = (reg_offset_wr == (32'hd084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_base_addr_high_0_wren = (reg_offset_wr == (32'hd074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_base_addr_low_0_wren = (reg_offset_wr == (32'hd070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_line_stride_0_wren = (reg_offset_wr == (32'hd078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_ram_cfg_0_wren = (reg_offset_wr == (32'hd080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_dst_surface_stride_0_wren = (reg_offset_wr == (32'hd07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_inf_input_num_0_wren = (reg_offset_wr == (32'hd088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_nan_flush_to_zero_0_wren = (reg_offset_wr == (32'hd028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_nan_input_num_0_wren = (reg_offset_wr == (32'hd08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_nan_output_num_0_wren = (reg_offset_wr == (32'hd090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_operation_mode_cfg_0_wren = (reg_offset_wr == (32'hd024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_op_enable_0_wren = (reg_offset_wr == (32'hd008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_partial_width_in_0_wren = (reg_offset_wr == (32'hd02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_partial_width_out_0_wren = (reg_offset_wr == (32'hd030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_perf_enable_0_wren = (reg_offset_wr == (32'hd094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_perf_write_stall_0_wren = (reg_offset_wr == (32'hd098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_kernel_cfg_0_wren = (reg_offset_wr == (32'hd034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_cfg_0_wren = (reg_offset_wr == (32'hd040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_1_cfg_0_wren = (reg_offset_wr == (32'hd044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_2_cfg_0_wren = (reg_offset_wr == (32'hd048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_3_cfg_0_wren = (reg_offset_wr == (32'hd04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_4_cfg_0_wren = (reg_offset_wr == (32'hd050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_5_cfg_0_wren = (reg_offset_wr == (32'hd054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_6_cfg_0_wren = (reg_offset_wr == (32'hd058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_pooling_padding_value_7_cfg_0_wren = (reg_offset_wr == (32'hd05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_recip_kernel_height_0_wren = (reg_offset_wr == (32'hd03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_recip_kernel_width_0_wren = (reg_offset_wr == (32'hd038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'hd064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'hd060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_line_stride_0_wren = (reg_offset_wr == (32'hd068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_d_src_surface_stride_0_wren = (reg_offset_wr == (32'hd06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_d_cya_0_out[31:0] = { cya }; +assign nvdla_pdp_d_data_cube_in_channel_0_out[31:0] = { 19'b0, cube_in_channel }; +assign nvdla_pdp_d_data_cube_in_height_0_out[31:0] = { 19'b0, cube_in_height }; +assign nvdla_pdp_d_data_cube_in_width_0_out[31:0] = { 19'b0, cube_in_width }; +assign nvdla_pdp_d_data_cube_out_channel_0_out[31:0] = { 19'b0, cube_out_channel }; +assign nvdla_pdp_d_data_cube_out_height_0_out[31:0] = { 19'b0, cube_out_height }; +assign nvdla_pdp_d_data_cube_out_width_0_out[31:0] = { 19'b0, cube_out_width }; +assign nvdla_pdp_d_data_format_0_out[31:0] = { 30'b0, input_data }; +assign nvdla_pdp_d_dst_base_addr_high_0_out[31:0] = { dst_base_addr_high }; +//assign nvdla_pdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low, 5'b0 }; +assign nvdla_pdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low }; +assign nvdla_pdp_d_dst_line_stride_0_out[31:0] = { dst_line_stride }; +assign nvdla_pdp_d_dst_ram_cfg_0_out[31:0] = { 31'b0, dst_ram_type }; +assign nvdla_pdp_d_dst_surface_stride_0_out[31:0] = { dst_surface_stride }; +assign nvdla_pdp_d_inf_input_num_0_out[31:0] = { inf_input_num }; +assign nvdla_pdp_d_nan_flush_to_zero_0_out[31:0] = { 31'b0, nan_to_zero }; +assign nvdla_pdp_d_nan_input_num_0_out[31:0] = { nan_input_num }; +assign nvdla_pdp_d_nan_output_num_0_out[31:0] = { nan_output_num }; +assign nvdla_pdp_d_operation_mode_cfg_0_out[31:0] = { 16'b0, split_num, 3'b0, flying_mode, 2'b0, pooling_method }; +assign nvdla_pdp_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_pdp_d_partial_width_in_0_out[31:0] = { 2'b0, partial_width_in_mid, partial_width_in_last, partial_width_in_first }; +assign nvdla_pdp_d_partial_width_out_0_out[31:0] = { 2'b0, partial_width_out_mid, partial_width_out_last, partial_width_out_first }; +assign nvdla_pdp_d_perf_enable_0_out[31:0] = { 31'b0, dma_en }; +assign nvdla_pdp_d_perf_write_stall_0_out[31:0] = { perf_write_stall }; +assign nvdla_pdp_d_pooling_kernel_cfg_0_out[31:0] = { 8'b0, kernel_stride_height, kernel_stride_width, 4'b0, kernel_height, 4'b0, kernel_width }; +assign nvdla_pdp_d_pooling_padding_cfg_0_out[31:0] = { 17'b0, pad_bottom, 1'b0, pad_right, 1'b0, pad_top, 1'b0, pad_left }; +assign nvdla_pdp_d_pooling_padding_value_1_cfg_0_out[31:0] = { 13'b0, pad_value_1x }; +assign nvdla_pdp_d_pooling_padding_value_2_cfg_0_out[31:0] = { 13'b0, pad_value_2x }; +assign nvdla_pdp_d_pooling_padding_value_3_cfg_0_out[31:0] = { 13'b0, pad_value_3x }; +assign nvdla_pdp_d_pooling_padding_value_4_cfg_0_out[31:0] = { 13'b0, pad_value_4x }; +assign nvdla_pdp_d_pooling_padding_value_5_cfg_0_out[31:0] = { 13'b0, pad_value_5x }; +assign nvdla_pdp_d_pooling_padding_value_6_cfg_0_out[31:0] = { 13'b0, pad_value_6x }; +assign nvdla_pdp_d_pooling_padding_value_7_cfg_0_out[31:0] = { 13'b0, pad_value_7x }; +assign nvdla_pdp_d_recip_kernel_height_0_out[31:0] = { 15'b0, recip_kernel_height }; +assign nvdla_pdp_d_recip_kernel_width_0_out[31:0] = { 15'b0, recip_kernel_width }; +assign nvdla_pdp_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_pdp_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low }; +assign nvdla_pdp_d_src_line_stride_0_out[31:0] = { src_line_stride }; +assign nvdla_pdp_d_src_surface_stride_0_out[31:0] = { src_surface_stride }; +assign op_en_trigger = nvdla_pdp_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_d_cya_0_out + or nvdla_pdp_d_data_cube_in_channel_0_out + or nvdla_pdp_d_data_cube_in_height_0_out + or nvdla_pdp_d_data_cube_in_width_0_out + or nvdla_pdp_d_data_cube_out_channel_0_out + or nvdla_pdp_d_data_cube_out_height_0_out + or nvdla_pdp_d_data_cube_out_width_0_out + or nvdla_pdp_d_data_format_0_out + or nvdla_pdp_d_dst_base_addr_high_0_out + or nvdla_pdp_d_dst_base_addr_low_0_out + or nvdla_pdp_d_dst_line_stride_0_out + or nvdla_pdp_d_dst_ram_cfg_0_out + or nvdla_pdp_d_dst_surface_stride_0_out + or nvdla_pdp_d_inf_input_num_0_out + or nvdla_pdp_d_nan_flush_to_zero_0_out + or nvdla_pdp_d_nan_input_num_0_out + or nvdla_pdp_d_nan_output_num_0_out + or nvdla_pdp_d_operation_mode_cfg_0_out + or nvdla_pdp_d_op_enable_0_out + or nvdla_pdp_d_partial_width_in_0_out + or nvdla_pdp_d_partial_width_out_0_out + or nvdla_pdp_d_perf_enable_0_out + or nvdla_pdp_d_perf_write_stall_0_out + or nvdla_pdp_d_pooling_kernel_cfg_0_out + or nvdla_pdp_d_pooling_padding_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_1_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_2_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_3_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_4_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_5_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_6_cfg_0_out + or nvdla_pdp_d_pooling_padding_value_7_cfg_0_out + or nvdla_pdp_d_recip_kernel_height_0_out + or nvdla_pdp_d_recip_kernel_width_0_out + or nvdla_pdp_d_src_base_addr_high_0_out + or nvdla_pdp_d_src_base_addr_low_0_out + or nvdla_pdp_d_src_line_stride_0_out + or nvdla_pdp_d_src_surface_stride_0_out + ) begin + case (reg_offset_rd_int) + (32'hd09c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_cya_0_out ; + end + (32'hd014 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_in_channel_0_out ; + end + (32'hd010 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_in_height_0_out ; + end + (32'hd00c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_in_width_0_out ; + end + (32'hd020 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_out_channel_0_out ; + end + (32'hd01c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_out_height_0_out ; + end + (32'hd018 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_cube_out_width_0_out ; + end + (32'hd084 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_data_format_0_out ; + end + (32'hd074 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_base_addr_high_0_out ; + end + (32'hd070 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_base_addr_low_0_out ; + end + (32'hd078 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_line_stride_0_out ; + end + (32'hd080 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_ram_cfg_0_out ; + end + (32'hd07c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_dst_surface_stride_0_out ; + end + (32'hd088 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_inf_input_num_0_out ; + end + (32'hd028 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_nan_flush_to_zero_0_out ; + end + (32'hd08c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_nan_input_num_0_out ; + end + (32'hd090 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_nan_output_num_0_out ; + end + (32'hd024 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_operation_mode_cfg_0_out ; + end + (32'hd008 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_op_enable_0_out ; + end + (32'hd02c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_partial_width_in_0_out ; + end + (32'hd030 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_partial_width_out_0_out ; + end + (32'hd094 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_perf_enable_0_out ; + end + (32'hd098 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_perf_write_stall_0_out ; + end + (32'hd034 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_kernel_cfg_0_out ; + end + (32'hd040 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_cfg_0_out ; + end + (32'hd044 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_1_cfg_0_out ; + end + (32'hd048 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_2_cfg_0_out ; + end + (32'hd04c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_3_cfg_0_out ; + end + (32'hd050 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_4_cfg_0_out ; + end + (32'hd054 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_5_cfg_0_out ; + end + (32'hd058 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_6_cfg_0_out ; + end + (32'hd05c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_pooling_padding_value_7_cfg_0_out ; + end + (32'hd03c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_recip_kernel_height_0_out ; + end + (32'hd038 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_recip_kernel_width_0_out ; + end + (32'hd064 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_base_addr_high_0_out ; + end + (32'hd060 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_base_addr_low_0_out ; + end + (32'hd068 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_line_stride_0_out ; + end + (32'hd06c & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_d_src_surface_stride_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cya[31:0] <= 32'b00000000000000000000000000000000; + cube_in_channel[12:0] <= 13'b0000000000000; + cube_in_height[12:0] <= 13'b0000000000000; + cube_in_width[12:0] <= 13'b0000000000000; + cube_out_channel[12:0] <= 13'b0000000000000; + cube_out_height[12:0] <= 13'b0000000000000; + cube_out_width[12:0] <= 13'b0000000000000; + input_data[1:0] <= 2'b00; + dst_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + dst_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + dst_line_stride[31:0] <= 32'b00000000000000000000000000000000; + dst_ram_type <= 1'b0; + dst_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + nan_to_zero <= 1'b0; + flying_mode <= 1'b0; + pooling_method[1:0] <= 2'b00; + split_num[7:0] <= 8'b00000000; + partial_width_in_first[9:0] <= 10'b0000000000; + partial_width_in_last[9:0] <= 10'b0000000000; + partial_width_in_mid[9:0] <= 10'b0000000000; + partial_width_out_first[9:0] <= 10'b0000000000; + partial_width_out_last[9:0] <= 10'b0000000000; + partial_width_out_mid[9:0] <= 10'b0000000000; + dma_en <= 1'b0; + kernel_height[3:0] <= 4'b0000; + kernel_stride_height[3:0] <= 4'b0000; + kernel_stride_width[3:0] <= 4'b0000; + kernel_width[3:0] <= 4'b0000; + pad_bottom[2:0] <= 3'b000; + pad_left[2:0] <= 3'b000; + pad_right[2:0] <= 3'b000; + pad_top[2:0] <= 3'b000; + pad_value_1x[18:0] <= 19'b0000000000000000000; + pad_value_2x[18:0] <= 19'b0000000000000000000; + pad_value_3x[18:0] <= 19'b0000000000000000000; + pad_value_4x[18:0] <= 19'b0000000000000000000; + pad_value_5x[18:0] <= 19'b0000000000000000000; + pad_value_6x[18:0] <= 19'b0000000000000000000; + pad_value_7x[18:0] <= 19'b0000000000000000000; + recip_kernel_height[16:0] <= 17'b00000000000000000; + recip_kernel_width[16:0] <= 17'b00000000000000000; + src_base_addr_high[31:0] <= 32'b00000000000000000000000000000000; + src_base_addr_low[31:0] <= 32'b00000000000000000000000000000000; + src_line_stride[31:0] <= 32'b00000000000000000000000000000000; + src_surface_stride[31:0] <= 32'b00000000000000000000000000000000; + end else begin +// Register: NVDLA_PDP_D_CYA_0 Field: cya + if (nvdla_pdp_d_cya_0_wren) begin + cya[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_IN_CHANNEL_0 Field: cube_in_channel + if (nvdla_pdp_d_data_cube_in_channel_0_wren) begin + cube_in_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_IN_HEIGHT_0 Field: cube_in_height + if (nvdla_pdp_d_data_cube_in_height_0_wren) begin + cube_in_height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_IN_WIDTH_0 Field: cube_in_width + if (nvdla_pdp_d_data_cube_in_width_0_wren) begin + cube_in_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_OUT_CHANNEL_0 Field: cube_out_channel + if (nvdla_pdp_d_data_cube_out_channel_0_wren) begin + cube_out_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_OUT_HEIGHT_0 Field: cube_out_height + if (nvdla_pdp_d_data_cube_out_height_0_wren) begin + cube_out_height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_CUBE_OUT_WIDTH_0 Field: cube_out_width + if (nvdla_pdp_d_data_cube_out_width_0_wren) begin + cube_out_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_PDP_D_DATA_FORMAT_0 Field: input_data + if (nvdla_pdp_d_data_format_0_wren) begin + input_data[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_PDP_D_DST_BASE_ADDR_HIGH_0 Field: dst_base_addr_high + if (nvdla_pdp_d_dst_base_addr_high_0_wren) begin + dst_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DST_BASE_ADDR_LOW_0 Field: dst_base_addr_low + if (nvdla_pdp_d_dst_base_addr_low_0_wren) begin + dst_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DST_LINE_STRIDE_0 Field: dst_line_stride + if (nvdla_pdp_d_dst_line_stride_0_wren) begin + dst_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_DST_RAM_CFG_0 Field: dst_ram_type + if (nvdla_pdp_d_dst_ram_cfg_0_wren) begin + dst_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_PDP_D_DST_SURFACE_STRIDE_0 Field: dst_surface_stride + if (nvdla_pdp_d_dst_surface_stride_0_wren) begin + dst_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_PDP_D_INF_INPUT_NUM_0::inf_input_num +// Register: NVDLA_PDP_D_NAN_FLUSH_TO_ZERO_0 Field: nan_to_zero + if (nvdla_pdp_d_nan_flush_to_zero_0_wren) begin + nan_to_zero <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_D_NAN_INPUT_NUM_0::nan_input_num +// Not generating flops for read-only field NVDLA_PDP_D_NAN_OUTPUT_NUM_0::nan_output_num +// Register: NVDLA_PDP_D_OPERATION_MODE_CFG_0 Field: flying_mode + if (nvdla_pdp_d_operation_mode_cfg_0_wren) begin + flying_mode <= reg_wr_data[4]; + end +// Register: NVDLA_PDP_D_OPERATION_MODE_CFG_0 Field: pooling_method + if (nvdla_pdp_d_operation_mode_cfg_0_wren) begin + pooling_method[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_PDP_D_OPERATION_MODE_CFG_0 Field: split_num + if (nvdla_pdp_d_operation_mode_cfg_0_wren) begin + split_num[7:0] <= reg_wr_data[15:8]; + end +// Not generating flops for field NVDLA_PDP_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_first + if (nvdla_pdp_d_partial_width_in_0_wren) begin + partial_width_in_first[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_last + if (nvdla_pdp_d_partial_width_in_0_wren) begin + partial_width_in_last[9:0] <= reg_wr_data[19:10]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 Field: partial_width_in_mid + if (nvdla_pdp_d_partial_width_in_0_wren) begin + partial_width_in_mid[9:0] <= reg_wr_data[29:20]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 Field: partial_width_out_first + if (nvdla_pdp_d_partial_width_out_0_wren) begin + partial_width_out_first[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 Field: partial_width_out_last + if (nvdla_pdp_d_partial_width_out_0_wren) begin + partial_width_out_last[9:0] <= reg_wr_data[19:10]; + end +// Register: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 Field: partial_width_out_mid + if (nvdla_pdp_d_partial_width_out_0_wren) begin + partial_width_out_mid[9:0] <= reg_wr_data[29:20]; + end +// Register: NVDLA_PDP_D_PERF_ENABLE_0 Field: dma_en + if (nvdla_pdp_d_perf_enable_0_wren) begin + dma_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_D_PERF_WRITE_STALL_0::perf_write_stall +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_height + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_height[3:0] <= reg_wr_data[11:8]; + end +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_stride_height + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_stride_height[3:0] <= reg_wr_data[23:20]; + end +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_stride_width + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_stride_width[3:0] <= reg_wr_data[19:16]; + end +// Register: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 Field: kernel_width + if (nvdla_pdp_d_pooling_kernel_cfg_0_wren) begin + kernel_width[3:0] <= reg_wr_data[3:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_bottom + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_bottom[2:0] <= reg_wr_data[14:12]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_left + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_left[2:0] <= reg_wr_data[2:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_right + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_right[2:0] <= reg_wr_data[10:8]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_CFG_0 Field: pad_top + if (nvdla_pdp_d_pooling_padding_cfg_0_wren) begin + pad_top[2:0] <= reg_wr_data[6:4]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_1_CFG_0 Field: pad_value_1x + if (nvdla_pdp_d_pooling_padding_value_1_cfg_0_wren) begin + pad_value_1x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_2_CFG_0 Field: pad_value_2x + if (nvdla_pdp_d_pooling_padding_value_2_cfg_0_wren) begin + pad_value_2x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_3_CFG_0 Field: pad_value_3x + if (nvdla_pdp_d_pooling_padding_value_3_cfg_0_wren) begin + pad_value_3x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_4_CFG_0 Field: pad_value_4x + if (nvdla_pdp_d_pooling_padding_value_4_cfg_0_wren) begin + pad_value_4x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_5_CFG_0 Field: pad_value_5x + if (nvdla_pdp_d_pooling_padding_value_5_cfg_0_wren) begin + pad_value_5x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_6_CFG_0 Field: pad_value_6x + if (nvdla_pdp_d_pooling_padding_value_6_cfg_0_wren) begin + pad_value_6x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_POOLING_PADDING_VALUE_7_CFG_0 Field: pad_value_7x + if (nvdla_pdp_d_pooling_padding_value_7_cfg_0_wren) begin + pad_value_7x[18:0] <= reg_wr_data[18:0]; + end +// Register: NVDLA_PDP_D_RECIP_KERNEL_HEIGHT_0 Field: recip_kernel_height + if (nvdla_pdp_d_recip_kernel_height_0_wren) begin + recip_kernel_height[16:0] <= reg_wr_data[16:0]; + end +// Register: NVDLA_PDP_D_RECIP_KERNEL_WIDTH_0 Field: recip_kernel_width + if (nvdla_pdp_d_recip_kernel_width_0_wren) begin + recip_kernel_width[16:0] <= reg_wr_data[16:0]; + end +// Register: NVDLA_PDP_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_pdp_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_pdp_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_pdp_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_PDP_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_pdp_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hd09c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_CYA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_cya_0_out, nvdla_pdp_d_cya_0_out); + (32'hd014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_IN_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_in_channel_0_out, nvdla_pdp_d_data_cube_in_channel_0_out); + (32'hd010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_IN_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_in_height_0_out, nvdla_pdp_d_data_cube_in_height_0_out); + (32'hd00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_IN_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_in_width_0_out, nvdla_pdp_d_data_cube_in_width_0_out); + (32'hd020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_OUT_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_out_channel_0_out, nvdla_pdp_d_data_cube_out_channel_0_out); + (32'hd01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_OUT_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_out_height_0_out, nvdla_pdp_d_data_cube_out_height_0_out); + (32'hd018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_CUBE_OUT_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_cube_out_width_0_out, nvdla_pdp_d_data_cube_out_width_0_out); + (32'hd084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_data_format_0_out, nvdla_pdp_d_data_format_0_out); + (32'hd074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_base_addr_high_0_out, nvdla_pdp_d_dst_base_addr_high_0_out); + (32'hd070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_base_addr_low_0_out, nvdla_pdp_d_dst_base_addr_low_0_out); + (32'hd078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_line_stride_0_out, nvdla_pdp_d_dst_line_stride_0_out); + (32'hd080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_RAM_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_ram_cfg_0_out, nvdla_pdp_d_dst_ram_cfg_0_out); + (32'hd07c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_DST_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_dst_surface_stride_0_out, nvdla_pdp_d_dst_surface_stride_0_out); + (32'hd088 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_NAN_FLUSH_TO_ZERO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_nan_flush_to_zero_0_out, nvdla_pdp_d_nan_flush_to_zero_0_out); + (32'hd08c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd090 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_NAN_OUTPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_OPERATION_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_operation_mode_cfg_0_out, nvdla_pdp_d_operation_mode_cfg_0_out); + (32'hd008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_op_enable_0_out, nvdla_pdp_d_op_enable_0_out); + (32'hd02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_PARTIAL_WIDTH_IN_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_partial_width_in_0_out, nvdla_pdp_d_partial_width_in_0_out); + (32'hd030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_PARTIAL_WIDTH_OUT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_partial_width_out_0_out, nvdla_pdp_d_partial_width_out_0_out); + (32'hd094 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_perf_enable_0_out, nvdla_pdp_d_perf_enable_0_out); + (32'hd098 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_D_PERF_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hd034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_KERNEL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_kernel_cfg_0_out, nvdla_pdp_d_pooling_kernel_cfg_0_out); + (32'hd040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_cfg_0_out, nvdla_pdp_d_pooling_padding_cfg_0_out); + (32'hd044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_1_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_1_cfg_0_out, nvdla_pdp_d_pooling_padding_value_1_cfg_0_out); + (32'hd048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_2_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_2_cfg_0_out, nvdla_pdp_d_pooling_padding_value_2_cfg_0_out); + (32'hd04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_3_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_3_cfg_0_out, nvdla_pdp_d_pooling_padding_value_3_cfg_0_out); + (32'hd050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_4_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_4_cfg_0_out, nvdla_pdp_d_pooling_padding_value_4_cfg_0_out); + (32'hd054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_5_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_5_cfg_0_out, nvdla_pdp_d_pooling_padding_value_5_cfg_0_out); + (32'hd058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_6_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_6_cfg_0_out, nvdla_pdp_d_pooling_padding_value_6_cfg_0_out); + (32'hd05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_POOLING_PADDING_VALUE_7_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_pooling_padding_value_7_cfg_0_out, nvdla_pdp_d_pooling_padding_value_7_cfg_0_out); + (32'hd03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_RECIP_KERNEL_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_recip_kernel_height_0_out, nvdla_pdp_d_recip_kernel_height_0_out); + (32'hd038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_RECIP_KERNEL_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_recip_kernel_width_0_out, nvdla_pdp_d_recip_kernel_width_0_out); + (32'hd064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_base_addr_high_0_out, nvdla_pdp_d_src_base_addr_high_0_out); + (32'hd060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_base_addr_low_0_out, nvdla_pdp_d_src_base_addr_low_0_out); + (32'hd068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_line_stride_0_out, nvdla_pdp_d_src_line_stride_0_out); + (32'hd06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_d_src_surface_stride_0_out, nvdla_pdp_d_src_surface_stride_0_out); + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v new file mode 100644 index 0000000..b2bed5f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_REG_single.v +module NV_NVDLA_PDP_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_pdp_s_pointer_0_out; +wire [31:0] nvdla_pdp_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_s_pointer_0_wren = (reg_offset_wr == (32'hd004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_s_status_0_wren = (reg_offset_wr == (32'hd000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_pdp_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_s_pointer_0_out + or nvdla_pdp_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hd004 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_s_pointer_0_out ; + end + (32'hd000 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_PDP_S_POINTER_0::consumer +// Register: NVDLA_PDP_S_POINTER_0 Field: producer + if (nvdla_pdp_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_PDP_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hd004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_s_pointer_0_out, nvdla_pdp_s_pointer_0_out); + (32'hd000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v.vcp new file mode 100644 index 0000000..b2bed5f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_REG_single.v +module NV_NVDLA_PDP_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_pdp_s_pointer_0_out; +wire [31:0] nvdla_pdp_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_pdp_s_pointer_0_wren = (reg_offset_wr == (32'hd004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_pdp_s_status_0_wren = (reg_offset_wr == (32'hd000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_pdp_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_pdp_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_pdp_s_pointer_0_out + or nvdla_pdp_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hd004 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_s_pointer_0_out ; + end + (32'hd000 & 32'h00000fff): begin + reg_rd_data = nvdla_pdp_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_PDP_S_POINTER_0::consumer +// Register: NVDLA_PDP_S_POINTER_0 Field: producer + if (nvdla_pdp_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_PDP_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_PDP_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hd004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_PDP_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_pdp_s_pointer_0_out, nvdla_pdp_s_pointer_0_out); + (32'hd000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_PDP_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_PDP_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v new file mode 100644 index 0000000..c277a85 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v @@ -0,0 +1,1081 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_WDMA_cmd.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_cmd ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cmd_fifo_rd_prdy //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_out_channel //|< i + ,reg2dp_cube_out_height //|< i + ,reg2dp_cube_out_width //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_surface_stride //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_split_num //|< i + ,cmd_fifo_rd_pd //|> o + ,cmd_fifo_rd_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////// +//&Catenate "NV_NVDLA_PDP_wdma_ports.v"; +input [12:0] reg2dp_cube_out_channel; +input [12:0] reg2dp_cube_out_height; +input [12:0] reg2dp_cube_out_width; +input [31:0] reg2dp_dst_base_addr_high; +input [31:0] reg2dp_dst_base_addr_low; +input [31:0] reg2dp_dst_line_stride; +input [31:0] reg2dp_dst_surface_stride; +//input [1:0] reg2dp_input_data; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [7:0] reg2dp_split_num; +input cmd_fifo_rd_prdy; +output [79:0] cmd_fifo_rd_pd; +output cmd_fifo_rd_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +//////////////////////////////////////////////////////////////////////// +reg [63:0] base_addr_line; +reg [63:0] base_addr_split; +reg [63:0] base_addr_surf; +//reg cfg_do_int16; +//reg cfg_do_int8; +reg [12:0] count_h; +reg [7:0] count_wg; +reg mon_base_addr_line_c; +reg mon_base_addr_split_c; +reg mon_base_addr_surf_c; +reg op_prcess; +//reg [14:0] size_of_byte_in_c; +wire [63:0] cfg_base_addr; +wire cfg_mode_split; +wire cmd_fifo_wr_accpet; +wire [79:0] cmd_fifo_wr_pd; +wire cmd_fifo_wr_prdy; +wire cmd_fifo_wr_pvld; +//wire [13:0] cube_out_channel_use; +wire is_cube_end; +wire is_first_wg; +wire is_fspt; +wire is_last_h; +wire is_last_surf; +wire is_last_wg; +wire is_line_end; +wire is_lspt; +wire is_mspt; +wire is_split_end; +wire is_surf_end; +//wire mon_size_of_surf; +wire op_done; +//wire [1:0] size_of_b; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print "reg [12-${k}:0] count_surf; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [12-3:0] count_surf; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [9:0] size_of_surf; +//wire [10:0] size_of_surf_use; +wire [12:0] size_of_width; +wire [9:0] split_size_of_width; +wire [18:0] splitw_stride; +wire [63:0] spt_cmd_addr; +wire spt_cmd_cube_end; +//wire [1:0] spt_cmd_lenb; +wire [12:0] spt_cmd_size; +//////////////////////////////////////////////////////////////////////// +assign op_done = op_prcess & cmd_fifo_wr_prdy & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_prcess <= 1'b0; + end else begin + if (op_load) begin + op_prcess <= 1'b1; + end else if (op_done) begin + op_prcess <= 1'b0; + end + end +end +assign cmd_fifo_wr_pvld = op_prcess; +assign cmd_fifo_wr_accpet = cmd_fifo_wr_pvld & cmd_fifo_wr_prdy; +// SPLIT MODE +assign cfg_mode_split = (reg2dp_split_num!=0); +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int8 <= 1'b0; +// end else begin +// cfg_do_int8 <= reg2dp_input_data== 0; +// end +//end +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int16 <= 1'b0; +// end else begin +// cfg_do_int16 <= reg2dp_input_data== 2'h1; +// end +//end +assign cfg_base_addr = {reg2dp_dst_base_addr_high,reg2dp_dst_base_addr_low}; +//============== +// CUBE DRAW +//============== +assign is_line_end = 1'b1; +assign is_surf_end = is_line_end & is_last_h; +assign is_split_end = is_surf_end & is_last_surf; +assign is_cube_end = is_split_end & is_last_wg; +// WIDTH COUNT: in width direction, indidate one block +assign split_size_of_width = is_fspt ? reg2dp_partial_width_out_first : + is_lspt ? reg2dp_partial_width_out_last : + is_mspt ? reg2dp_partial_width_out_mid : {10{`x_or_0}}; +assign size_of_width = cfg_mode_split ? {3'd0,split_size_of_width} : reg2dp_cube_out_width; +//assign splitw_stride = (size_of_width+1)<<5; +//: my $atmm_bw = int( log(8)/log(2) ); +//: print "assign splitw_stride = (size_of_width+1)<<${atmm_bw}; "; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign splitw_stride = (size_of_width+1)<<3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +// WG: WidthGroup, including one FSPT, one LSPT, and many MSPT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_wg <= {8{1'b0}}; + end else begin + if (op_load) begin + count_wg <= 0; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + count_wg <= count_wg + 1; + end + end + end +end +assign is_last_wg = (count_wg==reg2dp_split_num); +assign is_first_wg = (count_wg==0); +assign is_fspt = cfg_mode_split & is_first_wg; +assign is_lspt = cfg_mode_split & is_last_wg; +assign is_mspt = cfg_mode_split & !is_fspt & !is_lspt; +//============== +// C direction: count_b + count_surf +// count_b: in each W in line, will go 4 step in c first +// count_surf: when one surf with 4c is done, will go to next surf +//============== +// assign cube_out_channel_use[13:0] = reg2dp_cube_out_channel[12:0] + 1'b1; +// always @(*) begin +// if (cfg_do_int8) begin +// size_of_byte_in_c = {1'b0,cube_out_channel_use}; +// end else if (cfg_do_int16) begin +// size_of_byte_in_c = {cube_out_channel_use,1'b0}; +// end else begin +// size_of_byte_in_c = {cube_out_channel_use,1'b0}; +// end +// end +// assign size_of_surf_use[10:0] = size_of_byte_in_c[14:5] + (|size_of_byte_in_c[4:0]); // include the last unaligned channels +// assign {mon_size_of_surf,size_of_surf[9:0]} = size_of_surf_use - 1'b1; +// assign size_of_b = 2'd3; +//============== +// COUNT SURF +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_surf <= {10{1'b0}}; + end else begin + if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + count_surf <= 0; + end else if (is_surf_end) begin + count_surf <= count_surf + 1; + end + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign is_last_surf = (count_surf== reg2dp_cube_out_channel[12:${k}]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign is_last_surf = (count_surf== reg2dp_cube_out_channel[12:3]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// per Surf +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_fifo_wr_accpet) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_cube_out_height); +//============== +// ADDR +//============== +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {64{1'b0}}; + {mon_base_addr_line_c,base_addr_line} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_line <= cfg_base_addr; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_split + splitw_stride; + end else if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + reg2dp_dst_surface_stride; + end else if (is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + reg2dp_dst_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_WDMA: no overflow is allowed") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_surf <= {64{1'b0}}; + {mon_base_addr_surf_c,base_addr_surf} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_surf <= cfg_base_addr; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_split + splitw_stride; + end else if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + reg2dp_dst_surface_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_WDMA: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SPLIT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_split <= {64{1'b0}}; + {mon_base_addr_split_c,base_addr_split} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_split <= cfg_base_addr; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + {mon_base_addr_split_c,base_addr_split} <= base_addr_split + splitw_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_WDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_split_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// CMD FIFO WRITE +//============== +NV_NVDLA_PDP_WDMA_CMD_fifo u_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_fifo_wr_prdy (cmd_fifo_wr_prdy) //|> w + ,.cmd_fifo_wr_pvld (cmd_fifo_wr_pvld) //|< w + ,.cmd_fifo_wr_pd (cmd_fifo_wr_pd[79:0]) //|< w + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) //|< i + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) //|> o + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[79:0]) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//============== +// DMA Req : ADDR : Generation +//============== +assign spt_cmd_addr = base_addr_line; +assign spt_cmd_size = size_of_width; +//assign spt_cmd_lenb = size_of_b; +assign spt_cmd_cube_end = is_cube_end; +// PKT_PACK_WIRE( pdp_wdma_cmd , spt_cmd_ , cmd_fifo_wr_pd ) +assign cmd_fifo_wr_pd[63:0] = spt_cmd_addr[63:0]; +assign cmd_fifo_wr_pd[76:64] = spt_cmd_size[12:0]; +assign cmd_fifo_wr_pd[78:77] = 0;//spt_cmd_lenb[1:0]; +assign cmd_fifo_wr_pd[79] = spt_cmd_cube_end ; +endmodule // NV_NVDLA_PDP_WDMA_cmd +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_WDMA_CMD_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus cmd_fifo_wr -rd_pipebus cmd_fifo_rd -d 1 -wr_reg -ram_bypass -w 80 -ram ff -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_CMD_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , cmd_fifo_wr_prdy + , cmd_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , cmd_fifo_wr_pause +`endif + , cmd_fifo_wr_pd + , cmd_fifo_rd_prdy + , cmd_fifo_rd_pvld + , cmd_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cmd_fifo_wr_prdy; +input cmd_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input cmd_fifo_wr_pause; +`endif +input [79:0] cmd_fifo_wr_pd; +input cmd_fifo_rd_prdy; +output cmd_fifo_rd_pvld; +output [79:0] cmd_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cmd_fifo_wr_pvld_in; // registered cmd_fifo_wr_pvld +reg wr_busy_in; // inputs being held this cycle? +assign cmd_fifo_wr_prdy = !wr_busy_in; +wire cmd_fifo_wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant cmd_fifo_wr_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = cmd_fifo_wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (cmd_fifo_wr_pvld_in && cmd_fifo_wr_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (cmd_fifo_wr_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || cmd_fifo_wr_pause ; +`else +wire wr_busy_in_next = (cmd_fifo_wr_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + cmd_fifo_wr_pvld_in <= cmd_fifo_wr_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + cmd_fifo_wr_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg cmd_fifo_wr_busy_int; // copy for internal use +assign wr_reserving = cmd_fifo_wr_pvld_in && !cmd_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg cmd_fifo_wr_count; // write-side count +wire wr_count_next_wr_popping = wr_reserving ? cmd_fifo_wr_count : (cmd_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire wr_count_next_no_wr_popping = wr_reserving ? (cmd_fifo_wr_count + 1'd1) : cmd_fifo_wr_count; // spyglass disable W164a W484 +wire wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_1 = ( wr_count_next_no_wr_popping == 1'd1 ); +wire wr_count_next_is_1 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_1; +wire wr_limit_muxed; // muxed with simulation/emulation overrides +wire wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign cmd_fifo_wr_busy_next = wr_count_next_is_1 || // busy next cycle? + (wr_limit_reg != 1'd0 && // check cmd_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = cmd_fifo_wr_pvld_in && cmd_fifo_wr_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_busy_int <= 1'b0; + cmd_fifo_wr_count <= 1'd0; + end else begin + cmd_fifo_wr_busy_int <= cmd_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + cmd_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + cmd_fifo_wr_count <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as cmd_fifo_wr_pvld_in +// +// RAM +// +wire rd_popping; +wire ram_we = wr_pushing && (cmd_fifo_wr_count > 1'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && cmd_fifo_wr_pvld; +wire [79:0] cmd_fifo_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( cmd_fifo_wr_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .ra ( (cmd_fifo_wr_count == 0) ? 1'd1 : 1'b0 ) + , .dout ( cmd_fifo_rd_pd ) + ); +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd_fifo_rd_pvld; // data out of fifo is valid +assign rd_popping = cmd_fifo_rd_pvld && cmd_fifo_rd_prdy; +reg cmd_fifo_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire rd_count_next_rd_popping = rd_pushing ? cmd_fifo_rd_count : + (cmd_fifo_rd_count - 1'd1); +wire rd_count_next_no_rd_popping = rd_pushing ? (cmd_fifo_rd_count + 1'd1) : + cmd_fifo_rd_count; +// spyglass enable_block W164a W484 +wire rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd_fifo_rd_pvld = cmd_fifo_rd_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_count <= 1'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd_fifo_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd_fifo_rd_count <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cmd_fifo_wr_pvld_in && !cmd_fifo_wr_busy_int) || (cmd_fifo_wr_busy_int != cmd_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (cmd_fifo_rd_pvld && cmd_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit : 1'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 1'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 1'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 1'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 1'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cmd_fifo_wr_pvld && !(!cmd_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {31'd0, (wr_limit_reg == 1'd0) ? 1'd1 : wr_limit_reg} ) + , .curr ( {31'd0, cmd_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_WDMA_CMD_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_PDP_WDMA_CMD_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [79:0] di; +input iwe; +input we; +input [0:0] ra; +output [79:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [79:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +reg [79:0] ram_ff0; +always @( posedge clk_mgated ) begin + if ( we ) begin + ram_ff0 <= di_d; + end +end +reg [79:0] dout; +always @(*) begin + case( ra ) + 1'd0: dout = ram_ff0; + 1'd1: dout = di_d; +//VCS coverage off + default: dout = {80{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule // NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80 diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v.vcp new file mode 100644 index 0000000..6b08419 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v.vcp @@ -0,0 +1,1069 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_WDMA_cmd.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_cmd ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cmd_fifo_rd_prdy //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_out_channel //|< i + ,reg2dp_cube_out_height //|< i + ,reg2dp_cube_out_width //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_surface_stride //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_split_num //|< i + ,cmd_fifo_rd_pd //|> o + ,cmd_fifo_rd_pvld //|> o + ); +//////////////////////////////////////////////////////////////////////// +//&Catenate "NV_NVDLA_PDP_wdma_ports.v"; +input [12:0] reg2dp_cube_out_channel; +input [12:0] reg2dp_cube_out_height; +input [12:0] reg2dp_cube_out_width; +input [31:0] reg2dp_dst_base_addr_high; +input [31:0] reg2dp_dst_base_addr_low; +input [31:0] reg2dp_dst_line_stride; +input [31:0] reg2dp_dst_surface_stride; +//input [1:0] reg2dp_input_data; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [7:0] reg2dp_split_num; +input cmd_fifo_rd_prdy; +output [79:0] cmd_fifo_rd_pd; +output cmd_fifo_rd_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +//////////////////////////////////////////////////////////////////////// +reg [63:0] base_addr_line; +reg [63:0] base_addr_split; +reg [63:0] base_addr_surf; +//reg cfg_do_int16; +//reg cfg_do_int8; +reg [12:0] count_h; +reg [7:0] count_wg; +reg mon_base_addr_line_c; +reg mon_base_addr_split_c; +reg mon_base_addr_surf_c; +reg op_prcess; +//reg [14:0] size_of_byte_in_c; +wire [63:0] cfg_base_addr; +wire cfg_mode_split; +wire cmd_fifo_wr_accpet; +wire [79:0] cmd_fifo_wr_pd; +wire cmd_fifo_wr_prdy; +wire cmd_fifo_wr_pvld; +//wire [13:0] cube_out_channel_use; +wire is_cube_end; +wire is_first_wg; +wire is_fspt; +wire is_last_h; +wire is_last_surf; +wire is_last_wg; +wire is_line_end; +wire is_lspt; +wire is_mspt; +wire is_split_end; +wire is_surf_end; +//wire mon_size_of_surf; +wire op_done; +//wire [1:0] size_of_b; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print "reg [12-${k}:0] count_surf; \n"; +//wire [9:0] size_of_surf; +//wire [10:0] size_of_surf_use; +wire [12:0] size_of_width; +wire [9:0] split_size_of_width; +wire [18:0] splitw_stride; +wire [63:0] spt_cmd_addr; +wire spt_cmd_cube_end; +//wire [1:0] spt_cmd_lenb; +wire [12:0] spt_cmd_size; +//////////////////////////////////////////////////////////////////////// +assign op_done = op_prcess & cmd_fifo_wr_prdy & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_prcess <= 1'b0; + end else begin + if (op_load) begin + op_prcess <= 1'b1; + end else if (op_done) begin + op_prcess <= 1'b0; + end + end +end +assign cmd_fifo_wr_pvld = op_prcess; +assign cmd_fifo_wr_accpet = cmd_fifo_wr_pvld & cmd_fifo_wr_prdy; +// SPLIT MODE +assign cfg_mode_split = (reg2dp_split_num!=0); +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int8 <= 1'b0; +// end else begin +// cfg_do_int8 <= reg2dp_input_data== 0; +// end +//end +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int16 <= 1'b0; +// end else begin +// cfg_do_int16 <= reg2dp_input_data== 2'h1; +// end +//end +assign cfg_base_addr = {reg2dp_dst_base_addr_high,reg2dp_dst_base_addr_low}; +//============== +// CUBE DRAW +//============== +assign is_line_end = 1'b1; +assign is_surf_end = is_line_end & is_last_h; +assign is_split_end = is_surf_end & is_last_surf; +assign is_cube_end = is_split_end & is_last_wg; +// WIDTH COUNT: in width direction, indidate one block +assign split_size_of_width = is_fspt ? reg2dp_partial_width_out_first : + is_lspt ? reg2dp_partial_width_out_last : + is_mspt ? reg2dp_partial_width_out_mid : {10{`x_or_0}}; +assign size_of_width = cfg_mode_split ? {3'd0,split_size_of_width} : reg2dp_cube_out_width; +//assign splitw_stride = (size_of_width+1)<<5; +//: my $atmm_bw = int( log(8)/log(2) ); +//: print "assign splitw_stride = (size_of_width+1)<<${atmm_bw}; "; +// WG: WidthGroup, including one FSPT, one LSPT, and many MSPT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_wg <= {8{1'b0}}; + end else begin + if (op_load) begin + count_wg <= 0; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + count_wg <= count_wg + 1; + end + end + end +end +assign is_last_wg = (count_wg==reg2dp_split_num); +assign is_first_wg = (count_wg==0); +assign is_fspt = cfg_mode_split & is_first_wg; +assign is_lspt = cfg_mode_split & is_last_wg; +assign is_mspt = cfg_mode_split & !is_fspt & !is_lspt; +//============== +// C direction: count_b + count_surf +// count_b: in each W in line, will go 4 step in c first +// count_surf: when one surf with 4c is done, will go to next surf +//============== +// assign cube_out_channel_use[13:0] = reg2dp_cube_out_channel[12:0] + 1'b1; +// always @(*) begin +// if (cfg_do_int8) begin +// size_of_byte_in_c = {1'b0,cube_out_channel_use}; +// end else if (cfg_do_int16) begin +// size_of_byte_in_c = {cube_out_channel_use,1'b0}; +// end else begin +// size_of_byte_in_c = {cube_out_channel_use,1'b0}; +// end +// end +// assign size_of_surf_use[10:0] = size_of_byte_in_c[14:5] + (|size_of_byte_in_c[4:0]); // include the last unaligned channels +// assign {mon_size_of_surf,size_of_surf[9:0]} = size_of_surf_use - 1'b1; +// assign size_of_b = 2'd3; +//============== +// COUNT SURF +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_surf <= {10{1'b0}}; + end else begin + if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + count_surf <= 0; + end else if (is_surf_end) begin + count_surf <= count_surf + 1; + end + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign is_last_surf = (count_surf== reg2dp_cube_out_channel[12:${k}]); +//: ); +// per Surf +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_fifo_wr_accpet) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_cube_out_height); +//============== +// ADDR +//============== +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {64{1'b0}}; + {mon_base_addr_line_c,base_addr_line} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_line <= cfg_base_addr; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_split + splitw_stride; + end else if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + reg2dp_dst_surface_stride; + end else if (is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + reg2dp_dst_line_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_WDMA: no overflow is allowed") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_surf <= {64{1'b0}}; + {mon_base_addr_surf_c,base_addr_surf} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_surf <= cfg_base_addr; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_split + splitw_stride; + end else if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + reg2dp_dst_surface_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_WDMA: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SPLIT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_split <= {64{1'b0}}; + {mon_base_addr_split_c,base_addr_split} <= {65{1'b0}}; + end else begin + if (op_load) begin + base_addr_split <= cfg_base_addr; + end else if (cmd_fifo_wr_accpet) begin + if (is_split_end) begin + {mon_base_addr_split_c,base_addr_split} <= base_addr_split + splitw_stride; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP_WDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_split_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// CMD FIFO WRITE +//============== +NV_NVDLA_PDP_WDMA_CMD_fifo u_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_fifo_wr_prdy (cmd_fifo_wr_prdy) //|> w + ,.cmd_fifo_wr_pvld (cmd_fifo_wr_pvld) //|< w + ,.cmd_fifo_wr_pd (cmd_fifo_wr_pd[79:0]) //|< w + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) //|< i + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) //|> o + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[79:0]) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//============== +// DMA Req : ADDR : Generation +//============== +assign spt_cmd_addr = base_addr_line; +assign spt_cmd_size = size_of_width; +//assign spt_cmd_lenb = size_of_b; +assign spt_cmd_cube_end = is_cube_end; +// PKT_PACK_WIRE( pdp_wdma_cmd , spt_cmd_ , cmd_fifo_wr_pd ) +assign cmd_fifo_wr_pd[63:0] = spt_cmd_addr[63:0]; +assign cmd_fifo_wr_pd[76:64] = spt_cmd_size[12:0]; +assign cmd_fifo_wr_pd[78:77] = 0;//spt_cmd_lenb[1:0]; +assign cmd_fifo_wr_pd[79] = spt_cmd_cube_end ; +endmodule // NV_NVDLA_PDP_WDMA_cmd +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_WDMA_CMD_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus cmd_fifo_wr -rd_pipebus cmd_fifo_rd -d 1 -wr_reg -ram_bypass -w 80 -ram ff -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_CMD_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , cmd_fifo_wr_prdy + , cmd_fifo_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , cmd_fifo_wr_pause +`endif + , cmd_fifo_wr_pd + , cmd_fifo_rd_prdy + , cmd_fifo_rd_pvld + , cmd_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output cmd_fifo_wr_prdy; +input cmd_fifo_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input cmd_fifo_wr_pause; +`endif +input [79:0] cmd_fifo_wr_pd; +input cmd_fifo_rd_prdy; +output cmd_fifo_rd_pvld; +output [79:0] cmd_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg cmd_fifo_wr_pvld_in; // registered cmd_fifo_wr_pvld +reg wr_busy_in; // inputs being held this cycle? +assign cmd_fifo_wr_prdy = !wr_busy_in; +wire cmd_fifo_wr_busy_next; // fwd: fifo busy next? +// factor for better timing with distant cmd_fifo_wr_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = cmd_fifo_wr_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (cmd_fifo_wr_pvld_in && cmd_fifo_wr_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (cmd_fifo_wr_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || cmd_fifo_wr_pause ; +`else +wire wr_busy_in_next = (cmd_fifo_wr_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + cmd_fifo_wr_pvld_in <= cmd_fifo_wr_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + cmd_fifo_wr_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg cmd_fifo_wr_busy_int; // copy for internal use +assign wr_reserving = cmd_fifo_wr_pvld_in && !cmd_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg cmd_fifo_wr_count; // write-side count +wire wr_count_next_wr_popping = wr_reserving ? cmd_fifo_wr_count : (cmd_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire wr_count_next_no_wr_popping = wr_reserving ? (cmd_fifo_wr_count + 1'd1) : cmd_fifo_wr_count; // spyglass disable W164a W484 +wire wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_1 = ( wr_count_next_no_wr_popping == 1'd1 ); +wire wr_count_next_is_1 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_1; +wire wr_limit_muxed; // muxed with simulation/emulation overrides +wire wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign cmd_fifo_wr_busy_next = wr_count_next_is_1 || // busy next cycle? + (wr_limit_reg != 1'd0 && // check cmd_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = cmd_fifo_wr_pvld_in && cmd_fifo_wr_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_wr_busy_int <= 1'b0; + cmd_fifo_wr_count <= 1'd0; + end else begin + cmd_fifo_wr_busy_int <= cmd_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + cmd_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + cmd_fifo_wr_count <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as cmd_fifo_wr_pvld_in +// +// RAM +// +wire rd_popping; +wire ram_we = wr_pushing && (cmd_fifo_wr_count > 1'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && cmd_fifo_wr_pvld; +wire [79:0] cmd_fifo_rd_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( cmd_fifo_wr_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .ra ( (cmd_fifo_wr_count == 0) ? 1'd1 : 1'b0 ) + , .dout ( cmd_fifo_rd_pd ) + ); +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd_fifo_rd_pvld; // data out of fifo is valid +assign rd_popping = cmd_fifo_rd_pvld && cmd_fifo_rd_prdy; +reg cmd_fifo_rd_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire rd_count_next_rd_popping = rd_pushing ? cmd_fifo_rd_count : + (cmd_fifo_rd_count - 1'd1); +wire rd_count_next_no_rd_popping = rd_pushing ? (cmd_fifo_rd_count + 1'd1) : + cmd_fifo_rd_count; +// spyglass enable_block W164a W484 +wire rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd_fifo_rd_pvld = cmd_fifo_rd_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd_fifo_rd_count <= 1'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd_fifo_rd_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd_fifo_rd_count <= {1{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (cmd_fifo_wr_pvld_in && !cmd_fifo_wr_busy_int) || (cmd_fifo_wr_busy_int != cmd_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (cmd_fifo_rd_pvld && cmd_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit : 1'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 1'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 1'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 1'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 1'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_PDP_WDMA_CMD_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( cmd_fifo_wr_pvld && !(!cmd_fifo_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {31'd0, (wr_limit_reg == 1'd0) ? 1'd1 : wr_limit_reg} ) + , .curr ( {31'd0, cmd_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_WDMA_CMD_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_PDP_WDMA_CMD_fifo +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [79:0] di; +input iwe; +input we; +input [0:0] ra; +output [79:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [79:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +reg [79:0] ram_ff0; +always @( posedge clk_mgated ) begin + if ( we ) begin + ram_ff0 <= di_d; + end +end +reg [79:0] dout; +always @(*) begin + case( ra ) + 1'd0: dout = ram_ff0; + 1'd1: dout = di_d; +//VCS coverage off + default: dout = {80{`x_or_0}}; +//VCS coverage on + endcase +end +endmodule // NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80 diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v new file mode 100644 index 0000000..cb4f31a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v @@ -0,0 +1,1231 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_WDMA_dat.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_dat ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2wdma_pd //|< i + ,dp2wdma_vld //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_out_channel //|< i + ,reg2dp_cube_out_height //|< i + ,reg2dp_cube_out_width //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_split_num //|< i + ,wdma_done //|< i +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: ,dat${posw}_fifo${posb}_rd_pd +//: ,dat${posw}_fifo${posb}_rd_prdy +//: ,dat${posw}_fifo${posb}_rd_pvld +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,dat0_fifo0_rd_pd +,dat0_fifo0_rd_prdy +,dat0_fifo0_rd_pvld + +,dat0_fifo1_rd_pd +,dat0_fifo1_rd_prdy +,dat0_fifo1_rd_pvld + +,dat0_fifo2_rd_pd +,dat0_fifo2_rd_prdy +,dat0_fifo2_rd_pvld + +,dat0_fifo3_rd_pd +,dat0_fifo3_rd_prdy +,dat0_fifo3_rd_pvld + +,dat0_fifo4_rd_pd +,dat0_fifo4_rd_prdy +,dat0_fifo4_rd_pvld + +,dat0_fifo5_rd_pd +,dat0_fifo5_rd_prdy +,dat0_fifo5_rd_pvld + +,dat0_fifo6_rd_pd +,dat0_fifo6_rd_prdy +,dat0_fifo6_rd_pvld + +,dat0_fifo7_rd_pd +,dat0_fifo7_rd_prdy +,dat0_fifo7_rd_pvld + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,dp2wdma_rdy //|> o + ); +///////////////////////////////////////////////////////////////////// +//&Catenate "NV_NVDLA_PDP_wdma_ports.v"; +input [12:0] reg2dp_cube_out_channel; +input [12:0] reg2dp_cube_out_height; +input [12:0] reg2dp_cube_out_width; +//input [1:0] reg2dp_input_data; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [7:0] reg2dp_split_num; +input [1*8 -1:0] dp2wdma_pd; +input dp2wdma_vld; +output dp2wdma_rdy; +//&Ports /^spt/; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: output [$pdpbw-1:0] dat${posw}_fifo${posb}_rd_pd; +//: input dat${posw}_fifo${posb}_rd_prdy; +//: output dat${posw}_fifo${posb}_rd_pvld; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8-1:0] dat0_fifo0_rd_pd; +input dat0_fifo0_rd_prdy; +output dat0_fifo0_rd_pvld; + +output [8-1:0] dat0_fifo1_rd_pd; +input dat0_fifo1_rd_prdy; +output dat0_fifo1_rd_pvld; + +output [8-1:0] dat0_fifo2_rd_pd; +input dat0_fifo2_rd_prdy; +output dat0_fifo2_rd_pvld; + +output [8-1:0] dat0_fifo3_rd_pd; +input dat0_fifo3_rd_prdy; +output dat0_fifo3_rd_pvld; + +output [8-1:0] dat0_fifo4_rd_pd; +input dat0_fifo4_rd_prdy; +output dat0_fifo4_rd_pvld; + +output [8-1:0] dat0_fifo5_rd_pd; +input dat0_fifo5_rd_prdy; +output dat0_fifo5_rd_pvld; + +output [8-1:0] dat0_fifo6_rd_pd; +input dat0_fifo6_rd_prdy; +output dat0_fifo6_rd_pvld; + +output [8-1:0] dat0_fifo7_rd_pd; +input dat0_fifo7_rd_prdy; +output dat0_fifo7_rd_pvld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input wdma_done; +input op_load; +////////////////////////////////////////////////////////////////// +//reg cfg_do_fp16; +//reg cfg_do_int16; +//reg cfg_do_int8; +reg [4:0] count_b; +reg [12:0] count_h; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print "reg [12-${k}:0] count_surf; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [12-3:0] count_surf; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [12:0] count_w; +reg [7:0] count_wg; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +//reg [31:0] nan_out_num; +//reg [31:0] nan_output_num; +wire cfg_mode_split; +wire dat_fifo_wr_prdy; +wire dat_fifo_wr_pvld; +//wire [3:0] dat_is_nan; +wire [1*8 -1:0] dp2wdma_dat_pd; +//wire [15:0] fp16_in_pd_0; +//wire [15:0] fp16_in_pd_1; +//wire [15:0] fp16_in_pd_2; +//wire [15:0] fp16_in_pd_3; +wire is_blk_end; +wire is_cube_end; +wire is_first_wg; +wire is_fspt; +wire is_last_b; +wire is_last_h; +wire is_last_surf; +wire is_last_w; +wire is_last_wg; +wire is_line_end; +wire is_lspt; +wire is_mspt; +wire is_split_end; +wire is_surf_end; +//wire mon_size_of_surf; +//wire [2:0] nan_num_in_8byte; +//wire [1:0] nan_num_in_8byte_0; +//wire [1:0] nan_num_in_8byte_1; +wire [12:0] size_of_width; +wire [9:0] split_size_of_width; +wire spt_dat_accept; +//wire [1:0] spt_posb; +wire [4:0] spt_posb; +wire [1:0] spt_posw; +//wire wdma_loadin; +//////////////////////////////////////////////////////////////////////// +assign cfg_mode_split = (reg2dp_split_num!=0); +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int8 <= 1'b0; +// end else begin +// cfg_do_int8 <= reg2dp_input_data== 0; +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int16 <= 1'b0; +// end else begin +// cfg_do_int16 <= reg2dp_input_data== 2'h1; +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_fp16 <= 1'b0; +// end else begin +// cfg_do_fp16 <= reg2dp_input_data== 2'h2; +// end +// end +// +// //============== +// //NaN counter +// //============== +// assign wdma_loadin = spt_dat_accept;//dp2wdma_vld & dp2wdma_rdy; +// assign fp16_in_pd_0 = dp2wdma_pd[15:0]; +// assign fp16_in_pd_1 = dp2wdma_pd[31:16]; +// assign fp16_in_pd_2 = dp2wdma_pd[47:32]; +// assign fp16_in_pd_3 = dp2wdma_pd[63:48]; +// assign dat_is_nan[0] = cfg_do_fp16 & (&fp16_in_pd_0[14:10]) & (|fp16_in_pd_0[9:0]); +// assign dat_is_nan[1] = cfg_do_fp16 & (&fp16_in_pd_1[14:10]) & (|fp16_in_pd_1[9:0]); +// assign dat_is_nan[2] = cfg_do_fp16 & (&fp16_in_pd_2[14:10]) & (|fp16_in_pd_2[9:0]); +// assign dat_is_nan[3] = cfg_do_fp16 & (&fp16_in_pd_3[14:10]) & (|fp16_in_pd_3[9:0]); +// +// assign nan_num_in_8byte_0[1:0] = dat_is_nan[0] + dat_is_nan[1]; +// assign nan_num_in_8byte_1[1:0] = dat_is_nan[2] + dat_is_nan[3]; +// assign nan_num_in_8byte[2:0] = nan_num_in_8byte_0 + nan_num_in_8byte_1; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(wdma_loadin) begin +// if(is_cube_end) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte; +// end +// end +// end +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass disable_block NoWidthInBasedNum-ML +// // spyglass disable_block STARC-2.10.3.2a +// // spyglass disable_block STARC05-2.1.3.1 +// // spyglass disable_block STARC-2.1.4.6 +// // spyglass disable_block W116 +// // spyglass disable_block W154 +// // spyglass disable_block W239 +// // spyglass disable_block W362 +// // spyglass disable_block WRN_58 +// // spyglass disable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +// `ifdef ASSERT_ON +// `ifdef FV_ASSERT_ON +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef SYNTHESIS +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef ASSERT_OFF_RESET_IS_X +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +// `else +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +// `endif // ASSERT_OFF_RESET_IS_X +// `endif // SYNTHESIS +// `endif // FV_ASSERT_ON +// // VCS coverage off +// nv_assert_never #(0,0,"PDP WDMA: no overflow is allowed") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mon_nan_in_count); // spyglass disable W504 SelfDeterminedExpr-ML +// // VCS coverage on +// `undef ASSERT_RESET +// `endif // ASSERT_ON +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass enable_block NoWidthInBasedNum-ML +// // spyglass enable_block STARC-2.10.3.2a +// // spyglass enable_block STARC05-2.1.3.1 +// // spyglass enable_block STARC-2.1.4.6 +// // spyglass enable_block W116 +// // spyglass enable_block W154 +// // spyglass enable_block W239 +// // spyglass enable_block W362 +// // spyglass enable_block WRN_58 +// // spyglass enable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_out_num <= {32{1'b0}}; +// end else begin +// if(is_cube_end) +// nan_out_num <= nan_in_count; +// end +// end +// //assign wdma_done = dp2reg_done; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_output_num <= {32{1'b0}}; +// end else begin +// if(wdma_done) begin +// nan_output_num <= nan_out_num; +// end +// end +// end +// +//============== +// CUBE DRAW +//============== +assign is_blk_end = is_last_b; +assign is_line_end = is_blk_end & is_last_w; +assign is_surf_end = is_line_end & is_last_h; +assign is_split_end = is_surf_end & is_last_surf; +assign is_cube_end = is_split_end & is_last_wg; +// WIDTH COUNT: in width direction, indidate one block +assign split_size_of_width = is_fspt ? reg2dp_partial_width_out_first : + is_lspt ? reg2dp_partial_width_out_last : + is_mspt ? reg2dp_partial_width_out_mid : {10{`x_or_0}}; +assign size_of_width = cfg_mode_split ? {3'd0,split_size_of_width} : reg2dp_cube_out_width; +// WG: WidthGroup, including one FSPT, one LSPT, and many MSPT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_wg <= {8{1'b0}}; + end else begin + if (op_load) begin + count_wg <= 0; + end else if (spt_dat_accept) begin + if (is_cube_end) begin + count_wg <= 0; + end else if (is_split_end) begin + count_wg <= count_wg + 1; + end + end + end +end +assign is_last_wg = (count_wg==reg2dp_split_num); +assign is_first_wg = (count_wg==0); +assign is_fspt = cfg_mode_split & is_first_wg; +assign is_lspt = cfg_mode_split & is_last_wg; +assign is_mspt = cfg_mode_split & !is_fspt & !is_lspt; +//================================================================ +// C direction: count_b + count_surf +// count_b: in each W in line, will go 4 step in c first +// count_surf: when one surf with 4c is done, will go to next surf +//================================================================ +//============== +// COUNT B +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_b <= {5{1'b0}}; + end else begin + if (spt_dat_accept) begin + if (is_blk_end) begin + count_b <= 0; + end else begin + count_b <= count_b + 1; + end + end + end +end +//: my $atomicm = 8; +//: my $pdpth = 1; +//: my $k = int( $atomicm/$pdpth ); +//: print "assign is_last_b = (count_b==5'd${k} -1 ); \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign is_last_b = (count_b==5'd8 -1 ); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// COUNT W +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {13{1'b0}}; + end else begin + if (spt_dat_accept) begin + if (is_line_end) begin + count_w <= 0; + end else if (is_blk_end) begin + count_w <= count_w + 1; + end + end + end +end +assign is_last_w = (count_w==size_of_width); +//============== +// COUNT SURF +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_surf <= 0; + end else begin + if (spt_dat_accept) begin + if (is_split_end) begin + count_surf <= 0; + end else if (is_surf_end) begin + count_surf <= count_surf + 1; + end + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign is_last_surf = (count_surf== reg2dp_cube_out_channel[12:${k}]); +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign is_last_surf = (count_surf== reg2dp_cube_out_channel[12:3]); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// COUNT HEIGHT +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (spt_dat_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_cube_out_height); +//============== +// spt information gen +//============== +assign spt_posb = count_b; +//: my $Wnum = 64/8/8; +//: if($Wnum == 1) { +//: print qq( +//: assign spt_posw = 2'b0; +//: ); +//: } else { +//: my $k = int( log($Wnum)/log(2) ); +//: print qq( +//: assign spt_posw = {{(2-$k){1'b0}},count_w[$k-1:0]}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign spt_posw = 2'b0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// Data FIFO WRITE contrl +//============== +assign dp2wdma_dat_pd = dp2wdma_pd; +assign dat_fifo_wr_pvld = dp2wdma_vld; +assign dp2wdma_rdy = dat_fifo_wr_prdy; +//: my @dat_wr_rdys; +//: my @dat_wr_accepts; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: wire [$pdpbw-1:0] dat${posw}_fifo${posb}_wr_pd; +//: wire dat${posw}_fifo${posb}_wr_prdy; +//: wire dat${posw}_fifo${posb}_wr_pvld; +//: // DATA FIFO WRITE SIDE +//: // is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +//: assign dat${posw}_fifo${posb}_wr_pvld = dat_fifo_wr_pvld & (spt_posw==$posw) & (spt_posb == $posb); +//: assign dat${posw}_fifo${posb}_wr_pd = dp2wdma_dat_pd; +//: +//: // DATA FIFO INSTANCE +//: NV_NVDLA_PDP_WDMA_DAT_fifo u_dat${posw}_fifo${posb} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.dat_fifo_wr_prdy (dat${posw}_fifo${posb}_wr_prdy) +//: ,.dat_fifo_wr_pvld (dat${posw}_fifo${posb}_wr_pvld) +//: ,.dat_fifo_wr_pd (dat${posw}_fifo${posb}_wr_pd) +//: ,.dat_fifo_rd_prdy (dat${posw}_fifo${posb}_rd_prdy) +//: ,.dat_fifo_rd_pvld (dat${posw}_fifo${posb}_rd_pvld) +//: ,.dat_fifo_rd_pd (dat${posw}_fifo${posb}_rd_pd) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: ); +//: ); +//: +//: push @dat_wr_rdys, "( dat${posw}_fifo${posb}_wr_prdy & (spt_posw==$posw) & (spt_posb == $posb) )"; +//: +//: print qq { +//: // ::assert never "when the first fifo is ready, all the left fifo should be ready" dat${posw}_fifo0_wr_prdy & !dat${posw}_fifo${posb}_wr_prdy; +//: // ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat${posw}_fifo${posb}_wr_prdy & !dat${posw}_fifo3_wr_prdy; +//: }; +//: } +//: } +//: +//: # dat_wr_rdys to make sure the dat fifo which is to sink data is not full +//: my $dat_wr_rdys_str = join(" \n| ",@dat_wr_rdys); +//: print "assign dat_fifo_wr_prdy = $dat_wr_rdys_str;"; +//: +//: my $dat_wr_accepts_str = join(" \n| ",@dat_wr_accepts); +//: print "assign spt_dat_accept = dat_fifo_wr_pvld & dat_fifo_wr_prdy;"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8-1:0] dat0_fifo0_wr_pd; +wire dat0_fifo0_wr_prdy; +wire dat0_fifo0_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo0_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 0); +assign dat0_fifo0_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo0_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo0_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo0_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo0_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo0_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo0_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo0_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo0_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo1_wr_pd; +wire dat0_fifo1_wr_prdy; +wire dat0_fifo1_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo1_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 1); +assign dat0_fifo1_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo1 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo1_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo1_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo1_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo1_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo1_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo1_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo1_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo1_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo2_wr_pd; +wire dat0_fifo2_wr_prdy; +wire dat0_fifo2_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo2_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 2); +assign dat0_fifo2_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo2 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo2_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo2_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo2_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo2_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo2_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo2_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo2_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo2_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo3_wr_pd; +wire dat0_fifo3_wr_prdy; +wire dat0_fifo3_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo3_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 3); +assign dat0_fifo3_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo3 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo3_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo3_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo3_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo3_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo3_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo3_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo3_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo3_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo4_wr_pd; +wire dat0_fifo4_wr_prdy; +wire dat0_fifo4_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo4_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 4); +assign dat0_fifo4_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo4 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo4_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo4_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo4_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo4_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo4_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo4_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo4_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo4_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo5_wr_pd; +wire dat0_fifo5_wr_prdy; +wire dat0_fifo5_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo5_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 5); +assign dat0_fifo5_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo5 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo5_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo5_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo5_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo5_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo5_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo5_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo5_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo5_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo6_wr_pd; +wire dat0_fifo6_wr_prdy; +wire dat0_fifo6_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo6_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 6); +assign dat0_fifo6_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo6 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo6_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo6_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo6_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo6_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo6_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo6_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo6_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo6_wr_prdy & !dat0_fifo3_wr_prdy; + +wire [8-1:0] dat0_fifo7_wr_pd; +wire dat0_fifo7_wr_prdy; +wire dat0_fifo7_wr_pvld; +// DATA FIFO WRITE SIDE +// is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +assign dat0_fifo7_wr_pvld = dat_fifo_wr_pvld & (spt_posw==0) & (spt_posb == 7); +assign dat0_fifo7_wr_pd = dp2wdma_dat_pd; + +// DATA FIFO INSTANCE +NV_NVDLA_PDP_WDMA_DAT_fifo u_dat0_fifo7 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.dat_fifo_wr_prdy (dat0_fifo7_wr_prdy) +,.dat_fifo_wr_pvld (dat0_fifo7_wr_pvld) +,.dat_fifo_wr_pd (dat0_fifo7_wr_pd) +,.dat_fifo_rd_prdy (dat0_fifo7_rd_prdy) +,.dat_fifo_rd_pvld (dat0_fifo7_rd_pvld) +,.dat_fifo_rd_pd (dat0_fifo7_rd_pd) +,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +); + +// ::assert never "when the first fifo is ready, all the left fifo should be ready" dat0_fifo0_wr_prdy & !dat0_fifo7_wr_prdy; +// ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat0_fifo7_wr_prdy & !dat0_fifo3_wr_prdy; +assign dat_fifo_wr_prdy = ( dat0_fifo0_wr_prdy & (spt_posw==0) & (spt_posb == 0) ) +| ( dat0_fifo1_wr_prdy & (spt_posw==0) & (spt_posb == 1) ) +| ( dat0_fifo2_wr_prdy & (spt_posw==0) & (spt_posb == 2) ) +| ( dat0_fifo3_wr_prdy & (spt_posw==0) & (spt_posb == 3) ) +| ( dat0_fifo4_wr_prdy & (spt_posw==0) & (spt_posb == 4) ) +| ( dat0_fifo5_wr_prdy & (spt_posw==0) & (spt_posb == 5) ) +| ( dat0_fifo6_wr_prdy & (spt_posw==0) & (spt_posb == 6) ) +| ( dat0_fifo7_wr_prdy & (spt_posw==0) & (spt_posb == 7) );assign spt_dat_accept = dat_fifo_wr_pvld & dat_fifo_wr_prdy; +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_PDP_WDMA_dat +// -w 64, 8byte each fifo +// -d 3, depth=4 as we have rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_WDMA_DAT_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dat_fifo_wr -rd_pipebus dat_fifo_rd -rand_none -rd_reg -ram_bypass -d 3 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_DAT_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , dat_fifo_wr_prdy + , dat_fifo_wr_pvld + , dat_fifo_wr_pd + , dat_fifo_rd_prdy + , dat_fifo_rd_pvld + , dat_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dat_fifo_wr_prdy; +input dat_fifo_wr_pvld; +input [7:0] dat_fifo_wr_pd; +input dat_fifo_rd_prdy; +output dat_fifo_rd_pvld; +output [7:0] dat_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dat_fifo_wr_busy_int; // copy for internal use +assign dat_fifo_wr_prdy = !dat_fifo_wr_busy_int; +assign wr_reserving = dat_fifo_wr_pvld && !dat_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dat_fifo_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dat_fifo_wr_count : (dat_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dat_fifo_wr_count + 1'd1) : dat_fifo_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dat_fifo_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_busy_int <= 1'b0; + dat_fifo_wr_count <= 3'd0; + end else begin + dat_fifo_wr_busy_int <= dat_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dat_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dat_fifo_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dat_fifo_wr_pvld +// +// RAM +// +reg [1:0] dat_fifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dat_fifo_wr_adr <= dat_fifo_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] dat_fifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (dat_fifo_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] dat_fifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dat_fifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dat_fifo_wr_adr ) + , .ra ( (dat_fifo_wr_count == 0) ? 3'd4 : {1'b0,dat_fifo_rd_adr} ) + , .dout ( dat_fifo_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = dat_fifo_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + dat_fifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dat_fifo_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire dat_fifo_rd_pvld_p; // data out of fifo is valid +reg dat_fifo_rd_pvld_int; // internal copy of dat_fifo_rd_pvld +assign dat_fifo_rd_pvld = dat_fifo_rd_pvld_int; +assign rd_popping = dat_fifo_rd_pvld_p && !(dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy); +reg [2:0] dat_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? dat_fifo_rd_count_p : + (dat_fifo_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (dat_fifo_rd_count_p + 1'd1) : + dat_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign dat_fifo_rd_pvld_p = dat_fifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + dat_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dat_fifo_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] dat_fifo_rd_pd; // output data register +wire rd_req_next = (dat_fifo_rd_pvld_p || (dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_pvld_int <= 1'b0; + end else begin + dat_fifo_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + dat_fifo_rd_pd <= dat_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + dat_fifo_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dat_fifo_wr_pvld && !dat_fifo_wr_busy_int) || (dat_fifo_wr_busy_int != dat_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (dat_fifo_rd_pvld_int && dat_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dat_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_WDMA_DAT_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_WDMA_DAT_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [7:0] Di0; +input [1:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8] } +endmodule // vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +//vmw: Memory vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +//vmw: Address-size 2 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v.vcp new file mode 100644 index 0000000..c4dde97 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v.vcp @@ -0,0 +1,941 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_WDMA_dat.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_dat ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2wdma_pd //|< i + ,dp2wdma_vld //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_out_channel //|< i + ,reg2dp_cube_out_height //|< i + ,reg2dp_cube_out_width //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_split_num //|< i + ,wdma_done //|< i +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: ,dat${posw}_fifo${posb}_rd_pd +//: ,dat${posw}_fifo${posb}_rd_prdy +//: ,dat${posw}_fifo${posb}_rd_pvld +//: ); +//: } +//: } + ,dp2wdma_rdy //|> o + ); +///////////////////////////////////////////////////////////////////// +//&Catenate "NV_NVDLA_PDP_wdma_ports.v"; +input [12:0] reg2dp_cube_out_channel; +input [12:0] reg2dp_cube_out_height; +input [12:0] reg2dp_cube_out_width; +//input [1:0] reg2dp_input_data; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [7:0] reg2dp_split_num; +input [1*8 -1:0] dp2wdma_pd; +input dp2wdma_vld; +output dp2wdma_rdy; +//&Ports /^spt/; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: output [$pdpbw-1:0] dat${posw}_fifo${posb}_rd_pd; +//: input dat${posw}_fifo${posb}_rd_prdy; +//: output dat${posw}_fifo${posb}_rd_pvld; +//: ); +//: } +//: } +input wdma_done; +input op_load; +////////////////////////////////////////////////////////////////// +//reg cfg_do_fp16; +//reg cfg_do_int16; +//reg cfg_do_int8; +reg [4:0] count_b; +reg [12:0] count_h; +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print "reg [12-${k}:0] count_surf; \n"; +reg [12:0] count_w; +reg [7:0] count_wg; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +//reg [31:0] nan_out_num; +//reg [31:0] nan_output_num; +wire cfg_mode_split; +wire dat_fifo_wr_prdy; +wire dat_fifo_wr_pvld; +//wire [3:0] dat_is_nan; +wire [1*8 -1:0] dp2wdma_dat_pd; +//wire [15:0] fp16_in_pd_0; +//wire [15:0] fp16_in_pd_1; +//wire [15:0] fp16_in_pd_2; +//wire [15:0] fp16_in_pd_3; +wire is_blk_end; +wire is_cube_end; +wire is_first_wg; +wire is_fspt; +wire is_last_b; +wire is_last_h; +wire is_last_surf; +wire is_last_w; +wire is_last_wg; +wire is_line_end; +wire is_lspt; +wire is_mspt; +wire is_split_end; +wire is_surf_end; +//wire mon_size_of_surf; +//wire [2:0] nan_num_in_8byte; +//wire [1:0] nan_num_in_8byte_0; +//wire [1:0] nan_num_in_8byte_1; +wire [12:0] size_of_width; +wire [9:0] split_size_of_width; +wire spt_dat_accept; +//wire [1:0] spt_posb; +wire [4:0] spt_posb; +wire [1:0] spt_posw; +//wire wdma_loadin; +//////////////////////////////////////////////////////////////////////// +assign cfg_mode_split = (reg2dp_split_num!=0); +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int8 <= 1'b0; +// end else begin +// cfg_do_int8 <= reg2dp_input_data== 0; +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_int16 <= 1'b0; +// end else begin +// cfg_do_int16 <= reg2dp_input_data== 2'h1; +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cfg_do_fp16 <= 1'b0; +// end else begin +// cfg_do_fp16 <= reg2dp_input_data== 2'h2; +// end +// end +// +// //============== +// //NaN counter +// //============== +// assign wdma_loadin = spt_dat_accept;//dp2wdma_vld & dp2wdma_rdy; +// assign fp16_in_pd_0 = dp2wdma_pd[15:0]; +// assign fp16_in_pd_1 = dp2wdma_pd[31:16]; +// assign fp16_in_pd_2 = dp2wdma_pd[47:32]; +// assign fp16_in_pd_3 = dp2wdma_pd[63:48]; +// assign dat_is_nan[0] = cfg_do_fp16 & (&fp16_in_pd_0[14:10]) & (|fp16_in_pd_0[9:0]); +// assign dat_is_nan[1] = cfg_do_fp16 & (&fp16_in_pd_1[14:10]) & (|fp16_in_pd_1[9:0]); +// assign dat_is_nan[2] = cfg_do_fp16 & (&fp16_in_pd_2[14:10]) & (|fp16_in_pd_2[9:0]); +// assign dat_is_nan[3] = cfg_do_fp16 & (&fp16_in_pd_3[14:10]) & (|fp16_in_pd_3[9:0]); +// +// assign nan_num_in_8byte_0[1:0] = dat_is_nan[0] + dat_is_nan[1]; +// assign nan_num_in_8byte_1[1:0] = dat_is_nan[2] + dat_is_nan[3]; +// assign nan_num_in_8byte[2:0] = nan_num_in_8byte_0 + nan_num_in_8byte_1; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(wdma_loadin) begin +// if(is_cube_end) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte; +// end +// end +// end +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass disable_block NoWidthInBasedNum-ML +// // spyglass disable_block STARC-2.10.3.2a +// // spyglass disable_block STARC05-2.1.3.1 +// // spyglass disable_block STARC-2.1.4.6 +// // spyglass disable_block W116 +// // spyglass disable_block W154 +// // spyglass disable_block W239 +// // spyglass disable_block W362 +// // spyglass disable_block WRN_58 +// // spyglass disable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +// `ifdef ASSERT_ON +// `ifdef FV_ASSERT_ON +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef SYNTHESIS +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef ASSERT_OFF_RESET_IS_X +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +// `else +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +// `endif // ASSERT_OFF_RESET_IS_X +// `endif // SYNTHESIS +// `endif // FV_ASSERT_ON +// // VCS coverage off +// nv_assert_never #(0,0,"PDP WDMA: no overflow is allowed") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, mon_nan_in_count); // spyglass disable W504 SelfDeterminedExpr-ML +// // VCS coverage on +// `undef ASSERT_RESET +// `endif // ASSERT_ON +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass enable_block NoWidthInBasedNum-ML +// // spyglass enable_block STARC-2.10.3.2a +// // spyglass enable_block STARC05-2.1.3.1 +// // spyglass enable_block STARC-2.1.4.6 +// // spyglass enable_block W116 +// // spyglass enable_block W154 +// // spyglass enable_block W239 +// // spyglass enable_block W362 +// // spyglass enable_block WRN_58 +// // spyglass enable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_out_num <= {32{1'b0}}; +// end else begin +// if(is_cube_end) +// nan_out_num <= nan_in_count; +// end +// end +// //assign wdma_done = dp2reg_done; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_output_num <= {32{1'b0}}; +// end else begin +// if(wdma_done) begin +// nan_output_num <= nan_out_num; +// end +// end +// end +// +//============== +// CUBE DRAW +//============== +assign is_blk_end = is_last_b; +assign is_line_end = is_blk_end & is_last_w; +assign is_surf_end = is_line_end & is_last_h; +assign is_split_end = is_surf_end & is_last_surf; +assign is_cube_end = is_split_end & is_last_wg; +// WIDTH COUNT: in width direction, indidate one block +assign split_size_of_width = is_fspt ? reg2dp_partial_width_out_first : + is_lspt ? reg2dp_partial_width_out_last : + is_mspt ? reg2dp_partial_width_out_mid : {10{`x_or_0}}; +assign size_of_width = cfg_mode_split ? {3'd0,split_size_of_width} : reg2dp_cube_out_width; +// WG: WidthGroup, including one FSPT, one LSPT, and many MSPT +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_wg <= {8{1'b0}}; + end else begin + if (op_load) begin + count_wg <= 0; + end else if (spt_dat_accept) begin + if (is_cube_end) begin + count_wg <= 0; + end else if (is_split_end) begin + count_wg <= count_wg + 1; + end + end + end +end +assign is_last_wg = (count_wg==reg2dp_split_num); +assign is_first_wg = (count_wg==0); +assign is_fspt = cfg_mode_split & is_first_wg; +assign is_lspt = cfg_mode_split & is_last_wg; +assign is_mspt = cfg_mode_split & !is_fspt & !is_lspt; +//================================================================ +// C direction: count_b + count_surf +// count_b: in each W in line, will go 4 step in c first +// count_surf: when one surf with 4c is done, will go to next surf +//================================================================ +//============== +// COUNT B +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_b <= {5{1'b0}}; + end else begin + if (spt_dat_accept) begin + if (is_blk_end) begin + count_b <= 0; + end else begin + count_b <= count_b + 1; + end + end + end +end +//: my $atomicm = 8; +//: my $pdpth = 1; +//: my $k = int( $atomicm/$pdpth ); +//: print "assign is_last_b = (count_b==5'd${k} -1 ); \n"; +//============== +// COUNT W +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {13{1'b0}}; + end else begin + if (spt_dat_accept) begin + if (is_line_end) begin + count_w <= 0; + end else if (is_blk_end) begin + count_w <= count_w + 1; + end + end + end +end +assign is_last_w = (count_w==size_of_width); +//============== +// COUNT SURF +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_surf <= 0; + end else begin + if (spt_dat_accept) begin + if (is_split_end) begin + count_surf <= 0; + end else if (is_surf_end) begin + count_surf <= count_surf + 1; + end + end + end +end +//: my $atomicm = 8; +//: my $k = int( log($atomicm)/log(2) ); +//: print qq( +//: assign is_last_surf = (count_surf== reg2dp_cube_out_channel[12:${k}]); +//: ); +//============== +// COUNT HEIGHT +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (spt_dat_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_cube_out_height); +//============== +// spt information gen +//============== +assign spt_posb = count_b; +//: my $Wnum = 64/8/8; +//: if($Wnum == 1) { +//: print qq( +//: assign spt_posw = 2'b0; +//: ); +//: } else { +//: my $k = int( log($Wnum)/log(2) ); +//: print qq( +//: assign spt_posw = {{(2-$k){1'b0}},count_w[$k-1:0]}; +//: ); +//: } +//============== +// Data FIFO WRITE contrl +//============== +assign dp2wdma_dat_pd = dp2wdma_pd; +assign dat_fifo_wr_pvld = dp2wdma_vld; +assign dp2wdma_rdy = dat_fifo_wr_prdy; +//: my @dat_wr_rdys; +//: my @dat_wr_accepts; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: wire [$pdpbw-1:0] dat${posw}_fifo${posb}_wr_pd; +//: wire dat${posw}_fifo${posb}_wr_prdy; +//: wire dat${posw}_fifo${posb}_wr_pvld; +//: // DATA FIFO WRITE SIDE +//: // is last_b, then fifo idx large than count_b will need a push to fill in fake data to make up a full atomic_m +//: assign dat${posw}_fifo${posb}_wr_pvld = dat_fifo_wr_pvld & (spt_posw==$posw) & (spt_posb == $posb); +//: assign dat${posw}_fifo${posb}_wr_pd = dp2wdma_dat_pd; +//: +//: // DATA FIFO INSTANCE +//: NV_NVDLA_PDP_WDMA_DAT_fifo u_dat${posw}_fifo${posb} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.dat_fifo_wr_prdy (dat${posw}_fifo${posb}_wr_prdy) +//: ,.dat_fifo_wr_pvld (dat${posw}_fifo${posb}_wr_pvld) +//: ,.dat_fifo_wr_pd (dat${posw}_fifo${posb}_wr_pd) +//: ,.dat_fifo_rd_prdy (dat${posw}_fifo${posb}_rd_prdy) +//: ,.dat_fifo_rd_pvld (dat${posw}_fifo${posb}_rd_pvld) +//: ,.dat_fifo_rd_pd (dat${posw}_fifo${posb}_rd_pd) +//: ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: ); +//: ); +//: +//: push @dat_wr_rdys, "( dat${posw}_fifo${posb}_wr_prdy & (spt_posw==$posw) & (spt_posb == $posb) )"; +//: +//: print qq { +//: // ::assert never "when the first fifo is ready, all the left fifo should be ready" dat${posw}_fifo0_wr_prdy & !dat${posw}_fifo${posb}_wr_prdy; +//: // ::assert never "when the last fifo is not ready, all the previous fifo should not be ready" dat${posw}_fifo${posb}_wr_prdy & !dat${posw}_fifo3_wr_prdy; +//: }; +//: } +//: } +//: +//: # dat_wr_rdys to make sure the dat fifo which is to sink data is not full +//: my $dat_wr_rdys_str = join(" \n| ",@dat_wr_rdys); +//: print "assign dat_fifo_wr_prdy = $dat_wr_rdys_str;"; +//: +//: my $dat_wr_accepts_str = join(" \n| ",@dat_wr_accepts); +//: print "assign spt_dat_accept = dat_fifo_wr_pvld & dat_fifo_wr_prdy;"; +endmodule // NV_NVDLA_PDP_WDMA_dat +// -w 64, 8byte each fifo +// -d 3, depth=4 as we have rd_reg +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_WDMA_DAT_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus dat_fifo_wr -rd_pipebus dat_fifo_rd -rand_none -rd_reg -ram_bypass -d 3 -w 64 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_DAT_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , dat_fifo_wr_prdy + , dat_fifo_wr_pvld + , dat_fifo_wr_pd + , dat_fifo_rd_prdy + , dat_fifo_rd_pvld + , dat_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dat_fifo_wr_prdy; +input dat_fifo_wr_pvld; +input [7:0] dat_fifo_wr_pd; +input dat_fifo_rd_prdy; +output dat_fifo_rd_pvld; +output [7:0] dat_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dat_fifo_wr_busy_int; // copy for internal use +assign dat_fifo_wr_prdy = !dat_fifo_wr_busy_int; +assign wr_reserving = dat_fifo_wr_pvld && !dat_fifo_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dat_fifo_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dat_fifo_wr_count : (dat_fifo_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dat_fifo_wr_count + 1'd1) : dat_fifo_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dat_fifo_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dat_fifo_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_busy_int <= 1'b0; + dat_fifo_wr_count <= 3'd0; + end else begin + dat_fifo_wr_busy_int <= dat_fifo_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dat_fifo_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dat_fifo_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dat_fifo_wr_pvld +// +// RAM +// +reg [1:0] dat_fifo_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dat_fifo_wr_adr <= dat_fifo_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] dat_fifo_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (dat_fifo_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [7:0] dat_fifo_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dat_fifo_wr_pd ) + , .we ( ram_we ) + , .wa ( dat_fifo_wr_adr ) + , .ra ( (dat_fifo_wr_count == 0) ? 3'd4 : {1'b0,dat_fifo_rd_adr} ) + , .dout ( dat_fifo_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = dat_fifo_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + dat_fifo_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + dat_fifo_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire dat_fifo_rd_pvld_p; // data out of fifo is valid +reg dat_fifo_rd_pvld_int; // internal copy of dat_fifo_rd_pvld +assign dat_fifo_rd_pvld = dat_fifo_rd_pvld_int; +assign rd_popping = dat_fifo_rd_pvld_p && !(dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy); +reg [2:0] dat_fifo_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? dat_fifo_rd_count_p : + (dat_fifo_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (dat_fifo_rd_count_p + 1'd1) : + dat_fifo_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign dat_fifo_rd_pvld_p = dat_fifo_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + dat_fifo_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + dat_fifo_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [7:0] dat_fifo_rd_pd; // output data register +wire rd_req_next = (dat_fifo_rd_pvld_p || (dat_fifo_rd_pvld_int && !dat_fifo_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dat_fifo_rd_pvld_int <= 1'b0; + end else begin + dat_fifo_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + dat_fifo_rd_pd <= dat_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + dat_fifo_rd_pd <= {8{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dat_fifo_wr_pvld && !dat_fifo_wr_busy_int) || (dat_fifo_wr_busy_int != dat_fifo_wr_busy_next)) || (rd_pushing || rd_popping || (dat_fifo_rd_pvld_int && dat_fifo_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_PDP_WDMA_DAT_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dat_fifo_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_WDMA_DAT_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_WDMA_DAT_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [7:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [7:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [7:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [7:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [7:0] ram_ff0; +reg [7:0] ram_ff1; +reg [7:0] ram_ff2; +reg [7:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [7:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {8{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [7:0] Di0; +input [1:0] Ra0; +output [7:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 8'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [7:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [7:0] Q0 = mem[0]; +wire [7:0] Q1 = mem[1]; +wire [7:0] Q2 = mem[2]; +wire [7:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8] } +endmodule // vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +//vmw: Memory vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +//vmw: Address-size 2 +//vmw: Data-size 8 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[7:0] data0[7:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[7:0] data1[7:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_PDP_WDMA_DAT_fifo_flopram_rwsa_4x8 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v new file mode 100644 index 0000000..3583e51 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v @@ -0,0 +1,349 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,datin_src_cfg //|< i + ,dp2reg_done //|< i + ,padding_h_cfg //|< i + ,padding_v_cfg //|< i + ,pdp_dp2wdma_ready //|< i + ,pdp_rdma2dp_pd //|< i + ,pdp_rdma2dp_valid //|< i + ,pooling_channel_cfg //|< i + ,pooling_fwidth_cfg //|< i + ,pooling_lwidth_cfg //|< i + ,pooling_mwidth_cfg //|< i + ,pooling_out_fwidth_cfg //|< i + ,pooling_out_lwidth_cfg //|< i + ,pooling_out_mwidth_cfg //|< i + ,pooling_size_h_cfg //|< i + ,pooling_size_v_cfg //|< i + ,pooling_splitw_num_cfg //|< i + ,pooling_stride_h_cfg //|< i + ,pooling_stride_v_cfg //|< i + ,pooling_type_cfg //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_in_channel //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_in_width //|< i + ,reg2dp_cube_out_width //|< i + ,reg2dp_flying_mode //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_kernel_height //|< i + ,reg2dp_kernel_stride_width //|< i + ,reg2dp_kernel_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_pad_bottom_cfg //|< i + ,reg2dp_pad_left //|< i + ,reg2dp_pad_right //|< i + ,reg2dp_pad_right_cfg //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value_1x_cfg //|< i + ,reg2dp_pad_value_2x_cfg //|< i + ,reg2dp_pad_value_3x_cfg //|< i + ,reg2dp_pad_value_4x_cfg //|< i + ,reg2dp_pad_value_5x_cfg //|< i + ,reg2dp_pad_value_6x_cfg //|< i + ,reg2dp_pad_value_7x_cfg //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_recip_height_cfg //|< i + ,reg2dp_recip_width_cfg //|< i + ,sdp2pdp_pd //|< i + ,sdp2pdp_valid //|< i + ,pdp_dp2wdma_pd //|> o + ,pdp_dp2wdma_valid //|> o + ,pdp_rdma2dp_ready //|> o + ,sdp2pdp_ready //|> o + ); + input nvdla_core_clk; + input nvdla_core_rstn; + input datin_src_cfg; + input dp2reg_done; + input [2:0] padding_h_cfg; + input [2:0] padding_v_cfg; + input pdp_dp2wdma_ready; + input [1*8 +11:0] pdp_rdma2dp_pd; + input pdp_rdma2dp_valid; + input [12:0] pooling_channel_cfg; + input [9:0] pooling_fwidth_cfg; + input [9:0] pooling_lwidth_cfg; + input [9:0] pooling_mwidth_cfg; + input [9:0] pooling_out_fwidth_cfg; + input [9:0] pooling_out_lwidth_cfg; + input [9:0] pooling_out_mwidth_cfg; + input [2:0] pooling_size_h_cfg; + input [2:0] pooling_size_v_cfg; + input [7:0] pooling_splitw_num_cfg; + input [3:0] pooling_stride_h_cfg; + input [3:0] pooling_stride_v_cfg; + input [1:0] pooling_type_cfg; + input [31:0] pwrbus_ram_pd; + input [12:0] reg2dp_cube_in_channel; + input [12:0] reg2dp_cube_in_height; + input [12:0] reg2dp_cube_in_width; + input [12:0] reg2dp_cube_out_width; + input reg2dp_flying_mode; +// input [1:0] reg2dp_input_data; + input [2:0] reg2dp_kernel_height; + input [3:0] reg2dp_kernel_stride_width; + input [2:0] reg2dp_kernel_width; + input reg2dp_op_en; + input [2:0] reg2dp_pad_bottom_cfg; + input [2:0] reg2dp_pad_left; + input [2:0] reg2dp_pad_right; + input [2:0] reg2dp_pad_right_cfg; + input [2:0] reg2dp_pad_top; + input [18:0] reg2dp_pad_value_1x_cfg; + input [18:0] reg2dp_pad_value_2x_cfg; + input [18:0] reg2dp_pad_value_3x_cfg; + input [18:0] reg2dp_pad_value_4x_cfg; + input [18:0] reg2dp_pad_value_5x_cfg; + input [18:0] reg2dp_pad_value_6x_cfg; + input [18:0] reg2dp_pad_value_7x_cfg; + input [9:0] reg2dp_partial_width_out_first; + input [9:0] reg2dp_partial_width_out_last; + input [9:0] reg2dp_partial_width_out_mid; + input [16:0] reg2dp_recip_height_cfg; + input [16:0] reg2dp_recip_width_cfg; + input [8*1 -1:0] sdp2pdp_pd; + input sdp2pdp_valid; + output [1*8 -1:0] pdp_dp2wdma_pd; + output pdp_dp2wdma_valid; + output pdp_rdma2dp_ready; + output sdp2pdp_ready; +//wire + wire pdp_op_start; + wire [1*(8 +6)-1:0] pooling1d_pd; + wire pooling1d_prdy; + wire pooling1d_pvld; + wire [1*8 +11:0] pre2cal1d_pd; + wire pre2cal1d_prdy; + wire pre2cal1d_pvld; +//reg + reg [1:0] pooling_type_cfg_d; +// reg [1:0] reg2dp_input_data_d; +// reg reg2dp_int16_en; +// reg reg2dp_int8_en; +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// reg2dp_input_data_d[1:0] <= {2{1'b0}}; +// end else begin +// reg2dp_input_data_d[1:0] <= reg2dp_input_data[1:0]; +// end +//end +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// reg2dp_int16_en <= 1'b0; +// end else begin +// reg2dp_int16_en <= reg2dp_input_data[1:0] == 2'h1; +// end +//end +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// reg2dp_int8_en <= 1'b0; +// end else begin +// reg2dp_int8_en <= reg2dp_input_data[1:0] == 2'h0; +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_type_cfg_d[1:0] <= {2{1'b0}}; + end else begin + pooling_type_cfg_d[1:0] <= pooling_type_cfg[1:0]; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP reg2dp_pad_value_1x not sign extend") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & (pooling_type_cfg== 2'h0 ) & ((|reg2dp_pad_value_1x_cfg[18:8 -1]) != (®2dp_pad_value_1x_cfg[18:8 -1])) ); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//==================================================================== +//Instance--pooling 1D +// +//-------------------------------------------------------------------- +NV_NVDLA_PDP_CORE_preproc u_preproc ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pre2cal1d_prdy (pre2cal1d_prdy) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) //|< i + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< i + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) //|< i + ,.reg2dp_flying_mode (reg2dp_flying_mode) //|< i +//,.reg2dp_input_data (reg2dp_input_data_d[1:0]) //|< r + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.sdp2pdp_pd (sdp2pdp_pd) //|< i + ,.sdp2pdp_valid (sdp2pdp_valid) //|< i + ,.pre2cal1d_pd (pre2cal1d_pd) //|> w + ,.pre2cal1d_pvld (pre2cal1d_pvld) //|> w + ,.sdp2pdp_ready (sdp2pdp_ready) //|> o + ); +//==================================================================== +//Instance--pooling 1D +// +//-------------------------------------------------------------------- +NV_NVDLA_PDP_CORE_cal1d u_cal1d ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.datin_src_cfg (datin_src_cfg) //|< i + ,.dp2reg_done (dp2reg_done) //|< i + ,.padding_h_cfg (padding_h_cfg[2:0]) //|< i + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) //|< i + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) //|< i + ,.pooling1d_prdy (pooling1d_prdy) //|< w + ,.pooling_channel_cfg (pooling_channel_cfg[12:0]) //|< i + ,.pooling_fwidth_cfg (pooling_fwidth_cfg[9:0]) //|< i + ,.pooling_lwidth_cfg (pooling_lwidth_cfg[9:0]) //|< i + ,.pooling_mwidth_cfg (pooling_mwidth_cfg[9:0]) //|< i + ,.pooling_out_fwidth_cfg (pooling_out_fwidth_cfg[9:0]) //|< i + ,.pooling_out_lwidth_cfg (pooling_out_lwidth_cfg[9:0]) //|< i + ,.pooling_out_mwidth_cfg (pooling_out_mwidth_cfg[9:0]) //|< i + ,.pooling_size_h_cfg (pooling_size_h_cfg[2:0]) //|< i + ,.pooling_splitw_num_cfg (pooling_splitw_num_cfg[7:0]) //|< i + ,.pooling_stride_h_cfg (pooling_stride_h_cfg[3:0]) //|< i + ,.pooling_type_cfg (pooling_type_cfg_d[1:0]) //|< r + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< i + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) //|< i + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) //|< i +// ,.reg2dp_input_data (reg2dp_input_data_d[1:0]) //|< r +// ,.reg2dp_int16_en (reg2dp_int16_en) //|< r +// ,.reg2dp_int8_en (reg2dp_int8_en) //|< r + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) //|< i + ,.reg2dp_kernel_width (reg2dp_kernel_width[2:0]) //|< i + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_pad_left (reg2dp_pad_left[2:0]) //|< i + ,.reg2dp_pad_right (reg2dp_pad_right[2:0]) //|< i + ,.reg2dp_pad_right_cfg (reg2dp_pad_right_cfg[2:0]) //|< i + ,.reg2dp_pad_value_1x_cfg (reg2dp_pad_value_1x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_2x_cfg (reg2dp_pad_value_2x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_3x_cfg (reg2dp_pad_value_3x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_4x_cfg (reg2dp_pad_value_4x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_5x_cfg (reg2dp_pad_value_5x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_6x_cfg (reg2dp_pad_value_6x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_7x_cfg (reg2dp_pad_value_7x_cfg[18:0]) //|< i + ,.sdp2pdp_pd (pre2cal1d_pd) //|< w + ,.sdp2pdp_valid (pre2cal1d_pvld) //|< w + ,.pdp_op_start (pdp_op_start) //|> w + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) //|> o + ,.pooling1d_pd (pooling1d_pd) //|> w + ,.pooling1d_pvld (pooling1d_pvld) //|> w + ,.sdp2pdp_ready (pre2cal1d_prdy) //|> w + ); +//==================================================================== +//Instanfce--pooling 2D +// +//-------------------------------------------------------------------- +NV_NVDLA_PDP_CORE_cal2d u_cal2d ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.padding_v_cfg (padding_v_cfg[2:0]) //|< i + ,.pdp_dp2wdma_ready (pdp_dp2wdma_ready) //|< i + ,.pdp_op_start (pdp_op_start) //|< w + ,.pooling1d_pd (pooling1d_pd ) //|< w + ,.pooling1d_pvld (pooling1d_pvld) //|< w + ,.pooling_channel_cfg (pooling_channel_cfg[12:0]) //|< i + ,.pooling_out_fwidth_cfg (pooling_out_fwidth_cfg[9:0]) //|< i + ,.pooling_out_lwidth_cfg (pooling_out_lwidth_cfg[9:0]) //|< i + ,.pooling_out_mwidth_cfg (pooling_out_mwidth_cfg[9:0]) //|< i + ,.pooling_size_v_cfg (pooling_size_v_cfg[2:0]) //|< i + ,.pooling_splitw_num_cfg (pooling_splitw_num_cfg[7:0]) //|< i + ,.pooling_stride_v_cfg (pooling_stride_v_cfg[3:0]) //|< i + ,.pooling_type_cfg (pooling_type_cfg_d[1:0]) //|< r + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< i + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) //|< i +// ,.reg2dp_input_data (reg2dp_input_data_d[1:0]) //|< r +// ,.reg2dp_int16_en (reg2dp_int16_en) //|< r +// ,.reg2dp_int8_en (reg2dp_int8_en) //|< r + ,.reg2dp_kernel_height (reg2dp_kernel_height[2:0]) //|< i + ,.reg2dp_kernel_width (reg2dp_kernel_width[2:0]) //|< i + ,.reg2dp_pad_bottom_cfg (reg2dp_pad_bottom_cfg[2:0]) //|< i + ,.reg2dp_pad_top (reg2dp_pad_top[2:0]) //|< i + ,.reg2dp_pad_value_1x_cfg (reg2dp_pad_value_1x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_2x_cfg (reg2dp_pad_value_2x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_3x_cfg (reg2dp_pad_value_3x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_4x_cfg (reg2dp_pad_value_4x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_5x_cfg (reg2dp_pad_value_5x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_6x_cfg (reg2dp_pad_value_6x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_7x_cfg (reg2dp_pad_value_7x_cfg[18:0]) //|< i + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) //|< i + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) //|< i + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) //|< i + ,.reg2dp_recip_height_cfg (reg2dp_recip_height_cfg[16:0]) //|< i + ,.reg2dp_recip_width_cfg (reg2dp_recip_width_cfg[16:0]) //|< i + ,.pdp_dp2wdma_pd (pdp_dp2wdma_pd) //|> o + ,.pdp_dp2wdma_valid (pdp_dp2wdma_valid) //|> o + ,.pooling1d_prdy (pooling1d_prdy) //|> w + ); +////============== +////OBS signals +////============== +//assign obs_bus_pdp_rdma2dp_vld = pdp_rdma2dp_valid; +//assign obs_bus_pdp_rdma2dp_rdy = pdp_rdma2dp_ready; +//assign obs_bus_pdp_sdp2dp_vld = pre2cal1d_pvld; +//assign obs_bus_pdp_sdp2dp_rdy = pre2cal1d_prdy; +//assign obs_bus_pdp_cal1d_vld = pooling1d_pvld; +//assign obs_bus_pdp_cal1d_rdy = pooling1d_prdy; +//assign obs_bus_pdp_cal2d_vld = pdp_dp2wdma_valid; +//assign obs_bus_pdp_cal2d_rdy = pdp_dp2wdma_ready; +endmodule // NV_NVDLA_PDP_core diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v.vcp new file mode 100644 index 0000000..3583e51 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v.vcp @@ -0,0 +1,349 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,datin_src_cfg //|< i + ,dp2reg_done //|< i + ,padding_h_cfg //|< i + ,padding_v_cfg //|< i + ,pdp_dp2wdma_ready //|< i + ,pdp_rdma2dp_pd //|< i + ,pdp_rdma2dp_valid //|< i + ,pooling_channel_cfg //|< i + ,pooling_fwidth_cfg //|< i + ,pooling_lwidth_cfg //|< i + ,pooling_mwidth_cfg //|< i + ,pooling_out_fwidth_cfg //|< i + ,pooling_out_lwidth_cfg //|< i + ,pooling_out_mwidth_cfg //|< i + ,pooling_size_h_cfg //|< i + ,pooling_size_v_cfg //|< i + ,pooling_splitw_num_cfg //|< i + ,pooling_stride_h_cfg //|< i + ,pooling_stride_v_cfg //|< i + ,pooling_type_cfg //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_cube_in_channel //|< i + ,reg2dp_cube_in_height //|< i + ,reg2dp_cube_in_width //|< i + ,reg2dp_cube_out_width //|< i + ,reg2dp_flying_mode //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_kernel_height //|< i + ,reg2dp_kernel_stride_width //|< i + ,reg2dp_kernel_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_pad_bottom_cfg //|< i + ,reg2dp_pad_left //|< i + ,reg2dp_pad_right //|< i + ,reg2dp_pad_right_cfg //|< i + ,reg2dp_pad_top //|< i + ,reg2dp_pad_value_1x_cfg //|< i + ,reg2dp_pad_value_2x_cfg //|< i + ,reg2dp_pad_value_3x_cfg //|< i + ,reg2dp_pad_value_4x_cfg //|< i + ,reg2dp_pad_value_5x_cfg //|< i + ,reg2dp_pad_value_6x_cfg //|< i + ,reg2dp_pad_value_7x_cfg //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_recip_height_cfg //|< i + ,reg2dp_recip_width_cfg //|< i + ,sdp2pdp_pd //|< i + ,sdp2pdp_valid //|< i + ,pdp_dp2wdma_pd //|> o + ,pdp_dp2wdma_valid //|> o + ,pdp_rdma2dp_ready //|> o + ,sdp2pdp_ready //|> o + ); + input nvdla_core_clk; + input nvdla_core_rstn; + input datin_src_cfg; + input dp2reg_done; + input [2:0] padding_h_cfg; + input [2:0] padding_v_cfg; + input pdp_dp2wdma_ready; + input [1*8 +11:0] pdp_rdma2dp_pd; + input pdp_rdma2dp_valid; + input [12:0] pooling_channel_cfg; + input [9:0] pooling_fwidth_cfg; + input [9:0] pooling_lwidth_cfg; + input [9:0] pooling_mwidth_cfg; + input [9:0] pooling_out_fwidth_cfg; + input [9:0] pooling_out_lwidth_cfg; + input [9:0] pooling_out_mwidth_cfg; + input [2:0] pooling_size_h_cfg; + input [2:0] pooling_size_v_cfg; + input [7:0] pooling_splitw_num_cfg; + input [3:0] pooling_stride_h_cfg; + input [3:0] pooling_stride_v_cfg; + input [1:0] pooling_type_cfg; + input [31:0] pwrbus_ram_pd; + input [12:0] reg2dp_cube_in_channel; + input [12:0] reg2dp_cube_in_height; + input [12:0] reg2dp_cube_in_width; + input [12:0] reg2dp_cube_out_width; + input reg2dp_flying_mode; +// input [1:0] reg2dp_input_data; + input [2:0] reg2dp_kernel_height; + input [3:0] reg2dp_kernel_stride_width; + input [2:0] reg2dp_kernel_width; + input reg2dp_op_en; + input [2:0] reg2dp_pad_bottom_cfg; + input [2:0] reg2dp_pad_left; + input [2:0] reg2dp_pad_right; + input [2:0] reg2dp_pad_right_cfg; + input [2:0] reg2dp_pad_top; + input [18:0] reg2dp_pad_value_1x_cfg; + input [18:0] reg2dp_pad_value_2x_cfg; + input [18:0] reg2dp_pad_value_3x_cfg; + input [18:0] reg2dp_pad_value_4x_cfg; + input [18:0] reg2dp_pad_value_5x_cfg; + input [18:0] reg2dp_pad_value_6x_cfg; + input [18:0] reg2dp_pad_value_7x_cfg; + input [9:0] reg2dp_partial_width_out_first; + input [9:0] reg2dp_partial_width_out_last; + input [9:0] reg2dp_partial_width_out_mid; + input [16:0] reg2dp_recip_height_cfg; + input [16:0] reg2dp_recip_width_cfg; + input [8*1 -1:0] sdp2pdp_pd; + input sdp2pdp_valid; + output [1*8 -1:0] pdp_dp2wdma_pd; + output pdp_dp2wdma_valid; + output pdp_rdma2dp_ready; + output sdp2pdp_ready; +//wire + wire pdp_op_start; + wire [1*(8 +6)-1:0] pooling1d_pd; + wire pooling1d_prdy; + wire pooling1d_pvld; + wire [1*8 +11:0] pre2cal1d_pd; + wire pre2cal1d_prdy; + wire pre2cal1d_pvld; +//reg + reg [1:0] pooling_type_cfg_d; +// reg [1:0] reg2dp_input_data_d; +// reg reg2dp_int16_en; +// reg reg2dp_int8_en; +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// reg2dp_input_data_d[1:0] <= {2{1'b0}}; +// end else begin +// reg2dp_input_data_d[1:0] <= reg2dp_input_data[1:0]; +// end +//end +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// reg2dp_int16_en <= 1'b0; +// end else begin +// reg2dp_int16_en <= reg2dp_input_data[1:0] == 2'h1; +// end +//end +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// reg2dp_int8_en <= 1'b0; +// end else begin +// reg2dp_int8_en <= reg2dp_input_data[1:0] == 2'h0; +// end +//end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pooling_type_cfg_d[1:0] <= {2{1'b0}}; + end else begin + pooling_type_cfg_d[1:0] <= pooling_type_cfg[1:0]; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDP reg2dp_pad_value_1x not sign extend") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & (pooling_type_cfg== 2'h0 ) & ((|reg2dp_pad_value_1x_cfg[18:8 -1]) != (®2dp_pad_value_1x_cfg[18:8 -1])) ); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//==================================================================== +//Instance--pooling 1D +// +//-------------------------------------------------------------------- +NV_NVDLA_PDP_CORE_preproc u_preproc ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pre2cal1d_prdy (pre2cal1d_prdy) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) //|< i + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< i + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) //|< i + ,.reg2dp_flying_mode (reg2dp_flying_mode) //|< i +//,.reg2dp_input_data (reg2dp_input_data_d[1:0]) //|< r + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.sdp2pdp_pd (sdp2pdp_pd) //|< i + ,.sdp2pdp_valid (sdp2pdp_valid) //|< i + ,.pre2cal1d_pd (pre2cal1d_pd) //|> w + ,.pre2cal1d_pvld (pre2cal1d_pvld) //|> w + ,.sdp2pdp_ready (sdp2pdp_ready) //|> o + ); +//==================================================================== +//Instance--pooling 1D +// +//-------------------------------------------------------------------- +NV_NVDLA_PDP_CORE_cal1d u_cal1d ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.datin_src_cfg (datin_src_cfg) //|< i + ,.dp2reg_done (dp2reg_done) //|< i + ,.padding_h_cfg (padding_h_cfg[2:0]) //|< i + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) //|< i + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) //|< i + ,.pooling1d_prdy (pooling1d_prdy) //|< w + ,.pooling_channel_cfg (pooling_channel_cfg[12:0]) //|< i + ,.pooling_fwidth_cfg (pooling_fwidth_cfg[9:0]) //|< i + ,.pooling_lwidth_cfg (pooling_lwidth_cfg[9:0]) //|< i + ,.pooling_mwidth_cfg (pooling_mwidth_cfg[9:0]) //|< i + ,.pooling_out_fwidth_cfg (pooling_out_fwidth_cfg[9:0]) //|< i + ,.pooling_out_lwidth_cfg (pooling_out_lwidth_cfg[9:0]) //|< i + ,.pooling_out_mwidth_cfg (pooling_out_mwidth_cfg[9:0]) //|< i + ,.pooling_size_h_cfg (pooling_size_h_cfg[2:0]) //|< i + ,.pooling_splitw_num_cfg (pooling_splitw_num_cfg[7:0]) //|< i + ,.pooling_stride_h_cfg (pooling_stride_h_cfg[3:0]) //|< i + ,.pooling_type_cfg (pooling_type_cfg_d[1:0]) //|< r + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< i + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) //|< i + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) //|< i +// ,.reg2dp_input_data (reg2dp_input_data_d[1:0]) //|< r +// ,.reg2dp_int16_en (reg2dp_int16_en) //|< r +// ,.reg2dp_int8_en (reg2dp_int8_en) //|< r + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) //|< i + ,.reg2dp_kernel_width (reg2dp_kernel_width[2:0]) //|< i + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_pad_left (reg2dp_pad_left[2:0]) //|< i + ,.reg2dp_pad_right (reg2dp_pad_right[2:0]) //|< i + ,.reg2dp_pad_right_cfg (reg2dp_pad_right_cfg[2:0]) //|< i + ,.reg2dp_pad_value_1x_cfg (reg2dp_pad_value_1x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_2x_cfg (reg2dp_pad_value_2x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_3x_cfg (reg2dp_pad_value_3x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_4x_cfg (reg2dp_pad_value_4x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_5x_cfg (reg2dp_pad_value_5x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_6x_cfg (reg2dp_pad_value_6x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_7x_cfg (reg2dp_pad_value_7x_cfg[18:0]) //|< i + ,.sdp2pdp_pd (pre2cal1d_pd) //|< w + ,.sdp2pdp_valid (pre2cal1d_pvld) //|< w + ,.pdp_op_start (pdp_op_start) //|> w + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) //|> o + ,.pooling1d_pd (pooling1d_pd) //|> w + ,.pooling1d_pvld (pooling1d_pvld) //|> w + ,.sdp2pdp_ready (pre2cal1d_prdy) //|> w + ); +//==================================================================== +//Instanfce--pooling 2D +// +//-------------------------------------------------------------------- +NV_NVDLA_PDP_CORE_cal2d u_cal2d ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.padding_v_cfg (padding_v_cfg[2:0]) //|< i + ,.pdp_dp2wdma_ready (pdp_dp2wdma_ready) //|< i + ,.pdp_op_start (pdp_op_start) //|< w + ,.pooling1d_pd (pooling1d_pd ) //|< w + ,.pooling1d_pvld (pooling1d_pvld) //|< w + ,.pooling_channel_cfg (pooling_channel_cfg[12:0]) //|< i + ,.pooling_out_fwidth_cfg (pooling_out_fwidth_cfg[9:0]) //|< i + ,.pooling_out_lwidth_cfg (pooling_out_lwidth_cfg[9:0]) //|< i + ,.pooling_out_mwidth_cfg (pooling_out_mwidth_cfg[9:0]) //|< i + ,.pooling_size_v_cfg (pooling_size_v_cfg[2:0]) //|< i + ,.pooling_splitw_num_cfg (pooling_splitw_num_cfg[7:0]) //|< i + ,.pooling_stride_v_cfg (pooling_stride_v_cfg[3:0]) //|< i + ,.pooling_type_cfg (pooling_type_cfg_d[1:0]) //|< r + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< i + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) //|< i +// ,.reg2dp_input_data (reg2dp_input_data_d[1:0]) //|< r +// ,.reg2dp_int16_en (reg2dp_int16_en) //|< r +// ,.reg2dp_int8_en (reg2dp_int8_en) //|< r + ,.reg2dp_kernel_height (reg2dp_kernel_height[2:0]) //|< i + ,.reg2dp_kernel_width (reg2dp_kernel_width[2:0]) //|< i + ,.reg2dp_pad_bottom_cfg (reg2dp_pad_bottom_cfg[2:0]) //|< i + ,.reg2dp_pad_top (reg2dp_pad_top[2:0]) //|< i + ,.reg2dp_pad_value_1x_cfg (reg2dp_pad_value_1x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_2x_cfg (reg2dp_pad_value_2x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_3x_cfg (reg2dp_pad_value_3x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_4x_cfg (reg2dp_pad_value_4x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_5x_cfg (reg2dp_pad_value_5x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_6x_cfg (reg2dp_pad_value_6x_cfg[18:0]) //|< i + ,.reg2dp_pad_value_7x_cfg (reg2dp_pad_value_7x_cfg[18:0]) //|< i + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) //|< i + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) //|< i + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) //|< i + ,.reg2dp_recip_height_cfg (reg2dp_recip_height_cfg[16:0]) //|< i + ,.reg2dp_recip_width_cfg (reg2dp_recip_width_cfg[16:0]) //|< i + ,.pdp_dp2wdma_pd (pdp_dp2wdma_pd) //|> o + ,.pdp_dp2wdma_valid (pdp_dp2wdma_valid) //|> o + ,.pooling1d_prdy (pooling1d_prdy) //|> w + ); +////============== +////OBS signals +////============== +//assign obs_bus_pdp_rdma2dp_vld = pdp_rdma2dp_valid; +//assign obs_bus_pdp_rdma2dp_rdy = pdp_rdma2dp_ready; +//assign obs_bus_pdp_sdp2dp_vld = pre2cal1d_pvld; +//assign obs_bus_pdp_sdp2dp_rdy = pre2cal1d_prdy; +//assign obs_bus_pdp_cal1d_vld = pooling1d_pvld; +//assign obs_bus_pdp_cal1d_rdy = pooling1d_prdy; +//assign obs_bus_pdp_cal2d_vld = pdp_dp2wdma_valid; +//assign obs_bus_pdp_cal2d_rdy = pdp_dp2wdma_ready; +endmodule // NV_NVDLA_PDP_core diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v new file mode 100644 index 0000000..b8ec446 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v @@ -0,0 +1,344 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_nan.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_nan ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2reg_done + ,nan_preproc_prdy + ,pdp_rdma2dp_pd + ,pdp_rdma2dp_valid + ,reg2dp_flying_mode +// ,reg2dp_input_data + ,reg2dp_nan_to_zero + ,reg2dp_op_en + ,dp2reg_inf_input_num + ,dp2reg_nan_input_num + ,nan_preproc_pd + ,nan_preproc_pvld + ,pdp_rdma2dp_ready + ); +/////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input nan_preproc_prdy; +input [8*1 +11:0] pdp_rdma2dp_pd; +input pdp_rdma2dp_valid; +input reg2dp_flying_mode; +//input [1:0] reg2dp_input_data; +input reg2dp_nan_to_zero; +input reg2dp_op_en; +output [31:0] dp2reg_inf_input_num; +output [31:0] dp2reg_nan_input_num; +output [8*1 +11:0] nan_preproc_pd; +output nan_preproc_pvld; +output pdp_rdma2dp_ready; +/////////////////////////////////////////////////////////////////// +reg [8*1 +11:0] datin_d; +reg cube_end_d1; +//reg [11:0] datin_info_d; +reg din_pvld_d1; +wire [31:0] dp2reg_inf_input_num=0; +wire [31:0] dp2reg_nan_input_num=0; +//reg [31:0] inf_in_count; +//reg [31:0] inf_in_num0; +//reg [31:0] inf_in_num1; +//reg [2:0] inf_num_in_8byte_d1; +reg layer_flag; +//reg mon_inf_in_count; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +//reg [31:0] nan_in_num0; +//reg [31:0] nan_in_num1; +//reg [2:0] nan_num_in_8byte_d1; +//reg [15:0] nan_preproc_pd0; +//reg [15:0] nan_preproc_pd1; +//reg [15:0] nan_preproc_pd2; +//reg [15:0] nan_preproc_pd3; +reg op_en_d1; +reg waiting_for_op_en; +reg wdma_layer_flag; +wire cube_end; +//wire [3:0] dat_is_inf; +//wire [3:0] dat_is_nan; +wire din_prdy_d1; +//wire fp16_en; +//wire [15:0] fp16_in_pd_0; +//wire [15:0] fp16_in_pd_1; +//wire [15:0] fp16_in_pd_2; +//wire [15:0] fp16_in_pd_3; +//wire [2:0] inf_num_in_8byte; +//wire [1:0] inf_num_in_8byte_0; +//wire [1:0] inf_num_in_8byte_1; +wire layer_end; +wire load_din; +wire load_din_d1; +//wire [2:0] nan_num_in_8byte; +//wire [1:0] nan_num_in_8byte_0; +//wire [1:0] nan_num_in_8byte_1; +wire onfly_en; +wire op_en_load; +wire pdp_rdma2dp_ready_f; +//wire tozero_en; +wire wdma_done; +//========================================== +//DP input side +//========================================== +//---------------------------------------- +assign pdp_rdma2dp_ready = pdp_rdma2dp_ready_f; +assign pdp_rdma2dp_ready_f = (~din_pvld_d1 | din_prdy_d1) & (~waiting_for_op_en); +assign load_din = pdp_rdma2dp_valid & pdp_rdma2dp_ready_f; +//---------------------------------------- +// assign tozero_en = reg2dp_nan_to_zero == 1'h1 ; +// assign fp16_en = (reg2dp_input_data[1:0]== 2'h2 ); +assign onfly_en = (reg2dp_flying_mode == 1'h0 ); +//---------------------------------------- +// assign fp16_in_pd_0 = pdp_rdma2dp_pd[15:0] ; +// assign fp16_in_pd_1 = pdp_rdma2dp_pd[31:16] ; +// assign fp16_in_pd_2 = pdp_rdma2dp_pd[47:32] ; +// assign fp16_in_pd_3 = pdp_rdma2dp_pd[63:48] ; +// +// assign dat_is_nan[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (|fp16_in_pd_0[9:0]); +// assign dat_is_nan[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (|fp16_in_pd_1[9:0]); +// assign dat_is_nan[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (|fp16_in_pd_2[9:0]); +// assign dat_is_nan[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (|fp16_in_pd_3[9:0]); +// +// assign dat_is_inf[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (~(|fp16_in_pd_0[9:0])); +// assign dat_is_inf[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (~(|fp16_in_pd_1[9:0])); +// assign dat_is_inf[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (~(|fp16_in_pd_2[9:0])); +// assign dat_is_inf[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (~(|fp16_in_pd_3[9:0])); +////////////////////////////////////////////////////////////////////// +//waiting for op_en +////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 1'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +assign op_en_load = reg2dp_op_en & (~op_en_d1); +//assign layer_end = &{pdp_rdma2dp_pd[75],pdp_rdma2dp_pd[71]} & load_din; +assign layer_end = &{pdp_rdma2dp_pd[8*1 +11],pdp_rdma2dp_pd[8*1 +7]} & load_din; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_for_op_en <= 1'b1; + end else begin + if(layer_end & (~onfly_en)) + waiting_for_op_en <= 1'b1; + else if(op_en_load) begin + if(onfly_en) + waiting_for_op_en <= 1'b1; + else if(~onfly_en) + waiting_for_op_en <= 1'b0; + end + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & (~pdp_rdma2dp_ready_f) & pdp_rdma2dp_valid; + endproperty +// Cover 0 : "waiting_for_op_en & (~pdp_rdma2dp_ready_f) & pdp_rdma2dp_valid" + FUNCPOINT_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__0_COV : cover property (RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov); + `endif +`endif +//VCS coverage on +///////////////////////////////////// +//NaN process mode control +///////////////////////////////////// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_preproc_pd0 <= {16{1'b0}}; +// nan_preproc_pd1 <= {16{1'b0}}; +// nan_preproc_pd2 <= {16{1'b0}}; +// nan_preproc_pd3 <= {16{1'b0}}; +// datin_info_d <= {12{1'b0}}; +// end else begin +// if(load_din) begin +// nan_preproc_pd0 <= (dat_is_nan[0] & tozero_en) ? 16'd0 : fp16_in_pd_0; +// nan_preproc_pd1 <= (dat_is_nan[1] & tozero_en) ? 16'd0 : fp16_in_pd_1; +// nan_preproc_pd2 <= (dat_is_nan[2] & tozero_en) ? 16'd0 : fp16_in_pd_2; +// nan_preproc_pd3 <= (dat_is_nan[3] & tozero_en) ? 16'd0 : fp16_in_pd_3; +// datin_info_d <= pdp_rdma2dp_pd[75:64]; +// end +// end +// end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_d <= 0; + end else begin + if(load_din) begin + datin_d <= pdp_rdma2dp_pd; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + din_pvld_d1 <= 1'b0; + end else begin + if(pdp_rdma2dp_valid & (~waiting_for_op_en)) + din_pvld_d1 <= 1'b1; + else if(din_prdy_d1) + din_pvld_d1 <= 1'b0; + end +end +assign din_prdy_d1 = nan_preproc_prdy; +//-------------output data ----------------- +//assign nan_preproc_pd = {datin_info_d,nan_preproc_pd3,nan_preproc_pd2,nan_preproc_pd1,nan_preproc_pd0}; +assign nan_preproc_pd = datin_d; +assign nan_preproc_pvld = din_pvld_d1; +// +// ///////////////////////////////////// +// //input NaN element count +// ///////////////////////////////////// +// assign cube_end = pdp_rdma2dp_pd[75]; +// +// assign nan_num_in_8byte_0[1:0] = dat_is_nan[0] + dat_is_nan[1]; +// assign nan_num_in_8byte_1[1:0] = dat_is_nan[2] + dat_is_nan[3]; +// assign nan_num_in_8byte[2:0] = nan_num_in_8byte_0 + nan_num_in_8byte_1; +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cube_end_d1 <= 1'b0; +// end else begin +// if ((load_din) == 1'b1) begin +// cube_end_d1 <= cube_end; +// end +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_num_in_8byte_d1 <= {3{1'b0}}; +// end else begin +// if ((load_din) == 1'b1) begin +// nan_num_in_8byte_d1 <= nan_num_in_8byte[2:0]; +// end +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// inf_num_in_8byte_d1 <= {3{1'b0}}; +// end else begin +// if ((load_din) == 1'b1) begin +// inf_num_in_8byte_d1 <= inf_num_in_8byte[2:0]; +// end +// end +// end +// +// assign load_din_d1 = din_pvld_d1 & din_prdy_d1; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din_d1) begin +// if(cube_end_d1) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte_d1; +// end +// end +// end +// +// assign inf_num_in_8byte_0[1:0] = dat_is_inf[0] + dat_is_inf[1]; +// assign inf_num_in_8byte_1[1:0] = dat_is_inf[2] + dat_is_inf[3]; +// assign inf_num_in_8byte[2:0] = inf_num_in_8byte_0 + inf_num_in_8byte_1; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_inf_in_count,inf_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din_d1) begin +// if(cube_end_d1) +// {mon_inf_in_count,inf_in_count[31:0]} <= 33'd0; +// else +// {mon_inf_in_count,inf_in_count[31:0]} <= inf_in_count + inf_num_in_8byte_d1; +// end +// end +// end +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// layer_flag <= 1'b0; +// nan_in_num1 <= {32{1'b0}}; +// inf_in_num1 <= {32{1'b0}}; +// nan_in_num0 <= {32{1'b0}}; +// inf_in_num0 <= {32{1'b0}}; +// end else begin +// if(load_din_d1 & cube_end_d1) begin +// layer_flag <= ~layer_flag; +// if(layer_flag) begin +// nan_in_num1 <= nan_in_count; +// inf_in_num1 <= inf_in_count; +// end else begin +// nan_in_num0 <= nan_in_count; +// inf_in_num0 <= inf_in_count; +// end +// end +// end +// end +// +// //adding dp2reg_done to latch the num and output a sigle one for each +// assign wdma_done = dp2reg_done; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// wdma_layer_flag <= 1'b0; +// dp2reg_nan_input_num <= {32{1'b0}}; +// dp2reg_inf_input_num <= {32{1'b0}}; +// end else begin +// if(wdma_done) begin +// wdma_layer_flag <= ~wdma_layer_flag; +// if(wdma_layer_flag) begin +// dp2reg_nan_input_num <= nan_in_num1; +// dp2reg_inf_input_num <= inf_in_num1; +// end else begin +// dp2reg_nan_input_num <= nan_in_num0; +// dp2reg_inf_input_num <= inf_in_num0; +// end +// end +// end +// end +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA2CORE__rdma_layerDone_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & (~pdp_rdma2dp_ready_f); + endproperty +// Cover 1 : "waiting_for_op_en & (~pdp_rdma2dp_ready_f)" + FUNCPOINT_PDP_RDMA2CORE__rdma_layerDone_stall__1_COV : cover property (PDP_RDMA2CORE__rdma_layerDone_stall__1_cov); + `endif +`endif +//VCS coverage on +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_PDP_nan diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v.vcp new file mode 100644 index 0000000..b8ec446 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v.vcp @@ -0,0 +1,344 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_nan.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_nan ( + nvdla_core_clk + ,nvdla_core_rstn + ,dp2reg_done + ,nan_preproc_prdy + ,pdp_rdma2dp_pd + ,pdp_rdma2dp_valid + ,reg2dp_flying_mode +// ,reg2dp_input_data + ,reg2dp_nan_to_zero + ,reg2dp_op_en + ,dp2reg_inf_input_num + ,dp2reg_nan_input_num + ,nan_preproc_pd + ,nan_preproc_pvld + ,pdp_rdma2dp_ready + ); +/////////////////////////////////////////////////////////////////// +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_done; +input nan_preproc_prdy; +input [8*1 +11:0] pdp_rdma2dp_pd; +input pdp_rdma2dp_valid; +input reg2dp_flying_mode; +//input [1:0] reg2dp_input_data; +input reg2dp_nan_to_zero; +input reg2dp_op_en; +output [31:0] dp2reg_inf_input_num; +output [31:0] dp2reg_nan_input_num; +output [8*1 +11:0] nan_preproc_pd; +output nan_preproc_pvld; +output pdp_rdma2dp_ready; +/////////////////////////////////////////////////////////////////// +reg [8*1 +11:0] datin_d; +reg cube_end_d1; +//reg [11:0] datin_info_d; +reg din_pvld_d1; +wire [31:0] dp2reg_inf_input_num=0; +wire [31:0] dp2reg_nan_input_num=0; +//reg [31:0] inf_in_count; +//reg [31:0] inf_in_num0; +//reg [31:0] inf_in_num1; +//reg [2:0] inf_num_in_8byte_d1; +reg layer_flag; +//reg mon_inf_in_count; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +//reg [31:0] nan_in_num0; +//reg [31:0] nan_in_num1; +//reg [2:0] nan_num_in_8byte_d1; +//reg [15:0] nan_preproc_pd0; +//reg [15:0] nan_preproc_pd1; +//reg [15:0] nan_preproc_pd2; +//reg [15:0] nan_preproc_pd3; +reg op_en_d1; +reg waiting_for_op_en; +reg wdma_layer_flag; +wire cube_end; +//wire [3:0] dat_is_inf; +//wire [3:0] dat_is_nan; +wire din_prdy_d1; +//wire fp16_en; +//wire [15:0] fp16_in_pd_0; +//wire [15:0] fp16_in_pd_1; +//wire [15:0] fp16_in_pd_2; +//wire [15:0] fp16_in_pd_3; +//wire [2:0] inf_num_in_8byte; +//wire [1:0] inf_num_in_8byte_0; +//wire [1:0] inf_num_in_8byte_1; +wire layer_end; +wire load_din; +wire load_din_d1; +//wire [2:0] nan_num_in_8byte; +//wire [1:0] nan_num_in_8byte_0; +//wire [1:0] nan_num_in_8byte_1; +wire onfly_en; +wire op_en_load; +wire pdp_rdma2dp_ready_f; +//wire tozero_en; +wire wdma_done; +//========================================== +//DP input side +//========================================== +//---------------------------------------- +assign pdp_rdma2dp_ready = pdp_rdma2dp_ready_f; +assign pdp_rdma2dp_ready_f = (~din_pvld_d1 | din_prdy_d1) & (~waiting_for_op_en); +assign load_din = pdp_rdma2dp_valid & pdp_rdma2dp_ready_f; +//---------------------------------------- +// assign tozero_en = reg2dp_nan_to_zero == 1'h1 ; +// assign fp16_en = (reg2dp_input_data[1:0]== 2'h2 ); +assign onfly_en = (reg2dp_flying_mode == 1'h0 ); +//---------------------------------------- +// assign fp16_in_pd_0 = pdp_rdma2dp_pd[15:0] ; +// assign fp16_in_pd_1 = pdp_rdma2dp_pd[31:16] ; +// assign fp16_in_pd_2 = pdp_rdma2dp_pd[47:32] ; +// assign fp16_in_pd_3 = pdp_rdma2dp_pd[63:48] ; +// +// assign dat_is_nan[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (|fp16_in_pd_0[9:0]); +// assign dat_is_nan[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (|fp16_in_pd_1[9:0]); +// assign dat_is_nan[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (|fp16_in_pd_2[9:0]); +// assign dat_is_nan[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (|fp16_in_pd_3[9:0]); +// +// assign dat_is_inf[0] = fp16_en & (&fp16_in_pd_0[14:10]) & (~(|fp16_in_pd_0[9:0])); +// assign dat_is_inf[1] = fp16_en & (&fp16_in_pd_1[14:10]) & (~(|fp16_in_pd_1[9:0])); +// assign dat_is_inf[2] = fp16_en & (&fp16_in_pd_2[14:10]) & (~(|fp16_in_pd_2[9:0])); +// assign dat_is_inf[3] = fp16_en & (&fp16_in_pd_3[14:10]) & (~(|fp16_in_pd_3[9:0])); +////////////////////////////////////////////////////////////////////// +//waiting for op_en +////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_en_d1 <= 1'b0; + end else begin + op_en_d1 <= reg2dp_op_en; + end +end +assign op_en_load = reg2dp_op_en & (~op_en_d1); +//assign layer_end = &{pdp_rdma2dp_pd[75],pdp_rdma2dp_pd[71]} & load_din; +assign layer_end = &{pdp_rdma2dp_pd[8*1 +11],pdp_rdma2dp_pd[8*1 +7]} & load_din; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_for_op_en <= 1'b1; + end else begin + if(layer_end & (~onfly_en)) + waiting_for_op_en <= 1'b1; + else if(op_en_load) begin + if(onfly_en) + waiting_for_op_en <= 1'b1; + else if(~onfly_en) + waiting_for_op_en <= 1'b0; + end + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & (~pdp_rdma2dp_ready_f) & pdp_rdma2dp_valid; + endproperty +// Cover 0 : "waiting_for_op_en & (~pdp_rdma2dp_ready_f) & pdp_rdma2dp_valid" + FUNCPOINT_RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__0_COV : cover property (RDMA_NewLayer_out_req_And_core_CurLayer_not_finish__0_cov); + `endif +`endif +//VCS coverage on +///////////////////////////////////// +//NaN process mode control +///////////////////////////////////// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_preproc_pd0 <= {16{1'b0}}; +// nan_preproc_pd1 <= {16{1'b0}}; +// nan_preproc_pd2 <= {16{1'b0}}; +// nan_preproc_pd3 <= {16{1'b0}}; +// datin_info_d <= {12{1'b0}}; +// end else begin +// if(load_din) begin +// nan_preproc_pd0 <= (dat_is_nan[0] & tozero_en) ? 16'd0 : fp16_in_pd_0; +// nan_preproc_pd1 <= (dat_is_nan[1] & tozero_en) ? 16'd0 : fp16_in_pd_1; +// nan_preproc_pd2 <= (dat_is_nan[2] & tozero_en) ? 16'd0 : fp16_in_pd_2; +// nan_preproc_pd3 <= (dat_is_nan[3] & tozero_en) ? 16'd0 : fp16_in_pd_3; +// datin_info_d <= pdp_rdma2dp_pd[75:64]; +// end +// end +// end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + datin_d <= 0; + end else begin + if(load_din) begin + datin_d <= pdp_rdma2dp_pd; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + din_pvld_d1 <= 1'b0; + end else begin + if(pdp_rdma2dp_valid & (~waiting_for_op_en)) + din_pvld_d1 <= 1'b1; + else if(din_prdy_d1) + din_pvld_d1 <= 1'b0; + end +end +assign din_prdy_d1 = nan_preproc_prdy; +//-------------output data ----------------- +//assign nan_preproc_pd = {datin_info_d,nan_preproc_pd3,nan_preproc_pd2,nan_preproc_pd1,nan_preproc_pd0}; +assign nan_preproc_pd = datin_d; +assign nan_preproc_pvld = din_pvld_d1; +// +// ///////////////////////////////////// +// //input NaN element count +// ///////////////////////////////////// +// assign cube_end = pdp_rdma2dp_pd[75]; +// +// assign nan_num_in_8byte_0[1:0] = dat_is_nan[0] + dat_is_nan[1]; +// assign nan_num_in_8byte_1[1:0] = dat_is_nan[2] + dat_is_nan[3]; +// assign nan_num_in_8byte[2:0] = nan_num_in_8byte_0 + nan_num_in_8byte_1; +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// cube_end_d1 <= 1'b0; +// end else begin +// if ((load_din) == 1'b1) begin +// cube_end_d1 <= cube_end; +// end +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// nan_num_in_8byte_d1 <= {3{1'b0}}; +// end else begin +// if ((load_din) == 1'b1) begin +// nan_num_in_8byte_d1 <= nan_num_in_8byte[2:0]; +// end +// end +// end +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// inf_num_in_8byte_d1 <= {3{1'b0}}; +// end else begin +// if ((load_din) == 1'b1) begin +// inf_num_in_8byte_d1 <= inf_num_in_8byte[2:0]; +// end +// end +// end +// +// assign load_din_d1 = din_pvld_d1 & din_prdy_d1; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din_d1) begin +// if(cube_end_d1) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_8byte_d1; +// end +// end +// end +// +// assign inf_num_in_8byte_0[1:0] = dat_is_inf[0] + dat_is_inf[1]; +// assign inf_num_in_8byte_1[1:0] = dat_is_inf[2] + dat_is_inf[3]; +// assign inf_num_in_8byte[2:0] = inf_num_in_8byte_0 + inf_num_in_8byte_1; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_inf_in_count,inf_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(load_din_d1) begin +// if(cube_end_d1) +// {mon_inf_in_count,inf_in_count[31:0]} <= 33'd0; +// else +// {mon_inf_in_count,inf_in_count[31:0]} <= inf_in_count + inf_num_in_8byte_d1; +// end +// end +// end +// +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// layer_flag <= 1'b0; +// nan_in_num1 <= {32{1'b0}}; +// inf_in_num1 <= {32{1'b0}}; +// nan_in_num0 <= {32{1'b0}}; +// inf_in_num0 <= {32{1'b0}}; +// end else begin +// if(load_din_d1 & cube_end_d1) begin +// layer_flag <= ~layer_flag; +// if(layer_flag) begin +// nan_in_num1 <= nan_in_count; +// inf_in_num1 <= inf_in_count; +// end else begin +// nan_in_num0 <= nan_in_count; +// inf_in_num0 <= inf_in_count; +// end +// end +// end +// end +// +// //adding dp2reg_done to latch the num and output a sigle one for each +// assign wdma_done = dp2reg_done; +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// wdma_layer_flag <= 1'b0; +// dp2reg_nan_input_num <= {32{1'b0}}; +// dp2reg_inf_input_num <= {32{1'b0}}; +// end else begin +// if(wdma_done) begin +// wdma_layer_flag <= ~wdma_layer_flag; +// if(wdma_layer_flag) begin +// dp2reg_nan_input_num <= nan_in_num1; +// dp2reg_inf_input_num <= inf_in_num1; +// end else begin +// dp2reg_nan_input_num <= nan_in_num0; +// dp2reg_inf_input_num <= inf_in_num0; +// end +// end +// end +// end +//============== +//function points +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_RDMA2CORE__rdma_layerDone_stall__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + waiting_for_op_en & (~pdp_rdma2dp_ready_f); + endproperty +// Cover 1 : "waiting_for_op_en & (~pdp_rdma2dp_ready_f)" + FUNCPOINT_PDP_RDMA2CORE__rdma_layerDone_stall__1_COV : cover property (PDP_RDMA2CORE__rdma_layerDone_stall__1_cov); + `endif +`endif +//VCS coverage on +////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_PDP_nan diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v new file mode 100644 index 0000000..835b561 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v @@ -0,0 +1,221 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_rdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_rdma ( + csb2pdp_rdma_req_pd //|< i + ,csb2pdp_rdma_req_pvld //|< i +,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,mcif2pdp_rd_rsp_pd //|< i + ,mcif2pdp_rd_rsp_valid //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pdp2mcif_rd_req_ready //|< i + ,pdp_rdma2dp_ready //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,csb2pdp_rdma_req_prdy //|> o + ,mcif2pdp_rd_rsp_ready //|> o + ,pdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,pdp2mcif_rd_req_pd //|> o + ,pdp2mcif_rd_req_valid //|> o + ,pdp_rdma2csb_resp_pd //|> o + ,pdp_rdma2csb_resp_valid //|> o + ,pdp_rdma2dp_pd //|> o + ,pdp_rdma2dp_valid //|> o + ,rdma2wdma_done //|> o + ); +/////////////////////////////////////////////////////////////////////////////////////////// + output rdma2wdma_done; +// + input nvdla_core_clk; + input nvdla_core_rstn; + input csb2pdp_rdma_req_pvld; /* data valid */ + output csb2pdp_rdma_req_prdy; /* data return handshake */ + input [62:0] csb2pdp_rdma_req_pd; + input mcif2pdp_rd_rsp_valid; /* data valid */ + output mcif2pdp_rd_rsp_ready; /* data return handshake */ + input [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd; + output pdp2mcif_rd_cdt_lat_fifo_pop; + output pdp2mcif_rd_req_valid; /* data valid */ + input pdp2mcif_rd_req_ready; /* data return handshake */ + output [32 +14:0] pdp2mcif_rd_req_pd; + output pdp_rdma2csb_resp_valid; /* data valid */ + output [33:0] pdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + output pdp_rdma2dp_valid; /* data valid */ + input pdp_rdma2dp_ready; /* data return handshake */ + output [8*1 +11:0] pdp_rdma2dp_pd; + input [31:0] pwrbus_ram_pd; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; +/////////////////////////////////////////////////////////////////////////////////////////// + wire [17:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire [31:0] dp2reg_d0_perf_read_stall; + wire [31:0] dp2reg_d1_perf_read_stall; + wire dp2reg_done; + wire eg2ig_done; + wire [17:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire nvdla_op_gated_clk; + wire [12:0] reg2dp_cube_in_channel; + wire [12:0] reg2dp_cube_in_height; + wire [12:0] reg2dp_cube_in_width; + wire [31:0] reg2dp_cya; + wire [0:0] reg2dp_dma_en; + wire reg2dp_flying_mode; + wire [1:0] reg2dp_input_data; + wire [3:0] reg2dp_kernel_stride_width; + wire [3:0] reg2dp_kernel_width; + wire [0:0] reg2dp_op_en; + wire [3:0] reg2dp_pad_width; + wire [9:0] reg2dp_partial_width_in_first; + wire [9:0] reg2dp_partial_width_in_last; + wire [9:0] reg2dp_partial_width_in_mid; + wire [7:0] reg2dp_split_num; + wire [31:0] reg2dp_src_base_addr_high; + wire [31:0] reg2dp_src_base_addr_low; + wire [31:0] reg2dp_src_line_stride; + wire [0:0] reg2dp_src_ram_type; + wire [31:0] reg2dp_src_surface_stride; + wire [31:0] reg2dp_surf_stride; + wire [0:0] slcg_op_en; +/////////////////////////////////////////////////////////////////////////////////////////// +//======================================= +// SLCG gen unit +//--------------------------------------- +NV_NVDLA_PDP_slcg u_slcg ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src (slcg_op_en[0]) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk) //|> w + ); +//&Connect slcg_en_src slcg_op_en & off_fly_en; +//======================================= +// Ingress: send read request to external mem +//--------------------------------------- + NV_NVDLA_PDP_RDMA_ig u_ig ( + .reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) //|< w + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< w + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) //|< w + ,.reg2dp_dma_en (reg2dp_dma_en[0]) //|< w + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) //|< w + ,.reg2dp_kernel_width (reg2dp_kernel_width[3:0]) //|< w + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_partial_width_in_first (reg2dp_partial_width_in_first[9:0]) //|< w + ,.reg2dp_partial_width_in_last (reg2dp_partial_width_in_last[9:0]) //|< w + ,.reg2dp_partial_width_in_mid (reg2dp_partial_width_in_mid[9:0]) //|< w + ,.reg2dp_split_num (reg2dp_split_num[7:0]) //|< w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w + ,.reg2dp_src_base_addr_low ({reg2dp_src_base_addr_low[31:0]}) + ,.reg2dp_src_line_stride ({reg2dp_src_line_stride[31:0]}) + ,.reg2dp_src_surface_stride ({reg2dp_src_surface_stride[31:0]}) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type[0]) + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) + ,.reg2dp_surf_stride (reg2dp_surf_stride[31:0]) + ,.eg2ig_done (eg2ig_done) + ,.nvdla_core_clk (nvdla_op_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid) + ,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready) + ,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd) // + ,.ig2cq_pvld (ig2cq_pvld) + ,.ig2cq_prdy (ig2cq_prdy) + ,.ig2cq_pd (ig2cq_pd[17:0]) + ); +//======================================= +// Context Queue: trace outstanding req, and pass info from Ig to Eg +//--------------------------------------- + NV_NVDLA_PDP_RDMA_cq u_cq ( + .nvdla_core_clk (nvdla_op_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ig2cq_prdy (ig2cq_prdy) + ,.ig2cq_pvld (ig2cq_pvld) + ,.ig2cq_pd (ig2cq_pd[17:0]) + ,.cq2eg_prdy (cq2eg_prdy) + ,.cq2eg_pvld (cq2eg_pvld) + ,.cq2eg_pd (cq2eg_pd[17:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +//======================================= +// Egress: get return data from external mem +//--------------------------------------- + NV_NVDLA_PDP_RDMA_eg u_eg ( + .reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.dp2reg_done (dp2reg_done) + ,.eg2ig_done (eg2ig_done) + ,.rdma2wdma_done (rdma2wdma_done) + ,.nvdla_core_clk (nvdla_op_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid) + ,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready) + ,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd) + ,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop) + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) + ,.cq2eg_pvld (cq2eg_pvld) + ,.cq2eg_prdy (cq2eg_prdy) + ,.cq2eg_pd (cq2eg_pd[17:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +//======================================== +//CFG: Configure Registers +//---------------------------------------- + NV_NVDLA_PDP_RDMA_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd[62:0]) + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd[33:0]) + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) + ,.reg2dp_kernel_width (reg2dp_kernel_width[3:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_width (reg2dp_pad_width[3:0]) + ,.reg2dp_partial_width_in_first (reg2dp_partial_width_in_first[9:0]) + ,.reg2dp_partial_width_in_last (reg2dp_partial_width_in_last[9:0]) + ,.reg2dp_partial_width_in_mid (reg2dp_partial_width_in_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) + ,.slcg_op_en (slcg_op_en) + ); +//&Forget dangle .*; +endmodule // NV_NVDLA_PDP_rdma diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v.vcp new file mode 100644 index 0000000..835b561 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v.vcp @@ -0,0 +1,221 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_rdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_PDP_rdma ( + csb2pdp_rdma_req_pd //|< i + ,csb2pdp_rdma_req_pvld //|< i +,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,mcif2pdp_rd_rsp_pd //|< i + ,mcif2pdp_rd_rsp_valid //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pdp2mcif_rd_req_ready //|< i + ,pdp_rdma2dp_ready //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,csb2pdp_rdma_req_prdy //|> o + ,mcif2pdp_rd_rsp_ready //|> o + ,pdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,pdp2mcif_rd_req_pd //|> o + ,pdp2mcif_rd_req_valid //|> o + ,pdp_rdma2csb_resp_pd //|> o + ,pdp_rdma2csb_resp_valid //|> o + ,pdp_rdma2dp_pd //|> o + ,pdp_rdma2dp_valid //|> o + ,rdma2wdma_done //|> o + ); +/////////////////////////////////////////////////////////////////////////////////////////// + output rdma2wdma_done; +// + input nvdla_core_clk; + input nvdla_core_rstn; + input csb2pdp_rdma_req_pvld; /* data valid */ + output csb2pdp_rdma_req_prdy; /* data return handshake */ + input [62:0] csb2pdp_rdma_req_pd; + input mcif2pdp_rd_rsp_valid; /* data valid */ + output mcif2pdp_rd_rsp_ready; /* data return handshake */ + input [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd; + output pdp2mcif_rd_cdt_lat_fifo_pop; + output pdp2mcif_rd_req_valid; /* data valid */ + input pdp2mcif_rd_req_ready; /* data return handshake */ + output [32 +14:0] pdp2mcif_rd_req_pd; + output pdp_rdma2csb_resp_valid; /* data valid */ + output [33:0] pdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ + output pdp_rdma2dp_valid; /* data valid */ + input pdp_rdma2dp_ready; /* data return handshake */ + output [8*1 +11:0] pdp_rdma2dp_pd; + input [31:0] pwrbus_ram_pd; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; +/////////////////////////////////////////////////////////////////////////////////////////// + wire [17:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire [31:0] dp2reg_d0_perf_read_stall; + wire [31:0] dp2reg_d1_perf_read_stall; + wire dp2reg_done; + wire eg2ig_done; + wire [17:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire nvdla_op_gated_clk; + wire [12:0] reg2dp_cube_in_channel; + wire [12:0] reg2dp_cube_in_height; + wire [12:0] reg2dp_cube_in_width; + wire [31:0] reg2dp_cya; + wire [0:0] reg2dp_dma_en; + wire reg2dp_flying_mode; + wire [1:0] reg2dp_input_data; + wire [3:0] reg2dp_kernel_stride_width; + wire [3:0] reg2dp_kernel_width; + wire [0:0] reg2dp_op_en; + wire [3:0] reg2dp_pad_width; + wire [9:0] reg2dp_partial_width_in_first; + wire [9:0] reg2dp_partial_width_in_last; + wire [9:0] reg2dp_partial_width_in_mid; + wire [7:0] reg2dp_split_num; + wire [31:0] reg2dp_src_base_addr_high; + wire [31:0] reg2dp_src_base_addr_low; + wire [31:0] reg2dp_src_line_stride; + wire [0:0] reg2dp_src_ram_type; + wire [31:0] reg2dp_src_surface_stride; + wire [31:0] reg2dp_surf_stride; + wire [0:0] slcg_op_en; +/////////////////////////////////////////////////////////////////////////////////////////// +//======================================= +// SLCG gen unit +//--------------------------------------- +NV_NVDLA_PDP_slcg u_slcg ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.slcg_en_src (slcg_op_en[0]) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk) //|> w + ); +//&Connect slcg_en_src slcg_op_en & off_fly_en; +//======================================= +// Ingress: send read request to external mem +//--------------------------------------- + NV_NVDLA_PDP_RDMA_ig u_ig ( + .reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) //|< w + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) //|< w + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) //|< w + ,.reg2dp_dma_en (reg2dp_dma_en[0]) //|< w + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) //|< w + ,.reg2dp_kernel_width (reg2dp_kernel_width[3:0]) //|< w + ,.reg2dp_op_en (reg2dp_op_en[0]) //|< w + ,.reg2dp_partial_width_in_first (reg2dp_partial_width_in_first[9:0]) //|< w + ,.reg2dp_partial_width_in_last (reg2dp_partial_width_in_last[9:0]) //|< w + ,.reg2dp_partial_width_in_mid (reg2dp_partial_width_in_mid[9:0]) //|< w + ,.reg2dp_split_num (reg2dp_split_num[7:0]) //|< w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w + ,.reg2dp_src_base_addr_low ({reg2dp_src_base_addr_low[31:0]}) + ,.reg2dp_src_line_stride ({reg2dp_src_line_stride[31:0]}) + ,.reg2dp_src_surface_stride ({reg2dp_src_surface_stride[31:0]}) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type[0]) + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) + ,.reg2dp_surf_stride (reg2dp_surf_stride[31:0]) + ,.eg2ig_done (eg2ig_done) + ,.nvdla_core_clk (nvdla_op_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid) + ,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready) + ,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd) // + ,.ig2cq_pvld (ig2cq_pvld) + ,.ig2cq_prdy (ig2cq_prdy) + ,.ig2cq_pd (ig2cq_pd[17:0]) + ); +//======================================= +// Context Queue: trace outstanding req, and pass info from Ig to Eg +//--------------------------------------- + NV_NVDLA_PDP_RDMA_cq u_cq ( + .nvdla_core_clk (nvdla_op_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.ig2cq_prdy (ig2cq_prdy) + ,.ig2cq_pvld (ig2cq_pvld) + ,.ig2cq_pd (ig2cq_pd[17:0]) + ,.cq2eg_prdy (cq2eg_prdy) + ,.cq2eg_pvld (cq2eg_pvld) + ,.cq2eg_pd (cq2eg_pd[17:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +//======================================= +// Egress: get return data from external mem +//--------------------------------------- + NV_NVDLA_PDP_RDMA_eg u_eg ( + .reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.dp2reg_done (dp2reg_done) + ,.eg2ig_done (eg2ig_done) + ,.rdma2wdma_done (rdma2wdma_done) + ,.nvdla_core_clk (nvdla_op_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid) + ,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready) + ,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd) + ,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop) + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) + ,.cq2eg_pvld (cq2eg_pvld) + ,.cq2eg_prdy (cq2eg_prdy) + ,.cq2eg_pd (cq2eg_pd[17:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +//======================================== +//CFG: Configure Registers +//---------------------------------------- + NV_NVDLA_PDP_RDMA_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd[62:0]) + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) + ,.dp2reg_d0_perf_read_stall (dp2reg_d0_perf_read_stall[31:0]) + ,.dp2reg_d1_perf_read_stall (dp2reg_d1_perf_read_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd[33:0]) + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) + ,.reg2dp_kernel_width (reg2dp_kernel_width[3:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_width (reg2dp_pad_width[3:0]) + ,.reg2dp_partial_width_in_first (reg2dp_partial_width_in_first[9:0]) + ,.reg2dp_partial_width_in_last (reg2dp_partial_width_in_last[9:0]) + ,.reg2dp_partial_width_in_mid (reg2dp_partial_width_in_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) + ,.slcg_op_en (slcg_op_en) + ); +//&Forget dangle .*; +endmodule // NV_NVDLA_PDP_rdma diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v new file mode 100644 index 0000000..597e457 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v @@ -0,0 +1,1651 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2pdp_req_pd //|< i + ,csb2pdp_req_pvld //|< i + ,dp2reg_d0_perf_write_stall //|< i + ,dp2reg_d1_perf_write_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_inf_input_num //|< i + ,dp2reg_nan_input_num //|< i + ,dp2reg_nan_output_num //|< i + ,csb2pdp_req_prdy //|> o + ,pdp2csb_resp_pd //|> o + ,pdp2csb_resp_valid //|> o + ,reg2dp_cube_in_channel //|> o + ,reg2dp_cube_in_height //|> o + ,reg2dp_cube_in_width //|> o + ,reg2dp_cube_out_channel //|> o + ,reg2dp_cube_out_height //|> o + ,reg2dp_cube_out_width //|> o + ,reg2dp_cya //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_dst_base_addr_high //|> o + ,reg2dp_dst_base_addr_low //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_ram_type //|> o + ,reg2dp_dst_surface_stride //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_input_data //|> o + ,reg2dp_interrupt_ptr //|> o + ,reg2dp_kernel_height //|> o + ,reg2dp_kernel_stride_height //|> o + ,reg2dp_kernel_stride_width //|> o + ,reg2dp_kernel_width //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_bottom //|> o + ,reg2dp_pad_left //|> o + ,reg2dp_pad_right //|> o + ,reg2dp_pad_top //|> o + ,reg2dp_pad_value_1x //|> o + ,reg2dp_pad_value_2x //|> o + ,reg2dp_pad_value_3x //|> o + ,reg2dp_pad_value_4x //|> o + ,reg2dp_pad_value_5x //|> o + ,reg2dp_pad_value_6x //|> o + ,reg2dp_pad_value_7x //|> o + ,reg2dp_partial_width_in_first //|> o + ,reg2dp_partial_width_in_last //|> o + ,reg2dp_partial_width_in_mid //|> o + ,reg2dp_partial_width_out_first //|> o + ,reg2dp_partial_width_out_last //|> o + ,reg2dp_partial_width_out_mid //|> o + ,reg2dp_pooling_method //|> o + ,reg2dp_recip_kernel_height //|> o + ,reg2dp_recip_kernel_width //|> o + ,reg2dp_split_num //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_surface_stride //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2pdp_req_pd; +input csb2pdp_req_pvld; +input [31:0] dp2reg_d0_perf_write_stall; +input [31:0] dp2reg_d1_perf_write_stall; +input dp2reg_done; +input [31:0] dp2reg_inf_input_num; +input [31:0] dp2reg_nan_input_num; +input [31:0] dp2reg_nan_output_num; +output csb2pdp_req_prdy; +output [33:0] pdp2csb_resp_pd; +output pdp2csb_resp_valid; +output [12:0] reg2dp_cube_in_channel; +output [12:0] reg2dp_cube_in_height; +output [12:0] reg2dp_cube_in_width; +output [12:0] reg2dp_cube_out_channel; +output [12:0] reg2dp_cube_out_height; +output [12:0] reg2dp_cube_out_width; +output [31:0] reg2dp_cya; +output reg2dp_dma_en; +output [31:0] reg2dp_dst_base_addr_high; +output [31:0] reg2dp_dst_base_addr_low; +output [31:0] reg2dp_dst_line_stride; +output reg2dp_dst_ram_type; +output [31:0] reg2dp_dst_surface_stride; +output reg2dp_flying_mode; +output [1:0] reg2dp_input_data; +output reg2dp_interrupt_ptr; +output [3:0] reg2dp_kernel_height; +output [3:0] reg2dp_kernel_stride_height; +output [3:0] reg2dp_kernel_stride_width; +output [3:0] reg2dp_kernel_width; +output reg2dp_nan_to_zero; +output reg2dp_op_en; +output [2:0] reg2dp_pad_bottom; +output [2:0] reg2dp_pad_left; +output [2:0] reg2dp_pad_right; +output [2:0] reg2dp_pad_top; +output [18:0] reg2dp_pad_value_1x; +output [18:0] reg2dp_pad_value_2x; +output [18:0] reg2dp_pad_value_3x; +output [18:0] reg2dp_pad_value_4x; +output [18:0] reg2dp_pad_value_5x; +output [18:0] reg2dp_pad_value_6x; +output [18:0] reg2dp_pad_value_7x; +output [9:0] reg2dp_partial_width_in_first; +output [9:0] reg2dp_partial_width_in_last; +output [9:0] reg2dp_partial_width_in_mid; +output [9:0] reg2dp_partial_width_out_first; +output [9:0] reg2dp_partial_width_out_last; +output [9:0] reg2dp_partial_width_out_mid; +output [1:0] reg2dp_pooling_method; +output [16:0] reg2dp_recip_kernel_height; +output [16:0] reg2dp_recip_kernel_width; +output [7:0] reg2dp_split_num; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output [31:0] reg2dp_src_surface_stride; +output [2:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [12:0] reg2dp_d0_cube_in_channel; +wire [12:0] reg2dp_d0_cube_in_height; +wire [12:0] reg2dp_d0_cube_in_width; +wire [12:0] reg2dp_d0_cube_out_channel; +wire [12:0] reg2dp_d0_cube_out_height; +wire [12:0] reg2dp_d0_cube_out_width; +wire [31:0] reg2dp_d0_cya; +wire reg2dp_d0_dma_en; +wire [31:0] reg2dp_d0_dst_base_addr_high; +wire [31:0] reg2dp_d0_dst_base_addr_low; +wire [31:0] reg2dp_d0_dst_line_stride; +wire reg2dp_d0_dst_ram_type; +wire [31:0] reg2dp_d0_dst_surface_stride; +wire reg2dp_d0_flying_mode; +wire [1:0] reg2dp_d0_input_data; +wire [3:0] reg2dp_d0_kernel_height; +wire [3:0] reg2dp_d0_kernel_stride_height; +wire [3:0] reg2dp_d0_kernel_stride_width; +wire [3:0] reg2dp_d0_kernel_width; +wire reg2dp_d0_nan_to_zero; +wire reg2dp_d0_op_en_trigger; +wire [2:0] reg2dp_d0_pad_bottom; +wire [2:0] reg2dp_d0_pad_left; +wire [2:0] reg2dp_d0_pad_right; +wire [2:0] reg2dp_d0_pad_top; +wire [18:0] reg2dp_d0_pad_value_1x; +wire [18:0] reg2dp_d0_pad_value_2x; +wire [18:0] reg2dp_d0_pad_value_3x; +wire [18:0] reg2dp_d0_pad_value_4x; +wire [18:0] reg2dp_d0_pad_value_5x; +wire [18:0] reg2dp_d0_pad_value_6x; +wire [18:0] reg2dp_d0_pad_value_7x; +wire [9:0] reg2dp_d0_partial_width_in_first; +wire [9:0] reg2dp_d0_partial_width_in_last; +wire [9:0] reg2dp_d0_partial_width_in_mid; +wire [9:0] reg2dp_d0_partial_width_out_first; +wire [9:0] reg2dp_d0_partial_width_out_last; +wire [9:0] reg2dp_d0_partial_width_out_mid; +wire [1:0] reg2dp_d0_pooling_method; +wire [16:0] reg2dp_d0_recip_kernel_height; +wire [16:0] reg2dp_d0_recip_kernel_width; +wire [7:0] reg2dp_d0_split_num; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d1_cube_in_channel; +wire [12:0] reg2dp_d1_cube_in_height; +wire [12:0] reg2dp_d1_cube_in_width; +wire [12:0] reg2dp_d1_cube_out_channel; +wire [12:0] reg2dp_d1_cube_out_height; +wire [12:0] reg2dp_d1_cube_out_width; +wire [31:0] reg2dp_d1_cya; +wire reg2dp_d1_dma_en; +wire [31:0] reg2dp_d1_dst_base_addr_high; +wire [31:0] reg2dp_d1_dst_base_addr_low; +wire [31:0] reg2dp_d1_dst_line_stride; +wire reg2dp_d1_dst_ram_type; +wire [31:0] reg2dp_d1_dst_surface_stride; +wire reg2dp_d1_flying_mode; +wire [1:0] reg2dp_d1_input_data; +wire [3:0] reg2dp_d1_kernel_height; +wire [3:0] reg2dp_d1_kernel_stride_height; +wire [3:0] reg2dp_d1_kernel_stride_width; +wire [3:0] reg2dp_d1_kernel_width; +wire reg2dp_d1_nan_to_zero; +wire reg2dp_d1_op_en_trigger; +wire [2:0] reg2dp_d1_pad_bottom; +wire [2:0] reg2dp_d1_pad_left; +wire [2:0] reg2dp_d1_pad_right; +wire [2:0] reg2dp_d1_pad_top; +wire [18:0] reg2dp_d1_pad_value_1x; +wire [18:0] reg2dp_d1_pad_value_2x; +wire [18:0] reg2dp_d1_pad_value_3x; +wire [18:0] reg2dp_d1_pad_value_4x; +wire [18:0] reg2dp_d1_pad_value_5x; +wire [18:0] reg2dp_d1_pad_value_6x; +wire [18:0] reg2dp_d1_pad_value_7x; +wire [9:0] reg2dp_d1_partial_width_in_first; +wire [9:0] reg2dp_d1_partial_width_in_last; +wire [9:0] reg2dp_d1_partial_width_in_mid; +wire [9:0] reg2dp_d1_partial_width_out_first; +wire [9:0] reg2dp_d1_partial_width_out_last; +wire [9:0] reg2dp_d1_partial_width_out_mid; +wire [1:0] reg2dp_d1_pooling_method; +wire [16:0] reg2dp_d1_recip_kernel_height; +wire [16:0] reg2dp_d1_recip_kernel_width; +wire [7:0] reg2dp_d1_split_num; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [2:0] slcg_op_en_d0; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_inf_input_num; +reg [31:0] dp2reg_d0_inf_input_num_w; +reg [31:0] dp2reg_d0_nan_input_num; +reg [31:0] dp2reg_d0_nan_input_num_w; +reg [31:0] dp2reg_d0_nan_output_num; +reg [31:0] dp2reg_d0_nan_output_num_w; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_inf_input_num; +reg [31:0] dp2reg_d1_inf_input_num_w; +reg [31:0] dp2reg_d1_nan_input_num; +reg [31:0] dp2reg_d1_nan_input_num_w; +reg [31:0] dp2reg_d1_nan_output_num; +reg [31:0] dp2reg_d1_nan_output_num_w; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [33:0] pdp2csb_resp_pd; +reg pdp2csb_resp_valid; +reg [12:0] reg2dp_cube_in_channel; +reg [12:0] reg2dp_cube_in_height; +reg [12:0] reg2dp_cube_in_width; +reg [12:0] reg2dp_cube_out_channel; +reg [12:0] reg2dp_cube_out_height; +reg [12:0] reg2dp_cube_out_width; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_dma_en; +reg [31:0] reg2dp_dst_base_addr_high; +reg [31:0] reg2dp_dst_base_addr_low; +reg [31:0] reg2dp_dst_line_stride; +reg reg2dp_dst_ram_type; +reg [31:0] reg2dp_dst_surface_stride; +reg reg2dp_flying_mode; +reg [1:0] reg2dp_input_data; +reg [3:0] reg2dp_kernel_height; +reg [3:0] reg2dp_kernel_stride_height; +reg [3:0] reg2dp_kernel_stride_width; +reg [3:0] reg2dp_kernel_width; +reg reg2dp_nan_to_zero; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [2:0] reg2dp_pad_bottom; +reg [2:0] reg2dp_pad_left; +reg [2:0] reg2dp_pad_right; +reg [2:0] reg2dp_pad_top; +reg [18:0] reg2dp_pad_value_1x; +reg [18:0] reg2dp_pad_value_2x; +reg [18:0] reg2dp_pad_value_3x; +reg [18:0] reg2dp_pad_value_4x; +reg [18:0] reg2dp_pad_value_5x; +reg [18:0] reg2dp_pad_value_6x; +reg [18:0] reg2dp_pad_value_7x; +reg [9:0] reg2dp_partial_width_in_first; +reg [9:0] reg2dp_partial_width_in_last; +reg [9:0] reg2dp_partial_width_in_mid; +reg [9:0] reg2dp_partial_width_out_first; +reg [9:0] reg2dp_partial_width_out_last; +reg [9:0] reg2dp_partial_width_out_mid; +reg [1:0] reg2dp_pooling_method; +reg [16:0] reg2dp_recip_kernel_height; +reg [16:0] reg2dp_recip_kernel_width; +reg [7:0] reg2dp_split_num; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg [31:0] reg2dp_src_surface_stride; +reg [62:0] req_pd; +reg req_pvld; +reg [2:0] slcg_op_en_d1; +reg [2:0] slcg_op_en_d2; +reg [2:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_PDP_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_PDP_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d0_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d0_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d0_cube_in_width[12:0]) //|> w + ,.cube_out_channel (reg2dp_d0_cube_out_channel[12:0]) //|> w + ,.cube_out_height (reg2dp_d0_cube_out_height[12:0]) //|> w + ,.cube_out_width (reg2dp_d0_cube_out_width[12:0]) //|> w + ,.input_data (reg2dp_d0_input_data[1:0]) //|> w + ,.dst_base_addr_high (reg2dp_d0_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d0_dst_base_addr_low[31:0]) //|> w + ,.dst_line_stride (reg2dp_d0_dst_line_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d0_dst_ram_type) //|> w + ,.dst_surface_stride (reg2dp_d0_dst_surface_stride[31:0]) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.pooling_method (reg2dp_d0_pooling_method[1:0]) //|> w + ,.split_num (reg2dp_d0_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d0_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d0_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d0_partial_width_in_mid[9:0]) //|> w + ,.partial_width_out_first (reg2dp_d0_partial_width_out_first[9:0]) //|> w + ,.partial_width_out_last (reg2dp_d0_partial_width_out_last[9:0]) //|> w + ,.partial_width_out_mid (reg2dp_d0_partial_width_out_mid[9:0]) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.kernel_height (reg2dp_d0_kernel_height[3:0]) //|> w + ,.kernel_stride_height (reg2dp_d0_kernel_stride_height[3:0]) //|> w + ,.kernel_stride_width (reg2dp_d0_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d0_kernel_width[3:0]) //|> w + ,.pad_bottom (reg2dp_d0_pad_bottom[2:0]) //|> w + ,.pad_left (reg2dp_d0_pad_left[2:0]) //|> w + ,.pad_right (reg2dp_d0_pad_right[2:0]) //|> w + ,.pad_top (reg2dp_d0_pad_top[2:0]) //|> w + ,.pad_value_1x (reg2dp_d0_pad_value_1x[18:0]) //|> w + ,.pad_value_2x (reg2dp_d0_pad_value_2x[18:0]) //|> w + ,.pad_value_3x (reg2dp_d0_pad_value_3x[18:0]) //|> w + ,.pad_value_4x (reg2dp_d0_pad_value_4x[18:0]) //|> w + ,.pad_value_5x (reg2dp_d0_pad_value_5x[18:0]) //|> w + ,.pad_value_6x (reg2dp_d0_pad_value_6x[18:0]) //|> w + ,.pad_value_7x (reg2dp_d0_pad_value_7x[18:0]) //|> w + ,.recip_kernel_height (reg2dp_d0_recip_kernel_height[16:0]) //|> w + ,.recip_kernel_width (reg2dp_d0_recip_kernel_width[16:0]) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.inf_input_num (dp2reg_d0_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d0_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d0_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d0_op_en) //|< r + ,.perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) //|< i + ); +NV_NVDLA_PDP_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d1_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d1_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d1_cube_in_width[12:0]) //|> w + ,.cube_out_channel (reg2dp_d1_cube_out_channel[12:0]) //|> w + ,.cube_out_height (reg2dp_d1_cube_out_height[12:0]) //|> w + ,.cube_out_width (reg2dp_d1_cube_out_width[12:0]) //|> w + ,.input_data (reg2dp_d1_input_data[1:0]) //|> w + ,.dst_base_addr_high (reg2dp_d1_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d1_dst_base_addr_low[31:0]) //|> w + ,.dst_line_stride (reg2dp_d1_dst_line_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d1_dst_ram_type) //|> w + ,.dst_surface_stride (reg2dp_d1_dst_surface_stride[31:0]) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.pooling_method (reg2dp_d1_pooling_method[1:0]) //|> w + ,.split_num (reg2dp_d1_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d1_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d1_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d1_partial_width_in_mid[9:0]) //|> w + ,.partial_width_out_first (reg2dp_d1_partial_width_out_first[9:0]) //|> w + ,.partial_width_out_last (reg2dp_d1_partial_width_out_last[9:0]) //|> w + ,.partial_width_out_mid (reg2dp_d1_partial_width_out_mid[9:0]) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.kernel_height (reg2dp_d1_kernel_height[3:0]) //|> w + ,.kernel_stride_height (reg2dp_d1_kernel_stride_height[3:0]) //|> w + ,.kernel_stride_width (reg2dp_d1_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d1_kernel_width[3:0]) //|> w + ,.pad_bottom (reg2dp_d1_pad_bottom[2:0]) //|> w + ,.pad_left (reg2dp_d1_pad_left[2:0]) //|> w + ,.pad_right (reg2dp_d1_pad_right[2:0]) //|> w + ,.pad_top (reg2dp_d1_pad_top[2:0]) //|> w + ,.pad_value_1x (reg2dp_d1_pad_value_1x[18:0]) //|> w + ,.pad_value_2x (reg2dp_d1_pad_value_2x[18:0]) //|> w + ,.pad_value_3x (reg2dp_d1_pad_value_3x[18:0]) //|> w + ,.pad_value_4x (reg2dp_d1_pad_value_4x[18:0]) //|> w + ,.pad_value_5x (reg2dp_d1_pad_value_5x[18:0]) //|> w + ,.pad_value_6x (reg2dp_d1_pad_value_6x[18:0]) //|> w + ,.pad_value_7x (reg2dp_d1_pad_value_7x[18:0]) //|> w + ,.recip_kernel_height (reg2dp_d1_recip_kernel_height[16:0]) //|> w + ,.recip_kernel_width (reg2dp_d1_recip_kernel_width[16:0]) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.inf_input_num (dp2reg_d1_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d1_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d1_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d1_op_en) //|< r + ,.perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {3{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {3{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {3{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {3{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hd008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hd008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hd008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2pdp_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2pdp_req_pvld) == 1'b1) begin + req_pd <= csb2pdp_req_pd; +// VCS coverage off + end else if ((csb2pdp_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2pdp_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2pdp_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + pdp2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + pdp2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2csb_resp_valid <= 1'b0; + end else begin + pdp2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_channel + or reg2dp_d0_cube_in_channel + ) begin + reg2dp_cube_in_channel = dp2reg_consumer ? reg2dp_d1_cube_in_channel : reg2dp_d0_cube_in_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_height + or reg2dp_d0_cube_in_height + ) begin + reg2dp_cube_in_height = dp2reg_consumer ? reg2dp_d1_cube_in_height : reg2dp_d0_cube_in_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_width + or reg2dp_d0_cube_in_width + ) begin + reg2dp_cube_in_width = dp2reg_consumer ? reg2dp_d1_cube_in_width : reg2dp_d0_cube_in_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_out_channel + or reg2dp_d0_cube_out_channel + ) begin + reg2dp_cube_out_channel = dp2reg_consumer ? reg2dp_d1_cube_out_channel : reg2dp_d0_cube_out_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_out_height + or reg2dp_d0_cube_out_height + ) begin + reg2dp_cube_out_height = dp2reg_consumer ? reg2dp_d1_cube_out_height : reg2dp_d0_cube_out_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_out_width + or reg2dp_d0_cube_out_width + ) begin + reg2dp_cube_out_width = dp2reg_consumer ? reg2dp_d1_cube_out_width : reg2dp_d0_cube_out_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data + or reg2dp_d0_input_data + ) begin + reg2dp_input_data = dp2reg_consumer ? reg2dp_d1_input_data : reg2dp_d0_input_data; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_high + or reg2dp_d0_dst_base_addr_high + ) begin + reg2dp_dst_base_addr_high = dp2reg_consumer ? reg2dp_d1_dst_base_addr_high : reg2dp_d0_dst_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_low + or reg2dp_d0_dst_base_addr_low + ) begin + reg2dp_dst_base_addr_low = dp2reg_consumer ? reg2dp_d1_dst_base_addr_low : reg2dp_d0_dst_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_line_stride + or reg2dp_d0_dst_line_stride + ) begin + reg2dp_dst_line_stride = dp2reg_consumer ? reg2dp_d1_dst_line_stride : reg2dp_d0_dst_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_ram_type + or reg2dp_d0_dst_ram_type + ) begin + reg2dp_dst_ram_type = dp2reg_consumer ? reg2dp_d1_dst_ram_type : reg2dp_d0_dst_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_surface_stride + or reg2dp_d0_dst_surface_stride + ) begin + reg2dp_dst_surface_stride = dp2reg_consumer ? reg2dp_d1_dst_surface_stride : reg2dp_d0_dst_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_pooling_method + or reg2dp_d0_pooling_method + ) begin + reg2dp_pooling_method = dp2reg_consumer ? reg2dp_d1_pooling_method : reg2dp_d0_pooling_method; +end +always @( + dp2reg_consumer + or reg2dp_d1_split_num + or reg2dp_d0_split_num + ) begin + reg2dp_split_num = dp2reg_consumer ? reg2dp_d1_split_num : reg2dp_d0_split_num; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_first + or reg2dp_d0_partial_width_in_first + ) begin + reg2dp_partial_width_in_first = dp2reg_consumer ? reg2dp_d1_partial_width_in_first : reg2dp_d0_partial_width_in_first; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_last + or reg2dp_d0_partial_width_in_last + ) begin + reg2dp_partial_width_in_last = dp2reg_consumer ? reg2dp_d1_partial_width_in_last : reg2dp_d0_partial_width_in_last; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_mid + or reg2dp_d0_partial_width_in_mid + ) begin + reg2dp_partial_width_in_mid = dp2reg_consumer ? reg2dp_d1_partial_width_in_mid : reg2dp_d0_partial_width_in_mid; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_out_first + or reg2dp_d0_partial_width_out_first + ) begin + reg2dp_partial_width_out_first = dp2reg_consumer ? reg2dp_d1_partial_width_out_first : reg2dp_d0_partial_width_out_first; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_out_last + or reg2dp_d0_partial_width_out_last + ) begin + reg2dp_partial_width_out_last = dp2reg_consumer ? reg2dp_d1_partial_width_out_last : reg2dp_d0_partial_width_out_last; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_out_mid + or reg2dp_d0_partial_width_out_mid + ) begin + reg2dp_partial_width_out_mid = dp2reg_consumer ? reg2dp_d1_partial_width_out_mid : reg2dp_d0_partial_width_out_mid; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_height + or reg2dp_d0_kernel_height + ) begin + reg2dp_kernel_height = dp2reg_consumer ? reg2dp_d1_kernel_height : reg2dp_d0_kernel_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_stride_height + or reg2dp_d0_kernel_stride_height + ) begin + reg2dp_kernel_stride_height = dp2reg_consumer ? reg2dp_d1_kernel_stride_height : reg2dp_d0_kernel_stride_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_stride_width + or reg2dp_d0_kernel_stride_width + ) begin + reg2dp_kernel_stride_width = dp2reg_consumer ? reg2dp_d1_kernel_stride_width : reg2dp_d0_kernel_stride_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_width + or reg2dp_d0_kernel_width + ) begin + reg2dp_kernel_width = dp2reg_consumer ? reg2dp_d1_kernel_width : reg2dp_d0_kernel_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_bottom + or reg2dp_d0_pad_bottom + ) begin + reg2dp_pad_bottom = dp2reg_consumer ? reg2dp_d1_pad_bottom : reg2dp_d0_pad_bottom; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_left + or reg2dp_d0_pad_left + ) begin + reg2dp_pad_left = dp2reg_consumer ? reg2dp_d1_pad_left : reg2dp_d0_pad_left; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_right + or reg2dp_d0_pad_right + ) begin + reg2dp_pad_right = dp2reg_consumer ? reg2dp_d1_pad_right : reg2dp_d0_pad_right; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_top + or reg2dp_d0_pad_top + ) begin + reg2dp_pad_top = dp2reg_consumer ? reg2dp_d1_pad_top : reg2dp_d0_pad_top; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_1x + or reg2dp_d0_pad_value_1x + ) begin + reg2dp_pad_value_1x = dp2reg_consumer ? reg2dp_d1_pad_value_1x : reg2dp_d0_pad_value_1x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_2x + or reg2dp_d0_pad_value_2x + ) begin + reg2dp_pad_value_2x = dp2reg_consumer ? reg2dp_d1_pad_value_2x : reg2dp_d0_pad_value_2x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_3x + or reg2dp_d0_pad_value_3x + ) begin + reg2dp_pad_value_3x = dp2reg_consumer ? reg2dp_d1_pad_value_3x : reg2dp_d0_pad_value_3x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_4x + or reg2dp_d0_pad_value_4x + ) begin + reg2dp_pad_value_4x = dp2reg_consumer ? reg2dp_d1_pad_value_4x : reg2dp_d0_pad_value_4x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_5x + or reg2dp_d0_pad_value_5x + ) begin + reg2dp_pad_value_5x = dp2reg_consumer ? reg2dp_d1_pad_value_5x : reg2dp_d0_pad_value_5x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_6x + or reg2dp_d0_pad_value_6x + ) begin + reg2dp_pad_value_6x = dp2reg_consumer ? reg2dp_d1_pad_value_6x : reg2dp_d0_pad_value_6x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_7x + or reg2dp_d0_pad_value_7x + ) begin + reg2dp_pad_value_7x = dp2reg_consumer ? reg2dp_d1_pad_value_7x : reg2dp_d0_pad_value_7x; +end +always @( + dp2reg_consumer + or reg2dp_d1_recip_kernel_height + or reg2dp_d0_recip_kernel_height + ) begin + reg2dp_recip_kernel_height = dp2reg_consumer ? reg2dp_d1_recip_kernel_height : reg2dp_d0_recip_kernel_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_recip_kernel_width + or reg2dp_d0_recip_kernel_width + ) begin + reg2dp_recip_kernel_width = dp2reg_consumer ? reg2dp_d1_recip_kernel_width : reg2dp_d0_recip_kernel_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//assign reg2dp_lut_data = reg_wr_data[::range(15)]; +assign reg2dp_interrupt_ptr = dp2reg_consumer; +//////// for general counting register //////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for NaN and infinity counting registers //////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_nan_input_num + or dp2reg_d0_clr + or dp2reg_d0_nan_input_num + ) begin + dp2reg_d0_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_nan_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_input_num + or dp2reg_d0_clr + or dp2reg_d0_inf_input_num + ) begin + dp2reg_d0_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_inf_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_nan_output_num + or dp2reg_d0_clr + or dp2reg_d0_nan_output_num + ) begin + dp2reg_d0_nan_output_num_w = (dp2reg_d0_set) ? dp2reg_nan_output_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_input_num <= dp2reg_d0_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_input_num <= dp2reg_d0_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_output_num <= dp2reg_d0_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_nan_input_num + or dp2reg_d1_clr + or dp2reg_d1_nan_input_num + ) begin + dp2reg_d1_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_nan_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_input_num + or dp2reg_d1_clr + or dp2reg_d1_inf_input_num + ) begin + dp2reg_d1_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_inf_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_nan_output_num + or dp2reg_d1_clr + or dp2reg_d1_nan_output_num + ) begin + dp2reg_d1_nan_output_num_w = (dp2reg_d1_set) ? dp2reg_nan_output_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_input_num <= dp2reg_d1_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_input_num <= dp2reg_d1_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_output_num <= dp2reg_d1_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_PDP_reg diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v.vcp new file mode 100644 index 0000000..597e457 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v.vcp @@ -0,0 +1,1651 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_reg.v +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2pdp_req_pd //|< i + ,csb2pdp_req_pvld //|< i + ,dp2reg_d0_perf_write_stall //|< i + ,dp2reg_d1_perf_write_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_inf_input_num //|< i + ,dp2reg_nan_input_num //|< i + ,dp2reg_nan_output_num //|< i + ,csb2pdp_req_prdy //|> o + ,pdp2csb_resp_pd //|> o + ,pdp2csb_resp_valid //|> o + ,reg2dp_cube_in_channel //|> o + ,reg2dp_cube_in_height //|> o + ,reg2dp_cube_in_width //|> o + ,reg2dp_cube_out_channel //|> o + ,reg2dp_cube_out_height //|> o + ,reg2dp_cube_out_width //|> o + ,reg2dp_cya //|> o + ,reg2dp_dma_en //|> o + ,reg2dp_dst_base_addr_high //|> o + ,reg2dp_dst_base_addr_low //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_ram_type //|> o + ,reg2dp_dst_surface_stride //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_input_data //|> o + ,reg2dp_interrupt_ptr //|> o + ,reg2dp_kernel_height //|> o + ,reg2dp_kernel_stride_height //|> o + ,reg2dp_kernel_stride_width //|> o + ,reg2dp_kernel_width //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_op_en //|> o + ,reg2dp_pad_bottom //|> o + ,reg2dp_pad_left //|> o + ,reg2dp_pad_right //|> o + ,reg2dp_pad_top //|> o + ,reg2dp_pad_value_1x //|> o + ,reg2dp_pad_value_2x //|> o + ,reg2dp_pad_value_3x //|> o + ,reg2dp_pad_value_4x //|> o + ,reg2dp_pad_value_5x //|> o + ,reg2dp_pad_value_6x //|> o + ,reg2dp_pad_value_7x //|> o + ,reg2dp_partial_width_in_first //|> o + ,reg2dp_partial_width_in_last //|> o + ,reg2dp_partial_width_in_mid //|> o + ,reg2dp_partial_width_out_first //|> o + ,reg2dp_partial_width_out_last //|> o + ,reg2dp_partial_width_out_mid //|> o + ,reg2dp_pooling_method //|> o + ,reg2dp_recip_kernel_height //|> o + ,reg2dp_recip_kernel_width //|> o + ,reg2dp_split_num //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_surface_stride //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2pdp_req_pd; +input csb2pdp_req_pvld; +input [31:0] dp2reg_d0_perf_write_stall; +input [31:0] dp2reg_d1_perf_write_stall; +input dp2reg_done; +input [31:0] dp2reg_inf_input_num; +input [31:0] dp2reg_nan_input_num; +input [31:0] dp2reg_nan_output_num; +output csb2pdp_req_prdy; +output [33:0] pdp2csb_resp_pd; +output pdp2csb_resp_valid; +output [12:0] reg2dp_cube_in_channel; +output [12:0] reg2dp_cube_in_height; +output [12:0] reg2dp_cube_in_width; +output [12:0] reg2dp_cube_out_channel; +output [12:0] reg2dp_cube_out_height; +output [12:0] reg2dp_cube_out_width; +output [31:0] reg2dp_cya; +output reg2dp_dma_en; +output [31:0] reg2dp_dst_base_addr_high; +output [31:0] reg2dp_dst_base_addr_low; +output [31:0] reg2dp_dst_line_stride; +output reg2dp_dst_ram_type; +output [31:0] reg2dp_dst_surface_stride; +output reg2dp_flying_mode; +output [1:0] reg2dp_input_data; +output reg2dp_interrupt_ptr; +output [3:0] reg2dp_kernel_height; +output [3:0] reg2dp_kernel_stride_height; +output [3:0] reg2dp_kernel_stride_width; +output [3:0] reg2dp_kernel_width; +output reg2dp_nan_to_zero; +output reg2dp_op_en; +output [2:0] reg2dp_pad_bottom; +output [2:0] reg2dp_pad_left; +output [2:0] reg2dp_pad_right; +output [2:0] reg2dp_pad_top; +output [18:0] reg2dp_pad_value_1x; +output [18:0] reg2dp_pad_value_2x; +output [18:0] reg2dp_pad_value_3x; +output [18:0] reg2dp_pad_value_4x; +output [18:0] reg2dp_pad_value_5x; +output [18:0] reg2dp_pad_value_6x; +output [18:0] reg2dp_pad_value_7x; +output [9:0] reg2dp_partial_width_in_first; +output [9:0] reg2dp_partial_width_in_last; +output [9:0] reg2dp_partial_width_in_mid; +output [9:0] reg2dp_partial_width_out_first; +output [9:0] reg2dp_partial_width_out_last; +output [9:0] reg2dp_partial_width_out_mid; +output [1:0] reg2dp_pooling_method; +output [16:0] reg2dp_recip_kernel_height; +output [16:0] reg2dp_recip_kernel_width; +output [7:0] reg2dp_split_num; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output [31:0] reg2dp_src_surface_stride; +output [2:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [12:0] reg2dp_d0_cube_in_channel; +wire [12:0] reg2dp_d0_cube_in_height; +wire [12:0] reg2dp_d0_cube_in_width; +wire [12:0] reg2dp_d0_cube_out_channel; +wire [12:0] reg2dp_d0_cube_out_height; +wire [12:0] reg2dp_d0_cube_out_width; +wire [31:0] reg2dp_d0_cya; +wire reg2dp_d0_dma_en; +wire [31:0] reg2dp_d0_dst_base_addr_high; +wire [31:0] reg2dp_d0_dst_base_addr_low; +wire [31:0] reg2dp_d0_dst_line_stride; +wire reg2dp_d0_dst_ram_type; +wire [31:0] reg2dp_d0_dst_surface_stride; +wire reg2dp_d0_flying_mode; +wire [1:0] reg2dp_d0_input_data; +wire [3:0] reg2dp_d0_kernel_height; +wire [3:0] reg2dp_d0_kernel_stride_height; +wire [3:0] reg2dp_d0_kernel_stride_width; +wire [3:0] reg2dp_d0_kernel_width; +wire reg2dp_d0_nan_to_zero; +wire reg2dp_d0_op_en_trigger; +wire [2:0] reg2dp_d0_pad_bottom; +wire [2:0] reg2dp_d0_pad_left; +wire [2:0] reg2dp_d0_pad_right; +wire [2:0] reg2dp_d0_pad_top; +wire [18:0] reg2dp_d0_pad_value_1x; +wire [18:0] reg2dp_d0_pad_value_2x; +wire [18:0] reg2dp_d0_pad_value_3x; +wire [18:0] reg2dp_d0_pad_value_4x; +wire [18:0] reg2dp_d0_pad_value_5x; +wire [18:0] reg2dp_d0_pad_value_6x; +wire [18:0] reg2dp_d0_pad_value_7x; +wire [9:0] reg2dp_d0_partial_width_in_first; +wire [9:0] reg2dp_d0_partial_width_in_last; +wire [9:0] reg2dp_d0_partial_width_in_mid; +wire [9:0] reg2dp_d0_partial_width_out_first; +wire [9:0] reg2dp_d0_partial_width_out_last; +wire [9:0] reg2dp_d0_partial_width_out_mid; +wire [1:0] reg2dp_d0_pooling_method; +wire [16:0] reg2dp_d0_recip_kernel_height; +wire [16:0] reg2dp_d0_recip_kernel_width; +wire [7:0] reg2dp_d0_split_num; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d1_cube_in_channel; +wire [12:0] reg2dp_d1_cube_in_height; +wire [12:0] reg2dp_d1_cube_in_width; +wire [12:0] reg2dp_d1_cube_out_channel; +wire [12:0] reg2dp_d1_cube_out_height; +wire [12:0] reg2dp_d1_cube_out_width; +wire [31:0] reg2dp_d1_cya; +wire reg2dp_d1_dma_en; +wire [31:0] reg2dp_d1_dst_base_addr_high; +wire [31:0] reg2dp_d1_dst_base_addr_low; +wire [31:0] reg2dp_d1_dst_line_stride; +wire reg2dp_d1_dst_ram_type; +wire [31:0] reg2dp_d1_dst_surface_stride; +wire reg2dp_d1_flying_mode; +wire [1:0] reg2dp_d1_input_data; +wire [3:0] reg2dp_d1_kernel_height; +wire [3:0] reg2dp_d1_kernel_stride_height; +wire [3:0] reg2dp_d1_kernel_stride_width; +wire [3:0] reg2dp_d1_kernel_width; +wire reg2dp_d1_nan_to_zero; +wire reg2dp_d1_op_en_trigger; +wire [2:0] reg2dp_d1_pad_bottom; +wire [2:0] reg2dp_d1_pad_left; +wire [2:0] reg2dp_d1_pad_right; +wire [2:0] reg2dp_d1_pad_top; +wire [18:0] reg2dp_d1_pad_value_1x; +wire [18:0] reg2dp_d1_pad_value_2x; +wire [18:0] reg2dp_d1_pad_value_3x; +wire [18:0] reg2dp_d1_pad_value_4x; +wire [18:0] reg2dp_d1_pad_value_5x; +wire [18:0] reg2dp_d1_pad_value_6x; +wire [18:0] reg2dp_d1_pad_value_7x; +wire [9:0] reg2dp_d1_partial_width_in_first; +wire [9:0] reg2dp_d1_partial_width_in_last; +wire [9:0] reg2dp_d1_partial_width_in_mid; +wire [9:0] reg2dp_d1_partial_width_out_first; +wire [9:0] reg2dp_d1_partial_width_out_last; +wire [9:0] reg2dp_d1_partial_width_out_mid; +wire [1:0] reg2dp_d1_pooling_method; +wire [16:0] reg2dp_d1_recip_kernel_height; +wire [16:0] reg2dp_d1_recip_kernel_width; +wire [7:0] reg2dp_d1_split_num; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [2:0] slcg_op_en_d0; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_inf_input_num; +reg [31:0] dp2reg_d0_inf_input_num_w; +reg [31:0] dp2reg_d0_nan_input_num; +reg [31:0] dp2reg_d0_nan_input_num_w; +reg [31:0] dp2reg_d0_nan_output_num; +reg [31:0] dp2reg_d0_nan_output_num_w; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_inf_input_num; +reg [31:0] dp2reg_d1_inf_input_num_w; +reg [31:0] dp2reg_d1_nan_input_num; +reg [31:0] dp2reg_d1_nan_input_num_w; +reg [31:0] dp2reg_d1_nan_output_num; +reg [31:0] dp2reg_d1_nan_output_num_w; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [33:0] pdp2csb_resp_pd; +reg pdp2csb_resp_valid; +reg [12:0] reg2dp_cube_in_channel; +reg [12:0] reg2dp_cube_in_height; +reg [12:0] reg2dp_cube_in_width; +reg [12:0] reg2dp_cube_out_channel; +reg [12:0] reg2dp_cube_out_height; +reg [12:0] reg2dp_cube_out_width; +reg [31:0] reg2dp_cya; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_dma_en; +reg [31:0] reg2dp_dst_base_addr_high; +reg [31:0] reg2dp_dst_base_addr_low; +reg [31:0] reg2dp_dst_line_stride; +reg reg2dp_dst_ram_type; +reg [31:0] reg2dp_dst_surface_stride; +reg reg2dp_flying_mode; +reg [1:0] reg2dp_input_data; +reg [3:0] reg2dp_kernel_height; +reg [3:0] reg2dp_kernel_stride_height; +reg [3:0] reg2dp_kernel_stride_width; +reg [3:0] reg2dp_kernel_width; +reg reg2dp_nan_to_zero; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [2:0] reg2dp_pad_bottom; +reg [2:0] reg2dp_pad_left; +reg [2:0] reg2dp_pad_right; +reg [2:0] reg2dp_pad_top; +reg [18:0] reg2dp_pad_value_1x; +reg [18:0] reg2dp_pad_value_2x; +reg [18:0] reg2dp_pad_value_3x; +reg [18:0] reg2dp_pad_value_4x; +reg [18:0] reg2dp_pad_value_5x; +reg [18:0] reg2dp_pad_value_6x; +reg [18:0] reg2dp_pad_value_7x; +reg [9:0] reg2dp_partial_width_in_first; +reg [9:0] reg2dp_partial_width_in_last; +reg [9:0] reg2dp_partial_width_in_mid; +reg [9:0] reg2dp_partial_width_out_first; +reg [9:0] reg2dp_partial_width_out_last; +reg [9:0] reg2dp_partial_width_out_mid; +reg [1:0] reg2dp_pooling_method; +reg [16:0] reg2dp_recip_kernel_height; +reg [16:0] reg2dp_recip_kernel_width; +reg [7:0] reg2dp_split_num; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg [31:0] reg2dp_src_surface_stride; +reg [62:0] req_pd; +reg req_pvld; +reg [2:0] slcg_op_en_d1; +reg [2:0] slcg_op_en_d2; +reg [2:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_PDP_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_PDP_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d0_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d0_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d0_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d0_cube_in_width[12:0]) //|> w + ,.cube_out_channel (reg2dp_d0_cube_out_channel[12:0]) //|> w + ,.cube_out_height (reg2dp_d0_cube_out_height[12:0]) //|> w + ,.cube_out_width (reg2dp_d0_cube_out_width[12:0]) //|> w + ,.input_data (reg2dp_d0_input_data[1:0]) //|> w + ,.dst_base_addr_high (reg2dp_d0_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d0_dst_base_addr_low[31:0]) //|> w + ,.dst_line_stride (reg2dp_d0_dst_line_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d0_dst_ram_type) //|> w + ,.dst_surface_stride (reg2dp_d0_dst_surface_stride[31:0]) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.pooling_method (reg2dp_d0_pooling_method[1:0]) //|> w + ,.split_num (reg2dp_d0_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d0_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d0_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d0_partial_width_in_mid[9:0]) //|> w + ,.partial_width_out_first (reg2dp_d0_partial_width_out_first[9:0]) //|> w + ,.partial_width_out_last (reg2dp_d0_partial_width_out_last[9:0]) //|> w + ,.partial_width_out_mid (reg2dp_d0_partial_width_out_mid[9:0]) //|> w + ,.dma_en (reg2dp_d0_dma_en) //|> w + ,.kernel_height (reg2dp_d0_kernel_height[3:0]) //|> w + ,.kernel_stride_height (reg2dp_d0_kernel_stride_height[3:0]) //|> w + ,.kernel_stride_width (reg2dp_d0_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d0_kernel_width[3:0]) //|> w + ,.pad_bottom (reg2dp_d0_pad_bottom[2:0]) //|> w + ,.pad_left (reg2dp_d0_pad_left[2:0]) //|> w + ,.pad_right (reg2dp_d0_pad_right[2:0]) //|> w + ,.pad_top (reg2dp_d0_pad_top[2:0]) //|> w + ,.pad_value_1x (reg2dp_d0_pad_value_1x[18:0]) //|> w + ,.pad_value_2x (reg2dp_d0_pad_value_2x[18:0]) //|> w + ,.pad_value_3x (reg2dp_d0_pad_value_3x[18:0]) //|> w + ,.pad_value_4x (reg2dp_d0_pad_value_4x[18:0]) //|> w + ,.pad_value_5x (reg2dp_d0_pad_value_5x[18:0]) //|> w + ,.pad_value_6x (reg2dp_d0_pad_value_6x[18:0]) //|> w + ,.pad_value_7x (reg2dp_d0_pad_value_7x[18:0]) //|> w + ,.recip_kernel_height (reg2dp_d0_recip_kernel_height[16:0]) //|> w + ,.recip_kernel_width (reg2dp_d0_recip_kernel_width[16:0]) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.inf_input_num (dp2reg_d0_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d0_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d0_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d0_op_en) //|< r + ,.perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) //|< i + ); +NV_NVDLA_PDP_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cya (reg2dp_d1_cya[31:0]) //|> w + ,.cube_in_channel (reg2dp_d1_cube_in_channel[12:0]) //|> w + ,.cube_in_height (reg2dp_d1_cube_in_height[12:0]) //|> w + ,.cube_in_width (reg2dp_d1_cube_in_width[12:0]) //|> w + ,.cube_out_channel (reg2dp_d1_cube_out_channel[12:0]) //|> w + ,.cube_out_height (reg2dp_d1_cube_out_height[12:0]) //|> w + ,.cube_out_width (reg2dp_d1_cube_out_width[12:0]) //|> w + ,.input_data (reg2dp_d1_input_data[1:0]) //|> w + ,.dst_base_addr_high (reg2dp_d1_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d1_dst_base_addr_low[31:0]) //|> w + ,.dst_line_stride (reg2dp_d1_dst_line_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d1_dst_ram_type) //|> w + ,.dst_surface_stride (reg2dp_d1_dst_surface_stride[31:0]) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.pooling_method (reg2dp_d1_pooling_method[1:0]) //|> w + ,.split_num (reg2dp_d1_split_num[7:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.partial_width_in_first (reg2dp_d1_partial_width_in_first[9:0]) //|> w + ,.partial_width_in_last (reg2dp_d1_partial_width_in_last[9:0]) //|> w + ,.partial_width_in_mid (reg2dp_d1_partial_width_in_mid[9:0]) //|> w + ,.partial_width_out_first (reg2dp_d1_partial_width_out_first[9:0]) //|> w + ,.partial_width_out_last (reg2dp_d1_partial_width_out_last[9:0]) //|> w + ,.partial_width_out_mid (reg2dp_d1_partial_width_out_mid[9:0]) //|> w + ,.dma_en (reg2dp_d1_dma_en) //|> w + ,.kernel_height (reg2dp_d1_kernel_height[3:0]) //|> w + ,.kernel_stride_height (reg2dp_d1_kernel_stride_height[3:0]) //|> w + ,.kernel_stride_width (reg2dp_d1_kernel_stride_width[3:0]) //|> w + ,.kernel_width (reg2dp_d1_kernel_width[3:0]) //|> w + ,.pad_bottom (reg2dp_d1_pad_bottom[2:0]) //|> w + ,.pad_left (reg2dp_d1_pad_left[2:0]) //|> w + ,.pad_right (reg2dp_d1_pad_right[2:0]) //|> w + ,.pad_top (reg2dp_d1_pad_top[2:0]) //|> w + ,.pad_value_1x (reg2dp_d1_pad_value_1x[18:0]) //|> w + ,.pad_value_2x (reg2dp_d1_pad_value_2x[18:0]) //|> w + ,.pad_value_3x (reg2dp_d1_pad_value_3x[18:0]) //|> w + ,.pad_value_4x (reg2dp_d1_pad_value_4x[18:0]) //|> w + ,.pad_value_5x (reg2dp_d1_pad_value_5x[18:0]) //|> w + ,.pad_value_6x (reg2dp_d1_pad_value_6x[18:0]) //|> w + ,.pad_value_7x (reg2dp_d1_pad_value_7x[18:0]) //|> w + ,.recip_kernel_height (reg2dp_d1_recip_kernel_height[16:0]) //|> w + ,.recip_kernel_width (reg2dp_d1_recip_kernel_width[16:0]) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.inf_input_num (dp2reg_d1_inf_input_num[31:0]) //|< r + ,.nan_input_num (dp2reg_d1_nan_input_num[31:0]) //|< r + ,.nan_output_num (dp2reg_d1_nan_output_num[31:0]) //|< r + ,.op_en (reg2dp_d1_op_en) //|< r + ,.perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {3{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {3{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {3{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {3{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hd008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hd008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hd008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2pdp_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2pdp_req_pvld) == 1'b1) begin + req_pd <= csb2pdp_req_pd; +// VCS coverage off + end else if ((csb2pdp_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2pdp_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2pdp_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + pdp2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + pdp2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2csb_resp_valid <= 1'b0; + end else begin + pdp2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cya + or reg2dp_d0_cya + ) begin + reg2dp_cya = dp2reg_consumer ? reg2dp_d1_cya : reg2dp_d0_cya; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_channel + or reg2dp_d0_cube_in_channel + ) begin + reg2dp_cube_in_channel = dp2reg_consumer ? reg2dp_d1_cube_in_channel : reg2dp_d0_cube_in_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_height + or reg2dp_d0_cube_in_height + ) begin + reg2dp_cube_in_height = dp2reg_consumer ? reg2dp_d1_cube_in_height : reg2dp_d0_cube_in_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_in_width + or reg2dp_d0_cube_in_width + ) begin + reg2dp_cube_in_width = dp2reg_consumer ? reg2dp_d1_cube_in_width : reg2dp_d0_cube_in_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_out_channel + or reg2dp_d0_cube_out_channel + ) begin + reg2dp_cube_out_channel = dp2reg_consumer ? reg2dp_d1_cube_out_channel : reg2dp_d0_cube_out_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_out_height + or reg2dp_d0_cube_out_height + ) begin + reg2dp_cube_out_height = dp2reg_consumer ? reg2dp_d1_cube_out_height : reg2dp_d0_cube_out_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_cube_out_width + or reg2dp_d0_cube_out_width + ) begin + reg2dp_cube_out_width = dp2reg_consumer ? reg2dp_d1_cube_out_width : reg2dp_d0_cube_out_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_input_data + or reg2dp_d0_input_data + ) begin + reg2dp_input_data = dp2reg_consumer ? reg2dp_d1_input_data : reg2dp_d0_input_data; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_high + or reg2dp_d0_dst_base_addr_high + ) begin + reg2dp_dst_base_addr_high = dp2reg_consumer ? reg2dp_d1_dst_base_addr_high : reg2dp_d0_dst_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_low + or reg2dp_d0_dst_base_addr_low + ) begin + reg2dp_dst_base_addr_low = dp2reg_consumer ? reg2dp_d1_dst_base_addr_low : reg2dp_d0_dst_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_line_stride + or reg2dp_d0_dst_line_stride + ) begin + reg2dp_dst_line_stride = dp2reg_consumer ? reg2dp_d1_dst_line_stride : reg2dp_d0_dst_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_ram_type + or reg2dp_d0_dst_ram_type + ) begin + reg2dp_dst_ram_type = dp2reg_consumer ? reg2dp_d1_dst_ram_type : reg2dp_d0_dst_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_surface_stride + or reg2dp_d0_dst_surface_stride + ) begin + reg2dp_dst_surface_stride = dp2reg_consumer ? reg2dp_d1_dst_surface_stride : reg2dp_d0_dst_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_pooling_method + or reg2dp_d0_pooling_method + ) begin + reg2dp_pooling_method = dp2reg_consumer ? reg2dp_d1_pooling_method : reg2dp_d0_pooling_method; +end +always @( + dp2reg_consumer + or reg2dp_d1_split_num + or reg2dp_d0_split_num + ) begin + reg2dp_split_num = dp2reg_consumer ? reg2dp_d1_split_num : reg2dp_d0_split_num; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_first + or reg2dp_d0_partial_width_in_first + ) begin + reg2dp_partial_width_in_first = dp2reg_consumer ? reg2dp_d1_partial_width_in_first : reg2dp_d0_partial_width_in_first; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_last + or reg2dp_d0_partial_width_in_last + ) begin + reg2dp_partial_width_in_last = dp2reg_consumer ? reg2dp_d1_partial_width_in_last : reg2dp_d0_partial_width_in_last; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_in_mid + or reg2dp_d0_partial_width_in_mid + ) begin + reg2dp_partial_width_in_mid = dp2reg_consumer ? reg2dp_d1_partial_width_in_mid : reg2dp_d0_partial_width_in_mid; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_out_first + or reg2dp_d0_partial_width_out_first + ) begin + reg2dp_partial_width_out_first = dp2reg_consumer ? reg2dp_d1_partial_width_out_first : reg2dp_d0_partial_width_out_first; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_out_last + or reg2dp_d0_partial_width_out_last + ) begin + reg2dp_partial_width_out_last = dp2reg_consumer ? reg2dp_d1_partial_width_out_last : reg2dp_d0_partial_width_out_last; +end +always @( + dp2reg_consumer + or reg2dp_d1_partial_width_out_mid + or reg2dp_d0_partial_width_out_mid + ) begin + reg2dp_partial_width_out_mid = dp2reg_consumer ? reg2dp_d1_partial_width_out_mid : reg2dp_d0_partial_width_out_mid; +end +always @( + dp2reg_consumer + or reg2dp_d1_dma_en + or reg2dp_d0_dma_en + ) begin + reg2dp_dma_en = dp2reg_consumer ? reg2dp_d1_dma_en : reg2dp_d0_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_height + or reg2dp_d0_kernel_height + ) begin + reg2dp_kernel_height = dp2reg_consumer ? reg2dp_d1_kernel_height : reg2dp_d0_kernel_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_stride_height + or reg2dp_d0_kernel_stride_height + ) begin + reg2dp_kernel_stride_height = dp2reg_consumer ? reg2dp_d1_kernel_stride_height : reg2dp_d0_kernel_stride_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_stride_width + or reg2dp_d0_kernel_stride_width + ) begin + reg2dp_kernel_stride_width = dp2reg_consumer ? reg2dp_d1_kernel_stride_width : reg2dp_d0_kernel_stride_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_kernel_width + or reg2dp_d0_kernel_width + ) begin + reg2dp_kernel_width = dp2reg_consumer ? reg2dp_d1_kernel_width : reg2dp_d0_kernel_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_bottom + or reg2dp_d0_pad_bottom + ) begin + reg2dp_pad_bottom = dp2reg_consumer ? reg2dp_d1_pad_bottom : reg2dp_d0_pad_bottom; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_left + or reg2dp_d0_pad_left + ) begin + reg2dp_pad_left = dp2reg_consumer ? reg2dp_d1_pad_left : reg2dp_d0_pad_left; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_right + or reg2dp_d0_pad_right + ) begin + reg2dp_pad_right = dp2reg_consumer ? reg2dp_d1_pad_right : reg2dp_d0_pad_right; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_top + or reg2dp_d0_pad_top + ) begin + reg2dp_pad_top = dp2reg_consumer ? reg2dp_d1_pad_top : reg2dp_d0_pad_top; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_1x + or reg2dp_d0_pad_value_1x + ) begin + reg2dp_pad_value_1x = dp2reg_consumer ? reg2dp_d1_pad_value_1x : reg2dp_d0_pad_value_1x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_2x + or reg2dp_d0_pad_value_2x + ) begin + reg2dp_pad_value_2x = dp2reg_consumer ? reg2dp_d1_pad_value_2x : reg2dp_d0_pad_value_2x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_3x + or reg2dp_d0_pad_value_3x + ) begin + reg2dp_pad_value_3x = dp2reg_consumer ? reg2dp_d1_pad_value_3x : reg2dp_d0_pad_value_3x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_4x + or reg2dp_d0_pad_value_4x + ) begin + reg2dp_pad_value_4x = dp2reg_consumer ? reg2dp_d1_pad_value_4x : reg2dp_d0_pad_value_4x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_5x + or reg2dp_d0_pad_value_5x + ) begin + reg2dp_pad_value_5x = dp2reg_consumer ? reg2dp_d1_pad_value_5x : reg2dp_d0_pad_value_5x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_6x + or reg2dp_d0_pad_value_6x + ) begin + reg2dp_pad_value_6x = dp2reg_consumer ? reg2dp_d1_pad_value_6x : reg2dp_d0_pad_value_6x; +end +always @( + dp2reg_consumer + or reg2dp_d1_pad_value_7x + or reg2dp_d0_pad_value_7x + ) begin + reg2dp_pad_value_7x = dp2reg_consumer ? reg2dp_d1_pad_value_7x : reg2dp_d0_pad_value_7x; +end +always @( + dp2reg_consumer + or reg2dp_d1_recip_kernel_height + or reg2dp_d0_recip_kernel_height + ) begin + reg2dp_recip_kernel_height = dp2reg_consumer ? reg2dp_d1_recip_kernel_height : reg2dp_d0_recip_kernel_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_recip_kernel_width + or reg2dp_d0_recip_kernel_width + ) begin + reg2dp_recip_kernel_width = dp2reg_consumer ? reg2dp_d1_recip_kernel_width : reg2dp_d0_recip_kernel_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//assign reg2dp_lut_data = reg_wr_data[::range(15)]; +assign reg2dp_interrupt_ptr = dp2reg_consumer; +//////// for general counting register //////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for NaN and infinity counting registers //////// +//////// group 0 //////// +always @( + dp2reg_d0_set + or dp2reg_nan_input_num + or dp2reg_d0_clr + or dp2reg_d0_nan_input_num + ) begin + dp2reg_d0_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_nan_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_inf_input_num + or dp2reg_d0_clr + or dp2reg_d0_inf_input_num + ) begin + dp2reg_d0_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_inf_input_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_inf_input_num; +end +always @( + dp2reg_d0_set + or dp2reg_nan_output_num + or dp2reg_d0_clr + or dp2reg_d0_nan_output_num + ) begin + dp2reg_d0_nan_output_num_w = (dp2reg_d0_set) ? dp2reg_nan_output_num : + (dp2reg_d0_clr) ? 32'b0 : + dp2reg_d0_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_input_num <= dp2reg_d0_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_inf_input_num <= dp2reg_d0_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nan_output_num <= dp2reg_d0_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////// group 1 //////// +always @( + dp2reg_d1_set + or dp2reg_nan_input_num + or dp2reg_d1_clr + or dp2reg_d1_nan_input_num + ) begin + dp2reg_d1_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_nan_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_inf_input_num + or dp2reg_d1_clr + or dp2reg_d1_inf_input_num + ) begin + dp2reg_d1_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_inf_input_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_inf_input_num; +end +always @( + dp2reg_d1_set + or dp2reg_nan_output_num + or dp2reg_d1_clr + or dp2reg_d1_nan_output_num + ) begin + dp2reg_d1_nan_output_num_w = (dp2reg_d1_set) ? dp2reg_nan_output_num : + (dp2reg_d1_clr) ? 32'b0 : + dp2reg_d1_nan_output_num; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_input_num <= dp2reg_d1_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_inf_input_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_inf_input_num <= dp2reg_d1_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nan_output_num <= {32{1'b0}}; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nan_output_num <= dp2reg_d1_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_PDP_reg diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v new file mode 100644 index 0000000..0308eae --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v @@ -0,0 +1,389 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_slcg.v +module NV_NVDLA_PDP_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input [0:0] slcg_en_src; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src[0]; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_PDP_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v.vcp new file mode 100644 index 0000000..0308eae --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v.vcp @@ -0,0 +1,389 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_slcg.v +module NV_NVDLA_PDP_slcg ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,slcg_en_src + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input [0:0] slcg_en_src; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +wire enable; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign enable = slcg_en_src[0]; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_PDP_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_PDP_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v new file mode 100644 index 0000000..abc64a9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v @@ -0,0 +1,1579 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_wdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_wdma ( + nvdla_core_clk //|< i + ,nvdla_core_clk_orig //|< i + ,nvdla_core_rstn //|< i + ,mcif2pdp_wr_rsp_complete //|< i + ,pdp2mcif_wr_req_ready //|< i + ,pdp_dp2wdma_pd //|< i + ,pdp_dp2wdma_valid //|< i + ,pwrbus_ram_pd //|< i + ,rdma2wdma_done //|< i + ,reg2dp_cube_out_channel //|< i + ,reg2dp_cube_out_height //|< i + ,reg2dp_cube_out_width //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_ram_type //|< i + ,reg2dp_dst_surface_stride //|< i + ,reg2dp_flying_mode //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_interrupt_ptr //|< i + ,reg2dp_op_en //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_split_num //|< i + ,dp2reg_d0_perf_write_stall //|> o + ,dp2reg_d1_perf_write_stall //|> o + ,dp2reg_done //|> o +// ,dp2reg_nan_output_num //|> o + ,pdp2glb_done_intr_pd //|> o + ,pdp2mcif_wr_req_pd //|> o + ,pdp2mcif_wr_req_valid //|> o + ,pdp_dp2wdma_ready //|> o + ); +/////////////////////////////////////////////////////////////////////////////////////// +// +// NV_NVDLA_PDP_wdma_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output pdp2mcif_wr_req_valid; /* data valid */ +input pdp2mcif_wr_req_ready; /* data return handshake */ +output [( 64 + (64/8/8) + 1 )-1:0] pdp2mcif_wr_req_pd; +input mcif2pdp_wr_rsp_complete; +input pdp_dp2wdma_valid; +output pdp_dp2wdma_ready; +input [8*1 -1:0] pdp_dp2wdma_pd; +input [31:0] pwrbus_ram_pd; +output [1:0] pdp2glb_done_intr_pd; +input rdma2wdma_done; +input [12:0] reg2dp_cube_out_channel; +input [12:0] reg2dp_cube_out_height; +input [12:0] reg2dp_cube_out_width; +input reg2dp_dma_en; +input [31:0] reg2dp_dst_base_addr_high; +input [31:0] reg2dp_dst_base_addr_low; +input [31:0] reg2dp_dst_line_stride; +input reg2dp_dst_ram_type; +input [31:0] reg2dp_dst_surface_stride; +input reg2dp_flying_mode; +//input [1:0] reg2dp_input_data; +input reg2dp_interrupt_ptr; +input reg2dp_op_en; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [7:0] reg2dp_split_num; +output [31:0] dp2reg_d0_perf_write_stall; +output [31:0] dp2reg_d1_perf_write_stall; +output dp2reg_done; +//output [31:0] dp2reg_nan_output_num; +input nvdla_core_clk_orig; +/////////////////////////////////////////////////////////////////////////////////////// +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg cmd_en; +reg [12:0] cmd_fifo_rd_size_use; +reg [12:0] count_w; +reg cv_dma_wr_rsp_complete; +reg cv_pending; +reg dat0_fifo_rd_pvld; +reg dat1_fifo_rd_pvld; +reg dat_en; +reg [( 64 + (64/8/8) + 1 )-1:0] dma_wr_req_pd; +wire dma_wr_rsp_complete; +reg [31:0] dp2reg_d0_perf_write_stall; +reg [31:0] dp2reg_d1_perf_write_stall; +//reg [31:0] dp2reg_nan_output_num; +//reg [63:0] dp2wdma_pd; +//reg dp2wdma_vld; +//reg fp16_en; +reg intp_waiting_rdma; +reg layer_flag; +reg mc_dma_wr_rsp_complete; +reg mc_pending; +reg mcif2pdp_wr_rsp_complete_d1; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +reg op_prcess; +reg [1:0] pdp2glb_done_intr_pd; +wire pdp_dp2wdma_ready; +reg [31:0] pdp_wr_stall_count; +reg reading_done_flag; +reg reg_cube_last; +reg [4:0] reg_lenb; +reg [12:0] reg_size; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg waiting_rdma; +reg wdma_done; +reg wdma_done_d1; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire [63:0] cmd_fifo_rd_addr; +wire cmd_fifo_rd_cube_end; +//wire [4:0] cmd_fifo_rd_lenb; +wire [79:0] cmd_fifo_rd_pd; //bw ? +wire cmd_fifo_rd_prdy; +wire cmd_fifo_rd_pvld; +wire [12:0] cmd_fifo_rd_size; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: print "wire [${pdpbw}*${Bnum}-1:0] dat${posw}_data; \n"; +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: wire [${pdpbw}-1:0]dat${posw}_fifo${posb}_rd_pd; +//: wire dat${posw}_fifo${posb}_rd_prdy; +//: wire dat${posw}_fifo${posb}_rd_pvld; +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [8*8-1:0] dat0_data; + +wire [8-1:0]dat0_fifo0_rd_pd; +wire dat0_fifo0_rd_prdy; +wire dat0_fifo0_rd_pvld; + +wire [8-1:0]dat0_fifo1_rd_pd; +wire dat0_fifo1_rd_prdy; +wire dat0_fifo1_rd_pvld; + +wire [8-1:0]dat0_fifo2_rd_pd; +wire dat0_fifo2_rd_prdy; +wire dat0_fifo2_rd_pvld; + +wire [8-1:0]dat0_fifo3_rd_pd; +wire dat0_fifo3_rd_prdy; +wire dat0_fifo3_rd_pvld; + +wire [8-1:0]dat0_fifo4_rd_pd; +wire dat0_fifo4_rd_prdy; +wire dat0_fifo4_rd_pvld; + +wire [8-1:0]dat0_fifo5_rd_pd; +wire dat0_fifo5_rd_prdy; +wire dat0_fifo5_rd_pvld; + +wire [8-1:0]dat0_fifo6_rd_pd; +wire dat0_fifo6_rd_prdy; +wire dat0_fifo6_rd_pvld; + +wire [8-1:0]dat0_fifo7_rd_pd; +wire dat0_fifo7_rd_prdy; +wire dat0_fifo7_rd_pvld; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire dat_accept; +wire [64 -1:0] dat_data; +reg dat_fifo_rd_last_pvld; +wire dat_rdy; +wire dma_wr_cmd_accept; +wire [63:0] dma_wr_cmd_addr; +wire [32 +13:0] dma_wr_cmd_pd; +wire dma_wr_cmd_require_ack; +wire [22:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [64 -1:0] dma_wr_dat_data; +wire [1:0] dma_wr_dat_mask; +wire [64 + (64/8/8)-1:0] dma_wr_dat_pd; +wire dma_wr_dat_vld; +wire dma_wr_req_rdy; +wire dma_wr_req_type; +wire dma_wr_req_vld; +wire dp2wdma_rdy; +wire intr_fifo_rd_pd; +wire intr_fifo_rd_prdy; +wire intr_fifo_rd_pvld; +wire intr_fifo_wr_pd; +wire intr_fifo_wr_pvld; +wire is_last_beat; +wire is_size_odd; +wire off_fly_en; +wire on_fly_en; +wire op_done; +wire op_load; +wire pdp_wr_stall_count_dec; +wire releasing; +wire require_ack; +wire wr_req_rdyi; +/////////////////////////////////////////////////////////////////////////////////////// +//============== +// tracing rdma reading done to aviod layer switched but RDMA still reading the last layer +//============== +assign on_fly_en = reg2dp_flying_mode == 1'h0 ; +assign off_fly_en = reg2dp_flying_mode == 1'h1 ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reading_done_flag <= 1'b0; + end else begin + if(op_done) + reading_done_flag <= 1'b0; + else if(rdma2wdma_done & off_fly_en) + reading_done_flag <= 1'b1; + else if(op_load & on_fly_en) + reading_done_flag <= 1'b1; + else if(op_load & off_fly_en) + reading_done_flag <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_rdma <= 1'b0; + end else begin + if(op_done & (~reading_done_flag))// + waiting_rdma <= 1'b1; + else if(reading_done_flag) + waiting_rdma <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wdma_done <= 1'b0; + end else begin + if(op_done & reading_done_flag)//normal case + wdma_done <= 1'b1; + else if(waiting_rdma & reading_done_flag)//waiting RDMA case + wdma_done <= 1'b1; + else + wdma_done <= 1'b0; + end +end +//============== +// Work Processing +//============== +assign op_load = reg2dp_op_en & !op_prcess; +assign op_done = reg_cube_last & is_last_beat & dat_accept; +assign dp2reg_done = wdma_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_prcess <= 1'b0; + end else begin + if (op_load) begin + op_prcess <= 1'b1; + end else if (wdma_done) begin + op_prcess <= 1'b0; + end + end +end +//============== +// Data INPUT pipe and Unpack +//============== +//: my $k = 1*8; +//: &eperl::pipe("-wid $k -is -do dp2wdma_pd -vo dp2wdma_vld -ri dp2wdma_rdy -di pdp_dp2wdma_pd -vi pdp_dp2wdma_valid -ro pdp_dp2wdma_ready_ff "); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg pdp_dp2wdma_ready_ff; +reg skid_flop_pdp_dp2wdma_ready_ff; +reg skid_flop_pdp_dp2wdma_valid; +reg [8-1:0] skid_flop_pdp_dp2wdma_pd; +reg pipe_skid_pdp_dp2wdma_valid; +reg [8-1:0] pipe_skid_pdp_dp2wdma_pd; +// Wire +wire skid_pdp_dp2wdma_valid; +wire [8-1:0] skid_pdp_dp2wdma_pd; +wire skid_pdp_dp2wdma_ready_ff; +wire pipe_skid_pdp_dp2wdma_ready_ff; +wire dp2wdma_vld; +wire [8-1:0] dp2wdma_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp_dp2wdma_ready_ff <= 1'b1; + skid_flop_pdp_dp2wdma_ready_ff <= 1'b1; + end else begin + pdp_dp2wdma_ready_ff <= skid_pdp_dp2wdma_ready_ff; + skid_flop_pdp_dp2wdma_ready_ff <= skid_pdp_dp2wdma_ready_ff; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_pdp_dp2wdma_valid <= 1'b0; + end else begin + if (skid_flop_pdp_dp2wdma_ready_ff) begin + skid_flop_pdp_dp2wdma_valid <= pdp_dp2wdma_valid; + end + end +end +assign skid_pdp_dp2wdma_valid = (skid_flop_pdp_dp2wdma_ready_ff) ? pdp_dp2wdma_valid : skid_flop_pdp_dp2wdma_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_pdp_dp2wdma_ready_ff & pdp_dp2wdma_valid) begin + skid_flop_pdp_dp2wdma_pd[8-1:0] <= pdp_dp2wdma_pd[8-1:0]; + end +end +assign skid_pdp_dp2wdma_pd[8-1:0] = (skid_flop_pdp_dp2wdma_ready_ff) ? pdp_dp2wdma_pd[8-1:0] : skid_flop_pdp_dp2wdma_pd[8-1:0]; + + +// PIPE READY +assign skid_pdp_dp2wdma_ready_ff = pipe_skid_pdp_dp2wdma_ready_ff || !pipe_skid_pdp_dp2wdma_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_pdp_dp2wdma_valid <= 1'b0; + end else begin + if (skid_pdp_dp2wdma_ready_ff) begin + pipe_skid_pdp_dp2wdma_valid <= skid_pdp_dp2wdma_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_pdp_dp2wdma_ready_ff && skid_pdp_dp2wdma_valid) begin + pipe_skid_pdp_dp2wdma_pd[8-1:0] <= skid_pdp_dp2wdma_pd[8-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_pdp_dp2wdma_ready_ff = dp2wdma_rdy; +assign dp2wdma_vld = pipe_skid_pdp_dp2wdma_valid; +assign dp2wdma_pd = pipe_skid_pdp_dp2wdma_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign pdp_dp2wdma_ready = pdp_dp2wdma_ready_ff; +//============== +// Instance CMD +//============== +NV_NVDLA_PDP_WDMA_dat u_dat ( + .reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) +// ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.dp2wdma_pd (dp2wdma_pd) + ,.dp2wdma_vld (dp2wdma_vld) + ,.dp2wdma_rdy (dp2wdma_rdy) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: ,.dat${posw}_fifo${posb}_rd_pd (dat${posw}_fifo${posb}_rd_pd ) +//: ,.dat${posw}_fifo${posb}_rd_prdy (dat${posw}_fifo${posb}_rd_prdy ) +//: ,.dat${posw}_fifo${posb}_rd_pvld (dat${posw}_fifo${posb}_rd_pvld ) +//: ); +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.dat0_fifo0_rd_pd (dat0_fifo0_rd_pd ) +,.dat0_fifo0_rd_prdy (dat0_fifo0_rd_prdy ) +,.dat0_fifo0_rd_pvld (dat0_fifo0_rd_pvld ) + +,.dat0_fifo1_rd_pd (dat0_fifo1_rd_pd ) +,.dat0_fifo1_rd_prdy (dat0_fifo1_rd_prdy ) +,.dat0_fifo1_rd_pvld (dat0_fifo1_rd_pvld ) + +,.dat0_fifo2_rd_pd (dat0_fifo2_rd_pd ) +,.dat0_fifo2_rd_prdy (dat0_fifo2_rd_prdy ) +,.dat0_fifo2_rd_pvld (dat0_fifo2_rd_pvld ) + +,.dat0_fifo3_rd_pd (dat0_fifo3_rd_pd ) +,.dat0_fifo3_rd_prdy (dat0_fifo3_rd_prdy ) +,.dat0_fifo3_rd_pvld (dat0_fifo3_rd_pvld ) + +,.dat0_fifo4_rd_pd (dat0_fifo4_rd_pd ) +,.dat0_fifo4_rd_prdy (dat0_fifo4_rd_prdy ) +,.dat0_fifo4_rd_pvld (dat0_fifo4_rd_pvld ) + +,.dat0_fifo5_rd_pd (dat0_fifo5_rd_pd ) +,.dat0_fifo5_rd_prdy (dat0_fifo5_rd_prdy ) +,.dat0_fifo5_rd_pvld (dat0_fifo5_rd_pvld ) + +,.dat0_fifo6_rd_pd (dat0_fifo6_rd_pd ) +,.dat0_fifo6_rd_prdy (dat0_fifo6_rd_prdy ) +,.dat0_fifo6_rd_pvld (dat0_fifo6_rd_pvld ) + +,.dat0_fifo7_rd_pd (dat0_fifo7_rd_pd ) +,.dat0_fifo7_rd_prdy (dat0_fifo7_rd_prdy ) +,.dat0_fifo7_rd_pvld (dat0_fifo7_rd_pvld ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.wdma_done (wdma_done) + ,.op_load (op_load) + ); +///////////////////////////////////////// +// DATA FIFO: READ SIDE +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: ##my $p = int( log(${Wnum}) / log(2) ); +//: print "reg [${Wnum}-1:0] atomm_invld; \n"; +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: print qq( +//: always @(*) begin +//: case (reg_lenb) +//: ); +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: 5'd${posb}: dat${posw}_fifo_rd_pvld = dat${posw}_fifo${posb}_rd_pvld; +//: ); +//: } +//: print qq( +//: //VCS coverage off +//: default : begin +//: dat${posw}_fifo_rd_pvld = {1{`x_or_0}}; +//: end +//: //VCS coverage on +//: endcase +//: end +//: ); +//: +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: assign dat${posw}_fifo${posb}_rd_prdy = (atomm_invld[$posw] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); +//: ); +//: } +//: } +//: +//: print qq( +//: always @(*) begin +//: ); +//: if($Wnum == 1) { +//: print qq( +//: atomm_invld[0] = 1'b0; +//: dat_fifo_rd_last_pvld = dat0_fifo_rd_pvld; +//: ); +//: } elsif($Wnum == 2) { +//: print qq( +//: atomm_invld[0] = 1'b0; +//: atomm_invld[1] = (reg_size[0]==0); +//: dat_fifo_rd_last_pvld = ((reg_size[0]==0) & is_last_beat) ? dat0_fifo_rd_pvld : dat1_fifo_rd_pvld; +//: ); +//: } elsif($Wnum == 4) { +//: print qq( +//: atomm_invld[0] = 1'b0; +//: atomm_invld[1] = (reg_size[1:0]<2'd1); +//: atomm_invld[2] = (reg_size[1:0]<2'd2); +//: atomm_invld[3] = (reg_size[1:0]<2'd3); +//: dat_fifo_rd_last_pvld = ((reg_size[1:0]==0) & is_last_beat) ? dat0_fifo_rd_pvld : +//: ((reg_size[1:0]==1) & is_last_beat) ? dat1_fifo_rd_pvld : +//: ((reg_size[1:0]==2) & is_last_beat) ? dat2_fifo_rd_pvld : +//: ((reg_size[1:0]==3) & is_last_beat) ? dat3_fifo_rd_pvld : 0; +//: ); +//: } else { ## illegal case, atomic_m num within one dmaif tx should be one of 1/2/4 +//: } +//: print qq( +//: end +//: ); +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [1-1:0] atomm_invld; + +always @(*) begin +case (reg_lenb) + +5'd0: dat0_fifo_rd_pvld = dat0_fifo0_rd_pvld; + +5'd1: dat0_fifo_rd_pvld = dat0_fifo1_rd_pvld; + +5'd2: dat0_fifo_rd_pvld = dat0_fifo2_rd_pvld; + +5'd3: dat0_fifo_rd_pvld = dat0_fifo3_rd_pvld; + +5'd4: dat0_fifo_rd_pvld = dat0_fifo4_rd_pvld; + +5'd5: dat0_fifo_rd_pvld = dat0_fifo5_rd_pvld; + +5'd6: dat0_fifo_rd_pvld = dat0_fifo6_rd_pvld; + +5'd7: dat0_fifo_rd_pvld = dat0_fifo7_rd_pvld; + +//VCS coverage off +default : begin +dat0_fifo_rd_pvld = {1{`x_or_0}}; +end +//VCS coverage on +endcase +end + +assign dat0_fifo0_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo1_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo2_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo3_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo4_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo5_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo6_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +assign dat0_fifo7_rd_prdy = (atomm_invld[0] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); + +always @(*) begin + +atomm_invld[0] = 1'b0; +dat_fifo_rd_last_pvld = dat0_fifo_rd_pvld; + +end + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// assign is_size_odd = (reg_size[0]==0); +// assign dat0_fifo0_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat0_fifo1_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat0_fifo2_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat0_fifo3_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo0_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo1_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo2_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo3_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat_fifo_rd_last_pvld = (is_size_odd & is_last_beat) ? dat0_fifo_rd_pvld : dat1_fifo_rd_pvld; +// assign dat0_data= {dat0_fifo3_rd_pd, dat0_fifo2_rd_pd, dat0_fifo1_rd_pd, dat0_fifo0_rd_pd}; +// assign dat1_data= {dat1_fifo3_rd_pd, dat1_fifo2_rd_pd, dat1_fifo1_rd_pd, dat1_fifo0_rd_pd}; +// assign dat_data = {dat1_data,dat0_data}; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { +//: print "assign dat${posw}_data = { "; +//: if($Bnum > 1) { +//: foreach my $posb (0..$Bnum-2) { ##throughput in each atomic_m +//: my $invb = $Bnum -$posb -1; +//: print "dat${posw}_fifo${invb}_rd_pd, "; +//: } +//: } +//: print "dat${posw}_fifo0_rd_pd}; \n"; +//: } +//: +//: print "assign dat_data = { "; +//: if($Wnum > 1) { +//: foreach my $posw (0..$Wnum-2) { +//: my $invw = $Wnum - $posw -1; +//: print "dat${invw}_data, "; +//: } +//: } +//: print "dat0_data}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign dat0_data = { dat0_fifo7_rd_pd, dat0_fifo6_rd_pd, dat0_fifo5_rd_pd, dat0_fifo4_rd_pd, dat0_fifo3_rd_pd, dat0_fifo2_rd_pd, dat0_fifo1_rd_pd, dat0_fifo0_rd_pd}; +assign dat_data = { dat0_data}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//============== +// output NaN counter +//============== +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// fp16_en <= 1'b0; +// end else begin +// fp16_en <= reg2dp_input_data== 2'h2; +// end +//end +//assign dat0_is_nan_0[0] = fp16_en & (&dat0_fifo0_rd_pd[14:10]) & (|dat0_fifo0_rd_pd[9:0]); +//assign dat0_is_nan_0[1] = fp16_en & (&dat0_fifo0_rd_pd[30:26]) & (|dat0_fifo0_rd_pd[25:16]); +//assign dat0_is_nan_0[2] = fp16_en & (&dat0_fifo0_rd_pd[46:42]) & (|dat0_fifo0_rd_pd[41:32]); +//assign dat0_is_nan_0[3] = fp16_en & (&dat0_fifo0_rd_pd[62:58]) & (|dat0_fifo0_rd_pd[57:48]); +//assign dat1_is_nan_0[0] = fp16_en & (&dat1_fifo0_rd_pd[14:10]) & (|dat1_fifo0_rd_pd[9:0]); +//assign dat1_is_nan_0[1] = fp16_en & (&dat1_fifo0_rd_pd[30:26]) & (|dat1_fifo0_rd_pd[25:16]); +//assign dat1_is_nan_0[2] = fp16_en & (&dat1_fifo0_rd_pd[46:42]) & (|dat1_fifo0_rd_pd[41:32]); +//assign dat1_is_nan_0[3] = fp16_en & (&dat1_fifo0_rd_pd[62:58]) & (|dat1_fifo0_rd_pd[57:48]); +//assign dat0_is_nan_1[0] = fp16_en & (&dat0_fifo1_rd_pd[14:10]) & (|dat0_fifo1_rd_pd[9:0]); +//assign dat0_is_nan_1[1] = fp16_en & (&dat0_fifo1_rd_pd[30:26]) & (|dat0_fifo1_rd_pd[25:16]); +//assign dat0_is_nan_1[2] = fp16_en & (&dat0_fifo1_rd_pd[46:42]) & (|dat0_fifo1_rd_pd[41:32]); +//assign dat0_is_nan_1[3] = fp16_en & (&dat0_fifo1_rd_pd[62:58]) & (|dat0_fifo1_rd_pd[57:48]); +//assign dat1_is_nan_1[0] = fp16_en & (&dat1_fifo1_rd_pd[14:10]) & (|dat1_fifo1_rd_pd[9:0]); +//assign dat1_is_nan_1[1] = fp16_en & (&dat1_fifo1_rd_pd[30:26]) & (|dat1_fifo1_rd_pd[25:16]); +//assign dat1_is_nan_1[2] = fp16_en & (&dat1_fifo1_rd_pd[46:42]) & (|dat1_fifo1_rd_pd[41:32]); +//assign dat1_is_nan_1[3] = fp16_en & (&dat1_fifo1_rd_pd[62:58]) & (|dat1_fifo1_rd_pd[57:48]); +//assign dat0_is_nan_2[0] = fp16_en & (&dat0_fifo2_rd_pd[14:10]) & (|dat0_fifo2_rd_pd[9:0]); +//assign dat0_is_nan_2[1] = fp16_en & (&dat0_fifo2_rd_pd[30:26]) & (|dat0_fifo2_rd_pd[25:16]); +//assign dat0_is_nan_2[2] = fp16_en & (&dat0_fifo2_rd_pd[46:42]) & (|dat0_fifo2_rd_pd[41:32]); +//assign dat0_is_nan_2[3] = fp16_en & (&dat0_fifo2_rd_pd[62:58]) & (|dat0_fifo2_rd_pd[57:48]); +//assign dat1_is_nan_2[0] = fp16_en & (&dat1_fifo2_rd_pd[14:10]) & (|dat1_fifo2_rd_pd[9:0]); +//assign dat1_is_nan_2[1] = fp16_en & (&dat1_fifo2_rd_pd[30:26]) & (|dat1_fifo2_rd_pd[25:16]); +//assign dat1_is_nan_2[2] = fp16_en & (&dat1_fifo2_rd_pd[46:42]) & (|dat1_fifo2_rd_pd[41:32]); +//assign dat1_is_nan_2[3] = fp16_en & (&dat1_fifo2_rd_pd[62:58]) & (|dat1_fifo2_rd_pd[57:48]); +//assign dat0_is_nan_3[0] = fp16_en & (&dat0_fifo3_rd_pd[14:10]) & (|dat0_fifo3_rd_pd[9:0]); +//assign dat0_is_nan_3[1] = fp16_en & (&dat0_fifo3_rd_pd[30:26]) & (|dat0_fifo3_rd_pd[25:16]); +//assign dat0_is_nan_3[2] = fp16_en & (&dat0_fifo3_rd_pd[46:42]) & (|dat0_fifo3_rd_pd[41:32]); +//assign dat0_is_nan_3[3] = fp16_en & (&dat0_fifo3_rd_pd[62:58]) & (|dat0_fifo3_rd_pd[57:48]); +//assign dat1_is_nan_3[0] = fp16_en & (&dat1_fifo3_rd_pd[14:10]) & (|dat1_fifo3_rd_pd[9:0]); +//assign dat1_is_nan_3[1] = fp16_en & (&dat1_fifo3_rd_pd[30:26]) & (|dat1_fifo3_rd_pd[25:16]); +//assign dat1_is_nan_3[2] = fp16_en & (&dat1_fifo3_rd_pd[46:42]) & (|dat1_fifo3_rd_pd[41:32]); +//assign dat1_is_nan_3[3] = fp16_en & (&dat1_fifo3_rd_pd[62:58]) & (|dat1_fifo3_rd_pd[57:48]); +// +//assign nan_num_in_x[31:0] = {dat1_is_nan_3,dat1_is_nan_2,dat1_is_nan_1,dat1_is_nan_0,dat0_is_nan_3,dat0_is_nan_2,dat0_is_nan_1,dat0_is_nan_0}; +//assign nan_num_in_dat0_0[2:0] = (dat0_is_nan_0[0] + dat0_is_nan_0[1]) + (dat0_is_nan_0[2] + dat0_is_nan_0[3]); +//assign nan_num_in_dat0_1[2:0] = (dat0_is_nan_1[0] + dat0_is_nan_1[1]) + (dat0_is_nan_1[2] + dat0_is_nan_1[3]); +//assign nan_num_in_dat0_2[2:0] = (dat0_is_nan_2[0] + dat0_is_nan_2[1]) + (dat0_is_nan_2[2] + dat0_is_nan_2[3]); +//assign nan_num_in_dat0_3[2:0] = (dat0_is_nan_3[0] + dat0_is_nan_3[1]) + (dat0_is_nan_3[2] + dat0_is_nan_3[3]); +//assign nan_num_in_dat1_0[2:0] = (dat1_is_nan_0[0] + dat1_is_nan_0[1]) + (dat1_is_nan_0[2] + dat1_is_nan_0[3]); +//assign nan_num_in_dat1_1[2:0] = (dat1_is_nan_1[0] + dat1_is_nan_1[1]) + (dat1_is_nan_1[2] + dat1_is_nan_1[3]); +//assign nan_num_in_dat1_2[2:0] = (dat1_is_nan_2[0] + dat1_is_nan_2[1]) + (dat1_is_nan_2[2] + dat1_is_nan_2[3]); +//assign nan_num_in_dat1_3[2:0] = (dat1_is_nan_3[0] + dat1_is_nan_3[1]) + (dat1_is_nan_3[2] + dat1_is_nan_3[3]); +// +//function [5:0] fun_bit_sum_32; +// input [31:0] idata; +// reg [5:0] ocnt; +// begin +// ocnt = +// (((( idata[0] +// + idata[1] +// + idata[2] ) +// + ( idata[3] +// + idata[4] +// + idata[5] )) +// + (( idata[6] +// + idata[7] +// + idata[8] ) +// + ( idata[9] +// + idata[10] +// + idata[11] ))) +// + ((( idata[12] +// + idata[13] +// + idata[14] ) +// + ( idata[15] +// + idata[16] +// + idata[17] )) +// + (( idata[18] +// + idata[19] +// + idata[20] ) +// + ( idata[21] +// + idata[22] +// + idata[23] )))) +// + (( idata[24] +// + idata[25] +// + idata[26] ) +// + ( idata[27] +// + idata[28] +// + idata[29] )) +// + ( idata[30] +// + idata[31] ) ; +// fun_bit_sum_32 = ocnt; +// end +//endfunction +// +//assign nan_num_in_64B = fun_bit_sum_32(nan_num_in_x); +// +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(dat_accept) begin +// if(op_done) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_64B; +// end +// end +//end +//`ifdef SPYGLASS_ASSERT_ON +//`else +//// spyglass disable_block NoWidthInBasedNum-ML +//// spyglass disable_block STARC-2.10.3.2a +//// spyglass disable_block STARC05-2.1.3.1 +//// spyglass disable_block STARC-2.1.4.6 +//// spyglass disable_block W116 +//// spyglass disable_block W154 +//// spyglass disable_block W239 +//// spyglass disable_block W362 +//// spyglass disable_block WRN_58 +//// spyglass disable_block WRN_61 +//`endif // SPYGLASS_ASSERT_ON +//`ifdef ASSERT_ON +//`ifdef FV_ASSERT_ON +//`define ASSERT_RESET nvdla_core_rstn +//`else +//`ifdef SYNTHESIS +//`define ASSERT_RESET nvdla_core_rstn +//`else +//`ifdef ASSERT_OFF_RESET_IS_X +//`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +//`else +//`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +//`endif // ASSERT_OFF_RESET_IS_X +//`endif // SYNTHESIS +//`endif // FV_ASSERT_ON +// // VCS coverage off +// nv_assert_never #(0,0,"PDP WDMA: nan counter no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_nan_in_count); // spyglass disable W504 SelfDeterminedExpr-ML +// // VCS coverage on +//`undef ASSERT_RESET +//`endif // ASSERT_ON +//`ifdef SPYGLASS_ASSERT_ON +//`else +//// spyglass enable_block NoWidthInBasedNum-ML +//// spyglass enable_block STARC-2.10.3.2a +//// spyglass enable_block STARC05-2.1.3.1 +//// spyglass enable_block STARC-2.1.4.6 +//// spyglass enable_block W116 +//// spyglass enable_block W154 +//// spyglass enable_block W239 +//// spyglass enable_block W362 +//// spyglass enable_block WRN_58 +//// spyglass enable_block WRN_61 +//`endif // SPYGLASS_ASSERT_ON +// +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// dp2reg_nan_output_num <= {32{1'b0}}; +// end else begin +// if(op_done) +// dp2reg_nan_output_num <= nan_in_count; +// end +//end +//============== +// Instance CMD +//============== +NV_NVDLA_PDP_WDMA_cmd u_cmd ( + .reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) +// ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[79:0]) + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.op_load (op_load) + ); +// CMD FIFO: Read side +assign cmd_fifo_rd_prdy = cmd_en & dma_wr_req_rdy; +// Unpack cmd & data together +// PKT_UNPACK_WIRE( pdp_wdma_cmd , cmd_fifo_rd_ , cmd_fifo_rd_pd ) +assign cmd_fifo_rd_addr[63:0] = cmd_fifo_rd_pd[63:0]; +assign cmd_fifo_rd_size[12:0] = cmd_fifo_rd_pd[76:64]; +//assign cmd_fifo_rd_lenb[4:0] = cmd_fifo_rd_pd[78:77]; +assign cmd_fifo_rd_cube_end = cmd_fifo_rd_pd[79]; +// addr/size/lenb/end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_lenb <= 0; + end else begin + if ((dma_wr_cmd_accept) == 1'b1) begin +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Bnum = int($atomicm/$pdpbw); +//: print "reg_lenb <= ${Bnum} - 1;"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg_lenb <= 8 - 1; +//| eperl: generated_end (DO NOT EDIT ABOVE) +//reg_lenb <= cmd_fifo_rd_lenb; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_size <= {13{1'b0}}; + end else begin + if ((dma_wr_cmd_accept) == 1'b1) begin + reg_size <= cmd_fifo_rd_size; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_cube_last <= 1'b0; + end else begin + if ((dma_wr_cmd_accept) == 1'b1) begin + reg_cube_last <= cmd_fifo_rd_cube_end; + end + end +end +//============== +// BLOCK Operation +//============== +assign dma_wr_cmd_vld = cmd_en & cmd_fifo_rd_pvld; +assign dma_wr_cmd_accept = dma_wr_cmd_vld & dma_wr_req_rdy; +assign dma_wr_dat_vld = dat_en & dat_fifo_rd_last_pvld; +assign dat_rdy = dat_en & dma_wr_req_rdy; +assign dat_accept = dma_wr_dat_vld & dma_wr_req_rdy; +// count_w and tran_cnt is used to index 8B in each 8(B)x8(w)x4(c) block, (w may be < 8 if is_first_w or is_last_w) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {13{1'b0}}; + end else begin + if (dma_wr_cmd_accept) begin + count_w <= 0; + end else if (dat_accept) begin +//: my $Wnum= 64/8/8; +//: print " count_w <= count_w + ${Wnum}; \n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + count_w <= count_w + 1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) + end + end +end +//: my $Wnum= 64/8/8; +//: if($Wnum == 1) { +//: print qq( +//: assign is_last_beat = (count_w==reg_size); +//: ); +//: } elsif($Wnum == 2) { +//: print qq( +//: assign is_last_beat = (count_w==reg_size || count_w==reg_size-1); +//: ); +//: } elsif($Wnum == 4) { +//: print qq( +//: assign is_last_beat = (count_w==reg_size || count_w==reg_size-1 || count_w==reg_size-2 || count_w==reg_size-3); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign is_last_beat = (count_w==reg_size); + +//| eperl: generated_end (DO NOT EDIT ABOVE) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (is_last_beat & dat_accept) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else if (dma_wr_cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end + end +end +//============== +// DMA REQ: Size +//============== +// packet: cmd +//assign dma_wr_cmd_vld = cmd_vld; +assign dma_wr_cmd_addr = cmd_fifo_rd_addr; +assign dma_wr_cmd_size = {10'b0, cmd_fifo_rd_size}; +assign dma_wr_cmd_require_ack = cmd_fifo_rd_cube_end; +// PKT_PACK_WIRE( dma_write_cmd , dma_wr_cmd_ , dma_wr_cmd_pd ) +assign dma_wr_cmd_pd[32 -1:0] = dma_wr_cmd_addr[32 -1:0]; +assign dma_wr_cmd_pd[32 +12:32] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[32 +13] = dma_wr_cmd_require_ack ; +// packet: data +assign dma_wr_dat_data = dat_data; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_fifo_rd_size_use <= {13{1'b0}}; + end else begin + if ((cmd_fifo_rd_pvld & cmd_fifo_rd_prdy) == 1'b1) begin + cmd_fifo_rd_size_use <= cmd_fifo_rd_size[12:0]; +// VCS coverage off + end else if ((cmd_fifo_rd_pvld & cmd_fifo_rd_prdy) == 1'b0) begin + end else begin + cmd_fifo_rd_size_use <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd_fifo_rd_pvld & cmd_fifo_rd_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//: my $msk = (64/8/8); +//: if($msk == 1) { +//: print " assign dma_wr_dat_mask = 2'b1; \n"; +//: } elsif($msk == 2) { +//: print " assign dma_wr_dat_mask = (cmd_fifo_rd_size_use[0]==0 && is_last_beat) ? 2'b01 : 2'b11; \n"; +//: } elsif($msk == 4) { +//: print " assign dma_wr_dat_mask = ((cmd_fifo_rd_size_use[1:0]==2'b00) && is_last_beat) ? 4'b0001 : \n"; +//: print " ((cmd_fifo_rd_size_use[1:0]==2'b01) && is_last_beat) ? 4'b0011 : \n"; +//: print " ((cmd_fifo_rd_size_use[1:0]==2'b10) && is_last_beat) ? 4'b0111 : 4'b1111; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + assign dma_wr_dat_mask = 2'b1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// PKT_PACK_WIRE( dma_write_data , dma_wr_dat_ , dma_wr_dat_pd ) +assign dma_wr_dat_pd[64 -1:0] = dma_wr_dat_data[64 -1:0]; +assign dma_wr_dat_pd[64 +(64/8/8)-1:64] = dma_wr_dat_mask[(64/8/8)-1:0]; +// pack cmd & dat +assign dma_wr_req_vld = dma_wr_cmd_vld | dma_wr_dat_vld; +always @(*) begin +// init to 0 + dma_wr_req_pd[64 + (64/8/8)-1:0] = 0; +// cmd or dat + if (cmd_en) begin + dma_wr_req_pd[32 +13:0] = dma_wr_cmd_pd; + end else begin + dma_wr_req_pd[64 + (64/8/8)-1:0] = dma_wr_dat_pd; + end +// pkt id + dma_wr_req_pd[( 64 + (64/8/8) + 1 )-1] = cmd_en ? 1'd0 /* PKT_nvdla_dma_wr_req_dma_write_cmd_ID */ : 1'd1 /* PKT_nvdla_dma_wr_req_dma_write_data_ID */ ; +end +//============== +// reading stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = op_done; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_wr_req_vld & (~dma_wr_req_rdy)); + assign pdp_wr_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or pdp_wr_stall_count_dec + ) begin + stl_adv = cnt_inc ^ pdp_wr_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or pdp_wr_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !pdp_wr_stall_count_dec)? stl_cnt_inc : (!cnt_inc && pdp_wr_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + pdp_wr_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; +// VCS coverage off + end else if ((cnt_clr) == 1'b0) begin + end else begin + layer_flag <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_write_stall <= pdp_wr_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & (~layer_flag)) == 1'b0) begin + end else begin + dp2reg_d0_perf_write_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & (~layer_flag)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_write_stall <= pdp_wr_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & layer_flag ) == 1'b0) begin + end else begin + dp2reg_d1_perf_write_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & layer_flag ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +NV_NVDLA_DMAIF_wr NV_NVDLA_PDP_WDMA_wr( + .nvdla_core_clk (nvdla_core_clk_orig ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type ) + ,.mcif_wr_req_pd (pdp2mcif_wr_req_pd ) + ,.mcif_wr_req_valid (pdp2mcif_wr_req_valid ) + ,.mcif_wr_req_ready (pdp2mcif_wr_req_ready ) + ,.mcif_wr_rsp_complete (mcif2pdp_wr_rsp_complete) + ,.dmaif_wr_req_pd (dma_wr_req_pd ) + ,.dmaif_wr_req_pvld (dma_wr_req_vld ) + ,.dmaif_wr_req_prdy (dma_wr_req_rdy ) + ,.dmaif_wr_rsp_complete (dma_wr_rsp_complete ) +); +//logic for wdma writing done, and has accepted dma_wr_rsp_complete, but RDMA still not reading done +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wdma_done_d1 <= 1'b0; + end else begin + wdma_done_d1 <= wdma_done; + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intp_waiting_rdma <= 1'b0; + end else begin + if(dma_wr_rsp_complete & waiting_rdma) + intp_waiting_rdma <= 1'b1; + else if(wdma_done_d1) + intp_waiting_rdma <= 1'b0; + end +end +// +NV_NVDLA_PDP_WDMA_intr_fifo u_intr_fifo ( + .nvdla_core_clk (nvdla_core_clk_orig) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intr_fifo_wr_pvld (intr_fifo_wr_pvld) //|< w + ,.intr_fifo_wr_pd (intr_fifo_wr_pd) //|< w + ,.intr_fifo_rd_prdy (intr_fifo_rd_prdy) //|< w + ,.intr_fifo_rd_pvld (intr_fifo_rd_pvld) //|> w + ,.intr_fifo_rd_pd (intr_fifo_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign intr_fifo_wr_pd = reg2dp_interrupt_ptr; +assign intr_fifo_wr_pvld = wdma_done; +assign intr_fifo_rd_prdy = dma_wr_rsp_complete & (~waiting_rdma) || (intp_waiting_rdma & wdma_done_d1); +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2glb_done_intr_pd[0] <= 1'b0; + end else begin + pdp2glb_done_intr_pd[0] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==0); + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2glb_done_intr_pd[1] <= 1'b0; + end else begin + pdp2glb_done_intr_pd[1] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==1); + end +end +////============== +////OBS signals +////============== +//assign obs_bus_pdp_core_proc_en = op_prcess; +//============== +//function polint +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_WDMA__dma_writing_stall__7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_req_vld & (~dma_wr_req_rdy); + endproperty +// Cover 7 : "dma_wr_req_vld & (~dma_wr_req_rdy)" + FUNCPOINT_PDP_WDMA__dma_writing_stall__7_COV : cover property (PDP_WDMA__dma_writing_stall__7_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_WDMA__dp2wdma_stall__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_dp2wdma_valid & (~pdp_dp2wdma_ready); + endproperty +// Cover 8 : "pdp_dp2wdma_valid & (~pdp_dp2wdma_ready)" + FUNCPOINT_PDP_WDMA__dp2wdma_stall__8_COV : cover property (PDP_WDMA__dp2wdma_stall__8_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_PDP_wdma +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_WDMA_intr_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus intr_fifo_wr -rd_pipebus intr_fifo_rd -ram_bypass -d 0 -rd_reg -rd_busy_reg -no_wr_busy -w 1 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_intr_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intr_fifo_wr_pvld + , intr_fifo_wr_pd + , intr_fifo_rd_prdy + , intr_fifo_rd_pvld + , intr_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +input intr_fifo_wr_pvld; +input intr_fifo_wr_pd; +input intr_fifo_rd_prdy; +output intr_fifo_rd_pvld; +output intr_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] intr_fifo_rd_pd_p = intr_fifo_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg intr_fifo_rd_prdy_d; // intr_fifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_prdy_d <= 1'b1; + end else begin + intr_fifo_rd_prdy_d <= intr_fifo_rd_prdy; + end +end +wire intr_fifo_rd_prdy_d_o; // combinatorial rd_busy +reg intr_fifo_rd_pvld_int; // internal copy of intr_fifo_rd_pvld +assign intr_fifo_rd_pvld = intr_fifo_rd_pvld_int; +wire intr_fifo_rd_pvld_p = intr_fifo_wr_pvld ; // no real fifo, take from write-side input +reg intr_fifo_rd_pvld_int_o; // internal copy of intr_fifo_rd_pvld_o +wire intr_fifo_rd_pvld_o = intr_fifo_rd_pvld_int_o; +wire rd_popping = intr_fifo_rd_pvld_p && !(intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg intr_fifo_rd_pd_o; // output data register +wire rd_req_next_o = (intr_fifo_rd_pvld_p || (intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int_o <= 1'b0; + end else begin + intr_fifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + intr_fifo_rd_pd_o <= intr_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + intr_fifo_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg intr_fifo_rd_pd; // output data register +reg intr_fifo_rd_pvld_int_d; // so we can bubble-collapse intr_fifo_rd_prdy_d +assign intr_fifo_rd_prdy_d_o = !((intr_fifo_rd_pvld_o && intr_fifo_rd_pvld_int_d && !intr_fifo_rd_prdy_d ) ); +wire rd_req_next = (!intr_fifo_rd_prdy_d_o ? intr_fifo_rd_pvld_o : intr_fifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int <= 1'b0; + intr_fifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) begin + intr_fifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy) ) begin + end else begin + intr_fifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + intr_fifo_rd_pvld_int_d <= intr_fifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) ) begin + case (!intr_fifo_rd_prdy_d_o) + 1'b0: intr_fifo_rd_pd <= intr_fifo_rd_pd_p; + 1'b1: intr_fifo_rd_pd <= intr_fifo_rd_pd_o; +//VCS coverage off + default: intr_fifo_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy)) ) begin + end else begin + intr_fifo_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (intr_fifo_wr_pvld || (intr_fifo_rd_pvld_int && intr_fifo_rd_prdy_d) || (intr_fifo_rd_pvld_int_o && intr_fifo_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_WDMA_intr_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_WDMA_intr_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v.vcp new file mode 100644 index 0000000..2120c8f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v.vcp @@ -0,0 +1,1357 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_wdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_wdma ( + nvdla_core_clk //|< i + ,nvdla_core_clk_orig //|< i + ,nvdla_core_rstn //|< i + ,mcif2pdp_wr_rsp_complete //|< i + ,pdp2mcif_wr_req_ready //|< i + ,pdp_dp2wdma_pd //|< i + ,pdp_dp2wdma_valid //|< i + ,pwrbus_ram_pd //|< i + ,rdma2wdma_done //|< i + ,reg2dp_cube_out_channel //|< i + ,reg2dp_cube_out_height //|< i + ,reg2dp_cube_out_width //|< i + ,reg2dp_dma_en //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_ram_type //|< i + ,reg2dp_dst_surface_stride //|< i + ,reg2dp_flying_mode //|< i +// ,reg2dp_input_data //|< i + ,reg2dp_interrupt_ptr //|< i + ,reg2dp_op_en //|< i + ,reg2dp_partial_width_out_first //|< i + ,reg2dp_partial_width_out_last //|< i + ,reg2dp_partial_width_out_mid //|< i + ,reg2dp_split_num //|< i + ,dp2reg_d0_perf_write_stall //|> o + ,dp2reg_d1_perf_write_stall //|> o + ,dp2reg_done //|> o +// ,dp2reg_nan_output_num //|> o + ,pdp2glb_done_intr_pd //|> o + ,pdp2mcif_wr_req_pd //|> o + ,pdp2mcif_wr_req_valid //|> o + ,pdp_dp2wdma_ready //|> o + ); +/////////////////////////////////////////////////////////////////////////////////////// +// +// NV_NVDLA_PDP_wdma_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output pdp2mcif_wr_req_valid; /* data valid */ +input pdp2mcif_wr_req_ready; /* data return handshake */ +output [( 64 + (64/8/8) + 1 )-1:0] pdp2mcif_wr_req_pd; +input mcif2pdp_wr_rsp_complete; +input pdp_dp2wdma_valid; +output pdp_dp2wdma_ready; +input [8*1 -1:0] pdp_dp2wdma_pd; +input [31:0] pwrbus_ram_pd; +output [1:0] pdp2glb_done_intr_pd; +input rdma2wdma_done; +input [12:0] reg2dp_cube_out_channel; +input [12:0] reg2dp_cube_out_height; +input [12:0] reg2dp_cube_out_width; +input reg2dp_dma_en; +input [31:0] reg2dp_dst_base_addr_high; +input [31:0] reg2dp_dst_base_addr_low; +input [31:0] reg2dp_dst_line_stride; +input reg2dp_dst_ram_type; +input [31:0] reg2dp_dst_surface_stride; +input reg2dp_flying_mode; +//input [1:0] reg2dp_input_data; +input reg2dp_interrupt_ptr; +input reg2dp_op_en; +input [9:0] reg2dp_partial_width_out_first; +input [9:0] reg2dp_partial_width_out_last; +input [9:0] reg2dp_partial_width_out_mid; +input [7:0] reg2dp_split_num; +output [31:0] dp2reg_d0_perf_write_stall; +output [31:0] dp2reg_d1_perf_write_stall; +output dp2reg_done; +//output [31:0] dp2reg_nan_output_num; +input nvdla_core_clk_orig; +/////////////////////////////////////////////////////////////////////////////////////// +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg cmd_en; +reg [12:0] cmd_fifo_rd_size_use; +reg [12:0] count_w; +reg cv_dma_wr_rsp_complete; +reg cv_pending; +reg dat0_fifo_rd_pvld; +reg dat1_fifo_rd_pvld; +reg dat_en; +reg [( 64 + (64/8/8) + 1 )-1:0] dma_wr_req_pd; +wire dma_wr_rsp_complete; +reg [31:0] dp2reg_d0_perf_write_stall; +reg [31:0] dp2reg_d1_perf_write_stall; +//reg [31:0] dp2reg_nan_output_num; +//reg [63:0] dp2wdma_pd; +//reg dp2wdma_vld; +//reg fp16_en; +reg intp_waiting_rdma; +reg layer_flag; +reg mc_dma_wr_rsp_complete; +reg mc_pending; +reg mcif2pdp_wr_rsp_complete_d1; +//reg mon_nan_in_count; +//reg [31:0] nan_in_count; +reg op_prcess; +reg [1:0] pdp2glb_done_intr_pd; +wire pdp_dp2wdma_ready; +reg [31:0] pdp_wr_stall_count; +reg reading_done_flag; +reg reg_cube_last; +reg [4:0] reg_lenb; +reg [12:0] reg_size; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg waiting_rdma; +reg wdma_done; +reg wdma_done_d1; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire [63:0] cmd_fifo_rd_addr; +wire cmd_fifo_rd_cube_end; +//wire [4:0] cmd_fifo_rd_lenb; +wire [79:0] cmd_fifo_rd_pd; //bw ? +wire cmd_fifo_rd_prdy; +wire cmd_fifo_rd_pvld; +wire [12:0] cmd_fifo_rd_size; +wire cnt_cen; +wire cnt_clr; +wire cnt_inc; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: print "wire [${pdpbw}*${Bnum}-1:0] dat${posw}_data; \n"; +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: wire [${pdpbw}-1:0]dat${posw}_fifo${posb}_rd_pd; +//: wire dat${posw}_fifo${posb}_rd_prdy; +//: wire dat${posw}_fifo${posb}_rd_pvld; +//: ); +//: } +//: } +wire dat_accept; +wire [64 -1:0] dat_data; +reg dat_fifo_rd_last_pvld; +wire dat_rdy; +wire dma_wr_cmd_accept; +wire [63:0] dma_wr_cmd_addr; +wire [32 +13:0] dma_wr_cmd_pd; +wire dma_wr_cmd_require_ack; +wire [22:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [64 -1:0] dma_wr_dat_data; +wire [1:0] dma_wr_dat_mask; +wire [64 + (64/8/8)-1:0] dma_wr_dat_pd; +wire dma_wr_dat_vld; +wire dma_wr_req_rdy; +wire dma_wr_req_type; +wire dma_wr_req_vld; +wire dp2wdma_rdy; +wire intr_fifo_rd_pd; +wire intr_fifo_rd_prdy; +wire intr_fifo_rd_pvld; +wire intr_fifo_wr_pd; +wire intr_fifo_wr_pvld; +wire is_last_beat; +wire is_size_odd; +wire off_fly_en; +wire on_fly_en; +wire op_done; +wire op_load; +wire pdp_wr_stall_count_dec; +wire releasing; +wire require_ack; +wire wr_req_rdyi; +/////////////////////////////////////////////////////////////////////////////////////// +//============== +// tracing rdma reading done to aviod layer switched but RDMA still reading the last layer +//============== +assign on_fly_en = reg2dp_flying_mode == 1'h0 ; +assign off_fly_en = reg2dp_flying_mode == 1'h1 ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reading_done_flag <= 1'b0; + end else begin + if(op_done) + reading_done_flag <= 1'b0; + else if(rdma2wdma_done & off_fly_en) + reading_done_flag <= 1'b1; + else if(op_load & on_fly_en) + reading_done_flag <= 1'b1; + else if(op_load & off_fly_en) + reading_done_flag <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + waiting_rdma <= 1'b0; + end else begin + if(op_done & (~reading_done_flag))// + waiting_rdma <= 1'b1; + else if(reading_done_flag) + waiting_rdma <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wdma_done <= 1'b0; + end else begin + if(op_done & reading_done_flag)//normal case + wdma_done <= 1'b1; + else if(waiting_rdma & reading_done_flag)//waiting RDMA case + wdma_done <= 1'b1; + else + wdma_done <= 1'b0; + end +end +//============== +// Work Processing +//============== +assign op_load = reg2dp_op_en & !op_prcess; +assign op_done = reg_cube_last & is_last_beat & dat_accept; +assign dp2reg_done = wdma_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + op_prcess <= 1'b0; + end else begin + if (op_load) begin + op_prcess <= 1'b1; + end else if (wdma_done) begin + op_prcess <= 1'b0; + end + end +end +//============== +// Data INPUT pipe and Unpack +//============== +//: my $k = 1*8; +//: &eperl::pipe("-wid $k -is -do dp2wdma_pd -vo dp2wdma_vld -ri dp2wdma_rdy -di pdp_dp2wdma_pd -vi pdp_dp2wdma_valid -ro pdp_dp2wdma_ready_ff "); +assign pdp_dp2wdma_ready = pdp_dp2wdma_ready_ff; +//============== +// Instance CMD +//============== +NV_NVDLA_PDP_WDMA_dat u_dat ( + .reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) +// ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.dp2wdma_pd (dp2wdma_pd) + ,.dp2wdma_vld (dp2wdma_vld) + ,.dp2wdma_rdy (dp2wdma_rdy) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: ,.dat${posw}_fifo${posb}_rd_pd (dat${posw}_fifo${posb}_rd_pd ) +//: ,.dat${posw}_fifo${posb}_rd_prdy (dat${posw}_fifo${posb}_rd_prdy ) +//: ,.dat${posw}_fifo${posb}_rd_pvld (dat${posw}_fifo${posb}_rd_pvld ) +//: ); +//: } +//: } + ,.wdma_done (wdma_done) + ,.op_load (op_load) + ); +///////////////////////////////////////// +// DATA FIFO: READ SIDE +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: ##my $p = int( log(${Wnum}) / log(2) ); +//: print "reg [${Wnum}-1:0] atomm_invld; \n"; +//: foreach my $posw (0..$Wnum-1) { ##High...low atomic_m +//: print qq( +//: always @(*) begin +//: case (reg_lenb) +//: ); +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: 5'd${posb}: dat${posw}_fifo_rd_pvld = dat${posw}_fifo${posb}_rd_pvld; +//: ); +//: } +//: print qq( +//: //VCS coverage off +//: default : begin +//: dat${posw}_fifo_rd_pvld = {1{`x_or_0}}; +//: end +//: //VCS coverage on +//: endcase +//: end +//: ); +//: +//: foreach my $posb (0..$Bnum-1) { ##throughput in each atomic_m +//: print qq( +//: assign dat${posw}_fifo${posb}_rd_prdy = (atomm_invld[$posw] & is_last_beat)? 1'b0 : (dat_rdy & dat_fifo_rd_last_pvld); +//: ); +//: } +//: } +//: +//: print qq( +//: always @(*) begin +//: ); +//: if($Wnum == 1) { +//: print qq( +//: atomm_invld[0] = 1'b0; +//: dat_fifo_rd_last_pvld = dat0_fifo_rd_pvld; +//: ); +//: } elsif($Wnum == 2) { +//: print qq( +//: atomm_invld[0] = 1'b0; +//: atomm_invld[1] = (reg_size[0]==0); +//: dat_fifo_rd_last_pvld = ((reg_size[0]==0) & is_last_beat) ? dat0_fifo_rd_pvld : dat1_fifo_rd_pvld; +//: ); +//: } elsif($Wnum == 4) { +//: print qq( +//: atomm_invld[0] = 1'b0; +//: atomm_invld[1] = (reg_size[1:0]<2'd1); +//: atomm_invld[2] = (reg_size[1:0]<2'd2); +//: atomm_invld[3] = (reg_size[1:0]<2'd3); +//: dat_fifo_rd_last_pvld = ((reg_size[1:0]==0) & is_last_beat) ? dat0_fifo_rd_pvld : +//: ((reg_size[1:0]==1) & is_last_beat) ? dat1_fifo_rd_pvld : +//: ((reg_size[1:0]==2) & is_last_beat) ? dat2_fifo_rd_pvld : +//: ((reg_size[1:0]==3) & is_last_beat) ? dat3_fifo_rd_pvld : 0; +//: ); +//: } else { ## illegal case, atomic_m num within one dmaif tx should be one of 1/2/4 +//: } +//: print qq( +//: end +//: ); +// assign is_size_odd = (reg_size[0]==0); +// assign dat0_fifo0_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat0_fifo1_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat0_fifo2_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat0_fifo3_rd_prdy = dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo0_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo1_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo2_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat1_fifo3_rd_prdy = (is_size_odd & is_last_beat)? 1'b0 : dat_rdy & dat_fifo_rd_last_pvld; +// assign dat_fifo_rd_last_pvld = (is_size_odd & is_last_beat) ? dat0_fifo_rd_pvld : dat1_fifo_rd_pvld; +// assign dat0_data= {dat0_fifo3_rd_pd, dat0_fifo2_rd_pd, dat0_fifo1_rd_pd, dat0_fifo0_rd_pd}; +// assign dat1_data= {dat1_fifo3_rd_pd, dat1_fifo2_rd_pd, dat1_fifo1_rd_pd, dat1_fifo0_rd_pd}; +// assign dat_data = {dat1_data,dat0_data}; +//: my $dmaifBW = 64; +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Wnum = int( $dmaifBW/$atomicm ); +//: my $Bnum = int($atomicm/$pdpbw); +//: foreach my $posw (0..$Wnum-1) { +//: print "assign dat${posw}_data = { "; +//: if($Bnum > 1) { +//: foreach my $posb (0..$Bnum-2) { ##throughput in each atomic_m +//: my $invb = $Bnum -$posb -1; +//: print "dat${posw}_fifo${invb}_rd_pd, "; +//: } +//: } +//: print "dat${posw}_fifo0_rd_pd}; \n"; +//: } +//: +//: print "assign dat_data = { "; +//: if($Wnum > 1) { +//: foreach my $posw (0..$Wnum-2) { +//: my $invw = $Wnum - $posw -1; +//: print "dat${invw}_data, "; +//: } +//: } +//: print "dat0_data}; \n"; +//============== +// output NaN counter +//============== +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// fp16_en <= 1'b0; +// end else begin +// fp16_en <= reg2dp_input_data== 2'h2; +// end +//end +//assign dat0_is_nan_0[0] = fp16_en & (&dat0_fifo0_rd_pd[14:10]) & (|dat0_fifo0_rd_pd[9:0]); +//assign dat0_is_nan_0[1] = fp16_en & (&dat0_fifo0_rd_pd[30:26]) & (|dat0_fifo0_rd_pd[25:16]); +//assign dat0_is_nan_0[2] = fp16_en & (&dat0_fifo0_rd_pd[46:42]) & (|dat0_fifo0_rd_pd[41:32]); +//assign dat0_is_nan_0[3] = fp16_en & (&dat0_fifo0_rd_pd[62:58]) & (|dat0_fifo0_rd_pd[57:48]); +//assign dat1_is_nan_0[0] = fp16_en & (&dat1_fifo0_rd_pd[14:10]) & (|dat1_fifo0_rd_pd[9:0]); +//assign dat1_is_nan_0[1] = fp16_en & (&dat1_fifo0_rd_pd[30:26]) & (|dat1_fifo0_rd_pd[25:16]); +//assign dat1_is_nan_0[2] = fp16_en & (&dat1_fifo0_rd_pd[46:42]) & (|dat1_fifo0_rd_pd[41:32]); +//assign dat1_is_nan_0[3] = fp16_en & (&dat1_fifo0_rd_pd[62:58]) & (|dat1_fifo0_rd_pd[57:48]); +//assign dat0_is_nan_1[0] = fp16_en & (&dat0_fifo1_rd_pd[14:10]) & (|dat0_fifo1_rd_pd[9:0]); +//assign dat0_is_nan_1[1] = fp16_en & (&dat0_fifo1_rd_pd[30:26]) & (|dat0_fifo1_rd_pd[25:16]); +//assign dat0_is_nan_1[2] = fp16_en & (&dat0_fifo1_rd_pd[46:42]) & (|dat0_fifo1_rd_pd[41:32]); +//assign dat0_is_nan_1[3] = fp16_en & (&dat0_fifo1_rd_pd[62:58]) & (|dat0_fifo1_rd_pd[57:48]); +//assign dat1_is_nan_1[0] = fp16_en & (&dat1_fifo1_rd_pd[14:10]) & (|dat1_fifo1_rd_pd[9:0]); +//assign dat1_is_nan_1[1] = fp16_en & (&dat1_fifo1_rd_pd[30:26]) & (|dat1_fifo1_rd_pd[25:16]); +//assign dat1_is_nan_1[2] = fp16_en & (&dat1_fifo1_rd_pd[46:42]) & (|dat1_fifo1_rd_pd[41:32]); +//assign dat1_is_nan_1[3] = fp16_en & (&dat1_fifo1_rd_pd[62:58]) & (|dat1_fifo1_rd_pd[57:48]); +//assign dat0_is_nan_2[0] = fp16_en & (&dat0_fifo2_rd_pd[14:10]) & (|dat0_fifo2_rd_pd[9:0]); +//assign dat0_is_nan_2[1] = fp16_en & (&dat0_fifo2_rd_pd[30:26]) & (|dat0_fifo2_rd_pd[25:16]); +//assign dat0_is_nan_2[2] = fp16_en & (&dat0_fifo2_rd_pd[46:42]) & (|dat0_fifo2_rd_pd[41:32]); +//assign dat0_is_nan_2[3] = fp16_en & (&dat0_fifo2_rd_pd[62:58]) & (|dat0_fifo2_rd_pd[57:48]); +//assign dat1_is_nan_2[0] = fp16_en & (&dat1_fifo2_rd_pd[14:10]) & (|dat1_fifo2_rd_pd[9:0]); +//assign dat1_is_nan_2[1] = fp16_en & (&dat1_fifo2_rd_pd[30:26]) & (|dat1_fifo2_rd_pd[25:16]); +//assign dat1_is_nan_2[2] = fp16_en & (&dat1_fifo2_rd_pd[46:42]) & (|dat1_fifo2_rd_pd[41:32]); +//assign dat1_is_nan_2[3] = fp16_en & (&dat1_fifo2_rd_pd[62:58]) & (|dat1_fifo2_rd_pd[57:48]); +//assign dat0_is_nan_3[0] = fp16_en & (&dat0_fifo3_rd_pd[14:10]) & (|dat0_fifo3_rd_pd[9:0]); +//assign dat0_is_nan_3[1] = fp16_en & (&dat0_fifo3_rd_pd[30:26]) & (|dat0_fifo3_rd_pd[25:16]); +//assign dat0_is_nan_3[2] = fp16_en & (&dat0_fifo3_rd_pd[46:42]) & (|dat0_fifo3_rd_pd[41:32]); +//assign dat0_is_nan_3[3] = fp16_en & (&dat0_fifo3_rd_pd[62:58]) & (|dat0_fifo3_rd_pd[57:48]); +//assign dat1_is_nan_3[0] = fp16_en & (&dat1_fifo3_rd_pd[14:10]) & (|dat1_fifo3_rd_pd[9:0]); +//assign dat1_is_nan_3[1] = fp16_en & (&dat1_fifo3_rd_pd[30:26]) & (|dat1_fifo3_rd_pd[25:16]); +//assign dat1_is_nan_3[2] = fp16_en & (&dat1_fifo3_rd_pd[46:42]) & (|dat1_fifo3_rd_pd[41:32]); +//assign dat1_is_nan_3[3] = fp16_en & (&dat1_fifo3_rd_pd[62:58]) & (|dat1_fifo3_rd_pd[57:48]); +// +//assign nan_num_in_x[31:0] = {dat1_is_nan_3,dat1_is_nan_2,dat1_is_nan_1,dat1_is_nan_0,dat0_is_nan_3,dat0_is_nan_2,dat0_is_nan_1,dat0_is_nan_0}; +//assign nan_num_in_dat0_0[2:0] = (dat0_is_nan_0[0] + dat0_is_nan_0[1]) + (dat0_is_nan_0[2] + dat0_is_nan_0[3]); +//assign nan_num_in_dat0_1[2:0] = (dat0_is_nan_1[0] + dat0_is_nan_1[1]) + (dat0_is_nan_1[2] + dat0_is_nan_1[3]); +//assign nan_num_in_dat0_2[2:0] = (dat0_is_nan_2[0] + dat0_is_nan_2[1]) + (dat0_is_nan_2[2] + dat0_is_nan_2[3]); +//assign nan_num_in_dat0_3[2:0] = (dat0_is_nan_3[0] + dat0_is_nan_3[1]) + (dat0_is_nan_3[2] + dat0_is_nan_3[3]); +//assign nan_num_in_dat1_0[2:0] = (dat1_is_nan_0[0] + dat1_is_nan_0[1]) + (dat1_is_nan_0[2] + dat1_is_nan_0[3]); +//assign nan_num_in_dat1_1[2:0] = (dat1_is_nan_1[0] + dat1_is_nan_1[1]) + (dat1_is_nan_1[2] + dat1_is_nan_1[3]); +//assign nan_num_in_dat1_2[2:0] = (dat1_is_nan_2[0] + dat1_is_nan_2[1]) + (dat1_is_nan_2[2] + dat1_is_nan_2[3]); +//assign nan_num_in_dat1_3[2:0] = (dat1_is_nan_3[0] + dat1_is_nan_3[1]) + (dat1_is_nan_3[2] + dat1_is_nan_3[3]); +// +//function [5:0] fun_bit_sum_32; +// input [31:0] idata; +// reg [5:0] ocnt; +// begin +// ocnt = +// (((( idata[0] +// + idata[1] +// + idata[2] ) +// + ( idata[3] +// + idata[4] +// + idata[5] )) +// + (( idata[6] +// + idata[7] +// + idata[8] ) +// + ( idata[9] +// + idata[10] +// + idata[11] ))) +// + ((( idata[12] +// + idata[13] +// + idata[14] ) +// + ( idata[15] +// + idata[16] +// + idata[17] )) +// + (( idata[18] +// + idata[19] +// + idata[20] ) +// + ( idata[21] +// + idata[22] +// + idata[23] )))) +// + (( idata[24] +// + idata[25] +// + idata[26] ) +// + ( idata[27] +// + idata[28] +// + idata[29] )) +// + ( idata[30] +// + idata[31] ) ; +// fun_bit_sum_32 = ocnt; +// end +//endfunction +// +//assign nan_num_in_64B = fun_bit_sum_32(nan_num_in_x); +// +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// {mon_nan_in_count,nan_in_count[31:0]} <= {33{1'b0}}; +// end else begin +// if(dat_accept) begin +// if(op_done) +// {mon_nan_in_count,nan_in_count[31:0]} <= 33'd0; +// else +// {mon_nan_in_count,nan_in_count[31:0]} <= nan_in_count + nan_num_in_64B; +// end +// end +//end +//`ifdef SPYGLASS_ASSERT_ON +//`else +//// spyglass disable_block NoWidthInBasedNum-ML +//// spyglass disable_block STARC-2.10.3.2a +//// spyglass disable_block STARC05-2.1.3.1 +//// spyglass disable_block STARC-2.1.4.6 +//// spyglass disable_block W116 +//// spyglass disable_block W154 +//// spyglass disable_block W239 +//// spyglass disable_block W362 +//// spyglass disable_block WRN_58 +//// spyglass disable_block WRN_61 +//`endif // SPYGLASS_ASSERT_ON +//`ifdef ASSERT_ON +//`ifdef FV_ASSERT_ON +//`define ASSERT_RESET nvdla_core_rstn +//`else +//`ifdef SYNTHESIS +//`define ASSERT_RESET nvdla_core_rstn +//`else +//`ifdef ASSERT_OFF_RESET_IS_X +//`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +//`else +//`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +//`endif // ASSERT_OFF_RESET_IS_X +//`endif // SYNTHESIS +//`endif // FV_ASSERT_ON +// // VCS coverage off +// nv_assert_never #(0,0,"PDP WDMA: nan counter no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_nan_in_count); // spyglass disable W504 SelfDeterminedExpr-ML +// // VCS coverage on +//`undef ASSERT_RESET +//`endif // ASSERT_ON +//`ifdef SPYGLASS_ASSERT_ON +//`else +//// spyglass enable_block NoWidthInBasedNum-ML +//// spyglass enable_block STARC-2.10.3.2a +//// spyglass enable_block STARC05-2.1.3.1 +//// spyglass enable_block STARC-2.1.4.6 +//// spyglass enable_block W116 +//// spyglass enable_block W154 +//// spyglass enable_block W239 +//// spyglass enable_block W362 +//// spyglass enable_block WRN_58 +//// spyglass enable_block WRN_61 +//`endif // SPYGLASS_ASSERT_ON +// +//always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// dp2reg_nan_output_num <= {32{1'b0}}; +// end else begin +// if(op_done) +// dp2reg_nan_output_num <= nan_in_count; +// end +//end +//============== +// Instance CMD +//============== +NV_NVDLA_PDP_WDMA_cmd u_cmd ( + .reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) +// ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[79:0]) + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.op_load (op_load) + ); +// CMD FIFO: Read side +assign cmd_fifo_rd_prdy = cmd_en & dma_wr_req_rdy; +// Unpack cmd & data together +// PKT_UNPACK_WIRE( pdp_wdma_cmd , cmd_fifo_rd_ , cmd_fifo_rd_pd ) +assign cmd_fifo_rd_addr[63:0] = cmd_fifo_rd_pd[63:0]; +assign cmd_fifo_rd_size[12:0] = cmd_fifo_rd_pd[76:64]; +//assign cmd_fifo_rd_lenb[4:0] = cmd_fifo_rd_pd[78:77]; +assign cmd_fifo_rd_cube_end = cmd_fifo_rd_pd[79]; +// addr/size/lenb/end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_lenb <= 0; + end else begin + if ((dma_wr_cmd_accept) == 1'b1) begin +//: my $atomicm = 8*8; +//: my $pdpbw = 1*8; +//: my $Bnum = int($atomicm/$pdpbw); +//: print "reg_lenb <= ${Bnum} - 1;"; +//reg_lenb <= cmd_fifo_rd_lenb; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_size <= {13{1'b0}}; + end else begin + if ((dma_wr_cmd_accept) == 1'b1) begin + reg_size <= cmd_fifo_rd_size; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg_cube_last <= 1'b0; + end else begin + if ((dma_wr_cmd_accept) == 1'b1) begin + reg_cube_last <= cmd_fifo_rd_cube_end; + end + end +end +//============== +// BLOCK Operation +//============== +assign dma_wr_cmd_vld = cmd_en & cmd_fifo_rd_pvld; +assign dma_wr_cmd_accept = dma_wr_cmd_vld & dma_wr_req_rdy; +assign dma_wr_dat_vld = dat_en & dat_fifo_rd_last_pvld; +assign dat_rdy = dat_en & dma_wr_req_rdy; +assign dat_accept = dma_wr_dat_vld & dma_wr_req_rdy; +// count_w and tran_cnt is used to index 8B in each 8(B)x8(w)x4(c) block, (w may be < 8 if is_first_w or is_last_w) +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {13{1'b0}}; + end else begin + if (dma_wr_cmd_accept) begin + count_w <= 0; + end else if (dat_accept) begin +//: my $Wnum= 64/8/8; +//: print " count_w <= count_w + ${Wnum}; \n"; + end + end +end +//: my $Wnum= 64/8/8; +//: if($Wnum == 1) { +//: print qq( +//: assign is_last_beat = (count_w==reg_size); +//: ); +//: } elsif($Wnum == 2) { +//: print qq( +//: assign is_last_beat = (count_w==reg_size || count_w==reg_size-1); +//: ); +//: } elsif($Wnum == 4) { +//: print qq( +//: assign is_last_beat = (count_w==reg_size || count_w==reg_size-1 || count_w==reg_size-2 || count_w==reg_size-3); +//: ); +//: } +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (is_last_beat & dat_accept) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else if (dma_wr_cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end + end +end +//============== +// DMA REQ: Size +//============== +// packet: cmd +//assign dma_wr_cmd_vld = cmd_vld; +assign dma_wr_cmd_addr = cmd_fifo_rd_addr; +assign dma_wr_cmd_size = {10'b0, cmd_fifo_rd_size}; +assign dma_wr_cmd_require_ack = cmd_fifo_rd_cube_end; +// PKT_PACK_WIRE( dma_write_cmd , dma_wr_cmd_ , dma_wr_cmd_pd ) +assign dma_wr_cmd_pd[32 -1:0] = dma_wr_cmd_addr[32 -1:0]; +assign dma_wr_cmd_pd[32 +12:32] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[32 +13] = dma_wr_cmd_require_ack ; +// packet: data +assign dma_wr_dat_data = dat_data; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_fifo_rd_size_use <= {13{1'b0}}; + end else begin + if ((cmd_fifo_rd_pvld & cmd_fifo_rd_prdy) == 1'b1) begin + cmd_fifo_rd_size_use <= cmd_fifo_rd_size[12:0]; +// VCS coverage off + end else if ((cmd_fifo_rd_pvld & cmd_fifo_rd_prdy) == 1'b0) begin + end else begin + cmd_fifo_rd_size_use <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd_fifo_rd_pvld & cmd_fifo_rd_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//: my $msk = (64/8/8); +//: if($msk == 1) { +//: print " assign dma_wr_dat_mask = 2'b1; \n"; +//: } elsif($msk == 2) { +//: print " assign dma_wr_dat_mask = (cmd_fifo_rd_size_use[0]==0 && is_last_beat) ? 2'b01 : 2'b11; \n"; +//: } elsif($msk == 4) { +//: print " assign dma_wr_dat_mask = ((cmd_fifo_rd_size_use[1:0]==2'b00) && is_last_beat) ? 4'b0001 : \n"; +//: print " ((cmd_fifo_rd_size_use[1:0]==2'b01) && is_last_beat) ? 4'b0011 : \n"; +//: print " ((cmd_fifo_rd_size_use[1:0]==2'b10) && is_last_beat) ? 4'b0111 : 4'b1111; \n"; +//: } +// PKT_PACK_WIRE( dma_write_data , dma_wr_dat_ , dma_wr_dat_pd ) +assign dma_wr_dat_pd[64 -1:0] = dma_wr_dat_data[64 -1:0]; +assign dma_wr_dat_pd[64 +(64/8/8)-1:64] = dma_wr_dat_mask[(64/8/8)-1:0]; +// pack cmd & dat +assign dma_wr_req_vld = dma_wr_cmd_vld | dma_wr_dat_vld; +always @(*) begin +// init to 0 + dma_wr_req_pd[64 + (64/8/8)-1:0] = 0; +// cmd or dat + if (cmd_en) begin + dma_wr_req_pd[32 +13:0] = dma_wr_cmd_pd; + end else begin + dma_wr_req_pd[64 + (64/8/8)-1:0] = dma_wr_dat_pd; + end +// pkt id + dma_wr_req_pd[( 64 + (64/8/8) + 1 )-1] = cmd_en ? 1'd0 /* PKT_nvdla_dma_wr_req_dma_write_cmd_ID */ : 1'd1 /* PKT_nvdla_dma_wr_req_dma_write_data_ID */ ; +end +//============== +// reading stall counter before DMA_if +//============== +assign cnt_inc = 1'b1; +assign cnt_clr = op_done; +assign cnt_cen = (reg2dp_dma_en == 1'h1 ) & (dma_wr_req_vld & (~dma_wr_req_rdy)); + assign pdp_wr_stall_count_dec = 1'b0; +// stl adv logic + always @( + cnt_inc + or pdp_wr_stall_count_dec + ) begin + stl_adv = cnt_inc ^ pdp_wr_stall_count_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or cnt_inc + or pdp_wr_stall_count_dec + or stl_adv + or cnt_clr + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (cnt_inc && !pdp_wr_stall_count_dec)? stl_cnt_inc : (!cnt_inc && pdp_wr_stall_count_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + pdp_wr_stall_count[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_flag <= 1'b0; + end else begin + if ((cnt_clr) == 1'b1) begin + layer_flag <= ~layer_flag; +// VCS coverage off + end else if ((cnt_clr) == 1'b0) begin + end else begin + layer_flag <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & (~layer_flag)) == 1'b1) begin + dp2reg_d0_perf_write_stall <= pdp_wr_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & (~layer_flag)) == 1'b0) begin + end else begin + dp2reg_d0_perf_write_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & (~layer_flag)))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_perf_write_stall <= {32{1'b0}}; + end else begin + if ((cnt_clr & layer_flag ) == 1'b1) begin + dp2reg_d1_perf_write_stall <= pdp_wr_stall_count[31:0]; +// VCS coverage off + end else if ((cnt_clr & layer_flag ) == 1'b0) begin + end else begin + dp2reg_d1_perf_write_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cnt_clr & layer_flag ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +NV_NVDLA_DMAIF_wr NV_NVDLA_PDP_WDMA_wr( + .nvdla_core_clk (nvdla_core_clk_orig ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type ) + ,.mcif_wr_req_pd (pdp2mcif_wr_req_pd ) + ,.mcif_wr_req_valid (pdp2mcif_wr_req_valid ) + ,.mcif_wr_req_ready (pdp2mcif_wr_req_ready ) + ,.mcif_wr_rsp_complete (mcif2pdp_wr_rsp_complete) + ,.dmaif_wr_req_pd (dma_wr_req_pd ) + ,.dmaif_wr_req_pvld (dma_wr_req_vld ) + ,.dmaif_wr_req_prdy (dma_wr_req_rdy ) + ,.dmaif_wr_rsp_complete (dma_wr_rsp_complete ) +); +//logic for wdma writing done, and has accepted dma_wr_rsp_complete, but RDMA still not reading done +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wdma_done_d1 <= 1'b0; + end else begin + wdma_done_d1 <= wdma_done; + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intp_waiting_rdma <= 1'b0; + end else begin + if(dma_wr_rsp_complete & waiting_rdma) + intp_waiting_rdma <= 1'b1; + else if(wdma_done_d1) + intp_waiting_rdma <= 1'b0; + end +end +// +NV_NVDLA_PDP_WDMA_intr_fifo u_intr_fifo ( + .nvdla_core_clk (nvdla_core_clk_orig) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intr_fifo_wr_pvld (intr_fifo_wr_pvld) //|< w + ,.intr_fifo_wr_pd (intr_fifo_wr_pd) //|< w + ,.intr_fifo_rd_prdy (intr_fifo_rd_prdy) //|< w + ,.intr_fifo_rd_pvld (intr_fifo_rd_pvld) //|> w + ,.intr_fifo_rd_pd (intr_fifo_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign intr_fifo_wr_pd = reg2dp_interrupt_ptr; +assign intr_fifo_wr_pvld = wdma_done; +assign intr_fifo_rd_prdy = dma_wr_rsp_complete & (~waiting_rdma) || (intp_waiting_rdma & wdma_done_d1); +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2glb_done_intr_pd[0] <= 1'b0; + end else begin + pdp2glb_done_intr_pd[0] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==0); + end +end +always @(posedge nvdla_core_clk_orig or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pdp2glb_done_intr_pd[1] <= 1'b0; + end else begin + pdp2glb_done_intr_pd[1] <= intr_fifo_rd_pvld & intr_fifo_rd_prdy & (intr_fifo_rd_pd==1); + end +end +////============== +////OBS signals +////============== +//assign obs_bus_pdp_core_proc_en = op_prcess; +//============== +//function polint +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_WDMA__dma_writing_stall__7_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_req_vld & (~dma_wr_req_rdy); + endproperty +// Cover 7 : "dma_wr_req_vld & (~dma_wr_req_rdy)" + FUNCPOINT_PDP_WDMA__dma_writing_stall__7_COV : cover property (PDP_WDMA__dma_writing_stall__7_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_WDMA__dp2wdma_stall__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + pdp_dp2wdma_valid & (~pdp_dp2wdma_ready); + endproperty +// Cover 8 : "pdp_dp2wdma_valid & (~pdp_dp2wdma_ready)" + FUNCPOINT_PDP_WDMA__dp2wdma_stall__8_COV : cover property (PDP_WDMA__dp2wdma_stall__8_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_PDP_wdma +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_PDP_WDMA_intr_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus intr_fifo_wr -rd_pipebus intr_fifo_rd -ram_bypass -d 0 -rd_reg -rd_busy_reg -no_wr_busy -w 1 -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_PDP_WDMA_intr_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intr_fifo_wr_pvld + , intr_fifo_wr_pd + , intr_fifo_rd_prdy + , intr_fifo_rd_pvld + , intr_fifo_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +input intr_fifo_wr_pvld; +input intr_fifo_wr_pd; +input intr_fifo_rd_prdy; +output intr_fifo_rd_pvld; +output intr_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] intr_fifo_rd_pd_p = intr_fifo_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg intr_fifo_rd_prdy_d; // intr_fifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_prdy_d <= 1'b1; + end else begin + intr_fifo_rd_prdy_d <= intr_fifo_rd_prdy; + end +end +wire intr_fifo_rd_prdy_d_o; // combinatorial rd_busy +reg intr_fifo_rd_pvld_int; // internal copy of intr_fifo_rd_pvld +assign intr_fifo_rd_pvld = intr_fifo_rd_pvld_int; +wire intr_fifo_rd_pvld_p = intr_fifo_wr_pvld ; // no real fifo, take from write-side input +reg intr_fifo_rd_pvld_int_o; // internal copy of intr_fifo_rd_pvld_o +wire intr_fifo_rd_pvld_o = intr_fifo_rd_pvld_int_o; +wire rd_popping = intr_fifo_rd_pvld_p && !(intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg intr_fifo_rd_pd_o; // output data register +wire rd_req_next_o = (intr_fifo_rd_pvld_p || (intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int_o <= 1'b0; + end else begin + intr_fifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + intr_fifo_rd_pd_o <= intr_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + intr_fifo_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg intr_fifo_rd_pd; // output data register +reg intr_fifo_rd_pvld_int_d; // so we can bubble-collapse intr_fifo_rd_prdy_d +assign intr_fifo_rd_prdy_d_o = !((intr_fifo_rd_pvld_o && intr_fifo_rd_pvld_int_d && !intr_fifo_rd_prdy_d ) ); +wire rd_req_next = (!intr_fifo_rd_prdy_d_o ? intr_fifo_rd_pvld_o : intr_fifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int <= 1'b0; + intr_fifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) begin + intr_fifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy) ) begin + end else begin + intr_fifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + intr_fifo_rd_pvld_int_d <= intr_fifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) ) begin + case (!intr_fifo_rd_prdy_d_o) + 1'b0: intr_fifo_rd_pd <= intr_fifo_rd_pd_p; + 1'b1: intr_fifo_rd_pd <= intr_fifo_rd_pd_o; +//VCS coverage off + default: intr_fifo_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy)) ) begin + end else begin + intr_fifo_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (intr_fifo_wr_pvld || (intr_fifo_rd_pvld_int && intr_fifo_rd_prdy_d) || (intr_fifo_rd_pvld_int_o && intr_fifo_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_PDP_WDMA_intr_fifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_PDP_WDMA_intr_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_pdp.v b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_pdp.v new file mode 100644 index 0000000..b01e2ca --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_pdp.v @@ -0,0 +1,3115 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_pdp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_pdp ( + dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2pdp_rdma_req_pvld //|< i + ,csb2pdp_rdma_req_prdy //|> o + ,csb2pdp_rdma_req_pd //|< i + ,csb2pdp_req_pvld //|< i + ,csb2pdp_req_prdy //|> o + ,csb2pdp_req_pd //|< i + ,mcif2pdp_rd_rsp_valid //|< i + ,mcif2pdp_rd_rsp_ready //|> o + ,mcif2pdp_rd_rsp_pd //|< i + ,mcif2pdp_wr_rsp_complete //|< i + ,pdp2csb_resp_valid //|> o + ,pdp2csb_resp_pd //|> o + ,pdp2glb_done_intr_pd //|> o + ,pdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,pdp2mcif_rd_req_valid //|> o + ,pdp2mcif_rd_req_ready //|< i + ,pdp2mcif_rd_req_pd //|> o + ,pdp2mcif_wr_req_valid //|> o + ,pdp2mcif_wr_req_ready //|< i + ,pdp2mcif_wr_req_pd //|> o + ,pdp_rdma2csb_resp_valid //|> o + ,pdp_rdma2csb_resp_pd //|> o + ,pwrbus_ram_pd //|< i + ,sdp2pdp_valid //|< i + ,sdp2pdp_ready //|> o + ,sdp2pdp_pd //|< i + ); +/////////////////////////////////////////////////////////////////////// +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; + input nvdla_core_clk; + input nvdla_core_rstn; + input csb2pdp_rdma_req_pvld; + output csb2pdp_rdma_req_prdy; + input [62:0] csb2pdp_rdma_req_pd; + input csb2pdp_req_pvld; + output csb2pdp_req_prdy; + input [62:0] csb2pdp_req_pd; + input mcif2pdp_rd_rsp_valid; + output mcif2pdp_rd_rsp_ready; + input [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd; + input mcif2pdp_wr_rsp_complete; + output pdp2csb_resp_valid; + output [33:0] pdp2csb_resp_pd; + output [1:0] pdp2glb_done_intr_pd; + output pdp2mcif_rd_cdt_lat_fifo_pop; + output pdp2mcif_rd_req_valid; + input pdp2mcif_rd_req_ready; + output [32 +14:0] pdp2mcif_rd_req_pd; + output pdp2mcif_wr_req_valid; + input pdp2mcif_wr_req_ready; + output [( 64 + (64/8/8) + 1 )-1:0] pdp2mcif_wr_req_pd; + output pdp_rdma2csb_resp_valid; + output [33:0] pdp_rdma2csb_resp_pd; + input [31:0] pwrbus_ram_pd; + input sdp2pdp_valid; + output sdp2pdp_ready; + input [8*1 -1:0] sdp2pdp_pd; +/////////////////////////////////////////////////////////////////////// + wire aver_pooling_en; + wire [31:0] dp2reg_d0_perf_write_stall; + wire [31:0] dp2reg_d1_perf_write_stall; + wire dp2reg_done; + wire mon_op_en_neg; + wire mon_op_en_pos; + wire [8*1 +11:0] nan_preproc_pd; + wire nan_preproc_prdy; + wire nan_preproc_pvld; + wire nvdla_op_gated_clk_core; + wire nvdla_op_gated_clk_wdma; + wire [8*1 -1:0] pdp_dp2wdma_pd; + wire pdp_dp2wdma_ready; + wire pdp_dp2wdma_valid; + wire [8*1 +11:0] pdp_rdma2dp_pd; + wire pdp_rdma2dp_ready; + wire pdp_rdma2dp_valid; + wire rdma2wdma_done; + wire [12:0] reg2dp_cube_in_channel; + wire [12:0] reg2dp_cube_in_height; + wire [12:0] reg2dp_cube_in_width; + wire [12:0] reg2dp_cube_out_channel; + wire [12:0] reg2dp_cube_out_height; + wire [12:0] reg2dp_cube_out_width; + wire [31:0] reg2dp_cya; + wire reg2dp_dma_en; + wire [31:0] reg2dp_dst_base_addr_high; + wire [31:0] reg2dp_dst_base_addr_low; + wire [31:0] reg2dp_dst_line_stride; + wire reg2dp_dst_ram_type; + wire [31:0] reg2dp_dst_surface_stride; + wire reg2dp_flying_mode; +// wire [1:0] reg2dp_input_data; + wire reg2dp_interrupt_ptr; + wire [3:0] reg2dp_kernel_height; + wire [3:0] reg2dp_kernel_stride_height; + wire [3:0] reg2dp_kernel_stride_width; + wire [3:0] reg2dp_kernel_width; + wire reg2dp_nan_to_zero; + wire reg2dp_op_en; + wire [2:0] reg2dp_pad_bottom; + wire [2:0] reg2dp_pad_left; + wire [2:0] reg2dp_pad_right; + wire [2:0] reg2dp_pad_top; + wire [18:0] reg2dp_pad_value_1x; + wire [18:0] reg2dp_pad_value_2x; + wire [18:0] reg2dp_pad_value_3x; + wire [18:0] reg2dp_pad_value_4x; + wire [18:0] reg2dp_pad_value_5x; + wire [18:0] reg2dp_pad_value_6x; + wire [18:0] reg2dp_pad_value_7x; + wire [9:0] reg2dp_partial_width_in_first; + wire [9:0] reg2dp_partial_width_in_last; + wire [9:0] reg2dp_partial_width_in_mid; + wire [9:0] reg2dp_partial_width_out_first; + wire [9:0] reg2dp_partial_width_out_last; + wire [9:0] reg2dp_partial_width_out_mid; + wire [1:0] reg2dp_pooling_method; + wire [16:0] reg2dp_recip_kernel_height; + wire [16:0] reg2dp_recip_kernel_width; + wire [7:0] reg2dp_split_num; + wire [31:0] reg2dp_src_base_addr_high; + wire [31:0] reg2dp_src_base_addr_low; + wire [31:0] reg2dp_src_line_stride; + wire [31:0] reg2dp_src_surface_stride; + wire [2:0] slcg_op_en; + reg [31:0] mon_gap_between_layers; + reg mon_layer_end_flg; + reg mon_op_en_dly; + reg [12:0] mon_reg2dp_cube_in_channel; + reg [12:0] mon_reg2dp_cube_in_height; + reg [12:0] mon_reg2dp_cube_in_width; + reg [12:0] mon_reg2dp_cube_out_channel; + reg [12:0] mon_reg2dp_cube_out_height; + reg [12:0] mon_reg2dp_cube_out_width; + reg mon_reg2dp_flying_mode; + reg [3:0] mon_reg2dp_kernel_height; + reg [3:0] mon_reg2dp_kernel_stride_height; + reg [3:0] mon_reg2dp_kernel_stride_width; + reg [3:0] mon_reg2dp_kernel_width; + reg mon_reg2dp_nan_to_zero; + reg [2:0] mon_reg2dp_pad_bottom; + reg [2:0] mon_reg2dp_pad_left; + reg [2:0] mon_reg2dp_pad_right; + reg [2:0] mon_reg2dp_pad_top; + reg [9:0] mon_reg2dp_partial_width_in_first; + reg [9:0] mon_reg2dp_partial_width_in_last; + reg [9:0] mon_reg2dp_partial_width_in_mid; + reg [9:0] mon_reg2dp_partial_width_out_first; + reg [9:0] mon_reg2dp_partial_width_out_last; + reg [9:0] mon_reg2dp_partial_width_out_mid; + reg [1:0] mon_reg2dp_pooling_method; + reg [7:0] mon_reg2dp_split_num; +/////////////////////////////////////////////////////////////////////// +//======================================= +//RDMA +//--------------------------------------- + NV_NVDLA_PDP_rdma u_rdma ( + .rdma2wdma_done (rdma2wdma_done) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd[62:0]) + ,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid) + ,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready) + ,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd) + ,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop) + ,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid) + ,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready) + ,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd) + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd[33:0]) + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//======================================= +// SLCG gen unit +//--------------------------------------- +// assign fp16_en = reg2dp_input_data== 2'h2 ; + assign aver_pooling_en = reg2dp_pooling_method== 2'h0 ; + NV_NVDLA_PDP_slcg u_slcg_core ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[0]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_core) + ); + NV_NVDLA_PDP_slcg u_slcg_wdma ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[1]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_wdma) + ); +// NV_NVDLA_PDP_slcg u_slcg_fp16 ( +// .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) +// ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) +// ,.nvdla_core_clk (nvdla_core_clk) +// ,.nvdla_core_rstn (nvdla_core_rstn) +// ,.slcg_en_src (slcg_op_en[2] & fp16_en & aver_pooling_en) +// ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) +// ,.nvdla_core_gated_clk (nvdla_op_gated_clk_fp16) +// ); +//======================================= +//NaN control of RDMA output data +//--------------------------------------- + NV_NVDLA_PDP_nan u_nan ( + .nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dp2reg_done (dp2reg_done) + ,.nan_preproc_prdy (nan_preproc_prdy) + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.dp2reg_inf_input_num () //dp2reg_inf_input_num[31:0]) + ,.dp2reg_nan_input_num () //dp2reg_nan_input_num[31:0]) + ,.nan_preproc_pd (nan_preproc_pd) + ,.nan_preproc_pvld (nan_preproc_pvld) + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) + ); +//assign nan_preproc_pd = pdp_rdma2dp_pd; +//assign nan_preproc_pvld = pdp_rdma2dp_valid; +//assign pdp_rdma2dp_ready = nan_preproc_prdy; +//======================================= +//WDMA +//--------------------------------------- + NV_NVDLA_PDP_wdma u_wdma ( + .nvdla_core_clk (nvdla_op_gated_clk_wdma) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid) + ,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready) + ,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd) + ,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete) + ,.pdp_dp2wdma_valid (pdp_dp2wdma_valid) + ,.pdp_dp2wdma_ready (pdp_dp2wdma_ready) + ,.pdp_dp2wdma_pd (pdp_dp2wdma_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) + ,.rdma2wdma_done (rdma2wdma_done) + ,.reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low ({reg2dp_dst_base_addr_low[31:0]}) + ,.reg2dp_dst_line_stride ({reg2dp_dst_line_stride[31:0]}) + ,.reg2dp_dst_surface_stride ({reg2dp_dst_surface_stride[31:0]}) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.nvdla_core_clk_orig (nvdla_core_clk) + ); +//======================================== +//PDP core instance +//---------------------------------------- + NV_NVDLA_PDP_core u_core ( + .nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.datin_src_cfg (reg2dp_flying_mode) + ,.dp2reg_done (dp2reg_done) + ,.padding_h_cfg (reg2dp_pad_left[2:0]) + ,.padding_v_cfg (reg2dp_pad_top[2:0]) + ,.pdp_dp2wdma_ready (pdp_dp2wdma_ready) + ,.pdp_rdma2dp_pd (nan_preproc_pd) + ,.pdp_rdma2dp_valid (nan_preproc_pvld) + ,.pooling_channel_cfg (reg2dp_cube_out_channel[12:0]) + ,.pooling_fwidth_cfg (reg2dp_partial_width_in_first[9:0]) + ,.pooling_lwidth_cfg (reg2dp_partial_width_in_last[9:0]) + ,.pooling_mwidth_cfg (reg2dp_partial_width_in_mid[9:0]) + ,.pooling_out_fwidth_cfg (reg2dp_partial_width_out_first[9:0]) + ,.pooling_out_lwidth_cfg (reg2dp_partial_width_out_last[9:0]) + ,.pooling_out_mwidth_cfg (reg2dp_partial_width_out_mid[9:0]) + ,.pooling_size_h_cfg (reg2dp_kernel_width[2:0]) + ,.pooling_size_v_cfg (reg2dp_kernel_height[2:0]) + ,.pooling_splitw_num_cfg (reg2dp_split_num[7:0]) + ,.pooling_stride_h_cfg (reg2dp_kernel_stride_width[3:0]) + ,.pooling_stride_v_cfg (reg2dp_kernel_stride_height[3:0]) + ,.pooling_type_cfg (reg2dp_pooling_method[1:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_flying_mode (reg2dp_flying_mode) +// ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_kernel_height (reg2dp_kernel_height[2:0]) + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) + ,.reg2dp_kernel_width (reg2dp_kernel_width[2:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_bottom_cfg (reg2dp_pad_bottom[2:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[2:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[2:0]) + ,.reg2dp_pad_right_cfg (reg2dp_pad_right[2:0]) + ,.reg2dp_pad_top (reg2dp_pad_top[2:0]) + ,.reg2dp_pad_value_1x_cfg (reg2dp_pad_value_1x[18:0]) + ,.reg2dp_pad_value_2x_cfg (reg2dp_pad_value_2x[18:0]) + ,.reg2dp_pad_value_3x_cfg (reg2dp_pad_value_3x[18:0]) + ,.reg2dp_pad_value_4x_cfg (reg2dp_pad_value_4x[18:0]) + ,.reg2dp_pad_value_5x_cfg (reg2dp_pad_value_5x[18:0]) + ,.reg2dp_pad_value_6x_cfg (reg2dp_pad_value_6x[18:0]) + ,.reg2dp_pad_value_7x_cfg (reg2dp_pad_value_7x[18:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_recip_height_cfg (reg2dp_recip_kernel_height[16:0]) + ,.reg2dp_recip_width_cfg (reg2dp_recip_kernel_width[16:0]) + ,.sdp2pdp_pd (sdp2pdp_pd) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.pdp_dp2wdma_pd (pdp_dp2wdma_pd) + ,.pdp_dp2wdma_valid (pdp_dp2wdma_valid) + ,.pdp_rdma2dp_ready (nan_preproc_prdy) + ,.sdp2pdp_ready (sdp2pdp_ready) + ); +//======================================= +//CONFIG instance +//rdma has seperate config register, while wdma share with core +//--------------------------------------- + NV_NVDLA_PDP_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2pdp_req_pd (csb2pdp_req_pd[62:0]) + ,.csb2pdp_req_pvld (csb2pdp_req_pvld) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_inf_input_num (32'd0)//dp2reg_inf_input_num[31:0]) + ,.dp2reg_nan_input_num (32'd0)//dp2reg_nan_input_num[31:0]) + ,.dp2reg_nan_output_num (32'd0)//dp2reg_nan_output_num[31:0]) + ,.csb2pdp_req_prdy (csb2pdp_req_prdy) + ,.pdp2csb_resp_pd (pdp2csb_resp_pd[33:0]) + ,.pdp2csb_resp_valid (pdp2csb_resp_valid) + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) + ,.reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_input_data () //|> w + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_kernel_height (reg2dp_kernel_height[3:0]) + ,.reg2dp_kernel_stride_height (reg2dp_kernel_stride_height[3:0]) + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) + ,.reg2dp_kernel_width (reg2dp_kernel_width[3:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_bottom (reg2dp_pad_bottom[2:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[2:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[2:0]) + ,.reg2dp_pad_top (reg2dp_pad_top[2:0]) + ,.reg2dp_pad_value_1x (reg2dp_pad_value_1x[18:0]) + ,.reg2dp_pad_value_2x (reg2dp_pad_value_2x[18:0]) + ,.reg2dp_pad_value_3x (reg2dp_pad_value_3x[18:0]) + ,.reg2dp_pad_value_4x (reg2dp_pad_value_4x[18:0]) + ,.reg2dp_pad_value_5x (reg2dp_pad_value_5x[18:0]) + ,.reg2dp_pad_value_6x (reg2dp_pad_value_6x[18:0]) + ,.reg2dp_pad_value_7x (reg2dp_pad_value_7x[18:0]) + ,.reg2dp_partial_width_in_first (reg2dp_partial_width_in_first[9:0]) + ,.reg2dp_partial_width_in_last (reg2dp_partial_width_in_last[9:0]) + ,.reg2dp_partial_width_in_mid (reg2dp_partial_width_in_mid[9:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_pooling_method (reg2dp_pooling_method[1:0]) + ,.reg2dp_recip_kernel_height (reg2dp_recip_kernel_height[16:0]) + ,.reg2dp_recip_kernel_width (reg2dp_recip_kernel_width[16:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) + ,.slcg_op_en (slcg_op_en[2:0]) + ); +// //============== +// //OBS signals +// //============== +// //assign obs_bus_cdp_core_clk = nvdla_core_clk; +// //assign obs_bus_cdp_core_rstn = nvdla_core_rstn; +// assign obs_bus_pdp_csb_req_vld = csb2pdp_req_pvld; +// assign obs_bus_pdp_csb_req_rdy = csb2pdp_req_prdy; +// assign obs_bus_pdp_rdma_mc_rd_req_vld = pdp2mcif_rd_req_valid; +// assign obs_bus_pdp_rdma_mc_rd_req_rdy = pdp2mcif_rd_req_ready; +// assign obs_bus_pdp_rdma_cv_rd_req_vld = pdp2cvif_rd_req_valid; +// assign obs_bus_pdp_rdma_cv_rd_req_rdy = pdp2cvif_rd_req_ready; +// assign obs_bus_pdp_rdma_mc_rd_rsp_vld = mcif2pdp_rd_rsp_valid; +// assign obs_bus_pdp_rdma_mc_rd_rsp_rdy = mcif2pdp_rd_rsp_ready; +// assign obs_bus_pdp_rdma_cv_rd_rsp_vld = cvif2pdp_rd_rsp_valid; +// assign obs_bus_pdp_rdma_cv_rd_rsp_rdy = cvif2pdp_rd_rsp_ready; +// assign obs_bus_pdp_wdma_mc_wr_vld = pdp2mcif_wr_req_valid; +// assign obs_bus_pdp_wdma_mc_wr_rdy = pdp2mcif_wr_req_ready; +// assign obs_bus_pdp_wdma_cv_wr_vld = pdp2cvif_wr_req_valid; +// assign obs_bus_pdp_wdma_cv_wr_rdy = pdp2cvif_wr_req_ready; +//============== +//cfg assertion +//============== +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 2X != 1X * 2") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_2x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd2}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 3X != 1X * 3") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_3x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd3}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 4X != 1X * 4") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_4x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd4}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 5X != 1X * 5") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_5x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd5}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 6X != 1X * 6") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_6x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd6}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 7X != 1X * 7") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_7x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd7}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////// +////pdp cube_out_width setting, limited by line buffer size +//////////////////////////////// +////non-split mode +////two sub-cube split mode +////more than two sub-cube split mode +////////////////////////////// +//overlap vs partial width/partial_width in +//a) when split into 2 sub-cube, that is split_num=1, +//when kernel >=kernel_stride, overlap = kernel - kernel_stride, overlap <= width_first; +//when kernel < kernel_stride, overlap = kernel_stride - kernel, overlap < width_last , for this item, i think current constrain has cover it. because subcube num in output side equals to that in input side, and partial out first/right are all >=1 element; +//b) split_num>=2 +//when kernel >=kernel_stride, overlap = kernel - kernel_stride, overlap <= min(width_first, width_mid); +//when kernel < kernel_stride, overlap = kernel_stride - kernel, overlap < min(width_mid, width_last) , for this item, i think current constrain has cover it. because subcube num in output side equals to that in input side, and partial out first/mid/right are all >=1 element; +////////////////////////////// +//split into 2 sub-cube +////split into more than 2 sub-cube +//============== +//function points +//============== +/////////////// +//1*1*1 cube output +/////////////// +//1*1*1 cube output for nonsplit mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// reg funcpoint_cover_off; +// initial begin +// if ( $test$plusargs( "cover_off" ) ) begin +// funcpoint_cover_off = 1'b1; +// end else begin +// funcpoint_cover_off = 1'b0; +// end +// end +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_average_pooling__0_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 0 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_average_pooling__0_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_average_pooling__0_cov); +// +// `endif +//`endif +////VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_average_pooling__1_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 1 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_average_pooling__1_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_average_pooling__1_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_average_pooling__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 2 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_average_pooling__2_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_average_pooling__2_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_max_pooling__3_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 3 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_max_pooling__3_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_max_pooling__3_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_max_pooling__4_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 4 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_max_pooling__4_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_max_pooling__4_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_max_pooling__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 5 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_max_pooling__5_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_max_pooling__5_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_min_pooling__6_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 6 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_min_pooling__6_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_min_pooling__6_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_min_pooling__7_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 7 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_min_pooling__7_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_min_pooling__7_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_min_pooling__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 8 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_min_pooling__8_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_min_pooling__8_cov); + `endif +`endif +//VCS coverage on +////1*1*1 cube output for split 2 mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split2_average_pooling__9_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 9 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split2_average_pooling__9_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split2_average_pooling__9_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split2_average_pooling__10_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 10 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split2_average_pooling__10_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split2_average_pooling__10_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split2_average_pooling__11_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 11 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split2_average_pooling__11_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split2_average_pooling__11_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split2_max_pooling__12_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 12 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split2_max_pooling__12_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split2_max_pooling__12_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split2_max_pooling__13_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 13 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split2_max_pooling__13_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split2_max_pooling__13_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split2_max_pooling__14_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 14 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split2_max_pooling__14_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split2_max_pooling__14_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split2_min_pooling__15_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 15 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split2_min_pooling__15_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split2_min_pooling__15_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split2_min_pooling__16_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 16 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split2_min_pooling__16_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split2_min_pooling__16_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split2_min_pooling__17_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 17 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split2_min_pooling__17_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split2_min_pooling__17_cov); + `endif +`endif +//VCS coverage on +//1*1*1 cube output for split >2 mode +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split3_average_pooling__18_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 18 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split3_average_pooling__18_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split3_average_pooling__18_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split3_average_pooling__19_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 19 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split3_average_pooling__19_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split3_average_pooling__19_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split3_average_pooling__20_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 20 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split3_average_pooling__20_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split3_average_pooling__20_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split3_max_pooling__21_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 21 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split3_max_pooling__21_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split3_max_pooling__21_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split3_max_pooling__22_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 22 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split3_max_pooling__22_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split3_max_pooling__22_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split3_max_pooling__23_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 23 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split3_max_pooling__23_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split3_max_pooling__23_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split3_min_pooling__24_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 24 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split3_min_pooling__24_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split3_min_pooling__24_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split3_min_pooling__25_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 25 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split3_min_pooling__25_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split3_min_pooling__25_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split3_min_pooling__26_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 26 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split3_min_pooling__26_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split3_min_pooling__26_cov); + `endif +`endif +//VCS coverage on +//rdma lattency_buffer is full, but core op_en not trigger +//two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_layer__27_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 27 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_PDP_CORE_two_continuous_layer__27_COV : cover property (PDP_CORE_two_continuous_layer__27_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +//different config between two continous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_in_channel <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_in_channel <= reg2dp_cube_in_channel; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_in_channel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_in_height <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_in_height <= reg2dp_cube_in_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_in_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_in_width <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_in_width <= reg2dp_cube_in_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_in_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_out_channel <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_out_channel <= reg2dp_cube_out_channel; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_out_channel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_out_height <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_out_height <= reg2dp_cube_out_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_out_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_out_width <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_out_width <= reg2dp_cube_out_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_out_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_in_first <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_in_first <= reg2dp_partial_width_in_first; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_in_first <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_in_last <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_in_last <= reg2dp_partial_width_in_last; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_in_last <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_in_mid <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_in_mid <= reg2dp_partial_width_in_mid; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_in_mid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_out_first <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_out_first <= reg2dp_partial_width_out_first; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_out_first <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_out_last <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_out_last <= reg2dp_partial_width_out_last; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_out_last <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_out_mid <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_out_mid <= reg2dp_partial_width_out_mid; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_out_mid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_flying_mode <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_flying_mode <= reg2dp_flying_mode; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_flying_mode <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// // spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +// mon_reg2dp_input_data <= {2{1'b0}}; +// // spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +// end else begin +// if ((mon_op_en_pos) == 1'b1) begin +// mon_reg2dp_input_data <= reg2dp_input_data; +// // VCS coverage off +// end else if ((mon_op_en_pos) == 1'b0) begin +// end else begin +// mon_reg2dp_input_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// // VCS coverage on +// end +// end +// end +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass disable_block NoWidthInBasedNum-ML +// // spyglass disable_block STARC-2.10.3.2a +// // spyglass disable_block STARC05-2.1.3.1 +// // spyglass disable_block STARC-2.1.4.6 +// // spyglass disable_block W116 +// // spyglass disable_block W154 +// // spyglass disable_block W239 +// // spyglass disable_block W362 +// // spyglass disable_block WRN_58 +// // spyglass disable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +// `ifdef ASSERT_ON +// `ifdef FV_ASSERT_ON +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef SYNTHESIS +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef ASSERT_OFF_RESET_IS_X +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +// `else +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +// `endif // ASSERT_OFF_RESET_IS_X +// `endif // SYNTHESIS +// `endif // FV_ASSERT_ON +// `ifndef SYNTHESIS +// // VCS coverage off +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// // VCS coverage on +// `endif +// `undef ASSERT_RESET +// `endif // ASSERT_ON +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass enable_block NoWidthInBasedNum-ML +// // spyglass enable_block STARC-2.10.3.2a +// // spyglass enable_block STARC05-2.1.3.1 +// // spyglass enable_block STARC-2.1.4.6 +// // spyglass enable_block W116 +// // spyglass enable_block W154 +// // spyglass enable_block W239 +// // spyglass enable_block W362 +// // spyglass enable_block WRN_58 +// // spyglass enable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_height <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_height <= reg2dp_kernel_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_width <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_width <= reg2dp_kernel_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_stride_height <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_stride_height <= reg2dp_kernel_stride_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_stride_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_stride_width <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_stride_width <= reg2dp_kernel_stride_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_stride_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_nan_to_zero <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_nan_to_zero <= reg2dp_nan_to_zero; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_nan_to_zero <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_bottom <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_bottom <= reg2dp_pad_bottom; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_bottom <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_left <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_left <= reg2dp_pad_left; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_left <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_right <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_right <= reg2dp_pad_right; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_right <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_top <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_top <= reg2dp_pad_top; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_top <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pooling_method <= {2{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pooling_method <= reg2dp_pooling_method; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pooling_method <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_split_num <= {8{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_split_num <= reg2dp_split_num; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_split_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_in_w__28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_in_width!=reg2dp_cube_in_width)); + endproperty +// Cover 28 : "(mon_reg2dp_cube_in_width!=reg2dp_cube_in_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_in_w__28_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_in_w__28_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_in_h__29_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_in_height!=reg2dp_cube_in_height)); + endproperty +// Cover 29 : "(mon_reg2dp_cube_in_height!=reg2dp_cube_in_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_in_h__29_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_in_h__29_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_in_c__30_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_in_channel!=reg2dp_cube_in_channel)); + endproperty +// Cover 30 : "(mon_reg2dp_cube_in_channel!=reg2dp_cube_in_channel)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_in_c__30_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_in_c__30_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_out_w__31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_out_width!=reg2dp_cube_out_width)); + endproperty +// Cover 31 : "(mon_reg2dp_cube_out_width!=reg2dp_cube_out_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_out_w__31_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_out_w__31_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_out_h__32_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_out_height!=reg2dp_cube_out_height)); + endproperty +// Cover 32 : "(mon_reg2dp_cube_out_height!=reg2dp_cube_out_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_out_h__32_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_out_h__32_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_out_c__33_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_out_channel!=reg2dp_cube_out_channel)); + endproperty +// Cover 33 : "(mon_reg2dp_cube_out_channel!=reg2dp_cube_out_channel)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_out_c__33_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_out_c__33_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_f__34_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_in_first!=reg2dp_partial_width_in_first)); + endproperty +// Cover 34 : "(mon_reg2dp_partial_width_in_first!=reg2dp_partial_width_in_first)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_f__34_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_f__34_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_m__35_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_in_mid!=reg2dp_partial_width_in_mid)); + endproperty +// Cover 35 : "(mon_reg2dp_partial_width_in_mid!=reg2dp_partial_width_in_mid)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_m__35_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_m__35_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_l__36_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_in_last!=reg2dp_partial_width_in_last)); + endproperty +// Cover 36 : "(mon_reg2dp_partial_width_in_last!=reg2dp_partial_width_in_last)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_l__36_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_l__36_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_f__37_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_out_first!=reg2dp_partial_width_out_first)); + endproperty +// Cover 37 : "(mon_reg2dp_partial_width_out_first!=reg2dp_partial_width_out_first)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_f__37_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_f__37_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_m__38_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_out_mid!=reg2dp_partial_width_out_mid)); + endproperty +// Cover 38 : "(mon_reg2dp_partial_width_out_mid!=reg2dp_partial_width_out_mid)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_m__38_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_m__38_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_l__39_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_out_last!=reg2dp_partial_width_out_last)); + endproperty +// Cover 39 : "(mon_reg2dp_partial_width_out_last!=reg2dp_partial_width_out_last)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_l__39_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_l__39_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_onfly_2_offfly__40_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_flying_mode == 1'h0 ) & (reg2dp_flying_mode== 1'h1 )); + endproperty +// Cover 40 : "(mon_reg2dp_flying_mode == 1'h0 ) & (reg2dp_flying_mode== 1'h1 )" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_onfly_2_offfly__40_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_onfly_2_offfly__40_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_offfly_2_onfly__41_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_flying_mode == 1'h1 ) & (reg2dp_flying_mode== 1'h0 )); + endproperty +// Cover 41 : "(mon_reg2dp_flying_mode == 1'h1 ) & (reg2dp_flying_mode== 1'h0 )" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_offfly_2_onfly__41_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_offfly_2_onfly__41_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_CORE_two_continuous_changed_layer__change_data_type__42_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_input_data!=reg2dp_input_data)); +// endproperty +// // Cover 42 : "(mon_reg2dp_input_data!=reg2dp_input_data)" +// FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_data_type__42_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_data_type__42_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_w__43_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_width!=reg2dp_kernel_width)); + endproperty +// Cover 43 : "(mon_reg2dp_kernel_width!=reg2dp_kernel_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_w__43_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_w__43_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_h__44_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_height!=reg2dp_kernel_height)); + endproperty +// Cover 44 : "(mon_reg2dp_kernel_height!=reg2dp_kernel_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_h__44_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_h__44_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_stride_w__45_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_stride_width!=reg2dp_kernel_stride_width)); + endproperty +// Cover 45 : "(mon_reg2dp_kernel_stride_width!=reg2dp_kernel_stride_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_stride_w__45_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_stride_w__45_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_stride_h__46_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_stride_height!=reg2dp_kernel_stride_height)); + endproperty +// Cover 46 : "(mon_reg2dp_kernel_stride_height!=reg2dp_kernel_stride_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_stride_h__46_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_stride_h__46_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_nan2zero__47_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)); + endproperty +// Cover 47 : "(mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_nan2zero__47_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_nan2zero__47_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_bottom__48_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_bottom!=reg2dp_pad_bottom)); + endproperty +// Cover 48 : "(mon_reg2dp_pad_bottom!=reg2dp_pad_bottom)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_bottom__48_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_bottom__48_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_left__49_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_left!=reg2dp_pad_left)); + endproperty +// Cover 49 : "(mon_reg2dp_pad_left!=reg2dp_pad_left)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_left__49_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_left__49_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_right__50_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_right!=reg2dp_pad_right)); + endproperty +// Cover 50 : "(mon_reg2dp_pad_right!=reg2dp_pad_right)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_right__50_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_right__50_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_top__51_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_top!=reg2dp_pad_top)); + endproperty +// Cover 51 : "(mon_reg2dp_pad_top!=reg2dp_pad_top)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_top__51_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_top__51_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pooling_type__52_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pooling_method!=reg2dp_pooling_method)); + endproperty +// Cover 52 : "(mon_reg2dp_pooling_method!=reg2dp_pooling_method)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pooling_type__52_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pooling_type__52_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_split_num__53_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_split_num!=reg2dp_split_num)); + endproperty +// Cover 53 : "(mon_reg2dp_split_num!=reg2dp_split_num)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_split_num__53_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_split_num__53_cov); + `endif +`endif +//VCS coverage on +//============== +endmodule // NV_NVDLA_pdp diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_pdp.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_pdp.v.vcp new file mode 100644 index 0000000..b01e2ca --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/NV_NVDLA_pdp.v.vcp @@ -0,0 +1,3115 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_pdp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_PDP_define.h +///////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////// +module NV_NVDLA_pdp ( + dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2pdp_rdma_req_pvld //|< i + ,csb2pdp_rdma_req_prdy //|> o + ,csb2pdp_rdma_req_pd //|< i + ,csb2pdp_req_pvld //|< i + ,csb2pdp_req_prdy //|> o + ,csb2pdp_req_pd //|< i + ,mcif2pdp_rd_rsp_valid //|< i + ,mcif2pdp_rd_rsp_ready //|> o + ,mcif2pdp_rd_rsp_pd //|< i + ,mcif2pdp_wr_rsp_complete //|< i + ,pdp2csb_resp_valid //|> o + ,pdp2csb_resp_pd //|> o + ,pdp2glb_done_intr_pd //|> o + ,pdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,pdp2mcif_rd_req_valid //|> o + ,pdp2mcif_rd_req_ready //|< i + ,pdp2mcif_rd_req_pd //|> o + ,pdp2mcif_wr_req_valid //|> o + ,pdp2mcif_wr_req_ready //|< i + ,pdp2mcif_wr_req_pd //|> o + ,pdp_rdma2csb_resp_valid //|> o + ,pdp_rdma2csb_resp_pd //|> o + ,pwrbus_ram_pd //|< i + ,sdp2pdp_valid //|< i + ,sdp2pdp_ready //|> o + ,sdp2pdp_pd //|< i + ); +/////////////////////////////////////////////////////////////////////// +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; + input nvdla_core_clk; + input nvdla_core_rstn; + input csb2pdp_rdma_req_pvld; + output csb2pdp_rdma_req_prdy; + input [62:0] csb2pdp_rdma_req_pd; + input csb2pdp_req_pvld; + output csb2pdp_req_prdy; + input [62:0] csb2pdp_req_pd; + input mcif2pdp_rd_rsp_valid; + output mcif2pdp_rd_rsp_ready; + input [( 64 + (64/8/8) )-1:0] mcif2pdp_rd_rsp_pd; + input mcif2pdp_wr_rsp_complete; + output pdp2csb_resp_valid; + output [33:0] pdp2csb_resp_pd; + output [1:0] pdp2glb_done_intr_pd; + output pdp2mcif_rd_cdt_lat_fifo_pop; + output pdp2mcif_rd_req_valid; + input pdp2mcif_rd_req_ready; + output [32 +14:0] pdp2mcif_rd_req_pd; + output pdp2mcif_wr_req_valid; + input pdp2mcif_wr_req_ready; + output [( 64 + (64/8/8) + 1 )-1:0] pdp2mcif_wr_req_pd; + output pdp_rdma2csb_resp_valid; + output [33:0] pdp_rdma2csb_resp_pd; + input [31:0] pwrbus_ram_pd; + input sdp2pdp_valid; + output sdp2pdp_ready; + input [8*1 -1:0] sdp2pdp_pd; +/////////////////////////////////////////////////////////////////////// + wire aver_pooling_en; + wire [31:0] dp2reg_d0_perf_write_stall; + wire [31:0] dp2reg_d1_perf_write_stall; + wire dp2reg_done; + wire mon_op_en_neg; + wire mon_op_en_pos; + wire [8*1 +11:0] nan_preproc_pd; + wire nan_preproc_prdy; + wire nan_preproc_pvld; + wire nvdla_op_gated_clk_core; + wire nvdla_op_gated_clk_wdma; + wire [8*1 -1:0] pdp_dp2wdma_pd; + wire pdp_dp2wdma_ready; + wire pdp_dp2wdma_valid; + wire [8*1 +11:0] pdp_rdma2dp_pd; + wire pdp_rdma2dp_ready; + wire pdp_rdma2dp_valid; + wire rdma2wdma_done; + wire [12:0] reg2dp_cube_in_channel; + wire [12:0] reg2dp_cube_in_height; + wire [12:0] reg2dp_cube_in_width; + wire [12:0] reg2dp_cube_out_channel; + wire [12:0] reg2dp_cube_out_height; + wire [12:0] reg2dp_cube_out_width; + wire [31:0] reg2dp_cya; + wire reg2dp_dma_en; + wire [31:0] reg2dp_dst_base_addr_high; + wire [31:0] reg2dp_dst_base_addr_low; + wire [31:0] reg2dp_dst_line_stride; + wire reg2dp_dst_ram_type; + wire [31:0] reg2dp_dst_surface_stride; + wire reg2dp_flying_mode; +// wire [1:0] reg2dp_input_data; + wire reg2dp_interrupt_ptr; + wire [3:0] reg2dp_kernel_height; + wire [3:0] reg2dp_kernel_stride_height; + wire [3:0] reg2dp_kernel_stride_width; + wire [3:0] reg2dp_kernel_width; + wire reg2dp_nan_to_zero; + wire reg2dp_op_en; + wire [2:0] reg2dp_pad_bottom; + wire [2:0] reg2dp_pad_left; + wire [2:0] reg2dp_pad_right; + wire [2:0] reg2dp_pad_top; + wire [18:0] reg2dp_pad_value_1x; + wire [18:0] reg2dp_pad_value_2x; + wire [18:0] reg2dp_pad_value_3x; + wire [18:0] reg2dp_pad_value_4x; + wire [18:0] reg2dp_pad_value_5x; + wire [18:0] reg2dp_pad_value_6x; + wire [18:0] reg2dp_pad_value_7x; + wire [9:0] reg2dp_partial_width_in_first; + wire [9:0] reg2dp_partial_width_in_last; + wire [9:0] reg2dp_partial_width_in_mid; + wire [9:0] reg2dp_partial_width_out_first; + wire [9:0] reg2dp_partial_width_out_last; + wire [9:0] reg2dp_partial_width_out_mid; + wire [1:0] reg2dp_pooling_method; + wire [16:0] reg2dp_recip_kernel_height; + wire [16:0] reg2dp_recip_kernel_width; + wire [7:0] reg2dp_split_num; + wire [31:0] reg2dp_src_base_addr_high; + wire [31:0] reg2dp_src_base_addr_low; + wire [31:0] reg2dp_src_line_stride; + wire [31:0] reg2dp_src_surface_stride; + wire [2:0] slcg_op_en; + reg [31:0] mon_gap_between_layers; + reg mon_layer_end_flg; + reg mon_op_en_dly; + reg [12:0] mon_reg2dp_cube_in_channel; + reg [12:0] mon_reg2dp_cube_in_height; + reg [12:0] mon_reg2dp_cube_in_width; + reg [12:0] mon_reg2dp_cube_out_channel; + reg [12:0] mon_reg2dp_cube_out_height; + reg [12:0] mon_reg2dp_cube_out_width; + reg mon_reg2dp_flying_mode; + reg [3:0] mon_reg2dp_kernel_height; + reg [3:0] mon_reg2dp_kernel_stride_height; + reg [3:0] mon_reg2dp_kernel_stride_width; + reg [3:0] mon_reg2dp_kernel_width; + reg mon_reg2dp_nan_to_zero; + reg [2:0] mon_reg2dp_pad_bottom; + reg [2:0] mon_reg2dp_pad_left; + reg [2:0] mon_reg2dp_pad_right; + reg [2:0] mon_reg2dp_pad_top; + reg [9:0] mon_reg2dp_partial_width_in_first; + reg [9:0] mon_reg2dp_partial_width_in_last; + reg [9:0] mon_reg2dp_partial_width_in_mid; + reg [9:0] mon_reg2dp_partial_width_out_first; + reg [9:0] mon_reg2dp_partial_width_out_last; + reg [9:0] mon_reg2dp_partial_width_out_mid; + reg [1:0] mon_reg2dp_pooling_method; + reg [7:0] mon_reg2dp_split_num; +/////////////////////////////////////////////////////////////////////// +//======================================= +//RDMA +//--------------------------------------- + NV_NVDLA_PDP_rdma u_rdma ( + .rdma2wdma_done (rdma2wdma_done) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd[62:0]) + ,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid) + ,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready) + ,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd) + ,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop) + ,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid) + ,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready) + ,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd) + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd[33:0]) + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//======================================= +// SLCG gen unit +//--------------------------------------- +// assign fp16_en = reg2dp_input_data== 2'h2 ; + assign aver_pooling_en = reg2dp_pooling_method== 2'h0 ; + NV_NVDLA_PDP_slcg u_slcg_core ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[0]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_core) + ); + NV_NVDLA_PDP_slcg u_slcg_wdma ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.slcg_en_src (slcg_op_en[1]) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_wdma) + ); +// NV_NVDLA_PDP_slcg u_slcg_fp16 ( +// .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) +// ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) +// ,.nvdla_core_clk (nvdla_core_clk) +// ,.nvdla_core_rstn (nvdla_core_rstn) +// ,.slcg_en_src (slcg_op_en[2] & fp16_en & aver_pooling_en) +// ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) +// ,.nvdla_core_gated_clk (nvdla_op_gated_clk_fp16) +// ); +//======================================= +//NaN control of RDMA output data +//--------------------------------------- + NV_NVDLA_PDP_nan u_nan ( + .nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dp2reg_done (dp2reg_done) + ,.nan_preproc_prdy (nan_preproc_prdy) + ,.pdp_rdma2dp_pd (pdp_rdma2dp_pd) + ,.pdp_rdma2dp_valid (pdp_rdma2dp_valid) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.dp2reg_inf_input_num () //dp2reg_inf_input_num[31:0]) + ,.dp2reg_nan_input_num () //dp2reg_nan_input_num[31:0]) + ,.nan_preproc_pd (nan_preproc_pd) + ,.nan_preproc_pvld (nan_preproc_pvld) + ,.pdp_rdma2dp_ready (pdp_rdma2dp_ready) + ); +//assign nan_preproc_pd = pdp_rdma2dp_pd; +//assign nan_preproc_pvld = pdp_rdma2dp_valid; +//assign pdp_rdma2dp_ready = nan_preproc_prdy; +//======================================= +//WDMA +//--------------------------------------- + NV_NVDLA_PDP_wdma u_wdma ( + .nvdla_core_clk (nvdla_op_gated_clk_wdma) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid) + ,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready) + ,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd) + ,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete) + ,.pdp_dp2wdma_valid (pdp_dp2wdma_valid) + ,.pdp_dp2wdma_ready (pdp_dp2wdma_ready) + ,.pdp_dp2wdma_pd (pdp_dp2wdma_pd) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) + ,.rdma2wdma_done (rdma2wdma_done) + ,.reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low ({reg2dp_dst_base_addr_low[31:0]}) + ,.reg2dp_dst_line_stride ({reg2dp_dst_line_stride[31:0]}) + ,.reg2dp_dst_surface_stride ({reg2dp_dst_surface_stride[31:0]}) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.nvdla_core_clk_orig (nvdla_core_clk) + ); +//======================================== +//PDP core instance +//---------------------------------------- + NV_NVDLA_PDP_core u_core ( + .nvdla_core_clk (nvdla_op_gated_clk_core) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.datin_src_cfg (reg2dp_flying_mode) + ,.dp2reg_done (dp2reg_done) + ,.padding_h_cfg (reg2dp_pad_left[2:0]) + ,.padding_v_cfg (reg2dp_pad_top[2:0]) + ,.pdp_dp2wdma_ready (pdp_dp2wdma_ready) + ,.pdp_rdma2dp_pd (nan_preproc_pd) + ,.pdp_rdma2dp_valid (nan_preproc_pvld) + ,.pooling_channel_cfg (reg2dp_cube_out_channel[12:0]) + ,.pooling_fwidth_cfg (reg2dp_partial_width_in_first[9:0]) + ,.pooling_lwidth_cfg (reg2dp_partial_width_in_last[9:0]) + ,.pooling_mwidth_cfg (reg2dp_partial_width_in_mid[9:0]) + ,.pooling_out_fwidth_cfg (reg2dp_partial_width_out_first[9:0]) + ,.pooling_out_lwidth_cfg (reg2dp_partial_width_out_last[9:0]) + ,.pooling_out_mwidth_cfg (reg2dp_partial_width_out_mid[9:0]) + ,.pooling_size_h_cfg (reg2dp_kernel_width[2:0]) + ,.pooling_size_v_cfg (reg2dp_kernel_height[2:0]) + ,.pooling_splitw_num_cfg (reg2dp_split_num[7:0]) + ,.pooling_stride_h_cfg (reg2dp_kernel_stride_width[3:0]) + ,.pooling_stride_v_cfg (reg2dp_kernel_stride_height[3:0]) + ,.pooling_type_cfg (reg2dp_pooling_method[1:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_flying_mode (reg2dp_flying_mode) +// ,.reg2dp_input_data (reg2dp_input_data[1:0]) + ,.reg2dp_kernel_height (reg2dp_kernel_height[2:0]) + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) + ,.reg2dp_kernel_width (reg2dp_kernel_width[2:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_bottom_cfg (reg2dp_pad_bottom[2:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[2:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[2:0]) + ,.reg2dp_pad_right_cfg (reg2dp_pad_right[2:0]) + ,.reg2dp_pad_top (reg2dp_pad_top[2:0]) + ,.reg2dp_pad_value_1x_cfg (reg2dp_pad_value_1x[18:0]) + ,.reg2dp_pad_value_2x_cfg (reg2dp_pad_value_2x[18:0]) + ,.reg2dp_pad_value_3x_cfg (reg2dp_pad_value_3x[18:0]) + ,.reg2dp_pad_value_4x_cfg (reg2dp_pad_value_4x[18:0]) + ,.reg2dp_pad_value_5x_cfg (reg2dp_pad_value_5x[18:0]) + ,.reg2dp_pad_value_6x_cfg (reg2dp_pad_value_6x[18:0]) + ,.reg2dp_pad_value_7x_cfg (reg2dp_pad_value_7x[18:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_recip_height_cfg (reg2dp_recip_kernel_height[16:0]) + ,.reg2dp_recip_width_cfg (reg2dp_recip_kernel_width[16:0]) + ,.sdp2pdp_pd (sdp2pdp_pd) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.pdp_dp2wdma_pd (pdp_dp2wdma_pd) + ,.pdp_dp2wdma_valid (pdp_dp2wdma_valid) + ,.pdp_rdma2dp_ready (nan_preproc_prdy) + ,.sdp2pdp_ready (sdp2pdp_ready) + ); +//======================================= +//CONFIG instance +//rdma has seperate config register, while wdma share with core +//--------------------------------------- + NV_NVDLA_PDP_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2pdp_req_pd (csb2pdp_req_pd[62:0]) + ,.csb2pdp_req_pvld (csb2pdp_req_pvld) + ,.dp2reg_d0_perf_write_stall (dp2reg_d0_perf_write_stall[31:0]) + ,.dp2reg_d1_perf_write_stall (dp2reg_d1_perf_write_stall[31:0]) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_inf_input_num (32'd0)//dp2reg_inf_input_num[31:0]) + ,.dp2reg_nan_input_num (32'd0)//dp2reg_nan_input_num[31:0]) + ,.dp2reg_nan_output_num (32'd0)//dp2reg_nan_output_num[31:0]) + ,.csb2pdp_req_prdy (csb2pdp_req_prdy) + ,.pdp2csb_resp_pd (pdp2csb_resp_pd[33:0]) + ,.pdp2csb_resp_valid (pdp2csb_resp_valid) + ,.reg2dp_cube_in_channel (reg2dp_cube_in_channel[12:0]) + ,.reg2dp_cube_in_height (reg2dp_cube_in_height[12:0]) + ,.reg2dp_cube_in_width (reg2dp_cube_in_width[12:0]) + ,.reg2dp_cube_out_channel (reg2dp_cube_out_channel[12:0]) + ,.reg2dp_cube_out_height (reg2dp_cube_out_height[12:0]) + ,.reg2dp_cube_out_width (reg2dp_cube_out_width[12:0]) + ,.reg2dp_cya (reg2dp_cya[31:0]) + ,.reg2dp_dma_en (reg2dp_dma_en) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_input_data () //|> w + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_kernel_height (reg2dp_kernel_height[3:0]) + ,.reg2dp_kernel_stride_height (reg2dp_kernel_stride_height[3:0]) + ,.reg2dp_kernel_stride_width (reg2dp_kernel_stride_width[3:0]) + ,.reg2dp_kernel_width (reg2dp_kernel_width[3:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_pad_bottom (reg2dp_pad_bottom[2:0]) + ,.reg2dp_pad_left (reg2dp_pad_left[2:0]) + ,.reg2dp_pad_right (reg2dp_pad_right[2:0]) + ,.reg2dp_pad_top (reg2dp_pad_top[2:0]) + ,.reg2dp_pad_value_1x (reg2dp_pad_value_1x[18:0]) + ,.reg2dp_pad_value_2x (reg2dp_pad_value_2x[18:0]) + ,.reg2dp_pad_value_3x (reg2dp_pad_value_3x[18:0]) + ,.reg2dp_pad_value_4x (reg2dp_pad_value_4x[18:0]) + ,.reg2dp_pad_value_5x (reg2dp_pad_value_5x[18:0]) + ,.reg2dp_pad_value_6x (reg2dp_pad_value_6x[18:0]) + ,.reg2dp_pad_value_7x (reg2dp_pad_value_7x[18:0]) + ,.reg2dp_partial_width_in_first (reg2dp_partial_width_in_first[9:0]) + ,.reg2dp_partial_width_in_last (reg2dp_partial_width_in_last[9:0]) + ,.reg2dp_partial_width_in_mid (reg2dp_partial_width_in_mid[9:0]) + ,.reg2dp_partial_width_out_first (reg2dp_partial_width_out_first[9:0]) + ,.reg2dp_partial_width_out_last (reg2dp_partial_width_out_last[9:0]) + ,.reg2dp_partial_width_out_mid (reg2dp_partial_width_out_mid[9:0]) + ,.reg2dp_pooling_method (reg2dp_pooling_method[1:0]) + ,.reg2dp_recip_kernel_height (reg2dp_recip_kernel_height[16:0]) + ,.reg2dp_recip_kernel_width (reg2dp_recip_kernel_width[16:0]) + ,.reg2dp_split_num (reg2dp_split_num[7:0]) + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) + ,.slcg_op_en (slcg_op_en[2:0]) + ); +// //============== +// //OBS signals +// //============== +// //assign obs_bus_cdp_core_clk = nvdla_core_clk; +// //assign obs_bus_cdp_core_rstn = nvdla_core_rstn; +// assign obs_bus_pdp_csb_req_vld = csb2pdp_req_pvld; +// assign obs_bus_pdp_csb_req_rdy = csb2pdp_req_prdy; +// assign obs_bus_pdp_rdma_mc_rd_req_vld = pdp2mcif_rd_req_valid; +// assign obs_bus_pdp_rdma_mc_rd_req_rdy = pdp2mcif_rd_req_ready; +// assign obs_bus_pdp_rdma_cv_rd_req_vld = pdp2cvif_rd_req_valid; +// assign obs_bus_pdp_rdma_cv_rd_req_rdy = pdp2cvif_rd_req_ready; +// assign obs_bus_pdp_rdma_mc_rd_rsp_vld = mcif2pdp_rd_rsp_valid; +// assign obs_bus_pdp_rdma_mc_rd_rsp_rdy = mcif2pdp_rd_rsp_ready; +// assign obs_bus_pdp_rdma_cv_rd_rsp_vld = cvif2pdp_rd_rsp_valid; +// assign obs_bus_pdp_rdma_cv_rd_rsp_rdy = cvif2pdp_rd_rsp_ready; +// assign obs_bus_pdp_wdma_mc_wr_vld = pdp2mcif_wr_req_valid; +// assign obs_bus_pdp_wdma_mc_wr_rdy = pdp2mcif_wr_req_ready; +// assign obs_bus_pdp_wdma_cv_wr_vld = pdp2cvif_wr_req_valid; +// assign obs_bus_pdp_wdma_cv_wr_rdy = pdp2cvif_wr_req_ready; +//============== +//cfg assertion +//============== +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 2X != 1X * 2") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_2x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd2}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 3X != 1X * 3") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_3x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd3}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 4X != 1X * 4") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_4x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd4}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 5X != 1X * 5") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_5x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd5}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 6X != 1X * 6") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_6x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd6}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"PDPCore pad_value setting issue: 7X != 1X * 7") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, aver_pooling_en & reg2dp_op_en & (reg2dp_pad_value_7x != $signed(reg2dp_pad_value_1x) * $signed({1'b0,4'd7}))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////// +////pdp cube_out_width setting, limited by line buffer size +//////////////////////////////// +////non-split mode +////two sub-cube split mode +////more than two sub-cube split mode +////////////////////////////// +//overlap vs partial width/partial_width in +//a) when split into 2 sub-cube, that is split_num=1, +//when kernel >=kernel_stride, overlap = kernel - kernel_stride, overlap <= width_first; +//when kernel < kernel_stride, overlap = kernel_stride - kernel, overlap < width_last , for this item, i think current constrain has cover it. because subcube num in output side equals to that in input side, and partial out first/right are all >=1 element; +//b) split_num>=2 +//when kernel >=kernel_stride, overlap = kernel - kernel_stride, overlap <= min(width_first, width_mid); +//when kernel < kernel_stride, overlap = kernel_stride - kernel, overlap < min(width_mid, width_last) , for this item, i think current constrain has cover it. because subcube num in output side equals to that in input side, and partial out first/mid/right are all >=1 element; +////////////////////////////// +//split into 2 sub-cube +////split into more than 2 sub-cube +//============== +//function points +//============== +/////////////// +//1*1*1 cube output +/////////////// +//1*1*1 cube output for nonsplit mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// reg funcpoint_cover_off; +// initial begin +// if ( $test$plusargs( "cover_off" ) ) begin +// funcpoint_cover_off = 1'b1; +// end else begin +// funcpoint_cover_off = 1'b0; +// end +// end +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_average_pooling__0_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 0 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_average_pooling__0_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_average_pooling__0_cov); +// +// `endif +//`endif +////VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_average_pooling__1_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 1 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_average_pooling__1_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_average_pooling__1_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_average_pooling__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 2 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_average_pooling__2_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_average_pooling__2_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_max_pooling__3_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 3 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_max_pooling__3_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_max_pooling__3_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_max_pooling__4_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 4 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_max_pooling__4_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_max_pooling__4_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_max_pooling__5_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 5 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_max_pooling__5_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_max_pooling__5_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_min_pooling__6_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 6 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_min_pooling__6_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_nonsplit_min_pooling__6_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_min_pooling__7_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 7 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_min_pooling__7_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_nonsplit_min_pooling__7_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_min_pooling__8_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 8 : "reg2dp_op_en & (reg2dp_split_num==8'd0) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_cube_out_width)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_min_pooling__8_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_nonsplit_min_pooling__8_cov); + `endif +`endif +//VCS coverage on +////1*1*1 cube output for split 2 mode +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split2_average_pooling__9_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 9 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split2_average_pooling__9_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split2_average_pooling__9_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split2_average_pooling__10_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 10 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split2_average_pooling__10_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split2_average_pooling__10_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split2_average_pooling__11_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 11 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split2_average_pooling__11_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split2_average_pooling__11_cov); + `endif +`endif +//VCS coverage on +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split2_max_pooling__12_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 12 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split2_max_pooling__12_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split2_max_pooling__12_cov); +// +// `endif +//`endif +////VCS coverage on +// +////VCS coverage off +//`ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split2_max_pooling__13_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 13 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split2_max_pooling__13_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split2_max_pooling__13_cov); +// +// `endif +//`endif +////VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split2_max_pooling__14_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 14 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split2_max_pooling__14_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split2_max_pooling__14_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split2_min_pooling__15_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 15 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split2_min_pooling__15_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split2_min_pooling__15_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split2_min_pooling__16_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 16 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split2_min_pooling__16_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split2_min_pooling__16_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split2_min_pooling__17_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 17 : "reg2dp_op_en & (reg2dp_split_num==8'd1) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split2_min_pooling__17_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split2_min_pooling__17_cov); + `endif +`endif +//VCS coverage on +//1*1*1 cube output for split >2 mode +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split3_average_pooling__18_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 18 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split3_average_pooling__18_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split3_average_pooling__18_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split3_average_pooling__19_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 19 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split3_average_pooling__19_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split3_average_pooling__19_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split3_average_pooling__20_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 20 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h0 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split3_average_pooling__20_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split3_average_pooling__20_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split3_max_pooling__21_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 21 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split3_max_pooling__21_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split3_max_pooling__21_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split3_max_pooling__22_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 22 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split3_max_pooling__22_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split3_max_pooling__22_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split3_max_pooling__23_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 23 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h1 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split3_max_pooling__23_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split3_max_pooling__23_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_fp16_split3_min_pooling__24_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 24 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h2 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_fp16_split3_min_pooling__24_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_fp16_split3_min_pooling__24_cov); +// +// `endif +// `endif +// //VCS coverage on +// +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_min_cube_out__1_1_1_cube_out_int16_split3_min_pooling__25_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); +// endproperty +// // Cover 25 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_input_data== 2'h1 ) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" +// FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int16_split3_min_pooling__25_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int16_split3_min_pooling__25_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_min_cube_out__1_1_1_cube_out_int8_split3_min_pooling__26_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel)); + endproperty +// Cover 26 : "reg2dp_op_en & (reg2dp_split_num>=8'd2) & (reg2dp_pooling_method== 2'h2 ) & (~(|reg2dp_partial_width_out_first)) & (~(|reg2dp_partial_width_out_last)) & (~(|reg2dp_partial_width_out_mid)) & (~(|reg2dp_cube_out_height)) & (~(|reg2dp_cube_out_channel))" + FUNCPOINT_PDP_min_cube_out__1_1_1_cube_out_int8_split3_min_pooling__26_COV : cover property (PDP_min_cube_out__1_1_1_cube_out_int8_split3_min_pooling__26_cov); + `endif +`endif +//VCS coverage on +//rdma lattency_buffer is full, but core op_en not trigger +//two continuous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_op_en_dly <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + mon_op_en_dly <= reg2dp_op_en; + end +end +assign mon_op_en_pos = reg2dp_op_en & (~mon_op_en_dly); +assign mon_op_en_neg = (~reg2dp_op_en) & mon_op_en_dly; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_layer_end_flg <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_op_en_neg) + mon_layer_end_flg <= 1'b1; + else if(mon_op_en_pos) + mon_layer_end_flg <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_gap_between_layers[31:0] <= {32{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if(mon_layer_end_flg) + mon_gap_between_layers[31:0] <= mon_gap_between_layers + 1'b1; + else + mon_gap_between_layers[31:0] <= 32'd0; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_layer__27_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + (mon_gap_between_layers==32'd2) & mon_op_en_pos; + endproperty +// Cover 27 : "(mon_gap_between_layers==32'd2) & mon_op_en_pos" + FUNCPOINT_PDP_CORE_two_continuous_layer__27_COV : cover property (PDP_CORE_two_continuous_layer__27_cov); + `endif +`endif +//VCS coverage on +//3 cycles means continuous layer +//different config between two continous layers +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_in_channel <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_in_channel <= reg2dp_cube_in_channel; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_in_channel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_in_height <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_in_height <= reg2dp_cube_in_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_in_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_in_width <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_in_width <= reg2dp_cube_in_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_in_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_out_channel <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_out_channel <= reg2dp_cube_out_channel; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_out_channel <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_out_height <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_out_height <= reg2dp_cube_out_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_out_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_cube_out_width <= {13{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_cube_out_width <= reg2dp_cube_out_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_cube_out_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_in_first <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_in_first <= reg2dp_partial_width_in_first; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_in_first <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_in_last <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_in_last <= reg2dp_partial_width_in_last; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_in_last <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_in_mid <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_in_mid <= reg2dp_partial_width_in_mid; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_in_mid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_out_first <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_out_first <= reg2dp_partial_width_out_first; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_out_first <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_out_last <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_out_last <= reg2dp_partial_width_out_last; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_out_last <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_partial_width_out_mid <= {10{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_partial_width_out_mid <= reg2dp_partial_width_out_mid; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_partial_width_out_mid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_flying_mode <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_flying_mode <= reg2dp_flying_mode; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_flying_mode <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin +// if (!nvdla_core_rstn) begin +// // spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +// mon_reg2dp_input_data <= {2{1'b0}}; +// // spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a +// end else begin +// if ((mon_op_en_pos) == 1'b1) begin +// mon_reg2dp_input_data <= reg2dp_input_data; +// // VCS coverage off +// end else if ((mon_op_en_pos) == 1'b0) begin +// end else begin +// mon_reg2dp_input_data <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// // VCS coverage on +// end +// end +// end +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass disable_block NoWidthInBasedNum-ML +// // spyglass disable_block STARC-2.10.3.2a +// // spyglass disable_block STARC05-2.1.3.1 +// // spyglass disable_block STARC-2.1.4.6 +// // spyglass disable_block W116 +// // spyglass disable_block W154 +// // spyglass disable_block W239 +// // spyglass disable_block W362 +// // spyglass disable_block WRN_58 +// // spyglass disable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +// `ifdef ASSERT_ON +// `ifdef FV_ASSERT_ON +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef SYNTHESIS +// `define ASSERT_RESET nvdla_core_rstn +// `else +// `ifdef ASSERT_OFF_RESET_IS_X +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +// `else +// `define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +// `endif // ASSERT_OFF_RESET_IS_X +// `endif // SYNTHESIS +// `endif // FV_ASSERT_ON +// `ifndef SYNTHESIS +// // VCS coverage off +// nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// // VCS coverage on +// `endif +// `undef ASSERT_RESET +// `endif // ASSERT_ON +// `ifdef SPYGLASS_ASSERT_ON +// `else +// // spyglass enable_block NoWidthInBasedNum-ML +// // spyglass enable_block STARC-2.10.3.2a +// // spyglass enable_block STARC05-2.1.3.1 +// // spyglass enable_block STARC-2.1.4.6 +// // spyglass enable_block W116 +// // spyglass enable_block W154 +// // spyglass enable_block W239 +// // spyglass enable_block W362 +// // spyglass enable_block WRN_58 +// // spyglass enable_block WRN_61 +// `endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_height <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_height <= reg2dp_kernel_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_width <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_width <= reg2dp_kernel_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_stride_height <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_stride_height <= reg2dp_kernel_stride_height; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_stride_height <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_kernel_stride_width <= {4{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_kernel_stride_width <= reg2dp_kernel_stride_width; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_kernel_stride_width <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_nan_to_zero <= 1'b0; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_nan_to_zero <= reg2dp_nan_to_zero; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_nan_to_zero <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_bottom <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_bottom <= reg2dp_pad_bottom; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_bottom <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_left <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_left <= reg2dp_pad_left; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_left <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_right <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_right <= reg2dp_pad_right; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_right <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pad_top <= {3{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pad_top <= reg2dp_pad_top; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pad_top <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_pooling_method <= {2{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_pooling_method <= reg2dp_pooling_method; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_pooling_method <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin +// spyglass disable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + mon_reg2dp_split_num <= {8{1'b0}}; +// spyglass enable_block UnloadedNet-ML UnloadedOutTerm-ML W528 W123 W287a + end else begin + if ((mon_op_en_pos) == 1'b1) begin + mon_reg2dp_split_num <= reg2dp_split_num; +// VCS coverage off + end else if ((mon_op_en_pos) == 1'b0) begin + end else begin + mon_reg2dp_split_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(mon_op_en_pos))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_in_w__28_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_in_width!=reg2dp_cube_in_width)); + endproperty +// Cover 28 : "(mon_reg2dp_cube_in_width!=reg2dp_cube_in_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_in_w__28_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_in_w__28_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_in_h__29_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_in_height!=reg2dp_cube_in_height)); + endproperty +// Cover 29 : "(mon_reg2dp_cube_in_height!=reg2dp_cube_in_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_in_h__29_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_in_h__29_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_in_c__30_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_in_channel!=reg2dp_cube_in_channel)); + endproperty +// Cover 30 : "(mon_reg2dp_cube_in_channel!=reg2dp_cube_in_channel)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_in_c__30_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_in_c__30_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_out_w__31_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_out_width!=reg2dp_cube_out_width)); + endproperty +// Cover 31 : "(mon_reg2dp_cube_out_width!=reg2dp_cube_out_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_out_w__31_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_out_w__31_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_out_h__32_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_out_height!=reg2dp_cube_out_height)); + endproperty +// Cover 32 : "(mon_reg2dp_cube_out_height!=reg2dp_cube_out_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_out_h__32_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_out_h__32_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_out_c__33_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_cube_out_channel!=reg2dp_cube_out_channel)); + endproperty +// Cover 33 : "(mon_reg2dp_cube_out_channel!=reg2dp_cube_out_channel)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_out_c__33_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_out_c__33_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_f__34_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_in_first!=reg2dp_partial_width_in_first)); + endproperty +// Cover 34 : "(mon_reg2dp_partial_width_in_first!=reg2dp_partial_width_in_first)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_f__34_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_f__34_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_m__35_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_in_mid!=reg2dp_partial_width_in_mid)); + endproperty +// Cover 35 : "(mon_reg2dp_partial_width_in_mid!=reg2dp_partial_width_in_mid)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_m__35_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_m__35_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_l__36_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_in_last!=reg2dp_partial_width_in_last)); + endproperty +// Cover 36 : "(mon_reg2dp_partial_width_in_last!=reg2dp_partial_width_in_last)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_l__36_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_in_l__36_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_f__37_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_out_first!=reg2dp_partial_width_out_first)); + endproperty +// Cover 37 : "(mon_reg2dp_partial_width_out_first!=reg2dp_partial_width_out_first)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_f__37_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_f__37_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_m__38_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_out_mid!=reg2dp_partial_width_out_mid)); + endproperty +// Cover 38 : "(mon_reg2dp_partial_width_out_mid!=reg2dp_partial_width_out_mid)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_m__38_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_m__38_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_l__39_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_partial_width_out_last!=reg2dp_partial_width_out_last)); + endproperty +// Cover 39 : "(mon_reg2dp_partial_width_out_last!=reg2dp_partial_width_out_last)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_l__39_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_cube_partial_out_l__39_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_onfly_2_offfly__40_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_flying_mode == 1'h0 ) & (reg2dp_flying_mode== 1'h1 )); + endproperty +// Cover 40 : "(mon_reg2dp_flying_mode == 1'h0 ) & (reg2dp_flying_mode== 1'h1 )" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_onfly_2_offfly__40_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_onfly_2_offfly__40_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_offfly_2_onfly__41_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_flying_mode == 1'h1 ) & (reg2dp_flying_mode== 1'h0 )); + endproperty +// Cover 41 : "(mon_reg2dp_flying_mode == 1'h1 ) & (reg2dp_flying_mode== 1'h0 )" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_offfly_2_onfly__41_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_offfly_2_onfly__41_cov); + `endif +`endif +//VCS coverage on +// //VCS coverage off +// `ifndef DISABLE_FUNCPOINT +// `ifdef ENABLE_FUNCPOINT +// +// property PDP_CORE_two_continuous_changed_layer__change_data_type__42_cov; +// disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) +// @(posedge nvdla_core_clk) +// ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_input_data!=reg2dp_input_data)); +// endproperty +// // Cover 42 : "(mon_reg2dp_input_data!=reg2dp_input_data)" +// FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_data_type__42_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_data_type__42_cov); +// +// `endif +// `endif +// //VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_w__43_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_width!=reg2dp_kernel_width)); + endproperty +// Cover 43 : "(mon_reg2dp_kernel_width!=reg2dp_kernel_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_w__43_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_w__43_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_h__44_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_height!=reg2dp_kernel_height)); + endproperty +// Cover 44 : "(mon_reg2dp_kernel_height!=reg2dp_kernel_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_h__44_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_h__44_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_stride_w__45_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_stride_width!=reg2dp_kernel_stride_width)); + endproperty +// Cover 45 : "(mon_reg2dp_kernel_stride_width!=reg2dp_kernel_stride_width)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_stride_w__45_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_stride_w__45_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_kernel_stride_h__46_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_kernel_stride_height!=reg2dp_kernel_stride_height)); + endproperty +// Cover 46 : "(mon_reg2dp_kernel_stride_height!=reg2dp_kernel_stride_height)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_kernel_stride_h__46_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_kernel_stride_h__46_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_nan2zero__47_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)); + endproperty +// Cover 47 : "(mon_reg2dp_nan_to_zero!=reg2dp_nan_to_zero)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_nan2zero__47_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_nan2zero__47_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_bottom__48_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_bottom!=reg2dp_pad_bottom)); + endproperty +// Cover 48 : "(mon_reg2dp_pad_bottom!=reg2dp_pad_bottom)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_bottom__48_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_bottom__48_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_left__49_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_left!=reg2dp_pad_left)); + endproperty +// Cover 49 : "(mon_reg2dp_pad_left!=reg2dp_pad_left)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_left__49_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_left__49_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_right__50_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_right!=reg2dp_pad_right)); + endproperty +// Cover 50 : "(mon_reg2dp_pad_right!=reg2dp_pad_right)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_right__50_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_right__50_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pad_top__51_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pad_top!=reg2dp_pad_top)); + endproperty +// Cover 51 : "(mon_reg2dp_pad_top!=reg2dp_pad_top)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pad_top__51_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pad_top__51_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_pooling_type__52_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_pooling_method!=reg2dp_pooling_method)); + endproperty +// Cover 52 : "(mon_reg2dp_pooling_method!=reg2dp_pooling_method)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_pooling_type__52_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_pooling_type__52_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property PDP_CORE_two_continuous_changed_layer__change_split_num__53_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((mon_op_en_pos) && nvdla_core_rstn) |-> ((mon_reg2dp_split_num!=reg2dp_split_num)); + endproperty +// Cover 53 : "(mon_reg2dp_split_num!=reg2dp_split_num)" + FUNCPOINT_PDP_CORE_two_continuous_changed_layer__change_split_num__53_COV : cover property (PDP_CORE_two_continuous_changed_layer__change_split_num__53_cov); + `endif +`endif +//VCS coverage on +//============== +endmodule // NV_NVDLA_pdp diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v b/designs/src/NVDLA/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v new file mode 100644 index 0000000..81d2f54 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v @@ -0,0 +1,143 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: cal1d_fp16_pool_sum.v +module cal1d_fp16_pool_sum ( + inp_a_0 //|< i + ,inp_a_1 //|< i + ,inp_a_2 //|< i + ,inp_a_3 //|< i + ,inp_b_0 //|< i + ,inp_b_1 //|< i + ,inp_b_2 //|< i + ,inp_b_3 //|< i + ,inp_in_pvld //|< i + ,inp_out_prdy //|< i + ,nvdla_core_rstn //|< i + ,nvdla_op_gated_clk_fp16 //|< i + ,inp_in_prdy //|> o + ,inp_out_pvld //|> o + ,out_z_0 //|> o + ,out_z_1 //|> o + ,out_z_2 //|> o + ,out_z_3 //|> o + ); +input [16:0] inp_a_0; +input [16:0] inp_a_1; +input [16:0] inp_a_2; +input [16:0] inp_a_3; +input [16:0] inp_b_0; +input [16:0] inp_b_1; +input [16:0] inp_b_2; +input [16:0] inp_b_3; +input inp_in_pvld; +input inp_out_prdy; +input nvdla_core_rstn; +input nvdla_op_gated_clk_fp16; +output inp_in_prdy; +output inp_out_pvld; +output [16:0] out_z_0; +output [16:0] out_z_1; +output [16:0] out_z_2; +output [16:0] out_z_3; +wire [3:0] inp_a_rdy; +wire [3:0] inp_a_vld; +wire [3:0] inp_b_rdy; +wire [3:0] inp_b_vld; +wire [3:0] out_z_rdy; +wire [3:0] out_z_vld; +///////////////////////////////////////////// +assign inp_in_prdy = (&inp_a_rdy) & (&inp_b_rdy); +assign inp_a_vld[0] = inp_in_pvld & (&inp_a_rdy[3:1]) & (&inp_b_rdy[3:0]); +assign inp_a_vld[1] = inp_in_pvld & (&{inp_a_rdy[3:2],inp_a_rdy[0]}) & (&inp_b_rdy[3:0]); +assign inp_a_vld[2] = inp_in_pvld & (&{inp_a_rdy[3],inp_a_rdy[1:0]}) & (&inp_b_rdy[3:0]); +assign inp_a_vld[3] = inp_in_pvld & (&inp_a_rdy[2:0]) & (&inp_b_rdy[3:0]); +assign inp_b_vld[0] = inp_in_pvld & (&inp_b_rdy[3:1]) & (&inp_a_rdy[3:0]); +assign inp_b_vld[1] = inp_in_pvld & (&{inp_b_rdy[3:2],inp_b_rdy[0]}) & (&inp_a_rdy[3:0]); +assign inp_b_vld[2] = inp_in_pvld & (&{inp_b_rdy[3],inp_b_rdy[1:0]}) & (&inp_a_rdy[3:0]); +assign inp_b_vld[3] = inp_in_pvld & (&inp_b_rdy[2:0]) & (&inp_a_rdy[3:0]); +HLS_fp17_add u_cal1d_pool_sum_0 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_0[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[0]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[0]) //|> w + ,.chn_b_rsc_z (inp_b_0[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[0]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[0]) //|> w + ,.chn_o_rsc_z (out_z_0[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[0]) //|< w + ,.chn_o_rsc_lz (out_z_vld[0]) //|> w + ); +HLS_fp17_add u_cal1d_pool_sum_1 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_1[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[1]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[1]) //|> w + ,.chn_b_rsc_z (inp_b_1[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[1]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[1]) //|> w + ,.chn_o_rsc_z (out_z_1[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[1]) //|< w + ,.chn_o_rsc_lz (out_z_vld[1]) //|> w + ); +HLS_fp17_add u_cal1d_pool_sum_2 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_2[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[2]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[2]) //|> w + ,.chn_b_rsc_z (inp_b_2[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[2]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[2]) //|> w + ,.chn_o_rsc_z (out_z_2[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[2]) //|< w + ,.chn_o_rsc_lz (out_z_vld[2]) //|> w + ); +HLS_fp17_add u_cal1d_pool_sum_3 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_3[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[3]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[3]) //|> w + ,.chn_b_rsc_z (inp_b_3[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[3]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[3]) //|> w + ,.chn_o_rsc_z (out_z_3[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[3]) //|< w + ,.chn_o_rsc_lz (out_z_vld[3]) //|> w + ); +assign inp_out_pvld = &out_z_vld; +assign out_z_rdy[0] = inp_out_prdy & (&out_z_vld[3:1]); +assign out_z_rdy[1] = inp_out_prdy & (&out_z_vld[3:2] & out_z_vld[0]); +assign out_z_rdy[2] = inp_out_prdy & (out_z_vld[3] & (&out_z_vld[1:0])); +assign out_z_rdy[3] = inp_out_prdy & (&out_z_vld[2:0]); +//&Instance fp17_add u_cal1d_pool_sum_0; +// &Connect inp_a inp_a_0; +// &Connect inp_b inp_b_0; +// &Connect out_status out_status_0; +// &Connect out_z out_z_0; +// +//&Instance fp17_add u_cal1d_pool_sum_1; +// &Connect inp_a inp_a_1; +// &Connect inp_b inp_b_1; +// &Connect out_status out_status_1; +// &Connect out_z out_z_1; +// +//&Instance fp17_add u_cal1d_pool_sum_2; +// &Connect inp_a inp_a_2; +// &Connect inp_b inp_b_2; +// &Connect out_status out_status_2; +// &Connect out_z out_z_2; +// +//&Instance fp17_add u_cal1d_pool_sum_3; +// &Connect inp_a inp_a_3; +// &Connect inp_b inp_b_3; +// &Connect out_status out_status_3; +// &Connect out_z out_z_3; +endmodule // cal1d_fp16_pool_sum diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v.vcp new file mode 100644 index 0000000..81d2f54 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v.vcp @@ -0,0 +1,143 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: cal1d_fp16_pool_sum.v +module cal1d_fp16_pool_sum ( + inp_a_0 //|< i + ,inp_a_1 //|< i + ,inp_a_2 //|< i + ,inp_a_3 //|< i + ,inp_b_0 //|< i + ,inp_b_1 //|< i + ,inp_b_2 //|< i + ,inp_b_3 //|< i + ,inp_in_pvld //|< i + ,inp_out_prdy //|< i + ,nvdla_core_rstn //|< i + ,nvdla_op_gated_clk_fp16 //|< i + ,inp_in_prdy //|> o + ,inp_out_pvld //|> o + ,out_z_0 //|> o + ,out_z_1 //|> o + ,out_z_2 //|> o + ,out_z_3 //|> o + ); +input [16:0] inp_a_0; +input [16:0] inp_a_1; +input [16:0] inp_a_2; +input [16:0] inp_a_3; +input [16:0] inp_b_0; +input [16:0] inp_b_1; +input [16:0] inp_b_2; +input [16:0] inp_b_3; +input inp_in_pvld; +input inp_out_prdy; +input nvdla_core_rstn; +input nvdla_op_gated_clk_fp16; +output inp_in_prdy; +output inp_out_pvld; +output [16:0] out_z_0; +output [16:0] out_z_1; +output [16:0] out_z_2; +output [16:0] out_z_3; +wire [3:0] inp_a_rdy; +wire [3:0] inp_a_vld; +wire [3:0] inp_b_rdy; +wire [3:0] inp_b_vld; +wire [3:0] out_z_rdy; +wire [3:0] out_z_vld; +///////////////////////////////////////////// +assign inp_in_prdy = (&inp_a_rdy) & (&inp_b_rdy); +assign inp_a_vld[0] = inp_in_pvld & (&inp_a_rdy[3:1]) & (&inp_b_rdy[3:0]); +assign inp_a_vld[1] = inp_in_pvld & (&{inp_a_rdy[3:2],inp_a_rdy[0]}) & (&inp_b_rdy[3:0]); +assign inp_a_vld[2] = inp_in_pvld & (&{inp_a_rdy[3],inp_a_rdy[1:0]}) & (&inp_b_rdy[3:0]); +assign inp_a_vld[3] = inp_in_pvld & (&inp_a_rdy[2:0]) & (&inp_b_rdy[3:0]); +assign inp_b_vld[0] = inp_in_pvld & (&inp_b_rdy[3:1]) & (&inp_a_rdy[3:0]); +assign inp_b_vld[1] = inp_in_pvld & (&{inp_b_rdy[3:2],inp_b_rdy[0]}) & (&inp_a_rdy[3:0]); +assign inp_b_vld[2] = inp_in_pvld & (&{inp_b_rdy[3],inp_b_rdy[1:0]}) & (&inp_a_rdy[3:0]); +assign inp_b_vld[3] = inp_in_pvld & (&inp_b_rdy[2:0]) & (&inp_a_rdy[3:0]); +HLS_fp17_add u_cal1d_pool_sum_0 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_0[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[0]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[0]) //|> w + ,.chn_b_rsc_z (inp_b_0[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[0]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[0]) //|> w + ,.chn_o_rsc_z (out_z_0[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[0]) //|< w + ,.chn_o_rsc_lz (out_z_vld[0]) //|> w + ); +HLS_fp17_add u_cal1d_pool_sum_1 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_1[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[1]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[1]) //|> w + ,.chn_b_rsc_z (inp_b_1[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[1]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[1]) //|> w + ,.chn_o_rsc_z (out_z_1[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[1]) //|< w + ,.chn_o_rsc_lz (out_z_vld[1]) //|> w + ); +HLS_fp17_add u_cal1d_pool_sum_2 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_2[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[2]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[2]) //|> w + ,.chn_b_rsc_z (inp_b_2[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[2]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[2]) //|> w + ,.chn_o_rsc_z (out_z_2[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[2]) //|< w + ,.chn_o_rsc_lz (out_z_vld[2]) //|> w + ); +HLS_fp17_add u_cal1d_pool_sum_3 ( + .nvdla_core_clk (nvdla_op_gated_clk_fp16) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (inp_a_3[16:0]) //|< i + ,.chn_a_rsc_vz (inp_a_vld[3]) //|< w + ,.chn_a_rsc_lz (inp_a_rdy[3]) //|> w + ,.chn_b_rsc_z (inp_b_3[16:0]) //|< i + ,.chn_b_rsc_vz (inp_b_vld[3]) //|< w + ,.chn_b_rsc_lz (inp_b_rdy[3]) //|> w + ,.chn_o_rsc_z (out_z_3[16:0]) //|> o + ,.chn_o_rsc_vz (out_z_rdy[3]) //|< w + ,.chn_o_rsc_lz (out_z_vld[3]) //|> w + ); +assign inp_out_pvld = &out_z_vld; +assign out_z_rdy[0] = inp_out_prdy & (&out_z_vld[3:1]); +assign out_z_rdy[1] = inp_out_prdy & (&out_z_vld[3:2] & out_z_vld[0]); +assign out_z_rdy[2] = inp_out_prdy & (out_z_vld[3] & (&out_z_vld[1:0])); +assign out_z_rdy[3] = inp_out_prdy & (&out_z_vld[2:0]); +//&Instance fp17_add u_cal1d_pool_sum_0; +// &Connect inp_a inp_a_0; +// &Connect inp_b inp_b_0; +// &Connect out_status out_status_0; +// &Connect out_z out_z_0; +// +//&Instance fp17_add u_cal1d_pool_sum_1; +// &Connect inp_a inp_a_1; +// &Connect inp_b inp_b_1; +// &Connect out_status out_status_1; +// &Connect out_z out_z_1; +// +//&Instance fp17_add u_cal1d_pool_sum_2; +// &Connect inp_a inp_a_2; +// &Connect inp_b inp_b_2; +// &Connect out_status out_status_2; +// &Connect out_z out_z_2; +// +//&Instance fp17_add u_cal1d_pool_sum_3; +// &Connect inp_a inp_a_3; +// &Connect inp_b inp_b_3; +// &Connect out_status out_status_3; +// &Connect out_z out_z_3; +endmodule // cal1d_fp16_pool_sum diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/fp16_4add.v b/designs/src/NVDLA/vmod/nvdla/pdp/fp16_4add.v new file mode 100644 index 0000000..eb62424 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/fp16_4add.v @@ -0,0 +1,126 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: fp16_4add.v +module fp16_4add ( + fp16_add_in_a //|< i + ,fp16_add_in_b //|< i + ,fp16_add_in_pvld //|< i + ,fp16_add_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,fp16_add_in_prdy //|> o + ,fp16_add_out_dp //|> o + ,fp16_add_out_pvld //|> o + ); +input [67:0] fp16_add_in_a; +input [67:0] fp16_add_in_b; +input fp16_add_in_pvld; +input fp16_add_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output fp16_add_in_prdy; +output [67:0] fp16_add_out_dp; +output fp16_add_out_pvld; +wire fp16_add_in0_a_rdy; +wire fp16_add_in0_a_vld; +wire fp16_add_in0_b_rdy; +wire fp16_add_in0_b_vld; +wire fp16_add_in1_a_rdy; +wire fp16_add_in1_a_vld; +wire fp16_add_in1_b_rdy; +wire fp16_add_in1_b_vld; +wire fp16_add_in2_a_rdy; +wire fp16_add_in2_a_vld; +wire fp16_add_in2_b_rdy; +wire fp16_add_in2_b_vld; +wire fp16_add_in3_a_rdy; +wire fp16_add_in3_a_vld; +wire fp16_add_in3_b_rdy; +wire fp16_add_in3_b_vld; +wire [16:0] fp16_add_out0; +wire fp16_add_out0_rdy; +wire fp16_add_out0_vld; +wire [16:0] fp16_add_out1; +wire fp16_add_out1_rdy; +wire fp16_add_out1_vld; +wire [16:0] fp16_add_out2; +wire fp16_add_out2_rdy; +wire fp16_add_out2_vld; +wire [16:0] fp16_add_out3; +wire fp16_add_out3_rdy; +wire fp16_add_out3_vld; +///////////////////////////////////////////// +assign fp16_add_in_prdy = fp16_add_in3_b_rdy & fp16_add_in2_b_rdy & fp16_add_in1_b_rdy & fp16_add_in0_b_rdy + & fp16_add_in3_a_rdy & fp16_add_in2_a_rdy & fp16_add_in1_a_rdy & fp16_add_in0_a_rdy ; +assign fp16_add_in0_a_vld = fp16_add_in_pvld & (fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in1_a_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in2_a_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in3_a_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in0_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in1_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in2_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in3_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy); +HLS_fp17_add u_HLS_fp17_pooling_add_0 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[16:0]) //|< i + ,.chn_a_rsc_vz (fp16_add_in0_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in0_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[16:0]) //|< i + ,.chn_b_rsc_vz (fp16_add_in0_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in0_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out0[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out0_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out0_vld) //|> w + ); +HLS_fp17_add u_HLS_fp17_pooling_add_1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[33:17]) //|< i + ,.chn_a_rsc_vz (fp16_add_in1_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in1_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[33:17]) //|< i + ,.chn_b_rsc_vz (fp16_add_in1_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in1_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out1[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out1_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out1_vld) //|> w + ); +HLS_fp17_add u_HLS_fp17_pooling_add_2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[50:34]) //|< i + ,.chn_a_rsc_vz (fp16_add_in2_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in2_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[50:34]) //|< i + ,.chn_b_rsc_vz (fp16_add_in2_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in2_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out2[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out2_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out2_vld) //|> w + ); +HLS_fp17_add u_HLS_fp17_pooling_add_3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[67:51]) //|< i + ,.chn_a_rsc_vz (fp16_add_in3_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in3_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[67:51]) //|< i + ,.chn_b_rsc_vz (fp16_add_in3_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in3_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out3[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out3_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out3_vld) //|> w + ); +assign fp16_add_out0_rdy = fp16_add_out_prdy & (fp16_add_out3_vld & fp16_add_out2_vld & fp16_add_out1_vld); +assign fp16_add_out1_rdy = fp16_add_out_prdy & (fp16_add_out3_vld & fp16_add_out2_vld & fp16_add_out0_vld); +assign fp16_add_out2_rdy = fp16_add_out_prdy & (fp16_add_out3_vld & fp16_add_out1_vld & fp16_add_out0_vld); +assign fp16_add_out3_rdy = fp16_add_out_prdy & (fp16_add_out2_vld & fp16_add_out1_vld & fp16_add_out0_vld); +assign fp16_add_out_pvld = fp16_add_out3_vld & fp16_add_out2_vld & fp16_add_out1_vld & fp16_add_out0_vld; +assign fp16_add_out_dp = {fp16_add_out3,fp16_add_out2,fp16_add_out1,fp16_add_out0}; +endmodule // fp16_4add diff --git a/designs/src/NVDLA/vmod/nvdla/pdp/fp16_4add.v.vcp b/designs/src/NVDLA/vmod/nvdla/pdp/fp16_4add.v.vcp new file mode 100644 index 0000000..eb62424 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/pdp/fp16_4add.v.vcp @@ -0,0 +1,126 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: fp16_4add.v +module fp16_4add ( + fp16_add_in_a //|< i + ,fp16_add_in_b //|< i + ,fp16_add_in_pvld //|< i + ,fp16_add_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,fp16_add_in_prdy //|> o + ,fp16_add_out_dp //|> o + ,fp16_add_out_pvld //|> o + ); +input [67:0] fp16_add_in_a; +input [67:0] fp16_add_in_b; +input fp16_add_in_pvld; +input fp16_add_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output fp16_add_in_prdy; +output [67:0] fp16_add_out_dp; +output fp16_add_out_pvld; +wire fp16_add_in0_a_rdy; +wire fp16_add_in0_a_vld; +wire fp16_add_in0_b_rdy; +wire fp16_add_in0_b_vld; +wire fp16_add_in1_a_rdy; +wire fp16_add_in1_a_vld; +wire fp16_add_in1_b_rdy; +wire fp16_add_in1_b_vld; +wire fp16_add_in2_a_rdy; +wire fp16_add_in2_a_vld; +wire fp16_add_in2_b_rdy; +wire fp16_add_in2_b_vld; +wire fp16_add_in3_a_rdy; +wire fp16_add_in3_a_vld; +wire fp16_add_in3_b_rdy; +wire fp16_add_in3_b_vld; +wire [16:0] fp16_add_out0; +wire fp16_add_out0_rdy; +wire fp16_add_out0_vld; +wire [16:0] fp16_add_out1; +wire fp16_add_out1_rdy; +wire fp16_add_out1_vld; +wire [16:0] fp16_add_out2; +wire fp16_add_out2_rdy; +wire fp16_add_out2_vld; +wire [16:0] fp16_add_out3; +wire fp16_add_out3_rdy; +wire fp16_add_out3_vld; +///////////////////////////////////////////// +assign fp16_add_in_prdy = fp16_add_in3_b_rdy & fp16_add_in2_b_rdy & fp16_add_in1_b_rdy & fp16_add_in0_b_rdy + & fp16_add_in3_a_rdy & fp16_add_in2_a_rdy & fp16_add_in1_a_rdy & fp16_add_in0_a_rdy ; +assign fp16_add_in0_a_vld = fp16_add_in_pvld & (fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in1_a_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in2_a_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in3_a_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in0_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in1_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in2_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in3_a_rdy&fp16_add_in3_b_rdy); +assign fp16_add_in3_b_vld = fp16_add_in_pvld & (fp16_add_in0_a_rdy&fp16_add_in0_b_rdy&fp16_add_in1_a_rdy&fp16_add_in1_b_rdy&fp16_add_in2_a_rdy&fp16_add_in2_b_rdy&fp16_add_in3_a_rdy); +HLS_fp17_add u_HLS_fp17_pooling_add_0 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[16:0]) //|< i + ,.chn_a_rsc_vz (fp16_add_in0_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in0_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[16:0]) //|< i + ,.chn_b_rsc_vz (fp16_add_in0_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in0_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out0[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out0_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out0_vld) //|> w + ); +HLS_fp17_add u_HLS_fp17_pooling_add_1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[33:17]) //|< i + ,.chn_a_rsc_vz (fp16_add_in1_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in1_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[33:17]) //|< i + ,.chn_b_rsc_vz (fp16_add_in1_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in1_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out1[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out1_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out1_vld) //|> w + ); +HLS_fp17_add u_HLS_fp17_pooling_add_2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[50:34]) //|< i + ,.chn_a_rsc_vz (fp16_add_in2_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in2_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[50:34]) //|< i + ,.chn_b_rsc_vz (fp16_add_in2_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in2_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out2[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out2_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out2_vld) //|> w + ); +HLS_fp17_add u_HLS_fp17_pooling_add_3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_a_rsc_z (fp16_add_in_a[67:51]) //|< i + ,.chn_a_rsc_vz (fp16_add_in3_a_vld) //|< w + ,.chn_a_rsc_lz (fp16_add_in3_a_rdy) //|> w + ,.chn_b_rsc_z (fp16_add_in_b[67:51]) //|< i + ,.chn_b_rsc_vz (fp16_add_in3_b_vld) //|< w + ,.chn_b_rsc_lz (fp16_add_in3_b_rdy) //|> w + ,.chn_o_rsc_z (fp16_add_out3[16:0]) //|> w + ,.chn_o_rsc_vz (fp16_add_out3_rdy) //|< w + ,.chn_o_rsc_lz (fp16_add_out3_vld) //|> w + ); +assign fp16_add_out0_rdy = fp16_add_out_prdy & (fp16_add_out3_vld & fp16_add_out2_vld & fp16_add_out1_vld); +assign fp16_add_out1_rdy = fp16_add_out_prdy & (fp16_add_out3_vld & fp16_add_out2_vld & fp16_add_out0_vld); +assign fp16_add_out2_rdy = fp16_add_out_prdy & (fp16_add_out3_vld & fp16_add_out1_vld & fp16_add_out0_vld); +assign fp16_add_out3_rdy = fp16_add_out_prdy & (fp16_add_out2_vld & fp16_add_out1_vld & fp16_add_out0_vld); +assign fp16_add_out_pvld = fp16_add_out3_vld & fp16_add_out2_vld & fp16_add_out1_vld & fp16_add_out0_vld; +assign fp16_add_out_dp = {fp16_add_out3,fp16_add_out2,fp16_add_out1,fp16_add_out0}; +endmodule // fp16_4add diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v new file mode 100644 index 0000000..ff98915 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v @@ -0,0 +1,41 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_cacc2glb.v +module NV_NVDLA_RT_cacc2glb ( + nvdla_core_clk + ,nvdla_core_rstn + ,cacc2glb_done_intr_src_pd + ,cacc2glb_done_intr_dst_pd + ); +// +// NV_NVDLA_RT_cacc2glb_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] cacc2glb_done_intr_src_pd; +output [1:0] cacc2glb_done_intr_dst_pd; +wire [1:0] cacc2glb_done_intr_pd_d0; +reg [1:0] cacc2glb_done_intr_pd_d1; +reg [1:0] cacc2glb_done_intr_pd_d2; +assign cacc2glb_done_intr_pd_d0 = cacc2glb_done_intr_src_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2glb_done_intr_pd_d1 <= {2{1'b0}}; + end else begin + cacc2glb_done_intr_pd_d1 <= cacc2glb_done_intr_pd_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2glb_done_intr_pd_d2 <= {2{1'b0}}; + end else begin + cacc2glb_done_intr_pd_d2 <= cacc2glb_done_intr_pd_d1; + end +end +assign cacc2glb_done_intr_dst_pd = cacc2glb_done_intr_pd_d2; +endmodule // NV_NVDLA_RT_cacc2glb diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v.vcp new file mode 100644 index 0000000..ff98915 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v.vcp @@ -0,0 +1,41 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_cacc2glb.v +module NV_NVDLA_RT_cacc2glb ( + nvdla_core_clk + ,nvdla_core_rstn + ,cacc2glb_done_intr_src_pd + ,cacc2glb_done_intr_dst_pd + ); +// +// NV_NVDLA_RT_cacc2glb_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] cacc2glb_done_intr_src_pd; +output [1:0] cacc2glb_done_intr_dst_pd; +wire [1:0] cacc2glb_done_intr_pd_d0; +reg [1:0] cacc2glb_done_intr_pd_d1; +reg [1:0] cacc2glb_done_intr_pd_d2; +assign cacc2glb_done_intr_pd_d0 = cacc2glb_done_intr_src_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2glb_done_intr_pd_d1 <= {2{1'b0}}; + end else begin + cacc2glb_done_intr_pd_d1 <= cacc2glb_done_intr_pd_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2glb_done_intr_pd_d2 <= {2{1'b0}}; + end else begin + cacc2glb_done_intr_pd_d2 <= cacc2glb_done_intr_pd_d1; + end +end +assign cacc2glb_done_intr_dst_pd = cacc2glb_done_intr_pd_d2; +endmodule // NV_NVDLA_RT_cacc2glb diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v new file mode 100644 index 0000000..d682e16 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v @@ -0,0 +1,344 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_cmac_a2cacc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_RT_cmac_a2cacc ( + nvdla_core_clk + ,nvdla_core_rstn + ,mac2accu_src_pvld + ,mac2accu_src_mask + ,mac2accu_src_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_src_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_src_data0 +,mac2accu_src_data1 +,mac2accu_src_data2 +,mac2accu_src_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_src_pd + ,mac2accu_dst_pvld + ,mac2accu_dst_mask + ,mac2accu_dst_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_dst_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_dst_data0 +,mac2accu_dst_data1 +,mac2accu_dst_data2 +,mac2accu_dst_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_dst_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mac2accu_src_pvld; /* data valid */ +input [8/2 -1:0] mac2accu_src_mask; +input mac2accu_src_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: input [19 -1:0] mac2accu_src_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac2accu_src_data0; +input [19 -1:0] mac2accu_src_data1; +input [19 -1:0] mac2accu_src_data2; +input [19 -1:0] mac2accu_src_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] mac2accu_src_pd; +output mac2accu_dst_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_dst_mask; +output mac2accu_dst_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_dst_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [19 -1:0] mac2accu_dst_data0; +output [19 -1:0] mac2accu_dst_data1; +output [19 -1:0] mac2accu_dst_data2; +output [19 -1:0] mac2accu_dst_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] mac2accu_dst_pd; +wire mac2accu_pvld_d0 = mac2accu_src_pvld; +wire [8:0] mac2accu_pd_d0 = mac2accu_src_pd; +wire [8/2 -1:0] mac2accu_mask_d0 = mac2accu_src_mask; +wire mac2accu_mode_d0 = mac2accu_src_mode; +//: my $delay = 2; +//: my $i; +//: my $j; +//: my $k; +//: my $kk=8/2; +//: my $jj=19; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_data${k}_d0 = mac2accu_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q mac2accu_pvld_d${j} -d mac2accu_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q mac2accu_pd_d${j} -en mac2accu_pvld_d${i} -d mac2accu_pd_d${i}"); +//: &eperl::flop("-q mac2accu_mode_d${j} -en mac2accu_pvld_d${i} -d mac2accu_mode_d${i}"); +//: &eperl::flop("-wid ${kk} -q mac2accu_mask_d${j} -d mac2accu_mask_d${i}"); +//: for($k = 0; $k < 8/2; $k ++) { +//: &eperl::flop("-wid ${jj} -q mac2accu_data${k}_d${j} -en mac2accu_mask_d${i}[${k}] -d mac2accu_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "assign mac2accu_dst_pvld = mac2accu_pvld_d${i};\n"; +//: print "assign mac2accu_dst_pd = mac2accu_pd_d${i};\n"; +//: print "assign mac2accu_dst_mask = mac2accu_mask_d${i};\n"; +//: print "assign mac2accu_dst_mode = mac2accu_mode_d${i};\n"; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_dst_data${k} = mac2accu_data${k}_d${i};\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign mac2accu_data0_d0 = mac2accu_src_data0; +assign mac2accu_data1_d0 = mac2accu_src_data1; +assign mac2accu_data2_d0 = mac2accu_src_data2; +assign mac2accu_data3_d0 = mac2accu_src_data3; +reg mac2accu_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pvld_d1 <= 'b0; + end else begin + mac2accu_pvld_d1 <= mac2accu_pvld_d0; + end +end +reg [8:0] mac2accu_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pd_d1 <= 'b0; + end else begin + if ((mac2accu_pvld_d0) == 1'b1) begin + mac2accu_pd_d1 <= mac2accu_pd_d0; + // VCS coverage off + end else if ((mac2accu_pvld_d0) == 1'b0) begin + end else begin + mac2accu_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_mode_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mode_d1 <= 'b0; + end else begin + if ((mac2accu_pvld_d0) == 1'b1) begin + mac2accu_mode_d1 <= mac2accu_mode_d0; + // VCS coverage off + end else if ((mac2accu_pvld_d0) == 1'b0) begin + end else begin + mac2accu_mode_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] mac2accu_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mask_d1 <= 'b0; + end else begin + mac2accu_mask_d1 <= mac2accu_mask_d0; + end +end +reg [18:0] mac2accu_data0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data0_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[0]) == 1'b1) begin + mac2accu_data0_d1 <= mac2accu_data0_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[0]) == 1'b0) begin + end else begin + mac2accu_data0_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data1_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[1]) == 1'b1) begin + mac2accu_data1_d1 <= mac2accu_data1_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[1]) == 1'b0) begin + end else begin + mac2accu_data1_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data2_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data2_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[2]) == 1'b1) begin + mac2accu_data2_d1 <= mac2accu_data2_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[2]) == 1'b0) begin + end else begin + mac2accu_data2_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data3_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data3_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[3]) == 1'b1) begin + mac2accu_data3_d1 <= mac2accu_data3_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[3]) == 1'b0) begin + end else begin + mac2accu_data3_d1 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pvld_d2 <= 'b0; + end else begin + mac2accu_pvld_d2 <= mac2accu_pvld_d1; + end +end +reg [8:0] mac2accu_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pd_d2 <= 'b0; + end else begin + if ((mac2accu_pvld_d1) == 1'b1) begin + mac2accu_pd_d2 <= mac2accu_pd_d1; + // VCS coverage off + end else if ((mac2accu_pvld_d1) == 1'b0) begin + end else begin + mac2accu_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_mode_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mode_d2 <= 'b0; + end else begin + if ((mac2accu_pvld_d1) == 1'b1) begin + mac2accu_mode_d2 <= mac2accu_mode_d1; + // VCS coverage off + end else if ((mac2accu_pvld_d1) == 1'b0) begin + end else begin + mac2accu_mode_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] mac2accu_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mask_d2 <= 'b0; + end else begin + mac2accu_mask_d2 <= mac2accu_mask_d1; + end +end +reg [18:0] mac2accu_data0_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data0_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[0]) == 1'b1) begin + mac2accu_data0_d2 <= mac2accu_data0_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[0]) == 1'b0) begin + end else begin + mac2accu_data0_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data1_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data1_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[1]) == 1'b1) begin + mac2accu_data1_d2 <= mac2accu_data1_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[1]) == 1'b0) begin + end else begin + mac2accu_data1_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data2_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data2_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[2]) == 1'b1) begin + mac2accu_data2_d2 <= mac2accu_data2_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[2]) == 1'b0) begin + end else begin + mac2accu_data2_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data3_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data3_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[3]) == 1'b1) begin + mac2accu_data3_d2 <= mac2accu_data3_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[3]) == 1'b0) begin + end else begin + mac2accu_data3_d2 <= 'bx; + // VCS coverage on + end + end +end +assign mac2accu_dst_pvld = mac2accu_pvld_d2; +assign mac2accu_dst_pd = mac2accu_pd_d2; +assign mac2accu_dst_mask = mac2accu_mask_d2; +assign mac2accu_dst_mode = mac2accu_mode_d2; +assign mac2accu_dst_data0 = mac2accu_data0_d2; +assign mac2accu_dst_data1 = mac2accu_data1_d2; +assign mac2accu_dst_data2 = mac2accu_data2_d2; +assign mac2accu_dst_data3 = mac2accu_data3_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v.vcp new file mode 100644 index 0000000..0dbc485 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v.vcp @@ -0,0 +1,89 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_cmac_a2cacc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_RT_cmac_a2cacc ( + nvdla_core_clk + ,nvdla_core_rstn + ,mac2accu_src_pvld + ,mac2accu_src_mask + ,mac2accu_src_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_src_data${i} ) +//: } + ,mac2accu_src_pd + ,mac2accu_dst_pvld + ,mac2accu_dst_mask + ,mac2accu_dst_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_dst_data${i} ) +//: } + ,mac2accu_dst_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mac2accu_src_pvld; /* data valid */ +input [8/2 -1:0] mac2accu_src_mask; +input mac2accu_src_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: input [19 -1:0] mac2accu_src_data${i}; ) +//: } +input [8:0] mac2accu_src_pd; +output mac2accu_dst_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_dst_mask; +output mac2accu_dst_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_dst_data${i}; ) +//: } +output [8:0] mac2accu_dst_pd; +wire mac2accu_pvld_d0 = mac2accu_src_pvld; +wire [8:0] mac2accu_pd_d0 = mac2accu_src_pd; +wire [8/2 -1:0] mac2accu_mask_d0 = mac2accu_src_mask; +wire mac2accu_mode_d0 = mac2accu_src_mode; +//: my $delay = 2; +//: my $i; +//: my $j; +//: my $k; +//: my $kk=8/2; +//: my $jj=19; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_data${k}_d0 = mac2accu_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q mac2accu_pvld_d${j} -d mac2accu_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q mac2accu_pd_d${j} -en mac2accu_pvld_d${i} -d mac2accu_pd_d${i}"); +//: &eperl::flop("-q mac2accu_mode_d${j} -en mac2accu_pvld_d${i} -d mac2accu_mode_d${i}"); +//: &eperl::flop("-wid ${kk} -q mac2accu_mask_d${j} -d mac2accu_mask_d${i}"); +//: for($k = 0; $k < 8/2; $k ++) { +//: &eperl::flop("-wid ${jj} -q mac2accu_data${k}_d${j} -en mac2accu_mask_d${i}[${k}] -d mac2accu_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "assign mac2accu_dst_pvld = mac2accu_pvld_d${i};\n"; +//: print "assign mac2accu_dst_pd = mac2accu_pd_d${i};\n"; +//: print "assign mac2accu_dst_mask = mac2accu_mask_d${i};\n"; +//: print "assign mac2accu_dst_mode = mac2accu_mode_d${i};\n"; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_dst_data${k} = mac2accu_data${k}_d${i};\n"; +//: } +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v new file mode 100644 index 0000000..665b54d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v @@ -0,0 +1,450 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_cmac_b2cacc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_RT_cmac_b2cacc ( + nvdla_core_clk + ,nvdla_core_rstn + ,mac2accu_src_pvld + ,mac2accu_src_mask + ,mac2accu_src_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_src_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_src_data0 +,mac2accu_src_data1 +,mac2accu_src_data2 +,mac2accu_src_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_src_pd + ,mac2accu_dst_pvld + ,mac2accu_dst_mask + ,mac2accu_dst_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_dst_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_dst_data0 +,mac2accu_dst_data1 +,mac2accu_dst_data2 +,mac2accu_dst_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_dst_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mac2accu_src_pvld; /* data valid */ +input [8/2 -1:0] mac2accu_src_mask; +input mac2accu_src_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: input [19 -1:0] mac2accu_src_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac2accu_src_data0; +input [19 -1:0] mac2accu_src_data1; +input [19 -1:0] mac2accu_src_data2; +input [19 -1:0] mac2accu_src_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] mac2accu_src_pd; +output mac2accu_dst_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_dst_mask; +output mac2accu_dst_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_dst_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [19 -1:0] mac2accu_dst_data0; +output [19 -1:0] mac2accu_dst_data1; +output [19 -1:0] mac2accu_dst_data2; +output [19 -1:0] mac2accu_dst_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] mac2accu_dst_pd; +wire mac2accu_pvld_d0 = mac2accu_src_pvld; +wire [8:0] mac2accu_pd_d0 = mac2accu_src_pd; +wire [8/2 -1:0] mac2accu_mask_d0 = mac2accu_src_mask; +wire mac2accu_mode_d0 = mac2accu_src_mode; +//: my $delay = 3; +//: my $i; +//: my $j; +//: my $k; +//: my $kk=8/2; +//: my $jj=19; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_data${k}_d0 = mac2accu_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q mac2accu_pvld_d${j} -d mac2accu_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q mac2accu_pd_d${j} -en mac2accu_pvld_d${i} -d mac2accu_pd_d${i}"); +//: &eperl::flop("-q mac2accu_mode_d${j} -en mac2accu_pvld_d${i} -d mac2accu_mode_d${i}"); +//: &eperl::flop("-wid ${kk} -q mac2accu_mask_d${j} -d mac2accu_mask_d${i}"); +//: for($k = 0; $k < 8/2; $k ++) { +//: &eperl::flop("-wid ${jj} -q mac2accu_data${k}_d${j} -en mac2accu_mask_d${i}[${k}] -d mac2accu_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "assign mac2accu_dst_pvld = mac2accu_pvld_d${i};\n"; +//: print "assign mac2accu_dst_pd = mac2accu_pd_d${i};\n"; +//: print "assign mac2accu_dst_mask = mac2accu_mask_d${i};\n"; +//: print "assign mac2accu_dst_mode = mac2accu_mode_d${i};\n"; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_dst_data${k} = mac2accu_data${k}_d${i};\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign mac2accu_data0_d0 = mac2accu_src_data0; +assign mac2accu_data1_d0 = mac2accu_src_data1; +assign mac2accu_data2_d0 = mac2accu_src_data2; +assign mac2accu_data3_d0 = mac2accu_src_data3; +reg mac2accu_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pvld_d1 <= 'b0; + end else begin + mac2accu_pvld_d1 <= mac2accu_pvld_d0; + end +end +reg [8:0] mac2accu_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pd_d1 <= 'b0; + end else begin + if ((mac2accu_pvld_d0) == 1'b1) begin + mac2accu_pd_d1 <= mac2accu_pd_d0; + // VCS coverage off + end else if ((mac2accu_pvld_d0) == 1'b0) begin + end else begin + mac2accu_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_mode_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mode_d1 <= 'b0; + end else begin + if ((mac2accu_pvld_d0) == 1'b1) begin + mac2accu_mode_d1 <= mac2accu_mode_d0; + // VCS coverage off + end else if ((mac2accu_pvld_d0) == 1'b0) begin + end else begin + mac2accu_mode_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] mac2accu_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mask_d1 <= 'b0; + end else begin + mac2accu_mask_d1 <= mac2accu_mask_d0; + end +end +reg [18:0] mac2accu_data0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data0_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[0]) == 1'b1) begin + mac2accu_data0_d1 <= mac2accu_data0_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[0]) == 1'b0) begin + end else begin + mac2accu_data0_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data1_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[1]) == 1'b1) begin + mac2accu_data1_d1 <= mac2accu_data1_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[1]) == 1'b0) begin + end else begin + mac2accu_data1_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data2_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data2_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[2]) == 1'b1) begin + mac2accu_data2_d1 <= mac2accu_data2_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[2]) == 1'b0) begin + end else begin + mac2accu_data2_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data3_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data3_d1 <= 'b0; + end else begin + if ((mac2accu_mask_d0[3]) == 1'b1) begin + mac2accu_data3_d1 <= mac2accu_data3_d0; + // VCS coverage off + end else if ((mac2accu_mask_d0[3]) == 1'b0) begin + end else begin + mac2accu_data3_d1 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pvld_d2 <= 'b0; + end else begin + mac2accu_pvld_d2 <= mac2accu_pvld_d1; + end +end +reg [8:0] mac2accu_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pd_d2 <= 'b0; + end else begin + if ((mac2accu_pvld_d1) == 1'b1) begin + mac2accu_pd_d2 <= mac2accu_pd_d1; + // VCS coverage off + end else if ((mac2accu_pvld_d1) == 1'b0) begin + end else begin + mac2accu_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_mode_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mode_d2 <= 'b0; + end else begin + if ((mac2accu_pvld_d1) == 1'b1) begin + mac2accu_mode_d2 <= mac2accu_mode_d1; + // VCS coverage off + end else if ((mac2accu_pvld_d1) == 1'b0) begin + end else begin + mac2accu_mode_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] mac2accu_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mask_d2 <= 'b0; + end else begin + mac2accu_mask_d2 <= mac2accu_mask_d1; + end +end +reg [18:0] mac2accu_data0_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data0_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[0]) == 1'b1) begin + mac2accu_data0_d2 <= mac2accu_data0_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[0]) == 1'b0) begin + end else begin + mac2accu_data0_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data1_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data1_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[1]) == 1'b1) begin + mac2accu_data1_d2 <= mac2accu_data1_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[1]) == 1'b0) begin + end else begin + mac2accu_data1_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data2_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data2_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[2]) == 1'b1) begin + mac2accu_data2_d2 <= mac2accu_data2_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[2]) == 1'b0) begin + end else begin + mac2accu_data2_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data3_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data3_d2 <= 'b0; + end else begin + if ((mac2accu_mask_d1[3]) == 1'b1) begin + mac2accu_data3_d2 <= mac2accu_data3_d1; + // VCS coverage off + end else if ((mac2accu_mask_d1[3]) == 1'b0) begin + end else begin + mac2accu_data3_d2 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_pvld_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pvld_d3 <= 'b0; + end else begin + mac2accu_pvld_d3 <= mac2accu_pvld_d2; + end +end +reg [8:0] mac2accu_pd_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_pd_d3 <= 'b0; + end else begin + if ((mac2accu_pvld_d2) == 1'b1) begin + mac2accu_pd_d3 <= mac2accu_pd_d2; + // VCS coverage off + end else if ((mac2accu_pvld_d2) == 1'b0) begin + end else begin + mac2accu_pd_d3 <= 'bx; + // VCS coverage on + end + end +end +reg mac2accu_mode_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mode_d3 <= 'b0; + end else begin + if ((mac2accu_pvld_d2) == 1'b1) begin + mac2accu_mode_d3 <= mac2accu_mode_d2; + // VCS coverage off + end else if ((mac2accu_pvld_d2) == 1'b0) begin + end else begin + mac2accu_mode_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [3:0] mac2accu_mask_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_mask_d3 <= 'b0; + end else begin + mac2accu_mask_d3 <= mac2accu_mask_d2; + end +end +reg [18:0] mac2accu_data0_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data0_d3 <= 'b0; + end else begin + if ((mac2accu_mask_d2[0]) == 1'b1) begin + mac2accu_data0_d3 <= mac2accu_data0_d2; + // VCS coverage off + end else if ((mac2accu_mask_d2[0]) == 1'b0) begin + end else begin + mac2accu_data0_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data1_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data1_d3 <= 'b0; + end else begin + if ((mac2accu_mask_d2[1]) == 1'b1) begin + mac2accu_data1_d3 <= mac2accu_data1_d2; + // VCS coverage off + end else if ((mac2accu_mask_d2[1]) == 1'b0) begin + end else begin + mac2accu_data1_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data2_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data2_d3 <= 'b0; + end else begin + if ((mac2accu_mask_d2[2]) == 1'b1) begin + mac2accu_data2_d3 <= mac2accu_data2_d2; + // VCS coverage off + end else if ((mac2accu_mask_d2[2]) == 1'b0) begin + end else begin + mac2accu_data2_d3 <= 'bx; + // VCS coverage on + end + end +end +reg [18:0] mac2accu_data3_d3; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mac2accu_data3_d3 <= 'b0; + end else begin + if ((mac2accu_mask_d2[3]) == 1'b1) begin + mac2accu_data3_d3 <= mac2accu_data3_d2; + // VCS coverage off + end else if ((mac2accu_mask_d2[3]) == 1'b0) begin + end else begin + mac2accu_data3_d3 <= 'bx; + // VCS coverage on + end + end +end +assign mac2accu_dst_pvld = mac2accu_pvld_d3; +assign mac2accu_dst_pd = mac2accu_pd_d3; +assign mac2accu_dst_mask = mac2accu_mask_d3; +assign mac2accu_dst_mode = mac2accu_mode_d3; +assign mac2accu_dst_data0 = mac2accu_data0_d3; +assign mac2accu_dst_data1 = mac2accu_data1_d3; +assign mac2accu_dst_data2 = mac2accu_data2_d3; +assign mac2accu_dst_data3 = mac2accu_data3_d3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v.vcp new file mode 100644 index 0000000..f47e6ec --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v.vcp @@ -0,0 +1,89 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_cmac_b2cacc.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_RT_cmac_b2cacc ( + nvdla_core_clk + ,nvdla_core_rstn + ,mac2accu_src_pvld + ,mac2accu_src_mask + ,mac2accu_src_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_src_data${i} ) +//: } + ,mac2accu_src_pd + ,mac2accu_dst_pvld + ,mac2accu_dst_mask + ,mac2accu_dst_mode +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: ,mac2accu_dst_data${i} ) +//: } + ,mac2accu_dst_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mac2accu_src_pvld; /* data valid */ +input [8/2 -1:0] mac2accu_src_mask; +input mac2accu_src_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: input [19 -1:0] mac2accu_src_data${i}; ) +//: } +input [8:0] mac2accu_src_pd; +output mac2accu_dst_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_dst_mask; +output mac2accu_dst_mode; +//: for(my $i=0; $i<8/2; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_dst_data${i}; ) +//: } +output [8:0] mac2accu_dst_pd; +wire mac2accu_pvld_d0 = mac2accu_src_pvld; +wire [8:0] mac2accu_pd_d0 = mac2accu_src_pd; +wire [8/2 -1:0] mac2accu_mask_d0 = mac2accu_src_mask; +wire mac2accu_mode_d0 = mac2accu_src_mode; +//: my $delay = 3; +//: my $i; +//: my $j; +//: my $k; +//: my $kk=8/2; +//: my $jj=19; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_data${k}_d0 = mac2accu_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q mac2accu_pvld_d${j} -d mac2accu_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q mac2accu_pd_d${j} -en mac2accu_pvld_d${i} -d mac2accu_pd_d${i}"); +//: &eperl::flop("-q mac2accu_mode_d${j} -en mac2accu_pvld_d${i} -d mac2accu_mode_d${i}"); +//: &eperl::flop("-wid ${kk} -q mac2accu_mask_d${j} -d mac2accu_mask_d${i}"); +//: for($k = 0; $k < 8/2; $k ++) { +//: &eperl::flop("-wid ${jj} -q mac2accu_data${k}_d${j} -en mac2accu_mask_d${i}[${k}] -d mac2accu_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "assign mac2accu_dst_pvld = mac2accu_pvld_d${i};\n"; +//: print "assign mac2accu_dst_pd = mac2accu_pd_d${i};\n"; +//: print "assign mac2accu_dst_mask = mac2accu_mask_d${i};\n"; +//: print "assign mac2accu_dst_mode = mac2accu_mode_d${i};\n"; +//: for($k = 0; $k <8/2; $k ++) { +//: print "assign mac2accu_dst_data${k} = mac2accu_data${k}_d${i};\n"; +//: } +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v new file mode 100644 index 0000000..d63902c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v @@ -0,0 +1,165 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csb2cacc.v +module NV_NVDLA_RT_csb2cacc ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2cacc_req_src_pvld + ,csb2cacc_req_src_prdy + ,csb2cacc_req_src_pd + ,cacc2csb_resp_src_valid + ,cacc2csb_resp_src_pd + ,csb2cacc_req_dst_pvld + ,csb2cacc_req_dst_prdy + ,csb2cacc_req_dst_pd + ,cacc2csb_resp_dst_valid + ,cacc2csb_resp_dst_pd + ); +// +// NV_NVDLA_RT_csb2cacc_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input csb2cacc_req_src_pvld; /* data valid */ +output csb2cacc_req_src_prdy; /* data return handshake */ +input [62:0] csb2cacc_req_src_pd; +input cacc2csb_resp_src_valid; /* data valid */ +input [33:0] cacc2csb_resp_src_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cacc_req_dst_pvld; /* data valid */ +input csb2cacc_req_dst_prdy; /* data return handshake */ +output [62:0] csb2cacc_req_dst_pd; +output cacc2csb_resp_dst_valid; /* data valid */ +output [33:0] cacc2csb_resp_dst_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +wire [33:0] cacc2csb_resp_pd_d0; +wire cacc2csb_resp_valid_d0; +wire [62:0] csb2cacc_req_pd_d0; +wire csb2cacc_req_pvld_d0; +reg [33:0] cacc2csb_resp_pd_d1; +reg [33:0] cacc2csb_resp_pd_d2; +reg [33:0] cacc2csb_resp_pd_d3; +reg cacc2csb_resp_valid_d1; +reg cacc2csb_resp_valid_d2; +reg cacc2csb_resp_valid_d3; +reg [62:0] csb2cacc_req_pd_d1; +reg [62:0] csb2cacc_req_pd_d2; +reg [62:0] csb2cacc_req_pd_d3; +reg csb2cacc_req_pvld_d1; +reg csb2cacc_req_pvld_d2; +reg csb2cacc_req_pvld_d3; +assign csb2cacc_req_src_prdy = 1'b1; +assign csb2cacc_req_pvld_d0 = csb2cacc_req_src_pvld; +assign csb2cacc_req_pd_d0 = csb2cacc_req_src_pd; +assign cacc2csb_resp_valid_d0 = cacc2csb_resp_src_valid; +assign cacc2csb_resp_pd_d0 = cacc2csb_resp_src_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld_d1 <= 1'b0; + end else begin + csb2cacc_req_pvld_d1 <= csb2cacc_req_pvld_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_pvld_d0) == 1'b1) begin + csb2cacc_req_pd_d1 <= csb2cacc_req_pd_d0; +// VCS coverage off + end else if ((csb2cacc_req_pvld_d0) == 1'b0) begin + end else begin + csb2cacc_req_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid_d1 <= 1'b0; + end else begin + cacc2csb_resp_valid_d1 <= cacc2csb_resp_valid_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid_d0) == 1'b1) begin + cacc2csb_resp_pd_d1 <= cacc2csb_resp_pd_d0; +// VCS coverage off + end else if ((cacc2csb_resp_valid_d0) == 1'b0) begin + end else begin + cacc2csb_resp_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld_d2 <= 1'b0; + end else begin + csb2cacc_req_pvld_d2 <= csb2cacc_req_pvld_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_pvld_d1) == 1'b1) begin + csb2cacc_req_pd_d2 <= csb2cacc_req_pd_d1; +// VCS coverage off + end else if ((csb2cacc_req_pvld_d1) == 1'b0) begin + end else begin + csb2cacc_req_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid_d2 <= 1'b0; + end else begin + cacc2csb_resp_valid_d2 <= cacc2csb_resp_valid_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid_d1) == 1'b1) begin + cacc2csb_resp_pd_d2 <= cacc2csb_resp_pd_d1; +// VCS coverage off + end else if ((cacc2csb_resp_valid_d1) == 1'b0) begin + end else begin + cacc2csb_resp_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld_d3 <= 1'b0; + end else begin + csb2cacc_req_pvld_d3 <= csb2cacc_req_pvld_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_pvld_d2) == 1'b1) begin + csb2cacc_req_pd_d3 <= csb2cacc_req_pd_d2; +// VCS coverage off + end else if ((csb2cacc_req_pvld_d2) == 1'b0) begin + end else begin + csb2cacc_req_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid_d3 <= 1'b0; + end else begin + cacc2csb_resp_valid_d3 <= cacc2csb_resp_valid_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid_d2) == 1'b1) begin + cacc2csb_resp_pd_d3 <= cacc2csb_resp_pd_d2; +// VCS coverage off + end else if ((cacc2csb_resp_valid_d2) == 1'b0) begin + end else begin + cacc2csb_resp_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2cacc_req_dst_pvld = csb2cacc_req_pvld_d3; +assign csb2cacc_req_dst_pd = csb2cacc_req_pd_d3; +assign cacc2csb_resp_dst_valid = cacc2csb_resp_valid_d3; +assign cacc2csb_resp_dst_pd = cacc2csb_resp_pd_d3; +endmodule // NV_NVDLA_RT_csb2cacc diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v.vcp new file mode 100644 index 0000000..d63902c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v.vcp @@ -0,0 +1,165 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csb2cacc.v +module NV_NVDLA_RT_csb2cacc ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2cacc_req_src_pvld + ,csb2cacc_req_src_prdy + ,csb2cacc_req_src_pd + ,cacc2csb_resp_src_valid + ,cacc2csb_resp_src_pd + ,csb2cacc_req_dst_pvld + ,csb2cacc_req_dst_prdy + ,csb2cacc_req_dst_pd + ,cacc2csb_resp_dst_valid + ,cacc2csb_resp_dst_pd + ); +// +// NV_NVDLA_RT_csb2cacc_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input csb2cacc_req_src_pvld; /* data valid */ +output csb2cacc_req_src_prdy; /* data return handshake */ +input [62:0] csb2cacc_req_src_pd; +input cacc2csb_resp_src_valid; /* data valid */ +input [33:0] cacc2csb_resp_src_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cacc_req_dst_pvld; /* data valid */ +input csb2cacc_req_dst_prdy; /* data return handshake */ +output [62:0] csb2cacc_req_dst_pd; +output cacc2csb_resp_dst_valid; /* data valid */ +output [33:0] cacc2csb_resp_dst_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +wire [33:0] cacc2csb_resp_pd_d0; +wire cacc2csb_resp_valid_d0; +wire [62:0] csb2cacc_req_pd_d0; +wire csb2cacc_req_pvld_d0; +reg [33:0] cacc2csb_resp_pd_d1; +reg [33:0] cacc2csb_resp_pd_d2; +reg [33:0] cacc2csb_resp_pd_d3; +reg cacc2csb_resp_valid_d1; +reg cacc2csb_resp_valid_d2; +reg cacc2csb_resp_valid_d3; +reg [62:0] csb2cacc_req_pd_d1; +reg [62:0] csb2cacc_req_pd_d2; +reg [62:0] csb2cacc_req_pd_d3; +reg csb2cacc_req_pvld_d1; +reg csb2cacc_req_pvld_d2; +reg csb2cacc_req_pvld_d3; +assign csb2cacc_req_src_prdy = 1'b1; +assign csb2cacc_req_pvld_d0 = csb2cacc_req_src_pvld; +assign csb2cacc_req_pd_d0 = csb2cacc_req_src_pd; +assign cacc2csb_resp_valid_d0 = cacc2csb_resp_src_valid; +assign cacc2csb_resp_pd_d0 = cacc2csb_resp_src_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld_d1 <= 1'b0; + end else begin + csb2cacc_req_pvld_d1 <= csb2cacc_req_pvld_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_pvld_d0) == 1'b1) begin + csb2cacc_req_pd_d1 <= csb2cacc_req_pd_d0; +// VCS coverage off + end else if ((csb2cacc_req_pvld_d0) == 1'b0) begin + end else begin + csb2cacc_req_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid_d1 <= 1'b0; + end else begin + cacc2csb_resp_valid_d1 <= cacc2csb_resp_valid_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid_d0) == 1'b1) begin + cacc2csb_resp_pd_d1 <= cacc2csb_resp_pd_d0; +// VCS coverage off + end else if ((cacc2csb_resp_valid_d0) == 1'b0) begin + end else begin + cacc2csb_resp_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld_d2 <= 1'b0; + end else begin + csb2cacc_req_pvld_d2 <= csb2cacc_req_pvld_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_pvld_d1) == 1'b1) begin + csb2cacc_req_pd_d2 <= csb2cacc_req_pd_d1; +// VCS coverage off + end else if ((csb2cacc_req_pvld_d1) == 1'b0) begin + end else begin + csb2cacc_req_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid_d2 <= 1'b0; + end else begin + cacc2csb_resp_valid_d2 <= cacc2csb_resp_valid_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid_d1) == 1'b1) begin + cacc2csb_resp_pd_d2 <= cacc2csb_resp_pd_d1; +// VCS coverage off + end else if ((cacc2csb_resp_valid_d1) == 1'b0) begin + end else begin + cacc2csb_resp_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cacc_req_pvld_d3 <= 1'b0; + end else begin + csb2cacc_req_pvld_d3 <= csb2cacc_req_pvld_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cacc_req_pvld_d2) == 1'b1) begin + csb2cacc_req_pd_d3 <= csb2cacc_req_pd_d2; +// VCS coverage off + end else if ((csb2cacc_req_pvld_d2) == 1'b0) begin + end else begin + csb2cacc_req_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2csb_resp_valid_d3 <= 1'b0; + end else begin + cacc2csb_resp_valid_d3 <= cacc2csb_resp_valid_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((cacc2csb_resp_valid_d2) == 1'b1) begin + cacc2csb_resp_pd_d3 <= cacc2csb_resp_pd_d2; +// VCS coverage off + end else if ((cacc2csb_resp_valid_d2) == 1'b0) begin + end else begin + cacc2csb_resp_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2cacc_req_dst_pvld = csb2cacc_req_pvld_d3; +assign csb2cacc_req_dst_pd = csb2cacc_req_pd_d3; +assign cacc2csb_resp_dst_valid = cacc2csb_resp_valid_d3; +assign cacc2csb_resp_dst_pd = cacc2csb_resp_pd_d3; +endmodule // NV_NVDLA_RT_csb2cacc diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v new file mode 100644 index 0000000..a1a7999 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v @@ -0,0 +1,165 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csb2cmac.v +module NV_NVDLA_RT_csb2cmac ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2cmac_req_src_pvld + ,csb2cmac_req_src_prdy + ,csb2cmac_req_src_pd + ,cmac2csb_resp_src_valid + ,cmac2csb_resp_src_pd + ,csb2cmac_req_dst_pvld + ,csb2cmac_req_dst_prdy + ,csb2cmac_req_dst_pd + ,cmac2csb_resp_dst_valid + ,cmac2csb_resp_dst_pd + ); +// +// NV_NVDLA_RT_csb2cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input csb2cmac_req_src_pvld; /* data valid */ +output csb2cmac_req_src_prdy; /* data return handshake */ +input [62:0] csb2cmac_req_src_pd; +input cmac2csb_resp_src_valid; /* data valid */ +input [33:0] cmac2csb_resp_src_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_req_dst_pvld; /* data valid */ +input csb2cmac_req_dst_prdy; /* data return handshake */ +output [62:0] csb2cmac_req_dst_pd; +output cmac2csb_resp_dst_valid; /* data valid */ +output [33:0] cmac2csb_resp_dst_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +wire [33:0] cmac2csb_resp_pd_d0; +wire cmac2csb_resp_valid_d0; +wire [62:0] csb2cmac_req_pd_d0; +wire csb2cmac_req_pvld_d0; +reg [33:0] cmac2csb_resp_pd_d1; +reg [33:0] cmac2csb_resp_pd_d2; +reg [33:0] cmac2csb_resp_pd_d3; +reg cmac2csb_resp_valid_d1; +reg cmac2csb_resp_valid_d2; +reg cmac2csb_resp_valid_d3; +reg [62:0] csb2cmac_req_pd_d1; +reg [62:0] csb2cmac_req_pd_d2; +reg [62:0] csb2cmac_req_pd_d3; +reg csb2cmac_req_pvld_d1; +reg csb2cmac_req_pvld_d2; +reg csb2cmac_req_pvld_d3; +assign csb2cmac_req_src_prdy = 1'b1; +assign csb2cmac_req_pvld_d0 = csb2cmac_req_src_pvld; +assign csb2cmac_req_pd_d0 = csb2cmac_req_src_pd; +assign cmac2csb_resp_valid_d0 = cmac2csb_resp_src_valid; +assign cmac2csb_resp_pd_d0 = cmac2csb_resp_src_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_req_pvld_d1 <= 1'b0; + end else begin + csb2cmac_req_pvld_d1 <= csb2cmac_req_pvld_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_req_pvld_d0) == 1'b1) begin + csb2cmac_req_pd_d1 <= csb2cmac_req_pd_d0; +// VCS coverage off + end else if ((csb2cmac_req_pvld_d0) == 1'b0) begin + end else begin + csb2cmac_req_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac2csb_resp_valid_d1 <= 1'b0; + end else begin + cmac2csb_resp_valid_d1 <= cmac2csb_resp_valid_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac2csb_resp_valid_d0) == 1'b1) begin + cmac2csb_resp_pd_d1 <= cmac2csb_resp_pd_d0; +// VCS coverage off + end else if ((cmac2csb_resp_valid_d0) == 1'b0) begin + end else begin + cmac2csb_resp_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_req_pvld_d2 <= 1'b0; + end else begin + csb2cmac_req_pvld_d2 <= csb2cmac_req_pvld_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_req_pvld_d1) == 1'b1) begin + csb2cmac_req_pd_d2 <= csb2cmac_req_pd_d1; +// VCS coverage off + end else if ((csb2cmac_req_pvld_d1) == 1'b0) begin + end else begin + csb2cmac_req_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac2csb_resp_valid_d2 <= 1'b0; + end else begin + cmac2csb_resp_valid_d2 <= cmac2csb_resp_valid_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac2csb_resp_valid_d1) == 1'b1) begin + cmac2csb_resp_pd_d2 <= cmac2csb_resp_pd_d1; +// VCS coverage off + end else if ((cmac2csb_resp_valid_d1) == 1'b0) begin + end else begin + cmac2csb_resp_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_req_pvld_d3 <= 1'b0; + end else begin + csb2cmac_req_pvld_d3 <= csb2cmac_req_pvld_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_req_pvld_d2) == 1'b1) begin + csb2cmac_req_pd_d3 <= csb2cmac_req_pd_d2; +// VCS coverage off + end else if ((csb2cmac_req_pvld_d2) == 1'b0) begin + end else begin + csb2cmac_req_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac2csb_resp_valid_d3 <= 1'b0; + end else begin + cmac2csb_resp_valid_d3 <= cmac2csb_resp_valid_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac2csb_resp_valid_d2) == 1'b1) begin + cmac2csb_resp_pd_d3 <= cmac2csb_resp_pd_d2; +// VCS coverage off + end else if ((cmac2csb_resp_valid_d2) == 1'b0) begin + end else begin + cmac2csb_resp_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2cmac_req_dst_pvld = csb2cmac_req_pvld_d3; +assign csb2cmac_req_dst_pd = csb2cmac_req_pd_d3; +assign cmac2csb_resp_dst_valid = cmac2csb_resp_valid_d3; +assign cmac2csb_resp_dst_pd = cmac2csb_resp_pd_d3; +endmodule // NV_NVDLA_RT_csb2cmac diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v.vcp new file mode 100644 index 0000000..a1a7999 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v.vcp @@ -0,0 +1,165 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csb2cmac.v +module NV_NVDLA_RT_csb2cmac ( + nvdla_core_clk + ,nvdla_core_rstn + ,csb2cmac_req_src_pvld + ,csb2cmac_req_src_prdy + ,csb2cmac_req_src_pd + ,cmac2csb_resp_src_valid + ,cmac2csb_resp_src_pd + ,csb2cmac_req_dst_pvld + ,csb2cmac_req_dst_prdy + ,csb2cmac_req_dst_pd + ,cmac2csb_resp_dst_valid + ,cmac2csb_resp_dst_pd + ); +// +// NV_NVDLA_RT_csb2cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input csb2cmac_req_src_pvld; /* data valid */ +output csb2cmac_req_src_prdy; /* data return handshake */ +input [62:0] csb2cmac_req_src_pd; +input cmac2csb_resp_src_valid; /* data valid */ +input [33:0] cmac2csb_resp_src_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_req_dst_pvld; /* data valid */ +input csb2cmac_req_dst_prdy; /* data return handshake */ +output [62:0] csb2cmac_req_dst_pd; +output cmac2csb_resp_dst_valid; /* data valid */ +output [33:0] cmac2csb_resp_dst_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +wire [33:0] cmac2csb_resp_pd_d0; +wire cmac2csb_resp_valid_d0; +wire [62:0] csb2cmac_req_pd_d0; +wire csb2cmac_req_pvld_d0; +reg [33:0] cmac2csb_resp_pd_d1; +reg [33:0] cmac2csb_resp_pd_d2; +reg [33:0] cmac2csb_resp_pd_d3; +reg cmac2csb_resp_valid_d1; +reg cmac2csb_resp_valid_d2; +reg cmac2csb_resp_valid_d3; +reg [62:0] csb2cmac_req_pd_d1; +reg [62:0] csb2cmac_req_pd_d2; +reg [62:0] csb2cmac_req_pd_d3; +reg csb2cmac_req_pvld_d1; +reg csb2cmac_req_pvld_d2; +reg csb2cmac_req_pvld_d3; +assign csb2cmac_req_src_prdy = 1'b1; +assign csb2cmac_req_pvld_d0 = csb2cmac_req_src_pvld; +assign csb2cmac_req_pd_d0 = csb2cmac_req_src_pd; +assign cmac2csb_resp_valid_d0 = cmac2csb_resp_src_valid; +assign cmac2csb_resp_pd_d0 = cmac2csb_resp_src_pd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_req_pvld_d1 <= 1'b0; + end else begin + csb2cmac_req_pvld_d1 <= csb2cmac_req_pvld_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_req_pvld_d0) == 1'b1) begin + csb2cmac_req_pd_d1 <= csb2cmac_req_pd_d0; +// VCS coverage off + end else if ((csb2cmac_req_pvld_d0) == 1'b0) begin + end else begin + csb2cmac_req_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac2csb_resp_valid_d1 <= 1'b0; + end else begin + cmac2csb_resp_valid_d1 <= cmac2csb_resp_valid_d0; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac2csb_resp_valid_d0) == 1'b1) begin + cmac2csb_resp_pd_d1 <= cmac2csb_resp_pd_d0; +// VCS coverage off + end else if ((cmac2csb_resp_valid_d0) == 1'b0) begin + end else begin + cmac2csb_resp_pd_d1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_req_pvld_d2 <= 1'b0; + end else begin + csb2cmac_req_pvld_d2 <= csb2cmac_req_pvld_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_req_pvld_d1) == 1'b1) begin + csb2cmac_req_pd_d2 <= csb2cmac_req_pd_d1; +// VCS coverage off + end else if ((csb2cmac_req_pvld_d1) == 1'b0) begin + end else begin + csb2cmac_req_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac2csb_resp_valid_d2 <= 1'b0; + end else begin + cmac2csb_resp_valid_d2 <= cmac2csb_resp_valid_d1; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac2csb_resp_valid_d1) == 1'b1) begin + cmac2csb_resp_pd_d2 <= cmac2csb_resp_pd_d1; +// VCS coverage off + end else if ((cmac2csb_resp_valid_d1) == 1'b0) begin + end else begin + cmac2csb_resp_pd_d2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + csb2cmac_req_pvld_d3 <= 1'b0; + end else begin + csb2cmac_req_pvld_d3 <= csb2cmac_req_pvld_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((csb2cmac_req_pvld_d2) == 1'b1) begin + csb2cmac_req_pd_d3 <= csb2cmac_req_pd_d2; +// VCS coverage off + end else if ((csb2cmac_req_pvld_d2) == 1'b0) begin + end else begin + csb2cmac_req_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmac2csb_resp_valid_d3 <= 1'b0; + end else begin + cmac2csb_resp_valid_d3 <= cmac2csb_resp_valid_d2; + end +end +always @(posedge nvdla_core_clk) begin + if ((cmac2csb_resp_valid_d2) == 1'b1) begin + cmac2csb_resp_pd_d3 <= cmac2csb_resp_pd_d2; +// VCS coverage off + end else if ((cmac2csb_resp_valid_d2) == 1'b0) begin + end else begin + cmac2csb_resp_pd_d3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +assign csb2cmac_req_dst_pvld = csb2cmac_req_pvld_d3; +assign csb2cmac_req_dst_pd = csb2cmac_req_pd_d3; +assign cmac2csb_resp_dst_valid = cmac2csb_resp_valid_d3; +assign cmac2csb_resp_dst_pd = cmac2csb_resp_pd_d3; +endmodule // NV_NVDLA_RT_csb2cmac diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v new file mode 100644 index 0000000..a11eb92 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v @@ -0,0 +1,909 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csc2cmac_a.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_RT_csc2cmac_a ( + nvdla_core_clk + ,nvdla_core_rstn + ,sc2mac_wt_src_pvld + ,sc2mac_wt_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_src_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_wt_src_data0 +,sc2mac_wt_src_data1 +,sc2mac_wt_src_data2 +,sc2mac_wt_src_data3 +,sc2mac_wt_src_data4 +,sc2mac_wt_src_data5 +,sc2mac_wt_src_data6 +,sc2mac_wt_src_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_src_sel + ,sc2mac_dat_src_pvld + ,sc2mac_dat_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_src_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_dat_src_data0 +,sc2mac_dat_src_data1 +,sc2mac_dat_src_data2 +,sc2mac_dat_src_data3 +,sc2mac_dat_src_data4 +,sc2mac_dat_src_data5 +,sc2mac_dat_src_data6 +,sc2mac_dat_src_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_src_pd + ,sc2mac_wt_dst_pvld + ,sc2mac_wt_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_dst_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_wt_dst_data0 +,sc2mac_wt_dst_data1 +,sc2mac_wt_dst_data2 +,sc2mac_wt_dst_data3 +,sc2mac_wt_dst_data4 +,sc2mac_wt_dst_data5 +,sc2mac_wt_dst_data6 +,sc2mac_wt_dst_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_dst_sel + ,sc2mac_dat_dst_pvld + ,sc2mac_dat_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_dst_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_dat_dst_data0 +,sc2mac_dat_dst_data1 +,sc2mac_dat_dst_data2 +,sc2mac_dat_dst_data3 +,sc2mac_dat_dst_data4 +,sc2mac_dat_dst_data5 +,sc2mac_dat_dst_data6 +,sc2mac_dat_dst_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_dst_pd + ); +// +// NV_NVDLA_RT_csc2cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sc2mac_wt_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_wt_src_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [8-1:0] sc2mac_wt_src_data0; +input [8-1:0] sc2mac_wt_src_data1; +input [8-1:0] sc2mac_wt_src_data2; +input [8-1:0] sc2mac_wt_src_data3; +input [8-1:0] sc2mac_wt_src_data4; +input [8-1:0] sc2mac_wt_src_data5; +input [8-1:0] sc2mac_wt_src_data6; +input [8-1:0] sc2mac_wt_src_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2 -1:0] sc2mac_wt_src_sel; +input sc2mac_dat_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_dat_src_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [8-1:0] sc2mac_dat_src_data0; +input [8-1:0] sc2mac_dat_src_data1; +input [8-1:0] sc2mac_dat_src_data2; +input [8-1:0] sc2mac_dat_src_data3; +input [8-1:0] sc2mac_dat_src_data4; +input [8-1:0] sc2mac_dat_src_data5; +input [8-1:0] sc2mac_dat_src_data6; +input [8-1:0] sc2mac_dat_src_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] sc2mac_dat_src_pd; +output sc2mac_wt_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_wt_dst_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8-1:0] sc2mac_wt_dst_data0; +output [8-1:0] sc2mac_wt_dst_data1; +output [8-1:0] sc2mac_wt_dst_data2; +output [8-1:0] sc2mac_wt_dst_data3; +output [8-1:0] sc2mac_wt_dst_data4; +output [8-1:0] sc2mac_wt_dst_data5; +output [8-1:0] sc2mac_wt_dst_data6; +output [8-1:0] sc2mac_wt_dst_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8/2 -1:0] sc2mac_wt_dst_sel; +output sc2mac_dat_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_dat_dst_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8-1:0] sc2mac_dat_dst_data0; +output [8-1:0] sc2mac_dat_dst_data1; +output [8-1:0] sc2mac_dat_dst_data2; +output [8-1:0] sc2mac_dat_dst_data3; +output [8-1:0] sc2mac_dat_dst_data4; +output [8-1:0] sc2mac_dat_dst_data5; +output [8-1:0] sc2mac_dat_dst_data6; +output [8-1:0] sc2mac_dat_dst_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] sc2mac_dat_dst_pd; +//: my $delay = 2; +//: my $i; +//: my $j; +//: my $k; +//: my $bb=8; +//: my $kk=8/2; +//: my $cc=8; +//: print "wire sc2mac_wt_pvld_d0 = sc2mac_wt_src_pvld;\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_sel_d0 = sc2mac_wt_src_sel;\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_mask_d0 = sc2mac_wt_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire sc2mac_wt_data${k}_d0 = sc2mac_wt_src_data${k};\n"; +//: } +//: +//: print "wire sc2mac_dat_pvld_d0 = sc2mac_dat_src_pvld;\n"; +//: print "wire[8:0] sc2mac_dat_pd_d0 = sc2mac_dat_src_pd;\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_mask_d0 = sc2mac_dat_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_data${k}_d0 = sc2mac_dat_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q sc2mac_wt_pvld_d${j} -d sc2mac_wt_pvld_d${i}"); +//: &eperl::flop("-wid ${kk} -q sc2mac_wt_sel_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_sel_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_wt_mask_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_wt_data${k}_d${j} -en sc2mac_wt_mask_d${i}[${k}] -d sc2mac_wt_data${k}_d${i}"); +//: } +//: +//: &eperl::flop("-q sc2mac_dat_pvld_d${j} -d sc2mac_dat_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q sc2mac_dat_pd_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_pd_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_dat_mask_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_dat_data${k}_d${j} -en \"(sc2mac_dat_mask_d${i}[${k}])\" -d sc2mac_dat_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "wire sc2mac_wt_dst_pvld = sc2mac_wt_pvld_d${i};\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_dst_sel = sc2mac_wt_sel_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_dst_mask = sc2mac_wt_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_wt_dst_data${k} = sc2mac_wt_data${k}_d${i};\n"; +//: } +//: +//: print "wire sc2mac_dat_dst_pvld = sc2mac_dat_pvld_d${i};\n"; +//: print "wire[8:0] sc2mac_dat_dst_pd = sc2mac_dat_pd_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_dst_mask = sc2mac_dat_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_dst_data${k} = sc2mac_dat_data${k}_d${i};\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire sc2mac_wt_pvld_d0 = sc2mac_wt_src_pvld; +wire[4-1:0] sc2mac_wt_sel_d0 = sc2mac_wt_src_sel; +wire[8-1:0] sc2mac_wt_mask_d0 = sc2mac_wt_src_mask; +wire sc2mac_wt_data0_d0 = sc2mac_wt_src_data0; +wire sc2mac_wt_data1_d0 = sc2mac_wt_src_data1; +wire sc2mac_wt_data2_d0 = sc2mac_wt_src_data2; +wire sc2mac_wt_data3_d0 = sc2mac_wt_src_data3; +wire sc2mac_wt_data4_d0 = sc2mac_wt_src_data4; +wire sc2mac_wt_data5_d0 = sc2mac_wt_src_data5; +wire sc2mac_wt_data6_d0 = sc2mac_wt_src_data6; +wire sc2mac_wt_data7_d0 = sc2mac_wt_src_data7; +wire sc2mac_dat_pvld_d0 = sc2mac_dat_src_pvld; +wire[8:0] sc2mac_dat_pd_d0 = sc2mac_dat_src_pd; +wire[8-1:0] sc2mac_dat_mask_d0 = sc2mac_dat_src_mask; +wire[8-1:0] sc2mac_dat_data0_d0 = sc2mac_dat_src_data0; +wire[8-1:0] sc2mac_dat_data1_d0 = sc2mac_dat_src_data1; +wire[8-1:0] sc2mac_dat_data2_d0 = sc2mac_dat_src_data2; +wire[8-1:0] sc2mac_dat_data3_d0 = sc2mac_dat_src_data3; +wire[8-1:0] sc2mac_dat_data4_d0 = sc2mac_dat_src_data4; +wire[8-1:0] sc2mac_dat_data5_d0 = sc2mac_dat_src_data5; +wire[8-1:0] sc2mac_dat_data6_d0 = sc2mac_dat_src_data6; +wire[8-1:0] sc2mac_dat_data7_d0 = sc2mac_dat_src_data7; +reg sc2mac_wt_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_pvld_d1 <= 'b0; + end else begin + sc2mac_wt_pvld_d1 <= sc2mac_wt_pvld_d0; + end +end +reg [3:0] sc2mac_wt_sel_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_sel_d1 <= 'b0; + end else begin + if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b1) begin + sc2mac_wt_sel_d1 <= sc2mac_wt_sel_d0; + // VCS coverage off + end else if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_wt_sel_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_mask_d1 <= 'b0; + end else begin + if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b1) begin + sc2mac_wt_mask_d1 <= sc2mac_wt_mask_d0; + // VCS coverage off + end else if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_wt_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data0_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[0]) == 1'b1) begin + sc2mac_wt_data0_d1 <= sc2mac_wt_data0_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[0]) == 1'b0) begin + end else begin + sc2mac_wt_data0_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data1_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[1]) == 1'b1) begin + sc2mac_wt_data1_d1 <= sc2mac_wt_data1_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[1]) == 1'b0) begin + end else begin + sc2mac_wt_data1_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data2_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data2_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[2]) == 1'b1) begin + sc2mac_wt_data2_d1 <= sc2mac_wt_data2_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[2]) == 1'b0) begin + end else begin + sc2mac_wt_data2_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data3_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data3_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[3]) == 1'b1) begin + sc2mac_wt_data3_d1 <= sc2mac_wt_data3_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[3]) == 1'b0) begin + end else begin + sc2mac_wt_data3_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data4_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data4_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[4]) == 1'b1) begin + sc2mac_wt_data4_d1 <= sc2mac_wt_data4_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[4]) == 1'b0) begin + end else begin + sc2mac_wt_data4_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data5_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data5_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[5]) == 1'b1) begin + sc2mac_wt_data5_d1 <= sc2mac_wt_data5_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[5]) == 1'b0) begin + end else begin + sc2mac_wt_data5_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data6_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data6_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[6]) == 1'b1) begin + sc2mac_wt_data6_d1 <= sc2mac_wt_data6_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[6]) == 1'b0) begin + end else begin + sc2mac_wt_data6_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data7_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data7_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[7]) == 1'b1) begin + sc2mac_wt_data7_d1 <= sc2mac_wt_data7_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[7]) == 1'b0) begin + end else begin + sc2mac_wt_data7_d1 <= 'bx; + // VCS coverage on + end + end +end +reg sc2mac_dat_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_pvld_d1 <= 'b0; + end else begin + sc2mac_dat_pvld_d1 <= sc2mac_dat_pvld_d0; + end +end +reg [8:0] sc2mac_dat_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_pd_d1 <= 'b0; + end else begin + if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b1) begin + sc2mac_dat_pd_d1 <= sc2mac_dat_pd_d0; + // VCS coverage off + end else if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_dat_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_mask_d1 <= 'b0; + end else begin + if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b1) begin + sc2mac_dat_mask_d1 <= sc2mac_dat_mask_d0; + // VCS coverage off + end else if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_dat_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data0_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[0])) == 1'b1) begin + sc2mac_dat_data0_d1 <= sc2mac_dat_data0_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[0])) == 1'b0) begin + end else begin + sc2mac_dat_data0_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data1_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[1])) == 1'b1) begin + sc2mac_dat_data1_d1 <= sc2mac_dat_data1_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[1])) == 1'b0) begin + end else begin + sc2mac_dat_data1_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data2_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data2_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[2])) == 1'b1) begin + sc2mac_dat_data2_d1 <= sc2mac_dat_data2_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[2])) == 1'b0) begin + end else begin + sc2mac_dat_data2_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data3_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data3_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[3])) == 1'b1) begin + sc2mac_dat_data3_d1 <= sc2mac_dat_data3_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[3])) == 1'b0) begin + end else begin + sc2mac_dat_data3_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data4_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data4_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[4])) == 1'b1) begin + sc2mac_dat_data4_d1 <= sc2mac_dat_data4_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[4])) == 1'b0) begin + end else begin + sc2mac_dat_data4_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data5_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data5_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[5])) == 1'b1) begin + sc2mac_dat_data5_d1 <= sc2mac_dat_data5_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[5])) == 1'b0) begin + end else begin + sc2mac_dat_data5_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data6_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data6_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[6])) == 1'b1) begin + sc2mac_dat_data6_d1 <= sc2mac_dat_data6_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[6])) == 1'b0) begin + end else begin + sc2mac_dat_data6_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data7_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data7_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[7])) == 1'b1) begin + sc2mac_dat_data7_d1 <= sc2mac_dat_data7_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[7])) == 1'b0) begin + end else begin + sc2mac_dat_data7_d1 <= 'bx; + // VCS coverage on + end + end +end +reg sc2mac_wt_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_pvld_d2 <= 'b0; + end else begin + sc2mac_wt_pvld_d2 <= sc2mac_wt_pvld_d1; + end +end +reg [3:0] sc2mac_wt_sel_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_sel_d2 <= 'b0; + end else begin + if (((sc2mac_wt_pvld_d1 | sc2mac_wt_pvld_d2)) == 1'b1) begin + sc2mac_wt_sel_d2 <= sc2mac_wt_sel_d1; + // VCS coverage off + end else if (((sc2mac_wt_pvld_d1 | sc2mac_wt_pvld_d2)) == 1'b0) begin + end else begin + sc2mac_wt_sel_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_mask_d2 <= 'b0; + end else begin + if (((sc2mac_wt_pvld_d1 | sc2mac_wt_pvld_d2)) == 1'b1) begin + sc2mac_wt_mask_d2 <= sc2mac_wt_mask_d1; + // VCS coverage off + end else if (((sc2mac_wt_pvld_d1 | sc2mac_wt_pvld_d2)) == 1'b0) begin + end else begin + sc2mac_wt_mask_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data0_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data0_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[0]) == 1'b1) begin + sc2mac_wt_data0_d2 <= sc2mac_wt_data0_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[0]) == 1'b0) begin + end else begin + sc2mac_wt_data0_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data1_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data1_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[1]) == 1'b1) begin + sc2mac_wt_data1_d2 <= sc2mac_wt_data1_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[1]) == 1'b0) begin + end else begin + sc2mac_wt_data1_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data2_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data2_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[2]) == 1'b1) begin + sc2mac_wt_data2_d2 <= sc2mac_wt_data2_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[2]) == 1'b0) begin + end else begin + sc2mac_wt_data2_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data3_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data3_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[3]) == 1'b1) begin + sc2mac_wt_data3_d2 <= sc2mac_wt_data3_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[3]) == 1'b0) begin + end else begin + sc2mac_wt_data3_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data4_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data4_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[4]) == 1'b1) begin + sc2mac_wt_data4_d2 <= sc2mac_wt_data4_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[4]) == 1'b0) begin + end else begin + sc2mac_wt_data4_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data5_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data5_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[5]) == 1'b1) begin + sc2mac_wt_data5_d2 <= sc2mac_wt_data5_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[5]) == 1'b0) begin + end else begin + sc2mac_wt_data5_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data6_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data6_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[6]) == 1'b1) begin + sc2mac_wt_data6_d2 <= sc2mac_wt_data6_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[6]) == 1'b0) begin + end else begin + sc2mac_wt_data6_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data7_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data7_d2 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d1[7]) == 1'b1) begin + sc2mac_wt_data7_d2 <= sc2mac_wt_data7_d1; + // VCS coverage off + end else if ((sc2mac_wt_mask_d1[7]) == 1'b0) begin + end else begin + sc2mac_wt_data7_d2 <= 'bx; + // VCS coverage on + end + end +end +reg sc2mac_dat_pvld_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_pvld_d2 <= 'b0; + end else begin + sc2mac_dat_pvld_d2 <= sc2mac_dat_pvld_d1; + end +end +reg [8:0] sc2mac_dat_pd_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_pd_d2 <= 'b0; + end else begin + if (((sc2mac_dat_pvld_d1 | sc2mac_dat_pvld_d2)) == 1'b1) begin + sc2mac_dat_pd_d2 <= sc2mac_dat_pd_d1; + // VCS coverage off + end else if (((sc2mac_dat_pvld_d1 | sc2mac_dat_pvld_d2)) == 1'b0) begin + end else begin + sc2mac_dat_pd_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_mask_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_mask_d2 <= 'b0; + end else begin + if (((sc2mac_dat_pvld_d1 | sc2mac_dat_pvld_d2)) == 1'b1) begin + sc2mac_dat_mask_d2 <= sc2mac_dat_mask_d1; + // VCS coverage off + end else if (((sc2mac_dat_pvld_d1 | sc2mac_dat_pvld_d2)) == 1'b0) begin + end else begin + sc2mac_dat_mask_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data0_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data0_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[0])) == 1'b1) begin + sc2mac_dat_data0_d2 <= sc2mac_dat_data0_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[0])) == 1'b0) begin + end else begin + sc2mac_dat_data0_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data1_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data1_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[1])) == 1'b1) begin + sc2mac_dat_data1_d2 <= sc2mac_dat_data1_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[1])) == 1'b0) begin + end else begin + sc2mac_dat_data1_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data2_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data2_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[2])) == 1'b1) begin + sc2mac_dat_data2_d2 <= sc2mac_dat_data2_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[2])) == 1'b0) begin + end else begin + sc2mac_dat_data2_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data3_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data3_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[3])) == 1'b1) begin + sc2mac_dat_data3_d2 <= sc2mac_dat_data3_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[3])) == 1'b0) begin + end else begin + sc2mac_dat_data3_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data4_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data4_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[4])) == 1'b1) begin + sc2mac_dat_data4_d2 <= sc2mac_dat_data4_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[4])) == 1'b0) begin + end else begin + sc2mac_dat_data4_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data5_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data5_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[5])) == 1'b1) begin + sc2mac_dat_data5_d2 <= sc2mac_dat_data5_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[5])) == 1'b0) begin + end else begin + sc2mac_dat_data5_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data6_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data6_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[6])) == 1'b1) begin + sc2mac_dat_data6_d2 <= sc2mac_dat_data6_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[6])) == 1'b0) begin + end else begin + sc2mac_dat_data6_d2 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data7_d2; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data7_d2 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d1[7])) == 1'b1) begin + sc2mac_dat_data7_d2 <= sc2mac_dat_data7_d1; + // VCS coverage off + end else if (((sc2mac_dat_mask_d1[7])) == 1'b0) begin + end else begin + sc2mac_dat_data7_d2 <= 'bx; + // VCS coverage on + end + end +end +wire sc2mac_wt_dst_pvld = sc2mac_wt_pvld_d2; +wire[4-1:0] sc2mac_wt_dst_sel = sc2mac_wt_sel_d2; +wire[8-1:0] sc2mac_wt_dst_mask = sc2mac_wt_mask_d2; +wire[8-1:0] sc2mac_wt_dst_data0 = sc2mac_wt_data0_d2; +wire[8-1:0] sc2mac_wt_dst_data1 = sc2mac_wt_data1_d2; +wire[8-1:0] sc2mac_wt_dst_data2 = sc2mac_wt_data2_d2; +wire[8-1:0] sc2mac_wt_dst_data3 = sc2mac_wt_data3_d2; +wire[8-1:0] sc2mac_wt_dst_data4 = sc2mac_wt_data4_d2; +wire[8-1:0] sc2mac_wt_dst_data5 = sc2mac_wt_data5_d2; +wire[8-1:0] sc2mac_wt_dst_data6 = sc2mac_wt_data6_d2; +wire[8-1:0] sc2mac_wt_dst_data7 = sc2mac_wt_data7_d2; +wire sc2mac_dat_dst_pvld = sc2mac_dat_pvld_d2; +wire[8:0] sc2mac_dat_dst_pd = sc2mac_dat_pd_d2; +wire[8-1:0] sc2mac_dat_dst_mask = sc2mac_dat_mask_d2; +wire[8-1:0] sc2mac_dat_dst_data0 = sc2mac_dat_data0_d2; +wire[8-1:0] sc2mac_dat_dst_data1 = sc2mac_dat_data1_d2; +wire[8-1:0] sc2mac_dat_dst_data2 = sc2mac_dat_data2_d2; +wire[8-1:0] sc2mac_dat_dst_data3 = sc2mac_dat_data3_d2; +wire[8-1:0] sc2mac_dat_dst_data4 = sc2mac_dat_data4_d2; +wire[8-1:0] sc2mac_dat_dst_data5 = sc2mac_dat_data5_d2; +wire[8-1:0] sc2mac_dat_dst_data6 = sc2mac_dat_data6_d2; +wire[8-1:0] sc2mac_dat_dst_data7 = sc2mac_dat_data7_d2; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_RT_csc2cmac_a diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v.vcp new file mode 100644 index 0000000..4a83907 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v.vcp @@ -0,0 +1,142 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csc2cmac_a.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_RT_csc2cmac_a ( + nvdla_core_clk + ,nvdla_core_rstn + ,sc2mac_wt_src_pvld + ,sc2mac_wt_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_src_data${i} \n"; +//: } + ,sc2mac_wt_src_sel + ,sc2mac_dat_src_pvld + ,sc2mac_dat_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_src_data${i} \n"; +//: } + ,sc2mac_dat_src_pd + ,sc2mac_wt_dst_pvld + ,sc2mac_wt_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_dst_data${i} \n"; +//: } + ,sc2mac_wt_dst_sel + ,sc2mac_dat_dst_pvld + ,sc2mac_dat_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_dst_data${i} \n"; +//: } + ,sc2mac_dat_dst_pd + ); +// +// NV_NVDLA_RT_csc2cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sc2mac_wt_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_wt_src_data${i}; \n"; +//: } +input [8/2 -1:0] sc2mac_wt_src_sel; +input sc2mac_dat_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_dat_src_data${i}; \n"; +//: } +input [8:0] sc2mac_dat_src_pd; +output sc2mac_wt_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_wt_dst_data${i}; \n"; +//: } +output [8/2 -1:0] sc2mac_wt_dst_sel; +output sc2mac_dat_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_dat_dst_data${i}; \n"; +//: } +output [8:0] sc2mac_dat_dst_pd; +//: my $delay = 2; +//: my $i; +//: my $j; +//: my $k; +//: my $bb=8; +//: my $kk=8/2; +//: my $cc=8; +//: print "wire sc2mac_wt_pvld_d0 = sc2mac_wt_src_pvld;\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_sel_d0 = sc2mac_wt_src_sel;\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_mask_d0 = sc2mac_wt_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire sc2mac_wt_data${k}_d0 = sc2mac_wt_src_data${k};\n"; +//: } +//: +//: print "wire sc2mac_dat_pvld_d0 = sc2mac_dat_src_pvld;\n"; +//: print "wire[8:0] sc2mac_dat_pd_d0 = sc2mac_dat_src_pd;\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_mask_d0 = sc2mac_dat_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_data${k}_d0 = sc2mac_dat_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q sc2mac_wt_pvld_d${j} -d sc2mac_wt_pvld_d${i}"); +//: &eperl::flop("-wid ${kk} -q sc2mac_wt_sel_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_sel_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_wt_mask_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_wt_data${k}_d${j} -en sc2mac_wt_mask_d${i}[${k}] -d sc2mac_wt_data${k}_d${i}"); +//: } +//: +//: &eperl::flop("-q sc2mac_dat_pvld_d${j} -d sc2mac_dat_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q sc2mac_dat_pd_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_pd_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_dat_mask_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_dat_data${k}_d${j} -en \"(sc2mac_dat_mask_d${i}[${k}])\" -d sc2mac_dat_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "wire sc2mac_wt_dst_pvld = sc2mac_wt_pvld_d${i};\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_dst_sel = sc2mac_wt_sel_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_dst_mask = sc2mac_wt_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_wt_dst_data${k} = sc2mac_wt_data${k}_d${i};\n"; +//: } +//: +//: print "wire sc2mac_dat_dst_pvld = sc2mac_dat_pvld_d${i};\n"; +//: print "wire[8:0] sc2mac_dat_dst_pd = sc2mac_dat_pd_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_dst_mask = sc2mac_dat_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_dst_data${k} = sc2mac_dat_data${k}_d${i};\n"; +//: } +endmodule // NV_NVDLA_RT_csc2cmac_a diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v new file mode 100644 index 0000000..b0604de --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v @@ -0,0 +1,593 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csc2cmac_b.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_RT_csc2cmac_b( + nvdla_core_clk + ,nvdla_core_rstn + ,sc2mac_wt_src_pvld + ,sc2mac_wt_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_src_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_wt_src_data0 +,sc2mac_wt_src_data1 +,sc2mac_wt_src_data2 +,sc2mac_wt_src_data3 +,sc2mac_wt_src_data4 +,sc2mac_wt_src_data5 +,sc2mac_wt_src_data6 +,sc2mac_wt_src_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_src_sel + ,sc2mac_dat_src_pvld + ,sc2mac_dat_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_src_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_dat_src_data0 +,sc2mac_dat_src_data1 +,sc2mac_dat_src_data2 +,sc2mac_dat_src_data3 +,sc2mac_dat_src_data4 +,sc2mac_dat_src_data5 +,sc2mac_dat_src_data6 +,sc2mac_dat_src_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_src_pd + ,sc2mac_wt_dst_pvld + ,sc2mac_wt_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_dst_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_wt_dst_data0 +,sc2mac_wt_dst_data1 +,sc2mac_wt_dst_data2 +,sc2mac_wt_dst_data3 +,sc2mac_wt_dst_data4 +,sc2mac_wt_dst_data5 +,sc2mac_wt_dst_data6 +,sc2mac_wt_dst_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_dst_sel + ,sc2mac_dat_dst_pvld + ,sc2mac_dat_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_dst_data${i} \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,sc2mac_dat_dst_data0 +,sc2mac_dat_dst_data1 +,sc2mac_dat_dst_data2 +,sc2mac_dat_dst_data3 +,sc2mac_dat_dst_data4 +,sc2mac_dat_dst_data5 +,sc2mac_dat_dst_data6 +,sc2mac_dat_dst_data7 + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_dst_pd + ); +// +// NV_NVDLA_RT_csc2cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sc2mac_wt_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_wt_src_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [8-1:0] sc2mac_wt_src_data0; +input [8-1:0] sc2mac_wt_src_data1; +input [8-1:0] sc2mac_wt_src_data2; +input [8-1:0] sc2mac_wt_src_data3; +input [8-1:0] sc2mac_wt_src_data4; +input [8-1:0] sc2mac_wt_src_data5; +input [8-1:0] sc2mac_wt_src_data6; +input [8-1:0] sc2mac_wt_src_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2 -1:0] sc2mac_wt_src_sel; +input sc2mac_dat_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_dat_src_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +input [8-1:0] sc2mac_dat_src_data0; +input [8-1:0] sc2mac_dat_src_data1; +input [8-1:0] sc2mac_dat_src_data2; +input [8-1:0] sc2mac_dat_src_data3; +input [8-1:0] sc2mac_dat_src_data4; +input [8-1:0] sc2mac_dat_src_data5; +input [8-1:0] sc2mac_dat_src_data6; +input [8-1:0] sc2mac_dat_src_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] sc2mac_dat_src_pd; +output sc2mac_wt_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_wt_dst_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8-1:0] sc2mac_wt_dst_data0; +output [8-1:0] sc2mac_wt_dst_data1; +output [8-1:0] sc2mac_wt_dst_data2; +output [8-1:0] sc2mac_wt_dst_data3; +output [8-1:0] sc2mac_wt_dst_data4; +output [8-1:0] sc2mac_wt_dst_data5; +output [8-1:0] sc2mac_wt_dst_data6; +output [8-1:0] sc2mac_wt_dst_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8/2 -1:0] sc2mac_wt_dst_sel; +output sc2mac_dat_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_dat_dst_data${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +output [8-1:0] sc2mac_dat_dst_data0; +output [8-1:0] sc2mac_dat_dst_data1; +output [8-1:0] sc2mac_dat_dst_data2; +output [8-1:0] sc2mac_dat_dst_data3; +output [8-1:0] sc2mac_dat_dst_data4; +output [8-1:0] sc2mac_dat_dst_data5; +output [8-1:0] sc2mac_dat_dst_data6; +output [8-1:0] sc2mac_dat_dst_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] sc2mac_dat_dst_pd; +//: my $delay = 1; +//: my $i; +//: my $j; +//: my $k; +//: my $bb=8; +//: my $kk=8/2; +//: my $cc=8; +//: print "wire sc2mac_wt_pvld_d0 = sc2mac_wt_src_pvld;\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_sel_d0 = sc2mac_wt_src_sel;\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_mask_d0 = sc2mac_wt_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire sc2mac_wt_data${k}_d0 = sc2mac_wt_src_data${k};\n"; +//: } +//: +//: print "wire sc2mac_dat_pvld_d0 = sc2mac_dat_src_pvld;\n"; +//: print "wire[8:0] sc2mac_dat_pd_d0 = sc2mac_dat_src_pd;\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_mask_d0 = sc2mac_dat_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_data${k}_d0 = sc2mac_dat_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q sc2mac_wt_pvld_d${j} -d sc2mac_wt_pvld_d${i}"); +//: &eperl::flop("-wid ${kk} -q sc2mac_wt_sel_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_sel_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_wt_mask_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_wt_data${k}_d${j} -en sc2mac_wt_mask_d${i}[${k}] -d sc2mac_wt_data${k}_d${i}"); +//: } +//: +//: &eperl::flop("-q sc2mac_dat_pvld_d${j} -d sc2mac_dat_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q sc2mac_dat_pd_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_pd_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_dat_mask_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_dat_data${k}_d${j} -en \"(sc2mac_dat_mask_d${i}[${k}])\" -d sc2mac_dat_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "wire sc2mac_wt_dst_pvld = sc2mac_wt_pvld_d${i};\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_dst_sel = sc2mac_wt_sel_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_dst_mask = sc2mac_wt_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_wt_dst_data${k} = sc2mac_wt_data${k}_d${i};\n"; +//: } +//: +//: print "wire sc2mac_dat_dst_pvld = sc2mac_dat_pvld_d${i};\n"; +//: print "wire[8:0] sc2mac_dat_dst_pd = sc2mac_dat_pd_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_dst_mask = sc2mac_dat_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_dst_data${k} = sc2mac_dat_data${k}_d${i};\n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire sc2mac_wt_pvld_d0 = sc2mac_wt_src_pvld; +wire[4-1:0] sc2mac_wt_sel_d0 = sc2mac_wt_src_sel; +wire[8-1:0] sc2mac_wt_mask_d0 = sc2mac_wt_src_mask; +wire sc2mac_wt_data0_d0 = sc2mac_wt_src_data0; +wire sc2mac_wt_data1_d0 = sc2mac_wt_src_data1; +wire sc2mac_wt_data2_d0 = sc2mac_wt_src_data2; +wire sc2mac_wt_data3_d0 = sc2mac_wt_src_data3; +wire sc2mac_wt_data4_d0 = sc2mac_wt_src_data4; +wire sc2mac_wt_data5_d0 = sc2mac_wt_src_data5; +wire sc2mac_wt_data6_d0 = sc2mac_wt_src_data6; +wire sc2mac_wt_data7_d0 = sc2mac_wt_src_data7; +wire sc2mac_dat_pvld_d0 = sc2mac_dat_src_pvld; +wire[8:0] sc2mac_dat_pd_d0 = sc2mac_dat_src_pd; +wire[8-1:0] sc2mac_dat_mask_d0 = sc2mac_dat_src_mask; +wire[8-1:0] sc2mac_dat_data0_d0 = sc2mac_dat_src_data0; +wire[8-1:0] sc2mac_dat_data1_d0 = sc2mac_dat_src_data1; +wire[8-1:0] sc2mac_dat_data2_d0 = sc2mac_dat_src_data2; +wire[8-1:0] sc2mac_dat_data3_d0 = sc2mac_dat_src_data3; +wire[8-1:0] sc2mac_dat_data4_d0 = sc2mac_dat_src_data4; +wire[8-1:0] sc2mac_dat_data5_d0 = sc2mac_dat_src_data5; +wire[8-1:0] sc2mac_dat_data6_d0 = sc2mac_dat_src_data6; +wire[8-1:0] sc2mac_dat_data7_d0 = sc2mac_dat_src_data7; +reg sc2mac_wt_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_pvld_d1 <= 'b0; + end else begin + sc2mac_wt_pvld_d1 <= sc2mac_wt_pvld_d0; + end +end +reg [3:0] sc2mac_wt_sel_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_sel_d1 <= 'b0; + end else begin + if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b1) begin + sc2mac_wt_sel_d1 <= sc2mac_wt_sel_d0; + // VCS coverage off + end else if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_wt_sel_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_mask_d1 <= 'b0; + end else begin + if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b1) begin + sc2mac_wt_mask_d1 <= sc2mac_wt_mask_d0; + // VCS coverage off + end else if (((sc2mac_wt_pvld_d0 | sc2mac_wt_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_wt_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data0_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[0]) == 1'b1) begin + sc2mac_wt_data0_d1 <= sc2mac_wt_data0_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[0]) == 1'b0) begin + end else begin + sc2mac_wt_data0_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data1_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[1]) == 1'b1) begin + sc2mac_wt_data1_d1 <= sc2mac_wt_data1_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[1]) == 1'b0) begin + end else begin + sc2mac_wt_data1_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data2_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data2_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[2]) == 1'b1) begin + sc2mac_wt_data2_d1 <= sc2mac_wt_data2_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[2]) == 1'b0) begin + end else begin + sc2mac_wt_data2_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data3_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data3_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[3]) == 1'b1) begin + sc2mac_wt_data3_d1 <= sc2mac_wt_data3_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[3]) == 1'b0) begin + end else begin + sc2mac_wt_data3_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data4_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data4_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[4]) == 1'b1) begin + sc2mac_wt_data4_d1 <= sc2mac_wt_data4_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[4]) == 1'b0) begin + end else begin + sc2mac_wt_data4_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data5_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data5_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[5]) == 1'b1) begin + sc2mac_wt_data5_d1 <= sc2mac_wt_data5_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[5]) == 1'b0) begin + end else begin + sc2mac_wt_data5_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data6_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data6_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[6]) == 1'b1) begin + sc2mac_wt_data6_d1 <= sc2mac_wt_data6_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[6]) == 1'b0) begin + end else begin + sc2mac_wt_data6_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_wt_data7_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_wt_data7_d1 <= 'b0; + end else begin + if ((sc2mac_wt_mask_d0[7]) == 1'b1) begin + sc2mac_wt_data7_d1 <= sc2mac_wt_data7_d0; + // VCS coverage off + end else if ((sc2mac_wt_mask_d0[7]) == 1'b0) begin + end else begin + sc2mac_wt_data7_d1 <= 'bx; + // VCS coverage on + end + end +end +reg sc2mac_dat_pvld_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_pvld_d1 <= 'b0; + end else begin + sc2mac_dat_pvld_d1 <= sc2mac_dat_pvld_d0; + end +end +reg [8:0] sc2mac_dat_pd_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_pd_d1 <= 'b0; + end else begin + if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b1) begin + sc2mac_dat_pd_d1 <= sc2mac_dat_pd_d0; + // VCS coverage off + end else if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_dat_pd_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_mask_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_mask_d1 <= 'b0; + end else begin + if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b1) begin + sc2mac_dat_mask_d1 <= sc2mac_dat_mask_d0; + // VCS coverage off + end else if (((sc2mac_dat_pvld_d0 | sc2mac_dat_pvld_d1)) == 1'b0) begin + end else begin + sc2mac_dat_mask_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data0_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data0_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[0])) == 1'b1) begin + sc2mac_dat_data0_d1 <= sc2mac_dat_data0_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[0])) == 1'b0) begin + end else begin + sc2mac_dat_data0_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data1_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data1_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[1])) == 1'b1) begin + sc2mac_dat_data1_d1 <= sc2mac_dat_data1_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[1])) == 1'b0) begin + end else begin + sc2mac_dat_data1_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data2_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data2_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[2])) == 1'b1) begin + sc2mac_dat_data2_d1 <= sc2mac_dat_data2_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[2])) == 1'b0) begin + end else begin + sc2mac_dat_data2_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data3_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data3_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[3])) == 1'b1) begin + sc2mac_dat_data3_d1 <= sc2mac_dat_data3_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[3])) == 1'b0) begin + end else begin + sc2mac_dat_data3_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data4_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data4_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[4])) == 1'b1) begin + sc2mac_dat_data4_d1 <= sc2mac_dat_data4_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[4])) == 1'b0) begin + end else begin + sc2mac_dat_data4_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data5_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data5_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[5])) == 1'b1) begin + sc2mac_dat_data5_d1 <= sc2mac_dat_data5_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[5])) == 1'b0) begin + end else begin + sc2mac_dat_data5_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data6_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data6_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[6])) == 1'b1) begin + sc2mac_dat_data6_d1 <= sc2mac_dat_data6_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[6])) == 1'b0) begin + end else begin + sc2mac_dat_data6_d1 <= 'bx; + // VCS coverage on + end + end +end +reg [7:0] sc2mac_dat_data7_d1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sc2mac_dat_data7_d1 <= 'b0; + end else begin + if (((sc2mac_dat_mask_d0[7])) == 1'b1) begin + sc2mac_dat_data7_d1 <= sc2mac_dat_data7_d0; + // VCS coverage off + end else if (((sc2mac_dat_mask_d0[7])) == 1'b0) begin + end else begin + sc2mac_dat_data7_d1 <= 'bx; + // VCS coverage on + end + end +end +wire sc2mac_wt_dst_pvld = sc2mac_wt_pvld_d1; +wire[4-1:0] sc2mac_wt_dst_sel = sc2mac_wt_sel_d1; +wire[8-1:0] sc2mac_wt_dst_mask = sc2mac_wt_mask_d1; +wire[8-1:0] sc2mac_wt_dst_data0 = sc2mac_wt_data0_d1; +wire[8-1:0] sc2mac_wt_dst_data1 = sc2mac_wt_data1_d1; +wire[8-1:0] sc2mac_wt_dst_data2 = sc2mac_wt_data2_d1; +wire[8-1:0] sc2mac_wt_dst_data3 = sc2mac_wt_data3_d1; +wire[8-1:0] sc2mac_wt_dst_data4 = sc2mac_wt_data4_d1; +wire[8-1:0] sc2mac_wt_dst_data5 = sc2mac_wt_data5_d1; +wire[8-1:0] sc2mac_wt_dst_data6 = sc2mac_wt_data6_d1; +wire[8-1:0] sc2mac_wt_dst_data7 = sc2mac_wt_data7_d1; +wire sc2mac_dat_dst_pvld = sc2mac_dat_pvld_d1; +wire[8:0] sc2mac_dat_dst_pd = sc2mac_dat_pd_d1; +wire[8-1:0] sc2mac_dat_dst_mask = sc2mac_dat_mask_d1; +wire[8-1:0] sc2mac_dat_dst_data0 = sc2mac_dat_data0_d1; +wire[8-1:0] sc2mac_dat_dst_data1 = sc2mac_dat_data1_d1; +wire[8-1:0] sc2mac_dat_dst_data2 = sc2mac_dat_data2_d1; +wire[8-1:0] sc2mac_dat_dst_data3 = sc2mac_dat_data3_d1; +wire[8-1:0] sc2mac_dat_dst_data4 = sc2mac_dat_data4_d1; +wire[8-1:0] sc2mac_dat_dst_data5 = sc2mac_dat_data5_d1; +wire[8-1:0] sc2mac_dat_dst_data6 = sc2mac_dat_data6_d1; +wire[8-1:0] sc2mac_dat_dst_data7 = sc2mac_dat_data7_d1; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_RT_csc2cmac_b diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v.vcp new file mode 100644 index 0000000..cea9da2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v.vcp @@ -0,0 +1,142 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_csc2cmac_b.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_RT_csc2cmac_b( + nvdla_core_clk + ,nvdla_core_rstn + ,sc2mac_wt_src_pvld + ,sc2mac_wt_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_src_data${i} \n"; +//: } + ,sc2mac_wt_src_sel + ,sc2mac_dat_src_pvld + ,sc2mac_dat_src_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_src_data${i} \n"; +//: } + ,sc2mac_dat_src_pd + ,sc2mac_wt_dst_pvld + ,sc2mac_wt_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_wt_dst_data${i} \n"; +//: } + ,sc2mac_wt_dst_sel + ,sc2mac_dat_dst_pvld + ,sc2mac_dat_dst_mask +//: for(my $i=0; $i<8; $i++){ +//: print ",sc2mac_dat_dst_data${i} \n"; +//: } + ,sc2mac_dat_dst_pd + ); +// +// NV_NVDLA_RT_csc2cmac_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sc2mac_wt_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_wt_src_data${i}; \n"; +//: } +input [8/2 -1:0] sc2mac_wt_src_sel; +input sc2mac_dat_src_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_src_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "input [${bb}-1:0] sc2mac_dat_src_data${i}; \n"; +//: } +input [8:0] sc2mac_dat_src_pd; +output sc2mac_wt_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_wt_dst_data${i}; \n"; +//: } +output [8/2 -1:0] sc2mac_wt_dst_sel; +output sc2mac_dat_dst_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_dst_mask; +//: my $bb=8; +//: for(my $i=0; $i<8; $i++){ +//: print "output [${bb}-1:0] sc2mac_dat_dst_data${i}; \n"; +//: } +output [8:0] sc2mac_dat_dst_pd; +//: my $delay = 1; +//: my $i; +//: my $j; +//: my $k; +//: my $bb=8; +//: my $kk=8/2; +//: my $cc=8; +//: print "wire sc2mac_wt_pvld_d0 = sc2mac_wt_src_pvld;\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_sel_d0 = sc2mac_wt_src_sel;\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_mask_d0 = sc2mac_wt_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire sc2mac_wt_data${k}_d0 = sc2mac_wt_src_data${k};\n"; +//: } +//: +//: print "wire sc2mac_dat_pvld_d0 = sc2mac_dat_src_pvld;\n"; +//: print "wire[8:0] sc2mac_dat_pd_d0 = sc2mac_dat_src_pd;\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_mask_d0 = sc2mac_dat_src_mask;\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_data${k}_d0 = sc2mac_dat_src_data${k};\n"; +//: } +//: +//: for($i = 0; $i < $delay; $i ++) { +//: $j = $i + 1; +//: &eperl::flop("-q sc2mac_wt_pvld_d${j} -d sc2mac_wt_pvld_d${i}"); +//: &eperl::flop("-wid ${kk} -q sc2mac_wt_sel_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_sel_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_wt_mask_d${j} -en \"(sc2mac_wt_pvld_d${i} | sc2mac_wt_pvld_d${j})\" -d sc2mac_wt_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_wt_data${k}_d${j} -en sc2mac_wt_mask_d${i}[${k}] -d sc2mac_wt_data${k}_d${i}"); +//: } +//: +//: &eperl::flop("-q sc2mac_dat_pvld_d${j} -d sc2mac_dat_pvld_d${i}"); +//: &eperl::flop("-wid 9 -q sc2mac_dat_pd_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_pd_d${i}"); +//: &eperl::flop("-wid ${cc} -q sc2mac_dat_mask_d${j} -en \"(sc2mac_dat_pvld_d${i} | sc2mac_dat_pvld_d${j})\" -d sc2mac_dat_mask_d${i}"); +//: for($k = 0; $k <8; $k ++) { +//: &eperl::flop("-wid ${bb} -q sc2mac_dat_data${k}_d${j} -en \"(sc2mac_dat_mask_d${i}[${k}])\" -d sc2mac_dat_data${k}_d${i}"); +//: } +//: } +//: +//: $i = $delay; +//: print "wire sc2mac_wt_dst_pvld = sc2mac_wt_pvld_d${i};\n"; +//: print "wire[${kk}-1:0] sc2mac_wt_dst_sel = sc2mac_wt_sel_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_wt_dst_mask = sc2mac_wt_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_wt_dst_data${k} = sc2mac_wt_data${k}_d${i};\n"; +//: } +//: +//: print "wire sc2mac_dat_dst_pvld = sc2mac_dat_pvld_d${i};\n"; +//: print "wire[8:0] sc2mac_dat_dst_pd = sc2mac_dat_pd_d${i};\n"; +//: print "wire[${cc}-1:0] sc2mac_dat_dst_mask = sc2mac_dat_mask_d${i};\n"; +//: for($k = 0; $k <8; $k ++) { +//: print "wire[${bb}-1:0] sc2mac_dat_dst_data${k} = sc2mac_dat_data${k}_d${i};\n"; +//: } +endmodule // NV_NVDLA_RT_csc2cmac_b diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_sdp2nocif.v b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_sdp2nocif.v new file mode 100644 index 0000000..7c6cf17 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_sdp2nocif.v @@ -0,0 +1,1600 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_sdp2nocif.v +module NV_NVDLA_RT_sdp2nocif ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sdp2mcif_rd_req_src_valid //|< i + ,sdp2mcif_rd_req_src_ready //|> o + ,sdp2mcif_rd_req_src_pd //|< i + ,sdp2mcif_rd_req_dst_valid //|> o + ,sdp2mcif_rd_req_dst_ready //|< i + ,sdp2mcif_rd_req_dst_pd //|> o + ,sdp2cvif_rd_req_src_valid //|< i + ,sdp2cvif_rd_req_src_ready //|> o + ,sdp2cvif_rd_req_src_pd //|< i + ,sdp2cvif_rd_req_dst_valid //|> o + ,sdp2cvif_rd_req_dst_ready //|< i + ,sdp2cvif_rd_req_dst_pd //|> o + ,sdp2mcif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp2mcif_rd_cdt_dst_lat_fifo_pop //|> o + ,sdp2cvif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp2cvif_rd_cdt_dst_lat_fifo_pop //|> o + ,mcif2sdp_rd_rsp_src_valid //|< i + ,mcif2sdp_rd_rsp_src_ready //|> o + ,mcif2sdp_rd_rsp_src_pd //|< i + ,mcif2sdp_rd_rsp_dst_valid //|> o + ,mcif2sdp_rd_rsp_dst_ready //|< i + ,mcif2sdp_rd_rsp_dst_pd //|> o + ,cvif2sdp_rd_rsp_src_valid //|< i + ,cvif2sdp_rd_rsp_src_ready //|> o + ,cvif2sdp_rd_rsp_src_pd //|< i + ,cvif2sdp_rd_rsp_dst_valid //|> o + ,cvif2sdp_rd_rsp_dst_ready //|< i + ,cvif2sdp_rd_rsp_dst_pd //|> o + ,sdp_b2mcif_rd_req_src_valid //|< i + ,sdp_b2mcif_rd_req_src_ready //|> o + ,sdp_b2mcif_rd_req_src_pd //|< i + ,sdp_b2mcif_rd_req_dst_valid //|> o + ,sdp_b2mcif_rd_req_dst_ready //|< i + ,sdp_b2mcif_rd_req_dst_pd //|> o + ,sdp_b2cvif_rd_req_src_valid //|< i + ,sdp_b2cvif_rd_req_src_ready //|> o + ,sdp_b2cvif_rd_req_src_pd //|< i + ,sdp_b2cvif_rd_req_dst_valid //|> o + ,sdp_b2cvif_rd_req_dst_ready //|< i + ,sdp_b2cvif_rd_req_dst_pd //|> o + ,sdp_b2mcif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp_b2mcif_rd_cdt_dst_lat_fifo_pop //|> o + ,sdp_b2cvif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp_b2cvif_rd_cdt_dst_lat_fifo_pop //|> o + ,mcif2sdp_b_rd_rsp_src_valid //|< i + ,mcif2sdp_b_rd_rsp_src_ready //|> o + ,mcif2sdp_b_rd_rsp_src_pd //|< i + ,mcif2sdp_b_rd_rsp_dst_valid //|> o + ,mcif2sdp_b_rd_rsp_dst_ready //|< i + ,mcif2sdp_b_rd_rsp_dst_pd //|> o + ,cvif2sdp_b_rd_rsp_src_valid //|< i + ,cvif2sdp_b_rd_rsp_src_ready //|> o + ,cvif2sdp_b_rd_rsp_src_pd //|< i + ,cvif2sdp_b_rd_rsp_dst_valid //|> o + ,cvif2sdp_b_rd_rsp_dst_ready //|< i + ,cvif2sdp_b_rd_rsp_dst_pd //|> o + ); +// +// NV_NVDLA_RT_sdp2nocif_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sdp2mcif_rd_req_src_valid; /* data valid */ +output sdp2mcif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp2mcif_rd_req_src_pd; +output sdp2mcif_rd_req_dst_valid; /* data valid */ +input sdp2mcif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp2mcif_rd_req_dst_pd; +input sdp2cvif_rd_req_src_valid; /* data valid */ +output sdp2cvif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp2cvif_rd_req_src_pd; +output sdp2cvif_rd_req_dst_valid; /* data valid */ +input sdp2cvif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp2cvif_rd_req_dst_pd; +input sdp2mcif_rd_cdt_src_lat_fifo_pop; +output sdp2mcif_rd_cdt_dst_lat_fifo_pop; +input sdp2cvif_rd_cdt_src_lat_fifo_pop; +output sdp2cvif_rd_cdt_dst_lat_fifo_pop; +input mcif2sdp_rd_rsp_src_valid; /* data valid */ +output mcif2sdp_rd_rsp_src_ready; /* data return handshake */ +input [513:0] mcif2sdp_rd_rsp_src_pd; +output mcif2sdp_rd_rsp_dst_valid; /* data valid */ +input mcif2sdp_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] mcif2sdp_rd_rsp_dst_pd; +input cvif2sdp_rd_rsp_src_valid; /* data valid */ +output cvif2sdp_rd_rsp_src_ready; /* data return handshake */ +input [513:0] cvif2sdp_rd_rsp_src_pd; +output cvif2sdp_rd_rsp_dst_valid; /* data valid */ +input cvif2sdp_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] cvif2sdp_rd_rsp_dst_pd; +input sdp_b2mcif_rd_req_src_valid; /* data valid */ +output sdp_b2mcif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp_b2mcif_rd_req_src_pd; +output sdp_b2mcif_rd_req_dst_valid; /* data valid */ +input sdp_b2mcif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp_b2mcif_rd_req_dst_pd; +input sdp_b2cvif_rd_req_src_valid; /* data valid */ +output sdp_b2cvif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp_b2cvif_rd_req_src_pd; +output sdp_b2cvif_rd_req_dst_valid; /* data valid */ +input sdp_b2cvif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp_b2cvif_rd_req_dst_pd; +input sdp_b2mcif_rd_cdt_src_lat_fifo_pop; +output sdp_b2mcif_rd_cdt_dst_lat_fifo_pop; +input sdp_b2cvif_rd_cdt_src_lat_fifo_pop; +output sdp_b2cvif_rd_cdt_dst_lat_fifo_pop; +input mcif2sdp_b_rd_rsp_src_valid; /* data valid */ +output mcif2sdp_b_rd_rsp_src_ready; /* data return handshake */ +input [513:0] mcif2sdp_b_rd_rsp_src_pd; +output mcif2sdp_b_rd_rsp_dst_valid; /* data valid */ +input mcif2sdp_b_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] mcif2sdp_b_rd_rsp_dst_pd; +input cvif2sdp_b_rd_rsp_src_valid; /* data valid */ +output cvif2sdp_b_rd_rsp_src_ready; /* data return handshake */ +input [513:0] cvif2sdp_b_rd_rsp_src_pd; +output cvif2sdp_b_rd_rsp_dst_valid; /* data valid */ +input cvif2sdp_b_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] cvif2sdp_b_rd_rsp_dst_pd; +reg sdp2cvif_rd_cdt_src_lat_fifo_pop_d1; +reg sdp2mcif_rd_cdt_src_lat_fifo_pop_d1; +reg sdp_b2cvif_rd_cdt_src_lat_fifo_pop_d1; +reg sdp_b2mcif_rd_cdt_src_lat_fifo_pop_d1; +wire [513:0] cvif2sdp_b_rd_rsp_src_pd_d0; +wire [513:0] cvif2sdp_b_rd_rsp_src_pd_d1; +wire cvif2sdp_b_rd_rsp_src_ready_d0; +wire cvif2sdp_b_rd_rsp_src_ready_d1; +wire cvif2sdp_b_rd_rsp_src_valid_d0; +wire cvif2sdp_b_rd_rsp_src_valid_d1; +wire [513:0] cvif2sdp_rd_rsp_src_pd_d0; +wire [513:0] cvif2sdp_rd_rsp_src_pd_d1; +wire cvif2sdp_rd_rsp_src_ready_d0; +wire cvif2sdp_rd_rsp_src_ready_d1; +wire cvif2sdp_rd_rsp_src_valid_d0; +wire cvif2sdp_rd_rsp_src_valid_d1; +wire [513:0] mcif2sdp_b_rd_rsp_src_pd_d0; +wire [513:0] mcif2sdp_b_rd_rsp_src_pd_d1; +wire mcif2sdp_b_rd_rsp_src_ready_d0; +wire mcif2sdp_b_rd_rsp_src_ready_d1; +wire mcif2sdp_b_rd_rsp_src_valid_d0; +wire mcif2sdp_b_rd_rsp_src_valid_d1; +wire [513:0] mcif2sdp_rd_rsp_src_pd_d0; +wire [513:0] mcif2sdp_rd_rsp_src_pd_d1; +wire mcif2sdp_rd_rsp_src_ready_d0; +wire mcif2sdp_rd_rsp_src_ready_d1; +wire mcif2sdp_rd_rsp_src_valid_d0; +wire mcif2sdp_rd_rsp_src_valid_d1; +wire [78:0] sdp2cvif_rd_req_src_pd_d0; +wire [78:0] sdp2cvif_rd_req_src_pd_d1; +wire sdp2cvif_rd_req_src_ready_d0; +wire sdp2cvif_rd_req_src_ready_d1; +wire sdp2cvif_rd_req_src_valid_d0; +wire sdp2cvif_rd_req_src_valid_d1; +wire [78:0] sdp2mcif_rd_req_src_pd_d0; +wire [78:0] sdp2mcif_rd_req_src_pd_d1; +wire sdp2mcif_rd_req_src_ready_d0; +wire sdp2mcif_rd_req_src_ready_d1; +wire sdp2mcif_rd_req_src_valid_d0; +wire sdp2mcif_rd_req_src_valid_d1; +wire [78:0] sdp_b2cvif_rd_req_src_pd_d0; +wire [78:0] sdp_b2cvif_rd_req_src_pd_d1; +wire sdp_b2cvif_rd_req_src_ready_d0; +wire sdp_b2cvif_rd_req_src_ready_d1; +wire sdp_b2cvif_rd_req_src_valid_d0; +wire sdp_b2cvif_rd_req_src_valid_d1; +wire [78:0] sdp_b2mcif_rd_req_src_pd_d0; +wire [78:0] sdp_b2mcif_rd_req_src_pd_d1; +wire sdp_b2mcif_rd_req_src_ready_d0; +wire sdp_b2mcif_rd_req_src_ready_d1; +wire sdp_b2mcif_rd_req_src_valid_d0; +wire sdp_b2mcif_rd_req_src_valid_d1; +// Valid Ready Pipe +assign sdp2mcif_rd_req_src_valid_d0 = sdp2mcif_rd_req_src_valid; +assign sdp2mcif_rd_req_src_ready = sdp2mcif_rd_req_src_ready_d0; +assign sdp2mcif_rd_req_src_pd_d0[78:0] = sdp2mcif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_req_src_pd_d0 (sdp2mcif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp2mcif_rd_req_src_ready_d1 (sdp2mcif_rd_req_src_ready_d1) //|< w + ,.sdp2mcif_rd_req_src_valid_d0 (sdp2mcif_rd_req_src_valid_d0) //|< w + ,.sdp2mcif_rd_req_src_pd_d1 (sdp2mcif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp2mcif_rd_req_src_ready_d0 (sdp2mcif_rd_req_src_ready_d0) //|> w + ,.sdp2mcif_rd_req_src_valid_d1 (sdp2mcif_rd_req_src_valid_d1) //|> w + ); +assign sdp2mcif_rd_req_dst_valid = sdp2mcif_rd_req_src_valid_d1; +assign sdp2mcif_rd_req_src_ready_d1 = sdp2mcif_rd_req_dst_ready; +assign sdp2mcif_rd_req_dst_pd[78:0] = sdp2mcif_rd_req_src_pd_d1[78:0]; +assign mcif2sdp_b_rd_rsp_src_valid_d0 = mcif2sdp_b_rd_rsp_src_valid; +assign mcif2sdp_b_rd_rsp_src_ready = mcif2sdp_b_rd_rsp_src_ready_d0; +assign mcif2sdp_b_rd_rsp_src_pd_d0[513:0] = mcif2sdp_b_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2sdp_b_rd_rsp_src_pd_d0 (mcif2sdp_b_rd_rsp_src_pd_d0[513:0]) //|< w + ,.mcif2sdp_b_rd_rsp_src_ready_d1 (mcif2sdp_b_rd_rsp_src_ready_d1) //|< w + ,.mcif2sdp_b_rd_rsp_src_valid_d0 (mcif2sdp_b_rd_rsp_src_valid_d0) //|< w + ,.mcif2sdp_b_rd_rsp_src_pd_d1 (mcif2sdp_b_rd_rsp_src_pd_d1[513:0]) //|> w + ,.mcif2sdp_b_rd_rsp_src_ready_d0 (mcif2sdp_b_rd_rsp_src_ready_d0) //|> w + ,.mcif2sdp_b_rd_rsp_src_valid_d1 (mcif2sdp_b_rd_rsp_src_valid_d1) //|> w + ); +assign mcif2sdp_b_rd_rsp_dst_valid = mcif2sdp_b_rd_rsp_src_valid_d1; +assign mcif2sdp_b_rd_rsp_src_ready_d1 = mcif2sdp_b_rd_rsp_dst_ready; +assign mcif2sdp_b_rd_rsp_dst_pd[513:0] = mcif2sdp_b_rd_rsp_src_pd_d1[513:0]; +assign sdp2cvif_rd_req_src_valid_d0 = sdp2cvif_rd_req_src_valid; +assign sdp2cvif_rd_req_src_ready = sdp2cvif_rd_req_src_ready_d0; +assign sdp2cvif_rd_req_src_pd_d0[78:0] = sdp2cvif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2cvif_rd_req_src_pd_d0 (sdp2cvif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp2cvif_rd_req_src_ready_d1 (sdp2cvif_rd_req_src_ready_d1) //|< w + ,.sdp2cvif_rd_req_src_valid_d0 (sdp2cvif_rd_req_src_valid_d0) //|< w + ,.sdp2cvif_rd_req_src_pd_d1 (sdp2cvif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp2cvif_rd_req_src_ready_d0 (sdp2cvif_rd_req_src_ready_d0) //|> w + ,.sdp2cvif_rd_req_src_valid_d1 (sdp2cvif_rd_req_src_valid_d1) //|> w + ); +assign sdp2cvif_rd_req_dst_valid = sdp2cvif_rd_req_src_valid_d1; +assign sdp2cvif_rd_req_src_ready_d1 = sdp2cvif_rd_req_dst_ready; +assign sdp2cvif_rd_req_dst_pd[78:0] = sdp2cvif_rd_req_src_pd_d1[78:0]; +assign sdp_b2mcif_rd_req_src_valid_d0 = sdp_b2mcif_rd_req_src_valid; +assign sdp_b2mcif_rd_req_src_ready = sdp_b2mcif_rd_req_src_ready_d0; +assign sdp_b2mcif_rd_req_src_pd_d0[78:0] = sdp_b2mcif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp_b2mcif_rd_req_src_pd_d0 (sdp_b2mcif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp_b2mcif_rd_req_src_ready_d1 (sdp_b2mcif_rd_req_src_ready_d1) //|< w + ,.sdp_b2mcif_rd_req_src_valid_d0 (sdp_b2mcif_rd_req_src_valid_d0) //|< w + ,.sdp_b2mcif_rd_req_src_pd_d1 (sdp_b2mcif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp_b2mcif_rd_req_src_ready_d0 (sdp_b2mcif_rd_req_src_ready_d0) //|> w + ,.sdp_b2mcif_rd_req_src_valid_d1 (sdp_b2mcif_rd_req_src_valid_d1) //|> w + ); +assign sdp_b2mcif_rd_req_dst_valid = sdp_b2mcif_rd_req_src_valid_d1; +assign sdp_b2mcif_rd_req_src_ready_d1 = sdp_b2mcif_rd_req_dst_ready; +assign sdp_b2mcif_rd_req_dst_pd[78:0] = sdp_b2mcif_rd_req_src_pd_d1[78:0]; +assign sdp_b2cvif_rd_req_src_valid_d0 = sdp_b2cvif_rd_req_src_valid; +assign sdp_b2cvif_rd_req_src_ready = sdp_b2cvif_rd_req_src_ready_d0; +assign sdp_b2cvif_rd_req_src_pd_d0[78:0] = sdp_b2cvif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp_b2cvif_rd_req_src_pd_d0 (sdp_b2cvif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp_b2cvif_rd_req_src_ready_d1 (sdp_b2cvif_rd_req_src_ready_d1) //|< w + ,.sdp_b2cvif_rd_req_src_valid_d0 (sdp_b2cvif_rd_req_src_valid_d0) //|< w + ,.sdp_b2cvif_rd_req_src_pd_d1 (sdp_b2cvif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp_b2cvif_rd_req_src_ready_d0 (sdp_b2cvif_rd_req_src_ready_d0) //|> w + ,.sdp_b2cvif_rd_req_src_valid_d1 (sdp_b2cvif_rd_req_src_valid_d1) //|> w + ); +assign sdp_b2cvif_rd_req_dst_valid = sdp_b2cvif_rd_req_src_valid_d1; +assign sdp_b2cvif_rd_req_src_ready_d1 = sdp_b2cvif_rd_req_dst_ready; +assign sdp_b2cvif_rd_req_dst_pd[78:0] = sdp_b2cvif_rd_req_src_pd_d1[78:0]; +assign cvif2sdp_b_rd_rsp_src_valid_d0 = cvif2sdp_b_rd_rsp_src_valid; +assign cvif2sdp_b_rd_rsp_src_ready = cvif2sdp_b_rd_rsp_src_ready_d0; +assign cvif2sdp_b_rd_rsp_src_pd_d0[513:0] = cvif2sdp_b_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvif2sdp_b_rd_rsp_src_pd_d0 (cvif2sdp_b_rd_rsp_src_pd_d0[513:0]) //|< w + ,.cvif2sdp_b_rd_rsp_src_ready_d1 (cvif2sdp_b_rd_rsp_src_ready_d1) //|< w + ,.cvif2sdp_b_rd_rsp_src_valid_d0 (cvif2sdp_b_rd_rsp_src_valid_d0) //|< w + ,.cvif2sdp_b_rd_rsp_src_pd_d1 (cvif2sdp_b_rd_rsp_src_pd_d1[513:0]) //|> w + ,.cvif2sdp_b_rd_rsp_src_ready_d0 (cvif2sdp_b_rd_rsp_src_ready_d0) //|> w + ,.cvif2sdp_b_rd_rsp_src_valid_d1 (cvif2sdp_b_rd_rsp_src_valid_d1) //|> w + ); +assign cvif2sdp_b_rd_rsp_dst_valid = cvif2sdp_b_rd_rsp_src_valid_d1; +assign cvif2sdp_b_rd_rsp_src_ready_d1 = cvif2sdp_b_rd_rsp_dst_ready; +assign cvif2sdp_b_rd_rsp_dst_pd[513:0] = cvif2sdp_b_rd_rsp_src_pd_d1[513:0]; +assign mcif2sdp_rd_rsp_src_valid_d0 = mcif2sdp_rd_rsp_src_valid; +assign mcif2sdp_rd_rsp_src_ready = mcif2sdp_rd_rsp_src_ready_d0; +assign mcif2sdp_rd_rsp_src_pd_d0[513:0] = mcif2sdp_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2sdp_rd_rsp_src_pd_d0 (mcif2sdp_rd_rsp_src_pd_d0[513:0]) //|< w + ,.mcif2sdp_rd_rsp_src_ready_d1 (mcif2sdp_rd_rsp_src_ready_d1) //|< w + ,.mcif2sdp_rd_rsp_src_valid_d0 (mcif2sdp_rd_rsp_src_valid_d0) //|< w + ,.mcif2sdp_rd_rsp_src_pd_d1 (mcif2sdp_rd_rsp_src_pd_d1[513:0]) //|> w + ,.mcif2sdp_rd_rsp_src_ready_d0 (mcif2sdp_rd_rsp_src_ready_d0) //|> w + ,.mcif2sdp_rd_rsp_src_valid_d1 (mcif2sdp_rd_rsp_src_valid_d1) //|> w + ); +assign mcif2sdp_rd_rsp_dst_valid = mcif2sdp_rd_rsp_src_valid_d1; +assign mcif2sdp_rd_rsp_src_ready_d1 = mcif2sdp_rd_rsp_dst_ready; +assign mcif2sdp_rd_rsp_dst_pd[513:0] = mcif2sdp_rd_rsp_src_pd_d1[513:0]; +assign cvif2sdp_rd_rsp_src_valid_d0 = cvif2sdp_rd_rsp_src_valid; +assign cvif2sdp_rd_rsp_src_ready = cvif2sdp_rd_rsp_src_ready_d0; +assign cvif2sdp_rd_rsp_src_pd_d0[513:0] = cvif2sdp_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p8 pipe_p8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvif2sdp_rd_rsp_src_pd_d0 (cvif2sdp_rd_rsp_src_pd_d0[513:0]) //|< w + ,.cvif2sdp_rd_rsp_src_ready_d1 (cvif2sdp_rd_rsp_src_ready_d1) //|< w + ,.cvif2sdp_rd_rsp_src_valid_d0 (cvif2sdp_rd_rsp_src_valid_d0) //|< w + ,.cvif2sdp_rd_rsp_src_pd_d1 (cvif2sdp_rd_rsp_src_pd_d1[513:0]) //|> w + ,.cvif2sdp_rd_rsp_src_ready_d0 (cvif2sdp_rd_rsp_src_ready_d0) //|> w + ,.cvif2sdp_rd_rsp_src_valid_d1 (cvif2sdp_rd_rsp_src_valid_d1) //|> w + ); +assign cvif2sdp_rd_rsp_dst_valid = cvif2sdp_rd_rsp_src_valid_d1; +assign cvif2sdp_rd_rsp_src_ready_d1 = cvif2sdp_rd_rsp_dst_ready; +assign cvif2sdp_rd_rsp_dst_pd[513:0] = cvif2sdp_rd_rsp_src_pd_d1[513:0]; +// Valid Only Pipe +always @(posedge nvdla_core_clk) begin + sdp_b2cvif_rd_cdt_src_lat_fifo_pop_d1 <= sdp_b2cvif_rd_cdt_src_lat_fifo_pop; +end +assign sdp_b2cvif_rd_cdt_dst_lat_fifo_pop = sdp_b2cvif_rd_cdt_src_lat_fifo_pop_d1; +always @(posedge nvdla_core_clk) begin + sdp_b2mcif_rd_cdt_src_lat_fifo_pop_d1 <= sdp_b2mcif_rd_cdt_src_lat_fifo_pop; +end +assign sdp_b2mcif_rd_cdt_dst_lat_fifo_pop = sdp_b2mcif_rd_cdt_src_lat_fifo_pop_d1; +always @(posedge nvdla_core_clk) begin + sdp2mcif_rd_cdt_src_lat_fifo_pop_d1 <= sdp2mcif_rd_cdt_src_lat_fifo_pop; +end +assign sdp2mcif_rd_cdt_dst_lat_fifo_pop = sdp2mcif_rd_cdt_src_lat_fifo_pop_d1; +always @(posedge nvdla_core_clk) begin + sdp2cvif_rd_cdt_src_lat_fifo_pop_d1 <= sdp2cvif_rd_cdt_src_lat_fifo_pop; +end +assign sdp2cvif_rd_cdt_dst_lat_fifo_pop = sdp2cvif_rd_cdt_src_lat_fifo_pop_d1; +endmodule // NV_NVDLA_RT_sdp2nocif +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp2mcif_rd_req_src_pd_d1[78:0] (sdp2mcif_rd_req_src_valid_d1,sdp2mcif_rd_req_src_ready_d1) <= sdp2mcif_rd_req_src_pd_d0[78:0] (sdp2mcif_rd_req_src_valid_d0,sdp2mcif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp2mcif_rd_req_src_pd_d0 + ,sdp2mcif_rd_req_src_ready_d1 + ,sdp2mcif_rd_req_src_valid_d0 + ,sdp2mcif_rd_req_src_pd_d1 + ,sdp2mcif_rd_req_src_ready_d0 + ,sdp2mcif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp2mcif_rd_req_src_pd_d0; +input sdp2mcif_rd_req_src_ready_d1; +input sdp2mcif_rd_req_src_valid_d0; +output [78:0] sdp2mcif_rd_req_src_pd_d1; +output sdp2mcif_rd_req_src_ready_d0; +output sdp2mcif_rd_req_src_valid_d1; +reg [78:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg [78:0] sdp2mcif_rd_req_src_pd_d1; +reg sdp2mcif_rd_req_src_ready_d0; +reg sdp2mcif_rd_req_src_valid_d1; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? sdp2mcif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && sdp2mcif_rd_req_src_valid_d0)? sdp2mcif_rd_req_src_pd_d0[78:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + sdp2mcif_rd_req_src_ready_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sdp2mcif_rd_req_src_ready_d1 + or p1_pipe_data + ) begin + sdp2mcif_rd_req_src_valid_d1 = p1_pipe_valid; + p1_pipe_ready = sdp2mcif_rd_req_src_ready_d1; + sdp2mcif_rd_req_src_pd_d1[78:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp2mcif_rd_req_src_valid_d1^sdp2mcif_rd_req_src_ready_d1^sdp2mcif_rd_req_src_valid_d0^sdp2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (sdp2mcif_rd_req_src_valid_d0 && !sdp2mcif_rd_req_src_ready_d0), (sdp2mcif_rd_req_src_valid_d0), (sdp2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none mcif2sdp_b_rd_rsp_src_pd_d1[513:0] (mcif2sdp_b_rd_rsp_src_valid_d1,mcif2sdp_b_rd_rsp_src_ready_d1) <= mcif2sdp_b_rd_rsp_src_pd_d0[513:0] (mcif2sdp_b_rd_rsp_src_valid_d0,mcif2sdp_b_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mcif2sdp_b_rd_rsp_src_pd_d0 + ,mcif2sdp_b_rd_rsp_src_ready_d1 + ,mcif2sdp_b_rd_rsp_src_valid_d0 + ,mcif2sdp_b_rd_rsp_src_pd_d1 + ,mcif2sdp_b_rd_rsp_src_ready_d0 + ,mcif2sdp_b_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mcif2sdp_b_rd_rsp_src_pd_d0; +input mcif2sdp_b_rd_rsp_src_ready_d1; +input mcif2sdp_b_rd_rsp_src_valid_d0; +output [513:0] mcif2sdp_b_rd_rsp_src_pd_d1; +output mcif2sdp_b_rd_rsp_src_ready_d0; +output mcif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] mcif2sdp_b_rd_rsp_src_pd_d1; +reg mcif2sdp_b_rd_rsp_src_ready_d0; +reg mcif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? mcif2sdp_b_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && mcif2sdp_b_rd_rsp_src_valid_d0)? mcif2sdp_b_rd_rsp_src_pd_d0[513:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + mcif2sdp_b_rd_rsp_src_ready_d0 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mcif2sdp_b_rd_rsp_src_ready_d1 + or p2_pipe_data + ) begin + mcif2sdp_b_rd_rsp_src_valid_d1 = p2_pipe_valid; + p2_pipe_ready = mcif2sdp_b_rd_rsp_src_ready_d1; + mcif2sdp_b_rd_rsp_src_pd_d1[513:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2sdp_b_rd_rsp_src_valid_d1^mcif2sdp_b_rd_rsp_src_ready_d1^mcif2sdp_b_rd_rsp_src_valid_d0^mcif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mcif2sdp_b_rd_rsp_src_valid_d0 && !mcif2sdp_b_rd_rsp_src_ready_d0), (mcif2sdp_b_rd_rsp_src_valid_d0), (mcif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp2cvif_rd_req_src_pd_d1[78:0] (sdp2cvif_rd_req_src_valid_d1,sdp2cvif_rd_req_src_ready_d1) <= sdp2cvif_rd_req_src_pd_d0[78:0] (sdp2cvif_rd_req_src_valid_d0,sdp2cvif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp2cvif_rd_req_src_pd_d0 + ,sdp2cvif_rd_req_src_ready_d1 + ,sdp2cvif_rd_req_src_valid_d0 + ,sdp2cvif_rd_req_src_pd_d1 + ,sdp2cvif_rd_req_src_ready_d0 + ,sdp2cvif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp2cvif_rd_req_src_pd_d0; +input sdp2cvif_rd_req_src_ready_d1; +input sdp2cvif_rd_req_src_valid_d0; +output [78:0] sdp2cvif_rd_req_src_pd_d1; +output sdp2cvif_rd_req_src_ready_d0; +output sdp2cvif_rd_req_src_valid_d1; +reg [78:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg [78:0] sdp2cvif_rd_req_src_pd_d1; +reg sdp2cvif_rd_req_src_ready_d0; +reg sdp2cvif_rd_req_src_valid_d1; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? sdp2cvif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && sdp2cvif_rd_req_src_valid_d0)? sdp2cvif_rd_req_src_pd_d0[78:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + sdp2cvif_rd_req_src_ready_d0 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or sdp2cvif_rd_req_src_ready_d1 + or p3_pipe_data + ) begin + sdp2cvif_rd_req_src_valid_d1 = p3_pipe_valid; + p3_pipe_ready = sdp2cvif_rd_req_src_ready_d1; + sdp2cvif_rd_req_src_pd_d1[78:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp2cvif_rd_req_src_valid_d1^sdp2cvif_rd_req_src_ready_d1^sdp2cvif_rd_req_src_valid_d0^sdp2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (sdp2cvif_rd_req_src_valid_d0 && !sdp2cvif_rd_req_src_ready_d0), (sdp2cvif_rd_req_src_valid_d0), (sdp2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp_b2mcif_rd_req_src_pd_d1[78:0] (sdp_b2mcif_rd_req_src_valid_d1,sdp_b2mcif_rd_req_src_ready_d1) <= sdp_b2mcif_rd_req_src_pd_d0[78:0] (sdp_b2mcif_rd_req_src_valid_d0,sdp_b2mcif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp_b2mcif_rd_req_src_pd_d0 + ,sdp_b2mcif_rd_req_src_ready_d1 + ,sdp_b2mcif_rd_req_src_valid_d0 + ,sdp_b2mcif_rd_req_src_pd_d1 + ,sdp_b2mcif_rd_req_src_ready_d0 + ,sdp_b2mcif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp_b2mcif_rd_req_src_pd_d0; +input sdp_b2mcif_rd_req_src_ready_d1; +input sdp_b2mcif_rd_req_src_valid_d0; +output [78:0] sdp_b2mcif_rd_req_src_pd_d1; +output sdp_b2mcif_rd_req_src_ready_d0; +output sdp_b2mcif_rd_req_src_valid_d1; +reg [78:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg [78:0] sdp_b2mcif_rd_req_src_pd_d1; +reg sdp_b2mcif_rd_req_src_ready_d0; +reg sdp_b2mcif_rd_req_src_valid_d1; +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? sdp_b2mcif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && sdp_b2mcif_rd_req_src_valid_d0)? sdp_b2mcif_rd_req_src_pd_d0[78:0] : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + sdp_b2mcif_rd_req_src_ready_d0 = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or sdp_b2mcif_rd_req_src_ready_d1 + or p4_pipe_data + ) begin + sdp_b2mcif_rd_req_src_valid_d1 = p4_pipe_valid; + p4_pipe_ready = sdp_b2mcif_rd_req_src_ready_d1; + sdp_b2mcif_rd_req_src_pd_d1[78:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp_b2mcif_rd_req_src_valid_d1^sdp_b2mcif_rd_req_src_ready_d1^sdp_b2mcif_rd_req_src_valid_d0^sdp_b2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (sdp_b2mcif_rd_req_src_valid_d0 && !sdp_b2mcif_rd_req_src_ready_d0), (sdp_b2mcif_rd_req_src_valid_d0), (sdp_b2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp_b2cvif_rd_req_src_pd_d1[78:0] (sdp_b2cvif_rd_req_src_valid_d1,sdp_b2cvif_rd_req_src_ready_d1) <= sdp_b2cvif_rd_req_src_pd_d0[78:0] (sdp_b2cvif_rd_req_src_valid_d0,sdp_b2cvif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp_b2cvif_rd_req_src_pd_d0 + ,sdp_b2cvif_rd_req_src_ready_d1 + ,sdp_b2cvif_rd_req_src_valid_d0 + ,sdp_b2cvif_rd_req_src_pd_d1 + ,sdp_b2cvif_rd_req_src_ready_d0 + ,sdp_b2cvif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp_b2cvif_rd_req_src_pd_d0; +input sdp_b2cvif_rd_req_src_ready_d1; +input sdp_b2cvif_rd_req_src_valid_d0; +output [78:0] sdp_b2cvif_rd_req_src_pd_d1; +output sdp_b2cvif_rd_req_src_ready_d0; +output sdp_b2cvif_rd_req_src_valid_d1; +reg [78:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg [78:0] sdp_b2cvif_rd_req_src_pd_d1; +reg sdp_b2cvif_rd_req_src_ready_d0; +reg sdp_b2cvif_rd_req_src_valid_d1; +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? sdp_b2cvif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && sdp_b2cvif_rd_req_src_valid_d0)? sdp_b2cvif_rd_req_src_pd_d0[78:0] : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + sdp_b2cvif_rd_req_src_ready_d0 = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or sdp_b2cvif_rd_req_src_ready_d1 + or p5_pipe_data + ) begin + sdp_b2cvif_rd_req_src_valid_d1 = p5_pipe_valid; + p5_pipe_ready = sdp_b2cvif_rd_req_src_ready_d1; + sdp_b2cvif_rd_req_src_pd_d1[78:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp_b2cvif_rd_req_src_valid_d1^sdp_b2cvif_rd_req_src_ready_d1^sdp_b2cvif_rd_req_src_valid_d0^sdp_b2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (sdp_b2cvif_rd_req_src_valid_d0 && !sdp_b2cvif_rd_req_src_ready_d0), (sdp_b2cvif_rd_req_src_valid_d0), (sdp_b2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none cvif2sdp_b_rd_rsp_src_pd_d1[513:0] (cvif2sdp_b_rd_rsp_src_valid_d1,cvif2sdp_b_rd_rsp_src_ready_d1) <= cvif2sdp_b_rd_rsp_src_pd_d0[513:0] (cvif2sdp_b_rd_rsp_src_valid_d0,cvif2sdp_b_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvif2sdp_b_rd_rsp_src_pd_d0 + ,cvif2sdp_b_rd_rsp_src_ready_d1 + ,cvif2sdp_b_rd_rsp_src_valid_d0 + ,cvif2sdp_b_rd_rsp_src_pd_d1 + ,cvif2sdp_b_rd_rsp_src_ready_d0 + ,cvif2sdp_b_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] cvif2sdp_b_rd_rsp_src_pd_d0; +input cvif2sdp_b_rd_rsp_src_ready_d1; +input cvif2sdp_b_rd_rsp_src_valid_d0; +output [513:0] cvif2sdp_b_rd_rsp_src_pd_d1; +output cvif2sdp_b_rd_rsp_src_ready_d0; +output cvif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] cvif2sdp_b_rd_rsp_src_pd_d1; +reg cvif2sdp_b_rd_rsp_src_ready_d0; +reg cvif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? cvif2sdp_b_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && cvif2sdp_b_rd_rsp_src_valid_d0)? cvif2sdp_b_rd_rsp_src_pd_d0[513:0] : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + cvif2sdp_b_rd_rsp_src_ready_d0 = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or cvif2sdp_b_rd_rsp_src_ready_d1 + or p6_pipe_data + ) begin + cvif2sdp_b_rd_rsp_src_valid_d1 = p6_pipe_valid; + p6_pipe_ready = cvif2sdp_b_rd_rsp_src_ready_d1; + cvif2sdp_b_rd_rsp_src_pd_d1[513:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvif2sdp_b_rd_rsp_src_valid_d1^cvif2sdp_b_rd_rsp_src_ready_d1^cvif2sdp_b_rd_rsp_src_valid_d0^cvif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (cvif2sdp_b_rd_rsp_src_valid_d0 && !cvif2sdp_b_rd_rsp_src_ready_d0), (cvif2sdp_b_rd_rsp_src_valid_d0), (cvif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none mcif2sdp_rd_rsp_src_pd_d1[513:0] (mcif2sdp_rd_rsp_src_valid_d1,mcif2sdp_rd_rsp_src_ready_d1) <= mcif2sdp_rd_rsp_src_pd_d0[513:0] (mcif2sdp_rd_rsp_src_valid_d0,mcif2sdp_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mcif2sdp_rd_rsp_src_pd_d0 + ,mcif2sdp_rd_rsp_src_ready_d1 + ,mcif2sdp_rd_rsp_src_valid_d0 + ,mcif2sdp_rd_rsp_src_pd_d1 + ,mcif2sdp_rd_rsp_src_ready_d0 + ,mcif2sdp_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mcif2sdp_rd_rsp_src_pd_d0; +input mcif2sdp_rd_rsp_src_ready_d1; +input mcif2sdp_rd_rsp_src_valid_d0; +output [513:0] mcif2sdp_rd_rsp_src_pd_d1; +output mcif2sdp_rd_rsp_src_ready_d0; +output mcif2sdp_rd_rsp_src_valid_d1; +reg [513:0] mcif2sdp_rd_rsp_src_pd_d1; +reg mcif2sdp_rd_rsp_src_ready_d0; +reg mcif2sdp_rd_rsp_src_valid_d1; +reg [513:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? mcif2sdp_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && mcif2sdp_rd_rsp_src_valid_d0)? mcif2sdp_rd_rsp_src_pd_d0[513:0] : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + mcif2sdp_rd_rsp_src_ready_d0 = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or mcif2sdp_rd_rsp_src_ready_d1 + or p7_pipe_data + ) begin + mcif2sdp_rd_rsp_src_valid_d1 = p7_pipe_valid; + p7_pipe_ready = mcif2sdp_rd_rsp_src_ready_d1; + mcif2sdp_rd_rsp_src_pd_d1[513:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2sdp_rd_rsp_src_valid_d1^mcif2sdp_rd_rsp_src_ready_d1^mcif2sdp_rd_rsp_src_valid_d0^mcif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (mcif2sdp_rd_rsp_src_valid_d0 && !mcif2sdp_rd_rsp_src_ready_d0), (mcif2sdp_rd_rsp_src_valid_d0), (mcif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p7 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none cvif2sdp_rd_rsp_src_pd_d1[513:0] (cvif2sdp_rd_rsp_src_valid_d1,cvif2sdp_rd_rsp_src_ready_d1) <= cvif2sdp_rd_rsp_src_pd_d0[513:0] (cvif2sdp_rd_rsp_src_valid_d0,cvif2sdp_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvif2sdp_rd_rsp_src_pd_d0 + ,cvif2sdp_rd_rsp_src_ready_d1 + ,cvif2sdp_rd_rsp_src_valid_d0 + ,cvif2sdp_rd_rsp_src_pd_d1 + ,cvif2sdp_rd_rsp_src_ready_d0 + ,cvif2sdp_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] cvif2sdp_rd_rsp_src_pd_d0; +input cvif2sdp_rd_rsp_src_ready_d1; +input cvif2sdp_rd_rsp_src_valid_d0; +output [513:0] cvif2sdp_rd_rsp_src_pd_d1; +output cvif2sdp_rd_rsp_src_ready_d0; +output cvif2sdp_rd_rsp_src_valid_d1; +reg [513:0] cvif2sdp_rd_rsp_src_pd_d1; +reg cvif2sdp_rd_rsp_src_ready_d0; +reg cvif2sdp_rd_rsp_src_valid_d1; +reg [513:0] p8_pipe_data; +reg p8_pipe_ready; +reg p8_pipe_ready_bc; +reg p8_pipe_valid; +//## pipe (8) valid-ready-bubble-collapse +always @( + p8_pipe_ready + or p8_pipe_valid + ) begin + p8_pipe_ready_bc = p8_pipe_ready || !p8_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_pipe_valid <= 1'b0; + end else begin + p8_pipe_valid <= (p8_pipe_ready_bc)? cvif2sdp_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_pipe_data <= (p8_pipe_ready_bc && cvif2sdp_rd_rsp_src_valid_d0)? cvif2sdp_rd_rsp_src_pd_d0[513:0] : p8_pipe_data; +// VCS sop_coverage_off end +end +always @( + p8_pipe_ready_bc + ) begin + cvif2sdp_rd_rsp_src_ready_d0 = p8_pipe_ready_bc; +end +//## pipe (8) output +always @( + p8_pipe_valid + or cvif2sdp_rd_rsp_src_ready_d1 + or p8_pipe_data + ) begin + cvif2sdp_rd_rsp_src_valid_d1 = p8_pipe_valid; + p8_pipe_ready = cvif2sdp_rd_rsp_src_ready_d1; + cvif2sdp_rd_rsp_src_pd_d1[513:0] = p8_pipe_data; +end +//## pipe (8) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p8_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvif2sdp_rd_rsp_src_valid_d1^cvif2sdp_rd_rsp_src_ready_d1^cvif2sdp_rd_rsp_src_valid_d0^cvif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (cvif2sdp_rd_rsp_src_valid_d0 && !cvif2sdp_rd_rsp_src_ready_d0), (cvif2sdp_rd_rsp_src_valid_d0), (cvif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p8 diff --git a/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_sdp2nocif.v.vcp b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_sdp2nocif.v.vcp new file mode 100644 index 0000000..7c6cf17 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/retiming/NV_NVDLA_RT_sdp2nocif.v.vcp @@ -0,0 +1,1600 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RT_sdp2nocif.v +module NV_NVDLA_RT_sdp2nocif ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sdp2mcif_rd_req_src_valid //|< i + ,sdp2mcif_rd_req_src_ready //|> o + ,sdp2mcif_rd_req_src_pd //|< i + ,sdp2mcif_rd_req_dst_valid //|> o + ,sdp2mcif_rd_req_dst_ready //|< i + ,sdp2mcif_rd_req_dst_pd //|> o + ,sdp2cvif_rd_req_src_valid //|< i + ,sdp2cvif_rd_req_src_ready //|> o + ,sdp2cvif_rd_req_src_pd //|< i + ,sdp2cvif_rd_req_dst_valid //|> o + ,sdp2cvif_rd_req_dst_ready //|< i + ,sdp2cvif_rd_req_dst_pd //|> o + ,sdp2mcif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp2mcif_rd_cdt_dst_lat_fifo_pop //|> o + ,sdp2cvif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp2cvif_rd_cdt_dst_lat_fifo_pop //|> o + ,mcif2sdp_rd_rsp_src_valid //|< i + ,mcif2sdp_rd_rsp_src_ready //|> o + ,mcif2sdp_rd_rsp_src_pd //|< i + ,mcif2sdp_rd_rsp_dst_valid //|> o + ,mcif2sdp_rd_rsp_dst_ready //|< i + ,mcif2sdp_rd_rsp_dst_pd //|> o + ,cvif2sdp_rd_rsp_src_valid //|< i + ,cvif2sdp_rd_rsp_src_ready //|> o + ,cvif2sdp_rd_rsp_src_pd //|< i + ,cvif2sdp_rd_rsp_dst_valid //|> o + ,cvif2sdp_rd_rsp_dst_ready //|< i + ,cvif2sdp_rd_rsp_dst_pd //|> o + ,sdp_b2mcif_rd_req_src_valid //|< i + ,sdp_b2mcif_rd_req_src_ready //|> o + ,sdp_b2mcif_rd_req_src_pd //|< i + ,sdp_b2mcif_rd_req_dst_valid //|> o + ,sdp_b2mcif_rd_req_dst_ready //|< i + ,sdp_b2mcif_rd_req_dst_pd //|> o + ,sdp_b2cvif_rd_req_src_valid //|< i + ,sdp_b2cvif_rd_req_src_ready //|> o + ,sdp_b2cvif_rd_req_src_pd //|< i + ,sdp_b2cvif_rd_req_dst_valid //|> o + ,sdp_b2cvif_rd_req_dst_ready //|< i + ,sdp_b2cvif_rd_req_dst_pd //|> o + ,sdp_b2mcif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp_b2mcif_rd_cdt_dst_lat_fifo_pop //|> o + ,sdp_b2cvif_rd_cdt_src_lat_fifo_pop //|< i + ,sdp_b2cvif_rd_cdt_dst_lat_fifo_pop //|> o + ,mcif2sdp_b_rd_rsp_src_valid //|< i + ,mcif2sdp_b_rd_rsp_src_ready //|> o + ,mcif2sdp_b_rd_rsp_src_pd //|< i + ,mcif2sdp_b_rd_rsp_dst_valid //|> o + ,mcif2sdp_b_rd_rsp_dst_ready //|< i + ,mcif2sdp_b_rd_rsp_dst_pd //|> o + ,cvif2sdp_b_rd_rsp_src_valid //|< i + ,cvif2sdp_b_rd_rsp_src_ready //|> o + ,cvif2sdp_b_rd_rsp_src_pd //|< i + ,cvif2sdp_b_rd_rsp_dst_valid //|> o + ,cvif2sdp_b_rd_rsp_dst_ready //|< i + ,cvif2sdp_b_rd_rsp_dst_pd //|> o + ); +// +// NV_NVDLA_RT_sdp2nocif_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sdp2mcif_rd_req_src_valid; /* data valid */ +output sdp2mcif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp2mcif_rd_req_src_pd; +output sdp2mcif_rd_req_dst_valid; /* data valid */ +input sdp2mcif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp2mcif_rd_req_dst_pd; +input sdp2cvif_rd_req_src_valid; /* data valid */ +output sdp2cvif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp2cvif_rd_req_src_pd; +output sdp2cvif_rd_req_dst_valid; /* data valid */ +input sdp2cvif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp2cvif_rd_req_dst_pd; +input sdp2mcif_rd_cdt_src_lat_fifo_pop; +output sdp2mcif_rd_cdt_dst_lat_fifo_pop; +input sdp2cvif_rd_cdt_src_lat_fifo_pop; +output sdp2cvif_rd_cdt_dst_lat_fifo_pop; +input mcif2sdp_rd_rsp_src_valid; /* data valid */ +output mcif2sdp_rd_rsp_src_ready; /* data return handshake */ +input [513:0] mcif2sdp_rd_rsp_src_pd; +output mcif2sdp_rd_rsp_dst_valid; /* data valid */ +input mcif2sdp_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] mcif2sdp_rd_rsp_dst_pd; +input cvif2sdp_rd_rsp_src_valid; /* data valid */ +output cvif2sdp_rd_rsp_src_ready; /* data return handshake */ +input [513:0] cvif2sdp_rd_rsp_src_pd; +output cvif2sdp_rd_rsp_dst_valid; /* data valid */ +input cvif2sdp_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] cvif2sdp_rd_rsp_dst_pd; +input sdp_b2mcif_rd_req_src_valid; /* data valid */ +output sdp_b2mcif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp_b2mcif_rd_req_src_pd; +output sdp_b2mcif_rd_req_dst_valid; /* data valid */ +input sdp_b2mcif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp_b2mcif_rd_req_dst_pd; +input sdp_b2cvif_rd_req_src_valid; /* data valid */ +output sdp_b2cvif_rd_req_src_ready; /* data return handshake */ +input [78:0] sdp_b2cvif_rd_req_src_pd; +output sdp_b2cvif_rd_req_dst_valid; /* data valid */ +input sdp_b2cvif_rd_req_dst_ready; /* data return handshake */ +output [78:0] sdp_b2cvif_rd_req_dst_pd; +input sdp_b2mcif_rd_cdt_src_lat_fifo_pop; +output sdp_b2mcif_rd_cdt_dst_lat_fifo_pop; +input sdp_b2cvif_rd_cdt_src_lat_fifo_pop; +output sdp_b2cvif_rd_cdt_dst_lat_fifo_pop; +input mcif2sdp_b_rd_rsp_src_valid; /* data valid */ +output mcif2sdp_b_rd_rsp_src_ready; /* data return handshake */ +input [513:0] mcif2sdp_b_rd_rsp_src_pd; +output mcif2sdp_b_rd_rsp_dst_valid; /* data valid */ +input mcif2sdp_b_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] mcif2sdp_b_rd_rsp_dst_pd; +input cvif2sdp_b_rd_rsp_src_valid; /* data valid */ +output cvif2sdp_b_rd_rsp_src_ready; /* data return handshake */ +input [513:0] cvif2sdp_b_rd_rsp_src_pd; +output cvif2sdp_b_rd_rsp_dst_valid; /* data valid */ +input cvif2sdp_b_rd_rsp_dst_ready; /* data return handshake */ +output [513:0] cvif2sdp_b_rd_rsp_dst_pd; +reg sdp2cvif_rd_cdt_src_lat_fifo_pop_d1; +reg sdp2mcif_rd_cdt_src_lat_fifo_pop_d1; +reg sdp_b2cvif_rd_cdt_src_lat_fifo_pop_d1; +reg sdp_b2mcif_rd_cdt_src_lat_fifo_pop_d1; +wire [513:0] cvif2sdp_b_rd_rsp_src_pd_d0; +wire [513:0] cvif2sdp_b_rd_rsp_src_pd_d1; +wire cvif2sdp_b_rd_rsp_src_ready_d0; +wire cvif2sdp_b_rd_rsp_src_ready_d1; +wire cvif2sdp_b_rd_rsp_src_valid_d0; +wire cvif2sdp_b_rd_rsp_src_valid_d1; +wire [513:0] cvif2sdp_rd_rsp_src_pd_d0; +wire [513:0] cvif2sdp_rd_rsp_src_pd_d1; +wire cvif2sdp_rd_rsp_src_ready_d0; +wire cvif2sdp_rd_rsp_src_ready_d1; +wire cvif2sdp_rd_rsp_src_valid_d0; +wire cvif2sdp_rd_rsp_src_valid_d1; +wire [513:0] mcif2sdp_b_rd_rsp_src_pd_d0; +wire [513:0] mcif2sdp_b_rd_rsp_src_pd_d1; +wire mcif2sdp_b_rd_rsp_src_ready_d0; +wire mcif2sdp_b_rd_rsp_src_ready_d1; +wire mcif2sdp_b_rd_rsp_src_valid_d0; +wire mcif2sdp_b_rd_rsp_src_valid_d1; +wire [513:0] mcif2sdp_rd_rsp_src_pd_d0; +wire [513:0] mcif2sdp_rd_rsp_src_pd_d1; +wire mcif2sdp_rd_rsp_src_ready_d0; +wire mcif2sdp_rd_rsp_src_ready_d1; +wire mcif2sdp_rd_rsp_src_valid_d0; +wire mcif2sdp_rd_rsp_src_valid_d1; +wire [78:0] sdp2cvif_rd_req_src_pd_d0; +wire [78:0] sdp2cvif_rd_req_src_pd_d1; +wire sdp2cvif_rd_req_src_ready_d0; +wire sdp2cvif_rd_req_src_ready_d1; +wire sdp2cvif_rd_req_src_valid_d0; +wire sdp2cvif_rd_req_src_valid_d1; +wire [78:0] sdp2mcif_rd_req_src_pd_d0; +wire [78:0] sdp2mcif_rd_req_src_pd_d1; +wire sdp2mcif_rd_req_src_ready_d0; +wire sdp2mcif_rd_req_src_ready_d1; +wire sdp2mcif_rd_req_src_valid_d0; +wire sdp2mcif_rd_req_src_valid_d1; +wire [78:0] sdp_b2cvif_rd_req_src_pd_d0; +wire [78:0] sdp_b2cvif_rd_req_src_pd_d1; +wire sdp_b2cvif_rd_req_src_ready_d0; +wire sdp_b2cvif_rd_req_src_ready_d1; +wire sdp_b2cvif_rd_req_src_valid_d0; +wire sdp_b2cvif_rd_req_src_valid_d1; +wire [78:0] sdp_b2mcif_rd_req_src_pd_d0; +wire [78:0] sdp_b2mcif_rd_req_src_pd_d1; +wire sdp_b2mcif_rd_req_src_ready_d0; +wire sdp_b2mcif_rd_req_src_ready_d1; +wire sdp_b2mcif_rd_req_src_valid_d0; +wire sdp_b2mcif_rd_req_src_valid_d1; +// Valid Ready Pipe +assign sdp2mcif_rd_req_src_valid_d0 = sdp2mcif_rd_req_src_valid; +assign sdp2mcif_rd_req_src_ready = sdp2mcif_rd_req_src_ready_d0; +assign sdp2mcif_rd_req_src_pd_d0[78:0] = sdp2mcif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_req_src_pd_d0 (sdp2mcif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp2mcif_rd_req_src_ready_d1 (sdp2mcif_rd_req_src_ready_d1) //|< w + ,.sdp2mcif_rd_req_src_valid_d0 (sdp2mcif_rd_req_src_valid_d0) //|< w + ,.sdp2mcif_rd_req_src_pd_d1 (sdp2mcif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp2mcif_rd_req_src_ready_d0 (sdp2mcif_rd_req_src_ready_d0) //|> w + ,.sdp2mcif_rd_req_src_valid_d1 (sdp2mcif_rd_req_src_valid_d1) //|> w + ); +assign sdp2mcif_rd_req_dst_valid = sdp2mcif_rd_req_src_valid_d1; +assign sdp2mcif_rd_req_src_ready_d1 = sdp2mcif_rd_req_dst_ready; +assign sdp2mcif_rd_req_dst_pd[78:0] = sdp2mcif_rd_req_src_pd_d1[78:0]; +assign mcif2sdp_b_rd_rsp_src_valid_d0 = mcif2sdp_b_rd_rsp_src_valid; +assign mcif2sdp_b_rd_rsp_src_ready = mcif2sdp_b_rd_rsp_src_ready_d0; +assign mcif2sdp_b_rd_rsp_src_pd_d0[513:0] = mcif2sdp_b_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2sdp_b_rd_rsp_src_pd_d0 (mcif2sdp_b_rd_rsp_src_pd_d0[513:0]) //|< w + ,.mcif2sdp_b_rd_rsp_src_ready_d1 (mcif2sdp_b_rd_rsp_src_ready_d1) //|< w + ,.mcif2sdp_b_rd_rsp_src_valid_d0 (mcif2sdp_b_rd_rsp_src_valid_d0) //|< w + ,.mcif2sdp_b_rd_rsp_src_pd_d1 (mcif2sdp_b_rd_rsp_src_pd_d1[513:0]) //|> w + ,.mcif2sdp_b_rd_rsp_src_ready_d0 (mcif2sdp_b_rd_rsp_src_ready_d0) //|> w + ,.mcif2sdp_b_rd_rsp_src_valid_d1 (mcif2sdp_b_rd_rsp_src_valid_d1) //|> w + ); +assign mcif2sdp_b_rd_rsp_dst_valid = mcif2sdp_b_rd_rsp_src_valid_d1; +assign mcif2sdp_b_rd_rsp_src_ready_d1 = mcif2sdp_b_rd_rsp_dst_ready; +assign mcif2sdp_b_rd_rsp_dst_pd[513:0] = mcif2sdp_b_rd_rsp_src_pd_d1[513:0]; +assign sdp2cvif_rd_req_src_valid_d0 = sdp2cvif_rd_req_src_valid; +assign sdp2cvif_rd_req_src_ready = sdp2cvif_rd_req_src_ready_d0; +assign sdp2cvif_rd_req_src_pd_d0[78:0] = sdp2cvif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2cvif_rd_req_src_pd_d0 (sdp2cvif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp2cvif_rd_req_src_ready_d1 (sdp2cvif_rd_req_src_ready_d1) //|< w + ,.sdp2cvif_rd_req_src_valid_d0 (sdp2cvif_rd_req_src_valid_d0) //|< w + ,.sdp2cvif_rd_req_src_pd_d1 (sdp2cvif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp2cvif_rd_req_src_ready_d0 (sdp2cvif_rd_req_src_ready_d0) //|> w + ,.sdp2cvif_rd_req_src_valid_d1 (sdp2cvif_rd_req_src_valid_d1) //|> w + ); +assign sdp2cvif_rd_req_dst_valid = sdp2cvif_rd_req_src_valid_d1; +assign sdp2cvif_rd_req_src_ready_d1 = sdp2cvif_rd_req_dst_ready; +assign sdp2cvif_rd_req_dst_pd[78:0] = sdp2cvif_rd_req_src_pd_d1[78:0]; +assign sdp_b2mcif_rd_req_src_valid_d0 = sdp_b2mcif_rd_req_src_valid; +assign sdp_b2mcif_rd_req_src_ready = sdp_b2mcif_rd_req_src_ready_d0; +assign sdp_b2mcif_rd_req_src_pd_d0[78:0] = sdp_b2mcif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp_b2mcif_rd_req_src_pd_d0 (sdp_b2mcif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp_b2mcif_rd_req_src_ready_d1 (sdp_b2mcif_rd_req_src_ready_d1) //|< w + ,.sdp_b2mcif_rd_req_src_valid_d0 (sdp_b2mcif_rd_req_src_valid_d0) //|< w + ,.sdp_b2mcif_rd_req_src_pd_d1 (sdp_b2mcif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp_b2mcif_rd_req_src_ready_d0 (sdp_b2mcif_rd_req_src_ready_d0) //|> w + ,.sdp_b2mcif_rd_req_src_valid_d1 (sdp_b2mcif_rd_req_src_valid_d1) //|> w + ); +assign sdp_b2mcif_rd_req_dst_valid = sdp_b2mcif_rd_req_src_valid_d1; +assign sdp_b2mcif_rd_req_src_ready_d1 = sdp_b2mcif_rd_req_dst_ready; +assign sdp_b2mcif_rd_req_dst_pd[78:0] = sdp_b2mcif_rd_req_src_pd_d1[78:0]; +assign sdp_b2cvif_rd_req_src_valid_d0 = sdp_b2cvif_rd_req_src_valid; +assign sdp_b2cvif_rd_req_src_ready = sdp_b2cvif_rd_req_src_ready_d0; +assign sdp_b2cvif_rd_req_src_pd_d0[78:0] = sdp_b2cvif_rd_req_src_pd[78:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp_b2cvif_rd_req_src_pd_d0 (sdp_b2cvif_rd_req_src_pd_d0[78:0]) //|< w + ,.sdp_b2cvif_rd_req_src_ready_d1 (sdp_b2cvif_rd_req_src_ready_d1) //|< w + ,.sdp_b2cvif_rd_req_src_valid_d0 (sdp_b2cvif_rd_req_src_valid_d0) //|< w + ,.sdp_b2cvif_rd_req_src_pd_d1 (sdp_b2cvif_rd_req_src_pd_d1[78:0]) //|> w + ,.sdp_b2cvif_rd_req_src_ready_d0 (sdp_b2cvif_rd_req_src_ready_d0) //|> w + ,.sdp_b2cvif_rd_req_src_valid_d1 (sdp_b2cvif_rd_req_src_valid_d1) //|> w + ); +assign sdp_b2cvif_rd_req_dst_valid = sdp_b2cvif_rd_req_src_valid_d1; +assign sdp_b2cvif_rd_req_src_ready_d1 = sdp_b2cvif_rd_req_dst_ready; +assign sdp_b2cvif_rd_req_dst_pd[78:0] = sdp_b2cvif_rd_req_src_pd_d1[78:0]; +assign cvif2sdp_b_rd_rsp_src_valid_d0 = cvif2sdp_b_rd_rsp_src_valid; +assign cvif2sdp_b_rd_rsp_src_ready = cvif2sdp_b_rd_rsp_src_ready_d0; +assign cvif2sdp_b_rd_rsp_src_pd_d0[513:0] = cvif2sdp_b_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvif2sdp_b_rd_rsp_src_pd_d0 (cvif2sdp_b_rd_rsp_src_pd_d0[513:0]) //|< w + ,.cvif2sdp_b_rd_rsp_src_ready_d1 (cvif2sdp_b_rd_rsp_src_ready_d1) //|< w + ,.cvif2sdp_b_rd_rsp_src_valid_d0 (cvif2sdp_b_rd_rsp_src_valid_d0) //|< w + ,.cvif2sdp_b_rd_rsp_src_pd_d1 (cvif2sdp_b_rd_rsp_src_pd_d1[513:0]) //|> w + ,.cvif2sdp_b_rd_rsp_src_ready_d0 (cvif2sdp_b_rd_rsp_src_ready_d0) //|> w + ,.cvif2sdp_b_rd_rsp_src_valid_d1 (cvif2sdp_b_rd_rsp_src_valid_d1) //|> w + ); +assign cvif2sdp_b_rd_rsp_dst_valid = cvif2sdp_b_rd_rsp_src_valid_d1; +assign cvif2sdp_b_rd_rsp_src_ready_d1 = cvif2sdp_b_rd_rsp_dst_ready; +assign cvif2sdp_b_rd_rsp_dst_pd[513:0] = cvif2sdp_b_rd_rsp_src_pd_d1[513:0]; +assign mcif2sdp_rd_rsp_src_valid_d0 = mcif2sdp_rd_rsp_src_valid; +assign mcif2sdp_rd_rsp_src_ready = mcif2sdp_rd_rsp_src_ready_d0; +assign mcif2sdp_rd_rsp_src_pd_d0[513:0] = mcif2sdp_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2sdp_rd_rsp_src_pd_d0 (mcif2sdp_rd_rsp_src_pd_d0[513:0]) //|< w + ,.mcif2sdp_rd_rsp_src_ready_d1 (mcif2sdp_rd_rsp_src_ready_d1) //|< w + ,.mcif2sdp_rd_rsp_src_valid_d0 (mcif2sdp_rd_rsp_src_valid_d0) //|< w + ,.mcif2sdp_rd_rsp_src_pd_d1 (mcif2sdp_rd_rsp_src_pd_d1[513:0]) //|> w + ,.mcif2sdp_rd_rsp_src_ready_d0 (mcif2sdp_rd_rsp_src_ready_d0) //|> w + ,.mcif2sdp_rd_rsp_src_valid_d1 (mcif2sdp_rd_rsp_src_valid_d1) //|> w + ); +assign mcif2sdp_rd_rsp_dst_valid = mcif2sdp_rd_rsp_src_valid_d1; +assign mcif2sdp_rd_rsp_src_ready_d1 = mcif2sdp_rd_rsp_dst_ready; +assign mcif2sdp_rd_rsp_dst_pd[513:0] = mcif2sdp_rd_rsp_src_pd_d1[513:0]; +assign cvif2sdp_rd_rsp_src_valid_d0 = cvif2sdp_rd_rsp_src_valid; +assign cvif2sdp_rd_rsp_src_ready = cvif2sdp_rd_rsp_src_ready_d0; +assign cvif2sdp_rd_rsp_src_pd_d0[513:0] = cvif2sdp_rd_rsp_src_pd[513:0]; +NV_NVDLA_RT_SDP2NOCIF_pipe_p8 pipe_p8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvif2sdp_rd_rsp_src_pd_d0 (cvif2sdp_rd_rsp_src_pd_d0[513:0]) //|< w + ,.cvif2sdp_rd_rsp_src_ready_d1 (cvif2sdp_rd_rsp_src_ready_d1) //|< w + ,.cvif2sdp_rd_rsp_src_valid_d0 (cvif2sdp_rd_rsp_src_valid_d0) //|< w + ,.cvif2sdp_rd_rsp_src_pd_d1 (cvif2sdp_rd_rsp_src_pd_d1[513:0]) //|> w + ,.cvif2sdp_rd_rsp_src_ready_d0 (cvif2sdp_rd_rsp_src_ready_d0) //|> w + ,.cvif2sdp_rd_rsp_src_valid_d1 (cvif2sdp_rd_rsp_src_valid_d1) //|> w + ); +assign cvif2sdp_rd_rsp_dst_valid = cvif2sdp_rd_rsp_src_valid_d1; +assign cvif2sdp_rd_rsp_src_ready_d1 = cvif2sdp_rd_rsp_dst_ready; +assign cvif2sdp_rd_rsp_dst_pd[513:0] = cvif2sdp_rd_rsp_src_pd_d1[513:0]; +// Valid Only Pipe +always @(posedge nvdla_core_clk) begin + sdp_b2cvif_rd_cdt_src_lat_fifo_pop_d1 <= sdp_b2cvif_rd_cdt_src_lat_fifo_pop; +end +assign sdp_b2cvif_rd_cdt_dst_lat_fifo_pop = sdp_b2cvif_rd_cdt_src_lat_fifo_pop_d1; +always @(posedge nvdla_core_clk) begin + sdp_b2mcif_rd_cdt_src_lat_fifo_pop_d1 <= sdp_b2mcif_rd_cdt_src_lat_fifo_pop; +end +assign sdp_b2mcif_rd_cdt_dst_lat_fifo_pop = sdp_b2mcif_rd_cdt_src_lat_fifo_pop_d1; +always @(posedge nvdla_core_clk) begin + sdp2mcif_rd_cdt_src_lat_fifo_pop_d1 <= sdp2mcif_rd_cdt_src_lat_fifo_pop; +end +assign sdp2mcif_rd_cdt_dst_lat_fifo_pop = sdp2mcif_rd_cdt_src_lat_fifo_pop_d1; +always @(posedge nvdla_core_clk) begin + sdp2cvif_rd_cdt_src_lat_fifo_pop_d1 <= sdp2cvif_rd_cdt_src_lat_fifo_pop; +end +assign sdp2cvif_rd_cdt_dst_lat_fifo_pop = sdp2cvif_rd_cdt_src_lat_fifo_pop_d1; +endmodule // NV_NVDLA_RT_sdp2nocif +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp2mcif_rd_req_src_pd_d1[78:0] (sdp2mcif_rd_req_src_valid_d1,sdp2mcif_rd_req_src_ready_d1) <= sdp2mcif_rd_req_src_pd_d0[78:0] (sdp2mcif_rd_req_src_valid_d0,sdp2mcif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp2mcif_rd_req_src_pd_d0 + ,sdp2mcif_rd_req_src_ready_d1 + ,sdp2mcif_rd_req_src_valid_d0 + ,sdp2mcif_rd_req_src_pd_d1 + ,sdp2mcif_rd_req_src_ready_d0 + ,sdp2mcif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp2mcif_rd_req_src_pd_d0; +input sdp2mcif_rd_req_src_ready_d1; +input sdp2mcif_rd_req_src_valid_d0; +output [78:0] sdp2mcif_rd_req_src_pd_d1; +output sdp2mcif_rd_req_src_ready_d0; +output sdp2mcif_rd_req_src_valid_d1; +reg [78:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg [78:0] sdp2mcif_rd_req_src_pd_d1; +reg sdp2mcif_rd_req_src_ready_d0; +reg sdp2mcif_rd_req_src_valid_d1; +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? sdp2mcif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && sdp2mcif_rd_req_src_valid_d0)? sdp2mcif_rd_req_src_pd_d0[78:0] : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + sdp2mcif_rd_req_src_ready_d0 = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sdp2mcif_rd_req_src_ready_d1 + or p1_pipe_data + ) begin + sdp2mcif_rd_req_src_valid_d1 = p1_pipe_valid; + p1_pipe_ready = sdp2mcif_rd_req_src_ready_d1; + sdp2mcif_rd_req_src_pd_d1[78:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp2mcif_rd_req_src_valid_d1^sdp2mcif_rd_req_src_ready_d1^sdp2mcif_rd_req_src_valid_d0^sdp2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (sdp2mcif_rd_req_src_valid_d0 && !sdp2mcif_rd_req_src_ready_d0), (sdp2mcif_rd_req_src_valid_d0), (sdp2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none mcif2sdp_b_rd_rsp_src_pd_d1[513:0] (mcif2sdp_b_rd_rsp_src_valid_d1,mcif2sdp_b_rd_rsp_src_ready_d1) <= mcif2sdp_b_rd_rsp_src_pd_d0[513:0] (mcif2sdp_b_rd_rsp_src_valid_d0,mcif2sdp_b_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mcif2sdp_b_rd_rsp_src_pd_d0 + ,mcif2sdp_b_rd_rsp_src_ready_d1 + ,mcif2sdp_b_rd_rsp_src_valid_d0 + ,mcif2sdp_b_rd_rsp_src_pd_d1 + ,mcif2sdp_b_rd_rsp_src_ready_d0 + ,mcif2sdp_b_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mcif2sdp_b_rd_rsp_src_pd_d0; +input mcif2sdp_b_rd_rsp_src_ready_d1; +input mcif2sdp_b_rd_rsp_src_valid_d0; +output [513:0] mcif2sdp_b_rd_rsp_src_pd_d1; +output mcif2sdp_b_rd_rsp_src_ready_d0; +output mcif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] mcif2sdp_b_rd_rsp_src_pd_d1; +reg mcif2sdp_b_rd_rsp_src_ready_d0; +reg mcif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? mcif2sdp_b_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && mcif2sdp_b_rd_rsp_src_valid_d0)? mcif2sdp_b_rd_rsp_src_pd_d0[513:0] : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + mcif2sdp_b_rd_rsp_src_ready_d0 = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mcif2sdp_b_rd_rsp_src_ready_d1 + or p2_pipe_data + ) begin + mcif2sdp_b_rd_rsp_src_valid_d1 = p2_pipe_valid; + p2_pipe_ready = mcif2sdp_b_rd_rsp_src_ready_d1; + mcif2sdp_b_rd_rsp_src_pd_d1[513:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2sdp_b_rd_rsp_src_valid_d1^mcif2sdp_b_rd_rsp_src_ready_d1^mcif2sdp_b_rd_rsp_src_valid_d0^mcif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mcif2sdp_b_rd_rsp_src_valid_d0 && !mcif2sdp_b_rd_rsp_src_ready_d0), (mcif2sdp_b_rd_rsp_src_valid_d0), (mcif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp2cvif_rd_req_src_pd_d1[78:0] (sdp2cvif_rd_req_src_valid_d1,sdp2cvif_rd_req_src_ready_d1) <= sdp2cvif_rd_req_src_pd_d0[78:0] (sdp2cvif_rd_req_src_valid_d0,sdp2cvif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp2cvif_rd_req_src_pd_d0 + ,sdp2cvif_rd_req_src_ready_d1 + ,sdp2cvif_rd_req_src_valid_d0 + ,sdp2cvif_rd_req_src_pd_d1 + ,sdp2cvif_rd_req_src_ready_d0 + ,sdp2cvif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp2cvif_rd_req_src_pd_d0; +input sdp2cvif_rd_req_src_ready_d1; +input sdp2cvif_rd_req_src_valid_d0; +output [78:0] sdp2cvif_rd_req_src_pd_d1; +output sdp2cvif_rd_req_src_ready_d0; +output sdp2cvif_rd_req_src_valid_d1; +reg [78:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg [78:0] sdp2cvif_rd_req_src_pd_d1; +reg sdp2cvif_rd_req_src_ready_d0; +reg sdp2cvif_rd_req_src_valid_d1; +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? sdp2cvif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && sdp2cvif_rd_req_src_valid_d0)? sdp2cvif_rd_req_src_pd_d0[78:0] : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + sdp2cvif_rd_req_src_ready_d0 = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or sdp2cvif_rd_req_src_ready_d1 + or p3_pipe_data + ) begin + sdp2cvif_rd_req_src_valid_d1 = p3_pipe_valid; + p3_pipe_ready = sdp2cvif_rd_req_src_ready_d1; + sdp2cvif_rd_req_src_pd_d1[78:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp2cvif_rd_req_src_valid_d1^sdp2cvif_rd_req_src_ready_d1^sdp2cvif_rd_req_src_valid_d0^sdp2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (sdp2cvif_rd_req_src_valid_d0 && !sdp2cvif_rd_req_src_ready_d0), (sdp2cvif_rd_req_src_valid_d0), (sdp2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp_b2mcif_rd_req_src_pd_d1[78:0] (sdp_b2mcif_rd_req_src_valid_d1,sdp_b2mcif_rd_req_src_ready_d1) <= sdp_b2mcif_rd_req_src_pd_d0[78:0] (sdp_b2mcif_rd_req_src_valid_d0,sdp_b2mcif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp_b2mcif_rd_req_src_pd_d0 + ,sdp_b2mcif_rd_req_src_ready_d1 + ,sdp_b2mcif_rd_req_src_valid_d0 + ,sdp_b2mcif_rd_req_src_pd_d1 + ,sdp_b2mcif_rd_req_src_ready_d0 + ,sdp_b2mcif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp_b2mcif_rd_req_src_pd_d0; +input sdp_b2mcif_rd_req_src_ready_d1; +input sdp_b2mcif_rd_req_src_valid_d0; +output [78:0] sdp_b2mcif_rd_req_src_pd_d1; +output sdp_b2mcif_rd_req_src_ready_d0; +output sdp_b2mcif_rd_req_src_valid_d1; +reg [78:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg [78:0] sdp_b2mcif_rd_req_src_pd_d1; +reg sdp_b2mcif_rd_req_src_ready_d0; +reg sdp_b2mcif_rd_req_src_valid_d1; +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? sdp_b2mcif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && sdp_b2mcif_rd_req_src_valid_d0)? sdp_b2mcif_rd_req_src_pd_d0[78:0] : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + sdp_b2mcif_rd_req_src_ready_d0 = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or sdp_b2mcif_rd_req_src_ready_d1 + or p4_pipe_data + ) begin + sdp_b2mcif_rd_req_src_valid_d1 = p4_pipe_valid; + p4_pipe_ready = sdp_b2mcif_rd_req_src_ready_d1; + sdp_b2mcif_rd_req_src_pd_d1[78:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp_b2mcif_rd_req_src_valid_d1^sdp_b2mcif_rd_req_src_ready_d1^sdp_b2mcif_rd_req_src_valid_d0^sdp_b2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (sdp_b2mcif_rd_req_src_valid_d0 && !sdp_b2mcif_rd_req_src_ready_d0), (sdp_b2mcif_rd_req_src_valid_d0), (sdp_b2mcif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none sdp_b2cvif_rd_req_src_pd_d1[78:0] (sdp_b2cvif_rd_req_src_valid_d1,sdp_b2cvif_rd_req_src_ready_d1) <= sdp_b2cvif_rd_req_src_pd_d0[78:0] (sdp_b2cvif_rd_req_src_valid_d0,sdp_b2cvif_rd_req_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sdp_b2cvif_rd_req_src_pd_d0 + ,sdp_b2cvif_rd_req_src_ready_d1 + ,sdp_b2cvif_rd_req_src_valid_d0 + ,sdp_b2cvif_rd_req_src_pd_d1 + ,sdp_b2cvif_rd_req_src_ready_d0 + ,sdp_b2cvif_rd_req_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [78:0] sdp_b2cvif_rd_req_src_pd_d0; +input sdp_b2cvif_rd_req_src_ready_d1; +input sdp_b2cvif_rd_req_src_valid_d0; +output [78:0] sdp_b2cvif_rd_req_src_pd_d1; +output sdp_b2cvif_rd_req_src_ready_d0; +output sdp_b2cvif_rd_req_src_valid_d1; +reg [78:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg [78:0] sdp_b2cvif_rd_req_src_pd_d1; +reg sdp_b2cvif_rd_req_src_ready_d0; +reg sdp_b2cvif_rd_req_src_valid_d1; +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? sdp_b2cvif_rd_req_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && sdp_b2cvif_rd_req_src_valid_d0)? sdp_b2cvif_rd_req_src_pd_d0[78:0] : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + sdp_b2cvif_rd_req_src_ready_d0 = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or sdp_b2cvif_rd_req_src_ready_d1 + or p5_pipe_data + ) begin + sdp_b2cvif_rd_req_src_valid_d1 = p5_pipe_valid; + p5_pipe_ready = sdp_b2cvif_rd_req_src_ready_d1; + sdp_b2cvif_rd_req_src_pd_d1[78:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sdp_b2cvif_rd_req_src_valid_d1^sdp_b2cvif_rd_req_src_ready_d1^sdp_b2cvif_rd_req_src_valid_d0^sdp_b2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (sdp_b2cvif_rd_req_src_valid_d0 && !sdp_b2cvif_rd_req_src_ready_d0), (sdp_b2cvif_rd_req_src_valid_d0), (sdp_b2cvif_rd_req_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none cvif2sdp_b_rd_rsp_src_pd_d1[513:0] (cvif2sdp_b_rd_rsp_src_valid_d1,cvif2sdp_b_rd_rsp_src_ready_d1) <= cvif2sdp_b_rd_rsp_src_pd_d0[513:0] (cvif2sdp_b_rd_rsp_src_valid_d0,cvif2sdp_b_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvif2sdp_b_rd_rsp_src_pd_d0 + ,cvif2sdp_b_rd_rsp_src_ready_d1 + ,cvif2sdp_b_rd_rsp_src_valid_d0 + ,cvif2sdp_b_rd_rsp_src_pd_d1 + ,cvif2sdp_b_rd_rsp_src_ready_d0 + ,cvif2sdp_b_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] cvif2sdp_b_rd_rsp_src_pd_d0; +input cvif2sdp_b_rd_rsp_src_ready_d1; +input cvif2sdp_b_rd_rsp_src_valid_d0; +output [513:0] cvif2sdp_b_rd_rsp_src_pd_d1; +output cvif2sdp_b_rd_rsp_src_ready_d0; +output cvif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] cvif2sdp_b_rd_rsp_src_pd_d1; +reg cvif2sdp_b_rd_rsp_src_ready_d0; +reg cvif2sdp_b_rd_rsp_src_valid_d1; +reg [513:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? cvif2sdp_b_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && cvif2sdp_b_rd_rsp_src_valid_d0)? cvif2sdp_b_rd_rsp_src_pd_d0[513:0] : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + cvif2sdp_b_rd_rsp_src_ready_d0 = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or cvif2sdp_b_rd_rsp_src_ready_d1 + or p6_pipe_data + ) begin + cvif2sdp_b_rd_rsp_src_valid_d1 = p6_pipe_valid; + p6_pipe_ready = cvif2sdp_b_rd_rsp_src_ready_d1; + cvif2sdp_b_rd_rsp_src_pd_d1[513:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvif2sdp_b_rd_rsp_src_valid_d1^cvif2sdp_b_rd_rsp_src_ready_d1^cvif2sdp_b_rd_rsp_src_valid_d0^cvif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (cvif2sdp_b_rd_rsp_src_valid_d0 && !cvif2sdp_b_rd_rsp_src_ready_d0), (cvif2sdp_b_rd_rsp_src_valid_d0), (cvif2sdp_b_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none mcif2sdp_rd_rsp_src_pd_d1[513:0] (mcif2sdp_rd_rsp_src_valid_d1,mcif2sdp_rd_rsp_src_ready_d1) <= mcif2sdp_rd_rsp_src_pd_d0[513:0] (mcif2sdp_rd_rsp_src_valid_d0,mcif2sdp_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mcif2sdp_rd_rsp_src_pd_d0 + ,mcif2sdp_rd_rsp_src_ready_d1 + ,mcif2sdp_rd_rsp_src_valid_d0 + ,mcif2sdp_rd_rsp_src_pd_d1 + ,mcif2sdp_rd_rsp_src_ready_d0 + ,mcif2sdp_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mcif2sdp_rd_rsp_src_pd_d0; +input mcif2sdp_rd_rsp_src_ready_d1; +input mcif2sdp_rd_rsp_src_valid_d0; +output [513:0] mcif2sdp_rd_rsp_src_pd_d1; +output mcif2sdp_rd_rsp_src_ready_d0; +output mcif2sdp_rd_rsp_src_valid_d1; +reg [513:0] mcif2sdp_rd_rsp_src_pd_d1; +reg mcif2sdp_rd_rsp_src_ready_d0; +reg mcif2sdp_rd_rsp_src_valid_d1; +reg [513:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? mcif2sdp_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && mcif2sdp_rd_rsp_src_valid_d0)? mcif2sdp_rd_rsp_src_pd_d0[513:0] : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + mcif2sdp_rd_rsp_src_ready_d0 = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or mcif2sdp_rd_rsp_src_ready_d1 + or p7_pipe_data + ) begin + mcif2sdp_rd_rsp_src_valid_d1 = p7_pipe_valid; + p7_pipe_ready = mcif2sdp_rd_rsp_src_ready_d1; + mcif2sdp_rd_rsp_src_pd_d1[513:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mcif2sdp_rd_rsp_src_valid_d1^mcif2sdp_rd_rsp_src_ready_d1^mcif2sdp_rd_rsp_src_valid_d0^mcif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (mcif2sdp_rd_rsp_src_valid_d0 && !mcif2sdp_rd_rsp_src_ready_d0), (mcif2sdp_rd_rsp_src_valid_d0), (mcif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p7 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none cvif2sdp_rd_rsp_src_pd_d1[513:0] (cvif2sdp_rd_rsp_src_valid_d1,cvif2sdp_rd_rsp_src_ready_d1) <= cvif2sdp_rd_rsp_src_pd_d0[513:0] (cvif2sdp_rd_rsp_src_valid_d0,cvif2sdp_rd_rsp_src_ready_d0) +// ************************************************************************************************************** +module NV_NVDLA_RT_SDP2NOCIF_pipe_p8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvif2sdp_rd_rsp_src_pd_d0 + ,cvif2sdp_rd_rsp_src_ready_d1 + ,cvif2sdp_rd_rsp_src_valid_d0 + ,cvif2sdp_rd_rsp_src_pd_d1 + ,cvif2sdp_rd_rsp_src_ready_d0 + ,cvif2sdp_rd_rsp_src_valid_d1 + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] cvif2sdp_rd_rsp_src_pd_d0; +input cvif2sdp_rd_rsp_src_ready_d1; +input cvif2sdp_rd_rsp_src_valid_d0; +output [513:0] cvif2sdp_rd_rsp_src_pd_d1; +output cvif2sdp_rd_rsp_src_ready_d0; +output cvif2sdp_rd_rsp_src_valid_d1; +reg [513:0] cvif2sdp_rd_rsp_src_pd_d1; +reg cvif2sdp_rd_rsp_src_ready_d0; +reg cvif2sdp_rd_rsp_src_valid_d1; +reg [513:0] p8_pipe_data; +reg p8_pipe_ready; +reg p8_pipe_ready_bc; +reg p8_pipe_valid; +//## pipe (8) valid-ready-bubble-collapse +always @( + p8_pipe_ready + or p8_pipe_valid + ) begin + p8_pipe_ready_bc = p8_pipe_ready || !p8_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_pipe_valid <= 1'b0; + end else begin + p8_pipe_valid <= (p8_pipe_ready_bc)? cvif2sdp_rd_rsp_src_valid_d0 : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_pipe_data <= (p8_pipe_ready_bc && cvif2sdp_rd_rsp_src_valid_d0)? cvif2sdp_rd_rsp_src_pd_d0[513:0] : p8_pipe_data; +// VCS sop_coverage_off end +end +always @( + p8_pipe_ready_bc + ) begin + cvif2sdp_rd_rsp_src_ready_d0 = p8_pipe_ready_bc; +end +//## pipe (8) output +always @( + p8_pipe_valid + or cvif2sdp_rd_rsp_src_ready_d1 + or p8_pipe_data + ) begin + cvif2sdp_rd_rsp_src_valid_d1 = p8_pipe_valid; + p8_pipe_ready = cvif2sdp_rd_rsp_src_ready_d1; + cvif2sdp_rd_rsp_src_pd_d1[513:0] = p8_pipe_data; +end +//## pipe (8) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p8_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvif2sdp_rd_rsp_src_valid_d1^cvif2sdp_rd_rsp_src_ready_d1^cvif2sdp_rd_rsp_src_valid_d0^cvif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (cvif2sdp_rd_rsp_src_valid_d0 && !cvif2sdp_rd_rsp_src_ready_d0), (cvif2sdp_rd_rsp_src_valid_d0), (cvif2sdp_rd_rsp_src_ready_d0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RT_SDP2NOCIF_pipe_p8 diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v new file mode 100644 index 0000000..c1824ae --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v @@ -0,0 +1,1985 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_dma.v +module NV_NVDLA_RUBIK_dma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,mcif2rbk_rd_rsp_pd //|< i + ,mcif2rbk_rd_rsp_valid //|< i + ,mcif2rbk_wr_rsp_complete //|< i + ,rbk2mcif_rd_req_ready //|< i + ,rbk2mcif_wr_req_ready //|< i + ,rd_cdt_lat_fifo_pop //|< i + ,rd_req_pd //|< i + ,rd_req_type //|< i + ,rd_req_vld //|< i + ,rd_rsp_rdy //|< i + ,wr_req_pd //|< i + ,wr_req_type //|< i + ,wr_req_vld //|< i + ,mcif2rbk_rd_rsp_ready //|> o + ,rbk2mcif_rd_cdt_lat_fifo_pop //|> o + ,rbk2mcif_rd_req_pd //|> o + ,rbk2mcif_rd_req_valid //|> o + ,rbk2mcif_wr_req_pd //|> o + ,rbk2mcif_wr_req_valid //|> o + ,rd_req_rdy //|> o + ,rd_rsp_pd //|> o + ,rd_rsp_vld //|> o + ,wr_req_rdy //|> o + ,wr_rsp_complete //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mcif2rbk_rd_rsp_pd; +input mcif2rbk_rd_rsp_valid; +input mcif2rbk_wr_rsp_complete; +input rbk2mcif_rd_req_ready; +input rbk2mcif_wr_req_ready; +input rd_cdt_lat_fifo_pop; +input [78:0] rd_req_pd; +input rd_req_type; +input rd_req_vld; +input rd_rsp_rdy; +input [514:0] wr_req_pd; +input wr_req_type; +input wr_req_vld; +output mcif2rbk_rd_rsp_ready; +output rbk2mcif_rd_cdt_lat_fifo_pop; +output [78:0] rbk2mcif_rd_req_pd; +output rbk2mcif_rd_req_valid; +output [514:0] rbk2mcif_wr_req_pd; +output rbk2mcif_wr_req_valid; +output rd_req_rdy; +output [513:0] rd_rsp_pd; +output rd_rsp_vld; +output wr_req_rdy; +output wr_rsp_complete; +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg mc_pending; +reg mc_wr_rsp_complete; +reg rbk2mcif_rd_cdt_lat_fifo_pop; +reg wr_rsp_complete; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire [513:0] mc_int_rd_rsp_pd; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire [514:0] mc_int_wr_req_pd; +wire [514:0] mc_int_wr_req_pd_d0; +wire mc_int_wr_req_ready; +wire mc_int_wr_req_ready_d0; +wire mc_int_wr_req_valid; +wire mc_int_wr_req_valid_d0; +wire mc_int_wr_rsp_complete; +wire mc_rd_req_rdy; +wire mc_rd_req_rdyi; +wire mc_rd_req_vld; +wire [513:0] mc_rd_rsp_pd; +wire mc_rd_rsp_vld; +wire mc_releasing; +wire mc_wr_req_rdy; +wire mc_wr_req_rdyi; +wire mc_wr_req_vld; +wire [513:0] mcif2rbk_rd_rsp_pd_d0; +wire mcif2rbk_rd_rsp_ready_d0; +wire mcif2rbk_rd_rsp_valid_d0; +wire rd_req_rdyi; +wire rd_rsp_type; +wire releasing; +wire require_ack; +wire wr_req_rdyi; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//instance dma_rd & dma_wr +// rd Channel: Request +assign mc_rd_req_vld = rd_req_vld & (rd_req_type == 1'b1); +assign mc_rd_req_rdyi = mc_rd_req_rdy & (rd_req_type == 1'b1); +assign rd_req_rdyi = mc_rd_req_rdyi; +assign rd_req_rdy= rd_req_rdyi; +NV_NVDLA_RUBIK_DMA_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mc_int_rd_req_ready (mc_int_rd_req_ready) //|< w + ,.mc_rd_req_vld (mc_rd_req_vld) //|< w + ,.rd_req_pd (rd_req_pd[78:0]) //|< i + ,.mc_int_rd_req_pd (mc_int_rd_req_pd[78:0]) //|> w + ,.mc_int_rd_req_valid (mc_int_rd_req_valid) //|> w + ,.mc_rd_req_rdy (mc_rd_req_rdy) //|> w + ); +assign mc_int_rd_req_valid_d0 = mc_int_rd_req_valid; +assign mc_int_rd_req_ready = mc_int_rd_req_ready_d0; +assign mc_int_rd_req_pd_d0[78:0] = mc_int_rd_req_pd[78:0]; +assign rbk2mcif_rd_req_valid = mc_int_rd_req_valid_d0; +assign mc_int_rd_req_ready_d0 = rbk2mcif_rd_req_ready; +assign rbk2mcif_rd_req_pd[78:0] = mc_int_rd_req_pd_d0[78:0]; +// rd Channel: Response +assign mcif2rbk_rd_rsp_valid_d0 = mcif2rbk_rd_rsp_valid; +assign mcif2rbk_rd_rsp_ready = mcif2rbk_rd_rsp_ready_d0; +assign mcif2rbk_rd_rsp_pd_d0[513:0] = mcif2rbk_rd_rsp_pd[513:0]; +assign mc_int_rd_rsp_valid = mcif2rbk_rd_rsp_valid_d0; +assign mcif2rbk_rd_rsp_ready_d0 = mc_int_rd_rsp_ready; +assign mc_int_rd_rsp_pd[513:0] = mcif2rbk_rd_rsp_pd_d0[513:0]; +NV_NVDLA_RUBIK_DMA_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mc_int_rd_rsp_pd (mc_int_rd_rsp_pd[513:0]) //|< w + ,.mc_int_rd_rsp_valid (mc_int_rd_rsp_valid) //|< w + ,.rd_rsp_rdy (rd_rsp_rdy) //|< i + ,.mc_int_rd_rsp_ready (mc_int_rd_rsp_ready) //|> w + ,.mc_rd_rsp_pd (mc_rd_rsp_pd[513:0]) //|> w + ,.mc_rd_rsp_vld (mc_rd_rsp_vld) //|> w + ); +assign rd_rsp_vld = mc_rd_rsp_vld; +assign rd_rsp_pd = ({514{mc_rd_rsp_vld}} & mc_rd_rsp_pd); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rbk2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + rbk2mcif_rd_cdt_lat_fifo_pop <= rd_cdt_lat_fifo_pop & (rd_rsp_type == 1'b1); + end +end +// wr Channel: Request +assign mc_wr_req_vld = wr_req_vld & (wr_req_type == 1'b1); +assign mc_wr_req_rdyi = mc_wr_req_rdy & (wr_req_type == 1'b1); +assign wr_req_rdyi = mc_wr_req_rdyi; +assign wr_req_rdy= wr_req_rdyi; +NV_NVDLA_RUBIK_DMA_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mc_int_wr_req_ready (mc_int_wr_req_ready) //|< w + ,.mc_wr_req_vld (mc_wr_req_vld) //|< w + ,.wr_req_pd (wr_req_pd[514:0]) //|< i + ,.mc_int_wr_req_pd (mc_int_wr_req_pd[514:0]) //|> w + ,.mc_int_wr_req_valid (mc_int_wr_req_valid) //|> w + ,.mc_wr_req_rdy (mc_wr_req_rdy) //|> w + ); +assign mc_int_wr_req_valid_d0 = mc_int_wr_req_valid; +assign mc_int_wr_req_ready = mc_int_wr_req_ready_d0; +assign mc_int_wr_req_pd_d0[514:0] = mc_int_wr_req_pd[514:0]; +assign rbk2mcif_wr_req_valid = mc_int_wr_req_valid_d0; +assign mc_int_wr_req_ready_d0 = rbk2mcif_wr_req_ready; +assign rbk2mcif_wr_req_pd[514:0] = mc_int_wr_req_pd_d0[514:0]; +// wr Channel: Response +assign mc_int_wr_rsp_complete = mcif2rbk_wr_rsp_complete; +assign require_ack = (wr_req_pd[514:514]==0) & (wr_req_pd[77:77]==1); +assign ack_raw_vld = wr_req_vld & wr_req_rdyi & require_ack; +assign ack_raw_id = wr_req_type; +// stage1: bot +assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld; +always @(posedge nvdla_core_clk) begin + if ((ack_raw_vld & ack_raw_rdy) == 1'b1) begin + ack_bot_id <= ack_raw_id; +// VCS coverage off + end else if ((ack_raw_vld & ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_bot_vld <= 1'b0; + end else begin + if ((ack_raw_rdy) == 1'b1) begin + ack_bot_vld <= ack_raw_vld; +// VCS coverage off + end else if ((ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_raw_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"dmaif bot never push back") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, ack_raw_vld & !ack_raw_rdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// stage2: top +assign ack_bot_rdy = ack_top_rdy || !ack_top_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_id <= 1'b0; + end else begin + if ((ack_bot_vld & ack_bot_rdy) == 1'b1) begin + ack_top_id <= ack_bot_id; +// VCS coverage off + end else if ((ack_bot_vld & ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_vld & ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_vld <= 1'b0; + end else begin + if ((ack_bot_rdy) == 1'b1) begin + ack_top_vld <= ack_bot_vld; +// VCS coverage off + end else if ((ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign ack_top_rdy = releasing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_wr_rsp_complete <= 1'b0; + end else begin + mc_wr_rsp_complete <= mc_int_wr_rsp_complete; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_rsp_complete <= 1'b0; + end else begin + wr_rsp_complete <= releasing; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_pending <= 1'b0; + end else begin + if (ack_top_id==0) begin + if (mc_wr_rsp_complete) begin + mc_pending <= 1'b1; + end + end else if (ack_top_id==1) begin + if (mc_pending) begin + mc_pending <= 1'b0; + end + end + end +end +assign mc_releasing = ack_top_id==1'b1 & (mc_wr_rsp_complete | mc_pending); +assign releasing = mc_releasing; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no mc resp back and pending together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, mc_pending & mc_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no ack_top_vld when resp from mc") zzz_assert_never_10x (nvdla_core_clk, `ASSERT_RESET, (mc_pending | mc_wr_rsp_complete) & !ack_top_vld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +assign rd_rsp_type = rd_req_type; +endmodule // NV_NVDLA_RUBIK_dma +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_rd_req_pd (mc_int_rd_req_valid,mc_int_rd_req_ready) <= rd_req_pd[78:0] (mc_rd_req_vld,mc_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_DMA_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mc_int_rd_req_ready + ,mc_rd_req_vld + ,rd_req_pd + ,mc_int_rd_req_pd + ,mc_int_rd_req_valid + ,mc_rd_req_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mc_int_rd_req_ready; +input mc_rd_req_vld; +input [78:0] rd_req_pd; +output [78:0] mc_int_rd_req_pd; +output mc_int_rd_req_valid; +output mc_rd_req_rdy; +reg [78:0] mc_int_rd_req_pd; +reg mc_int_rd_req_valid; +reg mc_rd_req_rdy; +reg [78:0] p1_pipe_data; +reg [78:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [78:0] p1_skid_data; +reg [78:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_rd_req_vld + or p1_pipe_rand_ready + or rd_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_rd_req_vld; + mc_rd_req_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = rd_req_pd[78:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_rd_req_vld; + mc_rd_req_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_rd_req_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mc_int_rd_req_ready + or p1_pipe_data + ) begin + mc_int_rd_req_valid = p1_pipe_valid; + p1_pipe_ready = mc_int_rd_req_ready; + mc_int_rd_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_rd_req_valid^mc_int_rd_req_ready^mc_rd_req_vld^mc_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (mc_rd_req_vld && !mc_rd_req_rdy), (mc_rd_req_vld), (mc_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_DMA_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_rd_req_pd (cv_int_rd_req_valid,cv_int_rd_req_ready) <= rd_req_pd[78:0] (cv_rd_req_vld,cv_rd_req_rdy) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os mc_rd_rsp_pd (mc_rd_rsp_vld,rd_rsp_rdy) <= mc_int_rd_rsp_pd[513:0] (mc_int_rd_rsp_valid,mc_int_rd_rsp_ready) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_DMA_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mc_int_rd_rsp_pd + ,mc_int_rd_rsp_valid + ,rd_rsp_rdy + ,mc_int_rd_rsp_ready + ,mc_rd_rsp_pd + ,mc_rd_rsp_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mc_int_rd_rsp_pd; +input mc_int_rd_rsp_valid; +input rd_rsp_rdy; +output mc_int_rd_rsp_ready; +output [513:0] mc_rd_rsp_pd; +output mc_rd_rsp_vld; +reg mc_int_rd_rsp_ready; +reg [513:0] mc_rd_rsp_pd; +reg mc_rd_rsp_vld; +reg [513:0] p3_pipe_data; +reg [513:0] p3_pipe_rand_data; +reg p3_pipe_rand_ready; +reg p3_pipe_rand_valid; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg [513:0] p3_pipe_skid_data; +reg p3_pipe_skid_ready; +reg p3_pipe_skid_valid; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [513:0] p3_skid_data; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) randomizer +`ifndef SYNTHESIS +reg p3_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p3_pipe_rand_active + or + `endif + mc_int_rd_rsp_valid + or p3_pipe_rand_ready + or mc_int_rd_rsp_pd + ) begin + `ifdef SYNTHESIS + p3_pipe_rand_valid = mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = p3_pipe_rand_ready; + p3_pipe_rand_data = mc_int_rd_rsp_pd[513:0]; + `else +// VCS coverage off + p3_pipe_rand_valid = (p3_pipe_rand_active)? 1'b0 : mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = (p3_pipe_rand_active)? 1'b0 : p3_pipe_rand_ready; + p3_pipe_rand_data = (p3_pipe_rand_active)? 'bx : mc_int_rd_rsp_pd[513:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p3_pipe_stall_cycles; +integer p3_pipe_stall_probability; +integer p3_pipe_stall_cycles_min; +integer p3_pipe_stall_cycles_max; +initial begin + p3_pipe_stall_cycles = 0; + p3_pipe_stall_probability = 0; + p3_pipe_stall_cycles_min = 1; + p3_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability" ) ) p3_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min" ) ) p3_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max" ) ) p3_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p3_pipe_rand_enable; +reg p3_pipe_rand_poised; +always @( + p3_pipe_stall_cycles + or p3_pipe_stall_probability + or mc_int_rd_rsp_valid + ) begin + p3_pipe_rand_active = p3_pipe_stall_cycles != 0; + p3_pipe_rand_enable = p3_pipe_stall_probability != 0; + p3_pipe_rand_poised = p3_pipe_rand_enable && !p3_pipe_rand_active && mc_int_rd_rsp_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_stall_cycles <= 1'b0; + end else begin + if (p3_pipe_rand_poised) begin + if (p3_pipe_stall_probability >= prand_inst0(1, 100)) begin + p3_pipe_stall_cycles <= prand_inst1(p3_pipe_stall_cycles_min, p3_pipe_stall_cycles_max); + end + end else if (p3_pipe_rand_active) begin + p3_pipe_stall_cycles <= p3_pipe_stall_cycles - 1; + end else begin + p3_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_pipe_rand_valid)? p3_pipe_rand_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_pipe_rand_ready = p3_pipe_ready_bc; +end +//## pipe (3) skid buffer +always @( + p3_pipe_valid + or p3_skid_ready_flop + or p3_pipe_skid_ready + or p3_skid_valid + ) begin + p3_skid_catch = p3_pipe_valid && p3_skid_ready_flop && !p3_pipe_skid_ready; + p3_skid_ready = (p3_skid_valid)? p3_pipe_skid_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + p3_pipe_ready <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_pipe_skid_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + p3_pipe_ready <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or p3_pipe_valid + or p3_skid_valid + or p3_pipe_data + or p3_skid_data + ) begin + p3_pipe_skid_valid = (p3_skid_ready_flop)? p3_pipe_valid : p3_skid_valid; +// VCS sop_coverage_off start + p3_pipe_skid_data = (p3_skid_ready_flop)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) output +always @( + p3_pipe_skid_valid + or rd_rsp_rdy + or p3_pipe_skid_data + ) begin + mc_rd_rsp_vld = p3_pipe_skid_valid; + p3_pipe_skid_ready = rd_rsp_rdy; + mc_rd_rsp_pd = p3_pipe_skid_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_rd_rsp_vld^rd_rsp_rdy^mc_int_rd_rsp_valid^mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (mc_int_rd_rsp_valid && !mc_int_rd_rsp_ready), (mc_int_rd_rsp_valid), (mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_DMA_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cv_rd_rsp_pd (cv_rd_rsp_vld,rd_rsp_rdy) <= cv_int_rd_rsp_pd[513:0] (cv_int_rd_rsp_valid,cv_int_rd_rsp_ready) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_wr_req_pd (mc_int_wr_req_valid,mc_int_wr_req_ready) <= wr_req_pd[514:0] (mc_wr_req_vld,mc_wr_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_DMA_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mc_int_wr_req_ready + ,mc_wr_req_vld + ,wr_req_pd + ,mc_int_wr_req_pd + ,mc_int_wr_req_valid + ,mc_wr_req_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mc_int_wr_req_ready; +input mc_wr_req_vld; +input [514:0] wr_req_pd; +output [514:0] mc_int_wr_req_pd; +output mc_int_wr_req_valid; +output mc_wr_req_rdy; +reg [514:0] mc_int_wr_req_pd; +reg mc_int_wr_req_valid; +reg mc_wr_req_rdy; +reg [514:0] p5_pipe_data; +reg [514:0] p5_pipe_rand_data; +reg p5_pipe_rand_ready; +reg p5_pipe_rand_valid; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [514:0] p5_skid_data; +reg [514:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +//## pipe (5) randomizer +`ifndef SYNTHESIS +reg p5_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p5_pipe_rand_active + or + `endif + mc_wr_req_vld + or p5_pipe_rand_ready + or wr_req_pd + ) begin + `ifdef SYNTHESIS + p5_pipe_rand_valid = mc_wr_req_vld; + mc_wr_req_rdy = p5_pipe_rand_ready; + p5_pipe_rand_data = wr_req_pd[514:0]; + `else +// VCS coverage off + p5_pipe_rand_valid = (p5_pipe_rand_active)? 1'b0 : mc_wr_req_vld; + mc_wr_req_rdy = (p5_pipe_rand_active)? 1'b0 : p5_pipe_rand_ready; + p5_pipe_rand_data = (p5_pipe_rand_active)? 'bx : wr_req_pd[514:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p5_pipe_stall_cycles; +integer p5_pipe_stall_probability; +integer p5_pipe_stall_cycles_min; +integer p5_pipe_stall_cycles_max; +initial begin + p5_pipe_stall_cycles = 0; + p5_pipe_stall_probability = 0; + p5_pipe_stall_cycles_min = 1; + p5_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_rand_probability=%d", p5_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p5_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability=%d", p5_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p5_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min=%d", p5_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p5_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max=%d", p5_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p5_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability" ) ) p5_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min" ) ) p5_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max" ) ) p5_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p5_pipe_rand_enable; +reg p5_pipe_rand_poised; +always @( + p5_pipe_stall_cycles + or p5_pipe_stall_probability + or mc_wr_req_vld + ) begin + p5_pipe_rand_active = p5_pipe_stall_cycles != 0; + p5_pipe_rand_enable = p5_pipe_stall_probability != 0; + p5_pipe_rand_poised = p5_pipe_rand_enable && !p5_pipe_rand_active && mc_wr_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_stall_cycles <= 1'b0; + end else begin + if (p5_pipe_rand_poised) begin + if (p5_pipe_stall_probability >= prand_inst0(1, 100)) begin + p5_pipe_stall_cycles <= prand_inst1(p5_pipe_stall_cycles_min, p5_pipe_stall_cycles_max); + end + end else if (p5_pipe_rand_active) begin + p5_pipe_stall_cycles <= p5_pipe_stall_cycles - 1; + end else begin + p5_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (5) skid buffer +always @( + p5_pipe_rand_valid + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = p5_pipe_rand_valid && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + p5_pipe_rand_ready <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + p5_pipe_rand_ready <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? p5_pipe_rand_data : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or p5_pipe_rand_valid + or p5_skid_valid + or p5_pipe_rand_data + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? p5_pipe_rand_valid : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? p5_pipe_rand_data : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mc_int_wr_req_ready + or p5_pipe_data + ) begin + mc_int_wr_req_valid = p5_pipe_valid; + p5_pipe_ready = mc_int_wr_req_ready; + mc_int_wr_req_pd = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_wr_req_valid^mc_int_wr_req_ready^mc_wr_req_vld^mc_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_20x (nvdla_core_clk, `ASSERT_RESET, (mc_wr_req_vld && !mc_wr_req_rdy), (mc_wr_req_vld), (mc_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_DMA_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_wr_req_pd (cv_int_wr_req_valid,cv_int_wr_req_ready) <= wr_req_pd[514:0] (cv_wr_req_vld,cv_wr_req_rdy) +// ************************************************************************************************************** diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v.vcp new file mode 100644 index 0000000..c1824ae --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v.vcp @@ -0,0 +1,1985 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_dma.v +module NV_NVDLA_RUBIK_dma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,mcif2rbk_rd_rsp_pd //|< i + ,mcif2rbk_rd_rsp_valid //|< i + ,mcif2rbk_wr_rsp_complete //|< i + ,rbk2mcif_rd_req_ready //|< i + ,rbk2mcif_wr_req_ready //|< i + ,rd_cdt_lat_fifo_pop //|< i + ,rd_req_pd //|< i + ,rd_req_type //|< i + ,rd_req_vld //|< i + ,rd_rsp_rdy //|< i + ,wr_req_pd //|< i + ,wr_req_type //|< i + ,wr_req_vld //|< i + ,mcif2rbk_rd_rsp_ready //|> o + ,rbk2mcif_rd_cdt_lat_fifo_pop //|> o + ,rbk2mcif_rd_req_pd //|> o + ,rbk2mcif_rd_req_valid //|> o + ,rbk2mcif_wr_req_pd //|> o + ,rbk2mcif_wr_req_valid //|> o + ,rd_req_rdy //|> o + ,rd_rsp_pd //|> o + ,rd_rsp_vld //|> o + ,wr_req_rdy //|> o + ,wr_rsp_complete //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mcif2rbk_rd_rsp_pd; +input mcif2rbk_rd_rsp_valid; +input mcif2rbk_wr_rsp_complete; +input rbk2mcif_rd_req_ready; +input rbk2mcif_wr_req_ready; +input rd_cdt_lat_fifo_pop; +input [78:0] rd_req_pd; +input rd_req_type; +input rd_req_vld; +input rd_rsp_rdy; +input [514:0] wr_req_pd; +input wr_req_type; +input wr_req_vld; +output mcif2rbk_rd_rsp_ready; +output rbk2mcif_rd_cdt_lat_fifo_pop; +output [78:0] rbk2mcif_rd_req_pd; +output rbk2mcif_rd_req_valid; +output [514:0] rbk2mcif_wr_req_pd; +output rbk2mcif_wr_req_valid; +output rd_req_rdy; +output [513:0] rd_rsp_pd; +output rd_rsp_vld; +output wr_req_rdy; +output wr_rsp_complete; +reg ack_bot_id; +reg ack_bot_vld; +reg ack_top_id; +reg ack_top_vld; +reg mc_pending; +reg mc_wr_rsp_complete; +reg rbk2mcif_rd_cdt_lat_fifo_pop; +reg wr_rsp_complete; +wire ack_bot_rdy; +wire ack_raw_id; +wire ack_raw_rdy; +wire ack_raw_vld; +wire ack_top_rdy; +wire [78:0] mc_int_rd_req_pd; +wire [78:0] mc_int_rd_req_pd_d0; +wire mc_int_rd_req_ready; +wire mc_int_rd_req_ready_d0; +wire mc_int_rd_req_valid; +wire mc_int_rd_req_valid_d0; +wire [513:0] mc_int_rd_rsp_pd; +wire mc_int_rd_rsp_ready; +wire mc_int_rd_rsp_valid; +wire [514:0] mc_int_wr_req_pd; +wire [514:0] mc_int_wr_req_pd_d0; +wire mc_int_wr_req_ready; +wire mc_int_wr_req_ready_d0; +wire mc_int_wr_req_valid; +wire mc_int_wr_req_valid_d0; +wire mc_int_wr_rsp_complete; +wire mc_rd_req_rdy; +wire mc_rd_req_rdyi; +wire mc_rd_req_vld; +wire [513:0] mc_rd_rsp_pd; +wire mc_rd_rsp_vld; +wire mc_releasing; +wire mc_wr_req_rdy; +wire mc_wr_req_rdyi; +wire mc_wr_req_vld; +wire [513:0] mcif2rbk_rd_rsp_pd_d0; +wire mcif2rbk_rd_rsp_ready_d0; +wire mcif2rbk_rd_rsp_valid_d0; +wire rd_req_rdyi; +wire rd_rsp_type; +wire releasing; +wire require_ack; +wire wr_req_rdyi; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//instance dma_rd & dma_wr +// rd Channel: Request +assign mc_rd_req_vld = rd_req_vld & (rd_req_type == 1'b1); +assign mc_rd_req_rdyi = mc_rd_req_rdy & (rd_req_type == 1'b1); +assign rd_req_rdyi = mc_rd_req_rdyi; +assign rd_req_rdy= rd_req_rdyi; +NV_NVDLA_RUBIK_DMA_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mc_int_rd_req_ready (mc_int_rd_req_ready) //|< w + ,.mc_rd_req_vld (mc_rd_req_vld) //|< w + ,.rd_req_pd (rd_req_pd[78:0]) //|< i + ,.mc_int_rd_req_pd (mc_int_rd_req_pd[78:0]) //|> w + ,.mc_int_rd_req_valid (mc_int_rd_req_valid) //|> w + ,.mc_rd_req_rdy (mc_rd_req_rdy) //|> w + ); +assign mc_int_rd_req_valid_d0 = mc_int_rd_req_valid; +assign mc_int_rd_req_ready = mc_int_rd_req_ready_d0; +assign mc_int_rd_req_pd_d0[78:0] = mc_int_rd_req_pd[78:0]; +assign rbk2mcif_rd_req_valid = mc_int_rd_req_valid_d0; +assign mc_int_rd_req_ready_d0 = rbk2mcif_rd_req_ready; +assign rbk2mcif_rd_req_pd[78:0] = mc_int_rd_req_pd_d0[78:0]; +// rd Channel: Response +assign mcif2rbk_rd_rsp_valid_d0 = mcif2rbk_rd_rsp_valid; +assign mcif2rbk_rd_rsp_ready = mcif2rbk_rd_rsp_ready_d0; +assign mcif2rbk_rd_rsp_pd_d0[513:0] = mcif2rbk_rd_rsp_pd[513:0]; +assign mc_int_rd_rsp_valid = mcif2rbk_rd_rsp_valid_d0; +assign mcif2rbk_rd_rsp_ready_d0 = mc_int_rd_rsp_ready; +assign mc_int_rd_rsp_pd[513:0] = mcif2rbk_rd_rsp_pd_d0[513:0]; +NV_NVDLA_RUBIK_DMA_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mc_int_rd_rsp_pd (mc_int_rd_rsp_pd[513:0]) //|< w + ,.mc_int_rd_rsp_valid (mc_int_rd_rsp_valid) //|< w + ,.rd_rsp_rdy (rd_rsp_rdy) //|< i + ,.mc_int_rd_rsp_ready (mc_int_rd_rsp_ready) //|> w + ,.mc_rd_rsp_pd (mc_rd_rsp_pd[513:0]) //|> w + ,.mc_rd_rsp_vld (mc_rd_rsp_vld) //|> w + ); +assign rd_rsp_vld = mc_rd_rsp_vld; +assign rd_rsp_pd = ({514{mc_rd_rsp_vld}} & mc_rd_rsp_pd); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rbk2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + rbk2mcif_rd_cdt_lat_fifo_pop <= rd_cdt_lat_fifo_pop & (rd_rsp_type == 1'b1); + end +end +// wr Channel: Request +assign mc_wr_req_vld = wr_req_vld & (wr_req_type == 1'b1); +assign mc_wr_req_rdyi = mc_wr_req_rdy & (wr_req_type == 1'b1); +assign wr_req_rdyi = mc_wr_req_rdyi; +assign wr_req_rdy= wr_req_rdyi; +NV_NVDLA_RUBIK_DMA_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mc_int_wr_req_ready (mc_int_wr_req_ready) //|< w + ,.mc_wr_req_vld (mc_wr_req_vld) //|< w + ,.wr_req_pd (wr_req_pd[514:0]) //|< i + ,.mc_int_wr_req_pd (mc_int_wr_req_pd[514:0]) //|> w + ,.mc_int_wr_req_valid (mc_int_wr_req_valid) //|> w + ,.mc_wr_req_rdy (mc_wr_req_rdy) //|> w + ); +assign mc_int_wr_req_valid_d0 = mc_int_wr_req_valid; +assign mc_int_wr_req_ready = mc_int_wr_req_ready_d0; +assign mc_int_wr_req_pd_d0[514:0] = mc_int_wr_req_pd[514:0]; +assign rbk2mcif_wr_req_valid = mc_int_wr_req_valid_d0; +assign mc_int_wr_req_ready_d0 = rbk2mcif_wr_req_ready; +assign rbk2mcif_wr_req_pd[514:0] = mc_int_wr_req_pd_d0[514:0]; +// wr Channel: Response +assign mc_int_wr_rsp_complete = mcif2rbk_wr_rsp_complete; +assign require_ack = (wr_req_pd[514:514]==0) & (wr_req_pd[77:77]==1); +assign ack_raw_vld = wr_req_vld & wr_req_rdyi & require_ack; +assign ack_raw_id = wr_req_type; +// stage1: bot +assign ack_raw_rdy = ack_bot_rdy || !ack_bot_vld; +always @(posedge nvdla_core_clk) begin + if ((ack_raw_vld & ack_raw_rdy) == 1'b1) begin + ack_bot_id <= ack_raw_id; +// VCS coverage off + end else if ((ack_raw_vld & ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_bot_vld <= 1'b0; + end else begin + if ((ack_raw_rdy) == 1'b1) begin + ack_bot_vld <= ack_raw_vld; +// VCS coverage off + end else if ((ack_raw_rdy) == 1'b0) begin + end else begin + ack_bot_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_raw_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"dmaif bot never push back") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, ack_raw_vld & !ack_raw_rdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// stage2: top +assign ack_bot_rdy = ack_top_rdy || !ack_top_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_id <= 1'b0; + end else begin + if ((ack_bot_vld & ack_bot_rdy) == 1'b1) begin + ack_top_id <= ack_bot_id; +// VCS coverage off + end else if ((ack_bot_vld & ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_vld & ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + ack_top_vld <= 1'b0; + end else begin + if ((ack_bot_rdy) == 1'b1) begin + ack_top_vld <= ack_bot_vld; +// VCS coverage off + end else if ((ack_bot_rdy) == 1'b0) begin + end else begin + ack_top_vld <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(ack_bot_rdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign ack_top_rdy = releasing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_wr_rsp_complete <= 1'b0; + end else begin + mc_wr_rsp_complete <= mc_int_wr_rsp_complete; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_rsp_complete <= 1'b0; + end else begin + wr_rsp_complete <= releasing; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mc_pending <= 1'b0; + end else begin + if (ack_top_id==0) begin + if (mc_wr_rsp_complete) begin + mc_pending <= 1'b1; + end + end else if (ack_top_id==1) begin + if (mc_pending) begin + mc_pending <= 1'b0; + end + end + end +end +assign mc_releasing = ack_top_id==1'b1 & (mc_wr_rsp_complete | mc_pending); +assign releasing = mc_releasing; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no mc resp back and pending together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, mc_pending & mc_wr_rsp_complete); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"no ack_top_vld when resp from mc") zzz_assert_never_10x (nvdla_core_clk, `ASSERT_RESET, (mc_pending | mc_wr_rsp_complete) & !ack_top_vld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + `endif +`endif +//VCS coverage on +assign rd_rsp_type = rd_req_type; +endmodule // NV_NVDLA_RUBIK_dma +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_rd_req_pd (mc_int_rd_req_valid,mc_int_rd_req_ready) <= rd_req_pd[78:0] (mc_rd_req_vld,mc_rd_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_DMA_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mc_int_rd_req_ready + ,mc_rd_req_vld + ,rd_req_pd + ,mc_int_rd_req_pd + ,mc_int_rd_req_valid + ,mc_rd_req_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mc_int_rd_req_ready; +input mc_rd_req_vld; +input [78:0] rd_req_pd; +output [78:0] mc_int_rd_req_pd; +output mc_int_rd_req_valid; +output mc_rd_req_rdy; +reg [78:0] mc_int_rd_req_pd; +reg mc_int_rd_req_valid; +reg mc_rd_req_rdy; +reg [78:0] p1_pipe_data; +reg [78:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [78:0] p1_skid_data; +reg [78:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + mc_rd_req_vld + or p1_pipe_rand_ready + or rd_req_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = mc_rd_req_vld; + mc_rd_req_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = rd_req_pd[78:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : mc_rd_req_vld; + mc_rd_req_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : rd_req_pd[78:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or mc_rd_req_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && mc_rd_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mc_int_rd_req_ready + or p1_pipe_data + ) begin + mc_int_rd_req_valid = p1_pipe_valid; + p1_pipe_ready = mc_int_rd_req_ready; + mc_int_rd_req_pd = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_rd_req_valid^mc_int_rd_req_ready^mc_rd_req_vld^mc_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (mc_rd_req_vld && !mc_rd_req_rdy), (mc_rd_req_vld), (mc_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_DMA_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_rd_req_pd (cv_int_rd_req_valid,cv_int_rd_req_ready) <= rd_req_pd[78:0] (cv_rd_req_vld,cv_rd_req_rdy) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os mc_rd_rsp_pd (mc_rd_rsp_vld,rd_rsp_rdy) <= mc_int_rd_rsp_pd[513:0] (mc_int_rd_rsp_valid,mc_int_rd_rsp_ready) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_DMA_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mc_int_rd_rsp_pd + ,mc_int_rd_rsp_valid + ,rd_rsp_rdy + ,mc_int_rd_rsp_ready + ,mc_rd_rsp_pd + ,mc_rd_rsp_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [513:0] mc_int_rd_rsp_pd; +input mc_int_rd_rsp_valid; +input rd_rsp_rdy; +output mc_int_rd_rsp_ready; +output [513:0] mc_rd_rsp_pd; +output mc_rd_rsp_vld; +reg mc_int_rd_rsp_ready; +reg [513:0] mc_rd_rsp_pd; +reg mc_rd_rsp_vld; +reg [513:0] p3_pipe_data; +reg [513:0] p3_pipe_rand_data; +reg p3_pipe_rand_ready; +reg p3_pipe_rand_valid; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg [513:0] p3_pipe_skid_data; +reg p3_pipe_skid_ready; +reg p3_pipe_skid_valid; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [513:0] p3_skid_data; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) randomizer +`ifndef SYNTHESIS +reg p3_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p3_pipe_rand_active + or + `endif + mc_int_rd_rsp_valid + or p3_pipe_rand_ready + or mc_int_rd_rsp_pd + ) begin + `ifdef SYNTHESIS + p3_pipe_rand_valid = mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = p3_pipe_rand_ready; + p3_pipe_rand_data = mc_int_rd_rsp_pd[513:0]; + `else +// VCS coverage off + p3_pipe_rand_valid = (p3_pipe_rand_active)? 1'b0 : mc_int_rd_rsp_valid; + mc_int_rd_rsp_ready = (p3_pipe_rand_active)? 1'b0 : p3_pipe_rand_ready; + p3_pipe_rand_data = (p3_pipe_rand_active)? 'bx : mc_int_rd_rsp_pd[513:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p3_pipe_stall_cycles; +integer p3_pipe_stall_probability; +integer p3_pipe_stall_cycles_min; +integer p3_pipe_stall_cycles_max; +initial begin + p3_pipe_stall_cycles = 0; + p3_pipe_stall_probability = 0; + p3_pipe_stall_cycles_min = 1; + p3_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p3_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p3_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p3_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p3_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability" ) ) p3_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min" ) ) p3_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max" ) ) p3_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p3_pipe_rand_enable; +reg p3_pipe_rand_poised; +always @( + p3_pipe_stall_cycles + or p3_pipe_stall_probability + or mc_int_rd_rsp_valid + ) begin + p3_pipe_rand_active = p3_pipe_stall_cycles != 0; + p3_pipe_rand_enable = p3_pipe_stall_probability != 0; + p3_pipe_rand_poised = p3_pipe_rand_enable && !p3_pipe_rand_active && mc_int_rd_rsp_valid === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_stall_cycles <= 1'b0; + end else begin + if (p3_pipe_rand_poised) begin + if (p3_pipe_stall_probability >= prand_inst0(1, 100)) begin + p3_pipe_stall_cycles <= prand_inst1(p3_pipe_stall_cycles_min, p3_pipe_stall_cycles_max); + end + end else if (p3_pipe_rand_active) begin + p3_pipe_stall_cycles <= p3_pipe_stall_cycles - 1; + end else begin + p3_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_pipe_rand_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_pipe_rand_valid)? p3_pipe_rand_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_pipe_rand_ready = p3_pipe_ready_bc; +end +//## pipe (3) skid buffer +always @( + p3_pipe_valid + or p3_skid_ready_flop + or p3_pipe_skid_ready + or p3_skid_valid + ) begin + p3_skid_catch = p3_pipe_valid && p3_skid_ready_flop && !p3_pipe_skid_ready; + p3_skid_ready = (p3_skid_valid)? p3_pipe_skid_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + p3_pipe_ready <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_pipe_skid_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + p3_pipe_ready <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or p3_pipe_valid + or p3_skid_valid + or p3_pipe_data + or p3_skid_data + ) begin + p3_pipe_skid_valid = (p3_skid_ready_flop)? p3_pipe_valid : p3_skid_valid; +// VCS sop_coverage_off start + p3_pipe_skid_data = (p3_skid_ready_flop)? p3_pipe_data : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) output +always @( + p3_pipe_skid_valid + or rd_rsp_rdy + or p3_pipe_skid_data + ) begin + mc_rd_rsp_vld = p3_pipe_skid_valid; + p3_pipe_skid_ready = rd_rsp_rdy; + mc_rd_rsp_pd = p3_pipe_skid_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_rd_rsp_vld^rd_rsp_rdy^mc_int_rd_rsp_valid^mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (mc_int_rd_rsp_valid && !mc_int_rd_rsp_ready), (mc_int_rd_rsp_valid), (mc_int_rd_rsp_ready)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_DMA_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cv_rd_rsp_pd (cv_rd_rsp_vld,rd_rsp_rdy) <= cv_int_rd_rsp_pd[513:0] (cv_int_rd_rsp_valid,cv_int_rd_rsp_ready) +// ************************************************************************************************************** +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is mc_int_wr_req_pd (mc_int_wr_req_valid,mc_int_wr_req_ready) <= wr_req_pd[514:0] (mc_wr_req_vld,mc_wr_req_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_DMA_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mc_int_wr_req_ready + ,mc_wr_req_vld + ,wr_req_pd + ,mc_int_wr_req_pd + ,mc_int_wr_req_valid + ,mc_wr_req_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mc_int_wr_req_ready; +input mc_wr_req_vld; +input [514:0] wr_req_pd; +output [514:0] mc_int_wr_req_pd; +output mc_int_wr_req_valid; +output mc_wr_req_rdy; +reg [514:0] mc_int_wr_req_pd; +reg mc_int_wr_req_valid; +reg mc_wr_req_rdy; +reg [514:0] p5_pipe_data; +reg [514:0] p5_pipe_rand_data; +reg p5_pipe_rand_ready; +reg p5_pipe_rand_valid; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [514:0] p5_skid_data; +reg [514:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +//## pipe (5) randomizer +`ifndef SYNTHESIS +reg p5_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p5_pipe_rand_active + or + `endif + mc_wr_req_vld + or p5_pipe_rand_ready + or wr_req_pd + ) begin + `ifdef SYNTHESIS + p5_pipe_rand_valid = mc_wr_req_vld; + mc_wr_req_rdy = p5_pipe_rand_ready; + p5_pipe_rand_data = wr_req_pd[514:0]; + `else +// VCS coverage off + p5_pipe_rand_valid = (p5_pipe_rand_active)? 1'b0 : mc_wr_req_vld; + mc_wr_req_rdy = (p5_pipe_rand_active)? 1'b0 : p5_pipe_rand_ready; + p5_pipe_rand_data = (p5_pipe_rand_active)? 'bx : wr_req_pd[514:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p5_pipe_stall_cycles; +integer p5_pipe_stall_probability; +integer p5_pipe_stall_cycles_min; +integer p5_pipe_stall_cycles_max; +initial begin + p5_pipe_stall_cycles = 0; + p5_pipe_stall_probability = 0; + p5_pipe_stall_cycles_min = 1; + p5_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_rand_probability=%d", p5_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p5_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability=%d", p5_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p5_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min=%d", p5_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p5_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max=%d", p5_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p5_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_probability" ) ) p5_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_min" ) ) p5_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_dma_pipe_stall_cycles_max" ) ) p5_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p5_pipe_rand_enable; +reg p5_pipe_rand_poised; +always @( + p5_pipe_stall_cycles + or p5_pipe_stall_probability + or mc_wr_req_vld + ) begin + p5_pipe_rand_active = p5_pipe_stall_cycles != 0; + p5_pipe_rand_enable = p5_pipe_stall_probability != 0; + p5_pipe_rand_poised = p5_pipe_rand_enable && !p5_pipe_rand_active && mc_wr_req_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_stall_cycles <= 1'b0; + end else begin + if (p5_pipe_rand_poised) begin + if (p5_pipe_stall_probability >= prand_inst0(1, 100)) begin + p5_pipe_stall_cycles <= prand_inst1(p5_pipe_stall_cycles_min, p5_pipe_stall_cycles_max); + end + end else if (p5_pipe_rand_active) begin + p5_pipe_stall_cycles <= p5_pipe_stall_cycles - 1; + end else begin + p5_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (5) skid buffer +always @( + p5_pipe_rand_valid + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = p5_pipe_rand_valid && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + p5_pipe_rand_ready <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + p5_pipe_rand_ready <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? p5_pipe_rand_data : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or p5_pipe_rand_valid + or p5_skid_valid + or p5_pipe_rand_data + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? p5_pipe_rand_valid : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? p5_pipe_rand_data : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mc_int_wr_req_ready + or p5_pipe_data + ) begin + mc_int_wr_req_valid = p5_pipe_valid; + p5_pipe_ready = mc_int_wr_req_ready; + mc_int_wr_req_pd = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mc_int_wr_req_valid^mc_int_wr_req_ready^mc_wr_req_vld^mc_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_20x (nvdla_core_clk, `ASSERT_RESET, (mc_wr_req_vld && !mc_wr_req_rdy), (mc_wr_req_vld), (mc_wr_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_DMA_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is cv_int_wr_req_pd (cv_int_wr_req_valid,cv_int_wr_req_ready) <= wr_req_pd[514:0] (cv_wr_req_vld,cv_wr_req_rdy) +// ************************************************************************************************************** diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v new file mode 100644 index 0000000..b972f23 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v @@ -0,0 +1,150 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_dr2drc.v +module NV_NVDLA_RUBIK_dr2drc ( + data_fifo_rdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,rd_rsp_pd //|< i + ,rd_rsp_vld //|< i + ,data_fifo_pd //|> o + ,data_fifo_vld //|> o + ,rd_cdt_lat_fifo_pop //|> o + ,rd_rsp_rdy //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input rd_rsp_vld; +input [513:0] rd_rsp_pd; +output rd_rsp_rdy; +output rd_cdt_lat_fifo_pop; +output data_fifo_vld; +output [511:0] data_fifo_pd; +input data_fifo_rdy; +//output dr2drc_q0_vld; +//output [255:0] dr2drc_q0_pd; +//input dr2drc_q0_rdy; +//output dr2drc_q1_vld; +//output [255:0] dr2drc_q1_pd; +//input dr2drc_q1_rdy; +wire [255:0] data_fifo_pd_h; +wire [255:0] data_fifo_pd_l; +wire data_fifo_pop; +wire data_fifo_rdy_h; +wire data_fifo_rdy_l; +wire data_fifo_vld_h; +wire data_fifo_vld_l; +wire [511:0] fifo_idata; +wire [255:0] fifo_idata_h; +wire [255:0] fifo_idata_l; +wire fifo_idata_ready_h; +wire fifo_idata_ready_l; +wire fifo_idata_valid_h; +wire fifo_idata_valid_l; +wire [1:0] fifo_mask; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +/////////write data to data_fifo///////////// +assign fifo_mask[1:0] = rd_rsp_pd[513:512]; +assign fifo_idata[511:0] = rd_rsp_pd[511:0]; +assign fifo_idata_h[255:0] = fifo_mask[1] ? fifo_idata[511:256] : 256'h0; +assign fifo_idata_l[255:0] = fifo_mask[0] ? fifo_idata[255:0] : 256'h0; +assign fifo_idata_valid_h = rd_rsp_vld & rd_rsp_rdy; +assign fifo_idata_valid_l = rd_rsp_vld & rd_rsp_rdy; +assign rd_rsp_rdy = fifo_idata_ready_h & fifo_idata_ready_l; +//assign fifo_imask_vld = rd_rsp_vld & rd_rsp_rdy; +//read data from data fifo +assign data_fifo_vld = data_fifo_vld_h & data_fifo_vld_l; +assign data_fifo_rdy_h = data_fifo_rdy; +assign data_fifo_rdy_l = data_fifo_rdy; +assign data_fifo_pd = {data_fifo_pd_h[255:0],data_fifo_pd_l[255:0]}; //{fifo_mask_out[1:0],data_fifo_pd_h[255:0],data_fifo_pd_l[255:0]}; +assign data_fifo_pop = data_fifo_vld & data_fifo_rdy; +//assign data_mask_rdy = data_fifo_pop; +assign rd_cdt_lat_fifo_pop = data_fifo_pop; +//assign qbuf_vld_h = data_fifo_vld & ( fill_half || fifo_mask_out[1]); +//assign qbuf_vld_l = data_fifo_vld & (!fill_half || fifo_mask_out[0]); +//assign qbuf_pd_h[255:0]= fill_half ? data_fifo_pd_l[255:0] : data_fifo_pd_h[255:0] ; +//assign qbuf_pd_l[255:0]= fill_half ? data_fifo_pd_h[255:0] : data_fifo_pd_l[255:0] ; +// +//&Always posedge; +// if (data_fifo_pop & ~fifo_mask_out[1]) +// fill_half <0= ~fill_half; +//&End; +/****************** Fifo L *****************/ +NV_NVDLA_RUBIK_fifo rbk_fifo_l ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (fifo_idata_ready_l) //|> w + ,.idata_pvld (fifo_idata_valid_l) //|< w + ,.idata_pd (fifo_idata_l[255:0]) //|< w + ,.odata_prdy (data_fifo_rdy_l) //|< w + ,.odata_pvld (data_fifo_vld_l) //|> w + ,.odata_pd (data_fifo_pd_l[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +/****************** Fifo H *****************/ +NV_NVDLA_RUBIK_fifo rbk_fifo_h ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (fifo_idata_ready_h) //|> w + ,.idata_pvld (fifo_idata_valid_h) //|< w + ,.idata_pd (fifo_idata_h[255:0]) //|< w + ,.odata_prdy (data_fifo_rdy_h) //|< w + ,.odata_pvld (data_fifo_vld_h) //|> w + ,.odata_pd (data_fifo_pd_h[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +/* +//fifo mask buffer +&Instance NV_NVDLA_RUBIK_mbuf rbk_mask_buffer; +&Connect nvdla_core_clk nvdla_core_clk ; +&Connect nvdla_core_rstn nvdla_core_rstn ; +&Connect idata_prdy fifo_imask_ready ; +&Connect idata_pvld fifo_imask_vld ; +&Connect idata_pd fifo_mask[1:0] ; +&Connect odata_prdy data_mask_rdy ; +&Connect odata_pvld data_mask_vld ; +&Connect odata_pd fifo_mask_out[1:0] ; +&Connect pwrbus_ram_pd pwrbus_ram_pd[31:0]; + +&Terminate data_mask_vld; +&Terminate fifo_imask_ready; + +//q0 buffer +&Instance NV_NVDLA_RUBIK_qbuf rbk_qbuf_l; +&Connect nvdla_core_clk nvdla_core_clk ; +&Connect nvdla_core_rstn nvdla_core_rstn ; +&Connect idata_prdy qbuf_rdy_l ; +&Connect idata_pvld qbuf_vld_l ; +&Connect idata_pd qbuf_pd_l[255:0] ; +&Connect odata_prdy dr2drc_q0_rdy ; +&Connect odata_pvld dr2drc_q0_vld ; +&Connect odata_pd dr2drc_q0_pd[255:0]; +&Connect pwrbus_ram_pd pwrbus_ram_pd[31:0]; + +//q1 buffer +&Instance NV_NVDLA_RUBIK_qbuf rbk_qbuf_h; +&Connect nvdla_core_clk nvdla_core_clk ; +&Connect nvdla_core_rstn nvdla_core_rstn ; +&Connect idata_prdy qbuf_rdy_h ; +&Connect idata_pvld qbuf_vld_h ; +&Connect idata_pd qbuf_pd_h[255:0] ; +&Connect odata_prdy dr2drc_q1_rdy ; +&Connect odata_pvld dr2drc_q1_vld ; +&Connect odata_pd dr2drc_q1_pd[255:0]; +&Connect pwrbus_ram_pd pwrbus_ram_pd[31:0]; +*/ +endmodule // NV_NVDLA_RUBIK_dr2drc diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v.vcp new file mode 100644 index 0000000..b972f23 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v.vcp @@ -0,0 +1,150 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_dr2drc.v +module NV_NVDLA_RUBIK_dr2drc ( + data_fifo_rdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,rd_rsp_pd //|< i + ,rd_rsp_vld //|< i + ,data_fifo_pd //|> o + ,data_fifo_vld //|> o + ,rd_cdt_lat_fifo_pop //|> o + ,rd_rsp_rdy //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input rd_rsp_vld; +input [513:0] rd_rsp_pd; +output rd_rsp_rdy; +output rd_cdt_lat_fifo_pop; +output data_fifo_vld; +output [511:0] data_fifo_pd; +input data_fifo_rdy; +//output dr2drc_q0_vld; +//output [255:0] dr2drc_q0_pd; +//input dr2drc_q0_rdy; +//output dr2drc_q1_vld; +//output [255:0] dr2drc_q1_pd; +//input dr2drc_q1_rdy; +wire [255:0] data_fifo_pd_h; +wire [255:0] data_fifo_pd_l; +wire data_fifo_pop; +wire data_fifo_rdy_h; +wire data_fifo_rdy_l; +wire data_fifo_vld_h; +wire data_fifo_vld_l; +wire [511:0] fifo_idata; +wire [255:0] fifo_idata_h; +wire [255:0] fifo_idata_l; +wire fifo_idata_ready_h; +wire fifo_idata_ready_l; +wire fifo_idata_valid_h; +wire fifo_idata_valid_l; +wire [1:0] fifo_mask; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +/////////write data to data_fifo///////////// +assign fifo_mask[1:0] = rd_rsp_pd[513:512]; +assign fifo_idata[511:0] = rd_rsp_pd[511:0]; +assign fifo_idata_h[255:0] = fifo_mask[1] ? fifo_idata[511:256] : 256'h0; +assign fifo_idata_l[255:0] = fifo_mask[0] ? fifo_idata[255:0] : 256'h0; +assign fifo_idata_valid_h = rd_rsp_vld & rd_rsp_rdy; +assign fifo_idata_valid_l = rd_rsp_vld & rd_rsp_rdy; +assign rd_rsp_rdy = fifo_idata_ready_h & fifo_idata_ready_l; +//assign fifo_imask_vld = rd_rsp_vld & rd_rsp_rdy; +//read data from data fifo +assign data_fifo_vld = data_fifo_vld_h & data_fifo_vld_l; +assign data_fifo_rdy_h = data_fifo_rdy; +assign data_fifo_rdy_l = data_fifo_rdy; +assign data_fifo_pd = {data_fifo_pd_h[255:0],data_fifo_pd_l[255:0]}; //{fifo_mask_out[1:0],data_fifo_pd_h[255:0],data_fifo_pd_l[255:0]}; +assign data_fifo_pop = data_fifo_vld & data_fifo_rdy; +//assign data_mask_rdy = data_fifo_pop; +assign rd_cdt_lat_fifo_pop = data_fifo_pop; +//assign qbuf_vld_h = data_fifo_vld & ( fill_half || fifo_mask_out[1]); +//assign qbuf_vld_l = data_fifo_vld & (!fill_half || fifo_mask_out[0]); +//assign qbuf_pd_h[255:0]= fill_half ? data_fifo_pd_l[255:0] : data_fifo_pd_h[255:0] ; +//assign qbuf_pd_l[255:0]= fill_half ? data_fifo_pd_h[255:0] : data_fifo_pd_l[255:0] ; +// +//&Always posedge; +// if (data_fifo_pop & ~fifo_mask_out[1]) +// fill_half <0= ~fill_half; +//&End; +/****************** Fifo L *****************/ +NV_NVDLA_RUBIK_fifo rbk_fifo_l ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (fifo_idata_ready_l) //|> w + ,.idata_pvld (fifo_idata_valid_l) //|< w + ,.idata_pd (fifo_idata_l[255:0]) //|< w + ,.odata_prdy (data_fifo_rdy_l) //|< w + ,.odata_pvld (data_fifo_vld_l) //|> w + ,.odata_pd (data_fifo_pd_l[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +/****************** Fifo H *****************/ +NV_NVDLA_RUBIK_fifo rbk_fifo_h ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (fifo_idata_ready_h) //|> w + ,.idata_pvld (fifo_idata_valid_h) //|< w + ,.idata_pd (fifo_idata_h[255:0]) //|< w + ,.odata_prdy (data_fifo_rdy_h) //|< w + ,.odata_pvld (data_fifo_vld_h) //|> w + ,.odata_pd (data_fifo_pd_h[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +/* +//fifo mask buffer +&Instance NV_NVDLA_RUBIK_mbuf rbk_mask_buffer; +&Connect nvdla_core_clk nvdla_core_clk ; +&Connect nvdla_core_rstn nvdla_core_rstn ; +&Connect idata_prdy fifo_imask_ready ; +&Connect idata_pvld fifo_imask_vld ; +&Connect idata_pd fifo_mask[1:0] ; +&Connect odata_prdy data_mask_rdy ; +&Connect odata_pvld data_mask_vld ; +&Connect odata_pd fifo_mask_out[1:0] ; +&Connect pwrbus_ram_pd pwrbus_ram_pd[31:0]; + +&Terminate data_mask_vld; +&Terminate fifo_imask_ready; + +//q0 buffer +&Instance NV_NVDLA_RUBIK_qbuf rbk_qbuf_l; +&Connect nvdla_core_clk nvdla_core_clk ; +&Connect nvdla_core_rstn nvdla_core_rstn ; +&Connect idata_prdy qbuf_rdy_l ; +&Connect idata_pvld qbuf_vld_l ; +&Connect idata_pd qbuf_pd_l[255:0] ; +&Connect odata_prdy dr2drc_q0_rdy ; +&Connect odata_pvld dr2drc_q0_vld ; +&Connect odata_pd dr2drc_q0_pd[255:0]; +&Connect pwrbus_ram_pd pwrbus_ram_pd[31:0]; + +//q1 buffer +&Instance NV_NVDLA_RUBIK_qbuf rbk_qbuf_h; +&Connect nvdla_core_clk nvdla_core_clk ; +&Connect nvdla_core_rstn nvdla_core_rstn ; +&Connect idata_prdy qbuf_rdy_h ; +&Connect idata_pvld qbuf_vld_h ; +&Connect idata_pd qbuf_pd_h[255:0] ; +&Connect odata_prdy dr2drc_q1_rdy ; +&Connect odata_pvld dr2drc_q1_vld ; +&Connect odata_pd dr2drc_q1_pd[255:0]; +&Connect pwrbus_ram_pd pwrbus_ram_pd[31:0]; +*/ +endmodule // NV_NVDLA_RUBIK_dr2drc diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v new file mode 100644 index 0000000..1067340 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v @@ -0,0 +1,471 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_dual_reg.v +module NV_NVDLA_RUBIK_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,contract_stride_0 + ,contract_stride_1 + ,dain_addr_high + ,dain_addr_low + ,dain_line_stride + ,dain_planar_stride + ,datain_ram_type + ,dain_surf_stride + ,daout_addr_high + ,daout_addr_low + ,daout_line_stride + ,daout_planar_stride + ,dataout_ram_type + ,daout_surf_stride + ,datain_height + ,datain_width + ,datain_channel + ,dataout_channel + ,deconv_x_stride + ,deconv_y_stride + ,in_precision + ,rubik_mode + ,op_en_trigger + ,perf_en + ,op_en + ,rd_stall_cnt + ,wr_stall_cnt + ); +wire [31:0] nvdla_rbk_d_contract_stride_0_0_out; +wire [31:0] nvdla_rbk_d_contract_stride_1_0_out; +wire [31:0] nvdla_rbk_d_dain_addr_high_0_out; +wire [31:0] nvdla_rbk_d_dain_addr_low_0_out; +wire [31:0] nvdla_rbk_d_dain_line_stride_0_out; +wire [31:0] nvdla_rbk_d_dain_planar_stride_0_out; +wire [31:0] nvdla_rbk_d_dain_ram_type_0_out; +wire [31:0] nvdla_rbk_d_dain_surf_stride_0_out; +wire [31:0] nvdla_rbk_d_daout_addr_high_0_out; +wire [31:0] nvdla_rbk_d_daout_addr_low_0_out; +wire [31:0] nvdla_rbk_d_daout_line_stride_0_out; +wire [31:0] nvdla_rbk_d_daout_planar_stride_0_out; +wire [31:0] nvdla_rbk_d_daout_ram_type_0_out; +wire [31:0] nvdla_rbk_d_daout_surf_stride_0_out; +wire [31:0] nvdla_rbk_d_datain_size_0_0_out; +wire [31:0] nvdla_rbk_d_datain_size_1_0_out; +wire [31:0] nvdla_rbk_d_dataout_size_1_0_out; +wire [31:0] nvdla_rbk_d_deconv_stride_0_out; +wire [31:0] nvdla_rbk_d_misc_cfg_0_out; +wire [31:0] nvdla_rbk_d_op_enable_0_out; +wire [31:0] nvdla_rbk_d_perf_enable_0_out; +wire [31:0] nvdla_rbk_d_perf_read_stall_0_out; +wire [31:0] nvdla_rbk_d_perf_write_stall_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [26:0] contract_stride_0; +output [26:0] contract_stride_1; +output [31:0] dain_addr_high; +output [26:0] dain_addr_low; +output [26:0] dain_line_stride; +output [26:0] dain_planar_stride; +output datain_ram_type; +output [26:0] dain_surf_stride; +output [31:0] daout_addr_high; +output [26:0] daout_addr_low; +output [26:0] daout_line_stride; +output [26:0] daout_planar_stride; +output dataout_ram_type; +output [26:0] daout_surf_stride; +output [12:0] datain_height; +output [12:0] datain_width; +output [12:0] datain_channel; +output [12:0] dataout_channel; +output [4:0] deconv_x_stride; +output [4:0] deconv_y_stride; +output [1:0] in_precision; +output [1:0] rubik_mode; +output op_en_trigger; +output perf_en; +// Read-only register inputs +input op_en; +input [31:0] rd_stall_cnt; +input [31:0] wr_stall_cnt; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [26:0] contract_stride_0; +reg [26:0] contract_stride_1; +reg [31:0] dain_addr_high; +reg [26:0] dain_addr_low; +reg [26:0] dain_line_stride; +reg [26:0] dain_planar_stride; +reg [26:0] dain_surf_stride; +reg [31:0] daout_addr_high; +reg [26:0] daout_addr_low; +reg [26:0] daout_line_stride; +reg [26:0] daout_planar_stride; +reg [26:0] daout_surf_stride; +reg [12:0] datain_channel; +reg [12:0] datain_height; +reg datain_ram_type; +reg [12:0] datain_width; +reg [12:0] dataout_channel; +reg dataout_ram_type; +reg [4:0] deconv_x_stride; +reg [4:0] deconv_y_stride; +reg [1:0] in_precision; +reg perf_en; +reg [31:0] reg_rd_data; +reg [1:0] rubik_mode; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_rbk_d_contract_stride_0_0_wren = (reg_offset_wr == (32'h10044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_contract_stride_1_0_wren = (reg_offset_wr == (32'h10048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_addr_high_0_wren = (reg_offset_wr == (32'h1001c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_addr_low_0_wren = (reg_offset_wr == (32'h10020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_line_stride_0_wren = (reg_offset_wr == (32'h10024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_planar_stride_0_wren = (reg_offset_wr == (32'h1002c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_ram_type_0_wren = (reg_offset_wr == (32'h10010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_surf_stride_0_wren = (reg_offset_wr == (32'h10028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_addr_high_0_wren = (reg_offset_wr == (32'h10038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_addr_low_0_wren = (reg_offset_wr == (32'h1003c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_line_stride_0_wren = (reg_offset_wr == (32'h10040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_planar_stride_0_wren = (reg_offset_wr == (32'h10050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_ram_type_0_wren = (reg_offset_wr == (32'h10030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_surf_stride_0_wren = (reg_offset_wr == (32'h1004c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_datain_size_0_0_wren = (reg_offset_wr == (32'h10014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_datain_size_1_0_wren = (reg_offset_wr == (32'h10018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dataout_size_1_0_wren = (reg_offset_wr == (32'h10034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_deconv_stride_0_wren = (reg_offset_wr == (32'h10054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_misc_cfg_0_wren = (reg_offset_wr == (32'h1000c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_op_enable_0_wren = (reg_offset_wr == (32'h10008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_perf_enable_0_wren = (reg_offset_wr == (32'h10058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_perf_read_stall_0_wren = (reg_offset_wr == (32'h1005c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_perf_write_stall_0_wren = (reg_offset_wr == (32'h10060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_rbk_d_contract_stride_0_0_out[31:0] = { contract_stride_0, 5'b0 }; +assign nvdla_rbk_d_contract_stride_1_0_out[31:0] = { contract_stride_1, 5'b0 }; +assign nvdla_rbk_d_dain_addr_high_0_out[31:0] = { dain_addr_high }; +assign nvdla_rbk_d_dain_addr_low_0_out[31:0] = { dain_addr_low, 5'b0 }; +assign nvdla_rbk_d_dain_line_stride_0_out[31:0] = { dain_line_stride, 5'b0 }; +assign nvdla_rbk_d_dain_planar_stride_0_out[31:0] = { dain_planar_stride, 5'b0 }; +assign nvdla_rbk_d_dain_ram_type_0_out[31:0] = { 31'b0, datain_ram_type }; +assign nvdla_rbk_d_dain_surf_stride_0_out[31:0] = { dain_surf_stride, 5'b0 }; +assign nvdla_rbk_d_daout_addr_high_0_out[31:0] = { daout_addr_high }; +assign nvdla_rbk_d_daout_addr_low_0_out[31:0] = { daout_addr_low, 5'b0 }; +assign nvdla_rbk_d_daout_line_stride_0_out[31:0] = { daout_line_stride, 5'b0 }; +assign nvdla_rbk_d_daout_planar_stride_0_out[31:0] = { daout_planar_stride, 5'b0 }; +assign nvdla_rbk_d_daout_ram_type_0_out[31:0] = { 31'b0, dataout_ram_type }; +assign nvdla_rbk_d_daout_surf_stride_0_out[31:0] = { daout_surf_stride, 5'b0 }; +assign nvdla_rbk_d_datain_size_0_0_out[31:0] = { 3'b0, datain_height, 3'b0, datain_width }; +assign nvdla_rbk_d_datain_size_1_0_out[31:0] = { 19'b0, datain_channel }; +assign nvdla_rbk_d_dataout_size_1_0_out[31:0] = { 19'b0, dataout_channel }; +assign nvdla_rbk_d_deconv_stride_0_out[31:0] = { 11'b0, deconv_y_stride, 11'b0, deconv_x_stride }; +assign nvdla_rbk_d_misc_cfg_0_out[31:0] = { 22'b0, in_precision, 6'b0, rubik_mode }; +assign nvdla_rbk_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_rbk_d_perf_enable_0_out[31:0] = { 31'b0, perf_en }; +assign nvdla_rbk_d_perf_read_stall_0_out[31:0] = { rd_stall_cnt }; +assign nvdla_rbk_d_perf_write_stall_0_out[31:0] = { wr_stall_cnt }; +assign op_en_trigger = nvdla_rbk_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_rbk_d_contract_stride_0_0_out + or nvdla_rbk_d_contract_stride_1_0_out + or nvdla_rbk_d_dain_addr_high_0_out + or nvdla_rbk_d_dain_addr_low_0_out + or nvdla_rbk_d_dain_line_stride_0_out + or nvdla_rbk_d_dain_planar_stride_0_out + or nvdla_rbk_d_dain_ram_type_0_out + or nvdla_rbk_d_dain_surf_stride_0_out + or nvdla_rbk_d_daout_addr_high_0_out + or nvdla_rbk_d_daout_addr_low_0_out + or nvdla_rbk_d_daout_line_stride_0_out + or nvdla_rbk_d_daout_planar_stride_0_out + or nvdla_rbk_d_daout_ram_type_0_out + or nvdla_rbk_d_daout_surf_stride_0_out + or nvdla_rbk_d_datain_size_0_0_out + or nvdla_rbk_d_datain_size_1_0_out + or nvdla_rbk_d_dataout_size_1_0_out + or nvdla_rbk_d_deconv_stride_0_out + or nvdla_rbk_d_misc_cfg_0_out + or nvdla_rbk_d_op_enable_0_out + or nvdla_rbk_d_perf_enable_0_out + or nvdla_rbk_d_perf_read_stall_0_out + or nvdla_rbk_d_perf_write_stall_0_out + ) begin + case (reg_offset_rd_int) + (32'h10044 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_contract_stride_0_0_out ; + end + (32'h10048 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_contract_stride_1_0_out ; + end + (32'h1001c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_addr_high_0_out ; + end + (32'h10020 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_addr_low_0_out ; + end + (32'h10024 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_line_stride_0_out ; + end + (32'h1002c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_planar_stride_0_out ; + end + (32'h10010 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_ram_type_0_out ; + end + (32'h10028 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_surf_stride_0_out ; + end + (32'h10038 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_addr_high_0_out ; + end + (32'h1003c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_addr_low_0_out ; + end + (32'h10040 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_line_stride_0_out ; + end + (32'h10050 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_planar_stride_0_out ; + end + (32'h10030 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_ram_type_0_out ; + end + (32'h1004c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_surf_stride_0_out ; + end + (32'h10014 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_datain_size_0_0_out ; + end + (32'h10018 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_datain_size_1_0_out ; + end + (32'h10034 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dataout_size_1_0_out ; + end + (32'h10054 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_deconv_stride_0_out ; + end + (32'h1000c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_misc_cfg_0_out ; + end + (32'h10008 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_op_enable_0_out ; + end + (32'h10058 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_perf_enable_0_out ; + end + (32'h1005c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_perf_read_stall_0_out ; + end + (32'h10060 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_perf_write_stall_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + contract_stride_0[26:0] <= 27'b000000000000000000000000000; + contract_stride_1[26:0] <= 27'b000000000000000000000000000; + dain_addr_high[31:0] <= 32'b00000000000000000000000000000000; + dain_addr_low[26:0] <= 27'b000000000000000000000000000; + dain_line_stride[26:0] <= 27'b000000000000000000000000000; + dain_planar_stride[26:0] <= 27'b000000000000000000000000000; + datain_ram_type <= 1'b0; + dain_surf_stride[26:0] <= 27'b000000000000000000000000000; + daout_addr_high[31:0] <= 32'b00000000000000000000000000000000; + daout_addr_low[26:0] <= 27'b000000000000000000000000000; + daout_line_stride[26:0] <= 27'b000000000000000000000000000; + daout_planar_stride[26:0] <= 27'b000000000000000000000000000; + dataout_ram_type <= 1'b0; + daout_surf_stride[26:0] <= 27'b000000000000000000000000000; + datain_height[12:0] <= 13'b0000000000000; + datain_width[12:0] <= 13'b0000000000000; + datain_channel[12:0] <= 13'b0000000000000; + dataout_channel[12:0] <= 13'b0000000000000; + deconv_x_stride[4:0] <= 5'b00000; + deconv_y_stride[4:0] <= 5'b00000; + in_precision[1:0] <= 2'b01; + rubik_mode[1:0] <= 2'b00; + perf_en <= 1'b0; + end else begin +// Register: NVDLA_RBK_D_CONTRACT_STRIDE_0_0 Field: contract_stride_0 + if (nvdla_rbk_d_contract_stride_0_0_wren) begin + contract_stride_0[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_CONTRACT_STRIDE_1_0 Field: contract_stride_1 + if (nvdla_rbk_d_contract_stride_1_0_wren) begin + contract_stride_1[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_ADDR_HIGH_0 Field: dain_addr_high + if (nvdla_rbk_d_dain_addr_high_0_wren) begin + dain_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_RBK_D_DAIN_ADDR_LOW_0 Field: dain_addr_low + if (nvdla_rbk_d_dain_addr_low_0_wren) begin + dain_addr_low[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_LINE_STRIDE_0 Field: dain_line_stride + if (nvdla_rbk_d_dain_line_stride_0_wren) begin + dain_line_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_PLANAR_STRIDE_0 Field: dain_planar_stride + if (nvdla_rbk_d_dain_planar_stride_0_wren) begin + dain_planar_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_RAM_TYPE_0 Field: datain_ram_type + if (nvdla_rbk_d_dain_ram_type_0_wren) begin + datain_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_RBK_D_DAIN_SURF_STRIDE_0 Field: dain_surf_stride + if (nvdla_rbk_d_dain_surf_stride_0_wren) begin + dain_surf_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_ADDR_HIGH_0 Field: daout_addr_high + if (nvdla_rbk_d_daout_addr_high_0_wren) begin + daout_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_RBK_D_DAOUT_ADDR_LOW_0 Field: daout_addr_low + if (nvdla_rbk_d_daout_addr_low_0_wren) begin + daout_addr_low[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_LINE_STRIDE_0 Field: daout_line_stride + if (nvdla_rbk_d_daout_line_stride_0_wren) begin + daout_line_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_PLANAR_STRIDE_0 Field: daout_planar_stride + if (nvdla_rbk_d_daout_planar_stride_0_wren) begin + daout_planar_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_RAM_TYPE_0 Field: dataout_ram_type + if (nvdla_rbk_d_daout_ram_type_0_wren) begin + dataout_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_RBK_D_DAOUT_SURF_STRIDE_0 Field: daout_surf_stride + if (nvdla_rbk_d_daout_surf_stride_0_wren) begin + daout_surf_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DATAIN_SIZE_0_0 Field: datain_height + if (nvdla_rbk_d_datain_size_0_0_wren) begin + datain_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_RBK_D_DATAIN_SIZE_0_0 Field: datain_width + if (nvdla_rbk_d_datain_size_0_0_wren) begin + datain_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_RBK_D_DATAIN_SIZE_1_0 Field: datain_channel + if (nvdla_rbk_d_datain_size_1_0_wren) begin + datain_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_RBK_D_DATAOUT_SIZE_1_0 Field: dataout_channel + if (nvdla_rbk_d_dataout_size_1_0_wren) begin + dataout_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_RBK_D_DECONV_STRIDE_0 Field: deconv_x_stride + if (nvdla_rbk_d_deconv_stride_0_wren) begin + deconv_x_stride[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_RBK_D_DECONV_STRIDE_0 Field: deconv_y_stride + if (nvdla_rbk_d_deconv_stride_0_wren) begin + deconv_y_stride[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_RBK_D_MISC_CFG_0 Field: in_precision + if (nvdla_rbk_d_misc_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[9:8]; + end +// Register: NVDLA_RBK_D_MISC_CFG_0 Field: rubik_mode + if (nvdla_rbk_d_misc_cfg_0_wren) begin + rubik_mode[1:0] <= reg_wr_data[1:0]; + end +// Not generating flops for field NVDLA_RBK_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_RBK_D_PERF_ENABLE_0 Field: perf_en + if (nvdla_rbk_d_perf_enable_0_wren) begin + perf_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_RBK_D_PERF_READ_STALL_0::rd_stall_cnt +// Not generating flops for read-only field NVDLA_RBK_D_PERF_WRITE_STALL_0::wr_stall_cnt + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h10044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_CONTRACT_STRIDE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_contract_stride_0_0_out, nvdla_rbk_d_contract_stride_0_0_out); + (32'h10048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_CONTRACT_STRIDE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_contract_stride_1_0_out, nvdla_rbk_d_contract_stride_1_0_out); + (32'h1001c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_addr_high_0_out, nvdla_rbk_d_dain_addr_high_0_out); + (32'h10020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_addr_low_0_out, nvdla_rbk_d_dain_addr_low_0_out); + (32'h10024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_line_stride_0_out, nvdla_rbk_d_dain_line_stride_0_out); + (32'h1002c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_PLANAR_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_planar_stride_0_out, nvdla_rbk_d_dain_planar_stride_0_out); + (32'h10010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_ram_type_0_out, nvdla_rbk_d_dain_ram_type_0_out); + (32'h10028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_surf_stride_0_out, nvdla_rbk_d_dain_surf_stride_0_out); + (32'h10038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_addr_high_0_out, nvdla_rbk_d_daout_addr_high_0_out); + (32'h1003c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_addr_low_0_out, nvdla_rbk_d_daout_addr_low_0_out); + (32'h10040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_line_stride_0_out, nvdla_rbk_d_daout_line_stride_0_out); + (32'h10050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_PLANAR_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_planar_stride_0_out, nvdla_rbk_d_daout_planar_stride_0_out); + (32'h10030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_ram_type_0_out, nvdla_rbk_d_daout_ram_type_0_out); + (32'h1004c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_surf_stride_0_out, nvdla_rbk_d_daout_surf_stride_0_out); + (32'h10014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DATAIN_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_datain_size_0_0_out, nvdla_rbk_d_datain_size_0_0_out); + (32'h10018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DATAIN_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_datain_size_1_0_out, nvdla_rbk_d_datain_size_1_0_out); + (32'h10034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DATAOUT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dataout_size_1_0_out, nvdla_rbk_d_dataout_size_1_0_out); + (32'h10054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DECONV_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_deconv_stride_0_out, nvdla_rbk_d_deconv_stride_0_out); + (32'h1000c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_misc_cfg_0_out, nvdla_rbk_d_misc_cfg_0_out); + (32'h10008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_op_enable_0_out, nvdla_rbk_d_op_enable_0_out); + (32'h10058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_perf_enable_0_out, nvdla_rbk_d_perf_enable_0_out); + (32'h1005c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_RBK_D_PERF_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h10060 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_RBK_D_PERF_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_RUBIK_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v.vcp new file mode 100644 index 0000000..1067340 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v.vcp @@ -0,0 +1,471 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_dual_reg.v +module NV_NVDLA_RUBIK_dual_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,contract_stride_0 + ,contract_stride_1 + ,dain_addr_high + ,dain_addr_low + ,dain_line_stride + ,dain_planar_stride + ,datain_ram_type + ,dain_surf_stride + ,daout_addr_high + ,daout_addr_low + ,daout_line_stride + ,daout_planar_stride + ,dataout_ram_type + ,daout_surf_stride + ,datain_height + ,datain_width + ,datain_channel + ,dataout_channel + ,deconv_x_stride + ,deconv_y_stride + ,in_precision + ,rubik_mode + ,op_en_trigger + ,perf_en + ,op_en + ,rd_stall_cnt + ,wr_stall_cnt + ); +wire [31:0] nvdla_rbk_d_contract_stride_0_0_out; +wire [31:0] nvdla_rbk_d_contract_stride_1_0_out; +wire [31:0] nvdla_rbk_d_dain_addr_high_0_out; +wire [31:0] nvdla_rbk_d_dain_addr_low_0_out; +wire [31:0] nvdla_rbk_d_dain_line_stride_0_out; +wire [31:0] nvdla_rbk_d_dain_planar_stride_0_out; +wire [31:0] nvdla_rbk_d_dain_ram_type_0_out; +wire [31:0] nvdla_rbk_d_dain_surf_stride_0_out; +wire [31:0] nvdla_rbk_d_daout_addr_high_0_out; +wire [31:0] nvdla_rbk_d_daout_addr_low_0_out; +wire [31:0] nvdla_rbk_d_daout_line_stride_0_out; +wire [31:0] nvdla_rbk_d_daout_planar_stride_0_out; +wire [31:0] nvdla_rbk_d_daout_ram_type_0_out; +wire [31:0] nvdla_rbk_d_daout_surf_stride_0_out; +wire [31:0] nvdla_rbk_d_datain_size_0_0_out; +wire [31:0] nvdla_rbk_d_datain_size_1_0_out; +wire [31:0] nvdla_rbk_d_dataout_size_1_0_out; +wire [31:0] nvdla_rbk_d_deconv_stride_0_out; +wire [31:0] nvdla_rbk_d_misc_cfg_0_out; +wire [31:0] nvdla_rbk_d_op_enable_0_out; +wire [31:0] nvdla_rbk_d_perf_enable_0_out; +wire [31:0] nvdla_rbk_d_perf_read_stall_0_out; +wire [31:0] nvdla_rbk_d_perf_write_stall_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [26:0] contract_stride_0; +output [26:0] contract_stride_1; +output [31:0] dain_addr_high; +output [26:0] dain_addr_low; +output [26:0] dain_line_stride; +output [26:0] dain_planar_stride; +output datain_ram_type; +output [26:0] dain_surf_stride; +output [31:0] daout_addr_high; +output [26:0] daout_addr_low; +output [26:0] daout_line_stride; +output [26:0] daout_planar_stride; +output dataout_ram_type; +output [26:0] daout_surf_stride; +output [12:0] datain_height; +output [12:0] datain_width; +output [12:0] datain_channel; +output [12:0] dataout_channel; +output [4:0] deconv_x_stride; +output [4:0] deconv_y_stride; +output [1:0] in_precision; +output [1:0] rubik_mode; +output op_en_trigger; +output perf_en; +// Read-only register inputs +input op_en; +input [31:0] rd_stall_cnt; +input [31:0] wr_stall_cnt; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [26:0] contract_stride_0; +reg [26:0] contract_stride_1; +reg [31:0] dain_addr_high; +reg [26:0] dain_addr_low; +reg [26:0] dain_line_stride; +reg [26:0] dain_planar_stride; +reg [26:0] dain_surf_stride; +reg [31:0] daout_addr_high; +reg [26:0] daout_addr_low; +reg [26:0] daout_line_stride; +reg [26:0] daout_planar_stride; +reg [26:0] daout_surf_stride; +reg [12:0] datain_channel; +reg [12:0] datain_height; +reg datain_ram_type; +reg [12:0] datain_width; +reg [12:0] dataout_channel; +reg dataout_ram_type; +reg [4:0] deconv_x_stride; +reg [4:0] deconv_y_stride; +reg [1:0] in_precision; +reg perf_en; +reg [31:0] reg_rd_data; +reg [1:0] rubik_mode; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_rbk_d_contract_stride_0_0_wren = (reg_offset_wr == (32'h10044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_contract_stride_1_0_wren = (reg_offset_wr == (32'h10048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_addr_high_0_wren = (reg_offset_wr == (32'h1001c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_addr_low_0_wren = (reg_offset_wr == (32'h10020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_line_stride_0_wren = (reg_offset_wr == (32'h10024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_planar_stride_0_wren = (reg_offset_wr == (32'h1002c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_ram_type_0_wren = (reg_offset_wr == (32'h10010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dain_surf_stride_0_wren = (reg_offset_wr == (32'h10028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_addr_high_0_wren = (reg_offset_wr == (32'h10038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_addr_low_0_wren = (reg_offset_wr == (32'h1003c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_line_stride_0_wren = (reg_offset_wr == (32'h10040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_planar_stride_0_wren = (reg_offset_wr == (32'h10050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_ram_type_0_wren = (reg_offset_wr == (32'h10030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_daout_surf_stride_0_wren = (reg_offset_wr == (32'h1004c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_datain_size_0_0_wren = (reg_offset_wr == (32'h10014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_datain_size_1_0_wren = (reg_offset_wr == (32'h10018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_dataout_size_1_0_wren = (reg_offset_wr == (32'h10034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_deconv_stride_0_wren = (reg_offset_wr == (32'h10054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_misc_cfg_0_wren = (reg_offset_wr == (32'h1000c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_op_enable_0_wren = (reg_offset_wr == (32'h10008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_perf_enable_0_wren = (reg_offset_wr == (32'h10058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_perf_read_stall_0_wren = (reg_offset_wr == (32'h1005c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_d_perf_write_stall_0_wren = (reg_offset_wr == (32'h10060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_rbk_d_contract_stride_0_0_out[31:0] = { contract_stride_0, 5'b0 }; +assign nvdla_rbk_d_contract_stride_1_0_out[31:0] = { contract_stride_1, 5'b0 }; +assign nvdla_rbk_d_dain_addr_high_0_out[31:0] = { dain_addr_high }; +assign nvdla_rbk_d_dain_addr_low_0_out[31:0] = { dain_addr_low, 5'b0 }; +assign nvdla_rbk_d_dain_line_stride_0_out[31:0] = { dain_line_stride, 5'b0 }; +assign nvdla_rbk_d_dain_planar_stride_0_out[31:0] = { dain_planar_stride, 5'b0 }; +assign nvdla_rbk_d_dain_ram_type_0_out[31:0] = { 31'b0, datain_ram_type }; +assign nvdla_rbk_d_dain_surf_stride_0_out[31:0] = { dain_surf_stride, 5'b0 }; +assign nvdla_rbk_d_daout_addr_high_0_out[31:0] = { daout_addr_high }; +assign nvdla_rbk_d_daout_addr_low_0_out[31:0] = { daout_addr_low, 5'b0 }; +assign nvdla_rbk_d_daout_line_stride_0_out[31:0] = { daout_line_stride, 5'b0 }; +assign nvdla_rbk_d_daout_planar_stride_0_out[31:0] = { daout_planar_stride, 5'b0 }; +assign nvdla_rbk_d_daout_ram_type_0_out[31:0] = { 31'b0, dataout_ram_type }; +assign nvdla_rbk_d_daout_surf_stride_0_out[31:0] = { daout_surf_stride, 5'b0 }; +assign nvdla_rbk_d_datain_size_0_0_out[31:0] = { 3'b0, datain_height, 3'b0, datain_width }; +assign nvdla_rbk_d_datain_size_1_0_out[31:0] = { 19'b0, datain_channel }; +assign nvdla_rbk_d_dataout_size_1_0_out[31:0] = { 19'b0, dataout_channel }; +assign nvdla_rbk_d_deconv_stride_0_out[31:0] = { 11'b0, deconv_y_stride, 11'b0, deconv_x_stride }; +assign nvdla_rbk_d_misc_cfg_0_out[31:0] = { 22'b0, in_precision, 6'b0, rubik_mode }; +assign nvdla_rbk_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_rbk_d_perf_enable_0_out[31:0] = { 31'b0, perf_en }; +assign nvdla_rbk_d_perf_read_stall_0_out[31:0] = { rd_stall_cnt }; +assign nvdla_rbk_d_perf_write_stall_0_out[31:0] = { wr_stall_cnt }; +assign op_en_trigger = nvdla_rbk_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_rbk_d_contract_stride_0_0_out + or nvdla_rbk_d_contract_stride_1_0_out + or nvdla_rbk_d_dain_addr_high_0_out + or nvdla_rbk_d_dain_addr_low_0_out + or nvdla_rbk_d_dain_line_stride_0_out + or nvdla_rbk_d_dain_planar_stride_0_out + or nvdla_rbk_d_dain_ram_type_0_out + or nvdla_rbk_d_dain_surf_stride_0_out + or nvdla_rbk_d_daout_addr_high_0_out + or nvdla_rbk_d_daout_addr_low_0_out + or nvdla_rbk_d_daout_line_stride_0_out + or nvdla_rbk_d_daout_planar_stride_0_out + or nvdla_rbk_d_daout_ram_type_0_out + or nvdla_rbk_d_daout_surf_stride_0_out + or nvdla_rbk_d_datain_size_0_0_out + or nvdla_rbk_d_datain_size_1_0_out + or nvdla_rbk_d_dataout_size_1_0_out + or nvdla_rbk_d_deconv_stride_0_out + or nvdla_rbk_d_misc_cfg_0_out + or nvdla_rbk_d_op_enable_0_out + or nvdla_rbk_d_perf_enable_0_out + or nvdla_rbk_d_perf_read_stall_0_out + or nvdla_rbk_d_perf_write_stall_0_out + ) begin + case (reg_offset_rd_int) + (32'h10044 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_contract_stride_0_0_out ; + end + (32'h10048 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_contract_stride_1_0_out ; + end + (32'h1001c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_addr_high_0_out ; + end + (32'h10020 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_addr_low_0_out ; + end + (32'h10024 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_line_stride_0_out ; + end + (32'h1002c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_planar_stride_0_out ; + end + (32'h10010 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_ram_type_0_out ; + end + (32'h10028 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dain_surf_stride_0_out ; + end + (32'h10038 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_addr_high_0_out ; + end + (32'h1003c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_addr_low_0_out ; + end + (32'h10040 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_line_stride_0_out ; + end + (32'h10050 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_planar_stride_0_out ; + end + (32'h10030 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_ram_type_0_out ; + end + (32'h1004c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_daout_surf_stride_0_out ; + end + (32'h10014 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_datain_size_0_0_out ; + end + (32'h10018 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_datain_size_1_0_out ; + end + (32'h10034 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_dataout_size_1_0_out ; + end + (32'h10054 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_deconv_stride_0_out ; + end + (32'h1000c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_misc_cfg_0_out ; + end + (32'h10008 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_op_enable_0_out ; + end + (32'h10058 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_perf_enable_0_out ; + end + (32'h1005c & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_perf_read_stall_0_out ; + end + (32'h10060 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_d_perf_write_stall_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + contract_stride_0[26:0] <= 27'b000000000000000000000000000; + contract_stride_1[26:0] <= 27'b000000000000000000000000000; + dain_addr_high[31:0] <= 32'b00000000000000000000000000000000; + dain_addr_low[26:0] <= 27'b000000000000000000000000000; + dain_line_stride[26:0] <= 27'b000000000000000000000000000; + dain_planar_stride[26:0] <= 27'b000000000000000000000000000; + datain_ram_type <= 1'b0; + dain_surf_stride[26:0] <= 27'b000000000000000000000000000; + daout_addr_high[31:0] <= 32'b00000000000000000000000000000000; + daout_addr_low[26:0] <= 27'b000000000000000000000000000; + daout_line_stride[26:0] <= 27'b000000000000000000000000000; + daout_planar_stride[26:0] <= 27'b000000000000000000000000000; + dataout_ram_type <= 1'b0; + daout_surf_stride[26:0] <= 27'b000000000000000000000000000; + datain_height[12:0] <= 13'b0000000000000; + datain_width[12:0] <= 13'b0000000000000; + datain_channel[12:0] <= 13'b0000000000000; + dataout_channel[12:0] <= 13'b0000000000000; + deconv_x_stride[4:0] <= 5'b00000; + deconv_y_stride[4:0] <= 5'b00000; + in_precision[1:0] <= 2'b01; + rubik_mode[1:0] <= 2'b00; + perf_en <= 1'b0; + end else begin +// Register: NVDLA_RBK_D_CONTRACT_STRIDE_0_0 Field: contract_stride_0 + if (nvdla_rbk_d_contract_stride_0_0_wren) begin + contract_stride_0[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_CONTRACT_STRIDE_1_0 Field: contract_stride_1 + if (nvdla_rbk_d_contract_stride_1_0_wren) begin + contract_stride_1[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_ADDR_HIGH_0 Field: dain_addr_high + if (nvdla_rbk_d_dain_addr_high_0_wren) begin + dain_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_RBK_D_DAIN_ADDR_LOW_0 Field: dain_addr_low + if (nvdla_rbk_d_dain_addr_low_0_wren) begin + dain_addr_low[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_LINE_STRIDE_0 Field: dain_line_stride + if (nvdla_rbk_d_dain_line_stride_0_wren) begin + dain_line_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_PLANAR_STRIDE_0 Field: dain_planar_stride + if (nvdla_rbk_d_dain_planar_stride_0_wren) begin + dain_planar_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAIN_RAM_TYPE_0 Field: datain_ram_type + if (nvdla_rbk_d_dain_ram_type_0_wren) begin + datain_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_RBK_D_DAIN_SURF_STRIDE_0 Field: dain_surf_stride + if (nvdla_rbk_d_dain_surf_stride_0_wren) begin + dain_surf_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_ADDR_HIGH_0 Field: daout_addr_high + if (nvdla_rbk_d_daout_addr_high_0_wren) begin + daout_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_RBK_D_DAOUT_ADDR_LOW_0 Field: daout_addr_low + if (nvdla_rbk_d_daout_addr_low_0_wren) begin + daout_addr_low[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_LINE_STRIDE_0 Field: daout_line_stride + if (nvdla_rbk_d_daout_line_stride_0_wren) begin + daout_line_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_PLANAR_STRIDE_0 Field: daout_planar_stride + if (nvdla_rbk_d_daout_planar_stride_0_wren) begin + daout_planar_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DAOUT_RAM_TYPE_0 Field: dataout_ram_type + if (nvdla_rbk_d_daout_ram_type_0_wren) begin + dataout_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_RBK_D_DAOUT_SURF_STRIDE_0 Field: daout_surf_stride + if (nvdla_rbk_d_daout_surf_stride_0_wren) begin + daout_surf_stride[26:0] <= reg_wr_data[31:5]; + end +// Register: NVDLA_RBK_D_DATAIN_SIZE_0_0 Field: datain_height + if (nvdla_rbk_d_datain_size_0_0_wren) begin + datain_height[12:0] <= reg_wr_data[28:16]; + end +// Register: NVDLA_RBK_D_DATAIN_SIZE_0_0 Field: datain_width + if (nvdla_rbk_d_datain_size_0_0_wren) begin + datain_width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_RBK_D_DATAIN_SIZE_1_0 Field: datain_channel + if (nvdla_rbk_d_datain_size_1_0_wren) begin + datain_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_RBK_D_DATAOUT_SIZE_1_0 Field: dataout_channel + if (nvdla_rbk_d_dataout_size_1_0_wren) begin + dataout_channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_RBK_D_DECONV_STRIDE_0 Field: deconv_x_stride + if (nvdla_rbk_d_deconv_stride_0_wren) begin + deconv_x_stride[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_RBK_D_DECONV_STRIDE_0 Field: deconv_y_stride + if (nvdla_rbk_d_deconv_stride_0_wren) begin + deconv_y_stride[4:0] <= reg_wr_data[20:16]; + end +// Register: NVDLA_RBK_D_MISC_CFG_0 Field: in_precision + if (nvdla_rbk_d_misc_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[9:8]; + end +// Register: NVDLA_RBK_D_MISC_CFG_0 Field: rubik_mode + if (nvdla_rbk_d_misc_cfg_0_wren) begin + rubik_mode[1:0] <= reg_wr_data[1:0]; + end +// Not generating flops for field NVDLA_RBK_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_RBK_D_PERF_ENABLE_0 Field: perf_en + if (nvdla_rbk_d_perf_enable_0_wren) begin + perf_en <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_RBK_D_PERF_READ_STALL_0::rd_stall_cnt +// Not generating flops for read-only field NVDLA_RBK_D_PERF_WRITE_STALL_0::wr_stall_cnt + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h10044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_CONTRACT_STRIDE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_contract_stride_0_0_out, nvdla_rbk_d_contract_stride_0_0_out); + (32'h10048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_CONTRACT_STRIDE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_contract_stride_1_0_out, nvdla_rbk_d_contract_stride_1_0_out); + (32'h1001c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_addr_high_0_out, nvdla_rbk_d_dain_addr_high_0_out); + (32'h10020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_addr_low_0_out, nvdla_rbk_d_dain_addr_low_0_out); + (32'h10024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_line_stride_0_out, nvdla_rbk_d_dain_line_stride_0_out); + (32'h1002c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_PLANAR_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_planar_stride_0_out, nvdla_rbk_d_dain_planar_stride_0_out); + (32'h10010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_ram_type_0_out, nvdla_rbk_d_dain_ram_type_0_out); + (32'h10028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAIN_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dain_surf_stride_0_out, nvdla_rbk_d_dain_surf_stride_0_out); + (32'h10038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_addr_high_0_out, nvdla_rbk_d_daout_addr_high_0_out); + (32'h1003c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_addr_low_0_out, nvdla_rbk_d_daout_addr_low_0_out); + (32'h10040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_line_stride_0_out, nvdla_rbk_d_daout_line_stride_0_out); + (32'h10050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_PLANAR_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_planar_stride_0_out, nvdla_rbk_d_daout_planar_stride_0_out); + (32'h10030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_RAM_TYPE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_ram_type_0_out, nvdla_rbk_d_daout_ram_type_0_out); + (32'h1004c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DAOUT_SURF_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_daout_surf_stride_0_out, nvdla_rbk_d_daout_surf_stride_0_out); + (32'h10014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DATAIN_SIZE_0_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_datain_size_0_0_out, nvdla_rbk_d_datain_size_0_0_out); + (32'h10018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DATAIN_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_datain_size_1_0_out, nvdla_rbk_d_datain_size_1_0_out); + (32'h10034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DATAOUT_SIZE_1_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_dataout_size_1_0_out, nvdla_rbk_d_dataout_size_1_0_out); + (32'h10054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_DECONV_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_deconv_stride_0_out, nvdla_rbk_d_deconv_stride_0_out); + (32'h1000c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_MISC_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_misc_cfg_0_out, nvdla_rbk_d_misc_cfg_0_out); + (32'h10008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_op_enable_0_out, nvdla_rbk_d_op_enable_0_out); + (32'h10058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_d_perf_enable_0_out, nvdla_rbk_d_perf_enable_0_out); + (32'h1005c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_RBK_D_PERF_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'h10060 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_RBK_D_PERF_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_RUBIK_dual_reg diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v new file mode 100644 index 0000000..e8ed06b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v @@ -0,0 +1,641 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld +`ifdef FV_RAND_WR_PAUSE + , idata_pause +`endif + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +`ifdef FV_RAND_WR_PAUSE +input idata_pause; +`endif +input [255:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [255:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg [255:0] idata_pd_in; // registered idata_pd +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || idata_pause ; +`else +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge nvdla_core_clk ) begin + if ( !wr_busy_in && idata_pvld ) begin + idata_pd_in <= idata_pd; + end +//synopsys translate_off + else if ( !(!wr_busy_in && idata_pvld) ) begin + end else begin + idata_pd_in <= {256{`x_or_0}}; + end +//synopsys translate_on +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] idata_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 7'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [6:0] idata_adr; // current write address +wire [6:0] odata_adr_p; // read address to use for ram +wire [255:0] odata_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x256 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( idata_adr ) + , .we ( wr_pushing ) + , .di ( idata_pd_in ) + , .ra ( odata_adr_p ) + , .re ( rd_enable ) + , .dout ( odata_pd_p ) + , .ore ( ore ) + ); +// next idata_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (idata_adr == 7'd79) ? 7'd0 : (idata_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + idata_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] odata_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (odata_adr == 7'd79) ? 7'd0 : (odata_adr + 1'd1); // spyglass disable W484 +assign odata_adr_p = rd_popping ? rd_adr_next : odata_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [6:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~odata_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 7'd0; + odata_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + odata_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +assign odata_pd = odata_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( idata_pvld && !(!idata_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_RUBIK_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v.vcp new file mode 100644 index 0000000..e8ed06b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v.vcp @@ -0,0 +1,641 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld +`ifdef FV_RAND_WR_PAUSE + , idata_pause +`endif + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +`ifdef FV_RAND_WR_PAUSE +input idata_pause; +`endif +input [255:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [255:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg [255:0] idata_pd_in; // registered idata_pd +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || idata_pause ; +`else +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge nvdla_core_clk ) begin + if ( !wr_busy_in && idata_pvld ) begin + idata_pd_in <= idata_pd; + end +//synopsys translate_off + else if ( !(!wr_busy_in && idata_pvld) ) begin + end else begin + idata_pd_in <= {256{`x_or_0}}; + end +//synopsys translate_on +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] idata_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 7'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [6:0] idata_adr; // current write address +wire [6:0] odata_adr_p; // read address to use for ram +wire [255:0] odata_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x256 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( idata_adr ) + , .we ( wr_pushing ) + , .di ( idata_pd_in ) + , .ra ( odata_adr_p ) + , .re ( rd_enable ) + , .dout ( odata_pd_p ) + , .ore ( ore ) + ); +// next idata_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (idata_adr == 7'd79) ? 7'd0 : (idata_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + idata_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] odata_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (odata_adr == 7'd79) ? 7'd0 : (odata_adr + 1'd1); // spyglass disable W484 +assign odata_adr_p = rd_popping ? rd_adr_next : odata_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [6:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~odata_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 7'd0; + odata_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + odata_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +assign odata_pd = odata_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( idata_pvld && !(!idata_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_RUBIK_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v new file mode 100644 index 0000000..d806f3d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v @@ -0,0 +1,836 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_intr.v +module NV_NVDLA_RUBIK_intr ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2reg_consumer //|< i + ,dp2reg_done //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_op_en //|< i + ,wr_rsp_complete //|< i + ,rubik2glb_done_intr_pd //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_consumer; +input dp2reg_done; +input [31:0] pwrbus_ram_pd; +input reg2dp_op_en; +input wr_rsp_complete; +output [1:0] rubik2glb_done_intr_pd; +reg [1:0] rubik2glb_done_intr_pd; +wire layer0_done; +wire layer1_done; +wire op_done_rd_pd; +wire op_done_rd_prdy; +wire op_done_rd_pvld; +wire op_done_wr_pd; +wire op_done_wr_pvld; +wire [1:0] rubik_done_intr_w; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//&Always posedge; +// if (dp2reg_done) +// dp2reg_done_flg <0= ~dp2reg_done_flg; +//&End; +assign op_done_wr_pvld = reg2dp_op_en & dp2reg_done; +assign op_done_wr_pd = dp2reg_consumer; +assign op_done_rd_prdy = wr_rsp_complete; +NV_NVDLA_RUBIK_opdone_fifo rbk_opdone_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_done_wr_prdy () //|> ? + ,.op_done_wr_pvld (op_done_wr_pvld) //|< w + ,.op_done_wr_pd (op_done_wr_pd) //|< w + ,.op_done_rd_prdy (op_done_rd_prdy) //|< w + ,.op_done_rd_pvld (op_done_rd_pvld) //|> w + ,.op_done_rd_pd (op_done_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign layer0_done = op_done_rd_pvld & op_done_rd_prdy & !op_done_rd_pd; +assign layer1_done = op_done_rd_pvld & op_done_rd_prdy & op_done_rd_pd; +//Write done interrupt +assign rubik_done_intr_w[0] = wr_rsp_complete & layer0_done; //~dp2reg_consumer; +assign rubik_done_intr_w[1] = wr_rsp_complete & layer1_done; //dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rubik2glb_done_intr_pd[1:0] <= {2{1'b0}}; + end else begin + rubik2glb_done_intr_pd[1:0] <= rubik_done_intr_w; + end +end +endmodule // NV_NVDLA_RUBIK_intr +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_RUBIK_opdone_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus op_done_wr -rd_pipebus op_done_rd -d 4 -w 1 -rd_reg -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_opdone_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , op_done_wr_prdy + , op_done_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , op_done_wr_pause +`endif + , op_done_wr_pd + , op_done_rd_prdy + , op_done_rd_pvld + , op_done_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output op_done_wr_prdy; +input op_done_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input op_done_wr_pause; +`endif +input op_done_wr_pd; +input op_done_rd_prdy; +output op_done_rd_pvld; +output op_done_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg op_done_wr_busy_int; // copy for internal use +assign op_done_wr_prdy = !op_done_wr_busy_int; +assign wr_reserving = op_done_wr_pvld && !op_done_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [2:0] op_done_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? op_done_wr_count : (op_done_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (op_done_wr_count + 1'd1) : op_done_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire op_done_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check op_done_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || op_done_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire op_done_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check op_done_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_wr_busy_int <= 1'b0; + op_done_wr_count <= 3'd0; + end else begin + op_done_wr_busy_int <= op_done_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + op_done_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + op_done_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as op_done_wr_pvld +// +// RAM +// +reg [1:0] op_done_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + op_done_wr_adr <= op_done_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] op_done_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire op_done_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( op_done_wr_pd ) + , .we ( ram_we ) + , .wa ( op_done_wr_adr ) + , .ra ( op_done_rd_adr ) + , .dout ( op_done_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = op_done_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + op_done_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + op_done_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg op_done_rd_pvld_p; // data out of fifo is valid +reg op_done_rd_pvld_int; // internal copy of op_done_rd_pvld +assign op_done_rd_pvld = op_done_rd_pvld_int; +assign rd_popping = op_done_rd_pvld_p && !(op_done_rd_pvld_int && !op_done_rd_prdy); +reg [2:0] op_done_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? op_done_rd_count_p : + (op_done_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (op_done_rd_count_p + 1'd1) : + op_done_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_rd_count_p <= 3'd0; + op_done_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + op_done_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + op_done_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + op_done_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + op_done_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg op_done_rd_pd; // output data register +wire rd_req_next = (op_done_rd_pvld_p || (op_done_rd_pvld_int && !op_done_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_rd_pvld_int <= 1'b0; + end else begin + op_done_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + op_done_rd_pd <= op_done_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + op_done_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (op_done_wr_pvld && !op_done_wr_busy_int) || (op_done_wr_busy_int != op_done_wr_busy_next)) || (rd_pushing || rd_popping || (op_done_rd_pvld_int && op_done_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_opdone_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_opdone_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( op_done_wr_pvld && !(!op_done_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, op_done_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_opdone_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_RUBIK_opdone_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [0:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [0:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [0:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [0:0] ram_ff0; +reg [0:0] ram_ff1; +reg [0:0] ram_ff2; +reg [0:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [0:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {1{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [0:0] Di0; +input [1:0] Ra0; +output [0:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 1'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [0:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [0:0] Q0 = mem[0]; +wire [0:0] Q1 = mem[1]; +wire [0:0] Q2 = mem[2]; +wire [0:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1] } +endmodule // vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +//vmw: Memory vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +//vmw: Address-size 2 +//vmw: Data-size 1 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[0:0] data0[0:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[0:0] data1[0:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v.vcp new file mode 100644 index 0000000..d806f3d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v.vcp @@ -0,0 +1,836 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_intr.v +module NV_NVDLA_RUBIK_intr ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dp2reg_consumer //|< i + ,dp2reg_done //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_op_en //|< i + ,wr_rsp_complete //|< i + ,rubik2glb_done_intr_pd //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_consumer; +input dp2reg_done; +input [31:0] pwrbus_ram_pd; +input reg2dp_op_en; +input wr_rsp_complete; +output [1:0] rubik2glb_done_intr_pd; +reg [1:0] rubik2glb_done_intr_pd; +wire layer0_done; +wire layer1_done; +wire op_done_rd_pd; +wire op_done_rd_prdy; +wire op_done_rd_pvld; +wire op_done_wr_pd; +wire op_done_wr_pvld; +wire [1:0] rubik_done_intr_w; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//&Always posedge; +// if (dp2reg_done) +// dp2reg_done_flg <0= ~dp2reg_done_flg; +//&End; +assign op_done_wr_pvld = reg2dp_op_en & dp2reg_done; +assign op_done_wr_pd = dp2reg_consumer; +assign op_done_rd_prdy = wr_rsp_complete; +NV_NVDLA_RUBIK_opdone_fifo rbk_opdone_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_done_wr_prdy () //|> ? + ,.op_done_wr_pvld (op_done_wr_pvld) //|< w + ,.op_done_wr_pd (op_done_wr_pd) //|< w + ,.op_done_rd_prdy (op_done_rd_prdy) //|< w + ,.op_done_rd_pvld (op_done_rd_pvld) //|> w + ,.op_done_rd_pd (op_done_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign layer0_done = op_done_rd_pvld & op_done_rd_prdy & !op_done_rd_pd; +assign layer1_done = op_done_rd_pvld & op_done_rd_prdy & op_done_rd_pd; +//Write done interrupt +assign rubik_done_intr_w[0] = wr_rsp_complete & layer0_done; //~dp2reg_consumer; +assign rubik_done_intr_w[1] = wr_rsp_complete & layer1_done; //dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rubik2glb_done_intr_pd[1:0] <= {2{1'b0}}; + end else begin + rubik2glb_done_intr_pd[1:0] <= rubik_done_intr_w; + end +end +endmodule // NV_NVDLA_RUBIK_intr +// +// AUTOMATICALLY GENERATED -- DO NOT EDIT OR CHECK IN +// +// /home/nvtools/engr/2017/03/11_05_00_06/nvtools/scripts/fifogen +// fifogen -input_config_yaml ../../../../../../../socd/ip_chip_tools/1.0/defs/public/fifogen/golden/tlit5/fifogen.yml -no_make_ram -no_make_ram -stdout -m NV_NVDLA_RUBIK_opdone_fifo -clk_name nvdla_core_clk -reset_name nvdla_core_rstn -wr_pipebus op_done_wr -rd_pipebus op_done_rd -d 4 -w 1 -rd_reg -ram ff [Chosen ram type: ff - fifogen_flops (user specified, thus no other ram type is allowed)] +// chip config vars: assertion_module_prefix=nv_ strict_synchronizers=1 strict_synchronizers_use_lib_cells=1 strict_synchronizers_use_tm_lib_cells=1 strict_sync_randomizer=1 assertion_message_prefix=FIFOGEN_ASSERTION allow_async_fifola=0 ignore_ramgen_fifola_variant=1 uses_p_SSYNC=0 uses_prand=1 uses_rammake_inc=1 use_x_or_0=1 force_wr_reg_gated=1 no_force_reset=1 no_timescale=1 no_pli_ifdef=1 requires_full_throughput=1 ram_auto_ff_bits_cutoff=16 ram_auto_ff_width_cutoff=2 ram_auto_ff_width_cutoff_max_depth=32 ram_auto_ff_depth_cutoff=-1 ram_auto_ff_no_la2_depth_cutoff=5 ram_auto_la2_width_cutoff=8 ram_auto_la2_width_cutoff_max_depth=56 ram_auto_la2_depth_cutoff=16 flopram_emu_model=1 dslp_single_clamp_port=1 dslp_clamp_port=1 slp_single_clamp_port=1 slp_clamp_port=1 master_clk_gated=1 clk_gate_module=NV_CLK_gate_power redundant_timing_flops=0 hot_reset_async_force_ports_and_loopback=1 ram_sleep_en_width=1 async_cdc_reg_id=NV_AFIFO_ rd_reg_default_for_async=1 async_ram_instance_prefix=NV_ASYNC_RAM_ allow_rd_busy_reg_warning=0 do_dft_xelim_gating=1 add_dft_xelim_wr_clkgate=1 add_dft_xelim_rd_clkgate=1 +// +// leda B_3208_NV OFF -- Unequal length LHS and RHS in assignment +// leda B_1405 OFF -- 2 asynchronous resets in this unit detected +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_opdone_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , op_done_wr_prdy + , op_done_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , op_done_wr_pause +`endif + , op_done_wr_pd + , op_done_rd_prdy + , op_done_rd_pvld + , op_done_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output op_done_wr_prdy; +input op_done_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input op_done_wr_pause; +`endif +input op_done_wr_pd; +input op_done_rd_prdy; +output op_done_rd_pvld; +output op_done_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg op_done_wr_busy_int; // copy for internal use +assign op_done_wr_prdy = !op_done_wr_busy_int; +assign wr_reserving = op_done_wr_pvld && !op_done_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [2:0] op_done_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? op_done_wr_count : (op_done_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (op_done_wr_count + 1'd1) : op_done_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire op_done_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check op_done_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || op_done_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire op_done_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check op_done_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_wr_busy_int <= 1'b0; + op_done_wr_count <= 3'd0; + end else begin + op_done_wr_busy_int <= op_done_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + op_done_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + op_done_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as op_done_wr_pvld +// +// RAM +// +reg [1:0] op_done_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + op_done_wr_adr <= op_done_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +reg [1:0] op_done_rd_adr; // read address this cycle +wire ram_we = wr_pushing; // note: write occurs next cycle +wire op_done_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( op_done_wr_pd ) + , .we ( ram_we ) + , .wa ( op_done_wr_adr ) + , .ra ( op_done_rd_adr ) + , .dout ( op_done_rd_pd_p ) + ); +wire rd_popping; // read side doing pop this cycle? +wire [1:0] rd_adr_next_popping = op_done_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + op_done_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + op_done_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg op_done_rd_pvld_p; // data out of fifo is valid +reg op_done_rd_pvld_int; // internal copy of op_done_rd_pvld +assign op_done_rd_pvld = op_done_rd_pvld_int; +assign rd_popping = op_done_rd_pvld_p && !(op_done_rd_pvld_int && !op_done_rd_prdy); +reg [2:0] op_done_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? op_done_rd_count_p : + (op_done_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (op_done_rd_count_p + 1'd1) : + op_done_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_rd_count_p <= 3'd0; + op_done_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + op_done_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + op_done_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + op_done_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + op_done_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +reg op_done_rd_pd; // output data register +wire rd_req_next = (op_done_rd_pvld_p || (op_done_rd_pvld_int && !op_done_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + op_done_rd_pvld_int <= 1'b0; + end else begin + op_done_rd_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + op_done_rd_pd <= op_done_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + op_done_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (op_done_wr_pvld && !op_done_wr_busy_int) || (op_done_wr_busy_int != op_done_wr_busy_next)) || (rd_pushing || rd_popping || (op_done_rd_pvld_int && op_done_rd_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_opdone_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_opdone_fifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_opdone_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( op_done_wr_pvld && !(!op_done_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, op_done_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_opdone_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_RUBIK_opdone_fifo +// +// Flop-Based RAM +// +module NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [0:0] di; +input we; +input [1:0] wa; +input [1:0] ra; +output [0:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [0:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra ) + , .Do0( dout ) + ); +`else +reg [0:0] ram_ff0; +reg [0:0] ram_ff1; +reg [0:0] ram_ff2; +reg [0:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [0:0] dout; +always @(*) begin + case( ra ) + 2'd0: dout = ram_ff0; + 2'd1: dout = ram_ff1; + 2'd2: dout = ram_ff2; + 2'd3: dout = ram_ff3; +//VCS coverage off + default: dout = {1{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [0:0] Di0; +input [1:0] Ra0; +output [0:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 1'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [0:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [0:0] Q0 = mem[0]; +wire [0:0] Q1 = mem[1]; +wire [0:0] Q2 = mem[2]; +wire [0:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1] } +endmodule // vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +//vmw: Memory vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +//vmw: Address-size 2 +//vmw: Data-size 1 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[0:0] data0[0:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[0:0] data1[0:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v new file mode 100644 index 0000000..4befcef --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v @@ -0,0 +1,872 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2rbk_req_pd //|< i + ,csb2rbk_req_pvld //|< i + ,dp2reg_d0_rd_stall_cnt //|< i + ,dp2reg_d0_wr_stall_cnt //|< i + ,dp2reg_d1_rd_stall_cnt //|< i + ,dp2reg_d1_wr_stall_cnt //|< i + ,dp2reg_done //|< i + ,csb2rbk_req_prdy //|> o + ,dp2reg_consumer //|> o + ,rbk2csb_resp_pd //|> o + ,rbk2csb_resp_valid //|> o + ,reg2dp_contract_stride_0 //|> o + ,reg2dp_contract_stride_1 //|> o + ,reg2dp_dain_addr_high //|> o + ,reg2dp_dain_addr_low //|> o + ,reg2dp_dain_line_stride //|> o + ,reg2dp_dain_planar_stride //|> o + ,reg2dp_dain_surf_stride //|> o + ,reg2dp_daout_addr_high //|> o + ,reg2dp_daout_addr_low //|> o + ,reg2dp_daout_line_stride //|> o + ,reg2dp_daout_planar_stride //|> o + ,reg2dp_daout_surf_stride //|> o + ,reg2dp_datain_channel //|> o + ,reg2dp_datain_height //|> o + ,reg2dp_datain_ram_type //|> o + ,reg2dp_datain_width //|> o + ,reg2dp_dataout_channel //|> o + ,reg2dp_dataout_ram_type //|> o + ,reg2dp_deconv_x_stride //|> o + ,reg2dp_deconv_y_stride //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_op_en //|> o + ,reg2dp_perf_en //|> o + ,reg2dp_rubik_mode //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2rbk_req_pd; +input csb2rbk_req_pvld; +input [31:0] dp2reg_d0_rd_stall_cnt; +input [31:0] dp2reg_d0_wr_stall_cnt; +input [31:0] dp2reg_d1_rd_stall_cnt; +input [31:0] dp2reg_d1_wr_stall_cnt; +input dp2reg_done; +output csb2rbk_req_prdy; +output dp2reg_consumer; +output [33:0] rbk2csb_resp_pd; +output rbk2csb_resp_valid; +output [26:0] reg2dp_contract_stride_0; +output [26:0] reg2dp_contract_stride_1; +output [31:0] reg2dp_dain_addr_high; +output [26:0] reg2dp_dain_addr_low; +output [26:0] reg2dp_dain_line_stride; +output [26:0] reg2dp_dain_planar_stride; +output [26:0] reg2dp_dain_surf_stride; +output [31:0] reg2dp_daout_addr_high; +output [26:0] reg2dp_daout_addr_low; +output [26:0] reg2dp_daout_line_stride; +output [26:0] reg2dp_daout_planar_stride; +output [26:0] reg2dp_daout_surf_stride; +output [12:0] reg2dp_datain_channel; +output [12:0] reg2dp_datain_height; +output reg2dp_datain_ram_type; +output [12:0] reg2dp_datain_width; +output [12:0] reg2dp_dataout_channel; +output reg2dp_dataout_ram_type; +output [4:0] reg2dp_deconv_x_stride; +output [4:0] reg2dp_deconv_y_stride; +output [1:0] reg2dp_in_precision; +output reg2dp_op_en; +output reg2dp_perf_en; +output [1:0] reg2dp_rubik_mode; +output [2:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [26:0] reg2dp_d0_contract_stride_0; +wire [26:0] reg2dp_d0_contract_stride_1; +wire [31:0] reg2dp_d0_dain_addr_high; +wire [26:0] reg2dp_d0_dain_addr_low; +wire [26:0] reg2dp_d0_dain_line_stride; +wire [26:0] reg2dp_d0_dain_planar_stride; +wire [26:0] reg2dp_d0_dain_surf_stride; +wire [31:0] reg2dp_d0_daout_addr_high; +wire [26:0] reg2dp_d0_daout_addr_low; +wire [26:0] reg2dp_d0_daout_line_stride; +wire [26:0] reg2dp_d0_daout_planar_stride; +wire [26:0] reg2dp_d0_daout_surf_stride; +wire [12:0] reg2dp_d0_datain_channel; +wire [12:0] reg2dp_d0_datain_height; +wire reg2dp_d0_datain_ram_type; +wire [12:0] reg2dp_d0_datain_width; +wire [12:0] reg2dp_d0_dataout_channel; +wire reg2dp_d0_dataout_ram_type; +wire [4:0] reg2dp_d0_deconv_x_stride; +wire [4:0] reg2dp_d0_deconv_y_stride; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_op_en_trigger; +wire reg2dp_d0_perf_en; +wire [1:0] reg2dp_d0_rubik_mode; +wire [26:0] reg2dp_d1_contract_stride_0; +wire [26:0] reg2dp_d1_contract_stride_1; +wire [31:0] reg2dp_d1_dain_addr_high; +wire [26:0] reg2dp_d1_dain_addr_low; +wire [26:0] reg2dp_d1_dain_line_stride; +wire [26:0] reg2dp_d1_dain_planar_stride; +wire [26:0] reg2dp_d1_dain_surf_stride; +wire [31:0] reg2dp_d1_daout_addr_high; +wire [26:0] reg2dp_d1_daout_addr_low; +wire [26:0] reg2dp_d1_daout_line_stride; +wire [26:0] reg2dp_d1_daout_planar_stride; +wire [26:0] reg2dp_d1_daout_surf_stride; +wire [12:0] reg2dp_d1_datain_channel; +wire [12:0] reg2dp_d1_datain_height; +wire reg2dp_d1_datain_ram_type; +wire [12:0] reg2dp_d1_datain_width; +wire [12:0] reg2dp_d1_dataout_channel; +wire reg2dp_d1_dataout_ram_type; +wire [4:0] reg2dp_d1_deconv_x_stride; +wire [4:0] reg2dp_d1_deconv_y_stride; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_op_en_trigger; +wire reg2dp_d1_perf_en; +wire [1:0] reg2dp_d1_rubik_mode; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [2:0] slcg_op_en_d0; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [33:0] rbk2csb_resp_pd; +reg rbk2csb_resp_valid; +reg [26:0] reg2dp_contract_stride_0; +reg [26:0] reg2dp_contract_stride_1; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [31:0] reg2dp_dain_addr_high; +reg [26:0] reg2dp_dain_addr_low; +reg [26:0] reg2dp_dain_line_stride; +reg [26:0] reg2dp_dain_planar_stride; +reg [26:0] reg2dp_dain_surf_stride; +reg [31:0] reg2dp_daout_addr_high; +reg [26:0] reg2dp_daout_addr_low; +reg [26:0] reg2dp_daout_line_stride; +reg [26:0] reg2dp_daout_planar_stride; +reg [26:0] reg2dp_daout_surf_stride; +reg [12:0] reg2dp_datain_channel; +reg [12:0] reg2dp_datain_height; +reg reg2dp_datain_ram_type; +reg [12:0] reg2dp_datain_width; +reg [12:0] reg2dp_dataout_channel; +reg reg2dp_dataout_ram_type; +reg [4:0] reg2dp_deconv_x_stride; +reg [4:0] reg2dp_deconv_y_stride; +reg [1:0] reg2dp_in_precision; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg reg2dp_perf_en; +reg [1:0] reg2dp_rubik_mode; +reg [62:0] req_pd; +reg req_pvld; +reg [2:0] slcg_op_en_d1; +reg [2:0] slcg_op_en_d2; +reg [2:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_RUBIK_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< o + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_RUBIK_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.contract_stride_0 (reg2dp_d0_contract_stride_0[26:0]) //|> w + ,.contract_stride_1 (reg2dp_d0_contract_stride_1[26:0]) //|> w + ,.dain_addr_high (reg2dp_d0_dain_addr_high[31:0]) //|> w + ,.dain_addr_low (reg2dp_d0_dain_addr_low[26:0]) //|> w + ,.dain_line_stride (reg2dp_d0_dain_line_stride[26:0]) //|> w + ,.dain_planar_stride (reg2dp_d0_dain_planar_stride[26:0]) //|> w + ,.datain_ram_type (reg2dp_d0_datain_ram_type) //|> w + ,.dain_surf_stride (reg2dp_d0_dain_surf_stride[26:0]) //|> w + ,.daout_addr_high (reg2dp_d0_daout_addr_high[31:0]) //|> w + ,.daout_addr_low (reg2dp_d0_daout_addr_low[26:0]) //|> w + ,.daout_line_stride (reg2dp_d0_daout_line_stride[26:0]) //|> w + ,.daout_planar_stride (reg2dp_d0_daout_planar_stride[26:0]) //|> w + ,.dataout_ram_type (reg2dp_d0_dataout_ram_type) //|> w + ,.daout_surf_stride (reg2dp_d0_daout_surf_stride[26:0]) //|> w + ,.datain_height (reg2dp_d0_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d0_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d0_datain_channel[12:0]) //|> w + ,.dataout_channel (reg2dp_d0_dataout_channel[12:0]) //|> w + ,.deconv_x_stride (reg2dp_d0_deconv_x_stride[4:0]) //|> w + ,.deconv_y_stride (reg2dp_d0_deconv_y_stride[4:0]) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.rubik_mode (reg2dp_d0_rubik_mode[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.perf_en (reg2dp_d0_perf_en) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.rd_stall_cnt (dp2reg_d0_rd_stall_cnt[31:0]) //|< i + ,.wr_stall_cnt (dp2reg_d0_wr_stall_cnt[31:0]) //|< i + ); +NV_NVDLA_RUBIK_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.contract_stride_0 (reg2dp_d1_contract_stride_0[26:0]) //|> w + ,.contract_stride_1 (reg2dp_d1_contract_stride_1[26:0]) //|> w + ,.dain_addr_high (reg2dp_d1_dain_addr_high[31:0]) //|> w + ,.dain_addr_low (reg2dp_d1_dain_addr_low[26:0]) //|> w + ,.dain_line_stride (reg2dp_d1_dain_line_stride[26:0]) //|> w + ,.dain_planar_stride (reg2dp_d1_dain_planar_stride[26:0]) //|> w + ,.datain_ram_type (reg2dp_d1_datain_ram_type) //|> w + ,.dain_surf_stride (reg2dp_d1_dain_surf_stride[26:0]) //|> w + ,.daout_addr_high (reg2dp_d1_daout_addr_high[31:0]) //|> w + ,.daout_addr_low (reg2dp_d1_daout_addr_low[26:0]) //|> w + ,.daout_line_stride (reg2dp_d1_daout_line_stride[26:0]) //|> w + ,.daout_planar_stride (reg2dp_d1_daout_planar_stride[26:0]) //|> w + ,.dataout_ram_type (reg2dp_d1_dataout_ram_type) //|> w + ,.daout_surf_stride (reg2dp_d1_daout_surf_stride[26:0]) //|> w + ,.datain_height (reg2dp_d1_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d1_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d1_datain_channel[12:0]) //|> w + ,.dataout_channel (reg2dp_d1_dataout_channel[12:0]) //|> w + ,.deconv_x_stride (reg2dp_d1_deconv_x_stride[4:0]) //|> w + ,.deconv_y_stride (reg2dp_d1_deconv_y_stride[4:0]) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.rubik_mode (reg2dp_d1_rubik_mode[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.perf_en (reg2dp_d1_perf_en) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.rd_stall_cnt (dp2reg_d1_rd_stall_cnt[31:0]) //|< i + ,.wr_stall_cnt (dp2reg_d1_wr_stall_cnt[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {3{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {3{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {3{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {3{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h10008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h10008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h10008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2rbk_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2rbk_req_pvld) == 1'b1) begin + req_pd <= csb2rbk_req_pd; +// VCS coverage off + end else if ((csb2rbk_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2rbk_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2rbk_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rbk2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + rbk2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + rbk2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rbk2csb_resp_valid <= 1'b0; + end else begin + rbk2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_contract_stride_0 + or reg2dp_d0_contract_stride_0 + ) begin + reg2dp_contract_stride_0 = dp2reg_consumer ? reg2dp_d1_contract_stride_0 : reg2dp_d0_contract_stride_0; +end +always @( + dp2reg_consumer + or reg2dp_d1_contract_stride_1 + or reg2dp_d0_contract_stride_1 + ) begin + reg2dp_contract_stride_1 = dp2reg_consumer ? reg2dp_d1_contract_stride_1 : reg2dp_d0_contract_stride_1; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_addr_high + or reg2dp_d0_dain_addr_high + ) begin + reg2dp_dain_addr_high = dp2reg_consumer ? reg2dp_d1_dain_addr_high : reg2dp_d0_dain_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_addr_low + or reg2dp_d0_dain_addr_low + ) begin + reg2dp_dain_addr_low = dp2reg_consumer ? reg2dp_d1_dain_addr_low : reg2dp_d0_dain_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_line_stride + or reg2dp_d0_dain_line_stride + ) begin + reg2dp_dain_line_stride = dp2reg_consumer ? reg2dp_d1_dain_line_stride : reg2dp_d0_dain_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_planar_stride + or reg2dp_d0_dain_planar_stride + ) begin + reg2dp_dain_planar_stride = dp2reg_consumer ? reg2dp_d1_dain_planar_stride : reg2dp_d0_dain_planar_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_ram_type + or reg2dp_d0_datain_ram_type + ) begin + reg2dp_datain_ram_type = dp2reg_consumer ? reg2dp_d1_datain_ram_type : reg2dp_d0_datain_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_surf_stride + or reg2dp_d0_dain_surf_stride + ) begin + reg2dp_dain_surf_stride = dp2reg_consumer ? reg2dp_d1_dain_surf_stride : reg2dp_d0_dain_surf_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_addr_high + or reg2dp_d0_daout_addr_high + ) begin + reg2dp_daout_addr_high = dp2reg_consumer ? reg2dp_d1_daout_addr_high : reg2dp_d0_daout_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_addr_low + or reg2dp_d0_daout_addr_low + ) begin + reg2dp_daout_addr_low = dp2reg_consumer ? reg2dp_d1_daout_addr_low : reg2dp_d0_daout_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_line_stride + or reg2dp_d0_daout_line_stride + ) begin + reg2dp_daout_line_stride = dp2reg_consumer ? reg2dp_d1_daout_line_stride : reg2dp_d0_daout_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_planar_stride + or reg2dp_d0_daout_planar_stride + ) begin + reg2dp_daout_planar_stride = dp2reg_consumer ? reg2dp_d1_daout_planar_stride : reg2dp_d0_daout_planar_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_ram_type + or reg2dp_d0_dataout_ram_type + ) begin + reg2dp_dataout_ram_type = dp2reg_consumer ? reg2dp_d1_dataout_ram_type : reg2dp_d0_dataout_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_surf_stride + or reg2dp_d0_daout_surf_stride + ) begin + reg2dp_daout_surf_stride = dp2reg_consumer ? reg2dp_d1_daout_surf_stride : reg2dp_d0_daout_surf_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height + or reg2dp_d0_datain_height + ) begin + reg2dp_datain_height = dp2reg_consumer ? reg2dp_d1_datain_height : reg2dp_d0_datain_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width + or reg2dp_d0_datain_width + ) begin + reg2dp_datain_width = dp2reg_consumer ? reg2dp_d1_datain_width : reg2dp_d0_datain_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_channel + or reg2dp_d0_datain_channel + ) begin + reg2dp_datain_channel = dp2reg_consumer ? reg2dp_d1_datain_channel : reg2dp_d0_datain_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_channel + or reg2dp_d0_dataout_channel + ) begin + reg2dp_dataout_channel = dp2reg_consumer ? reg2dp_d1_dataout_channel : reg2dp_d0_dataout_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_deconv_x_stride + or reg2dp_d0_deconv_x_stride + ) begin + reg2dp_deconv_x_stride = dp2reg_consumer ? reg2dp_d1_deconv_x_stride : reg2dp_d0_deconv_x_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_deconv_y_stride + or reg2dp_d0_deconv_y_stride + ) begin + reg2dp_deconv_y_stride = dp2reg_consumer ? reg2dp_d1_deconv_y_stride : reg2dp_d0_deconv_y_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_rubik_mode + or reg2dp_d0_rubik_mode + ) begin + reg2dp_rubik_mode = dp2reg_consumer ? reg2dp_d1_rubik_mode : reg2dp_d0_rubik_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_en + or reg2dp_d0_perf_en + ) begin + reg2dp_perf_en = dp2reg_consumer ? reg2dp_d1_perf_en : reg2dp_d0_perf_en; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//for interrrupt +endmodule // NV_NVDLA_RUBIK_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v.vcp new file mode 100644 index 0000000..4befcef --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v.vcp @@ -0,0 +1,872 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_regfile.v +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_regfile ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2rbk_req_pd //|< i + ,csb2rbk_req_pvld //|< i + ,dp2reg_d0_rd_stall_cnt //|< i + ,dp2reg_d0_wr_stall_cnt //|< i + ,dp2reg_d1_rd_stall_cnt //|< i + ,dp2reg_d1_wr_stall_cnt //|< i + ,dp2reg_done //|< i + ,csb2rbk_req_prdy //|> o + ,dp2reg_consumer //|> o + ,rbk2csb_resp_pd //|> o + ,rbk2csb_resp_valid //|> o + ,reg2dp_contract_stride_0 //|> o + ,reg2dp_contract_stride_1 //|> o + ,reg2dp_dain_addr_high //|> o + ,reg2dp_dain_addr_low //|> o + ,reg2dp_dain_line_stride //|> o + ,reg2dp_dain_planar_stride //|> o + ,reg2dp_dain_surf_stride //|> o + ,reg2dp_daout_addr_high //|> o + ,reg2dp_daout_addr_low //|> o + ,reg2dp_daout_line_stride //|> o + ,reg2dp_daout_planar_stride //|> o + ,reg2dp_daout_surf_stride //|> o + ,reg2dp_datain_channel //|> o + ,reg2dp_datain_height //|> o + ,reg2dp_datain_ram_type //|> o + ,reg2dp_datain_width //|> o + ,reg2dp_dataout_channel //|> o + ,reg2dp_dataout_ram_type //|> o + ,reg2dp_deconv_x_stride //|> o + ,reg2dp_deconv_y_stride //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_op_en //|> o + ,reg2dp_perf_en //|> o + ,reg2dp_rubik_mode //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2rbk_req_pd; +input csb2rbk_req_pvld; +input [31:0] dp2reg_d0_rd_stall_cnt; +input [31:0] dp2reg_d0_wr_stall_cnt; +input [31:0] dp2reg_d1_rd_stall_cnt; +input [31:0] dp2reg_d1_wr_stall_cnt; +input dp2reg_done; +output csb2rbk_req_prdy; +output dp2reg_consumer; +output [33:0] rbk2csb_resp_pd; +output rbk2csb_resp_valid; +output [26:0] reg2dp_contract_stride_0; +output [26:0] reg2dp_contract_stride_1; +output [31:0] reg2dp_dain_addr_high; +output [26:0] reg2dp_dain_addr_low; +output [26:0] reg2dp_dain_line_stride; +output [26:0] reg2dp_dain_planar_stride; +output [26:0] reg2dp_dain_surf_stride; +output [31:0] reg2dp_daout_addr_high; +output [26:0] reg2dp_daout_addr_low; +output [26:0] reg2dp_daout_line_stride; +output [26:0] reg2dp_daout_planar_stride; +output [26:0] reg2dp_daout_surf_stride; +output [12:0] reg2dp_datain_channel; +output [12:0] reg2dp_datain_height; +output reg2dp_datain_ram_type; +output [12:0] reg2dp_datain_width; +output [12:0] reg2dp_dataout_channel; +output reg2dp_dataout_ram_type; +output [4:0] reg2dp_deconv_x_stride; +output [4:0] reg2dp_deconv_y_stride; +output [1:0] reg2dp_in_precision; +output reg2dp_op_en; +output reg2dp_perf_en; +output [1:0] reg2dp_rubik_mode; +output [2:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [26:0] reg2dp_d0_contract_stride_0; +wire [26:0] reg2dp_d0_contract_stride_1; +wire [31:0] reg2dp_d0_dain_addr_high; +wire [26:0] reg2dp_d0_dain_addr_low; +wire [26:0] reg2dp_d0_dain_line_stride; +wire [26:0] reg2dp_d0_dain_planar_stride; +wire [26:0] reg2dp_d0_dain_surf_stride; +wire [31:0] reg2dp_d0_daout_addr_high; +wire [26:0] reg2dp_d0_daout_addr_low; +wire [26:0] reg2dp_d0_daout_line_stride; +wire [26:0] reg2dp_d0_daout_planar_stride; +wire [26:0] reg2dp_d0_daout_surf_stride; +wire [12:0] reg2dp_d0_datain_channel; +wire [12:0] reg2dp_d0_datain_height; +wire reg2dp_d0_datain_ram_type; +wire [12:0] reg2dp_d0_datain_width; +wire [12:0] reg2dp_d0_dataout_channel; +wire reg2dp_d0_dataout_ram_type; +wire [4:0] reg2dp_d0_deconv_x_stride; +wire [4:0] reg2dp_d0_deconv_y_stride; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_op_en_trigger; +wire reg2dp_d0_perf_en; +wire [1:0] reg2dp_d0_rubik_mode; +wire [26:0] reg2dp_d1_contract_stride_0; +wire [26:0] reg2dp_d1_contract_stride_1; +wire [31:0] reg2dp_d1_dain_addr_high; +wire [26:0] reg2dp_d1_dain_addr_low; +wire [26:0] reg2dp_d1_dain_line_stride; +wire [26:0] reg2dp_d1_dain_planar_stride; +wire [26:0] reg2dp_d1_dain_surf_stride; +wire [31:0] reg2dp_d1_daout_addr_high; +wire [26:0] reg2dp_d1_daout_addr_low; +wire [26:0] reg2dp_d1_daout_line_stride; +wire [26:0] reg2dp_d1_daout_planar_stride; +wire [26:0] reg2dp_d1_daout_surf_stride; +wire [12:0] reg2dp_d1_datain_channel; +wire [12:0] reg2dp_d1_datain_height; +wire reg2dp_d1_datain_ram_type; +wire [12:0] reg2dp_d1_datain_width; +wire [12:0] reg2dp_d1_dataout_channel; +wire reg2dp_d1_dataout_ram_type; +wire [4:0] reg2dp_d1_deconv_x_stride; +wire [4:0] reg2dp_d1_deconv_y_stride; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_op_en_trigger; +wire reg2dp_d1_perf_en; +wire [1:0] reg2dp_d1_rubik_mode; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [2:0] slcg_op_en_d0; +reg dp2reg_consumer; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [33:0] rbk2csb_resp_pd; +reg rbk2csb_resp_valid; +reg [26:0] reg2dp_contract_stride_0; +reg [26:0] reg2dp_contract_stride_1; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [31:0] reg2dp_dain_addr_high; +reg [26:0] reg2dp_dain_addr_low; +reg [26:0] reg2dp_dain_line_stride; +reg [26:0] reg2dp_dain_planar_stride; +reg [26:0] reg2dp_dain_surf_stride; +reg [31:0] reg2dp_daout_addr_high; +reg [26:0] reg2dp_daout_addr_low; +reg [26:0] reg2dp_daout_line_stride; +reg [26:0] reg2dp_daout_planar_stride; +reg [26:0] reg2dp_daout_surf_stride; +reg [12:0] reg2dp_datain_channel; +reg [12:0] reg2dp_datain_height; +reg reg2dp_datain_ram_type; +reg [12:0] reg2dp_datain_width; +reg [12:0] reg2dp_dataout_channel; +reg reg2dp_dataout_ram_type; +reg [4:0] reg2dp_deconv_x_stride; +reg [4:0] reg2dp_deconv_y_stride; +reg [1:0] reg2dp_in_precision; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg reg2dp_perf_en; +reg [1:0] reg2dp_rubik_mode; +reg [62:0] req_pd; +reg req_pvld; +reg [2:0] slcg_op_en_d1; +reg [2:0] slcg_op_en_d2; +reg [2:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_RUBIK_single_reg u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< o + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_RUBIK_dual_reg u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.contract_stride_0 (reg2dp_d0_contract_stride_0[26:0]) //|> w + ,.contract_stride_1 (reg2dp_d0_contract_stride_1[26:0]) //|> w + ,.dain_addr_high (reg2dp_d0_dain_addr_high[31:0]) //|> w + ,.dain_addr_low (reg2dp_d0_dain_addr_low[26:0]) //|> w + ,.dain_line_stride (reg2dp_d0_dain_line_stride[26:0]) //|> w + ,.dain_planar_stride (reg2dp_d0_dain_planar_stride[26:0]) //|> w + ,.datain_ram_type (reg2dp_d0_datain_ram_type) //|> w + ,.dain_surf_stride (reg2dp_d0_dain_surf_stride[26:0]) //|> w + ,.daout_addr_high (reg2dp_d0_daout_addr_high[31:0]) //|> w + ,.daout_addr_low (reg2dp_d0_daout_addr_low[26:0]) //|> w + ,.daout_line_stride (reg2dp_d0_daout_line_stride[26:0]) //|> w + ,.daout_planar_stride (reg2dp_d0_daout_planar_stride[26:0]) //|> w + ,.dataout_ram_type (reg2dp_d0_dataout_ram_type) //|> w + ,.daout_surf_stride (reg2dp_d0_daout_surf_stride[26:0]) //|> w + ,.datain_height (reg2dp_d0_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d0_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d0_datain_channel[12:0]) //|> w + ,.dataout_channel (reg2dp_d0_dataout_channel[12:0]) //|> w + ,.deconv_x_stride (reg2dp_d0_deconv_x_stride[4:0]) //|> w + ,.deconv_y_stride (reg2dp_d0_deconv_y_stride[4:0]) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.rubik_mode (reg2dp_d0_rubik_mode[1:0]) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.perf_en (reg2dp_d0_perf_en) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.rd_stall_cnt (dp2reg_d0_rd_stall_cnt[31:0]) //|< i + ,.wr_stall_cnt (dp2reg_d0_wr_stall_cnt[31:0]) //|< i + ); +NV_NVDLA_RUBIK_dual_reg u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.contract_stride_0 (reg2dp_d1_contract_stride_0[26:0]) //|> w + ,.contract_stride_1 (reg2dp_d1_contract_stride_1[26:0]) //|> w + ,.dain_addr_high (reg2dp_d1_dain_addr_high[31:0]) //|> w + ,.dain_addr_low (reg2dp_d1_dain_addr_low[26:0]) //|> w + ,.dain_line_stride (reg2dp_d1_dain_line_stride[26:0]) //|> w + ,.dain_planar_stride (reg2dp_d1_dain_planar_stride[26:0]) //|> w + ,.datain_ram_type (reg2dp_d1_datain_ram_type) //|> w + ,.dain_surf_stride (reg2dp_d1_dain_surf_stride[26:0]) //|> w + ,.daout_addr_high (reg2dp_d1_daout_addr_high[31:0]) //|> w + ,.daout_addr_low (reg2dp_d1_daout_addr_low[26:0]) //|> w + ,.daout_line_stride (reg2dp_d1_daout_line_stride[26:0]) //|> w + ,.daout_planar_stride (reg2dp_d1_daout_planar_stride[26:0]) //|> w + ,.dataout_ram_type (reg2dp_d1_dataout_ram_type) //|> w + ,.daout_surf_stride (reg2dp_d1_daout_surf_stride[26:0]) //|> w + ,.datain_height (reg2dp_d1_datain_height[12:0]) //|> w + ,.datain_width (reg2dp_d1_datain_width[12:0]) //|> w + ,.datain_channel (reg2dp_d1_datain_channel[12:0]) //|> w + ,.dataout_channel (reg2dp_d1_dataout_channel[12:0]) //|> w + ,.deconv_x_stride (reg2dp_d1_deconv_x_stride[4:0]) //|> w + ,.deconv_y_stride (reg2dp_d1_deconv_y_stride[4:0]) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.rubik_mode (reg2dp_d1_rubik_mode[1:0]) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.perf_en (reg2dp_d1_perf_en) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.rd_stall_cnt (dp2reg_d1_rd_stall_cnt[31:0]) //|< i + ,.wr_stall_cnt (dp2reg_d1_wr_stall_cnt[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {3{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {3{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {3{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {3{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'h10008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'h10008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'h10008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2rbk_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2rbk_req_pvld) == 1'b1) begin + req_pd <= csb2rbk_req_pd; +// VCS coverage off + end else if ((csb2rbk_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2rbk_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2rbk_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rbk2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + rbk2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + rbk2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rbk2csb_resp_valid <= 1'b0; + end else begin + rbk2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_contract_stride_0 + or reg2dp_d0_contract_stride_0 + ) begin + reg2dp_contract_stride_0 = dp2reg_consumer ? reg2dp_d1_contract_stride_0 : reg2dp_d0_contract_stride_0; +end +always @( + dp2reg_consumer + or reg2dp_d1_contract_stride_1 + or reg2dp_d0_contract_stride_1 + ) begin + reg2dp_contract_stride_1 = dp2reg_consumer ? reg2dp_d1_contract_stride_1 : reg2dp_d0_contract_stride_1; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_addr_high + or reg2dp_d0_dain_addr_high + ) begin + reg2dp_dain_addr_high = dp2reg_consumer ? reg2dp_d1_dain_addr_high : reg2dp_d0_dain_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_addr_low + or reg2dp_d0_dain_addr_low + ) begin + reg2dp_dain_addr_low = dp2reg_consumer ? reg2dp_d1_dain_addr_low : reg2dp_d0_dain_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_line_stride + or reg2dp_d0_dain_line_stride + ) begin + reg2dp_dain_line_stride = dp2reg_consumer ? reg2dp_d1_dain_line_stride : reg2dp_d0_dain_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_planar_stride + or reg2dp_d0_dain_planar_stride + ) begin + reg2dp_dain_planar_stride = dp2reg_consumer ? reg2dp_d1_dain_planar_stride : reg2dp_d0_dain_planar_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_ram_type + or reg2dp_d0_datain_ram_type + ) begin + reg2dp_datain_ram_type = dp2reg_consumer ? reg2dp_d1_datain_ram_type : reg2dp_d0_datain_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dain_surf_stride + or reg2dp_d0_dain_surf_stride + ) begin + reg2dp_dain_surf_stride = dp2reg_consumer ? reg2dp_d1_dain_surf_stride : reg2dp_d0_dain_surf_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_addr_high + or reg2dp_d0_daout_addr_high + ) begin + reg2dp_daout_addr_high = dp2reg_consumer ? reg2dp_d1_daout_addr_high : reg2dp_d0_daout_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_addr_low + or reg2dp_d0_daout_addr_low + ) begin + reg2dp_daout_addr_low = dp2reg_consumer ? reg2dp_d1_daout_addr_low : reg2dp_d0_daout_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_line_stride + or reg2dp_d0_daout_line_stride + ) begin + reg2dp_daout_line_stride = dp2reg_consumer ? reg2dp_d1_daout_line_stride : reg2dp_d0_daout_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_planar_stride + or reg2dp_d0_daout_planar_stride + ) begin + reg2dp_daout_planar_stride = dp2reg_consumer ? reg2dp_d1_daout_planar_stride : reg2dp_d0_daout_planar_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_ram_type + or reg2dp_d0_dataout_ram_type + ) begin + reg2dp_dataout_ram_type = dp2reg_consumer ? reg2dp_d1_dataout_ram_type : reg2dp_d0_dataout_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_daout_surf_stride + or reg2dp_d0_daout_surf_stride + ) begin + reg2dp_daout_surf_stride = dp2reg_consumer ? reg2dp_d1_daout_surf_stride : reg2dp_d0_daout_surf_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_height + or reg2dp_d0_datain_height + ) begin + reg2dp_datain_height = dp2reg_consumer ? reg2dp_d1_datain_height : reg2dp_d0_datain_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_width + or reg2dp_d0_datain_width + ) begin + reg2dp_datain_width = dp2reg_consumer ? reg2dp_d1_datain_width : reg2dp_d0_datain_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_datain_channel + or reg2dp_d0_datain_channel + ) begin + reg2dp_datain_channel = dp2reg_consumer ? reg2dp_d1_datain_channel : reg2dp_d0_datain_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_dataout_channel + or reg2dp_d0_dataout_channel + ) begin + reg2dp_dataout_channel = dp2reg_consumer ? reg2dp_d1_dataout_channel : reg2dp_d0_dataout_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_deconv_x_stride + or reg2dp_d0_deconv_x_stride + ) begin + reg2dp_deconv_x_stride = dp2reg_consumer ? reg2dp_d1_deconv_x_stride : reg2dp_d0_deconv_x_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_deconv_y_stride + or reg2dp_d0_deconv_y_stride + ) begin + reg2dp_deconv_y_stride = dp2reg_consumer ? reg2dp_d1_deconv_y_stride : reg2dp_d0_deconv_y_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_rubik_mode + or reg2dp_d0_rubik_mode + ) begin + reg2dp_rubik_mode = dp2reg_consumer ? reg2dp_d1_rubik_mode : reg2dp_d0_rubik_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_en + or reg2dp_d0_perf_en + ) begin + reg2dp_perf_en = dp2reg_consumer ? reg2dp_d1_perf_en : reg2dp_d0_perf_en; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +//for interrrupt +endmodule // NV_NVDLA_RUBIK_regfile diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v new file mode 100644 index 0000000..2980afd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v @@ -0,0 +1,1987 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_core.v +module NV_NVDLA_RUBIK_rf_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dma_wr_data_rdy //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_rubik_mode //|< i + ,rf_rd_addr //|< i + ,rf_rd_done //|< i + ,rf_rd_mask //|< i + ,rf_rd_vld //|< i + ,rf_wr_addr //|< i + ,rf_wr_data //|< i + ,rf_wr_done //|< i + ,rf_wr_vld //|< i + ,dma_wr_data_pd //|> o + ,dma_wr_data_vld //|> o + ,rf_rd_rdy //|> o + ,rf_wr_rdy //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input rf_wr_vld; +input rf_wr_done; +input [4:0] rf_wr_addr; //row address,increase one when write 64Bytes +input [511:0] rf_wr_data; +output rf_wr_rdy; +input rf_rd_vld; +input rf_rd_done; +input [4:0] rf_rd_addr; //column address,increase one when read 64Bytes +input [11:0] rf_rd_mask; +output rf_rd_rdy; +output dma_wr_data_vld; +output [513:0] dma_wr_data_pd; +input dma_wr_data_rdy; +input [1:0] reg2dp_rubik_mode; +input [1:0] reg2dp_in_precision; +reg dma_wr_data_vld; +reg [511:0] rd_data_raw_reg; +reg [1:0] reg2dp_in_precision_drv2; +reg [1:0] reg2dp_rubik_mode_drv2; +reg [4:0] rf_rd_oaddr_d; +reg [11:0] rf_rd_omask_d; +reg rf_rd_osel_d; +reg rf_rd_pop_d; +reg [1:0] rf_rptr; +reg [1:0] rf_wptr; +wire [31:0] byte_mask_h; +wire [31:0] byte_mask_l; +wire [159:0] contract_rd_addr_shift; +wire [511:0] contract_rd_data; +wire [511:0] contract_wr_shift; +wire [511:0] dma_wr_pd_data; +wire [1:0] dma_wr_pd_mask; +wire m_byte_data; +wire m_contract; +wire m_split; +wire [159:0] merge16_rd_addr_shift; +wire [511:0] merge16_rd_data; +wire [511:0] merge16_wr_shift; +wire [159:0] merge8_rd_addr_shift; +wire [511:0] merge8_rd_data; +wire [511:0] merge8_wr_shift; +wire [159:0] merge_rd_addr_shift; +wire [511:0] merge_rd_data; +wire [511:0] merge_wr_shift; +wire mon_rd_mask_hc; +wire mon_rd_mask_lc; +wire mon_rd_snum; +wire mon_rd_snum1; +wire mon_rd_snum2; +wire mon_wr_snum; +wire mon_wr_snum1; +wire mon_wr_snum2; +wire [159:0] ram_even_seq; +wire [159:0] ram_gene_seq; +wire [159:0] ram_halfh_seq; +wire [159:0] ram_halfl_seq; +wire [159:0] ram_odd_seq; +wire [159:0] ram_rd_addr; +wire [159:0] ram_rd_oaddr; +wire [5:0] rd_addr_incr4; +wire [4:0] rd_addr_tmp; +wire [511:0] rd_data0_raw; +wire [511:0] rd_data1_raw; +wire [511:0] rd_data_raw; +wire [511:0] rd_data_raw_tmp; +wire [5:0] rd_omask_h; +wire [5:0] rd_omask_l; +wire [4:0] rd_shift_num; +wire [4:0] rd_shift_num1; +wire [4:0] rd_shift_num2; +wire rf_empty; +wire rf_full; +wire [511:0] rf_rd_data; +wire [4:0] rf_rd_oaddr; +wire rf_rd_odone; +wire [11:0] rf_rd_omask; +wire [177:0] rf_rd_opd; +wire rf_rd_ordy; +wire rf_rd_osel; +wire rf_rd_ovld; +wire [177:0] rf_rd_pd; +wire rf_rd_pop; +wire [4:0] rf_wr_oaddr; +wire [511:0] rf_wr_odata; +wire rf_wr_odone; +wire [517:0] rf_wr_opd; +wire rf_wr_ordy; +wire rf_wr_osel; +wire rf_wr_ovld; +wire [517:0] rf_wr_pd; +wire rf_wr_pop; +wire [159:0] split16_rd_addr_shift; +wire [511:0] split16_rd_data; +wire [511:0] split16_wr_shift; +wire [159:0] split8_rd_addr_shift; +wire [511:0] split8_rd_data; +wire [511:0] split8_wr_shift; +wire [159:0] split_rd_addr_shift; +wire [511:0] split_rd_data; +wire [511:0] split_wr_shift; +wire [511:0] wr_data_comb16; +wire [511:0] wr_data_comb8; +wire [511:0] wr_data_shift; +wire [4:0] wr_shift_num; +wire [4:0] wr_shift_num1; +wire [4:0] wr_shift_num2; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_rubik_mode_drv2[1:0] <= {2{1'b0}}; + end else begin + reg2dp_rubik_mode_drv2[1:0] <= reg2dp_rubik_mode[1:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_in_precision_drv2[1:0] <= {2{1'b0}}; + end else begin + reg2dp_in_precision_drv2[1:0] <= reg2dp_in_precision[1:0]; + end +end +assign m_contract = reg2dp_rubik_mode_drv2[1:0] == 2'h0 ; +assign m_split = reg2dp_rubik_mode_drv2[1:0] == 2'h1 ; +//assign m_merge = reg2dp_rubik_mode_drv2[1:0] == NVDLA_RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE; +assign m_byte_data = reg2dp_in_precision_drv2[1:0] == 2'h0 ; +function [511:0] shift512_16b; //shift 512bits data with 16bits per one step +input [511:0] di; +input [4:0] snum; +reg [511:0] shf0; +reg [511:0] shf1; +reg [511:0] shf2; +reg [511:0] shf3; +begin + shf0[511:0] = snum[4] ? { di[255:0], di[511:256]} : di[511:0]; + shf1[511:0] = snum[3] ? {shf0[127:0],shf0[511:128]} : shf0[511:0]; + shf2[511:0] = snum[2] ? {shf1[63:0],shf1[511:64]} : shf1[511:0]; + shf3[511:0] = snum[1] ? {shf2[31:0],shf2[511:32]} : shf2[511:0]; + shift512_16b= snum[0] ? {shf3[15:0],shf3[511:16]} : shf3[511:0]; +end +endfunction +function [159:0] shift160_5b; //shift 160bits ram addr with 5bits per one step +input [159:0] di; +input [4:0] snum; +reg [159:0] shf0; +reg [159:0] shf1; +reg [159:0] shf2; +reg [159:0] shf3; +begin + shf0[159:0] = snum[4] ? { di[79:0], di[159:80]} : di[159:0]; + shf1[159:0] = snum[3] ? {shf0[39:0],shf0[159:40]} : shf0[159:0]; + shf2[159:0] = snum[2] ? {shf1[19:0],shf1[159:20]} : shf1[159:0]; + shf3[159:0] = snum[1] ? {shf2[9:0], shf2[159:10]} : shf2[159:0]; + shift160_5b = snum[0] ? {shf3[4:0], shf3[159:5]} : shf3[159:0]; +end +endfunction +function [511:0] data_comb8; //combine atomic0 's element0 with atomic1'element0 in int8 precision +input [511:0] di; +reg [255:0] di0; +reg [255:0] di1; +begin + di0 = di[255:0]; + di1 = di[511:256]; + data_comb8 = {di1[255:248], di0[255:248],di1[247:240], di0[247:240], + di1[239:232], di0[239:232],di1[231:224], di0[231:224], + di1[223:216], di0[223:216],di1[215:208], di0[215:208], + di1[207:200], di0[207:200],di1[199:192], di0[199:192], + di1[191:184], di0[191:184],di1[183:176], di0[183:176], + di1[175:168], di0[175:168],di1[167:160], di0[167:160], + di1[159:152], di0[159:152],di1[151:144], di0[151:144], + di1[143:136], di0[143:136],di1[135:128], di0[135:128], + di1[127:120], di0[127:120],di1[119:112], di0[119:112], + di1[111:104], di0[111:104],di1[103:96], di0[103:96], + di1[95:88], di0[95:88], di1[87:80], di0[87:80], + di1[79:72], di0[79:72], di1[71:64], di0[71:64], + di1[63:56], di0[63:56], di1[55:48], di0[55:48], + di1[47:40], di0[47:40], di1[39:32], di0[39:32], + di1[31:24], di0[31:24], di1[23:16], di0[23:16], + di1[15:8], di0[15:8] , di1[7:0], di0[7:0]}; +end +endfunction +function [511:0] data_comb16; //combine atomic0 's element0 with atomic1'element0 in int16 precision +input [511:0] di; +reg [255:0] di0; +reg [255:0] di1; +begin + di0 = di[255:0]; + di1 = di[511:256]; + data_comb16 = {di1[255:240], di0[255:240],di1[239:224], di0[239:224], + di1[223:208], di0[223:208],di1[207:192], di0[207:192], + di1[191:176], di0[191:176],di1[175:160], di0[175:160], + di1[159:144], di0[159:144],di1[143:128], di0[143:128], + di1[127:112], di0[127:112],di1[111:96], di0[111:96] , + di1[95:80], di0[95:80] ,di1[79:64], di0[79:64], + di1[63:48], di0[63:48] ,di1[47:32], di0[47:32], + di1[31:16], di0[31:16] ,di1[15:0], di0[15:0]}; +end +endfunction +function [511:0] data_recomb8; //re-combine atomic0 's element0 with atomic1'element0 in int8 precision +input [511:0] di; +reg [255:0] di1; +reg [255:0] di0; +reg [127:0] do3; +reg [127:0] do2; +reg [127:0] do1; +reg [127:0] do0; +begin + di0 = di[255:0]; + di1 = di[511:256]; + do3 = {di1[255:248],di1[239:232], + di1[223:216],di1[207:200], + di1[191:184],di1[175:168], + di1[159:152],di1[143:136], + di1[127:120],di1[111:104], + di1[95:88], di1[79:72], + di1[63:56], di1[47:40], + di1[31:24], di1[15:8] }; + do2 = {di1[247:240],di1[231:224], + di1[215:208],di1[199:192], + di1[183:176],di1[167:160], + di1[151:144],di1[135:128], + di1[119:112],di1[103:96], + di1[87:80], di1[71:64], + di1[55:48], di1[39:32], + di1[23:16], di1[7:0]}; + do1 = {di0[255:248],di0[239:232], + di0[223:216],di0[207:200], + di0[191:184],di0[175:168], + di0[159:152],di0[143:136], + di0[127:120],di0[111:104], + di0[95:88], di0[79:72], + di0[63:56], di0[47:40], + di0[31:24], di0[15:8] }; + do0 = {di0[247:240],di0[231:224], + di0[215:208],di0[199:192], + di0[183:176],di0[167:160], + di0[151:144],di0[135:128], + di0[119:112],di0[103:96], + di0[87:80], di0[71:64], + di0[55:48], di0[39:32], + di0[23:16], di0[7:0]}; + data_recomb8 = {do3,do1,do2,do0}; +end +endfunction +function [511:0] data_recomb16; //re-combine atomic0 's element0 with atomic1'element0 in int16 precision +input [511:0] di; +reg [255:0] di1; +reg [255:0] di0; +reg [127:0] do3; +reg [127:0] do2; +reg [127:0] do1; +reg [127:0] do0; +begin + di0 = di[255:0]; + di1 = di[511:256]; + do3 = {di1[255:240],di1[223:208], + di1[191:176],di1[159:144], + di1[127:112],di1[95:80] , + di1[63:48] ,di1[31:16] }; + do2 = {di1[239:224],di1[207:192], + di1[175:160],di1[143:128], + di1[111:96] ,di1[79:64], + di1[47:32] ,di1[15:0]}; + do1 = {di0[255:240],di0[223:208], + di0[191:176],di0[159:144], + di0[127:112],di0[95:80] , + di0[63:48] ,di0[31:16] }; + do0 = {di0[239:224],di0[207:192], + di0[175:160],di0[143:128], + di0[111:96] ,di0[79:64], + di0[47:32] ,di0[15:0]}; + data_recomb16 = {do3,do1,do2,do0}; +end +endfunction +function [255:0] data_mask; +input [255:0] di; +input [31:0] byte_mask; +reg [31:0] data_mask0; +reg [31:0] data_mask1; +reg [31:0] data_mask2; +reg [31:0] data_mask3; +reg [31:0] data_mask4; +reg [31:0] data_mask5; +reg [31:0] data_mask6; +reg [31:0] data_mask7; +begin + data_mask0 = di[31:0] & {{8{byte_mask[3]}}, {8{byte_mask[2]}}, {8{byte_mask[1]}}, {8{byte_mask[0]}}}; + data_mask1 = di[63:32] & {{8{byte_mask[7]}}, {8{byte_mask[6]}}, {8{byte_mask[5]}}, {8{byte_mask[4]}}}; + data_mask2 = di[95:64] & {{8{byte_mask[11]}},{8{byte_mask[10]}},{8{byte_mask[9]}}, {8{byte_mask[8]}}}; + data_mask3 = di[127:96] & {{8{byte_mask[15]}},{8{byte_mask[14]}},{8{byte_mask[13]}},{8{byte_mask[12]}}}; + data_mask4 = di[159:128] & {{8{byte_mask[19]}},{8{byte_mask[18]}},{8{byte_mask[17]}},{8{byte_mask[16]}}}; + data_mask5 = di[191:160] & {{8{byte_mask[23]}},{8{byte_mask[22]}},{8{byte_mask[21]}},{8{byte_mask[20]}}}; + data_mask6 = di[223:192] & {{8{byte_mask[27]}},{8{byte_mask[26]}},{8{byte_mask[25]}},{8{byte_mask[24]}}}; + data_mask7 = di[255:224] & {{8{byte_mask[31]}},{8{byte_mask[30]}},{8{byte_mask[29]}},{8{byte_mask[28]}}}; + data_mask = {data_mask7,data_mask6,data_mask5,data_mask4,data_mask3,data_mask2,data_mask1,data_mask0}; +end +endfunction +//write data shift +assign wr_data_comb8 = data_comb8(rf_wr_data[511:0]); +assign wr_data_comb16 = data_comb16(rf_wr_data[511:0]); +assign {mon_wr_snum, wr_shift_num[4:0] } = 6'h20-rf_wr_addr; +assign {mon_wr_snum1,wr_shift_num1[4:0]} = 6'h20-{rf_wr_addr[4:1],1'b0}; +assign {mon_wr_snum2,wr_shift_num2[4:0]} = 6'h20-{rf_wr_addr[3:0],1'b0}; +assign merge8_wr_shift[511:0] = shift512_16b(rf_wr_data[511:0],wr_shift_num); //merge int8 +assign merge16_wr_shift[511:0] = shift512_16b(rf_wr_data[511:0],wr_shift_num1); +assign merge_wr_shift[511:0] = !m_byte_data ? merge16_wr_shift : merge8_wr_shift; +assign split8_wr_shift[511:0] = shift512_16b(wr_data_comb8,wr_shift_num); //split int8 +assign split16_wr_shift[511:0] = shift512_16b(wr_data_comb16,wr_shift_num2); +assign split_wr_shift[511:0] = !m_byte_data ? split16_wr_shift : split8_wr_shift; +assign contract_wr_shift[511:0]= rf_wr_addr[2] ? {rf_wr_data[255:0],rf_wr_data[511:256]} : rf_wr_data[511:0]; +assign wr_data_shift[511:0] = m_contract ? contract_wr_shift : m_split ? split_wr_shift : merge_wr_shift ; +assign rf_wr_pd[517:0] = {rf_wr_done,rf_wr_addr[4:0],wr_data_shift[511:0]}; +NV_NVDLA_RUBIK_RF_CORE_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.rf_wr_ordy (rf_wr_ordy) //|< w + ,.rf_wr_pd (rf_wr_pd[517:0]) //|< w + ,.rf_wr_vld (rf_wr_vld) //|< i + ,.rf_wr_opd (rf_wr_opd[517:0]) //|> w + ,.rf_wr_ovld (rf_wr_ovld) //|> w + ,.rf_wr_rdy (rf_wr_rdy) //|> o + ); +assign rf_wr_ordy = ~rf_full; +assign rf_wr_pop = rf_wr_ovld & rf_wr_ordy; +assign rf_wr_odone = rf_wr_pop & rf_wr_opd[517]; +assign rf_wr_oaddr = rf_wr_opd[516:512]; +assign rf_wr_odata = rf_wr_opd[511:0]; +assign rf_wr_osel = rf_wptr[0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_wr_odone) + rf_wptr[1:0] <= rf_wptr[1:0] + 1; + end +end +////////////////rf status//////////////////// +assign rf_empty = rf_wptr[1:0]==rf_rptr[1:0]; +assign rf_full = (rf_wptr[1]^rf_rptr[1]) & (rf_wptr[0]==rf_rptr[0]); +//read sram address shift +assign ram_gene_seq[159:0] = {5'h1f,5'h1e,5'h1d,5'h1c,5'h1b,5'h1a,5'h19,5'h18, + 5'h17,5'h16,5'h15,5'h14,5'h13,5'h12,5'h11,5'h10, + 5'h0f,5'h0e,5'h0d,5'h0c,5'h0b,5'h0a,5'h09,5'h08, + 5'h07,5'h06,5'h05,5'h04,5'h03,5'h02,5'h01,5'h00}; +assign ram_even_seq[159:0] = {5'h1e,5'h1e,5'h1c,5'h1c,5'h1a,5'h1a,5'h18,5'h18, + 5'h16,5'h16,5'h14,5'h14,5'h12,5'h12,5'h10,5'h10, + 5'h0e,5'h0e,5'h0c,5'h0c,5'h0a,5'h0a,5'h08,5'h08, + 5'h06,5'h06,5'h04,5'h04,5'h02,5'h02,5'h00,5'h00}; +assign ram_odd_seq[159:0] = {5'h1f,5'h1f,5'h1d,5'h1d,5'h1b,5'h1b,5'h19,5'h19, + 5'h17,5'h17,5'h15,5'h15,5'h13,5'h13,5'h11,5'h11, + 5'h0f,5'h0f,5'h0d,5'h0d,5'h0b,5'h0b,5'h09,5'h09, + 5'h07,5'h07,5'h05,5'h05,5'h03,5'h03,5'h01,5'h01}; +assign ram_halfl_seq[159:0]= {5'h0f,5'h0f,5'h0e,5'h0e,5'h0d,5'h0d,5'h0c,5'h0c, + 5'h0b,5'h0b,5'h0a,5'h0a,5'h09,5'h09,5'h08,5'h08, + 5'h07,5'h07,5'h06,5'h06,5'h05,5'h05,5'h04,5'h04, + 5'h03,5'h03,5'h02,5'h02,5'h01,5'h01,5'h00,5'h00}; +assign ram_halfh_seq[159:0]= {5'h1f,5'h1f,5'h1e,5'h1e,5'h1d,5'h1d,5'h1c,5'h1c, + 5'h1b,5'h1b,5'h1a,5'h1a,5'h19,5'h19,5'h18,5'h18, + 5'h17,5'h17,5'h16,5'h16,5'h15,5'h15,5'h14,5'h14, + 5'h13,5'h13,5'h12,5'h12,5'h11,5'h11,5'h10,5'h10}; +assign {mon_rd_snum, rd_shift_num[4:0] } = 6'h20-rf_rd_addr; +assign {mon_rd_snum1,rd_shift_num1[4:0]} = 6'h20-{rf_rd_addr[4:1],1'b0}; +assign {mon_rd_snum2,rd_shift_num2[4:0]} = 6'h20-{rf_rd_addr[3:0],1'b0}; +assign merge8_rd_addr_shift[159:0] = shift160_5b(ram_gene_seq,rd_shift_num); +assign merge16_rd_addr_shift[159:0] = rf_rd_addr[4] ? shift160_5b(ram_odd_seq,rd_shift_num2) : shift160_5b(ram_even_seq,rd_shift_num2); +assign merge_rd_addr_shift[159:0] = !m_byte_data ? merge16_rd_addr_shift : merge8_rd_addr_shift; +assign split8_rd_addr_shift[159:0] = shift160_5b(ram_gene_seq,rd_shift_num); +assign split16_rd_addr_shift[159:0] = rf_rd_addr[0] ? shift160_5b(ram_halfh_seq,rd_shift_num1) : shift160_5b(ram_halfl_seq,rd_shift_num1); +assign split_rd_addr_shift[159:0] = !m_byte_data ? split16_rd_addr_shift : split8_rd_addr_shift; +assign rd_addr_tmp[4:0] = rf_rd_addr[4:3] + {rf_rd_addr[1:0],3'h0}; +assign rd_addr_incr4[5:0] = rd_addr_tmp[4:0] + 4'h4; +assign contract_rd_addr_shift[159:0] = ~rf_rd_addr[2] ? {{16{rd_addr_incr4[4:0]}}, {16{rd_addr_tmp}}} : {{16{rd_addr_tmp}}, {16{rd_addr_incr4[4:0]}}}; +assign ram_rd_addr[159:0] = m_contract ? contract_rd_addr_shift : m_split ? split_rd_addr_shift : merge_rd_addr_shift ; +assign rf_rd_pd[177:0] = {rf_rd_done,rf_rd_mask[11:0],rf_rd_addr[4:0],ram_rd_addr[159:0]}; +NV_NVDLA_RUBIK_RF_CORE_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.rf_rd_ordy (rf_rd_ordy) //|< w + ,.rf_rd_pd (rf_rd_pd[177:0]) //|< w + ,.rf_rd_vld (rf_rd_vld) //|< i + ,.rf_rd_opd (rf_rd_opd[177:0]) //|> w + ,.rf_rd_ovld (rf_rd_ovld) //|> w + ,.rf_rd_rdy (rf_rd_rdy) //|> o + ); +assign rf_rd_ordy = dma_wr_data_rdy & ~rf_empty; +assign rf_rd_pop = rf_rd_ovld & rf_rd_ordy; +assign rf_rd_odone = rf_rd_pop & rf_rd_opd[177]; +assign rf_rd_omask = rf_rd_opd[176:165]; +assign rf_rd_oaddr = rf_rd_opd[164:160]; +assign ram_rd_oaddr= rf_rd_opd[159:0]; +assign rf_rd_osel = rf_rptr[0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_rd_odone) + rf_rptr[1:0] <= rf_rptr[1:0]+1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_pop_d <= 1'b0; + end else begin + rf_rd_pop_d <= rf_rd_pop; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_osel_d <= 1'b0; + end else begin + rf_rd_osel_d <= rf_rd_osel; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_oaddr_d[4:0] <= {5{1'b0}}; + end else begin + rf_rd_oaddr_d[4:0] <= dma_wr_data_rdy ? rf_rd_oaddr[4:0] : rf_rd_oaddr_d[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_omask_d[11:0] <= {12{1'b0}}; + end else begin + rf_rd_omask_d[11:0] <= dma_wr_data_rdy ? rf_rd_omask[11:0] : rf_rd_omask_d[11:0]; + end +end +assign rd_data_raw_tmp[511:0] = rf_rd_osel_d ? rd_data1_raw[511:0] : rd_data0_raw[511:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_data_raw_reg[511:0] <= {512{1'b0}}; + end else begin + if (rf_rd_pop_d) + rd_data_raw_reg[511:0] <= rd_data_raw_tmp[511:0]; + end +end +assign rd_data_raw[511:0] = rf_rd_pop_d & dma_wr_data_rdy ? rd_data_raw_tmp[511:0] : rd_data_raw_reg[511:0]; +//read data shift +assign merge8_rd_data[511:0] = shift512_16b(rd_data_raw,rf_rd_oaddr_d); +assign merge16_rd_data[511:0] = shift512_16b(rd_data_raw,{rf_rd_oaddr_d[3:0],1'b0}); +assign merge_rd_data[511:0] = !m_byte_data ? data_recomb16(merge16_rd_data) : data_recomb8(merge8_rd_data); +assign split8_rd_data[511:0] = shift512_16b(rd_data_raw,rf_rd_oaddr_d); +assign split16_rd_data[511:0] = shift512_16b(rd_data_raw,{rf_rd_oaddr_d[4:1],1'b0}); +assign split_rd_data[511:0] = !m_byte_data ? split16_rd_data : split8_rd_data; +assign contract_rd_data[511:0]= rf_rd_oaddr_d[2] ? {rd_data_raw[255:0],rd_data_raw[511:256]} : rd_data_raw[511:0]; +assign rf_rd_data[511:0] = m_contract ? contract_rd_data : m_split ? split_rd_data : merge_rd_data ; +//write rf rdata to dma data buffer +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_wr_data_vld <= 1'b0; + end else begin + if (rf_rd_pop) + dma_wr_data_vld <=1'b1; + else if (dma_wr_data_vld & dma_wr_data_rdy) + dma_wr_data_vld <=1'b0; + end +end +assign {mon_rd_mask_hc,rd_omask_h[5:0]} = 6'h20-rf_rd_omask_d[11:6]; +assign {mon_rd_mask_lc,rd_omask_l[5:0]} = 6'h20-rf_rd_omask_d[5:0]; +assign byte_mask_h[31:0] = 32'hffffffff >> rd_omask_h; +assign byte_mask_l[31:0] = 32'hffffffff >> rd_omask_l; +assign dma_wr_pd_data[511:0]= {data_mask(rf_rd_data[511:256],byte_mask_h[31:0]),data_mask(rf_rd_data[255:0],byte_mask_l[31:0])}; +assign dma_wr_pd_mask[1:0] = {|rf_rd_omask_d[11:6],|rf_rd_omask_d[5:0]}; +assign dma_wr_data_pd[513:0] = {dma_wr_pd_mask,dma_wr_pd_data}; +//register file 0 : contain 32 rams,one ram is 32x16 +nv_ram_rws_32x16 rubik_rf0_ram0 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[4:0]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[15:0]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[15:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram1 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[9:5]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[31:16]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[31:16]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram2 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[14:10]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[47:32]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[47:32]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram3 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[19:15]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[63:48]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[63:48]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram4 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[24:20]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[79:64]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[79:64]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram5 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[29:25]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[95:80]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[95:80]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram6 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[34:30]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[111:96]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[111:96]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram7 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[39:35]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[127:112]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[127:112]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram8 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[44:40]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[143:128]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[143:128]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram9 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[49:45]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[159:144]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[159:144]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram10 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[54:50]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[175:160]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[175:160]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram11 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[59:55]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[191:176]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[191:176]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram12 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[64:60]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[207:192]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[207:192]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram13 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[69:65]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[223:208]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[223:208]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram14 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[74:70]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[239:224]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[239:224]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram15 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[79:75]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[255:240]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[255:240]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram16 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[84:80]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[271:256]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[271:256]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram17 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[89:85]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[287:272]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[287:272]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram18 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[94:90]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[303:288]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[303:288]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram19 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[99:95]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[319:304]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[319:304]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram20 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[104:100]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[335:320]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[335:320]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram21 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[109:105]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[351:336]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[351:336]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram22 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[114:110]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[367:352]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[367:352]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram23 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[119:115]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[383:368]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[383:368]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram24 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[124:120]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[399:384]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[399:384]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram25 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[129:125]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[415:400]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[415:400]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram26 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[134:130]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[431:416]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[431:416]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram27 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[139:135]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[447:432]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[447:432]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram28 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[144:140]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[463:448]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[463:448]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram29 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[149:145]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[479:464]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[479:464]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram30 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[154:150]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[495:480]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[495:480]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram31 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[159:155]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[511:496]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[511:496]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//register file 1 : contain 32 rams,one ram is 32x16 +nv_ram_rws_32x16 rubik_rf1_ram0 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[4:0]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[15:0]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[15:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram1 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[9:5]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[31:16]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[31:16]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram2 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[14:10]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[47:32]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[47:32]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram3 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[19:15]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[63:48]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[63:48]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram4 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[24:20]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[79:64]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[79:64]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram5 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[29:25]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[95:80]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[95:80]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram6 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[34:30]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[111:96]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[111:96]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram7 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[39:35]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[127:112]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[127:112]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram8 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[44:40]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[143:128]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[143:128]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram9 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[49:45]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[159:144]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[159:144]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram10 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[54:50]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[175:160]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[175:160]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram11 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[59:55]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[191:176]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[191:176]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram12 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[64:60]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[207:192]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[207:192]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram13 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[69:65]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[223:208]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[223:208]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram14 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[74:70]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[239:224]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[239:224]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram15 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[79:75]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[255:240]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[255:240]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram16 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[84:80]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[271:256]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[271:256]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram17 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[89:85]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[287:272]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[287:272]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram18 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[94:90]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[303:288]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[303:288]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram19 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[99:95]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[319:304]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[319:304]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram20 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[104:100]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[335:320]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[335:320]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram21 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[109:105]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[351:336]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[351:336]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram22 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[114:110]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[367:352]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[367:352]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram23 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[119:115]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[383:368]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[383:368]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram24 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[124:120]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[399:384]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[399:384]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram25 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[129:125]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[415:400]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[415:400]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram26 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[134:130]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[431:416]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[431:416]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram27 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[139:135]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[447:432]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[447:432]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram28 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[144:140]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[463:448]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[463:448]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram29 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[149:145]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[479:464]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[479:464]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram30 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[154:150]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[495:480]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[495:480]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram31 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[159:155]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[511:496]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[511:496]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_rf_core__wr_rf_full__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_wr_ovld & ~rf_wr_ordy; + endproperty +// Cover 0 : "rf_wr_ovld & ~rf_wr_ordy" + FUNCPOINT_rubik_rf_core__wr_rf_full__0_COV : cover property (rubik_rf_core__wr_rf_full__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_core__rd_rf_empty__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((rf_rd_ovld) && nvdla_core_rstn) |-> (dma_wr_data_rdy & rf_empty); + endproperty +// Cover 1 : "dma_wr_data_rdy & rf_empty" + FUNCPOINT_rubik_rf_core__rd_rf_empty__1_COV : cover property (rubik_rf_core__rd_rf_empty__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_core__push_rf_rdata_block__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_rd_pop_d & ~dma_wr_data_rdy; + endproperty +// Cover 2 : "rf_rd_pop_d & ~dma_wr_data_rdy" + FUNCPOINT_rubik_rf_core__push_rf_rdata_block__2_COV : cover property (rubik_rf_core__push_rf_rdata_block__2_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_RUBIK_rf_core +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is rf_wr_opd[517:0] (rf_wr_ovld,rf_wr_ordy) <= rf_wr_pd[517:0] (rf_wr_vld,rf_wr_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_RF_CORE_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,rf_wr_ordy + ,rf_wr_pd + ,rf_wr_vld + ,rf_wr_opd + ,rf_wr_ovld + ,rf_wr_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input rf_wr_ordy; +input [517:0] rf_wr_pd; +input rf_wr_vld; +output [517:0] rf_wr_opd; +output rf_wr_ovld; +output rf_wr_rdy; +reg [517:0] p1_pipe_data; +reg [517:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [517:0] p1_skid_data; +reg [517:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [517:0] rf_wr_opd; +reg rf_wr_ovld; +reg rf_wr_rdy; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + rf_wr_vld + or p1_pipe_rand_ready + or rf_wr_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = rf_wr_vld; + rf_wr_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = rf_wr_pd[517:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : rf_wr_vld; + rf_wr_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : rf_wr_pd[517:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or rf_wr_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && rf_wr_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or rf_wr_ordy + or p1_pipe_data + ) begin + rf_wr_ovld = p1_pipe_valid; + p1_pipe_ready = rf_wr_ordy; + rf_wr_opd[517:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rf_wr_ovld^rf_wr_ordy^rf_wr_vld^rf_wr_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (rf_wr_vld && !rf_wr_rdy), (rf_wr_vld), (rf_wr_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_RF_CORE_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is rf_rd_opd[177:0] (rf_rd_ovld,rf_rd_ordy) <= rf_rd_pd[177:0] (rf_rd_vld,rf_rd_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_RF_CORE_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,rf_rd_ordy + ,rf_rd_pd + ,rf_rd_vld + ,rf_rd_opd + ,rf_rd_ovld + ,rf_rd_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input rf_rd_ordy; +input [177:0] rf_rd_pd; +input rf_rd_vld; +output [177:0] rf_rd_opd; +output rf_rd_ovld; +output rf_rd_rdy; +reg [177:0] p2_pipe_data; +reg [177:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [177:0] p2_skid_data; +reg [177:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg [177:0] rf_rd_opd; +reg rf_rd_ovld; +reg rf_rd_rdy; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + rf_rd_vld + or p2_pipe_rand_ready + or rf_rd_pd + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = rf_rd_vld; + rf_rd_rdy = p2_pipe_rand_ready; + p2_pipe_rand_data = rf_rd_pd[177:0]; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : rf_rd_vld; + rf_rd_rdy = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : rf_rd_pd[177:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or rf_rd_vld + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && rf_rd_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) skid buffer +always @( + p2_pipe_rand_valid + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_rand_valid && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_rand_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_rand_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_rand_valid + or p2_skid_valid + or p2_pipe_rand_data + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? p2_pipe_rand_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or rf_rd_ordy + or p2_pipe_data + ) begin + rf_rd_ovld = p2_pipe_valid; + p2_pipe_ready = rf_rd_ordy; + rf_rd_opd[177:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rf_rd_ovld^rf_rd_ordy^rf_rd_vld^rf_rd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (rf_rd_vld && !rf_rd_rdy), (rf_rd_vld), (rf_rd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_RF_CORE_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v.vcp new file mode 100644 index 0000000..2980afd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v.vcp @@ -0,0 +1,1987 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_core.v +module NV_NVDLA_RUBIK_rf_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dma_wr_data_rdy //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_rubik_mode //|< i + ,rf_rd_addr //|< i + ,rf_rd_done //|< i + ,rf_rd_mask //|< i + ,rf_rd_vld //|< i + ,rf_wr_addr //|< i + ,rf_wr_data //|< i + ,rf_wr_done //|< i + ,rf_wr_vld //|< i + ,dma_wr_data_pd //|> o + ,dma_wr_data_vld //|> o + ,rf_rd_rdy //|> o + ,rf_wr_rdy //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input rf_wr_vld; +input rf_wr_done; +input [4:0] rf_wr_addr; //row address,increase one when write 64Bytes +input [511:0] rf_wr_data; +output rf_wr_rdy; +input rf_rd_vld; +input rf_rd_done; +input [4:0] rf_rd_addr; //column address,increase one when read 64Bytes +input [11:0] rf_rd_mask; +output rf_rd_rdy; +output dma_wr_data_vld; +output [513:0] dma_wr_data_pd; +input dma_wr_data_rdy; +input [1:0] reg2dp_rubik_mode; +input [1:0] reg2dp_in_precision; +reg dma_wr_data_vld; +reg [511:0] rd_data_raw_reg; +reg [1:0] reg2dp_in_precision_drv2; +reg [1:0] reg2dp_rubik_mode_drv2; +reg [4:0] rf_rd_oaddr_d; +reg [11:0] rf_rd_omask_d; +reg rf_rd_osel_d; +reg rf_rd_pop_d; +reg [1:0] rf_rptr; +reg [1:0] rf_wptr; +wire [31:0] byte_mask_h; +wire [31:0] byte_mask_l; +wire [159:0] contract_rd_addr_shift; +wire [511:0] contract_rd_data; +wire [511:0] contract_wr_shift; +wire [511:0] dma_wr_pd_data; +wire [1:0] dma_wr_pd_mask; +wire m_byte_data; +wire m_contract; +wire m_split; +wire [159:0] merge16_rd_addr_shift; +wire [511:0] merge16_rd_data; +wire [511:0] merge16_wr_shift; +wire [159:0] merge8_rd_addr_shift; +wire [511:0] merge8_rd_data; +wire [511:0] merge8_wr_shift; +wire [159:0] merge_rd_addr_shift; +wire [511:0] merge_rd_data; +wire [511:0] merge_wr_shift; +wire mon_rd_mask_hc; +wire mon_rd_mask_lc; +wire mon_rd_snum; +wire mon_rd_snum1; +wire mon_rd_snum2; +wire mon_wr_snum; +wire mon_wr_snum1; +wire mon_wr_snum2; +wire [159:0] ram_even_seq; +wire [159:0] ram_gene_seq; +wire [159:0] ram_halfh_seq; +wire [159:0] ram_halfl_seq; +wire [159:0] ram_odd_seq; +wire [159:0] ram_rd_addr; +wire [159:0] ram_rd_oaddr; +wire [5:0] rd_addr_incr4; +wire [4:0] rd_addr_tmp; +wire [511:0] rd_data0_raw; +wire [511:0] rd_data1_raw; +wire [511:0] rd_data_raw; +wire [511:0] rd_data_raw_tmp; +wire [5:0] rd_omask_h; +wire [5:0] rd_omask_l; +wire [4:0] rd_shift_num; +wire [4:0] rd_shift_num1; +wire [4:0] rd_shift_num2; +wire rf_empty; +wire rf_full; +wire [511:0] rf_rd_data; +wire [4:0] rf_rd_oaddr; +wire rf_rd_odone; +wire [11:0] rf_rd_omask; +wire [177:0] rf_rd_opd; +wire rf_rd_ordy; +wire rf_rd_osel; +wire rf_rd_ovld; +wire [177:0] rf_rd_pd; +wire rf_rd_pop; +wire [4:0] rf_wr_oaddr; +wire [511:0] rf_wr_odata; +wire rf_wr_odone; +wire [517:0] rf_wr_opd; +wire rf_wr_ordy; +wire rf_wr_osel; +wire rf_wr_ovld; +wire [517:0] rf_wr_pd; +wire rf_wr_pop; +wire [159:0] split16_rd_addr_shift; +wire [511:0] split16_rd_data; +wire [511:0] split16_wr_shift; +wire [159:0] split8_rd_addr_shift; +wire [511:0] split8_rd_data; +wire [511:0] split8_wr_shift; +wire [159:0] split_rd_addr_shift; +wire [511:0] split_rd_data; +wire [511:0] split_wr_shift; +wire [511:0] wr_data_comb16; +wire [511:0] wr_data_comb8; +wire [511:0] wr_data_shift; +wire [4:0] wr_shift_num; +wire [4:0] wr_shift_num1; +wire [4:0] wr_shift_num2; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_rubik_mode_drv2[1:0] <= {2{1'b0}}; + end else begin + reg2dp_rubik_mode_drv2[1:0] <= reg2dp_rubik_mode[1:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_in_precision_drv2[1:0] <= {2{1'b0}}; + end else begin + reg2dp_in_precision_drv2[1:0] <= reg2dp_in_precision[1:0]; + end +end +assign m_contract = reg2dp_rubik_mode_drv2[1:0] == 2'h0 ; +assign m_split = reg2dp_rubik_mode_drv2[1:0] == 2'h1 ; +//assign m_merge = reg2dp_rubik_mode_drv2[1:0] == NVDLA_RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE; +assign m_byte_data = reg2dp_in_precision_drv2[1:0] == 2'h0 ; +function [511:0] shift512_16b; //shift 512bits data with 16bits per one step +input [511:0] di; +input [4:0] snum; +reg [511:0] shf0; +reg [511:0] shf1; +reg [511:0] shf2; +reg [511:0] shf3; +begin + shf0[511:0] = snum[4] ? { di[255:0], di[511:256]} : di[511:0]; + shf1[511:0] = snum[3] ? {shf0[127:0],shf0[511:128]} : shf0[511:0]; + shf2[511:0] = snum[2] ? {shf1[63:0],shf1[511:64]} : shf1[511:0]; + shf3[511:0] = snum[1] ? {shf2[31:0],shf2[511:32]} : shf2[511:0]; + shift512_16b= snum[0] ? {shf3[15:0],shf3[511:16]} : shf3[511:0]; +end +endfunction +function [159:0] shift160_5b; //shift 160bits ram addr with 5bits per one step +input [159:0] di; +input [4:0] snum; +reg [159:0] shf0; +reg [159:0] shf1; +reg [159:0] shf2; +reg [159:0] shf3; +begin + shf0[159:0] = snum[4] ? { di[79:0], di[159:80]} : di[159:0]; + shf1[159:0] = snum[3] ? {shf0[39:0],shf0[159:40]} : shf0[159:0]; + shf2[159:0] = snum[2] ? {shf1[19:0],shf1[159:20]} : shf1[159:0]; + shf3[159:0] = snum[1] ? {shf2[9:0], shf2[159:10]} : shf2[159:0]; + shift160_5b = snum[0] ? {shf3[4:0], shf3[159:5]} : shf3[159:0]; +end +endfunction +function [511:0] data_comb8; //combine atomic0 's element0 with atomic1'element0 in int8 precision +input [511:0] di; +reg [255:0] di0; +reg [255:0] di1; +begin + di0 = di[255:0]; + di1 = di[511:256]; + data_comb8 = {di1[255:248], di0[255:248],di1[247:240], di0[247:240], + di1[239:232], di0[239:232],di1[231:224], di0[231:224], + di1[223:216], di0[223:216],di1[215:208], di0[215:208], + di1[207:200], di0[207:200],di1[199:192], di0[199:192], + di1[191:184], di0[191:184],di1[183:176], di0[183:176], + di1[175:168], di0[175:168],di1[167:160], di0[167:160], + di1[159:152], di0[159:152],di1[151:144], di0[151:144], + di1[143:136], di0[143:136],di1[135:128], di0[135:128], + di1[127:120], di0[127:120],di1[119:112], di0[119:112], + di1[111:104], di0[111:104],di1[103:96], di0[103:96], + di1[95:88], di0[95:88], di1[87:80], di0[87:80], + di1[79:72], di0[79:72], di1[71:64], di0[71:64], + di1[63:56], di0[63:56], di1[55:48], di0[55:48], + di1[47:40], di0[47:40], di1[39:32], di0[39:32], + di1[31:24], di0[31:24], di1[23:16], di0[23:16], + di1[15:8], di0[15:8] , di1[7:0], di0[7:0]}; +end +endfunction +function [511:0] data_comb16; //combine atomic0 's element0 with atomic1'element0 in int16 precision +input [511:0] di; +reg [255:0] di0; +reg [255:0] di1; +begin + di0 = di[255:0]; + di1 = di[511:256]; + data_comb16 = {di1[255:240], di0[255:240],di1[239:224], di0[239:224], + di1[223:208], di0[223:208],di1[207:192], di0[207:192], + di1[191:176], di0[191:176],di1[175:160], di0[175:160], + di1[159:144], di0[159:144],di1[143:128], di0[143:128], + di1[127:112], di0[127:112],di1[111:96], di0[111:96] , + di1[95:80], di0[95:80] ,di1[79:64], di0[79:64], + di1[63:48], di0[63:48] ,di1[47:32], di0[47:32], + di1[31:16], di0[31:16] ,di1[15:0], di0[15:0]}; +end +endfunction +function [511:0] data_recomb8; //re-combine atomic0 's element0 with atomic1'element0 in int8 precision +input [511:0] di; +reg [255:0] di1; +reg [255:0] di0; +reg [127:0] do3; +reg [127:0] do2; +reg [127:0] do1; +reg [127:0] do0; +begin + di0 = di[255:0]; + di1 = di[511:256]; + do3 = {di1[255:248],di1[239:232], + di1[223:216],di1[207:200], + di1[191:184],di1[175:168], + di1[159:152],di1[143:136], + di1[127:120],di1[111:104], + di1[95:88], di1[79:72], + di1[63:56], di1[47:40], + di1[31:24], di1[15:8] }; + do2 = {di1[247:240],di1[231:224], + di1[215:208],di1[199:192], + di1[183:176],di1[167:160], + di1[151:144],di1[135:128], + di1[119:112],di1[103:96], + di1[87:80], di1[71:64], + di1[55:48], di1[39:32], + di1[23:16], di1[7:0]}; + do1 = {di0[255:248],di0[239:232], + di0[223:216],di0[207:200], + di0[191:184],di0[175:168], + di0[159:152],di0[143:136], + di0[127:120],di0[111:104], + di0[95:88], di0[79:72], + di0[63:56], di0[47:40], + di0[31:24], di0[15:8] }; + do0 = {di0[247:240],di0[231:224], + di0[215:208],di0[199:192], + di0[183:176],di0[167:160], + di0[151:144],di0[135:128], + di0[119:112],di0[103:96], + di0[87:80], di0[71:64], + di0[55:48], di0[39:32], + di0[23:16], di0[7:0]}; + data_recomb8 = {do3,do1,do2,do0}; +end +endfunction +function [511:0] data_recomb16; //re-combine atomic0 's element0 with atomic1'element0 in int16 precision +input [511:0] di; +reg [255:0] di1; +reg [255:0] di0; +reg [127:0] do3; +reg [127:0] do2; +reg [127:0] do1; +reg [127:0] do0; +begin + di0 = di[255:0]; + di1 = di[511:256]; + do3 = {di1[255:240],di1[223:208], + di1[191:176],di1[159:144], + di1[127:112],di1[95:80] , + di1[63:48] ,di1[31:16] }; + do2 = {di1[239:224],di1[207:192], + di1[175:160],di1[143:128], + di1[111:96] ,di1[79:64], + di1[47:32] ,di1[15:0]}; + do1 = {di0[255:240],di0[223:208], + di0[191:176],di0[159:144], + di0[127:112],di0[95:80] , + di0[63:48] ,di0[31:16] }; + do0 = {di0[239:224],di0[207:192], + di0[175:160],di0[143:128], + di0[111:96] ,di0[79:64], + di0[47:32] ,di0[15:0]}; + data_recomb16 = {do3,do1,do2,do0}; +end +endfunction +function [255:0] data_mask; +input [255:0] di; +input [31:0] byte_mask; +reg [31:0] data_mask0; +reg [31:0] data_mask1; +reg [31:0] data_mask2; +reg [31:0] data_mask3; +reg [31:0] data_mask4; +reg [31:0] data_mask5; +reg [31:0] data_mask6; +reg [31:0] data_mask7; +begin + data_mask0 = di[31:0] & {{8{byte_mask[3]}}, {8{byte_mask[2]}}, {8{byte_mask[1]}}, {8{byte_mask[0]}}}; + data_mask1 = di[63:32] & {{8{byte_mask[7]}}, {8{byte_mask[6]}}, {8{byte_mask[5]}}, {8{byte_mask[4]}}}; + data_mask2 = di[95:64] & {{8{byte_mask[11]}},{8{byte_mask[10]}},{8{byte_mask[9]}}, {8{byte_mask[8]}}}; + data_mask3 = di[127:96] & {{8{byte_mask[15]}},{8{byte_mask[14]}},{8{byte_mask[13]}},{8{byte_mask[12]}}}; + data_mask4 = di[159:128] & {{8{byte_mask[19]}},{8{byte_mask[18]}},{8{byte_mask[17]}},{8{byte_mask[16]}}}; + data_mask5 = di[191:160] & {{8{byte_mask[23]}},{8{byte_mask[22]}},{8{byte_mask[21]}},{8{byte_mask[20]}}}; + data_mask6 = di[223:192] & {{8{byte_mask[27]}},{8{byte_mask[26]}},{8{byte_mask[25]}},{8{byte_mask[24]}}}; + data_mask7 = di[255:224] & {{8{byte_mask[31]}},{8{byte_mask[30]}},{8{byte_mask[29]}},{8{byte_mask[28]}}}; + data_mask = {data_mask7,data_mask6,data_mask5,data_mask4,data_mask3,data_mask2,data_mask1,data_mask0}; +end +endfunction +//write data shift +assign wr_data_comb8 = data_comb8(rf_wr_data[511:0]); +assign wr_data_comb16 = data_comb16(rf_wr_data[511:0]); +assign {mon_wr_snum, wr_shift_num[4:0] } = 6'h20-rf_wr_addr; +assign {mon_wr_snum1,wr_shift_num1[4:0]} = 6'h20-{rf_wr_addr[4:1],1'b0}; +assign {mon_wr_snum2,wr_shift_num2[4:0]} = 6'h20-{rf_wr_addr[3:0],1'b0}; +assign merge8_wr_shift[511:0] = shift512_16b(rf_wr_data[511:0],wr_shift_num); //merge int8 +assign merge16_wr_shift[511:0] = shift512_16b(rf_wr_data[511:0],wr_shift_num1); +assign merge_wr_shift[511:0] = !m_byte_data ? merge16_wr_shift : merge8_wr_shift; +assign split8_wr_shift[511:0] = shift512_16b(wr_data_comb8,wr_shift_num); //split int8 +assign split16_wr_shift[511:0] = shift512_16b(wr_data_comb16,wr_shift_num2); +assign split_wr_shift[511:0] = !m_byte_data ? split16_wr_shift : split8_wr_shift; +assign contract_wr_shift[511:0]= rf_wr_addr[2] ? {rf_wr_data[255:0],rf_wr_data[511:256]} : rf_wr_data[511:0]; +assign wr_data_shift[511:0] = m_contract ? contract_wr_shift : m_split ? split_wr_shift : merge_wr_shift ; +assign rf_wr_pd[517:0] = {rf_wr_done,rf_wr_addr[4:0],wr_data_shift[511:0]}; +NV_NVDLA_RUBIK_RF_CORE_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.rf_wr_ordy (rf_wr_ordy) //|< w + ,.rf_wr_pd (rf_wr_pd[517:0]) //|< w + ,.rf_wr_vld (rf_wr_vld) //|< i + ,.rf_wr_opd (rf_wr_opd[517:0]) //|> w + ,.rf_wr_ovld (rf_wr_ovld) //|> w + ,.rf_wr_rdy (rf_wr_rdy) //|> o + ); +assign rf_wr_ordy = ~rf_full; +assign rf_wr_pop = rf_wr_ovld & rf_wr_ordy; +assign rf_wr_odone = rf_wr_pop & rf_wr_opd[517]; +assign rf_wr_oaddr = rf_wr_opd[516:512]; +assign rf_wr_odata = rf_wr_opd[511:0]; +assign rf_wr_osel = rf_wptr[0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_wr_odone) + rf_wptr[1:0] <= rf_wptr[1:0] + 1; + end +end +////////////////rf status//////////////////// +assign rf_empty = rf_wptr[1:0]==rf_rptr[1:0]; +assign rf_full = (rf_wptr[1]^rf_rptr[1]) & (rf_wptr[0]==rf_rptr[0]); +//read sram address shift +assign ram_gene_seq[159:0] = {5'h1f,5'h1e,5'h1d,5'h1c,5'h1b,5'h1a,5'h19,5'h18, + 5'h17,5'h16,5'h15,5'h14,5'h13,5'h12,5'h11,5'h10, + 5'h0f,5'h0e,5'h0d,5'h0c,5'h0b,5'h0a,5'h09,5'h08, + 5'h07,5'h06,5'h05,5'h04,5'h03,5'h02,5'h01,5'h00}; +assign ram_even_seq[159:0] = {5'h1e,5'h1e,5'h1c,5'h1c,5'h1a,5'h1a,5'h18,5'h18, + 5'h16,5'h16,5'h14,5'h14,5'h12,5'h12,5'h10,5'h10, + 5'h0e,5'h0e,5'h0c,5'h0c,5'h0a,5'h0a,5'h08,5'h08, + 5'h06,5'h06,5'h04,5'h04,5'h02,5'h02,5'h00,5'h00}; +assign ram_odd_seq[159:0] = {5'h1f,5'h1f,5'h1d,5'h1d,5'h1b,5'h1b,5'h19,5'h19, + 5'h17,5'h17,5'h15,5'h15,5'h13,5'h13,5'h11,5'h11, + 5'h0f,5'h0f,5'h0d,5'h0d,5'h0b,5'h0b,5'h09,5'h09, + 5'h07,5'h07,5'h05,5'h05,5'h03,5'h03,5'h01,5'h01}; +assign ram_halfl_seq[159:0]= {5'h0f,5'h0f,5'h0e,5'h0e,5'h0d,5'h0d,5'h0c,5'h0c, + 5'h0b,5'h0b,5'h0a,5'h0a,5'h09,5'h09,5'h08,5'h08, + 5'h07,5'h07,5'h06,5'h06,5'h05,5'h05,5'h04,5'h04, + 5'h03,5'h03,5'h02,5'h02,5'h01,5'h01,5'h00,5'h00}; +assign ram_halfh_seq[159:0]= {5'h1f,5'h1f,5'h1e,5'h1e,5'h1d,5'h1d,5'h1c,5'h1c, + 5'h1b,5'h1b,5'h1a,5'h1a,5'h19,5'h19,5'h18,5'h18, + 5'h17,5'h17,5'h16,5'h16,5'h15,5'h15,5'h14,5'h14, + 5'h13,5'h13,5'h12,5'h12,5'h11,5'h11,5'h10,5'h10}; +assign {mon_rd_snum, rd_shift_num[4:0] } = 6'h20-rf_rd_addr; +assign {mon_rd_snum1,rd_shift_num1[4:0]} = 6'h20-{rf_rd_addr[4:1],1'b0}; +assign {mon_rd_snum2,rd_shift_num2[4:0]} = 6'h20-{rf_rd_addr[3:0],1'b0}; +assign merge8_rd_addr_shift[159:0] = shift160_5b(ram_gene_seq,rd_shift_num); +assign merge16_rd_addr_shift[159:0] = rf_rd_addr[4] ? shift160_5b(ram_odd_seq,rd_shift_num2) : shift160_5b(ram_even_seq,rd_shift_num2); +assign merge_rd_addr_shift[159:0] = !m_byte_data ? merge16_rd_addr_shift : merge8_rd_addr_shift; +assign split8_rd_addr_shift[159:0] = shift160_5b(ram_gene_seq,rd_shift_num); +assign split16_rd_addr_shift[159:0] = rf_rd_addr[0] ? shift160_5b(ram_halfh_seq,rd_shift_num1) : shift160_5b(ram_halfl_seq,rd_shift_num1); +assign split_rd_addr_shift[159:0] = !m_byte_data ? split16_rd_addr_shift : split8_rd_addr_shift; +assign rd_addr_tmp[4:0] = rf_rd_addr[4:3] + {rf_rd_addr[1:0],3'h0}; +assign rd_addr_incr4[5:0] = rd_addr_tmp[4:0] + 4'h4; +assign contract_rd_addr_shift[159:0] = ~rf_rd_addr[2] ? {{16{rd_addr_incr4[4:0]}}, {16{rd_addr_tmp}}} : {{16{rd_addr_tmp}}, {16{rd_addr_incr4[4:0]}}}; +assign ram_rd_addr[159:0] = m_contract ? contract_rd_addr_shift : m_split ? split_rd_addr_shift : merge_rd_addr_shift ; +assign rf_rd_pd[177:0] = {rf_rd_done,rf_rd_mask[11:0],rf_rd_addr[4:0],ram_rd_addr[159:0]}; +NV_NVDLA_RUBIK_RF_CORE_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.rf_rd_ordy (rf_rd_ordy) //|< w + ,.rf_rd_pd (rf_rd_pd[177:0]) //|< w + ,.rf_rd_vld (rf_rd_vld) //|< i + ,.rf_rd_opd (rf_rd_opd[177:0]) //|> w + ,.rf_rd_ovld (rf_rd_ovld) //|> w + ,.rf_rd_rdy (rf_rd_rdy) //|> o + ); +assign rf_rd_ordy = dma_wr_data_rdy & ~rf_empty; +assign rf_rd_pop = rf_rd_ovld & rf_rd_ordy; +assign rf_rd_odone = rf_rd_pop & rf_rd_opd[177]; +assign rf_rd_omask = rf_rd_opd[176:165]; +assign rf_rd_oaddr = rf_rd_opd[164:160]; +assign ram_rd_oaddr= rf_rd_opd[159:0]; +assign rf_rd_osel = rf_rptr[0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_rd_odone) + rf_rptr[1:0] <= rf_rptr[1:0]+1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_pop_d <= 1'b0; + end else begin + rf_rd_pop_d <= rf_rd_pop; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_osel_d <= 1'b0; + end else begin + rf_rd_osel_d <= rf_rd_osel; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_oaddr_d[4:0] <= {5{1'b0}}; + end else begin + rf_rd_oaddr_d[4:0] <= dma_wr_data_rdy ? rf_rd_oaddr[4:0] : rf_rd_oaddr_d[4:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_omask_d[11:0] <= {12{1'b0}}; + end else begin + rf_rd_omask_d[11:0] <= dma_wr_data_rdy ? rf_rd_omask[11:0] : rf_rd_omask_d[11:0]; + end +end +assign rd_data_raw_tmp[511:0] = rf_rd_osel_d ? rd_data1_raw[511:0] : rd_data0_raw[511:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_data_raw_reg[511:0] <= {512{1'b0}}; + end else begin + if (rf_rd_pop_d) + rd_data_raw_reg[511:0] <= rd_data_raw_tmp[511:0]; + end +end +assign rd_data_raw[511:0] = rf_rd_pop_d & dma_wr_data_rdy ? rd_data_raw_tmp[511:0] : rd_data_raw_reg[511:0]; +//read data shift +assign merge8_rd_data[511:0] = shift512_16b(rd_data_raw,rf_rd_oaddr_d); +assign merge16_rd_data[511:0] = shift512_16b(rd_data_raw,{rf_rd_oaddr_d[3:0],1'b0}); +assign merge_rd_data[511:0] = !m_byte_data ? data_recomb16(merge16_rd_data) : data_recomb8(merge8_rd_data); +assign split8_rd_data[511:0] = shift512_16b(rd_data_raw,rf_rd_oaddr_d); +assign split16_rd_data[511:0] = shift512_16b(rd_data_raw,{rf_rd_oaddr_d[4:1],1'b0}); +assign split_rd_data[511:0] = !m_byte_data ? split16_rd_data : split8_rd_data; +assign contract_rd_data[511:0]= rf_rd_oaddr_d[2] ? {rd_data_raw[255:0],rd_data_raw[511:256]} : rd_data_raw[511:0]; +assign rf_rd_data[511:0] = m_contract ? contract_rd_data : m_split ? split_rd_data : merge_rd_data ; +//write rf rdata to dma data buffer +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_wr_data_vld <= 1'b0; + end else begin + if (rf_rd_pop) + dma_wr_data_vld <=1'b1; + else if (dma_wr_data_vld & dma_wr_data_rdy) + dma_wr_data_vld <=1'b0; + end +end +assign {mon_rd_mask_hc,rd_omask_h[5:0]} = 6'h20-rf_rd_omask_d[11:6]; +assign {mon_rd_mask_lc,rd_omask_l[5:0]} = 6'h20-rf_rd_omask_d[5:0]; +assign byte_mask_h[31:0] = 32'hffffffff >> rd_omask_h; +assign byte_mask_l[31:0] = 32'hffffffff >> rd_omask_l; +assign dma_wr_pd_data[511:0]= {data_mask(rf_rd_data[511:256],byte_mask_h[31:0]),data_mask(rf_rd_data[255:0],byte_mask_l[31:0])}; +assign dma_wr_pd_mask[1:0] = {|rf_rd_omask_d[11:6],|rf_rd_omask_d[5:0]}; +assign dma_wr_data_pd[513:0] = {dma_wr_pd_mask,dma_wr_pd_data}; +//register file 0 : contain 32 rams,one ram is 32x16 +nv_ram_rws_32x16 rubik_rf0_ram0 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[4:0]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[15:0]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[15:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram1 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[9:5]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[31:16]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[31:16]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram2 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[14:10]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[47:32]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[47:32]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram3 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[19:15]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[63:48]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[63:48]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram4 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[24:20]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[79:64]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[79:64]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram5 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[29:25]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[95:80]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[95:80]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram6 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[34:30]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[111:96]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[111:96]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram7 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[39:35]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[127:112]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[127:112]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram8 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[44:40]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[143:128]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[143:128]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram9 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[49:45]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[159:144]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[159:144]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram10 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[54:50]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[175:160]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[175:160]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram11 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[59:55]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[191:176]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[191:176]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram12 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[64:60]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[207:192]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[207:192]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram13 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[69:65]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[223:208]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[223:208]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram14 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[74:70]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[239:224]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[239:224]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram15 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[79:75]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[255:240]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[255:240]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram16 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[84:80]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[271:256]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[271:256]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram17 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[89:85]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[287:272]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[287:272]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram18 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[94:90]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[303:288]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[303:288]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram19 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[99:95]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[319:304]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[319:304]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram20 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[104:100]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[335:320]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[335:320]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram21 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[109:105]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[351:336]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[351:336]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram22 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[114:110]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[367:352]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[367:352]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram23 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[119:115]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[383:368]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[383:368]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram24 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[124:120]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[399:384]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[399:384]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram25 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[129:125]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[415:400]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[415:400]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram26 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[134:130]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[431:416]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[431:416]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram27 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[139:135]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[447:432]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[447:432]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram28 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[144:140]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[463:448]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[463:448]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram29 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[149:145]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[479:464]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[479:464]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram30 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[154:150]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[495:480]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[495:480]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf0_ram31 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[159:155]) //|< w + ,.re (~rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data0_raw[511:496]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (~rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[511:496]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//register file 1 : contain 32 rams,one ram is 32x16 +nv_ram_rws_32x16 rubik_rf1_ram0 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[4:0]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[15:0]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[15:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram1 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[9:5]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[31:16]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[31:16]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram2 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[14:10]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[47:32]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[47:32]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram3 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[19:15]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[63:48]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[63:48]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram4 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[24:20]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[79:64]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[79:64]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram5 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[29:25]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[95:80]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[95:80]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram6 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[34:30]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[111:96]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[111:96]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram7 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[39:35]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[127:112]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[127:112]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram8 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[44:40]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[143:128]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[143:128]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram9 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[49:45]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[159:144]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[159:144]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram10 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[54:50]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[175:160]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[175:160]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram11 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[59:55]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[191:176]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[191:176]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram12 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[64:60]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[207:192]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[207:192]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram13 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[69:65]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[223:208]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[223:208]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram14 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[74:70]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[239:224]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[239:224]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram15 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[79:75]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[255:240]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[255:240]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram16 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[84:80]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[271:256]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[271:256]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram17 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[89:85]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[287:272]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[287:272]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram18 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[94:90]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[303:288]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[303:288]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram19 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[99:95]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[319:304]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[319:304]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram20 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[104:100]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[335:320]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[335:320]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram21 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[109:105]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[351:336]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[351:336]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram22 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[114:110]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[367:352]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[367:352]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram23 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[119:115]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[383:368]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[383:368]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram24 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[124:120]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[399:384]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[399:384]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram25 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[129:125]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[415:400]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[415:400]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram26 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[134:130]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[431:416]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[431:416]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram27 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[139:135]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[447:432]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[447:432]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram28 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[144:140]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[463:448]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[463:448]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram29 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[149:145]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[479:464]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[479:464]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram30 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[154:150]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[495:480]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[495:480]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +nv_ram_rws_32x16 rubik_rf1_ram31 ( + .clk (nvdla_core_clk) //|< i + ,.ra (ram_rd_oaddr[159:155]) //|< w + ,.re (rf_rd_osel & rf_rd_pop) //|< ? + ,.dout (rd_data1_raw[511:496]) //|> w + ,.wa (rf_wr_oaddr[4:0]) //|< w + ,.we (rf_wr_osel & rf_wr_pop) //|< ? + ,.di (rf_wr_odata[511:496]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_rf_core__wr_rf_full__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_wr_ovld & ~rf_wr_ordy; + endproperty +// Cover 0 : "rf_wr_ovld & ~rf_wr_ordy" + FUNCPOINT_rubik_rf_core__wr_rf_full__0_COV : cover property (rubik_rf_core__wr_rf_full__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_core__rd_rf_empty__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((rf_rd_ovld) && nvdla_core_rstn) |-> (dma_wr_data_rdy & rf_empty); + endproperty +// Cover 1 : "dma_wr_data_rdy & rf_empty" + FUNCPOINT_rubik_rf_core__rd_rf_empty__1_COV : cover property (rubik_rf_core__rd_rf_empty__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_core__push_rf_rdata_block__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_rd_pop_d & ~dma_wr_data_rdy; + endproperty +// Cover 2 : "rf_rd_pop_d & ~dma_wr_data_rdy" + FUNCPOINT_rubik_rf_core__push_rf_rdata_block__2_COV : cover property (rubik_rf_core__push_rf_rdata_block__2_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_RUBIK_rf_core +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is rf_wr_opd[517:0] (rf_wr_ovld,rf_wr_ordy) <= rf_wr_pd[517:0] (rf_wr_vld,rf_wr_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_RF_CORE_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,rf_wr_ordy + ,rf_wr_pd + ,rf_wr_vld + ,rf_wr_opd + ,rf_wr_ovld + ,rf_wr_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input rf_wr_ordy; +input [517:0] rf_wr_pd; +input rf_wr_vld; +output [517:0] rf_wr_opd; +output rf_wr_ovld; +output rf_wr_rdy; +reg [517:0] p1_pipe_data; +reg [517:0] p1_pipe_rand_data; +reg p1_pipe_rand_ready; +reg p1_pipe_rand_valid; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [517:0] p1_skid_data; +reg [517:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [517:0] rf_wr_opd; +reg rf_wr_ovld; +reg rf_wr_rdy; +//## pipe (1) randomizer +`ifndef SYNTHESIS +reg p1_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p1_pipe_rand_active + or + `endif + rf_wr_vld + or p1_pipe_rand_ready + or rf_wr_pd + ) begin + `ifdef SYNTHESIS + p1_pipe_rand_valid = rf_wr_vld; + rf_wr_rdy = p1_pipe_rand_ready; + p1_pipe_rand_data = rf_wr_pd[517:0]; + `else +// VCS coverage off + p1_pipe_rand_valid = (p1_pipe_rand_active)? 1'b0 : rf_wr_vld; + rf_wr_rdy = (p1_pipe_rand_active)? 1'b0 : p1_pipe_rand_ready; + p1_pipe_rand_data = (p1_pipe_rand_active)? 'bx : rf_wr_pd[517:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p1_pipe_stall_cycles; +integer p1_pipe_stall_probability; +integer p1_pipe_stall_cycles_min; +integer p1_pipe_stall_cycles_max; +initial begin + p1_pipe_stall_cycles = 0; + p1_pipe_stall_probability = 0; + p1_pipe_stall_cycles_min = 1; + p1_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p1_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p1_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p1_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p1_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability" ) ) p1_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min" ) ) p1_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max" ) ) p1_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p1_pipe_rand_enable; +reg p1_pipe_rand_poised; +always @( + p1_pipe_stall_cycles + or p1_pipe_stall_probability + or rf_wr_vld + ) begin + p1_pipe_rand_active = p1_pipe_stall_cycles != 0; + p1_pipe_rand_enable = p1_pipe_stall_probability != 0; + p1_pipe_rand_poised = p1_pipe_rand_enable && !p1_pipe_rand_active && rf_wr_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_stall_cycles <= 1'b0; + end else begin + if (p1_pipe_rand_poised) begin + if (p1_pipe_stall_probability >= prand_inst0(1, 100)) begin + p1_pipe_stall_cycles <= prand_inst1(p1_pipe_stall_cycles_min, p1_pipe_stall_cycles_max); + end + end else if (p1_pipe_rand_active) begin + p1_pipe_stall_cycles <= p1_pipe_stall_cycles - 1; + end else begin + p1_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (1) skid buffer +always @( + p1_pipe_rand_valid + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = p1_pipe_rand_valid && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + p1_pipe_rand_ready <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + p1_pipe_rand_ready <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or p1_pipe_rand_valid + or p1_skid_valid + or p1_pipe_rand_data + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? p1_pipe_rand_valid : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? p1_pipe_rand_data : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or rf_wr_ordy + or p1_pipe_data + ) begin + rf_wr_ovld = p1_pipe_valid; + p1_pipe_ready = rf_wr_ordy; + rf_wr_opd[517:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rf_wr_ovld^rf_wr_ordy^rf_wr_vld^rf_wr_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (rf_wr_vld && !rf_wr_rdy), (rf_wr_vld), (rf_wr_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_RF_CORE_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is rf_rd_opd[177:0] (rf_rd_ovld,rf_rd_ordy) <= rf_rd_pd[177:0] (rf_rd_vld,rf_rd_rdy) +// ************************************************************************************************************** +module NV_NVDLA_RUBIK_RF_CORE_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,rf_rd_ordy + ,rf_rd_pd + ,rf_rd_vld + ,rf_rd_opd + ,rf_rd_ovld + ,rf_rd_rdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input rf_rd_ordy; +input [177:0] rf_rd_pd; +input rf_rd_vld; +output [177:0] rf_rd_opd; +output rf_rd_ovld; +output rf_rd_rdy; +reg [177:0] p2_pipe_data; +reg [177:0] p2_pipe_rand_data; +reg p2_pipe_rand_ready; +reg p2_pipe_rand_valid; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [177:0] p2_skid_data; +reg [177:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg [177:0] rf_rd_opd; +reg rf_rd_ovld; +reg rf_rd_rdy; +//## pipe (2) randomizer +`ifndef SYNTHESIS +reg p2_pipe_rand_active; +`endif +always @( + `ifndef SYNTHESIS + p2_pipe_rand_active + or + `endif + rf_rd_vld + or p2_pipe_rand_ready + or rf_rd_pd + ) begin + `ifdef SYNTHESIS + p2_pipe_rand_valid = rf_rd_vld; + rf_rd_rdy = p2_pipe_rand_ready; + p2_pipe_rand_data = rf_rd_pd[177:0]; + `else +// VCS coverage off + p2_pipe_rand_valid = (p2_pipe_rand_active)? 1'b0 : rf_rd_vld; + rf_rd_rdy = (p2_pipe_rand_active)? 1'b0 : p2_pipe_rand_ready; + p2_pipe_rand_data = (p2_pipe_rand_active)? 'bx : rf_rd_pd[177:0]; +// VCS coverage on + `endif +end +`ifndef SYNTHESIS +// VCS coverage off +//// randomization init +integer p2_pipe_stall_cycles; +integer p2_pipe_stall_probability; +integer p2_pipe_stall_cycles_min; +integer p2_pipe_stall_cycles_max; +initial begin + p2_pipe_stall_cycles = 0; + p2_pipe_stall_probability = 0; + p2_pipe_stall_cycles_min = 1; + p2_pipe_stall_cycles_max = 10; +`ifndef SYNTH_LEVEL1_COMPILE + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + else if ( $value$plusargs( "default_pipe_rand_probability=%d", p2_pipe_stall_probability ) ) ; // deprecated + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + else if ( $value$plusargs( "default_pipe_stall_probability=%d", p2_pipe_stall_probability ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_min=%d", p2_pipe_stall_cycles_min ) ) ; + if ( $value$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; + else if ( $value$plusargs( "default_pipe_stall_cycles_max=%d", p2_pipe_stall_cycles_max ) ) ; +`endif +end +// randomization globals +`ifndef SYNTH_LEVEL1_COMPILE +`ifdef SIMTOP_RANDOMIZE_STALLS +always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_probability" ) ) p2_pipe_stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_min" ) ) p2_pipe_stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_rf_core_pipe_stall_cycles_max" ) ) p2_pipe_stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_pipe_cycles_max; +end +`endif +`endif +//// randomization active +reg p2_pipe_rand_enable; +reg p2_pipe_rand_poised; +always @( + p2_pipe_stall_cycles + or p2_pipe_stall_probability + or rf_rd_vld + ) begin + p2_pipe_rand_active = p2_pipe_stall_cycles != 0; + p2_pipe_rand_enable = p2_pipe_stall_probability != 0; + p2_pipe_rand_poised = p2_pipe_rand_enable && !p2_pipe_rand_active && rf_rd_vld === 1'b1; +end +//// randomization cycles +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_stall_cycles <= 1'b0; + end else begin + if (p2_pipe_rand_poised) begin + if (p2_pipe_stall_probability >= prand_inst0(1, 100)) begin + p2_pipe_stall_cycles <= prand_inst1(p2_pipe_stall_cycles_min, p2_pipe_stall_cycles_max); + end + end else if (p2_pipe_rand_active) begin + p2_pipe_stall_cycles <= p2_pipe_stall_cycles - 1; + end else begin + p2_pipe_stall_cycles <= 0; + end + end +end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`endif +// VCS coverage on +//## pipe (2) skid buffer +always @( + p2_pipe_rand_valid + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = p2_pipe_rand_valid && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + p2_pipe_rand_ready <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + p2_pipe_rand_ready <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or p2_pipe_rand_valid + or p2_skid_valid + or p2_pipe_rand_data + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? p2_pipe_rand_valid : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? p2_pipe_rand_data : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or rf_rd_ordy + or p2_pipe_data + ) begin + rf_rd_ovld = p2_pipe_valid; + p2_pipe_ready = rf_rd_ordy; + rf_rd_opd[177:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (rf_rd_ovld^rf_rd_ordy^rf_rd_vld^rf_rd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (rf_rd_vld && !rf_rd_rdy), (rf_rd_vld), (rf_rd_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_RUBIK_RF_CORE_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v new file mode 100644 index 0000000..6fe7b7a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v @@ -0,0 +1,499 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_ctrl.v +module NV_NVDLA_RUBIK_rf_ctrl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,contract_lit_dx //|< i + ,data_fifo_pd //|< i + ,data_fifo_vld //|< i + ,inwidth //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_rubik_mode //|< i + ,rf_rd_cmd_pd //|< i + ,rf_rd_cmd_vld //|< i + ,rf_rd_rdy //|< i + ,rf_wr_cmd_pd //|< i + ,rf_wr_cmd_vld //|< i + ,rf_wr_rdy //|< i + ,data_fifo_rdy //|> o + ,rf_rd_addr //|> o + ,rf_rd_cmd_rdy //|> o + ,rf_rd_done //|> o + ,rf_rd_mask //|> o + ,rf_rd_vld //|> o + ,rf_wr_addr //|> o + ,rf_wr_cmd_rdy //|> o + ,rf_wr_data //|> o + ,rf_wr_done //|> o + ,rf_wr_vld //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input contract_lit_dx; +input [13:0] inwidth; +input [31:0] pwrbus_ram_pd; +input rf_wr_cmd_vld; +input [10:0] rf_wr_cmd_pd; +output rf_wr_cmd_rdy; +input rf_rd_cmd_vld; +input [11:0] rf_rd_cmd_pd; +output rf_rd_cmd_rdy; +input data_fifo_vld; +input [511:0] data_fifo_pd; +output data_fifo_rdy; +output rf_wr_vld; +output rf_wr_done; +output [4:0] rf_wr_addr; +output [511:0] rf_wr_data; +input rf_wr_rdy; +output rf_rd_vld; +output rf_rd_done; +output [11:0] rf_rd_mask; +output [4:0] rf_rd_addr; +input rf_rd_rdy; +input [1:0] reg2dp_rubik_mode; +input [1:0] reg2dp_in_precision; +reg mon_rf_rd_ccnt; +reg mon_rf_rd_gcnt; +reg mon_rf_rd_rcnt; +reg mon_rf_wr_ccnt; +reg mon_rf_wr_rcnt; +reg [6:0] rd_total_col_reg; +reg [6:0] rd_total_row_reg; +reg [1:0] reg2dp_in_precision_drv1; +reg [1:0] reg2dp_rubik_mode_drv1; +reg [4:0] rf_rd_addr; +reg [4:0] rf_rd_ccnt; +reg rf_rd_cmd_open; +reg rf_rd_cmd_ordy_hold; +reg [10:0] rf_rd_gcnt; +reg [5:0] rf_rd_rcnt; +reg [1:0] rf_rptr; +reg [1:0] rf_wptr; +reg [4:0] rf_wr_addr; +reg [4:0] rf_wr_ccnt; +reg rf_wr_cmd_open; +reg rf_wr_cmd_ordy_hold; +reg [4:0] rf_wr_rcnt; +reg [6:0] wr_total_col_reg; +reg [5:0] wr_total_row_reg; +wire [1:0] contract_atom_mask; +wire [11:0] contract_rd_mask; +wire m_byte_data; +wire m_contract; +wire m_split; +wire [1:0] merge_atom_mask; +wire [5:0] merge_byte_mask; +wire [11:0] merge_rd_mask; +wire mon_rd_tcol_c; +wire mon_remain_byte; +wire mon_remain_byte1; +wire mon_remain_rd_col; +wire mon_remain_rd_row; +wire mon_wr_tcol_c; +wire [7:0] rd_byte_num; +wire [11:0] rd_grp_num; +wire [6:0] rd_total_col; +wire [6:0] rd_total_col_tmp; +wire [5:0] rd_total_colm; +wire [6:0] rd_total_pcol; +wire [6:0] rd_total_prow; +wire [6:0] rd_total_row; +wire [6:0] rd_total_row_tmp; +wire [7:0] remain_byte; +wire [7:0] remain_byte1; +wire [6:0] remain_rd_col; +wire [6:0] remain_rd_row; +wire rf_full; +wire rf_nempty; +wire [5:0] rf_rd_ccnt_inc; +wire [11:0] rf_rd_cmd_opd; +wire rf_rd_cmd_ordy; +wire rf_rd_cmd_ovld; +wire rf_rd_col_end; +wire [11:0] rf_rd_gcnt_inc; +wire rf_rd_grp_end; +wire [6:0] rf_rd_rcnt_inc; +wire rf_rd_row_end; +wire [5:0] rf_wr_ccnt_inc; +wire [10:0] rf_wr_cmd_opd; +wire rf_wr_cmd_ordy; +wire rf_wr_cmd_ovld; +wire rf_wr_col_end; +wire [5:0] rf_wr_rcnt_inc; +wire rf_wr_row_end; +wire [11:0] split_rd_mask; +wire [6:0] wr_total_col; +wire [5:0] wr_total_colm; +wire [6:0] wr_total_pcol; +wire [5:0] wr_total_prow; +wire [5:0] wr_total_row; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_rubik_mode_drv1[1:0] <= {2{1'b0}}; + end else begin + reg2dp_rubik_mode_drv1[1:0] <= reg2dp_rubik_mode[1:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_in_precision_drv1[1:0] <= {2{1'b0}}; + end else begin + reg2dp_in_precision_drv1[1:0] <= reg2dp_in_precision[1:0]; + end +end +assign m_contract = reg2dp_rubik_mode_drv1[1:0] == 2'h0 ; +assign m_split = reg2dp_rubik_mode_drv1[1:0] == 2'h1 ; +//assign m_merge = reg2dp_rubik_mode_drv1[1:0] == NVDLA_RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE; +assign m_byte_data = reg2dp_in_precision_drv1[1:0] == 2'h0 ; +//////////////////////////////////////////////////////////////////////////////// +//////////////pop total row,total columun from rf_wr_cmd_fifo////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_cmd_ordy_hold <= 1'b1; + end else begin + if (rf_wr_cmd_ordy_hold & rf_wr_cmd_ovld) + rf_wr_cmd_ordy_hold <= 1'b0; + else if(rf_wr_row_end & ~rf_wr_cmd_ovld) + rf_wr_cmd_ordy_hold <= 1'b1; + end +end +assign rf_wr_cmd_ordy = rf_wr_row_end | rf_wr_cmd_ordy_hold; +assign wr_total_pcol[6:0] = rf_wr_cmd_opd[5:0]+1; +assign wr_total_prow[5:0] = rf_wr_cmd_opd[10:6]+1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_total_col_reg[6:0] <= {7{1'b0}}; + wr_total_row_reg[5:0] <= {6{1'b0}}; + end else begin + if (rf_wr_cmd_ovld & rf_wr_cmd_ordy) begin + wr_total_col_reg[6:0] <= wr_total_pcol[6:0]; + wr_total_row_reg[5:0] <= wr_total_prow[5:0]; + end + end +end +assign wr_total_col[6:0] = wr_total_col_reg[6:0]; +assign wr_total_row[5:0] = wr_total_row_reg[5:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_cmd_open <= 1'b0; + end else begin + if (rf_wr_cmd_ovld & rf_wr_cmd_ordy) + rf_wr_cmd_open <= 1'b1; + else if(rf_wr_row_end) + rf_wr_cmd_open <= 1'b0; + end +end +//////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////generate rf write address & data //////////////////////////// +assign data_fifo_rdy = rf_wr_cmd_open & rf_wr_rdy & ~rf_full & data_fifo_vld; //fifo random stall +assign rf_wr_vld = data_fifo_vld & data_fifo_rdy; +assign rf_wr_data = data_fifo_pd[511:0]; +assign rf_wr_done = rf_wr_row_end; +//in contract mode,when write one row is done,wr_addr should skip to a fix address +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_addr <= {5{1'b0}}; + end else begin + if (rf_wr_row_end) begin + rf_wr_addr <= 5'h0; + end + else if(m_contract & rf_wr_col_end) begin + rf_wr_addr <= {rf_wr_rcnt_inc[2:0],2'b0}; + end + else if(~m_split & ~m_contract & ~m_byte_data & rf_wr_col_end) begin + rf_wr_addr <= {rf_wr_rcnt_inc[3:0],1'b0}; + end + else if(rf_wr_vld) begin + rf_wr_addr <= rf_wr_addr + 1'b1; + end + end +end +//rf column counter & row counter +assign rf_wr_ccnt_inc[5:0] = rf_wr_ccnt + 1; +assign {mon_wr_tcol_c,wr_total_colm[5:0]} = wr_total_col[6:1]+wr_total_col[0]; +assign rf_wr_col_end = rf_wr_vld & (rf_wr_ccnt_inc >= wr_total_colm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_ccnt <= {5{1'b0}}; + {mon_rf_wr_ccnt,rf_wr_ccnt} <= {6{1'b0}}; + end else begin + if (rf_wr_col_end) begin + rf_wr_ccnt <= 5'h0; + end + else if(rf_wr_vld) begin + {mon_rf_wr_ccnt,rf_wr_ccnt} <= rf_wr_ccnt_inc; + end + end +end +assign rf_wr_rcnt_inc[5:0] = rf_wr_rcnt + 1; +assign rf_wr_row_end = rf_wr_col_end & (rf_wr_rcnt_inc == wr_total_row); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_rcnt <= {5{1'b0}}; + {mon_rf_wr_rcnt,rf_wr_rcnt} <= {6{1'b0}}; + end else begin + if (rf_wr_row_end) begin + rf_wr_rcnt <= 5'h0; + end + else if(rf_wr_col_end) begin + {mon_rf_wr_rcnt,rf_wr_rcnt} <= rf_wr_rcnt_inc; + end + end +end +NV_NVDLA_RUBIK_rf_wcmd rbk_rf_wr_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (rf_wr_cmd_rdy) //|> o + ,.idata_pvld (rf_wr_cmd_vld) //|< i + ,.idata_pd (rf_wr_cmd_pd[10:0]) //|< i + ,.odata_prdy (rf_wr_cmd_ordy) //|< w + ,.odata_pvld (rf_wr_cmd_ovld) //|> w + ,.odata_pd (rf_wr_cmd_opd[10:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////////////// +//////////////pop total row,total columun from rf_rd_cmd_fifo////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_cmd_ordy_hold <= 1'b1; + end else begin + if (rf_rd_cmd_ordy_hold & rf_rd_cmd_ovld) + rf_rd_cmd_ordy_hold <= 1'b0; + else if(rf_rd_grp_end & ~rf_rd_cmd_ovld) + rf_rd_cmd_ordy_hold <= 1'b1; + end +end +assign rf_rd_cmd_ordy = rf_rd_grp_end | rf_rd_cmd_ordy_hold; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_cmd_open <= 1'b0; + end else begin + if (rf_rd_cmd_ovld & rf_rd_cmd_ordy) + rf_rd_cmd_open <= 1'b1; + else if(rf_rd_grp_end) + rf_rd_cmd_open <= 1'b0; + end +end +//merge and split of read total column unit is element(1byte or 2byte), but contract unit is 32bytes +assign rd_total_pcol[6:0] = rf_rd_cmd_opd[5:0]+1; +assign rd_total_prow[6:0] = rf_rd_cmd_opd[11:6]+1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_total_col_reg[6:0] <= {7{1'b0}}; + rd_total_row_reg[6:0] <= {7{1'b0}}; + end else begin + if (rf_rd_cmd_ovld & rf_rd_cmd_ordy) begin + rd_total_col_reg[6:0] <= rd_total_pcol[6:0]; + rd_total_row_reg[6:0] <= rd_total_prow[6:0]; + end + end +end +assign rd_total_col_tmp[6:0] = rd_total_col_reg[6:0]; +assign rd_total_row_tmp[6:0] = rd_total_row_reg[6:0]; +assign rd_grp_num[11:0] = |inwidth[2:0] ? inwidth[13:3]+1 : inwidth[13:3]; +assign rd_total_col[6:0] = m_contract ? rd_total_col_tmp : m_split ? (m_byte_data ? 2'h2 : rd_total_col_tmp > 8'h20 ? 4'h4 : 4'h2) : rd_total_row_tmp; +assign rd_total_row[6:0] = contract_lit_dx ? (rf_rd_gcnt_inc == rd_grp_num ? (|inwidth[2:0] ? inwidth[2:0] : 7'h8) : 7'h8) : (m_contract | m_split) ? rd_total_row_tmp : 1'b1; +//////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////generate rf read address /////////////////////////////////// +assign rf_rd_vld = rf_rd_rdy & rf_nempty & rf_rd_cmd_open; +assign rf_rd_done = rf_rd_row_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_addr <= {5{1'b0}}; + end else begin + if (rf_rd_row_end) begin + rf_rd_addr <= 5'h0; + end + else if(m_contract & rf_rd_col_end) begin + rf_rd_addr <= {rf_rd_rcnt_inc[2:0],2'b0}; + end + else if(m_split & ~m_byte_data & rf_rd_col_end) begin + rf_rd_addr <= {rf_rd_rcnt_inc[3:0],1'b0}; + end + else if(rf_rd_vld) begin + rf_rd_addr <= rf_rd_addr + 1'b1; + end + end +end +assign rf_rd_ccnt_inc[5:0] = rf_rd_ccnt + 1; +assign {mon_rd_tcol_c,rd_total_colm[5:0]} = rd_total_col[6:1] + rd_total_col[0]; +assign rf_rd_col_end = rf_rd_vld & (rf_rd_ccnt_inc >= rd_total_colm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_ccnt <= {5{1'b0}}; + {mon_rf_rd_ccnt,rf_rd_ccnt} <= {6{1'b0}}; + end else begin + if (rf_rd_col_end) begin + rf_rd_ccnt <= 5'h0; + end + else if(rf_rd_vld) begin + {mon_rf_rd_ccnt,rf_rd_ccnt} <= rf_rd_ccnt_inc; + end + end +end +assign rf_rd_rcnt_inc[6:0] = rf_rd_rcnt + 1; +assign rf_rd_row_end = rf_rd_col_end & (rf_rd_rcnt_inc == rd_total_row); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_rcnt <= {6{1'b0}}; + {mon_rf_rd_rcnt,rf_rd_rcnt} <= {7{1'b0}}; + end else begin + if (rf_rd_row_end) begin + rf_rd_rcnt <= 6'h0; + end + else if(rf_rd_col_end) begin + {mon_rf_rd_rcnt,rf_rd_rcnt} <= rf_rd_rcnt_inc; + end + end +end +assign rf_rd_gcnt_inc[11:0] = rf_rd_gcnt + 1; +assign rf_rd_grp_end = rf_rd_row_end & (rf_rd_gcnt_inc == (contract_lit_dx ? rd_grp_num : 1'b1)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_gcnt <= {11{1'b0}}; + {mon_rf_rd_gcnt,rf_rd_gcnt} <= {12{1'b0}}; + end else begin + if (rf_rd_grp_end) begin + rf_rd_gcnt <= 11'h0; + end + else if(rf_rd_row_end) begin + {mon_rf_rd_gcnt,rf_rd_gcnt} <= rf_rd_gcnt_inc; + end + end +end +/////////////generate the 64byte data mask////////// +//rf_rd_mask[5:0] : how many valid byte of atomic0 +//rf_rd_mask[11:6] : how many valid byte of atomic1 +assign {mon_remain_rd_row,remain_rd_row[6:0]} = rd_total_row_tmp - {rf_rd_ccnt,1'b0}; +assign {mon_remain_rd_col,remain_rd_col[6:0]} = rd_total_col_tmp - {rf_rd_ccnt,1'b0}; +assign rd_byte_num[7:0] = m_byte_data ? {1'b0,rd_total_col_tmp} : {rd_total_col_tmp,1'b0}; +assign {mon_remain_byte, remain_byte[7:0] } = rd_byte_num - {rf_rd_ccnt[1:0],6'h0}; +assign {mon_remain_byte1,remain_byte1[7:0]} = rd_byte_num - {rf_rd_ccnt[1:0],6'h0} - 8'h20; +assign split_rd_mask[11:0] = (remain_byte >= 8'h40) ? {6'h20,6'h20} : + (remain_byte >= 8'h20) ? {remain_byte1[5:0],6'h20} : {6'h0,remain_byte[5:0]}; +assign merge_byte_mask[5:0] = m_byte_data ? rd_total_col_tmp[5:0] : {rd_total_col_tmp[4:0],1'b0}; +assign merge_atom_mask[1:0] = remain_rd_row == 7'b1 ? 2'b01 : 2'b11; +assign merge_rd_mask[11:0] = ~merge_atom_mask[1] ? {6'h0,merge_byte_mask[5:0]} : {merge_byte_mask[5:0],merge_byte_mask[5:0]}; +assign contract_atom_mask[1:0] = remain_rd_col == 7'b1 ? 2'b01 : 2'b11; +assign contract_rd_mask[11:0] = ~contract_atom_mask[1] ? {6'h0,6'h20} : {6'h20,6'h20}; +assign rf_rd_mask[11:0] = m_contract ? contract_rd_mask : m_split ? split_rd_mask : merge_rd_mask; +NV_NVDLA_RUBIK_rf_rcmd rbk_rf_rd_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (rf_rd_cmd_rdy) //|> o + ,.idata_pvld (rf_rd_cmd_vld) //|< i + ,.idata_pd (rf_rd_cmd_pd[11:0]) //|< i + ,.odata_prdy (rf_rd_cmd_ordy) //|< w + ,.odata_pvld (rf_rd_cmd_ovld) //|> w + ,.odata_pd (rf_rd_cmd_opd[11:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +////////////////rf status//////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_wr_done) + rf_wptr[1:0] <= rf_wptr[1:0] + 1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_rd_done) + rf_rptr[1:0] <= rf_rptr[1:0]+1; + end +end +assign rf_nempty = ~(rf_wptr[1:0]==rf_rptr[1:0]); +assign rf_full = (rf_wptr[1]^rf_rptr[1]) & (rf_wptr[0]==rf_rptr[0]); +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_rf_ctrl__rf_wr_cmd_pop_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_wr_row_end & ~rf_wr_cmd_ovld; + endproperty +// Cover 0 : "rf_wr_row_end & ~rf_wr_cmd_ovld" + FUNCPOINT_rubik_rf_ctrl__rf_wr_cmd_pop_block__0_COV : cover property (rubik_rf_ctrl__rf_wr_cmd_pop_block__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_wr_data_full__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((data_fifo_vld) && nvdla_core_rstn) |-> (rf_wr_rdy & rf_full); + endproperty +// Cover 1 : "rf_wr_rdy & rf_full" + FUNCPOINT_rubik_rf_ctrl__rf_wr_data_full__1_COV : cover property (rubik_rf_ctrl__rf_wr_data_full__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_rd_cmd_pop_block__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_rd_grp_end & ~rf_rd_cmd_ovld; + endproperty +// Cover 2 : "rf_rd_grp_end & ~rf_rd_cmd_ovld" + FUNCPOINT_rubik_rf_ctrl__rf_rd_cmd_pop_block__2_COV : cover property (rubik_rf_ctrl__rf_rd_cmd_pop_block__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_rd_data_after_cmd__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ~rf_rd_cmd_open & rf_rd_rdy & rf_nempty; + endproperty +// Cover 3 : "~rf_rd_cmd_open & rf_rd_rdy & rf_nempty" + FUNCPOINT_rubik_rf_ctrl__rf_rd_data_after_cmd__3_COV : cover property (rubik_rf_ctrl__rf_rd_data_after_cmd__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_rd_data_empty__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((rf_rd_cmd_open) && nvdla_core_rstn) |-> (rf_rd_rdy & ~rf_nempty); + endproperty +// Cover 4 : "rf_rd_rdy & ~rf_nempty" + FUNCPOINT_rubik_rf_ctrl__rf_rd_data_empty__4_COV : cover property (rubik_rf_ctrl__rf_rd_data_empty__4_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_RUBIK_rf_ctrl diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v.vcp new file mode 100644 index 0000000..6fe7b7a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v.vcp @@ -0,0 +1,499 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_ctrl.v +module NV_NVDLA_RUBIK_rf_ctrl ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,contract_lit_dx //|< i + ,data_fifo_pd //|< i + ,data_fifo_vld //|< i + ,inwidth //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_rubik_mode //|< i + ,rf_rd_cmd_pd //|< i + ,rf_rd_cmd_vld //|< i + ,rf_rd_rdy //|< i + ,rf_wr_cmd_pd //|< i + ,rf_wr_cmd_vld //|< i + ,rf_wr_rdy //|< i + ,data_fifo_rdy //|> o + ,rf_rd_addr //|> o + ,rf_rd_cmd_rdy //|> o + ,rf_rd_done //|> o + ,rf_rd_mask //|> o + ,rf_rd_vld //|> o + ,rf_wr_addr //|> o + ,rf_wr_cmd_rdy //|> o + ,rf_wr_data //|> o + ,rf_wr_done //|> o + ,rf_wr_vld //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input contract_lit_dx; +input [13:0] inwidth; +input [31:0] pwrbus_ram_pd; +input rf_wr_cmd_vld; +input [10:0] rf_wr_cmd_pd; +output rf_wr_cmd_rdy; +input rf_rd_cmd_vld; +input [11:0] rf_rd_cmd_pd; +output rf_rd_cmd_rdy; +input data_fifo_vld; +input [511:0] data_fifo_pd; +output data_fifo_rdy; +output rf_wr_vld; +output rf_wr_done; +output [4:0] rf_wr_addr; +output [511:0] rf_wr_data; +input rf_wr_rdy; +output rf_rd_vld; +output rf_rd_done; +output [11:0] rf_rd_mask; +output [4:0] rf_rd_addr; +input rf_rd_rdy; +input [1:0] reg2dp_rubik_mode; +input [1:0] reg2dp_in_precision; +reg mon_rf_rd_ccnt; +reg mon_rf_rd_gcnt; +reg mon_rf_rd_rcnt; +reg mon_rf_wr_ccnt; +reg mon_rf_wr_rcnt; +reg [6:0] rd_total_col_reg; +reg [6:0] rd_total_row_reg; +reg [1:0] reg2dp_in_precision_drv1; +reg [1:0] reg2dp_rubik_mode_drv1; +reg [4:0] rf_rd_addr; +reg [4:0] rf_rd_ccnt; +reg rf_rd_cmd_open; +reg rf_rd_cmd_ordy_hold; +reg [10:0] rf_rd_gcnt; +reg [5:0] rf_rd_rcnt; +reg [1:0] rf_rptr; +reg [1:0] rf_wptr; +reg [4:0] rf_wr_addr; +reg [4:0] rf_wr_ccnt; +reg rf_wr_cmd_open; +reg rf_wr_cmd_ordy_hold; +reg [4:0] rf_wr_rcnt; +reg [6:0] wr_total_col_reg; +reg [5:0] wr_total_row_reg; +wire [1:0] contract_atom_mask; +wire [11:0] contract_rd_mask; +wire m_byte_data; +wire m_contract; +wire m_split; +wire [1:0] merge_atom_mask; +wire [5:0] merge_byte_mask; +wire [11:0] merge_rd_mask; +wire mon_rd_tcol_c; +wire mon_remain_byte; +wire mon_remain_byte1; +wire mon_remain_rd_col; +wire mon_remain_rd_row; +wire mon_wr_tcol_c; +wire [7:0] rd_byte_num; +wire [11:0] rd_grp_num; +wire [6:0] rd_total_col; +wire [6:0] rd_total_col_tmp; +wire [5:0] rd_total_colm; +wire [6:0] rd_total_pcol; +wire [6:0] rd_total_prow; +wire [6:0] rd_total_row; +wire [6:0] rd_total_row_tmp; +wire [7:0] remain_byte; +wire [7:0] remain_byte1; +wire [6:0] remain_rd_col; +wire [6:0] remain_rd_row; +wire rf_full; +wire rf_nempty; +wire [5:0] rf_rd_ccnt_inc; +wire [11:0] rf_rd_cmd_opd; +wire rf_rd_cmd_ordy; +wire rf_rd_cmd_ovld; +wire rf_rd_col_end; +wire [11:0] rf_rd_gcnt_inc; +wire rf_rd_grp_end; +wire [6:0] rf_rd_rcnt_inc; +wire rf_rd_row_end; +wire [5:0] rf_wr_ccnt_inc; +wire [10:0] rf_wr_cmd_opd; +wire rf_wr_cmd_ordy; +wire rf_wr_cmd_ovld; +wire rf_wr_col_end; +wire [5:0] rf_wr_rcnt_inc; +wire rf_wr_row_end; +wire [11:0] split_rd_mask; +wire [6:0] wr_total_col; +wire [5:0] wr_total_colm; +wire [6:0] wr_total_pcol; +wire [5:0] wr_total_prow; +wire [5:0] wr_total_row; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_rubik_mode_drv1[1:0] <= {2{1'b0}}; + end else begin + reg2dp_rubik_mode_drv1[1:0] <= reg2dp_rubik_mode[1:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_in_precision_drv1[1:0] <= {2{1'b0}}; + end else begin + reg2dp_in_precision_drv1[1:0] <= reg2dp_in_precision[1:0]; + end +end +assign m_contract = reg2dp_rubik_mode_drv1[1:0] == 2'h0 ; +assign m_split = reg2dp_rubik_mode_drv1[1:0] == 2'h1 ; +//assign m_merge = reg2dp_rubik_mode_drv1[1:0] == NVDLA_RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE; +assign m_byte_data = reg2dp_in_precision_drv1[1:0] == 2'h0 ; +//////////////////////////////////////////////////////////////////////////////// +//////////////pop total row,total columun from rf_wr_cmd_fifo////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_cmd_ordy_hold <= 1'b1; + end else begin + if (rf_wr_cmd_ordy_hold & rf_wr_cmd_ovld) + rf_wr_cmd_ordy_hold <= 1'b0; + else if(rf_wr_row_end & ~rf_wr_cmd_ovld) + rf_wr_cmd_ordy_hold <= 1'b1; + end +end +assign rf_wr_cmd_ordy = rf_wr_row_end | rf_wr_cmd_ordy_hold; +assign wr_total_pcol[6:0] = rf_wr_cmd_opd[5:0]+1; +assign wr_total_prow[5:0] = rf_wr_cmd_opd[10:6]+1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_total_col_reg[6:0] <= {7{1'b0}}; + wr_total_row_reg[5:0] <= {6{1'b0}}; + end else begin + if (rf_wr_cmd_ovld & rf_wr_cmd_ordy) begin + wr_total_col_reg[6:0] <= wr_total_pcol[6:0]; + wr_total_row_reg[5:0] <= wr_total_prow[5:0]; + end + end +end +assign wr_total_col[6:0] = wr_total_col_reg[6:0]; +assign wr_total_row[5:0] = wr_total_row_reg[5:0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_cmd_open <= 1'b0; + end else begin + if (rf_wr_cmd_ovld & rf_wr_cmd_ordy) + rf_wr_cmd_open <= 1'b1; + else if(rf_wr_row_end) + rf_wr_cmd_open <= 1'b0; + end +end +//////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////generate rf write address & data //////////////////////////// +assign data_fifo_rdy = rf_wr_cmd_open & rf_wr_rdy & ~rf_full & data_fifo_vld; //fifo random stall +assign rf_wr_vld = data_fifo_vld & data_fifo_rdy; +assign rf_wr_data = data_fifo_pd[511:0]; +assign rf_wr_done = rf_wr_row_end; +//in contract mode,when write one row is done,wr_addr should skip to a fix address +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_addr <= {5{1'b0}}; + end else begin + if (rf_wr_row_end) begin + rf_wr_addr <= 5'h0; + end + else if(m_contract & rf_wr_col_end) begin + rf_wr_addr <= {rf_wr_rcnt_inc[2:0],2'b0}; + end + else if(~m_split & ~m_contract & ~m_byte_data & rf_wr_col_end) begin + rf_wr_addr <= {rf_wr_rcnt_inc[3:0],1'b0}; + end + else if(rf_wr_vld) begin + rf_wr_addr <= rf_wr_addr + 1'b1; + end + end +end +//rf column counter & row counter +assign rf_wr_ccnt_inc[5:0] = rf_wr_ccnt + 1; +assign {mon_wr_tcol_c,wr_total_colm[5:0]} = wr_total_col[6:1]+wr_total_col[0]; +assign rf_wr_col_end = rf_wr_vld & (rf_wr_ccnt_inc >= wr_total_colm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_ccnt <= {5{1'b0}}; + {mon_rf_wr_ccnt,rf_wr_ccnt} <= {6{1'b0}}; + end else begin + if (rf_wr_col_end) begin + rf_wr_ccnt <= 5'h0; + end + else if(rf_wr_vld) begin + {mon_rf_wr_ccnt,rf_wr_ccnt} <= rf_wr_ccnt_inc; + end + end +end +assign rf_wr_rcnt_inc[5:0] = rf_wr_rcnt + 1; +assign rf_wr_row_end = rf_wr_col_end & (rf_wr_rcnt_inc == wr_total_row); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wr_rcnt <= {5{1'b0}}; + {mon_rf_wr_rcnt,rf_wr_rcnt} <= {6{1'b0}}; + end else begin + if (rf_wr_row_end) begin + rf_wr_rcnt <= 5'h0; + end + else if(rf_wr_col_end) begin + {mon_rf_wr_rcnt,rf_wr_rcnt} <= rf_wr_rcnt_inc; + end + end +end +NV_NVDLA_RUBIK_rf_wcmd rbk_rf_wr_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (rf_wr_cmd_rdy) //|> o + ,.idata_pvld (rf_wr_cmd_vld) //|< i + ,.idata_pd (rf_wr_cmd_pd[10:0]) //|< i + ,.odata_prdy (rf_wr_cmd_ordy) //|< w + ,.odata_pvld (rf_wr_cmd_ovld) //|> w + ,.odata_pd (rf_wr_cmd_opd[10:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////////////// +//////////////pop total row,total columun from rf_rd_cmd_fifo////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_cmd_ordy_hold <= 1'b1; + end else begin + if (rf_rd_cmd_ordy_hold & rf_rd_cmd_ovld) + rf_rd_cmd_ordy_hold <= 1'b0; + else if(rf_rd_grp_end & ~rf_rd_cmd_ovld) + rf_rd_cmd_ordy_hold <= 1'b1; + end +end +assign rf_rd_cmd_ordy = rf_rd_grp_end | rf_rd_cmd_ordy_hold; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_cmd_open <= 1'b0; + end else begin + if (rf_rd_cmd_ovld & rf_rd_cmd_ordy) + rf_rd_cmd_open <= 1'b1; + else if(rf_rd_grp_end) + rf_rd_cmd_open <= 1'b0; + end +end +//merge and split of read total column unit is element(1byte or 2byte), but contract unit is 32bytes +assign rd_total_pcol[6:0] = rf_rd_cmd_opd[5:0]+1; +assign rd_total_prow[6:0] = rf_rd_cmd_opd[11:6]+1; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_total_col_reg[6:0] <= {7{1'b0}}; + rd_total_row_reg[6:0] <= {7{1'b0}}; + end else begin + if (rf_rd_cmd_ovld & rf_rd_cmd_ordy) begin + rd_total_col_reg[6:0] <= rd_total_pcol[6:0]; + rd_total_row_reg[6:0] <= rd_total_prow[6:0]; + end + end +end +assign rd_total_col_tmp[6:0] = rd_total_col_reg[6:0]; +assign rd_total_row_tmp[6:0] = rd_total_row_reg[6:0]; +assign rd_grp_num[11:0] = |inwidth[2:0] ? inwidth[13:3]+1 : inwidth[13:3]; +assign rd_total_col[6:0] = m_contract ? rd_total_col_tmp : m_split ? (m_byte_data ? 2'h2 : rd_total_col_tmp > 8'h20 ? 4'h4 : 4'h2) : rd_total_row_tmp; +assign rd_total_row[6:0] = contract_lit_dx ? (rf_rd_gcnt_inc == rd_grp_num ? (|inwidth[2:0] ? inwidth[2:0] : 7'h8) : 7'h8) : (m_contract | m_split) ? rd_total_row_tmp : 1'b1; +//////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////generate rf read address /////////////////////////////////// +assign rf_rd_vld = rf_rd_rdy & rf_nempty & rf_rd_cmd_open; +assign rf_rd_done = rf_rd_row_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_addr <= {5{1'b0}}; + end else begin + if (rf_rd_row_end) begin + rf_rd_addr <= 5'h0; + end + else if(m_contract & rf_rd_col_end) begin + rf_rd_addr <= {rf_rd_rcnt_inc[2:0],2'b0}; + end + else if(m_split & ~m_byte_data & rf_rd_col_end) begin + rf_rd_addr <= {rf_rd_rcnt_inc[3:0],1'b0}; + end + else if(rf_rd_vld) begin + rf_rd_addr <= rf_rd_addr + 1'b1; + end + end +end +assign rf_rd_ccnt_inc[5:0] = rf_rd_ccnt + 1; +assign {mon_rd_tcol_c,rd_total_colm[5:0]} = rd_total_col[6:1] + rd_total_col[0]; +assign rf_rd_col_end = rf_rd_vld & (rf_rd_ccnt_inc >= rd_total_colm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_ccnt <= {5{1'b0}}; + {mon_rf_rd_ccnt,rf_rd_ccnt} <= {6{1'b0}}; + end else begin + if (rf_rd_col_end) begin + rf_rd_ccnt <= 5'h0; + end + else if(rf_rd_vld) begin + {mon_rf_rd_ccnt,rf_rd_ccnt} <= rf_rd_ccnt_inc; + end + end +end +assign rf_rd_rcnt_inc[6:0] = rf_rd_rcnt + 1; +assign rf_rd_row_end = rf_rd_col_end & (rf_rd_rcnt_inc == rd_total_row); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_rcnt <= {6{1'b0}}; + {mon_rf_rd_rcnt,rf_rd_rcnt} <= {7{1'b0}}; + end else begin + if (rf_rd_row_end) begin + rf_rd_rcnt <= 6'h0; + end + else if(rf_rd_col_end) begin + {mon_rf_rd_rcnt,rf_rd_rcnt} <= rf_rd_rcnt_inc; + end + end +end +assign rf_rd_gcnt_inc[11:0] = rf_rd_gcnt + 1; +assign rf_rd_grp_end = rf_rd_row_end & (rf_rd_gcnt_inc == (contract_lit_dx ? rd_grp_num : 1'b1)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rd_gcnt <= {11{1'b0}}; + {mon_rf_rd_gcnt,rf_rd_gcnt} <= {12{1'b0}}; + end else begin + if (rf_rd_grp_end) begin + rf_rd_gcnt <= 11'h0; + end + else if(rf_rd_row_end) begin + {mon_rf_rd_gcnt,rf_rd_gcnt} <= rf_rd_gcnt_inc; + end + end +end +/////////////generate the 64byte data mask////////// +//rf_rd_mask[5:0] : how many valid byte of atomic0 +//rf_rd_mask[11:6] : how many valid byte of atomic1 +assign {mon_remain_rd_row,remain_rd_row[6:0]} = rd_total_row_tmp - {rf_rd_ccnt,1'b0}; +assign {mon_remain_rd_col,remain_rd_col[6:0]} = rd_total_col_tmp - {rf_rd_ccnt,1'b0}; +assign rd_byte_num[7:0] = m_byte_data ? {1'b0,rd_total_col_tmp} : {rd_total_col_tmp,1'b0}; +assign {mon_remain_byte, remain_byte[7:0] } = rd_byte_num - {rf_rd_ccnt[1:0],6'h0}; +assign {mon_remain_byte1,remain_byte1[7:0]} = rd_byte_num - {rf_rd_ccnt[1:0],6'h0} - 8'h20; +assign split_rd_mask[11:0] = (remain_byte >= 8'h40) ? {6'h20,6'h20} : + (remain_byte >= 8'h20) ? {remain_byte1[5:0],6'h20} : {6'h0,remain_byte[5:0]}; +assign merge_byte_mask[5:0] = m_byte_data ? rd_total_col_tmp[5:0] : {rd_total_col_tmp[4:0],1'b0}; +assign merge_atom_mask[1:0] = remain_rd_row == 7'b1 ? 2'b01 : 2'b11; +assign merge_rd_mask[11:0] = ~merge_atom_mask[1] ? {6'h0,merge_byte_mask[5:0]} : {merge_byte_mask[5:0],merge_byte_mask[5:0]}; +assign contract_atom_mask[1:0] = remain_rd_col == 7'b1 ? 2'b01 : 2'b11; +assign contract_rd_mask[11:0] = ~contract_atom_mask[1] ? {6'h0,6'h20} : {6'h20,6'h20}; +assign rf_rd_mask[11:0] = m_contract ? contract_rd_mask : m_split ? split_rd_mask : merge_rd_mask; +NV_NVDLA_RUBIK_rf_rcmd rbk_rf_rd_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (rf_rd_cmd_rdy) //|> o + ,.idata_pvld (rf_rd_cmd_vld) //|< i + ,.idata_pd (rf_rd_cmd_pd[11:0]) //|< i + ,.odata_prdy (rf_rd_cmd_ordy) //|< w + ,.odata_pvld (rf_rd_cmd_ovld) //|> w + ,.odata_pd (rf_rd_cmd_opd[11:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +////////////////rf status//////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_wptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_wr_done) + rf_wptr[1:0] <= rf_wptr[1:0] + 1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rf_rptr[1:0] <= {2{1'b0}}; + end else begin + if (rf_rd_done) + rf_rptr[1:0] <= rf_rptr[1:0]+1; + end +end +assign rf_nempty = ~(rf_wptr[1:0]==rf_rptr[1:0]); +assign rf_full = (rf_wptr[1]^rf_rptr[1]) & (rf_wptr[0]==rf_rptr[0]); +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_rf_ctrl__rf_wr_cmd_pop_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_wr_row_end & ~rf_wr_cmd_ovld; + endproperty +// Cover 0 : "rf_wr_row_end & ~rf_wr_cmd_ovld" + FUNCPOINT_rubik_rf_ctrl__rf_wr_cmd_pop_block__0_COV : cover property (rubik_rf_ctrl__rf_wr_cmd_pop_block__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_wr_data_full__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((data_fifo_vld) && nvdla_core_rstn) |-> (rf_wr_rdy & rf_full); + endproperty +// Cover 1 : "rf_wr_rdy & rf_full" + FUNCPOINT_rubik_rf_ctrl__rf_wr_data_full__1_COV : cover property (rubik_rf_ctrl__rf_wr_data_full__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_rd_cmd_pop_block__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rf_rd_grp_end & ~rf_rd_cmd_ovld; + endproperty +// Cover 2 : "rf_rd_grp_end & ~rf_rd_cmd_ovld" + FUNCPOINT_rubik_rf_ctrl__rf_rd_cmd_pop_block__2_COV : cover property (rubik_rf_ctrl__rf_rd_cmd_pop_block__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_rd_data_after_cmd__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ~rf_rd_cmd_open & rf_rd_rdy & rf_nempty; + endproperty +// Cover 3 : "~rf_rd_cmd_open & rf_rd_rdy & rf_nempty" + FUNCPOINT_rubik_rf_ctrl__rf_rd_data_after_cmd__3_COV : cover property (rubik_rf_ctrl__rf_rd_data_after_cmd__3_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_rf_ctrl__rf_rd_data_empty__4_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((rf_rd_cmd_open) && nvdla_core_rstn) |-> (rf_rd_rdy & ~rf_nempty); + endproperty +// Cover 4 : "rf_rd_rdy & ~rf_nempty" + FUNCPOINT_rubik_rf_ctrl__rf_rd_data_empty__4_COV : cover property (rubik_rf_ctrl__rf_rd_data_empty__4_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_RUBIK_rf_ctrl diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v new file mode 100644 index 0000000..30e255b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v @@ -0,0 +1,547 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_rcmd.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_rf_rcmd ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +input [11:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [11:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] idata_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 3'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [1:0] idata_adr; // current write address +// spyglass disable_block W484 +// next idata_adr if wr_pushing=1 +wire [1:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] odata_adr; // read address this cycle +wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && idata_pvld; +wire [11:0] odata_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( idata_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( idata_adr ) + , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} ) + , .dout ( odata_pd_p ) + ); +wire [1:0] rd_adr_next_popping = odata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [2:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign odata_pvld_p = odata_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [11:0] odata_pd; // output data register +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + odata_pd <= odata_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + odata_pd <= {12{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_rcmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_rcmd_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_rf_rcmd_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_rf_rcmd_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_rf_rcmd") true +// synopsys dc_script_end +endmodule // NV_NVDLA_RUBIK_rf_rcmd +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [11:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [11:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [11:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [11:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [11:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [11:0] ram_ff0; +reg [11:0] ram_ff1; +reg [11:0] ram_ff2; +reg [11:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [11:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {12{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [11:0] Di0; +input [1:0] Ra0; +output [11:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 12'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [11:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [11:0] Q0 = mem[0]; +wire [11:0] Q1 = mem[1]; +wire [11:0] Q2 = mem[2]; +wire [11:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12] } +endmodule // vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +//vmw: Memory vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +//vmw: Address-size 2 +//vmw: Data-size 12 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[11:0] data0[11:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[11:0] data1[11:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v.vcp new file mode 100644 index 0000000..30e255b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v.vcp @@ -0,0 +1,547 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_rcmd.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_rf_rcmd ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +input [11:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [11:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] idata_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 3'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [1:0] idata_adr; // current write address +// spyglass disable_block W484 +// next idata_adr if wr_pushing=1 +wire [1:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] odata_adr; // read address this cycle +wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && idata_pvld; +wire [11:0] odata_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( idata_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( idata_adr ) + , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} ) + , .dout ( odata_pd_p ) + ); +wire [1:0] rd_adr_next_popping = odata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [2:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign odata_pvld_p = odata_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [11:0] odata_pd; // output data register +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + odata_pd <= odata_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + odata_pd <= {12{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_rcmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_rcmd_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_rf_rcmd_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_rf_rcmd_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_rf_rcmd") true +// synopsys dc_script_end +endmodule // NV_NVDLA_RUBIK_rf_rcmd +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [11:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [11:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [11:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [11:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [11:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [11:0] ram_ff0; +reg [11:0] ram_ff1; +reg [11:0] ram_ff2; +reg [11:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [11:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {12{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [11:0] Di0; +input [1:0] Ra0; +output [11:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 12'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [11:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [11:0] Q0 = mem[0]; +wire [11:0] Q1 = mem[1]; +wire [11:0] Q2 = mem[2]; +wire [11:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12] } +endmodule // vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +//vmw: Memory vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +//vmw: Address-size 2 +//vmw: Data-size 12 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[11:0] data0[11:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[11:0] data1[11:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v new file mode 100644 index 0000000..0e4742b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_wcmd.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_rf_wcmd ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +input [10:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [10:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg [10:0] idata_pd_in; // registered idata_pd +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge nvdla_core_clk ) begin + if ( !wr_busy_in && idata_pvld ) begin + idata_pd_in <= idata_pd; + end +//synopsys translate_off + else if ( !(!wr_busy_in && idata_pvld) ) begin + end else begin + idata_pd_in <= {11{`x_or_0}}; + end +//synopsys translate_on +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [8:0] idata_count; // write-side count +wire [8:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [8:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 ); +wire wr_count_next_is_256 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_256; +wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [8:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 9'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [7:0] idata_adr; // current write address +wire [7:0] odata_adr_p; // read address to use for ram +wire [10:0] odata_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_256x11 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( idata_adr ) + , .we ( wr_pushing ) + , .di ( idata_pd_in ) + , .ra ( odata_adr_p ) + , .re ( rd_enable ) + , .dout ( odata_pd_p ) + , .ore ( ore ) + ); +// next idata_adr if wr_pushing=1 +wire [7:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + idata_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] odata_adr; // current read address +// next read address +wire [7:0] rd_adr_next = odata_adr + 1'd1; // spyglass disable W484 +assign odata_adr_p = rd_popping ? rd_adr_next : odata_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [8:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [8:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [8:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [8:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~odata_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 9'd0; + odata_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + odata_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +assign odata_pd = odata_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_wcmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_wcmd_wr_limit : 9'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 9'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 9'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 9'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [8:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_rf_wcmd_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_rf_wcmd_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} ) + , .curr ( {23'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_rf_wcmd") true +// synopsys dc_script_end +endmodule // NV_NVDLA_RUBIK_rf_wcmd diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v.vcp new file mode 100644 index 0000000..0e4742b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v.vcp @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_rf_wcmd.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_rf_wcmd ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +input [10:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [10:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg [10:0] idata_pd_in; // registered idata_pd +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +always @( posedge nvdla_core_clk ) begin + if ( !wr_busy_in && idata_pvld ) begin + idata_pd_in <= idata_pd; + end +//synopsys translate_off + else if ( !(!wr_busy_in && idata_pvld) ) begin + end else begin + idata_pd_in <= {11{`x_or_0}}; + end +//synopsys translate_on +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [8:0] idata_count; // write-side count +wire [8:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [8:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [8:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_256 = ( wr_count_next_no_wr_popping == 9'd256 ); +wire wr_count_next_is_256 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_256; +wire [8:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [8:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_256 || // busy next cycle? + (wr_limit_reg != 9'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 9'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {9{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [7:0] idata_adr; // current write address +wire [7:0] odata_adr_p; // read address to use for ram +wire [10:0] odata_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_256x11 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( idata_adr ) + , .we ( wr_pushing ) + , .di ( idata_pd_in ) + , .ra ( odata_adr_p ) + , .re ( rd_enable ) + , .dout ( odata_pd_p ) + , .ore ( ore ) + ); +// next idata_adr if wr_pushing=1 +wire [7:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + idata_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] odata_adr; // current read address +// next read address +wire [7:0] rd_adr_next = odata_adr + 1'd1; // spyglass disable W484 +assign odata_adr_p = rd_popping ? rd_adr_next : odata_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [8:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [8:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [8:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [8:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~odata_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 9'd0; + odata_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {9{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + odata_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +assign odata_pd = odata_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_wcmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_rf_wcmd_wr_limit : 9'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 9'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 9'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 9'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [8:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 9'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_rf_wcmd_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_rf_wcmd_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {23'd0, (wr_limit_reg == 9'd0) ? 9'd256 : wr_limit_reg} ) + , .curr ( {23'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_rf_wcmd") true +// synopsys dc_script_end +endmodule // NV_NVDLA_RUBIK_rf_wcmd diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v new file mode 100644 index 0000000..ec0c1c4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v @@ -0,0 +1,1014 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_seq_gen.v +module NV_NVDLA_RUBIK_seq_gen ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_wr_cmd_rdy + ,dp2reg_consumer + ,dp2reg_done + ,rd_req_rdy + ,reg2dp_contract_stride_0 + ,reg2dp_contract_stride_1 + ,reg2dp_dain_addr_high + ,reg2dp_dain_addr_low + ,reg2dp_dain_line_stride + ,reg2dp_dain_planar_stride + ,reg2dp_dain_surf_stride + ,reg2dp_daout_addr_high + ,reg2dp_daout_addr_low + ,reg2dp_daout_line_stride + ,reg2dp_daout_planar_stride + ,reg2dp_daout_surf_stride + ,reg2dp_datain_channel + ,reg2dp_datain_height + ,reg2dp_datain_ram_type + ,reg2dp_datain_width + ,reg2dp_dataout_channel + ,reg2dp_deconv_x_stride + ,reg2dp_deconv_y_stride + ,reg2dp_in_precision + ,reg2dp_op_en + ,reg2dp_perf_en + ,reg2dp_rubik_mode + ,rf_rd_cmd_rdy + ,rf_wr_cmd_rdy + ,contract_lit_dx + ,dma_wr_cmd_pd + ,dma_wr_cmd_vld + ,dp2reg_d0_rd_stall_cnt + ,dp2reg_d1_rd_stall_cnt + ,inwidth + ,rd_req_pd + ,rd_req_type + ,rd_req_vld + ,rf_rd_cmd_pd + ,rf_rd_cmd_vld + ,rf_wr_cmd_pd + ,rf_wr_cmd_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_consumer; +input reg2dp_perf_en; +output [31:0] dp2reg_d0_rd_stall_cnt; +output [31:0] dp2reg_d1_rd_stall_cnt; +input reg2dp_op_en; +input reg2dp_datain_ram_type; +input [1:0] reg2dp_rubik_mode; +input [1:0] reg2dp_in_precision; +input [31:0] reg2dp_dain_addr_high; +input [26:0] reg2dp_dain_addr_low; +input [12:0] reg2dp_datain_channel; +input [12:0] reg2dp_datain_height; +input [12:0] reg2dp_datain_width; +input [4:0] reg2dp_deconv_x_stride; +input [4:0] reg2dp_deconv_y_stride; +input [26:0] reg2dp_dain_line_stride; +input [26:0] reg2dp_dain_planar_stride; +input [26:0] reg2dp_dain_surf_stride; +input [26:0] reg2dp_contract_stride_0; +input [26:0] reg2dp_contract_stride_1; +//data out register +input [31:0] reg2dp_daout_addr_high; +input [26:0] reg2dp_daout_addr_low; +input [26:0] reg2dp_daout_line_stride; +input [26:0] reg2dp_daout_planar_stride; +input [26:0] reg2dp_daout_surf_stride; +input [12:0] reg2dp_dataout_channel; +input dp2reg_done; +//output rd_req_done; +output rd_req_type; +output rd_req_vld; +input rd_req_rdy; +output [78:0] rd_req_pd; +output rf_wr_cmd_vld; +input rf_wr_cmd_rdy; +output [10:0] rf_wr_cmd_pd; +output rf_rd_cmd_vld; +input rf_rd_cmd_rdy; +output [11:0] rf_rd_cmd_pd; +output dma_wr_cmd_vld; +input dma_wr_cmd_rdy; +output [77:0] dma_wr_cmd_pd; +output contract_lit_dx; +output [13:0] inwidth; +reg [31:0] chn_stride; +reg [31:0] cubey_stride; +reg dma_wr_cmd_vld_tmp; +reg [31:0] dp2reg_d0_rd_stall_cnt; +reg [31:0] dp2reg_d1_rd_stall_cnt; +reg [17:0] inheight_mul_dy; +reg [26:0] intern_stride; +reg [13:0] inwidth_mul_dx; +reg mon_rd_addr_c; +reg mon_rd_cbase_c; +reg mon_rd_chn_cnt; +reg mon_rd_lbase_c; +reg mon_rd_wbase_c; +reg mon_rd_width_cnt; +reg mon_rd_ybase_c; +reg mon_wr_addr_c; +reg mon_wr_cbase_c; +reg mon_wr_chn_cnt; +reg mon_wr_dx_cnt; +reg mon_wr_lbase_c; +reg mon_wr_wbase_c; +reg mon_wr_width_cnt; +reg mon_wr_xbase_c; +reg [31:0] out_chn_stride; +reg [26:0] out_intern_stride; +reg [7:0] out_width_stridem; +reg [58:0] rd_addr; +reg [58:0] rd_chn_base; +reg [8:0] rd_chn_cnt; +reg [4:0] rd_dx_cnt; +reg [58:0] rd_dy_base; +reg [4:0] rd_dy_cnt; +reg [58:0] rd_line_base; +reg [12:0] rd_line_cnt; +reg rd_req_done_hold; +reg rd_req_tmp; +reg [31:0] rd_stall_cnt; +reg [58:0] rd_width_base; +reg [9:0] rd_width_cnt; +reg [1:0] reg2dp_in_precision_drv0; +reg [1:0] reg2dp_rubik_mode_drv0; +reg rubik_en; +reg rubik_en_d; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [2:0] width_stridem; +reg [58:0] wr_addr; +reg [58:0] wr_chn_base; +reg [8:0] wr_chn_cnt; +reg [58:0] wr_dx_base; +reg [1:0] wr_dx_cnt; +reg [58:0] wr_line_base; +reg [17:0] wr_line_cnt; +reg [4:0] wr_plar_cnt; +reg wr_req_done_hold; +reg [58:0] wr_width_base; +reg [9:0] wr_width_cnt; +wire [12:0] contract_rd_size; +wire [14:0] contract_rd_size_ext; +wire [12:0] contract_wr_size; +wire [26:0] cube_stride; +wire [58:0] dest_base; +wire [2:0] dx_stride_num; +wire [13:0] inchannel; +wire [12:0] inchannel_raw; +wire [13:0] inheight; +wire [12:0] inheight_raw; +wire init_set; +wire [12:0] inwidth_raw; +wire [10:0] inwidthm; +wire [4:0] kpg_dec; +wire [1:0] kpgm; +wire [26:0] line_stride; +wire m_byte_data; +wire m_contract; +wire m_merge; +wire m_split; +wire [12:0] merge_rd_size; +wire [14:0] merge_rd_size_ext; +wire [12:0] merge_wr_size; +wire [26:0] mon_block_stride; +wire mon_dx_stride_num_c; +wire mon_inwidthm_c; +wire mon_outchannelm_c; +wire mon_rd_chn_num_c; +wire mon_remain_rdc; +wire mon_remain_rdw; +wire mon_remain_rdx; +wire mon_remain_wrc; +wire mon_remain_wrw; +wire mon_remain_wrx; +wire [26:0] out_line_stride; +wire [26:0] out_planar_stride; +wire [26:0] out_surf_stride; +wire [26:0] out_width_stride; +wire [13:0] outchannel; +wire [9:0] outchannelm; +wire [26:0] planar_stride; +wire rd_channel_end; +wire [9:0] rd_chn_cnt_inc; +wire [13:0] rd_chn_num; +wire [9:0] rd_chn_numm; +wire [10:0] rd_cwdth_cnt_inc; +wire rd_cwdth_end; +wire rd_cx_beg; +wire rd_dx_end; +wire [4:0] rd_dx_num; +wire rd_dy_end; +wire rd_height_end; +wire [10:0] rd_mwdth_cnt_inc; +wire rd_mwdth_end; +wire [4:0] rd_planar_num; +wire rd_plar_end; +wire rd_px_beg; +wire rd_req_accept; +wire rd_req_done; +wire rd_stall_cnt_dec; +wire [5:0] rd_total_col; +wire [5:0] rd_total_row; +wire [12:0] remain_rd_channel; +wire [4:0] remain_rd_dx; +wire [12:0] remain_rd_width; +wire [12:0] remain_wr_channel; +wire [4:0] remain_wr_dx; +wire [12:0] remain_wr_width; +wire [12:0] split_rd_size; +wire [14:0] split_rd_size_ext; +wire [12:0] split_wr_size; +wire [58:0] src_base; +wire [26:0] surf_stride; +wire [26:0] width_stride; +wire wr_channel_end; +wire wr_cheight_end; +wire [9:0] wr_chn_cnt_inc; +wire [10:0] wr_cwdth_cnt_inc; +wire wr_cwdth_end; +wire [2:0] wr_dx_cnt_inc; +wire wr_dx_end; +wire [4:0] wr_dx_num; +wire wr_height_end; +wire wr_hx_beg; +wire wr_hx_end; +wire wr_mheight_end; +wire [10:0] wr_mwdth_cnt_inc; +wire wr_mwdth_end; +wire [4:0] wr_planar_num; +wire wr_plar_beg; +wire wr_plar_end; +wire wr_req_accept; +wire wr_req_done; +wire [5:0] wr_total_col; +wire [4:0] wr_total_row; +wire wr_width_end; +wire [4:0] wr_width_num; +wire [4:0] x_stride; +wire [5:0] x_stride_add; +wire [4:0] y_stride; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +///////////////////////////////Configuration/////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_rubik_mode_drv0[1:0] <= {2{1'b0}}; + end else begin + reg2dp_rubik_mode_drv0[1:0] <= reg2dp_rubik_mode[1:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_in_precision_drv0[1:0] <= {2{1'b0}}; + end else begin + reg2dp_in_precision_drv0[1:0] <= reg2dp_in_precision[1:0]; + end +end +assign m_contract = reg2dp_rubik_mode_drv0[1:0] == 2'h0 ; +assign m_split = reg2dp_rubik_mode_drv0[1:0] == 2'h1 ; +assign m_merge = reg2dp_rubik_mode_drv0[1:0] == 2'h2 ; +assign m_byte_data = reg2dp_in_precision_drv0[1:0] == 2'h0 ; +assign src_base = {reg2dp_dain_addr_high,reg2dp_dain_addr_low}; +assign dest_base = {reg2dp_daout_addr_high,reg2dp_daout_addr_low}; +assign inwidth_raw[12:0] = reg2dp_datain_width[12:0] ; +assign inheight_raw[12:0] = reg2dp_datain_height[12:0] ; +assign inchannel_raw[12:0] = reg2dp_datain_channel[12:0] ; +assign inwidth[13:0] = reg2dp_datain_width[12:0] +1; +assign inheight[13:0] = reg2dp_datain_height[12:0] +1; +assign inchannel[13:0] = reg2dp_datain_channel[12:0] +1; +assign outchannel[13:0] = reg2dp_dataout_channel[12:0]+1; +assign mon_block_stride[26:0] = reg2dp_contract_stride_1[26:0]; +assign planar_stride[26:0]= reg2dp_dain_planar_stride[26:0]; +assign line_stride[26:0] = reg2dp_dain_line_stride[26:0]; +assign surf_stride[26:0] = reg2dp_dain_surf_stride[26:0]; +assign cube_stride[26:0] = reg2dp_contract_stride_0[26:0]; +assign x_stride[4:0] = reg2dp_deconv_x_stride[4:0]; +assign y_stride[4:0] = reg2dp_deconv_y_stride[4:0]; +assign x_stride_add[5:0] = reg2dp_deconv_x_stride[4:0]+1; +assign out_planar_stride[26:0] = reg2dp_daout_planar_stride[26:0]; +assign out_line_stride[26:0] = reg2dp_daout_line_stride[26:0]; +assign out_surf_stride[26:0] = reg2dp_daout_surf_stride[26:0]; +assign kpgm[1:0] = m_byte_data+1; +assign kpg_dec[4:0] = {m_byte_data,4'hf}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intern_stride[26:0] <= {27{1'b0}}; + end else begin + intern_stride[26:0] <= m_contract ? cube_stride : m_merge ? planar_stride : 8'h40; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_stridem[2:0] <= {3{1'b0}}; + end else begin + width_stridem[2:0] <= m_merge ? m_byte_data ? 3'h1 : 3'h2 : 3'h4; + end +end +assign width_stride[26:0] = {23'h0,width_stridem,1'b0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cubey_stride[31:0] <= {32{1'b0}}; + end else begin + cubey_stride[31:0] <= cube_stride * (x_stride+1); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + chn_stride[31:0] <= {32{1'b0}}; + end else begin + chn_stride[31:0] <= (m_split | m_contract ) ? {5'h0,surf_stride} : m_byte_data ? {planar_stride,5'h0} : {1'b0,planar_stride,4'h0}; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(m_split | m_contract ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_intern_stride[26:0] <= {27{1'b0}}; + end else begin + out_intern_stride[26:0] <= m_contract ? |x_stride[4:3] ? x_stride_add : out_line_stride : m_split ? out_planar_stride : 8'h40; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_width_stridem[7:0] <= {8{1'b0}}; + end else begin + out_width_stridem[7:0] <= m_contract ? {x_stride_add,2'h0} : (m_byte_data ? 2'h1 : 2'h2); + end +end +assign out_width_stride[26:0] = {18'h0,out_width_stridem,1'b0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_chn_stride[31:0] <= {32{1'b0}}; + end else begin + out_chn_stride[31:0] <= (m_merge | m_contract ) ? {5'h0,out_surf_stride} : m_byte_data ? {out_planar_stride,5'h0} : {1'b0,out_planar_stride,4'h0}; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(m_merge | m_contract ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + inwidth_mul_dx[13:0] <= {14{1'b0}}; + end else begin + inwidth_mul_dx[13:0] <= inwidth * (x_stride+1) -1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + inheight_mul_dy[17:0] <= {18{1'b0}}; + end else begin + inheight_mul_dy[17:0] <= inheight * (y_stride+1) -1; + end +end +/////////////////////rubik en//////////////////////// +//rubik enable +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rubik_en <= 1'b0; + end else begin + if (dp2reg_done) + rubik_en <= 1'b0; + else if (reg2dp_op_en) + rubik_en <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rubik_en_d <= 1'b0; + end else begin + rubik_en_d <= rubik_en; + end +end +assign init_set = rubik_en & ~rubik_en_d; +///////////////////////////////////////////////////////////////////////////// +/////////////////////////generate read dma sequence////////////////////////// +//read request valid +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_req_tmp <= 1'b0; + end else begin + if (rd_req_done | rd_req_done_hold | dp2reg_done) + rd_req_tmp <= 1'b0; + else if (rubik_en) + rd_req_tmp <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_req_done_hold <= 1'b0; + end else begin + if (dp2reg_done) + rd_req_done_hold <= 1'b0; + else if (rd_req_done) + rd_req_done_hold <= 1'b1; + end +end +assign rd_req_done = rd_channel_end; +assign rd_req_type = reg2dp_datain_ram_type; +assign rd_req_vld = rd_req_tmp & rf_wr_cmd_rdy; +assign rd_req_pd[63:0] = {rd_addr,5'h0}; +assign contract_rd_size_ext = {{2{1'b0}}, contract_rd_size}; +assign split_rd_size_ext = {{2{1'b0}}, split_rd_size}; +assign merge_rd_size_ext = {{2{1'b0}}, merge_rd_size}; +assign rd_req_pd[78:64] = m_contract ? contract_rd_size_ext : m_split ? split_rd_size_ext : merge_rd_size_ext ; //rd size 32bytes units and decrease 1 +assign rd_req_accept = rd_req_vld & rd_req_rdy; +//request burst size +assign {mon_remain_rdw,remain_rd_width[12:0]} = inwidth_raw - {rd_width_cnt,3'h0}; +assign {mon_remain_rdc,remain_rd_channel[12:0]} = inchannel_raw -{rd_chn_cnt,4'h0}; +assign {mon_remain_rdx,remain_rd_dx[4:0]} = x_stride - rd_dx_cnt; +assign contract_rd_size[12:0] = remain_rd_width >= 8'h7 ? 6'h7 : remain_rd_width; +assign split_rd_size[12:0] = remain_rd_width >= 8'h3f ? 6'h3f : remain_rd_width; +assign merge_rd_size[12:0] = m_byte_data ? (remain_rd_width >= 8'h20 ? 1'b1 : 1'b0) : + (remain_rd_width >= 8'h30 ? 4'h3 : remain_rd_width >= 8'h20 ? 4'h2 : + remain_rd_width >= 8'h10 ? 4'h1 : 4'h0); +assign rd_dx_num[4:0] = remain_rd_dx >= 5'h7 ? 5'h7 : remain_rd_dx; +assign rd_planar_num[4:0] = remain_rd_channel >= {8'h0,kpg_dec} ? kpg_dec : remain_rd_channel[4:0]; +//caculate ping pong array total row number & total column number +assign wr_total_col[5:0] = m_contract ? contract_rd_size[5:0] : m_split ? split_rd_size[5:0] : merge_rd_size[5:0] ; +assign wr_total_row[4:0] = m_contract ? (|x_stride[4:3] ? rd_dx_num : x_stride) : m_merge ? rd_planar_num[4:0] : 1'b0; +assign rf_wr_cmd_vld = rd_px_beg | rd_cx_beg | m_split & rd_req_accept; +assign rf_wr_cmd_pd = {wr_total_row,wr_total_col}; +/* +&Always posedge; + if(rd_px_beg | rd_cx_beg | m_split & rd_req_accept) begin + rf_wr_cmd_vld <0=1'b1; + rf_wr_cmd_pd <0= {wr_total_row,wr_total_col}; + end + else if (rf_wr_cmd_vld & rf_wr_cmd_rdy) + rf_wr_cmd_vld <0=1'b0; +&End; +*/ +///////generate read sequence address///////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_addr <= {59{1'b0}}; + {mon_rd_addr_c,rd_addr} <= {60{1'b0}}; + end else begin + if(init_set) + rd_addr <= src_base; + else if(rd_height_end) + {mon_rd_addr_c,rd_addr} <= rd_chn_base + chn_stride ; + else if(rd_dy_end | rd_mwdth_end) + {mon_rd_addr_c,rd_addr} <= rd_line_base + line_stride ; + else if(rd_cwdth_end) + {mon_rd_addr_c,rd_addr} <= rd_dy_base + cubey_stride ; + else if(rd_dx_end | rd_plar_end) + {mon_rd_addr_c,rd_addr} <= rd_width_base + width_stride ; + else if(rd_req_accept) + {mon_rd_addr_c,rd_addr} <= rd_addr + intern_stride ; + end +end +//record the pointer base address +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_width_base <= {59{1'b0}}; + {mon_rd_wbase_c,rd_width_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_width_base <= src_base; + else if(rd_height_end) + {mon_rd_wbase_c,rd_width_base} <= rd_chn_base + chn_stride ; + else if(rd_dy_end | rd_mwdth_end) + {mon_rd_wbase_c,rd_width_base} <= rd_line_base + line_stride ; + else if(rd_cwdth_end) + {mon_rd_wbase_c,rd_width_base} <= rd_dy_base + cubey_stride ; + else if(rd_dx_end | rd_plar_end) + {mon_rd_wbase_c,rd_width_base} <= rd_width_base + width_stride ; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_dy_base <= {59{1'b0}}; + {mon_rd_ybase_c,rd_dy_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_dy_base <= src_base; + else if(rd_height_end) + {mon_rd_ybase_c,rd_dy_base} <= rd_chn_base + chn_stride ; + else if(rd_dy_end) + {mon_rd_ybase_c,rd_dy_base} <= rd_line_base + line_stride ; + else if(rd_cwdth_end) + {mon_rd_ybase_c,rd_dy_base} <= rd_dy_base + cubey_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_line_base <= {59{1'b0}}; + {mon_rd_lbase_c,rd_line_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_line_base <= src_base; + else if (rd_height_end) + {mon_rd_lbase_c,rd_line_base} <= rd_chn_base + chn_stride; + else if(rd_dy_end | rd_mwdth_end) + {mon_rd_lbase_c,rd_line_base} <= rd_line_base + line_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_chn_base <= {59{1'b0}}; + {mon_rd_cbase_c,rd_chn_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_chn_base <= src_base; + else if(rd_height_end) + {mon_rd_cbase_c,rd_chn_base} <= rd_chn_base + chn_stride; + end +end +///////////for circle counter///////////// +//deconv x counter +assign rd_px_beg = m_merge & rd_req_accept & (rd_dx_cnt == 5'h0); +assign rd_cx_beg = m_contract & rd_req_accept & (rd_dx_cnt[2:0] == 3'h0); +assign rd_dx_end = m_contract & rd_req_accept & (rd_dx_cnt == x_stride); +assign rd_plar_end = m_merge & rd_req_accept & (rd_dx_cnt == rd_planar_num); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_dx_cnt <= {5{1'b0}}; + end else begin + if (!rubik_en | rd_dx_end | rd_plar_end) begin + rd_dx_cnt <= 0; + end + else if ((m_contract | m_merge) & rd_req_accept) begin + rd_dx_cnt <= rd_dx_cnt + 1; + end + end +end +//read width counter +assign rd_cwdth_cnt_inc[10:0] = rd_width_cnt + 1'b1; +assign rd_mwdth_cnt_inc[10:0] = rd_width_cnt + 4'h8; +assign {mon_inwidthm_c,inwidthm[10:0]} = inwidth[13:3]+|inwidth[2:0]; +assign rd_cwdth_end = rd_dx_end & (rd_cwdth_cnt_inc >= inwidthm); +assign rd_mwdth_end = (rd_plar_end | m_split & rd_req_accept) & (rd_mwdth_cnt_inc >= inwidthm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_width_cnt <= {10{1'b0}}; + {mon_rd_width_cnt,rd_width_cnt} <= {11{1'b0}}; + end else begin + if (!rubik_en | rd_cwdth_end |rd_mwdth_end) begin + rd_width_cnt <= 0; + end + else if(rd_dx_end) begin + {mon_rd_width_cnt,rd_width_cnt} <= rd_cwdth_cnt_inc; + end + else if(rd_plar_end | m_split & rd_req_accept) begin + {mon_rd_width_cnt,rd_width_cnt} <= rd_mwdth_cnt_inc; + end + end +end +//read deconv y counter +assign rd_dy_end = rd_cwdth_end & (rd_dy_cnt == y_stride); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_dy_cnt <= {5{1'b0}}; + end else begin + if (!rubik_en | rd_dy_end) begin + rd_dy_cnt <= 0; + end + else if (rd_cwdth_end) begin + rd_dy_cnt <= rd_dy_cnt + 1; + end + end +end +//read height counter +assign rd_height_end = (rd_dy_end | rd_mwdth_end) & (rd_line_cnt == inheight_raw); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_line_cnt <= {13{1'b0}}; + end else begin + if (!rubik_en | rd_height_end) begin + rd_line_cnt <= 0; + end + else if(rd_dy_end | rd_mwdth_end) begin + rd_line_cnt <= rd_line_cnt + 1; + end + end +end +//read outchannel counter +assign rd_chn_cnt_inc[9:0] = rd_chn_cnt + kpgm; +assign rd_chn_num[13:0] = m_contract ? outchannel : inchannel; +assign {mon_rd_chn_num_c,rd_chn_numm[9:0]} = rd_chn_num[13:4]+|rd_chn_num[3:0]; +assign rd_channel_end = rd_height_end & (rd_chn_cnt_inc >= rd_chn_numm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_chn_cnt <= {9{1'b0}}; + {mon_rd_chn_cnt,rd_chn_cnt} <= {10{1'b0}}; + end else begin + if (!rubik_en | rd_channel_end) begin + rd_chn_cnt <= 0; + end + else if(rd_height_end) begin + {mon_rd_chn_cnt,rd_chn_cnt} <= rd_chn_cnt_inc; + end + end +end +//////////////////////////////////////////////////////////////////////////////////// +///////////////////////////generate write dma sequence////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_wr_cmd_vld_tmp <= 1'b0; + end else begin + if (wr_req_done | wr_req_done_hold | dp2reg_done) + dma_wr_cmd_vld_tmp <= 1'b0; + else if (rubik_en) + dma_wr_cmd_vld_tmp <= 1'b1; + end +end +assign dma_wr_cmd_vld = dma_wr_cmd_vld_tmp & rf_rd_cmd_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_req_done_hold <= 1'b0; + end else begin + if (dp2reg_done) + wr_req_done_hold <= 1'b0; + else if (wr_req_done) + wr_req_done_hold <= 1'b1; + end +end +assign wr_req_done = wr_channel_end; +assign dma_wr_cmd_pd[77:77] = wr_req_done; +assign dma_wr_cmd_pd[76:64] = m_contract ? contract_wr_size : m_merge ? merge_wr_size : split_wr_size; +assign dma_wr_cmd_pd[63:0] = {wr_addr,5'b0}; +assign wr_req_accept = dma_wr_cmd_vld & dma_wr_cmd_rdy; +//request burst size +assign {mon_remain_wrw,remain_wr_width[12:0]} = inwidth_raw - {wr_width_cnt,3'h0}; +assign {mon_remain_wrc,remain_wr_channel[12:0]} = inchannel_raw -{wr_chn_cnt,4'h0}; +assign {mon_remain_wrx,remain_wr_dx[4:0]} = x_stride - {wr_dx_cnt,3'h0}; +assign contract_wr_size[12:0] = |x_stride[4:3] ? {8'h0,wr_dx_num[4:0]} : inwidth_mul_dx[12:0]; +assign merge_wr_size[12:0] = remain_wr_width >= 6'h3f ? 6'h3f : remain_wr_width; +assign split_wr_size[12:0] = m_byte_data ? (remain_wr_width >= 6'h20 ? 1'b1 : 1'b0) : + (remain_wr_width >= 6'h30 ? 4'h3 : remain_wr_width >= 6'h20 ? 4'h2 : + remain_wr_width >= 6'h10 ? 4'h1 : 4'h0); +assign wr_dx_num[4:0] = remain_wr_dx >= 4'h7 ? 4'h7 : remain_wr_dx ; +assign wr_width_num[4:0] = remain_wr_width >= 4'h7 ? 4'h7 : remain_wr_width[4:0]; +assign wr_planar_num[4:0] = remain_wr_channel >= {8'h0,kpg_dec} ? kpg_dec : remain_wr_channel[4:0]; +//merge and split of read total column unit is element(1byte or 2byte), but contract unit is 32bytes +assign rd_total_col[5:0] = m_contract ? (|x_stride[4:3] ? {1'b0,wr_dx_num} : {1'b0,x_stride}) : m_merge ? {1'b0,wr_planar_num[4:0]} : merge_wr_size[5:0]; +assign rd_total_row[5:0] = m_contract ? (|x_stride[4:3] ? {1'b0,wr_width_num[4:0]} : 1'b0) : m_merge ? merge_wr_size[5:0] : {1'b0,wr_planar_num[4:0]}; +assign contract_lit_dx = m_contract & ~(|x_stride[4:3]); +assign rf_rd_cmd_vld = wr_plar_beg | wr_hx_beg | (m_contract & ~(|x_stride[4:3]) | m_merge) & wr_req_accept; +assign rf_rd_cmd_pd = {rd_total_row,rd_total_col}; +/* +&Always posedge; + if (wr_plar_beg | wr_hx_beg | (m_contract & ~(|x_stride[4:3]) | m_merge) & wr_req_accept) begin + rf_rd_cmd_vld <0=1'b1; + rf_rd_cmd_pd <0= {rd_total_row,rd_total_col}; + end + else if (rf_rd_cmd_vld & rf_rd_cmd_rdy) + rf_rd_cmd_vld <0=1'b0; +&End; +*/ +///////generate write sequence address///////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_addr <= {59{1'b0}}; + {mon_wr_addr_c,wr_addr} <= {60{1'b0}}; + end else begin + if(init_set) + wr_addr <= dest_base; + else if(wr_height_end) + {mon_wr_addr_c,wr_addr} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_addr_c,wr_addr} <= wr_line_base + out_line_stride ; + else if(wr_dx_end | wr_plar_end) + {mon_wr_addr_c,wr_addr} <= wr_width_base + out_width_stride ; + else if(wr_hx_end) + {mon_wr_addr_c,wr_addr} <= wr_dx_base + 4'h8; + else if(wr_req_accept) + {mon_wr_addr_c,wr_addr} <= wr_addr + out_intern_stride ; + end +end +//record the pointer base address +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_dx_base <= {59{1'b0}}; + {mon_wr_xbase_c,wr_dx_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_dx_base <= dest_base; + else if(wr_height_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_line_base + out_line_stride ; + else if(wr_dx_end | wr_plar_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_width_base + out_width_stride ; + else if(wr_hx_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_dx_base + 4'h8; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_width_base <= {59{1'b0}}; + {mon_wr_wbase_c,wr_width_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_width_base <= dest_base; + else if(wr_height_end) + {mon_wr_wbase_c,wr_width_base} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_wbase_c,wr_width_base} <= wr_line_base + out_line_stride ; + else if(wr_dx_end | wr_plar_end) + {mon_wr_wbase_c,wr_width_base} <= wr_width_base + out_width_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_base <= {59{1'b0}}; + {mon_wr_lbase_c,wr_line_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_line_base <= dest_base; + else if(wr_height_end) + {mon_wr_lbase_c,wr_line_base} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_lbase_c,wr_line_base} <= wr_line_base + out_line_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_chn_base <= {59{1'b0}}; + {mon_wr_cbase_c,wr_chn_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_chn_base <= dest_base; + else if(wr_height_end) + {mon_wr_cbase_c,wr_chn_base} <= wr_chn_base + out_chn_stride; + end +end +///////////for circle counter///////////// +//internal counter +assign wr_hx_beg = m_contract & (|x_stride[4:3]) & wr_req_accept & (wr_plar_cnt == 0); +assign wr_hx_end = m_contract & (|x_stride[4:3]) & wr_req_accept & (wr_plar_cnt == wr_width_num); +assign wr_plar_beg = m_split & wr_req_accept & (wr_plar_cnt == 0); +assign wr_plar_end = m_split & wr_req_accept & (wr_plar_cnt == wr_planar_num); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_plar_cnt <= {5{1'b0}}; + end else begin + if (!rubik_en | wr_hx_end | wr_plar_end) begin + wr_plar_cnt <= 0; + end + else if ((m_contract & (|x_stride[4:3]) | m_split) & wr_req_accept) begin + wr_plar_cnt <= wr_plar_cnt + 1; + end + end +end +//deconv x counter +assign wr_dx_cnt_inc[2:0] = wr_dx_cnt + 1'b1; +assign {mon_dx_stride_num_c,dx_stride_num[2:0]} = x_stride_add[5:3]+|x_stride_add[2:0]; +assign wr_dx_end = wr_hx_end & (wr_dx_cnt_inc >= dx_stride_num); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_dx_cnt <= {2{1'b0}}; + {mon_wr_dx_cnt,wr_dx_cnt} <= {3{1'b0}}; + end else begin + if (!rubik_en | wr_dx_end) begin + wr_dx_cnt <= 0; + end + else if (wr_hx_end) begin + {mon_wr_dx_cnt,wr_dx_cnt} <= wr_dx_cnt_inc; + end + end +end +//write width counter +assign wr_cwdth_cnt_inc[10:0] = wr_width_cnt + 1'b1; +assign wr_mwdth_cnt_inc[10:0] = wr_width_cnt + 4'h8; +assign wr_cwdth_end = wr_dx_end & (wr_cwdth_cnt_inc >= inwidthm[10:0]); +assign wr_mwdth_end =(wr_plar_end | m_merge & wr_req_accept) & (wr_mwdth_cnt_inc >= inwidthm[10:0]); +assign wr_width_end = wr_cwdth_end | wr_mwdth_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_width_cnt <= {10{1'b0}}; + {mon_wr_width_cnt,wr_width_cnt} <= {11{1'b0}}; + end else begin + if (!rubik_en | wr_width_end) begin + wr_width_cnt <= 0; + end + else if(wr_dx_end) begin + {mon_wr_width_cnt,wr_width_cnt} <= wr_cwdth_cnt_inc; + end + else if(wr_plar_end | m_merge & wr_req_accept) begin + {mon_wr_width_cnt,wr_width_cnt} <= wr_mwdth_cnt_inc; + end + end +end +//write height counter +assign wr_cheight_end = (wr_cwdth_end | m_contract & ~(|x_stride[4:3]) & wr_req_accept) & (wr_line_cnt == inheight_mul_dy); +assign wr_mheight_end = wr_mwdth_end & (wr_line_cnt == {5'h0,inheight_raw}); +assign wr_height_end = wr_cheight_end | wr_mheight_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_cnt <= {18{1'b0}}; + end else begin + if (!rubik_en | wr_height_end) begin + wr_line_cnt <= 0; + end + else if(wr_width_end | m_contract & ~(|x_stride[4:3]) & wr_req_accept) begin + wr_line_cnt <= wr_line_cnt + 1; + end + end +end +//write channel counter +assign wr_chn_cnt_inc[9:0] = wr_chn_cnt + kpgm; +assign {mon_outchannelm_c,outchannelm[9:0]} = outchannel[13:4]+|outchannel[3:0]; +assign wr_channel_end = wr_height_end & (wr_chn_cnt_inc >= outchannelm[9:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_chn_cnt <= {9{1'b0}}; + {mon_wr_chn_cnt,wr_chn_cnt} <= {10{1'b0}}; + end else begin + if (!rubik_en | wr_channel_end) begin + wr_chn_cnt <= 0; + end + else if(wr_height_end) begin + {mon_wr_chn_cnt,wr_chn_cnt} <= wr_chn_cnt_inc; + end + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_seq_gen__read_request_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rd_req_vld & !rd_req_rdy; + endproperty +// Cover 0 : "rd_req_vld & !rd_req_rdy" + FUNCPOINT_rubik_seq_gen__read_request_block__0_COV : cover property (rubik_seq_gen__read_request_block__0_cov); + `endif +`endif +//VCS coverage on + assign rd_stall_cnt_dec = 1'b0; +// stl adv logic + always @( + rd_req_vld + or rd_stall_cnt_dec + ) begin + stl_adv = rd_req_vld ^ rd_stall_cnt_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or rd_req_vld + or rd_stall_cnt_dec + or stl_adv + or rd_req_done + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (rd_req_vld && !rd_stall_cnt_dec)? stl_cnt_inc : (!rd_req_vld && rd_stall_cnt_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (rd_req_done)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_en) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + rd_stall_cnt[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_rd_stall_cnt <= {32{1'b0}}; + end else begin + if (rd_req_done & ~dp2reg_consumer) + dp2reg_d0_rd_stall_cnt <= rd_stall_cnt; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_rd_stall_cnt <= {32{1'b0}}; + end else begin + if (rd_req_done & dp2reg_consumer) + dp2reg_d1_rd_stall_cnt <= rd_stall_cnt; + end +end +endmodule // NV_NVDLA_RUBIK_seq_gen diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v.vcp new file mode 100644 index 0000000..ec0c1c4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v.vcp @@ -0,0 +1,1014 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_seq_gen.v +module NV_NVDLA_RUBIK_seq_gen ( + nvdla_core_clk + ,nvdla_core_rstn + ,dma_wr_cmd_rdy + ,dp2reg_consumer + ,dp2reg_done + ,rd_req_rdy + ,reg2dp_contract_stride_0 + ,reg2dp_contract_stride_1 + ,reg2dp_dain_addr_high + ,reg2dp_dain_addr_low + ,reg2dp_dain_line_stride + ,reg2dp_dain_planar_stride + ,reg2dp_dain_surf_stride + ,reg2dp_daout_addr_high + ,reg2dp_daout_addr_low + ,reg2dp_daout_line_stride + ,reg2dp_daout_planar_stride + ,reg2dp_daout_surf_stride + ,reg2dp_datain_channel + ,reg2dp_datain_height + ,reg2dp_datain_ram_type + ,reg2dp_datain_width + ,reg2dp_dataout_channel + ,reg2dp_deconv_x_stride + ,reg2dp_deconv_y_stride + ,reg2dp_in_precision + ,reg2dp_op_en + ,reg2dp_perf_en + ,reg2dp_rubik_mode + ,rf_rd_cmd_rdy + ,rf_wr_cmd_rdy + ,contract_lit_dx + ,dma_wr_cmd_pd + ,dma_wr_cmd_vld + ,dp2reg_d0_rd_stall_cnt + ,dp2reg_d1_rd_stall_cnt + ,inwidth + ,rd_req_pd + ,rd_req_type + ,rd_req_vld + ,rf_rd_cmd_pd + ,rf_rd_cmd_vld + ,rf_wr_cmd_pd + ,rf_wr_cmd_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_consumer; +input reg2dp_perf_en; +output [31:0] dp2reg_d0_rd_stall_cnt; +output [31:0] dp2reg_d1_rd_stall_cnt; +input reg2dp_op_en; +input reg2dp_datain_ram_type; +input [1:0] reg2dp_rubik_mode; +input [1:0] reg2dp_in_precision; +input [31:0] reg2dp_dain_addr_high; +input [26:0] reg2dp_dain_addr_low; +input [12:0] reg2dp_datain_channel; +input [12:0] reg2dp_datain_height; +input [12:0] reg2dp_datain_width; +input [4:0] reg2dp_deconv_x_stride; +input [4:0] reg2dp_deconv_y_stride; +input [26:0] reg2dp_dain_line_stride; +input [26:0] reg2dp_dain_planar_stride; +input [26:0] reg2dp_dain_surf_stride; +input [26:0] reg2dp_contract_stride_0; +input [26:0] reg2dp_contract_stride_1; +//data out register +input [31:0] reg2dp_daout_addr_high; +input [26:0] reg2dp_daout_addr_low; +input [26:0] reg2dp_daout_line_stride; +input [26:0] reg2dp_daout_planar_stride; +input [26:0] reg2dp_daout_surf_stride; +input [12:0] reg2dp_dataout_channel; +input dp2reg_done; +//output rd_req_done; +output rd_req_type; +output rd_req_vld; +input rd_req_rdy; +output [78:0] rd_req_pd; +output rf_wr_cmd_vld; +input rf_wr_cmd_rdy; +output [10:0] rf_wr_cmd_pd; +output rf_rd_cmd_vld; +input rf_rd_cmd_rdy; +output [11:0] rf_rd_cmd_pd; +output dma_wr_cmd_vld; +input dma_wr_cmd_rdy; +output [77:0] dma_wr_cmd_pd; +output contract_lit_dx; +output [13:0] inwidth; +reg [31:0] chn_stride; +reg [31:0] cubey_stride; +reg dma_wr_cmd_vld_tmp; +reg [31:0] dp2reg_d0_rd_stall_cnt; +reg [31:0] dp2reg_d1_rd_stall_cnt; +reg [17:0] inheight_mul_dy; +reg [26:0] intern_stride; +reg [13:0] inwidth_mul_dx; +reg mon_rd_addr_c; +reg mon_rd_cbase_c; +reg mon_rd_chn_cnt; +reg mon_rd_lbase_c; +reg mon_rd_wbase_c; +reg mon_rd_width_cnt; +reg mon_rd_ybase_c; +reg mon_wr_addr_c; +reg mon_wr_cbase_c; +reg mon_wr_chn_cnt; +reg mon_wr_dx_cnt; +reg mon_wr_lbase_c; +reg mon_wr_wbase_c; +reg mon_wr_width_cnt; +reg mon_wr_xbase_c; +reg [31:0] out_chn_stride; +reg [26:0] out_intern_stride; +reg [7:0] out_width_stridem; +reg [58:0] rd_addr; +reg [58:0] rd_chn_base; +reg [8:0] rd_chn_cnt; +reg [4:0] rd_dx_cnt; +reg [58:0] rd_dy_base; +reg [4:0] rd_dy_cnt; +reg [58:0] rd_line_base; +reg [12:0] rd_line_cnt; +reg rd_req_done_hold; +reg rd_req_tmp; +reg [31:0] rd_stall_cnt; +reg [58:0] rd_width_base; +reg [9:0] rd_width_cnt; +reg [1:0] reg2dp_in_precision_drv0; +reg [1:0] reg2dp_rubik_mode_drv0; +reg rubik_en; +reg rubik_en_d; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [2:0] width_stridem; +reg [58:0] wr_addr; +reg [58:0] wr_chn_base; +reg [8:0] wr_chn_cnt; +reg [58:0] wr_dx_base; +reg [1:0] wr_dx_cnt; +reg [58:0] wr_line_base; +reg [17:0] wr_line_cnt; +reg [4:0] wr_plar_cnt; +reg wr_req_done_hold; +reg [58:0] wr_width_base; +reg [9:0] wr_width_cnt; +wire [12:0] contract_rd_size; +wire [14:0] contract_rd_size_ext; +wire [12:0] contract_wr_size; +wire [26:0] cube_stride; +wire [58:0] dest_base; +wire [2:0] dx_stride_num; +wire [13:0] inchannel; +wire [12:0] inchannel_raw; +wire [13:0] inheight; +wire [12:0] inheight_raw; +wire init_set; +wire [12:0] inwidth_raw; +wire [10:0] inwidthm; +wire [4:0] kpg_dec; +wire [1:0] kpgm; +wire [26:0] line_stride; +wire m_byte_data; +wire m_contract; +wire m_merge; +wire m_split; +wire [12:0] merge_rd_size; +wire [14:0] merge_rd_size_ext; +wire [12:0] merge_wr_size; +wire [26:0] mon_block_stride; +wire mon_dx_stride_num_c; +wire mon_inwidthm_c; +wire mon_outchannelm_c; +wire mon_rd_chn_num_c; +wire mon_remain_rdc; +wire mon_remain_rdw; +wire mon_remain_rdx; +wire mon_remain_wrc; +wire mon_remain_wrw; +wire mon_remain_wrx; +wire [26:0] out_line_stride; +wire [26:0] out_planar_stride; +wire [26:0] out_surf_stride; +wire [26:0] out_width_stride; +wire [13:0] outchannel; +wire [9:0] outchannelm; +wire [26:0] planar_stride; +wire rd_channel_end; +wire [9:0] rd_chn_cnt_inc; +wire [13:0] rd_chn_num; +wire [9:0] rd_chn_numm; +wire [10:0] rd_cwdth_cnt_inc; +wire rd_cwdth_end; +wire rd_cx_beg; +wire rd_dx_end; +wire [4:0] rd_dx_num; +wire rd_dy_end; +wire rd_height_end; +wire [10:0] rd_mwdth_cnt_inc; +wire rd_mwdth_end; +wire [4:0] rd_planar_num; +wire rd_plar_end; +wire rd_px_beg; +wire rd_req_accept; +wire rd_req_done; +wire rd_stall_cnt_dec; +wire [5:0] rd_total_col; +wire [5:0] rd_total_row; +wire [12:0] remain_rd_channel; +wire [4:0] remain_rd_dx; +wire [12:0] remain_rd_width; +wire [12:0] remain_wr_channel; +wire [4:0] remain_wr_dx; +wire [12:0] remain_wr_width; +wire [12:0] split_rd_size; +wire [14:0] split_rd_size_ext; +wire [12:0] split_wr_size; +wire [58:0] src_base; +wire [26:0] surf_stride; +wire [26:0] width_stride; +wire wr_channel_end; +wire wr_cheight_end; +wire [9:0] wr_chn_cnt_inc; +wire [10:0] wr_cwdth_cnt_inc; +wire wr_cwdth_end; +wire [2:0] wr_dx_cnt_inc; +wire wr_dx_end; +wire [4:0] wr_dx_num; +wire wr_height_end; +wire wr_hx_beg; +wire wr_hx_end; +wire wr_mheight_end; +wire [10:0] wr_mwdth_cnt_inc; +wire wr_mwdth_end; +wire [4:0] wr_planar_num; +wire wr_plar_beg; +wire wr_plar_end; +wire wr_req_accept; +wire wr_req_done; +wire [5:0] wr_total_col; +wire [4:0] wr_total_row; +wire wr_width_end; +wire [4:0] wr_width_num; +wire [4:0] x_stride; +wire [5:0] x_stride_add; +wire [4:0] y_stride; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +///////////////////////////////Configuration/////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_rubik_mode_drv0[1:0] <= {2{1'b0}}; + end else begin + reg2dp_rubik_mode_drv0[1:0] <= reg2dp_rubik_mode[1:0]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_in_precision_drv0[1:0] <= {2{1'b0}}; + end else begin + reg2dp_in_precision_drv0[1:0] <= reg2dp_in_precision[1:0]; + end +end +assign m_contract = reg2dp_rubik_mode_drv0[1:0] == 2'h0 ; +assign m_split = reg2dp_rubik_mode_drv0[1:0] == 2'h1 ; +assign m_merge = reg2dp_rubik_mode_drv0[1:0] == 2'h2 ; +assign m_byte_data = reg2dp_in_precision_drv0[1:0] == 2'h0 ; +assign src_base = {reg2dp_dain_addr_high,reg2dp_dain_addr_low}; +assign dest_base = {reg2dp_daout_addr_high,reg2dp_daout_addr_low}; +assign inwidth_raw[12:0] = reg2dp_datain_width[12:0] ; +assign inheight_raw[12:0] = reg2dp_datain_height[12:0] ; +assign inchannel_raw[12:0] = reg2dp_datain_channel[12:0] ; +assign inwidth[13:0] = reg2dp_datain_width[12:0] +1; +assign inheight[13:0] = reg2dp_datain_height[12:0] +1; +assign inchannel[13:0] = reg2dp_datain_channel[12:0] +1; +assign outchannel[13:0] = reg2dp_dataout_channel[12:0]+1; +assign mon_block_stride[26:0] = reg2dp_contract_stride_1[26:0]; +assign planar_stride[26:0]= reg2dp_dain_planar_stride[26:0]; +assign line_stride[26:0] = reg2dp_dain_line_stride[26:0]; +assign surf_stride[26:0] = reg2dp_dain_surf_stride[26:0]; +assign cube_stride[26:0] = reg2dp_contract_stride_0[26:0]; +assign x_stride[4:0] = reg2dp_deconv_x_stride[4:0]; +assign y_stride[4:0] = reg2dp_deconv_y_stride[4:0]; +assign x_stride_add[5:0] = reg2dp_deconv_x_stride[4:0]+1; +assign out_planar_stride[26:0] = reg2dp_daout_planar_stride[26:0]; +assign out_line_stride[26:0] = reg2dp_daout_line_stride[26:0]; +assign out_surf_stride[26:0] = reg2dp_daout_surf_stride[26:0]; +assign kpgm[1:0] = m_byte_data+1; +assign kpg_dec[4:0] = {m_byte_data,4'hf}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + intern_stride[26:0] <= {27{1'b0}}; + end else begin + intern_stride[26:0] <= m_contract ? cube_stride : m_merge ? planar_stride : 8'h40; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + width_stridem[2:0] <= {3{1'b0}}; + end else begin + width_stridem[2:0] <= m_merge ? m_byte_data ? 3'h1 : 3'h2 : 3'h4; + end +end +assign width_stride[26:0] = {23'h0,width_stridem,1'b0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cubey_stride[31:0] <= {32{1'b0}}; + end else begin + cubey_stride[31:0] <= cube_stride * (x_stride+1); + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + chn_stride[31:0] <= {32{1'b0}}; + end else begin + chn_stride[31:0] <= (m_split | m_contract ) ? {5'h0,surf_stride} : m_byte_data ? {planar_stride,5'h0} : {1'b0,planar_stride,4'h0}; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(m_split | m_contract ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_intern_stride[26:0] <= {27{1'b0}}; + end else begin + out_intern_stride[26:0] <= m_contract ? |x_stride[4:3] ? x_stride_add : out_line_stride : m_split ? out_planar_stride : 8'h40; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_width_stridem[7:0] <= {8{1'b0}}; + end else begin + out_width_stridem[7:0] <= m_contract ? {x_stride_add,2'h0} : (m_byte_data ? 2'h1 : 2'h2); + end +end +assign out_width_stride[26:0] = {18'h0,out_width_stridem,1'b0}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_chn_stride[31:0] <= {32{1'b0}}; + end else begin + out_chn_stride[31:0] <= (m_merge | m_contract ) ? {5'h0,out_surf_stride} : m_byte_data ? {out_planar_stride,5'h0} : {1'b0,out_planar_stride,4'h0}; + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(m_merge | m_contract ))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + inwidth_mul_dx[13:0] <= {14{1'b0}}; + end else begin + inwidth_mul_dx[13:0] <= inwidth * (x_stride+1) -1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + inheight_mul_dy[17:0] <= {18{1'b0}}; + end else begin + inheight_mul_dy[17:0] <= inheight * (y_stride+1) -1; + end +end +/////////////////////rubik en//////////////////////// +//rubik enable +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rubik_en <= 1'b0; + end else begin + if (dp2reg_done) + rubik_en <= 1'b0; + else if (reg2dp_op_en) + rubik_en <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rubik_en_d <= 1'b0; + end else begin + rubik_en_d <= rubik_en; + end +end +assign init_set = rubik_en & ~rubik_en_d; +///////////////////////////////////////////////////////////////////////////// +/////////////////////////generate read dma sequence////////////////////////// +//read request valid +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_req_tmp <= 1'b0; + end else begin + if (rd_req_done | rd_req_done_hold | dp2reg_done) + rd_req_tmp <= 1'b0; + else if (rubik_en) + rd_req_tmp <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_req_done_hold <= 1'b0; + end else begin + if (dp2reg_done) + rd_req_done_hold <= 1'b0; + else if (rd_req_done) + rd_req_done_hold <= 1'b1; + end +end +assign rd_req_done = rd_channel_end; +assign rd_req_type = reg2dp_datain_ram_type; +assign rd_req_vld = rd_req_tmp & rf_wr_cmd_rdy; +assign rd_req_pd[63:0] = {rd_addr,5'h0}; +assign contract_rd_size_ext = {{2{1'b0}}, contract_rd_size}; +assign split_rd_size_ext = {{2{1'b0}}, split_rd_size}; +assign merge_rd_size_ext = {{2{1'b0}}, merge_rd_size}; +assign rd_req_pd[78:64] = m_contract ? contract_rd_size_ext : m_split ? split_rd_size_ext : merge_rd_size_ext ; //rd size 32bytes units and decrease 1 +assign rd_req_accept = rd_req_vld & rd_req_rdy; +//request burst size +assign {mon_remain_rdw,remain_rd_width[12:0]} = inwidth_raw - {rd_width_cnt,3'h0}; +assign {mon_remain_rdc,remain_rd_channel[12:0]} = inchannel_raw -{rd_chn_cnt,4'h0}; +assign {mon_remain_rdx,remain_rd_dx[4:0]} = x_stride - rd_dx_cnt; +assign contract_rd_size[12:0] = remain_rd_width >= 8'h7 ? 6'h7 : remain_rd_width; +assign split_rd_size[12:0] = remain_rd_width >= 8'h3f ? 6'h3f : remain_rd_width; +assign merge_rd_size[12:0] = m_byte_data ? (remain_rd_width >= 8'h20 ? 1'b1 : 1'b0) : + (remain_rd_width >= 8'h30 ? 4'h3 : remain_rd_width >= 8'h20 ? 4'h2 : + remain_rd_width >= 8'h10 ? 4'h1 : 4'h0); +assign rd_dx_num[4:0] = remain_rd_dx >= 5'h7 ? 5'h7 : remain_rd_dx; +assign rd_planar_num[4:0] = remain_rd_channel >= {8'h0,kpg_dec} ? kpg_dec : remain_rd_channel[4:0]; +//caculate ping pong array total row number & total column number +assign wr_total_col[5:0] = m_contract ? contract_rd_size[5:0] : m_split ? split_rd_size[5:0] : merge_rd_size[5:0] ; +assign wr_total_row[4:0] = m_contract ? (|x_stride[4:3] ? rd_dx_num : x_stride) : m_merge ? rd_planar_num[4:0] : 1'b0; +assign rf_wr_cmd_vld = rd_px_beg | rd_cx_beg | m_split & rd_req_accept; +assign rf_wr_cmd_pd = {wr_total_row,wr_total_col}; +/* +&Always posedge; + if(rd_px_beg | rd_cx_beg | m_split & rd_req_accept) begin + rf_wr_cmd_vld <0=1'b1; + rf_wr_cmd_pd <0= {wr_total_row,wr_total_col}; + end + else if (rf_wr_cmd_vld & rf_wr_cmd_rdy) + rf_wr_cmd_vld <0=1'b0; +&End; +*/ +///////generate read sequence address///////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_addr <= {59{1'b0}}; + {mon_rd_addr_c,rd_addr} <= {60{1'b0}}; + end else begin + if(init_set) + rd_addr <= src_base; + else if(rd_height_end) + {mon_rd_addr_c,rd_addr} <= rd_chn_base + chn_stride ; + else if(rd_dy_end | rd_mwdth_end) + {mon_rd_addr_c,rd_addr} <= rd_line_base + line_stride ; + else if(rd_cwdth_end) + {mon_rd_addr_c,rd_addr} <= rd_dy_base + cubey_stride ; + else if(rd_dx_end | rd_plar_end) + {mon_rd_addr_c,rd_addr} <= rd_width_base + width_stride ; + else if(rd_req_accept) + {mon_rd_addr_c,rd_addr} <= rd_addr + intern_stride ; + end +end +//record the pointer base address +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_width_base <= {59{1'b0}}; + {mon_rd_wbase_c,rd_width_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_width_base <= src_base; + else if(rd_height_end) + {mon_rd_wbase_c,rd_width_base} <= rd_chn_base + chn_stride ; + else if(rd_dy_end | rd_mwdth_end) + {mon_rd_wbase_c,rd_width_base} <= rd_line_base + line_stride ; + else if(rd_cwdth_end) + {mon_rd_wbase_c,rd_width_base} <= rd_dy_base + cubey_stride ; + else if(rd_dx_end | rd_plar_end) + {mon_rd_wbase_c,rd_width_base} <= rd_width_base + width_stride ; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_dy_base <= {59{1'b0}}; + {mon_rd_ybase_c,rd_dy_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_dy_base <= src_base; + else if(rd_height_end) + {mon_rd_ybase_c,rd_dy_base} <= rd_chn_base + chn_stride ; + else if(rd_dy_end) + {mon_rd_ybase_c,rd_dy_base} <= rd_line_base + line_stride ; + else if(rd_cwdth_end) + {mon_rd_ybase_c,rd_dy_base} <= rd_dy_base + cubey_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_line_base <= {59{1'b0}}; + {mon_rd_lbase_c,rd_line_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_line_base <= src_base; + else if (rd_height_end) + {mon_rd_lbase_c,rd_line_base} <= rd_chn_base + chn_stride; + else if(rd_dy_end | rd_mwdth_end) + {mon_rd_lbase_c,rd_line_base} <= rd_line_base + line_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_chn_base <= {59{1'b0}}; + {mon_rd_cbase_c,rd_chn_base} <= {60{1'b0}}; + end else begin + if(init_set) + rd_chn_base <= src_base; + else if(rd_height_end) + {mon_rd_cbase_c,rd_chn_base} <= rd_chn_base + chn_stride; + end +end +///////////for circle counter///////////// +//deconv x counter +assign rd_px_beg = m_merge & rd_req_accept & (rd_dx_cnt == 5'h0); +assign rd_cx_beg = m_contract & rd_req_accept & (rd_dx_cnt[2:0] == 3'h0); +assign rd_dx_end = m_contract & rd_req_accept & (rd_dx_cnt == x_stride); +assign rd_plar_end = m_merge & rd_req_accept & (rd_dx_cnt == rd_planar_num); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_dx_cnt <= {5{1'b0}}; + end else begin + if (!rubik_en | rd_dx_end | rd_plar_end) begin + rd_dx_cnt <= 0; + end + else if ((m_contract | m_merge) & rd_req_accept) begin + rd_dx_cnt <= rd_dx_cnt + 1; + end + end +end +//read width counter +assign rd_cwdth_cnt_inc[10:0] = rd_width_cnt + 1'b1; +assign rd_mwdth_cnt_inc[10:0] = rd_width_cnt + 4'h8; +assign {mon_inwidthm_c,inwidthm[10:0]} = inwidth[13:3]+|inwidth[2:0]; +assign rd_cwdth_end = rd_dx_end & (rd_cwdth_cnt_inc >= inwidthm); +assign rd_mwdth_end = (rd_plar_end | m_split & rd_req_accept) & (rd_mwdth_cnt_inc >= inwidthm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_width_cnt <= {10{1'b0}}; + {mon_rd_width_cnt,rd_width_cnt} <= {11{1'b0}}; + end else begin + if (!rubik_en | rd_cwdth_end |rd_mwdth_end) begin + rd_width_cnt <= 0; + end + else if(rd_dx_end) begin + {mon_rd_width_cnt,rd_width_cnt} <= rd_cwdth_cnt_inc; + end + else if(rd_plar_end | m_split & rd_req_accept) begin + {mon_rd_width_cnt,rd_width_cnt} <= rd_mwdth_cnt_inc; + end + end +end +//read deconv y counter +assign rd_dy_end = rd_cwdth_end & (rd_dy_cnt == y_stride); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_dy_cnt <= {5{1'b0}}; + end else begin + if (!rubik_en | rd_dy_end) begin + rd_dy_cnt <= 0; + end + else if (rd_cwdth_end) begin + rd_dy_cnt <= rd_dy_cnt + 1; + end + end +end +//read height counter +assign rd_height_end = (rd_dy_end | rd_mwdth_end) & (rd_line_cnt == inheight_raw); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_line_cnt <= {13{1'b0}}; + end else begin + if (!rubik_en | rd_height_end) begin + rd_line_cnt <= 0; + end + else if(rd_dy_end | rd_mwdth_end) begin + rd_line_cnt <= rd_line_cnt + 1; + end + end +end +//read outchannel counter +assign rd_chn_cnt_inc[9:0] = rd_chn_cnt + kpgm; +assign rd_chn_num[13:0] = m_contract ? outchannel : inchannel; +assign {mon_rd_chn_num_c,rd_chn_numm[9:0]} = rd_chn_num[13:4]+|rd_chn_num[3:0]; +assign rd_channel_end = rd_height_end & (rd_chn_cnt_inc >= rd_chn_numm); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rd_chn_cnt <= {9{1'b0}}; + {mon_rd_chn_cnt,rd_chn_cnt} <= {10{1'b0}}; + end else begin + if (!rubik_en | rd_channel_end) begin + rd_chn_cnt <= 0; + end + else if(rd_height_end) begin + {mon_rd_chn_cnt,rd_chn_cnt} <= rd_chn_cnt_inc; + end + end +end +//////////////////////////////////////////////////////////////////////////////////// +///////////////////////////generate write dma sequence////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dma_wr_cmd_vld_tmp <= 1'b0; + end else begin + if (wr_req_done | wr_req_done_hold | dp2reg_done) + dma_wr_cmd_vld_tmp <= 1'b0; + else if (rubik_en) + dma_wr_cmd_vld_tmp <= 1'b1; + end +end +assign dma_wr_cmd_vld = dma_wr_cmd_vld_tmp & rf_rd_cmd_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_req_done_hold <= 1'b0; + end else begin + if (dp2reg_done) + wr_req_done_hold <= 1'b0; + else if (wr_req_done) + wr_req_done_hold <= 1'b1; + end +end +assign wr_req_done = wr_channel_end; +assign dma_wr_cmd_pd[77:77] = wr_req_done; +assign dma_wr_cmd_pd[76:64] = m_contract ? contract_wr_size : m_merge ? merge_wr_size : split_wr_size; +assign dma_wr_cmd_pd[63:0] = {wr_addr,5'b0}; +assign wr_req_accept = dma_wr_cmd_vld & dma_wr_cmd_rdy; +//request burst size +assign {mon_remain_wrw,remain_wr_width[12:0]} = inwidth_raw - {wr_width_cnt,3'h0}; +assign {mon_remain_wrc,remain_wr_channel[12:0]} = inchannel_raw -{wr_chn_cnt,4'h0}; +assign {mon_remain_wrx,remain_wr_dx[4:0]} = x_stride - {wr_dx_cnt,3'h0}; +assign contract_wr_size[12:0] = |x_stride[4:3] ? {8'h0,wr_dx_num[4:0]} : inwidth_mul_dx[12:0]; +assign merge_wr_size[12:0] = remain_wr_width >= 6'h3f ? 6'h3f : remain_wr_width; +assign split_wr_size[12:0] = m_byte_data ? (remain_wr_width >= 6'h20 ? 1'b1 : 1'b0) : + (remain_wr_width >= 6'h30 ? 4'h3 : remain_wr_width >= 6'h20 ? 4'h2 : + remain_wr_width >= 6'h10 ? 4'h1 : 4'h0); +assign wr_dx_num[4:0] = remain_wr_dx >= 4'h7 ? 4'h7 : remain_wr_dx ; +assign wr_width_num[4:0] = remain_wr_width >= 4'h7 ? 4'h7 : remain_wr_width[4:0]; +assign wr_planar_num[4:0] = remain_wr_channel >= {8'h0,kpg_dec} ? kpg_dec : remain_wr_channel[4:0]; +//merge and split of read total column unit is element(1byte or 2byte), but contract unit is 32bytes +assign rd_total_col[5:0] = m_contract ? (|x_stride[4:3] ? {1'b0,wr_dx_num} : {1'b0,x_stride}) : m_merge ? {1'b0,wr_planar_num[4:0]} : merge_wr_size[5:0]; +assign rd_total_row[5:0] = m_contract ? (|x_stride[4:3] ? {1'b0,wr_width_num[4:0]} : 1'b0) : m_merge ? merge_wr_size[5:0] : {1'b0,wr_planar_num[4:0]}; +assign contract_lit_dx = m_contract & ~(|x_stride[4:3]); +assign rf_rd_cmd_vld = wr_plar_beg | wr_hx_beg | (m_contract & ~(|x_stride[4:3]) | m_merge) & wr_req_accept; +assign rf_rd_cmd_pd = {rd_total_row,rd_total_col}; +/* +&Always posedge; + if (wr_plar_beg | wr_hx_beg | (m_contract & ~(|x_stride[4:3]) | m_merge) & wr_req_accept) begin + rf_rd_cmd_vld <0=1'b1; + rf_rd_cmd_pd <0= {rd_total_row,rd_total_col}; + end + else if (rf_rd_cmd_vld & rf_rd_cmd_rdy) + rf_rd_cmd_vld <0=1'b0; +&End; +*/ +///////generate write sequence address///////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_addr <= {59{1'b0}}; + {mon_wr_addr_c,wr_addr} <= {60{1'b0}}; + end else begin + if(init_set) + wr_addr <= dest_base; + else if(wr_height_end) + {mon_wr_addr_c,wr_addr} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_addr_c,wr_addr} <= wr_line_base + out_line_stride ; + else if(wr_dx_end | wr_plar_end) + {mon_wr_addr_c,wr_addr} <= wr_width_base + out_width_stride ; + else if(wr_hx_end) + {mon_wr_addr_c,wr_addr} <= wr_dx_base + 4'h8; + else if(wr_req_accept) + {mon_wr_addr_c,wr_addr} <= wr_addr + out_intern_stride ; + end +end +//record the pointer base address +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_dx_base <= {59{1'b0}}; + {mon_wr_xbase_c,wr_dx_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_dx_base <= dest_base; + else if(wr_height_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_line_base + out_line_stride ; + else if(wr_dx_end | wr_plar_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_width_base + out_width_stride ; + else if(wr_hx_end) + {mon_wr_xbase_c,wr_dx_base} <= wr_dx_base + 4'h8; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_width_base <= {59{1'b0}}; + {mon_wr_wbase_c,wr_width_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_width_base <= dest_base; + else if(wr_height_end) + {mon_wr_wbase_c,wr_width_base} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_wbase_c,wr_width_base} <= wr_line_base + out_line_stride ; + else if(wr_dx_end | wr_plar_end) + {mon_wr_wbase_c,wr_width_base} <= wr_width_base + out_width_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_base <= {59{1'b0}}; + {mon_wr_lbase_c,wr_line_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_line_base <= dest_base; + else if(wr_height_end) + {mon_wr_lbase_c,wr_line_base} <= wr_chn_base + out_chn_stride ; + else if(wr_width_end) + {mon_wr_lbase_c,wr_line_base} <= wr_line_base + out_line_stride; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_chn_base <= {59{1'b0}}; + {mon_wr_cbase_c,wr_chn_base} <= {60{1'b0}}; + end else begin + if(init_set) + wr_chn_base <= dest_base; + else if(wr_height_end) + {mon_wr_cbase_c,wr_chn_base} <= wr_chn_base + out_chn_stride; + end +end +///////////for circle counter///////////// +//internal counter +assign wr_hx_beg = m_contract & (|x_stride[4:3]) & wr_req_accept & (wr_plar_cnt == 0); +assign wr_hx_end = m_contract & (|x_stride[4:3]) & wr_req_accept & (wr_plar_cnt == wr_width_num); +assign wr_plar_beg = m_split & wr_req_accept & (wr_plar_cnt == 0); +assign wr_plar_end = m_split & wr_req_accept & (wr_plar_cnt == wr_planar_num); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_plar_cnt <= {5{1'b0}}; + end else begin + if (!rubik_en | wr_hx_end | wr_plar_end) begin + wr_plar_cnt <= 0; + end + else if ((m_contract & (|x_stride[4:3]) | m_split) & wr_req_accept) begin + wr_plar_cnt <= wr_plar_cnt + 1; + end + end +end +//deconv x counter +assign wr_dx_cnt_inc[2:0] = wr_dx_cnt + 1'b1; +assign {mon_dx_stride_num_c,dx_stride_num[2:0]} = x_stride_add[5:3]+|x_stride_add[2:0]; +assign wr_dx_end = wr_hx_end & (wr_dx_cnt_inc >= dx_stride_num); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_dx_cnt <= {2{1'b0}}; + {mon_wr_dx_cnt,wr_dx_cnt} <= {3{1'b0}}; + end else begin + if (!rubik_en | wr_dx_end) begin + wr_dx_cnt <= 0; + end + else if (wr_hx_end) begin + {mon_wr_dx_cnt,wr_dx_cnt} <= wr_dx_cnt_inc; + end + end +end +//write width counter +assign wr_cwdth_cnt_inc[10:0] = wr_width_cnt + 1'b1; +assign wr_mwdth_cnt_inc[10:0] = wr_width_cnt + 4'h8; +assign wr_cwdth_end = wr_dx_end & (wr_cwdth_cnt_inc >= inwidthm[10:0]); +assign wr_mwdth_end =(wr_plar_end | m_merge & wr_req_accept) & (wr_mwdth_cnt_inc >= inwidthm[10:0]); +assign wr_width_end = wr_cwdth_end | wr_mwdth_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_width_cnt <= {10{1'b0}}; + {mon_wr_width_cnt,wr_width_cnt} <= {11{1'b0}}; + end else begin + if (!rubik_en | wr_width_end) begin + wr_width_cnt <= 0; + end + else if(wr_dx_end) begin + {mon_wr_width_cnt,wr_width_cnt} <= wr_cwdth_cnt_inc; + end + else if(wr_plar_end | m_merge & wr_req_accept) begin + {mon_wr_width_cnt,wr_width_cnt} <= wr_mwdth_cnt_inc; + end + end +end +//write height counter +assign wr_cheight_end = (wr_cwdth_end | m_contract & ~(|x_stride[4:3]) & wr_req_accept) & (wr_line_cnt == inheight_mul_dy); +assign wr_mheight_end = wr_mwdth_end & (wr_line_cnt == {5'h0,inheight_raw}); +assign wr_height_end = wr_cheight_end | wr_mheight_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_line_cnt <= {18{1'b0}}; + end else begin + if (!rubik_en | wr_height_end) begin + wr_line_cnt <= 0; + end + else if(wr_width_end | m_contract & ~(|x_stride[4:3]) & wr_req_accept) begin + wr_line_cnt <= wr_line_cnt + 1; + end + end +end +//write channel counter +assign wr_chn_cnt_inc[9:0] = wr_chn_cnt + kpgm; +assign {mon_outchannelm_c,outchannelm[9:0]} = outchannel[13:4]+|outchannel[3:0]; +assign wr_channel_end = wr_height_end & (wr_chn_cnt_inc >= outchannelm[9:0]); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_chn_cnt <= {9{1'b0}}; + {mon_wr_chn_cnt,wr_chn_cnt} <= {10{1'b0}}; + end else begin + if (!rubik_en | wr_channel_end) begin + wr_chn_cnt <= 0; + end + else if(wr_height_end) begin + {mon_wr_chn_cnt,wr_chn_cnt} <= wr_chn_cnt_inc; + end + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_seq_gen__read_request_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + rd_req_vld & !rd_req_rdy; + endproperty +// Cover 0 : "rd_req_vld & !rd_req_rdy" + FUNCPOINT_rubik_seq_gen__read_request_block__0_COV : cover property (rubik_seq_gen__read_request_block__0_cov); + `endif +`endif +//VCS coverage on + assign rd_stall_cnt_dec = 1'b0; +// stl adv logic + always @( + rd_req_vld + or rd_stall_cnt_dec + ) begin + stl_adv = rd_req_vld ^ rd_stall_cnt_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or rd_req_vld + or rd_stall_cnt_dec + or stl_adv + or rd_req_done + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (rd_req_vld && !rd_stall_cnt_dec)? stl_cnt_inc : (!rd_req_vld && rd_stall_cnt_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (rd_req_done)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_en) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + rd_stall_cnt[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_rd_stall_cnt <= {32{1'b0}}; + end else begin + if (rd_req_done & ~dp2reg_consumer) + dp2reg_d0_rd_stall_cnt <= rd_stall_cnt; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_rd_stall_cnt <= {32{1'b0}}; + end else begin + if (rd_req_done & dp2reg_consumer) + dp2reg_d1_rd_stall_cnt <= rd_stall_cnt; + end +end +endmodule // NV_NVDLA_RUBIK_seq_gen diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v new file mode 100644 index 0000000..636dc96 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_single_reg.v +module NV_NVDLA_RUBIK_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_rbk_s_pointer_0_out; +wire [31:0] nvdla_rbk_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_rbk_s_pointer_0_wren = (reg_offset_wr == (32'h10004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_s_status_0_wren = (reg_offset_wr == (32'h10000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_rbk_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_rbk_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_rbk_s_pointer_0_out + or nvdla_rbk_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h10004 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_s_pointer_0_out ; + end + (32'h10000 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_RBK_S_POINTER_0::consumer +// Register: NVDLA_RBK_S_POINTER_0 Field: producer + if (nvdla_rbk_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_RBK_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_RBK_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h10004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_s_pointer_0_out, nvdla_rbk_s_pointer_0_out); + (32'h10000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_RBK_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_RUBIK_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v.vcp new file mode 100644 index 0000000..636dc96 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_single_reg.v +module NV_NVDLA_RUBIK_single_reg ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_rbk_s_pointer_0_out; +wire [31:0] nvdla_rbk_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_rbk_s_pointer_0_wren = (reg_offset_wr == (32'h10004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_rbk_s_status_0_wren = (reg_offset_wr == (32'h10000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_rbk_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_rbk_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_rbk_s_pointer_0_out + or nvdla_rbk_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'h10004 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_s_pointer_0_out ; + end + (32'h10000 & 32'h00000fff): begin + reg_rd_data = nvdla_rbk_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_RBK_S_POINTER_0::consumer +// Register: NVDLA_RBK_S_POINTER_0 Field: producer + if (nvdla_rbk_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_RBK_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_RBK_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'h10004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_RBK_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_rbk_s_pointer_0_out, nvdla_rbk_s_pointer_0_out); + (32'h10000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_RBK_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_RUBIK_single_reg diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v new file mode 100644 index 0000000..363bf02 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v @@ -0,0 +1,387 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_slcg.v +module NV_NVDLA_RUBIK_slcg ( + dla_clk_ovr_on_sync + ,enable + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input enable; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_RUBIK_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v.vcp new file mode 100644 index 0000000..363bf02 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v.vcp @@ -0,0 +1,387 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_slcg.v +module NV_NVDLA_RUBIK_slcg ( + dla_clk_ovr_on_sync + ,enable + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,tmc2slcg_disable_clock_gating + ,nvdla_core_gated_clk + ); +input dla_clk_ovr_on_sync; +input enable; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input tmc2slcg_disable_clock_gating; +output nvdla_core_gated_clk; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = enable | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_core_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_RUBIK_slcg ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +endmodule // NV_NVDLA_RUBIK_slcg diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v new file mode 100644 index 0000000..aabd8d4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v @@ -0,0 +1,401 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_wr_req.v +module NV_NVDLA_RUBIK_wr_req ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dma_wr_cmd_pd //|< i + ,dma_wr_cmd_vld //|< i + ,dma_wr_data_pd //|< i + ,dma_wr_data_vld //|< i + ,dp2reg_consumer //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_dataout_ram_type //|< i + ,reg2dp_perf_en //|< i + ,wr_req_rdy //|< i + ,dma_wr_cmd_rdy //|> o + ,dma_wr_data_rdy //|> o + ,dp2reg_d0_wr_stall_cnt //|> o + ,dp2reg_d1_wr_stall_cnt //|> o + ,dp2reg_done //|> o + ,wr_req_pd //|> o + ,wr_req_type //|> o + ,wr_req_vld //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_consumer; +input [31:0] pwrbus_ram_pd; +input reg2dp_dataout_ram_type; +input reg2dp_perf_en; +output [31:0] dp2reg_d0_wr_stall_cnt; +output [31:0] dp2reg_d1_wr_stall_cnt; +output wr_req_type; +output wr_req_vld; +output [514:0] wr_req_pd; +input wr_req_rdy; +input dma_wr_cmd_vld; +input [77:0] dma_wr_cmd_pd; +output dma_wr_cmd_rdy; +input dma_wr_data_vld; +input [513:0] dma_wr_data_pd; +output dma_wr_data_rdy; +output dp2reg_done; +reg [3:0] dbuf_remain; +reg [31:0] dp2reg_d0_wr_stall_cnt; +reg [31:0] dp2reg_d1_wr_stall_cnt; +reg dp2reg_done_d; +reg fill_half; +reg last_wr_cmd; +reg mon_dbuf_remain; +reg mon_wr_dcnt_c; +reg send_cmd; +reg send_cmd_open; +reg send_data; +reg [13:0] send_data_size; +reg send_half; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [12:0] wr_data_cnt; +reg wr_req_stall_inc_d; +reg [31:0] wr_stall_cnt; +wire dbuf_nempty; +wire [513:78] dma_wr_cmd_hpd; +wire [77:0] dma_wr_cmd_opd; +wire [72:0] dma_wr_cmd_opdt; +wire dma_wr_cmd_ordy; +wire dma_wr_cmd_ovld; +wire dma_wr_cmd_pop; +wire dma_wr_cmd_req_vld; +wire [511:0] dma_wr_data_opd; +wire dma_wr_data_ordy; +wire dma_wr_data_pop; +wire dma_wr_data_push; +wire dma_wr_data_req_vld; +wire [255:0] dma_wr_datah_opd; +wire dma_wr_datah_ordy; +wire dma_wr_datah_ovld; +wire [255:0] dma_wr_datah_pd; +wire dma_wr_datah_pop; +wire dma_wr_datah_rdy; +wire dma_wr_datah_vld; +wire [255:0] dma_wr_datal_opd; +wire dma_wr_datal_ordy; +wire dma_wr_datal_ovld; +wire [255:0] dma_wr_datal_pd; +wire dma_wr_datal_pop; +wire dma_wr_datal_rdy; +wire dma_wr_datal_vld; +wire [1:0] fifo_mask; +wire [1:0] fifo_omask; +wire mon_remain_dsize; +wire [1:0] pop_size; +wire [1:0] push_size; +wire [13:0] remain_data_size; +wire send_data_done; +wire [13:0] wr_data_cnt_inc; +wire wr_req_stall_inc; +wire wr_stall_cnt_dec; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign dp2reg_done = send_data_done & last_wr_cmd; +assign wr_req_type = reg2dp_dataout_ram_type; +assign wr_req_vld = dma_wr_cmd_req_vld || dma_wr_data_req_vld; +assign wr_req_pd[514:514] = dma_wr_cmd_pop ? 1'd0 /* PKT_nvdla_dma_wr_req_dma_write_cmd_ID */ : 1'd1 /* PKT_nvdla_dma_wr_req_dma_write_data_ID */ ; +assign wr_req_pd[513:0] = dma_wr_cmd_pop ? {dma_wr_cmd_hpd,dma_wr_cmd_opd} : {fifo_omask,dma_wr_data_opd}; +assign dma_wr_cmd_hpd[513:78] = {436{1'b0}}; +assign dma_wr_cmd_ordy = send_cmd & wr_req_rdy; +assign dma_wr_cmd_pop = dma_wr_cmd_ordy & dma_wr_cmd_ovld; +assign dma_wr_cmd_req_vld = send_cmd & dma_wr_cmd_ovld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_cmd <= 1'b0; + end else begin + if (dma_wr_cmd_pop) + send_cmd <= 1'b0; + else if((send_cmd_open | send_data_done) & dbuf_nempty) + send_cmd <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_cmd_open <= 1'b1; + end else begin + if (send_cmd_open & dbuf_nempty) + send_cmd_open <= 1'b0; + else if (send_data_done & ~dbuf_nempty) + send_cmd_open <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_data <= 1'b0; + end else begin + if (send_data_done) + send_data <= 1'b0; + else if (dma_wr_cmd_pop) + send_data <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_wr_cmd <= 1'b0; + send_data_size <= {14{1'b0}}; + end else begin + if (dma_wr_cmd_pop) begin + last_wr_cmd <= dma_wr_cmd_opd[77:77]; + send_data_size <= dma_wr_cmd_opd[76:64]+1; + end + end +end +//push data +assign fifo_mask[1:0] = dma_wr_data_pd[513:512]; +assign dma_wr_data_rdy = ~fifo_mask[1] ? (fill_half ? dma_wr_datah_rdy : dma_wr_datal_rdy) : dma_wr_datah_rdy & dma_wr_datal_rdy; +assign dma_wr_data_push = dma_wr_data_vld & dma_wr_data_rdy; +assign dma_wr_datah_vld = dma_wr_data_push & (&fifo_mask[1:0] || fill_half & ~fifo_mask[1]); +assign dma_wr_datal_vld = dma_wr_data_push & (&fifo_mask[1:0] || !fill_half & ~fifo_mask[1]); +assign dma_wr_datah_pd[255:0]= fill_half ? dma_wr_data_pd[255:0] : dma_wr_data_pd[511:256] ; +assign dma_wr_datal_pd[255:0]= fill_half ? dma_wr_data_pd[511:256] : dma_wr_data_pd[255:0] ; +assign push_size[1:0] = fifo_mask[1] + fifo_mask[0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + fill_half <= 1'b0; + end else begin + if (dp2reg_done) + fill_half <= 1'b0; + else if (dma_wr_data_push & ~fifo_mask[1]) + fill_half <= ~fill_half; + end +end +//pop data +assign dma_wr_data_ordy = send_data & wr_req_rdy; +assign dma_wr_datah_ordy = (~fifo_omask[1] ? !send_half ? 1'b0 : dma_wr_datah_ovld : dma_wr_datah_ovld & dma_wr_datal_ovld) & dma_wr_data_ordy; +assign dma_wr_datal_ordy = (~fifo_omask[1] ? send_half ? 1'b0 : dma_wr_datal_ovld : dma_wr_datah_ovld & dma_wr_datal_ovld) & dma_wr_data_ordy; +assign dma_wr_data_opd[511:0] = send_half ? {dma_wr_datal_opd[255:0],dma_wr_datah_opd[255:0]} : {dma_wr_datah_opd[255:0],dma_wr_datal_opd[255:0]}; +assign dma_wr_data_req_vld = send_data & (~fifo_omask[1] ? !send_half ? dma_wr_datal_ovld : dma_wr_datah_ovld : dma_wr_datah_ovld & dma_wr_datal_ovld); +assign dma_wr_datah_pop = dma_wr_datah_ordy & dma_wr_datah_ovld; +assign dma_wr_datal_pop = dma_wr_datal_ordy & dma_wr_datal_ovld; +assign dma_wr_data_pop = dma_wr_datah_pop | dma_wr_datal_pop; +assign pop_size[1:0] = dma_wr_datah_pop + dma_wr_datal_pop; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_half <= 1'b0; + end else begin + if (dp2reg_done) + send_half <= 1'b0; + else if (dma_wr_data_pop & ~fifo_omask[1]) + send_half <= ~send_half; + end +end +assign {mon_remain_dsize,remain_data_size} = send_data_size - wr_data_cnt; +assign fifo_omask[1:0] = remain_data_size == 1'b1 ? 2'b01 : 2'b11; +assign wr_data_cnt_inc = wr_data_cnt + pop_size; +assign send_data_done = dma_wr_data_pop & (wr_data_cnt_inc >= send_data_size); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_cnt <= {13{1'b0}}; + {mon_wr_dcnt_c,wr_data_cnt} <= {14{1'b0}}; + end else begin + if (send_data_done) + wr_data_cnt <= {13'b0}; + else if(dma_wr_data_pop) + {mon_wr_dcnt_c,wr_data_cnt} <= wr_data_cnt_inc; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_dbuf_remain,dbuf_remain[3:0]} <= {5{1'b0}}; + end else begin + if (dma_wr_data_push & dma_wr_data_pop) + {mon_dbuf_remain,dbuf_remain[3:0]} <= dbuf_remain+push_size-pop_size; + else if (dma_wr_data_push) + {mon_dbuf_remain,dbuf_remain[3:0]} <= dbuf_remain+push_size; + else if (dma_wr_data_pop) + {mon_dbuf_remain,dbuf_remain[3:0]} <= dbuf_remain-pop_size; + end +end +assign dbuf_nempty = |dbuf_remain[3:0]; +assign dma_wr_cmd_opd[77:0] = {dma_wr_cmd_opdt[72:0],5'h0}; +NV_NVDLA_RUBIK_wrdma_cmd rbk_dma_wr_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (dma_wr_cmd_rdy) //|> o + ,.idata_pvld (dma_wr_cmd_vld) //|< i + ,.idata_pd (dma_wr_cmd_pd[77:5]) //|< i + ,.odata_prdy (dma_wr_cmd_ordy) //|< w + ,.odata_pvld (dma_wr_cmd_ovld) //|> w + ,.odata_pd (dma_wr_cmd_opdt[72:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_RUBIK_wrdma_data rbk_dma_wr_datah_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (dma_wr_datah_rdy) //|> w + ,.idata_pvld (dma_wr_datah_vld) //|< w + ,.idata_pd (dma_wr_datah_pd[255:0]) //|< w + ,.odata_prdy (dma_wr_datah_ordy) //|< w + ,.odata_pvld (dma_wr_datah_ovld) //|> w + ,.odata_pd (dma_wr_datah_opd[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_RUBIK_wrdma_data rbk_dma_wr_datal_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (dma_wr_datal_rdy) //|> w + ,.idata_pvld (dma_wr_datal_vld) //|< w + ,.idata_pd (dma_wr_datal_pd[255:0]) //|< w + ,.odata_prdy (dma_wr_datal_ordy) //|< w + ,.odata_pvld (dma_wr_datal_ovld) //|> w + ,.odata_pd (dma_wr_datal_opd[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign wr_req_stall_inc = wr_req_vld & !wr_req_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_req_stall_inc_d <= 1'b0; + end else begin + wr_req_stall_inc_d <= wr_req_stall_inc; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_done_d <= 1'b0; + end else begin + dp2reg_done_d <= dp2reg_done; + end +end + assign wr_stall_cnt_dec = 1'b0; +// stl adv logic + always @( + wr_req_stall_inc_d + or wr_stall_cnt_dec + ) begin + stl_adv = wr_req_stall_inc_d ^ wr_stall_cnt_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or wr_req_stall_inc_d + or wr_stall_cnt_dec + or stl_adv + or dp2reg_done_d + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wr_req_stall_inc_d && !wr_stall_cnt_dec)? stl_cnt_inc : (!wr_req_stall_inc_d && wr_stall_cnt_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (dp2reg_done_d)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_en) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + wr_stall_cnt[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wr_stall_cnt <= {32{1'b0}}; + end else begin + if (dp2reg_done & ~dp2reg_consumer) + dp2reg_d0_wr_stall_cnt <= wr_stall_cnt; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wr_stall_cnt <= {32{1'b0}}; + end else begin + if (dp2reg_done & dp2reg_consumer) + dp2reg_d1_wr_stall_cnt <= wr_stall_cnt; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_wr_req__wr_request_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + wr_req_vld & ~wr_req_rdy; + endproperty +// Cover 0 : "wr_req_vld & ~wr_req_rdy" + FUNCPOINT_rubik_wr_req__wr_request_block__0_COV : cover property (rubik_wr_req__wr_request_block__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_wr_req__wr_req_cmd_after_rf_nempty__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + send_data_done & ~dbuf_nempty; + endproperty +// Cover 1 : "send_data_done & ~dbuf_nempty" + FUNCPOINT_rubik_wr_req__wr_req_cmd_after_rf_nempty__1_COV : cover property (rubik_wr_req__wr_req_cmd_after_rf_nempty__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_wr_req__dma_wr_dbuf_fill_half__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_data_push & fill_half; + endproperty +// Cover 2 : "dma_wr_data_push & fill_half" + FUNCPOINT_rubik_wr_req__dma_wr_dbuf_fill_half__2_COV : cover property (rubik_wr_req__dma_wr_dbuf_fill_half__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_wr_req__dma_wr_dbuf_send_half__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_data_pop & send_half; + endproperty +// Cover 3 : "dma_wr_data_pop & send_half" + FUNCPOINT_rubik_wr_req__dma_wr_dbuf_send_half__3_COV : cover property (rubik_wr_req__dma_wr_dbuf_send_half__3_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_RUBIK_wr_req diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v.vcp new file mode 100644 index 0000000..aabd8d4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v.vcp @@ -0,0 +1,401 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_wr_req.v +module NV_NVDLA_RUBIK_wr_req ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dma_wr_cmd_pd //|< i + ,dma_wr_cmd_vld //|< i + ,dma_wr_data_pd //|< i + ,dma_wr_data_vld //|< i + ,dp2reg_consumer //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_dataout_ram_type //|< i + ,reg2dp_perf_en //|< i + ,wr_req_rdy //|< i + ,dma_wr_cmd_rdy //|> o + ,dma_wr_data_rdy //|> o + ,dp2reg_d0_wr_stall_cnt //|> o + ,dp2reg_d1_wr_stall_cnt //|> o + ,dp2reg_done //|> o + ,wr_req_pd //|> o + ,wr_req_type //|> o + ,wr_req_vld //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dp2reg_consumer; +input [31:0] pwrbus_ram_pd; +input reg2dp_dataout_ram_type; +input reg2dp_perf_en; +output [31:0] dp2reg_d0_wr_stall_cnt; +output [31:0] dp2reg_d1_wr_stall_cnt; +output wr_req_type; +output wr_req_vld; +output [514:0] wr_req_pd; +input wr_req_rdy; +input dma_wr_cmd_vld; +input [77:0] dma_wr_cmd_pd; +output dma_wr_cmd_rdy; +input dma_wr_data_vld; +input [513:0] dma_wr_data_pd; +output dma_wr_data_rdy; +output dp2reg_done; +reg [3:0] dbuf_remain; +reg [31:0] dp2reg_d0_wr_stall_cnt; +reg [31:0] dp2reg_d1_wr_stall_cnt; +reg dp2reg_done_d; +reg fill_half; +reg last_wr_cmd; +reg mon_dbuf_remain; +reg mon_wr_dcnt_c; +reg send_cmd; +reg send_cmd_open; +reg send_data; +reg [13:0] send_data_size; +reg send_half; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [12:0] wr_data_cnt; +reg wr_req_stall_inc_d; +reg [31:0] wr_stall_cnt; +wire dbuf_nempty; +wire [513:78] dma_wr_cmd_hpd; +wire [77:0] dma_wr_cmd_opd; +wire [72:0] dma_wr_cmd_opdt; +wire dma_wr_cmd_ordy; +wire dma_wr_cmd_ovld; +wire dma_wr_cmd_pop; +wire dma_wr_cmd_req_vld; +wire [511:0] dma_wr_data_opd; +wire dma_wr_data_ordy; +wire dma_wr_data_pop; +wire dma_wr_data_push; +wire dma_wr_data_req_vld; +wire [255:0] dma_wr_datah_opd; +wire dma_wr_datah_ordy; +wire dma_wr_datah_ovld; +wire [255:0] dma_wr_datah_pd; +wire dma_wr_datah_pop; +wire dma_wr_datah_rdy; +wire dma_wr_datah_vld; +wire [255:0] dma_wr_datal_opd; +wire dma_wr_datal_ordy; +wire dma_wr_datal_ovld; +wire [255:0] dma_wr_datal_pd; +wire dma_wr_datal_pop; +wire dma_wr_datal_rdy; +wire dma_wr_datal_vld; +wire [1:0] fifo_mask; +wire [1:0] fifo_omask; +wire mon_remain_dsize; +wire [1:0] pop_size; +wire [1:0] push_size; +wire [13:0] remain_data_size; +wire send_data_done; +wire [13:0] wr_data_cnt_inc; +wire wr_req_stall_inc; +wire wr_stall_cnt_dec; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign dp2reg_done = send_data_done & last_wr_cmd; +assign wr_req_type = reg2dp_dataout_ram_type; +assign wr_req_vld = dma_wr_cmd_req_vld || dma_wr_data_req_vld; +assign wr_req_pd[514:514] = dma_wr_cmd_pop ? 1'd0 /* PKT_nvdla_dma_wr_req_dma_write_cmd_ID */ : 1'd1 /* PKT_nvdla_dma_wr_req_dma_write_data_ID */ ; +assign wr_req_pd[513:0] = dma_wr_cmd_pop ? {dma_wr_cmd_hpd,dma_wr_cmd_opd} : {fifo_omask,dma_wr_data_opd}; +assign dma_wr_cmd_hpd[513:78] = {436{1'b0}}; +assign dma_wr_cmd_ordy = send_cmd & wr_req_rdy; +assign dma_wr_cmd_pop = dma_wr_cmd_ordy & dma_wr_cmd_ovld; +assign dma_wr_cmd_req_vld = send_cmd & dma_wr_cmd_ovld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_cmd <= 1'b0; + end else begin + if (dma_wr_cmd_pop) + send_cmd <= 1'b0; + else if((send_cmd_open | send_data_done) & dbuf_nempty) + send_cmd <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_cmd_open <= 1'b1; + end else begin + if (send_cmd_open & dbuf_nempty) + send_cmd_open <= 1'b0; + else if (send_data_done & ~dbuf_nempty) + send_cmd_open <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_data <= 1'b0; + end else begin + if (send_data_done) + send_data <= 1'b0; + else if (dma_wr_cmd_pop) + send_data <= 1'b1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + last_wr_cmd <= 1'b0; + send_data_size <= {14{1'b0}}; + end else begin + if (dma_wr_cmd_pop) begin + last_wr_cmd <= dma_wr_cmd_opd[77:77]; + send_data_size <= dma_wr_cmd_opd[76:64]+1; + end + end +end +//push data +assign fifo_mask[1:0] = dma_wr_data_pd[513:512]; +assign dma_wr_data_rdy = ~fifo_mask[1] ? (fill_half ? dma_wr_datah_rdy : dma_wr_datal_rdy) : dma_wr_datah_rdy & dma_wr_datal_rdy; +assign dma_wr_data_push = dma_wr_data_vld & dma_wr_data_rdy; +assign dma_wr_datah_vld = dma_wr_data_push & (&fifo_mask[1:0] || fill_half & ~fifo_mask[1]); +assign dma_wr_datal_vld = dma_wr_data_push & (&fifo_mask[1:0] || !fill_half & ~fifo_mask[1]); +assign dma_wr_datah_pd[255:0]= fill_half ? dma_wr_data_pd[255:0] : dma_wr_data_pd[511:256] ; +assign dma_wr_datal_pd[255:0]= fill_half ? dma_wr_data_pd[511:256] : dma_wr_data_pd[255:0] ; +assign push_size[1:0] = fifo_mask[1] + fifo_mask[0]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + fill_half <= 1'b0; + end else begin + if (dp2reg_done) + fill_half <= 1'b0; + else if (dma_wr_data_push & ~fifo_mask[1]) + fill_half <= ~fill_half; + end +end +//pop data +assign dma_wr_data_ordy = send_data & wr_req_rdy; +assign dma_wr_datah_ordy = (~fifo_omask[1] ? !send_half ? 1'b0 : dma_wr_datah_ovld : dma_wr_datah_ovld & dma_wr_datal_ovld) & dma_wr_data_ordy; +assign dma_wr_datal_ordy = (~fifo_omask[1] ? send_half ? 1'b0 : dma_wr_datal_ovld : dma_wr_datah_ovld & dma_wr_datal_ovld) & dma_wr_data_ordy; +assign dma_wr_data_opd[511:0] = send_half ? {dma_wr_datal_opd[255:0],dma_wr_datah_opd[255:0]} : {dma_wr_datah_opd[255:0],dma_wr_datal_opd[255:0]}; +assign dma_wr_data_req_vld = send_data & (~fifo_omask[1] ? !send_half ? dma_wr_datal_ovld : dma_wr_datah_ovld : dma_wr_datah_ovld & dma_wr_datal_ovld); +assign dma_wr_datah_pop = dma_wr_datah_ordy & dma_wr_datah_ovld; +assign dma_wr_datal_pop = dma_wr_datal_ordy & dma_wr_datal_ovld; +assign dma_wr_data_pop = dma_wr_datah_pop | dma_wr_datal_pop; +assign pop_size[1:0] = dma_wr_datah_pop + dma_wr_datal_pop; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + send_half <= 1'b0; + end else begin + if (dp2reg_done) + send_half <= 1'b0; + else if (dma_wr_data_pop & ~fifo_omask[1]) + send_half <= ~send_half; + end +end +assign {mon_remain_dsize,remain_data_size} = send_data_size - wr_data_cnt; +assign fifo_omask[1:0] = remain_data_size == 1'b1 ? 2'b01 : 2'b11; +assign wr_data_cnt_inc = wr_data_cnt + pop_size; +assign send_data_done = dma_wr_data_pop & (wr_data_cnt_inc >= send_data_size); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_data_cnt <= {13{1'b0}}; + {mon_wr_dcnt_c,wr_data_cnt} <= {14{1'b0}}; + end else begin + if (send_data_done) + wr_data_cnt <= {13'b0}; + else if(dma_wr_data_pop) + {mon_wr_dcnt_c,wr_data_cnt} <= wr_data_cnt_inc; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_dbuf_remain,dbuf_remain[3:0]} <= {5{1'b0}}; + end else begin + if (dma_wr_data_push & dma_wr_data_pop) + {mon_dbuf_remain,dbuf_remain[3:0]} <= dbuf_remain+push_size-pop_size; + else if (dma_wr_data_push) + {mon_dbuf_remain,dbuf_remain[3:0]} <= dbuf_remain+push_size; + else if (dma_wr_data_pop) + {mon_dbuf_remain,dbuf_remain[3:0]} <= dbuf_remain-pop_size; + end +end +assign dbuf_nempty = |dbuf_remain[3:0]; +assign dma_wr_cmd_opd[77:0] = {dma_wr_cmd_opdt[72:0],5'h0}; +NV_NVDLA_RUBIK_wrdma_cmd rbk_dma_wr_cmd_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (dma_wr_cmd_rdy) //|> o + ,.idata_pvld (dma_wr_cmd_vld) //|< i + ,.idata_pd (dma_wr_cmd_pd[77:5]) //|< i + ,.odata_prdy (dma_wr_cmd_ordy) //|< w + ,.odata_pvld (dma_wr_cmd_ovld) //|> w + ,.odata_pd (dma_wr_cmd_opdt[72:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_RUBIK_wrdma_data rbk_dma_wr_datah_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (dma_wr_datah_rdy) //|> w + ,.idata_pvld (dma_wr_datah_vld) //|< w + ,.idata_pd (dma_wr_datah_pd[255:0]) //|< w + ,.odata_prdy (dma_wr_datah_ordy) //|< w + ,.odata_pvld (dma_wr_datah_ovld) //|> w + ,.odata_pd (dma_wr_datah_opd[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +NV_NVDLA_RUBIK_wrdma_data rbk_dma_wr_datal_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idata_prdy (dma_wr_datal_rdy) //|> w + ,.idata_pvld (dma_wr_datal_vld) //|< w + ,.idata_pd (dma_wr_datal_pd[255:0]) //|< w + ,.odata_prdy (dma_wr_datal_ordy) //|< w + ,.odata_pvld (dma_wr_datal_ovld) //|> w + ,.odata_pd (dma_wr_datal_opd[255:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign wr_req_stall_inc = wr_req_vld & !wr_req_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wr_req_stall_inc_d <= 1'b0; + end else begin + wr_req_stall_inc_d <= wr_req_stall_inc; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_done_d <= 1'b0; + end else begin + dp2reg_done_d <= dp2reg_done; + end +end + assign wr_stall_cnt_dec = 1'b0; +// stl adv logic + always @( + wr_req_stall_inc_d + or wr_stall_cnt_dec + ) begin + stl_adv = wr_req_stall_inc_d ^ wr_stall_cnt_dec; + end +// stl cnt logic + always @( + stl_cnt_cur + or wr_req_stall_inc_d + or wr_stall_cnt_dec + or stl_adv + or dp2reg_done_d + ) begin +// VCS sop_coverage_off start + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wr_req_stall_inc_d && !wr_stall_cnt_dec)? stl_cnt_inc : (!wr_req_stall_inc_d && wr_stall_cnt_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (dp2reg_done_d)? 34'd0 : stl_cnt_new[33:0]; +// VCS sop_coverage_off end + end +// stl flops + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_en) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end +// stl output logic + always @( + stl_cnt_cur + ) begin + wr_stall_cnt[31:0] = stl_cnt_cur[31:0]; + end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wr_stall_cnt <= {32{1'b0}}; + end else begin + if (dp2reg_done & ~dp2reg_consumer) + dp2reg_d0_wr_stall_cnt <= wr_stall_cnt; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wr_stall_cnt <= {32{1'b0}}; + end else begin + if (dp2reg_done & dp2reg_consumer) + dp2reg_d1_wr_stall_cnt <= wr_stall_cnt; + end +end +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property rubik_wr_req__wr_request_block__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + wr_req_vld & ~wr_req_rdy; + endproperty +// Cover 0 : "wr_req_vld & ~wr_req_rdy" + FUNCPOINT_rubik_wr_req__wr_request_block__0_COV : cover property (rubik_wr_req__wr_request_block__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_wr_req__wr_req_cmd_after_rf_nempty__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + send_data_done & ~dbuf_nempty; + endproperty +// Cover 1 : "send_data_done & ~dbuf_nempty" + FUNCPOINT_rubik_wr_req__wr_req_cmd_after_rf_nempty__1_COV : cover property (rubik_wr_req__wr_req_cmd_after_rf_nempty__1_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_wr_req__dma_wr_dbuf_fill_half__2_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_data_push & fill_half; + endproperty +// Cover 2 : "dma_wr_data_push & fill_half" + FUNCPOINT_rubik_wr_req__dma_wr_dbuf_fill_half__2_COV : cover property (rubik_wr_req__dma_wr_dbuf_fill_half__2_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property rubik_wr_req__dma_wr_dbuf_send_half__3_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + dma_wr_data_pop & send_half; + endproperty +// Cover 3 : "dma_wr_data_pop & send_half" + FUNCPOINT_rubik_wr_req__dma_wr_dbuf_send_half__3_COV : cover property (rubik_wr_req__dma_wr_dbuf_send_half__3_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_RUBIK_wr_req diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v new file mode 100644 index 0000000..28b56ba --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v @@ -0,0 +1,547 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_wrdma_cmd.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_wrdma_cmd ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +input [72:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [72:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] idata_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 3'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [1:0] idata_adr; // current write address +// spyglass disable_block W484 +// next idata_adr if wr_pushing=1 +wire [1:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] odata_adr; // read address this cycle +wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && idata_pvld; +wire [72:0] odata_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( idata_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( idata_adr ) + , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} ) + , .dout ( odata_pd_p ) + ); +wire [1:0] rd_adr_next_popping = odata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [2:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign odata_pvld_p = odata_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [72:0] odata_pd; // output data register +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + odata_pd <= odata_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + odata_pd <= {73{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_wrdma_cmd") true +// synopsys dc_script_end +endmodule // NV_NVDLA_RUBIK_wrdma_cmd +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [72:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [72:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [72:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [72:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [72:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [72:0] ram_ff0; +reg [72:0] ram_ff1; +reg [72:0] ram_ff2; +reg [72:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [72:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {73{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [72:0] Di0; +input [1:0] Ra0; +output [72:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 73'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [72:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [72:0] Q0 = mem[0]; +wire [72:0] Q1 = mem[1]; +wire [72:0] Q2 = mem[2]; +wire [72:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73] } +endmodule // vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +//vmw: Memory vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +//vmw: Address-size 2 +//vmw: Data-size 73 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[72:0] data0[72:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[72:0] data1[72:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v.vcp new file mode 100644 index 0000000..28b56ba --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v.vcp @@ -0,0 +1,547 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_wrdma_cmd.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_wrdma_cmd ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +input [72:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [72:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + ; +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] idata_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 3'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [1:0] idata_adr; // current write address +// spyglass disable_block W484 +// next idata_adr if wr_pushing=1 +wire [1:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] odata_adr; // read address this cycle +wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && idata_pvld; +wire [72:0] odata_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( idata_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( idata_adr ) + , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} ) + , .dout ( odata_pd_p ) + ); +wire [1:0] rd_adr_next_popping = odata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [2:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign odata_pvld_p = odata_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [72:0] odata_pd; // output data register +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + odata_pd <= odata_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + odata_pd <= {73{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_cmd_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_cmd_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_wrdma_cmd") true +// synopsys dc_script_end +endmodule // NV_NVDLA_RUBIK_wrdma_cmd +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [72:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [72:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [72:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [72:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [72:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [72:0] ram_ff0; +reg [72:0] ram_ff1; +reg [72:0] ram_ff2; +reg [72:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [72:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {73{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [72:0] Di0; +input [1:0] Ra0; +output [72:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 73'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [72:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [72:0] Q0 = mem[0]; +wire [72:0] Q1 = mem[1]; +wire [72:0] Q2 = mem[2]; +wire [72:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73] } +endmodule // vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +//vmw: Memory vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +//vmw: Address-size 2 +//vmw: Data-size 73 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[72:0] data0[72:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[72:0] data1[72:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v new file mode 100644 index 0000000..5a14c37 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v @@ -0,0 +1,783 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_wrdma_data.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_wrdma_data ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld +`ifdef FV_RAND_WR_PAUSE + , idata_pause +`endif + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +`ifdef FV_RAND_WR_PAUSE +input idata_pause; +`endif +input [255:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [255:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || idata_pause ; +`else +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] idata_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 3'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [1:0] idata_adr; // current write address +// spyglass disable_block W484 +// next idata_adr if wr_pushing=1 +wire [1:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] odata_adr; // read address this cycle +wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && idata_pvld; +wire [255:0] odata_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( idata_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( idata_adr ) + , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} ) + , .dout ( odata_pd_p ) + ); +wire [1:0] rd_adr_next_popping = odata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [2:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign odata_pvld_p = odata_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [255:0] odata_pd; // output data register +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + odata_pd <= odata_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + odata_pd <= {256{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_data_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_data_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( idata_pvld && !(!idata_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_wrdma_data") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_RUBIK_wrdma_data +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [255:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [255:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [255:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [255:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [255:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [255:0] ram_ff0; +reg [255:0] ram_ff1; +reg [255:0] ram_ff2; +reg [255:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [255:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {256{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [255:0] Di0; +input [1:0] Ra0; +output [255:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 256'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [255:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [255:0] Q0 = mem[0]; +wire [255:0] Q1 = mem[1]; +wire [255:0] Q2 = mem[2]; +wire [255:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256] } +endmodule // vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +//vmw: Memory vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +//vmw: Address-size 2 +//vmw: Data-size 256 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[255:0] data0[255:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[255:0] data1[255:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v.vcp new file mode 100644 index 0000000..5a14c37 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v.vcp @@ -0,0 +1,783 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_RUBIK_wrdma_data.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_RUBIK_wrdma_data ( + nvdla_core_clk + , nvdla_core_rstn + , idata_prdy + , idata_pvld +`ifdef FV_RAND_WR_PAUSE + , idata_pause +`endif + , idata_pd + , odata_prdy + , odata_pvld + , odata_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output idata_prdy; +input idata_pvld; +`ifdef FV_RAND_WR_PAUSE +input idata_pause; +`endif +input [255:0] idata_pd; +input odata_prdy; +output odata_pvld; +output [255:0] odata_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg idata_pvld_in; // registered idata_pvld +reg wr_busy_in; // inputs being held this cycle? +assign idata_prdy = !wr_busy_in; +wire idata_busy_next; // fwd: fifo busy next? +// factor for better timing with distant idata_pvld signal +wire wr_busy_in_next_wr_req_eq_1 = idata_busy_next; +wire wr_busy_in_next_wr_req_eq_0 = (idata_pvld_in && idata_busy_next) && !wr_reserving; +`ifdef FV_RAND_WR_PAUSE +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) + || idata_pause ; +`else +wire wr_busy_in_next = (idata_pvld? wr_busy_in_next_wr_req_eq_1 : wr_busy_in_next_wr_req_eq_0) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on + ; +`endif +wire wr_busy_in_int; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_pvld_in <= 1'b0; + wr_busy_in <= 1'b0; + end else begin + wr_busy_in <= wr_busy_in_next; + if ( !wr_busy_in_int ) begin + idata_pvld_in <= idata_pvld && !wr_busy_in; + end +//synopsys translate_off + else if ( wr_busy_in_int ) begin + end else begin + idata_pvld_in <= `x_or_0; + end +//synopsys translate_on + end +end +reg idata_busy_int; // copy for internal use +assign wr_reserving = idata_pvld_in && !idata_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] idata_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? idata_count : (idata_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (idata_count + 1'd1) : idata_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +assign idata_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check idata_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +assign wr_busy_in_int = idata_pvld_in && idata_busy_int; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_busy_int <= 1'b0; + idata_count <= 3'd0; + end else begin + idata_busy_int <= idata_busy_next; + if ( wr_reserving ^ wr_popping ) begin + idata_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + idata_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as idata_pvld_in +// +// RAM +// +reg [1:0] idata_adr; // current write address +// spyglass disable_block W484 +// next idata_adr if wr_pushing=1 +wire [1:0] wr_adr_next = idata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + idata_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + idata_adr <= wr_adr_next; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] odata_adr; // read address this cycle +wire ram_we = wr_pushing && (idata_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire ram_iwe = !wr_busy_in && idata_pvld; +wire [255:0] odata_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 ram ( + .clk( nvdla_core_clk ) + , .clk_mgated( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( idata_pd ) + , .iwe ( ram_iwe ) + , .we ( ram_we ) + , .wa ( idata_adr ) + , .ra ( (idata_count == 0) ? 3'd4 : {1'b0,odata_adr} ) + , .dout ( odata_pd_p ) + ); +wire [1:0] rd_adr_next_popping = odata_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + odata_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + odata_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire odata_pvld_p; // data out of fifo is valid +reg odata_pvld_int; // internal copy of odata_pvld +assign odata_pvld = odata_pvld_int; +assign rd_popping = odata_pvld_p && !(odata_pvld_int && !odata_prdy); +reg [2:0] odata_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? odata_count_p : + (odata_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (odata_count_p + 1'd1) : + odata_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign odata_pvld_p = odata_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + odata_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + odata_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +reg [255:0] odata_pd; // output data register +wire rd_req_next = (odata_pvld_p || (odata_pvld_int && !odata_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + odata_pvld_int <= 1'b0; + end else begin + odata_pvld_int <= rd_req_next; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + odata_pd <= odata_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + odata_pd <= {256{`x_or_0}}; + end +//synopsys translate_on +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (idata_pvld_in && !idata_busy_int) || (idata_busy_int != idata_busy_next)) || (rd_pushing || rd_popping || (odata_pvld_int && odata_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_data_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_RUBIK_wrdma_data_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_RUBIK_wrdma_data_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( idata_pvld && !(!idata_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, idata_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_RUBIK_wrdma_data") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_RUBIK_wrdma_data +// +// Flop-Based RAM (with internal wr_reg) +// +module NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 ( + clk + , clk_mgated + , pwrbus_ram_pd + , di + , iwe + , we + , wa + , ra + , dout + ); +input clk; // write clock +input clk_mgated; // write clock mgated +input [31 : 0] pwrbus_ram_pd; +input [255:0] di; +input iwe; +input we; +input [1:0] wa; +input [2:0] ra; +output [255:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +reg [255:0] di_d; // -wr_reg +always @( posedge clk ) begin + if ( iwe ) begin + di_d <= di; // -wr_reg + end +end +`ifdef EMU +wire [255:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [255:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di_d; +end +vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di_d : dout_p; +`else +reg [255:0] ram_ff0; +reg [255:0] ram_ff1; +reg [255:0] ram_ff2; +reg [255:0] ram_ff3; +always @( posedge clk_mgated ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di_d; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di_d; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di_d; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di_d; + end +end +reg [255:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di_d; +//VCS coverage off + default: dout = {256{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [255:0] Di0; +input [1:0] Ra0; +output [255:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 256'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [255:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [255:0] Q0 = mem[0]; +wire [255:0] Q1 = mem[1]; +wire [255:0] Q2 = mem[2]; +wire [255:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256] } +endmodule // vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +//vmw: Memory vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +//vmw: Address-size 2 +//vmw: Data-size 256 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[255:0] data0[255:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[255:0] data1[255:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_rubik.v b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_rubik.v new file mode 100644 index 0000000..8770534 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_rubik.v @@ -0,0 +1,399 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_rubik.v +module NV_NVDLA_rubik ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2rbk_req_pvld //|< i + ,csb2rbk_req_prdy //|> o + ,csb2rbk_req_pd //|< i + ,rbk2csb_resp_valid //|> o + ,rbk2csb_resp_pd //|> o + ,pwrbus_ram_pd //|< i + ,rbk2mcif_rd_req_valid //|> o + ,rbk2mcif_rd_req_ready //|< i + ,rbk2mcif_rd_req_pd //|> o + ,mcif2rbk_rd_rsp_valid //|< i + ,mcif2rbk_rd_rsp_ready //|> o + ,mcif2rbk_rd_rsp_pd //|< i + ,rbk2mcif_wr_req_valid //|> o + ,rbk2mcif_wr_req_ready //|< i + ,rbk2mcif_wr_req_pd //|> o + ,mcif2rbk_wr_rsp_complete //|< i + ,rbk2mcif_rd_cdt_lat_fifo_pop //|> o + ,rubik2glb_done_intr_pd //|> o + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ); +// +// NV_NVDLA_rubik_ports.v +// +input nvdla_core_clk; /* csb2rbk_req, rbk2csb_resp, rbk2mcif_rd_req, rbk2cvif_rd_req, mcif2rbk_rd_rsp, cvif2rbk_rd_rsp, rbk2mcif_wr_req, mcif2rbk_wr_rsp, rbk2cvif_wr_req, cvif2rbk_wr_rsp, rbk2mcif_rd_cdt, rbk2cvif_rd_cdt, rubik2glb_done_intr */ +input nvdla_core_rstn; /* csb2rbk_req, rbk2csb_resp, rbk2mcif_rd_req, rbk2cvif_rd_req, mcif2rbk_rd_rsp, cvif2rbk_rd_rsp, rbk2mcif_wr_req, mcif2rbk_wr_rsp, rbk2cvif_wr_req, cvif2rbk_wr_rsp, rbk2mcif_rd_cdt, rbk2cvif_rd_cdt, rubik2glb_done_intr */ +input csb2rbk_req_pvld; /* data valid */ +output csb2rbk_req_prdy; /* data return handshake */ +input [62:0] csb2rbk_req_pd; +output rbk2csb_resp_valid; /* data valid */ +output [33:0] rbk2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [31:0] pwrbus_ram_pd; +output rbk2mcif_rd_req_valid; /* data valid */ +input rbk2mcif_rd_req_ready; /* data return handshake */ +output [78:0] rbk2mcif_rd_req_pd; +input mcif2rbk_rd_rsp_valid; /* data valid */ +output mcif2rbk_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2rbk_rd_rsp_pd; +output rbk2mcif_wr_req_valid; /* data valid */ +input rbk2mcif_wr_req_ready; /* data return handshake */ +output [514:0] rbk2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ +input mcif2rbk_wr_rsp_complete; +output rbk2mcif_rd_cdt_lat_fifo_pop; +output [1:0] rubik2glb_done_intr_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +//&Ports /^obs_bus/; +wire contract_lit_dx; +wire [511:0] data_fifo_pd; +wire data_fifo_rdy; +wire data_fifo_vld; +wire [77:0] dma_wr_cmd_pd; +wire dma_wr_cmd_rdy; +wire dma_wr_cmd_vld; +wire [513:0] dma_wr_data_pd; +wire dma_wr_data_rdy; +wire dma_wr_data_vld; +wire dp2reg_consumer; +wire [31:0] dp2reg_d0_rd_stall_cnt; +wire [31:0] dp2reg_d0_wr_stall_cnt; +wire [31:0] dp2reg_d1_rd_stall_cnt; +wire [31:0] dp2reg_d1_wr_stall_cnt; +wire dp2reg_done; +wire [13:0] inwidth; +wire nvdla_op_gated_clk_0; +wire nvdla_op_gated_clk_1; +wire nvdla_op_gated_clk_2; +wire rd_cdt_lat_fifo_pop; +wire [78:0] rd_req_pd; +wire rd_req_rdy; +wire rd_req_type; +wire rd_req_vld; +wire [513:0] rd_rsp_pd; +wire rd_rsp_rdy; +wire rd_rsp_vld; +wire [26:0] reg2dp_contract_stride_0; +wire [26:0] reg2dp_contract_stride_1; +wire [31:0] reg2dp_dain_addr_high; +wire [26:0] reg2dp_dain_addr_low; +wire [26:0] reg2dp_dain_line_stride; +wire [26:0] reg2dp_dain_planar_stride; +wire [26:0] reg2dp_dain_surf_stride; +wire [31:0] reg2dp_daout_addr_high; +wire [26:0] reg2dp_daout_addr_low; +wire [26:0] reg2dp_daout_line_stride; +wire [26:0] reg2dp_daout_planar_stride; +wire [26:0] reg2dp_daout_surf_stride; +wire [12:0] reg2dp_datain_channel; +wire [12:0] reg2dp_datain_height; +wire reg2dp_datain_ram_type; +wire [12:0] reg2dp_datain_width; +wire [12:0] reg2dp_dataout_channel; +wire reg2dp_dataout_ram_type; +wire [4:0] reg2dp_deconv_x_stride; +wire [4:0] reg2dp_deconv_y_stride; +wire [1:0] reg2dp_in_precision; +wire reg2dp_op_en; +wire reg2dp_perf_en; +wire [1:0] reg2dp_rubik_mode; +wire [4:0] rf_rd_addr; +wire [11:0] rf_rd_cmd_pd; +wire rf_rd_cmd_rdy; +wire rf_rd_cmd_vld; +wire rf_rd_done; +wire [11:0] rf_rd_mask; +wire rf_rd_rdy; +wire rf_rd_vld; +wire [4:0] rf_wr_addr; +wire [10:0] rf_wr_cmd_pd; +wire rf_wr_cmd_rdy; +wire rf_wr_cmd_vld; +wire [511:0] rf_wr_data; +wire rf_wr_done; +wire rf_wr_rdy; +wire rf_wr_vld; +wire [2:0] slcg_op_en; +wire [514:0] wr_req_pd; +wire wr_req_rdy; +wire wr_req_type; +wire wr_req_vld; +wire wr_rsp_complete; +wire [1:0] cfg_reg2dp_rubik_mode; +assign reg2dp_rubik_mode[1:0] = cfg_reg2dp_rubik_mode[1:0]; +assign reg2dp_in_precision[1:0] = 2'b0; +NV_NVDLA_RUBIK_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2rbk_req_pd (csb2rbk_req_pd[62:0]) //|< i + ,.csb2rbk_req_pvld (csb2rbk_req_pvld) //|< i + ,.dp2reg_d0_rd_stall_cnt (dp2reg_d0_rd_stall_cnt[31:0]) //|< w + ,.dp2reg_d0_wr_stall_cnt (dp2reg_d0_wr_stall_cnt[31:0]) //|< w + ,.dp2reg_d1_rd_stall_cnt (dp2reg_d1_rd_stall_cnt[31:0]) //|< w + ,.dp2reg_d1_wr_stall_cnt (dp2reg_d1_wr_stall_cnt[31:0]) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.csb2rbk_req_prdy (csb2rbk_req_prdy) //|> o + ,.dp2reg_consumer (dp2reg_consumer) //|> w + ,.rbk2csb_resp_pd (rbk2csb_resp_pd[33:0]) //|> o + ,.rbk2csb_resp_valid (rbk2csb_resp_valid) //|> o + ,.reg2dp_contract_stride_0 (reg2dp_contract_stride_0[26:0]) //|> w + ,.reg2dp_contract_stride_1 (reg2dp_contract_stride_1[26:0]) //|> w + ,.reg2dp_dain_addr_high (reg2dp_dain_addr_high[31:0]) //|> w + ,.reg2dp_dain_addr_low (reg2dp_dain_addr_low[26:0]) //|> w + ,.reg2dp_dain_line_stride (reg2dp_dain_line_stride[26:0]) //|> w + ,.reg2dp_dain_planar_stride (reg2dp_dain_planar_stride[26:0]) //|> w + ,.reg2dp_dain_surf_stride (reg2dp_dain_surf_stride[26:0]) //|> w + ,.reg2dp_daout_addr_high (reg2dp_daout_addr_high[31:0]) //|> w + ,.reg2dp_daout_addr_low (reg2dp_daout_addr_low[26:0]) //|> w + ,.reg2dp_daout_line_stride (reg2dp_daout_line_stride[26:0]) //|> w + ,.reg2dp_daout_planar_stride (reg2dp_daout_planar_stride[26:0]) //|> w + ,.reg2dp_daout_surf_stride (reg2dp_daout_surf_stride[26:0]) //|> w + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) //|> w + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) //|> w + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type) //|> w + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) //|> w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel[12:0]) //|> w + ,.reg2dp_dataout_ram_type (reg2dp_dataout_ram_type) //|> w + ,.reg2dp_deconv_x_stride (reg2dp_deconv_x_stride[4:0]) //|> w + ,.reg2dp_deconv_y_stride (reg2dp_deconv_y_stride[4:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_perf_en (reg2dp_perf_en) //|> w + ,.reg2dp_rubik_mode (cfg_reg2dp_rubik_mode[1:0]) //|> w + ,.slcg_op_en (slcg_op_en[2:0]) //|> w + ); +NV_NVDLA_RUBIK_intr u_intr ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_consumer (dp2reg_consumer) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_op_en (reg2dp_op_en) //|< w + ,.wr_rsp_complete (wr_rsp_complete) //|< w + ,.rubik2glb_done_intr_pd (rubik2glb_done_intr_pd[1:0]) //|> o + ); +NV_NVDLA_RUBIK_dma u_dma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2rbk_rd_rsp_pd (mcif2rbk_rd_rsp_pd[513:0]) //|< i + ,.mcif2rbk_rd_rsp_valid (mcif2rbk_rd_rsp_valid) //|< i + ,.mcif2rbk_wr_rsp_complete (mcif2rbk_wr_rsp_complete) //|< i + ,.rbk2mcif_rd_req_ready (rbk2mcif_rd_req_ready) //|< i + ,.rbk2mcif_wr_req_ready (rbk2mcif_wr_req_ready) //|< i + ,.rd_cdt_lat_fifo_pop (rd_cdt_lat_fifo_pop) //|< w + ,.rd_req_pd (rd_req_pd[78:0]) //|< w + ,.rd_req_type (rd_req_type) //|< w + ,.rd_req_vld (rd_req_vld) //|< w + ,.rd_rsp_rdy (rd_rsp_rdy) //|< w + ,.wr_req_pd (wr_req_pd[514:0]) //|< w + ,.wr_req_type (wr_req_type) //|< w + ,.wr_req_vld (wr_req_vld) //|< w + ,.mcif2rbk_rd_rsp_ready (mcif2rbk_rd_rsp_ready) //|> o + ,.rbk2mcif_rd_cdt_lat_fifo_pop (rbk2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.rbk2mcif_rd_req_pd (rbk2mcif_rd_req_pd[78:0]) //|> o + ,.rbk2mcif_rd_req_valid (rbk2mcif_rd_req_valid) //|> o + ,.rbk2mcif_wr_req_pd (rbk2mcif_wr_req_pd[514:0]) //|> o + ,.rbk2mcif_wr_req_valid (rbk2mcif_wr_req_valid) //|> o + ,.rd_req_rdy (rd_req_rdy) //|> w + ,.rd_rsp_pd (rd_rsp_pd[513:0]) //|> w + ,.rd_rsp_vld (rd_rsp_vld) //|> w + ,.wr_req_rdy (wr_req_rdy) //|> w + ,.wr_rsp_complete (wr_rsp_complete) //|> w + ); +NV_NVDLA_RUBIK_seq_gen u_seq_gen ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_consumer (dp2reg_consumer) //|< w + ,.reg2dp_perf_en (reg2dp_perf_en) //|< w + ,.dp2reg_d0_rd_stall_cnt (dp2reg_d0_rd_stall_cnt[31:0]) //|> w + ,.dp2reg_d1_rd_stall_cnt (dp2reg_d1_rd_stall_cnt[31:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type) //|< w + ,.reg2dp_rubik_mode (reg2dp_rubik_mode[1:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_dain_addr_high (reg2dp_dain_addr_high[31:0]) //|< w + ,.reg2dp_dain_addr_low (reg2dp_dain_addr_low[26:0]) //|< w + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) //|< w + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) //|< w + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) //|< w + ,.reg2dp_deconv_x_stride (reg2dp_deconv_x_stride[4:0]) //|< w + ,.reg2dp_deconv_y_stride (reg2dp_deconv_y_stride[4:0]) //|< w + ,.reg2dp_dain_line_stride (reg2dp_dain_line_stride[26:0]) //|< w + ,.reg2dp_dain_planar_stride (reg2dp_dain_planar_stride[26:0]) //|< w + ,.reg2dp_dain_surf_stride (reg2dp_dain_surf_stride[26:0]) //|< w + ,.reg2dp_contract_stride_0 (reg2dp_contract_stride_0[26:0]) //|< w + ,.reg2dp_contract_stride_1 (reg2dp_contract_stride_1[26:0]) //|< w + ,.reg2dp_daout_addr_high (reg2dp_daout_addr_high[31:0]) //|< w + ,.reg2dp_daout_addr_low (reg2dp_daout_addr_low[26:0]) //|< w + ,.reg2dp_daout_line_stride (reg2dp_daout_line_stride[26:0]) //|< w + ,.reg2dp_daout_planar_stride (reg2dp_daout_planar_stride[26:0]) //|< w + ,.reg2dp_daout_surf_stride (reg2dp_daout_surf_stride[26:0]) //|< w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel[12:0]) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.rd_req_type (rd_req_type) //|> w + ,.rd_req_vld (rd_req_vld) //|> w + ,.rd_req_rdy (rd_req_rdy) //|< w + ,.rd_req_pd (rd_req_pd[78:0]) //|> w + ,.rf_wr_cmd_vld (rf_wr_cmd_vld) //|> w + ,.rf_wr_cmd_rdy (rf_wr_cmd_rdy) //|< w + ,.rf_wr_cmd_pd (rf_wr_cmd_pd[10:0]) //|> w + ,.rf_rd_cmd_vld (rf_rd_cmd_vld) //|> w + ,.rf_rd_cmd_rdy (rf_rd_cmd_rdy) //|< w + ,.rf_rd_cmd_pd (rf_rd_cmd_pd[11:0]) //|> w + ,.dma_wr_cmd_vld (dma_wr_cmd_vld) //|> w + ,.dma_wr_cmd_rdy (dma_wr_cmd_rdy) //|< w + ,.dma_wr_cmd_pd (dma_wr_cmd_pd[77:0]) //|> w + ,.contract_lit_dx (contract_lit_dx) //|> w + ,.inwidth (inwidth[13:0]) //|> w + ); +NV_NVDLA_RUBIK_wr_req u_wr_req ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_consumer (dp2reg_consumer) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_dataout_ram_type (reg2dp_dataout_ram_type) //|< w + ,.reg2dp_perf_en (reg2dp_perf_en) //|< w + ,.dp2reg_d0_wr_stall_cnt (dp2reg_d0_wr_stall_cnt[31:0]) //|> w + ,.dp2reg_d1_wr_stall_cnt (dp2reg_d1_wr_stall_cnt[31:0]) //|> w + ,.wr_req_type (wr_req_type) //|> w + ,.wr_req_vld (wr_req_vld) //|> w + ,.wr_req_pd (wr_req_pd[514:0]) //|> w + ,.wr_req_rdy (wr_req_rdy) //|< w + ,.dma_wr_cmd_vld (dma_wr_cmd_vld) //|< w + ,.dma_wr_cmd_pd (dma_wr_cmd_pd[77:0]) //|< w + ,.dma_wr_cmd_rdy (dma_wr_cmd_rdy) //|> w + ,.dma_wr_data_vld (dma_wr_data_vld) //|< w + ,.dma_wr_data_pd (dma_wr_data_pd[513:0]) //|< w + ,.dma_wr_data_rdy (dma_wr_data_rdy) //|> w + ,.dp2reg_done (dp2reg_done) //|> w + ); +NV_NVDLA_RUBIK_rf_ctrl u_rf_ctrl ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.contract_lit_dx (contract_lit_dx) //|< w + ,.inwidth (inwidth[13:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.rf_wr_cmd_vld (rf_wr_cmd_vld) //|< w + ,.rf_wr_cmd_pd (rf_wr_cmd_pd[10:0]) //|< w + ,.rf_wr_cmd_rdy (rf_wr_cmd_rdy) //|> w + ,.rf_rd_cmd_vld (rf_rd_cmd_vld) //|< w + ,.rf_rd_cmd_pd (rf_rd_cmd_pd[11:0]) //|< w + ,.rf_rd_cmd_rdy (rf_rd_cmd_rdy) //|> w + ,.data_fifo_vld (data_fifo_vld) //|< w + ,.data_fifo_pd (data_fifo_pd[511:0]) //|< w + ,.data_fifo_rdy (data_fifo_rdy) //|> w + ,.rf_wr_vld (rf_wr_vld) //|> w + ,.rf_wr_done (rf_wr_done) //|> w + ,.rf_wr_addr (rf_wr_addr[4:0]) //|> w + ,.rf_wr_data (rf_wr_data[511:0]) //|> w + ,.rf_wr_rdy (rf_wr_rdy) //|< w + ,.rf_rd_vld (rf_rd_vld) //|> w + ,.rf_rd_done (rf_rd_done) //|> w + ,.rf_rd_mask (rf_rd_mask[11:0]) //|> w + ,.rf_rd_addr (rf_rd_addr[4:0]) //|> w + ,.rf_rd_rdy (rf_rd_rdy) //|< w + ,.reg2dp_rubik_mode (reg2dp_rubik_mode[1:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ); +NV_NVDLA_RUBIK_dr2drc u_dr2drc ( + .nvdla_core_clk (nvdla_op_gated_clk_1) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.rd_rsp_vld (rd_rsp_vld) //|< w + ,.rd_rsp_pd (rd_rsp_pd[513:0]) //|< w + ,.rd_rsp_rdy (rd_rsp_rdy) //|> w + ,.rd_cdt_lat_fifo_pop (rd_cdt_lat_fifo_pop) //|> w + ,.data_fifo_vld (data_fifo_vld) //|> w + ,.data_fifo_pd (data_fifo_pd[511:0]) //|> w + ,.data_fifo_rdy (data_fifo_rdy) //|< w + ); +NV_NVDLA_RUBIK_rf_core u_rf_core ( + .nvdla_core_clk (nvdla_op_gated_clk_2) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.rf_wr_vld (rf_wr_vld) //|< w + ,.rf_wr_done (rf_wr_done) //|< w + ,.rf_wr_addr (rf_wr_addr[4:0]) //|< w + ,.rf_wr_data (rf_wr_data[511:0]) //|< w + ,.rf_wr_rdy (rf_wr_rdy) //|> w + ,.rf_rd_vld (rf_rd_vld) //|< w + ,.rf_rd_done (rf_rd_done) //|< w + ,.rf_rd_addr (rf_rd_addr[4:0]) //|< w + ,.rf_rd_mask (rf_rd_mask[11:0]) //|< w + ,.rf_rd_rdy (rf_rd_rdy) //|> w + ,.dma_wr_data_vld (dma_wr_data_vld) //|> w + ,.dma_wr_data_pd (dma_wr_data_pd[513:0]) //|> w + ,.dma_wr_data_rdy (dma_wr_data_rdy) //|< w + ,.reg2dp_rubik_mode (reg2dp_rubik_mode[1:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ); +//Insert SLCG groups +NV_NVDLA_RUBIK_slcg u_slcg_op_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.enable (slcg_op_en[0]) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w + ); +NV_NVDLA_RUBIK_slcg u_slcg_op_1 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.enable (slcg_op_en[1]) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w + ); +NV_NVDLA_RUBIK_slcg u_slcg_op_2 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.enable (slcg_op_en[2]) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w + ); +/////////////////obs bus/////////////////// +//assign obs_bus_rubik_rd_req_vld = rd_req_vld ; +//assign obs_bus_rubik_rd_req_rdy = rd_req_rdy ; +//assign obs_bus_rubik_rd_req_done = rd_req_done ; +//assign obs_bus_rubik_dma_wr_cmd_vld = dma_wr_cmd_vld ; +//assign obs_bus_rubik_dma_wr_cmd_rdy = dma_wr_cmd_rdy ; +//assign obs_bus_rubik_rf_wcmd_vld = rf_wr_cmd_vld ; +//assign obs_bus_rubik_rf_wcmd_rdy = rf_wr_cmd_rdy ; +//assign obs_bus_rubik_rf_wcmd_pd = rf_wr_cmd_pd ; +//assign obs_bus_rubik_rf_rcmd_vld = rf_rd_cmd_vld ; +//assign obs_bus_rubik_rf_rcmd_rdy = rf_rd_cmd_rdy ; +//assign obs_bus_rubik_rf_rcmd_pd = rf_rd_cmd_pd ; +// +//assign obs_bus_rubik_rf_wr_vld = rf_wr_vld; +//assign obs_bus_rubik_rf_wr_rdy = rf_wr_rdy; +//assign obs_bus_rubik_rf_wr_done = rf_wr_done; +//assign obs_bus_rubik_rf_wr_addr = rf_wr_addr; +//assign obs_bus_rubik_rf_rd_vld = rf_rd_vld; +//assign obs_bus_rubik_rf_rd_rdy = rf_rd_rdy; +//assign obs_bus_rubik_rf_rd_done = rf_rd_done; +//assign obs_bus_rubik_rf_rd_addr = rf_rd_addr; +//assign obs_bus_rubik_rf_rd_mask = rf_rd_mask; +//assign obs_bus_rubik_dma_wr_data_vld = dma_wr_data_vld; +//assign obs_bus_rubik_dma_wr_data_rdy = dma_wr_data_rdy; +// +//assign obs_bus_rubik_wr_req_vld = wr_req_vld; +//assign obs_bus_rubik_wr_req_rdy = wr_req_rdy; +//assign obs_bus_rubik_wr_req_done = dp2reg_done; +//assign obs_bus_rubik_wr_rsp_complete = wr_rsp_complete; +endmodule // NV_NVDLA_rubik diff --git a/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_rubik.v.vcp b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_rubik.v.vcp new file mode 100644 index 0000000..8770534 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/rubik/NV_NVDLA_rubik.v.vcp @@ -0,0 +1,399 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_rubik.v +module NV_NVDLA_rubik ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2rbk_req_pvld //|< i + ,csb2rbk_req_prdy //|> o + ,csb2rbk_req_pd //|< i + ,rbk2csb_resp_valid //|> o + ,rbk2csb_resp_pd //|> o + ,pwrbus_ram_pd //|< i + ,rbk2mcif_rd_req_valid //|> o + ,rbk2mcif_rd_req_ready //|< i + ,rbk2mcif_rd_req_pd //|> o + ,mcif2rbk_rd_rsp_valid //|< i + ,mcif2rbk_rd_rsp_ready //|> o + ,mcif2rbk_rd_rsp_pd //|< i + ,rbk2mcif_wr_req_valid //|> o + ,rbk2mcif_wr_req_ready //|< i + ,rbk2mcif_wr_req_pd //|> o + ,mcif2rbk_wr_rsp_complete //|< i + ,rbk2mcif_rd_cdt_lat_fifo_pop //|> o + ,rubik2glb_done_intr_pd //|> o + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ); +// +// NV_NVDLA_rubik_ports.v +// +input nvdla_core_clk; /* csb2rbk_req, rbk2csb_resp, rbk2mcif_rd_req, rbk2cvif_rd_req, mcif2rbk_rd_rsp, cvif2rbk_rd_rsp, rbk2mcif_wr_req, mcif2rbk_wr_rsp, rbk2cvif_wr_req, cvif2rbk_wr_rsp, rbk2mcif_rd_cdt, rbk2cvif_rd_cdt, rubik2glb_done_intr */ +input nvdla_core_rstn; /* csb2rbk_req, rbk2csb_resp, rbk2mcif_rd_req, rbk2cvif_rd_req, mcif2rbk_rd_rsp, cvif2rbk_rd_rsp, rbk2mcif_wr_req, mcif2rbk_wr_rsp, rbk2cvif_wr_req, cvif2rbk_wr_rsp, rbk2mcif_rd_cdt, rbk2cvif_rd_cdt, rubik2glb_done_intr */ +input csb2rbk_req_pvld; /* data valid */ +output csb2rbk_req_prdy; /* data return handshake */ +input [62:0] csb2rbk_req_pd; +output rbk2csb_resp_valid; /* data valid */ +output [33:0] rbk2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [31:0] pwrbus_ram_pd; +output rbk2mcif_rd_req_valid; /* data valid */ +input rbk2mcif_rd_req_ready; /* data return handshake */ +output [78:0] rbk2mcif_rd_req_pd; +input mcif2rbk_rd_rsp_valid; /* data valid */ +output mcif2rbk_rd_rsp_ready; /* data return handshake */ +input [513:0] mcif2rbk_rd_rsp_pd; +output rbk2mcif_wr_req_valid; /* data valid */ +input rbk2mcif_wr_req_ready; /* data return handshake */ +output [514:0] rbk2mcif_wr_req_pd; /* pkt_id_width=1 pkt_widths=78,514 */ +input mcif2rbk_wr_rsp_complete; +output rbk2mcif_rd_cdt_lat_fifo_pop; +output [1:0] rubik2glb_done_intr_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +//&Ports /^obs_bus/; +wire contract_lit_dx; +wire [511:0] data_fifo_pd; +wire data_fifo_rdy; +wire data_fifo_vld; +wire [77:0] dma_wr_cmd_pd; +wire dma_wr_cmd_rdy; +wire dma_wr_cmd_vld; +wire [513:0] dma_wr_data_pd; +wire dma_wr_data_rdy; +wire dma_wr_data_vld; +wire dp2reg_consumer; +wire [31:0] dp2reg_d0_rd_stall_cnt; +wire [31:0] dp2reg_d0_wr_stall_cnt; +wire [31:0] dp2reg_d1_rd_stall_cnt; +wire [31:0] dp2reg_d1_wr_stall_cnt; +wire dp2reg_done; +wire [13:0] inwidth; +wire nvdla_op_gated_clk_0; +wire nvdla_op_gated_clk_1; +wire nvdla_op_gated_clk_2; +wire rd_cdt_lat_fifo_pop; +wire [78:0] rd_req_pd; +wire rd_req_rdy; +wire rd_req_type; +wire rd_req_vld; +wire [513:0] rd_rsp_pd; +wire rd_rsp_rdy; +wire rd_rsp_vld; +wire [26:0] reg2dp_contract_stride_0; +wire [26:0] reg2dp_contract_stride_1; +wire [31:0] reg2dp_dain_addr_high; +wire [26:0] reg2dp_dain_addr_low; +wire [26:0] reg2dp_dain_line_stride; +wire [26:0] reg2dp_dain_planar_stride; +wire [26:0] reg2dp_dain_surf_stride; +wire [31:0] reg2dp_daout_addr_high; +wire [26:0] reg2dp_daout_addr_low; +wire [26:0] reg2dp_daout_line_stride; +wire [26:0] reg2dp_daout_planar_stride; +wire [26:0] reg2dp_daout_surf_stride; +wire [12:0] reg2dp_datain_channel; +wire [12:0] reg2dp_datain_height; +wire reg2dp_datain_ram_type; +wire [12:0] reg2dp_datain_width; +wire [12:0] reg2dp_dataout_channel; +wire reg2dp_dataout_ram_type; +wire [4:0] reg2dp_deconv_x_stride; +wire [4:0] reg2dp_deconv_y_stride; +wire [1:0] reg2dp_in_precision; +wire reg2dp_op_en; +wire reg2dp_perf_en; +wire [1:0] reg2dp_rubik_mode; +wire [4:0] rf_rd_addr; +wire [11:0] rf_rd_cmd_pd; +wire rf_rd_cmd_rdy; +wire rf_rd_cmd_vld; +wire rf_rd_done; +wire [11:0] rf_rd_mask; +wire rf_rd_rdy; +wire rf_rd_vld; +wire [4:0] rf_wr_addr; +wire [10:0] rf_wr_cmd_pd; +wire rf_wr_cmd_rdy; +wire rf_wr_cmd_vld; +wire [511:0] rf_wr_data; +wire rf_wr_done; +wire rf_wr_rdy; +wire rf_wr_vld; +wire [2:0] slcg_op_en; +wire [514:0] wr_req_pd; +wire wr_req_rdy; +wire wr_req_type; +wire wr_req_vld; +wire wr_rsp_complete; +wire [1:0] cfg_reg2dp_rubik_mode; +assign reg2dp_rubik_mode[1:0] = cfg_reg2dp_rubik_mode[1:0]; +assign reg2dp_in_precision[1:0] = 2'b0; +NV_NVDLA_RUBIK_regfile u_regfile ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2rbk_req_pd (csb2rbk_req_pd[62:0]) //|< i + ,.csb2rbk_req_pvld (csb2rbk_req_pvld) //|< i + ,.dp2reg_d0_rd_stall_cnt (dp2reg_d0_rd_stall_cnt[31:0]) //|< w + ,.dp2reg_d0_wr_stall_cnt (dp2reg_d0_wr_stall_cnt[31:0]) //|< w + ,.dp2reg_d1_rd_stall_cnt (dp2reg_d1_rd_stall_cnt[31:0]) //|< w + ,.dp2reg_d1_wr_stall_cnt (dp2reg_d1_wr_stall_cnt[31:0]) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.csb2rbk_req_prdy (csb2rbk_req_prdy) //|> o + ,.dp2reg_consumer (dp2reg_consumer) //|> w + ,.rbk2csb_resp_pd (rbk2csb_resp_pd[33:0]) //|> o + ,.rbk2csb_resp_valid (rbk2csb_resp_valid) //|> o + ,.reg2dp_contract_stride_0 (reg2dp_contract_stride_0[26:0]) //|> w + ,.reg2dp_contract_stride_1 (reg2dp_contract_stride_1[26:0]) //|> w + ,.reg2dp_dain_addr_high (reg2dp_dain_addr_high[31:0]) //|> w + ,.reg2dp_dain_addr_low (reg2dp_dain_addr_low[26:0]) //|> w + ,.reg2dp_dain_line_stride (reg2dp_dain_line_stride[26:0]) //|> w + ,.reg2dp_dain_planar_stride (reg2dp_dain_planar_stride[26:0]) //|> w + ,.reg2dp_dain_surf_stride (reg2dp_dain_surf_stride[26:0]) //|> w + ,.reg2dp_daout_addr_high (reg2dp_daout_addr_high[31:0]) //|> w + ,.reg2dp_daout_addr_low (reg2dp_daout_addr_low[26:0]) //|> w + ,.reg2dp_daout_line_stride (reg2dp_daout_line_stride[26:0]) //|> w + ,.reg2dp_daout_planar_stride (reg2dp_daout_planar_stride[26:0]) //|> w + ,.reg2dp_daout_surf_stride (reg2dp_daout_surf_stride[26:0]) //|> w + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) //|> w + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) //|> w + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type) //|> w + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) //|> w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel[12:0]) //|> w + ,.reg2dp_dataout_ram_type (reg2dp_dataout_ram_type) //|> w + ,.reg2dp_deconv_x_stride (reg2dp_deconv_x_stride[4:0]) //|> w + ,.reg2dp_deconv_y_stride (reg2dp_deconv_y_stride[4:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_perf_en (reg2dp_perf_en) //|> w + ,.reg2dp_rubik_mode (cfg_reg2dp_rubik_mode[1:0]) //|> w + ,.slcg_op_en (slcg_op_en[2:0]) //|> w + ); +NV_NVDLA_RUBIK_intr u_intr ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_consumer (dp2reg_consumer) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_op_en (reg2dp_op_en) //|< w + ,.wr_rsp_complete (wr_rsp_complete) //|< w + ,.rubik2glb_done_intr_pd (rubik2glb_done_intr_pd[1:0]) //|> o + ); +NV_NVDLA_RUBIK_dma u_dma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mcif2rbk_rd_rsp_pd (mcif2rbk_rd_rsp_pd[513:0]) //|< i + ,.mcif2rbk_rd_rsp_valid (mcif2rbk_rd_rsp_valid) //|< i + ,.mcif2rbk_wr_rsp_complete (mcif2rbk_wr_rsp_complete) //|< i + ,.rbk2mcif_rd_req_ready (rbk2mcif_rd_req_ready) //|< i + ,.rbk2mcif_wr_req_ready (rbk2mcif_wr_req_ready) //|< i + ,.rd_cdt_lat_fifo_pop (rd_cdt_lat_fifo_pop) //|< w + ,.rd_req_pd (rd_req_pd[78:0]) //|< w + ,.rd_req_type (rd_req_type) //|< w + ,.rd_req_vld (rd_req_vld) //|< w + ,.rd_rsp_rdy (rd_rsp_rdy) //|< w + ,.wr_req_pd (wr_req_pd[514:0]) //|< w + ,.wr_req_type (wr_req_type) //|< w + ,.wr_req_vld (wr_req_vld) //|< w + ,.mcif2rbk_rd_rsp_ready (mcif2rbk_rd_rsp_ready) //|> o + ,.rbk2mcif_rd_cdt_lat_fifo_pop (rbk2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.rbk2mcif_rd_req_pd (rbk2mcif_rd_req_pd[78:0]) //|> o + ,.rbk2mcif_rd_req_valid (rbk2mcif_rd_req_valid) //|> o + ,.rbk2mcif_wr_req_pd (rbk2mcif_wr_req_pd[514:0]) //|> o + ,.rbk2mcif_wr_req_valid (rbk2mcif_wr_req_valid) //|> o + ,.rd_req_rdy (rd_req_rdy) //|> w + ,.rd_rsp_pd (rd_rsp_pd[513:0]) //|> w + ,.rd_rsp_vld (rd_rsp_vld) //|> w + ,.wr_req_rdy (wr_req_rdy) //|> w + ,.wr_rsp_complete (wr_rsp_complete) //|> w + ); +NV_NVDLA_RUBIK_seq_gen u_seq_gen ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_consumer (dp2reg_consumer) //|< w + ,.reg2dp_perf_en (reg2dp_perf_en) //|< w + ,.dp2reg_d0_rd_stall_cnt (dp2reg_d0_rd_stall_cnt[31:0]) //|> w + ,.dp2reg_d1_rd_stall_cnt (dp2reg_d1_rd_stall_cnt[31:0]) //|> w + ,.reg2dp_op_en (reg2dp_op_en) //|< w + ,.reg2dp_datain_ram_type (reg2dp_datain_ram_type) //|< w + ,.reg2dp_rubik_mode (reg2dp_rubik_mode[1:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_dain_addr_high (reg2dp_dain_addr_high[31:0]) //|< w + ,.reg2dp_dain_addr_low (reg2dp_dain_addr_low[26:0]) //|< w + ,.reg2dp_datain_channel (reg2dp_datain_channel[12:0]) //|< w + ,.reg2dp_datain_height (reg2dp_datain_height[12:0]) //|< w + ,.reg2dp_datain_width (reg2dp_datain_width[12:0]) //|< w + ,.reg2dp_deconv_x_stride (reg2dp_deconv_x_stride[4:0]) //|< w + ,.reg2dp_deconv_y_stride (reg2dp_deconv_y_stride[4:0]) //|< w + ,.reg2dp_dain_line_stride (reg2dp_dain_line_stride[26:0]) //|< w + ,.reg2dp_dain_planar_stride (reg2dp_dain_planar_stride[26:0]) //|< w + ,.reg2dp_dain_surf_stride (reg2dp_dain_surf_stride[26:0]) //|< w + ,.reg2dp_contract_stride_0 (reg2dp_contract_stride_0[26:0]) //|< w + ,.reg2dp_contract_stride_1 (reg2dp_contract_stride_1[26:0]) //|< w + ,.reg2dp_daout_addr_high (reg2dp_daout_addr_high[31:0]) //|< w + ,.reg2dp_daout_addr_low (reg2dp_daout_addr_low[26:0]) //|< w + ,.reg2dp_daout_line_stride (reg2dp_daout_line_stride[26:0]) //|< w + ,.reg2dp_daout_planar_stride (reg2dp_daout_planar_stride[26:0]) //|< w + ,.reg2dp_daout_surf_stride (reg2dp_daout_surf_stride[26:0]) //|< w + ,.reg2dp_dataout_channel (reg2dp_dataout_channel[12:0]) //|< w + ,.dp2reg_done (dp2reg_done) //|< w + ,.rd_req_type (rd_req_type) //|> w + ,.rd_req_vld (rd_req_vld) //|> w + ,.rd_req_rdy (rd_req_rdy) //|< w + ,.rd_req_pd (rd_req_pd[78:0]) //|> w + ,.rf_wr_cmd_vld (rf_wr_cmd_vld) //|> w + ,.rf_wr_cmd_rdy (rf_wr_cmd_rdy) //|< w + ,.rf_wr_cmd_pd (rf_wr_cmd_pd[10:0]) //|> w + ,.rf_rd_cmd_vld (rf_rd_cmd_vld) //|> w + ,.rf_rd_cmd_rdy (rf_rd_cmd_rdy) //|< w + ,.rf_rd_cmd_pd (rf_rd_cmd_pd[11:0]) //|> w + ,.dma_wr_cmd_vld (dma_wr_cmd_vld) //|> w + ,.dma_wr_cmd_rdy (dma_wr_cmd_rdy) //|< w + ,.dma_wr_cmd_pd (dma_wr_cmd_pd[77:0]) //|> w + ,.contract_lit_dx (contract_lit_dx) //|> w + ,.inwidth (inwidth[13:0]) //|> w + ); +NV_NVDLA_RUBIK_wr_req u_wr_req ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dp2reg_consumer (dp2reg_consumer) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.reg2dp_dataout_ram_type (reg2dp_dataout_ram_type) //|< w + ,.reg2dp_perf_en (reg2dp_perf_en) //|< w + ,.dp2reg_d0_wr_stall_cnt (dp2reg_d0_wr_stall_cnt[31:0]) //|> w + ,.dp2reg_d1_wr_stall_cnt (dp2reg_d1_wr_stall_cnt[31:0]) //|> w + ,.wr_req_type (wr_req_type) //|> w + ,.wr_req_vld (wr_req_vld) //|> w + ,.wr_req_pd (wr_req_pd[514:0]) //|> w + ,.wr_req_rdy (wr_req_rdy) //|< w + ,.dma_wr_cmd_vld (dma_wr_cmd_vld) //|< w + ,.dma_wr_cmd_pd (dma_wr_cmd_pd[77:0]) //|< w + ,.dma_wr_cmd_rdy (dma_wr_cmd_rdy) //|> w + ,.dma_wr_data_vld (dma_wr_data_vld) //|< w + ,.dma_wr_data_pd (dma_wr_data_pd[513:0]) //|< w + ,.dma_wr_data_rdy (dma_wr_data_rdy) //|> w + ,.dp2reg_done (dp2reg_done) //|> w + ); +NV_NVDLA_RUBIK_rf_ctrl u_rf_ctrl ( + .nvdla_core_clk (nvdla_op_gated_clk_0) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.contract_lit_dx (contract_lit_dx) //|< w + ,.inwidth (inwidth[13:0]) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.rf_wr_cmd_vld (rf_wr_cmd_vld) //|< w + ,.rf_wr_cmd_pd (rf_wr_cmd_pd[10:0]) //|< w + ,.rf_wr_cmd_rdy (rf_wr_cmd_rdy) //|> w + ,.rf_rd_cmd_vld (rf_rd_cmd_vld) //|< w + ,.rf_rd_cmd_pd (rf_rd_cmd_pd[11:0]) //|< w + ,.rf_rd_cmd_rdy (rf_rd_cmd_rdy) //|> w + ,.data_fifo_vld (data_fifo_vld) //|< w + ,.data_fifo_pd (data_fifo_pd[511:0]) //|< w + ,.data_fifo_rdy (data_fifo_rdy) //|> w + ,.rf_wr_vld (rf_wr_vld) //|> w + ,.rf_wr_done (rf_wr_done) //|> w + ,.rf_wr_addr (rf_wr_addr[4:0]) //|> w + ,.rf_wr_data (rf_wr_data[511:0]) //|> w + ,.rf_wr_rdy (rf_wr_rdy) //|< w + ,.rf_rd_vld (rf_rd_vld) //|> w + ,.rf_rd_done (rf_rd_done) //|> w + ,.rf_rd_mask (rf_rd_mask[11:0]) //|> w + ,.rf_rd_addr (rf_rd_addr[4:0]) //|> w + ,.rf_rd_rdy (rf_rd_rdy) //|< w + ,.reg2dp_rubik_mode (reg2dp_rubik_mode[1:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ); +NV_NVDLA_RUBIK_dr2drc u_dr2drc ( + .nvdla_core_clk (nvdla_op_gated_clk_1) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.rd_rsp_vld (rd_rsp_vld) //|< w + ,.rd_rsp_pd (rd_rsp_pd[513:0]) //|< w + ,.rd_rsp_rdy (rd_rsp_rdy) //|> w + ,.rd_cdt_lat_fifo_pop (rd_cdt_lat_fifo_pop) //|> w + ,.data_fifo_vld (data_fifo_vld) //|> w + ,.data_fifo_pd (data_fifo_pd[511:0]) //|> w + ,.data_fifo_rdy (data_fifo_rdy) //|< w + ); +NV_NVDLA_RUBIK_rf_core u_rf_core ( + .nvdla_core_clk (nvdla_op_gated_clk_2) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.rf_wr_vld (rf_wr_vld) //|< w + ,.rf_wr_done (rf_wr_done) //|< w + ,.rf_wr_addr (rf_wr_addr[4:0]) //|< w + ,.rf_wr_data (rf_wr_data[511:0]) //|< w + ,.rf_wr_rdy (rf_wr_rdy) //|> w + ,.rf_rd_vld (rf_rd_vld) //|< w + ,.rf_rd_done (rf_rd_done) //|< w + ,.rf_rd_addr (rf_rd_addr[4:0]) //|< w + ,.rf_rd_mask (rf_rd_mask[11:0]) //|< w + ,.rf_rd_rdy (rf_rd_rdy) //|> w + ,.dma_wr_data_vld (dma_wr_data_vld) //|> w + ,.dma_wr_data_pd (dma_wr_data_pd[513:0]) //|> w + ,.dma_wr_data_rdy (dma_wr_data_rdy) //|< w + ,.reg2dp_rubik_mode (reg2dp_rubik_mode[1:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ); +//Insert SLCG groups +NV_NVDLA_RUBIK_slcg u_slcg_op_0 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.enable (slcg_op_en[0]) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_0) //|> w + ); +NV_NVDLA_RUBIK_slcg u_slcg_op_1 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.enable (slcg_op_en[1]) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_1) //|> w + ); +NV_NVDLA_RUBIK_slcg u_slcg_op_2 ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.enable (slcg_op_en[2]) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_gated_clk (nvdla_op_gated_clk_2) //|> w + ); +/////////////////obs bus/////////////////// +//assign obs_bus_rubik_rd_req_vld = rd_req_vld ; +//assign obs_bus_rubik_rd_req_rdy = rd_req_rdy ; +//assign obs_bus_rubik_rd_req_done = rd_req_done ; +//assign obs_bus_rubik_dma_wr_cmd_vld = dma_wr_cmd_vld ; +//assign obs_bus_rubik_dma_wr_cmd_rdy = dma_wr_cmd_rdy ; +//assign obs_bus_rubik_rf_wcmd_vld = rf_wr_cmd_vld ; +//assign obs_bus_rubik_rf_wcmd_rdy = rf_wr_cmd_rdy ; +//assign obs_bus_rubik_rf_wcmd_pd = rf_wr_cmd_pd ; +//assign obs_bus_rubik_rf_rcmd_vld = rf_rd_cmd_vld ; +//assign obs_bus_rubik_rf_rcmd_rdy = rf_rd_cmd_rdy ; +//assign obs_bus_rubik_rf_rcmd_pd = rf_rd_cmd_pd ; +// +//assign obs_bus_rubik_rf_wr_vld = rf_wr_vld; +//assign obs_bus_rubik_rf_wr_rdy = rf_wr_rdy; +//assign obs_bus_rubik_rf_wr_done = rf_wr_done; +//assign obs_bus_rubik_rf_wr_addr = rf_wr_addr; +//assign obs_bus_rubik_rf_rd_vld = rf_rd_vld; +//assign obs_bus_rubik_rf_rd_rdy = rf_rd_rdy; +//assign obs_bus_rubik_rf_rd_done = rf_rd_done; +//assign obs_bus_rubik_rf_rd_addr = rf_rd_addr; +//assign obs_bus_rubik_rf_rd_mask = rf_rd_mask; +//assign obs_bus_rubik_dma_wr_data_vld = dma_wr_data_vld; +//assign obs_bus_rubik_dma_wr_data_rdy = dma_wr_data_rdy; +// +//assign obs_bus_rubik_wr_req_vld = wr_req_vld; +//assign obs_bus_rubik_wr_req_rdy = wr_req_rdy; +//assign obs_bus_rubik_wr_req_done = dp2reg_done; +//assign obs_bus_rubik_wr_rsp_complete = wr_rsp_complete; +endmodule // NV_NVDLA_rubik diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq.v new file mode 100644 index 0000000..9ef22a6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq.v @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_BRDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_BRDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [15:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [15:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] ig2cq_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 8'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [7:0] ig2cq_adr; // current write address +wire [7:0] cq2eg_adr_p; // read address to use for ram +wire [15:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x16 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (ig2cq_adr == 8'd159) ? 8'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] cq2eg_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (cq2eg_adr == 8'd159) ? 8'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [7:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 8'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_cq_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_BRDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_BRDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_BRDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq.v.vcp new file mode 100644 index 0000000..9ef22a6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq.v.vcp @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_BRDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_BRDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [15:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [15:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] ig2cq_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 8'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [7:0] ig2cq_adr; // current write address +wire [7:0] cq2eg_adr_p; // read address to use for ram +wire [15:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x16 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (ig2cq_adr == 8'd159) ? 8'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] cq2eg_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (cq2eg_adr == 8'd159) ? 8'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [7:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 8'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_cq_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_BRDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_BRDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_BRDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v new file mode 100644 index 0000000..34765e5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_BRDMA_gate.v +module NV_NVDLA_SDP_BRDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,brdma_disable + ,brdma_slcg_op_en + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input brdma_disable; +input brdma_slcg_op_en; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg brdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + brdma_enable <= 1'b0; + end else begin + brdma_enable <= !brdma_disable; + end +end +assign cfg_clk_en = brdma_slcg_op_en & brdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_BRDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v.vcp new file mode 100644 index 0000000..34765e5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v.vcp @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_BRDMA_gate.v +module NV_NVDLA_SDP_BRDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,brdma_disable + ,brdma_slcg_op_en + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input brdma_disable; +input brdma_slcg_op_en; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg brdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + brdma_enable <= 1'b0; + end else begin + brdma_enable <= !brdma_disable; + end +end +assign cfg_clk_en = brdma_slcg_op_en & brdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_BRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_BRDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo.v new file mode 100644 index 0000000..6fec5b0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo.v @@ -0,0 +1,606 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_BRDMA_lat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_BRDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] lat_wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 8'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [7:0] lat_wr_adr; // current write address +wire [7:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (lat_wr_adr == 8'd159) ? 8'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] lat_rd_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (lat_rd_adr == 8'd159) ? 8'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [7:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 8'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst6(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst7(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_BRDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed6; +reg prand_initialized6; +reg prand_no_rollpli6; +`endif +`endif +`endif +function [31:0] prand_inst6; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst6 = min; +`else +`ifdef SYNTHESIS + prand_inst6 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized6 !== 1'b1) begin + prand_no_rollpli6 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli6) + prand_local_seed6 = {$prand_get_seed(6), 16'b0}; + prand_initialized6 = 1'b1; + end + if (prand_no_rollpli6) begin + prand_inst6 = min; + end else begin + diff = max - min + 1; + prand_inst6 = min + prand_local_seed6[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed6 = prand_local_seed6 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst6 = min; +`else + prand_inst6 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed7; +reg prand_initialized7; +reg prand_no_rollpli7; +`endif +`endif +`endif +function [31:0] prand_inst7; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst7 = min; +`else +`ifdef SYNTHESIS + prand_inst7 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized7 !== 1'b1) begin + prand_no_rollpli7 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli7) + prand_local_seed7 = {$prand_get_seed(7), 16'b0}; + prand_initialized7 = 1'b1; + end + if (prand_no_rollpli7) begin + prand_inst7 = min; + end else begin + diff = max - min + 1; + prand_inst7 = min + prand_local_seed7[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed7 = prand_local_seed7 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst7 = min; +`else + prand_inst7 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_BRDMA_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo.v.vcp new file mode 100644 index 0000000..6fec5b0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo.v.vcp @@ -0,0 +1,606 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_BRDMA_lat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_BRDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] lat_wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 8'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [7:0] lat_wr_adr; // current write address +wire [7:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (lat_wr_adr == 8'd159) ? 8'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] lat_rd_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (lat_rd_adr == 8'd159) ? 8'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [7:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 8'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_BRDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst6(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst7(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_BRDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed6; +reg prand_initialized6; +reg prand_no_rollpli6; +`endif +`endif +`endif +function [31:0] prand_inst6; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst6 = min; +`else +`ifdef SYNTHESIS + prand_inst6 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized6 !== 1'b1) begin + prand_no_rollpli6 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli6) + prand_local_seed6 = {$prand_get_seed(6), 16'b0}; + prand_initialized6 = 1'b1; + end + if (prand_no_rollpli6) begin + prand_inst6 = min; + end else begin + diff = max - min + 1; + prand_inst6 = min + prand_local_seed6[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed6 = prand_local_seed6 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst6 = min; +`else + prand_inst6 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed7; +reg prand_initialized7; +reg prand_no_rollpli7; +`endif +`endif +`endif +function [31:0] prand_inst7; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst7 = min; +`else +`ifdef SYNTHESIS + prand_inst7 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized7 !== 1'b1) begin + prand_no_rollpli7 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli7) + prand_local_seed7 = {$prand_get_seed(7), 16'b0}; + prand_initialized7 = 1'b1; + end + if (prand_no_rollpli7) begin + prand_inst7 = min; + end else begin + diff = max - min + 1; + prand_inst7 = min + prand_local_seed7[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed7 = prand_local_seed7 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst7 = min; +`else + prand_inst7 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_BRDMA_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v new file mode 100644 index 0000000..698643e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v @@ -0,0 +1,22827 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_Y_lut.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_CORE_Y_lut ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,idx2lut_pd //|< i + ,idx2lut_pvld //|< i + ,lut2inp_prdy //|< i + ,op_en_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_lut_int_access_type //|< i + ,reg2dp_lut_int_addr //|< i + ,reg2dp_lut_int_data //|< i + ,reg2dp_lut_int_data_wr //|< i + ,reg2dp_lut_int_table_id //|< i + ,reg2dp_lut_le_end //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_slope_oflow_scale //|< i + ,reg2dp_lut_le_slope_oflow_shift //|< i + ,reg2dp_lut_le_slope_uflow_scale //|< i + ,reg2dp_lut_le_slope_uflow_shift //|< i + ,reg2dp_lut_le_start //|< i + ,reg2dp_lut_lo_end //|< i + ,reg2dp_lut_lo_slope_oflow_scale //|< i + ,reg2dp_lut_lo_slope_oflow_shift //|< i + ,reg2dp_lut_lo_slope_uflow_scale //|< i + ,reg2dp_lut_lo_slope_uflow_shift //|< i + ,reg2dp_lut_lo_start //|< i + ,reg2dp_perf_lut_en //|< i + ,reg2dp_proc_precision //|< i + ,dp2reg_lut_hybrid //|> o + ,dp2reg_lut_int_data //|> o + ,dp2reg_lut_le_hit //|> o + ,dp2reg_lut_lo_hit //|> o + ,dp2reg_lut_oflow //|> o + ,dp2reg_lut_uflow //|> o + ,idx2lut_prdy //|> o + ,lut2inp_pd //|> o + ,lut2inp_pvld //|> o + ); +// +// NV_NVDLA_SDP_CORE_Y_lut_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output lut2inp_pvld; /* data valid */ +input lut2inp_prdy; /* data return handshake */ +output [185*0 -1:0] lut2inp_pd; +input idx2lut_pvld; /* data valid */ +output idx2lut_prdy; /* data return handshake */ +input [81*0 -1:0] idx2lut_pd; +input reg2dp_lut_int_access_type; +input [9:0] reg2dp_lut_int_addr; +input [15:0] reg2dp_lut_int_data; +input reg2dp_lut_int_data_wr; +input reg2dp_lut_int_table_id; +input [31:0] reg2dp_lut_le_end; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [15:0] reg2dp_lut_le_slope_oflow_scale; +input [4:0] reg2dp_lut_le_slope_oflow_shift; +input [15:0] reg2dp_lut_le_slope_uflow_scale; +input [4:0] reg2dp_lut_le_slope_uflow_shift; +input [31:0] reg2dp_lut_le_start; +input [31:0] reg2dp_lut_lo_end; +input [15:0] reg2dp_lut_lo_slope_oflow_scale; +input [4:0] reg2dp_lut_lo_slope_oflow_shift; +input [15:0] reg2dp_lut_lo_slope_uflow_scale; +input [4:0] reg2dp_lut_lo_slope_uflow_shift; +input [31:0] reg2dp_lut_lo_start; +input reg2dp_perf_lut_en; +input [1:0] reg2dp_proc_precision; +output [31:0] dp2reg_lut_hybrid; +output [15:0] dp2reg_lut_int_data; +output [31:0] dp2reg_lut_le_hit; +output [31:0] dp2reg_lut_lo_hit; +output [31:0] dp2reg_lut_oflow; +output [31:0] dp2reg_lut_uflow; +input [31:0] pwrbus_ram_pd; +input op_en_load; +reg idx2lut_prdy; +reg [185*0 -1:0] lut2inp_pd; +reg lut2inp_pvld; +reg [81*0 -1:0] lut_in_pd; +reg lut_in_pvld; +wire lut_in_prdy; +wire [185*0 -1:0] lut_out_pd; +wire lut_out_pvld; +reg lut_out_prdy; +//: my $k = 0; +//: my $m = 257; +//: foreach my $lut (qw(le lo)) { +//: foreach my $i (0..${m}-1) { +//: print "reg [15:0] REG_${lut}_${i}; \n"; +//: } +//: } +//: foreach my $lut (qw(le lo)) { +//: foreach my $j (0..1) { +//: foreach my $i (0..${k}-1) { +//: print "reg [15:0] ${lut}_data${j}_${i}; \n"; +//: } +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +reg [15:0] REG_le_0; +reg [15:0] REG_le_1; +reg [15:0] REG_le_2; +reg [15:0] REG_le_3; +reg [15:0] REG_le_4; +reg [15:0] REG_le_5; +reg [15:0] REG_le_6; +reg [15:0] REG_le_7; +reg [15:0] REG_le_8; +reg [15:0] REG_le_9; +reg [15:0] REG_le_10; +reg [15:0] REG_le_11; +reg [15:0] REG_le_12; +reg [15:0] REG_le_13; +reg [15:0] REG_le_14; +reg [15:0] REG_le_15; +reg [15:0] REG_le_16; +reg [15:0] REG_le_17; +reg [15:0] REG_le_18; +reg [15:0] REG_le_19; +reg [15:0] REG_le_20; +reg [15:0] REG_le_21; +reg [15:0] REG_le_22; +reg [15:0] REG_le_23; +reg [15:0] REG_le_24; +reg [15:0] REG_le_25; +reg [15:0] REG_le_26; +reg [15:0] REG_le_27; +reg [15:0] REG_le_28; +reg [15:0] REG_le_29; +reg [15:0] REG_le_30; +reg [15:0] REG_le_31; +reg [15:0] REG_le_32; +reg [15:0] REG_le_33; +reg [15:0] REG_le_34; +reg [15:0] REG_le_35; +reg [15:0] REG_le_36; +reg [15:0] REG_le_37; +reg [15:0] REG_le_38; +reg [15:0] REG_le_39; +reg [15:0] REG_le_40; +reg [15:0] REG_le_41; +reg [15:0] REG_le_42; +reg [15:0] REG_le_43; +reg [15:0] REG_le_44; +reg [15:0] REG_le_45; +reg [15:0] REG_le_46; +reg [15:0] REG_le_47; +reg [15:0] REG_le_48; +reg [15:0] REG_le_49; +reg [15:0] REG_le_50; +reg [15:0] REG_le_51; +reg [15:0] REG_le_52; +reg [15:0] REG_le_53; +reg [15:0] REG_le_54; +reg [15:0] REG_le_55; +reg [15:0] REG_le_56; +reg [15:0] REG_le_57; +reg [15:0] REG_le_58; +reg [15:0] REG_le_59; +reg [15:0] REG_le_60; +reg [15:0] REG_le_61; +reg [15:0] REG_le_62; +reg [15:0] REG_le_63; +reg [15:0] REG_le_64; +reg [15:0] REG_le_65; +reg [15:0] REG_le_66; +reg [15:0] REG_le_67; +reg [15:0] REG_le_68; +reg [15:0] REG_le_69; +reg [15:0] REG_le_70; +reg [15:0] REG_le_71; +reg [15:0] REG_le_72; +reg [15:0] REG_le_73; +reg [15:0] REG_le_74; +reg [15:0] REG_le_75; +reg [15:0] REG_le_76; +reg [15:0] REG_le_77; +reg [15:0] REG_le_78; +reg [15:0] REG_le_79; +reg [15:0] REG_le_80; +reg [15:0] REG_le_81; +reg [15:0] REG_le_82; +reg [15:0] REG_le_83; +reg [15:0] REG_le_84; +reg [15:0] REG_le_85; +reg [15:0] REG_le_86; +reg [15:0] REG_le_87; +reg [15:0] REG_le_88; +reg [15:0] REG_le_89; +reg [15:0] REG_le_90; +reg [15:0] REG_le_91; +reg [15:0] REG_le_92; +reg [15:0] REG_le_93; +reg [15:0] REG_le_94; +reg [15:0] REG_le_95; +reg [15:0] REG_le_96; +reg [15:0] REG_le_97; +reg [15:0] REG_le_98; +reg [15:0] REG_le_99; +reg [15:0] REG_le_100; +reg [15:0] REG_le_101; +reg [15:0] REG_le_102; +reg [15:0] REG_le_103; +reg [15:0] REG_le_104; +reg [15:0] REG_le_105; +reg [15:0] REG_le_106; +reg [15:0] REG_le_107; +reg [15:0] REG_le_108; +reg [15:0] REG_le_109; +reg [15:0] REG_le_110; +reg [15:0] REG_le_111; +reg [15:0] REG_le_112; +reg [15:0] REG_le_113; +reg [15:0] REG_le_114; +reg [15:0] REG_le_115; +reg [15:0] REG_le_116; +reg [15:0] REG_le_117; +reg [15:0] REG_le_118; +reg [15:0] REG_le_119; +reg [15:0] REG_le_120; +reg [15:0] REG_le_121; +reg [15:0] REG_le_122; +reg [15:0] REG_le_123; +reg [15:0] REG_le_124; +reg [15:0] REG_le_125; +reg [15:0] REG_le_126; +reg [15:0] REG_le_127; +reg [15:0] REG_le_128; +reg [15:0] REG_le_129; +reg [15:0] REG_le_130; +reg [15:0] REG_le_131; +reg [15:0] REG_le_132; +reg [15:0] REG_le_133; +reg [15:0] REG_le_134; +reg [15:0] REG_le_135; +reg [15:0] REG_le_136; +reg [15:0] REG_le_137; +reg [15:0] REG_le_138; +reg [15:0] REG_le_139; +reg [15:0] REG_le_140; +reg [15:0] REG_le_141; +reg [15:0] REG_le_142; +reg [15:0] REG_le_143; +reg [15:0] REG_le_144; +reg [15:0] REG_le_145; +reg [15:0] REG_le_146; +reg [15:0] REG_le_147; +reg [15:0] REG_le_148; +reg [15:0] REG_le_149; +reg [15:0] REG_le_150; +reg [15:0] REG_le_151; +reg [15:0] REG_le_152; +reg [15:0] REG_le_153; +reg [15:0] REG_le_154; +reg [15:0] REG_le_155; +reg [15:0] REG_le_156; +reg [15:0] REG_le_157; +reg [15:0] REG_le_158; +reg [15:0] REG_le_159; +reg [15:0] REG_le_160; +reg [15:0] REG_le_161; +reg [15:0] REG_le_162; +reg [15:0] REG_le_163; +reg [15:0] REG_le_164; +reg [15:0] REG_le_165; +reg [15:0] REG_le_166; +reg [15:0] REG_le_167; +reg [15:0] REG_le_168; +reg [15:0] REG_le_169; +reg [15:0] REG_le_170; +reg [15:0] REG_le_171; +reg [15:0] REG_le_172; +reg [15:0] REG_le_173; +reg [15:0] REG_le_174; +reg [15:0] REG_le_175; +reg [15:0] REG_le_176; +reg [15:0] REG_le_177; +reg [15:0] REG_le_178; +reg [15:0] REG_le_179; +reg [15:0] REG_le_180; +reg [15:0] REG_le_181; +reg [15:0] REG_le_182; +reg [15:0] REG_le_183; +reg [15:0] REG_le_184; +reg [15:0] REG_le_185; +reg [15:0] REG_le_186; +reg [15:0] REG_le_187; +reg [15:0] REG_le_188; +reg [15:0] REG_le_189; +reg [15:0] REG_le_190; +reg [15:0] REG_le_191; +reg [15:0] REG_le_192; +reg [15:0] REG_le_193; +reg [15:0] REG_le_194; +reg [15:0] REG_le_195; +reg [15:0] REG_le_196; +reg [15:0] REG_le_197; +reg [15:0] REG_le_198; +reg [15:0] REG_le_199; +reg [15:0] REG_le_200; +reg [15:0] REG_le_201; +reg [15:0] REG_le_202; +reg [15:0] REG_le_203; +reg [15:0] REG_le_204; +reg [15:0] REG_le_205; +reg [15:0] REG_le_206; +reg [15:0] REG_le_207; +reg [15:0] REG_le_208; +reg [15:0] REG_le_209; +reg [15:0] REG_le_210; +reg [15:0] REG_le_211; +reg [15:0] REG_le_212; +reg [15:0] REG_le_213; +reg [15:0] REG_le_214; +reg [15:0] REG_le_215; +reg [15:0] REG_le_216; +reg [15:0] REG_le_217; +reg [15:0] REG_le_218; +reg [15:0] REG_le_219; +reg [15:0] REG_le_220; +reg [15:0] REG_le_221; +reg [15:0] REG_le_222; +reg [15:0] REG_le_223; +reg [15:0] REG_le_224; +reg [15:0] REG_le_225; +reg [15:0] REG_le_226; +reg [15:0] REG_le_227; +reg [15:0] REG_le_228; +reg [15:0] REG_le_229; +reg [15:0] REG_le_230; +reg [15:0] REG_le_231; +reg [15:0] REG_le_232; +reg [15:0] REG_le_233; +reg [15:0] REG_le_234; +reg [15:0] REG_le_235; +reg [15:0] REG_le_236; +reg [15:0] REG_le_237; +reg [15:0] REG_le_238; +reg [15:0] REG_le_239; +reg [15:0] REG_le_240; +reg [15:0] REG_le_241; +reg [15:0] REG_le_242; +reg [15:0] REG_le_243; +reg [15:0] REG_le_244; +reg [15:0] REG_le_245; +reg [15:0] REG_le_246; +reg [15:0] REG_le_247; +reg [15:0] REG_le_248; +reg [15:0] REG_le_249; +reg [15:0] REG_le_250; +reg [15:0] REG_le_251; +reg [15:0] REG_le_252; +reg [15:0] REG_le_253; +reg [15:0] REG_le_254; +reg [15:0] REG_le_255; +reg [15:0] REG_le_256; +reg [15:0] REG_lo_0; +reg [15:0] REG_lo_1; +reg [15:0] REG_lo_2; +reg [15:0] REG_lo_3; +reg [15:0] REG_lo_4; +reg [15:0] REG_lo_5; +reg [15:0] REG_lo_6; +reg [15:0] REG_lo_7; +reg [15:0] REG_lo_8; +reg [15:0] REG_lo_9; +reg [15:0] REG_lo_10; +reg [15:0] REG_lo_11; +reg [15:0] REG_lo_12; +reg [15:0] REG_lo_13; +reg [15:0] REG_lo_14; +reg [15:0] REG_lo_15; +reg [15:0] REG_lo_16; +reg [15:0] REG_lo_17; +reg [15:0] REG_lo_18; +reg [15:0] REG_lo_19; +reg [15:0] REG_lo_20; +reg [15:0] REG_lo_21; +reg [15:0] REG_lo_22; +reg [15:0] REG_lo_23; +reg [15:0] REG_lo_24; +reg [15:0] REG_lo_25; +reg [15:0] REG_lo_26; +reg [15:0] REG_lo_27; +reg [15:0] REG_lo_28; +reg [15:0] REG_lo_29; +reg [15:0] REG_lo_30; +reg [15:0] REG_lo_31; +reg [15:0] REG_lo_32; +reg [15:0] REG_lo_33; +reg [15:0] REG_lo_34; +reg [15:0] REG_lo_35; +reg [15:0] REG_lo_36; +reg [15:0] REG_lo_37; +reg [15:0] REG_lo_38; +reg [15:0] REG_lo_39; +reg [15:0] REG_lo_40; +reg [15:0] REG_lo_41; +reg [15:0] REG_lo_42; +reg [15:0] REG_lo_43; +reg [15:0] REG_lo_44; +reg [15:0] REG_lo_45; +reg [15:0] REG_lo_46; +reg [15:0] REG_lo_47; +reg [15:0] REG_lo_48; +reg [15:0] REG_lo_49; +reg [15:0] REG_lo_50; +reg [15:0] REG_lo_51; +reg [15:0] REG_lo_52; +reg [15:0] REG_lo_53; +reg [15:0] REG_lo_54; +reg [15:0] REG_lo_55; +reg [15:0] REG_lo_56; +reg [15:0] REG_lo_57; +reg [15:0] REG_lo_58; +reg [15:0] REG_lo_59; +reg [15:0] REG_lo_60; +reg [15:0] REG_lo_61; +reg [15:0] REG_lo_62; +reg [15:0] REG_lo_63; +reg [15:0] REG_lo_64; +reg [15:0] REG_lo_65; +reg [15:0] REG_lo_66; +reg [15:0] REG_lo_67; +reg [15:0] REG_lo_68; +reg [15:0] REG_lo_69; +reg [15:0] REG_lo_70; +reg [15:0] REG_lo_71; +reg [15:0] REG_lo_72; +reg [15:0] REG_lo_73; +reg [15:0] REG_lo_74; +reg [15:0] REG_lo_75; +reg [15:0] REG_lo_76; +reg [15:0] REG_lo_77; +reg [15:0] REG_lo_78; +reg [15:0] REG_lo_79; +reg [15:0] REG_lo_80; +reg [15:0] REG_lo_81; +reg [15:0] REG_lo_82; +reg [15:0] REG_lo_83; +reg [15:0] REG_lo_84; +reg [15:0] REG_lo_85; +reg [15:0] REG_lo_86; +reg [15:0] REG_lo_87; +reg [15:0] REG_lo_88; +reg [15:0] REG_lo_89; +reg [15:0] REG_lo_90; +reg [15:0] REG_lo_91; +reg [15:0] REG_lo_92; +reg [15:0] REG_lo_93; +reg [15:0] REG_lo_94; +reg [15:0] REG_lo_95; +reg [15:0] REG_lo_96; +reg [15:0] REG_lo_97; +reg [15:0] REG_lo_98; +reg [15:0] REG_lo_99; +reg [15:0] REG_lo_100; +reg [15:0] REG_lo_101; +reg [15:0] REG_lo_102; +reg [15:0] REG_lo_103; +reg [15:0] REG_lo_104; +reg [15:0] REG_lo_105; +reg [15:0] REG_lo_106; +reg [15:0] REG_lo_107; +reg [15:0] REG_lo_108; +reg [15:0] REG_lo_109; +reg [15:0] REG_lo_110; +reg [15:0] REG_lo_111; +reg [15:0] REG_lo_112; +reg [15:0] REG_lo_113; +reg [15:0] REG_lo_114; +reg [15:0] REG_lo_115; +reg [15:0] REG_lo_116; +reg [15:0] REG_lo_117; +reg [15:0] REG_lo_118; +reg [15:0] REG_lo_119; +reg [15:0] REG_lo_120; +reg [15:0] REG_lo_121; +reg [15:0] REG_lo_122; +reg [15:0] REG_lo_123; +reg [15:0] REG_lo_124; +reg [15:0] REG_lo_125; +reg [15:0] REG_lo_126; +reg [15:0] REG_lo_127; +reg [15:0] REG_lo_128; +reg [15:0] REG_lo_129; +reg [15:0] REG_lo_130; +reg [15:0] REG_lo_131; +reg [15:0] REG_lo_132; +reg [15:0] REG_lo_133; +reg [15:0] REG_lo_134; +reg [15:0] REG_lo_135; +reg [15:0] REG_lo_136; +reg [15:0] REG_lo_137; +reg [15:0] REG_lo_138; +reg [15:0] REG_lo_139; +reg [15:0] REG_lo_140; +reg [15:0] REG_lo_141; +reg [15:0] REG_lo_142; +reg [15:0] REG_lo_143; +reg [15:0] REG_lo_144; +reg [15:0] REG_lo_145; +reg [15:0] REG_lo_146; +reg [15:0] REG_lo_147; +reg [15:0] REG_lo_148; +reg [15:0] REG_lo_149; +reg [15:0] REG_lo_150; +reg [15:0] REG_lo_151; +reg [15:0] REG_lo_152; +reg [15:0] REG_lo_153; +reg [15:0] REG_lo_154; +reg [15:0] REG_lo_155; +reg [15:0] REG_lo_156; +reg [15:0] REG_lo_157; +reg [15:0] REG_lo_158; +reg [15:0] REG_lo_159; +reg [15:0] REG_lo_160; +reg [15:0] REG_lo_161; +reg [15:0] REG_lo_162; +reg [15:0] REG_lo_163; +reg [15:0] REG_lo_164; +reg [15:0] REG_lo_165; +reg [15:0] REG_lo_166; +reg [15:0] REG_lo_167; +reg [15:0] REG_lo_168; +reg [15:0] REG_lo_169; +reg [15:0] REG_lo_170; +reg [15:0] REG_lo_171; +reg [15:0] REG_lo_172; +reg [15:0] REG_lo_173; +reg [15:0] REG_lo_174; +reg [15:0] REG_lo_175; +reg [15:0] REG_lo_176; +reg [15:0] REG_lo_177; +reg [15:0] REG_lo_178; +reg [15:0] REG_lo_179; +reg [15:0] REG_lo_180; +reg [15:0] REG_lo_181; +reg [15:0] REG_lo_182; +reg [15:0] REG_lo_183; +reg [15:0] REG_lo_184; +reg [15:0] REG_lo_185; +reg [15:0] REG_lo_186; +reg [15:0] REG_lo_187; +reg [15:0] REG_lo_188; +reg [15:0] REG_lo_189; +reg [15:0] REG_lo_190; +reg [15:0] REG_lo_191; +reg [15:0] REG_lo_192; +reg [15:0] REG_lo_193; +reg [15:0] REG_lo_194; +reg [15:0] REG_lo_195; +reg [15:0] REG_lo_196; +reg [15:0] REG_lo_197; +reg [15:0] REG_lo_198; +reg [15:0] REG_lo_199; +reg [15:0] REG_lo_200; +reg [15:0] REG_lo_201; +reg [15:0] REG_lo_202; +reg [15:0] REG_lo_203; +reg [15:0] REG_lo_204; +reg [15:0] REG_lo_205; +reg [15:0] REG_lo_206; +reg [15:0] REG_lo_207; +reg [15:0] REG_lo_208; +reg [15:0] REG_lo_209; +reg [15:0] REG_lo_210; +reg [15:0] REG_lo_211; +reg [15:0] REG_lo_212; +reg [15:0] REG_lo_213; +reg [15:0] REG_lo_214; +reg [15:0] REG_lo_215; +reg [15:0] REG_lo_216; +reg [15:0] REG_lo_217; +reg [15:0] REG_lo_218; +reg [15:0] REG_lo_219; +reg [15:0] REG_lo_220; +reg [15:0] REG_lo_221; +reg [15:0] REG_lo_222; +reg [15:0] REG_lo_223; +reg [15:0] REG_lo_224; +reg [15:0] REG_lo_225; +reg [15:0] REG_lo_226; +reg [15:0] REG_lo_227; +reg [15:0] REG_lo_228; +reg [15:0] REG_lo_229; +reg [15:0] REG_lo_230; +reg [15:0] REG_lo_231; +reg [15:0] REG_lo_232; +reg [15:0] REG_lo_233; +reg [15:0] REG_lo_234; +reg [15:0] REG_lo_235; +reg [15:0] REG_lo_236; +reg [15:0] REG_lo_237; +reg [15:0] REG_lo_238; +reg [15:0] REG_lo_239; +reg [15:0] REG_lo_240; +reg [15:0] REG_lo_241; +reg [15:0] REG_lo_242; +reg [15:0] REG_lo_243; +reg [15:0] REG_lo_244; +reg [15:0] REG_lo_245; +reg [15:0] REG_lo_246; +reg [15:0] REG_lo_247; +reg [15:0] REG_lo_248; +reg [15:0] REG_lo_249; +reg [15:0] REG_lo_250; +reg [15:0] REG_lo_251; +reg [15:0] REG_lo_252; +reg [15:0] REG_lo_253; +reg [15:0] REG_lo_254; +reg [15:0] REG_lo_255; +reg [15:0] REG_lo_256; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +reg [15:0] le_lut_data; +reg [15:0] lo_lut_data; +//: my $k = 0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: reg [31:0] out_bias${i}; +//: reg [31:0] out_offset${i}; +//: reg [15:0] out_scale${i}; +//: reg [4:0] out_shift${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [4:0] lut_hybrid_sum; +wire [4:0] lut_le_hit_sum; +wire [4:0] lut_lo_hit_sum; +wire [4:0] lut_oflow_sum; +wire [4:0] lut_uflow_sum; +wire [4:0] perf_lut_hybrid_add; +wire [0:0] perf_lut_hybrid_sub; +wire [4:0] perf_lut_le_hit_add; +wire [0:0] perf_lut_le_hit_sub; +wire [4:0] perf_lut_lo_hit_add; +wire [0:0] perf_lut_lo_hit_sub; +wire [4:0] perf_lut_oflow_add; +wire [0:0] perf_lut_oflow_sub; +wire [4:0] perf_lut_uflow_add; +wire [0:0] perf_lut_uflow_sub; +reg [31:0] lut_hybrid_cnt; +reg [31:0] lut_le_hit_cnt; +reg [31:0] lut_lo_hit_cnt; +reg [31:0] lut_oflow_cnt; +reg [31:0] lut_uflow_cnt; +reg perf_lut_hybrid_adv; +reg [31:0] perf_lut_hybrid_cnt_cur; +reg [33:0] perf_lut_hybrid_cnt_ext; +reg [33:0] perf_lut_hybrid_cnt_mod; +reg [33:0] perf_lut_hybrid_cnt_new; +reg [33:0] perf_lut_hybrid_cnt_nxt; +reg perf_lut_le_hit_adv; +reg [31:0] perf_lut_le_hit_cnt_cur; +reg [33:0] perf_lut_le_hit_cnt_ext; +reg [33:0] perf_lut_le_hit_cnt_mod; +reg [33:0] perf_lut_le_hit_cnt_new; +reg [33:0] perf_lut_le_hit_cnt_nxt; +reg perf_lut_lo_hit_adv; +reg [31:0] perf_lut_lo_hit_cnt_cur; +reg [33:0] perf_lut_lo_hit_cnt_ext; +reg [33:0] perf_lut_lo_hit_cnt_mod; +reg [33:0] perf_lut_lo_hit_cnt_new; +reg [33:0] perf_lut_lo_hit_cnt_nxt; +reg perf_lut_oflow_adv; +reg [31:0] perf_lut_oflow_cnt_cur; +reg [33:0] perf_lut_oflow_cnt_ext; +reg [33:0] perf_lut_oflow_cnt_mod; +reg [33:0] perf_lut_oflow_cnt_new; +reg [33:0] perf_lut_oflow_cnt_nxt; +reg perf_lut_uflow_adv; +reg [31:0] perf_lut_uflow_cnt_cur; +reg [33:0] perf_lut_uflow_cnt_ext; +reg [33:0] perf_lut_uflow_cnt_mod; +reg [33:0] perf_lut_uflow_cnt_new; +reg [33:0] perf_lut_uflow_cnt_nxt; +wire [70*0 -1:0] cmd_fifo_rd_pd; +wire cmd_fifo_rd_prdy; +wire cmd_fifo_rd_pvld; +wire [70*0 -1:0] cmd_fifo_wr_pd; +wire cmd_fifo_wr_prdy; +wire cmd_fifo_wr_pvld; +wire [32*0 -1:0] dat_fifo_rd_pd; +wire dat_fifo_rd_prdy; +wire dat_fifo_rd_pvld; +wire [32*0 -1:0] dat_fifo_wr_pd; +wire dat_fifo_wr_pvld; +//: my $k = 0; +//: foreach my $j (0..1) { +//: foreach my $i (0..${k}-1) { +//: print"wire [15:0] dat_in_y${j}_${i}; \n"; +//: } +//: } +//: my $ed = 65; +//: my $od = 257; +//: foreach my $i (0..${ed}-1) { +//: print"wire le_wr_en_$i; \n"; +//: } +//: foreach my $i (0..${od}-1) { +//: print"wire lo_wr_en_$i; \n"; +//: } +//: my $k = 0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [8:0] lut_in_addr${i}; +//: wire [8:0] lut_in_addr${i}_0; +//: wire [8:0] lut_in_addr${i}_1; +//: wire [34:0] lut_in_fraction${i}; +//: wire lut_in_hybrid${i}; +//: wire lut_in_le_hit${i}; +//: wire lut_in_lo_hit${i}; +//: wire lut_in_oflow${i}; +//: wire lut_in_sel${i}; +//: wire lut_in_uflow${i}; +//: wire [31:0] lut_in_x${i}; +//: wire out_flow${i}; +//: wire [34:0] out_fraction${i}; +//: wire out_oflow${i}; +//: wire out_sel${i}; +//: wire out_uflow${i}; +//: wire [31:0] out_x${i}; +//: wire [15:0] out_y0_${i}; +//: wire [15:0] out_y1_${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire le_wr_en_0; +wire le_wr_en_1; +wire le_wr_en_2; +wire le_wr_en_3; +wire le_wr_en_4; +wire le_wr_en_5; +wire le_wr_en_6; +wire le_wr_en_7; +wire le_wr_en_8; +wire le_wr_en_9; +wire le_wr_en_10; +wire le_wr_en_11; +wire le_wr_en_12; +wire le_wr_en_13; +wire le_wr_en_14; +wire le_wr_en_15; +wire le_wr_en_16; +wire le_wr_en_17; +wire le_wr_en_18; +wire le_wr_en_19; +wire le_wr_en_20; +wire le_wr_en_21; +wire le_wr_en_22; +wire le_wr_en_23; +wire le_wr_en_24; +wire le_wr_en_25; +wire le_wr_en_26; +wire le_wr_en_27; +wire le_wr_en_28; +wire le_wr_en_29; +wire le_wr_en_30; +wire le_wr_en_31; +wire le_wr_en_32; +wire le_wr_en_33; +wire le_wr_en_34; +wire le_wr_en_35; +wire le_wr_en_36; +wire le_wr_en_37; +wire le_wr_en_38; +wire le_wr_en_39; +wire le_wr_en_40; +wire le_wr_en_41; +wire le_wr_en_42; +wire le_wr_en_43; +wire le_wr_en_44; +wire le_wr_en_45; +wire le_wr_en_46; +wire le_wr_en_47; +wire le_wr_en_48; +wire le_wr_en_49; +wire le_wr_en_50; +wire le_wr_en_51; +wire le_wr_en_52; +wire le_wr_en_53; +wire le_wr_en_54; +wire le_wr_en_55; +wire le_wr_en_56; +wire le_wr_en_57; +wire le_wr_en_58; +wire le_wr_en_59; +wire le_wr_en_60; +wire le_wr_en_61; +wire le_wr_en_62; +wire le_wr_en_63; +wire le_wr_en_64; +wire lo_wr_en_0; +wire lo_wr_en_1; +wire lo_wr_en_2; +wire lo_wr_en_3; +wire lo_wr_en_4; +wire lo_wr_en_5; +wire lo_wr_en_6; +wire lo_wr_en_7; +wire lo_wr_en_8; +wire lo_wr_en_9; +wire lo_wr_en_10; +wire lo_wr_en_11; +wire lo_wr_en_12; +wire lo_wr_en_13; +wire lo_wr_en_14; +wire lo_wr_en_15; +wire lo_wr_en_16; +wire lo_wr_en_17; +wire lo_wr_en_18; +wire lo_wr_en_19; +wire lo_wr_en_20; +wire lo_wr_en_21; +wire lo_wr_en_22; +wire lo_wr_en_23; +wire lo_wr_en_24; +wire lo_wr_en_25; +wire lo_wr_en_26; +wire lo_wr_en_27; +wire lo_wr_en_28; +wire lo_wr_en_29; +wire lo_wr_en_30; +wire lo_wr_en_31; +wire lo_wr_en_32; +wire lo_wr_en_33; +wire lo_wr_en_34; +wire lo_wr_en_35; +wire lo_wr_en_36; +wire lo_wr_en_37; +wire lo_wr_en_38; +wire lo_wr_en_39; +wire lo_wr_en_40; +wire lo_wr_en_41; +wire lo_wr_en_42; +wire lo_wr_en_43; +wire lo_wr_en_44; +wire lo_wr_en_45; +wire lo_wr_en_46; +wire lo_wr_en_47; +wire lo_wr_en_48; +wire lo_wr_en_49; +wire lo_wr_en_50; +wire lo_wr_en_51; +wire lo_wr_en_52; +wire lo_wr_en_53; +wire lo_wr_en_54; +wire lo_wr_en_55; +wire lo_wr_en_56; +wire lo_wr_en_57; +wire lo_wr_en_58; +wire lo_wr_en_59; +wire lo_wr_en_60; +wire lo_wr_en_61; +wire lo_wr_en_62; +wire lo_wr_en_63; +wire lo_wr_en_64; +wire lo_wr_en_65; +wire lo_wr_en_66; +wire lo_wr_en_67; +wire lo_wr_en_68; +wire lo_wr_en_69; +wire lo_wr_en_70; +wire lo_wr_en_71; +wire lo_wr_en_72; +wire lo_wr_en_73; +wire lo_wr_en_74; +wire lo_wr_en_75; +wire lo_wr_en_76; +wire lo_wr_en_77; +wire lo_wr_en_78; +wire lo_wr_en_79; +wire lo_wr_en_80; +wire lo_wr_en_81; +wire lo_wr_en_82; +wire lo_wr_en_83; +wire lo_wr_en_84; +wire lo_wr_en_85; +wire lo_wr_en_86; +wire lo_wr_en_87; +wire lo_wr_en_88; +wire lo_wr_en_89; +wire lo_wr_en_90; +wire lo_wr_en_91; +wire lo_wr_en_92; +wire lo_wr_en_93; +wire lo_wr_en_94; +wire lo_wr_en_95; +wire lo_wr_en_96; +wire lo_wr_en_97; +wire lo_wr_en_98; +wire lo_wr_en_99; +wire lo_wr_en_100; +wire lo_wr_en_101; +wire lo_wr_en_102; +wire lo_wr_en_103; +wire lo_wr_en_104; +wire lo_wr_en_105; +wire lo_wr_en_106; +wire lo_wr_en_107; +wire lo_wr_en_108; +wire lo_wr_en_109; +wire lo_wr_en_110; +wire lo_wr_en_111; +wire lo_wr_en_112; +wire lo_wr_en_113; +wire lo_wr_en_114; +wire lo_wr_en_115; +wire lo_wr_en_116; +wire lo_wr_en_117; +wire lo_wr_en_118; +wire lo_wr_en_119; +wire lo_wr_en_120; +wire lo_wr_en_121; +wire lo_wr_en_122; +wire lo_wr_en_123; +wire lo_wr_en_124; +wire lo_wr_en_125; +wire lo_wr_en_126; +wire lo_wr_en_127; +wire lo_wr_en_128; +wire lo_wr_en_129; +wire lo_wr_en_130; +wire lo_wr_en_131; +wire lo_wr_en_132; +wire lo_wr_en_133; +wire lo_wr_en_134; +wire lo_wr_en_135; +wire lo_wr_en_136; +wire lo_wr_en_137; +wire lo_wr_en_138; +wire lo_wr_en_139; +wire lo_wr_en_140; +wire lo_wr_en_141; +wire lo_wr_en_142; +wire lo_wr_en_143; +wire lo_wr_en_144; +wire lo_wr_en_145; +wire lo_wr_en_146; +wire lo_wr_en_147; +wire lo_wr_en_148; +wire lo_wr_en_149; +wire lo_wr_en_150; +wire lo_wr_en_151; +wire lo_wr_en_152; +wire lo_wr_en_153; +wire lo_wr_en_154; +wire lo_wr_en_155; +wire lo_wr_en_156; +wire lo_wr_en_157; +wire lo_wr_en_158; +wire lo_wr_en_159; +wire lo_wr_en_160; +wire lo_wr_en_161; +wire lo_wr_en_162; +wire lo_wr_en_163; +wire lo_wr_en_164; +wire lo_wr_en_165; +wire lo_wr_en_166; +wire lo_wr_en_167; +wire lo_wr_en_168; +wire lo_wr_en_169; +wire lo_wr_en_170; +wire lo_wr_en_171; +wire lo_wr_en_172; +wire lo_wr_en_173; +wire lo_wr_en_174; +wire lo_wr_en_175; +wire lo_wr_en_176; +wire lo_wr_en_177; +wire lo_wr_en_178; +wire lo_wr_en_179; +wire lo_wr_en_180; +wire lo_wr_en_181; +wire lo_wr_en_182; +wire lo_wr_en_183; +wire lo_wr_en_184; +wire lo_wr_en_185; +wire lo_wr_en_186; +wire lo_wr_en_187; +wire lo_wr_en_188; +wire lo_wr_en_189; +wire lo_wr_en_190; +wire lo_wr_en_191; +wire lo_wr_en_192; +wire lo_wr_en_193; +wire lo_wr_en_194; +wire lo_wr_en_195; +wire lo_wr_en_196; +wire lo_wr_en_197; +wire lo_wr_en_198; +wire lo_wr_en_199; +wire lo_wr_en_200; +wire lo_wr_en_201; +wire lo_wr_en_202; +wire lo_wr_en_203; +wire lo_wr_en_204; +wire lo_wr_en_205; +wire lo_wr_en_206; +wire lo_wr_en_207; +wire lo_wr_en_208; +wire lo_wr_en_209; +wire lo_wr_en_210; +wire lo_wr_en_211; +wire lo_wr_en_212; +wire lo_wr_en_213; +wire lo_wr_en_214; +wire lo_wr_en_215; +wire lo_wr_en_216; +wire lo_wr_en_217; +wire lo_wr_en_218; +wire lo_wr_en_219; +wire lo_wr_en_220; +wire lo_wr_en_221; +wire lo_wr_en_222; +wire lo_wr_en_223; +wire lo_wr_en_224; +wire lo_wr_en_225; +wire lo_wr_en_226; +wire lo_wr_en_227; +wire lo_wr_en_228; +wire lo_wr_en_229; +wire lo_wr_en_230; +wire lo_wr_en_231; +wire lo_wr_en_232; +wire lo_wr_en_233; +wire lo_wr_en_234; +wire lo_wr_en_235; +wire lo_wr_en_236; +wire lo_wr_en_237; +wire lo_wr_en_238; +wire lo_wr_en_239; +wire lo_wr_en_240; +wire lo_wr_en_241; +wire lo_wr_en_242; +wire lo_wr_en_243; +wire lo_wr_en_244; +wire lo_wr_en_245; +wire lo_wr_en_246; +wire lo_wr_en_247; +wire lo_wr_en_248; +wire lo_wr_en_249; +wire lo_wr_en_250; +wire lo_wr_en_251; +wire lo_wr_en_252; +wire lo_wr_en_253; +wire lo_wr_en_254; +wire lo_wr_en_255; +wire lo_wr_en_256; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire lut_access_type; +wire [9:0] lut_addr; +wire [15:0] lut_data; +wire [27:0] pro2lut_pd; +wire pro2lut_valid; +wire [9:0] pro_in_addr; +wire [15:0] pro_in_data; +wire pro_in_select_le; +wire pro_in_select_lo; +wire pro_in_table_id; +wire pro_in_wr; +wire pro_in_wr_en; +wire rd_lut_en; +wire [27:0] lut_pd; +wire lut_table_id; +wire mon_cmd_fifo_rd_pvld; +//============== +// Reg Configure +//============== +// get the width of all regs +//======================================= +//=========================================== +// LUT Programing +//=========================================== +assign lut_addr = reg2dp_lut_int_addr[9:0]; +assign lut_data = reg2dp_lut_int_data[15:0]; +assign lut_table_id = reg2dp_lut_int_table_id; +assign lut_access_type = reg2dp_lut_int_access_type; +assign lut_pd = {lut_access_type,lut_table_id,lut_data,lut_addr}; +assign pro2lut_valid = reg2dp_lut_int_data_wr; +assign pro2lut_pd = lut_pd; +// PKT_UNPACK_WIRE( sdp_y_lut_pro , pro_in_ , pro2lut_pd ) +assign pro_in_addr[9:0] = pro2lut_pd[9:0]; +assign pro_in_data[15:0] = pro2lut_pd[25:10]; +assign pro_in_table_id = pro2lut_pd[26]; +assign pro_in_wr = pro2lut_pd[27]; +assign pro_in_wr_en = pro2lut_valid & (pro_in_wr== 1'h1 ); +//assign pro_in_rd_en = pro2lut_valid & pro_in_wr==0; +assign pro_in_select_le = pro_in_table_id== 1'h0 ; +assign pro_in_select_lo = pro_in_table_id== 1'h1 ; +//=========================================== +// READ LUT +always @( + pro_in_addr + or REG_le_0 + or REG_le_1 + or REG_le_2 + or REG_le_3 + or REG_le_4 + or REG_le_5 + or REG_le_6 + or REG_le_7 + or REG_le_8 + or REG_le_9 + or REG_le_10 + or REG_le_11 + or REG_le_12 + or REG_le_13 + or REG_le_14 + or REG_le_15 + or REG_le_16 + or REG_le_17 + or REG_le_18 + or REG_le_19 + or REG_le_20 + or REG_le_21 + or REG_le_22 + or REG_le_23 + or REG_le_24 + or REG_le_25 + or REG_le_26 + or REG_le_27 + or REG_le_28 + or REG_le_29 + or REG_le_30 + or REG_le_31 + or REG_le_32 + or REG_le_33 + or REG_le_34 + or REG_le_35 + or REG_le_36 + or REG_le_37 + or REG_le_38 + or REG_le_39 + or REG_le_40 + or REG_le_41 + or REG_le_42 + or REG_le_43 + or REG_le_44 + or REG_le_45 + or REG_le_46 + or REG_le_47 + or REG_le_48 + or REG_le_49 + or REG_le_50 + or REG_le_51 + or REG_le_52 + or REG_le_53 + or REG_le_54 + or REG_le_55 + or REG_le_56 + or REG_le_57 + or REG_le_58 + or REG_le_59 + or REG_le_60 + or REG_le_61 + or REG_le_62 + or REG_le_63 + or REG_le_64 + ) begin + case (pro_in_addr) +0: le_lut_data = REG_le_0; +1: le_lut_data = REG_le_1; +2: le_lut_data = REG_le_2; +3: le_lut_data = REG_le_3; +4: le_lut_data = REG_le_4; +5: le_lut_data = REG_le_5; +6: le_lut_data = REG_le_6; +7: le_lut_data = REG_le_7; +8: le_lut_data = REG_le_8; +9: le_lut_data = REG_le_9; +10: le_lut_data = REG_le_10; +11: le_lut_data = REG_le_11; +12: le_lut_data = REG_le_12; +13: le_lut_data = REG_le_13; +14: le_lut_data = REG_le_14; +15: le_lut_data = REG_le_15; +16: le_lut_data = REG_le_16; +17: le_lut_data = REG_le_17; +18: le_lut_data = REG_le_18; +19: le_lut_data = REG_le_19; +20: le_lut_data = REG_le_20; +21: le_lut_data = REG_le_21; +22: le_lut_data = REG_le_22; +23: le_lut_data = REG_le_23; +24: le_lut_data = REG_le_24; +25: le_lut_data = REG_le_25; +26: le_lut_data = REG_le_26; +27: le_lut_data = REG_le_27; +28: le_lut_data = REG_le_28; +29: le_lut_data = REG_le_29; +30: le_lut_data = REG_le_30; +31: le_lut_data = REG_le_31; +32: le_lut_data = REG_le_32; +33: le_lut_data = REG_le_33; +34: le_lut_data = REG_le_34; +35: le_lut_data = REG_le_35; +36: le_lut_data = REG_le_36; +37: le_lut_data = REG_le_37; +38: le_lut_data = REG_le_38; +39: le_lut_data = REG_le_39; +40: le_lut_data = REG_le_40; +41: le_lut_data = REG_le_41; +42: le_lut_data = REG_le_42; +43: le_lut_data = REG_le_43; +44: le_lut_data = REG_le_44; +45: le_lut_data = REG_le_45; +46: le_lut_data = REG_le_46; +47: le_lut_data = REG_le_47; +48: le_lut_data = REG_le_48; +49: le_lut_data = REG_le_49; +50: le_lut_data = REG_le_50; +51: le_lut_data = REG_le_51; +52: le_lut_data = REG_le_52; +53: le_lut_data = REG_le_53; +54: le_lut_data = REG_le_54; +55: le_lut_data = REG_le_55; +56: le_lut_data = REG_le_56; +57: le_lut_data = REG_le_57; +58: le_lut_data = REG_le_58; +59: le_lut_data = REG_le_59; +60: le_lut_data = REG_le_60; +61: le_lut_data = REG_le_61; +62: le_lut_data = REG_le_62; +63: le_lut_data = REG_le_63; +64: le_lut_data = REG_le_64; +//VCS coverage off + default : begin + le_lut_data[15:0] = {16{`x_or_0}}; + end +//VCS coverage on + endcase +end +always @( + pro_in_addr + or REG_lo_0 + or REG_lo_1 + or REG_lo_2 + or REG_lo_3 + or REG_lo_4 + or REG_lo_5 + or REG_lo_6 + or REG_lo_7 + or REG_lo_8 + or REG_lo_9 + or REG_lo_10 + or REG_lo_11 + or REG_lo_12 + or REG_lo_13 + or REG_lo_14 + or REG_lo_15 + or REG_lo_16 + or REG_lo_17 + or REG_lo_18 + or REG_lo_19 + or REG_lo_20 + or REG_lo_21 + or REG_lo_22 + or REG_lo_23 + or REG_lo_24 + or REG_lo_25 + or REG_lo_26 + or REG_lo_27 + or REG_lo_28 + or REG_lo_29 + or REG_lo_30 + or REG_lo_31 + or REG_lo_32 + or REG_lo_33 + or REG_lo_34 + or REG_lo_35 + or REG_lo_36 + or REG_lo_37 + or REG_lo_38 + or REG_lo_39 + or REG_lo_40 + or REG_lo_41 + or REG_lo_42 + or REG_lo_43 + or REG_lo_44 + or REG_lo_45 + or REG_lo_46 + or REG_lo_47 + or REG_lo_48 + or REG_lo_49 + or REG_lo_50 + or REG_lo_51 + or REG_lo_52 + or REG_lo_53 + or REG_lo_54 + or REG_lo_55 + or REG_lo_56 + or REG_lo_57 + or REG_lo_58 + or REG_lo_59 + or REG_lo_60 + or REG_lo_61 + or REG_lo_62 + or REG_lo_63 + or REG_lo_64 + or REG_lo_65 + or REG_lo_66 + or REG_lo_67 + or REG_lo_68 + or REG_lo_69 + or REG_lo_70 + or REG_lo_71 + or REG_lo_72 + or REG_lo_73 + or REG_lo_74 + or REG_lo_75 + or REG_lo_76 + or REG_lo_77 + or REG_lo_78 + or REG_lo_79 + or REG_lo_80 + or REG_lo_81 + or REG_lo_82 + or REG_lo_83 + or REG_lo_84 + or REG_lo_85 + or REG_lo_86 + or REG_lo_87 + or REG_lo_88 + or REG_lo_89 + or REG_lo_90 + or REG_lo_91 + or REG_lo_92 + or REG_lo_93 + or REG_lo_94 + or REG_lo_95 + or REG_lo_96 + or REG_lo_97 + or REG_lo_98 + or REG_lo_99 + or REG_lo_100 + or REG_lo_101 + or REG_lo_102 + or REG_lo_103 + or REG_lo_104 + or REG_lo_105 + or REG_lo_106 + or REG_lo_107 + or REG_lo_108 + or REG_lo_109 + or REG_lo_110 + or REG_lo_111 + or REG_lo_112 + or REG_lo_113 + or REG_lo_114 + or REG_lo_115 + or REG_lo_116 + or REG_lo_117 + or REG_lo_118 + or REG_lo_119 + or REG_lo_120 + or REG_lo_121 + or REG_lo_122 + or REG_lo_123 + or REG_lo_124 + or REG_lo_125 + or REG_lo_126 + or REG_lo_127 + or REG_lo_128 + or REG_lo_129 + or REG_lo_130 + or REG_lo_131 + or REG_lo_132 + or REG_lo_133 + or REG_lo_134 + or REG_lo_135 + or REG_lo_136 + or REG_lo_137 + or REG_lo_138 + or REG_lo_139 + or REG_lo_140 + or REG_lo_141 + or REG_lo_142 + or REG_lo_143 + or REG_lo_144 + or REG_lo_145 + or REG_lo_146 + or REG_lo_147 + or REG_lo_148 + or REG_lo_149 + or REG_lo_150 + or REG_lo_151 + or REG_lo_152 + or REG_lo_153 + or REG_lo_154 + or REG_lo_155 + or REG_lo_156 + or REG_lo_157 + or REG_lo_158 + or REG_lo_159 + or REG_lo_160 + or REG_lo_161 + or REG_lo_162 + or REG_lo_163 + or REG_lo_164 + or REG_lo_165 + or REG_lo_166 + or REG_lo_167 + or REG_lo_168 + or REG_lo_169 + or REG_lo_170 + or REG_lo_171 + or REG_lo_172 + or REG_lo_173 + or REG_lo_174 + or REG_lo_175 + or REG_lo_176 + or REG_lo_177 + or REG_lo_178 + or REG_lo_179 + or REG_lo_180 + or REG_lo_181 + or REG_lo_182 + or REG_lo_183 + or REG_lo_184 + or REG_lo_185 + or REG_lo_186 + or REG_lo_187 + or REG_lo_188 + or REG_lo_189 + or REG_lo_190 + or REG_lo_191 + or REG_lo_192 + or REG_lo_193 + or REG_lo_194 + or REG_lo_195 + or REG_lo_196 + or REG_lo_197 + or REG_lo_198 + or REG_lo_199 + or REG_lo_200 + or REG_lo_201 + or REG_lo_202 + or REG_lo_203 + or REG_lo_204 + or REG_lo_205 + or REG_lo_206 + or REG_lo_207 + or REG_lo_208 + or REG_lo_209 + or REG_lo_210 + or REG_lo_211 + or REG_lo_212 + or REG_lo_213 + or REG_lo_214 + or REG_lo_215 + or REG_lo_216 + or REG_lo_217 + or REG_lo_218 + or REG_lo_219 + or REG_lo_220 + or REG_lo_221 + or REG_lo_222 + or REG_lo_223 + or REG_lo_224 + or REG_lo_225 + or REG_lo_226 + or REG_lo_227 + or REG_lo_228 + or REG_lo_229 + or REG_lo_230 + or REG_lo_231 + or REG_lo_232 + or REG_lo_233 + or REG_lo_234 + or REG_lo_235 + or REG_lo_236 + or REG_lo_237 + or REG_lo_238 + or REG_lo_239 + or REG_lo_240 + or REG_lo_241 + or REG_lo_242 + or REG_lo_243 + or REG_lo_244 + or REG_lo_245 + or REG_lo_246 + or REG_lo_247 + or REG_lo_248 + or REG_lo_249 + or REG_lo_250 + or REG_lo_251 + or REG_lo_252 + or REG_lo_253 + or REG_lo_254 + or REG_lo_255 + or REG_lo_256 + ) begin + case (pro_in_addr) +0: lo_lut_data = REG_lo_0; +1: lo_lut_data = REG_lo_1; +2: lo_lut_data = REG_lo_2; +3: lo_lut_data = REG_lo_3; +4: lo_lut_data = REG_lo_4; +5: lo_lut_data = REG_lo_5; +6: lo_lut_data = REG_lo_6; +7: lo_lut_data = REG_lo_7; +8: lo_lut_data = REG_lo_8; +9: lo_lut_data = REG_lo_9; +10: lo_lut_data = REG_lo_10; +11: lo_lut_data = REG_lo_11; +12: lo_lut_data = REG_lo_12; +13: lo_lut_data = REG_lo_13; +14: lo_lut_data = REG_lo_14; +15: lo_lut_data = REG_lo_15; +16: lo_lut_data = REG_lo_16; +17: lo_lut_data = REG_lo_17; +18: lo_lut_data = REG_lo_18; +19: lo_lut_data = REG_lo_19; +20: lo_lut_data = REG_lo_20; +21: lo_lut_data = REG_lo_21; +22: lo_lut_data = REG_lo_22; +23: lo_lut_data = REG_lo_23; +24: lo_lut_data = REG_lo_24; +25: lo_lut_data = REG_lo_25; +26: lo_lut_data = REG_lo_26; +27: lo_lut_data = REG_lo_27; +28: lo_lut_data = REG_lo_28; +29: lo_lut_data = REG_lo_29; +30: lo_lut_data = REG_lo_30; +31: lo_lut_data = REG_lo_31; +32: lo_lut_data = REG_lo_32; +33: lo_lut_data = REG_lo_33; +34: lo_lut_data = REG_lo_34; +35: lo_lut_data = REG_lo_35; +36: lo_lut_data = REG_lo_36; +37: lo_lut_data = REG_lo_37; +38: lo_lut_data = REG_lo_38; +39: lo_lut_data = REG_lo_39; +40: lo_lut_data = REG_lo_40; +41: lo_lut_data = REG_lo_41; +42: lo_lut_data = REG_lo_42; +43: lo_lut_data = REG_lo_43; +44: lo_lut_data = REG_lo_44; +45: lo_lut_data = REG_lo_45; +46: lo_lut_data = REG_lo_46; +47: lo_lut_data = REG_lo_47; +48: lo_lut_data = REG_lo_48; +49: lo_lut_data = REG_lo_49; +50: lo_lut_data = REG_lo_50; +51: lo_lut_data = REG_lo_51; +52: lo_lut_data = REG_lo_52; +53: lo_lut_data = REG_lo_53; +54: lo_lut_data = REG_lo_54; +55: lo_lut_data = REG_lo_55; +56: lo_lut_data = REG_lo_56; +57: lo_lut_data = REG_lo_57; +58: lo_lut_data = REG_lo_58; +59: lo_lut_data = REG_lo_59; +60: lo_lut_data = REG_lo_60; +61: lo_lut_data = REG_lo_61; +62: lo_lut_data = REG_lo_62; +63: lo_lut_data = REG_lo_63; +64: lo_lut_data = REG_lo_64; +65: lo_lut_data = REG_lo_65; +66: lo_lut_data = REG_lo_66; +67: lo_lut_data = REG_lo_67; +68: lo_lut_data = REG_lo_68; +69: lo_lut_data = REG_lo_69; +70: lo_lut_data = REG_lo_70; +71: lo_lut_data = REG_lo_71; +72: lo_lut_data = REG_lo_72; +73: lo_lut_data = REG_lo_73; +74: lo_lut_data = REG_lo_74; +75: lo_lut_data = REG_lo_75; +76: lo_lut_data = REG_lo_76; +77: lo_lut_data = REG_lo_77; +78: lo_lut_data = REG_lo_78; +79: lo_lut_data = REG_lo_79; +80: lo_lut_data = REG_lo_80; +81: lo_lut_data = REG_lo_81; +82: lo_lut_data = REG_lo_82; +83: lo_lut_data = REG_lo_83; +84: lo_lut_data = REG_lo_84; +85: lo_lut_data = REG_lo_85; +86: lo_lut_data = REG_lo_86; +87: lo_lut_data = REG_lo_87; +88: lo_lut_data = REG_lo_88; +89: lo_lut_data = REG_lo_89; +90: lo_lut_data = REG_lo_90; +91: lo_lut_data = REG_lo_91; +92: lo_lut_data = REG_lo_92; +93: lo_lut_data = REG_lo_93; +94: lo_lut_data = REG_lo_94; +95: lo_lut_data = REG_lo_95; +96: lo_lut_data = REG_lo_96; +97: lo_lut_data = REG_lo_97; +98: lo_lut_data = REG_lo_98; +99: lo_lut_data = REG_lo_99; +100: lo_lut_data = REG_lo_100; +101: lo_lut_data = REG_lo_101; +102: lo_lut_data = REG_lo_102; +103: lo_lut_data = REG_lo_103; +104: lo_lut_data = REG_lo_104; +105: lo_lut_data = REG_lo_105; +106: lo_lut_data = REG_lo_106; +107: lo_lut_data = REG_lo_107; +108: lo_lut_data = REG_lo_108; +109: lo_lut_data = REG_lo_109; +110: lo_lut_data = REG_lo_110; +111: lo_lut_data = REG_lo_111; +112: lo_lut_data = REG_lo_112; +113: lo_lut_data = REG_lo_113; +114: lo_lut_data = REG_lo_114; +115: lo_lut_data = REG_lo_115; +116: lo_lut_data = REG_lo_116; +117: lo_lut_data = REG_lo_117; +118: lo_lut_data = REG_lo_118; +119: lo_lut_data = REG_lo_119; +120: lo_lut_data = REG_lo_120; +121: lo_lut_data = REG_lo_121; +122: lo_lut_data = REG_lo_122; +123: lo_lut_data = REG_lo_123; +124: lo_lut_data = REG_lo_124; +125: lo_lut_data = REG_lo_125; +126: lo_lut_data = REG_lo_126; +127: lo_lut_data = REG_lo_127; +128: lo_lut_data = REG_lo_128; +129: lo_lut_data = REG_lo_129; +130: lo_lut_data = REG_lo_130; +131: lo_lut_data = REG_lo_131; +132: lo_lut_data = REG_lo_132; +133: lo_lut_data = REG_lo_133; +134: lo_lut_data = REG_lo_134; +135: lo_lut_data = REG_lo_135; +136: lo_lut_data = REG_lo_136; +137: lo_lut_data = REG_lo_137; +138: lo_lut_data = REG_lo_138; +139: lo_lut_data = REG_lo_139; +140: lo_lut_data = REG_lo_140; +141: lo_lut_data = REG_lo_141; +142: lo_lut_data = REG_lo_142; +143: lo_lut_data = REG_lo_143; +144: lo_lut_data = REG_lo_144; +145: lo_lut_data = REG_lo_145; +146: lo_lut_data = REG_lo_146; +147: lo_lut_data = REG_lo_147; +148: lo_lut_data = REG_lo_148; +149: lo_lut_data = REG_lo_149; +150: lo_lut_data = REG_lo_150; +151: lo_lut_data = REG_lo_151; +152: lo_lut_data = REG_lo_152; +153: lo_lut_data = REG_lo_153; +154: lo_lut_data = REG_lo_154; +155: lo_lut_data = REG_lo_155; +156: lo_lut_data = REG_lo_156; +157: lo_lut_data = REG_lo_157; +158: lo_lut_data = REG_lo_158; +159: lo_lut_data = REG_lo_159; +160: lo_lut_data = REG_lo_160; +161: lo_lut_data = REG_lo_161; +162: lo_lut_data = REG_lo_162; +163: lo_lut_data = REG_lo_163; +164: lo_lut_data = REG_lo_164; +165: lo_lut_data = REG_lo_165; +166: lo_lut_data = REG_lo_166; +167: lo_lut_data = REG_lo_167; +168: lo_lut_data = REG_lo_168; +169: lo_lut_data = REG_lo_169; +170: lo_lut_data = REG_lo_170; +171: lo_lut_data = REG_lo_171; +172: lo_lut_data = REG_lo_172; +173: lo_lut_data = REG_lo_173; +174: lo_lut_data = REG_lo_174; +175: lo_lut_data = REG_lo_175; +176: lo_lut_data = REG_lo_176; +177: lo_lut_data = REG_lo_177; +178: lo_lut_data = REG_lo_178; +179: lo_lut_data = REG_lo_179; +180: lo_lut_data = REG_lo_180; +181: lo_lut_data = REG_lo_181; +182: lo_lut_data = REG_lo_182; +183: lo_lut_data = REG_lo_183; +184: lo_lut_data = REG_lo_184; +185: lo_lut_data = REG_lo_185; +186: lo_lut_data = REG_lo_186; +187: lo_lut_data = REG_lo_187; +188: lo_lut_data = REG_lo_188; +189: lo_lut_data = REG_lo_189; +190: lo_lut_data = REG_lo_190; +191: lo_lut_data = REG_lo_191; +192: lo_lut_data = REG_lo_192; +193: lo_lut_data = REG_lo_193; +194: lo_lut_data = REG_lo_194; +195: lo_lut_data = REG_lo_195; +196: lo_lut_data = REG_lo_196; +197: lo_lut_data = REG_lo_197; +198: lo_lut_data = REG_lo_198; +199: lo_lut_data = REG_lo_199; +200: lo_lut_data = REG_lo_200; +201: lo_lut_data = REG_lo_201; +202: lo_lut_data = REG_lo_202; +203: lo_lut_data = REG_lo_203; +204: lo_lut_data = REG_lo_204; +205: lo_lut_data = REG_lo_205; +206: lo_lut_data = REG_lo_206; +207: lo_lut_data = REG_lo_207; +208: lo_lut_data = REG_lo_208; +209: lo_lut_data = REG_lo_209; +210: lo_lut_data = REG_lo_210; +211: lo_lut_data = REG_lo_211; +212: lo_lut_data = REG_lo_212; +213: lo_lut_data = REG_lo_213; +214: lo_lut_data = REG_lo_214; +215: lo_lut_data = REG_lo_215; +216: lo_lut_data = REG_lo_216; +217: lo_lut_data = REG_lo_217; +218: lo_lut_data = REG_lo_218; +219: lo_lut_data = REG_lo_219; +220: lo_lut_data = REG_lo_220; +221: lo_lut_data = REG_lo_221; +222: lo_lut_data = REG_lo_222; +223: lo_lut_data = REG_lo_223; +224: lo_lut_data = REG_lo_224; +225: lo_lut_data = REG_lo_225; +226: lo_lut_data = REG_lo_226; +227: lo_lut_data = REG_lo_227; +228: lo_lut_data = REG_lo_228; +229: lo_lut_data = REG_lo_229; +230: lo_lut_data = REG_lo_230; +231: lo_lut_data = REG_lo_231; +232: lo_lut_data = REG_lo_232; +233: lo_lut_data = REG_lo_233; +234: lo_lut_data = REG_lo_234; +235: lo_lut_data = REG_lo_235; +236: lo_lut_data = REG_lo_236; +237: lo_lut_data = REG_lo_237; +238: lo_lut_data = REG_lo_238; +239: lo_lut_data = REG_lo_239; +240: lo_lut_data = REG_lo_240; +241: lo_lut_data = REG_lo_241; +242: lo_lut_data = REG_lo_242; +243: lo_lut_data = REG_lo_243; +244: lo_lut_data = REG_lo_244; +245: lo_lut_data = REG_lo_245; +246: lo_lut_data = REG_lo_246; +247: lo_lut_data = REG_lo_247; +248: lo_lut_data = REG_lo_248; +249: lo_lut_data = REG_lo_249; +250: lo_lut_data = REG_lo_250; +251: lo_lut_data = REG_lo_251; +252: lo_lut_data = REG_lo_252; +253: lo_lut_data = REG_lo_253; +254: lo_lut_data = REG_lo_254; +255: lo_lut_data = REG_lo_255; +256: lo_lut_data = REG_lo_256; +//VCS coverage off + default : begin + lo_lut_data[15:0] = {16{`x_or_0}}; + end +//VCS coverage on + endcase +end +assign dp2reg_lut_int_data = pro_in_select_le ? le_lut_data : lo_lut_data; +//======================================= +// WRITE LUT +assign le_wr_en_0 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_0 <= {16{1'b0}}; + end else begin + if ((le_wr_en_0) == 1'b1) begin + REG_le_0 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_0) == 1'b0) begin + end else begin + REG_le_0 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_0))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_1 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_1 <= {16{1'b0}}; + end else begin + if ((le_wr_en_1) == 1'b1) begin + REG_le_1 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_1) == 1'b0) begin + end else begin + REG_le_1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_2 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==2); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_2 <= {16{1'b0}}; + end else begin + if ((le_wr_en_2) == 1'b1) begin + REG_le_2 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_2) == 1'b0) begin + end else begin + REG_le_2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_2))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_3 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==3); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_3 <= {16{1'b0}}; + end else begin + if ((le_wr_en_3) == 1'b1) begin + REG_le_3 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_3) == 1'b0) begin + end else begin + REG_le_3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_3))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_4 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==4); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_4 <= {16{1'b0}}; + end else begin + if ((le_wr_en_4) == 1'b1) begin + REG_le_4 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_4) == 1'b0) begin + end else begin + REG_le_4 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_4))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_5 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==5); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_5 <= {16{1'b0}}; + end else begin + if ((le_wr_en_5) == 1'b1) begin + REG_le_5 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_5) == 1'b0) begin + end else begin + REG_le_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_5))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_6 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==6); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_6 <= {16{1'b0}}; + end else begin + if ((le_wr_en_6) == 1'b1) begin + REG_le_6 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_6) == 1'b0) begin + end else begin + REG_le_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_6))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_7 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==7); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_7 <= {16{1'b0}}; + end else begin + if ((le_wr_en_7) == 1'b1) begin + REG_le_7 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_7) == 1'b0) begin + end else begin + REG_le_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_7))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_8 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==8); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_8 <= {16{1'b0}}; + end else begin + if ((le_wr_en_8) == 1'b1) begin + REG_le_8 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_8) == 1'b0) begin + end else begin + REG_le_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_8))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_9 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==9); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_9 <= {16{1'b0}}; + end else begin + if ((le_wr_en_9) == 1'b1) begin + REG_le_9 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_9) == 1'b0) begin + end else begin + REG_le_9 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_9))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_10 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==10); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_10 <= {16{1'b0}}; + end else begin + if ((le_wr_en_10) == 1'b1) begin + REG_le_10 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_10) == 1'b0) begin + end else begin + REG_le_10 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_10))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_11 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==11); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_11 <= {16{1'b0}}; + end else begin + if ((le_wr_en_11) == 1'b1) begin + REG_le_11 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_11) == 1'b0) begin + end else begin + REG_le_11 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_11))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_12 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==12); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_12 <= {16{1'b0}}; + end else begin + if ((le_wr_en_12) == 1'b1) begin + REG_le_12 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_12) == 1'b0) begin + end else begin + REG_le_12 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_12))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_13 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==13); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_13 <= {16{1'b0}}; + end else begin + if ((le_wr_en_13) == 1'b1) begin + REG_le_13 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_13) == 1'b0) begin + end else begin + REG_le_13 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_13))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_14 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==14); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_14 <= {16{1'b0}}; + end else begin + if ((le_wr_en_14) == 1'b1) begin + REG_le_14 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_14) == 1'b0) begin + end else begin + REG_le_14 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_14))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_15 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==15); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_15 <= {16{1'b0}}; + end else begin + if ((le_wr_en_15) == 1'b1) begin + REG_le_15 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_15) == 1'b0) begin + end else begin + REG_le_15 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_15))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_16 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==16); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_16 <= {16{1'b0}}; + end else begin + if ((le_wr_en_16) == 1'b1) begin + REG_le_16 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_16) == 1'b0) begin + end else begin + REG_le_16 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_16))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_17 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==17); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_17 <= {16{1'b0}}; + end else begin + if ((le_wr_en_17) == 1'b1) begin + REG_le_17 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_17) == 1'b0) begin + end else begin + REG_le_17 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_17))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_18 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==18); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_18 <= {16{1'b0}}; + end else begin + if ((le_wr_en_18) == 1'b1) begin + REG_le_18 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_18) == 1'b0) begin + end else begin + REG_le_18 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_18))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_19 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==19); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_19 <= {16{1'b0}}; + end else begin + if ((le_wr_en_19) == 1'b1) begin + REG_le_19 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_19) == 1'b0) begin + end else begin + REG_le_19 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_19))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_20 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==20); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_20 <= {16{1'b0}}; + end else begin + if ((le_wr_en_20) == 1'b1) begin + REG_le_20 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_20) == 1'b0) begin + end else begin + REG_le_20 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_20))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_21 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==21); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_21 <= {16{1'b0}}; + end else begin + if ((le_wr_en_21) == 1'b1) begin + REG_le_21 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_21) == 1'b0) begin + end else begin + REG_le_21 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_21))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_22 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==22); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_22 <= {16{1'b0}}; + end else begin + if ((le_wr_en_22) == 1'b1) begin + REG_le_22 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_22) == 1'b0) begin + end else begin + REG_le_22 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_22))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_23 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==23); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_23 <= {16{1'b0}}; + end else begin + if ((le_wr_en_23) == 1'b1) begin + REG_le_23 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_23) == 1'b0) begin + end else begin + REG_le_23 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_23))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_24 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==24); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_24 <= {16{1'b0}}; + end else begin + if ((le_wr_en_24) == 1'b1) begin + REG_le_24 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_24) == 1'b0) begin + end else begin + REG_le_24 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_24))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_25 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==25); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_25 <= {16{1'b0}}; + end else begin + if ((le_wr_en_25) == 1'b1) begin + REG_le_25 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_25) == 1'b0) begin + end else begin + REG_le_25 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_25))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_26 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==26); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_26 <= {16{1'b0}}; + end else begin + if ((le_wr_en_26) == 1'b1) begin + REG_le_26 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_26) == 1'b0) begin + end else begin + REG_le_26 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_26))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_27 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==27); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_27 <= {16{1'b0}}; + end else begin + if ((le_wr_en_27) == 1'b1) begin + REG_le_27 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_27) == 1'b0) begin + end else begin + REG_le_27 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_27))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_28 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==28); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_28 <= {16{1'b0}}; + end else begin + if ((le_wr_en_28) == 1'b1) begin + REG_le_28 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_28) == 1'b0) begin + end else begin + REG_le_28 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_28))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_29 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==29); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_29 <= {16{1'b0}}; + end else begin + if ((le_wr_en_29) == 1'b1) begin + REG_le_29 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_29) == 1'b0) begin + end else begin + REG_le_29 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_29))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_30 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==30); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_30 <= {16{1'b0}}; + end else begin + if ((le_wr_en_30) == 1'b1) begin + REG_le_30 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_30) == 1'b0) begin + end else begin + REG_le_30 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_30))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_31 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==31); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_31 <= {16{1'b0}}; + end else begin + if ((le_wr_en_31) == 1'b1) begin + REG_le_31 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_31) == 1'b0) begin + end else begin + REG_le_31 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_31))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_32 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==32); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_32 <= {16{1'b0}}; + end else begin + if ((le_wr_en_32) == 1'b1) begin + REG_le_32 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_32) == 1'b0) begin + end else begin + REG_le_32 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_32))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_33 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==33); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_33 <= {16{1'b0}}; + end else begin + if ((le_wr_en_33) == 1'b1) begin + REG_le_33 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_33) == 1'b0) begin + end else begin + REG_le_33 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_33))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_34 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==34); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_34 <= {16{1'b0}}; + end else begin + if ((le_wr_en_34) == 1'b1) begin + REG_le_34 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_34) == 1'b0) begin + end else begin + REG_le_34 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_34))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_35 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==35); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_35 <= {16{1'b0}}; + end else begin + if ((le_wr_en_35) == 1'b1) begin + REG_le_35 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_35) == 1'b0) begin + end else begin + REG_le_35 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_35))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_36 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==36); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_36 <= {16{1'b0}}; + end else begin + if ((le_wr_en_36) == 1'b1) begin + REG_le_36 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_36) == 1'b0) begin + end else begin + REG_le_36 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_36))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_37 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==37); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_37 <= {16{1'b0}}; + end else begin + if ((le_wr_en_37) == 1'b1) begin + REG_le_37 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_37) == 1'b0) begin + end else begin + REG_le_37 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_37))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_38 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==38); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_38 <= {16{1'b0}}; + end else begin + if ((le_wr_en_38) == 1'b1) begin + REG_le_38 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_38) == 1'b0) begin + end else begin + REG_le_38 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_38))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_39 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==39); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_39 <= {16{1'b0}}; + end else begin + if ((le_wr_en_39) == 1'b1) begin + REG_le_39 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_39) == 1'b0) begin + end else begin + REG_le_39 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_39))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_40 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==40); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_40 <= {16{1'b0}}; + end else begin + if ((le_wr_en_40) == 1'b1) begin + REG_le_40 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_40) == 1'b0) begin + end else begin + REG_le_40 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_40))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_41 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==41); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_41 <= {16{1'b0}}; + end else begin + if ((le_wr_en_41) == 1'b1) begin + REG_le_41 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_41) == 1'b0) begin + end else begin + REG_le_41 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_41))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_42 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==42); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_42 <= {16{1'b0}}; + end else begin + if ((le_wr_en_42) == 1'b1) begin + REG_le_42 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_42) == 1'b0) begin + end else begin + REG_le_42 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_42))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_43 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==43); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_43 <= {16{1'b0}}; + end else begin + if ((le_wr_en_43) == 1'b1) begin + REG_le_43 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_43) == 1'b0) begin + end else begin + REG_le_43 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_43))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_44 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==44); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_44 <= {16{1'b0}}; + end else begin + if ((le_wr_en_44) == 1'b1) begin + REG_le_44 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_44) == 1'b0) begin + end else begin + REG_le_44 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_45x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_44))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_45 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==45); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_45 <= {16{1'b0}}; + end else begin + if ((le_wr_en_45) == 1'b1) begin + REG_le_45 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_45) == 1'b0) begin + end else begin + REG_le_45 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_46x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_45))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_46 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==46); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_46 <= {16{1'b0}}; + end else begin + if ((le_wr_en_46) == 1'b1) begin + REG_le_46 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_46) == 1'b0) begin + end else begin + REG_le_46 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_47x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_46))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_47 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==47); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_47 <= {16{1'b0}}; + end else begin + if ((le_wr_en_47) == 1'b1) begin + REG_le_47 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_47) == 1'b0) begin + end else begin + REG_le_47 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_48x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_47))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_48 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==48); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_48 <= {16{1'b0}}; + end else begin + if ((le_wr_en_48) == 1'b1) begin + REG_le_48 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_48) == 1'b0) begin + end else begin + REG_le_48 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_49x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_48))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_49 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==49); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_49 <= {16{1'b0}}; + end else begin + if ((le_wr_en_49) == 1'b1) begin + REG_le_49 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_49) == 1'b0) begin + end else begin + REG_le_49 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_50x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_49))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_50 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==50); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_50 <= {16{1'b0}}; + end else begin + if ((le_wr_en_50) == 1'b1) begin + REG_le_50 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_50) == 1'b0) begin + end else begin + REG_le_50 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_50))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_51 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==51); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_51 <= {16{1'b0}}; + end else begin + if ((le_wr_en_51) == 1'b1) begin + REG_le_51 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_51) == 1'b0) begin + end else begin + REG_le_51 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_51))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_52 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==52); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_52 <= {16{1'b0}}; + end else begin + if ((le_wr_en_52) == 1'b1) begin + REG_le_52 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_52) == 1'b0) begin + end else begin + REG_le_52 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_52))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_53 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==53); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_53 <= {16{1'b0}}; + end else begin + if ((le_wr_en_53) == 1'b1) begin + REG_le_53 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_53) == 1'b0) begin + end else begin + REG_le_53 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_53))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_54 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==54); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_54 <= {16{1'b0}}; + end else begin + if ((le_wr_en_54) == 1'b1) begin + REG_le_54 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_54) == 1'b0) begin + end else begin + REG_le_54 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_54))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_55 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==55); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_55 <= {16{1'b0}}; + end else begin + if ((le_wr_en_55) == 1'b1) begin + REG_le_55 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_55) == 1'b0) begin + end else begin + REG_le_55 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_55))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_56 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==56); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_56 <= {16{1'b0}}; + end else begin + if ((le_wr_en_56) == 1'b1) begin + REG_le_56 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_56) == 1'b0) begin + end else begin + REG_le_56 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_56))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_57 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==57); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_57 <= {16{1'b0}}; + end else begin + if ((le_wr_en_57) == 1'b1) begin + REG_le_57 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_57) == 1'b0) begin + end else begin + REG_le_57 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_57))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_58 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==58); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_58 <= {16{1'b0}}; + end else begin + if ((le_wr_en_58) == 1'b1) begin + REG_le_58 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_58) == 1'b0) begin + end else begin + REG_le_58 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_58))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_59 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==59); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_59 <= {16{1'b0}}; + end else begin + if ((le_wr_en_59) == 1'b1) begin + REG_le_59 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_59) == 1'b0) begin + end else begin + REG_le_59 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_59))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_60 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==60); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_60 <= {16{1'b0}}; + end else begin + if ((le_wr_en_60) == 1'b1) begin + REG_le_60 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_60) == 1'b0) begin + end else begin + REG_le_60 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_60))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_61 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==61); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_61 <= {16{1'b0}}; + end else begin + if ((le_wr_en_61) == 1'b1) begin + REG_le_61 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_61) == 1'b0) begin + end else begin + REG_le_61 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_61))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_62 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==62); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_62 <= {16{1'b0}}; + end else begin + if ((le_wr_en_62) == 1'b1) begin + REG_le_62 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_62) == 1'b0) begin + end else begin + REG_le_62 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_63x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_62))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_63 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==63); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_63 <= {16{1'b0}}; + end else begin + if ((le_wr_en_63) == 1'b1) begin + REG_le_63 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_63) == 1'b0) begin + end else begin + REG_le_63 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_63))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_64 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==64); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_64 <= {16{1'b0}}; + end else begin + if ((le_wr_en_64) == 1'b1) begin + REG_le_64 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_64) == 1'b0) begin + end else begin + REG_le_64 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_64))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign REG_le_65 = {16{`tick_x_or_0}}; +assign REG_le_66 = {16{`tick_x_or_0}}; +assign REG_le_67 = {16{`tick_x_or_0}}; +assign REG_le_68 = {16{`tick_x_or_0}}; +assign REG_le_69 = {16{`tick_x_or_0}}; +assign REG_le_70 = {16{`tick_x_or_0}}; +assign REG_le_71 = {16{`tick_x_or_0}}; +assign REG_le_72 = {16{`tick_x_or_0}}; +assign REG_le_73 = {16{`tick_x_or_0}}; +assign REG_le_74 = {16{`tick_x_or_0}}; +assign REG_le_75 = {16{`tick_x_or_0}}; +assign REG_le_76 = {16{`tick_x_or_0}}; +assign REG_le_77 = {16{`tick_x_or_0}}; +assign REG_le_78 = {16{`tick_x_or_0}}; +assign REG_le_79 = {16{`tick_x_or_0}}; +assign REG_le_80 = {16{`tick_x_or_0}}; +assign REG_le_81 = {16{`tick_x_or_0}}; +assign REG_le_82 = {16{`tick_x_or_0}}; +assign REG_le_83 = {16{`tick_x_or_0}}; +assign REG_le_84 = {16{`tick_x_or_0}}; +assign REG_le_85 = {16{`tick_x_or_0}}; +assign REG_le_86 = {16{`tick_x_or_0}}; +assign REG_le_87 = {16{`tick_x_or_0}}; +assign REG_le_88 = {16{`tick_x_or_0}}; +assign REG_le_89 = {16{`tick_x_or_0}}; +assign REG_le_90 = {16{`tick_x_or_0}}; +assign REG_le_91 = {16{`tick_x_or_0}}; +assign REG_le_92 = {16{`tick_x_or_0}}; +assign REG_le_93 = {16{`tick_x_or_0}}; +assign REG_le_94 = {16{`tick_x_or_0}}; +assign REG_le_95 = {16{`tick_x_or_0}}; +assign REG_le_96 = {16{`tick_x_or_0}}; +assign REG_le_97 = {16{`tick_x_or_0}}; +assign REG_le_98 = {16{`tick_x_or_0}}; +assign REG_le_99 = {16{`tick_x_or_0}}; +assign REG_le_100 = {16{`tick_x_or_0}}; +assign REG_le_101 = {16{`tick_x_or_0}}; +assign REG_le_102 = {16{`tick_x_or_0}}; +assign REG_le_103 = {16{`tick_x_or_0}}; +assign REG_le_104 = {16{`tick_x_or_0}}; +assign REG_le_105 = {16{`tick_x_or_0}}; +assign REG_le_106 = {16{`tick_x_or_0}}; +assign REG_le_107 = {16{`tick_x_or_0}}; +assign REG_le_108 = {16{`tick_x_or_0}}; +assign REG_le_109 = {16{`tick_x_or_0}}; +assign REG_le_110 = {16{`tick_x_or_0}}; +assign REG_le_111 = {16{`tick_x_or_0}}; +assign REG_le_112 = {16{`tick_x_or_0}}; +assign REG_le_113 = {16{`tick_x_or_0}}; +assign REG_le_114 = {16{`tick_x_or_0}}; +assign REG_le_115 = {16{`tick_x_or_0}}; +assign REG_le_116 = {16{`tick_x_or_0}}; +assign REG_le_117 = {16{`tick_x_or_0}}; +assign REG_le_118 = {16{`tick_x_or_0}}; +assign REG_le_119 = {16{`tick_x_or_0}}; +assign REG_le_120 = {16{`tick_x_or_0}}; +assign REG_le_121 = {16{`tick_x_or_0}}; +assign REG_le_122 = {16{`tick_x_or_0}}; +assign REG_le_123 = {16{`tick_x_or_0}}; +assign REG_le_124 = {16{`tick_x_or_0}}; +assign REG_le_125 = {16{`tick_x_or_0}}; +assign REG_le_126 = {16{`tick_x_or_0}}; +assign REG_le_127 = {16{`tick_x_or_0}}; +assign REG_le_128 = {16{`tick_x_or_0}}; +assign REG_le_129 = {16{`tick_x_or_0}}; +assign REG_le_130 = {16{`tick_x_or_0}}; +assign REG_le_131 = {16{`tick_x_or_0}}; +assign REG_le_132 = {16{`tick_x_or_0}}; +assign REG_le_133 = {16{`tick_x_or_0}}; +assign REG_le_134 = {16{`tick_x_or_0}}; +assign REG_le_135 = {16{`tick_x_or_0}}; +assign REG_le_136 = {16{`tick_x_or_0}}; +assign REG_le_137 = {16{`tick_x_or_0}}; +assign REG_le_138 = {16{`tick_x_or_0}}; +assign REG_le_139 = {16{`tick_x_or_0}}; +assign REG_le_140 = {16{`tick_x_or_0}}; +assign REG_le_141 = {16{`tick_x_or_0}}; +assign REG_le_142 = {16{`tick_x_or_0}}; +assign REG_le_143 = {16{`tick_x_or_0}}; +assign REG_le_144 = {16{`tick_x_or_0}}; +assign REG_le_145 = {16{`tick_x_or_0}}; +assign REG_le_146 = {16{`tick_x_or_0}}; +assign REG_le_147 = {16{`tick_x_or_0}}; +assign REG_le_148 = {16{`tick_x_or_0}}; +assign REG_le_149 = {16{`tick_x_or_0}}; +assign REG_le_150 = {16{`tick_x_or_0}}; +assign REG_le_151 = {16{`tick_x_or_0}}; +assign REG_le_152 = {16{`tick_x_or_0}}; +assign REG_le_153 = {16{`tick_x_or_0}}; +assign REG_le_154 = {16{`tick_x_or_0}}; +assign REG_le_155 = {16{`tick_x_or_0}}; +assign REG_le_156 = {16{`tick_x_or_0}}; +assign REG_le_157 = {16{`tick_x_or_0}}; +assign REG_le_158 = {16{`tick_x_or_0}}; +assign REG_le_159 = {16{`tick_x_or_0}}; +assign REG_le_160 = {16{`tick_x_or_0}}; +assign REG_le_161 = {16{`tick_x_or_0}}; +assign REG_le_162 = {16{`tick_x_or_0}}; +assign REG_le_163 = {16{`tick_x_or_0}}; +assign REG_le_164 = {16{`tick_x_or_0}}; +assign REG_le_165 = {16{`tick_x_or_0}}; +assign REG_le_166 = {16{`tick_x_or_0}}; +assign REG_le_167 = {16{`tick_x_or_0}}; +assign REG_le_168 = {16{`tick_x_or_0}}; +assign REG_le_169 = {16{`tick_x_or_0}}; +assign REG_le_170 = {16{`tick_x_or_0}}; +assign REG_le_171 = {16{`tick_x_or_0}}; +assign REG_le_172 = {16{`tick_x_or_0}}; +assign REG_le_173 = {16{`tick_x_or_0}}; +assign REG_le_174 = {16{`tick_x_or_0}}; +assign REG_le_175 = {16{`tick_x_or_0}}; +assign REG_le_176 = {16{`tick_x_or_0}}; +assign REG_le_177 = {16{`tick_x_or_0}}; +assign REG_le_178 = {16{`tick_x_or_0}}; +assign REG_le_179 = {16{`tick_x_or_0}}; +assign REG_le_180 = {16{`tick_x_or_0}}; +assign REG_le_181 = {16{`tick_x_or_0}}; +assign REG_le_182 = {16{`tick_x_or_0}}; +assign REG_le_183 = {16{`tick_x_or_0}}; +assign REG_le_184 = {16{`tick_x_or_0}}; +assign REG_le_185 = {16{`tick_x_or_0}}; +assign REG_le_186 = {16{`tick_x_or_0}}; +assign REG_le_187 = {16{`tick_x_or_0}}; +assign REG_le_188 = {16{`tick_x_or_0}}; +assign REG_le_189 = {16{`tick_x_or_0}}; +assign REG_le_190 = {16{`tick_x_or_0}}; +assign REG_le_191 = {16{`tick_x_or_0}}; +assign REG_le_192 = {16{`tick_x_or_0}}; +assign REG_le_193 = {16{`tick_x_or_0}}; +assign REG_le_194 = {16{`tick_x_or_0}}; +assign REG_le_195 = {16{`tick_x_or_0}}; +assign REG_le_196 = {16{`tick_x_or_0}}; +assign REG_le_197 = {16{`tick_x_or_0}}; +assign REG_le_198 = {16{`tick_x_or_0}}; +assign REG_le_199 = {16{`tick_x_or_0}}; +assign REG_le_200 = {16{`tick_x_or_0}}; +assign REG_le_201 = {16{`tick_x_or_0}}; +assign REG_le_202 = {16{`tick_x_or_0}}; +assign REG_le_203 = {16{`tick_x_or_0}}; +assign REG_le_204 = {16{`tick_x_or_0}}; +assign REG_le_205 = {16{`tick_x_or_0}}; +assign REG_le_206 = {16{`tick_x_or_0}}; +assign REG_le_207 = {16{`tick_x_or_0}}; +assign REG_le_208 = {16{`tick_x_or_0}}; +assign REG_le_209 = {16{`tick_x_or_0}}; +assign REG_le_210 = {16{`tick_x_or_0}}; +assign REG_le_211 = {16{`tick_x_or_0}}; +assign REG_le_212 = {16{`tick_x_or_0}}; +assign REG_le_213 = {16{`tick_x_or_0}}; +assign REG_le_214 = {16{`tick_x_or_0}}; +assign REG_le_215 = {16{`tick_x_or_0}}; +assign REG_le_216 = {16{`tick_x_or_0}}; +assign REG_le_217 = {16{`tick_x_or_0}}; +assign REG_le_218 = {16{`tick_x_or_0}}; +assign REG_le_219 = {16{`tick_x_or_0}}; +assign REG_le_220 = {16{`tick_x_or_0}}; +assign REG_le_221 = {16{`tick_x_or_0}}; +assign REG_le_222 = {16{`tick_x_or_0}}; +assign REG_le_223 = {16{`tick_x_or_0}}; +assign REG_le_224 = {16{`tick_x_or_0}}; +assign REG_le_225 = {16{`tick_x_or_0}}; +assign REG_le_226 = {16{`tick_x_or_0}}; +assign REG_le_227 = {16{`tick_x_or_0}}; +assign REG_le_228 = {16{`tick_x_or_0}}; +assign REG_le_229 = {16{`tick_x_or_0}}; +assign REG_le_230 = {16{`tick_x_or_0}}; +assign REG_le_231 = {16{`tick_x_or_0}}; +assign REG_le_232 = {16{`tick_x_or_0}}; +assign REG_le_233 = {16{`tick_x_or_0}}; +assign REG_le_234 = {16{`tick_x_or_0}}; +assign REG_le_235 = {16{`tick_x_or_0}}; +assign REG_le_236 = {16{`tick_x_or_0}}; +assign REG_le_237 = {16{`tick_x_or_0}}; +assign REG_le_238 = {16{`tick_x_or_0}}; +assign REG_le_239 = {16{`tick_x_or_0}}; +assign REG_le_240 = {16{`tick_x_or_0}}; +assign REG_le_241 = {16{`tick_x_or_0}}; +assign REG_le_242 = {16{`tick_x_or_0}}; +assign REG_le_243 = {16{`tick_x_or_0}}; +assign REG_le_244 = {16{`tick_x_or_0}}; +assign REG_le_245 = {16{`tick_x_or_0}}; +assign REG_le_246 = {16{`tick_x_or_0}}; +assign REG_le_247 = {16{`tick_x_or_0}}; +assign REG_le_248 = {16{`tick_x_or_0}}; +assign REG_le_249 = {16{`tick_x_or_0}}; +assign REG_le_250 = {16{`tick_x_or_0}}; +assign REG_le_251 = {16{`tick_x_or_0}}; +assign REG_le_252 = {16{`tick_x_or_0}}; +assign REG_le_253 = {16{`tick_x_or_0}}; +assign REG_le_254 = {16{`tick_x_or_0}}; +assign REG_le_255 = {16{`tick_x_or_0}}; +assign REG_le_256 = {16{`tick_x_or_0}}; +assign lo_wr_en_0 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_0 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_0) == 1'b1) begin + REG_lo_0 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_0) == 1'b0) begin + end else begin + REG_lo_0 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_0))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_1 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_1 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_1) == 1'b1) begin + REG_lo_1 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_1) == 1'b0) begin + end else begin + REG_lo_1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_2 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==2); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_2 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_2) == 1'b1) begin + REG_lo_2 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_2) == 1'b0) begin + end else begin + REG_lo_2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_2))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_3 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==3); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_3 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_3) == 1'b1) begin + REG_lo_3 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_3) == 1'b0) begin + end else begin + REG_lo_3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_3))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_4 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==4); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_4 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_4) == 1'b1) begin + REG_lo_4 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_4) == 1'b0) begin + end else begin + REG_lo_4 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_4))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_5 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==5); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_5 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_5) == 1'b1) begin + REG_lo_5 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_5) == 1'b0) begin + end else begin + REG_lo_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_71x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_5))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_6 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==6); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_6 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_6) == 1'b1) begin + REG_lo_6 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_6) == 1'b0) begin + end else begin + REG_lo_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_6))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_7 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==7); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_7 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_7) == 1'b1) begin + REG_lo_7 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_7) == 1'b0) begin + end else begin + REG_lo_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_7))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_8 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==8); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_8 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_8) == 1'b1) begin + REG_lo_8 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_8) == 1'b0) begin + end else begin + REG_lo_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_8))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_9 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==9); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_9 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_9) == 1'b1) begin + REG_lo_9 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_9) == 1'b0) begin + end else begin + REG_lo_9 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_9))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_10 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==10); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_10 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_10) == 1'b1) begin + REG_lo_10 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_10) == 1'b0) begin + end else begin + REG_lo_10 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_10))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_11 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==11); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_11 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_11) == 1'b1) begin + REG_lo_11 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_11) == 1'b0) begin + end else begin + REG_lo_11 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_11))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_12 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==12); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_12 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_12) == 1'b1) begin + REG_lo_12 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_12) == 1'b0) begin + end else begin + REG_lo_12 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_12))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_13 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==13); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_13 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_13) == 1'b1) begin + REG_lo_13 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_13) == 1'b0) begin + end else begin + REG_lo_13 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_13))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_14 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==14); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_14 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_14) == 1'b1) begin + REG_lo_14 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_14) == 1'b0) begin + end else begin + REG_lo_14 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_14))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_15 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==15); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_15 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_15) == 1'b1) begin + REG_lo_15 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_15) == 1'b0) begin + end else begin + REG_lo_15 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_15))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_16 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==16); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_16 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_16) == 1'b1) begin + REG_lo_16 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_16) == 1'b0) begin + end else begin + REG_lo_16 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_16))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_17 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==17); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_17 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_17) == 1'b1) begin + REG_lo_17 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_17) == 1'b0) begin + end else begin + REG_lo_17 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_17))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_18 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==18); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_18 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_18) == 1'b1) begin + REG_lo_18 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_18) == 1'b0) begin + end else begin + REG_lo_18 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_18))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_19 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==19); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_19 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_19) == 1'b1) begin + REG_lo_19 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_19) == 1'b0) begin + end else begin + REG_lo_19 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_85x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_19))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_20 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==20); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_20 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_20) == 1'b1) begin + REG_lo_20 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_20) == 1'b0) begin + end else begin + REG_lo_20 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_20))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_21 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==21); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_21 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_21) == 1'b1) begin + REG_lo_21 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_21) == 1'b0) begin + end else begin + REG_lo_21 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_21))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_22 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==22); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_22 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_22) == 1'b1) begin + REG_lo_22 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_22) == 1'b0) begin + end else begin + REG_lo_22 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_22))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_23 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==23); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_23 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_23) == 1'b1) begin + REG_lo_23 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_23) == 1'b0) begin + end else begin + REG_lo_23 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_23))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_24 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==24); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_24 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_24) == 1'b1) begin + REG_lo_24 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_24) == 1'b0) begin + end else begin + REG_lo_24 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_24))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_25 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==25); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_25 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_25) == 1'b1) begin + REG_lo_25 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_25) == 1'b0) begin + end else begin + REG_lo_25 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_25))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_26 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==26); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_26 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_26) == 1'b1) begin + REG_lo_26 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_26) == 1'b0) begin + end else begin + REG_lo_26 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_26))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_27 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==27); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_27 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_27) == 1'b1) begin + REG_lo_27 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_27) == 1'b0) begin + end else begin + REG_lo_27 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_27))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_28 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==28); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_28 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_28) == 1'b1) begin + REG_lo_28 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_28) == 1'b0) begin + end else begin + REG_lo_28 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_94x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_28))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_29 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==29); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_29 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_29) == 1'b1) begin + REG_lo_29 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_29) == 1'b0) begin + end else begin + REG_lo_29 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_29))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_30 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==30); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_30 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_30) == 1'b1) begin + REG_lo_30 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_30) == 1'b0) begin + end else begin + REG_lo_30 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_30))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_31 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==31); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_31 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_31) == 1'b1) begin + REG_lo_31 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_31) == 1'b0) begin + end else begin + REG_lo_31 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_31))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_32 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==32); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_32 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_32) == 1'b1) begin + REG_lo_32 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_32) == 1'b0) begin + end else begin + REG_lo_32 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_32))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_33 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==33); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_33 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_33) == 1'b1) begin + REG_lo_33 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_33) == 1'b0) begin + end else begin + REG_lo_33 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_33))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_34 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==34); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_34 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_34) == 1'b1) begin + REG_lo_34 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_34) == 1'b0) begin + end else begin + REG_lo_34 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_100x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_34))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_35 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==35); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_35 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_35) == 1'b1) begin + REG_lo_35 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_35) == 1'b0) begin + end else begin + REG_lo_35 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_35))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_36 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==36); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_36 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_36) == 1'b1) begin + REG_lo_36 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_36) == 1'b0) begin + end else begin + REG_lo_36 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_102x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_36))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_37 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==37); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_37 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_37) == 1'b1) begin + REG_lo_37 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_37) == 1'b0) begin + end else begin + REG_lo_37 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_103x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_37))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_38 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==38); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_38 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_38) == 1'b1) begin + REG_lo_38 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_38) == 1'b0) begin + end else begin + REG_lo_38 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_104x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_38))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_39 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==39); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_39 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_39) == 1'b1) begin + REG_lo_39 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_39) == 1'b0) begin + end else begin + REG_lo_39 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_39))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_40 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==40); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_40 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_40) == 1'b1) begin + REG_lo_40 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_40) == 1'b0) begin + end else begin + REG_lo_40 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_106x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_40))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_41 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==41); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_41 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_41) == 1'b1) begin + REG_lo_41 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_41) == 1'b0) begin + end else begin + REG_lo_41 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_107x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_41))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_42 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==42); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_42 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_42) == 1'b1) begin + REG_lo_42 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_42) == 1'b0) begin + end else begin + REG_lo_42 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_108x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_42))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_43 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==43); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_43 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_43) == 1'b1) begin + REG_lo_43 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_43) == 1'b0) begin + end else begin + REG_lo_43 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_109x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_43))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_44 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==44); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_44 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_44) == 1'b1) begin + REG_lo_44 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_44) == 1'b0) begin + end else begin + REG_lo_44 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_44))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_45 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==45); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_45 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_45) == 1'b1) begin + REG_lo_45 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_45) == 1'b0) begin + end else begin + REG_lo_45 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_111x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_45))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_46 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==46); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_46 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_46) == 1'b1) begin + REG_lo_46 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_46) == 1'b0) begin + end else begin + REG_lo_46 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_112x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_46))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_47 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==47); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_47 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_47) == 1'b1) begin + REG_lo_47 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_47) == 1'b0) begin + end else begin + REG_lo_47 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_47))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_48 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==48); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_48 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_48) == 1'b1) begin + REG_lo_48 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_48) == 1'b0) begin + end else begin + REG_lo_48 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_114x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_48))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_49 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==49); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_49 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_49) == 1'b1) begin + REG_lo_49 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_49) == 1'b0) begin + end else begin + REG_lo_49 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_115x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_49))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_50 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==50); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_50 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_50) == 1'b1) begin + REG_lo_50 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_50) == 1'b0) begin + end else begin + REG_lo_50 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_50))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_51 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==51); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_51 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_51) == 1'b1) begin + REG_lo_51 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_51) == 1'b0) begin + end else begin + REG_lo_51 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_117x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_51))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_52 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==52); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_52 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_52) == 1'b1) begin + REG_lo_52 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_52) == 1'b0) begin + end else begin + REG_lo_52 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_118x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_52))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_53 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==53); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_53 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_53) == 1'b1) begin + REG_lo_53 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_53) == 1'b0) begin + end else begin + REG_lo_53 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_119x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_53))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_54 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==54); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_54 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_54) == 1'b1) begin + REG_lo_54 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_54) == 1'b0) begin + end else begin + REG_lo_54 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_120x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_54))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_55 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==55); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_55 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_55) == 1'b1) begin + REG_lo_55 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_55) == 1'b0) begin + end else begin + REG_lo_55 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_121x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_55))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_56 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==56); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_56 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_56) == 1'b1) begin + REG_lo_56 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_56) == 1'b0) begin + end else begin + REG_lo_56 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_122x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_56))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_57 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==57); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_57 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_57) == 1'b1) begin + REG_lo_57 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_57) == 1'b0) begin + end else begin + REG_lo_57 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_123x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_57))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_58 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==58); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_58 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_58) == 1'b1) begin + REG_lo_58 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_58) == 1'b0) begin + end else begin + REG_lo_58 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_124x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_58))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_59 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==59); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_59 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_59) == 1'b1) begin + REG_lo_59 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_59) == 1'b0) begin + end else begin + REG_lo_59 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_125x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_59))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_60 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==60); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_60 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_60) == 1'b1) begin + REG_lo_60 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_60) == 1'b0) begin + end else begin + REG_lo_60 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_126x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_60))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_61 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==61); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_61 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_61) == 1'b1) begin + REG_lo_61 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_61) == 1'b0) begin + end else begin + REG_lo_61 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_127x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_61))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_62 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==62); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_62 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_62) == 1'b1) begin + REG_lo_62 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_62) == 1'b0) begin + end else begin + REG_lo_62 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_128x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_62))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_63 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==63); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_63 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_63) == 1'b1) begin + REG_lo_63 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_63) == 1'b0) begin + end else begin + REG_lo_63 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_129x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_63))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_64 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==64); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_64 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_64) == 1'b1) begin + REG_lo_64 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_64) == 1'b0) begin + end else begin + REG_lo_64 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_130x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_64))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_65 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==65); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_65 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_65) == 1'b1) begin + REG_lo_65 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_65) == 1'b0) begin + end else begin + REG_lo_65 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_131x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_65))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_66 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==66); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_66 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_66) == 1'b1) begin + REG_lo_66 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_66) == 1'b0) begin + end else begin + REG_lo_66 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_132x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_66))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_67 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==67); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_67 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_67) == 1'b1) begin + REG_lo_67 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_67) == 1'b0) begin + end else begin + REG_lo_67 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_133x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_67))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_68 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==68); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_68 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_68) == 1'b1) begin + REG_lo_68 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_68) == 1'b0) begin + end else begin + REG_lo_68 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_134x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_68))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_69 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==69); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_69 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_69) == 1'b1) begin + REG_lo_69 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_69) == 1'b0) begin + end else begin + REG_lo_69 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_135x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_69))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_70 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==70); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_70 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_70) == 1'b1) begin + REG_lo_70 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_70) == 1'b0) begin + end else begin + REG_lo_70 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_136x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_70))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_71 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==71); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_71 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_71) == 1'b1) begin + REG_lo_71 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_71) == 1'b0) begin + end else begin + REG_lo_71 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_137x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_71))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_72 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==72); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_72 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_72) == 1'b1) begin + REG_lo_72 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_72) == 1'b0) begin + end else begin + REG_lo_72 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_138x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_72))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_73 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==73); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_73 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_73) == 1'b1) begin + REG_lo_73 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_73) == 1'b0) begin + end else begin + REG_lo_73 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_139x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_73))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_74 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==74); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_74 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_74) == 1'b1) begin + REG_lo_74 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_74) == 1'b0) begin + end else begin + REG_lo_74 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_140x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_74))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_75 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==75); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_75 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_75) == 1'b1) begin + REG_lo_75 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_75) == 1'b0) begin + end else begin + REG_lo_75 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_141x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_75))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_76 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==76); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_76 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_76) == 1'b1) begin + REG_lo_76 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_76) == 1'b0) begin + end else begin + REG_lo_76 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_142x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_76))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_77 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==77); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_77 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_77) == 1'b1) begin + REG_lo_77 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_77) == 1'b0) begin + end else begin + REG_lo_77 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_143x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_77))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_78 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==78); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_78 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_78) == 1'b1) begin + REG_lo_78 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_78) == 1'b0) begin + end else begin + REG_lo_78 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_144x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_78))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_79 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==79); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_79 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_79) == 1'b1) begin + REG_lo_79 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_79) == 1'b0) begin + end else begin + REG_lo_79 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_145x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_79))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_80 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==80); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_80 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_80) == 1'b1) begin + REG_lo_80 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_80) == 1'b0) begin + end else begin + REG_lo_80 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_146x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_80))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_81 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==81); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_81 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_81) == 1'b1) begin + REG_lo_81 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_81) == 1'b0) begin + end else begin + REG_lo_81 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_147x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_81))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_82 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==82); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_82 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_82) == 1'b1) begin + REG_lo_82 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_82) == 1'b0) begin + end else begin + REG_lo_82 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_148x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_82))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_83 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==83); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_83 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_83) == 1'b1) begin + REG_lo_83 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_83) == 1'b0) begin + end else begin + REG_lo_83 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_149x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_83))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_84 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==84); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_84 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_84) == 1'b1) begin + REG_lo_84 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_84) == 1'b0) begin + end else begin + REG_lo_84 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_150x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_84))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_85 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==85); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_85 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_85) == 1'b1) begin + REG_lo_85 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_85) == 1'b0) begin + end else begin + REG_lo_85 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_151x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_85))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_86 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==86); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_86 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_86) == 1'b1) begin + REG_lo_86 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_86) == 1'b0) begin + end else begin + REG_lo_86 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_152x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_86))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_87 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==87); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_87 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_87) == 1'b1) begin + REG_lo_87 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_87) == 1'b0) begin + end else begin + REG_lo_87 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_153x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_87))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_88 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==88); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_88 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_88) == 1'b1) begin + REG_lo_88 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_88) == 1'b0) begin + end else begin + REG_lo_88 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_154x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_88))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_89 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==89); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_89 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_89) == 1'b1) begin + REG_lo_89 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_89) == 1'b0) begin + end else begin + REG_lo_89 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_155x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_89))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_90 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==90); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_90 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_90) == 1'b1) begin + REG_lo_90 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_90) == 1'b0) begin + end else begin + REG_lo_90 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_156x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_90))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_91 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==91); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_91 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_91) == 1'b1) begin + REG_lo_91 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_91) == 1'b0) begin + end else begin + REG_lo_91 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_157x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_91))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_92 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==92); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_92 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_92) == 1'b1) begin + REG_lo_92 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_92) == 1'b0) begin + end else begin + REG_lo_92 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_158x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_92))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_93 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==93); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_93 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_93) == 1'b1) begin + REG_lo_93 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_93) == 1'b0) begin + end else begin + REG_lo_93 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_159x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_93))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_94 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==94); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_94 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_94) == 1'b1) begin + REG_lo_94 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_94) == 1'b0) begin + end else begin + REG_lo_94 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_160x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_94))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_95 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==95); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_95 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_95) == 1'b1) begin + REG_lo_95 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_95) == 1'b0) begin + end else begin + REG_lo_95 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_161x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_95))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_96 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==96); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_96 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_96) == 1'b1) begin + REG_lo_96 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_96) == 1'b0) begin + end else begin + REG_lo_96 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_162x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_96))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_97 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==97); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_97 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_97) == 1'b1) begin + REG_lo_97 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_97) == 1'b0) begin + end else begin + REG_lo_97 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_163x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_97))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_98 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==98); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_98 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_98) == 1'b1) begin + REG_lo_98 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_98) == 1'b0) begin + end else begin + REG_lo_98 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_164x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_98))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_99 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==99); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_99 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_99) == 1'b1) begin + REG_lo_99 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_99) == 1'b0) begin + end else begin + REG_lo_99 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_165x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_99))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_100 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==100); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_100 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_100) == 1'b1) begin + REG_lo_100 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_100) == 1'b0) begin + end else begin + REG_lo_100 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_166x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_100))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_101 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==101); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_101 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_101) == 1'b1) begin + REG_lo_101 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_101) == 1'b0) begin + end else begin + REG_lo_101 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_167x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_101))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_102 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==102); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_102 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_102) == 1'b1) begin + REG_lo_102 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_102) == 1'b0) begin + end else begin + REG_lo_102 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_168x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_102))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_103 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==103); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_103 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_103) == 1'b1) begin + REG_lo_103 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_103) == 1'b0) begin + end else begin + REG_lo_103 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_169x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_103))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_104 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==104); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_104 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_104) == 1'b1) begin + REG_lo_104 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_104) == 1'b0) begin + end else begin + REG_lo_104 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_170x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_104))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_105 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==105); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_105 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_105) == 1'b1) begin + REG_lo_105 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_105) == 1'b0) begin + end else begin + REG_lo_105 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_171x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_105))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_106 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==106); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_106 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_106) == 1'b1) begin + REG_lo_106 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_106) == 1'b0) begin + end else begin + REG_lo_106 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_172x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_106))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_107 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==107); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_107 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_107) == 1'b1) begin + REG_lo_107 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_107) == 1'b0) begin + end else begin + REG_lo_107 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_173x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_107))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_108 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==108); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_108 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_108) == 1'b1) begin + REG_lo_108 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_108) == 1'b0) begin + end else begin + REG_lo_108 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_174x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_108))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_109 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==109); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_109 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_109) == 1'b1) begin + REG_lo_109 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_109) == 1'b0) begin + end else begin + REG_lo_109 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_175x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_109))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_110 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==110); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_110 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_110) == 1'b1) begin + REG_lo_110 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_110) == 1'b0) begin + end else begin + REG_lo_110 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_176x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_110))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_111 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==111); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_111 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_111) == 1'b1) begin + REG_lo_111 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_111) == 1'b0) begin + end else begin + REG_lo_111 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_177x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_111))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_112 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==112); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_112 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_112) == 1'b1) begin + REG_lo_112 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_112) == 1'b0) begin + end else begin + REG_lo_112 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_178x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_112))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_113 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==113); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_113 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_113) == 1'b1) begin + REG_lo_113 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_113) == 1'b0) begin + end else begin + REG_lo_113 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_179x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_113))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_114 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==114); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_114 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_114) == 1'b1) begin + REG_lo_114 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_114) == 1'b0) begin + end else begin + REG_lo_114 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_180x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_114))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_115 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==115); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_115 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_115) == 1'b1) begin + REG_lo_115 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_115) == 1'b0) begin + end else begin + REG_lo_115 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_181x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_115))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_116 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==116); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_116 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_116) == 1'b1) begin + REG_lo_116 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_116) == 1'b0) begin + end else begin + REG_lo_116 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_182x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_116))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_117 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==117); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_117 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_117) == 1'b1) begin + REG_lo_117 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_117) == 1'b0) begin + end else begin + REG_lo_117 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_183x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_117))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_118 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==118); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_118 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_118) == 1'b1) begin + REG_lo_118 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_118) == 1'b0) begin + end else begin + REG_lo_118 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_184x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_118))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_119 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==119); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_119 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_119) == 1'b1) begin + REG_lo_119 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_119) == 1'b0) begin + end else begin + REG_lo_119 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_185x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_119))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_120 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==120); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_120 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_120) == 1'b1) begin + REG_lo_120 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_120) == 1'b0) begin + end else begin + REG_lo_120 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_186x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_120))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_121 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==121); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_121 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_121) == 1'b1) begin + REG_lo_121 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_121) == 1'b0) begin + end else begin + REG_lo_121 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_187x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_121))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_122 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==122); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_122 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_122) == 1'b1) begin + REG_lo_122 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_122) == 1'b0) begin + end else begin + REG_lo_122 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_188x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_122))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_123 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==123); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_123 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_123) == 1'b1) begin + REG_lo_123 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_123) == 1'b0) begin + end else begin + REG_lo_123 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_189x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_123))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_124 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==124); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_124 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_124) == 1'b1) begin + REG_lo_124 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_124) == 1'b0) begin + end else begin + REG_lo_124 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_190x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_124))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_125 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==125); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_125 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_125) == 1'b1) begin + REG_lo_125 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_125) == 1'b0) begin + end else begin + REG_lo_125 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_191x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_125))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_126 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==126); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_126 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_126) == 1'b1) begin + REG_lo_126 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_126) == 1'b0) begin + end else begin + REG_lo_126 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_192x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_126))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_127 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==127); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_127 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_127) == 1'b1) begin + REG_lo_127 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_127) == 1'b0) begin + end else begin + REG_lo_127 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_193x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_127))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_128 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==128); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_128 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_128) == 1'b1) begin + REG_lo_128 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_128) == 1'b0) begin + end else begin + REG_lo_128 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_194x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_128))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_129 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==129); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_129 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_129) == 1'b1) begin + REG_lo_129 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_129) == 1'b0) begin + end else begin + REG_lo_129 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_195x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_129))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_130 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==130); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_130 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_130) == 1'b1) begin + REG_lo_130 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_130) == 1'b0) begin + end else begin + REG_lo_130 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_196x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_130))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_131 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==131); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_131 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_131) == 1'b1) begin + REG_lo_131 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_131) == 1'b0) begin + end else begin + REG_lo_131 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_197x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_131))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_132 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==132); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_132 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_132) == 1'b1) begin + REG_lo_132 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_132) == 1'b0) begin + end else begin + REG_lo_132 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_198x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_132))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_133 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==133); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_133 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_133) == 1'b1) begin + REG_lo_133 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_133) == 1'b0) begin + end else begin + REG_lo_133 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_199x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_133))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_134 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==134); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_134 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_134) == 1'b1) begin + REG_lo_134 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_134) == 1'b0) begin + end else begin + REG_lo_134 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_200x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_134))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_135 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==135); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_135 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_135) == 1'b1) begin + REG_lo_135 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_135) == 1'b0) begin + end else begin + REG_lo_135 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_201x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_135))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_136 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==136); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_136 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_136) == 1'b1) begin + REG_lo_136 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_136) == 1'b0) begin + end else begin + REG_lo_136 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_202x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_136))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_137 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==137); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_137 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_137) == 1'b1) begin + REG_lo_137 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_137) == 1'b0) begin + end else begin + REG_lo_137 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_203x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_137))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_138 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==138); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_138 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_138) == 1'b1) begin + REG_lo_138 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_138) == 1'b0) begin + end else begin + REG_lo_138 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_204x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_138))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_139 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==139); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_139 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_139) == 1'b1) begin + REG_lo_139 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_139) == 1'b0) begin + end else begin + REG_lo_139 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_205x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_139))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_140 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==140); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_140 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_140) == 1'b1) begin + REG_lo_140 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_140) == 1'b0) begin + end else begin + REG_lo_140 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_206x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_140))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_141 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==141); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_141 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_141) == 1'b1) begin + REG_lo_141 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_141) == 1'b0) begin + end else begin + REG_lo_141 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_207x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_141))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_142 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==142); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_142 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_142) == 1'b1) begin + REG_lo_142 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_142) == 1'b0) begin + end else begin + REG_lo_142 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_208x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_142))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_143 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==143); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_143 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_143) == 1'b1) begin + REG_lo_143 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_143) == 1'b0) begin + end else begin + REG_lo_143 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_209x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_143))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_144 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==144); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_144 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_144) == 1'b1) begin + REG_lo_144 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_144) == 1'b0) begin + end else begin + REG_lo_144 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_210x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_144))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_145 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==145); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_145 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_145) == 1'b1) begin + REG_lo_145 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_145) == 1'b0) begin + end else begin + REG_lo_145 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_211x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_145))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_146 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==146); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_146 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_146) == 1'b1) begin + REG_lo_146 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_146) == 1'b0) begin + end else begin + REG_lo_146 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_212x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_146))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_147 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==147); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_147 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_147) == 1'b1) begin + REG_lo_147 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_147) == 1'b0) begin + end else begin + REG_lo_147 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_213x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_147))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_148 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==148); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_148 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_148) == 1'b1) begin + REG_lo_148 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_148) == 1'b0) begin + end else begin + REG_lo_148 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_214x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_148))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_149 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==149); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_149 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_149) == 1'b1) begin + REG_lo_149 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_149) == 1'b0) begin + end else begin + REG_lo_149 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_215x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_149))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_150 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==150); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_150 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_150) == 1'b1) begin + REG_lo_150 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_150) == 1'b0) begin + end else begin + REG_lo_150 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_216x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_150))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_151 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==151); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_151 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_151) == 1'b1) begin + REG_lo_151 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_151) == 1'b0) begin + end else begin + REG_lo_151 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_217x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_151))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_152 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==152); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_152 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_152) == 1'b1) begin + REG_lo_152 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_152) == 1'b0) begin + end else begin + REG_lo_152 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_218x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_152))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_153 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==153); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_153 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_153) == 1'b1) begin + REG_lo_153 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_153) == 1'b0) begin + end else begin + REG_lo_153 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_219x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_153))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_154 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==154); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_154 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_154) == 1'b1) begin + REG_lo_154 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_154) == 1'b0) begin + end else begin + REG_lo_154 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_220x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_154))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_155 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==155); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_155 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_155) == 1'b1) begin + REG_lo_155 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_155) == 1'b0) begin + end else begin + REG_lo_155 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_221x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_155))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_156 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==156); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_156 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_156) == 1'b1) begin + REG_lo_156 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_156) == 1'b0) begin + end else begin + REG_lo_156 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_222x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_156))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_157 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==157); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_157 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_157) == 1'b1) begin + REG_lo_157 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_157) == 1'b0) begin + end else begin + REG_lo_157 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_223x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_157))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_158 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==158); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_158 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_158) == 1'b1) begin + REG_lo_158 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_158) == 1'b0) begin + end else begin + REG_lo_158 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_224x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_158))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_159 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==159); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_159 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_159) == 1'b1) begin + REG_lo_159 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_159) == 1'b0) begin + end else begin + REG_lo_159 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_225x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_159))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_160 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==160); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_160 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_160) == 1'b1) begin + REG_lo_160 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_160) == 1'b0) begin + end else begin + REG_lo_160 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_226x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_160))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_161 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==161); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_161 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_161) == 1'b1) begin + REG_lo_161 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_161) == 1'b0) begin + end else begin + REG_lo_161 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_227x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_161))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_162 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==162); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_162 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_162) == 1'b1) begin + REG_lo_162 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_162) == 1'b0) begin + end else begin + REG_lo_162 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_228x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_162))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_163 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==163); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_163 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_163) == 1'b1) begin + REG_lo_163 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_163) == 1'b0) begin + end else begin + REG_lo_163 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_229x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_163))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_164 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==164); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_164 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_164) == 1'b1) begin + REG_lo_164 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_164) == 1'b0) begin + end else begin + REG_lo_164 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_230x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_164))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_165 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==165); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_165 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_165) == 1'b1) begin + REG_lo_165 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_165) == 1'b0) begin + end else begin + REG_lo_165 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_231x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_165))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_166 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==166); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_166 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_166) == 1'b1) begin + REG_lo_166 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_166) == 1'b0) begin + end else begin + REG_lo_166 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_232x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_166))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_167 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==167); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_167 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_167) == 1'b1) begin + REG_lo_167 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_167) == 1'b0) begin + end else begin + REG_lo_167 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_233x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_167))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_168 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==168); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_168 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_168) == 1'b1) begin + REG_lo_168 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_168) == 1'b0) begin + end else begin + REG_lo_168 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_234x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_168))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_169 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==169); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_169 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_169) == 1'b1) begin + REG_lo_169 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_169) == 1'b0) begin + end else begin + REG_lo_169 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_235x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_169))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_170 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==170); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_170 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_170) == 1'b1) begin + REG_lo_170 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_170) == 1'b0) begin + end else begin + REG_lo_170 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_236x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_170))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_171 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==171); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_171 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_171) == 1'b1) begin + REG_lo_171 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_171) == 1'b0) begin + end else begin + REG_lo_171 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_237x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_171))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_172 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==172); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_172 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_172) == 1'b1) begin + REG_lo_172 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_172) == 1'b0) begin + end else begin + REG_lo_172 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_238x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_172))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_173 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==173); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_173 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_173) == 1'b1) begin + REG_lo_173 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_173) == 1'b0) begin + end else begin + REG_lo_173 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_239x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_173))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_174 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==174); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_174 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_174) == 1'b1) begin + REG_lo_174 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_174) == 1'b0) begin + end else begin + REG_lo_174 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_240x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_174))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_175 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==175); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_175 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_175) == 1'b1) begin + REG_lo_175 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_175) == 1'b0) begin + end else begin + REG_lo_175 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_241x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_175))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_176 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==176); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_176 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_176) == 1'b1) begin + REG_lo_176 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_176) == 1'b0) begin + end else begin + REG_lo_176 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_242x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_176))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_177 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==177); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_177 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_177) == 1'b1) begin + REG_lo_177 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_177) == 1'b0) begin + end else begin + REG_lo_177 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_243x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_177))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_178 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==178); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_178 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_178) == 1'b1) begin + REG_lo_178 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_178) == 1'b0) begin + end else begin + REG_lo_178 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_244x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_178))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_179 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==179); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_179 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_179) == 1'b1) begin + REG_lo_179 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_179) == 1'b0) begin + end else begin + REG_lo_179 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_245x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_179))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_180 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==180); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_180 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_180) == 1'b1) begin + REG_lo_180 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_180) == 1'b0) begin + end else begin + REG_lo_180 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_246x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_180))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_181 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==181); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_181 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_181) == 1'b1) begin + REG_lo_181 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_181) == 1'b0) begin + end else begin + REG_lo_181 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_247x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_181))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_182 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==182); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_182 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_182) == 1'b1) begin + REG_lo_182 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_182) == 1'b0) begin + end else begin + REG_lo_182 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_248x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_182))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_183 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==183); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_183 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_183) == 1'b1) begin + REG_lo_183 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_183) == 1'b0) begin + end else begin + REG_lo_183 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_249x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_183))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_184 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==184); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_184 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_184) == 1'b1) begin + REG_lo_184 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_184) == 1'b0) begin + end else begin + REG_lo_184 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_250x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_184))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_185 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==185); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_185 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_185) == 1'b1) begin + REG_lo_185 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_185) == 1'b0) begin + end else begin + REG_lo_185 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_251x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_185))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_186 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==186); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_186 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_186) == 1'b1) begin + REG_lo_186 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_186) == 1'b0) begin + end else begin + REG_lo_186 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_252x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_186))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_187 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==187); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_187 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_187) == 1'b1) begin + REG_lo_187 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_187) == 1'b0) begin + end else begin + REG_lo_187 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_253x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_187))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_188 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==188); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_188 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_188) == 1'b1) begin + REG_lo_188 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_188) == 1'b0) begin + end else begin + REG_lo_188 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_254x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_188))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_189 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==189); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_189 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_189) == 1'b1) begin + REG_lo_189 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_189) == 1'b0) begin + end else begin + REG_lo_189 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_255x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_189))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_190 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==190); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_190 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_190) == 1'b1) begin + REG_lo_190 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_190) == 1'b0) begin + end else begin + REG_lo_190 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_256x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_190))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_191 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==191); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_191 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_191) == 1'b1) begin + REG_lo_191 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_191) == 1'b0) begin + end else begin + REG_lo_191 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_257x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_191))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_192 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==192); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_192 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_192) == 1'b1) begin + REG_lo_192 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_192) == 1'b0) begin + end else begin + REG_lo_192 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_258x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_192))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_193 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==193); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_193 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_193) == 1'b1) begin + REG_lo_193 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_193) == 1'b0) begin + end else begin + REG_lo_193 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_259x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_193))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_194 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==194); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_194 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_194) == 1'b1) begin + REG_lo_194 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_194) == 1'b0) begin + end else begin + REG_lo_194 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_260x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_194))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_195 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==195); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_195 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_195) == 1'b1) begin + REG_lo_195 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_195) == 1'b0) begin + end else begin + REG_lo_195 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_261x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_195))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_196 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==196); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_196 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_196) == 1'b1) begin + REG_lo_196 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_196) == 1'b0) begin + end else begin + REG_lo_196 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_262x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_196))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_197 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==197); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_197 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_197) == 1'b1) begin + REG_lo_197 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_197) == 1'b0) begin + end else begin + REG_lo_197 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_263x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_197))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_198 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==198); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_198 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_198) == 1'b1) begin + REG_lo_198 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_198) == 1'b0) begin + end else begin + REG_lo_198 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_264x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_198))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_199 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==199); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_199 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_199) == 1'b1) begin + REG_lo_199 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_199) == 1'b0) begin + end else begin + REG_lo_199 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_265x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_199))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_200 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==200); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_200 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_200) == 1'b1) begin + REG_lo_200 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_200) == 1'b0) begin + end else begin + REG_lo_200 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_266x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_200))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_201 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==201); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_201 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_201) == 1'b1) begin + REG_lo_201 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_201) == 1'b0) begin + end else begin + REG_lo_201 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_267x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_201))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_202 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==202); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_202 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_202) == 1'b1) begin + REG_lo_202 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_202) == 1'b0) begin + end else begin + REG_lo_202 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_268x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_202))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_203 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==203); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_203 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_203) == 1'b1) begin + REG_lo_203 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_203) == 1'b0) begin + end else begin + REG_lo_203 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_269x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_203))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_204 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==204); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_204 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_204) == 1'b1) begin + REG_lo_204 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_204) == 1'b0) begin + end else begin + REG_lo_204 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_270x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_204))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_205 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==205); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_205 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_205) == 1'b1) begin + REG_lo_205 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_205) == 1'b0) begin + end else begin + REG_lo_205 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_271x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_205))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_206 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==206); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_206 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_206) == 1'b1) begin + REG_lo_206 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_206) == 1'b0) begin + end else begin + REG_lo_206 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_272x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_206))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_207 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==207); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_207 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_207) == 1'b1) begin + REG_lo_207 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_207) == 1'b0) begin + end else begin + REG_lo_207 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_273x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_207))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_208 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==208); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_208 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_208) == 1'b1) begin + REG_lo_208 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_208) == 1'b0) begin + end else begin + REG_lo_208 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_274x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_208))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_209 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==209); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_209 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_209) == 1'b1) begin + REG_lo_209 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_209) == 1'b0) begin + end else begin + REG_lo_209 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_275x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_209))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_210 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==210); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_210 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_210) == 1'b1) begin + REG_lo_210 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_210) == 1'b0) begin + end else begin + REG_lo_210 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_276x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_210))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_211 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==211); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_211 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_211) == 1'b1) begin + REG_lo_211 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_211) == 1'b0) begin + end else begin + REG_lo_211 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_277x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_211))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_212 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==212); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_212 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_212) == 1'b1) begin + REG_lo_212 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_212) == 1'b0) begin + end else begin + REG_lo_212 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_278x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_212))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_213 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==213); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_213 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_213) == 1'b1) begin + REG_lo_213 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_213) == 1'b0) begin + end else begin + REG_lo_213 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_279x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_213))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_214 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==214); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_214 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_214) == 1'b1) begin + REG_lo_214 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_214) == 1'b0) begin + end else begin + REG_lo_214 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_280x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_214))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_215 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==215); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_215 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_215) == 1'b1) begin + REG_lo_215 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_215) == 1'b0) begin + end else begin + REG_lo_215 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_281x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_215))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_216 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==216); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_216 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_216) == 1'b1) begin + REG_lo_216 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_216) == 1'b0) begin + end else begin + REG_lo_216 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_282x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_216))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_217 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==217); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_217 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_217) == 1'b1) begin + REG_lo_217 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_217) == 1'b0) begin + end else begin + REG_lo_217 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_283x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_217))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_218 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==218); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_218 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_218) == 1'b1) begin + REG_lo_218 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_218) == 1'b0) begin + end else begin + REG_lo_218 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_284x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_218))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_219 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==219); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_219 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_219) == 1'b1) begin + REG_lo_219 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_219) == 1'b0) begin + end else begin + REG_lo_219 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_285x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_219))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_220 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==220); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_220 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_220) == 1'b1) begin + REG_lo_220 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_220) == 1'b0) begin + end else begin + REG_lo_220 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_286x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_220))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_221 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==221); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_221 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_221) == 1'b1) begin + REG_lo_221 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_221) == 1'b0) begin + end else begin + REG_lo_221 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_287x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_221))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_222 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==222); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_222 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_222) == 1'b1) begin + REG_lo_222 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_222) == 1'b0) begin + end else begin + REG_lo_222 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_288x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_222))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_223 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==223); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_223 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_223) == 1'b1) begin + REG_lo_223 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_223) == 1'b0) begin + end else begin + REG_lo_223 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_289x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_223))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_224 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==224); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_224 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_224) == 1'b1) begin + REG_lo_224 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_224) == 1'b0) begin + end else begin + REG_lo_224 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_290x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_224))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_225 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==225); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_225 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_225) == 1'b1) begin + REG_lo_225 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_225) == 1'b0) begin + end else begin + REG_lo_225 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_291x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_225))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_226 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==226); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_226 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_226) == 1'b1) begin + REG_lo_226 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_226) == 1'b0) begin + end else begin + REG_lo_226 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_292x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_226))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_227 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==227); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_227 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_227) == 1'b1) begin + REG_lo_227 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_227) == 1'b0) begin + end else begin + REG_lo_227 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_293x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_227))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_228 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==228); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_228 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_228) == 1'b1) begin + REG_lo_228 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_228) == 1'b0) begin + end else begin + REG_lo_228 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_294x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_228))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_229 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==229); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_229 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_229) == 1'b1) begin + REG_lo_229 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_229) == 1'b0) begin + end else begin + REG_lo_229 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_295x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_229))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_230 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==230); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_230 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_230) == 1'b1) begin + REG_lo_230 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_230) == 1'b0) begin + end else begin + REG_lo_230 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_296x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_230))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_231 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==231); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_231 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_231) == 1'b1) begin + REG_lo_231 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_231) == 1'b0) begin + end else begin + REG_lo_231 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_297x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_231))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_232 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==232); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_232 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_232) == 1'b1) begin + REG_lo_232 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_232) == 1'b0) begin + end else begin + REG_lo_232 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_298x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_232))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_233 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==233); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_233 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_233) == 1'b1) begin + REG_lo_233 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_233) == 1'b0) begin + end else begin + REG_lo_233 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_299x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_233))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_234 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==234); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_234 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_234) == 1'b1) begin + REG_lo_234 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_234) == 1'b0) begin + end else begin + REG_lo_234 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_300x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_234))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_235 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==235); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_235 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_235) == 1'b1) begin + REG_lo_235 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_235) == 1'b0) begin + end else begin + REG_lo_235 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_301x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_235))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_236 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==236); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_236 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_236) == 1'b1) begin + REG_lo_236 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_236) == 1'b0) begin + end else begin + REG_lo_236 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_302x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_236))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_237 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==237); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_237 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_237) == 1'b1) begin + REG_lo_237 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_237) == 1'b0) begin + end else begin + REG_lo_237 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_303x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_237))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_238 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==238); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_238 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_238) == 1'b1) begin + REG_lo_238 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_238) == 1'b0) begin + end else begin + REG_lo_238 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_304x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_238))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_239 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==239); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_239 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_239) == 1'b1) begin + REG_lo_239 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_239) == 1'b0) begin + end else begin + REG_lo_239 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_305x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_239))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_240 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==240); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_240 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_240) == 1'b1) begin + REG_lo_240 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_240) == 1'b0) begin + end else begin + REG_lo_240 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_306x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_240))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_241 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==241); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_241 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_241) == 1'b1) begin + REG_lo_241 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_241) == 1'b0) begin + end else begin + REG_lo_241 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_307x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_241))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_242 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==242); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_242 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_242) == 1'b1) begin + REG_lo_242 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_242) == 1'b0) begin + end else begin + REG_lo_242 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_308x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_242))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_243 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==243); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_243 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_243) == 1'b1) begin + REG_lo_243 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_243) == 1'b0) begin + end else begin + REG_lo_243 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_309x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_243))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_244 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==244); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_244 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_244) == 1'b1) begin + REG_lo_244 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_244) == 1'b0) begin + end else begin + REG_lo_244 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_310x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_244))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_245 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==245); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_245 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_245) == 1'b1) begin + REG_lo_245 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_245) == 1'b0) begin + end else begin + REG_lo_245 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_311x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_245))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_246 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==246); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_246 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_246) == 1'b1) begin + REG_lo_246 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_246) == 1'b0) begin + end else begin + REG_lo_246 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_312x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_246))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_247 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==247); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_247 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_247) == 1'b1) begin + REG_lo_247 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_247) == 1'b0) begin + end else begin + REG_lo_247 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_313x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_247))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_248 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==248); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_248 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_248) == 1'b1) begin + REG_lo_248 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_248) == 1'b0) begin + end else begin + REG_lo_248 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_314x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_248))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_249 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==249); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_249 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_249) == 1'b1) begin + REG_lo_249 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_249) == 1'b0) begin + end else begin + REG_lo_249 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_315x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_249))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_250 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==250); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_250 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_250) == 1'b1) begin + REG_lo_250 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_250) == 1'b0) begin + end else begin + REG_lo_250 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_316x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_250))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_251 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==251); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_251 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_251) == 1'b1) begin + REG_lo_251 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_251) == 1'b0) begin + end else begin + REG_lo_251 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_317x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_251))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_252 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==252); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_252 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_252) == 1'b1) begin + REG_lo_252 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_252) == 1'b0) begin + end else begin + REG_lo_252 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_318x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_252))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_253 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==253); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_253 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_253) == 1'b1) begin + REG_lo_253 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_253) == 1'b0) begin + end else begin + REG_lo_253 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_319x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_253))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_254 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==254); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_254 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_254) == 1'b1) begin + REG_lo_254 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_254) == 1'b0) begin + end else begin + REG_lo_254 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_320x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_254))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_255 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==255); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_255 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_255) == 1'b1) begin + REG_lo_255 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_255) == 1'b0) begin + end else begin + REG_lo_255 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_321x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_255))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_256 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==256); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_256 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_256) == 1'b1) begin + REG_lo_256 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_256) == 1'b0) begin + end else begin + REG_lo_256 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_322x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_256))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//viva_pipe -bc lut_in_pd(lut_in_pvld, lut_in_prdy) <= idx2lut_pd(idx2lut_pvld,idx2lut_prdy); +NV_NVDLA_SDP_CORE_Y_lut_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.idx2lut_pvld (idx2lut_pvld) + ,.idx2lut_prdy (idx2lut_prdy) + ,.idx2lut_pd (idx2lut_pd[81*0 -1:0]) + ,.lut_in_pvld (lut_in_pvld) + ,.lut_in_prdy (lut_in_prdy) + ,.lut_in_pd (lut_in_pd[81*0 -1:0]) + ); +// PKT_UNPACK_WIRE( sdp_y_lut_in , lut_in_ , lut_in_pd ) +//: my $k=0; +//: my $bx =0*35; +//: my $bof=0*(35+32); +//: my $buf=0*(35+32+1); +//: my $bsl=0*(35+32+2); +//: my $ba =0*(35+32+3); +//: my $beh=0*(35+32+12); +//: my $boh=0*(35+32+13); +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_fraction${i}[34:0] = lut_in_pd[35*${i}+34:35*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_x${i}[31:0] = lut_in_pd[32*${i}+31+${bx}:32*${i}+${bx}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_oflow${i} = lut_in_pd[${i}+${bof}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_uflow${i} = lut_in_pd[${i}+${buf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_sel${i} = lut_in_pd[${i}+${bsl}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_addr${i}[8:0] = lut_in_pd[9*${i}+8+${ba}:9*${i}+${ba}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_le_hit${i} = lut_in_pd[${i}+${beh}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_lo_hit${i} = lut_in_pd[${i}+${boh}]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//======================================= +// PERF STATISTIC +// OFLOW +//: my $k=0; +//: print "assign lut_oflow_sum[4:0] = lut_in_oflow0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_oflow${i}"; +//: } +//: } +//: print ";\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign lut_oflow_sum[4:0] = lut_in_oflow0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign perf_lut_oflow_add = (&lut_oflow_cnt) ? 0 : lut_oflow_sum; +assign perf_lut_oflow_sub = 1'b0; +assign dp2reg_lut_oflow = lut_oflow_cnt; +always @( + perf_lut_oflow_add + or perf_lut_oflow_sub + ) begin + perf_lut_oflow_adv = perf_lut_oflow_add[4:0] != {{4{1'b0}}, perf_lut_oflow_sub[0:0]}; +end +always @( + perf_lut_oflow_cnt_cur + or perf_lut_oflow_add + or perf_lut_oflow_sub + or perf_lut_oflow_adv + or op_en_load + ) begin + perf_lut_oflow_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_oflow_cnt_cur}; + perf_lut_oflow_cnt_mod[33:0] = perf_lut_oflow_cnt_cur + perf_lut_oflow_add[4:0] - perf_lut_oflow_sub[0:0]; // spyglass disable W164b + perf_lut_oflow_cnt_new[33:0] = (perf_lut_oflow_adv)? perf_lut_oflow_cnt_mod[33:0] : perf_lut_oflow_cnt_ext[33:0]; + perf_lut_oflow_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_oflow_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_oflow_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_oflow_cnt_cur[31:0] <= perf_lut_oflow_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_oflow_cnt_cur + ) begin + lut_oflow_cnt[31:0] = perf_lut_oflow_cnt_cur[31:0]; +end +// UFLOW +//: my $k=0; +//: print "assign lut_uflow_sum[4:0] = lut_in_uflow0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_uflow${i}"; +//: } +//: } +//: print ";\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign lut_uflow_sum[4:0] = lut_in_uflow0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign perf_lut_uflow_add = (&lut_uflow_cnt) ? 0 : lut_uflow_sum; +assign perf_lut_uflow_sub = 1'b0; +assign dp2reg_lut_uflow = lut_uflow_cnt; +always @( + perf_lut_uflow_add + or perf_lut_uflow_sub + ) begin + perf_lut_uflow_adv = perf_lut_uflow_add[4:0] != {{4{1'b0}}, perf_lut_uflow_sub[0:0]}; +end +always @( + perf_lut_uflow_cnt_cur + or perf_lut_uflow_add + or perf_lut_uflow_sub + or perf_lut_uflow_adv + or op_en_load + ) begin + perf_lut_uflow_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_uflow_cnt_cur}; + perf_lut_uflow_cnt_mod[33:0] = perf_lut_uflow_cnt_cur + perf_lut_uflow_add[4:0] - perf_lut_uflow_sub[0:0]; // spyglass disable W164b + perf_lut_uflow_cnt_new[33:0] = (perf_lut_uflow_adv)? perf_lut_uflow_cnt_mod[33:0] : perf_lut_uflow_cnt_ext[33:0]; + perf_lut_uflow_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_uflow_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_uflow_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_uflow_cnt_cur[31:0] <= perf_lut_uflow_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_uflow_cnt_cur + ) begin + lut_uflow_cnt[31:0] = perf_lut_uflow_cnt_cur[31:0]; +end +// HYBRID +//: my $k=0; +//: foreach my $i (1..${k}-1) { +//: print "assign lut_in_hybrid${i} = !(lut_in_oflow${i} | lut_in_uflow${i}); \n"; +//: } +//: print "\n"; +//: print "assign lut_hybrid_sum[4:0] = lut_in_hybrid0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_hybrid${i}"; +//: } +//: } +//: print ";\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign lut_hybrid_sum[4:0] = lut_in_hybrid0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign perf_lut_hybrid_add = (&lut_hybrid_cnt) ? 0 : lut_hybrid_sum; +assign perf_lut_hybrid_sub = 1'b0; +assign dp2reg_lut_hybrid = lut_hybrid_cnt; +always @( + perf_lut_hybrid_add + or perf_lut_hybrid_sub + ) begin + perf_lut_hybrid_adv = perf_lut_hybrid_add[4:0] != {{4{1'b0}}, perf_lut_hybrid_sub[0:0]}; +end +always @( + perf_lut_hybrid_cnt_cur + or perf_lut_hybrid_add + or perf_lut_hybrid_sub + or perf_lut_hybrid_adv + or op_en_load + ) begin + perf_lut_hybrid_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_hybrid_cnt_cur}; + perf_lut_hybrid_cnt_mod[33:0] = perf_lut_hybrid_cnt_cur + perf_lut_hybrid_add[4:0] - perf_lut_hybrid_sub[0:0]; // spyglass disable W164b + perf_lut_hybrid_cnt_new[33:0] = (perf_lut_hybrid_adv)? perf_lut_hybrid_cnt_mod[33:0] : perf_lut_hybrid_cnt_ext[33:0]; + perf_lut_hybrid_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_hybrid_cnt_new[33:0]; +end +// perf_lut_hybrid flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_hybrid_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_hybrid_cnt_cur[31:0] <= perf_lut_hybrid_cnt_nxt[31:0]; + end + end +end +// perf_lut_hybrid output logic +always @( + perf_lut_hybrid_cnt_cur + ) begin + lut_hybrid_cnt[31:0] = perf_lut_hybrid_cnt_cur[31:0]; +end +// LE_HIT +//: my $k=0; +//: print "assign lut_le_hit_sum[4:0] = lut_in_le_hit0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_le_hit${i}"; +//: } +//: } +//: print ";\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign lut_le_hit_sum[4:0] = lut_in_le_hit0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign perf_lut_le_hit_add = (&lut_le_hit_cnt) ? 0 : lut_le_hit_sum; +assign perf_lut_le_hit_sub = 1'b0; +assign dp2reg_lut_le_hit = lut_le_hit_cnt; +always @( + perf_lut_le_hit_add + or perf_lut_le_hit_sub + ) begin + perf_lut_le_hit_adv = perf_lut_le_hit_add[4:0] != {{4{1'b0}}, perf_lut_le_hit_sub[0:0]}; +end +// perf_lut_le_hit cnt logic +always @( + perf_lut_le_hit_cnt_cur + or perf_lut_le_hit_add + or perf_lut_le_hit_sub + or perf_lut_le_hit_adv + or op_en_load + ) begin +// VCS sop_coverage_off start + perf_lut_le_hit_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_le_hit_cnt_cur}; + perf_lut_le_hit_cnt_mod[33:0] = perf_lut_le_hit_cnt_cur + perf_lut_le_hit_add[4:0] - perf_lut_le_hit_sub[0:0]; + perf_lut_le_hit_cnt_new[33:0] = (perf_lut_le_hit_adv)? perf_lut_le_hit_cnt_mod[33:0] : perf_lut_le_hit_cnt_ext[33:0]; + perf_lut_le_hit_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_le_hit_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_le_hit_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_le_hit_cnt_cur[31:0] <= perf_lut_le_hit_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_le_hit_cnt_cur + ) begin + lut_le_hit_cnt[31:0] = perf_lut_le_hit_cnt_cur[31:0]; +end +// LO_HIT +//: my $k=0; +//: print "assign lut_lo_hit_sum[4:0] = lut_in_lo_hit0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_lo_hit${i}"; +//: } +//: } +//: print ";\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign lut_lo_hit_sum[4:0] = lut_in_lo_hit0; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign perf_lut_lo_hit_add = (&lut_lo_hit_cnt) ? 0 : lut_lo_hit_sum; +assign perf_lut_lo_hit_sub = 1'b0; +assign dp2reg_lut_lo_hit = lut_lo_hit_cnt; +always @( + perf_lut_lo_hit_add + or perf_lut_lo_hit_sub + ) begin + perf_lut_lo_hit_adv = perf_lut_lo_hit_add[4:0] != {{4{1'b0}}, perf_lut_lo_hit_sub[0:0]}; +end +always @( + perf_lut_lo_hit_cnt_cur + or perf_lut_lo_hit_add + or perf_lut_lo_hit_sub + or perf_lut_lo_hit_adv + or op_en_load + ) begin + perf_lut_lo_hit_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_lo_hit_cnt_cur}; + perf_lut_lo_hit_cnt_mod[33:0] = perf_lut_lo_hit_cnt_cur + perf_lut_lo_hit_add[4:0] - perf_lut_lo_hit_sub[0:0]; // spyglass disable W164b + perf_lut_lo_hit_cnt_new[33:0] = (perf_lut_lo_hit_adv)? perf_lut_lo_hit_cnt_mod[33:0] : perf_lut_lo_hit_cnt_ext[33:0]; + perf_lut_lo_hit_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_lo_hit_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_lo_hit_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_lo_hit_cnt_cur[31:0] <= perf_lut_lo_hit_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_lo_hit_cnt_cur + ) begin + lut_lo_hit_cnt[31:0] = perf_lut_lo_hit_cnt_cur[31:0]; +end +//======================================= +// rd addr mux +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign lut_in_addr${i}_0 = lut_in_addr${i}; +//: assign lut_in_addr${i}_1 = lut_in_addr${i} + 1; +//: ); +//: } +//: +//: my $lut_depth = 257; +//: foreach my $lut (qw(le lo)) { +//: foreach my $x (0..1) { +//: foreach my $i (0.. ${k}-1) { +//: print qq( +//: always @ ( * ) begin +//: case (lut_in_addr${i}_${x}) +//: ); +//: foreach my $idx ($x .. ${lut_depth}-1) { +//: print" $idx: ${lut}_data${x}_${i} = REG_${lut}_$idx; \n"; +//: } +//: print qq( +//: default: ${lut}_data${x}_${i}= {16{`x_or_0}}; +//: endcase +//: end +//: ); +//: } +//: } +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign dat_in_y0_$i = (lut_in_sel${i}==1'b0) ? le_data0_$i : lo_data0_$i; +//: assign dat_in_y1_$i = (lut_in_sel${i}==1'b0) ? le_data1_$i : lo_data1_$i; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//======================================= +// dat fifo wr +assign rd_lut_en = lut_in_pvld & lut_in_prdy; +assign dat_fifo_wr_pvld = rd_lut_en; +// PKT_PACK_WIRE( sdp_y_lut_dat , dat_in_ , dat_fifo_wr_pd ) +//: my $k=0; +//: my $b=0*16; +//: foreach my $i (0..${k}-1) { +//: print "assign dat_fifo_wr_pd[16*${i}+15:16*${i}] = dat_in_y0_${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign dat_fifo_wr_pd[16*${i}+${b}+15:16*${i}+${b}] = dat_in_y1_${i}[15:0]; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print "assign out_y0_${i}[15:0] = dat_fifo_rd_pd[16*${i}+15:16*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_y1_${i}[15:0] = dat_fifo_rd_pd[16*${i}+${b}+15:16*${i}+${b}]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_SDP_CORE_Y_LUT_dat u_dat ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dat_fifo_wr_pvld (dat_fifo_wr_pvld) //|< w + ,.dat_fifo_wr_pd (dat_fifo_wr_pd[32*0 -1:0]) //|< w + ,.dat_fifo_rd_prdy (dat_fifo_rd_prdy) //|< w + ,.dat_fifo_rd_pvld (dat_fifo_rd_pvld) //|> w + ,.dat_fifo_rd_pd (dat_fifo_rd_pd[32*0 -1:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +// dat fifo rd +assign dat_fifo_rd_prdy = lut_out_prdy; +//============ +// cmd fifo wr: +// PKT_PACK_WIRE( sdp_y_lut_cmd , lut_in_ , cmd_fifo_wr_pd ) +//: my $k=0; +//: my $bx =0*35; +//: my $bof=0*(35+32); +//: my $buf=0*(35+32+1); +//: my $bsl=0*(35+32+2); +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[35*${i}+34:35*${i}] = lut_in_fraction${i}[34:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[32*${i}+31+${bx}:32*${i}+${bx}] = lut_in_x${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[${i}+${bof}] = lut_in_oflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[${i}+${buf}] = lut_in_uflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[${i}+${bsl}] = lut_in_sel${i} ; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print "assign out_fraction${i}[34:0] = cmd_fifo_rd_pd[35*${i}+34:35*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_x${i}[31:0] = cmd_fifo_rd_pd[32*${i}+31+${bx}:32*${i}+${bx}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_oflow${i} = cmd_fifo_rd_pd[${i}+${bof}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_uflow${i} = cmd_fifo_rd_pd[${i}+${buf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_sel${i} = cmd_fifo_rd_pd[${i}+${bsl}]; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cmd_fifo_wr_pvld = lut_in_pvld; +assign lut_in_prdy = cmd_fifo_wr_prdy; +// cmd fifo inst: +NV_NVDLA_SDP_CORE_Y_LUT_cmd u_cmd ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_fifo_wr_prdy (cmd_fifo_wr_prdy) //|> w + ,.cmd_fifo_wr_pvld (cmd_fifo_wr_pvld) //|< w + ,.cmd_fifo_wr_pd (cmd_fifo_wr_pd[70*0 -1:0]) //|< w + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) //|< w + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) //|> w + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[70*0 -1:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +// cmd fifo rd: +assign cmd_fifo_rd_prdy = lut_out_prdy & dat_fifo_rd_pvld; +//======================================= +// output mux when oflow/uflow +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print "assign out_flow${i} = out_uflow${i} | out_oflow${i}; \n"; +//: } +//: +//: foreach my $i (0.. ${k}-1) { +//: print qq( +//: always @( +//: out_uflow$i +//: or out_sel$i +//: or reg2dp_lut_le_slope_uflow_scale +//: or reg2dp_lut_le_slope_uflow_shift +//: or reg2dp_lut_le_start +//: or reg2dp_lut_le_function +//: or reg2dp_proc_precision +//: or reg2dp_lut_le_index_offset +//: or reg2dp_lut_lo_slope_uflow_scale +//: or reg2dp_lut_lo_slope_uflow_shift +//: or reg2dp_lut_lo_start +//: or out_oflow$i +//: or reg2dp_lut_le_slope_oflow_scale +//: or reg2dp_lut_le_slope_oflow_shift +//: or reg2dp_lut_le_end +//: or reg2dp_lut_lo_slope_oflow_scale +//: or reg2dp_lut_lo_slope_oflow_shift +//: or reg2dp_lut_lo_end +//: ) begin +//: if (out_uflow${i}) begin +//: if (out_sel${i}==1'b0) begin +//: out_scale${i} = reg2dp_lut_le_slope_uflow_scale; +//: out_shift${i} = reg2dp_lut_le_slope_uflow_shift; +//: out_offset${i} = reg2dp_lut_le_start; +//: if (reg2dp_lut_le_function==1'b0) begin +//: out_bias${i} = reg2dp_lut_le_index_offset[8 -1] ? 0 : (1 << reg2dp_lut_le_index_offset); +//: end else begin +//: out_bias${i} = 0; +//: end +//: end else begin +//: out_scale${i} = reg2dp_lut_lo_slope_uflow_scale; +//: out_shift${i} = reg2dp_lut_lo_slope_uflow_shift; +//: out_offset${i} = reg2dp_lut_lo_start; +//: out_bias${i} = 0; +//: end +//: end else if (out_oflow${i}) begin +//: if (out_sel${i}==1'b0) begin +//: out_scale${i} = reg2dp_lut_le_slope_oflow_scale; +//: out_shift${i} = reg2dp_lut_le_slope_oflow_shift; +//: out_offset${i} = reg2dp_lut_le_end; +//: out_bias${i} = 0; +//: end else begin +//: out_scale${i} = reg2dp_lut_lo_slope_oflow_scale; +//: out_shift${i} = reg2dp_lut_lo_slope_oflow_shift; +//: out_offset${i} = reg2dp_lut_lo_end; +//: out_bias${i} = 0; +//: end +//: end else begin +//: out_scale${i} = 0; +//: out_shift${i} = 0; +//: out_offset${i} = 0; +//: out_bias${i} = 0; +//: end +//: end +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//======================================= +// output pipe +assign lut_out_pvld = dat_fifo_rd_pvld; +// PKT_PACK_WIRE( sdp_y_lut_out , out_ , lut_out_pd ) +//: my $k=0; +//: my $bf =0*32; +//: my $by0=0*(32+35); +//: my $by1=0*(32+35+16); +//: my $bsc=0*(32+35+32); +//: my $bsf=0*(32+35+48); +//: my $bof=0*(32+35+48+5); +//: my $bbs=0*(32+35+85); +//: my $bfw=0*(32+35+85+32); +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[32*${i}+31:32*${i}] = out_x${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[35*${i}+${bf}+34:35*${i}+${bf}] = out_fraction${i}[34:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[16*${i}+${by0}+15:16*${i}+${by0}] = out_y0_${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[16*${i}+${by1}+15:16*${i}+${by1}] = out_y1_${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[16*${i}+${bsc}+15:16*${i}+${bsc}] = out_scale${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[5*${i}+${bsf}+4:5*${i}+${bsf}] = out_shift${i}[4:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[32*${i}+${bof}+31:32*${i}+${bof}] = out_offset${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[32*${i}+${bbs}+31:32*${i}+${bbs}] = out_bias${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[${i}+${bfw}] = out_flow${i}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +NV_NVDLA_SDP_CORE_Y_lut_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.lut_out_pvld (lut_out_pvld) + ,.lut_out_prdy (lut_out_prdy) + ,.lut_out_pd (lut_out_pd[185*0 -1:0]) + ,.lut2inp_pvld (lut2inp_pvld) + ,.lut2inp_prdy (lut2inp_prdy) + ,.lut2inp_pd (lut2inp_pd[185*0 -1:0]) + ); +//======================================= +// Assertions +assign mon_cmd_fifo_rd_pvld = cmd_fifo_rd_pvld; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when data is ready, cmd should be ready, which is faster") zzz_assert_never_327x (nvdla_core_clk, `ASSERT_RESET, dat_fifo_rd_pvld & !mon_cmd_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// Assertion for LUT Programing +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"exceed the size of LE LUT") zzz_assert_never_328x (nvdla_core_clk, `ASSERT_RESET, (lut_table_id== 1'h0 ) && lut_addr> 65); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"exceed the size of LE LUT") zzz_assert_never_329x (nvdla_core_clk, `ASSERT_RESET, (lut_table_id== 1'h1 ) && lut_addr> 257); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_SDP_CORE_Y_lut +module NV_NVDLA_SDP_CORE_Y_lut_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx2lut_pvld + ,idx2lut_prdy + ,idx2lut_pd + ,lut_in_pvld + ,lut_in_prdy + ,lut_in_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx2lut_pvld; +output idx2lut_prdy; +input [81*0 -1:0] idx2lut_pd; +output lut_in_pvld; +input lut_in_prdy; +output [81*0 -1:0] lut_in_pd; +//: my $dw = 81*0; +//: &eperl::pipe("-is -wid $dw -do lut_in_pd -vo lut_in_pvld -ri lut_in_prdy -di idx2lut_pd -vi idx2lut_pvld -ro idx2lut_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg idx2lut_prdy; +reg skid_flop_idx2lut_prdy; +reg skid_flop_idx2lut_pvld; +reg skid_flop_idx2lut_pd; +reg pipe_skid_idx2lut_pvld; +reg pipe_skid_idx2lut_pd; +// Wire +wire skid_idx2lut_pvld; +wire skid_idx2lut_pd; +wire skid_idx2lut_prdy; +wire pipe_skid_idx2lut_prdy; +wire lut_in_pvld; +wire lut_in_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + idx2lut_prdy <= 1'b1; + skid_flop_idx2lut_prdy <= 1'b1; + end else begin + idx2lut_prdy <= skid_idx2lut_prdy; + skid_flop_idx2lut_prdy <= skid_idx2lut_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_idx2lut_pvld <= 1'b0; + end else begin + if (skid_flop_idx2lut_prdy) begin + skid_flop_idx2lut_pvld <= idx2lut_pvld; + end + end +end +assign skid_idx2lut_pvld = (skid_flop_idx2lut_prdy) ? idx2lut_pvld : skid_flop_idx2lut_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_idx2lut_prdy & idx2lut_pvld) begin + skid_flop_idx2lut_pd <= idx2lut_pd; + end +end +assign skid_idx2lut_pd = (skid_flop_idx2lut_prdy) ? idx2lut_pd : skid_flop_idx2lut_pd; + + +// PIPE READY +assign skid_idx2lut_prdy = pipe_skid_idx2lut_prdy || !pipe_skid_idx2lut_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_idx2lut_pvld <= 1'b0; + end else begin + if (skid_idx2lut_prdy) begin + pipe_skid_idx2lut_pvld <= skid_idx2lut_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_idx2lut_prdy && skid_idx2lut_pvld) begin + pipe_skid_idx2lut_pd <= skid_idx2lut_pd; + end +end + + +// PIPE OUTPUT +assign pipe_skid_idx2lut_prdy = lut_in_prdy; +assign lut_in_pvld = pipe_skid_idx2lut_pvld; +assign lut_in_pd = pipe_skid_idx2lut_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule +module NV_NVDLA_SDP_CORE_Y_lut_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_out_pvld + ,lut_out_prdy + ,lut_out_pd + ,lut2inp_pvld + ,lut2inp_prdy + ,lut2inp_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input lut_out_pvld; +output lut_out_prdy; +input [185*0 -1:0] lut_out_pd; +output lut2inp_pvld; +input lut2inp_prdy; +output [185*0 -1:0] lut2inp_pd; +//: my $dw = 185*0; +//: &eperl::pipe("-is -wid $dw -do lut2inp_pd -vo lut2inp_pvld -ri lut2inp_prdy -di lut_out_pd -vi lut_out_pvld -ro lut_out_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg lut_out_prdy; +reg skid_flop_lut_out_prdy; +reg skid_flop_lut_out_pvld; +reg skid_flop_lut_out_pd; +reg pipe_skid_lut_out_pvld; +reg pipe_skid_lut_out_pd; +// Wire +wire skid_lut_out_pvld; +wire skid_lut_out_pd; +wire skid_lut_out_prdy; +wire pipe_skid_lut_out_prdy; +wire lut2inp_pvld; +wire lut2inp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_out_prdy <= 1'b1; + skid_flop_lut_out_prdy <= 1'b1; + end else begin + lut_out_prdy <= skid_lut_out_prdy; + skid_flop_lut_out_prdy <= skid_lut_out_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_lut_out_pvld <= 1'b0; + end else begin + if (skid_flop_lut_out_prdy) begin + skid_flop_lut_out_pvld <= lut_out_pvld; + end + end +end +assign skid_lut_out_pvld = (skid_flop_lut_out_prdy) ? lut_out_pvld : skid_flop_lut_out_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_lut_out_prdy & lut_out_pvld) begin + skid_flop_lut_out_pd <= lut_out_pd; + end +end +assign skid_lut_out_pd = (skid_flop_lut_out_prdy) ? lut_out_pd : skid_flop_lut_out_pd; + + +// PIPE READY +assign skid_lut_out_prdy = pipe_skid_lut_out_prdy || !pipe_skid_lut_out_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_lut_out_pvld <= 1'b0; + end else begin + if (skid_lut_out_prdy) begin + pipe_skid_lut_out_pvld <= skid_lut_out_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_lut_out_prdy && skid_lut_out_pvld) begin + pipe_skid_lut_out_pd <= skid_lut_out_pd; + end +end + + +// PIPE OUTPUT +assign pipe_skid_lut_out_prdy = lut2inp_prdy; +assign lut2inp_pvld = pipe_skid_lut_out_pvld; +assign lut2inp_pd = pipe_skid_lut_out_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v.vcp new file mode 100644 index 0000000..12acf9f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v.vcp @@ -0,0 +1,21791 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_Y_lut.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_CORE_Y_lut ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,idx2lut_pd //|< i + ,idx2lut_pvld //|< i + ,lut2inp_prdy //|< i + ,op_en_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_lut_int_access_type //|< i + ,reg2dp_lut_int_addr //|< i + ,reg2dp_lut_int_data //|< i + ,reg2dp_lut_int_data_wr //|< i + ,reg2dp_lut_int_table_id //|< i + ,reg2dp_lut_le_end //|< i + ,reg2dp_lut_le_function //|< i + ,reg2dp_lut_le_index_offset //|< i + ,reg2dp_lut_le_slope_oflow_scale //|< i + ,reg2dp_lut_le_slope_oflow_shift //|< i + ,reg2dp_lut_le_slope_uflow_scale //|< i + ,reg2dp_lut_le_slope_uflow_shift //|< i + ,reg2dp_lut_le_start //|< i + ,reg2dp_lut_lo_end //|< i + ,reg2dp_lut_lo_slope_oflow_scale //|< i + ,reg2dp_lut_lo_slope_oflow_shift //|< i + ,reg2dp_lut_lo_slope_uflow_scale //|< i + ,reg2dp_lut_lo_slope_uflow_shift //|< i + ,reg2dp_lut_lo_start //|< i + ,reg2dp_perf_lut_en //|< i + ,reg2dp_proc_precision //|< i + ,dp2reg_lut_hybrid //|> o + ,dp2reg_lut_int_data //|> o + ,dp2reg_lut_le_hit //|> o + ,dp2reg_lut_lo_hit //|> o + ,dp2reg_lut_oflow //|> o + ,dp2reg_lut_uflow //|> o + ,idx2lut_prdy //|> o + ,lut2inp_pd //|> o + ,lut2inp_pvld //|> o + ); +// +// NV_NVDLA_SDP_CORE_Y_lut_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output lut2inp_pvld; /* data valid */ +input lut2inp_prdy; /* data return handshake */ +output [185*0 -1:0] lut2inp_pd; +input idx2lut_pvld; /* data valid */ +output idx2lut_prdy; /* data return handshake */ +input [81*0 -1:0] idx2lut_pd; +input reg2dp_lut_int_access_type; +input [9:0] reg2dp_lut_int_addr; +input [15:0] reg2dp_lut_int_data; +input reg2dp_lut_int_data_wr; +input reg2dp_lut_int_table_id; +input [31:0] reg2dp_lut_le_end; +input reg2dp_lut_le_function; +input [7:0] reg2dp_lut_le_index_offset; +input [15:0] reg2dp_lut_le_slope_oflow_scale; +input [4:0] reg2dp_lut_le_slope_oflow_shift; +input [15:0] reg2dp_lut_le_slope_uflow_scale; +input [4:0] reg2dp_lut_le_slope_uflow_shift; +input [31:0] reg2dp_lut_le_start; +input [31:0] reg2dp_lut_lo_end; +input [15:0] reg2dp_lut_lo_slope_oflow_scale; +input [4:0] reg2dp_lut_lo_slope_oflow_shift; +input [15:0] reg2dp_lut_lo_slope_uflow_scale; +input [4:0] reg2dp_lut_lo_slope_uflow_shift; +input [31:0] reg2dp_lut_lo_start; +input reg2dp_perf_lut_en; +input [1:0] reg2dp_proc_precision; +output [31:0] dp2reg_lut_hybrid; +output [15:0] dp2reg_lut_int_data; +output [31:0] dp2reg_lut_le_hit; +output [31:0] dp2reg_lut_lo_hit; +output [31:0] dp2reg_lut_oflow; +output [31:0] dp2reg_lut_uflow; +input [31:0] pwrbus_ram_pd; +input op_en_load; +reg idx2lut_prdy; +reg [185*0 -1:0] lut2inp_pd; +reg lut2inp_pvld; +reg [81*0 -1:0] lut_in_pd; +reg lut_in_pvld; +wire lut_in_prdy; +wire [185*0 -1:0] lut_out_pd; +wire lut_out_pvld; +reg lut_out_prdy; +//: my $k = 0; +//: my $m = 257; +//: foreach my $lut (qw(le lo)) { +//: foreach my $i (0..${m}-1) { +//: print "reg [15:0] REG_${lut}_${i}; \n"; +//: } +//: } +//: foreach my $lut (qw(le lo)) { +//: foreach my $j (0..1) { +//: foreach my $i (0..${k}-1) { +//: print "reg [15:0] ${lut}_data${j}_${i}; \n"; +//: } +//: } +//: } +reg [15:0] le_lut_data; +reg [15:0] lo_lut_data; +//: my $k = 0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: reg [31:0] out_bias${i}; +//: reg [31:0] out_offset${i}; +//: reg [15:0] out_scale${i}; +//: reg [4:0] out_shift${i}; +//: ); +//: } +wire [4:0] lut_hybrid_sum; +wire [4:0] lut_le_hit_sum; +wire [4:0] lut_lo_hit_sum; +wire [4:0] lut_oflow_sum; +wire [4:0] lut_uflow_sum; +wire [4:0] perf_lut_hybrid_add; +wire [0:0] perf_lut_hybrid_sub; +wire [4:0] perf_lut_le_hit_add; +wire [0:0] perf_lut_le_hit_sub; +wire [4:0] perf_lut_lo_hit_add; +wire [0:0] perf_lut_lo_hit_sub; +wire [4:0] perf_lut_oflow_add; +wire [0:0] perf_lut_oflow_sub; +wire [4:0] perf_lut_uflow_add; +wire [0:0] perf_lut_uflow_sub; +reg [31:0] lut_hybrid_cnt; +reg [31:0] lut_le_hit_cnt; +reg [31:0] lut_lo_hit_cnt; +reg [31:0] lut_oflow_cnt; +reg [31:0] lut_uflow_cnt; +reg perf_lut_hybrid_adv; +reg [31:0] perf_lut_hybrid_cnt_cur; +reg [33:0] perf_lut_hybrid_cnt_ext; +reg [33:0] perf_lut_hybrid_cnt_mod; +reg [33:0] perf_lut_hybrid_cnt_new; +reg [33:0] perf_lut_hybrid_cnt_nxt; +reg perf_lut_le_hit_adv; +reg [31:0] perf_lut_le_hit_cnt_cur; +reg [33:0] perf_lut_le_hit_cnt_ext; +reg [33:0] perf_lut_le_hit_cnt_mod; +reg [33:0] perf_lut_le_hit_cnt_new; +reg [33:0] perf_lut_le_hit_cnt_nxt; +reg perf_lut_lo_hit_adv; +reg [31:0] perf_lut_lo_hit_cnt_cur; +reg [33:0] perf_lut_lo_hit_cnt_ext; +reg [33:0] perf_lut_lo_hit_cnt_mod; +reg [33:0] perf_lut_lo_hit_cnt_new; +reg [33:0] perf_lut_lo_hit_cnt_nxt; +reg perf_lut_oflow_adv; +reg [31:0] perf_lut_oflow_cnt_cur; +reg [33:0] perf_lut_oflow_cnt_ext; +reg [33:0] perf_lut_oflow_cnt_mod; +reg [33:0] perf_lut_oflow_cnt_new; +reg [33:0] perf_lut_oflow_cnt_nxt; +reg perf_lut_uflow_adv; +reg [31:0] perf_lut_uflow_cnt_cur; +reg [33:0] perf_lut_uflow_cnt_ext; +reg [33:0] perf_lut_uflow_cnt_mod; +reg [33:0] perf_lut_uflow_cnt_new; +reg [33:0] perf_lut_uflow_cnt_nxt; +wire [70*0 -1:0] cmd_fifo_rd_pd; +wire cmd_fifo_rd_prdy; +wire cmd_fifo_rd_pvld; +wire [70*0 -1:0] cmd_fifo_wr_pd; +wire cmd_fifo_wr_prdy; +wire cmd_fifo_wr_pvld; +wire [32*0 -1:0] dat_fifo_rd_pd; +wire dat_fifo_rd_prdy; +wire dat_fifo_rd_pvld; +wire [32*0 -1:0] dat_fifo_wr_pd; +wire dat_fifo_wr_pvld; +//: my $k = 0; +//: foreach my $j (0..1) { +//: foreach my $i (0..${k}-1) { +//: print"wire [15:0] dat_in_y${j}_${i}; \n"; +//: } +//: } +//: my $ed = 65; +//: my $od = 257; +//: foreach my $i (0..${ed}-1) { +//: print"wire le_wr_en_$i; \n"; +//: } +//: foreach my $i (0..${od}-1) { +//: print"wire lo_wr_en_$i; \n"; +//: } +//: my $k = 0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [8:0] lut_in_addr${i}; +//: wire [8:0] lut_in_addr${i}_0; +//: wire [8:0] lut_in_addr${i}_1; +//: wire [34:0] lut_in_fraction${i}; +//: wire lut_in_hybrid${i}; +//: wire lut_in_le_hit${i}; +//: wire lut_in_lo_hit${i}; +//: wire lut_in_oflow${i}; +//: wire lut_in_sel${i}; +//: wire lut_in_uflow${i}; +//: wire [31:0] lut_in_x${i}; +//: wire out_flow${i}; +//: wire [34:0] out_fraction${i}; +//: wire out_oflow${i}; +//: wire out_sel${i}; +//: wire out_uflow${i}; +//: wire [31:0] out_x${i}; +//: wire [15:0] out_y0_${i}; +//: wire [15:0] out_y1_${i}; +//: ); +//: } +wire lut_access_type; +wire [9:0] lut_addr; +wire [15:0] lut_data; +wire [27:0] pro2lut_pd; +wire pro2lut_valid; +wire [9:0] pro_in_addr; +wire [15:0] pro_in_data; +wire pro_in_select_le; +wire pro_in_select_lo; +wire pro_in_table_id; +wire pro_in_wr; +wire pro_in_wr_en; +wire rd_lut_en; +wire [27:0] lut_pd; +wire lut_table_id; +wire mon_cmd_fifo_rd_pvld; +//============== +// Reg Configure +//============== +// get the width of all regs +//======================================= +//=========================================== +// LUT Programing +//=========================================== +assign lut_addr = reg2dp_lut_int_addr[9:0]; +assign lut_data = reg2dp_lut_int_data[15:0]; +assign lut_table_id = reg2dp_lut_int_table_id; +assign lut_access_type = reg2dp_lut_int_access_type; +assign lut_pd = {lut_access_type,lut_table_id,lut_data,lut_addr}; +assign pro2lut_valid = reg2dp_lut_int_data_wr; +assign pro2lut_pd = lut_pd; +// PKT_UNPACK_WIRE( sdp_y_lut_pro , pro_in_ , pro2lut_pd ) +assign pro_in_addr[9:0] = pro2lut_pd[9:0]; +assign pro_in_data[15:0] = pro2lut_pd[25:10]; +assign pro_in_table_id = pro2lut_pd[26]; +assign pro_in_wr = pro2lut_pd[27]; +assign pro_in_wr_en = pro2lut_valid & (pro_in_wr== 1'h1 ); +//assign pro_in_rd_en = pro2lut_valid & pro_in_wr==0; +assign pro_in_select_le = pro_in_table_id== 1'h0 ; +assign pro_in_select_lo = pro_in_table_id== 1'h1 ; +//=========================================== +// READ LUT +always @( + pro_in_addr + or REG_le_0 + or REG_le_1 + or REG_le_2 + or REG_le_3 + or REG_le_4 + or REG_le_5 + or REG_le_6 + or REG_le_7 + or REG_le_8 + or REG_le_9 + or REG_le_10 + or REG_le_11 + or REG_le_12 + or REG_le_13 + or REG_le_14 + or REG_le_15 + or REG_le_16 + or REG_le_17 + or REG_le_18 + or REG_le_19 + or REG_le_20 + or REG_le_21 + or REG_le_22 + or REG_le_23 + or REG_le_24 + or REG_le_25 + or REG_le_26 + or REG_le_27 + or REG_le_28 + or REG_le_29 + or REG_le_30 + or REG_le_31 + or REG_le_32 + or REG_le_33 + or REG_le_34 + or REG_le_35 + or REG_le_36 + or REG_le_37 + or REG_le_38 + or REG_le_39 + or REG_le_40 + or REG_le_41 + or REG_le_42 + or REG_le_43 + or REG_le_44 + or REG_le_45 + or REG_le_46 + or REG_le_47 + or REG_le_48 + or REG_le_49 + or REG_le_50 + or REG_le_51 + or REG_le_52 + or REG_le_53 + or REG_le_54 + or REG_le_55 + or REG_le_56 + or REG_le_57 + or REG_le_58 + or REG_le_59 + or REG_le_60 + or REG_le_61 + or REG_le_62 + or REG_le_63 + or REG_le_64 + ) begin + case (pro_in_addr) +0: le_lut_data = REG_le_0; +1: le_lut_data = REG_le_1; +2: le_lut_data = REG_le_2; +3: le_lut_data = REG_le_3; +4: le_lut_data = REG_le_4; +5: le_lut_data = REG_le_5; +6: le_lut_data = REG_le_6; +7: le_lut_data = REG_le_7; +8: le_lut_data = REG_le_8; +9: le_lut_data = REG_le_9; +10: le_lut_data = REG_le_10; +11: le_lut_data = REG_le_11; +12: le_lut_data = REG_le_12; +13: le_lut_data = REG_le_13; +14: le_lut_data = REG_le_14; +15: le_lut_data = REG_le_15; +16: le_lut_data = REG_le_16; +17: le_lut_data = REG_le_17; +18: le_lut_data = REG_le_18; +19: le_lut_data = REG_le_19; +20: le_lut_data = REG_le_20; +21: le_lut_data = REG_le_21; +22: le_lut_data = REG_le_22; +23: le_lut_data = REG_le_23; +24: le_lut_data = REG_le_24; +25: le_lut_data = REG_le_25; +26: le_lut_data = REG_le_26; +27: le_lut_data = REG_le_27; +28: le_lut_data = REG_le_28; +29: le_lut_data = REG_le_29; +30: le_lut_data = REG_le_30; +31: le_lut_data = REG_le_31; +32: le_lut_data = REG_le_32; +33: le_lut_data = REG_le_33; +34: le_lut_data = REG_le_34; +35: le_lut_data = REG_le_35; +36: le_lut_data = REG_le_36; +37: le_lut_data = REG_le_37; +38: le_lut_data = REG_le_38; +39: le_lut_data = REG_le_39; +40: le_lut_data = REG_le_40; +41: le_lut_data = REG_le_41; +42: le_lut_data = REG_le_42; +43: le_lut_data = REG_le_43; +44: le_lut_data = REG_le_44; +45: le_lut_data = REG_le_45; +46: le_lut_data = REG_le_46; +47: le_lut_data = REG_le_47; +48: le_lut_data = REG_le_48; +49: le_lut_data = REG_le_49; +50: le_lut_data = REG_le_50; +51: le_lut_data = REG_le_51; +52: le_lut_data = REG_le_52; +53: le_lut_data = REG_le_53; +54: le_lut_data = REG_le_54; +55: le_lut_data = REG_le_55; +56: le_lut_data = REG_le_56; +57: le_lut_data = REG_le_57; +58: le_lut_data = REG_le_58; +59: le_lut_data = REG_le_59; +60: le_lut_data = REG_le_60; +61: le_lut_data = REG_le_61; +62: le_lut_data = REG_le_62; +63: le_lut_data = REG_le_63; +64: le_lut_data = REG_le_64; +//VCS coverage off + default : begin + le_lut_data[15:0] = {16{`x_or_0}}; + end +//VCS coverage on + endcase +end +always @( + pro_in_addr + or REG_lo_0 + or REG_lo_1 + or REG_lo_2 + or REG_lo_3 + or REG_lo_4 + or REG_lo_5 + or REG_lo_6 + or REG_lo_7 + or REG_lo_8 + or REG_lo_9 + or REG_lo_10 + or REG_lo_11 + or REG_lo_12 + or REG_lo_13 + or REG_lo_14 + or REG_lo_15 + or REG_lo_16 + or REG_lo_17 + or REG_lo_18 + or REG_lo_19 + or REG_lo_20 + or REG_lo_21 + or REG_lo_22 + or REG_lo_23 + or REG_lo_24 + or REG_lo_25 + or REG_lo_26 + or REG_lo_27 + or REG_lo_28 + or REG_lo_29 + or REG_lo_30 + or REG_lo_31 + or REG_lo_32 + or REG_lo_33 + or REG_lo_34 + or REG_lo_35 + or REG_lo_36 + or REG_lo_37 + or REG_lo_38 + or REG_lo_39 + or REG_lo_40 + or REG_lo_41 + or REG_lo_42 + or REG_lo_43 + or REG_lo_44 + or REG_lo_45 + or REG_lo_46 + or REG_lo_47 + or REG_lo_48 + or REG_lo_49 + or REG_lo_50 + or REG_lo_51 + or REG_lo_52 + or REG_lo_53 + or REG_lo_54 + or REG_lo_55 + or REG_lo_56 + or REG_lo_57 + or REG_lo_58 + or REG_lo_59 + or REG_lo_60 + or REG_lo_61 + or REG_lo_62 + or REG_lo_63 + or REG_lo_64 + or REG_lo_65 + or REG_lo_66 + or REG_lo_67 + or REG_lo_68 + or REG_lo_69 + or REG_lo_70 + or REG_lo_71 + or REG_lo_72 + or REG_lo_73 + or REG_lo_74 + or REG_lo_75 + or REG_lo_76 + or REG_lo_77 + or REG_lo_78 + or REG_lo_79 + or REG_lo_80 + or REG_lo_81 + or REG_lo_82 + or REG_lo_83 + or REG_lo_84 + or REG_lo_85 + or REG_lo_86 + or REG_lo_87 + or REG_lo_88 + or REG_lo_89 + or REG_lo_90 + or REG_lo_91 + or REG_lo_92 + or REG_lo_93 + or REG_lo_94 + or REG_lo_95 + or REG_lo_96 + or REG_lo_97 + or REG_lo_98 + or REG_lo_99 + or REG_lo_100 + or REG_lo_101 + or REG_lo_102 + or REG_lo_103 + or REG_lo_104 + or REG_lo_105 + or REG_lo_106 + or REG_lo_107 + or REG_lo_108 + or REG_lo_109 + or REG_lo_110 + or REG_lo_111 + or REG_lo_112 + or REG_lo_113 + or REG_lo_114 + or REG_lo_115 + or REG_lo_116 + or REG_lo_117 + or REG_lo_118 + or REG_lo_119 + or REG_lo_120 + or REG_lo_121 + or REG_lo_122 + or REG_lo_123 + or REG_lo_124 + or REG_lo_125 + or REG_lo_126 + or REG_lo_127 + or REG_lo_128 + or REG_lo_129 + or REG_lo_130 + or REG_lo_131 + or REG_lo_132 + or REG_lo_133 + or REG_lo_134 + or REG_lo_135 + or REG_lo_136 + or REG_lo_137 + or REG_lo_138 + or REG_lo_139 + or REG_lo_140 + or REG_lo_141 + or REG_lo_142 + or REG_lo_143 + or REG_lo_144 + or REG_lo_145 + or REG_lo_146 + or REG_lo_147 + or REG_lo_148 + or REG_lo_149 + or REG_lo_150 + or REG_lo_151 + or REG_lo_152 + or REG_lo_153 + or REG_lo_154 + or REG_lo_155 + or REG_lo_156 + or REG_lo_157 + or REG_lo_158 + or REG_lo_159 + or REG_lo_160 + or REG_lo_161 + or REG_lo_162 + or REG_lo_163 + or REG_lo_164 + or REG_lo_165 + or REG_lo_166 + or REG_lo_167 + or REG_lo_168 + or REG_lo_169 + or REG_lo_170 + or REG_lo_171 + or REG_lo_172 + or REG_lo_173 + or REG_lo_174 + or REG_lo_175 + or REG_lo_176 + or REG_lo_177 + or REG_lo_178 + or REG_lo_179 + or REG_lo_180 + or REG_lo_181 + or REG_lo_182 + or REG_lo_183 + or REG_lo_184 + or REG_lo_185 + or REG_lo_186 + or REG_lo_187 + or REG_lo_188 + or REG_lo_189 + or REG_lo_190 + or REG_lo_191 + or REG_lo_192 + or REG_lo_193 + or REG_lo_194 + or REG_lo_195 + or REG_lo_196 + or REG_lo_197 + or REG_lo_198 + or REG_lo_199 + or REG_lo_200 + or REG_lo_201 + or REG_lo_202 + or REG_lo_203 + or REG_lo_204 + or REG_lo_205 + or REG_lo_206 + or REG_lo_207 + or REG_lo_208 + or REG_lo_209 + or REG_lo_210 + or REG_lo_211 + or REG_lo_212 + or REG_lo_213 + or REG_lo_214 + or REG_lo_215 + or REG_lo_216 + or REG_lo_217 + or REG_lo_218 + or REG_lo_219 + or REG_lo_220 + or REG_lo_221 + or REG_lo_222 + or REG_lo_223 + or REG_lo_224 + or REG_lo_225 + or REG_lo_226 + or REG_lo_227 + or REG_lo_228 + or REG_lo_229 + or REG_lo_230 + or REG_lo_231 + or REG_lo_232 + or REG_lo_233 + or REG_lo_234 + or REG_lo_235 + or REG_lo_236 + or REG_lo_237 + or REG_lo_238 + or REG_lo_239 + or REG_lo_240 + or REG_lo_241 + or REG_lo_242 + or REG_lo_243 + or REG_lo_244 + or REG_lo_245 + or REG_lo_246 + or REG_lo_247 + or REG_lo_248 + or REG_lo_249 + or REG_lo_250 + or REG_lo_251 + or REG_lo_252 + or REG_lo_253 + or REG_lo_254 + or REG_lo_255 + or REG_lo_256 + ) begin + case (pro_in_addr) +0: lo_lut_data = REG_lo_0; +1: lo_lut_data = REG_lo_1; +2: lo_lut_data = REG_lo_2; +3: lo_lut_data = REG_lo_3; +4: lo_lut_data = REG_lo_4; +5: lo_lut_data = REG_lo_5; +6: lo_lut_data = REG_lo_6; +7: lo_lut_data = REG_lo_7; +8: lo_lut_data = REG_lo_8; +9: lo_lut_data = REG_lo_9; +10: lo_lut_data = REG_lo_10; +11: lo_lut_data = REG_lo_11; +12: lo_lut_data = REG_lo_12; +13: lo_lut_data = REG_lo_13; +14: lo_lut_data = REG_lo_14; +15: lo_lut_data = REG_lo_15; +16: lo_lut_data = REG_lo_16; +17: lo_lut_data = REG_lo_17; +18: lo_lut_data = REG_lo_18; +19: lo_lut_data = REG_lo_19; +20: lo_lut_data = REG_lo_20; +21: lo_lut_data = REG_lo_21; +22: lo_lut_data = REG_lo_22; +23: lo_lut_data = REG_lo_23; +24: lo_lut_data = REG_lo_24; +25: lo_lut_data = REG_lo_25; +26: lo_lut_data = REG_lo_26; +27: lo_lut_data = REG_lo_27; +28: lo_lut_data = REG_lo_28; +29: lo_lut_data = REG_lo_29; +30: lo_lut_data = REG_lo_30; +31: lo_lut_data = REG_lo_31; +32: lo_lut_data = REG_lo_32; +33: lo_lut_data = REG_lo_33; +34: lo_lut_data = REG_lo_34; +35: lo_lut_data = REG_lo_35; +36: lo_lut_data = REG_lo_36; +37: lo_lut_data = REG_lo_37; +38: lo_lut_data = REG_lo_38; +39: lo_lut_data = REG_lo_39; +40: lo_lut_data = REG_lo_40; +41: lo_lut_data = REG_lo_41; +42: lo_lut_data = REG_lo_42; +43: lo_lut_data = REG_lo_43; +44: lo_lut_data = REG_lo_44; +45: lo_lut_data = REG_lo_45; +46: lo_lut_data = REG_lo_46; +47: lo_lut_data = REG_lo_47; +48: lo_lut_data = REG_lo_48; +49: lo_lut_data = REG_lo_49; +50: lo_lut_data = REG_lo_50; +51: lo_lut_data = REG_lo_51; +52: lo_lut_data = REG_lo_52; +53: lo_lut_data = REG_lo_53; +54: lo_lut_data = REG_lo_54; +55: lo_lut_data = REG_lo_55; +56: lo_lut_data = REG_lo_56; +57: lo_lut_data = REG_lo_57; +58: lo_lut_data = REG_lo_58; +59: lo_lut_data = REG_lo_59; +60: lo_lut_data = REG_lo_60; +61: lo_lut_data = REG_lo_61; +62: lo_lut_data = REG_lo_62; +63: lo_lut_data = REG_lo_63; +64: lo_lut_data = REG_lo_64; +65: lo_lut_data = REG_lo_65; +66: lo_lut_data = REG_lo_66; +67: lo_lut_data = REG_lo_67; +68: lo_lut_data = REG_lo_68; +69: lo_lut_data = REG_lo_69; +70: lo_lut_data = REG_lo_70; +71: lo_lut_data = REG_lo_71; +72: lo_lut_data = REG_lo_72; +73: lo_lut_data = REG_lo_73; +74: lo_lut_data = REG_lo_74; +75: lo_lut_data = REG_lo_75; +76: lo_lut_data = REG_lo_76; +77: lo_lut_data = REG_lo_77; +78: lo_lut_data = REG_lo_78; +79: lo_lut_data = REG_lo_79; +80: lo_lut_data = REG_lo_80; +81: lo_lut_data = REG_lo_81; +82: lo_lut_data = REG_lo_82; +83: lo_lut_data = REG_lo_83; +84: lo_lut_data = REG_lo_84; +85: lo_lut_data = REG_lo_85; +86: lo_lut_data = REG_lo_86; +87: lo_lut_data = REG_lo_87; +88: lo_lut_data = REG_lo_88; +89: lo_lut_data = REG_lo_89; +90: lo_lut_data = REG_lo_90; +91: lo_lut_data = REG_lo_91; +92: lo_lut_data = REG_lo_92; +93: lo_lut_data = REG_lo_93; +94: lo_lut_data = REG_lo_94; +95: lo_lut_data = REG_lo_95; +96: lo_lut_data = REG_lo_96; +97: lo_lut_data = REG_lo_97; +98: lo_lut_data = REG_lo_98; +99: lo_lut_data = REG_lo_99; +100: lo_lut_data = REG_lo_100; +101: lo_lut_data = REG_lo_101; +102: lo_lut_data = REG_lo_102; +103: lo_lut_data = REG_lo_103; +104: lo_lut_data = REG_lo_104; +105: lo_lut_data = REG_lo_105; +106: lo_lut_data = REG_lo_106; +107: lo_lut_data = REG_lo_107; +108: lo_lut_data = REG_lo_108; +109: lo_lut_data = REG_lo_109; +110: lo_lut_data = REG_lo_110; +111: lo_lut_data = REG_lo_111; +112: lo_lut_data = REG_lo_112; +113: lo_lut_data = REG_lo_113; +114: lo_lut_data = REG_lo_114; +115: lo_lut_data = REG_lo_115; +116: lo_lut_data = REG_lo_116; +117: lo_lut_data = REG_lo_117; +118: lo_lut_data = REG_lo_118; +119: lo_lut_data = REG_lo_119; +120: lo_lut_data = REG_lo_120; +121: lo_lut_data = REG_lo_121; +122: lo_lut_data = REG_lo_122; +123: lo_lut_data = REG_lo_123; +124: lo_lut_data = REG_lo_124; +125: lo_lut_data = REG_lo_125; +126: lo_lut_data = REG_lo_126; +127: lo_lut_data = REG_lo_127; +128: lo_lut_data = REG_lo_128; +129: lo_lut_data = REG_lo_129; +130: lo_lut_data = REG_lo_130; +131: lo_lut_data = REG_lo_131; +132: lo_lut_data = REG_lo_132; +133: lo_lut_data = REG_lo_133; +134: lo_lut_data = REG_lo_134; +135: lo_lut_data = REG_lo_135; +136: lo_lut_data = REG_lo_136; +137: lo_lut_data = REG_lo_137; +138: lo_lut_data = REG_lo_138; +139: lo_lut_data = REG_lo_139; +140: lo_lut_data = REG_lo_140; +141: lo_lut_data = REG_lo_141; +142: lo_lut_data = REG_lo_142; +143: lo_lut_data = REG_lo_143; +144: lo_lut_data = REG_lo_144; +145: lo_lut_data = REG_lo_145; +146: lo_lut_data = REG_lo_146; +147: lo_lut_data = REG_lo_147; +148: lo_lut_data = REG_lo_148; +149: lo_lut_data = REG_lo_149; +150: lo_lut_data = REG_lo_150; +151: lo_lut_data = REG_lo_151; +152: lo_lut_data = REG_lo_152; +153: lo_lut_data = REG_lo_153; +154: lo_lut_data = REG_lo_154; +155: lo_lut_data = REG_lo_155; +156: lo_lut_data = REG_lo_156; +157: lo_lut_data = REG_lo_157; +158: lo_lut_data = REG_lo_158; +159: lo_lut_data = REG_lo_159; +160: lo_lut_data = REG_lo_160; +161: lo_lut_data = REG_lo_161; +162: lo_lut_data = REG_lo_162; +163: lo_lut_data = REG_lo_163; +164: lo_lut_data = REG_lo_164; +165: lo_lut_data = REG_lo_165; +166: lo_lut_data = REG_lo_166; +167: lo_lut_data = REG_lo_167; +168: lo_lut_data = REG_lo_168; +169: lo_lut_data = REG_lo_169; +170: lo_lut_data = REG_lo_170; +171: lo_lut_data = REG_lo_171; +172: lo_lut_data = REG_lo_172; +173: lo_lut_data = REG_lo_173; +174: lo_lut_data = REG_lo_174; +175: lo_lut_data = REG_lo_175; +176: lo_lut_data = REG_lo_176; +177: lo_lut_data = REG_lo_177; +178: lo_lut_data = REG_lo_178; +179: lo_lut_data = REG_lo_179; +180: lo_lut_data = REG_lo_180; +181: lo_lut_data = REG_lo_181; +182: lo_lut_data = REG_lo_182; +183: lo_lut_data = REG_lo_183; +184: lo_lut_data = REG_lo_184; +185: lo_lut_data = REG_lo_185; +186: lo_lut_data = REG_lo_186; +187: lo_lut_data = REG_lo_187; +188: lo_lut_data = REG_lo_188; +189: lo_lut_data = REG_lo_189; +190: lo_lut_data = REG_lo_190; +191: lo_lut_data = REG_lo_191; +192: lo_lut_data = REG_lo_192; +193: lo_lut_data = REG_lo_193; +194: lo_lut_data = REG_lo_194; +195: lo_lut_data = REG_lo_195; +196: lo_lut_data = REG_lo_196; +197: lo_lut_data = REG_lo_197; +198: lo_lut_data = REG_lo_198; +199: lo_lut_data = REG_lo_199; +200: lo_lut_data = REG_lo_200; +201: lo_lut_data = REG_lo_201; +202: lo_lut_data = REG_lo_202; +203: lo_lut_data = REG_lo_203; +204: lo_lut_data = REG_lo_204; +205: lo_lut_data = REG_lo_205; +206: lo_lut_data = REG_lo_206; +207: lo_lut_data = REG_lo_207; +208: lo_lut_data = REG_lo_208; +209: lo_lut_data = REG_lo_209; +210: lo_lut_data = REG_lo_210; +211: lo_lut_data = REG_lo_211; +212: lo_lut_data = REG_lo_212; +213: lo_lut_data = REG_lo_213; +214: lo_lut_data = REG_lo_214; +215: lo_lut_data = REG_lo_215; +216: lo_lut_data = REG_lo_216; +217: lo_lut_data = REG_lo_217; +218: lo_lut_data = REG_lo_218; +219: lo_lut_data = REG_lo_219; +220: lo_lut_data = REG_lo_220; +221: lo_lut_data = REG_lo_221; +222: lo_lut_data = REG_lo_222; +223: lo_lut_data = REG_lo_223; +224: lo_lut_data = REG_lo_224; +225: lo_lut_data = REG_lo_225; +226: lo_lut_data = REG_lo_226; +227: lo_lut_data = REG_lo_227; +228: lo_lut_data = REG_lo_228; +229: lo_lut_data = REG_lo_229; +230: lo_lut_data = REG_lo_230; +231: lo_lut_data = REG_lo_231; +232: lo_lut_data = REG_lo_232; +233: lo_lut_data = REG_lo_233; +234: lo_lut_data = REG_lo_234; +235: lo_lut_data = REG_lo_235; +236: lo_lut_data = REG_lo_236; +237: lo_lut_data = REG_lo_237; +238: lo_lut_data = REG_lo_238; +239: lo_lut_data = REG_lo_239; +240: lo_lut_data = REG_lo_240; +241: lo_lut_data = REG_lo_241; +242: lo_lut_data = REG_lo_242; +243: lo_lut_data = REG_lo_243; +244: lo_lut_data = REG_lo_244; +245: lo_lut_data = REG_lo_245; +246: lo_lut_data = REG_lo_246; +247: lo_lut_data = REG_lo_247; +248: lo_lut_data = REG_lo_248; +249: lo_lut_data = REG_lo_249; +250: lo_lut_data = REG_lo_250; +251: lo_lut_data = REG_lo_251; +252: lo_lut_data = REG_lo_252; +253: lo_lut_data = REG_lo_253; +254: lo_lut_data = REG_lo_254; +255: lo_lut_data = REG_lo_255; +256: lo_lut_data = REG_lo_256; +//VCS coverage off + default : begin + lo_lut_data[15:0] = {16{`x_or_0}}; + end +//VCS coverage on + endcase +end +assign dp2reg_lut_int_data = pro_in_select_le ? le_lut_data : lo_lut_data; +//======================================= +// WRITE LUT +assign le_wr_en_0 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_0 <= {16{1'b0}}; + end else begin + if ((le_wr_en_0) == 1'b1) begin + REG_le_0 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_0) == 1'b0) begin + end else begin + REG_le_0 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_0))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_1 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_1 <= {16{1'b0}}; + end else begin + if ((le_wr_en_1) == 1'b1) begin + REG_le_1 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_1) == 1'b0) begin + end else begin + REG_le_1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_2 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==2); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_2 <= {16{1'b0}}; + end else begin + if ((le_wr_en_2) == 1'b1) begin + REG_le_2 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_2) == 1'b0) begin + end else begin + REG_le_2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_2))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_3 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==3); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_3 <= {16{1'b0}}; + end else begin + if ((le_wr_en_3) == 1'b1) begin + REG_le_3 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_3) == 1'b0) begin + end else begin + REG_le_3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_3))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_4 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==4); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_4 <= {16{1'b0}}; + end else begin + if ((le_wr_en_4) == 1'b1) begin + REG_le_4 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_4) == 1'b0) begin + end else begin + REG_le_4 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_4))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_5 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==5); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_5 <= {16{1'b0}}; + end else begin + if ((le_wr_en_5) == 1'b1) begin + REG_le_5 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_5) == 1'b0) begin + end else begin + REG_le_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_5))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_6 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==6); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_6 <= {16{1'b0}}; + end else begin + if ((le_wr_en_6) == 1'b1) begin + REG_le_6 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_6) == 1'b0) begin + end else begin + REG_le_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_6))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_7 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==7); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_7 <= {16{1'b0}}; + end else begin + if ((le_wr_en_7) == 1'b1) begin + REG_le_7 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_7) == 1'b0) begin + end else begin + REG_le_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_7))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_8 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==8); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_8 <= {16{1'b0}}; + end else begin + if ((le_wr_en_8) == 1'b1) begin + REG_le_8 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_8) == 1'b0) begin + end else begin + REG_le_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_8))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_9 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==9); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_9 <= {16{1'b0}}; + end else begin + if ((le_wr_en_9) == 1'b1) begin + REG_le_9 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_9) == 1'b0) begin + end else begin + REG_le_9 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_9))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_10 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==10); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_10 <= {16{1'b0}}; + end else begin + if ((le_wr_en_10) == 1'b1) begin + REG_le_10 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_10) == 1'b0) begin + end else begin + REG_le_10 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_10))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_11 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==11); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_11 <= {16{1'b0}}; + end else begin + if ((le_wr_en_11) == 1'b1) begin + REG_le_11 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_11) == 1'b0) begin + end else begin + REG_le_11 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_11))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_12 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==12); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_12 <= {16{1'b0}}; + end else begin + if ((le_wr_en_12) == 1'b1) begin + REG_le_12 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_12) == 1'b0) begin + end else begin + REG_le_12 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_12))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_13 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==13); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_13 <= {16{1'b0}}; + end else begin + if ((le_wr_en_13) == 1'b1) begin + REG_le_13 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_13) == 1'b0) begin + end else begin + REG_le_13 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_13))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_14 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==14); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_14 <= {16{1'b0}}; + end else begin + if ((le_wr_en_14) == 1'b1) begin + REG_le_14 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_14) == 1'b0) begin + end else begin + REG_le_14 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_14))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_15 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==15); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_15 <= {16{1'b0}}; + end else begin + if ((le_wr_en_15) == 1'b1) begin + REG_le_15 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_15) == 1'b0) begin + end else begin + REG_le_15 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_15))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_16 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==16); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_16 <= {16{1'b0}}; + end else begin + if ((le_wr_en_16) == 1'b1) begin + REG_le_16 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_16) == 1'b0) begin + end else begin + REG_le_16 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_16))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_17 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==17); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_17 <= {16{1'b0}}; + end else begin + if ((le_wr_en_17) == 1'b1) begin + REG_le_17 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_17) == 1'b0) begin + end else begin + REG_le_17 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_17))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_18 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==18); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_18 <= {16{1'b0}}; + end else begin + if ((le_wr_en_18) == 1'b1) begin + REG_le_18 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_18) == 1'b0) begin + end else begin + REG_le_18 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_18))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_19 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==19); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_19 <= {16{1'b0}}; + end else begin + if ((le_wr_en_19) == 1'b1) begin + REG_le_19 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_19) == 1'b0) begin + end else begin + REG_le_19 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_19))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_20 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==20); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_20 <= {16{1'b0}}; + end else begin + if ((le_wr_en_20) == 1'b1) begin + REG_le_20 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_20) == 1'b0) begin + end else begin + REG_le_20 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_20))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_21 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==21); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_21 <= {16{1'b0}}; + end else begin + if ((le_wr_en_21) == 1'b1) begin + REG_le_21 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_21) == 1'b0) begin + end else begin + REG_le_21 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_21))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_22 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==22); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_22 <= {16{1'b0}}; + end else begin + if ((le_wr_en_22) == 1'b1) begin + REG_le_22 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_22) == 1'b0) begin + end else begin + REG_le_22 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_22))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_23 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==23); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_23 <= {16{1'b0}}; + end else begin + if ((le_wr_en_23) == 1'b1) begin + REG_le_23 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_23) == 1'b0) begin + end else begin + REG_le_23 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_23))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_24 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==24); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_24 <= {16{1'b0}}; + end else begin + if ((le_wr_en_24) == 1'b1) begin + REG_le_24 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_24) == 1'b0) begin + end else begin + REG_le_24 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_24))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_25 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==25); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_25 <= {16{1'b0}}; + end else begin + if ((le_wr_en_25) == 1'b1) begin + REG_le_25 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_25) == 1'b0) begin + end else begin + REG_le_25 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_25))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_26 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==26); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_26 <= {16{1'b0}}; + end else begin + if ((le_wr_en_26) == 1'b1) begin + REG_le_26 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_26) == 1'b0) begin + end else begin + REG_le_26 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_26))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_27 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==27); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_27 <= {16{1'b0}}; + end else begin + if ((le_wr_en_27) == 1'b1) begin + REG_le_27 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_27) == 1'b0) begin + end else begin + REG_le_27 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_27))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_28 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==28); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_28 <= {16{1'b0}}; + end else begin + if ((le_wr_en_28) == 1'b1) begin + REG_le_28 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_28) == 1'b0) begin + end else begin + REG_le_28 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_28))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_29 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==29); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_29 <= {16{1'b0}}; + end else begin + if ((le_wr_en_29) == 1'b1) begin + REG_le_29 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_29) == 1'b0) begin + end else begin + REG_le_29 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_30x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_29))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_30 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==30); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_30 <= {16{1'b0}}; + end else begin + if ((le_wr_en_30) == 1'b1) begin + REG_le_30 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_30) == 1'b0) begin + end else begin + REG_le_30 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_31x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_30))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_31 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==31); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_31 <= {16{1'b0}}; + end else begin + if ((le_wr_en_31) == 1'b1) begin + REG_le_31 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_31) == 1'b0) begin + end else begin + REG_le_31 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_32x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_31))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_32 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==32); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_32 <= {16{1'b0}}; + end else begin + if ((le_wr_en_32) == 1'b1) begin + REG_le_32 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_32) == 1'b0) begin + end else begin + REG_le_32 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_33x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_32))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_33 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==33); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_33 <= {16{1'b0}}; + end else begin + if ((le_wr_en_33) == 1'b1) begin + REG_le_33 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_33) == 1'b0) begin + end else begin + REG_le_33 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_34x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_33))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_34 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==34); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_34 <= {16{1'b0}}; + end else begin + if ((le_wr_en_34) == 1'b1) begin + REG_le_34 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_34) == 1'b0) begin + end else begin + REG_le_34 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_35x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_34))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_35 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==35); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_35 <= {16{1'b0}}; + end else begin + if ((le_wr_en_35) == 1'b1) begin + REG_le_35 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_35) == 1'b0) begin + end else begin + REG_le_35 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_36x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_35))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_36 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==36); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_36 <= {16{1'b0}}; + end else begin + if ((le_wr_en_36) == 1'b1) begin + REG_le_36 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_36) == 1'b0) begin + end else begin + REG_le_36 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_37x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_36))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_37 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==37); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_37 <= {16{1'b0}}; + end else begin + if ((le_wr_en_37) == 1'b1) begin + REG_le_37 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_37) == 1'b0) begin + end else begin + REG_le_37 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_38x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_37))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_38 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==38); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_38 <= {16{1'b0}}; + end else begin + if ((le_wr_en_38) == 1'b1) begin + REG_le_38 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_38) == 1'b0) begin + end else begin + REG_le_38 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_39x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_38))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_39 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==39); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_39 <= {16{1'b0}}; + end else begin + if ((le_wr_en_39) == 1'b1) begin + REG_le_39 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_39) == 1'b0) begin + end else begin + REG_le_39 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_40x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_39))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_40 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==40); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_40 <= {16{1'b0}}; + end else begin + if ((le_wr_en_40) == 1'b1) begin + REG_le_40 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_40) == 1'b0) begin + end else begin + REG_le_40 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_41x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_40))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_41 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==41); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_41 <= {16{1'b0}}; + end else begin + if ((le_wr_en_41) == 1'b1) begin + REG_le_41 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_41) == 1'b0) begin + end else begin + REG_le_41 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_42x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_41))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_42 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==42); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_42 <= {16{1'b0}}; + end else begin + if ((le_wr_en_42) == 1'b1) begin + REG_le_42 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_42) == 1'b0) begin + end else begin + REG_le_42 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_43x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_42))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_43 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==43); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_43 <= {16{1'b0}}; + end else begin + if ((le_wr_en_43) == 1'b1) begin + REG_le_43 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_43) == 1'b0) begin + end else begin + REG_le_43 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_44x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_43))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_44 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==44); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_44 <= {16{1'b0}}; + end else begin + if ((le_wr_en_44) == 1'b1) begin + REG_le_44 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_44) == 1'b0) begin + end else begin + REG_le_44 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_45x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_44))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_45 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==45); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_45 <= {16{1'b0}}; + end else begin + if ((le_wr_en_45) == 1'b1) begin + REG_le_45 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_45) == 1'b0) begin + end else begin + REG_le_45 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_46x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_45))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_46 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==46); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_46 <= {16{1'b0}}; + end else begin + if ((le_wr_en_46) == 1'b1) begin + REG_le_46 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_46) == 1'b0) begin + end else begin + REG_le_46 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_47x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_46))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_47 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==47); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_47 <= {16{1'b0}}; + end else begin + if ((le_wr_en_47) == 1'b1) begin + REG_le_47 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_47) == 1'b0) begin + end else begin + REG_le_47 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_48x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_47))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_48 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==48); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_48 <= {16{1'b0}}; + end else begin + if ((le_wr_en_48) == 1'b1) begin + REG_le_48 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_48) == 1'b0) begin + end else begin + REG_le_48 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_49x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_48))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_49 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==49); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_49 <= {16{1'b0}}; + end else begin + if ((le_wr_en_49) == 1'b1) begin + REG_le_49 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_49) == 1'b0) begin + end else begin + REG_le_49 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_50x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_49))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_50 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==50); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_50 <= {16{1'b0}}; + end else begin + if ((le_wr_en_50) == 1'b1) begin + REG_le_50 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_50) == 1'b0) begin + end else begin + REG_le_50 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_51x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_50))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_51 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==51); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_51 <= {16{1'b0}}; + end else begin + if ((le_wr_en_51) == 1'b1) begin + REG_le_51 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_51) == 1'b0) begin + end else begin + REG_le_51 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_52x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_51))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_52 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==52); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_52 <= {16{1'b0}}; + end else begin + if ((le_wr_en_52) == 1'b1) begin + REG_le_52 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_52) == 1'b0) begin + end else begin + REG_le_52 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_53x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_52))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_53 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==53); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_53 <= {16{1'b0}}; + end else begin + if ((le_wr_en_53) == 1'b1) begin + REG_le_53 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_53) == 1'b0) begin + end else begin + REG_le_53 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_54x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_53))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_54 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==54); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_54 <= {16{1'b0}}; + end else begin + if ((le_wr_en_54) == 1'b1) begin + REG_le_54 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_54) == 1'b0) begin + end else begin + REG_le_54 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_55x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_54))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_55 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==55); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_55 <= {16{1'b0}}; + end else begin + if ((le_wr_en_55) == 1'b1) begin + REG_le_55 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_55) == 1'b0) begin + end else begin + REG_le_55 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_56x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_55))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_56 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==56); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_56 <= {16{1'b0}}; + end else begin + if ((le_wr_en_56) == 1'b1) begin + REG_le_56 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_56) == 1'b0) begin + end else begin + REG_le_56 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_57x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_56))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_57 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==57); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_57 <= {16{1'b0}}; + end else begin + if ((le_wr_en_57) == 1'b1) begin + REG_le_57 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_57) == 1'b0) begin + end else begin + REG_le_57 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_58x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_57))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_58 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==58); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_58 <= {16{1'b0}}; + end else begin + if ((le_wr_en_58) == 1'b1) begin + REG_le_58 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_58) == 1'b0) begin + end else begin + REG_le_58 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_59x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_58))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_59 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==59); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_59 <= {16{1'b0}}; + end else begin + if ((le_wr_en_59) == 1'b1) begin + REG_le_59 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_59) == 1'b0) begin + end else begin + REG_le_59 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_60x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_59))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_60 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==60); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_60 <= {16{1'b0}}; + end else begin + if ((le_wr_en_60) == 1'b1) begin + REG_le_60 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_60) == 1'b0) begin + end else begin + REG_le_60 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_61x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_60))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_61 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==61); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_61 <= {16{1'b0}}; + end else begin + if ((le_wr_en_61) == 1'b1) begin + REG_le_61 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_61) == 1'b0) begin + end else begin + REG_le_61 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_62x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_61))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_62 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==62); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_62 <= {16{1'b0}}; + end else begin + if ((le_wr_en_62) == 1'b1) begin + REG_le_62 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_62) == 1'b0) begin + end else begin + REG_le_62 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_63x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_62))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_63 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==63); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_63 <= {16{1'b0}}; + end else begin + if ((le_wr_en_63) == 1'b1) begin + REG_le_63 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_63) == 1'b0) begin + end else begin + REG_le_63 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_64x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_63))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign le_wr_en_64 = pro_in_wr_en & pro_in_select_le & (pro_in_addr==64); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_le_64 <= {16{1'b0}}; + end else begin + if ((le_wr_en_64) == 1'b1) begin + REG_le_64 <= pro_in_data; +// VCS coverage off + end else if ((le_wr_en_64) == 1'b0) begin + end else begin + REG_le_64 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_65x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(le_wr_en_64))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign REG_le_65 = {16{`tick_x_or_0}}; +assign REG_le_66 = {16{`tick_x_or_0}}; +assign REG_le_67 = {16{`tick_x_or_0}}; +assign REG_le_68 = {16{`tick_x_or_0}}; +assign REG_le_69 = {16{`tick_x_or_0}}; +assign REG_le_70 = {16{`tick_x_or_0}}; +assign REG_le_71 = {16{`tick_x_or_0}}; +assign REG_le_72 = {16{`tick_x_or_0}}; +assign REG_le_73 = {16{`tick_x_or_0}}; +assign REG_le_74 = {16{`tick_x_or_0}}; +assign REG_le_75 = {16{`tick_x_or_0}}; +assign REG_le_76 = {16{`tick_x_or_0}}; +assign REG_le_77 = {16{`tick_x_or_0}}; +assign REG_le_78 = {16{`tick_x_or_0}}; +assign REG_le_79 = {16{`tick_x_or_0}}; +assign REG_le_80 = {16{`tick_x_or_0}}; +assign REG_le_81 = {16{`tick_x_or_0}}; +assign REG_le_82 = {16{`tick_x_or_0}}; +assign REG_le_83 = {16{`tick_x_or_0}}; +assign REG_le_84 = {16{`tick_x_or_0}}; +assign REG_le_85 = {16{`tick_x_or_0}}; +assign REG_le_86 = {16{`tick_x_or_0}}; +assign REG_le_87 = {16{`tick_x_or_0}}; +assign REG_le_88 = {16{`tick_x_or_0}}; +assign REG_le_89 = {16{`tick_x_or_0}}; +assign REG_le_90 = {16{`tick_x_or_0}}; +assign REG_le_91 = {16{`tick_x_or_0}}; +assign REG_le_92 = {16{`tick_x_or_0}}; +assign REG_le_93 = {16{`tick_x_or_0}}; +assign REG_le_94 = {16{`tick_x_or_0}}; +assign REG_le_95 = {16{`tick_x_or_0}}; +assign REG_le_96 = {16{`tick_x_or_0}}; +assign REG_le_97 = {16{`tick_x_or_0}}; +assign REG_le_98 = {16{`tick_x_or_0}}; +assign REG_le_99 = {16{`tick_x_or_0}}; +assign REG_le_100 = {16{`tick_x_or_0}}; +assign REG_le_101 = {16{`tick_x_or_0}}; +assign REG_le_102 = {16{`tick_x_or_0}}; +assign REG_le_103 = {16{`tick_x_or_0}}; +assign REG_le_104 = {16{`tick_x_or_0}}; +assign REG_le_105 = {16{`tick_x_or_0}}; +assign REG_le_106 = {16{`tick_x_or_0}}; +assign REG_le_107 = {16{`tick_x_or_0}}; +assign REG_le_108 = {16{`tick_x_or_0}}; +assign REG_le_109 = {16{`tick_x_or_0}}; +assign REG_le_110 = {16{`tick_x_or_0}}; +assign REG_le_111 = {16{`tick_x_or_0}}; +assign REG_le_112 = {16{`tick_x_or_0}}; +assign REG_le_113 = {16{`tick_x_or_0}}; +assign REG_le_114 = {16{`tick_x_or_0}}; +assign REG_le_115 = {16{`tick_x_or_0}}; +assign REG_le_116 = {16{`tick_x_or_0}}; +assign REG_le_117 = {16{`tick_x_or_0}}; +assign REG_le_118 = {16{`tick_x_or_0}}; +assign REG_le_119 = {16{`tick_x_or_0}}; +assign REG_le_120 = {16{`tick_x_or_0}}; +assign REG_le_121 = {16{`tick_x_or_0}}; +assign REG_le_122 = {16{`tick_x_or_0}}; +assign REG_le_123 = {16{`tick_x_or_0}}; +assign REG_le_124 = {16{`tick_x_or_0}}; +assign REG_le_125 = {16{`tick_x_or_0}}; +assign REG_le_126 = {16{`tick_x_or_0}}; +assign REG_le_127 = {16{`tick_x_or_0}}; +assign REG_le_128 = {16{`tick_x_or_0}}; +assign REG_le_129 = {16{`tick_x_or_0}}; +assign REG_le_130 = {16{`tick_x_or_0}}; +assign REG_le_131 = {16{`tick_x_or_0}}; +assign REG_le_132 = {16{`tick_x_or_0}}; +assign REG_le_133 = {16{`tick_x_or_0}}; +assign REG_le_134 = {16{`tick_x_or_0}}; +assign REG_le_135 = {16{`tick_x_or_0}}; +assign REG_le_136 = {16{`tick_x_or_0}}; +assign REG_le_137 = {16{`tick_x_or_0}}; +assign REG_le_138 = {16{`tick_x_or_0}}; +assign REG_le_139 = {16{`tick_x_or_0}}; +assign REG_le_140 = {16{`tick_x_or_0}}; +assign REG_le_141 = {16{`tick_x_or_0}}; +assign REG_le_142 = {16{`tick_x_or_0}}; +assign REG_le_143 = {16{`tick_x_or_0}}; +assign REG_le_144 = {16{`tick_x_or_0}}; +assign REG_le_145 = {16{`tick_x_or_0}}; +assign REG_le_146 = {16{`tick_x_or_0}}; +assign REG_le_147 = {16{`tick_x_or_0}}; +assign REG_le_148 = {16{`tick_x_or_0}}; +assign REG_le_149 = {16{`tick_x_or_0}}; +assign REG_le_150 = {16{`tick_x_or_0}}; +assign REG_le_151 = {16{`tick_x_or_0}}; +assign REG_le_152 = {16{`tick_x_or_0}}; +assign REG_le_153 = {16{`tick_x_or_0}}; +assign REG_le_154 = {16{`tick_x_or_0}}; +assign REG_le_155 = {16{`tick_x_or_0}}; +assign REG_le_156 = {16{`tick_x_or_0}}; +assign REG_le_157 = {16{`tick_x_or_0}}; +assign REG_le_158 = {16{`tick_x_or_0}}; +assign REG_le_159 = {16{`tick_x_or_0}}; +assign REG_le_160 = {16{`tick_x_or_0}}; +assign REG_le_161 = {16{`tick_x_or_0}}; +assign REG_le_162 = {16{`tick_x_or_0}}; +assign REG_le_163 = {16{`tick_x_or_0}}; +assign REG_le_164 = {16{`tick_x_or_0}}; +assign REG_le_165 = {16{`tick_x_or_0}}; +assign REG_le_166 = {16{`tick_x_or_0}}; +assign REG_le_167 = {16{`tick_x_or_0}}; +assign REG_le_168 = {16{`tick_x_or_0}}; +assign REG_le_169 = {16{`tick_x_or_0}}; +assign REG_le_170 = {16{`tick_x_or_0}}; +assign REG_le_171 = {16{`tick_x_or_0}}; +assign REG_le_172 = {16{`tick_x_or_0}}; +assign REG_le_173 = {16{`tick_x_or_0}}; +assign REG_le_174 = {16{`tick_x_or_0}}; +assign REG_le_175 = {16{`tick_x_or_0}}; +assign REG_le_176 = {16{`tick_x_or_0}}; +assign REG_le_177 = {16{`tick_x_or_0}}; +assign REG_le_178 = {16{`tick_x_or_0}}; +assign REG_le_179 = {16{`tick_x_or_0}}; +assign REG_le_180 = {16{`tick_x_or_0}}; +assign REG_le_181 = {16{`tick_x_or_0}}; +assign REG_le_182 = {16{`tick_x_or_0}}; +assign REG_le_183 = {16{`tick_x_or_0}}; +assign REG_le_184 = {16{`tick_x_or_0}}; +assign REG_le_185 = {16{`tick_x_or_0}}; +assign REG_le_186 = {16{`tick_x_or_0}}; +assign REG_le_187 = {16{`tick_x_or_0}}; +assign REG_le_188 = {16{`tick_x_or_0}}; +assign REG_le_189 = {16{`tick_x_or_0}}; +assign REG_le_190 = {16{`tick_x_or_0}}; +assign REG_le_191 = {16{`tick_x_or_0}}; +assign REG_le_192 = {16{`tick_x_or_0}}; +assign REG_le_193 = {16{`tick_x_or_0}}; +assign REG_le_194 = {16{`tick_x_or_0}}; +assign REG_le_195 = {16{`tick_x_or_0}}; +assign REG_le_196 = {16{`tick_x_or_0}}; +assign REG_le_197 = {16{`tick_x_or_0}}; +assign REG_le_198 = {16{`tick_x_or_0}}; +assign REG_le_199 = {16{`tick_x_or_0}}; +assign REG_le_200 = {16{`tick_x_or_0}}; +assign REG_le_201 = {16{`tick_x_or_0}}; +assign REG_le_202 = {16{`tick_x_or_0}}; +assign REG_le_203 = {16{`tick_x_or_0}}; +assign REG_le_204 = {16{`tick_x_or_0}}; +assign REG_le_205 = {16{`tick_x_or_0}}; +assign REG_le_206 = {16{`tick_x_or_0}}; +assign REG_le_207 = {16{`tick_x_or_0}}; +assign REG_le_208 = {16{`tick_x_or_0}}; +assign REG_le_209 = {16{`tick_x_or_0}}; +assign REG_le_210 = {16{`tick_x_or_0}}; +assign REG_le_211 = {16{`tick_x_or_0}}; +assign REG_le_212 = {16{`tick_x_or_0}}; +assign REG_le_213 = {16{`tick_x_or_0}}; +assign REG_le_214 = {16{`tick_x_or_0}}; +assign REG_le_215 = {16{`tick_x_or_0}}; +assign REG_le_216 = {16{`tick_x_or_0}}; +assign REG_le_217 = {16{`tick_x_or_0}}; +assign REG_le_218 = {16{`tick_x_or_0}}; +assign REG_le_219 = {16{`tick_x_or_0}}; +assign REG_le_220 = {16{`tick_x_or_0}}; +assign REG_le_221 = {16{`tick_x_or_0}}; +assign REG_le_222 = {16{`tick_x_or_0}}; +assign REG_le_223 = {16{`tick_x_or_0}}; +assign REG_le_224 = {16{`tick_x_or_0}}; +assign REG_le_225 = {16{`tick_x_or_0}}; +assign REG_le_226 = {16{`tick_x_or_0}}; +assign REG_le_227 = {16{`tick_x_or_0}}; +assign REG_le_228 = {16{`tick_x_or_0}}; +assign REG_le_229 = {16{`tick_x_or_0}}; +assign REG_le_230 = {16{`tick_x_or_0}}; +assign REG_le_231 = {16{`tick_x_or_0}}; +assign REG_le_232 = {16{`tick_x_or_0}}; +assign REG_le_233 = {16{`tick_x_or_0}}; +assign REG_le_234 = {16{`tick_x_or_0}}; +assign REG_le_235 = {16{`tick_x_or_0}}; +assign REG_le_236 = {16{`tick_x_or_0}}; +assign REG_le_237 = {16{`tick_x_or_0}}; +assign REG_le_238 = {16{`tick_x_or_0}}; +assign REG_le_239 = {16{`tick_x_or_0}}; +assign REG_le_240 = {16{`tick_x_or_0}}; +assign REG_le_241 = {16{`tick_x_or_0}}; +assign REG_le_242 = {16{`tick_x_or_0}}; +assign REG_le_243 = {16{`tick_x_or_0}}; +assign REG_le_244 = {16{`tick_x_or_0}}; +assign REG_le_245 = {16{`tick_x_or_0}}; +assign REG_le_246 = {16{`tick_x_or_0}}; +assign REG_le_247 = {16{`tick_x_or_0}}; +assign REG_le_248 = {16{`tick_x_or_0}}; +assign REG_le_249 = {16{`tick_x_or_0}}; +assign REG_le_250 = {16{`tick_x_or_0}}; +assign REG_le_251 = {16{`tick_x_or_0}}; +assign REG_le_252 = {16{`tick_x_or_0}}; +assign REG_le_253 = {16{`tick_x_or_0}}; +assign REG_le_254 = {16{`tick_x_or_0}}; +assign REG_le_255 = {16{`tick_x_or_0}}; +assign REG_le_256 = {16{`tick_x_or_0}}; +assign lo_wr_en_0 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_0 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_0) == 1'b1) begin + REG_lo_0 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_0) == 1'b0) begin + end else begin + REG_lo_0 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_66x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_0))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_1 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_1 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_1) == 1'b1) begin + REG_lo_1 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_1) == 1'b0) begin + end else begin + REG_lo_1 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_67x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_1))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_2 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==2); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_2 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_2) == 1'b1) begin + REG_lo_2 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_2) == 1'b0) begin + end else begin + REG_lo_2 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_68x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_2))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_3 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==3); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_3 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_3) == 1'b1) begin + REG_lo_3 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_3) == 1'b0) begin + end else begin + REG_lo_3 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_69x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_3))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_4 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==4); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_4 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_4) == 1'b1) begin + REG_lo_4 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_4) == 1'b0) begin + end else begin + REG_lo_4 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_70x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_4))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_5 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==5); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_5 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_5) == 1'b1) begin + REG_lo_5 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_5) == 1'b0) begin + end else begin + REG_lo_5 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_71x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_5))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_6 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==6); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_6 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_6) == 1'b1) begin + REG_lo_6 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_6) == 1'b0) begin + end else begin + REG_lo_6 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_72x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_6))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_7 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==7); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_7 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_7) == 1'b1) begin + REG_lo_7 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_7) == 1'b0) begin + end else begin + REG_lo_7 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_73x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_7))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_8 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==8); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_8 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_8) == 1'b1) begin + REG_lo_8 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_8) == 1'b0) begin + end else begin + REG_lo_8 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_74x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_8))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_9 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==9); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_9 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_9) == 1'b1) begin + REG_lo_9 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_9) == 1'b0) begin + end else begin + REG_lo_9 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_75x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_9))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_10 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==10); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_10 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_10) == 1'b1) begin + REG_lo_10 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_10) == 1'b0) begin + end else begin + REG_lo_10 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_76x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_10))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_11 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==11); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_11 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_11) == 1'b1) begin + REG_lo_11 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_11) == 1'b0) begin + end else begin + REG_lo_11 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_77x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_11))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_12 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==12); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_12 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_12) == 1'b1) begin + REG_lo_12 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_12) == 1'b0) begin + end else begin + REG_lo_12 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_78x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_12))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_13 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==13); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_13 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_13) == 1'b1) begin + REG_lo_13 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_13) == 1'b0) begin + end else begin + REG_lo_13 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_79x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_13))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_14 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==14); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_14 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_14) == 1'b1) begin + REG_lo_14 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_14) == 1'b0) begin + end else begin + REG_lo_14 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_80x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_14))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_15 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==15); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_15 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_15) == 1'b1) begin + REG_lo_15 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_15) == 1'b0) begin + end else begin + REG_lo_15 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_81x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_15))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_16 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==16); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_16 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_16) == 1'b1) begin + REG_lo_16 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_16) == 1'b0) begin + end else begin + REG_lo_16 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_82x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_16))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_17 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==17); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_17 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_17) == 1'b1) begin + REG_lo_17 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_17) == 1'b0) begin + end else begin + REG_lo_17 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_83x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_17))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_18 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==18); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_18 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_18) == 1'b1) begin + REG_lo_18 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_18) == 1'b0) begin + end else begin + REG_lo_18 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_84x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_18))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_19 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==19); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_19 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_19) == 1'b1) begin + REG_lo_19 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_19) == 1'b0) begin + end else begin + REG_lo_19 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_85x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_19))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_20 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==20); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_20 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_20) == 1'b1) begin + REG_lo_20 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_20) == 1'b0) begin + end else begin + REG_lo_20 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_86x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_20))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_21 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==21); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_21 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_21) == 1'b1) begin + REG_lo_21 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_21) == 1'b0) begin + end else begin + REG_lo_21 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_87x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_21))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_22 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==22); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_22 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_22) == 1'b1) begin + REG_lo_22 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_22) == 1'b0) begin + end else begin + REG_lo_22 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_88x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_22))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_23 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==23); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_23 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_23) == 1'b1) begin + REG_lo_23 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_23) == 1'b0) begin + end else begin + REG_lo_23 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_89x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_23))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_24 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==24); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_24 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_24) == 1'b1) begin + REG_lo_24 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_24) == 1'b0) begin + end else begin + REG_lo_24 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_90x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_24))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_25 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==25); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_25 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_25) == 1'b1) begin + REG_lo_25 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_25) == 1'b0) begin + end else begin + REG_lo_25 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_91x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_25))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_26 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==26); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_26 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_26) == 1'b1) begin + REG_lo_26 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_26) == 1'b0) begin + end else begin + REG_lo_26 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_92x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_26))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_27 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==27); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_27 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_27) == 1'b1) begin + REG_lo_27 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_27) == 1'b0) begin + end else begin + REG_lo_27 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_93x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_27))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_28 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==28); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_28 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_28) == 1'b1) begin + REG_lo_28 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_28) == 1'b0) begin + end else begin + REG_lo_28 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_94x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_28))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_29 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==29); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_29 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_29) == 1'b1) begin + REG_lo_29 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_29) == 1'b0) begin + end else begin + REG_lo_29 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_95x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_29))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_30 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==30); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_30 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_30) == 1'b1) begin + REG_lo_30 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_30) == 1'b0) begin + end else begin + REG_lo_30 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_96x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_30))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_31 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==31); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_31 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_31) == 1'b1) begin + REG_lo_31 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_31) == 1'b0) begin + end else begin + REG_lo_31 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_97x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_31))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_32 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==32); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_32 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_32) == 1'b1) begin + REG_lo_32 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_32) == 1'b0) begin + end else begin + REG_lo_32 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_98x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_32))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_33 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==33); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_33 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_33) == 1'b1) begin + REG_lo_33 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_33) == 1'b0) begin + end else begin + REG_lo_33 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_99x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_33))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_34 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==34); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_34 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_34) == 1'b1) begin + REG_lo_34 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_34) == 1'b0) begin + end else begin + REG_lo_34 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_100x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_34))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_35 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==35); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_35 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_35) == 1'b1) begin + REG_lo_35 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_35) == 1'b0) begin + end else begin + REG_lo_35 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_101x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_35))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_36 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==36); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_36 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_36) == 1'b1) begin + REG_lo_36 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_36) == 1'b0) begin + end else begin + REG_lo_36 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_102x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_36))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_37 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==37); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_37 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_37) == 1'b1) begin + REG_lo_37 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_37) == 1'b0) begin + end else begin + REG_lo_37 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_103x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_37))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_38 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==38); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_38 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_38) == 1'b1) begin + REG_lo_38 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_38) == 1'b0) begin + end else begin + REG_lo_38 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_104x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_38))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_39 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==39); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_39 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_39) == 1'b1) begin + REG_lo_39 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_39) == 1'b0) begin + end else begin + REG_lo_39 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_105x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_39))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_40 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==40); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_40 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_40) == 1'b1) begin + REG_lo_40 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_40) == 1'b0) begin + end else begin + REG_lo_40 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_106x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_40))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_41 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==41); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_41 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_41) == 1'b1) begin + REG_lo_41 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_41) == 1'b0) begin + end else begin + REG_lo_41 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_107x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_41))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_42 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==42); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_42 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_42) == 1'b1) begin + REG_lo_42 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_42) == 1'b0) begin + end else begin + REG_lo_42 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_108x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_42))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_43 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==43); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_43 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_43) == 1'b1) begin + REG_lo_43 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_43) == 1'b0) begin + end else begin + REG_lo_43 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_109x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_43))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_44 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==44); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_44 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_44) == 1'b1) begin + REG_lo_44 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_44) == 1'b0) begin + end else begin + REG_lo_44 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_110x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_44))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_45 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==45); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_45 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_45) == 1'b1) begin + REG_lo_45 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_45) == 1'b0) begin + end else begin + REG_lo_45 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_111x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_45))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_46 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==46); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_46 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_46) == 1'b1) begin + REG_lo_46 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_46) == 1'b0) begin + end else begin + REG_lo_46 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_112x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_46))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_47 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==47); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_47 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_47) == 1'b1) begin + REG_lo_47 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_47) == 1'b0) begin + end else begin + REG_lo_47 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_113x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_47))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_48 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==48); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_48 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_48) == 1'b1) begin + REG_lo_48 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_48) == 1'b0) begin + end else begin + REG_lo_48 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_114x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_48))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_49 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==49); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_49 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_49) == 1'b1) begin + REG_lo_49 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_49) == 1'b0) begin + end else begin + REG_lo_49 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_115x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_49))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_50 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==50); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_50 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_50) == 1'b1) begin + REG_lo_50 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_50) == 1'b0) begin + end else begin + REG_lo_50 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_116x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_50))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_51 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==51); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_51 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_51) == 1'b1) begin + REG_lo_51 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_51) == 1'b0) begin + end else begin + REG_lo_51 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_117x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_51))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_52 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==52); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_52 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_52) == 1'b1) begin + REG_lo_52 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_52) == 1'b0) begin + end else begin + REG_lo_52 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_118x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_52))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_53 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==53); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_53 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_53) == 1'b1) begin + REG_lo_53 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_53) == 1'b0) begin + end else begin + REG_lo_53 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_119x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_53))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_54 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==54); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_54 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_54) == 1'b1) begin + REG_lo_54 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_54) == 1'b0) begin + end else begin + REG_lo_54 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_120x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_54))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_55 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==55); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_55 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_55) == 1'b1) begin + REG_lo_55 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_55) == 1'b0) begin + end else begin + REG_lo_55 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_121x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_55))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_56 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==56); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_56 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_56) == 1'b1) begin + REG_lo_56 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_56) == 1'b0) begin + end else begin + REG_lo_56 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_122x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_56))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_57 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==57); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_57 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_57) == 1'b1) begin + REG_lo_57 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_57) == 1'b0) begin + end else begin + REG_lo_57 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_123x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_57))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_58 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==58); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_58 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_58) == 1'b1) begin + REG_lo_58 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_58) == 1'b0) begin + end else begin + REG_lo_58 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_124x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_58))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_59 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==59); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_59 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_59) == 1'b1) begin + REG_lo_59 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_59) == 1'b0) begin + end else begin + REG_lo_59 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_125x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_59))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_60 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==60); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_60 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_60) == 1'b1) begin + REG_lo_60 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_60) == 1'b0) begin + end else begin + REG_lo_60 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_126x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_60))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_61 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==61); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_61 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_61) == 1'b1) begin + REG_lo_61 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_61) == 1'b0) begin + end else begin + REG_lo_61 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_127x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_61))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_62 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==62); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_62 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_62) == 1'b1) begin + REG_lo_62 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_62) == 1'b0) begin + end else begin + REG_lo_62 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_128x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_62))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_63 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==63); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_63 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_63) == 1'b1) begin + REG_lo_63 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_63) == 1'b0) begin + end else begin + REG_lo_63 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_129x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_63))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_64 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==64); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_64 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_64) == 1'b1) begin + REG_lo_64 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_64) == 1'b0) begin + end else begin + REG_lo_64 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_130x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_64))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_65 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==65); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_65 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_65) == 1'b1) begin + REG_lo_65 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_65) == 1'b0) begin + end else begin + REG_lo_65 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_131x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_65))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_66 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==66); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_66 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_66) == 1'b1) begin + REG_lo_66 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_66) == 1'b0) begin + end else begin + REG_lo_66 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_132x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_66))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_67 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==67); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_67 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_67) == 1'b1) begin + REG_lo_67 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_67) == 1'b0) begin + end else begin + REG_lo_67 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_133x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_67))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_68 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==68); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_68 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_68) == 1'b1) begin + REG_lo_68 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_68) == 1'b0) begin + end else begin + REG_lo_68 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_134x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_68))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_69 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==69); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_69 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_69) == 1'b1) begin + REG_lo_69 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_69) == 1'b0) begin + end else begin + REG_lo_69 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_135x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_69))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_70 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==70); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_70 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_70) == 1'b1) begin + REG_lo_70 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_70) == 1'b0) begin + end else begin + REG_lo_70 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_136x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_70))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_71 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==71); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_71 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_71) == 1'b1) begin + REG_lo_71 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_71) == 1'b0) begin + end else begin + REG_lo_71 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_137x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_71))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_72 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==72); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_72 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_72) == 1'b1) begin + REG_lo_72 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_72) == 1'b0) begin + end else begin + REG_lo_72 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_138x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_72))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_73 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==73); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_73 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_73) == 1'b1) begin + REG_lo_73 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_73) == 1'b0) begin + end else begin + REG_lo_73 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_139x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_73))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_74 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==74); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_74 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_74) == 1'b1) begin + REG_lo_74 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_74) == 1'b0) begin + end else begin + REG_lo_74 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_140x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_74))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_75 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==75); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_75 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_75) == 1'b1) begin + REG_lo_75 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_75) == 1'b0) begin + end else begin + REG_lo_75 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_141x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_75))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_76 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==76); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_76 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_76) == 1'b1) begin + REG_lo_76 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_76) == 1'b0) begin + end else begin + REG_lo_76 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_142x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_76))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_77 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==77); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_77 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_77) == 1'b1) begin + REG_lo_77 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_77) == 1'b0) begin + end else begin + REG_lo_77 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_143x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_77))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_78 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==78); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_78 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_78) == 1'b1) begin + REG_lo_78 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_78) == 1'b0) begin + end else begin + REG_lo_78 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_144x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_78))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_79 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==79); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_79 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_79) == 1'b1) begin + REG_lo_79 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_79) == 1'b0) begin + end else begin + REG_lo_79 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_145x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_79))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_80 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==80); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_80 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_80) == 1'b1) begin + REG_lo_80 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_80) == 1'b0) begin + end else begin + REG_lo_80 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_146x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_80))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_81 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==81); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_81 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_81) == 1'b1) begin + REG_lo_81 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_81) == 1'b0) begin + end else begin + REG_lo_81 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_147x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_81))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_82 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==82); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_82 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_82) == 1'b1) begin + REG_lo_82 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_82) == 1'b0) begin + end else begin + REG_lo_82 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_148x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_82))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_83 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==83); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_83 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_83) == 1'b1) begin + REG_lo_83 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_83) == 1'b0) begin + end else begin + REG_lo_83 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_149x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_83))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_84 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==84); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_84 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_84) == 1'b1) begin + REG_lo_84 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_84) == 1'b0) begin + end else begin + REG_lo_84 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_150x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_84))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_85 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==85); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_85 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_85) == 1'b1) begin + REG_lo_85 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_85) == 1'b0) begin + end else begin + REG_lo_85 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_151x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_85))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_86 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==86); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_86 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_86) == 1'b1) begin + REG_lo_86 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_86) == 1'b0) begin + end else begin + REG_lo_86 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_152x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_86))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_87 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==87); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_87 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_87) == 1'b1) begin + REG_lo_87 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_87) == 1'b0) begin + end else begin + REG_lo_87 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_153x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_87))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_88 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==88); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_88 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_88) == 1'b1) begin + REG_lo_88 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_88) == 1'b0) begin + end else begin + REG_lo_88 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_154x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_88))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_89 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==89); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_89 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_89) == 1'b1) begin + REG_lo_89 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_89) == 1'b0) begin + end else begin + REG_lo_89 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_155x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_89))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_90 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==90); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_90 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_90) == 1'b1) begin + REG_lo_90 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_90) == 1'b0) begin + end else begin + REG_lo_90 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_156x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_90))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_91 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==91); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_91 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_91) == 1'b1) begin + REG_lo_91 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_91) == 1'b0) begin + end else begin + REG_lo_91 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_157x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_91))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_92 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==92); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_92 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_92) == 1'b1) begin + REG_lo_92 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_92) == 1'b0) begin + end else begin + REG_lo_92 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_158x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_92))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_93 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==93); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_93 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_93) == 1'b1) begin + REG_lo_93 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_93) == 1'b0) begin + end else begin + REG_lo_93 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_159x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_93))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_94 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==94); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_94 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_94) == 1'b1) begin + REG_lo_94 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_94) == 1'b0) begin + end else begin + REG_lo_94 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_160x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_94))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_95 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==95); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_95 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_95) == 1'b1) begin + REG_lo_95 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_95) == 1'b0) begin + end else begin + REG_lo_95 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_161x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_95))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_96 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==96); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_96 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_96) == 1'b1) begin + REG_lo_96 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_96) == 1'b0) begin + end else begin + REG_lo_96 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_162x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_96))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_97 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==97); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_97 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_97) == 1'b1) begin + REG_lo_97 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_97) == 1'b0) begin + end else begin + REG_lo_97 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_163x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_97))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_98 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==98); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_98 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_98) == 1'b1) begin + REG_lo_98 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_98) == 1'b0) begin + end else begin + REG_lo_98 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_164x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_98))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_99 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==99); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_99 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_99) == 1'b1) begin + REG_lo_99 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_99) == 1'b0) begin + end else begin + REG_lo_99 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_165x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_99))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_100 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==100); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_100 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_100) == 1'b1) begin + REG_lo_100 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_100) == 1'b0) begin + end else begin + REG_lo_100 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_166x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_100))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_101 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==101); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_101 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_101) == 1'b1) begin + REG_lo_101 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_101) == 1'b0) begin + end else begin + REG_lo_101 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_167x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_101))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_102 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==102); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_102 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_102) == 1'b1) begin + REG_lo_102 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_102) == 1'b0) begin + end else begin + REG_lo_102 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_168x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_102))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_103 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==103); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_103 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_103) == 1'b1) begin + REG_lo_103 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_103) == 1'b0) begin + end else begin + REG_lo_103 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_169x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_103))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_104 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==104); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_104 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_104) == 1'b1) begin + REG_lo_104 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_104) == 1'b0) begin + end else begin + REG_lo_104 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_170x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_104))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_105 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==105); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_105 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_105) == 1'b1) begin + REG_lo_105 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_105) == 1'b0) begin + end else begin + REG_lo_105 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_171x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_105))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_106 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==106); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_106 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_106) == 1'b1) begin + REG_lo_106 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_106) == 1'b0) begin + end else begin + REG_lo_106 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_172x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_106))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_107 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==107); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_107 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_107) == 1'b1) begin + REG_lo_107 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_107) == 1'b0) begin + end else begin + REG_lo_107 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_173x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_107))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_108 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==108); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_108 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_108) == 1'b1) begin + REG_lo_108 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_108) == 1'b0) begin + end else begin + REG_lo_108 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_174x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_108))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_109 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==109); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_109 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_109) == 1'b1) begin + REG_lo_109 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_109) == 1'b0) begin + end else begin + REG_lo_109 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_175x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_109))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_110 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==110); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_110 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_110) == 1'b1) begin + REG_lo_110 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_110) == 1'b0) begin + end else begin + REG_lo_110 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_176x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_110))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_111 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==111); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_111 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_111) == 1'b1) begin + REG_lo_111 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_111) == 1'b0) begin + end else begin + REG_lo_111 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_177x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_111))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_112 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==112); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_112 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_112) == 1'b1) begin + REG_lo_112 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_112) == 1'b0) begin + end else begin + REG_lo_112 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_178x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_112))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_113 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==113); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_113 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_113) == 1'b1) begin + REG_lo_113 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_113) == 1'b0) begin + end else begin + REG_lo_113 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_179x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_113))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_114 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==114); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_114 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_114) == 1'b1) begin + REG_lo_114 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_114) == 1'b0) begin + end else begin + REG_lo_114 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_180x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_114))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_115 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==115); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_115 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_115) == 1'b1) begin + REG_lo_115 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_115) == 1'b0) begin + end else begin + REG_lo_115 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_181x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_115))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_116 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==116); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_116 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_116) == 1'b1) begin + REG_lo_116 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_116) == 1'b0) begin + end else begin + REG_lo_116 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_182x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_116))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_117 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==117); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_117 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_117) == 1'b1) begin + REG_lo_117 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_117) == 1'b0) begin + end else begin + REG_lo_117 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_183x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_117))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_118 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==118); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_118 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_118) == 1'b1) begin + REG_lo_118 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_118) == 1'b0) begin + end else begin + REG_lo_118 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_184x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_118))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_119 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==119); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_119 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_119) == 1'b1) begin + REG_lo_119 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_119) == 1'b0) begin + end else begin + REG_lo_119 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_185x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_119))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_120 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==120); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_120 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_120) == 1'b1) begin + REG_lo_120 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_120) == 1'b0) begin + end else begin + REG_lo_120 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_186x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_120))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_121 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==121); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_121 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_121) == 1'b1) begin + REG_lo_121 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_121) == 1'b0) begin + end else begin + REG_lo_121 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_187x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_121))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_122 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==122); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_122 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_122) == 1'b1) begin + REG_lo_122 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_122) == 1'b0) begin + end else begin + REG_lo_122 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_188x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_122))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_123 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==123); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_123 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_123) == 1'b1) begin + REG_lo_123 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_123) == 1'b0) begin + end else begin + REG_lo_123 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_189x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_123))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_124 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==124); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_124 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_124) == 1'b1) begin + REG_lo_124 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_124) == 1'b0) begin + end else begin + REG_lo_124 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_190x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_124))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_125 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==125); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_125 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_125) == 1'b1) begin + REG_lo_125 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_125) == 1'b0) begin + end else begin + REG_lo_125 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_191x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_125))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_126 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==126); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_126 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_126) == 1'b1) begin + REG_lo_126 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_126) == 1'b0) begin + end else begin + REG_lo_126 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_192x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_126))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_127 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==127); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_127 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_127) == 1'b1) begin + REG_lo_127 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_127) == 1'b0) begin + end else begin + REG_lo_127 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_193x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_127))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_128 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==128); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_128 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_128) == 1'b1) begin + REG_lo_128 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_128) == 1'b0) begin + end else begin + REG_lo_128 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_194x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_128))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_129 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==129); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_129 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_129) == 1'b1) begin + REG_lo_129 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_129) == 1'b0) begin + end else begin + REG_lo_129 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_195x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_129))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_130 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==130); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_130 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_130) == 1'b1) begin + REG_lo_130 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_130) == 1'b0) begin + end else begin + REG_lo_130 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_196x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_130))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_131 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==131); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_131 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_131) == 1'b1) begin + REG_lo_131 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_131) == 1'b0) begin + end else begin + REG_lo_131 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_197x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_131))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_132 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==132); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_132 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_132) == 1'b1) begin + REG_lo_132 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_132) == 1'b0) begin + end else begin + REG_lo_132 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_198x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_132))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_133 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==133); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_133 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_133) == 1'b1) begin + REG_lo_133 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_133) == 1'b0) begin + end else begin + REG_lo_133 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_199x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_133))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_134 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==134); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_134 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_134) == 1'b1) begin + REG_lo_134 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_134) == 1'b0) begin + end else begin + REG_lo_134 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_200x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_134))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_135 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==135); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_135 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_135) == 1'b1) begin + REG_lo_135 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_135) == 1'b0) begin + end else begin + REG_lo_135 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_201x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_135))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_136 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==136); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_136 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_136) == 1'b1) begin + REG_lo_136 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_136) == 1'b0) begin + end else begin + REG_lo_136 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_202x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_136))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_137 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==137); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_137 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_137) == 1'b1) begin + REG_lo_137 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_137) == 1'b0) begin + end else begin + REG_lo_137 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_203x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_137))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_138 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==138); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_138 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_138) == 1'b1) begin + REG_lo_138 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_138) == 1'b0) begin + end else begin + REG_lo_138 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_204x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_138))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_139 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==139); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_139 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_139) == 1'b1) begin + REG_lo_139 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_139) == 1'b0) begin + end else begin + REG_lo_139 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_205x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_139))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_140 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==140); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_140 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_140) == 1'b1) begin + REG_lo_140 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_140) == 1'b0) begin + end else begin + REG_lo_140 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_206x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_140))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_141 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==141); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_141 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_141) == 1'b1) begin + REG_lo_141 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_141) == 1'b0) begin + end else begin + REG_lo_141 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_207x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_141))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_142 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==142); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_142 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_142) == 1'b1) begin + REG_lo_142 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_142) == 1'b0) begin + end else begin + REG_lo_142 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_208x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_142))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_143 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==143); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_143 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_143) == 1'b1) begin + REG_lo_143 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_143) == 1'b0) begin + end else begin + REG_lo_143 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_209x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_143))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_144 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==144); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_144 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_144) == 1'b1) begin + REG_lo_144 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_144) == 1'b0) begin + end else begin + REG_lo_144 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_210x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_144))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_145 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==145); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_145 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_145) == 1'b1) begin + REG_lo_145 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_145) == 1'b0) begin + end else begin + REG_lo_145 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_211x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_145))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_146 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==146); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_146 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_146) == 1'b1) begin + REG_lo_146 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_146) == 1'b0) begin + end else begin + REG_lo_146 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_212x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_146))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_147 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==147); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_147 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_147) == 1'b1) begin + REG_lo_147 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_147) == 1'b0) begin + end else begin + REG_lo_147 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_213x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_147))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_148 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==148); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_148 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_148) == 1'b1) begin + REG_lo_148 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_148) == 1'b0) begin + end else begin + REG_lo_148 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_214x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_148))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_149 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==149); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_149 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_149) == 1'b1) begin + REG_lo_149 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_149) == 1'b0) begin + end else begin + REG_lo_149 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_215x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_149))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_150 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==150); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_150 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_150) == 1'b1) begin + REG_lo_150 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_150) == 1'b0) begin + end else begin + REG_lo_150 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_216x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_150))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_151 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==151); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_151 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_151) == 1'b1) begin + REG_lo_151 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_151) == 1'b0) begin + end else begin + REG_lo_151 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_217x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_151))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_152 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==152); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_152 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_152) == 1'b1) begin + REG_lo_152 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_152) == 1'b0) begin + end else begin + REG_lo_152 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_218x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_152))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_153 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==153); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_153 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_153) == 1'b1) begin + REG_lo_153 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_153) == 1'b0) begin + end else begin + REG_lo_153 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_219x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_153))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_154 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==154); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_154 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_154) == 1'b1) begin + REG_lo_154 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_154) == 1'b0) begin + end else begin + REG_lo_154 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_220x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_154))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_155 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==155); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_155 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_155) == 1'b1) begin + REG_lo_155 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_155) == 1'b0) begin + end else begin + REG_lo_155 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_221x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_155))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_156 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==156); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_156 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_156) == 1'b1) begin + REG_lo_156 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_156) == 1'b0) begin + end else begin + REG_lo_156 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_222x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_156))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_157 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==157); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_157 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_157) == 1'b1) begin + REG_lo_157 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_157) == 1'b0) begin + end else begin + REG_lo_157 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_223x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_157))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_158 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==158); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_158 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_158) == 1'b1) begin + REG_lo_158 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_158) == 1'b0) begin + end else begin + REG_lo_158 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_224x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_158))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_159 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==159); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_159 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_159) == 1'b1) begin + REG_lo_159 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_159) == 1'b0) begin + end else begin + REG_lo_159 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_225x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_159))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_160 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==160); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_160 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_160) == 1'b1) begin + REG_lo_160 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_160) == 1'b0) begin + end else begin + REG_lo_160 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_226x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_160))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_161 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==161); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_161 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_161) == 1'b1) begin + REG_lo_161 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_161) == 1'b0) begin + end else begin + REG_lo_161 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_227x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_161))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_162 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==162); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_162 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_162) == 1'b1) begin + REG_lo_162 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_162) == 1'b0) begin + end else begin + REG_lo_162 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_228x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_162))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_163 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==163); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_163 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_163) == 1'b1) begin + REG_lo_163 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_163) == 1'b0) begin + end else begin + REG_lo_163 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_229x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_163))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_164 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==164); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_164 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_164) == 1'b1) begin + REG_lo_164 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_164) == 1'b0) begin + end else begin + REG_lo_164 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_230x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_164))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_165 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==165); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_165 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_165) == 1'b1) begin + REG_lo_165 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_165) == 1'b0) begin + end else begin + REG_lo_165 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_231x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_165))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_166 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==166); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_166 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_166) == 1'b1) begin + REG_lo_166 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_166) == 1'b0) begin + end else begin + REG_lo_166 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_232x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_166))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_167 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==167); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_167 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_167) == 1'b1) begin + REG_lo_167 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_167) == 1'b0) begin + end else begin + REG_lo_167 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_233x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_167))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_168 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==168); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_168 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_168) == 1'b1) begin + REG_lo_168 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_168) == 1'b0) begin + end else begin + REG_lo_168 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_234x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_168))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_169 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==169); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_169 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_169) == 1'b1) begin + REG_lo_169 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_169) == 1'b0) begin + end else begin + REG_lo_169 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_235x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_169))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_170 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==170); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_170 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_170) == 1'b1) begin + REG_lo_170 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_170) == 1'b0) begin + end else begin + REG_lo_170 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_236x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_170))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_171 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==171); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_171 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_171) == 1'b1) begin + REG_lo_171 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_171) == 1'b0) begin + end else begin + REG_lo_171 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_237x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_171))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_172 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==172); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_172 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_172) == 1'b1) begin + REG_lo_172 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_172) == 1'b0) begin + end else begin + REG_lo_172 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_238x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_172))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_173 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==173); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_173 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_173) == 1'b1) begin + REG_lo_173 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_173) == 1'b0) begin + end else begin + REG_lo_173 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_239x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_173))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_174 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==174); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_174 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_174) == 1'b1) begin + REG_lo_174 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_174) == 1'b0) begin + end else begin + REG_lo_174 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_240x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_174))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_175 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==175); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_175 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_175) == 1'b1) begin + REG_lo_175 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_175) == 1'b0) begin + end else begin + REG_lo_175 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_241x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_175))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_176 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==176); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_176 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_176) == 1'b1) begin + REG_lo_176 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_176) == 1'b0) begin + end else begin + REG_lo_176 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_242x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_176))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_177 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==177); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_177 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_177) == 1'b1) begin + REG_lo_177 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_177) == 1'b0) begin + end else begin + REG_lo_177 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_243x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_177))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_178 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==178); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_178 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_178) == 1'b1) begin + REG_lo_178 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_178) == 1'b0) begin + end else begin + REG_lo_178 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_244x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_178))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_179 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==179); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_179 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_179) == 1'b1) begin + REG_lo_179 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_179) == 1'b0) begin + end else begin + REG_lo_179 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_245x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_179))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_180 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==180); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_180 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_180) == 1'b1) begin + REG_lo_180 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_180) == 1'b0) begin + end else begin + REG_lo_180 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_246x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_180))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_181 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==181); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_181 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_181) == 1'b1) begin + REG_lo_181 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_181) == 1'b0) begin + end else begin + REG_lo_181 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_247x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_181))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_182 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==182); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_182 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_182) == 1'b1) begin + REG_lo_182 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_182) == 1'b0) begin + end else begin + REG_lo_182 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_248x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_182))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_183 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==183); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_183 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_183) == 1'b1) begin + REG_lo_183 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_183) == 1'b0) begin + end else begin + REG_lo_183 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_249x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_183))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_184 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==184); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_184 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_184) == 1'b1) begin + REG_lo_184 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_184) == 1'b0) begin + end else begin + REG_lo_184 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_250x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_184))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_185 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==185); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_185 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_185) == 1'b1) begin + REG_lo_185 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_185) == 1'b0) begin + end else begin + REG_lo_185 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_251x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_185))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_186 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==186); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_186 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_186) == 1'b1) begin + REG_lo_186 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_186) == 1'b0) begin + end else begin + REG_lo_186 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_252x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_186))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_187 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==187); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_187 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_187) == 1'b1) begin + REG_lo_187 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_187) == 1'b0) begin + end else begin + REG_lo_187 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_253x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_187))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_188 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==188); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_188 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_188) == 1'b1) begin + REG_lo_188 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_188) == 1'b0) begin + end else begin + REG_lo_188 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_254x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_188))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_189 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==189); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_189 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_189) == 1'b1) begin + REG_lo_189 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_189) == 1'b0) begin + end else begin + REG_lo_189 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_255x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_189))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_190 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==190); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_190 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_190) == 1'b1) begin + REG_lo_190 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_190) == 1'b0) begin + end else begin + REG_lo_190 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_256x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_190))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_191 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==191); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_191 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_191) == 1'b1) begin + REG_lo_191 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_191) == 1'b0) begin + end else begin + REG_lo_191 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_257x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_191))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_192 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==192); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_192 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_192) == 1'b1) begin + REG_lo_192 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_192) == 1'b0) begin + end else begin + REG_lo_192 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_258x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_192))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_193 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==193); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_193 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_193) == 1'b1) begin + REG_lo_193 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_193) == 1'b0) begin + end else begin + REG_lo_193 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_259x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_193))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_194 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==194); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_194 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_194) == 1'b1) begin + REG_lo_194 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_194) == 1'b0) begin + end else begin + REG_lo_194 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_260x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_194))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_195 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==195); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_195 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_195) == 1'b1) begin + REG_lo_195 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_195) == 1'b0) begin + end else begin + REG_lo_195 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_261x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_195))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_196 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==196); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_196 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_196) == 1'b1) begin + REG_lo_196 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_196) == 1'b0) begin + end else begin + REG_lo_196 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_262x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_196))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_197 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==197); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_197 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_197) == 1'b1) begin + REG_lo_197 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_197) == 1'b0) begin + end else begin + REG_lo_197 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_263x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_197))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_198 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==198); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_198 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_198) == 1'b1) begin + REG_lo_198 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_198) == 1'b0) begin + end else begin + REG_lo_198 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_264x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_198))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_199 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==199); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_199 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_199) == 1'b1) begin + REG_lo_199 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_199) == 1'b0) begin + end else begin + REG_lo_199 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_265x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_199))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_200 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==200); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_200 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_200) == 1'b1) begin + REG_lo_200 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_200) == 1'b0) begin + end else begin + REG_lo_200 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_266x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_200))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_201 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==201); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_201 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_201) == 1'b1) begin + REG_lo_201 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_201) == 1'b0) begin + end else begin + REG_lo_201 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_267x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_201))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_202 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==202); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_202 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_202) == 1'b1) begin + REG_lo_202 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_202) == 1'b0) begin + end else begin + REG_lo_202 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_268x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_202))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_203 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==203); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_203 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_203) == 1'b1) begin + REG_lo_203 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_203) == 1'b0) begin + end else begin + REG_lo_203 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_269x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_203))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_204 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==204); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_204 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_204) == 1'b1) begin + REG_lo_204 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_204) == 1'b0) begin + end else begin + REG_lo_204 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_270x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_204))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_205 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==205); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_205 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_205) == 1'b1) begin + REG_lo_205 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_205) == 1'b0) begin + end else begin + REG_lo_205 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_271x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_205))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_206 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==206); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_206 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_206) == 1'b1) begin + REG_lo_206 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_206) == 1'b0) begin + end else begin + REG_lo_206 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_272x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_206))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_207 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==207); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_207 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_207) == 1'b1) begin + REG_lo_207 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_207) == 1'b0) begin + end else begin + REG_lo_207 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_273x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_207))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_208 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==208); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_208 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_208) == 1'b1) begin + REG_lo_208 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_208) == 1'b0) begin + end else begin + REG_lo_208 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_274x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_208))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_209 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==209); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_209 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_209) == 1'b1) begin + REG_lo_209 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_209) == 1'b0) begin + end else begin + REG_lo_209 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_275x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_209))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_210 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==210); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_210 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_210) == 1'b1) begin + REG_lo_210 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_210) == 1'b0) begin + end else begin + REG_lo_210 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_276x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_210))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_211 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==211); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_211 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_211) == 1'b1) begin + REG_lo_211 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_211) == 1'b0) begin + end else begin + REG_lo_211 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_277x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_211))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_212 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==212); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_212 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_212) == 1'b1) begin + REG_lo_212 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_212) == 1'b0) begin + end else begin + REG_lo_212 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_278x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_212))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_213 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==213); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_213 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_213) == 1'b1) begin + REG_lo_213 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_213) == 1'b0) begin + end else begin + REG_lo_213 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_279x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_213))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_214 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==214); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_214 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_214) == 1'b1) begin + REG_lo_214 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_214) == 1'b0) begin + end else begin + REG_lo_214 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_280x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_214))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_215 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==215); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_215 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_215) == 1'b1) begin + REG_lo_215 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_215) == 1'b0) begin + end else begin + REG_lo_215 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_281x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_215))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_216 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==216); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_216 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_216) == 1'b1) begin + REG_lo_216 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_216) == 1'b0) begin + end else begin + REG_lo_216 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_282x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_216))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_217 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==217); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_217 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_217) == 1'b1) begin + REG_lo_217 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_217) == 1'b0) begin + end else begin + REG_lo_217 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_283x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_217))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_218 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==218); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_218 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_218) == 1'b1) begin + REG_lo_218 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_218) == 1'b0) begin + end else begin + REG_lo_218 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_284x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_218))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_219 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==219); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_219 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_219) == 1'b1) begin + REG_lo_219 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_219) == 1'b0) begin + end else begin + REG_lo_219 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_285x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_219))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_220 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==220); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_220 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_220) == 1'b1) begin + REG_lo_220 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_220) == 1'b0) begin + end else begin + REG_lo_220 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_286x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_220))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_221 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==221); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_221 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_221) == 1'b1) begin + REG_lo_221 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_221) == 1'b0) begin + end else begin + REG_lo_221 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_287x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_221))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_222 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==222); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_222 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_222) == 1'b1) begin + REG_lo_222 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_222) == 1'b0) begin + end else begin + REG_lo_222 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_288x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_222))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_223 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==223); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_223 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_223) == 1'b1) begin + REG_lo_223 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_223) == 1'b0) begin + end else begin + REG_lo_223 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_289x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_223))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_224 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==224); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_224 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_224) == 1'b1) begin + REG_lo_224 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_224) == 1'b0) begin + end else begin + REG_lo_224 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_290x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_224))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_225 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==225); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_225 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_225) == 1'b1) begin + REG_lo_225 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_225) == 1'b0) begin + end else begin + REG_lo_225 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_291x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_225))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_226 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==226); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_226 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_226) == 1'b1) begin + REG_lo_226 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_226) == 1'b0) begin + end else begin + REG_lo_226 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_292x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_226))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_227 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==227); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_227 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_227) == 1'b1) begin + REG_lo_227 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_227) == 1'b0) begin + end else begin + REG_lo_227 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_293x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_227))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_228 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==228); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_228 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_228) == 1'b1) begin + REG_lo_228 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_228) == 1'b0) begin + end else begin + REG_lo_228 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_294x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_228))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_229 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==229); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_229 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_229) == 1'b1) begin + REG_lo_229 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_229) == 1'b0) begin + end else begin + REG_lo_229 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_295x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_229))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_230 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==230); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_230 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_230) == 1'b1) begin + REG_lo_230 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_230) == 1'b0) begin + end else begin + REG_lo_230 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_296x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_230))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_231 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==231); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_231 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_231) == 1'b1) begin + REG_lo_231 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_231) == 1'b0) begin + end else begin + REG_lo_231 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_297x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_231))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_232 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==232); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_232 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_232) == 1'b1) begin + REG_lo_232 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_232) == 1'b0) begin + end else begin + REG_lo_232 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_298x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_232))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_233 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==233); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_233 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_233) == 1'b1) begin + REG_lo_233 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_233) == 1'b0) begin + end else begin + REG_lo_233 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_299x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_233))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_234 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==234); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_234 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_234) == 1'b1) begin + REG_lo_234 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_234) == 1'b0) begin + end else begin + REG_lo_234 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_300x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_234))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_235 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==235); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_235 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_235) == 1'b1) begin + REG_lo_235 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_235) == 1'b0) begin + end else begin + REG_lo_235 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_301x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_235))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_236 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==236); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_236 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_236) == 1'b1) begin + REG_lo_236 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_236) == 1'b0) begin + end else begin + REG_lo_236 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_302x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_236))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_237 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==237); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_237 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_237) == 1'b1) begin + REG_lo_237 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_237) == 1'b0) begin + end else begin + REG_lo_237 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_303x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_237))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_238 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==238); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_238 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_238) == 1'b1) begin + REG_lo_238 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_238) == 1'b0) begin + end else begin + REG_lo_238 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_304x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_238))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_239 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==239); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_239 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_239) == 1'b1) begin + REG_lo_239 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_239) == 1'b0) begin + end else begin + REG_lo_239 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_305x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_239))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_240 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==240); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_240 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_240) == 1'b1) begin + REG_lo_240 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_240) == 1'b0) begin + end else begin + REG_lo_240 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_306x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_240))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_241 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==241); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_241 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_241) == 1'b1) begin + REG_lo_241 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_241) == 1'b0) begin + end else begin + REG_lo_241 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_307x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_241))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_242 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==242); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_242 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_242) == 1'b1) begin + REG_lo_242 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_242) == 1'b0) begin + end else begin + REG_lo_242 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_308x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_242))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_243 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==243); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_243 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_243) == 1'b1) begin + REG_lo_243 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_243) == 1'b0) begin + end else begin + REG_lo_243 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_309x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_243))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_244 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==244); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_244 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_244) == 1'b1) begin + REG_lo_244 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_244) == 1'b0) begin + end else begin + REG_lo_244 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_310x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_244))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_245 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==245); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_245 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_245) == 1'b1) begin + REG_lo_245 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_245) == 1'b0) begin + end else begin + REG_lo_245 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_311x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_245))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_246 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==246); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_246 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_246) == 1'b1) begin + REG_lo_246 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_246) == 1'b0) begin + end else begin + REG_lo_246 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_312x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_246))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_247 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==247); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_247 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_247) == 1'b1) begin + REG_lo_247 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_247) == 1'b0) begin + end else begin + REG_lo_247 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_313x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_247))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_248 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==248); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_248 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_248) == 1'b1) begin + REG_lo_248 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_248) == 1'b0) begin + end else begin + REG_lo_248 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_314x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_248))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_249 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==249); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_249 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_249) == 1'b1) begin + REG_lo_249 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_249) == 1'b0) begin + end else begin + REG_lo_249 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_315x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_249))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_250 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==250); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_250 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_250) == 1'b1) begin + REG_lo_250 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_250) == 1'b0) begin + end else begin + REG_lo_250 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_316x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_250))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_251 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==251); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_251 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_251) == 1'b1) begin + REG_lo_251 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_251) == 1'b0) begin + end else begin + REG_lo_251 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_317x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_251))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_252 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==252); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_252 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_252) == 1'b1) begin + REG_lo_252 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_252) == 1'b0) begin + end else begin + REG_lo_252 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_318x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_252))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_253 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==253); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_253 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_253) == 1'b1) begin + REG_lo_253 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_253) == 1'b0) begin + end else begin + REG_lo_253 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_319x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_253))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_254 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==254); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_254 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_254) == 1'b1) begin + REG_lo_254 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_254) == 1'b0) begin + end else begin + REG_lo_254 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_320x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_254))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_255 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==255); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_255 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_255) == 1'b1) begin + REG_lo_255 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_255) == 1'b0) begin + end else begin + REG_lo_255 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_321x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_255))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign lo_wr_en_256 = pro_in_wr_en & pro_in_select_lo & (pro_in_addr==256); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + REG_lo_256 <= {16{1'b0}}; + end else begin + if ((lo_wr_en_256) == 1'b1) begin + REG_lo_256 <= pro_in_data; +// VCS coverage off + end else if ((lo_wr_en_256) == 1'b0) begin + end else begin + REG_lo_256 <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_322x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lo_wr_en_256))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//viva_pipe -bc lut_in_pd(lut_in_pvld, lut_in_prdy) <= idx2lut_pd(idx2lut_pvld,idx2lut_prdy); +NV_NVDLA_SDP_CORE_Y_lut_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.idx2lut_pvld (idx2lut_pvld) + ,.idx2lut_prdy (idx2lut_prdy) + ,.idx2lut_pd (idx2lut_pd[81*0 -1:0]) + ,.lut_in_pvld (lut_in_pvld) + ,.lut_in_prdy (lut_in_prdy) + ,.lut_in_pd (lut_in_pd[81*0 -1:0]) + ); +// PKT_UNPACK_WIRE( sdp_y_lut_in , lut_in_ , lut_in_pd ) +//: my $k=0; +//: my $bx =0*35; +//: my $bof=0*(35+32); +//: my $buf=0*(35+32+1); +//: my $bsl=0*(35+32+2); +//: my $ba =0*(35+32+3); +//: my $beh=0*(35+32+12); +//: my $boh=0*(35+32+13); +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_fraction${i}[34:0] = lut_in_pd[35*${i}+34:35*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_x${i}[31:0] = lut_in_pd[32*${i}+31+${bx}:32*${i}+${bx}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_oflow${i} = lut_in_pd[${i}+${bof}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_uflow${i} = lut_in_pd[${i}+${buf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_sel${i} = lut_in_pd[${i}+${bsl}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_addr${i}[8:0] = lut_in_pd[9*${i}+8+${ba}:9*${i}+${ba}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_le_hit${i} = lut_in_pd[${i}+${beh}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_in_lo_hit${i} = lut_in_pd[${i}+${boh}]; \n"; +//: } +//======================================= +// PERF STATISTIC +// OFLOW +//: my $k=0; +//: print "assign lut_oflow_sum[4:0] = lut_in_oflow0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_oflow${i}"; +//: } +//: } +//: print ";\n"; +assign perf_lut_oflow_add = (&lut_oflow_cnt) ? 0 : lut_oflow_sum; +assign perf_lut_oflow_sub = 1'b0; +assign dp2reg_lut_oflow = lut_oflow_cnt; +always @( + perf_lut_oflow_add + or perf_lut_oflow_sub + ) begin + perf_lut_oflow_adv = perf_lut_oflow_add[4:0] != {{4{1'b0}}, perf_lut_oflow_sub[0:0]}; +end +always @( + perf_lut_oflow_cnt_cur + or perf_lut_oflow_add + or perf_lut_oflow_sub + or perf_lut_oflow_adv + or op_en_load + ) begin + perf_lut_oflow_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_oflow_cnt_cur}; + perf_lut_oflow_cnt_mod[33:0] = perf_lut_oflow_cnt_cur + perf_lut_oflow_add[4:0] - perf_lut_oflow_sub[0:0]; // spyglass disable W164b + perf_lut_oflow_cnt_new[33:0] = (perf_lut_oflow_adv)? perf_lut_oflow_cnt_mod[33:0] : perf_lut_oflow_cnt_ext[33:0]; + perf_lut_oflow_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_oflow_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_oflow_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_oflow_cnt_cur[31:0] <= perf_lut_oflow_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_oflow_cnt_cur + ) begin + lut_oflow_cnt[31:0] = perf_lut_oflow_cnt_cur[31:0]; +end +// UFLOW +//: my $k=0; +//: print "assign lut_uflow_sum[4:0] = lut_in_uflow0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_uflow${i}"; +//: } +//: } +//: print ";\n"; +assign perf_lut_uflow_add = (&lut_uflow_cnt) ? 0 : lut_uflow_sum; +assign perf_lut_uflow_sub = 1'b0; +assign dp2reg_lut_uflow = lut_uflow_cnt; +always @( + perf_lut_uflow_add + or perf_lut_uflow_sub + ) begin + perf_lut_uflow_adv = perf_lut_uflow_add[4:0] != {{4{1'b0}}, perf_lut_uflow_sub[0:0]}; +end +always @( + perf_lut_uflow_cnt_cur + or perf_lut_uflow_add + or perf_lut_uflow_sub + or perf_lut_uflow_adv + or op_en_load + ) begin + perf_lut_uflow_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_uflow_cnt_cur}; + perf_lut_uflow_cnt_mod[33:0] = perf_lut_uflow_cnt_cur + perf_lut_uflow_add[4:0] - perf_lut_uflow_sub[0:0]; // spyglass disable W164b + perf_lut_uflow_cnt_new[33:0] = (perf_lut_uflow_adv)? perf_lut_uflow_cnt_mod[33:0] : perf_lut_uflow_cnt_ext[33:0]; + perf_lut_uflow_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_uflow_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_uflow_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_uflow_cnt_cur[31:0] <= perf_lut_uflow_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_uflow_cnt_cur + ) begin + lut_uflow_cnt[31:0] = perf_lut_uflow_cnt_cur[31:0]; +end +// HYBRID +//: my $k=0; +//: foreach my $i (1..${k}-1) { +//: print "assign lut_in_hybrid${i} = !(lut_in_oflow${i} | lut_in_uflow${i}); \n"; +//: } +//: print "\n"; +//: print "assign lut_hybrid_sum[4:0] = lut_in_hybrid0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_hybrid${i}"; +//: } +//: } +//: print ";\n"; +assign perf_lut_hybrid_add = (&lut_hybrid_cnt) ? 0 : lut_hybrid_sum; +assign perf_lut_hybrid_sub = 1'b0; +assign dp2reg_lut_hybrid = lut_hybrid_cnt; +always @( + perf_lut_hybrid_add + or perf_lut_hybrid_sub + ) begin + perf_lut_hybrid_adv = perf_lut_hybrid_add[4:0] != {{4{1'b0}}, perf_lut_hybrid_sub[0:0]}; +end +always @( + perf_lut_hybrid_cnt_cur + or perf_lut_hybrid_add + or perf_lut_hybrid_sub + or perf_lut_hybrid_adv + or op_en_load + ) begin + perf_lut_hybrid_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_hybrid_cnt_cur}; + perf_lut_hybrid_cnt_mod[33:0] = perf_lut_hybrid_cnt_cur + perf_lut_hybrid_add[4:0] - perf_lut_hybrid_sub[0:0]; // spyglass disable W164b + perf_lut_hybrid_cnt_new[33:0] = (perf_lut_hybrid_adv)? perf_lut_hybrid_cnt_mod[33:0] : perf_lut_hybrid_cnt_ext[33:0]; + perf_lut_hybrid_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_hybrid_cnt_new[33:0]; +end +// perf_lut_hybrid flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_hybrid_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_hybrid_cnt_cur[31:0] <= perf_lut_hybrid_cnt_nxt[31:0]; + end + end +end +// perf_lut_hybrid output logic +always @( + perf_lut_hybrid_cnt_cur + ) begin + lut_hybrid_cnt[31:0] = perf_lut_hybrid_cnt_cur[31:0]; +end +// LE_HIT +//: my $k=0; +//: print "assign lut_le_hit_sum[4:0] = lut_in_le_hit0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_le_hit${i}"; +//: } +//: } +//: print ";\n"; +assign perf_lut_le_hit_add = (&lut_le_hit_cnt) ? 0 : lut_le_hit_sum; +assign perf_lut_le_hit_sub = 1'b0; +assign dp2reg_lut_le_hit = lut_le_hit_cnt; +always @( + perf_lut_le_hit_add + or perf_lut_le_hit_sub + ) begin + perf_lut_le_hit_adv = perf_lut_le_hit_add[4:0] != {{4{1'b0}}, perf_lut_le_hit_sub[0:0]}; +end +// perf_lut_le_hit cnt logic +always @( + perf_lut_le_hit_cnt_cur + or perf_lut_le_hit_add + or perf_lut_le_hit_sub + or perf_lut_le_hit_adv + or op_en_load + ) begin +// VCS sop_coverage_off start + perf_lut_le_hit_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_le_hit_cnt_cur}; + perf_lut_le_hit_cnt_mod[33:0] = perf_lut_le_hit_cnt_cur + perf_lut_le_hit_add[4:0] - perf_lut_le_hit_sub[0:0]; + perf_lut_le_hit_cnt_new[33:0] = (perf_lut_le_hit_adv)? perf_lut_le_hit_cnt_mod[33:0] : perf_lut_le_hit_cnt_ext[33:0]; + perf_lut_le_hit_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_le_hit_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_le_hit_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_le_hit_cnt_cur[31:0] <= perf_lut_le_hit_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_le_hit_cnt_cur + ) begin + lut_le_hit_cnt[31:0] = perf_lut_le_hit_cnt_cur[31:0]; +end +// LO_HIT +//: my $k=0; +//: print "assign lut_lo_hit_sum[4:0] = lut_in_lo_hit0"; +//: if(${k} >1) { +//: foreach my $i (1..${k}-1) { +//: print "+ lut_in_lo_hit${i}"; +//: } +//: } +//: print ";\n"; +assign perf_lut_lo_hit_add = (&lut_lo_hit_cnt) ? 0 : lut_lo_hit_sum; +assign perf_lut_lo_hit_sub = 1'b0; +assign dp2reg_lut_lo_hit = lut_lo_hit_cnt; +always @( + perf_lut_lo_hit_add + or perf_lut_lo_hit_sub + ) begin + perf_lut_lo_hit_adv = perf_lut_lo_hit_add[4:0] != {{4{1'b0}}, perf_lut_lo_hit_sub[0:0]}; +end +always @( + perf_lut_lo_hit_cnt_cur + or perf_lut_lo_hit_add + or perf_lut_lo_hit_sub + or perf_lut_lo_hit_adv + or op_en_load + ) begin + perf_lut_lo_hit_cnt_ext[33:0] = {1'b0, 1'b0, perf_lut_lo_hit_cnt_cur}; + perf_lut_lo_hit_cnt_mod[33:0] = perf_lut_lo_hit_cnt_cur + perf_lut_lo_hit_add[4:0] - perf_lut_lo_hit_sub[0:0]; // spyglass disable W164b + perf_lut_lo_hit_cnt_new[33:0] = (perf_lut_lo_hit_adv)? perf_lut_lo_hit_cnt_mod[33:0] : perf_lut_lo_hit_cnt_ext[33:0]; + perf_lut_lo_hit_cnt_nxt[33:0] = (op_en_load)? 34'd0 : perf_lut_lo_hit_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + perf_lut_lo_hit_cnt_cur[31:0] <= 0; + end else begin + if (reg2dp_perf_lut_en) begin + perf_lut_lo_hit_cnt_cur[31:0] <= perf_lut_lo_hit_cnt_nxt[31:0]; + end + end +end +always @( + perf_lut_lo_hit_cnt_cur + ) begin + lut_lo_hit_cnt[31:0] = perf_lut_lo_hit_cnt_cur[31:0]; +end +//======================================= +// rd addr mux +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign lut_in_addr${i}_0 = lut_in_addr${i}; +//: assign lut_in_addr${i}_1 = lut_in_addr${i} + 1; +//: ); +//: } +//: +//: my $lut_depth = 257; +//: foreach my $lut (qw(le lo)) { +//: foreach my $x (0..1) { +//: foreach my $i (0.. ${k}-1) { +//: print qq( +//: always @ ( * ) begin +//: case (lut_in_addr${i}_${x}) +//: ); +//: foreach my $idx ($x .. ${lut_depth}-1) { +//: print" $idx: ${lut}_data${x}_${i} = REG_${lut}_$idx; \n"; +//: } +//: print qq( +//: default: ${lut}_data${x}_${i}= {16{`x_or_0}}; +//: endcase +//: end +//: ); +//: } +//: } +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign dat_in_y0_$i = (lut_in_sel${i}==1'b0) ? le_data0_$i : lo_data0_$i; +//: assign dat_in_y1_$i = (lut_in_sel${i}==1'b0) ? le_data1_$i : lo_data1_$i; +//: ); +//: } +//======================================= +// dat fifo wr +assign rd_lut_en = lut_in_pvld & lut_in_prdy; +assign dat_fifo_wr_pvld = rd_lut_en; +// PKT_PACK_WIRE( sdp_y_lut_dat , dat_in_ , dat_fifo_wr_pd ) +//: my $k=0; +//: my $b=0*16; +//: foreach my $i (0..${k}-1) { +//: print "assign dat_fifo_wr_pd[16*${i}+15:16*${i}] = dat_in_y0_${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign dat_fifo_wr_pd[16*${i}+${b}+15:16*${i}+${b}] = dat_in_y1_${i}[15:0]; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print "assign out_y0_${i}[15:0] = dat_fifo_rd_pd[16*${i}+15:16*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_y1_${i}[15:0] = dat_fifo_rd_pd[16*${i}+${b}+15:16*${i}+${b}]; \n"; +//: } +NV_NVDLA_SDP_CORE_Y_LUT_dat u_dat ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dat_fifo_wr_pvld (dat_fifo_wr_pvld) //|< w + ,.dat_fifo_wr_pd (dat_fifo_wr_pd[32*0 -1:0]) //|< w + ,.dat_fifo_rd_prdy (dat_fifo_rd_prdy) //|< w + ,.dat_fifo_rd_pvld (dat_fifo_rd_pvld) //|> w + ,.dat_fifo_rd_pd (dat_fifo_rd_pd[32*0 -1:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +// dat fifo rd +assign dat_fifo_rd_prdy = lut_out_prdy; +//============ +// cmd fifo wr: +// PKT_PACK_WIRE( sdp_y_lut_cmd , lut_in_ , cmd_fifo_wr_pd ) +//: my $k=0; +//: my $bx =0*35; +//: my $bof=0*(35+32); +//: my $buf=0*(35+32+1); +//: my $bsl=0*(35+32+2); +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[35*${i}+34:35*${i}] = lut_in_fraction${i}[34:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[32*${i}+31+${bx}:32*${i}+${bx}] = lut_in_x${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[${i}+${bof}] = lut_in_oflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[${i}+${buf}] = lut_in_uflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cmd_fifo_wr_pd[${i}+${bsl}] = lut_in_sel${i} ; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print "assign out_fraction${i}[34:0] = cmd_fifo_rd_pd[35*${i}+34:35*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_x${i}[31:0] = cmd_fifo_rd_pd[32*${i}+31+${bx}:32*${i}+${bx}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_oflow${i} = cmd_fifo_rd_pd[${i}+${bof}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_uflow${i} = cmd_fifo_rd_pd[${i}+${buf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign out_sel${i} = cmd_fifo_rd_pd[${i}+${bsl}]; \n"; +//: } +assign cmd_fifo_wr_pvld = lut_in_pvld; +assign lut_in_prdy = cmd_fifo_wr_prdy; +// cmd fifo inst: +NV_NVDLA_SDP_CORE_Y_LUT_cmd u_cmd ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd_fifo_wr_prdy (cmd_fifo_wr_prdy) //|> w + ,.cmd_fifo_wr_pvld (cmd_fifo_wr_pvld) //|< w + ,.cmd_fifo_wr_pd (cmd_fifo_wr_pd[70*0 -1:0]) //|< w + ,.cmd_fifo_rd_prdy (cmd_fifo_rd_prdy) //|< w + ,.cmd_fifo_rd_pvld (cmd_fifo_rd_pvld) //|> w + ,.cmd_fifo_rd_pd (cmd_fifo_rd_pd[70*0 -1:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +// cmd fifo rd: +assign cmd_fifo_rd_prdy = lut_out_prdy & dat_fifo_rd_pvld; +//======================================= +// output mux when oflow/uflow +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print "assign out_flow${i} = out_uflow${i} | out_oflow${i}; \n"; +//: } +//: +//: foreach my $i (0.. ${k}-1) { +//: print qq( +//: always @( +//: out_uflow$i +//: or out_sel$i +//: or reg2dp_lut_le_slope_uflow_scale +//: or reg2dp_lut_le_slope_uflow_shift +//: or reg2dp_lut_le_start +//: or reg2dp_lut_le_function +//: or reg2dp_proc_precision +//: or reg2dp_lut_le_index_offset +//: or reg2dp_lut_lo_slope_uflow_scale +//: or reg2dp_lut_lo_slope_uflow_shift +//: or reg2dp_lut_lo_start +//: or out_oflow$i +//: or reg2dp_lut_le_slope_oflow_scale +//: or reg2dp_lut_le_slope_oflow_shift +//: or reg2dp_lut_le_end +//: or reg2dp_lut_lo_slope_oflow_scale +//: or reg2dp_lut_lo_slope_oflow_shift +//: or reg2dp_lut_lo_end +//: ) begin +//: if (out_uflow${i}) begin +//: if (out_sel${i}==1'b0) begin +//: out_scale${i} = reg2dp_lut_le_slope_uflow_scale; +//: out_shift${i} = reg2dp_lut_le_slope_uflow_shift; +//: out_offset${i} = reg2dp_lut_le_start; +//: if (reg2dp_lut_le_function==1'b0) begin +//: out_bias${i} = reg2dp_lut_le_index_offset[8 -1] ? 0 : (1 << reg2dp_lut_le_index_offset); +//: end else begin +//: out_bias${i} = 0; +//: end +//: end else begin +//: out_scale${i} = reg2dp_lut_lo_slope_uflow_scale; +//: out_shift${i} = reg2dp_lut_lo_slope_uflow_shift; +//: out_offset${i} = reg2dp_lut_lo_start; +//: out_bias${i} = 0; +//: end +//: end else if (out_oflow${i}) begin +//: if (out_sel${i}==1'b0) begin +//: out_scale${i} = reg2dp_lut_le_slope_oflow_scale; +//: out_shift${i} = reg2dp_lut_le_slope_oflow_shift; +//: out_offset${i} = reg2dp_lut_le_end; +//: out_bias${i} = 0; +//: end else begin +//: out_scale${i} = reg2dp_lut_lo_slope_oflow_scale; +//: out_shift${i} = reg2dp_lut_lo_slope_oflow_shift; +//: out_offset${i} = reg2dp_lut_lo_end; +//: out_bias${i} = 0; +//: end +//: end else begin +//: out_scale${i} = 0; +//: out_shift${i} = 0; +//: out_offset${i} = 0; +//: out_bias${i} = 0; +//: end +//: end +//: ); +//: } +//======================================= +// output pipe +assign lut_out_pvld = dat_fifo_rd_pvld; +// PKT_PACK_WIRE( sdp_y_lut_out , out_ , lut_out_pd ) +//: my $k=0; +//: my $bf =0*32; +//: my $by0=0*(32+35); +//: my $by1=0*(32+35+16); +//: my $bsc=0*(32+35+32); +//: my $bsf=0*(32+35+48); +//: my $bof=0*(32+35+48+5); +//: my $bbs=0*(32+35+85); +//: my $bfw=0*(32+35+85+32); +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[32*${i}+31:32*${i}] = out_x${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[35*${i}+${bf}+34:35*${i}+${bf}] = out_fraction${i}[34:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[16*${i}+${by0}+15:16*${i}+${by0}] = out_y0_${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[16*${i}+${by1}+15:16*${i}+${by1}] = out_y1_${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[16*${i}+${bsc}+15:16*${i}+${bsc}] = out_scale${i}[15:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[5*${i}+${bsf}+4:5*${i}+${bsf}] = out_shift${i}[4:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[32*${i}+${bof}+31:32*${i}+${bof}] = out_offset${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[32*${i}+${bbs}+31:32*${i}+${bbs}] = out_bias${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign lut_out_pd[${i}+${bfw}] = out_flow${i}; \n"; +//: } +NV_NVDLA_SDP_CORE_Y_lut_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.lut_out_pvld (lut_out_pvld) + ,.lut_out_prdy (lut_out_prdy) + ,.lut_out_pd (lut_out_pd[185*0 -1:0]) + ,.lut2inp_pvld (lut2inp_pvld) + ,.lut2inp_prdy (lut2inp_prdy) + ,.lut2inp_pd (lut2inp_pd[185*0 -1:0]) + ); +//======================================= +// Assertions +assign mon_cmd_fifo_rd_pvld = cmd_fifo_rd_pvld; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when data is ready, cmd should be ready, which is faster") zzz_assert_never_327x (nvdla_core_clk, `ASSERT_RESET, dat_fifo_rd_pvld & !mon_cmd_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// Assertion for LUT Programing +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"exceed the size of LE LUT") zzz_assert_never_328x (nvdla_core_clk, `ASSERT_RESET, (lut_table_id== 1'h0 ) && lut_addr> 65); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"exceed the size of LE LUT") zzz_assert_never_329x (nvdla_core_clk, `ASSERT_RESET, (lut_table_id== 1'h1 ) && lut_addr> 257); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_SDP_CORE_Y_lut +module NV_NVDLA_SDP_CORE_Y_lut_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx2lut_pvld + ,idx2lut_prdy + ,idx2lut_pd + ,lut_in_pvld + ,lut_in_prdy + ,lut_in_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx2lut_pvld; +output idx2lut_prdy; +input [81*0 -1:0] idx2lut_pd; +output lut_in_pvld; +input lut_in_prdy; +output [81*0 -1:0] lut_in_pd; +//: my $dw = 81*0; +//: &eperl::pipe("-is -wid $dw -do lut_in_pd -vo lut_in_pvld -ri lut_in_prdy -di idx2lut_pd -vi idx2lut_pvld -ro idx2lut_prdy"); +endmodule +module NV_NVDLA_SDP_CORE_Y_lut_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_out_pvld + ,lut_out_prdy + ,lut_out_pd + ,lut2inp_pvld + ,lut2inp_prdy + ,lut2inp_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input lut_out_pvld; +output lut_out_prdy; +input [185*0 -1:0] lut_out_pd; +output lut2inp_pvld; +input lut2inp_prdy; +output [185*0 -1:0] lut2inp_pd; +//: my $dw = 185*0; +//: &eperl::pipe("-is -wid $dw -do lut2inp_pd -vo lut2inp_pvld -ri lut2inp_prdy -di lut_out_pd -vi lut_out_pvld -ro lut_out_prdy"); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v new file mode 100644 index 0000000..c314803 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v @@ -0,0 +1,1102 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_gate.v +module NV_NVDLA_SDP_CORE_gate ( + bcore_slcg_en + ,dla_clk_ovr_on_sync + ,ecore_slcg_en + ,global_clk_ovr_on_sync + ,ncore_slcg_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_bcore_clk + ,nvdla_gated_ecore_clk + ,nvdla_gated_ncore_clk + ); +input bcore_slcg_en; +input dla_clk_ovr_on_sync; +input ecore_slcg_en; +input global_clk_ovr_on_sync; +input ncore_slcg_en; +input nvdla_core_clk; +input nvdla_core_rstn; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_bcore_clk; +output nvdla_gated_ecore_clk; +output nvdla_gated_ncore_clk; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = bcore_slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_bcore_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_1_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_1_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_1_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_1_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_1_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_1_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_1_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_1_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_1_icg_override_to_ungated; +reg nvdla_core_clk_slcg_1_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_1_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_1_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_1_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_1_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_1"); +end +wire assert2slcg_disable_clock_gating_1; +assign assert2slcg_disable_clock_gating_1 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_1) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +always @(negedge assert2slcg_disable_clock_gating_1) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_1_en; +assign nvdla_core_clk_slcg_1_en = ncore_slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_1_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_1_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_1_end_of_sim_clock_enable + | nvdla_core_clk_slcg_1_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_1 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_1_en), + .clk_gated(nvdla_gated_ncore_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_2_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_2_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_2_internal_nvdla_core_rstn +// Clock signal: testpoint_2_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_2_internal_nvdla_core_clk or negedge testpoint_2_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_2 + if (~testpoint_2_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_2_count_0; + reg testpoint_2_goal_0; + initial testpoint_2_goal_0 = 0; + initial testpoint_2_count_0 = 0; + always@(testpoint_2_count_0) begin + if(testpoint_2_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_2_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1 ::: testpoint_2_goal_0 + testpoint_2_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_2_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_2_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2 + if (testpoint_2_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1 ::: testpoint_2_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk) + testpoint_2_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk) begin + `endif + testpoint_2_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_2_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_nvdla_core_clk), .tp(testpoint_2_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1__1_b1_0 (.clk (testpoint_2_internal_nvdla_core_clk), .tp(testpoint_2_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_3_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_3_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_3_internal_nvdla_core_rstn +// Clock signal: testpoint_3_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_3_internal_nvdla_core_clk or negedge testpoint_3_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_3 + if (~testpoint_3_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_3_count_0; + reg testpoint_3_goal_0; + initial testpoint_3_goal_0 = 0; + initial testpoint_3_count_0 = 0; + always@(testpoint_3_count_0) begin + if(testpoint_3_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_3_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0 ::: testpoint_3_goal_0 + testpoint_3_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_3_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_3_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_3 + if (testpoint_3_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0 ::: testpoint_3_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk) + testpoint_3_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk) begin + `endif + testpoint_3_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_3_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_3_goal_0 (.clk (testpoint_3_internal_nvdla_core_clk), .tp(testpoint_3_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1__1_b0_0 (.clk (testpoint_3_internal_nvdla_core_clk), .tp(testpoint_3_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_1; + reg done_monitor_1; + integer clk_count_1; + integer clk_disable_count_1; + initial begin + clk_count_1 = 0; + clk_disable_count_1 = 0; +// monitor_icg_summary_1 = 0; + done_monitor_1= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_1 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_1 <= 0; + clk_disable_count_1 <= 0; + end else begin + clk_count_1 <= clk_count_1 + 1; + if ( ~(nvdla_core_clk_slcg_1_en) == 1'b1) begin + clk_disable_count_1 <= clk_disable_count_1 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_1 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_1 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (1) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_1, clk_count_1, enabled_percent_1); + $display ("(%0d): INFO: %m (icg_template): ICG (1) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_1, clk_count_1, 1.0 - (1.0 * (clk_disable_count_1) / (clk_count_1))); + done_monitor_1 <= 1; + end + end + end + end + end +////integer enabled_percent_1; +////&Always; +//// if (monitor_icg_summary_1 == 1) begin +//// enabled_percent_1 = 1.0 - ( ( clk_disable_count_1 ) / ( clk_count_1 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (1) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_2_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_2_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_2_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_2_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_2_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_2_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_2_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_2_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_2_icg_override_to_ungated; +reg nvdla_core_clk_slcg_2_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_2_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_2_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_2_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_2_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_2"); +end +wire assert2slcg_disable_clock_gating_2; +assign assert2slcg_disable_clock_gating_2 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_2) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +always @(negedge assert2slcg_disable_clock_gating_2) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_2_en; +assign nvdla_core_clk_slcg_2_en = ecore_slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_2_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_2_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_2_end_of_sim_clock_enable + | nvdla_core_clk_slcg_2_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_2 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_2_en), + .clk_gated(nvdla_gated_ecore_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_4_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_4_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_4_internal_nvdla_core_rstn +// Clock signal: testpoint_4_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_4_internal_nvdla_core_clk or negedge testpoint_4_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_4 + if (~testpoint_4_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_4_count_0; + reg testpoint_4_goal_0; + initial testpoint_4_goal_0 = 0; + initial testpoint_4_count_0 = 0; + always@(testpoint_4_count_0) begin + if(testpoint_4_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_4_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1 ::: testpoint_4_goal_0 + testpoint_4_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_4_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_4_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_4 + if (testpoint_4_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1 ::: testpoint_4_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk) + testpoint_4_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk) begin + `endif + testpoint_4_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_4_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_4_goal_0 (.clk (testpoint_4_internal_nvdla_core_clk), .tp(testpoint_4_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2__1_b1_0 (.clk (testpoint_4_internal_nvdla_core_clk), .tp(testpoint_4_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_5_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_5_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_5_internal_nvdla_core_rstn +// Clock signal: testpoint_5_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_5_internal_nvdla_core_clk or negedge testpoint_5_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_5 + if (~testpoint_5_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_5_count_0; + reg testpoint_5_goal_0; + initial testpoint_5_goal_0 = 0; + initial testpoint_5_count_0 = 0; + always@(testpoint_5_count_0) begin + if(testpoint_5_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_5_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0 ::: testpoint_5_goal_0 + testpoint_5_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_5_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_5_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_5 + if (testpoint_5_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0 ::: testpoint_5_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk) + testpoint_5_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk) begin + `endif + testpoint_5_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_5_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_5_goal_0 (.clk (testpoint_5_internal_nvdla_core_clk), .tp(testpoint_5_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2__1_b0_0 (.clk (testpoint_5_internal_nvdla_core_clk), .tp(testpoint_5_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_2; + reg done_monitor_2; + integer clk_count_2; + integer clk_disable_count_2; + initial begin + clk_count_2 = 0; + clk_disable_count_2 = 0; +// monitor_icg_summary_2 = 0; + done_monitor_2= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_2 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_2 <= 0; + clk_disable_count_2 <= 0; + end else begin + clk_count_2 <= clk_count_2 + 1; + if ( ~(nvdla_core_clk_slcg_2_en) == 1'b1) begin + clk_disable_count_2 <= clk_disable_count_2 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_2 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_2 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (2) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_2, clk_count_2, enabled_percent_2); + $display ("(%0d): INFO: %m (icg_template): ICG (2) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_2, clk_count_2, 1.0 - (1.0 * (clk_disable_count_2) / (clk_count_2))); + done_monitor_2 <= 1; + end + end + end + end + end +////integer enabled_percent_2; +////&Always; +//// if (monitor_icg_summary_2 == 1) begin +//// enabled_percent_2 = 1.0 - ( ( clk_disable_count_2 ) / ( clk_count_2 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (2) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_CORE_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v.vcp new file mode 100644 index 0000000..c314803 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_gate.v.vcp @@ -0,0 +1,1102 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_gate.v +module NV_NVDLA_SDP_CORE_gate ( + bcore_slcg_en + ,dla_clk_ovr_on_sync + ,ecore_slcg_en + ,global_clk_ovr_on_sync + ,ncore_slcg_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_bcore_clk + ,nvdla_gated_ecore_clk + ,nvdla_gated_ncore_clk + ); +input bcore_slcg_en; +input dla_clk_ovr_on_sync; +input ecore_slcg_en; +input global_clk_ovr_on_sync; +input ncore_slcg_en; +input nvdla_core_clk; +input nvdla_core_rstn; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_bcore_clk; +output nvdla_gated_ecore_clk; +output nvdla_gated_ncore_clk; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = bcore_slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_bcore_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_1_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_1_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_1_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_1_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_1_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_1_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_1_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_1_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_1_icg_override_to_ungated; +reg nvdla_core_clk_slcg_1_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_1_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_1_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_1_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_1_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_1"); +end +wire assert2slcg_disable_clock_gating_1; +assign assert2slcg_disable_clock_gating_1 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_1) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +always @(negedge assert2slcg_disable_clock_gating_1) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_1"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_1_en; +assign nvdla_core_clk_slcg_1_en = ncore_slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_1_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_1_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_1_end_of_sim_clock_enable + | nvdla_core_clk_slcg_1_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_1 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_1_en), + .clk_gated(nvdla_gated_ncore_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_2_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_2_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_2_internal_nvdla_core_rstn +// Clock signal: testpoint_2_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_2_internal_nvdla_core_clk or negedge testpoint_2_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_2 + if (~testpoint_2_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_2_count_0; + reg testpoint_2_goal_0; + initial testpoint_2_goal_0 = 0; + initial testpoint_2_count_0 = 0; + always@(testpoint_2_count_0) begin + if(testpoint_2_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_2_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1 ::: testpoint_2_goal_0 + testpoint_2_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_2_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_2_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_2 + if (testpoint_2_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b1 ::: testpoint_2_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk) + testpoint_2_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk) begin + `endif + testpoint_2_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_2_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_2_internal_nvdla_core_rstn_with_clock_testpoint_2_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_2_goal_0 (.clk (testpoint_2_internal_nvdla_core_clk), .tp(testpoint_2_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1__1_b1_0 (.clk (testpoint_2_internal_nvdla_core_clk), .tp(testpoint_2_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_3_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_3_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_3_internal_nvdla_core_rstn +// Clock signal: testpoint_3_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_3_internal_nvdla_core_clk or negedge testpoint_3_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_3 + if (~testpoint_3_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_3_count_0; + reg testpoint_3_goal_0; + initial testpoint_3_goal_0 = 0; + initial testpoint_3_count_0 = 0; + always@(testpoint_3_count_0) begin + if(testpoint_3_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_3_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0 ::: testpoint_3_goal_0 + testpoint_3_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_3_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_3_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_3 + if (testpoint_3_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_1 = 1'b0 ::: testpoint_3_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk) + testpoint_3_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk) begin + `endif + testpoint_3_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_3_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_3_internal_nvdla_core_rstn_with_clock_testpoint_3_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_3_goal_0 (.clk (testpoint_3_internal_nvdla_core_clk), .tp(testpoint_3_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1__1_b0_0 (.clk (testpoint_3_internal_nvdla_core_clk), .tp(testpoint_3_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_1___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_1; + reg done_monitor_1; + integer clk_count_1; + integer clk_disable_count_1; + initial begin + clk_count_1 = 0; + clk_disable_count_1 = 0; +// monitor_icg_summary_1 = 0; + done_monitor_1= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_1 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_1 <= 0; + clk_disable_count_1 <= 0; + end else begin + clk_count_1 <= clk_count_1 + 1; + if ( ~(nvdla_core_clk_slcg_1_en) == 1'b1) begin + clk_disable_count_1 <= clk_disable_count_1 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_1 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_1 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (1) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_1, clk_count_1, enabled_percent_1); + $display ("(%0d): INFO: %m (icg_template): ICG (1) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_1, clk_count_1, 1.0 - (1.0 * (clk_disable_count_1) / (clk_count_1))); + done_monitor_1 <= 1; + end + end + end + end + end +////integer enabled_percent_1; +////&Always; +//// if (monitor_icg_summary_1 == 1) begin +//// enabled_percent_1 = 1.0 - ( ( clk_disable_count_1 ) / ( clk_count_1 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (1) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_2_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_2_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_2_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_2_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_2_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_2_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_2_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_2_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_2_icg_override_to_ungated; +reg nvdla_core_clk_slcg_2_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_2_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_2_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_2_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_2_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_2"); +end +wire assert2slcg_disable_clock_gating_2; +assign assert2slcg_disable_clock_gating_2 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_2) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +always @(negedge assert2slcg_disable_clock_gating_2) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_2"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_2_en; +assign nvdla_core_clk_slcg_2_en = ecore_slcg_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_2_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_2_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_2_end_of_sim_clock_enable + | nvdla_core_clk_slcg_2_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_2 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_2_en), + .clk_gated(nvdla_gated_ecore_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_4_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_4_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_4_internal_nvdla_core_rstn +// Clock signal: testpoint_4_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_4_internal_nvdla_core_clk or negedge testpoint_4_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_4 + if (~testpoint_4_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_4_count_0; + reg testpoint_4_goal_0; + initial testpoint_4_goal_0 = 0; + initial testpoint_4_count_0 = 0; + always@(testpoint_4_count_0) begin + if(testpoint_4_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_4_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1 ::: testpoint_4_goal_0 + testpoint_4_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_4_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_4_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_4 + if (testpoint_4_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b1 ::: testpoint_4_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk) + testpoint_4_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk) begin + `endif + testpoint_4_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_4_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_4_internal_nvdla_core_rstn_with_clock_testpoint_4_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_4_goal_0 (.clk (testpoint_4_internal_nvdla_core_clk), .tp(testpoint_4_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2__1_b1_0 (.clk (testpoint_4_internal_nvdla_core_clk), .tp(testpoint_4_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_5_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_5_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_5_internal_nvdla_core_rstn +// Clock signal: testpoint_5_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_5_internal_nvdla_core_clk or negedge testpoint_5_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_5 + if (~testpoint_5_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_5_count_0; + reg testpoint_5_goal_0; + initial testpoint_5_goal_0 = 0; + initial testpoint_5_count_0 = 0; + always@(testpoint_5_count_0) begin + if(testpoint_5_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_5_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0 ::: testpoint_5_goal_0 + testpoint_5_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_5_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_5_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_5 + if (testpoint_5_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_CORE_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_2 = 1'b0 ::: testpoint_5_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk) + testpoint_5_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk) begin + `endif + testpoint_5_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_5_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_5_internal_nvdla_core_rstn_with_clock_testpoint_5_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_5_goal_0 (.clk (testpoint_5_internal_nvdla_core_clk), .tp(testpoint_5_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2__1_b0_0 (.clk (testpoint_5_internal_nvdla_core_clk), .tp(testpoint_5_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_2___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_2; + reg done_monitor_2; + integer clk_count_2; + integer clk_disable_count_2; + initial begin + clk_count_2 = 0; + clk_disable_count_2 = 0; +// monitor_icg_summary_2 = 0; + done_monitor_2= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_2 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_2 <= 0; + clk_disable_count_2 <= 0; + end else begin + clk_count_2 <= clk_count_2 + 1; + if ( ~(nvdla_core_clk_slcg_2_en) == 1'b1) begin + clk_disable_count_2 <= clk_disable_count_2 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_2 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_2 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (2) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_2, clk_count_2, enabled_percent_2); + $display ("(%0d): INFO: %m (icg_template): ICG (2) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_2, clk_count_2, 1.0 - (1.0 * (clk_disable_count_2) / (clk_count_2))); + done_monitor_2 <= 1; + end + end + end + end + end +////integer enabled_percent_2; +////&Always; +//// if (monitor_icg_summary_2 == 1) begin +//// enabled_percent_2 = 1.0 - ( ( clk_disable_count_2 ) / ( clk_count_2 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (2) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_CORE_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v new file mode 100644 index 0000000..e9275d7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v @@ -0,0 +1,185 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_pack.v +module NV_NVDLA_SDP_CORE_pack ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 512; +parameter OW = 128; +parameter RATIO = IW/OW; +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_pvld; +output inp_prdy; +input [IW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW-1:0] out_data; +reg [IW-1:0] pack_data; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire out_acc; +wire is_pack_last; +reg [OW-1:0] mux_data; +assign out_data = mux_data; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | (pack_prdy & is_pack_last); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_pvld <= 1'b0; + else if (inp_prdy) + pack_pvld <= inp_pvld; +end +assign inp_acc = inp_pvld & inp_prdy; +assign out_acc = out_pvld & out_prdy; +always @(posedge nvdla_core_clk) begin + if (inp_acc) + pack_data <= inp_data; +end +wire [OW*16-1:0] pack_data_ext = {{(OW*16-IW){1'b0}},pack_data}; +reg [3:0] pack_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_cnt <= 4'h0; + else if (out_acc) begin + if (is_pack_last) + pack_cnt <= 4'h0; + else + pack_cnt <= pack_cnt + 1; + end +end +assign is_pack_last = (pack_cnt==RATIO-1); +wire [OW-1:0] pack_seg0 = pack_data_ext[((OW*0) + OW - 1):OW*0]; +wire [OW-1:0] pack_seg1 = pack_data_ext[((OW*1) + OW - 1):OW*1]; +wire [OW-1:0] pack_seg2 = pack_data_ext[((OW*2) + OW - 1):OW*2]; +wire [OW-1:0] pack_seg3 = pack_data_ext[((OW*3) + OW - 1):OW*3]; +wire [OW-1:0] pack_seg4 = pack_data_ext[((OW*4) + OW - 1):OW*4]; +wire [OW-1:0] pack_seg5 = pack_data_ext[((OW*5) + OW - 1):OW*5]; +wire [OW-1:0] pack_seg6 = pack_data_ext[((OW*6) + OW - 1):OW*6]; +wire [OW-1:0] pack_seg7 = pack_data_ext[((OW*7) + OW - 1):OW*7]; +wire [OW-1:0] pack_seg8 = pack_data_ext[((OW*8) + OW - 1):OW*8]; +wire [OW-1:0] pack_seg9 = pack_data_ext[((OW*9) + OW - 1):OW*9]; +wire [OW-1:0] pack_seg10 = pack_data_ext[((OW*10) + OW - 1):OW*10]; +wire [OW-1:0] pack_seg11 = pack_data_ext[((OW*11) + OW - 1):OW*11]; +wire [OW-1:0] pack_seg12 = pack_data_ext[((OW*12) + OW - 1):OW*12]; +wire [OW-1:0] pack_seg13 = pack_data_ext[((OW*13) + OW - 1):OW*13]; +wire [OW-1:0] pack_seg14 = pack_data_ext[((OW*14) + OW - 1):OW*14]; +wire [OW-1:0] pack_seg15 = pack_data_ext[((OW*15) + OW - 1):OW*15]; +generate +if(RATIO == 1) begin +always @( pack_seg0) begin + mux_data = pack_seg0; +end +end +else if(RATIO == 2) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if(RATIO == 4) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 8) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 16) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + or pack_seg8 + or pack_seg9 + or pack_seg10 + or pack_seg11 + or pack_seg12 + or pack_seg13 + or pack_seg14 + or pack_seg15 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + 8: mux_data = pack_seg8; + 9: mux_data = pack_seg9; + 10: mux_data = pack_seg10; + 11: mux_data = pack_seg11; + 12: mux_data = pack_seg12; + 13: mux_data = pack_seg13; + 14: mux_data = pack_seg14; + 15: mux_data = pack_seg15; + default : mux_data = {OW{1'b0}}; + endcase +end +end +endgenerate +endmodule // NV_NVDLA_SDP_CORE_pack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v.vcp new file mode 100644 index 0000000..e9275d7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v.vcp @@ -0,0 +1,185 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_pack.v +module NV_NVDLA_SDP_CORE_pack ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 512; +parameter OW = 128; +parameter RATIO = IW/OW; +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_pvld; +output inp_prdy; +input [IW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW-1:0] out_data; +reg [IW-1:0] pack_data; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire out_acc; +wire is_pack_last; +reg [OW-1:0] mux_data; +assign out_data = mux_data; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | (pack_prdy & is_pack_last); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_pvld <= 1'b0; + else if (inp_prdy) + pack_pvld <= inp_pvld; +end +assign inp_acc = inp_pvld & inp_prdy; +assign out_acc = out_pvld & out_prdy; +always @(posedge nvdla_core_clk) begin + if (inp_acc) + pack_data <= inp_data; +end +wire [OW*16-1:0] pack_data_ext = {{(OW*16-IW){1'b0}},pack_data}; +reg [3:0] pack_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_cnt <= 4'h0; + else if (out_acc) begin + if (is_pack_last) + pack_cnt <= 4'h0; + else + pack_cnt <= pack_cnt + 1; + end +end +assign is_pack_last = (pack_cnt==RATIO-1); +wire [OW-1:0] pack_seg0 = pack_data_ext[((OW*0) + OW - 1):OW*0]; +wire [OW-1:0] pack_seg1 = pack_data_ext[((OW*1) + OW - 1):OW*1]; +wire [OW-1:0] pack_seg2 = pack_data_ext[((OW*2) + OW - 1):OW*2]; +wire [OW-1:0] pack_seg3 = pack_data_ext[((OW*3) + OW - 1):OW*3]; +wire [OW-1:0] pack_seg4 = pack_data_ext[((OW*4) + OW - 1):OW*4]; +wire [OW-1:0] pack_seg5 = pack_data_ext[((OW*5) + OW - 1):OW*5]; +wire [OW-1:0] pack_seg6 = pack_data_ext[((OW*6) + OW - 1):OW*6]; +wire [OW-1:0] pack_seg7 = pack_data_ext[((OW*7) + OW - 1):OW*7]; +wire [OW-1:0] pack_seg8 = pack_data_ext[((OW*8) + OW - 1):OW*8]; +wire [OW-1:0] pack_seg9 = pack_data_ext[((OW*9) + OW - 1):OW*9]; +wire [OW-1:0] pack_seg10 = pack_data_ext[((OW*10) + OW - 1):OW*10]; +wire [OW-1:0] pack_seg11 = pack_data_ext[((OW*11) + OW - 1):OW*11]; +wire [OW-1:0] pack_seg12 = pack_data_ext[((OW*12) + OW - 1):OW*12]; +wire [OW-1:0] pack_seg13 = pack_data_ext[((OW*13) + OW - 1):OW*13]; +wire [OW-1:0] pack_seg14 = pack_data_ext[((OW*14) + OW - 1):OW*14]; +wire [OW-1:0] pack_seg15 = pack_data_ext[((OW*15) + OW - 1):OW*15]; +generate +if(RATIO == 1) begin +always @( pack_seg0) begin + mux_data = pack_seg0; +end +end +else if(RATIO == 2) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if(RATIO == 4) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 8) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 16) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + or pack_seg8 + or pack_seg9 + or pack_seg10 + or pack_seg11 + or pack_seg12 + or pack_seg13 + or pack_seg14 + or pack_seg15 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + 8: mux_data = pack_seg8; + 9: mux_data = pack_seg9; + 10: mux_data = pack_seg10; + 11: mux_data = pack_seg11; + 12: mux_data = pack_seg12; + 13: mux_data = pack_seg13; + 14: mux_data = pack_seg14; + 15: mux_data = pack_seg15; + default : mux_data = {OW{1'b0}}; + endcase +end +end +endgenerate +endmodule // NV_NVDLA_SDP_CORE_pack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v new file mode 100644 index 0000000..0c54651 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v @@ -0,0 +1,150 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_unpack.v +module NV_NVDLA_SDP_CORE_unpack ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 128; +parameter OW = 512; +parameter RATIO = OW/IW; +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_pvld; +output inp_prdy; +input [IW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW-1:0] out_data; +reg [3:0] pack_cnt; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire is_pack_last; +reg [IW-1:0] pack_seg0; +reg [IW-1:0] pack_seg1; +reg [IW-1:0] pack_seg2; +reg [IW-1:0] pack_seg3; +reg [IW-1:0] pack_seg4; +reg [IW-1:0] pack_seg5; +reg [IW-1:0] pack_seg6; +reg [IW-1:0] pack_seg7; +reg [IW-1:0] pack_seg8; +reg [IW-1:0] pack_seg9; +reg [IW-1:0] pack_sega; +reg [IW-1:0] pack_segb; +reg [IW-1:0] pack_segc; +reg [IW-1:0] pack_segd; +reg [IW-1:0] pack_sege; +reg [IW-1:0] pack_segf; +wire [16*IW-1:0] pack_total; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | pack_prdy ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_pvld <= 1'b0; + end + else if ((inp_prdy) == 1'b1) begin + pack_pvld <= inp_pvld & is_pack_last; + end +end +assign inp_acc = inp_pvld & inp_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_cnt <= {4{1'b0}}; + end else begin + if (inp_acc) begin + if (is_pack_last) begin + pack_cnt <= 0; + end else begin + pack_cnt <= pack_cnt + 1; + end + end + end +end +assign is_pack_last = (pack_cnt==RATIO-1); +generate +if(RATIO == 1) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + pack_seg0 <= inp_data; + end +end +assign out_data = pack_seg0; +end +else if(RATIO == 2) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + end +end +assign out_data = {pack_seg1 , pack_seg0}; +end +else if(RATIO == 4) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + end +end +assign out_data = {pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +end +else if (RATIO == 8) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + end +end +assign out_data = {pack_seg7 , pack_seg6 , pack_seg5 , pack_seg4, + pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +end +else if (RATIO == 16) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + if (pack_cnt==4'h8) pack_seg8 <= inp_data; + if (pack_cnt==4'h9) pack_seg9 <= inp_data; + if (pack_cnt==4'ha) pack_sega <= inp_data; + if (pack_cnt==4'hb) pack_segb <= inp_data; + if (pack_cnt==4'hc) pack_segc <= inp_data; + if (pack_cnt==4'hd) pack_segd <= inp_data; + if (pack_cnt==4'he) pack_sege <= inp_data; + if (pack_cnt==4'hf) pack_segf <= inp_data; + end +end +assign out_data = {pack_segf , pack_sege , pack_segd , pack_segc, + pack_segb , pack_sega , pack_seg9 , pack_seg8, + pack_seg7 , pack_seg6 , pack_seg5 , pack_seg4, + pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +end +endgenerate +endmodule // NV_NVDLA_SDP_CORE_unpack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v.vcp new file mode 100644 index 0000000..0c54651 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v.vcp @@ -0,0 +1,150 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_unpack.v +module NV_NVDLA_SDP_CORE_unpack ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 128; +parameter OW = 512; +parameter RATIO = OW/IW; +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_pvld; +output inp_prdy; +input [IW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW-1:0] out_data; +reg [3:0] pack_cnt; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire is_pack_last; +reg [IW-1:0] pack_seg0; +reg [IW-1:0] pack_seg1; +reg [IW-1:0] pack_seg2; +reg [IW-1:0] pack_seg3; +reg [IW-1:0] pack_seg4; +reg [IW-1:0] pack_seg5; +reg [IW-1:0] pack_seg6; +reg [IW-1:0] pack_seg7; +reg [IW-1:0] pack_seg8; +reg [IW-1:0] pack_seg9; +reg [IW-1:0] pack_sega; +reg [IW-1:0] pack_segb; +reg [IW-1:0] pack_segc; +reg [IW-1:0] pack_segd; +reg [IW-1:0] pack_sege; +reg [IW-1:0] pack_segf; +wire [16*IW-1:0] pack_total; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | pack_prdy ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_pvld <= 1'b0; + end + else if ((inp_prdy) == 1'b1) begin + pack_pvld <= inp_pvld & is_pack_last; + end +end +assign inp_acc = inp_pvld & inp_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_cnt <= {4{1'b0}}; + end else begin + if (inp_acc) begin + if (is_pack_last) begin + pack_cnt <= 0; + end else begin + pack_cnt <= pack_cnt + 1; + end + end + end +end +assign is_pack_last = (pack_cnt==RATIO-1); +generate +if(RATIO == 1) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + pack_seg0 <= inp_data; + end +end +assign out_data = pack_seg0; +end +else if(RATIO == 2) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + end +end +assign out_data = {pack_seg1 , pack_seg0}; +end +else if(RATIO == 4) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + end +end +assign out_data = {pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +end +else if (RATIO == 8) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + end +end +assign out_data = {pack_seg7 , pack_seg6 , pack_seg5 , pack_seg4, + pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +end +else if (RATIO == 16) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + if (pack_cnt==4'h8) pack_seg8 <= inp_data; + if (pack_cnt==4'h9) pack_seg9 <= inp_data; + if (pack_cnt==4'ha) pack_sega <= inp_data; + if (pack_cnt==4'hb) pack_segb <= inp_data; + if (pack_cnt==4'hc) pack_segc <= inp_data; + if (pack_cnt==4'hd) pack_segd <= inp_data; + if (pack_cnt==4'he) pack_sege <= inp_data; + if (pack_cnt==4'hf) pack_segf <= inp_data; + end +end +assign out_data = {pack_segf , pack_sege , pack_segd , pack_segc, + pack_segb , pack_sega , pack_seg9 , pack_seg8, + pack_seg7 , pack_seg6 , pack_seg5 , pack_seg4, + pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +end +endgenerate +endmodule // NV_NVDLA_SDP_CORE_unpack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v new file mode 100644 index 0000000..e451bab --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v @@ -0,0 +1,230 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_y.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_CORE_y ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,op_en_load //|< i + ,pwrbus_ram_pd //|< i + ,ew_alu_in_rdy //|> o + ,ew_alu_in_data //|< i + ,ew_alu_in_vld //|< i + ,ew_mul_in_data //|< i + ,ew_mul_in_vld //|< i + ,ew_mul_in_rdy //|> o + ,ew_data_in_pd //|< i + ,ew_data_in_pvld //|< i + ,ew_data_in_prdy //|> o + ,reg2dp_nan_to_zero //|< i + ,reg2dp_perf_lut_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_alu_cvt_bypass //|< i + ,reg2dp_ew_alu_cvt_offset //|< i + ,reg2dp_ew_alu_cvt_scale //|< i + ,reg2dp_ew_alu_cvt_truncate //|< i + ,reg2dp_ew_alu_operand //|< i + ,reg2dp_ew_alu_src //|< i + ,reg2dp_ew_lut_bypass //|< i + ,reg2dp_ew_mul_bypass //|< i + ,reg2dp_ew_mul_cvt_bypass //|< i + ,reg2dp_ew_mul_cvt_offset //|< i + ,reg2dp_ew_mul_cvt_scale //|< i + ,reg2dp_ew_mul_cvt_truncate //|< i + ,reg2dp_ew_mul_operand //|< i + ,reg2dp_ew_mul_prelu //|< i + ,reg2dp_ew_mul_src //|< i + ,reg2dp_ew_truncate //|< i + ,ew_data_out_pd //|> o + ,ew_data_out_pvld //|> o + ,ew_data_out_prdy //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [16*0 -1:0] ew_alu_in_data; +input ew_alu_in_vld; +output ew_alu_in_rdy; +input [32*0 -1:0] ew_data_in_pd; +input ew_data_in_pvld; +output ew_data_in_prdy; +input [16*0 -1:0] ew_mul_in_data; +input ew_mul_in_vld; +output ew_mul_in_rdy; +output [32*0 -1:0] ew_data_out_pd; +output ew_data_out_pvld; +input ew_data_out_prdy; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_alu_cvt_bypass; +input [31:0] reg2dp_ew_alu_cvt_offset; +input [15:0] reg2dp_ew_alu_cvt_scale; +input [5:0] reg2dp_ew_alu_cvt_truncate; +input [31:0] reg2dp_ew_alu_operand; +input reg2dp_ew_alu_src; +input reg2dp_ew_lut_bypass; +input reg2dp_ew_mul_bypass; +input reg2dp_ew_mul_cvt_bypass; +input [31:0] reg2dp_ew_mul_cvt_offset; +input [15:0] reg2dp_ew_mul_cvt_scale; +input [5:0] reg2dp_ew_mul_cvt_truncate; +input [31:0] reg2dp_ew_mul_operand; +input reg2dp_ew_mul_prelu; +input reg2dp_ew_mul_src; +input [9:0] reg2dp_ew_truncate; +input reg2dp_nan_to_zero; +input reg2dp_perf_lut_en; +input [1:0] reg2dp_proc_precision; +//&Ports /^cfg/; +input [31:0] pwrbus_ram_pd; +input op_en_load; +reg [1:0] cfg_ew_alu_algo; +reg cfg_ew_alu_bypass; +reg cfg_ew_alu_cvt_bypass; +reg [31:0] cfg_ew_alu_cvt_offset; +reg [15:0] cfg_ew_alu_cvt_scale; +reg [5:0] cfg_ew_alu_cvt_truncate; +reg [31:0] cfg_ew_alu_operand; +reg cfg_ew_alu_src; +reg cfg_ew_lut_bypass; +reg cfg_ew_mul_bypass; +reg cfg_ew_mul_cvt_bypass; +reg [31:0] cfg_ew_mul_cvt_offset; +reg [15:0] cfg_ew_mul_cvt_scale; +reg [5:0] cfg_ew_mul_cvt_truncate; +reg [31:0] cfg_ew_mul_operand; +reg cfg_ew_mul_prelu; +reg cfg_ew_mul_src; +reg [9:0] cfg_ew_truncate; +reg cfg_nan_to_zero; +reg [1:0] cfg_proc_precision; +wire [32*0 -1:0] alu_cvt_out_pd; +wire alu_cvt_out_prdy; +wire alu_cvt_out_pvld; +wire [32*0 -1:0] mul_cvt_out_pd; +wire mul_cvt_out_prdy; +wire mul_cvt_out_pvld; +wire [32*0 -1:0] core_out_pd; +wire core_out_prdy; +wire core_out_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_proc_precision <= {2{1'b0}}; + cfg_nan_to_zero <= 1'b0; + cfg_ew_alu_operand <= {32{1'b0}}; + cfg_ew_alu_bypass <= 1'b0; + cfg_ew_alu_algo <= {2{1'b0}}; + cfg_ew_alu_src <= 1'b0; + cfg_ew_alu_cvt_bypass <= 1'b0; + cfg_ew_alu_cvt_offset <= {32{1'b0}}; + cfg_ew_alu_cvt_scale <= {16{1'b0}}; + cfg_ew_alu_cvt_truncate <= {6{1'b0}}; + cfg_ew_mul_operand <= {32{1'b0}}; + cfg_ew_mul_bypass <= 1'b0; + cfg_ew_mul_src <= 1'b0; + cfg_ew_mul_cvt_bypass <= 1'b0; + cfg_ew_mul_cvt_offset <= {32{1'b0}}; + cfg_ew_mul_cvt_scale <= {16{1'b0}}; + cfg_ew_mul_cvt_truncate <= {6{1'b0}}; + cfg_ew_truncate <= {10{1'b0}}; + cfg_ew_mul_prelu <= 1'b0; + cfg_ew_lut_bypass <= 1'b1; + end else begin + if (op_en_load) begin + cfg_proc_precision <= reg2dp_proc_precision ; + cfg_nan_to_zero <= reg2dp_nan_to_zero ; + cfg_ew_alu_operand <= reg2dp_ew_alu_operand ; + cfg_ew_alu_bypass <= reg2dp_ew_alu_bypass ; + cfg_ew_alu_algo <= reg2dp_ew_alu_algo ; + cfg_ew_alu_src <= reg2dp_ew_alu_src ; + cfg_ew_alu_cvt_bypass <= reg2dp_ew_alu_cvt_bypass ; + cfg_ew_alu_cvt_offset <= reg2dp_ew_alu_cvt_offset ; + cfg_ew_alu_cvt_scale <= reg2dp_ew_alu_cvt_scale ; + cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate; + cfg_ew_mul_operand <= reg2dp_ew_mul_operand ; + cfg_ew_mul_bypass <= reg2dp_ew_mul_bypass ; + cfg_ew_mul_src <= reg2dp_ew_mul_src ; + cfg_ew_mul_cvt_bypass <= reg2dp_ew_mul_cvt_bypass ; + cfg_ew_mul_cvt_offset <= reg2dp_ew_mul_cvt_offset ; + cfg_ew_mul_cvt_scale <= reg2dp_ew_mul_cvt_scale ; + cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate; + cfg_ew_truncate <= reg2dp_ew_truncate ; + cfg_ew_mul_prelu <= reg2dp_ew_mul_prelu ; + cfg_ew_lut_bypass <= 1'b1; + end + end +end +//=========================================== +// y input pipe +//=========================================== +//================================================= +NV_NVDLA_SDP_HLS_Y_cvt_top u_alu_cvt ( + .cfg_cvt_bypass (cfg_ew_alu_cvt_bypass) //|< r + ,.cfg_cvt_offset (cfg_ew_alu_cvt_offset[31:0]) //|< r + ,.cfg_cvt_scale (cfg_ew_alu_cvt_scale[15:0]) //|< r + ,.cfg_cvt_truncate (cfg_ew_alu_cvt_truncate[5:0]) //|< r + ,.cvt_data_in (ew_alu_in_data[16*0 -1:0]) //|< w + ,.cvt_in_pvld (ew_alu_in_vld) //|< w + ,.cvt_in_prdy (ew_alu_in_rdy) //|> w + ,.cvt_out_prdy (alu_cvt_out_prdy) //|< w + ,.cvt_data_out (alu_cvt_out_pd[32*0 -1:0]) //|> w + ,.cvt_out_pvld (alu_cvt_out_pvld) //|> w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +NV_NVDLA_SDP_HLS_Y_cvt_top u_mul_cvt ( + .cfg_cvt_bypass (cfg_ew_mul_cvt_bypass) //|< r + ,.cfg_cvt_offset (cfg_ew_mul_cvt_offset[31:0]) //|< r + ,.cfg_cvt_scale (cfg_ew_mul_cvt_scale[15:0]) //|< r + ,.cfg_cvt_truncate (cfg_ew_mul_cvt_truncate[5:0]) //|< r + ,.cvt_data_in (ew_mul_in_data[16*0 -1:0]) //|< w + ,.cvt_in_pvld (ew_mul_in_vld) //|< w + ,.cvt_in_prdy (ew_mul_in_rdy) //|> w + ,.cvt_out_prdy (mul_cvt_out_prdy) //|< w + ,.cvt_data_out (mul_cvt_out_pd[32*0 -1:0]) //|> w + ,.cvt_out_pvld (mul_cvt_out_pvld) //|> w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +NV_NVDLA_SDP_HLS_Y_int_core u_core ( + .cfg_alu_algo (cfg_ew_alu_algo[1:0]) //|< r + ,.cfg_alu_bypass (cfg_ew_alu_bypass) //|< r + ,.cfg_alu_op (cfg_ew_alu_operand[31:0]) //|< r + ,.cfg_alu_src (cfg_ew_alu_src) //|< r + ,.cfg_mul_bypass (cfg_ew_mul_bypass) //|< r + ,.cfg_mul_op (cfg_ew_mul_operand[31:0]) //|< r + ,.cfg_mul_prelu (cfg_ew_mul_prelu) //|< r + ,.cfg_mul_src (cfg_ew_mul_src) //|< r + ,.cfg_mul_truncate (cfg_ew_truncate[9:0]) //|< r + ,.chn_alu_op (alu_cvt_out_pd[32*0 -1:0]) //|< w + ,.chn_alu_op_pvld (alu_cvt_out_pvld) //|< w + ,.chn_data_in (ew_data_in_pd[32*0 -1:0]) //|< w + ,.chn_in_pvld (ew_data_in_pvld) //|< w + ,.chn_in_prdy (ew_data_in_prdy) //|> w + ,.chn_mul_op (mul_cvt_out_pd[32*0 -1:0]) //|< w + ,.chn_mul_op_pvld (mul_cvt_out_pvld) //|< w + ,.chn_alu_op_prdy (alu_cvt_out_prdy) //|> w + ,.chn_mul_op_prdy (mul_cvt_out_prdy) //|> w + ,.chn_data_out (core_out_pd[32*0 -1:0]) //|> w + ,.chn_out_pvld (core_out_pvld) //|> w + ,.chn_out_prdy (core_out_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +assign core_out_prdy = ew_data_out_prdy; +assign ew_data_out_pvld = core_out_pvld; +assign ew_data_out_pd = core_out_pd; +endmodule // NV_NVDLA_SDP_CORE_y diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v.vcp new file mode 100644 index 0000000..e451bab --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v.vcp @@ -0,0 +1,230 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_CORE_y.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_CORE_y ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,op_en_load //|< i + ,pwrbus_ram_pd //|< i + ,ew_alu_in_rdy //|> o + ,ew_alu_in_data //|< i + ,ew_alu_in_vld //|< i + ,ew_mul_in_data //|< i + ,ew_mul_in_vld //|< i + ,ew_mul_in_rdy //|> o + ,ew_data_in_pd //|< i + ,ew_data_in_pvld //|< i + ,ew_data_in_prdy //|> o + ,reg2dp_nan_to_zero //|< i + ,reg2dp_perf_lut_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_alu_cvt_bypass //|< i + ,reg2dp_ew_alu_cvt_offset //|< i + ,reg2dp_ew_alu_cvt_scale //|< i + ,reg2dp_ew_alu_cvt_truncate //|< i + ,reg2dp_ew_alu_operand //|< i + ,reg2dp_ew_alu_src //|< i + ,reg2dp_ew_lut_bypass //|< i + ,reg2dp_ew_mul_bypass //|< i + ,reg2dp_ew_mul_cvt_bypass //|< i + ,reg2dp_ew_mul_cvt_offset //|< i + ,reg2dp_ew_mul_cvt_scale //|< i + ,reg2dp_ew_mul_cvt_truncate //|< i + ,reg2dp_ew_mul_operand //|< i + ,reg2dp_ew_mul_prelu //|< i + ,reg2dp_ew_mul_src //|< i + ,reg2dp_ew_truncate //|< i + ,ew_data_out_pd //|> o + ,ew_data_out_pvld //|> o + ,ew_data_out_prdy //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [16*0 -1:0] ew_alu_in_data; +input ew_alu_in_vld; +output ew_alu_in_rdy; +input [32*0 -1:0] ew_data_in_pd; +input ew_data_in_pvld; +output ew_data_in_prdy; +input [16*0 -1:0] ew_mul_in_data; +input ew_mul_in_vld; +output ew_mul_in_rdy; +output [32*0 -1:0] ew_data_out_pd; +output ew_data_out_pvld; +input ew_data_out_prdy; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_alu_cvt_bypass; +input [31:0] reg2dp_ew_alu_cvt_offset; +input [15:0] reg2dp_ew_alu_cvt_scale; +input [5:0] reg2dp_ew_alu_cvt_truncate; +input [31:0] reg2dp_ew_alu_operand; +input reg2dp_ew_alu_src; +input reg2dp_ew_lut_bypass; +input reg2dp_ew_mul_bypass; +input reg2dp_ew_mul_cvt_bypass; +input [31:0] reg2dp_ew_mul_cvt_offset; +input [15:0] reg2dp_ew_mul_cvt_scale; +input [5:0] reg2dp_ew_mul_cvt_truncate; +input [31:0] reg2dp_ew_mul_operand; +input reg2dp_ew_mul_prelu; +input reg2dp_ew_mul_src; +input [9:0] reg2dp_ew_truncate; +input reg2dp_nan_to_zero; +input reg2dp_perf_lut_en; +input [1:0] reg2dp_proc_precision; +//&Ports /^cfg/; +input [31:0] pwrbus_ram_pd; +input op_en_load; +reg [1:0] cfg_ew_alu_algo; +reg cfg_ew_alu_bypass; +reg cfg_ew_alu_cvt_bypass; +reg [31:0] cfg_ew_alu_cvt_offset; +reg [15:0] cfg_ew_alu_cvt_scale; +reg [5:0] cfg_ew_alu_cvt_truncate; +reg [31:0] cfg_ew_alu_operand; +reg cfg_ew_alu_src; +reg cfg_ew_lut_bypass; +reg cfg_ew_mul_bypass; +reg cfg_ew_mul_cvt_bypass; +reg [31:0] cfg_ew_mul_cvt_offset; +reg [15:0] cfg_ew_mul_cvt_scale; +reg [5:0] cfg_ew_mul_cvt_truncate; +reg [31:0] cfg_ew_mul_operand; +reg cfg_ew_mul_prelu; +reg cfg_ew_mul_src; +reg [9:0] cfg_ew_truncate; +reg cfg_nan_to_zero; +reg [1:0] cfg_proc_precision; +wire [32*0 -1:0] alu_cvt_out_pd; +wire alu_cvt_out_prdy; +wire alu_cvt_out_pvld; +wire [32*0 -1:0] mul_cvt_out_pd; +wire mul_cvt_out_prdy; +wire mul_cvt_out_pvld; +wire [32*0 -1:0] core_out_pd; +wire core_out_prdy; +wire core_out_pvld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_proc_precision <= {2{1'b0}}; + cfg_nan_to_zero <= 1'b0; + cfg_ew_alu_operand <= {32{1'b0}}; + cfg_ew_alu_bypass <= 1'b0; + cfg_ew_alu_algo <= {2{1'b0}}; + cfg_ew_alu_src <= 1'b0; + cfg_ew_alu_cvt_bypass <= 1'b0; + cfg_ew_alu_cvt_offset <= {32{1'b0}}; + cfg_ew_alu_cvt_scale <= {16{1'b0}}; + cfg_ew_alu_cvt_truncate <= {6{1'b0}}; + cfg_ew_mul_operand <= {32{1'b0}}; + cfg_ew_mul_bypass <= 1'b0; + cfg_ew_mul_src <= 1'b0; + cfg_ew_mul_cvt_bypass <= 1'b0; + cfg_ew_mul_cvt_offset <= {32{1'b0}}; + cfg_ew_mul_cvt_scale <= {16{1'b0}}; + cfg_ew_mul_cvt_truncate <= {6{1'b0}}; + cfg_ew_truncate <= {10{1'b0}}; + cfg_ew_mul_prelu <= 1'b0; + cfg_ew_lut_bypass <= 1'b1; + end else begin + if (op_en_load) begin + cfg_proc_precision <= reg2dp_proc_precision ; + cfg_nan_to_zero <= reg2dp_nan_to_zero ; + cfg_ew_alu_operand <= reg2dp_ew_alu_operand ; + cfg_ew_alu_bypass <= reg2dp_ew_alu_bypass ; + cfg_ew_alu_algo <= reg2dp_ew_alu_algo ; + cfg_ew_alu_src <= reg2dp_ew_alu_src ; + cfg_ew_alu_cvt_bypass <= reg2dp_ew_alu_cvt_bypass ; + cfg_ew_alu_cvt_offset <= reg2dp_ew_alu_cvt_offset ; + cfg_ew_alu_cvt_scale <= reg2dp_ew_alu_cvt_scale ; + cfg_ew_alu_cvt_truncate <= reg2dp_ew_alu_cvt_truncate; + cfg_ew_mul_operand <= reg2dp_ew_mul_operand ; + cfg_ew_mul_bypass <= reg2dp_ew_mul_bypass ; + cfg_ew_mul_src <= reg2dp_ew_mul_src ; + cfg_ew_mul_cvt_bypass <= reg2dp_ew_mul_cvt_bypass ; + cfg_ew_mul_cvt_offset <= reg2dp_ew_mul_cvt_offset ; + cfg_ew_mul_cvt_scale <= reg2dp_ew_mul_cvt_scale ; + cfg_ew_mul_cvt_truncate <= reg2dp_ew_mul_cvt_truncate; + cfg_ew_truncate <= reg2dp_ew_truncate ; + cfg_ew_mul_prelu <= reg2dp_ew_mul_prelu ; + cfg_ew_lut_bypass <= 1'b1; + end + end +end +//=========================================== +// y input pipe +//=========================================== +//================================================= +NV_NVDLA_SDP_HLS_Y_cvt_top u_alu_cvt ( + .cfg_cvt_bypass (cfg_ew_alu_cvt_bypass) //|< r + ,.cfg_cvt_offset (cfg_ew_alu_cvt_offset[31:0]) //|< r + ,.cfg_cvt_scale (cfg_ew_alu_cvt_scale[15:0]) //|< r + ,.cfg_cvt_truncate (cfg_ew_alu_cvt_truncate[5:0]) //|< r + ,.cvt_data_in (ew_alu_in_data[16*0 -1:0]) //|< w + ,.cvt_in_pvld (ew_alu_in_vld) //|< w + ,.cvt_in_prdy (ew_alu_in_rdy) //|> w + ,.cvt_out_prdy (alu_cvt_out_prdy) //|< w + ,.cvt_data_out (alu_cvt_out_pd[32*0 -1:0]) //|> w + ,.cvt_out_pvld (alu_cvt_out_pvld) //|> w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +NV_NVDLA_SDP_HLS_Y_cvt_top u_mul_cvt ( + .cfg_cvt_bypass (cfg_ew_mul_cvt_bypass) //|< r + ,.cfg_cvt_offset (cfg_ew_mul_cvt_offset[31:0]) //|< r + ,.cfg_cvt_scale (cfg_ew_mul_cvt_scale[15:0]) //|< r + ,.cfg_cvt_truncate (cfg_ew_mul_cvt_truncate[5:0]) //|< r + ,.cvt_data_in (ew_mul_in_data[16*0 -1:0]) //|< w + ,.cvt_in_pvld (ew_mul_in_vld) //|< w + ,.cvt_in_prdy (ew_mul_in_rdy) //|> w + ,.cvt_out_prdy (mul_cvt_out_prdy) //|< w + ,.cvt_data_out (mul_cvt_out_pd[32*0 -1:0]) //|> w + ,.cvt_out_pvld (mul_cvt_out_pvld) //|> w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +NV_NVDLA_SDP_HLS_Y_int_core u_core ( + .cfg_alu_algo (cfg_ew_alu_algo[1:0]) //|< r + ,.cfg_alu_bypass (cfg_ew_alu_bypass) //|< r + ,.cfg_alu_op (cfg_ew_alu_operand[31:0]) //|< r + ,.cfg_alu_src (cfg_ew_alu_src) //|< r + ,.cfg_mul_bypass (cfg_ew_mul_bypass) //|< r + ,.cfg_mul_op (cfg_ew_mul_operand[31:0]) //|< r + ,.cfg_mul_prelu (cfg_ew_mul_prelu) //|< r + ,.cfg_mul_src (cfg_ew_mul_src) //|< r + ,.cfg_mul_truncate (cfg_ew_truncate[9:0]) //|< r + ,.chn_alu_op (alu_cvt_out_pd[32*0 -1:0]) //|< w + ,.chn_alu_op_pvld (alu_cvt_out_pvld) //|< w + ,.chn_data_in (ew_data_in_pd[32*0 -1:0]) //|< w + ,.chn_in_pvld (ew_data_in_pvld) //|< w + ,.chn_in_prdy (ew_data_in_prdy) //|> w + ,.chn_mul_op (mul_cvt_out_pd[32*0 -1:0]) //|< w + ,.chn_mul_op_pvld (mul_cvt_out_pvld) //|< w + ,.chn_alu_op_prdy (alu_cvt_out_prdy) //|> w + ,.chn_mul_op_prdy (mul_cvt_out_prdy) //|> w + ,.chn_data_out (core_out_pd[32*0 -1:0]) //|> w + ,.chn_out_pvld (core_out_pvld) //|> w + ,.chn_out_prdy (core_out_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +assign core_out_prdy = ew_data_out_prdy; +assign ew_data_out_pvld = core_out_pvld; +assign ew_data_out_pd = core_out_pd; +endmodule // NV_NVDLA_SDP_CORE_y diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v new file mode 100644 index 0000000..c20c695 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_ERDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_ERDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [15:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [15:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] ig2cq_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 7'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [6:0] ig2cq_adr; // current write address +wire [6:0] cq2eg_adr_p; // read address to use for ram +wire [15:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x16 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (ig2cq_adr == 7'd79) ? 7'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] cq2eg_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (cq2eg_adr == 7'd79) ? 7'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [6:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 7'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_cq_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_ERDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_ERDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_ERDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v.vcp new file mode 100644 index 0000000..c20c695 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_cq.v.vcp @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_ERDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_ERDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [15:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [15:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] ig2cq_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 7'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [6:0] ig2cq_adr; // current write address +wire [6:0] cq2eg_adr_p; // read address to use for ram +wire [15:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x16 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (ig2cq_adr == 7'd79) ? 7'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] cq2eg_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (cq2eg_adr == 7'd79) ? 7'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [6:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 7'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_cq_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_ERDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_ERDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_ERDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v new file mode 100644 index 0000000..0922325 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_ERDMA_gate.v +module NV_NVDLA_SDP_ERDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,dla_clk_ovr_on_sync + ,erdma_disable + ,erdma_slcg_op_en + ,global_clk_ovr_on_sync + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dla_clk_ovr_on_sync; +input erdma_disable; +input erdma_slcg_op_en; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg erdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when ERDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + erdma_enable <= 1'b0; + end else begin + erdma_enable <= !erdma_disable; + end +end +assign cfg_clk_en = erdma_slcg_op_en & erdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_ERDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v.vcp new file mode 100644 index 0000000..0922325 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_gate.v.vcp @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_ERDMA_gate.v +module NV_NVDLA_SDP_ERDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,dla_clk_ovr_on_sync + ,erdma_disable + ,erdma_slcg_op_en + ,global_clk_ovr_on_sync + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dla_clk_ovr_on_sync; +input erdma_disable; +input erdma_slcg_op_en; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg erdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when ERDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + erdma_enable <= 1'b0; + end else begin + erdma_enable <= !erdma_disable; + end +end +assign cfg_clk_en = erdma_slcg_op_en & erdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_ERDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_ERDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_lat_fifo.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_lat_fifo.v new file mode 100644 index 0000000..b979aa3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_lat_fifo.v @@ -0,0 +1,606 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_ERDMA_lat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_ERDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] lat_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 7'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [6:0] lat_wr_adr; // current write address +wire [6:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (lat_wr_adr == 7'd79) ? 7'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] lat_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (lat_rd_adr == 7'd79) ? 7'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [6:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 7'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_ERDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_ERDMA_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_lat_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_lat_fifo.v.vcp new file mode 100644 index 0000000..b979aa3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_ERDMA_lat_fifo.v.vcp @@ -0,0 +1,606 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_ERDMA_lat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_ERDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] lat_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 7'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [6:0] lat_wr_adr; // current write address +wire [6:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (lat_wr_adr == 7'd79) ? 7'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] lat_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (lat_rd_adr == 7'd79) ? 7'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [6:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 7'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_ERDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst2(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst3(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_ERDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed2; +reg prand_initialized2; +reg prand_no_rollpli2; +`endif +`endif +`endif +function [31:0] prand_inst2; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst2 = min; +`else +`ifdef SYNTHESIS + prand_inst2 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized2 !== 1'b1) begin + prand_no_rollpli2 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli2) + prand_local_seed2 = {$prand_get_seed(2), 16'b0}; + prand_initialized2 = 1'b1; + end + if (prand_no_rollpli2) begin + prand_inst2 = min; + end else begin + diff = max - min + 1; + prand_inst2 = min + prand_local_seed2[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed2 = prand_local_seed2 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst2 = min; +`else + prand_inst2 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed3; +reg prand_initialized3; +reg prand_no_rollpli3; +`endif +`endif +`endif +function [31:0] prand_inst3; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst3 = min; +`else +`ifdef SYNTHESIS + prand_inst3 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized3 !== 1'b1) begin + prand_no_rollpli3 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli3) + prand_local_seed3 = {$prand_get_seed(3), 16'b0}; + prand_initialized3 = 1'b1; + end + if (prand_no_rollpli3) begin + prand_inst3 = min; + end else begin + diff = max - min + 1; + prand_inst3 = min + prand_local_seed3[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed3 = prand_local_seed3 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst3 = min; +`else + prand_inst3 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_ERDMA_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_C_int.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_C_int.v new file mode 100644 index 0000000..c377b47 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_C_int.v @@ -0,0 +1,995 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_C_int.v +module NV_NVDLA_SDP_HLS_C_int ( + cfg_mode_eql //|< i + ,cfg_offset //|< i + ,cfg_out_precision //|< i + ,cfg_scale //|< i + ,cfg_truncate //|< i + ,cvt_data_in //|< i + ,cvt_in_pvld //|< i + ,cvt_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt_data_out //|> o + ,cvt_in_prdy //|> o + ,cvt_out_pvld //|> o + ,cvt_sat_out //|> o + ); +input cfg_mode_eql; +input [31:0] cfg_offset; +input [1:0] cfg_out_precision; +input [15:0] cfg_scale; +input [5:0] cfg_truncate; +input [31:0] cvt_data_in; +input cvt_in_pvld; +input cvt_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [15:0] cvt_data_out; +output cvt_in_prdy; +output cvt_out_pvld; +output cvt_sat_out; +/* +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] cfg_out_precision; +input [C_ALU_OP_WIDTH-1:0] cfg_offset; +input [C_MUL_OP_WIDTH-1:0] cfg_scale; +input [C_TRU_WIDTH-1:0] cfg_truncate; +input [C_IN_WIDTH-1:0] cvt_data_in; +output [C_OUT_WIDTH-1:0] cvt_data_out; +input cvt_in_pvld; +output cvt_in_prdy; +input cvt_out_prdy; +output cvt_out_pvld; +*/ +wire [31:0] cfg_offset_mux; +wire [15:0] cfg_scale_mux; +wire [31:0] cvt_data_mux; +wire [15:0] cvt_dout; +wire cvt_sat; +wire [15:0] dout_int16_sat; +wire [7:0] dout_int8_sat; +wire final_out_prdy; +wire final_out_pvld; +wire [48:0] mul_data_out; +wire [48:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire sat_dout; +wire sat_out; +wire [32:0] sub_data_out; +wire [32:0] sub_dout; +wire sub_in_prdy; +wire sub_in_pvld; +wire sub_out_prdy; +wire sub_out_pvld; +wire [16:0] tru_dout; +wire [16:0] tru_out; +wire tru_out_prdy; +wire tru_out_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign cvt_data_mux[31:0] = cfg_mode_eql ? {32 {1'b0}} : cvt_data_in[31:0]; +assign cfg_offset_mux[31:0] = cfg_mode_eql ? {32 {1'b0}} : cfg_offset[31:0]; +assign cfg_scale_mux[15:0] = cfg_mode_eql ? {16 {1'b0}} : cfg_scale[15:0]; +//sub +assign sub_dout[32:0] = $signed(cvt_data_mux[31:0]) -$signed(cfg_offset_mux[31:0]); +//assign sub_mux[::range(C_ALU_OUT_WIDTH)] = cfg_mode_eql ? {{(C_ALU_OUT_WIDTH-C_IN_WIDTH){1'b0}},cvt_data_in[::range(C_IN_WIDTH)]} : sub_dout[::range(C_ALU_OUT_WIDTH)]; +NV_NVDLA_SDP_HLS_C_INT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sub_dout (sub_dout[32:0]) //|< w + ,.sub_in_pvld (sub_in_pvld) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.sub_data_out (sub_data_out[32:0]) //|> w + ,.sub_in_prdy (sub_in_prdy) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[48:0] = $signed(sub_data_out[32:0]) * $signed(cfg_scale_mux[15:0]); +//assign mul_mux[::range(C_MUL_OUT_WIDTH)] = cfg_mode_eql ? {{(C_MUL_OUT_WIDTH-C_IN_WIDTH){1'b0}},sub_data_out[::range(C_IN_WIDTH)]} : mul_dout[::range(C_MUL_OUT_WIDTH)]; +NV_NVDLA_SDP_HLS_C_INT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[48:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[48:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(49 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(6 )) c_shiftrightsat_su ( + .data_in (mul_data_out[48:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_dout[16:0]) //|> w + ,.sat_out (sat_dout) //|> w + ); +//signed +//unsigned +NV_NVDLA_SDP_HLS_C_INT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.sat_dout (sat_dout) //|< w + ,.tru_dout (tru_dout[16:0]) //|< w + ,.tru_out_prdy (tru_out_prdy) //|< w + ,.mul_out_prdy (mul_out_prdy) //|> w + ,.sat_out (sat_out) //|> w + ,.tru_out (tru_out[16:0]) //|> w + ,.tru_out_pvld (tru_out_pvld) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(16 )) c_saturate_int16 ( + .data_in (tru_out[16:0]) //|< w + ,.data_out (dout_int16_sat[15:0]) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(8 )) c_saturate_int8 ( + .data_in (tru_out[16:0]) //|< w + ,.data_out (dout_int8_sat[7:0]) //|> w + ); +assign sub_in_pvld = cfg_mode_eql ? 1'b0 : cvt_in_pvld; +assign cvt_in_prdy = cfg_mode_eql ? final_out_prdy : sub_in_prdy; +assign tru_out_prdy = cfg_mode_eql ? 1'b1 : final_out_prdy; +assign final_out_pvld = cfg_mode_eql ? cvt_in_pvld : tru_out_pvld; +assign cvt_dout = cfg_mode_eql ? cvt_data_in[15:0] : + (cfg_out_precision[1:0] == 1 ) ? dout_int16_sat[15:0] : {{(16 - 8 ){dout_int8_sat[8 -1]}},dout_int8_sat[7:0]}; +assign cvt_sat = cfg_mode_eql ? 1'b0 : sat_out; +NV_NVDLA_SDP_HLS_C_INT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_dout (cvt_dout[15:0]) //|< w + ,.cvt_out_prdy (cvt_out_prdy) //|< i + ,.cvt_sat (cvt_sat) //|< w + ,.final_out_pvld (final_out_pvld) //|< w + ,.cvt_data_out (cvt_data_out[15:0]) //|> o + ,.cvt_out_pvld (cvt_out_pvld) //|> o + ,.cvt_sat_out (cvt_sat_out) //|> o + ,.final_out_prdy (final_out_prdy) //|> w + ); +endmodule // NV_NVDLA_SDP_HLS_C_int +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[32:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[32:0] (sub_in_pvld,sub_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sub_dout + ,sub_in_pvld + ,sub_out_prdy + ,sub_data_out + ,sub_in_prdy + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] sub_dout; +input sub_in_pvld; +input sub_out_prdy; +output [32:0] sub_data_out; +output sub_in_prdy; +output sub_out_pvld; +reg [32:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32:0] p1_skid_data; +reg [32:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [32:0] sub_data_out; +reg sub_in_prdy; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + sub_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = sub_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + sub_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + sub_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or sub_in_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? sub_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[32:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^sub_in_pvld^sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (sub_in_pvld && !sub_in_prdy), (sub_in_pvld), (sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[48:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[48:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [48:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [48:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [48:0] mul_data_out; +reg mul_out_pvld; +reg [48:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [48:0] p2_skid_data; +reg [48:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[48:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sat_out,tru_out[16:0]} (tru_out_pvld,tru_out_prdy) <= {sat_dout,tru_dout[16:0]} (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,sat_dout + ,tru_dout + ,tru_out_prdy + ,mul_out_prdy + ,sat_out + ,tru_out + ,tru_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input sat_dout; +input [16:0] tru_dout; +input tru_out_prdy; +output mul_out_prdy; +output sat_out; +output [16:0] tru_out; +output tru_out_pvld; +reg mul_out_prdy; +reg [17:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [17:0] p3_skid_data; +reg [17:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg sat_out; +reg [16:0] tru_out; +reg tru_out_pvld; +//## pipe (3) skid buffer +always @( + mul_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {sat_dout,tru_dout[16:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_out_pvld + or p3_skid_valid + or sat_dout + or tru_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {sat_dout,tru_dout[16:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tru_out_prdy + or p3_pipe_data + ) begin + tru_out_pvld = p3_pipe_valid; + p3_pipe_ready = tru_out_prdy; + {sat_out,tru_out[16:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_out_pvld^tru_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {cvt_sat_out,cvt_data_out[15:0]} (cvt_out_pvld,cvt_out_prdy) <= {cvt_sat,cvt_dout[15:0]} (final_out_pvld,final_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvt_dout + ,cvt_out_prdy + ,cvt_sat + ,final_out_pvld + ,cvt_data_out + ,cvt_out_pvld + ,cvt_sat_out + ,final_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [15:0] cvt_dout; +input cvt_out_prdy; +input cvt_sat; +input final_out_pvld; +output [15:0] cvt_data_out; +output cvt_out_pvld; +output cvt_sat_out; +output final_out_prdy; +reg [15:0] cvt_data_out; +reg cvt_out_pvld; +reg cvt_sat_out; +reg final_out_prdy; +reg [16:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [16:0] p4_skid_data; +reg [16:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + final_out_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = final_out_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + final_out_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + final_out_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? {cvt_sat,cvt_dout[15:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or final_out_pvld + or p4_skid_valid + or cvt_sat + or cvt_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? final_out_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? {cvt_sat,cvt_dout[15:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or cvt_out_prdy + or p4_pipe_data + ) begin + cvt_out_pvld = p4_pipe_valid; + p4_pipe_ready = cvt_out_prdy; + {cvt_sat_out,cvt_data_out[15:0]} = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvt_out_pvld^cvt_out_prdy^final_out_pvld^final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (final_out_pvld && !final_out_prdy), (final_out_pvld), (final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_C_int.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_C_int.v.vcp new file mode 100644 index 0000000..c377b47 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_C_int.v.vcp @@ -0,0 +1,995 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_C_int.v +module NV_NVDLA_SDP_HLS_C_int ( + cfg_mode_eql //|< i + ,cfg_offset //|< i + ,cfg_out_precision //|< i + ,cfg_scale //|< i + ,cfg_truncate //|< i + ,cvt_data_in //|< i + ,cvt_in_pvld //|< i + ,cvt_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt_data_out //|> o + ,cvt_in_prdy //|> o + ,cvt_out_pvld //|> o + ,cvt_sat_out //|> o + ); +input cfg_mode_eql; +input [31:0] cfg_offset; +input [1:0] cfg_out_precision; +input [15:0] cfg_scale; +input [5:0] cfg_truncate; +input [31:0] cvt_data_in; +input cvt_in_pvld; +input cvt_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [15:0] cvt_data_out; +output cvt_in_prdy; +output cvt_out_pvld; +output cvt_sat_out; +/* +input nvdla_core_clk; +input nvdla_core_rstn; +input [1:0] cfg_out_precision; +input [C_ALU_OP_WIDTH-1:0] cfg_offset; +input [C_MUL_OP_WIDTH-1:0] cfg_scale; +input [C_TRU_WIDTH-1:0] cfg_truncate; +input [C_IN_WIDTH-1:0] cvt_data_in; +output [C_OUT_WIDTH-1:0] cvt_data_out; +input cvt_in_pvld; +output cvt_in_prdy; +input cvt_out_prdy; +output cvt_out_pvld; +*/ +wire [31:0] cfg_offset_mux; +wire [15:0] cfg_scale_mux; +wire [31:0] cvt_data_mux; +wire [15:0] cvt_dout; +wire cvt_sat; +wire [15:0] dout_int16_sat; +wire [7:0] dout_int8_sat; +wire final_out_prdy; +wire final_out_pvld; +wire [48:0] mul_data_out; +wire [48:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire sat_dout; +wire sat_out; +wire [32:0] sub_data_out; +wire [32:0] sub_dout; +wire sub_in_prdy; +wire sub_in_pvld; +wire sub_out_prdy; +wire sub_out_pvld; +wire [16:0] tru_dout; +wire [16:0] tru_out; +wire tru_out_prdy; +wire tru_out_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign cvt_data_mux[31:0] = cfg_mode_eql ? {32 {1'b0}} : cvt_data_in[31:0]; +assign cfg_offset_mux[31:0] = cfg_mode_eql ? {32 {1'b0}} : cfg_offset[31:0]; +assign cfg_scale_mux[15:0] = cfg_mode_eql ? {16 {1'b0}} : cfg_scale[15:0]; +//sub +assign sub_dout[32:0] = $signed(cvt_data_mux[31:0]) -$signed(cfg_offset_mux[31:0]); +//assign sub_mux[::range(C_ALU_OUT_WIDTH)] = cfg_mode_eql ? {{(C_ALU_OUT_WIDTH-C_IN_WIDTH){1'b0}},cvt_data_in[::range(C_IN_WIDTH)]} : sub_dout[::range(C_ALU_OUT_WIDTH)]; +NV_NVDLA_SDP_HLS_C_INT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sub_dout (sub_dout[32:0]) //|< w + ,.sub_in_pvld (sub_in_pvld) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.sub_data_out (sub_data_out[32:0]) //|> w + ,.sub_in_prdy (sub_in_prdy) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[48:0] = $signed(sub_data_out[32:0]) * $signed(cfg_scale_mux[15:0]); +//assign mul_mux[::range(C_MUL_OUT_WIDTH)] = cfg_mode_eql ? {{(C_MUL_OUT_WIDTH-C_IN_WIDTH){1'b0}},sub_data_out[::range(C_IN_WIDTH)]} : mul_dout[::range(C_MUL_OUT_WIDTH)]; +NV_NVDLA_SDP_HLS_C_INT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[48:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[48:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(49 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(6 )) c_shiftrightsat_su ( + .data_in (mul_data_out[48:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_dout[16:0]) //|> w + ,.sat_out (sat_dout) //|> w + ); +//signed +//unsigned +NV_NVDLA_SDP_HLS_C_INT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.sat_dout (sat_dout) //|< w + ,.tru_dout (tru_dout[16:0]) //|< w + ,.tru_out_prdy (tru_out_prdy) //|< w + ,.mul_out_prdy (mul_out_prdy) //|> w + ,.sat_out (sat_out) //|> w + ,.tru_out (tru_out[16:0]) //|> w + ,.tru_out_pvld (tru_out_pvld) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(16 )) c_saturate_int16 ( + .data_in (tru_out[16:0]) //|< w + ,.data_out (dout_int16_sat[15:0]) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(17 ),.OUT_WIDTH(8 )) c_saturate_int8 ( + .data_in (tru_out[16:0]) //|< w + ,.data_out (dout_int8_sat[7:0]) //|> w + ); +assign sub_in_pvld = cfg_mode_eql ? 1'b0 : cvt_in_pvld; +assign cvt_in_prdy = cfg_mode_eql ? final_out_prdy : sub_in_prdy; +assign tru_out_prdy = cfg_mode_eql ? 1'b1 : final_out_prdy; +assign final_out_pvld = cfg_mode_eql ? cvt_in_pvld : tru_out_pvld; +assign cvt_dout = cfg_mode_eql ? cvt_data_in[15:0] : + (cfg_out_precision[1:0] == 1 ) ? dout_int16_sat[15:0] : {{(16 - 8 ){dout_int8_sat[8 -1]}},dout_int8_sat[7:0]}; +assign cvt_sat = cfg_mode_eql ? 1'b0 : sat_out; +NV_NVDLA_SDP_HLS_C_INT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_dout (cvt_dout[15:0]) //|< w + ,.cvt_out_prdy (cvt_out_prdy) //|< i + ,.cvt_sat (cvt_sat) //|< w + ,.final_out_pvld (final_out_pvld) //|< w + ,.cvt_data_out (cvt_data_out[15:0]) //|> o + ,.cvt_out_pvld (cvt_out_pvld) //|> o + ,.cvt_sat_out (cvt_sat_out) //|> o + ,.final_out_prdy (final_out_prdy) //|> w + ); +endmodule // NV_NVDLA_SDP_HLS_C_int +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[32:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[32:0] (sub_in_pvld,sub_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sub_dout + ,sub_in_pvld + ,sub_out_prdy + ,sub_data_out + ,sub_in_prdy + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] sub_dout; +input sub_in_pvld; +input sub_out_prdy; +output [32:0] sub_data_out; +output sub_in_prdy; +output sub_out_pvld; +reg [32:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32:0] p1_skid_data; +reg [32:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [32:0] sub_data_out; +reg sub_in_prdy; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + sub_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = sub_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + sub_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + sub_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or sub_in_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? sub_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[32:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^sub_in_pvld^sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (sub_in_pvld && !sub_in_prdy), (sub_in_pvld), (sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[48:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[48:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [48:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [48:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [48:0] mul_data_out; +reg mul_out_pvld; +reg [48:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [48:0] p2_skid_data; +reg [48:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[48:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sat_out,tru_out[16:0]} (tru_out_pvld,tru_out_prdy) <= {sat_dout,tru_dout[16:0]} (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,sat_dout + ,tru_dout + ,tru_out_prdy + ,mul_out_prdy + ,sat_out + ,tru_out + ,tru_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input sat_dout; +input [16:0] tru_dout; +input tru_out_prdy; +output mul_out_prdy; +output sat_out; +output [16:0] tru_out; +output tru_out_pvld; +reg mul_out_prdy; +reg [17:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [17:0] p3_skid_data; +reg [17:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg sat_out; +reg [16:0] tru_out; +reg tru_out_pvld; +//## pipe (3) skid buffer +always @( + mul_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {sat_dout,tru_dout[16:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_out_pvld + or p3_skid_valid + or sat_dout + or tru_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {sat_dout,tru_dout[16:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tru_out_prdy + or p3_pipe_data + ) begin + tru_out_pvld = p3_pipe_valid; + p3_pipe_ready = tru_out_prdy; + {sat_out,tru_out[16:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_out_pvld^tru_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {cvt_sat_out,cvt_data_out[15:0]} (cvt_out_pvld,cvt_out_prdy) <= {cvt_sat,cvt_dout[15:0]} (final_out_pvld,final_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_C_INT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvt_dout + ,cvt_out_prdy + ,cvt_sat + ,final_out_pvld + ,cvt_data_out + ,cvt_out_pvld + ,cvt_sat_out + ,final_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [15:0] cvt_dout; +input cvt_out_prdy; +input cvt_sat; +input final_out_pvld; +output [15:0] cvt_data_out; +output cvt_out_pvld; +output cvt_sat_out; +output final_out_prdy; +reg [15:0] cvt_data_out; +reg cvt_out_pvld; +reg cvt_sat_out; +reg final_out_prdy; +reg [16:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [16:0] p4_skid_data; +reg [16:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + final_out_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = final_out_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + final_out_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + final_out_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? {cvt_sat,cvt_dout[15:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or final_out_pvld + or p4_skid_valid + or cvt_sat + or cvt_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? final_out_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? {cvt_sat,cvt_dout[15:0]} : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or cvt_out_prdy + or p4_pipe_data + ) begin + cvt_out_pvld = p4_pipe_valid; + p4_pipe_ready = cvt_out_prdy; + {cvt_sat_out,cvt_data_out[15:0]} = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvt_out_pvld^cvt_out_prdy^final_out_pvld^final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (final_out_pvld && !final_out_prdy), (final_out_pvld), (final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_C_INT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v new file mode 100644 index 0000000..3e2b938 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v @@ -0,0 +1,542 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_alu.v +module NV_NVDLA_SDP_HLS_X_int_alu ( + alu_data_in //|< i + ,alu_in_pvld //|< i + ,alu_op_pvld //|< i + ,alu_out_prdy //|< i + ,cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_shift_value //|< i + ,cfg_alu_src //|< i + ,chn_alu_op //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,alu_data_out //|> o + ,alu_in_prdy //|> o + ,alu_op_prdy //|> o + ,alu_out_pvld //|> o + ); +input [31:0] alu_data_in; +input alu_in_pvld; +input alu_op_pvld; +input alu_out_prdy; +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [15:0] cfg_alu_op; +input [5:0] cfg_alu_shift_value; +input cfg_alu_src; +input [15:0] chn_alu_op; +input nvdla_core_clk; +input nvdla_core_rstn; +output [32:0] alu_data_out; +output alu_in_prdy; +output alu_op_prdy; +output alu_out_pvld; +wire [32:0] alu_sum; +reg [32:0] alu_dout; +wire mon_sum_c; +wire [32:0] alu_data_ext; +wire [32:0] alu_data_final; +wire [31:0] alu_data_reg; +wire [31:0] alu_data_sync; +wire alu_final_prdy; +wire alu_final_pvld; +wire alu_in_srdy; +wire [15:0] alu_op_in; +wire [31:0] alu_op_shift; +wire [15:0] alu_op_sync; +wire alu_shift_prdy; +wire alu_shift_pvld; +wire alu_sync_prdy; +wire alu_sync_pvld; +wire [32:0] operand_ext; +wire [31:0] operand_shift; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(16 ),.DATA2_WIDTH(32 )) x_alu_sync2data ( + .chn1_en (cfg_alu_src & !cfg_alu_bypass) //|< ? + ,.chn2_en (!cfg_alu_bypass) //|< i + ,.chn1_in_pvld (alu_op_pvld) //|< i + ,.chn1_in_prdy (alu_op_prdy) //|> o + ,.chn2_in_pvld (alu_in_pvld) //|< i + ,.chn2_in_prdy (alu_in_srdy) //|> w + ,.chn_out_pvld (alu_sync_pvld) //|> w + ,.chn_out_prdy (alu_sync_prdy) //|< w + ,.data1_in (chn_alu_op[15:0]) //|< i + ,.data2_in (alu_data_in[31:0]) //|< i + ,.data1_out (alu_op_sync[15:0]) //|> w + ,.data2_out (alu_data_sync[31:0]) //|> w + ); +assign alu_op_in[15:0] = cfg_alu_src ? alu_op_sync[15:0] : cfg_alu_op[15:0]; +NV_NVDLA_HLS_shiftleftsu #(.IN_WIDTH(16 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6)) x_alu_shiftleft_su ( + .data_in (alu_op_in[15:0]) //|< w + ,.shift_num (cfg_alu_shift_value[5:0]) //|< i + ,.data_out (alu_op_shift[31:0]) //|> w + ); +//signed +//unsiged +NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_data_sync (alu_data_sync[31:0]) //|< w + ,.alu_op_shift (alu_op_shift[31:0]) //|< w + ,.alu_shift_prdy (alu_shift_prdy) //|< w + ,.alu_sync_pvld (alu_sync_pvld) //|< w + ,.alu_data_reg (alu_data_reg[31:0]) //|> w + ,.alu_shift_pvld (alu_shift_pvld) //|> w + ,.alu_sync_prdy (alu_sync_prdy) //|> w + ,.operand_shift (operand_shift[31:0]) //|> w + ); +assign operand_ext[32:0] = {{1{operand_shift[31]}}, operand_shift[31:0]}; +assign alu_data_ext[32:0] = {{1{alu_data_reg[31]}}, alu_data_reg[31:0]}; +assign {mon_sum_c,alu_sum[32:0]} = $signed(alu_data_ext) + $signed(operand_ext); +always @( + cfg_alu_algo + or alu_data_ext + or operand_ext + or alu_sum + ) begin + if (cfg_alu_algo[1:0]== 0 ) + alu_dout[32:0] = ($signed(alu_data_ext) > $signed(operand_ext)) ? alu_data_ext : operand_ext; + else if (cfg_alu_algo[1:0]== 1 ) + alu_dout[32:0] = ($signed(alu_data_ext) < $signed(operand_ext)) ? alu_data_ext : operand_ext; + else + alu_dout[32:0] = alu_sum[32:0]; +end +NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_dout (alu_dout[32:0]) //|< r + ,.alu_final_prdy (alu_final_prdy) //|< w + ,.alu_shift_pvld (alu_shift_pvld) //|< w + ,.alu_data_final (alu_data_final[32:0]) //|> w + ,.alu_final_pvld (alu_final_pvld) //|> w + ,.alu_shift_prdy (alu_shift_prdy) //|> w + ); +assign alu_in_prdy = cfg_alu_bypass ? alu_out_prdy : alu_in_srdy; +assign alu_final_prdy = cfg_alu_bypass ? 1'b1 : alu_out_prdy; +assign alu_out_pvld = cfg_alu_bypass ? alu_in_pvld : alu_final_pvld; +assign alu_data_out[32:0] = cfg_alu_bypass ? {{1{alu_data_in[31]}}, alu_data_in[31:0]} : alu_data_final[32:0]; +endmodule // NV_NVDLA_SDP_HLS_X_int_alu +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {operand_shift[31:0],alu_data_reg[31:0]} (alu_shift_pvld,alu_shift_prdy) <= {alu_op_shift[31:0],alu_data_sync[31:0]} (alu_sync_pvld,alu_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_data_sync + ,alu_op_shift + ,alu_shift_prdy + ,alu_sync_pvld + ,alu_data_reg + ,alu_shift_pvld + ,alu_sync_prdy + ,operand_shift + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] alu_data_sync; +input [31:0] alu_op_shift; +input alu_shift_prdy; +input alu_sync_pvld; +output [31:0] alu_data_reg; +output alu_shift_pvld; +output alu_sync_prdy; +output [31:0] operand_shift; +reg [31:0] alu_data_reg; +reg alu_shift_pvld; +reg alu_sync_prdy; +reg [31:0] operand_shift; +reg [63:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [63:0] p1_skid_data; +reg [63:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + alu_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = alu_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + alu_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + alu_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {alu_op_shift[31:0],alu_data_sync[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or alu_sync_pvld + or p1_skid_valid + or alu_op_shift + or alu_data_sync + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? alu_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {alu_op_shift[31:0],alu_data_sync[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or alu_shift_prdy + or p1_pipe_data + ) begin + alu_shift_pvld = p1_pipe_valid; + p1_pipe_ready = alu_shift_prdy; + {operand_shift[31:0],alu_data_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_shift_pvld^alu_shift_prdy^alu_sync_pvld^alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (alu_sync_pvld && !alu_sync_prdy), (alu_sync_pvld), (alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is alu_data_final[32:0] (alu_final_pvld,alu_final_prdy) <= alu_dout[32:0] (alu_shift_pvld,alu_shift_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_dout + ,alu_final_prdy + ,alu_shift_pvld + ,alu_data_final + ,alu_final_pvld + ,alu_shift_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] alu_dout; +input alu_final_prdy; +input alu_shift_pvld; +output [32:0] alu_data_final; +output alu_final_pvld; +output alu_shift_prdy; +reg [32:0] alu_data_final; +reg alu_final_pvld; +reg alu_shift_prdy; +reg [32:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32:0] p2_skid_data; +reg [32:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + alu_shift_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = alu_shift_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + alu_shift_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + alu_shift_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? alu_dout[32:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or alu_shift_pvld + or p2_skid_valid + or alu_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? alu_shift_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? alu_dout[32:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or alu_final_prdy + or p2_pipe_data + ) begin + alu_final_pvld = p2_pipe_valid; + p2_pipe_ready = alu_final_prdy; + alu_data_final[32:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_final_pvld^alu_final_prdy^alu_shift_pvld^alu_shift_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (alu_shift_pvld && !alu_shift_prdy), (alu_shift_pvld), (alu_shift_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v.vcp new file mode 100644 index 0000000..3e2b938 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_alu.v.vcp @@ -0,0 +1,542 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_alu.v +module NV_NVDLA_SDP_HLS_X_int_alu ( + alu_data_in //|< i + ,alu_in_pvld //|< i + ,alu_op_pvld //|< i + ,alu_out_prdy //|< i + ,cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_shift_value //|< i + ,cfg_alu_src //|< i + ,chn_alu_op //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,alu_data_out //|> o + ,alu_in_prdy //|> o + ,alu_op_prdy //|> o + ,alu_out_pvld //|> o + ); +input [31:0] alu_data_in; +input alu_in_pvld; +input alu_op_pvld; +input alu_out_prdy; +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [15:0] cfg_alu_op; +input [5:0] cfg_alu_shift_value; +input cfg_alu_src; +input [15:0] chn_alu_op; +input nvdla_core_clk; +input nvdla_core_rstn; +output [32:0] alu_data_out; +output alu_in_prdy; +output alu_op_prdy; +output alu_out_pvld; +wire [32:0] alu_sum; +reg [32:0] alu_dout; +wire mon_sum_c; +wire [32:0] alu_data_ext; +wire [32:0] alu_data_final; +wire [31:0] alu_data_reg; +wire [31:0] alu_data_sync; +wire alu_final_prdy; +wire alu_final_pvld; +wire alu_in_srdy; +wire [15:0] alu_op_in; +wire [31:0] alu_op_shift; +wire [15:0] alu_op_sync; +wire alu_shift_prdy; +wire alu_shift_pvld; +wire alu_sync_prdy; +wire alu_sync_pvld; +wire [32:0] operand_ext; +wire [31:0] operand_shift; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(16 ),.DATA2_WIDTH(32 )) x_alu_sync2data ( + .chn1_en (cfg_alu_src & !cfg_alu_bypass) //|< ? + ,.chn2_en (!cfg_alu_bypass) //|< i + ,.chn1_in_pvld (alu_op_pvld) //|< i + ,.chn1_in_prdy (alu_op_prdy) //|> o + ,.chn2_in_pvld (alu_in_pvld) //|< i + ,.chn2_in_prdy (alu_in_srdy) //|> w + ,.chn_out_pvld (alu_sync_pvld) //|> w + ,.chn_out_prdy (alu_sync_prdy) //|< w + ,.data1_in (chn_alu_op[15:0]) //|< i + ,.data2_in (alu_data_in[31:0]) //|< i + ,.data1_out (alu_op_sync[15:0]) //|> w + ,.data2_out (alu_data_sync[31:0]) //|> w + ); +assign alu_op_in[15:0] = cfg_alu_src ? alu_op_sync[15:0] : cfg_alu_op[15:0]; +NV_NVDLA_HLS_shiftleftsu #(.IN_WIDTH(16 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6)) x_alu_shiftleft_su ( + .data_in (alu_op_in[15:0]) //|< w + ,.shift_num (cfg_alu_shift_value[5:0]) //|< i + ,.data_out (alu_op_shift[31:0]) //|> w + ); +//signed +//unsiged +NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_data_sync (alu_data_sync[31:0]) //|< w + ,.alu_op_shift (alu_op_shift[31:0]) //|< w + ,.alu_shift_prdy (alu_shift_prdy) //|< w + ,.alu_sync_pvld (alu_sync_pvld) //|< w + ,.alu_data_reg (alu_data_reg[31:0]) //|> w + ,.alu_shift_pvld (alu_shift_pvld) //|> w + ,.alu_sync_prdy (alu_sync_prdy) //|> w + ,.operand_shift (operand_shift[31:0]) //|> w + ); +assign operand_ext[32:0] = {{1{operand_shift[31]}}, operand_shift[31:0]}; +assign alu_data_ext[32:0] = {{1{alu_data_reg[31]}}, alu_data_reg[31:0]}; +assign {mon_sum_c,alu_sum[32:0]} = $signed(alu_data_ext) + $signed(operand_ext); +always @( + cfg_alu_algo + or alu_data_ext + or operand_ext + or alu_sum + ) begin + if (cfg_alu_algo[1:0]== 0 ) + alu_dout[32:0] = ($signed(alu_data_ext) > $signed(operand_ext)) ? alu_data_ext : operand_ext; + else if (cfg_alu_algo[1:0]== 1 ) + alu_dout[32:0] = ($signed(alu_data_ext) < $signed(operand_ext)) ? alu_data_ext : operand_ext; + else + alu_dout[32:0] = alu_sum[32:0]; +end +NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_dout (alu_dout[32:0]) //|< r + ,.alu_final_prdy (alu_final_prdy) //|< w + ,.alu_shift_pvld (alu_shift_pvld) //|< w + ,.alu_data_final (alu_data_final[32:0]) //|> w + ,.alu_final_pvld (alu_final_pvld) //|> w + ,.alu_shift_prdy (alu_shift_prdy) //|> w + ); +assign alu_in_prdy = cfg_alu_bypass ? alu_out_prdy : alu_in_srdy; +assign alu_final_prdy = cfg_alu_bypass ? 1'b1 : alu_out_prdy; +assign alu_out_pvld = cfg_alu_bypass ? alu_in_pvld : alu_final_pvld; +assign alu_data_out[32:0] = cfg_alu_bypass ? {{1{alu_data_in[31]}}, alu_data_in[31:0]} : alu_data_final[32:0]; +endmodule // NV_NVDLA_SDP_HLS_X_int_alu +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {operand_shift[31:0],alu_data_reg[31:0]} (alu_shift_pvld,alu_shift_prdy) <= {alu_op_shift[31:0],alu_data_sync[31:0]} (alu_sync_pvld,alu_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_data_sync + ,alu_op_shift + ,alu_shift_prdy + ,alu_sync_pvld + ,alu_data_reg + ,alu_shift_pvld + ,alu_sync_prdy + ,operand_shift + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] alu_data_sync; +input [31:0] alu_op_shift; +input alu_shift_prdy; +input alu_sync_pvld; +output [31:0] alu_data_reg; +output alu_shift_pvld; +output alu_sync_prdy; +output [31:0] operand_shift; +reg [31:0] alu_data_reg; +reg alu_shift_pvld; +reg alu_sync_prdy; +reg [31:0] operand_shift; +reg [63:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [63:0] p1_skid_data; +reg [63:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + alu_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = alu_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + alu_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + alu_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {alu_op_shift[31:0],alu_data_sync[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or alu_sync_pvld + or p1_skid_valid + or alu_op_shift + or alu_data_sync + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? alu_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {alu_op_shift[31:0],alu_data_sync[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or alu_shift_prdy + or p1_pipe_data + ) begin + alu_shift_pvld = p1_pipe_valid; + p1_pipe_ready = alu_shift_prdy; + {operand_shift[31:0],alu_data_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_shift_pvld^alu_shift_prdy^alu_sync_pvld^alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (alu_sync_pvld && !alu_sync_prdy), (alu_sync_pvld), (alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is alu_data_final[32:0] (alu_final_pvld,alu_final_prdy) <= alu_dout[32:0] (alu_shift_pvld,alu_shift_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_dout + ,alu_final_prdy + ,alu_shift_pvld + ,alu_data_final + ,alu_final_pvld + ,alu_shift_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] alu_dout; +input alu_final_prdy; +input alu_shift_pvld; +output [32:0] alu_data_final; +output alu_final_pvld; +output alu_shift_prdy; +reg [32:0] alu_data_final; +reg alu_final_pvld; +reg alu_shift_prdy; +reg [32:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32:0] p2_skid_data; +reg [32:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + alu_shift_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = alu_shift_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + alu_shift_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + alu_shift_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? alu_dout[32:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or alu_shift_pvld + or p2_skid_valid + or alu_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? alu_shift_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? alu_dout[32:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or alu_final_prdy + or p2_pipe_data + ) begin + alu_final_pvld = p2_pipe_valid; + p2_pipe_ready = alu_final_prdy; + alu_data_final[32:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_final_pvld^alu_final_prdy^alu_shift_pvld^alu_shift_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (alu_shift_pvld && !alu_shift_prdy), (alu_shift_pvld), (alu_shift_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_ALU_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_mul.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_mul.v new file mode 100644 index 0000000..7452724 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_mul.v @@ -0,0 +1,307 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_mul.v +module NV_NVDLA_SDP_HLS_X_int_mul ( + alu_data_out //|< i + ,alu_out_pvld //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_src //|< i + ,chn_mul_op //|< i + ,mul_op_pvld //|< i + ,mul_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,alu_out_prdy //|> o + ,bypass_trt_out //|> o + ,mul_data_out //|> o + ,mul_op_prdy //|> o + ,mul_out_pvld //|> o + ); +input [32:0] alu_data_out; +input alu_out_pvld; +input cfg_mul_bypass; +input [15:0] cfg_mul_op; +input cfg_mul_prelu; +input cfg_mul_src; +input [15:0] chn_mul_op; +input mul_op_pvld; +input mul_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output alu_out_prdy; +output bypass_trt_out; +output [48:0] mul_data_out; +output mul_op_prdy; +output mul_out_pvld; +wire alu_out_srdy; +wire bypass_trt; +wire bypass_trt_reg; +wire [48:0] mul_data_final; +wire [32:0] mul_data_in; +wire [32:0] mul_data_sync; +wire mul_final_prdy; +wire mul_final_pvld; +wire [15:0] mul_op_in; +wire [15:0] mul_op_sync; +wire [48:0] mul_prelu_out; +wire mul_sync_prdy; +wire mul_sync_pvld; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(16 ),.DATA2_WIDTH(33 )) x_mul_sync2data ( + .chn1_en (!cfg_mul_bypass & cfg_mul_src) //|< ? + ,.chn2_en (!cfg_mul_bypass) //|< i + ,.chn1_in_pvld (mul_op_pvld) //|< i + ,.chn1_in_prdy (mul_op_prdy) //|> o + ,.chn2_in_pvld (alu_out_pvld) //|< i + ,.chn2_in_prdy (alu_out_srdy) //|> w + ,.chn_out_pvld (mul_sync_pvld) //|> w + ,.chn_out_prdy (mul_sync_prdy) //|< w + ,.data1_in (chn_mul_op[15:0]) //|< i + ,.data2_in (alu_data_out[32:0]) //|< i + ,.data1_out (mul_op_sync[15:0]) //|> w + ,.data2_out (mul_data_sync[32:0]) //|> w + ); +assign bypass_trt = cfg_mul_prelu & !mul_data_sync[33 -1]; +assign mul_op_in[15:0] = (cfg_mul_src == 0 ) ? cfg_mul_op[15:0] : mul_op_sync[15:0]; +assign mul_data_in[32:0] = mul_data_sync[32:0]; +NV_NVDLA_SDP_HLS_prelu #(.IN_WIDTH(33 ),.OUT_WIDTH(49 ),.OP_WIDTH(16 )) x_mul_prelu ( + .cfg_prelu_en (cfg_mul_prelu) //|< i + ,.data_in (mul_data_in[32:0]) //|< w + ,.op_in (mul_op_in[15:0]) //|< w + ,.data_out (mul_prelu_out[48:0]) //|> w + ); +NV_NVDLA_SDP_HLS_X_INT_MUL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bypass_trt (bypass_trt) //|< w + ,.mul_final_prdy (mul_final_prdy) //|< w + ,.mul_prelu_out (mul_prelu_out[48:0]) //|< w + ,.mul_sync_pvld (mul_sync_pvld) //|< w + ,.bypass_trt_reg (bypass_trt_reg) //|> w + ,.mul_data_final (mul_data_final[48:0]) //|> w + ,.mul_final_pvld (mul_final_pvld) //|> w + ,.mul_sync_prdy (mul_sync_prdy) //|> w + ); +assign alu_out_prdy = cfg_mul_bypass ? mul_out_prdy : alu_out_srdy; +assign mul_final_prdy = cfg_mul_bypass ? 1'b1 : mul_out_prdy; +assign mul_out_pvld = cfg_mul_bypass ? alu_out_pvld : mul_final_pvld; +assign bypass_trt_out = cfg_mul_bypass ? 1'b0 : bypass_trt_reg; +assign mul_data_out[48:0] = cfg_mul_bypass ? {{16{alu_data_out[32]}}, alu_data_out[32:0]} : mul_data_final[48:0]; +endmodule // NV_NVDLA_SDP_HLS_X_int_mul +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_data_final[48:0],bypass_trt_reg} (mul_final_pvld,mul_final_prdy) <= {mul_prelu_out[48:0],bypass_trt} (mul_sync_pvld,mul_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_MUL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,bypass_trt + ,mul_final_prdy + ,mul_prelu_out + ,mul_sync_pvld + ,bypass_trt_reg + ,mul_data_final + ,mul_final_pvld + ,mul_sync_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input bypass_trt; +input mul_final_prdy; +input [48:0] mul_prelu_out; +input mul_sync_pvld; +output bypass_trt_reg; +output [48:0] mul_data_final; +output mul_final_pvld; +output mul_sync_prdy; +reg bypass_trt_reg; +reg [48:0] mul_data_final; +reg mul_final_pvld; +reg mul_sync_prdy; +reg [49:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [49:0] p1_skid_data; +reg [49:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + mul_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = mul_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + mul_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + mul_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {mul_prelu_out[48:0],bypass_trt} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or mul_sync_pvld + or p1_skid_valid + or mul_prelu_out + or bypass_trt + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? mul_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {mul_prelu_out[48:0],bypass_trt} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mul_final_prdy + or p1_pipe_data + ) begin + mul_final_pvld = p1_pipe_valid; + p1_pipe_ready = mul_final_prdy; + {mul_data_final[48:0],bypass_trt_reg} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_final_pvld^mul_final_prdy^mul_sync_pvld^mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul_sync_pvld && !mul_sync_prdy), (mul_sync_pvld), (mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_MUL_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_mul.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_mul.v.vcp new file mode 100644 index 0000000..7452724 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_mul.v.vcp @@ -0,0 +1,307 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_mul.v +module NV_NVDLA_SDP_HLS_X_int_mul ( + alu_data_out //|< i + ,alu_out_pvld //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_src //|< i + ,chn_mul_op //|< i + ,mul_op_pvld //|< i + ,mul_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,alu_out_prdy //|> o + ,bypass_trt_out //|> o + ,mul_data_out //|> o + ,mul_op_prdy //|> o + ,mul_out_pvld //|> o + ); +input [32:0] alu_data_out; +input alu_out_pvld; +input cfg_mul_bypass; +input [15:0] cfg_mul_op; +input cfg_mul_prelu; +input cfg_mul_src; +input [15:0] chn_mul_op; +input mul_op_pvld; +input mul_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output alu_out_prdy; +output bypass_trt_out; +output [48:0] mul_data_out; +output mul_op_prdy; +output mul_out_pvld; +wire alu_out_srdy; +wire bypass_trt; +wire bypass_trt_reg; +wire [48:0] mul_data_final; +wire [32:0] mul_data_in; +wire [32:0] mul_data_sync; +wire mul_final_prdy; +wire mul_final_pvld; +wire [15:0] mul_op_in; +wire [15:0] mul_op_sync; +wire [48:0] mul_prelu_out; +wire mul_sync_prdy; +wire mul_sync_pvld; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(16 ),.DATA2_WIDTH(33 )) x_mul_sync2data ( + .chn1_en (!cfg_mul_bypass & cfg_mul_src) //|< ? + ,.chn2_en (!cfg_mul_bypass) //|< i + ,.chn1_in_pvld (mul_op_pvld) //|< i + ,.chn1_in_prdy (mul_op_prdy) //|> o + ,.chn2_in_pvld (alu_out_pvld) //|< i + ,.chn2_in_prdy (alu_out_srdy) //|> w + ,.chn_out_pvld (mul_sync_pvld) //|> w + ,.chn_out_prdy (mul_sync_prdy) //|< w + ,.data1_in (chn_mul_op[15:0]) //|< i + ,.data2_in (alu_data_out[32:0]) //|< i + ,.data1_out (mul_op_sync[15:0]) //|> w + ,.data2_out (mul_data_sync[32:0]) //|> w + ); +assign bypass_trt = cfg_mul_prelu & !mul_data_sync[33 -1]; +assign mul_op_in[15:0] = (cfg_mul_src == 0 ) ? cfg_mul_op[15:0] : mul_op_sync[15:0]; +assign mul_data_in[32:0] = mul_data_sync[32:0]; +NV_NVDLA_SDP_HLS_prelu #(.IN_WIDTH(33 ),.OUT_WIDTH(49 ),.OP_WIDTH(16 )) x_mul_prelu ( + .cfg_prelu_en (cfg_mul_prelu) //|< i + ,.data_in (mul_data_in[32:0]) //|< w + ,.op_in (mul_op_in[15:0]) //|< w + ,.data_out (mul_prelu_out[48:0]) //|> w + ); +NV_NVDLA_SDP_HLS_X_INT_MUL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bypass_trt (bypass_trt) //|< w + ,.mul_final_prdy (mul_final_prdy) //|< w + ,.mul_prelu_out (mul_prelu_out[48:0]) //|< w + ,.mul_sync_pvld (mul_sync_pvld) //|< w + ,.bypass_trt_reg (bypass_trt_reg) //|> w + ,.mul_data_final (mul_data_final[48:0]) //|> w + ,.mul_final_pvld (mul_final_pvld) //|> w + ,.mul_sync_prdy (mul_sync_prdy) //|> w + ); +assign alu_out_prdy = cfg_mul_bypass ? mul_out_prdy : alu_out_srdy; +assign mul_final_prdy = cfg_mul_bypass ? 1'b1 : mul_out_prdy; +assign mul_out_pvld = cfg_mul_bypass ? alu_out_pvld : mul_final_pvld; +assign bypass_trt_out = cfg_mul_bypass ? 1'b0 : bypass_trt_reg; +assign mul_data_out[48:0] = cfg_mul_bypass ? {{16{alu_data_out[32]}}, alu_data_out[32:0]} : mul_data_final[48:0]; +endmodule // NV_NVDLA_SDP_HLS_X_int_mul +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_data_final[48:0],bypass_trt_reg} (mul_final_pvld,mul_final_prdy) <= {mul_prelu_out[48:0],bypass_trt} (mul_sync_pvld,mul_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_MUL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,bypass_trt + ,mul_final_prdy + ,mul_prelu_out + ,mul_sync_pvld + ,bypass_trt_reg + ,mul_data_final + ,mul_final_pvld + ,mul_sync_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input bypass_trt; +input mul_final_prdy; +input [48:0] mul_prelu_out; +input mul_sync_pvld; +output bypass_trt_reg; +output [48:0] mul_data_final; +output mul_final_pvld; +output mul_sync_prdy; +reg bypass_trt_reg; +reg [48:0] mul_data_final; +reg mul_final_pvld; +reg mul_sync_prdy; +reg [49:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [49:0] p1_skid_data; +reg [49:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + mul_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = mul_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + mul_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + mul_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {mul_prelu_out[48:0],bypass_trt} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or mul_sync_pvld + or p1_skid_valid + or mul_prelu_out + or bypass_trt + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? mul_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {mul_prelu_out[48:0],bypass_trt} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mul_final_prdy + or p1_pipe_data + ) begin + mul_final_pvld = p1_pipe_valid; + p1_pipe_ready = mul_final_prdy; + {mul_data_final[48:0],bypass_trt_reg} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_final_pvld^mul_final_prdy^mul_sync_pvld^mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul_sync_pvld && !mul_sync_prdy), (mul_sync_pvld), (mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_MUL_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_relu.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_relu.v new file mode 100644 index 0000000..89d8013 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_relu.v @@ -0,0 +1,260 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_relu.v +module NV_NVDLA_SDP_HLS_X_int_relu ( + cfg_relu_bypass //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,relu_out_prdy //|< i + ,trt_data_out //|< i + ,trt_out_pvld //|< i + ,relu_data_out //|> o + ,relu_out_pvld //|> o + ,trt_out_prdy //|> o + ); +//parameter X_OUT_WIDTH = 32; +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_relu_bypass; +input trt_out_pvld; +output trt_out_prdy; +input [31:0] trt_data_out; +output [31:0] relu_data_out; +output relu_out_pvld; +input relu_out_prdy; +wire [31:0] relu_dout; +wire [31:0] relu_out; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_SDP_HLS_relu #(.DATA_WIDTH(32 )) u_x_relu ( + .data_in (trt_data_out[31:0]) //|< i + ,.data_out (relu_out[31:0]) //|> w + ); +assign relu_dout[31:0] = cfg_relu_bypass ? trt_data_out[31:0] : relu_out[31:0]; +NV_NVDLA_SDP_HLS_X_INT_RELU_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.relu_dout (relu_dout[31:0]) //|< w + ,.relu_out_prdy (relu_out_prdy) //|< i + ,.trt_out_pvld (trt_out_pvld) //|< i + ,.relu_data_out (relu_data_out[31:0]) //|> o + ,.relu_out_pvld (relu_out_pvld) //|> o + ,.trt_out_prdy (trt_out_prdy) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_X_int_relu +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is relu_data_out[31:0] (relu_out_pvld,relu_out_prdy) <= relu_dout[31:0] (trt_out_pvld,trt_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_RELU_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,relu_dout + ,relu_out_prdy + ,trt_out_pvld + ,relu_data_out + ,relu_out_pvld + ,trt_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] relu_dout; +input relu_out_prdy; +input trt_out_pvld; +output [31:0] relu_data_out; +output relu_out_pvld; +output trt_out_prdy; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [31:0] p1_skid_data; +reg [31:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [31:0] relu_data_out; +reg relu_out_pvld; +reg trt_out_prdy; +//## pipe (1) skid buffer +always @( + trt_out_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = trt_out_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + trt_out_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + trt_out_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? relu_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or trt_out_pvld + or p1_skid_valid + or relu_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? trt_out_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? relu_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or relu_out_prdy + or p1_pipe_data + ) begin + relu_out_pvld = p1_pipe_valid; + p1_pipe_ready = relu_out_prdy; + relu_data_out[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (relu_out_pvld^relu_out_prdy^trt_out_pvld^trt_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (trt_out_pvld && !trt_out_prdy), (trt_out_pvld), (trt_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_RELU_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_relu.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_relu.v.vcp new file mode 100644 index 0000000..89d8013 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_relu.v.vcp @@ -0,0 +1,260 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_relu.v +module NV_NVDLA_SDP_HLS_X_int_relu ( + cfg_relu_bypass //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,relu_out_prdy //|< i + ,trt_data_out //|< i + ,trt_out_pvld //|< i + ,relu_data_out //|> o + ,relu_out_pvld //|> o + ,trt_out_prdy //|> o + ); +//parameter X_OUT_WIDTH = 32; +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_relu_bypass; +input trt_out_pvld; +output trt_out_prdy; +input [31:0] trt_data_out; +output [31:0] relu_data_out; +output relu_out_pvld; +input relu_out_prdy; +wire [31:0] relu_dout; +wire [31:0] relu_out; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_SDP_HLS_relu #(.DATA_WIDTH(32 )) u_x_relu ( + .data_in (trt_data_out[31:0]) //|< i + ,.data_out (relu_out[31:0]) //|> w + ); +assign relu_dout[31:0] = cfg_relu_bypass ? trt_data_out[31:0] : relu_out[31:0]; +NV_NVDLA_SDP_HLS_X_INT_RELU_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.relu_dout (relu_dout[31:0]) //|< w + ,.relu_out_prdy (relu_out_prdy) //|< i + ,.trt_out_pvld (trt_out_pvld) //|< i + ,.relu_data_out (relu_data_out[31:0]) //|> o + ,.relu_out_pvld (relu_out_pvld) //|> o + ,.trt_out_prdy (trt_out_prdy) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_X_int_relu +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is relu_data_out[31:0] (relu_out_pvld,relu_out_prdy) <= relu_dout[31:0] (trt_out_pvld,trt_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_RELU_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,relu_dout + ,relu_out_prdy + ,trt_out_pvld + ,relu_data_out + ,relu_out_pvld + ,trt_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] relu_dout; +input relu_out_prdy; +input trt_out_pvld; +output [31:0] relu_data_out; +output relu_out_pvld; +output trt_out_prdy; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [31:0] p1_skid_data; +reg [31:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [31:0] relu_data_out; +reg relu_out_pvld; +reg trt_out_prdy; +//## pipe (1) skid buffer +always @( + trt_out_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = trt_out_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + trt_out_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + trt_out_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? relu_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or trt_out_pvld + or p1_skid_valid + or relu_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? trt_out_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? relu_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or relu_out_prdy + or p1_pipe_data + ) begin + relu_out_pvld = p1_pipe_valid; + p1_pipe_ready = relu_out_prdy; + relu_data_out[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (relu_out_pvld^relu_out_prdy^trt_out_pvld^trt_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (trt_out_pvld && !trt_out_prdy), (trt_out_pvld), (trt_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_RELU_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_trt.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_trt.v new file mode 100644 index 0000000..d314950 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_trt.v @@ -0,0 +1,275 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_trt.v +module NV_NVDLA_SDP_HLS_X_int_trt ( + bypass_trt_in //|< i + ,cfg_mul_shift_value //|< i + ,mul_data_out //|< i + ,mul_out_pvld //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,trt_out_prdy //|< i + ,mul_out_prdy //|> o + ,trt_data_out //|> o + ,trt_out_pvld //|> o + ); +//parameter X_MUL_OUT_WIDTH = 49; +//parameter X_OUT_WIDTH = 32; +input nvdla_core_clk; +input nvdla_core_rstn; +input [5:0] cfg_mul_shift_value; +input bypass_trt_in; +input [48:0] mul_data_out; +input mul_out_pvld; +output mul_out_prdy; +output [31:0] trt_data_out; +output trt_out_pvld; +input trt_out_prdy; +reg [31:0] trt_dout; +wire [31:0] trt_data_final; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(49 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6)) x_trt_shiftright_su ( + .data_in ((bypass_trt_in ? 0 : mul_data_out[48:0])) //|< ? + ,.shift_num (cfg_mul_shift_value[5:0]) //|< i + ,.data_out (trt_data_final[31:0]) //|> w + ); +//signed +//unsigned +always @( + bypass_trt_in + or mul_data_out + or trt_data_final + ) begin + if (bypass_trt_in) + trt_dout[31:0] = mul_data_out[31:0]; //morework + else + trt_dout[31:0] = trt_data_final[31:0]; +end +NV_NVDLA_SDP_HLS_X_INT_TRT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< i + ,.trt_dout (trt_dout[31:0]) //|< r + ,.trt_out_prdy (trt_out_prdy) //|< i + ,.mul_out_prdy (mul_out_prdy) //|> o + ,.trt_data_out (trt_data_out[31:0]) //|> o + ,.trt_out_pvld (trt_out_pvld) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_X_int_trt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is trt_data_out[31:0] (trt_out_pvld,trt_out_prdy) <= trt_dout[31:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_TRT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,trt_dout + ,trt_out_prdy + ,mul_out_prdy + ,trt_data_out + ,trt_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input [31:0] trt_dout; +input trt_out_prdy; +output mul_out_prdy; +output [31:0] trt_data_out; +output trt_out_pvld; +reg mul_out_prdy; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [31:0] p1_skid_data; +reg [31:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [31:0] trt_data_out; +reg trt_out_pvld; +//## pipe (1) skid buffer +always @( + mul_out_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = mul_out_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + mul_out_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? trt_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or mul_out_pvld + or p1_skid_valid + or trt_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? mul_out_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? trt_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or trt_out_prdy + or p1_pipe_data + ) begin + trt_out_pvld = p1_pipe_valid; + p1_pipe_ready = trt_out_prdy; + trt_data_out[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (trt_out_pvld^trt_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_TRT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_trt.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_trt.v.vcp new file mode 100644 index 0000000..d314950 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_X_int_trt.v.vcp @@ -0,0 +1,275 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_X_int_trt.v +module NV_NVDLA_SDP_HLS_X_int_trt ( + bypass_trt_in //|< i + ,cfg_mul_shift_value //|< i + ,mul_data_out //|< i + ,mul_out_pvld //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,trt_out_prdy //|< i + ,mul_out_prdy //|> o + ,trt_data_out //|> o + ,trt_out_pvld //|> o + ); +//parameter X_MUL_OUT_WIDTH = 49; +//parameter X_OUT_WIDTH = 32; +input nvdla_core_clk; +input nvdla_core_rstn; +input [5:0] cfg_mul_shift_value; +input bypass_trt_in; +input [48:0] mul_data_out; +input mul_out_pvld; +output mul_out_prdy; +output [31:0] trt_data_out; +output trt_out_pvld; +input trt_out_prdy; +reg [31:0] trt_dout; +wire [31:0] trt_data_final; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(49 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6)) x_trt_shiftright_su ( + .data_in ((bypass_trt_in ? 0 : mul_data_out[48:0])) //|< ? + ,.shift_num (cfg_mul_shift_value[5:0]) //|< i + ,.data_out (trt_data_final[31:0]) //|> w + ); +//signed +//unsigned +always @( + bypass_trt_in + or mul_data_out + or trt_data_final + ) begin + if (bypass_trt_in) + trt_dout[31:0] = mul_data_out[31:0]; //morework + else + trt_dout[31:0] = trt_data_final[31:0]; +end +NV_NVDLA_SDP_HLS_X_INT_TRT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< i + ,.trt_dout (trt_dout[31:0]) //|< r + ,.trt_out_prdy (trt_out_prdy) //|< i + ,.mul_out_prdy (mul_out_prdy) //|> o + ,.trt_data_out (trt_data_out[31:0]) //|> o + ,.trt_out_pvld (trt_out_pvld) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_X_int_trt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is trt_data_out[31:0] (trt_out_pvld,trt_out_prdy) <= trt_dout[31:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_X_INT_TRT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,trt_dout + ,trt_out_prdy + ,mul_out_prdy + ,trt_data_out + ,trt_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input [31:0] trt_dout; +input trt_out_prdy; +output mul_out_prdy; +output [31:0] trt_data_out; +output trt_out_pvld; +reg mul_out_prdy; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [31:0] p1_skid_data; +reg [31:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [31:0] trt_data_out; +reg trt_out_pvld; +//## pipe (1) skid buffer +always @( + mul_out_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = mul_out_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + mul_out_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? trt_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or mul_out_pvld + or p1_skid_valid + or trt_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? mul_out_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? trt_dout[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or trt_out_prdy + or p1_pipe_data + ) begin + trt_out_pvld = p1_pipe_valid; + p1_pipe_ready = trt_out_prdy; + trt_data_out[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (trt_out_pvld^trt_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_X_INT_TRT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v new file mode 100644 index 0000000..1c72a22 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v @@ -0,0 +1,84 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_cvt_top.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_cvt_top ( + cfg_cvt_bypass //|< i + ,cfg_cvt_offset //|< i + ,cfg_cvt_scale //|< i + ,cfg_cvt_truncate //|< i + ,cvt_data_in //|< i + ,cvt_in_pvld //|< i + ,cvt_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt_data_out //|> o + ,cvt_in_prdy //|> o + ,cvt_out_pvld //|> o + ); +input cfg_cvt_bypass; +input [31:0] cfg_cvt_offset; +input [15:0] cfg_cvt_scale; +input [5:0] cfg_cvt_truncate; +input [16*0 -1:0] cvt_data_in; +input cvt_in_pvld; +input cvt_out_prdy; +output [32*0 -1:0] cvt_data_out; +output cvt_in_prdy; +output cvt_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [15:0] cvt_data_in_${i}; +//: wire [31:0] cvt_data_out_${i}; +//: wire cvt_in_prdy_${i}; +//: wire cvt_out_pvld_${i}; +//: ); +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_data_in_${i} = cvt_data_in[16*${i}+15:16*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_data_out[32*${i}+31:32*${i}] = cvt_data_out_${i}; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_${i} ( +//: .cfg_cvt_bypass (cfg_cvt_bypass) //|< i +//: ,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i +//: ,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i +//: ,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i +//: ,.cvt_data_in (cvt_data_in_${i}[15:0]) //|< w +//: ,.cvt_in_pvld (cvt_in_pvld) //|< i +//: ,.cvt_out_prdy (cvt_out_prdy) //|< i +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.cvt_data_out (cvt_data_out_${i}[31:0]) //|> w +//: ,.cvt_in_prdy (cvt_in_prdy_${i}) //|> w +//: ,.cvt_out_pvld (cvt_out_pvld_${i}) //|> w +//: ); +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvt_in_prdy = cvt_in_prdy_0; +assign cvt_out_pvld = cvt_out_pvld_0; +endmodule // NV_NVDLA_SDP_HLS_Y_cvt_top diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v.vcp new file mode 100644 index 0000000..c303d5e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_cvt_top.v.vcp @@ -0,0 +1,80 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_cvt_top.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_cvt_top ( + cfg_cvt_bypass //|< i + ,cfg_cvt_offset //|< i + ,cfg_cvt_scale //|< i + ,cfg_cvt_truncate //|< i + ,cvt_data_in //|< i + ,cvt_in_pvld //|< i + ,cvt_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt_data_out //|> o + ,cvt_in_prdy //|> o + ,cvt_out_pvld //|> o + ); +input cfg_cvt_bypass; +input [31:0] cfg_cvt_offset; +input [15:0] cfg_cvt_scale; +input [5:0] cfg_cvt_truncate; +input [16*0 -1:0] cvt_data_in; +input cvt_in_pvld; +input cvt_out_prdy; +output [32*0 -1:0] cvt_data_out; +output cvt_in_prdy; +output cvt_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [15:0] cvt_data_in_${i}; +//: wire [31:0] cvt_data_out_${i}; +//: wire cvt_in_prdy_${i}; +//: wire cvt_out_pvld_${i}; +//: ); +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_data_in_${i} = cvt_data_in[16*${i}+15:16*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_data_out[32*${i}+31:32*${i}] = cvt_data_out_${i}; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_Y_int_cvt y_int_cvt_${i} ( +//: .cfg_cvt_bypass (cfg_cvt_bypass) //|< i +//: ,.cfg_cvt_offset (cfg_cvt_offset[31:0]) //|< i +//: ,.cfg_cvt_scale (cfg_cvt_scale[15:0]) //|< i +//: ,.cfg_cvt_truncate (cfg_cvt_truncate[5:0]) //|< i +//: ,.cvt_data_in (cvt_data_in_${i}[15:0]) //|< w +//: ,.cvt_in_pvld (cvt_in_pvld) //|< i +//: ,.cvt_out_prdy (cvt_out_prdy) //|< i +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.cvt_data_out (cvt_data_out_${i}[31:0]) //|> w +//: ,.cvt_in_prdy (cvt_in_prdy_${i}) //|> w +//: ,.cvt_out_pvld (cvt_out_pvld_${i}) //|> w +//: ); +//: ); +//: } +assign cvt_in_prdy = cvt_in_prdy_0; +assign cvt_out_pvld = cvt_out_pvld_0; +endmodule // NV_NVDLA_SDP_HLS_Y_cvt_top diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_idx_top.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_idx_top.v new file mode 100644 index 0000000..3a0192b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_idx_top.v @@ -0,0 +1,144 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_idx_top.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_idx_top ( + cfg_lut_hybrid_priority //|< i + ,cfg_lut_le_function //|< i + ,cfg_lut_le_index_offset //|< i + ,cfg_lut_le_index_select //|< i + ,cfg_lut_le_start //|< i + ,cfg_lut_lo_index_select //|< i + ,cfg_lut_lo_start //|< i + ,cfg_lut_oflow_priority //|< i + ,cfg_lut_uflow_priority //|< i + ,chn_lut_in_pd //|< i + ,chn_lut_in_pvld //|< i + ,chn_lut_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_lut_in_prdy //|> o + ,chn_lut_out_pd //|> o + ,chn_lut_out_pvld //|> o + ); +input cfg_lut_hybrid_priority; +input cfg_lut_le_function; +input [7:0] cfg_lut_le_index_offset; +input [7:0] cfg_lut_le_index_select; +input [31:0] cfg_lut_le_start; +input [7:0] cfg_lut_lo_index_select; +input [31:0] cfg_lut_lo_start; +input cfg_lut_oflow_priority; +input cfg_lut_uflow_priority; +input [32*0 -1:0] chn_lut_in_pd; +input chn_lut_in_pvld; +input chn_lut_out_prdy; +output chn_lut_in_prdy; +output [81*0 -1:0] chn_lut_out_pd; +output chn_lut_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: my $bx =0*35; +//: my $bof=0*(35+32); +//: my $buf=0*(35+32+1); +//: my $bsl=0*(35+32+2); +//: my $ba =0*(35+32+3); +//: my $beh=0*(35+32+12); +//: my $boh=0*(35+32+13); +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire chn_lut_in_prdy$i; +//: wire chn_lut_out_pvld$i; +//: wire [31:0] lut_data_in$i; +//: wire [8:0] lut_out_addr$i; +//: wire [34:0] lut_out_fraction$i; +//: wire lut_out_le_hit$i; +//: wire lut_out_lo_hit$i; +//: wire lut_out_oflow$i; +//: wire lut_out_sel$i; +//: wire lut_out_uflow$i; +//: wire [31:0] lut_out_x$i; +//: ); +//: } +//: +//: +//: foreach my $i (0..${k}-1) { +//: print "assign lut_data_in${i} = chn_lut_in_pd[32*${i}+31:32*${i}]; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_$i ( +//: .cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i +//: ,.cfg_lut_le_function (cfg_lut_le_function) //|< i +//: ,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i +//: ,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i +//: ,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i +//: ,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i +//: ,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i +//: ,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i +//: ,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i +//: ,.lut_data_in (lut_data_in${i}[31:0]) //|< w +//: ,.lut_in_pvld (chn_lut_in_pvld) //|< i +//: ,.lut_out_prdy (chn_lut_out_prdy) //|< i +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.lut_in_prdy (chn_lut_in_prdy${i}) //|> w +//: ,.lut_out_frac (lut_out_fraction${i}[34:0]) //|> w +//: ,.lut_out_le_hit (lut_out_le_hit${i}) //|> w +//: ,.lut_out_lo_hit (lut_out_lo_hit${i}) //|> w +//: ,.lut_out_oflow (lut_out_oflow${i}) //|> w +//: ,.lut_out_pvld (chn_lut_out_pvld${i}) //|> w +//: ,.lut_out_ram_addr (lut_out_addr${i}[8:0]) //|> w +//: ,.lut_out_ram_sel (lut_out_sel${i}) //|> w +//: ,.lut_out_uflow (lut_out_uflow${i}) //|> w +//: ,.lut_out_x (lut_out_x${i}[31:0]) //|> w +//: ); +//: ); +//: } +//: +//: +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[35*${i}+34:35*${i}] = lut_out_fraction${i}[34:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[32*${i}+31+${bx}:32*${i}+${bx}] = lut_out_x${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${bof}] = lut_out_oflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${buf}] = lut_out_uflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${bsl}] = lut_out_sel${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[9*${i}+8+${ba}:9*${i}+${ba}] = lut_out_addr${i}[8:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${beh}] = lut_out_le_hit${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${boh}] = lut_out_lo_hit${i} ; \n"; +//: } +//: +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign chn_lut_in_prdy = chn_lut_in_prdy0; +assign chn_lut_out_pvld = chn_lut_out_pvld0; +endmodule // NV_NVDLA_SDP_HLS_Y_idx_top diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_idx_top.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_idx_top.v.vcp new file mode 100644 index 0000000..2660595 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_idx_top.v.vcp @@ -0,0 +1,141 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_idx_top.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_idx_top ( + cfg_lut_hybrid_priority //|< i + ,cfg_lut_le_function //|< i + ,cfg_lut_le_index_offset //|< i + ,cfg_lut_le_index_select //|< i + ,cfg_lut_le_start //|< i + ,cfg_lut_lo_index_select //|< i + ,cfg_lut_lo_start //|< i + ,cfg_lut_oflow_priority //|< i + ,cfg_lut_uflow_priority //|< i + ,chn_lut_in_pd //|< i + ,chn_lut_in_pvld //|< i + ,chn_lut_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_lut_in_prdy //|> o + ,chn_lut_out_pd //|> o + ,chn_lut_out_pvld //|> o + ); +input cfg_lut_hybrid_priority; +input cfg_lut_le_function; +input [7:0] cfg_lut_le_index_offset; +input [7:0] cfg_lut_le_index_select; +input [31:0] cfg_lut_le_start; +input [7:0] cfg_lut_lo_index_select; +input [31:0] cfg_lut_lo_start; +input cfg_lut_oflow_priority; +input cfg_lut_uflow_priority; +input [32*0 -1:0] chn_lut_in_pd; +input chn_lut_in_pvld; +input chn_lut_out_prdy; +output chn_lut_in_prdy; +output [81*0 -1:0] chn_lut_out_pd; +output chn_lut_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: my $bx =0*35; +//: my $bof=0*(35+32); +//: my $buf=0*(35+32+1); +//: my $bsl=0*(35+32+2); +//: my $ba =0*(35+32+3); +//: my $beh=0*(35+32+12); +//: my $boh=0*(35+32+13); +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire chn_lut_in_prdy$i; +//: wire chn_lut_out_pvld$i; +//: wire [31:0] lut_data_in$i; +//: wire [8:0] lut_out_addr$i; +//: wire [34:0] lut_out_fraction$i; +//: wire lut_out_le_hit$i; +//: wire lut_out_lo_hit$i; +//: wire lut_out_oflow$i; +//: wire lut_out_sel$i; +//: wire lut_out_uflow$i; +//: wire [31:0] lut_out_x$i; +//: ); +//: } +//: +//: +//: foreach my $i (0..${k}-1) { +//: print "assign lut_data_in${i} = chn_lut_in_pd[32*${i}+31:32*${i}]; \n"; +//: } +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_Y_int_idx y_int_idx_$i ( +//: .cfg_lut_hybrid_priority (cfg_lut_hybrid_priority) //|< i +//: ,.cfg_lut_le_function (cfg_lut_le_function) //|< i +//: ,.cfg_lut_le_index_offset (cfg_lut_le_index_offset[7:0]) //|< i +//: ,.cfg_lut_le_index_select (cfg_lut_le_index_select[7:0]) //|< i +//: ,.cfg_lut_le_start (cfg_lut_le_start[31:0]) //|< i +//: ,.cfg_lut_lo_index_select (cfg_lut_lo_index_select[7:0]) //|< i +//: ,.cfg_lut_lo_start (cfg_lut_lo_start[31:0]) //|< i +//: ,.cfg_lut_oflow_priority (cfg_lut_oflow_priority) //|< i +//: ,.cfg_lut_uflow_priority (cfg_lut_uflow_priority) //|< i +//: ,.lut_data_in (lut_data_in${i}[31:0]) //|< w +//: ,.lut_in_pvld (chn_lut_in_pvld) //|< i +//: ,.lut_out_prdy (chn_lut_out_prdy) //|< i +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ,.lut_in_prdy (chn_lut_in_prdy${i}) //|> w +//: ,.lut_out_frac (lut_out_fraction${i}[34:0]) //|> w +//: ,.lut_out_le_hit (lut_out_le_hit${i}) //|> w +//: ,.lut_out_lo_hit (lut_out_lo_hit${i}) //|> w +//: ,.lut_out_oflow (lut_out_oflow${i}) //|> w +//: ,.lut_out_pvld (chn_lut_out_pvld${i}) //|> w +//: ,.lut_out_ram_addr (lut_out_addr${i}[8:0]) //|> w +//: ,.lut_out_ram_sel (lut_out_sel${i}) //|> w +//: ,.lut_out_uflow (lut_out_uflow${i}) //|> w +//: ,.lut_out_x (lut_out_x${i}[31:0]) //|> w +//: ); +//: ); +//: } +//: +//: +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[35*${i}+34:35*${i}] = lut_out_fraction${i}[34:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[32*${i}+31+${bx}:32*${i}+${bx}] = lut_out_x${i}[31:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${bof}] = lut_out_oflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${buf}] = lut_out_uflow${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${bsl}] = lut_out_sel${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[9*${i}+8+${ba}:9*${i}+${ba}] = lut_out_addr${i}[8:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${beh}] = lut_out_le_hit${i} ; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign chn_lut_out_pd[${i}+${boh}] = lut_out_lo_hit${i} ; \n"; +//: } +//: +assign chn_lut_in_prdy = chn_lut_in_prdy0; +assign chn_lut_out_pvld = chn_lut_out_pvld0; +endmodule // NV_NVDLA_SDP_HLS_Y_idx_top diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_inp_top.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_inp_top.v new file mode 100644 index 0000000..09b8eb3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_inp_top.v @@ -0,0 +1,128 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_inp_top.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_inp_top ( + chn_inp_in_pd //|< i + ,chn_inp_in_pvld //|< i + ,chn_inp_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_inp_in_prdy //|> o + ,chn_inp_out_pd //|> o + ,chn_inp_out_pvld //|> o + ); +input [185*0 -1:0] chn_inp_in_pd; +input chn_inp_in_pvld; +input chn_inp_out_prdy; +output chn_inp_in_prdy; +output [32*0 -1:0] chn_inp_out_pd; +output chn_inp_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: my $bf =0*32; +//: my $by0=0*(32+35); +//: my $by1=0*(32+35+16); +//: my $bsc=0*(32+35+32); +//: my $bsf=0*(32+35+48); +//: my $bof=0*(32+35+48+5); +//: my $bbs=0*(32+35+85); +//: my $bfw=0*(32+35+85+32); +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire chn_inp_in_prdy${i}; +//: wire [31:0] chn_inp_out_data${i}; +//: wire chn_inp_out_pvld${i}; +//: wire [31:0] inp_in_bias${i}; +//: wire inp_in_flow${i}; +//: wire [34:0] inp_in_fraction${i}; +//: wire [31:0] inp_in_offset${i}; +//: wire [15:0] inp_in_scale${i}; +//: wire [4:0] inp_in_shift${i}; +//: wire [31:0] inp_in_x${i}; +//: wire [15:0] inp_in_y0_${i}; +//: wire [15:0] inp_in_y1_${i}; +//: ); +//: } +//: print "\n"; +//: +//: foreach my $i (0..${k}-1) { +//: print "assign chn_inp_out_pd[32*${i}+31:32*${i}] = chn_inp_out_data${i}; \n"; +//: } +//: print "\n"; +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_${i} ( +//: .inp_bias_in (inp_in_bias${i}[31:0]) //|< w +//: ,.inp_flow_in (inp_in_flow${i}) //|< w +//: ,.inp_frac_in (inp_in_fraction${i}[34:0]) //|< w +//: ,.inp_in_pvld (chn_inp_in_pvld) //|< i +//: ,.inp_offset_in (inp_in_offset${i}[31:0]) //|< w +//: ,.inp_out_prdy (chn_inp_out_prdy) //|< i +//: ,.inp_scale_in (inp_in_scale${i}[15:0]) //|< w +//: ,.inp_shift_in (inp_in_shift${i}[4:0]) //|< w +//: ,.inp_x_in (inp_in_x${i}[31:0]) //|< w +//: ,.inp_y0_in (inp_in_y0_${i}[15:0]) //|< w +//: ,.inp_y1_in (inp_in_y1_${i}[15:0]) //|< w +//: ,.inp_data_out (chn_inp_out_data${i}[31:0]) //|> w +//: ,.inp_in_prdy (chn_inp_in_prdy${i}) //|> w +//: ,.inp_out_pvld (chn_inp_out_pvld${i}) //|> w +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ); +//: ); +//: } +//: print "\n"; +//: +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_x${i}[31:0] = chn_inp_in_pd[32*${i}+31:32*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_fraction${i}[34:0] = chn_inp_in_pd[35*${i}+${bf}+34:35*${i}+${bf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_y0_${i}[15:0] = chn_inp_in_pd[16*${i}+${by0}+15:16*${i}+${by0}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_y1_${i}[15:0] = chn_inp_in_pd[16*${i}+${by1}+15:16*${i}+${by1}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_scale${i}[15:0] = chn_inp_in_pd[16*${i}+${bsc}+15:16*${i}+${bsc}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_shift${i}[4:0] = chn_inp_in_pd[5*${i}+${bsf}+4:5*${i}+${bsf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_offset${i}[31:0] = chn_inp_in_pd[32*${i}+${bof}+31:32*${i}+${bof}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_bias${i}[31:0] = chn_inp_in_pd[32*${i}+${bbs}+31:32*${i}+${bbs}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_flow${i} = chn_inp_in_pd[${i}+${bfw}]; \n"; +//: } +//: print "\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) + + + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign chn_inp_in_prdy = chn_inp_in_prdy0; +assign chn_inp_out_pvld = chn_inp_out_pvld0; +endmodule // NV_NVDLA_SDP_HLS_Y_inp_top diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_inp_top.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_inp_top.v.vcp new file mode 100644 index 0000000..82607e4 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_inp_top.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_inp_top.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_inp_top ( + chn_inp_in_pd //|< i + ,chn_inp_in_pvld //|< i + ,chn_inp_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_inp_in_prdy //|> o + ,chn_inp_out_pd //|> o + ,chn_inp_out_pvld //|> o + ); +input [185*0 -1:0] chn_inp_in_pd; +input chn_inp_in_pvld; +input chn_inp_out_prdy; +output chn_inp_in_prdy; +output [32*0 -1:0] chn_inp_out_pd; +output chn_inp_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: my $bf =0*32; +//: my $by0=0*(32+35); +//: my $by1=0*(32+35+16); +//: my $bsc=0*(32+35+32); +//: my $bsf=0*(32+35+48); +//: my $bof=0*(32+35+48+5); +//: my $bbs=0*(32+35+85); +//: my $bfw=0*(32+35+85+32); +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire chn_inp_in_prdy${i}; +//: wire [31:0] chn_inp_out_data${i}; +//: wire chn_inp_out_pvld${i}; +//: wire [31:0] inp_in_bias${i}; +//: wire inp_in_flow${i}; +//: wire [34:0] inp_in_fraction${i}; +//: wire [31:0] inp_in_offset${i}; +//: wire [15:0] inp_in_scale${i}; +//: wire [4:0] inp_in_shift${i}; +//: wire [31:0] inp_in_x${i}; +//: wire [15:0] inp_in_y0_${i}; +//: wire [15:0] inp_in_y1_${i}; +//: ); +//: } +//: print "\n"; +//: +//: foreach my $i (0..${k}-1) { +//: print "assign chn_inp_out_pd[32*${i}+31:32*${i}] = chn_inp_out_data${i}; \n"; +//: } +//: print "\n"; +//: +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_Y_int_inp y_int_inp_${i} ( +//: .inp_bias_in (inp_in_bias${i}[31:0]) //|< w +//: ,.inp_flow_in (inp_in_flow${i}) //|< w +//: ,.inp_frac_in (inp_in_fraction${i}[34:0]) //|< w +//: ,.inp_in_pvld (chn_inp_in_pvld) //|< i +//: ,.inp_offset_in (inp_in_offset${i}[31:0]) //|< w +//: ,.inp_out_prdy (chn_inp_out_prdy) //|< i +//: ,.inp_scale_in (inp_in_scale${i}[15:0]) //|< w +//: ,.inp_shift_in (inp_in_shift${i}[4:0]) //|< w +//: ,.inp_x_in (inp_in_x${i}[31:0]) //|< w +//: ,.inp_y0_in (inp_in_y0_${i}[15:0]) //|< w +//: ,.inp_y1_in (inp_in_y1_${i}[15:0]) //|< w +//: ,.inp_data_out (chn_inp_out_data${i}[31:0]) //|> w +//: ,.inp_in_prdy (chn_inp_in_prdy${i}) //|> w +//: ,.inp_out_pvld (chn_inp_out_pvld${i}) //|> w +//: ,.nvdla_core_clk (nvdla_core_clk) //|< i +//: ,.nvdla_core_rstn (nvdla_core_rstn) //|< i +//: ); +//: ); +//: } +//: print "\n"; +//: +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_x${i}[31:0] = chn_inp_in_pd[32*${i}+31:32*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_fraction${i}[34:0] = chn_inp_in_pd[35*${i}+${bf}+34:35*${i}+${bf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_y0_${i}[15:0] = chn_inp_in_pd[16*${i}+${by0}+15:16*${i}+${by0}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_y1_${i}[15:0] = chn_inp_in_pd[16*${i}+${by1}+15:16*${i}+${by1}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_scale${i}[15:0] = chn_inp_in_pd[16*${i}+${bsc}+15:16*${i}+${bsc}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_shift${i}[4:0] = chn_inp_in_pd[5*${i}+${bsf}+4:5*${i}+${bsf}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_offset${i}[31:0] = chn_inp_in_pd[32*${i}+${bof}+31:32*${i}+${bof}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_bias${i}[31:0] = chn_inp_in_pd[32*${i}+${bbs}+31:32*${i}+${bbs}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign inp_in_flow${i} = chn_inp_in_pd[${i}+${bfw}]; \n"; +//: } +//: print "\n"; +assign chn_inp_in_prdy = chn_inp_in_prdy0; +assign chn_inp_out_pvld = chn_inp_out_pvld0; +endmodule // NV_NVDLA_SDP_HLS_Y_inp_top diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_alu.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_alu.v new file mode 100644 index 0000000..7d662a3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_alu.v @@ -0,0 +1,539 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_alu.v +module NV_NVDLA_SDP_HLS_Y_int_alu ( + alu_data_in //|< i + ,alu_in_pvld //|< i + ,alu_out_prdy //|< i + ,cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_src //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,alu_data_out //|> o + ,alu_in_prdy //|> o + ,alu_out_pvld //|> o + ,chn_alu_op_prdy //|> o + ); +input [31:0] alu_data_in; +input alu_in_pvld; +input alu_out_prdy; +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [31:0] cfg_alu_op; +input cfg_alu_src; +input [31:0] chn_alu_op; +input chn_alu_op_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +output [31:0] alu_data_out; +output alu_in_prdy; +output alu_out_pvld; +output chn_alu_op_prdy; +wire [32:0] alu_sum; +reg [32:0] alu_dout; +reg mon_sum_c; +wire [32:0] alu_data_ext; +wire [31:0] alu_data_final; +wire [31:0] alu_data_reg; +wire [31:0] alu_data_sync; +wire alu_final_prdy; +wire alu_final_pvld; +wire alu_in_srdy; +wire alu_mux_prdy; +wire alu_mux_pvld; +wire [32:0] alu_op_ext; +wire [31:0] alu_op_mux; +wire [31:0] alu_op_reg; +wire [31:0] alu_op_sync; +wire [31:0] alu_sat; +wire alu_sync_prdy; +wire alu_sync_pvld; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(32 ),.DATA2_WIDTH(32 )) y_alu_sync2data ( + .chn1_en (cfg_alu_src & !cfg_alu_bypass) //|< ? + ,.chn2_en (!cfg_alu_bypass) //|< i + ,.chn1_in_pvld (chn_alu_op_pvld) //|< i + ,.chn1_in_prdy (chn_alu_op_prdy) //|> o + ,.chn2_in_pvld (alu_in_pvld) //|< i + ,.chn2_in_prdy (alu_in_srdy) //|> w + ,.chn_out_pvld (alu_sync_pvld) //|> w + ,.chn_out_prdy (alu_sync_prdy) //|< w + ,.data1_in (chn_alu_op[31:0]) //|< i + ,.data2_in (alu_data_in[31:0]) //|< i + ,.data1_out (alu_op_sync[31:0]) //|> w + ,.data2_out (alu_data_sync[31:0]) //|> w + ); +assign alu_op_mux = cfg_alu_src ? alu_op_sync[31:0] : cfg_alu_op[31:0]; +NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_data_sync (alu_data_sync[31:0]) //|< w + ,.alu_mux_prdy (alu_mux_prdy) //|< w + ,.alu_op_mux (alu_op_mux[31:0]) //|< w + ,.alu_sync_pvld (alu_sync_pvld) //|< w + ,.alu_data_reg (alu_data_reg[31:0]) //|> w + ,.alu_mux_pvld (alu_mux_pvld) //|> w + ,.alu_op_reg (alu_op_reg[31:0]) //|> w + ,.alu_sync_prdy (alu_sync_prdy) //|> w + ); +assign alu_op_ext[32:0] = {{1{alu_op_reg[31]}}, alu_op_reg[31:0]}; +assign alu_data_ext[32:0] = {{1{alu_data_reg[31]}}, alu_data_reg[31:0]}; +assign {mon_sum_c,alu_sum[32:0]} = $signed(alu_data_ext) + $signed(alu_op_ext); +always @( + cfg_alu_algo + or alu_data_ext + or alu_op_ext + or alu_sum + ) begin + if (cfg_alu_algo[1:0] == 0 ) + alu_dout[32:0] = ($signed(alu_data_ext) > $signed(alu_op_ext)) ? alu_data_ext : alu_op_ext; + else if (cfg_alu_algo[1:0] == 1 ) + alu_dout[32:0] = ($signed(alu_data_ext) < $signed(alu_op_ext)) ? alu_data_ext : alu_op_ext; + else if (cfg_alu_algo[1:0] == 3 ) + alu_dout[32:0] = (alu_data_ext == alu_op_ext) ? 0 : 1; + else + alu_dout[32:0] = alu_sum[32:0]; +end +NV_NVDLA_HLS_saturate #(.IN_WIDTH(32 +1 ),.OUT_WIDTH(32 )) y_alu_saturate ( + .data_in (alu_dout[32:0]) //|< r + ,.data_out (alu_sat[31:0]) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_final_prdy (alu_final_prdy) //|< w + ,.alu_mux_pvld (alu_mux_pvld) //|< w + ,.alu_sat (alu_sat[31:0]) //|< w + ,.alu_data_final (alu_data_final[31:0]) //|> w + ,.alu_final_pvld (alu_final_pvld) //|> w + ,.alu_mux_prdy (alu_mux_prdy) //|> w + ); +assign alu_in_prdy = cfg_alu_bypass ? alu_out_prdy : alu_in_srdy; +assign alu_final_prdy = cfg_alu_bypass ? 1'b1 : alu_out_prdy; +assign alu_out_pvld = cfg_alu_bypass ? alu_in_pvld : alu_final_pvld; +assign alu_data_out[31:0] = cfg_alu_bypass ? alu_data_in[31:0] : alu_data_final[31:0]; +endmodule // NV_NVDLA_SDP_HLS_Y_int_alu +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {alu_data_reg[31:0],alu_op_reg[31:0]} (alu_mux_pvld,alu_mux_prdy) <= {alu_data_sync[31:0],alu_op_mux[31:0]} (alu_sync_pvld,alu_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_data_sync + ,alu_mux_prdy + ,alu_op_mux + ,alu_sync_pvld + ,alu_data_reg + ,alu_mux_pvld + ,alu_op_reg + ,alu_sync_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] alu_data_sync; +input alu_mux_prdy; +input [31:0] alu_op_mux; +input alu_sync_pvld; +output [31:0] alu_data_reg; +output alu_mux_pvld; +output [31:0] alu_op_reg; +output alu_sync_prdy; +reg [31:0] alu_data_reg; +reg alu_mux_pvld; +reg [31:0] alu_op_reg; +reg alu_sync_prdy; +reg [63:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [63:0] p1_skid_data; +reg [63:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + alu_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = alu_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + alu_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + alu_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {alu_data_sync[31:0],alu_op_mux[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or alu_sync_pvld + or p1_skid_valid + or alu_data_sync + or alu_op_mux + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? alu_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {alu_data_sync[31:0],alu_op_mux[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or alu_mux_prdy + or p1_pipe_data + ) begin + alu_mux_pvld = p1_pipe_valid; + p1_pipe_ready = alu_mux_prdy; + {alu_data_reg[31:0],alu_op_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_mux_pvld^alu_mux_prdy^alu_sync_pvld^alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (alu_sync_pvld && !alu_sync_prdy), (alu_sync_pvld), (alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is alu_data_final[31:0] (alu_final_pvld,alu_final_prdy) <= alu_sat[31:0] (alu_mux_pvld,alu_mux_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_final_prdy + ,alu_mux_pvld + ,alu_sat + ,alu_data_final + ,alu_final_pvld + ,alu_mux_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input alu_final_prdy; +input alu_mux_pvld; +input [31:0] alu_sat; +output [31:0] alu_data_final; +output alu_final_pvld; +output alu_mux_prdy; +reg [31:0] alu_data_final; +reg alu_final_pvld; +reg alu_mux_prdy; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [31:0] p2_skid_data; +reg [31:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + alu_mux_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = alu_mux_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + alu_mux_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + alu_mux_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? alu_sat[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or alu_mux_pvld + or p2_skid_valid + or alu_sat + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? alu_mux_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? alu_sat[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or alu_final_prdy + or p2_pipe_data + ) begin + alu_final_pvld = p2_pipe_valid; + p2_pipe_ready = alu_final_prdy; + alu_data_final[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_final_pvld^alu_final_prdy^alu_mux_pvld^alu_mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (alu_mux_pvld && !alu_mux_prdy), (alu_mux_pvld), (alu_mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_alu.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_alu.v.vcp new file mode 100644 index 0000000..7d662a3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_alu.v.vcp @@ -0,0 +1,539 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_alu.v +module NV_NVDLA_SDP_HLS_Y_int_alu ( + alu_data_in //|< i + ,alu_in_pvld //|< i + ,alu_out_prdy //|< i + ,cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_src //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,alu_data_out //|> o + ,alu_in_prdy //|> o + ,alu_out_pvld //|> o + ,chn_alu_op_prdy //|> o + ); +input [31:0] alu_data_in; +input alu_in_pvld; +input alu_out_prdy; +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [31:0] cfg_alu_op; +input cfg_alu_src; +input [31:0] chn_alu_op; +input chn_alu_op_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +output [31:0] alu_data_out; +output alu_in_prdy; +output alu_out_pvld; +output chn_alu_op_prdy; +wire [32:0] alu_sum; +reg [32:0] alu_dout; +reg mon_sum_c; +wire [32:0] alu_data_ext; +wire [31:0] alu_data_final; +wire [31:0] alu_data_reg; +wire [31:0] alu_data_sync; +wire alu_final_prdy; +wire alu_final_pvld; +wire alu_in_srdy; +wire alu_mux_prdy; +wire alu_mux_pvld; +wire [32:0] alu_op_ext; +wire [31:0] alu_op_mux; +wire [31:0] alu_op_reg; +wire [31:0] alu_op_sync; +wire [31:0] alu_sat; +wire alu_sync_prdy; +wire alu_sync_pvld; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(32 ),.DATA2_WIDTH(32 )) y_alu_sync2data ( + .chn1_en (cfg_alu_src & !cfg_alu_bypass) //|< ? + ,.chn2_en (!cfg_alu_bypass) //|< i + ,.chn1_in_pvld (chn_alu_op_pvld) //|< i + ,.chn1_in_prdy (chn_alu_op_prdy) //|> o + ,.chn2_in_pvld (alu_in_pvld) //|< i + ,.chn2_in_prdy (alu_in_srdy) //|> w + ,.chn_out_pvld (alu_sync_pvld) //|> w + ,.chn_out_prdy (alu_sync_prdy) //|< w + ,.data1_in (chn_alu_op[31:0]) //|< i + ,.data2_in (alu_data_in[31:0]) //|< i + ,.data1_out (alu_op_sync[31:0]) //|> w + ,.data2_out (alu_data_sync[31:0]) //|> w + ); +assign alu_op_mux = cfg_alu_src ? alu_op_sync[31:0] : cfg_alu_op[31:0]; +NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_data_sync (alu_data_sync[31:0]) //|< w + ,.alu_mux_prdy (alu_mux_prdy) //|< w + ,.alu_op_mux (alu_op_mux[31:0]) //|< w + ,.alu_sync_pvld (alu_sync_pvld) //|< w + ,.alu_data_reg (alu_data_reg[31:0]) //|> w + ,.alu_mux_pvld (alu_mux_pvld) //|> w + ,.alu_op_reg (alu_op_reg[31:0]) //|> w + ,.alu_sync_prdy (alu_sync_prdy) //|> w + ); +assign alu_op_ext[32:0] = {{1{alu_op_reg[31]}}, alu_op_reg[31:0]}; +assign alu_data_ext[32:0] = {{1{alu_data_reg[31]}}, alu_data_reg[31:0]}; +assign {mon_sum_c,alu_sum[32:0]} = $signed(alu_data_ext) + $signed(alu_op_ext); +always @( + cfg_alu_algo + or alu_data_ext + or alu_op_ext + or alu_sum + ) begin + if (cfg_alu_algo[1:0] == 0 ) + alu_dout[32:0] = ($signed(alu_data_ext) > $signed(alu_op_ext)) ? alu_data_ext : alu_op_ext; + else if (cfg_alu_algo[1:0] == 1 ) + alu_dout[32:0] = ($signed(alu_data_ext) < $signed(alu_op_ext)) ? alu_data_ext : alu_op_ext; + else if (cfg_alu_algo[1:0] == 3 ) + alu_dout[32:0] = (alu_data_ext == alu_op_ext) ? 0 : 1; + else + alu_dout[32:0] = alu_sum[32:0]; +end +NV_NVDLA_HLS_saturate #(.IN_WIDTH(32 +1 ),.OUT_WIDTH(32 )) y_alu_saturate ( + .data_in (alu_dout[32:0]) //|< r + ,.data_out (alu_sat[31:0]) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.alu_final_prdy (alu_final_prdy) //|< w + ,.alu_mux_pvld (alu_mux_pvld) //|< w + ,.alu_sat (alu_sat[31:0]) //|< w + ,.alu_data_final (alu_data_final[31:0]) //|> w + ,.alu_final_pvld (alu_final_pvld) //|> w + ,.alu_mux_prdy (alu_mux_prdy) //|> w + ); +assign alu_in_prdy = cfg_alu_bypass ? alu_out_prdy : alu_in_srdy; +assign alu_final_prdy = cfg_alu_bypass ? 1'b1 : alu_out_prdy; +assign alu_out_pvld = cfg_alu_bypass ? alu_in_pvld : alu_final_pvld; +assign alu_data_out[31:0] = cfg_alu_bypass ? alu_data_in[31:0] : alu_data_final[31:0]; +endmodule // NV_NVDLA_SDP_HLS_Y_int_alu +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {alu_data_reg[31:0],alu_op_reg[31:0]} (alu_mux_pvld,alu_mux_prdy) <= {alu_data_sync[31:0],alu_op_mux[31:0]} (alu_sync_pvld,alu_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_data_sync + ,alu_mux_prdy + ,alu_op_mux + ,alu_sync_pvld + ,alu_data_reg + ,alu_mux_pvld + ,alu_op_reg + ,alu_sync_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] alu_data_sync; +input alu_mux_prdy; +input [31:0] alu_op_mux; +input alu_sync_pvld; +output [31:0] alu_data_reg; +output alu_mux_pvld; +output [31:0] alu_op_reg; +output alu_sync_prdy; +reg [31:0] alu_data_reg; +reg alu_mux_pvld; +reg [31:0] alu_op_reg; +reg alu_sync_prdy; +reg [63:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [63:0] p1_skid_data; +reg [63:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + alu_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = alu_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + alu_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + alu_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {alu_data_sync[31:0],alu_op_mux[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or alu_sync_pvld + or p1_skid_valid + or alu_data_sync + or alu_op_mux + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? alu_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {alu_data_sync[31:0],alu_op_mux[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or alu_mux_prdy + or p1_pipe_data + ) begin + alu_mux_pvld = p1_pipe_valid; + p1_pipe_ready = alu_mux_prdy; + {alu_data_reg[31:0],alu_op_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_mux_pvld^alu_mux_prdy^alu_sync_pvld^alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (alu_sync_pvld && !alu_sync_prdy), (alu_sync_pvld), (alu_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is alu_data_final[31:0] (alu_final_pvld,alu_final_prdy) <= alu_sat[31:0] (alu_mux_pvld,alu_mux_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,alu_final_prdy + ,alu_mux_pvld + ,alu_sat + ,alu_data_final + ,alu_final_pvld + ,alu_mux_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input alu_final_prdy; +input alu_mux_pvld; +input [31:0] alu_sat; +output [31:0] alu_data_final; +output alu_final_pvld; +output alu_mux_prdy; +reg [31:0] alu_data_final; +reg alu_final_pvld; +reg alu_mux_prdy; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [31:0] p2_skid_data; +reg [31:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + alu_mux_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = alu_mux_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + alu_mux_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + alu_mux_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? alu_sat[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or alu_mux_pvld + or p2_skid_valid + or alu_sat + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? alu_mux_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? alu_sat[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or alu_final_prdy + or p2_pipe_data + ) begin + alu_final_pvld = p2_pipe_valid; + p2_pipe_ready = alu_final_prdy; + alu_data_final[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (alu_final_pvld^alu_final_prdy^alu_mux_pvld^alu_mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (alu_mux_pvld && !alu_mux_prdy), (alu_mux_pvld), (alu_mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_ALU_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_core.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_core.v new file mode 100644 index 0000000..a469cff --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_core.v @@ -0,0 +1,139 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_int_core ( + cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_src //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_src //|< i + ,cfg_mul_truncate //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_op_prdy //|> o + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,chn_out_pvld //|> o + ); +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [31:0] cfg_alu_op; +input cfg_alu_src; +input cfg_mul_bypass; +input [31:0] cfg_mul_op; +input cfg_mul_prelu; +input cfg_mul_src; +input [9:0] cfg_mul_truncate; +input [32*0 -1:0] chn_alu_op; +input chn_alu_op_pvld; +input [32*0 -1:0] chn_data_in; +input chn_in_pvld; +input [32*0 -1:0] chn_mul_op; +input chn_mul_op_pvld; +input chn_out_prdy; +output chn_alu_op_prdy; +output [32*0 -1:0] chn_data_out; +output chn_in_prdy; +output chn_mul_op_prdy; +output chn_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [31:0] chn_alu_op_${i}; +//: wire chn_alu_op_prdy_${i}; +//: wire [31:0] chn_data_in_${i}; +//: wire [31:0] chn_data_out_${i}; +//: wire chn_in_prdy_${i}; +//: wire [31:0] chn_mul_op_${i}; +//: wire chn_mul_op_prdy_${i}; +//: wire chn_out_pvld_${i}; +//: wire [31:0] mul_data_out_${i}; +//: wire mul_out_prdy_${i}; +//: wire mul_out_pvld_${i}; +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign chn_in_prdy = chn_in_prdy_0; +assign chn_alu_op_prdy = chn_alu_op_prdy_0; +assign chn_mul_op_prdy = chn_mul_op_prdy_0; +assign chn_out_pvld = chn_out_pvld_0; +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}]; +//: assign chn_alu_op_${i} = chn_alu_op[32*${i}+31:32*${i}]; +//: assign chn_mul_op_${i} = chn_mul_op[32*${i}+31:32*${i}]; +//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i}; +//: +//: NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_${i} ( +//: .cfg_mul_bypass (cfg_mul_bypass) +//: ,.cfg_mul_op (cfg_mul_op[31:0]) +//: ,.cfg_mul_prelu (cfg_mul_prelu) +//: ,.cfg_mul_src (cfg_mul_src) +//: ,.cfg_mul_truncate (cfg_mul_truncate[9:0]) +//: ,.chn_in_pvld (chn_in_pvld) +//: ,.chn_mul_in (chn_data_in_${i}[31:0]) +//: ,.chn_mul_op (chn_mul_op_${i}[31:0]) +//: ,.chn_mul_op_pvld (chn_mul_op_pvld) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.chn_in_prdy (chn_in_prdy_${i}) +//: ,.chn_mul_op_prdy (chn_mul_op_prdy_${i}) +//: ,.mul_data_out (mul_data_out_${i}[31:0]) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_${i} ( +//: .alu_data_in (mul_data_out_${i}[31:0]) +//: ,.alu_in_pvld (mul_out_pvld_${i}) +//: ,.alu_out_prdy (chn_out_prdy) +//: ,.cfg_alu_algo (cfg_alu_algo[1:0]) +//: ,.cfg_alu_bypass (cfg_alu_bypass) +//: ,.cfg_alu_op (cfg_alu_op[31:0]) +//: ,.cfg_alu_src (cfg_alu_src) +//: ,.chn_alu_op (chn_alu_op_${i}[31:0]) +//: ,.chn_alu_op_pvld (chn_alu_op_pvld) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_data_out (chn_data_out_${i}[31:0]) +//: ,.alu_in_prdy (mul_out_prdy_${i}) +//: ,.alu_out_pvld (chn_out_pvld_${i}) +//: ,.chn_alu_op_prdy (chn_alu_op_prdy_${i}) +//: ); +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_HLS_Y_int_core diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_core.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_core.v.vcp new file mode 100644 index 0000000..2df7b85 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_core.v.vcp @@ -0,0 +1,133 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_Y_int_core ( + cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_src //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_src //|< i + ,cfg_mul_truncate //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_op_prdy //|> o + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,chn_out_pvld //|> o + ); +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [31:0] cfg_alu_op; +input cfg_alu_src; +input cfg_mul_bypass; +input [31:0] cfg_mul_op; +input cfg_mul_prelu; +input cfg_mul_src; +input [9:0] cfg_mul_truncate; +input [32*0 -1:0] chn_alu_op; +input chn_alu_op_pvld; +input [32*0 -1:0] chn_data_in; +input chn_in_pvld; +input [32*0 -1:0] chn_mul_op; +input chn_mul_op_pvld; +input chn_out_prdy; +output chn_alu_op_prdy; +output [32*0 -1:0] chn_data_out; +output chn_in_prdy; +output chn_mul_op_prdy; +output chn_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [31:0] chn_alu_op_${i}; +//: wire chn_alu_op_prdy_${i}; +//: wire [31:0] chn_data_in_${i}; +//: wire [31:0] chn_data_out_${i}; +//: wire chn_in_prdy_${i}; +//: wire [31:0] chn_mul_op_${i}; +//: wire chn_mul_op_prdy_${i}; +//: wire chn_out_pvld_${i}; +//: wire [31:0] mul_data_out_${i}; +//: wire mul_out_prdy_${i}; +//: wire mul_out_pvld_${i}; +//: +//: ); +//: } +assign chn_in_prdy = chn_in_prdy_0; +assign chn_alu_op_prdy = chn_alu_op_prdy_0; +assign chn_mul_op_prdy = chn_mul_op_prdy_0; +assign chn_out_pvld = chn_out_pvld_0; +//: my $k=0; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}]; +//: assign chn_alu_op_${i} = chn_alu_op[32*${i}+31:32*${i}]; +//: assign chn_mul_op_${i} = chn_mul_op[32*${i}+31:32*${i}]; +//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i}; +//: +//: NV_NVDLA_SDP_HLS_Y_int_mul u_sdp_y_core_mul_${i} ( +//: .cfg_mul_bypass (cfg_mul_bypass) +//: ,.cfg_mul_op (cfg_mul_op[31:0]) +//: ,.cfg_mul_prelu (cfg_mul_prelu) +//: ,.cfg_mul_src (cfg_mul_src) +//: ,.cfg_mul_truncate (cfg_mul_truncate[9:0]) +//: ,.chn_in_pvld (chn_in_pvld) +//: ,.chn_mul_in (chn_data_in_${i}[31:0]) +//: ,.chn_mul_op (chn_mul_op_${i}[31:0]) +//: ,.chn_mul_op_pvld (chn_mul_op_pvld) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.chn_in_prdy (chn_in_prdy_${i}) +//: ,.chn_mul_op_prdy (chn_mul_op_prdy_${i}) +//: ,.mul_data_out (mul_data_out_${i}[31:0]) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_Y_int_alu u_sdp_y_core_alu_${i} ( +//: .alu_data_in (mul_data_out_${i}[31:0]) +//: ,.alu_in_pvld (mul_out_pvld_${i}) +//: ,.alu_out_prdy (chn_out_prdy) +//: ,.cfg_alu_algo (cfg_alu_algo[1:0]) +//: ,.cfg_alu_bypass (cfg_alu_bypass) +//: ,.cfg_alu_op (cfg_alu_op[31:0]) +//: ,.cfg_alu_src (cfg_alu_src) +//: ,.chn_alu_op (chn_alu_op_${i}[31:0]) +//: ,.chn_alu_op_pvld (chn_alu_op_pvld) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_data_out (chn_data_out_${i}[31:0]) +//: ,.alu_in_prdy (mul_out_prdy_${i}) +//: ,.alu_out_pvld (chn_out_pvld_${i}) +//: ,.chn_alu_op_prdy (chn_alu_op_prdy_${i}) +//: ); +//: +//: ); +//: } +endmodule // NV_NVDLA_SDP_HLS_Y_int_core diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_cvt.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_cvt.v new file mode 100644 index 0000000..d133788 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_cvt.v @@ -0,0 +1,720 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_cvt.v +module NV_NVDLA_SDP_HLS_Y_int_cvt ( + cfg_cvt_bypass //|< i + ,cfg_cvt_offset //|< i + ,cfg_cvt_scale //|< i + ,cfg_cvt_truncate //|< i + ,cvt_data_in //|< i + ,cvt_in_pvld //|< i + ,cvt_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt_data_out //|> o + ,cvt_in_prdy //|> o + ,cvt_out_pvld //|> o + ); +input cfg_cvt_bypass; +input [31:0] cfg_cvt_offset; +input [15:0] cfg_cvt_scale; +input [5:0] cfg_cvt_truncate; +input [15:0] cvt_data_in; +input cvt_in_pvld; +input cvt_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [31:0] cvt_data_out; +output cvt_in_prdy; +output cvt_out_pvld; +wire [32:0] cfg_offset_ext; +wire [15:0] cfg_scale; +wire [5:0] cfg_truncate; +wire [32:0] cvt_data_ext; +wire [31:0] cvt_dout; +wire final_out_prdy; +wire final_out_pvld; +wire mon_sub_c; +wire [48:0] mul_data_out; +wire [48:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [32:0] sub_data_out; +wire [32:0] sub_dout; +wire sub_in_prdy; +wire sub_in_pvld; +wire sub_out_prdy; +wire sub_out_pvld; +wire [31:0] tru_dout; +//sub +assign cfg_scale[15:0] = cfg_cvt_bypass ? {16 {1'b0}} : cfg_cvt_scale[15:0]; +assign cfg_truncate[5:0] = cfg_cvt_bypass ? {6 {1'b0}} : cfg_cvt_truncate[5:0]; +assign cfg_offset_ext[32:0] = cfg_cvt_bypass ? {33 {1'b0}} : ({{1{cfg_cvt_offset[31]}}, cfg_cvt_offset[31:0]}); +assign cvt_data_ext[32:0] = cfg_cvt_bypass ? {33 {1'b0}} : ({{17{cvt_data_in[15]}}, cvt_data_in[15:0]}); +assign {mon_sub_c,sub_dout[32:0]} = $signed(cvt_data_ext[32:0]) -$signed(cfg_offset_ext[32:0]); +NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sub_dout (sub_dout[32:0]) //|< w + ,.sub_in_pvld (sub_in_pvld) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.sub_data_out (sub_data_out[32:0]) //|> w + ,.sub_in_prdy (sub_in_prdy) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[48:0] = $signed(sub_data_out[32:0]) * $signed(cfg_scale[15:0]); +NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[48:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[48:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(33 + 16 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6 )) y_cvt_shiftright_su ( + .data_in (mul_data_out[48:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< w + ,.data_out (tru_dout[31:0]) //|> w + ); +//signed +//unsigned +assign sub_in_pvld = cfg_cvt_bypass ? 1'b0 : cvt_in_pvld; +assign cvt_in_prdy = cfg_cvt_bypass ? final_out_prdy : sub_in_prdy; +assign mul_out_prdy = cfg_cvt_bypass ? 1'b1 : final_out_prdy; +assign final_out_pvld = cfg_cvt_bypass ? cvt_in_pvld : mul_out_pvld; +assign cvt_dout[31:0] = cfg_cvt_bypass ? {{16{cvt_data_in[15]}}, cvt_data_in[15:0]} : tru_dout[31:0]; +NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_dout (cvt_dout[31:0]) //|< w + ,.cvt_out_prdy (cvt_out_prdy) //|< i + ,.final_out_pvld (final_out_pvld) //|< w + ,.cvt_data_out (cvt_data_out[31:0]) //|> o + ,.cvt_out_pvld (cvt_out_pvld) //|> o + ,.final_out_prdy (final_out_prdy) //|> w + ); +endmodule // NV_NVDLA_SDP_HLS_Y_int_cvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[32:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[32:0] (sub_in_pvld,sub_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sub_dout + ,sub_in_pvld + ,sub_out_prdy + ,sub_data_out + ,sub_in_prdy + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] sub_dout; +input sub_in_pvld; +input sub_out_prdy; +output [32:0] sub_data_out; +output sub_in_prdy; +output sub_out_pvld; +reg [32:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32:0] p1_skid_data; +reg [32:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [32:0] sub_data_out; +reg sub_in_prdy; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + sub_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = sub_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + sub_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + sub_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or sub_in_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? sub_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[32:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^sub_in_pvld^sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (sub_in_pvld && !sub_in_prdy), (sub_in_pvld), (sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[48:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[48:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [48:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [48:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [48:0] mul_data_out; +reg mul_out_pvld; +reg [48:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [48:0] p2_skid_data; +reg [48:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[48:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is cvt_data_out[31:0] (cvt_out_pvld,cvt_out_prdy) <= cvt_dout[31:0] (final_out_pvld,final_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvt_dout + ,cvt_out_prdy + ,final_out_pvld + ,cvt_data_out + ,cvt_out_pvld + ,final_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] cvt_dout; +input cvt_out_prdy; +input final_out_pvld; +output [31:0] cvt_data_out; +output cvt_out_pvld; +output final_out_prdy; +reg [31:0] cvt_data_out; +reg cvt_out_pvld; +reg final_out_prdy; +reg [31:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [31:0] p3_skid_data; +reg [31:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + final_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = final_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + final_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + final_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? cvt_dout[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or final_out_pvld + or p3_skid_valid + or cvt_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? final_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? cvt_dout[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or cvt_out_prdy + or p3_pipe_data + ) begin + cvt_out_pvld = p3_pipe_valid; + p3_pipe_ready = cvt_out_prdy; + cvt_data_out[31:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvt_out_pvld^cvt_out_prdy^final_out_pvld^final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (final_out_pvld && !final_out_prdy), (final_out_pvld), (final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_cvt.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_cvt.v.vcp new file mode 100644 index 0000000..d133788 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_cvt.v.vcp @@ -0,0 +1,720 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_cvt.v +module NV_NVDLA_SDP_HLS_Y_int_cvt ( + cfg_cvt_bypass //|< i + ,cfg_cvt_offset //|< i + ,cfg_cvt_scale //|< i + ,cfg_cvt_truncate //|< i + ,cvt_data_in //|< i + ,cvt_in_pvld //|< i + ,cvt_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cvt_data_out //|> o + ,cvt_in_prdy //|> o + ,cvt_out_pvld //|> o + ); +input cfg_cvt_bypass; +input [31:0] cfg_cvt_offset; +input [15:0] cfg_cvt_scale; +input [5:0] cfg_cvt_truncate; +input [15:0] cvt_data_in; +input cvt_in_pvld; +input cvt_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [31:0] cvt_data_out; +output cvt_in_prdy; +output cvt_out_pvld; +wire [32:0] cfg_offset_ext; +wire [15:0] cfg_scale; +wire [5:0] cfg_truncate; +wire [32:0] cvt_data_ext; +wire [31:0] cvt_dout; +wire final_out_prdy; +wire final_out_pvld; +wire mon_sub_c; +wire [48:0] mul_data_out; +wire [48:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [32:0] sub_data_out; +wire [32:0] sub_dout; +wire sub_in_prdy; +wire sub_in_pvld; +wire sub_out_prdy; +wire sub_out_pvld; +wire [31:0] tru_dout; +//sub +assign cfg_scale[15:0] = cfg_cvt_bypass ? {16 {1'b0}} : cfg_cvt_scale[15:0]; +assign cfg_truncate[5:0] = cfg_cvt_bypass ? {6 {1'b0}} : cfg_cvt_truncate[5:0]; +assign cfg_offset_ext[32:0] = cfg_cvt_bypass ? {33 {1'b0}} : ({{1{cfg_cvt_offset[31]}}, cfg_cvt_offset[31:0]}); +assign cvt_data_ext[32:0] = cfg_cvt_bypass ? {33 {1'b0}} : ({{17{cvt_data_in[15]}}, cvt_data_in[15:0]}); +assign {mon_sub_c,sub_dout[32:0]} = $signed(cvt_data_ext[32:0]) -$signed(cfg_offset_ext[32:0]); +NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sub_dout (sub_dout[32:0]) //|< w + ,.sub_in_pvld (sub_in_pvld) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.sub_data_out (sub_data_out[32:0]) //|> w + ,.sub_in_prdy (sub_in_prdy) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[48:0] = $signed(sub_data_out[32:0]) * $signed(cfg_scale[15:0]); +NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[48:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[48:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(33 + 16 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6 )) y_cvt_shiftright_su ( + .data_in (mul_data_out[48:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< w + ,.data_out (tru_dout[31:0]) //|> w + ); +//signed +//unsigned +assign sub_in_pvld = cfg_cvt_bypass ? 1'b0 : cvt_in_pvld; +assign cvt_in_prdy = cfg_cvt_bypass ? final_out_prdy : sub_in_prdy; +assign mul_out_prdy = cfg_cvt_bypass ? 1'b1 : final_out_prdy; +assign final_out_pvld = cfg_cvt_bypass ? cvt_in_pvld : mul_out_pvld; +assign cvt_dout[31:0] = cfg_cvt_bypass ? {{16{cvt_data_in[15]}}, cvt_data_in[15:0]} : tru_dout[31:0]; +NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_dout (cvt_dout[31:0]) //|< w + ,.cvt_out_prdy (cvt_out_prdy) //|< i + ,.final_out_pvld (final_out_pvld) //|< w + ,.cvt_data_out (cvt_data_out[31:0]) //|> o + ,.cvt_out_pvld (cvt_out_pvld) //|> o + ,.final_out_prdy (final_out_prdy) //|> w + ); +endmodule // NV_NVDLA_SDP_HLS_Y_int_cvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[32:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[32:0] (sub_in_pvld,sub_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sub_dout + ,sub_in_pvld + ,sub_out_prdy + ,sub_data_out + ,sub_in_prdy + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] sub_dout; +input sub_in_pvld; +input sub_out_prdy; +output [32:0] sub_data_out; +output sub_in_prdy; +output sub_out_pvld; +reg [32:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32:0] p1_skid_data; +reg [32:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [32:0] sub_data_out; +reg sub_in_prdy; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + sub_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = sub_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + sub_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + sub_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or sub_in_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? sub_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[32:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[32:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^sub_in_pvld^sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (sub_in_pvld && !sub_in_prdy), (sub_in_pvld), (sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[48:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[48:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [48:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [48:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [48:0] mul_data_out; +reg mul_out_pvld; +reg [48:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [48:0] p2_skid_data; +reg [48:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[48:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[48:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is cvt_data_out[31:0] (cvt_out_pvld,cvt_out_prdy) <= cvt_dout[31:0] (final_out_pvld,final_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cvt_dout + ,cvt_out_prdy + ,final_out_pvld + ,cvt_data_out + ,cvt_out_pvld + ,final_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] cvt_dout; +input cvt_out_prdy; +input final_out_pvld; +output [31:0] cvt_data_out; +output cvt_out_pvld; +output final_out_prdy; +reg [31:0] cvt_data_out; +reg cvt_out_pvld; +reg final_out_prdy; +reg [31:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [31:0] p3_skid_data; +reg [31:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + final_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = final_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + final_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + final_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? cvt_dout[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or final_out_pvld + or p3_skid_valid + or cvt_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? final_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? cvt_dout[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or cvt_out_prdy + or p3_pipe_data + ) begin + cvt_out_pvld = p3_pipe_valid; + p3_pipe_ready = cvt_out_prdy; + cvt_data_out[31:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (cvt_out_pvld^cvt_out_prdy^final_out_pvld^final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (final_out_pvld && !final_out_prdy), (final_out_pvld), (final_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_CVT_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_idx.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_idx.v new file mode 100644 index 0000000..eca378d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_idx.v @@ -0,0 +1,1147 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_idx.v +module NV_NVDLA_SDP_HLS_Y_int_idx ( + cfg_lut_hybrid_priority //|< i + ,cfg_lut_le_function //|< i + ,cfg_lut_le_index_offset //|< i + ,cfg_lut_le_index_select //|< i + ,cfg_lut_le_start //|< i + ,cfg_lut_lo_index_select //|< i + ,cfg_lut_lo_start //|< i + ,cfg_lut_oflow_priority //|< i + ,cfg_lut_uflow_priority //|< i + ,lut_data_in //|< i + ,lut_in_pvld //|< i + ,lut_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,lut_in_prdy //|> o + ,lut_out_frac //|> o + ,lut_out_le_hit //|> o + ,lut_out_lo_hit //|> o + ,lut_out_oflow //|> o + ,lut_out_pvld //|> o + ,lut_out_ram_addr //|> o + ,lut_out_ram_sel //|> o + ,lut_out_uflow //|> o + ,lut_out_x //|> o + ); +input cfg_lut_hybrid_priority; +input cfg_lut_le_function; +input [7:0] cfg_lut_le_index_offset; +input [7:0] cfg_lut_le_index_select; +input [31:0] cfg_lut_le_start; +input [7:0] cfg_lut_lo_index_select; +input [31:0] cfg_lut_lo_start; +input cfg_lut_oflow_priority; +input cfg_lut_uflow_priority; +input [31:0] lut_data_in; +input lut_in_pvld; +input lut_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output lut_in_prdy; +output [34:0] lut_out_frac; +output lut_out_le_hit; +output lut_out_lo_hit; +output lut_out_oflow; +output lut_out_pvld; +output [8:0] lut_out_ram_addr; +output lut_out_ram_sel; +output lut_out_uflow; +output [31:0] lut_out_x; +/* +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_lut_le_function; +input cfg_lut_hybrid_priority; +input cfg_lut_oflow_priority; +input cfg_lut_uflow_priority; + +input lut_in_pvld; +output lut_in_prdy; +output lut_out_pvld; +input lut_out_prdy; + +input [LUT_IDX_REG_WIDTH-1:0] cfg_lut_le_index_select; +input [LUT_IDX_REG_WIDTH-1:0] cfg_lut_lo_index_select; +input [LUT_IDX_REG_WIDTH-1:0] cfg_lut_le_index_offset; +input [LUT_REG_WIDTH-1:0] cfg_lut_le_start; +input [LUT_REG_WIDTH-1:0] cfg_lut_lo_start; +input [LUT_IN_WIDTH-1:0] lut_data_in; + +output [LUT_IN_WIDTH-1:0] lut_out_x; +output [LUT_FRAC_WIDTH-1:0] lut_out_frac; +output [LUT_ADDR_WIDTH-1:0] lut_out_ram_addr; +output lut_out_ram_sel; +output lut_out_le_hit; +output lut_out_lo_hit; +output lut_out_uflow; +output lut_out_oflow; +*/ +reg [34:0] lut_final_frac; +reg lut_final_oflow; +reg [8:0] lut_final_ram_addr; +reg lut_final_ram_sel; +reg lut_final_uflow; +wire [7:0] le_expn_cfg_offset; +wire [31:0] le_expn_cfg_start; +wire [31:0] le_expn_data_in; +wire [34:0] le_expn_frac; +wire le_expn_in_prdy; +wire le_expn_in_pvld; +wire [8:0] le_expn_index; +wire le_expn_oflow; +wire le_expn_out_prdy; +wire le_expn_out_pvld; +wire le_expn_uflow; +wire [34:0] le_frac; +wire le_hit; +wire [8:0] le_index; +wire [7:0] le_line_cfg_sel; +wire [31:0] le_line_cfg_start; +wire [31:0] le_line_data_in; +wire [34:0] le_line_frac; +wire le_line_in_prdy; +wire le_line_in_pvld; +wire [8:0] le_line_index; +wire le_line_oflow; +wire le_line_out_prdy; +wire le_line_out_pvld; +wire le_line_uflow; +wire le_miss; +wire le_oflow; +wire le_uflow; +wire [34:0] lo_frac; +wire lo_hit; +wire [8:0] lo_index; +wire [34:0] lo_line_frac; +wire lo_line_in_prdy; +wire [8:0] lo_line_index; +wire lo_line_oflow; +wire lo_line_out_pvld; +wire lo_line_uflow; +wire lo_miss; +wire lo_oflow; +wire lo_uflow; +wire [80:0] lut_final_pd; +wire lut_final_prdy; +wire lut_final_pvld; +wire [31:0] lut_final_x; +wire lut_in_xrdy; +wire [80:0] lut_out_pd; +wire lut_pipe2_prdy; +wire lut_pipe2_pvld; +wire [31:0] lut_pipe2_x; +wire lut_pipe3_pvld; +wire lut_pipe_prdy; +wire lut_pipe_pvld; +wire [31:0] lut_pipe_x; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//The same three stage pipe with lut_expn and lut_line +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_data_in (lut_data_in[31:0]) //|< i + ,.lut_in_pvld (lut_in_pvld) //|< i + ,.lut_pipe_prdy (lut_pipe_prdy) //|< w + ,.lut_in_xrdy (lut_in_xrdy) //|> w * + ,.lut_pipe_pvld (lut_pipe_pvld) //|> w + ,.lut_pipe_x (lut_pipe_x[31:0]) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_pipe2_prdy (lut_pipe2_prdy) //|< w + ,.lut_pipe_pvld (lut_pipe_pvld) //|< w + ,.lut_pipe_x (lut_pipe_x[31:0]) //|< w + ,.lut_pipe2_pvld (lut_pipe2_pvld) //|> w + ,.lut_pipe2_x (lut_pipe2_x[31:0]) //|> w + ,.lut_pipe_prdy (lut_pipe_prdy) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_final_prdy (lut_final_prdy) //|< w + ,.lut_pipe2_pvld (lut_pipe2_pvld) //|< w + ,.lut_pipe2_x (lut_pipe2_x[31:0]) //|< w + ,.lut_final_x (lut_final_x[31:0]) //|> w + ,.lut_pipe2_prdy (lut_pipe2_prdy) //|> w + ,.lut_pipe3_pvld (lut_pipe3_pvld) //|> w * + ); +NV_NVDLA_SDP_HLS_lut_expn #(.LUT_DEPTH(65 )) lut_le_expn ( + .cfg_lut_offset (le_expn_cfg_offset[7:0]) //|< w + ,.cfg_lut_start (le_expn_cfg_start[31:0]) //|< w + ,.idx_data_in (le_expn_data_in[31:0]) //|< w + ,.idx_in_pvld (le_expn_in_pvld) //|< w + ,.idx_out_prdy (le_expn_out_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_prdy (le_expn_in_prdy) //|> w + ,.idx_out_pvld (le_expn_out_pvld) //|> w + ,.lut_frac_out (le_expn_frac[34:0]) //|> w + ,.lut_index_out (le_expn_index[8:0]) //|> w + ,.lut_oflow_out (le_expn_oflow) //|> w + ,.lut_uflow_out (le_expn_uflow) //|> w + ); +NV_NVDLA_SDP_HLS_lut_line #(.LUT_DEPTH(65 )) lut_le_line ( + .cfg_lut_sel (le_line_cfg_sel[7:0]) //|< w + ,.cfg_lut_start (le_line_cfg_start[31:0]) //|< w + ,.idx_data_in (le_line_data_in[31:0]) //|< w + ,.idx_in_pvld (le_line_in_pvld) //|< w + ,.idx_out_prdy (le_line_out_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_prdy (le_line_in_prdy) //|> w + ,.idx_out_pvld (le_line_out_pvld) //|> w + ,.lut_frac_out (le_line_frac[34:0]) //|> w + ,.lut_index_out (le_line_index[8:0]) //|> w + ,.lut_oflow_out (le_line_oflow) //|> w + ,.lut_uflow_out (le_line_uflow) //|> w + ); +NV_NVDLA_SDP_HLS_lut_line #(.LUT_DEPTH(257 )) lut_lo_line ( + .cfg_lut_sel (cfg_lut_lo_index_select[7:0]) //|< i + ,.cfg_lut_start (cfg_lut_lo_start[31:0]) //|< i + ,.idx_data_in (lut_data_in[31:0]) //|< i + ,.idx_in_pvld (lut_in_pvld) //|< i + ,.idx_out_prdy (lut_final_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_prdy (lo_line_in_prdy) //|> w + ,.idx_out_pvld (lo_line_out_pvld) //|> w + ,.lut_frac_out (lo_line_frac[34:0]) //|> w + ,.lut_index_out (lo_line_index[8:0]) //|> w + ,.lut_oflow_out (lo_line_oflow) //|> w + ,.lut_uflow_out (lo_line_uflow) //|> w + ); +assign le_expn_in_pvld = (cfg_lut_le_function == 0 ) ? lut_in_pvld : 1'b0; +assign le_line_in_pvld = (cfg_lut_le_function != 0 ) ? lut_in_pvld : 1'b0; +assign le_expn_out_prdy = (cfg_lut_le_function == 0 ) ? lut_final_prdy : 1'b1; +assign le_line_out_prdy = (cfg_lut_le_function != 0 ) ? lut_final_prdy : 1'b1; +assign le_expn_data_in[31:0] = (cfg_lut_le_function == 0 ) ? lut_data_in[31:0] : {32 {1'b0}}; +assign le_expn_cfg_start[31:0] = (cfg_lut_le_function == 0 ) ? cfg_lut_le_start[31:0] : {32 {1'b0}}; +assign le_expn_cfg_offset[7:0] = (cfg_lut_le_function == 0 ) ? cfg_lut_le_index_offset[7:0] : {8 {1'b0}}; +assign le_line_data_in[31:0] = (cfg_lut_le_function != 0 ) ? lut_data_in[31:0] : {32 {1'b0}}; +assign le_line_cfg_start[31:0] = (cfg_lut_le_function != 0 ) ? cfg_lut_le_start[31:0] : {32 {1'b0}}; +assign le_line_cfg_sel[7:0] = (cfg_lut_le_function != 0 ) ? cfg_lut_le_index_select[7:0] : {8 {1'b0}}; +assign lut_in_prdy = ((cfg_lut_le_function == 0 ) ? le_expn_in_prdy : le_line_in_prdy ) & lo_line_in_prdy; +assign lut_final_pvld = ((cfg_lut_le_function == 0 ) ? le_expn_out_pvld : le_line_out_pvld) & lo_line_out_pvld; +assign le_oflow = (cfg_lut_le_function == 0 ) ? le_expn_oflow : le_line_oflow; +assign le_uflow = (cfg_lut_le_function == 0 ) ? le_expn_uflow : le_line_uflow; +assign le_index[8:0] = (cfg_lut_le_function == 0 ) ? le_expn_index[8:0] : le_line_index[8:0]; +assign le_frac[34:0] = (cfg_lut_le_function == 0 ) ? le_expn_frac[34:0] : le_line_frac[34:0]; +assign lo_oflow = lo_line_oflow; +assign lo_uflow = lo_line_uflow; +assign lo_index[8:0] = lo_line_index[8:0]; +assign lo_frac[34:0] = lo_line_frac[34:0]; +//hit miss +assign le_miss = (le_uflow | le_oflow); +assign le_hit = !le_miss; +assign lo_miss = (lo_uflow | lo_oflow); +assign lo_hit = !lo_miss; +always @( + le_uflow + or lo_uflow + or cfg_lut_uflow_priority + or lo_index + or le_index + or lo_frac + or le_frac + or le_oflow + or lo_oflow + or cfg_lut_oflow_priority + or le_hit + or lo_hit + or cfg_lut_hybrid_priority + or le_miss + or lo_miss + ) begin + if (le_uflow & lo_uflow) begin + lut_final_uflow = cfg_lut_uflow_priority ? lo_uflow : le_uflow; + lut_final_oflow = 0; + lut_final_ram_sel = cfg_lut_uflow_priority ? 1 : 0 ; + lut_final_ram_addr= cfg_lut_uflow_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_uflow_priority ? lo_frac : le_frac; + end + else if (le_oflow & lo_oflow) begin + lut_final_uflow = 0; + lut_final_oflow = cfg_lut_oflow_priority ? lo_oflow : le_oflow; + lut_final_ram_sel = cfg_lut_oflow_priority ? 1 : 0 ; + lut_final_ram_addr= cfg_lut_oflow_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_oflow_priority ? lo_frac : le_frac; + end + else if (le_hit & lo_hit) begin + lut_final_ram_addr= cfg_lut_hybrid_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_hybrid_priority ? lo_frac : le_frac; + lut_final_ram_sel = cfg_lut_hybrid_priority ? 1 : 0 ; + lut_final_uflow = 0; + lut_final_oflow = 0; + end + else if (le_miss & lo_miss) begin + lut_final_ram_addr= cfg_lut_hybrid_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_hybrid_priority ? lo_frac : le_frac; + lut_final_ram_sel = cfg_lut_hybrid_priority ? 1 : 0 ; + lut_final_uflow = cfg_lut_hybrid_priority ? lo_uflow : le_uflow; + lut_final_oflow = cfg_lut_hybrid_priority ? lo_oflow : le_oflow; + end + else if (le_hit) begin + lut_final_ram_addr= le_index; + lut_final_frac = le_frac; + lut_final_ram_sel = 0 ; + lut_final_uflow = 0; + lut_final_oflow = 0; + end + else begin // if (lo_hit) begin + lut_final_ram_addr= lo_index; + lut_final_frac = lo_frac; + lut_final_ram_sel = 1 ; + lut_final_uflow = 0; + lut_final_oflow = 0; + end +end +assign lut_final_pd = {lo_hit,le_hit,lut_final_oflow,lut_final_uflow,lut_final_frac[34:0],lut_final_ram_addr[8:0],lut_final_ram_sel,lut_final_x[31:0]}; +assign {lut_out_lo_hit,lut_out_le_hit,lut_out_oflow,lut_out_uflow,lut_out_frac[34:0],lut_out_ram_addr[8:0],lut_out_ram_sel,lut_out_x[31:0]} = lut_out_pd; +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_final_pd (lut_final_pd[80:0]) //|< w + ,.lut_final_pvld (lut_final_pvld) //|< w + ,.lut_out_prdy (lut_out_prdy) //|< i + ,.lut_final_prdy (lut_final_prdy) //|> w + ,.lut_out_pd (lut_out_pd[80:0]) //|> w + ,.lut_out_pvld (lut_out_pvld) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_Y_int_idx +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_pipe_x[31:0] (lut_pipe_pvld,lut_pipe_prdy) <= lut_data_in[31:0] (lut_in_pvld,lut_in_xrdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_data_in + ,lut_in_pvld + ,lut_pipe_prdy + ,lut_in_xrdy + ,lut_pipe_pvld + ,lut_pipe_x + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] lut_data_in; +input lut_in_pvld; +input lut_pipe_prdy; +output lut_in_xrdy; +output lut_pipe_pvld; +output [31:0] lut_pipe_x; +reg lut_in_xrdy; +reg lut_pipe_pvld; +reg [31:0] lut_pipe_x; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [31:0] p1_skid_data; +reg [31:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + lut_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = lut_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + lut_in_xrdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + lut_in_xrdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? lut_data_in[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or lut_in_pvld + or p1_skid_valid + or lut_data_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? lut_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? lut_data_in[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or lut_pipe_prdy + or p1_pipe_data + ) begin + lut_pipe_pvld = p1_pipe_valid; + p1_pipe_ready = lut_pipe_prdy; + lut_pipe_x[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_pipe_pvld^lut_pipe_prdy^lut_in_pvld^lut_in_xrdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (lut_in_pvld && !lut_in_xrdy), (lut_in_pvld), (lut_in_xrdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_pipe2_x[31:0] (lut_pipe2_pvld,lut_pipe2_prdy) <= lut_pipe_x[31:0] (lut_pipe_pvld,lut_pipe_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_pipe2_prdy + ,lut_pipe_pvld + ,lut_pipe_x + ,lut_pipe2_pvld + ,lut_pipe2_x + ,lut_pipe_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input lut_pipe2_prdy; +input lut_pipe_pvld; +input [31:0] lut_pipe_x; +output lut_pipe2_pvld; +output [31:0] lut_pipe2_x; +output lut_pipe_prdy; +reg lut_pipe2_pvld; +reg [31:0] lut_pipe2_x; +reg lut_pipe_prdy; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [31:0] p2_skid_data; +reg [31:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + lut_pipe_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = lut_pipe_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + lut_pipe_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + lut_pipe_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? lut_pipe_x[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or lut_pipe_pvld + or p2_skid_valid + or lut_pipe_x + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? lut_pipe_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? lut_pipe_x[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or lut_pipe2_prdy + or p2_pipe_data + ) begin + lut_pipe2_pvld = p2_pipe_valid; + p2_pipe_ready = lut_pipe2_prdy; + lut_pipe2_x[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_pipe2_pvld^lut_pipe2_prdy^lut_pipe_pvld^lut_pipe_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (lut_pipe_pvld && !lut_pipe_prdy), (lut_pipe_pvld), (lut_pipe_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_final_x[31:0] (lut_pipe3_pvld,lut_final_prdy) <= lut_pipe2_x[31:0] (lut_pipe2_pvld,lut_pipe2_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_final_prdy + ,lut_pipe2_pvld + ,lut_pipe2_x + ,lut_final_x + ,lut_pipe2_prdy + ,lut_pipe3_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input lut_final_prdy; +input lut_pipe2_pvld; +input [31:0] lut_pipe2_x; +output [31:0] lut_final_x; +output lut_pipe2_prdy; +output lut_pipe3_pvld; +reg [31:0] lut_final_x; +reg lut_pipe2_prdy; +reg lut_pipe3_pvld; +reg [31:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [31:0] p3_skid_data; +reg [31:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + lut_pipe2_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = lut_pipe2_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + lut_pipe2_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + lut_pipe2_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? lut_pipe2_x[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or lut_pipe2_pvld + or p3_skid_valid + or lut_pipe2_x + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? lut_pipe2_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? lut_pipe2_x[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or lut_final_prdy + or p3_pipe_data + ) begin + lut_pipe3_pvld = p3_pipe_valid; + p3_pipe_ready = lut_final_prdy; + lut_final_x[31:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_pipe3_pvld^lut_final_prdy^lut_pipe2_pvld^lut_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (lut_pipe2_pvld && !lut_pipe2_prdy), (lut_pipe2_pvld), (lut_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_out_pd[80:0] (lut_out_pvld,lut_out_prdy) <= lut_final_pd[80:0] (lut_final_pvld,lut_final_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_final_pd + ,lut_final_pvld + ,lut_out_prdy + ,lut_final_prdy + ,lut_out_pd + ,lut_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [80:0] lut_final_pd; +input lut_final_pvld; +input lut_out_prdy; +output lut_final_prdy; +output [80:0] lut_out_pd; +output lut_out_pvld; +reg lut_final_prdy; +reg [80:0] lut_out_pd; +reg lut_out_pvld; +reg [80:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [80:0] p4_skid_data; +reg [80:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + lut_final_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = lut_final_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + lut_final_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + lut_final_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? lut_final_pd[80:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or lut_final_pvld + or p4_skid_valid + or lut_final_pd + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? lut_final_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? lut_final_pd[80:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or lut_out_prdy + or p4_pipe_data + ) begin + lut_out_pvld = p4_pipe_valid; + p4_pipe_ready = lut_out_prdy; + lut_out_pd[80:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_out_pvld^lut_out_prdy^lut_final_pvld^lut_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (lut_final_pvld && !lut_final_prdy), (lut_final_pvld), (lut_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_idx.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_idx.v.vcp new file mode 100644 index 0000000..eca378d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_idx.v.vcp @@ -0,0 +1,1147 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_idx.v +module NV_NVDLA_SDP_HLS_Y_int_idx ( + cfg_lut_hybrid_priority //|< i + ,cfg_lut_le_function //|< i + ,cfg_lut_le_index_offset //|< i + ,cfg_lut_le_index_select //|< i + ,cfg_lut_le_start //|< i + ,cfg_lut_lo_index_select //|< i + ,cfg_lut_lo_start //|< i + ,cfg_lut_oflow_priority //|< i + ,cfg_lut_uflow_priority //|< i + ,lut_data_in //|< i + ,lut_in_pvld //|< i + ,lut_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,lut_in_prdy //|> o + ,lut_out_frac //|> o + ,lut_out_le_hit //|> o + ,lut_out_lo_hit //|> o + ,lut_out_oflow //|> o + ,lut_out_pvld //|> o + ,lut_out_ram_addr //|> o + ,lut_out_ram_sel //|> o + ,lut_out_uflow //|> o + ,lut_out_x //|> o + ); +input cfg_lut_hybrid_priority; +input cfg_lut_le_function; +input [7:0] cfg_lut_le_index_offset; +input [7:0] cfg_lut_le_index_select; +input [31:0] cfg_lut_le_start; +input [7:0] cfg_lut_lo_index_select; +input [31:0] cfg_lut_lo_start; +input cfg_lut_oflow_priority; +input cfg_lut_uflow_priority; +input [31:0] lut_data_in; +input lut_in_pvld; +input lut_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output lut_in_prdy; +output [34:0] lut_out_frac; +output lut_out_le_hit; +output lut_out_lo_hit; +output lut_out_oflow; +output lut_out_pvld; +output [8:0] lut_out_ram_addr; +output lut_out_ram_sel; +output lut_out_uflow; +output [31:0] lut_out_x; +/* +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_lut_le_function; +input cfg_lut_hybrid_priority; +input cfg_lut_oflow_priority; +input cfg_lut_uflow_priority; + +input lut_in_pvld; +output lut_in_prdy; +output lut_out_pvld; +input lut_out_prdy; + +input [LUT_IDX_REG_WIDTH-1:0] cfg_lut_le_index_select; +input [LUT_IDX_REG_WIDTH-1:0] cfg_lut_lo_index_select; +input [LUT_IDX_REG_WIDTH-1:0] cfg_lut_le_index_offset; +input [LUT_REG_WIDTH-1:0] cfg_lut_le_start; +input [LUT_REG_WIDTH-1:0] cfg_lut_lo_start; +input [LUT_IN_WIDTH-1:0] lut_data_in; + +output [LUT_IN_WIDTH-1:0] lut_out_x; +output [LUT_FRAC_WIDTH-1:0] lut_out_frac; +output [LUT_ADDR_WIDTH-1:0] lut_out_ram_addr; +output lut_out_ram_sel; +output lut_out_le_hit; +output lut_out_lo_hit; +output lut_out_uflow; +output lut_out_oflow; +*/ +reg [34:0] lut_final_frac; +reg lut_final_oflow; +reg [8:0] lut_final_ram_addr; +reg lut_final_ram_sel; +reg lut_final_uflow; +wire [7:0] le_expn_cfg_offset; +wire [31:0] le_expn_cfg_start; +wire [31:0] le_expn_data_in; +wire [34:0] le_expn_frac; +wire le_expn_in_prdy; +wire le_expn_in_pvld; +wire [8:0] le_expn_index; +wire le_expn_oflow; +wire le_expn_out_prdy; +wire le_expn_out_pvld; +wire le_expn_uflow; +wire [34:0] le_frac; +wire le_hit; +wire [8:0] le_index; +wire [7:0] le_line_cfg_sel; +wire [31:0] le_line_cfg_start; +wire [31:0] le_line_data_in; +wire [34:0] le_line_frac; +wire le_line_in_prdy; +wire le_line_in_pvld; +wire [8:0] le_line_index; +wire le_line_oflow; +wire le_line_out_prdy; +wire le_line_out_pvld; +wire le_line_uflow; +wire le_miss; +wire le_oflow; +wire le_uflow; +wire [34:0] lo_frac; +wire lo_hit; +wire [8:0] lo_index; +wire [34:0] lo_line_frac; +wire lo_line_in_prdy; +wire [8:0] lo_line_index; +wire lo_line_oflow; +wire lo_line_out_pvld; +wire lo_line_uflow; +wire lo_miss; +wire lo_oflow; +wire lo_uflow; +wire [80:0] lut_final_pd; +wire lut_final_prdy; +wire lut_final_pvld; +wire [31:0] lut_final_x; +wire lut_in_xrdy; +wire [80:0] lut_out_pd; +wire lut_pipe2_prdy; +wire lut_pipe2_pvld; +wire [31:0] lut_pipe2_x; +wire lut_pipe3_pvld; +wire lut_pipe_prdy; +wire lut_pipe_pvld; +wire [31:0] lut_pipe_x; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//The same three stage pipe with lut_expn and lut_line +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_data_in (lut_data_in[31:0]) //|< i + ,.lut_in_pvld (lut_in_pvld) //|< i + ,.lut_pipe_prdy (lut_pipe_prdy) //|< w + ,.lut_in_xrdy (lut_in_xrdy) //|> w * + ,.lut_pipe_pvld (lut_pipe_pvld) //|> w + ,.lut_pipe_x (lut_pipe_x[31:0]) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_pipe2_prdy (lut_pipe2_prdy) //|< w + ,.lut_pipe_pvld (lut_pipe_pvld) //|< w + ,.lut_pipe_x (lut_pipe_x[31:0]) //|< w + ,.lut_pipe2_pvld (lut_pipe2_pvld) //|> w + ,.lut_pipe2_x (lut_pipe2_x[31:0]) //|> w + ,.lut_pipe_prdy (lut_pipe_prdy) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_final_prdy (lut_final_prdy) //|< w + ,.lut_pipe2_pvld (lut_pipe2_pvld) //|< w + ,.lut_pipe2_x (lut_pipe2_x[31:0]) //|< w + ,.lut_final_x (lut_final_x[31:0]) //|> w + ,.lut_pipe2_prdy (lut_pipe2_prdy) //|> w + ,.lut_pipe3_pvld (lut_pipe3_pvld) //|> w * + ); +NV_NVDLA_SDP_HLS_lut_expn #(.LUT_DEPTH(65 )) lut_le_expn ( + .cfg_lut_offset (le_expn_cfg_offset[7:0]) //|< w + ,.cfg_lut_start (le_expn_cfg_start[31:0]) //|< w + ,.idx_data_in (le_expn_data_in[31:0]) //|< w + ,.idx_in_pvld (le_expn_in_pvld) //|< w + ,.idx_out_prdy (le_expn_out_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_prdy (le_expn_in_prdy) //|> w + ,.idx_out_pvld (le_expn_out_pvld) //|> w + ,.lut_frac_out (le_expn_frac[34:0]) //|> w + ,.lut_index_out (le_expn_index[8:0]) //|> w + ,.lut_oflow_out (le_expn_oflow) //|> w + ,.lut_uflow_out (le_expn_uflow) //|> w + ); +NV_NVDLA_SDP_HLS_lut_line #(.LUT_DEPTH(65 )) lut_le_line ( + .cfg_lut_sel (le_line_cfg_sel[7:0]) //|< w + ,.cfg_lut_start (le_line_cfg_start[31:0]) //|< w + ,.idx_data_in (le_line_data_in[31:0]) //|< w + ,.idx_in_pvld (le_line_in_pvld) //|< w + ,.idx_out_prdy (le_line_out_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_prdy (le_line_in_prdy) //|> w + ,.idx_out_pvld (le_line_out_pvld) //|> w + ,.lut_frac_out (le_line_frac[34:0]) //|> w + ,.lut_index_out (le_line_index[8:0]) //|> w + ,.lut_oflow_out (le_line_oflow) //|> w + ,.lut_uflow_out (le_line_uflow) //|> w + ); +NV_NVDLA_SDP_HLS_lut_line #(.LUT_DEPTH(257 )) lut_lo_line ( + .cfg_lut_sel (cfg_lut_lo_index_select[7:0]) //|< i + ,.cfg_lut_start (cfg_lut_lo_start[31:0]) //|< i + ,.idx_data_in (lut_data_in[31:0]) //|< i + ,.idx_in_pvld (lut_in_pvld) //|< i + ,.idx_out_prdy (lut_final_prdy) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_prdy (lo_line_in_prdy) //|> w + ,.idx_out_pvld (lo_line_out_pvld) //|> w + ,.lut_frac_out (lo_line_frac[34:0]) //|> w + ,.lut_index_out (lo_line_index[8:0]) //|> w + ,.lut_oflow_out (lo_line_oflow) //|> w + ,.lut_uflow_out (lo_line_uflow) //|> w + ); +assign le_expn_in_pvld = (cfg_lut_le_function == 0 ) ? lut_in_pvld : 1'b0; +assign le_line_in_pvld = (cfg_lut_le_function != 0 ) ? lut_in_pvld : 1'b0; +assign le_expn_out_prdy = (cfg_lut_le_function == 0 ) ? lut_final_prdy : 1'b1; +assign le_line_out_prdy = (cfg_lut_le_function != 0 ) ? lut_final_prdy : 1'b1; +assign le_expn_data_in[31:0] = (cfg_lut_le_function == 0 ) ? lut_data_in[31:0] : {32 {1'b0}}; +assign le_expn_cfg_start[31:0] = (cfg_lut_le_function == 0 ) ? cfg_lut_le_start[31:0] : {32 {1'b0}}; +assign le_expn_cfg_offset[7:0] = (cfg_lut_le_function == 0 ) ? cfg_lut_le_index_offset[7:0] : {8 {1'b0}}; +assign le_line_data_in[31:0] = (cfg_lut_le_function != 0 ) ? lut_data_in[31:0] : {32 {1'b0}}; +assign le_line_cfg_start[31:0] = (cfg_lut_le_function != 0 ) ? cfg_lut_le_start[31:0] : {32 {1'b0}}; +assign le_line_cfg_sel[7:0] = (cfg_lut_le_function != 0 ) ? cfg_lut_le_index_select[7:0] : {8 {1'b0}}; +assign lut_in_prdy = ((cfg_lut_le_function == 0 ) ? le_expn_in_prdy : le_line_in_prdy ) & lo_line_in_prdy; +assign lut_final_pvld = ((cfg_lut_le_function == 0 ) ? le_expn_out_pvld : le_line_out_pvld) & lo_line_out_pvld; +assign le_oflow = (cfg_lut_le_function == 0 ) ? le_expn_oflow : le_line_oflow; +assign le_uflow = (cfg_lut_le_function == 0 ) ? le_expn_uflow : le_line_uflow; +assign le_index[8:0] = (cfg_lut_le_function == 0 ) ? le_expn_index[8:0] : le_line_index[8:0]; +assign le_frac[34:0] = (cfg_lut_le_function == 0 ) ? le_expn_frac[34:0] : le_line_frac[34:0]; +assign lo_oflow = lo_line_oflow; +assign lo_uflow = lo_line_uflow; +assign lo_index[8:0] = lo_line_index[8:0]; +assign lo_frac[34:0] = lo_line_frac[34:0]; +//hit miss +assign le_miss = (le_uflow | le_oflow); +assign le_hit = !le_miss; +assign lo_miss = (lo_uflow | lo_oflow); +assign lo_hit = !lo_miss; +always @( + le_uflow + or lo_uflow + or cfg_lut_uflow_priority + or lo_index + or le_index + or lo_frac + or le_frac + or le_oflow + or lo_oflow + or cfg_lut_oflow_priority + or le_hit + or lo_hit + or cfg_lut_hybrid_priority + or le_miss + or lo_miss + ) begin + if (le_uflow & lo_uflow) begin + lut_final_uflow = cfg_lut_uflow_priority ? lo_uflow : le_uflow; + lut_final_oflow = 0; + lut_final_ram_sel = cfg_lut_uflow_priority ? 1 : 0 ; + lut_final_ram_addr= cfg_lut_uflow_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_uflow_priority ? lo_frac : le_frac; + end + else if (le_oflow & lo_oflow) begin + lut_final_uflow = 0; + lut_final_oflow = cfg_lut_oflow_priority ? lo_oflow : le_oflow; + lut_final_ram_sel = cfg_lut_oflow_priority ? 1 : 0 ; + lut_final_ram_addr= cfg_lut_oflow_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_oflow_priority ? lo_frac : le_frac; + end + else if (le_hit & lo_hit) begin + lut_final_ram_addr= cfg_lut_hybrid_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_hybrid_priority ? lo_frac : le_frac; + lut_final_ram_sel = cfg_lut_hybrid_priority ? 1 : 0 ; + lut_final_uflow = 0; + lut_final_oflow = 0; + end + else if (le_miss & lo_miss) begin + lut_final_ram_addr= cfg_lut_hybrid_priority ? lo_index : le_index; + lut_final_frac = cfg_lut_hybrid_priority ? lo_frac : le_frac; + lut_final_ram_sel = cfg_lut_hybrid_priority ? 1 : 0 ; + lut_final_uflow = cfg_lut_hybrid_priority ? lo_uflow : le_uflow; + lut_final_oflow = cfg_lut_hybrid_priority ? lo_oflow : le_oflow; + end + else if (le_hit) begin + lut_final_ram_addr= le_index; + lut_final_frac = le_frac; + lut_final_ram_sel = 0 ; + lut_final_uflow = 0; + lut_final_oflow = 0; + end + else begin // if (lo_hit) begin + lut_final_ram_addr= lo_index; + lut_final_frac = lo_frac; + lut_final_ram_sel = 1 ; + lut_final_uflow = 0; + lut_final_oflow = 0; + end +end +assign lut_final_pd = {lo_hit,le_hit,lut_final_oflow,lut_final_uflow,lut_final_frac[34:0],lut_final_ram_addr[8:0],lut_final_ram_sel,lut_final_x[31:0]}; +assign {lut_out_lo_hit,lut_out_le_hit,lut_out_oflow,lut_out_uflow,lut_out_frac[34:0],lut_out_ram_addr[8:0],lut_out_ram_sel,lut_out_x[31:0]} = lut_out_pd; +NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_final_pd (lut_final_pd[80:0]) //|< w + ,.lut_final_pvld (lut_final_pvld) //|< w + ,.lut_out_prdy (lut_out_prdy) //|< i + ,.lut_final_prdy (lut_final_prdy) //|> w + ,.lut_out_pd (lut_out_pd[80:0]) //|> w + ,.lut_out_pvld (lut_out_pvld) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_Y_int_idx +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_pipe_x[31:0] (lut_pipe_pvld,lut_pipe_prdy) <= lut_data_in[31:0] (lut_in_pvld,lut_in_xrdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_data_in + ,lut_in_pvld + ,lut_pipe_prdy + ,lut_in_xrdy + ,lut_pipe_pvld + ,lut_pipe_x + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] lut_data_in; +input lut_in_pvld; +input lut_pipe_prdy; +output lut_in_xrdy; +output lut_pipe_pvld; +output [31:0] lut_pipe_x; +reg lut_in_xrdy; +reg lut_pipe_pvld; +reg [31:0] lut_pipe_x; +reg [31:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [31:0] p1_skid_data; +reg [31:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + lut_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = lut_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + lut_in_xrdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + lut_in_xrdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? lut_data_in[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or lut_in_pvld + or p1_skid_valid + or lut_data_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? lut_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? lut_data_in[31:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or lut_pipe_prdy + or p1_pipe_data + ) begin + lut_pipe_pvld = p1_pipe_valid; + p1_pipe_ready = lut_pipe_prdy; + lut_pipe_x[31:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_pipe_pvld^lut_pipe_prdy^lut_in_pvld^lut_in_xrdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (lut_in_pvld && !lut_in_xrdy), (lut_in_pvld), (lut_in_xrdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_pipe2_x[31:0] (lut_pipe2_pvld,lut_pipe2_prdy) <= lut_pipe_x[31:0] (lut_pipe_pvld,lut_pipe_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_pipe2_prdy + ,lut_pipe_pvld + ,lut_pipe_x + ,lut_pipe2_pvld + ,lut_pipe2_x + ,lut_pipe_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input lut_pipe2_prdy; +input lut_pipe_pvld; +input [31:0] lut_pipe_x; +output lut_pipe2_pvld; +output [31:0] lut_pipe2_x; +output lut_pipe_prdy; +reg lut_pipe2_pvld; +reg [31:0] lut_pipe2_x; +reg lut_pipe_prdy; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [31:0] p2_skid_data; +reg [31:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + lut_pipe_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = lut_pipe_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + lut_pipe_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + lut_pipe_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? lut_pipe_x[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or lut_pipe_pvld + or p2_skid_valid + or lut_pipe_x + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? lut_pipe_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? lut_pipe_x[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or lut_pipe2_prdy + or p2_pipe_data + ) begin + lut_pipe2_pvld = p2_pipe_valid; + p2_pipe_ready = lut_pipe2_prdy; + lut_pipe2_x[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_pipe2_pvld^lut_pipe2_prdy^lut_pipe_pvld^lut_pipe_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (lut_pipe_pvld && !lut_pipe_prdy), (lut_pipe_pvld), (lut_pipe_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_final_x[31:0] (lut_pipe3_pvld,lut_final_prdy) <= lut_pipe2_x[31:0] (lut_pipe2_pvld,lut_pipe2_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_final_prdy + ,lut_pipe2_pvld + ,lut_pipe2_x + ,lut_final_x + ,lut_pipe2_prdy + ,lut_pipe3_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input lut_final_prdy; +input lut_pipe2_pvld; +input [31:0] lut_pipe2_x; +output [31:0] lut_final_x; +output lut_pipe2_prdy; +output lut_pipe3_pvld; +reg [31:0] lut_final_x; +reg lut_pipe2_prdy; +reg lut_pipe3_pvld; +reg [31:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [31:0] p3_skid_data; +reg [31:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + lut_pipe2_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = lut_pipe2_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + lut_pipe2_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + lut_pipe2_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? lut_pipe2_x[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or lut_pipe2_pvld + or p3_skid_valid + or lut_pipe2_x + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? lut_pipe2_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? lut_pipe2_x[31:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or lut_final_prdy + or p3_pipe_data + ) begin + lut_pipe3_pvld = p3_pipe_valid; + p3_pipe_ready = lut_final_prdy; + lut_final_x[31:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_pipe3_pvld^lut_final_prdy^lut_pipe2_pvld^lut_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (lut_pipe2_pvld && !lut_pipe2_prdy), (lut_pipe2_pvld), (lut_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is lut_out_pd[80:0] (lut_out_pvld,lut_out_prdy) <= lut_final_pd[80:0] (lut_final_pvld,lut_final_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_final_pd + ,lut_final_pvld + ,lut_out_prdy + ,lut_final_prdy + ,lut_out_pd + ,lut_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [80:0] lut_final_pd; +input lut_final_pvld; +input lut_out_prdy; +output lut_final_prdy; +output [80:0] lut_out_pd; +output lut_out_pvld; +reg lut_final_prdy; +reg [80:0] lut_out_pd; +reg lut_out_pvld; +reg [80:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [80:0] p4_skid_data; +reg [80:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + lut_final_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = lut_final_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + lut_final_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + lut_final_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? lut_final_pd[80:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or lut_final_pvld + or p4_skid_valid + or lut_final_pd + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? lut_final_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? lut_final_pd[80:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or lut_out_prdy + or p4_pipe_data + ) begin + lut_out_pvld = p4_pipe_valid; + p4_pipe_ready = lut_out_prdy; + lut_out_pd[80:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (lut_out_pvld^lut_out_prdy^lut_final_pvld^lut_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (lut_final_pvld && !lut_final_prdy), (lut_final_pvld), (lut_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_IDX_pipe_p4 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_inp.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_inp.v new file mode 100644 index 0000000..c99775b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_inp.v @@ -0,0 +1,2300 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_inp.v +module NV_NVDLA_SDP_HLS_Y_int_inp ( + inp_bias_in //|< i + ,inp_flow_in //|< i + ,inp_frac_in //|< i + ,inp_in_pvld //|< i + ,inp_offset_in //|< i + ,inp_out_prdy //|< i + ,inp_scale_in //|< i + ,inp_shift_in //|< i + ,inp_x_in //|< i + ,inp_y0_in //|< i + ,inp_y1_in //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,inp_data_out //|> o + ,inp_in_prdy //|> o + ,inp_out_pvld //|> o + ); +input [31:0] inp_bias_in; +input inp_flow_in; +input [34:0] inp_frac_in; +input inp_in_pvld; +input [31:0] inp_offset_in; +input inp_out_prdy; +input [15:0] inp_scale_in; +input [4:0] inp_shift_in; +input [31:0] inp_x_in; +input [15:0] inp_y0_in; +input [15:0] inp_y1_in; +output [31:0] inp_data_out; +output inp_in_prdy; +output inp_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +wire flow_in_pipe1; +wire flow_in_pipe2; +wire flow_in_pipe3; +wire [70:0] flow_pd; +wire [70:0] flow_pd2; +wire [70:0] flow_pd2_reg; +wire [70:0] flow_pd_reg; +wire flow_pipe0_prdy; +wire flow_pipe1_prdy; +wire flow_pipe1_pvld; +wire flow_pipe2_prdy; +wire flow_pipe2_pvld; +wire flow_pipe3_pvld; +wire [34:0] frac_in; +wire [35:0] frac_remain; +wire [32:0] inp_bias_mux; +wire [31:0] inp_flow_dout; +wire inp_fout_pvld; +wire inp_in_fvld; +wire inp_in_frdy; +wire inp_in_mvld; +wire inp_in_prdy0; +wire inp_in_prdy1; +wire inp_mout_pvld; +wire [49:0] inp_mul_scale; +wire [49:0] inp_mul_scale_reg; +wire [31:0] inp_mul_tru; +wire [31:0] inp_nrm_dout; +wire [33:0] inp_ob_in; +wire [32:0] inp_offset_mux; +wire [15:0] inp_scale_reg; +wire [4:0] inp_shift_reg; +wire [4:0] inp_shift_reg2; +wire [33:0] inp_x_ext; +wire [33:0] inp_xsub; +wire [33:0] inp_xsub_reg; +wire [15:0] inp_y0_mux; +wire [15:0] inp_y0_reg; +wire [15:0] inp_y0_reg2; +wire [32:0] inp_y0_sum; +wire [32:0] inp_y0_sum_reg; +wire [52:0] intp_sum; +wire [52:0] intp_sum_reg; +wire [31:0] intp_sum_tru; +wire mon_intp_sum_c; +wire mon_xsub_c; +wire [52:0] mul0; +wire mul0_prdy; +wire mul0_pvld; +wire [52:0] mul0_reg; +wire [52:0] mul1; +wire mul1_prdy; +wire mul1_pvld; +wire [52:0] mul1_reg; +wire mul_scale_prdy; +wire mul_scale_pvld; +wire sum_in_prdy; +wire sum_in_pvld; +wire sum_out_prdy; +wire sum_out_pvld; +wire xsub_prdy; +wire xsub_pvld; +//overflow and unflow interpolation +assign inp_x_ext[33:0] = inp_flow_in ? {{2{inp_x_in[31]}}, inp_x_in[31:0]} : {32 +2 {1'b0}}; +assign inp_offset_mux[32:0] = inp_flow_in ? {inp_offset_in[32 -1],inp_offset_in[31:0]} : {(32 +1){1'b0}}; +assign inp_bias_mux[32:0] = inp_flow_in ? {1'b0,inp_bias_in[31:0]} : {(32 +1){1'b0}}; +assign inp_y0_mux[15:0] = inp_flow_in ? inp_y0_in[15:0] : {16 {1'b0}}; +assign inp_ob_in[33:0] = $signed(inp_bias_mux[32:0]) + $signed({inp_offset_mux[32:0]}); +assign {mon_xsub_c,inp_xsub[33:0]} = $signed(inp_x_ext[33:0]) - $signed(inp_ob_in[33:0]); +assign flow_pd = {inp_y0_mux[15:0],inp_shift_in[4:0],inp_scale_in[15:0],inp_xsub[33:0]}; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_pd (flow_pd[70:0]) //|< w + ,.inp_in_pvld (inp_in_fvld) //|< i + ,.inp_in_frdy (inp_in_frdy) //|> w + ,.flow_pd_reg (flow_pd_reg[70:0]) //|> w + ,.xsub_pvld (xsub_pvld) //|> w + ,.xsub_prdy (xsub_prdy) //|< w + ); +assign {inp_y0_reg[15:0],inp_shift_reg[4:0],inp_scale_reg[15:0],inp_xsub_reg[33:0]} = flow_pd_reg; +assign inp_mul_scale[49:0] = $signed(inp_xsub_reg[33:0]) * $signed(inp_scale_reg[15:0]); //morework +assign flow_pd2 = {inp_y0_reg[15:0],inp_shift_reg[4:0],inp_mul_scale[49:0]}; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_pd2 (flow_pd2[70:0]) //|< w + ,.mul_scale_prdy (mul_scale_prdy) //|< w + ,.xsub_pvld (xsub_pvld) //|< w + ,.flow_pd2_reg (flow_pd2_reg[70:0]) //|> w + ,.mul_scale_pvld (mul_scale_pvld) //|> w + ,.xsub_prdy (xsub_prdy) //|> w + ); +assign {inp_y0_reg2[15:0],inp_shift_reg2[4:0],inp_mul_scale_reg[49:0]} = flow_pd2_reg; +NV_NVDLA_HLS_shiftrightss #(.IN_WIDTH(32 + 16 + 2 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(5 )) intp_flow_shiftright_ss ( + .data_in (inp_mul_scale_reg[49:0]) //|< w + ,.shift_num (inp_shift_reg2[4:0]) //|< w + ,.data_out (inp_mul_tru[31:0]) //|> w + ); +//signed +//signed +assign inp_y0_sum[32:0] = $signed(inp_y0_reg2[15:0]) + $signed(inp_mul_tru[31:0]); //morework +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_out_prdy (inp_out_prdy) //|< i + ,.inp_y0_sum (inp_y0_sum[32:0]) //|< w + ,.mul_scale_pvld (mul_scale_pvld) //|< w + ,.inp_fout_pvld (inp_fout_pvld) //|> w + ,.inp_y0_sum_reg (inp_y0_sum_reg[32:0]) //|> w + ,.mul_scale_prdy (mul_scale_prdy) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(32 +1 ),.OUT_WIDTH(32 )) intp_flow_saturate ( + .data_in (inp_y0_sum_reg[32:0]) //|< w + ,.data_out (inp_flow_dout[31:0]) //|> w + ); +//hit interpolation +assign frac_in[34:0] = inp_flow_in ? 0 : inp_frac_in[34:0]; //unsigned +assign frac_remain[35:0] = (1 << 35 ) - frac_in[34:0]; //unsigned +assign mul0[52:0] = $signed(inp_y0_in[15:0]) *$signed({1'b0,frac_remain[35:0]}); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_in_pvld (inp_in_mvld) //|< i + ,.inp_in_prdy0 (inp_in_prdy0) //|> w + ,.mul0 (mul0[52:0]) //|< w + ,.mul0_prdy (mul0_prdy) //|< w + ,.mul0_pvld (mul0_pvld) //|> w + ,.mul0_reg (mul0_reg[52:0]) //|> w + ); +assign mul1[52:0] = $signed(inp_y1_in[15:0]) *$signed({1'b0,frac_in[34:0]}); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_in_pvld (inp_in_mvld) //|< i + ,.inp_in_prdy1 (inp_in_prdy1) //|> w + ,.mul1 (mul1[52:0]) //|< w + ,.mul1_prdy (mul1_prdy) //|< w + ,.mul1_pvld (mul1_pvld) //|> w + ,.mul1_reg (mul1_reg[52:0]) //|> w + ); +assign {mon_intp_sum_c,intp_sum[52:0]} = $signed(mul0_reg[52:0]) + $signed(mul1_reg[52:0]); +assign mul0_prdy = sum_in_prdy; +assign mul1_prdy = sum_in_prdy; +assign sum_in_pvld = mul0_pvld & mul1_pvld; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intp_sum (intp_sum[52:0]) //|< w + ,.sum_in_pvld (sum_in_pvld) //|< w + ,.sum_out_prdy (sum_out_prdy) //|< w + ,.intp_sum_reg (intp_sum_reg[52:0]) //|> w + ,.sum_in_prdy (sum_in_prdy) //|> w + ,.sum_out_pvld (sum_out_pvld) //|> w + ); +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(35 + 16 + 2 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6)) inp_shiftright_su ( + .data_in (intp_sum_reg[52:0]) //|< w + ,.shift_num (6'd35) //|< ? + ,.data_out (intp_sum_tru[31:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_out_prdy (inp_out_prdy) //|< i + ,.intp_sum_tru (intp_sum_tru[31:0]) //|< w + ,.sum_out_pvld (sum_out_pvld) //|< w + ,.inp_mout_pvld (inp_mout_pvld) //|> w + ,.inp_nrm_dout (inp_nrm_dout[31:0]) //|> w + ,.sum_out_prdy (sum_out_prdy) //|> w + ); +assign inp_in_fvld = inp_flow_in ? inp_in_pvld : 1'b0; +assign inp_in_mvld = !inp_flow_in ? inp_in_pvld : 1'b0; +assign inp_in_prdy = inp_flow_in ? inp_in_frdy : inp_in_prdy0 & inp_in_prdy1; +assign inp_data_out = flow_in_pipe3 ? inp_flow_dout : inp_nrm_dout; +assign inp_out_pvld = flow_in_pipe3 ? inp_fout_pvld : inp_mout_pvld; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p8 pipe_p8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_pipe1_prdy (flow_pipe1_prdy) //|< w + ,.inp_flow_in (inp_flow_in) //|< i + ,.inp_in_pvld (inp_in_pvld) //|< i + ,.flow_in_pipe1 (flow_in_pipe1) //|> w + ,.flow_pipe0_prdy (flow_pipe0_prdy) //|> w * + ,.flow_pipe1_pvld (flow_pipe1_pvld) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p9 pipe_p9 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_in_pipe1 (flow_in_pipe1) //|< w + ,.flow_pipe1_pvld (flow_pipe1_pvld) //|< w + ,.flow_pipe2_prdy (flow_pipe2_prdy) //|< w + ,.flow_in_pipe2 (flow_in_pipe2) //|> w + ,.flow_pipe1_prdy (flow_pipe1_prdy) //|> w + ,.flow_pipe2_pvld (flow_pipe2_pvld) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p10 pipe_p10 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_in_pipe2 (flow_in_pipe2) //|< w + ,.flow_pipe2_pvld (flow_pipe2_pvld) //|< w + ,.inp_out_prdy (inp_out_prdy) //|< i + ,.flow_in_pipe3 (flow_in_pipe3) //|> w + ,.flow_pipe2_prdy (flow_pipe2_prdy) //|> w + ,.flow_pipe3_pvld (flow_pipe3_pvld) //|> w * + ); +endmodule // NV_NVDLA_SDP_HLS_Y_int_inp +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_pd_reg[70:0] (xsub_pvld,xsub_prdy) <= flow_pd[70:0] (inp_in_pvld,inp_in_frdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_pd + ,inp_in_pvld + ,xsub_prdy + ,flow_pd_reg + ,inp_in_frdy + ,xsub_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [70:0] flow_pd; +input inp_in_pvld; +input xsub_prdy; +output [70:0] flow_pd_reg; +output inp_in_frdy; +output xsub_pvld; +reg [70:0] flow_pd_reg; +reg inp_in_frdy; +reg [70:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [70:0] p1_skid_data; +reg [70:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg xsub_pvld; +//## pipe (1) skid buffer +always @( + inp_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = inp_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + inp_in_frdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + inp_in_frdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? flow_pd[70:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or inp_in_pvld + or p1_skid_valid + or flow_pd + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? inp_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? flow_pd[70:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or xsub_prdy + or p1_pipe_data + ) begin + xsub_pvld = p1_pipe_valid; + p1_pipe_ready = xsub_prdy; + flow_pd_reg[70:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (xsub_pvld^xsub_prdy^inp_in_pvld^inp_in_frdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !inp_in_frdy), (inp_in_pvld), (inp_in_frdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_pd2_reg[70:0] (mul_scale_pvld,mul_scale_prdy) <= flow_pd2[70:0] (xsub_pvld,xsub_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_pd2 + ,mul_scale_prdy + ,xsub_pvld + ,flow_pd2_reg + ,mul_scale_pvld + ,xsub_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [70:0] flow_pd2; +input mul_scale_prdy; +input xsub_pvld; +output [70:0] flow_pd2_reg; +output mul_scale_pvld; +output xsub_prdy; +reg [70:0] flow_pd2_reg; +reg mul_scale_pvld; +reg [70:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [70:0] p2_skid_data; +reg [70:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg xsub_prdy; +//## pipe (2) skid buffer +always @( + xsub_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = xsub_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + xsub_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + xsub_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? flow_pd2[70:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or xsub_pvld + or p2_skid_valid + or flow_pd2 + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? xsub_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? flow_pd2[70:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_scale_prdy + or p2_pipe_data + ) begin + mul_scale_pvld = p2_pipe_valid; + p2_pipe_ready = mul_scale_prdy; + flow_pd2_reg[70:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_scale_pvld^mul_scale_prdy^xsub_pvld^xsub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (xsub_pvld && !xsub_prdy), (xsub_pvld), (xsub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is inp_y0_sum_reg[32:0] (inp_fout_pvld,inp_out_prdy) <= inp_y0_sum[32:0] (mul_scale_pvld,mul_scale_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_out_prdy + ,inp_y0_sum + ,mul_scale_pvld + ,inp_fout_pvld + ,inp_y0_sum_reg + ,mul_scale_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_out_prdy; +input [32:0] inp_y0_sum; +input mul_scale_pvld; +output inp_fout_pvld; +output [32:0] inp_y0_sum_reg; +output mul_scale_prdy; +reg inp_fout_pvld; +reg [32:0] inp_y0_sum_reg; +reg mul_scale_prdy; +reg [32:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [32:0] p3_skid_data; +reg [32:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + mul_scale_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_scale_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_scale_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_scale_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? inp_y0_sum[32:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_scale_pvld + or p3_skid_valid + or inp_y0_sum + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_scale_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? inp_y0_sum[32:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or inp_out_prdy + or p3_pipe_data + ) begin + inp_fout_pvld = p3_pipe_valid; + p3_pipe_ready = inp_out_prdy; + inp_y0_sum_reg[32:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (inp_fout_pvld^inp_out_prdy^mul_scale_pvld^mul_scale_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_scale_pvld && !mul_scale_prdy), (mul_scale_pvld), (mul_scale_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul0_reg[52:0] (mul0_pvld,mul0_prdy) <= mul0[52:0] (inp_in_pvld,inp_in_prdy0) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_in_pvld + ,mul0 + ,mul0_prdy + ,inp_in_prdy0 + ,mul0_pvld + ,mul0_reg + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_in_pvld; +input [52:0] mul0; +input mul0_prdy; +output inp_in_prdy0; +output mul0_pvld; +output [52:0] mul0_reg; +reg inp_in_prdy0; +reg mul0_pvld; +reg [52:0] mul0_reg; +reg [52:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [52:0] p4_skid_data; +reg [52:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + inp_in_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = inp_in_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + inp_in_prdy0 <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + inp_in_prdy0 <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? mul0[52:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or inp_in_pvld + or p4_skid_valid + or mul0 + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? inp_in_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? mul0[52:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or mul0_prdy + or p4_pipe_data + ) begin + mul0_pvld = p4_pipe_valid; + p4_pipe_ready = mul0_prdy; + mul0_reg[52:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul0_pvld^mul0_prdy^inp_in_pvld^inp_in_prdy0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !inp_in_prdy0), (inp_in_pvld), (inp_in_prdy0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul1_reg[52:0] (mul1_pvld,mul1_prdy) <= mul1[52:0] (inp_in_pvld,inp_in_prdy1) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_in_pvld + ,mul1 + ,mul1_prdy + ,inp_in_prdy1 + ,mul1_pvld + ,mul1_reg + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_in_pvld; +input [52:0] mul1; +input mul1_prdy; +output inp_in_prdy1; +output mul1_pvld; +output [52:0] mul1_reg; +reg inp_in_prdy1; +reg mul1_pvld; +reg [52:0] mul1_reg; +reg [52:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [52:0] p5_skid_data; +reg [52:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +//## pipe (5) skid buffer +always @( + inp_in_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = inp_in_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + inp_in_prdy1 <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + inp_in_prdy1 <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? mul1[52:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or inp_in_pvld + or p5_skid_valid + or mul1 + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? inp_in_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? mul1[52:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mul1_prdy + or p5_pipe_data + ) begin + mul1_pvld = p5_pipe_valid; + p5_pipe_ready = mul1_prdy; + mul1_reg[52:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul1_pvld^mul1_prdy^inp_in_pvld^inp_in_prdy1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !inp_in_prdy1), (inp_in_pvld), (inp_in_prdy1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is intp_sum_reg[52:0] (sum_out_pvld,sum_out_prdy) <= intp_sum[52:0] (sum_in_pvld,sum_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,intp_sum + ,sum_in_pvld + ,sum_out_prdy + ,intp_sum_reg + ,sum_in_prdy + ,sum_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [52:0] intp_sum; +input sum_in_pvld; +input sum_out_prdy; +output [52:0] intp_sum_reg; +output sum_in_prdy; +output sum_out_pvld; +reg [52:0] intp_sum_reg; +reg [52:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg p6_skid_catch; +reg [52:0] p6_skid_data; +reg [52:0] p6_skid_pipe_data; +reg p6_skid_pipe_ready; +reg p6_skid_pipe_valid; +reg p6_skid_ready; +reg p6_skid_ready_flop; +reg p6_skid_valid; +reg sum_in_prdy; +reg sum_out_pvld; +//## pipe (6) skid buffer +always @( + sum_in_pvld + or p6_skid_ready_flop + or p6_skid_pipe_ready + or p6_skid_valid + ) begin + p6_skid_catch = sum_in_pvld && p6_skid_ready_flop && !p6_skid_pipe_ready; + p6_skid_ready = (p6_skid_valid)? p6_skid_pipe_ready : !p6_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_skid_valid <= 1'b0; + p6_skid_ready_flop <= 1'b1; + sum_in_prdy <= 1'b1; + end else begin + p6_skid_valid <= (p6_skid_valid)? !p6_skid_pipe_ready : p6_skid_catch; + p6_skid_ready_flop <= p6_skid_ready; + sum_in_prdy <= p6_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_skid_data <= (p6_skid_catch)? intp_sum[52:0] : p6_skid_data; +// VCS sop_coverage_off end +end +always @( + p6_skid_ready_flop + or sum_in_pvld + or p6_skid_valid + or intp_sum + or p6_skid_data + ) begin + p6_skid_pipe_valid = (p6_skid_ready_flop)? sum_in_pvld : p6_skid_valid; +// VCS sop_coverage_off start + p6_skid_pipe_data = (p6_skid_ready_flop)? intp_sum[52:0] : p6_skid_data; +// VCS sop_coverage_off end +end +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? p6_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && p6_skid_pipe_valid)? p6_skid_pipe_data : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + p6_skid_pipe_ready = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or sum_out_prdy + or p6_pipe_data + ) begin + sum_out_pvld = p6_pipe_valid; + p6_pipe_ready = sum_out_prdy; + intp_sum_reg[52:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sum_out_pvld^sum_out_prdy^sum_in_pvld^sum_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (sum_in_pvld && !sum_in_prdy), (sum_in_pvld), (sum_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is inp_nrm_dout[31:0] (inp_mout_pvld,inp_out_prdy) <= intp_sum_tru[31:0] (sum_out_pvld,sum_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_out_prdy + ,intp_sum_tru + ,sum_out_pvld + ,inp_mout_pvld + ,inp_nrm_dout + ,sum_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_out_prdy; +input [31:0] intp_sum_tru; +input sum_out_pvld; +output inp_mout_pvld; +output [31:0] inp_nrm_dout; +output sum_out_prdy; +reg inp_mout_pvld; +reg [31:0] inp_nrm_dout; +reg [31:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +reg p7_skid_catch; +reg [31:0] p7_skid_data; +reg [31:0] p7_skid_pipe_data; +reg p7_skid_pipe_ready; +reg p7_skid_pipe_valid; +reg p7_skid_ready; +reg p7_skid_ready_flop; +reg p7_skid_valid; +reg sum_out_prdy; +//## pipe (7) skid buffer +always @( + sum_out_pvld + or p7_skid_ready_flop + or p7_skid_pipe_ready + or p7_skid_valid + ) begin + p7_skid_catch = sum_out_pvld && p7_skid_ready_flop && !p7_skid_pipe_ready; + p7_skid_ready = (p7_skid_valid)? p7_skid_pipe_ready : !p7_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_skid_valid <= 1'b0; + p7_skid_ready_flop <= 1'b1; + sum_out_prdy <= 1'b1; + end else begin + p7_skid_valid <= (p7_skid_valid)? !p7_skid_pipe_ready : p7_skid_catch; + p7_skid_ready_flop <= p7_skid_ready; + sum_out_prdy <= p7_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_skid_data <= (p7_skid_catch)? intp_sum_tru[31:0] : p7_skid_data; +// VCS sop_coverage_off end +end +always @( + p7_skid_ready_flop + or sum_out_pvld + or p7_skid_valid + or intp_sum_tru + or p7_skid_data + ) begin + p7_skid_pipe_valid = (p7_skid_ready_flop)? sum_out_pvld : p7_skid_valid; +// VCS sop_coverage_off start + p7_skid_pipe_data = (p7_skid_ready_flop)? intp_sum_tru[31:0] : p7_skid_data; +// VCS sop_coverage_off end +end +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? p7_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && p7_skid_pipe_valid)? p7_skid_pipe_data : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + p7_skid_pipe_ready = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or inp_out_prdy + or p7_pipe_data + ) begin + inp_mout_pvld = p7_pipe_valid; + p7_pipe_ready = inp_out_prdy; + inp_nrm_dout[31:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (inp_mout_pvld^inp_out_prdy^sum_out_pvld^sum_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (sum_out_pvld && !sum_out_prdy), (sum_out_pvld), (sum_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p7 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_in_pipe1 (flow_pipe1_pvld,flow_pipe1_prdy) <= inp_flow_in (inp_in_pvld, flow_pipe0_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_pipe1_prdy + ,inp_flow_in + ,inp_in_pvld + ,flow_in_pipe1 + ,flow_pipe0_prdy + ,flow_pipe1_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input flow_pipe1_prdy; +input inp_flow_in; +input inp_in_pvld; +output flow_in_pipe1; +output flow_pipe0_prdy; +output flow_pipe1_pvld; +reg flow_in_pipe1; +reg flow_pipe0_prdy; +reg flow_pipe1_pvld; +reg p8_pipe_data; +reg p8_pipe_ready; +reg p8_pipe_ready_bc; +reg p8_pipe_valid; +reg p8_skid_catch; +reg p8_skid_data; +reg p8_skid_pipe_data; +reg p8_skid_pipe_ready; +reg p8_skid_pipe_valid; +reg p8_skid_ready; +reg p8_skid_ready_flop; +reg p8_skid_valid; +//## pipe (8) skid buffer +always @( + inp_in_pvld + or p8_skid_ready_flop + or p8_skid_pipe_ready + or p8_skid_valid + ) begin + p8_skid_catch = inp_in_pvld && p8_skid_ready_flop && !p8_skid_pipe_ready; + p8_skid_ready = (p8_skid_valid)? p8_skid_pipe_ready : !p8_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_skid_valid <= 1'b0; + p8_skid_ready_flop <= 1'b1; + flow_pipe0_prdy <= 1'b1; + end else begin + p8_skid_valid <= (p8_skid_valid)? !p8_skid_pipe_ready : p8_skid_catch; + p8_skid_ready_flop <= p8_skid_ready; + flow_pipe0_prdy <= p8_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_skid_data <= (p8_skid_catch)? inp_flow_in : p8_skid_data; +// VCS sop_coverage_off end +end +always @( + p8_skid_ready_flop + or inp_in_pvld + or p8_skid_valid + or inp_flow_in + or p8_skid_data + ) begin + p8_skid_pipe_valid = (p8_skid_ready_flop)? inp_in_pvld : p8_skid_valid; +// VCS sop_coverage_off start + p8_skid_pipe_data = (p8_skid_ready_flop)? inp_flow_in : p8_skid_data; +// VCS sop_coverage_off end +end +//## pipe (8) valid-ready-bubble-collapse +always @( + p8_pipe_ready + or p8_pipe_valid + ) begin + p8_pipe_ready_bc = p8_pipe_ready || !p8_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_pipe_valid <= 1'b0; + end else begin + p8_pipe_valid <= (p8_pipe_ready_bc)? p8_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_pipe_data <= (p8_pipe_ready_bc && p8_skid_pipe_valid)? p8_skid_pipe_data : p8_pipe_data; +// VCS sop_coverage_off end +end +always @( + p8_pipe_ready_bc + ) begin + p8_skid_pipe_ready = p8_pipe_ready_bc; +end +//## pipe (8) output +always @( + p8_pipe_valid + or flow_pipe1_prdy + or p8_pipe_data + ) begin + flow_pipe1_pvld = p8_pipe_valid; + p8_pipe_ready = flow_pipe1_prdy; + flow_in_pipe1 = p8_pipe_data; +end +//## pipe (8) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p8_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (flow_pipe1_pvld^flow_pipe1_prdy^inp_in_pvld^flow_pipe0_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !flow_pipe0_prdy), (inp_in_pvld), (flow_pipe0_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p8 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_in_pipe2 (flow_pipe2_pvld,flow_pipe2_prdy) <= flow_in_pipe1 (flow_pipe1_pvld,flow_pipe1_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p9 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_in_pipe1 + ,flow_pipe1_pvld + ,flow_pipe2_prdy + ,flow_in_pipe2 + ,flow_pipe1_prdy + ,flow_pipe2_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input flow_in_pipe1; +input flow_pipe1_pvld; +input flow_pipe2_prdy; +output flow_in_pipe2; +output flow_pipe1_prdy; +output flow_pipe2_pvld; +reg flow_in_pipe2; +reg flow_pipe1_prdy; +reg flow_pipe2_pvld; +reg p9_pipe_data; +reg p9_pipe_ready; +reg p9_pipe_ready_bc; +reg p9_pipe_valid; +reg p9_skid_catch; +reg p9_skid_data; +reg p9_skid_pipe_data; +reg p9_skid_pipe_ready; +reg p9_skid_pipe_valid; +reg p9_skid_ready; +reg p9_skid_ready_flop; +reg p9_skid_valid; +//## pipe (9) skid buffer +always @( + flow_pipe1_pvld + or p9_skid_ready_flop + or p9_skid_pipe_ready + or p9_skid_valid + ) begin + p9_skid_catch = flow_pipe1_pvld && p9_skid_ready_flop && !p9_skid_pipe_ready; + p9_skid_ready = (p9_skid_valid)? p9_skid_pipe_ready : !p9_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p9_skid_valid <= 1'b0; + p9_skid_ready_flop <= 1'b1; + flow_pipe1_prdy <= 1'b1; + end else begin + p9_skid_valid <= (p9_skid_valid)? !p9_skid_pipe_ready : p9_skid_catch; + p9_skid_ready_flop <= p9_skid_ready; + flow_pipe1_prdy <= p9_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p9_skid_data <= (p9_skid_catch)? flow_in_pipe1 : p9_skid_data; +// VCS sop_coverage_off end +end +always @( + p9_skid_ready_flop + or flow_pipe1_pvld + or p9_skid_valid + or flow_in_pipe1 + or p9_skid_data + ) begin + p9_skid_pipe_valid = (p9_skid_ready_flop)? flow_pipe1_pvld : p9_skid_valid; +// VCS sop_coverage_off start + p9_skid_pipe_data = (p9_skid_ready_flop)? flow_in_pipe1 : p9_skid_data; +// VCS sop_coverage_off end +end +//## pipe (9) valid-ready-bubble-collapse +always @( + p9_pipe_ready + or p9_pipe_valid + ) begin + p9_pipe_ready_bc = p9_pipe_ready || !p9_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p9_pipe_valid <= 1'b0; + end else begin + p9_pipe_valid <= (p9_pipe_ready_bc)? p9_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p9_pipe_data <= (p9_pipe_ready_bc && p9_skid_pipe_valid)? p9_skid_pipe_data : p9_pipe_data; +// VCS sop_coverage_off end +end +always @( + p9_pipe_ready_bc + ) begin + p9_skid_pipe_ready = p9_pipe_ready_bc; +end +//## pipe (9) output +always @( + p9_pipe_valid + or flow_pipe2_prdy + or p9_pipe_data + ) begin + flow_pipe2_pvld = p9_pipe_valid; + p9_pipe_ready = flow_pipe2_prdy; + flow_in_pipe2 = p9_pipe_data; +end +//## pipe (9) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p9_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (flow_pipe2_pvld^flow_pipe2_prdy^flow_pipe1_pvld^flow_pipe1_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_18x (nvdla_core_clk, `ASSERT_RESET, (flow_pipe1_pvld && !flow_pipe1_prdy), (flow_pipe1_pvld), (flow_pipe1_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p9 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_in_pipe3 (flow_pipe3_pvld,inp_out_prdy) <= flow_in_pipe2 (flow_pipe2_pvld,flow_pipe2_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p10 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_in_pipe2 + ,flow_pipe2_pvld + ,inp_out_prdy + ,flow_in_pipe3 + ,flow_pipe2_prdy + ,flow_pipe3_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input flow_in_pipe2; +input flow_pipe2_pvld; +input inp_out_prdy; +output flow_in_pipe3; +output flow_pipe2_prdy; +output flow_pipe3_pvld; +reg flow_in_pipe3; +reg flow_pipe2_prdy; +reg flow_pipe3_pvld; +reg p10_pipe_data; +reg p10_pipe_ready; +reg p10_pipe_ready_bc; +reg p10_pipe_valid; +reg p10_skid_catch; +reg p10_skid_data; +reg p10_skid_pipe_data; +reg p10_skid_pipe_ready; +reg p10_skid_pipe_valid; +reg p10_skid_ready; +reg p10_skid_ready_flop; +reg p10_skid_valid; +//## pipe (10) skid buffer +always @( + flow_pipe2_pvld + or p10_skid_ready_flop + or p10_skid_pipe_ready + or p10_skid_valid + ) begin + p10_skid_catch = flow_pipe2_pvld && p10_skid_ready_flop && !p10_skid_pipe_ready; + p10_skid_ready = (p10_skid_valid)? p10_skid_pipe_ready : !p10_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p10_skid_valid <= 1'b0; + p10_skid_ready_flop <= 1'b1; + flow_pipe2_prdy <= 1'b1; + end else begin + p10_skid_valid <= (p10_skid_valid)? !p10_skid_pipe_ready : p10_skid_catch; + p10_skid_ready_flop <= p10_skid_ready; + flow_pipe2_prdy <= p10_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p10_skid_data <= (p10_skid_catch)? flow_in_pipe2 : p10_skid_data; +// VCS sop_coverage_off end +end +always @( + p10_skid_ready_flop + or flow_pipe2_pvld + or p10_skid_valid + or flow_in_pipe2 + or p10_skid_data + ) begin + p10_skid_pipe_valid = (p10_skid_ready_flop)? flow_pipe2_pvld : p10_skid_valid; +// VCS sop_coverage_off start + p10_skid_pipe_data = (p10_skid_ready_flop)? flow_in_pipe2 : p10_skid_data; +// VCS sop_coverage_off end +end +//## pipe (10) valid-ready-bubble-collapse +always @( + p10_pipe_ready + or p10_pipe_valid + ) begin + p10_pipe_ready_bc = p10_pipe_ready || !p10_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p10_pipe_valid <= 1'b0; + end else begin + p10_pipe_valid <= (p10_pipe_ready_bc)? p10_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p10_pipe_data <= (p10_pipe_ready_bc && p10_skid_pipe_valid)? p10_skid_pipe_data : p10_pipe_data; +// VCS sop_coverage_off end +end +always @( + p10_pipe_ready_bc + ) begin + p10_skid_pipe_ready = p10_pipe_ready_bc; +end +//## pipe (10) output +always @( + p10_pipe_valid + or inp_out_prdy + or p10_pipe_data + ) begin + flow_pipe3_pvld = p10_pipe_valid; + p10_pipe_ready = inp_out_prdy; + flow_in_pipe3 = p10_pipe_data; +end +//## pipe (10) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p10_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (flow_pipe3_pvld^inp_out_prdy^flow_pipe2_pvld^flow_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_20x (nvdla_core_clk, `ASSERT_RESET, (flow_pipe2_pvld && !flow_pipe2_prdy), (flow_pipe2_pvld), (flow_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p10 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_inp.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_inp.v.vcp new file mode 100644 index 0000000..c99775b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_inp.v.vcp @@ -0,0 +1,2300 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_inp.v +module NV_NVDLA_SDP_HLS_Y_int_inp ( + inp_bias_in //|< i + ,inp_flow_in //|< i + ,inp_frac_in //|< i + ,inp_in_pvld //|< i + ,inp_offset_in //|< i + ,inp_out_prdy //|< i + ,inp_scale_in //|< i + ,inp_shift_in //|< i + ,inp_x_in //|< i + ,inp_y0_in //|< i + ,inp_y1_in //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,inp_data_out //|> o + ,inp_in_prdy //|> o + ,inp_out_pvld //|> o + ); +input [31:0] inp_bias_in; +input inp_flow_in; +input [34:0] inp_frac_in; +input inp_in_pvld; +input [31:0] inp_offset_in; +input inp_out_prdy; +input [15:0] inp_scale_in; +input [4:0] inp_shift_in; +input [31:0] inp_x_in; +input [15:0] inp_y0_in; +input [15:0] inp_y1_in; +output [31:0] inp_data_out; +output inp_in_prdy; +output inp_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +wire flow_in_pipe1; +wire flow_in_pipe2; +wire flow_in_pipe3; +wire [70:0] flow_pd; +wire [70:0] flow_pd2; +wire [70:0] flow_pd2_reg; +wire [70:0] flow_pd_reg; +wire flow_pipe0_prdy; +wire flow_pipe1_prdy; +wire flow_pipe1_pvld; +wire flow_pipe2_prdy; +wire flow_pipe2_pvld; +wire flow_pipe3_pvld; +wire [34:0] frac_in; +wire [35:0] frac_remain; +wire [32:0] inp_bias_mux; +wire [31:0] inp_flow_dout; +wire inp_fout_pvld; +wire inp_in_fvld; +wire inp_in_frdy; +wire inp_in_mvld; +wire inp_in_prdy0; +wire inp_in_prdy1; +wire inp_mout_pvld; +wire [49:0] inp_mul_scale; +wire [49:0] inp_mul_scale_reg; +wire [31:0] inp_mul_tru; +wire [31:0] inp_nrm_dout; +wire [33:0] inp_ob_in; +wire [32:0] inp_offset_mux; +wire [15:0] inp_scale_reg; +wire [4:0] inp_shift_reg; +wire [4:0] inp_shift_reg2; +wire [33:0] inp_x_ext; +wire [33:0] inp_xsub; +wire [33:0] inp_xsub_reg; +wire [15:0] inp_y0_mux; +wire [15:0] inp_y0_reg; +wire [15:0] inp_y0_reg2; +wire [32:0] inp_y0_sum; +wire [32:0] inp_y0_sum_reg; +wire [52:0] intp_sum; +wire [52:0] intp_sum_reg; +wire [31:0] intp_sum_tru; +wire mon_intp_sum_c; +wire mon_xsub_c; +wire [52:0] mul0; +wire mul0_prdy; +wire mul0_pvld; +wire [52:0] mul0_reg; +wire [52:0] mul1; +wire mul1_prdy; +wire mul1_pvld; +wire [52:0] mul1_reg; +wire mul_scale_prdy; +wire mul_scale_pvld; +wire sum_in_prdy; +wire sum_in_pvld; +wire sum_out_prdy; +wire sum_out_pvld; +wire xsub_prdy; +wire xsub_pvld; +//overflow and unflow interpolation +assign inp_x_ext[33:0] = inp_flow_in ? {{2{inp_x_in[31]}}, inp_x_in[31:0]} : {32 +2 {1'b0}}; +assign inp_offset_mux[32:0] = inp_flow_in ? {inp_offset_in[32 -1],inp_offset_in[31:0]} : {(32 +1){1'b0}}; +assign inp_bias_mux[32:0] = inp_flow_in ? {1'b0,inp_bias_in[31:0]} : {(32 +1){1'b0}}; +assign inp_y0_mux[15:0] = inp_flow_in ? inp_y0_in[15:0] : {16 {1'b0}}; +assign inp_ob_in[33:0] = $signed(inp_bias_mux[32:0]) + $signed({inp_offset_mux[32:0]}); +assign {mon_xsub_c,inp_xsub[33:0]} = $signed(inp_x_ext[33:0]) - $signed(inp_ob_in[33:0]); +assign flow_pd = {inp_y0_mux[15:0],inp_shift_in[4:0],inp_scale_in[15:0],inp_xsub[33:0]}; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_pd (flow_pd[70:0]) //|< w + ,.inp_in_pvld (inp_in_fvld) //|< i + ,.inp_in_frdy (inp_in_frdy) //|> w + ,.flow_pd_reg (flow_pd_reg[70:0]) //|> w + ,.xsub_pvld (xsub_pvld) //|> w + ,.xsub_prdy (xsub_prdy) //|< w + ); +assign {inp_y0_reg[15:0],inp_shift_reg[4:0],inp_scale_reg[15:0],inp_xsub_reg[33:0]} = flow_pd_reg; +assign inp_mul_scale[49:0] = $signed(inp_xsub_reg[33:0]) * $signed(inp_scale_reg[15:0]); //morework +assign flow_pd2 = {inp_y0_reg[15:0],inp_shift_reg[4:0],inp_mul_scale[49:0]}; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_pd2 (flow_pd2[70:0]) //|< w + ,.mul_scale_prdy (mul_scale_prdy) //|< w + ,.xsub_pvld (xsub_pvld) //|< w + ,.flow_pd2_reg (flow_pd2_reg[70:0]) //|> w + ,.mul_scale_pvld (mul_scale_pvld) //|> w + ,.xsub_prdy (xsub_prdy) //|> w + ); +assign {inp_y0_reg2[15:0],inp_shift_reg2[4:0],inp_mul_scale_reg[49:0]} = flow_pd2_reg; +NV_NVDLA_HLS_shiftrightss #(.IN_WIDTH(32 + 16 + 2 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(5 )) intp_flow_shiftright_ss ( + .data_in (inp_mul_scale_reg[49:0]) //|< w + ,.shift_num (inp_shift_reg2[4:0]) //|< w + ,.data_out (inp_mul_tru[31:0]) //|> w + ); +//signed +//signed +assign inp_y0_sum[32:0] = $signed(inp_y0_reg2[15:0]) + $signed(inp_mul_tru[31:0]); //morework +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_out_prdy (inp_out_prdy) //|< i + ,.inp_y0_sum (inp_y0_sum[32:0]) //|< w + ,.mul_scale_pvld (mul_scale_pvld) //|< w + ,.inp_fout_pvld (inp_fout_pvld) //|> w + ,.inp_y0_sum_reg (inp_y0_sum_reg[32:0]) //|> w + ,.mul_scale_prdy (mul_scale_prdy) //|> w + ); +NV_NVDLA_HLS_saturate #(.IN_WIDTH(32 +1 ),.OUT_WIDTH(32 )) intp_flow_saturate ( + .data_in (inp_y0_sum_reg[32:0]) //|< w + ,.data_out (inp_flow_dout[31:0]) //|> w + ); +//hit interpolation +assign frac_in[34:0] = inp_flow_in ? 0 : inp_frac_in[34:0]; //unsigned +assign frac_remain[35:0] = (1 << 35 ) - frac_in[34:0]; //unsigned +assign mul0[52:0] = $signed(inp_y0_in[15:0]) *$signed({1'b0,frac_remain[35:0]}); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_in_pvld (inp_in_mvld) //|< i + ,.inp_in_prdy0 (inp_in_prdy0) //|> w + ,.mul0 (mul0[52:0]) //|< w + ,.mul0_prdy (mul0_prdy) //|< w + ,.mul0_pvld (mul0_pvld) //|> w + ,.mul0_reg (mul0_reg[52:0]) //|> w + ); +assign mul1[52:0] = $signed(inp_y1_in[15:0]) *$signed({1'b0,frac_in[34:0]}); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_in_pvld (inp_in_mvld) //|< i + ,.inp_in_prdy1 (inp_in_prdy1) //|> w + ,.mul1 (mul1[52:0]) //|< w + ,.mul1_prdy (mul1_prdy) //|< w + ,.mul1_pvld (mul1_pvld) //|> w + ,.mul1_reg (mul1_reg[52:0]) //|> w + ); +assign {mon_intp_sum_c,intp_sum[52:0]} = $signed(mul0_reg[52:0]) + $signed(mul1_reg[52:0]); +assign mul0_prdy = sum_in_prdy; +assign mul1_prdy = sum_in_prdy; +assign sum_in_pvld = mul0_pvld & mul1_pvld; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intp_sum (intp_sum[52:0]) //|< w + ,.sum_in_pvld (sum_in_pvld) //|< w + ,.sum_out_prdy (sum_out_prdy) //|< w + ,.intp_sum_reg (intp_sum_reg[52:0]) //|> w + ,.sum_in_prdy (sum_in_prdy) //|> w + ,.sum_out_pvld (sum_out_pvld) //|> w + ); +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(35 + 16 + 2 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(6)) inp_shiftright_su ( + .data_in (intp_sum_reg[52:0]) //|< w + ,.shift_num (6'd35) //|< ? + ,.data_out (intp_sum_tru[31:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_out_prdy (inp_out_prdy) //|< i + ,.intp_sum_tru (intp_sum_tru[31:0]) //|< w + ,.sum_out_pvld (sum_out_pvld) //|< w + ,.inp_mout_pvld (inp_mout_pvld) //|> w + ,.inp_nrm_dout (inp_nrm_dout[31:0]) //|> w + ,.sum_out_prdy (sum_out_prdy) //|> w + ); +assign inp_in_fvld = inp_flow_in ? inp_in_pvld : 1'b0; +assign inp_in_mvld = !inp_flow_in ? inp_in_pvld : 1'b0; +assign inp_in_prdy = inp_flow_in ? inp_in_frdy : inp_in_prdy0 & inp_in_prdy1; +assign inp_data_out = flow_in_pipe3 ? inp_flow_dout : inp_nrm_dout; +assign inp_out_pvld = flow_in_pipe3 ? inp_fout_pvld : inp_mout_pvld; +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p8 pipe_p8 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_pipe1_prdy (flow_pipe1_prdy) //|< w + ,.inp_flow_in (inp_flow_in) //|< i + ,.inp_in_pvld (inp_in_pvld) //|< i + ,.flow_in_pipe1 (flow_in_pipe1) //|> w + ,.flow_pipe0_prdy (flow_pipe0_prdy) //|> w * + ,.flow_pipe1_pvld (flow_pipe1_pvld) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p9 pipe_p9 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_in_pipe1 (flow_in_pipe1) //|< w + ,.flow_pipe1_pvld (flow_pipe1_pvld) //|< w + ,.flow_pipe2_prdy (flow_pipe2_prdy) //|< w + ,.flow_in_pipe2 (flow_in_pipe2) //|> w + ,.flow_pipe1_prdy (flow_pipe1_prdy) //|> w + ,.flow_pipe2_pvld (flow_pipe2_pvld) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p10 pipe_p10 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.flow_in_pipe2 (flow_in_pipe2) //|< w + ,.flow_pipe2_pvld (flow_pipe2_pvld) //|< w + ,.inp_out_prdy (inp_out_prdy) //|< i + ,.flow_in_pipe3 (flow_in_pipe3) //|> w + ,.flow_pipe2_prdy (flow_pipe2_prdy) //|> w + ,.flow_pipe3_pvld (flow_pipe3_pvld) //|> w * + ); +endmodule // NV_NVDLA_SDP_HLS_Y_int_inp +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_pd_reg[70:0] (xsub_pvld,xsub_prdy) <= flow_pd[70:0] (inp_in_pvld,inp_in_frdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_pd + ,inp_in_pvld + ,xsub_prdy + ,flow_pd_reg + ,inp_in_frdy + ,xsub_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [70:0] flow_pd; +input inp_in_pvld; +input xsub_prdy; +output [70:0] flow_pd_reg; +output inp_in_frdy; +output xsub_pvld; +reg [70:0] flow_pd_reg; +reg inp_in_frdy; +reg [70:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [70:0] p1_skid_data; +reg [70:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg xsub_pvld; +//## pipe (1) skid buffer +always @( + inp_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = inp_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + inp_in_frdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + inp_in_frdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? flow_pd[70:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or inp_in_pvld + or p1_skid_valid + or flow_pd + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? inp_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? flow_pd[70:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or xsub_prdy + or p1_pipe_data + ) begin + xsub_pvld = p1_pipe_valid; + p1_pipe_ready = xsub_prdy; + flow_pd_reg[70:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (xsub_pvld^xsub_prdy^inp_in_pvld^inp_in_frdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !inp_in_frdy), (inp_in_pvld), (inp_in_frdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_pd2_reg[70:0] (mul_scale_pvld,mul_scale_prdy) <= flow_pd2[70:0] (xsub_pvld,xsub_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_pd2 + ,mul_scale_prdy + ,xsub_pvld + ,flow_pd2_reg + ,mul_scale_pvld + ,xsub_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [70:0] flow_pd2; +input mul_scale_prdy; +input xsub_pvld; +output [70:0] flow_pd2_reg; +output mul_scale_pvld; +output xsub_prdy; +reg [70:0] flow_pd2_reg; +reg mul_scale_pvld; +reg [70:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [70:0] p2_skid_data; +reg [70:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg xsub_prdy; +//## pipe (2) skid buffer +always @( + xsub_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = xsub_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + xsub_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + xsub_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? flow_pd2[70:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or xsub_pvld + or p2_skid_valid + or flow_pd2 + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? xsub_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? flow_pd2[70:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_scale_prdy + or p2_pipe_data + ) begin + mul_scale_pvld = p2_pipe_valid; + p2_pipe_ready = mul_scale_prdy; + flow_pd2_reg[70:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_scale_pvld^mul_scale_prdy^xsub_pvld^xsub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (xsub_pvld && !xsub_prdy), (xsub_pvld), (xsub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is inp_y0_sum_reg[32:0] (inp_fout_pvld,inp_out_prdy) <= inp_y0_sum[32:0] (mul_scale_pvld,mul_scale_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_out_prdy + ,inp_y0_sum + ,mul_scale_pvld + ,inp_fout_pvld + ,inp_y0_sum_reg + ,mul_scale_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_out_prdy; +input [32:0] inp_y0_sum; +input mul_scale_pvld; +output inp_fout_pvld; +output [32:0] inp_y0_sum_reg; +output mul_scale_prdy; +reg inp_fout_pvld; +reg [32:0] inp_y0_sum_reg; +reg mul_scale_prdy; +reg [32:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [32:0] p3_skid_data; +reg [32:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + mul_scale_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_scale_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_scale_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_scale_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? inp_y0_sum[32:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_scale_pvld + or p3_skid_valid + or inp_y0_sum + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_scale_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? inp_y0_sum[32:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or inp_out_prdy + or p3_pipe_data + ) begin + inp_fout_pvld = p3_pipe_valid; + p3_pipe_ready = inp_out_prdy; + inp_y0_sum_reg[32:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (inp_fout_pvld^inp_out_prdy^mul_scale_pvld^mul_scale_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_scale_pvld && !mul_scale_prdy), (mul_scale_pvld), (mul_scale_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul0_reg[52:0] (mul0_pvld,mul0_prdy) <= mul0[52:0] (inp_in_pvld,inp_in_prdy0) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_in_pvld + ,mul0 + ,mul0_prdy + ,inp_in_prdy0 + ,mul0_pvld + ,mul0_reg + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_in_pvld; +input [52:0] mul0; +input mul0_prdy; +output inp_in_prdy0; +output mul0_pvld; +output [52:0] mul0_reg; +reg inp_in_prdy0; +reg mul0_pvld; +reg [52:0] mul0_reg; +reg [52:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [52:0] p4_skid_data; +reg [52:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + inp_in_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = inp_in_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + inp_in_prdy0 <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + inp_in_prdy0 <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? mul0[52:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or inp_in_pvld + or p4_skid_valid + or mul0 + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? inp_in_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? mul0[52:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or mul0_prdy + or p4_pipe_data + ) begin + mul0_pvld = p4_pipe_valid; + p4_pipe_ready = mul0_prdy; + mul0_reg[52:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul0_pvld^mul0_prdy^inp_in_pvld^inp_in_prdy0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !inp_in_prdy0), (inp_in_pvld), (inp_in_prdy0)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul1_reg[52:0] (mul1_pvld,mul1_prdy) <= mul1[52:0] (inp_in_pvld,inp_in_prdy1) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_in_pvld + ,mul1 + ,mul1_prdy + ,inp_in_prdy1 + ,mul1_pvld + ,mul1_reg + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_in_pvld; +input [52:0] mul1; +input mul1_prdy; +output inp_in_prdy1; +output mul1_pvld; +output [52:0] mul1_reg; +reg inp_in_prdy1; +reg mul1_pvld; +reg [52:0] mul1_reg; +reg [52:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [52:0] p5_skid_data; +reg [52:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +//## pipe (5) skid buffer +always @( + inp_in_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = inp_in_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + inp_in_prdy1 <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + inp_in_prdy1 <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? mul1[52:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or inp_in_pvld + or p5_skid_valid + or mul1 + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? inp_in_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? mul1[52:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mul1_prdy + or p5_pipe_data + ) begin + mul1_pvld = p5_pipe_valid; + p5_pipe_ready = mul1_prdy; + mul1_reg[52:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul1_pvld^mul1_prdy^inp_in_pvld^inp_in_prdy1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !inp_in_prdy1), (inp_in_pvld), (inp_in_prdy1)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is intp_sum_reg[52:0] (sum_out_pvld,sum_out_prdy) <= intp_sum[52:0] (sum_in_pvld,sum_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,intp_sum + ,sum_in_pvld + ,sum_out_prdy + ,intp_sum_reg + ,sum_in_prdy + ,sum_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [52:0] intp_sum; +input sum_in_pvld; +input sum_out_prdy; +output [52:0] intp_sum_reg; +output sum_in_prdy; +output sum_out_pvld; +reg [52:0] intp_sum_reg; +reg [52:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg p6_skid_catch; +reg [52:0] p6_skid_data; +reg [52:0] p6_skid_pipe_data; +reg p6_skid_pipe_ready; +reg p6_skid_pipe_valid; +reg p6_skid_ready; +reg p6_skid_ready_flop; +reg p6_skid_valid; +reg sum_in_prdy; +reg sum_out_pvld; +//## pipe (6) skid buffer +always @( + sum_in_pvld + or p6_skid_ready_flop + or p6_skid_pipe_ready + or p6_skid_valid + ) begin + p6_skid_catch = sum_in_pvld && p6_skid_ready_flop && !p6_skid_pipe_ready; + p6_skid_ready = (p6_skid_valid)? p6_skid_pipe_ready : !p6_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_skid_valid <= 1'b0; + p6_skid_ready_flop <= 1'b1; + sum_in_prdy <= 1'b1; + end else begin + p6_skid_valid <= (p6_skid_valid)? !p6_skid_pipe_ready : p6_skid_catch; + p6_skid_ready_flop <= p6_skid_ready; + sum_in_prdy <= p6_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_skid_data <= (p6_skid_catch)? intp_sum[52:0] : p6_skid_data; +// VCS sop_coverage_off end +end +always @( + p6_skid_ready_flop + or sum_in_pvld + or p6_skid_valid + or intp_sum + or p6_skid_data + ) begin + p6_skid_pipe_valid = (p6_skid_ready_flop)? sum_in_pvld : p6_skid_valid; +// VCS sop_coverage_off start + p6_skid_pipe_data = (p6_skid_ready_flop)? intp_sum[52:0] : p6_skid_data; +// VCS sop_coverage_off end +end +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? p6_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && p6_skid_pipe_valid)? p6_skid_pipe_data : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + p6_skid_pipe_ready = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or sum_out_prdy + or p6_pipe_data + ) begin + sum_out_pvld = p6_pipe_valid; + p6_pipe_ready = sum_out_prdy; + intp_sum_reg[52:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sum_out_pvld^sum_out_prdy^sum_in_pvld^sum_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (sum_in_pvld && !sum_in_prdy), (sum_in_pvld), (sum_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is inp_nrm_dout[31:0] (inp_mout_pvld,inp_out_prdy) <= intp_sum_tru[31:0] (sum_out_pvld,sum_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_out_prdy + ,intp_sum_tru + ,sum_out_pvld + ,inp_mout_pvld + ,inp_nrm_dout + ,sum_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_out_prdy; +input [31:0] intp_sum_tru; +input sum_out_pvld; +output inp_mout_pvld; +output [31:0] inp_nrm_dout; +output sum_out_prdy; +reg inp_mout_pvld; +reg [31:0] inp_nrm_dout; +reg [31:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +reg p7_skid_catch; +reg [31:0] p7_skid_data; +reg [31:0] p7_skid_pipe_data; +reg p7_skid_pipe_ready; +reg p7_skid_pipe_valid; +reg p7_skid_ready; +reg p7_skid_ready_flop; +reg p7_skid_valid; +reg sum_out_prdy; +//## pipe (7) skid buffer +always @( + sum_out_pvld + or p7_skid_ready_flop + or p7_skid_pipe_ready + or p7_skid_valid + ) begin + p7_skid_catch = sum_out_pvld && p7_skid_ready_flop && !p7_skid_pipe_ready; + p7_skid_ready = (p7_skid_valid)? p7_skid_pipe_ready : !p7_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_skid_valid <= 1'b0; + p7_skid_ready_flop <= 1'b1; + sum_out_prdy <= 1'b1; + end else begin + p7_skid_valid <= (p7_skid_valid)? !p7_skid_pipe_ready : p7_skid_catch; + p7_skid_ready_flop <= p7_skid_ready; + sum_out_prdy <= p7_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_skid_data <= (p7_skid_catch)? intp_sum_tru[31:0] : p7_skid_data; +// VCS sop_coverage_off end +end +always @( + p7_skid_ready_flop + or sum_out_pvld + or p7_skid_valid + or intp_sum_tru + or p7_skid_data + ) begin + p7_skid_pipe_valid = (p7_skid_ready_flop)? sum_out_pvld : p7_skid_valid; +// VCS sop_coverage_off start + p7_skid_pipe_data = (p7_skid_ready_flop)? intp_sum_tru[31:0] : p7_skid_data; +// VCS sop_coverage_off end +end +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? p7_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && p7_skid_pipe_valid)? p7_skid_pipe_data : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + p7_skid_pipe_ready = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or inp_out_prdy + or p7_pipe_data + ) begin + inp_mout_pvld = p7_pipe_valid; + p7_pipe_ready = inp_out_prdy; + inp_nrm_dout[31:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (inp_mout_pvld^inp_out_prdy^sum_out_pvld^sum_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (sum_out_pvld && !sum_out_prdy), (sum_out_pvld), (sum_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p7 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_in_pipe1 (flow_pipe1_pvld,flow_pipe1_prdy) <= inp_flow_in (inp_in_pvld, flow_pipe0_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p8 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_pipe1_prdy + ,inp_flow_in + ,inp_in_pvld + ,flow_in_pipe1 + ,flow_pipe0_prdy + ,flow_pipe1_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input flow_pipe1_prdy; +input inp_flow_in; +input inp_in_pvld; +output flow_in_pipe1; +output flow_pipe0_prdy; +output flow_pipe1_pvld; +reg flow_in_pipe1; +reg flow_pipe0_prdy; +reg flow_pipe1_pvld; +reg p8_pipe_data; +reg p8_pipe_ready; +reg p8_pipe_ready_bc; +reg p8_pipe_valid; +reg p8_skid_catch; +reg p8_skid_data; +reg p8_skid_pipe_data; +reg p8_skid_pipe_ready; +reg p8_skid_pipe_valid; +reg p8_skid_ready; +reg p8_skid_ready_flop; +reg p8_skid_valid; +//## pipe (8) skid buffer +always @( + inp_in_pvld + or p8_skid_ready_flop + or p8_skid_pipe_ready + or p8_skid_valid + ) begin + p8_skid_catch = inp_in_pvld && p8_skid_ready_flop && !p8_skid_pipe_ready; + p8_skid_ready = (p8_skid_valid)? p8_skid_pipe_ready : !p8_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_skid_valid <= 1'b0; + p8_skid_ready_flop <= 1'b1; + flow_pipe0_prdy <= 1'b1; + end else begin + p8_skid_valid <= (p8_skid_valid)? !p8_skid_pipe_ready : p8_skid_catch; + p8_skid_ready_flop <= p8_skid_ready; + flow_pipe0_prdy <= p8_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_skid_data <= (p8_skid_catch)? inp_flow_in : p8_skid_data; +// VCS sop_coverage_off end +end +always @( + p8_skid_ready_flop + or inp_in_pvld + or p8_skid_valid + or inp_flow_in + or p8_skid_data + ) begin + p8_skid_pipe_valid = (p8_skid_ready_flop)? inp_in_pvld : p8_skid_valid; +// VCS sop_coverage_off start + p8_skid_pipe_data = (p8_skid_ready_flop)? inp_flow_in : p8_skid_data; +// VCS sop_coverage_off end +end +//## pipe (8) valid-ready-bubble-collapse +always @( + p8_pipe_ready + or p8_pipe_valid + ) begin + p8_pipe_ready_bc = p8_pipe_ready || !p8_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p8_pipe_valid <= 1'b0; + end else begin + p8_pipe_valid <= (p8_pipe_ready_bc)? p8_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p8_pipe_data <= (p8_pipe_ready_bc && p8_skid_pipe_valid)? p8_skid_pipe_data : p8_pipe_data; +// VCS sop_coverage_off end +end +always @( + p8_pipe_ready_bc + ) begin + p8_skid_pipe_ready = p8_pipe_ready_bc; +end +//## pipe (8) output +always @( + p8_pipe_valid + or flow_pipe1_prdy + or p8_pipe_data + ) begin + flow_pipe1_pvld = p8_pipe_valid; + p8_pipe_ready = flow_pipe1_prdy; + flow_in_pipe1 = p8_pipe_data; +end +//## pipe (8) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p8_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (flow_pipe1_pvld^flow_pipe1_prdy^inp_in_pvld^flow_pipe0_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_16x (nvdla_core_clk, `ASSERT_RESET, (inp_in_pvld && !flow_pipe0_prdy), (inp_in_pvld), (flow_pipe0_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p8 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_in_pipe2 (flow_pipe2_pvld,flow_pipe2_prdy) <= flow_in_pipe1 (flow_pipe1_pvld,flow_pipe1_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p9 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_in_pipe1 + ,flow_pipe1_pvld + ,flow_pipe2_prdy + ,flow_in_pipe2 + ,flow_pipe1_prdy + ,flow_pipe2_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input flow_in_pipe1; +input flow_pipe1_pvld; +input flow_pipe2_prdy; +output flow_in_pipe2; +output flow_pipe1_prdy; +output flow_pipe2_pvld; +reg flow_in_pipe2; +reg flow_pipe1_prdy; +reg flow_pipe2_pvld; +reg p9_pipe_data; +reg p9_pipe_ready; +reg p9_pipe_ready_bc; +reg p9_pipe_valid; +reg p9_skid_catch; +reg p9_skid_data; +reg p9_skid_pipe_data; +reg p9_skid_pipe_ready; +reg p9_skid_pipe_valid; +reg p9_skid_ready; +reg p9_skid_ready_flop; +reg p9_skid_valid; +//## pipe (9) skid buffer +always @( + flow_pipe1_pvld + or p9_skid_ready_flop + or p9_skid_pipe_ready + or p9_skid_valid + ) begin + p9_skid_catch = flow_pipe1_pvld && p9_skid_ready_flop && !p9_skid_pipe_ready; + p9_skid_ready = (p9_skid_valid)? p9_skid_pipe_ready : !p9_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p9_skid_valid <= 1'b0; + p9_skid_ready_flop <= 1'b1; + flow_pipe1_prdy <= 1'b1; + end else begin + p9_skid_valid <= (p9_skid_valid)? !p9_skid_pipe_ready : p9_skid_catch; + p9_skid_ready_flop <= p9_skid_ready; + flow_pipe1_prdy <= p9_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p9_skid_data <= (p9_skid_catch)? flow_in_pipe1 : p9_skid_data; +// VCS sop_coverage_off end +end +always @( + p9_skid_ready_flop + or flow_pipe1_pvld + or p9_skid_valid + or flow_in_pipe1 + or p9_skid_data + ) begin + p9_skid_pipe_valid = (p9_skid_ready_flop)? flow_pipe1_pvld : p9_skid_valid; +// VCS sop_coverage_off start + p9_skid_pipe_data = (p9_skid_ready_flop)? flow_in_pipe1 : p9_skid_data; +// VCS sop_coverage_off end +end +//## pipe (9) valid-ready-bubble-collapse +always @( + p9_pipe_ready + or p9_pipe_valid + ) begin + p9_pipe_ready_bc = p9_pipe_ready || !p9_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p9_pipe_valid <= 1'b0; + end else begin + p9_pipe_valid <= (p9_pipe_ready_bc)? p9_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p9_pipe_data <= (p9_pipe_ready_bc && p9_skid_pipe_valid)? p9_skid_pipe_data : p9_pipe_data; +// VCS sop_coverage_off end +end +always @( + p9_pipe_ready_bc + ) begin + p9_skid_pipe_ready = p9_pipe_ready_bc; +end +//## pipe (9) output +always @( + p9_pipe_valid + or flow_pipe2_prdy + or p9_pipe_data + ) begin + flow_pipe2_pvld = p9_pipe_valid; + p9_pipe_ready = flow_pipe2_prdy; + flow_in_pipe2 = p9_pipe_data; +end +//## pipe (9) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p9_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (flow_pipe2_pvld^flow_pipe2_prdy^flow_pipe1_pvld^flow_pipe1_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_18x (nvdla_core_clk, `ASSERT_RESET, (flow_pipe1_pvld && !flow_pipe1_prdy), (flow_pipe1_pvld), (flow_pipe1_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p9 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is flow_in_pipe3 (flow_pipe3_pvld,inp_out_prdy) <= flow_in_pipe2 (flow_pipe2_pvld,flow_pipe2_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p10 ( + nvdla_core_clk + ,nvdla_core_rstn + ,flow_in_pipe2 + ,flow_pipe2_pvld + ,inp_out_prdy + ,flow_in_pipe3 + ,flow_pipe2_prdy + ,flow_pipe3_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input flow_in_pipe2; +input flow_pipe2_pvld; +input inp_out_prdy; +output flow_in_pipe3; +output flow_pipe2_prdy; +output flow_pipe3_pvld; +reg flow_in_pipe3; +reg flow_pipe2_prdy; +reg flow_pipe3_pvld; +reg p10_pipe_data; +reg p10_pipe_ready; +reg p10_pipe_ready_bc; +reg p10_pipe_valid; +reg p10_skid_catch; +reg p10_skid_data; +reg p10_skid_pipe_data; +reg p10_skid_pipe_ready; +reg p10_skid_pipe_valid; +reg p10_skid_ready; +reg p10_skid_ready_flop; +reg p10_skid_valid; +//## pipe (10) skid buffer +always @( + flow_pipe2_pvld + or p10_skid_ready_flop + or p10_skid_pipe_ready + or p10_skid_valid + ) begin + p10_skid_catch = flow_pipe2_pvld && p10_skid_ready_flop && !p10_skid_pipe_ready; + p10_skid_ready = (p10_skid_valid)? p10_skid_pipe_ready : !p10_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p10_skid_valid <= 1'b0; + p10_skid_ready_flop <= 1'b1; + flow_pipe2_prdy <= 1'b1; + end else begin + p10_skid_valid <= (p10_skid_valid)? !p10_skid_pipe_ready : p10_skid_catch; + p10_skid_ready_flop <= p10_skid_ready; + flow_pipe2_prdy <= p10_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p10_skid_data <= (p10_skid_catch)? flow_in_pipe2 : p10_skid_data; +// VCS sop_coverage_off end +end +always @( + p10_skid_ready_flop + or flow_pipe2_pvld + or p10_skid_valid + or flow_in_pipe2 + or p10_skid_data + ) begin + p10_skid_pipe_valid = (p10_skid_ready_flop)? flow_pipe2_pvld : p10_skid_valid; +// VCS sop_coverage_off start + p10_skid_pipe_data = (p10_skid_ready_flop)? flow_in_pipe2 : p10_skid_data; +// VCS sop_coverage_off end +end +//## pipe (10) valid-ready-bubble-collapse +always @( + p10_pipe_ready + or p10_pipe_valid + ) begin + p10_pipe_ready_bc = p10_pipe_ready || !p10_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p10_pipe_valid <= 1'b0; + end else begin + p10_pipe_valid <= (p10_pipe_ready_bc)? p10_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p10_pipe_data <= (p10_pipe_ready_bc && p10_skid_pipe_valid)? p10_skid_pipe_data : p10_pipe_data; +// VCS sop_coverage_off end +end +always @( + p10_pipe_ready_bc + ) begin + p10_skid_pipe_ready = p10_pipe_ready_bc; +end +//## pipe (10) output +always @( + p10_pipe_valid + or inp_out_prdy + or p10_pipe_data + ) begin + flow_pipe3_pvld = p10_pipe_valid; + p10_pipe_ready = inp_out_prdy; + flow_in_pipe3 = p10_pipe_data; +end +//## pipe (10) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p10_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (flow_pipe3_pvld^inp_out_prdy^flow_pipe2_pvld^flow_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_20x (nvdla_core_clk, `ASSERT_RESET, (flow_pipe2_pvld && !flow_pipe2_prdy), (flow_pipe2_pvld), (flow_pipe2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_INP_pipe_p10 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_mul.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_mul.v new file mode 100644 index 0000000..b2755dd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_mul.v @@ -0,0 +1,542 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_mul.v +module NV_NVDLA_SDP_HLS_Y_int_mul ( + cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_src //|< i + ,cfg_mul_truncate //|< i + ,chn_in_pvld //|< i + ,chn_mul_in //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,mul_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,mul_data_out //|> o + ,mul_out_pvld //|> o + ); +input cfg_mul_bypass; +input [31:0] cfg_mul_op; +input cfg_mul_prelu; +input cfg_mul_src; +input [9:0] cfg_mul_truncate; +input chn_in_pvld; +input [31:0] chn_mul_in; +input [31:0] chn_mul_op; +input chn_mul_op_pvld; +input mul_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_in_prdy; +output chn_mul_op_prdy; +output [31:0] mul_data_out; +output mul_out_pvld; +reg [31:0] mul_dout; +wire chn_in_srdy; +wire [31:0] mul_data_final; +wire [31:0] mul_data_in; +wire [31:0] mul_data_reg; +wire [31:0] mul_data_sync; +wire mul_final_prdy; +wire mul_final_pvld; +wire [31:0] mul_op_in; +wire [31:0] mul_op_sync; +wire [63:0] mul_prelu_dout; +wire [63:0] mul_prelu_out; +wire mul_prelu_prdy; +wire mul_prelu_pvld; +wire mul_sync_prdy; +wire mul_sync_pvld; +wire [31:0] mul_truncate_out; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(32 ),.DATA2_WIDTH(32 )) y_mul_sync2data ( + .chn1_en (!cfg_mul_bypass & cfg_mul_src) //|< ? + ,.chn2_en (!cfg_mul_bypass) //|< i + ,.chn1_in_pvld (chn_mul_op_pvld) //|< i + ,.chn1_in_prdy (chn_mul_op_prdy) //|> o + ,.chn2_in_pvld (chn_in_pvld) //|< i + ,.chn2_in_prdy (chn_in_srdy) //|> w + ,.chn_out_pvld (mul_sync_pvld) //|> w + ,.chn_out_prdy (mul_sync_prdy) //|< w + ,.data1_in (chn_mul_op[31:0]) //|< i + ,.data2_in (chn_mul_in[31:0]) //|< i + ,.data1_out (mul_op_sync[31:0]) //|> w + ,.data2_out (mul_data_sync[31:0]) //|> w + ); +assign mul_data_in[31:0] = mul_data_sync[31:0]; +assign mul_op_in[31:0] = (cfg_mul_src == 0 ) ? cfg_mul_op[31:0] : mul_op_sync[31:0]; +NV_NVDLA_SDP_HLS_prelu #(.IN_WIDTH(32 ),.OUT_WIDTH(32 + 32 ),.OP_WIDTH(32 )) y_mul_prelu ( + .cfg_prelu_en (cfg_mul_prelu) //|< i + ,.data_in (mul_data_in[31:0]) //|< w + ,.op_in (mul_op_in[31:0]) //|< w + ,.data_out (mul_prelu_dout[63:0]) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_data_in (mul_data_in[31:0]) //|< w + ,.mul_prelu_dout (mul_prelu_dout[63:0]) //|< w + ,.mul_prelu_prdy (mul_prelu_prdy) //|< w + ,.mul_sync_pvld (mul_sync_pvld) //|< w + ,.mul_data_reg (mul_data_reg[31:0]) //|> w + ,.mul_prelu_out (mul_prelu_out[63:0]) //|> w + ,.mul_prelu_pvld (mul_prelu_pvld) //|> w + ,.mul_sync_prdy (mul_sync_prdy) //|> w + ); +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(32 + 32 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(10 )) y_mul_shiftright_su ( + .data_in (mul_prelu_out[63:0]) //|< w + ,.shift_num (cfg_mul_truncate[9:0]) //|< i + ,.data_out (mul_truncate_out[31:0]) //|> w + ); +//signed +//unsigned +assign mul_data_reg[31:0] = mul_prelu_out[31:0]; +always @( + cfg_mul_prelu + or mul_data_reg + or mul_truncate_out + ) begin + if (cfg_mul_prelu & !mul_data_reg[32 -1]) + mul_dout[31:0] = mul_data_reg; + else + mul_dout[31:0] = mul_truncate_out[31:0]; +end +NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[31:0]) //|< r + ,.mul_final_prdy (mul_final_prdy) //|< w + ,.mul_prelu_pvld (mul_prelu_pvld) //|< w + ,.mul_data_final (mul_data_final[31:0]) //|> w + ,.mul_final_pvld (mul_final_pvld) //|> w + ,.mul_prelu_prdy (mul_prelu_prdy) //|> w + ); +assign chn_in_prdy = cfg_mul_bypass ? mul_out_prdy : chn_in_srdy; +assign mul_final_prdy = cfg_mul_bypass ? 1'b1 : mul_out_prdy; +assign mul_out_pvld = cfg_mul_bypass ? chn_in_pvld : mul_final_pvld; +assign mul_data_out[31:0] = cfg_mul_bypass ? chn_mul_in : mul_data_final[31:0]; +endmodule // NV_NVDLA_SDP_HLS_Y_int_mul +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_data_reg[31:0],mul_prelu_out[63:0]} (mul_prelu_pvld,mul_prelu_prdy) <= {mul_data_in[31:0],mul_prelu_dout[63:0]} (mul_sync_pvld,mul_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_data_in + ,mul_prelu_dout + ,mul_prelu_prdy + ,mul_sync_pvld + ,mul_data_reg + ,mul_prelu_out + ,mul_prelu_pvld + ,mul_sync_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] mul_data_in; +input [63:0] mul_prelu_dout; +input mul_prelu_prdy; +input mul_sync_pvld; +output [31:0] mul_data_reg; +output [63:0] mul_prelu_out; +output mul_prelu_pvld; +output mul_sync_prdy; +reg [31:0] mul_data_reg; +reg [63:0] mul_prelu_out; +reg mul_prelu_pvld; +reg mul_sync_prdy; +reg [95:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [95:0] p1_skid_data; +reg [95:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + mul_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = mul_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + mul_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + mul_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {mul_data_in[31:0],mul_prelu_dout[63:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or mul_sync_pvld + or p1_skid_valid + or mul_data_in + or mul_prelu_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? mul_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {mul_data_in[31:0],mul_prelu_dout[63:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mul_prelu_prdy + or p1_pipe_data + ) begin + mul_prelu_pvld = p1_pipe_valid; + p1_pipe_ready = mul_prelu_prdy; + {mul_data_reg[31:0],mul_prelu_out[63:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_prelu_pvld^mul_prelu_prdy^mul_sync_pvld^mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul_sync_pvld && !mul_sync_prdy), (mul_sync_pvld), (mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_final[31:0] (mul_final_pvld,mul_final_prdy) <= mul_dout[31:0] (mul_prelu_pvld,mul_prelu_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_final_prdy + ,mul_prelu_pvld + ,mul_data_final + ,mul_final_pvld + ,mul_prelu_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] mul_dout; +input mul_final_prdy; +input mul_prelu_pvld; +output [31:0] mul_data_final; +output mul_final_pvld; +output mul_prelu_prdy; +reg [31:0] mul_data_final; +reg mul_final_pvld; +reg mul_prelu_prdy; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [31:0] p2_skid_data; +reg [31:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + mul_prelu_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = mul_prelu_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + mul_prelu_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + mul_prelu_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or mul_prelu_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? mul_prelu_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_final_prdy + or p2_pipe_data + ) begin + mul_final_pvld = p2_pipe_valid; + p2_pipe_ready = mul_final_prdy; + mul_data_final[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_final_pvld^mul_final_prdy^mul_prelu_pvld^mul_prelu_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mul_prelu_pvld && !mul_prelu_prdy), (mul_prelu_pvld), (mul_prelu_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_mul.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_mul.v.vcp new file mode 100644 index 0000000..b2755dd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_Y_int_mul.v.vcp @@ -0,0 +1,542 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_Y_int_mul.v +module NV_NVDLA_SDP_HLS_Y_int_mul ( + cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_src //|< i + ,cfg_mul_truncate //|< i + ,chn_in_pvld //|< i + ,chn_mul_in //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,mul_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,mul_data_out //|> o + ,mul_out_pvld //|> o + ); +input cfg_mul_bypass; +input [31:0] cfg_mul_op; +input cfg_mul_prelu; +input cfg_mul_src; +input [9:0] cfg_mul_truncate; +input chn_in_pvld; +input [31:0] chn_mul_in; +input [31:0] chn_mul_op; +input chn_mul_op_pvld; +input mul_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_in_prdy; +output chn_mul_op_prdy; +output [31:0] mul_data_out; +output mul_out_pvld; +reg [31:0] mul_dout; +wire chn_in_srdy; +wire [31:0] mul_data_final; +wire [31:0] mul_data_in; +wire [31:0] mul_data_reg; +wire [31:0] mul_data_sync; +wire mul_final_prdy; +wire mul_final_pvld; +wire [31:0] mul_op_in; +wire [31:0] mul_op_sync; +wire [63:0] mul_prelu_dout; +wire [63:0] mul_prelu_out; +wire mul_prelu_prdy; +wire mul_prelu_pvld; +wire mul_sync_prdy; +wire mul_sync_pvld; +wire [31:0] mul_truncate_out; +NV_NVDLA_SDP_HLS_sync2data #(.DATA1_WIDTH(32 ),.DATA2_WIDTH(32 )) y_mul_sync2data ( + .chn1_en (!cfg_mul_bypass & cfg_mul_src) //|< ? + ,.chn2_en (!cfg_mul_bypass) //|< i + ,.chn1_in_pvld (chn_mul_op_pvld) //|< i + ,.chn1_in_prdy (chn_mul_op_prdy) //|> o + ,.chn2_in_pvld (chn_in_pvld) //|< i + ,.chn2_in_prdy (chn_in_srdy) //|> w + ,.chn_out_pvld (mul_sync_pvld) //|> w + ,.chn_out_prdy (mul_sync_prdy) //|< w + ,.data1_in (chn_mul_op[31:0]) //|< i + ,.data2_in (chn_mul_in[31:0]) //|< i + ,.data1_out (mul_op_sync[31:0]) //|> w + ,.data2_out (mul_data_sync[31:0]) //|> w + ); +assign mul_data_in[31:0] = mul_data_sync[31:0]; +assign mul_op_in[31:0] = (cfg_mul_src == 0 ) ? cfg_mul_op[31:0] : mul_op_sync[31:0]; +NV_NVDLA_SDP_HLS_prelu #(.IN_WIDTH(32 ),.OUT_WIDTH(32 + 32 ),.OP_WIDTH(32 )) y_mul_prelu ( + .cfg_prelu_en (cfg_mul_prelu) //|< i + ,.data_in (mul_data_in[31:0]) //|< w + ,.op_in (mul_op_in[31:0]) //|< w + ,.data_out (mul_prelu_dout[63:0]) //|> w + ); +NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_data_in (mul_data_in[31:0]) //|< w + ,.mul_prelu_dout (mul_prelu_dout[63:0]) //|< w + ,.mul_prelu_prdy (mul_prelu_prdy) //|< w + ,.mul_sync_pvld (mul_sync_pvld) //|< w + ,.mul_data_reg (mul_data_reg[31:0]) //|> w + ,.mul_prelu_out (mul_prelu_out[63:0]) //|> w + ,.mul_prelu_pvld (mul_prelu_pvld) //|> w + ,.mul_sync_prdy (mul_sync_prdy) //|> w + ); +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(32 + 32 ),.OUT_WIDTH(32 ),.SHIFT_WIDTH(10 )) y_mul_shiftright_su ( + .data_in (mul_prelu_out[63:0]) //|< w + ,.shift_num (cfg_mul_truncate[9:0]) //|< i + ,.data_out (mul_truncate_out[31:0]) //|> w + ); +//signed +//unsigned +assign mul_data_reg[31:0] = mul_prelu_out[31:0]; +always @( + cfg_mul_prelu + or mul_data_reg + or mul_truncate_out + ) begin + if (cfg_mul_prelu & !mul_data_reg[32 -1]) + mul_dout[31:0] = mul_data_reg; + else + mul_dout[31:0] = mul_truncate_out[31:0]; +end +NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[31:0]) //|< r + ,.mul_final_prdy (mul_final_prdy) //|< w + ,.mul_prelu_pvld (mul_prelu_pvld) //|< w + ,.mul_data_final (mul_data_final[31:0]) //|> w + ,.mul_final_pvld (mul_final_pvld) //|> w + ,.mul_prelu_prdy (mul_prelu_prdy) //|> w + ); +assign chn_in_prdy = cfg_mul_bypass ? mul_out_prdy : chn_in_srdy; +assign mul_final_prdy = cfg_mul_bypass ? 1'b1 : mul_out_prdy; +assign mul_out_pvld = cfg_mul_bypass ? chn_in_pvld : mul_final_pvld; +assign mul_data_out[31:0] = cfg_mul_bypass ? chn_mul_in : mul_data_final[31:0]; +endmodule // NV_NVDLA_SDP_HLS_Y_int_mul +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_data_reg[31:0],mul_prelu_out[63:0]} (mul_prelu_pvld,mul_prelu_prdy) <= {mul_data_in[31:0],mul_prelu_dout[63:0]} (mul_sync_pvld,mul_sync_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_data_in + ,mul_prelu_dout + ,mul_prelu_prdy + ,mul_sync_pvld + ,mul_data_reg + ,mul_prelu_out + ,mul_prelu_pvld + ,mul_sync_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] mul_data_in; +input [63:0] mul_prelu_dout; +input mul_prelu_prdy; +input mul_sync_pvld; +output [31:0] mul_data_reg; +output [63:0] mul_prelu_out; +output mul_prelu_pvld; +output mul_sync_prdy; +reg [31:0] mul_data_reg; +reg [63:0] mul_prelu_out; +reg mul_prelu_pvld; +reg mul_sync_prdy; +reg [95:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [95:0] p1_skid_data; +reg [95:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + mul_sync_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = mul_sync_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + mul_sync_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + mul_sync_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {mul_data_in[31:0],mul_prelu_dout[63:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or mul_sync_pvld + or p1_skid_valid + or mul_data_in + or mul_prelu_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? mul_sync_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {mul_data_in[31:0],mul_prelu_dout[63:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mul_prelu_prdy + or p1_pipe_data + ) begin + mul_prelu_pvld = p1_pipe_valid; + p1_pipe_ready = mul_prelu_prdy; + {mul_data_reg[31:0],mul_prelu_out[63:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_prelu_pvld^mul_prelu_prdy^mul_sync_pvld^mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (mul_sync_pvld && !mul_sync_prdy), (mul_sync_pvld), (mul_sync_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_final[31:0] (mul_final_pvld,mul_final_prdy) <= mul_dout[31:0] (mul_prelu_pvld,mul_prelu_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_final_prdy + ,mul_prelu_pvld + ,mul_data_final + ,mul_final_pvld + ,mul_prelu_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] mul_dout; +input mul_final_prdy; +input mul_prelu_pvld; +output [31:0] mul_data_final; +output mul_final_pvld; +output mul_prelu_prdy; +reg [31:0] mul_data_final; +reg mul_final_pvld; +reg mul_prelu_prdy; +reg [31:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [31:0] p2_skid_data; +reg [31:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +//## pipe (2) skid buffer +always @( + mul_prelu_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = mul_prelu_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + mul_prelu_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + mul_prelu_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or mul_prelu_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? mul_prelu_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[31:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_final_prdy + or p2_pipe_data + ) begin + mul_final_pvld = p2_pipe_valid; + p2_pipe_ready = mul_final_prdy; + mul_data_final[31:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_final_pvld^mul_final_prdy^mul_prelu_pvld^mul_prelu_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mul_prelu_pvld && !mul_prelu_prdy), (mul_prelu_pvld), (mul_prelu_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_Y_INT_MUL_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_c.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_c.v new file mode 100644 index 0000000..50a5287 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_c.v @@ -0,0 +1,133 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_c.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_c ( + cfg_mode_eql + ,cfg_offset + ,cfg_out_precision + ,cfg_scale + ,cfg_truncate + ,cvt_in_pvld + ,cvt_out_prdy + ,cvt_pd_in + ,nvdla_core_clk + ,nvdla_core_rstn + ,cvt_in_prdy + ,cvt_out_pvld + ,cvt_pd_out + ); +input cfg_mode_eql; +input [31:0] cfg_offset; +input [1:0] cfg_out_precision; +input [15:0] cfg_scale; +input [5:0] cfg_truncate; +input cvt_in_pvld; +input cvt_out_prdy; +input [32*1 -1:0] cvt_pd_in; +output cvt_in_prdy; +output cvt_out_pvld; +output [16*1 +1 -1:0] cvt_pd_out; +input nvdla_core_clk; +input nvdla_core_rstn; +wire [8*1 -1:0] cvt_pd_out8; +wire [16*1 -1:0] cvt_pd_out16; +//: my $b = 8; +//: my $dw = 16*1; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [31:0] cvt_data_in_$i; +//: wire [15:0] cvt_data_out_$i; +//: wire cvt_in_prdy_$i; +//: wire cvt_out_pvld_$i; +//: wire cvt_sat_out_$i; +//: ); +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_data_in_${i} = cvt_pd_in[32*${i}+31:32*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_pd_out8[8*${i}+7:8*${i}] = cvt_data_out_${i}[7:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_pd_out16[16*${i}+15:16*${i}] = cvt_data_out_${i}; \n"; +//: } +//: print "\n"; +//: print "assign cvt_pd_out[${dw}-1:0] = cfg_out_precision[1:0]==2'b0 ? {{(8*$k){1'b0}},cvt_pd_out8[8*${k}-1:0]} : cvt_pd_out16[16*${k}-1:0]; \n"; +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_pd_out[${dw}+${i}] = cvt_sat_out_${i}; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_C_int c_int_${i} ( +//: .cfg_mode_eql (cfg_mode_eql) +//: ,.cfg_offset (cfg_offset[31:0]) +//: ,.cfg_out_precision (cfg_out_precision[1:0]) +//: ,.cfg_scale (cfg_scale[15:0]) +//: ,.cfg_truncate (cfg_truncate[5:0]) +//: ,.cvt_data_in (cvt_data_in_${i}[31:0]) +//: ,.cvt_in_pvld (cvt_in_pvld) +//: ,.cvt_out_prdy (cvt_out_prdy) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cvt_data_out (cvt_data_out_${i}[15:0]) +//: ,.cvt_in_prdy (cvt_in_prdy_${i}) +//: ,.cvt_out_pvld (cvt_out_pvld_${i}) +//: ,.cvt_sat_out (cvt_sat_out_${i}) +//: ); +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [31:0] cvt_data_in_0; +wire [15:0] cvt_data_out_0; +wire cvt_in_prdy_0; +wire cvt_out_pvld_0; +wire cvt_sat_out_0; + +assign cvt_data_in_0 = cvt_pd_in[32*0+31:32*0]; +assign cvt_pd_out8[8*0+7:8*0] = cvt_data_out_0[7:0]; +assign cvt_pd_out16[16*0+15:16*0] = cvt_data_out_0; + +assign cvt_pd_out[16-1:0] = cfg_out_precision[1:0]==2'b0 ? {{(8*1){1'b0}},cvt_pd_out8[8*1-1:0]} : cvt_pd_out16[16*1-1:0]; +assign cvt_pd_out[16+0] = cvt_sat_out_0; + + +NV_NVDLA_SDP_HLS_C_int c_int_0 ( +.cfg_mode_eql (cfg_mode_eql) +,.cfg_offset (cfg_offset[31:0]) +,.cfg_out_precision (cfg_out_precision[1:0]) +,.cfg_scale (cfg_scale[15:0]) +,.cfg_truncate (cfg_truncate[5:0]) +,.cvt_data_in (cvt_data_in_0[31:0]) +,.cvt_in_pvld (cvt_in_pvld) +,.cvt_out_prdy (cvt_out_prdy) +,.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.cvt_data_out (cvt_data_out_0[15:0]) +,.cvt_in_prdy (cvt_in_prdy_0) +,.cvt_out_pvld (cvt_out_pvld_0) +,.cvt_sat_out (cvt_sat_out_0) +); + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign cvt_in_prdy = cvt_in_prdy_0; +assign cvt_out_pvld = cvt_out_pvld_0; +endmodule // NV_NVDLA_SDP_HLS_c diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_c.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_c.v.vcp new file mode 100644 index 0000000..0cb1bd0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_c.v.vcp @@ -0,0 +1,98 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_c.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_c ( + cfg_mode_eql + ,cfg_offset + ,cfg_out_precision + ,cfg_scale + ,cfg_truncate + ,cvt_in_pvld + ,cvt_out_prdy + ,cvt_pd_in + ,nvdla_core_clk + ,nvdla_core_rstn + ,cvt_in_prdy + ,cvt_out_pvld + ,cvt_pd_out + ); +input cfg_mode_eql; +input [31:0] cfg_offset; +input [1:0] cfg_out_precision; +input [15:0] cfg_scale; +input [5:0] cfg_truncate; +input cvt_in_pvld; +input cvt_out_prdy; +input [32*1 -1:0] cvt_pd_in; +output cvt_in_prdy; +output cvt_out_pvld; +output [16*1 +1 -1:0] cvt_pd_out; +input nvdla_core_clk; +input nvdla_core_rstn; +wire [8*1 -1:0] cvt_pd_out8; +wire [16*1 -1:0] cvt_pd_out16; +//: my $b = 8; +//: my $dw = 16*1; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [31:0] cvt_data_in_$i; +//: wire [15:0] cvt_data_out_$i; +//: wire cvt_in_prdy_$i; +//: wire cvt_out_pvld_$i; +//: wire cvt_sat_out_$i; +//: ); +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_data_in_${i} = cvt_pd_in[32*${i}+31:32*${i}]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_pd_out8[8*${i}+7:8*${i}] = cvt_data_out_${i}[7:0]; \n"; +//: } +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_pd_out16[16*${i}+15:16*${i}] = cvt_data_out_${i}; \n"; +//: } +//: print "\n"; +//: print "assign cvt_pd_out[${dw}-1:0] = cfg_out_precision[1:0]==2'b0 ? {{(8*$k){1'b0}},cvt_pd_out8[8*${k}-1:0]} : cvt_pd_out16[16*${k}-1:0]; \n"; +//: foreach my $i (0..${k}-1) { +//: print "assign cvt_pd_out[${dw}+${i}] = cvt_sat_out_${i}; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: NV_NVDLA_SDP_HLS_C_int c_int_${i} ( +//: .cfg_mode_eql (cfg_mode_eql) +//: ,.cfg_offset (cfg_offset[31:0]) +//: ,.cfg_out_precision (cfg_out_precision[1:0]) +//: ,.cfg_scale (cfg_scale[15:0]) +//: ,.cfg_truncate (cfg_truncate[5:0]) +//: ,.cvt_data_in (cvt_data_in_${i}[31:0]) +//: ,.cvt_in_pvld (cvt_in_pvld) +//: ,.cvt_out_prdy (cvt_out_prdy) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cvt_data_out (cvt_data_out_${i}[15:0]) +//: ,.cvt_in_prdy (cvt_in_prdy_${i}) +//: ,.cvt_out_pvld (cvt_out_pvld_${i}) +//: ,.cvt_sat_out (cvt_sat_out_${i}) +//: ); +//: +//: ); +//: } +assign cvt_in_prdy = cvt_in_prdy_0; +assign cvt_out_pvld = cvt_out_pvld_0; +endmodule // NV_NVDLA_SDP_HLS_c diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_expn.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_expn.v new file mode 100644 index 0000000..d16f0a6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_expn.v @@ -0,0 +1,795 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_lut_expn.v +module NV_NVDLA_SDP_HLS_lut_expn ( + cfg_lut_offset //|< i + ,cfg_lut_start //|< i + ,idx_data_in //|< i + ,idx_in_pvld //|< i + ,idx_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,idx_in_prdy //|> o + ,idx_out_pvld //|> o + ,lut_frac_out //|> o + ,lut_index_out //|> o + ,lut_oflow_out //|> o + ,lut_uflow_out //|> o + ); +parameter LUT_DEPTH = 256; +input [7:0] cfg_lut_offset; +input [31:0] cfg_lut_start; +input [31:0] idx_data_in; +input idx_in_pvld; +input idx_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output idx_in_prdy; +output idx_out_pvld; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +reg [8:0] lut_index_final; +wire [8:0] cfg_lut_offset_ext; +wire [31:0] filter_frac; +wire [4:0] leadzero; +wire [31:0] log2_lut_frac; +wire [31:0] log2_lut_frac_reg; +wire [31:0] log2_lut_index; +wire [8:0] log2_lut_index_reg; +wire [8:0] log2_lut_index_tru; +wire log2_prdy; +wire log2_pvld; +wire [34:0] lut_frac_final; +wire [31:0] lut_index_sub; +wire [8:0] lut_index_sub_mid; +wire [8:0] lut_index_sub_mid_tmp; +wire [31:0] lut_index_sub_reg; +wire [31:0] lut_index_sub_tmp; +wire lut_oflow_final; +wire lut_uflow_final; +wire lut_uflow_in; +wire lut_uflow_mid; +wire lut_uflow_reg; +wire lut_uflow_reg2; +wire mon_lutin_sub_c; +wire [1:0] mon_lutmid_sub_c; +wire sub_prdy; +wire sub_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign lut_uflow_in = ($signed(idx_data_in[31:0]) <= $signed(cfg_lut_start[31:0])); +assign {mon_lutin_sub_c,lut_index_sub_tmp[31:0]} = $signed(idx_data_in[31:0])- $signed(cfg_lut_start[31:0]); +//unsigned int +assign lut_index_sub[31:0] = lut_uflow_in ? 0 : lut_index_sub_tmp[31:0]; +NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_pvld (idx_in_pvld) //|< i + ,.lut_index_sub (lut_index_sub[31:0]) //|< w + ,.lut_uflow_in (lut_uflow_in) //|< w + ,.sub_prdy (sub_prdy) //|< w + ,.idx_in_prdy (idx_in_prdy) //|> o + ,.lut_index_sub_reg (lut_index_sub_reg[31:0]) //|> w + ,.lut_uflow_reg (lut_uflow_reg) //|> w + ,.sub_pvld (sub_pvld) //|> w + ); +//log2 function +NV_DW_lsd #(.a_width(32 )) log2_dw_lsd(.a(lut_index_sub_reg[31:0]), .enc(leadzero[4:0]), .dec()); //unsigned +assign log2_lut_index[31:0] = (lut_uflow_reg | !(|lut_index_sub_reg)) ? {32 {1'b0}} : (32 -2 - leadzero[4:0]); //morework +assign filter_frac[31:0] = (1 << log2_lut_index) - 1 ; +assign log2_lut_frac[31:0] = lut_index_sub_reg & filter_frac; +//log2 end +assign log2_lut_index_tru[8:0] = log2_lut_index[8:0]; //always positive +NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.log2_lut_frac (log2_lut_frac[31:0]) //|< w + ,.log2_lut_index_tru (log2_lut_index_tru[8:0]) //|< w + ,.log2_prdy (log2_prdy) //|< w + ,.lut_uflow_reg (lut_uflow_reg) //|< w + ,.sub_pvld (sub_pvld) //|< w + ,.log2_lut_frac_reg (log2_lut_frac_reg[31:0]) //|> w + ,.log2_lut_index_reg (log2_lut_index_reg[8:0]) //|> w + ,.log2_pvld (log2_pvld) //|> w + ,.lut_uflow_reg2 (lut_uflow_reg2) //|> w + ,.sub_prdy (sub_prdy) //|> w + ); +assign cfg_lut_offset_ext[8:0] = {{1{cfg_lut_offset[7]}}, cfg_lut_offset[7:0]}; +assign lut_uflow_mid = $signed({1'b0,log2_lut_index_reg[8:0]}) < $signed(cfg_lut_offset_ext[8:0]); //morework +assign {mon_lutmid_sub_c[1:0],lut_index_sub_mid_tmp[8:0]} = $signed({1'b0,log2_lut_index_reg[8:0]}) - $signed(cfg_lut_offset_ext[8:0]); //morework +assign lut_index_sub_mid[8:0] = (lut_uflow_reg2 | lut_uflow_mid) ? 0 : lut_index_sub_mid_tmp[8:0]; +assign lut_oflow_final = (lut_index_sub_mid >= LUT_DEPTH -1); +assign lut_uflow_final = lut_uflow_reg2 | lut_uflow_mid; +//index integar +always @( + lut_oflow_final + or lut_index_sub_mid + ) begin + if (lut_oflow_final) + lut_index_final[8:0] = LUT_DEPTH - 1; + else + lut_index_final[8:0] = lut_index_sub_mid[8:0]; +end +//index fraction +assign lut_frac_final[34:0] = {{(35 - 32 ){1'b0}},log2_lut_frac_reg[31:0]} << (35 - log2_lut_index_reg[8:0]); +NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_out_prdy (idx_out_prdy) //|< i + ,.log2_pvld (log2_pvld) //|< w + ,.lut_frac_final (lut_frac_final[34:0]) //|< w + ,.lut_index_final (lut_index_final[8:0]) //|< r + ,.lut_oflow_final (lut_oflow_final) //|< w + ,.lut_uflow_final (lut_uflow_final) //|< w + ,.idx_out_pvld (idx_out_pvld) //|> o + ,.log2_prdy (log2_prdy) //|> w + ,.lut_frac_out (lut_frac_out[34:0]) //|> o + ,.lut_index_out (lut_index_out[8:0]) //|> o + ,.lut_oflow_out (lut_oflow_out) //|> o + ,.lut_uflow_out (lut_uflow_out) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_lut_expn +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_reg,lut_index_sub_reg[31:0]} (sub_pvld,sub_prdy) <= {lut_uflow_in,lut_index_sub[31:0]} (idx_in_pvld,idx_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx_in_pvld + ,lut_index_sub + ,lut_uflow_in + ,sub_prdy + ,idx_in_prdy + ,lut_index_sub_reg + ,lut_uflow_reg + ,sub_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx_in_pvld; +input [31:0] lut_index_sub; +input lut_uflow_in; +input sub_prdy; +output idx_in_prdy; +output [31:0] lut_index_sub_reg; +output lut_uflow_reg; +output sub_pvld; +reg idx_in_prdy; +reg [31:0] lut_index_sub_reg; +reg lut_uflow_reg; +reg [32:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32:0] p1_skid_data; +reg [32:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg sub_pvld; +//## pipe (1) skid buffer +always @( + idx_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = idx_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + idx_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + idx_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {lut_uflow_in,lut_index_sub[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or idx_in_pvld + or p1_skid_valid + or lut_uflow_in + or lut_index_sub + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? idx_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {lut_uflow_in,lut_index_sub[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_prdy + or p1_pipe_data + ) begin + sub_pvld = p1_pipe_valid; + p1_pipe_ready = sub_prdy; + {lut_uflow_reg,lut_index_sub_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_pvld^sub_prdy^idx_in_pvld^idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (idx_in_pvld && !idx_in_prdy), (idx_in_pvld), (idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_reg2,log2_lut_index_reg[8:0],log2_lut_frac_reg[31:0]} (log2_pvld,log2_prdy) <= {lut_uflow_reg,log2_lut_index_tru[8:0],log2_lut_frac[31:0]} (sub_pvld,sub_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,log2_lut_frac + ,log2_lut_index_tru + ,log2_prdy + ,lut_uflow_reg + ,sub_pvld + ,log2_lut_frac_reg + ,log2_lut_index_reg + ,log2_pvld + ,lut_uflow_reg2 + ,sub_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] log2_lut_frac; +input [8:0] log2_lut_index_tru; +input log2_prdy; +input lut_uflow_reg; +input sub_pvld; +output [31:0] log2_lut_frac_reg; +output [8:0] log2_lut_index_reg; +output log2_pvld; +output lut_uflow_reg2; +output sub_prdy; +reg [31:0] log2_lut_frac_reg; +reg [8:0] log2_lut_index_reg; +reg log2_pvld; +reg lut_uflow_reg2; +reg [41:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [41:0] p2_skid_data; +reg [41:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_prdy; +//## pipe (2) skid buffer +always @( + sub_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {lut_uflow_reg,log2_lut_index_tru[8:0],log2_lut_frac[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_pvld + or p2_skid_valid + or lut_uflow_reg + or log2_lut_index_tru + or log2_lut_frac + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {lut_uflow_reg,log2_lut_index_tru[8:0],log2_lut_frac[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or log2_prdy + or p2_pipe_data + ) begin + log2_pvld = p2_pipe_valid; + p2_pipe_ready = log2_prdy; + {lut_uflow_reg2,log2_lut_index_reg[8:0],log2_lut_frac_reg[31:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (log2_pvld^log2_prdy^sub_pvld^sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_pvld && !sub_prdy), (sub_pvld), (sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} (idx_out_pvld,idx_out_prdy) <= {lut_uflow_final,lut_oflow_final,lut_index_final[8:0],lut_frac_final[34:0]} (log2_pvld,log2_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx_out_prdy + ,log2_pvld + ,lut_frac_final + ,lut_index_final + ,lut_oflow_final + ,lut_uflow_final + ,idx_out_pvld + ,log2_prdy + ,lut_frac_out + ,lut_index_out + ,lut_oflow_out + ,lut_uflow_out + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx_out_prdy; +input log2_pvld; +input [34:0] lut_frac_final; +input [8:0] lut_index_final; +input lut_oflow_final; +input lut_uflow_final; +output idx_out_pvld; +output log2_prdy; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +reg idx_out_pvld; +reg log2_prdy; +reg [34:0] lut_frac_out; +reg [8:0] lut_index_out; +reg lut_oflow_out; +reg lut_uflow_out; +reg [45:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [45:0] p3_skid_data; +reg [45:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + log2_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = log2_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + log2_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + log2_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {lut_uflow_final,lut_oflow_final,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or log2_pvld + or p3_skid_valid + or lut_uflow_final + or lut_oflow_final + or lut_index_final + or lut_frac_final + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? log2_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {lut_uflow_final,lut_oflow_final,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or idx_out_prdy + or p3_pipe_data + ) begin + idx_out_pvld = p3_pipe_valid; + p3_pipe_ready = idx_out_prdy; + {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (idx_out_pvld^idx_out_prdy^log2_pvld^log2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (log2_pvld && !log2_prdy), (log2_pvld), (log2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_expn.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_expn.v.vcp new file mode 100644 index 0000000..d16f0a6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_expn.v.vcp @@ -0,0 +1,795 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_lut_expn.v +module NV_NVDLA_SDP_HLS_lut_expn ( + cfg_lut_offset //|< i + ,cfg_lut_start //|< i + ,idx_data_in //|< i + ,idx_in_pvld //|< i + ,idx_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,idx_in_prdy //|> o + ,idx_out_pvld //|> o + ,lut_frac_out //|> o + ,lut_index_out //|> o + ,lut_oflow_out //|> o + ,lut_uflow_out //|> o + ); +parameter LUT_DEPTH = 256; +input [7:0] cfg_lut_offset; +input [31:0] cfg_lut_start; +input [31:0] idx_data_in; +input idx_in_pvld; +input idx_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output idx_in_prdy; +output idx_out_pvld; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +reg [8:0] lut_index_final; +wire [8:0] cfg_lut_offset_ext; +wire [31:0] filter_frac; +wire [4:0] leadzero; +wire [31:0] log2_lut_frac; +wire [31:0] log2_lut_frac_reg; +wire [31:0] log2_lut_index; +wire [8:0] log2_lut_index_reg; +wire [8:0] log2_lut_index_tru; +wire log2_prdy; +wire log2_pvld; +wire [34:0] lut_frac_final; +wire [31:0] lut_index_sub; +wire [8:0] lut_index_sub_mid; +wire [8:0] lut_index_sub_mid_tmp; +wire [31:0] lut_index_sub_reg; +wire [31:0] lut_index_sub_tmp; +wire lut_oflow_final; +wire lut_uflow_final; +wire lut_uflow_in; +wire lut_uflow_mid; +wire lut_uflow_reg; +wire lut_uflow_reg2; +wire mon_lutin_sub_c; +wire [1:0] mon_lutmid_sub_c; +wire sub_prdy; +wire sub_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign lut_uflow_in = ($signed(idx_data_in[31:0]) <= $signed(cfg_lut_start[31:0])); +assign {mon_lutin_sub_c,lut_index_sub_tmp[31:0]} = $signed(idx_data_in[31:0])- $signed(cfg_lut_start[31:0]); +//unsigned int +assign lut_index_sub[31:0] = lut_uflow_in ? 0 : lut_index_sub_tmp[31:0]; +NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_in_pvld (idx_in_pvld) //|< i + ,.lut_index_sub (lut_index_sub[31:0]) //|< w + ,.lut_uflow_in (lut_uflow_in) //|< w + ,.sub_prdy (sub_prdy) //|< w + ,.idx_in_prdy (idx_in_prdy) //|> o + ,.lut_index_sub_reg (lut_index_sub_reg[31:0]) //|> w + ,.lut_uflow_reg (lut_uflow_reg) //|> w + ,.sub_pvld (sub_pvld) //|> w + ); +//log2 function +NV_DW_lsd #(.a_width(32 )) log2_dw_lsd(.a(lut_index_sub_reg[31:0]), .enc(leadzero[4:0]), .dec()); //unsigned +assign log2_lut_index[31:0] = (lut_uflow_reg | !(|lut_index_sub_reg)) ? {32 {1'b0}} : (32 -2 - leadzero[4:0]); //morework +assign filter_frac[31:0] = (1 << log2_lut_index) - 1 ; +assign log2_lut_frac[31:0] = lut_index_sub_reg & filter_frac; +//log2 end +assign log2_lut_index_tru[8:0] = log2_lut_index[8:0]; //always positive +NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.log2_lut_frac (log2_lut_frac[31:0]) //|< w + ,.log2_lut_index_tru (log2_lut_index_tru[8:0]) //|< w + ,.log2_prdy (log2_prdy) //|< w + ,.lut_uflow_reg (lut_uflow_reg) //|< w + ,.sub_pvld (sub_pvld) //|< w + ,.log2_lut_frac_reg (log2_lut_frac_reg[31:0]) //|> w + ,.log2_lut_index_reg (log2_lut_index_reg[8:0]) //|> w + ,.log2_pvld (log2_pvld) //|> w + ,.lut_uflow_reg2 (lut_uflow_reg2) //|> w + ,.sub_prdy (sub_prdy) //|> w + ); +assign cfg_lut_offset_ext[8:0] = {{1{cfg_lut_offset[7]}}, cfg_lut_offset[7:0]}; +assign lut_uflow_mid = $signed({1'b0,log2_lut_index_reg[8:0]}) < $signed(cfg_lut_offset_ext[8:0]); //morework +assign {mon_lutmid_sub_c[1:0],lut_index_sub_mid_tmp[8:0]} = $signed({1'b0,log2_lut_index_reg[8:0]}) - $signed(cfg_lut_offset_ext[8:0]); //morework +assign lut_index_sub_mid[8:0] = (lut_uflow_reg2 | lut_uflow_mid) ? 0 : lut_index_sub_mid_tmp[8:0]; +assign lut_oflow_final = (lut_index_sub_mid >= LUT_DEPTH -1); +assign lut_uflow_final = lut_uflow_reg2 | lut_uflow_mid; +//index integar +always @( + lut_oflow_final + or lut_index_sub_mid + ) begin + if (lut_oflow_final) + lut_index_final[8:0] = LUT_DEPTH - 1; + else + lut_index_final[8:0] = lut_index_sub_mid[8:0]; +end +//index fraction +assign lut_frac_final[34:0] = {{(35 - 32 ){1'b0}},log2_lut_frac_reg[31:0]} << (35 - log2_lut_index_reg[8:0]); +NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_out_prdy (idx_out_prdy) //|< i + ,.log2_pvld (log2_pvld) //|< w + ,.lut_frac_final (lut_frac_final[34:0]) //|< w + ,.lut_index_final (lut_index_final[8:0]) //|< r + ,.lut_oflow_final (lut_oflow_final) //|< w + ,.lut_uflow_final (lut_uflow_final) //|< w + ,.idx_out_pvld (idx_out_pvld) //|> o + ,.log2_prdy (log2_prdy) //|> w + ,.lut_frac_out (lut_frac_out[34:0]) //|> o + ,.lut_index_out (lut_index_out[8:0]) //|> o + ,.lut_oflow_out (lut_oflow_out) //|> o + ,.lut_uflow_out (lut_uflow_out) //|> o + ); +endmodule // NV_NVDLA_SDP_HLS_lut_expn +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_reg,lut_index_sub_reg[31:0]} (sub_pvld,sub_prdy) <= {lut_uflow_in,lut_index_sub[31:0]} (idx_in_pvld,idx_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx_in_pvld + ,lut_index_sub + ,lut_uflow_in + ,sub_prdy + ,idx_in_prdy + ,lut_index_sub_reg + ,lut_uflow_reg + ,sub_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx_in_pvld; +input [31:0] lut_index_sub; +input lut_uflow_in; +input sub_prdy; +output idx_in_prdy; +output [31:0] lut_index_sub_reg; +output lut_uflow_reg; +output sub_pvld; +reg idx_in_prdy; +reg [31:0] lut_index_sub_reg; +reg lut_uflow_reg; +reg [32:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [32:0] p1_skid_data; +reg [32:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg sub_pvld; +//## pipe (1) skid buffer +always @( + idx_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = idx_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + idx_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + idx_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {lut_uflow_in,lut_index_sub[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or idx_in_pvld + or p1_skid_valid + or lut_uflow_in + or lut_index_sub + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? idx_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {lut_uflow_in,lut_index_sub[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_prdy + or p1_pipe_data + ) begin + sub_pvld = p1_pipe_valid; + p1_pipe_ready = sub_prdy; + {lut_uflow_reg,lut_index_sub_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_pvld^sub_prdy^idx_in_pvld^idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (idx_in_pvld && !idx_in_prdy), (idx_in_pvld), (idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_reg2,log2_lut_index_reg[8:0],log2_lut_frac_reg[31:0]} (log2_pvld,log2_prdy) <= {lut_uflow_reg,log2_lut_index_tru[8:0],log2_lut_frac[31:0]} (sub_pvld,sub_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,log2_lut_frac + ,log2_lut_index_tru + ,log2_prdy + ,lut_uflow_reg + ,sub_pvld + ,log2_lut_frac_reg + ,log2_lut_index_reg + ,log2_pvld + ,lut_uflow_reg2 + ,sub_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] log2_lut_frac; +input [8:0] log2_lut_index_tru; +input log2_prdy; +input lut_uflow_reg; +input sub_pvld; +output [31:0] log2_lut_frac_reg; +output [8:0] log2_lut_index_reg; +output log2_pvld; +output lut_uflow_reg2; +output sub_prdy; +reg [31:0] log2_lut_frac_reg; +reg [8:0] log2_lut_index_reg; +reg log2_pvld; +reg lut_uflow_reg2; +reg [41:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [41:0] p2_skid_data; +reg [41:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_prdy; +//## pipe (2) skid buffer +always @( + sub_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {lut_uflow_reg,log2_lut_index_tru[8:0],log2_lut_frac[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_pvld + or p2_skid_valid + or lut_uflow_reg + or log2_lut_index_tru + or log2_lut_frac + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {lut_uflow_reg,log2_lut_index_tru[8:0],log2_lut_frac[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or log2_prdy + or p2_pipe_data + ) begin + log2_pvld = p2_pipe_valid; + p2_pipe_ready = log2_prdy; + {lut_uflow_reg2,log2_lut_index_reg[8:0],log2_lut_frac_reg[31:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (log2_pvld^log2_prdy^sub_pvld^sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_pvld && !sub_prdy), (sub_pvld), (sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} (idx_out_pvld,idx_out_prdy) <= {lut_uflow_final,lut_oflow_final,lut_index_final[8:0],lut_frac_final[34:0]} (log2_pvld,log2_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx_out_prdy + ,log2_pvld + ,lut_frac_final + ,lut_index_final + ,lut_oflow_final + ,lut_uflow_final + ,idx_out_pvld + ,log2_prdy + ,lut_frac_out + ,lut_index_out + ,lut_oflow_out + ,lut_uflow_out + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx_out_prdy; +input log2_pvld; +input [34:0] lut_frac_final; +input [8:0] lut_index_final; +input lut_oflow_final; +input lut_uflow_final; +output idx_out_pvld; +output log2_prdy; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +reg idx_out_pvld; +reg log2_prdy; +reg [34:0] lut_frac_out; +reg [8:0] lut_index_out; +reg lut_oflow_out; +reg lut_uflow_out; +reg [45:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [45:0] p3_skid_data; +reg [45:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + log2_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = log2_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + log2_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + log2_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {lut_uflow_final,lut_oflow_final,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or log2_pvld + or p3_skid_valid + or lut_uflow_final + or lut_oflow_final + or lut_index_final + or lut_frac_final + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? log2_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {lut_uflow_final,lut_oflow_final,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or idx_out_prdy + or p3_pipe_data + ) begin + idx_out_pvld = p3_pipe_valid; + p3_pipe_ready = idx_out_prdy; + {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (idx_out_pvld^idx_out_prdy^log2_pvld^log2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (log2_pvld && !log2_prdy), (log2_pvld), (log2_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_EXPN_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_line.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_line.v new file mode 100644 index 0000000..3de37d7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_line.v @@ -0,0 +1,780 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_lut_line.v +module NV_NVDLA_SDP_HLS_lut_line ( + cfg_lut_sel //|< i + ,cfg_lut_start //|< i + ,idx_data_in //|< i + ,idx_in_pvld //|< i + ,idx_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,idx_in_prdy //|> o + ,idx_out_pvld //|> o + ,lut_frac_out //|> o + ,lut_index_out //|> o + ,lut_oflow_out //|> o + ,lut_uflow_out //|> o + ); +parameter LUT_DEPTH = 256; +input [7:0] cfg_lut_sel; +input [31:0] cfg_lut_start; +input [31:0] idx_data_in; +input idx_in_pvld; +input idx_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output idx_in_prdy; +output idx_out_pvld; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +reg [8:0] lut_index_final; +wire [7:0] cfg_lut_sel_reg; +wire [31:0] cfg_lut_start_reg; +wire [31:0] idx_data_reg; +wire [34:0] lut_frac_final; +wire [34:0] lut_frac_shift; +wire [8:0] lut_index_shift; +wire [31:0] lut_index_sub; +wire [31:0] lut_index_sub_reg; +wire [31:0] lut_index_sub_tmp; +wire lut_oflow; +wire lut_uflow; +wire lut_uflow_in; +wire mon_index_sub_c; +wire mux_prdy; +wire mux_pvld; +wire sub_prdy; +wire sub_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_lut_sel (cfg_lut_sel[7:0]) //|< i + ,.cfg_lut_start (cfg_lut_start[31:0]) //|< i + ,.idx_data_in (idx_data_in[31:0]) //|< i + ,.idx_in_pvld (idx_in_pvld) //|< i + ,.mux_prdy (mux_prdy) //|< w + ,.cfg_lut_sel_reg (cfg_lut_sel_reg[7:0]) //|> w + ,.cfg_lut_start_reg (cfg_lut_start_reg[31:0]) //|> w + ,.idx_data_reg (idx_data_reg[31:0]) //|> w + ,.idx_in_prdy (idx_in_prdy) //|> o + ,.mux_pvld (mux_pvld) //|> w + ); +assign lut_uflow_in = ($signed(idx_data_reg[31:0]) <= $signed(cfg_lut_start_reg[31:0])); +assign {mon_index_sub_c,lut_index_sub_tmp[31:0]} = $signed(idx_data_reg[31:0])- $signed(cfg_lut_start_reg[31:0]); +//unsigned int +assign lut_index_sub[31:0] = lut_uflow_in ? 0 : lut_index_sub_tmp[31:0]; +NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_index_sub (lut_index_sub[31:0]) //|< w + ,.lut_uflow_in (lut_uflow_in) //|< w + ,.mux_pvld (mux_pvld) //|< w + ,.sub_prdy (sub_prdy) //|< w + ,.lut_index_sub_reg (lut_index_sub_reg[31:0]) //|> w + ,.lut_uflow (lut_uflow) //|> w + ,.mux_prdy (mux_prdy) //|> w + ,.sub_pvld (sub_pvld) //|> w + ); +//saturation and truncate, but no rounding +NV_NVDLA_HLS_shiftrightusz #(.IN_WIDTH(32 ),.OUT_WIDTH(9 ),.FRAC_WIDTH(35 ),.SHIFT_WIDTH(8 )) lut_index_shiftright_usz ( + .data_in (lut_index_sub_reg[31:0]) //|< w + ,.shift_num (cfg_lut_sel_reg[7:0]) //|< w + ,.data_out (lut_index_shift[8:0]) //|> w + ,.frac_out (lut_frac_shift[34:0]) //|> w + ); +assign lut_oflow = (lut_index_shift[8:0] >= LUT_DEPTH -1); +//index integar +always @( + lut_oflow + or lut_index_shift + ) begin + if (lut_oflow) + lut_index_final[8:0] = LUT_DEPTH - 1; + else + lut_index_final[8:0] = lut_index_shift[8:0]; +end +assign lut_frac_final[34:0] = lut_frac_shift[34:0]; +NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_out_prdy (idx_out_prdy) //|< i + ,.lut_frac_final (lut_frac_final[34:0]) //|< w + ,.lut_index_final (lut_index_final[8:0]) //|< r + ,.lut_oflow (lut_oflow) //|< w + ,.lut_uflow (lut_uflow) //|< w + ,.sub_pvld (sub_pvld) //|< w + ,.idx_out_pvld (idx_out_pvld) //|> o + ,.lut_frac_out (lut_frac_out[34:0]) //|> o + ,.lut_index_out (lut_index_out[8:0]) //|> o + ,.lut_oflow_out (lut_oflow_out) //|> o + ,.lut_uflow_out (lut_uflow_out) //|> o + ,.sub_prdy (sub_prdy) //|> w + ); +endmodule // NV_NVDLA_SDP_HLS_lut_line +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {cfg_lut_sel_reg[7:0],cfg_lut_start_reg[31:0],idx_data_reg[31:0]} (mux_pvld,mux_prdy) <= {cfg_lut_sel[7:0],cfg_lut_start[31:0],idx_data_in[31:0]} (idx_in_pvld,idx_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_lut_sel + ,cfg_lut_start + ,idx_data_in + ,idx_in_pvld + ,mux_prdy + ,cfg_lut_sel_reg + ,cfg_lut_start_reg + ,idx_data_reg + ,idx_in_prdy + ,mux_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [7:0] cfg_lut_sel; +input [31:0] cfg_lut_start; +input [31:0] idx_data_in; +input idx_in_pvld; +input mux_prdy; +output [7:0] cfg_lut_sel_reg; +output [31:0] cfg_lut_start_reg; +output [31:0] idx_data_reg; +output idx_in_prdy; +output mux_pvld; +reg [7:0] cfg_lut_sel_reg; +reg [31:0] cfg_lut_start_reg; +reg [31:0] idx_data_reg; +reg idx_in_prdy; +reg mux_pvld; +reg [71:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [71:0] p1_skid_data; +reg [71:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + idx_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = idx_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + idx_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + idx_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {cfg_lut_sel[7:0],cfg_lut_start[31:0],idx_data_in[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or idx_in_pvld + or p1_skid_valid + or cfg_lut_sel + or cfg_lut_start + or idx_data_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? idx_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {cfg_lut_sel[7:0],cfg_lut_start[31:0],idx_data_in[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mux_prdy + or p1_pipe_data + ) begin + mux_pvld = p1_pipe_valid; + p1_pipe_ready = mux_prdy; + {cfg_lut_sel_reg[7:0],cfg_lut_start_reg[31:0],idx_data_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mux_pvld^mux_prdy^idx_in_pvld^idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (idx_in_pvld && !idx_in_prdy), (idx_in_pvld), (idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow,lut_index_sub_reg[31:0]} (sub_pvld,sub_prdy) <= {lut_uflow_in,lut_index_sub[31:0]} (mux_pvld,mux_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_index_sub + ,lut_uflow_in + ,mux_pvld + ,sub_prdy + ,lut_index_sub_reg + ,lut_uflow + ,mux_prdy + ,sub_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] lut_index_sub; +input lut_uflow_in; +input mux_pvld; +input sub_prdy; +output [31:0] lut_index_sub_reg; +output lut_uflow; +output mux_prdy; +output sub_pvld; +reg [31:0] lut_index_sub_reg; +reg lut_uflow; +reg mux_prdy; +reg [32:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32:0] p2_skid_data; +reg [32:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_pvld; +//## pipe (2) skid buffer +always @( + mux_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = mux_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + mux_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + mux_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {lut_uflow_in,lut_index_sub[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or mux_pvld + or p2_skid_valid + or lut_uflow_in + or lut_index_sub + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? mux_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {lut_uflow_in,lut_index_sub[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or sub_prdy + or p2_pipe_data + ) begin + sub_pvld = p2_pipe_valid; + p2_pipe_ready = sub_prdy; + {lut_uflow,lut_index_sub_reg[31:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_pvld^sub_prdy^mux_pvld^mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mux_pvld && !mux_prdy), (mux_pvld), (mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} (idx_out_pvld,idx_out_prdy) <= {lut_uflow,lut_oflow,lut_index_final[8:0],lut_frac_final[34:0]} (sub_pvld,sub_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx_out_prdy + ,lut_frac_final + ,lut_index_final + ,lut_oflow + ,lut_uflow + ,sub_pvld + ,idx_out_pvld + ,lut_frac_out + ,lut_index_out + ,lut_oflow_out + ,lut_uflow_out + ,sub_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx_out_prdy; +input [34:0] lut_frac_final; +input [8:0] lut_index_final; +input lut_oflow; +input lut_uflow; +input sub_pvld; +output idx_out_pvld; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +output sub_prdy; +reg idx_out_pvld; +reg [34:0] lut_frac_out; +reg [8:0] lut_index_out; +reg lut_oflow_out; +reg lut_uflow_out; +reg [45:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [45:0] p3_skid_data; +reg [45:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg sub_prdy; +//## pipe (3) skid buffer +always @( + sub_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = sub_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + sub_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + sub_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {lut_uflow,lut_oflow,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or sub_pvld + or p3_skid_valid + or lut_uflow + or lut_oflow + or lut_index_final + or lut_frac_final + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? sub_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {lut_uflow,lut_oflow,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or idx_out_prdy + or p3_pipe_data + ) begin + idx_out_pvld = p3_pipe_valid; + p3_pipe_ready = idx_out_prdy; + {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (idx_out_pvld^idx_out_prdy^sub_pvld^sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (sub_pvld && !sub_prdy), (sub_pvld), (sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_line.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_line.v.vcp new file mode 100644 index 0000000..3de37d7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_lut_line.v.vcp @@ -0,0 +1,780 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_lut_line.v +module NV_NVDLA_SDP_HLS_lut_line ( + cfg_lut_sel //|< i + ,cfg_lut_start //|< i + ,idx_data_in //|< i + ,idx_in_pvld //|< i + ,idx_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,idx_in_prdy //|> o + ,idx_out_pvld //|> o + ,lut_frac_out //|> o + ,lut_index_out //|> o + ,lut_oflow_out //|> o + ,lut_uflow_out //|> o + ); +parameter LUT_DEPTH = 256; +input [7:0] cfg_lut_sel; +input [31:0] cfg_lut_start; +input [31:0] idx_data_in; +input idx_in_pvld; +input idx_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output idx_in_prdy; +output idx_out_pvld; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +reg [8:0] lut_index_final; +wire [7:0] cfg_lut_sel_reg; +wire [31:0] cfg_lut_start_reg; +wire [31:0] idx_data_reg; +wire [34:0] lut_frac_final; +wire [34:0] lut_frac_shift; +wire [8:0] lut_index_shift; +wire [31:0] lut_index_sub; +wire [31:0] lut_index_sub_reg; +wire [31:0] lut_index_sub_tmp; +wire lut_oflow; +wire lut_uflow; +wire lut_uflow_in; +wire mon_index_sub_c; +wire mux_prdy; +wire mux_pvld; +wire sub_prdy; +wire sub_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_lut_sel (cfg_lut_sel[7:0]) //|< i + ,.cfg_lut_start (cfg_lut_start[31:0]) //|< i + ,.idx_data_in (idx_data_in[31:0]) //|< i + ,.idx_in_pvld (idx_in_pvld) //|< i + ,.mux_prdy (mux_prdy) //|< w + ,.cfg_lut_sel_reg (cfg_lut_sel_reg[7:0]) //|> w + ,.cfg_lut_start_reg (cfg_lut_start_reg[31:0]) //|> w + ,.idx_data_reg (idx_data_reg[31:0]) //|> w + ,.idx_in_prdy (idx_in_prdy) //|> o + ,.mux_pvld (mux_pvld) //|> w + ); +assign lut_uflow_in = ($signed(idx_data_reg[31:0]) <= $signed(cfg_lut_start_reg[31:0])); +assign {mon_index_sub_c,lut_index_sub_tmp[31:0]} = $signed(idx_data_reg[31:0])- $signed(cfg_lut_start_reg[31:0]); +//unsigned int +assign lut_index_sub[31:0] = lut_uflow_in ? 0 : lut_index_sub_tmp[31:0]; +NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_index_sub (lut_index_sub[31:0]) //|< w + ,.lut_uflow_in (lut_uflow_in) //|< w + ,.mux_pvld (mux_pvld) //|< w + ,.sub_prdy (sub_prdy) //|< w + ,.lut_index_sub_reg (lut_index_sub_reg[31:0]) //|> w + ,.lut_uflow (lut_uflow) //|> w + ,.mux_prdy (mux_prdy) //|> w + ,.sub_pvld (sub_pvld) //|> w + ); +//saturation and truncate, but no rounding +NV_NVDLA_HLS_shiftrightusz #(.IN_WIDTH(32 ),.OUT_WIDTH(9 ),.FRAC_WIDTH(35 ),.SHIFT_WIDTH(8 )) lut_index_shiftright_usz ( + .data_in (lut_index_sub_reg[31:0]) //|< w + ,.shift_num (cfg_lut_sel_reg[7:0]) //|< w + ,.data_out (lut_index_shift[8:0]) //|> w + ,.frac_out (lut_frac_shift[34:0]) //|> w + ); +assign lut_oflow = (lut_index_shift[8:0] >= LUT_DEPTH -1); +//index integar +always @( + lut_oflow + or lut_index_shift + ) begin + if (lut_oflow) + lut_index_final[8:0] = LUT_DEPTH - 1; + else + lut_index_final[8:0] = lut_index_shift[8:0]; +end +assign lut_frac_final[34:0] = lut_frac_shift[34:0]; +NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.idx_out_prdy (idx_out_prdy) //|< i + ,.lut_frac_final (lut_frac_final[34:0]) //|< w + ,.lut_index_final (lut_index_final[8:0]) //|< r + ,.lut_oflow (lut_oflow) //|< w + ,.lut_uflow (lut_uflow) //|< w + ,.sub_pvld (sub_pvld) //|< w + ,.idx_out_pvld (idx_out_pvld) //|> o + ,.lut_frac_out (lut_frac_out[34:0]) //|> o + ,.lut_index_out (lut_index_out[8:0]) //|> o + ,.lut_oflow_out (lut_oflow_out) //|> o + ,.lut_uflow_out (lut_uflow_out) //|> o + ,.sub_prdy (sub_prdy) //|> w + ); +endmodule // NV_NVDLA_SDP_HLS_lut_line +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {cfg_lut_sel_reg[7:0],cfg_lut_start_reg[31:0],idx_data_reg[31:0]} (mux_pvld,mux_prdy) <= {cfg_lut_sel[7:0],cfg_lut_start[31:0],idx_data_in[31:0]} (idx_in_pvld,idx_in_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_lut_sel + ,cfg_lut_start + ,idx_data_in + ,idx_in_pvld + ,mux_prdy + ,cfg_lut_sel_reg + ,cfg_lut_start_reg + ,idx_data_reg + ,idx_in_prdy + ,mux_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [7:0] cfg_lut_sel; +input [31:0] cfg_lut_start; +input [31:0] idx_data_in; +input idx_in_pvld; +input mux_prdy; +output [7:0] cfg_lut_sel_reg; +output [31:0] cfg_lut_start_reg; +output [31:0] idx_data_reg; +output idx_in_prdy; +output mux_pvld; +reg [7:0] cfg_lut_sel_reg; +reg [31:0] cfg_lut_start_reg; +reg [31:0] idx_data_reg; +reg idx_in_prdy; +reg mux_pvld; +reg [71:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [71:0] p1_skid_data; +reg [71:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +//## pipe (1) skid buffer +always @( + idx_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = idx_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + idx_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + idx_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {cfg_lut_sel[7:0],cfg_lut_start[31:0],idx_data_in[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or idx_in_pvld + or p1_skid_valid + or cfg_lut_sel + or cfg_lut_start + or idx_data_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? idx_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {cfg_lut_sel[7:0],cfg_lut_start[31:0],idx_data_in[31:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or mux_prdy + or p1_pipe_data + ) begin + mux_pvld = p1_pipe_valid; + p1_pipe_ready = mux_prdy; + {cfg_lut_sel_reg[7:0],cfg_lut_start_reg[31:0],idx_data_reg[31:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mux_pvld^mux_prdy^idx_in_pvld^idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (idx_in_pvld && !idx_in_prdy), (idx_in_pvld), (idx_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow,lut_index_sub_reg[31:0]} (sub_pvld,sub_prdy) <= {lut_uflow_in,lut_index_sub[31:0]} (mux_pvld,mux_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,lut_index_sub + ,lut_uflow_in + ,mux_pvld + ,sub_prdy + ,lut_index_sub_reg + ,lut_uflow + ,mux_prdy + ,sub_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] lut_index_sub; +input lut_uflow_in; +input mux_pvld; +input sub_prdy; +output [31:0] lut_index_sub_reg; +output lut_uflow; +output mux_prdy; +output sub_pvld; +reg [31:0] lut_index_sub_reg; +reg lut_uflow; +reg mux_prdy; +reg [32:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [32:0] p2_skid_data; +reg [32:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_pvld; +//## pipe (2) skid buffer +always @( + mux_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = mux_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + mux_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + mux_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {lut_uflow_in,lut_index_sub[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or mux_pvld + or p2_skid_valid + or lut_uflow_in + or lut_index_sub + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? mux_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {lut_uflow_in,lut_index_sub[31:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or sub_prdy + or p2_pipe_data + ) begin + sub_pvld = p2_pipe_valid; + p2_pipe_ready = sub_prdy; + {lut_uflow,lut_index_sub_reg[31:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_pvld^sub_prdy^mux_pvld^mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (mux_pvld && !mux_prdy), (mux_pvld), (mux_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} (idx_out_pvld,idx_out_prdy) <= {lut_uflow,lut_oflow,lut_index_final[8:0],lut_frac_final[34:0]} (sub_pvld,sub_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,idx_out_prdy + ,lut_frac_final + ,lut_index_final + ,lut_oflow + ,lut_uflow + ,sub_pvld + ,idx_out_pvld + ,lut_frac_out + ,lut_index_out + ,lut_oflow_out + ,lut_uflow_out + ,sub_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input idx_out_prdy; +input [34:0] lut_frac_final; +input [8:0] lut_index_final; +input lut_oflow; +input lut_uflow; +input sub_pvld; +output idx_out_pvld; +output [34:0] lut_frac_out; +output [8:0] lut_index_out; +output lut_oflow_out; +output lut_uflow_out; +output sub_prdy; +reg idx_out_pvld; +reg [34:0] lut_frac_out; +reg [8:0] lut_index_out; +reg lut_oflow_out; +reg lut_uflow_out; +reg [45:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [45:0] p3_skid_data; +reg [45:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg sub_prdy; +//## pipe (3) skid buffer +always @( + sub_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = sub_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + sub_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + sub_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {lut_uflow,lut_oflow,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or sub_pvld + or p3_skid_valid + or lut_uflow + or lut_oflow + or lut_index_final + or lut_frac_final + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? sub_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {lut_uflow,lut_oflow,lut_index_final[8:0],lut_frac_final[34:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or idx_out_prdy + or p3_pipe_data + ) begin + idx_out_pvld = p3_pipe_valid; + p3_pipe_ready = idx_out_prdy; + {lut_uflow_out,lut_oflow_out,lut_index_out[8:0],lut_frac_out[34:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (idx_out_pvld^idx_out_prdy^sub_pvld^sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (sub_pvld && !sub_prdy), (sub_pvld), (sub_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_SDP_HLS_LUT_LINE_pipe_p3 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_prelu.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_prelu.v new file mode 100644 index 0000000..0cbdd8d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_prelu.v @@ -0,0 +1,44 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_prelu.v +module NV_NVDLA_SDP_HLS_prelu ( + cfg_prelu_en + ,data_in + ,op_in + ,data_out + ); +parameter IN_WIDTH = 32; +parameter OP_WIDTH = 32; +parameter OUT_WIDTH = 64; +input cfg_prelu_en; +input [IN_WIDTH-1:0] data_in; +input [OP_WIDTH-1:0] op_in; +output [OUT_WIDTH-1:0] data_out; +reg [OUT_WIDTH-1:0] data_out; +wire data_in_sign; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_in_sign = data_in[IN_WIDTH-1]; +always @( + cfg_prelu_en + or data_in_sign + or data_in + or op_in + ) begin + if (cfg_prelu_en & !data_in_sign) + data_out[((OUT_WIDTH) - 1):0] = {{(OUT_WIDTH-IN_WIDTH){1'b0}},data_in[IN_WIDTH-1:0]}; + else + data_out[((OUT_WIDTH) - 1):0] = $signed(data_in[((IN_WIDTH) - 1):0]) * $signed(op_in[((OP_WIDTH) - 1):0]); +end +endmodule // NV_NVDLA_SDP_HLS_prelu diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_prelu.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_prelu.v.vcp new file mode 100644 index 0000000..0cbdd8d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_prelu.v.vcp @@ -0,0 +1,44 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_prelu.v +module NV_NVDLA_SDP_HLS_prelu ( + cfg_prelu_en + ,data_in + ,op_in + ,data_out + ); +parameter IN_WIDTH = 32; +parameter OP_WIDTH = 32; +parameter OUT_WIDTH = 64; +input cfg_prelu_en; +input [IN_WIDTH-1:0] data_in; +input [OP_WIDTH-1:0] op_in; +output [OUT_WIDTH-1:0] data_out; +reg [OUT_WIDTH-1:0] data_out; +wire data_in_sign; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_in_sign = data_in[IN_WIDTH-1]; +always @( + cfg_prelu_en + or data_in_sign + or data_in + or op_in + ) begin + if (cfg_prelu_en & !data_in_sign) + data_out[((OUT_WIDTH) - 1):0] = {{(OUT_WIDTH-IN_WIDTH){1'b0}},data_in[IN_WIDTH-1:0]}; + else + data_out[((OUT_WIDTH) - 1):0] = $signed(data_in[((IN_WIDTH) - 1):0]) * $signed(op_in[((OP_WIDTH) - 1):0]); +end +endmodule // NV_NVDLA_SDP_HLS_prelu diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_relu.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_relu.v new file mode 100644 index 0000000..6d2e4d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_relu.v @@ -0,0 +1,36 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_relu.v +module NV_NVDLA_SDP_HLS_relu ( + data_in + ,data_out + ); +parameter DATA_WIDTH = 32; +input [DATA_WIDTH-1:0] data_in; +output [DATA_WIDTH-1:0] data_out; +reg [DATA_WIDTH-1:0] data_out; +wire data_in_sign; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_in_sign = data_in[DATA_WIDTH-1]; +always @( + data_in_sign + or data_in + ) begin + if (!data_in_sign) + data_out[((DATA_WIDTH) - 1):0] = data_in[((DATA_WIDTH) - 1):0]; + else + data_out[((DATA_WIDTH) - 1):0] = {DATA_WIDTH{1'b0}}; +end +endmodule // NV_NVDLA_SDP_HLS_relu diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_relu.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_relu.v.vcp new file mode 100644 index 0000000..6d2e4d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_relu.v.vcp @@ -0,0 +1,36 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_relu.v +module NV_NVDLA_SDP_HLS_relu ( + data_in + ,data_out + ); +parameter DATA_WIDTH = 32; +input [DATA_WIDTH-1:0] data_in; +output [DATA_WIDTH-1:0] data_out; +reg [DATA_WIDTH-1:0] data_out; +wire data_in_sign; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_in_sign = data_in[DATA_WIDTH-1]; +always @( + data_in_sign + or data_in + ) begin + if (!data_in_sign) + data_out[((DATA_WIDTH) - 1):0] = data_in[((DATA_WIDTH) - 1):0]; + else + data_out[((DATA_WIDTH) - 1):0] = {DATA_WIDTH{1'b0}}; +end +endmodule // NV_NVDLA_SDP_HLS_relu diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_sync2data.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_sync2data.v new file mode 100644 index 0000000..5d618cd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_sync2data.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_sync2data.v +module NV_NVDLA_SDP_HLS_sync2data ( + chn1_en + ,chn1_in_pvld + ,chn2_en + ,chn2_in_pvld + ,chn_out_prdy + ,data1_in + ,data2_in + ,chn1_in_prdy + ,chn2_in_prdy + ,chn_out_pvld + ,data1_out + ,data2_out + ); +parameter DATA1_WIDTH = 32; +parameter DATA2_WIDTH = 32; +input chn1_en; +input chn2_en; +input chn1_in_pvld; +output chn1_in_prdy; +input chn2_in_pvld; +output chn2_in_prdy; +output chn_out_pvld; +input chn_out_prdy; +input [DATA1_WIDTH-1:0] data1_in; +input [DATA2_WIDTH-1:0] data2_in; +output [DATA1_WIDTH-1:0] data1_out; +output [DATA2_WIDTH-1:0] data2_out; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_out_pvld = chn1_en & chn2_en ? chn1_in_pvld & chn2_in_pvld : chn2_en ? chn2_in_pvld : chn1_en ? chn1_in_pvld : 1'b0; +assign chn1_in_prdy = chn1_en & chn2_en ? chn_out_prdy & chn2_in_pvld : chn2_en ? 1'b1 : chn_out_prdy ; +assign chn2_in_prdy = chn1_en & chn2_en ? chn_out_prdy & chn1_in_pvld : chn2_en ? chn_out_prdy : 1'b1 ; +assign data1_out[DATA1_WIDTH-1:0] = chn1_en ? data1_in[DATA1_WIDTH-1:0] : {DATA1_WIDTH{1'b0}}; +assign data2_out[DATA2_WIDTH-1:0] = chn2_en ? data2_in[DATA2_WIDTH-1:0] : {DATA2_WIDTH{1'b0}}; +endmodule // NV_NVDLA_SDP_HLS_sync2data diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_sync2data.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_sync2data.v.vcp new file mode 100644 index 0000000..5d618cd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_sync2data.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_sync2data.v +module NV_NVDLA_SDP_HLS_sync2data ( + chn1_en + ,chn1_in_pvld + ,chn2_en + ,chn2_in_pvld + ,chn_out_prdy + ,data1_in + ,data2_in + ,chn1_in_prdy + ,chn2_in_prdy + ,chn_out_pvld + ,data1_out + ,data2_out + ); +parameter DATA1_WIDTH = 32; +parameter DATA2_WIDTH = 32; +input chn1_en; +input chn2_en; +input chn1_in_pvld; +output chn1_in_prdy; +input chn2_in_pvld; +output chn2_in_prdy; +output chn_out_pvld; +input chn_out_prdy; +input [DATA1_WIDTH-1:0] data1_in; +input [DATA2_WIDTH-1:0] data2_in; +output [DATA1_WIDTH-1:0] data1_out; +output [DATA2_WIDTH-1:0] data2_out; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_out_pvld = chn1_en & chn2_en ? chn1_in_pvld & chn2_in_pvld : chn2_en ? chn2_in_pvld : chn1_en ? chn1_in_pvld : 1'b0; +assign chn1_in_prdy = chn1_en & chn2_en ? chn_out_prdy & chn2_in_pvld : chn2_en ? 1'b1 : chn_out_prdy ; +assign chn2_in_prdy = chn1_en & chn2_en ? chn_out_prdy & chn1_in_pvld : chn2_en ? chn_out_prdy : 1'b1 ; +assign data1_out[DATA1_WIDTH-1:0] = chn1_en ? data1_in[DATA1_WIDTH-1:0] : {DATA1_WIDTH{1'b0}}; +assign data2_out[DATA2_WIDTH-1:0] = chn2_en ? data2_in[DATA2_WIDTH-1:0] : {DATA2_WIDTH{1'b0}}; +endmodule // NV_NVDLA_SDP_HLS_sync2data diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x1_int.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x1_int.v new file mode 100644 index 0000000..ca43036 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x1_int.v @@ -0,0 +1,265 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_x1_int.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_x1_int ( + cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_shift_value //|< i + ,cfg_alu_src //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_shift_value //|< i + ,cfg_mul_src //|< i + ,cfg_relu_bypass //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_op_prdy //|> o + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,chn_out_pvld //|> o + ); +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [15:0] cfg_alu_op; +input [5:0] cfg_alu_shift_value; +input cfg_alu_src; +input cfg_mul_bypass; +input [15:0] cfg_mul_op; +input cfg_mul_prelu; +input [5:0] cfg_mul_shift_value; +input cfg_mul_src; +input cfg_relu_bypass; +input [16*1 -1:0] chn_alu_op; +input chn_alu_op_pvld; +input [32*1 -1:0] chn_data_in; +input chn_in_pvld; +input [16*1 -1:0] chn_mul_op; +input chn_mul_op_pvld; +input chn_out_prdy; +output chn_alu_op_prdy; +output [32*1 -1:0] chn_data_out; +output chn_in_prdy; +output chn_mul_op_prdy; +output chn_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [32:0] alu_data_out_${i}; +//: wire alu_out_prdy_${i}; +//: wire alu_out_pvld_${i}; +//: wire bypass_trt_out_${i}; +//: wire [15:0] chn_alu_op_${i}; +//: wire chn_alu_op_prdy_${i}; +//: wire [31:0] chn_data_in_${i}; +//: wire [31:0] chn_data_out_${i}; +//: wire chn_in_prdy_${i}; +//: wire [15:0] chn_mul_op_${i}; +//: wire chn_mul_op_prdy_${i}; +//: wire chn_out_pvld_${i}; +//: wire [48:0] mul_data_out_${i}; +//: wire mul_out_prdy_${i}; +//: wire mul_out_pvld_${i}; +//: wire [31:0] trt_data_out_${i}; +//: wire trt_out_prdy_${i}; +//: wire trt_out_pvld_${i}; +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [32:0] alu_data_out_0; +wire alu_out_prdy_0; +wire alu_out_pvld_0; +wire bypass_trt_out_0; +wire [15:0] chn_alu_op_0; +wire chn_alu_op_prdy_0; +wire [31:0] chn_data_in_0; +wire [31:0] chn_data_out_0; +wire chn_in_prdy_0; +wire [15:0] chn_mul_op_0; +wire chn_mul_op_prdy_0; +wire chn_out_pvld_0; +wire [48:0] mul_data_out_0; +wire mul_out_prdy_0; +wire mul_out_pvld_0; +wire [31:0] trt_data_out_0; +wire trt_out_prdy_0; +wire trt_out_pvld_0; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign chn_in_prdy = chn_in_prdy_0; +assign chn_alu_op_prdy = chn_alu_op_prdy_0; +assign chn_mul_op_prdy = chn_mul_op_prdy_0; +assign chn_out_pvld = chn_out_pvld_0; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}]; +//: assign chn_alu_op_${i} = chn_alu_op[16*${i}+15:16*${i}]; +//: assign chn_mul_op_${i} = chn_mul_op[16*${i}+15:16*${i}]; +//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i}; +//: +//: NV_NVDLA_SDP_HLS_X_int_alu u_sdp_x_alu_${i} ( +//: .alu_data_in (chn_data_in_${i}[31:0]) +//: ,.alu_in_pvld (chn_in_pvld) +//: ,.alu_op_pvld (chn_alu_op_pvld) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.cfg_alu_algo (cfg_alu_algo[1:0]) +//: ,.cfg_alu_bypass (cfg_alu_bypass) +//: ,.cfg_alu_op (cfg_alu_op[15:0]) +//: ,.cfg_alu_shift_value (cfg_alu_shift_value[5:0]) +//: ,.cfg_alu_src (cfg_alu_src) +//: ,.chn_alu_op (chn_alu_op_${i}[15:0]) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_in_prdy (chn_in_prdy_${i}) +//: ,.alu_op_prdy (chn_alu_op_prdy_${i}) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_mul u_sdp_x_mul_${i} ( +//: .alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ,.cfg_mul_bypass (cfg_mul_bypass) +//: ,.cfg_mul_op (cfg_mul_op[15:0]) +//: ,.cfg_mul_prelu (cfg_mul_prelu) +//: ,.cfg_mul_src (cfg_mul_src) +//: ,.chn_mul_op (chn_mul_op_${i}[15:0]) +//: ,.mul_op_pvld (chn_mul_op_pvld) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.bypass_trt_out (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_op_prdy (chn_mul_op_prdy_${i}) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_trt u_sdp_x_trt_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_mul_shift_value (cfg_mul_shift_value[5:0]) +//: ,.bypass_trt_in (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_relu u_sdp_x_relu_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_relu_bypass (cfg_relu_bypass) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.relu_data_out (chn_data_out_${i}[31:0]) +//: ,.relu_out_pvld (chn_out_pvld_${i}) +//: ,.relu_out_prdy (chn_out_prdy) +//: ); +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign chn_data_in_0= chn_data_in[32*0+31:32*0]; +assign chn_alu_op_0 = chn_alu_op[16*0+15:16*0]; +assign chn_mul_op_0 = chn_mul_op[16*0+15:16*0]; +assign chn_data_out[32*0+31:32*0] = chn_data_out_0; + +NV_NVDLA_SDP_HLS_X_int_alu u_sdp_x_alu_0 ( +.alu_data_in (chn_data_in_0[31:0]) +,.alu_in_pvld (chn_in_pvld) +,.alu_op_pvld (chn_alu_op_pvld) +,.alu_out_prdy (alu_out_prdy_0) +,.cfg_alu_algo (cfg_alu_algo[1:0]) +,.cfg_alu_bypass (cfg_alu_bypass) +,.cfg_alu_op (cfg_alu_op[15:0]) +,.cfg_alu_shift_value (cfg_alu_shift_value[5:0]) +,.cfg_alu_src (cfg_alu_src) +,.chn_alu_op (chn_alu_op_0[15:0]) +,.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.alu_data_out (alu_data_out_0[32:0]) +,.alu_in_prdy (chn_in_prdy_0) +,.alu_op_prdy (chn_alu_op_prdy_0) +,.alu_out_pvld (alu_out_pvld_0) +); + +NV_NVDLA_SDP_HLS_X_int_mul u_sdp_x_mul_0 ( +.alu_data_out (alu_data_out_0[32:0]) +,.alu_out_pvld (alu_out_pvld_0) +,.cfg_mul_bypass (cfg_mul_bypass) +,.cfg_mul_op (cfg_mul_op[15:0]) +,.cfg_mul_prelu (cfg_mul_prelu) +,.cfg_mul_src (cfg_mul_src) +,.chn_mul_op (chn_mul_op_0[15:0]) +,.mul_op_pvld (chn_mul_op_pvld) +,.mul_out_prdy (mul_out_prdy_0) +,.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.alu_out_prdy (alu_out_prdy_0) +,.bypass_trt_out (bypass_trt_out_0) +,.mul_data_out (mul_data_out_0[48:0]) +,.mul_op_prdy (chn_mul_op_prdy_0) +,.mul_out_pvld (mul_out_pvld_0) +); + +NV_NVDLA_SDP_HLS_X_int_trt u_sdp_x_trt_0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.cfg_mul_shift_value (cfg_mul_shift_value[5:0]) +,.bypass_trt_in (bypass_trt_out_0) +,.mul_data_out (mul_data_out_0[48:0]) +,.mul_out_pvld (mul_out_pvld_0) +,.mul_out_prdy (mul_out_prdy_0) +,.trt_data_out (trt_data_out_0[31:0]) +,.trt_out_pvld (trt_out_pvld_0) +,.trt_out_prdy (trt_out_prdy_0) +); + +NV_NVDLA_SDP_HLS_X_int_relu u_sdp_x_relu_0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.cfg_relu_bypass (cfg_relu_bypass) +,.trt_out_pvld (trt_out_pvld_0) +,.trt_out_prdy (trt_out_prdy_0) +,.trt_data_out (trt_data_out_0[31:0]) +,.relu_data_out (chn_data_out_0[31:0]) +,.relu_out_pvld (chn_out_pvld_0) +,.relu_out_prdy (chn_out_prdy) +); + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_HLS_x1_int diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x1_int.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x1_int.v.vcp new file mode 100644 index 0000000..29fd9ff --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x1_int.v.vcp @@ -0,0 +1,170 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_x1_int.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_x1_int ( + cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_shift_value //|< i + ,cfg_alu_src //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_shift_value //|< i + ,cfg_mul_src //|< i + ,cfg_relu_bypass //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_op_prdy //|> o + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,chn_out_pvld //|> o + ); +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [15:0] cfg_alu_op; +input [5:0] cfg_alu_shift_value; +input cfg_alu_src; +input cfg_mul_bypass; +input [15:0] cfg_mul_op; +input cfg_mul_prelu; +input [5:0] cfg_mul_shift_value; +input cfg_mul_src; +input cfg_relu_bypass; +input [16*1 -1:0] chn_alu_op; +input chn_alu_op_pvld; +input [32*1 -1:0] chn_data_in; +input chn_in_pvld; +input [16*1 -1:0] chn_mul_op; +input chn_mul_op_pvld; +input chn_out_prdy; +output chn_alu_op_prdy; +output [32*1 -1:0] chn_data_out; +output chn_in_prdy; +output chn_mul_op_prdy; +output chn_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [32:0] alu_data_out_${i}; +//: wire alu_out_prdy_${i}; +//: wire alu_out_pvld_${i}; +//: wire bypass_trt_out_${i}; +//: wire [15:0] chn_alu_op_${i}; +//: wire chn_alu_op_prdy_${i}; +//: wire [31:0] chn_data_in_${i}; +//: wire [31:0] chn_data_out_${i}; +//: wire chn_in_prdy_${i}; +//: wire [15:0] chn_mul_op_${i}; +//: wire chn_mul_op_prdy_${i}; +//: wire chn_out_pvld_${i}; +//: wire [48:0] mul_data_out_${i}; +//: wire mul_out_prdy_${i}; +//: wire mul_out_pvld_${i}; +//: wire [31:0] trt_data_out_${i}; +//: wire trt_out_prdy_${i}; +//: wire trt_out_pvld_${i}; +//: +//: ); +//: } +assign chn_in_prdy = chn_in_prdy_0; +assign chn_alu_op_prdy = chn_alu_op_prdy_0; +assign chn_mul_op_prdy = chn_mul_op_prdy_0; +assign chn_out_pvld = chn_out_pvld_0; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}]; +//: assign chn_alu_op_${i} = chn_alu_op[16*${i}+15:16*${i}]; +//: assign chn_mul_op_${i} = chn_mul_op[16*${i}+15:16*${i}]; +//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i}; +//: +//: NV_NVDLA_SDP_HLS_X_int_alu u_sdp_x_alu_${i} ( +//: .alu_data_in (chn_data_in_${i}[31:0]) +//: ,.alu_in_pvld (chn_in_pvld) +//: ,.alu_op_pvld (chn_alu_op_pvld) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.cfg_alu_algo (cfg_alu_algo[1:0]) +//: ,.cfg_alu_bypass (cfg_alu_bypass) +//: ,.cfg_alu_op (cfg_alu_op[15:0]) +//: ,.cfg_alu_shift_value (cfg_alu_shift_value[5:0]) +//: ,.cfg_alu_src (cfg_alu_src) +//: ,.chn_alu_op (chn_alu_op_${i}[15:0]) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_in_prdy (chn_in_prdy_${i}) +//: ,.alu_op_prdy (chn_alu_op_prdy_${i}) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_mul u_sdp_x_mul_${i} ( +//: .alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ,.cfg_mul_bypass (cfg_mul_bypass) +//: ,.cfg_mul_op (cfg_mul_op[15:0]) +//: ,.cfg_mul_prelu (cfg_mul_prelu) +//: ,.cfg_mul_src (cfg_mul_src) +//: ,.chn_mul_op (chn_mul_op_${i}[15:0]) +//: ,.mul_op_pvld (chn_mul_op_pvld) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.bypass_trt_out (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_op_prdy (chn_mul_op_prdy_${i}) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_trt u_sdp_x_trt_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_mul_shift_value (cfg_mul_shift_value[5:0]) +//: ,.bypass_trt_in (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_relu u_sdp_x_relu_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_relu_bypass (cfg_relu_bypass) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.relu_data_out (chn_data_out_${i}[31:0]) +//: ,.relu_out_pvld (chn_out_pvld_${i}) +//: ,.relu_out_prdy (chn_out_prdy) +//: ); +//: +//: ); +//: } +endmodule // NV_NVDLA_SDP_HLS_x1_int diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x2_int.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x2_int.v new file mode 100644 index 0000000..27b5db5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x2_int.v @@ -0,0 +1,265 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_x2_int.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_x2_int ( + cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_shift_value //|< i + ,cfg_alu_src //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_shift_value //|< i + ,cfg_mul_src //|< i + ,cfg_relu_bypass //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_op_prdy //|> o + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,chn_out_pvld //|> o + ); +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [15:0] cfg_alu_op; +input [5:0] cfg_alu_shift_value; +input cfg_alu_src; +input cfg_mul_bypass; +input [15:0] cfg_mul_op; +input cfg_mul_prelu; +input [5:0] cfg_mul_shift_value; +input cfg_mul_src; +input cfg_relu_bypass; +input [16*1 -1:0] chn_alu_op; +input chn_alu_op_pvld; +input [32*1 -1:0] chn_data_in; +input chn_in_pvld; +input [16*1 -1:0] chn_mul_op; +input chn_mul_op_pvld; +input chn_out_prdy; +output chn_alu_op_prdy; +output [32*1 -1:0] chn_data_out; +output chn_in_prdy; +output chn_mul_op_prdy; +output chn_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [32:0] alu_data_out_${i}; +//: wire alu_out_prdy_${i}; +//: wire alu_out_pvld_${i}; +//: wire bypass_trt_out_${i}; +//: wire [15:0] chn_alu_op_${i}; +//: wire chn_alu_op_prdy_${i}; +//: wire [31:0] chn_data_in_${i}; +//: wire [31:0] chn_data_out_${i}; +//: wire chn_in_prdy_${i}; +//: wire [15:0] chn_mul_op_${i}; +//: wire chn_mul_op_prdy_${i}; +//: wire chn_out_pvld_${i}; +//: wire [48:0] mul_data_out_${i}; +//: wire mul_out_prdy_${i}; +//: wire mul_out_pvld_${i}; +//: wire [31:0] trt_data_out_${i}; +//: wire trt_out_prdy_${i}; +//: wire trt_out_pvld_${i}; +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [32:0] alu_data_out_0; +wire alu_out_prdy_0; +wire alu_out_pvld_0; +wire bypass_trt_out_0; +wire [15:0] chn_alu_op_0; +wire chn_alu_op_prdy_0; +wire [31:0] chn_data_in_0; +wire [31:0] chn_data_out_0; +wire chn_in_prdy_0; +wire [15:0] chn_mul_op_0; +wire chn_mul_op_prdy_0; +wire chn_out_pvld_0; +wire [48:0] mul_data_out_0; +wire mul_out_prdy_0; +wire mul_out_pvld_0; +wire [31:0] trt_data_out_0; +wire trt_out_prdy_0; +wire trt_out_pvld_0; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +assign chn_in_prdy = chn_in_prdy_0; +assign chn_alu_op_prdy = chn_alu_op_prdy_0; +assign chn_mul_op_prdy = chn_mul_op_prdy_0; +assign chn_out_pvld = chn_out_pvld_0; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}]; +//: assign chn_alu_op_${i} = chn_alu_op[16*${i}+15:16*${i}]; +//: assign chn_mul_op_${i} = chn_mul_op[16*${i}+15:16*${i}]; +//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i}; +//: +//: NV_NVDLA_SDP_HLS_X_int_alu u_sdp_x_alu_${i} ( +//: .alu_data_in (chn_data_in_${i}[31:0]) +//: ,.alu_in_pvld (chn_in_pvld) +//: ,.alu_op_pvld (chn_alu_op_pvld) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.cfg_alu_algo (cfg_alu_algo[1:0]) +//: ,.cfg_alu_bypass (cfg_alu_bypass) +//: ,.cfg_alu_op (cfg_alu_op[15:0]) +//: ,.cfg_alu_shift_value (cfg_alu_shift_value[5:0]) +//: ,.cfg_alu_src (cfg_alu_src) +//: ,.chn_alu_op (chn_alu_op_${i}[15:0]) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_in_prdy (chn_in_prdy_${i}) +//: ,.alu_op_prdy (chn_alu_op_prdy_${i}) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_mul u_sdp_x_mul_${i} ( +//: .alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ,.cfg_mul_bypass (cfg_mul_bypass) +//: ,.cfg_mul_op (cfg_mul_op[15:0]) +//: ,.cfg_mul_prelu (cfg_mul_prelu) +//: ,.cfg_mul_src (cfg_mul_src) +//: ,.chn_mul_op (chn_mul_op_${i}[15:0]) +//: ,.mul_op_pvld (chn_mul_op_pvld) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.bypass_trt_out (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_op_prdy (chn_mul_op_prdy_${i}) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_trt u_sdp_x_trt_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_mul_shift_value (cfg_mul_shift_value[5:0]) +//: ,.bypass_trt_in (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_relu u_sdp_x_relu_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_relu_bypass (cfg_relu_bypass) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.relu_data_out (chn_data_out_${i}[31:0]) +//: ,.relu_out_pvld (chn_out_pvld_${i}) +//: ,.relu_out_prdy (chn_out_prdy) +//: ); +//: +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +assign chn_data_in_0= chn_data_in[32*0+31:32*0]; +assign chn_alu_op_0 = chn_alu_op[16*0+15:16*0]; +assign chn_mul_op_0 = chn_mul_op[16*0+15:16*0]; +assign chn_data_out[32*0+31:32*0] = chn_data_out_0; + +NV_NVDLA_SDP_HLS_X_int_alu u_sdp_x_alu_0 ( +.alu_data_in (chn_data_in_0[31:0]) +,.alu_in_pvld (chn_in_pvld) +,.alu_op_pvld (chn_alu_op_pvld) +,.alu_out_prdy (alu_out_prdy_0) +,.cfg_alu_algo (cfg_alu_algo[1:0]) +,.cfg_alu_bypass (cfg_alu_bypass) +,.cfg_alu_op (cfg_alu_op[15:0]) +,.cfg_alu_shift_value (cfg_alu_shift_value[5:0]) +,.cfg_alu_src (cfg_alu_src) +,.chn_alu_op (chn_alu_op_0[15:0]) +,.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.alu_data_out (alu_data_out_0[32:0]) +,.alu_in_prdy (chn_in_prdy_0) +,.alu_op_prdy (chn_alu_op_prdy_0) +,.alu_out_pvld (alu_out_pvld_0) +); + +NV_NVDLA_SDP_HLS_X_int_mul u_sdp_x_mul_0 ( +.alu_data_out (alu_data_out_0[32:0]) +,.alu_out_pvld (alu_out_pvld_0) +,.cfg_mul_bypass (cfg_mul_bypass) +,.cfg_mul_op (cfg_mul_op[15:0]) +,.cfg_mul_prelu (cfg_mul_prelu) +,.cfg_mul_src (cfg_mul_src) +,.chn_mul_op (chn_mul_op_0[15:0]) +,.mul_op_pvld (chn_mul_op_pvld) +,.mul_out_prdy (mul_out_prdy_0) +,.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.alu_out_prdy (alu_out_prdy_0) +,.bypass_trt_out (bypass_trt_out_0) +,.mul_data_out (mul_data_out_0[48:0]) +,.mul_op_prdy (chn_mul_op_prdy_0) +,.mul_out_pvld (mul_out_pvld_0) +); + +NV_NVDLA_SDP_HLS_X_int_trt u_sdp_x_trt_0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.cfg_mul_shift_value (cfg_mul_shift_value[5:0]) +,.bypass_trt_in (bypass_trt_out_0) +,.mul_data_out (mul_data_out_0[48:0]) +,.mul_out_pvld (mul_out_pvld_0) +,.mul_out_prdy (mul_out_prdy_0) +,.trt_data_out (trt_data_out_0[31:0]) +,.trt_out_pvld (trt_out_pvld_0) +,.trt_out_prdy (trt_out_prdy_0) +); + +NV_NVDLA_SDP_HLS_X_int_relu u_sdp_x_relu_0 ( +.nvdla_core_clk (nvdla_core_clk) +,.nvdla_core_rstn (nvdla_core_rstn) +,.cfg_relu_bypass (cfg_relu_bypass) +,.trt_out_pvld (trt_out_pvld_0) +,.trt_out_prdy (trt_out_prdy_0) +,.trt_data_out (trt_data_out_0[31:0]) +,.relu_data_out (chn_data_out_0[31:0]) +,.relu_out_pvld (chn_out_pvld_0) +,.relu_out_prdy (chn_out_prdy) +); + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_HLS_x2_int diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x2_int.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x2_int.v.vcp new file mode 100644 index 0000000..abf85b9 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_HLS_x2_int.v.vcp @@ -0,0 +1,170 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_HLS_x2_int.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_HLS_x2_int ( + cfg_alu_algo //|< i + ,cfg_alu_bypass //|< i + ,cfg_alu_op //|< i + ,cfg_alu_shift_value //|< i + ,cfg_alu_src //|< i + ,cfg_mul_bypass //|< i + ,cfg_mul_op //|< i + ,cfg_mul_prelu //|< i + ,cfg_mul_shift_value //|< i + ,cfg_mul_src //|< i + ,cfg_relu_bypass //|< i + ,chn_alu_op //|< i + ,chn_alu_op_pvld //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_mul_op //|< i + ,chn_mul_op_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_alu_op_prdy //|> o + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_mul_op_prdy //|> o + ,chn_out_pvld //|> o + ); +input [1:0] cfg_alu_algo; +input cfg_alu_bypass; +input [15:0] cfg_alu_op; +input [5:0] cfg_alu_shift_value; +input cfg_alu_src; +input cfg_mul_bypass; +input [15:0] cfg_mul_op; +input cfg_mul_prelu; +input [5:0] cfg_mul_shift_value; +input cfg_mul_src; +input cfg_relu_bypass; +input [16*1 -1:0] chn_alu_op; +input chn_alu_op_pvld; +input [32*1 -1:0] chn_data_in; +input chn_in_pvld; +input [16*1 -1:0] chn_mul_op; +input chn_mul_op_pvld; +input chn_out_prdy; +output chn_alu_op_prdy; +output [32*1 -1:0] chn_data_out; +output chn_in_prdy; +output chn_mul_op_prdy; +output chn_out_pvld; +input nvdla_core_clk; +input nvdla_core_rstn; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: wire [32:0] alu_data_out_${i}; +//: wire alu_out_prdy_${i}; +//: wire alu_out_pvld_${i}; +//: wire bypass_trt_out_${i}; +//: wire [15:0] chn_alu_op_${i}; +//: wire chn_alu_op_prdy_${i}; +//: wire [31:0] chn_data_in_${i}; +//: wire [31:0] chn_data_out_${i}; +//: wire chn_in_prdy_${i}; +//: wire [15:0] chn_mul_op_${i}; +//: wire chn_mul_op_prdy_${i}; +//: wire chn_out_pvld_${i}; +//: wire [48:0] mul_data_out_${i}; +//: wire mul_out_prdy_${i}; +//: wire mul_out_pvld_${i}; +//: wire [31:0] trt_data_out_${i}; +//: wire trt_out_prdy_${i}; +//: wire trt_out_pvld_${i}; +//: +//: ); +//: } +assign chn_in_prdy = chn_in_prdy_0; +assign chn_alu_op_prdy = chn_alu_op_prdy_0; +assign chn_mul_op_prdy = chn_mul_op_prdy_0; +assign chn_out_pvld = chn_out_pvld_0; +//: my $k=1; +//: foreach my $i (0..${k}-1) { +//: print qq( +//: assign chn_data_in_${i}= chn_data_in[32*${i}+31:32*${i}]; +//: assign chn_alu_op_${i} = chn_alu_op[16*${i}+15:16*${i}]; +//: assign chn_mul_op_${i} = chn_mul_op[16*${i}+15:16*${i}]; +//: assign chn_data_out[32*${i}+31:32*${i}] = chn_data_out_${i}; +//: +//: NV_NVDLA_SDP_HLS_X_int_alu u_sdp_x_alu_${i} ( +//: .alu_data_in (chn_data_in_${i}[31:0]) +//: ,.alu_in_pvld (chn_in_pvld) +//: ,.alu_op_pvld (chn_alu_op_pvld) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.cfg_alu_algo (cfg_alu_algo[1:0]) +//: ,.cfg_alu_bypass (cfg_alu_bypass) +//: ,.cfg_alu_op (cfg_alu_op[15:0]) +//: ,.cfg_alu_shift_value (cfg_alu_shift_value[5:0]) +//: ,.cfg_alu_src (cfg_alu_src) +//: ,.chn_alu_op (chn_alu_op_${i}[15:0]) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_in_prdy (chn_in_prdy_${i}) +//: ,.alu_op_prdy (chn_alu_op_prdy_${i}) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_mul u_sdp_x_mul_${i} ( +//: .alu_data_out (alu_data_out_${i}[32:0]) +//: ,.alu_out_pvld (alu_out_pvld_${i}) +//: ,.cfg_mul_bypass (cfg_mul_bypass) +//: ,.cfg_mul_op (cfg_mul_op[15:0]) +//: ,.cfg_mul_prelu (cfg_mul_prelu) +//: ,.cfg_mul_src (cfg_mul_src) +//: ,.chn_mul_op (chn_mul_op_${i}[15:0]) +//: ,.mul_op_pvld (chn_mul_op_pvld) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.alu_out_prdy (alu_out_prdy_${i}) +//: ,.bypass_trt_out (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_op_prdy (chn_mul_op_prdy_${i}) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_trt u_sdp_x_trt_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_mul_shift_value (cfg_mul_shift_value[5:0]) +//: ,.bypass_trt_in (bypass_trt_out_${i}) +//: ,.mul_data_out (mul_data_out_${i}[48:0]) +//: ,.mul_out_pvld (mul_out_pvld_${i}) +//: ,.mul_out_prdy (mul_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ); +//: +//: NV_NVDLA_SDP_HLS_X_int_relu u_sdp_x_relu_${i} ( +//: .nvdla_core_clk (nvdla_core_clk) +//: ,.nvdla_core_rstn (nvdla_core_rstn) +//: ,.cfg_relu_bypass (cfg_relu_bypass) +//: ,.trt_out_pvld (trt_out_pvld_${i}) +//: ,.trt_out_prdy (trt_out_prdy_${i}) +//: ,.trt_data_out (trt_data_out_${i}[31:0]) +//: ,.relu_data_out (chn_data_out_${i}[31:0]) +//: ,.relu_out_pvld (chn_out_pvld_${i}) +//: ,.relu_out_prdy (chn_out_prdy) +//: ); +//: +//: ); +//: } +endmodule // NV_NVDLA_SDP_HLS_x2_int diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v new file mode 100644 index 0000000..6ce284e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v @@ -0,0 +1,1314 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_EG_cmd.v +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_cmd ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,eg_done //|< i + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,cq2eg_prdy //|> o + ,cmd2dat_dma_pd //|> o + ,cmd2dat_dma_pvld //|> o + ,cmd2dat_dma_prdy //|< i + ,cmd2dat_spt_pd //|> o + ,cmd2dat_spt_pvld //|> o + ,cmd2dat_spt_prdy //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ); +// +// NV_NVDLA_SDP_MRDMA_EG_cmd_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input eg_done; +input cq2eg_pvld; +output cq2eg_prdy; +input [13:0] cq2eg_pd; +output cmd2dat_spt_pvld; +input cmd2dat_spt_prdy; +output [12:0] cmd2dat_spt_pd; +output cmd2dat_dma_pvld; +input cmd2dat_dma_prdy; +output [14:0] cmd2dat_dma_pd; +input [12:0] reg2dp_height; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +wire cfg_di_int16; +wire cfg_do_int8; +wire cfg_do_16; +wire cfg_do_fp16; +wire cfg_do_int16; +wire cfg_mode_1x1_pack; +reg cmd_vld; +wire cmd_rdy; +reg cmd_cube_end; +reg [13:0] cmd_dma_size; +reg [12:0] cmd_spt_size; +wire dma_cube_end; +wire [14:0] dma_fifo_pd; +wire dma_fifo_prdy; +wire dma_fifo_pvld; +wire [13:0] dma_size; +reg [13:0] ig2eg_dma_size; +wire cq2eg_accept; +wire ig2eg_cube_end; +wire [12:0] ig2eg_size; +wire [12:0] ig2eg_spt_size; +wire [12:0] spt_fifo_pd; +wire spt_fifo_prdy; +wire spt_fifo_pvld; +wire [12:0] spt_size; +//============== +// CFG +assign cfg_di_int16 = reg2dp_in_precision == 1 ; +assign cfg_do_int8 = reg2dp_proc_precision == 0 ; +assign cfg_do_int16 = reg2dp_proc_precision == 1 ; +assign cfg_do_fp16 = reg2dp_proc_precision == 2 ; +assign cfg_do_16 = cfg_do_int16 | cfg_do_fp16; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign ig2eg_size[12:0] = cq2eg_pd[12:0]; +assign ig2eg_cube_end = cq2eg_pd[13]; +assign cq2eg_prdy = !cmd_vld || cmd_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_vld <= 1'b0; + end else begin + if ((cq2eg_prdy) == 1'b1) begin + cmd_vld <= cq2eg_pvld; +//end else if ((cq2eg_prdy) == 1'b0) begin +//end else begin +// cmd_vld <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign cq2eg_accept = cq2eg_pvld & cq2eg_prdy; +//dma_size is in unit of atomic_m * 1B +assign ig2eg_spt_size[12:0] = ig2eg_size; //ig2eg_size[12:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_spt_size <= {13{1'b0}}; + end else begin + if ((cq2eg_accept) == 1'b1) begin + cmd_spt_size <= ig2eg_spt_size; +//end else if ((cq2eg_accept) == 1'b0) begin +//end else begin +// cmd_spt_size <= 13'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//dma_size is in unit of 16B +always @( ig2eg_size ) begin + ig2eg_dma_size = {1'b0,ig2eg_size}; //fixme +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_dma_size <= {14{1'b0}}; + end else begin + if ((cq2eg_accept) == 1'b1) begin + cmd_dma_size <= ig2eg_dma_size; +//end else if ((cq2eg_accept) == 1'b0) begin +//end else begin +// cmd_dma_size <= 14'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_cube_end <= 1'b0; + end else begin + if ((cq2eg_accept) == 1'b1) begin + cmd_cube_end <= ig2eg_cube_end; +//end else if ((cq2eg_accept) == 1'b0) begin +//end else begin +// cmd_cube_end <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +wire dma_req_en = 1'b1; +assign spt_size = cmd_spt_size; +assign dma_size = cmd_dma_size; +assign dma_cube_end = cmd_cube_end; +//============== +// OUTPUT PACK and PIPE: To EG_DAT +//============== +assign spt_fifo_pd[12:0] = spt_size[12:0]; +assign dma_fifo_pd[13:0] = dma_size[13:0]; +assign dma_fifo_pd[14] = dma_cube_end ; +assign spt_fifo_pvld = cmd_vld & dma_fifo_prdy; +assign dma_fifo_pvld = cmd_vld & dma_req_en & spt_fifo_prdy; +assign cmd_rdy = spt_fifo_prdy & dma_fifo_prdy; +NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo u_sfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.spt_fifo_prdy (spt_fifo_prdy) + ,.spt_fifo_pvld (spt_fifo_pvld) + ,.spt_fifo_pd (spt_fifo_pd[12:0]) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +//fixme +NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dma_fifo_prdy (dma_fifo_prdy) + ,.dma_fifo_pvld (dma_fifo_pvld) + ,.dma_fifo_pd (dma_fifo_pd[14:0]) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +endmodule // NV_NVDLA_SDP_MRDMA_EG_cmd +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo ( + nvdla_core_clk + , nvdla_core_rstn + , spt_fifo_prdy + , spt_fifo_pvld + , spt_fifo_pd + , cmd2dat_spt_prdy + , cmd2dat_spt_pvld + , cmd2dat_spt_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output spt_fifo_prdy; +input spt_fifo_pvld; +input [12:0] spt_fifo_pd; +input cmd2dat_spt_prdy; +output cmd2dat_spt_pvld; +output [12:0] cmd2dat_spt_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg spt_fifo_busy_int; // copy for internal use +assign spt_fifo_prdy = !spt_fifo_busy_int; +assign wr_reserving = spt_fifo_pvld && !spt_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] spt_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? spt_fifo_count : (spt_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (spt_fifo_count + 1'd1) : spt_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire spt_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check spt_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_busy_int <= 1'b0; + spt_fifo_count <= 3'd0; + end else begin + spt_fifo_busy_int <= spt_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + spt_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + spt_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as spt_fifo_pvld +// +// RAM +// +reg [1:0] spt_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + spt_fifo_adr <= spt_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_spt_adr; // read address this cycle +wire ram_we = wr_pushing && (spt_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [12:0] cmd2dat_spt_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( spt_fifo_pd ) + , .we ( ram_we ) + , .wa ( spt_fifo_adr ) + , .ra ( (spt_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_spt_adr} ) + , .dout ( cmd2dat_spt_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_spt_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_spt_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_spt_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_spt_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_spt_pvld && cmd2dat_spt_prdy; +reg [2:0] cmd2dat_spt_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_spt_count : + (cmd2dat_spt_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_spt_count + 1'd1) : + cmd2dat_spt_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_spt_pvld = cmd2dat_spt_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_spt_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_spt_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (spt_fifo_pvld && !spt_fifo_busy_int) || (spt_fifo_busy_int != spt_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_spt_pvld && cmd2dat_spt_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, spt_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [12:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [12:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [12:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [12:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [12:0] ram_ff0; +reg [12:0] ram_ff1; +reg [12:0] ram_ff2; +reg [12:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [12:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {13{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [12:0] Di0; +input [1:0] Ra0; +output [12:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 13'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [12:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [12:0] Q0 = mem[0]; +wire [12:0] Q1 = mem[1]; +wire [12:0] Q2 = mem[2]; +wire [12:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13] } +endmodule // vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +//vmw: Memory vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +//vmw: Address-size 2 +//vmw: Data-size 13 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[12:0] data0[12:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[12:0] data1[12:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dma_fifo_prdy + , dma_fifo_pvld + , dma_fifo_pd + , cmd2dat_dma_prdy + , cmd2dat_dma_pvld + , cmd2dat_dma_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dma_fifo_prdy; +input dma_fifo_pvld; +input [14:0] dma_fifo_pd; +input cmd2dat_dma_prdy; +output cmd2dat_dma_pvld; +output [14:0] cmd2dat_dma_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dma_fifo_busy_int; // copy for internal use +assign dma_fifo_prdy = !dma_fifo_busy_int; +assign wr_reserving = dma_fifo_pvld && !dma_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dma_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dma_fifo_count : (dma_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dma_fifo_count + 1'd1) : dma_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dma_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dma_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_busy_int <= 1'b0; + dma_fifo_count <= 3'd0; + end else begin + dma_fifo_busy_int <= dma_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dma_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dma_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dma_fifo_pvld +// +// RAM +// +reg [1:0] dma_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dma_fifo_adr <= dma_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_dma_adr; // read address this cycle +wire ram_we = wr_pushing && (dma_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [14:0] cmd2dat_dma_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dma_fifo_pd ) + , .we ( ram_we ) + , .wa ( dma_fifo_adr ) + , .ra ( (dma_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_dma_adr} ) + , .dout ( cmd2dat_dma_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_dma_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_dma_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_dma_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_dma_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_dma_pvld && cmd2dat_dma_prdy; +reg [2:0] cmd2dat_dma_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_dma_count : + (cmd2dat_dma_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_dma_count + 1'd1) : + cmd2dat_dma_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_dma_pvld = cmd2dat_dma_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_dma_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_dma_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dma_fifo_pvld && !dma_fifo_busy_int) || (dma_fifo_busy_int != dma_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_dma_pvld && cmd2dat_dma_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dma_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [14:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [14:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [14:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [14:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [14:0] ram_ff0; +reg [14:0] ram_ff1; +reg [14:0] ram_ff2; +reg [14:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [14:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {15{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [14:0] Di0; +input [1:0] Ra0; +output [14:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 15'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [14:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [14:0] Q0 = mem[0]; +wire [14:0] Q1 = mem[1]; +wire [14:0] Q2 = mem[2]; +wire [14:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15] } +endmodule // vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +//vmw: Memory vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +//vmw: Address-size 2 +//vmw: Data-size 15 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[14:0] data0[14:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[14:0] data1[14:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v.vcp new file mode 100644 index 0000000..6ce284e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v.vcp @@ -0,0 +1,1314 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_EG_cmd.v +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_cmd ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,eg_done //|< i + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,cq2eg_prdy //|> o + ,cmd2dat_dma_pd //|> o + ,cmd2dat_dma_pvld //|> o + ,cmd2dat_dma_prdy //|< i + ,cmd2dat_spt_pd //|> o + ,cmd2dat_spt_pvld //|> o + ,cmd2dat_spt_prdy //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ); +// +// NV_NVDLA_SDP_MRDMA_EG_cmd_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input eg_done; +input cq2eg_pvld; +output cq2eg_prdy; +input [13:0] cq2eg_pd; +output cmd2dat_spt_pvld; +input cmd2dat_spt_prdy; +output [12:0] cmd2dat_spt_pd; +output cmd2dat_dma_pvld; +input cmd2dat_dma_prdy; +output [14:0] cmd2dat_dma_pd; +input [12:0] reg2dp_height; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +wire cfg_di_int16; +wire cfg_do_int8; +wire cfg_do_16; +wire cfg_do_fp16; +wire cfg_do_int16; +wire cfg_mode_1x1_pack; +reg cmd_vld; +wire cmd_rdy; +reg cmd_cube_end; +reg [13:0] cmd_dma_size; +reg [12:0] cmd_spt_size; +wire dma_cube_end; +wire [14:0] dma_fifo_pd; +wire dma_fifo_prdy; +wire dma_fifo_pvld; +wire [13:0] dma_size; +reg [13:0] ig2eg_dma_size; +wire cq2eg_accept; +wire ig2eg_cube_end; +wire [12:0] ig2eg_size; +wire [12:0] ig2eg_spt_size; +wire [12:0] spt_fifo_pd; +wire spt_fifo_prdy; +wire spt_fifo_pvld; +wire [12:0] spt_size; +//============== +// CFG +assign cfg_di_int16 = reg2dp_in_precision == 1 ; +assign cfg_do_int8 = reg2dp_proc_precision == 0 ; +assign cfg_do_int16 = reg2dp_proc_precision == 1 ; +assign cfg_do_fp16 = reg2dp_proc_precision == 2 ; +assign cfg_do_16 = cfg_do_int16 | cfg_do_fp16; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign ig2eg_size[12:0] = cq2eg_pd[12:0]; +assign ig2eg_cube_end = cq2eg_pd[13]; +assign cq2eg_prdy = !cmd_vld || cmd_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_vld <= 1'b0; + end else begin + if ((cq2eg_prdy) == 1'b1) begin + cmd_vld <= cq2eg_pvld; +//end else if ((cq2eg_prdy) == 1'b0) begin +//end else begin +// cmd_vld <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign cq2eg_accept = cq2eg_pvld & cq2eg_prdy; +//dma_size is in unit of atomic_m * 1B +assign ig2eg_spt_size[12:0] = ig2eg_size; //ig2eg_size[12:1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_spt_size <= {13{1'b0}}; + end else begin + if ((cq2eg_accept) == 1'b1) begin + cmd_spt_size <= ig2eg_spt_size; +//end else if ((cq2eg_accept) == 1'b0) begin +//end else begin +// cmd_spt_size <= 13'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//dma_size is in unit of 16B +always @( ig2eg_size ) begin + ig2eg_dma_size = {1'b0,ig2eg_size}; //fixme +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_dma_size <= {14{1'b0}}; + end else begin + if ((cq2eg_accept) == 1'b1) begin + cmd_dma_size <= ig2eg_dma_size; +//end else if ((cq2eg_accept) == 1'b0) begin +//end else begin +// cmd_dma_size <= 14'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_cube_end <= 1'b0; + end else begin + if ((cq2eg_accept) == 1'b1) begin + cmd_cube_end <= ig2eg_cube_end; +//end else if ((cq2eg_accept) == 1'b0) begin +//end else begin +// cmd_cube_end <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cq2eg_accept))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +wire dma_req_en = 1'b1; +assign spt_size = cmd_spt_size; +assign dma_size = cmd_dma_size; +assign dma_cube_end = cmd_cube_end; +//============== +// OUTPUT PACK and PIPE: To EG_DAT +//============== +assign spt_fifo_pd[12:0] = spt_size[12:0]; +assign dma_fifo_pd[13:0] = dma_size[13:0]; +assign dma_fifo_pd[14] = dma_cube_end ; +assign spt_fifo_pvld = cmd_vld & dma_fifo_prdy; +assign dma_fifo_pvld = cmd_vld & dma_req_en & spt_fifo_prdy; +assign cmd_rdy = spt_fifo_prdy & dma_fifo_prdy; +NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo u_sfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.spt_fifo_prdy (spt_fifo_prdy) + ,.spt_fifo_pvld (spt_fifo_pvld) + ,.spt_fifo_pd (spt_fifo_pd[12:0]) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +//fixme +NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dma_fifo_prdy (dma_fifo_prdy) + ,.dma_fifo_pvld (dma_fifo_pvld) + ,.dma_fifo_pd (dma_fifo_pd[14:0]) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +endmodule // NV_NVDLA_SDP_MRDMA_EG_cmd +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo ( + nvdla_core_clk + , nvdla_core_rstn + , spt_fifo_prdy + , spt_fifo_pvld + , spt_fifo_pd + , cmd2dat_spt_prdy + , cmd2dat_spt_pvld + , cmd2dat_spt_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output spt_fifo_prdy; +input spt_fifo_pvld; +input [12:0] spt_fifo_pd; +input cmd2dat_spt_prdy; +output cmd2dat_spt_pvld; +output [12:0] cmd2dat_spt_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg spt_fifo_busy_int; // copy for internal use +assign spt_fifo_prdy = !spt_fifo_busy_int; +assign wr_reserving = spt_fifo_pvld && !spt_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] spt_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? spt_fifo_count : (spt_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (spt_fifo_count + 1'd1) : spt_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire spt_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check spt_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_busy_int <= 1'b0; + spt_fifo_count <= 3'd0; + end else begin + spt_fifo_busy_int <= spt_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + spt_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + spt_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as spt_fifo_pvld +// +// RAM +// +reg [1:0] spt_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + spt_fifo_adr <= spt_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_spt_adr; // read address this cycle +wire ram_we = wr_pushing && (spt_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [12:0] cmd2dat_spt_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( spt_fifo_pd ) + , .we ( ram_we ) + , .wa ( spt_fifo_adr ) + , .ra ( (spt_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_spt_adr} ) + , .dout ( cmd2dat_spt_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_spt_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_spt_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_spt_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_spt_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_spt_pvld && cmd2dat_spt_prdy; +reg [2:0] cmd2dat_spt_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_spt_count : + (cmd2dat_spt_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_spt_count + 1'd1) : + cmd2dat_spt_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_spt_pvld = cmd2dat_spt_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_spt_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_spt_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (spt_fifo_pvld && !spt_fifo_busy_int) || (spt_fifo_busy_int != spt_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_spt_pvld && cmd2dat_spt_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, spt_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [12:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [12:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [12:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [12:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [12:0] ram_ff0; +reg [12:0] ram_ff1; +reg [12:0] ram_ff2; +reg [12:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [12:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {13{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [12:0] Di0; +input [1:0] Ra0; +output [12:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 13'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [12:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [12:0] Q0 = mem[0]; +wire [12:0] Q1 = mem[1]; +wire [12:0] Q2 = mem[2]; +wire [12:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13] } +endmodule // vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +//vmw: Memory vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +//vmw: Address-size 2 +//vmw: Data-size 13 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[12:0] data0[12:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[12:0] data1[12:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_sfifo_flopram_rwsa_4x13 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dma_fifo_prdy + , dma_fifo_pvld + , dma_fifo_pd + , cmd2dat_dma_prdy + , cmd2dat_dma_pvld + , cmd2dat_dma_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dma_fifo_prdy; +input dma_fifo_pvld; +input [14:0] dma_fifo_pd; +input cmd2dat_dma_prdy; +output cmd2dat_dma_pvld; +output [14:0] cmd2dat_dma_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dma_fifo_busy_int; // copy for internal use +assign dma_fifo_prdy = !dma_fifo_busy_int; +assign wr_reserving = dma_fifo_pvld && !dma_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dma_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dma_fifo_count : (dma_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dma_fifo_count + 1'd1) : dma_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dma_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dma_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_busy_int <= 1'b0; + dma_fifo_count <= 3'd0; + end else begin + dma_fifo_busy_int <= dma_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dma_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dma_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dma_fifo_pvld +// +// RAM +// +reg [1:0] dma_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dma_fifo_adr <= dma_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_dma_adr; // read address this cycle +wire ram_we = wr_pushing && (dma_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [14:0] cmd2dat_dma_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dma_fifo_pd ) + , .we ( ram_we ) + , .wa ( dma_fifo_adr ) + , .ra ( (dma_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_dma_adr} ) + , .dout ( cmd2dat_dma_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_dma_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_dma_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_dma_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_dma_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_dma_pvld && cmd2dat_dma_prdy; +reg [2:0] cmd2dat_dma_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_dma_count : + (cmd2dat_dma_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_dma_count + 1'd1) : + cmd2dat_dma_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_dma_pvld = cmd2dat_dma_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_dma_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_dma_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dma_fifo_pvld && !dma_fifo_busy_int) || (dma_fifo_busy_int != dma_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_dma_pvld && cmd2dat_dma_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dma_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [14:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [14:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [14:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [14:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [14:0] ram_ff0; +reg [14:0] ram_ff1; +reg [14:0] ram_ff2; +reg [14:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [14:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {15{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [14:0] Di0; +input [1:0] Ra0; +output [14:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 15'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [14:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [14:0] Q0 = mem[0]; +wire [14:0] Q1 = mem[1]; +wire [14:0] Q2 = mem[2]; +wire [14:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15] } +endmodule // vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +//vmw: Memory vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +//vmw: Address-size 2 +//vmw: Data-size 15 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[14:0] data0[14:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[14:0] data1[14:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_MRDMA_EG_CMD_dfifo_flopram_rwsa_4x15 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v new file mode 100644 index 0000000..38f3921 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v @@ -0,0 +1,904 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_EG_din.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_MRDMA_EG_din ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_src_ram_type //|< i + ,cmd2dat_spt_prdy //|> o + ,cmd2dat_spt_pd //|< i + ,cmd2dat_spt_pvld //|< i + ,dma_rd_cdt_lat_fifo_pop //|> o + ,dma_rd_rsp_ram_type //|> o + ,dma_rd_rsp_pd //|< i + ,dma_rd_rsp_vld //|< i + ,dma_rd_rsp_rdy //|> o + ,pfifo0_rd_prdy //|< i + ,pfifo1_rd_prdy //|< i + ,pfifo2_rd_prdy //|< i + ,pfifo3_rd_prdy //|< i + ,pfifo0_rd_pd //|> o + ,pfifo0_rd_pvld //|> o + ,pfifo1_rd_pd //|> o + ,pfifo1_rd_pvld //|> o + ,pfifo2_rd_pd //|> o + ,pfifo2_rd_pvld //|> o + ,pfifo3_rd_pd //|> o + ,pfifo3_rd_pvld //|> o + ); +//&Catenate "NV_NVDLA_SDP_MRDMA_EG_din_ports.v"; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input reg2dp_src_ram_type; +output dma_rd_rsp_ram_type; +input [65 -1:0] dma_rd_rsp_pd; +input dma_rd_rsp_vld; +output dma_rd_rsp_rdy; +output dma_rd_cdt_lat_fifo_pop; +input [12:0] cmd2dat_spt_pd; +input cmd2dat_spt_pvld; +output cmd2dat_spt_prdy; +input pfifo0_rd_prdy; +input pfifo1_rd_prdy; +input pfifo2_rd_prdy; +input pfifo3_rd_prdy; +output [8*8 -1:0] pfifo0_rd_pd; +output pfifo0_rd_pvld; +output [8*8 -1:0] pfifo1_rd_pd; +output pfifo1_rd_pvld; +output [8*8 -1:0] pfifo2_rd_pd; +output pfifo2_rd_pvld; +output [8*8 -1:0] pfifo3_rd_pd; +output pfifo3_rd_pvld; +wire cmd2dat_spt_primary; +wire [12:0] cmd2dat_spt_size; +wire [13:0] cmd_size; +wire is_last_beat; +reg [12:0] beat_cnt; +wire [13:0] beat_cnt_nxt; +reg mon_beat_cnt; +wire lat_ecc_rd_accept; +wire [64 -1:0] lat_ecc_rd_data; +wire [3:0] lat_ecc_rd_mask; +wire [65 -1:0] lat_ecc_rd_pd; +wire lat_ecc_rd_pvld; +wire lat_ecc_rd_prdy; +wire [8*8 -1:0] pfifo0_wr_pd; +wire pfifo0_wr_prdy; +wire pfifo0_wr_pvld; +wire [8*8 -1:0] pfifo1_wr_pd; +wire pfifo1_wr_prdy; +wire pfifo1_wr_pvld; +wire [8*8 -1:0] pfifo2_wr_pd; +wire pfifo2_wr_prdy; +wire pfifo2_wr_pvld; +wire [8*8 -1:0] pfifo3_wr_pd; +wire pfifo3_wr_prdy; +wire pfifo3_wr_pvld; +wire [4*8*8 +3:0] unpack_out_pd; +wire unpack_out_pvld; +wire unpack_out_prdy; +wire pfifo_wr_rdy; +wire pfifo_wr_vld; +wire [3:0] pfifo_wr_mask; +//============== +// Latency FIFO to buffer return DATA +//============== +assign dma_rd_rsp_ram_type = reg2dp_src_ram_type; +assign dma_rd_cdt_lat_fifo_pop = lat_ecc_rd_pvld & lat_ecc_rd_prdy; +NV_NVDLA_SDP_MRDMA_EG_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_ecc_rd_prdy) + ,.lat_rd_pvld (lat_ecc_rd_pvld) + ,.lat_rd_pd (lat_ecc_rd_pd[65 -1:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +assign lat_ecc_rd_accept = lat_ecc_rd_pvld & lat_ecc_rd_prdy; +assign lat_ecc_rd_data[64 -1:0] = lat_ecc_rd_pd[64 -1:0]; +assign lat_ecc_rd_mask[3:0] = {{(4-1){1'b0}},lat_ecc_rd_pd[65 -1:64]}; +wire [2:0] lat_ecc_rd_size = lat_ecc_rd_mask[3]+lat_ecc_rd_mask[2]+lat_ecc_rd_mask[1]+lat_ecc_rd_mask[0]; +//========command for pfifo wr ==================== +assign cmd2dat_spt_prdy = lat_ecc_rd_accept & is_last_beat; +assign cmd2dat_spt_size[12:0] = cmd2dat_spt_pd[12:0]; +//assign cmd2dat_spt_primary = cmd2dat_spt_pd[12]; +assign cmd_size = cmd2dat_spt_pvld ? (cmd2dat_spt_size+1) : 0; +assign beat_cnt_nxt = beat_cnt + lat_ecc_rd_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_cnt,beat_cnt} <= 14'h0; + end else begin + if (lat_ecc_rd_accept) begin + if (is_last_beat) begin + {mon_beat_cnt,beat_cnt} <= 14'h0; + end else begin + {mon_beat_cnt,beat_cnt} <= beat_cnt_nxt; + end + end + end +end +assign is_last_beat = beat_cnt_nxt == cmd_size; +/////////combine lat fifo pd to 4*atomic_m*bpe////// +wire lat_ecc_rd_beat_end = is_last_beat; +NV_NVDLA_SDP_RDMA_unpack u_rdma_unpack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.inp_data (lat_ecc_rd_pd[65 -1:0]) + ,.inp_pvld (lat_ecc_rd_pvld) + ,.inp_prdy (lat_ecc_rd_prdy) + ,.inp_end (lat_ecc_rd_beat_end) + ,.out_data (unpack_out_pd[4*8*8 +3:0]) + ,.out_pvld (unpack_out_pvld) + ,.out_prdy (unpack_out_prdy) + ); +assign unpack_out_prdy = pfifo_wr_rdy; +assign pfifo_wr_mask = unpack_out_pd[4*8*8 +3:4*8*8]; +assign pfifo_wr_vld = unpack_out_pvld; +//================================== +// FIFO WRITE +assign pfifo0_wr_pd = unpack_out_pd[8*8*0+8*8 -1:8*8*0]; +assign pfifo1_wr_pd = unpack_out_pd[8*8*1+8*8 -1:8*8*1]; +assign pfifo2_wr_pd = unpack_out_pd[8*8*2+8*8 -1:8*8*2]; +assign pfifo3_wr_pd = unpack_out_pd[8*8*3+8*8 -1:8*8*3]; +assign pfifo_wr_rdy = ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy |pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo0_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[0] & ~(pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo1_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[1] & ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo2_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[2] & ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy | pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo3_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[3] & ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy | pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy ); +//================================== +// FIFO INSTANCE +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo0 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo0_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo0_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo0_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo0_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo0_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo0_rd_pd[8*8 -1:0]) //|> o + ); +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo1_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo1_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo1_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo1_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo1_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo1_rd_pd[8*8 -1:0]) //|> o + ); +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo2_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo2_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo2_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo2_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo2_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo2_rd_pd[8*8 -1:0]) //|> o + ); +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo3_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo3_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo3_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo3_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo3_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo3_rd_pd[8*8 -1:0]) //|> o + ); +endmodule // NV_NVDLA_SDP_MRDMA_EG_din +module NV_NVDLA_SDP_MRDMA_EG_pfifo ( + nvdla_core_clk + , nvdla_core_rstn + , pfifo_wr_prdy + , pfifo_wr_pvld + , pfifo_wr_pd + , pfifo_rd_prdy + , pfifo_rd_pvld + , pfifo_rd_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output pfifo_wr_prdy; +input pfifo_wr_pvld; +input [8*8 -1:0] pfifo_wr_pd; +input pfifo_rd_prdy; +output pfifo_rd_pvld; +output [8*8 -1:0] pfifo_rd_pd; +//: my $dw = 8*8; +//: &eperl::pipe("-is -wid $dw -do pfifo_rd_pd -vo pfifo_rd_pvld -ri pfifo_rd_prdy -di pfifo_wr_pd -vi pfifo_wr_pvld -ro pfifo_wr_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg pfifo_wr_prdy; +reg skid_flop_pfifo_wr_prdy; +reg skid_flop_pfifo_wr_pvld; +reg [64-1:0] skid_flop_pfifo_wr_pd; +reg pipe_skid_pfifo_wr_pvld; +reg [64-1:0] pipe_skid_pfifo_wr_pd; +// Wire +wire skid_pfifo_wr_pvld; +wire [64-1:0] skid_pfifo_wr_pd; +wire skid_pfifo_wr_prdy; +wire pipe_skid_pfifo_wr_prdy; +wire pfifo_rd_pvld; +wire [64-1:0] pfifo_rd_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pfifo_wr_prdy <= 1'b1; + skid_flop_pfifo_wr_prdy <= 1'b1; + end else begin + pfifo_wr_prdy <= skid_pfifo_wr_prdy; + skid_flop_pfifo_wr_prdy <= skid_pfifo_wr_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_pfifo_wr_pvld <= 1'b0; + end else begin + if (skid_flop_pfifo_wr_prdy) begin + skid_flop_pfifo_wr_pvld <= pfifo_wr_pvld; + end + end +end +assign skid_pfifo_wr_pvld = (skid_flop_pfifo_wr_prdy) ? pfifo_wr_pvld : skid_flop_pfifo_wr_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_pfifo_wr_prdy & pfifo_wr_pvld) begin + skid_flop_pfifo_wr_pd[64-1:0] <= pfifo_wr_pd[64-1:0]; + end +end +assign skid_pfifo_wr_pd[64-1:0] = (skid_flop_pfifo_wr_prdy) ? pfifo_wr_pd[64-1:0] : skid_flop_pfifo_wr_pd[64-1:0]; + + +// PIPE READY +assign skid_pfifo_wr_prdy = pipe_skid_pfifo_wr_prdy || !pipe_skid_pfifo_wr_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_pfifo_wr_pvld <= 1'b0; + end else begin + if (skid_pfifo_wr_prdy) begin + pipe_skid_pfifo_wr_pvld <= skid_pfifo_wr_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_pfifo_wr_prdy && skid_pfifo_wr_pvld) begin + pipe_skid_pfifo_wr_pd[64-1:0] <= skid_pfifo_wr_pd[64-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_pfifo_wr_prdy = pfifo_rd_prdy; +assign pfifo_rd_pvld = pipe_skid_pfifo_wr_pvld; +assign pfifo_rd_pd = pipe_skid_pfifo_wr_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_MRDMA_EG_pfifo +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] lat_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 7'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [6:0] lat_wr_adr; // current write address +wire [6:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (lat_wr_adr == 7'd79) ? 7'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] lat_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (lat_rd_adr == 7'd79) ? 7'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [6:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 7'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_EG_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_MRDMA_EG_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v.vcp new file mode 100644 index 0000000..dc82bd6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v.vcp @@ -0,0 +1,828 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_EG_din.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_MRDMA_EG_din ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_src_ram_type //|< i + ,cmd2dat_spt_prdy //|> o + ,cmd2dat_spt_pd //|< i + ,cmd2dat_spt_pvld //|< i + ,dma_rd_cdt_lat_fifo_pop //|> o + ,dma_rd_rsp_ram_type //|> o + ,dma_rd_rsp_pd //|< i + ,dma_rd_rsp_vld //|< i + ,dma_rd_rsp_rdy //|> o + ,pfifo0_rd_prdy //|< i + ,pfifo1_rd_prdy //|< i + ,pfifo2_rd_prdy //|< i + ,pfifo3_rd_prdy //|< i + ,pfifo0_rd_pd //|> o + ,pfifo0_rd_pvld //|> o + ,pfifo1_rd_pd //|> o + ,pfifo1_rd_pvld //|> o + ,pfifo2_rd_pd //|> o + ,pfifo2_rd_pvld //|> o + ,pfifo3_rd_pd //|> o + ,pfifo3_rd_pvld //|> o + ); +//&Catenate "NV_NVDLA_SDP_MRDMA_EG_din_ports.v"; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input reg2dp_src_ram_type; +output dma_rd_rsp_ram_type; +input [65 -1:0] dma_rd_rsp_pd; +input dma_rd_rsp_vld; +output dma_rd_rsp_rdy; +output dma_rd_cdt_lat_fifo_pop; +input [12:0] cmd2dat_spt_pd; +input cmd2dat_spt_pvld; +output cmd2dat_spt_prdy; +input pfifo0_rd_prdy; +input pfifo1_rd_prdy; +input pfifo2_rd_prdy; +input pfifo3_rd_prdy; +output [8*8 -1:0] pfifo0_rd_pd; +output pfifo0_rd_pvld; +output [8*8 -1:0] pfifo1_rd_pd; +output pfifo1_rd_pvld; +output [8*8 -1:0] pfifo2_rd_pd; +output pfifo2_rd_pvld; +output [8*8 -1:0] pfifo3_rd_pd; +output pfifo3_rd_pvld; +wire cmd2dat_spt_primary; +wire [12:0] cmd2dat_spt_size; +wire [13:0] cmd_size; +wire is_last_beat; +reg [12:0] beat_cnt; +wire [13:0] beat_cnt_nxt; +reg mon_beat_cnt; +wire lat_ecc_rd_accept; +wire [64 -1:0] lat_ecc_rd_data; +wire [3:0] lat_ecc_rd_mask; +wire [65 -1:0] lat_ecc_rd_pd; +wire lat_ecc_rd_pvld; +wire lat_ecc_rd_prdy; +wire [8*8 -1:0] pfifo0_wr_pd; +wire pfifo0_wr_prdy; +wire pfifo0_wr_pvld; +wire [8*8 -1:0] pfifo1_wr_pd; +wire pfifo1_wr_prdy; +wire pfifo1_wr_pvld; +wire [8*8 -1:0] pfifo2_wr_pd; +wire pfifo2_wr_prdy; +wire pfifo2_wr_pvld; +wire [8*8 -1:0] pfifo3_wr_pd; +wire pfifo3_wr_prdy; +wire pfifo3_wr_pvld; +wire [4*8*8 +3:0] unpack_out_pd; +wire unpack_out_pvld; +wire unpack_out_prdy; +wire pfifo_wr_rdy; +wire pfifo_wr_vld; +wire [3:0] pfifo_wr_mask; +//============== +// Latency FIFO to buffer return DATA +//============== +assign dma_rd_rsp_ram_type = reg2dp_src_ram_type; +assign dma_rd_cdt_lat_fifo_pop = lat_ecc_rd_pvld & lat_ecc_rd_prdy; +NV_NVDLA_SDP_MRDMA_EG_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_ecc_rd_prdy) + ,.lat_rd_pvld (lat_ecc_rd_pvld) + ,.lat_rd_pd (lat_ecc_rd_pd[65 -1:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +assign lat_ecc_rd_accept = lat_ecc_rd_pvld & lat_ecc_rd_prdy; +assign lat_ecc_rd_data[64 -1:0] = lat_ecc_rd_pd[64 -1:0]; +assign lat_ecc_rd_mask[3:0] = {{(4-1){1'b0}},lat_ecc_rd_pd[65 -1:64]}; +wire [2:0] lat_ecc_rd_size = lat_ecc_rd_mask[3]+lat_ecc_rd_mask[2]+lat_ecc_rd_mask[1]+lat_ecc_rd_mask[0]; +//========command for pfifo wr ==================== +assign cmd2dat_spt_prdy = lat_ecc_rd_accept & is_last_beat; +assign cmd2dat_spt_size[12:0] = cmd2dat_spt_pd[12:0]; +//assign cmd2dat_spt_primary = cmd2dat_spt_pd[12]; +assign cmd_size = cmd2dat_spt_pvld ? (cmd2dat_spt_size+1) : 0; +assign beat_cnt_nxt = beat_cnt + lat_ecc_rd_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_cnt,beat_cnt} <= 14'h0; + end else begin + if (lat_ecc_rd_accept) begin + if (is_last_beat) begin + {mon_beat_cnt,beat_cnt} <= 14'h0; + end else begin + {mon_beat_cnt,beat_cnt} <= beat_cnt_nxt; + end + end + end +end +assign is_last_beat = beat_cnt_nxt == cmd_size; +/////////combine lat fifo pd to 4*atomic_m*bpe////// +wire lat_ecc_rd_beat_end = is_last_beat; +NV_NVDLA_SDP_RDMA_unpack u_rdma_unpack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.inp_data (lat_ecc_rd_pd[65 -1:0]) + ,.inp_pvld (lat_ecc_rd_pvld) + ,.inp_prdy (lat_ecc_rd_prdy) + ,.inp_end (lat_ecc_rd_beat_end) + ,.out_data (unpack_out_pd[4*8*8 +3:0]) + ,.out_pvld (unpack_out_pvld) + ,.out_prdy (unpack_out_prdy) + ); +assign unpack_out_prdy = pfifo_wr_rdy; +assign pfifo_wr_mask = unpack_out_pd[4*8*8 +3:4*8*8]; +assign pfifo_wr_vld = unpack_out_pvld; +//================================== +// FIFO WRITE +assign pfifo0_wr_pd = unpack_out_pd[8*8*0+8*8 -1:8*8*0]; +assign pfifo1_wr_pd = unpack_out_pd[8*8*1+8*8 -1:8*8*1]; +assign pfifo2_wr_pd = unpack_out_pd[8*8*2+8*8 -1:8*8*2]; +assign pfifo3_wr_pd = unpack_out_pd[8*8*3+8*8 -1:8*8*3]; +assign pfifo_wr_rdy = ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy |pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo0_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[0] & ~(pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo1_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[1] & ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo2_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[2] & ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy | pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[3] & ~pfifo3_wr_prdy ); +assign pfifo3_wr_pvld = pfifo_wr_vld & pfifo_wr_mask[3] & ~(pfifo_wr_mask[0] & ~pfifo0_wr_prdy | pfifo_wr_mask[1] & ~pfifo1_wr_prdy | pfifo_wr_mask[2] & ~pfifo2_wr_prdy ); +//================================== +// FIFO INSTANCE +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo0 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo0_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo0_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo0_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo0_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo0_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo0_rd_pd[8*8 -1:0]) //|> o + ); +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo1_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo1_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo1_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo1_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo1_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo1_rd_pd[8*8 -1:0]) //|> o + ); +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo2_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo2_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo2_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo2_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo2_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo2_rd_pd[8*8 -1:0]) //|> o + ); +NV_NVDLA_SDP_MRDMA_EG_pfifo u_pfifo3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pfifo_wr_prdy (pfifo3_wr_prdy) //|> w + ,.pfifo_wr_pvld (pfifo3_wr_pvld) //|< w + ,.pfifo_wr_pd (pfifo3_wr_pd[8*8 -1:0]) //|< w + ,.pfifo_rd_prdy (pfifo3_rd_prdy) //|< i + ,.pfifo_rd_pvld (pfifo3_rd_pvld) //|> o + ,.pfifo_rd_pd (pfifo3_rd_pd[8*8 -1:0]) //|> o + ); +endmodule // NV_NVDLA_SDP_MRDMA_EG_din +module NV_NVDLA_SDP_MRDMA_EG_pfifo ( + nvdla_core_clk + , nvdla_core_rstn + , pfifo_wr_prdy + , pfifo_wr_pvld + , pfifo_wr_pd + , pfifo_rd_prdy + , pfifo_rd_pvld + , pfifo_rd_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output pfifo_wr_prdy; +input pfifo_wr_pvld; +input [8*8 -1:0] pfifo_wr_pd; +input pfifo_rd_prdy; +output pfifo_rd_pvld; +output [8*8 -1:0] pfifo_rd_pd; +//: my $dw = 8*8; +//: &eperl::pipe("-is -wid $dw -do pfifo_rd_pd -vo pfifo_rd_pvld -ri pfifo_rd_prdy -di pfifo_wr_pd -vi pfifo_wr_pvld -ro pfifo_wr_prdy"); +endmodule // NV_NVDLA_SDP_MRDMA_EG_pfifo +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_EG_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] lat_wr_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 7'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [6:0] lat_wr_adr; // current write address +wire [6:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (lat_wr_adr == 7'd79) ? 7'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] lat_rd_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (lat_rd_adr == 7'd79) ? 7'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [6:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 7'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_MRDMA_EG_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst0(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst1(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_EG_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed0; +reg prand_initialized0; +reg prand_no_rollpli0; +`endif +`endif +`endif +function [31:0] prand_inst0; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst0 = min; +`else +`ifdef SYNTHESIS + prand_inst0 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized0 !== 1'b1) begin + prand_no_rollpli0 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli0) + prand_local_seed0 = {$prand_get_seed(0), 16'b0}; + prand_initialized0 = 1'b1; + end + if (prand_no_rollpli0) begin + prand_inst0 = min; + end else begin + diff = max - min + 1; + prand_inst0 = min + prand_local_seed0[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed0 = prand_local_seed0 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst0 = min; +`else + prand_inst0 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed1; +reg prand_initialized1; +reg prand_no_rollpli1; +`endif +`endif +`endif +function [31:0] prand_inst1; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst1 = min; +`else +`ifdef SYNTHESIS + prand_inst1 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized1 !== 1'b1) begin + prand_no_rollpli1 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli1) + prand_local_seed1 = {$prand_get_seed(1), 16'b0}; + prand_initialized1 = 1'b1; + end + if (prand_no_rollpli1) begin + prand_inst1 = min; + end else begin + diff = max - min + 1; + prand_inst1 = min + prand_local_seed1[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed1 = prand_local_seed1 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst1 = min; +`else + prand_inst1 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_MRDMA_EG_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v new file mode 100644 index 0000000..2267133 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v @@ -0,0 +1,675 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_EG_dout.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_MRDMA_EG_dout ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,op_load //|< i + ,eg_done //|> o + ,cmd2dat_dma_pd //|< i + ,cmd2dat_dma_pvld //|< i + ,cmd2dat_dma_prdy //|> o + ,pfifo0_rd_pd //|< i + ,pfifo0_rd_pvld //|< i + ,pfifo1_rd_pd //|< i + ,pfifo1_rd_pvld //|< i + ,pfifo2_rd_pd //|< i + ,pfifo2_rd_pvld //|< i + ,pfifo3_rd_pd //|< i + ,pfifo3_rd_pvld //|< i + ,pfifo0_rd_prdy //|> o + ,pfifo1_rd_prdy //|> o + ,pfifo2_rd_prdy //|> o + ,pfifo3_rd_prdy //|> o + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_perf_nan_inf_count_en //|< i + ,dp2reg_status_inf_input_num //|> o + ,dp2reg_status_nan_input_num //|> o + ); +// +// NV_NVDLA_SDP_MRDMA_EG_dout_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +output eg_done; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input reg2dp_perf_nan_inf_count_en; +output [31:0] dp2reg_status_inf_input_num; +output [31:0] dp2reg_status_nan_input_num; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +input cmd2dat_dma_pvld; +output cmd2dat_dma_prdy; +input [14:0] cmd2dat_dma_pd; +input pfifo0_rd_pvld; +output pfifo0_rd_prdy; +input [8*8 -1:0] pfifo0_rd_pd; +input pfifo1_rd_pvld; +output pfifo1_rd_prdy; +input [8*8 -1:0] pfifo1_rd_pd; +input pfifo2_rd_pvld; +output pfifo2_rd_prdy; +input [8*8 -1:0] pfifo2_rd_pd; +input pfifo3_rd_pvld; +output pfifo3_rd_prdy; +input [8*8 -1:0] pfifo3_rd_pd; +reg eg_done; +wire cfg_di_16; +wire cfg_di_fp16; +wire cfg_di_int16; +wire cfg_di_int8; +wire cfg_do_int8; +wire cfg_mode_1x1_pack; +wire cfg_perf_nan_inf_count_en; +wire [13:0] size_of_beat; +reg [13:0] beat_cnt; +wire is_last_beat; +wire cmd2dat_dma_cube_end; +wire [13:0] cmd2dat_dma_size; +wire cmd_cube_end; +wire dat_accept; +wire dat_batch_end; +wire [32*8 -1:0] dat_data; +wire dat_layer_end; +wire [32*8 +1:0] dat_pd; +wire dat_rdy; +wire dat_vld; +wire fifo_vld; +wire pfifo0_sel; +wire pfifo1_sel; +wire pfifo2_sel; +wire pfifo3_sel; +wire [8*8 -1:0] pfifo0_rd_data; +wire [8*8 -1:0] pfifo1_rd_data; +wire [8*8 -1:0] pfifo2_rd_data; +wire [8*8 -1:0] pfifo3_rd_data; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [15:0] pfifo${j}_data_byte${i}_16; \n"; +//: } +//: } +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [31:0] pfifo${j}_data_ext_byte${i}_int16; \n"; +//: print "wire [31:0] pfifo${j}_data_ext_byte${i}_16; \n"; +//: } +//: } +//: my $k = 8; +//: my $dw = $k * 8 -1; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [7:0] pfifo${j}_data_byte${i}_8; \n"; +//: } +//: } +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [31:0] pfifo${j}_data_ext_byte${i}_8; \n"; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +wire [15:0] pfifo0_data_byte0_16; +wire [15:0] pfifo0_data_byte1_16; +wire [15:0] pfifo0_data_byte2_16; +wire [15:0] pfifo0_data_byte3_16; +wire [15:0] pfifo1_data_byte0_16; +wire [15:0] pfifo1_data_byte1_16; +wire [15:0] pfifo1_data_byte2_16; +wire [15:0] pfifo1_data_byte3_16; +wire [15:0] pfifo2_data_byte0_16; +wire [15:0] pfifo2_data_byte1_16; +wire [15:0] pfifo2_data_byte2_16; +wire [15:0] pfifo2_data_byte3_16; +wire [15:0] pfifo3_data_byte0_16; +wire [15:0] pfifo3_data_byte1_16; +wire [15:0] pfifo3_data_byte2_16; +wire [15:0] pfifo3_data_byte3_16; +wire [31:0] pfifo0_data_ext_byte0_int16; +wire [31:0] pfifo0_data_ext_byte0_16; +wire [31:0] pfifo0_data_ext_byte1_int16; +wire [31:0] pfifo0_data_ext_byte1_16; +wire [31:0] pfifo0_data_ext_byte2_int16; +wire [31:0] pfifo0_data_ext_byte2_16; +wire [31:0] pfifo0_data_ext_byte3_int16; +wire [31:0] pfifo0_data_ext_byte3_16; +wire [31:0] pfifo1_data_ext_byte0_int16; +wire [31:0] pfifo1_data_ext_byte0_16; +wire [31:0] pfifo1_data_ext_byte1_int16; +wire [31:0] pfifo1_data_ext_byte1_16; +wire [31:0] pfifo1_data_ext_byte2_int16; +wire [31:0] pfifo1_data_ext_byte2_16; +wire [31:0] pfifo1_data_ext_byte3_int16; +wire [31:0] pfifo1_data_ext_byte3_16; +wire [31:0] pfifo2_data_ext_byte0_int16; +wire [31:0] pfifo2_data_ext_byte0_16; +wire [31:0] pfifo2_data_ext_byte1_int16; +wire [31:0] pfifo2_data_ext_byte1_16; +wire [31:0] pfifo2_data_ext_byte2_int16; +wire [31:0] pfifo2_data_ext_byte2_16; +wire [31:0] pfifo2_data_ext_byte3_int16; +wire [31:0] pfifo2_data_ext_byte3_16; +wire [31:0] pfifo3_data_ext_byte0_int16; +wire [31:0] pfifo3_data_ext_byte0_16; +wire [31:0] pfifo3_data_ext_byte1_int16; +wire [31:0] pfifo3_data_ext_byte1_16; +wire [31:0] pfifo3_data_ext_byte2_int16; +wire [31:0] pfifo3_data_ext_byte2_16; +wire [31:0] pfifo3_data_ext_byte3_int16; +wire [31:0] pfifo3_data_ext_byte3_16; +wire [7:0] pfifo0_data_byte0_8; +wire [7:0] pfifo0_data_byte1_8; +wire [7:0] pfifo0_data_byte2_8; +wire [7:0] pfifo0_data_byte3_8; +wire [7:0] pfifo0_data_byte4_8; +wire [7:0] pfifo0_data_byte5_8; +wire [7:0] pfifo0_data_byte6_8; +wire [7:0] pfifo0_data_byte7_8; +wire [7:0] pfifo1_data_byte0_8; +wire [7:0] pfifo1_data_byte1_8; +wire [7:0] pfifo1_data_byte2_8; +wire [7:0] pfifo1_data_byte3_8; +wire [7:0] pfifo1_data_byte4_8; +wire [7:0] pfifo1_data_byte5_8; +wire [7:0] pfifo1_data_byte6_8; +wire [7:0] pfifo1_data_byte7_8; +wire [7:0] pfifo2_data_byte0_8; +wire [7:0] pfifo2_data_byte1_8; +wire [7:0] pfifo2_data_byte2_8; +wire [7:0] pfifo2_data_byte3_8; +wire [7:0] pfifo2_data_byte4_8; +wire [7:0] pfifo2_data_byte5_8; +wire [7:0] pfifo2_data_byte6_8; +wire [7:0] pfifo2_data_byte7_8; +wire [7:0] pfifo3_data_byte0_8; +wire [7:0] pfifo3_data_byte1_8; +wire [7:0] pfifo3_data_byte2_8; +wire [7:0] pfifo3_data_byte3_8; +wire [7:0] pfifo3_data_byte4_8; +wire [7:0] pfifo3_data_byte5_8; +wire [7:0] pfifo3_data_byte6_8; +wire [7:0] pfifo3_data_byte7_8; +wire [31:0] pfifo0_data_ext_byte0_8; +wire [31:0] pfifo0_data_ext_byte1_8; +wire [31:0] pfifo0_data_ext_byte2_8; +wire [31:0] pfifo0_data_ext_byte3_8; +wire [31:0] pfifo0_data_ext_byte4_8; +wire [31:0] pfifo0_data_ext_byte5_8; +wire [31:0] pfifo0_data_ext_byte6_8; +wire [31:0] pfifo0_data_ext_byte7_8; +wire [31:0] pfifo1_data_ext_byte0_8; +wire [31:0] pfifo1_data_ext_byte1_8; +wire [31:0] pfifo1_data_ext_byte2_8; +wire [31:0] pfifo1_data_ext_byte3_8; +wire [31:0] pfifo1_data_ext_byte4_8; +wire [31:0] pfifo1_data_ext_byte5_8; +wire [31:0] pfifo1_data_ext_byte6_8; +wire [31:0] pfifo1_data_ext_byte7_8; +wire [31:0] pfifo2_data_ext_byte0_8; +wire [31:0] pfifo2_data_ext_byte1_8; +wire [31:0] pfifo2_data_ext_byte2_8; +wire [31:0] pfifo2_data_ext_byte3_8; +wire [31:0] pfifo2_data_ext_byte4_8; +wire [31:0] pfifo2_data_ext_byte5_8; +wire [31:0] pfifo2_data_ext_byte6_8; +wire [31:0] pfifo2_data_ext_byte7_8; +wire [31:0] pfifo3_data_ext_byte0_8; +wire [31:0] pfifo3_data_ext_byte1_8; +wire [31:0] pfifo3_data_ext_byte2_8; +wire [31:0] pfifo3_data_ext_byte3_8; +wire [31:0] pfifo3_data_ext_byte4_8; +wire [31:0] pfifo3_data_ext_byte5_8; +wire [31:0] pfifo3_data_ext_byte6_8; +wire [31:0] pfifo3_data_ext_byte7_8; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [32*8 -1:0] pfifo_data0_16; +wire [32*8 -1:0] pfifo_data1_16; +wire [32*8 -1:0] pfifo_data2_16; +wire [32*8 -1:0] pfifo_data3_16; +wire [32*8 -1:0] pfifo_data0_8; +wire [32*8 -1:0] pfifo_data1_8; +wire [32*8 -1:0] pfifo_data2_8; +wire [32*8 -1:0] pfifo_data3_8; +reg [32*8 -1:0] pfifo_data_r; +wire [32*8 -1:0] pfifo_data; +wire pfifo_sel; +wire pfifo_vld; +wire sdp_mrdma2cmux_layer_end; +//============== +// CFG +//============== +assign cfg_di_int8 = reg2dp_in_precision == 0 ; +assign cfg_di_int16 = reg2dp_in_precision == 1 ; +assign cfg_di_fp16 = reg2dp_in_precision == 2 ; +assign cfg_di_16 = cfg_di_int16 | cfg_di_fp16; +assign cfg_do_int8 = reg2dp_proc_precision == 0 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_perf_nan_inf_count_en = reg2dp_perf_nan_inf_count_en; +//pop command dat fifo // +assign cmd2dat_dma_prdy = dat_accept & is_last_beat & fifo_vld & dat_rdy; +assign cmd2dat_dma_size[13:0] = cmd2dat_dma_pd[13:0]; +assign cmd2dat_dma_cube_end = cmd2dat_dma_pd[14]; +assign size_of_beat = {14 {cmd2dat_dma_pvld}} & cmd2dat_dma_size; +assign cmd_cube_end = {1 {cmd2dat_dma_pvld}} & cmd2dat_dma_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_cnt <= {14{1'b0}}; + end else begin + if (dat_accept) begin + if (is_last_beat) begin + beat_cnt <= 0; + end else begin + beat_cnt <= beat_cnt + 1; + end + end + end +end +assign is_last_beat = (beat_cnt==size_of_beat); +assign pfifo0_sel = beat_cnt[1:0]==0; +assign pfifo1_sel = beat_cnt[1:0]==1; +assign pfifo2_sel = beat_cnt[1:0]==2; +assign pfifo3_sel = beat_cnt[1:0]==3; +assign pfifo_vld = (pfifo3_rd_pvld & pfifo3_sel) | (pfifo2_rd_pvld & pfifo2_sel) | (pfifo1_rd_pvld & pfifo1_sel) | (pfifo0_rd_pvld & pfifo0_sel); +assign fifo_vld = pfifo_vld; +assign dat_vld = fifo_vld; //& cmd2dat_dma_pvld; +assign pfifo0_rd_prdy = dat_rdy & pfifo0_sel; //& cmd2dat_dma_pvld; +assign pfifo1_rd_prdy = dat_rdy & pfifo1_sel; //& cmd2dat_dma_pvld; +assign pfifo2_rd_prdy = dat_rdy & pfifo2_sel; //& cmd2dat_dma_pvld; +assign pfifo3_rd_prdy = dat_rdy & pfifo3_sel; //& cmd2dat_dma_pvld; +assign pfifo0_rd_data = {8*8{pfifo0_sel}} & pfifo0_rd_pd; +assign pfifo1_rd_data = {8*8{pfifo1_sel}} & pfifo1_rd_pd; +assign pfifo2_rd_data = {8*8{pfifo2_sel}} & pfifo2_rd_pd; +assign pfifo3_rd_data = {8*8{pfifo3_sel}} & pfifo3_rd_pd; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_byte${i}_16 = pfifo${j}_rd_data[${i}*16+15:${i}*16]; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_ext_byte${i}_int16 = {{16{pfifo${j}_data_byte${i}_16[15]}}, pfifo${j}_data_byte${i}_16[15:0]}; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_ext_byte${i}_16 = pfifo${j}_data_ext_byte${i}_int16; \n"; +//: } +//: } +//: print "\n"; +//: my $k = 8/2; +//: my $remain = $k*32; +//: foreach my $j (0..3) { +//: print "assign pfifo_data${j}_16 = {${remain}\'h0,"; +//: foreach my $i (0..${k}-2) { +//: my $ii = $k - $i -1; +//: print "pfifo${j}_data_ext_byte${ii}_16,"; +//: } +//: print "pfifo${j}_data_ext_byte0_16}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign pfifo0_data_byte0_16 = pfifo0_rd_data[0*16+15:0*16]; +assign pfifo0_data_byte1_16 = pfifo0_rd_data[1*16+15:1*16]; +assign pfifo0_data_byte2_16 = pfifo0_rd_data[2*16+15:2*16]; +assign pfifo0_data_byte3_16 = pfifo0_rd_data[3*16+15:3*16]; + +assign pfifo1_data_byte0_16 = pfifo1_rd_data[0*16+15:0*16]; +assign pfifo1_data_byte1_16 = pfifo1_rd_data[1*16+15:1*16]; +assign pfifo1_data_byte2_16 = pfifo1_rd_data[2*16+15:2*16]; +assign pfifo1_data_byte3_16 = pfifo1_rd_data[3*16+15:3*16]; + +assign pfifo2_data_byte0_16 = pfifo2_rd_data[0*16+15:0*16]; +assign pfifo2_data_byte1_16 = pfifo2_rd_data[1*16+15:1*16]; +assign pfifo2_data_byte2_16 = pfifo2_rd_data[2*16+15:2*16]; +assign pfifo2_data_byte3_16 = pfifo2_rd_data[3*16+15:3*16]; + +assign pfifo3_data_byte0_16 = pfifo3_rd_data[0*16+15:0*16]; +assign pfifo3_data_byte1_16 = pfifo3_rd_data[1*16+15:1*16]; +assign pfifo3_data_byte2_16 = pfifo3_rd_data[2*16+15:2*16]; +assign pfifo3_data_byte3_16 = pfifo3_rd_data[3*16+15:3*16]; + + +assign pfifo0_data_ext_byte0_int16 = {{16{pfifo0_data_byte0_16[15]}}, pfifo0_data_byte0_16[15:0]}; +assign pfifo0_data_ext_byte1_int16 = {{16{pfifo0_data_byte1_16[15]}}, pfifo0_data_byte1_16[15:0]}; +assign pfifo0_data_ext_byte2_int16 = {{16{pfifo0_data_byte2_16[15]}}, pfifo0_data_byte2_16[15:0]}; +assign pfifo0_data_ext_byte3_int16 = {{16{pfifo0_data_byte3_16[15]}}, pfifo0_data_byte3_16[15:0]}; + +assign pfifo1_data_ext_byte0_int16 = {{16{pfifo1_data_byte0_16[15]}}, pfifo1_data_byte0_16[15:0]}; +assign pfifo1_data_ext_byte1_int16 = {{16{pfifo1_data_byte1_16[15]}}, pfifo1_data_byte1_16[15:0]}; +assign pfifo1_data_ext_byte2_int16 = {{16{pfifo1_data_byte2_16[15]}}, pfifo1_data_byte2_16[15:0]}; +assign pfifo1_data_ext_byte3_int16 = {{16{pfifo1_data_byte3_16[15]}}, pfifo1_data_byte3_16[15:0]}; + +assign pfifo2_data_ext_byte0_int16 = {{16{pfifo2_data_byte0_16[15]}}, pfifo2_data_byte0_16[15:0]}; +assign pfifo2_data_ext_byte1_int16 = {{16{pfifo2_data_byte1_16[15]}}, pfifo2_data_byte1_16[15:0]}; +assign pfifo2_data_ext_byte2_int16 = {{16{pfifo2_data_byte2_16[15]}}, pfifo2_data_byte2_16[15:0]}; +assign pfifo2_data_ext_byte3_int16 = {{16{pfifo2_data_byte3_16[15]}}, pfifo2_data_byte3_16[15:0]}; + +assign pfifo3_data_ext_byte0_int16 = {{16{pfifo3_data_byte0_16[15]}}, pfifo3_data_byte0_16[15:0]}; +assign pfifo3_data_ext_byte1_int16 = {{16{pfifo3_data_byte1_16[15]}}, pfifo3_data_byte1_16[15:0]}; +assign pfifo3_data_ext_byte2_int16 = {{16{pfifo3_data_byte2_16[15]}}, pfifo3_data_byte2_16[15:0]}; +assign pfifo3_data_ext_byte3_int16 = {{16{pfifo3_data_byte3_16[15]}}, pfifo3_data_byte3_16[15:0]}; + + +assign pfifo0_data_ext_byte0_16 = pfifo0_data_ext_byte0_int16; +assign pfifo0_data_ext_byte1_16 = pfifo0_data_ext_byte1_int16; +assign pfifo0_data_ext_byte2_16 = pfifo0_data_ext_byte2_int16; +assign pfifo0_data_ext_byte3_16 = pfifo0_data_ext_byte3_int16; +assign pfifo1_data_ext_byte0_16 = pfifo1_data_ext_byte0_int16; +assign pfifo1_data_ext_byte1_16 = pfifo1_data_ext_byte1_int16; +assign pfifo1_data_ext_byte2_16 = pfifo1_data_ext_byte2_int16; +assign pfifo1_data_ext_byte3_16 = pfifo1_data_ext_byte3_int16; +assign pfifo2_data_ext_byte0_16 = pfifo2_data_ext_byte0_int16; +assign pfifo2_data_ext_byte1_16 = pfifo2_data_ext_byte1_int16; +assign pfifo2_data_ext_byte2_16 = pfifo2_data_ext_byte2_int16; +assign pfifo2_data_ext_byte3_16 = pfifo2_data_ext_byte3_int16; +assign pfifo3_data_ext_byte0_16 = pfifo3_data_ext_byte0_int16; +assign pfifo3_data_ext_byte1_16 = pfifo3_data_ext_byte1_int16; +assign pfifo3_data_ext_byte2_16 = pfifo3_data_ext_byte2_int16; +assign pfifo3_data_ext_byte3_16 = pfifo3_data_ext_byte3_int16; + +assign pfifo_data0_16 = {128'h0,pfifo0_data_ext_byte3_16,pfifo0_data_ext_byte2_16,pfifo0_data_ext_byte1_16,pfifo0_data_ext_byte0_16}; +assign pfifo_data1_16 = {128'h0,pfifo1_data_ext_byte3_16,pfifo1_data_ext_byte2_16,pfifo1_data_ext_byte1_16,pfifo1_data_ext_byte0_16}; +assign pfifo_data2_16 = {128'h0,pfifo2_data_ext_byte3_16,pfifo2_data_ext_byte2_16,pfifo2_data_ext_byte1_16,pfifo2_data_ext_byte0_16}; +assign pfifo_data3_16 = {128'h0,pfifo3_data_ext_byte3_16,pfifo3_data_ext_byte2_16,pfifo3_data_ext_byte1_16,pfifo3_data_ext_byte0_16}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//// int8 /////////// +//: my $k = 8; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_byte${i}_8 = pfifo${j}_rd_data[${i}*8+7:${i}*8]; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//: my $k = 8; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_ext_byte${i}_8 = {{24{pfifo${j}_data_byte${i}_8[7]}}, pfifo${j}_data_byte${i}_8[7:0]}; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign pfifo0_data_byte0_8 = pfifo0_rd_data[0*8+7:0*8]; +assign pfifo0_data_byte1_8 = pfifo0_rd_data[1*8+7:1*8]; +assign pfifo0_data_byte2_8 = pfifo0_rd_data[2*8+7:2*8]; +assign pfifo0_data_byte3_8 = pfifo0_rd_data[3*8+7:3*8]; +assign pfifo0_data_byte4_8 = pfifo0_rd_data[4*8+7:4*8]; +assign pfifo0_data_byte5_8 = pfifo0_rd_data[5*8+7:5*8]; +assign pfifo0_data_byte6_8 = pfifo0_rd_data[6*8+7:6*8]; +assign pfifo0_data_byte7_8 = pfifo0_rd_data[7*8+7:7*8]; + +assign pfifo1_data_byte0_8 = pfifo1_rd_data[0*8+7:0*8]; +assign pfifo1_data_byte1_8 = pfifo1_rd_data[1*8+7:1*8]; +assign pfifo1_data_byte2_8 = pfifo1_rd_data[2*8+7:2*8]; +assign pfifo1_data_byte3_8 = pfifo1_rd_data[3*8+7:3*8]; +assign pfifo1_data_byte4_8 = pfifo1_rd_data[4*8+7:4*8]; +assign pfifo1_data_byte5_8 = pfifo1_rd_data[5*8+7:5*8]; +assign pfifo1_data_byte6_8 = pfifo1_rd_data[6*8+7:6*8]; +assign pfifo1_data_byte7_8 = pfifo1_rd_data[7*8+7:7*8]; + +assign pfifo2_data_byte0_8 = pfifo2_rd_data[0*8+7:0*8]; +assign pfifo2_data_byte1_8 = pfifo2_rd_data[1*8+7:1*8]; +assign pfifo2_data_byte2_8 = pfifo2_rd_data[2*8+7:2*8]; +assign pfifo2_data_byte3_8 = pfifo2_rd_data[3*8+7:3*8]; +assign pfifo2_data_byte4_8 = pfifo2_rd_data[4*8+7:4*8]; +assign pfifo2_data_byte5_8 = pfifo2_rd_data[5*8+7:5*8]; +assign pfifo2_data_byte6_8 = pfifo2_rd_data[6*8+7:6*8]; +assign pfifo2_data_byte7_8 = pfifo2_rd_data[7*8+7:7*8]; + +assign pfifo3_data_byte0_8 = pfifo3_rd_data[0*8+7:0*8]; +assign pfifo3_data_byte1_8 = pfifo3_rd_data[1*8+7:1*8]; +assign pfifo3_data_byte2_8 = pfifo3_rd_data[2*8+7:2*8]; +assign pfifo3_data_byte3_8 = pfifo3_rd_data[3*8+7:3*8]; +assign pfifo3_data_byte4_8 = pfifo3_rd_data[4*8+7:4*8]; +assign pfifo3_data_byte5_8 = pfifo3_rd_data[5*8+7:5*8]; +assign pfifo3_data_byte6_8 = pfifo3_rd_data[6*8+7:6*8]; +assign pfifo3_data_byte7_8 = pfifo3_rd_data[7*8+7:7*8]; + + +assign pfifo0_data_ext_byte0_8 = {{24{pfifo0_data_byte0_8[7]}}, pfifo0_data_byte0_8[7:0]}; +assign pfifo0_data_ext_byte1_8 = {{24{pfifo0_data_byte1_8[7]}}, pfifo0_data_byte1_8[7:0]}; +assign pfifo0_data_ext_byte2_8 = {{24{pfifo0_data_byte2_8[7]}}, pfifo0_data_byte2_8[7:0]}; +assign pfifo0_data_ext_byte3_8 = {{24{pfifo0_data_byte3_8[7]}}, pfifo0_data_byte3_8[7:0]}; +assign pfifo0_data_ext_byte4_8 = {{24{pfifo0_data_byte4_8[7]}}, pfifo0_data_byte4_8[7:0]}; +assign pfifo0_data_ext_byte5_8 = {{24{pfifo0_data_byte5_8[7]}}, pfifo0_data_byte5_8[7:0]}; +assign pfifo0_data_ext_byte6_8 = {{24{pfifo0_data_byte6_8[7]}}, pfifo0_data_byte6_8[7:0]}; +assign pfifo0_data_ext_byte7_8 = {{24{pfifo0_data_byte7_8[7]}}, pfifo0_data_byte7_8[7:0]}; + +assign pfifo1_data_ext_byte0_8 = {{24{pfifo1_data_byte0_8[7]}}, pfifo1_data_byte0_8[7:0]}; +assign pfifo1_data_ext_byte1_8 = {{24{pfifo1_data_byte1_8[7]}}, pfifo1_data_byte1_8[7:0]}; +assign pfifo1_data_ext_byte2_8 = {{24{pfifo1_data_byte2_8[7]}}, pfifo1_data_byte2_8[7:0]}; +assign pfifo1_data_ext_byte3_8 = {{24{pfifo1_data_byte3_8[7]}}, pfifo1_data_byte3_8[7:0]}; +assign pfifo1_data_ext_byte4_8 = {{24{pfifo1_data_byte4_8[7]}}, pfifo1_data_byte4_8[7:0]}; +assign pfifo1_data_ext_byte5_8 = {{24{pfifo1_data_byte5_8[7]}}, pfifo1_data_byte5_8[7:0]}; +assign pfifo1_data_ext_byte6_8 = {{24{pfifo1_data_byte6_8[7]}}, pfifo1_data_byte6_8[7:0]}; +assign pfifo1_data_ext_byte7_8 = {{24{pfifo1_data_byte7_8[7]}}, pfifo1_data_byte7_8[7:0]}; + +assign pfifo2_data_ext_byte0_8 = {{24{pfifo2_data_byte0_8[7]}}, pfifo2_data_byte0_8[7:0]}; +assign pfifo2_data_ext_byte1_8 = {{24{pfifo2_data_byte1_8[7]}}, pfifo2_data_byte1_8[7:0]}; +assign pfifo2_data_ext_byte2_8 = {{24{pfifo2_data_byte2_8[7]}}, pfifo2_data_byte2_8[7:0]}; +assign pfifo2_data_ext_byte3_8 = {{24{pfifo2_data_byte3_8[7]}}, pfifo2_data_byte3_8[7:0]}; +assign pfifo2_data_ext_byte4_8 = {{24{pfifo2_data_byte4_8[7]}}, pfifo2_data_byte4_8[7:0]}; +assign pfifo2_data_ext_byte5_8 = {{24{pfifo2_data_byte5_8[7]}}, pfifo2_data_byte5_8[7:0]}; +assign pfifo2_data_ext_byte6_8 = {{24{pfifo2_data_byte6_8[7]}}, pfifo2_data_byte6_8[7:0]}; +assign pfifo2_data_ext_byte7_8 = {{24{pfifo2_data_byte7_8[7]}}, pfifo2_data_byte7_8[7:0]}; + +assign pfifo3_data_ext_byte0_8 = {{24{pfifo3_data_byte0_8[7]}}, pfifo3_data_byte0_8[7:0]}; +assign pfifo3_data_ext_byte1_8 = {{24{pfifo3_data_byte1_8[7]}}, pfifo3_data_byte1_8[7:0]}; +assign pfifo3_data_ext_byte2_8 = {{24{pfifo3_data_byte2_8[7]}}, pfifo3_data_byte2_8[7:0]}; +assign pfifo3_data_ext_byte3_8 = {{24{pfifo3_data_byte3_8[7]}}, pfifo3_data_byte3_8[7:0]}; +assign pfifo3_data_ext_byte4_8 = {{24{pfifo3_data_byte4_8[7]}}, pfifo3_data_byte4_8[7:0]}; +assign pfifo3_data_ext_byte5_8 = {{24{pfifo3_data_byte5_8[7]}}, pfifo3_data_byte5_8[7:0]}; +assign pfifo3_data_ext_byte6_8 = {{24{pfifo3_data_byte6_8[7]}}, pfifo3_data_byte6_8[7:0]}; +assign pfifo3_data_ext_byte7_8 = {{24{pfifo3_data_byte7_8[7]}}, pfifo3_data_byte7_8[7:0]}; + + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// INT8, concate +//: my $k = 8; +//: foreach my $j (0..3) { +//: print "assign pfifo_data${j}_8 = {"; +//: foreach my $i (0..${k}-2) { +//: my $ii = $k - $i -1; +//: print "pfifo${j}_data_ext_byte${ii}_8,"; +//: } +//: print "pfifo${j}_data_ext_byte0_8}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign pfifo_data0_8 = {pfifo0_data_ext_byte7_8,pfifo0_data_ext_byte6_8,pfifo0_data_ext_byte5_8,pfifo0_data_ext_byte4_8,pfifo0_data_ext_byte3_8,pfifo0_data_ext_byte2_8,pfifo0_data_ext_byte1_8,pfifo0_data_ext_byte0_8}; +assign pfifo_data1_8 = {pfifo1_data_ext_byte7_8,pfifo1_data_ext_byte6_8,pfifo1_data_ext_byte5_8,pfifo1_data_ext_byte4_8,pfifo1_data_ext_byte3_8,pfifo1_data_ext_byte2_8,pfifo1_data_ext_byte1_8,pfifo1_data_ext_byte0_8}; +assign pfifo_data2_8 = {pfifo2_data_ext_byte7_8,pfifo2_data_ext_byte6_8,pfifo2_data_ext_byte5_8,pfifo2_data_ext_byte4_8,pfifo2_data_ext_byte3_8,pfifo2_data_ext_byte2_8,pfifo2_data_ext_byte1_8,pfifo2_data_ext_byte0_8}; +assign pfifo_data3_8 = {pfifo3_data_ext_byte7_8,pfifo3_data_ext_byte6_8,pfifo3_data_ext_byte5_8,pfifo3_data_ext_byte4_8,pfifo3_data_ext_byte3_8,pfifo3_data_ext_byte2_8,pfifo3_data_ext_byte1_8,pfifo3_data_ext_byte0_8}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//=====PERF COUNT BEG============= +assign dp2reg_status_inf_input_num = 32'h0; +assign dp2reg_status_nan_input_num = 32'h0; +//=====PERF COUNT END============= +always @( + pfifo0_sel + or pfifo1_sel + or pfifo2_sel + or pfifo3_sel + or cfg_di_16 + or pfifo_data0_8 + or pfifo_data1_8 + or pfifo_data2_8 + or pfifo_data3_8 + or pfifo_data0_16 + or pfifo_data1_16 + or pfifo_data2_16 + or pfifo_data3_16 + ) begin +//spyglass disable_block W171 W226 + case (1'b1) + pfifo0_sel: pfifo_data_r = cfg_di_16 ? pfifo_data0_16 : pfifo_data0_8; + pfifo1_sel: pfifo_data_r = cfg_di_16 ? pfifo_data1_16 : pfifo_data1_8; + pfifo2_sel: pfifo_data_r = cfg_di_16 ? pfifo_data2_16 : pfifo_data2_8; + pfifo3_sel: pfifo_data_r = cfg_di_16 ? pfifo_data3_16 : pfifo_data3_8; + default : begin + pfifo_data_r[32*8 -1:0] = {(32*8){`x_or_0}}; + end + endcase +//spyglass enable_block W171 W226 +end +assign dat_data = pfifo_data_r; +assign dat_accept = dat_vld & dat_rdy; +assign dat_layer_end = cmd_cube_end & is_last_beat; +assign dat_batch_end = cmd_cube_end & is_last_beat; +assign dat_pd[32*8 -1:0] = dat_data[32*8 -1:0]; +assign dat_pd[32*8] = dat_batch_end ; +assign dat_pd[32*8 +1] = dat_layer_end ; +NV_NVDLA_SDP_MRDMA_EG_DOUT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dat_pd (dat_pd[32*8 +1:0]) + ,.dat_vld (dat_vld) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.dat_rdy (dat_rdy) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ); +assign sdp_mrdma2cmux_layer_end = sdp_mrdma2cmux_pd[32*8 +1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg_done <= 1'b0; + end else begin + eg_done <= sdp_mrdma2cmux_layer_end & sdp_mrdma2cmux_valid & sdp_mrdma2cmux_ready; + end +end +//Shift-left - unsigned shift argument one bit more +endmodule // NV_NVDLA_SDP_MRDMA_EG_dout +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is sdp_mrdma2cmux_pd (sdp_mrdma2cmux_valid, sdp_mrdma2cmux_ready) <= dat_pd[32*8 +1:0] (dat_vld,dat_rdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_MRDMA_EG_DOUT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dat_pd + ,dat_vld + ,dat_rdy + ,sdp_mrdma2cmux_pd + ,sdp_mrdma2cmux_valid + ,sdp_mrdma2cmux_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32*8 +1:0] dat_pd; +input dat_vld; +output dat_rdy; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +//: my $dw = 32*8 +2; +//: &eperl::pipe("-is -wid $dw -do sdp_mrdma2cmux_pd -vo sdp_mrdma2cmux_valid -ri sdp_mrdma2cmux_ready -di dat_pd -vi dat_vld -ro dat_rdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg dat_rdy; +reg skid_flop_dat_rdy; +reg skid_flop_dat_vld; +reg [258-1:0] skid_flop_dat_pd; +reg pipe_skid_dat_vld; +reg [258-1:0] pipe_skid_dat_pd; +// Wire +wire skid_dat_vld; +wire [258-1:0] skid_dat_pd; +wire skid_dat_rdy; +wire pipe_skid_dat_rdy; +wire sdp_mrdma2cmux_valid; +wire [258-1:0] sdp_mrdma2cmux_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dat_rdy <= 1'b1; + skid_flop_dat_rdy <= 1'b1; + end else begin + dat_rdy <= skid_dat_rdy; + skid_flop_dat_rdy <= skid_dat_rdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_dat_vld <= 1'b0; + end else begin + if (skid_flop_dat_rdy) begin + skid_flop_dat_vld <= dat_vld; + end + end +end +assign skid_dat_vld = (skid_flop_dat_rdy) ? dat_vld : skid_flop_dat_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_dat_rdy & dat_vld) begin + skid_flop_dat_pd[258-1:0] <= dat_pd[258-1:0]; + end +end +assign skid_dat_pd[258-1:0] = (skid_flop_dat_rdy) ? dat_pd[258-1:0] : skid_flop_dat_pd[258-1:0]; + + +// PIPE READY +assign skid_dat_rdy = pipe_skid_dat_rdy || !pipe_skid_dat_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_dat_vld <= 1'b0; + end else begin + if (skid_dat_rdy) begin + pipe_skid_dat_vld <= skid_dat_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_dat_rdy && skid_dat_vld) begin + pipe_skid_dat_pd[258-1:0] <= skid_dat_pd[258-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_dat_rdy = sdp_mrdma2cmux_ready; +assign sdp_mrdma2cmux_valid = pipe_skid_dat_vld; +assign sdp_mrdma2cmux_pd = pipe_skid_dat_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_MRDMA_EG_DOUT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v.vcp new file mode 100644 index 0000000..3dd6cf6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v.vcp @@ -0,0 +1,334 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_EG_dout.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_MRDMA_EG_dout ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,op_load //|< i + ,eg_done //|> o + ,cmd2dat_dma_pd //|< i + ,cmd2dat_dma_pvld //|< i + ,cmd2dat_dma_prdy //|> o + ,pfifo0_rd_pd //|< i + ,pfifo0_rd_pvld //|< i + ,pfifo1_rd_pd //|< i + ,pfifo1_rd_pvld //|< i + ,pfifo2_rd_pd //|< i + ,pfifo2_rd_pvld //|< i + ,pfifo3_rd_pd //|< i + ,pfifo3_rd_pvld //|< i + ,pfifo0_rd_prdy //|> o + ,pfifo1_rd_prdy //|> o + ,pfifo2_rd_prdy //|> o + ,pfifo3_rd_prdy //|> o + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_perf_nan_inf_count_en //|< i + ,dp2reg_status_inf_input_num //|> o + ,dp2reg_status_nan_input_num //|> o + ); +// +// NV_NVDLA_SDP_MRDMA_EG_dout_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +output eg_done; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input reg2dp_perf_nan_inf_count_en; +output [31:0] dp2reg_status_inf_input_num; +output [31:0] dp2reg_status_nan_input_num; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +input cmd2dat_dma_pvld; +output cmd2dat_dma_prdy; +input [14:0] cmd2dat_dma_pd; +input pfifo0_rd_pvld; +output pfifo0_rd_prdy; +input [8*8 -1:0] pfifo0_rd_pd; +input pfifo1_rd_pvld; +output pfifo1_rd_prdy; +input [8*8 -1:0] pfifo1_rd_pd; +input pfifo2_rd_pvld; +output pfifo2_rd_prdy; +input [8*8 -1:0] pfifo2_rd_pd; +input pfifo3_rd_pvld; +output pfifo3_rd_prdy; +input [8*8 -1:0] pfifo3_rd_pd; +reg eg_done; +wire cfg_di_16; +wire cfg_di_fp16; +wire cfg_di_int16; +wire cfg_di_int8; +wire cfg_do_int8; +wire cfg_mode_1x1_pack; +wire cfg_perf_nan_inf_count_en; +wire [13:0] size_of_beat; +reg [13:0] beat_cnt; +wire is_last_beat; +wire cmd2dat_dma_cube_end; +wire [13:0] cmd2dat_dma_size; +wire cmd_cube_end; +wire dat_accept; +wire dat_batch_end; +wire [32*8 -1:0] dat_data; +wire dat_layer_end; +wire [32*8 +1:0] dat_pd; +wire dat_rdy; +wire dat_vld; +wire fifo_vld; +wire pfifo0_sel; +wire pfifo1_sel; +wire pfifo2_sel; +wire pfifo3_sel; +wire [8*8 -1:0] pfifo0_rd_data; +wire [8*8 -1:0] pfifo1_rd_data; +wire [8*8 -1:0] pfifo2_rd_data; +wire [8*8 -1:0] pfifo3_rd_data; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [15:0] pfifo${j}_data_byte${i}_16; \n"; +//: } +//: } +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [31:0] pfifo${j}_data_ext_byte${i}_int16; \n"; +//: print "wire [31:0] pfifo${j}_data_ext_byte${i}_16; \n"; +//: } +//: } +//: my $k = 8; +//: my $dw = $k * 8 -1; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [7:0] pfifo${j}_data_byte${i}_8; \n"; +//: } +//: } +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "wire [31:0] pfifo${j}_data_ext_byte${i}_8; \n"; +//: } +//: } +wire [32*8 -1:0] pfifo_data0_16; +wire [32*8 -1:0] pfifo_data1_16; +wire [32*8 -1:0] pfifo_data2_16; +wire [32*8 -1:0] pfifo_data3_16; +wire [32*8 -1:0] pfifo_data0_8; +wire [32*8 -1:0] pfifo_data1_8; +wire [32*8 -1:0] pfifo_data2_8; +wire [32*8 -1:0] pfifo_data3_8; +reg [32*8 -1:0] pfifo_data_r; +wire [32*8 -1:0] pfifo_data; +wire pfifo_sel; +wire pfifo_vld; +wire sdp_mrdma2cmux_layer_end; +//============== +// CFG +//============== +assign cfg_di_int8 = reg2dp_in_precision == 0 ; +assign cfg_di_int16 = reg2dp_in_precision == 1 ; +assign cfg_di_fp16 = reg2dp_in_precision == 2 ; +assign cfg_di_16 = cfg_di_int16 | cfg_di_fp16; +assign cfg_do_int8 = reg2dp_proc_precision == 0 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_perf_nan_inf_count_en = reg2dp_perf_nan_inf_count_en; +//pop command dat fifo // +assign cmd2dat_dma_prdy = dat_accept & is_last_beat & fifo_vld & dat_rdy; +assign cmd2dat_dma_size[13:0] = cmd2dat_dma_pd[13:0]; +assign cmd2dat_dma_cube_end = cmd2dat_dma_pd[14]; +assign size_of_beat = {14 {cmd2dat_dma_pvld}} & cmd2dat_dma_size; +assign cmd_cube_end = {1 {cmd2dat_dma_pvld}} & cmd2dat_dma_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_cnt <= {14{1'b0}}; + end else begin + if (dat_accept) begin + if (is_last_beat) begin + beat_cnt <= 0; + end else begin + beat_cnt <= beat_cnt + 1; + end + end + end +end +assign is_last_beat = (beat_cnt==size_of_beat); +assign pfifo0_sel = beat_cnt[1:0]==0; +assign pfifo1_sel = beat_cnt[1:0]==1; +assign pfifo2_sel = beat_cnt[1:0]==2; +assign pfifo3_sel = beat_cnt[1:0]==3; +assign pfifo_vld = (pfifo3_rd_pvld & pfifo3_sel) | (pfifo2_rd_pvld & pfifo2_sel) | (pfifo1_rd_pvld & pfifo1_sel) | (pfifo0_rd_pvld & pfifo0_sel); +assign fifo_vld = pfifo_vld; +assign dat_vld = fifo_vld; //& cmd2dat_dma_pvld; +assign pfifo0_rd_prdy = dat_rdy & pfifo0_sel; //& cmd2dat_dma_pvld; +assign pfifo1_rd_prdy = dat_rdy & pfifo1_sel; //& cmd2dat_dma_pvld; +assign pfifo2_rd_prdy = dat_rdy & pfifo2_sel; //& cmd2dat_dma_pvld; +assign pfifo3_rd_prdy = dat_rdy & pfifo3_sel; //& cmd2dat_dma_pvld; +assign pfifo0_rd_data = {8*8{pfifo0_sel}} & pfifo0_rd_pd; +assign pfifo1_rd_data = {8*8{pfifo1_sel}} & pfifo1_rd_pd; +assign pfifo2_rd_data = {8*8{pfifo2_sel}} & pfifo2_rd_pd; +assign pfifo3_rd_data = {8*8{pfifo3_sel}} & pfifo3_rd_pd; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_byte${i}_16 = pfifo${j}_rd_data[${i}*16+15:${i}*16]; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_ext_byte${i}_int16 = {{16{pfifo${j}_data_byte${i}_16[15]}}, pfifo${j}_data_byte${i}_16[15:0]}; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//: my $k = 8/2; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_ext_byte${i}_16 = pfifo${j}_data_ext_byte${i}_int16; \n"; +//: } +//: } +//: print "\n"; +//: my $k = 8/2; +//: my $remain = $k*32; +//: foreach my $j (0..3) { +//: print "assign pfifo_data${j}_16 = {${remain}\'h0,"; +//: foreach my $i (0..${k}-2) { +//: my $ii = $k - $i -1; +//: print "pfifo${j}_data_ext_byte${ii}_16,"; +//: } +//: print "pfifo${j}_data_ext_byte0_16}; \n"; +//: } +//// int8 /////////// +//: my $k = 8; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_byte${i}_8 = pfifo${j}_rd_data[${i}*8+7:${i}*8]; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +//: my $k = 8; +//: foreach my $j (0..3) { +//: foreach my $i (0..${k}-1) { +//: print "assign pfifo${j}_data_ext_byte${i}_8 = {{24{pfifo${j}_data_byte${i}_8[7]}}, pfifo${j}_data_byte${i}_8[7:0]}; \n"; +//: } +//: print "\n"; +//: } +//: print "\n"; +// INT8, concate +//: my $k = 8; +//: foreach my $j (0..3) { +//: print "assign pfifo_data${j}_8 = {"; +//: foreach my $i (0..${k}-2) { +//: my $ii = $k - $i -1; +//: print "pfifo${j}_data_ext_byte${ii}_8,"; +//: } +//: print "pfifo${j}_data_ext_byte0_8}; \n"; +//: } +//=====PERF COUNT BEG============= +assign dp2reg_status_inf_input_num = 32'h0; +assign dp2reg_status_nan_input_num = 32'h0; +//=====PERF COUNT END============= +always @( + pfifo0_sel + or pfifo1_sel + or pfifo2_sel + or pfifo3_sel + or cfg_di_16 + or pfifo_data0_8 + or pfifo_data1_8 + or pfifo_data2_8 + or pfifo_data3_8 + or pfifo_data0_16 + or pfifo_data1_16 + or pfifo_data2_16 + or pfifo_data3_16 + ) begin +//spyglass disable_block W171 W226 + case (1'b1) + pfifo0_sel: pfifo_data_r = cfg_di_16 ? pfifo_data0_16 : pfifo_data0_8; + pfifo1_sel: pfifo_data_r = cfg_di_16 ? pfifo_data1_16 : pfifo_data1_8; + pfifo2_sel: pfifo_data_r = cfg_di_16 ? pfifo_data2_16 : pfifo_data2_8; + pfifo3_sel: pfifo_data_r = cfg_di_16 ? pfifo_data3_16 : pfifo_data3_8; + default : begin + pfifo_data_r[32*8 -1:0] = {(32*8){`x_or_0}}; + end + endcase +//spyglass enable_block W171 W226 +end +assign dat_data = pfifo_data_r; +assign dat_accept = dat_vld & dat_rdy; +assign dat_layer_end = cmd_cube_end & is_last_beat; +assign dat_batch_end = cmd_cube_end & is_last_beat; +assign dat_pd[32*8 -1:0] = dat_data[32*8 -1:0]; +assign dat_pd[32*8] = dat_batch_end ; +assign dat_pd[32*8 +1] = dat_layer_end ; +NV_NVDLA_SDP_MRDMA_EG_DOUT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dat_pd (dat_pd[32*8 +1:0]) + ,.dat_vld (dat_vld) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.dat_rdy (dat_rdy) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ); +assign sdp_mrdma2cmux_layer_end = sdp_mrdma2cmux_pd[32*8 +1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg_done <= 1'b0; + end else begin + eg_done <= sdp_mrdma2cmux_layer_end & sdp_mrdma2cmux_valid & sdp_mrdma2cmux_ready; + end +end +//Shift-left - unsigned shift argument one bit more +endmodule // NV_NVDLA_SDP_MRDMA_EG_dout +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is sdp_mrdma2cmux_pd (sdp_mrdma2cmux_valid, sdp_mrdma2cmux_ready) <= dat_pd[32*8 +1:0] (dat_vld,dat_rdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_MRDMA_EG_DOUT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,dat_pd + ,dat_vld + ,dat_rdy + ,sdp_mrdma2cmux_pd + ,sdp_mrdma2cmux_valid + ,sdp_mrdma2cmux_ready + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32*8 +1:0] dat_pd; +input dat_vld; +output dat_rdy; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +//: my $dw = 32*8 +2; +//: &eperl::pipe("-is -wid $dw -do sdp_mrdma2cmux_pd -vo sdp_mrdma2cmux_valid -ri sdp_mrdma2cmux_ready -di dat_pd -vi dat_vld -ro dat_rdy"); +endmodule // NV_NVDLA_SDP_MRDMA_EG_DOUT_pipe_p1 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_cq.v new file mode 100644 index 0000000..653690e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_cq.v @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [13:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [13:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] ig2cq_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 7'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [6:0] ig2cq_adr; // current write address +wire [6:0] cq2eg_adr_p; // read address to use for ram +wire [13:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x14 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (ig2cq_adr == 7'd79) ? 7'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] cq2eg_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (cq2eg_adr == 7'd79) ? 7'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [6:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 7'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_cq_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_MRDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_cq.v.vcp new file mode 100644 index 0000000..653690e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_cq.v.vcp @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [13:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [13:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [6:0] ig2cq_count; // write-side count +wire [6:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [6:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [6:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_80 = ( wr_count_next_no_wr_popping == 7'd80 ); +wire wr_count_next_is_80 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_80; +wire [6:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [6:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_80 || // busy next cycle? + (wr_limit_reg != 7'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 7'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [6:0] ig2cq_adr; // current write address +wire [6:0] cq2eg_adr_p; // read address to use for ram +wire [13:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_80x14 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [6:0] wr_adr_next = (ig2cq_adr == 7'd79) ? 7'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 7'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [6:0] cq2eg_adr; // current read address +// next read address +wire [6:0] rd_adr_next = (cq2eg_adr == 7'd79) ? 7'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 7'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {7{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [6:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [6:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [6:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [6:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 7'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {7{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_MRDMA_cq_wr_limit : 7'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 7'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 7'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 7'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [6:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 7'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_MRDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_MRDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {25'd0, (wr_limit_reg == 7'd0) ? 7'd80 : wr_limit_reg} ) + , .curr ( {25'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_MRDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_MRDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v new file mode 100644 index 0000000..9dd7c0c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v @@ -0,0 +1,163 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,eg_done //|> o + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,cq2eg_prdy //|> o + ,dma_rd_rsp_ram_type //|> o + ,dma_rd_rsp_pd //|< i + ,dma_rd_rsp_vld //|< i + ,dma_rd_rsp_rdy //|> o + ,dma_rd_cdt_lat_fifo_pop //|> o + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_width //|< i + ,reg2dp_height //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_perf_nan_inf_count_en //|< i + ,dp2reg_status_inf_input_num //|> o + ,dp2reg_status_nan_input_num //|> o + ); +//&Catenate "NV_NVDLA_SDP_MRDMA_eg_ports.v"; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +output eg_done; +input [13:0] cq2eg_pd; +input cq2eg_pvld; +output cq2eg_prdy; +output dma_rd_rsp_ram_type; +input [65 -1:0] dma_rd_rsp_pd; +input dma_rd_rsp_vld; +output dma_rd_rsp_rdy; +output dma_rd_cdt_lat_fifo_pop; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +input reg2dp_src_ram_type; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input reg2dp_perf_nan_inf_count_en; +output [31:0] dp2reg_status_inf_input_num; +output [31:0] dp2reg_status_nan_input_num; +wire [14:0] cmd2dat_dma_pd; +wire cmd2dat_dma_prdy; +wire cmd2dat_dma_pvld; +wire [12:0] cmd2dat_spt_pd; +wire cmd2dat_spt_prdy; +wire cmd2dat_spt_pvld; +wire [8*8 -1:0] pfifo0_rd_pd; +wire pfifo0_rd_prdy; +wire pfifo0_rd_pvld; +wire [8*8 -1:0] pfifo1_rd_pd; +wire pfifo1_rd_prdy; +wire pfifo1_rd_pvld; +wire [8*8 -1:0] pfifo2_rd_pd; +wire pfifo2_rd_prdy; +wire pfifo2_rd_pvld; +wire [8*8 -1:0] pfifo3_rd_pd; +wire pfifo3_rd_prdy; +wire pfifo3_rd_pvld; +NV_NVDLA_SDP_MRDMA_EG_cmd u_cmd ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.eg_done (eg_done) + ,.cq2eg_pvld (cq2eg_pvld) + ,.cq2eg_prdy (cq2eg_prdy) + ,.cq2eg_pd (cq2eg_pd[13:0]) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0]) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ); +NV_NVDLA_SDP_MRDMA_EG_din u_din ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.dma_rd_rsp_ram_type (dma_rd_rsp_ram_type) + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0]) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.pfifo0_rd_pd (pfifo0_rd_pd[8*8 -1:0]) + ,.pfifo0_rd_pvld (pfifo0_rd_pvld) + ,.pfifo0_rd_prdy (pfifo0_rd_prdy) + ,.pfifo1_rd_pd (pfifo1_rd_pd[8*8 -1:0]) + ,.pfifo1_rd_pvld (pfifo1_rd_pvld) + ,.pfifo1_rd_prdy (pfifo1_rd_prdy) + ,.pfifo2_rd_pd (pfifo2_rd_pd[8*8 -1:0]) + ,.pfifo2_rd_pvld (pfifo2_rd_pvld) + ,.pfifo2_rd_prdy (pfifo2_rd_prdy) + ,.pfifo3_rd_pd (pfifo3_rd_pd[8*8 -1:0]) + ,.pfifo3_rd_pvld (pfifo3_rd_pvld) + ,.pfifo3_rd_prdy (pfifo3_rd_prdy) + ); +NV_NVDLA_SDP_MRDMA_EG_dout u_dout ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.op_load (op_load) + ,.eg_done (eg_done) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0]) + ,.pfifo0_rd_pvld (pfifo0_rd_pvld) + ,.pfifo0_rd_prdy (pfifo0_rd_prdy) + ,.pfifo0_rd_pd (pfifo0_rd_pd[8*8 -1:0]) + ,.pfifo1_rd_pvld (pfifo1_rd_pvld) + ,.pfifo1_rd_prdy (pfifo1_rd_prdy) + ,.pfifo1_rd_pd (pfifo1_rd_pd[8*8 -1:0]) + ,.pfifo2_rd_pvld (pfifo2_rd_pvld) + ,.pfifo2_rd_prdy (pfifo2_rd_prdy) + ,.pfifo2_rd_pd (pfifo2_rd_pd[8*8 -1:0]) + ,.pfifo3_rd_pvld (pfifo3_rd_pvld) + ,.pfifo3_rd_prdy (pfifo3_rd_prdy) + ,.pfifo3_rd_pd (pfifo3_rd_pd[8*8 -1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) + ); +endmodule // NV_NVDLA_SDP_MRDMA_eg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v.vcp new file mode 100644 index 0000000..9dd7c0c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_eg.v.vcp @@ -0,0 +1,163 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,eg_done //|> o + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,cq2eg_prdy //|> o + ,dma_rd_rsp_ram_type //|> o + ,dma_rd_rsp_pd //|< i + ,dma_rd_rsp_vld //|< i + ,dma_rd_rsp_rdy //|> o + ,dma_rd_cdt_lat_fifo_pop //|> o + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_width //|< i + ,reg2dp_height //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_perf_nan_inf_count_en //|< i + ,dp2reg_status_inf_input_num //|> o + ,dp2reg_status_nan_input_num //|> o + ); +//&Catenate "NV_NVDLA_SDP_MRDMA_eg_ports.v"; +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +output eg_done; +input [13:0] cq2eg_pd; +input cq2eg_pvld; +output cq2eg_prdy; +output dma_rd_rsp_ram_type; +input [65 -1:0] dma_rd_rsp_pd; +input dma_rd_rsp_vld; +output dma_rd_rsp_rdy; +output dma_rd_cdt_lat_fifo_pop; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +input reg2dp_src_ram_type; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input reg2dp_perf_nan_inf_count_en; +output [31:0] dp2reg_status_inf_input_num; +output [31:0] dp2reg_status_nan_input_num; +wire [14:0] cmd2dat_dma_pd; +wire cmd2dat_dma_prdy; +wire cmd2dat_dma_pvld; +wire [12:0] cmd2dat_spt_pd; +wire cmd2dat_spt_prdy; +wire cmd2dat_spt_pvld; +wire [8*8 -1:0] pfifo0_rd_pd; +wire pfifo0_rd_prdy; +wire pfifo0_rd_pvld; +wire [8*8 -1:0] pfifo1_rd_pd; +wire pfifo1_rd_prdy; +wire pfifo1_rd_pvld; +wire [8*8 -1:0] pfifo2_rd_pd; +wire pfifo2_rd_prdy; +wire pfifo2_rd_pvld; +wire [8*8 -1:0] pfifo3_rd_pd; +wire pfifo3_rd_prdy; +wire pfifo3_rd_pvld; +NV_NVDLA_SDP_MRDMA_EG_cmd u_cmd ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.eg_done (eg_done) + ,.cq2eg_pvld (cq2eg_pvld) + ,.cq2eg_prdy (cq2eg_prdy) + ,.cq2eg_pd (cq2eg_pd[13:0]) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0]) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ); +NV_NVDLA_SDP_MRDMA_EG_din u_din ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) + ,.dma_rd_rsp_ram_type (dma_rd_rsp_ram_type) + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[12:0]) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.pfifo0_rd_pd (pfifo0_rd_pd[8*8 -1:0]) + ,.pfifo0_rd_pvld (pfifo0_rd_pvld) + ,.pfifo0_rd_prdy (pfifo0_rd_prdy) + ,.pfifo1_rd_pd (pfifo1_rd_pd[8*8 -1:0]) + ,.pfifo1_rd_pvld (pfifo1_rd_pvld) + ,.pfifo1_rd_prdy (pfifo1_rd_prdy) + ,.pfifo2_rd_pd (pfifo2_rd_pd[8*8 -1:0]) + ,.pfifo2_rd_pvld (pfifo2_rd_pvld) + ,.pfifo2_rd_prdy (pfifo2_rd_prdy) + ,.pfifo3_rd_pd (pfifo3_rd_pd[8*8 -1:0]) + ,.pfifo3_rd_pvld (pfifo3_rd_pvld) + ,.pfifo3_rd_prdy (pfifo3_rd_prdy) + ); +NV_NVDLA_SDP_MRDMA_EG_dout u_dout ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.op_load (op_load) + ,.eg_done (eg_done) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[14:0]) + ,.pfifo0_rd_pvld (pfifo0_rd_pvld) + ,.pfifo0_rd_prdy (pfifo0_rd_prdy) + ,.pfifo0_rd_pd (pfifo0_rd_pd[8*8 -1:0]) + ,.pfifo1_rd_pvld (pfifo1_rd_pvld) + ,.pfifo1_rd_prdy (pfifo1_rd_prdy) + ,.pfifo1_rd_pd (pfifo1_rd_pd[8*8 -1:0]) + ,.pfifo2_rd_pvld (pfifo2_rd_pvld) + ,.pfifo2_rd_prdy (pfifo2_rd_prdy) + ,.pfifo2_rd_pd (pfifo2_rd_pd[8*8 -1:0]) + ,.pfifo3_rd_pvld (pfifo3_rd_pvld) + ,.pfifo3_rd_prdy (pfifo3_rd_prdy) + ,.pfifo3_rd_pd (pfifo3_rd_pd[8*8 -1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) + ); +endmodule // NV_NVDLA_SDP_MRDMA_eg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v new file mode 100644 index 0000000..049e6b2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_gate.v +module NV_NVDLA_SDP_MRDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,mrdma_disable + ,mrdma_slcg_op_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input mrdma_disable; +input mrdma_slcg_op_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg mrdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mrdma_enable <= 1'b0; + end else begin + mrdma_enable <= !mrdma_disable; + end +end +assign cfg_clk_en = mrdma_slcg_op_en & mrdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_MRDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v.vcp new file mode 100644 index 0000000..049e6b2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_gate.v.vcp @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_gate.v +module NV_NVDLA_SDP_MRDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,mrdma_disable + ,mrdma_slcg_op_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input mrdma_disable; +input mrdma_slcg_op_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg mrdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mrdma_enable <= 1'b0; + end else begin + mrdma_enable <= !mrdma_disable; + end +end +assign cfg_clk_en = mrdma_slcg_op_en & mrdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_MRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_MRDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v new file mode 100644 index 0000000..19b72c2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v @@ -0,0 +1,604 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_ig.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_ig ( + nvdla_core_clk + ,nvdla_core_rstn + ,op_load + ,ig2cq_pd + ,ig2cq_pvld + ,ig2cq_prdy + ,dma_rd_req_ram_type + ,dma_rd_req_pd + ,dma_rd_req_vld + ,dma_rd_req_rdy + ,reg2dp_batch_number + ,reg2dp_channel + ,reg2dp_height + ,reg2dp_width + ,reg2dp_in_precision + ,reg2dp_proc_precision + ,reg2dp_src_base_addr_high + ,reg2dp_src_base_addr_low + ,reg2dp_src_line_stride + ,reg2dp_src_ram_type + ,reg2dp_src_surface_stride + ,reg2dp_perf_dma_en + ,dp2reg_mrdma_stall + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +output [13:0] ig2cq_pd; +output ig2cq_pvld; +input ig2cq_prdy; +output dma_rd_req_ram_type; +output dma_rd_req_vld; +input dma_rd_req_rdy; +output [47 -1:0] dma_rd_req_pd; +input reg2dp_src_ram_type; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [31:0] reg2dp_src_base_addr_high; +input [31-3:0] reg2dp_src_base_addr_low; +input [31-3:0] reg2dp_src_line_stride; +input [31-3:0] reg2dp_src_surface_stride; +input reg2dp_perf_dma_en; +output [31:0] dp2reg_mrdma_stall; +reg cmd_process; +wire cmd_accept; +wire cmd_done; +wire [14:0] ig2eg_size; +wire ig2eg_cube_end; +wire cfg_di_int16; +wire cfg_di_int8; +wire cfg_do_int8; +wire cfg_mode_1x1_pack; +wire cfg_mode_multi_batch; +wire [31-3:0] cfg_line_stride; +wire [31-3:0] cfg_surf_stride; +wire [32 -3 -1:0] cfg_base_addr; +reg [32 -3 -1:0] base_addr_elem; +reg [32 -3 -1:0] base_addr_line; +reg [32 -3 -1:0] base_addr_surf; +reg [32 -3 -1:0] base_addr_width; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +reg mon_base_addr_elem_c; +reg mon_base_addr_line_c; +reg [4:0] count_b; +reg [13-3:0] count_c; +reg [12:0] count_h; +reg count_e; +reg [9:0] count_w; +wire is_batch_end; +wire is_cube_end; +wire is_elem_end; +wire is_last_b; +wire is_last_c; +wire is_last_e; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +wire [13-3:0] mode_1x1_req_size; +reg [14:0] dma_req_size; +wire [32 -3 -1:0] req_addr; +wire [32 -1:0] dma_req_addr; +wire [4:0] size_of_batch; +wire size_of_elem; +wire [9:0] size_of_width; +reg [13-3:0] size_of_surf; +reg mrdma_rd_stall_cnt_cen; +wire mrdma_rd_stall_cnt_clr; +wire mrdma_rd_stall_cnt_inc; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [31:0] dp2reg_mrdma_stall; +wire dp2reg_mrdma_stall_dec; +assign cmd_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_process <= 1'b0; + end else begin + if (op_load) begin + cmd_process <= 1'b1; + end else if (cmd_done) begin + cmd_process <= 1'b0; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !cmd_process && cmd_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// Address catenate and offset calc +//============== +//============== +// CFG value calculation +//============== +assign cfg_base_addr = reg2dp_src_base_addr_low; +assign cfg_line_stride = {reg2dp_src_line_stride}; +assign cfg_surf_stride = {reg2dp_src_surface_stride}; +assign cfg_di_int8 = reg2dp_in_precision == 0 ; +assign cfg_di_int16 = reg2dp_in_precision == 1 ; +assign cfg_do_int8 = reg2dp_proc_precision == 0 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_mode_multi_batch = reg2dp_batch_number!=0; +//============== +// CHANNEL Direction +// calculate how many 32x8 blocks in channel direction +//============== +always @( + reg2dp_channel + or cfg_di_int8 + or cfg_di_int16 + ) begin + if (cfg_di_int8) begin + size_of_surf = {1'b0,reg2dp_channel[12:3]}; + end else if (cfg_di_int16) begin + size_of_surf = reg2dp_channel[12:3 -1]; + end else begin + size_of_surf = reg2dp_channel[12:3 -1]; + end +end +//================================================= +// Cube Shape +//================================================= +assign is_batch_end = is_last_b; +assign is_elem_end = is_batch_end; +assign is_line_end = is_elem_end ; +assign is_surf_end = is_line_end & ( (cfg_mode_1x1_pack) || (is_last_h) ); +assign is_cube_end = is_surf_end & ( (cfg_mode_1x1_pack) || (is_last_c) ); +assign is_last_b = 1'b1; +//============== +// CHANNEL Count: +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {(14-3){1'b0}}; + end else begin + if (cmd_accept) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1'b1; + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +//============== +// LINE Count: +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1'b1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_height); +//========================================== +// DMA Req : ADDR PREPARE +//========================================== +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {(32 -3){1'b0}}; + mon_base_addr_line_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_line <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + cfg_surf_stride; + end else if (is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + cfg_line_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"MRDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_surf <= {(32 -3){1'b0}}; + mon_base_addr_surf_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_surf <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + cfg_surf_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"MRDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//========================================== +// DMA Req : Addr : Generation +//========================================== +assign req_addr = base_addr_line; +assign dma_req_addr = {req_addr,{3{1'b0}}}; +//============== +// DMA Req : SIZE : Generation +//============== +// in 1x1_pack mode, only send one request out +assign mode_1x1_req_size = size_of_surf; +always @( + cfg_mode_1x1_pack + or mode_1x1_req_size + or reg2dp_width + ) begin + if (cfg_mode_1x1_pack) begin + dma_req_size = {{(3 +1){1'b0}}, mode_1x1_req_size}; + end + else begin + dma_req_size = {{2{1'b0}}, reg2dp_width}; + end +end +assign ig2eg_size = dma_req_size; +assign ig2eg_cube_end = is_cube_end; +assign ig2cq_pd[12:0] = ig2eg_size[12:0]; +assign ig2cq_pd[13] = ig2eg_cube_end ; +assign ig2cq_pvld = cmd_process & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (ig2cq_pvld & ig2cq_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = cmd_process & ig2cq_prdy; +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[47 -1:32] = dma_req_size[14:0]; +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// PERF STATISTIC +//============== +assign mrdma_rd_stall_cnt_inc = dma_rd_req_vld & !dma_rd_req_rdy; +assign mrdma_rd_stall_cnt_clr = op_load; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mrdma_rd_stall_cnt_cen <= 1'b0; + end else begin + if ((op_load) == 1'b1) begin + mrdma_rd_stall_cnt_cen <= reg2dp_perf_dma_en; +//end else if ((op_load) == 1'b0) begin +//end else begin +// mrdma_rd_stall_cnt_cen <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(op_load))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_mrdma_stall_dec = 1'b0; +// stl adv logic +always @( + mrdma_rd_stall_cnt_inc + or dp2reg_mrdma_stall_dec + ) begin + stl_adv = mrdma_rd_stall_cnt_inc ^ dp2reg_mrdma_stall_dec; +end +// stl cnt logic +always @( + stl_cnt_cur + or mrdma_rd_stall_cnt_inc + or dp2reg_mrdma_stall_dec + or stl_adv + or mrdma_rd_stall_cnt_clr + ) begin + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (mrdma_rd_stall_cnt_inc && !dp2reg_mrdma_stall_dec)? stl_cnt_inc : (!mrdma_rd_stall_cnt_inc && dp2reg_mrdma_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (mrdma_rd_stall_cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (mrdma_rd_stall_cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @( + stl_cnt_cur + ) begin + dp2reg_mrdma_stall[31:0] = stl_cnt_cur[31:0]; +end +//============== +// FUNCTION POINT +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property sdp_mrdma_ig__access_CVIF__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((dma_rd_req_vld) && nvdla_core_rstn) |-> (dma_rd_req_ram_type==0); + endproperty +// Cover 0 : "dma_rd_req_ram_type==0" + FUNCPOINT_sdp_mrdma_ig__access_CVIF__0_COV : cover property (sdp_mrdma_ig__access_CVIF__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property sdp_mrdma_ig__access_MCIF__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((dma_rd_req_vld) && nvdla_core_rstn) |-> (dma_rd_req_ram_type==1); + endproperty +// Cover 1 : "dma_rd_req_ram_type==1" + FUNCPOINT_sdp_mrdma_ig__access_MCIF__1_COV : cover property (sdp_mrdma_ig__access_MCIF__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_SDP_MRDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v.vcp new file mode 100644 index 0000000..19b72c2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v.vcp @@ -0,0 +1,604 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_MRDMA_ig.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_MRDMA_ig ( + nvdla_core_clk + ,nvdla_core_rstn + ,op_load + ,ig2cq_pd + ,ig2cq_pvld + ,ig2cq_prdy + ,dma_rd_req_ram_type + ,dma_rd_req_pd + ,dma_rd_req_vld + ,dma_rd_req_rdy + ,reg2dp_batch_number + ,reg2dp_channel + ,reg2dp_height + ,reg2dp_width + ,reg2dp_in_precision + ,reg2dp_proc_precision + ,reg2dp_src_base_addr_high + ,reg2dp_src_base_addr_low + ,reg2dp_src_line_stride + ,reg2dp_src_ram_type + ,reg2dp_src_surface_stride + ,reg2dp_perf_dma_en + ,dp2reg_mrdma_stall + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +output [13:0] ig2cq_pd; +output ig2cq_pvld; +input ig2cq_prdy; +output dma_rd_req_ram_type; +output dma_rd_req_vld; +input dma_rd_req_rdy; +output [47 -1:0] dma_rd_req_pd; +input reg2dp_src_ram_type; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_in_precision; +input [1:0] reg2dp_proc_precision; +input [31:0] reg2dp_src_base_addr_high; +input [31-3:0] reg2dp_src_base_addr_low; +input [31-3:0] reg2dp_src_line_stride; +input [31-3:0] reg2dp_src_surface_stride; +input reg2dp_perf_dma_en; +output [31:0] dp2reg_mrdma_stall; +reg cmd_process; +wire cmd_accept; +wire cmd_done; +wire [14:0] ig2eg_size; +wire ig2eg_cube_end; +wire cfg_di_int16; +wire cfg_di_int8; +wire cfg_do_int8; +wire cfg_mode_1x1_pack; +wire cfg_mode_multi_batch; +wire [31-3:0] cfg_line_stride; +wire [31-3:0] cfg_surf_stride; +wire [32 -3 -1:0] cfg_base_addr; +reg [32 -3 -1:0] base_addr_elem; +reg [32 -3 -1:0] base_addr_line; +reg [32 -3 -1:0] base_addr_surf; +reg [32 -3 -1:0] base_addr_width; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +reg mon_base_addr_elem_c; +reg mon_base_addr_line_c; +reg [4:0] count_b; +reg [13-3:0] count_c; +reg [12:0] count_h; +reg count_e; +reg [9:0] count_w; +wire is_batch_end; +wire is_cube_end; +wire is_elem_end; +wire is_last_b; +wire is_last_c; +wire is_last_e; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +wire [13-3:0] mode_1x1_req_size; +reg [14:0] dma_req_size; +wire [32 -3 -1:0] req_addr; +wire [32 -1:0] dma_req_addr; +wire [4:0] size_of_batch; +wire size_of_elem; +wire [9:0] size_of_width; +reg [13-3:0] size_of_surf; +reg mrdma_rd_stall_cnt_cen; +wire mrdma_rd_stall_cnt_clr; +wire mrdma_rd_stall_cnt_inc; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +reg [31:0] dp2reg_mrdma_stall; +wire dp2reg_mrdma_stall_dec; +assign cmd_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_process <= 1'b0; + end else begin + if (op_load) begin + cmd_process <= 1'b1; + end else if (cmd_done) begin + cmd_process <= 1'b0; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !cmd_process && cmd_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// Address catenate and offset calc +//============== +//============== +// CFG value calculation +//============== +assign cfg_base_addr = reg2dp_src_base_addr_low; +assign cfg_line_stride = {reg2dp_src_line_stride}; +assign cfg_surf_stride = {reg2dp_src_surface_stride}; +assign cfg_di_int8 = reg2dp_in_precision == 0 ; +assign cfg_di_int16 = reg2dp_in_precision == 1 ; +assign cfg_do_int8 = reg2dp_proc_precision == 0 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_mode_multi_batch = reg2dp_batch_number!=0; +//============== +// CHANNEL Direction +// calculate how many 32x8 blocks in channel direction +//============== +always @( + reg2dp_channel + or cfg_di_int8 + or cfg_di_int16 + ) begin + if (cfg_di_int8) begin + size_of_surf = {1'b0,reg2dp_channel[12:3]}; + end else if (cfg_di_int16) begin + size_of_surf = reg2dp_channel[12:3 -1]; + end else begin + size_of_surf = reg2dp_channel[12:3 -1]; + end +end +//================================================= +// Cube Shape +//================================================= +assign is_batch_end = is_last_b; +assign is_elem_end = is_batch_end; +assign is_line_end = is_elem_end ; +assign is_surf_end = is_line_end & ( (cfg_mode_1x1_pack) || (is_last_h) ); +assign is_cube_end = is_surf_end & ( (cfg_mode_1x1_pack) || (is_last_c) ); +assign is_last_b = 1'b1; +//============== +// CHANNEL Count: +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {(14-3){1'b0}}; + end else begin + if (cmd_accept) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1'b1; + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +//============== +// LINE Count: +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1'b1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_height); +//========================================== +// DMA Req : ADDR PREPARE +//========================================== +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {(32 -3){1'b0}}; + mon_base_addr_line_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_line <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + cfg_surf_stride; + end else if (is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + cfg_line_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"MRDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_surf <= {(32 -3){1'b0}}; + mon_base_addr_surf_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_surf <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + cfg_surf_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"MRDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//========================================== +// DMA Req : Addr : Generation +//========================================== +assign req_addr = base_addr_line; +assign dma_req_addr = {req_addr,{3{1'b0}}}; +//============== +// DMA Req : SIZE : Generation +//============== +// in 1x1_pack mode, only send one request out +assign mode_1x1_req_size = size_of_surf; +always @( + cfg_mode_1x1_pack + or mode_1x1_req_size + or reg2dp_width + ) begin + if (cfg_mode_1x1_pack) begin + dma_req_size = {{(3 +1){1'b0}}, mode_1x1_req_size}; + end + else begin + dma_req_size = {{2{1'b0}}, reg2dp_width}; + end +end +assign ig2eg_size = dma_req_size; +assign ig2eg_cube_end = is_cube_end; +assign ig2cq_pd[12:0] = ig2eg_size[12:0]; +assign ig2cq_pd[13] = ig2eg_cube_end ; +assign ig2cq_pvld = cmd_process & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, (ig2cq_pvld & ig2cq_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = cmd_process & ig2cq_prdy; +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[47 -1:32] = dma_req_size[14:0]; +assign dma_rd_req_ram_type = reg2dp_src_ram_type; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// PERF STATISTIC +//============== +assign mrdma_rd_stall_cnt_inc = dma_rd_req_vld & !dma_rd_req_rdy; +assign mrdma_rd_stall_cnt_clr = op_load; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mrdma_rd_stall_cnt_cen <= 1'b0; + end else begin + if ((op_load) == 1'b1) begin + mrdma_rd_stall_cnt_cen <= reg2dp_perf_dma_en; +//end else if ((op_load) == 1'b0) begin +//end else begin +// mrdma_rd_stall_cnt_cen <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(op_load))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_mrdma_stall_dec = 1'b0; +// stl adv logic +always @( + mrdma_rd_stall_cnt_inc + or dp2reg_mrdma_stall_dec + ) begin + stl_adv = mrdma_rd_stall_cnt_inc ^ dp2reg_mrdma_stall_dec; +end +// stl cnt logic +always @( + stl_cnt_cur + or mrdma_rd_stall_cnt_inc + or dp2reg_mrdma_stall_dec + or stl_adv + or mrdma_rd_stall_cnt_clr + ) begin + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (mrdma_rd_stall_cnt_inc && !dp2reg_mrdma_stall_dec)? stl_cnt_inc : (!mrdma_rd_stall_cnt_inc && dp2reg_mrdma_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (mrdma_rd_stall_cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (mrdma_rd_stall_cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @( + stl_cnt_cur + ) begin + dp2reg_mrdma_stall[31:0] = stl_cnt_cur[31:0]; +end +//============== +// FUNCTION POINT +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property sdp_mrdma_ig__access_CVIF__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((dma_rd_req_vld) && nvdla_core_rstn) |-> (dma_rd_req_ram_type==0); + endproperty +// Cover 0 : "dma_rd_req_ram_type==0" + FUNCPOINT_sdp_mrdma_ig__access_CVIF__0_COV : cover property (sdp_mrdma_ig__access_CVIF__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property sdp_mrdma_ig__access_MCIF__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((dma_rd_req_vld) && nvdla_core_rstn) |-> (dma_rd_req_ram_type==1); + endproperty +// Cover 1 : "dma_rd_req_ram_type==1" + FUNCPOINT_sdp_mrdma_ig__access_MCIF__1_COV : cover property (sdp_mrdma_ig__access_MCIF__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_SDP_MRDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_cq.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_cq.v new file mode 100644 index 0000000..d6e19dd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_cq.v @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_NRDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_NRDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [15:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [15:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] ig2cq_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 8'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [7:0] ig2cq_adr; // current write address +wire [7:0] cq2eg_adr_p; // read address to use for ram +wire [15:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x16 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (ig2cq_adr == 8'd159) ? 8'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] cq2eg_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (cq2eg_adr == 8'd159) ? 8'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [7:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 8'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_cq_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_NRDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_NRDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_cq.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_cq.v.vcp new file mode 100644 index 0000000..d6e19dd --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_cq.v.vcp @@ -0,0 +1,367 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_NRDMA_cq.v +`include "simulate_x_tick.vh" +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_NRDMA_cq ( + nvdla_core_clk + , nvdla_core_rstn + , ig2cq_prdy + , ig2cq_pvld + , ig2cq_pd + , cq2eg_prdy + , cq2eg_pvld + , cq2eg_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output ig2cq_prdy; +input ig2cq_pvld; +input [15:0] ig2cq_pd; +input cq2eg_prdy; +output cq2eg_pvld; +output [15:0] cq2eg_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg ig2cq_busy_int; // copy for internal use +assign ig2cq_prdy = !ig2cq_busy_int; +assign wr_reserving = ig2cq_pvld && !ig2cq_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] ig2cq_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? ig2cq_count : (ig2cq_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (ig2cq_count + 1'd1) : ig2cq_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire ig2cq_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check ig2cq_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_busy_int <= 1'b0; + ig2cq_count <= 8'd0; + end else begin + ig2cq_busy_int <= ig2cq_busy_next; + if ( wr_reserving ^ wr_popping ) begin + ig2cq_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + ig2cq_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as ig2cq_pvld +// +// RAM +// +reg [7:0] ig2cq_adr; // current write address +wire [7:0] cq2eg_adr_p; // read address to use for ram +wire [15:0] cq2eg_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x16 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( ig2cq_adr ) + , .we ( wr_pushing ) + , .di ( ig2cq_pd ) + , .ra ( cq2eg_adr_p ) + , .re ( rd_enable ) + , .dout ( cq2eg_pd_p ) + , .ore ( ore ) + ); +// next ig2cq_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (ig2cq_adr == 8'd159) ? 8'd0 : (ig2cq_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + ig2cq_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + ig2cq_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + ig2cq_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] cq2eg_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (cq2eg_adr == 8'd159) ? 8'd0 : (cq2eg_adr + 1'd1); // spyglass disable W484 +assign cq2eg_adr_p = rd_popping ? rd_adr_next : cq2eg_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + cq2eg_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cq2eg_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg cq2eg_pvld_p; // data out of fifo is valid +reg cq2eg_pvld_int; // internal copy of cq2eg_pvld +assign cq2eg_pvld = cq2eg_pvld_int; +assign rd_popping = cq2eg_pvld_p && !(cq2eg_pvld_int && !cq2eg_prdy); +reg [7:0] cq2eg_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? cq2eg_count_p : + (cq2eg_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (cq2eg_count_p + 1'd1) : + cq2eg_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~cq2eg_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_count_p <= 8'd0; + cq2eg_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + cq2eg_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + cq2eg_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cq2eg_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (cq2eg_pvld_p || (cq2eg_pvld_int && !cq2eg_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cq2eg_pvld_int <= 1'b0; + end else begin + cq2eg_pvld_int <= rd_req_next; + end +end +assign cq2eg_pd = cq2eg_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (ig2cq_pvld && !ig2cq_busy_int) || (ig2cq_busy_int != ig2cq_busy_next)) || (rd_pushing || rd_popping || (cq2eg_pvld_int && cq2eg_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_cq_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_cq_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_cq_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_NRDMA_cq_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, ig2cq_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_cq") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_NRDMA_cq diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v new file mode 100644 index 0000000..d29306a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_NRDMA_gate.v +module NV_NVDLA_SDP_NRDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nrdma_disable + ,nrdma_slcg_op_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nrdma_disable; +input nrdma_slcg_op_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg nrdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when NRDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nrdma_enable <= 1'b0; + end else begin + nrdma_enable <= !nrdma_disable; + end +end +assign cfg_clk_en = nrdma_slcg_op_en & nrdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_NRDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v.vcp new file mode 100644 index 0000000..d29306a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_gate.v.vcp @@ -0,0 +1,398 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_NRDMA_gate.v +module NV_NVDLA_SDP_NRDMA_gate ( + nvdla_core_clk + ,nvdla_core_rstn + ,dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nrdma_disable + ,nrdma_slcg_op_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nrdma_disable; +input nrdma_slcg_op_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +reg nrdma_enable; +wire cfg_clk_en; +//======================================= +//CLock Gating: when NRDMA_MODE = NONE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nrdma_enable <= 1'b0; + end else begin + nrdma_enable <= !nrdma_disable; + end +end +assign cfg_clk_en = nrdma_slcg_op_en & nrdma_enable; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_NRDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_NRDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_lat_fifo.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_lat_fifo.v new file mode 100644 index 0000000..35ec72c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_lat_fifo.v @@ -0,0 +1,606 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_NRDMA_lat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_NRDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] lat_wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 8'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [7:0] lat_wr_adr; // current write address +wire [7:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (lat_wr_adr == 8'd159) ? 8'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] lat_rd_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (lat_rd_adr == 8'd159) ? 8'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [7:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 8'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_NRDMA_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_lat_fifo.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_lat_fifo.v.vcp new file mode 100644 index 0000000..35ec72c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_NRDMA_lat_fifo.v.vcp @@ -0,0 +1,606 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_NRDMA_lat_fifo.v +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_NRDMA_lat_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , lat_wr_prdy + , lat_wr_pvld +`ifdef FV_RAND_WR_PAUSE + , lat_wr_pause +`endif + , lat_wr_pd + , lat_rd_prdy + , lat_rd_pvld + , lat_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output lat_wr_prdy; +input lat_wr_pvld; +`ifdef FV_RAND_WR_PAUSE +input lat_wr_pause; +`endif +input [64:0] lat_wr_pd; +input lat_rd_prdy; +output lat_rd_pvld; +output [64:0] lat_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +wire wr_pause_rand; // random stalling +`endif +`endif +// synopsys translate_on +wire wr_reserving; +reg lat_wr_busy_int; // copy for internal use +assign lat_wr_prdy = !lat_wr_busy_int; +assign wr_reserving = lat_wr_pvld && !lat_wr_busy_int; // reserving write space? +reg wr_popping; // fwd: write side sees pop? +reg [7:0] lat_wr_count; // write-side count +wire [7:0] wr_count_next_wr_popping = wr_reserving ? lat_wr_count : (lat_wr_count - 1'd1); // spyglass disable W164a W484 +wire [7:0] wr_count_next_no_wr_popping = wr_reserving ? (lat_wr_count + 1'd1) : lat_wr_count; // spyglass disable W164a W484 +wire [7:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_160 = ( wr_count_next_no_wr_popping == 8'd160 ); +wire wr_count_next_is_160 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_160; +wire [7:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [7:0] wr_limit_reg = wr_limit_muxed; +`ifdef FV_RAND_WR_PAUSE +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) || lat_wr_pause; +// VCS coverage on +`else +// VCS coverage off +wire lat_wr_busy_next = wr_count_next_is_160 || // busy next cycle? + (wr_limit_reg != 8'd0 && // check lat_wr_limit if != 0 + wr_count_next >= wr_limit_reg) +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || wr_pause_rand + `endif + `endif +// synopsys translate_on +; +// VCS coverage on +`endif +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_busy_int <= 1'b0; + lat_wr_count <= 8'd0; + end else begin + lat_wr_busy_int <= lat_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + lat_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + lat_wr_count <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as lat_wr_pvld +// +// RAM +// +reg [7:0] lat_wr_adr; // current write address +wire [7:0] lat_rd_adr_p; // read address to use for ram +wire [64:0] lat_rd_pd_p; // read data directly out of ram +wire rd_enable; +wire ore; +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +nv_ram_rwsp_160x65 #(`FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) ram ( + .clk ( nvdla_core_clk ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .wa ( lat_wr_adr ) + , .we ( wr_pushing ) + , .di ( lat_wr_pd ) + , .ra ( lat_rd_adr_p ) + , .re ( rd_enable ) + , .dout ( lat_rd_pd_p ) + , .ore ( ore ) + ); +// next lat_wr_adr if wr_pushing=1 +wire [7:0] wr_adr_next = (lat_wr_adr == 8'd159) ? 8'd0 : (lat_wr_adr + 1'd1); // spyglass disable W484 +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_wr_adr <= 8'd0; + end else begin + if ( wr_pushing ) begin + lat_wr_adr <= wr_adr_next; + end +//synopsys translate_off + else if ( !(wr_pushing) ) begin + end else begin + lat_wr_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +wire rd_popping; // read side doing pop this cycle? +reg [7:0] lat_rd_adr; // current read address +// next read address +wire [7:0] rd_adr_next = (lat_rd_adr == 8'd159) ? 8'd0 : (lat_rd_adr + 1'd1); // spyglass disable W484 +assign lat_rd_adr_p = rd_popping ? rd_adr_next : lat_rd_adr; // for ram +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_adr <= 8'd0; + end else begin + if ( rd_popping ) begin + lat_rd_adr <= rd_adr_next; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + lat_rd_adr <= {8{`x_or_0}}; + end +//synopsys translate_on + end +end +// spyglass enable_block W484 +// +// SYNCHRONOUS BOUNDARY +// +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_popping <= 1'b0; + end else begin + wr_popping <= rd_popping; + end +end +reg rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + rd_pushing <= 1'b0; + end else begin + rd_pushing <= wr_pushing; // let data go into ram first + end +end +// +// READ SIDE +// +reg lat_rd_pvld_p; // data out of fifo is valid +reg lat_rd_pvld_int; // internal copy of lat_rd_pvld +assign lat_rd_pvld = lat_rd_pvld_int; +assign rd_popping = lat_rd_pvld_p && !(lat_rd_pvld_int && !lat_rd_prdy); +reg [7:0] lat_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [7:0] rd_count_p_next_rd_popping = rd_pushing ? lat_rd_count_p : + (lat_rd_count_p - 1'd1); +wire [7:0] rd_count_p_next_no_rd_popping = rd_pushing ? (lat_rd_count_p + 1'd1) : + lat_rd_count_p; +// spyglass enable_block W164a W484 +wire [7:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +wire rd_count_p_next_rd_popping_not_0 = rd_count_p_next_rd_popping != 0; +wire rd_count_p_next_no_rd_popping_not_0 = rd_count_p_next_no_rd_popping != 0; +wire rd_count_p_next_not_0 = rd_popping ? rd_count_p_next_rd_popping_not_0 : + rd_count_p_next_no_rd_popping_not_0; +assign rd_enable = ((rd_count_p_next_not_0) && ((~lat_rd_pvld_p) || rd_popping)); // anytime data's there and not stalled +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_count_p <= 8'd0; + lat_rd_pvld_p <= 1'b0; + end else begin + if ( rd_pushing || rd_popping ) begin + lat_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_count_p <= {8{`x_or_0}}; + end +//synopsys translate_on + if ( rd_pushing || rd_popping ) begin + lat_rd_pvld_p <= (rd_count_p_next_not_0); + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + lat_rd_pvld_p <= `x_or_0; + end +//synopsys translate_on + end +end +wire rd_req_next = (lat_rd_pvld_p || (lat_rd_pvld_int && !lat_rd_prdy)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + lat_rd_pvld_int <= 1'b0; + end else begin + lat_rd_pvld_int <= rd_req_next; + end +end +assign lat_rd_pd = lat_rd_pd_p; +assign ore = rd_popping; +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg wr_pause_rand_dly; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + wr_pause_rand_dly <= 1'b0; + end else begin + wr_pause_rand_dly <= wr_pause_rand; + end +end +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || rd_popping || wr_popping || (lat_wr_pvld && !lat_wr_busy_int) || (lat_wr_busy_int != lat_wr_busy_next)) || (rd_pushing || rd_popping || (lat_rd_pvld_int && lat_rd_prdy) || wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled || (wr_pause_rand != wr_pause_rand_dly) + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit : 8'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 8'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 8'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 8'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [7:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 8'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// Random Write-Side Stalling +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +// leda W339 OFF -- Non synthesizable operator +// leda W372 OFF -- Undefined PLI task +// leda W373 OFF -- Undefined PLI function +// leda W599 OFF -- This construct is not supported by Synopsys +// leda W430 OFF -- Initial statement is not synthesizable +// leda W182 OFF -- Illegal statement for synthesis +// leda W639 OFF -- For synthesis, operands of a division or modulo operation need to be constants +// leda DCVER_274_NV OFF -- This system task is not supported by DC +integer stall_probability; // prob of stalling +integer stall_cycles_min; // min cycles to stall +integer stall_cycles_max; // max cycles to stall +integer stall_cycles_left; // stall cycles left +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + stall_probability = 0; // no stalling by default + stall_cycles_min = 1; + stall_cycles_max = 10; +`ifdef NO_PLI +`else + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_probability" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_probability=%d", stall_probability); + end else if ( $test$plusargs( "default_fifo_stall_probability" ) ) begin + $value$plusargs( "default_fifo_stall_probability=%d", stall_probability); + end + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_min=%d", stall_cycles_min); + end else if ( $test$plusargs( "default_fifo_stall_cycles_min" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_min=%d", stall_cycles_min); + end + if ( $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_max=%d", stall_cycles_max); + end else if ( $test$plusargs( "default_fifo_stall_cycles_max" ) ) begin + $value$plusargs( "default_fifo_stall_cycles_max=%d", stall_cycles_max); + end +`endif + if ( stall_cycles_min < 1 ) begin + stall_cycles_min = 1; + end + if ( stall_cycles_min > stall_cycles_max ) begin + stall_cycles_max = stall_cycles_min; + end +end +`ifdef NO_PLI +`else +// randomization globals +`ifdef SIMTOP_RANDOMIZE_STALLS + always @( `SIMTOP_RANDOMIZE_STALLS.global_stall_event ) begin + if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_probability" ) ) stall_probability = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_probability; + if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_min" ) ) stall_cycles_min = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_min; + if ( ! $test$plusargs( "NV_NVDLA_SDP_NRDMA_lat_fifo_fifo_stall_cycles_max" ) ) stall_cycles_max = `SIMTOP_RANDOMIZE_STALLS.global_stall_fifo_cycles_max; + end +`endif +`endif +always @( negedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + stall_cycles_left <= 0; + end else begin +`ifdef NO_PLI + stall_cycles_left <= 0; +`else + if ( lat_wr_pvld && !(!lat_wr_prdy) + && stall_probability != 0 ) begin + if ( prand_inst4(1, 100) <= stall_probability ) begin + stall_cycles_left <= prand_inst5(stall_cycles_min, stall_cycles_max); + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end + end else if ( stall_cycles_left !== 0 ) begin + stall_cycles_left <= stall_cycles_left - 1; + end +`endif + end +end +assign wr_pause_rand = (stall_cycles_left !== 0) ; +// VCS coverage on +`endif +`endif +// synopsys translate_on +// VCS coverage on +// leda W339 ON +// leda W372 ON +// leda W373 ON +// leda W599 ON +// leda W430 ON +// leda W182 ON +// leda W639 ON +// leda DCVER_274_NV ON +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {24'd0, (wr_limit_reg == 8'd0) ? 8'd160 : wr_limit_reg} ) + , .curr ( {24'd0, lat_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_NRDMA_lat_fifo") true +// synopsys dc_script_end +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed4; +reg prand_initialized4; +reg prand_no_rollpli4; +`endif +`endif +`endif +function [31:0] prand_inst4; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst4 = min; +`else +`ifdef SYNTHESIS + prand_inst4 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized4 !== 1'b1) begin + prand_no_rollpli4 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli4) + prand_local_seed4 = {$prand_get_seed(4), 16'b0}; + prand_initialized4 = 1'b1; + end + if (prand_no_rollpli4) begin + prand_inst4 = min; + end else begin + diff = max - min + 1; + prand_inst4 = min + prand_local_seed4[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed4 = prand_local_seed4 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst4 = min; +`else + prand_inst4 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +`ifdef SYNTH_LEVEL1_COMPILE +`else +`ifdef SYNTHESIS +`else +`ifdef PRAND_VERILOG +// Only verilog needs any local variables +reg [47:0] prand_local_seed5; +reg prand_initialized5; +reg prand_no_rollpli5; +`endif +`endif +`endif +function [31:0] prand_inst5; +//VCS coverage off + input [31:0] min; + input [31:0] max; + reg [32:0] diff; + begin +`ifdef SYNTH_LEVEL1_COMPILE + prand_inst5 = min; +`else +`ifdef SYNTHESIS + prand_inst5 = min; +`else +`ifdef PRAND_VERILOG + if (prand_initialized5 !== 1'b1) begin + prand_no_rollpli5 = $test$plusargs("NO_ROLLPLI"); + if (!prand_no_rollpli5) + prand_local_seed5 = {$prand_get_seed(5), 16'b0}; + prand_initialized5 = 1'b1; + end + if (prand_no_rollpli5) begin + prand_inst5 = min; + end else begin + diff = max - min + 1; + prand_inst5 = min + prand_local_seed5[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) + prand_local_seed5 = prand_local_seed5 * 48'h5deece66d + 48'd11; + end +`else +`ifdef PRAND_OFF + prand_inst5 = min; +`else + prand_inst5 = $RollPLI(min, max, "auto"); +`endif +`endif +`endif +`endif + end +//VCS coverage on +endfunction +endmodule // NV_NVDLA_SDP_NRDMA_lat_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v new file mode 100644 index 0000000..4c88702 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v @@ -0,0 +1,1117 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_EG_ro.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_RDMA_EG_ro ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,cfg_dp_8 //|< i + ,cfg_dp_size_1byte //|< i + ,cfg_mode_per_element //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,rod0_wr_pd //|< i + ,rod1_wr_pd //|< i + ,rod2_wr_pd //|< i + ,rod3_wr_pd //|< i + ,rod_wr_mask //|< i + ,rod_wr_vld //|< i + ,rod_wr_rdy //|> o + ,roc_wr_pd //|< i + ,roc_wr_vld //|< i + ,roc_wr_rdy //|> o + ,layer_end //|> o + ,sdp_rdma2dp_pd //|> o + ,sdp_rdma2dp_valid //|> o + ,sdp_rdma2dp_ready //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output sdp_rdma2dp_valid; +input sdp_rdma2dp_ready; +output [8*16:0] sdp_rdma2dp_pd; +input [8*8 -1:0] rod0_wr_pd; +input [8*8 -1:0] rod1_wr_pd; +input [8*8 -1:0] rod2_wr_pd; +input [8*8 -1:0] rod3_wr_pd; +input [3:0] rod_wr_mask; +input rod_wr_vld; +output rod_wr_rdy; +input [1:0] roc_wr_pd; +input roc_wr_vld; +output roc_wr_rdy; +input cfg_dp_8; +input cfg_dp_size_1byte; +input cfg_mode_per_element; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +output layer_end; +wire [2:0] size_of_beat; +wire [12:0] size_of_width; +wire [13-3:0] size_of_surf; +reg [1:0] beat_cnt; +wire [2:0] beat_cnt_nxt; +reg mon_beat_cnt; +reg [12:0] count_h; +reg [12:0] count_w; +reg [13-3:0] count_c; +wire is_last_beat; +wire is_cube_end; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +reg roc_rd_en; +wire [1:0] roc_rd_pd; +wire roc_rd_prdy; +wire roc_rd_pvld; +reg rodx_rd_en; +wire [8*8 -1:0] rod0_rd_pd; +wire rod0_rd_prdy; +wire rod0_rd_pvld; +wire rod0_wr_prdy; +wire rod0_wr_pvld; +wire [8*8 -1:0] rod1_rd_pd; +wire rod1_rd_prdy; +wire rod1_rd_pvld; +wire rod1_wr_prdy; +wire rod1_wr_pvld; +wire [8*8 -1:0] rod2_rd_pd; +wire rod2_rd_prdy; +wire rod2_rd_pvld; +wire rod2_wr_prdy; +wire rod2_wr_pvld; +wire [8*8 -1:0] rod3_rd_pd; +wire rod3_rd_prdy; +wire rod3_rd_pvld; +wire rod3_wr_prdy; +wire rod3_wr_pvld; +wire [1:0] rod_sel; +wire rod0_sel; +wire rod1_sel; +wire rod2_sel; +wire rod3_sel; +reg [8*8 -1:0] out_data_1bpe; +wire [8*16 -1:0] out_data_1bpe_ext; +reg [8*16 -1:0] out_data_2bpe; +reg out_vld_1bpe; +reg out_vld_2bpe; +wire out_accept; +wire out_rdy; +wire out_vld; +wire [8*16:0] out_pd; +//======================================================= +// DATA FIFO: WRITE SIDE +//======================================================= +assign rod_wr_rdy = ~(rod_wr_mask[0] & ~rod0_wr_prdy |rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod0_wr_pvld = rod_wr_vld & rod_wr_mask[0] & ~(rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod1_wr_pvld = rod_wr_vld & rod_wr_mask[1] & ~(rod_wr_mask[0] & ~rod0_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod2_wr_pvld = rod_wr_vld & rod_wr_mask[2] & ~(rod_wr_mask[0] & ~rod0_wr_prdy | rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod3_wr_pvld = rod_wr_vld & rod_wr_mask[3] & ~(rod_wr_mask[0] & ~rod0_wr_prdy | rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod0 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod0_wr_prdy) + ,.rod_wr_pvld (rod0_wr_pvld) + ,.rod_wr_pd (rod0_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod0_rd_prdy) + ,.rod_rd_pvld (rod0_rd_pvld) + ,.rod_rd_pd (rod0_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod1_wr_prdy) + ,.rod_wr_pvld (rod1_wr_pvld) + ,.rod_wr_pd (rod1_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod1_rd_prdy) + ,.rod_rd_pvld (rod1_rd_pvld) + ,.rod_rd_pd (rod1_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod2 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod2_wr_prdy) + ,.rod_wr_pvld (rod2_wr_pvld) + ,.rod_wr_pd (rod2_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod2_rd_prdy) + ,.rod_rd_pvld (rod2_rd_pvld) + ,.rod_rd_pd (rod2_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod3 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod3_wr_prdy) + ,.rod_wr_pvld (rod3_wr_pvld) + ,.rod_wr_pd (rod3_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod3_rd_prdy) + ,.rod_rd_pvld (rod3_rd_pvld) + ,.rod_rd_pd (rod3_rd_pd[8*8 -1:0]) + ); +//======================================================= +// DATA FIFO: READ SIDE +//======================================================= +always @( + cfg_mode_per_element + or is_last_h + or is_last_w + ) begin + begin + if (cfg_mode_per_element) begin + rodx_rd_en = 1'b1; + end else begin + rodx_rd_en = is_last_h & is_last_w; + end + end +end +assign rod0_rd_prdy = out_rdy & rodx_rd_en & rod0_sel & ~(rod1_sel & ~rod1_rd_pvld); +assign rod1_rd_prdy = out_rdy & rodx_rd_en & rod1_sel & ~(rod0_sel & ~rod0_rd_pvld); +assign rod2_rd_prdy = out_rdy & rodx_rd_en & rod2_sel & ~(rod3_sel & ~rod3_rd_pvld); +assign rod3_rd_prdy = out_rdy & rodx_rd_en & rod3_sel & ~(rod2_sel & ~rod2_rd_pvld); +//============== +// CMD FIFO +//============== +// One entry in ROC indicates one entry from latency fifo +NV_NVDLA_SDP_RDMA_EG_RO_cfifo u_roc ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.roc_wr_prdy (roc_wr_rdy) + ,.roc_wr_pvld (roc_wr_vld) + ,.roc_wr_pd (roc_wr_pd[1:0]) + ,.roc_rd_prdy (roc_rd_prdy) + ,.roc_rd_pvld (roc_rd_pvld) + ,.roc_rd_pd (roc_rd_pd[1:0]) + ); +always @( + cfg_mode_per_element + or is_surf_end + or is_last_beat + ) begin + begin + roc_rd_en = is_last_beat & (is_surf_end | cfg_mode_per_element); + end +end +assign roc_rd_prdy = roc_rd_en & out_accept; +assign size_of_beat = roc_rd_pvld ? (roc_rd_pd[1:0] + 1) : 3'b0; +//============== +// END +//============== +assign is_line_end = is_last_w; +assign is_surf_end = is_line_end & is_last_h; +assign is_cube_end = is_surf_end & is_last_c; +//============== +// Width Count +//============== +assign size_of_width = reg2dp_width; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {13{1'b0}}; + end else begin + if (out_accept) begin + begin + if (is_line_end) begin + count_w <= 0; + end else begin + count_w <= count_w + 1; + end + end + end + end +end +assign is_last_w = (count_w==size_of_width); +//============== +// HEIGHT Count +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (out_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_height); +//============== +// SURF Count +//============== +assign size_of_surf = cfg_dp_8 ? {1'b0,reg2dp_channel[12:3]} : reg2dp_channel[12:3 -1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {(14-3){1'b0}}; + end else begin + if (out_accept) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1; + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +//============== +// BEAT CNT: used to foreach 1~4 16E rod FIFOs +//============== +wire [1:0] size_of_elem = (cfg_dp_size_1byte | !cfg_dp_8) ? 2'h1 : 2'h2; +assign beat_cnt_nxt = beat_cnt + size_of_elem; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_cnt,beat_cnt} <= 3'h0; + end else begin + if (out_accept) begin + if (cfg_mode_per_element) begin + if (is_last_beat) begin + {mon_beat_cnt,beat_cnt} <= 3'h0; + end else begin + {mon_beat_cnt,beat_cnt} <= beat_cnt_nxt; + end + end else if (is_surf_end) begin + if (is_last_beat) begin + {mon_beat_cnt,beat_cnt} <= 3'h0; + end else begin + {mon_beat_cnt,beat_cnt} <= beat_cnt_nxt; + end + end + end + end +end +assign is_last_beat = beat_cnt_nxt == size_of_beat; +assign rod_sel = beat_cnt; +assign rod0_sel = beat_cnt == 2'h0; +assign rod2_sel = beat_cnt == 2'h2; +assign rod1_sel = (cfg_dp_size_1byte | !cfg_dp_8)? beat_cnt == 2'h1 : beat_cnt == 2'h0; +assign rod3_sel = (cfg_dp_size_1byte | !cfg_dp_8)? beat_cnt == 2'h3 : beat_cnt == 2'h2; +////dp int8 one byte per element or int16 two bytes per elment/////////// +always @( + rod_sel + or rod0_rd_pd + or rod1_rd_pd + or rod2_rd_pd + or rod3_rd_pd + ) begin + case (rod_sel) + 2'd0: out_data_1bpe = rod0_rd_pd; + 2'd1: out_data_1bpe = rod1_rd_pd; + 2'd2: out_data_1bpe = rod2_rd_pd; + 2'd3: out_data_1bpe = rod3_rd_pd; + default : out_data_1bpe[8*8 -1:0] = {8*8{`x_or_0}}; + endcase +end +always @( + rod_sel + or rod0_rd_pvld + or rod1_rd_pvld + or rod2_rd_pvld + or rod3_rd_pvld + ) begin + case (rod_sel) + 2'd0: out_vld_1bpe = rod0_rd_pvld; + 2'd1: out_vld_1bpe = rod1_rd_pvld; + 2'd2: out_vld_1bpe = rod2_rd_pvld; + 2'd3: out_vld_1bpe = rod3_rd_pvld; + default : out_vld_1bpe = {1{`x_or_0}}; + endcase +end +//: my $m = 8; +//: foreach my $i (0..${m}-1) { +//: print "assign out_data_1bpe_ext[16*${i}+15:16*${i}] = {{8{out_data_1bpe[8*${i}+7]}}, out_data_1bpe[8*${i}+7:8*${i}]}; \n"; +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign out_data_1bpe_ext[16*0+15:16*0] = {{8{out_data_1bpe[8*0+7]}}, out_data_1bpe[8*0+7:8*0]}; +assign out_data_1bpe_ext[16*1+15:16*1] = {{8{out_data_1bpe[8*1+7]}}, out_data_1bpe[8*1+7:8*1]}; +assign out_data_1bpe_ext[16*2+15:16*2] = {{8{out_data_1bpe[8*2+7]}}, out_data_1bpe[8*2+7:8*2]}; +assign out_data_1bpe_ext[16*3+15:16*3] = {{8{out_data_1bpe[8*3+7]}}, out_data_1bpe[8*3+7:8*3]}; +assign out_data_1bpe_ext[16*4+15:16*4] = {{8{out_data_1bpe[8*4+7]}}, out_data_1bpe[8*4+7:8*4]}; +assign out_data_1bpe_ext[16*5+15:16*5] = {{8{out_data_1bpe[8*5+7]}}, out_data_1bpe[8*5+7:8*5]}; +assign out_data_1bpe_ext[16*6+15:16*6] = {{8{out_data_1bpe[8*6+7]}}, out_data_1bpe[8*6+7:8*6]}; +assign out_data_1bpe_ext[16*7+15:16*7] = {{8{out_data_1bpe[8*7+7]}}, out_data_1bpe[8*7+7:8*7]}; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +////dp int8 two byte per element/////////// +always @( + rod_sel + or rod0_rd_pd + or rod1_rd_pd + or rod2_rd_pd + or rod3_rd_pd + ) begin + case (rod_sel) + 2'd0: out_data_2bpe = {rod1_rd_pd,rod0_rd_pd}; + 2'd2: out_data_2bpe = {rod3_rd_pd,rod2_rd_pd}; + default : out_data_2bpe[8*16 -1:0] = {8*16{`x_or_0}}; + endcase +end +always @( + rod_sel + or rod0_rd_pvld + or rod1_rd_pvld + or rod2_rd_pvld + or rod3_rd_pvld + ) begin + case (rod_sel) + 2'd0: out_vld_2bpe = rod1_rd_pvld & rod0_rd_pvld; + 2'd2: out_vld_2bpe = rod3_rd_pvld & rod2_rd_pvld; + default : out_vld_2bpe = {1{`x_or_0}}; + endcase +end +////mux out data //// +assign out_vld = (cfg_dp_size_1byte | !cfg_dp_8) ? out_vld_1bpe : out_vld_2bpe; +assign out_pd[8*16 -1:0] = !cfg_dp_8 ? {{8*8{1'b0}},out_data_1bpe[8*8 -1:0]} : cfg_dp_size_1byte ? out_data_1bpe_ext[8*16 -1:0] : out_data_2bpe[8*16 -1:0]; +assign out_pd[8*16] = is_cube_end; +assign out_accept = out_vld & out_rdy; +NV_NVDLA_SDP_RDMA_EG_RO_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.out_pd (out_pd[8*16:0]) //|< w + ,.out_vld (out_vld) //|< r + ,.out_rdy (out_rdy) //|> w + ,.sdp_rdma2dp_ready (sdp_rdma2dp_ready) //|< i + ,.sdp_rdma2dp_pd (sdp_rdma2dp_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_valid (sdp_rdma2dp_valid) //|> o + ); +assign layer_end = sdp_rdma2dp_valid & sdp_rdma2dp_ready & sdp_rdma2dp_pd[8*16]; +endmodule // NV_NVDLA_SDP_RDMA_EG_ro +// ************************************************************************************************************** +// Generated by ::pipe -m -bc sdp_rdma2dp_pd (sdp_rdma2dp_valid,sdp_rdma2dp_ready) <= out_pd[8*8:0] (out_vld, out_rdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_RDMA_EG_RO_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,out_pd + ,out_vld + ,out_rdy + ,sdp_rdma2dp_ready + ,sdp_rdma2dp_pd + ,sdp_rdma2dp_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input out_vld; +output out_rdy; +input [8*16:0] out_pd; +output [8*16:0] sdp_rdma2dp_pd; +output sdp_rdma2dp_valid; +input sdp_rdma2dp_ready; +//: my $dw = 1 + 8*16; +//: &eperl::pipe("-is -wid $dw -do sdp_rdma2dp_pd -vo sdp_rdma2dp_valid -ri sdp_rdma2dp_ready -di out_pd -vi out_vld -ro out_rdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg out_rdy; +reg skid_flop_out_rdy; +reg skid_flop_out_vld; +reg [129-1:0] skid_flop_out_pd; +reg pipe_skid_out_vld; +reg [129-1:0] pipe_skid_out_pd; +// Wire +wire skid_out_vld; +wire [129-1:0] skid_out_pd; +wire skid_out_rdy; +wire pipe_skid_out_rdy; +wire sdp_rdma2dp_valid; +wire [129-1:0] sdp_rdma2dp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + out_rdy <= 1'b1; + skid_flop_out_rdy <= 1'b1; + end else begin + out_rdy <= skid_out_rdy; + skid_flop_out_rdy <= skid_out_rdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_out_vld <= 1'b0; + end else begin + if (skid_flop_out_rdy) begin + skid_flop_out_vld <= out_vld; + end + end +end +assign skid_out_vld = (skid_flop_out_rdy) ? out_vld : skid_flop_out_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_out_rdy & out_vld) begin + skid_flop_out_pd[129-1:0] <= out_pd[129-1:0]; + end +end +assign skid_out_pd[129-1:0] = (skid_flop_out_rdy) ? out_pd[129-1:0] : skid_flop_out_pd[129-1:0]; + + +// PIPE READY +assign skid_out_rdy = pipe_skid_out_rdy || !pipe_skid_out_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_out_vld <= 1'b0; + end else begin + if (skid_out_rdy) begin + pipe_skid_out_vld <= skid_out_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_out_rdy && skid_out_vld) begin + pipe_skid_out_pd[129-1:0] <= skid_out_pd[129-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_out_rdy = sdp_rdma2dp_ready; +assign sdp_rdma2dp_valid = pipe_skid_out_vld; +assign sdp_rdma2dp_pd = pipe_skid_out_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_RDMA_EG_RO_pipe_p1 +module NV_NVDLA_SDP_RDMA_EG_RO_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , rod_wr_prdy + , rod_wr_pvld + , rod_wr_pd + , rod_rd_prdy + , rod_rd_pvld + , rod_rd_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output rod_wr_prdy; +input rod_wr_pvld; +input [8*8 -1:0] rod_wr_pd; +input rod_rd_prdy; +output rod_rd_pvld; +output [8*8 -1:0] rod_rd_pd; +//: my $dw = 8*8; +//: &eperl::pipe("-is -wid $dw -do rod_rd_pd -vo rod_rd_pvld -ri rod_rd_prdy -di rod_wr_pd -vi rod_wr_pvld -ro rod_wr_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg rod_wr_prdy; +reg skid_flop_rod_wr_prdy; +reg skid_flop_rod_wr_pvld; +reg [64-1:0] skid_flop_rod_wr_pd; +reg pipe_skid_rod_wr_pvld; +reg [64-1:0] pipe_skid_rod_wr_pd; +// Wire +wire skid_rod_wr_pvld; +wire [64-1:0] skid_rod_wr_pd; +wire skid_rod_wr_prdy; +wire pipe_skid_rod_wr_prdy; +wire rod_rd_pvld; +wire [64-1:0] rod_rd_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + rod_wr_prdy <= 1'b1; + skid_flop_rod_wr_prdy <= 1'b1; + end else begin + rod_wr_prdy <= skid_rod_wr_prdy; + skid_flop_rod_wr_prdy <= skid_rod_wr_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_rod_wr_pvld <= 1'b0; + end else begin + if (skid_flop_rod_wr_prdy) begin + skid_flop_rod_wr_pvld <= rod_wr_pvld; + end + end +end +assign skid_rod_wr_pvld = (skid_flop_rod_wr_prdy) ? rod_wr_pvld : skid_flop_rod_wr_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_rod_wr_prdy & rod_wr_pvld) begin + skid_flop_rod_wr_pd[64-1:0] <= rod_wr_pd[64-1:0]; + end +end +assign skid_rod_wr_pd[64-1:0] = (skid_flop_rod_wr_prdy) ? rod_wr_pd[64-1:0] : skid_flop_rod_wr_pd[64-1:0]; + + +// PIPE READY +assign skid_rod_wr_prdy = pipe_skid_rod_wr_prdy || !pipe_skid_rod_wr_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_rod_wr_pvld <= 1'b0; + end else begin + if (skid_rod_wr_prdy) begin + pipe_skid_rod_wr_pvld <= skid_rod_wr_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_rod_wr_prdy && skid_rod_wr_pvld) begin + pipe_skid_rod_wr_pd[64-1:0] <= skid_rod_wr_pd[64-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_rod_wr_prdy = rod_rd_prdy; +assign rod_rd_pvld = pipe_skid_rod_wr_pvld; +assign rod_rd_pd = pipe_skid_rod_wr_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_RDMA_EG_RO_cfifo ( + nvdla_core_clk + , nvdla_core_rstn + , roc_wr_prdy + , roc_wr_pvld + , roc_wr_pd + , roc_rd_prdy + , roc_rd_pvld + , roc_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output roc_wr_prdy; +input roc_wr_pvld; +input [1:0] roc_wr_pd; +input roc_rd_prdy; +output roc_rd_pvld; +output [1:0] roc_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg roc_wr_busy_int; // copy for internal use +assign roc_wr_prdy = !roc_wr_busy_int; +assign wr_reserving = roc_wr_pvld && !roc_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] roc_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? roc_wr_count : (roc_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (roc_wr_count + 1'd1) : roc_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire roc_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check roc_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_wr_busy_int <= 1'b0; + roc_wr_count <= 3'd0; + end else begin + roc_wr_busy_int <= roc_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + roc_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + roc_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as roc_wr_pvld +// +// RAM +// +reg [1:0] roc_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + roc_wr_adr <= roc_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] roc_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (roc_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [1:0] roc_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( roc_wr_pd ) + , .we ( ram_we ) + , .wa ( roc_wr_adr ) + , .ra ( (roc_wr_count == 0) ? 3'd4 : {1'b0,roc_rd_adr} ) + , .dout ( roc_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = roc_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + roc_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + roc_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg roc_rd_prdy_d; // roc_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_prdy_d <= 1'b1; + end else begin + roc_rd_prdy_d <= roc_rd_prdy; + end +end +wire roc_rd_prdy_d_o; // combinatorial rd_busy +wire roc_rd_pvld_p; // data out of fifo is valid +reg roc_rd_pvld_int_o; // internal copy of roc_rd_pvld_o +wire roc_rd_pvld_o = roc_rd_pvld_int_o; +assign rd_popping = roc_rd_pvld_p && !(roc_rd_pvld_int_o && !roc_rd_prdy_d_o); +reg [2:0] roc_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? roc_rd_count_p : + (roc_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (roc_rd_count_p + 1'd1) : + roc_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign roc_rd_pvld_p = roc_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + roc_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + roc_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SKID for -rd_busy_reg +// +reg [1:0] roc_rd_pd_o; // output data register +wire rd_req_next_o = (roc_rd_pvld_p || (roc_rd_pvld_int_o && !roc_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_pvld_int_o <= 1'b0; + end else begin + roc_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + roc_rd_pd_o <= roc_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + roc_rd_pd_o <= {2{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +assign roc_rd_pd = !roc_rd_prdy_d_o ? roc_rd_pd_o : roc_rd_pd_p; // skid reg assign +reg roc_rd_pvld_d; // previous roc_rd_pvld +assign roc_rd_prdy_d_o = !(roc_rd_pvld_d && !roc_rd_prdy_d ); +assign roc_rd_pvld = !roc_rd_prdy_d_o ? roc_rd_pvld_o : roc_rd_pvld_p; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_pvld_d <= 1'b0; + end else begin + roc_rd_pvld_d <= roc_rd_pvld; + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (roc_wr_pvld && !roc_wr_busy_int) || (roc_wr_busy_int != roc_wr_busy_next)) || (rd_pushing || rd_popping || (roc_rd_pvld && roc_rd_prdy_d) || (roc_rd_pvld_int_o && roc_rd_prdy_d_o)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, roc_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_RDMA_EG_RO_cfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_RDMA_EG_RO_cfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [1:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [1:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [1:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [1:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [1:0] ram_ff0; +reg [1:0] ram_ff1; +reg [1:0] ram_ff2; +reg [1:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [1:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {2{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [1:0] Di0; +input [1:0] Ra0; +output [1:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 2'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [1:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [1:0] Q0 = mem[0]; +wire [1:0] Q1 = mem[1]; +wire [1:0] Q2 = mem[2]; +wire [1:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2] } +endmodule // vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +//vmw: Memory vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +//vmw: Address-size 2 +//vmw: Data-size 2 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[1:0] data0[1:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[1:0] data1[1:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v.vcp new file mode 100644 index 0000000..44985a6 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_EG_ro.v.vcp @@ -0,0 +1,954 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_EG_ro.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_RDMA_EG_ro ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,cfg_dp_8 //|< i + ,cfg_dp_size_1byte //|< i + ,cfg_mode_per_element //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,rod0_wr_pd //|< i + ,rod1_wr_pd //|< i + ,rod2_wr_pd //|< i + ,rod3_wr_pd //|< i + ,rod_wr_mask //|< i + ,rod_wr_vld //|< i + ,rod_wr_rdy //|> o + ,roc_wr_pd //|< i + ,roc_wr_vld //|< i + ,roc_wr_rdy //|> o + ,layer_end //|> o + ,sdp_rdma2dp_pd //|> o + ,sdp_rdma2dp_valid //|> o + ,sdp_rdma2dp_ready //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +output sdp_rdma2dp_valid; +input sdp_rdma2dp_ready; +output [8*16:0] sdp_rdma2dp_pd; +input [8*8 -1:0] rod0_wr_pd; +input [8*8 -1:0] rod1_wr_pd; +input [8*8 -1:0] rod2_wr_pd; +input [8*8 -1:0] rod3_wr_pd; +input [3:0] rod_wr_mask; +input rod_wr_vld; +output rod_wr_rdy; +input [1:0] roc_wr_pd; +input roc_wr_vld; +output roc_wr_rdy; +input cfg_dp_8; +input cfg_dp_size_1byte; +input cfg_mode_per_element; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +output layer_end; +wire [2:0] size_of_beat; +wire [12:0] size_of_width; +wire [13-3:0] size_of_surf; +reg [1:0] beat_cnt; +wire [2:0] beat_cnt_nxt; +reg mon_beat_cnt; +reg [12:0] count_h; +reg [12:0] count_w; +reg [13-3:0] count_c; +wire is_last_beat; +wire is_cube_end; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +reg roc_rd_en; +wire [1:0] roc_rd_pd; +wire roc_rd_prdy; +wire roc_rd_pvld; +reg rodx_rd_en; +wire [8*8 -1:0] rod0_rd_pd; +wire rod0_rd_prdy; +wire rod0_rd_pvld; +wire rod0_wr_prdy; +wire rod0_wr_pvld; +wire [8*8 -1:0] rod1_rd_pd; +wire rod1_rd_prdy; +wire rod1_rd_pvld; +wire rod1_wr_prdy; +wire rod1_wr_pvld; +wire [8*8 -1:0] rod2_rd_pd; +wire rod2_rd_prdy; +wire rod2_rd_pvld; +wire rod2_wr_prdy; +wire rod2_wr_pvld; +wire [8*8 -1:0] rod3_rd_pd; +wire rod3_rd_prdy; +wire rod3_rd_pvld; +wire rod3_wr_prdy; +wire rod3_wr_pvld; +wire [1:0] rod_sel; +wire rod0_sel; +wire rod1_sel; +wire rod2_sel; +wire rod3_sel; +reg [8*8 -1:0] out_data_1bpe; +wire [8*16 -1:0] out_data_1bpe_ext; +reg [8*16 -1:0] out_data_2bpe; +reg out_vld_1bpe; +reg out_vld_2bpe; +wire out_accept; +wire out_rdy; +wire out_vld; +wire [8*16:0] out_pd; +//======================================================= +// DATA FIFO: WRITE SIDE +//======================================================= +assign rod_wr_rdy = ~(rod_wr_mask[0] & ~rod0_wr_prdy |rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod0_wr_pvld = rod_wr_vld & rod_wr_mask[0] & ~(rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod1_wr_pvld = rod_wr_vld & rod_wr_mask[1] & ~(rod_wr_mask[0] & ~rod0_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod2_wr_pvld = rod_wr_vld & rod_wr_mask[2] & ~(rod_wr_mask[0] & ~rod0_wr_prdy | rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[3] & ~rod3_wr_prdy ); +assign rod3_wr_pvld = rod_wr_vld & rod_wr_mask[3] & ~(rod_wr_mask[0] & ~rod0_wr_prdy | rod_wr_mask[1] & ~rod1_wr_prdy | rod_wr_mask[2] & ~rod2_wr_prdy ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod0 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod0_wr_prdy) + ,.rod_wr_pvld (rod0_wr_pvld) + ,.rod_wr_pd (rod0_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod0_rd_prdy) + ,.rod_rd_pvld (rod0_rd_pvld) + ,.rod_rd_pd (rod0_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod1_wr_prdy) + ,.rod_wr_pvld (rod1_wr_pvld) + ,.rod_wr_pd (rod1_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod1_rd_prdy) + ,.rod_rd_pvld (rod1_rd_pvld) + ,.rod_rd_pd (rod1_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod2 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod2_wr_prdy) + ,.rod_wr_pvld (rod2_wr_pvld) + ,.rod_wr_pd (rod2_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod2_rd_prdy) + ,.rod_rd_pvld (rod2_rd_pvld) + ,.rod_rd_pd (rod2_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_RDMA_EG_RO_dfifo u_rod3 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.rod_wr_prdy (rod3_wr_prdy) + ,.rod_wr_pvld (rod3_wr_pvld) + ,.rod_wr_pd (rod3_wr_pd[8*8 -1:0]) + ,.rod_rd_prdy (rod3_rd_prdy) + ,.rod_rd_pvld (rod3_rd_pvld) + ,.rod_rd_pd (rod3_rd_pd[8*8 -1:0]) + ); +//======================================================= +// DATA FIFO: READ SIDE +//======================================================= +always @( + cfg_mode_per_element + or is_last_h + or is_last_w + ) begin + begin + if (cfg_mode_per_element) begin + rodx_rd_en = 1'b1; + end else begin + rodx_rd_en = is_last_h & is_last_w; + end + end +end +assign rod0_rd_prdy = out_rdy & rodx_rd_en & rod0_sel & ~(rod1_sel & ~rod1_rd_pvld); +assign rod1_rd_prdy = out_rdy & rodx_rd_en & rod1_sel & ~(rod0_sel & ~rod0_rd_pvld); +assign rod2_rd_prdy = out_rdy & rodx_rd_en & rod2_sel & ~(rod3_sel & ~rod3_rd_pvld); +assign rod3_rd_prdy = out_rdy & rodx_rd_en & rod3_sel & ~(rod2_sel & ~rod2_rd_pvld); +//============== +// CMD FIFO +//============== +// One entry in ROC indicates one entry from latency fifo +NV_NVDLA_SDP_RDMA_EG_RO_cfifo u_roc ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.roc_wr_prdy (roc_wr_rdy) + ,.roc_wr_pvld (roc_wr_vld) + ,.roc_wr_pd (roc_wr_pd[1:0]) + ,.roc_rd_prdy (roc_rd_prdy) + ,.roc_rd_pvld (roc_rd_pvld) + ,.roc_rd_pd (roc_rd_pd[1:0]) + ); +always @( + cfg_mode_per_element + or is_surf_end + or is_last_beat + ) begin + begin + roc_rd_en = is_last_beat & (is_surf_end | cfg_mode_per_element); + end +end +assign roc_rd_prdy = roc_rd_en & out_accept; +assign size_of_beat = roc_rd_pvld ? (roc_rd_pd[1:0] + 1) : 3'b0; +//============== +// END +//============== +assign is_line_end = is_last_w; +assign is_surf_end = is_line_end & is_last_h; +assign is_cube_end = is_surf_end & is_last_c; +//============== +// Width Count +//============== +assign size_of_width = reg2dp_width; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {13{1'b0}}; + end else begin + if (out_accept) begin + begin + if (is_line_end) begin + count_w <= 0; + end else begin + count_w <= count_w + 1; + end + end + end + end +end +assign is_last_w = (count_w==size_of_width); +//============== +// HEIGHT Count +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (out_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==reg2dp_height); +//============== +// SURF Count +//============== +assign size_of_surf = cfg_dp_8 ? {1'b0,reg2dp_channel[12:3]} : reg2dp_channel[12:3 -1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {(14-3){1'b0}}; + end else begin + if (out_accept) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1; + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +//============== +// BEAT CNT: used to foreach 1~4 16E rod FIFOs +//============== +wire [1:0] size_of_elem = (cfg_dp_size_1byte | !cfg_dp_8) ? 2'h1 : 2'h2; +assign beat_cnt_nxt = beat_cnt + size_of_elem; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_cnt,beat_cnt} <= 3'h0; + end else begin + if (out_accept) begin + if (cfg_mode_per_element) begin + if (is_last_beat) begin + {mon_beat_cnt,beat_cnt} <= 3'h0; + end else begin + {mon_beat_cnt,beat_cnt} <= beat_cnt_nxt; + end + end else if (is_surf_end) begin + if (is_last_beat) begin + {mon_beat_cnt,beat_cnt} <= 3'h0; + end else begin + {mon_beat_cnt,beat_cnt} <= beat_cnt_nxt; + end + end + end + end +end +assign is_last_beat = beat_cnt_nxt == size_of_beat; +assign rod_sel = beat_cnt; +assign rod0_sel = beat_cnt == 2'h0; +assign rod2_sel = beat_cnt == 2'h2; +assign rod1_sel = (cfg_dp_size_1byte | !cfg_dp_8)? beat_cnt == 2'h1 : beat_cnt == 2'h0; +assign rod3_sel = (cfg_dp_size_1byte | !cfg_dp_8)? beat_cnt == 2'h3 : beat_cnt == 2'h2; +////dp int8 one byte per element or int16 two bytes per elment/////////// +always @( + rod_sel + or rod0_rd_pd + or rod1_rd_pd + or rod2_rd_pd + or rod3_rd_pd + ) begin + case (rod_sel) + 2'd0: out_data_1bpe = rod0_rd_pd; + 2'd1: out_data_1bpe = rod1_rd_pd; + 2'd2: out_data_1bpe = rod2_rd_pd; + 2'd3: out_data_1bpe = rod3_rd_pd; + default : out_data_1bpe[8*8 -1:0] = {8*8{`x_or_0}}; + endcase +end +always @( + rod_sel + or rod0_rd_pvld + or rod1_rd_pvld + or rod2_rd_pvld + or rod3_rd_pvld + ) begin + case (rod_sel) + 2'd0: out_vld_1bpe = rod0_rd_pvld; + 2'd1: out_vld_1bpe = rod1_rd_pvld; + 2'd2: out_vld_1bpe = rod2_rd_pvld; + 2'd3: out_vld_1bpe = rod3_rd_pvld; + default : out_vld_1bpe = {1{`x_or_0}}; + endcase +end +//: my $m = 8; +//: foreach my $i (0..${m}-1) { +//: print "assign out_data_1bpe_ext[16*${i}+15:16*${i}] = {{8{out_data_1bpe[8*${i}+7]}}, out_data_1bpe[8*${i}+7:8*${i}]}; \n"; +//: } +////dp int8 two byte per element/////////// +always @( + rod_sel + or rod0_rd_pd + or rod1_rd_pd + or rod2_rd_pd + or rod3_rd_pd + ) begin + case (rod_sel) + 2'd0: out_data_2bpe = {rod1_rd_pd,rod0_rd_pd}; + 2'd2: out_data_2bpe = {rod3_rd_pd,rod2_rd_pd}; + default : out_data_2bpe[8*16 -1:0] = {8*16{`x_or_0}}; + endcase +end +always @( + rod_sel + or rod0_rd_pvld + or rod1_rd_pvld + or rod2_rd_pvld + or rod3_rd_pvld + ) begin + case (rod_sel) + 2'd0: out_vld_2bpe = rod1_rd_pvld & rod0_rd_pvld; + 2'd2: out_vld_2bpe = rod3_rd_pvld & rod2_rd_pvld; + default : out_vld_2bpe = {1{`x_or_0}}; + endcase +end +////mux out data //// +assign out_vld = (cfg_dp_size_1byte | !cfg_dp_8) ? out_vld_1bpe : out_vld_2bpe; +assign out_pd[8*16 -1:0] = !cfg_dp_8 ? {{8*8{1'b0}},out_data_1bpe[8*8 -1:0]} : cfg_dp_size_1byte ? out_data_1bpe_ext[8*16 -1:0] : out_data_2bpe[8*16 -1:0]; +assign out_pd[8*16] = is_cube_end; +assign out_accept = out_vld & out_rdy; +NV_NVDLA_SDP_RDMA_EG_RO_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.out_pd (out_pd[8*16:0]) //|< w + ,.out_vld (out_vld) //|< r + ,.out_rdy (out_rdy) //|> w + ,.sdp_rdma2dp_ready (sdp_rdma2dp_ready) //|< i + ,.sdp_rdma2dp_pd (sdp_rdma2dp_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_valid (sdp_rdma2dp_valid) //|> o + ); +assign layer_end = sdp_rdma2dp_valid & sdp_rdma2dp_ready & sdp_rdma2dp_pd[8*16]; +endmodule // NV_NVDLA_SDP_RDMA_EG_ro +// ************************************************************************************************************** +// Generated by ::pipe -m -bc sdp_rdma2dp_pd (sdp_rdma2dp_valid,sdp_rdma2dp_ready) <= out_pd[8*8:0] (out_vld, out_rdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_RDMA_EG_RO_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,out_pd + ,out_vld + ,out_rdy + ,sdp_rdma2dp_ready + ,sdp_rdma2dp_pd + ,sdp_rdma2dp_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input out_vld; +output out_rdy; +input [8*16:0] out_pd; +output [8*16:0] sdp_rdma2dp_pd; +output sdp_rdma2dp_valid; +input sdp_rdma2dp_ready; +//: my $dw = 1 + 8*16; +//: &eperl::pipe("-is -wid $dw -do sdp_rdma2dp_pd -vo sdp_rdma2dp_valid -ri sdp_rdma2dp_ready -di out_pd -vi out_vld -ro out_rdy"); +endmodule // NV_NVDLA_SDP_RDMA_EG_RO_pipe_p1 +module NV_NVDLA_SDP_RDMA_EG_RO_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , rod_wr_prdy + , rod_wr_pvld + , rod_wr_pd + , rod_rd_prdy + , rod_rd_pvld + , rod_rd_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output rod_wr_prdy; +input rod_wr_pvld; +input [8*8 -1:0] rod_wr_pd; +input rod_rd_prdy; +output rod_rd_pvld; +output [8*8 -1:0] rod_rd_pd; +//: my $dw = 8*8; +//: &eperl::pipe("-is -wid $dw -do rod_rd_pd -vo rod_rd_pvld -ri rod_rd_prdy -di rod_wr_pd -vi rod_wr_pvld -ro rod_wr_prdy"); +endmodule +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_RDMA_EG_RO_cfifo ( + nvdla_core_clk + , nvdla_core_rstn + , roc_wr_prdy + , roc_wr_pvld + , roc_wr_pd + , roc_rd_prdy + , roc_rd_pvld + , roc_rd_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output roc_wr_prdy; +input roc_wr_pvld; +input [1:0] roc_wr_pd; +input roc_rd_prdy; +output roc_rd_pvld; +output [1:0] roc_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg roc_wr_busy_int; // copy for internal use +assign roc_wr_prdy = !roc_wr_busy_int; +assign wr_reserving = roc_wr_pvld && !roc_wr_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] roc_wr_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? roc_wr_count : (roc_wr_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (roc_wr_count + 1'd1) : roc_wr_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire roc_wr_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check roc_wr_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_wr_busy_int <= 1'b0; + roc_wr_count <= 3'd0; + end else begin + roc_wr_busy_int <= roc_wr_busy_next; + if ( wr_reserving ^ wr_popping ) begin + roc_wr_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + roc_wr_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as roc_wr_pvld +// +// RAM +// +reg [1:0] roc_wr_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_wr_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + roc_wr_adr <= roc_wr_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] roc_rd_adr; // read address this cycle +wire ram_we = wr_pushing && (roc_wr_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [1:0] roc_rd_pd_p; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( roc_wr_pd ) + , .we ( ram_we ) + , .wa ( roc_wr_adr ) + , .ra ( (roc_wr_count == 0) ? 3'd4 : {1'b0,roc_rd_adr} ) + , .dout ( roc_rd_pd_p ) + ); +wire [1:0] rd_adr_next_popping = roc_rd_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + roc_rd_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + roc_rd_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +reg roc_rd_prdy_d; // roc_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_prdy_d <= 1'b1; + end else begin + roc_rd_prdy_d <= roc_rd_prdy; + end +end +wire roc_rd_prdy_d_o; // combinatorial rd_busy +wire roc_rd_pvld_p; // data out of fifo is valid +reg roc_rd_pvld_int_o; // internal copy of roc_rd_pvld_o +wire roc_rd_pvld_o = roc_rd_pvld_int_o; +assign rd_popping = roc_rd_pvld_p && !(roc_rd_pvld_int_o && !roc_rd_prdy_d_o); +reg [2:0] roc_rd_count_p; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_p_next_rd_popping = rd_pushing ? roc_rd_count_p : + (roc_rd_count_p - 1'd1); +wire [2:0] rd_count_p_next_no_rd_popping = rd_pushing ? (roc_rd_count_p + 1'd1) : + roc_rd_count_p; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_p_next = rd_popping ? rd_count_p_next_rd_popping : + rd_count_p_next_no_rd_popping; +assign roc_rd_pvld_p = roc_rd_count_p != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_count_p <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + roc_rd_count_p <= rd_count_p_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + roc_rd_count_p <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SKID for -rd_busy_reg +// +reg [1:0] roc_rd_pd_o; // output data register +wire rd_req_next_o = (roc_rd_pvld_p || (roc_rd_pvld_int_o && !roc_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_pvld_int_o <= 1'b0; + end else begin + roc_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (rd_popping) ) begin + roc_rd_pd_o <= roc_rd_pd_p; + end +//synopsys translate_off + else if ( !((rd_popping)) ) begin + end else begin + roc_rd_pd_o <= {2{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +assign roc_rd_pd = !roc_rd_prdy_d_o ? roc_rd_pd_o : roc_rd_pd_p; // skid reg assign +reg roc_rd_pvld_d; // previous roc_rd_pvld +assign roc_rd_prdy_d_o = !(roc_rd_pvld_d && !roc_rd_prdy_d ); +assign roc_rd_pvld = !roc_rd_prdy_d_o ? roc_rd_pvld_o : roc_rd_pvld_p; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + roc_rd_pvld_d <= 1'b0; + end else begin + roc_rd_pvld_d <= roc_rd_pvld; + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (roc_wr_pvld && !roc_wr_busy_int) || (roc_wr_busy_int != roc_wr_busy_next)) || (rd_pushing || rd_popping || (roc_rd_pvld && roc_rd_prdy_d) || (roc_rd_pvld_int_o && roc_rd_prdy_d_o)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_RDMA_EG_RO_cfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, roc_wr_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_RDMA_EG_RO_cfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_RDMA_EG_RO_cfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [1:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [1:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [1:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [1:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [1:0] ram_ff0; +reg [1:0] ram_ff1; +reg [1:0] ram_ff2; +reg [1:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [1:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {2{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [1:0] Di0; +input [1:0] Ra0; +output [1:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 2'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [1:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [1:0] Q0 = mem[0]; +wire [1:0] Q1 = mem[1]; +wire [1:0] Q2 = mem[2]; +wire [1:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2] } +endmodule // vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +//vmw: Memory vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +//vmw: Address-size 2 +//vmw: Data-size 2 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[1:0] data0[1:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[1:0] data1[1:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_RDMA_EG_RO_cfifo_flopram_rwsa_4x2 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v new file mode 100644 index 0000000..0b32072 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v @@ -0,0 +1,783 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_REG_dual.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,bn_base_addr_high + ,bn_base_addr_low + ,bn_batch_stride + ,bn_line_stride + ,bn_surface_stride + ,brdma_data_mode + ,brdma_data_size + ,brdma_data_use + ,brdma_disable + ,brdma_ram_type + ,bs_base_addr_high + ,bs_base_addr_low + ,bs_batch_stride + ,bs_line_stride + ,bs_surface_stride + ,channel + ,height + ,width + ,erdma_data_mode + ,erdma_data_size + ,erdma_data_use + ,erdma_disable + ,erdma_ram_type + ,ew_base_addr_high + ,ew_base_addr_low + ,ew_batch_stride + ,ew_line_stride + ,ew_surface_stride + ,batch_number + ,flying_mode + ,in_precision + ,out_precision + ,proc_precision + ,winograd + ,nrdma_data_mode + ,nrdma_data_size + ,nrdma_data_use + ,nrdma_disable + ,nrdma_ram_type + ,op_en_trigger + ,perf_dma_en + ,perf_nan_inf_count_en + ,src_base_addr_high + ,src_base_addr_low + ,src_ram_type + ,src_line_stride + ,src_surface_stride + ,op_en + ,brdma_stall + ,erdma_stall + ,mrdma_stall + ,nrdma_stall + ,status_inf_input_num + ,status_nan_input_num + ); +wire [31:0] nvdla_sdp_rdma_d_bn_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_batch_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_brdma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_batch_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_data_cube_channel_0_out; +wire [31:0] nvdla_sdp_rdma_d_data_cube_height_0_out; +wire [31:0] nvdla_sdp_rdma_d_data_cube_width_0_out; +wire [31:0] nvdla_sdp_rdma_d_erdma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_batch_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_feature_mode_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_nrdma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_op_enable_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_enable_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_dma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_status_inf_input_num_0_out; +wire [31:0] nvdla_sdp_rdma_d_status_nan_input_num_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] bn_base_addr_high; +output [31:0] bn_base_addr_low; +output [31:0] bn_batch_stride; +output [31:0] bn_line_stride; +output [31:0] bn_surface_stride; +output brdma_data_mode; +output brdma_data_size; +output [1:0] brdma_data_use; +output brdma_disable; +output brdma_ram_type; +output [31:0] bs_base_addr_high; +output [31:0] bs_base_addr_low; +output [31:0] bs_batch_stride; +output [31:0] bs_line_stride; +output [31:0] bs_surface_stride; +output [12:0] channel; +output [12:0] height; +output [12:0] width; +output erdma_data_mode; +output erdma_data_size; +output [1:0] erdma_data_use; +output erdma_disable; +output erdma_ram_type; +output [31:0] ew_base_addr_high; +output [31:0] ew_base_addr_low; +output [31:0] ew_batch_stride; +output [31:0] ew_line_stride; +output [31:0] ew_surface_stride; +output [4:0] batch_number; +output flying_mode; +output [1:0] in_precision; +output [1:0] out_precision; +output [1:0] proc_precision; +output winograd; +output nrdma_data_mode; +output nrdma_data_size; +output [1:0] nrdma_data_use; +output nrdma_disable; +output nrdma_ram_type; +output op_en_trigger; +output perf_dma_en; +output perf_nan_inf_count_en; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output src_ram_type; +output [31:0] src_line_stride; +output [31:0] src_surface_stride; +// Read-only register inputs +input op_en; +input [31:0] brdma_stall; +input [31:0] erdma_stall; +input [31:0] mrdma_stall; +input [31:0] nrdma_stall; +input [31:0] status_inf_input_num; +input [31:0] status_nan_input_num; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [4:0] batch_number; +reg [31:0] bn_base_addr_high; +reg [31:0] bn_base_addr_low; +reg [31:0] bn_batch_stride; +reg [31:0] bn_line_stride; +reg [31:0] bn_surface_stride; +reg brdma_data_mode; +reg brdma_data_size; +reg [1:0] brdma_data_use; +reg brdma_disable; +reg brdma_ram_type; +reg [31:0] bs_base_addr_high; +reg [31:0] bs_base_addr_low; +reg [31:0] bs_batch_stride; +reg [31:0] bs_line_stride; +reg [31:0] bs_surface_stride; +reg [12:0] channel; +reg erdma_data_mode; +reg erdma_data_size; +reg [1:0] erdma_data_use; +reg erdma_disable; +reg erdma_ram_type; +reg [31:0] ew_base_addr_high; +reg [31:0] ew_base_addr_low; +reg [31:0] ew_batch_stride; +reg [31:0] ew_line_stride; +reg [31:0] ew_surface_stride; +reg flying_mode; +reg [12:0] height; +reg [1:0] in_precision; +reg nrdma_data_mode; +reg nrdma_data_size; +reg [1:0] nrdma_data_use; +reg nrdma_disable; +reg nrdma_ram_type; +reg [1:0] out_precision; +reg perf_dma_en; +reg perf_nan_inf_count_en; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg src_ram_type; +reg [31:0] src_surface_stride; +reg [12:0] width; +reg winograd; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_rdma_d_bn_base_addr_high_0_wren = (reg_offset_wr == (32'ha048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_base_addr_low_0_wren = (reg_offset_wr == (32'ha044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_batch_stride_0_wren = (reg_offset_wr == (32'ha054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_line_stride_0_wren = (reg_offset_wr == (32'ha04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_surface_stride_0_wren = (reg_offset_wr == (32'ha050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_brdma_cfg_0_wren = (reg_offset_wr == (32'ha028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_base_addr_high_0_wren = (reg_offset_wr == (32'ha030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_base_addr_low_0_wren = (reg_offset_wr == (32'ha02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_batch_stride_0_wren = (reg_offset_wr == (32'ha03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_line_stride_0_wren = (reg_offset_wr == (32'ha034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_surface_stride_0_wren = (reg_offset_wr == (32'ha038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_data_cube_channel_0_wren = (reg_offset_wr == (32'ha014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_data_cube_height_0_wren = (reg_offset_wr == (32'ha010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_data_cube_width_0_wren = (reg_offset_wr == (32'ha00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_erdma_cfg_0_wren = (reg_offset_wr == (32'ha058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_base_addr_high_0_wren = (reg_offset_wr == (32'ha060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_base_addr_low_0_wren = (reg_offset_wr == (32'ha05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_batch_stride_0_wren = (reg_offset_wr == (32'ha06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_line_stride_0_wren = (reg_offset_wr == (32'ha064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_surface_stride_0_wren = (reg_offset_wr == (32'ha068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_feature_mode_cfg_0_wren = (reg_offset_wr == (32'ha070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_nrdma_cfg_0_wren = (reg_offset_wr == (32'ha040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_op_enable_0_wren = (reg_offset_wr == (32'ha008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_brdma_read_stall_0_wren = (reg_offset_wr == (32'ha088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_enable_0_wren = (reg_offset_wr == (32'ha080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_erdma_read_stall_0_wren = (reg_offset_wr == (32'ha090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_wren = (reg_offset_wr == (32'ha084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_wren = (reg_offset_wr == (32'ha08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'ha01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'ha018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_dma_cfg_0_wren = (reg_offset_wr == (32'ha074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_line_stride_0_wren = (reg_offset_wr == (32'ha020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_surface_stride_0_wren = (reg_offset_wr == (32'ha024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_status_inf_input_num_0_wren = (reg_offset_wr == (32'ha07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_status_nan_input_num_0_wren = (reg_offset_wr == (32'ha078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_rdma_d_bn_base_addr_high_0_out[31:0] = { bn_base_addr_high }; +assign nvdla_sdp_rdma_d_bn_base_addr_low_0_out[31:0] = { bn_base_addr_low}; +assign nvdla_sdp_rdma_d_bn_batch_stride_0_out[31:0] = { bn_batch_stride}; +assign nvdla_sdp_rdma_d_bn_line_stride_0_out[31:0] = { bn_line_stride}; +assign nvdla_sdp_rdma_d_bn_surface_stride_0_out[31:0] = { bn_surface_stride}; +assign nvdla_sdp_rdma_d_brdma_cfg_0_out[31:0] = { 26'b0, brdma_ram_type, brdma_data_mode, brdma_data_size, brdma_data_use, brdma_disable }; +assign nvdla_sdp_rdma_d_bs_base_addr_high_0_out[31:0] = { bs_base_addr_high }; +assign nvdla_sdp_rdma_d_bs_base_addr_low_0_out[31:0] = { bs_base_addr_low}; +assign nvdla_sdp_rdma_d_bs_batch_stride_0_out[31:0] = { bs_batch_stride}; +assign nvdla_sdp_rdma_d_bs_line_stride_0_out[31:0] = { bs_line_stride}; +assign nvdla_sdp_rdma_d_bs_surface_stride_0_out[31:0] = { bs_surface_stride}; +assign nvdla_sdp_rdma_d_data_cube_channel_0_out[31:0] = { 19'b0, channel }; +assign nvdla_sdp_rdma_d_data_cube_height_0_out[31:0] = { 19'b0, height }; +assign nvdla_sdp_rdma_d_data_cube_width_0_out[31:0] = { 19'b0, width }; +assign nvdla_sdp_rdma_d_erdma_cfg_0_out[31:0] = { 26'b0, erdma_ram_type, erdma_data_mode, erdma_data_size, erdma_data_use, erdma_disable }; +assign nvdla_sdp_rdma_d_ew_base_addr_high_0_out[31:0] = { ew_base_addr_high }; +assign nvdla_sdp_rdma_d_ew_base_addr_low_0_out[31:0] = { ew_base_addr_low}; +assign nvdla_sdp_rdma_d_ew_batch_stride_0_out[31:0] = { ew_batch_stride}; +assign nvdla_sdp_rdma_d_ew_line_stride_0_out[31:0] = { ew_line_stride}; +assign nvdla_sdp_rdma_d_ew_surface_stride_0_out[31:0] = { ew_surface_stride}; +assign nvdla_sdp_rdma_d_feature_mode_cfg_0_out[31:0] = { 19'b0, batch_number, out_precision, proc_precision, in_precision, winograd, flying_mode }; +assign nvdla_sdp_rdma_d_nrdma_cfg_0_out[31:0] = { 26'b0, nrdma_ram_type, nrdma_data_mode, nrdma_data_size, nrdma_data_use, nrdma_disable }; +assign nvdla_sdp_rdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out[31:0] = { brdma_stall }; +assign nvdla_sdp_rdma_d_perf_enable_0_out[31:0] = { 30'b0, perf_nan_inf_count_en, perf_dma_en }; +assign nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out[31:0] = { erdma_stall }; +assign nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out[31:0] = { mrdma_stall }; +assign nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out[31:0] = { nrdma_stall }; +assign nvdla_sdp_rdma_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_sdp_rdma_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low}; +assign nvdla_sdp_rdma_d_src_dma_cfg_0_out[31:0] = { 31'b0, src_ram_type }; +assign nvdla_sdp_rdma_d_src_line_stride_0_out[31:0] = { src_line_stride}; +assign nvdla_sdp_rdma_d_src_surface_stride_0_out[31:0] = { src_surface_stride}; +assign nvdla_sdp_rdma_d_status_inf_input_num_0_out[31:0] = { status_inf_input_num }; +assign nvdla_sdp_rdma_d_status_nan_input_num_0_out[31:0] = { status_nan_input_num }; +assign op_en_trigger = nvdla_sdp_rdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_rdma_d_bn_base_addr_high_0_out + or nvdla_sdp_rdma_d_bn_base_addr_low_0_out + or nvdla_sdp_rdma_d_bn_batch_stride_0_out + or nvdla_sdp_rdma_d_bn_line_stride_0_out + or nvdla_sdp_rdma_d_bn_surface_stride_0_out + or nvdla_sdp_rdma_d_brdma_cfg_0_out + or nvdla_sdp_rdma_d_bs_base_addr_high_0_out + or nvdla_sdp_rdma_d_bs_base_addr_low_0_out + or nvdla_sdp_rdma_d_bs_batch_stride_0_out + or nvdla_sdp_rdma_d_bs_line_stride_0_out + or nvdla_sdp_rdma_d_bs_surface_stride_0_out + or nvdla_sdp_rdma_d_data_cube_channel_0_out + or nvdla_sdp_rdma_d_data_cube_height_0_out + or nvdla_sdp_rdma_d_data_cube_width_0_out + or nvdla_sdp_rdma_d_erdma_cfg_0_out + or nvdla_sdp_rdma_d_ew_base_addr_high_0_out + or nvdla_sdp_rdma_d_ew_base_addr_low_0_out + or nvdla_sdp_rdma_d_ew_batch_stride_0_out + or nvdla_sdp_rdma_d_ew_line_stride_0_out + or nvdla_sdp_rdma_d_ew_surface_stride_0_out + or nvdla_sdp_rdma_d_feature_mode_cfg_0_out + or nvdla_sdp_rdma_d_nrdma_cfg_0_out + or nvdla_sdp_rdma_d_op_enable_0_out + or nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out + or nvdla_sdp_rdma_d_perf_enable_0_out + or nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out + or nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out + or nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out + or nvdla_sdp_rdma_d_src_base_addr_high_0_out + or nvdla_sdp_rdma_d_src_base_addr_low_0_out + or nvdla_sdp_rdma_d_src_dma_cfg_0_out + or nvdla_sdp_rdma_d_src_line_stride_0_out + or nvdla_sdp_rdma_d_src_surface_stride_0_out + or nvdla_sdp_rdma_d_status_inf_input_num_0_out + or nvdla_sdp_rdma_d_status_nan_input_num_0_out + ) begin + case (reg_offset_rd_int) + (32'ha048 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_base_addr_high_0_out ; + end + (32'ha044 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_base_addr_low_0_out ; + end + (32'ha054 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_batch_stride_0_out ; + end + (32'ha04c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_line_stride_0_out ; + end + (32'ha050 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_surface_stride_0_out ; + end + (32'ha028 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_brdma_cfg_0_out ; + end + (32'ha030 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_base_addr_high_0_out ; + end + (32'ha02c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_base_addr_low_0_out ; + end + (32'ha03c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_batch_stride_0_out ; + end + (32'ha034 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_line_stride_0_out ; + end + (32'ha038 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_surface_stride_0_out ; + end + (32'ha014 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_data_cube_channel_0_out ; + end + (32'ha010 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_data_cube_height_0_out ; + end + (32'ha00c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_data_cube_width_0_out ; + end + (32'ha058 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_erdma_cfg_0_out ; + end + (32'ha060 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_base_addr_high_0_out ; + end + (32'ha05c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_base_addr_low_0_out ; + end + (32'ha06c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_batch_stride_0_out ; + end + (32'ha064 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_line_stride_0_out ; + end + (32'ha068 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_surface_stride_0_out ; + end + (32'ha070 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_feature_mode_cfg_0_out ; + end + (32'ha040 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_nrdma_cfg_0_out ; + end + (32'ha008 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_op_enable_0_out ; + end + (32'ha088 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out ; + end + (32'ha080 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_enable_0_out ; + end + (32'ha090 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out ; + end + (32'ha084 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out ; + end + (32'ha08c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out ; + end + (32'ha01c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_base_addr_high_0_out ; + end + (32'ha018 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_base_addr_low_0_out ; + end + (32'ha074 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_dma_cfg_0_out ; + end + (32'ha020 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_line_stride_0_out ; + end + (32'ha024 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_surface_stride_0_out ; + end + (32'ha07c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_status_inf_input_num_0_out ; + end + (32'ha078 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_status_nan_input_num_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bn_base_addr_high[31:0] <= 32'h0; + bn_base_addr_low[31:0] <= {(32){1'b0}}; + bn_batch_stride[31:0] <= {(32){1'b0}}; + bn_line_stride[31:0] <= {(32){1'b0}}; + bn_surface_stride[31:0] <= {(32){1'b0}}; + brdma_data_mode <= 1'b0; + brdma_data_size <= 1'b0; + brdma_data_use[1:0] <= 2'b00; + brdma_disable <= 1'b1; + brdma_ram_type <= 1'b0; + bs_base_addr_high[31:0] <= 32'h0; + bs_base_addr_low[31:0] <= {(32){1'b0}}; + bs_batch_stride[31:0] <= {(32){1'b0}}; + bs_line_stride[31:0] <= {(32){1'b0}}; + bs_surface_stride[31:0] <= {(32){1'b0}}; + channel[12:0] <= 13'b0000000000000; + height[12:0] <= 13'b0000000000000; + width[12:0] <= 13'b0000000000000; + erdma_data_mode <= 1'b0; + erdma_data_size <= 1'b0; + erdma_data_use[1:0] <= 2'b00; + erdma_disable <= 1'b1; + erdma_ram_type <= 1'b0; + ew_base_addr_high[31:0] <= 32'h0; + ew_base_addr_low[31:0] <= {(32){1'b0}}; + ew_batch_stride[31:0] <= {(32){1'b0}}; + ew_line_stride[31:0] <= {(32){1'b0}}; + ew_surface_stride[31:0] <= {(32){1'b0}}; + batch_number[4:0] <= 5'b00000; + flying_mode <= 1'b0; + in_precision[1:0] <= 2'b01; + out_precision[1:0] <= 2'b00; + proc_precision[1:0] <= 2'b01; + winograd <= 1'b0; + nrdma_data_mode <= 1'b0; + nrdma_data_size <= 1'b0; + nrdma_data_use[1:0] <= 2'b00; + nrdma_disable <= 1'b1; + nrdma_ram_type <= 1'b0; + perf_dma_en <= 1'b0; + perf_nan_inf_count_en <= 1'b0; + src_base_addr_high[31:0] <= 32'h0; + src_base_addr_low[31:0] <= {(32){1'b0}}; + src_ram_type <= 1'b0; + src_line_stride[31:0] <= {(32){1'b0}}; + src_surface_stride[31:0] <= {(32){1'b0}}; + end else begin +// Register: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 Field: bn_base_addr_high + if (nvdla_sdp_rdma_d_bn_base_addr_high_0_wren) begin + bn_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_LOW_0 Field: bn_base_addr_low + if (nvdla_sdp_rdma_d_bn_base_addr_low_0_wren) begin + bn_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_BATCH_STRIDE_0 Field: bn_batch_stride + if (nvdla_sdp_rdma_d_bn_batch_stride_0_wren) begin + bn_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_LINE_STRIDE_0 Field: bn_line_stride + if (nvdla_sdp_rdma_d_bn_line_stride_0_wren) begin + bn_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_SURFACE_STRIDE_0 Field: bn_surface_stride + if (nvdla_sdp_rdma_d_bn_surface_stride_0_wren) begin + bn_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_data_mode + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_data_mode <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_data_size + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_data_size <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_data_use + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_data_use[1:0] <= reg_wr_data[2:1]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_disable + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_disable <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_ram_type + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_ram_type <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 Field: bs_base_addr_high + if (nvdla_sdp_rdma_d_bs_base_addr_high_0_wren) begin + bs_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_LOW_0 Field: bs_base_addr_low + if (nvdla_sdp_rdma_d_bs_base_addr_low_0_wren) begin + bs_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_BATCH_STRIDE_0 Field: bs_batch_stride + if (nvdla_sdp_rdma_d_bs_batch_stride_0_wren) begin + bs_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_LINE_STRIDE_0 Field: bs_line_stride + if (nvdla_sdp_rdma_d_bs_line_stride_0_wren) begin + bs_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_SURFACE_STRIDE_0 Field: bs_surface_stride + if (nvdla_sdp_rdma_d_bs_surface_stride_0_wren) begin + bs_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_DATA_CUBE_CHANNEL_0 Field: channel + if (nvdla_sdp_rdma_d_data_cube_channel_0_wren) begin + channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_RDMA_D_DATA_CUBE_HEIGHT_0 Field: height + if (nvdla_sdp_rdma_d_data_cube_height_0_wren) begin + height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_RDMA_D_DATA_CUBE_WIDTH_0 Field: width + if (nvdla_sdp_rdma_d_data_cube_width_0_wren) begin + width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_data_mode + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_data_mode <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_data_size + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_data_size <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_data_use + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_data_use[1:0] <= reg_wr_data[2:1]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_disable + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_disable <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_ram_type + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_ram_type <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 Field: ew_base_addr_high + if (nvdla_sdp_rdma_d_ew_base_addr_high_0_wren) begin + ew_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_LOW_0 Field: ew_base_addr_low + if (nvdla_sdp_rdma_d_ew_base_addr_low_0_wren) begin + ew_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_BATCH_STRIDE_0 Field: ew_batch_stride + if (nvdla_sdp_rdma_d_ew_batch_stride_0_wren) begin + ew_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_LINE_STRIDE_0 Field: ew_line_stride + if (nvdla_sdp_rdma_d_ew_line_stride_0_wren) begin + ew_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_SURFACE_STRIDE_0 Field: ew_surface_stride + if (nvdla_sdp_rdma_d_ew_surface_stride_0_wren) begin + ew_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: batch_number + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + batch_number[4:0] <= reg_wr_data[12:8]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: flying_mode + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + flying_mode <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: in_precision + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: out_precision + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + out_precision[1:0] <= reg_wr_data[7:6]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: proc_precision + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[5:4]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: winograd + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + winograd <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_data_mode + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_data_mode <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_data_size + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_data_size <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_data_use + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_data_use[1:0] <= reg_wr_data[2:1]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_disable + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_disable <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_ram_type + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_ram_type <= reg_wr_data[5]; + end +// Not generating flops for field NVDLA_SDP_RDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_BRDMA_READ_STALL_0::brdma_stall +// Register: NVDLA_SDP_RDMA_D_PERF_ENABLE_0 Field: perf_dma_en + if (nvdla_sdp_rdma_d_perf_enable_0_wren) begin + perf_dma_en <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_PERF_ENABLE_0 Field: perf_nan_inf_count_en + if (nvdla_sdp_rdma_d_perf_enable_0_wren) begin + perf_nan_inf_count_en <= reg_wr_data[1]; + end +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_ERDMA_READ_STALL_0::erdma_stall +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_MRDMA_READ_STALL_0::mrdma_stall +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_NRDMA_READ_STALL_0::nrdma_stall +// Register: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_sdp_rdma_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_sdp_rdma_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_DMA_CFG_0 Field: src_ram_type + if (nvdla_sdp_rdma_d_src_dma_cfg_0_wren) begin + src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_sdp_rdma_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_sdp_rdma_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_STATUS_INF_INPUT_NUM_0::status_inf_input_num +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0::status_nan_input_num + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'ha048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_base_addr_high_0_out, nvdla_sdp_rdma_d_bn_base_addr_high_0_out); + (32'ha044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_base_addr_low_0_out, nvdla_sdp_rdma_d_bn_base_addr_low_0_out); + (32'ha054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_batch_stride_0_out, nvdla_sdp_rdma_d_bn_batch_stride_0_out); + (32'ha04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_line_stride_0_out, nvdla_sdp_rdma_d_bn_line_stride_0_out); + (32'ha050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_surface_stride_0_out, nvdla_sdp_rdma_d_bn_surface_stride_0_out); + (32'ha028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_brdma_cfg_0_out, nvdla_sdp_rdma_d_brdma_cfg_0_out); + (32'ha030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_base_addr_high_0_out, nvdla_sdp_rdma_d_bs_base_addr_high_0_out); + (32'ha02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_base_addr_low_0_out, nvdla_sdp_rdma_d_bs_base_addr_low_0_out); + (32'ha03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_batch_stride_0_out, nvdla_sdp_rdma_d_bs_batch_stride_0_out); + (32'ha034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_line_stride_0_out, nvdla_sdp_rdma_d_bs_line_stride_0_out); + (32'ha038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_surface_stride_0_out, nvdla_sdp_rdma_d_bs_surface_stride_0_out); + (32'ha014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_DATA_CUBE_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_data_cube_channel_0_out, nvdla_sdp_rdma_d_data_cube_channel_0_out); + (32'ha010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_DATA_CUBE_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_data_cube_height_0_out, nvdla_sdp_rdma_d_data_cube_height_0_out); + (32'ha00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_DATA_CUBE_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_data_cube_width_0_out, nvdla_sdp_rdma_d_data_cube_width_0_out); + (32'ha058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_erdma_cfg_0_out, nvdla_sdp_rdma_d_erdma_cfg_0_out); + (32'ha060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_base_addr_high_0_out, nvdla_sdp_rdma_d_ew_base_addr_high_0_out); + (32'ha05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_base_addr_low_0_out, nvdla_sdp_rdma_d_ew_base_addr_low_0_out); + (32'ha06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_batch_stride_0_out, nvdla_sdp_rdma_d_ew_batch_stride_0_out); + (32'ha064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_line_stride_0_out, nvdla_sdp_rdma_d_ew_line_stride_0_out); + (32'ha068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_surface_stride_0_out, nvdla_sdp_rdma_d_ew_surface_stride_0_out); + (32'ha070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_feature_mode_cfg_0_out, nvdla_sdp_rdma_d_feature_mode_cfg_0_out); + (32'ha040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_nrdma_cfg_0_out, nvdla_sdp_rdma_d_nrdma_cfg_0_out); + (32'ha008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_op_enable_0_out, nvdla_sdp_rdma_d_op_enable_0_out); + (32'ha088 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_BRDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_perf_enable_0_out, nvdla_sdp_rdma_d_perf_enable_0_out); + (32'ha090 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_ERDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha084 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_MRDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha08c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_NRDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_base_addr_high_0_out, nvdla_sdp_rdma_d_src_base_addr_high_0_out); + (32'ha018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_base_addr_low_0_out, nvdla_sdp_rdma_d_src_base_addr_low_0_out); + (32'ha074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_dma_cfg_0_out, nvdla_sdp_rdma_d_src_dma_cfg_0_out); + (32'ha020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_line_stride_0_out, nvdla_sdp_rdma_d_src_line_stride_0_out); + (32'ha024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_surface_stride_0_out, nvdla_sdp_rdma_d_src_surface_stride_0_out); + (32'ha07c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_STATUS_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha078 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_RDMA_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v.vcp new file mode 100644 index 0000000..0b32072 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v.vcp @@ -0,0 +1,783 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_REG_dual.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,bn_base_addr_high + ,bn_base_addr_low + ,bn_batch_stride + ,bn_line_stride + ,bn_surface_stride + ,brdma_data_mode + ,brdma_data_size + ,brdma_data_use + ,brdma_disable + ,brdma_ram_type + ,bs_base_addr_high + ,bs_base_addr_low + ,bs_batch_stride + ,bs_line_stride + ,bs_surface_stride + ,channel + ,height + ,width + ,erdma_data_mode + ,erdma_data_size + ,erdma_data_use + ,erdma_disable + ,erdma_ram_type + ,ew_base_addr_high + ,ew_base_addr_low + ,ew_batch_stride + ,ew_line_stride + ,ew_surface_stride + ,batch_number + ,flying_mode + ,in_precision + ,out_precision + ,proc_precision + ,winograd + ,nrdma_data_mode + ,nrdma_data_size + ,nrdma_data_use + ,nrdma_disable + ,nrdma_ram_type + ,op_en_trigger + ,perf_dma_en + ,perf_nan_inf_count_en + ,src_base_addr_high + ,src_base_addr_low + ,src_ram_type + ,src_line_stride + ,src_surface_stride + ,op_en + ,brdma_stall + ,erdma_stall + ,mrdma_stall + ,nrdma_stall + ,status_inf_input_num + ,status_nan_input_num + ); +wire [31:0] nvdla_sdp_rdma_d_bn_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_batch_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bn_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_brdma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_batch_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_bs_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_data_cube_channel_0_out; +wire [31:0] nvdla_sdp_rdma_d_data_cube_height_0_out; +wire [31:0] nvdla_sdp_rdma_d_data_cube_width_0_out; +wire [31:0] nvdla_sdp_rdma_d_erdma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_batch_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_ew_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_feature_mode_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_nrdma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_op_enable_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_enable_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_base_addr_high_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_base_addr_low_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_dma_cfg_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_line_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_src_surface_stride_0_out; +wire [31:0] nvdla_sdp_rdma_d_status_inf_input_num_0_out; +wire [31:0] nvdla_sdp_rdma_d_status_nan_input_num_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] bn_base_addr_high; +output [31:0] bn_base_addr_low; +output [31:0] bn_batch_stride; +output [31:0] bn_line_stride; +output [31:0] bn_surface_stride; +output brdma_data_mode; +output brdma_data_size; +output [1:0] brdma_data_use; +output brdma_disable; +output brdma_ram_type; +output [31:0] bs_base_addr_high; +output [31:0] bs_base_addr_low; +output [31:0] bs_batch_stride; +output [31:0] bs_line_stride; +output [31:0] bs_surface_stride; +output [12:0] channel; +output [12:0] height; +output [12:0] width; +output erdma_data_mode; +output erdma_data_size; +output [1:0] erdma_data_use; +output erdma_disable; +output erdma_ram_type; +output [31:0] ew_base_addr_high; +output [31:0] ew_base_addr_low; +output [31:0] ew_batch_stride; +output [31:0] ew_line_stride; +output [31:0] ew_surface_stride; +output [4:0] batch_number; +output flying_mode; +output [1:0] in_precision; +output [1:0] out_precision; +output [1:0] proc_precision; +output winograd; +output nrdma_data_mode; +output nrdma_data_size; +output [1:0] nrdma_data_use; +output nrdma_disable; +output nrdma_ram_type; +output op_en_trigger; +output perf_dma_en; +output perf_nan_inf_count_en; +output [31:0] src_base_addr_high; +output [31:0] src_base_addr_low; +output src_ram_type; +output [31:0] src_line_stride; +output [31:0] src_surface_stride; +// Read-only register inputs +input op_en; +input [31:0] brdma_stall; +input [31:0] erdma_stall; +input [31:0] mrdma_stall; +input [31:0] nrdma_stall; +input [31:0] status_inf_input_num; +input [31:0] status_nan_input_num; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [4:0] batch_number; +reg [31:0] bn_base_addr_high; +reg [31:0] bn_base_addr_low; +reg [31:0] bn_batch_stride; +reg [31:0] bn_line_stride; +reg [31:0] bn_surface_stride; +reg brdma_data_mode; +reg brdma_data_size; +reg [1:0] brdma_data_use; +reg brdma_disable; +reg brdma_ram_type; +reg [31:0] bs_base_addr_high; +reg [31:0] bs_base_addr_low; +reg [31:0] bs_batch_stride; +reg [31:0] bs_line_stride; +reg [31:0] bs_surface_stride; +reg [12:0] channel; +reg erdma_data_mode; +reg erdma_data_size; +reg [1:0] erdma_data_use; +reg erdma_disable; +reg erdma_ram_type; +reg [31:0] ew_base_addr_high; +reg [31:0] ew_base_addr_low; +reg [31:0] ew_batch_stride; +reg [31:0] ew_line_stride; +reg [31:0] ew_surface_stride; +reg flying_mode; +reg [12:0] height; +reg [1:0] in_precision; +reg nrdma_data_mode; +reg nrdma_data_size; +reg [1:0] nrdma_data_use; +reg nrdma_disable; +reg nrdma_ram_type; +reg [1:0] out_precision; +reg perf_dma_en; +reg perf_nan_inf_count_en; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [31:0] src_base_addr_high; +reg [31:0] src_base_addr_low; +reg [31:0] src_line_stride; +reg src_ram_type; +reg [31:0] src_surface_stride; +reg [12:0] width; +reg winograd; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_rdma_d_bn_base_addr_high_0_wren = (reg_offset_wr == (32'ha048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_base_addr_low_0_wren = (reg_offset_wr == (32'ha044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_batch_stride_0_wren = (reg_offset_wr == (32'ha054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_line_stride_0_wren = (reg_offset_wr == (32'ha04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bn_surface_stride_0_wren = (reg_offset_wr == (32'ha050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_brdma_cfg_0_wren = (reg_offset_wr == (32'ha028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_base_addr_high_0_wren = (reg_offset_wr == (32'ha030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_base_addr_low_0_wren = (reg_offset_wr == (32'ha02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_batch_stride_0_wren = (reg_offset_wr == (32'ha03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_line_stride_0_wren = (reg_offset_wr == (32'ha034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_bs_surface_stride_0_wren = (reg_offset_wr == (32'ha038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_data_cube_channel_0_wren = (reg_offset_wr == (32'ha014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_data_cube_height_0_wren = (reg_offset_wr == (32'ha010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_data_cube_width_0_wren = (reg_offset_wr == (32'ha00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_erdma_cfg_0_wren = (reg_offset_wr == (32'ha058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_base_addr_high_0_wren = (reg_offset_wr == (32'ha060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_base_addr_low_0_wren = (reg_offset_wr == (32'ha05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_batch_stride_0_wren = (reg_offset_wr == (32'ha06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_line_stride_0_wren = (reg_offset_wr == (32'ha064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_ew_surface_stride_0_wren = (reg_offset_wr == (32'ha068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_feature_mode_cfg_0_wren = (reg_offset_wr == (32'ha070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_nrdma_cfg_0_wren = (reg_offset_wr == (32'ha040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_op_enable_0_wren = (reg_offset_wr == (32'ha008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_brdma_read_stall_0_wren = (reg_offset_wr == (32'ha088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_enable_0_wren = (reg_offset_wr == (32'ha080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_erdma_read_stall_0_wren = (reg_offset_wr == (32'ha090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_wren = (reg_offset_wr == (32'ha084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_wren = (reg_offset_wr == (32'ha08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_base_addr_high_0_wren = (reg_offset_wr == (32'ha01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_base_addr_low_0_wren = (reg_offset_wr == (32'ha018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_dma_cfg_0_wren = (reg_offset_wr == (32'ha074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_line_stride_0_wren = (reg_offset_wr == (32'ha020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_src_surface_stride_0_wren = (reg_offset_wr == (32'ha024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_status_inf_input_num_0_wren = (reg_offset_wr == (32'ha07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_d_status_nan_input_num_0_wren = (reg_offset_wr == (32'ha078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_rdma_d_bn_base_addr_high_0_out[31:0] = { bn_base_addr_high }; +assign nvdla_sdp_rdma_d_bn_base_addr_low_0_out[31:0] = { bn_base_addr_low}; +assign nvdla_sdp_rdma_d_bn_batch_stride_0_out[31:0] = { bn_batch_stride}; +assign nvdla_sdp_rdma_d_bn_line_stride_0_out[31:0] = { bn_line_stride}; +assign nvdla_sdp_rdma_d_bn_surface_stride_0_out[31:0] = { bn_surface_stride}; +assign nvdla_sdp_rdma_d_brdma_cfg_0_out[31:0] = { 26'b0, brdma_ram_type, brdma_data_mode, brdma_data_size, brdma_data_use, brdma_disable }; +assign nvdla_sdp_rdma_d_bs_base_addr_high_0_out[31:0] = { bs_base_addr_high }; +assign nvdla_sdp_rdma_d_bs_base_addr_low_0_out[31:0] = { bs_base_addr_low}; +assign nvdla_sdp_rdma_d_bs_batch_stride_0_out[31:0] = { bs_batch_stride}; +assign nvdla_sdp_rdma_d_bs_line_stride_0_out[31:0] = { bs_line_stride}; +assign nvdla_sdp_rdma_d_bs_surface_stride_0_out[31:0] = { bs_surface_stride}; +assign nvdla_sdp_rdma_d_data_cube_channel_0_out[31:0] = { 19'b0, channel }; +assign nvdla_sdp_rdma_d_data_cube_height_0_out[31:0] = { 19'b0, height }; +assign nvdla_sdp_rdma_d_data_cube_width_0_out[31:0] = { 19'b0, width }; +assign nvdla_sdp_rdma_d_erdma_cfg_0_out[31:0] = { 26'b0, erdma_ram_type, erdma_data_mode, erdma_data_size, erdma_data_use, erdma_disable }; +assign nvdla_sdp_rdma_d_ew_base_addr_high_0_out[31:0] = { ew_base_addr_high }; +assign nvdla_sdp_rdma_d_ew_base_addr_low_0_out[31:0] = { ew_base_addr_low}; +assign nvdla_sdp_rdma_d_ew_batch_stride_0_out[31:0] = { ew_batch_stride}; +assign nvdla_sdp_rdma_d_ew_line_stride_0_out[31:0] = { ew_line_stride}; +assign nvdla_sdp_rdma_d_ew_surface_stride_0_out[31:0] = { ew_surface_stride}; +assign nvdla_sdp_rdma_d_feature_mode_cfg_0_out[31:0] = { 19'b0, batch_number, out_precision, proc_precision, in_precision, winograd, flying_mode }; +assign nvdla_sdp_rdma_d_nrdma_cfg_0_out[31:0] = { 26'b0, nrdma_ram_type, nrdma_data_mode, nrdma_data_size, nrdma_data_use, nrdma_disable }; +assign nvdla_sdp_rdma_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out[31:0] = { brdma_stall }; +assign nvdla_sdp_rdma_d_perf_enable_0_out[31:0] = { 30'b0, perf_nan_inf_count_en, perf_dma_en }; +assign nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out[31:0] = { erdma_stall }; +assign nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out[31:0] = { mrdma_stall }; +assign nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out[31:0] = { nrdma_stall }; +assign nvdla_sdp_rdma_d_src_base_addr_high_0_out[31:0] = { src_base_addr_high }; +assign nvdla_sdp_rdma_d_src_base_addr_low_0_out[31:0] = { src_base_addr_low}; +assign nvdla_sdp_rdma_d_src_dma_cfg_0_out[31:0] = { 31'b0, src_ram_type }; +assign nvdla_sdp_rdma_d_src_line_stride_0_out[31:0] = { src_line_stride}; +assign nvdla_sdp_rdma_d_src_surface_stride_0_out[31:0] = { src_surface_stride}; +assign nvdla_sdp_rdma_d_status_inf_input_num_0_out[31:0] = { status_inf_input_num }; +assign nvdla_sdp_rdma_d_status_nan_input_num_0_out[31:0] = { status_nan_input_num }; +assign op_en_trigger = nvdla_sdp_rdma_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_rdma_d_bn_base_addr_high_0_out + or nvdla_sdp_rdma_d_bn_base_addr_low_0_out + or nvdla_sdp_rdma_d_bn_batch_stride_0_out + or nvdla_sdp_rdma_d_bn_line_stride_0_out + or nvdla_sdp_rdma_d_bn_surface_stride_0_out + or nvdla_sdp_rdma_d_brdma_cfg_0_out + or nvdla_sdp_rdma_d_bs_base_addr_high_0_out + or nvdla_sdp_rdma_d_bs_base_addr_low_0_out + or nvdla_sdp_rdma_d_bs_batch_stride_0_out + or nvdla_sdp_rdma_d_bs_line_stride_0_out + or nvdla_sdp_rdma_d_bs_surface_stride_0_out + or nvdla_sdp_rdma_d_data_cube_channel_0_out + or nvdla_sdp_rdma_d_data_cube_height_0_out + or nvdla_sdp_rdma_d_data_cube_width_0_out + or nvdla_sdp_rdma_d_erdma_cfg_0_out + or nvdla_sdp_rdma_d_ew_base_addr_high_0_out + or nvdla_sdp_rdma_d_ew_base_addr_low_0_out + or nvdla_sdp_rdma_d_ew_batch_stride_0_out + or nvdla_sdp_rdma_d_ew_line_stride_0_out + or nvdla_sdp_rdma_d_ew_surface_stride_0_out + or nvdla_sdp_rdma_d_feature_mode_cfg_0_out + or nvdla_sdp_rdma_d_nrdma_cfg_0_out + or nvdla_sdp_rdma_d_op_enable_0_out + or nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out + or nvdla_sdp_rdma_d_perf_enable_0_out + or nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out + or nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out + or nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out + or nvdla_sdp_rdma_d_src_base_addr_high_0_out + or nvdla_sdp_rdma_d_src_base_addr_low_0_out + or nvdla_sdp_rdma_d_src_dma_cfg_0_out + or nvdla_sdp_rdma_d_src_line_stride_0_out + or nvdla_sdp_rdma_d_src_surface_stride_0_out + or nvdla_sdp_rdma_d_status_inf_input_num_0_out + or nvdla_sdp_rdma_d_status_nan_input_num_0_out + ) begin + case (reg_offset_rd_int) + (32'ha048 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_base_addr_high_0_out ; + end + (32'ha044 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_base_addr_low_0_out ; + end + (32'ha054 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_batch_stride_0_out ; + end + (32'ha04c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_line_stride_0_out ; + end + (32'ha050 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bn_surface_stride_0_out ; + end + (32'ha028 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_brdma_cfg_0_out ; + end + (32'ha030 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_base_addr_high_0_out ; + end + (32'ha02c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_base_addr_low_0_out ; + end + (32'ha03c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_batch_stride_0_out ; + end + (32'ha034 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_line_stride_0_out ; + end + (32'ha038 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_bs_surface_stride_0_out ; + end + (32'ha014 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_data_cube_channel_0_out ; + end + (32'ha010 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_data_cube_height_0_out ; + end + (32'ha00c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_data_cube_width_0_out ; + end + (32'ha058 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_erdma_cfg_0_out ; + end + (32'ha060 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_base_addr_high_0_out ; + end + (32'ha05c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_base_addr_low_0_out ; + end + (32'ha06c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_batch_stride_0_out ; + end + (32'ha064 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_line_stride_0_out ; + end + (32'ha068 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_ew_surface_stride_0_out ; + end + (32'ha070 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_feature_mode_cfg_0_out ; + end + (32'ha040 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_nrdma_cfg_0_out ; + end + (32'ha008 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_op_enable_0_out ; + end + (32'ha088 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_brdma_read_stall_0_out ; + end + (32'ha080 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_enable_0_out ; + end + (32'ha090 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_erdma_read_stall_0_out ; + end + (32'ha084 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_mrdma_read_stall_0_out ; + end + (32'ha08c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_perf_nrdma_read_stall_0_out ; + end + (32'ha01c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_base_addr_high_0_out ; + end + (32'ha018 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_base_addr_low_0_out ; + end + (32'ha074 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_dma_cfg_0_out ; + end + (32'ha020 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_line_stride_0_out ; + end + (32'ha024 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_src_surface_stride_0_out ; + end + (32'ha07c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_status_inf_input_num_0_out ; + end + (32'ha078 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_d_status_nan_input_num_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bn_base_addr_high[31:0] <= 32'h0; + bn_base_addr_low[31:0] <= {(32){1'b0}}; + bn_batch_stride[31:0] <= {(32){1'b0}}; + bn_line_stride[31:0] <= {(32){1'b0}}; + bn_surface_stride[31:0] <= {(32){1'b0}}; + brdma_data_mode <= 1'b0; + brdma_data_size <= 1'b0; + brdma_data_use[1:0] <= 2'b00; + brdma_disable <= 1'b1; + brdma_ram_type <= 1'b0; + bs_base_addr_high[31:0] <= 32'h0; + bs_base_addr_low[31:0] <= {(32){1'b0}}; + bs_batch_stride[31:0] <= {(32){1'b0}}; + bs_line_stride[31:0] <= {(32){1'b0}}; + bs_surface_stride[31:0] <= {(32){1'b0}}; + channel[12:0] <= 13'b0000000000000; + height[12:0] <= 13'b0000000000000; + width[12:0] <= 13'b0000000000000; + erdma_data_mode <= 1'b0; + erdma_data_size <= 1'b0; + erdma_data_use[1:0] <= 2'b00; + erdma_disable <= 1'b1; + erdma_ram_type <= 1'b0; + ew_base_addr_high[31:0] <= 32'h0; + ew_base_addr_low[31:0] <= {(32){1'b0}}; + ew_batch_stride[31:0] <= {(32){1'b0}}; + ew_line_stride[31:0] <= {(32){1'b0}}; + ew_surface_stride[31:0] <= {(32){1'b0}}; + batch_number[4:0] <= 5'b00000; + flying_mode <= 1'b0; + in_precision[1:0] <= 2'b01; + out_precision[1:0] <= 2'b00; + proc_precision[1:0] <= 2'b01; + winograd <= 1'b0; + nrdma_data_mode <= 1'b0; + nrdma_data_size <= 1'b0; + nrdma_data_use[1:0] <= 2'b00; + nrdma_disable <= 1'b1; + nrdma_ram_type <= 1'b0; + perf_dma_en <= 1'b0; + perf_nan_inf_count_en <= 1'b0; + src_base_addr_high[31:0] <= 32'h0; + src_base_addr_low[31:0] <= {(32){1'b0}}; + src_ram_type <= 1'b0; + src_line_stride[31:0] <= {(32){1'b0}}; + src_surface_stride[31:0] <= {(32){1'b0}}; + end else begin +// Register: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 Field: bn_base_addr_high + if (nvdla_sdp_rdma_d_bn_base_addr_high_0_wren) begin + bn_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_LOW_0 Field: bn_base_addr_low + if (nvdla_sdp_rdma_d_bn_base_addr_low_0_wren) begin + bn_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_BATCH_STRIDE_0 Field: bn_batch_stride + if (nvdla_sdp_rdma_d_bn_batch_stride_0_wren) begin + bn_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_LINE_STRIDE_0 Field: bn_line_stride + if (nvdla_sdp_rdma_d_bn_line_stride_0_wren) begin + bn_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BN_SURFACE_STRIDE_0 Field: bn_surface_stride + if (nvdla_sdp_rdma_d_bn_surface_stride_0_wren) begin + bn_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_data_mode + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_data_mode <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_data_size + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_data_size <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_data_use + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_data_use[1:0] <= reg_wr_data[2:1]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_disable + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_disable <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 Field: brdma_ram_type + if (nvdla_sdp_rdma_d_brdma_cfg_0_wren) begin + brdma_ram_type <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 Field: bs_base_addr_high + if (nvdla_sdp_rdma_d_bs_base_addr_high_0_wren) begin + bs_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_LOW_0 Field: bs_base_addr_low + if (nvdla_sdp_rdma_d_bs_base_addr_low_0_wren) begin + bs_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_BATCH_STRIDE_0 Field: bs_batch_stride + if (nvdla_sdp_rdma_d_bs_batch_stride_0_wren) begin + bs_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_LINE_STRIDE_0 Field: bs_line_stride + if (nvdla_sdp_rdma_d_bs_line_stride_0_wren) begin + bs_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_BS_SURFACE_STRIDE_0 Field: bs_surface_stride + if (nvdla_sdp_rdma_d_bs_surface_stride_0_wren) begin + bs_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_DATA_CUBE_CHANNEL_0 Field: channel + if (nvdla_sdp_rdma_d_data_cube_channel_0_wren) begin + channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_RDMA_D_DATA_CUBE_HEIGHT_0 Field: height + if (nvdla_sdp_rdma_d_data_cube_height_0_wren) begin + height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_RDMA_D_DATA_CUBE_WIDTH_0 Field: width + if (nvdla_sdp_rdma_d_data_cube_width_0_wren) begin + width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_data_mode + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_data_mode <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_data_size + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_data_size <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_data_use + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_data_use[1:0] <= reg_wr_data[2:1]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_disable + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_disable <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 Field: erdma_ram_type + if (nvdla_sdp_rdma_d_erdma_cfg_0_wren) begin + erdma_ram_type <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 Field: ew_base_addr_high + if (nvdla_sdp_rdma_d_ew_base_addr_high_0_wren) begin + ew_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_LOW_0 Field: ew_base_addr_low + if (nvdla_sdp_rdma_d_ew_base_addr_low_0_wren) begin + ew_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_BATCH_STRIDE_0 Field: ew_batch_stride + if (nvdla_sdp_rdma_d_ew_batch_stride_0_wren) begin + ew_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_LINE_STRIDE_0 Field: ew_line_stride + if (nvdla_sdp_rdma_d_ew_line_stride_0_wren) begin + ew_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_EW_SURFACE_STRIDE_0 Field: ew_surface_stride + if (nvdla_sdp_rdma_d_ew_surface_stride_0_wren) begin + ew_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: batch_number + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + batch_number[4:0] <= reg_wr_data[12:8]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: flying_mode + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + flying_mode <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: in_precision + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + in_precision[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: out_precision + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + out_precision[1:0] <= reg_wr_data[7:6]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: proc_precision + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + proc_precision[1:0] <= reg_wr_data[5:4]; + end +// Register: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 Field: winograd + if (nvdla_sdp_rdma_d_feature_mode_cfg_0_wren) begin + winograd <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_data_mode + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_data_mode <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_data_size + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_data_size <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_data_use + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_data_use[1:0] <= reg_wr_data[2:1]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_disable + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_disable <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 Field: nrdma_ram_type + if (nvdla_sdp_rdma_d_nrdma_cfg_0_wren) begin + nrdma_ram_type <= reg_wr_data[5]; + end +// Not generating flops for field NVDLA_SDP_RDMA_D_OP_ENABLE_0::op_en (to be implemented outside) +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_BRDMA_READ_STALL_0::brdma_stall +// Register: NVDLA_SDP_RDMA_D_PERF_ENABLE_0 Field: perf_dma_en + if (nvdla_sdp_rdma_d_perf_enable_0_wren) begin + perf_dma_en <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_PERF_ENABLE_0 Field: perf_nan_inf_count_en + if (nvdla_sdp_rdma_d_perf_enable_0_wren) begin + perf_nan_inf_count_en <= reg_wr_data[1]; + end +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_ERDMA_READ_STALL_0::erdma_stall +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_MRDMA_READ_STALL_0::mrdma_stall +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_PERF_NRDMA_READ_STALL_0::nrdma_stall +// Register: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 Field: src_base_addr_high + if (nvdla_sdp_rdma_d_src_base_addr_high_0_wren) begin + src_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 Field: src_base_addr_low + if (nvdla_sdp_rdma_d_src_base_addr_low_0_wren) begin + src_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_DMA_CFG_0 Field: src_ram_type + if (nvdla_sdp_rdma_d_src_dma_cfg_0_wren) begin + src_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_LINE_STRIDE_0 Field: src_line_stride + if (nvdla_sdp_rdma_d_src_line_stride_0_wren) begin + src_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_RDMA_D_SRC_SURFACE_STRIDE_0 Field: src_surface_stride + if (nvdla_sdp_rdma_d_src_surface_stride_0_wren) begin + src_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_STATUS_INF_INPUT_NUM_0::status_inf_input_num +// Not generating flops for read-only field NVDLA_SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0::status_nan_input_num + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'ha048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_base_addr_high_0_out, nvdla_sdp_rdma_d_bn_base_addr_high_0_out); + (32'ha044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_base_addr_low_0_out, nvdla_sdp_rdma_d_bn_base_addr_low_0_out); + (32'ha054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_batch_stride_0_out, nvdla_sdp_rdma_d_bn_batch_stride_0_out); + (32'ha04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_line_stride_0_out, nvdla_sdp_rdma_d_bn_line_stride_0_out); + (32'ha050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BN_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bn_surface_stride_0_out, nvdla_sdp_rdma_d_bn_surface_stride_0_out); + (32'ha028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BRDMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_brdma_cfg_0_out, nvdla_sdp_rdma_d_brdma_cfg_0_out); + (32'ha030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_base_addr_high_0_out, nvdla_sdp_rdma_d_bs_base_addr_high_0_out); + (32'ha02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_base_addr_low_0_out, nvdla_sdp_rdma_d_bs_base_addr_low_0_out); + (32'ha03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_batch_stride_0_out, nvdla_sdp_rdma_d_bs_batch_stride_0_out); + (32'ha034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_line_stride_0_out, nvdla_sdp_rdma_d_bs_line_stride_0_out); + (32'ha038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_BS_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_bs_surface_stride_0_out, nvdla_sdp_rdma_d_bs_surface_stride_0_out); + (32'ha014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_DATA_CUBE_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_data_cube_channel_0_out, nvdla_sdp_rdma_d_data_cube_channel_0_out); + (32'ha010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_DATA_CUBE_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_data_cube_height_0_out, nvdla_sdp_rdma_d_data_cube_height_0_out); + (32'ha00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_DATA_CUBE_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_data_cube_width_0_out, nvdla_sdp_rdma_d_data_cube_width_0_out); + (32'ha058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_ERDMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_erdma_cfg_0_out, nvdla_sdp_rdma_d_erdma_cfg_0_out); + (32'ha060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_base_addr_high_0_out, nvdla_sdp_rdma_d_ew_base_addr_high_0_out); + (32'ha05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_base_addr_low_0_out, nvdla_sdp_rdma_d_ew_base_addr_low_0_out); + (32'ha06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_batch_stride_0_out, nvdla_sdp_rdma_d_ew_batch_stride_0_out); + (32'ha064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_line_stride_0_out, nvdla_sdp_rdma_d_ew_line_stride_0_out); + (32'ha068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_EW_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_ew_surface_stride_0_out, nvdla_sdp_rdma_d_ew_surface_stride_0_out); + (32'ha070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_FEATURE_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_feature_mode_cfg_0_out, nvdla_sdp_rdma_d_feature_mode_cfg_0_out); + (32'ha040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_NRDMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_nrdma_cfg_0_out, nvdla_sdp_rdma_d_nrdma_cfg_0_out); + (32'ha008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_op_enable_0_out, nvdla_sdp_rdma_d_op_enable_0_out); + (32'ha088 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_BRDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_perf_enable_0_out, nvdla_sdp_rdma_d_perf_enable_0_out); + (32'ha090 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_ERDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha084 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_MRDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha08c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_PERF_NRDMA_READ_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_base_addr_high_0_out, nvdla_sdp_rdma_d_src_base_addr_high_0_out); + (32'ha018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_base_addr_low_0_out, nvdla_sdp_rdma_d_src_base_addr_low_0_out); + (32'ha074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_dma_cfg_0_out, nvdla_sdp_rdma_d_src_dma_cfg_0_out); + (32'ha020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_line_stride_0_out, nvdla_sdp_rdma_d_src_line_stride_0_out); + (32'ha024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_D_SRC_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_d_src_surface_stride_0_out, nvdla_sdp_rdma_d_src_surface_stride_0_out); + (32'ha07c & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_STATUS_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'ha078 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_RDMA_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v new file mode 100644 index 0000000..e5bfd8b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_REG_single.v +module NV_NVDLA_SDP_RDMA_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_sdp_rdma_s_pointer_0_out; +wire [31:0] nvdla_sdp_rdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_rdma_s_pointer_0_wren = (reg_offset_wr == (32'ha004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_s_status_0_wren = (reg_offset_wr == (32'ha000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_rdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_sdp_rdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_rdma_s_pointer_0_out + or nvdla_sdp_rdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'ha004 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_s_pointer_0_out ; + end + (32'ha000 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_SDP_RDMA_S_POINTER_0::consumer +// Register: NVDLA_SDP_RDMA_S_POINTER_0 Field: producer + if (nvdla_sdp_rdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_SDP_RDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_SDP_RDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'ha004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_s_pointer_0_out, nvdla_sdp_rdma_s_pointer_0_out); + (32'ha000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_RDMA_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v.vcp new file mode 100644 index 0000000..e5bfd8b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v.vcp @@ -0,0 +1,121 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_REG_single.v +module NV_NVDLA_SDP_RDMA_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,producer + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_sdp_rdma_s_pointer_0_out; +wire [31:0] nvdla_sdp_rdma_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output producer; +// Read-only register inputs +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_rdma_s_pointer_0_wren = (reg_offset_wr == (32'ha004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_rdma_s_status_0_wren = (reg_offset_wr == (32'ha000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_rdma_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_sdp_rdma_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_rdma_s_pointer_0_out + or nvdla_sdp_rdma_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'ha004 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_s_pointer_0_out ; + end + (32'ha000 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_rdma_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + producer <= 1'b0; + end else begin +// Not generating flops for read-only field NVDLA_SDP_RDMA_S_POINTER_0::consumer +// Register: NVDLA_SDP_RDMA_S_POINTER_0 Field: producer + if (nvdla_sdp_rdma_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_SDP_RDMA_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_SDP_RDMA_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'ha004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_RDMA_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_rdma_s_pointer_0_out, nvdla_sdp_rdma_s_pointer_0_out); + (32'ha000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_RDMA_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_RDMA_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_dmaif.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_dmaif.v new file mode 100644 index 0000000..e8f9f8d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_dmaif.v @@ -0,0 +1,84 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_dmaif.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_dmaif ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,dma_rd_req_ram_type //|< i + ,dma_rd_req_pd //|< i + ,dma_rd_req_vld //|< i + ,dma_rd_req_rdy //|> o + ,dma_rd_rsp_ram_type //|< i + ,dma_rd_rsp_pd //|> o + ,dma_rd_rsp_vld //|> o + ,dma_rd_rsp_rdy //|< i + ,dma_rd_cdt_lat_fifo_pop //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output [47 -1:0] sdp2mcif_rd_req_pd; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +input [65 -1:0] mcif2sdp_rd_rsp_pd; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +output sdp2mcif_rd_cdt_lat_fifo_pop; +input dma_rd_req_ram_type; +input dma_rd_req_vld; +output dma_rd_req_rdy; +input [47 -1:0] dma_rd_req_pd; +input dma_rd_rsp_ram_type; +output [65 -1:0] dma_rd_rsp_pd; +output dma_rd_rsp_vld; +input dma_rd_rsp_rdy; +input dma_rd_cdt_lat_fifo_pop; +reg sdp2mcif_rd_cdt_lat_fifo_pop; +NV_NVDLA_DMAIF_rdreq NV_NVDLA_SDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (dma_rd_req_ram_type) + ,.mcif_rd_req_pd (sdp2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_SDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2sdp_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2sdp_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2sdp_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + sdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1); + end +end +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_dmaif.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_dmaif.v.vcp new file mode 100644 index 0000000..e8f9f8d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_dmaif.v.vcp @@ -0,0 +1,84 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_dmaif.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_dmaif ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,dma_rd_req_ram_type //|< i + ,dma_rd_req_pd //|< i + ,dma_rd_req_vld //|< i + ,dma_rd_req_rdy //|> o + ,dma_rd_rsp_ram_type //|< i + ,dma_rd_rsp_pd //|> o + ,dma_rd_rsp_vld //|> o + ,dma_rd_rsp_rdy //|< i + ,dma_rd_cdt_lat_fifo_pop //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output [47 -1:0] sdp2mcif_rd_req_pd; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +input [65 -1:0] mcif2sdp_rd_rsp_pd; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +output sdp2mcif_rd_cdt_lat_fifo_pop; +input dma_rd_req_ram_type; +input dma_rd_req_vld; +output dma_rd_req_rdy; +input [47 -1:0] dma_rd_req_pd; +input dma_rd_rsp_ram_type; +output [65 -1:0] dma_rd_rsp_pd; +output dma_rd_rsp_vld; +input dma_rd_rsp_rdy; +input dma_rd_cdt_lat_fifo_pop; +reg sdp2mcif_rd_cdt_lat_fifo_pop; +NV_NVDLA_DMAIF_rdreq NV_NVDLA_SDP_RDMA_rdreq( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.reg2dp_src_ram_type (dma_rd_req_ram_type) + ,.mcif_rd_req_pd (sdp2mcif_rd_req_pd ) + ,.mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.dmaif_rd_req_pd (dma_rd_req_pd ) + ,.dmaif_rd_req_vld (dma_rd_req_vld ) + ,.dmaif_rd_req_rdy (dma_rd_req_rdy ) +); +NV_NVDLA_DMAIF_rdrsp NV_NVDLA_SDP_RDMA_rdrsp( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.mcif_rd_rsp_pd (mcif2sdp_rd_rsp_pd ) + ,.mcif_rd_rsp_valid (mcif2sdp_rd_rsp_valid ) + ,.mcif_rd_rsp_ready (mcif2sdp_rd_rsp_ready ) + ,.dmaif_rd_rsp_pd (dma_rd_rsp_pd ) + ,.dmaif_rd_rsp_pvld (dma_rd_rsp_vld ) + ,.dmaif_rd_rsp_prdy (dma_rd_rsp_rdy ) +); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2mcif_rd_cdt_lat_fifo_pop <= 1'b0; + end else begin + sdp2mcif_rd_cdt_lat_fifo_pop <= dma_rd_cdt_lat_fifo_pop & (dma_rd_rsp_ram_type == 1'b1); + end +end +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v new file mode 100644 index 0000000..2623fd7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v @@ -0,0 +1,471 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_RDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,eg_done //|> o + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,cq2eg_prdy //|> o + ,lat_fifo_rd_pd //|< i + ,lat_fifo_rd_pvld //|< i + ,lat_fifo_rd_prdy //|> o + ,dma_rd_cdt_lat_fifo_pop //|> o + ,sdp_rdma2dp_alu_pd //|> o + ,sdp_rdma2dp_alu_valid //|> o + ,sdp_rdma2dp_alu_ready //|< i + ,sdp_rdma2dp_mul_pd //|> o + ,sdp_rdma2dp_mul_valid //|> o + ,sdp_rdma2dp_mul_ready //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_rdma_data_mode //|< i + ,reg2dp_rdma_data_size //|< i + ,reg2dp_rdma_data_use //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +output eg_done; +input [15:0] cq2eg_pd; +input cq2eg_pvld; +output cq2eg_prdy; +input [65 -1:0] lat_fifo_rd_pd; +input lat_fifo_rd_pvld; +output lat_fifo_rd_prdy; +output dma_rd_cdt_lat_fifo_pop; +output [8*16:0] sdp_rdma2dp_alu_pd; +output sdp_rdma2dp_alu_valid; +input sdp_rdma2dp_alu_ready; +output [8*16:0] sdp_rdma2dp_mul_pd; +output sdp_rdma2dp_mul_valid; +input sdp_rdma2dp_mul_ready; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_proc_precision; +input [1:0] reg2dp_out_precision; +input reg2dp_rdma_data_mode; +input reg2dp_rdma_data_size; +input [1:0] reg2dp_rdma_data_use; +wire cfg_alu_en; +wire cfg_mul_en; +wire cfg_do_8; +wire cfg_dp_8; +wire cfg_data_size_1byte; +wire cfg_data_size_2byte; +wire cfg_mode_1bytex1; +wire cfg_mode_1bytex2; +wire cfg_mode_2bytex1; +wire cfg_mode_2bytex2; +wire cfg_mode_alu_only; +wire cfg_mode_both; +wire cfg_mode_mul_only; +wire cfg_mode_per_element; +wire cfg_mode_single; +reg cq2eg_prdy_hold; +wire ig2eg_cube_end; +wire [14:0] ig2eg_size; +wire [15:0] beat_size; +reg [14:0] beat_count; +wire [15:0] beat_count_nxt; +reg mon_beat_count; +wire is_last_beat; +wire is_beat_end; +wire layer_done; +wire mul_layer_end; +wire mul_roc_rdy; +wire mul_roc_vld; +wire mul_rod_rdy; +wire mul_rod_vld; +reg alu_layer_done; +reg alu_roc_en; +reg eg_done; +reg mul_layer_done; +reg mul_roc_en; +wire alu_layer_end; +wire alu_roc_rdy; +wire alu_roc_vld; +wire alu_rod_rdy; +wire alu_rod_vld; +wire [4*8*8 +3:0] unpack_out_pd; +wire unpack_out_pvld; +wire unpack_out_prdy; +wire [8*8 -1:0] mode_1bytex2_alu_rod0_pd; +wire [8*8 -1:0] mode_1bytex2_alu_rod1_pd; +wire [8*8 -1:0] mode_2bytex2_alu_rod0_pd; +wire [8*8 -1:0] mode_2bytex2_alu_rod1_pd; +wire [8*8 -1:0] mode_1bytex2_mul_rod0_pd; +wire [8*8 -1:0] mode_1bytex2_mul_rod1_pd; +wire [8*8 -1:0] mode_2bytex2_mul_rod0_pd; +wire [8*8 -1:0] mode_2bytex2_mul_rod1_pd; +//============== +// CFG REG +//============== +assign cfg_data_size_1byte = reg2dp_rdma_data_size == 1'h0 ; +assign cfg_data_size_2byte = reg2dp_rdma_data_size == 1'h1 ; +assign cfg_mode_mul_only = reg2dp_rdma_data_use == 2'h0 ; +assign cfg_mode_alu_only = reg2dp_rdma_data_use == 2'h1 ; +assign cfg_mode_both = reg2dp_rdma_data_use == 2'h2 ; +assign cfg_mode_per_element = reg2dp_rdma_data_mode == 1'h1 ; +assign cfg_mode_single = cfg_mode_mul_only || cfg_mode_alu_only; +assign cfg_mode_1bytex1 = cfg_data_size_1byte & cfg_mode_single; +assign cfg_mode_2bytex1 = cfg_data_size_2byte & cfg_mode_single; +assign cfg_mode_1bytex2 = cfg_data_size_1byte & cfg_mode_both; +assign cfg_mode_2bytex2 = cfg_data_size_2byte & cfg_mode_both; +assign cfg_dp_8 = reg2dp_proc_precision== 0 ; +assign cfg_do_8 = reg2dp_out_precision== 0 ; +assign cfg_alu_en = cfg_mode_alu_only || cfg_mode_both; +assign cfg_mul_en = cfg_mode_mul_only || cfg_mode_both; +//============== +// DMA Interface +//============== +assign dma_rd_cdt_lat_fifo_pop = lat_fifo_rd_pvld & lat_fifo_rd_prdy; +//============== +// Latency FIFO to buffer return DATA +//============== +wire [3:0] lat_fifo_rd_mask = {{(4-1){1'b0}},lat_fifo_rd_pd[65 -1:64]}; +wire [2:0] lat_fifo_rd_size = lat_fifo_rd_mask[3]+lat_fifo_rd_mask[2]+lat_fifo_rd_mask[1]+lat_fifo_rd_mask[0]; +//================================================================== +// Context Queue: read +//================================================================== +assign cq2eg_prdy = is_beat_end; +assign ig2eg_size[14:0] = cq2eg_pd[14:0]; +assign ig2eg_cube_end = cq2eg_pd[15]; +assign beat_size = ig2eg_size+1; +assign beat_count_nxt = beat_count+lat_fifo_rd_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_count,beat_count} <= 16'h0; + end else begin + if (lat_fifo_rd_pvld & lat_fifo_rd_prdy) begin + if (is_last_beat) begin + {mon_beat_count,beat_count} <= 16'h0; + end else begin + {mon_beat_count,beat_count} <= beat_count_nxt; + end + end + end +end +assign is_last_beat = (beat_count_nxt == beat_size); +assign is_beat_end = is_last_beat & lat_fifo_rd_pvld & lat_fifo_rd_prdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"info in CQ there be there when return data come") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (!cq2eg_pvld) & lat_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +/////////combine lat fifo pd to 4*atomic_m*bpe////// +wire lat_fifo_rd_beat_end = is_last_beat; +NV_NVDLA_SDP_RDMA_unpack u_rdma_unpack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.inp_data (lat_fifo_rd_pd[65 -1:0]) + ,.inp_pvld (lat_fifo_rd_pvld) + ,.inp_prdy (lat_fifo_rd_prdy) + ,.inp_end (lat_fifo_rd_beat_end) + ,.out_data (unpack_out_pd[4*8*8 +3:0]) + ,.out_pvld (unpack_out_pvld) + ,.out_prdy (unpack_out_prdy) + ); +wire [3:0] unpack_out_mask = unpack_out_pd[4*8*8 +3:4*8*8]; +assign unpack_out_prdy = cfg_mode_both ? alu_rod_rdy & mul_rod_rdy : cfg_mode_alu_only ? alu_rod_rdy : mul_rod_rdy; +//============================================================ +// Re-Order FIFO to send data to SDP-core +//============================================================ +// |----------------------------------------------------| +// | 16B | 16B | 16B | 16B | +// MODE |----------------------------------------------------| +// | 0 1 2 3 | +// 1Bx1 | ALU or MUL | ALU or MUL | ALU or MUL or ALU or MUL | +// |----------------------------------------------------| +// | 0 | 1 | +// 2Bx1 | ALU or MUL | ALU or MUL | +// |====================================================| +// | 0 | 1 | +// 1Bx2 | ALU | MUL | ALU | MUL | +// |----------------------------------------------------| +// | 0 | 1 | +// 2Bx2 | ALU | MUL | +// |----------------------------------------------------| +//============================================================ +//: my $k = 8; +//: foreach my $i (0..${k}-1) { +//: my $j = ${i}*2; +//: print "assign mode_1bytex2_alu_rod0_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${j}+7: 8*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: my $jj = ${i}*2+$k*2; +//: print "assign mode_1bytex2_alu_rod1_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${jj}+7: 8*${jj}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $j = ${i}*2; +//: print "assign mode_2bytex2_alu_rod0_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${j}+15: 16*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $jj = ${i}*2+$k; +//: print "assign mode_2bytex2_alu_rod1_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${jj}+15: 16*${jj}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: my $j = ${i}*2+1; +//: print "assign mode_1bytex2_mul_rod0_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${j}+7: 8*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: my $jj = ${i}*2+1+$k*2; +//: print "assign mode_1bytex2_mul_rod1_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${jj}+7: 8*${jj}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $j = ${i}*2+1; +//: print "assign mode_2bytex2_mul_rod0_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${j}+15: 16*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $jj = ${i}*2+1+$k; +//: print "assign mode_2bytex2_mul_rod1_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${jj}+15: 16*${jj}]; \n"; +//: } +//: print "\n"; +//| eperl: generated_beg (DO NOT EDIT BELOW) +assign mode_1bytex2_alu_rod0_pd[8*0+7:8*0] = unpack_out_pd[8*0+7: 8*0]; +assign mode_1bytex2_alu_rod0_pd[8*1+7:8*1] = unpack_out_pd[8*2+7: 8*2]; +assign mode_1bytex2_alu_rod0_pd[8*2+7:8*2] = unpack_out_pd[8*4+7: 8*4]; +assign mode_1bytex2_alu_rod0_pd[8*3+7:8*3] = unpack_out_pd[8*6+7: 8*6]; +assign mode_1bytex2_alu_rod0_pd[8*4+7:8*4] = unpack_out_pd[8*8+7: 8*8]; +assign mode_1bytex2_alu_rod0_pd[8*5+7:8*5] = unpack_out_pd[8*10+7: 8*10]; +assign mode_1bytex2_alu_rod0_pd[8*6+7:8*6] = unpack_out_pd[8*12+7: 8*12]; +assign mode_1bytex2_alu_rod0_pd[8*7+7:8*7] = unpack_out_pd[8*14+7: 8*14]; + +assign mode_1bytex2_alu_rod1_pd[8*0+7:8*0] = unpack_out_pd[8*16+7: 8*16]; +assign mode_1bytex2_alu_rod1_pd[8*1+7:8*1] = unpack_out_pd[8*18+7: 8*18]; +assign mode_1bytex2_alu_rod1_pd[8*2+7:8*2] = unpack_out_pd[8*20+7: 8*20]; +assign mode_1bytex2_alu_rod1_pd[8*3+7:8*3] = unpack_out_pd[8*22+7: 8*22]; +assign mode_1bytex2_alu_rod1_pd[8*4+7:8*4] = unpack_out_pd[8*24+7: 8*24]; +assign mode_1bytex2_alu_rod1_pd[8*5+7:8*5] = unpack_out_pd[8*26+7: 8*26]; +assign mode_1bytex2_alu_rod1_pd[8*6+7:8*6] = unpack_out_pd[8*28+7: 8*28]; +assign mode_1bytex2_alu_rod1_pd[8*7+7:8*7] = unpack_out_pd[8*30+7: 8*30]; + +assign mode_2bytex2_alu_rod0_pd[16*0+15:16*0] = unpack_out_pd[16*0+15: 16*0]; +assign mode_2bytex2_alu_rod0_pd[16*1+15:16*1] = unpack_out_pd[16*2+15: 16*2]; +assign mode_2bytex2_alu_rod0_pd[16*2+15:16*2] = unpack_out_pd[16*4+15: 16*4]; +assign mode_2bytex2_alu_rod0_pd[16*3+15:16*3] = unpack_out_pd[16*6+15: 16*6]; + +assign mode_2bytex2_alu_rod1_pd[16*0+15:16*0] = unpack_out_pd[16*8+15: 16*8]; +assign mode_2bytex2_alu_rod1_pd[16*1+15:16*1] = unpack_out_pd[16*10+15: 16*10]; +assign mode_2bytex2_alu_rod1_pd[16*2+15:16*2] = unpack_out_pd[16*12+15: 16*12]; +assign mode_2bytex2_alu_rod1_pd[16*3+15:16*3] = unpack_out_pd[16*14+15: 16*14]; + +assign mode_1bytex2_mul_rod0_pd[8*0+7:8*0] = unpack_out_pd[8*1+7: 8*1]; +assign mode_1bytex2_mul_rod0_pd[8*1+7:8*1] = unpack_out_pd[8*3+7: 8*3]; +assign mode_1bytex2_mul_rod0_pd[8*2+7:8*2] = unpack_out_pd[8*5+7: 8*5]; +assign mode_1bytex2_mul_rod0_pd[8*3+7:8*3] = unpack_out_pd[8*7+7: 8*7]; +assign mode_1bytex2_mul_rod0_pd[8*4+7:8*4] = unpack_out_pd[8*9+7: 8*9]; +assign mode_1bytex2_mul_rod0_pd[8*5+7:8*5] = unpack_out_pd[8*11+7: 8*11]; +assign mode_1bytex2_mul_rod0_pd[8*6+7:8*6] = unpack_out_pd[8*13+7: 8*13]; +assign mode_1bytex2_mul_rod0_pd[8*7+7:8*7] = unpack_out_pd[8*15+7: 8*15]; + +assign mode_1bytex2_mul_rod1_pd[8*0+7:8*0] = unpack_out_pd[8*17+7: 8*17]; +assign mode_1bytex2_mul_rod1_pd[8*1+7:8*1] = unpack_out_pd[8*19+7: 8*19]; +assign mode_1bytex2_mul_rod1_pd[8*2+7:8*2] = unpack_out_pd[8*21+7: 8*21]; +assign mode_1bytex2_mul_rod1_pd[8*3+7:8*3] = unpack_out_pd[8*23+7: 8*23]; +assign mode_1bytex2_mul_rod1_pd[8*4+7:8*4] = unpack_out_pd[8*25+7: 8*25]; +assign mode_1bytex2_mul_rod1_pd[8*5+7:8*5] = unpack_out_pd[8*27+7: 8*27]; +assign mode_1bytex2_mul_rod1_pd[8*6+7:8*6] = unpack_out_pd[8*29+7: 8*29]; +assign mode_1bytex2_mul_rod1_pd[8*7+7:8*7] = unpack_out_pd[8*31+7: 8*31]; + +assign mode_2bytex2_mul_rod0_pd[16*0+15:16*0] = unpack_out_pd[16*1+15: 16*1]; +assign mode_2bytex2_mul_rod0_pd[16*1+15:16*1] = unpack_out_pd[16*3+15: 16*3]; +assign mode_2bytex2_mul_rod0_pd[16*2+15:16*2] = unpack_out_pd[16*5+15: 16*5]; +assign mode_2bytex2_mul_rod0_pd[16*3+15:16*3] = unpack_out_pd[16*7+15: 16*7]; + +assign mode_2bytex2_mul_rod1_pd[16*0+15:16*0] = unpack_out_pd[16*9+15: 16*9]; +assign mode_2bytex2_mul_rod1_pd[16*1+15:16*1] = unpack_out_pd[16*11+15: 16*11]; +assign mode_2bytex2_mul_rod1_pd[16*2+15:16*2] = unpack_out_pd[16*13+15: 16*13]; +assign mode_2bytex2_mul_rod1_pd[16*3+15:16*3] = unpack_out_pd[16*15+15: 16*15]; + + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8*8 -1:0] alu_rod0_pd = cfg_mode_2bytex2 ? mode_2bytex2_alu_rod0_pd : cfg_mode_1bytex2 ? mode_1bytex2_alu_rod0_pd : unpack_out_pd[(8*8*0+8*8 -1):8*8*0]; +wire [8*8 -1:0] alu_rod1_pd = cfg_mode_2bytex2 ? mode_2bytex2_alu_rod1_pd : cfg_mode_1bytex2 ? mode_1bytex2_alu_rod1_pd : unpack_out_pd[(8*8*1+8*8 -1):8*8*1]; +wire [8*8 -1:0] alu_rod2_pd = unpack_out_pd[(8*8*2+8*8 -1):8*8*2]; +wire [8*8 -1:0] alu_rod3_pd = unpack_out_pd[(8*8*3+8*8 -1):8*8*3]; +wire [8*8 -1:0] mul_rod0_pd = cfg_mode_2bytex2 ? mode_2bytex2_mul_rod0_pd : cfg_mode_1bytex2 ? mode_1bytex2_mul_rod0_pd : unpack_out_pd[(8*8*0+8*8 -1):8*8*0]; +wire [8*8 -1:0] mul_rod1_pd = cfg_mode_2bytex2 ? mode_2bytex2_mul_rod1_pd : cfg_mode_1bytex2 ? mode_1bytex2_mul_rod1_pd : unpack_out_pd[(8*8*1+8*8 -1):8*8*1]; +wire [8*8 -1:0] mul_rod2_pd = unpack_out_pd[(8*8*2+8*8 -1):8*8*2]; +wire [8*8 -1:0] mul_rod3_pd = unpack_out_pd[(8*8*3+8*8 -1):8*8*3]; +wire [3:0] alu_rod_mask = cfg_mode_both ? {2'h0,unpack_out_mask[2],unpack_out_mask[0]} : unpack_out_mask[3:0]; +wire [3:0] mul_rod_mask = cfg_mode_both ? {2'h0,unpack_out_mask[2],unpack_out_mask[0]} : unpack_out_mask[3:0]; +wire [2:0] alu_roc_size = alu_rod_mask[3] + alu_rod_mask[2] + alu_rod_mask[1] + alu_rod_mask[0]; +wire [2:0] mul_roc_size = mul_rod_mask[3] + mul_rod_mask[2] + mul_rod_mask[1] + mul_rod_mask[0]; +assign alu_rod_vld = cfg_alu_en & unpack_out_pvld & (cfg_mode_both ? mul_rod_rdy : 1'b1); +assign mul_rod_vld = cfg_mul_en & unpack_out_pvld & (cfg_mode_both ? alu_rod_rdy : 1'b1); +assign alu_roc_vld = cfg_alu_en & unpack_out_pvld & (cfg_mode_both ? mul_roc_rdy & mul_rod_rdy & alu_rod_rdy : alu_rod_rdy); +assign mul_roc_vld = cfg_mul_en & unpack_out_pvld & (cfg_mode_both ? alu_roc_rdy & mul_rod_rdy & alu_rod_rdy : mul_rod_rdy); +wire [1:0] alu_roc_pd,mul_roc_pd; +wire mon_alu_roc_c,mon_mul_roc_c; +assign {mon_alu_roc_c,alu_roc_pd} = alu_roc_size -1; +assign {mon_mul_roc_c,mul_roc_pd} = mul_roc_size -1; +//assert: alu_rod_vld & !alu_roc_rdy +////////////////split unpack pd to 4 atomic_m alu or mul data ///////////////////// +NV_NVDLA_SDP_RDMA_EG_ro u_alu ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sdp_rdma2dp_valid (sdp_rdma2dp_alu_valid) + ,.sdp_rdma2dp_ready (sdp_rdma2dp_alu_ready) + ,.sdp_rdma2dp_pd (sdp_rdma2dp_alu_pd[8*16:0]) + ,.rod0_wr_pd (alu_rod0_pd[8*8 -1:0]) + ,.rod1_wr_pd (alu_rod1_pd[8*8 -1:0]) + ,.rod2_wr_pd (alu_rod2_pd[8*8 -1:0]) + ,.rod3_wr_pd (alu_rod3_pd[8*8 -1:0]) + ,.rod_wr_mask (alu_rod_mask[3:0]) + ,.rod_wr_vld (alu_rod_vld) + ,.rod_wr_rdy (alu_rod_rdy) + ,.roc_wr_pd (alu_roc_pd[1:0]) + ,.roc_wr_vld (alu_roc_vld) + ,.roc_wr_rdy (alu_roc_rdy) + ,.cfg_dp_8 (cfg_dp_8) + ,.cfg_dp_size_1byte (cfg_data_size_1byte) + ,.cfg_mode_per_element (cfg_mode_per_element) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.layer_end (alu_layer_end) + ); +NV_NVDLA_SDP_RDMA_EG_ro u_mul ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sdp_rdma2dp_valid (sdp_rdma2dp_mul_valid) + ,.sdp_rdma2dp_ready (sdp_rdma2dp_mul_ready) + ,.sdp_rdma2dp_pd (sdp_rdma2dp_mul_pd[8*16:0]) + ,.rod0_wr_pd (mul_rod0_pd[8*8 -1:0]) + ,.rod1_wr_pd (mul_rod1_pd[8*8 -1:0]) + ,.rod2_wr_pd (mul_rod2_pd[8*8 -1:0]) + ,.rod3_wr_pd (mul_rod3_pd[8*8 -1:0]) + ,.rod_wr_mask (mul_rod_mask[3:0]) + ,.rod_wr_vld (mul_rod_vld) + ,.rod_wr_rdy (mul_rod_rdy) + ,.roc_wr_pd (mul_roc_pd[1:0]) + ,.roc_wr_vld (mul_roc_vld) + ,.roc_wr_rdy (mul_roc_rdy) + ,.cfg_dp_8 (cfg_dp_8) + ,.cfg_dp_size_1byte (cfg_data_size_1byte) + ,.cfg_mode_per_element (cfg_mode_per_element) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.layer_end (mul_layer_end) + ); +//========================================================== +// Layer Done +//========================================================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + alu_layer_done <= 1'b0; + end else begin + if (op_load) begin + if (cfg_alu_en) begin + alu_layer_done <= 1'b0; + end else begin + alu_layer_done <= 1'b1; + end + end else if (alu_layer_end) begin + alu_layer_done <= 1'b1; + end else if (layer_done) begin + alu_layer_done <= 1'b0; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_layer_done <= 1'b0; + end else begin + if (op_load) begin + if (cfg_mul_en) begin + mul_layer_done <= 1'b0; + end else begin + mul_layer_done <= 1'b1; + end + end else if (mul_layer_end) begin + mul_layer_done <= 1'b1; + end else if (layer_done) begin + mul_layer_done <= 1'b0; + end + end +end +assign layer_done = alu_layer_done & mul_layer_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg_done <= 1'b0; + end else begin + eg_done <= layer_done; + end +end +endmodule // NV_NVDLA_SDP_RDMA_eg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v.vcp new file mode 100644 index 0000000..4ad9f8f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v.vcp @@ -0,0 +1,412 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_eg.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_RDMA_eg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,eg_done //|> o + ,cq2eg_pd //|< i + ,cq2eg_pvld //|< i + ,cq2eg_prdy //|> o + ,lat_fifo_rd_pd //|< i + ,lat_fifo_rd_pvld //|< i + ,lat_fifo_rd_prdy //|> o + ,dma_rd_cdt_lat_fifo_pop //|> o + ,sdp_rdma2dp_alu_pd //|> o + ,sdp_rdma2dp_alu_valid //|> o + ,sdp_rdma2dp_alu_ready //|< i + ,sdp_rdma2dp_mul_pd //|> o + ,sdp_rdma2dp_mul_valid //|> o + ,sdp_rdma2dp_mul_ready //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_rdma_data_mode //|< i + ,reg2dp_rdma_data_size //|< i + ,reg2dp_rdma_data_use //|< i + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +output eg_done; +input [15:0] cq2eg_pd; +input cq2eg_pvld; +output cq2eg_prdy; +input [65 -1:0] lat_fifo_rd_pd; +input lat_fifo_rd_pvld; +output lat_fifo_rd_prdy; +output dma_rd_cdt_lat_fifo_pop; +output [8*16:0] sdp_rdma2dp_alu_pd; +output sdp_rdma2dp_alu_valid; +input sdp_rdma2dp_alu_ready; +output [8*16:0] sdp_rdma2dp_mul_pd; +output sdp_rdma2dp_mul_valid; +input sdp_rdma2dp_mul_ready; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_proc_precision; +input [1:0] reg2dp_out_precision; +input reg2dp_rdma_data_mode; +input reg2dp_rdma_data_size; +input [1:0] reg2dp_rdma_data_use; +wire cfg_alu_en; +wire cfg_mul_en; +wire cfg_do_8; +wire cfg_dp_8; +wire cfg_data_size_1byte; +wire cfg_data_size_2byte; +wire cfg_mode_1bytex1; +wire cfg_mode_1bytex2; +wire cfg_mode_2bytex1; +wire cfg_mode_2bytex2; +wire cfg_mode_alu_only; +wire cfg_mode_both; +wire cfg_mode_mul_only; +wire cfg_mode_per_element; +wire cfg_mode_single; +reg cq2eg_prdy_hold; +wire ig2eg_cube_end; +wire [14:0] ig2eg_size; +wire [15:0] beat_size; +reg [14:0] beat_count; +wire [15:0] beat_count_nxt; +reg mon_beat_count; +wire is_last_beat; +wire is_beat_end; +wire layer_done; +wire mul_layer_end; +wire mul_roc_rdy; +wire mul_roc_vld; +wire mul_rod_rdy; +wire mul_rod_vld; +reg alu_layer_done; +reg alu_roc_en; +reg eg_done; +reg mul_layer_done; +reg mul_roc_en; +wire alu_layer_end; +wire alu_roc_rdy; +wire alu_roc_vld; +wire alu_rod_rdy; +wire alu_rod_vld; +wire [4*8*8 +3:0] unpack_out_pd; +wire unpack_out_pvld; +wire unpack_out_prdy; +wire [8*8 -1:0] mode_1bytex2_alu_rod0_pd; +wire [8*8 -1:0] mode_1bytex2_alu_rod1_pd; +wire [8*8 -1:0] mode_2bytex2_alu_rod0_pd; +wire [8*8 -1:0] mode_2bytex2_alu_rod1_pd; +wire [8*8 -1:0] mode_1bytex2_mul_rod0_pd; +wire [8*8 -1:0] mode_1bytex2_mul_rod1_pd; +wire [8*8 -1:0] mode_2bytex2_mul_rod0_pd; +wire [8*8 -1:0] mode_2bytex2_mul_rod1_pd; +//============== +// CFG REG +//============== +assign cfg_data_size_1byte = reg2dp_rdma_data_size == 1'h0 ; +assign cfg_data_size_2byte = reg2dp_rdma_data_size == 1'h1 ; +assign cfg_mode_mul_only = reg2dp_rdma_data_use == 2'h0 ; +assign cfg_mode_alu_only = reg2dp_rdma_data_use == 2'h1 ; +assign cfg_mode_both = reg2dp_rdma_data_use == 2'h2 ; +assign cfg_mode_per_element = reg2dp_rdma_data_mode == 1'h1 ; +assign cfg_mode_single = cfg_mode_mul_only || cfg_mode_alu_only; +assign cfg_mode_1bytex1 = cfg_data_size_1byte & cfg_mode_single; +assign cfg_mode_2bytex1 = cfg_data_size_2byte & cfg_mode_single; +assign cfg_mode_1bytex2 = cfg_data_size_1byte & cfg_mode_both; +assign cfg_mode_2bytex2 = cfg_data_size_2byte & cfg_mode_both; +assign cfg_dp_8 = reg2dp_proc_precision== 0 ; +assign cfg_do_8 = reg2dp_out_precision== 0 ; +assign cfg_alu_en = cfg_mode_alu_only || cfg_mode_both; +assign cfg_mul_en = cfg_mode_mul_only || cfg_mode_both; +//============== +// DMA Interface +//============== +assign dma_rd_cdt_lat_fifo_pop = lat_fifo_rd_pvld & lat_fifo_rd_prdy; +//============== +// Latency FIFO to buffer return DATA +//============== +wire [3:0] lat_fifo_rd_mask = {{(4-1){1'b0}},lat_fifo_rd_pd[65 -1:64]}; +wire [2:0] lat_fifo_rd_size = lat_fifo_rd_mask[3]+lat_fifo_rd_mask[2]+lat_fifo_rd_mask[1]+lat_fifo_rd_mask[0]; +//================================================================== +// Context Queue: read +//================================================================== +assign cq2eg_prdy = is_beat_end; +assign ig2eg_size[14:0] = cq2eg_pd[14:0]; +assign ig2eg_cube_end = cq2eg_pd[15]; +assign beat_size = ig2eg_size+1; +assign beat_count_nxt = beat_count+lat_fifo_rd_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_count,beat_count} <= 16'h0; + end else begin + if (lat_fifo_rd_pvld & lat_fifo_rd_prdy) begin + if (is_last_beat) begin + {mon_beat_count,beat_count} <= 16'h0; + end else begin + {mon_beat_count,beat_count} <= beat_count_nxt; + end + end + end +end +assign is_last_beat = (beat_count_nxt == beat_size); +assign is_beat_end = is_last_beat & lat_fifo_rd_pvld & lat_fifo_rd_prdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"info in CQ there be there when return data come") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (!cq2eg_pvld) & lat_fifo_rd_pvld); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +/////////combine lat fifo pd to 4*atomic_m*bpe////// +wire lat_fifo_rd_beat_end = is_last_beat; +NV_NVDLA_SDP_RDMA_unpack u_rdma_unpack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.inp_data (lat_fifo_rd_pd[65 -1:0]) + ,.inp_pvld (lat_fifo_rd_pvld) + ,.inp_prdy (lat_fifo_rd_prdy) + ,.inp_end (lat_fifo_rd_beat_end) + ,.out_data (unpack_out_pd[4*8*8 +3:0]) + ,.out_pvld (unpack_out_pvld) + ,.out_prdy (unpack_out_prdy) + ); +wire [3:0] unpack_out_mask = unpack_out_pd[4*8*8 +3:4*8*8]; +assign unpack_out_prdy = cfg_mode_both ? alu_rod_rdy & mul_rod_rdy : cfg_mode_alu_only ? alu_rod_rdy : mul_rod_rdy; +//============================================================ +// Re-Order FIFO to send data to SDP-core +//============================================================ +// |----------------------------------------------------| +// | 16B | 16B | 16B | 16B | +// MODE |----------------------------------------------------| +// | 0 1 2 3 | +// 1Bx1 | ALU or MUL | ALU or MUL | ALU or MUL or ALU or MUL | +// |----------------------------------------------------| +// | 0 | 1 | +// 2Bx1 | ALU or MUL | ALU or MUL | +// |====================================================| +// | 0 | 1 | +// 1Bx2 | ALU | MUL | ALU | MUL | +// |----------------------------------------------------| +// | 0 | 1 | +// 2Bx2 | ALU | MUL | +// |----------------------------------------------------| +//============================================================ +//: my $k = 8; +//: foreach my $i (0..${k}-1) { +//: my $j = ${i}*2; +//: print "assign mode_1bytex2_alu_rod0_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${j}+7: 8*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: my $jj = ${i}*2+$k*2; +//: print "assign mode_1bytex2_alu_rod1_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${jj}+7: 8*${jj}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $j = ${i}*2; +//: print "assign mode_2bytex2_alu_rod0_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${j}+15: 16*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $jj = ${i}*2+$k; +//: print "assign mode_2bytex2_alu_rod1_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${jj}+15: 16*${jj}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: my $j = ${i}*2+1; +//: print "assign mode_1bytex2_mul_rod0_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${j}+7: 8*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}-1) { +//: my $jj = ${i}*2+1+$k*2; +//: print "assign mode_1bytex2_mul_rod1_pd[8*${i}+7:8*${i}] = unpack_out_pd[8*${jj}+7: 8*${jj}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $j = ${i}*2+1; +//: print "assign mode_2bytex2_mul_rod0_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${j}+15: 16*${j}]; \n"; +//: } +//: print "\n"; +//: foreach my $i (0..${k}/2-1) { +//: my $jj = ${i}*2+1+$k; +//: print "assign mode_2bytex2_mul_rod1_pd[16*${i}+15:16*${i}] = unpack_out_pd[16*${jj}+15: 16*${jj}]; \n"; +//: } +//: print "\n"; +wire [8*8 -1:0] alu_rod0_pd = cfg_mode_2bytex2 ? mode_2bytex2_alu_rod0_pd : cfg_mode_1bytex2 ? mode_1bytex2_alu_rod0_pd : unpack_out_pd[(8*8*0+8*8 -1):8*8*0]; +wire [8*8 -1:0] alu_rod1_pd = cfg_mode_2bytex2 ? mode_2bytex2_alu_rod1_pd : cfg_mode_1bytex2 ? mode_1bytex2_alu_rod1_pd : unpack_out_pd[(8*8*1+8*8 -1):8*8*1]; +wire [8*8 -1:0] alu_rod2_pd = unpack_out_pd[(8*8*2+8*8 -1):8*8*2]; +wire [8*8 -1:0] alu_rod3_pd = unpack_out_pd[(8*8*3+8*8 -1):8*8*3]; +wire [8*8 -1:0] mul_rod0_pd = cfg_mode_2bytex2 ? mode_2bytex2_mul_rod0_pd : cfg_mode_1bytex2 ? mode_1bytex2_mul_rod0_pd : unpack_out_pd[(8*8*0+8*8 -1):8*8*0]; +wire [8*8 -1:0] mul_rod1_pd = cfg_mode_2bytex2 ? mode_2bytex2_mul_rod1_pd : cfg_mode_1bytex2 ? mode_1bytex2_mul_rod1_pd : unpack_out_pd[(8*8*1+8*8 -1):8*8*1]; +wire [8*8 -1:0] mul_rod2_pd = unpack_out_pd[(8*8*2+8*8 -1):8*8*2]; +wire [8*8 -1:0] mul_rod3_pd = unpack_out_pd[(8*8*3+8*8 -1):8*8*3]; +wire [3:0] alu_rod_mask = cfg_mode_both ? {2'h0,unpack_out_mask[2],unpack_out_mask[0]} : unpack_out_mask[3:0]; +wire [3:0] mul_rod_mask = cfg_mode_both ? {2'h0,unpack_out_mask[2],unpack_out_mask[0]} : unpack_out_mask[3:0]; +wire [2:0] alu_roc_size = alu_rod_mask[3] + alu_rod_mask[2] + alu_rod_mask[1] + alu_rod_mask[0]; +wire [2:0] mul_roc_size = mul_rod_mask[3] + mul_rod_mask[2] + mul_rod_mask[1] + mul_rod_mask[0]; +assign alu_rod_vld = cfg_alu_en & unpack_out_pvld & (cfg_mode_both ? mul_rod_rdy : 1'b1); +assign mul_rod_vld = cfg_mul_en & unpack_out_pvld & (cfg_mode_both ? alu_rod_rdy : 1'b1); +assign alu_roc_vld = cfg_alu_en & unpack_out_pvld & (cfg_mode_both ? mul_roc_rdy & mul_rod_rdy & alu_rod_rdy : alu_rod_rdy); +assign mul_roc_vld = cfg_mul_en & unpack_out_pvld & (cfg_mode_both ? alu_roc_rdy & mul_rod_rdy & alu_rod_rdy : mul_rod_rdy); +wire [1:0] alu_roc_pd,mul_roc_pd; +wire mon_alu_roc_c,mon_mul_roc_c; +assign {mon_alu_roc_c,alu_roc_pd} = alu_roc_size -1; +assign {mon_mul_roc_c,mul_roc_pd} = mul_roc_size -1; +//assert: alu_rod_vld & !alu_roc_rdy +////////////////split unpack pd to 4 atomic_m alu or mul data ///////////////////// +NV_NVDLA_SDP_RDMA_EG_ro u_alu ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sdp_rdma2dp_valid (sdp_rdma2dp_alu_valid) + ,.sdp_rdma2dp_ready (sdp_rdma2dp_alu_ready) + ,.sdp_rdma2dp_pd (sdp_rdma2dp_alu_pd[8*16:0]) + ,.rod0_wr_pd (alu_rod0_pd[8*8 -1:0]) + ,.rod1_wr_pd (alu_rod1_pd[8*8 -1:0]) + ,.rod2_wr_pd (alu_rod2_pd[8*8 -1:0]) + ,.rod3_wr_pd (alu_rod3_pd[8*8 -1:0]) + ,.rod_wr_mask (alu_rod_mask[3:0]) + ,.rod_wr_vld (alu_rod_vld) + ,.rod_wr_rdy (alu_rod_rdy) + ,.roc_wr_pd (alu_roc_pd[1:0]) + ,.roc_wr_vld (alu_roc_vld) + ,.roc_wr_rdy (alu_roc_rdy) + ,.cfg_dp_8 (cfg_dp_8) + ,.cfg_dp_size_1byte (cfg_data_size_1byte) + ,.cfg_mode_per_element (cfg_mode_per_element) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.layer_end (alu_layer_end) + ); +NV_NVDLA_SDP_RDMA_EG_ro u_mul ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sdp_rdma2dp_valid (sdp_rdma2dp_mul_valid) + ,.sdp_rdma2dp_ready (sdp_rdma2dp_mul_ready) + ,.sdp_rdma2dp_pd (sdp_rdma2dp_mul_pd[8*16:0]) + ,.rod0_wr_pd (mul_rod0_pd[8*8 -1:0]) + ,.rod1_wr_pd (mul_rod1_pd[8*8 -1:0]) + ,.rod2_wr_pd (mul_rod2_pd[8*8 -1:0]) + ,.rod3_wr_pd (mul_rod3_pd[8*8 -1:0]) + ,.rod_wr_mask (mul_rod_mask[3:0]) + ,.rod_wr_vld (mul_rod_vld) + ,.rod_wr_rdy (mul_rod_rdy) + ,.roc_wr_pd (mul_roc_pd[1:0]) + ,.roc_wr_vld (mul_roc_vld) + ,.roc_wr_rdy (mul_roc_rdy) + ,.cfg_dp_8 (cfg_dp_8) + ,.cfg_dp_size_1byte (cfg_data_size_1byte) + ,.cfg_mode_per_element (cfg_mode_per_element) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.layer_end (mul_layer_end) + ); +//========================================================== +// Layer Done +//========================================================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + alu_layer_done <= 1'b0; + end else begin + if (op_load) begin + if (cfg_alu_en) begin + alu_layer_done <= 1'b0; + end else begin + alu_layer_done <= 1'b1; + end + end else if (alu_layer_end) begin + alu_layer_done <= 1'b1; + end else if (layer_done) begin + alu_layer_done <= 1'b0; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mul_layer_done <= 1'b0; + end else begin + if (op_load) begin + if (cfg_mul_en) begin + mul_layer_done <= 1'b0; + end else begin + mul_layer_done <= 1'b1; + end + end else if (mul_layer_end) begin + mul_layer_done <= 1'b1; + end else if (layer_done) begin + mul_layer_done <= 1'b0; + end + end +end +assign layer_done = alu_layer_done & mul_layer_done; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + eg_done <= 1'b0; + end else begin + eg_done <= layer_done; + end +end +endmodule // NV_NVDLA_SDP_RDMA_eg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v new file mode 100644 index 0000000..ba1c8f7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v @@ -0,0 +1,619 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_ig.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_ig ( + nvdla_core_clk + ,nvdla_core_rstn + ,op_load + ,ig2cq_pd + ,ig2cq_pvld + ,ig2cq_prdy + ,dma_rd_req_pd + ,dma_rd_req_vld + ,dma_rd_req_rdy + ,reg2dp_op_en + ,reg2dp_winograd + ,reg2dp_channel + ,reg2dp_height + ,reg2dp_width + ,reg2dp_rdma_data_mode + ,reg2dp_rdma_data_size + ,reg2dp_rdma_data_use + ,reg2dp_base_addr_high + ,reg2dp_base_addr_low + ,reg2dp_line_stride + ,reg2dp_surface_stride + ,reg2dp_proc_precision + ,reg2dp_perf_dma_en + ,dp2reg_rdma_stall + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +input dma_rd_req_rdy; +output [47 -1:0] dma_rd_req_pd; +output dma_rd_req_vld; +input ig2cq_prdy; +output [15:0] ig2cq_pd; +output ig2cq_pvld; +input reg2dp_op_en; +input reg2dp_winograd; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_proc_precision; +input reg2dp_rdma_data_mode; +input reg2dp_rdma_data_size; +input [1:0] reg2dp_rdma_data_use; +input [31:0] reg2dp_base_addr_high; +input [31-3:0] reg2dp_base_addr_low; +input [31-3:0] reg2dp_line_stride; +input [31-3:0] reg2dp_surface_stride; +input reg2dp_perf_dma_en; +output [31:0] dp2reg_rdma_stall; +reg [32 -3 -1:0] base_addr_line; +reg [32 -3 -1:0] base_addr_surf; +reg [32 -3 -1:0] base_addr_width; +reg mon_base_addr_line_c; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +wire ig2eg_cube_end; +wire [14:0] ig2eg_size; +reg cmd_process; +wire cmd_accept; +wire op_done; +reg [13-3:0] count_c; +reg [14:0] count_w; +reg [12:0] count_h; +reg [13-3:0] size_of_surf; +reg [14:0] size_of_straight; +reg [14:0] size_of_width; +wire [12:0] size_of_height; +wire [32 -3 -1:0] cfg_base_addr; +wire cfg_data_mode_per_kernel; +wire cfg_data_size_1byte; +wire cfg_data_use_both; +wire cfg_mode_1x1_pack; +wire cfg_proc_int16; +wire cfg_proc_int8; +wire [31-3:0] cfg_line_stride; +wire [31-3:0] cfg_surf_stride; +wire is_cube_end; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +reg [14:0] dma_req_size; +reg [32 -1:0] dma_req_addr; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire rdma_stall_cnt_cen; +wire rdma_stall_cnt_clr; +wire rdma_stall_cnt_inc; +wire dp2reg_rdma_stall_dec; +reg [31:0] dp2reg_rdma_stall; +assign op_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_process <= 1'b0; + end else begin + if (op_load) begin + cmd_process <= 1'b1; + end else if (op_done) begin + cmd_process <= 1'b0; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !cmd_process && op_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// Address catenate and offset calc +//============== +assign cfg_base_addr = reg2dp_base_addr_low; +assign cfg_surf_stride = {reg2dp_surface_stride}; +assign cfg_line_stride = {reg2dp_line_stride}; +assign cfg_data_size_1byte = reg2dp_rdma_data_size == 1'h0 ; +assign cfg_data_use_both = reg2dp_rdma_data_use == 2'h2 ; +assign cfg_data_mode_per_kernel = reg2dp_rdma_data_mode == 1'h0 ; +assign cfg_proc_int8 = reg2dp_proc_precision == 0 ; +assign cfg_proc_int16 = reg2dp_proc_precision == 1 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +//================================================= +// Cube Shape +//================================================= +assign is_line_end = 1'b1; +assign is_surf_end = cfg_mode_1x1_pack | cfg_data_mode_per_kernel | (is_line_end & is_last_h); +assign is_cube_end = cfg_mode_1x1_pack | cfg_data_mode_per_kernel | (is_surf_end & is_last_c); +//============== +// CHANNEL Count: +//============== +always @( + cfg_proc_int8 + or reg2dp_channel + or cfg_proc_int16 + ) begin + if (cfg_proc_int8) begin + size_of_surf = {1'b0,reg2dp_channel[12:3]}; + end else if (cfg_proc_int16) begin + size_of_surf = reg2dp_channel[12:3 -1]; + end else begin + size_of_surf = reg2dp_channel[12:3 -1]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {(14-3){1'b0}}; + end else begin + if (cmd_accept) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1; + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +//============== +// HEIGHT Count: +//============== +assign size_of_height = reg2dp_height; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==size_of_height); +//========================================== +// DMA Req : ADDR PREPARE +//========================================== +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {(32 -3){1'b0}}; + mon_base_addr_line_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_line <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + cfg_surf_stride; + end else begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + cfg_line_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP RDMA: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_surf <= {(32 -3){1'b0}}; + mon_base_addr_surf_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_surf <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + cfg_surf_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP RDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//========================================== +// DMA Req : Addr +//========================================== +always @( + base_addr_line + ) begin + dma_req_addr = {base_addr_line,{3{1'b0}}}; +end +// Size_Of_Width: As each element is 1B or 2B, the width of cube will be resized accordingly +always @( + reg2dp_width + or cfg_proc_int8 + or cfg_data_use_both + or cfg_data_size_1byte + ) begin + if (cfg_proc_int8) begin + if (cfg_data_use_both) begin + if (cfg_data_size_1byte) begin + size_of_width = (reg2dp_width << 1) + 1; + end else begin + size_of_width = (reg2dp_width << 2) + 3; + end + end else begin + if (cfg_data_size_1byte) begin + size_of_width = {2'd0,reg2dp_width}; + end else begin + size_of_width = (reg2dp_width << 1) + 1; + end + end + end else begin + if (cfg_data_use_both) begin + size_of_width = (reg2dp_width << 1) + 1; + end else begin + size_of_width = {2'd0,reg2dp_width}; + end + end +end +//========================================== +// DMA Req : SIZE +//========================================== +// in 1x1_pack mode, only send one request out +//assign mode_1x1_req_size = size_of_surf; +// PRECISION: 2byte both +// 8:1byte:single - 1B/elem - 32B/surf - 1 x surf +// 8:2byte:single - 2B/elem - 64B/surf - 2 x surf +// 8:1byte:both - 2B/elem - 64B/surf - 2 x surf +// 8:2byte:both - 4B/elem - 128B/surf - 4 x surf +// 16:2byte:single - 2B/elem - 32B/surf - 1 x surf +// 16:2byte:both - 4B/elem - 64B/surf - 2 x surf +always @( + cfg_proc_int8 + or cfg_data_use_both + or cfg_data_size_1byte + or size_of_surf + ) begin + if (cfg_proc_int8) begin + if (cfg_data_use_both) begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 1) + 1; + end else begin + size_of_straight = (size_of_surf << 2) + 3; + end + end else begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 0) + 0; + end else begin + size_of_straight = (size_of_surf << 1) + 1; + end + end + end else begin + if (cfg_data_use_both) begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 1) + 0; // illegal + end else begin + size_of_straight = (size_of_surf << 1) + 1; + end + end else begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 1) + 0; // illegal + end else begin + size_of_straight = (size_of_surf << 0) + 0; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"NO SIZE of 1Byte supported if proc precision is INT16") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & cfg_proc_int16 & cfg_data_size_1byte); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + cfg_data_mode_per_kernel + or cfg_mode_1x1_pack + or size_of_straight + or size_of_width + ) begin + if (cfg_data_mode_per_kernel || cfg_mode_1x1_pack) begin + dma_req_size = size_of_straight; + end else begin + begin + dma_req_size = size_of_width; + end + end +end +//========================================== +// Context Queue Interface +// size,cube_end +//========================================== +assign ig2eg_size = dma_req_size; +assign ig2eg_cube_end = is_cube_end; +assign ig2cq_pd[14:0] = ig2eg_size[14:0]; +assign ig2cq_pd[15] = ig2eg_cube_end ; +assign ig2cq_pvld = cmd_process & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (ig2cq_pvld & ig2cq_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = cmd_process & ig2cq_prdy; +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[47 -1:32] = dma_req_size[14:0]; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// PERF STATISTIC +assign rdma_stall_cnt_inc = dma_rd_req_vld & !dma_rd_req_rdy; +assign rdma_stall_cnt_clr = op_load; +assign rdma_stall_cnt_cen = reg2dp_op_en & reg2dp_perf_dma_en; +assign dp2reg_rdma_stall_dec = 1'b0; +// stl adv logic +always @( + rdma_stall_cnt_inc + or dp2reg_rdma_stall_dec + ) begin + stl_adv = rdma_stall_cnt_inc ^ dp2reg_rdma_stall_dec; +end +// stl cnt logic +always @( + stl_cnt_cur + or rdma_stall_cnt_inc + or dp2reg_rdma_stall_dec + or stl_adv + or rdma_stall_cnt_clr + ) begin + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; + stl_cnt_mod[33:0] = (rdma_stall_cnt_inc && !dp2reg_rdma_stall_dec)? stl_cnt_inc : (!rdma_stall_cnt_inc && dp2reg_rdma_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (rdma_stall_cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (rdma_stall_cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @( + stl_cnt_cur + ) begin + dp2reg_rdma_stall[31:0] = stl_cnt_cur[31:0]; +end +endmodule // NV_NVDLA_SDP_RDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v.vcp new file mode 100644 index 0000000..ba1c8f7 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v.vcp @@ -0,0 +1,619 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_ig.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_ig ( + nvdla_core_clk + ,nvdla_core_rstn + ,op_load + ,ig2cq_pd + ,ig2cq_pvld + ,ig2cq_prdy + ,dma_rd_req_pd + ,dma_rd_req_vld + ,dma_rd_req_rdy + ,reg2dp_op_en + ,reg2dp_winograd + ,reg2dp_channel + ,reg2dp_height + ,reg2dp_width + ,reg2dp_rdma_data_mode + ,reg2dp_rdma_data_size + ,reg2dp_rdma_data_use + ,reg2dp_base_addr_high + ,reg2dp_base_addr_low + ,reg2dp_line_stride + ,reg2dp_surface_stride + ,reg2dp_proc_precision + ,reg2dp_perf_dma_en + ,dp2reg_rdma_stall + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +input dma_rd_req_rdy; +output [47 -1:0] dma_rd_req_pd; +output dma_rd_req_vld; +input ig2cq_prdy; +output [15:0] ig2cq_pd; +output ig2cq_pvld; +input reg2dp_op_en; +input reg2dp_winograd; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input [1:0] reg2dp_proc_precision; +input reg2dp_rdma_data_mode; +input reg2dp_rdma_data_size; +input [1:0] reg2dp_rdma_data_use; +input [31:0] reg2dp_base_addr_high; +input [31-3:0] reg2dp_base_addr_low; +input [31-3:0] reg2dp_line_stride; +input [31-3:0] reg2dp_surface_stride; +input reg2dp_perf_dma_en; +output [31:0] dp2reg_rdma_stall; +reg [32 -3 -1:0] base_addr_line; +reg [32 -3 -1:0] base_addr_surf; +reg [32 -3 -1:0] base_addr_width; +reg mon_base_addr_line_c; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +wire ig2eg_cube_end; +wire [14:0] ig2eg_size; +reg cmd_process; +wire cmd_accept; +wire op_done; +reg [13-3:0] count_c; +reg [14:0] count_w; +reg [12:0] count_h; +reg [13-3:0] size_of_surf; +reg [14:0] size_of_straight; +reg [14:0] size_of_width; +wire [12:0] size_of_height; +wire [32 -3 -1:0] cfg_base_addr; +wire cfg_data_mode_per_kernel; +wire cfg_data_size_1byte; +wire cfg_data_use_both; +wire cfg_mode_1x1_pack; +wire cfg_proc_int16; +wire cfg_proc_int8; +wire [31-3:0] cfg_line_stride; +wire [31-3:0] cfg_surf_stride; +wire is_cube_end; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +reg [14:0] dma_req_size; +reg [32 -1:0] dma_req_addr; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire rdma_stall_cnt_cen; +wire rdma_stall_cnt_clr; +wire rdma_stall_cnt_inc; +wire dp2reg_rdma_stall_dec; +reg [31:0] dp2reg_rdma_stall; +assign op_done = cmd_accept & is_cube_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_process <= 1'b0; + end else begin + if (op_load) begin + cmd_process <= 1'b1; + end else if (op_done) begin + cmd_process <= 1'b0; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: get an op-done without starting the op") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !cmd_process && op_done); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// Address catenate and offset calc +//============== +assign cfg_base_addr = reg2dp_base_addr_low; +assign cfg_surf_stride = {reg2dp_surface_stride}; +assign cfg_line_stride = {reg2dp_line_stride}; +assign cfg_data_size_1byte = reg2dp_rdma_data_size == 1'h0 ; +assign cfg_data_use_both = reg2dp_rdma_data_use == 2'h2 ; +assign cfg_data_mode_per_kernel = reg2dp_rdma_data_mode == 1'h0 ; +assign cfg_proc_int8 = reg2dp_proc_precision == 0 ; +assign cfg_proc_int16 = reg2dp_proc_precision == 1 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +//================================================= +// Cube Shape +//================================================= +assign is_line_end = 1'b1; +assign is_surf_end = cfg_mode_1x1_pack | cfg_data_mode_per_kernel | (is_line_end & is_last_h); +assign is_cube_end = cfg_mode_1x1_pack | cfg_data_mode_per_kernel | (is_surf_end & is_last_c); +//============== +// CHANNEL Count: +//============== +always @( + cfg_proc_int8 + or reg2dp_channel + or cfg_proc_int16 + ) begin + if (cfg_proc_int8) begin + size_of_surf = {1'b0,reg2dp_channel[12:3]}; + end else if (cfg_proc_int16) begin + size_of_surf = reg2dp_channel[12:3 -1]; + end else begin + size_of_surf = reg2dp_channel[12:3 -1]; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {(14-3){1'b0}}; + end else begin + if (cmd_accept) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1; + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +//============== +// HEIGHT Count: +//============== +assign size_of_height = reg2dp_height; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end +end +assign is_last_h = (count_h==size_of_height); +//========================================== +// DMA Req : ADDR PREPARE +//========================================== +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_line <= {(32 -3){1'b0}}; + mon_base_addr_line_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_line <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + cfg_surf_stride; + end else begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + cfg_line_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP RDMA: no overflow is allowed") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + base_addr_surf <= {(32 -3){1'b0}}; + mon_base_addr_surf_c <= 1'b0; + end else begin + if (op_load) begin + base_addr_surf <= cfg_base_addr; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + cfg_surf_stride; + end + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP RDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//========================================== +// DMA Req : Addr +//========================================== +always @( + base_addr_line + ) begin + dma_req_addr = {base_addr_line,{3{1'b0}}}; +end +// Size_Of_Width: As each element is 1B or 2B, the width of cube will be resized accordingly +always @( + reg2dp_width + or cfg_proc_int8 + or cfg_data_use_both + or cfg_data_size_1byte + ) begin + if (cfg_proc_int8) begin + if (cfg_data_use_both) begin + if (cfg_data_size_1byte) begin + size_of_width = (reg2dp_width << 1) + 1; + end else begin + size_of_width = (reg2dp_width << 2) + 3; + end + end else begin + if (cfg_data_size_1byte) begin + size_of_width = {2'd0,reg2dp_width}; + end else begin + size_of_width = (reg2dp_width << 1) + 1; + end + end + end else begin + if (cfg_data_use_both) begin + size_of_width = (reg2dp_width << 1) + 1; + end else begin + size_of_width = {2'd0,reg2dp_width}; + end + end +end +//========================================== +// DMA Req : SIZE +//========================================== +// in 1x1_pack mode, only send one request out +//assign mode_1x1_req_size = size_of_surf; +// PRECISION: 2byte both +// 8:1byte:single - 1B/elem - 32B/surf - 1 x surf +// 8:2byte:single - 2B/elem - 64B/surf - 2 x surf +// 8:1byte:both - 2B/elem - 64B/surf - 2 x surf +// 8:2byte:both - 4B/elem - 128B/surf - 4 x surf +// 16:2byte:single - 2B/elem - 32B/surf - 1 x surf +// 16:2byte:both - 4B/elem - 64B/surf - 2 x surf +always @( + cfg_proc_int8 + or cfg_data_use_both + or cfg_data_size_1byte + or size_of_surf + ) begin + if (cfg_proc_int8) begin + if (cfg_data_use_both) begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 1) + 1; + end else begin + size_of_straight = (size_of_surf << 2) + 3; + end + end else begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 0) + 0; + end else begin + size_of_straight = (size_of_surf << 1) + 1; + end + end + end else begin + if (cfg_data_use_both) begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 1) + 0; // illegal + end else begin + size_of_straight = (size_of_surf << 1) + 1; + end + end else begin + if (cfg_data_size_1byte) begin + size_of_straight = (size_of_surf << 1) + 0; // illegal + end else begin + size_of_straight = (size_of_surf << 0) + 0; + end + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"NO SIZE of 1Byte supported if proc precision is INT16") zzz_assert_never_6x (nvdla_core_clk, `ASSERT_RESET, reg2dp_op_en & cfg_proc_int16 & cfg_data_size_1byte); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @( + cfg_data_mode_per_kernel + or cfg_mode_1x1_pack + or size_of_straight + or size_of_width + ) begin + if (cfg_data_mode_per_kernel || cfg_mode_1x1_pack) begin + dma_req_size = size_of_straight; + end else begin + begin + dma_req_size = size_of_width; + end + end +end +//========================================== +// Context Queue Interface +// size,cube_end +//========================================== +assign ig2eg_size = dma_req_size; +assign ig2eg_cube_end = is_cube_end; +assign ig2cq_pd[14:0] = ig2eg_size[14:0]; +assign ig2cq_pd[15] = ig2eg_cube_end ; +assign ig2cq_pvld = cmd_process & dma_rd_req_rdy; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP-RDMA: CQ and DMA should accept or reject together") zzz_assert_never_7x (nvdla_core_clk, `ASSERT_RESET, (ig2cq_pvld & ig2cq_prdy) ^ (dma_rd_req_vld & dma_rd_req_rdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// DMA Req : PIPE +//============== +// VALID: clamp when when cq is not ready +assign dma_rd_req_vld = cmd_process & ig2cq_prdy; +assign dma_rd_req_pd[32 -1:0] = dma_req_addr[32 -1:0]; +assign dma_rd_req_pd[47 -1:32] = dma_req_size[14:0]; +// Accept +assign cmd_accept = dma_rd_req_vld & dma_rd_req_rdy; +//============== +// PERF STATISTIC +assign rdma_stall_cnt_inc = dma_rd_req_vld & !dma_rd_req_rdy; +assign rdma_stall_cnt_clr = op_load; +assign rdma_stall_cnt_cen = reg2dp_op_en & reg2dp_perf_dma_en; +assign dp2reg_rdma_stall_dec = 1'b0; +// stl adv logic +always @( + rdma_stall_cnt_inc + or dp2reg_rdma_stall_dec + ) begin + stl_adv = rdma_stall_cnt_inc ^ dp2reg_rdma_stall_dec; +end +// stl cnt logic +always @( + stl_cnt_cur + or rdma_stall_cnt_inc + or dp2reg_rdma_stall_dec + or stl_adv + or rdma_stall_cnt_clr + ) begin + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; + stl_cnt_mod[33:0] = (rdma_stall_cnt_inc && !dp2reg_rdma_stall_dec)? stl_cnt_inc : (!rdma_stall_cnt_inc && dp2reg_rdma_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (rdma_stall_cnt_clr)? 34'd0 : stl_cnt_new[33:0]; +end +// stl flops +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (rdma_stall_cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end +end +// stl output logic +always @( + stl_cnt_cur + ) begin + dp2reg_rdma_stall[31:0] = stl_cnt_cur[31:0]; +end +endmodule // NV_NVDLA_SDP_RDMA_ig diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v new file mode 100644 index 0000000..a5e3306 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v @@ -0,0 +1,198 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_pack.v +module NV_NVDLA_SDP_RDMA_pack ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_dp_8 + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 512; //data width +parameter CW = 1; //control width +parameter OW = 256; +parameter RATIO = IW/OW; +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_dp_8; +input inp_pvld; +output inp_prdy; +input [IW+CW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW+CW-1:0] out_data; +reg [CW-1:0] ctrl_done; +wire [CW-1:0] ctrl_end; +reg [IW-1:0] pack_data; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire out_acc; +wire is_pack_last; +reg [OW-1:0] mux_data; +assign out_data = {ctrl_end,mux_data}; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | (pack_prdy & is_pack_last); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_pvld <= 1'b0; + else if (inp_prdy) + pack_pvld <= inp_pvld; +end +assign inp_acc = inp_pvld & inp_prdy; +assign out_acc = out_pvld & out_prdy; +always @(posedge nvdla_core_clk) begin + if (inp_acc) + ctrl_done[CW-1:0] <= inp_data[IW+CW-1:IW]; + else if (out_acc & is_pack_last) + ctrl_done[CW-1:0] <= {CW{1'b0}}; +end +assign ctrl_end = ctrl_done & {CW{is_pack_last}}; +//push data +always @(posedge nvdla_core_clk) begin + if (inp_acc) + pack_data <= inp_data[IW-1:0]; +end +wire [OW*16-1:0] pack_data_ext = {{(OW*16-IW){1'b0}},pack_data}; +reg [3:0] pack_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_cnt <= 4'h0; + else if (out_acc) begin + if (is_pack_last) + pack_cnt <= 4'h0; + else + pack_cnt <= pack_cnt + 1; + end +end +assign is_pack_last = !cfg_dp_8 ? (pack_cnt==RATIO/2-1) : (pack_cnt==RATIO-1); +wire [OW-1:0] pack_seg0 = pack_data_ext[((OW*0) + OW - 1):OW*0]; +wire [OW-1:0] pack_seg1 = pack_data_ext[((OW*1) + OW - 1):OW*1]; +wire [OW-1:0] pack_seg2 = pack_data_ext[((OW*2) + OW - 1):OW*2]; +wire [OW-1:0] pack_seg3 = pack_data_ext[((OW*3) + OW - 1):OW*3]; +wire [OW-1:0] pack_seg4 = pack_data_ext[((OW*4) + OW - 1):OW*4]; +wire [OW-1:0] pack_seg5 = pack_data_ext[((OW*5) + OW - 1):OW*5]; +wire [OW-1:0] pack_seg6 = pack_data_ext[((OW*6) + OW - 1):OW*6]; +wire [OW-1:0] pack_seg7 = pack_data_ext[((OW*7) + OW - 1):OW*7]; +wire [OW-1:0] pack_seg8 = pack_data_ext[((OW*8) + OW - 1):OW*8]; +wire [OW-1:0] pack_seg9 = pack_data_ext[((OW*9) + OW - 1):OW*9]; +wire [OW-1:0] pack_seg10 = pack_data_ext[((OW*10) + OW - 1):OW*10]; +wire [OW-1:0] pack_seg11 = pack_data_ext[((OW*11) + OW - 1):OW*11]; +wire [OW-1:0] pack_seg12 = pack_data_ext[((OW*12) + OW - 1):OW*12]; +wire [OW-1:0] pack_seg13 = pack_data_ext[((OW*13) + OW - 1):OW*13]; +wire [OW-1:0] pack_seg14 = pack_data_ext[((OW*14) + OW - 1):OW*14]; +wire [OW-1:0] pack_seg15 = pack_data_ext[((OW*15) + OW - 1):OW*15]; +generate +if(RATIO == 1) begin +always @( pack_seg0) begin + mux_data = pack_seg0; +end +end +else if(RATIO == 2) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if(RATIO == 4) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 8) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 16) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + or pack_seg8 + or pack_seg9 + or pack_seg10 + or pack_seg11 + or pack_seg12 + or pack_seg13 + or pack_seg14 + or pack_seg15 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + 8: mux_data = pack_seg8; + 9: mux_data = pack_seg9; + 10: mux_data = pack_seg10; + 11: mux_data = pack_seg11; + 12: mux_data = pack_seg12; + 13: mux_data = pack_seg13; + 14: mux_data = pack_seg14; + 15: mux_data = pack_seg15; + default : mux_data = {OW{1'b0}}; + endcase +end +end +endgenerate +endmodule // NV_NVDLA_SDP_RDMA_pack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v.vcp new file mode 100644 index 0000000..a5e3306 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v.vcp @@ -0,0 +1,198 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_pack.v +module NV_NVDLA_SDP_RDMA_pack ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_dp_8 + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 512; //data width +parameter CW = 1; //control width +parameter OW = 256; +parameter RATIO = IW/OW; +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_dp_8; +input inp_pvld; +output inp_prdy; +input [IW+CW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW+CW-1:0] out_data; +reg [CW-1:0] ctrl_done; +wire [CW-1:0] ctrl_end; +reg [IW-1:0] pack_data; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire out_acc; +wire is_pack_last; +reg [OW-1:0] mux_data; +assign out_data = {ctrl_end,mux_data}; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | (pack_prdy & is_pack_last); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_pvld <= 1'b0; + else if (inp_prdy) + pack_pvld <= inp_pvld; +end +assign inp_acc = inp_pvld & inp_prdy; +assign out_acc = out_pvld & out_prdy; +always @(posedge nvdla_core_clk) begin + if (inp_acc) + ctrl_done[CW-1:0] <= inp_data[IW+CW-1:IW]; + else if (out_acc & is_pack_last) + ctrl_done[CW-1:0] <= {CW{1'b0}}; +end +assign ctrl_end = ctrl_done & {CW{is_pack_last}}; +//push data +always @(posedge nvdla_core_clk) begin + if (inp_acc) + pack_data <= inp_data[IW-1:0]; +end +wire [OW*16-1:0] pack_data_ext = {{(OW*16-IW){1'b0}},pack_data}; +reg [3:0] pack_cnt; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_cnt <= 4'h0; + else if (out_acc) begin + if (is_pack_last) + pack_cnt <= 4'h0; + else + pack_cnt <= pack_cnt + 1; + end +end +assign is_pack_last = !cfg_dp_8 ? (pack_cnt==RATIO/2-1) : (pack_cnt==RATIO-1); +wire [OW-1:0] pack_seg0 = pack_data_ext[((OW*0) + OW - 1):OW*0]; +wire [OW-1:0] pack_seg1 = pack_data_ext[((OW*1) + OW - 1):OW*1]; +wire [OW-1:0] pack_seg2 = pack_data_ext[((OW*2) + OW - 1):OW*2]; +wire [OW-1:0] pack_seg3 = pack_data_ext[((OW*3) + OW - 1):OW*3]; +wire [OW-1:0] pack_seg4 = pack_data_ext[((OW*4) + OW - 1):OW*4]; +wire [OW-1:0] pack_seg5 = pack_data_ext[((OW*5) + OW - 1):OW*5]; +wire [OW-1:0] pack_seg6 = pack_data_ext[((OW*6) + OW - 1):OW*6]; +wire [OW-1:0] pack_seg7 = pack_data_ext[((OW*7) + OW - 1):OW*7]; +wire [OW-1:0] pack_seg8 = pack_data_ext[((OW*8) + OW - 1):OW*8]; +wire [OW-1:0] pack_seg9 = pack_data_ext[((OW*9) + OW - 1):OW*9]; +wire [OW-1:0] pack_seg10 = pack_data_ext[((OW*10) + OW - 1):OW*10]; +wire [OW-1:0] pack_seg11 = pack_data_ext[((OW*11) + OW - 1):OW*11]; +wire [OW-1:0] pack_seg12 = pack_data_ext[((OW*12) + OW - 1):OW*12]; +wire [OW-1:0] pack_seg13 = pack_data_ext[((OW*13) + OW - 1):OW*13]; +wire [OW-1:0] pack_seg14 = pack_data_ext[((OW*14) + OW - 1):OW*14]; +wire [OW-1:0] pack_seg15 = pack_data_ext[((OW*15) + OW - 1):OW*15]; +generate +if(RATIO == 1) begin +always @( pack_seg0) begin + mux_data = pack_seg0; +end +end +else if(RATIO == 2) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if(RATIO == 4) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 8) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + default : mux_data = {OW{1'b0}}; + endcase +end +end +else if (RATIO == 16) begin +always @( + pack_cnt + or pack_seg0 + or pack_seg1 + or pack_seg2 + or pack_seg3 + or pack_seg4 + or pack_seg5 + or pack_seg6 + or pack_seg7 + or pack_seg8 + or pack_seg9 + or pack_seg10 + or pack_seg11 + or pack_seg12 + or pack_seg13 + or pack_seg14 + or pack_seg15 + ) begin + case (pack_cnt) + 0: mux_data = pack_seg0; + 1: mux_data = pack_seg1; + 2: mux_data = pack_seg2; + 3: mux_data = pack_seg3; + 4: mux_data = pack_seg4; + 5: mux_data = pack_seg5; + 6: mux_data = pack_seg6; + 7: mux_data = pack_seg7; + 8: mux_data = pack_seg8; + 9: mux_data = pack_seg9; + 10: mux_data = pack_seg10; + 11: mux_data = pack_seg11; + 12: mux_data = pack_seg12; + 13: mux_data = pack_seg13; + 14: mux_data = pack_seg14; + 15: mux_data = pack_seg15; + default : mux_data = {OW{1'b0}}; + endcase +end +end +endgenerate +endmodule // NV_NVDLA_SDP_RDMA_pack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_reg.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_reg.v new file mode 100644 index 0000000..c3bab0b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_reg.v @@ -0,0 +1,2028 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_reg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,dp2reg_brdma_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_erdma_stall //|< i + ,dp2reg_mrdma_stall //|< i + ,dp2reg_nrdma_stall //|< i + ,dp2reg_status_inf_input_num //|< i + ,dp2reg_status_nan_input_num //|< i + ,csb2sdp_rdma_req_prdy //|> o + ,reg2dp_batch_number //|> o + ,reg2dp_bn_base_addr_high //|> o + ,reg2dp_bn_base_addr_low //|> o + ,reg2dp_bn_batch_stride //|> o + ,reg2dp_bn_line_stride //|> o + ,reg2dp_bn_surface_stride //|> o + ,reg2dp_brdma_data_mode //|> o + ,reg2dp_brdma_data_size //|> o + ,reg2dp_brdma_data_use //|> o + ,reg2dp_brdma_disable //|> o + ,reg2dp_brdma_ram_type //|> o + ,reg2dp_bs_base_addr_high //|> o + ,reg2dp_bs_base_addr_low //|> o + ,reg2dp_bs_batch_stride //|> o + ,reg2dp_bs_line_stride //|> o + ,reg2dp_bs_surface_stride //|> o + ,reg2dp_channel //|> o + ,reg2dp_erdma_data_mode //|> o + ,reg2dp_erdma_data_size //|> o + ,reg2dp_erdma_data_use //|> o + ,reg2dp_erdma_disable //|> o + ,reg2dp_erdma_ram_type //|> o + ,reg2dp_ew_base_addr_high //|> o + ,reg2dp_ew_base_addr_low //|> o + ,reg2dp_ew_batch_stride //|> o + ,reg2dp_ew_line_stride //|> o + ,reg2dp_ew_surface_stride //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_height //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_nrdma_data_mode //|> o + ,reg2dp_nrdma_data_size //|> o + ,reg2dp_nrdma_data_use //|> o + ,reg2dp_nrdma_disable //|> o + ,reg2dp_nrdma_ram_type //|> o + ,reg2dp_op_en //|> o + ,reg2dp_out_precision //|> o + ,reg2dp_perf_dma_en //|> o + ,reg2dp_perf_nan_inf_count_en //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_ram_type //|> o + ,reg2dp_src_surface_stride //|> o + ,reg2dp_width //|> o + ,reg2dp_winograd //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2sdp_rdma_req_pd; +input csb2sdp_rdma_req_pvld; +input [31:0] dp2reg_brdma_stall; +input dp2reg_done; +input [31:0] dp2reg_erdma_stall; +input [31:0] dp2reg_mrdma_stall; +input [31:0] dp2reg_nrdma_stall; +input [31:0] dp2reg_status_inf_input_num; +input [31:0] dp2reg_status_nan_input_num; +output csb2sdp_rdma_req_prdy; +output [4:0] reg2dp_batch_number; +output [31:0] reg2dp_bn_base_addr_high; +output [31:0] reg2dp_bn_base_addr_low; +output [31:0] reg2dp_bn_batch_stride; +output [31:0] reg2dp_bn_line_stride; +output [31:0] reg2dp_bn_surface_stride; +output reg2dp_brdma_data_mode; +output reg2dp_brdma_data_size; +output [1:0] reg2dp_brdma_data_use; +output reg2dp_brdma_disable; +output reg2dp_brdma_ram_type; +output [31:0] reg2dp_bs_base_addr_high; +output [31:0] reg2dp_bs_base_addr_low; +output [31:0] reg2dp_bs_batch_stride; +output [31:0] reg2dp_bs_line_stride; +output [31:0] reg2dp_bs_surface_stride; +output [12:0] reg2dp_channel; +output reg2dp_erdma_data_mode; +output reg2dp_erdma_data_size; +output [1:0] reg2dp_erdma_data_use; +output reg2dp_erdma_disable; +output reg2dp_erdma_ram_type; +output [31:0] reg2dp_ew_base_addr_high; +output [31:0] reg2dp_ew_base_addr_low; +output [31:0] reg2dp_ew_batch_stride; +output [31:0] reg2dp_ew_line_stride; +output [31:0] reg2dp_ew_surface_stride; +output reg2dp_flying_mode; +output [12:0] reg2dp_height; +output [1:0] reg2dp_in_precision; +output reg2dp_nrdma_data_mode; +output reg2dp_nrdma_data_size; +output [1:0] reg2dp_nrdma_data_use; +output reg2dp_nrdma_disable; +output reg2dp_nrdma_ram_type; +output reg2dp_op_en; +output [1:0] reg2dp_out_precision; +output reg2dp_perf_dma_en; +output reg2dp_perf_nan_inf_count_en; +output [1:0] reg2dp_proc_precision; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output reg2dp_src_ram_type; +output [31:0] reg2dp_src_surface_stride; +output [12:0] reg2dp_width; +output reg2dp_winograd; +output [33:0] sdp_rdma2csb_resp_pd; +output sdp_rdma2csb_resp_valid; +output [3:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [31:0] dp2reg_d0_brdma_stall_w; +wire [31:0] dp2reg_d0_erdma_stall_w; +wire [31:0] dp2reg_d0_mrdma_stall_w; +wire [31:0] dp2reg_d0_nrdma_stall_w; +wire [31:0] dp2reg_d0_status_inf_input_num_w; +wire [31:0] dp2reg_d0_status_nan_input_num_w; +wire [31:0] dp2reg_d1_brdma_stall_w; +wire [31:0] dp2reg_d1_erdma_stall_w; +wire [31:0] dp2reg_d1_mrdma_stall_w; +wire [31:0] dp2reg_d1_nrdma_stall_w; +wire [31:0] dp2reg_d1_status_inf_input_num_w; +wire [31:0] dp2reg_d1_status_nan_input_num_w; +wire [4:0] reg2dp_d0_batch_number; +wire [31:0] reg2dp_d0_bn_base_addr_high; +wire [31:0] reg2dp_d0_bn_base_addr_low; +wire [31:0] reg2dp_d0_bn_batch_stride; +wire [31:0] reg2dp_d0_bn_line_stride; +wire [31:0] reg2dp_d0_bn_surface_stride; +wire reg2dp_d0_brdma_data_mode; +wire reg2dp_d0_brdma_data_size; +wire [1:0] reg2dp_d0_brdma_data_use; +wire reg2dp_d0_brdma_disable; +wire reg2dp_d0_brdma_ram_type; +wire [31:0] reg2dp_d0_bs_base_addr_high; +wire [31:0] reg2dp_d0_bs_base_addr_low; +wire [31:0] reg2dp_d0_bs_batch_stride; +wire [31:0] reg2dp_d0_bs_line_stride; +wire [31:0] reg2dp_d0_bs_surface_stride; +wire [12:0] reg2dp_d0_channel; +wire reg2dp_d0_erdma_data_mode; +wire reg2dp_d0_erdma_data_size; +wire [1:0] reg2dp_d0_erdma_data_use; +wire reg2dp_d0_erdma_disable; +wire reg2dp_d0_erdma_ram_type; +wire [31:0] reg2dp_d0_ew_base_addr_high; +wire [31:0] reg2dp_d0_ew_base_addr_low; +wire [31:0] reg2dp_d0_ew_batch_stride; +wire [31:0] reg2dp_d0_ew_line_stride; +wire [31:0] reg2dp_d0_ew_surface_stride; +wire reg2dp_d0_flying_mode; +wire [12:0] reg2dp_d0_height; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_nrdma_data_mode; +wire reg2dp_d0_nrdma_data_size; +wire [1:0] reg2dp_d0_nrdma_data_use; +wire reg2dp_d0_nrdma_disable; +wire reg2dp_d0_nrdma_ram_type; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_out_precision; +wire reg2dp_d0_perf_dma_en; +wire reg2dp_d0_perf_nan_inf_count_en; +wire [1:0] reg2dp_d0_proc_precision; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire reg2dp_d0_src_ram_type; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d0_width; +wire reg2dp_d0_winograd; +wire [4:0] reg2dp_d1_batch_number; +wire [31:0] reg2dp_d1_bn_base_addr_high; +wire [31:0] reg2dp_d1_bn_base_addr_low; +wire [31:0] reg2dp_d1_bn_batch_stride; +wire [31:0] reg2dp_d1_bn_line_stride; +wire [31:0] reg2dp_d1_bn_surface_stride; +wire reg2dp_d1_brdma_data_mode; +wire reg2dp_d1_brdma_data_size; +wire [1:0] reg2dp_d1_brdma_data_use; +wire reg2dp_d1_brdma_disable; +wire reg2dp_d1_brdma_ram_type; +wire [31:0] reg2dp_d1_bs_base_addr_high; +wire [31:0] reg2dp_d1_bs_base_addr_low; +wire [31:0] reg2dp_d1_bs_batch_stride; +wire [31:0] reg2dp_d1_bs_line_stride; +wire [31:0] reg2dp_d1_bs_surface_stride; +wire [12:0] reg2dp_d1_channel; +wire reg2dp_d1_erdma_data_mode; +wire reg2dp_d1_erdma_data_size; +wire [1:0] reg2dp_d1_erdma_data_use; +wire reg2dp_d1_erdma_disable; +wire reg2dp_d1_erdma_ram_type; +wire [31:0] reg2dp_d1_ew_base_addr_high; +wire [31:0] reg2dp_d1_ew_base_addr_low; +wire [31:0] reg2dp_d1_ew_batch_stride; +wire [31:0] reg2dp_d1_ew_line_stride; +wire [31:0] reg2dp_d1_ew_surface_stride; +wire reg2dp_d1_flying_mode; +wire [12:0] reg2dp_d1_height; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_nrdma_data_mode; +wire reg2dp_d1_nrdma_data_size; +wire [1:0] reg2dp_d1_nrdma_data_use; +wire reg2dp_d1_nrdma_disable; +wire reg2dp_d1_nrdma_ram_type; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_out_precision; +wire reg2dp_d1_perf_dma_en; +wire reg2dp_d1_perf_nan_inf_count_en; +wire [1:0] reg2dp_d1_proc_precision; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire reg2dp_d1_src_ram_type; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [12:0] reg2dp_d1_width; +wire reg2dp_d1_winograd; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en_d0; +reg dp2reg_consumer; +reg [31:0] dp2reg_d0_brdma_stall; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_erdma_stall; +reg [31:0] dp2reg_d0_mrdma_stall; +reg [31:0] dp2reg_d0_nrdma_stall; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg [31:0] dp2reg_d0_status_inf_input_num; +reg [31:0] dp2reg_d0_status_nan_input_num; +reg [31:0] dp2reg_d1_brdma_stall; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_erdma_stall; +reg [31:0] dp2reg_d1_mrdma_stall; +reg [31:0] dp2reg_d1_nrdma_stall; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [31:0] dp2reg_d1_status_inf_input_num; +reg [31:0] dp2reg_d1_status_nan_input_num; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [4:0] reg2dp_batch_number; +reg [31:0] reg2dp_bn_base_addr_high; +reg [31:0] reg2dp_bn_base_addr_low; +reg [31:0] reg2dp_bn_batch_stride; +reg [31:0] reg2dp_bn_line_stride; +reg [31:0] reg2dp_bn_surface_stride; +reg reg2dp_brdma_data_mode; +reg reg2dp_brdma_data_size; +reg [1:0] reg2dp_brdma_data_use; +reg reg2dp_brdma_disable; +reg reg2dp_brdma_ram_type; +reg [31:0] reg2dp_bs_base_addr_high; +reg [31:0] reg2dp_bs_base_addr_low; +reg [31:0] reg2dp_bs_batch_stride; +reg [31:0] reg2dp_bs_line_stride; +reg [31:0] reg2dp_bs_surface_stride; +reg [12:0] reg2dp_channel; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_erdma_data_mode; +reg reg2dp_erdma_data_size; +reg [1:0] reg2dp_erdma_data_use; +reg reg2dp_erdma_disable; +reg reg2dp_erdma_ram_type; +reg [31:0] reg2dp_ew_base_addr_high; +reg [31:0] reg2dp_ew_base_addr_low; +reg [31:0] reg2dp_ew_batch_stride; +reg [31:0] reg2dp_ew_line_stride; +reg [31:0] reg2dp_ew_surface_stride; +reg reg2dp_flying_mode; +reg [12:0] reg2dp_height; +reg [1:0] reg2dp_in_precision; +reg reg2dp_nrdma_data_mode; +reg reg2dp_nrdma_data_size; +reg [1:0] reg2dp_nrdma_data_use; +reg reg2dp_nrdma_disable; +reg reg2dp_nrdma_ram_type; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_out_precision; +reg reg2dp_perf_dma_en; +reg reg2dp_perf_nan_inf_count_en; +reg [1:0] reg2dp_proc_precision; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg reg2dp_src_ram_type; +reg [31:0] reg2dp_src_surface_stride; +reg [12:0] reg2dp_width; +reg reg2dp_winograd; +reg [62:0] req_pd; +reg req_pvld; +reg [33:0] sdp_rdma2csb_resp_pd; +reg sdp_rdma2csb_resp_valid; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_SDP_RDMA_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_SDP_RDMA_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bn_base_addr_high (reg2dp_d0_bn_base_addr_high[31:0]) //|> w + ,.bn_base_addr_low (reg2dp_d0_bn_base_addr_low[31:0]) //|> w + ,.bn_batch_stride (reg2dp_d0_bn_batch_stride[31:0]) //|> w + ,.bn_line_stride (reg2dp_d0_bn_line_stride[31:0]) //|> w + ,.bn_surface_stride (reg2dp_d0_bn_surface_stride[31:0]) //|> w + ,.brdma_data_mode (reg2dp_d0_brdma_data_mode) //|> w + ,.brdma_data_size (reg2dp_d0_brdma_data_size) //|> w + ,.brdma_data_use (reg2dp_d0_brdma_data_use[1:0]) //|> w + ,.brdma_disable (reg2dp_d0_brdma_disable) //|> w + ,.brdma_ram_type (reg2dp_d0_brdma_ram_type) //|> w + ,.bs_base_addr_high (reg2dp_d0_bs_base_addr_high[31:0]) //|> w + ,.bs_base_addr_low (reg2dp_d0_bs_base_addr_low[31:0]) //|> w + ,.bs_batch_stride (reg2dp_d0_bs_batch_stride[31:0]) //|> w + ,.bs_line_stride (reg2dp_d0_bs_line_stride[31:0]) //|> w + ,.bs_surface_stride (reg2dp_d0_bs_surface_stride[31:0]) //|> w + ,.channel (reg2dp_d0_channel[12:0]) //|> w + ,.height (reg2dp_d0_height[12:0]) //|> w + ,.width (reg2dp_d0_width[12:0]) //|> w + ,.erdma_data_mode (reg2dp_d0_erdma_data_mode) //|> w + ,.erdma_data_size (reg2dp_d0_erdma_data_size) //|> w + ,.erdma_data_use (reg2dp_d0_erdma_data_use[1:0]) //|> w + ,.erdma_disable (reg2dp_d0_erdma_disable) //|> w + ,.erdma_ram_type (reg2dp_d0_erdma_ram_type) //|> w + ,.ew_base_addr_high (reg2dp_d0_ew_base_addr_high[31:0]) //|> w + ,.ew_base_addr_low (reg2dp_d0_ew_base_addr_low[31:0]) //|> w + ,.ew_batch_stride (reg2dp_d0_ew_batch_stride[31:0]) //|> w + ,.ew_line_stride (reg2dp_d0_ew_line_stride[31:0]) //|> w + ,.ew_surface_stride (reg2dp_d0_ew_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d0_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.out_precision (reg2dp_d0_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.winograd (reg2dp_d0_winograd) //|> w + ,.nrdma_data_mode (reg2dp_d0_nrdma_data_mode) //|> w + ,.nrdma_data_size (reg2dp_d0_nrdma_data_size) //|> w + ,.nrdma_data_use (reg2dp_d0_nrdma_data_use[1:0]) //|> w + ,.nrdma_disable (reg2dp_d0_nrdma_disable) //|> w + ,.nrdma_ram_type (reg2dp_d0_nrdma_ram_type) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d0_perf_dma_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d0_perf_nan_inf_count_en) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d0_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.brdma_stall (dp2reg_d0_brdma_stall[31:0]) //|< r + ,.erdma_stall (dp2reg_d0_erdma_stall[31:0]) //|< r + ,.mrdma_stall (dp2reg_d0_mrdma_stall[31:0]) //|< r + ,.nrdma_stall (dp2reg_d0_nrdma_stall[31:0]) //|< r + ,.status_inf_input_num (dp2reg_d0_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d0_status_nan_input_num[31:0]) //|< r + ); +NV_NVDLA_SDP_RDMA_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bn_base_addr_high (reg2dp_d1_bn_base_addr_high[31:0]) //|> w + ,.bn_base_addr_low (reg2dp_d1_bn_base_addr_low[31:0]) //|> w + ,.bn_batch_stride (reg2dp_d1_bn_batch_stride[31:0]) //|> w + ,.bn_line_stride (reg2dp_d1_bn_line_stride[31:0]) //|> w + ,.bn_surface_stride (reg2dp_d1_bn_surface_stride[31:0]) //|> w + ,.brdma_data_mode (reg2dp_d1_brdma_data_mode) //|> w + ,.brdma_data_size (reg2dp_d1_brdma_data_size) //|> w + ,.brdma_data_use (reg2dp_d1_brdma_data_use[1:0]) //|> w + ,.brdma_disable (reg2dp_d1_brdma_disable) //|> w + ,.brdma_ram_type (reg2dp_d1_brdma_ram_type) //|> w + ,.bs_base_addr_high (reg2dp_d1_bs_base_addr_high[31:0]) //|> w + ,.bs_base_addr_low (reg2dp_d1_bs_base_addr_low[31:0]) //|> w + ,.bs_batch_stride (reg2dp_d1_bs_batch_stride[31:0]) //|> w + ,.bs_line_stride (reg2dp_d1_bs_line_stride[31:0]) //|> w + ,.bs_surface_stride (reg2dp_d1_bs_surface_stride[31:0]) //|> w + ,.channel (reg2dp_d1_channel[12:0]) //|> w + ,.height (reg2dp_d1_height[12:0]) //|> w + ,.width (reg2dp_d1_width[12:0]) //|> w + ,.erdma_data_mode (reg2dp_d1_erdma_data_mode) //|> w + ,.erdma_data_size (reg2dp_d1_erdma_data_size) //|> w + ,.erdma_data_use (reg2dp_d1_erdma_data_use[1:0]) //|> w + ,.erdma_disable (reg2dp_d1_erdma_disable) //|> w + ,.erdma_ram_type (reg2dp_d1_erdma_ram_type) //|> w + ,.ew_base_addr_high (reg2dp_d1_ew_base_addr_high[31:0]) //|> w + ,.ew_base_addr_low (reg2dp_d1_ew_base_addr_low[31:0]) //|> w + ,.ew_batch_stride (reg2dp_d1_ew_batch_stride[31:0]) //|> w + ,.ew_line_stride (reg2dp_d1_ew_line_stride[31:0]) //|> w + ,.ew_surface_stride (reg2dp_d1_ew_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d1_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.out_precision (reg2dp_d1_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.winograd (reg2dp_d1_winograd) //|> w + ,.nrdma_data_mode (reg2dp_d1_nrdma_data_mode) //|> w + ,.nrdma_data_size (reg2dp_d1_nrdma_data_size) //|> w + ,.nrdma_data_use (reg2dp_d1_nrdma_data_use[1:0]) //|> w + ,.nrdma_disable (reg2dp_d1_nrdma_disable) //|> w + ,.nrdma_ram_type (reg2dp_d1_nrdma_ram_type) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d1_perf_dma_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d1_perf_nan_inf_count_en) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d1_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.brdma_stall (dp2reg_d1_brdma_stall[31:0]) //|< r + ,.erdma_stall (dp2reg_d1_erdma_stall[31:0]) //|< r + ,.mrdma_stall (dp2reg_d1_mrdma_stall[31:0]) //|< r + ,.nrdma_stall (dp2reg_d1_nrdma_stall[31:0]) //|< r + ,.status_inf_input_num (dp2reg_d1_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d1_status_nan_input_num[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'ha008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'ha008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'ha008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2sdp_rdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2sdp_rdma_req_pvld) == 1'b1) begin + req_pd <= csb2sdp_rdma_req_pd; +// VCS coverage off + end else if ((csb2sdp_rdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2sdp_rdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2sdp_rdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + sdp_rdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + sdp_rdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma2csb_resp_valid <= 1'b0; + end else begin + sdp_rdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_bn_base_addr_high + or reg2dp_d0_bn_base_addr_high + ) begin + reg2dp_bn_base_addr_high = dp2reg_consumer ? reg2dp_d1_bn_base_addr_high : reg2dp_d0_bn_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_base_addr_low + or reg2dp_d0_bn_base_addr_low + ) begin + reg2dp_bn_base_addr_low = dp2reg_consumer ? reg2dp_d1_bn_base_addr_low : reg2dp_d0_bn_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_batch_stride + or reg2dp_d0_bn_batch_stride + ) begin + reg2dp_bn_batch_stride = dp2reg_consumer ? reg2dp_d1_bn_batch_stride : reg2dp_d0_bn_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_line_stride + or reg2dp_d0_bn_line_stride + ) begin + reg2dp_bn_line_stride = dp2reg_consumer ? reg2dp_d1_bn_line_stride : reg2dp_d0_bn_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_surface_stride + or reg2dp_d0_bn_surface_stride + ) begin + reg2dp_bn_surface_stride = dp2reg_consumer ? reg2dp_d1_bn_surface_stride : reg2dp_d0_bn_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_data_mode + or reg2dp_d0_brdma_data_mode + ) begin + reg2dp_brdma_data_mode = dp2reg_consumer ? reg2dp_d1_brdma_data_mode : reg2dp_d0_brdma_data_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_data_size + or reg2dp_d0_brdma_data_size + ) begin + reg2dp_brdma_data_size = dp2reg_consumer ? reg2dp_d1_brdma_data_size : reg2dp_d0_brdma_data_size; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_data_use + or reg2dp_d0_brdma_data_use + ) begin + reg2dp_brdma_data_use = dp2reg_consumer ? reg2dp_d1_brdma_data_use : reg2dp_d0_brdma_data_use; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_disable + or reg2dp_d0_brdma_disable + ) begin + reg2dp_brdma_disable = dp2reg_consumer ? reg2dp_d1_brdma_disable : reg2dp_d0_brdma_disable; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_ram_type + or reg2dp_d0_brdma_ram_type + ) begin + reg2dp_brdma_ram_type = dp2reg_consumer ? reg2dp_d1_brdma_ram_type : reg2dp_d0_brdma_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_base_addr_high + or reg2dp_d0_bs_base_addr_high + ) begin + reg2dp_bs_base_addr_high = dp2reg_consumer ? reg2dp_d1_bs_base_addr_high : reg2dp_d0_bs_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_base_addr_low + or reg2dp_d0_bs_base_addr_low + ) begin + reg2dp_bs_base_addr_low = dp2reg_consumer ? reg2dp_d1_bs_base_addr_low : reg2dp_d0_bs_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_batch_stride + or reg2dp_d0_bs_batch_stride + ) begin + reg2dp_bs_batch_stride = dp2reg_consumer ? reg2dp_d1_bs_batch_stride : reg2dp_d0_bs_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_line_stride + or reg2dp_d0_bs_line_stride + ) begin + reg2dp_bs_line_stride = dp2reg_consumer ? reg2dp_d1_bs_line_stride : reg2dp_d0_bs_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_surface_stride + or reg2dp_d0_bs_surface_stride + ) begin + reg2dp_bs_surface_stride = dp2reg_consumer ? reg2dp_d1_bs_surface_stride : reg2dp_d0_bs_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_channel + or reg2dp_d0_channel + ) begin + reg2dp_channel = dp2reg_consumer ? reg2dp_d1_channel : reg2dp_d0_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_height + or reg2dp_d0_height + ) begin + reg2dp_height = dp2reg_consumer ? reg2dp_d1_height : reg2dp_d0_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_width + or reg2dp_d0_width + ) begin + reg2dp_width = dp2reg_consumer ? reg2dp_d1_width : reg2dp_d0_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_data_mode + or reg2dp_d0_erdma_data_mode + ) begin + reg2dp_erdma_data_mode = dp2reg_consumer ? reg2dp_d1_erdma_data_mode : reg2dp_d0_erdma_data_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_data_size + or reg2dp_d0_erdma_data_size + ) begin + reg2dp_erdma_data_size = dp2reg_consumer ? reg2dp_d1_erdma_data_size : reg2dp_d0_erdma_data_size; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_data_use + or reg2dp_d0_erdma_data_use + ) begin + reg2dp_erdma_data_use = dp2reg_consumer ? reg2dp_d1_erdma_data_use : reg2dp_d0_erdma_data_use; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_disable + or reg2dp_d0_erdma_disable + ) begin + reg2dp_erdma_disable = dp2reg_consumer ? reg2dp_d1_erdma_disable : reg2dp_d0_erdma_disable; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_ram_type + or reg2dp_d0_erdma_ram_type + ) begin + reg2dp_erdma_ram_type = dp2reg_consumer ? reg2dp_d1_erdma_ram_type : reg2dp_d0_erdma_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_base_addr_high + or reg2dp_d0_ew_base_addr_high + ) begin + reg2dp_ew_base_addr_high = dp2reg_consumer ? reg2dp_d1_ew_base_addr_high : reg2dp_d0_ew_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_base_addr_low + or reg2dp_d0_ew_base_addr_low + ) begin + reg2dp_ew_base_addr_low = dp2reg_consumer ? reg2dp_d1_ew_base_addr_low : reg2dp_d0_ew_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_batch_stride + or reg2dp_d0_ew_batch_stride + ) begin + reg2dp_ew_batch_stride = dp2reg_consumer ? reg2dp_d1_ew_batch_stride : reg2dp_d0_ew_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_line_stride + or reg2dp_d0_ew_line_stride + ) begin + reg2dp_ew_line_stride = dp2reg_consumer ? reg2dp_d1_ew_line_stride : reg2dp_d0_ew_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_surface_stride + or reg2dp_d0_ew_surface_stride + ) begin + reg2dp_ew_surface_stride = dp2reg_consumer ? reg2dp_d1_ew_surface_stride : reg2dp_d0_ew_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_batch_number + or reg2dp_d0_batch_number + ) begin + reg2dp_batch_number = dp2reg_consumer ? reg2dp_d1_batch_number : reg2dp_d0_batch_number; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_out_precision + or reg2dp_d0_out_precision + ) begin + reg2dp_out_precision = dp2reg_consumer ? reg2dp_d1_out_precision : reg2dp_d0_out_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_winograd + or reg2dp_d0_winograd + ) begin + reg2dp_winograd = dp2reg_consumer ? reg2dp_d1_winograd : reg2dp_d0_winograd; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_data_mode + or reg2dp_d0_nrdma_data_mode + ) begin + reg2dp_nrdma_data_mode = dp2reg_consumer ? reg2dp_d1_nrdma_data_mode : reg2dp_d0_nrdma_data_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_data_size + or reg2dp_d0_nrdma_data_size + ) begin + reg2dp_nrdma_data_size = dp2reg_consumer ? reg2dp_d1_nrdma_data_size : reg2dp_d0_nrdma_data_size; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_data_use + or reg2dp_d0_nrdma_data_use + ) begin + reg2dp_nrdma_data_use = dp2reg_consumer ? reg2dp_d1_nrdma_data_use : reg2dp_d0_nrdma_data_use; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_disable + or reg2dp_d0_nrdma_disable + ) begin + reg2dp_nrdma_disable = dp2reg_consumer ? reg2dp_d1_nrdma_disable : reg2dp_d0_nrdma_disable; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_ram_type + or reg2dp_d0_nrdma_ram_type + ) begin + reg2dp_nrdma_ram_type = dp2reg_consumer ? reg2dp_d1_nrdma_ram_type : reg2dp_d0_nrdma_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_dma_en + or reg2dp_d0_perf_dma_en + ) begin + reg2dp_perf_dma_en = dp2reg_consumer ? reg2dp_d1_perf_dma_en : reg2dp_d0_perf_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_nan_inf_count_en + or reg2dp_d0_perf_nan_inf_count_en + ) begin + reg2dp_perf_nan_inf_count_en = dp2reg_consumer ? reg2dp_d1_perf_nan_inf_count_en : reg2dp_d0_perf_nan_inf_count_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_ram_type + or reg2dp_d0_src_ram_type + ) begin + reg2dp_src_ram_type = dp2reg_consumer ? reg2dp_d1_src_ram_type : reg2dp_d0_src_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +// USER logic can be put here: +//////// Dual Flop Write Control//////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for overflow counting register //////// +assign dp2reg_d0_status_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_nan_input_num <= dp2reg_d0_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_brdma_stall_w = (dp2reg_d0_set) ? dp2reg_brdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_brdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_brdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_brdma_stall <= dp2reg_d0_brdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_brdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_inf_input_num <= dp2reg_d0_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_erdma_stall_w = (dp2reg_d0_set) ? dp2reg_erdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_erdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_erdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_erdma_stall <= dp2reg_d0_erdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_erdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_nrdma_stall_w = (dp2reg_d0_set) ? dp2reg_nrdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_nrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nrdma_stall <= dp2reg_d0_nrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_mrdma_stall_w = (dp2reg_d0_set) ? dp2reg_mrdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_mrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_mrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_mrdma_stall <= dp2reg_d0_mrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_mrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_nan_input_num <= dp2reg_d1_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_brdma_stall_w = (dp2reg_d1_set) ? dp2reg_brdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_brdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_brdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_brdma_stall <= dp2reg_d1_brdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_brdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_inf_input_num <= dp2reg_d1_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_erdma_stall_w = (dp2reg_d1_set) ? dp2reg_erdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_erdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_erdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_erdma_stall <= dp2reg_d1_erdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_erdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_nrdma_stall_w = (dp2reg_d1_set) ? dp2reg_nrdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_nrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nrdma_stall <= dp2reg_d1_nrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_mrdma_stall_w = (dp2reg_d1_set) ? dp2reg_mrdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_mrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_mrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_mrdma_stall <= dp2reg_d1_mrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_mrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_SDP_RDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_reg.v.vcp new file mode 100644 index 0000000..c3bab0b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_reg.v.vcp @@ -0,0 +1,2028 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_reg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,dp2reg_brdma_stall //|< i + ,dp2reg_done //|< i + ,dp2reg_erdma_stall //|< i + ,dp2reg_mrdma_stall //|< i + ,dp2reg_nrdma_stall //|< i + ,dp2reg_status_inf_input_num //|< i + ,dp2reg_status_nan_input_num //|< i + ,csb2sdp_rdma_req_prdy //|> o + ,reg2dp_batch_number //|> o + ,reg2dp_bn_base_addr_high //|> o + ,reg2dp_bn_base_addr_low //|> o + ,reg2dp_bn_batch_stride //|> o + ,reg2dp_bn_line_stride //|> o + ,reg2dp_bn_surface_stride //|> o + ,reg2dp_brdma_data_mode //|> o + ,reg2dp_brdma_data_size //|> o + ,reg2dp_brdma_data_use //|> o + ,reg2dp_brdma_disable //|> o + ,reg2dp_brdma_ram_type //|> o + ,reg2dp_bs_base_addr_high //|> o + ,reg2dp_bs_base_addr_low //|> o + ,reg2dp_bs_batch_stride //|> o + ,reg2dp_bs_line_stride //|> o + ,reg2dp_bs_surface_stride //|> o + ,reg2dp_channel //|> o + ,reg2dp_erdma_data_mode //|> o + ,reg2dp_erdma_data_size //|> o + ,reg2dp_erdma_data_use //|> o + ,reg2dp_erdma_disable //|> o + ,reg2dp_erdma_ram_type //|> o + ,reg2dp_ew_base_addr_high //|> o + ,reg2dp_ew_base_addr_low //|> o + ,reg2dp_ew_batch_stride //|> o + ,reg2dp_ew_line_stride //|> o + ,reg2dp_ew_surface_stride //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_height //|> o + ,reg2dp_in_precision //|> o + ,reg2dp_nrdma_data_mode //|> o + ,reg2dp_nrdma_data_size //|> o + ,reg2dp_nrdma_data_use //|> o + ,reg2dp_nrdma_disable //|> o + ,reg2dp_nrdma_ram_type //|> o + ,reg2dp_op_en //|> o + ,reg2dp_out_precision //|> o + ,reg2dp_perf_dma_en //|> o + ,reg2dp_perf_nan_inf_count_en //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_src_base_addr_high //|> o + ,reg2dp_src_base_addr_low //|> o + ,reg2dp_src_line_stride //|> o + ,reg2dp_src_ram_type //|> o + ,reg2dp_src_surface_stride //|> o + ,reg2dp_width //|> o + ,reg2dp_winograd //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ,slcg_op_en //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2sdp_rdma_req_pd; +input csb2sdp_rdma_req_pvld; +input [31:0] dp2reg_brdma_stall; +input dp2reg_done; +input [31:0] dp2reg_erdma_stall; +input [31:0] dp2reg_mrdma_stall; +input [31:0] dp2reg_nrdma_stall; +input [31:0] dp2reg_status_inf_input_num; +input [31:0] dp2reg_status_nan_input_num; +output csb2sdp_rdma_req_prdy; +output [4:0] reg2dp_batch_number; +output [31:0] reg2dp_bn_base_addr_high; +output [31:0] reg2dp_bn_base_addr_low; +output [31:0] reg2dp_bn_batch_stride; +output [31:0] reg2dp_bn_line_stride; +output [31:0] reg2dp_bn_surface_stride; +output reg2dp_brdma_data_mode; +output reg2dp_brdma_data_size; +output [1:0] reg2dp_brdma_data_use; +output reg2dp_brdma_disable; +output reg2dp_brdma_ram_type; +output [31:0] reg2dp_bs_base_addr_high; +output [31:0] reg2dp_bs_base_addr_low; +output [31:0] reg2dp_bs_batch_stride; +output [31:0] reg2dp_bs_line_stride; +output [31:0] reg2dp_bs_surface_stride; +output [12:0] reg2dp_channel; +output reg2dp_erdma_data_mode; +output reg2dp_erdma_data_size; +output [1:0] reg2dp_erdma_data_use; +output reg2dp_erdma_disable; +output reg2dp_erdma_ram_type; +output [31:0] reg2dp_ew_base_addr_high; +output [31:0] reg2dp_ew_base_addr_low; +output [31:0] reg2dp_ew_batch_stride; +output [31:0] reg2dp_ew_line_stride; +output [31:0] reg2dp_ew_surface_stride; +output reg2dp_flying_mode; +output [12:0] reg2dp_height; +output [1:0] reg2dp_in_precision; +output reg2dp_nrdma_data_mode; +output reg2dp_nrdma_data_size; +output [1:0] reg2dp_nrdma_data_use; +output reg2dp_nrdma_disable; +output reg2dp_nrdma_ram_type; +output reg2dp_op_en; +output [1:0] reg2dp_out_precision; +output reg2dp_perf_dma_en; +output reg2dp_perf_nan_inf_count_en; +output [1:0] reg2dp_proc_precision; +output [31:0] reg2dp_src_base_addr_high; +output [31:0] reg2dp_src_base_addr_low; +output [31:0] reg2dp_src_line_stride; +output reg2dp_src_ram_type; +output [31:0] reg2dp_src_surface_stride; +output [12:0] reg2dp_width; +output reg2dp_winograd; +output [33:0] sdp_rdma2csb_resp_pd; +output sdp_rdma2csb_resp_valid; +output [3:0] slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [31:0] dp2reg_d0_brdma_stall_w; +wire [31:0] dp2reg_d0_erdma_stall_w; +wire [31:0] dp2reg_d0_mrdma_stall_w; +wire [31:0] dp2reg_d0_nrdma_stall_w; +wire [31:0] dp2reg_d0_status_inf_input_num_w; +wire [31:0] dp2reg_d0_status_nan_input_num_w; +wire [31:0] dp2reg_d1_brdma_stall_w; +wire [31:0] dp2reg_d1_erdma_stall_w; +wire [31:0] dp2reg_d1_mrdma_stall_w; +wire [31:0] dp2reg_d1_nrdma_stall_w; +wire [31:0] dp2reg_d1_status_inf_input_num_w; +wire [31:0] dp2reg_d1_status_nan_input_num_w; +wire [4:0] reg2dp_d0_batch_number; +wire [31:0] reg2dp_d0_bn_base_addr_high; +wire [31:0] reg2dp_d0_bn_base_addr_low; +wire [31:0] reg2dp_d0_bn_batch_stride; +wire [31:0] reg2dp_d0_bn_line_stride; +wire [31:0] reg2dp_d0_bn_surface_stride; +wire reg2dp_d0_brdma_data_mode; +wire reg2dp_d0_brdma_data_size; +wire [1:0] reg2dp_d0_brdma_data_use; +wire reg2dp_d0_brdma_disable; +wire reg2dp_d0_brdma_ram_type; +wire [31:0] reg2dp_d0_bs_base_addr_high; +wire [31:0] reg2dp_d0_bs_base_addr_low; +wire [31:0] reg2dp_d0_bs_batch_stride; +wire [31:0] reg2dp_d0_bs_line_stride; +wire [31:0] reg2dp_d0_bs_surface_stride; +wire [12:0] reg2dp_d0_channel; +wire reg2dp_d0_erdma_data_mode; +wire reg2dp_d0_erdma_data_size; +wire [1:0] reg2dp_d0_erdma_data_use; +wire reg2dp_d0_erdma_disable; +wire reg2dp_d0_erdma_ram_type; +wire [31:0] reg2dp_d0_ew_base_addr_high; +wire [31:0] reg2dp_d0_ew_base_addr_low; +wire [31:0] reg2dp_d0_ew_batch_stride; +wire [31:0] reg2dp_d0_ew_line_stride; +wire [31:0] reg2dp_d0_ew_surface_stride; +wire reg2dp_d0_flying_mode; +wire [12:0] reg2dp_d0_height; +wire [1:0] reg2dp_d0_in_precision; +wire reg2dp_d0_nrdma_data_mode; +wire reg2dp_d0_nrdma_data_size; +wire [1:0] reg2dp_d0_nrdma_data_use; +wire reg2dp_d0_nrdma_disable; +wire reg2dp_d0_nrdma_ram_type; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_out_precision; +wire reg2dp_d0_perf_dma_en; +wire reg2dp_d0_perf_nan_inf_count_en; +wire [1:0] reg2dp_d0_proc_precision; +wire [31:0] reg2dp_d0_src_base_addr_high; +wire [31:0] reg2dp_d0_src_base_addr_low; +wire [31:0] reg2dp_d0_src_line_stride; +wire reg2dp_d0_src_ram_type; +wire [31:0] reg2dp_d0_src_surface_stride; +wire [12:0] reg2dp_d0_width; +wire reg2dp_d0_winograd; +wire [4:0] reg2dp_d1_batch_number; +wire [31:0] reg2dp_d1_bn_base_addr_high; +wire [31:0] reg2dp_d1_bn_base_addr_low; +wire [31:0] reg2dp_d1_bn_batch_stride; +wire [31:0] reg2dp_d1_bn_line_stride; +wire [31:0] reg2dp_d1_bn_surface_stride; +wire reg2dp_d1_brdma_data_mode; +wire reg2dp_d1_brdma_data_size; +wire [1:0] reg2dp_d1_brdma_data_use; +wire reg2dp_d1_brdma_disable; +wire reg2dp_d1_brdma_ram_type; +wire [31:0] reg2dp_d1_bs_base_addr_high; +wire [31:0] reg2dp_d1_bs_base_addr_low; +wire [31:0] reg2dp_d1_bs_batch_stride; +wire [31:0] reg2dp_d1_bs_line_stride; +wire [31:0] reg2dp_d1_bs_surface_stride; +wire [12:0] reg2dp_d1_channel; +wire reg2dp_d1_erdma_data_mode; +wire reg2dp_d1_erdma_data_size; +wire [1:0] reg2dp_d1_erdma_data_use; +wire reg2dp_d1_erdma_disable; +wire reg2dp_d1_erdma_ram_type; +wire [31:0] reg2dp_d1_ew_base_addr_high; +wire [31:0] reg2dp_d1_ew_base_addr_low; +wire [31:0] reg2dp_d1_ew_batch_stride; +wire [31:0] reg2dp_d1_ew_line_stride; +wire [31:0] reg2dp_d1_ew_surface_stride; +wire reg2dp_d1_flying_mode; +wire [12:0] reg2dp_d1_height; +wire [1:0] reg2dp_d1_in_precision; +wire reg2dp_d1_nrdma_data_mode; +wire reg2dp_d1_nrdma_data_size; +wire [1:0] reg2dp_d1_nrdma_data_use; +wire reg2dp_d1_nrdma_disable; +wire reg2dp_d1_nrdma_ram_type; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_out_precision; +wire reg2dp_d1_perf_dma_en; +wire reg2dp_d1_perf_nan_inf_count_en; +wire [1:0] reg2dp_d1_proc_precision; +wire [31:0] reg2dp_d1_src_base_addr_high; +wire [31:0] reg2dp_d1_src_base_addr_low; +wire [31:0] reg2dp_d1_src_line_stride; +wire reg2dp_d1_src_ram_type; +wire [31:0] reg2dp_d1_src_surface_stride; +wire [12:0] reg2dp_d1_width; +wire reg2dp_d1_winograd; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en_d0; +reg dp2reg_consumer; +reg [31:0] dp2reg_d0_brdma_stall; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_erdma_stall; +reg [31:0] dp2reg_d0_mrdma_stall; +reg [31:0] dp2reg_d0_nrdma_stall; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg [31:0] dp2reg_d0_status_inf_input_num; +reg [31:0] dp2reg_d0_status_nan_input_num; +reg [31:0] dp2reg_d1_brdma_stall; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_erdma_stall; +reg [31:0] dp2reg_d1_mrdma_stall; +reg [31:0] dp2reg_d1_nrdma_stall; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [31:0] dp2reg_d1_status_inf_input_num; +reg [31:0] dp2reg_d1_status_nan_input_num; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg [4:0] reg2dp_batch_number; +reg [31:0] reg2dp_bn_base_addr_high; +reg [31:0] reg2dp_bn_base_addr_low; +reg [31:0] reg2dp_bn_batch_stride; +reg [31:0] reg2dp_bn_line_stride; +reg [31:0] reg2dp_bn_surface_stride; +reg reg2dp_brdma_data_mode; +reg reg2dp_brdma_data_size; +reg [1:0] reg2dp_brdma_data_use; +reg reg2dp_brdma_disable; +reg reg2dp_brdma_ram_type; +reg [31:0] reg2dp_bs_base_addr_high; +reg [31:0] reg2dp_bs_base_addr_low; +reg [31:0] reg2dp_bs_batch_stride; +reg [31:0] reg2dp_bs_line_stride; +reg [31:0] reg2dp_bs_surface_stride; +reg [12:0] reg2dp_channel; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg reg2dp_erdma_data_mode; +reg reg2dp_erdma_data_size; +reg [1:0] reg2dp_erdma_data_use; +reg reg2dp_erdma_disable; +reg reg2dp_erdma_ram_type; +reg [31:0] reg2dp_ew_base_addr_high; +reg [31:0] reg2dp_ew_base_addr_low; +reg [31:0] reg2dp_ew_batch_stride; +reg [31:0] reg2dp_ew_line_stride; +reg [31:0] reg2dp_ew_surface_stride; +reg reg2dp_flying_mode; +reg [12:0] reg2dp_height; +reg [1:0] reg2dp_in_precision; +reg reg2dp_nrdma_data_mode; +reg reg2dp_nrdma_data_size; +reg [1:0] reg2dp_nrdma_data_use; +reg reg2dp_nrdma_disable; +reg reg2dp_nrdma_ram_type; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_out_precision; +reg reg2dp_perf_dma_en; +reg reg2dp_perf_nan_inf_count_en; +reg [1:0] reg2dp_proc_precision; +reg [31:0] reg2dp_src_base_addr_high; +reg [31:0] reg2dp_src_base_addr_low; +reg [31:0] reg2dp_src_line_stride; +reg reg2dp_src_ram_type; +reg [31:0] reg2dp_src_surface_stride; +reg [12:0] reg2dp_width; +reg reg2dp_winograd; +reg [62:0] req_pd; +reg req_pvld; +reg [33:0] sdp_rdma2csb_resp_pd; +reg sdp_rdma2csb_resp_valid; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_SDP_RDMA_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.producer (reg2dp_producer) //|> w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_SDP_RDMA_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bn_base_addr_high (reg2dp_d0_bn_base_addr_high[31:0]) //|> w + ,.bn_base_addr_low (reg2dp_d0_bn_base_addr_low[31:0]) //|> w + ,.bn_batch_stride (reg2dp_d0_bn_batch_stride[31:0]) //|> w + ,.bn_line_stride (reg2dp_d0_bn_line_stride[31:0]) //|> w + ,.bn_surface_stride (reg2dp_d0_bn_surface_stride[31:0]) //|> w + ,.brdma_data_mode (reg2dp_d0_brdma_data_mode) //|> w + ,.brdma_data_size (reg2dp_d0_brdma_data_size) //|> w + ,.brdma_data_use (reg2dp_d0_brdma_data_use[1:0]) //|> w + ,.brdma_disable (reg2dp_d0_brdma_disable) //|> w + ,.brdma_ram_type (reg2dp_d0_brdma_ram_type) //|> w + ,.bs_base_addr_high (reg2dp_d0_bs_base_addr_high[31:0]) //|> w + ,.bs_base_addr_low (reg2dp_d0_bs_base_addr_low[31:0]) //|> w + ,.bs_batch_stride (reg2dp_d0_bs_batch_stride[31:0]) //|> w + ,.bs_line_stride (reg2dp_d0_bs_line_stride[31:0]) //|> w + ,.bs_surface_stride (reg2dp_d0_bs_surface_stride[31:0]) //|> w + ,.channel (reg2dp_d0_channel[12:0]) //|> w + ,.height (reg2dp_d0_height[12:0]) //|> w + ,.width (reg2dp_d0_width[12:0]) //|> w + ,.erdma_data_mode (reg2dp_d0_erdma_data_mode) //|> w + ,.erdma_data_size (reg2dp_d0_erdma_data_size) //|> w + ,.erdma_data_use (reg2dp_d0_erdma_data_use[1:0]) //|> w + ,.erdma_disable (reg2dp_d0_erdma_disable) //|> w + ,.erdma_ram_type (reg2dp_d0_erdma_ram_type) //|> w + ,.ew_base_addr_high (reg2dp_d0_ew_base_addr_high[31:0]) //|> w + ,.ew_base_addr_low (reg2dp_d0_ew_base_addr_low[31:0]) //|> w + ,.ew_batch_stride (reg2dp_d0_ew_batch_stride[31:0]) //|> w + ,.ew_line_stride (reg2dp_d0_ew_line_stride[31:0]) //|> w + ,.ew_surface_stride (reg2dp_d0_ew_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d0_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.in_precision (reg2dp_d0_in_precision[1:0]) //|> w + ,.out_precision (reg2dp_d0_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.winograd (reg2dp_d0_winograd) //|> w + ,.nrdma_data_mode (reg2dp_d0_nrdma_data_mode) //|> w + ,.nrdma_data_size (reg2dp_d0_nrdma_data_size) //|> w + ,.nrdma_data_use (reg2dp_d0_nrdma_data_use[1:0]) //|> w + ,.nrdma_disable (reg2dp_d0_nrdma_disable) //|> w + ,.nrdma_ram_type (reg2dp_d0_nrdma_ram_type) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d0_perf_dma_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d0_perf_nan_inf_count_en) //|> w + ,.src_base_addr_high (reg2dp_d0_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d0_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d0_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d0_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d0_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.brdma_stall (dp2reg_d0_brdma_stall[31:0]) //|< r + ,.erdma_stall (dp2reg_d0_erdma_stall[31:0]) //|< r + ,.mrdma_stall (dp2reg_d0_mrdma_stall[31:0]) //|< r + ,.nrdma_stall (dp2reg_d0_nrdma_stall[31:0]) //|< r + ,.status_inf_input_num (dp2reg_d0_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d0_status_nan_input_num[31:0]) //|< r + ); +NV_NVDLA_SDP_RDMA_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.bn_base_addr_high (reg2dp_d1_bn_base_addr_high[31:0]) //|> w + ,.bn_base_addr_low (reg2dp_d1_bn_base_addr_low[31:0]) //|> w + ,.bn_batch_stride (reg2dp_d1_bn_batch_stride[31:0]) //|> w + ,.bn_line_stride (reg2dp_d1_bn_line_stride[31:0]) //|> w + ,.bn_surface_stride (reg2dp_d1_bn_surface_stride[31:0]) //|> w + ,.brdma_data_mode (reg2dp_d1_brdma_data_mode) //|> w + ,.brdma_data_size (reg2dp_d1_brdma_data_size) //|> w + ,.brdma_data_use (reg2dp_d1_brdma_data_use[1:0]) //|> w + ,.brdma_disable (reg2dp_d1_brdma_disable) //|> w + ,.brdma_ram_type (reg2dp_d1_brdma_ram_type) //|> w + ,.bs_base_addr_high (reg2dp_d1_bs_base_addr_high[31:0]) //|> w + ,.bs_base_addr_low (reg2dp_d1_bs_base_addr_low[31:0]) //|> w + ,.bs_batch_stride (reg2dp_d1_bs_batch_stride[31:0]) //|> w + ,.bs_line_stride (reg2dp_d1_bs_line_stride[31:0]) //|> w + ,.bs_surface_stride (reg2dp_d1_bs_surface_stride[31:0]) //|> w + ,.channel (reg2dp_d1_channel[12:0]) //|> w + ,.height (reg2dp_d1_height[12:0]) //|> w + ,.width (reg2dp_d1_width[12:0]) //|> w + ,.erdma_data_mode (reg2dp_d1_erdma_data_mode) //|> w + ,.erdma_data_size (reg2dp_d1_erdma_data_size) //|> w + ,.erdma_data_use (reg2dp_d1_erdma_data_use[1:0]) //|> w + ,.erdma_disable (reg2dp_d1_erdma_disable) //|> w + ,.erdma_ram_type (reg2dp_d1_erdma_ram_type) //|> w + ,.ew_base_addr_high (reg2dp_d1_ew_base_addr_high[31:0]) //|> w + ,.ew_base_addr_low (reg2dp_d1_ew_base_addr_low[31:0]) //|> w + ,.ew_batch_stride (reg2dp_d1_ew_batch_stride[31:0]) //|> w + ,.ew_line_stride (reg2dp_d1_ew_line_stride[31:0]) //|> w + ,.ew_surface_stride (reg2dp_d1_ew_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d1_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.in_precision (reg2dp_d1_in_precision[1:0]) //|> w + ,.out_precision (reg2dp_d1_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.winograd (reg2dp_d1_winograd) //|> w + ,.nrdma_data_mode (reg2dp_d1_nrdma_data_mode) //|> w + ,.nrdma_data_size (reg2dp_d1_nrdma_data_size) //|> w + ,.nrdma_data_use (reg2dp_d1_nrdma_data_use[1:0]) //|> w + ,.nrdma_disable (reg2dp_d1_nrdma_disable) //|> w + ,.nrdma_ram_type (reg2dp_d1_nrdma_ram_type) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d1_perf_dma_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d1_perf_nan_inf_count_en) //|> w + ,.src_base_addr_high (reg2dp_d1_src_base_addr_high[31:0]) //|> w + ,.src_base_addr_low (reg2dp_d1_src_base_addr_low[31:0]) //|> w + ,.src_ram_type (reg2dp_d1_src_ram_type) //|> w + ,.src_line_stride (reg2dp_d1_src_line_stride[31:0]) //|> w + ,.src_surface_stride (reg2dp_d1_src_surface_stride[31:0]) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.brdma_stall (dp2reg_d1_brdma_stall[31:0]) //|< r + ,.erdma_stall (dp2reg_d1_erdma_stall[31:0]) //|< r + ,.mrdma_stall (dp2reg_d1_mrdma_stall[31:0]) //|< r + ,.nrdma_stall (dp2reg_d1_nrdma_stall[31:0]) //|< r + ,.status_inf_input_num (dp2reg_d1_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d1_status_nan_input_num[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'ha008 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'ha008 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'ha008 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2sdp_rdma_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2sdp_rdma_req_pvld) == 1'b1) begin + req_pd <= csb2sdp_rdma_req_pd; +// VCS coverage off + end else if ((csb2sdp_rdma_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2sdp_rdma_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2sdp_rdma_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + sdp_rdma2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + sdp_rdma2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp_rdma2csb_resp_valid <= 1'b0; + end else begin + sdp_rdma2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_bn_base_addr_high + or reg2dp_d0_bn_base_addr_high + ) begin + reg2dp_bn_base_addr_high = dp2reg_consumer ? reg2dp_d1_bn_base_addr_high : reg2dp_d0_bn_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_base_addr_low + or reg2dp_d0_bn_base_addr_low + ) begin + reg2dp_bn_base_addr_low = dp2reg_consumer ? reg2dp_d1_bn_base_addr_low : reg2dp_d0_bn_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_batch_stride + or reg2dp_d0_bn_batch_stride + ) begin + reg2dp_bn_batch_stride = dp2reg_consumer ? reg2dp_d1_bn_batch_stride : reg2dp_d0_bn_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_line_stride + or reg2dp_d0_bn_line_stride + ) begin + reg2dp_bn_line_stride = dp2reg_consumer ? reg2dp_d1_bn_line_stride : reg2dp_d0_bn_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_surface_stride + or reg2dp_d0_bn_surface_stride + ) begin + reg2dp_bn_surface_stride = dp2reg_consumer ? reg2dp_d1_bn_surface_stride : reg2dp_d0_bn_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_data_mode + or reg2dp_d0_brdma_data_mode + ) begin + reg2dp_brdma_data_mode = dp2reg_consumer ? reg2dp_d1_brdma_data_mode : reg2dp_d0_brdma_data_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_data_size + or reg2dp_d0_brdma_data_size + ) begin + reg2dp_brdma_data_size = dp2reg_consumer ? reg2dp_d1_brdma_data_size : reg2dp_d0_brdma_data_size; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_data_use + or reg2dp_d0_brdma_data_use + ) begin + reg2dp_brdma_data_use = dp2reg_consumer ? reg2dp_d1_brdma_data_use : reg2dp_d0_brdma_data_use; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_disable + or reg2dp_d0_brdma_disable + ) begin + reg2dp_brdma_disable = dp2reg_consumer ? reg2dp_d1_brdma_disable : reg2dp_d0_brdma_disable; +end +always @( + dp2reg_consumer + or reg2dp_d1_brdma_ram_type + or reg2dp_d0_brdma_ram_type + ) begin + reg2dp_brdma_ram_type = dp2reg_consumer ? reg2dp_d1_brdma_ram_type : reg2dp_d0_brdma_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_base_addr_high + or reg2dp_d0_bs_base_addr_high + ) begin + reg2dp_bs_base_addr_high = dp2reg_consumer ? reg2dp_d1_bs_base_addr_high : reg2dp_d0_bs_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_base_addr_low + or reg2dp_d0_bs_base_addr_low + ) begin + reg2dp_bs_base_addr_low = dp2reg_consumer ? reg2dp_d1_bs_base_addr_low : reg2dp_d0_bs_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_batch_stride + or reg2dp_d0_bs_batch_stride + ) begin + reg2dp_bs_batch_stride = dp2reg_consumer ? reg2dp_d1_bs_batch_stride : reg2dp_d0_bs_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_line_stride + or reg2dp_d0_bs_line_stride + ) begin + reg2dp_bs_line_stride = dp2reg_consumer ? reg2dp_d1_bs_line_stride : reg2dp_d0_bs_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_surface_stride + or reg2dp_d0_bs_surface_stride + ) begin + reg2dp_bs_surface_stride = dp2reg_consumer ? reg2dp_d1_bs_surface_stride : reg2dp_d0_bs_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_channel + or reg2dp_d0_channel + ) begin + reg2dp_channel = dp2reg_consumer ? reg2dp_d1_channel : reg2dp_d0_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_height + or reg2dp_d0_height + ) begin + reg2dp_height = dp2reg_consumer ? reg2dp_d1_height : reg2dp_d0_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_width + or reg2dp_d0_width + ) begin + reg2dp_width = dp2reg_consumer ? reg2dp_d1_width : reg2dp_d0_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_data_mode + or reg2dp_d0_erdma_data_mode + ) begin + reg2dp_erdma_data_mode = dp2reg_consumer ? reg2dp_d1_erdma_data_mode : reg2dp_d0_erdma_data_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_data_size + or reg2dp_d0_erdma_data_size + ) begin + reg2dp_erdma_data_size = dp2reg_consumer ? reg2dp_d1_erdma_data_size : reg2dp_d0_erdma_data_size; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_data_use + or reg2dp_d0_erdma_data_use + ) begin + reg2dp_erdma_data_use = dp2reg_consumer ? reg2dp_d1_erdma_data_use : reg2dp_d0_erdma_data_use; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_disable + or reg2dp_d0_erdma_disable + ) begin + reg2dp_erdma_disable = dp2reg_consumer ? reg2dp_d1_erdma_disable : reg2dp_d0_erdma_disable; +end +always @( + dp2reg_consumer + or reg2dp_d1_erdma_ram_type + or reg2dp_d0_erdma_ram_type + ) begin + reg2dp_erdma_ram_type = dp2reg_consumer ? reg2dp_d1_erdma_ram_type : reg2dp_d0_erdma_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_base_addr_high + or reg2dp_d0_ew_base_addr_high + ) begin + reg2dp_ew_base_addr_high = dp2reg_consumer ? reg2dp_d1_ew_base_addr_high : reg2dp_d0_ew_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_base_addr_low + or reg2dp_d0_ew_base_addr_low + ) begin + reg2dp_ew_base_addr_low = dp2reg_consumer ? reg2dp_d1_ew_base_addr_low : reg2dp_d0_ew_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_batch_stride + or reg2dp_d0_ew_batch_stride + ) begin + reg2dp_ew_batch_stride = dp2reg_consumer ? reg2dp_d1_ew_batch_stride : reg2dp_d0_ew_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_line_stride + or reg2dp_d0_ew_line_stride + ) begin + reg2dp_ew_line_stride = dp2reg_consumer ? reg2dp_d1_ew_line_stride : reg2dp_d0_ew_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_surface_stride + or reg2dp_d0_ew_surface_stride + ) begin + reg2dp_ew_surface_stride = dp2reg_consumer ? reg2dp_d1_ew_surface_stride : reg2dp_d0_ew_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_batch_number + or reg2dp_d0_batch_number + ) begin + reg2dp_batch_number = dp2reg_consumer ? reg2dp_d1_batch_number : reg2dp_d0_batch_number; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_in_precision + or reg2dp_d0_in_precision + ) begin + reg2dp_in_precision = dp2reg_consumer ? reg2dp_d1_in_precision : reg2dp_d0_in_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_out_precision + or reg2dp_d0_out_precision + ) begin + reg2dp_out_precision = dp2reg_consumer ? reg2dp_d1_out_precision : reg2dp_d0_out_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_winograd + or reg2dp_d0_winograd + ) begin + reg2dp_winograd = dp2reg_consumer ? reg2dp_d1_winograd : reg2dp_d0_winograd; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_data_mode + or reg2dp_d0_nrdma_data_mode + ) begin + reg2dp_nrdma_data_mode = dp2reg_consumer ? reg2dp_d1_nrdma_data_mode : reg2dp_d0_nrdma_data_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_data_size + or reg2dp_d0_nrdma_data_size + ) begin + reg2dp_nrdma_data_size = dp2reg_consumer ? reg2dp_d1_nrdma_data_size : reg2dp_d0_nrdma_data_size; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_data_use + or reg2dp_d0_nrdma_data_use + ) begin + reg2dp_nrdma_data_use = dp2reg_consumer ? reg2dp_d1_nrdma_data_use : reg2dp_d0_nrdma_data_use; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_disable + or reg2dp_d0_nrdma_disable + ) begin + reg2dp_nrdma_disable = dp2reg_consumer ? reg2dp_d1_nrdma_disable : reg2dp_d0_nrdma_disable; +end +always @( + dp2reg_consumer + or reg2dp_d1_nrdma_ram_type + or reg2dp_d0_nrdma_ram_type + ) begin + reg2dp_nrdma_ram_type = dp2reg_consumer ? reg2dp_d1_nrdma_ram_type : reg2dp_d0_nrdma_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_dma_en + or reg2dp_d0_perf_dma_en + ) begin + reg2dp_perf_dma_en = dp2reg_consumer ? reg2dp_d1_perf_dma_en : reg2dp_d0_perf_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_nan_inf_count_en + or reg2dp_d0_perf_nan_inf_count_en + ) begin + reg2dp_perf_nan_inf_count_en = dp2reg_consumer ? reg2dp_d1_perf_nan_inf_count_en : reg2dp_d0_perf_nan_inf_count_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_high + or reg2dp_d0_src_base_addr_high + ) begin + reg2dp_src_base_addr_high = dp2reg_consumer ? reg2dp_d1_src_base_addr_high : reg2dp_d0_src_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_base_addr_low + or reg2dp_d0_src_base_addr_low + ) begin + reg2dp_src_base_addr_low = dp2reg_consumer ? reg2dp_d1_src_base_addr_low : reg2dp_d0_src_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_ram_type + or reg2dp_d0_src_ram_type + ) begin + reg2dp_src_ram_type = dp2reg_consumer ? reg2dp_d1_src_ram_type : reg2dp_d0_src_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_line_stride + or reg2dp_d0_src_line_stride + ) begin + reg2dp_src_line_stride = dp2reg_consumer ? reg2dp_d1_src_line_stride : reg2dp_d0_src_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_src_surface_stride + or reg2dp_d0_src_surface_stride + ) begin + reg2dp_src_surface_stride = dp2reg_consumer ? reg2dp_d1_src_surface_stride : reg2dp_d0_src_surface_stride; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +// USER logic can be put here: +//////// Dual Flop Write Control//////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for overflow counting register //////// +assign dp2reg_d0_status_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_nan_input_num <= dp2reg_d0_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_brdma_stall_w = (dp2reg_d0_set) ? dp2reg_brdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_brdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_brdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_brdma_stall <= dp2reg_d0_brdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_brdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_inf_input_num <= dp2reg_d0_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_erdma_stall_w = (dp2reg_d0_set) ? dp2reg_erdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_erdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_erdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_erdma_stall <= dp2reg_d0_erdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_erdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_nrdma_stall_w = (dp2reg_d0_set) ? dp2reg_nrdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_nrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_nrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_nrdma_stall <= dp2reg_d0_nrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_nrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_mrdma_stall_w = (dp2reg_d0_set) ? dp2reg_mrdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_mrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_mrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_mrdma_stall <= dp2reg_d0_mrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_mrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_nan_input_num <= dp2reg_d1_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_brdma_stall_w = (dp2reg_d1_set) ? dp2reg_brdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_brdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_brdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_brdma_stall <= dp2reg_d1_brdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_brdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_inf_input_num <= dp2reg_d1_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_erdma_stall_w = (dp2reg_d1_set) ? dp2reg_erdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_erdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_erdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_erdma_stall <= dp2reg_d1_erdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_erdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_nrdma_stall_w = (dp2reg_d1_set) ? dp2reg_nrdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_nrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_nrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_nrdma_stall <= dp2reg_d1_nrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_nrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_mrdma_stall_w = (dp2reg_d1_set) ? dp2reg_mrdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_mrdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_mrdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_mrdma_stall <= dp2reg_d1_mrdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_mrdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_SDP_RDMA_reg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v new file mode 100644 index 0000000..f77707b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v @@ -0,0 +1,112 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_unpack.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_unpack ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_data + ,inp_pvld + ,inp_prdy + ,inp_end + ,out_pvld + ,out_data + ,out_prdy +); +parameter RATIO = 4*8*8/64; +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_end; +input inp_pvld; +output inp_prdy; +input [65 -1:0] inp_data; +output out_pvld; +input out_prdy; +output [4*8*8 +3:0] out_data; +reg [1:0] pack_cnt; +wire [2:0] pack_cnt_nxt; +reg mon_pack_cnt; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire is_pack_last; +reg [3:0] pack_mask; +reg [8*8 -1:0] pack_seq0; +reg [8*8 -1:0] pack_seq1; +reg [8*8 -1:0] pack_seq2; +reg [8*8 -1:0] pack_seq3; +wire [4*8*8 -1:0] pack_total; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | pack_prdy ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_pvld <= 1'b0; + else if (inp_prdy) + pack_pvld <= inp_pvld & is_pack_last; +end +assign inp_acc = inp_pvld & inp_prdy; +wire [3:0] data_mask = {{(4-1){1'b0}},inp_data[65 -1:64]}; +wire [1:0] data_size = data_mask[0] + data_mask[1] + data_mask[2] + data_mask[3]; +assign pack_cnt_nxt = pack_cnt + data_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_pack_cnt,pack_cnt} <= 3'h0; + end else begin + if (inp_acc) begin + if (is_pack_last) begin + {mon_pack_cnt,pack_cnt} <= 3'h0; + end else begin + {mon_pack_cnt,pack_cnt} <= pack_cnt_nxt; + end + end + end +end +assign is_pack_last = (pack_cnt_nxt == 3'h4) | inp_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_mask <= 4'h0; + else if (inp_acc & is_pack_last) + pack_mask <= pack_cnt_nxt == 3'h4 ? 4'hf : pack_cnt_nxt == 3'h3 ? 4'h7 : + pack_cnt_nxt == 3'h2 ? 4'h3 : pack_cnt_nxt; +end +generate +if(RATIO == 1) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) {pack_seq3,pack_seq2,pack_seq1,pack_seq0} <= inp_data[4*8*8 -1:0]; +end +end +else if(RATIO == 2) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==3'h0) {pack_seq1,pack_seq0} <= inp_data[2*8*8 -1:0]; + if (pack_cnt==3'h2) {pack_seq3,pack_seq2} <= inp_data[2*8*8 -1:0]; + end +end +end +else if(RATIO == 4) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==3'h0) pack_seq0 <= inp_data[8*8 -1:0]; + if (pack_cnt==3'h1) pack_seq1 <= inp_data[8*8 -1:0]; + if (pack_cnt==3'h2) pack_seq2 <= inp_data[8*8 -1:0]; + if (pack_cnt==3'h3) pack_seq3 <= inp_data[8*8 -1:0]; + end +end +end +endgenerate +assign pack_total = {pack_seq3,pack_seq2,pack_seq1,pack_seq0}; +assign out_data = {pack_mask[3:0],pack_total[4*8*8 -1:0]}; +endmodule // NV_NVDLA_SDP_RDMA_unpack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v.vcp new file mode 100644 index 0000000..f77707b --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v.vcp @@ -0,0 +1,112 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_RDMA_unpack.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_RDMA_unpack ( + nvdla_core_clk + ,nvdla_core_rstn + ,inp_data + ,inp_pvld + ,inp_prdy + ,inp_end + ,out_pvld + ,out_data + ,out_prdy +); +parameter RATIO = 4*8*8/64; +input nvdla_core_clk; +input nvdla_core_rstn; +input inp_end; +input inp_pvld; +output inp_prdy; +input [65 -1:0] inp_data; +output out_pvld; +input out_prdy; +output [4*8*8 +3:0] out_data; +reg [1:0] pack_cnt; +wire [2:0] pack_cnt_nxt; +reg mon_pack_cnt; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire is_pack_last; +reg [3:0] pack_mask; +reg [8*8 -1:0] pack_seq0; +reg [8*8 -1:0] pack_seq1; +reg [8*8 -1:0] pack_seq2; +reg [8*8 -1:0] pack_seq3; +wire [4*8*8 -1:0] pack_total; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | pack_prdy ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_pvld <= 1'b0; + else if (inp_prdy) + pack_pvld <= inp_pvld & is_pack_last; +end +assign inp_acc = inp_pvld & inp_prdy; +wire [3:0] data_mask = {{(4-1){1'b0}},inp_data[65 -1:64]}; +wire [1:0] data_size = data_mask[0] + data_mask[1] + data_mask[2] + data_mask[3]; +assign pack_cnt_nxt = pack_cnt + data_size; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_pack_cnt,pack_cnt} <= 3'h0; + end else begin + if (inp_acc) begin + if (is_pack_last) begin + {mon_pack_cnt,pack_cnt} <= 3'h0; + end else begin + {mon_pack_cnt,pack_cnt} <= pack_cnt_nxt; + end + end + end +end +assign is_pack_last = (pack_cnt_nxt == 3'h4) | inp_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) + pack_mask <= 4'h0; + else if (inp_acc & is_pack_last) + pack_mask <= pack_cnt_nxt == 3'h4 ? 4'hf : pack_cnt_nxt == 3'h3 ? 4'h7 : + pack_cnt_nxt == 3'h2 ? 4'h3 : pack_cnt_nxt; +end +generate +if(RATIO == 1) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) {pack_seq3,pack_seq2,pack_seq1,pack_seq0} <= inp_data[4*8*8 -1:0]; +end +end +else if(RATIO == 2) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==3'h0) {pack_seq1,pack_seq0} <= inp_data[2*8*8 -1:0]; + if (pack_cnt==3'h2) {pack_seq3,pack_seq2} <= inp_data[2*8*8 -1:0]; + end +end +end +else if(RATIO == 4) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==3'h0) pack_seq0 <= inp_data[8*8 -1:0]; + if (pack_cnt==3'h1) pack_seq1 <= inp_data[8*8 -1:0]; + if (pack_cnt==3'h2) pack_seq2 <= inp_data[8*8 -1:0]; + if (pack_cnt==3'h3) pack_seq3 <= inp_data[8*8 -1:0]; + end +end +end +endgenerate +assign pack_total = {pack_seq3,pack_seq2,pack_seq1,pack_seq0}; +assign out_data = {pack_mask[3:0],pack_total[4*8*8 -1:0]}; +endmodule // NV_NVDLA_SDP_RDMA_unpack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v new file mode 100644 index 0000000..4424eb0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v @@ -0,0 +1,1085 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_REG_dual.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cvt_offset + ,cvt_scale + ,cvt_shift + ,channel + ,height + ,width + ,out_precision + ,proc_precision + ,bn_alu_shift_value + ,bn_alu_src + ,bn_alu_operand + ,bn_alu_algo + ,bn_alu_bypass + ,bn_bypass + ,bn_mul_bypass + ,bn_mul_prelu + ,bn_relu_bypass + ,bn_mul_shift_value + ,bn_mul_src + ,bn_mul_operand + ,bs_alu_shift_value + ,bs_alu_src + ,bs_alu_operand + ,bs_alu_algo + ,bs_alu_bypass + ,bs_bypass + ,bs_mul_bypass + ,bs_mul_prelu + ,bs_relu_bypass + ,bs_mul_shift_value + ,bs_mul_src + ,bs_mul_operand + ,ew_alu_cvt_bypass + ,ew_alu_src + ,ew_alu_cvt_offset + ,ew_alu_cvt_scale + ,ew_alu_cvt_truncate + ,ew_alu_operand + ,ew_alu_algo + ,ew_alu_bypass + ,ew_bypass + ,ew_lut_bypass + ,ew_mul_bypass + ,ew_mul_prelu + ,ew_mul_cvt_bypass + ,ew_mul_src + ,ew_mul_cvt_offset + ,ew_mul_cvt_scale + ,ew_mul_cvt_truncate + ,ew_mul_operand + ,ew_truncate + ,dst_base_addr_high + ,dst_base_addr_low + ,dst_batch_stride + ,dst_ram_type + ,dst_line_stride + ,dst_surface_stride + ,batch_number + ,flying_mode + ,nan_to_zero + ,output_dst + ,winograd + ,op_en_trigger + ,perf_dma_en + ,perf_lut_en + ,perf_nan_inf_count_en + ,perf_sat_en + ,op_en + ,lut_hybrid + ,lut_le_hit + ,lut_lo_hit + ,lut_oflow + ,lut_uflow + ,out_saturation + ,wdma_stall + ,status_unequal + ,status_inf_input_num + ,status_nan_input_num + ,status_nan_output_num + ); +wire [31:0] nvdla_sdp_d_cvt_offset_0_out; +wire [31:0] nvdla_sdp_d_cvt_scale_0_out; +wire [31:0] nvdla_sdp_d_cvt_shift_0_out; +wire [31:0] nvdla_sdp_d_data_cube_channel_0_out; +wire [31:0] nvdla_sdp_d_data_cube_height_0_out; +wire [31:0] nvdla_sdp_d_data_cube_width_0_out; +wire [31:0] nvdla_sdp_d_data_format_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_alu_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_alu_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_mul_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_mul_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_alu_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_alu_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_mul_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_mul_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_truncate_value_0_out; +wire [31:0] nvdla_sdp_d_dst_base_addr_high_0_out; +wire [31:0] nvdla_sdp_d_dst_base_addr_low_0_out; +wire [31:0] nvdla_sdp_d_dst_batch_stride_0_out; +wire [31:0] nvdla_sdp_d_dst_dma_cfg_0_out; +wire [31:0] nvdla_sdp_d_dst_line_stride_0_out; +wire [31:0] nvdla_sdp_d_dst_surface_stride_0_out; +wire [31:0] nvdla_sdp_d_feature_mode_cfg_0_out; +wire [31:0] nvdla_sdp_d_op_enable_0_out; +wire [31:0] nvdla_sdp_d_perf_enable_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_hybrid_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_le_hit_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_lo_hit_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_oflow_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_uflow_0_out; +wire [31:0] nvdla_sdp_d_perf_out_saturation_0_out; +wire [31:0] nvdla_sdp_d_perf_wdma_write_stall_0_out; +wire [31:0] nvdla_sdp_d_status_0_out; +wire [31:0] nvdla_sdp_d_status_inf_input_num_0_out; +wire [31:0] nvdla_sdp_d_status_nan_input_num_0_out; +wire [31:0] nvdla_sdp_d_status_nan_output_num_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cvt_offset; +output [15:0] cvt_scale; +output [5:0] cvt_shift; +output [12:0] channel; +output [12:0] height; +output [12:0] width; +output [1:0] out_precision; +output [1:0] proc_precision; +output [5:0] bn_alu_shift_value; +output bn_alu_src; +output [15:0] bn_alu_operand; +output [1:0] bn_alu_algo; +output bn_alu_bypass; +output bn_bypass; +output bn_mul_bypass; +output bn_mul_prelu; +output bn_relu_bypass; +output [7:0] bn_mul_shift_value; +output bn_mul_src; +output [15:0] bn_mul_operand; +output [5:0] bs_alu_shift_value; +output bs_alu_src; +output [15:0] bs_alu_operand; +output [1:0] bs_alu_algo; +output bs_alu_bypass; +output bs_bypass; +output bs_mul_bypass; +output bs_mul_prelu; +output bs_relu_bypass; +output [7:0] bs_mul_shift_value; +output bs_mul_src; +output [15:0] bs_mul_operand; +output ew_alu_cvt_bypass; +output ew_alu_src; +output [31:0] ew_alu_cvt_offset; +output [15:0] ew_alu_cvt_scale; +output [5:0] ew_alu_cvt_truncate; +output [31:0] ew_alu_operand; +output [1:0] ew_alu_algo; +output ew_alu_bypass; +output ew_bypass; +output ew_lut_bypass; +output ew_mul_bypass; +output ew_mul_prelu; +output ew_mul_cvt_bypass; +output ew_mul_src; +output [31:0] ew_mul_cvt_offset; +output [15:0] ew_mul_cvt_scale; +output [5:0] ew_mul_cvt_truncate; +output [31:0] ew_mul_operand; +output [9:0] ew_truncate; +output [31:0] dst_base_addr_high; +output [31:0] dst_base_addr_low; +output [31:0] dst_batch_stride; +output dst_ram_type; +output [31:0] dst_line_stride; +output [31:0] dst_surface_stride; +output [4:0] batch_number; +output flying_mode; +output nan_to_zero; +output output_dst; +output winograd; +output op_en_trigger; +output perf_dma_en; +output perf_lut_en; +output perf_nan_inf_count_en; +output perf_sat_en; +// Read-only register inputs +input op_en; +input [31:0] lut_hybrid; +input [31:0] lut_le_hit; +input [31:0] lut_lo_hit; +input [31:0] lut_oflow; +input [31:0] lut_uflow; +input [31:0] out_saturation; +input [31:0] wdma_stall; +input status_unequal; +input [31:0] status_inf_input_num; +input [31:0] status_nan_input_num; +input [31:0] status_nan_output_num; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [4:0] batch_number; +reg [1:0] bn_alu_algo; +reg bn_alu_bypass; +reg [15:0] bn_alu_operand; +reg [5:0] bn_alu_shift_value; +reg bn_alu_src; +reg bn_bypass; +reg bn_mul_bypass; +reg [15:0] bn_mul_operand; +reg bn_mul_prelu; +reg [7:0] bn_mul_shift_value; +reg bn_mul_src; +reg bn_relu_bypass; +reg [1:0] bs_alu_algo; +reg bs_alu_bypass; +reg [15:0] bs_alu_operand; +reg [5:0] bs_alu_shift_value; +reg bs_alu_src; +reg bs_bypass; +reg bs_mul_bypass; +reg [15:0] bs_mul_operand; +reg bs_mul_prelu; +reg [7:0] bs_mul_shift_value; +reg bs_mul_src; +reg bs_relu_bypass; +reg [12:0] channel; +reg [31:0] cvt_offset; +reg [15:0] cvt_scale; +reg [5:0] cvt_shift; +reg [31:0] dst_base_addr_high; +reg [31:0] dst_base_addr_low; +reg [31:0] dst_batch_stride; +reg [31:0] dst_line_stride; +reg dst_ram_type; +reg [31:0] dst_surface_stride; +reg [1:0] ew_alu_algo; +reg ew_alu_bypass; +reg ew_alu_cvt_bypass; +reg [31:0] ew_alu_cvt_offset; +reg [15:0] ew_alu_cvt_scale; +reg [5:0] ew_alu_cvt_truncate; +reg [31:0] ew_alu_operand; +reg ew_alu_src; +reg ew_bypass; +reg ew_lut_bypass; +reg ew_mul_bypass; +reg ew_mul_cvt_bypass; +reg [31:0] ew_mul_cvt_offset; +reg [15:0] ew_mul_cvt_scale; +reg [5:0] ew_mul_cvt_truncate; +reg [31:0] ew_mul_operand; +reg ew_mul_prelu; +reg ew_mul_src; +reg [9:0] ew_truncate; +reg flying_mode; +reg [12:0] height; +reg nan_to_zero; +reg [1:0] out_precision; +reg output_dst; +reg perf_dma_en; +reg perf_lut_en; +reg perf_nan_inf_count_en; +reg perf_sat_en; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [12:0] width; +reg winograd; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_d_cvt_offset_0_wren = (reg_offset_wr == (32'hb0c0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_cvt_scale_0_wren = (reg_offset_wr == (32'hb0c4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_cvt_shift_0_wren = (reg_offset_wr == (32'hb0c8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_cube_channel_0_wren = (reg_offset_wr == (32'hb044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_cube_height_0_wren = (reg_offset_wr == (32'hb040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_cube_width_0_wren = (reg_offset_wr == (32'hb03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_format_0_wren = (reg_offset_wr == (32'hb0bc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_alu_cfg_0_wren = (reg_offset_wr == (32'hb070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_alu_src_value_0_wren = (reg_offset_wr == (32'hb074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_cfg_0_wren = (reg_offset_wr == (32'hb06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_mul_cfg_0_wren = (reg_offset_wr == (32'hb078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_mul_src_value_0_wren = (reg_offset_wr == (32'hb07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_alu_cfg_0_wren = (reg_offset_wr == (32'hb05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_alu_src_value_0_wren = (reg_offset_wr == (32'hb060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_cfg_0_wren = (reg_offset_wr == (32'hb058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_mul_cfg_0_wren = (reg_offset_wr == (32'hb064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_mul_src_value_0_wren = (reg_offset_wr == (32'hb068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cfg_0_wren = (reg_offset_wr == (32'hb084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_wren = (reg_offset_wr == (32'hb08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_wren = (reg_offset_wr == (32'hb090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_wren = (reg_offset_wr == (32'hb094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_src_value_0_wren = (reg_offset_wr == (32'hb088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_cfg_0_wren = (reg_offset_wr == (32'hb080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cfg_0_wren = (reg_offset_wr == (32'hb098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_wren = (reg_offset_wr == (32'hb0a0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_wren = (reg_offset_wr == (32'hb0a4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_wren = (reg_offset_wr == (32'hb0a8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_src_value_0_wren = (reg_offset_wr == (32'hb09c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_truncate_value_0_wren = (reg_offset_wr == (32'hb0ac & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_base_addr_high_0_wren = (reg_offset_wr == (32'hb04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_base_addr_low_0_wren = (reg_offset_wr == (32'hb048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_batch_stride_0_wren = (reg_offset_wr == (32'hb0b8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_dma_cfg_0_wren = (reg_offset_wr == (32'hb0b4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_line_stride_0_wren = (reg_offset_wr == (32'hb050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_surface_stride_0_wren = (reg_offset_wr == (32'hb054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_feature_mode_cfg_0_wren = (reg_offset_wr == (32'hb0b0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_op_enable_0_wren = (reg_offset_wr == (32'hb038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_enable_0_wren = (reg_offset_wr == (32'hb0dc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_hybrid_0_wren = (reg_offset_wr == (32'hb0f0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_le_hit_0_wren = (reg_offset_wr == (32'hb0f4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_lo_hit_0_wren = (reg_offset_wr == (32'hb0f8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_oflow_0_wren = (reg_offset_wr == (32'hb0e8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_uflow_0_wren = (reg_offset_wr == (32'hb0e4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_out_saturation_0_wren = (reg_offset_wr == (32'hb0ec & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_wdma_write_stall_0_wren = (reg_offset_wr == (32'hb0e0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_0_wren = (reg_offset_wr == (32'hb0cc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_inf_input_num_0_wren = (reg_offset_wr == (32'hb0d4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_nan_input_num_0_wren = (reg_offset_wr == (32'hb0d0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_nan_output_num_0_wren = (reg_offset_wr == (32'hb0d8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_d_cvt_offset_0_out[31:0] = { cvt_offset }; +assign nvdla_sdp_d_cvt_scale_0_out[31:0] = { 16'b0, cvt_scale }; +assign nvdla_sdp_d_cvt_shift_0_out[31:0] = { 26'b0, cvt_shift }; +assign nvdla_sdp_d_data_cube_channel_0_out[31:0] = { 19'b0, channel }; +assign nvdla_sdp_d_data_cube_height_0_out[31:0] = { 19'b0, height }; +assign nvdla_sdp_d_data_cube_width_0_out[31:0] = { 19'b0, width }; +assign nvdla_sdp_d_data_format_0_out[31:0] = { 28'b0, out_precision, proc_precision }; +assign nvdla_sdp_d_dp_bn_alu_cfg_0_out[31:0] = { 18'b0, bn_alu_shift_value, 7'b0, bn_alu_src }; +assign nvdla_sdp_d_dp_bn_alu_src_value_0_out[31:0] = { 16'b0, bn_alu_operand }; +assign nvdla_sdp_d_dp_bn_cfg_0_out[31:0] = { 25'b0, bn_relu_bypass, bn_mul_prelu, bn_mul_bypass, bn_alu_algo, bn_alu_bypass, bn_bypass }; +assign nvdla_sdp_d_dp_bn_mul_cfg_0_out[31:0] = { 16'b0, bn_mul_shift_value, 7'b0, bn_mul_src }; +assign nvdla_sdp_d_dp_bn_mul_src_value_0_out[31:0] = { 16'b0, bn_mul_operand }; +assign nvdla_sdp_d_dp_bs_alu_cfg_0_out[31:0] = { 18'b0, bs_alu_shift_value, 7'b0, bs_alu_src }; +assign nvdla_sdp_d_dp_bs_alu_src_value_0_out[31:0] = { 16'b0, bs_alu_operand }; +assign nvdla_sdp_d_dp_bs_cfg_0_out[31:0] = { 25'b0, bs_relu_bypass, bs_mul_prelu, bs_mul_bypass, bs_alu_algo, bs_alu_bypass, bs_bypass }; +assign nvdla_sdp_d_dp_bs_mul_cfg_0_out[31:0] = { 16'b0, bs_mul_shift_value, 7'b0, bs_mul_src }; +assign nvdla_sdp_d_dp_bs_mul_src_value_0_out[31:0] = { 16'b0, bs_mul_operand }; +assign nvdla_sdp_d_dp_ew_alu_cfg_0_out[31:0] = { 30'b0, ew_alu_cvt_bypass, ew_alu_src }; +assign nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out[31:0] = { ew_alu_cvt_offset }; +assign nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out[31:0] = { 16'b0, ew_alu_cvt_scale }; +assign nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out[31:0] = { 26'b0, ew_alu_cvt_truncate }; +assign nvdla_sdp_d_dp_ew_alu_src_value_0_out[31:0] = { ew_alu_operand }; +assign nvdla_sdp_d_dp_ew_cfg_0_out[31:0] = { 25'b0, ew_lut_bypass, ew_mul_prelu, ew_mul_bypass, ew_alu_algo, ew_alu_bypass, ew_bypass }; +assign nvdla_sdp_d_dp_ew_mul_cfg_0_out[31:0] = { 30'b0, ew_mul_cvt_bypass, ew_mul_src }; +assign nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out[31:0] = { ew_mul_cvt_offset }; +assign nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out[31:0] = { 16'b0, ew_mul_cvt_scale }; +assign nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out[31:0] = { 26'b0, ew_mul_cvt_truncate }; +assign nvdla_sdp_d_dp_ew_mul_src_value_0_out[31:0] = { ew_mul_operand }; +assign nvdla_sdp_d_dp_ew_truncate_value_0_out[31:0] = { 22'b0, ew_truncate }; +assign nvdla_sdp_d_dst_base_addr_high_0_out[31:0] = { dst_base_addr_high }; +assign nvdla_sdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low}; +assign nvdla_sdp_d_dst_batch_stride_0_out[31:0] = { dst_batch_stride}; +assign nvdla_sdp_d_dst_dma_cfg_0_out[31:0] = { 31'b0, dst_ram_type }; +assign nvdla_sdp_d_dst_line_stride_0_out[31:0] = { dst_line_stride}; +assign nvdla_sdp_d_dst_surface_stride_0_out[31:0] = { dst_surface_stride}; +assign nvdla_sdp_d_feature_mode_cfg_0_out[31:0] = { 19'b0, batch_number, 4'b0, nan_to_zero, winograd, output_dst, flying_mode }; +assign nvdla_sdp_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_sdp_d_perf_enable_0_out[31:0] = { 28'b0, perf_nan_inf_count_en, perf_sat_en, perf_lut_en, perf_dma_en }; +assign nvdla_sdp_d_perf_lut_hybrid_0_out[31:0] = { lut_hybrid }; +assign nvdla_sdp_d_perf_lut_le_hit_0_out[31:0] = { lut_le_hit }; +assign nvdla_sdp_d_perf_lut_lo_hit_0_out[31:0] = { lut_lo_hit }; +assign nvdla_sdp_d_perf_lut_oflow_0_out[31:0] = { lut_oflow }; +assign nvdla_sdp_d_perf_lut_uflow_0_out[31:0] = { lut_uflow }; +assign nvdla_sdp_d_perf_out_saturation_0_out[31:0] = { out_saturation }; +assign nvdla_sdp_d_perf_wdma_write_stall_0_out[31:0] = { wdma_stall }; +assign nvdla_sdp_d_status_0_out[31:0] = { 31'b0, status_unequal }; +assign nvdla_sdp_d_status_inf_input_num_0_out[31:0] = { status_inf_input_num }; +assign nvdla_sdp_d_status_nan_input_num_0_out[31:0] = { status_nan_input_num }; +assign nvdla_sdp_d_status_nan_output_num_0_out[31:0] = { status_nan_output_num }; +assign op_en_trigger = nvdla_sdp_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_d_cvt_offset_0_out + or nvdla_sdp_d_cvt_scale_0_out + or nvdla_sdp_d_cvt_shift_0_out + or nvdla_sdp_d_data_cube_channel_0_out + or nvdla_sdp_d_data_cube_height_0_out + or nvdla_sdp_d_data_cube_width_0_out + or nvdla_sdp_d_data_format_0_out + or nvdla_sdp_d_dp_bn_alu_cfg_0_out + or nvdla_sdp_d_dp_bn_alu_src_value_0_out + or nvdla_sdp_d_dp_bn_cfg_0_out + or nvdla_sdp_d_dp_bn_mul_cfg_0_out + or nvdla_sdp_d_dp_bn_mul_src_value_0_out + or nvdla_sdp_d_dp_bs_alu_cfg_0_out + or nvdla_sdp_d_dp_bs_alu_src_value_0_out + or nvdla_sdp_d_dp_bs_cfg_0_out + or nvdla_sdp_d_dp_bs_mul_cfg_0_out + or nvdla_sdp_d_dp_bs_mul_src_value_0_out + or nvdla_sdp_d_dp_ew_alu_cfg_0_out + or nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out + or nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out + or nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out + or nvdla_sdp_d_dp_ew_alu_src_value_0_out + or nvdla_sdp_d_dp_ew_cfg_0_out + or nvdla_sdp_d_dp_ew_mul_cfg_0_out + or nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out + or nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out + or nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out + or nvdla_sdp_d_dp_ew_mul_src_value_0_out + or nvdla_sdp_d_dp_ew_truncate_value_0_out + or nvdla_sdp_d_dst_base_addr_high_0_out + or nvdla_sdp_d_dst_base_addr_low_0_out + or nvdla_sdp_d_dst_batch_stride_0_out + or nvdla_sdp_d_dst_dma_cfg_0_out + or nvdla_sdp_d_dst_line_stride_0_out + or nvdla_sdp_d_dst_surface_stride_0_out + or nvdla_sdp_d_feature_mode_cfg_0_out + or nvdla_sdp_d_op_enable_0_out + or nvdla_sdp_d_perf_enable_0_out + or nvdla_sdp_d_perf_lut_hybrid_0_out + or nvdla_sdp_d_perf_lut_le_hit_0_out + or nvdla_sdp_d_perf_lut_lo_hit_0_out + or nvdla_sdp_d_perf_lut_oflow_0_out + or nvdla_sdp_d_perf_lut_uflow_0_out + or nvdla_sdp_d_perf_out_saturation_0_out + or nvdla_sdp_d_perf_wdma_write_stall_0_out + or nvdla_sdp_d_status_0_out + or nvdla_sdp_d_status_inf_input_num_0_out + or nvdla_sdp_d_status_nan_input_num_0_out + or nvdla_sdp_d_status_nan_output_num_0_out + ) begin + case (reg_offset_rd_int) + (32'hb0c0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_cvt_offset_0_out ; + end + (32'hb0c4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_cvt_scale_0_out ; + end + (32'hb0c8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_cvt_shift_0_out ; + end + (32'hb044 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_cube_channel_0_out ; + end + (32'hb040 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_cube_height_0_out ; + end + (32'hb03c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_cube_width_0_out ; + end + (32'hb0bc & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_format_0_out ; + end + (32'hb070 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_alu_cfg_0_out ; + end + (32'hb074 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_alu_src_value_0_out ; + end + (32'hb06c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_cfg_0_out ; + end + (32'hb078 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_mul_cfg_0_out ; + end + (32'hb07c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_mul_src_value_0_out ; + end + (32'hb05c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_alu_cfg_0_out ; + end + (32'hb060 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_alu_src_value_0_out ; + end + (32'hb058 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_cfg_0_out ; + end + (32'hb064 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_mul_cfg_0_out ; + end + (32'hb068 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_mul_src_value_0_out ; + end + (32'hb084 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cfg_0_out ; + end + (32'hb08c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out ; + end + (32'hb090 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out ; + end + (32'hb094 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out ; + end + (32'hb088 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_src_value_0_out ; + end + (32'hb080 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_cfg_0_out ; + end + (32'hb098 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cfg_0_out ; + end + (32'hb0a0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out ; + end + (32'hb0a4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out ; + end + (32'hb0a8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out ; + end + (32'hb09c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_src_value_0_out ; + end + (32'hb0ac & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_truncate_value_0_out ; + end + (32'hb04c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_base_addr_high_0_out ; + end + (32'hb048 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_base_addr_low_0_out ; + end + (32'hb0b8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_batch_stride_0_out ; + end + (32'hb0b4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_dma_cfg_0_out ; + end + (32'hb050 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_line_stride_0_out ; + end + (32'hb054 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_surface_stride_0_out ; + end + (32'hb0b0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_feature_mode_cfg_0_out ; + end + (32'hb038 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_op_enable_0_out ; + end + (32'hb0dc & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_enable_0_out ; + end + (32'hb0f0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_hybrid_0_out ; + end + (32'hb0f4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_le_hit_0_out ; + end + (32'hb0f8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_lo_hit_0_out ; + end + (32'hb0e8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_oflow_0_out ; + end + (32'hb0e4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_uflow_0_out ; + end + (32'hb0ec & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_out_saturation_0_out ; + end + (32'hb0e0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_wdma_write_stall_0_out ; + end + (32'hb0cc & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_0_out ; + end + (32'hb0d4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_inf_input_num_0_out ; + end + (32'hb0d0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_nan_input_num_0_out ; + end + (32'hb0d8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_nan_output_num_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_offset[31:0] <= 32'h0; + cvt_scale[15:0] <= 16'b0000000000000000; + cvt_shift[5:0] <= 6'b000000; + channel[12:0] <= 13'b0000000000000; + height[12:0] <= 13'b0000000000000; + width[12:0] <= 13'b0000000000000; + out_precision[1:0] <= 2'b00; + proc_precision[1:0] <= 2'b00; + bn_alu_shift_value[5:0] <= 6'b000000; + bn_alu_src <= 1'b0; + bn_alu_operand[15:0] <= 16'b0000000000000000; + bn_alu_algo[1:0] <= 2'b00; + bn_alu_bypass <= 1'b1; + bn_bypass <= 1'b1; + bn_mul_bypass <= 1'b1; + bn_mul_prelu <= 1'b0; + bn_relu_bypass <= 1'b1; + bn_mul_shift_value[7:0] <= 8'b00000000; + bn_mul_src <= 1'b0; + bn_mul_operand[15:0] <= 16'b0000000000000000; + bs_alu_shift_value[5:0] <= 6'b000000; + bs_alu_src <= 1'b0; + bs_alu_operand[15:0] <= 16'b0000000000000000; + bs_alu_algo[1:0] <= 2'b00; + bs_alu_bypass <= 1'b1; + bs_bypass <= 1'b1; + bs_mul_bypass <= 1'b1; + bs_mul_prelu <= 1'b1; + bs_relu_bypass <= 1'b1; + bs_mul_shift_value[7:0] <= 8'b00000000; + bs_mul_src <= 1'b0; + bs_mul_operand[15:0] <= 16'b0000000000000000; + ew_alu_cvt_bypass <= 1'b1; + ew_alu_src <= 1'b0; + ew_alu_cvt_offset[31:0] <= 32'h0; + ew_alu_cvt_scale[15:0] <= 16'b0000000000000000; + ew_alu_cvt_truncate[5:0] <= 6'b000000; + ew_alu_operand[31:0] <= 32'h0; + ew_alu_algo[1:0] <= 2'b00; + ew_alu_bypass <= 1'b1; + ew_bypass <= 1'b1; + ew_lut_bypass <= 1'b1; + ew_mul_bypass <= 1'b1; + ew_mul_prelu <= 1'b0; + ew_mul_cvt_bypass <= 1'b1; + ew_mul_src <= 1'b0; + ew_mul_cvt_offset[31:0] <= 32'h0; + ew_mul_cvt_scale[15:0] <= 16'b0000000000000000; + ew_mul_cvt_truncate[5:0] <= 6'b000000; + ew_mul_operand[31:0] <= 32'h0; + ew_truncate[9:0] <= 10'b0000000000; + dst_base_addr_high[31:0] <= 32'h0; + dst_base_addr_low[31:0] <= {(32){1'b0}}; + dst_batch_stride[31:0] <= {(32){1'b0}}; + dst_ram_type <= 1'b0; + dst_line_stride[31:0] <= {(32){1'b0}}; + dst_surface_stride[31:0] <= {(32){1'b0}}; + batch_number[4:0] <= 5'b00000; + flying_mode <= 1'b0; + nan_to_zero <= 1'b0; + output_dst <= 1'b0; + winograd <= 1'b0; + perf_dma_en <= 1'b0; + perf_lut_en <= 1'b0; + perf_nan_inf_count_en <= 1'b0; + perf_sat_en <= 1'b0; + end else begin +// Register: NVDLA_SDP_D_CVT_OFFSET_0 Field: cvt_offset + if (nvdla_sdp_d_cvt_offset_0_wren) begin + cvt_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_CVT_SCALE_0 Field: cvt_scale + if (nvdla_sdp_d_cvt_scale_0_wren) begin + cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_CVT_SHIFT_0 Field: cvt_shift + if (nvdla_sdp_d_cvt_shift_0_wren) begin + cvt_shift[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_SDP_D_DATA_CUBE_CHANNEL_0 Field: channel + if (nvdla_sdp_d_data_cube_channel_0_wren) begin + channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_D_DATA_CUBE_HEIGHT_0 Field: height + if (nvdla_sdp_d_data_cube_height_0_wren) begin + height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_D_DATA_CUBE_WIDTH_0 Field: width + if (nvdla_sdp_d_data_cube_width_0_wren) begin + width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_D_DATA_FORMAT_0 Field: out_precision + if (nvdla_sdp_d_data_format_0_wren) begin + out_precision[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DATA_FORMAT_0 Field: proc_precision + if (nvdla_sdp_d_data_format_0_wren) begin + proc_precision[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_SDP_D_DP_BN_ALU_CFG_0 Field: bn_alu_shift_value + if (nvdla_sdp_d_dp_bn_alu_cfg_0_wren) begin + bn_alu_shift_value[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_SDP_D_DP_BN_ALU_CFG_0 Field: bn_alu_src + if (nvdla_sdp_d_dp_bn_alu_cfg_0_wren) begin + bn_alu_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BN_ALU_SRC_VALUE_0 Field: bn_alu_operand + if (nvdla_sdp_d_dp_bn_alu_src_value_0_wren) begin + bn_alu_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_alu_algo + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_alu_algo[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_alu_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_alu_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_bypass <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_mul_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_mul_bypass <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_mul_prelu + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_mul_prelu <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_relu_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_relu_bypass <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_D_DP_BN_MUL_CFG_0 Field: bn_mul_shift_value + if (nvdla_sdp_d_dp_bn_mul_cfg_0_wren) begin + bn_mul_shift_value[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_SDP_D_DP_BN_MUL_CFG_0 Field: bn_mul_src + if (nvdla_sdp_d_dp_bn_mul_cfg_0_wren) begin + bn_mul_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BN_MUL_SRC_VALUE_0 Field: bn_mul_operand + if (nvdla_sdp_d_dp_bn_mul_src_value_0_wren) begin + bn_mul_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_BS_ALU_CFG_0 Field: bs_alu_shift_value + if (nvdla_sdp_d_dp_bs_alu_cfg_0_wren) begin + bs_alu_shift_value[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_SDP_D_DP_BS_ALU_CFG_0 Field: bs_alu_src + if (nvdla_sdp_d_dp_bs_alu_cfg_0_wren) begin + bs_alu_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BS_ALU_SRC_VALUE_0 Field: bs_alu_operand + if (nvdla_sdp_d_dp_bs_alu_src_value_0_wren) begin + bs_alu_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_alu_algo + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_alu_algo[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_alu_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_alu_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_bypass <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_mul_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_mul_bypass <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_mul_prelu + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_mul_prelu <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_relu_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_relu_bypass <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_D_DP_BS_MUL_CFG_0 Field: bs_mul_shift_value + if (nvdla_sdp_d_dp_bs_mul_cfg_0_wren) begin + bs_mul_shift_value[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_SDP_D_DP_BS_MUL_CFG_0 Field: bs_mul_src + if (nvdla_sdp_d_dp_bs_mul_cfg_0_wren) begin + bs_mul_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BS_MUL_SRC_VALUE_0 Field: bs_mul_operand + if (nvdla_sdp_d_dp_bs_mul_src_value_0_wren) begin + bs_mul_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CFG_0 Field: ew_alu_cvt_bypass + if (nvdla_sdp_d_dp_ew_alu_cfg_0_wren) begin + ew_alu_cvt_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CFG_0 Field: ew_alu_src + if (nvdla_sdp_d_dp_ew_alu_cfg_0_wren) begin + ew_alu_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 Field: ew_alu_cvt_offset + if (nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_wren) begin + ew_alu_cvt_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 Field: ew_alu_cvt_scale + if (nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_wren) begin + ew_alu_cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 Field: ew_alu_cvt_truncate + if (nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_wren) begin + ew_alu_cvt_truncate[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_SRC_VALUE_0 Field: ew_alu_operand + if (nvdla_sdp_d_dp_ew_alu_src_value_0_wren) begin + ew_alu_operand[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_alu_algo + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_alu_algo[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_alu_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_alu_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_bypass <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_lut_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_lut_bypass <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_mul_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_mul_bypass <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_mul_prelu + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_mul_prelu <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CFG_0 Field: ew_mul_cvt_bypass + if (nvdla_sdp_d_dp_ew_mul_cfg_0_wren) begin + ew_mul_cvt_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CFG_0 Field: ew_mul_src + if (nvdla_sdp_d_dp_ew_mul_cfg_0_wren) begin + ew_mul_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 Field: ew_mul_cvt_offset + if (nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_wren) begin + ew_mul_cvt_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 Field: ew_mul_cvt_scale + if (nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_wren) begin + ew_mul_cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 Field: ew_mul_cvt_truncate + if (nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_wren) begin + ew_mul_cvt_truncate[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_SRC_VALUE_0 Field: ew_mul_operand + if (nvdla_sdp_d_dp_ew_mul_src_value_0_wren) begin + ew_mul_operand[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_TRUNCATE_VALUE_0 Field: ew_truncate + if (nvdla_sdp_d_dp_ew_truncate_value_0_wren) begin + ew_truncate[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_SDP_D_DST_BASE_ADDR_HIGH_0 Field: dst_base_addr_high + if (nvdla_sdp_d_dst_base_addr_high_0_wren) begin + dst_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_BASE_ADDR_LOW_0 Field: dst_base_addr_low + if (nvdla_sdp_d_dst_base_addr_low_0_wren) begin + dst_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_BATCH_STRIDE_0 Field: dst_batch_stride + if (nvdla_sdp_d_dst_batch_stride_0_wren) begin + dst_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_DMA_CFG_0 Field: dst_ram_type + if (nvdla_sdp_d_dst_dma_cfg_0_wren) begin + dst_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DST_LINE_STRIDE_0 Field: dst_line_stride + if (nvdla_sdp_d_dst_line_stride_0_wren) begin + dst_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_SURFACE_STRIDE_0 Field: dst_surface_stride + if (nvdla_sdp_d_dst_surface_stride_0_wren) begin + dst_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: batch_number + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + batch_number[4:0] <= reg_wr_data[12:8]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: flying_mode + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + flying_mode <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: nan_to_zero + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + nan_to_zero <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: output_dst + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + output_dst <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: winograd + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + winograd <= reg_wr_data[2]; + end +// Not generating flops for field NVDLA_SDP_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_dma_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_dma_en <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_lut_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_lut_en <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_nan_inf_count_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_nan_inf_count_en <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_sat_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_sat_en <= reg_wr_data[2]; + end +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_HYBRID_0::lut_hybrid +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_LE_HIT_0::lut_le_hit +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_LO_HIT_0::lut_lo_hit +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_OFLOW_0::lut_oflow +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_UFLOW_0::lut_uflow +// Not generating flops for read-only field NVDLA_SDP_D_PERF_OUT_SATURATION_0::out_saturation +// Not generating flops for read-only field NVDLA_SDP_D_PERF_WDMA_WRITE_STALL_0::wdma_stall +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_0::status_unequal +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_INF_INPUT_NUM_0::status_inf_input_num +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_NAN_INPUT_NUM_0::status_nan_input_num +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_NAN_OUTPUT_NUM_0::status_nan_output_num + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hb0c0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_CVT_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_cvt_offset_0_out, nvdla_sdp_d_cvt_offset_0_out); + (32'hb0c4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_CVT_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_cvt_scale_0_out, nvdla_sdp_d_cvt_scale_0_out); + (32'hb0c8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_CVT_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_cvt_shift_0_out, nvdla_sdp_d_cvt_shift_0_out); + (32'hb044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_CUBE_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_cube_channel_0_out, nvdla_sdp_d_data_cube_channel_0_out); + (32'hb040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_CUBE_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_cube_height_0_out, nvdla_sdp_d_data_cube_height_0_out); + (32'hb03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_CUBE_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_cube_width_0_out, nvdla_sdp_d_data_cube_width_0_out); + (32'hb0bc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_format_0_out, nvdla_sdp_d_data_format_0_out); + (32'hb070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_ALU_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_alu_cfg_0_out, nvdla_sdp_d_dp_bn_alu_cfg_0_out); + (32'hb074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_ALU_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_alu_src_value_0_out, nvdla_sdp_d_dp_bn_alu_src_value_0_out); + (32'hb06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_cfg_0_out, nvdla_sdp_d_dp_bn_cfg_0_out); + (32'hb078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_MUL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_mul_cfg_0_out, nvdla_sdp_d_dp_bn_mul_cfg_0_out); + (32'hb07c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_MUL_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_mul_src_value_0_out, nvdla_sdp_d_dp_bn_mul_src_value_0_out); + (32'hb05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_ALU_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_alu_cfg_0_out, nvdla_sdp_d_dp_bs_alu_cfg_0_out); + (32'hb060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_ALU_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_alu_src_value_0_out, nvdla_sdp_d_dp_bs_alu_src_value_0_out); + (32'hb058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_cfg_0_out, nvdla_sdp_d_dp_bs_cfg_0_out); + (32'hb064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_MUL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_mul_cfg_0_out, nvdla_sdp_d_dp_bs_mul_cfg_0_out); + (32'hb068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_MUL_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_mul_src_value_0_out, nvdla_sdp_d_dp_bs_mul_src_value_0_out); + (32'hb084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cfg_0_out, nvdla_sdp_d_dp_ew_alu_cfg_0_out); + (32'hb08c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out, nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out); + (32'hb090 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out, nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out); + (32'hb094 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out, nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out); + (32'hb088 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_src_value_0_out, nvdla_sdp_d_dp_ew_alu_src_value_0_out); + (32'hb080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_cfg_0_out, nvdla_sdp_d_dp_ew_cfg_0_out); + (32'hb098 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cfg_0_out, nvdla_sdp_d_dp_ew_mul_cfg_0_out); + (32'hb0a0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out, nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out); + (32'hb0a4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out, nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out); + (32'hb0a8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out, nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out); + (32'hb09c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_src_value_0_out, nvdla_sdp_d_dp_ew_mul_src_value_0_out); + (32'hb0ac & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_TRUNCATE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_truncate_value_0_out, nvdla_sdp_d_dp_ew_truncate_value_0_out); + (32'hb04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_base_addr_high_0_out, nvdla_sdp_d_dst_base_addr_high_0_out); + (32'hb048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_base_addr_low_0_out, nvdla_sdp_d_dst_base_addr_low_0_out); + (32'hb0b8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_batch_stride_0_out, nvdla_sdp_d_dst_batch_stride_0_out); + (32'hb0b4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_dma_cfg_0_out, nvdla_sdp_d_dst_dma_cfg_0_out); + (32'hb050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_line_stride_0_out, nvdla_sdp_d_dst_line_stride_0_out); + (32'hb054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_surface_stride_0_out, nvdla_sdp_d_dst_surface_stride_0_out); + (32'hb0b0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_FEATURE_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_feature_mode_cfg_0_out, nvdla_sdp_d_feature_mode_cfg_0_out); + (32'hb038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_op_enable_0_out, nvdla_sdp_d_op_enable_0_out); + (32'hb0dc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_perf_enable_0_out, nvdla_sdp_d_perf_enable_0_out); + (32'hb0f0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_HYBRID_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0f4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_LE_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0f8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_LO_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0e8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_OFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0e4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_UFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0ec & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_OUT_SATURATION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0e0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_WDMA_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0cc & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0d4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0d0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0d8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_NAN_OUTPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v.vcp new file mode 100644 index 0000000..4424eb0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v.vcp @@ -0,0 +1,1085 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_REG_dual.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_REG_dual ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,cvt_offset + ,cvt_scale + ,cvt_shift + ,channel + ,height + ,width + ,out_precision + ,proc_precision + ,bn_alu_shift_value + ,bn_alu_src + ,bn_alu_operand + ,bn_alu_algo + ,bn_alu_bypass + ,bn_bypass + ,bn_mul_bypass + ,bn_mul_prelu + ,bn_relu_bypass + ,bn_mul_shift_value + ,bn_mul_src + ,bn_mul_operand + ,bs_alu_shift_value + ,bs_alu_src + ,bs_alu_operand + ,bs_alu_algo + ,bs_alu_bypass + ,bs_bypass + ,bs_mul_bypass + ,bs_mul_prelu + ,bs_relu_bypass + ,bs_mul_shift_value + ,bs_mul_src + ,bs_mul_operand + ,ew_alu_cvt_bypass + ,ew_alu_src + ,ew_alu_cvt_offset + ,ew_alu_cvt_scale + ,ew_alu_cvt_truncate + ,ew_alu_operand + ,ew_alu_algo + ,ew_alu_bypass + ,ew_bypass + ,ew_lut_bypass + ,ew_mul_bypass + ,ew_mul_prelu + ,ew_mul_cvt_bypass + ,ew_mul_src + ,ew_mul_cvt_offset + ,ew_mul_cvt_scale + ,ew_mul_cvt_truncate + ,ew_mul_operand + ,ew_truncate + ,dst_base_addr_high + ,dst_base_addr_low + ,dst_batch_stride + ,dst_ram_type + ,dst_line_stride + ,dst_surface_stride + ,batch_number + ,flying_mode + ,nan_to_zero + ,output_dst + ,winograd + ,op_en_trigger + ,perf_dma_en + ,perf_lut_en + ,perf_nan_inf_count_en + ,perf_sat_en + ,op_en + ,lut_hybrid + ,lut_le_hit + ,lut_lo_hit + ,lut_oflow + ,lut_uflow + ,out_saturation + ,wdma_stall + ,status_unequal + ,status_inf_input_num + ,status_nan_input_num + ,status_nan_output_num + ); +wire [31:0] nvdla_sdp_d_cvt_offset_0_out; +wire [31:0] nvdla_sdp_d_cvt_scale_0_out; +wire [31:0] nvdla_sdp_d_cvt_shift_0_out; +wire [31:0] nvdla_sdp_d_data_cube_channel_0_out; +wire [31:0] nvdla_sdp_d_data_cube_height_0_out; +wire [31:0] nvdla_sdp_d_data_cube_width_0_out; +wire [31:0] nvdla_sdp_d_data_format_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_alu_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_alu_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_mul_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bn_mul_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_alu_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_alu_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_mul_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_bs_mul_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_alu_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cfg_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_mul_src_value_0_out; +wire [31:0] nvdla_sdp_d_dp_ew_truncate_value_0_out; +wire [31:0] nvdla_sdp_d_dst_base_addr_high_0_out; +wire [31:0] nvdla_sdp_d_dst_base_addr_low_0_out; +wire [31:0] nvdla_sdp_d_dst_batch_stride_0_out; +wire [31:0] nvdla_sdp_d_dst_dma_cfg_0_out; +wire [31:0] nvdla_sdp_d_dst_line_stride_0_out; +wire [31:0] nvdla_sdp_d_dst_surface_stride_0_out; +wire [31:0] nvdla_sdp_d_feature_mode_cfg_0_out; +wire [31:0] nvdla_sdp_d_op_enable_0_out; +wire [31:0] nvdla_sdp_d_perf_enable_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_hybrid_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_le_hit_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_lo_hit_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_oflow_0_out; +wire [31:0] nvdla_sdp_d_perf_lut_uflow_0_out; +wire [31:0] nvdla_sdp_d_perf_out_saturation_0_out; +wire [31:0] nvdla_sdp_d_perf_wdma_write_stall_0_out; +wire [31:0] nvdla_sdp_d_status_0_out; +wire [31:0] nvdla_sdp_d_status_inf_input_num_0_out; +wire [31:0] nvdla_sdp_d_status_nan_input_num_0_out; +wire [31:0] nvdla_sdp_d_status_nan_output_num_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output [31:0] cvt_offset; +output [15:0] cvt_scale; +output [5:0] cvt_shift; +output [12:0] channel; +output [12:0] height; +output [12:0] width; +output [1:0] out_precision; +output [1:0] proc_precision; +output [5:0] bn_alu_shift_value; +output bn_alu_src; +output [15:0] bn_alu_operand; +output [1:0] bn_alu_algo; +output bn_alu_bypass; +output bn_bypass; +output bn_mul_bypass; +output bn_mul_prelu; +output bn_relu_bypass; +output [7:0] bn_mul_shift_value; +output bn_mul_src; +output [15:0] bn_mul_operand; +output [5:0] bs_alu_shift_value; +output bs_alu_src; +output [15:0] bs_alu_operand; +output [1:0] bs_alu_algo; +output bs_alu_bypass; +output bs_bypass; +output bs_mul_bypass; +output bs_mul_prelu; +output bs_relu_bypass; +output [7:0] bs_mul_shift_value; +output bs_mul_src; +output [15:0] bs_mul_operand; +output ew_alu_cvt_bypass; +output ew_alu_src; +output [31:0] ew_alu_cvt_offset; +output [15:0] ew_alu_cvt_scale; +output [5:0] ew_alu_cvt_truncate; +output [31:0] ew_alu_operand; +output [1:0] ew_alu_algo; +output ew_alu_bypass; +output ew_bypass; +output ew_lut_bypass; +output ew_mul_bypass; +output ew_mul_prelu; +output ew_mul_cvt_bypass; +output ew_mul_src; +output [31:0] ew_mul_cvt_offset; +output [15:0] ew_mul_cvt_scale; +output [5:0] ew_mul_cvt_truncate; +output [31:0] ew_mul_operand; +output [9:0] ew_truncate; +output [31:0] dst_base_addr_high; +output [31:0] dst_base_addr_low; +output [31:0] dst_batch_stride; +output dst_ram_type; +output [31:0] dst_line_stride; +output [31:0] dst_surface_stride; +output [4:0] batch_number; +output flying_mode; +output nan_to_zero; +output output_dst; +output winograd; +output op_en_trigger; +output perf_dma_en; +output perf_lut_en; +output perf_nan_inf_count_en; +output perf_sat_en; +// Read-only register inputs +input op_en; +input [31:0] lut_hybrid; +input [31:0] lut_le_hit; +input [31:0] lut_lo_hit; +input [31:0] lut_oflow; +input [31:0] lut_uflow; +input [31:0] out_saturation; +input [31:0] wdma_stall; +input status_unequal; +input [31:0] status_inf_input_num; +input [31:0] status_nan_input_num; +input [31:0] status_nan_output_num; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg [4:0] batch_number; +reg [1:0] bn_alu_algo; +reg bn_alu_bypass; +reg [15:0] bn_alu_operand; +reg [5:0] bn_alu_shift_value; +reg bn_alu_src; +reg bn_bypass; +reg bn_mul_bypass; +reg [15:0] bn_mul_operand; +reg bn_mul_prelu; +reg [7:0] bn_mul_shift_value; +reg bn_mul_src; +reg bn_relu_bypass; +reg [1:0] bs_alu_algo; +reg bs_alu_bypass; +reg [15:0] bs_alu_operand; +reg [5:0] bs_alu_shift_value; +reg bs_alu_src; +reg bs_bypass; +reg bs_mul_bypass; +reg [15:0] bs_mul_operand; +reg bs_mul_prelu; +reg [7:0] bs_mul_shift_value; +reg bs_mul_src; +reg bs_relu_bypass; +reg [12:0] channel; +reg [31:0] cvt_offset; +reg [15:0] cvt_scale; +reg [5:0] cvt_shift; +reg [31:0] dst_base_addr_high; +reg [31:0] dst_base_addr_low; +reg [31:0] dst_batch_stride; +reg [31:0] dst_line_stride; +reg dst_ram_type; +reg [31:0] dst_surface_stride; +reg [1:0] ew_alu_algo; +reg ew_alu_bypass; +reg ew_alu_cvt_bypass; +reg [31:0] ew_alu_cvt_offset; +reg [15:0] ew_alu_cvt_scale; +reg [5:0] ew_alu_cvt_truncate; +reg [31:0] ew_alu_operand; +reg ew_alu_src; +reg ew_bypass; +reg ew_lut_bypass; +reg ew_mul_bypass; +reg ew_mul_cvt_bypass; +reg [31:0] ew_mul_cvt_offset; +reg [15:0] ew_mul_cvt_scale; +reg [5:0] ew_mul_cvt_truncate; +reg [31:0] ew_mul_operand; +reg ew_mul_prelu; +reg ew_mul_src; +reg [9:0] ew_truncate; +reg flying_mode; +reg [12:0] height; +reg nan_to_zero; +reg [1:0] out_precision; +reg output_dst; +reg perf_dma_en; +reg perf_lut_en; +reg perf_nan_inf_count_en; +reg perf_sat_en; +reg [1:0] proc_precision; +reg [31:0] reg_rd_data; +reg [12:0] width; +reg winograd; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_d_cvt_offset_0_wren = (reg_offset_wr == (32'hb0c0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_cvt_scale_0_wren = (reg_offset_wr == (32'hb0c4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_cvt_shift_0_wren = (reg_offset_wr == (32'hb0c8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_cube_channel_0_wren = (reg_offset_wr == (32'hb044 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_cube_height_0_wren = (reg_offset_wr == (32'hb040 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_cube_width_0_wren = (reg_offset_wr == (32'hb03c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_data_format_0_wren = (reg_offset_wr == (32'hb0bc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_alu_cfg_0_wren = (reg_offset_wr == (32'hb070 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_alu_src_value_0_wren = (reg_offset_wr == (32'hb074 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_cfg_0_wren = (reg_offset_wr == (32'hb06c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_mul_cfg_0_wren = (reg_offset_wr == (32'hb078 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bn_mul_src_value_0_wren = (reg_offset_wr == (32'hb07c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_alu_cfg_0_wren = (reg_offset_wr == (32'hb05c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_alu_src_value_0_wren = (reg_offset_wr == (32'hb060 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_cfg_0_wren = (reg_offset_wr == (32'hb058 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_mul_cfg_0_wren = (reg_offset_wr == (32'hb064 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_bs_mul_src_value_0_wren = (reg_offset_wr == (32'hb068 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cfg_0_wren = (reg_offset_wr == (32'hb084 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_wren = (reg_offset_wr == (32'hb08c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_wren = (reg_offset_wr == (32'hb090 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_wren = (reg_offset_wr == (32'hb094 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_alu_src_value_0_wren = (reg_offset_wr == (32'hb088 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_cfg_0_wren = (reg_offset_wr == (32'hb080 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cfg_0_wren = (reg_offset_wr == (32'hb098 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_wren = (reg_offset_wr == (32'hb0a0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_wren = (reg_offset_wr == (32'hb0a4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_wren = (reg_offset_wr == (32'hb0a8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_mul_src_value_0_wren = (reg_offset_wr == (32'hb09c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dp_ew_truncate_value_0_wren = (reg_offset_wr == (32'hb0ac & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_base_addr_high_0_wren = (reg_offset_wr == (32'hb04c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_base_addr_low_0_wren = (reg_offset_wr == (32'hb048 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_batch_stride_0_wren = (reg_offset_wr == (32'hb0b8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_dma_cfg_0_wren = (reg_offset_wr == (32'hb0b4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_line_stride_0_wren = (reg_offset_wr == (32'hb050 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_dst_surface_stride_0_wren = (reg_offset_wr == (32'hb054 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_feature_mode_cfg_0_wren = (reg_offset_wr == (32'hb0b0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_op_enable_0_wren = (reg_offset_wr == (32'hb038 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_enable_0_wren = (reg_offset_wr == (32'hb0dc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_hybrid_0_wren = (reg_offset_wr == (32'hb0f0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_le_hit_0_wren = (reg_offset_wr == (32'hb0f4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_lo_hit_0_wren = (reg_offset_wr == (32'hb0f8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_oflow_0_wren = (reg_offset_wr == (32'hb0e8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_lut_uflow_0_wren = (reg_offset_wr == (32'hb0e4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_out_saturation_0_wren = (reg_offset_wr == (32'hb0ec & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_perf_wdma_write_stall_0_wren = (reg_offset_wr == (32'hb0e0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_0_wren = (reg_offset_wr == (32'hb0cc & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_inf_input_num_0_wren = (reg_offset_wr == (32'hb0d4 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_nan_input_num_0_wren = (reg_offset_wr == (32'hb0d0 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_d_status_nan_output_num_0_wren = (reg_offset_wr == (32'hb0d8 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_d_cvt_offset_0_out[31:0] = { cvt_offset }; +assign nvdla_sdp_d_cvt_scale_0_out[31:0] = { 16'b0, cvt_scale }; +assign nvdla_sdp_d_cvt_shift_0_out[31:0] = { 26'b0, cvt_shift }; +assign nvdla_sdp_d_data_cube_channel_0_out[31:0] = { 19'b0, channel }; +assign nvdla_sdp_d_data_cube_height_0_out[31:0] = { 19'b0, height }; +assign nvdla_sdp_d_data_cube_width_0_out[31:0] = { 19'b0, width }; +assign nvdla_sdp_d_data_format_0_out[31:0] = { 28'b0, out_precision, proc_precision }; +assign nvdla_sdp_d_dp_bn_alu_cfg_0_out[31:0] = { 18'b0, bn_alu_shift_value, 7'b0, bn_alu_src }; +assign nvdla_sdp_d_dp_bn_alu_src_value_0_out[31:0] = { 16'b0, bn_alu_operand }; +assign nvdla_sdp_d_dp_bn_cfg_0_out[31:0] = { 25'b0, bn_relu_bypass, bn_mul_prelu, bn_mul_bypass, bn_alu_algo, bn_alu_bypass, bn_bypass }; +assign nvdla_sdp_d_dp_bn_mul_cfg_0_out[31:0] = { 16'b0, bn_mul_shift_value, 7'b0, bn_mul_src }; +assign nvdla_sdp_d_dp_bn_mul_src_value_0_out[31:0] = { 16'b0, bn_mul_operand }; +assign nvdla_sdp_d_dp_bs_alu_cfg_0_out[31:0] = { 18'b0, bs_alu_shift_value, 7'b0, bs_alu_src }; +assign nvdla_sdp_d_dp_bs_alu_src_value_0_out[31:0] = { 16'b0, bs_alu_operand }; +assign nvdla_sdp_d_dp_bs_cfg_0_out[31:0] = { 25'b0, bs_relu_bypass, bs_mul_prelu, bs_mul_bypass, bs_alu_algo, bs_alu_bypass, bs_bypass }; +assign nvdla_sdp_d_dp_bs_mul_cfg_0_out[31:0] = { 16'b0, bs_mul_shift_value, 7'b0, bs_mul_src }; +assign nvdla_sdp_d_dp_bs_mul_src_value_0_out[31:0] = { 16'b0, bs_mul_operand }; +assign nvdla_sdp_d_dp_ew_alu_cfg_0_out[31:0] = { 30'b0, ew_alu_cvt_bypass, ew_alu_src }; +assign nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out[31:0] = { ew_alu_cvt_offset }; +assign nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out[31:0] = { 16'b0, ew_alu_cvt_scale }; +assign nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out[31:0] = { 26'b0, ew_alu_cvt_truncate }; +assign nvdla_sdp_d_dp_ew_alu_src_value_0_out[31:0] = { ew_alu_operand }; +assign nvdla_sdp_d_dp_ew_cfg_0_out[31:0] = { 25'b0, ew_lut_bypass, ew_mul_prelu, ew_mul_bypass, ew_alu_algo, ew_alu_bypass, ew_bypass }; +assign nvdla_sdp_d_dp_ew_mul_cfg_0_out[31:0] = { 30'b0, ew_mul_cvt_bypass, ew_mul_src }; +assign nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out[31:0] = { ew_mul_cvt_offset }; +assign nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out[31:0] = { 16'b0, ew_mul_cvt_scale }; +assign nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out[31:0] = { 26'b0, ew_mul_cvt_truncate }; +assign nvdla_sdp_d_dp_ew_mul_src_value_0_out[31:0] = { ew_mul_operand }; +assign nvdla_sdp_d_dp_ew_truncate_value_0_out[31:0] = { 22'b0, ew_truncate }; +assign nvdla_sdp_d_dst_base_addr_high_0_out[31:0] = { dst_base_addr_high }; +assign nvdla_sdp_d_dst_base_addr_low_0_out[31:0] = { dst_base_addr_low}; +assign nvdla_sdp_d_dst_batch_stride_0_out[31:0] = { dst_batch_stride}; +assign nvdla_sdp_d_dst_dma_cfg_0_out[31:0] = { 31'b0, dst_ram_type }; +assign nvdla_sdp_d_dst_line_stride_0_out[31:0] = { dst_line_stride}; +assign nvdla_sdp_d_dst_surface_stride_0_out[31:0] = { dst_surface_stride}; +assign nvdla_sdp_d_feature_mode_cfg_0_out[31:0] = { 19'b0, batch_number, 4'b0, nan_to_zero, winograd, output_dst, flying_mode }; +assign nvdla_sdp_d_op_enable_0_out[31:0] = { 31'b0, op_en }; +assign nvdla_sdp_d_perf_enable_0_out[31:0] = { 28'b0, perf_nan_inf_count_en, perf_sat_en, perf_lut_en, perf_dma_en }; +assign nvdla_sdp_d_perf_lut_hybrid_0_out[31:0] = { lut_hybrid }; +assign nvdla_sdp_d_perf_lut_le_hit_0_out[31:0] = { lut_le_hit }; +assign nvdla_sdp_d_perf_lut_lo_hit_0_out[31:0] = { lut_lo_hit }; +assign nvdla_sdp_d_perf_lut_oflow_0_out[31:0] = { lut_oflow }; +assign nvdla_sdp_d_perf_lut_uflow_0_out[31:0] = { lut_uflow }; +assign nvdla_sdp_d_perf_out_saturation_0_out[31:0] = { out_saturation }; +assign nvdla_sdp_d_perf_wdma_write_stall_0_out[31:0] = { wdma_stall }; +assign nvdla_sdp_d_status_0_out[31:0] = { 31'b0, status_unequal }; +assign nvdla_sdp_d_status_inf_input_num_0_out[31:0] = { status_inf_input_num }; +assign nvdla_sdp_d_status_nan_input_num_0_out[31:0] = { status_nan_input_num }; +assign nvdla_sdp_d_status_nan_output_num_0_out[31:0] = { status_nan_output_num }; +assign op_en_trigger = nvdla_sdp_d_op_enable_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_d_cvt_offset_0_out + or nvdla_sdp_d_cvt_scale_0_out + or nvdla_sdp_d_cvt_shift_0_out + or nvdla_sdp_d_data_cube_channel_0_out + or nvdla_sdp_d_data_cube_height_0_out + or nvdla_sdp_d_data_cube_width_0_out + or nvdla_sdp_d_data_format_0_out + or nvdla_sdp_d_dp_bn_alu_cfg_0_out + or nvdla_sdp_d_dp_bn_alu_src_value_0_out + or nvdla_sdp_d_dp_bn_cfg_0_out + or nvdla_sdp_d_dp_bn_mul_cfg_0_out + or nvdla_sdp_d_dp_bn_mul_src_value_0_out + or nvdla_sdp_d_dp_bs_alu_cfg_0_out + or nvdla_sdp_d_dp_bs_alu_src_value_0_out + or nvdla_sdp_d_dp_bs_cfg_0_out + or nvdla_sdp_d_dp_bs_mul_cfg_0_out + or nvdla_sdp_d_dp_bs_mul_src_value_0_out + or nvdla_sdp_d_dp_ew_alu_cfg_0_out + or nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out + or nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out + or nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out + or nvdla_sdp_d_dp_ew_alu_src_value_0_out + or nvdla_sdp_d_dp_ew_cfg_0_out + or nvdla_sdp_d_dp_ew_mul_cfg_0_out + or nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out + or nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out + or nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out + or nvdla_sdp_d_dp_ew_mul_src_value_0_out + or nvdla_sdp_d_dp_ew_truncate_value_0_out + or nvdla_sdp_d_dst_base_addr_high_0_out + or nvdla_sdp_d_dst_base_addr_low_0_out + or nvdla_sdp_d_dst_batch_stride_0_out + or nvdla_sdp_d_dst_dma_cfg_0_out + or nvdla_sdp_d_dst_line_stride_0_out + or nvdla_sdp_d_dst_surface_stride_0_out + or nvdla_sdp_d_feature_mode_cfg_0_out + or nvdla_sdp_d_op_enable_0_out + or nvdla_sdp_d_perf_enable_0_out + or nvdla_sdp_d_perf_lut_hybrid_0_out + or nvdla_sdp_d_perf_lut_le_hit_0_out + or nvdla_sdp_d_perf_lut_lo_hit_0_out + or nvdla_sdp_d_perf_lut_oflow_0_out + or nvdla_sdp_d_perf_lut_uflow_0_out + or nvdla_sdp_d_perf_out_saturation_0_out + or nvdla_sdp_d_perf_wdma_write_stall_0_out + or nvdla_sdp_d_status_0_out + or nvdla_sdp_d_status_inf_input_num_0_out + or nvdla_sdp_d_status_nan_input_num_0_out + or nvdla_sdp_d_status_nan_output_num_0_out + ) begin + case (reg_offset_rd_int) + (32'hb0c0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_cvt_offset_0_out ; + end + (32'hb0c4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_cvt_scale_0_out ; + end + (32'hb0c8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_cvt_shift_0_out ; + end + (32'hb044 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_cube_channel_0_out ; + end + (32'hb040 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_cube_height_0_out ; + end + (32'hb03c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_cube_width_0_out ; + end + (32'hb0bc & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_data_format_0_out ; + end + (32'hb070 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_alu_cfg_0_out ; + end + (32'hb074 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_alu_src_value_0_out ; + end + (32'hb06c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_cfg_0_out ; + end + (32'hb078 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_mul_cfg_0_out ; + end + (32'hb07c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bn_mul_src_value_0_out ; + end + (32'hb05c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_alu_cfg_0_out ; + end + (32'hb060 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_alu_src_value_0_out ; + end + (32'hb058 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_cfg_0_out ; + end + (32'hb064 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_mul_cfg_0_out ; + end + (32'hb068 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_bs_mul_src_value_0_out ; + end + (32'hb084 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cfg_0_out ; + end + (32'hb08c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out ; + end + (32'hb090 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out ; + end + (32'hb094 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out ; + end + (32'hb088 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_alu_src_value_0_out ; + end + (32'hb080 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_cfg_0_out ; + end + (32'hb098 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cfg_0_out ; + end + (32'hb0a0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out ; + end + (32'hb0a4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out ; + end + (32'hb0a8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out ; + end + (32'hb09c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_mul_src_value_0_out ; + end + (32'hb0ac & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dp_ew_truncate_value_0_out ; + end + (32'hb04c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_base_addr_high_0_out ; + end + (32'hb048 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_base_addr_low_0_out ; + end + (32'hb0b8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_batch_stride_0_out ; + end + (32'hb0b4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_dma_cfg_0_out ; + end + (32'hb050 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_line_stride_0_out ; + end + (32'hb054 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_dst_surface_stride_0_out ; + end + (32'hb0b0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_feature_mode_cfg_0_out ; + end + (32'hb038 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_op_enable_0_out ; + end + (32'hb0dc & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_enable_0_out ; + end + (32'hb0f0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_hybrid_0_out ; + end + (32'hb0f4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_le_hit_0_out ; + end + (32'hb0f8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_lo_hit_0_out ; + end + (32'hb0e8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_oflow_0_out ; + end + (32'hb0e4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_lut_uflow_0_out ; + end + (32'hb0ec & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_out_saturation_0_out ; + end + (32'hb0e0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_perf_wdma_write_stall_0_out ; + end + (32'hb0cc & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_0_out ; + end + (32'hb0d4 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_inf_input_num_0_out ; + end + (32'hb0d0 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_nan_input_num_0_out ; + end + (32'hb0d8 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_d_status_nan_output_num_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_offset[31:0] <= 32'h0; + cvt_scale[15:0] <= 16'b0000000000000000; + cvt_shift[5:0] <= 6'b000000; + channel[12:0] <= 13'b0000000000000; + height[12:0] <= 13'b0000000000000; + width[12:0] <= 13'b0000000000000; + out_precision[1:0] <= 2'b00; + proc_precision[1:0] <= 2'b00; + bn_alu_shift_value[5:0] <= 6'b000000; + bn_alu_src <= 1'b0; + bn_alu_operand[15:0] <= 16'b0000000000000000; + bn_alu_algo[1:0] <= 2'b00; + bn_alu_bypass <= 1'b1; + bn_bypass <= 1'b1; + bn_mul_bypass <= 1'b1; + bn_mul_prelu <= 1'b0; + bn_relu_bypass <= 1'b1; + bn_mul_shift_value[7:0] <= 8'b00000000; + bn_mul_src <= 1'b0; + bn_mul_operand[15:0] <= 16'b0000000000000000; + bs_alu_shift_value[5:0] <= 6'b000000; + bs_alu_src <= 1'b0; + bs_alu_operand[15:0] <= 16'b0000000000000000; + bs_alu_algo[1:0] <= 2'b00; + bs_alu_bypass <= 1'b1; + bs_bypass <= 1'b1; + bs_mul_bypass <= 1'b1; + bs_mul_prelu <= 1'b1; + bs_relu_bypass <= 1'b1; + bs_mul_shift_value[7:0] <= 8'b00000000; + bs_mul_src <= 1'b0; + bs_mul_operand[15:0] <= 16'b0000000000000000; + ew_alu_cvt_bypass <= 1'b1; + ew_alu_src <= 1'b0; + ew_alu_cvt_offset[31:0] <= 32'h0; + ew_alu_cvt_scale[15:0] <= 16'b0000000000000000; + ew_alu_cvt_truncate[5:0] <= 6'b000000; + ew_alu_operand[31:0] <= 32'h0; + ew_alu_algo[1:0] <= 2'b00; + ew_alu_bypass <= 1'b1; + ew_bypass <= 1'b1; + ew_lut_bypass <= 1'b1; + ew_mul_bypass <= 1'b1; + ew_mul_prelu <= 1'b0; + ew_mul_cvt_bypass <= 1'b1; + ew_mul_src <= 1'b0; + ew_mul_cvt_offset[31:0] <= 32'h0; + ew_mul_cvt_scale[15:0] <= 16'b0000000000000000; + ew_mul_cvt_truncate[5:0] <= 6'b000000; + ew_mul_operand[31:0] <= 32'h0; + ew_truncate[9:0] <= 10'b0000000000; + dst_base_addr_high[31:0] <= 32'h0; + dst_base_addr_low[31:0] <= {(32){1'b0}}; + dst_batch_stride[31:0] <= {(32){1'b0}}; + dst_ram_type <= 1'b0; + dst_line_stride[31:0] <= {(32){1'b0}}; + dst_surface_stride[31:0] <= {(32){1'b0}}; + batch_number[4:0] <= 5'b00000; + flying_mode <= 1'b0; + nan_to_zero <= 1'b0; + output_dst <= 1'b0; + winograd <= 1'b0; + perf_dma_en <= 1'b0; + perf_lut_en <= 1'b0; + perf_nan_inf_count_en <= 1'b0; + perf_sat_en <= 1'b0; + end else begin +// Register: NVDLA_SDP_D_CVT_OFFSET_0 Field: cvt_offset + if (nvdla_sdp_d_cvt_offset_0_wren) begin + cvt_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_CVT_SCALE_0 Field: cvt_scale + if (nvdla_sdp_d_cvt_scale_0_wren) begin + cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_CVT_SHIFT_0 Field: cvt_shift + if (nvdla_sdp_d_cvt_shift_0_wren) begin + cvt_shift[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_SDP_D_DATA_CUBE_CHANNEL_0 Field: channel + if (nvdla_sdp_d_data_cube_channel_0_wren) begin + channel[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_D_DATA_CUBE_HEIGHT_0 Field: height + if (nvdla_sdp_d_data_cube_height_0_wren) begin + height[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_D_DATA_CUBE_WIDTH_0 Field: width + if (nvdla_sdp_d_data_cube_width_0_wren) begin + width[12:0] <= reg_wr_data[12:0]; + end +// Register: NVDLA_SDP_D_DATA_FORMAT_0 Field: out_precision + if (nvdla_sdp_d_data_format_0_wren) begin + out_precision[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DATA_FORMAT_0 Field: proc_precision + if (nvdla_sdp_d_data_format_0_wren) begin + proc_precision[1:0] <= reg_wr_data[1:0]; + end +// Register: NVDLA_SDP_D_DP_BN_ALU_CFG_0 Field: bn_alu_shift_value + if (nvdla_sdp_d_dp_bn_alu_cfg_0_wren) begin + bn_alu_shift_value[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_SDP_D_DP_BN_ALU_CFG_0 Field: bn_alu_src + if (nvdla_sdp_d_dp_bn_alu_cfg_0_wren) begin + bn_alu_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BN_ALU_SRC_VALUE_0 Field: bn_alu_operand + if (nvdla_sdp_d_dp_bn_alu_src_value_0_wren) begin + bn_alu_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_alu_algo + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_alu_algo[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_alu_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_alu_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_bypass <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_mul_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_mul_bypass <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_mul_prelu + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_mul_prelu <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_D_DP_BN_CFG_0 Field: bn_relu_bypass + if (nvdla_sdp_d_dp_bn_cfg_0_wren) begin + bn_relu_bypass <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_D_DP_BN_MUL_CFG_0 Field: bn_mul_shift_value + if (nvdla_sdp_d_dp_bn_mul_cfg_0_wren) begin + bn_mul_shift_value[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_SDP_D_DP_BN_MUL_CFG_0 Field: bn_mul_src + if (nvdla_sdp_d_dp_bn_mul_cfg_0_wren) begin + bn_mul_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BN_MUL_SRC_VALUE_0 Field: bn_mul_operand + if (nvdla_sdp_d_dp_bn_mul_src_value_0_wren) begin + bn_mul_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_BS_ALU_CFG_0 Field: bs_alu_shift_value + if (nvdla_sdp_d_dp_bs_alu_cfg_0_wren) begin + bs_alu_shift_value[5:0] <= reg_wr_data[13:8]; + end +// Register: NVDLA_SDP_D_DP_BS_ALU_CFG_0 Field: bs_alu_src + if (nvdla_sdp_d_dp_bs_alu_cfg_0_wren) begin + bs_alu_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BS_ALU_SRC_VALUE_0 Field: bs_alu_operand + if (nvdla_sdp_d_dp_bs_alu_src_value_0_wren) begin + bs_alu_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_alu_algo + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_alu_algo[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_alu_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_alu_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_bypass <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_mul_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_mul_bypass <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_mul_prelu + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_mul_prelu <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_D_DP_BS_CFG_0 Field: bs_relu_bypass + if (nvdla_sdp_d_dp_bs_cfg_0_wren) begin + bs_relu_bypass <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_D_DP_BS_MUL_CFG_0 Field: bs_mul_shift_value + if (nvdla_sdp_d_dp_bs_mul_cfg_0_wren) begin + bs_mul_shift_value[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_SDP_D_DP_BS_MUL_CFG_0 Field: bs_mul_src + if (nvdla_sdp_d_dp_bs_mul_cfg_0_wren) begin + bs_mul_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_BS_MUL_SRC_VALUE_0 Field: bs_mul_operand + if (nvdla_sdp_d_dp_bs_mul_src_value_0_wren) begin + bs_mul_operand[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CFG_0 Field: ew_alu_cvt_bypass + if (nvdla_sdp_d_dp_ew_alu_cfg_0_wren) begin + ew_alu_cvt_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CFG_0 Field: ew_alu_src + if (nvdla_sdp_d_dp_ew_alu_cfg_0_wren) begin + ew_alu_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 Field: ew_alu_cvt_offset + if (nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_wren) begin + ew_alu_cvt_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 Field: ew_alu_cvt_scale + if (nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_wren) begin + ew_alu_cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 Field: ew_alu_cvt_truncate + if (nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_wren) begin + ew_alu_cvt_truncate[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_SDP_D_DP_EW_ALU_SRC_VALUE_0 Field: ew_alu_operand + if (nvdla_sdp_d_dp_ew_alu_src_value_0_wren) begin + ew_alu_operand[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_alu_algo + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_alu_algo[1:0] <= reg_wr_data[3:2]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_alu_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_alu_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_bypass <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_lut_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_lut_bypass <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_mul_bypass + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_mul_bypass <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_D_DP_EW_CFG_0 Field: ew_mul_prelu + if (nvdla_sdp_d_dp_ew_cfg_0_wren) begin + ew_mul_prelu <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CFG_0 Field: ew_mul_cvt_bypass + if (nvdla_sdp_d_dp_ew_mul_cfg_0_wren) begin + ew_mul_cvt_bypass <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CFG_0 Field: ew_mul_src + if (nvdla_sdp_d_dp_ew_mul_cfg_0_wren) begin + ew_mul_src <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 Field: ew_mul_cvt_offset + if (nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_wren) begin + ew_mul_cvt_offset[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 Field: ew_mul_cvt_scale + if (nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_wren) begin + ew_mul_cvt_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 Field: ew_mul_cvt_truncate + if (nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_wren) begin + ew_mul_cvt_truncate[5:0] <= reg_wr_data[5:0]; + end +// Register: NVDLA_SDP_D_DP_EW_MUL_SRC_VALUE_0 Field: ew_mul_operand + if (nvdla_sdp_d_dp_ew_mul_src_value_0_wren) begin + ew_mul_operand[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DP_EW_TRUNCATE_VALUE_0 Field: ew_truncate + if (nvdla_sdp_d_dp_ew_truncate_value_0_wren) begin + ew_truncate[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_SDP_D_DST_BASE_ADDR_HIGH_0 Field: dst_base_addr_high + if (nvdla_sdp_d_dst_base_addr_high_0_wren) begin + dst_base_addr_high[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_BASE_ADDR_LOW_0 Field: dst_base_addr_low + if (nvdla_sdp_d_dst_base_addr_low_0_wren) begin + dst_base_addr_low[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_BATCH_STRIDE_0 Field: dst_batch_stride + if (nvdla_sdp_d_dst_batch_stride_0_wren) begin + dst_batch_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_DMA_CFG_0 Field: dst_ram_type + if (nvdla_sdp_d_dst_dma_cfg_0_wren) begin + dst_ram_type <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_DST_LINE_STRIDE_0 Field: dst_line_stride + if (nvdla_sdp_d_dst_line_stride_0_wren) begin + dst_line_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_DST_SURFACE_STRIDE_0 Field: dst_surface_stride + if (nvdla_sdp_d_dst_surface_stride_0_wren) begin + dst_surface_stride[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: batch_number + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + batch_number[4:0] <= reg_wr_data[12:8]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: flying_mode + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + flying_mode <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: nan_to_zero + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + nan_to_zero <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: output_dst + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + output_dst <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_FEATURE_MODE_CFG_0 Field: winograd + if (nvdla_sdp_d_feature_mode_cfg_0_wren) begin + winograd <= reg_wr_data[2]; + end +// Not generating flops for field NVDLA_SDP_D_OP_ENABLE_0::op_en (to be implemented outside) +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_dma_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_dma_en <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_lut_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_lut_en <= reg_wr_data[1]; + end +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_nan_inf_count_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_nan_inf_count_en <= reg_wr_data[3]; + end +// Register: NVDLA_SDP_D_PERF_ENABLE_0 Field: perf_sat_en + if (nvdla_sdp_d_perf_enable_0_wren) begin + perf_sat_en <= reg_wr_data[2]; + end +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_HYBRID_0::lut_hybrid +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_LE_HIT_0::lut_le_hit +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_LO_HIT_0::lut_lo_hit +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_OFLOW_0::lut_oflow +// Not generating flops for read-only field NVDLA_SDP_D_PERF_LUT_UFLOW_0::lut_uflow +// Not generating flops for read-only field NVDLA_SDP_D_PERF_OUT_SATURATION_0::out_saturation +// Not generating flops for read-only field NVDLA_SDP_D_PERF_WDMA_WRITE_STALL_0::wdma_stall +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_0::status_unequal +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_INF_INPUT_NUM_0::status_inf_input_num +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_NAN_INPUT_NUM_0::status_nan_input_num +// Not generating flops for read-only field NVDLA_SDP_D_STATUS_NAN_OUTPUT_NUM_0::status_nan_output_num + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hb0c0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_CVT_OFFSET_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_cvt_offset_0_out, nvdla_sdp_d_cvt_offset_0_out); + (32'hb0c4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_CVT_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_cvt_scale_0_out, nvdla_sdp_d_cvt_scale_0_out); + (32'hb0c8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_CVT_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_cvt_shift_0_out, nvdla_sdp_d_cvt_shift_0_out); + (32'hb044 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_CUBE_CHANNEL_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_cube_channel_0_out, nvdla_sdp_d_data_cube_channel_0_out); + (32'hb040 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_CUBE_HEIGHT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_cube_height_0_out, nvdla_sdp_d_data_cube_height_0_out); + (32'hb03c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_CUBE_WIDTH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_cube_width_0_out, nvdla_sdp_d_data_cube_width_0_out); + (32'hb0bc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DATA_FORMAT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_data_format_0_out, nvdla_sdp_d_data_format_0_out); + (32'hb070 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_ALU_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_alu_cfg_0_out, nvdla_sdp_d_dp_bn_alu_cfg_0_out); + (32'hb074 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_ALU_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_alu_src_value_0_out, nvdla_sdp_d_dp_bn_alu_src_value_0_out); + (32'hb06c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_cfg_0_out, nvdla_sdp_d_dp_bn_cfg_0_out); + (32'hb078 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_MUL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_mul_cfg_0_out, nvdla_sdp_d_dp_bn_mul_cfg_0_out); + (32'hb07c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BN_MUL_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bn_mul_src_value_0_out, nvdla_sdp_d_dp_bn_mul_src_value_0_out); + (32'hb05c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_ALU_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_alu_cfg_0_out, nvdla_sdp_d_dp_bs_alu_cfg_0_out); + (32'hb060 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_ALU_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_alu_src_value_0_out, nvdla_sdp_d_dp_bs_alu_src_value_0_out); + (32'hb058 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_cfg_0_out, nvdla_sdp_d_dp_bs_cfg_0_out); + (32'hb064 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_MUL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_mul_cfg_0_out, nvdla_sdp_d_dp_bs_mul_cfg_0_out); + (32'hb068 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_BS_MUL_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_bs_mul_src_value_0_out, nvdla_sdp_d_dp_bs_mul_src_value_0_out); + (32'hb084 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cfg_0_out, nvdla_sdp_d_dp_ew_alu_cfg_0_out); + (32'hb08c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out, nvdla_sdp_d_dp_ew_alu_cvt_offset_value_0_out); + (32'hb090 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out, nvdla_sdp_d_dp_ew_alu_cvt_scale_value_0_out); + (32'hb094 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out, nvdla_sdp_d_dp_ew_alu_cvt_truncate_value_0_out); + (32'hb088 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_ALU_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_alu_src_value_0_out, nvdla_sdp_d_dp_ew_alu_src_value_0_out); + (32'hb080 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_cfg_0_out, nvdla_sdp_d_dp_ew_cfg_0_out); + (32'hb098 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cfg_0_out, nvdla_sdp_d_dp_ew_mul_cfg_0_out); + (32'hb0a0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out, nvdla_sdp_d_dp_ew_mul_cvt_offset_value_0_out); + (32'hb0a4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out, nvdla_sdp_d_dp_ew_mul_cvt_scale_value_0_out); + (32'hb0a8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out, nvdla_sdp_d_dp_ew_mul_cvt_truncate_value_0_out); + (32'hb09c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_MUL_SRC_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_mul_src_value_0_out, nvdla_sdp_d_dp_ew_mul_src_value_0_out); + (32'hb0ac & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DP_EW_TRUNCATE_VALUE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dp_ew_truncate_value_0_out, nvdla_sdp_d_dp_ew_truncate_value_0_out); + (32'hb04c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_BASE_ADDR_HIGH_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_base_addr_high_0_out, nvdla_sdp_d_dst_base_addr_high_0_out); + (32'hb048 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_BASE_ADDR_LOW_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_base_addr_low_0_out, nvdla_sdp_d_dst_base_addr_low_0_out); + (32'hb0b8 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_BATCH_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_batch_stride_0_out, nvdla_sdp_d_dst_batch_stride_0_out); + (32'hb0b4 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_DMA_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_dma_cfg_0_out, nvdla_sdp_d_dst_dma_cfg_0_out); + (32'hb050 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_LINE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_line_stride_0_out, nvdla_sdp_d_dst_line_stride_0_out); + (32'hb054 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_DST_SURFACE_STRIDE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_dst_surface_stride_0_out, nvdla_sdp_d_dst_surface_stride_0_out); + (32'hb0b0 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_FEATURE_MODE_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_feature_mode_cfg_0_out, nvdla_sdp_d_feature_mode_cfg_0_out); + (32'hb038 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_OP_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_op_enable_0_out, nvdla_sdp_d_op_enable_0_out); + (32'hb0dc & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_D_PERF_ENABLE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_d_perf_enable_0_out, nvdla_sdp_d_perf_enable_0_out); + (32'hb0f0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_HYBRID_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0f4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_LE_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0f8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_LO_HIT_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0e8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_OFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0e4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_LUT_UFLOW_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0ec & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_OUT_SATURATION_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0e0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_PERF_WDMA_WRITE_STALL_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0cc & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0d4 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_INF_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0d0 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_NAN_INPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + (32'hb0d8 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_D_STATUS_NAN_OUTPUT_NUM_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_REG_dual diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v new file mode 100644 index 0000000..153f147 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v @@ -0,0 +1,402 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_REG_single.v +module NV_NVDLA_SDP_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,lut_access_type + ,lut_addr + ,lut_addr_trigger + ,lut_table_id + ,lut_data_trigger + ,lut_hybrid_priority + ,lut_le_function + ,lut_oflow_priority + ,lut_uflow_priority + ,lut_le_index_offset + ,lut_le_index_select + ,lut_lo_index_select + ,lut_le_end + ,lut_le_slope_oflow_scale + ,lut_le_slope_uflow_scale + ,lut_le_slope_oflow_shift + ,lut_le_slope_uflow_shift + ,lut_le_start + ,lut_lo_end + ,lut_lo_slope_oflow_scale + ,lut_lo_slope_uflow_scale + ,lut_lo_slope_oflow_shift + ,lut_lo_slope_uflow_shift + ,lut_lo_start + ,producer + ,lut_data + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_sdp_s_lut_access_cfg_0_out; +wire [31:0] nvdla_sdp_s_lut_access_data_0_out; +wire [31:0] nvdla_sdp_s_lut_cfg_0_out; +wire [31:0] nvdla_sdp_s_lut_info_0_out; +wire [31:0] nvdla_sdp_s_lut_le_end_0_out; +wire [31:0] nvdla_sdp_s_lut_le_slope_scale_0_out; +wire [31:0] nvdla_sdp_s_lut_le_slope_shift_0_out; +wire [31:0] nvdla_sdp_s_lut_le_start_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_end_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_slope_scale_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_slope_shift_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_start_0_out; +wire [31:0] nvdla_sdp_s_pointer_0_out; +wire [31:0] nvdla_sdp_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output lut_access_type; +output [9:0] lut_addr; +output lut_addr_trigger; +output lut_table_id; +output lut_data_trigger; +output lut_hybrid_priority; +output lut_le_function; +output lut_oflow_priority; +output lut_uflow_priority; +output [7:0] lut_le_index_offset; +output [7:0] lut_le_index_select; +output [7:0] lut_lo_index_select; +output [31:0] lut_le_end; +output [15:0] lut_le_slope_oflow_scale; +output [15:0] lut_le_slope_uflow_scale; +output [4:0] lut_le_slope_oflow_shift; +output [4:0] lut_le_slope_uflow_shift; +output [31:0] lut_le_start; +output [31:0] lut_lo_end; +output [15:0] lut_lo_slope_oflow_scale; +output [15:0] lut_lo_slope_uflow_scale; +output [4:0] lut_lo_slope_oflow_shift; +output [4:0] lut_lo_slope_uflow_shift; +output [31:0] lut_lo_start; +output producer; +// Read-only register inputs +input [15:0] lut_data; +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg lut_access_type; +reg [9:0] lut_addr; +reg lut_hybrid_priority; +reg [31:0] lut_le_end; +reg lut_le_function; +reg [7:0] lut_le_index_offset; +reg [7:0] lut_le_index_select; +reg [15:0] lut_le_slope_oflow_scale; +reg [4:0] lut_le_slope_oflow_shift; +reg [15:0] lut_le_slope_uflow_scale; +reg [4:0] lut_le_slope_uflow_shift; +reg [31:0] lut_le_start; +reg [31:0] lut_lo_end; +reg [7:0] lut_lo_index_select; +reg [15:0] lut_lo_slope_oflow_scale; +reg [4:0] lut_lo_slope_oflow_shift; +reg [15:0] lut_lo_slope_uflow_scale; +reg [4:0] lut_lo_slope_uflow_shift; +reg [31:0] lut_lo_start; +reg lut_oflow_priority; +reg lut_table_id; +reg lut_uflow_priority; +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_s_lut_access_cfg_0_wren = (reg_offset_wr == (32'hb008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_access_data_0_wren = (reg_offset_wr == (32'hb00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_cfg_0_wren = (reg_offset_wr == (32'hb010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_info_0_wren = (reg_offset_wr == (32'hb014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_end_0_wren = (reg_offset_wr == (32'hb01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_slope_scale_0_wren = (reg_offset_wr == (32'hb028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_slope_shift_0_wren = (reg_offset_wr == (32'hb02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_start_0_wren = (reg_offset_wr == (32'hb018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_end_0_wren = (reg_offset_wr == (32'hb024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_slope_scale_0_wren = (reg_offset_wr == (32'hb030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_slope_shift_0_wren = (reg_offset_wr == (32'hb034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_start_0_wren = (reg_offset_wr == (32'hb020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_pointer_0_wren = (reg_offset_wr == (32'hb004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_status_0_wren = (reg_offset_wr == (32'hb000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_s_lut_access_cfg_0_out[31:0] = { 14'b0, lut_access_type, lut_table_id, 6'b0, lut_addr }; +assign nvdla_sdp_s_lut_access_data_0_out[31:0] = { 16'b0, lut_data }; +assign nvdla_sdp_s_lut_cfg_0_out[31:0] = { 25'b0, lut_hybrid_priority, lut_oflow_priority, lut_uflow_priority, 3'b0, lut_le_function }; +assign nvdla_sdp_s_lut_info_0_out[31:0] = { 8'b0, lut_lo_index_select, lut_le_index_select, lut_le_index_offset }; +assign nvdla_sdp_s_lut_le_end_0_out[31:0] = { lut_le_end }; +assign nvdla_sdp_s_lut_le_slope_scale_0_out[31:0] = { lut_le_slope_oflow_scale, lut_le_slope_uflow_scale }; +assign nvdla_sdp_s_lut_le_slope_shift_0_out[31:0] = { 22'b0, lut_le_slope_oflow_shift, lut_le_slope_uflow_shift }; +assign nvdla_sdp_s_lut_le_start_0_out[31:0] = { lut_le_start }; +assign nvdla_sdp_s_lut_lo_end_0_out[31:0] = { lut_lo_end }; +assign nvdla_sdp_s_lut_lo_slope_scale_0_out[31:0] = { lut_lo_slope_oflow_scale, lut_lo_slope_uflow_scale }; +assign nvdla_sdp_s_lut_lo_slope_shift_0_out[31:0] = { 22'b0, lut_lo_slope_oflow_shift, lut_lo_slope_uflow_shift }; +assign nvdla_sdp_s_lut_lo_start_0_out[31:0] = { lut_lo_start }; +assign nvdla_sdp_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_sdp_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign lut_addr_trigger = nvdla_sdp_s_lut_access_cfg_0_wren; //(W563) +assign lut_data_trigger = nvdla_sdp_s_lut_access_data_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_s_lut_access_cfg_0_out + or nvdla_sdp_s_lut_access_data_0_out + or nvdla_sdp_s_lut_cfg_0_out + or nvdla_sdp_s_lut_info_0_out + or nvdla_sdp_s_lut_le_end_0_out + or nvdla_sdp_s_lut_le_slope_scale_0_out + or nvdla_sdp_s_lut_le_slope_shift_0_out + or nvdla_sdp_s_lut_le_start_0_out + or nvdla_sdp_s_lut_lo_end_0_out + or nvdla_sdp_s_lut_lo_slope_scale_0_out + or nvdla_sdp_s_lut_lo_slope_shift_0_out + or nvdla_sdp_s_lut_lo_start_0_out + or nvdla_sdp_s_pointer_0_out + or nvdla_sdp_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hb008 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_access_cfg_0_out ; + end + (32'hb00c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_access_data_0_out ; + end + (32'hb010 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_cfg_0_out ; + end + (32'hb014 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_info_0_out ; + end + (32'hb01c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_end_0_out ; + end + (32'hb028 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_slope_scale_0_out ; + end + (32'hb02c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_slope_shift_0_out ; + end + (32'hb018 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_start_0_out ; + end + (32'hb024 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_end_0_out ; + end + (32'hb030 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_slope_scale_0_out ; + end + (32'hb034 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_slope_shift_0_out ; + end + (32'hb020 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_start_0_out ; + end + (32'hb004 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_pointer_0_out ; + end + (32'hb000 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_access_type <= 1'b0; + lut_addr[9:0] <= 10'b0000000000; + lut_table_id <= 1'b0; + lut_hybrid_priority <= 1'b0; + lut_le_function <= 1'b0; + lut_oflow_priority <= 1'b0; + lut_uflow_priority <= 1'b0; + lut_le_index_offset[7:0] <= 8'b00000000; + lut_le_index_select[7:0] <= 8'b00000000; + lut_lo_index_select[7:0] <= 8'b00000000; + lut_le_end[31:0] <= 32'b00000000000000000000000000000000; + lut_le_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_oflow_shift[4:0] <= 5'b00000; + lut_le_slope_uflow_shift[4:0] <= 5'b00000; + lut_le_start[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_end[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_oflow_shift[4:0] <= 5'b00000; + lut_lo_slope_uflow_shift[4:0] <= 5'b00000; + lut_lo_start[31:0] <= 32'b00000000000000000000000000000000; + producer <= 1'b0; + end else begin +// Register: NVDLA_SDP_S_LUT_ACCESS_CFG_0 Field: lut_access_type + if (nvdla_sdp_s_lut_access_cfg_0_wren) begin + lut_access_type <= reg_wr_data[17]; + end +// Register: NVDLA_SDP_S_LUT_ACCESS_CFG_0 Field: lut_addr + if (nvdla_sdp_s_lut_access_cfg_0_wren) begin + lut_addr[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_SDP_S_LUT_ACCESS_CFG_0 Field: lut_table_id + if (nvdla_sdp_s_lut_access_cfg_0_wren) begin + lut_table_id <= reg_wr_data[16]; + end +// Not generating flops for field NVDLA_SDP_S_LUT_ACCESS_DATA_0::lut_data (to be implemented outside) +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_hybrid_priority + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_hybrid_priority <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_le_function + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_le_function <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_oflow_priority + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_oflow_priority <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_uflow_priority + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_uflow_priority <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_S_LUT_INFO_0 Field: lut_le_index_offset + if (nvdla_sdp_s_lut_info_0_wren) begin + lut_le_index_offset[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_SDP_S_LUT_INFO_0 Field: lut_le_index_select + if (nvdla_sdp_s_lut_info_0_wren) begin + lut_le_index_select[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_SDP_S_LUT_INFO_0 Field: lut_lo_index_select + if (nvdla_sdp_s_lut_info_0_wren) begin + lut_lo_index_select[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_SDP_S_LUT_LE_END_0 Field: lut_le_end + if (nvdla_sdp_s_lut_le_end_0_wren) begin + lut_le_end[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_oflow_scale + if (nvdla_sdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_uflow_scale + if (nvdla_sdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_oflow_shift + if (nvdla_sdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_uflow_shift + if (nvdla_sdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_SDP_S_LUT_LE_START_0 Field: lut_le_start + if (nvdla_sdp_s_lut_le_start_0_wren) begin + lut_le_start[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_END_0 Field: lut_lo_end + if (nvdla_sdp_s_lut_lo_end_0_wren) begin + lut_lo_end[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_oflow_scale + if (nvdla_sdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_uflow_scale + if (nvdla_sdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_oflow_shift + if (nvdla_sdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_uflow_shift + if (nvdla_sdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_START_0 Field: lut_lo_start + if (nvdla_sdp_s_lut_lo_start_0_wren) begin + lut_lo_start[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_SDP_S_POINTER_0::consumer +// Register: NVDLA_SDP_S_POINTER_0 Field: producer + if (nvdla_sdp_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_SDP_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_SDP_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hb008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_ACCESS_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_access_cfg_0_out, nvdla_sdp_s_lut_access_cfg_0_out); + (32'hb00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_ACCESS_DATA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_access_data_0_out, nvdla_sdp_s_lut_access_data_0_out); + (32'hb010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_cfg_0_out, nvdla_sdp_s_lut_cfg_0_out); + (32'hb014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_INFO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_info_0_out, nvdla_sdp_s_lut_info_0_out); + (32'hb01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_END_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_end_0_out, nvdla_sdp_s_lut_le_end_0_out); + (32'hb028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_slope_scale_0_out, nvdla_sdp_s_lut_le_slope_scale_0_out); + (32'hb02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_slope_shift_0_out, nvdla_sdp_s_lut_le_slope_shift_0_out); + (32'hb018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_START_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_start_0_out, nvdla_sdp_s_lut_le_start_0_out); + (32'hb024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_END_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_end_0_out, nvdla_sdp_s_lut_lo_end_0_out); + (32'hb030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_slope_scale_0_out, nvdla_sdp_s_lut_lo_slope_scale_0_out); + (32'hb034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_slope_shift_0_out, nvdla_sdp_s_lut_lo_slope_shift_0_out); + (32'hb020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_START_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_start_0_out, nvdla_sdp_s_lut_lo_start_0_out); + (32'hb004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_pointer_0_out, nvdla_sdp_s_pointer_0_out); + (32'hb000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v.vcp new file mode 100644 index 0000000..153f147 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v.vcp @@ -0,0 +1,402 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_REG_single.v +module NV_NVDLA_SDP_REG_single ( + reg_rd_data + ,reg_offset +// verilint 498 off +// leda UNUSED_DEC off + ,reg_wr_data +// verilint 498 on +// leda UNUSED_DEC on + ,reg_wr_en + ,nvdla_core_clk + ,nvdla_core_rstn + ,lut_access_type + ,lut_addr + ,lut_addr_trigger + ,lut_table_id + ,lut_data_trigger + ,lut_hybrid_priority + ,lut_le_function + ,lut_oflow_priority + ,lut_uflow_priority + ,lut_le_index_offset + ,lut_le_index_select + ,lut_lo_index_select + ,lut_le_end + ,lut_le_slope_oflow_scale + ,lut_le_slope_uflow_scale + ,lut_le_slope_oflow_shift + ,lut_le_slope_uflow_shift + ,lut_le_start + ,lut_lo_end + ,lut_lo_slope_oflow_scale + ,lut_lo_slope_uflow_scale + ,lut_lo_slope_oflow_shift + ,lut_lo_slope_uflow_shift + ,lut_lo_start + ,producer + ,lut_data + ,consumer + ,status_0 + ,status_1 + ); +wire [31:0] nvdla_sdp_s_lut_access_cfg_0_out; +wire [31:0] nvdla_sdp_s_lut_access_data_0_out; +wire [31:0] nvdla_sdp_s_lut_cfg_0_out; +wire [31:0] nvdla_sdp_s_lut_info_0_out; +wire [31:0] nvdla_sdp_s_lut_le_end_0_out; +wire [31:0] nvdla_sdp_s_lut_le_slope_scale_0_out; +wire [31:0] nvdla_sdp_s_lut_le_slope_shift_0_out; +wire [31:0] nvdla_sdp_s_lut_le_start_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_end_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_slope_scale_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_slope_shift_0_out; +wire [31:0] nvdla_sdp_s_lut_lo_start_0_out; +wire [31:0] nvdla_sdp_s_pointer_0_out; +wire [31:0] nvdla_sdp_s_status_0_out; +wire [11:0] reg_offset_rd_int; +wire [31:0] reg_offset_wr; +// Register control interface +output [31:0] reg_rd_data; +input [11:0] reg_offset; +input [31:0] reg_wr_data; //(UNUSED_DEC) +input reg_wr_en; +input nvdla_core_clk; +input nvdla_core_rstn; +// Writable register flop/trigger outputs +output lut_access_type; +output [9:0] lut_addr; +output lut_addr_trigger; +output lut_table_id; +output lut_data_trigger; +output lut_hybrid_priority; +output lut_le_function; +output lut_oflow_priority; +output lut_uflow_priority; +output [7:0] lut_le_index_offset; +output [7:0] lut_le_index_select; +output [7:0] lut_lo_index_select; +output [31:0] lut_le_end; +output [15:0] lut_le_slope_oflow_scale; +output [15:0] lut_le_slope_uflow_scale; +output [4:0] lut_le_slope_oflow_shift; +output [4:0] lut_le_slope_uflow_shift; +output [31:0] lut_le_start; +output [31:0] lut_lo_end; +output [15:0] lut_lo_slope_oflow_scale; +output [15:0] lut_lo_slope_uflow_scale; +output [4:0] lut_lo_slope_oflow_shift; +output [4:0] lut_lo_slope_uflow_shift; +output [31:0] lut_lo_start; +output producer; +// Read-only register inputs +input [15:0] lut_data; +input consumer; +input [1:0] status_0; +input [1:0] status_1; +// wr_mask register inputs +// rstn register inputs +// leda FM_2_23 off +reg arreggen_abort_on_invalid_wr; +reg arreggen_abort_on_rowr; +reg arreggen_dump; +// leda FM_2_23 on +reg lut_access_type; +reg [9:0] lut_addr; +reg lut_hybrid_priority; +reg [31:0] lut_le_end; +reg lut_le_function; +reg [7:0] lut_le_index_offset; +reg [7:0] lut_le_index_select; +reg [15:0] lut_le_slope_oflow_scale; +reg [4:0] lut_le_slope_oflow_shift; +reg [15:0] lut_le_slope_uflow_scale; +reg [4:0] lut_le_slope_uflow_shift; +reg [31:0] lut_le_start; +reg [31:0] lut_lo_end; +reg [7:0] lut_lo_index_select; +reg [15:0] lut_lo_slope_oflow_scale; +reg [4:0] lut_lo_slope_oflow_shift; +reg [15:0] lut_lo_slope_uflow_scale; +reg [4:0] lut_lo_slope_uflow_shift; +reg [31:0] lut_lo_start; +reg lut_oflow_priority; +reg lut_table_id; +reg lut_uflow_priority; +reg producer; +reg [31:0] reg_rd_data; +assign reg_offset_wr = {20'b0 , reg_offset}; +// SCR signals +// Address decode +wire nvdla_sdp_s_lut_access_cfg_0_wren = (reg_offset_wr == (32'hb008 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_access_data_0_wren = (reg_offset_wr == (32'hb00c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_cfg_0_wren = (reg_offset_wr == (32'hb010 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_info_0_wren = (reg_offset_wr == (32'hb014 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_end_0_wren = (reg_offset_wr == (32'hb01c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_slope_scale_0_wren = (reg_offset_wr == (32'hb028 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_slope_shift_0_wren = (reg_offset_wr == (32'hb02c & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_le_start_0_wren = (reg_offset_wr == (32'hb018 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_end_0_wren = (reg_offset_wr == (32'hb024 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_slope_scale_0_wren = (reg_offset_wr == (32'hb030 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_slope_shift_0_wren = (reg_offset_wr == (32'hb034 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_lut_lo_start_0_wren = (reg_offset_wr == (32'hb020 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_pointer_0_wren = (reg_offset_wr == (32'hb004 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +wire nvdla_sdp_s_status_0_wren = (reg_offset_wr == (32'hb000 & 32'h00000fff)) & reg_wr_en ; //spyglass disable UnloadedNet-ML //(W528) +assign nvdla_sdp_s_lut_access_cfg_0_out[31:0] = { 14'b0, lut_access_type, lut_table_id, 6'b0, lut_addr }; +assign nvdla_sdp_s_lut_access_data_0_out[31:0] = { 16'b0, lut_data }; +assign nvdla_sdp_s_lut_cfg_0_out[31:0] = { 25'b0, lut_hybrid_priority, lut_oflow_priority, lut_uflow_priority, 3'b0, lut_le_function }; +assign nvdla_sdp_s_lut_info_0_out[31:0] = { 8'b0, lut_lo_index_select, lut_le_index_select, lut_le_index_offset }; +assign nvdla_sdp_s_lut_le_end_0_out[31:0] = { lut_le_end }; +assign nvdla_sdp_s_lut_le_slope_scale_0_out[31:0] = { lut_le_slope_oflow_scale, lut_le_slope_uflow_scale }; +assign nvdla_sdp_s_lut_le_slope_shift_0_out[31:0] = { 22'b0, lut_le_slope_oflow_shift, lut_le_slope_uflow_shift }; +assign nvdla_sdp_s_lut_le_start_0_out[31:0] = { lut_le_start }; +assign nvdla_sdp_s_lut_lo_end_0_out[31:0] = { lut_lo_end }; +assign nvdla_sdp_s_lut_lo_slope_scale_0_out[31:0] = { lut_lo_slope_oflow_scale, lut_lo_slope_uflow_scale }; +assign nvdla_sdp_s_lut_lo_slope_shift_0_out[31:0] = { 22'b0, lut_lo_slope_oflow_shift, lut_lo_slope_uflow_shift }; +assign nvdla_sdp_s_lut_lo_start_0_out[31:0] = { lut_lo_start }; +assign nvdla_sdp_s_pointer_0_out[31:0] = { 15'b0, consumer, 15'b0, producer }; +assign nvdla_sdp_s_status_0_out[31:0] = { 14'b0, status_1, 14'b0, status_0 }; +assign lut_addr_trigger = nvdla_sdp_s_lut_access_cfg_0_wren; //(W563) +assign lut_data_trigger = nvdla_sdp_s_lut_access_data_0_wren; //(W563) +assign reg_offset_rd_int = reg_offset; +// Output mux +//spyglass disable_block W338, W263 +always @( + reg_offset_rd_int + or nvdla_sdp_s_lut_access_cfg_0_out + or nvdla_sdp_s_lut_access_data_0_out + or nvdla_sdp_s_lut_cfg_0_out + or nvdla_sdp_s_lut_info_0_out + or nvdla_sdp_s_lut_le_end_0_out + or nvdla_sdp_s_lut_le_slope_scale_0_out + or nvdla_sdp_s_lut_le_slope_shift_0_out + or nvdla_sdp_s_lut_le_start_0_out + or nvdla_sdp_s_lut_lo_end_0_out + or nvdla_sdp_s_lut_lo_slope_scale_0_out + or nvdla_sdp_s_lut_lo_slope_shift_0_out + or nvdla_sdp_s_lut_lo_start_0_out + or nvdla_sdp_s_pointer_0_out + or nvdla_sdp_s_status_0_out + ) begin + case (reg_offset_rd_int) + (32'hb008 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_access_cfg_0_out ; + end + (32'hb00c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_access_data_0_out ; + end + (32'hb010 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_cfg_0_out ; + end + (32'hb014 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_info_0_out ; + end + (32'hb01c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_end_0_out ; + end + (32'hb028 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_slope_scale_0_out ; + end + (32'hb02c & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_slope_shift_0_out ; + end + (32'hb018 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_le_start_0_out ; + end + (32'hb024 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_end_0_out ; + end + (32'hb030 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_slope_scale_0_out ; + end + (32'hb034 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_slope_shift_0_out ; + end + (32'hb020 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_lut_lo_start_0_out ; + end + (32'hb004 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_pointer_0_out ; + end + (32'hb000 & 32'h00000fff): begin + reg_rd_data = nvdla_sdp_s_status_0_out ; + end + default: reg_rd_data = {32{1'b0}}; + endcase +end +//spyglass enable_block W338, W263 +// spyglass disable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// Register flop declarations +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_access_type <= 1'b0; + lut_addr[9:0] <= 10'b0000000000; + lut_table_id <= 1'b0; + lut_hybrid_priority <= 1'b0; + lut_le_function <= 1'b0; + lut_oflow_priority <= 1'b0; + lut_uflow_priority <= 1'b0; + lut_le_index_offset[7:0] <= 8'b00000000; + lut_le_index_select[7:0] <= 8'b00000000; + lut_lo_index_select[7:0] <= 8'b00000000; + lut_le_end[31:0] <= 32'b00000000000000000000000000000000; + lut_le_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_le_slope_oflow_shift[4:0] <= 5'b00000; + lut_le_slope_uflow_shift[4:0] <= 5'b00000; + lut_le_start[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_end[31:0] <= 32'b00000000000000000000000000000000; + lut_lo_slope_oflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_uflow_scale[15:0] <= 16'b0000000000000000; + lut_lo_slope_oflow_shift[4:0] <= 5'b00000; + lut_lo_slope_uflow_shift[4:0] <= 5'b00000; + lut_lo_start[31:0] <= 32'b00000000000000000000000000000000; + producer <= 1'b0; + end else begin +// Register: NVDLA_SDP_S_LUT_ACCESS_CFG_0 Field: lut_access_type + if (nvdla_sdp_s_lut_access_cfg_0_wren) begin + lut_access_type <= reg_wr_data[17]; + end +// Register: NVDLA_SDP_S_LUT_ACCESS_CFG_0 Field: lut_addr + if (nvdla_sdp_s_lut_access_cfg_0_wren) begin + lut_addr[9:0] <= reg_wr_data[9:0]; + end +// Register: NVDLA_SDP_S_LUT_ACCESS_CFG_0 Field: lut_table_id + if (nvdla_sdp_s_lut_access_cfg_0_wren) begin + lut_table_id <= reg_wr_data[16]; + end +// Not generating flops for field NVDLA_SDP_S_LUT_ACCESS_DATA_0::lut_data (to be implemented outside) +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_hybrid_priority + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_hybrid_priority <= reg_wr_data[6]; + end +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_le_function + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_le_function <= reg_wr_data[0]; + end +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_oflow_priority + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_oflow_priority <= reg_wr_data[5]; + end +// Register: NVDLA_SDP_S_LUT_CFG_0 Field: lut_uflow_priority + if (nvdla_sdp_s_lut_cfg_0_wren) begin + lut_uflow_priority <= reg_wr_data[4]; + end +// Register: NVDLA_SDP_S_LUT_INFO_0 Field: lut_le_index_offset + if (nvdla_sdp_s_lut_info_0_wren) begin + lut_le_index_offset[7:0] <= reg_wr_data[7:0]; + end +// Register: NVDLA_SDP_S_LUT_INFO_0 Field: lut_le_index_select + if (nvdla_sdp_s_lut_info_0_wren) begin + lut_le_index_select[7:0] <= reg_wr_data[15:8]; + end +// Register: NVDLA_SDP_S_LUT_INFO_0 Field: lut_lo_index_select + if (nvdla_sdp_s_lut_info_0_wren) begin + lut_lo_index_select[7:0] <= reg_wr_data[23:16]; + end +// Register: NVDLA_SDP_S_LUT_LE_END_0 Field: lut_le_end + if (nvdla_sdp_s_lut_le_end_0_wren) begin + lut_le_end[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_oflow_scale + if (nvdla_sdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SCALE_0 Field: lut_le_slope_uflow_scale + if (nvdla_sdp_s_lut_le_slope_scale_0_wren) begin + lut_le_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_oflow_shift + if (nvdla_sdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_SDP_S_LUT_LE_SLOPE_SHIFT_0 Field: lut_le_slope_uflow_shift + if (nvdla_sdp_s_lut_le_slope_shift_0_wren) begin + lut_le_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_SDP_S_LUT_LE_START_0 Field: lut_le_start + if (nvdla_sdp_s_lut_le_start_0_wren) begin + lut_le_start[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_END_0 Field: lut_lo_end + if (nvdla_sdp_s_lut_lo_end_0_wren) begin + lut_lo_end[31:0] <= reg_wr_data[31:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_oflow_scale + if (nvdla_sdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_oflow_scale[15:0] <= reg_wr_data[31:16]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SCALE_0 Field: lut_lo_slope_uflow_scale + if (nvdla_sdp_s_lut_lo_slope_scale_0_wren) begin + lut_lo_slope_uflow_scale[15:0] <= reg_wr_data[15:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_oflow_shift + if (nvdla_sdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_oflow_shift[4:0] <= reg_wr_data[9:5]; + end +// Register: NVDLA_SDP_S_LUT_LO_SLOPE_SHIFT_0 Field: lut_lo_slope_uflow_shift + if (nvdla_sdp_s_lut_lo_slope_shift_0_wren) begin + lut_lo_slope_uflow_shift[4:0] <= reg_wr_data[4:0]; + end +// Register: NVDLA_SDP_S_LUT_LO_START_0 Field: lut_lo_start + if (nvdla_sdp_s_lut_lo_start_0_wren) begin + lut_lo_start[31:0] <= reg_wr_data[31:0]; + end +// Not generating flops for read-only field NVDLA_SDP_S_POINTER_0::consumer +// Register: NVDLA_SDP_S_POINTER_0 Field: producer + if (nvdla_sdp_s_pointer_0_wren) begin + producer <= reg_wr_data[0]; + end +// Not generating flops for read-only field NVDLA_SDP_S_STATUS_0::status_0 +// Not generating flops for read-only field NVDLA_SDP_S_STATUS_0::status_1 + end +end +// spyglass enable_block STARC-2.10.1.6, NoConstWithXZ, W443 +// synopsys translate_off +// VCS coverage off +initial begin + arreggen_dump = $test$plusargs("arreggen_dump_wr"); + arreggen_abort_on_rowr = $test$plusargs("arreggen_abort_on_rowr"); + arreggen_abort_on_invalid_wr = $test$plusargs("arreggen_abort_on_invalid_wr"); +`ifdef VERILATOR +`else + $timeformat(-9, 2, "ns", 15); +`endif +end +always @(posedge nvdla_core_clk) begin + if (reg_wr_en) begin + case(reg_offset) + (32'hb008 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_ACCESS_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_access_cfg_0_out, nvdla_sdp_s_lut_access_cfg_0_out); + (32'hb00c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_ACCESS_DATA_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_access_data_0_out, nvdla_sdp_s_lut_access_data_0_out); + (32'hb010 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_CFG_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_cfg_0_out, nvdla_sdp_s_lut_cfg_0_out); + (32'hb014 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_INFO_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_info_0_out, nvdla_sdp_s_lut_info_0_out); + (32'hb01c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_END_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_end_0_out, nvdla_sdp_s_lut_le_end_0_out); + (32'hb028 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_slope_scale_0_out, nvdla_sdp_s_lut_le_slope_scale_0_out); + (32'hb02c & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_slope_shift_0_out, nvdla_sdp_s_lut_le_slope_shift_0_out); + (32'hb018 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LE_START_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_le_start_0_out, nvdla_sdp_s_lut_le_start_0_out); + (32'hb024 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_END_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_end_0_out, nvdla_sdp_s_lut_lo_end_0_out); + (32'hb030 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_SLOPE_SCALE_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_slope_scale_0_out, nvdla_sdp_s_lut_lo_slope_scale_0_out); + (32'hb034 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_SLOPE_SHIFT_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_slope_shift_0_out, nvdla_sdp_s_lut_lo_slope_shift_0_out); + (32'hb020 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_LUT_LO_START_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_lut_lo_start_0_out, nvdla_sdp_s_lut_lo_start_0_out); + (32'hb004 & 32'h00000fff): if (arreggen_dump) $display("%t:%m: reg wr: NVDLA_SDP_S_POINTER_0 = 0x%h (old value: 0x%h, 0x%b))", $time, reg_wr_data, nvdla_sdp_s_pointer_0_out, nvdla_sdp_s_pointer_0_out); + (32'hb000 & 32'h00000fff): begin + if (arreggen_dump) $display("%t:%m: read-only reg wr: NVDLA_SDP_S_STATUS_0 = 0x%h", $time, reg_wr_data); + if (arreggen_abort_on_rowr) begin $display("ERROR: write to read-only register!"); $finish; end + end + default: begin + if (arreggen_dump) $display("%t:%m: reg wr: Unknown register (0x%h) = 0x%h", $time, reg_offset, reg_wr_data); + if (arreggen_abort_on_invalid_wr) begin $display("ERROR: write to undefined register!"); $finish; end + end + endcase + end +end +// VCS coverage on +// synopsys translate_on +endmodule // NV_NVDLA_SDP_REG_single diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v new file mode 100644 index 0000000..e05b6b0 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v @@ -0,0 +1,517 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_DAT_in.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_DAT_in ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,cmd2dat_spt_pd //|< i + ,cmd2dat_spt_pvld //|< i + ,cmd2dat_spt_prdy //|> o + ,sdp_dp2wdma_pd //|< i + ,sdp_dp2wdma_valid //|< i + ,sdp_dp2wdma_ready //|> o + ,dfifo0_rd_prdy //|< i + ,dfifo1_rd_prdy //|< i + ,dfifo2_rd_prdy //|< i + ,dfifo3_rd_prdy //|< i + ,dfifo0_rd_pd //|> o + ,dfifo0_rd_pvld //|> o + ,dfifo1_rd_pd //|> o + ,dfifo1_rd_pvld //|> o + ,dfifo2_rd_pd //|> o + ,dfifo2_rd_pvld //|> o + ,dfifo3_rd_pd //|> o + ,dfifo3_rd_pvld //|> o + ,reg2dp_batch_number //|< i + ,reg2dp_winograd //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_out_precision //|< i + ,dp2reg_status_nan_output_num //|> o + ); +// +// NV_NVDLA_SDP_WDMA_DAT_in_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +input cmd2dat_spt_pvld; +output cmd2dat_spt_prdy; +input [14:0] cmd2dat_spt_pd; +input sdp_dp2wdma_valid; +output sdp_dp2wdma_ready; +input [8*8 -1:0] sdp_dp2wdma_pd; +output dfifo0_rd_pvld; +input dfifo0_rd_prdy; +output [8*8 -1:0] dfifo0_rd_pd; +output dfifo1_rd_pvld; +input dfifo1_rd_prdy; +output [8*8 -1:0] dfifo1_rd_pd; +output dfifo2_rd_pvld; +input dfifo2_rd_prdy; +output [8*8 -1:0] dfifo2_rd_pd; +output dfifo3_rd_pvld; +input dfifo3_rd_prdy; +output [8*8 -1:0] dfifo3_rd_pd; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_height; +input [1:0] reg2dp_out_precision; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +input reg2dp_winograd; +output [31:0] dp2reg_status_nan_output_num; +wire cfg_di_8; +wire cfg_do_16; +wire cfg_do_8; +wire cfg_do_fp16; +wire cfg_do_int16; +wire cfg_mode_1x1_pack; +wire cfg_mode_batch; +wire cfg_mode_winograd; +wire [8*8 -1:0] dp2wdma_data; +wire [8*8 -1:0] dp2wdma_data_16; +wire [8*8 -1:0] dp2wdma_data_8; +wire cmd2dat_spt_odd; +wire [13:0] cmd2dat_spt_size; +reg [13:0] spt_size; +reg spt_vld; +wire spt_rdy; +wire in_dat_accept; +wire in_dat_rdy; +wire is_last_beat; +reg [13:0] beat_count; +wire [8*8 -1:0] dfifo0_wr_pd; +wire dfifo0_wr_prdy; +wire dfifo0_wr_pvld; +wire dfifo0_wr_rdy; +wire [8*8 -1:0] dfifo1_wr_pd; +wire dfifo1_wr_prdy; +wire dfifo1_wr_pvld; +wire dfifo1_wr_rdy; +wire [8*8 -1:0] dfifo2_wr_pd; +wire dfifo2_wr_prdy; +wire dfifo2_wr_pvld; +wire dfifo2_wr_rdy; +wire [8*8 -1:0] dfifo3_wr_pd; +wire dfifo3_wr_prdy; +wire dfifo3_wr_pvld; +wire dfifo3_wr_rdy; +assign cfg_mode_batch = (reg2dp_batch_number!=0); +assign cfg_mode_winograd = reg2dp_winograd== 1'h1 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_di_8 = reg2dp_proc_precision== 0 ; +assign cfg_do_8 = reg2dp_out_precision== 0 ; +assign cfg_do_int16 = (reg2dp_out_precision== 1 ); +assign cfg_do_fp16 = (reg2dp_out_precision== 2 ); +assign cfg_do_16 = cfg_do_int16 | cfg_do_fp16; +//================================== +// DATA split and assembly +//================================== +assign dp2wdma_data = sdp_dp2wdma_pd; +assign dp2wdma_data_16 = dp2wdma_data; +assign dp2wdma_data_8 = dp2wdma_data; +assign dp2reg_status_nan_output_num = 32'h0; +assign sdp_dp2wdma_ready = in_dat_rdy; +//pop comand +assign spt_rdy = in_dat_accept & is_last_beat; +assign cmd2dat_spt_size[13:0] = cmd2dat_spt_pd[13:0]; +assign cmd2dat_spt_odd = cmd2dat_spt_pd[14]; +assign cmd2dat_spt_prdy = spt_rdy || !spt_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + spt_vld <= 1'b0; + end else begin + if ((cmd2dat_spt_prdy) == 1'b1) begin + spt_vld <= cmd2dat_spt_pvld; +//end else if ((cmd2dat_spt_prdy) == 1'b0) begin +//end else begin +// spt_vld <= 1'bx; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {14{1'b0}}; + end else begin + if (in_dat_accept) begin + if (is_last_beat) begin + beat_count <= 0; + end else begin + beat_count <= beat_count + 1; + end + end + end +end +assign is_last_beat = (beat_count==spt_size); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_spt_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + spt_size <= {14{1'b0}}; + end else begin + if ((cmd2dat_spt_pvld & cmd2dat_spt_prdy) == 1'b1) begin + spt_size <= cmd2dat_spt_size; +//end else if ((cmd2dat_spt_pvld & cmd2dat_spt_prdy) == 1'b0) begin +//end else begin +// spt_size <= 14'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_spt_pvld & cmd2dat_spt_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_spt_pvld & cmd2dat_spt_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"spt_vld should be faster than dp2wdma_valid") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (!spt_vld) && sdp_dp2wdma_valid); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign in_dat_rdy = dfifo0_wr_rdy & dfifo1_wr_rdy & dfifo2_wr_rdy & dfifo3_wr_rdy; +assign in_dat_accept = (dfifo0_wr_pvld & dfifo0_wr_prdy) | (dfifo1_wr_pvld & dfifo1_wr_prdy) | (dfifo2_wr_pvld & dfifo2_wr_prdy) | (dfifo3_wr_pvld & dfifo3_wr_prdy); +wire dfifo0_wr_en = beat_count[1:0] == 2'h0; +wire dfifo1_wr_en = beat_count[1:0] == 2'h1; +wire dfifo2_wr_en = beat_count[1:0] == 2'h2; +wire dfifo3_wr_en = beat_count[1:0] == 2'h3; +assign dfifo0_wr_pvld = sdp_dp2wdma_valid & dfifo0_wr_en; +assign dfifo0_wr_rdy = dfifo0_wr_en ? dfifo0_wr_prdy : 1'b1; +assign dfifo0_wr_pd = dp2wdma_data[8*8 -1:0]; +assign dfifo1_wr_pvld = sdp_dp2wdma_valid & dfifo1_wr_en; +assign dfifo1_wr_rdy = dfifo1_wr_en ? dfifo1_wr_prdy : 1'b1; +assign dfifo1_wr_pd = dp2wdma_data[8*8 -1:0]; +assign dfifo2_wr_pvld = sdp_dp2wdma_valid & dfifo2_wr_en; +assign dfifo2_wr_rdy = dfifo2_wr_en ? dfifo2_wr_prdy : 1'b1; +assign dfifo2_wr_pd = dp2wdma_data[8*8 -1:0]; +assign dfifo3_wr_pvld = sdp_dp2wdma_valid & dfifo3_wr_en; +assign dfifo3_wr_rdy = dfifo3_wr_en ? dfifo3_wr_prdy : 1'b1; +assign dfifo3_wr_pd = dp2wdma_data[8*8 -1:0]; +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo0 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo0_wr_prdy) + ,.dfifo_wr_pvld (dfifo0_wr_pvld) + ,.dfifo_wr_pd (dfifo0_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo0_rd_prdy) + ,.dfifo_rd_pvld (dfifo0_rd_pvld) + ,.dfifo_rd_pd (dfifo0_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo1_wr_prdy) + ,.dfifo_wr_pvld (dfifo1_wr_pvld) + ,.dfifo_wr_pd (dfifo1_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo1_rd_prdy) + ,.dfifo_rd_pvld (dfifo1_rd_pvld) + ,.dfifo_rd_pd (dfifo1_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo2 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo2_wr_prdy) + ,.dfifo_wr_pvld (dfifo2_wr_pvld) + ,.dfifo_wr_pd (dfifo2_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo2_rd_prdy) + ,.dfifo_rd_pvld (dfifo2_rd_pvld) + ,.dfifo_rd_pd (dfifo2_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo3 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo3_wr_prdy) + ,.dfifo_wr_pvld (dfifo3_wr_pvld) + ,.dfifo_wr_pd (dfifo3_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo3_rd_prdy) + ,.dfifo_rd_pvld (dfifo3_rd_pvld) + ,.dfifo_rd_pd (dfifo3_rd_pd[8*8 -1:0]) + ); +endmodule // NV_NVDLA_SDP_WDMA_DAT_in +module NV_NVDLA_SDP_WDMA_DAT_IN_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dfifo_wr_prdy + , dfifo_wr_pvld + , dfifo_wr_pd + , dfifo_rd_prdy + , dfifo_rd_pvld + , dfifo_rd_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output dfifo_wr_prdy; +input dfifo_wr_pvld; +input [8*8 -1:0] dfifo_wr_pd; +input dfifo_rd_prdy; +output dfifo_rd_pvld; +output [8*8 -1:0] dfifo_rd_pd; +//: my $dw = 8*8; +//: &eperl::pipe("-is -wid $dw -do dfifo_rd_pd -vo dfifo_rd_pvld -ri dfifo_rd_prdy -di dfifo_wr_pd -vi dfifo_wr_pvld -ro dfifo_wr_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg dfifo_wr_prdy; +reg skid_flop_dfifo_wr_prdy; +reg skid_flop_dfifo_wr_pvld; +reg [64-1:0] skid_flop_dfifo_wr_pd; +reg pipe_skid_dfifo_wr_pvld; +reg [64-1:0] pipe_skid_dfifo_wr_pd; +// Wire +wire skid_dfifo_wr_pvld; +wire [64-1:0] skid_dfifo_wr_pd; +wire skid_dfifo_wr_prdy; +wire pipe_skid_dfifo_wr_prdy; +wire dfifo_rd_pvld; +wire [64-1:0] dfifo_rd_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo_wr_prdy <= 1'b1; + skid_flop_dfifo_wr_prdy <= 1'b1; + end else begin + dfifo_wr_prdy <= skid_dfifo_wr_prdy; + skid_flop_dfifo_wr_prdy <= skid_dfifo_wr_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_dfifo_wr_pvld <= 1'b0; + end else begin + if (skid_flop_dfifo_wr_prdy) begin + skid_flop_dfifo_wr_pvld <= dfifo_wr_pvld; + end + end +end +assign skid_dfifo_wr_pvld = (skid_flop_dfifo_wr_prdy) ? dfifo_wr_pvld : skid_flop_dfifo_wr_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_dfifo_wr_prdy & dfifo_wr_pvld) begin + skid_flop_dfifo_wr_pd[64-1:0] <= dfifo_wr_pd[64-1:0]; + end +end +assign skid_dfifo_wr_pd[64-1:0] = (skid_flop_dfifo_wr_prdy) ? dfifo_wr_pd[64-1:0] : skid_flop_dfifo_wr_pd[64-1:0]; + + +// PIPE READY +assign skid_dfifo_wr_prdy = pipe_skid_dfifo_wr_prdy || !pipe_skid_dfifo_wr_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_dfifo_wr_pvld <= 1'b0; + end else begin + if (skid_dfifo_wr_prdy) begin + pipe_skid_dfifo_wr_pvld <= skid_dfifo_wr_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_dfifo_wr_prdy && skid_dfifo_wr_pvld) begin + pipe_skid_dfifo_wr_pd[64-1:0] <= skid_dfifo_wr_pd[64-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_dfifo_wr_prdy = dfifo_rd_prdy; +assign dfifo_rd_pvld = pipe_skid_dfifo_wr_pvld; +assign dfifo_rd_pd = pipe_skid_dfifo_wr_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v.vcp new file mode 100644 index 0000000..7ed0d73 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v.vcp @@ -0,0 +1,441 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_DAT_in.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_DAT_in ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,cmd2dat_spt_pd //|< i + ,cmd2dat_spt_pvld //|< i + ,cmd2dat_spt_prdy //|> o + ,sdp_dp2wdma_pd //|< i + ,sdp_dp2wdma_valid //|< i + ,sdp_dp2wdma_ready //|> o + ,dfifo0_rd_prdy //|< i + ,dfifo1_rd_prdy //|< i + ,dfifo2_rd_prdy //|< i + ,dfifo3_rd_prdy //|< i + ,dfifo0_rd_pd //|> o + ,dfifo0_rd_pvld //|> o + ,dfifo1_rd_pd //|> o + ,dfifo1_rd_pvld //|> o + ,dfifo2_rd_pd //|> o + ,dfifo2_rd_pvld //|> o + ,dfifo3_rd_pd //|> o + ,dfifo3_rd_pvld //|> o + ,reg2dp_batch_number //|< i + ,reg2dp_winograd //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_out_precision //|< i + ,dp2reg_status_nan_output_num //|> o + ); +// +// NV_NVDLA_SDP_WDMA_DAT_in_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +input cmd2dat_spt_pvld; +output cmd2dat_spt_prdy; +input [14:0] cmd2dat_spt_pd; +input sdp_dp2wdma_valid; +output sdp_dp2wdma_ready; +input [8*8 -1:0] sdp_dp2wdma_pd; +output dfifo0_rd_pvld; +input dfifo0_rd_prdy; +output [8*8 -1:0] dfifo0_rd_pd; +output dfifo1_rd_pvld; +input dfifo1_rd_prdy; +output [8*8 -1:0] dfifo1_rd_pd; +output dfifo2_rd_pvld; +input dfifo2_rd_prdy; +output [8*8 -1:0] dfifo2_rd_pd; +output dfifo3_rd_pvld; +input dfifo3_rd_prdy; +output [8*8 -1:0] dfifo3_rd_pd; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_height; +input [1:0] reg2dp_out_precision; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +input reg2dp_winograd; +output [31:0] dp2reg_status_nan_output_num; +wire cfg_di_8; +wire cfg_do_16; +wire cfg_do_8; +wire cfg_do_fp16; +wire cfg_do_int16; +wire cfg_mode_1x1_pack; +wire cfg_mode_batch; +wire cfg_mode_winograd; +wire [8*8 -1:0] dp2wdma_data; +wire [8*8 -1:0] dp2wdma_data_16; +wire [8*8 -1:0] dp2wdma_data_8; +wire cmd2dat_spt_odd; +wire [13:0] cmd2dat_spt_size; +reg [13:0] spt_size; +reg spt_vld; +wire spt_rdy; +wire in_dat_accept; +wire in_dat_rdy; +wire is_last_beat; +reg [13:0] beat_count; +wire [8*8 -1:0] dfifo0_wr_pd; +wire dfifo0_wr_prdy; +wire dfifo0_wr_pvld; +wire dfifo0_wr_rdy; +wire [8*8 -1:0] dfifo1_wr_pd; +wire dfifo1_wr_prdy; +wire dfifo1_wr_pvld; +wire dfifo1_wr_rdy; +wire [8*8 -1:0] dfifo2_wr_pd; +wire dfifo2_wr_prdy; +wire dfifo2_wr_pvld; +wire dfifo2_wr_rdy; +wire [8*8 -1:0] dfifo3_wr_pd; +wire dfifo3_wr_prdy; +wire dfifo3_wr_pvld; +wire dfifo3_wr_rdy; +assign cfg_mode_batch = (reg2dp_batch_number!=0); +assign cfg_mode_winograd = reg2dp_winograd== 1'h1 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_di_8 = reg2dp_proc_precision== 0 ; +assign cfg_do_8 = reg2dp_out_precision== 0 ; +assign cfg_do_int16 = (reg2dp_out_precision== 1 ); +assign cfg_do_fp16 = (reg2dp_out_precision== 2 ); +assign cfg_do_16 = cfg_do_int16 | cfg_do_fp16; +//================================== +// DATA split and assembly +//================================== +assign dp2wdma_data = sdp_dp2wdma_pd; +assign dp2wdma_data_16 = dp2wdma_data; +assign dp2wdma_data_8 = dp2wdma_data; +assign dp2reg_status_nan_output_num = 32'h0; +assign sdp_dp2wdma_ready = in_dat_rdy; +//pop comand +assign spt_rdy = in_dat_accept & is_last_beat; +assign cmd2dat_spt_size[13:0] = cmd2dat_spt_pd[13:0]; +assign cmd2dat_spt_odd = cmd2dat_spt_pd[14]; +assign cmd2dat_spt_prdy = spt_rdy || !spt_vld; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + spt_vld <= 1'b0; + end else begin + if ((cmd2dat_spt_prdy) == 1'b1) begin + spt_vld <= cmd2dat_spt_pvld; +//end else if ((cmd2dat_spt_prdy) == 1'b0) begin +//end else begin +// spt_vld <= 1'bx; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + beat_count <= {14{1'b0}}; + end else begin + if (in_dat_accept) begin + if (is_last_beat) begin + beat_count <= 0; + end else begin + beat_count <= beat_count + 1; + end + end + end +end +assign is_last_beat = (beat_count==spt_size); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_spt_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + spt_size <= {14{1'b0}}; + end else begin + if ((cmd2dat_spt_pvld & cmd2dat_spt_prdy) == 1'b1) begin + spt_size <= cmd2dat_spt_size; +//end else if ((cmd2dat_spt_pvld & cmd2dat_spt_prdy) == 1'b0) begin +//end else begin +// spt_size <= 14'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_spt_pvld & cmd2dat_spt_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_spt_pvld & cmd2dat_spt_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"spt_vld should be faster than dp2wdma_valid") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, (!spt_vld) && sdp_dp2wdma_valid); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign in_dat_rdy = dfifo0_wr_rdy & dfifo1_wr_rdy & dfifo2_wr_rdy & dfifo3_wr_rdy; +assign in_dat_accept = (dfifo0_wr_pvld & dfifo0_wr_prdy) | (dfifo1_wr_pvld & dfifo1_wr_prdy) | (dfifo2_wr_pvld & dfifo2_wr_prdy) | (dfifo3_wr_pvld & dfifo3_wr_prdy); +wire dfifo0_wr_en = beat_count[1:0] == 2'h0; +wire dfifo1_wr_en = beat_count[1:0] == 2'h1; +wire dfifo2_wr_en = beat_count[1:0] == 2'h2; +wire dfifo3_wr_en = beat_count[1:0] == 2'h3; +assign dfifo0_wr_pvld = sdp_dp2wdma_valid & dfifo0_wr_en; +assign dfifo0_wr_rdy = dfifo0_wr_en ? dfifo0_wr_prdy : 1'b1; +assign dfifo0_wr_pd = dp2wdma_data[8*8 -1:0]; +assign dfifo1_wr_pvld = sdp_dp2wdma_valid & dfifo1_wr_en; +assign dfifo1_wr_rdy = dfifo1_wr_en ? dfifo1_wr_prdy : 1'b1; +assign dfifo1_wr_pd = dp2wdma_data[8*8 -1:0]; +assign dfifo2_wr_pvld = sdp_dp2wdma_valid & dfifo2_wr_en; +assign dfifo2_wr_rdy = dfifo2_wr_en ? dfifo2_wr_prdy : 1'b1; +assign dfifo2_wr_pd = dp2wdma_data[8*8 -1:0]; +assign dfifo3_wr_pvld = sdp_dp2wdma_valid & dfifo3_wr_en; +assign dfifo3_wr_rdy = dfifo3_wr_en ? dfifo3_wr_prdy : 1'b1; +assign dfifo3_wr_pd = dp2wdma_data[8*8 -1:0]; +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo0 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo0_wr_prdy) + ,.dfifo_wr_pvld (dfifo0_wr_pvld) + ,.dfifo_wr_pd (dfifo0_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo0_rd_prdy) + ,.dfifo_rd_pvld (dfifo0_rd_pvld) + ,.dfifo_rd_pd (dfifo0_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo1 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo1_wr_prdy) + ,.dfifo_wr_pvld (dfifo1_wr_pvld) + ,.dfifo_wr_pd (dfifo1_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo1_rd_prdy) + ,.dfifo_rd_pvld (dfifo1_rd_pvld) + ,.dfifo_rd_pd (dfifo1_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo2 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo2_wr_prdy) + ,.dfifo_wr_pvld (dfifo2_wr_pvld) + ,.dfifo_wr_pd (dfifo2_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo2_rd_prdy) + ,.dfifo_rd_pvld (dfifo2_rd_pvld) + ,.dfifo_rd_pd (dfifo2_rd_pd[8*8 -1:0]) + ); +NV_NVDLA_SDP_WDMA_DAT_IN_dfifo u_dfifo3 ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dfifo_wr_prdy (dfifo3_wr_prdy) + ,.dfifo_wr_pvld (dfifo3_wr_pvld) + ,.dfifo_wr_pd (dfifo3_wr_pd[8*8 -1:0]) + ,.dfifo_rd_prdy (dfifo3_rd_prdy) + ,.dfifo_rd_pvld (dfifo3_rd_pvld) + ,.dfifo_rd_pd (dfifo3_rd_pd[8*8 -1:0]) + ); +endmodule // NV_NVDLA_SDP_WDMA_DAT_in +module NV_NVDLA_SDP_WDMA_DAT_IN_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dfifo_wr_prdy + , dfifo_wr_pvld + , dfifo_wr_pd + , dfifo_rd_prdy + , dfifo_rd_pvld + , dfifo_rd_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +output dfifo_wr_prdy; +input dfifo_wr_pvld; +input [8*8 -1:0] dfifo_wr_pd; +input dfifo_rd_prdy; +output dfifo_rd_pvld; +output [8*8 -1:0] dfifo_rd_pd; +//: my $dw = 8*8; +//: &eperl::pipe("-is -wid $dw -do dfifo_rd_pd -vo dfifo_rd_pvld -ri dfifo_rd_prdy -di dfifo_wr_pd -vi dfifo_wr_pvld -ro dfifo_wr_prdy"); +endmodule diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v new file mode 100644 index 0000000..3fe8e90 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v @@ -0,0 +1,655 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_DAT_out.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_WDMA_DAT_out ( + nvdla_core_clk + ,nvdla_core_rstn + ,op_load + ,cmd2dat_dma_pd + ,cmd2dat_dma_pvld + ,cmd2dat_dma_prdy + ,dma_wr_req_pd + ,dma_wr_req_vld + ,dma_wr_req_rdy + ,dfifo0_rd_pd + ,dfifo0_rd_pvld + ,dfifo1_rd_pd + ,dfifo1_rd_pvld + ,dfifo2_rd_pd + ,dfifo2_rd_pvld + ,dfifo3_rd_pd + ,dfifo3_rd_pvld + ,dfifo0_rd_prdy + ,dfifo1_rd_prdy + ,dfifo2_rd_prdy + ,dfifo3_rd_prdy + ,reg2dp_batch_number + ,reg2dp_winograd + ,reg2dp_height + ,reg2dp_width + ,reg2dp_output_dst + ,reg2dp_ew_alu_algo + ,reg2dp_ew_alu_bypass + ,reg2dp_ew_bypass + ,reg2dp_out_precision + ,reg2dp_proc_precision + ,reg2dp_interrupt_ptr + ,dp2reg_done + ,dp2reg_status_unequal + ,intr_req_ptr + ,intr_req_pvld + ); +// +// NV_NVDLA_SDP_WDMA_DAT_out_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +input dma_wr_req_rdy; +output [66 -1:0] dma_wr_req_pd; +output dma_wr_req_vld; +input cmd2dat_dma_pvld; +output cmd2dat_dma_prdy; +input [32 -3 +13 +1:0] cmd2dat_dma_pd; +input dfifo0_rd_pvld; +output dfifo0_rd_prdy; +input [8*8 -1:0] dfifo0_rd_pd; +input dfifo1_rd_pvld; +output dfifo1_rd_prdy; +input [8*8 -1:0] dfifo1_rd_pd; +input dfifo2_rd_pvld; +output dfifo2_rd_prdy; +input [8*8 -1:0] dfifo2_rd_pd; +input dfifo3_rd_pvld; +output dfifo3_rd_prdy; +input [8*8 -1:0] dfifo3_rd_pd; +input [4:0] reg2dp_batch_number; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input [12:0] reg2dp_height; +input reg2dp_interrupt_ptr; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +input reg2dp_winograd; +output dp2reg_done; +output dp2reg_status_unequal; +output intr_req_ptr; +output intr_req_pvld; +reg [32 -3 -1:0] cmd_addr; +reg cmd_cube_end; +reg cmd_en; +reg [12:0] cmd_size; +reg cmd_vld; +reg dat_en; +reg dfifo0_unequal; +reg dfifo1_unequal; +reg dfifo2_unequal; +reg dfifo3_unequal; +reg [66 -1:0] dma_wr_req_pd; +reg dp2reg_done; +wire cfg_di_int8; +wire cfg_do_int16; +wire cfg_mode_1x1_pack; +wire cfg_mode_batch; +wire cfg_mode_eql; +wire cfg_mode_pdp; +wire cfg_mode_quite; +wire cfg_mode_winog; +wire [32 -3 -1:0] cmd2dat_dma_addr; +wire cmd2dat_dma_cube_end; +wire cmd2dat_dma_odd; +wire [12:0] cmd2dat_dma_size; +wire cmd_accept; +wire cmd_rdy; +wire dat_accept; +wire [4*8*8 -1:0] dat_pd; +wire dat_rdy; +wire dat_vld; +wire [32 -1:0] dma_wr_cmd_addr; +wire [32 +13:0] dma_wr_cmd_pd; +wire dma_wr_cmd_require_ack; +wire [12:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [64 -1:0] dma_wr_dat_data; +wire [3:0] dma_wr_dat_mask; +wire [66 -2:0] dma_wr_dat_pd; +wire dma_wr_dat_vld; +wire dma_wr_rdy; +wire is_last_beat; +wire layer_done; +wire [13:0] size_of_beat; +reg [12:0] beat_count; +wire [13:0] beat_count_nxt; +reg mon_beat_count; +wire [13:0] remain_beat; +wire mon_remain_beat; +wire [2:0] dfifo_rd_size; +assign cfg_mode_batch = (reg2dp_batch_number!=0); +assign cfg_mode_winog = reg2dp_winograd== 1'h1 ; +assign cfg_mode_eql = (reg2dp_ew_bypass== 1'h0 ) + & (reg2dp_ew_alu_bypass== 1'h0 ) + & (reg2dp_ew_alu_algo== 2'h3 ); +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cfg_mode_quite = cfg_mode_eql | cfg_mode_pdp; +assign cfg_di_int8 = reg2dp_proc_precision == 0 ; +assign cfg_do_int16 = reg2dp_out_precision == 1 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +//pop command data +assign cmd2dat_dma_addr[32 -3 -1:0] = cmd2dat_dma_pd[32 -3 -1:0]; +assign cmd2dat_dma_size[12:0] = cmd2dat_dma_pd[32 -3 +13 -1:32 -3]; +assign cmd2dat_dma_odd = cmd2dat_dma_pd[32 -3 +13]; +assign cmd2dat_dma_cube_end = cmd2dat_dma_pd[32 -3 +13 +1]; +assign cmd2dat_dma_prdy = cmd_rdy || !cmd_vld; +assign cmd_rdy = dat_accept & is_last_beat; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_vld <= 1'b0; + end else begin + if ((cmd2dat_dma_prdy) == 1'b1) begin + cmd_vld <= cmd2dat_dma_pvld; +//end else if ((cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_vld <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_size <= {13{1'b0}}; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_size <= cmd2dat_dma_size; +// VCS coverage off +//end else if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_size <= 13'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_addr <= {(32 -3){1'b0}}; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_addr <= cmd2dat_dma_addr; +// VCS coverage off + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +reg cmd_odd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_odd <= 1'b0; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_odd <= cmd2dat_dma_odd; +// VCS coverage off +//end else if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_odd <= 1'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_cube_end <= 1'b0; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_cube_end <= cmd2dat_dma_cube_end; +// VCS coverage off +//end else if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_cube_end <= 1'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// Switch between CMD/DAT pkt +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end else if (dat_accept) begin + if (is_last_beat) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end + end + end +end +wire [2:0] size_of_atom = 1; +assign size_of_beat = cmd_size[12:0] + 1; +assign beat_count_nxt = beat_count + size_of_atom; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_count,beat_count} <= 14'h0; + end else begin + if (dat_accept) begin + if (is_last_beat) begin + {mon_beat_count,beat_count} <= 14'h0; + end else begin + {mon_beat_count,beat_count} <= beat_count_nxt; + end + end + end +end +assign is_last_beat = beat_count_nxt >= size_of_beat; +assign {mon_remain_beat,remain_beat} = size_of_beat - beat_count; +assign dfifo_rd_size[2:0] = is_last_beat ? remain_beat[2:0] : size_of_atom; +wire dfifo0_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h0 : beat_count[1:0] == 2'h0; +wire dfifo1_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h0 : beat_count[1:0] == 2'h1; +wire dfifo2_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h2 : beat_count[1:0] == 2'h2; +wire dfifo3_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h2 : beat_count[1:0] == 2'h3; +assign dfifo0_rd_prdy = dat_rdy & dfifo0_rd_en & ~(dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld | dfifo3_rd_en & ~dfifo3_rd_pvld); +assign dfifo1_rd_prdy = dat_rdy & dfifo1_rd_en & ~(dfifo0_rd_en & ~dfifo0_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld | dfifo3_rd_en & ~dfifo3_rd_pvld); +assign dfifo2_rd_prdy = dat_rdy & dfifo2_rd_en & ~(dfifo0_rd_en & ~dfifo0_rd_pvld | dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo3_rd_en & ~dfifo3_rd_pvld); +assign dfifo3_rd_prdy = dat_rdy & dfifo3_rd_en & ~(dfifo0_rd_en & ~dfifo0_rd_pvld | dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld); +assign dat_vld = ~(dfifo3_rd_en & ~dfifo3_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld | dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo0_rd_en & ~dfifo0_rd_pvld); +wire [4*8*8 -1:0] dat_pd_atom4 = {dfifo3_rd_pd , dfifo2_rd_pd , dfifo1_rd_pd , dfifo0_rd_pd}; +wire [4*8*8 -1:0] dat_pd_atom2 = beat_count[1:0] == 2'h2 ? {{(2*8*8){1'b0}},dfifo3_rd_pd , dfifo2_rd_pd} : {{(2*8*8){1'b0}},dfifo1_rd_pd , dfifo0_rd_pd}; +wire [4*8*8 -1:0] dat_pd_atom1 = beat_count[1:0] == 2'h3 ? {{(3*8*8){1'b0}},dfifo3_rd_pd} : beat_count[1:0] == 2'h2 ? {{(3*8*8){1'b0}},dfifo2_rd_pd} : + beat_count[1:0] == 2'h1 ? {{(3*8*8){1'b0}},dfifo1_rd_pd} : {{(3*8*8){1'b0}},dfifo0_rd_pd}; +wire [4*8*8 -1:0] dat_pd_mux = size_of_atom == 3'h4 ? dat_pd_atom4 : size_of_atom == 3'h2 ? dat_pd_atom2 : dat_pd_atom1; +assign dat_pd = dat_pd_mux & {{8*8{dma_wr_dat_mask[3]}},{8*8{dma_wr_dat_mask[2]}},{8*8{dma_wr_dat_mask[1]}},{8*8{dma_wr_dat_mask[0]}}}; +assign dat_rdy = dat_en & dma_wr_rdy; +assign dat_accept = dat_vld & dat_rdy; +assign cmd_accept = cmd_en & cmd_vld & dma_wr_rdy; +assign dma_wr_rdy = cfg_mode_quite || dma_wr_req_rdy; +//=========================== +// DMA OUTPUT +//=========================== +// packet: cmd +assign dma_wr_cmd_vld = cmd_en & cmd_vld; +assign dma_wr_cmd_addr = {cmd_addr,{3{1'b0}}}; +assign dma_wr_cmd_size = cmd_size; +assign dma_wr_cmd_require_ack = cmd_cube_end; +assign dma_wr_cmd_pd[32 -1:0] = dma_wr_cmd_addr[32 -1:0]; +assign dma_wr_cmd_pd[32 +12:32] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[32 +13] = dma_wr_cmd_require_ack ; +assign dma_wr_dat_vld = dat_en & dat_vld; +assign dma_wr_dat_mask[3:0] = dfifo_rd_size == 3'h4 ? 4'hf : dfifo_rd_size == 3'h3 ? 4'h7 : dfifo_rd_size == 3'h2 ? 4'h3 : dfifo_rd_size; +assign dma_wr_dat_data = dat_pd[64 -1:0]; +assign dma_wr_dat_pd[64 -1:0] = dma_wr_dat_data[64 -1:0]; +assign dma_wr_dat_pd[66 -2:64] = dma_wr_dat_mask[1 -1:0]; +assign dma_wr_req_vld = (dma_wr_cmd_vld | dma_wr_dat_vld) & !cfg_mode_quite; +always @( + cmd_en + or dma_wr_cmd_pd + or dma_wr_dat_pd + ) begin + dma_wr_req_pd[66 -2:0] = 0; + if (cmd_en) begin + dma_wr_req_pd[66 -2:0] = {{(66 -46 -1){1'b0}},dma_wr_cmd_pd}; + end else begin + dma_wr_req_pd[66 -2:0] = dma_wr_dat_pd; + end + dma_wr_req_pd[66 -1] = cmd_en ? 1'd0 : 1'd1 ; +end +//================================================= +// Count the Equal Bit in EQ Mode +//================================================= +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo0_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo0_unequal <= 1'b0; + end else begin + if (dfifo0_rd_pvld & dfifo0_rd_prdy) begin + dfifo0_unequal <= dfifo0_unequal | (|dfifo0_rd_pd); + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo1_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo1_unequal <= 1'b0; + end else begin + if (dfifo1_rd_pvld & dfifo1_rd_prdy) begin + dfifo1_unequal <= dfifo1_unequal | (|dfifo1_rd_pd); + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo2_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo2_unequal <= 1'b0; + end else begin + if (dfifo2_rd_pvld & dfifo2_rd_prdy) begin + dfifo2_unequal <= dfifo2_unequal | (|dfifo2_rd_pd); + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo3_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo3_unequal <= 1'b0; + end else begin + if (dfifo3_rd_pvld & dfifo3_rd_prdy) begin + dfifo3_unequal <= dfifo3_unequal | (|dfifo3_rd_pd); + end + end + end +end +assign dp2reg_status_unequal = dfifo3_unequal | dfifo2_unequal | dfifo1_unequal | dfifo0_unequal; +//=========================== +// op_done +//=========================== +assign layer_done = dat_accept & cmd_cube_end & is_last_beat; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_done <= 1'b0; + end else begin + dp2reg_done <= layer_done; + end +end +//============== +// INTR Interface +//============== +assign intr_req_ptr = reg2dp_interrupt_ptr; +assign intr_req_pvld = dat_accept & is_last_beat & cmd_cube_end; +//============== +// FUNCTION POINT +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property sdp_wdma_dout__interrupt_point0__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((intr_req_pvld) && nvdla_core_rstn) |-> (intr_req_ptr==0); + endproperty +// Cover 0 : "intr_req_ptr==0" + FUNCPOINT_sdp_wdma_dout__interrupt_point0__0_COV : cover property (sdp_wdma_dout__interrupt_point0__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property sdp_wdma_dout__interrupt_point1__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((intr_req_pvld) && nvdla_core_rstn) |-> (intr_req_ptr==1); + endproperty +// Cover 1 : "intr_req_ptr==1" + FUNCPOINT_sdp_wdma_dout__interrupt_point1__1_COV : cover property (sdp_wdma_dout__interrupt_point1__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_SDP_WDMA_DAT_out diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v.vcp new file mode 100644 index 0000000..3fe8e90 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v.vcp @@ -0,0 +1,655 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_DAT_out.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_WDMA_DAT_out ( + nvdla_core_clk + ,nvdla_core_rstn + ,op_load + ,cmd2dat_dma_pd + ,cmd2dat_dma_pvld + ,cmd2dat_dma_prdy + ,dma_wr_req_pd + ,dma_wr_req_vld + ,dma_wr_req_rdy + ,dfifo0_rd_pd + ,dfifo0_rd_pvld + ,dfifo1_rd_pd + ,dfifo1_rd_pvld + ,dfifo2_rd_pd + ,dfifo2_rd_pvld + ,dfifo3_rd_pd + ,dfifo3_rd_pvld + ,dfifo0_rd_prdy + ,dfifo1_rd_prdy + ,dfifo2_rd_prdy + ,dfifo3_rd_prdy + ,reg2dp_batch_number + ,reg2dp_winograd + ,reg2dp_height + ,reg2dp_width + ,reg2dp_output_dst + ,reg2dp_ew_alu_algo + ,reg2dp_ew_alu_bypass + ,reg2dp_ew_bypass + ,reg2dp_out_precision + ,reg2dp_proc_precision + ,reg2dp_interrupt_ptr + ,dp2reg_done + ,dp2reg_status_unequal + ,intr_req_ptr + ,intr_req_pvld + ); +// +// NV_NVDLA_SDP_WDMA_DAT_out_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input op_load; +input dma_wr_req_rdy; +output [66 -1:0] dma_wr_req_pd; +output dma_wr_req_vld; +input cmd2dat_dma_pvld; +output cmd2dat_dma_prdy; +input [32 -3 +13 +1:0] cmd2dat_dma_pd; +input dfifo0_rd_pvld; +output dfifo0_rd_prdy; +input [8*8 -1:0] dfifo0_rd_pd; +input dfifo1_rd_pvld; +output dfifo1_rd_prdy; +input [8*8 -1:0] dfifo1_rd_pd; +input dfifo2_rd_pvld; +output dfifo2_rd_prdy; +input [8*8 -1:0] dfifo2_rd_pd; +input dfifo3_rd_pvld; +output dfifo3_rd_prdy; +input [8*8 -1:0] dfifo3_rd_pd; +input [4:0] reg2dp_batch_number; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input [12:0] reg2dp_height; +input reg2dp_interrupt_ptr; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +input reg2dp_winograd; +output dp2reg_done; +output dp2reg_status_unequal; +output intr_req_ptr; +output intr_req_pvld; +reg [32 -3 -1:0] cmd_addr; +reg cmd_cube_end; +reg cmd_en; +reg [12:0] cmd_size; +reg cmd_vld; +reg dat_en; +reg dfifo0_unequal; +reg dfifo1_unequal; +reg dfifo2_unequal; +reg dfifo3_unequal; +reg [66 -1:0] dma_wr_req_pd; +reg dp2reg_done; +wire cfg_di_int8; +wire cfg_do_int16; +wire cfg_mode_1x1_pack; +wire cfg_mode_batch; +wire cfg_mode_eql; +wire cfg_mode_pdp; +wire cfg_mode_quite; +wire cfg_mode_winog; +wire [32 -3 -1:0] cmd2dat_dma_addr; +wire cmd2dat_dma_cube_end; +wire cmd2dat_dma_odd; +wire [12:0] cmd2dat_dma_size; +wire cmd_accept; +wire cmd_rdy; +wire dat_accept; +wire [4*8*8 -1:0] dat_pd; +wire dat_rdy; +wire dat_vld; +wire [32 -1:0] dma_wr_cmd_addr; +wire [32 +13:0] dma_wr_cmd_pd; +wire dma_wr_cmd_require_ack; +wire [12:0] dma_wr_cmd_size; +wire dma_wr_cmd_vld; +wire [64 -1:0] dma_wr_dat_data; +wire [3:0] dma_wr_dat_mask; +wire [66 -2:0] dma_wr_dat_pd; +wire dma_wr_dat_vld; +wire dma_wr_rdy; +wire is_last_beat; +wire layer_done; +wire [13:0] size_of_beat; +reg [12:0] beat_count; +wire [13:0] beat_count_nxt; +reg mon_beat_count; +wire [13:0] remain_beat; +wire mon_remain_beat; +wire [2:0] dfifo_rd_size; +assign cfg_mode_batch = (reg2dp_batch_number!=0); +assign cfg_mode_winog = reg2dp_winograd== 1'h1 ; +assign cfg_mode_eql = (reg2dp_ew_bypass== 1'h0 ) + & (reg2dp_ew_alu_bypass== 1'h0 ) + & (reg2dp_ew_alu_algo== 2'h3 ); +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cfg_mode_quite = cfg_mode_eql | cfg_mode_pdp; +assign cfg_di_int8 = reg2dp_proc_precision == 0 ; +assign cfg_do_int16 = reg2dp_out_precision == 1 ; +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +//pop command data +assign cmd2dat_dma_addr[32 -3 -1:0] = cmd2dat_dma_pd[32 -3 -1:0]; +assign cmd2dat_dma_size[12:0] = cmd2dat_dma_pd[32 -3 +13 -1:32 -3]; +assign cmd2dat_dma_odd = cmd2dat_dma_pd[32 -3 +13]; +assign cmd2dat_dma_cube_end = cmd2dat_dma_pd[32 -3 +13 +1]; +assign cmd2dat_dma_prdy = cmd_rdy || !cmd_vld; +assign cmd_rdy = dat_accept & is_last_beat; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_vld <= 1'b0; + end else begin + if ((cmd2dat_dma_prdy) == 1'b1) begin + cmd_vld <= cmd2dat_dma_pvld; +//end else if ((cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_vld <= 1'bx; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_size <= {13{1'b0}}; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_size <= cmd2dat_dma_size; +// VCS coverage off +//end else if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_size <= 13'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_2x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_addr <= {(32 -3){1'b0}}; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_addr <= cmd2dat_dma_addr; +// VCS coverage off + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +reg cmd_odd; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_odd <= 1'b0; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_odd <= cmd2dat_dma_odd; +// VCS coverage off +//end else if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_odd <= 1'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_cube_end <= 1'b0; + end else begin + if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b1) begin + cmd_cube_end <= cmd2dat_dma_cube_end; +// VCS coverage off +//end else if ((cmd2dat_dma_pvld & cmd2dat_dma_prdy) == 1'b0) begin +//end else begin +// cmd_cube_end <= 1'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(cmd2dat_dma_pvld & cmd2dat_dma_prdy))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// Switch between CMD/DAT pkt +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end else begin + if (cmd_accept) begin + cmd_en <= 1'b0; + dat_en <= 1'b1; + end else if (dat_accept) begin + if (is_last_beat) begin + cmd_en <= 1'b1; + dat_en <= 1'b0; + end + end + end +end +wire [2:0] size_of_atom = 1; +assign size_of_beat = cmd_size[12:0] + 1; +assign beat_count_nxt = beat_count + size_of_atom; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_beat_count,beat_count} <= 14'h0; + end else begin + if (dat_accept) begin + if (is_last_beat) begin + {mon_beat_count,beat_count} <= 14'h0; + end else begin + {mon_beat_count,beat_count} <= beat_count_nxt; + end + end + end +end +assign is_last_beat = beat_count_nxt >= size_of_beat; +assign {mon_remain_beat,remain_beat} = size_of_beat - beat_count; +assign dfifo_rd_size[2:0] = is_last_beat ? remain_beat[2:0] : size_of_atom; +wire dfifo0_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h0 : beat_count[1:0] == 2'h0; +wire dfifo1_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h0 : beat_count[1:0] == 2'h1; +wire dfifo2_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h2 : beat_count[1:0] == 2'h2; +wire dfifo3_rd_en = dfifo_rd_size == 3'h4 ? beat_count[1:0] == 2'h0 : dfifo_rd_size == 3'h2 ? beat_count[1:0] == 2'h2 : beat_count[1:0] == 2'h3; +assign dfifo0_rd_prdy = dat_rdy & dfifo0_rd_en & ~(dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld | dfifo3_rd_en & ~dfifo3_rd_pvld); +assign dfifo1_rd_prdy = dat_rdy & dfifo1_rd_en & ~(dfifo0_rd_en & ~dfifo0_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld | dfifo3_rd_en & ~dfifo3_rd_pvld); +assign dfifo2_rd_prdy = dat_rdy & dfifo2_rd_en & ~(dfifo0_rd_en & ~dfifo0_rd_pvld | dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo3_rd_en & ~dfifo3_rd_pvld); +assign dfifo3_rd_prdy = dat_rdy & dfifo3_rd_en & ~(dfifo0_rd_en & ~dfifo0_rd_pvld | dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld); +assign dat_vld = ~(dfifo3_rd_en & ~dfifo3_rd_pvld | dfifo2_rd_en & ~dfifo2_rd_pvld | dfifo1_rd_en & ~dfifo1_rd_pvld | dfifo0_rd_en & ~dfifo0_rd_pvld); +wire [4*8*8 -1:0] dat_pd_atom4 = {dfifo3_rd_pd , dfifo2_rd_pd , dfifo1_rd_pd , dfifo0_rd_pd}; +wire [4*8*8 -1:0] dat_pd_atom2 = beat_count[1:0] == 2'h2 ? {{(2*8*8){1'b0}},dfifo3_rd_pd , dfifo2_rd_pd} : {{(2*8*8){1'b0}},dfifo1_rd_pd , dfifo0_rd_pd}; +wire [4*8*8 -1:0] dat_pd_atom1 = beat_count[1:0] == 2'h3 ? {{(3*8*8){1'b0}},dfifo3_rd_pd} : beat_count[1:0] == 2'h2 ? {{(3*8*8){1'b0}},dfifo2_rd_pd} : + beat_count[1:0] == 2'h1 ? {{(3*8*8){1'b0}},dfifo1_rd_pd} : {{(3*8*8){1'b0}},dfifo0_rd_pd}; +wire [4*8*8 -1:0] dat_pd_mux = size_of_atom == 3'h4 ? dat_pd_atom4 : size_of_atom == 3'h2 ? dat_pd_atom2 : dat_pd_atom1; +assign dat_pd = dat_pd_mux & {{8*8{dma_wr_dat_mask[3]}},{8*8{dma_wr_dat_mask[2]}},{8*8{dma_wr_dat_mask[1]}},{8*8{dma_wr_dat_mask[0]}}}; +assign dat_rdy = dat_en & dma_wr_rdy; +assign dat_accept = dat_vld & dat_rdy; +assign cmd_accept = cmd_en & cmd_vld & dma_wr_rdy; +assign dma_wr_rdy = cfg_mode_quite || dma_wr_req_rdy; +//=========================== +// DMA OUTPUT +//=========================== +// packet: cmd +assign dma_wr_cmd_vld = cmd_en & cmd_vld; +assign dma_wr_cmd_addr = {cmd_addr,{3{1'b0}}}; +assign dma_wr_cmd_size = cmd_size; +assign dma_wr_cmd_require_ack = cmd_cube_end; +assign dma_wr_cmd_pd[32 -1:0] = dma_wr_cmd_addr[32 -1:0]; +assign dma_wr_cmd_pd[32 +12:32] = dma_wr_cmd_size[12:0]; +assign dma_wr_cmd_pd[32 +13] = dma_wr_cmd_require_ack ; +assign dma_wr_dat_vld = dat_en & dat_vld; +assign dma_wr_dat_mask[3:0] = dfifo_rd_size == 3'h4 ? 4'hf : dfifo_rd_size == 3'h3 ? 4'h7 : dfifo_rd_size == 3'h2 ? 4'h3 : dfifo_rd_size; +assign dma_wr_dat_data = dat_pd[64 -1:0]; +assign dma_wr_dat_pd[64 -1:0] = dma_wr_dat_data[64 -1:0]; +assign dma_wr_dat_pd[66 -2:64] = dma_wr_dat_mask[1 -1:0]; +assign dma_wr_req_vld = (dma_wr_cmd_vld | dma_wr_dat_vld) & !cfg_mode_quite; +always @( + cmd_en + or dma_wr_cmd_pd + or dma_wr_dat_pd + ) begin + dma_wr_req_pd[66 -2:0] = 0; + if (cmd_en) begin + dma_wr_req_pd[66 -2:0] = {{(66 -46 -1){1'b0}},dma_wr_cmd_pd}; + end else begin + dma_wr_req_pd[66 -2:0] = dma_wr_dat_pd; + end + dma_wr_req_pd[66 -1] = cmd_en ? 1'd0 : 1'd1 ; +end +//================================================= +// Count the Equal Bit in EQ Mode +//================================================= +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo0_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo0_unequal <= 1'b0; + end else begin + if (dfifo0_rd_pvld & dfifo0_rd_prdy) begin + dfifo0_unequal <= dfifo0_unequal | (|dfifo0_rd_pd); + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo1_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo1_unequal <= 1'b0; + end else begin + if (dfifo1_rd_pvld & dfifo1_rd_prdy) begin + dfifo1_unequal <= dfifo1_unequal | (|dfifo1_rd_pd); + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo2_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo2_unequal <= 1'b0; + end else begin + if (dfifo2_rd_pvld & dfifo2_rd_prdy) begin + dfifo2_unequal <= dfifo2_unequal | (|dfifo2_rd_pd); + end + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dfifo3_unequal <= 1'b0; + end else begin + if (op_load) begin + dfifo3_unequal <= 1'b0; + end else begin + if (dfifo3_rd_pvld & dfifo3_rd_prdy) begin + dfifo3_unequal <= dfifo3_unequal | (|dfifo3_rd_pd); + end + end + end +end +assign dp2reg_status_unequal = dfifo3_unequal | dfifo2_unequal | dfifo1_unequal | dfifo0_unequal; +//=========================== +// op_done +//=========================== +assign layer_done = dat_accept & cmd_cube_end & is_last_beat; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_done <= 1'b0; + end else begin + dp2reg_done <= layer_done; + end +end +//============== +// INTR Interface +//============== +assign intr_req_ptr = reg2dp_interrupt_ptr; +assign intr_req_pvld = dat_accept & is_last_beat & cmd_cube_end; +//============== +// FUNCTION POINT +//============== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property sdp_wdma_dout__interrupt_point0__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((intr_req_pvld) && nvdla_core_rstn) |-> (intr_req_ptr==0); + endproperty +// Cover 0 : "intr_req_ptr==0" + FUNCPOINT_sdp_wdma_dout__interrupt_point0__0_COV : cover property (sdp_wdma_dout__interrupt_point0__0_cov); + `endif +`endif +//VCS coverage on +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + property sdp_wdma_dout__interrupt_point1__1_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((intr_req_pvld) && nvdla_core_rstn) |-> (intr_req_ptr==1); + endproperty +// Cover 1 : "intr_req_ptr==1" + FUNCPOINT_sdp_wdma_dout__interrupt_point1__1_COV : cover property (sdp_wdma_dout__interrupt_point1__1_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_SDP_WDMA_DAT_out diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_cmd.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_cmd.v new file mode 100644 index 0000000..5b2be4a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_cmd.v @@ -0,0 +1,1512 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_cmd.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_cmd ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,cmd2dat_dma_pd //|> o + ,cmd2dat_dma_pvld //|> o + ,cmd2dat_dma_prdy //|< i + ,cmd2dat_spt_pd //|> o + ,cmd2dat_spt_pvld //|> o + ,cmd2dat_spt_prdy //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_winograd //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_batch_stride //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_surface_stride //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ); +// +// NV_NVDLA_SDP_WDMA_cmd_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +output cmd2dat_spt_pvld; +input cmd2dat_spt_prdy; +output [14:0] cmd2dat_spt_pd; +output cmd2dat_dma_pvld; +input cmd2dat_dma_prdy; +output [32 -3 +13 +1:0] cmd2dat_dma_pd; +input [4:0] reg2dp_batch_number; +input reg2dp_winograd; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input reg2dp_output_dst; +input [1:0] reg2dp_out_precision; +input [1:0] reg2dp_proc_precision; +input [31:0] reg2dp_dst_base_addr_high; +input [31-3:0] reg2dp_dst_base_addr_low; +input [31-3:0] reg2dp_dst_batch_stride; +input [31-3:0] reg2dp_dst_line_stride; +input [31-3:0] reg2dp_dst_surface_stride; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +reg [32 -3 -1:0] base_addr_line; +reg [32 -3 -1:0] base_addr_surf; +reg [32 -3 -1:0] base_addr_width; +reg mon_base_addr_line_c; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +wire cfg_addr_en; +wire cfg_di_int16; +wire cfg_di_int8; +wire cfg_do_int16; +wire cfg_do_int8; +wire cfg_mode_8to16; +wire cfg_mode_1x1_nbatch; +wire cfg_mode_batch; +wire [31-3:0] cfg_dst_batch_stride; +wire cfg_mode_winog; +wire [32 -3 -1:0] cfg_dst_addr; +wire [31-3:0] cfg_dst_line_stride; +wire [31-3:0] cfg_dst_surf_stride; +wire cfg_mode_1x1_pack; +wire cfg_mode_eql; +wire cfg_mode_norml; +wire cfg_mode_pdp; +wire cfg_mode_quite; +reg [13-3:0] count_c; +reg [12:0] count_h; +reg [13:0] count_w; +reg [13-3:0] size_of_surf; +wire [12:0] size_of_height; +reg [13:0] size_of_width; +wire is_cube_end; +wire is_elem_end; +wire is_last_e; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +wire is_last_wg; +wire is_winog_end; +wire is_last_batch; +wire cmd_accept; +reg cmd_vld; +wire cmd_rdy; +wire [32 -3 +13 +1:0] dma_fifo_pd; +wire dma_fifo_prdy; +wire dma_fifo_pvld; +reg [32 -3 -1:0] dma_addr; +reg [12:0] dma_size; +reg [13:0] spt_size; +wire [13-3:0] mode_1x1_dma_size; +wire [13-3:0] mode_1x1_spt_size; +wire is_ftrans; +wire is_ltrans; +wire [12:0] mode_norml_dma_size; +wire [13:0] mode_norml_spt_size; +wire [14:0] spt_fifo_pd; +wire spt_fifo_prdy; +wire spt_fifo_pvld; +////////cfg reg//////////// +assign cfg_dst_addr = reg2dp_dst_base_addr_low; +assign cfg_dst_surf_stride = {reg2dp_dst_surface_stride}; +assign cfg_dst_line_stride = {reg2dp_dst_line_stride}; +assign cfg_mode_batch = 1'b0; +assign cfg_mode_winog = 1'b0 ; +assign cfg_di_int8 = reg2dp_proc_precision == 0 ; +assign cfg_di_int16 = reg2dp_proc_precision == 1 ; +assign cfg_do_int8 = reg2dp_out_precision == 0 ; +assign cfg_do_int16 = reg2dp_out_precision == 1 ; +assign cfg_mode_8to16 = 1'b0; +assign cfg_mode_norml = !(cfg_mode_batch | cfg_mode_winog | cfg_mode_8to16); +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_mode_1x1_nbatch = cfg_mode_1x1_pack & !cfg_mode_batch ; +assign cfg_mode_eql = (reg2dp_ew_bypass== 1'h0 ) + & (reg2dp_ew_alu_bypass== 1'h0 ) + & (reg2dp_ew_alu_algo== 2'h3 ); +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cfg_mode_quite = cfg_mode_eql | cfg_mode_pdp; +assign cfg_addr_en = !cfg_mode_quite; +//============== +// Surf is always in unit of ATOMIC (1x1x32B) +always @( + cfg_di_int8 + or reg2dp_channel + or cfg_di_int16 + ) begin + if (cfg_di_int8) begin + size_of_surf = {1'b0,reg2dp_channel[12:3]}; + end else if (cfg_di_int16) begin + size_of_surf = reg2dp_channel[12:3 -1]; + end else begin + size_of_surf = reg2dp_channel[12:3 -1]; + end +end +//================================================= +// Cube Shape +//================================================= +assign is_winog_end = is_last_wg; +assign is_elem_end = cfg_mode_1x1_nbatch | is_last_e; +assign is_line_end = cfg_mode_1x1_nbatch | cfg_mode_norml | (is_last_batch & is_elem_end & is_last_w & is_winog_end); +assign is_surf_end = cfg_mode_1x1_nbatch | is_line_end & is_last_h; +assign is_cube_end = cfg_mode_1x1_nbatch | is_surf_end & is_last_c; +//============== +// Width Count; +//============== +// Norml Mode +wire [2:0] beg_addr_offset = base_addr_line[2:0]; +wire is_beg_addr_odd = beg_addr_offset[0]==1'b1; +wire [3:0] end_addr_offset = beg_addr_offset + reg2dp_width[2:0]; +wire is_end_addr_odd = end_addr_offset[0]==1'b0; +wire odd = ((is_ftrans & is_beg_addr_odd) || (is_ltrans && is_end_addr_odd)); +//================================ +// SIZE of Trans +//================================ +assign is_last_wg = 1'b1; +always @( + reg2dp_width + ) begin + size_of_width = {1'b0, reg2dp_width}; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {14{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_line_end) begin + count_w <= 0; + end else if (is_last_batch & is_winog_end) begin + count_w <= count_w + 1'b1; + end + end + end +end +assign is_ltrans = (count_w==size_of_width); +assign is_ftrans = (count_w==0); +assign is_last_w = is_ltrans; +assign is_last_e = 1'b1; +//============== +// HEIGHT Count: +//============== +assign size_of_height = reg2dp_height; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_last_batch) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end + end +end +assign is_last_h = count_h==size_of_height; +//============== +// CHANNEL Count +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {9{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_last_batch) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1; + end + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +assign is_last_batch = 1'b1; +//========================================== +// DMA Req : ADDR PREPARE +//========================================== +// WIDTH +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_base_addr_width_c,base_addr_width} <= {(32 -3 +1){1'b0}}; + end else begin + if (cfg_addr_en) begin + if (op_load) begin + {mon_base_addr_width_c,base_addr_width} <= {1'b0,cfg_dst_addr}; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_surf + cfg_dst_surf_stride; + end else if (is_line_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_line + cfg_dst_line_stride; + end + end + end + end + end +end +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_base_addr_line_c,base_addr_line} <= {(32 -3 +1){1'b0}}; + end else begin + if (cfg_addr_en) begin + if (op_load) begin + {mon_base_addr_line_c,base_addr_line} <= {1'b0,cfg_dst_addr}; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + cfg_dst_surf_stride; + end else if (is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + cfg_dst_line_stride; + end + end + end + end + end +end +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_base_addr_surf_c,base_addr_surf} <= {(32 -3 +1){1'b0}}; + end else begin + if (cfg_addr_en) begin + if (op_load) begin + {mon_base_addr_surf_c,base_addr_surf} <= {1'b0,cfg_dst_addr}; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + cfg_dst_surf_stride; + end + end + end + end + end +end +//========================================== +// DMA Req : SIZE +//========================================== +always @( + base_addr_line + ) begin + begin + dma_addr = base_addr_line; + end +end +//======================== +// Output: one for data write spt_; and one for data read dma_ +//======================== +// spt_size is to tell how many data from dp2wdma for a corresponding DMA req to MC/CF if +// spt_size is in unit of cycle on dp2wdma +assign mode_1x1_spt_size = (cfg_do_int8 | cfg_di_int8) ? {1'b0,reg2dp_channel[12:3]} : reg2dp_channel[12:3 -1]; +assign mode_norml_spt_size[13:0] = {1'b0,reg2dp_width}; +always @( + cfg_mode_1x1_nbatch + or mode_1x1_spt_size + or mode_norml_spt_size + ) begin + if (cfg_mode_1x1_nbatch) + spt_size = {{3{1'b0}}, mode_1x1_spt_size}; + else + spt_size = mode_norml_spt_size; +end +//======================== +// Output: one for data write spt_; and one for data read dma_ +//======================== +assign mode_1x1_dma_size = size_of_surf; +assign mode_norml_dma_size = reg2dp_width; +always @( + cfg_mode_1x1_nbatch + or mode_1x1_dma_size + or mode_norml_dma_size + ) begin + if (cfg_mode_1x1_nbatch) + dma_size = {{3 -1{1'b0}}, mode_1x1_dma_size}; + else + dma_size = mode_norml_dma_size; +end +//================================================= +// OUTPUT FIFO: SPT & DMA channel +//================================================= +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_vld <= 1'b0; + end else begin + if (op_load) begin + cmd_vld <= 1'b1; + end else if (cmd_accept) begin + if (is_cube_end) begin + cmd_vld <= 1'b0; + end + end + end +end +assign spt_fifo_pvld = cmd_vld & dma_fifo_prdy; +assign dma_fifo_pvld = cmd_vld & spt_fifo_prdy; +assign cmd_rdy = dma_fifo_prdy & spt_fifo_prdy; +assign cmd_accept = cmd_vld & cmd_rdy; +assign spt_fifo_pd[13:0] = spt_size[13:0]; +assign spt_fifo_pd[14] = odd ; +assign dma_fifo_pd[32 -3 -1:0] = dma_addr[32 -3 -1:0]; +assign dma_fifo_pd[32 -3 +13 -1:32 -3] = dma_size[12:0]; +assign dma_fifo_pd[32 -3 +13] = odd ; +assign dma_fifo_pd[32 -3 +13 +1] = is_cube_end ; +NV_NVDLA_SDP_WDMA_CMD_sfifo u_sfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.spt_fifo_prdy (spt_fifo_prdy) + ,.spt_fifo_pvld (spt_fifo_pvld) + ,.spt_fifo_pd (spt_fifo_pd[14:0]) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +NV_NVDLA_SDP_WDMA_CMD_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dma_fifo_prdy (dma_fifo_prdy) + ,.dma_fifo_pvld (dma_fifo_pvld) + ,.dma_fifo_pd (dma_fifo_pd[32 -3 +13 +1:0]) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP_WDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_width_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP_WDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP_WDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//======================== +// FUNCTION POINT +//======================== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property sdp_wdma_cmd__odd_address__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cmd_vld) && nvdla_core_rstn) |-> (odd); + endproperty +// Cover 0 : "odd" + FUNCPOINT_sdp_wdma_cmd__odd_address__0_COV : cover property (sdp_wdma_cmd__odd_address__0_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_SDP_WDMA_cmd +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_CMD_sfifo ( + nvdla_core_clk + , nvdla_core_rstn + , spt_fifo_prdy + , spt_fifo_pvld + , spt_fifo_pd + , cmd2dat_spt_prdy + , cmd2dat_spt_pvld + , cmd2dat_spt_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output spt_fifo_prdy; +input spt_fifo_pvld; +input [14:0] spt_fifo_pd; +input cmd2dat_spt_prdy; +output cmd2dat_spt_pvld; +output [14:0] cmd2dat_spt_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg spt_fifo_busy_int; // copy for internal use +assign spt_fifo_prdy = !spt_fifo_busy_int; +assign wr_reserving = spt_fifo_pvld && !spt_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] spt_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? spt_fifo_count : (spt_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (spt_fifo_count + 1'd1) : spt_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire spt_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check spt_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_busy_int <= 1'b0; + spt_fifo_count <= 3'd0; + end else begin + spt_fifo_busy_int <= spt_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + spt_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + spt_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as spt_fifo_pvld +// +// RAM +// +reg [1:0] spt_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + spt_fifo_adr <= spt_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_spt_adr; // read address this cycle +wire ram_we = wr_pushing && (spt_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [14:0] cmd2dat_spt_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( spt_fifo_pd ) + , .we ( ram_we ) + , .wa ( spt_fifo_adr ) + , .ra ( (spt_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_spt_adr} ) + , .dout ( cmd2dat_spt_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_spt_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_spt_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_spt_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_spt_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_spt_pvld && cmd2dat_spt_prdy; +reg [2:0] cmd2dat_spt_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_spt_count : + (cmd2dat_spt_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_spt_count + 1'd1) : + cmd2dat_spt_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_spt_pvld = cmd2dat_spt_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_spt_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_spt_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (spt_fifo_pvld && !spt_fifo_busy_int) || (spt_fifo_busy_int != spt_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_spt_pvld && cmd2dat_spt_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, spt_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_WDMA_CMD_sfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_WDMA_CMD_sfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [14:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [14:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [14:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [14:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [14:0] ram_ff0; +reg [14:0] ram_ff1; +reg [14:0] ram_ff2; +reg [14:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [14:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {15{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [14:0] Di0; +input [1:0] Ra0; +output [14:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 15'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [14:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [14:0] Q0 = mem[0]; +wire [14:0] Q1 = mem[1]; +wire [14:0] Q2 = mem[2]; +wire [14:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15] } +endmodule // vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +//vmw: Memory vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +//vmw: Address-size 2 +//vmw: Data-size 15 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[14:0] data0[14:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[14:0] data1[14:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_CMD_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dma_fifo_prdy + , dma_fifo_pvld + , dma_fifo_pd + , cmd2dat_dma_prdy + , cmd2dat_dma_pvld + , cmd2dat_dma_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dma_fifo_prdy; +input dma_fifo_pvld; +input [43:0] dma_fifo_pd; +input cmd2dat_dma_prdy; +output cmd2dat_dma_pvld; +output [43:0] cmd2dat_dma_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dma_fifo_busy_int; // copy for internal use +assign dma_fifo_prdy = !dma_fifo_busy_int; +assign wr_reserving = dma_fifo_pvld && !dma_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dma_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dma_fifo_count : (dma_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dma_fifo_count + 1'd1) : dma_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dma_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dma_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_busy_int <= 1'b0; + dma_fifo_count <= 3'd0; + end else begin + dma_fifo_busy_int <= dma_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dma_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dma_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dma_fifo_pvld +// +// RAM +// +reg [1:0] dma_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dma_fifo_adr <= dma_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_dma_adr; // read address this cycle +wire ram_we = wr_pushing && (dma_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [43:0] cmd2dat_dma_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dma_fifo_pd ) + , .we ( ram_we ) + , .wa ( dma_fifo_adr ) + , .ra ( (dma_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_dma_adr} ) + , .dout ( cmd2dat_dma_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_dma_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_dma_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_dma_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_dma_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_dma_pvld && cmd2dat_dma_prdy; +reg [2:0] cmd2dat_dma_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_dma_count : + (cmd2dat_dma_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_dma_count + 1'd1) : + cmd2dat_dma_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_dma_pvld = cmd2dat_dma_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_dma_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_dma_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dma_fifo_pvld && !dma_fifo_busy_int) || (dma_fifo_busy_int != dma_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_dma_pvld && cmd2dat_dma_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dma_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_WDMA_CMD_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_WDMA_CMD_dfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [43:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [43:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [43:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [43:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [43:0] ram_ff0; +reg [43:0] ram_ff1; +reg [43:0] ram_ff2; +reg [43:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [43:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {44{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [43:0] Di0; +input [1:0] Ra0; +output [43:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 44'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [43:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [43:0] Q0 = mem[0]; +wire [43:0] Q1 = mem[1]; +wire [43:0] Q2 = mem[2]; +wire [43:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44] } +endmodule // vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +//vmw: Memory vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +//vmw: Address-size 2 +//vmw: Data-size 44 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[43:0] data0[43:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[43:0] data1[43:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_cmd.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_cmd.v.vcp new file mode 100644 index 0000000..5b2be4a --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_cmd.v.vcp @@ -0,0 +1,1512 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_cmd.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_cmd ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,op_load //|< i + ,cmd2dat_dma_pd //|> o + ,cmd2dat_dma_pvld //|> o + ,cmd2dat_dma_prdy //|< i + ,cmd2dat_spt_pd //|> o + ,cmd2dat_spt_pvld //|> o + ,cmd2dat_spt_prdy //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_winograd //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_batch_stride //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_surface_stride //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ); +// +// NV_NVDLA_SDP_WDMA_cmd_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input op_load; +output cmd2dat_spt_pvld; +input cmd2dat_spt_prdy; +output [14:0] cmd2dat_spt_pd; +output cmd2dat_dma_pvld; +input cmd2dat_dma_prdy; +output [32 -3 +13 +1:0] cmd2dat_dma_pd; +input [4:0] reg2dp_batch_number; +input reg2dp_winograd; +input [12:0] reg2dp_channel; +input [12:0] reg2dp_height; +input [12:0] reg2dp_width; +input reg2dp_output_dst; +input [1:0] reg2dp_out_precision; +input [1:0] reg2dp_proc_precision; +input [31:0] reg2dp_dst_base_addr_high; +input [31-3:0] reg2dp_dst_base_addr_low; +input [31-3:0] reg2dp_dst_batch_stride; +input [31-3:0] reg2dp_dst_line_stride; +input [31-3:0] reg2dp_dst_surface_stride; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +reg [32 -3 -1:0] base_addr_line; +reg [32 -3 -1:0] base_addr_surf; +reg [32 -3 -1:0] base_addr_width; +reg mon_base_addr_line_c; +reg mon_base_addr_surf_c; +reg mon_base_addr_width_c; +wire cfg_addr_en; +wire cfg_di_int16; +wire cfg_di_int8; +wire cfg_do_int16; +wire cfg_do_int8; +wire cfg_mode_8to16; +wire cfg_mode_1x1_nbatch; +wire cfg_mode_batch; +wire [31-3:0] cfg_dst_batch_stride; +wire cfg_mode_winog; +wire [32 -3 -1:0] cfg_dst_addr; +wire [31-3:0] cfg_dst_line_stride; +wire [31-3:0] cfg_dst_surf_stride; +wire cfg_mode_1x1_pack; +wire cfg_mode_eql; +wire cfg_mode_norml; +wire cfg_mode_pdp; +wire cfg_mode_quite; +reg [13-3:0] count_c; +reg [12:0] count_h; +reg [13:0] count_w; +reg [13-3:0] size_of_surf; +wire [12:0] size_of_height; +reg [13:0] size_of_width; +wire is_cube_end; +wire is_elem_end; +wire is_last_e; +wire is_last_c; +wire is_last_h; +wire is_last_w; +wire is_line_end; +wire is_surf_end; +wire is_last_wg; +wire is_winog_end; +wire is_last_batch; +wire cmd_accept; +reg cmd_vld; +wire cmd_rdy; +wire [32 -3 +13 +1:0] dma_fifo_pd; +wire dma_fifo_prdy; +wire dma_fifo_pvld; +reg [32 -3 -1:0] dma_addr; +reg [12:0] dma_size; +reg [13:0] spt_size; +wire [13-3:0] mode_1x1_dma_size; +wire [13-3:0] mode_1x1_spt_size; +wire is_ftrans; +wire is_ltrans; +wire [12:0] mode_norml_dma_size; +wire [13:0] mode_norml_spt_size; +wire [14:0] spt_fifo_pd; +wire spt_fifo_prdy; +wire spt_fifo_pvld; +////////cfg reg//////////// +assign cfg_dst_addr = reg2dp_dst_base_addr_low; +assign cfg_dst_surf_stride = {reg2dp_dst_surface_stride}; +assign cfg_dst_line_stride = {reg2dp_dst_line_stride}; +assign cfg_mode_batch = 1'b0; +assign cfg_mode_winog = 1'b0 ; +assign cfg_di_int8 = reg2dp_proc_precision == 0 ; +assign cfg_di_int16 = reg2dp_proc_precision == 1 ; +assign cfg_do_int8 = reg2dp_out_precision == 0 ; +assign cfg_do_int16 = reg2dp_out_precision == 1 ; +assign cfg_mode_8to16 = 1'b0; +assign cfg_mode_norml = !(cfg_mode_batch | cfg_mode_winog | cfg_mode_8to16); +assign cfg_mode_1x1_pack = (reg2dp_width==0) & (reg2dp_height==0); +assign cfg_mode_1x1_nbatch = cfg_mode_1x1_pack & !cfg_mode_batch ; +assign cfg_mode_eql = (reg2dp_ew_bypass== 1'h0 ) + & (reg2dp_ew_alu_bypass== 1'h0 ) + & (reg2dp_ew_alu_algo== 2'h3 ); +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cfg_mode_quite = cfg_mode_eql | cfg_mode_pdp; +assign cfg_addr_en = !cfg_mode_quite; +//============== +// Surf is always in unit of ATOMIC (1x1x32B) +always @( + cfg_di_int8 + or reg2dp_channel + or cfg_di_int16 + ) begin + if (cfg_di_int8) begin + size_of_surf = {1'b0,reg2dp_channel[12:3]}; + end else if (cfg_di_int16) begin + size_of_surf = reg2dp_channel[12:3 -1]; + end else begin + size_of_surf = reg2dp_channel[12:3 -1]; + end +end +//================================================= +// Cube Shape +//================================================= +assign is_winog_end = is_last_wg; +assign is_elem_end = cfg_mode_1x1_nbatch | is_last_e; +assign is_line_end = cfg_mode_1x1_nbatch | cfg_mode_norml | (is_last_batch & is_elem_end & is_last_w & is_winog_end); +assign is_surf_end = cfg_mode_1x1_nbatch | is_line_end & is_last_h; +assign is_cube_end = cfg_mode_1x1_nbatch | is_surf_end & is_last_c; +//============== +// Width Count; +//============== +// Norml Mode +wire [2:0] beg_addr_offset = base_addr_line[2:0]; +wire is_beg_addr_odd = beg_addr_offset[0]==1'b1; +wire [3:0] end_addr_offset = beg_addr_offset + reg2dp_width[2:0]; +wire is_end_addr_odd = end_addr_offset[0]==1'b0; +wire odd = ((is_ftrans & is_beg_addr_odd) || (is_ltrans && is_end_addr_odd)); +//================================ +// SIZE of Trans +//================================ +assign is_last_wg = 1'b1; +always @( + reg2dp_width + ) begin + size_of_width = {1'b0, reg2dp_width}; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_w <= {14{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_line_end) begin + count_w <= 0; + end else if (is_last_batch & is_winog_end) begin + count_w <= count_w + 1'b1; + end + end + end +end +assign is_ltrans = (count_w==size_of_width); +assign is_ftrans = (count_w==0); +assign is_last_w = is_ltrans; +assign is_last_e = 1'b1; +//============== +// HEIGHT Count: +//============== +assign size_of_height = reg2dp_height; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_h <= {13{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_last_batch) begin + if (is_surf_end) begin + count_h <= 0; + end else if (is_line_end) begin + count_h <= count_h + 1; + end + end + end + end +end +assign is_last_h = count_h==size_of_height; +//============== +// CHANNEL Count +//============== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + count_c <= {9{1'b0}}; + end else begin + if (cmd_accept) begin + if (is_last_batch) begin + if (is_cube_end) begin + count_c <= 0; + end else if (is_surf_end) begin + count_c <= count_c + 1; + end + end + end + end +end +assign is_last_c = (count_c==size_of_surf); +assign is_last_batch = 1'b1; +//========================================== +// DMA Req : ADDR PREPARE +//========================================== +// WIDTH +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_base_addr_width_c,base_addr_width} <= {(32 -3 +1){1'b0}}; + end else begin + if (cfg_addr_en) begin + if (op_load) begin + {mon_base_addr_width_c,base_addr_width} <= {1'b0,cfg_dst_addr}; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_surf + cfg_dst_surf_stride; + end else if (is_line_end) begin + {mon_base_addr_width_c,base_addr_width} <= base_addr_line + cfg_dst_line_stride; + end + end + end + end + end +end +// LINE +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_base_addr_line_c,base_addr_line} <= {(32 -3 +1){1'b0}}; + end else begin + if (cfg_addr_en) begin + if (op_load) begin + {mon_base_addr_line_c,base_addr_line} <= {1'b0,cfg_dst_addr}; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_surf + cfg_dst_surf_stride; + end else if (is_line_end) begin + {mon_base_addr_line_c,base_addr_line} <= base_addr_line + cfg_dst_line_stride; + end + end + end + end + end +end +// SURF +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + {mon_base_addr_surf_c,base_addr_surf} <= {(32 -3 +1){1'b0}}; + end else begin + if (cfg_addr_en) begin + if (op_load) begin + {mon_base_addr_surf_c,base_addr_surf} <= {1'b0,cfg_dst_addr}; + end else if (cmd_accept) begin + begin + if (is_surf_end) begin + {mon_base_addr_surf_c,base_addr_surf} <= base_addr_surf + cfg_dst_surf_stride; + end + end + end + end + end +end +//========================================== +// DMA Req : SIZE +//========================================== +always @( + base_addr_line + ) begin + begin + dma_addr = base_addr_line; + end +end +//======================== +// Output: one for data write spt_; and one for data read dma_ +//======================== +// spt_size is to tell how many data from dp2wdma for a corresponding DMA req to MC/CF if +// spt_size is in unit of cycle on dp2wdma +assign mode_1x1_spt_size = (cfg_do_int8 | cfg_di_int8) ? {1'b0,reg2dp_channel[12:3]} : reg2dp_channel[12:3 -1]; +assign mode_norml_spt_size[13:0] = {1'b0,reg2dp_width}; +always @( + cfg_mode_1x1_nbatch + or mode_1x1_spt_size + or mode_norml_spt_size + ) begin + if (cfg_mode_1x1_nbatch) + spt_size = {{3{1'b0}}, mode_1x1_spt_size}; + else + spt_size = mode_norml_spt_size; +end +//======================== +// Output: one for data write spt_; and one for data read dma_ +//======================== +assign mode_1x1_dma_size = size_of_surf; +assign mode_norml_dma_size = reg2dp_width; +always @( + cfg_mode_1x1_nbatch + or mode_1x1_dma_size + or mode_norml_dma_size + ) begin + if (cfg_mode_1x1_nbatch) + dma_size = {{3 -1{1'b0}}, mode_1x1_dma_size}; + else + dma_size = mode_norml_dma_size; +end +//================================================= +// OUTPUT FIFO: SPT & DMA channel +//================================================= +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmd_vld <= 1'b0; + end else begin + if (op_load) begin + cmd_vld <= 1'b1; + end else if (cmd_accept) begin + if (is_cube_end) begin + cmd_vld <= 1'b0; + end + end + end +end +assign spt_fifo_pvld = cmd_vld & dma_fifo_prdy; +assign dma_fifo_pvld = cmd_vld & spt_fifo_prdy; +assign cmd_rdy = dma_fifo_prdy & spt_fifo_prdy; +assign cmd_accept = cmd_vld & cmd_rdy; +assign spt_fifo_pd[13:0] = spt_size[13:0]; +assign spt_fifo_pd[14] = odd ; +assign dma_fifo_pd[32 -3 -1:0] = dma_addr[32 -3 -1:0]; +assign dma_fifo_pd[32 -3 +13 -1:32 -3] = dma_size[12:0]; +assign dma_fifo_pd[32 -3 +13] = odd ; +assign dma_fifo_pd[32 -3 +13 +1] = is_cube_end ; +NV_NVDLA_SDP_WDMA_CMD_sfifo u_sfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.spt_fifo_prdy (spt_fifo_prdy) + ,.spt_fifo_pvld (spt_fifo_pvld) + ,.spt_fifo_pd (spt_fifo_pd[14:0]) + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +NV_NVDLA_SDP_WDMA_CMD_dfifo u_dfifo ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.dma_fifo_prdy (dma_fifo_prdy) + ,.dma_fifo_pvld (dma_fifo_pvld) + ,.dma_fifo_pd (dma_fifo_pd[32 -3 +13 +1:0]) + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP_WDMA: no overflow is allowed") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_width_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP_WDMA: no overflow is allowed") zzz_assert_never_4x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_line_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"SDP_WDMA: no overflow is allowed") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, mon_base_addr_surf_c); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//======================== +// FUNCTION POINT +//======================== +//VCS coverage off +`ifndef DISABLE_FUNCPOINT + `ifdef ENABLE_FUNCPOINT + reg funcpoint_cover_off; + initial begin + if ( $test$plusargs( "cover_off" ) ) begin + funcpoint_cover_off = 1'b1; + end else begin + funcpoint_cover_off = 1'b0; + end + end + property sdp_wdma_cmd__odd_address__0_cov; + disable iff((nvdla_core_rstn !== 1) || funcpoint_cover_off) + @(posedge nvdla_core_clk) + ((cmd_vld) && nvdla_core_rstn) |-> (odd); + endproperty +// Cover 0 : "odd" + FUNCPOINT_sdp_wdma_cmd__odd_address__0_COV : cover property (sdp_wdma_cmd__odd_address__0_cov); + `endif +`endif +//VCS coverage on +endmodule // NV_NVDLA_SDP_WDMA_cmd +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_CMD_sfifo ( + nvdla_core_clk + , nvdla_core_rstn + , spt_fifo_prdy + , spt_fifo_pvld + , spt_fifo_pd + , cmd2dat_spt_prdy + , cmd2dat_spt_pvld + , cmd2dat_spt_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output spt_fifo_prdy; +input spt_fifo_pvld; +input [14:0] spt_fifo_pd; +input cmd2dat_spt_prdy; +output cmd2dat_spt_pvld; +output [14:0] cmd2dat_spt_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg spt_fifo_busy_int; // copy for internal use +assign spt_fifo_prdy = !spt_fifo_busy_int; +assign wr_reserving = spt_fifo_pvld && !spt_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] spt_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? spt_fifo_count : (spt_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (spt_fifo_count + 1'd1) : spt_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire spt_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check spt_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_busy_int <= 1'b0; + spt_fifo_count <= 3'd0; + end else begin + spt_fifo_busy_int <= spt_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + spt_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + spt_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as spt_fifo_pvld +// +// RAM +// +reg [1:0] spt_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + spt_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + spt_fifo_adr <= spt_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_spt_adr; // read address this cycle +wire ram_we = wr_pushing && (spt_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [14:0] cmd2dat_spt_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( spt_fifo_pd ) + , .we ( ram_we ) + , .wa ( spt_fifo_adr ) + , .ra ( (spt_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_spt_adr} ) + , .dout ( cmd2dat_spt_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_spt_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_spt_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_spt_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_spt_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_spt_pvld && cmd2dat_spt_prdy; +reg [2:0] cmd2dat_spt_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_spt_count : + (cmd2dat_spt_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_spt_count + 1'd1) : + cmd2dat_spt_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_spt_pvld = cmd2dat_spt_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_spt_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_spt_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_spt_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (spt_fifo_pvld && !spt_fifo_busy_int) || (spt_fifo_busy_int != spt_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_spt_pvld && cmd2dat_spt_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_WDMA_CMD_sfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, spt_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_WDMA_CMD_sfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_WDMA_CMD_sfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [14:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [14:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [14:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [14:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [14:0] ram_ff0; +reg [14:0] ram_ff1; +reg [14:0] ram_ff2; +reg [14:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [14:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {15{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [14:0] Di0; +input [1:0] Ra0; +output [14:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 15'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [14:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [14:0] Q0 = mem[0]; +wire [14:0] Q1 = mem[1]; +wire [14:0] Q2 = mem[2]; +wire [14:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15] } +endmodule // vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +//vmw: Memory vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +//vmw: Address-size 2 +//vmw: Data-size 15 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[14:0] data0[14:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[14:0] data1[14:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_WDMA_CMD_sfifo_flopram_rwsa_4x15 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_CMD_dfifo ( + nvdla_core_clk + , nvdla_core_rstn + , dma_fifo_prdy + , dma_fifo_pvld + , dma_fifo_pd + , cmd2dat_dma_prdy + , cmd2dat_dma_pvld + , cmd2dat_dma_pd + , pwrbus_ram_pd + ); +// spyglass disable_block W401 -- clock is not input to module +input nvdla_core_clk; +input nvdla_core_rstn; +output dma_fifo_prdy; +input dma_fifo_pvld; +input [43:0] dma_fifo_pd; +input cmd2dat_dma_prdy; +output cmd2dat_dma_pvld; +output [43:0] cmd2dat_dma_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +wire wr_reserving; +reg dma_fifo_busy_int; // copy for internal use +assign dma_fifo_prdy = !dma_fifo_busy_int; +assign wr_reserving = dma_fifo_pvld && !dma_fifo_busy_int; // reserving write space? +wire wr_popping; // fwd: write side sees pop? +reg [2:0] dma_fifo_count; // write-side count +wire [2:0] wr_count_next_wr_popping = wr_reserving ? dma_fifo_count : (dma_fifo_count - 1'd1); // spyglass disable W164a W484 +wire [2:0] wr_count_next_no_wr_popping = wr_reserving ? (dma_fifo_count + 1'd1) : dma_fifo_count; // spyglass disable W164a W484 +wire [2:0] wr_count_next = wr_popping ? wr_count_next_wr_popping : + wr_count_next_no_wr_popping; +wire wr_count_next_no_wr_popping_is_4 = ( wr_count_next_no_wr_popping == 3'd4 ); +wire wr_count_next_is_4 = wr_popping ? 1'b0 : + wr_count_next_no_wr_popping_is_4; +wire [2:0] wr_limit_muxed; // muxed with simulation/emulation overrides +wire [2:0] wr_limit_reg = wr_limit_muxed; +// VCS coverage off +wire dma_fifo_busy_next = wr_count_next_is_4 || // busy next cycle? + (wr_limit_reg != 3'd0 && // check dma_fifo_limit if != 0 + wr_count_next >= wr_limit_reg) ; +// VCS coverage on +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_busy_int <= 1'b0; + dma_fifo_count <= 3'd0; + end else begin + dma_fifo_busy_int <= dma_fifo_busy_next; + if ( wr_reserving ^ wr_popping ) begin + dma_fifo_count <= wr_count_next; + end +//synopsys translate_off + else if ( !(wr_reserving ^ wr_popping) ) begin + end else begin + dma_fifo_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +wire wr_pushing = wr_reserving; // data pushed same cycle as dma_fifo_pvld +// +// RAM +// +reg [1:0] dma_fifo_adr; // current write address +// spyglass disable_block W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + dma_fifo_adr <= 2'd0; + end else begin + if ( wr_pushing ) begin + dma_fifo_adr <= dma_fifo_adr + 1'd1; + end + end +end +// spyglass enable_block W484 +wire rd_popping; +reg [1:0] cmd2dat_dma_adr; // read address this cycle +wire ram_we = wr_pushing && (dma_fifo_count > 3'd0 || !rd_popping); // note: write occurs next cycle +wire [43:0] cmd2dat_dma_pd; // read data out of ram +wire [31 : 0] pwrbus_ram_pd; +// Adding parameter for fifogen to disable wr/rd contention assertion in ramgen. +// Fifogen handles this by ignoring the data on the ram data out for that cycle. +NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 ram ( + .clk( nvdla_core_clk_mgated ) + , .pwrbus_ram_pd ( pwrbus_ram_pd ) + , .di ( dma_fifo_pd ) + , .we ( ram_we ) + , .wa ( dma_fifo_adr ) + , .ra ( (dma_fifo_count == 0) ? 3'd4 : {1'b0,cmd2dat_dma_adr} ) + , .dout ( cmd2dat_dma_pd ) + ); +wire [1:0] rd_adr_next_popping = cmd2dat_dma_adr + 1'd1; // spyglass disable W484 +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_adr <= 2'd0; + end else begin + if ( rd_popping ) begin + cmd2dat_dma_adr <= rd_adr_next_popping; + end +//synopsys translate_off + else if ( !rd_popping ) begin + end else begin + cmd2dat_dma_adr <= {2{`x_or_0}}; + end +//synopsys translate_on + end +end +// +// SYNCHRONOUS BOUNDARY +// +assign wr_popping = rd_popping; // let it be seen immediately +wire rd_pushing = wr_pushing; // let it be seen immediately +// +// READ SIDE +// +wire cmd2dat_dma_pvld; // data out of fifo is valid +assign rd_popping = cmd2dat_dma_pvld && cmd2dat_dma_prdy; +reg [2:0] cmd2dat_dma_count; // read-side fifo count +// spyglass disable_block W164a W484 +wire [2:0] rd_count_next_rd_popping = rd_pushing ? cmd2dat_dma_count : + (cmd2dat_dma_count - 1'd1); +wire [2:0] rd_count_next_no_rd_popping = rd_pushing ? (cmd2dat_dma_count + 1'd1) : + cmd2dat_dma_count; +// spyglass enable_block W164a W484 +wire [2:0] rd_count_next = rd_popping ? rd_count_next_rd_popping : + rd_count_next_no_rd_popping; +assign cmd2dat_dma_pvld = cmd2dat_dma_count != 0 || rd_pushing; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + cmd2dat_dma_count <= 3'd0; + end else begin + if ( rd_pushing || rd_popping ) begin + cmd2dat_dma_count <= rd_count_next; + end +//synopsys translate_off + else if ( !(rd_pushing || rd_popping ) ) begin + end else begin + cmd2dat_dma_count <= {3{`x_or_0}}; + end +//synopsys translate_on + end +end +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((wr_reserving || wr_pushing || wr_popping || (dma_fifo_pvld && !dma_fifo_busy_int) || (dma_fifo_busy_int != dma_fifo_busy_next)) || (rd_pushing || rd_popping || (cmd2dat_dma_pvld && cmd2dat_dma_prdy)) || (wr_pushing)) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// Simulation and Emulation Overrides of wr_limit(s) +// +`ifdef EMU +`ifdef EMU_FIFO_CFG +// Emulation Global Config Override +// +assign wr_limit_muxed = `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit_override ? `EMU_FIFO_CFG.NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit : 3'd0; +`else +// No Global Override for Emulation +// +assign wr_limit_muxed = 3'd0; +`endif // EMU_FIFO_CFG +`else // !EMU +`ifdef SYNTH_LEVEL1_COMPILE +// No Override for GCS Compiles +// +assign wr_limit_muxed = 3'd0; +`else +`ifdef SYNTHESIS +// No Override for RTL Synthesis +// +assign wr_limit_muxed = 3'd0; +`else +// RTL Simulation Plusarg Override +// VCS coverage off +reg wr_limit_override; +reg [2:0] wr_limit_override_value; +assign wr_limit_muxed = wr_limit_override ? wr_limit_override_value : 3'd0; +`ifdef NV_ARCHPRO +event reinit; +initial begin + $display("fifogen reinit initial block %m"); + -> reinit; +end +`endif +`ifdef NV_ARCHPRO +always @( reinit ) begin +`else +initial begin +`endif + wr_limit_override = 0; + wr_limit_override_value = 0; // to keep viva happy with dangles + if ( $test$plusargs( "NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit" ) ) begin + wr_limit_override = 1; + $value$plusargs( "NV_NVDLA_SDP_WDMA_CMD_dfifo_wr_limit=%d", wr_limit_override_value); + end +end +// VCS coverage on +`endif +`endif +`endif +// +// Histogram of fifo depth (from write side's perspective) +// +// NOTE: it will reference `SIMTOP.perfmon_enabled, so that +// has to at least be defined, though not initialized. +// tbgen testbenches have it already and various +// ways to turn it on and off. +// +`ifdef PERFMON_HISTOGRAM +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +perfmon_histogram perfmon ( + .clk ( nvdla_core_clk ) + , .max ( {29'd0, (wr_limit_reg == 3'd0) ? 3'd4 : wr_limit_reg} ) + , .curr ( {29'd0, dma_fifo_count} ) + ); +`endif +`endif +// synopsys translate_on +`endif +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +// spyglass enable_block W401 -- clock is not input to module +// synopsys dc_script_begin +// set_boundary_optimization find(design, "NV_NVDLA_SDP_WDMA_CMD_dfifo") true +// synopsys dc_script_end +endmodule // NV_NVDLA_SDP_WDMA_CMD_dfifo +// +// Flop-Based RAM +// +module NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 ( + clk + , pwrbus_ram_pd + , di + , we + , wa + , ra + , dout + ); +input clk; // write clock +input [31 : 0] pwrbus_ram_pd; +input [43:0] di; +input we; +input [1:0] wa; +input [2:0] ra; +output [43:0] dout; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +`ifdef EMU +wire [43:0] dout_p; +// we use an emulation ram here to save flops on the emulation board +// so that the monstrous chip can fit :-) +// +reg [1:0] Wa0_vmw; +reg we0_vmw; +reg [43:0] Di0_vmw; +always @( posedge clk ) begin + Wa0_vmw <= wa; + we0_vmw <= we; + Di0_vmw <= di; +end +vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 emu_ram ( + .Wa0( Wa0_vmw ) + , .we0( we0_vmw ) + , .Di0( Di0_vmw ) + , .Ra0( ra[1:0] ) + , .Do0( dout_p ) + ); +assign dout = (ra == 4) ? di : dout_p; +`else +reg [43:0] ram_ff0; +reg [43:0] ram_ff1; +reg [43:0] ram_ff2; +reg [43:0] ram_ff3; +always @( posedge clk ) begin + if ( we && wa == 2'd0 ) begin + ram_ff0 <= di; + end + if ( we && wa == 2'd1 ) begin + ram_ff1 <= di; + end + if ( we && wa == 2'd2 ) begin + ram_ff2 <= di; + end + if ( we && wa == 2'd3 ) begin + ram_ff3 <= di; + end +end +reg [43:0] dout; +always @(*) begin + case( ra ) + 3'd0: dout = ram_ff0; + 3'd1: dout = ram_ff1; + 3'd2: dout = ram_ff2; + 3'd3: dout = ram_ff3; + 3'd4: dout = di; +//VCS coverage off + default: dout = {44{`x_or_0}}; +//VCS coverage on + endcase +end +`endif // EMU +endmodule // NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +// emulation model of flopram guts +// +`ifdef EMU +module vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 ( + Wa0, we0, Di0, + Ra0, Do0 + ); +input [1:0] Wa0; +input we0; +input [43:0] Di0; +input [1:0] Ra0; +output [43:0] Do0; +// Only visible during Spyglass to avoid blackboxes. +`ifdef SPYGLASS_FLOPRAM +assign Do0 = 44'd0; +wire dummy = 1'b0 | (|Wa0) | (|we0) | (|Di0) | (|Ra0); +`endif +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg [43:0] mem[3:0]; +// expand mem for debug ease +`ifdef EMU_EXPAND_FLOPRAM_MEM +wire [43:0] Q0 = mem[0]; +wire [43:0] Q1 = mem[1]; +wire [43:0] Q2 = mem[2]; +wire [43:0] Q3 = mem[3]; +`endif +// asynchronous ram writes +always @(*) begin + if ( we0 == 1'b1 ) begin + #0.1; + mem[Wa0] = Di0; + end +end +assign Do0 = mem[Ra0]; +`endif +`endif +// synopsys translate_on +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44] != {} } { set_attr preserve 1 [find / -subdesign vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44] } +endmodule // vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +//vmw: Memory vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +//vmw: Address-size 2 +//vmw: Data-size 44 +//vmw: Sensitivity level 1 +//vmw: Ports W R +//vmw: terminal we0 WriteEnable0 +//vmw: terminal Wa0 address0 +//vmw: terminal Di0[43:0] data0[43:0] +//vmw: +//vmw: terminal Ra0 address1 +//vmw: terminal Do0[43:0] data1[43:0] +//vmw: +//qt: CELL vmw_NV_NVDLA_SDP_WDMA_CMD_dfifo_flopram_rwsa_4x44 +//qt: TERMINAL we0 TYPE=WE POLARITY=H PORT=1 +//qt: TERMINAL Wa0[%d] TYPE=ADDRESS DIR=W BIT=%1 PORT=1 +//qt: TERMINAL Di0[%d] TYPE=DATA DIR=I BIT=%1 PORT=1 +//qt: +//qt: TERMINAL Ra0[%d] TYPE=ADDRESS DIR=R BIT=%1 PORT=1 +//qt: TERMINAL Do0[%d] TYPE=DATA DIR=O BIT=%1 PORT=1 +//qt: +`endif // EMU diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v new file mode 100644 index 0000000..b988945 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v @@ -0,0 +1,167 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_dat.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_WDMA_dat ( + cmd2dat_dma_pd //|< i + ,cmd2dat_dma_pvld //|< i + ,cmd2dat_spt_pd //|< i + ,cmd2dat_spt_pvld //|< i + ,dma_wr_req_rdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ,reg2dp_height //|< i + ,reg2dp_interrupt_ptr //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_width //|< i + ,reg2dp_winograd //|< i + ,sdp_dp2wdma_pd //|< i + ,sdp_dp2wdma_valid //|< i + ,cmd2dat_dma_prdy //|> o + ,cmd2dat_spt_prdy //|> o + ,dma_wr_req_pd //|> o + ,dma_wr_req_vld //|> o + ,dp2reg_done //|> o + ,dp2reg_status_nan_output_num //|> o + ,dp2reg_status_unequal //|> o + ,intr_req_ptr //|> o + ,intr_req_pvld //|> o + ,sdp_dp2wdma_ready //|> o + ); +// +// NV_NVDLA_SDP_WDMA_dat_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input cmd2dat_dma_pvld; +output cmd2dat_dma_prdy; +input [32 -3 +13 +1:0] cmd2dat_dma_pd; +input cmd2dat_spt_pvld; +output cmd2dat_spt_prdy; +input [14:0] cmd2dat_spt_pd; +input sdp_dp2wdma_valid; +output sdp_dp2wdma_ready; +input [8*8 -1:0] sdp_dp2wdma_pd; +input dma_wr_req_rdy; +input op_load; +input [31:0] pwrbus_ram_pd; +input [4:0] reg2dp_batch_number; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input [12:0] reg2dp_height; +input reg2dp_interrupt_ptr; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +input reg2dp_winograd; +output [66 -1:0] dma_wr_req_pd; +output dma_wr_req_vld; +output dp2reg_done; +output [31:0] dp2reg_status_nan_output_num; +output dp2reg_status_unequal; +output intr_req_ptr; +output intr_req_pvld; +wire [8*8 -1:0] dfifo0_rd_pd; +wire dfifo0_rd_prdy; +wire dfifo0_rd_pvld; +wire [8*8 -1:0] dfifo1_rd_pd; +wire dfifo1_rd_prdy; +wire dfifo1_rd_pvld; +wire [8*8 -1:0] dfifo2_rd_pd; +wire dfifo2_rd_prdy; +wire dfifo2_rd_pvld; +wire [8*8 -1:0] dfifo3_rd_pd; +wire dfifo3_rd_prdy; +wire dfifo3_rd_pvld; +NV_NVDLA_SDP_WDMA_DAT_in u_in ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) //|< i + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) //|> o + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) //|< i + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) //|< i + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) //|> o + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) //|< i + ,.dfifo0_rd_pvld (dfifo0_rd_pvld) //|> w + ,.dfifo0_rd_prdy (dfifo0_rd_prdy) //|< w + ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0]) //|> w + ,.dfifo1_rd_pvld (dfifo1_rd_pvld) //|> w + ,.dfifo1_rd_prdy (dfifo1_rd_prdy) //|< w + ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0]) //|> w + ,.dfifo2_rd_pvld (dfifo2_rd_pvld) //|> w + ,.dfifo2_rd_prdy (dfifo2_rd_prdy) //|< w + ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0]) //|> w + ,.dfifo3_rd_pvld (dfifo3_rd_pvld) //|> w + ,.dfifo3_rd_prdy (dfifo3_rd_prdy) //|< w + ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0]) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< i + ); +NV_NVDLA_SDP_WDMA_DAT_out u_out ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) //|< i + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) //|> o + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) //|< i + ,.dfifo0_rd_pvld (dfifo0_rd_pvld) //|< w + ,.dfifo0_rd_prdy (dfifo0_rd_prdy) //|> w + ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0]) //|< w + ,.dfifo1_rd_pvld (dfifo1_rd_pvld) //|< w + ,.dfifo1_rd_prdy (dfifo1_rd_prdy) //|> w + ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0]) //|< w + ,.dfifo2_rd_pvld (dfifo2_rd_pvld) //|< w + ,.dfifo2_rd_prdy (dfifo2_rd_prdy) //|> w + ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0]) //|< w + ,.dfifo3_rd_pvld (dfifo3_rd_pvld) //|< w + ,.dfifo3_rd_prdy (dfifo3_rd_prdy) //|> w + ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0]) //|< w + ,.op_load (op_load) //|< i + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) //|< i + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) //|< i + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_output_dst (reg2dp_output_dst) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.dp2reg_done (dp2reg_done) //|> o + ,.dp2reg_status_unequal (dp2reg_status_unequal) //|> o + ,.dma_wr_req_rdy (dma_wr_req_rdy) //|< i + ,.dma_wr_req_pd (dma_wr_req_pd[66 -1:0]) //|> o + ,.dma_wr_req_vld (dma_wr_req_vld) //|> o + ,.intr_req_ptr (intr_req_ptr) //|> o + ,.intr_req_pvld (intr_req_pvld) //|> o + ); +endmodule // NV_NVDLA_SDP_WDMA_dat diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v.vcp new file mode 100644 index 0000000..b988945 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_dat.v.vcp @@ -0,0 +1,167 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_dat.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_WDMA_dat ( + cmd2dat_dma_pd //|< i + ,cmd2dat_dma_pvld //|< i + ,cmd2dat_spt_pd //|< i + ,cmd2dat_spt_pvld //|< i + ,dma_wr_req_rdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ,reg2dp_height //|< i + ,reg2dp_interrupt_ptr //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_width //|< i + ,reg2dp_winograd //|< i + ,sdp_dp2wdma_pd //|< i + ,sdp_dp2wdma_valid //|< i + ,cmd2dat_dma_prdy //|> o + ,cmd2dat_spt_prdy //|> o + ,dma_wr_req_pd //|> o + ,dma_wr_req_vld //|> o + ,dp2reg_done //|> o + ,dp2reg_status_nan_output_num //|> o + ,dp2reg_status_unequal //|> o + ,intr_req_ptr //|> o + ,intr_req_pvld //|> o + ,sdp_dp2wdma_ready //|> o + ); +// +// NV_NVDLA_SDP_WDMA_dat_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input cmd2dat_dma_pvld; +output cmd2dat_dma_prdy; +input [32 -3 +13 +1:0] cmd2dat_dma_pd; +input cmd2dat_spt_pvld; +output cmd2dat_spt_prdy; +input [14:0] cmd2dat_spt_pd; +input sdp_dp2wdma_valid; +output sdp_dp2wdma_ready; +input [8*8 -1:0] sdp_dp2wdma_pd; +input dma_wr_req_rdy; +input op_load; +input [31:0] pwrbus_ram_pd; +input [4:0] reg2dp_batch_number; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input [12:0] reg2dp_height; +input reg2dp_interrupt_ptr; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input [1:0] reg2dp_proc_precision; +input [12:0] reg2dp_width; +input reg2dp_winograd; +output [66 -1:0] dma_wr_req_pd; +output dma_wr_req_vld; +output dp2reg_done; +output [31:0] dp2reg_status_nan_output_num; +output dp2reg_status_unequal; +output intr_req_ptr; +output intr_req_pvld; +wire [8*8 -1:0] dfifo0_rd_pd; +wire dfifo0_rd_prdy; +wire dfifo0_rd_pvld; +wire [8*8 -1:0] dfifo1_rd_pd; +wire dfifo1_rd_prdy; +wire dfifo1_rd_pvld; +wire [8*8 -1:0] dfifo2_rd_pd; +wire dfifo2_rd_prdy; +wire dfifo2_rd_pvld; +wire [8*8 -1:0] dfifo3_rd_pd; +wire dfifo3_rd_prdy; +wire dfifo3_rd_pvld; +NV_NVDLA_SDP_WDMA_DAT_in u_in ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) //|< i + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) //|> o + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) //|< i + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) //|< i + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) //|> o + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) //|< i + ,.dfifo0_rd_pvld (dfifo0_rd_pvld) //|> w + ,.dfifo0_rd_prdy (dfifo0_rd_prdy) //|< w + ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0]) //|> w + ,.dfifo1_rd_pvld (dfifo1_rd_pvld) //|> w + ,.dfifo1_rd_prdy (dfifo1_rd_prdy) //|< w + ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0]) //|> w + ,.dfifo2_rd_pvld (dfifo2_rd_pvld) //|> w + ,.dfifo2_rd_prdy (dfifo2_rd_prdy) //|< w + ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0]) //|> w + ,.dfifo3_rd_pvld (dfifo3_rd_pvld) //|> w + ,.dfifo3_rd_prdy (dfifo3_rd_prdy) //|< w + ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0]) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) //|> o + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< i + ); +NV_NVDLA_SDP_WDMA_DAT_out u_out ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) //|< i + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) //|> o + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) //|< i + ,.dfifo0_rd_pvld (dfifo0_rd_pvld) //|< w + ,.dfifo0_rd_prdy (dfifo0_rd_prdy) //|> w + ,.dfifo0_rd_pd (dfifo0_rd_pd[8*8 -1:0]) //|< w + ,.dfifo1_rd_pvld (dfifo1_rd_pvld) //|< w + ,.dfifo1_rd_prdy (dfifo1_rd_prdy) //|> w + ,.dfifo1_rd_pd (dfifo1_rd_pd[8*8 -1:0]) //|< w + ,.dfifo2_rd_pvld (dfifo2_rd_pvld) //|< w + ,.dfifo2_rd_prdy (dfifo2_rd_prdy) //|> w + ,.dfifo2_rd_pd (dfifo2_rd_pd[8*8 -1:0]) //|< w + ,.dfifo3_rd_pvld (dfifo3_rd_pvld) //|< w + ,.dfifo3_rd_prdy (dfifo3_rd_prdy) //|> w + ,.dfifo3_rd_pd (dfifo3_rd_pd[8*8 -1:0]) //|< w + ,.op_load (op_load) //|< i + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) //|< i + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) //|< i + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_output_dst (reg2dp_output_dst) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.dp2reg_done (dp2reg_done) //|> o + ,.dp2reg_status_unequal (dp2reg_status_unequal) //|> o + ,.dma_wr_req_rdy (dma_wr_req_rdy) //|< i + ,.dma_wr_req_pd (dma_wr_req_pd[66 -1:0]) //|> o + ,.dma_wr_req_vld (dma_wr_req_vld) //|> o + ,.intr_req_ptr (intr_req_ptr) //|> o + ,.intr_req_pvld (intr_req_pvld) //|> o + ); +endmodule // NV_NVDLA_SDP_WDMA_dat diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v new file mode 100644 index 0000000..8c4af19 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v @@ -0,0 +1,388 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_gate.v +module NV_NVDLA_SDP_WDMA_gate ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,reg2dp_wdma_slcg_op_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_wdma_slcg_op_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +wire cfg_clk_en; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +assign cfg_clk_en = reg2dp_wdma_slcg_op_en; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_WDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v.vcp new file mode 100644 index 0000000..8c4af19 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_gate.v.vcp @@ -0,0 +1,388 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_gate.v +module NV_NVDLA_SDP_WDMA_gate ( + dla_clk_ovr_on_sync + ,global_clk_ovr_on_sync + ,nvdla_core_clk + ,nvdla_core_rstn + ,reg2dp_wdma_slcg_op_en + ,tmc2slcg_disable_clock_gating + ,nvdla_gated_clk + ); +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input nvdla_core_clk; +input nvdla_core_rstn; +input reg2dp_wdma_slcg_op_en; +input tmc2slcg_disable_clock_gating; +output nvdla_gated_clk; +wire cfg_clk_en; +//======================================= +//CLock Gating: when BRDMA_MODE = NONE +assign cfg_clk_en = reg2dp_wdma_slcg_op_en; +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +reg nvdla_core_clk_slcg_0_icg_disable_eos; +initial begin + nvdla_core_clk_slcg_0_icg_disable_eos = 1'b0; + if ($test$plusargs ("icg_no_eos_disable")) nvdla_core_clk_slcg_0_icg_disable_eos = 1'b1; +end +wire nvdla_core_clk_slcg_0_end_of_sim_clock_enable; +`ifndef SIMTOP_EOS_SIGNAL +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & 0; +`else +assign nvdla_core_clk_slcg_0_end_of_sim_clock_enable = ~nvdla_core_clk_slcg_0_icg_disable_eos & `SIMTOP_EOS_SIGNAL; +`endif // SIMTOP_EOS_SIGNAL +reg nvdla_core_clk_slcg_0_icg_override_to_ungated; +reg nvdla_core_clk_slcg_0_icg_override_to_gateable; +initial begin + nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b0; + nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b0; + if ($test$plusargs ("icg_override_to_ungated")) nvdla_core_clk_slcg_0_icg_override_to_ungated = 1'b1; + if ($test$plusargs ("icg_override_to_gateable")) nvdla_core_clk_slcg_0_icg_override_to_gateable = 1'b1; +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off +initial begin + if ($test$plusargs ("icg_global_force_message_on")) + $display("ICG_Assert::Found ICG instance: %m :: %s","nvdla_core_clk_slcg_0"); +end +wire assert2slcg_disable_clock_gating_0; +assign assert2slcg_disable_clock_gating_0 = tmc2slcg_disable_clock_gating; +always @(posedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge assert2slcg_disable_clock_gating_0) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on tmc2slcg_disable_clock_gating change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(posedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 0->1 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +always @(negedge global_clk_ovr_on_sync) begin + if ($test$plusargs ("icg_global_force_message_on")) begin + $display(" ICG_Assert::Found global_force_on global_clk_ovr_on_sync change from 1->0 for ICG instance %m :: %s","nvdla_core_clk_slcg_0"); + end +end +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +wire nvdla_core_clk_slcg_0_en; +assign nvdla_core_clk_slcg_0_en = cfg_clk_en | (dla_clk_ovr_on_sync +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) + | ((tmc2slcg_disable_clock_gating|global_clk_ovr_on_sync) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + && !nvdla_core_clk_slcg_0_icg_override_to_gateable +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM + ) +`ifndef NO_SIMTOP_END_OF_SIM +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +// VCS coverage off + | nvdla_core_clk_slcg_0_end_of_sim_clock_enable + | nvdla_core_clk_slcg_0_icg_override_to_ungated +// VCS coverage on +`endif // SYNTHESIS +`endif // SYNTH_LEVEL1_COMPILE +`endif // NO_SIMTOP_END_OF_SIM +; +NV_CLK_gate_power nvdla_core_clk_slcg_0 ( + .clk(nvdla_core_clk), + .reset_(nvdla_core_rstn), + .clk_en(nvdla_core_clk_slcg_0_en), + .clk_gated(nvdla_gated_clk) ); // spyglass disable GatedClock +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_0_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_0_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_0_internal_nvdla_core_rstn +// Clock signal: testpoint_0_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_0_internal_nvdla_core_clk or negedge testpoint_0_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_0 + if (~testpoint_0_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_0_count_0; + reg testpoint_0_goal_0; + initial testpoint_0_goal_0 = 0; + initial testpoint_0_count_0 = 0; + always@(testpoint_0_count_0) begin + if(testpoint_0_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_0_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: (dla_clk_ovr_on_sync)"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0 + testpoint_0_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_0_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_0_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_0 + if (testpoint_0_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b1 ::: testpoint_0_goal_0"); + `endif + if (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) + testpoint_0_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk) begin + `endif + testpoint_0_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_0_goal_0_active = (((dla_clk_ovr_on_sync)) && testpoint_got_reset_testpoint_0_internal_nvdla_core_rstn_with_clock_testpoint_0_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_0_goal_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b1_0 (.clk (testpoint_0_internal_nvdla_core_clk), .tp(testpoint_0_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b1_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END +`ifndef DISABLE_TESTPOINTS + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef COVER + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // COVER + `ifdef TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 + `define COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER + `endif // TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0 +`ifdef COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +//VCS coverage off +// TESTPOINT_START +// NAME=":Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0" +// TYPE=OCCURRENCE +// AUTOGEN=true +// COUNT=1 +// GROUP="DEFAULT" +// INFO="" +// RANDOM_COVER=true +// ASYNC_RESET=1 +// ACTIVE_HIGH_RESET=0 +wire testpoint_1_internal_nvdla_core_clk = nvdla_core_clk; +wire testpoint_1_internal_nvdla_core_rstn = nvdla_core_rstn; +`ifdef FV_COVER_ON +// Synthesizable code for SFV. + wire testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk = 1'b1; +`else +// Must be clocked with reset active before we start gathering +// coverage. +// Reset signal: testpoint_1_internal_nvdla_core_rstn +// Clock signal: testpoint_1_internal_nvdla_core_clk + reg testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk; + initial + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b0; + always @(posedge testpoint_1_internal_nvdla_core_clk or negedge testpoint_1_internal_nvdla_core_rstn) begin: HAS_RETENTION_TESTPOINT_RESET_1 + if (~testpoint_1_internal_nvdla_core_rstn) + testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk <= 1'b1; + end +`endif +`ifndef LINE_TESTPOINTS_OFF + reg testpoint_1_count_0; + reg testpoint_1_goal_0; + initial testpoint_1_goal_0 = 0; + initial testpoint_1_count_0 = 0; + always@(testpoint_1_count_0) begin + if(testpoint_1_count_0 >= 1) + begin + `ifdef COVER_PRINT_TESTPOINT_HITS + if (testpoint_1_goal_0 != 1'b1) + $display("TESTPOINT_HIT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: (!(dla_clk_ovr_on_sync))"); + `endif +//VCS coverage on +//coverage name NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0 + testpoint_1_goal_0 = 1'b1; +//VCS coverage off + end + else + testpoint_1_goal_0 = 1'b0; + end +// Increment counters for every condition that's true this clock. + always @(posedge testpoint_1_internal_nvdla_core_clk) begin: HAS_RETENTION_TESTPOINT_GOAL_1 + if (testpoint_1_internal_nvdla_core_rstn) begin + `ifdef ASSOCIATE_TESTPOINT_NAME_GOAL_NUMBER + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + $display("NVIDIA TESTPOINT: NV_NVDLA_SDP_WDMA_gate ::: :Test dla_clk_ovr_on_sync for nvdla_core_clk_slcg_0 = 1'b0 ::: testpoint_1_goal_0"); + `endif + if (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) + testpoint_1_count_0 <= 1'd1; + end + else begin + `ifndef FV_COVER_ON + if (!testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk) begin + `endif + testpoint_1_count_0 <= 1'd0; + `ifndef FV_COVER_ON + end + `endif + end + end +`endif // LINE_TESTPOINTS_OFF +`ifndef SV_TESTPOINTS_OFF + wire testpoint_1_goal_0_active = (((!(dla_clk_ovr_on_sync))) && testpoint_got_reset_testpoint_1_internal_nvdla_core_rstn_with_clock_testpoint_1_internal_nvdla_core_clk); +// system verilog testpoints, to leverage vcs testpoint coverage tools + `ifndef SV_TESTPOINTS_DESCRIPTIVE + system_verilog_testpoint svt_testpoint_1_goal_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `else + system_verilog_testpoint svt__Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0__1_b0_0 (.clk (testpoint_1_internal_nvdla_core_clk), .tp(testpoint_1_goal_0_active)); + `endif +`endif +//VCS coverage on +`endif //COVER_OR_TP___Test_dla_clk_ovr_on_sync_for_nvdla_core_clk_slcg_0___1_b0_OR_COVER +`endif // DISABLE_TESTPOINTS +// TESTPOINT_END + `ifdef ICG_SUMMARY + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS +// VCS coverage off +// reg monitor_icg_summary_0; + reg done_monitor_0; + integer clk_count_0; + integer clk_disable_count_0; + initial begin + clk_count_0 = 0; + clk_disable_count_0 = 0; +// monitor_icg_summary_0 = 0; + done_monitor_0= 0; + if ($test$plusargs( "icg_summary" ) ) begin +// monitor_icg_summary_0 = 1; + forever begin + @ (posedge nvdla_core_clk); + if(nvdla_core_rstn === 1'b0) begin + clk_count_0 <= 0; + clk_disable_count_0 <= 0; + end else begin + clk_count_0 <= clk_count_0 + 1; + if ( ~(nvdla_core_clk_slcg_0_en) == 1'b1) begin + clk_disable_count_0 <= clk_disable_count_0 + 1; + end + `ifndef SIMTOP_EOS_SIGNAL + if (0 == 1 && done_monitor_0 == 0) begin + `else + if (`SIMTOP_EOS_SIGNAL == 1 && done_monitor_0 == 0) begin + `endif // SIMTOP_EOS_SIGNAL +// $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, enabled_percent_0); + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary. Number of disabled clks = %0d, Total clks = %0d, Enabled %0f", $stime, clk_disable_count_0, clk_count_0, 1.0 - (1.0 * (clk_disable_count_0) / (clk_count_0))); + done_monitor_0 <= 1; + end + end + end + end + end +////integer enabled_percent_0; +////&Always; +//// if (monitor_icg_summary_0 == 1) begin +//// enabled_percent_0 = 1.0 - ( ( clk_disable_count_0 ) / ( clk_count_0 ) ); +//// end +////&End; +// VCS coverage on + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `else + `ifndef NO_SIMTOP_END_OF_SIM + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + initial begin + if ($test$plusargs( "icg_summary" ) ) begin + `ifndef SIMTOP_EOS_SIGNAL + @(posedge (0)) begin + `else + @(posedge (`SIMTOP_EOS_SIGNAL)) begin + `endif // SIMTOP_EOS_SIGNAL + $display ("(%0d): INFO: %m (icg_template): ICG (0) summary feature was not enabled at compile time. Please define ICG_SUMMARY, re-compile and re-run for icg summary",$stime); + end + end + end + `endif // SYNTHESIS + `endif // SYNTH_LEVEL1_COMPILE + `endif // NO_SIMTOP_END_OF_SIM + `endif // ICG_SUMMARY +//======================================= +//DMA +//--------------------------------------- +//| +//| +endmodule // NV_NVDLA_SDP_WDMA_gate diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v new file mode 100644 index 0000000..54431fa --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v @@ -0,0 +1,528 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_intr.v +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_intr ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dma_wr_req_rdy //|< i + ,dma_wr_req_vld //|< i + ,dma_wr_rsp_complete //|< i + ,intr_req_ptr //|< i + ,intr_req_pvld //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ,reg2dp_op_en //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_perf_dma_en //|< i + ,dp2reg_wdma_stall //|> o + ,sdp2glb_done_intr_pd //|> o + ); +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input reg2dp_op_en; +input reg2dp_output_dst; +input reg2dp_perf_dma_en; +output [31:0] dp2reg_wdma_stall; +input intr_req_ptr; +input intr_req_pvld; +input [31:0] pwrbus_ram_pd; +input nvdla_core_clk; +input nvdla_core_rstn; +input dma_wr_req_rdy; +input dma_wr_req_vld; +input dma_wr_rsp_complete; +output [1:0] sdp2glb_done_intr_pd; +input op_load; +reg [31:0] dp2reg_wdma_stall; +reg [1:0] sdp2glb_done_intr_pd; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire cfg_mode_eql; +wire cfg_mode_pdp; +wire cfg_mode_quite; +wire dp2reg_wdma_stall_dec; +wire intr0_internal; +wire intr0_wr; +wire intr1_internal; +wire intr1_wr; +wire intr_fifo_rd_pd; +wire intr_fifo_rd_prdy; +wire intr_fifo_rd_pvld; +wire intr_fifo_wr_pd; +wire intr_fifo_wr_pvld; +wire mon_intr_fifo_rd_pvld; +wire wdma_stall_cnt_cen; +wire wdma_stall_cnt_clr; +wire wdma_stall_cnt_inc; +//============================ +// CFG +//============================ +assign cfg_mode_eql = (reg2dp_ew_bypass== 1'h0 ) + & (reg2dp_ew_alu_bypass== 1'h0 ) + & (reg2dp_ew_alu_algo== 2'h3 ); +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cfg_mode_quite = cfg_mode_eql | cfg_mode_pdp; +//============== +// Interrupt +//============== +assign intr_fifo_wr_pvld = intr_req_pvld & !cfg_mode_quite; +assign intr_fifo_wr_pd = intr_req_ptr; +NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo u_NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intr_fifo_wr_pvld (intr_fifo_wr_pvld) //|< w + ,.intr_fifo_wr_pd (intr_fifo_wr_pd) //|< w + ,.intr_fifo_rd_prdy (intr_fifo_rd_prdy) //|< w + ,.intr_fifo_rd_pvld (intr_fifo_rd_pvld) //|> w + ,.intr_fifo_rd_pd (intr_fifo_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign intr_fifo_rd_prdy = dma_wr_rsp_complete; +assign intr0_internal = cfg_mode_quite & intr_req_pvld & (intr_req_ptr==0); +assign intr0_wr = dma_wr_rsp_complete & (intr_fifo_rd_pd==0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2glb_done_intr_pd[0] <= 1'b0; + end else begin + sdp2glb_done_intr_pd[0] <= intr0_wr | intr0_internal; + end +end +assign intr1_internal = cfg_mode_quite & intr_req_pvld & (intr_req_ptr==1); +assign intr1_wr = dma_wr_rsp_complete & (intr_fifo_rd_pd==1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2glb_done_intr_pd[1] <= 1'b0; + end else begin + sdp2glb_done_intr_pd[1] <= intr1_wr | intr1_internal; + end +end +assign mon_intr_fifo_rd_pvld = intr_fifo_rd_pvld; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when write complete, intr_ptr should be already in the head of intr_fifo read side") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !mon_intr_fifo_rd_pvld & intr_fifo_rd_prdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"write intr0 and eql intr0 never happen in the same layer") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, intr0_wr & intr0_internal); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"write intr1 and eql intr1 never happen in the same layer") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, intr1_wr & intr1_internal); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// PERF STATISTIC +assign wdma_stall_cnt_inc = dma_wr_req_vld & !dma_wr_req_rdy; +assign wdma_stall_cnt_clr = op_load; +assign wdma_stall_cnt_cen = reg2dp_op_en & reg2dp_perf_dma_en; + assign dp2reg_wdma_stall_dec = 1'b0; + always @( + wdma_stall_cnt_inc + or dp2reg_wdma_stall_dec + ) begin + stl_adv = wdma_stall_cnt_inc ^ dp2reg_wdma_stall_dec; + end + always @( + stl_cnt_cur + or wdma_stall_cnt_inc + or dp2reg_wdma_stall_dec + or stl_adv + or wdma_stall_cnt_clr + ) begin + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wdma_stall_cnt_inc && !dp2reg_wdma_stall_dec)? stl_cnt_inc : (!wdma_stall_cnt_inc && dp2reg_wdma_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (wdma_stall_cnt_clr)? 34'd0 : stl_cnt_new[33:0]; + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (wdma_stall_cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end + always @( + stl_cnt_cur + ) begin + dp2reg_wdma_stall[31:0] = stl_cnt_cur[31:0]; + end +endmodule // NV_NVDLA_SDP_WDMA_intr +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intr_fifo_wr_pvld + , intr_fifo_wr_pd + , intr_fifo_rd_prdy + , intr_fifo_rd_pvld + , intr_fifo_rd_pd + , pwrbus_ram_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input intr_fifo_wr_pvld; +input intr_fifo_wr_pd; +input intr_fifo_rd_prdy; +output intr_fifo_rd_pvld; +output intr_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] intr_fifo_rd_pd_p = intr_fifo_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg intr_fifo_rd_prdy_d; // intr_fifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_prdy_d <= 1'b1; + end else begin + intr_fifo_rd_prdy_d <= intr_fifo_rd_prdy; + end +end +wire intr_fifo_rd_prdy_d_o; // combinatorial rd_busy +reg intr_fifo_rd_pvld_int; // internal copy of intr_fifo_rd_pvld +assign intr_fifo_rd_pvld = intr_fifo_rd_pvld_int; +wire intr_fifo_rd_pvld_p = intr_fifo_wr_pvld ; // no real fifo, take from write-side input +reg intr_fifo_rd_pvld_int_o; // internal copy of intr_fifo_rd_pvld_o +wire intr_fifo_rd_pvld_o = intr_fifo_rd_pvld_int_o; +wire rd_popping = intr_fifo_rd_pvld_p && !(intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg intr_fifo_rd_pd_o; // output data register +wire rd_req_next_o = (intr_fifo_rd_pvld_p || (intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int_o <= 1'b0; + end else begin + intr_fifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + intr_fifo_rd_pd_o <= intr_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + intr_fifo_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg intr_fifo_rd_pd; // output data register +reg intr_fifo_rd_pvld_int_d; // so we can bubble-collapse intr_fifo_rd_prdy_d +assign intr_fifo_rd_prdy_d_o = !((intr_fifo_rd_pvld_o && intr_fifo_rd_pvld_int_d && !intr_fifo_rd_prdy_d ) ); +wire rd_req_next = (!intr_fifo_rd_prdy_d_o ? intr_fifo_rd_pvld_o : intr_fifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int <= 1'b0; + intr_fifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) begin + intr_fifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy) ) begin + end else begin + intr_fifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + intr_fifo_rd_pvld_int_d <= intr_fifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) ) begin + case (!intr_fifo_rd_prdy_d_o) + 1'b0: intr_fifo_rd_pd <= intr_fifo_rd_pd_p; + 1'b1: intr_fifo_rd_pd <= intr_fifo_rd_pd_o; +//VCS coverage off + default: intr_fifo_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy)) ) begin + end else begin + intr_fifo_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (intr_fifo_wr_pvld || (intr_fifo_rd_pvld_int && intr_fifo_rd_prdy_d) || (intr_fifo_rd_pvld_int_o && intr_fifo_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +endmodule // NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v.vcp new file mode 100644 index 0000000..54431fa --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v.vcp @@ -0,0 +1,528 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_intr.v +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_intr ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,dma_wr_req_rdy //|< i + ,dma_wr_req_vld //|< i + ,dma_wr_rsp_complete //|< i + ,intr_req_ptr //|< i + ,intr_req_pvld //|< i + ,op_load //|< i + ,pwrbus_ram_pd //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ,reg2dp_op_en //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_perf_dma_en //|< i + ,dp2reg_wdma_stall //|> o + ,sdp2glb_done_intr_pd //|> o + ); +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input reg2dp_op_en; +input reg2dp_output_dst; +input reg2dp_perf_dma_en; +output [31:0] dp2reg_wdma_stall; +input intr_req_ptr; +input intr_req_pvld; +input [31:0] pwrbus_ram_pd; +input nvdla_core_clk; +input nvdla_core_rstn; +input dma_wr_req_rdy; +input dma_wr_req_vld; +input dma_wr_rsp_complete; +output [1:0] sdp2glb_done_intr_pd; +input op_load; +reg [31:0] dp2reg_wdma_stall; +reg [1:0] sdp2glb_done_intr_pd; +reg stl_adv; +reg [31:0] stl_cnt_cur; +reg [33:0] stl_cnt_dec; +reg [33:0] stl_cnt_ext; +reg [33:0] stl_cnt_inc; +reg [33:0] stl_cnt_mod; +reg [33:0] stl_cnt_new; +reg [33:0] stl_cnt_nxt; +wire cfg_mode_eql; +wire cfg_mode_pdp; +wire cfg_mode_quite; +wire dp2reg_wdma_stall_dec; +wire intr0_internal; +wire intr0_wr; +wire intr1_internal; +wire intr1_wr; +wire intr_fifo_rd_pd; +wire intr_fifo_rd_prdy; +wire intr_fifo_rd_pvld; +wire intr_fifo_wr_pd; +wire intr_fifo_wr_pvld; +wire mon_intr_fifo_rd_pvld; +wire wdma_stall_cnt_cen; +wire wdma_stall_cnt_clr; +wire wdma_stall_cnt_inc; +//============================ +// CFG +//============================ +assign cfg_mode_eql = (reg2dp_ew_bypass== 1'h0 ) + & (reg2dp_ew_alu_bypass== 1'h0 ) + & (reg2dp_ew_alu_algo== 2'h3 ); +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cfg_mode_quite = cfg_mode_eql | cfg_mode_pdp; +//============== +// Interrupt +//============== +assign intr_fifo_wr_pvld = intr_req_pvld & !cfg_mode_quite; +assign intr_fifo_wr_pd = intr_req_ptr; +NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo u_NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.intr_fifo_wr_pvld (intr_fifo_wr_pvld) //|< w + ,.intr_fifo_wr_pd (intr_fifo_wr_pd) //|< w + ,.intr_fifo_rd_prdy (intr_fifo_rd_prdy) //|< w + ,.intr_fifo_rd_pvld (intr_fifo_rd_pvld) //|> w + ,.intr_fifo_rd_pd (intr_fifo_rd_pd) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +assign intr_fifo_rd_prdy = dma_wr_rsp_complete; +assign intr0_internal = cfg_mode_quite & intr_req_pvld & (intr_req_ptr==0); +assign intr0_wr = dma_wr_rsp_complete & (intr_fifo_rd_pd==0); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2glb_done_intr_pd[0] <= 1'b0; + end else begin + sdp2glb_done_intr_pd[0] <= intr0_wr | intr0_internal; + end +end +assign intr1_internal = cfg_mode_quite & intr_req_pvld & (intr_req_ptr==1); +assign intr1_wr = dma_wr_rsp_complete & (intr_fifo_rd_pd==1); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2glb_done_intr_pd[1] <= 1'b0; + end else begin + sdp2glb_done_intr_pd[1] <= intr1_wr | intr1_internal; + end +end +assign mon_intr_fifo_rd_pvld = intr_fifo_rd_pvld; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"when write complete, intr_ptr should be already in the head of intr_fifo read side") zzz_assert_never_1x (nvdla_core_clk, `ASSERT_RESET, !mon_intr_fifo_rd_pvld & intr_fifo_rd_prdy); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"write intr0 and eql intr0 never happen in the same layer") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, intr0_wr & intr0_internal); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"write intr1 and eql intr1 never happen in the same layer") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, intr1_wr & intr1_internal); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//============== +// PERF STATISTIC +assign wdma_stall_cnt_inc = dma_wr_req_vld & !dma_wr_req_rdy; +assign wdma_stall_cnt_clr = op_load; +assign wdma_stall_cnt_cen = reg2dp_op_en & reg2dp_perf_dma_en; + assign dp2reg_wdma_stall_dec = 1'b0; + always @( + wdma_stall_cnt_inc + or dp2reg_wdma_stall_dec + ) begin + stl_adv = wdma_stall_cnt_inc ^ dp2reg_wdma_stall_dec; + end + always @( + stl_cnt_cur + or wdma_stall_cnt_inc + or dp2reg_wdma_stall_dec + or stl_adv + or wdma_stall_cnt_clr + ) begin + stl_cnt_ext[33:0] = {1'b0, 1'b0, stl_cnt_cur}; + stl_cnt_inc[33:0] = stl_cnt_cur + 1'b1; // spyglass disable W164b + stl_cnt_dec[33:0] = stl_cnt_cur - 1'b1; // spyglass disable W164b + stl_cnt_mod[33:0] = (wdma_stall_cnt_inc && !dp2reg_wdma_stall_dec)? stl_cnt_inc : (!wdma_stall_cnt_inc && dp2reg_wdma_stall_dec)? stl_cnt_dec : stl_cnt_ext; + stl_cnt_new[33:0] = (stl_adv)? stl_cnt_mod[33:0] : stl_cnt_ext[33:0]; + stl_cnt_nxt[33:0] = (wdma_stall_cnt_clr)? 34'd0 : stl_cnt_new[33:0]; + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + stl_cnt_cur[31:0] <= 0; + end else begin + if (wdma_stall_cnt_cen) begin + stl_cnt_cur[31:0] <= stl_cnt_nxt[31:0]; + end + end + end + always @( + stl_cnt_cur + ) begin + dp2reg_wdma_stall[31:0] = stl_cnt_cur[31:0]; + end +endmodule // NV_NVDLA_SDP_WDMA_intr +`define FORCE_CONTENTION_ASSERTION_RESET_ACTIVE 1'b1 +`include "simulate_x_tick.vh" +module NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo ( + nvdla_core_clk + , nvdla_core_rstn + , intr_fifo_wr_pvld + , intr_fifo_wr_pd + , intr_fifo_rd_prdy + , intr_fifo_rd_pvld + , intr_fifo_rd_pd + , pwrbus_ram_pd + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input intr_fifo_wr_pvld; +input intr_fifo_wr_pd; +input intr_fifo_rd_prdy; +output intr_fifo_rd_pvld; +output intr_fifo_rd_pd; +input [31:0] pwrbus_ram_pd; +// Master Clock Gating (SLCG) +// +// We gate the clock(s) when idle or stalled. +// This allows us to turn off numerous miscellaneous flops +// that don't get gated during synthesis for one reason or another. +// +// We gate write side and read side separately. +// If the fifo is synchronous, we also gate the ram separately, but if +// -master_clk_gated_unified or -status_reg/-status_logic_reg is specified, +// then we use one clk gate for write, ram, and read. +// +wire nvdla_core_clk_mgated_enable; // assigned by code at end of this module +wire nvdla_core_clk_mgated; // used only in synchronous fifos +NV_CLK_gate_power nvdla_core_clk_mgate( .clk(nvdla_core_clk), .reset_(nvdla_core_rstn), .clk_en(nvdla_core_clk_mgated_enable), .clk_gated(nvdla_core_clk_mgated) ); +// +// WRITE SIDE +// +// +// NOTE: 0-depth fifo has no write side +// +// +// RAM +// +// +// NOTE: 0-depth fifo has no ram. +// +wire [0:0] intr_fifo_rd_pd_p = intr_fifo_wr_pd; +// +// SYNCHRONOUS BOUNDARY +// +// +// NOTE: 0-depth fifo has no real boundary between write and read sides +// +// +// READ SIDE +// +reg intr_fifo_rd_prdy_d; // intr_fifo_rd_prdy registered in cleanly +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_prdy_d <= 1'b1; + end else begin + intr_fifo_rd_prdy_d <= intr_fifo_rd_prdy; + end +end +wire intr_fifo_rd_prdy_d_o; // combinatorial rd_busy +reg intr_fifo_rd_pvld_int; // internal copy of intr_fifo_rd_pvld +assign intr_fifo_rd_pvld = intr_fifo_rd_pvld_int; +wire intr_fifo_rd_pvld_p = intr_fifo_wr_pvld ; // no real fifo, take from write-side input +reg intr_fifo_rd_pvld_int_o; // internal copy of intr_fifo_rd_pvld_o +wire intr_fifo_rd_pvld_o = intr_fifo_rd_pvld_int_o; +wire rd_popping = intr_fifo_rd_pvld_p && !(intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o); +// +// SKID for -rd_busy_reg +// +reg intr_fifo_rd_pd_o; // output data register +wire rd_req_next_o = (intr_fifo_rd_pvld_p || (intr_fifo_rd_pvld_int_o && !intr_fifo_rd_prdy_d_o)) ; +always @( posedge nvdla_core_clk_mgated or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int_o <= 1'b0; + end else begin + intr_fifo_rd_pvld_int_o <= rd_req_next_o; + end +end +always @( posedge nvdla_core_clk_mgated ) begin + if ( (intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping) ) begin + intr_fifo_rd_pd_o <= intr_fifo_rd_pd_p; + end +//synopsys translate_off + else if ( !((intr_fifo_rd_pvld_int && rd_req_next_o && rd_popping)) ) begin + end else begin + intr_fifo_rd_pd_o <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// +// FINAL OUTPUT +// +reg intr_fifo_rd_pd; // output data register +reg intr_fifo_rd_pvld_int_d; // so we can bubble-collapse intr_fifo_rd_prdy_d +assign intr_fifo_rd_prdy_d_o = !((intr_fifo_rd_pvld_o && intr_fifo_rd_pvld_int_d && !intr_fifo_rd_prdy_d ) ); +wire rd_req_next = (!intr_fifo_rd_prdy_d_o ? intr_fifo_rd_pvld_o : intr_fifo_rd_pvld_p) ; +always @( posedge nvdla_core_clk or negedge nvdla_core_rstn ) begin + if ( !nvdla_core_rstn ) begin + intr_fifo_rd_pvld_int <= 1'b0; + intr_fifo_rd_pvld_int_d <= 1'b0; + end else begin + if ( !intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) begin + intr_fifo_rd_pvld_int <= rd_req_next; + end +//synopsys translate_off + else if ( !(!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy) ) begin + end else begin + intr_fifo_rd_pvld_int <= `x_or_0; + end +//synopsys translate_on + intr_fifo_rd_pvld_int_d <= intr_fifo_rd_pvld_int; + end +end +always @( posedge nvdla_core_clk ) begin + if ( rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy ) ) begin + case (!intr_fifo_rd_prdy_d_o) + 1'b0: intr_fifo_rd_pd <= intr_fifo_rd_pd_p; + 1'b1: intr_fifo_rd_pd <= intr_fifo_rd_pd_o; +//VCS coverage off + default: intr_fifo_rd_pd <= {1{`x_or_0}}; +//VCS coverage on + endcase + end +//synopsys translate_off + else if ( !(rd_req_next && (!intr_fifo_rd_pvld_int || intr_fifo_rd_prdy)) ) begin + end else begin + intr_fifo_rd_pd <= {1{`x_or_0}}; + end +//synopsys translate_on +end +// Tie-offs for pwrbus_ram_pd +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_0 (.A(pwrbus_ram_pd[0])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_1 (.A(pwrbus_ram_pd[1])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_2 (.A(pwrbus_ram_pd[2])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_3 (.A(pwrbus_ram_pd[3])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_4 (.A(pwrbus_ram_pd[4])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_5 (.A(pwrbus_ram_pd[5])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_6 (.A(pwrbus_ram_pd[6])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_7 (.A(pwrbus_ram_pd[7])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_8 (.A(pwrbus_ram_pd[8])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +// Master Clock Gating (SLCG) Enables +// +// plusarg for disabling this stuff: +// synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +reg master_clk_gating_disabled; initial master_clk_gating_disabled = $test$plusargs( "fifogen_disable_master_clk_gating" ) != 0; +`endif +`endif +// synopsys translate_on +assign nvdla_core_clk_mgated_enable = ((1'b0) || (intr_fifo_wr_pvld || (intr_fifo_rd_pvld_int && intr_fifo_rd_prdy_d) || (intr_fifo_rd_pvld_int_o && intr_fifo_rd_prdy_d_o))) + `ifdef FIFOGEN_MASTER_CLK_GATING_DISABLED + || 1'b1 + `endif +// synopsys translate_off + `ifndef SYNTH_LEVEL1_COMPILE + `ifndef SYNTHESIS + || master_clk_gating_disabled + `endif + `endif +// synopsys translate_on + ; +// spyglass disable_block W164a W164b W116 W484 W504 +`ifdef SPYGLASS +`else +`ifdef FV_ASSERT_ON +`else +// synopsys translate_off +`endif +`ifdef ASSERT_ON +`ifdef SPYGLASS +wire disable_assert_plusarg = 1'b0; +`else +`ifdef FV_ASSERT_ON +wire disable_assert_plusarg = 1'b0; +`else +wire disable_assert_plusarg = $test$plusargs("DISABLE_NESS_FLOW_ASSERTIONS"); +`endif +`endif +wire assert_enabled = 1'b1 && !disable_assert_plusarg; +`endif +`ifdef FV_ASSERT_ON +`else +// synopsys translate_on +`endif +`ifdef ASSERT_ON +//synopsys translate_off +`ifndef SYNTH_LEVEL1_COMPILE +`ifndef SYNTHESIS +always @(assert_enabled) begin + if ( assert_enabled === 1'b0 ) begin + $display("Asserts are disabled for %m"); + end +end +`endif +`endif +//synopsys translate_on +`endif +`endif +// spyglass enable_block W164a W164b W116 W484 W504 +//The NV_BLKBOX_SRC0 module is only present when the FIFOGEN_MODULE_SEARCH +// define is set. This is to aid fifogen team search for fifogen fifo +// instance and module names in a given design. +`ifdef FIFOGEN_MODULE_SEARCH +NV_BLKBOX_SRC0 dummy_breadcrumb_fifogen_blkbox (.Y()); +`endif +endmodule // NV_NVDLA_SDP_WDMA_DAT_DMAIF_intr_fifo diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_unpack.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_unpack.v new file mode 100644 index 0000000..1d28cb3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_unpack.v @@ -0,0 +1,147 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_unpack.v +module NV_NVDLA_SDP_WDMA_unpack ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_dp_8 + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 256; +parameter IHW = IW/2; +parameter OW = 256; +parameter RATIO = OW/IW; +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_dp_8; +input inp_pvld; +output inp_prdy; +input [IW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW-1:0] out_data; +reg [3:0] pack_cnt; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire is_pack_last; +reg [IW-1:0] pack_seg0; +reg [IW-1:0] pack_seg1; +reg [IW-1:0] pack_seg2; +reg [IW-1:0] pack_seg3; +reg [IW-1:0] pack_seg4; +reg [IW-1:0] pack_seg5; +reg [IW-1:0] pack_seg6; +reg [IW-1:0] pack_seg7; +reg [IW-1:0] pack_seg8; +reg [IW-1:0] pack_seg9; +reg [IW-1:0] pack_sega; +reg [IW-1:0] pack_segb; +reg [IW-1:0] pack_segc; +reg [IW-1:0] pack_segd; +reg [IW-1:0] pack_sege; +reg [IW-1:0] pack_segf; +wire [8*IW-1:0] pack_total_8; +wire [8*IW-1:0] pack_total_16; +wire [8*IW-1:0] pack_total; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | pack_prdy ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_pvld <= 1'b0; + end + else if ((inp_prdy) == 1'b1) begin + pack_pvld <= inp_pvld & is_pack_last; + end +end +assign inp_acc = inp_pvld & inp_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_cnt <= {4{1'b0}}; + end else begin + if (inp_acc) begin + if (is_pack_last) begin + pack_cnt <= 0; + end else begin + pack_cnt <= pack_cnt + 1; + end + end + end +end +assign is_pack_last = cfg_dp_8 ? (pack_cnt==2*RATIO-1) : (pack_cnt==RATIO-1); +generate +if(RATIO == 1) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + end +end +end +else if(RATIO == 2) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + end +end +end +else if (RATIO == 4) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + end +end +end +else if (RATIO == 8) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + if (pack_cnt==4'h8) pack_seg8 <= inp_data; + if (pack_cnt==4'h9) pack_seg9 <= inp_data; + if (pack_cnt==4'ha) pack_sega <= inp_data; + if (pack_cnt==4'hb) pack_segb <= inp_data; + if (pack_cnt==4'hc) pack_segc <= inp_data; + if (pack_cnt==4'hd) pack_segd <= inp_data; + if (pack_cnt==4'he) pack_sege <= inp_data; + if (pack_cnt==4'hf) pack_segf <= inp_data; + end +end +end +endgenerate +assign pack_total_8 = {pack_segf[IHW-1:0], pack_sege[IHW-1:0], pack_segd[IHW-1:0], pack_segc[IHW-1:0], + pack_segb[IHW-1:0], pack_sega[IHW-1:0], pack_seg9[IHW-1:0], pack_seg8[IHW-1:0], + pack_seg7[IHW-1:0], pack_seg6[IHW-1:0], pack_seg5[IHW-1:0], pack_seg4[IHW-1:0], + pack_seg3[IHW-1:0], pack_seg2[IHW-1:0], pack_seg1[IHW-1:0], pack_seg0[IHW-1:0]}; +assign pack_total_16 = {pack_seg7 , pack_seg6 , pack_seg5 , pack_seg4, + pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +assign pack_total = cfg_dp_8 ? pack_total_8 : pack_total_16; +assign out_data = pack_total[OW-1:0]; +endmodule // NV_NVDLA_SDP_WDMA_unpack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_unpack.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_unpack.v.vcp new file mode 100644 index 0000000..1d28cb3 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_unpack.v.vcp @@ -0,0 +1,147 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_WDMA_unpack.v +module NV_NVDLA_SDP_WDMA_unpack ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_dp_8 + ,inp_pvld + ,inp_data + ,inp_prdy + ,out_pvld + ,out_data + ,out_prdy +); +parameter IW = 256; +parameter IHW = IW/2; +parameter OW = 256; +parameter RATIO = OW/IW; +input nvdla_core_clk; +input nvdla_core_rstn; +input cfg_dp_8; +input inp_pvld; +output inp_prdy; +input [IW-1:0] inp_data; +output out_pvld; +input out_prdy; +output [OW-1:0] out_data; +reg [3:0] pack_cnt; +reg pack_pvld; +wire pack_prdy; +wire inp_acc; +wire is_pack_last; +reg [IW-1:0] pack_seg0; +reg [IW-1:0] pack_seg1; +reg [IW-1:0] pack_seg2; +reg [IW-1:0] pack_seg3; +reg [IW-1:0] pack_seg4; +reg [IW-1:0] pack_seg5; +reg [IW-1:0] pack_seg6; +reg [IW-1:0] pack_seg7; +reg [IW-1:0] pack_seg8; +reg [IW-1:0] pack_seg9; +reg [IW-1:0] pack_sega; +reg [IW-1:0] pack_segb; +reg [IW-1:0] pack_segc; +reg [IW-1:0] pack_segd; +reg [IW-1:0] pack_sege; +reg [IW-1:0] pack_segf; +wire [8*IW-1:0] pack_total_8; +wire [8*IW-1:0] pack_total_16; +wire [8*IW-1:0] pack_total; +assign pack_prdy = out_prdy; +assign out_pvld = pack_pvld; +assign inp_prdy = (!pack_pvld) | pack_prdy ; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_pvld <= 1'b0; + end + else if ((inp_prdy) == 1'b1) begin + pack_pvld <= inp_pvld & is_pack_last; + end +end +assign inp_acc = inp_pvld & inp_prdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pack_cnt <= {4{1'b0}}; + end else begin + if (inp_acc) begin + if (is_pack_last) begin + pack_cnt <= 0; + end else begin + pack_cnt <= pack_cnt + 1; + end + end + end +end +assign is_pack_last = cfg_dp_8 ? (pack_cnt==2*RATIO-1) : (pack_cnt==RATIO-1); +generate +if(RATIO == 1) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + end +end +end +else if(RATIO == 2) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + end +end +end +else if (RATIO == 4) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + end +end +end +else if (RATIO == 8) begin +always @(posedge nvdla_core_clk) begin + if (inp_acc) begin + if (pack_cnt==4'h0) pack_seg0 <= inp_data; + if (pack_cnt==4'h1) pack_seg1 <= inp_data; + if (pack_cnt==4'h2) pack_seg2 <= inp_data; + if (pack_cnt==4'h3) pack_seg3 <= inp_data; + if (pack_cnt==4'h4) pack_seg4 <= inp_data; + if (pack_cnt==4'h5) pack_seg5 <= inp_data; + if (pack_cnt==4'h6) pack_seg6 <= inp_data; + if (pack_cnt==4'h7) pack_seg7 <= inp_data; + if (pack_cnt==4'h8) pack_seg8 <= inp_data; + if (pack_cnt==4'h9) pack_seg9 <= inp_data; + if (pack_cnt==4'ha) pack_sega <= inp_data; + if (pack_cnt==4'hb) pack_segb <= inp_data; + if (pack_cnt==4'hc) pack_segc <= inp_data; + if (pack_cnt==4'hd) pack_segd <= inp_data; + if (pack_cnt==4'he) pack_sege <= inp_data; + if (pack_cnt==4'hf) pack_segf <= inp_data; + end +end +end +endgenerate +assign pack_total_8 = {pack_segf[IHW-1:0], pack_sege[IHW-1:0], pack_segd[IHW-1:0], pack_segc[IHW-1:0], + pack_segb[IHW-1:0], pack_sega[IHW-1:0], pack_seg9[IHW-1:0], pack_seg8[IHW-1:0], + pack_seg7[IHW-1:0], pack_seg6[IHW-1:0], pack_seg5[IHW-1:0], pack_seg4[IHW-1:0], + pack_seg3[IHW-1:0], pack_seg2[IHW-1:0], pack_seg1[IHW-1:0], pack_seg0[IHW-1:0]}; +assign pack_total_16 = {pack_seg7 , pack_seg6 , pack_seg5 , pack_seg4, + pack_seg3 , pack_seg2 , pack_seg1 , pack_seg0}; +assign pack_total = cfg_dp_8 ? pack_total_8 : pack_total_16; +assign out_data = pack_total[OW-1:0]; +endmodule // NV_NVDLA_SDP_WDMA_unpack diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v new file mode 100644 index 0000000..6ace1c8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v @@ -0,0 +1,244 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_brdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_brdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,brdma_disable //|< i + ,brdma_slcg_op_en //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,reg2dp_brdma_data_mode //|< i + ,reg2dp_brdma_data_size //|< i + ,reg2dp_brdma_data_use //|< i + ,reg2dp_brdma_ram_type //|< i + ,reg2dp_bs_base_addr_high //|< i + ,reg2dp_bs_base_addr_low //|< i + ,reg2dp_bs_line_stride //|< i + ,reg2dp_bs_surface_stride //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_winograd //|< i + ,dp2reg_brdma_stall //|> o + ,dp2reg_done //|> o + ,sdp_brdma2dp_alu_ready //|< i + ,sdp_brdma2dp_mul_ready //|< i + ,sdp_brdma2dp_alu_pd //|> o + ,sdp_brdma2dp_alu_valid //|> o + ,sdp_brdma2dp_mul_pd //|> o + ,sdp_brdma2dp_mul_valid //|> o + ); +// +// NV_NVDLA_SDP_brdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + output sdp_b2mcif_rd_req_valid; + input sdp_b2mcif_rd_req_ready; + output [47 -1:0] sdp_b2mcif_rd_req_pd; + input mcif2sdp_b_rd_rsp_valid; + output mcif2sdp_b_rd_rsp_ready; + input [65 -1:0] mcif2sdp_b_rd_rsp_pd; + output sdp_b2mcif_rd_cdt_lat_fifo_pop; + output sdp_brdma2dp_alu_valid; + input sdp_brdma2dp_alu_ready; + output [8*16:0] sdp_brdma2dp_alu_pd; + output sdp_brdma2dp_mul_valid; + input sdp_brdma2dp_mul_ready; + output [8*16:0] sdp_brdma2dp_mul_pd; + input reg2dp_brdma_data_mode; + input reg2dp_brdma_data_size; + input [1:0] reg2dp_brdma_data_use; + input reg2dp_brdma_ram_type; + input [31:0] reg2dp_bs_base_addr_high; + input [31-3:0] reg2dp_bs_base_addr_low; + input [31-3:0] reg2dp_bs_line_stride; + input [31-3:0] reg2dp_bs_surface_stride; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input reg2dp_op_en; + input [1:0] reg2dp_out_precision; + input reg2dp_perf_dma_en; + input [1:0] reg2dp_proc_precision; + input [12:0] reg2dp_width; + input reg2dp_winograd; + output [31:0] dp2reg_brdma_stall; + output dp2reg_done; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input brdma_slcg_op_en; + input brdma_disable; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + reg layer_process; + wire [15:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire [15:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; + wire [65 -1:0] lat_fifo_rd_pd; + wire lat_fifo_rd_pvld; + wire lat_fifo_rd_prdy; +// Layer Switch +assign op_load = reg2dp_op_en & !layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= +NV_NVDLA_SDP_BRDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.brdma_disable (brdma_disable) //|< i + ,.brdma_slcg_op_en (brdma_slcg_op_en) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_RDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_brdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_brdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_brdma_data_use[1:0]) //|< i + ,.reg2dp_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|< i + ,.reg2dp_base_addr_low (reg2dp_bs_base_addr_low[31-3:0]) //|< i + ,.reg2dp_line_stride (reg2dp_bs_line_stride[31-3:0]) //|< i + ,.reg2dp_surface_stride (reg2dp_bs_surface_stride[31-3:0]) //|< i + ,.dp2reg_rdma_stall (dp2reg_brdma_stall[31:0]) //|> o + ); +NV_NVDLA_SDP_BRDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|> w + ); +NV_NVDLA_SDP_RDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.lat_fifo_rd_pd (lat_fifo_rd_pd[65 -1:0]) //|< w + ,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w + ,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w + ,.sdp_rdma2dp_alu_ready (sdp_brdma2dp_alu_ready) //|< i + ,.sdp_rdma2dp_mul_ready (sdp_brdma2dp_mul_ready) //|< i + ,.sdp_rdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_alu_valid (sdp_brdma2dp_alu_valid) //|> o + ,.sdp_rdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_mul_valid (sdp_brdma2dp_mul_valid) //|> o + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_brdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_brdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_brdma_data_use[1:0]) //|< i + ); +NV_NVDLA_SDP_BRDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_fifo_rd_prdy) + ,.lat_rd_pvld (lat_fifo_rd_pvld) + ,.lat_rd_pd (lat_fifo_rd_pd[65 -1:0]) + ); +NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|> o + ,.dma_rd_req_ram_type (reg2dp_brdma_ram_type) //|< w + ,.dma_rd_rsp_ram_type (reg2dp_brdma_ram_type) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ); +endmodule // NV_NVDLA_SDP_brdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v.vcp new file mode 100644 index 0000000..6ace1c8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_brdma.v.vcp @@ -0,0 +1,244 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_brdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_brdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,brdma_disable //|< i + ,brdma_slcg_op_en //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,reg2dp_brdma_data_mode //|< i + ,reg2dp_brdma_data_size //|< i + ,reg2dp_brdma_data_use //|< i + ,reg2dp_brdma_ram_type //|< i + ,reg2dp_bs_base_addr_high //|< i + ,reg2dp_bs_base_addr_low //|< i + ,reg2dp_bs_line_stride //|< i + ,reg2dp_bs_surface_stride //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_winograd //|< i + ,dp2reg_brdma_stall //|> o + ,dp2reg_done //|> o + ,sdp_brdma2dp_alu_ready //|< i + ,sdp_brdma2dp_mul_ready //|< i + ,sdp_brdma2dp_alu_pd //|> o + ,sdp_brdma2dp_alu_valid //|> o + ,sdp_brdma2dp_mul_pd //|> o + ,sdp_brdma2dp_mul_valid //|> o + ); +// +// NV_NVDLA_SDP_brdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + output sdp_b2mcif_rd_req_valid; + input sdp_b2mcif_rd_req_ready; + output [47 -1:0] sdp_b2mcif_rd_req_pd; + input mcif2sdp_b_rd_rsp_valid; + output mcif2sdp_b_rd_rsp_ready; + input [65 -1:0] mcif2sdp_b_rd_rsp_pd; + output sdp_b2mcif_rd_cdt_lat_fifo_pop; + output sdp_brdma2dp_alu_valid; + input sdp_brdma2dp_alu_ready; + output [8*16:0] sdp_brdma2dp_alu_pd; + output sdp_brdma2dp_mul_valid; + input sdp_brdma2dp_mul_ready; + output [8*16:0] sdp_brdma2dp_mul_pd; + input reg2dp_brdma_data_mode; + input reg2dp_brdma_data_size; + input [1:0] reg2dp_brdma_data_use; + input reg2dp_brdma_ram_type; + input [31:0] reg2dp_bs_base_addr_high; + input [31-3:0] reg2dp_bs_base_addr_low; + input [31-3:0] reg2dp_bs_line_stride; + input [31-3:0] reg2dp_bs_surface_stride; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input reg2dp_op_en; + input [1:0] reg2dp_out_precision; + input reg2dp_perf_dma_en; + input [1:0] reg2dp_proc_precision; + input [12:0] reg2dp_width; + input reg2dp_winograd; + output [31:0] dp2reg_brdma_stall; + output dp2reg_done; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input brdma_slcg_op_en; + input brdma_disable; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + reg layer_process; + wire [15:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire [15:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; + wire [65 -1:0] lat_fifo_rd_pd; + wire lat_fifo_rd_pvld; + wire lat_fifo_rd_prdy; +// Layer Switch +assign op_load = reg2dp_op_en & !layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= +NV_NVDLA_SDP_BRDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.brdma_disable (brdma_disable) //|< i + ,.brdma_slcg_op_en (brdma_slcg_op_en) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_RDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_brdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_brdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_brdma_data_use[1:0]) //|< i + ,.reg2dp_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|< i + ,.reg2dp_base_addr_low (reg2dp_bs_base_addr_low[31-3:0]) //|< i + ,.reg2dp_line_stride (reg2dp_bs_line_stride[31-3:0]) //|< i + ,.reg2dp_surface_stride (reg2dp_bs_surface_stride[31-3:0]) //|< i + ,.dp2reg_rdma_stall (dp2reg_brdma_stall[31:0]) //|> o + ); +NV_NVDLA_SDP_BRDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|> w + ); +NV_NVDLA_SDP_RDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.lat_fifo_rd_pd (lat_fifo_rd_pd[65 -1:0]) //|< w + ,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w + ,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w + ,.sdp_rdma2dp_alu_ready (sdp_brdma2dp_alu_ready) //|< i + ,.sdp_rdma2dp_mul_ready (sdp_brdma2dp_mul_ready) //|< i + ,.sdp_rdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_alu_valid (sdp_brdma2dp_alu_valid) //|> o + ,.sdp_rdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_mul_valid (sdp_brdma2dp_mul_valid) //|> o + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_brdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_brdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_brdma_data_use[1:0]) //|< i + ); +NV_NVDLA_SDP_BRDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_fifo_rd_prdy) + ,.lat_rd_pvld (lat_fifo_rd_pvld) + ,.lat_rd_pd (lat_fifo_rd_pd[65 -1:0]) + ); +NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|> o + ,.dma_rd_req_ram_type (reg2dp_brdma_ram_type) //|< w + ,.dma_rd_rsp_ram_type (reg2dp_brdma_ram_type) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ); +endmodule // NV_NVDLA_SDP_brdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_cmux.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_cmux.v new file mode 100644 index 0000000..885d758 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_cmux.v @@ -0,0 +1,325 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_cmux.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_cmux ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,op_en_load //|< i + ,reg2dp_flying_mode //|< i + ,reg2dp_nan_to_zero //|< i + ,reg2dp_proc_precision //|< i + ,sdp_cmux2dp_ready //|< i + ,sdp_mrdma2cmux_pd //|< i + ,sdp_mrdma2cmux_valid //|< i + ,cacc2sdp_ready //|> o + ,sdp_cmux2dp_pd //|> o + ,sdp_cmux2dp_valid //|> o + ,sdp_mrdma2cmux_ready //|> o + ); +// +// NV_NVDLA_SDP_cmux_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc2sdp_valid; /* data valid */ +output cacc2sdp_ready; /* data return handshake */ +input [32*1 +1:0] cacc2sdp_pd; +input sdp_mrdma2cmux_valid; /* data valid */ +output sdp_mrdma2cmux_ready; /* data return handshake */ +input [32*1 +1:0] sdp_mrdma2cmux_pd; +output sdp_cmux2dp_valid; +input sdp_cmux2dp_ready; +output [32*1 -1:0] sdp_cmux2dp_pd; +input reg2dp_flying_mode; +input reg2dp_nan_to_zero; +input [1:0] reg2dp_proc_precision; +input op_en_load; +reg cfg_flying_mode_on; +reg cfg_proc_precision; +reg cmux_in_en; +wire cacc_rdy; +wire cacc_vld; +wire [32*1 +1:0] cacc_pd; +wire [32*1 +1:0] cmux_pd; +wire cmux_pd_batch_end; +wire cmux_pd_layer_end; +wire cmux_pd_flush_batch_end_NC; +wire [32*1 -1:0] cmux_pd_flush_data; +wire cmux2dp_prdy; +wire cmux2dp_pvld; +wire [32*1 -1:0] cmux2dp_pd; +//======================= +// CFG +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_flying_mode_on <= 1'b0; + end else begin + cfg_flying_mode_on <= reg2dp_flying_mode == 1'h1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_proc_precision <= 1'b0; + end else begin + cfg_proc_precision <= reg2dp_proc_precision == 2'h2; + end +end +NV_NVDLA_SDP_CMUX_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2sdp_pd (cacc2sdp_pd[32*1 +1:0]) //|< i + ,.cacc2sdp_valid (cacc2sdp_valid) //|< i + ,.cacc_rdy (cacc_rdy) //|< w + ,.cacc2sdp_ready (cacc2sdp_ready) //|> o + ,.cacc_pd (cacc_pd[32*1 +1:0]) //|> w + ,.cacc_vld (cacc_vld) //|> w + ); +assign cmux2dp_pvld = cmux_in_en & ((cfg_flying_mode_on) ? cacc_vld : sdp_mrdma2cmux_valid); +assign cacc_rdy = cmux_in_en & cfg_flying_mode_on & cmux2dp_prdy; +assign sdp_mrdma2cmux_ready = cmux_in_en & (!cfg_flying_mode_on) & cmux2dp_prdy; +//=========================================== +// Layer Switch +//=========================================== +assign cmux_pd = (cfg_flying_mode_on) ? cacc_pd : sdp_mrdma2cmux_pd; +assign cmux_pd_batch_end = cmux_pd[32*1]; +assign cmux_pd_layer_end = cmux_pd[32*1 +1]; +assign cmux_pd_flush_batch_end_NC = cmux_pd_batch_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmux_in_en <= 1'b0; + end else begin + if (op_en_load) begin + cmux_in_en <= 1'b1; + end else if (cmux_pd_layer_end && cmux2dp_pvld && cmux2dp_prdy) begin + cmux_in_en <= 1'b0; + end + end +end +assign cmux2dp_pd[32*1 -1:0] = cmux_pd[32*1 -1:0]; +NV_NVDLA_SDP_CMUX_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmux2dp_pd (cmux2dp_pd[32*1 -1:0]) //|< w + ,.cmux2dp_pvld (cmux2dp_pvld) //|< w + ,.sdp_cmux2dp_ready (sdp_cmux2dp_ready) //|< i + ,.cmux2dp_prdy (cmux2dp_prdy) //|> w + ,.sdp_cmux2dp_pd (sdp_cmux2dp_pd[32*1 -1:0]) //|> o + ,.sdp_cmux2dp_valid (sdp_cmux2dp_valid) //|> o + ); +endmodule // NV_NVDLA_SDP_cmux +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cacc_pd (cacc_vld, cacc_rdy) <= cacc2sdp_pd (cacc2sdp_valid, cacc2sdp_ready) +// ************************************************************************************************************** +module NV_NVDLA_SDP_CMUX_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cacc2sdp_pd + ,cacc2sdp_valid + ,cacc2sdp_ready + ,cacc_rdy + ,cacc_pd + ,cacc_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32*1 +1:0] cacc2sdp_pd; +input cacc2sdp_valid; +output cacc2sdp_ready; +input cacc_rdy; +output cacc_vld; +output [32*1 +1:0] cacc_pd; +//: my $dw = 32*1 +2; +//: &eperl::pipe("-is -wid $dw -do cacc_pd -vo cacc_vld -ri cacc_rdy -di cacc2sdp_pd -vi cacc2sdp_valid -ro cacc2sdp_ready"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg cacc2sdp_ready; +reg skid_flop_cacc2sdp_ready; +reg skid_flop_cacc2sdp_valid; +reg [34-1:0] skid_flop_cacc2sdp_pd; +reg pipe_skid_cacc2sdp_valid; +reg [34-1:0] pipe_skid_cacc2sdp_pd; +// Wire +wire skid_cacc2sdp_valid; +wire [34-1:0] skid_cacc2sdp_pd; +wire skid_cacc2sdp_ready; +wire pipe_skid_cacc2sdp_ready; +wire cacc_vld; +wire [34-1:0] cacc_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cacc2sdp_ready <= 1'b1; + skid_flop_cacc2sdp_ready <= 1'b1; + end else begin + cacc2sdp_ready <= skid_cacc2sdp_ready; + skid_flop_cacc2sdp_ready <= skid_cacc2sdp_ready; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_cacc2sdp_valid <= 1'b0; + end else begin + if (skid_flop_cacc2sdp_ready) begin + skid_flop_cacc2sdp_valid <= cacc2sdp_valid; + end + end +end +assign skid_cacc2sdp_valid = (skid_flop_cacc2sdp_ready) ? cacc2sdp_valid : skid_flop_cacc2sdp_valid; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_cacc2sdp_ready & cacc2sdp_valid) begin + skid_flop_cacc2sdp_pd[34-1:0] <= cacc2sdp_pd[34-1:0]; + end +end +assign skid_cacc2sdp_pd[34-1:0] = (skid_flop_cacc2sdp_ready) ? cacc2sdp_pd[34-1:0] : skid_flop_cacc2sdp_pd[34-1:0]; + + +// PIPE READY +assign skid_cacc2sdp_ready = pipe_skid_cacc2sdp_ready || !pipe_skid_cacc2sdp_valid; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_cacc2sdp_valid <= 1'b0; + end else begin + if (skid_cacc2sdp_ready) begin + pipe_skid_cacc2sdp_valid <= skid_cacc2sdp_valid; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_cacc2sdp_ready && skid_cacc2sdp_valid) begin + pipe_skid_cacc2sdp_pd[34-1:0] <= skid_cacc2sdp_pd[34-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_cacc2sdp_ready = cacc_rdy; +assign cacc_vld = pipe_skid_cacc2sdp_valid; +assign cacc_pd = pipe_skid_cacc2sdp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_CMUX_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is sdp_cmux2dp_pd (sdp_cmux2dp_valid,sdp_cmux2dp_ready) <= cmux2dp_pd[511:0] (cmux2dp_pvld,cmux2dp_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_CMUX_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cmux2dp_pd + ,cmux2dp_pvld + ,cmux2dp_prdy + ,sdp_cmux2dp_ready + ,sdp_cmux2dp_pd + ,sdp_cmux2dp_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32*1 -1:0] cmux2dp_pd; +input cmux2dp_pvld; +output cmux2dp_prdy; +output [32*1 -1:0] sdp_cmux2dp_pd; +output sdp_cmux2dp_valid; +input sdp_cmux2dp_ready; +//: my $dw = 32*1; +//: &eperl::pipe("-is -wid $dw -do sdp_cmux2dp_pd -vo sdp_cmux2dp_valid -ri sdp_cmux2dp_ready -di cmux2dp_pd -vi cmux2dp_pvld -ro cmux2dp_prdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg cmux2dp_prdy; +reg skid_flop_cmux2dp_prdy; +reg skid_flop_cmux2dp_pvld; +reg [32-1:0] skid_flop_cmux2dp_pd; +reg pipe_skid_cmux2dp_pvld; +reg [32-1:0] pipe_skid_cmux2dp_pd; +// Wire +wire skid_cmux2dp_pvld; +wire [32-1:0] skid_cmux2dp_pd; +wire skid_cmux2dp_prdy; +wire pipe_skid_cmux2dp_prdy; +wire sdp_cmux2dp_valid; +wire [32-1:0] sdp_cmux2dp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmux2dp_prdy <= 1'b1; + skid_flop_cmux2dp_prdy <= 1'b1; + end else begin + cmux2dp_prdy <= skid_cmux2dp_prdy; + skid_flop_cmux2dp_prdy <= skid_cmux2dp_prdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_cmux2dp_pvld <= 1'b0; + end else begin + if (skid_flop_cmux2dp_prdy) begin + skid_flop_cmux2dp_pvld <= cmux2dp_pvld; + end + end +end +assign skid_cmux2dp_pvld = (skid_flop_cmux2dp_prdy) ? cmux2dp_pvld : skid_flop_cmux2dp_pvld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_cmux2dp_prdy & cmux2dp_pvld) begin + skid_flop_cmux2dp_pd[32-1:0] <= cmux2dp_pd[32-1:0]; + end +end +assign skid_cmux2dp_pd[32-1:0] = (skid_flop_cmux2dp_prdy) ? cmux2dp_pd[32-1:0] : skid_flop_cmux2dp_pd[32-1:0]; + + +// PIPE READY +assign skid_cmux2dp_prdy = pipe_skid_cmux2dp_prdy || !pipe_skid_cmux2dp_pvld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_cmux2dp_pvld <= 1'b0; + end else begin + if (skid_cmux2dp_prdy) begin + pipe_skid_cmux2dp_pvld <= skid_cmux2dp_pvld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_cmux2dp_prdy && skid_cmux2dp_pvld) begin + pipe_skid_cmux2dp_pd[32-1:0] <= skid_cmux2dp_pd[32-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_cmux2dp_prdy = sdp_cmux2dp_ready; +assign sdp_cmux2dp_valid = pipe_skid_cmux2dp_pvld; +assign sdp_cmux2dp_pd = pipe_skid_cmux2dp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_CMUX_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_cmux.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_cmux.v.vcp new file mode 100644 index 0000000..8434d08 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_cmux.v.vcp @@ -0,0 +1,173 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_cmux.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_cmux ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,op_en_load //|< i + ,reg2dp_flying_mode //|< i + ,reg2dp_nan_to_zero //|< i + ,reg2dp_proc_precision //|< i + ,sdp_cmux2dp_ready //|< i + ,sdp_mrdma2cmux_pd //|< i + ,sdp_mrdma2cmux_valid //|< i + ,cacc2sdp_ready //|> o + ,sdp_cmux2dp_pd //|> o + ,sdp_cmux2dp_valid //|> o + ,sdp_mrdma2cmux_ready //|> o + ); +// +// NV_NVDLA_SDP_cmux_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input cacc2sdp_valid; /* data valid */ +output cacc2sdp_ready; /* data return handshake */ +input [32*1 +1:0] cacc2sdp_pd; +input sdp_mrdma2cmux_valid; /* data valid */ +output sdp_mrdma2cmux_ready; /* data return handshake */ +input [32*1 +1:0] sdp_mrdma2cmux_pd; +output sdp_cmux2dp_valid; +input sdp_cmux2dp_ready; +output [32*1 -1:0] sdp_cmux2dp_pd; +input reg2dp_flying_mode; +input reg2dp_nan_to_zero; +input [1:0] reg2dp_proc_precision; +input op_en_load; +reg cfg_flying_mode_on; +reg cfg_proc_precision; +reg cmux_in_en; +wire cacc_rdy; +wire cacc_vld; +wire [32*1 +1:0] cacc_pd; +wire [32*1 +1:0] cmux_pd; +wire cmux_pd_batch_end; +wire cmux_pd_layer_end; +wire cmux_pd_flush_batch_end_NC; +wire [32*1 -1:0] cmux_pd_flush_data; +wire cmux2dp_prdy; +wire cmux2dp_pvld; +wire [32*1 -1:0] cmux2dp_pd; +//======================= +// CFG +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_flying_mode_on <= 1'b0; + end else begin + cfg_flying_mode_on <= reg2dp_flying_mode == 1'h1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_proc_precision <= 1'b0; + end else begin + cfg_proc_precision <= reg2dp_proc_precision == 2'h2; + end +end +NV_NVDLA_SDP_CMUX_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cacc2sdp_pd (cacc2sdp_pd[32*1 +1:0]) //|< i + ,.cacc2sdp_valid (cacc2sdp_valid) //|< i + ,.cacc_rdy (cacc_rdy) //|< w + ,.cacc2sdp_ready (cacc2sdp_ready) //|> o + ,.cacc_pd (cacc_pd[32*1 +1:0]) //|> w + ,.cacc_vld (cacc_vld) //|> w + ); +assign cmux2dp_pvld = cmux_in_en & ((cfg_flying_mode_on) ? cacc_vld : sdp_mrdma2cmux_valid); +assign cacc_rdy = cmux_in_en & cfg_flying_mode_on & cmux2dp_prdy; +assign sdp_mrdma2cmux_ready = cmux_in_en & (!cfg_flying_mode_on) & cmux2dp_prdy; +//=========================================== +// Layer Switch +//=========================================== +assign cmux_pd = (cfg_flying_mode_on) ? cacc_pd : sdp_mrdma2cmux_pd; +assign cmux_pd_batch_end = cmux_pd[32*1]; +assign cmux_pd_layer_end = cmux_pd[32*1 +1]; +assign cmux_pd_flush_batch_end_NC = cmux_pd_batch_end; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cmux_in_en <= 1'b0; + end else begin + if (op_en_load) begin + cmux_in_en <= 1'b1; + end else if (cmux_pd_layer_end && cmux2dp_pvld && cmux2dp_prdy) begin + cmux_in_en <= 1'b0; + end + end +end +assign cmux2dp_pd[32*1 -1:0] = cmux_pd[32*1 -1:0]; +NV_NVDLA_SDP_CMUX_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmux2dp_pd (cmux2dp_pd[32*1 -1:0]) //|< w + ,.cmux2dp_pvld (cmux2dp_pvld) //|< w + ,.sdp_cmux2dp_ready (sdp_cmux2dp_ready) //|< i + ,.cmux2dp_prdy (cmux2dp_prdy) //|> w + ,.sdp_cmux2dp_pd (sdp_cmux2dp_pd[32*1 -1:0]) //|> o + ,.sdp_cmux2dp_valid (sdp_cmux2dp_valid) //|> o + ); +endmodule // NV_NVDLA_SDP_cmux +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -os cacc_pd (cacc_vld, cacc_rdy) <= cacc2sdp_pd (cacc2sdp_valid, cacc2sdp_ready) +// ************************************************************************************************************** +module NV_NVDLA_SDP_CMUX_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cacc2sdp_pd + ,cacc2sdp_valid + ,cacc2sdp_ready + ,cacc_rdy + ,cacc_pd + ,cacc_vld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32*1 +1:0] cacc2sdp_pd; +input cacc2sdp_valid; +output cacc2sdp_ready; +input cacc_rdy; +output cacc_vld; +output [32*1 +1:0] cacc_pd; +//: my $dw = 32*1 +2; +//: &eperl::pipe("-is -wid $dw -do cacc_pd -vo cacc_vld -ri cacc_rdy -di cacc2sdp_pd -vi cacc2sdp_valid -ro cacc2sdp_ready"); +endmodule // NV_NVDLA_SDP_CMUX_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -is sdp_cmux2dp_pd (sdp_cmux2dp_valid,sdp_cmux2dp_ready) <= cmux2dp_pd[511:0] (cmux2dp_pvld,cmux2dp_prdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_CMUX_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cmux2dp_pd + ,cmux2dp_pvld + ,cmux2dp_prdy + ,sdp_cmux2dp_ready + ,sdp_cmux2dp_pd + ,sdp_cmux2dp_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32*1 -1:0] cmux2dp_pd; +input cmux2dp_pvld; +output cmux2dp_prdy; +output [32*1 -1:0] sdp_cmux2dp_pd; +output sdp_cmux2dp_valid; +input sdp_cmux2dp_ready; +//: my $dw = 32*1; +//: &eperl::pipe("-is -wid $dw -do sdp_cmux2dp_pd -vo sdp_cmux2dp_valid -ri sdp_cmux2dp_ready -di cmux2dp_pd -vi cmux2dp_pvld -ro cmux2dp_prdy"); +endmodule // NV_NVDLA_SDP_CMUX_pipe_p2 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_core.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_core.v new file mode 100644 index 0000000..0e87878 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_core.v @@ -0,0 +1,955 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,cacc2sdp_ready //|> o + ,dla_clk_ovr_on_sync //|< i + ,dp2reg_done //|< i + ,global_clk_ovr_on_sync //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,reg2dp_bcore_slcg_op_en //|< i + ,reg2dp_flying_mode //|< i + ,reg2dp_bn_alu_algo //|< i + ,reg2dp_bn_alu_bypass //|< i + ,reg2dp_bn_alu_operand //|< i + ,reg2dp_bn_alu_shift_value //|< i + ,reg2dp_bn_alu_src //|< i + ,reg2dp_bn_bypass //|< i + ,reg2dp_bn_mul_bypass //|< i + ,reg2dp_bn_mul_operand //|< i + ,reg2dp_bn_mul_prelu //|< i + ,reg2dp_bn_mul_shift_value //|< i + ,reg2dp_bn_mul_src //|< i + ,reg2dp_bn_relu_bypass //|< i + ,reg2dp_bs_alu_algo //|< i + ,reg2dp_bs_alu_bypass //|< i + ,reg2dp_bs_alu_operand //|< i + ,reg2dp_bs_alu_shift_value //|< i + ,reg2dp_bs_alu_src //|< i + ,reg2dp_bs_bypass //|< i + ,reg2dp_bs_mul_bypass //|< i + ,reg2dp_bs_mul_operand //|< i + ,reg2dp_bs_mul_prelu //|< i + ,reg2dp_bs_mul_shift_value //|< i + ,reg2dp_bs_mul_src //|< i + ,reg2dp_bs_relu_bypass //|< i + ,reg2dp_cvt_offset //|< i + ,reg2dp_cvt_scale //|< i + ,reg2dp_cvt_shift //|< i + ,reg2dp_ecore_slcg_op_en //|< i + ,reg2dp_nan_to_zero //|< i + ,reg2dp_ncore_slcg_op_en //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_perf_lut_en //|< i + ,reg2dp_perf_sat_en //|< i + ,reg2dp_proc_precision //|< i + ,dp2reg_out_saturation //|> o + ,sdp_brdma2dp_alu_pd //|< i + ,sdp_brdma2dp_alu_valid //|< i + ,sdp_brdma2dp_alu_ready //|> o + ,sdp_brdma2dp_mul_pd //|< i + ,sdp_brdma2dp_mul_valid //|< i + ,sdp_brdma2dp_mul_ready //|> o + ,sdp_nrdma2dp_alu_pd //|< i + ,sdp_nrdma2dp_alu_valid //|< i + ,sdp_nrdma2dp_alu_ready //|> o + ,sdp_nrdma2dp_mul_pd //|< i + ,sdp_nrdma2dp_mul_valid //|< i + ,sdp_nrdma2dp_mul_ready //|> o + ,sdp_mrdma2cmux_pd //|< i + ,sdp_mrdma2cmux_valid //|< i + ,sdp_mrdma2cmux_ready //|> o + ,sdp2pdp_pd //|> o + ,sdp2pdp_valid //|> o + ,sdp2pdp_ready //|< i + ,sdp_dp2wdma_pd //|> o + ,sdp_dp2wdma_valid //|> o + ,sdp_dp2wdma_ready //|< i + ); +// +// NV_NVDLA_SDP_core_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sdp_brdma2dp_mul_valid; +output sdp_brdma2dp_mul_ready; +input [8*16:0] sdp_brdma2dp_mul_pd; +input sdp_brdma2dp_alu_valid; +output sdp_brdma2dp_alu_ready; +input [8*16:0] sdp_brdma2dp_alu_pd; +input sdp_nrdma2dp_mul_valid; +output sdp_nrdma2dp_mul_ready; +input [8*16:0] sdp_nrdma2dp_mul_pd; +input sdp_nrdma2dp_alu_valid; +output sdp_nrdma2dp_alu_ready; +input [8*16:0] sdp_nrdma2dp_alu_pd; +output sdp_dp2wdma_valid; +input sdp_dp2wdma_ready; +output [8*8 -1:0] sdp_dp2wdma_pd; +output sdp2pdp_valid; +input sdp2pdp_ready; +output [8*1 -1:0] sdp2pdp_pd; +input [31:0] pwrbus_ram_pd; +input cacc2sdp_valid; +output cacc2sdp_ready; +input [32*1 +1:0] cacc2sdp_pd; +input sdp_mrdma2cmux_valid; +output sdp_mrdma2cmux_ready; +input [32*8 +1:0] sdp_mrdma2cmux_pd; +input reg2dp_bcore_slcg_op_en; +input reg2dp_flying_mode; +input [1:0] reg2dp_bn_alu_algo; +input reg2dp_bn_alu_bypass; +input [15:0] reg2dp_bn_alu_operand; +input [5:0] reg2dp_bn_alu_shift_value; +input reg2dp_bn_alu_src; +input reg2dp_bn_bypass; +input reg2dp_bn_mul_bypass; +input [15:0] reg2dp_bn_mul_operand; +input reg2dp_bn_mul_prelu; +input [7:0] reg2dp_bn_mul_shift_value; +input reg2dp_bn_mul_src; +input reg2dp_bn_relu_bypass; +input [1:0] reg2dp_bs_alu_algo; +input reg2dp_bs_alu_bypass; +input [15:0] reg2dp_bs_alu_operand; +input [5:0] reg2dp_bs_alu_shift_value; +input reg2dp_bs_alu_src; +input reg2dp_bs_bypass; +input reg2dp_bs_mul_bypass; +input [15:0] reg2dp_bs_mul_operand; +input reg2dp_bs_mul_prelu; +input [7:0] reg2dp_bs_mul_shift_value; +input reg2dp_bs_mul_src; +input reg2dp_bs_relu_bypass; +input [31:0] reg2dp_cvt_offset; +input [15:0] reg2dp_cvt_scale; +input [5:0] reg2dp_cvt_shift; +input reg2dp_ecore_slcg_op_en; +input reg2dp_nan_to_zero; +input reg2dp_ncore_slcg_op_en; +input reg2dp_op_en; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input reg2dp_perf_lut_en; +input reg2dp_perf_sat_en; +input [1:0] reg2dp_proc_precision; +input dp2reg_done; +output [31:0] dp2reg_out_saturation; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire bcore_slcg_en; +wire ncore_slcg_en; +wire ecore_slcg_en; +wire nvdla_gated_bcore_clk; +wire nvdla_gated_ecore_clk; +wire nvdla_gated_ncore_clk; +wire op_en_load; +reg wait_for_op_en; +reg cfg_bs_en; +reg cfg_bn_en; +reg cfg_ew_en; +reg cfg_mode_eql; +reg cfg_nan_to_zero; +reg [1:0] cfg_out_precision; +reg [1:0] cfg_proc_precision; +wire cfg_mode_pdp; +reg [31:0] cfg_cvt_offset; +reg [15:0] cfg_cvt_scale; +reg [5:0] cfg_cvt_shift; +reg [1:0] cfg_bn_alu_algo; +reg cfg_bn_alu_bypass; +reg [15:0] cfg_bn_alu_operand; +reg [5:0] cfg_bn_alu_shift_value; +reg cfg_bn_alu_src; +reg cfg_bn_mul_bypass; +reg [15:0] cfg_bn_mul_operand; +reg cfg_bn_mul_prelu; +reg [7:0] cfg_bn_mul_shift_value; +reg cfg_bn_mul_src; +reg cfg_bn_relu_bypass; +reg [1:0] cfg_bs_alu_algo; +reg cfg_bs_alu_bypass; +reg [15:0] cfg_bs_alu_operand; +reg [5:0] cfg_bs_alu_shift_value; +reg cfg_bs_alu_src; +reg cfg_bs_mul_bypass; +reg [15:0] cfg_bs_mul_operand; +reg cfg_bs_mul_prelu; +reg [7:0] cfg_bs_mul_shift_value; +reg cfg_bs_mul_src; +reg cfg_bs_relu_bypass; +reg bn_alu_in_en; +reg bn_mul_in_en; +wire [16*1 -1:0] bn_alu_in_data; +wire bn_alu_in_layer_end; +wire [16*1:0] bn_alu_in_pd; +wire bn_alu_in_prdy; +wire bn_alu_in_pvld; +wire bn_alu_in_rdy; +wire bn_alu_in_vld; +wire [16*1 -1:0] bn_mul_in_data; +wire bn_mul_in_layer_end; +wire [16*1:0] bn_mul_in_pd; +wire bn_mul_in_prdy; +wire bn_mul_in_pvld; +wire bn_mul_in_rdy; +wire bn_mul_in_vld; +reg bs_alu_in_en; +reg bs_mul_in_en; +wire [16*1 -1:0] bs_alu_in_data; +wire bs_alu_in_layer_end; +wire [16*1:0] bs_alu_in_pd; +wire bs_alu_in_prdy; +wire bs_alu_in_pvld; +wire bs_alu_in_rdy; +wire bs_alu_in_vld; +wire [16*1 -1:0] bs_mul_in_data; +wire bs_mul_in_layer_end; +wire [16*1:0] bs_mul_in_pd; +wire bs_mul_in_prdy; +wire bs_mul_in_pvld; +wire bs_mul_in_rdy; +wire bs_mul_in_vld; +wire sdp_mrdma_data_in_valid; +wire sdp_mrdma_data_in_ready; +wire [32*1 +1:0] sdp_mrdma_data_in_pd; +wire [32*1 -1:0] sdp_cmux2dp_data; +wire [32*1 -1:0] sdp_cmux2dp_pd; +wire sdp_cmux2dp_ready; +wire sdp_cmux2dp_valid; +wire bn2ew_data_pvld; +wire bs_data_in_pvld; +wire [32*1 -1:0] bs_data_in_pd; +wire bs_data_in_prdy; +wire [32*1 -1:0] flop_bs_data_in_pd; +wire flop_bs_data_in_prdy; +wire flop_bs_data_in_pvld; +wire [32*1:0] bs_data_out_pd; +wire bs_data_out_prdy; +wire bs_data_out_pvld; +wire [32*1 -1:0] flop_bs_data_out_pd; +wire flop_bs_data_out_pvld; +wire flop_bs_data_out_prdy; +wire bs2bn_data_pvld; +wire bn_data_in_pvld; +wire bn_data_in_prdy; +wire [32*1 -1:0] bn_data_in_pd; +wire flop_bn_data_in_prdy; +wire flop_bn_data_in_pvld; +wire [32*1 -1:0] flop_bn_data_in_pd; +wire bn_data_out_prdy; +wire bn_data_out_pvld; +wire [32*1 -1:0] bn_data_out_pd; +wire flop_bn_data_out_pvld; +wire flop_bn_data_out_prdy; +wire [32*1 -1:0] flop_bn_data_out_pd; +wire ew_data_in_prdy; +wire ew_data_in_pvld; +wire [32*1 -1:0] ew_data_in_pd; +wire flop_ew_data_in_prdy; +wire flop_ew_data_in_pvld; +wire [32*0 -1:0] flop_ew_data_in_pd; +wire ew_data_out_prdy; +wire ew_data_out_pvld; +wire [32*0 -1:0] ew_data_out_pd; +wire flop_ew_data_out_prdy; +wire flop_ew_data_out_pvld; +wire [32*1 -1:0] flop_ew_data_out_pd; +wire ew2cvt_data_pvld; +wire cvt_data_in_pvld; +wire cvt_data_in_prdy; +wire [32*1 -1:0] cvt_data_in_pd; +wire [16*1 +1 -1:0] cvt_data_out_pd; +wire [16*1 -1:0] cvt_data_out_data; +wire cvt_data_out_prdy; +wire cvt_data_out_pvld; +wire [16*1 -1:0] core2wdma_pd; +wire core2wdma_rdy; +wire core2wdma_vld; +wire [8*1 -1:0] core2pdp_pd; +wire core2pdp_rdy; +wire core2pdp_vld; +wire [1 -1:0] cvt_data_out_sat; +reg [1 -1:0] saturation_bits; +reg cvt_sat_cvt_sat_adv; +reg [31:0] cvt_sat_cvt_sat_cnt_cur; +reg [33:0] cvt_sat_cvt_sat_cnt_ext; +reg [33:0] cvt_sat_cvt_sat_cnt_mod; +reg [33:0] cvt_sat_cvt_sat_cnt_new; +reg [33:0] cvt_sat_cvt_sat_cnt_nxt; +reg [31:0] cvt_saturation_cnt; +wire [5:0] i_add; +wire [0:0] i_sub; +wire [5:0] cvt_sat_add_act; +wire [5:0] cvt_sat_add_act_ext; +wire [5:0] cvt_sat_add_ext; +wire cvt_sat_add_flow; +wire cvt_sat_add_guard; +wire cvt_sat_dec; +wire cvt_sat_inc; +wire [5:0] cvt_sat_mod_ext; +wire cvt_sat_sub_act; +wire [5:0] cvt_sat_sub_act_ext; +wire [5:0] cvt_sat_sub_ext; +wire cvt_sat_sub_flow; +wire cvt_sat_sub_guard; +wire [5:0] cvt_saturation_add; +wire cvt_saturation_cen; +wire cvt_saturation_clr; +wire cvt_saturation_sub; +//=========================================== +// CFG +//=========================================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_bs_en <= 1'b0; + cfg_bn_en <= 1'b0; + cfg_ew_en <= 1'b0; + cfg_mode_eql <= 1'b0; + end else begin + cfg_bs_en <= reg2dp_bs_bypass== 1'h0 ; + cfg_bn_en <= reg2dp_bn_bypass== 1'h0 ; + cfg_ew_en <= 1'b0; + cfg_mode_eql <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_bs_alu_operand <= {16{1'b0}}; + cfg_bs_mul_operand <= {16{1'b0}}; + cfg_bs_alu_bypass <= 1'b0; + cfg_bs_alu_algo <= {2{1'b0}}; + cfg_bs_alu_src <= 1'b0; + cfg_bs_alu_shift_value <= {6{1'b0}}; + cfg_bs_mul_bypass <= 1'b0; + cfg_bs_mul_prelu <= 1'b0; + cfg_bs_mul_src <= 1'b0; + cfg_bs_mul_shift_value <= {8{1'b0}}; + cfg_bs_relu_bypass <= 1'b0; + cfg_bn_alu_operand <= {16{1'b0}}; + cfg_bn_mul_operand <= {16{1'b0}}; + cfg_bn_alu_bypass <= 1'b0; + cfg_bn_alu_algo <= {2{1'b0}}; + cfg_bn_alu_src <= 1'b0; + cfg_bn_alu_shift_value <= {6{1'b0}}; + cfg_bn_mul_bypass <= 1'b0; + cfg_bn_mul_prelu <= 1'b0; + cfg_bn_mul_src <= 1'b0; + cfg_bn_mul_shift_value <= {8{1'b0}}; + cfg_bn_relu_bypass <= 1'b0; + cfg_cvt_offset <= {32{1'b0}}; + cfg_cvt_scale <= {16{1'b0}}; + cfg_cvt_shift <= {6{1'b0}}; + cfg_proc_precision <= {2{1'b0}}; + cfg_out_precision <= {2{1'b0}}; + cfg_nan_to_zero <= 1'b0; + end else begin + if (op_en_load) begin + cfg_bs_alu_operand <= reg2dp_bs_alu_operand ; + cfg_bs_mul_operand <= reg2dp_bs_mul_operand ; + cfg_bs_alu_bypass <= reg2dp_bs_alu_bypass ; + cfg_bs_alu_algo <= reg2dp_bs_alu_algo ; + cfg_bs_alu_src <= reg2dp_bs_alu_src ; + cfg_bs_alu_shift_value <= reg2dp_bs_alu_shift_value ; + cfg_bs_mul_bypass <= reg2dp_bs_mul_bypass ; + cfg_bs_mul_prelu <= reg2dp_bs_mul_prelu ; + cfg_bs_mul_src <= reg2dp_bs_mul_src ; + cfg_bs_mul_shift_value <= reg2dp_bs_mul_shift_value ; + cfg_bs_relu_bypass <= reg2dp_bs_relu_bypass ; + cfg_bn_alu_operand <= reg2dp_bn_alu_operand ; + cfg_bn_mul_operand <= reg2dp_bn_mul_operand ; + cfg_bn_alu_bypass <= reg2dp_bn_alu_bypass ; + cfg_bn_alu_algo <= reg2dp_bn_alu_algo ; + cfg_bn_alu_src <= reg2dp_bn_alu_src ; + cfg_bn_alu_shift_value <= reg2dp_bn_alu_shift_value ; + cfg_bn_mul_bypass <= reg2dp_bn_mul_bypass ; + cfg_bn_mul_prelu <= reg2dp_bn_mul_prelu ; + cfg_bn_mul_src <= reg2dp_bn_mul_src ; + cfg_bn_mul_shift_value <= reg2dp_bn_mul_shift_value ; + cfg_bn_relu_bypass <= reg2dp_bn_relu_bypass ; + cfg_cvt_offset <= reg2dp_cvt_offset ; + cfg_cvt_scale <= reg2dp_cvt_scale ; + cfg_cvt_shift <= reg2dp_cvt_shift ; + cfg_proc_precision <= reg2dp_proc_precision ; + cfg_out_precision <= reg2dp_out_precision ; + cfg_nan_to_zero <= reg2dp_nan_to_zero ; + end + end +end +//=========================================== +// SLCG Gate +//=========================================== +assign bcore_slcg_en = cfg_bs_en & reg2dp_bcore_slcg_op_en; +assign ncore_slcg_en = cfg_bn_en & reg2dp_ncore_slcg_op_en; +assign ecore_slcg_en = (cfg_ew_en & reg2dp_ecore_slcg_op_en); +NV_NVDLA_SDP_CORE_gate u_gate ( + .bcore_slcg_en (bcore_slcg_en) //|< w + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.ecore_slcg_en (ecore_slcg_en) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.ncore_slcg_en (ncore_slcg_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_bcore_clk (nvdla_gated_bcore_clk) //|> w + ,.nvdla_gated_ecore_clk (nvdla_gated_ecore_clk) //|> w + ,.nvdla_gated_ncore_clk (nvdla_gated_ncore_clk) //|> w + ); +//=========================================================================== +// DATA PATH LOGIC +// RDMA data +//=========================================================================== +//covert mrdma data from atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(32*8),.OW(32*1),.CW(2)) u_dpin_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_mrdma2cmux_valid) + ,.inp_prdy (sdp_mrdma2cmux_ready) + ,.inp_data (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.out_pvld (sdp_mrdma_data_in_valid) + ,.out_prdy (sdp_mrdma_data_in_ready) + ,.out_data (sdp_mrdma_data_in_pd[32*1 +1:0]) + ); +//covert atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bs_mul_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_brdma2dp_mul_valid) + ,.inp_prdy (sdp_brdma2dp_mul_ready) + ,.inp_data (sdp_brdma2dp_mul_pd[8*16:0]) + ,.out_pvld (bs_mul_in_pvld) + ,.out_prdy (bs_mul_in_prdy) + ,.out_data (bs_mul_in_pd[16*1:0]) + ); +assign bs_mul_in_data[16*1 -1:0] = bs_mul_in_pd[16*1 -1:0]; +assign bs_mul_in_layer_end = bs_mul_in_pd[16*1]; +//covert atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bs_alu_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_brdma2dp_alu_valid) + ,.inp_prdy (sdp_brdma2dp_alu_ready) + ,.inp_data (sdp_brdma2dp_alu_pd[8*16:0]) + ,.out_pvld (bs_alu_in_pvld) + ,.out_prdy (bs_alu_in_prdy) + ,.out_data (bs_alu_in_pd[16*1:0]) + ); +assign bs_alu_in_data[16*1 -1:0] = bs_alu_in_pd[16*1 -1:0]; +assign bs_alu_in_layer_end = bs_alu_in_pd[16*1]; +//covert atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bn_mul_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_nrdma2dp_mul_valid) + ,.inp_prdy (sdp_nrdma2dp_mul_ready) + ,.inp_data (sdp_nrdma2dp_mul_pd[8*16:0]) + ,.out_pvld (bn_mul_in_pvld) + ,.out_prdy (bn_mul_in_prdy) + ,.out_data (bn_mul_in_pd[16*1:0]) + ); +assign bn_mul_in_data[16*1 -1:0] = bn_mul_in_pd[16*1 -1:0]; +assign bn_mul_in_layer_end = bn_mul_in_pd[16*1]; +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bn_alu_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_nrdma2dp_alu_valid) + ,.inp_prdy (sdp_nrdma2dp_alu_ready) + ,.inp_data (sdp_nrdma2dp_alu_pd[8*16:0]) + ,.out_pvld (bn_alu_in_pvld) + ,.out_prdy (bn_alu_in_prdy) + ,.out_data (bn_alu_in_pd[16*1:0]) + ); +assign bn_alu_in_data[16*1 -1:0] = bn_alu_in_pd[16*1 -1:0]; +assign bn_alu_in_layer_end = bn_alu_in_pd[16*1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wait_for_op_en <= 1'b1; + end else begin + if (dp2reg_done) begin + wait_for_op_en <= 1'b1; + end else if (reg2dp_op_en) begin + wait_for_op_en <= 1'b0; + end + end +end +assign op_en_load = wait_for_op_en & reg2dp_op_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bs_alu_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bs_alu_in_en <= 1'b0; + end else if (op_en_load) begin + bs_alu_in_en <= cfg_bs_en && (!reg2dp_bs_alu_bypass) && (reg2dp_bs_alu_src==1); + end else if (bs_alu_in_layer_end && bs_alu_in_pvld && bs_alu_in_prdy) begin + bs_alu_in_en <= 1'b0; + end + end +end +assign bs_alu_in_vld = bs_alu_in_en & bs_alu_in_pvld; +assign bs_alu_in_prdy = bs_alu_in_en & bs_alu_in_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bs_mul_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bs_mul_in_en <= 1'b0; + end else if (op_en_load) begin + bs_mul_in_en <= cfg_bs_en && (!reg2dp_bs_mul_bypass) &(reg2dp_bs_mul_src==1); + end else if (bs_mul_in_layer_end && bs_mul_in_pvld && bs_mul_in_prdy) begin + bs_mul_in_en <= 1'b0; + end + end +end +assign bs_mul_in_vld = bs_mul_in_en & bs_mul_in_pvld; +assign bs_mul_in_prdy = bs_mul_in_en & bs_mul_in_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bn_alu_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bn_alu_in_en <= 1'b0; + end else if (op_en_load) begin + bn_alu_in_en <= cfg_bn_en && (!reg2dp_bn_alu_bypass) && (reg2dp_bn_alu_src==1); + end else if (bn_alu_in_layer_end && bn_alu_in_pvld && bn_alu_in_prdy) begin + bn_alu_in_en <= 1'b0; + end + end +end +assign bn_alu_in_vld = bn_alu_in_en & bn_alu_in_pvld; +assign bn_alu_in_prdy = bn_alu_in_en & bn_alu_in_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bn_mul_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bn_mul_in_en <= 1'b0; + end else if (op_en_load) begin + bn_mul_in_en <= cfg_bn_en && (!reg2dp_bn_mul_bypass) &(reg2dp_bn_mul_src==1); + end else if (bn_mul_in_layer_end && bn_mul_in_pvld && bn_mul_in_prdy) begin + bn_mul_in_en <= 1'b0; + end + end +end +assign bn_mul_in_vld = bn_mul_in_en & bn_mul_in_pvld; +assign bn_mul_in_prdy = bn_mul_in_en & bn_mul_in_rdy; +//=========================================== +// CORE +//=========================================== +// data from MUX ? CC : MEM +NV_NVDLA_SDP_cmux u_NV_NVDLA_SDP_cmux ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd[32*1 +1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma_data_in_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma_data_in_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma_data_in_pd[32*1 +1:0]) + ,.sdp_cmux2dp_ready (sdp_cmux2dp_ready) + ,.sdp_cmux2dp_pd (sdp_cmux2dp_pd[32*1 -1:0]) + ,.sdp_cmux2dp_valid (sdp_cmux2dp_valid) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.op_en_load (op_en_load) + ); +assign sdp_cmux2dp_data[32*1 -1:0] = sdp_cmux2dp_pd[32*1 -1:0]; +// MUX to bypass CORE_x0 +assign sdp_cmux2dp_ready = cfg_bs_en ? bs_data_in_prdy : flop_bs_data_out_prdy; +assign bs_data_in_pd = sdp_cmux2dp_data; +assign bs_data_in_pvld = cfg_bs_en & sdp_cmux2dp_valid; +//covert 1 to 1 +NV_NVDLA_SDP_CORE_pack #(.IW(32*1),.OW(32*1)) u_bs_dppack ( + .nvdla_core_clk (nvdla_gated_bcore_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bs_data_in_pvld) //|< i + ,.inp_data (bs_data_in_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bs_data_in_prdy) //|> o + ,.out_pvld (flop_bs_data_in_pvld) //|> w + ,.out_data (flop_bs_data_in_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bs_data_in_prdy) //|< w + ); +NV_NVDLA_SDP_HLS_x1_int u_bs ( + .cfg_alu_algo (cfg_bs_alu_algo[1:0]) //|< r + ,.cfg_alu_bypass (cfg_bs_alu_bypass) //|< r + ,.cfg_alu_op (cfg_bs_alu_operand[15:0]) //|< r + ,.cfg_alu_shift_value (cfg_bs_alu_shift_value[5:0]) //|< r + ,.cfg_alu_src (cfg_bs_alu_src) //|< r + ,.cfg_mul_bypass (cfg_bs_mul_bypass) //|< r + ,.cfg_mul_op (cfg_bs_mul_operand[15:0]) //|< r + ,.cfg_mul_prelu (cfg_bs_mul_prelu) //|< r + ,.cfg_mul_shift_value (cfg_bs_mul_shift_value[5:0]) //|< r + ,.cfg_mul_src (cfg_bs_mul_src) //|< r + ,.cfg_relu_bypass (cfg_bs_relu_bypass) //|< r + ,.chn_alu_op (bs_alu_in_data[16*1 -1:0]) //|< w + ,.chn_alu_op_pvld (bs_alu_in_vld) //|< w + ,.chn_data_in (flop_bs_data_in_pd[32*1 -1:0]) //|< w + ,.chn_in_pvld (flop_bs_data_in_pvld) //|< w + ,.chn_mul_op (bs_mul_in_data[16*1 -1:0]) //|< w + ,.chn_mul_op_pvld (bs_mul_in_vld) //|< w + ,.chn_out_prdy (bs_data_out_prdy) //|< w + ,.chn_alu_op_prdy (bs_alu_in_rdy) //|> w + ,.chn_data_out (bs_data_out_pd[32*1 -1:0]) //|> w + ,.chn_in_prdy (flop_bs_data_in_prdy) //|> w + ,.chn_mul_op_prdy (bs_mul_in_rdy) //|> w + ,.chn_out_pvld (bs_data_out_pvld) //|> w + ,.nvdla_core_clk (nvdla_gated_bcore_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +//covert 1 to 1 +NV_NVDLA_SDP_CORE_unpack #(.IW(32*1),.OW(32*1)) u_bs_dpunpack ( + .nvdla_core_clk (nvdla_gated_bcore_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bs_data_out_pvld) //|< i + ,.inp_data (bs_data_out_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bs_data_out_prdy) //|> o + ,.out_pvld (flop_bs_data_out_pvld) //|> w + ,.out_data (flop_bs_data_out_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bs_data_out_prdy) //|< w + ); +//=========================================== +// MUX between BS and BN +//=========================================== +assign flop_bs_data_out_prdy = cfg_bn_en ? bn_data_in_prdy : flop_bn_data_out_prdy; +assign bs2bn_data_pvld = cfg_bs_en ? flop_bs_data_out_pvld : sdp_cmux2dp_valid; +assign bn_data_in_pd = cfg_bs_en ? flop_bs_data_out_pd : bs_data_in_pd; +assign bn_data_in_pvld = cfg_bn_en & bs2bn_data_pvld; +//covert 1 to 1 +NV_NVDLA_SDP_CORE_pack #(.IW(32*1),.OW(32*1)) u_bn_dppack ( + .nvdla_core_clk (nvdla_gated_ncore_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bn_data_in_pvld) //|< i + ,.inp_data (bn_data_in_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bn_data_in_prdy) //|> o + ,.out_pvld (flop_bn_data_in_pvld) //|> w + ,.out_data (flop_bn_data_in_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bn_data_in_prdy) //|< w + ); +NV_NVDLA_SDP_HLS_x2_int u_bn ( + .nvdla_core_clk (nvdla_gated_ncore_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_alu_algo (cfg_bn_alu_algo[1:0]) //|< r + ,.cfg_alu_bypass (cfg_bn_alu_bypass) //|< r + ,.cfg_alu_op (cfg_bn_alu_operand[15:0]) //|< r + ,.cfg_alu_shift_value (cfg_bn_alu_shift_value[5:0]) //|< r + ,.cfg_alu_src (cfg_bn_alu_src) //|< r + ,.cfg_mul_bypass (cfg_bn_mul_bypass) //|< r + ,.cfg_mul_op (cfg_bn_mul_operand[15:0]) //|< r + ,.cfg_mul_prelu (cfg_bn_mul_prelu) //|< r + ,.cfg_mul_shift_value (cfg_bn_mul_shift_value[5:0]) //|< r + ,.cfg_mul_src (cfg_bn_mul_src) //|< r + ,.cfg_relu_bypass (cfg_bn_relu_bypass) //|< r + ,.chn_data_in (flop_bn_data_in_pd[32*1 -1:0]) //|< w + ,.chn_in_pvld (flop_bn_data_in_pvld) //|< w + ,.chn_in_prdy (flop_bn_data_in_prdy) //|> w + ,.chn_alu_op (bn_alu_in_data[16*1 -1:0]) //|< w + ,.chn_alu_op_pvld (bn_alu_in_vld) //|< w + ,.chn_alu_op_prdy (bn_alu_in_rdy) //|> w + ,.chn_mul_op (bn_mul_in_data[16*1 -1:0]) //|< w + ,.chn_mul_op_pvld (bn_mul_in_vld) //|< w + ,.chn_mul_op_prdy (bn_mul_in_rdy) //|> w + ,.chn_out_prdy (bn_data_out_prdy) //|< w + ,.chn_data_out (bn_data_out_pd[32*1 -1:0]) //|> w + ,.chn_out_pvld (bn_data_out_pvld) //|> w + ); +//covert 1 to 1 +NV_NVDLA_SDP_CORE_unpack #(.IW(32*1),.OW(32*1)) u_bn_dpunpack ( + .nvdla_core_clk (nvdla_gated_ncore_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bn_data_out_pvld) //|< i + ,.inp_data (bn_data_out_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bn_data_out_prdy) //|> o + ,.out_pvld (flop_bn_data_out_pvld) //|> w + ,.out_data (flop_bn_data_out_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bn_data_out_prdy) //|< w + ); +//=========================================== +// MUX between BN and EW +//=========================================== +assign flop_bn_data_out_prdy = flop_ew_data_out_prdy; +assign bn2ew_data_pvld = cfg_bn_en ? flop_bn_data_out_pvld : bs2bn_data_pvld; +assign ew_data_in_pd = cfg_bn_en ? flop_bn_data_out_pd : bn_data_in_pd; +assign flop_ew_data_out_prdy = cvt_data_in_prdy; +assign cvt_data_in_pvld = bn2ew_data_pvld; +assign cvt_data_in_pd = ew_data_in_pd; +NV_NVDLA_SDP_HLS_c u_c ( + .cfg_mode_eql (cfg_mode_eql) //|< r + ,.cfg_out_precision (cfg_out_precision[1:0]) //|< r + ,.cfg_offset (cfg_cvt_offset[31:0]) //|< r + ,.cfg_scale (cfg_cvt_scale[15:0]) //|< r + ,.cfg_truncate (cfg_cvt_shift[5:0]) //|< r + ,.cvt_in_pvld (cvt_data_in_pvld) //|< w + ,.cvt_in_prdy (cvt_data_in_prdy) //|> w + ,.cvt_pd_in (cvt_data_in_pd[32*1 -1:0]) //|< w + ,.cvt_out_pvld (cvt_data_out_pvld) //|> w + ,.cvt_out_prdy (cvt_data_out_prdy) //|< w + ,.cvt_pd_out (cvt_data_out_pd[16*1 +1 -1:0]) //|> w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +assign cvt_data_out_data = cvt_data_out_pd[16*1 -1:0]; +assign cvt_data_out_sat = cvt_data_out_pd[16*1 +1 -1:16*1]; +// to (PDP | WDMA) +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cvt_data_out_prdy = core2wdma_rdy & ((!cfg_mode_pdp) || core2pdp_rdy); +assign core2wdma_vld = cvt_data_out_pvld & ( (!cfg_mode_pdp) || core2pdp_rdy); +assign core2pdp_vld = cfg_mode_pdp & cvt_data_out_pvld & core2wdma_rdy; +assign core2wdma_pd = cfg_mode_pdp ? {8*1{1'b0}} : cvt_data_out_data; +assign core2pdp_pd = cfg_mode_pdp ? cvt_data_out_data[8*1 -1:0] : {8*1{1'b0}}; +//covert 1 to atomic_m +//only int8 or int16. If support both, use NV_NVDLA_SDP_WDMA_unpack +NV_NVDLA_SDP_CORE_unpack #(.IW(8*1),.OW(8*8)) u_dpout_unpack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.inp_pvld (core2wdma_vld) + ,.inp_prdy (core2wdma_rdy) + ,.inp_data (core2wdma_pd[8*1 -1:0]) + ,.out_pvld (sdp_dp2wdma_valid) + ,.out_prdy (sdp_dp2wdma_ready) + ,.out_data (sdp_dp2wdma_pd[8*8 -1:0]) + ); +//pdp THROUGHPUT is 1 +NV_NVDLA_SDP_CORE_pipe_p11 pipe_p11 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.core2pdp_pd (core2pdp_pd[8*1 -1:0]) //|< w + ,.core2pdp_vld (core2pdp_vld) //|< w + ,.core2pdp_rdy (core2pdp_rdy) //|> w + ,.sdp2pdp_pd (sdp2pdp_pd[8*1 -1:0]) //|> o + ,.sdp2pdp_valid (sdp2pdp_valid) //|> o + ,.sdp2pdp_ready (sdp2pdp_ready) //|< i + ); +//=========================================== +// PERF STATISTIC: SATURATION +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + saturation_bits <= {1{1'b0}}; + end else begin + if (cvt_data_out_pvld & cvt_data_out_prdy) begin + saturation_bits <= cvt_data_out_sat; + end else begin + saturation_bits <= 0; + end + end +end +assign cvt_saturation_add = fun_my_bit_sum({{(32-1){1'b0}},saturation_bits}); +assign cvt_saturation_sub = 1'b0; +assign cvt_saturation_clr = op_en_load; +assign cvt_saturation_cen = reg2dp_perf_sat_en; +assign cvt_sat_add_ext = cvt_saturation_add; +assign cvt_sat_sub_ext = {{5{1'b0}}, cvt_saturation_sub}; +assign cvt_sat_inc = cvt_sat_add_ext > cvt_sat_sub_ext; +assign cvt_sat_dec = cvt_sat_add_ext < cvt_sat_sub_ext; +assign cvt_sat_mod_ext[5:0] = cvt_sat_inc ? (cvt_sat_add_ext - cvt_sat_sub_ext) : (cvt_sat_sub_ext - cvt_sat_add_ext); // spyglass disable W484 +assign cvt_sat_sub_guard = (|cvt_saturation_cnt[31:1])==1'b0; +assign cvt_sat_sub_act = cvt_saturation_cnt[0:0]; +assign cvt_sat_sub_act_ext = {{5{1'b0}}, cvt_sat_sub_act}; +assign cvt_sat_sub_flow = cvt_sat_dec & cvt_sat_sub_guard & (cvt_sat_sub_act_ext < cvt_sat_mod_ext); +assign cvt_sat_add_guard = (&cvt_saturation_cnt[31:6])==1'b1; +assign cvt_sat_add_act = cvt_saturation_cnt[5:0]; +assign cvt_sat_add_act_ext = cvt_sat_add_act; +assign cvt_sat_add_flow = cvt_sat_inc & cvt_sat_add_guard & (cvt_sat_add_act_ext + cvt_sat_mod_ext > 63 ); +assign i_add = cvt_sat_add_flow ? (63 - cvt_sat_add_act) : cvt_sat_sub_flow ? 0 : cvt_saturation_add; +assign i_sub = cvt_sat_sub_flow ? (cvt_sat_sub_act) : cvt_sat_add_flow ? 0 : cvt_saturation_sub ; +always @( + i_add + or i_sub + ) begin + cvt_sat_cvt_sat_adv = i_add[5:0] != {{5{1'b0}}, i_sub[0:0]}; +end +always @( + cvt_sat_cvt_sat_cnt_cur + or i_add + or i_sub + or cvt_sat_cvt_sat_adv + or cvt_saturation_clr + ) begin + cvt_sat_cvt_sat_cnt_ext[33:0] = {1'b0, 1'b0, cvt_sat_cvt_sat_cnt_cur}; + cvt_sat_cvt_sat_cnt_mod[33:0] = cvt_sat_cvt_sat_cnt_cur + i_add[5:0] - i_sub[0:0]; // spyglass disable W164b + cvt_sat_cvt_sat_cnt_new[33:0] = (cvt_sat_cvt_sat_adv)? cvt_sat_cvt_sat_cnt_mod[33:0] : cvt_sat_cvt_sat_cnt_ext[33:0]; + cvt_sat_cvt_sat_cnt_nxt[33:0] = (cvt_saturation_clr)? 34'd0 : cvt_sat_cvt_sat_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_sat_cvt_sat_cnt_cur[31:0] <= 0; + end else begin + if (cvt_saturation_cen) begin + cvt_sat_cvt_sat_cnt_cur[31:0] <= cvt_sat_cvt_sat_cnt_nxt[31:0]; + end + end +end +always @( + cvt_sat_cvt_sat_cnt_cur + ) begin + cvt_saturation_cnt[31:0] = cvt_sat_cvt_sat_cnt_cur[31:0]; +end +assign dp2reg_out_saturation = cvt_saturation_cnt; +function [5:0] fun_my_bit_sum; + input [31:0] idata; + reg [5:0] ocnt; + begin + ocnt = + (((( idata[0] + + idata[1] + + idata[2] ) + + ( idata[3] + + idata[4] + + idata[5] )) + + (( idata[6] + + idata[7] + + idata[8] ) + + ( idata[9] + + idata[10] + + idata[11] ))) + + ((( idata[12] + + idata[13] + + idata[14] ) + + ( idata[15] + + idata[16] + + idata[17] )) + + (( idata[18] + + idata[19] + + idata[20] ) + + ( idata[21] + + idata[22] + + idata[23] )))) + + (( idata[24] + + idata[25] + + idata[26] ) + + ( idata[27] + + idata[28] + + idata[29] )) + + ( idata[30] + + idata[31] ) ; + fun_my_bit_sum = ocnt; + end +endfunction +endmodule // NV_NVDLA_SDP_core +// ************************************************************************************************************** +// Generated by ::pipe -m -bc sdp2pdp_pd (sdp2pdp_valid,sdp2pdp_ready) <= core2pdp_pd[255:0] (core2pdp_vld,core2pdp_rdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_CORE_pipe_p11 ( + nvdla_core_clk + ,nvdla_core_rstn + ,core2pdp_pd + ,core2pdp_vld + ,sdp2pdp_ready + ,core2pdp_rdy + ,sdp2pdp_pd + ,sdp2pdp_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [8*1 -1:0] core2pdp_pd; +input core2pdp_vld; +input sdp2pdp_ready; +output core2pdp_rdy; +output [8*1 -1:0] sdp2pdp_pd; +output sdp2pdp_valid; +//: my $dw = 8*1; +//: &eperl::pipe("-is -wid $dw -do sdp2pdp_pd -vo sdp2pdp_valid -ri sdp2pdp_ready -di core2pdp_pd -vi core2pdp_vld -ro core2pdp_rdy"); +//| eperl: generated_beg (DO NOT EDIT BELOW) +// Reg +reg core2pdp_rdy; +reg skid_flop_core2pdp_rdy; +reg skid_flop_core2pdp_vld; +reg [8-1:0] skid_flop_core2pdp_pd; +reg pipe_skid_core2pdp_vld; +reg [8-1:0] pipe_skid_core2pdp_pd; +// Wire +wire skid_core2pdp_vld; +wire [8-1:0] skid_core2pdp_pd; +wire skid_core2pdp_rdy; +wire pipe_skid_core2pdp_rdy; +wire sdp2pdp_valid; +wire [8-1:0] sdp2pdp_pd; +// Code +// SKID READY +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + core2pdp_rdy <= 1'b1; + skid_flop_core2pdp_rdy <= 1'b1; + end else begin + core2pdp_rdy <= skid_core2pdp_rdy; + skid_flop_core2pdp_rdy <= skid_core2pdp_rdy; + end +end + +// SKID VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + skid_flop_core2pdp_vld <= 1'b0; + end else begin + if (skid_flop_core2pdp_rdy) begin + skid_flop_core2pdp_vld <= core2pdp_vld; + end + end +end +assign skid_core2pdp_vld = (skid_flop_core2pdp_rdy) ? core2pdp_vld : skid_flop_core2pdp_vld; + +// SKID DATA +always @(posedge nvdla_core_clk) begin + if (skid_flop_core2pdp_rdy & core2pdp_vld) begin + skid_flop_core2pdp_pd[8-1:0] <= core2pdp_pd[8-1:0]; + end +end +assign skid_core2pdp_pd[8-1:0] = (skid_flop_core2pdp_rdy) ? core2pdp_pd[8-1:0] : skid_flop_core2pdp_pd[8-1:0]; + + +// PIPE READY +assign skid_core2pdp_rdy = pipe_skid_core2pdp_rdy || !pipe_skid_core2pdp_vld; + +// PIPE VALID +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + pipe_skid_core2pdp_vld <= 1'b0; + end else begin + if (skid_core2pdp_rdy) begin + pipe_skid_core2pdp_vld <= skid_core2pdp_vld; + end + end +end + +// PIPE DATA +always @(posedge nvdla_core_clk) begin + if (skid_core2pdp_rdy && skid_core2pdp_vld) begin + pipe_skid_core2pdp_pd[8-1:0] <= skid_core2pdp_pd[8-1:0]; + end +end + + +// PIPE OUTPUT +assign pipe_skid_core2pdp_rdy = sdp2pdp_ready; +assign sdp2pdp_valid = pipe_skid_core2pdp_vld; +assign sdp2pdp_pd = pipe_skid_core2pdp_pd; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +endmodule // NV_NVDLA_SDP_CORE_pipe_p11 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_core.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_core.v.vcp new file mode 100644 index 0000000..db30dc2 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_core.v.vcp @@ -0,0 +1,879 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_core.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_core ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,cacc2sdp_ready //|> o + ,dla_clk_ovr_on_sync //|< i + ,dp2reg_done //|< i + ,global_clk_ovr_on_sync //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,reg2dp_bcore_slcg_op_en //|< i + ,reg2dp_flying_mode //|< i + ,reg2dp_bn_alu_algo //|< i + ,reg2dp_bn_alu_bypass //|< i + ,reg2dp_bn_alu_operand //|< i + ,reg2dp_bn_alu_shift_value //|< i + ,reg2dp_bn_alu_src //|< i + ,reg2dp_bn_bypass //|< i + ,reg2dp_bn_mul_bypass //|< i + ,reg2dp_bn_mul_operand //|< i + ,reg2dp_bn_mul_prelu //|< i + ,reg2dp_bn_mul_shift_value //|< i + ,reg2dp_bn_mul_src //|< i + ,reg2dp_bn_relu_bypass //|< i + ,reg2dp_bs_alu_algo //|< i + ,reg2dp_bs_alu_bypass //|< i + ,reg2dp_bs_alu_operand //|< i + ,reg2dp_bs_alu_shift_value //|< i + ,reg2dp_bs_alu_src //|< i + ,reg2dp_bs_bypass //|< i + ,reg2dp_bs_mul_bypass //|< i + ,reg2dp_bs_mul_operand //|< i + ,reg2dp_bs_mul_prelu //|< i + ,reg2dp_bs_mul_shift_value //|< i + ,reg2dp_bs_mul_src //|< i + ,reg2dp_bs_relu_bypass //|< i + ,reg2dp_cvt_offset //|< i + ,reg2dp_cvt_scale //|< i + ,reg2dp_cvt_shift //|< i + ,reg2dp_ecore_slcg_op_en //|< i + ,reg2dp_nan_to_zero //|< i + ,reg2dp_ncore_slcg_op_en //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_perf_lut_en //|< i + ,reg2dp_perf_sat_en //|< i + ,reg2dp_proc_precision //|< i + ,dp2reg_out_saturation //|> o + ,sdp_brdma2dp_alu_pd //|< i + ,sdp_brdma2dp_alu_valid //|< i + ,sdp_brdma2dp_alu_ready //|> o + ,sdp_brdma2dp_mul_pd //|< i + ,sdp_brdma2dp_mul_valid //|< i + ,sdp_brdma2dp_mul_ready //|> o + ,sdp_nrdma2dp_alu_pd //|< i + ,sdp_nrdma2dp_alu_valid //|< i + ,sdp_nrdma2dp_alu_ready //|> o + ,sdp_nrdma2dp_mul_pd //|< i + ,sdp_nrdma2dp_mul_valid //|< i + ,sdp_nrdma2dp_mul_ready //|> o + ,sdp_mrdma2cmux_pd //|< i + ,sdp_mrdma2cmux_valid //|< i + ,sdp_mrdma2cmux_ready //|> o + ,sdp2pdp_pd //|> o + ,sdp2pdp_valid //|> o + ,sdp2pdp_ready //|< i + ,sdp_dp2wdma_pd //|> o + ,sdp_dp2wdma_valid //|> o + ,sdp_dp2wdma_ready //|< i + ); +// +// NV_NVDLA_SDP_core_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input sdp_brdma2dp_mul_valid; +output sdp_brdma2dp_mul_ready; +input [8*16:0] sdp_brdma2dp_mul_pd; +input sdp_brdma2dp_alu_valid; +output sdp_brdma2dp_alu_ready; +input [8*16:0] sdp_brdma2dp_alu_pd; +input sdp_nrdma2dp_mul_valid; +output sdp_nrdma2dp_mul_ready; +input [8*16:0] sdp_nrdma2dp_mul_pd; +input sdp_nrdma2dp_alu_valid; +output sdp_nrdma2dp_alu_ready; +input [8*16:0] sdp_nrdma2dp_alu_pd; +output sdp_dp2wdma_valid; +input sdp_dp2wdma_ready; +output [8*8 -1:0] sdp_dp2wdma_pd; +output sdp2pdp_valid; +input sdp2pdp_ready; +output [8*1 -1:0] sdp2pdp_pd; +input [31:0] pwrbus_ram_pd; +input cacc2sdp_valid; +output cacc2sdp_ready; +input [32*1 +1:0] cacc2sdp_pd; +input sdp_mrdma2cmux_valid; +output sdp_mrdma2cmux_ready; +input [32*8 +1:0] sdp_mrdma2cmux_pd; +input reg2dp_bcore_slcg_op_en; +input reg2dp_flying_mode; +input [1:0] reg2dp_bn_alu_algo; +input reg2dp_bn_alu_bypass; +input [15:0] reg2dp_bn_alu_operand; +input [5:0] reg2dp_bn_alu_shift_value; +input reg2dp_bn_alu_src; +input reg2dp_bn_bypass; +input reg2dp_bn_mul_bypass; +input [15:0] reg2dp_bn_mul_operand; +input reg2dp_bn_mul_prelu; +input [7:0] reg2dp_bn_mul_shift_value; +input reg2dp_bn_mul_src; +input reg2dp_bn_relu_bypass; +input [1:0] reg2dp_bs_alu_algo; +input reg2dp_bs_alu_bypass; +input [15:0] reg2dp_bs_alu_operand; +input [5:0] reg2dp_bs_alu_shift_value; +input reg2dp_bs_alu_src; +input reg2dp_bs_bypass; +input reg2dp_bs_mul_bypass; +input [15:0] reg2dp_bs_mul_operand; +input reg2dp_bs_mul_prelu; +input [7:0] reg2dp_bs_mul_shift_value; +input reg2dp_bs_mul_src; +input reg2dp_bs_relu_bypass; +input [31:0] reg2dp_cvt_offset; +input [15:0] reg2dp_cvt_scale; +input [5:0] reg2dp_cvt_shift; +input reg2dp_ecore_slcg_op_en; +input reg2dp_nan_to_zero; +input reg2dp_ncore_slcg_op_en; +input reg2dp_op_en; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input reg2dp_perf_lut_en; +input reg2dp_perf_sat_en; +input [1:0] reg2dp_proc_precision; +input dp2reg_done; +output [31:0] dp2reg_out_saturation; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +wire bcore_slcg_en; +wire ncore_slcg_en; +wire ecore_slcg_en; +wire nvdla_gated_bcore_clk; +wire nvdla_gated_ecore_clk; +wire nvdla_gated_ncore_clk; +wire op_en_load; +reg wait_for_op_en; +reg cfg_bs_en; +reg cfg_bn_en; +reg cfg_ew_en; +reg cfg_mode_eql; +reg cfg_nan_to_zero; +reg [1:0] cfg_out_precision; +reg [1:0] cfg_proc_precision; +wire cfg_mode_pdp; +reg [31:0] cfg_cvt_offset; +reg [15:0] cfg_cvt_scale; +reg [5:0] cfg_cvt_shift; +reg [1:0] cfg_bn_alu_algo; +reg cfg_bn_alu_bypass; +reg [15:0] cfg_bn_alu_operand; +reg [5:0] cfg_bn_alu_shift_value; +reg cfg_bn_alu_src; +reg cfg_bn_mul_bypass; +reg [15:0] cfg_bn_mul_operand; +reg cfg_bn_mul_prelu; +reg [7:0] cfg_bn_mul_shift_value; +reg cfg_bn_mul_src; +reg cfg_bn_relu_bypass; +reg [1:0] cfg_bs_alu_algo; +reg cfg_bs_alu_bypass; +reg [15:0] cfg_bs_alu_operand; +reg [5:0] cfg_bs_alu_shift_value; +reg cfg_bs_alu_src; +reg cfg_bs_mul_bypass; +reg [15:0] cfg_bs_mul_operand; +reg cfg_bs_mul_prelu; +reg [7:0] cfg_bs_mul_shift_value; +reg cfg_bs_mul_src; +reg cfg_bs_relu_bypass; +reg bn_alu_in_en; +reg bn_mul_in_en; +wire [16*1 -1:0] bn_alu_in_data; +wire bn_alu_in_layer_end; +wire [16*1:0] bn_alu_in_pd; +wire bn_alu_in_prdy; +wire bn_alu_in_pvld; +wire bn_alu_in_rdy; +wire bn_alu_in_vld; +wire [16*1 -1:0] bn_mul_in_data; +wire bn_mul_in_layer_end; +wire [16*1:0] bn_mul_in_pd; +wire bn_mul_in_prdy; +wire bn_mul_in_pvld; +wire bn_mul_in_rdy; +wire bn_mul_in_vld; +reg bs_alu_in_en; +reg bs_mul_in_en; +wire [16*1 -1:0] bs_alu_in_data; +wire bs_alu_in_layer_end; +wire [16*1:0] bs_alu_in_pd; +wire bs_alu_in_prdy; +wire bs_alu_in_pvld; +wire bs_alu_in_rdy; +wire bs_alu_in_vld; +wire [16*1 -1:0] bs_mul_in_data; +wire bs_mul_in_layer_end; +wire [16*1:0] bs_mul_in_pd; +wire bs_mul_in_prdy; +wire bs_mul_in_pvld; +wire bs_mul_in_rdy; +wire bs_mul_in_vld; +wire sdp_mrdma_data_in_valid; +wire sdp_mrdma_data_in_ready; +wire [32*1 +1:0] sdp_mrdma_data_in_pd; +wire [32*1 -1:0] sdp_cmux2dp_data; +wire [32*1 -1:0] sdp_cmux2dp_pd; +wire sdp_cmux2dp_ready; +wire sdp_cmux2dp_valid; +wire bn2ew_data_pvld; +wire bs_data_in_pvld; +wire [32*1 -1:0] bs_data_in_pd; +wire bs_data_in_prdy; +wire [32*1 -1:0] flop_bs_data_in_pd; +wire flop_bs_data_in_prdy; +wire flop_bs_data_in_pvld; +wire [32*1:0] bs_data_out_pd; +wire bs_data_out_prdy; +wire bs_data_out_pvld; +wire [32*1 -1:0] flop_bs_data_out_pd; +wire flop_bs_data_out_pvld; +wire flop_bs_data_out_prdy; +wire bs2bn_data_pvld; +wire bn_data_in_pvld; +wire bn_data_in_prdy; +wire [32*1 -1:0] bn_data_in_pd; +wire flop_bn_data_in_prdy; +wire flop_bn_data_in_pvld; +wire [32*1 -1:0] flop_bn_data_in_pd; +wire bn_data_out_prdy; +wire bn_data_out_pvld; +wire [32*1 -1:0] bn_data_out_pd; +wire flop_bn_data_out_pvld; +wire flop_bn_data_out_prdy; +wire [32*1 -1:0] flop_bn_data_out_pd; +wire ew_data_in_prdy; +wire ew_data_in_pvld; +wire [32*1 -1:0] ew_data_in_pd; +wire flop_ew_data_in_prdy; +wire flop_ew_data_in_pvld; +wire [32*0 -1:0] flop_ew_data_in_pd; +wire ew_data_out_prdy; +wire ew_data_out_pvld; +wire [32*0 -1:0] ew_data_out_pd; +wire flop_ew_data_out_prdy; +wire flop_ew_data_out_pvld; +wire [32*1 -1:0] flop_ew_data_out_pd; +wire ew2cvt_data_pvld; +wire cvt_data_in_pvld; +wire cvt_data_in_prdy; +wire [32*1 -1:0] cvt_data_in_pd; +wire [16*1 +1 -1:0] cvt_data_out_pd; +wire [16*1 -1:0] cvt_data_out_data; +wire cvt_data_out_prdy; +wire cvt_data_out_pvld; +wire [16*1 -1:0] core2wdma_pd; +wire core2wdma_rdy; +wire core2wdma_vld; +wire [8*1 -1:0] core2pdp_pd; +wire core2pdp_rdy; +wire core2pdp_vld; +wire [1 -1:0] cvt_data_out_sat; +reg [1 -1:0] saturation_bits; +reg cvt_sat_cvt_sat_adv; +reg [31:0] cvt_sat_cvt_sat_cnt_cur; +reg [33:0] cvt_sat_cvt_sat_cnt_ext; +reg [33:0] cvt_sat_cvt_sat_cnt_mod; +reg [33:0] cvt_sat_cvt_sat_cnt_new; +reg [33:0] cvt_sat_cvt_sat_cnt_nxt; +reg [31:0] cvt_saturation_cnt; +wire [5:0] i_add; +wire [0:0] i_sub; +wire [5:0] cvt_sat_add_act; +wire [5:0] cvt_sat_add_act_ext; +wire [5:0] cvt_sat_add_ext; +wire cvt_sat_add_flow; +wire cvt_sat_add_guard; +wire cvt_sat_dec; +wire cvt_sat_inc; +wire [5:0] cvt_sat_mod_ext; +wire cvt_sat_sub_act; +wire [5:0] cvt_sat_sub_act_ext; +wire [5:0] cvt_sat_sub_ext; +wire cvt_sat_sub_flow; +wire cvt_sat_sub_guard; +wire [5:0] cvt_saturation_add; +wire cvt_saturation_cen; +wire cvt_saturation_clr; +wire cvt_saturation_sub; +//=========================================== +// CFG +//=========================================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_bs_en <= 1'b0; + cfg_bn_en <= 1'b0; + cfg_ew_en <= 1'b0; + cfg_mode_eql <= 1'b0; + end else begin + cfg_bs_en <= reg2dp_bs_bypass== 1'h0 ; + cfg_bn_en <= reg2dp_bn_bypass== 1'h0 ; + cfg_ew_en <= 1'b0; + cfg_mode_eql <= 1'b0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cfg_bs_alu_operand <= {16{1'b0}}; + cfg_bs_mul_operand <= {16{1'b0}}; + cfg_bs_alu_bypass <= 1'b0; + cfg_bs_alu_algo <= {2{1'b0}}; + cfg_bs_alu_src <= 1'b0; + cfg_bs_alu_shift_value <= {6{1'b0}}; + cfg_bs_mul_bypass <= 1'b0; + cfg_bs_mul_prelu <= 1'b0; + cfg_bs_mul_src <= 1'b0; + cfg_bs_mul_shift_value <= {8{1'b0}}; + cfg_bs_relu_bypass <= 1'b0; + cfg_bn_alu_operand <= {16{1'b0}}; + cfg_bn_mul_operand <= {16{1'b0}}; + cfg_bn_alu_bypass <= 1'b0; + cfg_bn_alu_algo <= {2{1'b0}}; + cfg_bn_alu_src <= 1'b0; + cfg_bn_alu_shift_value <= {6{1'b0}}; + cfg_bn_mul_bypass <= 1'b0; + cfg_bn_mul_prelu <= 1'b0; + cfg_bn_mul_src <= 1'b0; + cfg_bn_mul_shift_value <= {8{1'b0}}; + cfg_bn_relu_bypass <= 1'b0; + cfg_cvt_offset <= {32{1'b0}}; + cfg_cvt_scale <= {16{1'b0}}; + cfg_cvt_shift <= {6{1'b0}}; + cfg_proc_precision <= {2{1'b0}}; + cfg_out_precision <= {2{1'b0}}; + cfg_nan_to_zero <= 1'b0; + end else begin + if (op_en_load) begin + cfg_bs_alu_operand <= reg2dp_bs_alu_operand ; + cfg_bs_mul_operand <= reg2dp_bs_mul_operand ; + cfg_bs_alu_bypass <= reg2dp_bs_alu_bypass ; + cfg_bs_alu_algo <= reg2dp_bs_alu_algo ; + cfg_bs_alu_src <= reg2dp_bs_alu_src ; + cfg_bs_alu_shift_value <= reg2dp_bs_alu_shift_value ; + cfg_bs_mul_bypass <= reg2dp_bs_mul_bypass ; + cfg_bs_mul_prelu <= reg2dp_bs_mul_prelu ; + cfg_bs_mul_src <= reg2dp_bs_mul_src ; + cfg_bs_mul_shift_value <= reg2dp_bs_mul_shift_value ; + cfg_bs_relu_bypass <= reg2dp_bs_relu_bypass ; + cfg_bn_alu_operand <= reg2dp_bn_alu_operand ; + cfg_bn_mul_operand <= reg2dp_bn_mul_operand ; + cfg_bn_alu_bypass <= reg2dp_bn_alu_bypass ; + cfg_bn_alu_algo <= reg2dp_bn_alu_algo ; + cfg_bn_alu_src <= reg2dp_bn_alu_src ; + cfg_bn_alu_shift_value <= reg2dp_bn_alu_shift_value ; + cfg_bn_mul_bypass <= reg2dp_bn_mul_bypass ; + cfg_bn_mul_prelu <= reg2dp_bn_mul_prelu ; + cfg_bn_mul_src <= reg2dp_bn_mul_src ; + cfg_bn_mul_shift_value <= reg2dp_bn_mul_shift_value ; + cfg_bn_relu_bypass <= reg2dp_bn_relu_bypass ; + cfg_cvt_offset <= reg2dp_cvt_offset ; + cfg_cvt_scale <= reg2dp_cvt_scale ; + cfg_cvt_shift <= reg2dp_cvt_shift ; + cfg_proc_precision <= reg2dp_proc_precision ; + cfg_out_precision <= reg2dp_out_precision ; + cfg_nan_to_zero <= reg2dp_nan_to_zero ; + end + end +end +//=========================================== +// SLCG Gate +//=========================================== +assign bcore_slcg_en = cfg_bs_en & reg2dp_bcore_slcg_op_en; +assign ncore_slcg_en = cfg_bn_en & reg2dp_ncore_slcg_op_en; +assign ecore_slcg_en = (cfg_ew_en & reg2dp_ecore_slcg_op_en); +NV_NVDLA_SDP_CORE_gate u_gate ( + .bcore_slcg_en (bcore_slcg_en) //|< w + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.ecore_slcg_en (ecore_slcg_en) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.ncore_slcg_en (ncore_slcg_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_bcore_clk (nvdla_gated_bcore_clk) //|> w + ,.nvdla_gated_ecore_clk (nvdla_gated_ecore_clk) //|> w + ,.nvdla_gated_ncore_clk (nvdla_gated_ncore_clk) //|> w + ); +//=========================================================================== +// DATA PATH LOGIC +// RDMA data +//=========================================================================== +//covert mrdma data from atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(32*8),.OW(32*1),.CW(2)) u_dpin_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_mrdma2cmux_valid) + ,.inp_prdy (sdp_mrdma2cmux_ready) + ,.inp_data (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.out_pvld (sdp_mrdma_data_in_valid) + ,.out_prdy (sdp_mrdma_data_in_ready) + ,.out_data (sdp_mrdma_data_in_pd[32*1 +1:0]) + ); +//covert atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bs_mul_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_brdma2dp_mul_valid) + ,.inp_prdy (sdp_brdma2dp_mul_ready) + ,.inp_data (sdp_brdma2dp_mul_pd[8*16:0]) + ,.out_pvld (bs_mul_in_pvld) + ,.out_prdy (bs_mul_in_prdy) + ,.out_data (bs_mul_in_pd[16*1:0]) + ); +assign bs_mul_in_data[16*1 -1:0] = bs_mul_in_pd[16*1 -1:0]; +assign bs_mul_in_layer_end = bs_mul_in_pd[16*1]; +//covert atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bs_alu_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_brdma2dp_alu_valid) + ,.inp_prdy (sdp_brdma2dp_alu_ready) + ,.inp_data (sdp_brdma2dp_alu_pd[8*16:0]) + ,.out_pvld (bs_alu_in_pvld) + ,.out_prdy (bs_alu_in_prdy) + ,.out_data (bs_alu_in_pd[16*1:0]) + ); +assign bs_alu_in_data[16*1 -1:0] = bs_alu_in_pd[16*1 -1:0]; +assign bs_alu_in_layer_end = bs_alu_in_pd[16*1]; +//covert atomic_m to 1 +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bn_mul_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_nrdma2dp_mul_valid) + ,.inp_prdy (sdp_nrdma2dp_mul_ready) + ,.inp_data (sdp_nrdma2dp_mul_pd[8*16:0]) + ,.out_pvld (bn_mul_in_pvld) + ,.out_prdy (bn_mul_in_prdy) + ,.out_data (bn_mul_in_pd[16*1:0]) + ); +assign bn_mul_in_data[16*1 -1:0] = bn_mul_in_pd[16*1 -1:0]; +assign bn_mul_in_layer_end = bn_mul_in_pd[16*1]; +NV_NVDLA_SDP_RDMA_pack #(.IW(8*16),.OW(16*1),.CW(1)) u_bn_alu_pack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cfg_dp_8 (~(|reg2dp_proc_precision)) + ,.inp_pvld (sdp_nrdma2dp_alu_valid) + ,.inp_prdy (sdp_nrdma2dp_alu_ready) + ,.inp_data (sdp_nrdma2dp_alu_pd[8*16:0]) + ,.out_pvld (bn_alu_in_pvld) + ,.out_prdy (bn_alu_in_prdy) + ,.out_data (bn_alu_in_pd[16*1:0]) + ); +assign bn_alu_in_data[16*1 -1:0] = bn_alu_in_pd[16*1 -1:0]; +assign bn_alu_in_layer_end = bn_alu_in_pd[16*1]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + wait_for_op_en <= 1'b1; + end else begin + if (dp2reg_done) begin + wait_for_op_en <= 1'b1; + end else if (reg2dp_op_en) begin + wait_for_op_en <= 1'b0; + end + end +end +assign op_en_load = wait_for_op_en & reg2dp_op_en; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bs_alu_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bs_alu_in_en <= 1'b0; + end else if (op_en_load) begin + bs_alu_in_en <= cfg_bs_en && (!reg2dp_bs_alu_bypass) && (reg2dp_bs_alu_src==1); + end else if (bs_alu_in_layer_end && bs_alu_in_pvld && bs_alu_in_prdy) begin + bs_alu_in_en <= 1'b0; + end + end +end +assign bs_alu_in_vld = bs_alu_in_en & bs_alu_in_pvld; +assign bs_alu_in_prdy = bs_alu_in_en & bs_alu_in_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bs_mul_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bs_mul_in_en <= 1'b0; + end else if (op_en_load) begin + bs_mul_in_en <= cfg_bs_en && (!reg2dp_bs_mul_bypass) &(reg2dp_bs_mul_src==1); + end else if (bs_mul_in_layer_end && bs_mul_in_pvld && bs_mul_in_prdy) begin + bs_mul_in_en <= 1'b0; + end + end +end +assign bs_mul_in_vld = bs_mul_in_en & bs_mul_in_pvld; +assign bs_mul_in_prdy = bs_mul_in_en & bs_mul_in_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bn_alu_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bn_alu_in_en <= 1'b0; + end else if (op_en_load) begin + bn_alu_in_en <= cfg_bn_en && (!reg2dp_bn_alu_bypass) && (reg2dp_bn_alu_src==1); + end else if (bn_alu_in_layer_end && bn_alu_in_pvld && bn_alu_in_prdy) begin + bn_alu_in_en <= 1'b0; + end + end +end +assign bn_alu_in_vld = bn_alu_in_en & bn_alu_in_pvld; +assign bn_alu_in_prdy = bn_alu_in_en & bn_alu_in_rdy; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + bn_mul_in_en <= 1'b0; + end else begin + if (dp2reg_done) begin + bn_mul_in_en <= 1'b0; + end else if (op_en_load) begin + bn_mul_in_en <= cfg_bn_en && (!reg2dp_bn_mul_bypass) &(reg2dp_bn_mul_src==1); + end else if (bn_mul_in_layer_end && bn_mul_in_pvld && bn_mul_in_prdy) begin + bn_mul_in_en <= 1'b0; + end + end +end +assign bn_mul_in_vld = bn_mul_in_en & bn_mul_in_pvld; +assign bn_mul_in_prdy = bn_mul_in_en & bn_mul_in_rdy; +//=========================================== +// CORE +//=========================================== +// data from MUX ? CC : MEM +NV_NVDLA_SDP_cmux u_NV_NVDLA_SDP_cmux ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd[32*1 +1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma_data_in_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma_data_in_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma_data_in_pd[32*1 +1:0]) + ,.sdp_cmux2dp_ready (sdp_cmux2dp_ready) + ,.sdp_cmux2dp_pd (sdp_cmux2dp_pd[32*1 -1:0]) + ,.sdp_cmux2dp_valid (sdp_cmux2dp_valid) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.op_en_load (op_en_load) + ); +assign sdp_cmux2dp_data[32*1 -1:0] = sdp_cmux2dp_pd[32*1 -1:0]; +// MUX to bypass CORE_x0 +assign sdp_cmux2dp_ready = cfg_bs_en ? bs_data_in_prdy : flop_bs_data_out_prdy; +assign bs_data_in_pd = sdp_cmux2dp_data; +assign bs_data_in_pvld = cfg_bs_en & sdp_cmux2dp_valid; +//covert 1 to 1 +NV_NVDLA_SDP_CORE_pack #(.IW(32*1),.OW(32*1)) u_bs_dppack ( + .nvdla_core_clk (nvdla_gated_bcore_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bs_data_in_pvld) //|< i + ,.inp_data (bs_data_in_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bs_data_in_prdy) //|> o + ,.out_pvld (flop_bs_data_in_pvld) //|> w + ,.out_data (flop_bs_data_in_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bs_data_in_prdy) //|< w + ); +NV_NVDLA_SDP_HLS_x1_int u_bs ( + .cfg_alu_algo (cfg_bs_alu_algo[1:0]) //|< r + ,.cfg_alu_bypass (cfg_bs_alu_bypass) //|< r + ,.cfg_alu_op (cfg_bs_alu_operand[15:0]) //|< r + ,.cfg_alu_shift_value (cfg_bs_alu_shift_value[5:0]) //|< r + ,.cfg_alu_src (cfg_bs_alu_src) //|< r + ,.cfg_mul_bypass (cfg_bs_mul_bypass) //|< r + ,.cfg_mul_op (cfg_bs_mul_operand[15:0]) //|< r + ,.cfg_mul_prelu (cfg_bs_mul_prelu) //|< r + ,.cfg_mul_shift_value (cfg_bs_mul_shift_value[5:0]) //|< r + ,.cfg_mul_src (cfg_bs_mul_src) //|< r + ,.cfg_relu_bypass (cfg_bs_relu_bypass) //|< r + ,.chn_alu_op (bs_alu_in_data[16*1 -1:0]) //|< w + ,.chn_alu_op_pvld (bs_alu_in_vld) //|< w + ,.chn_data_in (flop_bs_data_in_pd[32*1 -1:0]) //|< w + ,.chn_in_pvld (flop_bs_data_in_pvld) //|< w + ,.chn_mul_op (bs_mul_in_data[16*1 -1:0]) //|< w + ,.chn_mul_op_pvld (bs_mul_in_vld) //|< w + ,.chn_out_prdy (bs_data_out_prdy) //|< w + ,.chn_alu_op_prdy (bs_alu_in_rdy) //|> w + ,.chn_data_out (bs_data_out_pd[32*1 -1:0]) //|> w + ,.chn_in_prdy (flop_bs_data_in_prdy) //|> w + ,.chn_mul_op_prdy (bs_mul_in_rdy) //|> w + ,.chn_out_pvld (bs_data_out_pvld) //|> w + ,.nvdla_core_clk (nvdla_gated_bcore_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +//covert 1 to 1 +NV_NVDLA_SDP_CORE_unpack #(.IW(32*1),.OW(32*1)) u_bs_dpunpack ( + .nvdla_core_clk (nvdla_gated_bcore_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bs_data_out_pvld) //|< i + ,.inp_data (bs_data_out_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bs_data_out_prdy) //|> o + ,.out_pvld (flop_bs_data_out_pvld) //|> w + ,.out_data (flop_bs_data_out_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bs_data_out_prdy) //|< w + ); +//=========================================== +// MUX between BS and BN +//=========================================== +assign flop_bs_data_out_prdy = cfg_bn_en ? bn_data_in_prdy : flop_bn_data_out_prdy; +assign bs2bn_data_pvld = cfg_bs_en ? flop_bs_data_out_pvld : sdp_cmux2dp_valid; +assign bn_data_in_pd = cfg_bs_en ? flop_bs_data_out_pd : bs_data_in_pd; +assign bn_data_in_pvld = cfg_bn_en & bs2bn_data_pvld; +//covert 1 to 1 +NV_NVDLA_SDP_CORE_pack #(.IW(32*1),.OW(32*1)) u_bn_dppack ( + .nvdla_core_clk (nvdla_gated_ncore_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bn_data_in_pvld) //|< i + ,.inp_data (bn_data_in_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bn_data_in_prdy) //|> o + ,.out_pvld (flop_bn_data_in_pvld) //|> w + ,.out_data (flop_bn_data_in_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bn_data_in_prdy) //|< w + ); +NV_NVDLA_SDP_HLS_x2_int u_bn ( + .nvdla_core_clk (nvdla_gated_ncore_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_alu_algo (cfg_bn_alu_algo[1:0]) //|< r + ,.cfg_alu_bypass (cfg_bn_alu_bypass) //|< r + ,.cfg_alu_op (cfg_bn_alu_operand[15:0]) //|< r + ,.cfg_alu_shift_value (cfg_bn_alu_shift_value[5:0]) //|< r + ,.cfg_alu_src (cfg_bn_alu_src) //|< r + ,.cfg_mul_bypass (cfg_bn_mul_bypass) //|< r + ,.cfg_mul_op (cfg_bn_mul_operand[15:0]) //|< r + ,.cfg_mul_prelu (cfg_bn_mul_prelu) //|< r + ,.cfg_mul_shift_value (cfg_bn_mul_shift_value[5:0]) //|< r + ,.cfg_mul_src (cfg_bn_mul_src) //|< r + ,.cfg_relu_bypass (cfg_bn_relu_bypass) //|< r + ,.chn_data_in (flop_bn_data_in_pd[32*1 -1:0]) //|< w + ,.chn_in_pvld (flop_bn_data_in_pvld) //|< w + ,.chn_in_prdy (flop_bn_data_in_prdy) //|> w + ,.chn_alu_op (bn_alu_in_data[16*1 -1:0]) //|< w + ,.chn_alu_op_pvld (bn_alu_in_vld) //|< w + ,.chn_alu_op_prdy (bn_alu_in_rdy) //|> w + ,.chn_mul_op (bn_mul_in_data[16*1 -1:0]) //|< w + ,.chn_mul_op_pvld (bn_mul_in_vld) //|< w + ,.chn_mul_op_prdy (bn_mul_in_rdy) //|> w + ,.chn_out_prdy (bn_data_out_prdy) //|< w + ,.chn_data_out (bn_data_out_pd[32*1 -1:0]) //|> w + ,.chn_out_pvld (bn_data_out_pvld) //|> w + ); +//covert 1 to 1 +NV_NVDLA_SDP_CORE_unpack #(.IW(32*1),.OW(32*1)) u_bn_dpunpack ( + .nvdla_core_clk (nvdla_gated_ncore_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.inp_pvld (bn_data_out_pvld) //|< i + ,.inp_data (bn_data_out_pd[32*1 -1:0]) //|< i + ,.inp_prdy (bn_data_out_prdy) //|> o + ,.out_pvld (flop_bn_data_out_pvld) //|> w + ,.out_data (flop_bn_data_out_pd[32*1 -1:0]) //|> w + ,.out_prdy (flop_bn_data_out_prdy) //|< w + ); +//=========================================== +// MUX between BN and EW +//=========================================== +assign flop_bn_data_out_prdy = flop_ew_data_out_prdy; +assign bn2ew_data_pvld = cfg_bn_en ? flop_bn_data_out_pvld : bs2bn_data_pvld; +assign ew_data_in_pd = cfg_bn_en ? flop_bn_data_out_pd : bn_data_in_pd; +assign flop_ew_data_out_prdy = cvt_data_in_prdy; +assign cvt_data_in_pvld = bn2ew_data_pvld; +assign cvt_data_in_pd = ew_data_in_pd; +NV_NVDLA_SDP_HLS_c u_c ( + .cfg_mode_eql (cfg_mode_eql) //|< r + ,.cfg_out_precision (cfg_out_precision[1:0]) //|< r + ,.cfg_offset (cfg_cvt_offset[31:0]) //|< r + ,.cfg_scale (cfg_cvt_scale[15:0]) //|< r + ,.cfg_truncate (cfg_cvt_shift[5:0]) //|< r + ,.cvt_in_pvld (cvt_data_in_pvld) //|< w + ,.cvt_in_prdy (cvt_data_in_prdy) //|> w + ,.cvt_pd_in (cvt_data_in_pd[32*1 -1:0]) //|< w + ,.cvt_out_pvld (cvt_data_out_pvld) //|> w + ,.cvt_out_prdy (cvt_data_out_prdy) //|< w + ,.cvt_pd_out (cvt_data_out_pd[16*1 +1 -1:0]) //|> w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ); +assign cvt_data_out_data = cvt_data_out_pd[16*1 -1:0]; +assign cvt_data_out_sat = cvt_data_out_pd[16*1 +1 -1:16*1]; +// to (PDP | WDMA) +assign cfg_mode_pdp = reg2dp_output_dst== 1'h1 ; +assign cvt_data_out_prdy = core2wdma_rdy & ((!cfg_mode_pdp) || core2pdp_rdy); +assign core2wdma_vld = cvt_data_out_pvld & ( (!cfg_mode_pdp) || core2pdp_rdy); +assign core2pdp_vld = cfg_mode_pdp & cvt_data_out_pvld & core2wdma_rdy; +assign core2wdma_pd = cfg_mode_pdp ? {8*1{1'b0}} : cvt_data_out_data; +assign core2pdp_pd = cfg_mode_pdp ? cvt_data_out_data[8*1 -1:0] : {8*1{1'b0}}; +//covert 1 to atomic_m +//only int8 or int16. If support both, use NV_NVDLA_SDP_WDMA_unpack +NV_NVDLA_SDP_CORE_unpack #(.IW(8*1),.OW(8*8)) u_dpout_unpack ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.inp_pvld (core2wdma_vld) + ,.inp_prdy (core2wdma_rdy) + ,.inp_data (core2wdma_pd[8*1 -1:0]) + ,.out_pvld (sdp_dp2wdma_valid) + ,.out_prdy (sdp_dp2wdma_ready) + ,.out_data (sdp_dp2wdma_pd[8*8 -1:0]) + ); +//pdp THROUGHPUT is 1 +NV_NVDLA_SDP_CORE_pipe_p11 pipe_p11 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.core2pdp_pd (core2pdp_pd[8*1 -1:0]) //|< w + ,.core2pdp_vld (core2pdp_vld) //|< w + ,.core2pdp_rdy (core2pdp_rdy) //|> w + ,.sdp2pdp_pd (sdp2pdp_pd[8*1 -1:0]) //|> o + ,.sdp2pdp_valid (sdp2pdp_valid) //|> o + ,.sdp2pdp_ready (sdp2pdp_ready) //|< i + ); +//=========================================== +// PERF STATISTIC: SATURATION +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + saturation_bits <= {1{1'b0}}; + end else begin + if (cvt_data_out_pvld & cvt_data_out_prdy) begin + saturation_bits <= cvt_data_out_sat; + end else begin + saturation_bits <= 0; + end + end +end +assign cvt_saturation_add = fun_my_bit_sum({{(32-1){1'b0}},saturation_bits}); +assign cvt_saturation_sub = 1'b0; +assign cvt_saturation_clr = op_en_load; +assign cvt_saturation_cen = reg2dp_perf_sat_en; +assign cvt_sat_add_ext = cvt_saturation_add; +assign cvt_sat_sub_ext = {{5{1'b0}}, cvt_saturation_sub}; +assign cvt_sat_inc = cvt_sat_add_ext > cvt_sat_sub_ext; +assign cvt_sat_dec = cvt_sat_add_ext < cvt_sat_sub_ext; +assign cvt_sat_mod_ext[5:0] = cvt_sat_inc ? (cvt_sat_add_ext - cvt_sat_sub_ext) : (cvt_sat_sub_ext - cvt_sat_add_ext); // spyglass disable W484 +assign cvt_sat_sub_guard = (|cvt_saturation_cnt[31:1])==1'b0; +assign cvt_sat_sub_act = cvt_saturation_cnt[0:0]; +assign cvt_sat_sub_act_ext = {{5{1'b0}}, cvt_sat_sub_act}; +assign cvt_sat_sub_flow = cvt_sat_dec & cvt_sat_sub_guard & (cvt_sat_sub_act_ext < cvt_sat_mod_ext); +assign cvt_sat_add_guard = (&cvt_saturation_cnt[31:6])==1'b1; +assign cvt_sat_add_act = cvt_saturation_cnt[5:0]; +assign cvt_sat_add_act_ext = cvt_sat_add_act; +assign cvt_sat_add_flow = cvt_sat_inc & cvt_sat_add_guard & (cvt_sat_add_act_ext + cvt_sat_mod_ext > 63 ); +assign i_add = cvt_sat_add_flow ? (63 - cvt_sat_add_act) : cvt_sat_sub_flow ? 0 : cvt_saturation_add; +assign i_sub = cvt_sat_sub_flow ? (cvt_sat_sub_act) : cvt_sat_add_flow ? 0 : cvt_saturation_sub ; +always @( + i_add + or i_sub + ) begin + cvt_sat_cvt_sat_adv = i_add[5:0] != {{5{1'b0}}, i_sub[0:0]}; +end +always @( + cvt_sat_cvt_sat_cnt_cur + or i_add + or i_sub + or cvt_sat_cvt_sat_adv + or cvt_saturation_clr + ) begin + cvt_sat_cvt_sat_cnt_ext[33:0] = {1'b0, 1'b0, cvt_sat_cvt_sat_cnt_cur}; + cvt_sat_cvt_sat_cnt_mod[33:0] = cvt_sat_cvt_sat_cnt_cur + i_add[5:0] - i_sub[0:0]; // spyglass disable W164b + cvt_sat_cvt_sat_cnt_new[33:0] = (cvt_sat_cvt_sat_adv)? cvt_sat_cvt_sat_cnt_mod[33:0] : cvt_sat_cvt_sat_cnt_ext[33:0]; + cvt_sat_cvt_sat_cnt_nxt[33:0] = (cvt_saturation_clr)? 34'd0 : cvt_sat_cvt_sat_cnt_new[33:0]; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + cvt_sat_cvt_sat_cnt_cur[31:0] <= 0; + end else begin + if (cvt_saturation_cen) begin + cvt_sat_cvt_sat_cnt_cur[31:0] <= cvt_sat_cvt_sat_cnt_nxt[31:0]; + end + end +end +always @( + cvt_sat_cvt_sat_cnt_cur + ) begin + cvt_saturation_cnt[31:0] = cvt_sat_cvt_sat_cnt_cur[31:0]; +end +assign dp2reg_out_saturation = cvt_saturation_cnt; +function [5:0] fun_my_bit_sum; + input [31:0] idata; + reg [5:0] ocnt; + begin + ocnt = + (((( idata[0] + + idata[1] + + idata[2] ) + + ( idata[3] + + idata[4] + + idata[5] )) + + (( idata[6] + + idata[7] + + idata[8] ) + + ( idata[9] + + idata[10] + + idata[11] ))) + + ((( idata[12] + + idata[13] + + idata[14] ) + + ( idata[15] + + idata[16] + + idata[17] )) + + (( idata[18] + + idata[19] + + idata[20] ) + + ( idata[21] + + idata[22] + + idata[23] )))) + + (( idata[24] + + idata[25] + + idata[26] ) + + ( idata[27] + + idata[28] + + idata[29] )) + + ( idata[30] + + idata[31] ) ; + fun_my_bit_sum = ocnt; + end +endfunction +endmodule // NV_NVDLA_SDP_core +// ************************************************************************************************************** +// Generated by ::pipe -m -bc sdp2pdp_pd (sdp2pdp_valid,sdp2pdp_ready) <= core2pdp_pd[255:0] (core2pdp_vld,core2pdp_rdy) +// ************************************************************************************************************** +module NV_NVDLA_SDP_CORE_pipe_p11 ( + nvdla_core_clk + ,nvdla_core_rstn + ,core2pdp_pd + ,core2pdp_vld + ,sdp2pdp_ready + ,core2pdp_rdy + ,sdp2pdp_pd + ,sdp2pdp_valid + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [8*1 -1:0] core2pdp_pd; +input core2pdp_vld; +input sdp2pdp_ready; +output core2pdp_rdy; +output [8*1 -1:0] sdp2pdp_pd; +output sdp2pdp_valid; +//: my $dw = 8*1; +//: &eperl::pipe("-is -wid $dw -do sdp2pdp_pd -vo sdp2pdp_valid -ri sdp2pdp_ready -di core2pdp_pd -vi core2pdp_vld -ro core2pdp_rdy"); +endmodule // NV_NVDLA_SDP_CORE_pipe_p11 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v new file mode 100644 index 0000000..ea94fba --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v @@ -0,0 +1,244 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_erdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_erdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,erdma_disable //|< i + ,erdma_slcg_op_en //|< i + ,sdp_e2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_e2mcif_rd_req_pd //|> o + ,sdp_e2mcif_rd_req_valid //|> o + ,sdp_e2mcif_rd_req_ready //|< i + ,mcif2sdp_e_rd_rsp_pd //|< i + ,mcif2sdp_e_rd_rsp_valid //|< i + ,mcif2sdp_e_rd_rsp_ready //|> o + ,reg2dp_erdma_data_mode //|< i + ,reg2dp_erdma_data_size //|< i + ,reg2dp_erdma_data_use //|< i + ,reg2dp_erdma_ram_type //|< i + ,reg2dp_ew_base_addr_high //|< i + ,reg2dp_ew_base_addr_low //|< i + ,reg2dp_ew_line_stride //|< i + ,reg2dp_ew_surface_stride //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_winograd //|< i + ,dp2reg_erdma_stall //|> o + ,dp2reg_done //|> o + ,sdp_erdma2dp_alu_ready //|< i + ,sdp_erdma2dp_mul_ready //|< i + ,sdp_erdma2dp_alu_pd //|> o + ,sdp_erdma2dp_alu_valid //|> o + ,sdp_erdma2dp_mul_pd //|> o + ,sdp_erdma2dp_mul_valid //|> o + ); +// +// NV_NVDLA_SDP_erdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + output sdp_e2mcif_rd_req_valid; + input sdp_e2mcif_rd_req_ready; + output [47 -1:0] sdp_e2mcif_rd_req_pd; + input mcif2sdp_e_rd_rsp_valid; + output mcif2sdp_e_rd_rsp_ready; + input [65 -1:0] mcif2sdp_e_rd_rsp_pd; + output sdp_e2mcif_rd_cdt_lat_fifo_pop; + output sdp_erdma2dp_alu_valid; + input sdp_erdma2dp_alu_ready; + output [8*16:0] sdp_erdma2dp_alu_pd; + output sdp_erdma2dp_mul_valid; + input sdp_erdma2dp_mul_ready; + output [8*16:0] sdp_erdma2dp_mul_pd; + input reg2dp_erdma_data_mode; + input reg2dp_erdma_data_size; + input [1:0] reg2dp_erdma_data_use; + input reg2dp_erdma_ram_type; + input [31:0] reg2dp_ew_base_addr_high; + input [31-3:0] reg2dp_ew_base_addr_low; + input [31-3:0] reg2dp_ew_line_stride; + input [31-3:0] reg2dp_ew_surface_stride; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input reg2dp_op_en; + input [1:0] reg2dp_out_precision; + input reg2dp_perf_dma_en; + input [1:0] reg2dp_proc_precision; + input [12:0] reg2dp_width; + input reg2dp_winograd; + output [31:0] dp2reg_erdma_stall; + output dp2reg_done; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input erdma_slcg_op_en; + input erdma_disable; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + reg layer_process; + wire [15:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire [15:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; + wire [65 -1:0] lat_fifo_rd_pd; + wire lat_fifo_rd_pvld; + wire lat_fifo_rd_prdy; +// Layer Switch +assign op_load = reg2dp_op_en & !layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= +NV_NVDLA_SDP_ERDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.erdma_disable (erdma_disable) //|< i + ,.erdma_slcg_op_en (erdma_slcg_op_en) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_RDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_erdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_erdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_erdma_data_use[1:0]) //|< i + ,.reg2dp_base_addr_high (reg2dp_ew_base_addr_high[31:0]) //|< i + ,.reg2dp_base_addr_low (reg2dp_ew_base_addr_low[31-3:0]) //|< i + ,.reg2dp_line_stride (reg2dp_ew_line_stride[31-3:0]) //|< i + ,.reg2dp_surface_stride (reg2dp_ew_surface_stride[31-3:0]) //|< i + ,.dp2reg_rdma_stall (dp2reg_erdma_stall[31:0]) //|> o + ); +NV_NVDLA_SDP_ERDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|> w + ); +NV_NVDLA_SDP_RDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.lat_fifo_rd_pd (lat_fifo_rd_pd[65 -1:0]) //|< w + ,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w + ,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w + ,.sdp_rdma2dp_alu_ready (sdp_erdma2dp_alu_ready) //|< i + ,.sdp_rdma2dp_mul_ready (sdp_erdma2dp_mul_ready) //|< i + ,.sdp_rdma2dp_alu_pd (sdp_erdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_alu_valid (sdp_erdma2dp_alu_valid) //|> o + ,.sdp_rdma2dp_mul_pd (sdp_erdma2dp_mul_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_mul_valid (sdp_erdma2dp_mul_valid) //|> o + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_erdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_erdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_erdma_data_use[1:0]) //|< i + ); +NV_NVDLA_SDP_ERDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_fifo_rd_prdy) + ,.lat_rd_pvld (lat_fifo_rd_pvld) + ,.lat_rd_pd (lat_fifo_rd_pd[65 -1:0]) + ); +NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready) //|> o + ,.dma_rd_req_ram_type (reg2dp_erdma_ram_type) //|< w + ,.dma_rd_rsp_ram_type (reg2dp_erdma_ram_type) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ); +endmodule // NV_NVDLA_SDP_erdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v.vcp new file mode 100644 index 0000000..ea94fba --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_erdma.v.vcp @@ -0,0 +1,244 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_erdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_erdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,erdma_disable //|< i + ,erdma_slcg_op_en //|< i + ,sdp_e2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_e2mcif_rd_req_pd //|> o + ,sdp_e2mcif_rd_req_valid //|> o + ,sdp_e2mcif_rd_req_ready //|< i + ,mcif2sdp_e_rd_rsp_pd //|< i + ,mcif2sdp_e_rd_rsp_valid //|< i + ,mcif2sdp_e_rd_rsp_ready //|> o + ,reg2dp_erdma_data_mode //|< i + ,reg2dp_erdma_data_size //|< i + ,reg2dp_erdma_data_use //|< i + ,reg2dp_erdma_ram_type //|< i + ,reg2dp_ew_base_addr_high //|< i + ,reg2dp_ew_base_addr_low //|< i + ,reg2dp_ew_line_stride //|< i + ,reg2dp_ew_surface_stride //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_winograd //|< i + ,dp2reg_erdma_stall //|> o + ,dp2reg_done //|> o + ,sdp_erdma2dp_alu_ready //|< i + ,sdp_erdma2dp_mul_ready //|< i + ,sdp_erdma2dp_alu_pd //|> o + ,sdp_erdma2dp_alu_valid //|> o + ,sdp_erdma2dp_mul_pd //|> o + ,sdp_erdma2dp_mul_valid //|> o + ); +// +// NV_NVDLA_SDP_erdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + output sdp_e2mcif_rd_req_valid; + input sdp_e2mcif_rd_req_ready; + output [47 -1:0] sdp_e2mcif_rd_req_pd; + input mcif2sdp_e_rd_rsp_valid; + output mcif2sdp_e_rd_rsp_ready; + input [65 -1:0] mcif2sdp_e_rd_rsp_pd; + output sdp_e2mcif_rd_cdt_lat_fifo_pop; + output sdp_erdma2dp_alu_valid; + input sdp_erdma2dp_alu_ready; + output [8*16:0] sdp_erdma2dp_alu_pd; + output sdp_erdma2dp_mul_valid; + input sdp_erdma2dp_mul_ready; + output [8*16:0] sdp_erdma2dp_mul_pd; + input reg2dp_erdma_data_mode; + input reg2dp_erdma_data_size; + input [1:0] reg2dp_erdma_data_use; + input reg2dp_erdma_ram_type; + input [31:0] reg2dp_ew_base_addr_high; + input [31-3:0] reg2dp_ew_base_addr_low; + input [31-3:0] reg2dp_ew_line_stride; + input [31-3:0] reg2dp_ew_surface_stride; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input reg2dp_op_en; + input [1:0] reg2dp_out_precision; + input reg2dp_perf_dma_en; + input [1:0] reg2dp_proc_precision; + input [12:0] reg2dp_width; + input reg2dp_winograd; + output [31:0] dp2reg_erdma_stall; + output dp2reg_done; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input erdma_slcg_op_en; + input erdma_disable; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + reg layer_process; + wire [15:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire [15:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; + wire [65 -1:0] lat_fifo_rd_pd; + wire lat_fifo_rd_pvld; + wire lat_fifo_rd_prdy; +// Layer Switch +assign op_load = reg2dp_op_en & !layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= +NV_NVDLA_SDP_ERDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.erdma_disable (erdma_disable) //|< i + ,.erdma_slcg_op_en (erdma_slcg_op_en) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_RDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_erdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_erdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_erdma_data_use[1:0]) //|< i + ,.reg2dp_base_addr_high (reg2dp_ew_base_addr_high[31:0]) //|< i + ,.reg2dp_base_addr_low (reg2dp_ew_base_addr_low[31-3:0]) //|< i + ,.reg2dp_line_stride (reg2dp_ew_line_stride[31-3:0]) //|< i + ,.reg2dp_surface_stride (reg2dp_ew_surface_stride[31-3:0]) //|< i + ,.dp2reg_rdma_stall (dp2reg_erdma_stall[31:0]) //|> o + ); +NV_NVDLA_SDP_ERDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|> w + ); +NV_NVDLA_SDP_RDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.lat_fifo_rd_pd (lat_fifo_rd_pd[65 -1:0]) //|< w + ,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w + ,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w + ,.sdp_rdma2dp_alu_ready (sdp_erdma2dp_alu_ready) //|< i + ,.sdp_rdma2dp_mul_ready (sdp_erdma2dp_mul_ready) //|< i + ,.sdp_rdma2dp_alu_pd (sdp_erdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_alu_valid (sdp_erdma2dp_alu_valid) //|> o + ,.sdp_rdma2dp_mul_pd (sdp_erdma2dp_mul_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_mul_valid (sdp_erdma2dp_mul_valid) //|> o + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_erdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_erdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_erdma_data_use[1:0]) //|< i + ); +NV_NVDLA_SDP_ERDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_fifo_rd_prdy) + ,.lat_rd_pvld (lat_fifo_rd_pvld) + ,.lat_rd_pd (lat_fifo_rd_pd[65 -1:0]) + ); +NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_e2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp_e2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp_e2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp_e2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_e_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_e_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_e_rd_rsp_ready) //|> o + ,.dma_rd_req_ram_type (reg2dp_erdma_ram_type) //|< w + ,.dma_rd_rsp_ram_type (reg2dp_erdma_ram_type) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ); +endmodule // NV_NVDLA_SDP_erdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v new file mode 100644 index 0000000..4a2b18e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v @@ -0,0 +1,231 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_mrdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_mrdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,mrdma_slcg_op_en //|< i + ,mrdma_disable //|< i + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,reg2dp_op_en //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_src_base_addr_high //|< i + ,reg2dp_src_base_addr_low //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_surface_stride //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_perf_nan_inf_count_en //|< i + ,dp2reg_done //|> o + ,dp2reg_mrdma_stall //|> o + ,dp2reg_status_inf_input_num //|> o + ,dp2reg_status_nan_input_num //|> o + ); +// +// NV_NVDLA_SDP_mrdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input mrdma_disable; + input mrdma_slcg_op_en; + output sdp2mcif_rd_req_valid; + input sdp2mcif_rd_req_ready; + output [47 -1:0] sdp2mcif_rd_req_pd; + input mcif2sdp_rd_rsp_valid; + output mcif2sdp_rd_rsp_ready; + input [65 -1:0] mcif2sdp_rd_rsp_pd; + output sdp2mcif_rd_cdt_lat_fifo_pop; + output sdp_mrdma2cmux_valid; + input sdp_mrdma2cmux_ready; + output [32*8 +1:0] sdp_mrdma2cmux_pd; + input reg2dp_op_en; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input [12:0] reg2dp_width; + input [1:0] reg2dp_in_precision; + input [1:0] reg2dp_proc_precision; + input reg2dp_src_ram_type; + input [31:0] reg2dp_src_base_addr_high; + input [31-3:0] reg2dp_src_base_addr_low; + input [31-3:0] reg2dp_src_line_stride; + input [31-3:0] reg2dp_src_surface_stride; + input reg2dp_perf_dma_en; + input reg2dp_perf_nan_inf_count_en; + output dp2reg_done; + output [31:0] dp2reg_mrdma_stall; + output [31:0] dp2reg_status_inf_input_num; + output [31:0] dp2reg_status_nan_input_num; + reg layer_process; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + wire [13:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire [13:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_ram_type; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire dma_rd_rsp_ram_type; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; +//============== +// Work Processing +//============== +assign op_load = reg2dp_op_en & ~layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= + NV_NVDLA_SDP_MRDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.mrdma_slcg_op_en (mrdma_slcg_op_en) //|< i + ,.mrdma_disable (mrdma_disable) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +//======================================= +// Ingress: send read request to external mem +//--------------------------------------- + NV_NVDLA_SDP_MRDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.ig2cq_pd (ig2cq_pd[13:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_ram_type (dma_rd_req_ram_type) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< i + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< i + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31-3:0]) //|< i + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31-3:0]) //|< i + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31-3:0]) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|> o + ); +//======================================= +// Context Queue: trace outstanding req, and pass info from Ig to Eg +//--------------------------------------- + NV_NVDLA_SDP_MRDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[13:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[13:0]) //|> w + ); +//======================================= +// Egress: get return data from external mem +//--------------------------------------- + NV_NVDLA_SDP_MRDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[13:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_rsp_ram_type (dma_rd_rsp_ram_type) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|< w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) //|< i + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) //|> o + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) //|> o + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< i + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|< i + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|> o + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|> o + ); + NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i fixme + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) //|> o + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_ram_type (dma_rd_req_ram_type) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_rsp_ram_type (dma_rd_rsp_ram_type) //|< w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ); +endmodule // NV_NVDLA_SDP_mrdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v.vcp new file mode 100644 index 0000000..4a2b18e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_mrdma.v.vcp @@ -0,0 +1,231 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_mrdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_mrdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,mrdma_slcg_op_en //|< i + ,mrdma_disable //|< i + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,reg2dp_op_en //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_in_precision //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_src_ram_type //|< i + ,reg2dp_src_base_addr_high //|< i + ,reg2dp_src_base_addr_low //|< i + ,reg2dp_src_line_stride //|< i + ,reg2dp_src_surface_stride //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_perf_nan_inf_count_en //|< i + ,dp2reg_done //|> o + ,dp2reg_mrdma_stall //|> o + ,dp2reg_status_inf_input_num //|> o + ,dp2reg_status_nan_input_num //|> o + ); +// +// NV_NVDLA_SDP_mrdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input mrdma_disable; + input mrdma_slcg_op_en; + output sdp2mcif_rd_req_valid; + input sdp2mcif_rd_req_ready; + output [47 -1:0] sdp2mcif_rd_req_pd; + input mcif2sdp_rd_rsp_valid; + output mcif2sdp_rd_rsp_ready; + input [65 -1:0] mcif2sdp_rd_rsp_pd; + output sdp2mcif_rd_cdt_lat_fifo_pop; + output sdp_mrdma2cmux_valid; + input sdp_mrdma2cmux_ready; + output [32*8 +1:0] sdp_mrdma2cmux_pd; + input reg2dp_op_en; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input [12:0] reg2dp_width; + input [1:0] reg2dp_in_precision; + input [1:0] reg2dp_proc_precision; + input reg2dp_src_ram_type; + input [31:0] reg2dp_src_base_addr_high; + input [31-3:0] reg2dp_src_base_addr_low; + input [31-3:0] reg2dp_src_line_stride; + input [31-3:0] reg2dp_src_surface_stride; + input reg2dp_perf_dma_en; + input reg2dp_perf_nan_inf_count_en; + output dp2reg_done; + output [31:0] dp2reg_mrdma_stall; + output [31:0] dp2reg_status_inf_input_num; + output [31:0] dp2reg_status_nan_input_num; + reg layer_process; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + wire [13:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire [13:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_ram_type; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire dma_rd_rsp_ram_type; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; +//============== +// Work Processing +//============== +assign op_load = reg2dp_op_en & ~layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= + NV_NVDLA_SDP_MRDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.mrdma_slcg_op_en (mrdma_slcg_op_en) //|< i + ,.mrdma_disable (mrdma_disable) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +//======================================= +// Ingress: send read request to external mem +//--------------------------------------- + NV_NVDLA_SDP_MRDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.ig2cq_pd (ig2cq_pd[13:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_ram_type (dma_rd_req_ram_type) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< i + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< i + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31-3:0]) //|< i + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31-3:0]) //|< i + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31-3:0]) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|> o + ); +//======================================= +// Context Queue: trace outstanding req, and pass info from Ig to Eg +//--------------------------------------- + NV_NVDLA_SDP_MRDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[13:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[13:0]) //|> w + ); +//======================================= +// Egress: get return data from external mem +//--------------------------------------- + NV_NVDLA_SDP_MRDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[13:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_rsp_ram_type (dma_rd_rsp_ram_type) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|< w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) //|< i + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) //|> o + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) //|> o + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< i + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|< i + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|> o + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|> o + ); + NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i fixme + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) //|> o + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_ram_type (dma_rd_req_ram_type) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_rsp_ram_type (dma_rd_rsp_ram_type) //|< w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ); +endmodule // NV_NVDLA_SDP_mrdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v new file mode 100644 index 0000000..2d3deab --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v @@ -0,0 +1,244 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_nrdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_nrdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,nrdma_disable //|< i + ,nrdma_slcg_op_en //|< i + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,reg2dp_bn_base_addr_high //|< i + ,reg2dp_bn_base_addr_low //|< i + ,reg2dp_bn_line_stride //|< i + ,reg2dp_bn_surface_stride //|< i + ,reg2dp_nrdma_data_mode //|< i + ,reg2dp_nrdma_data_size //|< i + ,reg2dp_nrdma_data_use //|< i + ,reg2dp_nrdma_ram_type //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_winograd //|< i + ,dp2reg_nrdma_stall //|> o + ,dp2reg_done //|> o + ,sdp_nrdma2dp_alu_ready //|< i + ,sdp_nrdma2dp_mul_ready //|< i + ,sdp_nrdma2dp_alu_pd //|> o + ,sdp_nrdma2dp_alu_valid //|> o + ,sdp_nrdma2dp_mul_pd //|> o + ,sdp_nrdma2dp_mul_valid //|> o + ); +// +// NV_NVDLA_SDP_nrdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + output sdp_n2mcif_rd_req_valid; + input sdp_n2mcif_rd_req_ready; + output [47 -1:0] sdp_n2mcif_rd_req_pd; + input mcif2sdp_n_rd_rsp_valid; + output mcif2sdp_n_rd_rsp_ready; + input [65 -1:0] mcif2sdp_n_rd_rsp_pd; + output sdp_n2mcif_rd_cdt_lat_fifo_pop; + output sdp_nrdma2dp_alu_valid; + input sdp_nrdma2dp_alu_ready; + output [8*16:0] sdp_nrdma2dp_alu_pd; + output sdp_nrdma2dp_mul_valid; + input sdp_nrdma2dp_mul_ready; + output [8*16:0] sdp_nrdma2dp_mul_pd; + input reg2dp_nrdma_data_mode; + input reg2dp_nrdma_data_size; + input [1:0] reg2dp_nrdma_data_use; + input reg2dp_nrdma_ram_type; + input [31:0] reg2dp_bn_base_addr_high; + input [31-3:0] reg2dp_bn_base_addr_low; + input [31-3:0] reg2dp_bn_line_stride; + input [31-3:0] reg2dp_bn_surface_stride; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input reg2dp_op_en; + input [1:0] reg2dp_out_precision; + input reg2dp_perf_dma_en; + input [1:0] reg2dp_proc_precision; + input [12:0] reg2dp_width; + input reg2dp_winograd; + output [31:0] dp2reg_nrdma_stall; + output dp2reg_done; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input nrdma_slcg_op_en; + input nrdma_disable; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + reg layer_process; + wire [15:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire [15:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; + wire [65 -1:0] lat_fifo_rd_pd; + wire lat_fifo_rd_pvld; + wire lat_fifo_rd_prdy; +// Layer Switch +assign op_load = reg2dp_op_en & !layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= +NV_NVDLA_SDP_NRDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.nrdma_disable (nrdma_disable) //|< i + ,.nrdma_slcg_op_en (nrdma_slcg_op_en) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_RDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_nrdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_nrdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< i + ,.reg2dp_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|< i + ,.reg2dp_base_addr_low (reg2dp_bn_base_addr_low[31-3:0]) //|< i + ,.reg2dp_line_stride (reg2dp_bn_line_stride[31-3:0]) //|< i + ,.reg2dp_surface_stride (reg2dp_bn_surface_stride[31-3:0]) //|< i + ,.dp2reg_rdma_stall (dp2reg_nrdma_stall[31:0]) //|> o + ); +NV_NVDLA_SDP_NRDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|> w + ); +NV_NVDLA_SDP_RDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.lat_fifo_rd_pd (lat_fifo_rd_pd[65 -1:0]) //|< w + ,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w + ,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w + ,.sdp_rdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) //|< i + ,.sdp_rdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) //|< i + ,.sdp_rdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) //|> o + ,.sdp_rdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) //|> o + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_nrdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_nrdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< i + ); +NV_NVDLA_SDP_NRDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_fifo_rd_prdy) + ,.lat_rd_pvld (lat_fifo_rd_pvld) + ,.lat_rd_pd (lat_fifo_rd_pd[65 -1:0]) + ); +NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|> o + ,.dma_rd_req_ram_type (reg2dp_nrdma_ram_type) //|< w + ,.dma_rd_rsp_ram_type (reg2dp_nrdma_ram_type) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ); +endmodule // NV_NVDLA_SDP_nrdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v.vcp new file mode 100644 index 0000000..2d3deab --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_nrdma.v.vcp @@ -0,0 +1,244 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_nrdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_nrdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,nrdma_disable //|< i + ,nrdma_slcg_op_en //|< i + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,reg2dp_bn_base_addr_high //|< i + ,reg2dp_bn_base_addr_low //|< i + ,reg2dp_bn_line_stride //|< i + ,reg2dp_bn_surface_stride //|< i + ,reg2dp_nrdma_data_mode //|< i + ,reg2dp_nrdma_data_size //|< i + ,reg2dp_nrdma_data_use //|< i + ,reg2dp_nrdma_ram_type //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_height //|< i + ,reg2dp_width //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_winograd //|< i + ,dp2reg_nrdma_stall //|> o + ,dp2reg_done //|> o + ,sdp_nrdma2dp_alu_ready //|< i + ,sdp_nrdma2dp_mul_ready //|< i + ,sdp_nrdma2dp_alu_pd //|> o + ,sdp_nrdma2dp_alu_valid //|> o + ,sdp_nrdma2dp_mul_pd //|> o + ,sdp_nrdma2dp_mul_valid //|> o + ); +// +// NV_NVDLA_SDP_nrdma_ports.v +// + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] pwrbus_ram_pd; + output sdp_n2mcif_rd_req_valid; + input sdp_n2mcif_rd_req_ready; + output [47 -1:0] sdp_n2mcif_rd_req_pd; + input mcif2sdp_n_rd_rsp_valid; + output mcif2sdp_n_rd_rsp_ready; + input [65 -1:0] mcif2sdp_n_rd_rsp_pd; + output sdp_n2mcif_rd_cdt_lat_fifo_pop; + output sdp_nrdma2dp_alu_valid; + input sdp_nrdma2dp_alu_ready; + output [8*16:0] sdp_nrdma2dp_alu_pd; + output sdp_nrdma2dp_mul_valid; + input sdp_nrdma2dp_mul_ready; + output [8*16:0] sdp_nrdma2dp_mul_pd; + input reg2dp_nrdma_data_mode; + input reg2dp_nrdma_data_size; + input [1:0] reg2dp_nrdma_data_use; + input reg2dp_nrdma_ram_type; + input [31:0] reg2dp_bn_base_addr_high; + input [31-3:0] reg2dp_bn_base_addr_low; + input [31-3:0] reg2dp_bn_line_stride; + input [31-3:0] reg2dp_bn_surface_stride; + input [4:0] reg2dp_batch_number; + input [12:0] reg2dp_channel; + input [12:0] reg2dp_height; + input reg2dp_op_en; + input [1:0] reg2dp_out_precision; + input reg2dp_perf_dma_en; + input [1:0] reg2dp_proc_precision; + input [12:0] reg2dp_width; + input reg2dp_winograd; + output [31:0] dp2reg_nrdma_stall; + output dp2reg_done; + input dla_clk_ovr_on_sync; + input global_clk_ovr_on_sync; + input tmc2slcg_disable_clock_gating; + input nrdma_slcg_op_en; + input nrdma_disable; + wire nvdla_gated_clk; + wire op_load; + wire eg_done; + reg layer_process; + wire [15:0] ig2cq_pd; + wire ig2cq_prdy; + wire ig2cq_pvld; + wire [15:0] cq2eg_pd; + wire cq2eg_prdy; + wire cq2eg_pvld; + wire dma_rd_cdt_lat_fifo_pop; + wire [47 -1:0] dma_rd_req_pd; + wire dma_rd_req_rdy; + wire dma_rd_req_vld; + wire [65 -1:0] dma_rd_rsp_pd; + wire dma_rd_rsp_rdy; + wire dma_rd_rsp_vld; + wire [65 -1:0] lat_fifo_rd_pd; + wire lat_fifo_rd_pvld; + wire lat_fifo_rd_prdy; +// Layer Switch +assign op_load = reg2dp_op_en & !layer_process; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + layer_process <= 1'b0; + end else begin + if (op_load) begin + layer_process <= 1'b1; + end else if (eg_done) begin + layer_process <= 1'b0; + end + end +end +assign dp2reg_done = eg_done; +//======================================= +NV_NVDLA_SDP_NRDMA_gate u_gate ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.nrdma_disable (nrdma_disable) //|< i + ,.nrdma_slcg_op_en (nrdma_slcg_op_en) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_RDMA_ig u_ig ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.op_load (op_load) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|> w + ,.ig2cq_prdy (ig2cq_prdy) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|> w + ,.dma_rd_req_vld (dma_rd_req_vld) //|> w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|< w + ,.reg2dp_op_en (reg2dp_op_en) //|< i + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_nrdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_nrdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< i + ,.reg2dp_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|< i + ,.reg2dp_base_addr_low (reg2dp_bn_base_addr_low[31-3:0]) //|< i + ,.reg2dp_line_stride (reg2dp_bn_line_stride[31-3:0]) //|< i + ,.reg2dp_surface_stride (reg2dp_bn_surface_stride[31-3:0]) //|< i + ,.dp2reg_rdma_stall (dp2reg_nrdma_stall[31:0]) //|> o + ); +NV_NVDLA_SDP_NRDMA_cq u_cq ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.ig2cq_prdy (ig2cq_prdy) //|> w + ,.ig2cq_pvld (ig2cq_pvld) //|< w + ,.ig2cq_pd (ig2cq_pd[15:0]) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|> w + ); +NV_NVDLA_SDP_RDMA_eg u_eg ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.eg_done (eg_done) //|> w + ,.cq2eg_pd (cq2eg_pd[15:0]) //|< w + ,.cq2eg_pvld (cq2eg_pvld) //|< w + ,.cq2eg_prdy (cq2eg_prdy) //|> w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|> w + ,.lat_fifo_rd_pd (lat_fifo_rd_pd[65 -1:0]) //|< w + ,.lat_fifo_rd_pvld (lat_fifo_rd_pvld) //|< w + ,.lat_fifo_rd_prdy (lat_fifo_rd_prdy) //|> w + ,.sdp_rdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) //|< i + ,.sdp_rdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) //|< i + ,.sdp_rdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) //|> o + ,.sdp_rdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) //|> o + ,.sdp_rdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) //|> o + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_rdma_data_mode (reg2dp_nrdma_data_mode) //|< i + ,.reg2dp_rdma_data_size (reg2dp_nrdma_data_size) //|< i + ,.reg2dp_rdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< i + ); +NV_NVDLA_SDP_NRDMA_lat_fifo u_lat_fifo ( + .nvdla_core_clk (nvdla_gated_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.lat_wr_prdy (dma_rd_rsp_rdy) + ,.lat_wr_pvld (dma_rd_rsp_vld) + ,.lat_wr_pd (dma_rd_rsp_pd[65 -1:0]) + ,.lat_rd_prdy (lat_fifo_rd_prdy) + ,.lat_rd_pvld (lat_fifo_rd_pvld) + ,.lat_rd_pd (lat_fifo_rd_pd[65 -1:0]) + ); +NV_NVDLA_SDP_RDMA_dmaif u_NV_NVDLA_SDP_RDMA_dmaif ( + .nvdla_core_clk (nvdla_gated_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[47 -1:0]) //|> o + ,.sdp2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) //|< i + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[65 -1:0]) //|< i + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|> o + ,.dma_rd_req_ram_type (reg2dp_nrdma_ram_type) //|< w + ,.dma_rd_rsp_ram_type (reg2dp_nrdma_ram_type) //|< w + ,.dma_rd_req_pd (dma_rd_req_pd[47 -1:0]) //|< w + ,.dma_rd_req_vld (dma_rd_req_vld) //|< w + ,.dma_rd_req_rdy (dma_rd_req_rdy) //|> w + ,.dma_rd_rsp_pd (dma_rd_rsp_pd[65 -1:0]) //|> w + ,.dma_rd_rsp_vld (dma_rd_rsp_vld) //|> w + ,.dma_rd_rsp_rdy (dma_rd_rsp_rdy) //|< w + ,.dma_rd_cdt_lat_fifo_pop (dma_rd_cdt_lat_fifo_pop) //|< w + ); +endmodule // NV_NVDLA_SDP_nrdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v new file mode 100644 index 0000000..2240d12 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_rdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_rdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp_brdma2dp_alu_ready //|< i + ,sdp_brdma2dp_mul_ready //|< i + ,sdp_brdma2dp_alu_pd //|> o + ,sdp_brdma2dp_alu_valid //|> o + ,sdp_brdma2dp_mul_pd //|> o + ,sdp_brdma2dp_mul_valid //|> o + ,sdp_nrdma2dp_alu_ready //|< i + ,sdp_nrdma2dp_mul_ready //|< i + ,sdp_nrdma2dp_alu_pd //|> o + ,sdp_nrdma2dp_alu_valid //|> o + ,sdp_nrdma2dp_mul_pd //|> o + ,sdp_nrdma2dp_mul_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,csb2sdp_rdma_req_prdy //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ); +// +// NV_NVDLA_SDP_rdma_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +input csb2sdp_rdma_req_pvld; +output csb2sdp_rdma_req_prdy; +input [62:0] csb2sdp_rdma_req_pd; +output sdp_rdma2csb_resp_valid; +output [33:0] sdp_rdma2csb_resp_pd; +output sdp2mcif_rd_cdt_lat_fifo_pop; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +output [47 -1:0] sdp2mcif_rd_req_pd; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +input [65 -1:0] mcif2sdp_rd_rsp_pd; +output sdp_b2mcif_rd_cdt_lat_fifo_pop; +output sdp_b2mcif_rd_req_valid; +input sdp_b2mcif_rd_req_ready; +output [47 -1:0] sdp_b2mcif_rd_req_pd; +input mcif2sdp_b_rd_rsp_valid; +output mcif2sdp_b_rd_rsp_ready; +input [65 -1:0] mcif2sdp_b_rd_rsp_pd; +output sdp_brdma2dp_alu_valid; +input sdp_brdma2dp_alu_ready; +output [8*16:0] sdp_brdma2dp_alu_pd; +output sdp_brdma2dp_mul_valid; +input sdp_brdma2dp_mul_ready; +output [8*16:0] sdp_brdma2dp_mul_pd; +output sdp_n2mcif_rd_cdt_lat_fifo_pop; +output sdp_n2mcif_rd_req_valid; +input sdp_n2mcif_rd_req_ready; +output [47 -1:0] sdp_n2mcif_rd_req_pd; +input mcif2sdp_n_rd_rsp_valid; +output mcif2sdp_n_rd_rsp_ready; +input [65 -1:0] mcif2sdp_n_rd_rsp_pd; +output sdp_nrdma2dp_alu_valid; +input sdp_nrdma2dp_alu_ready; +output [8*16:0] sdp_nrdma2dp_alu_pd; +output sdp_nrdma2dp_mul_valid; +input sdp_nrdma2dp_mul_ready; +output [8*16:0] sdp_nrdma2dp_mul_pd; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +reg mrdma_done_pending; +wire dp2reg_done; +wire [31:0] dp2reg_mrdma_stall; +wire [31:0] dp2reg_status_inf_input_num; +wire [31:0] dp2reg_status_nan_input_num; +wire mrdma_disable; +wire nrdma_disable; +wire brdma_disable; +wire erdma_disable; +wire mrdma_done; +wire nrdma_done; +wire brdma_done; +wire erdma_done; +wire mrdma_op_en; +wire mrdma_slcg_op_en; +wire nrdma_slcg_op_en; +wire brdma_slcg_op_en; +wire erdma_slcg_op_en; +wire [4:0] reg2dp_batch_number; +wire nrdma_op_en; +wire reg2dp_nrdma_data_mode; +wire reg2dp_nrdma_data_size; +wire [1:0] reg2dp_nrdma_data_use; +wire reg2dp_nrdma_disable; +wire reg2dp_nrdma_ram_type; +wire [31:0] reg2dp_bn_base_addr_high; +wire [31:0] reg2dp_bn_base_addr_low; +wire [31:0] reg2dp_bn_batch_stride; +wire [31:0] reg2dp_bn_line_stride; +wire [31:0] reg2dp_bn_surface_stride; +wire [31:0] dp2reg_nrdma_stall; +wire brdma_op_en; +wire reg2dp_brdma_data_mode; +wire reg2dp_brdma_data_size; +wire [1:0] reg2dp_brdma_data_use; +wire reg2dp_brdma_disable; +wire reg2dp_brdma_ram_type; +wire [31:0] reg2dp_bs_base_addr_high; +wire [31:0] reg2dp_bs_base_addr_low; +wire [31:0] reg2dp_bs_batch_stride; +wire [31:0] reg2dp_bs_line_stride; +wire [31:0] reg2dp_bs_surface_stride; +wire [31:0] dp2reg_brdma_stall; +wire reg2dp_op_en; +wire reg2dp_flying_mode; +wire reg2dp_src_ram_type; +wire [1:0] reg2dp_in_precision; +wire [1:0] reg2dp_out_precision; +wire reg2dp_perf_dma_en; +wire reg2dp_perf_nan_inf_count_en; +wire [1:0] reg2dp_proc_precision; +wire [31:0] reg2dp_src_base_addr_high; +wire [31:0] reg2dp_src_base_addr_low; +wire [31:0] reg2dp_src_line_stride; +wire [31:0] reg2dp_src_surface_stride; +wire [12:0] reg2dp_width; +wire [12:0] reg2dp_height; +wire [12:0] reg2dp_channel; +wire reg2dp_winograd; +wire [3:0] slcg_op_en; +//======================================= +// M-RDMA +NV_NVDLA_SDP_mrdma u_mrdma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.mrdma_slcg_op_en (mrdma_slcg_op_en) //|< w + ,.mrdma_disable (mrdma_disable) //|< w + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) //|< i + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[47 -1:0]) //|> o + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) //|> o + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[65 -1:0]) //|< i + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) //|> o + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) //|< i + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) //|> o + ,.reg2dp_op_en (mrdma_op_en) //|< w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:3]) //|< w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:3]) //|< w + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:3]) //|< w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|< w + ,.dp2reg_done (mrdma_done) //|> w + ,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|> w + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|> w + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|> w + ); +NV_NVDLA_SDP_brdma u_brdma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.brdma_slcg_op_en (brdma_slcg_op_en) //|< w + ,.brdma_disable (brdma_disable) //|< w + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) //|> o + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) //|< i + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[47 -1:0]) //|> o + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|< i + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|> o + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[65 -1:0]) //|< i + ,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) //|> o + ,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) //|< i + ,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) //|> o + ,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) //|< i + ,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) //|> o + ,.reg2dp_op_en (brdma_op_en) //|< w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w + ,.reg2dp_winograd (reg2dp_winograd) //|< w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.reg2dp_brdma_data_mode (reg2dp_brdma_data_mode) //|< w + ,.reg2dp_brdma_data_size (reg2dp_brdma_data_size) //|< w + ,.reg2dp_brdma_data_use (reg2dp_brdma_data_use[1:0]) //|< w + ,.reg2dp_brdma_ram_type (reg2dp_brdma_ram_type) //|< w + ,.reg2dp_bs_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|< w + ,.reg2dp_bs_base_addr_low (reg2dp_bs_base_addr_low[31:3]) //|< w + ,.reg2dp_bs_line_stride (reg2dp_bs_line_stride[31:3]) //|< w + ,.reg2dp_bs_surface_stride (reg2dp_bs_surface_stride[31:3]) //|< w + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w + ,.dp2reg_brdma_stall (dp2reg_brdma_stall[31:0]) //|> w + ,.dp2reg_done (brdma_done) //|> w + ); +NV_NVDLA_SDP_nrdma u_nrdma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nrdma_slcg_op_en (nrdma_slcg_op_en) //|< w + ,.nrdma_disable (nrdma_disable) //|< w + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) //|> o + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) //|< i + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[47 -1:0]) //|> o + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|< i + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|> o + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[65 -1:0]) //|< i + ,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) //|> o + ,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) //|< i + ,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) //|> o + ,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) //|< i + ,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) //|> o + ,.reg2dp_op_en (nrdma_op_en) //|< w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w + ,.reg2dp_winograd (reg2dp_winograd) //|< w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.reg2dp_nrdma_data_mode (reg2dp_nrdma_data_mode) //|< w + ,.reg2dp_nrdma_data_size (reg2dp_nrdma_data_size) //|< w + ,.reg2dp_nrdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< w + ,.reg2dp_nrdma_ram_type (reg2dp_nrdma_ram_type) //|< w + ,.reg2dp_bn_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|< w + ,.reg2dp_bn_base_addr_low (reg2dp_bn_base_addr_low[31:3]) //|< w + ,.reg2dp_bn_line_stride (reg2dp_bn_line_stride[31:3]) //|< w + ,.reg2dp_bn_surface_stride (reg2dp_bn_surface_stride[31:3]) //|< w + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w + ,.dp2reg_done (nrdma_done) //|> w + ,.dp2reg_nrdma_stall (dp2reg_nrdma_stall[31:0]) //|> w + ); +//======================================= +// Configuration Register File +assign mrdma_slcg_op_en = slcg_op_en[0]; +assign brdma_slcg_op_en = slcg_op_en[1]; +assign nrdma_slcg_op_en = slcg_op_en[2]; +assign erdma_slcg_op_en = slcg_op_en[3]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mrdma_done_pending <= 1'b0; + end else begin + if (dp2reg_done) begin + mrdma_done_pending <= 1'b0; + end else if (mrdma_done) begin + mrdma_done_pending <= 1'b1; + end + end +end +assign mrdma_op_en = reg2dp_op_en & ~mrdma_done_pending & ~mrdma_disable; +reg brdma_done_pending; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + brdma_done_pending <= 1'b0; + end else begin + if (dp2reg_done) begin + brdma_done_pending <= 1'b0; + end else if (brdma_done) begin + brdma_done_pending <= 1'b1; + end + end +end +assign brdma_op_en = reg2dp_op_en & ~brdma_done_pending & ~brdma_disable; +reg nrdma_done_pending; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nrdma_done_pending <= 1'b0; + end else begin + if (dp2reg_done) begin + nrdma_done_pending <= 1'b0; + end else if (nrdma_done) begin + nrdma_done_pending <= 1'b1; + end + end +end +assign nrdma_op_en = reg2dp_op_en & ~nrdma_done_pending & ~nrdma_disable; +wire erdma_done_pending = 1'b0; +assign erdma_done = 1'b0; +assign dp2reg_done = reg2dp_op_en & ((mrdma_done_pending || mrdma_done || mrdma_disable)&(brdma_done_pending || brdma_done || brdma_disable)&(nrdma_done_pending || nrdma_done || nrdma_disable)&(erdma_done_pending || erdma_done || erdma_disable)); +assign mrdma_disable = reg2dp_flying_mode == 1'h1 ; +assign brdma_disable = reg2dp_brdma_disable == 1'h1 ; +assign nrdma_disable = reg2dp_nrdma_disable == 1'h1 ; +assign erdma_disable = 1'h1 ; +NV_NVDLA_SDP_RDMA_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) //|< i + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) //|< i + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) //|> o + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) //|> o + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) //|> o + ,.slcg_op_en (slcg_op_en[3:0]) //|> w + ,.dp2reg_done (dp2reg_done) //|< w + ,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|< w + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|< w + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|< w + ,.reg2dp_nrdma_data_mode (reg2dp_nrdma_data_mode) //|> w + ,.reg2dp_nrdma_data_size (reg2dp_nrdma_data_size) //|> w + ,.reg2dp_nrdma_data_use (reg2dp_nrdma_data_use[1:0]) //|> w + ,.reg2dp_nrdma_disable (reg2dp_nrdma_disable) //|> w + ,.reg2dp_nrdma_ram_type (reg2dp_nrdma_ram_type) //|> w + ,.reg2dp_bn_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|> w + ,.reg2dp_bn_base_addr_low (reg2dp_bn_base_addr_low[31:0]) //|> w + ,.reg2dp_bn_batch_stride (reg2dp_bn_batch_stride[31:0]) //|> w + ,.reg2dp_bn_line_stride (reg2dp_bn_line_stride[31:0]) //|> w + ,.reg2dp_bn_surface_stride (reg2dp_bn_surface_stride[31:0]) //|> w + ,.dp2reg_nrdma_stall (dp2reg_nrdma_stall[31:0]) //|< w + ,.reg2dp_brdma_data_mode (reg2dp_brdma_data_mode) //|> w + ,.reg2dp_brdma_data_size (reg2dp_brdma_data_size) //|> w + ,.reg2dp_brdma_data_use (reg2dp_brdma_data_use[1:0]) //|> w + ,.reg2dp_brdma_disable (reg2dp_brdma_disable) //|> w + ,.reg2dp_brdma_ram_type (reg2dp_brdma_ram_type) //|> w + ,.reg2dp_bs_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|> w + ,.reg2dp_bs_base_addr_low (reg2dp_bs_base_addr_low[31:0]) //|> w + ,.reg2dp_bs_batch_stride (reg2dp_bs_batch_stride[31:0]) //|> w + ,.reg2dp_bs_line_stride (reg2dp_bs_line_stride[31:0]) //|> w + ,.reg2dp_bs_surface_stride (reg2dp_bs_surface_stride[31:0]) //|> w + ,.dp2reg_brdma_stall (dp2reg_brdma_stall[31:0]) //|< w + ,.dp2reg_erdma_stall (32'h0) + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|> w + ,.reg2dp_winograd (reg2dp_winograd) //|> w + ,.reg2dp_flying_mode (reg2dp_flying_mode) //|> w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|> w + ,.reg2dp_height (reg2dp_height[12:0]) //|> w + ,.reg2dp_width (reg2dp_width[12:0]) //|> w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|> w + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|> w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|> w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|> w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) //|> w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) //|> w + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) //|> w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|> w + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|> w + ); +endmodule // NV_NVDLA_SDP_rdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v.vcp new file mode 100644 index 0000000..2240d12 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v.vcp @@ -0,0 +1,405 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_rdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_rdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp_brdma2dp_alu_ready //|< i + ,sdp_brdma2dp_mul_ready //|< i + ,sdp_brdma2dp_alu_pd //|> o + ,sdp_brdma2dp_alu_valid //|> o + ,sdp_brdma2dp_mul_pd //|> o + ,sdp_brdma2dp_mul_valid //|> o + ,sdp_nrdma2dp_alu_ready //|< i + ,sdp_nrdma2dp_mul_ready //|< i + ,sdp_nrdma2dp_alu_pd //|> o + ,sdp_nrdma2dp_alu_valid //|> o + ,sdp_nrdma2dp_mul_pd //|> o + ,sdp_nrdma2dp_mul_valid //|> o + ,sdp_mrdma2cmux_ready //|< i + ,sdp_mrdma2cmux_pd //|> o + ,sdp_mrdma2cmux_valid //|> o + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,csb2sdp_rdma_req_prdy //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ); +// +// NV_NVDLA_SDP_rdma_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +input csb2sdp_rdma_req_pvld; +output csb2sdp_rdma_req_prdy; +input [62:0] csb2sdp_rdma_req_pd; +output sdp_rdma2csb_resp_valid; +output [33:0] sdp_rdma2csb_resp_pd; +output sdp2mcif_rd_cdt_lat_fifo_pop; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +output [47 -1:0] sdp2mcif_rd_req_pd; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +input [65 -1:0] mcif2sdp_rd_rsp_pd; +output sdp_b2mcif_rd_cdt_lat_fifo_pop; +output sdp_b2mcif_rd_req_valid; +input sdp_b2mcif_rd_req_ready; +output [47 -1:0] sdp_b2mcif_rd_req_pd; +input mcif2sdp_b_rd_rsp_valid; +output mcif2sdp_b_rd_rsp_ready; +input [65 -1:0] mcif2sdp_b_rd_rsp_pd; +output sdp_brdma2dp_alu_valid; +input sdp_brdma2dp_alu_ready; +output [8*16:0] sdp_brdma2dp_alu_pd; +output sdp_brdma2dp_mul_valid; +input sdp_brdma2dp_mul_ready; +output [8*16:0] sdp_brdma2dp_mul_pd; +output sdp_n2mcif_rd_cdt_lat_fifo_pop; +output sdp_n2mcif_rd_req_valid; +input sdp_n2mcif_rd_req_ready; +output [47 -1:0] sdp_n2mcif_rd_req_pd; +input mcif2sdp_n_rd_rsp_valid; +output mcif2sdp_n_rd_rsp_ready; +input [65 -1:0] mcif2sdp_n_rd_rsp_pd; +output sdp_nrdma2dp_alu_valid; +input sdp_nrdma2dp_alu_ready; +output [8*16:0] sdp_nrdma2dp_alu_pd; +output sdp_nrdma2dp_mul_valid; +input sdp_nrdma2dp_mul_ready; +output [8*16:0] sdp_nrdma2dp_mul_pd; +output sdp_mrdma2cmux_valid; +input sdp_mrdma2cmux_ready; +output [32*8 +1:0] sdp_mrdma2cmux_pd; +reg mrdma_done_pending; +wire dp2reg_done; +wire [31:0] dp2reg_mrdma_stall; +wire [31:0] dp2reg_status_inf_input_num; +wire [31:0] dp2reg_status_nan_input_num; +wire mrdma_disable; +wire nrdma_disable; +wire brdma_disable; +wire erdma_disable; +wire mrdma_done; +wire nrdma_done; +wire brdma_done; +wire erdma_done; +wire mrdma_op_en; +wire mrdma_slcg_op_en; +wire nrdma_slcg_op_en; +wire brdma_slcg_op_en; +wire erdma_slcg_op_en; +wire [4:0] reg2dp_batch_number; +wire nrdma_op_en; +wire reg2dp_nrdma_data_mode; +wire reg2dp_nrdma_data_size; +wire [1:0] reg2dp_nrdma_data_use; +wire reg2dp_nrdma_disable; +wire reg2dp_nrdma_ram_type; +wire [31:0] reg2dp_bn_base_addr_high; +wire [31:0] reg2dp_bn_base_addr_low; +wire [31:0] reg2dp_bn_batch_stride; +wire [31:0] reg2dp_bn_line_stride; +wire [31:0] reg2dp_bn_surface_stride; +wire [31:0] dp2reg_nrdma_stall; +wire brdma_op_en; +wire reg2dp_brdma_data_mode; +wire reg2dp_brdma_data_size; +wire [1:0] reg2dp_brdma_data_use; +wire reg2dp_brdma_disable; +wire reg2dp_brdma_ram_type; +wire [31:0] reg2dp_bs_base_addr_high; +wire [31:0] reg2dp_bs_base_addr_low; +wire [31:0] reg2dp_bs_batch_stride; +wire [31:0] reg2dp_bs_line_stride; +wire [31:0] reg2dp_bs_surface_stride; +wire [31:0] dp2reg_brdma_stall; +wire reg2dp_op_en; +wire reg2dp_flying_mode; +wire reg2dp_src_ram_type; +wire [1:0] reg2dp_in_precision; +wire [1:0] reg2dp_out_precision; +wire reg2dp_perf_dma_en; +wire reg2dp_perf_nan_inf_count_en; +wire [1:0] reg2dp_proc_precision; +wire [31:0] reg2dp_src_base_addr_high; +wire [31:0] reg2dp_src_base_addr_low; +wire [31:0] reg2dp_src_line_stride; +wire [31:0] reg2dp_src_surface_stride; +wire [12:0] reg2dp_width; +wire [12:0] reg2dp_height; +wire [12:0] reg2dp_channel; +wire reg2dp_winograd; +wire [3:0] slcg_op_en; +//======================================= +// M-RDMA +NV_NVDLA_SDP_mrdma u_mrdma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.mrdma_slcg_op_en (mrdma_slcg_op_en) //|< w + ,.mrdma_disable (mrdma_disable) //|< w + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) //|> o + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) //|< i + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[47 -1:0]) //|> o + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) //|< i + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) //|> o + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[65 -1:0]) //|< i + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) //|> o + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) //|< i + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) //|> o + ,.reg2dp_op_en (mrdma_op_en) //|< w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|< w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|< w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:3]) //|< w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:3]) //|< w + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:3]) //|< w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|< w + ,.dp2reg_done (mrdma_done) //|> w + ,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|> w + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|> w + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|> w + ); +NV_NVDLA_SDP_brdma u_brdma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.brdma_slcg_op_en (brdma_slcg_op_en) //|< w + ,.brdma_disable (brdma_disable) //|< w + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) //|> o + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) //|< i + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[47 -1:0]) //|> o + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|< i + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|> o + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[65 -1:0]) //|< i + ,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) //|> o + ,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) //|< i + ,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) //|> o + ,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) //|< i + ,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) //|> o + ,.reg2dp_op_en (brdma_op_en) //|< w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w + ,.reg2dp_winograd (reg2dp_winograd) //|< w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.reg2dp_brdma_data_mode (reg2dp_brdma_data_mode) //|< w + ,.reg2dp_brdma_data_size (reg2dp_brdma_data_size) //|< w + ,.reg2dp_brdma_data_use (reg2dp_brdma_data_use[1:0]) //|< w + ,.reg2dp_brdma_ram_type (reg2dp_brdma_ram_type) //|< w + ,.reg2dp_bs_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|< w + ,.reg2dp_bs_base_addr_low (reg2dp_bs_base_addr_low[31:3]) //|< w + ,.reg2dp_bs_line_stride (reg2dp_bs_line_stride[31:3]) //|< w + ,.reg2dp_bs_surface_stride (reg2dp_bs_surface_stride[31:3]) //|< w + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w + ,.dp2reg_brdma_stall (dp2reg_brdma_stall[31:0]) //|> w + ,.dp2reg_done (brdma_done) //|> w + ); +NV_NVDLA_SDP_nrdma u_nrdma ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nrdma_slcg_op_en (nrdma_slcg_op_en) //|< w + ,.nrdma_disable (nrdma_disable) //|< w + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) //|> o + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) //|> o + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) //|< i + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[47 -1:0]) //|> o + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|< i + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|> o + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[65 -1:0]) //|< i + ,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) //|> o + ,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) //|< i + ,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) //|> o + ,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) //|> o + ,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) //|< i + ,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) //|> o + ,.reg2dp_op_en (nrdma_op_en) //|< w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< w + ,.reg2dp_winograd (reg2dp_winograd) //|< w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< w + ,.reg2dp_height (reg2dp_height[12:0]) //|< w + ,.reg2dp_width (reg2dp_width[12:0]) //|< w + ,.reg2dp_nrdma_data_mode (reg2dp_nrdma_data_mode) //|< w + ,.reg2dp_nrdma_data_size (reg2dp_nrdma_data_size) //|< w + ,.reg2dp_nrdma_data_use (reg2dp_nrdma_data_use[1:0]) //|< w + ,.reg2dp_nrdma_ram_type (reg2dp_nrdma_ram_type) //|< w + ,.reg2dp_bn_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|< w + ,.reg2dp_bn_base_addr_low (reg2dp_bn_base_addr_low[31:3]) //|< w + ,.reg2dp_bn_line_stride (reg2dp_bn_line_stride[31:3]) //|< w + ,.reg2dp_bn_surface_stride (reg2dp_bn_surface_stride[31:3]) //|< w + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|< w + ,.dp2reg_done (nrdma_done) //|> w + ,.dp2reg_nrdma_stall (dp2reg_nrdma_stall[31:0]) //|> w + ); +//======================================= +// Configuration Register File +assign mrdma_slcg_op_en = slcg_op_en[0]; +assign brdma_slcg_op_en = slcg_op_en[1]; +assign nrdma_slcg_op_en = slcg_op_en[2]; +assign erdma_slcg_op_en = slcg_op_en[3]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + mrdma_done_pending <= 1'b0; + end else begin + if (dp2reg_done) begin + mrdma_done_pending <= 1'b0; + end else if (mrdma_done) begin + mrdma_done_pending <= 1'b1; + end + end +end +assign mrdma_op_en = reg2dp_op_en & ~mrdma_done_pending & ~mrdma_disable; +reg brdma_done_pending; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + brdma_done_pending <= 1'b0; + end else begin + if (dp2reg_done) begin + brdma_done_pending <= 1'b0; + end else if (brdma_done) begin + brdma_done_pending <= 1'b1; + end + end +end +assign brdma_op_en = reg2dp_op_en & ~brdma_done_pending & ~brdma_disable; +reg nrdma_done_pending; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + nrdma_done_pending <= 1'b0; + end else begin + if (dp2reg_done) begin + nrdma_done_pending <= 1'b0; + end else if (nrdma_done) begin + nrdma_done_pending <= 1'b1; + end + end +end +assign nrdma_op_en = reg2dp_op_en & ~nrdma_done_pending & ~nrdma_disable; +wire erdma_done_pending = 1'b0; +assign erdma_done = 1'b0; +assign dp2reg_done = reg2dp_op_en & ((mrdma_done_pending || mrdma_done || mrdma_disable)&(brdma_done_pending || brdma_done || brdma_disable)&(nrdma_done_pending || nrdma_done || nrdma_disable)&(erdma_done_pending || erdma_done || erdma_disable)); +assign mrdma_disable = reg2dp_flying_mode == 1'h1 ; +assign brdma_disable = reg2dp_brdma_disable == 1'h1 ; +assign nrdma_disable = reg2dp_nrdma_disable == 1'h1 ; +assign erdma_disable = 1'h1 ; +NV_NVDLA_SDP_RDMA_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) //|< i + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) //|< i + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) //|> o + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) //|> o + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) //|> o + ,.slcg_op_en (slcg_op_en[3:0]) //|> w + ,.dp2reg_done (dp2reg_done) //|< w + ,.dp2reg_mrdma_stall (dp2reg_mrdma_stall[31:0]) //|< w + ,.dp2reg_status_inf_input_num (dp2reg_status_inf_input_num[31:0]) //|< w + ,.dp2reg_status_nan_input_num (dp2reg_status_nan_input_num[31:0]) //|< w + ,.reg2dp_nrdma_data_mode (reg2dp_nrdma_data_mode) //|> w + ,.reg2dp_nrdma_data_size (reg2dp_nrdma_data_size) //|> w + ,.reg2dp_nrdma_data_use (reg2dp_nrdma_data_use[1:0]) //|> w + ,.reg2dp_nrdma_disable (reg2dp_nrdma_disable) //|> w + ,.reg2dp_nrdma_ram_type (reg2dp_nrdma_ram_type) //|> w + ,.reg2dp_bn_base_addr_high (reg2dp_bn_base_addr_high[31:0]) //|> w + ,.reg2dp_bn_base_addr_low (reg2dp_bn_base_addr_low[31:0]) //|> w + ,.reg2dp_bn_batch_stride (reg2dp_bn_batch_stride[31:0]) //|> w + ,.reg2dp_bn_line_stride (reg2dp_bn_line_stride[31:0]) //|> w + ,.reg2dp_bn_surface_stride (reg2dp_bn_surface_stride[31:0]) //|> w + ,.dp2reg_nrdma_stall (dp2reg_nrdma_stall[31:0]) //|< w + ,.reg2dp_brdma_data_mode (reg2dp_brdma_data_mode) //|> w + ,.reg2dp_brdma_data_size (reg2dp_brdma_data_size) //|> w + ,.reg2dp_brdma_data_use (reg2dp_brdma_data_use[1:0]) //|> w + ,.reg2dp_brdma_disable (reg2dp_brdma_disable) //|> w + ,.reg2dp_brdma_ram_type (reg2dp_brdma_ram_type) //|> w + ,.reg2dp_bs_base_addr_high (reg2dp_bs_base_addr_high[31:0]) //|> w + ,.reg2dp_bs_base_addr_low (reg2dp_bs_base_addr_low[31:0]) //|> w + ,.reg2dp_bs_batch_stride (reg2dp_bs_batch_stride[31:0]) //|> w + ,.reg2dp_bs_line_stride (reg2dp_bs_line_stride[31:0]) //|> w + ,.reg2dp_bs_surface_stride (reg2dp_bs_surface_stride[31:0]) //|> w + ,.dp2reg_brdma_stall (dp2reg_brdma_stall[31:0]) //|< w + ,.dp2reg_erdma_stall (32'h0) + ,.reg2dp_op_en (reg2dp_op_en) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|> w + ,.reg2dp_winograd (reg2dp_winograd) //|> w + ,.reg2dp_flying_mode (reg2dp_flying_mode) //|> w + ,.reg2dp_channel (reg2dp_channel[12:0]) //|> w + ,.reg2dp_height (reg2dp_height[12:0]) //|> w + ,.reg2dp_width (reg2dp_width[12:0]) //|> w + ,.reg2dp_in_precision (reg2dp_in_precision[1:0]) //|> w + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|> w + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|> w + ,.reg2dp_src_ram_type (reg2dp_src_ram_type) //|> w + ,.reg2dp_src_base_addr_high (reg2dp_src_base_addr_high[31:0]) //|> w + ,.reg2dp_src_base_addr_low (reg2dp_src_base_addr_low[31:0]) //|> w + ,.reg2dp_src_line_stride (reg2dp_src_line_stride[31:0]) //|> w + ,.reg2dp_src_surface_stride (reg2dp_src_surface_stride[31:0]) //|> w + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) //|> w + ,.reg2dp_perf_nan_inf_count_en (reg2dp_perf_nan_inf_count_en) //|> w + ); +endmodule // NV_NVDLA_SDP_rdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_reg.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_reg.v new file mode 100644 index 0000000..8b2d02e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_reg.v @@ -0,0 +1,3326 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_reg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2sdp_req_pd //|< i + ,csb2sdp_req_pvld //|< i + ,dp2reg_done //|< i + ,dp2reg_lut_hybrid //|< i + ,dp2reg_lut_int_data //|< i + ,dp2reg_lut_le_hit //|< i + ,dp2reg_lut_lo_hit //|< i + ,dp2reg_lut_oflow //|< i + ,dp2reg_lut_uflow //|< i + ,dp2reg_out_saturation //|< i + ,dp2reg_status_inf_input_num //|< i + ,dp2reg_status_nan_input_num //|< i + ,dp2reg_status_nan_output_num //|< i + ,dp2reg_status_unequal //|< i + ,dp2reg_wdma_stall //|< i + ,csb2sdp_req_prdy //|> o + ,reg2dp_batch_number //|> o + ,reg2dp_bcore_slcg_op_en //|> o + ,reg2dp_bn_alu_algo //|> o + ,reg2dp_bn_alu_bypass //|> o + ,reg2dp_bn_alu_operand //|> o + ,reg2dp_bn_alu_shift_value //|> o + ,reg2dp_bn_alu_src //|> o + ,reg2dp_bn_bypass //|> o + ,reg2dp_bn_mul_bypass //|> o + ,reg2dp_bn_mul_operand //|> o + ,reg2dp_bn_mul_prelu //|> o + ,reg2dp_bn_mul_shift_value //|> o + ,reg2dp_bn_mul_src //|> o + ,reg2dp_bn_relu_bypass //|> o + ,reg2dp_bs_alu_algo //|> o + ,reg2dp_bs_alu_bypass //|> o + ,reg2dp_bs_alu_operand //|> o + ,reg2dp_bs_alu_shift_value //|> o + ,reg2dp_bs_alu_src //|> o + ,reg2dp_bs_bypass //|> o + ,reg2dp_bs_mul_bypass //|> o + ,reg2dp_bs_mul_operand //|> o + ,reg2dp_bs_mul_prelu //|> o + ,reg2dp_bs_mul_shift_value //|> o + ,reg2dp_bs_mul_src //|> o + ,reg2dp_bs_relu_bypass //|> o + ,reg2dp_channel //|> o + ,reg2dp_cvt_offset //|> o + ,reg2dp_cvt_scale //|> o + ,reg2dp_cvt_shift //|> o + ,reg2dp_dst_base_addr_high //|> o + ,reg2dp_dst_base_addr_low //|> o + ,reg2dp_dst_batch_stride //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_ram_type //|> o + ,reg2dp_dst_surface_stride //|> o + ,reg2dp_ecore_slcg_op_en //|> o + ,reg2dp_ew_alu_algo //|> o + ,reg2dp_ew_alu_bypass //|> o + ,reg2dp_ew_alu_cvt_bypass //|> o + ,reg2dp_ew_alu_cvt_offset //|> o + ,reg2dp_ew_alu_cvt_scale //|> o + ,reg2dp_ew_alu_cvt_truncate //|> o + ,reg2dp_ew_alu_operand //|> o + ,reg2dp_ew_alu_src //|> o + ,reg2dp_ew_bypass //|> o + ,reg2dp_ew_lut_bypass //|> o + ,reg2dp_ew_mul_bypass //|> o + ,reg2dp_ew_mul_cvt_bypass //|> o + ,reg2dp_ew_mul_cvt_offset //|> o + ,reg2dp_ew_mul_cvt_scale //|> o + ,reg2dp_ew_mul_cvt_truncate //|> o + ,reg2dp_ew_mul_operand //|> o + ,reg2dp_ew_mul_prelu //|> o + ,reg2dp_ew_mul_src //|> o + ,reg2dp_ew_truncate //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_height //|> o + ,reg2dp_interrupt_ptr //|> o + ,reg2dp_lut_hybrid_priority //|> o + ,reg2dp_lut_int_access_type //|> o + ,reg2dp_lut_int_addr //|> o + ,reg2dp_lut_int_data //|> o + ,reg2dp_lut_int_data_wr //|> o + ,reg2dp_lut_int_table_id //|> o + ,reg2dp_lut_le_end //|> o + ,reg2dp_lut_le_function //|> o + ,reg2dp_lut_le_index_offset //|> o + ,reg2dp_lut_le_index_select //|> o + ,reg2dp_lut_le_slope_oflow_scale //|> o + ,reg2dp_lut_le_slope_oflow_shift //|> o + ,reg2dp_lut_le_slope_uflow_scale //|> o + ,reg2dp_lut_le_slope_uflow_shift //|> o + ,reg2dp_lut_le_start //|> o + ,reg2dp_lut_lo_end //|> o + ,reg2dp_lut_lo_index_select //|> o + ,reg2dp_lut_lo_slope_oflow_scale //|> o + ,reg2dp_lut_lo_slope_oflow_shift //|> o + ,reg2dp_lut_lo_slope_uflow_scale //|> o + ,reg2dp_lut_lo_slope_uflow_shift //|> o + ,reg2dp_lut_lo_start //|> o + ,reg2dp_lut_oflow_priority //|> o + ,reg2dp_lut_slcg_en //|> o + ,reg2dp_lut_uflow_priority //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_ncore_slcg_op_en //|> o + ,reg2dp_op_en //|> o + ,reg2dp_out_precision //|> o + ,reg2dp_output_dst //|> o + ,reg2dp_perf_dma_en //|> o + ,reg2dp_perf_lut_en //|> o + ,reg2dp_perf_nan_inf_count_en //|> o + ,reg2dp_perf_sat_en //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_wdma_slcg_op_en //|> o + ,reg2dp_width //|> o + ,reg2dp_winograd //|> o + ,sdp2csb_resp_pd //|> o + ,sdp2csb_resp_valid //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2sdp_req_pd; +input csb2sdp_req_pvld; +input dp2reg_done; +input [31:0] dp2reg_lut_hybrid; +input [15:0] dp2reg_lut_int_data; +input [31:0] dp2reg_lut_le_hit; +input [31:0] dp2reg_lut_lo_hit; +input [31:0] dp2reg_lut_oflow; +input [31:0] dp2reg_lut_uflow; +input [31:0] dp2reg_out_saturation; +input [31:0] dp2reg_status_inf_input_num; +input [31:0] dp2reg_status_nan_input_num; +input [31:0] dp2reg_status_nan_output_num; +input [0:0] dp2reg_status_unequal; +input [31:0] dp2reg_wdma_stall; +output csb2sdp_req_prdy; +output [4:0] reg2dp_batch_number; +output reg2dp_bcore_slcg_op_en; +output [1:0] reg2dp_bn_alu_algo; +output reg2dp_bn_alu_bypass; +output [15:0] reg2dp_bn_alu_operand; +output [5:0] reg2dp_bn_alu_shift_value; +output reg2dp_bn_alu_src; +output reg2dp_bn_bypass; +output reg2dp_bn_mul_bypass; +output [15:0] reg2dp_bn_mul_operand; +output reg2dp_bn_mul_prelu; +output [7:0] reg2dp_bn_mul_shift_value; +output reg2dp_bn_mul_src; +output reg2dp_bn_relu_bypass; +output [1:0] reg2dp_bs_alu_algo; +output reg2dp_bs_alu_bypass; +output [15:0] reg2dp_bs_alu_operand; +output [5:0] reg2dp_bs_alu_shift_value; +output reg2dp_bs_alu_src; +output reg2dp_bs_bypass; +output reg2dp_bs_mul_bypass; +output [15:0] reg2dp_bs_mul_operand; +output reg2dp_bs_mul_prelu; +output [7:0] reg2dp_bs_mul_shift_value; +output reg2dp_bs_mul_src; +output reg2dp_bs_relu_bypass; +output [12:0] reg2dp_channel; +output [31:0] reg2dp_cvt_offset; +output [15:0] reg2dp_cvt_scale; +output [5:0] reg2dp_cvt_shift; +output [31:0] reg2dp_dst_base_addr_high; +output [31:0] reg2dp_dst_base_addr_low; +output [31:0] reg2dp_dst_batch_stride; +output [31:0] reg2dp_dst_line_stride; +output reg2dp_dst_ram_type; +output [31:0] reg2dp_dst_surface_stride; +output reg2dp_ecore_slcg_op_en; +output [1:0] reg2dp_ew_alu_algo; +output reg2dp_ew_alu_bypass; +output reg2dp_ew_alu_cvt_bypass; +output [31:0] reg2dp_ew_alu_cvt_offset; +output [15:0] reg2dp_ew_alu_cvt_scale; +output [5:0] reg2dp_ew_alu_cvt_truncate; +output [31:0] reg2dp_ew_alu_operand; +output reg2dp_ew_alu_src; +output reg2dp_ew_bypass; +output reg2dp_ew_lut_bypass; +output reg2dp_ew_mul_bypass; +output reg2dp_ew_mul_cvt_bypass; +output [31:0] reg2dp_ew_mul_cvt_offset; +output [15:0] reg2dp_ew_mul_cvt_scale; +output [5:0] reg2dp_ew_mul_cvt_truncate; +output [31:0] reg2dp_ew_mul_operand; +output reg2dp_ew_mul_prelu; +output reg2dp_ew_mul_src; +output [9:0] reg2dp_ew_truncate; +output reg2dp_flying_mode; +output [12:0] reg2dp_height; +output reg2dp_interrupt_ptr; +output reg2dp_lut_hybrid_priority; +output reg2dp_lut_int_access_type; +output [9:0] reg2dp_lut_int_addr; +output [15:0] reg2dp_lut_int_data; +output reg2dp_lut_int_data_wr; +output reg2dp_lut_int_table_id; +output [31:0] reg2dp_lut_le_end; +output reg2dp_lut_le_function; +output [7:0] reg2dp_lut_le_index_offset; +output [7:0] reg2dp_lut_le_index_select; +output [15:0] reg2dp_lut_le_slope_oflow_scale; +output [4:0] reg2dp_lut_le_slope_oflow_shift; +output [15:0] reg2dp_lut_le_slope_uflow_scale; +output [4:0] reg2dp_lut_le_slope_uflow_shift; +output [31:0] reg2dp_lut_le_start; +output [31:0] reg2dp_lut_lo_end; +output [7:0] reg2dp_lut_lo_index_select; +output [15:0] reg2dp_lut_lo_slope_oflow_scale; +output [4:0] reg2dp_lut_lo_slope_oflow_shift; +output [15:0] reg2dp_lut_lo_slope_uflow_scale; +output [4:0] reg2dp_lut_lo_slope_uflow_shift; +output [31:0] reg2dp_lut_lo_start; +output reg2dp_lut_oflow_priority; +output reg2dp_lut_slcg_en; +output reg2dp_lut_uflow_priority; +output reg2dp_nan_to_zero; +output reg2dp_ncore_slcg_op_en; +output reg2dp_op_en; +output [1:0] reg2dp_out_precision; +output reg2dp_output_dst; +output reg2dp_perf_dma_en; +output reg2dp_perf_lut_en; +output reg2dp_perf_nan_inf_count_en; +output reg2dp_perf_sat_en; +output [1:0] reg2dp_proc_precision; +output reg2dp_wdma_slcg_op_en; +output [12:0] reg2dp_width; +output reg2dp_winograd; +output [33:0] sdp2csb_resp_pd; +output sdp2csb_resp_valid; +wire bcore_slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [31:0] dp2reg_d0_lut_hybrid_w; +wire [31:0] dp2reg_d0_lut_le_hit_w; +wire [31:0] dp2reg_d0_lut_lo_hit_w; +wire [31:0] dp2reg_d0_lut_oflow_w; +wire [31:0] dp2reg_d0_lut_uflow_w; +wire [31:0] dp2reg_d0_out_saturation_w; +wire [31:0] dp2reg_d0_status_inf_input_num_w; +wire [31:0] dp2reg_d0_status_nan_input_num_w; +wire [31:0] dp2reg_d0_status_nan_output_num_w; +wire dp2reg_d0_status_unequal_w; +wire [31:0] dp2reg_d0_wdma_stall_w; +wire [31:0] dp2reg_d1_lut_hybrid_w; +wire [31:0] dp2reg_d1_lut_le_hit_w; +wire [31:0] dp2reg_d1_lut_lo_hit_w; +wire [31:0] dp2reg_d1_lut_oflow_w; +wire [31:0] dp2reg_d1_lut_uflow_w; +wire [31:0] dp2reg_d1_out_saturation_w; +wire [31:0] dp2reg_d1_status_inf_input_num_w; +wire [31:0] dp2reg_d1_status_nan_input_num_w; +wire [31:0] dp2reg_d1_status_nan_output_num_w; +wire dp2reg_d1_status_unequal_w; +wire [31:0] dp2reg_d1_wdma_stall_w; +wire [15:0] dp2reg_lut_data; +wire ecore_slcg_op_en; +wire lut_int_data_rd_trigger; +wire ncore_slcg_op_en; +wire [4:0] reg2dp_d0_batch_number; +wire [1:0] reg2dp_d0_bn_alu_algo; +wire reg2dp_d0_bn_alu_bypass; +wire [15:0] reg2dp_d0_bn_alu_operand; +wire [5:0] reg2dp_d0_bn_alu_shift_value; +wire reg2dp_d0_bn_alu_src; +wire reg2dp_d0_bn_bypass; +wire reg2dp_d0_bn_mul_bypass; +wire [15:0] reg2dp_d0_bn_mul_operand; +wire reg2dp_d0_bn_mul_prelu; +wire [7:0] reg2dp_d0_bn_mul_shift_value; +wire reg2dp_d0_bn_mul_src; +wire reg2dp_d0_bn_relu_bypass; +wire [1:0] reg2dp_d0_bs_alu_algo; +wire reg2dp_d0_bs_alu_bypass; +wire [15:0] reg2dp_d0_bs_alu_operand; +wire [5:0] reg2dp_d0_bs_alu_shift_value; +wire reg2dp_d0_bs_alu_src; +wire reg2dp_d0_bs_bypass; +wire reg2dp_d0_bs_mul_bypass; +wire [15:0] reg2dp_d0_bs_mul_operand; +wire reg2dp_d0_bs_mul_prelu; +wire [7:0] reg2dp_d0_bs_mul_shift_value; +wire reg2dp_d0_bs_mul_src; +wire reg2dp_d0_bs_relu_bypass; +wire [12:0] reg2dp_d0_channel; +wire [31:0] reg2dp_d0_cvt_offset; +wire [15:0] reg2dp_d0_cvt_scale; +wire [5:0] reg2dp_d0_cvt_shift; +wire [31:0] reg2dp_d0_dst_base_addr_high; +wire [31:0] reg2dp_d0_dst_base_addr_low; +wire [31:0] reg2dp_d0_dst_batch_stride; +wire [31:0] reg2dp_d0_dst_line_stride; +wire reg2dp_d0_dst_ram_type; +wire [31:0] reg2dp_d0_dst_surface_stride; +wire [1:0] reg2dp_d0_ew_alu_algo; +wire reg2dp_d0_ew_alu_bypass; +wire reg2dp_d0_ew_alu_cvt_bypass; +wire [31:0] reg2dp_d0_ew_alu_cvt_offset; +wire [15:0] reg2dp_d0_ew_alu_cvt_scale; +wire [5:0] reg2dp_d0_ew_alu_cvt_truncate; +wire [31:0] reg2dp_d0_ew_alu_operand; +wire reg2dp_d0_ew_alu_src; +wire reg2dp_d0_ew_bypass; +wire reg2dp_d0_ew_lut_bypass; +wire reg2dp_d0_ew_mul_bypass; +wire reg2dp_d0_ew_mul_cvt_bypass; +wire [31:0] reg2dp_d0_ew_mul_cvt_offset; +wire [15:0] reg2dp_d0_ew_mul_cvt_scale; +wire [5:0] reg2dp_d0_ew_mul_cvt_truncate; +wire [31:0] reg2dp_d0_ew_mul_operand; +wire reg2dp_d0_ew_mul_prelu; +wire reg2dp_d0_ew_mul_src; +wire [9:0] reg2dp_d0_ew_truncate; +wire reg2dp_d0_flying_mode; +wire [12:0] reg2dp_d0_height; +wire reg2dp_d0_nan_to_zero; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_out_precision; +wire reg2dp_d0_output_dst; +wire reg2dp_d0_perf_dma_en; +wire reg2dp_d0_perf_lut_en; +wire reg2dp_d0_perf_nan_inf_count_en; +wire reg2dp_d0_perf_sat_en; +wire [1:0] reg2dp_d0_proc_precision; +wire [12:0] reg2dp_d0_width; +wire reg2dp_d0_winograd; +wire [4:0] reg2dp_d1_batch_number; +wire [1:0] reg2dp_d1_bn_alu_algo; +wire reg2dp_d1_bn_alu_bypass; +wire [15:0] reg2dp_d1_bn_alu_operand; +wire [5:0] reg2dp_d1_bn_alu_shift_value; +wire reg2dp_d1_bn_alu_src; +wire reg2dp_d1_bn_bypass; +wire reg2dp_d1_bn_mul_bypass; +wire [15:0] reg2dp_d1_bn_mul_operand; +wire reg2dp_d1_bn_mul_prelu; +wire [7:0] reg2dp_d1_bn_mul_shift_value; +wire reg2dp_d1_bn_mul_src; +wire reg2dp_d1_bn_relu_bypass; +wire [1:0] reg2dp_d1_bs_alu_algo; +wire reg2dp_d1_bs_alu_bypass; +wire [15:0] reg2dp_d1_bs_alu_operand; +wire [5:0] reg2dp_d1_bs_alu_shift_value; +wire reg2dp_d1_bs_alu_src; +wire reg2dp_d1_bs_bypass; +wire reg2dp_d1_bs_mul_bypass; +wire [15:0] reg2dp_d1_bs_mul_operand; +wire reg2dp_d1_bs_mul_prelu; +wire [7:0] reg2dp_d1_bs_mul_shift_value; +wire reg2dp_d1_bs_mul_src; +wire reg2dp_d1_bs_relu_bypass; +wire [12:0] reg2dp_d1_channel; +wire [31:0] reg2dp_d1_cvt_offset; +wire [15:0] reg2dp_d1_cvt_scale; +wire [5:0] reg2dp_d1_cvt_shift; +wire [31:0] reg2dp_d1_dst_base_addr_high; +wire [31:0] reg2dp_d1_dst_base_addr_low; +wire [31:0] reg2dp_d1_dst_batch_stride; +wire [31:0] reg2dp_d1_dst_line_stride; +wire reg2dp_d1_dst_ram_type; +wire [31:0] reg2dp_d1_dst_surface_stride; +wire [1:0] reg2dp_d1_ew_alu_algo; +wire reg2dp_d1_ew_alu_bypass; +wire reg2dp_d1_ew_alu_cvt_bypass; +wire [31:0] reg2dp_d1_ew_alu_cvt_offset; +wire [15:0] reg2dp_d1_ew_alu_cvt_scale; +wire [5:0] reg2dp_d1_ew_alu_cvt_truncate; +wire [31:0] reg2dp_d1_ew_alu_operand; +wire reg2dp_d1_ew_alu_src; +wire reg2dp_d1_ew_bypass; +wire reg2dp_d1_ew_lut_bypass; +wire reg2dp_d1_ew_mul_bypass; +wire reg2dp_d1_ew_mul_cvt_bypass; +wire [31:0] reg2dp_d1_ew_mul_cvt_offset; +wire [15:0] reg2dp_d1_ew_mul_cvt_scale; +wire [5:0] reg2dp_d1_ew_mul_cvt_truncate; +wire [31:0] reg2dp_d1_ew_mul_operand; +wire reg2dp_d1_ew_mul_prelu; +wire reg2dp_d1_ew_mul_src; +wire [9:0] reg2dp_d1_ew_truncate; +wire reg2dp_d1_flying_mode; +wire [12:0] reg2dp_d1_height; +wire reg2dp_d1_nan_to_zero; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_out_precision; +wire reg2dp_d1_output_dst; +wire reg2dp_d1_perf_dma_en; +wire reg2dp_d1_perf_lut_en; +wire reg2dp_d1_perf_nan_inf_count_en; +wire reg2dp_d1_perf_sat_en; +wire [1:0] reg2dp_d1_proc_precision; +wire [12:0] reg2dp_d1_width; +wire reg2dp_d1_winograd; +wire reg2dp_lut_access_type; +wire [9:0] reg2dp_lut_addr; +wire reg2dp_lut_addr_trigger; +wire reg2dp_lut_data_trigger; +wire reg2dp_lut_table_id; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en; +wire [3:0] slcg_op_en_d0; +wire wdma_slcg_op_en; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_lut_hybrid; +reg [31:0] dp2reg_d0_lut_le_hit; +reg [31:0] dp2reg_d0_lut_lo_hit; +reg [31:0] dp2reg_d0_lut_oflow; +reg [31:0] dp2reg_d0_lut_uflow; +reg [31:0] dp2reg_d0_out_saturation; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg [31:0] dp2reg_d0_status_inf_input_num; +reg [31:0] dp2reg_d0_status_nan_input_num; +reg [31:0] dp2reg_d0_status_nan_output_num; +reg dp2reg_d0_status_unequal; +reg [31:0] dp2reg_d0_wdma_stall; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_lut_hybrid; +reg [31:0] dp2reg_d1_lut_le_hit; +reg [31:0] dp2reg_d1_lut_lo_hit; +reg [31:0] dp2reg_d1_lut_oflow; +reg [31:0] dp2reg_d1_lut_uflow; +reg [31:0] dp2reg_d1_out_saturation; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [31:0] dp2reg_d1_status_inf_input_num; +reg [31:0] dp2reg_d1_status_nan_input_num; +reg [31:0] dp2reg_d1_status_nan_output_num; +reg dp2reg_d1_status_unequal; +reg [31:0] dp2reg_d1_wdma_stall; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg lut_int_access_type; +reg [9:0] lut_int_addr; +reg lut_int_addr_trigger; +reg lut_int_data_wr_trigger; +reg lut_int_table_id; +reg [4:0] reg2dp_batch_number; +reg [1:0] reg2dp_bn_alu_algo; +reg reg2dp_bn_alu_bypass; +reg [15:0] reg2dp_bn_alu_operand; +reg [5:0] reg2dp_bn_alu_shift_value; +reg reg2dp_bn_alu_src; +reg reg2dp_bn_bypass; +reg reg2dp_bn_mul_bypass; +reg [15:0] reg2dp_bn_mul_operand; +reg reg2dp_bn_mul_prelu; +reg [7:0] reg2dp_bn_mul_shift_value; +reg reg2dp_bn_mul_src; +reg reg2dp_bn_relu_bypass; +reg [1:0] reg2dp_bs_alu_algo; +reg reg2dp_bs_alu_bypass; +reg [15:0] reg2dp_bs_alu_operand; +reg [5:0] reg2dp_bs_alu_shift_value; +reg reg2dp_bs_alu_src; +reg reg2dp_bs_bypass; +reg reg2dp_bs_mul_bypass; +reg [15:0] reg2dp_bs_mul_operand; +reg reg2dp_bs_mul_prelu; +reg [7:0] reg2dp_bs_mul_shift_value; +reg reg2dp_bs_mul_src; +reg reg2dp_bs_relu_bypass; +reg [12:0] reg2dp_channel; +reg [31:0] reg2dp_cvt_offset; +reg [15:0] reg2dp_cvt_scale; +reg [5:0] reg2dp_cvt_shift; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [31:0] reg2dp_dst_base_addr_high; +reg [31:0] reg2dp_dst_base_addr_low; +reg [31:0] reg2dp_dst_batch_stride; +reg [31:0] reg2dp_dst_line_stride; +reg reg2dp_dst_ram_type; +reg [31:0] reg2dp_dst_surface_stride; +reg [1:0] reg2dp_ew_alu_algo; +reg reg2dp_ew_alu_bypass; +reg reg2dp_ew_alu_cvt_bypass; +reg [31:0] reg2dp_ew_alu_cvt_offset; +reg [15:0] reg2dp_ew_alu_cvt_scale; +reg [5:0] reg2dp_ew_alu_cvt_truncate; +reg [31:0] reg2dp_ew_alu_operand; +reg reg2dp_ew_alu_src; +reg reg2dp_ew_bypass; +reg reg2dp_ew_lut_bypass; +reg reg2dp_ew_mul_bypass; +reg reg2dp_ew_mul_cvt_bypass; +reg [31:0] reg2dp_ew_mul_cvt_offset; +reg [15:0] reg2dp_ew_mul_cvt_scale; +reg [5:0] reg2dp_ew_mul_cvt_truncate; +reg [31:0] reg2dp_ew_mul_operand; +reg reg2dp_ew_mul_prelu; +reg reg2dp_ew_mul_src; +reg [9:0] reg2dp_ew_truncate; +reg reg2dp_flying_mode; +reg [12:0] reg2dp_height; +reg [15:0] reg2dp_lut_int_data; +reg reg2dp_lut_slcg_en; +reg reg2dp_nan_to_zero; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_out_precision; +reg reg2dp_output_dst; +reg reg2dp_perf_dma_en; +reg reg2dp_perf_lut_en; +reg reg2dp_perf_nan_inf_count_en; +reg reg2dp_perf_sat_en; +reg [1:0] reg2dp_proc_precision; +reg [12:0] reg2dp_width; +reg reg2dp_winograd; +reg [62:0] req_pd; +reg req_pvld; +reg [33:0] sdp2csb_resp_pd; +reg sdp2csb_resp_valid; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_SDP_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_access_type (reg2dp_lut_access_type) //|> w + ,.lut_addr (reg2dp_lut_addr[9:0]) //|> w + ,.lut_addr_trigger (reg2dp_lut_addr_trigger) //|> w + ,.lut_table_id (reg2dp_lut_table_id) //|> w + ,.lut_data_trigger (reg2dp_lut_data_trigger) //|> w + ,.lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|> o + ,.lut_le_function (reg2dp_lut_le_function) //|> o + ,.lut_oflow_priority (reg2dp_lut_oflow_priority) //|> o + ,.lut_uflow_priority (reg2dp_lut_uflow_priority) //|> o + ,.lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|> o + ,.lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|> o + ,.lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|> o + ,.lut_le_end (reg2dp_lut_le_end[31:0]) //|> o + ,.lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|> o + ,.lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|> o + ,.lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|> o + ,.lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|> o + ,.lut_le_start (reg2dp_lut_le_start[31:0]) //|> o + ,.lut_lo_end (reg2dp_lut_lo_end[31:0]) //|> o + ,.lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|> o + ,.lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|> o + ,.lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|> o + ,.lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|> o + ,.lut_lo_start (reg2dp_lut_lo_start[31:0]) //|> o + ,.producer (reg2dp_producer) //|> w + ,.lut_data (dp2reg_lut_data[15:0]) //|< w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_SDP_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_offset (reg2dp_d0_cvt_offset[31:0]) //|> w + ,.cvt_scale (reg2dp_d0_cvt_scale[15:0]) //|> w + ,.cvt_shift (reg2dp_d0_cvt_shift[5:0]) //|> w + ,.channel (reg2dp_d0_channel[12:0]) //|> w + ,.height (reg2dp_d0_height[12:0]) //|> w + ,.width (reg2dp_d0_width[12:0]) //|> w + ,.out_precision (reg2dp_d0_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.bn_alu_shift_value (reg2dp_d0_bn_alu_shift_value[5:0]) //|> w + ,.bn_alu_src (reg2dp_d0_bn_alu_src) //|> w + ,.bn_alu_operand (reg2dp_d0_bn_alu_operand[15:0]) //|> w + ,.bn_alu_algo (reg2dp_d0_bn_alu_algo[1:0]) //|> w + ,.bn_alu_bypass (reg2dp_d0_bn_alu_bypass) //|> w + ,.bn_bypass (reg2dp_d0_bn_bypass) //|> w + ,.bn_mul_bypass (reg2dp_d0_bn_mul_bypass) //|> w + ,.bn_mul_prelu (reg2dp_d0_bn_mul_prelu) //|> w + ,.bn_relu_bypass (reg2dp_d0_bn_relu_bypass) //|> w + ,.bn_mul_shift_value (reg2dp_d0_bn_mul_shift_value[7:0]) //|> w + ,.bn_mul_src (reg2dp_d0_bn_mul_src) //|> w + ,.bn_mul_operand (reg2dp_d0_bn_mul_operand[15:0]) //|> w + ,.bs_alu_shift_value (reg2dp_d0_bs_alu_shift_value[5:0]) //|> w + ,.bs_alu_src (reg2dp_d0_bs_alu_src) //|> w + ,.bs_alu_operand (reg2dp_d0_bs_alu_operand[15:0]) //|> w + ,.bs_alu_algo (reg2dp_d0_bs_alu_algo[1:0]) //|> w + ,.bs_alu_bypass (reg2dp_d0_bs_alu_bypass) //|> w + ,.bs_bypass (reg2dp_d0_bs_bypass) //|> w + ,.bs_mul_bypass (reg2dp_d0_bs_mul_bypass) //|> w + ,.bs_mul_prelu (reg2dp_d0_bs_mul_prelu) //|> w + ,.bs_relu_bypass (reg2dp_d0_bs_relu_bypass) //|> w + ,.bs_mul_shift_value (reg2dp_d0_bs_mul_shift_value[7:0]) //|> w + ,.bs_mul_src (reg2dp_d0_bs_mul_src) //|> w + ,.bs_mul_operand (reg2dp_d0_bs_mul_operand[15:0]) //|> w + ,.ew_alu_cvt_bypass (reg2dp_d0_ew_alu_cvt_bypass) //|> w + ,.ew_alu_src (reg2dp_d0_ew_alu_src) //|> w + ,.ew_alu_cvt_offset (reg2dp_d0_ew_alu_cvt_offset[31:0]) //|> w + ,.ew_alu_cvt_scale (reg2dp_d0_ew_alu_cvt_scale[15:0]) //|> w + ,.ew_alu_cvt_truncate (reg2dp_d0_ew_alu_cvt_truncate[5:0]) //|> w + ,.ew_alu_operand (reg2dp_d0_ew_alu_operand[31:0]) //|> w + ,.ew_alu_algo (reg2dp_d0_ew_alu_algo[1:0]) //|> w + ,.ew_alu_bypass (reg2dp_d0_ew_alu_bypass) //|> w + ,.ew_bypass (reg2dp_d0_ew_bypass) //|> w + ,.ew_lut_bypass (reg2dp_d0_ew_lut_bypass) //|> w + ,.ew_mul_bypass (reg2dp_d0_ew_mul_bypass) //|> w + ,.ew_mul_prelu (reg2dp_d0_ew_mul_prelu) //|> w + ,.ew_mul_cvt_bypass (reg2dp_d0_ew_mul_cvt_bypass) //|> w + ,.ew_mul_src (reg2dp_d0_ew_mul_src) //|> w + ,.ew_mul_cvt_offset (reg2dp_d0_ew_mul_cvt_offset[31:0]) //|> w + ,.ew_mul_cvt_scale (reg2dp_d0_ew_mul_cvt_scale[15:0]) //|> w + ,.ew_mul_cvt_truncate (reg2dp_d0_ew_mul_cvt_truncate[5:0]) //|> w + ,.ew_mul_operand (reg2dp_d0_ew_mul_operand[31:0]) //|> w + ,.ew_truncate (reg2dp_d0_ew_truncate[9:0]) //|> w + ,.dst_base_addr_high (reg2dp_d0_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d0_dst_base_addr_low[31:0]) //|> w + ,.dst_batch_stride (reg2dp_d0_dst_batch_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d0_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d0_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d0_dst_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d0_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.output_dst (reg2dp_d0_output_dst) //|> w + ,.winograd (reg2dp_d0_winograd) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d0_perf_dma_en) //|> w + ,.perf_lut_en (reg2dp_d0_perf_lut_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d0_perf_nan_inf_count_en) //|> w + ,.perf_sat_en (reg2dp_d0_perf_sat_en) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.lut_hybrid (dp2reg_d0_lut_hybrid[31:0]) //|< r + ,.lut_le_hit (dp2reg_d0_lut_le_hit[31:0]) //|< r + ,.lut_lo_hit (dp2reg_d0_lut_lo_hit[31:0]) //|< r + ,.lut_oflow (dp2reg_d0_lut_oflow[31:0]) //|< r + ,.lut_uflow (dp2reg_d0_lut_uflow[31:0]) //|< r + ,.out_saturation (dp2reg_d0_out_saturation[31:0]) //|< r + ,.wdma_stall (dp2reg_d0_wdma_stall[31:0]) //|< r + ,.status_unequal (dp2reg_d0_status_unequal) //|< r + ,.status_inf_input_num (dp2reg_d0_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d0_status_nan_input_num[31:0]) //|< r + ,.status_nan_output_num (dp2reg_d0_status_nan_output_num[31:0]) //|< r + ); +NV_NVDLA_SDP_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_offset (reg2dp_d1_cvt_offset[31:0]) //|> w + ,.cvt_scale (reg2dp_d1_cvt_scale[15:0]) //|> w + ,.cvt_shift (reg2dp_d1_cvt_shift[5:0]) //|> w + ,.channel (reg2dp_d1_channel[12:0]) //|> w + ,.height (reg2dp_d1_height[12:0]) //|> w + ,.width (reg2dp_d1_width[12:0]) //|> w + ,.out_precision (reg2dp_d1_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.bn_alu_shift_value (reg2dp_d1_bn_alu_shift_value[5:0]) //|> w + ,.bn_alu_src (reg2dp_d1_bn_alu_src) //|> w + ,.bn_alu_operand (reg2dp_d1_bn_alu_operand[15:0]) //|> w + ,.bn_alu_algo (reg2dp_d1_bn_alu_algo[1:0]) //|> w + ,.bn_alu_bypass (reg2dp_d1_bn_alu_bypass) //|> w + ,.bn_bypass (reg2dp_d1_bn_bypass) //|> w + ,.bn_mul_bypass (reg2dp_d1_bn_mul_bypass) //|> w + ,.bn_mul_prelu (reg2dp_d1_bn_mul_prelu) //|> w + ,.bn_relu_bypass (reg2dp_d1_bn_relu_bypass) //|> w + ,.bn_mul_shift_value (reg2dp_d1_bn_mul_shift_value[7:0]) //|> w + ,.bn_mul_src (reg2dp_d1_bn_mul_src) //|> w + ,.bn_mul_operand (reg2dp_d1_bn_mul_operand[15:0]) //|> w + ,.bs_alu_shift_value (reg2dp_d1_bs_alu_shift_value[5:0]) //|> w + ,.bs_alu_src (reg2dp_d1_bs_alu_src) //|> w + ,.bs_alu_operand (reg2dp_d1_bs_alu_operand[15:0]) //|> w + ,.bs_alu_algo (reg2dp_d1_bs_alu_algo[1:0]) //|> w + ,.bs_alu_bypass (reg2dp_d1_bs_alu_bypass) //|> w + ,.bs_bypass (reg2dp_d1_bs_bypass) //|> w + ,.bs_mul_bypass (reg2dp_d1_bs_mul_bypass) //|> w + ,.bs_mul_prelu (reg2dp_d1_bs_mul_prelu) //|> w + ,.bs_relu_bypass (reg2dp_d1_bs_relu_bypass) //|> w + ,.bs_mul_shift_value (reg2dp_d1_bs_mul_shift_value[7:0]) //|> w + ,.bs_mul_src (reg2dp_d1_bs_mul_src) //|> w + ,.bs_mul_operand (reg2dp_d1_bs_mul_operand[15:0]) //|> w + ,.ew_alu_cvt_bypass (reg2dp_d1_ew_alu_cvt_bypass) //|> w + ,.ew_alu_src (reg2dp_d1_ew_alu_src) //|> w + ,.ew_alu_cvt_offset (reg2dp_d1_ew_alu_cvt_offset[31:0]) //|> w + ,.ew_alu_cvt_scale (reg2dp_d1_ew_alu_cvt_scale[15:0]) //|> w + ,.ew_alu_cvt_truncate (reg2dp_d1_ew_alu_cvt_truncate[5:0]) //|> w + ,.ew_alu_operand (reg2dp_d1_ew_alu_operand[31:0]) //|> w + ,.ew_alu_algo (reg2dp_d1_ew_alu_algo[1:0]) //|> w + ,.ew_alu_bypass (reg2dp_d1_ew_alu_bypass) //|> w + ,.ew_bypass (reg2dp_d1_ew_bypass) //|> w + ,.ew_lut_bypass (reg2dp_d1_ew_lut_bypass) //|> w + ,.ew_mul_bypass (reg2dp_d1_ew_mul_bypass) //|> w + ,.ew_mul_prelu (reg2dp_d1_ew_mul_prelu) //|> w + ,.ew_mul_cvt_bypass (reg2dp_d1_ew_mul_cvt_bypass) //|> w + ,.ew_mul_src (reg2dp_d1_ew_mul_src) //|> w + ,.ew_mul_cvt_offset (reg2dp_d1_ew_mul_cvt_offset[31:0]) //|> w + ,.ew_mul_cvt_scale (reg2dp_d1_ew_mul_cvt_scale[15:0]) //|> w + ,.ew_mul_cvt_truncate (reg2dp_d1_ew_mul_cvt_truncate[5:0]) //|> w + ,.ew_mul_operand (reg2dp_d1_ew_mul_operand[31:0]) //|> w + ,.ew_truncate (reg2dp_d1_ew_truncate[9:0]) //|> w + ,.dst_base_addr_high (reg2dp_d1_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d1_dst_base_addr_low[31:0]) //|> w + ,.dst_batch_stride (reg2dp_d1_dst_batch_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d1_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d1_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d1_dst_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d1_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.output_dst (reg2dp_d1_output_dst) //|> w + ,.winograd (reg2dp_d1_winograd) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d1_perf_dma_en) //|> w + ,.perf_lut_en (reg2dp_d1_perf_lut_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d1_perf_nan_inf_count_en) //|> w + ,.perf_sat_en (reg2dp_d1_perf_sat_en) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.lut_hybrid (dp2reg_d1_lut_hybrid[31:0]) //|< r + ,.lut_le_hit (dp2reg_d1_lut_le_hit[31:0]) //|< r + ,.lut_lo_hit (dp2reg_d1_lut_lo_hit[31:0]) //|< r + ,.lut_oflow (dp2reg_d1_lut_oflow[31:0]) //|< r + ,.lut_uflow (dp2reg_d1_lut_uflow[31:0]) //|< r + ,.out_saturation (dp2reg_d1_out_saturation[31:0]) //|< r + ,.wdma_stall (dp2reg_d1_wdma_stall[31:0]) //|< r + ,.status_unequal (dp2reg_d1_status_unequal) //|< r + ,.status_inf_input_num (dp2reg_d1_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d1_status_nan_input_num[31:0]) //|< r + ,.status_nan_output_num (dp2reg_d1_status_nan_output_num[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hb038 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hb038 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hb038 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2sdp_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2sdp_req_pvld) == 1'b1) begin + req_pd <= csb2sdp_req_pd; +// VCS coverage off + end else if ((csb2sdp_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2sdp_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2sdp_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + sdp2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + sdp2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2csb_resp_valid <= 1'b0; + end else begin + sdp2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cvt_offset + or reg2dp_d0_cvt_offset + ) begin + reg2dp_cvt_offset = dp2reg_consumer ? reg2dp_d1_cvt_offset : reg2dp_d0_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_scale + or reg2dp_d0_cvt_scale + ) begin + reg2dp_cvt_scale = dp2reg_consumer ? reg2dp_d1_cvt_scale : reg2dp_d0_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_shift + or reg2dp_d0_cvt_shift + ) begin + reg2dp_cvt_shift = dp2reg_consumer ? reg2dp_d1_cvt_shift : reg2dp_d0_cvt_shift; +end +always @( + dp2reg_consumer + or reg2dp_d1_channel + or reg2dp_d0_channel + ) begin + reg2dp_channel = dp2reg_consumer ? reg2dp_d1_channel : reg2dp_d0_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_height + or reg2dp_d0_height + ) begin + reg2dp_height = dp2reg_consumer ? reg2dp_d1_height : reg2dp_d0_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_width + or reg2dp_d0_width + ) begin + reg2dp_width = dp2reg_consumer ? reg2dp_d1_width : reg2dp_d0_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_out_precision + or reg2dp_d0_out_precision + ) begin + reg2dp_out_precision = dp2reg_consumer ? reg2dp_d1_out_precision : reg2dp_d0_out_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_shift_value + or reg2dp_d0_bn_alu_shift_value + ) begin + reg2dp_bn_alu_shift_value = dp2reg_consumer ? reg2dp_d1_bn_alu_shift_value : reg2dp_d0_bn_alu_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_src + or reg2dp_d0_bn_alu_src + ) begin + reg2dp_bn_alu_src = dp2reg_consumer ? reg2dp_d1_bn_alu_src : reg2dp_d0_bn_alu_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_operand + or reg2dp_d0_bn_alu_operand + ) begin + reg2dp_bn_alu_operand = dp2reg_consumer ? reg2dp_d1_bn_alu_operand : reg2dp_d0_bn_alu_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_algo + or reg2dp_d0_bn_alu_algo + ) begin + reg2dp_bn_alu_algo = dp2reg_consumer ? reg2dp_d1_bn_alu_algo : reg2dp_d0_bn_alu_algo; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_bypass + or reg2dp_d0_bn_alu_bypass + ) begin + reg2dp_bn_alu_bypass = dp2reg_consumer ? reg2dp_d1_bn_alu_bypass : reg2dp_d0_bn_alu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_bypass + or reg2dp_d0_bn_bypass + ) begin + reg2dp_bn_bypass = dp2reg_consumer ? reg2dp_d1_bn_bypass : reg2dp_d0_bn_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_bypass + or reg2dp_d0_bn_mul_bypass + ) begin + reg2dp_bn_mul_bypass = dp2reg_consumer ? reg2dp_d1_bn_mul_bypass : reg2dp_d0_bn_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_prelu + or reg2dp_d0_bn_mul_prelu + ) begin + reg2dp_bn_mul_prelu = dp2reg_consumer ? reg2dp_d1_bn_mul_prelu : reg2dp_d0_bn_mul_prelu; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_relu_bypass + or reg2dp_d0_bn_relu_bypass + ) begin + reg2dp_bn_relu_bypass = dp2reg_consumer ? reg2dp_d1_bn_relu_bypass : reg2dp_d0_bn_relu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_shift_value + or reg2dp_d0_bn_mul_shift_value + ) begin + reg2dp_bn_mul_shift_value = dp2reg_consumer ? reg2dp_d1_bn_mul_shift_value : reg2dp_d0_bn_mul_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_src + or reg2dp_d0_bn_mul_src + ) begin + reg2dp_bn_mul_src = dp2reg_consumer ? reg2dp_d1_bn_mul_src : reg2dp_d0_bn_mul_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_operand + or reg2dp_d0_bn_mul_operand + ) begin + reg2dp_bn_mul_operand = dp2reg_consumer ? reg2dp_d1_bn_mul_operand : reg2dp_d0_bn_mul_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_shift_value + or reg2dp_d0_bs_alu_shift_value + ) begin + reg2dp_bs_alu_shift_value = dp2reg_consumer ? reg2dp_d1_bs_alu_shift_value : reg2dp_d0_bs_alu_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_src + or reg2dp_d0_bs_alu_src + ) begin + reg2dp_bs_alu_src = dp2reg_consumer ? reg2dp_d1_bs_alu_src : reg2dp_d0_bs_alu_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_operand + or reg2dp_d0_bs_alu_operand + ) begin + reg2dp_bs_alu_operand = dp2reg_consumer ? reg2dp_d1_bs_alu_operand : reg2dp_d0_bs_alu_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_algo + or reg2dp_d0_bs_alu_algo + ) begin + reg2dp_bs_alu_algo = dp2reg_consumer ? reg2dp_d1_bs_alu_algo : reg2dp_d0_bs_alu_algo; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_bypass + or reg2dp_d0_bs_alu_bypass + ) begin + reg2dp_bs_alu_bypass = dp2reg_consumer ? reg2dp_d1_bs_alu_bypass : reg2dp_d0_bs_alu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_bypass + or reg2dp_d0_bs_bypass + ) begin + reg2dp_bs_bypass = dp2reg_consumer ? reg2dp_d1_bs_bypass : reg2dp_d0_bs_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_bypass + or reg2dp_d0_bs_mul_bypass + ) begin + reg2dp_bs_mul_bypass = dp2reg_consumer ? reg2dp_d1_bs_mul_bypass : reg2dp_d0_bs_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_prelu + or reg2dp_d0_bs_mul_prelu + ) begin + reg2dp_bs_mul_prelu = dp2reg_consumer ? reg2dp_d1_bs_mul_prelu : reg2dp_d0_bs_mul_prelu; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_relu_bypass + or reg2dp_d0_bs_relu_bypass + ) begin + reg2dp_bs_relu_bypass = dp2reg_consumer ? reg2dp_d1_bs_relu_bypass : reg2dp_d0_bs_relu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_shift_value + or reg2dp_d0_bs_mul_shift_value + ) begin + reg2dp_bs_mul_shift_value = dp2reg_consumer ? reg2dp_d1_bs_mul_shift_value : reg2dp_d0_bs_mul_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_src + or reg2dp_d0_bs_mul_src + ) begin + reg2dp_bs_mul_src = dp2reg_consumer ? reg2dp_d1_bs_mul_src : reg2dp_d0_bs_mul_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_operand + or reg2dp_d0_bs_mul_operand + ) begin + reg2dp_bs_mul_operand = dp2reg_consumer ? reg2dp_d1_bs_mul_operand : reg2dp_d0_bs_mul_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_bypass + or reg2dp_d0_ew_alu_cvt_bypass + ) begin + reg2dp_ew_alu_cvt_bypass = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_bypass : reg2dp_d0_ew_alu_cvt_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_src + or reg2dp_d0_ew_alu_src + ) begin + reg2dp_ew_alu_src = dp2reg_consumer ? reg2dp_d1_ew_alu_src : reg2dp_d0_ew_alu_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_offset + or reg2dp_d0_ew_alu_cvt_offset + ) begin + reg2dp_ew_alu_cvt_offset = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_offset : reg2dp_d0_ew_alu_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_scale + or reg2dp_d0_ew_alu_cvt_scale + ) begin + reg2dp_ew_alu_cvt_scale = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_scale : reg2dp_d0_ew_alu_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_truncate + or reg2dp_d0_ew_alu_cvt_truncate + ) begin + reg2dp_ew_alu_cvt_truncate = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_truncate : reg2dp_d0_ew_alu_cvt_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_operand + or reg2dp_d0_ew_alu_operand + ) begin + reg2dp_ew_alu_operand = dp2reg_consumer ? reg2dp_d1_ew_alu_operand : reg2dp_d0_ew_alu_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_algo + or reg2dp_d0_ew_alu_algo + ) begin + reg2dp_ew_alu_algo = dp2reg_consumer ? reg2dp_d1_ew_alu_algo : reg2dp_d0_ew_alu_algo; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_bypass + or reg2dp_d0_ew_alu_bypass + ) begin + reg2dp_ew_alu_bypass = dp2reg_consumer ? reg2dp_d1_ew_alu_bypass : reg2dp_d0_ew_alu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_bypass + or reg2dp_d0_ew_bypass + ) begin + reg2dp_ew_bypass = dp2reg_consumer ? reg2dp_d1_ew_bypass : reg2dp_d0_ew_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_lut_bypass + or reg2dp_d0_ew_lut_bypass + ) begin + reg2dp_ew_lut_bypass = dp2reg_consumer ? reg2dp_d1_ew_lut_bypass : reg2dp_d0_ew_lut_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_bypass + or reg2dp_d0_ew_mul_bypass + ) begin + reg2dp_ew_mul_bypass = dp2reg_consumer ? reg2dp_d1_ew_mul_bypass : reg2dp_d0_ew_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_prelu + or reg2dp_d0_ew_mul_prelu + ) begin + reg2dp_ew_mul_prelu = dp2reg_consumer ? reg2dp_d1_ew_mul_prelu : reg2dp_d0_ew_mul_prelu; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_bypass + or reg2dp_d0_ew_mul_cvt_bypass + ) begin + reg2dp_ew_mul_cvt_bypass = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_bypass : reg2dp_d0_ew_mul_cvt_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_src + or reg2dp_d0_ew_mul_src + ) begin + reg2dp_ew_mul_src = dp2reg_consumer ? reg2dp_d1_ew_mul_src : reg2dp_d0_ew_mul_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_offset + or reg2dp_d0_ew_mul_cvt_offset + ) begin + reg2dp_ew_mul_cvt_offset = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_offset : reg2dp_d0_ew_mul_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_scale + or reg2dp_d0_ew_mul_cvt_scale + ) begin + reg2dp_ew_mul_cvt_scale = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_scale : reg2dp_d0_ew_mul_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_truncate + or reg2dp_d0_ew_mul_cvt_truncate + ) begin + reg2dp_ew_mul_cvt_truncate = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_truncate : reg2dp_d0_ew_mul_cvt_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_operand + or reg2dp_d0_ew_mul_operand + ) begin + reg2dp_ew_mul_operand = dp2reg_consumer ? reg2dp_d1_ew_mul_operand : reg2dp_d0_ew_mul_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_truncate + or reg2dp_d0_ew_truncate + ) begin + reg2dp_ew_truncate = dp2reg_consumer ? reg2dp_d1_ew_truncate : reg2dp_d0_ew_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_high + or reg2dp_d0_dst_base_addr_high + ) begin + reg2dp_dst_base_addr_high = dp2reg_consumer ? reg2dp_d1_dst_base_addr_high : reg2dp_d0_dst_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_low + or reg2dp_d0_dst_base_addr_low + ) begin + reg2dp_dst_base_addr_low = dp2reg_consumer ? reg2dp_d1_dst_base_addr_low : reg2dp_d0_dst_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_batch_stride + or reg2dp_d0_dst_batch_stride + ) begin + reg2dp_dst_batch_stride = dp2reg_consumer ? reg2dp_d1_dst_batch_stride : reg2dp_d0_dst_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_ram_type + or reg2dp_d0_dst_ram_type + ) begin + reg2dp_dst_ram_type = dp2reg_consumer ? reg2dp_d1_dst_ram_type : reg2dp_d0_dst_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_line_stride + or reg2dp_d0_dst_line_stride + ) begin + reg2dp_dst_line_stride = dp2reg_consumer ? reg2dp_d1_dst_line_stride : reg2dp_d0_dst_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_surface_stride + or reg2dp_d0_dst_surface_stride + ) begin + reg2dp_dst_surface_stride = dp2reg_consumer ? reg2dp_d1_dst_surface_stride : reg2dp_d0_dst_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_batch_number + or reg2dp_d0_batch_number + ) begin + reg2dp_batch_number = dp2reg_consumer ? reg2dp_d1_batch_number : reg2dp_d0_batch_number; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_output_dst + or reg2dp_d0_output_dst + ) begin + reg2dp_output_dst = dp2reg_consumer ? reg2dp_d1_output_dst : reg2dp_d0_output_dst; +end +always @( + dp2reg_consumer + or reg2dp_d1_winograd + or reg2dp_d0_winograd + ) begin + reg2dp_winograd = dp2reg_consumer ? reg2dp_d1_winograd : reg2dp_d0_winograd; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_dma_en + or reg2dp_d0_perf_dma_en + ) begin + reg2dp_perf_dma_en = dp2reg_consumer ? reg2dp_d1_perf_dma_en : reg2dp_d0_perf_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_lut_en + or reg2dp_d0_perf_lut_en + ) begin + reg2dp_perf_lut_en = dp2reg_consumer ? reg2dp_d1_perf_lut_en : reg2dp_d0_perf_lut_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_nan_inf_count_en + or reg2dp_d0_perf_nan_inf_count_en + ) begin + reg2dp_perf_nan_inf_count_en = dp2reg_consumer ? reg2dp_d1_perf_nan_inf_count_en : reg2dp_d0_perf_nan_inf_count_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_sat_en + or reg2dp_d0_perf_sat_en + ) begin + reg2dp_perf_sat_en = dp2reg_consumer ? reg2dp_d1_perf_sat_en : reg2dp_d0_perf_sat_en; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +// +// DO NOT EDIT - generated by simspec! +// +// ifndef ___ARNVDLA_VH_INC_ +//assign reg2dp_lut_data = reg_wr_data[::range(15)]; +assign reg2dp_interrupt_ptr = dp2reg_consumer; +//=================================================== +//////// Single Flop Write Control//////// +//=================================================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_addr_trigger <= 1'b0; + end else begin + lut_int_addr_trigger <= reg2dp_lut_addr_trigger; + end +end +//assign reg2dp_lut_int_addr_trigger = lut_int_addr_trigger; +assign lut_int_data_rd_trigger = reg_rd_en & ( {20'h0,reg_offset[11:0]}==(32'hb00c & 32'h00000fff)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_data_wr_trigger <= 1'b0; + end else begin + lut_int_data_wr_trigger <= reg2dp_lut_data_trigger; + end +end +//assign reg2dp_lut_int_data_wr = lut_int_data_wr_trigger && (lut_int_access_type==NVDLA_SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE); +assign reg2dp_lut_int_data_wr = lut_int_data_wr_trigger; +assign reg2dp_lut_int_addr = lut_int_addr; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_addr <= {10{1'b0}}; + end else begin + if (lut_int_addr_trigger) begin + lut_int_addr <= reg2dp_lut_addr; + end else if (lut_int_data_wr_trigger || lut_int_data_rd_trigger) begin + lut_int_addr <= lut_int_addr + 1'b1; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"WRITE on LUT_ADDR need be NPOST before LUT_DATA READ") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, lut_int_data_rd_trigger & lut_int_addr_trigger); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_access_type <= 1'b0; + end else begin + if ((lut_int_addr_trigger) == 1'b1) begin + lut_int_access_type <= reg2dp_lut_access_type; +// VCS coverage off + end else if ((lut_int_addr_trigger) == 1'b0) begin + end else begin + lut_int_access_type <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lut_int_addr_trigger))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign reg2dp_lut_int_access_type = lut_int_access_type; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_table_id <= 1'b0; + end else begin + if ((lut_int_addr_trigger) == 1'b1) begin + lut_int_table_id <= reg2dp_lut_table_id; +// VCS coverage off + end else if ((lut_int_addr_trigger) == 1'b0) begin + end else begin + lut_int_table_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lut_int_addr_trigger))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign reg2dp_lut_int_table_id = lut_int_table_id; +always @(posedge nvdla_core_clk) begin + if (reg2dp_lut_data_trigger) begin + reg2dp_lut_int_data <= s_reg_wr_data[15:0]; + end +end +assign dp2reg_lut_data = dp2reg_lut_int_data[15:0]; +assign wdma_slcg_op_en = slcg_op_en[0]; +assign bcore_slcg_op_en = slcg_op_en[1]; +assign ncore_slcg_op_en = slcg_op_en[2]; +assign ecore_slcg_op_en = slcg_op_en[3]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_slcg_en <= 1'b0; + end else begin + if (reg2dp_lut_addr_trigger) begin + reg2dp_lut_slcg_en <= 1'b1; + end else if (ecore_slcg_op_en) begin + reg2dp_lut_slcg_en <= 1'b0; + end + end +end +assign reg2dp_wdma_slcg_op_en = wdma_slcg_op_en; +assign reg2dp_bcore_slcg_op_en = bcore_slcg_op_en; +assign reg2dp_ncore_slcg_op_en = ncore_slcg_op_en; +assign reg2dp_ecore_slcg_op_en = ecore_slcg_op_en; +//=================================================== +//////// Dual Flop Write Control//////// +//=================================================== +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for overflow counting register //////// +assign dp2reg_d0_lut_oflow_w = (dp2reg_d0_set) ? dp2reg_lut_oflow[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_oflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_oflow <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_oflow <= dp2reg_d0_lut_oflow_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_uflow_w = (dp2reg_d0_set) ? dp2reg_lut_uflow[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_uflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_uflow <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_uflow <= dp2reg_d0_lut_uflow_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_wdma_stall_w = (dp2reg_d0_set) ? dp2reg_wdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_wdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_wdma_stall <= dp2reg_d0_wdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_wdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_inf_input_num <= dp2reg_d0_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_out_saturation_w = (dp2reg_d0_set) ? dp2reg_out_saturation[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_out_saturation; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_out_saturation <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_out_saturation <= dp2reg_d0_out_saturation_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_out_saturation <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_nan_output_num_w = (dp2reg_d0_set) ? dp2reg_status_nan_output_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_nan_output_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_nan_output_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_nan_output_num <= dp2reg_d0_status_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_le_hit_w = (dp2reg_d0_set) ? dp2reg_lut_le_hit[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_le_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_le_hit <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_le_hit <= dp2reg_d0_lut_le_hit_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_nan_input_num <= dp2reg_d0_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_unequal_w = (dp2reg_d0_set) ? dp2reg_status_unequal[0:0] : + (dp2reg_d0_clr) ? 1'd0 : + dp2reg_d0_status_unequal; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_unequal <= 1'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_unequal <= dp2reg_d0_status_unequal_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_unequal <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_hybrid_w = (dp2reg_d0_set) ? dp2reg_lut_hybrid[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_hybrid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_hybrid <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_hybrid <= dp2reg_d0_lut_hybrid_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_lo_hit_w = (dp2reg_d0_set) ? dp2reg_lut_lo_hit[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_lo_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_lo_hit <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_lo_hit <= dp2reg_d0_lut_lo_hit_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_oflow_w = (dp2reg_d1_set) ? dp2reg_lut_oflow[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_oflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_oflow <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_oflow <= dp2reg_d1_lut_oflow_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_uflow_w = (dp2reg_d1_set) ? dp2reg_lut_uflow[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_uflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_uflow <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_uflow <= dp2reg_d1_lut_uflow_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_wdma_stall_w = (dp2reg_d1_set) ? dp2reg_wdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_wdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_wdma_stall <= dp2reg_d1_wdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_wdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_inf_input_num <= dp2reg_d1_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_out_saturation_w = (dp2reg_d1_set) ? dp2reg_out_saturation[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_out_saturation; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_out_saturation <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_out_saturation <= dp2reg_d1_out_saturation_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_out_saturation <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_nan_output_num_w = (dp2reg_d1_set) ? dp2reg_status_nan_output_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_nan_output_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_nan_output_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_nan_output_num <= dp2reg_d1_status_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_le_hit_w = (dp2reg_d1_set) ? dp2reg_lut_le_hit[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_le_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_le_hit <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_le_hit <= dp2reg_d1_lut_le_hit_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_nan_input_num <= dp2reg_d1_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_unequal_w = (dp2reg_d1_set) ? dp2reg_status_unequal[0:0] : + (dp2reg_d1_clr) ? 1'd0 : + dp2reg_d1_status_unequal; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_unequal <= 1'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_unequal <= dp2reg_d1_status_unequal_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_unequal <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_hybrid_w = (dp2reg_d1_set) ? dp2reg_lut_hybrid[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_hybrid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_hybrid <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_hybrid <= dp2reg_d1_lut_hybrid_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_lo_hit_w = (dp2reg_d1_set) ? dp2reg_lut_lo_hit[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_lo_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_lo_hit <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_lo_hit <= dp2reg_d1_lut_lo_hit_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_SDP_reg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_reg.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_reg.v.vcp new file mode 100644 index 0000000..8b2d02e --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_reg.v.vcp @@ -0,0 +1,3326 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_reg.v +`include "simulate_x_tick.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_reg ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,csb2sdp_req_pd //|< i + ,csb2sdp_req_pvld //|< i + ,dp2reg_done //|< i + ,dp2reg_lut_hybrid //|< i + ,dp2reg_lut_int_data //|< i + ,dp2reg_lut_le_hit //|< i + ,dp2reg_lut_lo_hit //|< i + ,dp2reg_lut_oflow //|< i + ,dp2reg_lut_uflow //|< i + ,dp2reg_out_saturation //|< i + ,dp2reg_status_inf_input_num //|< i + ,dp2reg_status_nan_input_num //|< i + ,dp2reg_status_nan_output_num //|< i + ,dp2reg_status_unequal //|< i + ,dp2reg_wdma_stall //|< i + ,csb2sdp_req_prdy //|> o + ,reg2dp_batch_number //|> o + ,reg2dp_bcore_slcg_op_en //|> o + ,reg2dp_bn_alu_algo //|> o + ,reg2dp_bn_alu_bypass //|> o + ,reg2dp_bn_alu_operand //|> o + ,reg2dp_bn_alu_shift_value //|> o + ,reg2dp_bn_alu_src //|> o + ,reg2dp_bn_bypass //|> o + ,reg2dp_bn_mul_bypass //|> o + ,reg2dp_bn_mul_operand //|> o + ,reg2dp_bn_mul_prelu //|> o + ,reg2dp_bn_mul_shift_value //|> o + ,reg2dp_bn_mul_src //|> o + ,reg2dp_bn_relu_bypass //|> o + ,reg2dp_bs_alu_algo //|> o + ,reg2dp_bs_alu_bypass //|> o + ,reg2dp_bs_alu_operand //|> o + ,reg2dp_bs_alu_shift_value //|> o + ,reg2dp_bs_alu_src //|> o + ,reg2dp_bs_bypass //|> o + ,reg2dp_bs_mul_bypass //|> o + ,reg2dp_bs_mul_operand //|> o + ,reg2dp_bs_mul_prelu //|> o + ,reg2dp_bs_mul_shift_value //|> o + ,reg2dp_bs_mul_src //|> o + ,reg2dp_bs_relu_bypass //|> o + ,reg2dp_channel //|> o + ,reg2dp_cvt_offset //|> o + ,reg2dp_cvt_scale //|> o + ,reg2dp_cvt_shift //|> o + ,reg2dp_dst_base_addr_high //|> o + ,reg2dp_dst_base_addr_low //|> o + ,reg2dp_dst_batch_stride //|> o + ,reg2dp_dst_line_stride //|> o + ,reg2dp_dst_ram_type //|> o + ,reg2dp_dst_surface_stride //|> o + ,reg2dp_ecore_slcg_op_en //|> o + ,reg2dp_ew_alu_algo //|> o + ,reg2dp_ew_alu_bypass //|> o + ,reg2dp_ew_alu_cvt_bypass //|> o + ,reg2dp_ew_alu_cvt_offset //|> o + ,reg2dp_ew_alu_cvt_scale //|> o + ,reg2dp_ew_alu_cvt_truncate //|> o + ,reg2dp_ew_alu_operand //|> o + ,reg2dp_ew_alu_src //|> o + ,reg2dp_ew_bypass //|> o + ,reg2dp_ew_lut_bypass //|> o + ,reg2dp_ew_mul_bypass //|> o + ,reg2dp_ew_mul_cvt_bypass //|> o + ,reg2dp_ew_mul_cvt_offset //|> o + ,reg2dp_ew_mul_cvt_scale //|> o + ,reg2dp_ew_mul_cvt_truncate //|> o + ,reg2dp_ew_mul_operand //|> o + ,reg2dp_ew_mul_prelu //|> o + ,reg2dp_ew_mul_src //|> o + ,reg2dp_ew_truncate //|> o + ,reg2dp_flying_mode //|> o + ,reg2dp_height //|> o + ,reg2dp_interrupt_ptr //|> o + ,reg2dp_lut_hybrid_priority //|> o + ,reg2dp_lut_int_access_type //|> o + ,reg2dp_lut_int_addr //|> o + ,reg2dp_lut_int_data //|> o + ,reg2dp_lut_int_data_wr //|> o + ,reg2dp_lut_int_table_id //|> o + ,reg2dp_lut_le_end //|> o + ,reg2dp_lut_le_function //|> o + ,reg2dp_lut_le_index_offset //|> o + ,reg2dp_lut_le_index_select //|> o + ,reg2dp_lut_le_slope_oflow_scale //|> o + ,reg2dp_lut_le_slope_oflow_shift //|> o + ,reg2dp_lut_le_slope_uflow_scale //|> o + ,reg2dp_lut_le_slope_uflow_shift //|> o + ,reg2dp_lut_le_start //|> o + ,reg2dp_lut_lo_end //|> o + ,reg2dp_lut_lo_index_select //|> o + ,reg2dp_lut_lo_slope_oflow_scale //|> o + ,reg2dp_lut_lo_slope_oflow_shift //|> o + ,reg2dp_lut_lo_slope_uflow_scale //|> o + ,reg2dp_lut_lo_slope_uflow_shift //|> o + ,reg2dp_lut_lo_start //|> o + ,reg2dp_lut_oflow_priority //|> o + ,reg2dp_lut_slcg_en //|> o + ,reg2dp_lut_uflow_priority //|> o + ,reg2dp_nan_to_zero //|> o + ,reg2dp_ncore_slcg_op_en //|> o + ,reg2dp_op_en //|> o + ,reg2dp_out_precision //|> o + ,reg2dp_output_dst //|> o + ,reg2dp_perf_dma_en //|> o + ,reg2dp_perf_lut_en //|> o + ,reg2dp_perf_nan_inf_count_en //|> o + ,reg2dp_perf_sat_en //|> o + ,reg2dp_proc_precision //|> o + ,reg2dp_wdma_slcg_op_en //|> o + ,reg2dp_width //|> o + ,reg2dp_winograd //|> o + ,sdp2csb_resp_pd //|> o + ,sdp2csb_resp_valid //|> o + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [62:0] csb2sdp_req_pd; +input csb2sdp_req_pvld; +input dp2reg_done; +input [31:0] dp2reg_lut_hybrid; +input [15:0] dp2reg_lut_int_data; +input [31:0] dp2reg_lut_le_hit; +input [31:0] dp2reg_lut_lo_hit; +input [31:0] dp2reg_lut_oflow; +input [31:0] dp2reg_lut_uflow; +input [31:0] dp2reg_out_saturation; +input [31:0] dp2reg_status_inf_input_num; +input [31:0] dp2reg_status_nan_input_num; +input [31:0] dp2reg_status_nan_output_num; +input [0:0] dp2reg_status_unequal; +input [31:0] dp2reg_wdma_stall; +output csb2sdp_req_prdy; +output [4:0] reg2dp_batch_number; +output reg2dp_bcore_slcg_op_en; +output [1:0] reg2dp_bn_alu_algo; +output reg2dp_bn_alu_bypass; +output [15:0] reg2dp_bn_alu_operand; +output [5:0] reg2dp_bn_alu_shift_value; +output reg2dp_bn_alu_src; +output reg2dp_bn_bypass; +output reg2dp_bn_mul_bypass; +output [15:0] reg2dp_bn_mul_operand; +output reg2dp_bn_mul_prelu; +output [7:0] reg2dp_bn_mul_shift_value; +output reg2dp_bn_mul_src; +output reg2dp_bn_relu_bypass; +output [1:0] reg2dp_bs_alu_algo; +output reg2dp_bs_alu_bypass; +output [15:0] reg2dp_bs_alu_operand; +output [5:0] reg2dp_bs_alu_shift_value; +output reg2dp_bs_alu_src; +output reg2dp_bs_bypass; +output reg2dp_bs_mul_bypass; +output [15:0] reg2dp_bs_mul_operand; +output reg2dp_bs_mul_prelu; +output [7:0] reg2dp_bs_mul_shift_value; +output reg2dp_bs_mul_src; +output reg2dp_bs_relu_bypass; +output [12:0] reg2dp_channel; +output [31:0] reg2dp_cvt_offset; +output [15:0] reg2dp_cvt_scale; +output [5:0] reg2dp_cvt_shift; +output [31:0] reg2dp_dst_base_addr_high; +output [31:0] reg2dp_dst_base_addr_low; +output [31:0] reg2dp_dst_batch_stride; +output [31:0] reg2dp_dst_line_stride; +output reg2dp_dst_ram_type; +output [31:0] reg2dp_dst_surface_stride; +output reg2dp_ecore_slcg_op_en; +output [1:0] reg2dp_ew_alu_algo; +output reg2dp_ew_alu_bypass; +output reg2dp_ew_alu_cvt_bypass; +output [31:0] reg2dp_ew_alu_cvt_offset; +output [15:0] reg2dp_ew_alu_cvt_scale; +output [5:0] reg2dp_ew_alu_cvt_truncate; +output [31:0] reg2dp_ew_alu_operand; +output reg2dp_ew_alu_src; +output reg2dp_ew_bypass; +output reg2dp_ew_lut_bypass; +output reg2dp_ew_mul_bypass; +output reg2dp_ew_mul_cvt_bypass; +output [31:0] reg2dp_ew_mul_cvt_offset; +output [15:0] reg2dp_ew_mul_cvt_scale; +output [5:0] reg2dp_ew_mul_cvt_truncate; +output [31:0] reg2dp_ew_mul_operand; +output reg2dp_ew_mul_prelu; +output reg2dp_ew_mul_src; +output [9:0] reg2dp_ew_truncate; +output reg2dp_flying_mode; +output [12:0] reg2dp_height; +output reg2dp_interrupt_ptr; +output reg2dp_lut_hybrid_priority; +output reg2dp_lut_int_access_type; +output [9:0] reg2dp_lut_int_addr; +output [15:0] reg2dp_lut_int_data; +output reg2dp_lut_int_data_wr; +output reg2dp_lut_int_table_id; +output [31:0] reg2dp_lut_le_end; +output reg2dp_lut_le_function; +output [7:0] reg2dp_lut_le_index_offset; +output [7:0] reg2dp_lut_le_index_select; +output [15:0] reg2dp_lut_le_slope_oflow_scale; +output [4:0] reg2dp_lut_le_slope_oflow_shift; +output [15:0] reg2dp_lut_le_slope_uflow_scale; +output [4:0] reg2dp_lut_le_slope_uflow_shift; +output [31:0] reg2dp_lut_le_start; +output [31:0] reg2dp_lut_lo_end; +output [7:0] reg2dp_lut_lo_index_select; +output [15:0] reg2dp_lut_lo_slope_oflow_scale; +output [4:0] reg2dp_lut_lo_slope_oflow_shift; +output [15:0] reg2dp_lut_lo_slope_uflow_scale; +output [4:0] reg2dp_lut_lo_slope_uflow_shift; +output [31:0] reg2dp_lut_lo_start; +output reg2dp_lut_oflow_priority; +output reg2dp_lut_slcg_en; +output reg2dp_lut_uflow_priority; +output reg2dp_nan_to_zero; +output reg2dp_ncore_slcg_op_en; +output reg2dp_op_en; +output [1:0] reg2dp_out_precision; +output reg2dp_output_dst; +output reg2dp_perf_dma_en; +output reg2dp_perf_lut_en; +output reg2dp_perf_nan_inf_count_en; +output reg2dp_perf_sat_en; +output [1:0] reg2dp_proc_precision; +output reg2dp_wdma_slcg_op_en; +output [12:0] reg2dp_width; +output reg2dp_winograd; +output [33:0] sdp2csb_resp_pd; +output sdp2csb_resp_valid; +wire bcore_slcg_op_en; +wire csb_rresp_error; +wire [33:0] csb_rresp_pd_w; +wire [31:0] csb_rresp_rdat; +wire csb_wresp_error; +wire [33:0] csb_wresp_pd_w; +wire [31:0] csb_wresp_rdat; +wire [23:0] d0_reg_offset; +wire [31:0] d0_reg_rd_data; +wire [31:0] d0_reg_wr_data; +wire d0_reg_wr_en; +wire [23:0] d1_reg_offset; +wire [31:0] d1_reg_rd_data; +wire [31:0] d1_reg_wr_data; +wire d1_reg_wr_en; +wire dp2reg_consumer_w; +wire [31:0] dp2reg_d0_lut_hybrid_w; +wire [31:0] dp2reg_d0_lut_le_hit_w; +wire [31:0] dp2reg_d0_lut_lo_hit_w; +wire [31:0] dp2reg_d0_lut_oflow_w; +wire [31:0] dp2reg_d0_lut_uflow_w; +wire [31:0] dp2reg_d0_out_saturation_w; +wire [31:0] dp2reg_d0_status_inf_input_num_w; +wire [31:0] dp2reg_d0_status_nan_input_num_w; +wire [31:0] dp2reg_d0_status_nan_output_num_w; +wire dp2reg_d0_status_unequal_w; +wire [31:0] dp2reg_d0_wdma_stall_w; +wire [31:0] dp2reg_d1_lut_hybrid_w; +wire [31:0] dp2reg_d1_lut_le_hit_w; +wire [31:0] dp2reg_d1_lut_lo_hit_w; +wire [31:0] dp2reg_d1_lut_oflow_w; +wire [31:0] dp2reg_d1_lut_uflow_w; +wire [31:0] dp2reg_d1_out_saturation_w; +wire [31:0] dp2reg_d1_status_inf_input_num_w; +wire [31:0] dp2reg_d1_status_nan_input_num_w; +wire [31:0] dp2reg_d1_status_nan_output_num_w; +wire dp2reg_d1_status_unequal_w; +wire [31:0] dp2reg_d1_wdma_stall_w; +wire [15:0] dp2reg_lut_data; +wire ecore_slcg_op_en; +wire lut_int_data_rd_trigger; +wire ncore_slcg_op_en; +wire [4:0] reg2dp_d0_batch_number; +wire [1:0] reg2dp_d0_bn_alu_algo; +wire reg2dp_d0_bn_alu_bypass; +wire [15:0] reg2dp_d0_bn_alu_operand; +wire [5:0] reg2dp_d0_bn_alu_shift_value; +wire reg2dp_d0_bn_alu_src; +wire reg2dp_d0_bn_bypass; +wire reg2dp_d0_bn_mul_bypass; +wire [15:0] reg2dp_d0_bn_mul_operand; +wire reg2dp_d0_bn_mul_prelu; +wire [7:0] reg2dp_d0_bn_mul_shift_value; +wire reg2dp_d0_bn_mul_src; +wire reg2dp_d0_bn_relu_bypass; +wire [1:0] reg2dp_d0_bs_alu_algo; +wire reg2dp_d0_bs_alu_bypass; +wire [15:0] reg2dp_d0_bs_alu_operand; +wire [5:0] reg2dp_d0_bs_alu_shift_value; +wire reg2dp_d0_bs_alu_src; +wire reg2dp_d0_bs_bypass; +wire reg2dp_d0_bs_mul_bypass; +wire [15:0] reg2dp_d0_bs_mul_operand; +wire reg2dp_d0_bs_mul_prelu; +wire [7:0] reg2dp_d0_bs_mul_shift_value; +wire reg2dp_d0_bs_mul_src; +wire reg2dp_d0_bs_relu_bypass; +wire [12:0] reg2dp_d0_channel; +wire [31:0] reg2dp_d0_cvt_offset; +wire [15:0] reg2dp_d0_cvt_scale; +wire [5:0] reg2dp_d0_cvt_shift; +wire [31:0] reg2dp_d0_dst_base_addr_high; +wire [31:0] reg2dp_d0_dst_base_addr_low; +wire [31:0] reg2dp_d0_dst_batch_stride; +wire [31:0] reg2dp_d0_dst_line_stride; +wire reg2dp_d0_dst_ram_type; +wire [31:0] reg2dp_d0_dst_surface_stride; +wire [1:0] reg2dp_d0_ew_alu_algo; +wire reg2dp_d0_ew_alu_bypass; +wire reg2dp_d0_ew_alu_cvt_bypass; +wire [31:0] reg2dp_d0_ew_alu_cvt_offset; +wire [15:0] reg2dp_d0_ew_alu_cvt_scale; +wire [5:0] reg2dp_d0_ew_alu_cvt_truncate; +wire [31:0] reg2dp_d0_ew_alu_operand; +wire reg2dp_d0_ew_alu_src; +wire reg2dp_d0_ew_bypass; +wire reg2dp_d0_ew_lut_bypass; +wire reg2dp_d0_ew_mul_bypass; +wire reg2dp_d0_ew_mul_cvt_bypass; +wire [31:0] reg2dp_d0_ew_mul_cvt_offset; +wire [15:0] reg2dp_d0_ew_mul_cvt_scale; +wire [5:0] reg2dp_d0_ew_mul_cvt_truncate; +wire [31:0] reg2dp_d0_ew_mul_operand; +wire reg2dp_d0_ew_mul_prelu; +wire reg2dp_d0_ew_mul_src; +wire [9:0] reg2dp_d0_ew_truncate; +wire reg2dp_d0_flying_mode; +wire [12:0] reg2dp_d0_height; +wire reg2dp_d0_nan_to_zero; +wire reg2dp_d0_op_en_trigger; +wire [1:0] reg2dp_d0_out_precision; +wire reg2dp_d0_output_dst; +wire reg2dp_d0_perf_dma_en; +wire reg2dp_d0_perf_lut_en; +wire reg2dp_d0_perf_nan_inf_count_en; +wire reg2dp_d0_perf_sat_en; +wire [1:0] reg2dp_d0_proc_precision; +wire [12:0] reg2dp_d0_width; +wire reg2dp_d0_winograd; +wire [4:0] reg2dp_d1_batch_number; +wire [1:0] reg2dp_d1_bn_alu_algo; +wire reg2dp_d1_bn_alu_bypass; +wire [15:0] reg2dp_d1_bn_alu_operand; +wire [5:0] reg2dp_d1_bn_alu_shift_value; +wire reg2dp_d1_bn_alu_src; +wire reg2dp_d1_bn_bypass; +wire reg2dp_d1_bn_mul_bypass; +wire [15:0] reg2dp_d1_bn_mul_operand; +wire reg2dp_d1_bn_mul_prelu; +wire [7:0] reg2dp_d1_bn_mul_shift_value; +wire reg2dp_d1_bn_mul_src; +wire reg2dp_d1_bn_relu_bypass; +wire [1:0] reg2dp_d1_bs_alu_algo; +wire reg2dp_d1_bs_alu_bypass; +wire [15:0] reg2dp_d1_bs_alu_operand; +wire [5:0] reg2dp_d1_bs_alu_shift_value; +wire reg2dp_d1_bs_alu_src; +wire reg2dp_d1_bs_bypass; +wire reg2dp_d1_bs_mul_bypass; +wire [15:0] reg2dp_d1_bs_mul_operand; +wire reg2dp_d1_bs_mul_prelu; +wire [7:0] reg2dp_d1_bs_mul_shift_value; +wire reg2dp_d1_bs_mul_src; +wire reg2dp_d1_bs_relu_bypass; +wire [12:0] reg2dp_d1_channel; +wire [31:0] reg2dp_d1_cvt_offset; +wire [15:0] reg2dp_d1_cvt_scale; +wire [5:0] reg2dp_d1_cvt_shift; +wire [31:0] reg2dp_d1_dst_base_addr_high; +wire [31:0] reg2dp_d1_dst_base_addr_low; +wire [31:0] reg2dp_d1_dst_batch_stride; +wire [31:0] reg2dp_d1_dst_line_stride; +wire reg2dp_d1_dst_ram_type; +wire [31:0] reg2dp_d1_dst_surface_stride; +wire [1:0] reg2dp_d1_ew_alu_algo; +wire reg2dp_d1_ew_alu_bypass; +wire reg2dp_d1_ew_alu_cvt_bypass; +wire [31:0] reg2dp_d1_ew_alu_cvt_offset; +wire [15:0] reg2dp_d1_ew_alu_cvt_scale; +wire [5:0] reg2dp_d1_ew_alu_cvt_truncate; +wire [31:0] reg2dp_d1_ew_alu_operand; +wire reg2dp_d1_ew_alu_src; +wire reg2dp_d1_ew_bypass; +wire reg2dp_d1_ew_lut_bypass; +wire reg2dp_d1_ew_mul_bypass; +wire reg2dp_d1_ew_mul_cvt_bypass; +wire [31:0] reg2dp_d1_ew_mul_cvt_offset; +wire [15:0] reg2dp_d1_ew_mul_cvt_scale; +wire [5:0] reg2dp_d1_ew_mul_cvt_truncate; +wire [31:0] reg2dp_d1_ew_mul_operand; +wire reg2dp_d1_ew_mul_prelu; +wire reg2dp_d1_ew_mul_src; +wire [9:0] reg2dp_d1_ew_truncate; +wire reg2dp_d1_flying_mode; +wire [12:0] reg2dp_d1_height; +wire reg2dp_d1_nan_to_zero; +wire reg2dp_d1_op_en_trigger; +wire [1:0] reg2dp_d1_out_precision; +wire reg2dp_d1_output_dst; +wire reg2dp_d1_perf_dma_en; +wire reg2dp_d1_perf_lut_en; +wire reg2dp_d1_perf_nan_inf_count_en; +wire reg2dp_d1_perf_sat_en; +wire [1:0] reg2dp_d1_proc_precision; +wire [12:0] reg2dp_d1_width; +wire reg2dp_d1_winograd; +wire reg2dp_lut_access_type; +wire [9:0] reg2dp_lut_addr; +wire reg2dp_lut_addr_trigger; +wire reg2dp_lut_data_trigger; +wire reg2dp_lut_table_id; +wire [2:0] reg2dp_op_en_reg_w; +wire reg2dp_producer; +wire [23:0] reg_offset; +wire [31:0] reg_rd_data; +wire reg_rd_en; +wire [31:0] reg_wr_data; +wire reg_wr_en; +wire [21:0] req_addr; +wire [1:0] req_level; +wire req_nposted; +wire req_srcpriv; +wire [31:0] req_wdat; +wire [3:0] req_wrbe; +wire req_write; +wire [23:0] s_reg_offset; +wire [31:0] s_reg_rd_data; +wire [31:0] s_reg_wr_data; +wire s_reg_wr_en; +wire select_d0; +wire select_d1; +wire select_s; +wire [3:0] slcg_op_en; +wire [3:0] slcg_op_en_d0; +wire wdma_slcg_op_en; +reg dp2reg_consumer; +reg dp2reg_d0_clr; +reg [31:0] dp2reg_d0_lut_hybrid; +reg [31:0] dp2reg_d0_lut_le_hit; +reg [31:0] dp2reg_d0_lut_lo_hit; +reg [31:0] dp2reg_d0_lut_oflow; +reg [31:0] dp2reg_d0_lut_uflow; +reg [31:0] dp2reg_d0_out_saturation; +reg dp2reg_d0_reg; +reg dp2reg_d0_set; +reg [31:0] dp2reg_d0_status_inf_input_num; +reg [31:0] dp2reg_d0_status_nan_input_num; +reg [31:0] dp2reg_d0_status_nan_output_num; +reg dp2reg_d0_status_unequal; +reg [31:0] dp2reg_d0_wdma_stall; +reg dp2reg_d1_clr; +reg [31:0] dp2reg_d1_lut_hybrid; +reg [31:0] dp2reg_d1_lut_le_hit; +reg [31:0] dp2reg_d1_lut_lo_hit; +reg [31:0] dp2reg_d1_lut_oflow; +reg [31:0] dp2reg_d1_lut_uflow; +reg [31:0] dp2reg_d1_out_saturation; +reg dp2reg_d1_reg; +reg dp2reg_d1_set; +reg [31:0] dp2reg_d1_status_inf_input_num; +reg [31:0] dp2reg_d1_status_nan_input_num; +reg [31:0] dp2reg_d1_status_nan_output_num; +reg dp2reg_d1_status_unequal; +reg [31:0] dp2reg_d1_wdma_stall; +reg [1:0] dp2reg_status_0; +reg [1:0] dp2reg_status_1; +reg lut_int_access_type; +reg [9:0] lut_int_addr; +reg lut_int_addr_trigger; +reg lut_int_data_wr_trigger; +reg lut_int_table_id; +reg [4:0] reg2dp_batch_number; +reg [1:0] reg2dp_bn_alu_algo; +reg reg2dp_bn_alu_bypass; +reg [15:0] reg2dp_bn_alu_operand; +reg [5:0] reg2dp_bn_alu_shift_value; +reg reg2dp_bn_alu_src; +reg reg2dp_bn_bypass; +reg reg2dp_bn_mul_bypass; +reg [15:0] reg2dp_bn_mul_operand; +reg reg2dp_bn_mul_prelu; +reg [7:0] reg2dp_bn_mul_shift_value; +reg reg2dp_bn_mul_src; +reg reg2dp_bn_relu_bypass; +reg [1:0] reg2dp_bs_alu_algo; +reg reg2dp_bs_alu_bypass; +reg [15:0] reg2dp_bs_alu_operand; +reg [5:0] reg2dp_bs_alu_shift_value; +reg reg2dp_bs_alu_src; +reg reg2dp_bs_bypass; +reg reg2dp_bs_mul_bypass; +reg [15:0] reg2dp_bs_mul_operand; +reg reg2dp_bs_mul_prelu; +reg [7:0] reg2dp_bs_mul_shift_value; +reg reg2dp_bs_mul_src; +reg reg2dp_bs_relu_bypass; +reg [12:0] reg2dp_channel; +reg [31:0] reg2dp_cvt_offset; +reg [15:0] reg2dp_cvt_scale; +reg [5:0] reg2dp_cvt_shift; +reg reg2dp_d0_op_en; +reg reg2dp_d0_op_en_w; +reg reg2dp_d1_op_en; +reg reg2dp_d1_op_en_w; +reg [31:0] reg2dp_dst_base_addr_high; +reg [31:0] reg2dp_dst_base_addr_low; +reg [31:0] reg2dp_dst_batch_stride; +reg [31:0] reg2dp_dst_line_stride; +reg reg2dp_dst_ram_type; +reg [31:0] reg2dp_dst_surface_stride; +reg [1:0] reg2dp_ew_alu_algo; +reg reg2dp_ew_alu_bypass; +reg reg2dp_ew_alu_cvt_bypass; +reg [31:0] reg2dp_ew_alu_cvt_offset; +reg [15:0] reg2dp_ew_alu_cvt_scale; +reg [5:0] reg2dp_ew_alu_cvt_truncate; +reg [31:0] reg2dp_ew_alu_operand; +reg reg2dp_ew_alu_src; +reg reg2dp_ew_bypass; +reg reg2dp_ew_lut_bypass; +reg reg2dp_ew_mul_bypass; +reg reg2dp_ew_mul_cvt_bypass; +reg [31:0] reg2dp_ew_mul_cvt_offset; +reg [15:0] reg2dp_ew_mul_cvt_scale; +reg [5:0] reg2dp_ew_mul_cvt_truncate; +reg [31:0] reg2dp_ew_mul_operand; +reg reg2dp_ew_mul_prelu; +reg reg2dp_ew_mul_src; +reg [9:0] reg2dp_ew_truncate; +reg reg2dp_flying_mode; +reg [12:0] reg2dp_height; +reg [15:0] reg2dp_lut_int_data; +reg reg2dp_lut_slcg_en; +reg reg2dp_nan_to_zero; +reg reg2dp_op_en_ori; +reg [2:0] reg2dp_op_en_reg; +reg [1:0] reg2dp_out_precision; +reg reg2dp_output_dst; +reg reg2dp_perf_dma_en; +reg reg2dp_perf_lut_en; +reg reg2dp_perf_nan_inf_count_en; +reg reg2dp_perf_sat_en; +reg [1:0] reg2dp_proc_precision; +reg [12:0] reg2dp_width; +reg reg2dp_winograd; +reg [62:0] req_pd; +reg req_pvld; +reg [33:0] sdp2csb_resp_pd; +reg sdp2csb_resp_valid; +reg [3:0] slcg_op_en_d1; +reg [3:0] slcg_op_en_d2; +reg [3:0] slcg_op_en_d3; +//Instance single register group +NV_NVDLA_SDP_REG_single u_single_reg ( + .reg_rd_data (s_reg_rd_data[31:0]) //|> w + ,.reg_offset (s_reg_offset[11:0]) //|< w + ,.reg_wr_data (s_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (s_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.lut_access_type (reg2dp_lut_access_type) //|> w + ,.lut_addr (reg2dp_lut_addr[9:0]) //|> w + ,.lut_addr_trigger (reg2dp_lut_addr_trigger) //|> w + ,.lut_table_id (reg2dp_lut_table_id) //|> w + ,.lut_data_trigger (reg2dp_lut_data_trigger) //|> w + ,.lut_hybrid_priority (reg2dp_lut_hybrid_priority) //|> o + ,.lut_le_function (reg2dp_lut_le_function) //|> o + ,.lut_oflow_priority (reg2dp_lut_oflow_priority) //|> o + ,.lut_uflow_priority (reg2dp_lut_uflow_priority) //|> o + ,.lut_le_index_offset (reg2dp_lut_le_index_offset[7:0]) //|> o + ,.lut_le_index_select (reg2dp_lut_le_index_select[7:0]) //|> o + ,.lut_lo_index_select (reg2dp_lut_lo_index_select[7:0]) //|> o + ,.lut_le_end (reg2dp_lut_le_end[31:0]) //|> o + ,.lut_le_slope_oflow_scale (reg2dp_lut_le_slope_oflow_scale[15:0]) //|> o + ,.lut_le_slope_uflow_scale (reg2dp_lut_le_slope_uflow_scale[15:0]) //|> o + ,.lut_le_slope_oflow_shift (reg2dp_lut_le_slope_oflow_shift[4:0]) //|> o + ,.lut_le_slope_uflow_shift (reg2dp_lut_le_slope_uflow_shift[4:0]) //|> o + ,.lut_le_start (reg2dp_lut_le_start[31:0]) //|> o + ,.lut_lo_end (reg2dp_lut_lo_end[31:0]) //|> o + ,.lut_lo_slope_oflow_scale (reg2dp_lut_lo_slope_oflow_scale[15:0]) //|> o + ,.lut_lo_slope_uflow_scale (reg2dp_lut_lo_slope_uflow_scale[15:0]) //|> o + ,.lut_lo_slope_oflow_shift (reg2dp_lut_lo_slope_oflow_shift[4:0]) //|> o + ,.lut_lo_slope_uflow_shift (reg2dp_lut_lo_slope_uflow_shift[4:0]) //|> o + ,.lut_lo_start (reg2dp_lut_lo_start[31:0]) //|> o + ,.producer (reg2dp_producer) //|> w + ,.lut_data (dp2reg_lut_data[15:0]) //|< w + ,.consumer (dp2reg_consumer) //|< r + ,.status_0 (dp2reg_status_0[1:0]) //|< r + ,.status_1 (dp2reg_status_1[1:0]) //|< r + ); +//Instance two duplicated register groups +NV_NVDLA_SDP_REG_dual u_dual_reg_d0 ( + .reg_rd_data (d0_reg_rd_data[31:0]) //|> w + ,.reg_offset (d0_reg_offset[11:0]) //|< w + ,.reg_wr_data (d0_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d0_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_offset (reg2dp_d0_cvt_offset[31:0]) //|> w + ,.cvt_scale (reg2dp_d0_cvt_scale[15:0]) //|> w + ,.cvt_shift (reg2dp_d0_cvt_shift[5:0]) //|> w + ,.channel (reg2dp_d0_channel[12:0]) //|> w + ,.height (reg2dp_d0_height[12:0]) //|> w + ,.width (reg2dp_d0_width[12:0]) //|> w + ,.out_precision (reg2dp_d0_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d0_proc_precision[1:0]) //|> w + ,.bn_alu_shift_value (reg2dp_d0_bn_alu_shift_value[5:0]) //|> w + ,.bn_alu_src (reg2dp_d0_bn_alu_src) //|> w + ,.bn_alu_operand (reg2dp_d0_bn_alu_operand[15:0]) //|> w + ,.bn_alu_algo (reg2dp_d0_bn_alu_algo[1:0]) //|> w + ,.bn_alu_bypass (reg2dp_d0_bn_alu_bypass) //|> w + ,.bn_bypass (reg2dp_d0_bn_bypass) //|> w + ,.bn_mul_bypass (reg2dp_d0_bn_mul_bypass) //|> w + ,.bn_mul_prelu (reg2dp_d0_bn_mul_prelu) //|> w + ,.bn_relu_bypass (reg2dp_d0_bn_relu_bypass) //|> w + ,.bn_mul_shift_value (reg2dp_d0_bn_mul_shift_value[7:0]) //|> w + ,.bn_mul_src (reg2dp_d0_bn_mul_src) //|> w + ,.bn_mul_operand (reg2dp_d0_bn_mul_operand[15:0]) //|> w + ,.bs_alu_shift_value (reg2dp_d0_bs_alu_shift_value[5:0]) //|> w + ,.bs_alu_src (reg2dp_d0_bs_alu_src) //|> w + ,.bs_alu_operand (reg2dp_d0_bs_alu_operand[15:0]) //|> w + ,.bs_alu_algo (reg2dp_d0_bs_alu_algo[1:0]) //|> w + ,.bs_alu_bypass (reg2dp_d0_bs_alu_bypass) //|> w + ,.bs_bypass (reg2dp_d0_bs_bypass) //|> w + ,.bs_mul_bypass (reg2dp_d0_bs_mul_bypass) //|> w + ,.bs_mul_prelu (reg2dp_d0_bs_mul_prelu) //|> w + ,.bs_relu_bypass (reg2dp_d0_bs_relu_bypass) //|> w + ,.bs_mul_shift_value (reg2dp_d0_bs_mul_shift_value[7:0]) //|> w + ,.bs_mul_src (reg2dp_d0_bs_mul_src) //|> w + ,.bs_mul_operand (reg2dp_d0_bs_mul_operand[15:0]) //|> w + ,.ew_alu_cvt_bypass (reg2dp_d0_ew_alu_cvt_bypass) //|> w + ,.ew_alu_src (reg2dp_d0_ew_alu_src) //|> w + ,.ew_alu_cvt_offset (reg2dp_d0_ew_alu_cvt_offset[31:0]) //|> w + ,.ew_alu_cvt_scale (reg2dp_d0_ew_alu_cvt_scale[15:0]) //|> w + ,.ew_alu_cvt_truncate (reg2dp_d0_ew_alu_cvt_truncate[5:0]) //|> w + ,.ew_alu_operand (reg2dp_d0_ew_alu_operand[31:0]) //|> w + ,.ew_alu_algo (reg2dp_d0_ew_alu_algo[1:0]) //|> w + ,.ew_alu_bypass (reg2dp_d0_ew_alu_bypass) //|> w + ,.ew_bypass (reg2dp_d0_ew_bypass) //|> w + ,.ew_lut_bypass (reg2dp_d0_ew_lut_bypass) //|> w + ,.ew_mul_bypass (reg2dp_d0_ew_mul_bypass) //|> w + ,.ew_mul_prelu (reg2dp_d0_ew_mul_prelu) //|> w + ,.ew_mul_cvt_bypass (reg2dp_d0_ew_mul_cvt_bypass) //|> w + ,.ew_mul_src (reg2dp_d0_ew_mul_src) //|> w + ,.ew_mul_cvt_offset (reg2dp_d0_ew_mul_cvt_offset[31:0]) //|> w + ,.ew_mul_cvt_scale (reg2dp_d0_ew_mul_cvt_scale[15:0]) //|> w + ,.ew_mul_cvt_truncate (reg2dp_d0_ew_mul_cvt_truncate[5:0]) //|> w + ,.ew_mul_operand (reg2dp_d0_ew_mul_operand[31:0]) //|> w + ,.ew_truncate (reg2dp_d0_ew_truncate[9:0]) //|> w + ,.dst_base_addr_high (reg2dp_d0_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d0_dst_base_addr_low[31:0]) //|> w + ,.dst_batch_stride (reg2dp_d0_dst_batch_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d0_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d0_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d0_dst_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d0_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d0_flying_mode) //|> w + ,.nan_to_zero (reg2dp_d0_nan_to_zero) //|> w + ,.output_dst (reg2dp_d0_output_dst) //|> w + ,.winograd (reg2dp_d0_winograd) //|> w + ,.op_en_trigger (reg2dp_d0_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d0_perf_dma_en) //|> w + ,.perf_lut_en (reg2dp_d0_perf_lut_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d0_perf_nan_inf_count_en) //|> w + ,.perf_sat_en (reg2dp_d0_perf_sat_en) //|> w + ,.op_en (reg2dp_d0_op_en) //|< r + ,.lut_hybrid (dp2reg_d0_lut_hybrid[31:0]) //|< r + ,.lut_le_hit (dp2reg_d0_lut_le_hit[31:0]) //|< r + ,.lut_lo_hit (dp2reg_d0_lut_lo_hit[31:0]) //|< r + ,.lut_oflow (dp2reg_d0_lut_oflow[31:0]) //|< r + ,.lut_uflow (dp2reg_d0_lut_uflow[31:0]) //|< r + ,.out_saturation (dp2reg_d0_out_saturation[31:0]) //|< r + ,.wdma_stall (dp2reg_d0_wdma_stall[31:0]) //|< r + ,.status_unequal (dp2reg_d0_status_unequal) //|< r + ,.status_inf_input_num (dp2reg_d0_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d0_status_nan_input_num[31:0]) //|< r + ,.status_nan_output_num (dp2reg_d0_status_nan_output_num[31:0]) //|< r + ); +NV_NVDLA_SDP_REG_dual u_dual_reg_d1 ( + .reg_rd_data (d1_reg_rd_data[31:0]) //|> w + ,.reg_offset (d1_reg_offset[11:0]) //|< w + ,.reg_wr_data (d1_reg_wr_data[31:0]) //|< w + ,.reg_wr_en (d1_reg_wr_en) //|< w + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cvt_offset (reg2dp_d1_cvt_offset[31:0]) //|> w + ,.cvt_scale (reg2dp_d1_cvt_scale[15:0]) //|> w + ,.cvt_shift (reg2dp_d1_cvt_shift[5:0]) //|> w + ,.channel (reg2dp_d1_channel[12:0]) //|> w + ,.height (reg2dp_d1_height[12:0]) //|> w + ,.width (reg2dp_d1_width[12:0]) //|> w + ,.out_precision (reg2dp_d1_out_precision[1:0]) //|> w + ,.proc_precision (reg2dp_d1_proc_precision[1:0]) //|> w + ,.bn_alu_shift_value (reg2dp_d1_bn_alu_shift_value[5:0]) //|> w + ,.bn_alu_src (reg2dp_d1_bn_alu_src) //|> w + ,.bn_alu_operand (reg2dp_d1_bn_alu_operand[15:0]) //|> w + ,.bn_alu_algo (reg2dp_d1_bn_alu_algo[1:0]) //|> w + ,.bn_alu_bypass (reg2dp_d1_bn_alu_bypass) //|> w + ,.bn_bypass (reg2dp_d1_bn_bypass) //|> w + ,.bn_mul_bypass (reg2dp_d1_bn_mul_bypass) //|> w + ,.bn_mul_prelu (reg2dp_d1_bn_mul_prelu) //|> w + ,.bn_relu_bypass (reg2dp_d1_bn_relu_bypass) //|> w + ,.bn_mul_shift_value (reg2dp_d1_bn_mul_shift_value[7:0]) //|> w + ,.bn_mul_src (reg2dp_d1_bn_mul_src) //|> w + ,.bn_mul_operand (reg2dp_d1_bn_mul_operand[15:0]) //|> w + ,.bs_alu_shift_value (reg2dp_d1_bs_alu_shift_value[5:0]) //|> w + ,.bs_alu_src (reg2dp_d1_bs_alu_src) //|> w + ,.bs_alu_operand (reg2dp_d1_bs_alu_operand[15:0]) //|> w + ,.bs_alu_algo (reg2dp_d1_bs_alu_algo[1:0]) //|> w + ,.bs_alu_bypass (reg2dp_d1_bs_alu_bypass) //|> w + ,.bs_bypass (reg2dp_d1_bs_bypass) //|> w + ,.bs_mul_bypass (reg2dp_d1_bs_mul_bypass) //|> w + ,.bs_mul_prelu (reg2dp_d1_bs_mul_prelu) //|> w + ,.bs_relu_bypass (reg2dp_d1_bs_relu_bypass) //|> w + ,.bs_mul_shift_value (reg2dp_d1_bs_mul_shift_value[7:0]) //|> w + ,.bs_mul_src (reg2dp_d1_bs_mul_src) //|> w + ,.bs_mul_operand (reg2dp_d1_bs_mul_operand[15:0]) //|> w + ,.ew_alu_cvt_bypass (reg2dp_d1_ew_alu_cvt_bypass) //|> w + ,.ew_alu_src (reg2dp_d1_ew_alu_src) //|> w + ,.ew_alu_cvt_offset (reg2dp_d1_ew_alu_cvt_offset[31:0]) //|> w + ,.ew_alu_cvt_scale (reg2dp_d1_ew_alu_cvt_scale[15:0]) //|> w + ,.ew_alu_cvt_truncate (reg2dp_d1_ew_alu_cvt_truncate[5:0]) //|> w + ,.ew_alu_operand (reg2dp_d1_ew_alu_operand[31:0]) //|> w + ,.ew_alu_algo (reg2dp_d1_ew_alu_algo[1:0]) //|> w + ,.ew_alu_bypass (reg2dp_d1_ew_alu_bypass) //|> w + ,.ew_bypass (reg2dp_d1_ew_bypass) //|> w + ,.ew_lut_bypass (reg2dp_d1_ew_lut_bypass) //|> w + ,.ew_mul_bypass (reg2dp_d1_ew_mul_bypass) //|> w + ,.ew_mul_prelu (reg2dp_d1_ew_mul_prelu) //|> w + ,.ew_mul_cvt_bypass (reg2dp_d1_ew_mul_cvt_bypass) //|> w + ,.ew_mul_src (reg2dp_d1_ew_mul_src) //|> w + ,.ew_mul_cvt_offset (reg2dp_d1_ew_mul_cvt_offset[31:0]) //|> w + ,.ew_mul_cvt_scale (reg2dp_d1_ew_mul_cvt_scale[15:0]) //|> w + ,.ew_mul_cvt_truncate (reg2dp_d1_ew_mul_cvt_truncate[5:0]) //|> w + ,.ew_mul_operand (reg2dp_d1_ew_mul_operand[31:0]) //|> w + ,.ew_truncate (reg2dp_d1_ew_truncate[9:0]) //|> w + ,.dst_base_addr_high (reg2dp_d1_dst_base_addr_high[31:0]) //|> w + ,.dst_base_addr_low (reg2dp_d1_dst_base_addr_low[31:0]) //|> w + ,.dst_batch_stride (reg2dp_d1_dst_batch_stride[31:0]) //|> w + ,.dst_ram_type (reg2dp_d1_dst_ram_type) //|> w + ,.dst_line_stride (reg2dp_d1_dst_line_stride[31:0]) //|> w + ,.dst_surface_stride (reg2dp_d1_dst_surface_stride[31:0]) //|> w + ,.batch_number (reg2dp_d1_batch_number[4:0]) //|> w + ,.flying_mode (reg2dp_d1_flying_mode) //|> w + ,.nan_to_zero (reg2dp_d1_nan_to_zero) //|> w + ,.output_dst (reg2dp_d1_output_dst) //|> w + ,.winograd (reg2dp_d1_winograd) //|> w + ,.op_en_trigger (reg2dp_d1_op_en_trigger) //|> w + ,.perf_dma_en (reg2dp_d1_perf_dma_en) //|> w + ,.perf_lut_en (reg2dp_d1_perf_lut_en) //|> w + ,.perf_nan_inf_count_en (reg2dp_d1_perf_nan_inf_count_en) //|> w + ,.perf_sat_en (reg2dp_d1_perf_sat_en) //|> w + ,.op_en (reg2dp_d1_op_en) //|< r + ,.lut_hybrid (dp2reg_d1_lut_hybrid[31:0]) //|< r + ,.lut_le_hit (dp2reg_d1_lut_le_hit[31:0]) //|< r + ,.lut_lo_hit (dp2reg_d1_lut_lo_hit[31:0]) //|< r + ,.lut_oflow (dp2reg_d1_lut_oflow[31:0]) //|< r + ,.lut_uflow (dp2reg_d1_lut_uflow[31:0]) //|< r + ,.out_saturation (dp2reg_d1_out_saturation[31:0]) //|< r + ,.wdma_stall (dp2reg_d1_wdma_stall[31:0]) //|< r + ,.status_unequal (dp2reg_d1_status_unequal) //|< r + ,.status_inf_input_num (dp2reg_d1_status_inf_input_num[31:0]) //|< r + ,.status_nan_input_num (dp2reg_d1_status_nan_input_num[31:0]) //|< r + ,.status_nan_output_num (dp2reg_d1_status_nan_output_num[31:0]) //|< r + ); +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CONSUMER PIONTER IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +assign dp2reg_consumer_w = ~dp2reg_consumer; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_consumer <= 1'b0; + end else begin + if ((dp2reg_done) == 1'b1) begin + dp2reg_consumer <= dp2reg_consumer_w; +// VCS coverage off + end else if ((dp2reg_done) == 1'b0) begin + end else begin + dp2reg_consumer <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_done))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE TWO STATUS FIELDS IN GENERAL SINGLE REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or dp2reg_consumer + ) begin + dp2reg_status_0 = (reg2dp_d0_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h1 ) ? 2'h2 : + 2'h1 ; +end +always @( + reg2dp_d1_op_en + or dp2reg_consumer + ) begin + dp2reg_status_1 = (reg2dp_d1_op_en == 1'h0 ) ? 2'h0 : + (dp2reg_consumer == 1'h0 ) ? 2'h2 : + 2'h1 ; +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OP_EN LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d0_op_en_w = (~reg2dp_d0_op_en & reg2dp_d0_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h0 ) ? 1'b0 : + reg2dp_d0_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d0_op_en <= 1'b0; + end else begin + reg2dp_d0_op_en <= reg2dp_d0_op_en_w; + end +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_trigger + or reg_wr_data + or dp2reg_done + or dp2reg_consumer + ) begin + reg2dp_d1_op_en_w = (~reg2dp_d1_op_en & reg2dp_d1_op_en_trigger) ? reg_wr_data[0 ] : + (dp2reg_done && dp2reg_consumer == 1'h1 ) ? 1'b0 : + reg2dp_d1_op_en; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_d1_op_en <= 1'b0; + end else begin + reg2dp_d1_op_en <= reg2dp_d1_op_en_w; + end +end +always @( + dp2reg_consumer + or reg2dp_d1_op_en + or reg2dp_d0_op_en + ) begin + reg2dp_op_en_ori = dp2reg_consumer ? reg2dp_d1_op_en : reg2dp_d0_op_en; +end +assign reg2dp_op_en_reg_w = dp2reg_done ? 3'b0 : + {reg2dp_op_en_reg[1:0], reg2dp_op_en_ori}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_op_en_reg <= {3{1'b0}}; + end else begin + reg2dp_op_en_reg <= reg2dp_op_en_reg_w; + end +end +assign reg2dp_op_en = reg2dp_op_en_reg[3-1]; +assign slcg_op_en_d0 = {4{reg2dp_op_en_ori}}; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d1 <= {4{1'b0}}; + end else begin + slcg_op_en_d1 <= slcg_op_en_d0; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d2 <= {4{1'b0}}; + end else begin + slcg_op_en_d2 <= slcg_op_en_d1; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + slcg_op_en_d3 <= {4{1'b0}}; + end else begin + slcg_op_en_d3 <= slcg_op_en_d2; + end +end +assign slcg_op_en = slcg_op_en_d3; +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE ACCESS LOGIC TO EACH REGISTER GROUP // +// // +//////////////////////////////////////////////////////////////////////// +//EACH subunit has 4KB address space +assign select_s = (reg_offset[11:0] < (32'hb038 & 32'hfff)) ? 1'b1: 1'b0; +assign select_d0 = (reg_offset[11:0] >= (32'hb038 & 32'hfff)) & (reg2dp_producer == 1'h0 ); +assign select_d1 = (reg_offset[11:0] >= (32'hb038 & 32'hfff)) & (reg2dp_producer == 1'h1 ); +assign s_reg_wr_en = reg_wr_en & select_s; +assign d0_reg_wr_en = reg_wr_en & select_d0 & ~reg2dp_d0_op_en; +assign d1_reg_wr_en = reg_wr_en & select_d1 & ~reg2dp_d1_op_en; +assign s_reg_offset = reg_offset; +assign d0_reg_offset = reg_offset; +assign d1_reg_offset = reg_offset; +assign s_reg_wr_data = reg_wr_data; +assign d0_reg_wr_data = reg_wr_data; +assign d1_reg_wr_data = reg_wr_data; +assign reg_rd_data = ({32{select_s}} & s_reg_rd_data) | + ({32{select_d0}} & d0_reg_rd_data) | + ({32{select_d1}} & d1_reg_rd_data); +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 0 registers when OP_EN is set!") zzz_assert_never_2x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d0 & reg2dp_d0_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_never #(0,0,"Error! Write group 1 registers when OP_EN is set!") zzz_assert_never_3x (nvdla_core_clk, `ASSERT_RESET, (reg_wr_en & select_d1 & reg2dp_d1_op_en)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE CSB TO REGISTER CONNECTION LOGIC // +// // +//////////////////////////////////////////////////////////////////////// +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pvld <= 1'b0; + end else begin + req_pvld <= csb2sdp_req_pvld; + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + req_pd <= {63{1'b0}}; + end else begin + if ((csb2sdp_req_pvld) == 1'b1) begin + req_pd <= csb2sdp_req_pd; +// VCS coverage off + end else if ((csb2sdp_req_pvld) == 1'b0) begin + end else begin + req_pd <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_4x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(csb2sdp_req_pvld))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +// PKT_UNPACK_WIRE( csb2xx_16m_be_lvl , req_ , req_pd ) +assign req_addr[21:0] = req_pd[21:0]; +assign req_wdat[31:0] = req_pd[53:22]; +assign req_write = req_pd[54]; +assign req_nposted = req_pd[55]; +assign req_srcpriv = req_pd[56]; +assign req_wrbe[3:0] = req_pd[60:57]; +assign req_level[1:0] = req_pd[62:61]; +assign csb2sdp_req_prdy = 1'b1; +//Address in CSB master is word aligned while address in regfile is byte aligned. +assign reg_offset = {req_addr, 2'b0}; +assign reg_wr_data = req_wdat; +assign reg_wr_en = req_pvld & req_write; +assign reg_rd_en = req_pvld & ~req_write; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_rd_erpt , csb_rresp_ , csb_rresp_pd_w ) +assign csb_rresp_pd_w[31:0] = csb_rresp_rdat[31:0]; +assign csb_rresp_pd_w[32] = csb_rresp_error ; +assign csb_rresp_pd_w[33:33] = 1'd0 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_rd_erpt_ID */ ; +// PKT_PACK_WIRE_ID( nvdla_xx2csb_resp , dla_xx2csb_wr_erpt , csb_wresp_ , csb_wresp_pd_w ) +assign csb_wresp_pd_w[31:0] = csb_wresp_rdat[31:0]; +assign csb_wresp_pd_w[32] = csb_wresp_error ; +assign csb_wresp_pd_w[33:33] = 1'd1 /* PKT_nvdla_xx2csb_resp_dla_xx2csb_wr_erpt_ID */ ; +assign csb_rresp_rdat = reg_rd_data; +assign csb_rresp_error = 1'b0; +assign csb_wresp_rdat = {32{1'b0}}; +assign csb_wresp_error = 1'b0; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2csb_resp_pd <= {34{1'b0}}; + end else begin + if(reg_rd_en) + begin + sdp2csb_resp_pd <= csb_rresp_pd_w; + end + else if(reg_wr_en & req_nposted) + begin + sdp2csb_resp_pd <= csb_wresp_pd_w; + end + end +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + sdp2csb_resp_valid <= 1'b0; + end else begin + sdp2csb_resp_valid <= (reg_wr_en & req_nposted) | reg_rd_en; + end +end +//////////////////////////////////////////////////////////////////////// +// // +// GENERATE OUTPUT REGISTER FILED FROM DUPLICATED REGISTER GROUPS // +// // +//////////////////////////////////////////////////////////////////////// +always @( + dp2reg_consumer + or reg2dp_d1_cvt_offset + or reg2dp_d0_cvt_offset + ) begin + reg2dp_cvt_offset = dp2reg_consumer ? reg2dp_d1_cvt_offset : reg2dp_d0_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_scale + or reg2dp_d0_cvt_scale + ) begin + reg2dp_cvt_scale = dp2reg_consumer ? reg2dp_d1_cvt_scale : reg2dp_d0_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_cvt_shift + or reg2dp_d0_cvt_shift + ) begin + reg2dp_cvt_shift = dp2reg_consumer ? reg2dp_d1_cvt_shift : reg2dp_d0_cvt_shift; +end +always @( + dp2reg_consumer + or reg2dp_d1_channel + or reg2dp_d0_channel + ) begin + reg2dp_channel = dp2reg_consumer ? reg2dp_d1_channel : reg2dp_d0_channel; +end +always @( + dp2reg_consumer + or reg2dp_d1_height + or reg2dp_d0_height + ) begin + reg2dp_height = dp2reg_consumer ? reg2dp_d1_height : reg2dp_d0_height; +end +always @( + dp2reg_consumer + or reg2dp_d1_width + or reg2dp_d0_width + ) begin + reg2dp_width = dp2reg_consumer ? reg2dp_d1_width : reg2dp_d0_width; +end +always @( + dp2reg_consumer + or reg2dp_d1_out_precision + or reg2dp_d0_out_precision + ) begin + reg2dp_out_precision = dp2reg_consumer ? reg2dp_d1_out_precision : reg2dp_d0_out_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_proc_precision + or reg2dp_d0_proc_precision + ) begin + reg2dp_proc_precision = dp2reg_consumer ? reg2dp_d1_proc_precision : reg2dp_d0_proc_precision; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_shift_value + or reg2dp_d0_bn_alu_shift_value + ) begin + reg2dp_bn_alu_shift_value = dp2reg_consumer ? reg2dp_d1_bn_alu_shift_value : reg2dp_d0_bn_alu_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_src + or reg2dp_d0_bn_alu_src + ) begin + reg2dp_bn_alu_src = dp2reg_consumer ? reg2dp_d1_bn_alu_src : reg2dp_d0_bn_alu_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_operand + or reg2dp_d0_bn_alu_operand + ) begin + reg2dp_bn_alu_operand = dp2reg_consumer ? reg2dp_d1_bn_alu_operand : reg2dp_d0_bn_alu_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_algo + or reg2dp_d0_bn_alu_algo + ) begin + reg2dp_bn_alu_algo = dp2reg_consumer ? reg2dp_d1_bn_alu_algo : reg2dp_d0_bn_alu_algo; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_alu_bypass + or reg2dp_d0_bn_alu_bypass + ) begin + reg2dp_bn_alu_bypass = dp2reg_consumer ? reg2dp_d1_bn_alu_bypass : reg2dp_d0_bn_alu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_bypass + or reg2dp_d0_bn_bypass + ) begin + reg2dp_bn_bypass = dp2reg_consumer ? reg2dp_d1_bn_bypass : reg2dp_d0_bn_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_bypass + or reg2dp_d0_bn_mul_bypass + ) begin + reg2dp_bn_mul_bypass = dp2reg_consumer ? reg2dp_d1_bn_mul_bypass : reg2dp_d0_bn_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_prelu + or reg2dp_d0_bn_mul_prelu + ) begin + reg2dp_bn_mul_prelu = dp2reg_consumer ? reg2dp_d1_bn_mul_prelu : reg2dp_d0_bn_mul_prelu; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_relu_bypass + or reg2dp_d0_bn_relu_bypass + ) begin + reg2dp_bn_relu_bypass = dp2reg_consumer ? reg2dp_d1_bn_relu_bypass : reg2dp_d0_bn_relu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_shift_value + or reg2dp_d0_bn_mul_shift_value + ) begin + reg2dp_bn_mul_shift_value = dp2reg_consumer ? reg2dp_d1_bn_mul_shift_value : reg2dp_d0_bn_mul_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_src + or reg2dp_d0_bn_mul_src + ) begin + reg2dp_bn_mul_src = dp2reg_consumer ? reg2dp_d1_bn_mul_src : reg2dp_d0_bn_mul_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bn_mul_operand + or reg2dp_d0_bn_mul_operand + ) begin + reg2dp_bn_mul_operand = dp2reg_consumer ? reg2dp_d1_bn_mul_operand : reg2dp_d0_bn_mul_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_shift_value + or reg2dp_d0_bs_alu_shift_value + ) begin + reg2dp_bs_alu_shift_value = dp2reg_consumer ? reg2dp_d1_bs_alu_shift_value : reg2dp_d0_bs_alu_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_src + or reg2dp_d0_bs_alu_src + ) begin + reg2dp_bs_alu_src = dp2reg_consumer ? reg2dp_d1_bs_alu_src : reg2dp_d0_bs_alu_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_operand + or reg2dp_d0_bs_alu_operand + ) begin + reg2dp_bs_alu_operand = dp2reg_consumer ? reg2dp_d1_bs_alu_operand : reg2dp_d0_bs_alu_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_algo + or reg2dp_d0_bs_alu_algo + ) begin + reg2dp_bs_alu_algo = dp2reg_consumer ? reg2dp_d1_bs_alu_algo : reg2dp_d0_bs_alu_algo; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_alu_bypass + or reg2dp_d0_bs_alu_bypass + ) begin + reg2dp_bs_alu_bypass = dp2reg_consumer ? reg2dp_d1_bs_alu_bypass : reg2dp_d0_bs_alu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_bypass + or reg2dp_d0_bs_bypass + ) begin + reg2dp_bs_bypass = dp2reg_consumer ? reg2dp_d1_bs_bypass : reg2dp_d0_bs_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_bypass + or reg2dp_d0_bs_mul_bypass + ) begin + reg2dp_bs_mul_bypass = dp2reg_consumer ? reg2dp_d1_bs_mul_bypass : reg2dp_d0_bs_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_prelu + or reg2dp_d0_bs_mul_prelu + ) begin + reg2dp_bs_mul_prelu = dp2reg_consumer ? reg2dp_d1_bs_mul_prelu : reg2dp_d0_bs_mul_prelu; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_relu_bypass + or reg2dp_d0_bs_relu_bypass + ) begin + reg2dp_bs_relu_bypass = dp2reg_consumer ? reg2dp_d1_bs_relu_bypass : reg2dp_d0_bs_relu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_shift_value + or reg2dp_d0_bs_mul_shift_value + ) begin + reg2dp_bs_mul_shift_value = dp2reg_consumer ? reg2dp_d1_bs_mul_shift_value : reg2dp_d0_bs_mul_shift_value; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_src + or reg2dp_d0_bs_mul_src + ) begin + reg2dp_bs_mul_src = dp2reg_consumer ? reg2dp_d1_bs_mul_src : reg2dp_d0_bs_mul_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_bs_mul_operand + or reg2dp_d0_bs_mul_operand + ) begin + reg2dp_bs_mul_operand = dp2reg_consumer ? reg2dp_d1_bs_mul_operand : reg2dp_d0_bs_mul_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_bypass + or reg2dp_d0_ew_alu_cvt_bypass + ) begin + reg2dp_ew_alu_cvt_bypass = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_bypass : reg2dp_d0_ew_alu_cvt_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_src + or reg2dp_d0_ew_alu_src + ) begin + reg2dp_ew_alu_src = dp2reg_consumer ? reg2dp_d1_ew_alu_src : reg2dp_d0_ew_alu_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_offset + or reg2dp_d0_ew_alu_cvt_offset + ) begin + reg2dp_ew_alu_cvt_offset = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_offset : reg2dp_d0_ew_alu_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_scale + or reg2dp_d0_ew_alu_cvt_scale + ) begin + reg2dp_ew_alu_cvt_scale = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_scale : reg2dp_d0_ew_alu_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_cvt_truncate + or reg2dp_d0_ew_alu_cvt_truncate + ) begin + reg2dp_ew_alu_cvt_truncate = dp2reg_consumer ? reg2dp_d1_ew_alu_cvt_truncate : reg2dp_d0_ew_alu_cvt_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_operand + or reg2dp_d0_ew_alu_operand + ) begin + reg2dp_ew_alu_operand = dp2reg_consumer ? reg2dp_d1_ew_alu_operand : reg2dp_d0_ew_alu_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_algo + or reg2dp_d0_ew_alu_algo + ) begin + reg2dp_ew_alu_algo = dp2reg_consumer ? reg2dp_d1_ew_alu_algo : reg2dp_d0_ew_alu_algo; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_alu_bypass + or reg2dp_d0_ew_alu_bypass + ) begin + reg2dp_ew_alu_bypass = dp2reg_consumer ? reg2dp_d1_ew_alu_bypass : reg2dp_d0_ew_alu_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_bypass + or reg2dp_d0_ew_bypass + ) begin + reg2dp_ew_bypass = dp2reg_consumer ? reg2dp_d1_ew_bypass : reg2dp_d0_ew_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_lut_bypass + or reg2dp_d0_ew_lut_bypass + ) begin + reg2dp_ew_lut_bypass = dp2reg_consumer ? reg2dp_d1_ew_lut_bypass : reg2dp_d0_ew_lut_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_bypass + or reg2dp_d0_ew_mul_bypass + ) begin + reg2dp_ew_mul_bypass = dp2reg_consumer ? reg2dp_d1_ew_mul_bypass : reg2dp_d0_ew_mul_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_prelu + or reg2dp_d0_ew_mul_prelu + ) begin + reg2dp_ew_mul_prelu = dp2reg_consumer ? reg2dp_d1_ew_mul_prelu : reg2dp_d0_ew_mul_prelu; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_bypass + or reg2dp_d0_ew_mul_cvt_bypass + ) begin + reg2dp_ew_mul_cvt_bypass = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_bypass : reg2dp_d0_ew_mul_cvt_bypass; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_src + or reg2dp_d0_ew_mul_src + ) begin + reg2dp_ew_mul_src = dp2reg_consumer ? reg2dp_d1_ew_mul_src : reg2dp_d0_ew_mul_src; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_offset + or reg2dp_d0_ew_mul_cvt_offset + ) begin + reg2dp_ew_mul_cvt_offset = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_offset : reg2dp_d0_ew_mul_cvt_offset; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_scale + or reg2dp_d0_ew_mul_cvt_scale + ) begin + reg2dp_ew_mul_cvt_scale = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_scale : reg2dp_d0_ew_mul_cvt_scale; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_cvt_truncate + or reg2dp_d0_ew_mul_cvt_truncate + ) begin + reg2dp_ew_mul_cvt_truncate = dp2reg_consumer ? reg2dp_d1_ew_mul_cvt_truncate : reg2dp_d0_ew_mul_cvt_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_mul_operand + or reg2dp_d0_ew_mul_operand + ) begin + reg2dp_ew_mul_operand = dp2reg_consumer ? reg2dp_d1_ew_mul_operand : reg2dp_d0_ew_mul_operand; +end +always @( + dp2reg_consumer + or reg2dp_d1_ew_truncate + or reg2dp_d0_ew_truncate + ) begin + reg2dp_ew_truncate = dp2reg_consumer ? reg2dp_d1_ew_truncate : reg2dp_d0_ew_truncate; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_high + or reg2dp_d0_dst_base_addr_high + ) begin + reg2dp_dst_base_addr_high = dp2reg_consumer ? reg2dp_d1_dst_base_addr_high : reg2dp_d0_dst_base_addr_high; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_base_addr_low + or reg2dp_d0_dst_base_addr_low + ) begin + reg2dp_dst_base_addr_low = dp2reg_consumer ? reg2dp_d1_dst_base_addr_low : reg2dp_d0_dst_base_addr_low; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_batch_stride + or reg2dp_d0_dst_batch_stride + ) begin + reg2dp_dst_batch_stride = dp2reg_consumer ? reg2dp_d1_dst_batch_stride : reg2dp_d0_dst_batch_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_ram_type + or reg2dp_d0_dst_ram_type + ) begin + reg2dp_dst_ram_type = dp2reg_consumer ? reg2dp_d1_dst_ram_type : reg2dp_d0_dst_ram_type; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_line_stride + or reg2dp_d0_dst_line_stride + ) begin + reg2dp_dst_line_stride = dp2reg_consumer ? reg2dp_d1_dst_line_stride : reg2dp_d0_dst_line_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_dst_surface_stride + or reg2dp_d0_dst_surface_stride + ) begin + reg2dp_dst_surface_stride = dp2reg_consumer ? reg2dp_d1_dst_surface_stride : reg2dp_d0_dst_surface_stride; +end +always @( + dp2reg_consumer + or reg2dp_d1_batch_number + or reg2dp_d0_batch_number + ) begin + reg2dp_batch_number = dp2reg_consumer ? reg2dp_d1_batch_number : reg2dp_d0_batch_number; +end +always @( + dp2reg_consumer + or reg2dp_d1_flying_mode + or reg2dp_d0_flying_mode + ) begin + reg2dp_flying_mode = dp2reg_consumer ? reg2dp_d1_flying_mode : reg2dp_d0_flying_mode; +end +always @( + dp2reg_consumer + or reg2dp_d1_nan_to_zero + or reg2dp_d0_nan_to_zero + ) begin + reg2dp_nan_to_zero = dp2reg_consumer ? reg2dp_d1_nan_to_zero : reg2dp_d0_nan_to_zero; +end +always @( + dp2reg_consumer + or reg2dp_d1_output_dst + or reg2dp_d0_output_dst + ) begin + reg2dp_output_dst = dp2reg_consumer ? reg2dp_d1_output_dst : reg2dp_d0_output_dst; +end +always @( + dp2reg_consumer + or reg2dp_d1_winograd + or reg2dp_d0_winograd + ) begin + reg2dp_winograd = dp2reg_consumer ? reg2dp_d1_winograd : reg2dp_d0_winograd; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_dma_en + or reg2dp_d0_perf_dma_en + ) begin + reg2dp_perf_dma_en = dp2reg_consumer ? reg2dp_d1_perf_dma_en : reg2dp_d0_perf_dma_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_lut_en + or reg2dp_d0_perf_lut_en + ) begin + reg2dp_perf_lut_en = dp2reg_consumer ? reg2dp_d1_perf_lut_en : reg2dp_d0_perf_lut_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_nan_inf_count_en + or reg2dp_d0_perf_nan_inf_count_en + ) begin + reg2dp_perf_nan_inf_count_en = dp2reg_consumer ? reg2dp_d1_perf_nan_inf_count_en : reg2dp_d0_perf_nan_inf_count_en; +end +always @( + dp2reg_consumer + or reg2dp_d1_perf_sat_en + or reg2dp_d0_perf_sat_en + ) begin + reg2dp_perf_sat_en = dp2reg_consumer ? reg2dp_d1_perf_sat_en : reg2dp_d0_perf_sat_en; +end +//////////////////////////////////////////////////////////////////////// +// // +// PASTE ADDIFITON LOGIC HERE FROM EXTRA FILE // +// // +//////////////////////////////////////////////////////////////////////// +// +// DO NOT EDIT - generated by simspec! +// +// ifndef ___ARNVDLA_VH_INC_ +//assign reg2dp_lut_data = reg_wr_data[::range(15)]; +assign reg2dp_interrupt_ptr = dp2reg_consumer; +//=================================================== +//////// Single Flop Write Control//////// +//=================================================== +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_addr_trigger <= 1'b0; + end else begin + lut_int_addr_trigger <= reg2dp_lut_addr_trigger; + end +end +//assign reg2dp_lut_int_addr_trigger = lut_int_addr_trigger; +assign lut_int_data_rd_trigger = reg_rd_en & ( {20'h0,reg_offset[11:0]}==(32'hb00c & 32'h00000fff)); +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_data_wr_trigger <= 1'b0; + end else begin + lut_int_data_wr_trigger <= reg2dp_lut_data_trigger; + end +end +//assign reg2dp_lut_int_data_wr = lut_int_data_wr_trigger && (lut_int_access_type==NVDLA_SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE); +assign reg2dp_lut_int_data_wr = lut_int_data_wr_trigger; +assign reg2dp_lut_int_addr = lut_int_addr; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_addr <= {10{1'b0}}; + end else begin + if (lut_int_addr_trigger) begin + lut_int_addr <= reg2dp_lut_addr; + end else if (lut_int_data_wr_trigger || lut_int_data_rd_trigger) begin + lut_int_addr <= lut_int_addr + 1'b1; + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_never #(0,0,"WRITE on LUT_ADDR need be NPOST before LUT_DATA READ") zzz_assert_never_5x (nvdla_core_clk, `ASSERT_RESET, lut_int_data_rd_trigger & lut_int_addr_trigger); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_access_type <= 1'b0; + end else begin + if ((lut_int_addr_trigger) == 1'b1) begin + lut_int_access_type <= reg2dp_lut_access_type; +// VCS coverage off + end else if ((lut_int_addr_trigger) == 1'b0) begin + end else begin + lut_int_access_type <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_6x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lut_int_addr_trigger))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign reg2dp_lut_int_access_type = lut_int_access_type; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + lut_int_table_id <= 1'b0; + end else begin + if ((lut_int_addr_trigger) == 1'b1) begin + lut_int_table_id <= reg2dp_lut_table_id; +// VCS coverage off + end else if ((lut_int_addr_trigger) == 1'b0) begin + end else begin + lut_int_table_id <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(lut_int_addr_trigger))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign reg2dp_lut_int_table_id = lut_int_table_id; +always @(posedge nvdla_core_clk) begin + if (reg2dp_lut_data_trigger) begin + reg2dp_lut_int_data <= s_reg_wr_data[15:0]; + end +end +assign dp2reg_lut_data = dp2reg_lut_int_data[15:0]; +assign wdma_slcg_op_en = slcg_op_en[0]; +assign bcore_slcg_op_en = slcg_op_en[1]; +assign ncore_slcg_op_en = slcg_op_en[2]; +assign ecore_slcg_op_en = slcg_op_en[3]; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + reg2dp_lut_slcg_en <= 1'b0; + end else begin + if (reg2dp_lut_addr_trigger) begin + reg2dp_lut_slcg_en <= 1'b1; + end else if (ecore_slcg_op_en) begin + reg2dp_lut_slcg_en <= 1'b0; + end + end +end +assign reg2dp_wdma_slcg_op_en = wdma_slcg_op_en; +assign reg2dp_bcore_slcg_op_en = bcore_slcg_op_en; +assign reg2dp_ncore_slcg_op_en = ncore_slcg_op_en; +assign reg2dp_ecore_slcg_op_en = ecore_slcg_op_en; +//=================================================== +//////// Dual Flop Write Control//////// +//=================================================== +always @( + reg2dp_d0_op_en + or reg2dp_d0_op_en_w + ) begin + dp2reg_d0_set = reg2dp_d0_op_en & ~reg2dp_d0_op_en_w; + dp2reg_d0_clr = ~reg2dp_d0_op_en & reg2dp_d0_op_en_w; + dp2reg_d0_reg = reg2dp_d0_op_en ^ reg2dp_d0_op_en_w; +end +always @( + reg2dp_d1_op_en + or reg2dp_d1_op_en_w + ) begin + dp2reg_d1_set = reg2dp_d1_op_en & ~reg2dp_d1_op_en_w; + dp2reg_d1_clr = ~reg2dp_d1_op_en & reg2dp_d1_op_en_w; + dp2reg_d1_reg = reg2dp_d1_op_en ^ reg2dp_d1_op_en_w; +end +//////// for overflow counting register //////// +assign dp2reg_d0_lut_oflow_w = (dp2reg_d0_set) ? dp2reg_lut_oflow[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_oflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_oflow <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_oflow <= dp2reg_d0_lut_oflow_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_8x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_uflow_w = (dp2reg_d0_set) ? dp2reg_lut_uflow[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_uflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_uflow <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_uflow <= dp2reg_d0_lut_uflow_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_wdma_stall_w = (dp2reg_d0_set) ? dp2reg_wdma_stall[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_wdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_wdma_stall <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_wdma_stall <= dp2reg_d0_wdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_wdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_10x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_inf_input_num_w = (dp2reg_d0_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_inf_input_num <= dp2reg_d0_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_out_saturation_w = (dp2reg_d0_set) ? dp2reg_out_saturation[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_out_saturation; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_out_saturation <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_out_saturation <= dp2reg_d0_out_saturation_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_out_saturation <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_12x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_nan_output_num_w = (dp2reg_d0_set) ? dp2reg_status_nan_output_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_nan_output_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_nan_output_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_nan_output_num <= dp2reg_d0_status_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_le_hit_w = (dp2reg_d0_set) ? dp2reg_lut_le_hit[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_le_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_le_hit <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_le_hit <= dp2reg_d0_lut_le_hit_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_14x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_nan_input_num_w = (dp2reg_d0_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_nan_input_num <= dp2reg_d0_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_15x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_status_unequal_w = (dp2reg_d0_set) ? dp2reg_status_unequal[0:0] : + (dp2reg_d0_clr) ? 1'd0 : + dp2reg_d0_status_unequal; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_status_unequal <= 1'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_status_unequal <= dp2reg_d0_status_unequal_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_status_unequal <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_16x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_hybrid_w = (dp2reg_d0_set) ? dp2reg_lut_hybrid[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_hybrid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_hybrid <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_hybrid <= dp2reg_d0_lut_hybrid_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_17x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d0_lut_lo_hit_w = (dp2reg_d0_set) ? dp2reg_lut_lo_hit[31:0] : + (dp2reg_d0_clr) ? 32'd0 : + dp2reg_d0_lut_lo_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d0_lut_lo_hit <= 32'd0; + end else begin + if ((dp2reg_d0_reg) == 1'b1) begin + dp2reg_d0_lut_lo_hit <= dp2reg_d0_lut_lo_hit_w; +// VCS coverage off + end else if ((dp2reg_d0_reg) == 1'b0) begin + end else begin + dp2reg_d0_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_18x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d0_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_oflow_w = (dp2reg_d1_set) ? dp2reg_lut_oflow[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_oflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_oflow <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_oflow <= dp2reg_d1_lut_oflow_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_oflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_19x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_uflow_w = (dp2reg_d1_set) ? dp2reg_lut_uflow[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_uflow; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_uflow <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_uflow <= dp2reg_d1_lut_uflow_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_uflow <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_20x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_wdma_stall_w = (dp2reg_d1_set) ? dp2reg_wdma_stall[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_wdma_stall; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_wdma_stall <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_wdma_stall <= dp2reg_d1_wdma_stall_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_wdma_stall <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_21x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_inf_input_num_w = (dp2reg_d1_set) ? dp2reg_status_inf_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_inf_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_inf_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_inf_input_num <= dp2reg_d1_status_inf_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_inf_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_22x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_out_saturation_w = (dp2reg_d1_set) ? dp2reg_out_saturation[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_out_saturation; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_out_saturation <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_out_saturation <= dp2reg_d1_out_saturation_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_out_saturation <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_23x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_nan_output_num_w = (dp2reg_d1_set) ? dp2reg_status_nan_output_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_nan_output_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_nan_output_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_nan_output_num <= dp2reg_d1_status_nan_output_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_nan_output_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_24x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_le_hit_w = (dp2reg_d1_set) ? dp2reg_lut_le_hit[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_le_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_le_hit <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_le_hit <= dp2reg_d1_lut_le_hit_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_le_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_25x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_nan_input_num_w = (dp2reg_d1_set) ? dp2reg_status_nan_input_num[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_status_nan_input_num; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_nan_input_num <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_nan_input_num <= dp2reg_d1_status_nan_input_num_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_nan_input_num <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_26x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_status_unequal_w = (dp2reg_d1_set) ? dp2reg_status_unequal[0:0] : + (dp2reg_d1_clr) ? 1'd0 : + dp2reg_d1_status_unequal; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_status_unequal <= 1'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_status_unequal <= dp2reg_d1_status_unequal_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_status_unequal <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_27x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_hybrid_w = (dp2reg_d1_set) ? dp2reg_lut_hybrid[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_hybrid; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_hybrid <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_hybrid <= dp2reg_d1_lut_hybrid_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_hybrid <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_28x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +assign dp2reg_d1_lut_lo_hit_w = (dp2reg_d1_set) ? dp2reg_lut_lo_hit[31:0] : + (dp2reg_d1_clr) ? 32'd0 : + dp2reg_d1_lut_lo_hit; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + dp2reg_d1_lut_lo_hit <= 32'd0; + end else begin + if ((dp2reg_d1_reg) == 1'b1) begin + dp2reg_d1_lut_lo_hit <= dp2reg_d1_lut_lo_hit_w; +// VCS coverage off + end else if ((dp2reg_d1_reg) == 1'b0) begin + end else begin + dp2reg_d1_lut_lo_hit <= 'bx; // spyglass disable STARC-2.10.1.6 W443 NoWidthInBasedNum-ML -- (Constant containing x or z used, Based number `bx contains an X, Width specification missing for based number) +// VCS coverage on + end + end +end +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_29x (nvdla_core_clk, `ASSERT_RESET, 1'd1, (^(dp2reg_d1_reg))); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +endmodule // NV_NVDLA_SDP_reg diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v new file mode 100644 index 0000000..77ace82 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v @@ -0,0 +1,234 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_wdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_wdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_batch_stride //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_ram_type //|< i + ,reg2dp_dst_surface_stride //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ,reg2dp_height //|< i + ,reg2dp_interrupt_ptr //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_wdma_slcg_op_en //|< i + ,reg2dp_width //|< i + ,reg2dp_winograd //|< i + ,dp2reg_done //|> o + ,dp2reg_status_nan_output_num //|> o + ,dp2reg_status_unequal //|> o + ,dp2reg_wdma_stall //|> o + ,sdp_dp2wdma_pd //|< i + ,sdp_dp2wdma_valid //|< i + ,sdp_dp2wdma_ready //|> o + ,sdp2mcif_wr_req_pd //|> o + ,sdp2mcif_wr_req_valid //|> o + ,sdp2mcif_wr_req_ready //|< i + ,mcif2sdp_wr_rsp_complete //|< i + ,sdp2glb_done_intr_pd //|> o + ); +// +// NV_NVDLA_SDP_wdma_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output [1:0] sdp2glb_done_intr_pd; +output sdp2mcif_wr_req_valid; +input sdp2mcif_wr_req_ready; +output [66 -1:0] sdp2mcif_wr_req_pd; +input mcif2sdp_wr_rsp_complete; +input sdp_dp2wdma_valid; +output sdp_dp2wdma_ready; +input [8*8 -1:0] sdp_dp2wdma_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input [31:0] pwrbus_ram_pd; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_channel; +input [31:0] reg2dp_dst_base_addr_high; +input [31-3:0] reg2dp_dst_base_addr_low; +input [31-3:0] reg2dp_dst_batch_stride; +input [31-3:0] reg2dp_dst_line_stride; +input reg2dp_dst_ram_type; +input [31-3:0] reg2dp_dst_surface_stride; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input [12:0] reg2dp_height; +input reg2dp_interrupt_ptr; +input reg2dp_op_en; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input reg2dp_perf_dma_en; +input [1:0] reg2dp_proc_precision; +input reg2dp_wdma_slcg_op_en; +input [12:0] reg2dp_width; +input reg2dp_winograd; +input tmc2slcg_disable_clock_gating; +output dp2reg_done; +output [31:0] dp2reg_status_nan_output_num; +output dp2reg_status_unequal; +output [31:0] dp2reg_wdma_stall; +reg processing; +wire [32 -3 +13 +1:0] cmd2dat_dma_pd; +wire cmd2dat_dma_prdy; +wire cmd2dat_dma_pvld; +wire [14:0] cmd2dat_spt_pd; +wire cmd2dat_spt_prdy; +wire cmd2dat_spt_pvld; +wire [66 -1:0] dma_wr_req_pd; +wire dma_wr_req_rdy; +wire dma_wr_req_type; +wire dma_wr_req_vld; +wire dma_wr_rsp_complete; +wire intr_req_ptr; +wire intr_req_pvld; +wire nvdla_gated_clk; +wire op_load; +//============== +// Start Processing +//============== +assign op_load = reg2dp_op_en & !processing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + processing <= 1'b0; + end else begin + if (op_load) begin + processing <= 1'b1; + end else if (dp2reg_done) begin + processing <= 1'b0; + end + end +end +NV_NVDLA_SDP_WDMA_gate u_gate ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.reg2dp_wdma_slcg_op_en (reg2dp_wdma_slcg_op_en) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_WDMA_cmd u_cmd ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) //|> w + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) //|< w + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) //|> w + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) //|> w + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) //|< w + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) //|< i + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31-3:0]) //|< i + ,.reg2dp_dst_batch_stride (reg2dp_dst_batch_stride[31-3:0]) //|< i + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31-3:0]) //|< i + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31-3:0]) //|< i + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) //|< i + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) //|< i + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_output_dst (reg2dp_output_dst) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ); +NV_NVDLA_SDP_WDMA_dat u_dat ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) //|< w + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) //|> w + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) //|< w + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) //|< w + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) //|> w + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) //|< w + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) //|< i + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) //|> o + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) //|< i + ,.dma_wr_req_rdy (dma_wr_req_rdy) //|< w + ,.dma_wr_req_pd (dma_wr_req_pd[66 -1:0]) //|> w + ,.dma_wr_req_vld (dma_wr_req_vld) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) //|< i + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) //|< i + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_output_dst (reg2dp_output_dst) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.dp2reg_done (dp2reg_done) //|> o + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) //|> o + ,.dp2reg_status_unequal (dp2reg_status_unequal) //|> o + ,.intr_req_ptr (intr_req_ptr) //|> w + ,.intr_req_pvld (intr_req_pvld) //|> w + ); +NV_NVDLA_DMAIF_wr u_dmaif_wr( + .nvdla_core_clk (nvdla_core_clk) //fixme + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.mcif_wr_req_pd (sdp2mcif_wr_req_pd) + ,.mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.mcif_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.dmaif_wr_req_pd (dma_wr_req_pd) + ,.dmaif_wr_req_pvld (dma_wr_req_vld) + ,.dmaif_wr_req_prdy (dma_wr_req_rdy) + ,.dmaif_wr_rsp_complete (dma_wr_rsp_complete ) +); +NV_NVDLA_SDP_WDMA_intr u_intr ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.op_load (op_load) + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) + ,.dp2reg_wdma_stall (dp2reg_wdma_stall[31:0]) + ,.dma_wr_req_vld (dma_wr_req_vld) + ,.dma_wr_req_rdy (dma_wr_req_rdy) + ,.dma_wr_rsp_complete (dma_wr_rsp_complete ) + ,.intr_req_ptr (intr_req_ptr) + ,.intr_req_pvld (intr_req_pvld) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ); +endmodule // NV_NVDLA_SDP_wdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v.vcp new file mode 100644 index 0000000..77ace82 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_SDP_wdma.v.vcp @@ -0,0 +1,234 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_wdma.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_SDP_wdma ( + nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,reg2dp_batch_number //|< i + ,reg2dp_channel //|< i + ,reg2dp_dst_base_addr_high //|< i + ,reg2dp_dst_base_addr_low //|< i + ,reg2dp_dst_batch_stride //|< i + ,reg2dp_dst_line_stride //|< i + ,reg2dp_dst_ram_type //|< i + ,reg2dp_dst_surface_stride //|< i + ,reg2dp_ew_alu_algo //|< i + ,reg2dp_ew_alu_bypass //|< i + ,reg2dp_ew_bypass //|< i + ,reg2dp_height //|< i + ,reg2dp_interrupt_ptr //|< i + ,reg2dp_op_en //|< i + ,reg2dp_out_precision //|< i + ,reg2dp_output_dst //|< i + ,reg2dp_perf_dma_en //|< i + ,reg2dp_proc_precision //|< i + ,reg2dp_wdma_slcg_op_en //|< i + ,reg2dp_width //|< i + ,reg2dp_winograd //|< i + ,dp2reg_done //|> o + ,dp2reg_status_nan_output_num //|> o + ,dp2reg_status_unequal //|> o + ,dp2reg_wdma_stall //|> o + ,sdp_dp2wdma_pd //|< i + ,sdp_dp2wdma_valid //|< i + ,sdp_dp2wdma_ready //|> o + ,sdp2mcif_wr_req_pd //|> o + ,sdp2mcif_wr_req_valid //|> o + ,sdp2mcif_wr_req_ready //|< i + ,mcif2sdp_wr_rsp_complete //|< i + ,sdp2glb_done_intr_pd //|> o + ); +// +// NV_NVDLA_SDP_wdma_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +output [1:0] sdp2glb_done_intr_pd; +output sdp2mcif_wr_req_valid; +input sdp2mcif_wr_req_ready; +output [66 -1:0] sdp2mcif_wr_req_pd; +input mcif2sdp_wr_rsp_complete; +input sdp_dp2wdma_valid; +output sdp_dp2wdma_ready; +input [8*8 -1:0] sdp_dp2wdma_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input [31:0] pwrbus_ram_pd; +input [4:0] reg2dp_batch_number; +input [12:0] reg2dp_channel; +input [31:0] reg2dp_dst_base_addr_high; +input [31-3:0] reg2dp_dst_base_addr_low; +input [31-3:0] reg2dp_dst_batch_stride; +input [31-3:0] reg2dp_dst_line_stride; +input reg2dp_dst_ram_type; +input [31-3:0] reg2dp_dst_surface_stride; +input [1:0] reg2dp_ew_alu_algo; +input reg2dp_ew_alu_bypass; +input reg2dp_ew_bypass; +input [12:0] reg2dp_height; +input reg2dp_interrupt_ptr; +input reg2dp_op_en; +input [1:0] reg2dp_out_precision; +input reg2dp_output_dst; +input reg2dp_perf_dma_en; +input [1:0] reg2dp_proc_precision; +input reg2dp_wdma_slcg_op_en; +input [12:0] reg2dp_width; +input reg2dp_winograd; +input tmc2slcg_disable_clock_gating; +output dp2reg_done; +output [31:0] dp2reg_status_nan_output_num; +output dp2reg_status_unequal; +output [31:0] dp2reg_wdma_stall; +reg processing; +wire [32 -3 +13 +1:0] cmd2dat_dma_pd; +wire cmd2dat_dma_prdy; +wire cmd2dat_dma_pvld; +wire [14:0] cmd2dat_spt_pd; +wire cmd2dat_spt_prdy; +wire cmd2dat_spt_pvld; +wire [66 -1:0] dma_wr_req_pd; +wire dma_wr_req_rdy; +wire dma_wr_req_type; +wire dma_wr_req_vld; +wire dma_wr_rsp_complete; +wire intr_req_ptr; +wire intr_req_pvld; +wire nvdla_gated_clk; +wire op_load; +//============== +// Start Processing +//============== +assign op_load = reg2dp_op_en & !processing; +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + processing <= 1'b0; + end else begin + if (op_load) begin + processing <= 1'b1; + end else if (dp2reg_done) begin + processing <= 1'b0; + end + end +end +NV_NVDLA_SDP_WDMA_gate u_gate ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< i + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< i + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.reg2dp_wdma_slcg_op_en (reg2dp_wdma_slcg_op_en) //|< i + ,.nvdla_gated_clk (nvdla_gated_clk) //|> w + ); +NV_NVDLA_SDP_WDMA_cmd u_cmd ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) //|> w + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) //|< w + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) //|> w + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) //|> w + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) //|< w + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_channel (reg2dp_channel[12:0]) //|< i + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) //|< i + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31-3:0]) //|< i + ,.reg2dp_dst_batch_stride (reg2dp_dst_batch_stride[31-3:0]) //|< i + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31-3:0]) //|< i + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31-3:0]) //|< i + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) //|< i + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) //|< i + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_output_dst (reg2dp_output_dst) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ); +NV_NVDLA_SDP_WDMA_dat u_dat ( + .nvdla_core_clk (nvdla_gated_clk) //|< w + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.op_load (op_load) //|< w + ,.cmd2dat_dma_pvld (cmd2dat_dma_pvld) //|< w + ,.cmd2dat_dma_prdy (cmd2dat_dma_prdy) //|> w + ,.cmd2dat_dma_pd (cmd2dat_dma_pd[32 -3 +13 +1:0]) //|< w + ,.cmd2dat_spt_pvld (cmd2dat_spt_pvld) //|< w + ,.cmd2dat_spt_prdy (cmd2dat_spt_prdy) //|> w + ,.cmd2dat_spt_pd (cmd2dat_spt_pd[14:0]) //|< w + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) //|< i + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) //|> o + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) //|< i + ,.dma_wr_req_rdy (dma_wr_req_rdy) //|< w + ,.dma_wr_req_pd (dma_wr_req_pd[66 -1:0]) //|> w + ,.dma_wr_req_vld (dma_wr_req_vld) //|> w + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) //|< i + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) //|< i + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) //|< i + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) //|< i + ,.reg2dp_height (reg2dp_height[12:0]) //|< i + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) //|< i + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) //|< i + ,.reg2dp_output_dst (reg2dp_output_dst) //|< i + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) //|< i + ,.reg2dp_width (reg2dp_width[12:0]) //|< i + ,.reg2dp_winograd (reg2dp_winograd) //|< i + ,.dp2reg_done (dp2reg_done) //|> o + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) //|> o + ,.dp2reg_status_unequal (dp2reg_status_unequal) //|> o + ,.intr_req_ptr (intr_req_ptr) //|> w + ,.intr_req_pvld (intr_req_pvld) //|> w + ); +NV_NVDLA_DMAIF_wr u_dmaif_wr( + .nvdla_core_clk (nvdla_core_clk) //fixme + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.mcif_wr_req_pd (sdp2mcif_wr_req_pd) + ,.mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.mcif_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.dmaif_wr_req_pd (dma_wr_req_pd) + ,.dmaif_wr_req_pvld (dma_wr_req_vld) + ,.dmaif_wr_req_prdy (dma_wr_req_rdy) + ,.dmaif_wr_rsp_complete (dma_wr_rsp_complete ) +); +NV_NVDLA_SDP_WDMA_intr u_intr ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.op_load (op_load) + ,.reg2dp_ew_alu_algo (reg2dp_ew_alu_algo[1:0]) + ,.reg2dp_ew_alu_bypass (reg2dp_ew_alu_bypass) + ,.reg2dp_ew_bypass (reg2dp_ew_bypass) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) + ,.dp2reg_wdma_stall (dp2reg_wdma_stall[31:0]) + ,.dma_wr_req_vld (dma_wr_req_vld) + ,.dma_wr_req_rdy (dma_wr_req_rdy) + ,.dma_wr_rsp_complete (dma_wr_rsp_complete ) + ,.intr_req_ptr (intr_req_ptr) + ,.intr_req_pvld (intr_req_pvld) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ); +endmodule // NV_NVDLA_SDP_wdma diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.swl b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.swl new file mode 100644 index 0000000..cbf720c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.swl @@ -0,0 +1,2 @@ +waive -regexp -file NV_NVDLA_SDP_rdma.v -msg "Instance u_reg.*" -rule W210 +waive -regexp -file NV_NVDLA_sdp.v -msg "Instance u_reg.*" -rule W210 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.swl.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.swl.vcp new file mode 100644 index 0000000..cbf720c --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.swl.vcp @@ -0,0 +1,2 @@ +waive -regexp -file NV_NVDLA_SDP_rdma.v -msg "Instance u_reg.*" -rule W210 +waive -regexp -file NV_NVDLA_sdp.v -msg "Instance u_reg.*" -rule W210 diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.v b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.v new file mode 100644 index 0000000..5f2dabb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.v @@ -0,0 +1,440 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sdp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_sdp ( + cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,cacc2sdp_ready //|> o + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,csb2sdp_req_pd //|< i + ,csb2sdp_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp2mcif_wr_req_pd //|> o + ,sdp2mcif_wr_req_valid //|> o + ,sdp2mcif_wr_req_ready //|< i + ,mcif2sdp_wr_rsp_complete //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,sdp2glb_done_intr_pd //|> o + ,csb2sdp_rdma_req_prdy //|> o + ,csb2sdp_req_prdy //|> o + ,sdp2csb_resp_pd //|> o + ,sdp2csb_resp_valid //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ,sdp2pdp_pd //|> o + ,sdp2pdp_valid //|> o + ,sdp2pdp_ready //|< i + ); +// +// NV_NVDLA_sdp_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +input cacc2sdp_valid; +output cacc2sdp_ready; +input [32*1 +1:0] cacc2sdp_pd; +output sdp2pdp_valid; +input sdp2pdp_ready; +output [8*1 -1:0] sdp2pdp_pd; +output [1:0] sdp2glb_done_intr_pd; +input csb2sdp_rdma_req_pvld; +output csb2sdp_rdma_req_prdy; +input [62:0] csb2sdp_rdma_req_pd; +output sdp_rdma2csb_resp_valid; +output [33:0] sdp_rdma2csb_resp_pd; +input csb2sdp_req_pvld; +output csb2sdp_req_prdy; +input [62:0] csb2sdp_req_pd; +output sdp2csb_resp_valid; +output [33:0] sdp2csb_resp_pd; +output sdp_b2mcif_rd_cdt_lat_fifo_pop; +output sdp_b2mcif_rd_req_valid; +input sdp_b2mcif_rd_req_ready; +output [47 -1:0] sdp_b2mcif_rd_req_pd; +input mcif2sdp_b_rd_rsp_valid; +output mcif2sdp_b_rd_rsp_ready; +input [65 -1:0] mcif2sdp_b_rd_rsp_pd; +output sdp_n2mcif_rd_cdt_lat_fifo_pop; +output sdp_n2mcif_rd_req_valid; +input sdp_n2mcif_rd_req_ready; +output [47 -1:0] sdp_n2mcif_rd_req_pd; +input mcif2sdp_n_rd_rsp_valid; +output mcif2sdp_n_rd_rsp_ready; +input [65 -1:0] mcif2sdp_n_rd_rsp_pd; +output sdp2mcif_rd_cdt_lat_fifo_pop; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +output [47 -1:0] sdp2mcif_rd_req_pd; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +input [65 -1:0] mcif2sdp_rd_rsp_pd; +output sdp2mcif_wr_req_valid; +input sdp2mcif_wr_req_ready; +output [66 -1:0] sdp2mcif_wr_req_pd; +input mcif2sdp_wr_rsp_complete; +wire dp2reg_done; +wire [31:0] dp2reg_out_saturation; +wire [31:0] dp2reg_status_nan_output_num; +wire [0:0] dp2reg_status_unequal; +wire [31:0] dp2reg_wdma_stall; +wire [4:0] reg2dp_batch_number; +wire reg2dp_bcore_slcg_op_en; +wire reg2dp_flying_mode; +wire [12:0] reg2dp_height; +wire reg2dp_interrupt_ptr; +wire [1:0] reg2dp_bn_alu_algo; +wire reg2dp_bn_alu_bypass; +wire [15:0] reg2dp_bn_alu_operand; +wire [5:0] reg2dp_bn_alu_shift_value; +wire reg2dp_bn_alu_src; +wire reg2dp_bn_bypass; +wire reg2dp_bn_mul_bypass; +wire [15:0] reg2dp_bn_mul_operand; +wire reg2dp_bn_mul_prelu; +wire [7:0] reg2dp_bn_mul_shift_value; +wire reg2dp_bn_mul_src; +wire reg2dp_bn_relu_bypass; +wire [1:0] reg2dp_bs_alu_algo; +wire reg2dp_bs_alu_bypass; +wire [15:0] reg2dp_bs_alu_operand; +wire [5:0] reg2dp_bs_alu_shift_value; +wire reg2dp_bs_alu_src; +wire reg2dp_bs_bypass; +wire reg2dp_bs_mul_bypass; +wire [15:0] reg2dp_bs_mul_operand; +wire reg2dp_bs_mul_prelu; +wire [7:0] reg2dp_bs_mul_shift_value; +wire reg2dp_bs_mul_src; +wire reg2dp_bs_relu_bypass; +wire [12:0] reg2dp_channel; +wire [31:0] reg2dp_cvt_offset; +wire [15:0] reg2dp_cvt_scale; +wire [5:0] reg2dp_cvt_shift; +wire [31:0] reg2dp_dst_base_addr_high; +wire [31:0] reg2dp_dst_base_addr_low; +wire [31:0] reg2dp_dst_batch_stride; +wire [31:0] reg2dp_dst_line_stride; +wire reg2dp_dst_ram_type; +wire [31:0] reg2dp_dst_surface_stride; +wire reg2dp_ecore_slcg_op_en; +wire reg2dp_nan_to_zero; +wire reg2dp_ncore_slcg_op_en; +wire reg2dp_op_en; +wire [1:0] reg2dp_out_precision; +wire reg2dp_output_dst; +wire reg2dp_perf_dma_en; +wire reg2dp_perf_lut_en; +wire reg2dp_perf_sat_en; +wire [1:0] reg2dp_proc_precision; +wire reg2dp_wdma_slcg_op_en; +wire [12:0] reg2dp_width; +wire reg2dp_winograd; +wire [32*8 +1:0] sdp_mrdma2cmux_pd; +wire sdp_mrdma2cmux_ready; +wire sdp_mrdma2cmux_valid; +wire sdp_dp2wdma_ready; +wire sdp_dp2wdma_valid; +wire [8*8 -1:0] sdp_dp2wdma_pd; +wire [8*16:0] sdp_brdma2dp_alu_pd; +wire sdp_brdma2dp_alu_ready; +wire sdp_brdma2dp_alu_valid; +wire [8*16:0] sdp_brdma2dp_mul_pd; +wire sdp_brdma2dp_mul_ready; +wire sdp_brdma2dp_mul_valid; +wire [8*16:0] sdp_nrdma2dp_alu_pd; +wire sdp_nrdma2dp_alu_ready; +wire sdp_nrdma2dp_alu_valid; +wire [8*16:0] sdp_nrdma2dp_mul_pd; +wire sdp_nrdma2dp_mul_ready; +wire sdp_nrdma2dp_mul_valid; +//======================================= +//DMA +//--------------------------------------- +NV_NVDLA_SDP_rdma u_rdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[47 -1:0]) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[65 -1:0]) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[47 -1:0]) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[65 -1:0]) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[47 -1:0]) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[65 -1:0]) + ,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) + ,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) + ,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) + ,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) + ,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) + ,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) + ,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) + ,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) + ,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) + ,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) + ,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) + ,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +NV_NVDLA_SDP_wdma u_wdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd[66 -1:0]) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) + ,.reg2dp_ew_alu_algo ( 2'b0 ) //reg2dp_ew_alu_algo[1:0]) + ,.reg2dp_ew_alu_bypass ( 1'b1 ) //reg2dp_ew_alu_bypass) + ,.reg2dp_ew_bypass ( 1'b1 ) //reg2dp_ew_bypass) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_wdma_slcg_op_en (reg2dp_wdma_slcg_op_en) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) + ,.reg2dp_winograd (reg2dp_winograd) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:3]) + ,.reg2dp_dst_batch_stride (reg2dp_dst_batch_stride[31:3]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:3]) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:3]) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) + ,.dp2reg_status_unequal (dp2reg_status_unequal) + ,.dp2reg_wdma_stall (dp2reg_wdma_stall[31:0]) + ); +//======================================== +//SDP core instance +//---------------------------------------- +NV_NVDLA_SDP_core u_core ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd[32*1 +1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) + ,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) + ,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) + ,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) + ,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) + ,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) + ,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) + ,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) + ,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) + ,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) + ,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) + ,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd[8*1 -1:0]) + ,.reg2dp_ncore_slcg_op_en (reg2dp_ncore_slcg_op_en) + ,.reg2dp_bn_alu_algo (reg2dp_bn_alu_algo[1:0]) + ,.reg2dp_bn_alu_bypass (reg2dp_bn_alu_bypass) + ,.reg2dp_bn_alu_operand (reg2dp_bn_alu_operand[15:0]) + ,.reg2dp_bn_alu_shift_value (reg2dp_bn_alu_shift_value[5:0]) + ,.reg2dp_bn_alu_src (reg2dp_bn_alu_src) + ,.reg2dp_bn_bypass (reg2dp_bn_bypass) + ,.reg2dp_bn_mul_bypass (reg2dp_bn_mul_bypass) + ,.reg2dp_bn_mul_operand (reg2dp_bn_mul_operand[15:0]) + ,.reg2dp_bn_mul_prelu (reg2dp_bn_mul_prelu) + ,.reg2dp_bn_mul_shift_value (reg2dp_bn_mul_shift_value[7:0]) + ,.reg2dp_bn_mul_src (reg2dp_bn_mul_src) + ,.reg2dp_bn_relu_bypass (reg2dp_bn_relu_bypass) + ,.reg2dp_bcore_slcg_op_en (reg2dp_bcore_slcg_op_en) + ,.reg2dp_bs_alu_algo (reg2dp_bs_alu_algo[1:0]) + ,.reg2dp_bs_alu_bypass (reg2dp_bs_alu_bypass) + ,.reg2dp_bs_alu_operand (reg2dp_bs_alu_operand[15:0]) + ,.reg2dp_bs_alu_shift_value (reg2dp_bs_alu_shift_value[5:0]) + ,.reg2dp_bs_alu_src (reg2dp_bs_alu_src) + ,.reg2dp_bs_bypass (reg2dp_bs_bypass) + ,.reg2dp_bs_mul_bypass (reg2dp_bs_mul_bypass) + ,.reg2dp_bs_mul_operand (reg2dp_bs_mul_operand[15:0]) + ,.reg2dp_bs_mul_prelu (reg2dp_bs_mul_prelu) + ,.reg2dp_bs_mul_shift_value (reg2dp_bs_mul_shift_value[7:0]) + ,.reg2dp_bs_mul_src (reg2dp_bs_mul_src) + ,.reg2dp_bs_relu_bypass (reg2dp_bs_relu_bypass) + ,.reg2dp_ecore_slcg_op_en (reg2dp_ecore_slcg_op_en) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[31:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_cvt_shift (reg2dp_cvt_shift[5:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) + ,.reg2dp_perf_lut_en (reg2dp_perf_lut_en) + ,.reg2dp_perf_sat_en (reg2dp_perf_sat_en) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_out_saturation (dp2reg_out_saturation[31:0]) + ); +//======================================= +//CONFIG instance +//rdma has seperate config register, while wdma share with core +//--------------------------------------- +NV_NVDLA_SDP_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2sdp_req_pd (csb2sdp_req_pd[62:0]) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd[33:0]) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_out_saturation (dp2reg_out_saturation[31:0]) + ,.dp2reg_status_inf_input_num ({32{1'b0}}) + ,.dp2reg_status_nan_input_num ({32{1'b0}}) + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) + ,.dp2reg_status_unequal (dp2reg_status_unequal[0]) + ,.dp2reg_wdma_stall (dp2reg_wdma_stall[31:0]) + ,.reg2dp_ncore_slcg_op_en (reg2dp_ncore_slcg_op_en) + ,.reg2dp_bn_alu_algo (reg2dp_bn_alu_algo[1:0]) + ,.reg2dp_bn_alu_bypass (reg2dp_bn_alu_bypass) + ,.reg2dp_bn_alu_operand (reg2dp_bn_alu_operand[15:0]) + ,.reg2dp_bn_alu_shift_value (reg2dp_bn_alu_shift_value[5:0]) + ,.reg2dp_bn_alu_src (reg2dp_bn_alu_src) + ,.reg2dp_bn_bypass (reg2dp_bn_bypass) + ,.reg2dp_bn_mul_bypass (reg2dp_bn_mul_bypass) + ,.reg2dp_bn_mul_operand (reg2dp_bn_mul_operand[15:0]) + ,.reg2dp_bn_mul_prelu (reg2dp_bn_mul_prelu) + ,.reg2dp_bn_mul_shift_value (reg2dp_bn_mul_shift_value[7:0]) + ,.reg2dp_bn_mul_src (reg2dp_bn_mul_src) + ,.reg2dp_bn_relu_bypass (reg2dp_bn_relu_bypass) + ,.reg2dp_bcore_slcg_op_en (reg2dp_bcore_slcg_op_en) + ,.reg2dp_bs_alu_algo (reg2dp_bs_alu_algo[1:0]) + ,.reg2dp_bs_alu_bypass (reg2dp_bs_alu_bypass) + ,.reg2dp_bs_alu_operand (reg2dp_bs_alu_operand[15:0]) + ,.reg2dp_bs_alu_shift_value (reg2dp_bs_alu_shift_value[5:0]) + ,.reg2dp_bs_alu_src (reg2dp_bs_alu_src) + ,.reg2dp_bs_bypass (reg2dp_bs_bypass) + ,.reg2dp_bs_mul_bypass (reg2dp_bs_mul_bypass) + ,.reg2dp_bs_mul_operand (reg2dp_bs_mul_operand[15:0]) + ,.reg2dp_bs_mul_prelu (reg2dp_bs_mul_prelu) + ,.reg2dp_bs_mul_shift_value (reg2dp_bs_mul_shift_value[7:0]) + ,.reg2dp_bs_mul_src (reg2dp_bs_mul_src) + ,.reg2dp_bs_relu_bypass (reg2dp_bs_relu_bypass) + ,.reg2dp_ecore_slcg_op_en (reg2dp_ecore_slcg_op_en) + ,.dp2reg_lut_hybrid ( 32'h0) //dp2reg_lut_hybrid[31:0]) + ,.dp2reg_lut_int_data ( 16'h0) //dp2reg_lut_int_data[15:0]) + ,.dp2reg_lut_le_hit ( 32'h0) //dp2reg_lut_le_hit[31:0]) + ,.dp2reg_lut_lo_hit ( 32'h0) //dp2reg_lut_lo_hit[31:0]) + ,.dp2reg_lut_oflow ( 32'h0) //dp2reg_lut_oflow[31:0]) + ,.dp2reg_lut_uflow ( 32'h0) //dp2reg_lut_uflow[31:0]) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[31:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_cvt_shift (reg2dp_cvt_shift[5:0]) + ,.reg2dp_wdma_slcg_op_en (reg2dp_wdma_slcg_op_en) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) + ,.reg2dp_winograd (reg2dp_winograd) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_batch_stride (reg2dp_dst_batch_stride[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) + ,.reg2dp_perf_lut_en (reg2dp_perf_lut_en) + ,.reg2dp_perf_nan_inf_count_en () + ,.reg2dp_perf_sat_en (reg2dp_perf_sat_en) + ); +endmodule // NV_NVDLA_sdp diff --git a/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.v.vcp b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.v.vcp new file mode 100644 index 0000000..5f2dabb --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/sdp/NV_NVDLA_sdp.v.vcp @@ -0,0 +1,440 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_sdp.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_SDP_define.h +module NV_NVDLA_sdp ( + cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,cacc2sdp_ready //|> o + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,csb2sdp_req_pd //|< i + ,csb2sdp_req_pvld //|< i + ,dla_clk_ovr_on_sync //|< i + ,global_clk_ovr_on_sync //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_rd_req_ready //|< i + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp2mcif_wr_req_pd //|> o + ,sdp2mcif_wr_req_valid //|> o + ,sdp2mcif_wr_req_ready //|< i + ,mcif2sdp_wr_rsp_complete //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,pwrbus_ram_pd //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,sdp2glb_done_intr_pd //|> o + ,csb2sdp_rdma_req_prdy //|> o + ,csb2sdp_req_prdy //|> o + ,sdp2csb_resp_pd //|> o + ,sdp2csb_resp_valid //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ,sdp2pdp_pd //|> o + ,sdp2pdp_valid //|> o + ,sdp2pdp_ready //|< i + ); +// +// NV_NVDLA_sdp_ports.v +// +input nvdla_core_clk; +input nvdla_core_rstn; +input [31:0] pwrbus_ram_pd; +input dla_clk_ovr_on_sync; +input global_clk_ovr_on_sync; +input tmc2slcg_disable_clock_gating; +input cacc2sdp_valid; +output cacc2sdp_ready; +input [32*1 +1:0] cacc2sdp_pd; +output sdp2pdp_valid; +input sdp2pdp_ready; +output [8*1 -1:0] sdp2pdp_pd; +output [1:0] sdp2glb_done_intr_pd; +input csb2sdp_rdma_req_pvld; +output csb2sdp_rdma_req_prdy; +input [62:0] csb2sdp_rdma_req_pd; +output sdp_rdma2csb_resp_valid; +output [33:0] sdp_rdma2csb_resp_pd; +input csb2sdp_req_pvld; +output csb2sdp_req_prdy; +input [62:0] csb2sdp_req_pd; +output sdp2csb_resp_valid; +output [33:0] sdp2csb_resp_pd; +output sdp_b2mcif_rd_cdt_lat_fifo_pop; +output sdp_b2mcif_rd_req_valid; +input sdp_b2mcif_rd_req_ready; +output [47 -1:0] sdp_b2mcif_rd_req_pd; +input mcif2sdp_b_rd_rsp_valid; +output mcif2sdp_b_rd_rsp_ready; +input [65 -1:0] mcif2sdp_b_rd_rsp_pd; +output sdp_n2mcif_rd_cdt_lat_fifo_pop; +output sdp_n2mcif_rd_req_valid; +input sdp_n2mcif_rd_req_ready; +output [47 -1:0] sdp_n2mcif_rd_req_pd; +input mcif2sdp_n_rd_rsp_valid; +output mcif2sdp_n_rd_rsp_ready; +input [65 -1:0] mcif2sdp_n_rd_rsp_pd; +output sdp2mcif_rd_cdt_lat_fifo_pop; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +output [47 -1:0] sdp2mcif_rd_req_pd; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +input [65 -1:0] mcif2sdp_rd_rsp_pd; +output sdp2mcif_wr_req_valid; +input sdp2mcif_wr_req_ready; +output [66 -1:0] sdp2mcif_wr_req_pd; +input mcif2sdp_wr_rsp_complete; +wire dp2reg_done; +wire [31:0] dp2reg_out_saturation; +wire [31:0] dp2reg_status_nan_output_num; +wire [0:0] dp2reg_status_unequal; +wire [31:0] dp2reg_wdma_stall; +wire [4:0] reg2dp_batch_number; +wire reg2dp_bcore_slcg_op_en; +wire reg2dp_flying_mode; +wire [12:0] reg2dp_height; +wire reg2dp_interrupt_ptr; +wire [1:0] reg2dp_bn_alu_algo; +wire reg2dp_bn_alu_bypass; +wire [15:0] reg2dp_bn_alu_operand; +wire [5:0] reg2dp_bn_alu_shift_value; +wire reg2dp_bn_alu_src; +wire reg2dp_bn_bypass; +wire reg2dp_bn_mul_bypass; +wire [15:0] reg2dp_bn_mul_operand; +wire reg2dp_bn_mul_prelu; +wire [7:0] reg2dp_bn_mul_shift_value; +wire reg2dp_bn_mul_src; +wire reg2dp_bn_relu_bypass; +wire [1:0] reg2dp_bs_alu_algo; +wire reg2dp_bs_alu_bypass; +wire [15:0] reg2dp_bs_alu_operand; +wire [5:0] reg2dp_bs_alu_shift_value; +wire reg2dp_bs_alu_src; +wire reg2dp_bs_bypass; +wire reg2dp_bs_mul_bypass; +wire [15:0] reg2dp_bs_mul_operand; +wire reg2dp_bs_mul_prelu; +wire [7:0] reg2dp_bs_mul_shift_value; +wire reg2dp_bs_mul_src; +wire reg2dp_bs_relu_bypass; +wire [12:0] reg2dp_channel; +wire [31:0] reg2dp_cvt_offset; +wire [15:0] reg2dp_cvt_scale; +wire [5:0] reg2dp_cvt_shift; +wire [31:0] reg2dp_dst_base_addr_high; +wire [31:0] reg2dp_dst_base_addr_low; +wire [31:0] reg2dp_dst_batch_stride; +wire [31:0] reg2dp_dst_line_stride; +wire reg2dp_dst_ram_type; +wire [31:0] reg2dp_dst_surface_stride; +wire reg2dp_ecore_slcg_op_en; +wire reg2dp_nan_to_zero; +wire reg2dp_ncore_slcg_op_en; +wire reg2dp_op_en; +wire [1:0] reg2dp_out_precision; +wire reg2dp_output_dst; +wire reg2dp_perf_dma_en; +wire reg2dp_perf_lut_en; +wire reg2dp_perf_sat_en; +wire [1:0] reg2dp_proc_precision; +wire reg2dp_wdma_slcg_op_en; +wire [12:0] reg2dp_width; +wire reg2dp_winograd; +wire [32*8 +1:0] sdp_mrdma2cmux_pd; +wire sdp_mrdma2cmux_ready; +wire sdp_mrdma2cmux_valid; +wire sdp_dp2wdma_ready; +wire sdp_dp2wdma_valid; +wire [8*8 -1:0] sdp_dp2wdma_pd; +wire [8*16:0] sdp_brdma2dp_alu_pd; +wire sdp_brdma2dp_alu_ready; +wire sdp_brdma2dp_alu_valid; +wire [8*16:0] sdp_brdma2dp_mul_pd; +wire sdp_brdma2dp_mul_ready; +wire sdp_brdma2dp_mul_valid; +wire [8*16:0] sdp_nrdma2dp_alu_pd; +wire sdp_nrdma2dp_alu_ready; +wire sdp_nrdma2dp_alu_valid; +wire [8*16:0] sdp_nrdma2dp_mul_pd; +wire sdp_nrdma2dp_mul_ready; +wire sdp_nrdma2dp_mul_valid; +//======================================= +//DMA +//--------------------------------------- +NV_NVDLA_SDP_rdma u_rdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd[47 -1:0]) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd[65 -1:0]) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd[47 -1:0]) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd[65 -1:0]) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd[47 -1:0]) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd[65 -1:0]) + ,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) + ,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) + ,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) + ,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) + ,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) + ,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) + ,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) + ,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) + ,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) + ,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) + ,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) + ,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +NV_NVDLA_SDP_wdma u_wdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd[66 -1:0]) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) + ,.reg2dp_ew_alu_algo ( 2'b0 ) //reg2dp_ew_alu_algo[1:0]) + ,.reg2dp_ew_alu_bypass ( 1'b1 ) //reg2dp_ew_alu_bypass) + ,.reg2dp_ew_bypass ( 1'b1 ) //reg2dp_ew_bypass) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_wdma_slcg_op_en (reg2dp_wdma_slcg_op_en) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) + ,.reg2dp_winograd (reg2dp_winograd) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:3]) + ,.reg2dp_dst_batch_stride (reg2dp_dst_batch_stride[31:3]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:3]) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:3]) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) + ,.dp2reg_status_unequal (dp2reg_status_unequal) + ,.dp2reg_wdma_stall (dp2reg_wdma_stall[31:0]) + ); +//======================================== +//SDP core instance +//---------------------------------------- +NV_NVDLA_SDP_core u_core ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd[32*1 +1:0]) + ,.sdp_mrdma2cmux_valid (sdp_mrdma2cmux_valid) + ,.sdp_mrdma2cmux_ready (sdp_mrdma2cmux_ready) + ,.sdp_mrdma2cmux_pd (sdp_mrdma2cmux_pd[32*8 +1:0]) + ,.sdp_brdma2dp_mul_valid (sdp_brdma2dp_mul_valid) + ,.sdp_brdma2dp_mul_ready (sdp_brdma2dp_mul_ready) + ,.sdp_brdma2dp_mul_pd (sdp_brdma2dp_mul_pd[8*16:0]) + ,.sdp_brdma2dp_alu_valid (sdp_brdma2dp_alu_valid) + ,.sdp_brdma2dp_alu_ready (sdp_brdma2dp_alu_ready) + ,.sdp_brdma2dp_alu_pd (sdp_brdma2dp_alu_pd[8*16:0]) + ,.sdp_nrdma2dp_mul_valid (sdp_nrdma2dp_mul_valid) + ,.sdp_nrdma2dp_mul_ready (sdp_nrdma2dp_mul_ready) + ,.sdp_nrdma2dp_mul_pd (sdp_nrdma2dp_mul_pd[8*16:0]) + ,.sdp_nrdma2dp_alu_valid (sdp_nrdma2dp_alu_valid) + ,.sdp_nrdma2dp_alu_ready (sdp_nrdma2dp_alu_ready) + ,.sdp_nrdma2dp_alu_pd (sdp_nrdma2dp_alu_pd[8*16:0]) + ,.sdp_dp2wdma_valid (sdp_dp2wdma_valid) + ,.sdp_dp2wdma_ready (sdp_dp2wdma_ready) + ,.sdp_dp2wdma_pd (sdp_dp2wdma_pd[8*8 -1:0]) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd[8*1 -1:0]) + ,.reg2dp_ncore_slcg_op_en (reg2dp_ncore_slcg_op_en) + ,.reg2dp_bn_alu_algo (reg2dp_bn_alu_algo[1:0]) + ,.reg2dp_bn_alu_bypass (reg2dp_bn_alu_bypass) + ,.reg2dp_bn_alu_operand (reg2dp_bn_alu_operand[15:0]) + ,.reg2dp_bn_alu_shift_value (reg2dp_bn_alu_shift_value[5:0]) + ,.reg2dp_bn_alu_src (reg2dp_bn_alu_src) + ,.reg2dp_bn_bypass (reg2dp_bn_bypass) + ,.reg2dp_bn_mul_bypass (reg2dp_bn_mul_bypass) + ,.reg2dp_bn_mul_operand (reg2dp_bn_mul_operand[15:0]) + ,.reg2dp_bn_mul_prelu (reg2dp_bn_mul_prelu) + ,.reg2dp_bn_mul_shift_value (reg2dp_bn_mul_shift_value[7:0]) + ,.reg2dp_bn_mul_src (reg2dp_bn_mul_src) + ,.reg2dp_bn_relu_bypass (reg2dp_bn_relu_bypass) + ,.reg2dp_bcore_slcg_op_en (reg2dp_bcore_slcg_op_en) + ,.reg2dp_bs_alu_algo (reg2dp_bs_alu_algo[1:0]) + ,.reg2dp_bs_alu_bypass (reg2dp_bs_alu_bypass) + ,.reg2dp_bs_alu_operand (reg2dp_bs_alu_operand[15:0]) + ,.reg2dp_bs_alu_shift_value (reg2dp_bs_alu_shift_value[5:0]) + ,.reg2dp_bs_alu_src (reg2dp_bs_alu_src) + ,.reg2dp_bs_bypass (reg2dp_bs_bypass) + ,.reg2dp_bs_mul_bypass (reg2dp_bs_mul_bypass) + ,.reg2dp_bs_mul_operand (reg2dp_bs_mul_operand[15:0]) + ,.reg2dp_bs_mul_prelu (reg2dp_bs_mul_prelu) + ,.reg2dp_bs_mul_shift_value (reg2dp_bs_mul_shift_value[7:0]) + ,.reg2dp_bs_mul_src (reg2dp_bs_mul_src) + ,.reg2dp_bs_relu_bypass (reg2dp_bs_relu_bypass) + ,.reg2dp_ecore_slcg_op_en (reg2dp_ecore_slcg_op_en) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[31:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_cvt_shift (reg2dp_cvt_shift[5:0]) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) + ,.reg2dp_perf_lut_en (reg2dp_perf_lut_en) + ,.reg2dp_perf_sat_en (reg2dp_perf_sat_en) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_out_saturation (dp2reg_out_saturation[31:0]) + ); +//======================================= +//CONFIG instance +//rdma has seperate config register, while wdma share with core +//--------------------------------------- +NV_NVDLA_SDP_reg u_reg ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.csb2sdp_req_pd (csb2sdp_req_pd[62:0]) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd[33:0]) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.dp2reg_done (dp2reg_done) + ,.dp2reg_out_saturation (dp2reg_out_saturation[31:0]) + ,.dp2reg_status_inf_input_num ({32{1'b0}}) + ,.dp2reg_status_nan_input_num ({32{1'b0}}) + ,.dp2reg_status_nan_output_num (dp2reg_status_nan_output_num[31:0]) + ,.dp2reg_status_unequal (dp2reg_status_unequal[0]) + ,.dp2reg_wdma_stall (dp2reg_wdma_stall[31:0]) + ,.reg2dp_ncore_slcg_op_en (reg2dp_ncore_slcg_op_en) + ,.reg2dp_bn_alu_algo (reg2dp_bn_alu_algo[1:0]) + ,.reg2dp_bn_alu_bypass (reg2dp_bn_alu_bypass) + ,.reg2dp_bn_alu_operand (reg2dp_bn_alu_operand[15:0]) + ,.reg2dp_bn_alu_shift_value (reg2dp_bn_alu_shift_value[5:0]) + ,.reg2dp_bn_alu_src (reg2dp_bn_alu_src) + ,.reg2dp_bn_bypass (reg2dp_bn_bypass) + ,.reg2dp_bn_mul_bypass (reg2dp_bn_mul_bypass) + ,.reg2dp_bn_mul_operand (reg2dp_bn_mul_operand[15:0]) + ,.reg2dp_bn_mul_prelu (reg2dp_bn_mul_prelu) + ,.reg2dp_bn_mul_shift_value (reg2dp_bn_mul_shift_value[7:0]) + ,.reg2dp_bn_mul_src (reg2dp_bn_mul_src) + ,.reg2dp_bn_relu_bypass (reg2dp_bn_relu_bypass) + ,.reg2dp_bcore_slcg_op_en (reg2dp_bcore_slcg_op_en) + ,.reg2dp_bs_alu_algo (reg2dp_bs_alu_algo[1:0]) + ,.reg2dp_bs_alu_bypass (reg2dp_bs_alu_bypass) + ,.reg2dp_bs_alu_operand (reg2dp_bs_alu_operand[15:0]) + ,.reg2dp_bs_alu_shift_value (reg2dp_bs_alu_shift_value[5:0]) + ,.reg2dp_bs_alu_src (reg2dp_bs_alu_src) + ,.reg2dp_bs_bypass (reg2dp_bs_bypass) + ,.reg2dp_bs_mul_bypass (reg2dp_bs_mul_bypass) + ,.reg2dp_bs_mul_operand (reg2dp_bs_mul_operand[15:0]) + ,.reg2dp_bs_mul_prelu (reg2dp_bs_mul_prelu) + ,.reg2dp_bs_mul_shift_value (reg2dp_bs_mul_shift_value[7:0]) + ,.reg2dp_bs_mul_src (reg2dp_bs_mul_src) + ,.reg2dp_bs_relu_bypass (reg2dp_bs_relu_bypass) + ,.reg2dp_ecore_slcg_op_en (reg2dp_ecore_slcg_op_en) + ,.dp2reg_lut_hybrid ( 32'h0) //dp2reg_lut_hybrid[31:0]) + ,.dp2reg_lut_int_data ( 16'h0) //dp2reg_lut_int_data[15:0]) + ,.dp2reg_lut_le_hit ( 32'h0) //dp2reg_lut_le_hit[31:0]) + ,.dp2reg_lut_lo_hit ( 32'h0) //dp2reg_lut_lo_hit[31:0]) + ,.dp2reg_lut_oflow ( 32'h0) //dp2reg_lut_oflow[31:0]) + ,.dp2reg_lut_uflow ( 32'h0) //dp2reg_lut_uflow[31:0]) + ,.reg2dp_cvt_offset (reg2dp_cvt_offset[31:0]) + ,.reg2dp_cvt_scale (reg2dp_cvt_scale[15:0]) + ,.reg2dp_cvt_shift (reg2dp_cvt_shift[5:0]) + ,.reg2dp_wdma_slcg_op_en (reg2dp_wdma_slcg_op_en) + ,.reg2dp_op_en (reg2dp_op_en) + ,.reg2dp_flying_mode (reg2dp_flying_mode) + ,.reg2dp_output_dst (reg2dp_output_dst) + ,.reg2dp_batch_number (reg2dp_batch_number[4:0]) + ,.reg2dp_winograd (reg2dp_winograd) + ,.reg2dp_channel (reg2dp_channel[12:0]) + ,.reg2dp_height (reg2dp_height[12:0]) + ,.reg2dp_width (reg2dp_width[12:0]) + ,.reg2dp_dst_ram_type (reg2dp_dst_ram_type) + ,.reg2dp_dst_base_addr_high (reg2dp_dst_base_addr_high[31:0]) + ,.reg2dp_dst_base_addr_low (reg2dp_dst_base_addr_low[31:0]) + ,.reg2dp_dst_batch_stride (reg2dp_dst_batch_stride[31:0]) + ,.reg2dp_dst_line_stride (reg2dp_dst_line_stride[31:0]) + ,.reg2dp_dst_surface_stride (reg2dp_dst_surface_stride[31:0]) + ,.reg2dp_nan_to_zero (reg2dp_nan_to_zero) + ,.reg2dp_proc_precision (reg2dp_proc_precision[1:0]) + ,.reg2dp_out_precision (reg2dp_out_precision[1:0]) + ,.reg2dp_interrupt_ptr (reg2dp_interrupt_ptr) + ,.reg2dp_perf_dma_en (reg2dp_perf_dma_en) + ,.reg2dp_perf_lut_en (reg2dp_perf_lut_en) + ,.reg2dp_perf_nan_inf_count_en () + ,.reg2dp_perf_sat_en (reg2dp_perf_sat_en) + ); +endmodule // NV_NVDLA_sdp diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_a.v b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_a.v new file mode 100644 index 0000000..eaa56f8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_a.v @@ -0,0 +1,246 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_a.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +`include "NV_HWACC_NVDLA_tick_defines.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_partition_a ( + cacc2sdp_ready + ,csb2cacc_req_pvld + ,csb2cacc_req_prdy + ,csb2cacc_req_pd + ,cacc2csb_resp_pd + ,cacc2csb_resp_valid + ,cacc2glb_done_intr_pd + ,direct_reset_ + ,dla_reset_rstn + ,global_clk_ovr_on +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_a2accu_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac_a2accu_data0 +,mac_a2accu_data1 +,mac_a2accu_data2 +,mac_a2accu_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac_a2accu_mask + ,mac_a2accu_mode + ,mac_a2accu_pd + ,mac_a2accu_pvld +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_b2accu_data${i} ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac_b2accu_data0 +,mac_b2accu_data1 +,mac_b2accu_data2 +,mac_b2accu_data3 +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac_b2accu_mask + ,mac_b2accu_mode + ,mac_b2accu_pd + ,mac_b2accu_pvld + ,nvdla_clk_ovr_on + ,nvdla_core_clk + ,pwrbus_ram_pd + ,test_mode + ,tmc2slcg_disable_clock_gating + ,accu2sc_credit_size + ,accu2sc_credit_vld + ,cacc2sdp_pd + ,cacc2sdp_valid + ); +// +// NV_NVDLA_partition_a_io.v +// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +output accu2sc_credit_vld; /* data valid */ +output [2:0] accu2sc_credit_size; +output cacc2csb_resp_valid; /* data valid */ +output [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] cacc2glb_done_intr_pd; +input csb2cacc_req_pvld; /* data valid */ +output csb2cacc_req_prdy; /* data return handshake */ +input [62:0] csb2cacc_req_pd; +output cacc2sdp_valid; /* data valid */ +input cacc2sdp_ready; /* data return handshake */ +output [32*1 +2 -1:0] cacc2sdp_pd; +input mac_a2accu_pvld; /* data valid */ +input [8/2 -1:0] mac_a2accu_mask; +input mac_a2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_a2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac_a2accu_data0; +input [19 -1:0] mac_a2accu_data1; +input [19 -1:0] mac_a2accu_data2; +input [19 -1:0] mac_a2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] mac_a2accu_pd; +input mac_b2accu_pvld; /* data valid */ +input [8/2 -1:0] mac_b2accu_mask; +input mac_b2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_b2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [19 -1:0] mac_b2accu_data0; +input [19 -1:0] mac_b2accu_data1; +input [19 -1:0] mac_b2accu_data2; +input [19 -1:0] mac_b2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] mac_b2accu_pd; +input [31:0] pwrbus_ram_pd; +//input la_r_clk; +//input larstn; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +wire dla_clk_ovr_on_sync; +wire global_clk_ovr_on_sync; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: wire [19 -1:0] mac_b2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [19 -1:0] mac_b2accu_data0; +wire [19 -1:0] mac_b2accu_data1; +wire [19 -1:0] mac_b2accu_data2; +wire [19 -1:0] mac_b2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8/2 -1:0] mac_b2accu_mask; +wire mac_b2accu_mode; +wire [8:0] mac_b2accu_pd; +wire mac_b2accu_pvld; +wire nvdla_core_rstn; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition M: Reset Syncer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_a_reset ( + .dla_reset_rstn (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.synced_rstn (nvdla_core_rstn) //|> w + ,.nvdla_clk (nvdla_core_clk) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) //|< i + ,.sync_i (nvdla_clk_ovr_on) //|< i + ,.sync_o (dla_clk_ovr_on_sync) //|> w + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync ( + .clk (nvdla_core_clk) //|< i + ,.prst (nvdla_core_rstn) //|< w + ,.sync_i (global_clk_ovr_on) //|< i + ,.sync_o (global_clk_ovr_on_sync) //|> w + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition A: Convolution Accumulator // +//////////////////////////////////////////////////////////////////////// +//stepheng, modify for cacc verification +NV_NVDLA_cacc u_NV_NVDLA_cacc ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd) + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd) + ,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i + ,.mac_a2accu_mask (mac_a2accu_mask[8/2 -1:0]) //|< i + ,.mac_a2accu_mode (mac_a2accu_mode) //|< i +//:for(my $i=0; $i<8/2; $i++){ +//: print ",.mac_a2accu_data${i} (mac_a2accu_data${i}) \n"; #//|< i +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.mac_a2accu_data0 (mac_a2accu_data0) +,.mac_a2accu_data1 (mac_a2accu_data1) +,.mac_a2accu_data2 (mac_a2accu_data2) +,.mac_a2accu_data3 (mac_a2accu_data3) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac_a2accu_pd (mac_a2accu_pd[8:0]) //|< i + ,.mac_b2accu_pvld (mac_b2accu_pvld) //|< w + ,.mac_b2accu_mask (mac_b2accu_mask[8/2 -1:0]) //|< w + ,.mac_b2accu_mode (mac_b2accu_mode) //|< w +//:for(my $i=0; $i<8/2; $i++){ +//: print ",.mac_b2accu_data${i} (mac_b2accu_data${i}) \n"; #//|< i +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) +,.mac_b2accu_data0 (mac_b2accu_data0) +,.mac_b2accu_data1 (mac_b2accu_data1) +,.mac_b2accu_data2 (mac_b2accu_data2) +,.mac_b2accu_data3 (mac_b2accu_data3) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac_b2accu_pd (mac_b2accu_pd[8:0]) //|< w + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.accu2sc_credit_vld (accu2sc_credit_vld) + ,.accu2sc_credit_size (accu2sc_credit_size) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition A: OBS // +//////////////////////////////////////////////////////////////////////// +//&Instance NV_NVDLA_A_obs; +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +//| +//| +//| +//| +endmodule // NV_NVDLA_partition_a diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_a.v.vcp b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_a.v.vcp new file mode 100644 index 0000000..7ccf674 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_a.v.vcp @@ -0,0 +1,197 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_a.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +`include "NV_HWACC_NVDLA_tick_defines.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CACC.h +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_partition_a ( + cacc2sdp_ready + ,csb2cacc_req_pvld + ,csb2cacc_req_prdy + ,csb2cacc_req_pd + ,cacc2csb_resp_pd + ,cacc2csb_resp_valid + ,cacc2glb_done_intr_pd + ,direct_reset_ + ,dla_reset_rstn + ,global_clk_ovr_on +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_a2accu_data${i} ) +//: } + ,mac_a2accu_mask + ,mac_a2accu_mode + ,mac_a2accu_pd + ,mac_a2accu_pvld +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac_b2accu_data${i} ) +//: } + ,mac_b2accu_mask + ,mac_b2accu_mode + ,mac_b2accu_pd + ,mac_b2accu_pvld + ,nvdla_clk_ovr_on + ,nvdla_core_clk + ,pwrbus_ram_pd + ,test_mode + ,tmc2slcg_disable_clock_gating + ,accu2sc_credit_size + ,accu2sc_credit_vld + ,cacc2sdp_pd + ,cacc2sdp_valid + ); +// +// NV_NVDLA_partition_a_io.v +// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +output accu2sc_credit_vld; /* data valid */ +output [2:0] accu2sc_credit_size; +output cacc2csb_resp_valid; /* data valid */ +output [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] cacc2glb_done_intr_pd; +input csb2cacc_req_pvld; /* data valid */ +output csb2cacc_req_prdy; /* data return handshake */ +input [62:0] csb2cacc_req_pd; +output cacc2sdp_valid; /* data valid */ +input cacc2sdp_ready; /* data return handshake */ +output [32*1 +2 -1:0] cacc2sdp_pd; +input mac_a2accu_pvld; /* data valid */ +input [8/2 -1:0] mac_a2accu_mask; +input mac_a2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_a2accu_data${i}; ) +//: } +input [8:0] mac_a2accu_pd; +input mac_b2accu_pvld; /* data valid */ +input [8/2 -1:0] mac_b2accu_mask; +input mac_b2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: input [19 -1:0] mac_b2accu_data${i}; ) +//: } +input [8:0] mac_b2accu_pd; +input [31:0] pwrbus_ram_pd; +//input la_r_clk; +//input larstn; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +wire dla_clk_ovr_on_sync; +wire global_clk_ovr_on_sync; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: wire [19 -1:0] mac_b2accu_data${i}; ) +//: } +wire [8/2 -1:0] mac_b2accu_mask; +wire mac_b2accu_mode; +wire [8:0] mac_b2accu_pd; +wire mac_b2accu_pvld; +wire nvdla_core_rstn; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition M: Reset Syncer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_a_reset ( + .dla_reset_rstn (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.synced_rstn (nvdla_core_rstn) //|> w + ,.nvdla_clk (nvdla_core_clk) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) //|< i + ,.sync_i (nvdla_clk_ovr_on) //|< i + ,.sync_o (dla_clk_ovr_on_sync) //|> w + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync ( + .clk (nvdla_core_clk) //|< i + ,.prst (nvdla_core_rstn) //|< w + ,.sync_i (global_clk_ovr_on) //|< i + ,.sync_o (global_clk_ovr_on_sync) //|> w + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition A: Convolution Accumulator // +//////////////////////////////////////////////////////////////////////// +//stepheng, modify for cacc verification +NV_NVDLA_cacc u_NV_NVDLA_cacc ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd) + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd) + ,.mac_a2accu_pvld (mac_a2accu_pvld) //|< i + ,.mac_a2accu_mask (mac_a2accu_mask[8/2 -1:0]) //|< i + ,.mac_a2accu_mode (mac_a2accu_mode) //|< i +//:for(my $i=0; $i<8/2; $i++){ +//: print ",.mac_a2accu_data${i} (mac_a2accu_data${i}) \n"; #//|< i +//: } + ,.mac_a2accu_pd (mac_a2accu_pd[8:0]) //|< i + ,.mac_b2accu_pvld (mac_b2accu_pvld) //|< w + ,.mac_b2accu_mask (mac_b2accu_mask[8/2 -1:0]) //|< w + ,.mac_b2accu_mode (mac_b2accu_mode) //|< w +//:for(my $i=0; $i<8/2; $i++){ +//: print ",.mac_b2accu_data${i} (mac_b2accu_data${i}) \n"; #//|< i +//: } + ,.mac_b2accu_pd (mac_b2accu_pd[8:0]) //|< w + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.accu2sc_credit_vld (accu2sc_credit_vld) + ,.accu2sc_credit_size (accu2sc_credit_size) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition A: OBS // +//////////////////////////////////////////////////////////////////////// +//&Instance NV_NVDLA_A_obs; +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +//| +//| +//| +//| +endmodule // NV_NVDLA_partition_a diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_c.v b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_c.v new file mode 100644 index 0000000..7f5fbd5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_c.v @@ -0,0 +1,791 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_c.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +module NV_NVDLA_partition_c ( + accu2sc_credit_size //|< i + ,accu2sc_credit_vld //|< i + ,cdma_dat2mcif_rd_req_ready //|< i + ,cdma_wt2mcif_rd_req_ready //|< i + ,csb2cdma_req_pd //|< i + ,csb2cdma_req_pvld //|< i + ,csb2csc_req_pd //|< i + ,csb2csc_req_pvld //|< i + ,direct_reset_ //|< i + ,dla_reset_rstn //|< i + ,global_clk_ovr_on //|< i + ,mcif2cdma_dat_rd_rsp_pd //|< i + ,mcif2cdma_dat_rd_rsp_valid //|< i + ,mcif2cdma_wt_rd_rsp_pd //|< i + ,mcif2cdma_wt_rd_rsp_valid //|< i + ,nvdla_clk_ovr_on //|< i + ,nvdla_core_clk //|< i + ,pwrbus_ram_pd //|< i + ,test_mode //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cdma2csb_resp_pd //|> o + ,cdma2csb_resp_valid //|> o + ,cdma_dat2glb_done_intr_pd //|> o + ,cdma_dat2mcif_rd_req_pd //|> o + ,cdma_dat2mcif_rd_req_valid //|> o + ,cdma_wt2glb_done_intr_pd //|> o + ,cdma_wt2mcif_rd_req_pd //|> o + ,cdma_wt2mcif_rd_req_valid //|> o + ,csb2cdma_req_prdy //|> o + ,csb2csc_req_prdy //|> o + ,csc2csb_resp_pd //|> o + ,csc2csb_resp_valid //|> o + ,mcif2cdma_dat_rd_rsp_ready //|> o + ,mcif2cdma_wt_rd_rsp_ready //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_a_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_a_data0 //|> o +,sc2mac_dat_a_data1 //|> o +,sc2mac_dat_a_data2 //|> o +,sc2mac_dat_a_data3 //|> o +,sc2mac_dat_a_data4 //|> o +,sc2mac_dat_a_data5 //|> o +,sc2mac_dat_a_data6 //|> o +,sc2mac_dat_a_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_a_mask //|> o + ,sc2mac_dat_a_pd //|> o + ,sc2mac_dat_a_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_b_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_b_data0 //|> o +,sc2mac_dat_b_data1 //|> o +,sc2mac_dat_b_data2 //|> o +,sc2mac_dat_b_data3 //|> o +,sc2mac_dat_b_data4 //|> o +,sc2mac_dat_b_data5 //|> o +,sc2mac_dat_b_data6 //|> o +,sc2mac_dat_b_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_b_mask //|> o + ,sc2mac_dat_b_pd //|> o + ,sc2mac_dat_b_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_a_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_a_data0 //|> o +,sc2mac_wt_a_data1 //|> o +,sc2mac_wt_a_data2 //|> o +,sc2mac_wt_a_data3 //|> o +,sc2mac_wt_a_data4 //|> o +,sc2mac_wt_a_data5 //|> o +,sc2mac_wt_a_data6 //|> o +,sc2mac_wt_a_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_a_mask //|> o + ,sc2mac_wt_a_pvld //|> o + ,sc2mac_wt_a_sel //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_b_data${i} //|> o ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_b_data0 //|> o +,sc2mac_wt_b_data1 //|> o +,sc2mac_wt_b_data2 //|> o +,sc2mac_wt_b_data3 //|> o +,sc2mac_wt_b_data4 //|> o +,sc2mac_wt_b_data5 //|> o +,sc2mac_wt_b_data6 //|> o +,sc2mac_wt_b_data7 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_b_mask //|> o + ,sc2mac_wt_b_pvld //|> o + ,sc2mac_wt_b_sel //|> o + ); +// +// NV_NVDLA_partition_c_io.v +// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input accu2sc_credit_vld; /* data valid */ +input [2:0] accu2sc_credit_size; +output cdma2csb_resp_valid; /* data valid */ +output [33:0] cdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] cdma_dat2glb_done_intr_pd; +output cdma_dat2mcif_rd_req_valid; /* data valid */ +input cdma_dat2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] cdma_dat2mcif_rd_req_pd; +output [1:0] cdma_wt2glb_done_intr_pd; +output cdma_wt2mcif_rd_req_valid; /* data valid */ +input cdma_wt2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] cdma_wt2mcif_rd_req_pd; +input csb2cdma_req_pvld; /* data valid */ +output csb2cdma_req_prdy; /* data return handshake */ +input [62:0] csb2cdma_req_pd; +input csb2csc_req_pvld; /* data valid */ +output csb2csc_req_prdy; /* data return handshake */ +input [62:0] csb2csc_req_pd; +output csc2csb_resp_valid; /* data valid */ +output [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input mcif2cdma_dat_rd_rsp_valid; /* data valid */ +output mcif2cdma_dat_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2cdma_dat_rd_rsp_pd; +input mcif2cdma_wt_rd_rsp_valid; /* data valid */ +output mcif2cdma_wt_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2cdma_wt_rd_rsp_pd; +input [31:0] pwrbus_ram_pd; +output sc2mac_dat_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_a_mask; +output [8:0] sc2mac_dat_a_pd; +output sc2mac_dat_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_b_mask; +output [8:0] sc2mac_dat_b_pd; +output sc2mac_wt_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_a_mask; +output [8/2-1:0] sc2mac_wt_a_sel; +output sc2mac_wt_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_b_mask; +//: my $kk=8 -1; +//: foreach my $i (0..${kk}) { +//: print qq( +//: output [8 -1:0] sc2mac_dat_a_data${i}; +//: output [8 -1:0] sc2mac_dat_b_data${i}; +//: output [8 -1:0] sc2mac_wt_a_data${i}; +//: output [8 -1:0] sc2mac_wt_b_data${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [8 -1:0] sc2mac_dat_a_data0; +output [8 -1:0] sc2mac_dat_b_data0; +output [8 -1:0] sc2mac_wt_a_data0; +output [8 -1:0] sc2mac_wt_b_data0; + +output [8 -1:0] sc2mac_dat_a_data1; +output [8 -1:0] sc2mac_dat_b_data1; +output [8 -1:0] sc2mac_wt_a_data1; +output [8 -1:0] sc2mac_wt_b_data1; + +output [8 -1:0] sc2mac_dat_a_data2; +output [8 -1:0] sc2mac_dat_b_data2; +output [8 -1:0] sc2mac_wt_a_data2; +output [8 -1:0] sc2mac_wt_b_data2; + +output [8 -1:0] sc2mac_dat_a_data3; +output [8 -1:0] sc2mac_dat_b_data3; +output [8 -1:0] sc2mac_wt_a_data3; +output [8 -1:0] sc2mac_wt_b_data3; + +output [8 -1:0] sc2mac_dat_a_data4; +output [8 -1:0] sc2mac_dat_b_data4; +output [8 -1:0] sc2mac_wt_a_data4; +output [8 -1:0] sc2mac_wt_b_data4; + +output [8 -1:0] sc2mac_dat_a_data5; +output [8 -1:0] sc2mac_dat_b_data5; +output [8 -1:0] sc2mac_wt_a_data5; +output [8 -1:0] sc2mac_wt_b_data5; + +output [8 -1:0] sc2mac_dat_a_data6; +output [8 -1:0] sc2mac_dat_b_data6; +output [8 -1:0] sc2mac_wt_a_data6; +output [8 -1:0] sc2mac_wt_b_data6; + +output [8 -1:0] sc2mac_dat_a_data7; +output [8 -1:0] sc2mac_dat_b_data7; +output [8 -1:0] sc2mac_wt_a_data7; +output [8 -1:0] sc2mac_wt_b_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8/2-1:0] sc2mac_wt_b_sel; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +////////////////////////////////////////////////////// +wire cdma2buf_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: wire [${k}-1:0] cdma2buf_dat_wr_sel; +//: wire [16:0] cdma2buf_dat_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] cdma2buf_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] cdma2buf_dat_wr_addr${i}; +//: wire [${dmaif}-1:0] cdma2buf_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] cdma2buf_dat_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [16:0] cdma2buf_dat_wr_addr; +wire [64-1:0] cdma2buf_dat_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [11:0] cdma2buf_dat_wr_addr; +//wire [1023:0] cdma2buf_dat_wr_data; +//wire [1:0] cdma2buf_dat_wr_hsel; +wire cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: wire [${k}-1:0] cdma2buf_wt_wr_sel ; +//: wire [16:0] cdma2buf_wt_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] cdma2buf_wt_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] cdma2buf_wt_wr_addr${i}; +//: wire [${dmaif}-1:0] cdma2buf_wt_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] cdma2buf_wt_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [16:0] cdma2buf_wt_wr_addr; +wire [64-1:0] cdma2buf_wt_wr_data; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//wire [11:0] cdma2buf_wt_wr_addr; +//wire [511:0] cdma2buf_wt_wr_data; +//wire cdma2buf_wt_wr_hsel; +wire [15 -1:0] cdma2sc_dat_entries; +wire cdma2sc_dat_pending_ack; +wire [13:0] cdma2sc_dat_slices; +wire cdma2sc_dat_updt; +wire [8:0] cdma2sc_wmb_entries; +wire [15 -1:0] cdma2sc_wt_entries; +wire [13:0] cdma2sc_wt_kernels; +wire cdma2sc_wt_pending_ack; +wire cdma2sc_wt_updt; +wire cdma_dla_clk_ovr_on_sync; +wire cdma_global_clk_ovr_on_sync; +wire csc_dla_clk_ovr_on_sync; +wire csc_global_clk_ovr_on_sync; +wire nvdla_core_rstn; +wire [14 -1:0] sc2buf_dat_rd_addr; +wire [64 -1:0] sc2buf_dat_rd_data; +wire sc2buf_dat_rd_en; +wire sc2buf_dat_rd_valid; +wire [7 -1:0] sc2buf_dat_rd_shift; +wire sc2buf_dat_rd_next1_en; +wire [14 -1:0] sc2buf_dat_rd_next1_addr; +`ifdef CBUF_WEIGHT_COMPRESSED +wire [14 -1:0] sc2buf_wmb_rd_addr; +wire [64 -1:0] sc2buf_wmb_rd_data; +wire sc2buf_wmb_rd_en; +wire sc2buf_wmb_rd_valid; +`endif +wire [14 -1:0] sc2buf_wt_rd_addr; +wire [64 -1:0] sc2buf_wt_rd_data; +wire sc2buf_wt_rd_en; +wire sc2buf_wt_rd_valid; +wire [15 -1:0] sc2cdma_dat_entries; +wire sc2cdma_dat_pending_req; +wire [13:0] sc2cdma_dat_slices; +wire sc2cdma_dat_updt; +wire [8:0] sc2cdma_wmb_entries; +wire [15 -1:0] sc2cdma_wt_entries; +wire [13:0] sc2cdma_wt_kernels; +wire sc2cdma_wt_pending_req; +wire sc2cdma_wt_updt; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Reset Sync // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_c_reset ( + .dla_reset_rstn (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.synced_rstn (nvdla_core_rstn) //|> w + ,.nvdla_clk (nvdla_core_clk) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_csc_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (csc_dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d u_cdma_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (cdma_dla_clk_ovr_on_sync) + ); +//&Instance NV_NVDLA_sync3d u_dla_clk_ovr_on_sync; +//&Connect clk nvdla_core_clk; +//&Connect sync_i nvdla_clk_ovr_on; +//&Connect sync_o dla_clk_ovr_on_sync; +NV_NVDLA_sync3d_s u_global_csc_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (csc_global_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_cdma_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (cdma_global_clk_ovr_on_sync) + ); +//&Instance NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync; +//&Connect clk nvdla_core_clk; +//&Connect prst nvdla_core_rstn; +//&Connect sync_i global_clk_ovr_on; +//&Connect sync_o global_clk_ovr_on_sync; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Convolution DMA // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cdma u_NV_NVDLA_cdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd) + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd ) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd) + ,.cdma2buf_dat_wr_en (cdma2buf_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//: ,.cdma2buf_dat_wr_sel (cdma2buf_dat_wr_sel) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,. cdma2buf_dat_wr_mask (cdma2buf_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_dat_wr_addr${i} (cdma2buf_dat_wr_addr${i} ) +//: ,.cdma2buf_dat_wr_data${i} (cdma2buf_dat_wr_data${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_hsel) +//,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) + ,.cdma2buf_wt_wr_en (cdma2buf_wt_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +//: ,.cdma2buf_wt_wr_sel (cdma2buf_wt_wr_sel) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_mask (cdma2buf_wt_wr_mask) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_wt_wr_addr${i} (cdma2buf_wt_wr_addr${i}) +//: ,.cdma2buf_wt_wr_data${i} (cdma2buf_wt_wr_data${i}) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) + +//| eperl: generated_end (DO NOT EDIT ABOVE) +//,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +//,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_hsel) +//,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) + ,.cdma2sc_dat_entries (cdma2sc_dat_entries) + ,.cdma2sc_dat_slices (cdma2sc_dat_slices) + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) + ,.sc2cdma_dat_entries (sc2cdma_dat_entries) + ,.sc2cdma_dat_slices (sc2cdma_dat_slices) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels) + ,.cdma2sc_wt_entries (cdma2sc_wt_entries) + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries) + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels) + ,.sc2cdma_wt_entries (sc2cdma_wt_entries) + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries) + ,.dla_clk_ovr_on_sync (cdma_dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (cdma_global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Convolution Buffer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cbuf u_NV_NVDLA_cbuf ( +// .nvdla_core_clk (nvdla_core_clk) +// ,.nvdla_core_rstn (nvdla_core_rstn) +// ,.pwrbus_ram_pd (pwrbus_ram_pd) +// ,.cdma2buf_dat_wr_en (cdma2buf_dat_wr_en) +// //: my $dmaif=NVDLA_DMAIF_BW; +// //: my $atmc=NVDLA_MAC_ATOMIC_C_SIZE*NVDLA_BPE; +// //: if($dmaif < $atmc) { +// //: my $k = int(log(int($atmc/$dmaif))/log(2)); +// //: print qq( +// //: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +// //: ,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_sel) +// //: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +// //: ); +// //: } elsif($dmaif > $atmc) { +// //: my $k = int(log(int($dmaif/$atmc))/log(2)); +// //: print qq( +// //: ,. cdma2buf_dat_wr_mask (cdma2buf_dat_wr_mask ) +// //: ); +// //: foreach my $i (0..$k-1) { +// //: print qq( +// //: ,.cdma2buf_dat_wr_addr${i} (cdma2buf_dat_wr_addr${i} ) +// //: ,.cdma2buf_dat_wr_data${i} (cdma2buf_dat_wr_data${i} ) +// //: ); +// //: } +// //: } else { +// //: print qq( +// //: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +// //: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +// //: ); +// //: } +// //,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +// //,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_hsel) +// //,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +// ,.cdma2buf_wt_wr_en (cdma2buf_wt_wr_en) +// //: my $dmaif=NVDLA_DMAIF_BW; +// //: my $atmc=NVDLA_MAC_ATOMIC_C_SIZE*NVDLA_BPE; +// //: if($dmaif < $atmc) { +// //: my $k = int(log(int($atmc/$dmaif))/log(2)); +// //: print qq( +// //: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +// //: ,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_sel) +// //: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +// //: ); +// //: } elsif($dmaif > $atmc) { +// //: my $k = int(log(int($dmaif/$atmc))/log(2)); +// //: print qq( +// //: ,.cdma2buf_wt_wr_mask (cdma2buf_wt_wr_mask) +// //: ); +// //: foreach my $i (0..$k-1) { +// //: print qq( +// //: ,.cdma2buf_wt_wr_addr${i} (cdma2buf_wt_wr_addr${i}) +// //: ,.cdma2buf_wt_wr_data${i} (cdma2buf_wt_wr_data${i}) +// //: ); +// //: } +// //: } else { +// //: print qq( +// //: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +// //: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +// //: ); +// //: } +// //,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +// //,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_hsel) +// //,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +// ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) +// ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr) +// ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) +// ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data) +// ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) +// ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr) +// ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) +// ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data) +// ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) +// ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr) +// ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) +// ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data) + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.cdma2buf_wr_en0 (cdma2buf_dat_wr_en) //|< w + ,.cdma2buf_wr_addr0 (cdma2buf_dat_wr_addr[14 -1:0]) //|< w + ,.cdma2buf_wr_data0 (cdma2buf_dat_wr_data)//DorisL cdma2buf_dat_wr_data_new) //|< w + ,.cdma2buf_wr_en1 (cdma2buf_wt_wr_en) //|< w + ,.cdma2buf_wr_addr1 (cdma2buf_wt_wr_addr[14 -1:0]) //|< w + ,.cdma2buf_wr_data1 (cdma2buf_wt_wr_data) //|< w +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_4 + ,.cdma2buf_wr_sel0 (cdma2buf_dat_wr_sel) //|< w + ,.cdma2buf_wr_sel1 (cdma2buf_wt_wr_sel) //|< w +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_2 + ,.cdma2buf_wr_sel0 (cdma2buf_dat_wr_sel) //|< w + ,.cdma2buf_wr_sel1 (cdma2buf_wt_wr_sel) //|< w +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_1 + ,.cdma2buf_wr_sel0 ({1{1'b1}}) //|< w + ,.cdma2buf_wr_sel1 ({1{1'b1}}) //|< w +`endif + ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) //|< w + ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr[14 -1:0]) //|< w + ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) //|> w + ,.sc2buf_dat_rd_shift (sc2buf_dat_rd_shift) + ,.sc2buf_dat_rd_next1_en (sc2buf_dat_rd_next1_en) + ,.sc2buf_dat_rd_next1_addr (sc2buf_dat_rd_next1_addr) + ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data[64 -1:0]) //|> w + ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) //|< w + ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr[14 -1:0]) //|< w + ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) //|> w + ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data[64 -1:0]) //|> w + `ifdef CBUF_WEIGHT_COMPRESSED + ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) //|< w + ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr[14 -1:0]) //|< w + ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) //|> w + ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data[64 -1:0]) //|> w + `endif + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Convolution Sequence Controller // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_csc u_NV_NVDLA_csc ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|> w + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) //|> w + ,.accu2sc_credit_vld (accu2sc_credit_vld) //|< i + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) //|< i + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) //|< w + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) //|< w + ,.csb2csc_req_pvld (csb2csc_req_pvld) //|< i + ,.csb2csc_req_prdy (csb2csc_req_prdy) //|> o + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) //|< i + ,.csc2csb_resp_valid (csc2csb_resp_valid) //|> o + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) //|> o + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) //|< w + ,.cdma2sc_dat_entries (cdma2sc_dat_entries[15 -1:0]) //|< w + ,.cdma2sc_dat_slices (cdma2sc_dat_slices[13:0]) //|< w + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) //|> w + ,.sc2cdma_dat_entries (sc2cdma_dat_entries[15 -1:0]) //|> w + ,.sc2cdma_dat_slices (sc2cdma_dat_slices[13:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) //|> w + ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr[14 -1:0]) //|> w + ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) //|< w + ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data[64 -1:0]) //|< w + ,.sc2buf_dat_rd_shift (sc2buf_dat_rd_shift[7 -1:0]) + ,.sc2buf_dat_rd_next1_en (sc2buf_dat_rd_next1_en) + ,.sc2buf_dat_rd_next1_addr (sc2buf_dat_rd_next1_addr) + `ifdef CBUF_WEIGHT_COMPRESSED + ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) //|> w + ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr[14 -1:0]) //|> w + ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) //|< w + ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data[64 -1:0]) //|< w + `endif + ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) //|> w + ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr[14 -1:0]) //|> w + ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) //|< w + ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data[64 -1:0]) //|< w + ,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld) //|> o + ,.sc2mac_dat_a_mask (sc2mac_dat_a_mask[8 -1:0]) //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_a_data${i} (sc2mac_dat_a_data${i}[8 -1:0]) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_a_data0 (sc2mac_dat_a_data0[8 -1:0]) //|> o +,.sc2mac_dat_a_data1 (sc2mac_dat_a_data1[8 -1:0]) //|> o +,.sc2mac_dat_a_data2 (sc2mac_dat_a_data2[8 -1:0]) //|> o +,.sc2mac_dat_a_data3 (sc2mac_dat_a_data3[8 -1:0]) //|> o +,.sc2mac_dat_a_data4 (sc2mac_dat_a_data4[8 -1:0]) //|> o +,.sc2mac_dat_a_data5 (sc2mac_dat_a_data5[8 -1:0]) //|> o +,.sc2mac_dat_a_data6 (sc2mac_dat_a_data6[8 -1:0]) //|> o +,.sc2mac_dat_a_data7 (sc2mac_dat_a_data7[8 -1:0]) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_a_pd (sc2mac_dat_a_pd[8:0]) //|> o + ,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld) //|> w + ,.sc2mac_dat_b_mask (sc2mac_dat_b_mask[8 -1:0]) //|> w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_b_data${i} (sc2mac_dat_b_data${i}[8 -1:0]) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_b_data0 (sc2mac_dat_b_data0[8 -1:0]) //|> o +,.sc2mac_dat_b_data1 (sc2mac_dat_b_data1[8 -1:0]) //|> o +,.sc2mac_dat_b_data2 (sc2mac_dat_b_data2[8 -1:0]) //|> o +,.sc2mac_dat_b_data3 (sc2mac_dat_b_data3[8 -1:0]) //|> o +,.sc2mac_dat_b_data4 (sc2mac_dat_b_data4[8 -1:0]) //|> o +,.sc2mac_dat_b_data5 (sc2mac_dat_b_data5[8 -1:0]) //|> o +,.sc2mac_dat_b_data6 (sc2mac_dat_b_data6[8 -1:0]) //|> o +,.sc2mac_dat_b_data7 (sc2mac_dat_b_data7[8 -1:0]) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_b_pd (sc2mac_dat_b_pd[8:0]) //|> w + ,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld) //|> o + ,.sc2mac_wt_a_mask (sc2mac_wt_a_mask[8 -1:0]) //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_a_data${i} (sc2mac_wt_a_data${i}[8 -1:0]) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_a_data0 (sc2mac_wt_a_data0[8 -1:0]) //|> o +,.sc2mac_wt_a_data1 (sc2mac_wt_a_data1[8 -1:0]) //|> o +,.sc2mac_wt_a_data2 (sc2mac_wt_a_data2[8 -1:0]) //|> o +,.sc2mac_wt_a_data3 (sc2mac_wt_a_data3[8 -1:0]) //|> o +,.sc2mac_wt_a_data4 (sc2mac_wt_a_data4[8 -1:0]) //|> o +,.sc2mac_wt_a_data5 (sc2mac_wt_a_data5[8 -1:0]) //|> o +,.sc2mac_wt_a_data6 (sc2mac_wt_a_data6[8 -1:0]) //|> o +,.sc2mac_wt_a_data7 (sc2mac_wt_a_data7[8 -1:0]) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_a_sel (sc2mac_wt_a_sel[8/2 -1:0]) //|> o + ,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld) //|> w + ,.sc2mac_wt_b_mask (sc2mac_wt_b_mask[8 -1:0]) //|> w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_b_data${i} (sc2mac_wt_b_data${i}[8 -1:0]) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_b_data0 (sc2mac_wt_b_data0[8 -1:0]) //|> o +,.sc2mac_wt_b_data1 (sc2mac_wt_b_data1[8 -1:0]) //|> o +,.sc2mac_wt_b_data2 (sc2mac_wt_b_data2[8 -1:0]) //|> o +,.sc2mac_wt_b_data3 (sc2mac_wt_b_data3[8 -1:0]) //|> o +,.sc2mac_wt_b_data4 (sc2mac_wt_b_data4[8 -1:0]) //|> o +,.sc2mac_wt_b_data5 (sc2mac_wt_b_data5[8 -1:0]) //|> o +,.sc2mac_wt_b_data6 (sc2mac_wt_b_data6[8 -1:0]) //|> o +,.sc2mac_wt_b_data7 (sc2mac_wt_b_data7[8 -1:0]) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_b_sel (sc2mac_wt_b_sel[8/2 -1:0]) //|> w + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels) + ,.cdma2sc_wt_entries (cdma2sc_wt_entries) + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries) + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels) + ,.sc2cdma_wt_entries (sc2cdma_wt_entries) + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries) + ,.dla_clk_ovr_on_sync (csc_dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (csc_global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_partition_c diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_c.v.vcp b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_c.v.vcp new file mode 100644 index 0000000..d47c718 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_c.v.vcp @@ -0,0 +1,636 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_c.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CBUF.h + `define CBUF_BANK_RAM_CASE2 +//ram case could be 0/1/2/3/4 0:1ram/bank; 1:1*2ram/bank; 2:2*1ram/bank; 3:2*2ram/bank 4:4*1ram/bank +`define CDMA2CBUF_DEBUG_PRINT //open debug print +module NV_NVDLA_partition_c ( + accu2sc_credit_size //|< i + ,accu2sc_credit_vld //|< i + ,cdma_dat2mcif_rd_req_ready //|< i + ,cdma_wt2mcif_rd_req_ready //|< i + ,csb2cdma_req_pd //|< i + ,csb2cdma_req_pvld //|< i + ,csb2csc_req_pd //|< i + ,csb2csc_req_pvld //|< i + ,direct_reset_ //|< i + ,dla_reset_rstn //|< i + ,global_clk_ovr_on //|< i + ,mcif2cdma_dat_rd_rsp_pd //|< i + ,mcif2cdma_dat_rd_rsp_valid //|< i + ,mcif2cdma_wt_rd_rsp_pd //|< i + ,mcif2cdma_wt_rd_rsp_valid //|< i + ,nvdla_clk_ovr_on //|< i + ,nvdla_core_clk //|< i + ,pwrbus_ram_pd //|< i + ,test_mode //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cdma2csb_resp_pd //|> o + ,cdma2csb_resp_valid //|> o + ,cdma_dat2glb_done_intr_pd //|> o + ,cdma_dat2mcif_rd_req_pd //|> o + ,cdma_dat2mcif_rd_req_valid //|> o + ,cdma_wt2glb_done_intr_pd //|> o + ,cdma_wt2mcif_rd_req_pd //|> o + ,cdma_wt2mcif_rd_req_valid //|> o + ,csb2cdma_req_prdy //|> o + ,csb2csc_req_prdy //|> o + ,csc2csb_resp_pd //|> o + ,csc2csb_resp_valid //|> o + ,mcif2cdma_dat_rd_rsp_ready //|> o + ,mcif2cdma_wt_rd_rsp_ready //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_a_data${i} //|> o ); +//: } + ,sc2mac_dat_a_mask //|> o + ,sc2mac_dat_a_pd //|> o + ,sc2mac_dat_a_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_b_data${i} //|> o ); +//: } + ,sc2mac_dat_b_mask //|> o + ,sc2mac_dat_b_pd //|> o + ,sc2mac_dat_b_pvld //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_a_data${i} //|> o ); +//: } + ,sc2mac_wt_a_mask //|> o + ,sc2mac_wt_a_pvld //|> o + ,sc2mac_wt_a_sel //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_b_data${i} //|> o ); +//: } + ,sc2mac_wt_b_mask //|> o + ,sc2mac_wt_b_pvld //|> o + ,sc2mac_wt_b_sel //|> o + ); +// +// NV_NVDLA_partition_c_io.v +// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input accu2sc_credit_vld; /* data valid */ +input [2:0] accu2sc_credit_size; +output cdma2csb_resp_valid; /* data valid */ +output [33:0] cdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] cdma_dat2glb_done_intr_pd; +output cdma_dat2mcif_rd_req_valid; /* data valid */ +input cdma_dat2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] cdma_dat2mcif_rd_req_pd; +output [1:0] cdma_wt2glb_done_intr_pd; +output cdma_wt2mcif_rd_req_valid; /* data valid */ +input cdma_wt2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] cdma_wt2mcif_rd_req_pd; +input csb2cdma_req_pvld; /* data valid */ +output csb2cdma_req_prdy; /* data return handshake */ +input [62:0] csb2cdma_req_pd; +input csb2csc_req_pvld; /* data valid */ +output csb2csc_req_prdy; /* data return handshake */ +input [62:0] csb2csc_req_pd; +output csc2csb_resp_valid; /* data valid */ +output [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input mcif2cdma_dat_rd_rsp_valid; /* data valid */ +output mcif2cdma_dat_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2cdma_dat_rd_rsp_pd; +input mcif2cdma_wt_rd_rsp_valid; /* data valid */ +output mcif2cdma_wt_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2cdma_wt_rd_rsp_pd; +input [31:0] pwrbus_ram_pd; +output sc2mac_dat_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_a_mask; +output [8:0] sc2mac_dat_a_pd; +output sc2mac_dat_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_dat_b_mask; +output [8:0] sc2mac_dat_b_pd; +output sc2mac_wt_a_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_a_mask; +output [8/2-1:0] sc2mac_wt_a_sel; +output sc2mac_wt_b_pvld; /* data valid */ +output [8 -1:0] sc2mac_wt_b_mask; +//: my $kk=8 -1; +//: foreach my $i (0..${kk}) { +//: print qq( +//: output [8 -1:0] sc2mac_dat_a_data${i}; +//: output [8 -1:0] sc2mac_dat_b_data${i}; +//: output [8 -1:0] sc2mac_wt_a_data${i}; +//: output [8 -1:0] sc2mac_wt_b_data${i}; +//: ); +//: } +output [8/2-1:0] sc2mac_wt_b_sel; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +////////////////////////////////////////////////////// +wire cdma2buf_dat_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: wire [${k}-1:0] cdma2buf_dat_wr_sel; +//: wire [16:0] cdma2buf_dat_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] cdma2buf_dat_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] cdma2buf_dat_wr_addr${i}; +//: wire [${dmaif}-1:0] cdma2buf_dat_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] cdma2buf_dat_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_dat_wr_data; +//: ); +//: } +//wire [11:0] cdma2buf_dat_wr_addr; +//wire [1023:0] cdma2buf_dat_wr_data; +//wire [1:0] cdma2buf_dat_wr_hsel; +wire cdma2buf_wt_wr_en; +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int($atmc/$dmaif); +//: print qq( +//: wire [${k}-1:0] cdma2buf_wt_wr_sel ; +//: wire [16:0] cdma2buf_wt_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: wire [${k}-1:0] cdma2buf_wt_wr_mask; +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: wire [16:0] cdma2buf_wt_wr_addr${i}; +//: wire [${dmaif}-1:0] cdma2buf_wt_wr_data${i}; +//: ); +//: } +//: } else { +//: print qq( +//: wire [16:0] cdma2buf_wt_wr_addr; +//: wire [${dmaif}-1:0] cdma2buf_wt_wr_data; +//: ); +//: } +//wire [11:0] cdma2buf_wt_wr_addr; +//wire [511:0] cdma2buf_wt_wr_data; +//wire cdma2buf_wt_wr_hsel; +wire [15 -1:0] cdma2sc_dat_entries; +wire cdma2sc_dat_pending_ack; +wire [13:0] cdma2sc_dat_slices; +wire cdma2sc_dat_updt; +wire [8:0] cdma2sc_wmb_entries; +wire [15 -1:0] cdma2sc_wt_entries; +wire [13:0] cdma2sc_wt_kernels; +wire cdma2sc_wt_pending_ack; +wire cdma2sc_wt_updt; +wire cdma_dla_clk_ovr_on_sync; +wire cdma_global_clk_ovr_on_sync; +wire csc_dla_clk_ovr_on_sync; +wire csc_global_clk_ovr_on_sync; +wire nvdla_core_rstn; +wire [14 -1:0] sc2buf_dat_rd_addr; +wire [64 -1:0] sc2buf_dat_rd_data; +wire sc2buf_dat_rd_en; +wire sc2buf_dat_rd_valid; +wire [7 -1:0] sc2buf_dat_rd_shift; +wire sc2buf_dat_rd_next1_en; +wire [14 -1:0] sc2buf_dat_rd_next1_addr; +`ifdef CBUF_WEIGHT_COMPRESSED +wire [14 -1:0] sc2buf_wmb_rd_addr; +wire [64 -1:0] sc2buf_wmb_rd_data; +wire sc2buf_wmb_rd_en; +wire sc2buf_wmb_rd_valid; +`endif +wire [14 -1:0] sc2buf_wt_rd_addr; +wire [64 -1:0] sc2buf_wt_rd_data; +wire sc2buf_wt_rd_en; +wire sc2buf_wt_rd_valid; +wire [15 -1:0] sc2cdma_dat_entries; +wire sc2cdma_dat_pending_req; +wire [13:0] sc2cdma_dat_slices; +wire sc2cdma_dat_updt; +wire [8:0] sc2cdma_wmb_entries; +wire [15 -1:0] sc2cdma_wt_entries; +wire [13:0] sc2cdma_wt_kernels; +wire sc2cdma_wt_pending_req; +wire sc2cdma_wt_updt; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Reset Sync // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_c_reset ( + .dla_reset_rstn (dla_reset_rstn) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ,.test_mode (test_mode) //|< i + ,.synced_rstn (nvdla_core_rstn) //|> w + ,.nvdla_clk (nvdla_core_clk) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_csc_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (csc_dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d u_cdma_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (cdma_dla_clk_ovr_on_sync) + ); +//&Instance NV_NVDLA_sync3d u_dla_clk_ovr_on_sync; +//&Connect clk nvdla_core_clk; +//&Connect sync_i nvdla_clk_ovr_on; +//&Connect sync_o dla_clk_ovr_on_sync; +NV_NVDLA_sync3d_s u_global_csc_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (csc_global_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_cdma_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (cdma_global_clk_ovr_on_sync) + ); +//&Instance NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync; +//&Connect clk nvdla_core_clk; +//&Connect prst nvdla_core_rstn; +//&Connect sync_i global_clk_ovr_on; +//&Connect sync_o global_clk_ovr_on_sync; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Convolution DMA // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cdma u_NV_NVDLA_cdma ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd) + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd ) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd) + ,.cdma2buf_dat_wr_en (cdma2buf_dat_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//: ,.cdma2buf_dat_wr_sel (cdma2buf_dat_wr_sel) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,. cdma2buf_dat_wr_mask (cdma2buf_dat_wr_mask ) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_dat_wr_addr${i} (cdma2buf_dat_wr_addr${i} ) +//: ,.cdma2buf_dat_wr_data${i} (cdma2buf_dat_wr_data${i} ) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +//: ); +//: } +//,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +//,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_hsel) +//,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) + ,.cdma2buf_wt_wr_en (cdma2buf_wt_wr_en) +//: my $dmaif=64; +//: my $atmc=8*8; +//: if($dmaif < $atmc) { +//: my $k = int(log(int($atmc/$dmaif))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +//: ,.cdma2buf_wt_wr_sel (cdma2buf_wt_wr_sel) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +//: ); +//: } elsif($dmaif > $atmc) { +//: my $k = int(log(int($dmaif/$atmc))/log(2)); +//: print qq( +//: ,.cdma2buf_wt_wr_mask (cdma2buf_wt_wr_mask) +//: ); +//: foreach my $i (0..$k-1) { +//: print qq( +//: ,.cdma2buf_wt_wr_addr${i} (cdma2buf_wt_wr_addr${i}) +//: ,.cdma2buf_wt_wr_data${i} (cdma2buf_wt_wr_data${i}) +//: ); +//: } +//: } else { +//: print qq( +//: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +//: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +//: ); +//: } +//,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +//,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_hsel) +//,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) + ,.cdma2sc_dat_entries (cdma2sc_dat_entries) + ,.cdma2sc_dat_slices (cdma2sc_dat_slices) + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) + ,.sc2cdma_dat_entries (sc2cdma_dat_entries) + ,.sc2cdma_dat_slices (sc2cdma_dat_slices) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels) + ,.cdma2sc_wt_entries (cdma2sc_wt_entries) + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries) + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels) + ,.sc2cdma_wt_entries (sc2cdma_wt_entries) + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries) + ,.dla_clk_ovr_on_sync (cdma_dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (cdma_global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Convolution Buffer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cbuf u_NV_NVDLA_cbuf ( +// .nvdla_core_clk (nvdla_core_clk) +// ,.nvdla_core_rstn (nvdla_core_rstn) +// ,.pwrbus_ram_pd (pwrbus_ram_pd) +// ,.cdma2buf_dat_wr_en (cdma2buf_dat_wr_en) +// //: my $dmaif=NVDLA_DMAIF_BW; +// //: my $atmc=NVDLA_MAC_ATOMIC_C_SIZE*NVDLA_BPE; +// //: if($dmaif < $atmc) { +// //: my $k = int(log(int($atmc/$dmaif))/log(2)); +// //: print qq( +// //: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +// //: ,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_sel) +// //: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +// //: ); +// //: } elsif($dmaif > $atmc) { +// //: my $k = int(log(int($dmaif/$atmc))/log(2)); +// //: print qq( +// //: ,. cdma2buf_dat_wr_mask (cdma2buf_dat_wr_mask ) +// //: ); +// //: foreach my $i (0..$k-1) { +// //: print qq( +// //: ,.cdma2buf_dat_wr_addr${i} (cdma2buf_dat_wr_addr${i} ) +// //: ,.cdma2buf_dat_wr_data${i} (cdma2buf_dat_wr_data${i} ) +// //: ); +// //: } +// //: } else { +// //: print qq( +// //: ,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +// //: ,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +// //: ); +// //: } +// //,.cdma2buf_dat_wr_addr (cdma2buf_dat_wr_addr) +// //,.cdma2buf_dat_wr_hsel (cdma2buf_dat_wr_hsel) +// //,.cdma2buf_dat_wr_data (cdma2buf_dat_wr_data) +// ,.cdma2buf_wt_wr_en (cdma2buf_wt_wr_en) +// //: my $dmaif=NVDLA_DMAIF_BW; +// //: my $atmc=NVDLA_MAC_ATOMIC_C_SIZE*NVDLA_BPE; +// //: if($dmaif < $atmc) { +// //: my $k = int(log(int($atmc/$dmaif))/log(2)); +// //: print qq( +// //: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +// //: ,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_sel) +// //: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +// //: ); +// //: } elsif($dmaif > $atmc) { +// //: my $k = int(log(int($dmaif/$atmc))/log(2)); +// //: print qq( +// //: ,.cdma2buf_wt_wr_mask (cdma2buf_wt_wr_mask) +// //: ); +// //: foreach my $i (0..$k-1) { +// //: print qq( +// //: ,.cdma2buf_wt_wr_addr${i} (cdma2buf_wt_wr_addr${i}) +// //: ,.cdma2buf_wt_wr_data${i} (cdma2buf_wt_wr_data${i}) +// //: ); +// //: } +// //: } else { +// //: print qq( +// //: ,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +// //: ,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +// //: ); +// //: } +// //,.cdma2buf_wt_wr_addr (cdma2buf_wt_wr_addr) +// //,.cdma2buf_wt_wr_hsel (cdma2buf_wt_wr_hsel) +// //,.cdma2buf_wt_wr_data (cdma2buf_wt_wr_data) +// ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) +// ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr) +// ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) +// ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data) +// ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) +// ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr) +// ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) +// ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data) +// ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) +// ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr) +// ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) +// ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data) + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.cdma2buf_wr_en0 (cdma2buf_dat_wr_en) //|< w + ,.cdma2buf_wr_addr0 (cdma2buf_dat_wr_addr[14 -1:0]) //|< w + ,.cdma2buf_wr_data0 (cdma2buf_dat_wr_data)//DorisL cdma2buf_dat_wr_data_new) //|< w + ,.cdma2buf_wr_en1 (cdma2buf_wt_wr_en) //|< w + ,.cdma2buf_wr_addr1 (cdma2buf_wt_wr_addr[14 -1:0]) //|< w + ,.cdma2buf_wr_data1 (cdma2buf_wt_wr_data) //|< w +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_4 + ,.cdma2buf_wr_sel0 (cdma2buf_dat_wr_sel) //|< w + ,.cdma2buf_wr_sel1 (cdma2buf_wt_wr_sel) //|< w +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_2 + ,.cdma2buf_wr_sel0 (cdma2buf_dat_wr_sel) //|< w + ,.cdma2buf_wr_sel1 (cdma2buf_wt_wr_sel) //|< w +`endif +`ifdef CC_ATOMC_DIV_ATOMK_EQUAL_1 + ,.cdma2buf_wr_sel0 ({1{1'b1}}) //|< w + ,.cdma2buf_wr_sel1 ({1{1'b1}}) //|< w +`endif + ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) //|< w + ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr[14 -1:0]) //|< w + ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) //|> w + ,.sc2buf_dat_rd_shift (sc2buf_dat_rd_shift) + ,.sc2buf_dat_rd_next1_en (sc2buf_dat_rd_next1_en) + ,.sc2buf_dat_rd_next1_addr (sc2buf_dat_rd_next1_addr) + ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data[64 -1:0]) //|> w + ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) //|< w + ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr[14 -1:0]) //|< w + ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) //|> w + ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data[64 -1:0]) //|> w + `ifdef CBUF_WEIGHT_COMPRESSED + ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) //|< w + ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr[14 -1:0]) //|< w + ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) //|> w + ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data[64 -1:0]) //|> w + `endif + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C: Convolution Sequence Controller // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_csc u_NV_NVDLA_csc ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< w + ,.sc2cdma_dat_pending_req (sc2cdma_dat_pending_req) //|> w + ,.sc2cdma_wt_pending_req (sc2cdma_wt_pending_req) //|> w + ,.accu2sc_credit_vld (accu2sc_credit_vld) //|< i + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) //|< i + ,.cdma2sc_dat_pending_ack (cdma2sc_dat_pending_ack) //|< w + ,.cdma2sc_wt_pending_ack (cdma2sc_wt_pending_ack) //|< w + ,.csb2csc_req_pvld (csb2csc_req_pvld) //|< i + ,.csb2csc_req_prdy (csb2csc_req_prdy) //|> o + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) //|< i + ,.csc2csb_resp_valid (csc2csb_resp_valid) //|> o + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) //|> o + ,.cdma2sc_dat_updt (cdma2sc_dat_updt) //|< w + ,.cdma2sc_dat_entries (cdma2sc_dat_entries[15 -1:0]) //|< w + ,.cdma2sc_dat_slices (cdma2sc_dat_slices[13:0]) //|< w + ,.sc2cdma_dat_updt (sc2cdma_dat_updt) //|> w + ,.sc2cdma_dat_entries (sc2cdma_dat_entries[15 -1:0]) //|> w + ,.sc2cdma_dat_slices (sc2cdma_dat_slices[13:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.sc2buf_dat_rd_en (sc2buf_dat_rd_en) //|> w + ,.sc2buf_dat_rd_addr (sc2buf_dat_rd_addr[14 -1:0]) //|> w + ,.sc2buf_dat_rd_valid (sc2buf_dat_rd_valid) //|< w + ,.sc2buf_dat_rd_data (sc2buf_dat_rd_data[64 -1:0]) //|< w + ,.sc2buf_dat_rd_shift (sc2buf_dat_rd_shift[7 -1:0]) + ,.sc2buf_dat_rd_next1_en (sc2buf_dat_rd_next1_en) + ,.sc2buf_dat_rd_next1_addr (sc2buf_dat_rd_next1_addr) + `ifdef CBUF_WEIGHT_COMPRESSED + ,.sc2buf_wmb_rd_en (sc2buf_wmb_rd_en) //|> w + ,.sc2buf_wmb_rd_addr (sc2buf_wmb_rd_addr[14 -1:0]) //|> w + ,.sc2buf_wmb_rd_valid (sc2buf_wmb_rd_valid) //|< w + ,.sc2buf_wmb_rd_data (sc2buf_wmb_rd_data[64 -1:0]) //|< w + `endif + ,.sc2buf_wt_rd_en (sc2buf_wt_rd_en) //|> w + ,.sc2buf_wt_rd_addr (sc2buf_wt_rd_addr[14 -1:0]) //|> w + ,.sc2buf_wt_rd_valid (sc2buf_wt_rd_valid) //|< w + ,.sc2buf_wt_rd_data (sc2buf_wt_rd_data[64 -1:0]) //|< w + ,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld) //|> o + ,.sc2mac_dat_a_mask (sc2mac_dat_a_mask[8 -1:0]) //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_a_data${i} (sc2mac_dat_a_data${i}[8 -1:0]) //|> o ) +//: } + ,.sc2mac_dat_a_pd (sc2mac_dat_a_pd[8:0]) //|> o + ,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld) //|> w + ,.sc2mac_dat_b_mask (sc2mac_dat_b_mask[8 -1:0]) //|> w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_b_data${i} (sc2mac_dat_b_data${i}[8 -1:0]) //|> o ) +//: } + ,.sc2mac_dat_b_pd (sc2mac_dat_b_pd[8:0]) //|> w + ,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld) //|> o + ,.sc2mac_wt_a_mask (sc2mac_wt_a_mask[8 -1:0]) //|> o +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_a_data${i} (sc2mac_wt_a_data${i}[8 -1:0]) //|> o ) +//: } + ,.sc2mac_wt_a_sel (sc2mac_wt_a_sel[8/2 -1:0]) //|> o + ,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld) //|> w + ,.sc2mac_wt_b_mask (sc2mac_wt_b_mask[8 -1:0]) //|> w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_b_data${i} (sc2mac_wt_b_data${i}[8 -1:0]) //|> o ) +//: } + ,.sc2mac_wt_b_sel (sc2mac_wt_b_sel[8/2 -1:0]) //|> w + ,.cdma2sc_wt_updt (cdma2sc_wt_updt) + ,.cdma2sc_wt_kernels (cdma2sc_wt_kernels) + ,.cdma2sc_wt_entries (cdma2sc_wt_entries) + ,.cdma2sc_wmb_entries (cdma2sc_wmb_entries) + ,.sc2cdma_wt_updt (sc2cdma_wt_updt) + ,.sc2cdma_wt_kernels (sc2cdma_wt_kernels) + ,.sc2cdma_wt_entries (sc2cdma_wt_entries) + ,.sc2cdma_wmb_entries (sc2cdma_wmb_entries) + ,.dla_clk_ovr_on_sync (csc_dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (csc_global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_partition_c diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_m.v b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_m.v new file mode 100644 index 0000000..4b702e1 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_m.v @@ -0,0 +1,242 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_m.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_partition_m ( + csb2cmac_a_req_pd //|< i + ,csb2cmac_a_req_pvld //|< i + ,direct_reset_ //|< i + ,dla_reset_rstn //|< i + ,global_clk_ovr_on //|< i + ,nvdla_clk_ovr_on //|< i + ,nvdla_core_clk //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_dat_data0 //|< i +,sc2mac_dat_data1 //|< i +,sc2mac_dat_data2 //|< i +,sc2mac_dat_data3 //|< i +,sc2mac_dat_data4 //|< i +,sc2mac_dat_data5 //|< i +,sc2mac_dat_data6 //|< i +,sc2mac_dat_data7 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_dat_mask //|< i + ,sc2mac_dat_pd //|< i + ,sc2mac_dat_pvld //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i} //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,sc2mac_wt_data0 //|< i +,sc2mac_wt_data1 //|< i +,sc2mac_wt_data2 //|< i +,sc2mac_wt_data3 //|< i +,sc2mac_wt_data4 //|< i +,sc2mac_wt_data5 //|< i +,sc2mac_wt_data6 //|< i +,sc2mac_wt_data7 //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,sc2mac_wt_mask //|< i + ,sc2mac_wt_pvld //|< i + ,sc2mac_wt_sel //|< i + ,test_mode //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cmac_a2csb_resp_pd //|> o + ,cmac_a2csb_resp_valid //|> o + ,csb2cmac_a_req_prdy //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac2accu_data${i} //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,mac2accu_data0 //|> o +,mac2accu_data1 //|> o +,mac2accu_data2 //|> o +,mac2accu_data3 //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,mac2accu_mask //|> o + ,mac2accu_mode //|> o + ,mac2accu_pd //|> o + ,mac2accu_pvld //|> o + ); +// +// NV_NVDLA_partition_m_io.v +// +input test_mode; +input direct_reset_; +input csb2cmac_a_req_pvld; +output csb2cmac_a_req_prdy; +input [62:0] csb2cmac_a_req_pd; +output cmac_a2csb_resp_valid; +output [33:0] cmac_a2csb_resp_pd; +input sc2mac_wt_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i}; //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_wt_data0; //|< i +input [8 -1:0] sc2mac_wt_data1; //|< i +input [8 -1:0] sc2mac_wt_data2; //|< i +input [8 -1:0] sc2mac_wt_data3; //|< i +input [8 -1:0] sc2mac_wt_data4; //|< i +input [8 -1:0] sc2mac_wt_data5; //|< i +input [8 -1:0] sc2mac_wt_data6; //|< i +input [8 -1:0] sc2mac_wt_data7; //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8/2 -1:0] sc2mac_wt_sel; +input sc2mac_dat_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i}; //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +input [8 -1:0] sc2mac_dat_data0; //|< i +input [8 -1:0] sc2mac_dat_data1; //|< i +input [8 -1:0] sc2mac_dat_data2; //|< i +input [8 -1:0] sc2mac_dat_data3; //|< i +input [8 -1:0] sc2mac_dat_data4; //|< i +input [8 -1:0] sc2mac_dat_data5; //|< i +input [8 -1:0] sc2mac_dat_data6; //|< i +input [8 -1:0] sc2mac_dat_data7; //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) +input [8:0] sc2mac_dat_pd; +output mac2accu_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_mask; +output mac2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_data${i}; ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +output [19 -1:0] mac2accu_data0; +output [19 -1:0] mac2accu_data1; +output [19 -1:0] mac2accu_data2; +output [19 -1:0] mac2accu_data3; +//| eperl: generated_end (DO NOT EDIT ABOVE) +output [8:0] mac2accu_pd; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +wire dla_clk_ovr_on_sync; +wire global_clk_ovr_on_sync; +wire nvdla_core_rstn; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition M: Reset Syncer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_m_reset ( + .dla_reset_rstn (dla_reset_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_core_rstn) + ,.nvdla_clk (nvdla_core_clk) + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (global_clk_ovr_on_sync) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition M: Convolution MAC Array // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cmac u_NV_NVDLA_cmac ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< w + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> o + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> o + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< i + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> o + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< i + ,.mac2accu_pvld (mac2accu_pvld) //|> o + ,.mac2accu_mask (mac2accu_mask) //|> o + ,.mac2accu_mode (mac2accu_mode) //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac2accu_data0 (mac2accu_data0) //|> o +,.mac2accu_data1 (mac2accu_data1) //|> o +,.mac2accu_data2 (mac2accu_data2) //|> o +,.mac2accu_data3 (mac2accu_data3) //|> o +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac2accu_pd (mac2accu_pd) //|> o + ,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i + ,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_data0 (sc2mac_dat_data0) //|< i +,.sc2mac_dat_data1 (sc2mac_dat_data1) //|< i +,.sc2mac_dat_data2 (sc2mac_dat_data2) //|< i +,.sc2mac_dat_data3 (sc2mac_dat_data3) //|< i +,.sc2mac_dat_data4 (sc2mac_dat_data4) //|< i +,.sc2mac_dat_data5 (sc2mac_dat_data5) //|< i +,.sc2mac_dat_data6 (sc2mac_dat_data6) //|< i +,.sc2mac_dat_data7 (sc2mac_dat_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i + ,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i + ,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_data0 (sc2mac_wt_data0) //|< i +,.sc2mac_wt_data1 (sc2mac_wt_data1) //|< i +,.sc2mac_wt_data2 (sc2mac_wt_data2) //|< i +,.sc2mac_wt_data3 (sc2mac_wt_data3) //|< i +,.sc2mac_wt_data4 (sc2mac_wt_data4) //|< i +,.sc2mac_wt_data5 (sc2mac_wt_data5) //|< i +,.sc2mac_wt_data6 (sc2mac_wt_data6) //|< i +,.sc2mac_wt_data7 (sc2mac_wt_data7) //|< i +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ); +endmodule // NV_NVDLA_partition_m diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_m.v.vcp b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_m.v.vcp new file mode 100644 index 0000000..f865245 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_m.v.vcp @@ -0,0 +1,155 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_m.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +module NV_NVDLA_partition_m ( + csb2cmac_a_req_pd //|< i + ,csb2cmac_a_req_pvld //|< i + ,direct_reset_ //|< i + ,dla_reset_rstn //|< i + ,global_clk_ovr_on //|< i + ,nvdla_clk_ovr_on //|< i + ,nvdla_core_clk //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_dat_data${i} //|< i ) +//: } + ,sc2mac_dat_mask //|< i + ,sc2mac_dat_pd //|< i + ,sc2mac_dat_pvld //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,sc2mac_wt_data${i} //|< i ) +//: } + ,sc2mac_wt_mask //|< i + ,sc2mac_wt_pvld //|< i + ,sc2mac_wt_sel //|< i + ,test_mode //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cmac_a2csb_resp_pd //|> o + ,cmac_a2csb_resp_valid //|> o + ,csb2cmac_a_req_prdy //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,mac2accu_data${i} //|> o ) +//: } + ,mac2accu_mask //|> o + ,mac2accu_mode //|> o + ,mac2accu_pd //|> o + ,mac2accu_pvld //|> o + ); +// +// NV_NVDLA_partition_m_io.v +// +input test_mode; +input direct_reset_; +input csb2cmac_a_req_pvld; +output csb2cmac_a_req_prdy; +input [62:0] csb2cmac_a_req_pd; +output cmac_a2csb_resp_valid; +output [33:0] cmac_a2csb_resp_pd; +input sc2mac_wt_pvld; /* data valid */ +input [8 -1:0] sc2mac_wt_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_wt_data${i}; //|< i ) +//: } +input [8/2 -1:0] sc2mac_wt_sel; +input sc2mac_dat_pvld; /* data valid */ +input [8 -1:0] sc2mac_dat_mask; +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: input [8 -1:0] sc2mac_dat_data${i}; //|< i ) +//: } +input [8:0] sc2mac_dat_pd; +output mac2accu_pvld; /* data valid */ +output [8/2 -1:0] mac2accu_mask; +output mac2accu_mode; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: output [19 -1:0] mac2accu_data${i}; ) +//: } +output [8:0] mac2accu_pd; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +wire dla_clk_ovr_on_sync; +wire global_clk_ovr_on_sync; +wire nvdla_core_rstn; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition M: Reset Syncer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_m_reset ( + .dla_reset_rstn (dla_reset_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_core_rstn) + ,.nvdla_clk (nvdla_core_clk) + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (global_clk_ovr_on_sync) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition M: Convolution MAC Array // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cmac u_NV_NVDLA_cmac ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< w + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> o + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> o + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< i + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> o + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< i + ,.mac2accu_pvld (mac2accu_pvld) //|> o + ,.mac2accu_mask (mac2accu_mask) //|> o + ,.mac2accu_mode (mac2accu_mode) //|> o +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac2accu_data${i}) //|> o ) +//: } + ,.mac2accu_pd (mac2accu_pd) //|> o + ,.sc2mac_dat_pvld (sc2mac_dat_pvld) //|< i + ,.sc2mac_dat_mask (sc2mac_dat_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_data${i}) //|< i ) +//: } + ,.sc2mac_dat_pd (sc2mac_dat_pd) //|< i + ,.sc2mac_wt_pvld (sc2mac_wt_pvld) //|< i + ,.sc2mac_wt_mask (sc2mac_wt_mask) //|< i +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_data${i}) //|< i ) +//: } + ,.sc2mac_wt_sel (sc2mac_wt_sel) //|< i + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ); +endmodule // NV_NVDLA_partition_m diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_o.v b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_o.v new file mode 100644 index 0000000..6e8409d --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_o.v @@ -0,0 +1,867 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_o.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_partition_o ( + test_mode + ,direct_reset_ + ,global_clk_ovr_on + ,tmc2slcg_disable_clock_gating + ,cdma2csb_resp_valid + ,cdma2csb_resp_pd + ,cdma_dat2glb_done_intr_pd + ,cdma_dat2mcif_rd_req_valid + ,cdma_dat2mcif_rd_req_ready + ,cdma_dat2mcif_rd_req_pd + ,cdma_wt2glb_done_intr_pd + ,cdma_wt2mcif_rd_req_valid + ,cdma_wt2mcif_rd_req_ready + ,cdma_wt2mcif_rd_req_pd + ,cmac_a2csb_resp_valid + ,cmac_a2csb_resp_pd + ,csb2cmac_a_req_pvld + ,csb2cmac_a_req_prdy + ,csb2cmac_a_req_pd + ,cmac_b2csb_resp_valid + ,cmac_b2csb_resp_pd + ,csb2cmac_b_req_pvld + ,csb2cmac_b_req_prdy + ,csb2cmac_b_req_pd + ,cacc2csb_resp_valid + ,cacc2csb_resp_pd + ,cacc2glb_done_intr_pd + ,csb2cacc_req_pvld + ,csb2cacc_req_prdy + ,csb2cacc_req_pd + ,csb2cdma_req_pvld + ,csb2cdma_req_prdy + ,csb2cdma_req_pd + ,csb2csc_req_pvld + ,csb2csc_req_prdy + ,csb2csc_req_pd + ,csb2nvdla_valid + ,csb2nvdla_ready + ,csb2nvdla_addr + ,csb2nvdla_wdat + ,csb2nvdla_write + ,csb2nvdla_nposted + ,csb2sdp_rdma_req_pvld + ,csb2sdp_rdma_req_prdy + ,csb2sdp_rdma_req_pd + ,csb2sdp_req_pvld + ,csb2sdp_req_prdy + ,csb2sdp_req_pd + ,csc2csb_resp_valid + ,csc2csb_resp_pd + ,mcif2cdma_dat_rd_rsp_valid + ,mcif2cdma_dat_rd_rsp_ready + ,mcif2cdma_dat_rd_rsp_pd + ,mcif2cdma_wt_rd_rsp_valid + ,mcif2cdma_wt_rd_rsp_ready + ,mcif2cdma_wt_rd_rsp_pd + ,mcif2noc_axi_ar_arvalid + ,mcif2noc_axi_ar_arready + ,mcif2noc_axi_ar_arid + ,mcif2noc_axi_ar_arlen + ,mcif2noc_axi_ar_araddr + ,mcif2noc_axi_aw_awvalid + ,mcif2noc_axi_aw_awready + ,mcif2noc_axi_aw_awid + ,mcif2noc_axi_aw_awlen + ,mcif2noc_axi_aw_awaddr + ,mcif2noc_axi_w_wvalid + ,mcif2noc_axi_w_wready + ,mcif2noc_axi_w_wdata + ,mcif2noc_axi_w_wstrb + ,mcif2noc_axi_w_wlast + ,mcif2sdp_b_rd_rsp_valid + ,mcif2sdp_b_rd_rsp_ready + ,mcif2sdp_b_rd_rsp_pd + ,sdp_b2mcif_rd_cdt_lat_fifo_pop + ,sdp_b2mcif_rd_req_valid + ,sdp_b2mcif_rd_req_ready + ,sdp_b2mcif_rd_req_pd + ,mcif2sdp_n_rd_rsp_valid + ,mcif2sdp_n_rd_rsp_ready + ,mcif2sdp_n_rd_rsp_pd + ,sdp_n2mcif_rd_cdt_lat_fifo_pop + ,sdp_n2mcif_rd_req_valid + ,sdp_n2mcif_rd_req_ready + ,sdp_n2mcif_rd_req_pd + ,mcif2sdp_rd_rsp_valid + ,mcif2sdp_rd_rsp_ready + ,mcif2sdp_rd_rsp_pd + ,mcif2sdp_wr_rsp_complete + ,noc2mcif_axi_b_bvalid + ,noc2mcif_axi_b_bready + ,noc2mcif_axi_b_bid + ,noc2mcif_axi_r_rvalid + ,noc2mcif_axi_r_rready + ,noc2mcif_axi_r_rid + ,noc2mcif_axi_r_rlast + ,noc2mcif_axi_r_rdata + ,nvdla2csb_valid + ,nvdla2csb_data + ,nvdla2csb_wr_complete + ,core_intr + ,pwrbus_ram_pd + ,sdp2csb_resp_valid + ,sdp2csb_resp_pd + ,sdp2glb_done_intr_pd + ,sdp2mcif_rd_cdt_lat_fifo_pop + ,sdp2mcif_rd_req_valid + ,sdp2mcif_rd_req_ready + ,sdp2mcif_rd_req_pd + ,sdp2mcif_wr_req_valid + ,sdp2mcif_wr_req_ready + ,sdp2mcif_wr_req_pd + ,sdp2pdp_valid + ,sdp2pdp_ready + ,sdp2pdp_pd + ,sdp_rdma2csb_resp_valid + ,sdp_rdma2csb_resp_pd + ,nvdla_core_clk + ,dla_reset_rstn + ,nvdla_core_rstn + ,nvdla_falcon_clk + ,nvdla_clk_ovr_on + ); +// +// NV_NVDLA_partition_o_io.v +// +//////////////////////////////////////////////////////////////////// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input cdma2csb_resp_valid; /* data valid */ +input [33:0] cdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [1:0] cdma_dat2glb_done_intr_pd; +input [1:0] cdma_wt2glb_done_intr_pd; +input cmac_a2csb_resp_valid; /* data valid */ +input [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_a_req_pvld; /* data valid */ +input csb2cmac_a_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_a_req_pd; +input cmac_b2csb_resp_valid; /* data valid */ +input [33:0] cmac_b2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_b_req_pvld; /* data valid */ +input csb2cmac_b_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_b_req_pd; +input cacc2csb_resp_valid; /* data valid */ +input [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [1:0] cacc2glb_done_intr_pd; +output csb2cacc_req_pvld; /* data valid */ +input csb2cacc_req_prdy; /* data return handshake */ +output [62:0] csb2cacc_req_pd; +output csb2cdma_req_pvld; /* data valid */ +input csb2cdma_req_prdy; /* data return handshake */ +output [62:0] csb2cdma_req_pd; +output csb2csc_req_pvld; /* data valid */ +input csb2csc_req_prdy; /* data return handshake */ +output [62:0] csb2csc_req_pd; +input csc2csb_resp_valid; /* data valid */ +input [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input csb2nvdla_valid; /* data valid */ +output csb2nvdla_ready; /* data return handshake */ +input [15:0] csb2nvdla_addr; +input [31:0] csb2nvdla_wdat; +input csb2nvdla_write; +input csb2nvdla_nposted; +output csb2sdp_rdma_req_pvld; /* data valid */ +input csb2sdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_rdma_req_pd; +output csb2sdp_req_pvld; /* data valid */ +input csb2sdp_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_req_pd; +output mcif2noc_axi_ar_arvalid; +input mcif2noc_axi_ar_arready; +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +output mcif2noc_axi_aw_awvalid; +input mcif2noc_axi_aw_awready; +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; +input mcif2noc_axi_w_wready; +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; +output noc2mcif_axi_b_bready; +input [7:0] noc2mcif_axi_b_bid; +input noc2mcif_axi_r_rvalid; +output noc2mcif_axi_r_rready; +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +input cdma_dat2mcif_rd_req_valid; +output cdma_dat2mcif_rd_req_ready; +input [32 +14:0] cdma_dat2mcif_rd_req_pd; +input cdma_wt2mcif_rd_req_valid; +output cdma_wt2mcif_rd_req_ready; +input [32 +14:0] cdma_wt2mcif_rd_req_pd; +output mcif2cdma_dat_rd_rsp_valid; +input mcif2cdma_dat_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2cdma_dat_rd_rsp_pd; +output mcif2cdma_wt_rd_rsp_valid; +input mcif2cdma_wt_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2cdma_wt_rd_rsp_pd; +output mcif2sdp_b_rd_rsp_valid; +input mcif2sdp_b_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2sdp_b_rd_rsp_pd; +input sdp_b2mcif_rd_cdt_lat_fifo_pop; +input sdp_b2mcif_rd_req_valid; +output sdp_b2mcif_rd_req_ready; +input [32 +14:0] sdp_b2mcif_rd_req_pd; +output mcif2sdp_n_rd_rsp_valid; +input mcif2sdp_n_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2sdp_n_rd_rsp_pd; +input sdp_n2mcif_rd_cdt_lat_fifo_pop; +input sdp_n2mcif_rd_req_valid; +output sdp_n2mcif_rd_req_ready; +input [32 +14:0] sdp_n2mcif_rd_req_pd; +input sdp2mcif_rd_cdt_lat_fifo_pop; +input sdp2mcif_rd_req_valid; +output sdp2mcif_rd_req_ready; +input [32 +14:0] sdp2mcif_rd_req_pd; +output mcif2sdp_rd_rsp_valid; +input mcif2sdp_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2sdp_rd_rsp_pd; +output mcif2sdp_wr_rsp_complete; +input sdp2mcif_wr_req_valid; +output sdp2mcif_wr_req_ready; +input [64 +(64/8/8):0] sdp2mcif_wr_req_pd; +output nvdla2csb_valid; /* data valid */ +output [31:0] nvdla2csb_data; +output nvdla2csb_wr_complete; +output core_intr; +input [31:0] pwrbus_ram_pd; +input sdp2csb_resp_valid; /* data valid */ +input [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [1:0] sdp2glb_done_intr_pd; +input sdp2pdp_valid; +output sdp2pdp_ready; +input [8*1 -1:0] sdp2pdp_pd; +input sdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] sdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input nvdla_core_clk; +input dla_reset_rstn; +output nvdla_core_rstn; +input nvdla_falcon_clk; +output nvdla_clk_ovr_on; +///////////////////////////////////////////////////////// +wire [62:0] csb2cfgrom_req_pd; +wire csb2cfgrom_req_pvld; +wire csb2cfgrom_req_prdy; +wire [33:0] cfgrom2csb_resp_pd; +wire cfgrom2csb_resp_valid; +wire [33:0] bdma2csb_resp_pd; +wire bdma2csb_resp_valid; +wire bdma2cvif_rd_cdt_lat_fifo_pop; +wire cdp2cvif_rd_cdt_lat_fifo_pop; +wire pdp2cvif_rd_cdt_lat_fifo_pop; +wire rbk2cvif_rd_cdt_lat_fifo_pop; +wire sdp2cvif_rd_cdt_lat_fifo_pop; +wire sdp_n2cvif_rd_cdt_lat_fifo_pop; +wire sdp_e2cvif_rd_cdt_lat_fifo_pop; +wire sdp_b2cvif_rd_cdt_lat_fifo_pop; +wire bdma2mcif_rd_cdt_lat_fifo_pop; +wire cdp2mcif_rd_cdt_lat_fifo_pop; +wire pdp2mcif_rd_cdt_lat_fifo_pop; +wire rbk2mcif_rd_cdt_lat_fifo_pop; +wire sdp2mcif_rd_cdt_lat_fifo_pop; +wire sdp_n2mcif_rd_cdt_lat_fifo_pop; +wire sdp_e2mcif_rd_cdt_lat_fifo_pop; +wire sdp_b2mcif_rd_cdt_lat_fifo_pop; +wire cdma_wt2cvif_rd_cdt_lat_fifo_pop; +wire cdma_wt2mcif_rd_cdt_lat_fifo_pop; +wire cdma_dat2cvif_rd_cdt_lat_fifo_pop; +wire cdma_dat2mcif_rd_cdt_lat_fifo_pop; +wire [1:0] bdma2glb_done_intr_pd; +wire [32 +14:0] bdma2mcif_rd_req_pd; +wire bdma2mcif_rd_req_ready; +wire bdma2mcif_rd_req_valid; +wire [64 +(64/8/8):0] bdma2mcif_wr_req_pd; +wire bdma2mcif_wr_req_ready; +wire bdma2mcif_wr_req_valid; +wire [33:0] cdp2csb_resp_pd; +wire cdp2csb_resp_valid; +wire [1:0] cdp2glb_done_intr_pd; +wire [32 +14:0] cdp2mcif_rd_req_pd; +wire cdp2mcif_rd_req_ready; +wire cdp2mcif_rd_req_valid; +wire [64 +(64/8/8):0] cdp2mcif_wr_req_pd; +wire cdp2mcif_wr_req_ready; +wire cdp2mcif_wr_req_valid; +wire [33:0] cdp_rdma2csb_resp_pd; +wire cdp_rdma2csb_resp_valid; +wire [62:0] csb2bdma_req_pd; +wire csb2bdma_req_prdy; +wire csb2bdma_req_pvld; +wire [62:0] csb2cdp_rdma_req_pd; +wire csb2cdp_rdma_req_prdy; +wire csb2cdp_rdma_req_pvld; +wire [62:0] csb2cdp_req_pd; +wire csb2cdp_req_prdy; +wire csb2cdp_req_pvld; +wire [62:0] csb2glb_req_pd; +wire csb2glb_req_prdy; +wire csb2glb_req_pvld; +wire [62:0] csb2mcif_req_pd; +wire csb2mcif_req_prdy; +wire csb2mcif_req_pvld; +wire [62:0] csb2pdp_rdma_req_pd; +wire csb2pdp_rdma_req_prdy; +wire csb2pdp_rdma_req_pvld; +wire [62:0] csb2pdp_req_pd; +wire csb2pdp_req_prdy; +wire csb2pdp_req_pvld; +wire [62:0] csb2rbk_req_pd; +wire csb2rbk_req_prdy; +wire csb2rbk_req_pvld; +wire dla_clk_ovr_on_sync; +wire [33:0] glb2csb_resp_pd; +wire glb2csb_resp_valid; +wire global_clk_ovr_on_sync; +wire [64 +(64/8/8)-1:0] mcif2bdma_rd_rsp_pd; +wire mcif2bdma_rd_rsp_ready; +wire mcif2bdma_rd_rsp_valid; +wire mcif2bdma_wr_rsp_complete; +wire [64 +(64/8/8)-1:0] mcif2cdp_rd_rsp_pd; +wire mcif2cdp_rd_rsp_ready; +wire mcif2cdp_rd_rsp_valid; +wire mcif2cdp_wr_rsp_complete; +wire [33:0] mcif2csb_resp_pd; +wire mcif2csb_resp_valid; +wire [64 +(64/8/8)-1:0] mcif2pdp_rd_rsp_pd; +wire mcif2pdp_rd_rsp_ready; +wire mcif2pdp_rd_rsp_valid; +wire mcif2pdp_wr_rsp_complete; +wire [64 +(64/8/8)-1:0] mcif2rbk_rd_rsp_pd; +wire mcif2rbk_rd_rsp_ready; +wire mcif2rbk_rd_rsp_valid; +wire mcif2rbk_wr_rsp_complete; +wire nvdla_falcon_rstn; +wire [33:0] pdp2csb_resp_pd; +wire pdp2csb_resp_valid; +wire [1:0] pdp2glb_done_intr_pd; +wire [32 +14:0] pdp2mcif_rd_req_pd; +wire pdp2mcif_rd_req_ready; +wire pdp2mcif_rd_req_valid; +wire [64 +(64/8/8):0] pdp2mcif_wr_req_pd; +wire pdp2mcif_wr_req_ready; +wire pdp2mcif_wr_req_valid; +wire [33:0] pdp_rdma2csb_resp_pd; +wire pdp_rdma2csb_resp_valid; +wire [33:0] rbk2csb_resp_pd; +wire rbk2csb_resp_valid; +wire [32 +14:0] rbk2mcif_rd_req_pd; +wire rbk2mcif_rd_req_ready; +wire rbk2mcif_rd_req_valid; +wire [64 +(64/8/8):0] rbk2mcif_wr_req_pd; +wire rbk2mcif_wr_req_ready; +wire rbk2mcif_wr_req_valid; +wire [1:0] rubik2glb_done_intr_pd; +// +assign nvdla_clk_ovr_on = 0; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Reset Syncer for nvdla_core_clk // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_core_reset u_sync_core_reset ( + .dla_reset_rstn (dla_reset_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_core_rstn) + ,.core_reset_rstn (1'b1) + ,.nvdla_clk (nvdla_core_clk) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Reset Syncer for nvdla_falcon_clk // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_sync_falcon_reset ( + .dla_reset_rstn (nvdla_core_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_falcon_rstn) + ,.nvdla_clk (nvdla_falcon_clk) + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_core_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_core_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (global_clk_ovr_on_sync) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: CFGROM // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cfgrom u_NV_NVDLA_cfgrom( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.csb2cfgrom_req_pd (csb2cfgrom_req_pd ) + ,.csb2cfgrom_req_pvld (csb2cfgrom_req_pvld ) + ,.csb2cfgrom_req_prdy (csb2cfgrom_req_prdy ) + ,.cfgrom2csb_resp_pd (cfgrom2csb_resp_pd ) + ,.cfgrom2csb_resp_valid (cfgrom2csb_resp_valid ) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: CSB master // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_csb_master u_NV_NVDLA_csb_master ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.nvdla_falcon_clk (nvdla_falcon_clk) + ,.nvdla_falcon_rstn (nvdla_falcon_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.csb2nvdla_valid (csb2nvdla_valid) + ,.csb2nvdla_ready (csb2nvdla_ready) + ,.csb2nvdla_addr (csb2nvdla_addr) + ,.csb2nvdla_wdat (csb2nvdla_wdat) + ,.csb2nvdla_write (csb2nvdla_write) + ,.csb2nvdla_nposted (csb2nvdla_nposted) + ,.nvdla2csb_valid (nvdla2csb_valid) + ,.nvdla2csb_data (nvdla2csb_data) + ,.nvdla2csb_wr_complete (nvdla2csb_wr_complete) + ,.csb2cfgrom_req_pd (csb2cfgrom_req_pd ) + ,.csb2cfgrom_req_pvld (csb2cfgrom_req_pvld ) + ,.csb2cfgrom_req_prdy (csb2cfgrom_req_prdy ) + ,.cfgrom2csb_resp_pd (cfgrom2csb_resp_pd ) + ,.cfgrom2csb_resp_valid (cfgrom2csb_resp_valid ) + ,.csb2glb_req_pvld (csb2glb_req_pvld) + ,.csb2glb_req_prdy (csb2glb_req_prdy) + ,.csb2glb_req_pd (csb2glb_req_pd) + ,.glb2csb_resp_valid (glb2csb_resp_valid) + ,.glb2csb_resp_pd (glb2csb_resp_pd) + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) + ,.csb2mcif_req_pd (csb2mcif_req_pd) + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) + ,.mcif2csb_resp_pd (mcif2csb_resp_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd) + ,.csb2csc_req_pvld (csb2csc_req_pvld) + ,.csb2csc_req_prdy (csb2csc_req_prdy) + ,.csb2csc_req_pd (csb2csc_req_pd) + ,.csc2csb_resp_valid (csc2csb_resp_valid) + ,.csc2csb_resp_pd (csc2csb_resp_pd) + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) + ,.csb2cmac_b_req_pvld (csb2cmac_b_req_pvld) + ,.csb2cmac_b_req_prdy (csb2cmac_b_req_prdy) + ,.csb2cmac_b_req_pd (csb2cmac_b_req_pd) + ,.cmac_b2csb_resp_valid (cmac_b2csb_resp_valid) + ,.cmac_b2csb_resp_pd (cmac_b2csb_resp_pd) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd) + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd) + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd) + ,.csb2pdp_req_pvld (csb2pdp_req_pvld) + ,.csb2pdp_req_prdy (csb2pdp_req_prdy) + ,.csb2pdp_req_pd (csb2pdp_req_pd) + ,.pdp2csb_resp_valid (pdp2csb_resp_valid) + ,.pdp2csb_resp_pd (pdp2csb_resp_pd) + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd) + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd) + ,.csb2cdp_req_pvld (csb2cdp_req_pvld) + ,.csb2cdp_req_prdy (csb2cdp_req_prdy) + ,.csb2cdp_req_pd (csb2cdp_req_pd) + ,.cdp2csb_resp_valid (cdp2csb_resp_valid) + ,.cdp2csb_resp_pd (cdp2csb_resp_pd) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: ASYNC CROSSING INTERFACE // +//////////////////////////////////////////////////////////////////////// +//&Instance NV_NVDLA_async; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: AXI Interface to MC // +//////////////////////////////////////////////////////////////////////// +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//: my @dma_name = ("bdma","cdma_dat","cdma_wt","cdp","pdp","rbk","sdp","sdp_b","sdp_e","sdp_n"); +//: my @lat_fifo_depth = (245,0,0,61,61,80,80,160,80,160,0,0,0,0,0,0); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: if ($lat_fifo_depth[$i] != 0) { +//: print qq( +//: wire dma_sr_$dma_name[$i]_lat_fifo_pop = $dma_name[$i]2cvif_rd_cdt_lat_fifo_pop; +//: wire dma_dr_$dma_name[$i]_lat_fifo_pop = $dma_name[$i]2mcif_rd_cdt_lat_fifo_pop; +//: ); +//: } else { +//: print qq( +//: wire dma_sr_$dma_name[$i]_lat_fifo_pop = 1'b0; +//: wire dma_dr_$dma_name[$i]_lat_fifo_pop = 1'b0; +//: ); +//: } +//: $nindex++; +//: } +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire dma_sr_cdma_dat_lat_fifo_pop = 1'b0; +wire dma_dr_cdma_dat_lat_fifo_pop = 1'b0; + +wire dma_sr_cdma_wt_lat_fifo_pop = 1'b0; +wire dma_dr_cdma_wt_lat_fifo_pop = 1'b0; + +wire dma_sr_cdp_lat_fifo_pop = cdp2cvif_rd_cdt_lat_fifo_pop; +wire dma_dr_cdp_lat_fifo_pop = cdp2mcif_rd_cdt_lat_fifo_pop; + +wire dma_sr_pdp_lat_fifo_pop = pdp2cvif_rd_cdt_lat_fifo_pop; +wire dma_dr_pdp_lat_fifo_pop = pdp2mcif_rd_cdt_lat_fifo_pop; + +wire dma_sr_sdp_lat_fifo_pop = sdp2cvif_rd_cdt_lat_fifo_pop; +wire dma_dr_sdp_lat_fifo_pop = sdp2mcif_rd_cdt_lat_fifo_pop; + +wire dma_sr_sdp_b_lat_fifo_pop = sdp_b2cvif_rd_cdt_lat_fifo_pop; +wire dma_dr_sdp_b_lat_fifo_pop = sdp_b2mcif_rd_cdt_lat_fifo_pop; + +wire dma_sr_sdp_n_lat_fifo_pop = sdp_n2cvif_rd_cdt_lat_fifo_pop; +wire dma_dr_sdp_n_lat_fifo_pop = sdp_n2mcif_rd_cdt_lat_fifo_pop; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +// just for nv_small test, can be replaced by configurable design +NV_NVDLA_NOCIF_dram u_NV_NVDLA_mcif ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//: my @dma_name = ("bdma","cdma_dat","cdma_wt","cdp","pdp","rbk","sdp","sdp_b","sdp_e","sdp_n"); +//: my @client_id = (0, 8, 9, 3, 2, 4, 1, 5, 7, 6,0,0,0,0,0,0,0); +//: my @lat_fifo_depth = (245,0,0,61,61,80,80,160,80,160,0,0,0,0,0,0); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: ,.client${nindex}2mcif_rd_cdt_lat_fifo_pop (dma_dr_$dma_name[$i]_lat_fifo_pop) //| w +//: ,.client${nindex}2mcif_rd_req_pd ($dma_name[$i]2mcif_rd_req_pd ) //|< w +//: ,.client${nindex}2mcif_lat_fifo_depth (8'd$lat_fifo_depth[$i] ) //|< w +//: ,.mcif2client${nindex}_rd_rsp_valid (mcif2$dma_name[$i]_rd_rsp_valid) //|> w +//: ,.mcif2client${nindex}_rd_rsp_ready (mcif2$dma_name[$i]_rd_rsp_ready) //|< w +//: ,.mcif2client${nindex}_rd_rsp_pd (mcif2$dma_name[$i]_rd_rsp_pd ) //|> w +//: ,.client${nindex}2mcif_rd_axid (4'd$client_id[$i] ) +//:); +//:$nindex = $nindex + 1; +//:} +//:} +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1,1, 1,0, 0,0,0,0,0,0,0,0,0,0,0); +//: my @dma_name = ("bdma","sdp","pdp","cdp","rbk"); +//: my @client_id = (0,1,2,3,4); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: ,.client${nindex}2mcif_wr_req_valid ($dma_name[$i]2mcif_wr_req_valid) //|< w +//: ,.client${nindex}2mcif_wr_req_ready ($dma_name[$i]2mcif_wr_req_ready) //|> w +//: ,.client${nindex}2mcif_wr_req_pd ($dma_name[$i]2mcif_wr_req_pd ) //|< w +//: ,.mcif2client${nindex}_wr_rsp_complete (mcif2$dma_name[$i]_wr_rsp_complete) //|> w +//: ,.client${nindex}2mcif_wr_axid (4'd$client_id[$i] ) +//:); +//:$nindex = $nindex + 1; +//:} +//:} +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.client02mcif_rd_cdt_lat_fifo_pop (dma_dr_cdma_dat_lat_fifo_pop) //| w +,.client02mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd ) //|< w +,.client02mcif_lat_fifo_depth (8'd0 ) //|< w +,.mcif2client0_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) //|> w +,.mcif2client0_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) //|< w +,.mcif2client0_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd ) //|> w +,.client02mcif_rd_axid (4'd8 ) + +,.client12mcif_rd_cdt_lat_fifo_pop (dma_dr_cdma_wt_lat_fifo_pop) //| w +,.client12mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd ) //|< w +,.client12mcif_lat_fifo_depth (8'd0 ) //|< w +,.mcif2client1_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) //|> w +,.mcif2client1_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) //|< w +,.mcif2client1_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd ) //|> w +,.client12mcif_rd_axid (4'd9 ) + +,.client22mcif_rd_cdt_lat_fifo_pop (dma_dr_cdp_lat_fifo_pop) //| w +,.client22mcif_rd_req_pd (cdp2mcif_rd_req_pd ) //|< w +,.client22mcif_lat_fifo_depth (8'd61 ) //|< w +,.mcif2client2_rd_rsp_valid (mcif2cdp_rd_rsp_valid) //|> w +,.mcif2client2_rd_rsp_ready (mcif2cdp_rd_rsp_ready) //|< w +,.mcif2client2_rd_rsp_pd (mcif2cdp_rd_rsp_pd ) //|> w +,.client22mcif_rd_axid (4'd3 ) + +,.client32mcif_rd_cdt_lat_fifo_pop (dma_dr_pdp_lat_fifo_pop) //| w +,.client32mcif_rd_req_pd (pdp2mcif_rd_req_pd ) //|< w +,.client32mcif_lat_fifo_depth (8'd61 ) //|< w +,.mcif2client3_rd_rsp_valid (mcif2pdp_rd_rsp_valid) //|> w +,.mcif2client3_rd_rsp_ready (mcif2pdp_rd_rsp_ready) //|< w +,.mcif2client3_rd_rsp_pd (mcif2pdp_rd_rsp_pd ) //|> w +,.client32mcif_rd_axid (4'd2 ) + +,.client42mcif_rd_cdt_lat_fifo_pop (dma_dr_sdp_lat_fifo_pop) //| w +,.client42mcif_rd_req_pd (sdp2mcif_rd_req_pd ) //|< w +,.client42mcif_lat_fifo_depth (8'd80 ) //|< w +,.mcif2client4_rd_rsp_valid (mcif2sdp_rd_rsp_valid) //|> w +,.mcif2client4_rd_rsp_ready (mcif2sdp_rd_rsp_ready) //|< w +,.mcif2client4_rd_rsp_pd (mcif2sdp_rd_rsp_pd ) //|> w +,.client42mcif_rd_axid (4'd1 ) + +,.client52mcif_rd_cdt_lat_fifo_pop (dma_dr_sdp_b_lat_fifo_pop) //| w +,.client52mcif_rd_req_pd (sdp_b2mcif_rd_req_pd ) //|< w +,.client52mcif_lat_fifo_depth (8'd160 ) //|< w +,.mcif2client5_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) //|> w +,.mcif2client5_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) //|< w +,.mcif2client5_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd ) //|> w +,.client52mcif_rd_axid (4'd5 ) + +,.client62mcif_rd_cdt_lat_fifo_pop (dma_dr_sdp_n_lat_fifo_pop) //| w +,.client62mcif_rd_req_pd (sdp_n2mcif_rd_req_pd ) //|< w +,.client62mcif_lat_fifo_depth (8'd160 ) //|< w +,.mcif2client6_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) //|> w +,.mcif2client6_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) //|< w +,.mcif2client6_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd ) //|> w +,.client62mcif_rd_axid (4'd6 ) + +,.client02mcif_wr_req_valid (sdp2mcif_wr_req_valid) //|< w +,.client02mcif_wr_req_ready (sdp2mcif_wr_req_ready) //|> w +,.client02mcif_wr_req_pd (sdp2mcif_wr_req_pd ) //|< w +,.mcif2client0_wr_rsp_complete (mcif2sdp_wr_rsp_complete) //|> w +,.client02mcif_wr_axid (4'd1 ) + +,.client12mcif_wr_req_valid (pdp2mcif_wr_req_valid) //|< w +,.client12mcif_wr_req_ready (pdp2mcif_wr_req_ready) //|> w +,.client12mcif_wr_req_pd (pdp2mcif_wr_req_pd ) //|< w +,.mcif2client1_wr_rsp_complete (mcif2pdp_wr_rsp_complete) //|> w +,.client12mcif_wr_axid (4'd2 ) + +,.client22mcif_wr_req_valid (cdp2mcif_wr_req_valid) //|< w +,.client22mcif_wr_req_ready (cdp2mcif_wr_req_ready) //|> w +,.client22mcif_wr_req_pd (cdp2mcif_wr_req_pd ) //|< w +,.mcif2client2_wr_rsp_complete (mcif2cdp_wr_rsp_complete) //|> w +,.client22mcif_wr_axid (4'd3 ) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< w + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> w + ,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< w + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> w + ,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> w + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr ) //|> o + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr ) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata ) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb ) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid) //|< i + ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready) //|> o + ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid[7:0]) //|< i + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid[7:0]) //|< i + ,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i + ,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata ) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: AXI Interface to CVSRAM // +//////////////////////////////////////////////////////////////////////// +// +// +// +//&Connect s/sdp2(mc|cv)if_rd_(req|cdt)/sdp2${1}if_rd_${2}_dst/; +//&Connect s/(mc|cv)if2sdp_rd_(rsp)/${1}if2sdp_rd_${2}_src/; +//&Connect s/sdp_b2(mc|cv)if_rd_(req|cdt)/sdp_b2${1}if_rd_${2}_dst/; +//&Connect s/(mc|cv)if2sdp_b_rd_(rsp)/${1}if2sdp_b_rd_${2}_src/; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Bridge DMA // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Rubik engine // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Cross-Channel Data Processor // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cdp u_NV_NVDLA_cdp ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o + ,.cdp2csb_resp_valid (cdp2csb_resp_valid) //|> w + ,.cdp2csb_resp_pd (cdp2csb_resp_pd[33:0]) //|> w + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|> w + ,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop) //|> w + ,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid) //|> w + ,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready) //|< w + ,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd ) //|> w + ,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid) //|> w + ,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready) //|< w + ,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd ) //|> w + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) //|> w + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd[33:0]) //|> w + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) //|< w + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) //|> w + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd[62:0]) //|< w + ,.csb2cdp_req_pvld (csb2cdp_req_pvld) //|< w + ,.csb2cdp_req_prdy (csb2cdp_req_prdy) //|> w + ,.csb2cdp_req_pd (csb2cdp_req_pd[62:0]) //|< w + ,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid) //|< w + ,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready) //|> w + ,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd ) //|< w + ,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Planar Data Processor // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_pdp u_NV_NVDLA_pdp ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) //|< w + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) //|> w + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd[62:0]) //|< w + ,.csb2pdp_req_pvld (csb2pdp_req_pvld) //|< w + ,.csb2pdp_req_prdy (csb2pdp_req_prdy) //|> w + ,.csb2pdp_req_pd (csb2pdp_req_pd[62:0]) //|< w + ,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid) //|< w + ,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready) //|> w + ,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd ) //|< w + ,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete) //|< w + ,.pdp2csb_resp_valid (pdp2csb_resp_valid) //|> w + ,.pdp2csb_resp_pd (pdp2csb_resp_pd[33:0]) //|> w + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|> w + ,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop) //|> w + ,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid) //|> w + ,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready) //|< w + ,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd ) //|> w + ,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid) //|> w + ,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready) //|< w + ,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd ) //|> w + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) //|> w + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd[33:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.sdp2pdp_valid (sdp2pdp_valid) //|< i + ,.sdp2pdp_ready (sdp2pdp_ready) //|> o + ,.sdp2pdp_pd (sdp2pdp_pd ) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Global Unit // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_glb u_NV_NVDLA_glb ( + .csb2glb_req_pvld (csb2glb_req_pvld) //|< w + ,.csb2glb_req_prdy (csb2glb_req_prdy) //|> w + ,.csb2glb_req_pd (csb2glb_req_pd[62:0]) //|< w + ,.glb2csb_resp_valid (glb2csb_resp_valid) //|> w + ,.glb2csb_resp_pd (glb2csb_resp_pd[33:0]) //|> w + ,.core_intr (core_intr) //|> o + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) //|< i + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|< w + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|< w + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) //|< i + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) //|< i + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_falcon_clk (nvdla_falcon_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o + ,.nvdla_falcon_rstn (nvdla_falcon_rstn) //|< w + ,.test_mode (test_mode) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_partition_o diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_o.v.vcp b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_o.v.vcp new file mode 100644 index 0000000..f143d64 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_o.v.vcp @@ -0,0 +1,752 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_o.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_NVDLA_partition_o ( + test_mode + ,direct_reset_ + ,global_clk_ovr_on + ,tmc2slcg_disable_clock_gating + ,cdma2csb_resp_valid + ,cdma2csb_resp_pd + ,cdma_dat2glb_done_intr_pd + ,cdma_dat2mcif_rd_req_valid + ,cdma_dat2mcif_rd_req_ready + ,cdma_dat2mcif_rd_req_pd + ,cdma_wt2glb_done_intr_pd + ,cdma_wt2mcif_rd_req_valid + ,cdma_wt2mcif_rd_req_ready + ,cdma_wt2mcif_rd_req_pd + ,cmac_a2csb_resp_valid + ,cmac_a2csb_resp_pd + ,csb2cmac_a_req_pvld + ,csb2cmac_a_req_prdy + ,csb2cmac_a_req_pd + ,cmac_b2csb_resp_valid + ,cmac_b2csb_resp_pd + ,csb2cmac_b_req_pvld + ,csb2cmac_b_req_prdy + ,csb2cmac_b_req_pd + ,cacc2csb_resp_valid + ,cacc2csb_resp_pd + ,cacc2glb_done_intr_pd + ,csb2cacc_req_pvld + ,csb2cacc_req_prdy + ,csb2cacc_req_pd + ,csb2cdma_req_pvld + ,csb2cdma_req_prdy + ,csb2cdma_req_pd + ,csb2csc_req_pvld + ,csb2csc_req_prdy + ,csb2csc_req_pd + ,csb2nvdla_valid + ,csb2nvdla_ready + ,csb2nvdla_addr + ,csb2nvdla_wdat + ,csb2nvdla_write + ,csb2nvdla_nposted + ,csb2sdp_rdma_req_pvld + ,csb2sdp_rdma_req_prdy + ,csb2sdp_rdma_req_pd + ,csb2sdp_req_pvld + ,csb2sdp_req_prdy + ,csb2sdp_req_pd + ,csc2csb_resp_valid + ,csc2csb_resp_pd + ,mcif2cdma_dat_rd_rsp_valid + ,mcif2cdma_dat_rd_rsp_ready + ,mcif2cdma_dat_rd_rsp_pd + ,mcif2cdma_wt_rd_rsp_valid + ,mcif2cdma_wt_rd_rsp_ready + ,mcif2cdma_wt_rd_rsp_pd + ,mcif2noc_axi_ar_arvalid + ,mcif2noc_axi_ar_arready + ,mcif2noc_axi_ar_arid + ,mcif2noc_axi_ar_arlen + ,mcif2noc_axi_ar_araddr + ,mcif2noc_axi_aw_awvalid + ,mcif2noc_axi_aw_awready + ,mcif2noc_axi_aw_awid + ,mcif2noc_axi_aw_awlen + ,mcif2noc_axi_aw_awaddr + ,mcif2noc_axi_w_wvalid + ,mcif2noc_axi_w_wready + ,mcif2noc_axi_w_wdata + ,mcif2noc_axi_w_wstrb + ,mcif2noc_axi_w_wlast + ,mcif2sdp_b_rd_rsp_valid + ,mcif2sdp_b_rd_rsp_ready + ,mcif2sdp_b_rd_rsp_pd + ,sdp_b2mcif_rd_cdt_lat_fifo_pop + ,sdp_b2mcif_rd_req_valid + ,sdp_b2mcif_rd_req_ready + ,sdp_b2mcif_rd_req_pd + ,mcif2sdp_n_rd_rsp_valid + ,mcif2sdp_n_rd_rsp_ready + ,mcif2sdp_n_rd_rsp_pd + ,sdp_n2mcif_rd_cdt_lat_fifo_pop + ,sdp_n2mcif_rd_req_valid + ,sdp_n2mcif_rd_req_ready + ,sdp_n2mcif_rd_req_pd + ,mcif2sdp_rd_rsp_valid + ,mcif2sdp_rd_rsp_ready + ,mcif2sdp_rd_rsp_pd + ,mcif2sdp_wr_rsp_complete + ,noc2mcif_axi_b_bvalid + ,noc2mcif_axi_b_bready + ,noc2mcif_axi_b_bid + ,noc2mcif_axi_r_rvalid + ,noc2mcif_axi_r_rready + ,noc2mcif_axi_r_rid + ,noc2mcif_axi_r_rlast + ,noc2mcif_axi_r_rdata + ,nvdla2csb_valid + ,nvdla2csb_data + ,nvdla2csb_wr_complete + ,core_intr + ,pwrbus_ram_pd + ,sdp2csb_resp_valid + ,sdp2csb_resp_pd + ,sdp2glb_done_intr_pd + ,sdp2mcif_rd_cdt_lat_fifo_pop + ,sdp2mcif_rd_req_valid + ,sdp2mcif_rd_req_ready + ,sdp2mcif_rd_req_pd + ,sdp2mcif_wr_req_valid + ,sdp2mcif_wr_req_ready + ,sdp2mcif_wr_req_pd + ,sdp2pdp_valid + ,sdp2pdp_ready + ,sdp2pdp_pd + ,sdp_rdma2csb_resp_valid + ,sdp_rdma2csb_resp_pd + ,nvdla_core_clk + ,dla_reset_rstn + ,nvdla_core_rstn + ,nvdla_falcon_clk + ,nvdla_clk_ovr_on + ); +// +// NV_NVDLA_partition_o_io.v +// +//////////////////////////////////////////////////////////////////// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input cdma2csb_resp_valid; /* data valid */ +input [33:0] cdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [1:0] cdma_dat2glb_done_intr_pd; +input [1:0] cdma_wt2glb_done_intr_pd; +input cmac_a2csb_resp_valid; /* data valid */ +input [33:0] cmac_a2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_a_req_pvld; /* data valid */ +input csb2cmac_a_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_a_req_pd; +input cmac_b2csb_resp_valid; /* data valid */ +input [33:0] cmac_b2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output csb2cmac_b_req_pvld; /* data valid */ +input csb2cmac_b_req_prdy; /* data return handshake */ +output [62:0] csb2cmac_b_req_pd; +input cacc2csb_resp_valid; /* data valid */ +input [33:0] cacc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [1:0] cacc2glb_done_intr_pd; +output csb2cacc_req_pvld; /* data valid */ +input csb2cacc_req_prdy; /* data return handshake */ +output [62:0] csb2cacc_req_pd; +output csb2cdma_req_pvld; /* data valid */ +input csb2cdma_req_prdy; /* data return handshake */ +output [62:0] csb2cdma_req_pd; +output csb2csc_req_pvld; /* data valid */ +input csb2csc_req_prdy; /* data return handshake */ +output [62:0] csb2csc_req_pd; +input csc2csb_resp_valid; /* data valid */ +input [33:0] csc2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input csb2nvdla_valid; /* data valid */ +output csb2nvdla_ready; /* data return handshake */ +input [15:0] csb2nvdla_addr; +input [31:0] csb2nvdla_wdat; +input csb2nvdla_write; +input csb2nvdla_nposted; +output csb2sdp_rdma_req_pvld; /* data valid */ +input csb2sdp_rdma_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_rdma_req_pd; +output csb2sdp_req_pvld; /* data valid */ +input csb2sdp_req_prdy; /* data return handshake */ +output [62:0] csb2sdp_req_pd; +output mcif2noc_axi_ar_arvalid; +input mcif2noc_axi_ar_arready; +output [7:0] mcif2noc_axi_ar_arid; +output [3:0] mcif2noc_axi_ar_arlen; +output [32 -1:0] mcif2noc_axi_ar_araddr; +output mcif2noc_axi_aw_awvalid; +input mcif2noc_axi_aw_awready; +output [7:0] mcif2noc_axi_aw_awid; +output [3:0] mcif2noc_axi_aw_awlen; +output [32 -1:0] mcif2noc_axi_aw_awaddr; +output mcif2noc_axi_w_wvalid; +input mcif2noc_axi_w_wready; +output [64 -1:0] mcif2noc_axi_w_wdata; +output [64/8-1:0] mcif2noc_axi_w_wstrb; +output mcif2noc_axi_w_wlast; +input noc2mcif_axi_b_bvalid; +output noc2mcif_axi_b_bready; +input [7:0] noc2mcif_axi_b_bid; +input noc2mcif_axi_r_rvalid; +output noc2mcif_axi_r_rready; +input [7:0] noc2mcif_axi_r_rid; +input noc2mcif_axi_r_rlast; +input [64 -1:0] noc2mcif_axi_r_rdata; +input cdma_dat2mcif_rd_req_valid; +output cdma_dat2mcif_rd_req_ready; +input [32 +14:0] cdma_dat2mcif_rd_req_pd; +input cdma_wt2mcif_rd_req_valid; +output cdma_wt2mcif_rd_req_ready; +input [32 +14:0] cdma_wt2mcif_rd_req_pd; +output mcif2cdma_dat_rd_rsp_valid; +input mcif2cdma_dat_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2cdma_dat_rd_rsp_pd; +output mcif2cdma_wt_rd_rsp_valid; +input mcif2cdma_wt_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2cdma_wt_rd_rsp_pd; +output mcif2sdp_b_rd_rsp_valid; +input mcif2sdp_b_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2sdp_b_rd_rsp_pd; +input sdp_b2mcif_rd_cdt_lat_fifo_pop; +input sdp_b2mcif_rd_req_valid; +output sdp_b2mcif_rd_req_ready; +input [32 +14:0] sdp_b2mcif_rd_req_pd; +output mcif2sdp_n_rd_rsp_valid; +input mcif2sdp_n_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2sdp_n_rd_rsp_pd; +input sdp_n2mcif_rd_cdt_lat_fifo_pop; +input sdp_n2mcif_rd_req_valid; +output sdp_n2mcif_rd_req_ready; +input [32 +14:0] sdp_n2mcif_rd_req_pd; +input sdp2mcif_rd_cdt_lat_fifo_pop; +input sdp2mcif_rd_req_valid; +output sdp2mcif_rd_req_ready; +input [32 +14:0] sdp2mcif_rd_req_pd; +output mcif2sdp_rd_rsp_valid; +input mcif2sdp_rd_rsp_ready; +output [64 +(64/8/8)-1:0] mcif2sdp_rd_rsp_pd; +output mcif2sdp_wr_rsp_complete; +input sdp2mcif_wr_req_valid; +output sdp2mcif_wr_req_ready; +input [64 +(64/8/8):0] sdp2mcif_wr_req_pd; +output nvdla2csb_valid; /* data valid */ +output [31:0] nvdla2csb_data; +output nvdla2csb_wr_complete; +output core_intr; +input [31:0] pwrbus_ram_pd; +input sdp2csb_resp_valid; /* data valid */ +input [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input [1:0] sdp2glb_done_intr_pd; +input sdp2pdp_valid; +output sdp2pdp_ready; +input [8*1 -1:0] sdp2pdp_pd; +input sdp_rdma2csb_resp_valid; /* data valid */ +input [33:0] sdp_rdma2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +input nvdla_core_clk; +input dla_reset_rstn; +output nvdla_core_rstn; +input nvdla_falcon_clk; +output nvdla_clk_ovr_on; +///////////////////////////////////////////////////////// +wire [62:0] csb2cfgrom_req_pd; +wire csb2cfgrom_req_pvld; +wire csb2cfgrom_req_prdy; +wire [33:0] cfgrom2csb_resp_pd; +wire cfgrom2csb_resp_valid; +wire [33:0] bdma2csb_resp_pd; +wire bdma2csb_resp_valid; +wire bdma2cvif_rd_cdt_lat_fifo_pop; +wire cdp2cvif_rd_cdt_lat_fifo_pop; +wire pdp2cvif_rd_cdt_lat_fifo_pop; +wire rbk2cvif_rd_cdt_lat_fifo_pop; +wire sdp2cvif_rd_cdt_lat_fifo_pop; +wire sdp_n2cvif_rd_cdt_lat_fifo_pop; +wire sdp_e2cvif_rd_cdt_lat_fifo_pop; +wire sdp_b2cvif_rd_cdt_lat_fifo_pop; +wire bdma2mcif_rd_cdt_lat_fifo_pop; +wire cdp2mcif_rd_cdt_lat_fifo_pop; +wire pdp2mcif_rd_cdt_lat_fifo_pop; +wire rbk2mcif_rd_cdt_lat_fifo_pop; +wire sdp2mcif_rd_cdt_lat_fifo_pop; +wire sdp_n2mcif_rd_cdt_lat_fifo_pop; +wire sdp_e2mcif_rd_cdt_lat_fifo_pop; +wire sdp_b2mcif_rd_cdt_lat_fifo_pop; +wire cdma_wt2cvif_rd_cdt_lat_fifo_pop; +wire cdma_wt2mcif_rd_cdt_lat_fifo_pop; +wire cdma_dat2cvif_rd_cdt_lat_fifo_pop; +wire cdma_dat2mcif_rd_cdt_lat_fifo_pop; +wire [1:0] bdma2glb_done_intr_pd; +wire [32 +14:0] bdma2mcif_rd_req_pd; +wire bdma2mcif_rd_req_ready; +wire bdma2mcif_rd_req_valid; +wire [64 +(64/8/8):0] bdma2mcif_wr_req_pd; +wire bdma2mcif_wr_req_ready; +wire bdma2mcif_wr_req_valid; +wire [33:0] cdp2csb_resp_pd; +wire cdp2csb_resp_valid; +wire [1:0] cdp2glb_done_intr_pd; +wire [32 +14:0] cdp2mcif_rd_req_pd; +wire cdp2mcif_rd_req_ready; +wire cdp2mcif_rd_req_valid; +wire [64 +(64/8/8):0] cdp2mcif_wr_req_pd; +wire cdp2mcif_wr_req_ready; +wire cdp2mcif_wr_req_valid; +wire [33:0] cdp_rdma2csb_resp_pd; +wire cdp_rdma2csb_resp_valid; +wire [62:0] csb2bdma_req_pd; +wire csb2bdma_req_prdy; +wire csb2bdma_req_pvld; +wire [62:0] csb2cdp_rdma_req_pd; +wire csb2cdp_rdma_req_prdy; +wire csb2cdp_rdma_req_pvld; +wire [62:0] csb2cdp_req_pd; +wire csb2cdp_req_prdy; +wire csb2cdp_req_pvld; +wire [62:0] csb2glb_req_pd; +wire csb2glb_req_prdy; +wire csb2glb_req_pvld; +wire [62:0] csb2mcif_req_pd; +wire csb2mcif_req_prdy; +wire csb2mcif_req_pvld; +wire [62:0] csb2pdp_rdma_req_pd; +wire csb2pdp_rdma_req_prdy; +wire csb2pdp_rdma_req_pvld; +wire [62:0] csb2pdp_req_pd; +wire csb2pdp_req_prdy; +wire csb2pdp_req_pvld; +wire [62:0] csb2rbk_req_pd; +wire csb2rbk_req_prdy; +wire csb2rbk_req_pvld; +wire dla_clk_ovr_on_sync; +wire [33:0] glb2csb_resp_pd; +wire glb2csb_resp_valid; +wire global_clk_ovr_on_sync; +wire [64 +(64/8/8)-1:0] mcif2bdma_rd_rsp_pd; +wire mcif2bdma_rd_rsp_ready; +wire mcif2bdma_rd_rsp_valid; +wire mcif2bdma_wr_rsp_complete; +wire [64 +(64/8/8)-1:0] mcif2cdp_rd_rsp_pd; +wire mcif2cdp_rd_rsp_ready; +wire mcif2cdp_rd_rsp_valid; +wire mcif2cdp_wr_rsp_complete; +wire [33:0] mcif2csb_resp_pd; +wire mcif2csb_resp_valid; +wire [64 +(64/8/8)-1:0] mcif2pdp_rd_rsp_pd; +wire mcif2pdp_rd_rsp_ready; +wire mcif2pdp_rd_rsp_valid; +wire mcif2pdp_wr_rsp_complete; +wire [64 +(64/8/8)-1:0] mcif2rbk_rd_rsp_pd; +wire mcif2rbk_rd_rsp_ready; +wire mcif2rbk_rd_rsp_valid; +wire mcif2rbk_wr_rsp_complete; +wire nvdla_falcon_rstn; +wire [33:0] pdp2csb_resp_pd; +wire pdp2csb_resp_valid; +wire [1:0] pdp2glb_done_intr_pd; +wire [32 +14:0] pdp2mcif_rd_req_pd; +wire pdp2mcif_rd_req_ready; +wire pdp2mcif_rd_req_valid; +wire [64 +(64/8/8):0] pdp2mcif_wr_req_pd; +wire pdp2mcif_wr_req_ready; +wire pdp2mcif_wr_req_valid; +wire [33:0] pdp_rdma2csb_resp_pd; +wire pdp_rdma2csb_resp_valid; +wire [33:0] rbk2csb_resp_pd; +wire rbk2csb_resp_valid; +wire [32 +14:0] rbk2mcif_rd_req_pd; +wire rbk2mcif_rd_req_ready; +wire rbk2mcif_rd_req_valid; +wire [64 +(64/8/8):0] rbk2mcif_wr_req_pd; +wire rbk2mcif_wr_req_ready; +wire rbk2mcif_wr_req_valid; +wire [1:0] rubik2glb_done_intr_pd; +// +assign nvdla_clk_ovr_on = 0; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Reset Syncer for nvdla_core_clk // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_core_reset u_sync_core_reset ( + .dla_reset_rstn (dla_reset_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_core_rstn) + ,.core_reset_rstn (1'b1) + ,.nvdla_clk (nvdla_core_clk) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Reset Syncer for nvdla_falcon_clk // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_sync_falcon_reset ( + .dla_reset_rstn (nvdla_core_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_falcon_rstn) + ,.nvdla_clk (nvdla_falcon_clk) + ); +//////////////////////////////////////////////////////////////////////// +// SLCG override +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_core_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_core_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (global_clk_ovr_on_sync) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: CFGROM // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cfgrom u_NV_NVDLA_cfgrom( + .nvdla_core_clk (nvdla_core_clk ) + ,.nvdla_core_rstn (nvdla_core_rstn ) + ,.csb2cfgrom_req_pd (csb2cfgrom_req_pd ) + ,.csb2cfgrom_req_pvld (csb2cfgrom_req_pvld ) + ,.csb2cfgrom_req_prdy (csb2cfgrom_req_prdy ) + ,.cfgrom2csb_resp_pd (cfgrom2csb_resp_pd ) + ,.cfgrom2csb_resp_valid (cfgrom2csb_resp_valid ) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: CSB master // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_csb_master u_NV_NVDLA_csb_master ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.nvdla_falcon_clk (nvdla_falcon_clk) + ,.nvdla_falcon_rstn (nvdla_falcon_rstn) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.csb2nvdla_valid (csb2nvdla_valid) + ,.csb2nvdla_ready (csb2nvdla_ready) + ,.csb2nvdla_addr (csb2nvdla_addr) + ,.csb2nvdla_wdat (csb2nvdla_wdat) + ,.csb2nvdla_write (csb2nvdla_write) + ,.csb2nvdla_nposted (csb2nvdla_nposted) + ,.nvdla2csb_valid (nvdla2csb_valid) + ,.nvdla2csb_data (nvdla2csb_data) + ,.nvdla2csb_wr_complete (nvdla2csb_wr_complete) + ,.csb2cfgrom_req_pd (csb2cfgrom_req_pd ) + ,.csb2cfgrom_req_pvld (csb2cfgrom_req_pvld ) + ,.csb2cfgrom_req_prdy (csb2cfgrom_req_prdy ) + ,.cfgrom2csb_resp_pd (cfgrom2csb_resp_pd ) + ,.cfgrom2csb_resp_valid (cfgrom2csb_resp_valid ) + ,.csb2glb_req_pvld (csb2glb_req_pvld) + ,.csb2glb_req_prdy (csb2glb_req_prdy) + ,.csb2glb_req_pd (csb2glb_req_pd) + ,.glb2csb_resp_valid (glb2csb_resp_valid) + ,.glb2csb_resp_pd (glb2csb_resp_pd) + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) + ,.csb2mcif_req_pd (csb2mcif_req_pd) + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) + ,.mcif2csb_resp_pd (mcif2csb_resp_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd) + ,.csb2csc_req_pvld (csb2csc_req_pvld) + ,.csb2csc_req_prdy (csb2csc_req_prdy) + ,.csb2csc_req_pd (csb2csc_req_pd) + ,.csc2csb_resp_valid (csc2csb_resp_valid) + ,.csc2csb_resp_pd (csc2csb_resp_pd) + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) + ,.csb2cmac_b_req_pvld (csb2cmac_b_req_pvld) + ,.csb2cmac_b_req_prdy (csb2cmac_b_req_prdy) + ,.csb2cmac_b_req_pd (csb2cmac_b_req_pd) + ,.cmac_b2csb_resp_valid (cmac_b2csb_resp_valid) + ,.cmac_b2csb_resp_pd (cmac_b2csb_resp_pd) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd) + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd) + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd) + ,.csb2pdp_req_pvld (csb2pdp_req_pvld) + ,.csb2pdp_req_prdy (csb2pdp_req_prdy) + ,.csb2pdp_req_pd (csb2pdp_req_pd) + ,.pdp2csb_resp_valid (pdp2csb_resp_valid) + ,.pdp2csb_resp_pd (pdp2csb_resp_pd) + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd) + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd) + ,.csb2cdp_req_pvld (csb2cdp_req_pvld) + ,.csb2cdp_req_prdy (csb2cdp_req_prdy) + ,.csb2cdp_req_pd (csb2cdp_req_pd) + ,.cdp2csb_resp_valid (cdp2csb_resp_valid) + ,.cdp2csb_resp_pd (cdp2csb_resp_pd) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: ASYNC CROSSING INTERFACE // +//////////////////////////////////////////////////////////////////////// +//&Instance NV_NVDLA_async; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: AXI Interface to MC // +//////////////////////////////////////////////////////////////////////// +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//: my @dma_name = ("bdma","cdma_dat","cdma_wt","cdp","pdp","rbk","sdp","sdp_b","sdp_e","sdp_n"); +//: my @lat_fifo_depth = (245,0,0,61,61,80,80,160,80,160,0,0,0,0,0,0); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: if ($lat_fifo_depth[$i] != 0) { +//: print qq( +//: wire dma_sr_$dma_name[$i]_lat_fifo_pop = $dma_name[$i]2cvif_rd_cdt_lat_fifo_pop; +//: wire dma_dr_$dma_name[$i]_lat_fifo_pop = $dma_name[$i]2mcif_rd_cdt_lat_fifo_pop; +//: ); +//: } else { +//: print qq( +//: wire dma_sr_$dma_name[$i]_lat_fifo_pop = 1'b0; +//: wire dma_dr_$dma_name[$i]_lat_fifo_pop = 1'b0; +//: ); +//: } +//: $nindex++; +//: } +//: } +// just for nv_small test, can be replaced by configurable design +NV_NVDLA_NOCIF_dram u_NV_NVDLA_mcif ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1, 1,1, 1,0, 1, 1, 0, 1,0,0,0,0,0,0); +//: my @dma_name = ("bdma","cdma_dat","cdma_wt","cdp","pdp","rbk","sdp","sdp_b","sdp_e","sdp_n"); +//: my @client_id = (0, 8, 9, 3, 2, 4, 1, 5, 7, 6,0,0,0,0,0,0,0); +//: my @lat_fifo_depth = (245,0,0,61,61,80,80,160,80,160,0,0,0,0,0,0); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: ,.client${nindex}2mcif_rd_cdt_lat_fifo_pop (dma_dr_$dma_name[$i]_lat_fifo_pop) //| w +//: ,.client${nindex}2mcif_rd_req_pd ($dma_name[$i]2mcif_rd_req_pd ) //|< w +//: ,.client${nindex}2mcif_lat_fifo_depth (8'd$lat_fifo_depth[$i] ) //|< w +//: ,.mcif2client${nindex}_rd_rsp_valid (mcif2$dma_name[$i]_rd_rsp_valid) //|> w +//: ,.mcif2client${nindex}_rd_rsp_ready (mcif2$dma_name[$i]_rd_rsp_ready) //|< w +//: ,.mcif2client${nindex}_rd_rsp_pd (mcif2$dma_name[$i]_rd_rsp_pd ) //|> w +//: ,.client${nindex}2mcif_rd_axid (4'd$client_id[$i] ) +//:); +//:$nindex = $nindex + 1; +//:} +//:} +//:my $i; +//:my $nindex=0; +//: my @dma_index = (0, 1,1, 1,0, 0,0,0,0,0,0,0,0,0,0,0); +//: my @dma_name = ("bdma","sdp","pdp","cdp","rbk"); +//: my @client_id = (0,1,2,3,4); +//: for ($i=0;$i<16;$i++) { +//: if ($dma_index[$i]) { +//: print qq( +//: ,.client${nindex}2mcif_wr_req_valid ($dma_name[$i]2mcif_wr_req_valid) //|< w +//: ,.client${nindex}2mcif_wr_req_ready ($dma_name[$i]2mcif_wr_req_ready) //|> w +//: ,.client${nindex}2mcif_wr_req_pd ($dma_name[$i]2mcif_wr_req_pd ) //|< w +//: ,.mcif2client${nindex}_wr_rsp_complete (mcif2$dma_name[$i]_wr_rsp_complete) //|> w +//: ,.client${nindex}2mcif_wr_axid (4'd$client_id[$i] ) +//:); +//:$nindex = $nindex + 1; +//:} +//:} + ,.csb2mcif_req_pvld (csb2mcif_req_pvld) //|< w + ,.csb2mcif_req_prdy (csb2mcif_req_prdy) //|> w + ,.csb2mcif_req_pd (csb2mcif_req_pd[62:0]) //|< w + ,.mcif2csb_resp_valid (mcif2csb_resp_valid) //|> w + ,.mcif2csb_resp_pd (mcif2csb_resp_pd[33:0]) //|> w + ,.mcif2noc_axi_ar_arvalid (mcif2noc_axi_ar_arvalid) //|> o + ,.mcif2noc_axi_ar_arready (mcif2noc_axi_ar_arready) //|< i + ,.mcif2noc_axi_ar_arid (mcif2noc_axi_ar_arid[7:0]) //|> o + ,.mcif2noc_axi_ar_arlen (mcif2noc_axi_ar_arlen[3:0]) //|> o + ,.mcif2noc_axi_ar_araddr (mcif2noc_axi_ar_araddr ) //|> o + ,.mcif2noc_axi_aw_awvalid (mcif2noc_axi_aw_awvalid) //|> o + ,.mcif2noc_axi_aw_awready (mcif2noc_axi_aw_awready) //|< i + ,.mcif2noc_axi_aw_awid (mcif2noc_axi_aw_awid[7:0]) //|> o + ,.mcif2noc_axi_aw_awlen (mcif2noc_axi_aw_awlen[3:0]) //|> o + ,.mcif2noc_axi_aw_awaddr (mcif2noc_axi_aw_awaddr ) //|> o + ,.mcif2noc_axi_w_wvalid (mcif2noc_axi_w_wvalid) //|> o + ,.mcif2noc_axi_w_wready (mcif2noc_axi_w_wready) //|< i + ,.mcif2noc_axi_w_wdata (mcif2noc_axi_w_wdata ) //|> o + ,.mcif2noc_axi_w_wstrb (mcif2noc_axi_w_wstrb ) //|> o + ,.mcif2noc_axi_w_wlast (mcif2noc_axi_w_wlast) //|> o + ,.noc2mcif_axi_b_bvalid (noc2mcif_axi_b_bvalid) //|< i + ,.noc2mcif_axi_b_bready (noc2mcif_axi_b_bready) //|> o + ,.noc2mcif_axi_b_bid (noc2mcif_axi_b_bid[7:0]) //|< i + ,.noc2mcif_axi_r_rvalid (noc2mcif_axi_r_rvalid) //|< i + ,.noc2mcif_axi_r_rready (noc2mcif_axi_r_rready) //|> o + ,.noc2mcif_axi_r_rid (noc2mcif_axi_r_rid[7:0]) //|< i + ,.noc2mcif_axi_r_rlast (noc2mcif_axi_r_rlast) //|< i + ,.noc2mcif_axi_r_rdata (noc2mcif_axi_r_rdata ) //|< i + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: AXI Interface to CVSRAM // +//////////////////////////////////////////////////////////////////////// +// +// +// +//&Connect s/sdp2(mc|cv)if_rd_(req|cdt)/sdp2${1}if_rd_${2}_dst/; +//&Connect s/(mc|cv)if2sdp_rd_(rsp)/${1}if2sdp_rd_${2}_src/; +//&Connect s/sdp_b2(mc|cv)if_rd_(req|cdt)/sdp_b2${1}if_rd_${2}_dst/; +//&Connect s/(mc|cv)if2sdp_b_rd_(rsp)/${1}if2sdp_b_rd_${2}_src/; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Bridge DMA // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Rubik engine // +//////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Cross-Channel Data Processor // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_cdp u_NV_NVDLA_cdp ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o + ,.cdp2csb_resp_valid (cdp2csb_resp_valid) //|> w + ,.cdp2csb_resp_pd (cdp2csb_resp_pd[33:0]) //|> w + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|> w + ,.cdp2mcif_rd_cdt_lat_fifo_pop (cdp2mcif_rd_cdt_lat_fifo_pop) //|> w + ,.cdp2mcif_rd_req_valid (cdp2mcif_rd_req_valid) //|> w + ,.cdp2mcif_rd_req_ready (cdp2mcif_rd_req_ready) //|< w + ,.cdp2mcif_rd_req_pd (cdp2mcif_rd_req_pd ) //|> w + ,.cdp2mcif_wr_req_valid (cdp2mcif_wr_req_valid) //|> w + ,.cdp2mcif_wr_req_ready (cdp2mcif_wr_req_ready) //|< w + ,.cdp2mcif_wr_req_pd (cdp2mcif_wr_req_pd ) //|> w + ,.cdp_rdma2csb_resp_valid (cdp_rdma2csb_resp_valid) //|> w + ,.cdp_rdma2csb_resp_pd (cdp_rdma2csb_resp_pd[33:0]) //|> w + ,.csb2cdp_rdma_req_pvld (csb2cdp_rdma_req_pvld) //|< w + ,.csb2cdp_rdma_req_prdy (csb2cdp_rdma_req_prdy) //|> w + ,.csb2cdp_rdma_req_pd (csb2cdp_rdma_req_pd[62:0]) //|< w + ,.csb2cdp_req_pvld (csb2cdp_req_pvld) //|< w + ,.csb2cdp_req_prdy (csb2cdp_req_prdy) //|> w + ,.csb2cdp_req_pd (csb2cdp_req_pd[62:0]) //|< w + ,.mcif2cdp_rd_rsp_valid (mcif2cdp_rd_rsp_valid) //|< w + ,.mcif2cdp_rd_rsp_ready (mcif2cdp_rd_rsp_ready) //|> w + ,.mcif2cdp_rd_rsp_pd (mcif2cdp_rd_rsp_pd ) //|< w + ,.mcif2cdp_wr_rsp_complete (mcif2cdp_wr_rsp_complete) //|< w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Planar Data Processor // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_pdp u_NV_NVDLA_pdp ( + .dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) //|< w + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) //|< w + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o + ,.csb2pdp_rdma_req_pvld (csb2pdp_rdma_req_pvld) //|< w + ,.csb2pdp_rdma_req_prdy (csb2pdp_rdma_req_prdy) //|> w + ,.csb2pdp_rdma_req_pd (csb2pdp_rdma_req_pd[62:0]) //|< w + ,.csb2pdp_req_pvld (csb2pdp_req_pvld) //|< w + ,.csb2pdp_req_prdy (csb2pdp_req_prdy) //|> w + ,.csb2pdp_req_pd (csb2pdp_req_pd[62:0]) //|< w + ,.mcif2pdp_rd_rsp_valid (mcif2pdp_rd_rsp_valid) //|< w + ,.mcif2pdp_rd_rsp_ready (mcif2pdp_rd_rsp_ready) //|> w + ,.mcif2pdp_rd_rsp_pd (mcif2pdp_rd_rsp_pd ) //|< w + ,.mcif2pdp_wr_rsp_complete (mcif2pdp_wr_rsp_complete) //|< w + ,.pdp2csb_resp_valid (pdp2csb_resp_valid) //|> w + ,.pdp2csb_resp_pd (pdp2csb_resp_pd[33:0]) //|> w + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|> w + ,.pdp2mcif_rd_cdt_lat_fifo_pop (pdp2mcif_rd_cdt_lat_fifo_pop) //|> w + ,.pdp2mcif_rd_req_valid (pdp2mcif_rd_req_valid) //|> w + ,.pdp2mcif_rd_req_ready (pdp2mcif_rd_req_ready) //|< w + ,.pdp2mcif_rd_req_pd (pdp2mcif_rd_req_pd ) //|> w + ,.pdp2mcif_wr_req_valid (pdp2mcif_wr_req_valid) //|> w + ,.pdp2mcif_wr_req_ready (pdp2mcif_wr_req_ready) //|< w + ,.pdp2mcif_wr_req_pd (pdp2mcif_wr_req_pd ) //|> w + ,.pdp_rdma2csb_resp_valid (pdp_rdma2csb_resp_valid) //|> w + ,.pdp_rdma2csb_resp_pd (pdp_rdma2csb_resp_pd[33:0]) //|> w + ,.pwrbus_ram_pd (pwrbus_ram_pd[31:0]) //|< i + ,.sdp2pdp_valid (sdp2pdp_valid) //|< i + ,.sdp2pdp_ready (sdp2pdp_ready) //|> o + ,.sdp2pdp_pd (sdp2pdp_pd ) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O: Global Unit // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_glb u_NV_NVDLA_glb ( + .csb2glb_req_pvld (csb2glb_req_pvld) //|< w + ,.csb2glb_req_prdy (csb2glb_req_prdy) //|> w + ,.csb2glb_req_pd (csb2glb_req_pd[62:0]) //|< w + ,.glb2csb_resp_valid (glb2csb_resp_valid) //|> w + ,.glb2csb_resp_pd (glb2csb_resp_pd[33:0]) //|> w + ,.core_intr (core_intr) //|> o + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) //|< i + ,.cdp2glb_done_intr_pd (cdp2glb_done_intr_pd[1:0]) //|< w + ,.pdp2glb_done_intr_pd (pdp2glb_done_intr_pd[1:0]) //|< w + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) //|< i + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) //|< i + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) //|< i + ,.nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_falcon_clk (nvdla_falcon_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< o + ,.nvdla_falcon_rstn (nvdla_falcon_rstn) //|< w + ,.test_mode (test_mode) //|< i + ,.direct_reset_ (direct_reset_) //|< i + ); +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_partition_o diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_p.v b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_p.v new file mode 100644 index 0000000..f27fe9f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_p.v @@ -0,0 +1,219 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_p.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +`include "NV_HWACC_NVDLA_tick_defines.vh" +module NV_NVDLA_partition_p ( + cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,csb2sdp_req_pd //|< i + ,csb2sdp_req_pvld //|< i + ,direct_reset_ //|< i + ,dla_reset_rstn //|< i + ,global_clk_ovr_on //|< i + ,nvdla_clk_ovr_on //|< i + ,nvdla_core_clk //|< i + ,pwrbus_ram_pd //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_wr_rsp_complete //|< i + ,sdp2mcif_rd_req_ready //|< i + ,sdp2mcif_wr_req_ready //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_wr_req_pd //|> o + ,sdp2mcif_wr_req_valid //|> o + ,sdp2pdp_ready //|< i + ,test_mode //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cacc2sdp_ready //|> o + ,csb2sdp_rdma_req_prdy //|> o + ,csb2sdp_req_prdy //|> o + ,sdp2csb_resp_pd //|> o + ,sdp2csb_resp_valid //|> o + ,sdp2glb_done_intr_pd //|> o + ,sdp2pdp_pd //|> o + ,sdp2pdp_valid //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ); +// +// NV_NVDLA_partition_p_io.v +// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input cacc2sdp_valid; /* data valid */ +output cacc2sdp_ready; /* data return handshake */ +input [1*32+2-1:0] cacc2sdp_pd; +input csb2sdp_rdma_req_pvld; /* data valid */ +output csb2sdp_rdma_req_prdy; /* data return handshake */ +input [62:0] csb2sdp_rdma_req_pd; +input csb2sdp_req_pvld; /* data valid */ +output csb2sdp_req_prdy; /* data return handshake */ +input [62:0] csb2sdp_req_pd; +input [31:0] pwrbus_ram_pd; +output sdp2csb_resp_valid; /* data valid */ +output [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] sdp2glb_done_intr_pd; +output sdp_b2mcif_rd_cdt_lat_fifo_pop; +output sdp_b2mcif_rd_req_valid; /* data valid */ +input sdp_b2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] sdp_b2mcif_rd_req_pd; +input mcif2sdp_b_rd_rsp_valid; /* data valid */ +output mcif2sdp_b_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2sdp_b_rd_rsp_pd; +output sdp_n2mcif_rd_cdt_lat_fifo_pop; +output sdp_n2mcif_rd_req_valid; /* data valid */ +input sdp_n2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] sdp_n2mcif_rd_req_pd; +input mcif2sdp_n_rd_rsp_valid; /* data valid */ +output mcif2sdp_n_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2sdp_n_rd_rsp_pd; +output sdp2mcif_rd_cdt_lat_fifo_pop; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +input [64 +(64/8/8)-1:0] mcif2sdp_rd_rsp_pd; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +output [32 +14:0] sdp2mcif_rd_req_pd; +output sdp2mcif_wr_req_valid; +input sdp2mcif_wr_req_ready; +output [64 +(64/8/8):0] sdp2mcif_wr_req_pd; +input mcif2sdp_wr_rsp_complete; +output sdp2pdp_valid; +input sdp2pdp_ready; +output [1*8 -1:0] sdp2pdp_pd; +output sdp_rdma2csb_resp_valid; +output [33:0] sdp_rdma2csb_resp_pd; +//input la_r_clk; +//input larstn; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +wire dla_clk_ovr_on_sync; +wire global_clk_ovr_on_sync; +wire nvdla_core_rstn; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition P: Reset Syncer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_p_reset ( + .dla_reset_rstn (dla_reset_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_core_rstn) + ,.nvdla_clk (nvdla_core_clk) + ); +//////////////////////////////////////////////////////////////////////// +// Sync for SLCG +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (global_clk_ovr_on_sync) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition P: Single Data Processor // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sdp u_NV_NVDLA_sdp ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_partition_p diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_p.v.vcp b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_p.v.vcp new file mode 100644 index 0000000..f27fe9f --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_NVDLA_partition_p.v.vcp @@ -0,0 +1,219 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_partition_p.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +`include "NV_HWACC_NVDLA_tick_defines.vh" +module NV_NVDLA_partition_p ( + cacc2sdp_pd //|< i + ,cacc2sdp_valid //|< i + ,csb2sdp_rdma_req_pd //|< i + ,csb2sdp_rdma_req_pvld //|< i + ,csb2sdp_req_pd //|< i + ,csb2sdp_req_pvld //|< i + ,direct_reset_ //|< i + ,dla_reset_rstn //|< i + ,global_clk_ovr_on //|< i + ,nvdla_clk_ovr_on //|< i + ,nvdla_core_clk //|< i + ,pwrbus_ram_pd //|< i + ,sdp_b2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_b2mcif_rd_req_pd //|> o + ,sdp_b2mcif_rd_req_valid //|> o + ,sdp_b2mcif_rd_req_ready //|< i + ,mcif2sdp_b_rd_rsp_pd //|< i + ,mcif2sdp_b_rd_rsp_valid //|< i + ,mcif2sdp_b_rd_rsp_ready //|> o + ,sdp_n2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp_n2mcif_rd_req_pd //|> o + ,sdp_n2mcif_rd_req_valid //|> o + ,sdp_n2mcif_rd_req_ready //|< i + ,mcif2sdp_n_rd_rsp_pd //|< i + ,mcif2sdp_n_rd_rsp_valid //|< i + ,mcif2sdp_n_rd_rsp_ready //|> o + ,mcif2sdp_rd_rsp_pd //|< i + ,mcif2sdp_rd_rsp_valid //|< i + ,mcif2sdp_wr_rsp_complete //|< i + ,sdp2mcif_rd_req_ready //|< i + ,sdp2mcif_wr_req_ready //|< i + ,mcif2sdp_rd_rsp_ready //|> o + ,sdp2mcif_rd_cdt_lat_fifo_pop //|> o + ,sdp2mcif_rd_req_pd //|> o + ,sdp2mcif_rd_req_valid //|> o + ,sdp2mcif_wr_req_pd //|> o + ,sdp2mcif_wr_req_valid //|> o + ,sdp2pdp_ready //|< i + ,test_mode //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,cacc2sdp_ready //|> o + ,csb2sdp_rdma_req_prdy //|> o + ,csb2sdp_req_prdy //|> o + ,sdp2csb_resp_pd //|> o + ,sdp2csb_resp_valid //|> o + ,sdp2glb_done_intr_pd //|> o + ,sdp2pdp_pd //|> o + ,sdp2pdp_valid //|> o + ,sdp_rdma2csb_resp_pd //|> o + ,sdp_rdma2csb_resp_valid //|> o + ); +// +// NV_NVDLA_partition_p_io.v +// +input test_mode; +input direct_reset_; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input cacc2sdp_valid; /* data valid */ +output cacc2sdp_ready; /* data return handshake */ +input [1*32+2-1:0] cacc2sdp_pd; +input csb2sdp_rdma_req_pvld; /* data valid */ +output csb2sdp_rdma_req_prdy; /* data return handshake */ +input [62:0] csb2sdp_rdma_req_pd; +input csb2sdp_req_pvld; /* data valid */ +output csb2sdp_req_prdy; /* data return handshake */ +input [62:0] csb2sdp_req_pd; +input [31:0] pwrbus_ram_pd; +output sdp2csb_resp_valid; /* data valid */ +output [33:0] sdp2csb_resp_pd; /* pkt_id_width=1 pkt_widths=33,33 */ +output [1:0] sdp2glb_done_intr_pd; +output sdp_b2mcif_rd_cdt_lat_fifo_pop; +output sdp_b2mcif_rd_req_valid; /* data valid */ +input sdp_b2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] sdp_b2mcif_rd_req_pd; +input mcif2sdp_b_rd_rsp_valid; /* data valid */ +output mcif2sdp_b_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2sdp_b_rd_rsp_pd; +output sdp_n2mcif_rd_cdt_lat_fifo_pop; +output sdp_n2mcif_rd_req_valid; /* data valid */ +input sdp_n2mcif_rd_req_ready; /* data return handshake */ +output [32 +14:0] sdp_n2mcif_rd_req_pd; +input mcif2sdp_n_rd_rsp_valid; /* data valid */ +output mcif2sdp_n_rd_rsp_ready; /* data return handshake */ +input [64 +(64/8/8)-1:0] mcif2sdp_n_rd_rsp_pd; +output sdp2mcif_rd_cdt_lat_fifo_pop; +input mcif2sdp_rd_rsp_valid; +output mcif2sdp_rd_rsp_ready; +input [64 +(64/8/8)-1:0] mcif2sdp_rd_rsp_pd; +output sdp2mcif_rd_req_valid; +input sdp2mcif_rd_req_ready; +output [32 +14:0] sdp2mcif_rd_req_pd; +output sdp2mcif_wr_req_valid; +input sdp2mcif_wr_req_ready; +output [64 +(64/8/8):0] sdp2mcif_wr_req_pd; +input mcif2sdp_wr_rsp_complete; +output sdp2pdp_valid; +input sdp2pdp_ready; +output [1*8 -1:0] sdp2pdp_pd; +output sdp_rdma2csb_resp_valid; +output [33:0] sdp_rdma2csb_resp_pd; +//input la_r_clk; +//input larstn; +input nvdla_core_clk; +input dla_reset_rstn; +input nvdla_clk_ovr_on; +wire dla_clk_ovr_on_sync; +wire global_clk_ovr_on_sync; +wire nvdla_core_rstn; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition P: Reset Syncer // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_reset u_partition_p_reset ( + .dla_reset_rstn (dla_reset_rstn) + ,.direct_reset_ (direct_reset_) + ,.test_mode (test_mode) + ,.synced_rstn (nvdla_core_rstn) + ,.nvdla_clk (nvdla_core_clk) + ); +//////////////////////////////////////////////////////////////////////// +// Sync for SLCG +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sync3d u_dla_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.sync_i (nvdla_clk_ovr_on) + ,.sync_o (dla_clk_ovr_on_sync) + ); +NV_NVDLA_sync3d_s u_global_clk_ovr_on_sync ( + .clk (nvdla_core_clk) + ,.prst (nvdla_core_rstn) + ,.sync_i (global_clk_ovr_on) + ,.sync_o (global_clk_ovr_on_sync) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition P: Single Data Processor // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_sdp u_NV_NVDLA_sdp ( + .nvdla_core_clk (nvdla_core_clk) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.pwrbus_ram_pd (pwrbus_ram_pd) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd) + ,.dla_clk_ovr_on_sync (dla_clk_ovr_on_sync) + ,.global_clk_ovr_on_sync (global_clk_ovr_on_sync) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ); +//////////////////////////////////////////////////////////////////////// +// Dangles/Contenders report // +//////////////////////////////////////////////////////////////////////// +endmodule // NV_NVDLA_partition_p diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_nvdla.v b/designs/src/NVDLA/vmod/nvdla/top/NV_nvdla.v new file mode 100644 index 0000000..9b5cec5 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_nvdla.v @@ -0,0 +1,808 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_nvdla.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +`include "NV_HWACC_NVDLA_tick_defines.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_nvdla ( + dla_core_clk //|< i + ,dla_csb_clk //|< i + ,global_clk_ovr_on //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,dla_reset_rstn //|< i + ,direct_reset_ //|< i + ,test_mode //|< i + ,csb2nvdla_valid //|< i + ,csb2nvdla_ready //|> o + ,csb2nvdla_addr //|< i + ,csb2nvdla_wdat //|< i + ,csb2nvdla_write //|< i + ,csb2nvdla_nposted //|< i + ,nvdla2csb_valid //|> o + ,nvdla2csb_data //|> o + ,nvdla2csb_wr_complete //|> o + ,nvdla_core2dbb_aw_awvalid //|> o + ,nvdla_core2dbb_aw_awready //|< i + ,nvdla_core2dbb_aw_awid //|> o + ,nvdla_core2dbb_aw_awlen //|> o + ,nvdla_core2dbb_aw_awaddr //|> o + ,nvdla_core2dbb_w_wvalid //|> o + ,nvdla_core2dbb_w_wready //|< i + ,nvdla_core2dbb_w_wdata //|> o + ,nvdla_core2dbb_w_wstrb //|> o + ,nvdla_core2dbb_w_wlast //|> o + ,nvdla_core2dbb_b_bvalid //|< i + ,nvdla_core2dbb_b_bready //|> o + ,nvdla_core2dbb_b_bid //|< i + ,nvdla_core2dbb_ar_arvalid //|> o + ,nvdla_core2dbb_ar_arready //|< i + ,nvdla_core2dbb_ar_arid //|> o + ,nvdla_core2dbb_ar_arlen //|> o + ,nvdla_core2dbb_ar_araddr //|> o + ,nvdla_core2dbb_r_rvalid //|< i + ,nvdla_core2dbb_r_rready //|> o + ,nvdla_core2dbb_r_rid //|< i + ,nvdla_core2dbb_r_rlast //|< i + ,nvdla_core2dbb_r_rdata //|< i + ,dla_intr //|> o + ,nvdla_pwrbus_ram_c_pd //|< i + ,nvdla_pwrbus_ram_ma_pd //|< i * + ,nvdla_pwrbus_ram_mb_pd //|< i * + ,nvdla_pwrbus_ram_p_pd //|< i + ,nvdla_pwrbus_ram_o_pd //|< i + ,nvdla_pwrbus_ram_a_pd //|< i + ); +//////////////////////////////////////////////////////////////////////////////// +input dla_core_clk; +input dla_csb_clk; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input dla_reset_rstn; +input direct_reset_; +input test_mode; +//csb +input csb2nvdla_valid; +output csb2nvdla_ready; +input [15:0] csb2nvdla_addr; +input [31:0] csb2nvdla_wdat; +input csb2nvdla_write; +input csb2nvdla_nposted; +output nvdla2csb_valid; +output [31:0] nvdla2csb_data; +output nvdla2csb_wr_complete; +/////////////// +output nvdla_core2dbb_aw_awvalid; +input nvdla_core2dbb_aw_awready; +output [7:0] nvdla_core2dbb_aw_awid; +output [3:0] nvdla_core2dbb_aw_awlen; +output [32 -1:0] nvdla_core2dbb_aw_awaddr; +output nvdla_core2dbb_w_wvalid; +input nvdla_core2dbb_w_wready; +output [64 -1:0] nvdla_core2dbb_w_wdata; +output [64/8-1:0] nvdla_core2dbb_w_wstrb; +output nvdla_core2dbb_w_wlast; +output nvdla_core2dbb_ar_arvalid; +input nvdla_core2dbb_ar_arready; +output [7:0] nvdla_core2dbb_ar_arid; +output [3:0] nvdla_core2dbb_ar_arlen; +output [32 -1:0] nvdla_core2dbb_ar_araddr; +input nvdla_core2dbb_b_bvalid; +output nvdla_core2dbb_b_bready; +input [7:0] nvdla_core2dbb_b_bid; +input nvdla_core2dbb_r_rvalid; +output nvdla_core2dbb_r_rready; +input [7:0] nvdla_core2dbb_r_rid; +input nvdla_core2dbb_r_rlast; +input [64 -1:0] nvdla_core2dbb_r_rdata; +output dla_intr; +input [31:0] nvdla_pwrbus_ram_c_pd; +input [31:0] nvdla_pwrbus_ram_ma_pd; +input [31:0] nvdla_pwrbus_ram_mb_pd; +input [31:0] nvdla_pwrbus_ram_p_pd; +input [31:0] nvdla_pwrbus_ram_o_pd; +input [31:0] nvdla_pwrbus_ram_a_pd; +//////////////////////////////////////////////////////////////////////////////// +wire [2:0] accu2sc_credit_size; +wire accu2sc_credit_vld; +wire [33:0] cacc2csb_resp_pd; +wire cacc2csb_resp_valid; +wire [1:0] cacc2glb_done_intr_pd; +wire [1*32+2-1:0] cacc2sdp_pd; +wire cacc2sdp_ready; +wire cacc2sdp_valid; +wire [33:0] cdma2csb_resp_pd; +wire cdma2csb_resp_valid; +wire [1:0] cdma_dat2glb_done_intr_pd; +wire [1:0] cdma_wt2glb_done_intr_pd; +wire [33:0] cmac_a2csb_resp_pd; +wire cmac_a2csb_resp_valid; +wire [33:0] cmac_b2csb_resp_pd; +wire cmac_b2csb_resp_valid; +wire [62:0] csb2cdma_req_pd; +wire csb2cdma_req_prdy; +wire csb2cdma_req_pvld; +wire [62:0] csb2cacc_req_pd; +wire csb2cacc_req_prdy; +wire csb2cacc_req_pvld; +wire [62:0] csb2cmac_a_req_pd; +wire csb2cmac_a_req_prdy; +wire csb2cmac_a_req_pvld; +wire [62:0] csb2cmac_b_req_pd; +wire csb2cmac_b_req_prdy; +wire csb2cmac_b_req_pvld; +wire [62:0] csb2csc_req_pd; +wire csb2csc_req_prdy; +wire csb2csc_req_pvld; +wire [62:0] csb2sdp_rdma_req_pd; +wire csb2sdp_rdma_req_prdy; +wire csb2sdp_rdma_req_pvld; +wire [62:0] csb2sdp_req_pd; +wire csb2sdp_req_prdy; +wire csb2sdp_req_pvld; +wire [33:0] csc2csb_resp_pd; +wire csc2csb_resp_valid; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: wire [19 -1:0] mac_a2accu_data${i}; +//: wire [19 -1:0] mac_b2accu_data${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [19 -1:0] mac_a2accu_data0; +wire [19 -1:0] mac_b2accu_data0; + +wire [19 -1:0] mac_a2accu_data1; +wire [19 -1:0] mac_b2accu_data1; + +wire [19 -1:0] mac_a2accu_data2; +wire [19 -1:0] mac_b2accu_data2; + +wire [19 -1:0] mac_a2accu_data3; +wire [19 -1:0] mac_b2accu_data3; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8/2-1:0] mac_a2accu_mask; +wire mac_a2accu_mode; +wire [8:0] mac_a2accu_pd; +wire mac_a2accu_pvld; +wire [8/2-1:0] mac_b2accu_mask; +wire mac_b2accu_mode; +wire [8:0] mac_b2accu_pd; +wire mac_b2accu_pvld; +wire [32 +14:0] cdma_dat2mcif_rd_req_pd; +wire cdma_dat2mcif_rd_req_ready; +wire cdma_dat2mcif_rd_req_valid; +wire [32 +14:0] cdma_wt2mcif_rd_req_pd; +wire cdma_wt2mcif_rd_req_ready; +wire cdma_wt2mcif_rd_req_valid; +wire [64 +(64/8/8)-1:0] mcif2cdma_dat_rd_rsp_pd; +wire mcif2cdma_dat_rd_rsp_ready; +wire mcif2cdma_dat_rd_rsp_valid; +wire [64 +(64/8/8)-1:0] mcif2cdma_wt_rd_rsp_pd; +wire mcif2cdma_wt_rd_rsp_ready; +wire mcif2cdma_wt_rd_rsp_valid; + wire [64 +(64/8/8)-1:0] mcif2sdp_b_rd_rsp_pd; + wire mcif2sdp_b_rd_rsp_ready; + wire mcif2sdp_b_rd_rsp_valid; + wire sdp_b2mcif_rd_cdt_lat_fifo_pop; + wire [32 +14:0] sdp_b2mcif_rd_req_pd; + wire sdp_b2mcif_rd_req_ready; + wire sdp_b2mcif_rd_req_valid; + wire [64 +(64/8/8)-1:0] mcif2sdp_n_rd_rsp_pd; + wire mcif2sdp_n_rd_rsp_ready; + wire mcif2sdp_n_rd_rsp_valid; + wire sdp_n2mcif_rd_cdt_lat_fifo_pop; + wire [32 +14:0] sdp_n2mcif_rd_req_pd; + wire sdp_n2mcif_rd_req_ready; + wire sdp_n2mcif_rd_req_valid; +wire [64 +(64/8/8)-1:0] mcif2sdp_rd_rsp_pd; +wire mcif2sdp_rd_rsp_ready; +wire mcif2sdp_rd_rsp_valid; +wire mcif2sdp_wr_rsp_complete; +wire sdp2mcif_rd_cdt_lat_fifo_pop; +wire [32 +14:0] sdp2mcif_rd_req_pd; +wire sdp2mcif_rd_req_ready; +wire sdp2mcif_rd_req_valid; +wire [64 +(64/8/8):0] sdp2mcif_wr_req_pd; +wire sdp2mcif_wr_req_ready; +wire sdp2mcif_wr_req_valid; +wire [33:0] sdp2csb_resp_pd; +wire sdp2csb_resp_valid; +wire [1:0] sdp2glb_done_intr_pd; +wire [1*8 -1:0] sdp2pdp_pd; +wire sdp2pdp_ready; +wire sdp2pdp_valid; +wire [33:0] sdp_rdma2csb_resp_pd; +wire sdp_rdma2csb_resp_valid; +wire nvdla_clk_ovr_on; +wire nvdla_core_rstn; +//: my $kk=8 -1; +//: foreach my $i (0..${kk}) { +//: print qq( +//: wire [8 -1:0] sc2mac_dat_a_data${i}; +//: wire [8 -1:0] sc2mac_dat_b_data${i}; +//: wire [8 -1:0] sc2mac_wt_a_data${i}; +//: wire [8 -1:0] sc2mac_wt_b_data${i}; +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +wire [8 -1:0] sc2mac_dat_a_data0; +wire [8 -1:0] sc2mac_dat_b_data0; +wire [8 -1:0] sc2mac_wt_a_data0; +wire [8 -1:0] sc2mac_wt_b_data0; + +wire [8 -1:0] sc2mac_dat_a_data1; +wire [8 -1:0] sc2mac_dat_b_data1; +wire [8 -1:0] sc2mac_wt_a_data1; +wire [8 -1:0] sc2mac_wt_b_data1; + +wire [8 -1:0] sc2mac_dat_a_data2; +wire [8 -1:0] sc2mac_dat_b_data2; +wire [8 -1:0] sc2mac_wt_a_data2; +wire [8 -1:0] sc2mac_wt_b_data2; + +wire [8 -1:0] sc2mac_dat_a_data3; +wire [8 -1:0] sc2mac_dat_b_data3; +wire [8 -1:0] sc2mac_wt_a_data3; +wire [8 -1:0] sc2mac_wt_b_data3; + +wire [8 -1:0] sc2mac_dat_a_data4; +wire [8 -1:0] sc2mac_dat_b_data4; +wire [8 -1:0] sc2mac_wt_a_data4; +wire [8 -1:0] sc2mac_wt_b_data4; + +wire [8 -1:0] sc2mac_dat_a_data5; +wire [8 -1:0] sc2mac_dat_b_data5; +wire [8 -1:0] sc2mac_wt_a_data5; +wire [8 -1:0] sc2mac_wt_b_data5; + +wire [8 -1:0] sc2mac_dat_a_data6; +wire [8 -1:0] sc2mac_dat_b_data6; +wire [8 -1:0] sc2mac_wt_a_data6; +wire [8 -1:0] sc2mac_wt_b_data6; + +wire [8 -1:0] sc2mac_dat_a_data7; +wire [8 -1:0] sc2mac_dat_b_data7; +wire [8 -1:0] sc2mac_wt_a_data7; +wire [8 -1:0] sc2mac_wt_b_data7; + +//| eperl: generated_end (DO NOT EDIT ABOVE) +wire [8 -1:0] sc2mac_dat_a_mask; +wire [8:0] sc2mac_dat_a_pd; +wire sc2mac_dat_a_pvld; +wire [8 -1:0] sc2mac_dat_b_mask; +wire [8:0] sc2mac_dat_b_pd; +wire sc2mac_dat_b_pvld; +wire [8 -1:0] sc2mac_wt_a_mask; +wire sc2mac_wt_a_pvld; +wire [8/2-1:0] sc2mac_wt_a_sel; +wire [8 -1:0] sc2mac_wt_b_mask; +wire sc2mac_wt_b_pvld; +wire [8/2-1:0] sc2mac_wt_b_sel; +//////////////////////////////////////////////////////////////////////////////// + assign nvdla_core2cvsram_aw_awvalid = 1'b0; + assign nvdla_core2cvsram_w_wvalid = 1'b0; + assign nvdla_core2cvsram_w_wlast = 1'b0; + assign nvdla_core2cvsram_b_bready = 1'b1; + assign nvdla_core2cvsram_r_rready = 1'b1; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_o u_partition_o ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd[33:0]) + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd[62:0]) + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd[33:0]) + ,.cmac_b2csb_resp_valid (cmac_b2csb_resp_valid) + ,.cmac_b2csb_resp_pd (cmac_b2csb_resp_pd[33:0]) + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd[62:0]) + ,.csb2cmac_b_req_pvld (csb2cmac_b_req_pvld) + ,.csb2cmac_b_req_prdy (csb2cmac_b_req_prdy) + ,.csb2cmac_b_req_pd (csb2cmac_b_req_pd[62:0]) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd[33:0]) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd[62:0]) + ,.csb2csc_req_pvld (csb2csc_req_pvld) + ,.csb2csc_req_prdy (csb2csc_req_prdy) + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) + ,.csb2nvdla_valid (csb2nvdla_valid) + ,.csb2nvdla_ready (csb2nvdla_ready) + ,.csb2nvdla_addr (csb2nvdla_addr[15:0]) + ,.csb2nvdla_wdat (csb2nvdla_wdat[31:0]) + ,.csb2nvdla_write (csb2nvdla_write) + ,.csb2nvdla_nposted (csb2nvdla_nposted) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd[62:0]) + ,.csc2csb_resp_valid (csc2csb_resp_valid) + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) + ,.mcif2noc_axi_ar_arvalid (nvdla_core2dbb_ar_arvalid) + ,.mcif2noc_axi_ar_arready (nvdla_core2dbb_ar_arready) + ,.mcif2noc_axi_ar_arid (nvdla_core2dbb_ar_arid[7:0]) + ,.mcif2noc_axi_ar_arlen (nvdla_core2dbb_ar_arlen[3:0]) + ,.mcif2noc_axi_ar_araddr (nvdla_core2dbb_ar_araddr) + ,.mcif2noc_axi_aw_awvalid (nvdla_core2dbb_aw_awvalid) + ,.mcif2noc_axi_aw_awready (nvdla_core2dbb_aw_awready) + ,.mcif2noc_axi_aw_awid (nvdla_core2dbb_aw_awid[7:0]) + ,.mcif2noc_axi_aw_awlen (nvdla_core2dbb_aw_awlen[3:0]) + ,.mcif2noc_axi_aw_awaddr (nvdla_core2dbb_aw_awaddr) + ,.mcif2noc_axi_w_wvalid (nvdla_core2dbb_w_wvalid) + ,.mcif2noc_axi_w_wready (nvdla_core2dbb_w_wready) + ,.mcif2noc_axi_w_wdata (nvdla_core2dbb_w_wdata) + ,.mcif2noc_axi_w_wstrb (nvdla_core2dbb_w_wstrb) + ,.mcif2noc_axi_w_wlast (nvdla_core2dbb_w_wlast) + ,.noc2mcif_axi_b_bvalid (nvdla_core2dbb_b_bvalid) + ,.noc2mcif_axi_b_bready (nvdla_core2dbb_b_bready) + ,.noc2mcif_axi_b_bid (nvdla_core2dbb_b_bid[7:0]) + ,.noc2mcif_axi_r_rvalid (nvdla_core2dbb_r_rvalid) + ,.noc2mcif_axi_r_rready (nvdla_core2dbb_r_rready) + ,.noc2mcif_axi_r_rid (nvdla_core2dbb_r_rid[7:0]) + ,.noc2mcif_axi_r_rlast (nvdla_core2dbb_r_rlast) + ,.noc2mcif_axi_r_rdata (nvdla_core2dbb_r_rdata) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd) + ,.nvdla2csb_valid (nvdla2csb_valid) + ,.nvdla2csb_data (nvdla2csb_data[31:0]) + ,.nvdla2csb_wr_complete (nvdla2csb_wr_complete) + ,.core_intr (dla_intr) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_o_pd[31:0]) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd[33:0]) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (dla_reset_rstn) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.nvdla_falcon_clk (dla_csb_clk) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_c u_partition_c ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.accu2sc_credit_vld (accu2sc_credit_vld) + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd[33:0]) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd[62:0]) + ,.csb2csc_req_pvld (csb2csc_req_pvld) + ,.csb2csc_req_prdy (csb2csc_req_prdy) + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) + ,.csc2csb_resp_valid (csc2csb_resp_valid) + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_c_pd[31:0]) + ,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld) + ,.sc2mac_dat_a_mask (sc2mac_dat_a_mask[8 -1:0]) +//: my $kk=8 -1; +//: foreach my $i (0..${kk}){ +//: print qq( +//: ,.sc2mac_dat_a_data${i} (sc2mac_dat_a_data${i}) +//: ,.sc2mac_dat_b_data${i} (sc2mac_dat_b_data${i}) +//: ,.sc2mac_wt_a_data${i} (sc2mac_wt_a_data${i}) +//: ,.sc2mac_wt_b_data${i} (sc2mac_wt_b_data${i}) +//: ); +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_a_data0 (sc2mac_dat_a_data0) +,.sc2mac_dat_b_data0 (sc2mac_dat_b_data0) +,.sc2mac_wt_a_data0 (sc2mac_wt_a_data0) +,.sc2mac_wt_b_data0 (sc2mac_wt_b_data0) + +,.sc2mac_dat_a_data1 (sc2mac_dat_a_data1) +,.sc2mac_dat_b_data1 (sc2mac_dat_b_data1) +,.sc2mac_wt_a_data1 (sc2mac_wt_a_data1) +,.sc2mac_wt_b_data1 (sc2mac_wt_b_data1) + +,.sc2mac_dat_a_data2 (sc2mac_dat_a_data2) +,.sc2mac_dat_b_data2 (sc2mac_dat_b_data2) +,.sc2mac_wt_a_data2 (sc2mac_wt_a_data2) +,.sc2mac_wt_b_data2 (sc2mac_wt_b_data2) + +,.sc2mac_dat_a_data3 (sc2mac_dat_a_data3) +,.sc2mac_dat_b_data3 (sc2mac_dat_b_data3) +,.sc2mac_wt_a_data3 (sc2mac_wt_a_data3) +,.sc2mac_wt_b_data3 (sc2mac_wt_b_data3) + +,.sc2mac_dat_a_data4 (sc2mac_dat_a_data4) +,.sc2mac_dat_b_data4 (sc2mac_dat_b_data4) +,.sc2mac_wt_a_data4 (sc2mac_wt_a_data4) +,.sc2mac_wt_b_data4 (sc2mac_wt_b_data4) + +,.sc2mac_dat_a_data5 (sc2mac_dat_a_data5) +,.sc2mac_dat_b_data5 (sc2mac_dat_b_data5) +,.sc2mac_wt_a_data5 (sc2mac_wt_a_data5) +,.sc2mac_wt_b_data5 (sc2mac_wt_b_data5) + +,.sc2mac_dat_a_data6 (sc2mac_dat_a_data6) +,.sc2mac_dat_b_data6 (sc2mac_dat_b_data6) +,.sc2mac_wt_a_data6 (sc2mac_wt_a_data6) +,.sc2mac_wt_b_data6 (sc2mac_wt_b_data6) + +,.sc2mac_dat_a_data7 (sc2mac_dat_a_data7) +,.sc2mac_dat_b_data7 (sc2mac_dat_b_data7) +,.sc2mac_wt_a_data7 (sc2mac_wt_a_data7) +,.sc2mac_wt_b_data7 (sc2mac_wt_b_data7) + +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_a_pd (sc2mac_dat_a_pd[8:0]) + ,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld) + ,.sc2mac_dat_b_mask (sc2mac_dat_b_mask[8 -1:0]) + ,.sc2mac_dat_b_pd (sc2mac_dat_b_pd[8:0]) + ,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld) + ,.sc2mac_wt_a_mask (sc2mac_wt_a_mask[8 -1:0]) + ,.sc2mac_wt_a_sel (sc2mac_wt_a_sel[8/2-1:0]) + ,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld) + ,.sc2mac_wt_b_mask (sc2mac_wt_b_mask[8 -1:0]) + ,.sc2mac_wt_b_sel (sc2mac_wt_b_sel[8/2-1:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//&Connect /nvdla_obs/ nvdla_pwrpart_c_obs; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition MA // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_m u_partition_ma ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< w + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> w + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< w + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> w + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> w + ,.sc2mac_wt_pvld (sc2mac_wt_a_pvld) //|< w + ,.sc2mac_wt_mask (sc2mac_wt_a_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_a_data${i}) //|< w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_data0 (sc2mac_wt_a_data0) //|< w +,.sc2mac_wt_data1 (sc2mac_wt_a_data1) //|< w +,.sc2mac_wt_data2 (sc2mac_wt_a_data2) //|< w +,.sc2mac_wt_data3 (sc2mac_wt_a_data3) //|< w +,.sc2mac_wt_data4 (sc2mac_wt_a_data4) //|< w +,.sc2mac_wt_data5 (sc2mac_wt_a_data5) //|< w +,.sc2mac_wt_data6 (sc2mac_wt_a_data6) //|< w +,.sc2mac_wt_data7 (sc2mac_wt_a_data7) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_sel (sc2mac_wt_a_sel) //|< w + ,.sc2mac_dat_pvld (sc2mac_dat_a_pvld) //|< w + ,.sc2mac_dat_mask (sc2mac_dat_a_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_a_data${i}) //|< w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_data0 (sc2mac_dat_a_data0) //|< w +,.sc2mac_dat_data1 (sc2mac_dat_a_data1) //|< w +,.sc2mac_dat_data2 (sc2mac_dat_a_data2) //|< w +,.sc2mac_dat_data3 (sc2mac_dat_a_data3) //|< w +,.sc2mac_dat_data4 (sc2mac_dat_a_data4) //|< w +,.sc2mac_dat_data5 (sc2mac_dat_a_data5) //|< w +,.sc2mac_dat_data6 (sc2mac_dat_a_data6) //|< w +,.sc2mac_dat_data7 (sc2mac_dat_a_data7) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_pd (sc2mac_dat_a_pd) //|< w + ,.mac2accu_pvld (mac_a2accu_pvld) //|> w + ,.mac2accu_mask (mac_a2accu_mask) //|> w + ,.mac2accu_mode (mac_a2accu_mode) //|> w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac_a2accu_data${i}) //|> w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac2accu_data0 (mac_a2accu_data0) //|> w +,.mac2accu_data1 (mac_a2accu_data1) //|> w +,.mac2accu_data2 (mac_a2accu_data2) //|> w +,.mac2accu_data3 (mac_a2accu_data3) //|> w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac2accu_pd (mac_a2accu_pd) //|> w + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition MB // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_m u_partition_mb ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.csb2cmac_a_req_pvld (csb2cmac_b_req_pvld) //|< w + ,.csb2cmac_a_req_prdy (csb2cmac_b_req_prdy) //|> w + ,.csb2cmac_a_req_pd (csb2cmac_b_req_pd) //|< w + ,.cmac_a2csb_resp_valid (cmac_b2csb_resp_valid) //|> w + ,.cmac_a2csb_resp_pd (cmac_b2csb_resp_pd) //|> w + ,.sc2mac_wt_pvld (sc2mac_wt_b_pvld) //|< w + ,.sc2mac_wt_mask (sc2mac_wt_b_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_b_data${i}) //|< w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_wt_data0 (sc2mac_wt_b_data0) //|< w +,.sc2mac_wt_data1 (sc2mac_wt_b_data1) //|< w +,.sc2mac_wt_data2 (sc2mac_wt_b_data2) //|< w +,.sc2mac_wt_data3 (sc2mac_wt_b_data3) //|< w +,.sc2mac_wt_data4 (sc2mac_wt_b_data4) //|< w +,.sc2mac_wt_data5 (sc2mac_wt_b_data5) //|< w +,.sc2mac_wt_data6 (sc2mac_wt_b_data6) //|< w +,.sc2mac_wt_data7 (sc2mac_wt_b_data7) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_wt_sel (sc2mac_wt_b_sel) //|< w + ,.sc2mac_dat_pvld (sc2mac_dat_b_pvld) //|< w + ,.sc2mac_dat_mask (sc2mac_dat_b_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_b_data${i}) //|< w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.sc2mac_dat_data0 (sc2mac_dat_b_data0) //|< w +,.sc2mac_dat_data1 (sc2mac_dat_b_data1) //|< w +,.sc2mac_dat_data2 (sc2mac_dat_b_data2) //|< w +,.sc2mac_dat_data3 (sc2mac_dat_b_data3) //|< w +,.sc2mac_dat_data4 (sc2mac_dat_b_data4) //|< w +,.sc2mac_dat_data5 (sc2mac_dat_b_data5) //|< w +,.sc2mac_dat_data6 (sc2mac_dat_b_data6) //|< w +,.sc2mac_dat_data7 (sc2mac_dat_b_data7) //|< w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.sc2mac_dat_pd (sc2mac_dat_b_pd) //|< w + ,.mac2accu_pvld (mac_b2accu_pvld) //|> w + ,.mac2accu_mask (mac_b2accu_mask) //|> w + ,.mac2accu_mode (mac_b2accu_mode) //|> w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac_b2accu_data${i}) //|> w ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac2accu_data0 (mac_b2accu_data0) //|> w +,.mac2accu_data1 (mac_b2accu_data1) //|> w +,.mac2accu_data2 (mac_b2accu_data2) //|> w +,.mac2accu_data3 (mac_b2accu_data3) //|> w +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac2accu_pd (mac_b2accu_pd) //|> w + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition A // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_a u_partition_a ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.accu2sc_credit_vld (accu2sc_credit_vld) + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd[62:0]) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd[33:0]) + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.mac_a2accu_pvld (mac_a2accu_pvld) + ,.mac_a2accu_mask (mac_a2accu_mask[8/2-1:0]) + ,.mac_a2accu_mode (mac_a2accu_mode) +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_a2accu_data${i} (mac_a2accu_data${i}[19 -1:0]) ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac_a2accu_data0 (mac_a2accu_data0[19 -1:0]) +,.mac_a2accu_data1 (mac_a2accu_data1[19 -1:0]) +,.mac_a2accu_data2 (mac_a2accu_data2[19 -1:0]) +,.mac_a2accu_data3 (mac_a2accu_data3[19 -1:0]) +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac_a2accu_pd (mac_a2accu_pd[8:0]) + ,.mac_b2accu_pvld (mac_b2accu_pvld) + ,.mac_b2accu_mask (mac_b2accu_mask[8/2-1:0]) + ,.mac_b2accu_mode (mac_b2accu_mode) +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_b2accu_data${i} (mac_b2accu_data${i}[19 -1:0]) ) +//: } +//| eperl: generated_beg (DO NOT EDIT BELOW) + +,.mac_b2accu_data0 (mac_b2accu_data0[19 -1:0]) +,.mac_b2accu_data1 (mac_b2accu_data1[19 -1:0]) +,.mac_b2accu_data2 (mac_b2accu_data2[19 -1:0]) +,.mac_b2accu_data3 (mac_b2accu_data3[19 -1:0]) +//| eperl: generated_end (DO NOT EDIT ABOVE) + ,.mac_b2accu_pd (mac_b2accu_pd[8:0]) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_a_pd[31:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition P // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_p u_partition_p ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd[62:0]) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd ) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd ) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd ) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd ) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd ) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_p_pd[31:0]) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd[33:0]) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd ) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd ) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd ) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +endmodule // NV_nvdla diff --git a/designs/src/NVDLA/vmod/nvdla/top/NV_nvdla.v.vcp b/designs/src/NVDLA/vmod/nvdla/top/NV_nvdla.v.vcp new file mode 100644 index 0000000..57b45c8 --- /dev/null +++ b/designs/src/NVDLA/vmod/nvdla/top/NV_nvdla.v.vcp @@ -0,0 +1,635 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_nvdla.v +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_define.h +/////////////////////////////////////////////////// +// +`include "NV_HWACC_NVDLA_tick_defines.vh" +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CMAC.h +`define DESIGNWARE_NOEXIST 1 +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CSC.h + //entry bits + //atomC + //in bytes, entry/8 + //CSC_ENTRY_HEX/2 + //CSC_ENTRY_HEX/4 + //CSC_ENTRY_HEX-1 + //atomK + //atomK + //atomK*2 + `define CC_ATOMC_DIV_ATOMK_EQUAL_1 +//image stripe keep 2*atomK +//batch keep 1 +module NV_nvdla ( + dla_core_clk //|< i + ,dla_csb_clk //|< i + ,global_clk_ovr_on //|< i + ,tmc2slcg_disable_clock_gating //|< i + ,dla_reset_rstn //|< i + ,direct_reset_ //|< i + ,test_mode //|< i + ,csb2nvdla_valid //|< i + ,csb2nvdla_ready //|> o + ,csb2nvdla_addr //|< i + ,csb2nvdla_wdat //|< i + ,csb2nvdla_write //|< i + ,csb2nvdla_nposted //|< i + ,nvdla2csb_valid //|> o + ,nvdla2csb_data //|> o + ,nvdla2csb_wr_complete //|> o + ,nvdla_core2dbb_aw_awvalid //|> o + ,nvdla_core2dbb_aw_awready //|< i + ,nvdla_core2dbb_aw_awid //|> o + ,nvdla_core2dbb_aw_awlen //|> o + ,nvdla_core2dbb_aw_awaddr //|> o + ,nvdla_core2dbb_w_wvalid //|> o + ,nvdla_core2dbb_w_wready //|< i + ,nvdla_core2dbb_w_wdata //|> o + ,nvdla_core2dbb_w_wstrb //|> o + ,nvdla_core2dbb_w_wlast //|> o + ,nvdla_core2dbb_b_bvalid //|< i + ,nvdla_core2dbb_b_bready //|> o + ,nvdla_core2dbb_b_bid //|< i + ,nvdla_core2dbb_ar_arvalid //|> o + ,nvdla_core2dbb_ar_arready //|< i + ,nvdla_core2dbb_ar_arid //|> o + ,nvdla_core2dbb_ar_arlen //|> o + ,nvdla_core2dbb_ar_araddr //|> o + ,nvdla_core2dbb_r_rvalid //|< i + ,nvdla_core2dbb_r_rready //|> o + ,nvdla_core2dbb_r_rid //|< i + ,nvdla_core2dbb_r_rlast //|< i + ,nvdla_core2dbb_r_rdata //|< i + ,dla_intr //|> o + ,nvdla_pwrbus_ram_c_pd //|< i + ,nvdla_pwrbus_ram_ma_pd //|< i * + ,nvdla_pwrbus_ram_mb_pd //|< i * + ,nvdla_pwrbus_ram_p_pd //|< i + ,nvdla_pwrbus_ram_o_pd //|< i + ,nvdla_pwrbus_ram_a_pd //|< i + ); +//////////////////////////////////////////////////////////////////////////////// +input dla_core_clk; +input dla_csb_clk; +input global_clk_ovr_on; +input tmc2slcg_disable_clock_gating; +input dla_reset_rstn; +input direct_reset_; +input test_mode; +//csb +input csb2nvdla_valid; +output csb2nvdla_ready; +input [15:0] csb2nvdla_addr; +input [31:0] csb2nvdla_wdat; +input csb2nvdla_write; +input csb2nvdla_nposted; +output nvdla2csb_valid; +output [31:0] nvdla2csb_data; +output nvdla2csb_wr_complete; +/////////////// +output nvdla_core2dbb_aw_awvalid; +input nvdla_core2dbb_aw_awready; +output [7:0] nvdla_core2dbb_aw_awid; +output [3:0] nvdla_core2dbb_aw_awlen; +output [32 -1:0] nvdla_core2dbb_aw_awaddr; +output nvdla_core2dbb_w_wvalid; +input nvdla_core2dbb_w_wready; +output [64 -1:0] nvdla_core2dbb_w_wdata; +output [64/8-1:0] nvdla_core2dbb_w_wstrb; +output nvdla_core2dbb_w_wlast; +output nvdla_core2dbb_ar_arvalid; +input nvdla_core2dbb_ar_arready; +output [7:0] nvdla_core2dbb_ar_arid; +output [3:0] nvdla_core2dbb_ar_arlen; +output [32 -1:0] nvdla_core2dbb_ar_araddr; +input nvdla_core2dbb_b_bvalid; +output nvdla_core2dbb_b_bready; +input [7:0] nvdla_core2dbb_b_bid; +input nvdla_core2dbb_r_rvalid; +output nvdla_core2dbb_r_rready; +input [7:0] nvdla_core2dbb_r_rid; +input nvdla_core2dbb_r_rlast; +input [64 -1:0] nvdla_core2dbb_r_rdata; +output dla_intr; +input [31:0] nvdla_pwrbus_ram_c_pd; +input [31:0] nvdla_pwrbus_ram_ma_pd; +input [31:0] nvdla_pwrbus_ram_mb_pd; +input [31:0] nvdla_pwrbus_ram_p_pd; +input [31:0] nvdla_pwrbus_ram_o_pd; +input [31:0] nvdla_pwrbus_ram_a_pd; +//////////////////////////////////////////////////////////////////////////////// +wire [2:0] accu2sc_credit_size; +wire accu2sc_credit_vld; +wire [33:0] cacc2csb_resp_pd; +wire cacc2csb_resp_valid; +wire [1:0] cacc2glb_done_intr_pd; +wire [1*32+2-1:0] cacc2sdp_pd; +wire cacc2sdp_ready; +wire cacc2sdp_valid; +wire [33:0] cdma2csb_resp_pd; +wire cdma2csb_resp_valid; +wire [1:0] cdma_dat2glb_done_intr_pd; +wire [1:0] cdma_wt2glb_done_intr_pd; +wire [33:0] cmac_a2csb_resp_pd; +wire cmac_a2csb_resp_valid; +wire [33:0] cmac_b2csb_resp_pd; +wire cmac_b2csb_resp_valid; +wire [62:0] csb2cdma_req_pd; +wire csb2cdma_req_prdy; +wire csb2cdma_req_pvld; +wire [62:0] csb2cacc_req_pd; +wire csb2cacc_req_prdy; +wire csb2cacc_req_pvld; +wire [62:0] csb2cmac_a_req_pd; +wire csb2cmac_a_req_prdy; +wire csb2cmac_a_req_pvld; +wire [62:0] csb2cmac_b_req_pd; +wire csb2cmac_b_req_prdy; +wire csb2cmac_b_req_pvld; +wire [62:0] csb2csc_req_pd; +wire csb2csc_req_prdy; +wire csb2csc_req_pvld; +wire [62:0] csb2sdp_rdma_req_pd; +wire csb2sdp_rdma_req_prdy; +wire csb2sdp_rdma_req_pvld; +wire [62:0] csb2sdp_req_pd; +wire csb2sdp_req_prdy; +wire csb2sdp_req_pvld; +wire [33:0] csc2csb_resp_pd; +wire csc2csb_resp_valid; +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: wire [19 -1:0] mac_a2accu_data${i}; +//: wire [19 -1:0] mac_b2accu_data${i}; +//: ); +//: } +wire [8/2-1:0] mac_a2accu_mask; +wire mac_a2accu_mode; +wire [8:0] mac_a2accu_pd; +wire mac_a2accu_pvld; +wire [8/2-1:0] mac_b2accu_mask; +wire mac_b2accu_mode; +wire [8:0] mac_b2accu_pd; +wire mac_b2accu_pvld; +wire [32 +14:0] cdma_dat2mcif_rd_req_pd; +wire cdma_dat2mcif_rd_req_ready; +wire cdma_dat2mcif_rd_req_valid; +wire [32 +14:0] cdma_wt2mcif_rd_req_pd; +wire cdma_wt2mcif_rd_req_ready; +wire cdma_wt2mcif_rd_req_valid; +wire [64 +(64/8/8)-1:0] mcif2cdma_dat_rd_rsp_pd; +wire mcif2cdma_dat_rd_rsp_ready; +wire mcif2cdma_dat_rd_rsp_valid; +wire [64 +(64/8/8)-1:0] mcif2cdma_wt_rd_rsp_pd; +wire mcif2cdma_wt_rd_rsp_ready; +wire mcif2cdma_wt_rd_rsp_valid; + wire [64 +(64/8/8)-1:0] mcif2sdp_b_rd_rsp_pd; + wire mcif2sdp_b_rd_rsp_ready; + wire mcif2sdp_b_rd_rsp_valid; + wire sdp_b2mcif_rd_cdt_lat_fifo_pop; + wire [32 +14:0] sdp_b2mcif_rd_req_pd; + wire sdp_b2mcif_rd_req_ready; + wire sdp_b2mcif_rd_req_valid; + wire [64 +(64/8/8)-1:0] mcif2sdp_n_rd_rsp_pd; + wire mcif2sdp_n_rd_rsp_ready; + wire mcif2sdp_n_rd_rsp_valid; + wire sdp_n2mcif_rd_cdt_lat_fifo_pop; + wire [32 +14:0] sdp_n2mcif_rd_req_pd; + wire sdp_n2mcif_rd_req_ready; + wire sdp_n2mcif_rd_req_valid; +wire [64 +(64/8/8)-1:0] mcif2sdp_rd_rsp_pd; +wire mcif2sdp_rd_rsp_ready; +wire mcif2sdp_rd_rsp_valid; +wire mcif2sdp_wr_rsp_complete; +wire sdp2mcif_rd_cdt_lat_fifo_pop; +wire [32 +14:0] sdp2mcif_rd_req_pd; +wire sdp2mcif_rd_req_ready; +wire sdp2mcif_rd_req_valid; +wire [64 +(64/8/8):0] sdp2mcif_wr_req_pd; +wire sdp2mcif_wr_req_ready; +wire sdp2mcif_wr_req_valid; +wire [33:0] sdp2csb_resp_pd; +wire sdp2csb_resp_valid; +wire [1:0] sdp2glb_done_intr_pd; +wire [1*8 -1:0] sdp2pdp_pd; +wire sdp2pdp_ready; +wire sdp2pdp_valid; +wire [33:0] sdp_rdma2csb_resp_pd; +wire sdp_rdma2csb_resp_valid; +wire nvdla_clk_ovr_on; +wire nvdla_core_rstn; +//: my $kk=8 -1; +//: foreach my $i (0..${kk}) { +//: print qq( +//: wire [8 -1:0] sc2mac_dat_a_data${i}; +//: wire [8 -1:0] sc2mac_dat_b_data${i}; +//: wire [8 -1:0] sc2mac_wt_a_data${i}; +//: wire [8 -1:0] sc2mac_wt_b_data${i}; +//: ); +//: } +wire [8 -1:0] sc2mac_dat_a_mask; +wire [8:0] sc2mac_dat_a_pd; +wire sc2mac_dat_a_pvld; +wire [8 -1:0] sc2mac_dat_b_mask; +wire [8:0] sc2mac_dat_b_pd; +wire sc2mac_dat_b_pvld; +wire [8 -1:0] sc2mac_wt_a_mask; +wire sc2mac_wt_a_pvld; +wire [8/2-1:0] sc2mac_wt_a_sel; +wire [8 -1:0] sc2mac_wt_b_mask; +wire sc2mac_wt_b_pvld; +wire [8/2-1:0] sc2mac_wt_b_sel; +//////////////////////////////////////////////////////////////////////////////// + assign nvdla_core2cvsram_aw_awvalid = 1'b0; + assign nvdla_core2cvsram_w_wvalid = 1'b0; + assign nvdla_core2cvsram_w_wlast = 1'b0; + assign nvdla_core2cvsram_b_bready = 1'b1; + assign nvdla_core2cvsram_r_rready = 1'b1; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition O // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_o u_partition_o ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd[33:0]) + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd[62:0]) + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd[33:0]) + ,.cmac_b2csb_resp_valid (cmac_b2csb_resp_valid) + ,.cmac_b2csb_resp_pd (cmac_b2csb_resp_pd[33:0]) + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd[62:0]) + ,.csb2cmac_b_req_pvld (csb2cmac_b_req_pvld) + ,.csb2cmac_b_req_prdy (csb2cmac_b_req_prdy) + ,.csb2cmac_b_req_pd (csb2cmac_b_req_pd[62:0]) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd[33:0]) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd[62:0]) + ,.csb2csc_req_pvld (csb2csc_req_pvld) + ,.csb2csc_req_prdy (csb2csc_req_prdy) + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) + ,.csb2nvdla_valid (csb2nvdla_valid) + ,.csb2nvdla_ready (csb2nvdla_ready) + ,.csb2nvdla_addr (csb2nvdla_addr[15:0]) + ,.csb2nvdla_wdat (csb2nvdla_wdat[31:0]) + ,.csb2nvdla_write (csb2nvdla_write) + ,.csb2nvdla_nposted (csb2nvdla_nposted) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd[62:0]) + ,.csc2csb_resp_valid (csc2csb_resp_valid) + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) + ,.mcif2noc_axi_ar_arvalid (nvdla_core2dbb_ar_arvalid) + ,.mcif2noc_axi_ar_arready (nvdla_core2dbb_ar_arready) + ,.mcif2noc_axi_ar_arid (nvdla_core2dbb_ar_arid[7:0]) + ,.mcif2noc_axi_ar_arlen (nvdla_core2dbb_ar_arlen[3:0]) + ,.mcif2noc_axi_ar_araddr (nvdla_core2dbb_ar_araddr) + ,.mcif2noc_axi_aw_awvalid (nvdla_core2dbb_aw_awvalid) + ,.mcif2noc_axi_aw_awready (nvdla_core2dbb_aw_awready) + ,.mcif2noc_axi_aw_awid (nvdla_core2dbb_aw_awid[7:0]) + ,.mcif2noc_axi_aw_awlen (nvdla_core2dbb_aw_awlen[3:0]) + ,.mcif2noc_axi_aw_awaddr (nvdla_core2dbb_aw_awaddr) + ,.mcif2noc_axi_w_wvalid (nvdla_core2dbb_w_wvalid) + ,.mcif2noc_axi_w_wready (nvdla_core2dbb_w_wready) + ,.mcif2noc_axi_w_wdata (nvdla_core2dbb_w_wdata) + ,.mcif2noc_axi_w_wstrb (nvdla_core2dbb_w_wstrb) + ,.mcif2noc_axi_w_wlast (nvdla_core2dbb_w_wlast) + ,.noc2mcif_axi_b_bvalid (nvdla_core2dbb_b_bvalid) + ,.noc2mcif_axi_b_bready (nvdla_core2dbb_b_bready) + ,.noc2mcif_axi_b_bid (nvdla_core2dbb_b_bid[7:0]) + ,.noc2mcif_axi_r_rvalid (nvdla_core2dbb_r_rvalid) + ,.noc2mcif_axi_r_rready (nvdla_core2dbb_r_rready) + ,.noc2mcif_axi_r_rid (nvdla_core2dbb_r_rid[7:0]) + ,.noc2mcif_axi_r_rlast (nvdla_core2dbb_r_rlast) + ,.noc2mcif_axi_r_rdata (nvdla_core2dbb_r_rdata) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd) + ,.nvdla2csb_valid (nvdla2csb_valid) + ,.nvdla2csb_data (nvdla2csb_data[31:0]) + ,.nvdla2csb_wr_complete (nvdla2csb_wr_complete) + ,.core_intr (dla_intr) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_o_pd[31:0]) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd[33:0]) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (dla_reset_rstn) + ,.nvdla_core_rstn (nvdla_core_rstn) + ,.nvdla_falcon_clk (dla_csb_clk) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition C // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_c u_partition_c ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.accu2sc_credit_vld (accu2sc_credit_vld) + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) + ,.cdma2csb_resp_valid (cdma2csb_resp_valid) + ,.cdma2csb_resp_pd (cdma2csb_resp_pd[33:0]) + ,.cdma_dat2glb_done_intr_pd (cdma_dat2glb_done_intr_pd[1:0]) + ,.cdma_dat2mcif_rd_req_valid (cdma_dat2mcif_rd_req_valid) + ,.cdma_dat2mcif_rd_req_ready (cdma_dat2mcif_rd_req_ready) + ,.cdma_dat2mcif_rd_req_pd (cdma_dat2mcif_rd_req_pd) + ,.cdma_wt2glb_done_intr_pd (cdma_wt2glb_done_intr_pd[1:0]) + ,.cdma_wt2mcif_rd_req_valid (cdma_wt2mcif_rd_req_valid) + ,.cdma_wt2mcif_rd_req_ready (cdma_wt2mcif_rd_req_ready) + ,.cdma_wt2mcif_rd_req_pd (cdma_wt2mcif_rd_req_pd) + ,.csb2cdma_req_pvld (csb2cdma_req_pvld) + ,.csb2cdma_req_prdy (csb2cdma_req_prdy) + ,.csb2cdma_req_pd (csb2cdma_req_pd[62:0]) + ,.csb2csc_req_pvld (csb2csc_req_pvld) + ,.csb2csc_req_prdy (csb2csc_req_prdy) + ,.csb2csc_req_pd (csb2csc_req_pd[62:0]) + ,.csc2csb_resp_valid (csc2csb_resp_valid) + ,.csc2csb_resp_pd (csc2csb_resp_pd[33:0]) + ,.mcif2cdma_dat_rd_rsp_valid (mcif2cdma_dat_rd_rsp_valid) + ,.mcif2cdma_dat_rd_rsp_ready (mcif2cdma_dat_rd_rsp_ready) + ,.mcif2cdma_dat_rd_rsp_pd (mcif2cdma_dat_rd_rsp_pd) + ,.mcif2cdma_wt_rd_rsp_valid (mcif2cdma_wt_rd_rsp_valid) + ,.mcif2cdma_wt_rd_rsp_ready (mcif2cdma_wt_rd_rsp_ready) + ,.mcif2cdma_wt_rd_rsp_pd (mcif2cdma_wt_rd_rsp_pd) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_c_pd[31:0]) + ,.sc2mac_dat_a_pvld (sc2mac_dat_a_pvld) + ,.sc2mac_dat_a_mask (sc2mac_dat_a_mask[8 -1:0]) +//: my $kk=8 -1; +//: foreach my $i (0..${kk}){ +//: print qq( +//: ,.sc2mac_dat_a_data${i} (sc2mac_dat_a_data${i}) +//: ,.sc2mac_dat_b_data${i} (sc2mac_dat_b_data${i}) +//: ,.sc2mac_wt_a_data${i} (sc2mac_wt_a_data${i}) +//: ,.sc2mac_wt_b_data${i} (sc2mac_wt_b_data${i}) +//: ); +//: } + ,.sc2mac_dat_a_pd (sc2mac_dat_a_pd[8:0]) + ,.sc2mac_dat_b_pvld (sc2mac_dat_b_pvld) + ,.sc2mac_dat_b_mask (sc2mac_dat_b_mask[8 -1:0]) + ,.sc2mac_dat_b_pd (sc2mac_dat_b_pd[8:0]) + ,.sc2mac_wt_a_pvld (sc2mac_wt_a_pvld) + ,.sc2mac_wt_a_mask (sc2mac_wt_a_mask[8 -1:0]) + ,.sc2mac_wt_a_sel (sc2mac_wt_a_sel[8/2-1:0]) + ,.sc2mac_wt_b_pvld (sc2mac_wt_b_pvld) + ,.sc2mac_wt_b_mask (sc2mac_wt_b_mask[8 -1:0]) + ,.sc2mac_wt_b_sel (sc2mac_wt_b_sel[8/2-1:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//&Connect /nvdla_obs/ nvdla_pwrpart_c_obs; +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition MA // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_m u_partition_ma ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.csb2cmac_a_req_pvld (csb2cmac_a_req_pvld) //|< w + ,.csb2cmac_a_req_prdy (csb2cmac_a_req_prdy) //|> w + ,.csb2cmac_a_req_pd (csb2cmac_a_req_pd) //|< w + ,.cmac_a2csb_resp_valid (cmac_a2csb_resp_valid) //|> w + ,.cmac_a2csb_resp_pd (cmac_a2csb_resp_pd) //|> w + ,.sc2mac_wt_pvld (sc2mac_wt_a_pvld) //|< w + ,.sc2mac_wt_mask (sc2mac_wt_a_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_a_data${i}) //|< w ) +//: } + ,.sc2mac_wt_sel (sc2mac_wt_a_sel) //|< w + ,.sc2mac_dat_pvld (sc2mac_dat_a_pvld) //|< w + ,.sc2mac_dat_mask (sc2mac_dat_a_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_a_data${i}) //|< w ) +//: } + ,.sc2mac_dat_pd (sc2mac_dat_a_pd) //|< w + ,.mac2accu_pvld (mac_a2accu_pvld) //|> w + ,.mac2accu_mask (mac_a2accu_mask) //|> w + ,.mac2accu_mode (mac_a2accu_mode) //|> w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac_a2accu_data${i}) //|> w ) +//: } + ,.mac2accu_pd (mac_a2accu_pd) //|> w + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition MB // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_m u_partition_mb ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.csb2cmac_a_req_pvld (csb2cmac_b_req_pvld) //|< w + ,.csb2cmac_a_req_prdy (csb2cmac_b_req_prdy) //|> w + ,.csb2cmac_a_req_pd (csb2cmac_b_req_pd) //|< w + ,.cmac_a2csb_resp_valid (cmac_b2csb_resp_valid) //|> w + ,.cmac_a2csb_resp_pd (cmac_b2csb_resp_pd) //|> w + ,.sc2mac_wt_pvld (sc2mac_wt_b_pvld) //|< w + ,.sc2mac_wt_mask (sc2mac_wt_b_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_wt_data${i} (sc2mac_wt_b_data${i}) //|< w ) +//: } + ,.sc2mac_wt_sel (sc2mac_wt_b_sel) //|< w + ,.sc2mac_dat_pvld (sc2mac_dat_b_pvld) //|< w + ,.sc2mac_dat_mask (sc2mac_dat_b_mask) //|< w +//: for(my $i=0; $i<8 ; $i++){ +//: print qq( +//: ,.sc2mac_dat_data${i} (sc2mac_dat_b_data${i}) //|< w ) +//: } + ,.sc2mac_dat_pd (sc2mac_dat_b_pd) //|< w + ,.mac2accu_pvld (mac_b2accu_pvld) //|> w + ,.mac2accu_mask (mac_b2accu_mask) //|> w + ,.mac2accu_mode (mac_b2accu_mode) //|> w +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac2accu_data${i} (mac_b2accu_data${i}) //|> w ) +//: } + ,.mac2accu_pd (mac_b2accu_pd) //|> w + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition A // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_a u_partition_a ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.accu2sc_credit_vld (accu2sc_credit_vld) + ,.accu2sc_credit_size (accu2sc_credit_size[2:0]) + ,.csb2cacc_req_pvld (csb2cacc_req_pvld) + ,.csb2cacc_req_prdy (csb2cacc_req_prdy) + ,.csb2cacc_req_pd (csb2cacc_req_pd[62:0]) + ,.cacc2csb_resp_valid (cacc2csb_resp_valid) + ,.cacc2csb_resp_pd (cacc2csb_resp_pd[33:0]) + ,.cacc2glb_done_intr_pd (cacc2glb_done_intr_pd[1:0]) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.mac_a2accu_pvld (mac_a2accu_pvld) + ,.mac_a2accu_mask (mac_a2accu_mask[8/2-1:0]) + ,.mac_a2accu_mode (mac_a2accu_mode) +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_a2accu_data${i} (mac_a2accu_data${i}[19 -1:0]) ) +//: } + ,.mac_a2accu_pd (mac_a2accu_pd[8:0]) + ,.mac_b2accu_pvld (mac_b2accu_pvld) + ,.mac_b2accu_mask (mac_b2accu_mask[8/2-1:0]) + ,.mac_b2accu_mode (mac_b2accu_mode) +//: for(my $i=0; $i<8/2 ; $i++){ +//: print qq( +//: ,.mac_b2accu_data${i} (mac_b2accu_data${i}[19 -1:0]) ) +//: } + ,.mac_b2accu_pd (mac_b2accu_pd[8:0]) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_a_pd[31:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +//////////////////////////////////////////////////////////////////////// +// NVDLA Partition P // +//////////////////////////////////////////////////////////////////////// +NV_NVDLA_partition_p u_partition_p ( + .test_mode (test_mode) + ,.direct_reset_ (direct_reset_) + ,.global_clk_ovr_on (global_clk_ovr_on) + ,.tmc2slcg_disable_clock_gating (tmc2slcg_disable_clock_gating) + ,.cacc2sdp_valid (cacc2sdp_valid) + ,.cacc2sdp_ready (cacc2sdp_ready) + ,.cacc2sdp_pd (cacc2sdp_pd) + ,.csb2sdp_rdma_req_pvld (csb2sdp_rdma_req_pvld) + ,.csb2sdp_rdma_req_prdy (csb2sdp_rdma_req_prdy) + ,.csb2sdp_rdma_req_pd (csb2sdp_rdma_req_pd[62:0]) + ,.csb2sdp_req_pvld (csb2sdp_req_pvld) + ,.csb2sdp_req_prdy (csb2sdp_req_prdy) + ,.csb2sdp_req_pd (csb2sdp_req_pd[62:0]) + ,.sdp_b2mcif_rd_cdt_lat_fifo_pop (sdp_b2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_b2mcif_rd_req_valid (sdp_b2mcif_rd_req_valid) + ,.sdp_b2mcif_rd_req_ready (sdp_b2mcif_rd_req_ready) + ,.sdp_b2mcif_rd_req_pd (sdp_b2mcif_rd_req_pd ) + ,.mcif2sdp_b_rd_rsp_valid (mcif2sdp_b_rd_rsp_valid) + ,.mcif2sdp_b_rd_rsp_ready (mcif2sdp_b_rd_rsp_ready) + ,.mcif2sdp_b_rd_rsp_pd (mcif2sdp_b_rd_rsp_pd ) + ,.sdp_n2mcif_rd_cdt_lat_fifo_pop (sdp_n2mcif_rd_cdt_lat_fifo_pop) + ,.sdp_n2mcif_rd_req_valid (sdp_n2mcif_rd_req_valid) + ,.sdp_n2mcif_rd_req_ready (sdp_n2mcif_rd_req_ready) + ,.sdp_n2mcif_rd_req_pd (sdp_n2mcif_rd_req_pd ) + ,.mcif2sdp_n_rd_rsp_valid (mcif2sdp_n_rd_rsp_valid) + ,.mcif2sdp_n_rd_rsp_ready (mcif2sdp_n_rd_rsp_ready) + ,.mcif2sdp_n_rd_rsp_pd (mcif2sdp_n_rd_rsp_pd ) + ,.mcif2sdp_rd_rsp_valid (mcif2sdp_rd_rsp_valid) + ,.mcif2sdp_rd_rsp_ready (mcif2sdp_rd_rsp_ready) + ,.mcif2sdp_rd_rsp_pd (mcif2sdp_rd_rsp_pd ) + ,.mcif2sdp_wr_rsp_complete (mcif2sdp_wr_rsp_complete) + ,.pwrbus_ram_pd (nvdla_pwrbus_ram_p_pd[31:0]) + ,.sdp2csb_resp_valid (sdp2csb_resp_valid) + ,.sdp2csb_resp_pd (sdp2csb_resp_pd[33:0]) + ,.sdp2glb_done_intr_pd (sdp2glb_done_intr_pd[1:0]) + ,.sdp2mcif_rd_cdt_lat_fifo_pop (sdp2mcif_rd_cdt_lat_fifo_pop) + ,.sdp2mcif_rd_req_valid (sdp2mcif_rd_req_valid) + ,.sdp2mcif_rd_req_ready (sdp2mcif_rd_req_ready) + ,.sdp2mcif_rd_req_pd (sdp2mcif_rd_req_pd ) + ,.sdp2mcif_wr_req_valid (sdp2mcif_wr_req_valid) + ,.sdp2mcif_wr_req_ready (sdp2mcif_wr_req_ready) + ,.sdp2mcif_wr_req_pd (sdp2mcif_wr_req_pd ) + ,.sdp2pdp_valid (sdp2pdp_valid) + ,.sdp2pdp_ready (sdp2pdp_ready) + ,.sdp2pdp_pd (sdp2pdp_pd ) + ,.sdp_rdma2csb_resp_valid (sdp_rdma2csb_resp_valid) + ,.sdp_rdma2csb_resp_pd (sdp_rdma2csb_resp_pd[33:0]) + ,.nvdla_core_clk (dla_core_clk) + ,.dla_reset_rstn (nvdla_core_rstn) + ,.nvdla_clk_ovr_on (nvdla_clk_ovr_on) + ); +endmodule // NV_nvdla diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x18.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x18.v new file mode 100644 index 0000000..cdd9187 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x18.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_128x18.v +module nv_ram_rws_128x18 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +output [17:0] dout; +input [6:0] wa; +input we; +input [17:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [17:0] dout; +reg [17:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x18.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x18.v.vcp new file mode 100644 index 0000000..cdd9187 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x18.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_128x18.v +module nv_ram_rws_128x18 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +output [17:0] dout; +input [6:0] wa; +input we; +input [17:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [17:0] dout; +reg [17:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x256.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x256.v new file mode 100644 index 0000000..c78931b --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x256.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_128x256.v +module nv_ram_rws_128x256 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +output [255:0] dout; +input [6:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [255:0] dout; +reg [255:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x256.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x256.v.vcp new file mode 100644 index 0000000..c78931b --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x256.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_128x256.v +module nv_ram_rws_128x256 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +output [255:0] dout; +input [6:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [255:0] dout; +reg [255:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x64.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x64.v new file mode 100644 index 0000000..715124d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x64.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_128x64.v +module nv_ram_rws_128x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +output [63:0] dout; +input [6:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [63:0] dout; +reg [63:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x64.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x64.v.vcp new file mode 100644 index 0000000..715124d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_128x64.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_128x64.v +module nv_ram_rws_128x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +output [63:0] dout; +input [6:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [63:0] dout; +reg [63:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x256.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x256.v new file mode 100644 index 0000000..058f1ab --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x256.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_16x256.v +module nv_ram_rws_16x256 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [3:0] ra; +input re; +output [255:0] dout; +input [3:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [3:0] ra_d; +wire [255:0] dout; +reg [255:0] M [15:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x256.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x256.v.vcp new file mode 100644 index 0000000..058f1ab --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x256.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_16x256.v +module nv_ram_rws_16x256 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [3:0] ra; +input re; +output [255:0] dout; +input [3:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [3:0] ra_d; +wire [255:0] dout; +reg [255:0] M [15:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x272.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x272.v new file mode 100644 index 0000000..a95a4ed --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x272.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_16x272.v +module nv_ram_rws_16x272 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [3:0] ra; +input re; +output [271:0] dout; +input [3:0] wa; +input we; +input [271:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [3:0] ra_d; +wire [271:0] dout; +reg [271:0] M [15:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x272.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x272.v.vcp new file mode 100644 index 0000000..a95a4ed --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x272.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_16x272.v +module nv_ram_rws_16x272 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [3:0] ra; +input re; +output [271:0] dout; +input [3:0] wa; +input we; +input [271:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [3:0] ra_d; +wire [271:0] dout; +reg [271:0] M [15:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x64.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x64.v new file mode 100644 index 0000000..7191751 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x64.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_16x64.v +module nv_ram_rws_16x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [3:0] ra; +input re; +output [63:0] dout; +input [3:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [3:0] ra_d; +wire [63:0] dout; +reg [63:0] M [15:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x64.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x64.v.vcp new file mode 100644 index 0000000..7191751 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_16x64.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_16x64.v +module nv_ram_rws_16x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [3:0] ra; +input re; +output [63:0] dout; +input [3:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [3:0] ra_d; +wire [63:0] dout; +reg [63:0] M [15:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x3.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x3.v new file mode 100644 index 0000000..b9be359 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x3.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x3.v +module nv_ram_rws_256x3 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [2:0] dout; +input [7:0] wa; +input we; +input [2:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [2:0] dout; +reg [2:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x3.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x3.v.vcp new file mode 100644 index 0000000..b9be359 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x3.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x3.v +module nv_ram_rws_256x3 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [2:0] dout; +input [7:0] wa; +input we; +input [2:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [2:0] dout; +reg [2:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x512.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x512.v new file mode 100644 index 0000000..875d008 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x512.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x512.v +module nv_ram_rws_256x512 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [511:0] dout; +input [7:0] wa; +input we; +input [511:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [511:0] dout; +reg [511:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x512.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x512.v.vcp new file mode 100644 index 0000000..875d008 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x512.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x512.v +module nv_ram_rws_256x512 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [511:0] dout; +input [7:0] wa; +input we; +input [511:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [511:0] dout; +reg [511:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x64.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x64.v new file mode 100644 index 0000000..9abf964 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x64.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x64.v +module nv_ram_rws_256x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [63:0] dout; +input [7:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [63:0] dout; +reg [63:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x64.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x64.v.vcp new file mode 100644 index 0000000..9abf964 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x64.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x64.v +module nv_ram_rws_256x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [63:0] dout; +input [7:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [63:0] dout; +reg [63:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x7.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x7.v new file mode 100644 index 0000000..4e1e3bc --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x7.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x7.v +module nv_ram_rws_256x7 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [6:0] dout; +input [7:0] wa; +input we; +input [6:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [6:0] dout; +reg [6:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x7.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x7.v.vcp new file mode 100644 index 0000000..4e1e3bc --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_256x7.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_256x7.v +module nv_ram_rws_256x7 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [6:0] dout; +input [7:0] wa; +input we; +input [6:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [6:0] dout; +reg [6:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x16.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x16.v new file mode 100644 index 0000000..a1f9d59 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x16.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x16.v +module nv_ram_rws_32x16 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [15:0] dout; +input [4:0] wa; +input we; +input [15:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [15:0] dout; +reg [15:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x16.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x16.v.vcp new file mode 100644 index 0000000..a1f9d59 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x16.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x16.v +module nv_ram_rws_32x16 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [15:0] dout; +input [4:0] wa; +input we; +input [15:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [15:0] dout; +reg [15:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x512.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x512.v new file mode 100644 index 0000000..420f8c3 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x512.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x512.v +module nv_ram_rws_32x512 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [511:0] dout; +input [4:0] wa; +input we; +input [511:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [511:0] dout; +reg [511:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x512.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x512.v.vcp new file mode 100644 index 0000000..420f8c3 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x512.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x512.v +module nv_ram_rws_32x512 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [511:0] dout; +input [4:0] wa; +input we; +input [511:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [511:0] dout; +reg [511:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x544.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x544.v new file mode 100644 index 0000000..315e927 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x544.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x544.v +module nv_ram_rws_32x544 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [543:0] dout; +input [4:0] wa; +input we; +input [543:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [543:0] dout; +reg [543:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x544.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x544.v.vcp new file mode 100644 index 0000000..315e927 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x544.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x544.v +module nv_ram_rws_32x544 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [543:0] dout; +input [4:0] wa; +input we; +input [543:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [543:0] dout; +reg [543:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x768.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x768.v new file mode 100644 index 0000000..6a944c4 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x768.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x768.v +module nv_ram_rws_32x768 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [767:0] dout; +input [4:0] wa; +input we; +input [767:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [767:0] dout; +reg [767:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x768.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x768.v.vcp new file mode 100644 index 0000000..6a944c4 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_32x768.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_32x768.v +module nv_ram_rws_32x768 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +output [767:0] dout; +input [4:0] wa; +input we; +input [767:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [767:0] dout; +reg [767:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x256.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x256.v new file mode 100644 index 0000000..604ce0d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x256.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_512x256.v +module nv_ram_rws_512x256 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [8:0] ra; +input re; +output [255:0] dout; +input [8:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [8:0] ra_d; +wire [255:0] dout; +reg [255:0] M [511:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x256.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x256.v.vcp new file mode 100644 index 0000000..604ce0d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x256.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_512x256.v +module nv_ram_rws_512x256 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [8:0] ra; +input re; +output [255:0] dout; +input [8:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [8:0] ra_d; +wire [255:0] dout; +reg [255:0] M [511:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x512.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x512.v new file mode 100644 index 0000000..51b7cd6 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x512.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_512x512.v +module nv_ram_rws_512x512 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [8:0] ra; +input re; +output [511:0] dout; +input [8:0] wa; +input we; +input [511:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [8:0] ra_d; +wire [511:0] dout; +reg [511:0] M [511:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x512.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x512.v.vcp new file mode 100644 index 0000000..51b7cd6 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x512.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_512x512.v +module nv_ram_rws_512x512 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [8:0] ra; +input re; +output [511:0] dout; +input [8:0] wa; +input we; +input [511:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [8:0] ra_d; +wire [511:0] dout; +reg [511:0] M [511:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x64.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x64.v new file mode 100644 index 0000000..3dd8f7c --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x64.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_512x64.v +module nv_ram_rws_512x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [8:0] ra; +input re; +output [63:0] dout; +input [8:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [8:0] ra_d; +wire [63:0] dout; +reg [63:0] M [511:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x64.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x64.v.vcp new file mode 100644 index 0000000..3dd8f7c --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_512x64.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_512x64.v +module nv_ram_rws_512x64 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [8:0] ra; +input re; +output [63:0] dout; +input [8:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [8:0] ra_d; +wire [63:0] dout; +reg [63:0] M [511:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x10.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x10.v new file mode 100644 index 0000000..4e54fe7 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x10.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x10.v +module nv_ram_rws_64x10 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [9:0] dout; +input [5:0] wa; +input we; +input [9:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [9:0] dout; +reg [9:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x10.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x10.v.vcp new file mode 100644 index 0000000..4e54fe7 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x10.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x10.v +module nv_ram_rws_64x10 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [9:0] dout; +input [5:0] wa; +input we; +input [9:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [9:0] dout; +reg [9:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1024.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1024.v new file mode 100644 index 0000000..cdd15ad --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1024.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x1024.v +module nv_ram_rws_64x1024 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [1023:0] dout; +input [5:0] wa; +input we; +input [1023:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [1023:0] dout; +reg [1023:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1024.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1024.v.vcp new file mode 100644 index 0000000..cdd15ad --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1024.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x1024.v +module nv_ram_rws_64x1024 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [1023:0] dout; +input [5:0] wa; +input we; +input [1023:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [1023:0] dout; +reg [1023:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1088.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1088.v new file mode 100644 index 0000000..eae0358 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1088.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x1088.v +module nv_ram_rws_64x1088 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [1087:0] dout; +input [5:0] wa; +input we; +input [1087:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [1087:0] dout; +reg [1087:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1088.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1088.v.vcp new file mode 100644 index 0000000..eae0358 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x1088.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x1088.v +module nv_ram_rws_64x1088 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [1087:0] dout; +input [5:0] wa; +input we; +input [1087:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [1087:0] dout; +reg [1087:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x116.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x116.v new file mode 100644 index 0000000..4e6a8c5 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x116.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x116.v +module nv_ram_rws_64x116 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [115:0] dout; +input [5:0] wa; +input we; +input [115:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [115:0] dout; +reg [115:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x116.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x116.v.vcp new file mode 100644 index 0000000..4e6a8c5 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x116.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x116.v +module nv_ram_rws_64x116 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [115:0] dout; +input [5:0] wa; +input we; +input [115:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [115:0] dout; +reg [115:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x18.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x18.v new file mode 100644 index 0000000..f3d4831 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x18.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x18.v +module nv_ram_rws_64x18 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [17:0] dout; +input [5:0] wa; +input we; +input [17:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [17:0] dout; +reg [17:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x18.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x18.v.vcp new file mode 100644 index 0000000..f3d4831 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rws_64x18.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rws_64x18.v +module nv_ram_rws_64x18 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +output [17:0] dout; +input [5:0] wa; +input we; +input [17:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [17:0] dout; +reg [17:0] M [63:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x11.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x11.v new file mode 100644 index 0000000..dd26bfc --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x11.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_128x11.v +module nv_ram_rwsp_128x11 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [10:0] dout; +input [6:0] wa; +input we; +input [10:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [10:0] dout; +reg [10:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [10:0] dout_ram = M[ra_d]; +reg [10:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x11.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x11.v.vcp new file mode 100644 index 0000000..dd26bfc --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x11.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_128x11.v +module nv_ram_rwsp_128x11 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [10:0] dout; +input [6:0] wa; +input we; +input [10:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [10:0] dout; +reg [10:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [10:0] dout_ram = M[ra_d]; +reg [10:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x6.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x6.v new file mode 100644 index 0000000..6e8b3e5 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x6.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_128x6.v +module nv_ram_rwsp_128x6 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [5:0] dout; +input [6:0] wa; +input we; +input [5:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [5:0] dout; +reg [5:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [5:0] dout_ram = M[ra_d]; +reg [5:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x6.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x6.v.vcp new file mode 100644 index 0000000..6e8b3e5 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_128x6.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_128x6.v +module nv_ram_rwsp_128x6 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [5:0] dout; +input [6:0] wa; +input we; +input [5:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [5:0] dout; +reg [5:0] M [127:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [5:0] dout_ram = M[ra_d]; +reg [5:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x16.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x16.v new file mode 100644 index 0000000..1a4c8aa --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x16.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_160x16.v +module nv_ram_rwsp_160x16 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [15:0] dout; +input [7:0] wa; +input we; +input [15:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [15:0] dout; +reg [15:0] M [159:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [15:0] dout_ram = M[ra_d]; +reg [15:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x16.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x16.v.vcp new file mode 100644 index 0000000..1a4c8aa --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x16.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_160x16.v +module nv_ram_rwsp_160x16 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [15:0] dout; +input [7:0] wa; +input we; +input [15:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [15:0] dout; +reg [15:0] M [159:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [15:0] dout_ram = M[ra_d]; +reg [15:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x514.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x514.v new file mode 100644 index 0000000..c2e3598 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x514.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_160x514.v +module nv_ram_rwsp_160x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [513:0] dout; +input [7:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [513:0] dout; +reg [513:0] M [159:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x514.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x514.v.vcp new file mode 100644 index 0000000..c2e3598 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x514.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_160x514.v +module nv_ram_rwsp_160x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [513:0] dout; +input [7:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [513:0] dout; +reg [513:0] M [159:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x65.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x65.v new file mode 100644 index 0000000..75b8fd0 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x65.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_160x65.v +module nv_ram_rwsp_160x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [64:0] dout; +input [7:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [64:0] dout; +reg [64:0] M [159:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x65.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x65.v.vcp new file mode 100644 index 0000000..75b8fd0 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_160x65.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_160x65.v +module nv_ram_rwsp_160x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [64:0] dout; +input [7:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [64:0] dout; +reg [64:0] M [159:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_20x289.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_20x289.v new file mode 100644 index 0000000..08d0725 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_20x289.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_20x289.v +module nv_ram_rwsp_20x289 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [288:0] dout; +input [4:0] wa; +input we; +input [288:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [288:0] dout; +reg [288:0] M [19:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [288:0] dout_ram = M[ra_d]; +reg [288:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_20x289.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_20x289.v.vcp new file mode 100644 index 0000000..08d0725 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_20x289.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_20x289.v +module nv_ram_rwsp_20x289 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [288:0] dout; +input [4:0] wa; +input we; +input [288:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [288:0] dout; +reg [288:0] M [19:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [288:0] dout_ram = M[ra_d]; +reg [288:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_245x514.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_245x514.v new file mode 100644 index 0000000..f2d18d8 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_245x514.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_245x514.v +module nv_ram_rwsp_245x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [513:0] dout; +input [7:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [513:0] dout; +reg [513:0] M [244:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_245x514.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_245x514.v.vcp new file mode 100644 index 0000000..f2d18d8 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_245x514.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_245x514.v +module nv_ram_rwsp_245x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [513:0] dout; +input [7:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [513:0] dout; +reg [513:0] M [244:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_256x11.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_256x11.v new file mode 100644 index 0000000..28af976 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_256x11.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_256x11.v +module nv_ram_rwsp_256x11 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [10:0] dout; +input [7:0] wa; +input we; +input [10:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [10:0] dout; +reg [10:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [10:0] dout_ram = M[ra_d]; +reg [10:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_256x11.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_256x11.v.vcp new file mode 100644 index 0000000..28af976 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_256x11.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_256x11.v +module nv_ram_rwsp_256x11 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +input ore; +output [10:0] dout; +input [7:0] wa; +input we; +input [10:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [10:0] dout; +reg [10:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [10:0] dout_ram = M[ra_d]; +reg [10:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_32x32.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_32x32.v new file mode 100644 index 0000000..05bc8cf --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_32x32.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_32x32.v +module nv_ram_rwsp_32x32 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [31:0] dout; +input [4:0] wa; +input we; +input [31:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [31:0] dout; +reg [31:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [31:0] dout_ram = M[ra_d]; +reg [31:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_32x32.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_32x32.v.vcp new file mode 100644 index 0000000..05bc8cf --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_32x32.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_32x32.v +module nv_ram_rwsp_32x32 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [31:0] dout; +input [4:0] wa; +input we; +input [31:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [31:0] dout; +reg [31:0] M [31:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [31:0] dout_ram = M[ra_d]; +reg [31:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x514.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x514.v new file mode 100644 index 0000000..db706ef --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x514.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_61x514.v +module nv_ram_rwsp_61x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [513:0] dout; +input [5:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [513:0] dout; +reg [513:0] M [60:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x514.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x514.v.vcp new file mode 100644 index 0000000..db706ef --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x514.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_61x514.v +module nv_ram_rwsp_61x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [513:0] dout; +input [5:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [513:0] dout; +reg [513:0] M [60:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x64.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x64.v new file mode 100644 index 0000000..4b9db6a --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x64.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_61x64.v +module nv_ram_rwsp_61x64 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [63:0] dout; +input [5:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [63:0] dout; +reg [63:0] M [60:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [63:0] dout_ram = M[ra_d]; +reg [63:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x64.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x64.v.vcp new file mode 100644 index 0000000..4b9db6a --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x64.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_61x64.v +module nv_ram_rwsp_61x64 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [63:0] dout; +input [5:0] wa; +input we; +input [63:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [63:0] dout; +reg [63:0] M [60:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [63:0] dout_ram = M[ra_d]; +reg [63:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x65.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x65.v new file mode 100644 index 0000000..b220139 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x65.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_61x65.v +module nv_ram_rwsp_61x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [64:0] dout; +input [5:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [64:0] dout; +reg [64:0] M [60:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x65.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x65.v.vcp new file mode 100644 index 0000000..b220139 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_61x65.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_61x65.v +module nv_ram_rwsp_61x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [64:0] dout; +input [5:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [64:0] dout; +reg [64:0] M [60:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x14.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x14.v new file mode 100644 index 0000000..5357c55 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x14.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x14.v +module nv_ram_rwsp_80x14 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [13:0] dout; +input [6:0] wa; +input we; +input [13:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [13:0] dout; +reg [13:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [13:0] dout_ram = M[ra_d]; +reg [13:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x14.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x14.v.vcp new file mode 100644 index 0000000..5357c55 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x14.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x14.v +module nv_ram_rwsp_80x14 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [13:0] dout; +input [6:0] wa; +input we; +input [13:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [13:0] dout; +reg [13:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [13:0] dout_ram = M[ra_d]; +reg [13:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x16.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x16.v new file mode 100644 index 0000000..d8a4225 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x16.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x16.v +module nv_ram_rwsp_80x16 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [15:0] dout; +input [6:0] wa; +input we; +input [15:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [15:0] dout; +reg [15:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [15:0] dout_ram = M[ra_d]; +reg [15:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x16.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x16.v.vcp new file mode 100644 index 0000000..d8a4225 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x16.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x16.v +module nv_ram_rwsp_80x16 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [15:0] dout; +input [6:0] wa; +input we; +input [15:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [15:0] dout; +reg [15:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [15:0] dout_ram = M[ra_d]; +reg [15:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x256.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x256.v new file mode 100644 index 0000000..ff6641b --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x256.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x256.v +module nv_ram_rwsp_80x256 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [255:0] dout; +input [6:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [255:0] dout; +reg [255:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [255:0] dout_ram = M[ra_d]; +reg [255:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x256.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x256.v.vcp new file mode 100644 index 0000000..ff6641b --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x256.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x256.v +module nv_ram_rwsp_80x256 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [255:0] dout; +input [6:0] wa; +input we; +input [255:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [255:0] dout; +reg [255:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [255:0] dout_ram = M[ra_d]; +reg [255:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x514.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x514.v new file mode 100644 index 0000000..b2e3a13 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x514.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x514.v +module nv_ram_rwsp_80x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [513:0] dout; +input [6:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [513:0] dout; +reg [513:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x514.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x514.v.vcp new file mode 100644 index 0000000..b2e3a13 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x514.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x514.v +module nv_ram_rwsp_80x514 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [513:0] dout; +input [6:0] wa; +input we; +input [513:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [513:0] dout; +reg [513:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [513:0] dout_ram = M[ra_d]; +reg [513:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x65.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x65.v new file mode 100644 index 0000000..2e59ce9 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x65.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x65.v +module nv_ram_rwsp_80x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [64:0] dout; +input [6:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [64:0] dout; +reg [64:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x65.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x65.v.vcp new file mode 100644 index 0000000..2e59ce9 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_80x65.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsp_80x65.v +module nv_ram_rwsp_80x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [64:0] dout; +input [6:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [64:0] dout; +reg [64:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v new file mode 100644 index 0000000..331386e --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v @@ -0,0 +1,42 @@ +module nv_ram_rwsp_8x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [2:0] ra; +input re; +input ore; +output [64:0] dout; +input [2:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [2:0] ra_d; +wire [64:0] dout; +reg [64:0] M [7:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v.vcp new file mode 100644 index 0000000..331386e --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsp_8x65.v.vcp @@ -0,0 +1,42 @@ +module nv_ram_rwsp_8x65 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [2:0] ra; +input re; +input ore; +output [64:0] dout; +input [2:0] wa; +input we; +input [64:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [2:0] ra_d; +wire [64:0] dout; +reg [64:0] M [7:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [64:0] dout_ram = M[ra_d]; +reg [64:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwst_256x8.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwst_256x8.v new file mode 100644 index 0000000..e4dd019 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwst_256x8.v @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwst_256x8.v +module nv_ram_rwst_256x8 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [7:0] dout; +input [7:0] wa; +input we; +input [7:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [7:0] dout; +reg [7:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwst_256x8.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwst_256x8.v.vcp new file mode 100644 index 0000000..e4dd019 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwst_256x8.v.vcp @@ -0,0 +1,42 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwst_256x8.v +module nv_ram_rwst_256x8 ( + clk, + ra, + re, + dout, + wa, + we, + di, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [7:0] ra; +input re; +output [7:0] dout; +input [7:0] wa; +input we; +input [7:0] di; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [7:0] ra_d; +wire [7:0] dout; +reg [7:0] M [255:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +assign dout = M[ra_d]; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x32.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x32.v new file mode 100644 index 0000000..8f84a5f --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x32.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x32.v +module nv_ram_rwsthp_19x32 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [31:0] dout; +input [4:0] wa; +input we; +input [31:0] di; +input byp_sel; +input [31:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [31:0] dout; +reg [31:0] M [18:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [31:0] dout_ram = M[ra_d]; +wire [31:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [31:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x32.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x32.v.vcp new file mode 100644 index 0000000..8f84a5f --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x32.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x32.v +module nv_ram_rwsthp_19x32 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [31:0] dout; +input [4:0] wa; +input we; +input [31:0] di; +input byp_sel; +input [31:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [31:0] dout; +reg [31:0] M [18:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [31:0] dout_ram = M[ra_d]; +wire [31:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [31:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x4.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x4.v new file mode 100644 index 0000000..ffc3b75 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x4.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x4.v +module nv_ram_rwsthp_19x4 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [3:0] dout; +input [4:0] wa; +input we; +input [3:0] di; +input byp_sel; +input [3:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [3:0] dout; +reg [3:0] M [18:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [3:0] dout_ram = M[ra_d]; +wire [3:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [3:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x4.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x4.v.vcp new file mode 100644 index 0000000..ffc3b75 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x4.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x4.v +module nv_ram_rwsthp_19x4 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [3:0] dout; +input [4:0] wa; +input we; +input [3:0] di; +input byp_sel; +input [3:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [3:0] dout; +reg [3:0] M [18:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [3:0] dout_ram = M[ra_d]; +wire [3:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [3:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x80.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x80.v new file mode 100644 index 0000000..08a288d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x80.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x80.v +module nv_ram_rwsthp_19x80 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [79:0] dout; +input [4:0] wa; +input we; +input [79:0] di; +input byp_sel; +input [79:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [79:0] dout; +reg [79:0] M [18:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [79:0] dout_ram = M[ra_d]; +wire [79:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [79:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x80.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x80.v.vcp new file mode 100644 index 0000000..08a288d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_19x80.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x80.v +module nv_ram_rwsthp_19x80 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [79:0] dout; +input [4:0] wa; +input we; +input [79:0] di; +input byp_sel; +input [79:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [4:0] ra_d; +wire [79:0] dout; +reg [79:0] M [18:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [79:0] dout_ram = M[ra_d]; +wire [79:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [79:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x168.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x168.v new file mode 100644 index 0000000..88aaa9a --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x168.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x168.v +module nv_ram_rwsthp_60x168 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [167:0] dout; +input [5:0] wa; +input we; +input [167:0] di; +input byp_sel; +input [167:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [167:0] dout; +reg [167:0] M [59:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [167:0] dout_ram = M[ra_d]; +wire [167:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [167:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x168.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x168.v.vcp new file mode 100644 index 0000000..88aaa9a --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x168.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x168.v +module nv_ram_rwsthp_60x168 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [167:0] dout; +input [5:0] wa; +input we; +input [167:0] di; +input byp_sel; +input [167:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [167:0] dout; +reg [167:0] M [59:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [167:0] dout_ram = M[ra_d]; +wire [167:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [167:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x21.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x21.v new file mode 100644 index 0000000..151955d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x21.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x21.v +module nv_ram_rwsthp_60x21 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [20:0] dout; +input [5:0] wa; +input we; +input [20:0] di; +input byp_sel; +input [20:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [20:0] dout; +reg [20:0] M [59:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [20:0] dout_ram = M[ra_d]; +wire [20:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [20:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x21.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x21.v.vcp new file mode 100644 index 0000000..151955d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_60x21.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x21.v +module nv_ram_rwsthp_60x21 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [20:0] dout; +input [5:0] wa; +input we; +input [20:0] di; +input byp_sel; +input [20:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [5:0] ra_d; +wire [20:0] dout; +reg [20:0] M [59:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [20:0] dout_ram = M[ra_d]; +wire [20:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [20:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x15.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x15.v new file mode 100644 index 0000000..d3c8239 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x15.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x15.v +module nv_ram_rwsthp_80x15 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [14:0] dout; +input [6:0] wa; +input we; +input [14:0] di; +input byp_sel; +input [14:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [14:0] dout; +reg [14:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [14:0] dout_ram = M[ra_d]; +wire [14:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [14:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x15.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x15.v.vcp new file mode 100644 index 0000000..d3c8239 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x15.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x15.v +module nv_ram_rwsthp_80x15 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [14:0] dout; +input [6:0] wa; +input we; +input [14:0] di; +input byp_sel; +input [14:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [14:0] dout; +reg [14:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [14:0] dout_ram = M[ra_d]; +wire [14:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [14:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x72.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x72.v new file mode 100644 index 0000000..bd0ba8b --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x72.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x72.v +module nv_ram_rwsthp_80x72 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [71:0] dout; +input [6:0] wa; +input we; +input [71:0] di; +input byp_sel; +input [71:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [71:0] dout; +reg [71:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [71:0] dout_ram = M[ra_d]; +wire [71:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [71:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x72.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x72.v.vcp new file mode 100644 index 0000000..bd0ba8b --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x72.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x72.v +module nv_ram_rwsthp_80x72 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [71:0] dout; +input [6:0] wa; +input we; +input [71:0] di; +input byp_sel; +input [71:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [71:0] dout; +reg [71:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [71:0] dout_ram = M[ra_d]; +wire [71:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [71:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x9.v b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x9.v new file mode 100644 index 0000000..6a3498a --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x9.v @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x9.v +module nv_ram_rwsthp_80x9 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [8:0] dout; +input [6:0] wa; +input we; +input [8:0] di; +input byp_sel; +input [8:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [8:0] dout; +reg [8:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [8:0] dout_ram = M[ra_d]; +wire [8:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [8:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x9.v.vcp b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x9.v.vcp new file mode 100644 index 0000000..6a3498a --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/fpga/small_rams/nv_ram_rwsthp_80x9.v.vcp @@ -0,0 +1,55 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x9.v +module nv_ram_rwsthp_80x9 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd +); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [8:0] dout; +input [6:0] wa; +input we; +input [8:0] di; +input byp_sel; +input [8:0] dbyp; +input [31:0] pwrbus_ram_pd; +//reg and wire list +reg [6:0] ra_d; +wire [8:0] dout; +reg [8:0] M [79:0]; +always @( posedge clk ) begin + if (we) + M[wa] <= di; +end +always @( posedge clk ) begin + if (re) + ra_d <= ra; +end +wire [8:0] dout_ram = M[ra_d]; +wire [8:0] fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [8:0] dout_r; +always @( posedge clk ) begin + if (ore) + dout_r <= fbypass_dout_ram; +end +assign dout = dout_r; +endmodule diff --git a/designs/src/NVDLA/vmod/rams/model/RAMDP_128X11_GL_M2_E2.v b/designs/src/NVDLA/vmod/rams/model/RAMDP_128X11_GL_M2_E2.v new file mode 100644 index 0000000..34226ea --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/model/RAMDP_128X11_GL_M2_E2.v @@ -0,0 +1,957 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: RAMDP_128X11_GL_M2_E2.v +`timescale 10ps/1ps +`celldefine +module RAMDP_128X11_GL_M2_E2 (CLK_R, CLK_W, RE, WE + , RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0 + , WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0 + , WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0 + , RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0 + , IDDQ + , SVOP_1, SVOP_0 + , SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN +); +// nvProps NoBus SLEEP_EN_ +`ifndef RAM_INTERFACE +`ifndef EMULATION +`ifndef SYNTHESIS +// Physical ram size defined as localparam +localparam phy_rows = 64; +localparam phy_cols = 22; +localparam phy_rcols_pos = 22'b0; +`endif //ndef SYNTHESIS +`endif //EMULATION +`endif //ndef RAM_INTERFACE +input CLK_R, CLK_W, RE, WE + , RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0 + , WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0 + , WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0 + , SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0, RET_EN + , IDDQ + , SVOP_1, SVOP_0; +output RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0; +`ifndef RAM_INTERFACE +//assemble & rename wires + wire [6:0] RA = {RADR_6, RADR_5, RADR_4, RADR_3, RADR_2, RADR_1, RADR_0}; + wire [6:0] WA = {WADR_6, WADR_5, WADR_4, WADR_3, WADR_2, WADR_1, WADR_0}; + wire [10:0] WD = {WD_10, WD_9, WD_8, WD_7, WD_6, WD_5, WD_4, WD_3, WD_2, WD_1, WD_0}; + wire [10:0] RD; + assign {RD_10, RD_9, RD_8, RD_7, RD_6, RD_5, RD_4, RD_3, RD_2, RD_1, RD_0} = RD; + wire [1:0] SVOP = {SVOP_1, SVOP_0}; + wire [7:0] SLEEP_EN = {SLEEP_EN_7, SLEEP_EN_6, SLEEP_EN_5, SLEEP_EN_4, SLEEP_EN_3, SLEEP_EN_2, SLEEP_EN_1, SLEEP_EN_0}; +`ifndef EMULATION +`ifndef SYNTHESIS +//State point clobering signals: + wire check_x = (SVOP_0 ^ SVOP_1); + wire clobber_x; + assign clobber_x = ((check_x === 1'bx) || (check_x === 1'bz)) ? 1'b1 : 1'b0; + wire clobber_array = ((|SLEEP_EN) & ~RET_EN) | clobber_x; + wire clobber_flops = (|SLEEP_EN) | clobber_x; + integer i; + always @(clobber_array) begin + if (clobber_array) begin + for (i=0; i<128; i=i+1) begin + ITOP.io.array[i] <= 11'bx; + end + end + end +//VCS coverage off + always @(clobber_flops) begin + if (clobber_flops) begin + ITOP.we_lat <= 1'bx; + ITOP.wa_lat <= 7'bx; + ITOP.wd_lat <= 11'bx; + ITOP.re_lat <= 1'bx; + ITOP.ra_lat <= 7'bx; + ITOP.io.r0_dout_tmp <= 11'b0; + end + end +//VCS coverage on +//VCS coverage off +`ifdef NV_RAM_ASSERT +//first reset signal for nv_assert_module: + reg sim_reset; + initial begin: init_sim_reset + sim_reset = 0; + #6 sim_reset = 1; + end + reg rst_clk; + initial begin: init_rst_clk + rst_clk = 0; + #2 rst_clk = 1; + #4 rst_clk = 0; + end +//internal weclk|reclk gating signal: + wire weclk_gating = ITOP.we_lat & ~IDDQ; + wire reclk_gating = ITOP.re_lat & ~IDDQ; +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [11-1:0] Q_127 = ITOP.io.array[127]; + wire [11-1:0] Q_126 = ITOP.io.array[126]; + wire [11-1:0] Q_125 = ITOP.io.array[125]; + wire [11-1:0] Q_124 = ITOP.io.array[124]; + wire [11-1:0] Q_123 = ITOP.io.array[123]; + wire [11-1:0] Q_122 = ITOP.io.array[122]; + wire [11-1:0] Q_121 = ITOP.io.array[121]; + wire [11-1:0] Q_120 = ITOP.io.array[120]; + wire [11-1:0] Q_119 = ITOP.io.array[119]; + wire [11-1:0] Q_118 = ITOP.io.array[118]; + wire [11-1:0] Q_117 = ITOP.io.array[117]; + wire [11-1:0] Q_116 = ITOP.io.array[116]; + wire [11-1:0] Q_115 = ITOP.io.array[115]; + wire [11-1:0] Q_114 = ITOP.io.array[114]; + wire [11-1:0] Q_113 = ITOP.io.array[113]; + wire [11-1:0] Q_112 = ITOP.io.array[112]; + wire [11-1:0] Q_111 = ITOP.io.array[111]; + wire [11-1:0] Q_110 = ITOP.io.array[110]; + wire [11-1:0] Q_109 = ITOP.io.array[109]; + wire [11-1:0] Q_108 = ITOP.io.array[108]; + wire [11-1:0] Q_107 = ITOP.io.array[107]; + wire [11-1:0] Q_106 = ITOP.io.array[106]; + wire [11-1:0] Q_105 = ITOP.io.array[105]; + wire [11-1:0] Q_104 = ITOP.io.array[104]; + wire [11-1:0] Q_103 = ITOP.io.array[103]; + wire [11-1:0] Q_102 = ITOP.io.array[102]; + wire [11-1:0] Q_101 = ITOP.io.array[101]; + wire [11-1:0] Q_100 = ITOP.io.array[100]; + wire [11-1:0] Q_99 = ITOP.io.array[99]; + wire [11-1:0] Q_98 = ITOP.io.array[98]; + wire [11-1:0] Q_97 = ITOP.io.array[97]; + wire [11-1:0] Q_96 = ITOP.io.array[96]; + wire [11-1:0] Q_95 = ITOP.io.array[95]; + wire [11-1:0] Q_94 = ITOP.io.array[94]; + wire [11-1:0] Q_93 = ITOP.io.array[93]; + wire [11-1:0] Q_92 = ITOP.io.array[92]; + wire [11-1:0] Q_91 = ITOP.io.array[91]; + wire [11-1:0] Q_90 = ITOP.io.array[90]; + wire [11-1:0] Q_89 = ITOP.io.array[89]; + wire [11-1:0] Q_88 = ITOP.io.array[88]; + wire [11-1:0] Q_87 = ITOP.io.array[87]; + wire [11-1:0] Q_86 = ITOP.io.array[86]; + wire [11-1:0] Q_85 = ITOP.io.array[85]; + wire [11-1:0] Q_84 = ITOP.io.array[84]; + wire [11-1:0] Q_83 = ITOP.io.array[83]; + wire [11-1:0] Q_82 = ITOP.io.array[82]; + wire [11-1:0] Q_81 = ITOP.io.array[81]; + wire [11-1:0] Q_80 = ITOP.io.array[80]; + wire [11-1:0] Q_79 = ITOP.io.array[79]; + wire [11-1:0] Q_78 = ITOP.io.array[78]; + wire [11-1:0] Q_77 = ITOP.io.array[77]; + wire [11-1:0] Q_76 = ITOP.io.array[76]; + wire [11-1:0] Q_75 = ITOP.io.array[75]; + wire [11-1:0] Q_74 = ITOP.io.array[74]; + wire [11-1:0] Q_73 = ITOP.io.array[73]; + wire [11-1:0] Q_72 = ITOP.io.array[72]; + wire [11-1:0] Q_71 = ITOP.io.array[71]; + wire [11-1:0] Q_70 = ITOP.io.array[70]; + wire [11-1:0] Q_69 = ITOP.io.array[69]; + wire [11-1:0] Q_68 = ITOP.io.array[68]; + wire [11-1:0] Q_67 = ITOP.io.array[67]; + wire [11-1:0] Q_66 = ITOP.io.array[66]; + wire [11-1:0] Q_65 = ITOP.io.array[65]; + wire [11-1:0] Q_64 = ITOP.io.array[64]; + wire [11-1:0] Q_63 = ITOP.io.array[63]; + wire [11-1:0] Q_62 = ITOP.io.array[62]; + wire [11-1:0] Q_61 = ITOP.io.array[61]; + wire [11-1:0] Q_60 = ITOP.io.array[60]; + wire [11-1:0] Q_59 = ITOP.io.array[59]; + wire [11-1:0] Q_58 = ITOP.io.array[58]; + wire [11-1:0] Q_57 = ITOP.io.array[57]; + wire [11-1:0] Q_56 = ITOP.io.array[56]; + wire [11-1:0] Q_55 = ITOP.io.array[55]; + wire [11-1:0] Q_54 = ITOP.io.array[54]; + wire [11-1:0] Q_53 = ITOP.io.array[53]; + wire [11-1:0] Q_52 = ITOP.io.array[52]; + wire [11-1:0] Q_51 = ITOP.io.array[51]; + wire [11-1:0] Q_50 = ITOP.io.array[50]; + wire [11-1:0] Q_49 = ITOP.io.array[49]; + wire [11-1:0] Q_48 = ITOP.io.array[48]; + wire [11-1:0] Q_47 = ITOP.io.array[47]; + wire [11-1:0] Q_46 = ITOP.io.array[46]; + wire [11-1:0] Q_45 = ITOP.io.array[45]; + wire [11-1:0] Q_44 = ITOP.io.array[44]; + wire [11-1:0] Q_43 = ITOP.io.array[43]; + wire [11-1:0] Q_42 = ITOP.io.array[42]; + wire [11-1:0] Q_41 = ITOP.io.array[41]; + wire [11-1:0] Q_40 = ITOP.io.array[40]; + wire [11-1:0] Q_39 = ITOP.io.array[39]; + wire [11-1:0] Q_38 = ITOP.io.array[38]; + wire [11-1:0] Q_37 = ITOP.io.array[37]; + wire [11-1:0] Q_36 = ITOP.io.array[36]; + wire [11-1:0] Q_35 = ITOP.io.array[35]; + wire [11-1:0] Q_34 = ITOP.io.array[34]; + wire [11-1:0] Q_33 = ITOP.io.array[33]; + wire [11-1:0] Q_32 = ITOP.io.array[32]; + wire [11-1:0] Q_31 = ITOP.io.array[31]; + wire [11-1:0] Q_30 = ITOP.io.array[30]; + wire [11-1:0] Q_29 = ITOP.io.array[29]; + wire [11-1:0] Q_28 = ITOP.io.array[28]; + wire [11-1:0] Q_27 = ITOP.io.array[27]; + wire [11-1:0] Q_26 = ITOP.io.array[26]; + wire [11-1:0] Q_25 = ITOP.io.array[25]; + wire [11-1:0] Q_24 = ITOP.io.array[24]; + wire [11-1:0] Q_23 = ITOP.io.array[23]; + wire [11-1:0] Q_22 = ITOP.io.array[22]; + wire [11-1:0] Q_21 = ITOP.io.array[21]; + wire [11-1:0] Q_20 = ITOP.io.array[20]; + wire [11-1:0] Q_19 = ITOP.io.array[19]; + wire [11-1:0] Q_18 = ITOP.io.array[18]; + wire [11-1:0] Q_17 = ITOP.io.array[17]; + wire [11-1:0] Q_16 = ITOP.io.array[16]; + wire [11-1:0] Q_15 = ITOP.io.array[15]; + wire [11-1:0] Q_14 = ITOP.io.array[14]; + wire [11-1:0] Q_13 = ITOP.io.array[13]; + wire [11-1:0] Q_12 = ITOP.io.array[12]; + wire [11-1:0] Q_11 = ITOP.io.array[11]; + wire [11-1:0] Q_10 = ITOP.io.array[10]; + wire [11-1:0] Q_9 = ITOP.io.array[9]; + wire [11-1:0] Q_8 = ITOP.io.array[8]; + wire [11-1:0] Q_7 = ITOP.io.array[7]; + wire [11-1:0] Q_6 = ITOP.io.array[6]; + wire [11-1:0] Q_5 = ITOP.io.array[5]; + wire [11-1:0] Q_4 = ITOP.io.array[4]; + wire [11-1:0] Q_3 = ITOP.io.array[3]; + wire [11-1:0] Q_2 = ITOP.io.array[2]; + wire [11-1:0] Q_1 = ITOP.io.array[1]; + wire [11-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<128; i=i+1) begin + ITOP.io.array[i] = {11{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [10:0] val; +begin + for (j=0; j<128; j=j+1) begin + for (i=0; i<11; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [10:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [10:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [21:0] data; + reg [10:0] wd0, wd1; + integer i; + begin + for (i=0; i<11; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [21:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [21:0] data; + reg [10:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=10; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [21:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [21:0] data; + reg [10:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 11'bx; + end + 1'b1: begin + rd0 = 11'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=10; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [21:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [10:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [10:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [10:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_128X11_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [10:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [10:0] dout; + assign RD = dout; +//memory array + reg [10:0] array[0:127]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_128X11_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [10:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [10:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [10:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [10:0] dout; + assign RD = clamp_o ? 11'b0 : (output_valid ? dout : 11'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_128X11_GL_M2_E2 # (128, 11, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({11{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_128X11_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 128; +parameter bits = 11; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=5'd20) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=5'd20) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [288-1:0] Q_19 = ITOP.io.array[19]; + wire [288-1:0] Q_18 = ITOP.io.array[18]; + wire [288-1:0] Q_17 = ITOP.io.array[17]; + wire [288-1:0] Q_16 = ITOP.io.array[16]; + wire [288-1:0] Q_15 = ITOP.io.array[15]; + wire [288-1:0] Q_14 = ITOP.io.array[14]; + wire [288-1:0] Q_13 = ITOP.io.array[13]; + wire [288-1:0] Q_12 = ITOP.io.array[12]; + wire [288-1:0] Q_11 = ITOP.io.array[11]; + wire [288-1:0] Q_10 = ITOP.io.array[10]; + wire [288-1:0] Q_9 = ITOP.io.array[9]; + wire [288-1:0] Q_8 = ITOP.io.array[8]; + wire [288-1:0] Q_7 = ITOP.io.array[7]; + wire [288-1:0] Q_6 = ITOP.io.array[6]; + wire [288-1:0] Q_5 = ITOP.io.array[5]; + wire [288-1:0] Q_4 = ITOP.io.array[4]; + wire [288-1:0] Q_3 = ITOP.io.array[3]; + wire [288-1:0] Q_2 = ITOP.io.array[2]; + wire [288-1:0] Q_1 = ITOP.io.array[1]; + wire [288-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<20; i=i+1) begin + ITOP.io.array[i] = {288{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [287:0] val; +begin + for (j=0; j<20; j=j+1) begin + for (i=0; i<288; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [4:0] addr; + input [287:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [287:0] mem_read; + input [4:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [4:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [4:0] addr; + input [287:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [287:0] mem_phys_read_padr; + input [4:0] addr; + begin + mem_phys_read_padr = ITOP.io.mem_read_raw(addr); + end +endfunction +function [4:0] mem_log_to_phys_adr; + input [4:0] addr; + begin + mem_log_to_phys_adr = addr; + end +endfunction +function [287:0] mem_phys_read_pmasked; + input [4:0] addr; + begin + mem_phys_read_pmasked = ITOP.io.mem_read_raw(addr); + end +endfunction +function [287:0] mem_phys_read_ladr; + input [4:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [287:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [287:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [287:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_20X288_GL_M1_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [4:0] wa_ff; + reg [287:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [4:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [287:0] dout; + assign RD = dout; +//memory array + reg [287:0] array[0:19]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_20X288_GL_M1_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [4:0] RA, WA; +input [287:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [287:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [4:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [287:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [4:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [287:0] dout; + assign RD = clamp_o ? 288'b0 : (output_valid ? dout : 288'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_20X288_GL_M1_E2 # (20, 288, 5) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({288{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_20X288_GL_M1_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 20; +parameter bits = 288; +parameter addrs = 5; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=5'd20) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=5'd20) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [288-1:0] Q_19 = ITOP.io.array[19]; + wire [288-1:0] Q_18 = ITOP.io.array[18]; + wire [288-1:0] Q_17 = ITOP.io.array[17]; + wire [288-1:0] Q_16 = ITOP.io.array[16]; + wire [288-1:0] Q_15 = ITOP.io.array[15]; + wire [288-1:0] Q_14 = ITOP.io.array[14]; + wire [288-1:0] Q_13 = ITOP.io.array[13]; + wire [288-1:0] Q_12 = ITOP.io.array[12]; + wire [288-1:0] Q_11 = ITOP.io.array[11]; + wire [288-1:0] Q_10 = ITOP.io.array[10]; + wire [288-1:0] Q_9 = ITOP.io.array[9]; + wire [288-1:0] Q_8 = ITOP.io.array[8]; + wire [288-1:0] Q_7 = ITOP.io.array[7]; + wire [288-1:0] Q_6 = ITOP.io.array[6]; + wire [288-1:0] Q_5 = ITOP.io.array[5]; + wire [288-1:0] Q_4 = ITOP.io.array[4]; + wire [288-1:0] Q_3 = ITOP.io.array[3]; + wire [288-1:0] Q_2 = ITOP.io.array[2]; + wire [288-1:0] Q_1 = ITOP.io.array[1]; + wire [288-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<20; i=i+1) begin + ITOP.io.array[i] = {288{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [287:0] val; +begin + for (j=0; j<20; j=j+1) begin + for (i=0; i<288; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [4:0] addr; + input [287:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [287:0] mem_read; + input [4:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [4:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [4:0] addr; + input [287:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [287:0] mem_phys_read_padr; + input [4:0] addr; + begin + mem_phys_read_padr = ITOP.io.mem_read_raw(addr); + end +endfunction +function [4:0] mem_log_to_phys_adr; + input [4:0] addr; + begin + mem_log_to_phys_adr = addr; + end +endfunction +function [287:0] mem_phys_read_pmasked; + input [4:0] addr; + begin + mem_phys_read_pmasked = ITOP.io.mem_read_raw(addr); + end +endfunction +function [287:0] mem_phys_read_ladr; + input [4:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [287:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [287:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [287:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_20X288_GL_M1_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [4:0] wa_ff; + reg [287:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [4:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [287:0] dout; + assign RD = dout; +//memory array + reg [287:0] array[0:19]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_20X288_GL_M1_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [4:0] RA, WA; +input [287:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [287:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [4:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [287:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [4:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [287:0] dout; + assign RD = clamp_o ? 288'b0 : (output_valid ? dout : 288'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_20X288_GL_M1_E2 # (20, 288, 5) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({288{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_20X288_GL_M1_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 20; +parameter bits = 288; +parameter addrs = 5; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=5'd20) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=5'd20) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [80-1:0] Q_19 = ITOP.io.array[19]; + wire [80-1:0] Q_18 = ITOP.io.array[18]; + wire [80-1:0] Q_17 = ITOP.io.array[17]; + wire [80-1:0] Q_16 = ITOP.io.array[16]; + wire [80-1:0] Q_15 = ITOP.io.array[15]; + wire [80-1:0] Q_14 = ITOP.io.array[14]; + wire [80-1:0] Q_13 = ITOP.io.array[13]; + wire [80-1:0] Q_12 = ITOP.io.array[12]; + wire [80-1:0] Q_11 = ITOP.io.array[11]; + wire [80-1:0] Q_10 = ITOP.io.array[10]; + wire [80-1:0] Q_9 = ITOP.io.array[9]; + wire [80-1:0] Q_8 = ITOP.io.array[8]; + wire [80-1:0] Q_7 = ITOP.io.array[7]; + wire [80-1:0] Q_6 = ITOP.io.array[6]; + wire [80-1:0] Q_5 = ITOP.io.array[5]; + wire [80-1:0] Q_4 = ITOP.io.array[4]; + wire [80-1:0] Q_3 = ITOP.io.array[3]; + wire [80-1:0] Q_2 = ITOP.io.array[2]; + wire [80-1:0] Q_1 = ITOP.io.array[1]; + wire [80-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<20; i=i+1) begin + ITOP.io.array[i] = {80{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [79:0] val; +begin + for (j=0; j<20; j=j+1) begin + for (i=0; i<80; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [4:0] addr; + input [79:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [79:0] mem_read; + input [4:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [4:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [4:0] addr; + input [79:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [79:0] mem_phys_read_padr; + input [4:0] addr; + begin + mem_phys_read_padr = ITOP.io.mem_read_raw(addr); + end +endfunction +function [4:0] mem_log_to_phys_adr; + input [4:0] addr; + begin + mem_log_to_phys_adr = addr; + end +endfunction +function [79:0] mem_phys_read_pmasked; + input [4:0] addr; + begin + mem_phys_read_pmasked = ITOP.io.mem_read_raw(addr); + end +endfunction +function [79:0] mem_phys_read_ladr; + input [4:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [79:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [79:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [79:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_20X80_GL_M1_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [4:0] wa_ff; + reg [79:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [4:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [79:0] dout; + assign RD = dout; +//memory array + reg [79:0] array[0:19]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_20X80_GL_M1_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [4:0] RA, WA; +input [79:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [79:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [4:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [79:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [4:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [79:0] dout; + assign RD = clamp_o ? 80'b0 : (output_valid ? dout : 80'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_20X80_GL_M1_E2 # (20, 80, 5) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({80{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_20X80_GL_M1_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 20; +parameter bits = 80; +parameter addrs = 5; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=5'd20) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=5'd20) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [80-1:0] Q_19 = ITOP.io.array[19]; + wire [80-1:0] Q_18 = ITOP.io.array[18]; + wire [80-1:0] Q_17 = ITOP.io.array[17]; + wire [80-1:0] Q_16 = ITOP.io.array[16]; + wire [80-1:0] Q_15 = ITOP.io.array[15]; + wire [80-1:0] Q_14 = ITOP.io.array[14]; + wire [80-1:0] Q_13 = ITOP.io.array[13]; + wire [80-1:0] Q_12 = ITOP.io.array[12]; + wire [80-1:0] Q_11 = ITOP.io.array[11]; + wire [80-1:0] Q_10 = ITOP.io.array[10]; + wire [80-1:0] Q_9 = ITOP.io.array[9]; + wire [80-1:0] Q_8 = ITOP.io.array[8]; + wire [80-1:0] Q_7 = ITOP.io.array[7]; + wire [80-1:0] Q_6 = ITOP.io.array[6]; + wire [80-1:0] Q_5 = ITOP.io.array[5]; + wire [80-1:0] Q_4 = ITOP.io.array[4]; + wire [80-1:0] Q_3 = ITOP.io.array[3]; + wire [80-1:0] Q_2 = ITOP.io.array[2]; + wire [80-1:0] Q_1 = ITOP.io.array[1]; + wire [80-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<20; i=i+1) begin + ITOP.io.array[i] = {80{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [79:0] val; +begin + for (j=0; j<20; j=j+1) begin + for (i=0; i<80; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [4:0] addr; + input [79:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [79:0] mem_read; + input [4:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [4:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [4:0] addr; + input [79:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [79:0] mem_phys_read_padr; + input [4:0] addr; + begin + mem_phys_read_padr = ITOP.io.mem_read_raw(addr); + end +endfunction +function [4:0] mem_log_to_phys_adr; + input [4:0] addr; + begin + mem_log_to_phys_adr = addr; + end +endfunction +function [79:0] mem_phys_read_pmasked; + input [4:0] addr; + begin + mem_phys_read_pmasked = ITOP.io.mem_read_raw(addr); + end +endfunction +function [79:0] mem_phys_read_ladr; + input [4:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [79:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [79:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [79:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_20X80_GL_M1_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [4:0] wa_ff; + reg [79:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [4:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [79:0] dout; + assign RD = dout; +//memory array + reg [79:0] array[0:19]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_20X80_GL_M1_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [4:0] RA, WA; +input [79:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [79:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [4:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [79:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [4:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [79:0] dout; + assign RD = clamp_o ? 80'b0 : (output_valid ? dout : 80'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_20X80_GL_M1_E2 # (20, 80, 5) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({80{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_20X80_GL_M1_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 20; +parameter bits = 80; +parameter addrs = 5; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=6'd60) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=6'd60) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [22-1:0] Q_59 = ITOP.io.array[59]; + wire [22-1:0] Q_58 = ITOP.io.array[58]; + wire [22-1:0] Q_57 = ITOP.io.array[57]; + wire [22-1:0] Q_56 = ITOP.io.array[56]; + wire [22-1:0] Q_55 = ITOP.io.array[55]; + wire [22-1:0] Q_54 = ITOP.io.array[54]; + wire [22-1:0] Q_53 = ITOP.io.array[53]; + wire [22-1:0] Q_52 = ITOP.io.array[52]; + wire [22-1:0] Q_51 = ITOP.io.array[51]; + wire [22-1:0] Q_50 = ITOP.io.array[50]; + wire [22-1:0] Q_49 = ITOP.io.array[49]; + wire [22-1:0] Q_48 = ITOP.io.array[48]; + wire [22-1:0] Q_47 = ITOP.io.array[47]; + wire [22-1:0] Q_46 = ITOP.io.array[46]; + wire [22-1:0] Q_45 = ITOP.io.array[45]; + wire [22-1:0] Q_44 = ITOP.io.array[44]; + wire [22-1:0] Q_43 = ITOP.io.array[43]; + wire [22-1:0] Q_42 = ITOP.io.array[42]; + wire [22-1:0] Q_41 = ITOP.io.array[41]; + wire [22-1:0] Q_40 = ITOP.io.array[40]; + wire [22-1:0] Q_39 = ITOP.io.array[39]; + wire [22-1:0] Q_38 = ITOP.io.array[38]; + wire [22-1:0] Q_37 = ITOP.io.array[37]; + wire [22-1:0] Q_36 = ITOP.io.array[36]; + wire [22-1:0] Q_35 = ITOP.io.array[35]; + wire [22-1:0] Q_34 = ITOP.io.array[34]; + wire [22-1:0] Q_33 = ITOP.io.array[33]; + wire [22-1:0] Q_32 = ITOP.io.array[32]; + wire [22-1:0] Q_31 = ITOP.io.array[31]; + wire [22-1:0] Q_30 = ITOP.io.array[30]; + wire [22-1:0] Q_29 = ITOP.io.array[29]; + wire [22-1:0] Q_28 = ITOP.io.array[28]; + wire [22-1:0] Q_27 = ITOP.io.array[27]; + wire [22-1:0] Q_26 = ITOP.io.array[26]; + wire [22-1:0] Q_25 = ITOP.io.array[25]; + wire [22-1:0] Q_24 = ITOP.io.array[24]; + wire [22-1:0] Q_23 = ITOP.io.array[23]; + wire [22-1:0] Q_22 = ITOP.io.array[22]; + wire [22-1:0] Q_21 = ITOP.io.array[21]; + wire [22-1:0] Q_20 = ITOP.io.array[20]; + wire [22-1:0] Q_19 = ITOP.io.array[19]; + wire [22-1:0] Q_18 = ITOP.io.array[18]; + wire [22-1:0] Q_17 = ITOP.io.array[17]; + wire [22-1:0] Q_16 = ITOP.io.array[16]; + wire [22-1:0] Q_15 = ITOP.io.array[15]; + wire [22-1:0] Q_14 = ITOP.io.array[14]; + wire [22-1:0] Q_13 = ITOP.io.array[13]; + wire [22-1:0] Q_12 = ITOP.io.array[12]; + wire [22-1:0] Q_11 = ITOP.io.array[11]; + wire [22-1:0] Q_10 = ITOP.io.array[10]; + wire [22-1:0] Q_9 = ITOP.io.array[9]; + wire [22-1:0] Q_8 = ITOP.io.array[8]; + wire [22-1:0] Q_7 = ITOP.io.array[7]; + wire [22-1:0] Q_6 = ITOP.io.array[6]; + wire [22-1:0] Q_5 = ITOP.io.array[5]; + wire [22-1:0] Q_4 = ITOP.io.array[4]; + wire [22-1:0] Q_3 = ITOP.io.array[3]; + wire [22-1:0] Q_2 = ITOP.io.array[2]; + wire [22-1:0] Q_1 = ITOP.io.array[1]; + wire [22-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<60; i=i+1) begin + ITOP.io.array[i] = {22{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [21:0] val; +begin + for (j=0; j<60; j=j+1) begin + for (i=0; i<22; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [5:0] addr; + input [21:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [21:0] mem_read; + input [5:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [5:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [5:0] addr; + input [21:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [21:0] mem_phys_read_padr; + input [5:0] addr; + begin + mem_phys_read_padr = ITOP.io.mem_read_raw(addr); + end +endfunction +function [5:0] mem_log_to_phys_adr; + input [5:0] addr; + begin + mem_log_to_phys_adr = addr; + end +endfunction +function [21:0] mem_phys_read_pmasked; + input [5:0] addr; + begin + mem_phys_read_pmasked = ITOP.io.mem_read_raw(addr); + end +endfunction +function [21:0] mem_phys_read_ladr; + input [5:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [21:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [21:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [21:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_60X22_GL_M1_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [5:0] wa_ff; + reg [21:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [5:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [21:0] dout; + assign RD = dout; +//memory array + reg [21:0] array[0:59]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_60X22_GL_M1_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [5:0] RA, WA; +input [21:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [21:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [5:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [21:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [5:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [21:0] dout; + assign RD = clamp_o ? 22'b0 : (output_valid ? dout : 22'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_60X22_GL_M1_E2 # (60, 22, 6) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({22{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_60X22_GL_M1_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 60; +parameter bits = 22; +parameter addrs = 6; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=6'd60) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=6'd60) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [22-1:0] Q_59 = ITOP.io.array[59]; + wire [22-1:0] Q_58 = ITOP.io.array[58]; + wire [22-1:0] Q_57 = ITOP.io.array[57]; + wire [22-1:0] Q_56 = ITOP.io.array[56]; + wire [22-1:0] Q_55 = ITOP.io.array[55]; + wire [22-1:0] Q_54 = ITOP.io.array[54]; + wire [22-1:0] Q_53 = ITOP.io.array[53]; + wire [22-1:0] Q_52 = ITOP.io.array[52]; + wire [22-1:0] Q_51 = ITOP.io.array[51]; + wire [22-1:0] Q_50 = ITOP.io.array[50]; + wire [22-1:0] Q_49 = ITOP.io.array[49]; + wire [22-1:0] Q_48 = ITOP.io.array[48]; + wire [22-1:0] Q_47 = ITOP.io.array[47]; + wire [22-1:0] Q_46 = ITOP.io.array[46]; + wire [22-1:0] Q_45 = ITOP.io.array[45]; + wire [22-1:0] Q_44 = ITOP.io.array[44]; + wire [22-1:0] Q_43 = ITOP.io.array[43]; + wire [22-1:0] Q_42 = ITOP.io.array[42]; + wire [22-1:0] Q_41 = ITOP.io.array[41]; + wire [22-1:0] Q_40 = ITOP.io.array[40]; + wire [22-1:0] Q_39 = ITOP.io.array[39]; + wire [22-1:0] Q_38 = ITOP.io.array[38]; + wire [22-1:0] Q_37 = ITOP.io.array[37]; + wire [22-1:0] Q_36 = ITOP.io.array[36]; + wire [22-1:0] Q_35 = ITOP.io.array[35]; + wire [22-1:0] Q_34 = ITOP.io.array[34]; + wire [22-1:0] Q_33 = ITOP.io.array[33]; + wire [22-1:0] Q_32 = ITOP.io.array[32]; + wire [22-1:0] Q_31 = ITOP.io.array[31]; + wire [22-1:0] Q_30 = ITOP.io.array[30]; + wire [22-1:0] Q_29 = ITOP.io.array[29]; + wire [22-1:0] Q_28 = ITOP.io.array[28]; + wire [22-1:0] Q_27 = ITOP.io.array[27]; + wire [22-1:0] Q_26 = ITOP.io.array[26]; + wire [22-1:0] Q_25 = ITOP.io.array[25]; + wire [22-1:0] Q_24 = ITOP.io.array[24]; + wire [22-1:0] Q_23 = ITOP.io.array[23]; + wire [22-1:0] Q_22 = ITOP.io.array[22]; + wire [22-1:0] Q_21 = ITOP.io.array[21]; + wire [22-1:0] Q_20 = ITOP.io.array[20]; + wire [22-1:0] Q_19 = ITOP.io.array[19]; + wire [22-1:0] Q_18 = ITOP.io.array[18]; + wire [22-1:0] Q_17 = ITOP.io.array[17]; + wire [22-1:0] Q_16 = ITOP.io.array[16]; + wire [22-1:0] Q_15 = ITOP.io.array[15]; + wire [22-1:0] Q_14 = ITOP.io.array[14]; + wire [22-1:0] Q_13 = ITOP.io.array[13]; + wire [22-1:0] Q_12 = ITOP.io.array[12]; + wire [22-1:0] Q_11 = ITOP.io.array[11]; + wire [22-1:0] Q_10 = ITOP.io.array[10]; + wire [22-1:0] Q_9 = ITOP.io.array[9]; + wire [22-1:0] Q_8 = ITOP.io.array[8]; + wire [22-1:0] Q_7 = ITOP.io.array[7]; + wire [22-1:0] Q_6 = ITOP.io.array[6]; + wire [22-1:0] Q_5 = ITOP.io.array[5]; + wire [22-1:0] Q_4 = ITOP.io.array[4]; + wire [22-1:0] Q_3 = ITOP.io.array[3]; + wire [22-1:0] Q_2 = ITOP.io.array[2]; + wire [22-1:0] Q_1 = ITOP.io.array[1]; + wire [22-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<60; i=i+1) begin + ITOP.io.array[i] = {22{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [21:0] val; +begin + for (j=0; j<60; j=j+1) begin + for (i=0; i<22; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [5:0] addr; + input [21:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [21:0] mem_read; + input [5:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [5:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [5:0] addr; + input [21:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [21:0] mem_phys_read_padr; + input [5:0] addr; + begin + mem_phys_read_padr = ITOP.io.mem_read_raw(addr); + end +endfunction +function [5:0] mem_log_to_phys_adr; + input [5:0] addr; + begin + mem_log_to_phys_adr = addr; + end +endfunction +function [21:0] mem_phys_read_pmasked; + input [5:0] addr; + begin + mem_phys_read_pmasked = ITOP.io.mem_read_raw(addr); + end +endfunction +function [21:0] mem_phys_read_ladr; + input [5:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [21:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [21:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [21:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_60X22_GL_M1_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [5:0] wa_ff; + reg [21:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [5:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [21:0] dout; + assign RD = dout; +//memory array + reg [21:0] array[0:59]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_60X22_GL_M1_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [5:0] RA, WA; +input [21:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [21:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [5:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [21:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [5:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [21:0] dout; + assign RD = clamp_o ? 22'b0 : (output_valid ? dout : 22'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_60X22_GL_M1_E2 # (60, 22, 6) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({22{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_60X22_GL_M1_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 60; +parameter bits = 22; +parameter addrs = 6; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=7'd80) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=7'd80) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [14-1:0] Q_79 = ITOP.io.array[79]; + wire [14-1:0] Q_78 = ITOP.io.array[78]; + wire [14-1:0] Q_77 = ITOP.io.array[77]; + wire [14-1:0] Q_76 = ITOP.io.array[76]; + wire [14-1:0] Q_75 = ITOP.io.array[75]; + wire [14-1:0] Q_74 = ITOP.io.array[74]; + wire [14-1:0] Q_73 = ITOP.io.array[73]; + wire [14-1:0] Q_72 = ITOP.io.array[72]; + wire [14-1:0] Q_71 = ITOP.io.array[71]; + wire [14-1:0] Q_70 = ITOP.io.array[70]; + wire [14-1:0] Q_69 = ITOP.io.array[69]; + wire [14-1:0] Q_68 = ITOP.io.array[68]; + wire [14-1:0] Q_67 = ITOP.io.array[67]; + wire [14-1:0] Q_66 = ITOP.io.array[66]; + wire [14-1:0] Q_65 = ITOP.io.array[65]; + wire [14-1:0] Q_64 = ITOP.io.array[64]; + wire [14-1:0] Q_63 = ITOP.io.array[63]; + wire [14-1:0] Q_62 = ITOP.io.array[62]; + wire [14-1:0] Q_61 = ITOP.io.array[61]; + wire [14-1:0] Q_60 = ITOP.io.array[60]; + wire [14-1:0] Q_59 = ITOP.io.array[59]; + wire [14-1:0] Q_58 = ITOP.io.array[58]; + wire [14-1:0] Q_57 = ITOP.io.array[57]; + wire [14-1:0] Q_56 = ITOP.io.array[56]; + wire [14-1:0] Q_55 = ITOP.io.array[55]; + wire [14-1:0] Q_54 = ITOP.io.array[54]; + wire [14-1:0] Q_53 = ITOP.io.array[53]; + wire [14-1:0] Q_52 = ITOP.io.array[52]; + wire [14-1:0] Q_51 = ITOP.io.array[51]; + wire [14-1:0] Q_50 = ITOP.io.array[50]; + wire [14-1:0] Q_49 = ITOP.io.array[49]; + wire [14-1:0] Q_48 = ITOP.io.array[48]; + wire [14-1:0] Q_47 = ITOP.io.array[47]; + wire [14-1:0] Q_46 = ITOP.io.array[46]; + wire [14-1:0] Q_45 = ITOP.io.array[45]; + wire [14-1:0] Q_44 = ITOP.io.array[44]; + wire [14-1:0] Q_43 = ITOP.io.array[43]; + wire [14-1:0] Q_42 = ITOP.io.array[42]; + wire [14-1:0] Q_41 = ITOP.io.array[41]; + wire [14-1:0] Q_40 = ITOP.io.array[40]; + wire [14-1:0] Q_39 = ITOP.io.array[39]; + wire [14-1:0] Q_38 = ITOP.io.array[38]; + wire [14-1:0] Q_37 = ITOP.io.array[37]; + wire [14-1:0] Q_36 = ITOP.io.array[36]; + wire [14-1:0] Q_35 = ITOP.io.array[35]; + wire [14-1:0] Q_34 = ITOP.io.array[34]; + wire [14-1:0] Q_33 = ITOP.io.array[33]; + wire [14-1:0] Q_32 = ITOP.io.array[32]; + wire [14-1:0] Q_31 = ITOP.io.array[31]; + wire [14-1:0] Q_30 = ITOP.io.array[30]; + wire [14-1:0] Q_29 = ITOP.io.array[29]; + wire [14-1:0] Q_28 = ITOP.io.array[28]; + wire [14-1:0] Q_27 = ITOP.io.array[27]; + wire [14-1:0] Q_26 = ITOP.io.array[26]; + wire [14-1:0] Q_25 = ITOP.io.array[25]; + wire [14-1:0] Q_24 = ITOP.io.array[24]; + wire [14-1:0] Q_23 = ITOP.io.array[23]; + wire [14-1:0] Q_22 = ITOP.io.array[22]; + wire [14-1:0] Q_21 = ITOP.io.array[21]; + wire [14-1:0] Q_20 = ITOP.io.array[20]; + wire [14-1:0] Q_19 = ITOP.io.array[19]; + wire [14-1:0] Q_18 = ITOP.io.array[18]; + wire [14-1:0] Q_17 = ITOP.io.array[17]; + wire [14-1:0] Q_16 = ITOP.io.array[16]; + wire [14-1:0] Q_15 = ITOP.io.array[15]; + wire [14-1:0] Q_14 = ITOP.io.array[14]; + wire [14-1:0] Q_13 = ITOP.io.array[13]; + wire [14-1:0] Q_12 = ITOP.io.array[12]; + wire [14-1:0] Q_11 = ITOP.io.array[11]; + wire [14-1:0] Q_10 = ITOP.io.array[10]; + wire [14-1:0] Q_9 = ITOP.io.array[9]; + wire [14-1:0] Q_8 = ITOP.io.array[8]; + wire [14-1:0] Q_7 = ITOP.io.array[7]; + wire [14-1:0] Q_6 = ITOP.io.array[6]; + wire [14-1:0] Q_5 = ITOP.io.array[5]; + wire [14-1:0] Q_4 = ITOP.io.array[4]; + wire [14-1:0] Q_3 = ITOP.io.array[3]; + wire [14-1:0] Q_2 = ITOP.io.array[2]; + wire [14-1:0] Q_1 = ITOP.io.array[1]; + wire [14-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<80; i=i+1) begin + ITOP.io.array[i] = {14{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [13:0] val; +begin + for (j=0; j<80; j=j+1) begin + for (i=0; i<14; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [13:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [13:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [27:0] data; + reg [13:0] wd0, wd1; + integer i; + begin + for (i=0; i<14; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [27:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [27:0] data; + reg [13:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=13; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [27:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [27:0] data; + reg [13:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 14'bx; + end + 1'b1: begin + rd0 = 14'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=13; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [27:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [13:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [13:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [13:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_80X14_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [13:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [13:0] dout; + assign RD = dout; +//memory array + reg [13:0] array[0:79]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_80X14_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [13:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [13:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [13:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [13:0] dout; + assign RD = clamp_o ? 14'b0 : (output_valid ? dout : 14'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_80X14_GL_M2_E2 # (80, 14, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({14{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_80X14_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 80; +parameter bits = 14; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=7'd80) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=7'd80) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [14-1:0] Q_79 = ITOP.io.array[79]; + wire [14-1:0] Q_78 = ITOP.io.array[78]; + wire [14-1:0] Q_77 = ITOP.io.array[77]; + wire [14-1:0] Q_76 = ITOP.io.array[76]; + wire [14-1:0] Q_75 = ITOP.io.array[75]; + wire [14-1:0] Q_74 = ITOP.io.array[74]; + wire [14-1:0] Q_73 = ITOP.io.array[73]; + wire [14-1:0] Q_72 = ITOP.io.array[72]; + wire [14-1:0] Q_71 = ITOP.io.array[71]; + wire [14-1:0] Q_70 = ITOP.io.array[70]; + wire [14-1:0] Q_69 = ITOP.io.array[69]; + wire [14-1:0] Q_68 = ITOP.io.array[68]; + wire [14-1:0] Q_67 = ITOP.io.array[67]; + wire [14-1:0] Q_66 = ITOP.io.array[66]; + wire [14-1:0] Q_65 = ITOP.io.array[65]; + wire [14-1:0] Q_64 = ITOP.io.array[64]; + wire [14-1:0] Q_63 = ITOP.io.array[63]; + wire [14-1:0] Q_62 = ITOP.io.array[62]; + wire [14-1:0] Q_61 = ITOP.io.array[61]; + wire [14-1:0] Q_60 = ITOP.io.array[60]; + wire [14-1:0] Q_59 = ITOP.io.array[59]; + wire [14-1:0] Q_58 = ITOP.io.array[58]; + wire [14-1:0] Q_57 = ITOP.io.array[57]; + wire [14-1:0] Q_56 = ITOP.io.array[56]; + wire [14-1:0] Q_55 = ITOP.io.array[55]; + wire [14-1:0] Q_54 = ITOP.io.array[54]; + wire [14-1:0] Q_53 = ITOP.io.array[53]; + wire [14-1:0] Q_52 = ITOP.io.array[52]; + wire [14-1:0] Q_51 = ITOP.io.array[51]; + wire [14-1:0] Q_50 = ITOP.io.array[50]; + wire [14-1:0] Q_49 = ITOP.io.array[49]; + wire [14-1:0] Q_48 = ITOP.io.array[48]; + wire [14-1:0] Q_47 = ITOP.io.array[47]; + wire [14-1:0] Q_46 = ITOP.io.array[46]; + wire [14-1:0] Q_45 = ITOP.io.array[45]; + wire [14-1:0] Q_44 = ITOP.io.array[44]; + wire [14-1:0] Q_43 = ITOP.io.array[43]; + wire [14-1:0] Q_42 = ITOP.io.array[42]; + wire [14-1:0] Q_41 = ITOP.io.array[41]; + wire [14-1:0] Q_40 = ITOP.io.array[40]; + wire [14-1:0] Q_39 = ITOP.io.array[39]; + wire [14-1:0] Q_38 = ITOP.io.array[38]; + wire [14-1:0] Q_37 = ITOP.io.array[37]; + wire [14-1:0] Q_36 = ITOP.io.array[36]; + wire [14-1:0] Q_35 = ITOP.io.array[35]; + wire [14-1:0] Q_34 = ITOP.io.array[34]; + wire [14-1:0] Q_33 = ITOP.io.array[33]; + wire [14-1:0] Q_32 = ITOP.io.array[32]; + wire [14-1:0] Q_31 = ITOP.io.array[31]; + wire [14-1:0] Q_30 = ITOP.io.array[30]; + wire [14-1:0] Q_29 = ITOP.io.array[29]; + wire [14-1:0] Q_28 = ITOP.io.array[28]; + wire [14-1:0] Q_27 = ITOP.io.array[27]; + wire [14-1:0] Q_26 = ITOP.io.array[26]; + wire [14-1:0] Q_25 = ITOP.io.array[25]; + wire [14-1:0] Q_24 = ITOP.io.array[24]; + wire [14-1:0] Q_23 = ITOP.io.array[23]; + wire [14-1:0] Q_22 = ITOP.io.array[22]; + wire [14-1:0] Q_21 = ITOP.io.array[21]; + wire [14-1:0] Q_20 = ITOP.io.array[20]; + wire [14-1:0] Q_19 = ITOP.io.array[19]; + wire [14-1:0] Q_18 = ITOP.io.array[18]; + wire [14-1:0] Q_17 = ITOP.io.array[17]; + wire [14-1:0] Q_16 = ITOP.io.array[16]; + wire [14-1:0] Q_15 = ITOP.io.array[15]; + wire [14-1:0] Q_14 = ITOP.io.array[14]; + wire [14-1:0] Q_13 = ITOP.io.array[13]; + wire [14-1:0] Q_12 = ITOP.io.array[12]; + wire [14-1:0] Q_11 = ITOP.io.array[11]; + wire [14-1:0] Q_10 = ITOP.io.array[10]; + wire [14-1:0] Q_9 = ITOP.io.array[9]; + wire [14-1:0] Q_8 = ITOP.io.array[8]; + wire [14-1:0] Q_7 = ITOP.io.array[7]; + wire [14-1:0] Q_6 = ITOP.io.array[6]; + wire [14-1:0] Q_5 = ITOP.io.array[5]; + wire [14-1:0] Q_4 = ITOP.io.array[4]; + wire [14-1:0] Q_3 = ITOP.io.array[3]; + wire [14-1:0] Q_2 = ITOP.io.array[2]; + wire [14-1:0] Q_1 = ITOP.io.array[1]; + wire [14-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<80; i=i+1) begin + ITOP.io.array[i] = {14{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [13:0] val; +begin + for (j=0; j<80; j=j+1) begin + for (i=0; i<14; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [13:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [13:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [27:0] data; + reg [13:0] wd0, wd1; + integer i; + begin + for (i=0; i<14; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [27:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [27:0] data; + reg [13:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=13; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [27:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [27:0] data; + reg [13:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 14'bx; + end + 1'b1: begin + rd0 = 14'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=13; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [27:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [13:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [13:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [13:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_80X14_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [13:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [13:0] dout; + assign RD = dout; +//memory array + reg [13:0] array[0:79]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_80X14_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [13:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [13:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [13:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [13:0] dout; + assign RD = clamp_o ? 14'b0 : (output_valid ? dout : 14'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_80X14_GL_M2_E2 # (80, 14, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({14{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_80X14_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 80; +parameter bits = 14; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=7'd80) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=7'd80) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [15-1:0] Q_79 = ITOP.io.array[79]; + wire [15-1:0] Q_78 = ITOP.io.array[78]; + wire [15-1:0] Q_77 = ITOP.io.array[77]; + wire [15-1:0] Q_76 = ITOP.io.array[76]; + wire [15-1:0] Q_75 = ITOP.io.array[75]; + wire [15-1:0] Q_74 = ITOP.io.array[74]; + wire [15-1:0] Q_73 = ITOP.io.array[73]; + wire [15-1:0] Q_72 = ITOP.io.array[72]; + wire [15-1:0] Q_71 = ITOP.io.array[71]; + wire [15-1:0] Q_70 = ITOP.io.array[70]; + wire [15-1:0] Q_69 = ITOP.io.array[69]; + wire [15-1:0] Q_68 = ITOP.io.array[68]; + wire [15-1:0] Q_67 = ITOP.io.array[67]; + wire [15-1:0] Q_66 = ITOP.io.array[66]; + wire [15-1:0] Q_65 = ITOP.io.array[65]; + wire [15-1:0] Q_64 = ITOP.io.array[64]; + wire [15-1:0] Q_63 = ITOP.io.array[63]; + wire [15-1:0] Q_62 = ITOP.io.array[62]; + wire [15-1:0] Q_61 = ITOP.io.array[61]; + wire [15-1:0] Q_60 = ITOP.io.array[60]; + wire [15-1:0] Q_59 = ITOP.io.array[59]; + wire [15-1:0] Q_58 = ITOP.io.array[58]; + wire [15-1:0] Q_57 = ITOP.io.array[57]; + wire [15-1:0] Q_56 = ITOP.io.array[56]; + wire [15-1:0] Q_55 = ITOP.io.array[55]; + wire [15-1:0] Q_54 = ITOP.io.array[54]; + wire [15-1:0] Q_53 = ITOP.io.array[53]; + wire [15-1:0] Q_52 = ITOP.io.array[52]; + wire [15-1:0] Q_51 = ITOP.io.array[51]; + wire [15-1:0] Q_50 = ITOP.io.array[50]; + wire [15-1:0] Q_49 = ITOP.io.array[49]; + wire [15-1:0] Q_48 = ITOP.io.array[48]; + wire [15-1:0] Q_47 = ITOP.io.array[47]; + wire [15-1:0] Q_46 = ITOP.io.array[46]; + wire [15-1:0] Q_45 = ITOP.io.array[45]; + wire [15-1:0] Q_44 = ITOP.io.array[44]; + wire [15-1:0] Q_43 = ITOP.io.array[43]; + wire [15-1:0] Q_42 = ITOP.io.array[42]; + wire [15-1:0] Q_41 = ITOP.io.array[41]; + wire [15-1:0] Q_40 = ITOP.io.array[40]; + wire [15-1:0] Q_39 = ITOP.io.array[39]; + wire [15-1:0] Q_38 = ITOP.io.array[38]; + wire [15-1:0] Q_37 = ITOP.io.array[37]; + wire [15-1:0] Q_36 = ITOP.io.array[36]; + wire [15-1:0] Q_35 = ITOP.io.array[35]; + wire [15-1:0] Q_34 = ITOP.io.array[34]; + wire [15-1:0] Q_33 = ITOP.io.array[33]; + wire [15-1:0] Q_32 = ITOP.io.array[32]; + wire [15-1:0] Q_31 = ITOP.io.array[31]; + wire [15-1:0] Q_30 = ITOP.io.array[30]; + wire [15-1:0] Q_29 = ITOP.io.array[29]; + wire [15-1:0] Q_28 = ITOP.io.array[28]; + wire [15-1:0] Q_27 = ITOP.io.array[27]; + wire [15-1:0] Q_26 = ITOP.io.array[26]; + wire [15-1:0] Q_25 = ITOP.io.array[25]; + wire [15-1:0] Q_24 = ITOP.io.array[24]; + wire [15-1:0] Q_23 = ITOP.io.array[23]; + wire [15-1:0] Q_22 = ITOP.io.array[22]; + wire [15-1:0] Q_21 = ITOP.io.array[21]; + wire [15-1:0] Q_20 = ITOP.io.array[20]; + wire [15-1:0] Q_19 = ITOP.io.array[19]; + wire [15-1:0] Q_18 = ITOP.io.array[18]; + wire [15-1:0] Q_17 = ITOP.io.array[17]; + wire [15-1:0] Q_16 = ITOP.io.array[16]; + wire [15-1:0] Q_15 = ITOP.io.array[15]; + wire [15-1:0] Q_14 = ITOP.io.array[14]; + wire [15-1:0] Q_13 = ITOP.io.array[13]; + wire [15-1:0] Q_12 = ITOP.io.array[12]; + wire [15-1:0] Q_11 = ITOP.io.array[11]; + wire [15-1:0] Q_10 = ITOP.io.array[10]; + wire [15-1:0] Q_9 = ITOP.io.array[9]; + wire [15-1:0] Q_8 = ITOP.io.array[8]; + wire [15-1:0] Q_7 = ITOP.io.array[7]; + wire [15-1:0] Q_6 = ITOP.io.array[6]; + wire [15-1:0] Q_5 = ITOP.io.array[5]; + wire [15-1:0] Q_4 = ITOP.io.array[4]; + wire [15-1:0] Q_3 = ITOP.io.array[3]; + wire [15-1:0] Q_2 = ITOP.io.array[2]; + wire [15-1:0] Q_1 = ITOP.io.array[1]; + wire [15-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<80; i=i+1) begin + ITOP.io.array[i] = {15{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [14:0] val; +begin + for (j=0; j<80; j=j+1) begin + for (i=0; i<15; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [14:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [14:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [29:0] data; + reg [14:0] wd0, wd1; + integer i; + begin + for (i=0; i<15; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [29:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [29:0] data; + reg [14:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=14; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [29:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [29:0] data; + reg [14:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 15'bx; + end + 1'b1: begin + rd0 = 15'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=14; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [29:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [14:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [14:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [14:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_80X15_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [14:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [14:0] dout; + assign RD = dout; +//memory array + reg [14:0] array[0:79]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_80X15_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [14:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [14:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [14:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [14:0] dout; + assign RD = clamp_o ? 15'b0 : (output_valid ? dout : 15'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_80X15_GL_M2_E2 # (80, 15, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({15{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_80X15_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 80; +parameter bits = 15; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=7'd80) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=7'd80) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [15-1:0] Q_79 = ITOP.io.array[79]; + wire [15-1:0] Q_78 = ITOP.io.array[78]; + wire [15-1:0] Q_77 = ITOP.io.array[77]; + wire [15-1:0] Q_76 = ITOP.io.array[76]; + wire [15-1:0] Q_75 = ITOP.io.array[75]; + wire [15-1:0] Q_74 = ITOP.io.array[74]; + wire [15-1:0] Q_73 = ITOP.io.array[73]; + wire [15-1:0] Q_72 = ITOP.io.array[72]; + wire [15-1:0] Q_71 = ITOP.io.array[71]; + wire [15-1:0] Q_70 = ITOP.io.array[70]; + wire [15-1:0] Q_69 = ITOP.io.array[69]; + wire [15-1:0] Q_68 = ITOP.io.array[68]; + wire [15-1:0] Q_67 = ITOP.io.array[67]; + wire [15-1:0] Q_66 = ITOP.io.array[66]; + wire [15-1:0] Q_65 = ITOP.io.array[65]; + wire [15-1:0] Q_64 = ITOP.io.array[64]; + wire [15-1:0] Q_63 = ITOP.io.array[63]; + wire [15-1:0] Q_62 = ITOP.io.array[62]; + wire [15-1:0] Q_61 = ITOP.io.array[61]; + wire [15-1:0] Q_60 = ITOP.io.array[60]; + wire [15-1:0] Q_59 = ITOP.io.array[59]; + wire [15-1:0] Q_58 = ITOP.io.array[58]; + wire [15-1:0] Q_57 = ITOP.io.array[57]; + wire [15-1:0] Q_56 = ITOP.io.array[56]; + wire [15-1:0] Q_55 = ITOP.io.array[55]; + wire [15-1:0] Q_54 = ITOP.io.array[54]; + wire [15-1:0] Q_53 = ITOP.io.array[53]; + wire [15-1:0] Q_52 = ITOP.io.array[52]; + wire [15-1:0] Q_51 = ITOP.io.array[51]; + wire [15-1:0] Q_50 = ITOP.io.array[50]; + wire [15-1:0] Q_49 = ITOP.io.array[49]; + wire [15-1:0] Q_48 = ITOP.io.array[48]; + wire [15-1:0] Q_47 = ITOP.io.array[47]; + wire [15-1:0] Q_46 = ITOP.io.array[46]; + wire [15-1:0] Q_45 = ITOP.io.array[45]; + wire [15-1:0] Q_44 = ITOP.io.array[44]; + wire [15-1:0] Q_43 = ITOP.io.array[43]; + wire [15-1:0] Q_42 = ITOP.io.array[42]; + wire [15-1:0] Q_41 = ITOP.io.array[41]; + wire [15-1:0] Q_40 = ITOP.io.array[40]; + wire [15-1:0] Q_39 = ITOP.io.array[39]; + wire [15-1:0] Q_38 = ITOP.io.array[38]; + wire [15-1:0] Q_37 = ITOP.io.array[37]; + wire [15-1:0] Q_36 = ITOP.io.array[36]; + wire [15-1:0] Q_35 = ITOP.io.array[35]; + wire [15-1:0] Q_34 = ITOP.io.array[34]; + wire [15-1:0] Q_33 = ITOP.io.array[33]; + wire [15-1:0] Q_32 = ITOP.io.array[32]; + wire [15-1:0] Q_31 = ITOP.io.array[31]; + wire [15-1:0] Q_30 = ITOP.io.array[30]; + wire [15-1:0] Q_29 = ITOP.io.array[29]; + wire [15-1:0] Q_28 = ITOP.io.array[28]; + wire [15-1:0] Q_27 = ITOP.io.array[27]; + wire [15-1:0] Q_26 = ITOP.io.array[26]; + wire [15-1:0] Q_25 = ITOP.io.array[25]; + wire [15-1:0] Q_24 = ITOP.io.array[24]; + wire [15-1:0] Q_23 = ITOP.io.array[23]; + wire [15-1:0] Q_22 = ITOP.io.array[22]; + wire [15-1:0] Q_21 = ITOP.io.array[21]; + wire [15-1:0] Q_20 = ITOP.io.array[20]; + wire [15-1:0] Q_19 = ITOP.io.array[19]; + wire [15-1:0] Q_18 = ITOP.io.array[18]; + wire [15-1:0] Q_17 = ITOP.io.array[17]; + wire [15-1:0] Q_16 = ITOP.io.array[16]; + wire [15-1:0] Q_15 = ITOP.io.array[15]; + wire [15-1:0] Q_14 = ITOP.io.array[14]; + wire [15-1:0] Q_13 = ITOP.io.array[13]; + wire [15-1:0] Q_12 = ITOP.io.array[12]; + wire [15-1:0] Q_11 = ITOP.io.array[11]; + wire [15-1:0] Q_10 = ITOP.io.array[10]; + wire [15-1:0] Q_9 = ITOP.io.array[9]; + wire [15-1:0] Q_8 = ITOP.io.array[8]; + wire [15-1:0] Q_7 = ITOP.io.array[7]; + wire [15-1:0] Q_6 = ITOP.io.array[6]; + wire [15-1:0] Q_5 = ITOP.io.array[5]; + wire [15-1:0] Q_4 = ITOP.io.array[4]; + wire [15-1:0] Q_3 = ITOP.io.array[3]; + wire [15-1:0] Q_2 = ITOP.io.array[2]; + wire [15-1:0] Q_1 = ITOP.io.array[1]; + wire [15-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<80; i=i+1) begin + ITOP.io.array[i] = {15{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [14:0] val; +begin + for (j=0; j<80; j=j+1) begin + for (i=0; i<15; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [14:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [14:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [29:0] data; + reg [14:0] wd0, wd1; + integer i; + begin + for (i=0; i<15; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [29:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [29:0] data; + reg [14:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=14; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [29:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [29:0] data; + reg [14:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 15'bx; + end + 1'b1: begin + rd0 = 15'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=14; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [29:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [14:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [14:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [14:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_80X15_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [14:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [14:0] dout; + assign RD = dout; +//memory array + reg [14:0] array[0:79]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_80X15_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [14:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [14:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [14:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [14:0] dout; + assign RD = clamp_o ? 15'b0 : (output_valid ? dout : 15'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_80X15_GL_M2_E2 # (80, 15, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({15{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_80X15_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 80; +parameter bits = 15; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=7'd80) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=7'd80) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [9-1:0] Q_79 = ITOP.io.array[79]; + wire [9-1:0] Q_78 = ITOP.io.array[78]; + wire [9-1:0] Q_77 = ITOP.io.array[77]; + wire [9-1:0] Q_76 = ITOP.io.array[76]; + wire [9-1:0] Q_75 = ITOP.io.array[75]; + wire [9-1:0] Q_74 = ITOP.io.array[74]; + wire [9-1:0] Q_73 = ITOP.io.array[73]; + wire [9-1:0] Q_72 = ITOP.io.array[72]; + wire [9-1:0] Q_71 = ITOP.io.array[71]; + wire [9-1:0] Q_70 = ITOP.io.array[70]; + wire [9-1:0] Q_69 = ITOP.io.array[69]; + wire [9-1:0] Q_68 = ITOP.io.array[68]; + wire [9-1:0] Q_67 = ITOP.io.array[67]; + wire [9-1:0] Q_66 = ITOP.io.array[66]; + wire [9-1:0] Q_65 = ITOP.io.array[65]; + wire [9-1:0] Q_64 = ITOP.io.array[64]; + wire [9-1:0] Q_63 = ITOP.io.array[63]; + wire [9-1:0] Q_62 = ITOP.io.array[62]; + wire [9-1:0] Q_61 = ITOP.io.array[61]; + wire [9-1:0] Q_60 = ITOP.io.array[60]; + wire [9-1:0] Q_59 = ITOP.io.array[59]; + wire [9-1:0] Q_58 = ITOP.io.array[58]; + wire [9-1:0] Q_57 = ITOP.io.array[57]; + wire [9-1:0] Q_56 = ITOP.io.array[56]; + wire [9-1:0] Q_55 = ITOP.io.array[55]; + wire [9-1:0] Q_54 = ITOP.io.array[54]; + wire [9-1:0] Q_53 = ITOP.io.array[53]; + wire [9-1:0] Q_52 = ITOP.io.array[52]; + wire [9-1:0] Q_51 = ITOP.io.array[51]; + wire [9-1:0] Q_50 = ITOP.io.array[50]; + wire [9-1:0] Q_49 = ITOP.io.array[49]; + wire [9-1:0] Q_48 = ITOP.io.array[48]; + wire [9-1:0] Q_47 = ITOP.io.array[47]; + wire [9-1:0] Q_46 = ITOP.io.array[46]; + wire [9-1:0] Q_45 = ITOP.io.array[45]; + wire [9-1:0] Q_44 = ITOP.io.array[44]; + wire [9-1:0] Q_43 = ITOP.io.array[43]; + wire [9-1:0] Q_42 = ITOP.io.array[42]; + wire [9-1:0] Q_41 = ITOP.io.array[41]; + wire [9-1:0] Q_40 = ITOP.io.array[40]; + wire [9-1:0] Q_39 = ITOP.io.array[39]; + wire [9-1:0] Q_38 = ITOP.io.array[38]; + wire [9-1:0] Q_37 = ITOP.io.array[37]; + wire [9-1:0] Q_36 = ITOP.io.array[36]; + wire [9-1:0] Q_35 = ITOP.io.array[35]; + wire [9-1:0] Q_34 = ITOP.io.array[34]; + wire [9-1:0] Q_33 = ITOP.io.array[33]; + wire [9-1:0] Q_32 = ITOP.io.array[32]; + wire [9-1:0] Q_31 = ITOP.io.array[31]; + wire [9-1:0] Q_30 = ITOP.io.array[30]; + wire [9-1:0] Q_29 = ITOP.io.array[29]; + wire [9-1:0] Q_28 = ITOP.io.array[28]; + wire [9-1:0] Q_27 = ITOP.io.array[27]; + wire [9-1:0] Q_26 = ITOP.io.array[26]; + wire [9-1:0] Q_25 = ITOP.io.array[25]; + wire [9-1:0] Q_24 = ITOP.io.array[24]; + wire [9-1:0] Q_23 = ITOP.io.array[23]; + wire [9-1:0] Q_22 = ITOP.io.array[22]; + wire [9-1:0] Q_21 = ITOP.io.array[21]; + wire [9-1:0] Q_20 = ITOP.io.array[20]; + wire [9-1:0] Q_19 = ITOP.io.array[19]; + wire [9-1:0] Q_18 = ITOP.io.array[18]; + wire [9-1:0] Q_17 = ITOP.io.array[17]; + wire [9-1:0] Q_16 = ITOP.io.array[16]; + wire [9-1:0] Q_15 = ITOP.io.array[15]; + wire [9-1:0] Q_14 = ITOP.io.array[14]; + wire [9-1:0] Q_13 = ITOP.io.array[13]; + wire [9-1:0] Q_12 = ITOP.io.array[12]; + wire [9-1:0] Q_11 = ITOP.io.array[11]; + wire [9-1:0] Q_10 = ITOP.io.array[10]; + wire [9-1:0] Q_9 = ITOP.io.array[9]; + wire [9-1:0] Q_8 = ITOP.io.array[8]; + wire [9-1:0] Q_7 = ITOP.io.array[7]; + wire [9-1:0] Q_6 = ITOP.io.array[6]; + wire [9-1:0] Q_5 = ITOP.io.array[5]; + wire [9-1:0] Q_4 = ITOP.io.array[4]; + wire [9-1:0] Q_3 = ITOP.io.array[3]; + wire [9-1:0] Q_2 = ITOP.io.array[2]; + wire [9-1:0] Q_1 = ITOP.io.array[1]; + wire [9-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<80; i=i+1) begin + ITOP.io.array[i] = {9{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [8:0] val; +begin + for (j=0; j<80; j=j+1) begin + for (i=0; i<9; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [8:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [8:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [17:0] data; + reg [8:0] wd0, wd1; + integer i; + begin + for (i=0; i<9; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [17:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [17:0] data; + reg [8:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=8; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [17:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [17:0] data; + reg [8:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 9'bx; + end + 1'b1: begin + rd0 = 9'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=8; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [17:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [8:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [8:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [8:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_80X9_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [8:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [8:0] dout; + assign RD = dout; +//memory array + reg [8:0] array[0:79]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_80X9_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [8:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [8:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [8:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [8:0] dout; + assign RD = clamp_o ? 9'b0 : (output_valid ? dout : 9'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_80X9_GL_M2_E2 # (80, 9, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({9{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_80X9_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 80; +parameter bits = 9; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a=7'd80) & weclk_gating; + wire disable_logic_assertion_wadr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_wadr_out_of_range"); + nv_assert_never #(0,0, "Logic-S1:write address out of range") disable_logic_assertion_wadr_out_of_range_x (CLK_W ^ rst_clk, ~disable_logic_assertion_wadr_out_of_range & sim_reset, illegal_logic_assertion_wadr_out_of_range); +//Logic-S2: read address out of range + wire illegal_logic_assertion_radr_out_of_range = (ITOP.ra_lat>=7'd80) & reclk_gating; + wire disable_logic_assertion_radr_out_of_range = $test$plusargs("disable_logic_assertions_globally") | $test$plusargs("disable_logic_assertion_radr_out_of_range"); + nv_assert_never #(0,0, "Logic-S2:read address out of range") disable_logic_assertion_radr_out_of_range_x (CLK_R ^ rst_clk, ~disable_logic_assertion_radr_out_of_range & sim_reset, illegal_logic_assertion_radr_out_of_range); +//Assertion checks for power sequence of G-option RAMDP: +//weclk_gating after 2 clk + reg weclk_gating_1p, weclk_gating_2p; + always @(posedge CLK_W) begin + weclk_gating_1p <= weclk_gating; + weclk_gating_2p <= weclk_gating_1p; + end +//reclk_gating after 2 clk + reg reclk_gating_1p, reclk_gating_2p; + always @(posedge CLK_R) begin + reclk_gating_1p <= reclk_gating; + reclk_gating_2p <= reclk_gating_1p; + end +//RET_EN off after 2 CLK_W + reg ret_en_w_1p, ret_en_w_2p; + always @(posedge CLK_W or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_w_1p <= 1'b1; + ret_en_w_2p <= 1'b1; + end + else + begin + ret_en_w_1p <= RET_EN; + ret_en_w_2p <= ret_en_w_1p; + end + end +//RET_EN off after 2 CLK_R + reg ret_en_r_1p, ret_en_r_2p; + always @(posedge CLK_R or posedge RET_EN) begin + if(RET_EN) + begin + ret_en_r_1p <= 1'b1; + ret_en_r_2p <= 1'b1; + end + else + begin + ret_en_r_1p <= RET_EN; + ret_en_r_2p <= ret_en_r_1p; + end + end + wire sleep_en_or = (|SLEEP_EN) ; +//SLEEP_EN off after 2 CLK_W + reg sleep_en_off_w_1p, sleep_en_off_w_2p; + always @(posedge CLK_W or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_w_1p <= 1'b1; + sleep_en_off_w_2p <= 1'b1; + end + else + begin + sleep_en_off_w_1p <= sleep_en_or; + sleep_en_off_w_2p <= sleep_en_off_w_1p; + end + end +//SLEEP_EN off after 2 CLK_R + reg sleep_en_off_r_1p, sleep_en_off_r_2p; + always @(posedge CLK_R or posedge sleep_en_or) begin + if(sleep_en_or) + begin + sleep_en_off_r_1p <= 1'b1; + sleep_en_off_r_2p <= 1'b1; + end + else + begin + sleep_en_off_r_1p <= |sleep_en_or; + sleep_en_off_r_2p <= sleep_en_off_r_1p; + end + end +//#1 From function mode to retention mode: +//Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN + wire disable_power_assertion_S1P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_after_SLEEP_EN_on_when_function2retention"); + nv_assert_never #(0,0, "Power-S1.1:illegal assert RET_EN after asserting SLEEP_EN") inst_S1P1 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P1 & sim_reset, (|SLEEP_EN)); +//Power-S1.2:illegal assert RET_EN without 2 nop-CLK + wire disable_power_assertion_S1P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_RET_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S1.2:illegal assert RET_EN without 2 nop-CLK") inst_S1P2 (RET_EN ^ rst_clk, ~disable_power_assertion_S1P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#2 From retention mode to function mode: +//Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.1:illegal write without 2 nop-CLK after de-asserting RET_EN") inst_S2P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S2P1 & sim_reset, ~RET_EN & ret_en_w_2p & weclk_gating); +//Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN + wire disable_power_assertion_S2P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_CLK_after_retention2function"); + nv_assert_never #(0,0, "Power-S2.2:illegal read without 2 nop-CLK after de-asserting RET_EN") inst_S2P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S2P2 & sim_reset, ~RET_EN & ret_en_r_2p & reclk_gating); +//#3 From function mode to sleep mode: +//Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK + wire disable_power_assertion_S3P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_assert_SLEEP_EN_without_2_nop_CLK"); + nv_assert_never #(0,0, "Power-S3.2:illegal assert SLEEP_EN without 2 nop-CLK") inst_S3P2 ((|SLEEP_EN) ^ rst_clk, ~disable_power_assertion_S3P2 & sim_reset, weclk_gating | weclk_gating_1p | weclk_gating_2p | reclk_gating | reclk_gating_1p | reclk_gating_2p); +//#4 From sleep mode to function mode: +//Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P1 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_write_without_2_nop_CLK_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.1:illegal write without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P1 (CLK_W ^ rst_clk, ~disable_power_assertion_S4P1 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_w_2p & weclk_gating); +//Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode + wire disable_power_assertion_S4P2 = $test$plusargs("disable_power_assertions_globally") | $test$plusargs("disable_power_assertion_read_without_2_nop_after_sleep2function"); + nv_assert_never #(0,0, "Power-S4.2:illegal read without 2 nop-CLK after switching from sleep mode to function mode") inst_S4P2 (CLK_R ^ rst_clk, ~disable_power_assertion_S4P2 & sim_reset, ~(|SLEEP_EN) & sleep_en_off_r_2p & reclk_gating); +`endif //NV_RAM_ASSERT +//VCS coverage on +`ifdef NV_RAM_EXPAND_ARRAY + wire [9-1:0] Q_79 = ITOP.io.array[79]; + wire [9-1:0] Q_78 = ITOP.io.array[78]; + wire [9-1:0] Q_77 = ITOP.io.array[77]; + wire [9-1:0] Q_76 = ITOP.io.array[76]; + wire [9-1:0] Q_75 = ITOP.io.array[75]; + wire [9-1:0] Q_74 = ITOP.io.array[74]; + wire [9-1:0] Q_73 = ITOP.io.array[73]; + wire [9-1:0] Q_72 = ITOP.io.array[72]; + wire [9-1:0] Q_71 = ITOP.io.array[71]; + wire [9-1:0] Q_70 = ITOP.io.array[70]; + wire [9-1:0] Q_69 = ITOP.io.array[69]; + wire [9-1:0] Q_68 = ITOP.io.array[68]; + wire [9-1:0] Q_67 = ITOP.io.array[67]; + wire [9-1:0] Q_66 = ITOP.io.array[66]; + wire [9-1:0] Q_65 = ITOP.io.array[65]; + wire [9-1:0] Q_64 = ITOP.io.array[64]; + wire [9-1:0] Q_63 = ITOP.io.array[63]; + wire [9-1:0] Q_62 = ITOP.io.array[62]; + wire [9-1:0] Q_61 = ITOP.io.array[61]; + wire [9-1:0] Q_60 = ITOP.io.array[60]; + wire [9-1:0] Q_59 = ITOP.io.array[59]; + wire [9-1:0] Q_58 = ITOP.io.array[58]; + wire [9-1:0] Q_57 = ITOP.io.array[57]; + wire [9-1:0] Q_56 = ITOP.io.array[56]; + wire [9-1:0] Q_55 = ITOP.io.array[55]; + wire [9-1:0] Q_54 = ITOP.io.array[54]; + wire [9-1:0] Q_53 = ITOP.io.array[53]; + wire [9-1:0] Q_52 = ITOP.io.array[52]; + wire [9-1:0] Q_51 = ITOP.io.array[51]; + wire [9-1:0] Q_50 = ITOP.io.array[50]; + wire [9-1:0] Q_49 = ITOP.io.array[49]; + wire [9-1:0] Q_48 = ITOP.io.array[48]; + wire [9-1:0] Q_47 = ITOP.io.array[47]; + wire [9-1:0] Q_46 = ITOP.io.array[46]; + wire [9-1:0] Q_45 = ITOP.io.array[45]; + wire [9-1:0] Q_44 = ITOP.io.array[44]; + wire [9-1:0] Q_43 = ITOP.io.array[43]; + wire [9-1:0] Q_42 = ITOP.io.array[42]; + wire [9-1:0] Q_41 = ITOP.io.array[41]; + wire [9-1:0] Q_40 = ITOP.io.array[40]; + wire [9-1:0] Q_39 = ITOP.io.array[39]; + wire [9-1:0] Q_38 = ITOP.io.array[38]; + wire [9-1:0] Q_37 = ITOP.io.array[37]; + wire [9-1:0] Q_36 = ITOP.io.array[36]; + wire [9-1:0] Q_35 = ITOP.io.array[35]; + wire [9-1:0] Q_34 = ITOP.io.array[34]; + wire [9-1:0] Q_33 = ITOP.io.array[33]; + wire [9-1:0] Q_32 = ITOP.io.array[32]; + wire [9-1:0] Q_31 = ITOP.io.array[31]; + wire [9-1:0] Q_30 = ITOP.io.array[30]; + wire [9-1:0] Q_29 = ITOP.io.array[29]; + wire [9-1:0] Q_28 = ITOP.io.array[28]; + wire [9-1:0] Q_27 = ITOP.io.array[27]; + wire [9-1:0] Q_26 = ITOP.io.array[26]; + wire [9-1:0] Q_25 = ITOP.io.array[25]; + wire [9-1:0] Q_24 = ITOP.io.array[24]; + wire [9-1:0] Q_23 = ITOP.io.array[23]; + wire [9-1:0] Q_22 = ITOP.io.array[22]; + wire [9-1:0] Q_21 = ITOP.io.array[21]; + wire [9-1:0] Q_20 = ITOP.io.array[20]; + wire [9-1:0] Q_19 = ITOP.io.array[19]; + wire [9-1:0] Q_18 = ITOP.io.array[18]; + wire [9-1:0] Q_17 = ITOP.io.array[17]; + wire [9-1:0] Q_16 = ITOP.io.array[16]; + wire [9-1:0] Q_15 = ITOP.io.array[15]; + wire [9-1:0] Q_14 = ITOP.io.array[14]; + wire [9-1:0] Q_13 = ITOP.io.array[13]; + wire [9-1:0] Q_12 = ITOP.io.array[12]; + wire [9-1:0] Q_11 = ITOP.io.array[11]; + wire [9-1:0] Q_10 = ITOP.io.array[10]; + wire [9-1:0] Q_9 = ITOP.io.array[9]; + wire [9-1:0] Q_8 = ITOP.io.array[8]; + wire [9-1:0] Q_7 = ITOP.io.array[7]; + wire [9-1:0] Q_6 = ITOP.io.array[6]; + wire [9-1:0] Q_5 = ITOP.io.array[5]; + wire [9-1:0] Q_4 = ITOP.io.array[4]; + wire [9-1:0] Q_3 = ITOP.io.array[3]; + wire [9-1:0] Q_2 = ITOP.io.array[2]; + wire [9-1:0] Q_1 = ITOP.io.array[1]; + wire [9-1:0] Q_0 = ITOP.io.array[0]; +`endif //def NV_RAM_EXPAND_ARRAY +//VCS coverage off +`ifdef MONITOR +task monitor_on; + begin + ITOP.io.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.io.monitor_on = 1'b0; + ITOP.io.dump_monitor_result = 1'b1; + end +endtask +`endif//def MONITOR +//VCS coverage on +//VCS coverage off +task mem_fill_value; +input fill_bit; +integer i; +begin + for (i=0; i<80; i=i+1) begin + ITOP.io.array[i] = {9{fill_bit}}; + end +end +endtask +task mem_fill_random; +integer i; +integer j; +reg [8:0] val; +begin + for (j=0; j<80; j=j+1) begin + for (i=0; i<9; i=i+1) begin + val[i] = {$random}; + end + ITOP.io.array[j] = val; + end +end +endtask +task mem_write; + input [6:0] addr; + input [8:0] data; + begin + ITOP.io.mem_wr_raw(addr,data); + end +endtask +function [8:0] mem_read; + input [6:0] addr; + begin + mem_read = ITOP.io.mem_read_raw(addr); + end +endfunction +task force_rd; + input [6:0] addr; + begin + ITOP.io.r0_dout_tmp = ITOP.io.array[addr]; + end +endtask +`ifdef MEM_PHYS_INFO +task mem_phys_write; + input [6-1:0] addr; + input [17:0] data; + reg [8:0] wd0, wd1; + integer i; + begin + for (i=0; i<9; i=i+1) begin + wd0[i] = data[i*2]; + wd1[i] = data[i*2+1]; + end + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b0}, wd0); + ITOP.io.mem_wr_raw({addr[6-1:0], 1'b1}, wd1); + end +endtask +function [17:0] mem_phys_read_padr; + input [6-1:0] addr; + reg [17:0] data; + reg [8:0] rd0, rd1; + integer i; + begin + rd0 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b0}); + rd1 = ITOP.io.mem_read_raw({addr[6-1:0], 1'b1}); + for (i=0; i<=8; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_padr = data; + end +endfunction +function [6-1:0] mem_log_to_phys_adr; + input [6:0] addr; + begin + mem_log_to_phys_adr = addr[6:1]; + end +endfunction +function [17:0] mem_phys_read_pmasked; + input [6:0] addr; + reg [17:0] data; + reg [8:0] rd0, rd1; + integer i; + begin + case (addr[0]) + 1'b0: begin + rd0 = ITOP.io.mem_read_raw(addr); + rd1 = 9'bx; + end + 1'b1: begin + rd0 = 9'bx; + rd1 = ITOP.io.mem_read_raw(addr); + end + endcase + for (i=0; i<=8; i=i+1) begin + data[i*2] = rd0[i]; + data[i*2+1] = rd1[i]; + end + mem_phys_read_pmasked = data; + end +endfunction +function [17:0] mem_phys_read_ladr; + input [6:0] addr; + begin + mem_phys_read_ladr = mem_phys_read_padr(mem_log_to_phys_adr(addr)); + end +endfunction +`endif //def MEM_PHYS_INFO +`ifdef FAULT_INJECTION +task mem_fault_no_write; + input [8:0] fault_mask; + begin + ITOP.io.mem_fault_no_write(fault_mask); + end +endtask +task mem_fault_stuck_0; + input [8:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_0(fault_mask); + end +endtask +task mem_fault_stuck_1; + input [8:0] fault_mask; + integer i; + begin + ITOP.io.mem_fault_stuck_1(fault_mask); + end +endtask +task set_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_0(r,c); +endtask +task set_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.set_bit_fault_stuck_1(r,c); +endtask +task clear_bit_fault_stuck_0; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_0(r,c); +endtask +task clear_bit_fault_stuck_1; + input r; + input c; + integer r; + integer c; + ITOP.io.clear_bit_fault_stuck_1(r,c); +endtask +//VCS coverage on +`endif //def FAULT_INJECTION +`else //def SYNTHESIS + wire clobber_x; + assign clobber_x = 1'b0; + wire clobber_array = 1'b0; + wire clobber_flops = 1'b0; +`endif //ndef SYNTHESIS +//instantiate memory bank + RAM_BANK_RAMDP_80X9_GL_M2_E2 ITOP ( + .RE(RE), + .WE(WE), + .RA(RA), + .WA(WA), + .CLK_R(CLK_R), + .CLK_W(CLK_W), + .IDDQ(IDDQ), + .SVOP(SVOP), + .WD(WD), + .RD(RD), + .SLEEP_EN(SLEEP_EN), + .RET_EN(RET_EN), + .clobber_flops(clobber_flops), + .clobber_array(clobber_array), + .clobber_x(clobber_x) + ); +//VCS coverage off +`else //def EMULATION +// Simple emulation model without MBIST, SCAN or REDUNDANCY +//common part for write + reg we_ff; + reg [6:0] wa_ff; + reg [8:0] wd_ff; + always @(posedge CLK_W) begin // spyglass disable W391 + we_ff <= WE; + wa_ff <= WA; + wd_ff <= WD; + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R) begin + re_lat <= RE; // spyglass disable W18 + end + end + wire reclk = CLK_R & re_lat; + reg [6:0] ra_ff; + always @(posedge CLK_R) begin // spyglass disable W391 + ra_ff <= RA; + end + reg [8:0] dout; + assign RD = dout; +//memory array + reg [8:0] array[0:79]; + always @(negedge CLK_W ) begin + if (we_ff) begin + array[wa_ff] <= wd_ff; // spyglass disable SYNTH_5130 + end + end + always @(*) begin + if (reclk) begin + dout <= array[ra_ff]; // spyglass disable SYNTH_5130, W18 + end + end +// End of the simple emulation model +`endif //def EMULATION +//VCS coverage on +`endif //ndef RAM_INTERFACE +endmodule +`endcelldefine +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// memory bank block : defines internal logic of the RAMDP ///////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAM_BANK_RAMDP_80X9_GL_M2_E2 (RE, WE, RA, WA, CLK_R, CLK_W, IDDQ, SVOP, WD, RD, SLEEP_EN, RET_EN, clobber_flops, clobber_array, clobber_x +); +input RET_EN; +input RE, WE, CLK_R, CLK_W, IDDQ; +input [6:0] RA, WA; +input [8:0] WD; +input [1:0] SVOP; +input [7:0] SLEEP_EN; +input clobber_flops, clobber_array, clobber_x; +output [8:0] RD; +//State point clobering signals: + wire output_valid = ~(clobber_x | (|SLEEP_EN)); + wire clamp_o = SLEEP_EN[7] | RET_EN; +//common part for write + wire clk_w_iddq = CLK_W & ~IDDQ & ~clamp_o; + reg we_lat; + always @(*) begin + if (!clk_w_iddq & !clobber_flops) begin + we_lat <= WE; // spyglass disable W18, IntClock + end + end +// weclk with posedge 1 dly | negedge 2 dly + wire weclk, weclk_d0, weclk_d1, weclk_d2; + assign weclk_d0 = clk_w_iddq & we_lat & ~clobber_flops & ~clobber_array; + assign #1 weclk_d1 = weclk_d0; + assign #1 weclk_d2 = weclk_d1; + assign weclk = weclk_d1 | weclk_d2; // spyglass disable GatedClock +// wadclk with posedge 0 dly | negedge 3 dly + wire wadclk, wadclk_d0, wadclk_d1, wadclk_d2, wadclk_d3; + assign wadclk_d0 = clk_w_iddq & we_lat; + assign #1 wadclk_d1 = wadclk_d0; + assign #1 wadclk_d2 = wadclk_d1; + assign #1 wadclk_d3 = wadclk_d2; + assign wadclk = wadclk_d0 | wadclk_d1 | wadclk_d2 | wadclk_d3; +// wdclk with posedge 0 dly | negedge 3 dly + wire wdclk, wdclk_d0, wdclk_d1, wdclk_d2, wdclk_d3; + assign wdclk_d0 = clk_w_iddq & we_lat; + assign #1 wdclk_d1 = wdclk_d0; + assign #1 wdclk_d2 = wdclk_d1; + assign #1 wdclk_d3 = wdclk_d2; + assign wdclk = wdclk_d0 | wdclk_d1 | wdclk_d2 | wdclk_d3; + reg [6:0] wa_lat; + always @(*) begin + if (!wadclk & !clobber_flops) begin + wa_lat <= WA; // spyglass disable W18, IntClock + end + end + reg [8:0] wd_lat; + always @(*) begin + if (!wdclk & !clobber_flops) begin + wd_lat <= WD; // spyglass disable W18, IntClock + end + end +//common part for read + reg re_lat; + always @(*) begin + if (!CLK_R & !clobber_flops) begin + re_lat <= RE; // spyglass disable W18, IntClock + end + end +// reclk with posedge 1 dly | negedge 0 dly + wire reclk, reclk_d0, reclk_d1; + assign reclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 reclk_d1 = reclk_d0; + assign reclk = reclk_d0 & reclk_d1; // spyglass disable GatedClock +// radclk with posedge 0 dly | negedge 1 dly + wire radclk, radclk_d0, radclk_d1; + assign radclk_d0 = CLK_R & ~IDDQ & re_lat & ~clamp_o; + assign #1 radclk_d1 = radclk_d0; + assign radclk = radclk_d0 | radclk_d1; + reg [6:0] ra_lat; + always @(*) begin + if (!radclk & !clobber_flops) begin + ra_lat <= RA; // spyglass disable W18, IntClock + end + end + wire [8:0] dout; + assign RD = clamp_o ? 9'b0 : (output_valid ? dout : 9'bx); //spyglass disable STARC-2.10.1.6 +//for E-option RAM + vram_RAMDP_80X9_GL_M2_E2 # (80, 9, 7) io ( + .w0_addr(wa_lat), + .w0_clk(weclk), + .w0_bwe({9{1'b1}}), + .w0_din(wd_lat), + .r0_addr(ra_lat), + .r0_clk(reclk), + .r0_dout(dout), + .clamp_o(clamp_o) + ); +endmodule +`endif //ndef EMULATION +`endif //ndef RAM_INTERFACE +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// ram primitive : defines 2D behavioral memory array of the RAMDP //////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +`ifndef RAM_INTERFACE +`ifndef EMULATION +module vram_RAMDP_80X9_GL_M2_E2 ( + w0_addr, + w0_clk, + w0_bwe, + w0_din, + r0_addr, + r0_clk, + r0_dout, + clamp_o +); +parameter words = 80; +parameter bits = 9; +parameter addrs = 7; +input [addrs-1:0] w0_addr; +input w0_clk; +input [bits-1:0] w0_din; +input [bits-1:0] w0_bwe; +input [addrs-1:0] r0_addr; +input r0_clk; +input clamp_o; +output [bits-1:0] r0_dout; +integer a; +`ifndef SYNTHESIS +`ifdef FAULT_INJECTION +// regs for inducing faults + reg [bits-1:0] fault_no_write; // block writes to this column + reg [bits-1:0] fault_stuck_0; // column always reads as 0 + reg [bits-1:0] fault_stuck_1; // column always reads as 1 + reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 + reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 + initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for (i=0; i<=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end + end +`endif //def FAULT_INJECTION +`ifdef MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg dump_monitor_result; +// this monitors coverage including redundancy cols +// 1'bx = not accessed +// 1'b0 = accessed as a 0 +// 1'b1 = accessed as a 1 +// 1'bz = accessed as both 0 and 1 +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + monitor_on = 1'b0; + dump_monitor_result = 1'b0; + for(a=0;a 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [17:0] val; + integer i; + begin + for (i=0; i<128; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [17:0] val; + integer i; + begin + val = {18{fill_bit}}; + for (i=0; i<128; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [17:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [18-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {18 {1'b1}} `else { $RollPLI(0,{18{1'b1}}) } `endif ; + else raminit_fullval = {18 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[6:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [35:0] mem_phys_read_padr; +input [5:0] addr; + reg [35:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [36-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {36 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {36 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [17:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=17; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [35:0] mem_phys_read_ladr; +input [6:0] addr; + reg [5:0] paddr; + reg [35:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [36-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {36 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {36 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [17:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=17; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [35:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [35:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [36-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {36 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {36 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [17:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[6:1]) : 18'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[6:1]) : 18'bx; + for (i=0; i<=17; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [35:0] data; + reg [17:0] wr[1:0]; + integer i; + begin + for (i=0; i<=17; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [35:0] mon_bit_w; +input [5:0] addr; + reg [35:0] mon_row; + reg [17:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=17; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [35:0] mon_bit_r; +input [5:0] addr; + reg [35:0] mon_row; + reg [17:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=17; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [35:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [17:0] Q_0 = ITOP.iow0.arr[0]; +wire [17:0] Q_1 = ITOP.iow1.arr[0]; +wire [17:0] Q_2 = ITOP.iow0.arr[1]; +wire [17:0] Q_3 = ITOP.iow1.arr[1]; +wire [17:0] Q_4 = ITOP.iow0.arr[2]; +wire [17:0] Q_5 = ITOP.iow1.arr[2]; +wire [17:0] Q_6 = ITOP.iow0.arr[3]; +wire [17:0] Q_7 = ITOP.iow1.arr[3]; +wire [17:0] Q_8 = ITOP.iow0.arr[4]; +wire [17:0] Q_9 = ITOP.iow1.arr[4]; +wire [17:0] Q_10 = ITOP.iow0.arr[5]; +wire [17:0] Q_11 = ITOP.iow1.arr[5]; +wire [17:0] Q_12 = ITOP.iow0.arr[6]; +wire [17:0] Q_13 = ITOP.iow1.arr[6]; +wire [17:0] Q_14 = ITOP.iow0.arr[7]; +wire [17:0] Q_15 = ITOP.iow1.arr[7]; +wire [17:0] Q_16 = ITOP.iow0.arr[8]; +wire [17:0] Q_17 = ITOP.iow1.arr[8]; +wire [17:0] Q_18 = ITOP.iow0.arr[9]; +wire [17:0] Q_19 = ITOP.iow1.arr[9]; +wire [17:0] Q_20 = ITOP.iow0.arr[10]; +wire [17:0] Q_21 = ITOP.iow1.arr[10]; +wire [17:0] Q_22 = ITOP.iow0.arr[11]; +wire [17:0] Q_23 = ITOP.iow1.arr[11]; +wire [17:0] Q_24 = ITOP.iow0.arr[12]; +wire [17:0] Q_25 = ITOP.iow1.arr[12]; +wire [17:0] Q_26 = ITOP.iow0.arr[13]; +wire [17:0] Q_27 = ITOP.iow1.arr[13]; +wire [17:0] Q_28 = ITOP.iow0.arr[14]; +wire [17:0] Q_29 = ITOP.iow1.arr[14]; +wire [17:0] Q_30 = ITOP.iow0.arr[15]; +wire [17:0] Q_31 = ITOP.iow1.arr[15]; +wire [17:0] Q_32 = ITOP.iow0.arr[16]; +wire [17:0] Q_33 = ITOP.iow1.arr[16]; +wire [17:0] Q_34 = ITOP.iow0.arr[17]; +wire [17:0] Q_35 = ITOP.iow1.arr[17]; +wire [17:0] Q_36 = ITOP.iow0.arr[18]; +wire [17:0] Q_37 = ITOP.iow1.arr[18]; +wire [17:0] Q_38 = ITOP.iow0.arr[19]; +wire [17:0] Q_39 = ITOP.iow1.arr[19]; +wire [17:0] Q_40 = ITOP.iow0.arr[20]; +wire [17:0] Q_41 = ITOP.iow1.arr[20]; +wire [17:0] Q_42 = ITOP.iow0.arr[21]; +wire [17:0] Q_43 = ITOP.iow1.arr[21]; +wire [17:0] Q_44 = ITOP.iow0.arr[22]; +wire [17:0] Q_45 = ITOP.iow1.arr[22]; +wire [17:0] Q_46 = ITOP.iow0.arr[23]; +wire [17:0] Q_47 = ITOP.iow1.arr[23]; +wire [17:0] Q_48 = ITOP.iow0.arr[24]; +wire [17:0] Q_49 = ITOP.iow1.arr[24]; +wire [17:0] Q_50 = ITOP.iow0.arr[25]; +wire [17:0] Q_51 = ITOP.iow1.arr[25]; +wire [17:0] Q_52 = ITOP.iow0.arr[26]; +wire [17:0] Q_53 = ITOP.iow1.arr[26]; +wire [17:0] Q_54 = ITOP.iow0.arr[27]; +wire [17:0] Q_55 = ITOP.iow1.arr[27]; +wire [17:0] Q_56 = ITOP.iow0.arr[28]; +wire [17:0] Q_57 = ITOP.iow1.arr[28]; +wire [17:0] Q_58 = ITOP.iow0.arr[29]; +wire [17:0] Q_59 = ITOP.iow1.arr[29]; +wire [17:0] Q_60 = ITOP.iow0.arr[30]; +wire [17:0] Q_61 = ITOP.iow1.arr[30]; +wire [17:0] Q_62 = ITOP.iow0.arr[31]; +wire [17:0] Q_63 = ITOP.iow1.arr[31]; +wire [17:0] Q_64 = ITOP.iow0.arr[32]; +wire [17:0] Q_65 = ITOP.iow1.arr[32]; +wire [17:0] Q_66 = ITOP.iow0.arr[33]; +wire [17:0] Q_67 = ITOP.iow1.arr[33]; +wire [17:0] Q_68 = ITOP.iow0.arr[34]; +wire [17:0] Q_69 = ITOP.iow1.arr[34]; +wire [17:0] Q_70 = ITOP.iow0.arr[35]; +wire [17:0] Q_71 = ITOP.iow1.arr[35]; +wire [17:0] Q_72 = ITOP.iow0.arr[36]; +wire [17:0] Q_73 = ITOP.iow1.arr[36]; +wire [17:0] Q_74 = ITOP.iow0.arr[37]; +wire [17:0] Q_75 = ITOP.iow1.arr[37]; +wire [17:0] Q_76 = ITOP.iow0.arr[38]; +wire [17:0] Q_77 = ITOP.iow1.arr[38]; +wire [17:0] Q_78 = ITOP.iow0.arr[39]; +wire [17:0] Q_79 = ITOP.iow1.arr[39]; +wire [17:0] Q_80 = ITOP.iow0.arr[40]; +wire [17:0] Q_81 = ITOP.iow1.arr[40]; +wire [17:0] Q_82 = ITOP.iow0.arr[41]; +wire [17:0] Q_83 = ITOP.iow1.arr[41]; +wire [17:0] Q_84 = ITOP.iow0.arr[42]; +wire [17:0] Q_85 = ITOP.iow1.arr[42]; +wire [17:0] Q_86 = ITOP.iow0.arr[43]; +wire [17:0] Q_87 = ITOP.iow1.arr[43]; +wire [17:0] Q_88 = ITOP.iow0.arr[44]; +wire [17:0] Q_89 = ITOP.iow1.arr[44]; +wire [17:0] Q_90 = ITOP.iow0.arr[45]; +wire [17:0] Q_91 = ITOP.iow1.arr[45]; +wire [17:0] Q_92 = ITOP.iow0.arr[46]; +wire [17:0] Q_93 = ITOP.iow1.arr[46]; +wire [17:0] Q_94 = ITOP.iow0.arr[47]; +wire [17:0] Q_95 = ITOP.iow1.arr[47]; +wire [17:0] Q_96 = ITOP.iow0.arr[48]; +wire [17:0] Q_97 = ITOP.iow1.arr[48]; +wire [17:0] Q_98 = ITOP.iow0.arr[49]; +wire [17:0] Q_99 = ITOP.iow1.arr[49]; +wire [17:0] Q_100 = ITOP.iow0.arr[50]; +wire [17:0] Q_101 = ITOP.iow1.arr[50]; +wire [17:0] Q_102 = ITOP.iow0.arr[51]; +wire [17:0] Q_103 = ITOP.iow1.arr[51]; +wire [17:0] Q_104 = ITOP.iow0.arr[52]; +wire [17:0] Q_105 = ITOP.iow1.arr[52]; +wire [17:0] Q_106 = ITOP.iow0.arr[53]; +wire [17:0] Q_107 = ITOP.iow1.arr[53]; +wire [17:0] Q_108 = ITOP.iow0.arr[54]; +wire [17:0] Q_109 = ITOP.iow1.arr[54]; +wire [17:0] Q_110 = ITOP.iow0.arr[55]; +wire [17:0] Q_111 = ITOP.iow1.arr[55]; +wire [17:0] Q_112 = ITOP.iow0.arr[56]; +wire [17:0] Q_113 = ITOP.iow1.arr[56]; +wire [17:0] Q_114 = ITOP.iow0.arr[57]; +wire [17:0] Q_115 = ITOP.iow1.arr[57]; +wire [17:0] Q_116 = ITOP.iow0.arr[58]; +wire [17:0] Q_117 = ITOP.iow1.arr[58]; +wire [17:0] Q_118 = ITOP.iow0.arr[59]; +wire [17:0] Q_119 = ITOP.iow1.arr[59]; +wire [17:0] Q_120 = ITOP.iow0.arr[60]; +wire [17:0] Q_121 = ITOP.iow1.arr[60]; +wire [17:0] Q_122 = ITOP.iow0.arr[61]; +wire [17:0] Q_123 = ITOP.iow1.arr[61]; +wire [17:0] Q_124 = ITOP.iow0.arr[62]; +wire [17:0] Q_125 = ITOP.iow1.arr[62]; +wire [17:0] Q_126 = ITOP.iow0.arr[63]; +wire [17:0] Q_127 = ITOP.iow1.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [17:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [17:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [17:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [17:0] WD_FF; + reg [17:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [17:0] mem[127:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [17:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [17:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_128X18_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [17:0] WD; +input [7:0] RA, WA; +output [17:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [17:0] WDQ; + wire [17:0] WDBQ; + wire [17:0] WMNexp; + wire [17:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [17:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {18{1'b0}}; + assign SHFT = {18{1'b1}}; + reg [17:0] WDQ_pr; + wire [17:0] WDBQ_pr; + assign WMNexp = {18{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[17:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [17:0] dout; + wire [17:0] RD; + wire RD_rdnt; + wire [17:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [17:0] RDBYPASS = {18{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 128 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[7:7]); +// Max address is 128 --> ['1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [17:0] force_x; +`ifndef SYNTHESIS + assign force_x = {18{1'bx}}; +`else + assign force_x = {18{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [17:0] rmuxd0, rmuxd1; + wire [17:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {18{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {18{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {18{RdClk0}} & ~dout0 ; + assign rmuxd1 = {18{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[17:0] <= (rmuxd0[17:0] | rmuxd1[17:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_128X18_GL_M2_D2_ram # (64, 18, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_128X18_GL_M2_D2_ram # (64, 18, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [17:0] data; + reg [17:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[6:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[6:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [17:0] mem_read_bank; +input [6:0] addr; +reg [17:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[6:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_128X18_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 18; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [17:0] val; + integer i; + begin + for (i=0; i<128; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [17:0] val; + integer i; + begin + val = {18{fill_bit}}; + for (i=0; i<128; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [17:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [18-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {18 {1'b1}} `else { $RollPLI(0,{18{1'b1}}) } `endif ; + else raminit_fullval = {18 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[6:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [35:0] mem_phys_read_padr; +input [5:0] addr; + reg [35:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [36-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {36 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {36 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [17:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=17; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [35:0] mem_phys_read_ladr; +input [6:0] addr; + reg [5:0] paddr; + reg [35:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [36-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {36 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {36 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [17:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=17; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [35:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [35:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [36-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {36 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {36 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [17:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[6:1]) : 18'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[6:1]) : 18'bx; + for (i=0; i<=17; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [35:0] data; + reg [17:0] wr[1:0]; + integer i; + begin + for (i=0; i<=17; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [35:0] mon_bit_w; +input [5:0] addr; + reg [35:0] mon_row; + reg [17:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=17; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [35:0] mon_bit_r; +input [5:0] addr; + reg [35:0] mon_row; + reg [17:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=17; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [35:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<36; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [17:0] Q_0 = ITOP.iow0.arr[0]; +wire [17:0] Q_1 = ITOP.iow1.arr[0]; +wire [17:0] Q_2 = ITOP.iow0.arr[1]; +wire [17:0] Q_3 = ITOP.iow1.arr[1]; +wire [17:0] Q_4 = ITOP.iow0.arr[2]; +wire [17:0] Q_5 = ITOP.iow1.arr[2]; +wire [17:0] Q_6 = ITOP.iow0.arr[3]; +wire [17:0] Q_7 = ITOP.iow1.arr[3]; +wire [17:0] Q_8 = ITOP.iow0.arr[4]; +wire [17:0] Q_9 = ITOP.iow1.arr[4]; +wire [17:0] Q_10 = ITOP.iow0.arr[5]; +wire [17:0] Q_11 = ITOP.iow1.arr[5]; +wire [17:0] Q_12 = ITOP.iow0.arr[6]; +wire [17:0] Q_13 = ITOP.iow1.arr[6]; +wire [17:0] Q_14 = ITOP.iow0.arr[7]; +wire [17:0] Q_15 = ITOP.iow1.arr[7]; +wire [17:0] Q_16 = ITOP.iow0.arr[8]; +wire [17:0] Q_17 = ITOP.iow1.arr[8]; +wire [17:0] Q_18 = ITOP.iow0.arr[9]; +wire [17:0] Q_19 = ITOP.iow1.arr[9]; +wire [17:0] Q_20 = ITOP.iow0.arr[10]; +wire [17:0] Q_21 = ITOP.iow1.arr[10]; +wire [17:0] Q_22 = ITOP.iow0.arr[11]; +wire [17:0] Q_23 = ITOP.iow1.arr[11]; +wire [17:0] Q_24 = ITOP.iow0.arr[12]; +wire [17:0] Q_25 = ITOP.iow1.arr[12]; +wire [17:0] Q_26 = ITOP.iow0.arr[13]; +wire [17:0] Q_27 = ITOP.iow1.arr[13]; +wire [17:0] Q_28 = ITOP.iow0.arr[14]; +wire [17:0] Q_29 = ITOP.iow1.arr[14]; +wire [17:0] Q_30 = ITOP.iow0.arr[15]; +wire [17:0] Q_31 = ITOP.iow1.arr[15]; +wire [17:0] Q_32 = ITOP.iow0.arr[16]; +wire [17:0] Q_33 = ITOP.iow1.arr[16]; +wire [17:0] Q_34 = ITOP.iow0.arr[17]; +wire [17:0] Q_35 = ITOP.iow1.arr[17]; +wire [17:0] Q_36 = ITOP.iow0.arr[18]; +wire [17:0] Q_37 = ITOP.iow1.arr[18]; +wire [17:0] Q_38 = ITOP.iow0.arr[19]; +wire [17:0] Q_39 = ITOP.iow1.arr[19]; +wire [17:0] Q_40 = ITOP.iow0.arr[20]; +wire [17:0] Q_41 = ITOP.iow1.arr[20]; +wire [17:0] Q_42 = ITOP.iow0.arr[21]; +wire [17:0] Q_43 = ITOP.iow1.arr[21]; +wire [17:0] Q_44 = ITOP.iow0.arr[22]; +wire [17:0] Q_45 = ITOP.iow1.arr[22]; +wire [17:0] Q_46 = ITOP.iow0.arr[23]; +wire [17:0] Q_47 = ITOP.iow1.arr[23]; +wire [17:0] Q_48 = ITOP.iow0.arr[24]; +wire [17:0] Q_49 = ITOP.iow1.arr[24]; +wire [17:0] Q_50 = ITOP.iow0.arr[25]; +wire [17:0] Q_51 = ITOP.iow1.arr[25]; +wire [17:0] Q_52 = ITOP.iow0.arr[26]; +wire [17:0] Q_53 = ITOP.iow1.arr[26]; +wire [17:0] Q_54 = ITOP.iow0.arr[27]; +wire [17:0] Q_55 = ITOP.iow1.arr[27]; +wire [17:0] Q_56 = ITOP.iow0.arr[28]; +wire [17:0] Q_57 = ITOP.iow1.arr[28]; +wire [17:0] Q_58 = ITOP.iow0.arr[29]; +wire [17:0] Q_59 = ITOP.iow1.arr[29]; +wire [17:0] Q_60 = ITOP.iow0.arr[30]; +wire [17:0] Q_61 = ITOP.iow1.arr[30]; +wire [17:0] Q_62 = ITOP.iow0.arr[31]; +wire [17:0] Q_63 = ITOP.iow1.arr[31]; +wire [17:0] Q_64 = ITOP.iow0.arr[32]; +wire [17:0] Q_65 = ITOP.iow1.arr[32]; +wire [17:0] Q_66 = ITOP.iow0.arr[33]; +wire [17:0] Q_67 = ITOP.iow1.arr[33]; +wire [17:0] Q_68 = ITOP.iow0.arr[34]; +wire [17:0] Q_69 = ITOP.iow1.arr[34]; +wire [17:0] Q_70 = ITOP.iow0.arr[35]; +wire [17:0] Q_71 = ITOP.iow1.arr[35]; +wire [17:0] Q_72 = ITOP.iow0.arr[36]; +wire [17:0] Q_73 = ITOP.iow1.arr[36]; +wire [17:0] Q_74 = ITOP.iow0.arr[37]; +wire [17:0] Q_75 = ITOP.iow1.arr[37]; +wire [17:0] Q_76 = ITOP.iow0.arr[38]; +wire [17:0] Q_77 = ITOP.iow1.arr[38]; +wire [17:0] Q_78 = ITOP.iow0.arr[39]; +wire [17:0] Q_79 = ITOP.iow1.arr[39]; +wire [17:0] Q_80 = ITOP.iow0.arr[40]; +wire [17:0] Q_81 = ITOP.iow1.arr[40]; +wire [17:0] Q_82 = ITOP.iow0.arr[41]; +wire [17:0] Q_83 = ITOP.iow1.arr[41]; +wire [17:0] Q_84 = ITOP.iow0.arr[42]; +wire [17:0] Q_85 = ITOP.iow1.arr[42]; +wire [17:0] Q_86 = ITOP.iow0.arr[43]; +wire [17:0] Q_87 = ITOP.iow1.arr[43]; +wire [17:0] Q_88 = ITOP.iow0.arr[44]; +wire [17:0] Q_89 = ITOP.iow1.arr[44]; +wire [17:0] Q_90 = ITOP.iow0.arr[45]; +wire [17:0] Q_91 = ITOP.iow1.arr[45]; +wire [17:0] Q_92 = ITOP.iow0.arr[46]; +wire [17:0] Q_93 = ITOP.iow1.arr[46]; +wire [17:0] Q_94 = ITOP.iow0.arr[47]; +wire [17:0] Q_95 = ITOP.iow1.arr[47]; +wire [17:0] Q_96 = ITOP.iow0.arr[48]; +wire [17:0] Q_97 = ITOP.iow1.arr[48]; +wire [17:0] Q_98 = ITOP.iow0.arr[49]; +wire [17:0] Q_99 = ITOP.iow1.arr[49]; +wire [17:0] Q_100 = ITOP.iow0.arr[50]; +wire [17:0] Q_101 = ITOP.iow1.arr[50]; +wire [17:0] Q_102 = ITOP.iow0.arr[51]; +wire [17:0] Q_103 = ITOP.iow1.arr[51]; +wire [17:0] Q_104 = ITOP.iow0.arr[52]; +wire [17:0] Q_105 = ITOP.iow1.arr[52]; +wire [17:0] Q_106 = ITOP.iow0.arr[53]; +wire [17:0] Q_107 = ITOP.iow1.arr[53]; +wire [17:0] Q_108 = ITOP.iow0.arr[54]; +wire [17:0] Q_109 = ITOP.iow1.arr[54]; +wire [17:0] Q_110 = ITOP.iow0.arr[55]; +wire [17:0] Q_111 = ITOP.iow1.arr[55]; +wire [17:0] Q_112 = ITOP.iow0.arr[56]; +wire [17:0] Q_113 = ITOP.iow1.arr[56]; +wire [17:0] Q_114 = ITOP.iow0.arr[57]; +wire [17:0] Q_115 = ITOP.iow1.arr[57]; +wire [17:0] Q_116 = ITOP.iow0.arr[58]; +wire [17:0] Q_117 = ITOP.iow1.arr[58]; +wire [17:0] Q_118 = ITOP.iow0.arr[59]; +wire [17:0] Q_119 = ITOP.iow1.arr[59]; +wire [17:0] Q_120 = ITOP.iow0.arr[60]; +wire [17:0] Q_121 = ITOP.iow1.arr[60]; +wire [17:0] Q_122 = ITOP.iow0.arr[61]; +wire [17:0] Q_123 = ITOP.iow1.arr[61]; +wire [17:0] Q_124 = ITOP.iow0.arr[62]; +wire [17:0] Q_125 = ITOP.iow1.arr[62]; +wire [17:0] Q_126 = ITOP.iow0.arr[63]; +wire [17:0] Q_127 = ITOP.iow1.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [17:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [17:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [17:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [17:0] WD_FF; + reg [17:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [17:0] mem[127:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [17:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [17:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_128X18_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [17:0] WD; +input [7:0] RA, WA; +output [17:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [17:0] WDQ; + wire [17:0] WDBQ; + wire [17:0] WMNexp; + wire [17:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [17:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {18{1'b0}}; + assign SHFT = {18{1'b1}}; + reg [17:0] WDQ_pr; + wire [17:0] WDBQ_pr; + assign WMNexp = {18{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[17:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [17:0] dout; + wire [17:0] RD; + wire RD_rdnt; + wire [17:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [17:0] RDBYPASS = {18{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 128 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[7:7]); +// Max address is 128 --> ['1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [17:0] force_x; +`ifndef SYNTHESIS + assign force_x = {18{1'bx}}; +`else + assign force_x = {18{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [17:0] rmuxd0, rmuxd1; + wire [17:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {18{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {18{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {18{RdClk0}} & ~dout0 ; + assign rmuxd1 = {18{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[17:0] <= (rmuxd0[17:0] | rmuxd1[17:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_128X18_GL_M2_D2_ram # (64, 18, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_128X18_GL_M2_D2_ram # (64, 18, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [17:0] data; + reg [17:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[6:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[6:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [17:0] mem_read_bank; +input [6:0] addr; +reg [17:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[6:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_128X18_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 18; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [255:0] val; + integer i; + begin + for (i=0; i<128; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [255:0] val; + integer i; + begin + val = {256{fill_bit}}; + for (i=0; i<128; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [255:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [255:0] data; + reg [255:0] wr[0:0]; + integer i; + begin + for (i=0; i<=255; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [255:0] Q_0 = ITOP.iow0.arr[0]; +wire [255:0] Q_1 = ITOP.iow0.arr[1]; +wire [255:0] Q_2 = ITOP.iow0.arr[2]; +wire [255:0] Q_3 = ITOP.iow0.arr[3]; +wire [255:0] Q_4 = ITOP.iow0.arr[4]; +wire [255:0] Q_5 = ITOP.iow0.arr[5]; +wire [255:0] Q_6 = ITOP.iow0.arr[6]; +wire [255:0] Q_7 = ITOP.iow0.arr[7]; +wire [255:0] Q_8 = ITOP.iow0.arr[8]; +wire [255:0] Q_9 = ITOP.iow0.arr[9]; +wire [255:0] Q_10 = ITOP.iow0.arr[10]; +wire [255:0] Q_11 = ITOP.iow0.arr[11]; +wire [255:0] Q_12 = ITOP.iow0.arr[12]; +wire [255:0] Q_13 = ITOP.iow0.arr[13]; +wire [255:0] Q_14 = ITOP.iow0.arr[14]; +wire [255:0] Q_15 = ITOP.iow0.arr[15]; +wire [255:0] Q_16 = ITOP.iow0.arr[16]; +wire [255:0] Q_17 = ITOP.iow0.arr[17]; +wire [255:0] Q_18 = ITOP.iow0.arr[18]; +wire [255:0] Q_19 = ITOP.iow0.arr[19]; +wire [255:0] Q_20 = ITOP.iow0.arr[20]; +wire [255:0] Q_21 = ITOP.iow0.arr[21]; +wire [255:0] Q_22 = ITOP.iow0.arr[22]; +wire [255:0] Q_23 = ITOP.iow0.arr[23]; +wire [255:0] Q_24 = ITOP.iow0.arr[24]; +wire [255:0] Q_25 = ITOP.iow0.arr[25]; +wire [255:0] Q_26 = ITOP.iow0.arr[26]; +wire [255:0] Q_27 = ITOP.iow0.arr[27]; +wire [255:0] Q_28 = ITOP.iow0.arr[28]; +wire [255:0] Q_29 = ITOP.iow0.arr[29]; +wire [255:0] Q_30 = ITOP.iow0.arr[30]; +wire [255:0] Q_31 = ITOP.iow0.arr[31]; +wire [255:0] Q_32 = ITOP.iow0.arr[32]; +wire [255:0] Q_33 = ITOP.iow0.arr[33]; +wire [255:0] Q_34 = ITOP.iow0.arr[34]; +wire [255:0] Q_35 = ITOP.iow0.arr[35]; +wire [255:0] Q_36 = ITOP.iow0.arr[36]; +wire [255:0] Q_37 = ITOP.iow0.arr[37]; +wire [255:0] Q_38 = ITOP.iow0.arr[38]; +wire [255:0] Q_39 = ITOP.iow0.arr[39]; +wire [255:0] Q_40 = ITOP.iow0.arr[40]; +wire [255:0] Q_41 = ITOP.iow0.arr[41]; +wire [255:0] Q_42 = ITOP.iow0.arr[42]; +wire [255:0] Q_43 = ITOP.iow0.arr[43]; +wire [255:0] Q_44 = ITOP.iow0.arr[44]; +wire [255:0] Q_45 = ITOP.iow0.arr[45]; +wire [255:0] Q_46 = ITOP.iow0.arr[46]; +wire [255:0] Q_47 = ITOP.iow0.arr[47]; +wire [255:0] Q_48 = ITOP.iow0.arr[48]; +wire [255:0] Q_49 = ITOP.iow0.arr[49]; +wire [255:0] Q_50 = ITOP.iow0.arr[50]; +wire [255:0] Q_51 = ITOP.iow0.arr[51]; +wire [255:0] Q_52 = ITOP.iow0.arr[52]; +wire [255:0] Q_53 = ITOP.iow0.arr[53]; +wire [255:0] Q_54 = ITOP.iow0.arr[54]; +wire [255:0] Q_55 = ITOP.iow0.arr[55]; +wire [255:0] Q_56 = ITOP.iow0.arr[56]; +wire [255:0] Q_57 = ITOP.iow0.arr[57]; +wire [255:0] Q_58 = ITOP.iow0.arr[58]; +wire [255:0] Q_59 = ITOP.iow0.arr[59]; +wire [255:0] Q_60 = ITOP.iow0.arr[60]; +wire [255:0] Q_61 = ITOP.iow0.arr[61]; +wire [255:0] Q_62 = ITOP.iow0.arr[62]; +wire [255:0] Q_63 = ITOP.iow0.arr[63]; +wire [255:0] Q_64 = ITOP.iow0.arr[64]; +wire [255:0] Q_65 = ITOP.iow0.arr[65]; +wire [255:0] Q_66 = ITOP.iow0.arr[66]; +wire [255:0] Q_67 = ITOP.iow0.arr[67]; +wire [255:0] Q_68 = ITOP.iow0.arr[68]; +wire [255:0] Q_69 = ITOP.iow0.arr[69]; +wire [255:0] Q_70 = ITOP.iow0.arr[70]; +wire [255:0] Q_71 = ITOP.iow0.arr[71]; +wire [255:0] Q_72 = ITOP.iow0.arr[72]; +wire [255:0] Q_73 = ITOP.iow0.arr[73]; +wire [255:0] Q_74 = ITOP.iow0.arr[74]; +wire [255:0] Q_75 = ITOP.iow0.arr[75]; +wire [255:0] Q_76 = ITOP.iow0.arr[76]; +wire [255:0] Q_77 = ITOP.iow0.arr[77]; +wire [255:0] Q_78 = ITOP.iow0.arr[78]; +wire [255:0] Q_79 = ITOP.iow0.arr[79]; +wire [255:0] Q_80 = ITOP.iow0.arr[80]; +wire [255:0] Q_81 = ITOP.iow0.arr[81]; +wire [255:0] Q_82 = ITOP.iow0.arr[82]; +wire [255:0] Q_83 = ITOP.iow0.arr[83]; +wire [255:0] Q_84 = ITOP.iow0.arr[84]; +wire [255:0] Q_85 = ITOP.iow0.arr[85]; +wire [255:0] Q_86 = ITOP.iow0.arr[86]; +wire [255:0] Q_87 = ITOP.iow0.arr[87]; +wire [255:0] Q_88 = ITOP.iow0.arr[88]; +wire [255:0] Q_89 = ITOP.iow0.arr[89]; +wire [255:0] Q_90 = ITOP.iow0.arr[90]; +wire [255:0] Q_91 = ITOP.iow0.arr[91]; +wire [255:0] Q_92 = ITOP.iow0.arr[92]; +wire [255:0] Q_93 = ITOP.iow0.arr[93]; +wire [255:0] Q_94 = ITOP.iow0.arr[94]; +wire [255:0] Q_95 = ITOP.iow0.arr[95]; +wire [255:0] Q_96 = ITOP.iow0.arr[96]; +wire [255:0] Q_97 = ITOP.iow0.arr[97]; +wire [255:0] Q_98 = ITOP.iow0.arr[98]; +wire [255:0] Q_99 = ITOP.iow0.arr[99]; +wire [255:0] Q_100 = ITOP.iow0.arr[100]; +wire [255:0] Q_101 = ITOP.iow0.arr[101]; +wire [255:0] Q_102 = ITOP.iow0.arr[102]; +wire [255:0] Q_103 = ITOP.iow0.arr[103]; +wire [255:0] Q_104 = ITOP.iow0.arr[104]; +wire [255:0] Q_105 = ITOP.iow0.arr[105]; +wire [255:0] Q_106 = ITOP.iow0.arr[106]; +wire [255:0] Q_107 = ITOP.iow0.arr[107]; +wire [255:0] Q_108 = ITOP.iow0.arr[108]; +wire [255:0] Q_109 = ITOP.iow0.arr[109]; +wire [255:0] Q_110 = ITOP.iow0.arr[110]; +wire [255:0] Q_111 = ITOP.iow0.arr[111]; +wire [255:0] Q_112 = ITOP.iow0.arr[112]; +wire [255:0] Q_113 = ITOP.iow0.arr[113]; +wire [255:0] Q_114 = ITOP.iow0.arr[114]; +wire [255:0] Q_115 = ITOP.iow0.arr[115]; +wire [255:0] Q_116 = ITOP.iow0.arr[116]; +wire [255:0] Q_117 = ITOP.iow0.arr[117]; +wire [255:0] Q_118 = ITOP.iow0.arr[118]; +wire [255:0] Q_119 = ITOP.iow0.arr[119]; +wire [255:0] Q_120 = ITOP.iow0.arr[120]; +wire [255:0] Q_121 = ITOP.iow0.arr[121]; +wire [255:0] Q_122 = ITOP.iow0.arr[122]; +wire [255:0] Q_123 = ITOP.iow0.arr[123]; +wire [255:0] Q_124 = ITOP.iow0.arr[124]; +wire [255:0] Q_125 = ITOP.iow0.arr[125]; +wire [255:0] Q_126 = ITOP.iow0.arr[126]; +wire [255:0] Q_127 = ITOP.iow0.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [255:0] WD_FF; + reg [255:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [255:0] mem[127:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [255:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [255:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_128X256_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [255:0] WD; +input [6:0] RA, WA; +output [255:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [255:0] WDQ; + wire [255:0] WDBQ; + wire [255:0] WMNexp; + wire [255:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [255:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {256{1'b0}}; + assign SHFT = {256{1'b1}}; + reg [255:0] WDQ_pr; + wire [255:0] WDBQ_pr; + assign WMNexp = {256{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[255:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [255:0] dout; + wire [255:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [255:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [255:0] RDBYPASS = {256{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 128 --> ['1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [255:0] force_x; +`ifndef SYNTHESIS + assign force_x = {256{1'bx}}; +`else + assign force_x = {256{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [255:0] rmuxd0; + wire [255:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {256{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {256{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[255:0] <= (rmuxd0[255:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_128X256_GL_M1_D2_ram # (128, 256, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [255:0] data; + reg [255:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [255:0] mem_read_bank; +input [6:0] addr; +reg [255:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_128X256_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 256; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [255:0] val; + integer i; + begin + for (i=0; i<128; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [255:0] val; + integer i; + begin + val = {256{fill_bit}}; + for (i=0; i<128; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [255:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [255:0] data; + reg [255:0] wr[0:0]; + integer i; + begin + for (i=0; i<=255; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [255:0] Q_0 = ITOP.iow0.arr[0]; +wire [255:0] Q_1 = ITOP.iow0.arr[1]; +wire [255:0] Q_2 = ITOP.iow0.arr[2]; +wire [255:0] Q_3 = ITOP.iow0.arr[3]; +wire [255:0] Q_4 = ITOP.iow0.arr[4]; +wire [255:0] Q_5 = ITOP.iow0.arr[5]; +wire [255:0] Q_6 = ITOP.iow0.arr[6]; +wire [255:0] Q_7 = ITOP.iow0.arr[7]; +wire [255:0] Q_8 = ITOP.iow0.arr[8]; +wire [255:0] Q_9 = ITOP.iow0.arr[9]; +wire [255:0] Q_10 = ITOP.iow0.arr[10]; +wire [255:0] Q_11 = ITOP.iow0.arr[11]; +wire [255:0] Q_12 = ITOP.iow0.arr[12]; +wire [255:0] Q_13 = ITOP.iow0.arr[13]; +wire [255:0] Q_14 = ITOP.iow0.arr[14]; +wire [255:0] Q_15 = ITOP.iow0.arr[15]; +wire [255:0] Q_16 = ITOP.iow0.arr[16]; +wire [255:0] Q_17 = ITOP.iow0.arr[17]; +wire [255:0] Q_18 = ITOP.iow0.arr[18]; +wire [255:0] Q_19 = ITOP.iow0.arr[19]; +wire [255:0] Q_20 = ITOP.iow0.arr[20]; +wire [255:0] Q_21 = ITOP.iow0.arr[21]; +wire [255:0] Q_22 = ITOP.iow0.arr[22]; +wire [255:0] Q_23 = ITOP.iow0.arr[23]; +wire [255:0] Q_24 = ITOP.iow0.arr[24]; +wire [255:0] Q_25 = ITOP.iow0.arr[25]; +wire [255:0] Q_26 = ITOP.iow0.arr[26]; +wire [255:0] Q_27 = ITOP.iow0.arr[27]; +wire [255:0] Q_28 = ITOP.iow0.arr[28]; +wire [255:0] Q_29 = ITOP.iow0.arr[29]; +wire [255:0] Q_30 = ITOP.iow0.arr[30]; +wire [255:0] Q_31 = ITOP.iow0.arr[31]; +wire [255:0] Q_32 = ITOP.iow0.arr[32]; +wire [255:0] Q_33 = ITOP.iow0.arr[33]; +wire [255:0] Q_34 = ITOP.iow0.arr[34]; +wire [255:0] Q_35 = ITOP.iow0.arr[35]; +wire [255:0] Q_36 = ITOP.iow0.arr[36]; +wire [255:0] Q_37 = ITOP.iow0.arr[37]; +wire [255:0] Q_38 = ITOP.iow0.arr[38]; +wire [255:0] Q_39 = ITOP.iow0.arr[39]; +wire [255:0] Q_40 = ITOP.iow0.arr[40]; +wire [255:0] Q_41 = ITOP.iow0.arr[41]; +wire [255:0] Q_42 = ITOP.iow0.arr[42]; +wire [255:0] Q_43 = ITOP.iow0.arr[43]; +wire [255:0] Q_44 = ITOP.iow0.arr[44]; +wire [255:0] Q_45 = ITOP.iow0.arr[45]; +wire [255:0] Q_46 = ITOP.iow0.arr[46]; +wire [255:0] Q_47 = ITOP.iow0.arr[47]; +wire [255:0] Q_48 = ITOP.iow0.arr[48]; +wire [255:0] Q_49 = ITOP.iow0.arr[49]; +wire [255:0] Q_50 = ITOP.iow0.arr[50]; +wire [255:0] Q_51 = ITOP.iow0.arr[51]; +wire [255:0] Q_52 = ITOP.iow0.arr[52]; +wire [255:0] Q_53 = ITOP.iow0.arr[53]; +wire [255:0] Q_54 = ITOP.iow0.arr[54]; +wire [255:0] Q_55 = ITOP.iow0.arr[55]; +wire [255:0] Q_56 = ITOP.iow0.arr[56]; +wire [255:0] Q_57 = ITOP.iow0.arr[57]; +wire [255:0] Q_58 = ITOP.iow0.arr[58]; +wire [255:0] Q_59 = ITOP.iow0.arr[59]; +wire [255:0] Q_60 = ITOP.iow0.arr[60]; +wire [255:0] Q_61 = ITOP.iow0.arr[61]; +wire [255:0] Q_62 = ITOP.iow0.arr[62]; +wire [255:0] Q_63 = ITOP.iow0.arr[63]; +wire [255:0] Q_64 = ITOP.iow0.arr[64]; +wire [255:0] Q_65 = ITOP.iow0.arr[65]; +wire [255:0] Q_66 = ITOP.iow0.arr[66]; +wire [255:0] Q_67 = ITOP.iow0.arr[67]; +wire [255:0] Q_68 = ITOP.iow0.arr[68]; +wire [255:0] Q_69 = ITOP.iow0.arr[69]; +wire [255:0] Q_70 = ITOP.iow0.arr[70]; +wire [255:0] Q_71 = ITOP.iow0.arr[71]; +wire [255:0] Q_72 = ITOP.iow0.arr[72]; +wire [255:0] Q_73 = ITOP.iow0.arr[73]; +wire [255:0] Q_74 = ITOP.iow0.arr[74]; +wire [255:0] Q_75 = ITOP.iow0.arr[75]; +wire [255:0] Q_76 = ITOP.iow0.arr[76]; +wire [255:0] Q_77 = ITOP.iow0.arr[77]; +wire [255:0] Q_78 = ITOP.iow0.arr[78]; +wire [255:0] Q_79 = ITOP.iow0.arr[79]; +wire [255:0] Q_80 = ITOP.iow0.arr[80]; +wire [255:0] Q_81 = ITOP.iow0.arr[81]; +wire [255:0] Q_82 = ITOP.iow0.arr[82]; +wire [255:0] Q_83 = ITOP.iow0.arr[83]; +wire [255:0] Q_84 = ITOP.iow0.arr[84]; +wire [255:0] Q_85 = ITOP.iow0.arr[85]; +wire [255:0] Q_86 = ITOP.iow0.arr[86]; +wire [255:0] Q_87 = ITOP.iow0.arr[87]; +wire [255:0] Q_88 = ITOP.iow0.arr[88]; +wire [255:0] Q_89 = ITOP.iow0.arr[89]; +wire [255:0] Q_90 = ITOP.iow0.arr[90]; +wire [255:0] Q_91 = ITOP.iow0.arr[91]; +wire [255:0] Q_92 = ITOP.iow0.arr[92]; +wire [255:0] Q_93 = ITOP.iow0.arr[93]; +wire [255:0] Q_94 = ITOP.iow0.arr[94]; +wire [255:0] Q_95 = ITOP.iow0.arr[95]; +wire [255:0] Q_96 = ITOP.iow0.arr[96]; +wire [255:0] Q_97 = ITOP.iow0.arr[97]; +wire [255:0] Q_98 = ITOP.iow0.arr[98]; +wire [255:0] Q_99 = ITOP.iow0.arr[99]; +wire [255:0] Q_100 = ITOP.iow0.arr[100]; +wire [255:0] Q_101 = ITOP.iow0.arr[101]; +wire [255:0] Q_102 = ITOP.iow0.arr[102]; +wire [255:0] Q_103 = ITOP.iow0.arr[103]; +wire [255:0] Q_104 = ITOP.iow0.arr[104]; +wire [255:0] Q_105 = ITOP.iow0.arr[105]; +wire [255:0] Q_106 = ITOP.iow0.arr[106]; +wire [255:0] Q_107 = ITOP.iow0.arr[107]; +wire [255:0] Q_108 = ITOP.iow0.arr[108]; +wire [255:0] Q_109 = ITOP.iow0.arr[109]; +wire [255:0] Q_110 = ITOP.iow0.arr[110]; +wire [255:0] Q_111 = ITOP.iow0.arr[111]; +wire [255:0] Q_112 = ITOP.iow0.arr[112]; +wire [255:0] Q_113 = ITOP.iow0.arr[113]; +wire [255:0] Q_114 = ITOP.iow0.arr[114]; +wire [255:0] Q_115 = ITOP.iow0.arr[115]; +wire [255:0] Q_116 = ITOP.iow0.arr[116]; +wire [255:0] Q_117 = ITOP.iow0.arr[117]; +wire [255:0] Q_118 = ITOP.iow0.arr[118]; +wire [255:0] Q_119 = ITOP.iow0.arr[119]; +wire [255:0] Q_120 = ITOP.iow0.arr[120]; +wire [255:0] Q_121 = ITOP.iow0.arr[121]; +wire [255:0] Q_122 = ITOP.iow0.arr[122]; +wire [255:0] Q_123 = ITOP.iow0.arr[123]; +wire [255:0] Q_124 = ITOP.iow0.arr[124]; +wire [255:0] Q_125 = ITOP.iow0.arr[125]; +wire [255:0] Q_126 = ITOP.iow0.arr[126]; +wire [255:0] Q_127 = ITOP.iow0.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [255:0] WD_FF; + reg [255:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [255:0] mem[127:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [255:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [255:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_128X256_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [255:0] WD; +input [6:0] RA, WA; +output [255:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [255:0] WDQ; + wire [255:0] WDBQ; + wire [255:0] WMNexp; + wire [255:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [255:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {256{1'b0}}; + assign SHFT = {256{1'b1}}; + reg [255:0] WDQ_pr; + wire [255:0] WDBQ_pr; + assign WMNexp = {256{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[255:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [255:0] dout; + wire [255:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [255:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [255:0] RDBYPASS = {256{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 128 --> ['1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [255:0] force_x; +`ifndef SYNTHESIS + assign force_x = {256{1'bx}}; +`else + assign force_x = {256{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [255:0] rmuxd0; + wire [255:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {256{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {256{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[255:0] <= (rmuxd0[255:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_128X256_GL_M1_D2_ram # (128, 256, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [255:0] data; + reg [255:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [255:0] mem_read_bank; +input [6:0] addr; +reg [255:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_128X256_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 256; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<128; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<128; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [63:0] mem_phys_read_padr; +input [6:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [63:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [63:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [63:0] data; + reg [63:0] wr[0:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [63:0] mon_bit_w; +input [6:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [63:0] mon_bit_r; +input [6:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [63:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow0.arr[1]; +wire [63:0] Q_2 = ITOP.iow0.arr[2]; +wire [63:0] Q_3 = ITOP.iow0.arr[3]; +wire [63:0] Q_4 = ITOP.iow0.arr[4]; +wire [63:0] Q_5 = ITOP.iow0.arr[5]; +wire [63:0] Q_6 = ITOP.iow0.arr[6]; +wire [63:0] Q_7 = ITOP.iow0.arr[7]; +wire [63:0] Q_8 = ITOP.iow0.arr[8]; +wire [63:0] Q_9 = ITOP.iow0.arr[9]; +wire [63:0] Q_10 = ITOP.iow0.arr[10]; +wire [63:0] Q_11 = ITOP.iow0.arr[11]; +wire [63:0] Q_12 = ITOP.iow0.arr[12]; +wire [63:0] Q_13 = ITOP.iow0.arr[13]; +wire [63:0] Q_14 = ITOP.iow0.arr[14]; +wire [63:0] Q_15 = ITOP.iow0.arr[15]; +wire [63:0] Q_16 = ITOP.iow0.arr[16]; +wire [63:0] Q_17 = ITOP.iow0.arr[17]; +wire [63:0] Q_18 = ITOP.iow0.arr[18]; +wire [63:0] Q_19 = ITOP.iow0.arr[19]; +wire [63:0] Q_20 = ITOP.iow0.arr[20]; +wire [63:0] Q_21 = ITOP.iow0.arr[21]; +wire [63:0] Q_22 = ITOP.iow0.arr[22]; +wire [63:0] Q_23 = ITOP.iow0.arr[23]; +wire [63:0] Q_24 = ITOP.iow0.arr[24]; +wire [63:0] Q_25 = ITOP.iow0.arr[25]; +wire [63:0] Q_26 = ITOP.iow0.arr[26]; +wire [63:0] Q_27 = ITOP.iow0.arr[27]; +wire [63:0] Q_28 = ITOP.iow0.arr[28]; +wire [63:0] Q_29 = ITOP.iow0.arr[29]; +wire [63:0] Q_30 = ITOP.iow0.arr[30]; +wire [63:0] Q_31 = ITOP.iow0.arr[31]; +wire [63:0] Q_32 = ITOP.iow0.arr[32]; +wire [63:0] Q_33 = ITOP.iow0.arr[33]; +wire [63:0] Q_34 = ITOP.iow0.arr[34]; +wire [63:0] Q_35 = ITOP.iow0.arr[35]; +wire [63:0] Q_36 = ITOP.iow0.arr[36]; +wire [63:0] Q_37 = ITOP.iow0.arr[37]; +wire [63:0] Q_38 = ITOP.iow0.arr[38]; +wire [63:0] Q_39 = ITOP.iow0.arr[39]; +wire [63:0] Q_40 = ITOP.iow0.arr[40]; +wire [63:0] Q_41 = ITOP.iow0.arr[41]; +wire [63:0] Q_42 = ITOP.iow0.arr[42]; +wire [63:0] Q_43 = ITOP.iow0.arr[43]; +wire [63:0] Q_44 = ITOP.iow0.arr[44]; +wire [63:0] Q_45 = ITOP.iow0.arr[45]; +wire [63:0] Q_46 = ITOP.iow0.arr[46]; +wire [63:0] Q_47 = ITOP.iow0.arr[47]; +wire [63:0] Q_48 = ITOP.iow0.arr[48]; +wire [63:0] Q_49 = ITOP.iow0.arr[49]; +wire [63:0] Q_50 = ITOP.iow0.arr[50]; +wire [63:0] Q_51 = ITOP.iow0.arr[51]; +wire [63:0] Q_52 = ITOP.iow0.arr[52]; +wire [63:0] Q_53 = ITOP.iow0.arr[53]; +wire [63:0] Q_54 = ITOP.iow0.arr[54]; +wire [63:0] Q_55 = ITOP.iow0.arr[55]; +wire [63:0] Q_56 = ITOP.iow0.arr[56]; +wire [63:0] Q_57 = ITOP.iow0.arr[57]; +wire [63:0] Q_58 = ITOP.iow0.arr[58]; +wire [63:0] Q_59 = ITOP.iow0.arr[59]; +wire [63:0] Q_60 = ITOP.iow0.arr[60]; +wire [63:0] Q_61 = ITOP.iow0.arr[61]; +wire [63:0] Q_62 = ITOP.iow0.arr[62]; +wire [63:0] Q_63 = ITOP.iow0.arr[63]; +wire [63:0] Q_64 = ITOP.iow0.arr[64]; +wire [63:0] Q_65 = ITOP.iow0.arr[65]; +wire [63:0] Q_66 = ITOP.iow0.arr[66]; +wire [63:0] Q_67 = ITOP.iow0.arr[67]; +wire [63:0] Q_68 = ITOP.iow0.arr[68]; +wire [63:0] Q_69 = ITOP.iow0.arr[69]; +wire [63:0] Q_70 = ITOP.iow0.arr[70]; +wire [63:0] Q_71 = ITOP.iow0.arr[71]; +wire [63:0] Q_72 = ITOP.iow0.arr[72]; +wire [63:0] Q_73 = ITOP.iow0.arr[73]; +wire [63:0] Q_74 = ITOP.iow0.arr[74]; +wire [63:0] Q_75 = ITOP.iow0.arr[75]; +wire [63:0] Q_76 = ITOP.iow0.arr[76]; +wire [63:0] Q_77 = ITOP.iow0.arr[77]; +wire [63:0] Q_78 = ITOP.iow0.arr[78]; +wire [63:0] Q_79 = ITOP.iow0.arr[79]; +wire [63:0] Q_80 = ITOP.iow0.arr[80]; +wire [63:0] Q_81 = ITOP.iow0.arr[81]; +wire [63:0] Q_82 = ITOP.iow0.arr[82]; +wire [63:0] Q_83 = ITOP.iow0.arr[83]; +wire [63:0] Q_84 = ITOP.iow0.arr[84]; +wire [63:0] Q_85 = ITOP.iow0.arr[85]; +wire [63:0] Q_86 = ITOP.iow0.arr[86]; +wire [63:0] Q_87 = ITOP.iow0.arr[87]; +wire [63:0] Q_88 = ITOP.iow0.arr[88]; +wire [63:0] Q_89 = ITOP.iow0.arr[89]; +wire [63:0] Q_90 = ITOP.iow0.arr[90]; +wire [63:0] Q_91 = ITOP.iow0.arr[91]; +wire [63:0] Q_92 = ITOP.iow0.arr[92]; +wire [63:0] Q_93 = ITOP.iow0.arr[93]; +wire [63:0] Q_94 = ITOP.iow0.arr[94]; +wire [63:0] Q_95 = ITOP.iow0.arr[95]; +wire [63:0] Q_96 = ITOP.iow0.arr[96]; +wire [63:0] Q_97 = ITOP.iow0.arr[97]; +wire [63:0] Q_98 = ITOP.iow0.arr[98]; +wire [63:0] Q_99 = ITOP.iow0.arr[99]; +wire [63:0] Q_100 = ITOP.iow0.arr[100]; +wire [63:0] Q_101 = ITOP.iow0.arr[101]; +wire [63:0] Q_102 = ITOP.iow0.arr[102]; +wire [63:0] Q_103 = ITOP.iow0.arr[103]; +wire [63:0] Q_104 = ITOP.iow0.arr[104]; +wire [63:0] Q_105 = ITOP.iow0.arr[105]; +wire [63:0] Q_106 = ITOP.iow0.arr[106]; +wire [63:0] Q_107 = ITOP.iow0.arr[107]; +wire [63:0] Q_108 = ITOP.iow0.arr[108]; +wire [63:0] Q_109 = ITOP.iow0.arr[109]; +wire [63:0] Q_110 = ITOP.iow0.arr[110]; +wire [63:0] Q_111 = ITOP.iow0.arr[111]; +wire [63:0] Q_112 = ITOP.iow0.arr[112]; +wire [63:0] Q_113 = ITOP.iow0.arr[113]; +wire [63:0] Q_114 = ITOP.iow0.arr[114]; +wire [63:0] Q_115 = ITOP.iow0.arr[115]; +wire [63:0] Q_116 = ITOP.iow0.arr[116]; +wire [63:0] Q_117 = ITOP.iow0.arr[117]; +wire [63:0] Q_118 = ITOP.iow0.arr[118]; +wire [63:0] Q_119 = ITOP.iow0.arr[119]; +wire [63:0] Q_120 = ITOP.iow0.arr[120]; +wire [63:0] Q_121 = ITOP.iow0.arr[121]; +wire [63:0] Q_122 = ITOP.iow0.arr[122]; +wire [63:0] Q_123 = ITOP.iow0.arr[123]; +wire [63:0] Q_124 = ITOP.iow0.arr[124]; +wire [63:0] Q_125 = ITOP.iow0.arr[125]; +wire [63:0] Q_126 = ITOP.iow0.arr[126]; +wire [63:0] Q_127 = ITOP.iow0.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[127:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_128X64_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [6:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 128 --> ['1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [63:0] rmuxd0; + wire [63:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_128X64_GL_M1_D2_ram # (128, 64, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [6:0] addr; +reg [63:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_128X64_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<128; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<128; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [63:0] mem_phys_read_padr; +input [6:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [63:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [63:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [63:0] data; + reg [63:0] wr[0:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [63:0] mon_bit_w; +input [6:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [63:0] mon_bit_r; +input [6:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [63:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow0.arr[1]; +wire [63:0] Q_2 = ITOP.iow0.arr[2]; +wire [63:0] Q_3 = ITOP.iow0.arr[3]; +wire [63:0] Q_4 = ITOP.iow0.arr[4]; +wire [63:0] Q_5 = ITOP.iow0.arr[5]; +wire [63:0] Q_6 = ITOP.iow0.arr[6]; +wire [63:0] Q_7 = ITOP.iow0.arr[7]; +wire [63:0] Q_8 = ITOP.iow0.arr[8]; +wire [63:0] Q_9 = ITOP.iow0.arr[9]; +wire [63:0] Q_10 = ITOP.iow0.arr[10]; +wire [63:0] Q_11 = ITOP.iow0.arr[11]; +wire [63:0] Q_12 = ITOP.iow0.arr[12]; +wire [63:0] Q_13 = ITOP.iow0.arr[13]; +wire [63:0] Q_14 = ITOP.iow0.arr[14]; +wire [63:0] Q_15 = ITOP.iow0.arr[15]; +wire [63:0] Q_16 = ITOP.iow0.arr[16]; +wire [63:0] Q_17 = ITOP.iow0.arr[17]; +wire [63:0] Q_18 = ITOP.iow0.arr[18]; +wire [63:0] Q_19 = ITOP.iow0.arr[19]; +wire [63:0] Q_20 = ITOP.iow0.arr[20]; +wire [63:0] Q_21 = ITOP.iow0.arr[21]; +wire [63:0] Q_22 = ITOP.iow0.arr[22]; +wire [63:0] Q_23 = ITOP.iow0.arr[23]; +wire [63:0] Q_24 = ITOP.iow0.arr[24]; +wire [63:0] Q_25 = ITOP.iow0.arr[25]; +wire [63:0] Q_26 = ITOP.iow0.arr[26]; +wire [63:0] Q_27 = ITOP.iow0.arr[27]; +wire [63:0] Q_28 = ITOP.iow0.arr[28]; +wire [63:0] Q_29 = ITOP.iow0.arr[29]; +wire [63:0] Q_30 = ITOP.iow0.arr[30]; +wire [63:0] Q_31 = ITOP.iow0.arr[31]; +wire [63:0] Q_32 = ITOP.iow0.arr[32]; +wire [63:0] Q_33 = ITOP.iow0.arr[33]; +wire [63:0] Q_34 = ITOP.iow0.arr[34]; +wire [63:0] Q_35 = ITOP.iow0.arr[35]; +wire [63:0] Q_36 = ITOP.iow0.arr[36]; +wire [63:0] Q_37 = ITOP.iow0.arr[37]; +wire [63:0] Q_38 = ITOP.iow0.arr[38]; +wire [63:0] Q_39 = ITOP.iow0.arr[39]; +wire [63:0] Q_40 = ITOP.iow0.arr[40]; +wire [63:0] Q_41 = ITOP.iow0.arr[41]; +wire [63:0] Q_42 = ITOP.iow0.arr[42]; +wire [63:0] Q_43 = ITOP.iow0.arr[43]; +wire [63:0] Q_44 = ITOP.iow0.arr[44]; +wire [63:0] Q_45 = ITOP.iow0.arr[45]; +wire [63:0] Q_46 = ITOP.iow0.arr[46]; +wire [63:0] Q_47 = ITOP.iow0.arr[47]; +wire [63:0] Q_48 = ITOP.iow0.arr[48]; +wire [63:0] Q_49 = ITOP.iow0.arr[49]; +wire [63:0] Q_50 = ITOP.iow0.arr[50]; +wire [63:0] Q_51 = ITOP.iow0.arr[51]; +wire [63:0] Q_52 = ITOP.iow0.arr[52]; +wire [63:0] Q_53 = ITOP.iow0.arr[53]; +wire [63:0] Q_54 = ITOP.iow0.arr[54]; +wire [63:0] Q_55 = ITOP.iow0.arr[55]; +wire [63:0] Q_56 = ITOP.iow0.arr[56]; +wire [63:0] Q_57 = ITOP.iow0.arr[57]; +wire [63:0] Q_58 = ITOP.iow0.arr[58]; +wire [63:0] Q_59 = ITOP.iow0.arr[59]; +wire [63:0] Q_60 = ITOP.iow0.arr[60]; +wire [63:0] Q_61 = ITOP.iow0.arr[61]; +wire [63:0] Q_62 = ITOP.iow0.arr[62]; +wire [63:0] Q_63 = ITOP.iow0.arr[63]; +wire [63:0] Q_64 = ITOP.iow0.arr[64]; +wire [63:0] Q_65 = ITOP.iow0.arr[65]; +wire [63:0] Q_66 = ITOP.iow0.arr[66]; +wire [63:0] Q_67 = ITOP.iow0.arr[67]; +wire [63:0] Q_68 = ITOP.iow0.arr[68]; +wire [63:0] Q_69 = ITOP.iow0.arr[69]; +wire [63:0] Q_70 = ITOP.iow0.arr[70]; +wire [63:0] Q_71 = ITOP.iow0.arr[71]; +wire [63:0] Q_72 = ITOP.iow0.arr[72]; +wire [63:0] Q_73 = ITOP.iow0.arr[73]; +wire [63:0] Q_74 = ITOP.iow0.arr[74]; +wire [63:0] Q_75 = ITOP.iow0.arr[75]; +wire [63:0] Q_76 = ITOP.iow0.arr[76]; +wire [63:0] Q_77 = ITOP.iow0.arr[77]; +wire [63:0] Q_78 = ITOP.iow0.arr[78]; +wire [63:0] Q_79 = ITOP.iow0.arr[79]; +wire [63:0] Q_80 = ITOP.iow0.arr[80]; +wire [63:0] Q_81 = ITOP.iow0.arr[81]; +wire [63:0] Q_82 = ITOP.iow0.arr[82]; +wire [63:0] Q_83 = ITOP.iow0.arr[83]; +wire [63:0] Q_84 = ITOP.iow0.arr[84]; +wire [63:0] Q_85 = ITOP.iow0.arr[85]; +wire [63:0] Q_86 = ITOP.iow0.arr[86]; +wire [63:0] Q_87 = ITOP.iow0.arr[87]; +wire [63:0] Q_88 = ITOP.iow0.arr[88]; +wire [63:0] Q_89 = ITOP.iow0.arr[89]; +wire [63:0] Q_90 = ITOP.iow0.arr[90]; +wire [63:0] Q_91 = ITOP.iow0.arr[91]; +wire [63:0] Q_92 = ITOP.iow0.arr[92]; +wire [63:0] Q_93 = ITOP.iow0.arr[93]; +wire [63:0] Q_94 = ITOP.iow0.arr[94]; +wire [63:0] Q_95 = ITOP.iow0.arr[95]; +wire [63:0] Q_96 = ITOP.iow0.arr[96]; +wire [63:0] Q_97 = ITOP.iow0.arr[97]; +wire [63:0] Q_98 = ITOP.iow0.arr[98]; +wire [63:0] Q_99 = ITOP.iow0.arr[99]; +wire [63:0] Q_100 = ITOP.iow0.arr[100]; +wire [63:0] Q_101 = ITOP.iow0.arr[101]; +wire [63:0] Q_102 = ITOP.iow0.arr[102]; +wire [63:0] Q_103 = ITOP.iow0.arr[103]; +wire [63:0] Q_104 = ITOP.iow0.arr[104]; +wire [63:0] Q_105 = ITOP.iow0.arr[105]; +wire [63:0] Q_106 = ITOP.iow0.arr[106]; +wire [63:0] Q_107 = ITOP.iow0.arr[107]; +wire [63:0] Q_108 = ITOP.iow0.arr[108]; +wire [63:0] Q_109 = ITOP.iow0.arr[109]; +wire [63:0] Q_110 = ITOP.iow0.arr[110]; +wire [63:0] Q_111 = ITOP.iow0.arr[111]; +wire [63:0] Q_112 = ITOP.iow0.arr[112]; +wire [63:0] Q_113 = ITOP.iow0.arr[113]; +wire [63:0] Q_114 = ITOP.iow0.arr[114]; +wire [63:0] Q_115 = ITOP.iow0.arr[115]; +wire [63:0] Q_116 = ITOP.iow0.arr[116]; +wire [63:0] Q_117 = ITOP.iow0.arr[117]; +wire [63:0] Q_118 = ITOP.iow0.arr[118]; +wire [63:0] Q_119 = ITOP.iow0.arr[119]; +wire [63:0] Q_120 = ITOP.iow0.arr[120]; +wire [63:0] Q_121 = ITOP.iow0.arr[121]; +wire [63:0] Q_122 = ITOP.iow0.arr[122]; +wire [63:0] Q_123 = ITOP.iow0.arr[123]; +wire [63:0] Q_124 = ITOP.iow0.arr[124]; +wire [63:0] Q_125 = ITOP.iow0.arr[125]; +wire [63:0] Q_126 = ITOP.iow0.arr[126]; +wire [63:0] Q_127 = ITOP.iow0.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[127:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_128X64_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [6:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 128 --> ['1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [63:0] rmuxd0; + wire [63:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_128X64_GL_M1_D2_ram # (128, 64, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [6:0] addr; +reg [63:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_128X64_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [143:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [143:0] val; + integer i; + begin + val = {144{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [143:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [144-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {144 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {144 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 144'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 144'bx; + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [143:0] wr[1:0]; + integer i; + begin + for (i=0; i<=143; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [143:0] Q_0 = ITOP.iow0.arr[0]; +wire [143:0] Q_1 = ITOP.iow1.arr[0]; +wire [143:0] Q_2 = ITOP.iow0.arr[1]; +wire [143:0] Q_3 = ITOP.iow1.arr[1]; +wire [143:0] Q_4 = ITOP.iow0.arr[2]; +wire [143:0] Q_5 = ITOP.iow1.arr[2]; +wire [143:0] Q_6 = ITOP.iow0.arr[3]; +wire [143:0] Q_7 = ITOP.iow1.arr[3]; +wire [143:0] Q_8 = ITOP.iow0.arr[4]; +wire [143:0] Q_9 = ITOP.iow1.arr[4]; +wire [143:0] Q_10 = ITOP.iow0.arr[5]; +wire [143:0] Q_11 = ITOP.iow1.arr[5]; +wire [143:0] Q_12 = ITOP.iow0.arr[6]; +wire [143:0] Q_13 = ITOP.iow1.arr[6]; +wire [143:0] Q_14 = ITOP.iow0.arr[7]; +wire [143:0] Q_15 = ITOP.iow1.arr[7]; +wire [143:0] Q_16 = ITOP.iow0.arr[8]; +wire [143:0] Q_17 = ITOP.iow1.arr[8]; +wire [143:0] Q_18 = ITOP.iow0.arr[9]; +wire [143:0] Q_19 = ITOP.iow1.arr[9]; +wire [143:0] Q_20 = ITOP.iow0.arr[10]; +wire [143:0] Q_21 = ITOP.iow1.arr[10]; +wire [143:0] Q_22 = ITOP.iow0.arr[11]; +wire [143:0] Q_23 = ITOP.iow1.arr[11]; +wire [143:0] Q_24 = ITOP.iow0.arr[12]; +wire [143:0] Q_25 = ITOP.iow1.arr[12]; +wire [143:0] Q_26 = ITOP.iow0.arr[13]; +wire [143:0] Q_27 = ITOP.iow1.arr[13]; +wire [143:0] Q_28 = ITOP.iow0.arr[14]; +wire [143:0] Q_29 = ITOP.iow1.arr[14]; +wire [143:0] Q_30 = ITOP.iow0.arr[15]; +wire [143:0] Q_31 = ITOP.iow1.arr[15]; +wire [143:0] Q_32 = ITOP.iow0.arr[16]; +wire [143:0] Q_33 = ITOP.iow1.arr[16]; +wire [143:0] Q_34 = ITOP.iow0.arr[17]; +wire [143:0] Q_35 = ITOP.iow1.arr[17]; +wire [143:0] Q_36 = ITOP.iow0.arr[18]; +wire [143:0] Q_37 = ITOP.iow1.arr[18]; +wire [143:0] Q_38 = ITOP.iow0.arr[19]; +wire [143:0] Q_39 = ITOP.iow1.arr[19]; +wire [143:0] Q_40 = ITOP.iow0.arr[20]; +wire [143:0] Q_41 = ITOP.iow1.arr[20]; +wire [143:0] Q_42 = ITOP.iow0.arr[21]; +wire [143:0] Q_43 = ITOP.iow1.arr[21]; +wire [143:0] Q_44 = ITOP.iow0.arr[22]; +wire [143:0] Q_45 = ITOP.iow1.arr[22]; +wire [143:0] Q_46 = ITOP.iow0.arr[23]; +wire [143:0] Q_47 = ITOP.iow1.arr[23]; +wire [143:0] Q_48 = ITOP.iow0.arr[24]; +wire [143:0] Q_49 = ITOP.iow1.arr[24]; +wire [143:0] Q_50 = ITOP.iow0.arr[25]; +wire [143:0] Q_51 = ITOP.iow1.arr[25]; +wire [143:0] Q_52 = ITOP.iow0.arr[26]; +wire [143:0] Q_53 = ITOP.iow1.arr[26]; +wire [143:0] Q_54 = ITOP.iow0.arr[27]; +wire [143:0] Q_55 = ITOP.iow1.arr[27]; +wire [143:0] Q_56 = ITOP.iow0.arr[28]; +wire [143:0] Q_57 = ITOP.iow1.arr[28]; +wire [143:0] Q_58 = ITOP.iow0.arr[29]; +wire [143:0] Q_59 = ITOP.iow1.arr[29]; +wire [143:0] Q_60 = ITOP.iow0.arr[30]; +wire [143:0] Q_61 = ITOP.iow1.arr[30]; +wire [143:0] Q_62 = ITOP.iow0.arr[31]; +wire [143:0] Q_63 = ITOP.iow1.arr[31]; +wire [143:0] Q_64 = ITOP.iow0.arr[32]; +wire [143:0] Q_65 = ITOP.iow1.arr[32]; +wire [143:0] Q_66 = ITOP.iow0.arr[33]; +wire [143:0] Q_67 = ITOP.iow1.arr[33]; +wire [143:0] Q_68 = ITOP.iow0.arr[34]; +wire [143:0] Q_69 = ITOP.iow1.arr[34]; +wire [143:0] Q_70 = ITOP.iow0.arr[35]; +wire [143:0] Q_71 = ITOP.iow1.arr[35]; +wire [143:0] Q_72 = ITOP.iow0.arr[36]; +wire [143:0] Q_73 = ITOP.iow1.arr[36]; +wire [143:0] Q_74 = ITOP.iow0.arr[37]; +wire [143:0] Q_75 = ITOP.iow1.arr[37]; +wire [143:0] Q_76 = ITOP.iow0.arr[38]; +wire [143:0] Q_77 = ITOP.iow1.arr[38]; +wire [143:0] Q_78 = ITOP.iow0.arr[39]; +wire [143:0] Q_79 = ITOP.iow1.arr[39]; +wire [143:0] Q_80 = ITOP.iow0.arr[40]; +wire [143:0] Q_81 = ITOP.iow1.arr[40]; +wire [143:0] Q_82 = ITOP.iow0.arr[41]; +wire [143:0] Q_83 = ITOP.iow1.arr[41]; +wire [143:0] Q_84 = ITOP.iow0.arr[42]; +wire [143:0] Q_85 = ITOP.iow1.arr[42]; +wire [143:0] Q_86 = ITOP.iow0.arr[43]; +wire [143:0] Q_87 = ITOP.iow1.arr[43]; +wire [143:0] Q_88 = ITOP.iow0.arr[44]; +wire [143:0] Q_89 = ITOP.iow1.arr[44]; +wire [143:0] Q_90 = ITOP.iow0.arr[45]; +wire [143:0] Q_91 = ITOP.iow1.arr[45]; +wire [143:0] Q_92 = ITOP.iow0.arr[46]; +wire [143:0] Q_93 = ITOP.iow1.arr[46]; +wire [143:0] Q_94 = ITOP.iow0.arr[47]; +wire [143:0] Q_95 = ITOP.iow1.arr[47]; +wire [143:0] Q_96 = ITOP.iow0.arr[48]; +wire [143:0] Q_97 = ITOP.iow1.arr[48]; +wire [143:0] Q_98 = ITOP.iow0.arr[49]; +wire [143:0] Q_99 = ITOP.iow1.arr[49]; +wire [143:0] Q_100 = ITOP.iow0.arr[50]; +wire [143:0] Q_101 = ITOP.iow1.arr[50]; +wire [143:0] Q_102 = ITOP.iow0.arr[51]; +wire [143:0] Q_103 = ITOP.iow1.arr[51]; +wire [143:0] Q_104 = ITOP.iow0.arr[52]; +wire [143:0] Q_105 = ITOP.iow1.arr[52]; +wire [143:0] Q_106 = ITOP.iow0.arr[53]; +wire [143:0] Q_107 = ITOP.iow1.arr[53]; +wire [143:0] Q_108 = ITOP.iow0.arr[54]; +wire [143:0] Q_109 = ITOP.iow1.arr[54]; +wire [143:0] Q_110 = ITOP.iow0.arr[55]; +wire [143:0] Q_111 = ITOP.iow1.arr[55]; +wire [143:0] Q_112 = ITOP.iow0.arr[56]; +wire [143:0] Q_113 = ITOP.iow1.arr[56]; +wire [143:0] Q_114 = ITOP.iow0.arr[57]; +wire [143:0] Q_115 = ITOP.iow1.arr[57]; +wire [143:0] Q_116 = ITOP.iow0.arr[58]; +wire [143:0] Q_117 = ITOP.iow1.arr[58]; +wire [143:0] Q_118 = ITOP.iow0.arr[59]; +wire [143:0] Q_119 = ITOP.iow1.arr[59]; +wire [143:0] Q_120 = ITOP.iow0.arr[60]; +wire [143:0] Q_121 = ITOP.iow1.arr[60]; +wire [143:0] Q_122 = ITOP.iow0.arr[61]; +wire [143:0] Q_123 = ITOP.iow1.arr[61]; +wire [143:0] Q_124 = ITOP.iow0.arr[62]; +wire [143:0] Q_125 = ITOP.iow1.arr[62]; +wire [143:0] Q_126 = ITOP.iow0.arr[63]; +wire [143:0] Q_127 = ITOP.iow1.arr[63]; +wire [143:0] Q_128 = ITOP.iow0.arr[64]; +wire [143:0] Q_129 = ITOP.iow1.arr[64]; +wire [143:0] Q_130 = ITOP.iow0.arr[65]; +wire [143:0] Q_131 = ITOP.iow1.arr[65]; +wire [143:0] Q_132 = ITOP.iow0.arr[66]; +wire [143:0] Q_133 = ITOP.iow1.arr[66]; +wire [143:0] Q_134 = ITOP.iow0.arr[67]; +wire [143:0] Q_135 = ITOP.iow1.arr[67]; +wire [143:0] Q_136 = ITOP.iow0.arr[68]; +wire [143:0] Q_137 = ITOP.iow1.arr[68]; +wire [143:0] Q_138 = ITOP.iow0.arr[69]; +wire [143:0] Q_139 = ITOP.iow1.arr[69]; +wire [143:0] Q_140 = ITOP.iow0.arr[70]; +wire [143:0] Q_141 = ITOP.iow1.arr[70]; +wire [143:0] Q_142 = ITOP.iow0.arr[71]; +wire [143:0] Q_143 = ITOP.iow1.arr[71]; +wire [143:0] Q_144 = ITOP.iow0.arr[72]; +wire [143:0] Q_145 = ITOP.iow1.arr[72]; +wire [143:0] Q_146 = ITOP.iow0.arr[73]; +wire [143:0] Q_147 = ITOP.iow1.arr[73]; +wire [143:0] Q_148 = ITOP.iow0.arr[74]; +wire [143:0] Q_149 = ITOP.iow1.arr[74]; +wire [143:0] Q_150 = ITOP.iow0.arr[75]; +wire [143:0] Q_151 = ITOP.iow1.arr[75]; +wire [143:0] Q_152 = ITOP.iow0.arr[76]; +wire [143:0] Q_153 = ITOP.iow1.arr[76]; +wire [143:0] Q_154 = ITOP.iow0.arr[77]; +wire [143:0] Q_155 = ITOP.iow1.arr[77]; +wire [143:0] Q_156 = ITOP.iow0.arr[78]; +wire [143:0] Q_157 = ITOP.iow1.arr[78]; +wire [143:0] Q_158 = ITOP.iow0.arr[79]; +wire [143:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [143:0] WD_FF; + reg [143:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [143:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [143:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [143:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X144_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [143:0] WD; +input [7:0] RA, WA; +output [143:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [143:0] WDQ; + wire [143:0] WDBQ; + wire [143:0] WMNexp; + wire [143:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [143:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {144{1'b0}}; + assign SHFT = {144{1'b1}}; + reg [143:0] WDQ_pr; + wire [143:0] WDBQ_pr; + assign WMNexp = {144{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[143:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [143:0] dout; + wire [143:0] RD; + wire RD_rdnt; + wire [143:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [143:0] RDBYPASS = {144{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [143:0] force_x; +`ifndef SYNTHESIS + assign force_x = {144{1'bx}}; +`else + assign force_x = {144{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [143:0] rmuxd0, rmuxd1; + wire [143:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {144{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {144{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {144{RdClk0}} & ~dout0 ; + assign rmuxd1 = {144{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[143:0] <= (rmuxd0[143:0] | rmuxd1[143:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X144_GL_M2_D2_ram # (80, 144, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X144_GL_M2_D2_ram # (80, 144, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [143:0] data; + reg [143:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [143:0] mem_read_bank; +input [7:0] addr; +reg [143:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X144_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 144; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [143:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [143:0] val; + integer i; + begin + val = {144{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [143:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [144-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {144 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {144 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 144'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 144'bx; + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [143:0] wr[1:0]; + integer i; + begin + for (i=0; i<=143; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [143:0] Q_0 = ITOP.iow0.arr[0]; +wire [143:0] Q_1 = ITOP.iow1.arr[0]; +wire [143:0] Q_2 = ITOP.iow0.arr[1]; +wire [143:0] Q_3 = ITOP.iow1.arr[1]; +wire [143:0] Q_4 = ITOP.iow0.arr[2]; +wire [143:0] Q_5 = ITOP.iow1.arr[2]; +wire [143:0] Q_6 = ITOP.iow0.arr[3]; +wire [143:0] Q_7 = ITOP.iow1.arr[3]; +wire [143:0] Q_8 = ITOP.iow0.arr[4]; +wire [143:0] Q_9 = ITOP.iow1.arr[4]; +wire [143:0] Q_10 = ITOP.iow0.arr[5]; +wire [143:0] Q_11 = ITOP.iow1.arr[5]; +wire [143:0] Q_12 = ITOP.iow0.arr[6]; +wire [143:0] Q_13 = ITOP.iow1.arr[6]; +wire [143:0] Q_14 = ITOP.iow0.arr[7]; +wire [143:0] Q_15 = ITOP.iow1.arr[7]; +wire [143:0] Q_16 = ITOP.iow0.arr[8]; +wire [143:0] Q_17 = ITOP.iow1.arr[8]; +wire [143:0] Q_18 = ITOP.iow0.arr[9]; +wire [143:0] Q_19 = ITOP.iow1.arr[9]; +wire [143:0] Q_20 = ITOP.iow0.arr[10]; +wire [143:0] Q_21 = ITOP.iow1.arr[10]; +wire [143:0] Q_22 = ITOP.iow0.arr[11]; +wire [143:0] Q_23 = ITOP.iow1.arr[11]; +wire [143:0] Q_24 = ITOP.iow0.arr[12]; +wire [143:0] Q_25 = ITOP.iow1.arr[12]; +wire [143:0] Q_26 = ITOP.iow0.arr[13]; +wire [143:0] Q_27 = ITOP.iow1.arr[13]; +wire [143:0] Q_28 = ITOP.iow0.arr[14]; +wire [143:0] Q_29 = ITOP.iow1.arr[14]; +wire [143:0] Q_30 = ITOP.iow0.arr[15]; +wire [143:0] Q_31 = ITOP.iow1.arr[15]; +wire [143:0] Q_32 = ITOP.iow0.arr[16]; +wire [143:0] Q_33 = ITOP.iow1.arr[16]; +wire [143:0] Q_34 = ITOP.iow0.arr[17]; +wire [143:0] Q_35 = ITOP.iow1.arr[17]; +wire [143:0] Q_36 = ITOP.iow0.arr[18]; +wire [143:0] Q_37 = ITOP.iow1.arr[18]; +wire [143:0] Q_38 = ITOP.iow0.arr[19]; +wire [143:0] Q_39 = ITOP.iow1.arr[19]; +wire [143:0] Q_40 = ITOP.iow0.arr[20]; +wire [143:0] Q_41 = ITOP.iow1.arr[20]; +wire [143:0] Q_42 = ITOP.iow0.arr[21]; +wire [143:0] Q_43 = ITOP.iow1.arr[21]; +wire [143:0] Q_44 = ITOP.iow0.arr[22]; +wire [143:0] Q_45 = ITOP.iow1.arr[22]; +wire [143:0] Q_46 = ITOP.iow0.arr[23]; +wire [143:0] Q_47 = ITOP.iow1.arr[23]; +wire [143:0] Q_48 = ITOP.iow0.arr[24]; +wire [143:0] Q_49 = ITOP.iow1.arr[24]; +wire [143:0] Q_50 = ITOP.iow0.arr[25]; +wire [143:0] Q_51 = ITOP.iow1.arr[25]; +wire [143:0] Q_52 = ITOP.iow0.arr[26]; +wire [143:0] Q_53 = ITOP.iow1.arr[26]; +wire [143:0] Q_54 = ITOP.iow0.arr[27]; +wire [143:0] Q_55 = ITOP.iow1.arr[27]; +wire [143:0] Q_56 = ITOP.iow0.arr[28]; +wire [143:0] Q_57 = ITOP.iow1.arr[28]; +wire [143:0] Q_58 = ITOP.iow0.arr[29]; +wire [143:0] Q_59 = ITOP.iow1.arr[29]; +wire [143:0] Q_60 = ITOP.iow0.arr[30]; +wire [143:0] Q_61 = ITOP.iow1.arr[30]; +wire [143:0] Q_62 = ITOP.iow0.arr[31]; +wire [143:0] Q_63 = ITOP.iow1.arr[31]; +wire [143:0] Q_64 = ITOP.iow0.arr[32]; +wire [143:0] Q_65 = ITOP.iow1.arr[32]; +wire [143:0] Q_66 = ITOP.iow0.arr[33]; +wire [143:0] Q_67 = ITOP.iow1.arr[33]; +wire [143:0] Q_68 = ITOP.iow0.arr[34]; +wire [143:0] Q_69 = ITOP.iow1.arr[34]; +wire [143:0] Q_70 = ITOP.iow0.arr[35]; +wire [143:0] Q_71 = ITOP.iow1.arr[35]; +wire [143:0] Q_72 = ITOP.iow0.arr[36]; +wire [143:0] Q_73 = ITOP.iow1.arr[36]; +wire [143:0] Q_74 = ITOP.iow0.arr[37]; +wire [143:0] Q_75 = ITOP.iow1.arr[37]; +wire [143:0] Q_76 = ITOP.iow0.arr[38]; +wire [143:0] Q_77 = ITOP.iow1.arr[38]; +wire [143:0] Q_78 = ITOP.iow0.arr[39]; +wire [143:0] Q_79 = ITOP.iow1.arr[39]; +wire [143:0] Q_80 = ITOP.iow0.arr[40]; +wire [143:0] Q_81 = ITOP.iow1.arr[40]; +wire [143:0] Q_82 = ITOP.iow0.arr[41]; +wire [143:0] Q_83 = ITOP.iow1.arr[41]; +wire [143:0] Q_84 = ITOP.iow0.arr[42]; +wire [143:0] Q_85 = ITOP.iow1.arr[42]; +wire [143:0] Q_86 = ITOP.iow0.arr[43]; +wire [143:0] Q_87 = ITOP.iow1.arr[43]; +wire [143:0] Q_88 = ITOP.iow0.arr[44]; +wire [143:0] Q_89 = ITOP.iow1.arr[44]; +wire [143:0] Q_90 = ITOP.iow0.arr[45]; +wire [143:0] Q_91 = ITOP.iow1.arr[45]; +wire [143:0] Q_92 = ITOP.iow0.arr[46]; +wire [143:0] Q_93 = ITOP.iow1.arr[46]; +wire [143:0] Q_94 = ITOP.iow0.arr[47]; +wire [143:0] Q_95 = ITOP.iow1.arr[47]; +wire [143:0] Q_96 = ITOP.iow0.arr[48]; +wire [143:0] Q_97 = ITOP.iow1.arr[48]; +wire [143:0] Q_98 = ITOP.iow0.arr[49]; +wire [143:0] Q_99 = ITOP.iow1.arr[49]; +wire [143:0] Q_100 = ITOP.iow0.arr[50]; +wire [143:0] Q_101 = ITOP.iow1.arr[50]; +wire [143:0] Q_102 = ITOP.iow0.arr[51]; +wire [143:0] Q_103 = ITOP.iow1.arr[51]; +wire [143:0] Q_104 = ITOP.iow0.arr[52]; +wire [143:0] Q_105 = ITOP.iow1.arr[52]; +wire [143:0] Q_106 = ITOP.iow0.arr[53]; +wire [143:0] Q_107 = ITOP.iow1.arr[53]; +wire [143:0] Q_108 = ITOP.iow0.arr[54]; +wire [143:0] Q_109 = ITOP.iow1.arr[54]; +wire [143:0] Q_110 = ITOP.iow0.arr[55]; +wire [143:0] Q_111 = ITOP.iow1.arr[55]; +wire [143:0] Q_112 = ITOP.iow0.arr[56]; +wire [143:0] Q_113 = ITOP.iow1.arr[56]; +wire [143:0] Q_114 = ITOP.iow0.arr[57]; +wire [143:0] Q_115 = ITOP.iow1.arr[57]; +wire [143:0] Q_116 = ITOP.iow0.arr[58]; +wire [143:0] Q_117 = ITOP.iow1.arr[58]; +wire [143:0] Q_118 = ITOP.iow0.arr[59]; +wire [143:0] Q_119 = ITOP.iow1.arr[59]; +wire [143:0] Q_120 = ITOP.iow0.arr[60]; +wire [143:0] Q_121 = ITOP.iow1.arr[60]; +wire [143:0] Q_122 = ITOP.iow0.arr[61]; +wire [143:0] Q_123 = ITOP.iow1.arr[61]; +wire [143:0] Q_124 = ITOP.iow0.arr[62]; +wire [143:0] Q_125 = ITOP.iow1.arr[62]; +wire [143:0] Q_126 = ITOP.iow0.arr[63]; +wire [143:0] Q_127 = ITOP.iow1.arr[63]; +wire [143:0] Q_128 = ITOP.iow0.arr[64]; +wire [143:0] Q_129 = ITOP.iow1.arr[64]; +wire [143:0] Q_130 = ITOP.iow0.arr[65]; +wire [143:0] Q_131 = ITOP.iow1.arr[65]; +wire [143:0] Q_132 = ITOP.iow0.arr[66]; +wire [143:0] Q_133 = ITOP.iow1.arr[66]; +wire [143:0] Q_134 = ITOP.iow0.arr[67]; +wire [143:0] Q_135 = ITOP.iow1.arr[67]; +wire [143:0] Q_136 = ITOP.iow0.arr[68]; +wire [143:0] Q_137 = ITOP.iow1.arr[68]; +wire [143:0] Q_138 = ITOP.iow0.arr[69]; +wire [143:0] Q_139 = ITOP.iow1.arr[69]; +wire [143:0] Q_140 = ITOP.iow0.arr[70]; +wire [143:0] Q_141 = ITOP.iow1.arr[70]; +wire [143:0] Q_142 = ITOP.iow0.arr[71]; +wire [143:0] Q_143 = ITOP.iow1.arr[71]; +wire [143:0] Q_144 = ITOP.iow0.arr[72]; +wire [143:0] Q_145 = ITOP.iow1.arr[72]; +wire [143:0] Q_146 = ITOP.iow0.arr[73]; +wire [143:0] Q_147 = ITOP.iow1.arr[73]; +wire [143:0] Q_148 = ITOP.iow0.arr[74]; +wire [143:0] Q_149 = ITOP.iow1.arr[74]; +wire [143:0] Q_150 = ITOP.iow0.arr[75]; +wire [143:0] Q_151 = ITOP.iow1.arr[75]; +wire [143:0] Q_152 = ITOP.iow0.arr[76]; +wire [143:0] Q_153 = ITOP.iow1.arr[76]; +wire [143:0] Q_154 = ITOP.iow0.arr[77]; +wire [143:0] Q_155 = ITOP.iow1.arr[77]; +wire [143:0] Q_156 = ITOP.iow0.arr[78]; +wire [143:0] Q_157 = ITOP.iow1.arr[78]; +wire [143:0] Q_158 = ITOP.iow0.arr[79]; +wire [143:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [143:0] WD_FF; + reg [143:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [143:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [143:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [143:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X144_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [143:0] WD; +input [7:0] RA, WA; +output [143:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [143:0] WDQ; + wire [143:0] WDBQ; + wire [143:0] WMNexp; + wire [143:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [143:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {144{1'b0}}; + assign SHFT = {144{1'b1}}; + reg [143:0] WDQ_pr; + wire [143:0] WDBQ_pr; + assign WMNexp = {144{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[143:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [143:0] dout; + wire [143:0] RD; + wire RD_rdnt; + wire [143:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [143:0] RDBYPASS = {144{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [143:0] force_x; +`ifndef SYNTHESIS + assign force_x = {144{1'bx}}; +`else + assign force_x = {144{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [143:0] rmuxd0, rmuxd1; + wire [143:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {144{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {144{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {144{RdClk0}} & ~dout0 ; + assign rmuxd1 = {144{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[143:0] <= (rmuxd0[143:0] | rmuxd1[143:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X144_GL_M2_D2_ram # (80, 144, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X144_GL_M2_D2_ram # (80, 144, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [143:0] data; + reg [143:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [143:0] mem_read_bank; +input [7:0] addr; +reg [143:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X144_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 144; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [15:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [15:0] val; + integer i; + begin + val = {16{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [15:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [16-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {16 {1'b1}} `else { $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {16 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [31:0] mem_phys_read_padr; +input [6:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [31:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [31:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 16'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 16'bx; + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [31:0] data; + reg [15:0] wr[1:0]; + integer i; + begin + for (i=0; i<=15; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [31:0] mon_bit_w; +input [6:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [31:0] mon_bit_r; +input [6:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [31:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [15:0] Q_0 = ITOP.iow0.arr[0]; +wire [15:0] Q_1 = ITOP.iow1.arr[0]; +wire [15:0] Q_2 = ITOP.iow0.arr[1]; +wire [15:0] Q_3 = ITOP.iow1.arr[1]; +wire [15:0] Q_4 = ITOP.iow0.arr[2]; +wire [15:0] Q_5 = ITOP.iow1.arr[2]; +wire [15:0] Q_6 = ITOP.iow0.arr[3]; +wire [15:0] Q_7 = ITOP.iow1.arr[3]; +wire [15:0] Q_8 = ITOP.iow0.arr[4]; +wire [15:0] Q_9 = ITOP.iow1.arr[4]; +wire [15:0] Q_10 = ITOP.iow0.arr[5]; +wire [15:0] Q_11 = ITOP.iow1.arr[5]; +wire [15:0] Q_12 = ITOP.iow0.arr[6]; +wire [15:0] Q_13 = ITOP.iow1.arr[6]; +wire [15:0] Q_14 = ITOP.iow0.arr[7]; +wire [15:0] Q_15 = ITOP.iow1.arr[7]; +wire [15:0] Q_16 = ITOP.iow0.arr[8]; +wire [15:0] Q_17 = ITOP.iow1.arr[8]; +wire [15:0] Q_18 = ITOP.iow0.arr[9]; +wire [15:0] Q_19 = ITOP.iow1.arr[9]; +wire [15:0] Q_20 = ITOP.iow0.arr[10]; +wire [15:0] Q_21 = ITOP.iow1.arr[10]; +wire [15:0] Q_22 = ITOP.iow0.arr[11]; +wire [15:0] Q_23 = ITOP.iow1.arr[11]; +wire [15:0] Q_24 = ITOP.iow0.arr[12]; +wire [15:0] Q_25 = ITOP.iow1.arr[12]; +wire [15:0] Q_26 = ITOP.iow0.arr[13]; +wire [15:0] Q_27 = ITOP.iow1.arr[13]; +wire [15:0] Q_28 = ITOP.iow0.arr[14]; +wire [15:0] Q_29 = ITOP.iow1.arr[14]; +wire [15:0] Q_30 = ITOP.iow0.arr[15]; +wire [15:0] Q_31 = ITOP.iow1.arr[15]; +wire [15:0] Q_32 = ITOP.iow0.arr[16]; +wire [15:0] Q_33 = ITOP.iow1.arr[16]; +wire [15:0] Q_34 = ITOP.iow0.arr[17]; +wire [15:0] Q_35 = ITOP.iow1.arr[17]; +wire [15:0] Q_36 = ITOP.iow0.arr[18]; +wire [15:0] Q_37 = ITOP.iow1.arr[18]; +wire [15:0] Q_38 = ITOP.iow0.arr[19]; +wire [15:0] Q_39 = ITOP.iow1.arr[19]; +wire [15:0] Q_40 = ITOP.iow0.arr[20]; +wire [15:0] Q_41 = ITOP.iow1.arr[20]; +wire [15:0] Q_42 = ITOP.iow0.arr[21]; +wire [15:0] Q_43 = ITOP.iow1.arr[21]; +wire [15:0] Q_44 = ITOP.iow0.arr[22]; +wire [15:0] Q_45 = ITOP.iow1.arr[22]; +wire [15:0] Q_46 = ITOP.iow0.arr[23]; +wire [15:0] Q_47 = ITOP.iow1.arr[23]; +wire [15:0] Q_48 = ITOP.iow0.arr[24]; +wire [15:0] Q_49 = ITOP.iow1.arr[24]; +wire [15:0] Q_50 = ITOP.iow0.arr[25]; +wire [15:0] Q_51 = ITOP.iow1.arr[25]; +wire [15:0] Q_52 = ITOP.iow0.arr[26]; +wire [15:0] Q_53 = ITOP.iow1.arr[26]; +wire [15:0] Q_54 = ITOP.iow0.arr[27]; +wire [15:0] Q_55 = ITOP.iow1.arr[27]; +wire [15:0] Q_56 = ITOP.iow0.arr[28]; +wire [15:0] Q_57 = ITOP.iow1.arr[28]; +wire [15:0] Q_58 = ITOP.iow0.arr[29]; +wire [15:0] Q_59 = ITOP.iow1.arr[29]; +wire [15:0] Q_60 = ITOP.iow0.arr[30]; +wire [15:0] Q_61 = ITOP.iow1.arr[30]; +wire [15:0] Q_62 = ITOP.iow0.arr[31]; +wire [15:0] Q_63 = ITOP.iow1.arr[31]; +wire [15:0] Q_64 = ITOP.iow0.arr[32]; +wire [15:0] Q_65 = ITOP.iow1.arr[32]; +wire [15:0] Q_66 = ITOP.iow0.arr[33]; +wire [15:0] Q_67 = ITOP.iow1.arr[33]; +wire [15:0] Q_68 = ITOP.iow0.arr[34]; +wire [15:0] Q_69 = ITOP.iow1.arr[34]; +wire [15:0] Q_70 = ITOP.iow0.arr[35]; +wire [15:0] Q_71 = ITOP.iow1.arr[35]; +wire [15:0] Q_72 = ITOP.iow0.arr[36]; +wire [15:0] Q_73 = ITOP.iow1.arr[36]; +wire [15:0] Q_74 = ITOP.iow0.arr[37]; +wire [15:0] Q_75 = ITOP.iow1.arr[37]; +wire [15:0] Q_76 = ITOP.iow0.arr[38]; +wire [15:0] Q_77 = ITOP.iow1.arr[38]; +wire [15:0] Q_78 = ITOP.iow0.arr[39]; +wire [15:0] Q_79 = ITOP.iow1.arr[39]; +wire [15:0] Q_80 = ITOP.iow0.arr[40]; +wire [15:0] Q_81 = ITOP.iow1.arr[40]; +wire [15:0] Q_82 = ITOP.iow0.arr[41]; +wire [15:0] Q_83 = ITOP.iow1.arr[41]; +wire [15:0] Q_84 = ITOP.iow0.arr[42]; +wire [15:0] Q_85 = ITOP.iow1.arr[42]; +wire [15:0] Q_86 = ITOP.iow0.arr[43]; +wire [15:0] Q_87 = ITOP.iow1.arr[43]; +wire [15:0] Q_88 = ITOP.iow0.arr[44]; +wire [15:0] Q_89 = ITOP.iow1.arr[44]; +wire [15:0] Q_90 = ITOP.iow0.arr[45]; +wire [15:0] Q_91 = ITOP.iow1.arr[45]; +wire [15:0] Q_92 = ITOP.iow0.arr[46]; +wire [15:0] Q_93 = ITOP.iow1.arr[46]; +wire [15:0] Q_94 = ITOP.iow0.arr[47]; +wire [15:0] Q_95 = ITOP.iow1.arr[47]; +wire [15:0] Q_96 = ITOP.iow0.arr[48]; +wire [15:0] Q_97 = ITOP.iow1.arr[48]; +wire [15:0] Q_98 = ITOP.iow0.arr[49]; +wire [15:0] Q_99 = ITOP.iow1.arr[49]; +wire [15:0] Q_100 = ITOP.iow0.arr[50]; +wire [15:0] Q_101 = ITOP.iow1.arr[50]; +wire [15:0] Q_102 = ITOP.iow0.arr[51]; +wire [15:0] Q_103 = ITOP.iow1.arr[51]; +wire [15:0] Q_104 = ITOP.iow0.arr[52]; +wire [15:0] Q_105 = ITOP.iow1.arr[52]; +wire [15:0] Q_106 = ITOP.iow0.arr[53]; +wire [15:0] Q_107 = ITOP.iow1.arr[53]; +wire [15:0] Q_108 = ITOP.iow0.arr[54]; +wire [15:0] Q_109 = ITOP.iow1.arr[54]; +wire [15:0] Q_110 = ITOP.iow0.arr[55]; +wire [15:0] Q_111 = ITOP.iow1.arr[55]; +wire [15:0] Q_112 = ITOP.iow0.arr[56]; +wire [15:0] Q_113 = ITOP.iow1.arr[56]; +wire [15:0] Q_114 = ITOP.iow0.arr[57]; +wire [15:0] Q_115 = ITOP.iow1.arr[57]; +wire [15:0] Q_116 = ITOP.iow0.arr[58]; +wire [15:0] Q_117 = ITOP.iow1.arr[58]; +wire [15:0] Q_118 = ITOP.iow0.arr[59]; +wire [15:0] Q_119 = ITOP.iow1.arr[59]; +wire [15:0] Q_120 = ITOP.iow0.arr[60]; +wire [15:0] Q_121 = ITOP.iow1.arr[60]; +wire [15:0] Q_122 = ITOP.iow0.arr[61]; +wire [15:0] Q_123 = ITOP.iow1.arr[61]; +wire [15:0] Q_124 = ITOP.iow0.arr[62]; +wire [15:0] Q_125 = ITOP.iow1.arr[62]; +wire [15:0] Q_126 = ITOP.iow0.arr[63]; +wire [15:0] Q_127 = ITOP.iow1.arr[63]; +wire [15:0] Q_128 = ITOP.iow0.arr[64]; +wire [15:0] Q_129 = ITOP.iow1.arr[64]; +wire [15:0] Q_130 = ITOP.iow0.arr[65]; +wire [15:0] Q_131 = ITOP.iow1.arr[65]; +wire [15:0] Q_132 = ITOP.iow0.arr[66]; +wire [15:0] Q_133 = ITOP.iow1.arr[66]; +wire [15:0] Q_134 = ITOP.iow0.arr[67]; +wire [15:0] Q_135 = ITOP.iow1.arr[67]; +wire [15:0] Q_136 = ITOP.iow0.arr[68]; +wire [15:0] Q_137 = ITOP.iow1.arr[68]; +wire [15:0] Q_138 = ITOP.iow0.arr[69]; +wire [15:0] Q_139 = ITOP.iow1.arr[69]; +wire [15:0] Q_140 = ITOP.iow0.arr[70]; +wire [15:0] Q_141 = ITOP.iow1.arr[70]; +wire [15:0] Q_142 = ITOP.iow0.arr[71]; +wire [15:0] Q_143 = ITOP.iow1.arr[71]; +wire [15:0] Q_144 = ITOP.iow0.arr[72]; +wire [15:0] Q_145 = ITOP.iow1.arr[72]; +wire [15:0] Q_146 = ITOP.iow0.arr[73]; +wire [15:0] Q_147 = ITOP.iow1.arr[73]; +wire [15:0] Q_148 = ITOP.iow0.arr[74]; +wire [15:0] Q_149 = ITOP.iow1.arr[74]; +wire [15:0] Q_150 = ITOP.iow0.arr[75]; +wire [15:0] Q_151 = ITOP.iow1.arr[75]; +wire [15:0] Q_152 = ITOP.iow0.arr[76]; +wire [15:0] Q_153 = ITOP.iow1.arr[76]; +wire [15:0] Q_154 = ITOP.iow0.arr[77]; +wire [15:0] Q_155 = ITOP.iow1.arr[77]; +wire [15:0] Q_156 = ITOP.iow0.arr[78]; +wire [15:0] Q_157 = ITOP.iow1.arr[78]; +wire [15:0] Q_158 = ITOP.iow0.arr[79]; +wire [15:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [15:0] WD_FF; + reg [15:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [15:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [15:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [15:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X16_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [15:0] WD; +input [7:0] RA, WA; +output [15:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [15:0] WDQ; + wire [15:0] WDBQ; + wire [15:0] WMNexp; + wire [15:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [15:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {16{1'b0}}; + assign SHFT = {16{1'b1}}; + reg [15:0] WDQ_pr; + wire [15:0] WDBQ_pr; + assign WMNexp = {16{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[15:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [15:0] dout; + wire [15:0] RD; + wire RD_rdnt; + wire [15:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [15:0] RDBYPASS = {16{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [15:0] force_x; +`ifndef SYNTHESIS + assign force_x = {16{1'bx}}; +`else + assign force_x = {16{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [15:0] rmuxd0, rmuxd1; + wire [15:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {16{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {16{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {16{RdClk0}} & ~dout0 ; + assign rmuxd1 = {16{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[15:0] <= (rmuxd0[15:0] | rmuxd1[15:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X16_GL_M2_D2_ram # (80, 16, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X16_GL_M2_D2_ram # (80, 16, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [15:0] data; + reg [15:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [15:0] mem_read_bank; +input [7:0] addr; +reg [15:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X16_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 16; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [15:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [15:0] val; + integer i; + begin + val = {16{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [15:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [16-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {16 {1'b1}} `else { $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {16 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [31:0] mem_phys_read_padr; +input [6:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [31:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [31:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 16'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 16'bx; + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [31:0] data; + reg [15:0] wr[1:0]; + integer i; + begin + for (i=0; i<=15; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [31:0] mon_bit_w; +input [6:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [31:0] mon_bit_r; +input [6:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [31:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [15:0] Q_0 = ITOP.iow0.arr[0]; +wire [15:0] Q_1 = ITOP.iow1.arr[0]; +wire [15:0] Q_2 = ITOP.iow0.arr[1]; +wire [15:0] Q_3 = ITOP.iow1.arr[1]; +wire [15:0] Q_4 = ITOP.iow0.arr[2]; +wire [15:0] Q_5 = ITOP.iow1.arr[2]; +wire [15:0] Q_6 = ITOP.iow0.arr[3]; +wire [15:0] Q_7 = ITOP.iow1.arr[3]; +wire [15:0] Q_8 = ITOP.iow0.arr[4]; +wire [15:0] Q_9 = ITOP.iow1.arr[4]; +wire [15:0] Q_10 = ITOP.iow0.arr[5]; +wire [15:0] Q_11 = ITOP.iow1.arr[5]; +wire [15:0] Q_12 = ITOP.iow0.arr[6]; +wire [15:0] Q_13 = ITOP.iow1.arr[6]; +wire [15:0] Q_14 = ITOP.iow0.arr[7]; +wire [15:0] Q_15 = ITOP.iow1.arr[7]; +wire [15:0] Q_16 = ITOP.iow0.arr[8]; +wire [15:0] Q_17 = ITOP.iow1.arr[8]; +wire [15:0] Q_18 = ITOP.iow0.arr[9]; +wire [15:0] Q_19 = ITOP.iow1.arr[9]; +wire [15:0] Q_20 = ITOP.iow0.arr[10]; +wire [15:0] Q_21 = ITOP.iow1.arr[10]; +wire [15:0] Q_22 = ITOP.iow0.arr[11]; +wire [15:0] Q_23 = ITOP.iow1.arr[11]; +wire [15:0] Q_24 = ITOP.iow0.arr[12]; +wire [15:0] Q_25 = ITOP.iow1.arr[12]; +wire [15:0] Q_26 = ITOP.iow0.arr[13]; +wire [15:0] Q_27 = ITOP.iow1.arr[13]; +wire [15:0] Q_28 = ITOP.iow0.arr[14]; +wire [15:0] Q_29 = ITOP.iow1.arr[14]; +wire [15:0] Q_30 = ITOP.iow0.arr[15]; +wire [15:0] Q_31 = ITOP.iow1.arr[15]; +wire [15:0] Q_32 = ITOP.iow0.arr[16]; +wire [15:0] Q_33 = ITOP.iow1.arr[16]; +wire [15:0] Q_34 = ITOP.iow0.arr[17]; +wire [15:0] Q_35 = ITOP.iow1.arr[17]; +wire [15:0] Q_36 = ITOP.iow0.arr[18]; +wire [15:0] Q_37 = ITOP.iow1.arr[18]; +wire [15:0] Q_38 = ITOP.iow0.arr[19]; +wire [15:0] Q_39 = ITOP.iow1.arr[19]; +wire [15:0] Q_40 = ITOP.iow0.arr[20]; +wire [15:0] Q_41 = ITOP.iow1.arr[20]; +wire [15:0] Q_42 = ITOP.iow0.arr[21]; +wire [15:0] Q_43 = ITOP.iow1.arr[21]; +wire [15:0] Q_44 = ITOP.iow0.arr[22]; +wire [15:0] Q_45 = ITOP.iow1.arr[22]; +wire [15:0] Q_46 = ITOP.iow0.arr[23]; +wire [15:0] Q_47 = ITOP.iow1.arr[23]; +wire [15:0] Q_48 = ITOP.iow0.arr[24]; +wire [15:0] Q_49 = ITOP.iow1.arr[24]; +wire [15:0] Q_50 = ITOP.iow0.arr[25]; +wire [15:0] Q_51 = ITOP.iow1.arr[25]; +wire [15:0] Q_52 = ITOP.iow0.arr[26]; +wire [15:0] Q_53 = ITOP.iow1.arr[26]; +wire [15:0] Q_54 = ITOP.iow0.arr[27]; +wire [15:0] Q_55 = ITOP.iow1.arr[27]; +wire [15:0] Q_56 = ITOP.iow0.arr[28]; +wire [15:0] Q_57 = ITOP.iow1.arr[28]; +wire [15:0] Q_58 = ITOP.iow0.arr[29]; +wire [15:0] Q_59 = ITOP.iow1.arr[29]; +wire [15:0] Q_60 = ITOP.iow0.arr[30]; +wire [15:0] Q_61 = ITOP.iow1.arr[30]; +wire [15:0] Q_62 = ITOP.iow0.arr[31]; +wire [15:0] Q_63 = ITOP.iow1.arr[31]; +wire [15:0] Q_64 = ITOP.iow0.arr[32]; +wire [15:0] Q_65 = ITOP.iow1.arr[32]; +wire [15:0] Q_66 = ITOP.iow0.arr[33]; +wire [15:0] Q_67 = ITOP.iow1.arr[33]; +wire [15:0] Q_68 = ITOP.iow0.arr[34]; +wire [15:0] Q_69 = ITOP.iow1.arr[34]; +wire [15:0] Q_70 = ITOP.iow0.arr[35]; +wire [15:0] Q_71 = ITOP.iow1.arr[35]; +wire [15:0] Q_72 = ITOP.iow0.arr[36]; +wire [15:0] Q_73 = ITOP.iow1.arr[36]; +wire [15:0] Q_74 = ITOP.iow0.arr[37]; +wire [15:0] Q_75 = ITOP.iow1.arr[37]; +wire [15:0] Q_76 = ITOP.iow0.arr[38]; +wire [15:0] Q_77 = ITOP.iow1.arr[38]; +wire [15:0] Q_78 = ITOP.iow0.arr[39]; +wire [15:0] Q_79 = ITOP.iow1.arr[39]; +wire [15:0] Q_80 = ITOP.iow0.arr[40]; +wire [15:0] Q_81 = ITOP.iow1.arr[40]; +wire [15:0] Q_82 = ITOP.iow0.arr[41]; +wire [15:0] Q_83 = ITOP.iow1.arr[41]; +wire [15:0] Q_84 = ITOP.iow0.arr[42]; +wire [15:0] Q_85 = ITOP.iow1.arr[42]; +wire [15:0] Q_86 = ITOP.iow0.arr[43]; +wire [15:0] Q_87 = ITOP.iow1.arr[43]; +wire [15:0] Q_88 = ITOP.iow0.arr[44]; +wire [15:0] Q_89 = ITOP.iow1.arr[44]; +wire [15:0] Q_90 = ITOP.iow0.arr[45]; +wire [15:0] Q_91 = ITOP.iow1.arr[45]; +wire [15:0] Q_92 = ITOP.iow0.arr[46]; +wire [15:0] Q_93 = ITOP.iow1.arr[46]; +wire [15:0] Q_94 = ITOP.iow0.arr[47]; +wire [15:0] Q_95 = ITOP.iow1.arr[47]; +wire [15:0] Q_96 = ITOP.iow0.arr[48]; +wire [15:0] Q_97 = ITOP.iow1.arr[48]; +wire [15:0] Q_98 = ITOP.iow0.arr[49]; +wire [15:0] Q_99 = ITOP.iow1.arr[49]; +wire [15:0] Q_100 = ITOP.iow0.arr[50]; +wire [15:0] Q_101 = ITOP.iow1.arr[50]; +wire [15:0] Q_102 = ITOP.iow0.arr[51]; +wire [15:0] Q_103 = ITOP.iow1.arr[51]; +wire [15:0] Q_104 = ITOP.iow0.arr[52]; +wire [15:0] Q_105 = ITOP.iow1.arr[52]; +wire [15:0] Q_106 = ITOP.iow0.arr[53]; +wire [15:0] Q_107 = ITOP.iow1.arr[53]; +wire [15:0] Q_108 = ITOP.iow0.arr[54]; +wire [15:0] Q_109 = ITOP.iow1.arr[54]; +wire [15:0] Q_110 = ITOP.iow0.arr[55]; +wire [15:0] Q_111 = ITOP.iow1.arr[55]; +wire [15:0] Q_112 = ITOP.iow0.arr[56]; +wire [15:0] Q_113 = ITOP.iow1.arr[56]; +wire [15:0] Q_114 = ITOP.iow0.arr[57]; +wire [15:0] Q_115 = ITOP.iow1.arr[57]; +wire [15:0] Q_116 = ITOP.iow0.arr[58]; +wire [15:0] Q_117 = ITOP.iow1.arr[58]; +wire [15:0] Q_118 = ITOP.iow0.arr[59]; +wire [15:0] Q_119 = ITOP.iow1.arr[59]; +wire [15:0] Q_120 = ITOP.iow0.arr[60]; +wire [15:0] Q_121 = ITOP.iow1.arr[60]; +wire [15:0] Q_122 = ITOP.iow0.arr[61]; +wire [15:0] Q_123 = ITOP.iow1.arr[61]; +wire [15:0] Q_124 = ITOP.iow0.arr[62]; +wire [15:0] Q_125 = ITOP.iow1.arr[62]; +wire [15:0] Q_126 = ITOP.iow0.arr[63]; +wire [15:0] Q_127 = ITOP.iow1.arr[63]; +wire [15:0] Q_128 = ITOP.iow0.arr[64]; +wire [15:0] Q_129 = ITOP.iow1.arr[64]; +wire [15:0] Q_130 = ITOP.iow0.arr[65]; +wire [15:0] Q_131 = ITOP.iow1.arr[65]; +wire [15:0] Q_132 = ITOP.iow0.arr[66]; +wire [15:0] Q_133 = ITOP.iow1.arr[66]; +wire [15:0] Q_134 = ITOP.iow0.arr[67]; +wire [15:0] Q_135 = ITOP.iow1.arr[67]; +wire [15:0] Q_136 = ITOP.iow0.arr[68]; +wire [15:0] Q_137 = ITOP.iow1.arr[68]; +wire [15:0] Q_138 = ITOP.iow0.arr[69]; +wire [15:0] Q_139 = ITOP.iow1.arr[69]; +wire [15:0] Q_140 = ITOP.iow0.arr[70]; +wire [15:0] Q_141 = ITOP.iow1.arr[70]; +wire [15:0] Q_142 = ITOP.iow0.arr[71]; +wire [15:0] Q_143 = ITOP.iow1.arr[71]; +wire [15:0] Q_144 = ITOP.iow0.arr[72]; +wire [15:0] Q_145 = ITOP.iow1.arr[72]; +wire [15:0] Q_146 = ITOP.iow0.arr[73]; +wire [15:0] Q_147 = ITOP.iow1.arr[73]; +wire [15:0] Q_148 = ITOP.iow0.arr[74]; +wire [15:0] Q_149 = ITOP.iow1.arr[74]; +wire [15:0] Q_150 = ITOP.iow0.arr[75]; +wire [15:0] Q_151 = ITOP.iow1.arr[75]; +wire [15:0] Q_152 = ITOP.iow0.arr[76]; +wire [15:0] Q_153 = ITOP.iow1.arr[76]; +wire [15:0] Q_154 = ITOP.iow0.arr[77]; +wire [15:0] Q_155 = ITOP.iow1.arr[77]; +wire [15:0] Q_156 = ITOP.iow0.arr[78]; +wire [15:0] Q_157 = ITOP.iow1.arr[78]; +wire [15:0] Q_158 = ITOP.iow0.arr[79]; +wire [15:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [15:0] WD_FF; + reg [15:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [15:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [15:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [15:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X16_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [15:0] WD; +input [7:0] RA, WA; +output [15:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [15:0] WDQ; + wire [15:0] WDBQ; + wire [15:0] WMNexp; + wire [15:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [15:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {16{1'b0}}; + assign SHFT = {16{1'b1}}; + reg [15:0] WDQ_pr; + wire [15:0] WDBQ_pr; + assign WMNexp = {16{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[15:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [15:0] dout; + wire [15:0] RD; + wire RD_rdnt; + wire [15:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [15:0] RDBYPASS = {16{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [15:0] force_x; +`ifndef SYNTHESIS + assign force_x = {16{1'bx}}; +`else + assign force_x = {16{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [15:0] rmuxd0, rmuxd1; + wire [15:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {16{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {16{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {16{RdClk0}} & ~dout0 ; + assign rmuxd1 = {16{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[15:0] <= (rmuxd0[15:0] | rmuxd1[15:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X16_GL_M2_D2_ram # (80, 16, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X16_GL_M2_D2_ram # (80, 16, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [15:0] data; + reg [15:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [15:0] mem_read_bank; +input [7:0] addr; +reg [15:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X16_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 16; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [64:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [64:0] val; + integer i; + begin + val = {65{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [64:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [65-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {65 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{1{1'b1}}) } `endif ; + else raminit_fullval = {65 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [129:0] mem_phys_read_padr; +input [6:0] addr; + reg [129:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [130-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {130 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {130 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [64:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=64; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [129:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [129:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [130-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {130 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {130 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [64:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=64; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [129:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [129:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [130-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {130 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {130 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [64:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 65'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 65'bx; + for (i=0; i<=64; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [129:0] data; + reg [64:0] wr[1:0]; + integer i; + begin + for (i=0; i<=64; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [129:0] mon_bit_w; +input [6:0] addr; + reg [129:0] mon_row; + reg [64:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=64; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [129:0] mon_bit_r; +input [6:0] addr; + reg [129:0] mon_row; + reg [64:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=64; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [129:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [64:0] Q_0 = ITOP.iow0.arr[0]; +wire [64:0] Q_1 = ITOP.iow1.arr[0]; +wire [64:0] Q_2 = ITOP.iow0.arr[1]; +wire [64:0] Q_3 = ITOP.iow1.arr[1]; +wire [64:0] Q_4 = ITOP.iow0.arr[2]; +wire [64:0] Q_5 = ITOP.iow1.arr[2]; +wire [64:0] Q_6 = ITOP.iow0.arr[3]; +wire [64:0] Q_7 = ITOP.iow1.arr[3]; +wire [64:0] Q_8 = ITOP.iow0.arr[4]; +wire [64:0] Q_9 = ITOP.iow1.arr[4]; +wire [64:0] Q_10 = ITOP.iow0.arr[5]; +wire [64:0] Q_11 = ITOP.iow1.arr[5]; +wire [64:0] Q_12 = ITOP.iow0.arr[6]; +wire [64:0] Q_13 = ITOP.iow1.arr[6]; +wire [64:0] Q_14 = ITOP.iow0.arr[7]; +wire [64:0] Q_15 = ITOP.iow1.arr[7]; +wire [64:0] Q_16 = ITOP.iow0.arr[8]; +wire [64:0] Q_17 = ITOP.iow1.arr[8]; +wire [64:0] Q_18 = ITOP.iow0.arr[9]; +wire [64:0] Q_19 = ITOP.iow1.arr[9]; +wire [64:0] Q_20 = ITOP.iow0.arr[10]; +wire [64:0] Q_21 = ITOP.iow1.arr[10]; +wire [64:0] Q_22 = ITOP.iow0.arr[11]; +wire [64:0] Q_23 = ITOP.iow1.arr[11]; +wire [64:0] Q_24 = ITOP.iow0.arr[12]; +wire [64:0] Q_25 = ITOP.iow1.arr[12]; +wire [64:0] Q_26 = ITOP.iow0.arr[13]; +wire [64:0] Q_27 = ITOP.iow1.arr[13]; +wire [64:0] Q_28 = ITOP.iow0.arr[14]; +wire [64:0] Q_29 = ITOP.iow1.arr[14]; +wire [64:0] Q_30 = ITOP.iow0.arr[15]; +wire [64:0] Q_31 = ITOP.iow1.arr[15]; +wire [64:0] Q_32 = ITOP.iow0.arr[16]; +wire [64:0] Q_33 = ITOP.iow1.arr[16]; +wire [64:0] Q_34 = ITOP.iow0.arr[17]; +wire [64:0] Q_35 = ITOP.iow1.arr[17]; +wire [64:0] Q_36 = ITOP.iow0.arr[18]; +wire [64:0] Q_37 = ITOP.iow1.arr[18]; +wire [64:0] Q_38 = ITOP.iow0.arr[19]; +wire [64:0] Q_39 = ITOP.iow1.arr[19]; +wire [64:0] Q_40 = ITOP.iow0.arr[20]; +wire [64:0] Q_41 = ITOP.iow1.arr[20]; +wire [64:0] Q_42 = ITOP.iow0.arr[21]; +wire [64:0] Q_43 = ITOP.iow1.arr[21]; +wire [64:0] Q_44 = ITOP.iow0.arr[22]; +wire [64:0] Q_45 = ITOP.iow1.arr[22]; +wire [64:0] Q_46 = ITOP.iow0.arr[23]; +wire [64:0] Q_47 = ITOP.iow1.arr[23]; +wire [64:0] Q_48 = ITOP.iow0.arr[24]; +wire [64:0] Q_49 = ITOP.iow1.arr[24]; +wire [64:0] Q_50 = ITOP.iow0.arr[25]; +wire [64:0] Q_51 = ITOP.iow1.arr[25]; +wire [64:0] Q_52 = ITOP.iow0.arr[26]; +wire [64:0] Q_53 = ITOP.iow1.arr[26]; +wire [64:0] Q_54 = ITOP.iow0.arr[27]; +wire [64:0] Q_55 = ITOP.iow1.arr[27]; +wire [64:0] Q_56 = ITOP.iow0.arr[28]; +wire [64:0] Q_57 = ITOP.iow1.arr[28]; +wire [64:0] Q_58 = ITOP.iow0.arr[29]; +wire [64:0] Q_59 = ITOP.iow1.arr[29]; +wire [64:0] Q_60 = ITOP.iow0.arr[30]; +wire [64:0] Q_61 = ITOP.iow1.arr[30]; +wire [64:0] Q_62 = ITOP.iow0.arr[31]; +wire [64:0] Q_63 = ITOP.iow1.arr[31]; +wire [64:0] Q_64 = ITOP.iow0.arr[32]; +wire [64:0] Q_65 = ITOP.iow1.arr[32]; +wire [64:0] Q_66 = ITOP.iow0.arr[33]; +wire [64:0] Q_67 = ITOP.iow1.arr[33]; +wire [64:0] Q_68 = ITOP.iow0.arr[34]; +wire [64:0] Q_69 = ITOP.iow1.arr[34]; +wire [64:0] Q_70 = ITOP.iow0.arr[35]; +wire [64:0] Q_71 = ITOP.iow1.arr[35]; +wire [64:0] Q_72 = ITOP.iow0.arr[36]; +wire [64:0] Q_73 = ITOP.iow1.arr[36]; +wire [64:0] Q_74 = ITOP.iow0.arr[37]; +wire [64:0] Q_75 = ITOP.iow1.arr[37]; +wire [64:0] Q_76 = ITOP.iow0.arr[38]; +wire [64:0] Q_77 = ITOP.iow1.arr[38]; +wire [64:0] Q_78 = ITOP.iow0.arr[39]; +wire [64:0] Q_79 = ITOP.iow1.arr[39]; +wire [64:0] Q_80 = ITOP.iow0.arr[40]; +wire [64:0] Q_81 = ITOP.iow1.arr[40]; +wire [64:0] Q_82 = ITOP.iow0.arr[41]; +wire [64:0] Q_83 = ITOP.iow1.arr[41]; +wire [64:0] Q_84 = ITOP.iow0.arr[42]; +wire [64:0] Q_85 = ITOP.iow1.arr[42]; +wire [64:0] Q_86 = ITOP.iow0.arr[43]; +wire [64:0] Q_87 = ITOP.iow1.arr[43]; +wire [64:0] Q_88 = ITOP.iow0.arr[44]; +wire [64:0] Q_89 = ITOP.iow1.arr[44]; +wire [64:0] Q_90 = ITOP.iow0.arr[45]; +wire [64:0] Q_91 = ITOP.iow1.arr[45]; +wire [64:0] Q_92 = ITOP.iow0.arr[46]; +wire [64:0] Q_93 = ITOP.iow1.arr[46]; +wire [64:0] Q_94 = ITOP.iow0.arr[47]; +wire [64:0] Q_95 = ITOP.iow1.arr[47]; +wire [64:0] Q_96 = ITOP.iow0.arr[48]; +wire [64:0] Q_97 = ITOP.iow1.arr[48]; +wire [64:0] Q_98 = ITOP.iow0.arr[49]; +wire [64:0] Q_99 = ITOP.iow1.arr[49]; +wire [64:0] Q_100 = ITOP.iow0.arr[50]; +wire [64:0] Q_101 = ITOP.iow1.arr[50]; +wire [64:0] Q_102 = ITOP.iow0.arr[51]; +wire [64:0] Q_103 = ITOP.iow1.arr[51]; +wire [64:0] Q_104 = ITOP.iow0.arr[52]; +wire [64:0] Q_105 = ITOP.iow1.arr[52]; +wire [64:0] Q_106 = ITOP.iow0.arr[53]; +wire [64:0] Q_107 = ITOP.iow1.arr[53]; +wire [64:0] Q_108 = ITOP.iow0.arr[54]; +wire [64:0] Q_109 = ITOP.iow1.arr[54]; +wire [64:0] Q_110 = ITOP.iow0.arr[55]; +wire [64:0] Q_111 = ITOP.iow1.arr[55]; +wire [64:0] Q_112 = ITOP.iow0.arr[56]; +wire [64:0] Q_113 = ITOP.iow1.arr[56]; +wire [64:0] Q_114 = ITOP.iow0.arr[57]; +wire [64:0] Q_115 = ITOP.iow1.arr[57]; +wire [64:0] Q_116 = ITOP.iow0.arr[58]; +wire [64:0] Q_117 = ITOP.iow1.arr[58]; +wire [64:0] Q_118 = ITOP.iow0.arr[59]; +wire [64:0] Q_119 = ITOP.iow1.arr[59]; +wire [64:0] Q_120 = ITOP.iow0.arr[60]; +wire [64:0] Q_121 = ITOP.iow1.arr[60]; +wire [64:0] Q_122 = ITOP.iow0.arr[61]; +wire [64:0] Q_123 = ITOP.iow1.arr[61]; +wire [64:0] Q_124 = ITOP.iow0.arr[62]; +wire [64:0] Q_125 = ITOP.iow1.arr[62]; +wire [64:0] Q_126 = ITOP.iow0.arr[63]; +wire [64:0] Q_127 = ITOP.iow1.arr[63]; +wire [64:0] Q_128 = ITOP.iow0.arr[64]; +wire [64:0] Q_129 = ITOP.iow1.arr[64]; +wire [64:0] Q_130 = ITOP.iow0.arr[65]; +wire [64:0] Q_131 = ITOP.iow1.arr[65]; +wire [64:0] Q_132 = ITOP.iow0.arr[66]; +wire [64:0] Q_133 = ITOP.iow1.arr[66]; +wire [64:0] Q_134 = ITOP.iow0.arr[67]; +wire [64:0] Q_135 = ITOP.iow1.arr[67]; +wire [64:0] Q_136 = ITOP.iow0.arr[68]; +wire [64:0] Q_137 = ITOP.iow1.arr[68]; +wire [64:0] Q_138 = ITOP.iow0.arr[69]; +wire [64:0] Q_139 = ITOP.iow1.arr[69]; +wire [64:0] Q_140 = ITOP.iow0.arr[70]; +wire [64:0] Q_141 = ITOP.iow1.arr[70]; +wire [64:0] Q_142 = ITOP.iow0.arr[71]; +wire [64:0] Q_143 = ITOP.iow1.arr[71]; +wire [64:0] Q_144 = ITOP.iow0.arr[72]; +wire [64:0] Q_145 = ITOP.iow1.arr[72]; +wire [64:0] Q_146 = ITOP.iow0.arr[73]; +wire [64:0] Q_147 = ITOP.iow1.arr[73]; +wire [64:0] Q_148 = ITOP.iow0.arr[74]; +wire [64:0] Q_149 = ITOP.iow1.arr[74]; +wire [64:0] Q_150 = ITOP.iow0.arr[75]; +wire [64:0] Q_151 = ITOP.iow1.arr[75]; +wire [64:0] Q_152 = ITOP.iow0.arr[76]; +wire [64:0] Q_153 = ITOP.iow1.arr[76]; +wire [64:0] Q_154 = ITOP.iow0.arr[77]; +wire [64:0] Q_155 = ITOP.iow1.arr[77]; +wire [64:0] Q_156 = ITOP.iow0.arr[78]; +wire [64:0] Q_157 = ITOP.iow1.arr[78]; +wire [64:0] Q_158 = ITOP.iow0.arr[79]; +wire [64:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [64:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [64:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [64:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [64:0] WD_FF; + reg [64:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [64:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [64:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [64:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X65_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [64:0] WD; +input [7:0] RA, WA; +output [64:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [64:0] WDQ; + wire [64:0] WDBQ; + wire [64:0] WMNexp; + wire [64:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [64:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {65{1'b0}}; + assign SHFT = {65{1'b1}}; + reg [64:0] WDQ_pr; + wire [64:0] WDBQ_pr; + assign WMNexp = {65{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[64:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [64:0] dout; + wire [64:0] RD; + wire RD_rdnt; + wire [64:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [64:0] RDBYPASS = {65{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [64:0] force_x; +`ifndef SYNTHESIS + assign force_x = {65{1'bx}}; +`else + assign force_x = {65{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [64:0] rmuxd0, rmuxd1; + wire [64:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {65{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {65{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {65{RdClk0}} & ~dout0 ; + assign rmuxd1 = {65{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[64:0] <= (rmuxd0[64:0] | rmuxd1[64:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X65_GL_M2_D2_ram # (80, 65, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X65_GL_M2_D2_ram # (80, 65, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [64:0] data; + reg [64:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [64:0] mem_read_bank; +input [7:0] addr; +reg [64:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X65_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 65; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [64:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [64:0] val; + integer i; + begin + val = {65{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [64:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [65-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {65 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{1{1'b1}}) } `endif ; + else raminit_fullval = {65 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [129:0] mem_phys_read_padr; +input [6:0] addr; + reg [129:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [130-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {130 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {130 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [64:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=64; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [129:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [129:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [130-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {130 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {130 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [64:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=64; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [129:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [129:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [130-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {130 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {130 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [64:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 65'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 65'bx; + for (i=0; i<=64; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [129:0] data; + reg [64:0] wr[1:0]; + integer i; + begin + for (i=0; i<=64; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [129:0] mon_bit_w; +input [6:0] addr; + reg [129:0] mon_row; + reg [64:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=64; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [129:0] mon_bit_r; +input [6:0] addr; + reg [129:0] mon_row; + reg [64:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=64; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [129:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<130; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [64:0] Q_0 = ITOP.iow0.arr[0]; +wire [64:0] Q_1 = ITOP.iow1.arr[0]; +wire [64:0] Q_2 = ITOP.iow0.arr[1]; +wire [64:0] Q_3 = ITOP.iow1.arr[1]; +wire [64:0] Q_4 = ITOP.iow0.arr[2]; +wire [64:0] Q_5 = ITOP.iow1.arr[2]; +wire [64:0] Q_6 = ITOP.iow0.arr[3]; +wire [64:0] Q_7 = ITOP.iow1.arr[3]; +wire [64:0] Q_8 = ITOP.iow0.arr[4]; +wire [64:0] Q_9 = ITOP.iow1.arr[4]; +wire [64:0] Q_10 = ITOP.iow0.arr[5]; +wire [64:0] Q_11 = ITOP.iow1.arr[5]; +wire [64:0] Q_12 = ITOP.iow0.arr[6]; +wire [64:0] Q_13 = ITOP.iow1.arr[6]; +wire [64:0] Q_14 = ITOP.iow0.arr[7]; +wire [64:0] Q_15 = ITOP.iow1.arr[7]; +wire [64:0] Q_16 = ITOP.iow0.arr[8]; +wire [64:0] Q_17 = ITOP.iow1.arr[8]; +wire [64:0] Q_18 = ITOP.iow0.arr[9]; +wire [64:0] Q_19 = ITOP.iow1.arr[9]; +wire [64:0] Q_20 = ITOP.iow0.arr[10]; +wire [64:0] Q_21 = ITOP.iow1.arr[10]; +wire [64:0] Q_22 = ITOP.iow0.arr[11]; +wire [64:0] Q_23 = ITOP.iow1.arr[11]; +wire [64:0] Q_24 = ITOP.iow0.arr[12]; +wire [64:0] Q_25 = ITOP.iow1.arr[12]; +wire [64:0] Q_26 = ITOP.iow0.arr[13]; +wire [64:0] Q_27 = ITOP.iow1.arr[13]; +wire [64:0] Q_28 = ITOP.iow0.arr[14]; +wire [64:0] Q_29 = ITOP.iow1.arr[14]; +wire [64:0] Q_30 = ITOP.iow0.arr[15]; +wire [64:0] Q_31 = ITOP.iow1.arr[15]; +wire [64:0] Q_32 = ITOP.iow0.arr[16]; +wire [64:0] Q_33 = ITOP.iow1.arr[16]; +wire [64:0] Q_34 = ITOP.iow0.arr[17]; +wire [64:0] Q_35 = ITOP.iow1.arr[17]; +wire [64:0] Q_36 = ITOP.iow0.arr[18]; +wire [64:0] Q_37 = ITOP.iow1.arr[18]; +wire [64:0] Q_38 = ITOP.iow0.arr[19]; +wire [64:0] Q_39 = ITOP.iow1.arr[19]; +wire [64:0] Q_40 = ITOP.iow0.arr[20]; +wire [64:0] Q_41 = ITOP.iow1.arr[20]; +wire [64:0] Q_42 = ITOP.iow0.arr[21]; +wire [64:0] Q_43 = ITOP.iow1.arr[21]; +wire [64:0] Q_44 = ITOP.iow0.arr[22]; +wire [64:0] Q_45 = ITOP.iow1.arr[22]; +wire [64:0] Q_46 = ITOP.iow0.arr[23]; +wire [64:0] Q_47 = ITOP.iow1.arr[23]; +wire [64:0] Q_48 = ITOP.iow0.arr[24]; +wire [64:0] Q_49 = ITOP.iow1.arr[24]; +wire [64:0] Q_50 = ITOP.iow0.arr[25]; +wire [64:0] Q_51 = ITOP.iow1.arr[25]; +wire [64:0] Q_52 = ITOP.iow0.arr[26]; +wire [64:0] Q_53 = ITOP.iow1.arr[26]; +wire [64:0] Q_54 = ITOP.iow0.arr[27]; +wire [64:0] Q_55 = ITOP.iow1.arr[27]; +wire [64:0] Q_56 = ITOP.iow0.arr[28]; +wire [64:0] Q_57 = ITOP.iow1.arr[28]; +wire [64:0] Q_58 = ITOP.iow0.arr[29]; +wire [64:0] Q_59 = ITOP.iow1.arr[29]; +wire [64:0] Q_60 = ITOP.iow0.arr[30]; +wire [64:0] Q_61 = ITOP.iow1.arr[30]; +wire [64:0] Q_62 = ITOP.iow0.arr[31]; +wire [64:0] Q_63 = ITOP.iow1.arr[31]; +wire [64:0] Q_64 = ITOP.iow0.arr[32]; +wire [64:0] Q_65 = ITOP.iow1.arr[32]; +wire [64:0] Q_66 = ITOP.iow0.arr[33]; +wire [64:0] Q_67 = ITOP.iow1.arr[33]; +wire [64:0] Q_68 = ITOP.iow0.arr[34]; +wire [64:0] Q_69 = ITOP.iow1.arr[34]; +wire [64:0] Q_70 = ITOP.iow0.arr[35]; +wire [64:0] Q_71 = ITOP.iow1.arr[35]; +wire [64:0] Q_72 = ITOP.iow0.arr[36]; +wire [64:0] Q_73 = ITOP.iow1.arr[36]; +wire [64:0] Q_74 = ITOP.iow0.arr[37]; +wire [64:0] Q_75 = ITOP.iow1.arr[37]; +wire [64:0] Q_76 = ITOP.iow0.arr[38]; +wire [64:0] Q_77 = ITOP.iow1.arr[38]; +wire [64:0] Q_78 = ITOP.iow0.arr[39]; +wire [64:0] Q_79 = ITOP.iow1.arr[39]; +wire [64:0] Q_80 = ITOP.iow0.arr[40]; +wire [64:0] Q_81 = ITOP.iow1.arr[40]; +wire [64:0] Q_82 = ITOP.iow0.arr[41]; +wire [64:0] Q_83 = ITOP.iow1.arr[41]; +wire [64:0] Q_84 = ITOP.iow0.arr[42]; +wire [64:0] Q_85 = ITOP.iow1.arr[42]; +wire [64:0] Q_86 = ITOP.iow0.arr[43]; +wire [64:0] Q_87 = ITOP.iow1.arr[43]; +wire [64:0] Q_88 = ITOP.iow0.arr[44]; +wire [64:0] Q_89 = ITOP.iow1.arr[44]; +wire [64:0] Q_90 = ITOP.iow0.arr[45]; +wire [64:0] Q_91 = ITOP.iow1.arr[45]; +wire [64:0] Q_92 = ITOP.iow0.arr[46]; +wire [64:0] Q_93 = ITOP.iow1.arr[46]; +wire [64:0] Q_94 = ITOP.iow0.arr[47]; +wire [64:0] Q_95 = ITOP.iow1.arr[47]; +wire [64:0] Q_96 = ITOP.iow0.arr[48]; +wire [64:0] Q_97 = ITOP.iow1.arr[48]; +wire [64:0] Q_98 = ITOP.iow0.arr[49]; +wire [64:0] Q_99 = ITOP.iow1.arr[49]; +wire [64:0] Q_100 = ITOP.iow0.arr[50]; +wire [64:0] Q_101 = ITOP.iow1.arr[50]; +wire [64:0] Q_102 = ITOP.iow0.arr[51]; +wire [64:0] Q_103 = ITOP.iow1.arr[51]; +wire [64:0] Q_104 = ITOP.iow0.arr[52]; +wire [64:0] Q_105 = ITOP.iow1.arr[52]; +wire [64:0] Q_106 = ITOP.iow0.arr[53]; +wire [64:0] Q_107 = ITOP.iow1.arr[53]; +wire [64:0] Q_108 = ITOP.iow0.arr[54]; +wire [64:0] Q_109 = ITOP.iow1.arr[54]; +wire [64:0] Q_110 = ITOP.iow0.arr[55]; +wire [64:0] Q_111 = ITOP.iow1.arr[55]; +wire [64:0] Q_112 = ITOP.iow0.arr[56]; +wire [64:0] Q_113 = ITOP.iow1.arr[56]; +wire [64:0] Q_114 = ITOP.iow0.arr[57]; +wire [64:0] Q_115 = ITOP.iow1.arr[57]; +wire [64:0] Q_116 = ITOP.iow0.arr[58]; +wire [64:0] Q_117 = ITOP.iow1.arr[58]; +wire [64:0] Q_118 = ITOP.iow0.arr[59]; +wire [64:0] Q_119 = ITOP.iow1.arr[59]; +wire [64:0] Q_120 = ITOP.iow0.arr[60]; +wire [64:0] Q_121 = ITOP.iow1.arr[60]; +wire [64:0] Q_122 = ITOP.iow0.arr[61]; +wire [64:0] Q_123 = ITOP.iow1.arr[61]; +wire [64:0] Q_124 = ITOP.iow0.arr[62]; +wire [64:0] Q_125 = ITOP.iow1.arr[62]; +wire [64:0] Q_126 = ITOP.iow0.arr[63]; +wire [64:0] Q_127 = ITOP.iow1.arr[63]; +wire [64:0] Q_128 = ITOP.iow0.arr[64]; +wire [64:0] Q_129 = ITOP.iow1.arr[64]; +wire [64:0] Q_130 = ITOP.iow0.arr[65]; +wire [64:0] Q_131 = ITOP.iow1.arr[65]; +wire [64:0] Q_132 = ITOP.iow0.arr[66]; +wire [64:0] Q_133 = ITOP.iow1.arr[66]; +wire [64:0] Q_134 = ITOP.iow0.arr[67]; +wire [64:0] Q_135 = ITOP.iow1.arr[67]; +wire [64:0] Q_136 = ITOP.iow0.arr[68]; +wire [64:0] Q_137 = ITOP.iow1.arr[68]; +wire [64:0] Q_138 = ITOP.iow0.arr[69]; +wire [64:0] Q_139 = ITOP.iow1.arr[69]; +wire [64:0] Q_140 = ITOP.iow0.arr[70]; +wire [64:0] Q_141 = ITOP.iow1.arr[70]; +wire [64:0] Q_142 = ITOP.iow0.arr[71]; +wire [64:0] Q_143 = ITOP.iow1.arr[71]; +wire [64:0] Q_144 = ITOP.iow0.arr[72]; +wire [64:0] Q_145 = ITOP.iow1.arr[72]; +wire [64:0] Q_146 = ITOP.iow0.arr[73]; +wire [64:0] Q_147 = ITOP.iow1.arr[73]; +wire [64:0] Q_148 = ITOP.iow0.arr[74]; +wire [64:0] Q_149 = ITOP.iow1.arr[74]; +wire [64:0] Q_150 = ITOP.iow0.arr[75]; +wire [64:0] Q_151 = ITOP.iow1.arr[75]; +wire [64:0] Q_152 = ITOP.iow0.arr[76]; +wire [64:0] Q_153 = ITOP.iow1.arr[76]; +wire [64:0] Q_154 = ITOP.iow0.arr[77]; +wire [64:0] Q_155 = ITOP.iow1.arr[77]; +wire [64:0] Q_156 = ITOP.iow0.arr[78]; +wire [64:0] Q_157 = ITOP.iow1.arr[78]; +wire [64:0] Q_158 = ITOP.iow0.arr[79]; +wire [64:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [64:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [64:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [64:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [64:0] WD_FF; + reg [64:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [64:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [64:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [64:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X65_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [64:0] WD; +input [7:0] RA, WA; +output [64:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [64:0] WDQ; + wire [64:0] WDBQ; + wire [64:0] WMNexp; + wire [64:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [64:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {65{1'b0}}; + assign SHFT = {65{1'b1}}; + reg [64:0] WDQ_pr; + wire [64:0] WDBQ_pr; + assign WMNexp = {65{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[64:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [64:0] dout; + wire [64:0] RD; + wire RD_rdnt; + wire [64:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [64:0] RDBYPASS = {65{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [64:0] force_x; +`ifndef SYNTHESIS + assign force_x = {65{1'bx}}; +`else + assign force_x = {65{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [64:0] rmuxd0, rmuxd1; + wire [64:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {65{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {65{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {65{RdClk0}} & ~dout0 ; + assign rmuxd1 = {65{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[64:0] <= (rmuxd0[64:0] | rmuxd1[64:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X65_GL_M2_D2_ram # (80, 65, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X65_GL_M2_D2_ram # (80, 65, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [64:0] data; + reg [64:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [64:0] mem_read_bank; +input [7:0] addr; +reg [64:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X65_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 65; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [81:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [81:0] val; + integer i; + begin + val = {82{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [81:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [82-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {82 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{18{1'b1}}) } `endif ; + else raminit_fullval = {82 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [163:0] mem_phys_read_padr; +input [6:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [163:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [163:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 82'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 82'bx; + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [163:0] data; + reg [81:0] wr[1:0]; + integer i; + begin + for (i=0; i<=81; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [163:0] mon_bit_w; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [163:0] mon_bit_r; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [163:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [81:0] Q_0 = ITOP.iow0.arr[0]; +wire [81:0] Q_1 = ITOP.iow1.arr[0]; +wire [81:0] Q_2 = ITOP.iow0.arr[1]; +wire [81:0] Q_3 = ITOP.iow1.arr[1]; +wire [81:0] Q_4 = ITOP.iow0.arr[2]; +wire [81:0] Q_5 = ITOP.iow1.arr[2]; +wire [81:0] Q_6 = ITOP.iow0.arr[3]; +wire [81:0] Q_7 = ITOP.iow1.arr[3]; +wire [81:0] Q_8 = ITOP.iow0.arr[4]; +wire [81:0] Q_9 = ITOP.iow1.arr[4]; +wire [81:0] Q_10 = ITOP.iow0.arr[5]; +wire [81:0] Q_11 = ITOP.iow1.arr[5]; +wire [81:0] Q_12 = ITOP.iow0.arr[6]; +wire [81:0] Q_13 = ITOP.iow1.arr[6]; +wire [81:0] Q_14 = ITOP.iow0.arr[7]; +wire [81:0] Q_15 = ITOP.iow1.arr[7]; +wire [81:0] Q_16 = ITOP.iow0.arr[8]; +wire [81:0] Q_17 = ITOP.iow1.arr[8]; +wire [81:0] Q_18 = ITOP.iow0.arr[9]; +wire [81:0] Q_19 = ITOP.iow1.arr[9]; +wire [81:0] Q_20 = ITOP.iow0.arr[10]; +wire [81:0] Q_21 = ITOP.iow1.arr[10]; +wire [81:0] Q_22 = ITOP.iow0.arr[11]; +wire [81:0] Q_23 = ITOP.iow1.arr[11]; +wire [81:0] Q_24 = ITOP.iow0.arr[12]; +wire [81:0] Q_25 = ITOP.iow1.arr[12]; +wire [81:0] Q_26 = ITOP.iow0.arr[13]; +wire [81:0] Q_27 = ITOP.iow1.arr[13]; +wire [81:0] Q_28 = ITOP.iow0.arr[14]; +wire [81:0] Q_29 = ITOP.iow1.arr[14]; +wire [81:0] Q_30 = ITOP.iow0.arr[15]; +wire [81:0] Q_31 = ITOP.iow1.arr[15]; +wire [81:0] Q_32 = ITOP.iow0.arr[16]; +wire [81:0] Q_33 = ITOP.iow1.arr[16]; +wire [81:0] Q_34 = ITOP.iow0.arr[17]; +wire [81:0] Q_35 = ITOP.iow1.arr[17]; +wire [81:0] Q_36 = ITOP.iow0.arr[18]; +wire [81:0] Q_37 = ITOP.iow1.arr[18]; +wire [81:0] Q_38 = ITOP.iow0.arr[19]; +wire [81:0] Q_39 = ITOP.iow1.arr[19]; +wire [81:0] Q_40 = ITOP.iow0.arr[20]; +wire [81:0] Q_41 = ITOP.iow1.arr[20]; +wire [81:0] Q_42 = ITOP.iow0.arr[21]; +wire [81:0] Q_43 = ITOP.iow1.arr[21]; +wire [81:0] Q_44 = ITOP.iow0.arr[22]; +wire [81:0] Q_45 = ITOP.iow1.arr[22]; +wire [81:0] Q_46 = ITOP.iow0.arr[23]; +wire [81:0] Q_47 = ITOP.iow1.arr[23]; +wire [81:0] Q_48 = ITOP.iow0.arr[24]; +wire [81:0] Q_49 = ITOP.iow1.arr[24]; +wire [81:0] Q_50 = ITOP.iow0.arr[25]; +wire [81:0] Q_51 = ITOP.iow1.arr[25]; +wire [81:0] Q_52 = ITOP.iow0.arr[26]; +wire [81:0] Q_53 = ITOP.iow1.arr[26]; +wire [81:0] Q_54 = ITOP.iow0.arr[27]; +wire [81:0] Q_55 = ITOP.iow1.arr[27]; +wire [81:0] Q_56 = ITOP.iow0.arr[28]; +wire [81:0] Q_57 = ITOP.iow1.arr[28]; +wire [81:0] Q_58 = ITOP.iow0.arr[29]; +wire [81:0] Q_59 = ITOP.iow1.arr[29]; +wire [81:0] Q_60 = ITOP.iow0.arr[30]; +wire [81:0] Q_61 = ITOP.iow1.arr[30]; +wire [81:0] Q_62 = ITOP.iow0.arr[31]; +wire [81:0] Q_63 = ITOP.iow1.arr[31]; +wire [81:0] Q_64 = ITOP.iow0.arr[32]; +wire [81:0] Q_65 = ITOP.iow1.arr[32]; +wire [81:0] Q_66 = ITOP.iow0.arr[33]; +wire [81:0] Q_67 = ITOP.iow1.arr[33]; +wire [81:0] Q_68 = ITOP.iow0.arr[34]; +wire [81:0] Q_69 = ITOP.iow1.arr[34]; +wire [81:0] Q_70 = ITOP.iow0.arr[35]; +wire [81:0] Q_71 = ITOP.iow1.arr[35]; +wire [81:0] Q_72 = ITOP.iow0.arr[36]; +wire [81:0] Q_73 = ITOP.iow1.arr[36]; +wire [81:0] Q_74 = ITOP.iow0.arr[37]; +wire [81:0] Q_75 = ITOP.iow1.arr[37]; +wire [81:0] Q_76 = ITOP.iow0.arr[38]; +wire [81:0] Q_77 = ITOP.iow1.arr[38]; +wire [81:0] Q_78 = ITOP.iow0.arr[39]; +wire [81:0] Q_79 = ITOP.iow1.arr[39]; +wire [81:0] Q_80 = ITOP.iow0.arr[40]; +wire [81:0] Q_81 = ITOP.iow1.arr[40]; +wire [81:0] Q_82 = ITOP.iow0.arr[41]; +wire [81:0] Q_83 = ITOP.iow1.arr[41]; +wire [81:0] Q_84 = ITOP.iow0.arr[42]; +wire [81:0] Q_85 = ITOP.iow1.arr[42]; +wire [81:0] Q_86 = ITOP.iow0.arr[43]; +wire [81:0] Q_87 = ITOP.iow1.arr[43]; +wire [81:0] Q_88 = ITOP.iow0.arr[44]; +wire [81:0] Q_89 = ITOP.iow1.arr[44]; +wire [81:0] Q_90 = ITOP.iow0.arr[45]; +wire [81:0] Q_91 = ITOP.iow1.arr[45]; +wire [81:0] Q_92 = ITOP.iow0.arr[46]; +wire [81:0] Q_93 = ITOP.iow1.arr[46]; +wire [81:0] Q_94 = ITOP.iow0.arr[47]; +wire [81:0] Q_95 = ITOP.iow1.arr[47]; +wire [81:0] Q_96 = ITOP.iow0.arr[48]; +wire [81:0] Q_97 = ITOP.iow1.arr[48]; +wire [81:0] Q_98 = ITOP.iow0.arr[49]; +wire [81:0] Q_99 = ITOP.iow1.arr[49]; +wire [81:0] Q_100 = ITOP.iow0.arr[50]; +wire [81:0] Q_101 = ITOP.iow1.arr[50]; +wire [81:0] Q_102 = ITOP.iow0.arr[51]; +wire [81:0] Q_103 = ITOP.iow1.arr[51]; +wire [81:0] Q_104 = ITOP.iow0.arr[52]; +wire [81:0] Q_105 = ITOP.iow1.arr[52]; +wire [81:0] Q_106 = ITOP.iow0.arr[53]; +wire [81:0] Q_107 = ITOP.iow1.arr[53]; +wire [81:0] Q_108 = ITOP.iow0.arr[54]; +wire [81:0] Q_109 = ITOP.iow1.arr[54]; +wire [81:0] Q_110 = ITOP.iow0.arr[55]; +wire [81:0] Q_111 = ITOP.iow1.arr[55]; +wire [81:0] Q_112 = ITOP.iow0.arr[56]; +wire [81:0] Q_113 = ITOP.iow1.arr[56]; +wire [81:0] Q_114 = ITOP.iow0.arr[57]; +wire [81:0] Q_115 = ITOP.iow1.arr[57]; +wire [81:0] Q_116 = ITOP.iow0.arr[58]; +wire [81:0] Q_117 = ITOP.iow1.arr[58]; +wire [81:0] Q_118 = ITOP.iow0.arr[59]; +wire [81:0] Q_119 = ITOP.iow1.arr[59]; +wire [81:0] Q_120 = ITOP.iow0.arr[60]; +wire [81:0] Q_121 = ITOP.iow1.arr[60]; +wire [81:0] Q_122 = ITOP.iow0.arr[61]; +wire [81:0] Q_123 = ITOP.iow1.arr[61]; +wire [81:0] Q_124 = ITOP.iow0.arr[62]; +wire [81:0] Q_125 = ITOP.iow1.arr[62]; +wire [81:0] Q_126 = ITOP.iow0.arr[63]; +wire [81:0] Q_127 = ITOP.iow1.arr[63]; +wire [81:0] Q_128 = ITOP.iow0.arr[64]; +wire [81:0] Q_129 = ITOP.iow1.arr[64]; +wire [81:0] Q_130 = ITOP.iow0.arr[65]; +wire [81:0] Q_131 = ITOP.iow1.arr[65]; +wire [81:0] Q_132 = ITOP.iow0.arr[66]; +wire [81:0] Q_133 = ITOP.iow1.arr[66]; +wire [81:0] Q_134 = ITOP.iow0.arr[67]; +wire [81:0] Q_135 = ITOP.iow1.arr[67]; +wire [81:0] Q_136 = ITOP.iow0.arr[68]; +wire [81:0] Q_137 = ITOP.iow1.arr[68]; +wire [81:0] Q_138 = ITOP.iow0.arr[69]; +wire [81:0] Q_139 = ITOP.iow1.arr[69]; +wire [81:0] Q_140 = ITOP.iow0.arr[70]; +wire [81:0] Q_141 = ITOP.iow1.arr[70]; +wire [81:0] Q_142 = ITOP.iow0.arr[71]; +wire [81:0] Q_143 = ITOP.iow1.arr[71]; +wire [81:0] Q_144 = ITOP.iow0.arr[72]; +wire [81:0] Q_145 = ITOP.iow1.arr[72]; +wire [81:0] Q_146 = ITOP.iow0.arr[73]; +wire [81:0] Q_147 = ITOP.iow1.arr[73]; +wire [81:0] Q_148 = ITOP.iow0.arr[74]; +wire [81:0] Q_149 = ITOP.iow1.arr[74]; +wire [81:0] Q_150 = ITOP.iow0.arr[75]; +wire [81:0] Q_151 = ITOP.iow1.arr[75]; +wire [81:0] Q_152 = ITOP.iow0.arr[76]; +wire [81:0] Q_153 = ITOP.iow1.arr[76]; +wire [81:0] Q_154 = ITOP.iow0.arr[77]; +wire [81:0] Q_155 = ITOP.iow1.arr[77]; +wire [81:0] Q_156 = ITOP.iow0.arr[78]; +wire [81:0] Q_157 = ITOP.iow1.arr[78]; +wire [81:0] Q_158 = ITOP.iow0.arr[79]; +wire [81:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [81:0] WD_FF; + reg [81:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [81:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [81:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [81:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X82_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [81:0] WD; +input [7:0] RA, WA; +output [81:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [81:0] WDQ; + wire [81:0] WDBQ; + wire [81:0] WMNexp; + wire [81:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [81:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {82{1'b0}}; + assign SHFT = {82{1'b1}}; + reg [81:0] WDQ_pr; + wire [81:0] WDBQ_pr; + assign WMNexp = {82{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[81:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [81:0] dout; + wire [81:0] RD; + wire RD_rdnt; + wire [81:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [81:0] RDBYPASS = {82{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [81:0] force_x; +`ifndef SYNTHESIS + assign force_x = {82{1'bx}}; +`else + assign force_x = {82{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [81:0] rmuxd0, rmuxd1; + wire [81:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {82{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {82{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {82{RdClk0}} & ~dout0 ; + assign rmuxd1 = {82{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[81:0] <= (rmuxd0[81:0] | rmuxd1[81:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X82_GL_M2_D2_ram # (80, 82, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X82_GL_M2_D2_ram # (80, 82, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [81:0] data; + reg [81:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [81:0] mem_read_bank; +input [7:0] addr; +reg [81:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X82_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 82; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [81:0] val; + integer i; + begin + for (i=0; i<160; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [81:0] val; + integer i; + begin + val = {82{fill_bit}}; + for (i=0; i<160; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [81:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [82-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {82 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{18{1'b1}}) } `endif ; + else raminit_fullval = {82 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [163:0] mem_phys_read_padr; +input [6:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [163:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [163:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 82'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 82'bx; + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [163:0] data; + reg [81:0] wr[1:0]; + integer i; + begin + for (i=0; i<=81; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [163:0] mon_bit_w; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [163:0] mon_bit_r; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [163:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [81:0] Q_0 = ITOP.iow0.arr[0]; +wire [81:0] Q_1 = ITOP.iow1.arr[0]; +wire [81:0] Q_2 = ITOP.iow0.arr[1]; +wire [81:0] Q_3 = ITOP.iow1.arr[1]; +wire [81:0] Q_4 = ITOP.iow0.arr[2]; +wire [81:0] Q_5 = ITOP.iow1.arr[2]; +wire [81:0] Q_6 = ITOP.iow0.arr[3]; +wire [81:0] Q_7 = ITOP.iow1.arr[3]; +wire [81:0] Q_8 = ITOP.iow0.arr[4]; +wire [81:0] Q_9 = ITOP.iow1.arr[4]; +wire [81:0] Q_10 = ITOP.iow0.arr[5]; +wire [81:0] Q_11 = ITOP.iow1.arr[5]; +wire [81:0] Q_12 = ITOP.iow0.arr[6]; +wire [81:0] Q_13 = ITOP.iow1.arr[6]; +wire [81:0] Q_14 = ITOP.iow0.arr[7]; +wire [81:0] Q_15 = ITOP.iow1.arr[7]; +wire [81:0] Q_16 = ITOP.iow0.arr[8]; +wire [81:0] Q_17 = ITOP.iow1.arr[8]; +wire [81:0] Q_18 = ITOP.iow0.arr[9]; +wire [81:0] Q_19 = ITOP.iow1.arr[9]; +wire [81:0] Q_20 = ITOP.iow0.arr[10]; +wire [81:0] Q_21 = ITOP.iow1.arr[10]; +wire [81:0] Q_22 = ITOP.iow0.arr[11]; +wire [81:0] Q_23 = ITOP.iow1.arr[11]; +wire [81:0] Q_24 = ITOP.iow0.arr[12]; +wire [81:0] Q_25 = ITOP.iow1.arr[12]; +wire [81:0] Q_26 = ITOP.iow0.arr[13]; +wire [81:0] Q_27 = ITOP.iow1.arr[13]; +wire [81:0] Q_28 = ITOP.iow0.arr[14]; +wire [81:0] Q_29 = ITOP.iow1.arr[14]; +wire [81:0] Q_30 = ITOP.iow0.arr[15]; +wire [81:0] Q_31 = ITOP.iow1.arr[15]; +wire [81:0] Q_32 = ITOP.iow0.arr[16]; +wire [81:0] Q_33 = ITOP.iow1.arr[16]; +wire [81:0] Q_34 = ITOP.iow0.arr[17]; +wire [81:0] Q_35 = ITOP.iow1.arr[17]; +wire [81:0] Q_36 = ITOP.iow0.arr[18]; +wire [81:0] Q_37 = ITOP.iow1.arr[18]; +wire [81:0] Q_38 = ITOP.iow0.arr[19]; +wire [81:0] Q_39 = ITOP.iow1.arr[19]; +wire [81:0] Q_40 = ITOP.iow0.arr[20]; +wire [81:0] Q_41 = ITOP.iow1.arr[20]; +wire [81:0] Q_42 = ITOP.iow0.arr[21]; +wire [81:0] Q_43 = ITOP.iow1.arr[21]; +wire [81:0] Q_44 = ITOP.iow0.arr[22]; +wire [81:0] Q_45 = ITOP.iow1.arr[22]; +wire [81:0] Q_46 = ITOP.iow0.arr[23]; +wire [81:0] Q_47 = ITOP.iow1.arr[23]; +wire [81:0] Q_48 = ITOP.iow0.arr[24]; +wire [81:0] Q_49 = ITOP.iow1.arr[24]; +wire [81:0] Q_50 = ITOP.iow0.arr[25]; +wire [81:0] Q_51 = ITOP.iow1.arr[25]; +wire [81:0] Q_52 = ITOP.iow0.arr[26]; +wire [81:0] Q_53 = ITOP.iow1.arr[26]; +wire [81:0] Q_54 = ITOP.iow0.arr[27]; +wire [81:0] Q_55 = ITOP.iow1.arr[27]; +wire [81:0] Q_56 = ITOP.iow0.arr[28]; +wire [81:0] Q_57 = ITOP.iow1.arr[28]; +wire [81:0] Q_58 = ITOP.iow0.arr[29]; +wire [81:0] Q_59 = ITOP.iow1.arr[29]; +wire [81:0] Q_60 = ITOP.iow0.arr[30]; +wire [81:0] Q_61 = ITOP.iow1.arr[30]; +wire [81:0] Q_62 = ITOP.iow0.arr[31]; +wire [81:0] Q_63 = ITOP.iow1.arr[31]; +wire [81:0] Q_64 = ITOP.iow0.arr[32]; +wire [81:0] Q_65 = ITOP.iow1.arr[32]; +wire [81:0] Q_66 = ITOP.iow0.arr[33]; +wire [81:0] Q_67 = ITOP.iow1.arr[33]; +wire [81:0] Q_68 = ITOP.iow0.arr[34]; +wire [81:0] Q_69 = ITOP.iow1.arr[34]; +wire [81:0] Q_70 = ITOP.iow0.arr[35]; +wire [81:0] Q_71 = ITOP.iow1.arr[35]; +wire [81:0] Q_72 = ITOP.iow0.arr[36]; +wire [81:0] Q_73 = ITOP.iow1.arr[36]; +wire [81:0] Q_74 = ITOP.iow0.arr[37]; +wire [81:0] Q_75 = ITOP.iow1.arr[37]; +wire [81:0] Q_76 = ITOP.iow0.arr[38]; +wire [81:0] Q_77 = ITOP.iow1.arr[38]; +wire [81:0] Q_78 = ITOP.iow0.arr[39]; +wire [81:0] Q_79 = ITOP.iow1.arr[39]; +wire [81:0] Q_80 = ITOP.iow0.arr[40]; +wire [81:0] Q_81 = ITOP.iow1.arr[40]; +wire [81:0] Q_82 = ITOP.iow0.arr[41]; +wire [81:0] Q_83 = ITOP.iow1.arr[41]; +wire [81:0] Q_84 = ITOP.iow0.arr[42]; +wire [81:0] Q_85 = ITOP.iow1.arr[42]; +wire [81:0] Q_86 = ITOP.iow0.arr[43]; +wire [81:0] Q_87 = ITOP.iow1.arr[43]; +wire [81:0] Q_88 = ITOP.iow0.arr[44]; +wire [81:0] Q_89 = ITOP.iow1.arr[44]; +wire [81:0] Q_90 = ITOP.iow0.arr[45]; +wire [81:0] Q_91 = ITOP.iow1.arr[45]; +wire [81:0] Q_92 = ITOP.iow0.arr[46]; +wire [81:0] Q_93 = ITOP.iow1.arr[46]; +wire [81:0] Q_94 = ITOP.iow0.arr[47]; +wire [81:0] Q_95 = ITOP.iow1.arr[47]; +wire [81:0] Q_96 = ITOP.iow0.arr[48]; +wire [81:0] Q_97 = ITOP.iow1.arr[48]; +wire [81:0] Q_98 = ITOP.iow0.arr[49]; +wire [81:0] Q_99 = ITOP.iow1.arr[49]; +wire [81:0] Q_100 = ITOP.iow0.arr[50]; +wire [81:0] Q_101 = ITOP.iow1.arr[50]; +wire [81:0] Q_102 = ITOP.iow0.arr[51]; +wire [81:0] Q_103 = ITOP.iow1.arr[51]; +wire [81:0] Q_104 = ITOP.iow0.arr[52]; +wire [81:0] Q_105 = ITOP.iow1.arr[52]; +wire [81:0] Q_106 = ITOP.iow0.arr[53]; +wire [81:0] Q_107 = ITOP.iow1.arr[53]; +wire [81:0] Q_108 = ITOP.iow0.arr[54]; +wire [81:0] Q_109 = ITOP.iow1.arr[54]; +wire [81:0] Q_110 = ITOP.iow0.arr[55]; +wire [81:0] Q_111 = ITOP.iow1.arr[55]; +wire [81:0] Q_112 = ITOP.iow0.arr[56]; +wire [81:0] Q_113 = ITOP.iow1.arr[56]; +wire [81:0] Q_114 = ITOP.iow0.arr[57]; +wire [81:0] Q_115 = ITOP.iow1.arr[57]; +wire [81:0] Q_116 = ITOP.iow0.arr[58]; +wire [81:0] Q_117 = ITOP.iow1.arr[58]; +wire [81:0] Q_118 = ITOP.iow0.arr[59]; +wire [81:0] Q_119 = ITOP.iow1.arr[59]; +wire [81:0] Q_120 = ITOP.iow0.arr[60]; +wire [81:0] Q_121 = ITOP.iow1.arr[60]; +wire [81:0] Q_122 = ITOP.iow0.arr[61]; +wire [81:0] Q_123 = ITOP.iow1.arr[61]; +wire [81:0] Q_124 = ITOP.iow0.arr[62]; +wire [81:0] Q_125 = ITOP.iow1.arr[62]; +wire [81:0] Q_126 = ITOP.iow0.arr[63]; +wire [81:0] Q_127 = ITOP.iow1.arr[63]; +wire [81:0] Q_128 = ITOP.iow0.arr[64]; +wire [81:0] Q_129 = ITOP.iow1.arr[64]; +wire [81:0] Q_130 = ITOP.iow0.arr[65]; +wire [81:0] Q_131 = ITOP.iow1.arr[65]; +wire [81:0] Q_132 = ITOP.iow0.arr[66]; +wire [81:0] Q_133 = ITOP.iow1.arr[66]; +wire [81:0] Q_134 = ITOP.iow0.arr[67]; +wire [81:0] Q_135 = ITOP.iow1.arr[67]; +wire [81:0] Q_136 = ITOP.iow0.arr[68]; +wire [81:0] Q_137 = ITOP.iow1.arr[68]; +wire [81:0] Q_138 = ITOP.iow0.arr[69]; +wire [81:0] Q_139 = ITOP.iow1.arr[69]; +wire [81:0] Q_140 = ITOP.iow0.arr[70]; +wire [81:0] Q_141 = ITOP.iow1.arr[70]; +wire [81:0] Q_142 = ITOP.iow0.arr[71]; +wire [81:0] Q_143 = ITOP.iow1.arr[71]; +wire [81:0] Q_144 = ITOP.iow0.arr[72]; +wire [81:0] Q_145 = ITOP.iow1.arr[72]; +wire [81:0] Q_146 = ITOP.iow0.arr[73]; +wire [81:0] Q_147 = ITOP.iow1.arr[73]; +wire [81:0] Q_148 = ITOP.iow0.arr[74]; +wire [81:0] Q_149 = ITOP.iow1.arr[74]; +wire [81:0] Q_150 = ITOP.iow0.arr[75]; +wire [81:0] Q_151 = ITOP.iow1.arr[75]; +wire [81:0] Q_152 = ITOP.iow0.arr[76]; +wire [81:0] Q_153 = ITOP.iow1.arr[76]; +wire [81:0] Q_154 = ITOP.iow0.arr[77]; +wire [81:0] Q_155 = ITOP.iow1.arr[77]; +wire [81:0] Q_156 = ITOP.iow0.arr[78]; +wire [81:0] Q_157 = ITOP.iow1.arr[78]; +wire [81:0] Q_158 = ITOP.iow0.arr[79]; +wire [81:0] Q_159 = ITOP.iow1.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [81:0] WD_FF; + reg [81:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [81:0] mem[159:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [81:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [81:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_160X82_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [81:0] WD; +input [7:0] RA, WA; +output [81:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [81:0] WDQ; + wire [81:0] WDBQ; + wire [81:0] WMNexp; + wire [81:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [81:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {82{1'b0}}; + assign SHFT = {82{1'b1}}; + reg [81:0] WDQ_pr; + wire [81:0] WDBQ_pr; + assign WMNexp = {82{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[81:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [81:0] dout; + wire [81:0] RD; + wire RD_rdnt; + wire [81:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [81:0] RDBYPASS = {82{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 160 --> ['1', '0', '0', '1', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] | + ADR[7] & ADR[5]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [81:0] force_x; +`ifndef SYNTHESIS + assign force_x = {82{1'bx}}; +`else + assign force_x = {82{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [81:0] rmuxd0, rmuxd1; + wire [81:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {82{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {82{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {82{RdClk0}} & ~dout0 ; + assign rmuxd1 = {82{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[81:0] <= (rmuxd0[81:0] | rmuxd1[81:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_160X82_GL_M2_D2_ram # (80, 82, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_160X82_GL_M2_D2_ram # (80, 82, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [81:0] data; + reg [81:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [81:0] mem_read_bank; +input [7:0] addr; +reg [81:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_160X82_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 82; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [143:0] val; + integer i; + begin + for (i=0; i<248; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [143:0] val; + integer i; + begin + val = {144{fill_bit}}; + for (i=0; i<248; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [143:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [144-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {144 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {144 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 144'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 144'bx; + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [143:0] wr[1:0]; + integer i; + begin + for (i=0; i<=143; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [143:0] Q_0 = ITOP.iow0.arr[0]; +wire [143:0] Q_1 = ITOP.iow1.arr[0]; +wire [143:0] Q_2 = ITOP.iow0.arr[1]; +wire [143:0] Q_3 = ITOP.iow1.arr[1]; +wire [143:0] Q_4 = ITOP.iow0.arr[2]; +wire [143:0] Q_5 = ITOP.iow1.arr[2]; +wire [143:0] Q_6 = ITOP.iow0.arr[3]; +wire [143:0] Q_7 = ITOP.iow1.arr[3]; +wire [143:0] Q_8 = ITOP.iow0.arr[4]; +wire [143:0] Q_9 = ITOP.iow1.arr[4]; +wire [143:0] Q_10 = ITOP.iow0.arr[5]; +wire [143:0] Q_11 = ITOP.iow1.arr[5]; +wire [143:0] Q_12 = ITOP.iow0.arr[6]; +wire [143:0] Q_13 = ITOP.iow1.arr[6]; +wire [143:0] Q_14 = ITOP.iow0.arr[7]; +wire [143:0] Q_15 = ITOP.iow1.arr[7]; +wire [143:0] Q_16 = ITOP.iow0.arr[8]; +wire [143:0] Q_17 = ITOP.iow1.arr[8]; +wire [143:0] Q_18 = ITOP.iow0.arr[9]; +wire [143:0] Q_19 = ITOP.iow1.arr[9]; +wire [143:0] Q_20 = ITOP.iow0.arr[10]; +wire [143:0] Q_21 = ITOP.iow1.arr[10]; +wire [143:0] Q_22 = ITOP.iow0.arr[11]; +wire [143:0] Q_23 = ITOP.iow1.arr[11]; +wire [143:0] Q_24 = ITOP.iow0.arr[12]; +wire [143:0] Q_25 = ITOP.iow1.arr[12]; +wire [143:0] Q_26 = ITOP.iow0.arr[13]; +wire [143:0] Q_27 = ITOP.iow1.arr[13]; +wire [143:0] Q_28 = ITOP.iow0.arr[14]; +wire [143:0] Q_29 = ITOP.iow1.arr[14]; +wire [143:0] Q_30 = ITOP.iow0.arr[15]; +wire [143:0] Q_31 = ITOP.iow1.arr[15]; +wire [143:0] Q_32 = ITOP.iow0.arr[16]; +wire [143:0] Q_33 = ITOP.iow1.arr[16]; +wire [143:0] Q_34 = ITOP.iow0.arr[17]; +wire [143:0] Q_35 = ITOP.iow1.arr[17]; +wire [143:0] Q_36 = ITOP.iow0.arr[18]; +wire [143:0] Q_37 = ITOP.iow1.arr[18]; +wire [143:0] Q_38 = ITOP.iow0.arr[19]; +wire [143:0] Q_39 = ITOP.iow1.arr[19]; +wire [143:0] Q_40 = ITOP.iow0.arr[20]; +wire [143:0] Q_41 = ITOP.iow1.arr[20]; +wire [143:0] Q_42 = ITOP.iow0.arr[21]; +wire [143:0] Q_43 = ITOP.iow1.arr[21]; +wire [143:0] Q_44 = ITOP.iow0.arr[22]; +wire [143:0] Q_45 = ITOP.iow1.arr[22]; +wire [143:0] Q_46 = ITOP.iow0.arr[23]; +wire [143:0] Q_47 = ITOP.iow1.arr[23]; +wire [143:0] Q_48 = ITOP.iow0.arr[24]; +wire [143:0] Q_49 = ITOP.iow1.arr[24]; +wire [143:0] Q_50 = ITOP.iow0.arr[25]; +wire [143:0] Q_51 = ITOP.iow1.arr[25]; +wire [143:0] Q_52 = ITOP.iow0.arr[26]; +wire [143:0] Q_53 = ITOP.iow1.arr[26]; +wire [143:0] Q_54 = ITOP.iow0.arr[27]; +wire [143:0] Q_55 = ITOP.iow1.arr[27]; +wire [143:0] Q_56 = ITOP.iow0.arr[28]; +wire [143:0] Q_57 = ITOP.iow1.arr[28]; +wire [143:0] Q_58 = ITOP.iow0.arr[29]; +wire [143:0] Q_59 = ITOP.iow1.arr[29]; +wire [143:0] Q_60 = ITOP.iow0.arr[30]; +wire [143:0] Q_61 = ITOP.iow1.arr[30]; +wire [143:0] Q_62 = ITOP.iow0.arr[31]; +wire [143:0] Q_63 = ITOP.iow1.arr[31]; +wire [143:0] Q_64 = ITOP.iow0.arr[32]; +wire [143:0] Q_65 = ITOP.iow1.arr[32]; +wire [143:0] Q_66 = ITOP.iow0.arr[33]; +wire [143:0] Q_67 = ITOP.iow1.arr[33]; +wire [143:0] Q_68 = ITOP.iow0.arr[34]; +wire [143:0] Q_69 = ITOP.iow1.arr[34]; +wire [143:0] Q_70 = ITOP.iow0.arr[35]; +wire [143:0] Q_71 = ITOP.iow1.arr[35]; +wire [143:0] Q_72 = ITOP.iow0.arr[36]; +wire [143:0] Q_73 = ITOP.iow1.arr[36]; +wire [143:0] Q_74 = ITOP.iow0.arr[37]; +wire [143:0] Q_75 = ITOP.iow1.arr[37]; +wire [143:0] Q_76 = ITOP.iow0.arr[38]; +wire [143:0] Q_77 = ITOP.iow1.arr[38]; +wire [143:0] Q_78 = ITOP.iow0.arr[39]; +wire [143:0] Q_79 = ITOP.iow1.arr[39]; +wire [143:0] Q_80 = ITOP.iow0.arr[40]; +wire [143:0] Q_81 = ITOP.iow1.arr[40]; +wire [143:0] Q_82 = ITOP.iow0.arr[41]; +wire [143:0] Q_83 = ITOP.iow1.arr[41]; +wire [143:0] Q_84 = ITOP.iow0.arr[42]; +wire [143:0] Q_85 = ITOP.iow1.arr[42]; +wire [143:0] Q_86 = ITOP.iow0.arr[43]; +wire [143:0] Q_87 = ITOP.iow1.arr[43]; +wire [143:0] Q_88 = ITOP.iow0.arr[44]; +wire [143:0] Q_89 = ITOP.iow1.arr[44]; +wire [143:0] Q_90 = ITOP.iow0.arr[45]; +wire [143:0] Q_91 = ITOP.iow1.arr[45]; +wire [143:0] Q_92 = ITOP.iow0.arr[46]; +wire [143:0] Q_93 = ITOP.iow1.arr[46]; +wire [143:0] Q_94 = ITOP.iow0.arr[47]; +wire [143:0] Q_95 = ITOP.iow1.arr[47]; +wire [143:0] Q_96 = ITOP.iow0.arr[48]; +wire [143:0] Q_97 = ITOP.iow1.arr[48]; +wire [143:0] Q_98 = ITOP.iow0.arr[49]; +wire [143:0] Q_99 = ITOP.iow1.arr[49]; +wire [143:0] Q_100 = ITOP.iow0.arr[50]; +wire [143:0] Q_101 = ITOP.iow1.arr[50]; +wire [143:0] Q_102 = ITOP.iow0.arr[51]; +wire [143:0] Q_103 = ITOP.iow1.arr[51]; +wire [143:0] Q_104 = ITOP.iow0.arr[52]; +wire [143:0] Q_105 = ITOP.iow1.arr[52]; +wire [143:0] Q_106 = ITOP.iow0.arr[53]; +wire [143:0] Q_107 = ITOP.iow1.arr[53]; +wire [143:0] Q_108 = ITOP.iow0.arr[54]; +wire [143:0] Q_109 = ITOP.iow1.arr[54]; +wire [143:0] Q_110 = ITOP.iow0.arr[55]; +wire [143:0] Q_111 = ITOP.iow1.arr[55]; +wire [143:0] Q_112 = ITOP.iow0.arr[56]; +wire [143:0] Q_113 = ITOP.iow1.arr[56]; +wire [143:0] Q_114 = ITOP.iow0.arr[57]; +wire [143:0] Q_115 = ITOP.iow1.arr[57]; +wire [143:0] Q_116 = ITOP.iow0.arr[58]; +wire [143:0] Q_117 = ITOP.iow1.arr[58]; +wire [143:0] Q_118 = ITOP.iow0.arr[59]; +wire [143:0] Q_119 = ITOP.iow1.arr[59]; +wire [143:0] Q_120 = ITOP.iow0.arr[60]; +wire [143:0] Q_121 = ITOP.iow1.arr[60]; +wire [143:0] Q_122 = ITOP.iow0.arr[61]; +wire [143:0] Q_123 = ITOP.iow1.arr[61]; +wire [143:0] Q_124 = ITOP.iow0.arr[62]; +wire [143:0] Q_125 = ITOP.iow1.arr[62]; +wire [143:0] Q_126 = ITOP.iow0.arr[63]; +wire [143:0] Q_127 = ITOP.iow1.arr[63]; +wire [143:0] Q_128 = ITOP.iow0.arr[64]; +wire [143:0] Q_129 = ITOP.iow1.arr[64]; +wire [143:0] Q_130 = ITOP.iow0.arr[65]; +wire [143:0] Q_131 = ITOP.iow1.arr[65]; +wire [143:0] Q_132 = ITOP.iow0.arr[66]; +wire [143:0] Q_133 = ITOP.iow1.arr[66]; +wire [143:0] Q_134 = ITOP.iow0.arr[67]; +wire [143:0] Q_135 = ITOP.iow1.arr[67]; +wire [143:0] Q_136 = ITOP.iow0.arr[68]; +wire [143:0] Q_137 = ITOP.iow1.arr[68]; +wire [143:0] Q_138 = ITOP.iow0.arr[69]; +wire [143:0] Q_139 = ITOP.iow1.arr[69]; +wire [143:0] Q_140 = ITOP.iow0.arr[70]; +wire [143:0] Q_141 = ITOP.iow1.arr[70]; +wire [143:0] Q_142 = ITOP.iow0.arr[71]; +wire [143:0] Q_143 = ITOP.iow1.arr[71]; +wire [143:0] Q_144 = ITOP.iow0.arr[72]; +wire [143:0] Q_145 = ITOP.iow1.arr[72]; +wire [143:0] Q_146 = ITOP.iow0.arr[73]; +wire [143:0] Q_147 = ITOP.iow1.arr[73]; +wire [143:0] Q_148 = ITOP.iow0.arr[74]; +wire [143:0] Q_149 = ITOP.iow1.arr[74]; +wire [143:0] Q_150 = ITOP.iow0.arr[75]; +wire [143:0] Q_151 = ITOP.iow1.arr[75]; +wire [143:0] Q_152 = ITOP.iow0.arr[76]; +wire [143:0] Q_153 = ITOP.iow1.arr[76]; +wire [143:0] Q_154 = ITOP.iow0.arr[77]; +wire [143:0] Q_155 = ITOP.iow1.arr[77]; +wire [143:0] Q_156 = ITOP.iow0.arr[78]; +wire [143:0] Q_157 = ITOP.iow1.arr[78]; +wire [143:0] Q_158 = ITOP.iow0.arr[79]; +wire [143:0] Q_159 = ITOP.iow1.arr[79]; +wire [143:0] Q_160 = ITOP.iow0.arr[80]; +wire [143:0] Q_161 = ITOP.iow1.arr[80]; +wire [143:0] Q_162 = ITOP.iow0.arr[81]; +wire [143:0] Q_163 = ITOP.iow1.arr[81]; +wire [143:0] Q_164 = ITOP.iow0.arr[82]; +wire [143:0] Q_165 = ITOP.iow1.arr[82]; +wire [143:0] Q_166 = ITOP.iow0.arr[83]; +wire [143:0] Q_167 = ITOP.iow1.arr[83]; +wire [143:0] Q_168 = ITOP.iow0.arr[84]; +wire [143:0] Q_169 = ITOP.iow1.arr[84]; +wire [143:0] Q_170 = ITOP.iow0.arr[85]; +wire [143:0] Q_171 = ITOP.iow1.arr[85]; +wire [143:0] Q_172 = ITOP.iow0.arr[86]; +wire [143:0] Q_173 = ITOP.iow1.arr[86]; +wire [143:0] Q_174 = ITOP.iow0.arr[87]; +wire [143:0] Q_175 = ITOP.iow1.arr[87]; +wire [143:0] Q_176 = ITOP.iow0.arr[88]; +wire [143:0] Q_177 = ITOP.iow1.arr[88]; +wire [143:0] Q_178 = ITOP.iow0.arr[89]; +wire [143:0] Q_179 = ITOP.iow1.arr[89]; +wire [143:0] Q_180 = ITOP.iow0.arr[90]; +wire [143:0] Q_181 = ITOP.iow1.arr[90]; +wire [143:0] Q_182 = ITOP.iow0.arr[91]; +wire [143:0] Q_183 = ITOP.iow1.arr[91]; +wire [143:0] Q_184 = ITOP.iow0.arr[92]; +wire [143:0] Q_185 = ITOP.iow1.arr[92]; +wire [143:0] Q_186 = ITOP.iow0.arr[93]; +wire [143:0] Q_187 = ITOP.iow1.arr[93]; +wire [143:0] Q_188 = ITOP.iow0.arr[94]; +wire [143:0] Q_189 = ITOP.iow1.arr[94]; +wire [143:0] Q_190 = ITOP.iow0.arr[95]; +wire [143:0] Q_191 = ITOP.iow1.arr[95]; +wire [143:0] Q_192 = ITOP.iow0.arr[96]; +wire [143:0] Q_193 = ITOP.iow1.arr[96]; +wire [143:0] Q_194 = ITOP.iow0.arr[97]; +wire [143:0] Q_195 = ITOP.iow1.arr[97]; +wire [143:0] Q_196 = ITOP.iow0.arr[98]; +wire [143:0] Q_197 = ITOP.iow1.arr[98]; +wire [143:0] Q_198 = ITOP.iow0.arr[99]; +wire [143:0] Q_199 = ITOP.iow1.arr[99]; +wire [143:0] Q_200 = ITOP.iow0.arr[100]; +wire [143:0] Q_201 = ITOP.iow1.arr[100]; +wire [143:0] Q_202 = ITOP.iow0.arr[101]; +wire [143:0] Q_203 = ITOP.iow1.arr[101]; +wire [143:0] Q_204 = ITOP.iow0.arr[102]; +wire [143:0] Q_205 = ITOP.iow1.arr[102]; +wire [143:0] Q_206 = ITOP.iow0.arr[103]; +wire [143:0] Q_207 = ITOP.iow1.arr[103]; +wire [143:0] Q_208 = ITOP.iow0.arr[104]; +wire [143:0] Q_209 = ITOP.iow1.arr[104]; +wire [143:0] Q_210 = ITOP.iow0.arr[105]; +wire [143:0] Q_211 = ITOP.iow1.arr[105]; +wire [143:0] Q_212 = ITOP.iow0.arr[106]; +wire [143:0] Q_213 = ITOP.iow1.arr[106]; +wire [143:0] Q_214 = ITOP.iow0.arr[107]; +wire [143:0] Q_215 = ITOP.iow1.arr[107]; +wire [143:0] Q_216 = ITOP.iow0.arr[108]; +wire [143:0] Q_217 = ITOP.iow1.arr[108]; +wire [143:0] Q_218 = ITOP.iow0.arr[109]; +wire [143:0] Q_219 = ITOP.iow1.arr[109]; +wire [143:0] Q_220 = ITOP.iow0.arr[110]; +wire [143:0] Q_221 = ITOP.iow1.arr[110]; +wire [143:0] Q_222 = ITOP.iow0.arr[111]; +wire [143:0] Q_223 = ITOP.iow1.arr[111]; +wire [143:0] Q_224 = ITOP.iow0.arr[112]; +wire [143:0] Q_225 = ITOP.iow1.arr[112]; +wire [143:0] Q_226 = ITOP.iow0.arr[113]; +wire [143:0] Q_227 = ITOP.iow1.arr[113]; +wire [143:0] Q_228 = ITOP.iow0.arr[114]; +wire [143:0] Q_229 = ITOP.iow1.arr[114]; +wire [143:0] Q_230 = ITOP.iow0.arr[115]; +wire [143:0] Q_231 = ITOP.iow1.arr[115]; +wire [143:0] Q_232 = ITOP.iow0.arr[116]; +wire [143:0] Q_233 = ITOP.iow1.arr[116]; +wire [143:0] Q_234 = ITOP.iow0.arr[117]; +wire [143:0] Q_235 = ITOP.iow1.arr[117]; +wire [143:0] Q_236 = ITOP.iow0.arr[118]; +wire [143:0] Q_237 = ITOP.iow1.arr[118]; +wire [143:0] Q_238 = ITOP.iow0.arr[119]; +wire [143:0] Q_239 = ITOP.iow1.arr[119]; +wire [143:0] Q_240 = ITOP.iow0.arr[120]; +wire [143:0] Q_241 = ITOP.iow1.arr[120]; +wire [143:0] Q_242 = ITOP.iow0.arr[121]; +wire [143:0] Q_243 = ITOP.iow1.arr[121]; +wire [143:0] Q_244 = ITOP.iow0.arr[122]; +wire [143:0] Q_245 = ITOP.iow1.arr[122]; +wire [143:0] Q_246 = ITOP.iow0.arr[123]; +wire [143:0] Q_247 = ITOP.iow1.arr[123]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [143:0] WD_FF; + reg [143:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [143:0] mem[247:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [143:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [143:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_248X144_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [143:0] WD; +input [7:0] RA, WA; +output [143:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [143:0] WDQ; + wire [143:0] WDBQ; + wire [143:0] WMNexp; + wire [143:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [143:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {144{1'b0}}; + assign SHFT = {144{1'b1}}; + reg [143:0] WDQ_pr; + wire [143:0] WDBQ_pr; + assign WMNexp = {144{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[143:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [143:0] dout; + wire [143:0] RD; + wire RD_rdnt; + wire [143:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [143:0] RDBYPASS = {144{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 248 --> ['1', '1', '1', '1', '0', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] & ADR[5] & ADR[4] & ADR[3]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [143:0] force_x; +`ifndef SYNTHESIS + assign force_x = {144{1'bx}}; +`else + assign force_x = {144{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [143:0] rmuxd0, rmuxd1; + wire [143:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {144{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {144{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {144{RdClk0}} & ~dout0 ; + assign rmuxd1 = {144{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[143:0] <= (rmuxd0[143:0] | rmuxd1[143:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_248X144_GL_M2_D2_ram # (124, 144, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_248X144_GL_M2_D2_ram # (124, 144, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [143:0] data; + reg [143:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [143:0] mem_read_bank; +input [7:0] addr; +reg [143:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_248X144_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 124; +parameter bits = 144; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [143:0] val; + integer i; + begin + for (i=0; i<248; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [143:0] val; + integer i; + begin + val = {144{fill_bit}}; + for (i=0; i<248; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [143:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [144-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {144 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {144 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 144'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 144'bx; + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [143:0] wr[1:0]; + integer i; + begin + for (i=0; i<=143; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [143:0] Q_0 = ITOP.iow0.arr[0]; +wire [143:0] Q_1 = ITOP.iow1.arr[0]; +wire [143:0] Q_2 = ITOP.iow0.arr[1]; +wire [143:0] Q_3 = ITOP.iow1.arr[1]; +wire [143:0] Q_4 = ITOP.iow0.arr[2]; +wire [143:0] Q_5 = ITOP.iow1.arr[2]; +wire [143:0] Q_6 = ITOP.iow0.arr[3]; +wire [143:0] Q_7 = ITOP.iow1.arr[3]; +wire [143:0] Q_8 = ITOP.iow0.arr[4]; +wire [143:0] Q_9 = ITOP.iow1.arr[4]; +wire [143:0] Q_10 = ITOP.iow0.arr[5]; +wire [143:0] Q_11 = ITOP.iow1.arr[5]; +wire [143:0] Q_12 = ITOP.iow0.arr[6]; +wire [143:0] Q_13 = ITOP.iow1.arr[6]; +wire [143:0] Q_14 = ITOP.iow0.arr[7]; +wire [143:0] Q_15 = ITOP.iow1.arr[7]; +wire [143:0] Q_16 = ITOP.iow0.arr[8]; +wire [143:0] Q_17 = ITOP.iow1.arr[8]; +wire [143:0] Q_18 = ITOP.iow0.arr[9]; +wire [143:0] Q_19 = ITOP.iow1.arr[9]; +wire [143:0] Q_20 = ITOP.iow0.arr[10]; +wire [143:0] Q_21 = ITOP.iow1.arr[10]; +wire [143:0] Q_22 = ITOP.iow0.arr[11]; +wire [143:0] Q_23 = ITOP.iow1.arr[11]; +wire [143:0] Q_24 = ITOP.iow0.arr[12]; +wire [143:0] Q_25 = ITOP.iow1.arr[12]; +wire [143:0] Q_26 = ITOP.iow0.arr[13]; +wire [143:0] Q_27 = ITOP.iow1.arr[13]; +wire [143:0] Q_28 = ITOP.iow0.arr[14]; +wire [143:0] Q_29 = ITOP.iow1.arr[14]; +wire [143:0] Q_30 = ITOP.iow0.arr[15]; +wire [143:0] Q_31 = ITOP.iow1.arr[15]; +wire [143:0] Q_32 = ITOP.iow0.arr[16]; +wire [143:0] Q_33 = ITOP.iow1.arr[16]; +wire [143:0] Q_34 = ITOP.iow0.arr[17]; +wire [143:0] Q_35 = ITOP.iow1.arr[17]; +wire [143:0] Q_36 = ITOP.iow0.arr[18]; +wire [143:0] Q_37 = ITOP.iow1.arr[18]; +wire [143:0] Q_38 = ITOP.iow0.arr[19]; +wire [143:0] Q_39 = ITOP.iow1.arr[19]; +wire [143:0] Q_40 = ITOP.iow0.arr[20]; +wire [143:0] Q_41 = ITOP.iow1.arr[20]; +wire [143:0] Q_42 = ITOP.iow0.arr[21]; +wire [143:0] Q_43 = ITOP.iow1.arr[21]; +wire [143:0] Q_44 = ITOP.iow0.arr[22]; +wire [143:0] Q_45 = ITOP.iow1.arr[22]; +wire [143:0] Q_46 = ITOP.iow0.arr[23]; +wire [143:0] Q_47 = ITOP.iow1.arr[23]; +wire [143:0] Q_48 = ITOP.iow0.arr[24]; +wire [143:0] Q_49 = ITOP.iow1.arr[24]; +wire [143:0] Q_50 = ITOP.iow0.arr[25]; +wire [143:0] Q_51 = ITOP.iow1.arr[25]; +wire [143:0] Q_52 = ITOP.iow0.arr[26]; +wire [143:0] Q_53 = ITOP.iow1.arr[26]; +wire [143:0] Q_54 = ITOP.iow0.arr[27]; +wire [143:0] Q_55 = ITOP.iow1.arr[27]; +wire [143:0] Q_56 = ITOP.iow0.arr[28]; +wire [143:0] Q_57 = ITOP.iow1.arr[28]; +wire [143:0] Q_58 = ITOP.iow0.arr[29]; +wire [143:0] Q_59 = ITOP.iow1.arr[29]; +wire [143:0] Q_60 = ITOP.iow0.arr[30]; +wire [143:0] Q_61 = ITOP.iow1.arr[30]; +wire [143:0] Q_62 = ITOP.iow0.arr[31]; +wire [143:0] Q_63 = ITOP.iow1.arr[31]; +wire [143:0] Q_64 = ITOP.iow0.arr[32]; +wire [143:0] Q_65 = ITOP.iow1.arr[32]; +wire [143:0] Q_66 = ITOP.iow0.arr[33]; +wire [143:0] Q_67 = ITOP.iow1.arr[33]; +wire [143:0] Q_68 = ITOP.iow0.arr[34]; +wire [143:0] Q_69 = ITOP.iow1.arr[34]; +wire [143:0] Q_70 = ITOP.iow0.arr[35]; +wire [143:0] Q_71 = ITOP.iow1.arr[35]; +wire [143:0] Q_72 = ITOP.iow0.arr[36]; +wire [143:0] Q_73 = ITOP.iow1.arr[36]; +wire [143:0] Q_74 = ITOP.iow0.arr[37]; +wire [143:0] Q_75 = ITOP.iow1.arr[37]; +wire [143:0] Q_76 = ITOP.iow0.arr[38]; +wire [143:0] Q_77 = ITOP.iow1.arr[38]; +wire [143:0] Q_78 = ITOP.iow0.arr[39]; +wire [143:0] Q_79 = ITOP.iow1.arr[39]; +wire [143:0] Q_80 = ITOP.iow0.arr[40]; +wire [143:0] Q_81 = ITOP.iow1.arr[40]; +wire [143:0] Q_82 = ITOP.iow0.arr[41]; +wire [143:0] Q_83 = ITOP.iow1.arr[41]; +wire [143:0] Q_84 = ITOP.iow0.arr[42]; +wire [143:0] Q_85 = ITOP.iow1.arr[42]; +wire [143:0] Q_86 = ITOP.iow0.arr[43]; +wire [143:0] Q_87 = ITOP.iow1.arr[43]; +wire [143:0] Q_88 = ITOP.iow0.arr[44]; +wire [143:0] Q_89 = ITOP.iow1.arr[44]; +wire [143:0] Q_90 = ITOP.iow0.arr[45]; +wire [143:0] Q_91 = ITOP.iow1.arr[45]; +wire [143:0] Q_92 = ITOP.iow0.arr[46]; +wire [143:0] Q_93 = ITOP.iow1.arr[46]; +wire [143:0] Q_94 = ITOP.iow0.arr[47]; +wire [143:0] Q_95 = ITOP.iow1.arr[47]; +wire [143:0] Q_96 = ITOP.iow0.arr[48]; +wire [143:0] Q_97 = ITOP.iow1.arr[48]; +wire [143:0] Q_98 = ITOP.iow0.arr[49]; +wire [143:0] Q_99 = ITOP.iow1.arr[49]; +wire [143:0] Q_100 = ITOP.iow0.arr[50]; +wire [143:0] Q_101 = ITOP.iow1.arr[50]; +wire [143:0] Q_102 = ITOP.iow0.arr[51]; +wire [143:0] Q_103 = ITOP.iow1.arr[51]; +wire [143:0] Q_104 = ITOP.iow0.arr[52]; +wire [143:0] Q_105 = ITOP.iow1.arr[52]; +wire [143:0] Q_106 = ITOP.iow0.arr[53]; +wire [143:0] Q_107 = ITOP.iow1.arr[53]; +wire [143:0] Q_108 = ITOP.iow0.arr[54]; +wire [143:0] Q_109 = ITOP.iow1.arr[54]; +wire [143:0] Q_110 = ITOP.iow0.arr[55]; +wire [143:0] Q_111 = ITOP.iow1.arr[55]; +wire [143:0] Q_112 = ITOP.iow0.arr[56]; +wire [143:0] Q_113 = ITOP.iow1.arr[56]; +wire [143:0] Q_114 = ITOP.iow0.arr[57]; +wire [143:0] Q_115 = ITOP.iow1.arr[57]; +wire [143:0] Q_116 = ITOP.iow0.arr[58]; +wire [143:0] Q_117 = ITOP.iow1.arr[58]; +wire [143:0] Q_118 = ITOP.iow0.arr[59]; +wire [143:0] Q_119 = ITOP.iow1.arr[59]; +wire [143:0] Q_120 = ITOP.iow0.arr[60]; +wire [143:0] Q_121 = ITOP.iow1.arr[60]; +wire [143:0] Q_122 = ITOP.iow0.arr[61]; +wire [143:0] Q_123 = ITOP.iow1.arr[61]; +wire [143:0] Q_124 = ITOP.iow0.arr[62]; +wire [143:0] Q_125 = ITOP.iow1.arr[62]; +wire [143:0] Q_126 = ITOP.iow0.arr[63]; +wire [143:0] Q_127 = ITOP.iow1.arr[63]; +wire [143:0] Q_128 = ITOP.iow0.arr[64]; +wire [143:0] Q_129 = ITOP.iow1.arr[64]; +wire [143:0] Q_130 = ITOP.iow0.arr[65]; +wire [143:0] Q_131 = ITOP.iow1.arr[65]; +wire [143:0] Q_132 = ITOP.iow0.arr[66]; +wire [143:0] Q_133 = ITOP.iow1.arr[66]; +wire [143:0] Q_134 = ITOP.iow0.arr[67]; +wire [143:0] Q_135 = ITOP.iow1.arr[67]; +wire [143:0] Q_136 = ITOP.iow0.arr[68]; +wire [143:0] Q_137 = ITOP.iow1.arr[68]; +wire [143:0] Q_138 = ITOP.iow0.arr[69]; +wire [143:0] Q_139 = ITOP.iow1.arr[69]; +wire [143:0] Q_140 = ITOP.iow0.arr[70]; +wire [143:0] Q_141 = ITOP.iow1.arr[70]; +wire [143:0] Q_142 = ITOP.iow0.arr[71]; +wire [143:0] Q_143 = ITOP.iow1.arr[71]; +wire [143:0] Q_144 = ITOP.iow0.arr[72]; +wire [143:0] Q_145 = ITOP.iow1.arr[72]; +wire [143:0] Q_146 = ITOP.iow0.arr[73]; +wire [143:0] Q_147 = ITOP.iow1.arr[73]; +wire [143:0] Q_148 = ITOP.iow0.arr[74]; +wire [143:0] Q_149 = ITOP.iow1.arr[74]; +wire [143:0] Q_150 = ITOP.iow0.arr[75]; +wire [143:0] Q_151 = ITOP.iow1.arr[75]; +wire [143:0] Q_152 = ITOP.iow0.arr[76]; +wire [143:0] Q_153 = ITOP.iow1.arr[76]; +wire [143:0] Q_154 = ITOP.iow0.arr[77]; +wire [143:0] Q_155 = ITOP.iow1.arr[77]; +wire [143:0] Q_156 = ITOP.iow0.arr[78]; +wire [143:0] Q_157 = ITOP.iow1.arr[78]; +wire [143:0] Q_158 = ITOP.iow0.arr[79]; +wire [143:0] Q_159 = ITOP.iow1.arr[79]; +wire [143:0] Q_160 = ITOP.iow0.arr[80]; +wire [143:0] Q_161 = ITOP.iow1.arr[80]; +wire [143:0] Q_162 = ITOP.iow0.arr[81]; +wire [143:0] Q_163 = ITOP.iow1.arr[81]; +wire [143:0] Q_164 = ITOP.iow0.arr[82]; +wire [143:0] Q_165 = ITOP.iow1.arr[82]; +wire [143:0] Q_166 = ITOP.iow0.arr[83]; +wire [143:0] Q_167 = ITOP.iow1.arr[83]; +wire [143:0] Q_168 = ITOP.iow0.arr[84]; +wire [143:0] Q_169 = ITOP.iow1.arr[84]; +wire [143:0] Q_170 = ITOP.iow0.arr[85]; +wire [143:0] Q_171 = ITOP.iow1.arr[85]; +wire [143:0] Q_172 = ITOP.iow0.arr[86]; +wire [143:0] Q_173 = ITOP.iow1.arr[86]; +wire [143:0] Q_174 = ITOP.iow0.arr[87]; +wire [143:0] Q_175 = ITOP.iow1.arr[87]; +wire [143:0] Q_176 = ITOP.iow0.arr[88]; +wire [143:0] Q_177 = ITOP.iow1.arr[88]; +wire [143:0] Q_178 = ITOP.iow0.arr[89]; +wire [143:0] Q_179 = ITOP.iow1.arr[89]; +wire [143:0] Q_180 = ITOP.iow0.arr[90]; +wire [143:0] Q_181 = ITOP.iow1.arr[90]; +wire [143:0] Q_182 = ITOP.iow0.arr[91]; +wire [143:0] Q_183 = ITOP.iow1.arr[91]; +wire [143:0] Q_184 = ITOP.iow0.arr[92]; +wire [143:0] Q_185 = ITOP.iow1.arr[92]; +wire [143:0] Q_186 = ITOP.iow0.arr[93]; +wire [143:0] Q_187 = ITOP.iow1.arr[93]; +wire [143:0] Q_188 = ITOP.iow0.arr[94]; +wire [143:0] Q_189 = ITOP.iow1.arr[94]; +wire [143:0] Q_190 = ITOP.iow0.arr[95]; +wire [143:0] Q_191 = ITOP.iow1.arr[95]; +wire [143:0] Q_192 = ITOP.iow0.arr[96]; +wire [143:0] Q_193 = ITOP.iow1.arr[96]; +wire [143:0] Q_194 = ITOP.iow0.arr[97]; +wire [143:0] Q_195 = ITOP.iow1.arr[97]; +wire [143:0] Q_196 = ITOP.iow0.arr[98]; +wire [143:0] Q_197 = ITOP.iow1.arr[98]; +wire [143:0] Q_198 = ITOP.iow0.arr[99]; +wire [143:0] Q_199 = ITOP.iow1.arr[99]; +wire [143:0] Q_200 = ITOP.iow0.arr[100]; +wire [143:0] Q_201 = ITOP.iow1.arr[100]; +wire [143:0] Q_202 = ITOP.iow0.arr[101]; +wire [143:0] Q_203 = ITOP.iow1.arr[101]; +wire [143:0] Q_204 = ITOP.iow0.arr[102]; +wire [143:0] Q_205 = ITOP.iow1.arr[102]; +wire [143:0] Q_206 = ITOP.iow0.arr[103]; +wire [143:0] Q_207 = ITOP.iow1.arr[103]; +wire [143:0] Q_208 = ITOP.iow0.arr[104]; +wire [143:0] Q_209 = ITOP.iow1.arr[104]; +wire [143:0] Q_210 = ITOP.iow0.arr[105]; +wire [143:0] Q_211 = ITOP.iow1.arr[105]; +wire [143:0] Q_212 = ITOP.iow0.arr[106]; +wire [143:0] Q_213 = ITOP.iow1.arr[106]; +wire [143:0] Q_214 = ITOP.iow0.arr[107]; +wire [143:0] Q_215 = ITOP.iow1.arr[107]; +wire [143:0] Q_216 = ITOP.iow0.arr[108]; +wire [143:0] Q_217 = ITOP.iow1.arr[108]; +wire [143:0] Q_218 = ITOP.iow0.arr[109]; +wire [143:0] Q_219 = ITOP.iow1.arr[109]; +wire [143:0] Q_220 = ITOP.iow0.arr[110]; +wire [143:0] Q_221 = ITOP.iow1.arr[110]; +wire [143:0] Q_222 = ITOP.iow0.arr[111]; +wire [143:0] Q_223 = ITOP.iow1.arr[111]; +wire [143:0] Q_224 = ITOP.iow0.arr[112]; +wire [143:0] Q_225 = ITOP.iow1.arr[112]; +wire [143:0] Q_226 = ITOP.iow0.arr[113]; +wire [143:0] Q_227 = ITOP.iow1.arr[113]; +wire [143:0] Q_228 = ITOP.iow0.arr[114]; +wire [143:0] Q_229 = ITOP.iow1.arr[114]; +wire [143:0] Q_230 = ITOP.iow0.arr[115]; +wire [143:0] Q_231 = ITOP.iow1.arr[115]; +wire [143:0] Q_232 = ITOP.iow0.arr[116]; +wire [143:0] Q_233 = ITOP.iow1.arr[116]; +wire [143:0] Q_234 = ITOP.iow0.arr[117]; +wire [143:0] Q_235 = ITOP.iow1.arr[117]; +wire [143:0] Q_236 = ITOP.iow0.arr[118]; +wire [143:0] Q_237 = ITOP.iow1.arr[118]; +wire [143:0] Q_238 = ITOP.iow0.arr[119]; +wire [143:0] Q_239 = ITOP.iow1.arr[119]; +wire [143:0] Q_240 = ITOP.iow0.arr[120]; +wire [143:0] Q_241 = ITOP.iow1.arr[120]; +wire [143:0] Q_242 = ITOP.iow0.arr[121]; +wire [143:0] Q_243 = ITOP.iow1.arr[121]; +wire [143:0] Q_244 = ITOP.iow0.arr[122]; +wire [143:0] Q_245 = ITOP.iow1.arr[122]; +wire [143:0] Q_246 = ITOP.iow0.arr[123]; +wire [143:0] Q_247 = ITOP.iow1.arr[123]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [143:0] WD_FF; + reg [143:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [143:0] mem[247:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [143:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [143:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_248X144_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [143:0] WD; +input [7:0] RA, WA; +output [143:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [143:0] WDQ; + wire [143:0] WDBQ; + wire [143:0] WMNexp; + wire [143:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [143:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {144{1'b0}}; + assign SHFT = {144{1'b1}}; + reg [143:0] WDQ_pr; + wire [143:0] WDBQ_pr; + assign WMNexp = {144{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[143:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [143:0] dout; + wire [143:0] RD; + wire RD_rdnt; + wire [143:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [143:0] RDBYPASS = {144{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 248 --> ['1', '1', '1', '1', '0', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] & ADR[5] & ADR[4] & ADR[3]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [143:0] force_x; +`ifndef SYNTHESIS + assign force_x = {144{1'bx}}; +`else + assign force_x = {144{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [143:0] rmuxd0, rmuxd1; + wire [143:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {144{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {144{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {144{RdClk0}} & ~dout0 ; + assign rmuxd1 = {144{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[143:0] <= (rmuxd0[143:0] | rmuxd1[143:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_248X144_GL_M2_D2_ram # (124, 144, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_248X144_GL_M2_D2_ram # (124, 144, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [143:0] data; + reg [143:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [143:0] mem_read_bank; +input [7:0] addr; +reg [143:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_248X144_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 124; +parameter bits = 144; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [81:0] val; + integer i; + begin + for (i=0; i<248; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [81:0] val; + integer i; + begin + val = {82{fill_bit}}; + for (i=0; i<248; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [81:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [82-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {82 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{18{1'b1}}) } `endif ; + else raminit_fullval = {82 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [163:0] mem_phys_read_padr; +input [6:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [163:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [163:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 82'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 82'bx; + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [163:0] data; + reg [81:0] wr[1:0]; + integer i; + begin + for (i=0; i<=81; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [163:0] mon_bit_w; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [163:0] mon_bit_r; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [163:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [81:0] Q_0 = ITOP.iow0.arr[0]; +wire [81:0] Q_1 = ITOP.iow1.arr[0]; +wire [81:0] Q_2 = ITOP.iow0.arr[1]; +wire [81:0] Q_3 = ITOP.iow1.arr[1]; +wire [81:0] Q_4 = ITOP.iow0.arr[2]; +wire [81:0] Q_5 = ITOP.iow1.arr[2]; +wire [81:0] Q_6 = ITOP.iow0.arr[3]; +wire [81:0] Q_7 = ITOP.iow1.arr[3]; +wire [81:0] Q_8 = ITOP.iow0.arr[4]; +wire [81:0] Q_9 = ITOP.iow1.arr[4]; +wire [81:0] Q_10 = ITOP.iow0.arr[5]; +wire [81:0] Q_11 = ITOP.iow1.arr[5]; +wire [81:0] Q_12 = ITOP.iow0.arr[6]; +wire [81:0] Q_13 = ITOP.iow1.arr[6]; +wire [81:0] Q_14 = ITOP.iow0.arr[7]; +wire [81:0] Q_15 = ITOP.iow1.arr[7]; +wire [81:0] Q_16 = ITOP.iow0.arr[8]; +wire [81:0] Q_17 = ITOP.iow1.arr[8]; +wire [81:0] Q_18 = ITOP.iow0.arr[9]; +wire [81:0] Q_19 = ITOP.iow1.arr[9]; +wire [81:0] Q_20 = ITOP.iow0.arr[10]; +wire [81:0] Q_21 = ITOP.iow1.arr[10]; +wire [81:0] Q_22 = ITOP.iow0.arr[11]; +wire [81:0] Q_23 = ITOP.iow1.arr[11]; +wire [81:0] Q_24 = ITOP.iow0.arr[12]; +wire [81:0] Q_25 = ITOP.iow1.arr[12]; +wire [81:0] Q_26 = ITOP.iow0.arr[13]; +wire [81:0] Q_27 = ITOP.iow1.arr[13]; +wire [81:0] Q_28 = ITOP.iow0.arr[14]; +wire [81:0] Q_29 = ITOP.iow1.arr[14]; +wire [81:0] Q_30 = ITOP.iow0.arr[15]; +wire [81:0] Q_31 = ITOP.iow1.arr[15]; +wire [81:0] Q_32 = ITOP.iow0.arr[16]; +wire [81:0] Q_33 = ITOP.iow1.arr[16]; +wire [81:0] Q_34 = ITOP.iow0.arr[17]; +wire [81:0] Q_35 = ITOP.iow1.arr[17]; +wire [81:0] Q_36 = ITOP.iow0.arr[18]; +wire [81:0] Q_37 = ITOP.iow1.arr[18]; +wire [81:0] Q_38 = ITOP.iow0.arr[19]; +wire [81:0] Q_39 = ITOP.iow1.arr[19]; +wire [81:0] Q_40 = ITOP.iow0.arr[20]; +wire [81:0] Q_41 = ITOP.iow1.arr[20]; +wire [81:0] Q_42 = ITOP.iow0.arr[21]; +wire [81:0] Q_43 = ITOP.iow1.arr[21]; +wire [81:0] Q_44 = ITOP.iow0.arr[22]; +wire [81:0] Q_45 = ITOP.iow1.arr[22]; +wire [81:0] Q_46 = ITOP.iow0.arr[23]; +wire [81:0] Q_47 = ITOP.iow1.arr[23]; +wire [81:0] Q_48 = ITOP.iow0.arr[24]; +wire [81:0] Q_49 = ITOP.iow1.arr[24]; +wire [81:0] Q_50 = ITOP.iow0.arr[25]; +wire [81:0] Q_51 = ITOP.iow1.arr[25]; +wire [81:0] Q_52 = ITOP.iow0.arr[26]; +wire [81:0] Q_53 = ITOP.iow1.arr[26]; +wire [81:0] Q_54 = ITOP.iow0.arr[27]; +wire [81:0] Q_55 = ITOP.iow1.arr[27]; +wire [81:0] Q_56 = ITOP.iow0.arr[28]; +wire [81:0] Q_57 = ITOP.iow1.arr[28]; +wire [81:0] Q_58 = ITOP.iow0.arr[29]; +wire [81:0] Q_59 = ITOP.iow1.arr[29]; +wire [81:0] Q_60 = ITOP.iow0.arr[30]; +wire [81:0] Q_61 = ITOP.iow1.arr[30]; +wire [81:0] Q_62 = ITOP.iow0.arr[31]; +wire [81:0] Q_63 = ITOP.iow1.arr[31]; +wire [81:0] Q_64 = ITOP.iow0.arr[32]; +wire [81:0] Q_65 = ITOP.iow1.arr[32]; +wire [81:0] Q_66 = ITOP.iow0.arr[33]; +wire [81:0] Q_67 = ITOP.iow1.arr[33]; +wire [81:0] Q_68 = ITOP.iow0.arr[34]; +wire [81:0] Q_69 = ITOP.iow1.arr[34]; +wire [81:0] Q_70 = ITOP.iow0.arr[35]; +wire [81:0] Q_71 = ITOP.iow1.arr[35]; +wire [81:0] Q_72 = ITOP.iow0.arr[36]; +wire [81:0] Q_73 = ITOP.iow1.arr[36]; +wire [81:0] Q_74 = ITOP.iow0.arr[37]; +wire [81:0] Q_75 = ITOP.iow1.arr[37]; +wire [81:0] Q_76 = ITOP.iow0.arr[38]; +wire [81:0] Q_77 = ITOP.iow1.arr[38]; +wire [81:0] Q_78 = ITOP.iow0.arr[39]; +wire [81:0] Q_79 = ITOP.iow1.arr[39]; +wire [81:0] Q_80 = ITOP.iow0.arr[40]; +wire [81:0] Q_81 = ITOP.iow1.arr[40]; +wire [81:0] Q_82 = ITOP.iow0.arr[41]; +wire [81:0] Q_83 = ITOP.iow1.arr[41]; +wire [81:0] Q_84 = ITOP.iow0.arr[42]; +wire [81:0] Q_85 = ITOP.iow1.arr[42]; +wire [81:0] Q_86 = ITOP.iow0.arr[43]; +wire [81:0] Q_87 = ITOP.iow1.arr[43]; +wire [81:0] Q_88 = ITOP.iow0.arr[44]; +wire [81:0] Q_89 = ITOP.iow1.arr[44]; +wire [81:0] Q_90 = ITOP.iow0.arr[45]; +wire [81:0] Q_91 = ITOP.iow1.arr[45]; +wire [81:0] Q_92 = ITOP.iow0.arr[46]; +wire [81:0] Q_93 = ITOP.iow1.arr[46]; +wire [81:0] Q_94 = ITOP.iow0.arr[47]; +wire [81:0] Q_95 = ITOP.iow1.arr[47]; +wire [81:0] Q_96 = ITOP.iow0.arr[48]; +wire [81:0] Q_97 = ITOP.iow1.arr[48]; +wire [81:0] Q_98 = ITOP.iow0.arr[49]; +wire [81:0] Q_99 = ITOP.iow1.arr[49]; +wire [81:0] Q_100 = ITOP.iow0.arr[50]; +wire [81:0] Q_101 = ITOP.iow1.arr[50]; +wire [81:0] Q_102 = ITOP.iow0.arr[51]; +wire [81:0] Q_103 = ITOP.iow1.arr[51]; +wire [81:0] Q_104 = ITOP.iow0.arr[52]; +wire [81:0] Q_105 = ITOP.iow1.arr[52]; +wire [81:0] Q_106 = ITOP.iow0.arr[53]; +wire [81:0] Q_107 = ITOP.iow1.arr[53]; +wire [81:0] Q_108 = ITOP.iow0.arr[54]; +wire [81:0] Q_109 = ITOP.iow1.arr[54]; +wire [81:0] Q_110 = ITOP.iow0.arr[55]; +wire [81:0] Q_111 = ITOP.iow1.arr[55]; +wire [81:0] Q_112 = ITOP.iow0.arr[56]; +wire [81:0] Q_113 = ITOP.iow1.arr[56]; +wire [81:0] Q_114 = ITOP.iow0.arr[57]; +wire [81:0] Q_115 = ITOP.iow1.arr[57]; +wire [81:0] Q_116 = ITOP.iow0.arr[58]; +wire [81:0] Q_117 = ITOP.iow1.arr[58]; +wire [81:0] Q_118 = ITOP.iow0.arr[59]; +wire [81:0] Q_119 = ITOP.iow1.arr[59]; +wire [81:0] Q_120 = ITOP.iow0.arr[60]; +wire [81:0] Q_121 = ITOP.iow1.arr[60]; +wire [81:0] Q_122 = ITOP.iow0.arr[61]; +wire [81:0] Q_123 = ITOP.iow1.arr[61]; +wire [81:0] Q_124 = ITOP.iow0.arr[62]; +wire [81:0] Q_125 = ITOP.iow1.arr[62]; +wire [81:0] Q_126 = ITOP.iow0.arr[63]; +wire [81:0] Q_127 = ITOP.iow1.arr[63]; +wire [81:0] Q_128 = ITOP.iow0.arr[64]; +wire [81:0] Q_129 = ITOP.iow1.arr[64]; +wire [81:0] Q_130 = ITOP.iow0.arr[65]; +wire [81:0] Q_131 = ITOP.iow1.arr[65]; +wire [81:0] Q_132 = ITOP.iow0.arr[66]; +wire [81:0] Q_133 = ITOP.iow1.arr[66]; +wire [81:0] Q_134 = ITOP.iow0.arr[67]; +wire [81:0] Q_135 = ITOP.iow1.arr[67]; +wire [81:0] Q_136 = ITOP.iow0.arr[68]; +wire [81:0] Q_137 = ITOP.iow1.arr[68]; +wire [81:0] Q_138 = ITOP.iow0.arr[69]; +wire [81:0] Q_139 = ITOP.iow1.arr[69]; +wire [81:0] Q_140 = ITOP.iow0.arr[70]; +wire [81:0] Q_141 = ITOP.iow1.arr[70]; +wire [81:0] Q_142 = ITOP.iow0.arr[71]; +wire [81:0] Q_143 = ITOP.iow1.arr[71]; +wire [81:0] Q_144 = ITOP.iow0.arr[72]; +wire [81:0] Q_145 = ITOP.iow1.arr[72]; +wire [81:0] Q_146 = ITOP.iow0.arr[73]; +wire [81:0] Q_147 = ITOP.iow1.arr[73]; +wire [81:0] Q_148 = ITOP.iow0.arr[74]; +wire [81:0] Q_149 = ITOP.iow1.arr[74]; +wire [81:0] Q_150 = ITOP.iow0.arr[75]; +wire [81:0] Q_151 = ITOP.iow1.arr[75]; +wire [81:0] Q_152 = ITOP.iow0.arr[76]; +wire [81:0] Q_153 = ITOP.iow1.arr[76]; +wire [81:0] Q_154 = ITOP.iow0.arr[77]; +wire [81:0] Q_155 = ITOP.iow1.arr[77]; +wire [81:0] Q_156 = ITOP.iow0.arr[78]; +wire [81:0] Q_157 = ITOP.iow1.arr[78]; +wire [81:0] Q_158 = ITOP.iow0.arr[79]; +wire [81:0] Q_159 = ITOP.iow1.arr[79]; +wire [81:0] Q_160 = ITOP.iow0.arr[80]; +wire [81:0] Q_161 = ITOP.iow1.arr[80]; +wire [81:0] Q_162 = ITOP.iow0.arr[81]; +wire [81:0] Q_163 = ITOP.iow1.arr[81]; +wire [81:0] Q_164 = ITOP.iow0.arr[82]; +wire [81:0] Q_165 = ITOP.iow1.arr[82]; +wire [81:0] Q_166 = ITOP.iow0.arr[83]; +wire [81:0] Q_167 = ITOP.iow1.arr[83]; +wire [81:0] Q_168 = ITOP.iow0.arr[84]; +wire [81:0] Q_169 = ITOP.iow1.arr[84]; +wire [81:0] Q_170 = ITOP.iow0.arr[85]; +wire [81:0] Q_171 = ITOP.iow1.arr[85]; +wire [81:0] Q_172 = ITOP.iow0.arr[86]; +wire [81:0] Q_173 = ITOP.iow1.arr[86]; +wire [81:0] Q_174 = ITOP.iow0.arr[87]; +wire [81:0] Q_175 = ITOP.iow1.arr[87]; +wire [81:0] Q_176 = ITOP.iow0.arr[88]; +wire [81:0] Q_177 = ITOP.iow1.arr[88]; +wire [81:0] Q_178 = ITOP.iow0.arr[89]; +wire [81:0] Q_179 = ITOP.iow1.arr[89]; +wire [81:0] Q_180 = ITOP.iow0.arr[90]; +wire [81:0] Q_181 = ITOP.iow1.arr[90]; +wire [81:0] Q_182 = ITOP.iow0.arr[91]; +wire [81:0] Q_183 = ITOP.iow1.arr[91]; +wire [81:0] Q_184 = ITOP.iow0.arr[92]; +wire [81:0] Q_185 = ITOP.iow1.arr[92]; +wire [81:0] Q_186 = ITOP.iow0.arr[93]; +wire [81:0] Q_187 = ITOP.iow1.arr[93]; +wire [81:0] Q_188 = ITOP.iow0.arr[94]; +wire [81:0] Q_189 = ITOP.iow1.arr[94]; +wire [81:0] Q_190 = ITOP.iow0.arr[95]; +wire [81:0] Q_191 = ITOP.iow1.arr[95]; +wire [81:0] Q_192 = ITOP.iow0.arr[96]; +wire [81:0] Q_193 = ITOP.iow1.arr[96]; +wire [81:0] Q_194 = ITOP.iow0.arr[97]; +wire [81:0] Q_195 = ITOP.iow1.arr[97]; +wire [81:0] Q_196 = ITOP.iow0.arr[98]; +wire [81:0] Q_197 = ITOP.iow1.arr[98]; +wire [81:0] Q_198 = ITOP.iow0.arr[99]; +wire [81:0] Q_199 = ITOP.iow1.arr[99]; +wire [81:0] Q_200 = ITOP.iow0.arr[100]; +wire [81:0] Q_201 = ITOP.iow1.arr[100]; +wire [81:0] Q_202 = ITOP.iow0.arr[101]; +wire [81:0] Q_203 = ITOP.iow1.arr[101]; +wire [81:0] Q_204 = ITOP.iow0.arr[102]; +wire [81:0] Q_205 = ITOP.iow1.arr[102]; +wire [81:0] Q_206 = ITOP.iow0.arr[103]; +wire [81:0] Q_207 = ITOP.iow1.arr[103]; +wire [81:0] Q_208 = ITOP.iow0.arr[104]; +wire [81:0] Q_209 = ITOP.iow1.arr[104]; +wire [81:0] Q_210 = ITOP.iow0.arr[105]; +wire [81:0] Q_211 = ITOP.iow1.arr[105]; +wire [81:0] Q_212 = ITOP.iow0.arr[106]; +wire [81:0] Q_213 = ITOP.iow1.arr[106]; +wire [81:0] Q_214 = ITOP.iow0.arr[107]; +wire [81:0] Q_215 = ITOP.iow1.arr[107]; +wire [81:0] Q_216 = ITOP.iow0.arr[108]; +wire [81:0] Q_217 = ITOP.iow1.arr[108]; +wire [81:0] Q_218 = ITOP.iow0.arr[109]; +wire [81:0] Q_219 = ITOP.iow1.arr[109]; +wire [81:0] Q_220 = ITOP.iow0.arr[110]; +wire [81:0] Q_221 = ITOP.iow1.arr[110]; +wire [81:0] Q_222 = ITOP.iow0.arr[111]; +wire [81:0] Q_223 = ITOP.iow1.arr[111]; +wire [81:0] Q_224 = ITOP.iow0.arr[112]; +wire [81:0] Q_225 = ITOP.iow1.arr[112]; +wire [81:0] Q_226 = ITOP.iow0.arr[113]; +wire [81:0] Q_227 = ITOP.iow1.arr[113]; +wire [81:0] Q_228 = ITOP.iow0.arr[114]; +wire [81:0] Q_229 = ITOP.iow1.arr[114]; +wire [81:0] Q_230 = ITOP.iow0.arr[115]; +wire [81:0] Q_231 = ITOP.iow1.arr[115]; +wire [81:0] Q_232 = ITOP.iow0.arr[116]; +wire [81:0] Q_233 = ITOP.iow1.arr[116]; +wire [81:0] Q_234 = ITOP.iow0.arr[117]; +wire [81:0] Q_235 = ITOP.iow1.arr[117]; +wire [81:0] Q_236 = ITOP.iow0.arr[118]; +wire [81:0] Q_237 = ITOP.iow1.arr[118]; +wire [81:0] Q_238 = ITOP.iow0.arr[119]; +wire [81:0] Q_239 = ITOP.iow1.arr[119]; +wire [81:0] Q_240 = ITOP.iow0.arr[120]; +wire [81:0] Q_241 = ITOP.iow1.arr[120]; +wire [81:0] Q_242 = ITOP.iow0.arr[121]; +wire [81:0] Q_243 = ITOP.iow1.arr[121]; +wire [81:0] Q_244 = ITOP.iow0.arr[122]; +wire [81:0] Q_245 = ITOP.iow1.arr[122]; +wire [81:0] Q_246 = ITOP.iow0.arr[123]; +wire [81:0] Q_247 = ITOP.iow1.arr[123]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [81:0] WD_FF; + reg [81:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [81:0] mem[247:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [81:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [81:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_248X82_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [81:0] WD; +input [7:0] RA, WA; +output [81:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [81:0] WDQ; + wire [81:0] WDBQ; + wire [81:0] WMNexp; + wire [81:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [81:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {82{1'b0}}; + assign SHFT = {82{1'b1}}; + reg [81:0] WDQ_pr; + wire [81:0] WDBQ_pr; + assign WMNexp = {82{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[81:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [81:0] dout; + wire [81:0] RD; + wire RD_rdnt; + wire [81:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [81:0] RDBYPASS = {82{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 248 --> ['1', '1', '1', '1', '0', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] & ADR[5] & ADR[4] & ADR[3]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [81:0] force_x; +`ifndef SYNTHESIS + assign force_x = {82{1'bx}}; +`else + assign force_x = {82{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [81:0] rmuxd0, rmuxd1; + wire [81:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {82{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {82{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {82{RdClk0}} & ~dout0 ; + assign rmuxd1 = {82{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[81:0] <= (rmuxd0[81:0] | rmuxd1[81:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_248X82_GL_M2_D2_ram # (124, 82, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_248X82_GL_M2_D2_ram # (124, 82, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [81:0] data; + reg [81:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [81:0] mem_read_bank; +input [7:0] addr; +reg [81:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_248X82_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 124; +parameter bits = 82; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [81:0] val; + integer i; + begin + for (i=0; i<248; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [81:0] val; + integer i; + begin + val = {82{fill_bit}}; + for (i=0; i<248; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [81:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [82-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {82 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{18{1'b1}}) } `endif ; + else raminit_fullval = {82 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [163:0] mem_phys_read_padr; +input [6:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [163:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [163:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [163:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [164-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {164 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{4{1'b1}}) } `endif ; + else raminit_fullval = {164 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [81:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 82'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 82'bx; + for (i=0; i<=81; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [163:0] data; + reg [81:0] wr[1:0]; + integer i; + begin + for (i=0; i<=81; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [163:0] mon_bit_w; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [163:0] mon_bit_r; +input [6:0] addr; + reg [163:0] mon_row; + reg [81:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=81; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [163:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=124;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<124; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<164; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [81:0] Q_0 = ITOP.iow0.arr[0]; +wire [81:0] Q_1 = ITOP.iow1.arr[0]; +wire [81:0] Q_2 = ITOP.iow0.arr[1]; +wire [81:0] Q_3 = ITOP.iow1.arr[1]; +wire [81:0] Q_4 = ITOP.iow0.arr[2]; +wire [81:0] Q_5 = ITOP.iow1.arr[2]; +wire [81:0] Q_6 = ITOP.iow0.arr[3]; +wire [81:0] Q_7 = ITOP.iow1.arr[3]; +wire [81:0] Q_8 = ITOP.iow0.arr[4]; +wire [81:0] Q_9 = ITOP.iow1.arr[4]; +wire [81:0] Q_10 = ITOP.iow0.arr[5]; +wire [81:0] Q_11 = ITOP.iow1.arr[5]; +wire [81:0] Q_12 = ITOP.iow0.arr[6]; +wire [81:0] Q_13 = ITOP.iow1.arr[6]; +wire [81:0] Q_14 = ITOP.iow0.arr[7]; +wire [81:0] Q_15 = ITOP.iow1.arr[7]; +wire [81:0] Q_16 = ITOP.iow0.arr[8]; +wire [81:0] Q_17 = ITOP.iow1.arr[8]; +wire [81:0] Q_18 = ITOP.iow0.arr[9]; +wire [81:0] Q_19 = ITOP.iow1.arr[9]; +wire [81:0] Q_20 = ITOP.iow0.arr[10]; +wire [81:0] Q_21 = ITOP.iow1.arr[10]; +wire [81:0] Q_22 = ITOP.iow0.arr[11]; +wire [81:0] Q_23 = ITOP.iow1.arr[11]; +wire [81:0] Q_24 = ITOP.iow0.arr[12]; +wire [81:0] Q_25 = ITOP.iow1.arr[12]; +wire [81:0] Q_26 = ITOP.iow0.arr[13]; +wire [81:0] Q_27 = ITOP.iow1.arr[13]; +wire [81:0] Q_28 = ITOP.iow0.arr[14]; +wire [81:0] Q_29 = ITOP.iow1.arr[14]; +wire [81:0] Q_30 = ITOP.iow0.arr[15]; +wire [81:0] Q_31 = ITOP.iow1.arr[15]; +wire [81:0] Q_32 = ITOP.iow0.arr[16]; +wire [81:0] Q_33 = ITOP.iow1.arr[16]; +wire [81:0] Q_34 = ITOP.iow0.arr[17]; +wire [81:0] Q_35 = ITOP.iow1.arr[17]; +wire [81:0] Q_36 = ITOP.iow0.arr[18]; +wire [81:0] Q_37 = ITOP.iow1.arr[18]; +wire [81:0] Q_38 = ITOP.iow0.arr[19]; +wire [81:0] Q_39 = ITOP.iow1.arr[19]; +wire [81:0] Q_40 = ITOP.iow0.arr[20]; +wire [81:0] Q_41 = ITOP.iow1.arr[20]; +wire [81:0] Q_42 = ITOP.iow0.arr[21]; +wire [81:0] Q_43 = ITOP.iow1.arr[21]; +wire [81:0] Q_44 = ITOP.iow0.arr[22]; +wire [81:0] Q_45 = ITOP.iow1.arr[22]; +wire [81:0] Q_46 = ITOP.iow0.arr[23]; +wire [81:0] Q_47 = ITOP.iow1.arr[23]; +wire [81:0] Q_48 = ITOP.iow0.arr[24]; +wire [81:0] Q_49 = ITOP.iow1.arr[24]; +wire [81:0] Q_50 = ITOP.iow0.arr[25]; +wire [81:0] Q_51 = ITOP.iow1.arr[25]; +wire [81:0] Q_52 = ITOP.iow0.arr[26]; +wire [81:0] Q_53 = ITOP.iow1.arr[26]; +wire [81:0] Q_54 = ITOP.iow0.arr[27]; +wire [81:0] Q_55 = ITOP.iow1.arr[27]; +wire [81:0] Q_56 = ITOP.iow0.arr[28]; +wire [81:0] Q_57 = ITOP.iow1.arr[28]; +wire [81:0] Q_58 = ITOP.iow0.arr[29]; +wire [81:0] Q_59 = ITOP.iow1.arr[29]; +wire [81:0] Q_60 = ITOP.iow0.arr[30]; +wire [81:0] Q_61 = ITOP.iow1.arr[30]; +wire [81:0] Q_62 = ITOP.iow0.arr[31]; +wire [81:0] Q_63 = ITOP.iow1.arr[31]; +wire [81:0] Q_64 = ITOP.iow0.arr[32]; +wire [81:0] Q_65 = ITOP.iow1.arr[32]; +wire [81:0] Q_66 = ITOP.iow0.arr[33]; +wire [81:0] Q_67 = ITOP.iow1.arr[33]; +wire [81:0] Q_68 = ITOP.iow0.arr[34]; +wire [81:0] Q_69 = ITOP.iow1.arr[34]; +wire [81:0] Q_70 = ITOP.iow0.arr[35]; +wire [81:0] Q_71 = ITOP.iow1.arr[35]; +wire [81:0] Q_72 = ITOP.iow0.arr[36]; +wire [81:0] Q_73 = ITOP.iow1.arr[36]; +wire [81:0] Q_74 = ITOP.iow0.arr[37]; +wire [81:0] Q_75 = ITOP.iow1.arr[37]; +wire [81:0] Q_76 = ITOP.iow0.arr[38]; +wire [81:0] Q_77 = ITOP.iow1.arr[38]; +wire [81:0] Q_78 = ITOP.iow0.arr[39]; +wire [81:0] Q_79 = ITOP.iow1.arr[39]; +wire [81:0] Q_80 = ITOP.iow0.arr[40]; +wire [81:0] Q_81 = ITOP.iow1.arr[40]; +wire [81:0] Q_82 = ITOP.iow0.arr[41]; +wire [81:0] Q_83 = ITOP.iow1.arr[41]; +wire [81:0] Q_84 = ITOP.iow0.arr[42]; +wire [81:0] Q_85 = ITOP.iow1.arr[42]; +wire [81:0] Q_86 = ITOP.iow0.arr[43]; +wire [81:0] Q_87 = ITOP.iow1.arr[43]; +wire [81:0] Q_88 = ITOP.iow0.arr[44]; +wire [81:0] Q_89 = ITOP.iow1.arr[44]; +wire [81:0] Q_90 = ITOP.iow0.arr[45]; +wire [81:0] Q_91 = ITOP.iow1.arr[45]; +wire [81:0] Q_92 = ITOP.iow0.arr[46]; +wire [81:0] Q_93 = ITOP.iow1.arr[46]; +wire [81:0] Q_94 = ITOP.iow0.arr[47]; +wire [81:0] Q_95 = ITOP.iow1.arr[47]; +wire [81:0] Q_96 = ITOP.iow0.arr[48]; +wire [81:0] Q_97 = ITOP.iow1.arr[48]; +wire [81:0] Q_98 = ITOP.iow0.arr[49]; +wire [81:0] Q_99 = ITOP.iow1.arr[49]; +wire [81:0] Q_100 = ITOP.iow0.arr[50]; +wire [81:0] Q_101 = ITOP.iow1.arr[50]; +wire [81:0] Q_102 = ITOP.iow0.arr[51]; +wire [81:0] Q_103 = ITOP.iow1.arr[51]; +wire [81:0] Q_104 = ITOP.iow0.arr[52]; +wire [81:0] Q_105 = ITOP.iow1.arr[52]; +wire [81:0] Q_106 = ITOP.iow0.arr[53]; +wire [81:0] Q_107 = ITOP.iow1.arr[53]; +wire [81:0] Q_108 = ITOP.iow0.arr[54]; +wire [81:0] Q_109 = ITOP.iow1.arr[54]; +wire [81:0] Q_110 = ITOP.iow0.arr[55]; +wire [81:0] Q_111 = ITOP.iow1.arr[55]; +wire [81:0] Q_112 = ITOP.iow0.arr[56]; +wire [81:0] Q_113 = ITOP.iow1.arr[56]; +wire [81:0] Q_114 = ITOP.iow0.arr[57]; +wire [81:0] Q_115 = ITOP.iow1.arr[57]; +wire [81:0] Q_116 = ITOP.iow0.arr[58]; +wire [81:0] Q_117 = ITOP.iow1.arr[58]; +wire [81:0] Q_118 = ITOP.iow0.arr[59]; +wire [81:0] Q_119 = ITOP.iow1.arr[59]; +wire [81:0] Q_120 = ITOP.iow0.arr[60]; +wire [81:0] Q_121 = ITOP.iow1.arr[60]; +wire [81:0] Q_122 = ITOP.iow0.arr[61]; +wire [81:0] Q_123 = ITOP.iow1.arr[61]; +wire [81:0] Q_124 = ITOP.iow0.arr[62]; +wire [81:0] Q_125 = ITOP.iow1.arr[62]; +wire [81:0] Q_126 = ITOP.iow0.arr[63]; +wire [81:0] Q_127 = ITOP.iow1.arr[63]; +wire [81:0] Q_128 = ITOP.iow0.arr[64]; +wire [81:0] Q_129 = ITOP.iow1.arr[64]; +wire [81:0] Q_130 = ITOP.iow0.arr[65]; +wire [81:0] Q_131 = ITOP.iow1.arr[65]; +wire [81:0] Q_132 = ITOP.iow0.arr[66]; +wire [81:0] Q_133 = ITOP.iow1.arr[66]; +wire [81:0] Q_134 = ITOP.iow0.arr[67]; +wire [81:0] Q_135 = ITOP.iow1.arr[67]; +wire [81:0] Q_136 = ITOP.iow0.arr[68]; +wire [81:0] Q_137 = ITOP.iow1.arr[68]; +wire [81:0] Q_138 = ITOP.iow0.arr[69]; +wire [81:0] Q_139 = ITOP.iow1.arr[69]; +wire [81:0] Q_140 = ITOP.iow0.arr[70]; +wire [81:0] Q_141 = ITOP.iow1.arr[70]; +wire [81:0] Q_142 = ITOP.iow0.arr[71]; +wire [81:0] Q_143 = ITOP.iow1.arr[71]; +wire [81:0] Q_144 = ITOP.iow0.arr[72]; +wire [81:0] Q_145 = ITOP.iow1.arr[72]; +wire [81:0] Q_146 = ITOP.iow0.arr[73]; +wire [81:0] Q_147 = ITOP.iow1.arr[73]; +wire [81:0] Q_148 = ITOP.iow0.arr[74]; +wire [81:0] Q_149 = ITOP.iow1.arr[74]; +wire [81:0] Q_150 = ITOP.iow0.arr[75]; +wire [81:0] Q_151 = ITOP.iow1.arr[75]; +wire [81:0] Q_152 = ITOP.iow0.arr[76]; +wire [81:0] Q_153 = ITOP.iow1.arr[76]; +wire [81:0] Q_154 = ITOP.iow0.arr[77]; +wire [81:0] Q_155 = ITOP.iow1.arr[77]; +wire [81:0] Q_156 = ITOP.iow0.arr[78]; +wire [81:0] Q_157 = ITOP.iow1.arr[78]; +wire [81:0] Q_158 = ITOP.iow0.arr[79]; +wire [81:0] Q_159 = ITOP.iow1.arr[79]; +wire [81:0] Q_160 = ITOP.iow0.arr[80]; +wire [81:0] Q_161 = ITOP.iow1.arr[80]; +wire [81:0] Q_162 = ITOP.iow0.arr[81]; +wire [81:0] Q_163 = ITOP.iow1.arr[81]; +wire [81:0] Q_164 = ITOP.iow0.arr[82]; +wire [81:0] Q_165 = ITOP.iow1.arr[82]; +wire [81:0] Q_166 = ITOP.iow0.arr[83]; +wire [81:0] Q_167 = ITOP.iow1.arr[83]; +wire [81:0] Q_168 = ITOP.iow0.arr[84]; +wire [81:0] Q_169 = ITOP.iow1.arr[84]; +wire [81:0] Q_170 = ITOP.iow0.arr[85]; +wire [81:0] Q_171 = ITOP.iow1.arr[85]; +wire [81:0] Q_172 = ITOP.iow0.arr[86]; +wire [81:0] Q_173 = ITOP.iow1.arr[86]; +wire [81:0] Q_174 = ITOP.iow0.arr[87]; +wire [81:0] Q_175 = ITOP.iow1.arr[87]; +wire [81:0] Q_176 = ITOP.iow0.arr[88]; +wire [81:0] Q_177 = ITOP.iow1.arr[88]; +wire [81:0] Q_178 = ITOP.iow0.arr[89]; +wire [81:0] Q_179 = ITOP.iow1.arr[89]; +wire [81:0] Q_180 = ITOP.iow0.arr[90]; +wire [81:0] Q_181 = ITOP.iow1.arr[90]; +wire [81:0] Q_182 = ITOP.iow0.arr[91]; +wire [81:0] Q_183 = ITOP.iow1.arr[91]; +wire [81:0] Q_184 = ITOP.iow0.arr[92]; +wire [81:0] Q_185 = ITOP.iow1.arr[92]; +wire [81:0] Q_186 = ITOP.iow0.arr[93]; +wire [81:0] Q_187 = ITOP.iow1.arr[93]; +wire [81:0] Q_188 = ITOP.iow0.arr[94]; +wire [81:0] Q_189 = ITOP.iow1.arr[94]; +wire [81:0] Q_190 = ITOP.iow0.arr[95]; +wire [81:0] Q_191 = ITOP.iow1.arr[95]; +wire [81:0] Q_192 = ITOP.iow0.arr[96]; +wire [81:0] Q_193 = ITOP.iow1.arr[96]; +wire [81:0] Q_194 = ITOP.iow0.arr[97]; +wire [81:0] Q_195 = ITOP.iow1.arr[97]; +wire [81:0] Q_196 = ITOP.iow0.arr[98]; +wire [81:0] Q_197 = ITOP.iow1.arr[98]; +wire [81:0] Q_198 = ITOP.iow0.arr[99]; +wire [81:0] Q_199 = ITOP.iow1.arr[99]; +wire [81:0] Q_200 = ITOP.iow0.arr[100]; +wire [81:0] Q_201 = ITOP.iow1.arr[100]; +wire [81:0] Q_202 = ITOP.iow0.arr[101]; +wire [81:0] Q_203 = ITOP.iow1.arr[101]; +wire [81:0] Q_204 = ITOP.iow0.arr[102]; +wire [81:0] Q_205 = ITOP.iow1.arr[102]; +wire [81:0] Q_206 = ITOP.iow0.arr[103]; +wire [81:0] Q_207 = ITOP.iow1.arr[103]; +wire [81:0] Q_208 = ITOP.iow0.arr[104]; +wire [81:0] Q_209 = ITOP.iow1.arr[104]; +wire [81:0] Q_210 = ITOP.iow0.arr[105]; +wire [81:0] Q_211 = ITOP.iow1.arr[105]; +wire [81:0] Q_212 = ITOP.iow0.arr[106]; +wire [81:0] Q_213 = ITOP.iow1.arr[106]; +wire [81:0] Q_214 = ITOP.iow0.arr[107]; +wire [81:0] Q_215 = ITOP.iow1.arr[107]; +wire [81:0] Q_216 = ITOP.iow0.arr[108]; +wire [81:0] Q_217 = ITOP.iow1.arr[108]; +wire [81:0] Q_218 = ITOP.iow0.arr[109]; +wire [81:0] Q_219 = ITOP.iow1.arr[109]; +wire [81:0] Q_220 = ITOP.iow0.arr[110]; +wire [81:0] Q_221 = ITOP.iow1.arr[110]; +wire [81:0] Q_222 = ITOP.iow0.arr[111]; +wire [81:0] Q_223 = ITOP.iow1.arr[111]; +wire [81:0] Q_224 = ITOP.iow0.arr[112]; +wire [81:0] Q_225 = ITOP.iow1.arr[112]; +wire [81:0] Q_226 = ITOP.iow0.arr[113]; +wire [81:0] Q_227 = ITOP.iow1.arr[113]; +wire [81:0] Q_228 = ITOP.iow0.arr[114]; +wire [81:0] Q_229 = ITOP.iow1.arr[114]; +wire [81:0] Q_230 = ITOP.iow0.arr[115]; +wire [81:0] Q_231 = ITOP.iow1.arr[115]; +wire [81:0] Q_232 = ITOP.iow0.arr[116]; +wire [81:0] Q_233 = ITOP.iow1.arr[116]; +wire [81:0] Q_234 = ITOP.iow0.arr[117]; +wire [81:0] Q_235 = ITOP.iow1.arr[117]; +wire [81:0] Q_236 = ITOP.iow0.arr[118]; +wire [81:0] Q_237 = ITOP.iow1.arr[118]; +wire [81:0] Q_238 = ITOP.iow0.arr[119]; +wire [81:0] Q_239 = ITOP.iow1.arr[119]; +wire [81:0] Q_240 = ITOP.iow0.arr[120]; +wire [81:0] Q_241 = ITOP.iow1.arr[120]; +wire [81:0] Q_242 = ITOP.iow0.arr[121]; +wire [81:0] Q_243 = ITOP.iow1.arr[121]; +wire [81:0] Q_244 = ITOP.iow0.arr[122]; +wire [81:0] Q_245 = ITOP.iow1.arr[122]; +wire [81:0] Q_246 = ITOP.iow0.arr[123]; +wire [81:0] Q_247 = ITOP.iow1.arr[123]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [81:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [81:0] WD_FF; + reg [81:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [81:0] mem[247:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [81:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [81:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_248X82_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [81:0] WD; +input [7:0] RA, WA; +output [81:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [81:0] WDQ; + wire [81:0] WDBQ; + wire [81:0] WMNexp; + wire [81:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [81:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {82{1'b0}}; + assign SHFT = {82{1'b1}}; + reg [81:0] WDQ_pr; + wire [81:0] WDBQ_pr; + assign WMNexp = {82{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[81:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [81:0] dout; + wire [81:0] RD; + wire RD_rdnt; + wire [81:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [81:0] RDBYPASS = {82{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 248 --> ['1', '1', '1', '1', '0', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[7] & ADR[6] & ADR[5] & ADR[4] & ADR[3]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [81:0] force_x; +`ifndef SYNTHESIS + assign force_x = {82{1'bx}}; +`else + assign force_x = {82{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [81:0] rmuxd0, rmuxd1; + wire [81:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {82{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {82{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {82{RdClk0}} & ~dout0 ; + assign rmuxd1 = {82{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[81:0] <= (rmuxd0[81:0] | rmuxd1[81:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_248X82_GL_M2_D2_ram # (124, 82, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_248X82_GL_M2_D2_ram # (124, 82, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [81:0] data; + reg [81:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [81:0] mem_read_bank; +input [7:0] addr; +reg [81:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_248X82_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 124; +parameter bits = 82; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [10:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [10:0] val; + integer i; + begin + val = {11{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [10:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [11-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {11 {1'b1}} `else { $RollPLI(0,{11{1'b1}}) } `endif ; + else raminit_fullval = {11 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[7:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [43:0] mem_phys_read_padr; +input [5:0] addr; + reg [43:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [44-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {44 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{12{1'b1}}) } `endif ; + else raminit_fullval = {44 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [10:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=10; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [43:0] mem_phys_read_ladr; +input [7:0] addr; + reg [5:0] paddr; + reg [43:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [44-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {44 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{12{1'b1}}) } `endif ; + else raminit_fullval = {44 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [10:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=10; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [43:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [43:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [44-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {44 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{12{1'b1}}) } `endif ; + else raminit_fullval = {44 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [10:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:2]) : 11'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:2]) : 11'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[7:2]) : 11'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[7:2]) : 11'bx; + for (i=0; i<=10; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [43:0] data; + reg [10:0] wr[3:0]; + integer i; + begin + for (i=0; i<=10; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [43:0] mon_bit_w; +input [5:0] addr; + reg [43:0] mon_row; + reg [10:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=10; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [43:0] mon_bit_r; +input [5:0] addr; + reg [43:0] mon_row; + reg [10:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=10; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [43:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [10:0] Q_0 = ITOP.iow0.arr[0]; +wire [10:0] Q_1 = ITOP.iow1.arr[0]; +wire [10:0] Q_2 = ITOP.iow2.arr[0]; +wire [10:0] Q_3 = ITOP.iow3.arr[0]; +wire [10:0] Q_4 = ITOP.iow0.arr[1]; +wire [10:0] Q_5 = ITOP.iow1.arr[1]; +wire [10:0] Q_6 = ITOP.iow2.arr[1]; +wire [10:0] Q_7 = ITOP.iow3.arr[1]; +wire [10:0] Q_8 = ITOP.iow0.arr[2]; +wire [10:0] Q_9 = ITOP.iow1.arr[2]; +wire [10:0] Q_10 = ITOP.iow2.arr[2]; +wire [10:0] Q_11 = ITOP.iow3.arr[2]; +wire [10:0] Q_12 = ITOP.iow0.arr[3]; +wire [10:0] Q_13 = ITOP.iow1.arr[3]; +wire [10:0] Q_14 = ITOP.iow2.arr[3]; +wire [10:0] Q_15 = ITOP.iow3.arr[3]; +wire [10:0] Q_16 = ITOP.iow0.arr[4]; +wire [10:0] Q_17 = ITOP.iow1.arr[4]; +wire [10:0] Q_18 = ITOP.iow2.arr[4]; +wire [10:0] Q_19 = ITOP.iow3.arr[4]; +wire [10:0] Q_20 = ITOP.iow0.arr[5]; +wire [10:0] Q_21 = ITOP.iow1.arr[5]; +wire [10:0] Q_22 = ITOP.iow2.arr[5]; +wire [10:0] Q_23 = ITOP.iow3.arr[5]; +wire [10:0] Q_24 = ITOP.iow0.arr[6]; +wire [10:0] Q_25 = ITOP.iow1.arr[6]; +wire [10:0] Q_26 = ITOP.iow2.arr[6]; +wire [10:0] Q_27 = ITOP.iow3.arr[6]; +wire [10:0] Q_28 = ITOP.iow0.arr[7]; +wire [10:0] Q_29 = ITOP.iow1.arr[7]; +wire [10:0] Q_30 = ITOP.iow2.arr[7]; +wire [10:0] Q_31 = ITOP.iow3.arr[7]; +wire [10:0] Q_32 = ITOP.iow0.arr[8]; +wire [10:0] Q_33 = ITOP.iow1.arr[8]; +wire [10:0] Q_34 = ITOP.iow2.arr[8]; +wire [10:0] Q_35 = ITOP.iow3.arr[8]; +wire [10:0] Q_36 = ITOP.iow0.arr[9]; +wire [10:0] Q_37 = ITOP.iow1.arr[9]; +wire [10:0] Q_38 = ITOP.iow2.arr[9]; +wire [10:0] Q_39 = ITOP.iow3.arr[9]; +wire [10:0] Q_40 = ITOP.iow0.arr[10]; +wire [10:0] Q_41 = ITOP.iow1.arr[10]; +wire [10:0] Q_42 = ITOP.iow2.arr[10]; +wire [10:0] Q_43 = ITOP.iow3.arr[10]; +wire [10:0] Q_44 = ITOP.iow0.arr[11]; +wire [10:0] Q_45 = ITOP.iow1.arr[11]; +wire [10:0] Q_46 = ITOP.iow2.arr[11]; +wire [10:0] Q_47 = ITOP.iow3.arr[11]; +wire [10:0] Q_48 = ITOP.iow0.arr[12]; +wire [10:0] Q_49 = ITOP.iow1.arr[12]; +wire [10:0] Q_50 = ITOP.iow2.arr[12]; +wire [10:0] Q_51 = ITOP.iow3.arr[12]; +wire [10:0] Q_52 = ITOP.iow0.arr[13]; +wire [10:0] Q_53 = ITOP.iow1.arr[13]; +wire [10:0] Q_54 = ITOP.iow2.arr[13]; +wire [10:0] Q_55 = ITOP.iow3.arr[13]; +wire [10:0] Q_56 = ITOP.iow0.arr[14]; +wire [10:0] Q_57 = ITOP.iow1.arr[14]; +wire [10:0] Q_58 = ITOP.iow2.arr[14]; +wire [10:0] Q_59 = ITOP.iow3.arr[14]; +wire [10:0] Q_60 = ITOP.iow0.arr[15]; +wire [10:0] Q_61 = ITOP.iow1.arr[15]; +wire [10:0] Q_62 = ITOP.iow2.arr[15]; +wire [10:0] Q_63 = ITOP.iow3.arr[15]; +wire [10:0] Q_64 = ITOP.iow0.arr[16]; +wire [10:0] Q_65 = ITOP.iow1.arr[16]; +wire [10:0] Q_66 = ITOP.iow2.arr[16]; +wire [10:0] Q_67 = ITOP.iow3.arr[16]; +wire [10:0] Q_68 = ITOP.iow0.arr[17]; +wire [10:0] Q_69 = ITOP.iow1.arr[17]; +wire [10:0] Q_70 = ITOP.iow2.arr[17]; +wire [10:0] Q_71 = ITOP.iow3.arr[17]; +wire [10:0] Q_72 = ITOP.iow0.arr[18]; +wire [10:0] Q_73 = ITOP.iow1.arr[18]; +wire [10:0] Q_74 = ITOP.iow2.arr[18]; +wire [10:0] Q_75 = ITOP.iow3.arr[18]; +wire [10:0] Q_76 = ITOP.iow0.arr[19]; +wire [10:0] Q_77 = ITOP.iow1.arr[19]; +wire [10:0] Q_78 = ITOP.iow2.arr[19]; +wire [10:0] Q_79 = ITOP.iow3.arr[19]; +wire [10:0] Q_80 = ITOP.iow0.arr[20]; +wire [10:0] Q_81 = ITOP.iow1.arr[20]; +wire [10:0] Q_82 = ITOP.iow2.arr[20]; +wire [10:0] Q_83 = ITOP.iow3.arr[20]; +wire [10:0] Q_84 = ITOP.iow0.arr[21]; +wire [10:0] Q_85 = ITOP.iow1.arr[21]; +wire [10:0] Q_86 = ITOP.iow2.arr[21]; +wire [10:0] Q_87 = ITOP.iow3.arr[21]; +wire [10:0] Q_88 = ITOP.iow0.arr[22]; +wire [10:0] Q_89 = ITOP.iow1.arr[22]; +wire [10:0] Q_90 = ITOP.iow2.arr[22]; +wire [10:0] Q_91 = ITOP.iow3.arr[22]; +wire [10:0] Q_92 = ITOP.iow0.arr[23]; +wire [10:0] Q_93 = ITOP.iow1.arr[23]; +wire [10:0] Q_94 = ITOP.iow2.arr[23]; +wire [10:0] Q_95 = ITOP.iow3.arr[23]; +wire [10:0] Q_96 = ITOP.iow0.arr[24]; +wire [10:0] Q_97 = ITOP.iow1.arr[24]; +wire [10:0] Q_98 = ITOP.iow2.arr[24]; +wire [10:0] Q_99 = ITOP.iow3.arr[24]; +wire [10:0] Q_100 = ITOP.iow0.arr[25]; +wire [10:0] Q_101 = ITOP.iow1.arr[25]; +wire [10:0] Q_102 = ITOP.iow2.arr[25]; +wire [10:0] Q_103 = ITOP.iow3.arr[25]; +wire [10:0] Q_104 = ITOP.iow0.arr[26]; +wire [10:0] Q_105 = ITOP.iow1.arr[26]; +wire [10:0] Q_106 = ITOP.iow2.arr[26]; +wire [10:0] Q_107 = ITOP.iow3.arr[26]; +wire [10:0] Q_108 = ITOP.iow0.arr[27]; +wire [10:0] Q_109 = ITOP.iow1.arr[27]; +wire [10:0] Q_110 = ITOP.iow2.arr[27]; +wire [10:0] Q_111 = ITOP.iow3.arr[27]; +wire [10:0] Q_112 = ITOP.iow0.arr[28]; +wire [10:0] Q_113 = ITOP.iow1.arr[28]; +wire [10:0] Q_114 = ITOP.iow2.arr[28]; +wire [10:0] Q_115 = ITOP.iow3.arr[28]; +wire [10:0] Q_116 = ITOP.iow0.arr[29]; +wire [10:0] Q_117 = ITOP.iow1.arr[29]; +wire [10:0] Q_118 = ITOP.iow2.arr[29]; +wire [10:0] Q_119 = ITOP.iow3.arr[29]; +wire [10:0] Q_120 = ITOP.iow0.arr[30]; +wire [10:0] Q_121 = ITOP.iow1.arr[30]; +wire [10:0] Q_122 = ITOP.iow2.arr[30]; +wire [10:0] Q_123 = ITOP.iow3.arr[30]; +wire [10:0] Q_124 = ITOP.iow0.arr[31]; +wire [10:0] Q_125 = ITOP.iow1.arr[31]; +wire [10:0] Q_126 = ITOP.iow2.arr[31]; +wire [10:0] Q_127 = ITOP.iow3.arr[31]; +wire [10:0] Q_128 = ITOP.iow0.arr[32]; +wire [10:0] Q_129 = ITOP.iow1.arr[32]; +wire [10:0] Q_130 = ITOP.iow2.arr[32]; +wire [10:0] Q_131 = ITOP.iow3.arr[32]; +wire [10:0] Q_132 = ITOP.iow0.arr[33]; +wire [10:0] Q_133 = ITOP.iow1.arr[33]; +wire [10:0] Q_134 = ITOP.iow2.arr[33]; +wire [10:0] Q_135 = ITOP.iow3.arr[33]; +wire [10:0] Q_136 = ITOP.iow0.arr[34]; +wire [10:0] Q_137 = ITOP.iow1.arr[34]; +wire [10:0] Q_138 = ITOP.iow2.arr[34]; +wire [10:0] Q_139 = ITOP.iow3.arr[34]; +wire [10:0] Q_140 = ITOP.iow0.arr[35]; +wire [10:0] Q_141 = ITOP.iow1.arr[35]; +wire [10:0] Q_142 = ITOP.iow2.arr[35]; +wire [10:0] Q_143 = ITOP.iow3.arr[35]; +wire [10:0] Q_144 = ITOP.iow0.arr[36]; +wire [10:0] Q_145 = ITOP.iow1.arr[36]; +wire [10:0] Q_146 = ITOP.iow2.arr[36]; +wire [10:0] Q_147 = ITOP.iow3.arr[36]; +wire [10:0] Q_148 = ITOP.iow0.arr[37]; +wire [10:0] Q_149 = ITOP.iow1.arr[37]; +wire [10:0] Q_150 = ITOP.iow2.arr[37]; +wire [10:0] Q_151 = ITOP.iow3.arr[37]; +wire [10:0] Q_152 = ITOP.iow0.arr[38]; +wire [10:0] Q_153 = ITOP.iow1.arr[38]; +wire [10:0] Q_154 = ITOP.iow2.arr[38]; +wire [10:0] Q_155 = ITOP.iow3.arr[38]; +wire [10:0] Q_156 = ITOP.iow0.arr[39]; +wire [10:0] Q_157 = ITOP.iow1.arr[39]; +wire [10:0] Q_158 = ITOP.iow2.arr[39]; +wire [10:0] Q_159 = ITOP.iow3.arr[39]; +wire [10:0] Q_160 = ITOP.iow0.arr[40]; +wire [10:0] Q_161 = ITOP.iow1.arr[40]; +wire [10:0] Q_162 = ITOP.iow2.arr[40]; +wire [10:0] Q_163 = ITOP.iow3.arr[40]; +wire [10:0] Q_164 = ITOP.iow0.arr[41]; +wire [10:0] Q_165 = ITOP.iow1.arr[41]; +wire [10:0] Q_166 = ITOP.iow2.arr[41]; +wire [10:0] Q_167 = ITOP.iow3.arr[41]; +wire [10:0] Q_168 = ITOP.iow0.arr[42]; +wire [10:0] Q_169 = ITOP.iow1.arr[42]; +wire [10:0] Q_170 = ITOP.iow2.arr[42]; +wire [10:0] Q_171 = ITOP.iow3.arr[42]; +wire [10:0] Q_172 = ITOP.iow0.arr[43]; +wire [10:0] Q_173 = ITOP.iow1.arr[43]; +wire [10:0] Q_174 = ITOP.iow2.arr[43]; +wire [10:0] Q_175 = ITOP.iow3.arr[43]; +wire [10:0] Q_176 = ITOP.iow0.arr[44]; +wire [10:0] Q_177 = ITOP.iow1.arr[44]; +wire [10:0] Q_178 = ITOP.iow2.arr[44]; +wire [10:0] Q_179 = ITOP.iow3.arr[44]; +wire [10:0] Q_180 = ITOP.iow0.arr[45]; +wire [10:0] Q_181 = ITOP.iow1.arr[45]; +wire [10:0] Q_182 = ITOP.iow2.arr[45]; +wire [10:0] Q_183 = ITOP.iow3.arr[45]; +wire [10:0] Q_184 = ITOP.iow0.arr[46]; +wire [10:0] Q_185 = ITOP.iow1.arr[46]; +wire [10:0] Q_186 = ITOP.iow2.arr[46]; +wire [10:0] Q_187 = ITOP.iow3.arr[46]; +wire [10:0] Q_188 = ITOP.iow0.arr[47]; +wire [10:0] Q_189 = ITOP.iow1.arr[47]; +wire [10:0] Q_190 = ITOP.iow2.arr[47]; +wire [10:0] Q_191 = ITOP.iow3.arr[47]; +wire [10:0] Q_192 = ITOP.iow0.arr[48]; +wire [10:0] Q_193 = ITOP.iow1.arr[48]; +wire [10:0] Q_194 = ITOP.iow2.arr[48]; +wire [10:0] Q_195 = ITOP.iow3.arr[48]; +wire [10:0] Q_196 = ITOP.iow0.arr[49]; +wire [10:0] Q_197 = ITOP.iow1.arr[49]; +wire [10:0] Q_198 = ITOP.iow2.arr[49]; +wire [10:0] Q_199 = ITOP.iow3.arr[49]; +wire [10:0] Q_200 = ITOP.iow0.arr[50]; +wire [10:0] Q_201 = ITOP.iow1.arr[50]; +wire [10:0] Q_202 = ITOP.iow2.arr[50]; +wire [10:0] Q_203 = ITOP.iow3.arr[50]; +wire [10:0] Q_204 = ITOP.iow0.arr[51]; +wire [10:0] Q_205 = ITOP.iow1.arr[51]; +wire [10:0] Q_206 = ITOP.iow2.arr[51]; +wire [10:0] Q_207 = ITOP.iow3.arr[51]; +wire [10:0] Q_208 = ITOP.iow0.arr[52]; +wire [10:0] Q_209 = ITOP.iow1.arr[52]; +wire [10:0] Q_210 = ITOP.iow2.arr[52]; +wire [10:0] Q_211 = ITOP.iow3.arr[52]; +wire [10:0] Q_212 = ITOP.iow0.arr[53]; +wire [10:0] Q_213 = ITOP.iow1.arr[53]; +wire [10:0] Q_214 = ITOP.iow2.arr[53]; +wire [10:0] Q_215 = ITOP.iow3.arr[53]; +wire [10:0] Q_216 = ITOP.iow0.arr[54]; +wire [10:0] Q_217 = ITOP.iow1.arr[54]; +wire [10:0] Q_218 = ITOP.iow2.arr[54]; +wire [10:0] Q_219 = ITOP.iow3.arr[54]; +wire [10:0] Q_220 = ITOP.iow0.arr[55]; +wire [10:0] Q_221 = ITOP.iow1.arr[55]; +wire [10:0] Q_222 = ITOP.iow2.arr[55]; +wire [10:0] Q_223 = ITOP.iow3.arr[55]; +wire [10:0] Q_224 = ITOP.iow0.arr[56]; +wire [10:0] Q_225 = ITOP.iow1.arr[56]; +wire [10:0] Q_226 = ITOP.iow2.arr[56]; +wire [10:0] Q_227 = ITOP.iow3.arr[56]; +wire [10:0] Q_228 = ITOP.iow0.arr[57]; +wire [10:0] Q_229 = ITOP.iow1.arr[57]; +wire [10:0] Q_230 = ITOP.iow2.arr[57]; +wire [10:0] Q_231 = ITOP.iow3.arr[57]; +wire [10:0] Q_232 = ITOP.iow0.arr[58]; +wire [10:0] Q_233 = ITOP.iow1.arr[58]; +wire [10:0] Q_234 = ITOP.iow2.arr[58]; +wire [10:0] Q_235 = ITOP.iow3.arr[58]; +wire [10:0] Q_236 = ITOP.iow0.arr[59]; +wire [10:0] Q_237 = ITOP.iow1.arr[59]; +wire [10:0] Q_238 = ITOP.iow2.arr[59]; +wire [10:0] Q_239 = ITOP.iow3.arr[59]; +wire [10:0] Q_240 = ITOP.iow0.arr[60]; +wire [10:0] Q_241 = ITOP.iow1.arr[60]; +wire [10:0] Q_242 = ITOP.iow2.arr[60]; +wire [10:0] Q_243 = ITOP.iow3.arr[60]; +wire [10:0] Q_244 = ITOP.iow0.arr[61]; +wire [10:0] Q_245 = ITOP.iow1.arr[61]; +wire [10:0] Q_246 = ITOP.iow2.arr[61]; +wire [10:0] Q_247 = ITOP.iow3.arr[61]; +wire [10:0] Q_248 = ITOP.iow0.arr[62]; +wire [10:0] Q_249 = ITOP.iow1.arr[62]; +wire [10:0] Q_250 = ITOP.iow2.arr[62]; +wire [10:0] Q_251 = ITOP.iow3.arr[62]; +wire [10:0] Q_252 = ITOP.iow0.arr[63]; +wire [10:0] Q_253 = ITOP.iow1.arr[63]; +wire [10:0] Q_254 = ITOP.iow2.arr[63]; +wire [10:0] Q_255 = ITOP.iow3.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [10:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [10:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [10:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [10:0] WD_FF; + reg [10:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [10:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [10:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [10:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X11_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [10:0] WD; +input [8:0] RA, WA; +output [10:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [10:0] WDQ; + wire [10:0] WDBQ; + wire [10:0] WMNexp; + wire [10:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [10:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {11{1'b0}}; + assign SHFT = {11{1'b1}}; + reg [10:0] WDQ_pr; + wire [10:0] WDBQ_pr; + assign WMNexp = {11{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[10:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [10:0] dout; + wire [10:0] RD; + wire RD_rdnt; + wire [10:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [10:0] RDBYPASS = {11{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 256 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[8:8]); +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [10:0] force_x; +`ifndef SYNTHESIS + assign force_x = {11{1'bx}}; +`else + assign force_x = {11{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [10:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [10:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {11{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {11{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {11{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {11{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {11{RdClk0}} & ~dout0; + assign rmuxd1 = {11{RdClk1}} & ~dout1; + assign rmuxd2 = {11{RdClk2}} & ~dout2; + assign rmuxd3 = {11{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[10:0] <= (rmuxd0[10:0] | rmuxd1[10:0] | rmuxd2[10:0] | rmuxd3[10:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [10:0] data; + reg [10:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[7:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[7:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[7:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[7:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [10:0] mem_read_bank; +input [7:0] addr; +reg [10:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[7:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X11_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 11; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [10:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [10:0] val; + integer i; + begin + val = {11{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [10:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [11-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {11 {1'b1}} `else { $RollPLI(0,{11{1'b1}}) } `endif ; + else raminit_fullval = {11 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[7:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [43:0] mem_phys_read_padr; +input [5:0] addr; + reg [43:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [44-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {44 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{12{1'b1}}) } `endif ; + else raminit_fullval = {44 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [10:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=10; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [43:0] mem_phys_read_ladr; +input [7:0] addr; + reg [5:0] paddr; + reg [43:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [44-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {44 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{12{1'b1}}) } `endif ; + else raminit_fullval = {44 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [10:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=10; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [43:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [43:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [44-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {44 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{12{1'b1}}) } `endif ; + else raminit_fullval = {44 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [10:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:2]) : 11'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:2]) : 11'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[7:2]) : 11'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[7:2]) : 11'bx; + for (i=0; i<=10; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [43:0] data; + reg [10:0] wr[3:0]; + integer i; + begin + for (i=0; i<=10; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [43:0] mon_bit_w; +input [5:0] addr; + reg [43:0] mon_row; + reg [10:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=10; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [43:0] mon_bit_r; +input [5:0] addr; + reg [43:0] mon_row; + reg [10:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=10; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [43:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<44; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [10:0] Q_0 = ITOP.iow0.arr[0]; +wire [10:0] Q_1 = ITOP.iow1.arr[0]; +wire [10:0] Q_2 = ITOP.iow2.arr[0]; +wire [10:0] Q_3 = ITOP.iow3.arr[0]; +wire [10:0] Q_4 = ITOP.iow0.arr[1]; +wire [10:0] Q_5 = ITOP.iow1.arr[1]; +wire [10:0] Q_6 = ITOP.iow2.arr[1]; +wire [10:0] Q_7 = ITOP.iow3.arr[1]; +wire [10:0] Q_8 = ITOP.iow0.arr[2]; +wire [10:0] Q_9 = ITOP.iow1.arr[2]; +wire [10:0] Q_10 = ITOP.iow2.arr[2]; +wire [10:0] Q_11 = ITOP.iow3.arr[2]; +wire [10:0] Q_12 = ITOP.iow0.arr[3]; +wire [10:0] Q_13 = ITOP.iow1.arr[3]; +wire [10:0] Q_14 = ITOP.iow2.arr[3]; +wire [10:0] Q_15 = ITOP.iow3.arr[3]; +wire [10:0] Q_16 = ITOP.iow0.arr[4]; +wire [10:0] Q_17 = ITOP.iow1.arr[4]; +wire [10:0] Q_18 = ITOP.iow2.arr[4]; +wire [10:0] Q_19 = ITOP.iow3.arr[4]; +wire [10:0] Q_20 = ITOP.iow0.arr[5]; +wire [10:0] Q_21 = ITOP.iow1.arr[5]; +wire [10:0] Q_22 = ITOP.iow2.arr[5]; +wire [10:0] Q_23 = ITOP.iow3.arr[5]; +wire [10:0] Q_24 = ITOP.iow0.arr[6]; +wire [10:0] Q_25 = ITOP.iow1.arr[6]; +wire [10:0] Q_26 = ITOP.iow2.arr[6]; +wire [10:0] Q_27 = ITOP.iow3.arr[6]; +wire [10:0] Q_28 = ITOP.iow0.arr[7]; +wire [10:0] Q_29 = ITOP.iow1.arr[7]; +wire [10:0] Q_30 = ITOP.iow2.arr[7]; +wire [10:0] Q_31 = ITOP.iow3.arr[7]; +wire [10:0] Q_32 = ITOP.iow0.arr[8]; +wire [10:0] Q_33 = ITOP.iow1.arr[8]; +wire [10:0] Q_34 = ITOP.iow2.arr[8]; +wire [10:0] Q_35 = ITOP.iow3.arr[8]; +wire [10:0] Q_36 = ITOP.iow0.arr[9]; +wire [10:0] Q_37 = ITOP.iow1.arr[9]; +wire [10:0] Q_38 = ITOP.iow2.arr[9]; +wire [10:0] Q_39 = ITOP.iow3.arr[9]; +wire [10:0] Q_40 = ITOP.iow0.arr[10]; +wire [10:0] Q_41 = ITOP.iow1.arr[10]; +wire [10:0] Q_42 = ITOP.iow2.arr[10]; +wire [10:0] Q_43 = ITOP.iow3.arr[10]; +wire [10:0] Q_44 = ITOP.iow0.arr[11]; +wire [10:0] Q_45 = ITOP.iow1.arr[11]; +wire [10:0] Q_46 = ITOP.iow2.arr[11]; +wire [10:0] Q_47 = ITOP.iow3.arr[11]; +wire [10:0] Q_48 = ITOP.iow0.arr[12]; +wire [10:0] Q_49 = ITOP.iow1.arr[12]; +wire [10:0] Q_50 = ITOP.iow2.arr[12]; +wire [10:0] Q_51 = ITOP.iow3.arr[12]; +wire [10:0] Q_52 = ITOP.iow0.arr[13]; +wire [10:0] Q_53 = ITOP.iow1.arr[13]; +wire [10:0] Q_54 = ITOP.iow2.arr[13]; +wire [10:0] Q_55 = ITOP.iow3.arr[13]; +wire [10:0] Q_56 = ITOP.iow0.arr[14]; +wire [10:0] Q_57 = ITOP.iow1.arr[14]; +wire [10:0] Q_58 = ITOP.iow2.arr[14]; +wire [10:0] Q_59 = ITOP.iow3.arr[14]; +wire [10:0] Q_60 = ITOP.iow0.arr[15]; +wire [10:0] Q_61 = ITOP.iow1.arr[15]; +wire [10:0] Q_62 = ITOP.iow2.arr[15]; +wire [10:0] Q_63 = ITOP.iow3.arr[15]; +wire [10:0] Q_64 = ITOP.iow0.arr[16]; +wire [10:0] Q_65 = ITOP.iow1.arr[16]; +wire [10:0] Q_66 = ITOP.iow2.arr[16]; +wire [10:0] Q_67 = ITOP.iow3.arr[16]; +wire [10:0] Q_68 = ITOP.iow0.arr[17]; +wire [10:0] Q_69 = ITOP.iow1.arr[17]; +wire [10:0] Q_70 = ITOP.iow2.arr[17]; +wire [10:0] Q_71 = ITOP.iow3.arr[17]; +wire [10:0] Q_72 = ITOP.iow0.arr[18]; +wire [10:0] Q_73 = ITOP.iow1.arr[18]; +wire [10:0] Q_74 = ITOP.iow2.arr[18]; +wire [10:0] Q_75 = ITOP.iow3.arr[18]; +wire [10:0] Q_76 = ITOP.iow0.arr[19]; +wire [10:0] Q_77 = ITOP.iow1.arr[19]; +wire [10:0] Q_78 = ITOP.iow2.arr[19]; +wire [10:0] Q_79 = ITOP.iow3.arr[19]; +wire [10:0] Q_80 = ITOP.iow0.arr[20]; +wire [10:0] Q_81 = ITOP.iow1.arr[20]; +wire [10:0] Q_82 = ITOP.iow2.arr[20]; +wire [10:0] Q_83 = ITOP.iow3.arr[20]; +wire [10:0] Q_84 = ITOP.iow0.arr[21]; +wire [10:0] Q_85 = ITOP.iow1.arr[21]; +wire [10:0] Q_86 = ITOP.iow2.arr[21]; +wire [10:0] Q_87 = ITOP.iow3.arr[21]; +wire [10:0] Q_88 = ITOP.iow0.arr[22]; +wire [10:0] Q_89 = ITOP.iow1.arr[22]; +wire [10:0] Q_90 = ITOP.iow2.arr[22]; +wire [10:0] Q_91 = ITOP.iow3.arr[22]; +wire [10:0] Q_92 = ITOP.iow0.arr[23]; +wire [10:0] Q_93 = ITOP.iow1.arr[23]; +wire [10:0] Q_94 = ITOP.iow2.arr[23]; +wire [10:0] Q_95 = ITOP.iow3.arr[23]; +wire [10:0] Q_96 = ITOP.iow0.arr[24]; +wire [10:0] Q_97 = ITOP.iow1.arr[24]; +wire [10:0] Q_98 = ITOP.iow2.arr[24]; +wire [10:0] Q_99 = ITOP.iow3.arr[24]; +wire [10:0] Q_100 = ITOP.iow0.arr[25]; +wire [10:0] Q_101 = ITOP.iow1.arr[25]; +wire [10:0] Q_102 = ITOP.iow2.arr[25]; +wire [10:0] Q_103 = ITOP.iow3.arr[25]; +wire [10:0] Q_104 = ITOP.iow0.arr[26]; +wire [10:0] Q_105 = ITOP.iow1.arr[26]; +wire [10:0] Q_106 = ITOP.iow2.arr[26]; +wire [10:0] Q_107 = ITOP.iow3.arr[26]; +wire [10:0] Q_108 = ITOP.iow0.arr[27]; +wire [10:0] Q_109 = ITOP.iow1.arr[27]; +wire [10:0] Q_110 = ITOP.iow2.arr[27]; +wire [10:0] Q_111 = ITOP.iow3.arr[27]; +wire [10:0] Q_112 = ITOP.iow0.arr[28]; +wire [10:0] Q_113 = ITOP.iow1.arr[28]; +wire [10:0] Q_114 = ITOP.iow2.arr[28]; +wire [10:0] Q_115 = ITOP.iow3.arr[28]; +wire [10:0] Q_116 = ITOP.iow0.arr[29]; +wire [10:0] Q_117 = ITOP.iow1.arr[29]; +wire [10:0] Q_118 = ITOP.iow2.arr[29]; +wire [10:0] Q_119 = ITOP.iow3.arr[29]; +wire [10:0] Q_120 = ITOP.iow0.arr[30]; +wire [10:0] Q_121 = ITOP.iow1.arr[30]; +wire [10:0] Q_122 = ITOP.iow2.arr[30]; +wire [10:0] Q_123 = ITOP.iow3.arr[30]; +wire [10:0] Q_124 = ITOP.iow0.arr[31]; +wire [10:0] Q_125 = ITOP.iow1.arr[31]; +wire [10:0] Q_126 = ITOP.iow2.arr[31]; +wire [10:0] Q_127 = ITOP.iow3.arr[31]; +wire [10:0] Q_128 = ITOP.iow0.arr[32]; +wire [10:0] Q_129 = ITOP.iow1.arr[32]; +wire [10:0] Q_130 = ITOP.iow2.arr[32]; +wire [10:0] Q_131 = ITOP.iow3.arr[32]; +wire [10:0] Q_132 = ITOP.iow0.arr[33]; +wire [10:0] Q_133 = ITOP.iow1.arr[33]; +wire [10:0] Q_134 = ITOP.iow2.arr[33]; +wire [10:0] Q_135 = ITOP.iow3.arr[33]; +wire [10:0] Q_136 = ITOP.iow0.arr[34]; +wire [10:0] Q_137 = ITOP.iow1.arr[34]; +wire [10:0] Q_138 = ITOP.iow2.arr[34]; +wire [10:0] Q_139 = ITOP.iow3.arr[34]; +wire [10:0] Q_140 = ITOP.iow0.arr[35]; +wire [10:0] Q_141 = ITOP.iow1.arr[35]; +wire [10:0] Q_142 = ITOP.iow2.arr[35]; +wire [10:0] Q_143 = ITOP.iow3.arr[35]; +wire [10:0] Q_144 = ITOP.iow0.arr[36]; +wire [10:0] Q_145 = ITOP.iow1.arr[36]; +wire [10:0] Q_146 = ITOP.iow2.arr[36]; +wire [10:0] Q_147 = ITOP.iow3.arr[36]; +wire [10:0] Q_148 = ITOP.iow0.arr[37]; +wire [10:0] Q_149 = ITOP.iow1.arr[37]; +wire [10:0] Q_150 = ITOP.iow2.arr[37]; +wire [10:0] Q_151 = ITOP.iow3.arr[37]; +wire [10:0] Q_152 = ITOP.iow0.arr[38]; +wire [10:0] Q_153 = ITOP.iow1.arr[38]; +wire [10:0] Q_154 = ITOP.iow2.arr[38]; +wire [10:0] Q_155 = ITOP.iow3.arr[38]; +wire [10:0] Q_156 = ITOP.iow0.arr[39]; +wire [10:0] Q_157 = ITOP.iow1.arr[39]; +wire [10:0] Q_158 = ITOP.iow2.arr[39]; +wire [10:0] Q_159 = ITOP.iow3.arr[39]; +wire [10:0] Q_160 = ITOP.iow0.arr[40]; +wire [10:0] Q_161 = ITOP.iow1.arr[40]; +wire [10:0] Q_162 = ITOP.iow2.arr[40]; +wire [10:0] Q_163 = ITOP.iow3.arr[40]; +wire [10:0] Q_164 = ITOP.iow0.arr[41]; +wire [10:0] Q_165 = ITOP.iow1.arr[41]; +wire [10:0] Q_166 = ITOP.iow2.arr[41]; +wire [10:0] Q_167 = ITOP.iow3.arr[41]; +wire [10:0] Q_168 = ITOP.iow0.arr[42]; +wire [10:0] Q_169 = ITOP.iow1.arr[42]; +wire [10:0] Q_170 = ITOP.iow2.arr[42]; +wire [10:0] Q_171 = ITOP.iow3.arr[42]; +wire [10:0] Q_172 = ITOP.iow0.arr[43]; +wire [10:0] Q_173 = ITOP.iow1.arr[43]; +wire [10:0] Q_174 = ITOP.iow2.arr[43]; +wire [10:0] Q_175 = ITOP.iow3.arr[43]; +wire [10:0] Q_176 = ITOP.iow0.arr[44]; +wire [10:0] Q_177 = ITOP.iow1.arr[44]; +wire [10:0] Q_178 = ITOP.iow2.arr[44]; +wire [10:0] Q_179 = ITOP.iow3.arr[44]; +wire [10:0] Q_180 = ITOP.iow0.arr[45]; +wire [10:0] Q_181 = ITOP.iow1.arr[45]; +wire [10:0] Q_182 = ITOP.iow2.arr[45]; +wire [10:0] Q_183 = ITOP.iow3.arr[45]; +wire [10:0] Q_184 = ITOP.iow0.arr[46]; +wire [10:0] Q_185 = ITOP.iow1.arr[46]; +wire [10:0] Q_186 = ITOP.iow2.arr[46]; +wire [10:0] Q_187 = ITOP.iow3.arr[46]; +wire [10:0] Q_188 = ITOP.iow0.arr[47]; +wire [10:0] Q_189 = ITOP.iow1.arr[47]; +wire [10:0] Q_190 = ITOP.iow2.arr[47]; +wire [10:0] Q_191 = ITOP.iow3.arr[47]; +wire [10:0] Q_192 = ITOP.iow0.arr[48]; +wire [10:0] Q_193 = ITOP.iow1.arr[48]; +wire [10:0] Q_194 = ITOP.iow2.arr[48]; +wire [10:0] Q_195 = ITOP.iow3.arr[48]; +wire [10:0] Q_196 = ITOP.iow0.arr[49]; +wire [10:0] Q_197 = ITOP.iow1.arr[49]; +wire [10:0] Q_198 = ITOP.iow2.arr[49]; +wire [10:0] Q_199 = ITOP.iow3.arr[49]; +wire [10:0] Q_200 = ITOP.iow0.arr[50]; +wire [10:0] Q_201 = ITOP.iow1.arr[50]; +wire [10:0] Q_202 = ITOP.iow2.arr[50]; +wire [10:0] Q_203 = ITOP.iow3.arr[50]; +wire [10:0] Q_204 = ITOP.iow0.arr[51]; +wire [10:0] Q_205 = ITOP.iow1.arr[51]; +wire [10:0] Q_206 = ITOP.iow2.arr[51]; +wire [10:0] Q_207 = ITOP.iow3.arr[51]; +wire [10:0] Q_208 = ITOP.iow0.arr[52]; +wire [10:0] Q_209 = ITOP.iow1.arr[52]; +wire [10:0] Q_210 = ITOP.iow2.arr[52]; +wire [10:0] Q_211 = ITOP.iow3.arr[52]; +wire [10:0] Q_212 = ITOP.iow0.arr[53]; +wire [10:0] Q_213 = ITOP.iow1.arr[53]; +wire [10:0] Q_214 = ITOP.iow2.arr[53]; +wire [10:0] Q_215 = ITOP.iow3.arr[53]; +wire [10:0] Q_216 = ITOP.iow0.arr[54]; +wire [10:0] Q_217 = ITOP.iow1.arr[54]; +wire [10:0] Q_218 = ITOP.iow2.arr[54]; +wire [10:0] Q_219 = ITOP.iow3.arr[54]; +wire [10:0] Q_220 = ITOP.iow0.arr[55]; +wire [10:0] Q_221 = ITOP.iow1.arr[55]; +wire [10:0] Q_222 = ITOP.iow2.arr[55]; +wire [10:0] Q_223 = ITOP.iow3.arr[55]; +wire [10:0] Q_224 = ITOP.iow0.arr[56]; +wire [10:0] Q_225 = ITOP.iow1.arr[56]; +wire [10:0] Q_226 = ITOP.iow2.arr[56]; +wire [10:0] Q_227 = ITOP.iow3.arr[56]; +wire [10:0] Q_228 = ITOP.iow0.arr[57]; +wire [10:0] Q_229 = ITOP.iow1.arr[57]; +wire [10:0] Q_230 = ITOP.iow2.arr[57]; +wire [10:0] Q_231 = ITOP.iow3.arr[57]; +wire [10:0] Q_232 = ITOP.iow0.arr[58]; +wire [10:0] Q_233 = ITOP.iow1.arr[58]; +wire [10:0] Q_234 = ITOP.iow2.arr[58]; +wire [10:0] Q_235 = ITOP.iow3.arr[58]; +wire [10:0] Q_236 = ITOP.iow0.arr[59]; +wire [10:0] Q_237 = ITOP.iow1.arr[59]; +wire [10:0] Q_238 = ITOP.iow2.arr[59]; +wire [10:0] Q_239 = ITOP.iow3.arr[59]; +wire [10:0] Q_240 = ITOP.iow0.arr[60]; +wire [10:0] Q_241 = ITOP.iow1.arr[60]; +wire [10:0] Q_242 = ITOP.iow2.arr[60]; +wire [10:0] Q_243 = ITOP.iow3.arr[60]; +wire [10:0] Q_244 = ITOP.iow0.arr[61]; +wire [10:0] Q_245 = ITOP.iow1.arr[61]; +wire [10:0] Q_246 = ITOP.iow2.arr[61]; +wire [10:0] Q_247 = ITOP.iow3.arr[61]; +wire [10:0] Q_248 = ITOP.iow0.arr[62]; +wire [10:0] Q_249 = ITOP.iow1.arr[62]; +wire [10:0] Q_250 = ITOP.iow2.arr[62]; +wire [10:0] Q_251 = ITOP.iow3.arr[62]; +wire [10:0] Q_252 = ITOP.iow0.arr[63]; +wire [10:0] Q_253 = ITOP.iow1.arr[63]; +wire [10:0] Q_254 = ITOP.iow2.arr[63]; +wire [10:0] Q_255 = ITOP.iow3.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [10:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [10:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [10:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [10:0] WD_FF; + reg [10:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [10:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [10:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [10:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X11_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [10:0] WD; +input [8:0] RA, WA; +output [10:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [10:0] WDQ; + wire [10:0] WDBQ; + wire [10:0] WMNexp; + wire [10:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [10:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {11{1'b0}}; + assign SHFT = {11{1'b1}}; + reg [10:0] WDQ_pr; + wire [10:0] WDBQ_pr; + assign WMNexp = {11{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[10:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [10:0] dout; + wire [10:0] RD; + wire RD_rdnt; + wire [10:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [10:0] RDBYPASS = {11{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 256 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[8:8]); +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [10:0] force_x; +`ifndef SYNTHESIS + assign force_x = {11{1'bx}}; +`else + assign force_x = {11{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [10:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [10:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {11{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {11{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {11{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {11{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {11{RdClk0}} & ~dout0; + assign rmuxd1 = {11{RdClk1}} & ~dout1; + assign rmuxd2 = {11{RdClk2}} & ~dout2; + assign rmuxd3 = {11{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[10:0] <= (rmuxd0[10:0] | rmuxd1[10:0] | rmuxd2[10:0] | rmuxd3[10:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_256X11_GL_M4_D2_ram # (64, 11, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [10:0] data; + reg [10:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[7:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[7:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[7:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[7:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [10:0] mem_read_bank; +input [7:0] addr; +reg [10:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[7:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[7:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X11_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 11; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [143:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [143:0] val; + integer i; + begin + val = {144{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [143:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [144-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {144 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {144 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 144'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 144'bx; + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [143:0] wr[1:0]; + integer i; + begin + for (i=0; i<=143; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [143:0] Q_0 = ITOP.iow0.arr[0]; +wire [143:0] Q_1 = ITOP.iow1.arr[0]; +wire [143:0] Q_2 = ITOP.iow0.arr[1]; +wire [143:0] Q_3 = ITOP.iow1.arr[1]; +wire [143:0] Q_4 = ITOP.iow0.arr[2]; +wire [143:0] Q_5 = ITOP.iow1.arr[2]; +wire [143:0] Q_6 = ITOP.iow0.arr[3]; +wire [143:0] Q_7 = ITOP.iow1.arr[3]; +wire [143:0] Q_8 = ITOP.iow0.arr[4]; +wire [143:0] Q_9 = ITOP.iow1.arr[4]; +wire [143:0] Q_10 = ITOP.iow0.arr[5]; +wire [143:0] Q_11 = ITOP.iow1.arr[5]; +wire [143:0] Q_12 = ITOP.iow0.arr[6]; +wire [143:0] Q_13 = ITOP.iow1.arr[6]; +wire [143:0] Q_14 = ITOP.iow0.arr[7]; +wire [143:0] Q_15 = ITOP.iow1.arr[7]; +wire [143:0] Q_16 = ITOP.iow0.arr[8]; +wire [143:0] Q_17 = ITOP.iow1.arr[8]; +wire [143:0] Q_18 = ITOP.iow0.arr[9]; +wire [143:0] Q_19 = ITOP.iow1.arr[9]; +wire [143:0] Q_20 = ITOP.iow0.arr[10]; +wire [143:0] Q_21 = ITOP.iow1.arr[10]; +wire [143:0] Q_22 = ITOP.iow0.arr[11]; +wire [143:0] Q_23 = ITOP.iow1.arr[11]; +wire [143:0] Q_24 = ITOP.iow0.arr[12]; +wire [143:0] Q_25 = ITOP.iow1.arr[12]; +wire [143:0] Q_26 = ITOP.iow0.arr[13]; +wire [143:0] Q_27 = ITOP.iow1.arr[13]; +wire [143:0] Q_28 = ITOP.iow0.arr[14]; +wire [143:0] Q_29 = ITOP.iow1.arr[14]; +wire [143:0] Q_30 = ITOP.iow0.arr[15]; +wire [143:0] Q_31 = ITOP.iow1.arr[15]; +wire [143:0] Q_32 = ITOP.iow0.arr[16]; +wire [143:0] Q_33 = ITOP.iow1.arr[16]; +wire [143:0] Q_34 = ITOP.iow0.arr[17]; +wire [143:0] Q_35 = ITOP.iow1.arr[17]; +wire [143:0] Q_36 = ITOP.iow0.arr[18]; +wire [143:0] Q_37 = ITOP.iow1.arr[18]; +wire [143:0] Q_38 = ITOP.iow0.arr[19]; +wire [143:0] Q_39 = ITOP.iow1.arr[19]; +wire [143:0] Q_40 = ITOP.iow0.arr[20]; +wire [143:0] Q_41 = ITOP.iow1.arr[20]; +wire [143:0] Q_42 = ITOP.iow0.arr[21]; +wire [143:0] Q_43 = ITOP.iow1.arr[21]; +wire [143:0] Q_44 = ITOP.iow0.arr[22]; +wire [143:0] Q_45 = ITOP.iow1.arr[22]; +wire [143:0] Q_46 = ITOP.iow0.arr[23]; +wire [143:0] Q_47 = ITOP.iow1.arr[23]; +wire [143:0] Q_48 = ITOP.iow0.arr[24]; +wire [143:0] Q_49 = ITOP.iow1.arr[24]; +wire [143:0] Q_50 = ITOP.iow0.arr[25]; +wire [143:0] Q_51 = ITOP.iow1.arr[25]; +wire [143:0] Q_52 = ITOP.iow0.arr[26]; +wire [143:0] Q_53 = ITOP.iow1.arr[26]; +wire [143:0] Q_54 = ITOP.iow0.arr[27]; +wire [143:0] Q_55 = ITOP.iow1.arr[27]; +wire [143:0] Q_56 = ITOP.iow0.arr[28]; +wire [143:0] Q_57 = ITOP.iow1.arr[28]; +wire [143:0] Q_58 = ITOP.iow0.arr[29]; +wire [143:0] Q_59 = ITOP.iow1.arr[29]; +wire [143:0] Q_60 = ITOP.iow0.arr[30]; +wire [143:0] Q_61 = ITOP.iow1.arr[30]; +wire [143:0] Q_62 = ITOP.iow0.arr[31]; +wire [143:0] Q_63 = ITOP.iow1.arr[31]; +wire [143:0] Q_64 = ITOP.iow0.arr[32]; +wire [143:0] Q_65 = ITOP.iow1.arr[32]; +wire [143:0] Q_66 = ITOP.iow0.arr[33]; +wire [143:0] Q_67 = ITOP.iow1.arr[33]; +wire [143:0] Q_68 = ITOP.iow0.arr[34]; +wire [143:0] Q_69 = ITOP.iow1.arr[34]; +wire [143:0] Q_70 = ITOP.iow0.arr[35]; +wire [143:0] Q_71 = ITOP.iow1.arr[35]; +wire [143:0] Q_72 = ITOP.iow0.arr[36]; +wire [143:0] Q_73 = ITOP.iow1.arr[36]; +wire [143:0] Q_74 = ITOP.iow0.arr[37]; +wire [143:0] Q_75 = ITOP.iow1.arr[37]; +wire [143:0] Q_76 = ITOP.iow0.arr[38]; +wire [143:0] Q_77 = ITOP.iow1.arr[38]; +wire [143:0] Q_78 = ITOP.iow0.arr[39]; +wire [143:0] Q_79 = ITOP.iow1.arr[39]; +wire [143:0] Q_80 = ITOP.iow0.arr[40]; +wire [143:0] Q_81 = ITOP.iow1.arr[40]; +wire [143:0] Q_82 = ITOP.iow0.arr[41]; +wire [143:0] Q_83 = ITOP.iow1.arr[41]; +wire [143:0] Q_84 = ITOP.iow0.arr[42]; +wire [143:0] Q_85 = ITOP.iow1.arr[42]; +wire [143:0] Q_86 = ITOP.iow0.arr[43]; +wire [143:0] Q_87 = ITOP.iow1.arr[43]; +wire [143:0] Q_88 = ITOP.iow0.arr[44]; +wire [143:0] Q_89 = ITOP.iow1.arr[44]; +wire [143:0] Q_90 = ITOP.iow0.arr[45]; +wire [143:0] Q_91 = ITOP.iow1.arr[45]; +wire [143:0] Q_92 = ITOP.iow0.arr[46]; +wire [143:0] Q_93 = ITOP.iow1.arr[46]; +wire [143:0] Q_94 = ITOP.iow0.arr[47]; +wire [143:0] Q_95 = ITOP.iow1.arr[47]; +wire [143:0] Q_96 = ITOP.iow0.arr[48]; +wire [143:0] Q_97 = ITOP.iow1.arr[48]; +wire [143:0] Q_98 = ITOP.iow0.arr[49]; +wire [143:0] Q_99 = ITOP.iow1.arr[49]; +wire [143:0] Q_100 = ITOP.iow0.arr[50]; +wire [143:0] Q_101 = ITOP.iow1.arr[50]; +wire [143:0] Q_102 = ITOP.iow0.arr[51]; +wire [143:0] Q_103 = ITOP.iow1.arr[51]; +wire [143:0] Q_104 = ITOP.iow0.arr[52]; +wire [143:0] Q_105 = ITOP.iow1.arr[52]; +wire [143:0] Q_106 = ITOP.iow0.arr[53]; +wire [143:0] Q_107 = ITOP.iow1.arr[53]; +wire [143:0] Q_108 = ITOP.iow0.arr[54]; +wire [143:0] Q_109 = ITOP.iow1.arr[54]; +wire [143:0] Q_110 = ITOP.iow0.arr[55]; +wire [143:0] Q_111 = ITOP.iow1.arr[55]; +wire [143:0] Q_112 = ITOP.iow0.arr[56]; +wire [143:0] Q_113 = ITOP.iow1.arr[56]; +wire [143:0] Q_114 = ITOP.iow0.arr[57]; +wire [143:0] Q_115 = ITOP.iow1.arr[57]; +wire [143:0] Q_116 = ITOP.iow0.arr[58]; +wire [143:0] Q_117 = ITOP.iow1.arr[58]; +wire [143:0] Q_118 = ITOP.iow0.arr[59]; +wire [143:0] Q_119 = ITOP.iow1.arr[59]; +wire [143:0] Q_120 = ITOP.iow0.arr[60]; +wire [143:0] Q_121 = ITOP.iow1.arr[60]; +wire [143:0] Q_122 = ITOP.iow0.arr[61]; +wire [143:0] Q_123 = ITOP.iow1.arr[61]; +wire [143:0] Q_124 = ITOP.iow0.arr[62]; +wire [143:0] Q_125 = ITOP.iow1.arr[62]; +wire [143:0] Q_126 = ITOP.iow0.arr[63]; +wire [143:0] Q_127 = ITOP.iow1.arr[63]; +wire [143:0] Q_128 = ITOP.iow0.arr[64]; +wire [143:0] Q_129 = ITOP.iow1.arr[64]; +wire [143:0] Q_130 = ITOP.iow0.arr[65]; +wire [143:0] Q_131 = ITOP.iow1.arr[65]; +wire [143:0] Q_132 = ITOP.iow0.arr[66]; +wire [143:0] Q_133 = ITOP.iow1.arr[66]; +wire [143:0] Q_134 = ITOP.iow0.arr[67]; +wire [143:0] Q_135 = ITOP.iow1.arr[67]; +wire [143:0] Q_136 = ITOP.iow0.arr[68]; +wire [143:0] Q_137 = ITOP.iow1.arr[68]; +wire [143:0] Q_138 = ITOP.iow0.arr[69]; +wire [143:0] Q_139 = ITOP.iow1.arr[69]; +wire [143:0] Q_140 = ITOP.iow0.arr[70]; +wire [143:0] Q_141 = ITOP.iow1.arr[70]; +wire [143:0] Q_142 = ITOP.iow0.arr[71]; +wire [143:0] Q_143 = ITOP.iow1.arr[71]; +wire [143:0] Q_144 = ITOP.iow0.arr[72]; +wire [143:0] Q_145 = ITOP.iow1.arr[72]; +wire [143:0] Q_146 = ITOP.iow0.arr[73]; +wire [143:0] Q_147 = ITOP.iow1.arr[73]; +wire [143:0] Q_148 = ITOP.iow0.arr[74]; +wire [143:0] Q_149 = ITOP.iow1.arr[74]; +wire [143:0] Q_150 = ITOP.iow0.arr[75]; +wire [143:0] Q_151 = ITOP.iow1.arr[75]; +wire [143:0] Q_152 = ITOP.iow0.arr[76]; +wire [143:0] Q_153 = ITOP.iow1.arr[76]; +wire [143:0] Q_154 = ITOP.iow0.arr[77]; +wire [143:0] Q_155 = ITOP.iow1.arr[77]; +wire [143:0] Q_156 = ITOP.iow0.arr[78]; +wire [143:0] Q_157 = ITOP.iow1.arr[78]; +wire [143:0] Q_158 = ITOP.iow0.arr[79]; +wire [143:0] Q_159 = ITOP.iow1.arr[79]; +wire [143:0] Q_160 = ITOP.iow0.arr[80]; +wire [143:0] Q_161 = ITOP.iow1.arr[80]; +wire [143:0] Q_162 = ITOP.iow0.arr[81]; +wire [143:0] Q_163 = ITOP.iow1.arr[81]; +wire [143:0] Q_164 = ITOP.iow0.arr[82]; +wire [143:0] Q_165 = ITOP.iow1.arr[82]; +wire [143:0] Q_166 = ITOP.iow0.arr[83]; +wire [143:0] Q_167 = ITOP.iow1.arr[83]; +wire [143:0] Q_168 = ITOP.iow0.arr[84]; +wire [143:0] Q_169 = ITOP.iow1.arr[84]; +wire [143:0] Q_170 = ITOP.iow0.arr[85]; +wire [143:0] Q_171 = ITOP.iow1.arr[85]; +wire [143:0] Q_172 = ITOP.iow0.arr[86]; +wire [143:0] Q_173 = ITOP.iow1.arr[86]; +wire [143:0] Q_174 = ITOP.iow0.arr[87]; +wire [143:0] Q_175 = ITOP.iow1.arr[87]; +wire [143:0] Q_176 = ITOP.iow0.arr[88]; +wire [143:0] Q_177 = ITOP.iow1.arr[88]; +wire [143:0] Q_178 = ITOP.iow0.arr[89]; +wire [143:0] Q_179 = ITOP.iow1.arr[89]; +wire [143:0] Q_180 = ITOP.iow0.arr[90]; +wire [143:0] Q_181 = ITOP.iow1.arr[90]; +wire [143:0] Q_182 = ITOP.iow0.arr[91]; +wire [143:0] Q_183 = ITOP.iow1.arr[91]; +wire [143:0] Q_184 = ITOP.iow0.arr[92]; +wire [143:0] Q_185 = ITOP.iow1.arr[92]; +wire [143:0] Q_186 = ITOP.iow0.arr[93]; +wire [143:0] Q_187 = ITOP.iow1.arr[93]; +wire [143:0] Q_188 = ITOP.iow0.arr[94]; +wire [143:0] Q_189 = ITOP.iow1.arr[94]; +wire [143:0] Q_190 = ITOP.iow0.arr[95]; +wire [143:0] Q_191 = ITOP.iow1.arr[95]; +wire [143:0] Q_192 = ITOP.iow0.arr[96]; +wire [143:0] Q_193 = ITOP.iow1.arr[96]; +wire [143:0] Q_194 = ITOP.iow0.arr[97]; +wire [143:0] Q_195 = ITOP.iow1.arr[97]; +wire [143:0] Q_196 = ITOP.iow0.arr[98]; +wire [143:0] Q_197 = ITOP.iow1.arr[98]; +wire [143:0] Q_198 = ITOP.iow0.arr[99]; +wire [143:0] Q_199 = ITOP.iow1.arr[99]; +wire [143:0] Q_200 = ITOP.iow0.arr[100]; +wire [143:0] Q_201 = ITOP.iow1.arr[100]; +wire [143:0] Q_202 = ITOP.iow0.arr[101]; +wire [143:0] Q_203 = ITOP.iow1.arr[101]; +wire [143:0] Q_204 = ITOP.iow0.arr[102]; +wire [143:0] Q_205 = ITOP.iow1.arr[102]; +wire [143:0] Q_206 = ITOP.iow0.arr[103]; +wire [143:0] Q_207 = ITOP.iow1.arr[103]; +wire [143:0] Q_208 = ITOP.iow0.arr[104]; +wire [143:0] Q_209 = ITOP.iow1.arr[104]; +wire [143:0] Q_210 = ITOP.iow0.arr[105]; +wire [143:0] Q_211 = ITOP.iow1.arr[105]; +wire [143:0] Q_212 = ITOP.iow0.arr[106]; +wire [143:0] Q_213 = ITOP.iow1.arr[106]; +wire [143:0] Q_214 = ITOP.iow0.arr[107]; +wire [143:0] Q_215 = ITOP.iow1.arr[107]; +wire [143:0] Q_216 = ITOP.iow0.arr[108]; +wire [143:0] Q_217 = ITOP.iow1.arr[108]; +wire [143:0] Q_218 = ITOP.iow0.arr[109]; +wire [143:0] Q_219 = ITOP.iow1.arr[109]; +wire [143:0] Q_220 = ITOP.iow0.arr[110]; +wire [143:0] Q_221 = ITOP.iow1.arr[110]; +wire [143:0] Q_222 = ITOP.iow0.arr[111]; +wire [143:0] Q_223 = ITOP.iow1.arr[111]; +wire [143:0] Q_224 = ITOP.iow0.arr[112]; +wire [143:0] Q_225 = ITOP.iow1.arr[112]; +wire [143:0] Q_226 = ITOP.iow0.arr[113]; +wire [143:0] Q_227 = ITOP.iow1.arr[113]; +wire [143:0] Q_228 = ITOP.iow0.arr[114]; +wire [143:0] Q_229 = ITOP.iow1.arr[114]; +wire [143:0] Q_230 = ITOP.iow0.arr[115]; +wire [143:0] Q_231 = ITOP.iow1.arr[115]; +wire [143:0] Q_232 = ITOP.iow0.arr[116]; +wire [143:0] Q_233 = ITOP.iow1.arr[116]; +wire [143:0] Q_234 = ITOP.iow0.arr[117]; +wire [143:0] Q_235 = ITOP.iow1.arr[117]; +wire [143:0] Q_236 = ITOP.iow0.arr[118]; +wire [143:0] Q_237 = ITOP.iow1.arr[118]; +wire [143:0] Q_238 = ITOP.iow0.arr[119]; +wire [143:0] Q_239 = ITOP.iow1.arr[119]; +wire [143:0] Q_240 = ITOP.iow0.arr[120]; +wire [143:0] Q_241 = ITOP.iow1.arr[120]; +wire [143:0] Q_242 = ITOP.iow0.arr[121]; +wire [143:0] Q_243 = ITOP.iow1.arr[121]; +wire [143:0] Q_244 = ITOP.iow0.arr[122]; +wire [143:0] Q_245 = ITOP.iow1.arr[122]; +wire [143:0] Q_246 = ITOP.iow0.arr[123]; +wire [143:0] Q_247 = ITOP.iow1.arr[123]; +wire [143:0] Q_248 = ITOP.iow0.arr[124]; +wire [143:0] Q_249 = ITOP.iow1.arr[124]; +wire [143:0] Q_250 = ITOP.iow0.arr[125]; +wire [143:0] Q_251 = ITOP.iow1.arr[125]; +wire [143:0] Q_252 = ITOP.iow0.arr[126]; +wire [143:0] Q_253 = ITOP.iow1.arr[126]; +wire [143:0] Q_254 = ITOP.iow0.arr[127]; +wire [143:0] Q_255 = ITOP.iow1.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [143:0] WD_FF; + reg [143:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [143:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [143:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [143:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X144_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [143:0] WD; +input [7:0] RA, WA; +output [143:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [143:0] WDQ; + wire [143:0] WDBQ; + wire [143:0] WMNexp; + wire [143:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [143:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {144{1'b0}}; + assign SHFT = {144{1'b1}}; + reg [143:0] WDQ_pr; + wire [143:0] WDBQ_pr; + assign WMNexp = {144{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[143:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [143:0] dout; + wire [143:0] RD; + wire RD_rdnt; + wire [143:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [143:0] RDBYPASS = {144{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [143:0] force_x; +`ifndef SYNTHESIS + assign force_x = {144{1'bx}}; +`else + assign force_x = {144{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [143:0] rmuxd0, rmuxd1; + wire [143:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {144{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {144{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {144{RdClk0}} & ~dout0 ; + assign rmuxd1 = {144{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[143:0] <= (rmuxd0[143:0] | rmuxd1[143:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X144_GL_M2_D2_ram # (128, 144, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_256X144_GL_M2_D2_ram # (128, 144, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [143:0] data; + reg [143:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [143:0] mem_read_bank; +input [7:0] addr; +reg [143:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X144_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 144; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [143:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [143:0] val; + integer i; + begin + val = {144{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [143:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [144-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {144 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {144 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [143:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 144'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 144'bx; + for (i=0; i<=143; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [143:0] wr[1:0]; + integer i; + begin + for (i=0; i<=143; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [143:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=143; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [143:0] Q_0 = ITOP.iow0.arr[0]; +wire [143:0] Q_1 = ITOP.iow1.arr[0]; +wire [143:0] Q_2 = ITOP.iow0.arr[1]; +wire [143:0] Q_3 = ITOP.iow1.arr[1]; +wire [143:0] Q_4 = ITOP.iow0.arr[2]; +wire [143:0] Q_5 = ITOP.iow1.arr[2]; +wire [143:0] Q_6 = ITOP.iow0.arr[3]; +wire [143:0] Q_7 = ITOP.iow1.arr[3]; +wire [143:0] Q_8 = ITOP.iow0.arr[4]; +wire [143:0] Q_9 = ITOP.iow1.arr[4]; +wire [143:0] Q_10 = ITOP.iow0.arr[5]; +wire [143:0] Q_11 = ITOP.iow1.arr[5]; +wire [143:0] Q_12 = ITOP.iow0.arr[6]; +wire [143:0] Q_13 = ITOP.iow1.arr[6]; +wire [143:0] Q_14 = ITOP.iow0.arr[7]; +wire [143:0] Q_15 = ITOP.iow1.arr[7]; +wire [143:0] Q_16 = ITOP.iow0.arr[8]; +wire [143:0] Q_17 = ITOP.iow1.arr[8]; +wire [143:0] Q_18 = ITOP.iow0.arr[9]; +wire [143:0] Q_19 = ITOP.iow1.arr[9]; +wire [143:0] Q_20 = ITOP.iow0.arr[10]; +wire [143:0] Q_21 = ITOP.iow1.arr[10]; +wire [143:0] Q_22 = ITOP.iow0.arr[11]; +wire [143:0] Q_23 = ITOP.iow1.arr[11]; +wire [143:0] Q_24 = ITOP.iow0.arr[12]; +wire [143:0] Q_25 = ITOP.iow1.arr[12]; +wire [143:0] Q_26 = ITOP.iow0.arr[13]; +wire [143:0] Q_27 = ITOP.iow1.arr[13]; +wire [143:0] Q_28 = ITOP.iow0.arr[14]; +wire [143:0] Q_29 = ITOP.iow1.arr[14]; +wire [143:0] Q_30 = ITOP.iow0.arr[15]; +wire [143:0] Q_31 = ITOP.iow1.arr[15]; +wire [143:0] Q_32 = ITOP.iow0.arr[16]; +wire [143:0] Q_33 = ITOP.iow1.arr[16]; +wire [143:0] Q_34 = ITOP.iow0.arr[17]; +wire [143:0] Q_35 = ITOP.iow1.arr[17]; +wire [143:0] Q_36 = ITOP.iow0.arr[18]; +wire [143:0] Q_37 = ITOP.iow1.arr[18]; +wire [143:0] Q_38 = ITOP.iow0.arr[19]; +wire [143:0] Q_39 = ITOP.iow1.arr[19]; +wire [143:0] Q_40 = ITOP.iow0.arr[20]; +wire [143:0] Q_41 = ITOP.iow1.arr[20]; +wire [143:0] Q_42 = ITOP.iow0.arr[21]; +wire [143:0] Q_43 = ITOP.iow1.arr[21]; +wire [143:0] Q_44 = ITOP.iow0.arr[22]; +wire [143:0] Q_45 = ITOP.iow1.arr[22]; +wire [143:0] Q_46 = ITOP.iow0.arr[23]; +wire [143:0] Q_47 = ITOP.iow1.arr[23]; +wire [143:0] Q_48 = ITOP.iow0.arr[24]; +wire [143:0] Q_49 = ITOP.iow1.arr[24]; +wire [143:0] Q_50 = ITOP.iow0.arr[25]; +wire [143:0] Q_51 = ITOP.iow1.arr[25]; +wire [143:0] Q_52 = ITOP.iow0.arr[26]; +wire [143:0] Q_53 = ITOP.iow1.arr[26]; +wire [143:0] Q_54 = ITOP.iow0.arr[27]; +wire [143:0] Q_55 = ITOP.iow1.arr[27]; +wire [143:0] Q_56 = ITOP.iow0.arr[28]; +wire [143:0] Q_57 = ITOP.iow1.arr[28]; +wire [143:0] Q_58 = ITOP.iow0.arr[29]; +wire [143:0] Q_59 = ITOP.iow1.arr[29]; +wire [143:0] Q_60 = ITOP.iow0.arr[30]; +wire [143:0] Q_61 = ITOP.iow1.arr[30]; +wire [143:0] Q_62 = ITOP.iow0.arr[31]; +wire [143:0] Q_63 = ITOP.iow1.arr[31]; +wire [143:0] Q_64 = ITOP.iow0.arr[32]; +wire [143:0] Q_65 = ITOP.iow1.arr[32]; +wire [143:0] Q_66 = ITOP.iow0.arr[33]; +wire [143:0] Q_67 = ITOP.iow1.arr[33]; +wire [143:0] Q_68 = ITOP.iow0.arr[34]; +wire [143:0] Q_69 = ITOP.iow1.arr[34]; +wire [143:0] Q_70 = ITOP.iow0.arr[35]; +wire [143:0] Q_71 = ITOP.iow1.arr[35]; +wire [143:0] Q_72 = ITOP.iow0.arr[36]; +wire [143:0] Q_73 = ITOP.iow1.arr[36]; +wire [143:0] Q_74 = ITOP.iow0.arr[37]; +wire [143:0] Q_75 = ITOP.iow1.arr[37]; +wire [143:0] Q_76 = ITOP.iow0.arr[38]; +wire [143:0] Q_77 = ITOP.iow1.arr[38]; +wire [143:0] Q_78 = ITOP.iow0.arr[39]; +wire [143:0] Q_79 = ITOP.iow1.arr[39]; +wire [143:0] Q_80 = ITOP.iow0.arr[40]; +wire [143:0] Q_81 = ITOP.iow1.arr[40]; +wire [143:0] Q_82 = ITOP.iow0.arr[41]; +wire [143:0] Q_83 = ITOP.iow1.arr[41]; +wire [143:0] Q_84 = ITOP.iow0.arr[42]; +wire [143:0] Q_85 = ITOP.iow1.arr[42]; +wire [143:0] Q_86 = ITOP.iow0.arr[43]; +wire [143:0] Q_87 = ITOP.iow1.arr[43]; +wire [143:0] Q_88 = ITOP.iow0.arr[44]; +wire [143:0] Q_89 = ITOP.iow1.arr[44]; +wire [143:0] Q_90 = ITOP.iow0.arr[45]; +wire [143:0] Q_91 = ITOP.iow1.arr[45]; +wire [143:0] Q_92 = ITOP.iow0.arr[46]; +wire [143:0] Q_93 = ITOP.iow1.arr[46]; +wire [143:0] Q_94 = ITOP.iow0.arr[47]; +wire [143:0] Q_95 = ITOP.iow1.arr[47]; +wire [143:0] Q_96 = ITOP.iow0.arr[48]; +wire [143:0] Q_97 = ITOP.iow1.arr[48]; +wire [143:0] Q_98 = ITOP.iow0.arr[49]; +wire [143:0] Q_99 = ITOP.iow1.arr[49]; +wire [143:0] Q_100 = ITOP.iow0.arr[50]; +wire [143:0] Q_101 = ITOP.iow1.arr[50]; +wire [143:0] Q_102 = ITOP.iow0.arr[51]; +wire [143:0] Q_103 = ITOP.iow1.arr[51]; +wire [143:0] Q_104 = ITOP.iow0.arr[52]; +wire [143:0] Q_105 = ITOP.iow1.arr[52]; +wire [143:0] Q_106 = ITOP.iow0.arr[53]; +wire [143:0] Q_107 = ITOP.iow1.arr[53]; +wire [143:0] Q_108 = ITOP.iow0.arr[54]; +wire [143:0] Q_109 = ITOP.iow1.arr[54]; +wire [143:0] Q_110 = ITOP.iow0.arr[55]; +wire [143:0] Q_111 = ITOP.iow1.arr[55]; +wire [143:0] Q_112 = ITOP.iow0.arr[56]; +wire [143:0] Q_113 = ITOP.iow1.arr[56]; +wire [143:0] Q_114 = ITOP.iow0.arr[57]; +wire [143:0] Q_115 = ITOP.iow1.arr[57]; +wire [143:0] Q_116 = ITOP.iow0.arr[58]; +wire [143:0] Q_117 = ITOP.iow1.arr[58]; +wire [143:0] Q_118 = ITOP.iow0.arr[59]; +wire [143:0] Q_119 = ITOP.iow1.arr[59]; +wire [143:0] Q_120 = ITOP.iow0.arr[60]; +wire [143:0] Q_121 = ITOP.iow1.arr[60]; +wire [143:0] Q_122 = ITOP.iow0.arr[61]; +wire [143:0] Q_123 = ITOP.iow1.arr[61]; +wire [143:0] Q_124 = ITOP.iow0.arr[62]; +wire [143:0] Q_125 = ITOP.iow1.arr[62]; +wire [143:0] Q_126 = ITOP.iow0.arr[63]; +wire [143:0] Q_127 = ITOP.iow1.arr[63]; +wire [143:0] Q_128 = ITOP.iow0.arr[64]; +wire [143:0] Q_129 = ITOP.iow1.arr[64]; +wire [143:0] Q_130 = ITOP.iow0.arr[65]; +wire [143:0] Q_131 = ITOP.iow1.arr[65]; +wire [143:0] Q_132 = ITOP.iow0.arr[66]; +wire [143:0] Q_133 = ITOP.iow1.arr[66]; +wire [143:0] Q_134 = ITOP.iow0.arr[67]; +wire [143:0] Q_135 = ITOP.iow1.arr[67]; +wire [143:0] Q_136 = ITOP.iow0.arr[68]; +wire [143:0] Q_137 = ITOP.iow1.arr[68]; +wire [143:0] Q_138 = ITOP.iow0.arr[69]; +wire [143:0] Q_139 = ITOP.iow1.arr[69]; +wire [143:0] Q_140 = ITOP.iow0.arr[70]; +wire [143:0] Q_141 = ITOP.iow1.arr[70]; +wire [143:0] Q_142 = ITOP.iow0.arr[71]; +wire [143:0] Q_143 = ITOP.iow1.arr[71]; +wire [143:0] Q_144 = ITOP.iow0.arr[72]; +wire [143:0] Q_145 = ITOP.iow1.arr[72]; +wire [143:0] Q_146 = ITOP.iow0.arr[73]; +wire [143:0] Q_147 = ITOP.iow1.arr[73]; +wire [143:0] Q_148 = ITOP.iow0.arr[74]; +wire [143:0] Q_149 = ITOP.iow1.arr[74]; +wire [143:0] Q_150 = ITOP.iow0.arr[75]; +wire [143:0] Q_151 = ITOP.iow1.arr[75]; +wire [143:0] Q_152 = ITOP.iow0.arr[76]; +wire [143:0] Q_153 = ITOP.iow1.arr[76]; +wire [143:0] Q_154 = ITOP.iow0.arr[77]; +wire [143:0] Q_155 = ITOP.iow1.arr[77]; +wire [143:0] Q_156 = ITOP.iow0.arr[78]; +wire [143:0] Q_157 = ITOP.iow1.arr[78]; +wire [143:0] Q_158 = ITOP.iow0.arr[79]; +wire [143:0] Q_159 = ITOP.iow1.arr[79]; +wire [143:0] Q_160 = ITOP.iow0.arr[80]; +wire [143:0] Q_161 = ITOP.iow1.arr[80]; +wire [143:0] Q_162 = ITOP.iow0.arr[81]; +wire [143:0] Q_163 = ITOP.iow1.arr[81]; +wire [143:0] Q_164 = ITOP.iow0.arr[82]; +wire [143:0] Q_165 = ITOP.iow1.arr[82]; +wire [143:0] Q_166 = ITOP.iow0.arr[83]; +wire [143:0] Q_167 = ITOP.iow1.arr[83]; +wire [143:0] Q_168 = ITOP.iow0.arr[84]; +wire [143:0] Q_169 = ITOP.iow1.arr[84]; +wire [143:0] Q_170 = ITOP.iow0.arr[85]; +wire [143:0] Q_171 = ITOP.iow1.arr[85]; +wire [143:0] Q_172 = ITOP.iow0.arr[86]; +wire [143:0] Q_173 = ITOP.iow1.arr[86]; +wire [143:0] Q_174 = ITOP.iow0.arr[87]; +wire [143:0] Q_175 = ITOP.iow1.arr[87]; +wire [143:0] Q_176 = ITOP.iow0.arr[88]; +wire [143:0] Q_177 = ITOP.iow1.arr[88]; +wire [143:0] Q_178 = ITOP.iow0.arr[89]; +wire [143:0] Q_179 = ITOP.iow1.arr[89]; +wire [143:0] Q_180 = ITOP.iow0.arr[90]; +wire [143:0] Q_181 = ITOP.iow1.arr[90]; +wire [143:0] Q_182 = ITOP.iow0.arr[91]; +wire [143:0] Q_183 = ITOP.iow1.arr[91]; +wire [143:0] Q_184 = ITOP.iow0.arr[92]; +wire [143:0] Q_185 = ITOP.iow1.arr[92]; +wire [143:0] Q_186 = ITOP.iow0.arr[93]; +wire [143:0] Q_187 = ITOP.iow1.arr[93]; +wire [143:0] Q_188 = ITOP.iow0.arr[94]; +wire [143:0] Q_189 = ITOP.iow1.arr[94]; +wire [143:0] Q_190 = ITOP.iow0.arr[95]; +wire [143:0] Q_191 = ITOP.iow1.arr[95]; +wire [143:0] Q_192 = ITOP.iow0.arr[96]; +wire [143:0] Q_193 = ITOP.iow1.arr[96]; +wire [143:0] Q_194 = ITOP.iow0.arr[97]; +wire [143:0] Q_195 = ITOP.iow1.arr[97]; +wire [143:0] Q_196 = ITOP.iow0.arr[98]; +wire [143:0] Q_197 = ITOP.iow1.arr[98]; +wire [143:0] Q_198 = ITOP.iow0.arr[99]; +wire [143:0] Q_199 = ITOP.iow1.arr[99]; +wire [143:0] Q_200 = ITOP.iow0.arr[100]; +wire [143:0] Q_201 = ITOP.iow1.arr[100]; +wire [143:0] Q_202 = ITOP.iow0.arr[101]; +wire [143:0] Q_203 = ITOP.iow1.arr[101]; +wire [143:0] Q_204 = ITOP.iow0.arr[102]; +wire [143:0] Q_205 = ITOP.iow1.arr[102]; +wire [143:0] Q_206 = ITOP.iow0.arr[103]; +wire [143:0] Q_207 = ITOP.iow1.arr[103]; +wire [143:0] Q_208 = ITOP.iow0.arr[104]; +wire [143:0] Q_209 = ITOP.iow1.arr[104]; +wire [143:0] Q_210 = ITOP.iow0.arr[105]; +wire [143:0] Q_211 = ITOP.iow1.arr[105]; +wire [143:0] Q_212 = ITOP.iow0.arr[106]; +wire [143:0] Q_213 = ITOP.iow1.arr[106]; +wire [143:0] Q_214 = ITOP.iow0.arr[107]; +wire [143:0] Q_215 = ITOP.iow1.arr[107]; +wire [143:0] Q_216 = ITOP.iow0.arr[108]; +wire [143:0] Q_217 = ITOP.iow1.arr[108]; +wire [143:0] Q_218 = ITOP.iow0.arr[109]; +wire [143:0] Q_219 = ITOP.iow1.arr[109]; +wire [143:0] Q_220 = ITOP.iow0.arr[110]; +wire [143:0] Q_221 = ITOP.iow1.arr[110]; +wire [143:0] Q_222 = ITOP.iow0.arr[111]; +wire [143:0] Q_223 = ITOP.iow1.arr[111]; +wire [143:0] Q_224 = ITOP.iow0.arr[112]; +wire [143:0] Q_225 = ITOP.iow1.arr[112]; +wire [143:0] Q_226 = ITOP.iow0.arr[113]; +wire [143:0] Q_227 = ITOP.iow1.arr[113]; +wire [143:0] Q_228 = ITOP.iow0.arr[114]; +wire [143:0] Q_229 = ITOP.iow1.arr[114]; +wire [143:0] Q_230 = ITOP.iow0.arr[115]; +wire [143:0] Q_231 = ITOP.iow1.arr[115]; +wire [143:0] Q_232 = ITOP.iow0.arr[116]; +wire [143:0] Q_233 = ITOP.iow1.arr[116]; +wire [143:0] Q_234 = ITOP.iow0.arr[117]; +wire [143:0] Q_235 = ITOP.iow1.arr[117]; +wire [143:0] Q_236 = ITOP.iow0.arr[118]; +wire [143:0] Q_237 = ITOP.iow1.arr[118]; +wire [143:0] Q_238 = ITOP.iow0.arr[119]; +wire [143:0] Q_239 = ITOP.iow1.arr[119]; +wire [143:0] Q_240 = ITOP.iow0.arr[120]; +wire [143:0] Q_241 = ITOP.iow1.arr[120]; +wire [143:0] Q_242 = ITOP.iow0.arr[121]; +wire [143:0] Q_243 = ITOP.iow1.arr[121]; +wire [143:0] Q_244 = ITOP.iow0.arr[122]; +wire [143:0] Q_245 = ITOP.iow1.arr[122]; +wire [143:0] Q_246 = ITOP.iow0.arr[123]; +wire [143:0] Q_247 = ITOP.iow1.arr[123]; +wire [143:0] Q_248 = ITOP.iow0.arr[124]; +wire [143:0] Q_249 = ITOP.iow1.arr[124]; +wire [143:0] Q_250 = ITOP.iow0.arr[125]; +wire [143:0] Q_251 = ITOP.iow1.arr[125]; +wire [143:0] Q_252 = ITOP.iow0.arr[126]; +wire [143:0] Q_253 = ITOP.iow1.arr[126]; +wire [143:0] Q_254 = ITOP.iow0.arr[127]; +wire [143:0] Q_255 = ITOP.iow1.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [143:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [143:0] WD_FF; + reg [143:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [143:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [143:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [143:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X144_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [143:0] WD; +input [7:0] RA, WA; +output [143:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [143:0] WDQ; + wire [143:0] WDBQ; + wire [143:0] WMNexp; + wire [143:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [143:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {144{1'b0}}; + assign SHFT = {144{1'b1}}; + reg [143:0] WDQ_pr; + wire [143:0] WDBQ_pr; + assign WMNexp = {144{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[143:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [143:0] dout; + wire [143:0] RD; + wire RD_rdnt; + wire [143:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [143:0] RDBYPASS = {144{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [143:0] force_x; +`ifndef SYNTHESIS + assign force_x = {144{1'bx}}; +`else + assign force_x = {144{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [143:0] rmuxd0, rmuxd1; + wire [143:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {144{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {144{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {144{RdClk0}} & ~dout0 ; + assign rmuxd1 = {144{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[143:0] <= (rmuxd0[143:0] | rmuxd1[143:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X144_GL_M2_D2_ram # (128, 144, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_256X144_GL_M2_D2_ram # (128, 144, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [143:0] data; + reg [143:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [143:0] mem_read_bank; +input [7:0] addr; +reg [143:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X144_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 144; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [127:0] mem_phys_read_padr; +input [6:0] addr; + reg [127:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [128-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {128 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {128 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [127:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [127:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [128-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {128 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {128 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [127:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [127:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [128-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {128 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {128 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 64'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 64'bx; + for (i=0; i<=63; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [127:0] data; + reg [63:0] wr[1:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [127:0] mon_bit_w; +input [6:0] addr; + reg [127:0] mon_row; + reg [63:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [127:0] mon_bit_r; +input [6:0] addr; + reg [127:0] mon_row; + reg [63:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [127:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow1.arr[0]; +wire [63:0] Q_2 = ITOP.iow0.arr[1]; +wire [63:0] Q_3 = ITOP.iow1.arr[1]; +wire [63:0] Q_4 = ITOP.iow0.arr[2]; +wire [63:0] Q_5 = ITOP.iow1.arr[2]; +wire [63:0] Q_6 = ITOP.iow0.arr[3]; +wire [63:0] Q_7 = ITOP.iow1.arr[3]; +wire [63:0] Q_8 = ITOP.iow0.arr[4]; +wire [63:0] Q_9 = ITOP.iow1.arr[4]; +wire [63:0] Q_10 = ITOP.iow0.arr[5]; +wire [63:0] Q_11 = ITOP.iow1.arr[5]; +wire [63:0] Q_12 = ITOP.iow0.arr[6]; +wire [63:0] Q_13 = ITOP.iow1.arr[6]; +wire [63:0] Q_14 = ITOP.iow0.arr[7]; +wire [63:0] Q_15 = ITOP.iow1.arr[7]; +wire [63:0] Q_16 = ITOP.iow0.arr[8]; +wire [63:0] Q_17 = ITOP.iow1.arr[8]; +wire [63:0] Q_18 = ITOP.iow0.arr[9]; +wire [63:0] Q_19 = ITOP.iow1.arr[9]; +wire [63:0] Q_20 = ITOP.iow0.arr[10]; +wire [63:0] Q_21 = ITOP.iow1.arr[10]; +wire [63:0] Q_22 = ITOP.iow0.arr[11]; +wire [63:0] Q_23 = ITOP.iow1.arr[11]; +wire [63:0] Q_24 = ITOP.iow0.arr[12]; +wire [63:0] Q_25 = ITOP.iow1.arr[12]; +wire [63:0] Q_26 = ITOP.iow0.arr[13]; +wire [63:0] Q_27 = ITOP.iow1.arr[13]; +wire [63:0] Q_28 = ITOP.iow0.arr[14]; +wire [63:0] Q_29 = ITOP.iow1.arr[14]; +wire [63:0] Q_30 = ITOP.iow0.arr[15]; +wire [63:0] Q_31 = ITOP.iow1.arr[15]; +wire [63:0] Q_32 = ITOP.iow0.arr[16]; +wire [63:0] Q_33 = ITOP.iow1.arr[16]; +wire [63:0] Q_34 = ITOP.iow0.arr[17]; +wire [63:0] Q_35 = ITOP.iow1.arr[17]; +wire [63:0] Q_36 = ITOP.iow0.arr[18]; +wire [63:0] Q_37 = ITOP.iow1.arr[18]; +wire [63:0] Q_38 = ITOP.iow0.arr[19]; +wire [63:0] Q_39 = ITOP.iow1.arr[19]; +wire [63:0] Q_40 = ITOP.iow0.arr[20]; +wire [63:0] Q_41 = ITOP.iow1.arr[20]; +wire [63:0] Q_42 = ITOP.iow0.arr[21]; +wire [63:0] Q_43 = ITOP.iow1.arr[21]; +wire [63:0] Q_44 = ITOP.iow0.arr[22]; +wire [63:0] Q_45 = ITOP.iow1.arr[22]; +wire [63:0] Q_46 = ITOP.iow0.arr[23]; +wire [63:0] Q_47 = ITOP.iow1.arr[23]; +wire [63:0] Q_48 = ITOP.iow0.arr[24]; +wire [63:0] Q_49 = ITOP.iow1.arr[24]; +wire [63:0] Q_50 = ITOP.iow0.arr[25]; +wire [63:0] Q_51 = ITOP.iow1.arr[25]; +wire [63:0] Q_52 = ITOP.iow0.arr[26]; +wire [63:0] Q_53 = ITOP.iow1.arr[26]; +wire [63:0] Q_54 = ITOP.iow0.arr[27]; +wire [63:0] Q_55 = ITOP.iow1.arr[27]; +wire [63:0] Q_56 = ITOP.iow0.arr[28]; +wire [63:0] Q_57 = ITOP.iow1.arr[28]; +wire [63:0] Q_58 = ITOP.iow0.arr[29]; +wire [63:0] Q_59 = ITOP.iow1.arr[29]; +wire [63:0] Q_60 = ITOP.iow0.arr[30]; +wire [63:0] Q_61 = ITOP.iow1.arr[30]; +wire [63:0] Q_62 = ITOP.iow0.arr[31]; +wire [63:0] Q_63 = ITOP.iow1.arr[31]; +wire [63:0] Q_64 = ITOP.iow0.arr[32]; +wire [63:0] Q_65 = ITOP.iow1.arr[32]; +wire [63:0] Q_66 = ITOP.iow0.arr[33]; +wire [63:0] Q_67 = ITOP.iow1.arr[33]; +wire [63:0] Q_68 = ITOP.iow0.arr[34]; +wire [63:0] Q_69 = ITOP.iow1.arr[34]; +wire [63:0] Q_70 = ITOP.iow0.arr[35]; +wire [63:0] Q_71 = ITOP.iow1.arr[35]; +wire [63:0] Q_72 = ITOP.iow0.arr[36]; +wire [63:0] Q_73 = ITOP.iow1.arr[36]; +wire [63:0] Q_74 = ITOP.iow0.arr[37]; +wire [63:0] Q_75 = ITOP.iow1.arr[37]; +wire [63:0] Q_76 = ITOP.iow0.arr[38]; +wire [63:0] Q_77 = ITOP.iow1.arr[38]; +wire [63:0] Q_78 = ITOP.iow0.arr[39]; +wire [63:0] Q_79 = ITOP.iow1.arr[39]; +wire [63:0] Q_80 = ITOP.iow0.arr[40]; +wire [63:0] Q_81 = ITOP.iow1.arr[40]; +wire [63:0] Q_82 = ITOP.iow0.arr[41]; +wire [63:0] Q_83 = ITOP.iow1.arr[41]; +wire [63:0] Q_84 = ITOP.iow0.arr[42]; +wire [63:0] Q_85 = ITOP.iow1.arr[42]; +wire [63:0] Q_86 = ITOP.iow0.arr[43]; +wire [63:0] Q_87 = ITOP.iow1.arr[43]; +wire [63:0] Q_88 = ITOP.iow0.arr[44]; +wire [63:0] Q_89 = ITOP.iow1.arr[44]; +wire [63:0] Q_90 = ITOP.iow0.arr[45]; +wire [63:0] Q_91 = ITOP.iow1.arr[45]; +wire [63:0] Q_92 = ITOP.iow0.arr[46]; +wire [63:0] Q_93 = ITOP.iow1.arr[46]; +wire [63:0] Q_94 = ITOP.iow0.arr[47]; +wire [63:0] Q_95 = ITOP.iow1.arr[47]; +wire [63:0] Q_96 = ITOP.iow0.arr[48]; +wire [63:0] Q_97 = ITOP.iow1.arr[48]; +wire [63:0] Q_98 = ITOP.iow0.arr[49]; +wire [63:0] Q_99 = ITOP.iow1.arr[49]; +wire [63:0] Q_100 = ITOP.iow0.arr[50]; +wire [63:0] Q_101 = ITOP.iow1.arr[50]; +wire [63:0] Q_102 = ITOP.iow0.arr[51]; +wire [63:0] Q_103 = ITOP.iow1.arr[51]; +wire [63:0] Q_104 = ITOP.iow0.arr[52]; +wire [63:0] Q_105 = ITOP.iow1.arr[52]; +wire [63:0] Q_106 = ITOP.iow0.arr[53]; +wire [63:0] Q_107 = ITOP.iow1.arr[53]; +wire [63:0] Q_108 = ITOP.iow0.arr[54]; +wire [63:0] Q_109 = ITOP.iow1.arr[54]; +wire [63:0] Q_110 = ITOP.iow0.arr[55]; +wire [63:0] Q_111 = ITOP.iow1.arr[55]; +wire [63:0] Q_112 = ITOP.iow0.arr[56]; +wire [63:0] Q_113 = ITOP.iow1.arr[56]; +wire [63:0] Q_114 = ITOP.iow0.arr[57]; +wire [63:0] Q_115 = ITOP.iow1.arr[57]; +wire [63:0] Q_116 = ITOP.iow0.arr[58]; +wire [63:0] Q_117 = ITOP.iow1.arr[58]; +wire [63:0] Q_118 = ITOP.iow0.arr[59]; +wire [63:0] Q_119 = ITOP.iow1.arr[59]; +wire [63:0] Q_120 = ITOP.iow0.arr[60]; +wire [63:0] Q_121 = ITOP.iow1.arr[60]; +wire [63:0] Q_122 = ITOP.iow0.arr[61]; +wire [63:0] Q_123 = ITOP.iow1.arr[61]; +wire [63:0] Q_124 = ITOP.iow0.arr[62]; +wire [63:0] Q_125 = ITOP.iow1.arr[62]; +wire [63:0] Q_126 = ITOP.iow0.arr[63]; +wire [63:0] Q_127 = ITOP.iow1.arr[63]; +wire [63:0] Q_128 = ITOP.iow0.arr[64]; +wire [63:0] Q_129 = ITOP.iow1.arr[64]; +wire [63:0] Q_130 = ITOP.iow0.arr[65]; +wire [63:0] Q_131 = ITOP.iow1.arr[65]; +wire [63:0] Q_132 = ITOP.iow0.arr[66]; +wire [63:0] Q_133 = ITOP.iow1.arr[66]; +wire [63:0] Q_134 = ITOP.iow0.arr[67]; +wire [63:0] Q_135 = ITOP.iow1.arr[67]; +wire [63:0] Q_136 = ITOP.iow0.arr[68]; +wire [63:0] Q_137 = ITOP.iow1.arr[68]; +wire [63:0] Q_138 = ITOP.iow0.arr[69]; +wire [63:0] Q_139 = ITOP.iow1.arr[69]; +wire [63:0] Q_140 = ITOP.iow0.arr[70]; +wire [63:0] Q_141 = ITOP.iow1.arr[70]; +wire [63:0] Q_142 = ITOP.iow0.arr[71]; +wire [63:0] Q_143 = ITOP.iow1.arr[71]; +wire [63:0] Q_144 = ITOP.iow0.arr[72]; +wire [63:0] Q_145 = ITOP.iow1.arr[72]; +wire [63:0] Q_146 = ITOP.iow0.arr[73]; +wire [63:0] Q_147 = ITOP.iow1.arr[73]; +wire [63:0] Q_148 = ITOP.iow0.arr[74]; +wire [63:0] Q_149 = ITOP.iow1.arr[74]; +wire [63:0] Q_150 = ITOP.iow0.arr[75]; +wire [63:0] Q_151 = ITOP.iow1.arr[75]; +wire [63:0] Q_152 = ITOP.iow0.arr[76]; +wire [63:0] Q_153 = ITOP.iow1.arr[76]; +wire [63:0] Q_154 = ITOP.iow0.arr[77]; +wire [63:0] Q_155 = ITOP.iow1.arr[77]; +wire [63:0] Q_156 = ITOP.iow0.arr[78]; +wire [63:0] Q_157 = ITOP.iow1.arr[78]; +wire [63:0] Q_158 = ITOP.iow0.arr[79]; +wire [63:0] Q_159 = ITOP.iow1.arr[79]; +wire [63:0] Q_160 = ITOP.iow0.arr[80]; +wire [63:0] Q_161 = ITOP.iow1.arr[80]; +wire [63:0] Q_162 = ITOP.iow0.arr[81]; +wire [63:0] Q_163 = ITOP.iow1.arr[81]; +wire [63:0] Q_164 = ITOP.iow0.arr[82]; +wire [63:0] Q_165 = ITOP.iow1.arr[82]; +wire [63:0] Q_166 = ITOP.iow0.arr[83]; +wire [63:0] Q_167 = ITOP.iow1.arr[83]; +wire [63:0] Q_168 = ITOP.iow0.arr[84]; +wire [63:0] Q_169 = ITOP.iow1.arr[84]; +wire [63:0] Q_170 = ITOP.iow0.arr[85]; +wire [63:0] Q_171 = ITOP.iow1.arr[85]; +wire [63:0] Q_172 = ITOP.iow0.arr[86]; +wire [63:0] Q_173 = ITOP.iow1.arr[86]; +wire [63:0] Q_174 = ITOP.iow0.arr[87]; +wire [63:0] Q_175 = ITOP.iow1.arr[87]; +wire [63:0] Q_176 = ITOP.iow0.arr[88]; +wire [63:0] Q_177 = ITOP.iow1.arr[88]; +wire [63:0] Q_178 = ITOP.iow0.arr[89]; +wire [63:0] Q_179 = ITOP.iow1.arr[89]; +wire [63:0] Q_180 = ITOP.iow0.arr[90]; +wire [63:0] Q_181 = ITOP.iow1.arr[90]; +wire [63:0] Q_182 = ITOP.iow0.arr[91]; +wire [63:0] Q_183 = ITOP.iow1.arr[91]; +wire [63:0] Q_184 = ITOP.iow0.arr[92]; +wire [63:0] Q_185 = ITOP.iow1.arr[92]; +wire [63:0] Q_186 = ITOP.iow0.arr[93]; +wire [63:0] Q_187 = ITOP.iow1.arr[93]; +wire [63:0] Q_188 = ITOP.iow0.arr[94]; +wire [63:0] Q_189 = ITOP.iow1.arr[94]; +wire [63:0] Q_190 = ITOP.iow0.arr[95]; +wire [63:0] Q_191 = ITOP.iow1.arr[95]; +wire [63:0] Q_192 = ITOP.iow0.arr[96]; +wire [63:0] Q_193 = ITOP.iow1.arr[96]; +wire [63:0] Q_194 = ITOP.iow0.arr[97]; +wire [63:0] Q_195 = ITOP.iow1.arr[97]; +wire [63:0] Q_196 = ITOP.iow0.arr[98]; +wire [63:0] Q_197 = ITOP.iow1.arr[98]; +wire [63:0] Q_198 = ITOP.iow0.arr[99]; +wire [63:0] Q_199 = ITOP.iow1.arr[99]; +wire [63:0] Q_200 = ITOP.iow0.arr[100]; +wire [63:0] Q_201 = ITOP.iow1.arr[100]; +wire [63:0] Q_202 = ITOP.iow0.arr[101]; +wire [63:0] Q_203 = ITOP.iow1.arr[101]; +wire [63:0] Q_204 = ITOP.iow0.arr[102]; +wire [63:0] Q_205 = ITOP.iow1.arr[102]; +wire [63:0] Q_206 = ITOP.iow0.arr[103]; +wire [63:0] Q_207 = ITOP.iow1.arr[103]; +wire [63:0] Q_208 = ITOP.iow0.arr[104]; +wire [63:0] Q_209 = ITOP.iow1.arr[104]; +wire [63:0] Q_210 = ITOP.iow0.arr[105]; +wire [63:0] Q_211 = ITOP.iow1.arr[105]; +wire [63:0] Q_212 = ITOP.iow0.arr[106]; +wire [63:0] Q_213 = ITOP.iow1.arr[106]; +wire [63:0] Q_214 = ITOP.iow0.arr[107]; +wire [63:0] Q_215 = ITOP.iow1.arr[107]; +wire [63:0] Q_216 = ITOP.iow0.arr[108]; +wire [63:0] Q_217 = ITOP.iow1.arr[108]; +wire [63:0] Q_218 = ITOP.iow0.arr[109]; +wire [63:0] Q_219 = ITOP.iow1.arr[109]; +wire [63:0] Q_220 = ITOP.iow0.arr[110]; +wire [63:0] Q_221 = ITOP.iow1.arr[110]; +wire [63:0] Q_222 = ITOP.iow0.arr[111]; +wire [63:0] Q_223 = ITOP.iow1.arr[111]; +wire [63:0] Q_224 = ITOP.iow0.arr[112]; +wire [63:0] Q_225 = ITOP.iow1.arr[112]; +wire [63:0] Q_226 = ITOP.iow0.arr[113]; +wire [63:0] Q_227 = ITOP.iow1.arr[113]; +wire [63:0] Q_228 = ITOP.iow0.arr[114]; +wire [63:0] Q_229 = ITOP.iow1.arr[114]; +wire [63:0] Q_230 = ITOP.iow0.arr[115]; +wire [63:0] Q_231 = ITOP.iow1.arr[115]; +wire [63:0] Q_232 = ITOP.iow0.arr[116]; +wire [63:0] Q_233 = ITOP.iow1.arr[116]; +wire [63:0] Q_234 = ITOP.iow0.arr[117]; +wire [63:0] Q_235 = ITOP.iow1.arr[117]; +wire [63:0] Q_236 = ITOP.iow0.arr[118]; +wire [63:0] Q_237 = ITOP.iow1.arr[118]; +wire [63:0] Q_238 = ITOP.iow0.arr[119]; +wire [63:0] Q_239 = ITOP.iow1.arr[119]; +wire [63:0] Q_240 = ITOP.iow0.arr[120]; +wire [63:0] Q_241 = ITOP.iow1.arr[120]; +wire [63:0] Q_242 = ITOP.iow0.arr[121]; +wire [63:0] Q_243 = ITOP.iow1.arr[121]; +wire [63:0] Q_244 = ITOP.iow0.arr[122]; +wire [63:0] Q_245 = ITOP.iow1.arr[122]; +wire [63:0] Q_246 = ITOP.iow0.arr[123]; +wire [63:0] Q_247 = ITOP.iow1.arr[123]; +wire [63:0] Q_248 = ITOP.iow0.arr[124]; +wire [63:0] Q_249 = ITOP.iow1.arr[124]; +wire [63:0] Q_250 = ITOP.iow0.arr[125]; +wire [63:0] Q_251 = ITOP.iow1.arr[125]; +wire [63:0] Q_252 = ITOP.iow0.arr[126]; +wire [63:0] Q_253 = ITOP.iow1.arr[126]; +wire [63:0] Q_254 = ITOP.iow0.arr[127]; +wire [63:0] Q_255 = ITOP.iow1.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X64_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [7:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [63:0] rmuxd0, rmuxd1; + wire [63:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {64{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0 ; + assign rmuxd1 = {64{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0] | rmuxd1[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X64_GL_M2_D2_ram # (128, 64, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_256X64_GL_M2_D2_ram # (128, 64, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [7:0] addr; +reg [63:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X64_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [127:0] mem_phys_read_padr; +input [6:0] addr; + reg [127:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [128-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {128 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {128 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [127:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [127:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [128-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {128 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {128 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [127:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [127:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [128-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {128 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {128 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 64'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 64'bx; + for (i=0; i<=63; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [127:0] data; + reg [63:0] wr[1:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [127:0] mon_bit_w; +input [6:0] addr; + reg [127:0] mon_row; + reg [63:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [127:0] mon_bit_r; +input [6:0] addr; + reg [127:0] mon_row; + reg [63:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [127:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<128; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow1.arr[0]; +wire [63:0] Q_2 = ITOP.iow0.arr[1]; +wire [63:0] Q_3 = ITOP.iow1.arr[1]; +wire [63:0] Q_4 = ITOP.iow0.arr[2]; +wire [63:0] Q_5 = ITOP.iow1.arr[2]; +wire [63:0] Q_6 = ITOP.iow0.arr[3]; +wire [63:0] Q_7 = ITOP.iow1.arr[3]; +wire [63:0] Q_8 = ITOP.iow0.arr[4]; +wire [63:0] Q_9 = ITOP.iow1.arr[4]; +wire [63:0] Q_10 = ITOP.iow0.arr[5]; +wire [63:0] Q_11 = ITOP.iow1.arr[5]; +wire [63:0] Q_12 = ITOP.iow0.arr[6]; +wire [63:0] Q_13 = ITOP.iow1.arr[6]; +wire [63:0] Q_14 = ITOP.iow0.arr[7]; +wire [63:0] Q_15 = ITOP.iow1.arr[7]; +wire [63:0] Q_16 = ITOP.iow0.arr[8]; +wire [63:0] Q_17 = ITOP.iow1.arr[8]; +wire [63:0] Q_18 = ITOP.iow0.arr[9]; +wire [63:0] Q_19 = ITOP.iow1.arr[9]; +wire [63:0] Q_20 = ITOP.iow0.arr[10]; +wire [63:0] Q_21 = ITOP.iow1.arr[10]; +wire [63:0] Q_22 = ITOP.iow0.arr[11]; +wire [63:0] Q_23 = ITOP.iow1.arr[11]; +wire [63:0] Q_24 = ITOP.iow0.arr[12]; +wire [63:0] Q_25 = ITOP.iow1.arr[12]; +wire [63:0] Q_26 = ITOP.iow0.arr[13]; +wire [63:0] Q_27 = ITOP.iow1.arr[13]; +wire [63:0] Q_28 = ITOP.iow0.arr[14]; +wire [63:0] Q_29 = ITOP.iow1.arr[14]; +wire [63:0] Q_30 = ITOP.iow0.arr[15]; +wire [63:0] Q_31 = ITOP.iow1.arr[15]; +wire [63:0] Q_32 = ITOP.iow0.arr[16]; +wire [63:0] Q_33 = ITOP.iow1.arr[16]; +wire [63:0] Q_34 = ITOP.iow0.arr[17]; +wire [63:0] Q_35 = ITOP.iow1.arr[17]; +wire [63:0] Q_36 = ITOP.iow0.arr[18]; +wire [63:0] Q_37 = ITOP.iow1.arr[18]; +wire [63:0] Q_38 = ITOP.iow0.arr[19]; +wire [63:0] Q_39 = ITOP.iow1.arr[19]; +wire [63:0] Q_40 = ITOP.iow0.arr[20]; +wire [63:0] Q_41 = ITOP.iow1.arr[20]; +wire [63:0] Q_42 = ITOP.iow0.arr[21]; +wire [63:0] Q_43 = ITOP.iow1.arr[21]; +wire [63:0] Q_44 = ITOP.iow0.arr[22]; +wire [63:0] Q_45 = ITOP.iow1.arr[22]; +wire [63:0] Q_46 = ITOP.iow0.arr[23]; +wire [63:0] Q_47 = ITOP.iow1.arr[23]; +wire [63:0] Q_48 = ITOP.iow0.arr[24]; +wire [63:0] Q_49 = ITOP.iow1.arr[24]; +wire [63:0] Q_50 = ITOP.iow0.arr[25]; +wire [63:0] Q_51 = ITOP.iow1.arr[25]; +wire [63:0] Q_52 = ITOP.iow0.arr[26]; +wire [63:0] Q_53 = ITOP.iow1.arr[26]; +wire [63:0] Q_54 = ITOP.iow0.arr[27]; +wire [63:0] Q_55 = ITOP.iow1.arr[27]; +wire [63:0] Q_56 = ITOP.iow0.arr[28]; +wire [63:0] Q_57 = ITOP.iow1.arr[28]; +wire [63:0] Q_58 = ITOP.iow0.arr[29]; +wire [63:0] Q_59 = ITOP.iow1.arr[29]; +wire [63:0] Q_60 = ITOP.iow0.arr[30]; +wire [63:0] Q_61 = ITOP.iow1.arr[30]; +wire [63:0] Q_62 = ITOP.iow0.arr[31]; +wire [63:0] Q_63 = ITOP.iow1.arr[31]; +wire [63:0] Q_64 = ITOP.iow0.arr[32]; +wire [63:0] Q_65 = ITOP.iow1.arr[32]; +wire [63:0] Q_66 = ITOP.iow0.arr[33]; +wire [63:0] Q_67 = ITOP.iow1.arr[33]; +wire [63:0] Q_68 = ITOP.iow0.arr[34]; +wire [63:0] Q_69 = ITOP.iow1.arr[34]; +wire [63:0] Q_70 = ITOP.iow0.arr[35]; +wire [63:0] Q_71 = ITOP.iow1.arr[35]; +wire [63:0] Q_72 = ITOP.iow0.arr[36]; +wire [63:0] Q_73 = ITOP.iow1.arr[36]; +wire [63:0] Q_74 = ITOP.iow0.arr[37]; +wire [63:0] Q_75 = ITOP.iow1.arr[37]; +wire [63:0] Q_76 = ITOP.iow0.arr[38]; +wire [63:0] Q_77 = ITOP.iow1.arr[38]; +wire [63:0] Q_78 = ITOP.iow0.arr[39]; +wire [63:0] Q_79 = ITOP.iow1.arr[39]; +wire [63:0] Q_80 = ITOP.iow0.arr[40]; +wire [63:0] Q_81 = ITOP.iow1.arr[40]; +wire [63:0] Q_82 = ITOP.iow0.arr[41]; +wire [63:0] Q_83 = ITOP.iow1.arr[41]; +wire [63:0] Q_84 = ITOP.iow0.arr[42]; +wire [63:0] Q_85 = ITOP.iow1.arr[42]; +wire [63:0] Q_86 = ITOP.iow0.arr[43]; +wire [63:0] Q_87 = ITOP.iow1.arr[43]; +wire [63:0] Q_88 = ITOP.iow0.arr[44]; +wire [63:0] Q_89 = ITOP.iow1.arr[44]; +wire [63:0] Q_90 = ITOP.iow0.arr[45]; +wire [63:0] Q_91 = ITOP.iow1.arr[45]; +wire [63:0] Q_92 = ITOP.iow0.arr[46]; +wire [63:0] Q_93 = ITOP.iow1.arr[46]; +wire [63:0] Q_94 = ITOP.iow0.arr[47]; +wire [63:0] Q_95 = ITOP.iow1.arr[47]; +wire [63:0] Q_96 = ITOP.iow0.arr[48]; +wire [63:0] Q_97 = ITOP.iow1.arr[48]; +wire [63:0] Q_98 = ITOP.iow0.arr[49]; +wire [63:0] Q_99 = ITOP.iow1.arr[49]; +wire [63:0] Q_100 = ITOP.iow0.arr[50]; +wire [63:0] Q_101 = ITOP.iow1.arr[50]; +wire [63:0] Q_102 = ITOP.iow0.arr[51]; +wire [63:0] Q_103 = ITOP.iow1.arr[51]; +wire [63:0] Q_104 = ITOP.iow0.arr[52]; +wire [63:0] Q_105 = ITOP.iow1.arr[52]; +wire [63:0] Q_106 = ITOP.iow0.arr[53]; +wire [63:0] Q_107 = ITOP.iow1.arr[53]; +wire [63:0] Q_108 = ITOP.iow0.arr[54]; +wire [63:0] Q_109 = ITOP.iow1.arr[54]; +wire [63:0] Q_110 = ITOP.iow0.arr[55]; +wire [63:0] Q_111 = ITOP.iow1.arr[55]; +wire [63:0] Q_112 = ITOP.iow0.arr[56]; +wire [63:0] Q_113 = ITOP.iow1.arr[56]; +wire [63:0] Q_114 = ITOP.iow0.arr[57]; +wire [63:0] Q_115 = ITOP.iow1.arr[57]; +wire [63:0] Q_116 = ITOP.iow0.arr[58]; +wire [63:0] Q_117 = ITOP.iow1.arr[58]; +wire [63:0] Q_118 = ITOP.iow0.arr[59]; +wire [63:0] Q_119 = ITOP.iow1.arr[59]; +wire [63:0] Q_120 = ITOP.iow0.arr[60]; +wire [63:0] Q_121 = ITOP.iow1.arr[60]; +wire [63:0] Q_122 = ITOP.iow0.arr[61]; +wire [63:0] Q_123 = ITOP.iow1.arr[61]; +wire [63:0] Q_124 = ITOP.iow0.arr[62]; +wire [63:0] Q_125 = ITOP.iow1.arr[62]; +wire [63:0] Q_126 = ITOP.iow0.arr[63]; +wire [63:0] Q_127 = ITOP.iow1.arr[63]; +wire [63:0] Q_128 = ITOP.iow0.arr[64]; +wire [63:0] Q_129 = ITOP.iow1.arr[64]; +wire [63:0] Q_130 = ITOP.iow0.arr[65]; +wire [63:0] Q_131 = ITOP.iow1.arr[65]; +wire [63:0] Q_132 = ITOP.iow0.arr[66]; +wire [63:0] Q_133 = ITOP.iow1.arr[66]; +wire [63:0] Q_134 = ITOP.iow0.arr[67]; +wire [63:0] Q_135 = ITOP.iow1.arr[67]; +wire [63:0] Q_136 = ITOP.iow0.arr[68]; +wire [63:0] Q_137 = ITOP.iow1.arr[68]; +wire [63:0] Q_138 = ITOP.iow0.arr[69]; +wire [63:0] Q_139 = ITOP.iow1.arr[69]; +wire [63:0] Q_140 = ITOP.iow0.arr[70]; +wire [63:0] Q_141 = ITOP.iow1.arr[70]; +wire [63:0] Q_142 = ITOP.iow0.arr[71]; +wire [63:0] Q_143 = ITOP.iow1.arr[71]; +wire [63:0] Q_144 = ITOP.iow0.arr[72]; +wire [63:0] Q_145 = ITOP.iow1.arr[72]; +wire [63:0] Q_146 = ITOP.iow0.arr[73]; +wire [63:0] Q_147 = ITOP.iow1.arr[73]; +wire [63:0] Q_148 = ITOP.iow0.arr[74]; +wire [63:0] Q_149 = ITOP.iow1.arr[74]; +wire [63:0] Q_150 = ITOP.iow0.arr[75]; +wire [63:0] Q_151 = ITOP.iow1.arr[75]; +wire [63:0] Q_152 = ITOP.iow0.arr[76]; +wire [63:0] Q_153 = ITOP.iow1.arr[76]; +wire [63:0] Q_154 = ITOP.iow0.arr[77]; +wire [63:0] Q_155 = ITOP.iow1.arr[77]; +wire [63:0] Q_156 = ITOP.iow0.arr[78]; +wire [63:0] Q_157 = ITOP.iow1.arr[78]; +wire [63:0] Q_158 = ITOP.iow0.arr[79]; +wire [63:0] Q_159 = ITOP.iow1.arr[79]; +wire [63:0] Q_160 = ITOP.iow0.arr[80]; +wire [63:0] Q_161 = ITOP.iow1.arr[80]; +wire [63:0] Q_162 = ITOP.iow0.arr[81]; +wire [63:0] Q_163 = ITOP.iow1.arr[81]; +wire [63:0] Q_164 = ITOP.iow0.arr[82]; +wire [63:0] Q_165 = ITOP.iow1.arr[82]; +wire [63:0] Q_166 = ITOP.iow0.arr[83]; +wire [63:0] Q_167 = ITOP.iow1.arr[83]; +wire [63:0] Q_168 = ITOP.iow0.arr[84]; +wire [63:0] Q_169 = ITOP.iow1.arr[84]; +wire [63:0] Q_170 = ITOP.iow0.arr[85]; +wire [63:0] Q_171 = ITOP.iow1.arr[85]; +wire [63:0] Q_172 = ITOP.iow0.arr[86]; +wire [63:0] Q_173 = ITOP.iow1.arr[86]; +wire [63:0] Q_174 = ITOP.iow0.arr[87]; +wire [63:0] Q_175 = ITOP.iow1.arr[87]; +wire [63:0] Q_176 = ITOP.iow0.arr[88]; +wire [63:0] Q_177 = ITOP.iow1.arr[88]; +wire [63:0] Q_178 = ITOP.iow0.arr[89]; +wire [63:0] Q_179 = ITOP.iow1.arr[89]; +wire [63:0] Q_180 = ITOP.iow0.arr[90]; +wire [63:0] Q_181 = ITOP.iow1.arr[90]; +wire [63:0] Q_182 = ITOP.iow0.arr[91]; +wire [63:0] Q_183 = ITOP.iow1.arr[91]; +wire [63:0] Q_184 = ITOP.iow0.arr[92]; +wire [63:0] Q_185 = ITOP.iow1.arr[92]; +wire [63:0] Q_186 = ITOP.iow0.arr[93]; +wire [63:0] Q_187 = ITOP.iow1.arr[93]; +wire [63:0] Q_188 = ITOP.iow0.arr[94]; +wire [63:0] Q_189 = ITOP.iow1.arr[94]; +wire [63:0] Q_190 = ITOP.iow0.arr[95]; +wire [63:0] Q_191 = ITOP.iow1.arr[95]; +wire [63:0] Q_192 = ITOP.iow0.arr[96]; +wire [63:0] Q_193 = ITOP.iow1.arr[96]; +wire [63:0] Q_194 = ITOP.iow0.arr[97]; +wire [63:0] Q_195 = ITOP.iow1.arr[97]; +wire [63:0] Q_196 = ITOP.iow0.arr[98]; +wire [63:0] Q_197 = ITOP.iow1.arr[98]; +wire [63:0] Q_198 = ITOP.iow0.arr[99]; +wire [63:0] Q_199 = ITOP.iow1.arr[99]; +wire [63:0] Q_200 = ITOP.iow0.arr[100]; +wire [63:0] Q_201 = ITOP.iow1.arr[100]; +wire [63:0] Q_202 = ITOP.iow0.arr[101]; +wire [63:0] Q_203 = ITOP.iow1.arr[101]; +wire [63:0] Q_204 = ITOP.iow0.arr[102]; +wire [63:0] Q_205 = ITOP.iow1.arr[102]; +wire [63:0] Q_206 = ITOP.iow0.arr[103]; +wire [63:0] Q_207 = ITOP.iow1.arr[103]; +wire [63:0] Q_208 = ITOP.iow0.arr[104]; +wire [63:0] Q_209 = ITOP.iow1.arr[104]; +wire [63:0] Q_210 = ITOP.iow0.arr[105]; +wire [63:0] Q_211 = ITOP.iow1.arr[105]; +wire [63:0] Q_212 = ITOP.iow0.arr[106]; +wire [63:0] Q_213 = ITOP.iow1.arr[106]; +wire [63:0] Q_214 = ITOP.iow0.arr[107]; +wire [63:0] Q_215 = ITOP.iow1.arr[107]; +wire [63:0] Q_216 = ITOP.iow0.arr[108]; +wire [63:0] Q_217 = ITOP.iow1.arr[108]; +wire [63:0] Q_218 = ITOP.iow0.arr[109]; +wire [63:0] Q_219 = ITOP.iow1.arr[109]; +wire [63:0] Q_220 = ITOP.iow0.arr[110]; +wire [63:0] Q_221 = ITOP.iow1.arr[110]; +wire [63:0] Q_222 = ITOP.iow0.arr[111]; +wire [63:0] Q_223 = ITOP.iow1.arr[111]; +wire [63:0] Q_224 = ITOP.iow0.arr[112]; +wire [63:0] Q_225 = ITOP.iow1.arr[112]; +wire [63:0] Q_226 = ITOP.iow0.arr[113]; +wire [63:0] Q_227 = ITOP.iow1.arr[113]; +wire [63:0] Q_228 = ITOP.iow0.arr[114]; +wire [63:0] Q_229 = ITOP.iow1.arr[114]; +wire [63:0] Q_230 = ITOP.iow0.arr[115]; +wire [63:0] Q_231 = ITOP.iow1.arr[115]; +wire [63:0] Q_232 = ITOP.iow0.arr[116]; +wire [63:0] Q_233 = ITOP.iow1.arr[116]; +wire [63:0] Q_234 = ITOP.iow0.arr[117]; +wire [63:0] Q_235 = ITOP.iow1.arr[117]; +wire [63:0] Q_236 = ITOP.iow0.arr[118]; +wire [63:0] Q_237 = ITOP.iow1.arr[118]; +wire [63:0] Q_238 = ITOP.iow0.arr[119]; +wire [63:0] Q_239 = ITOP.iow1.arr[119]; +wire [63:0] Q_240 = ITOP.iow0.arr[120]; +wire [63:0] Q_241 = ITOP.iow1.arr[120]; +wire [63:0] Q_242 = ITOP.iow0.arr[121]; +wire [63:0] Q_243 = ITOP.iow1.arr[121]; +wire [63:0] Q_244 = ITOP.iow0.arr[122]; +wire [63:0] Q_245 = ITOP.iow1.arr[122]; +wire [63:0] Q_246 = ITOP.iow0.arr[123]; +wire [63:0] Q_247 = ITOP.iow1.arr[123]; +wire [63:0] Q_248 = ITOP.iow0.arr[124]; +wire [63:0] Q_249 = ITOP.iow1.arr[124]; +wire [63:0] Q_250 = ITOP.iow0.arr[125]; +wire [63:0] Q_251 = ITOP.iow1.arr[125]; +wire [63:0] Q_252 = ITOP.iow0.arr[126]; +wire [63:0] Q_253 = ITOP.iow1.arr[126]; +wire [63:0] Q_254 = ITOP.iow0.arr[127]; +wire [63:0] Q_255 = ITOP.iow1.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X64_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [7:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [63:0] rmuxd0, rmuxd1; + wire [63:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {64{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0 ; + assign rmuxd1 = {64{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0] | rmuxd1[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X64_GL_M2_D2_ram # (128, 64, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_256X64_GL_M2_D2_ram # (128, 64, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [7:0] addr; +reg [63:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X64_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [79:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [79:0] val; + integer i; + begin + val = {80{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [79:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [80-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {80 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {80 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [159:0] mem_phys_read_padr; +input [6:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [79:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=79; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [159:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [79:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=79; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [159:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [79:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 80'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 80'bx; + for (i=0; i<=79; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [159:0] data; + reg [79:0] wr[1:0]; + integer i; + begin + for (i=0; i<=79; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [159:0] mon_bit_w; +input [6:0] addr; + reg [159:0] mon_row; + reg [79:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=79; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [159:0] mon_bit_r; +input [6:0] addr; + reg [159:0] mon_row; + reg [79:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=79; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [159:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [79:0] Q_0 = ITOP.iow0.arr[0]; +wire [79:0] Q_1 = ITOP.iow1.arr[0]; +wire [79:0] Q_2 = ITOP.iow0.arr[1]; +wire [79:0] Q_3 = ITOP.iow1.arr[1]; +wire [79:0] Q_4 = ITOP.iow0.arr[2]; +wire [79:0] Q_5 = ITOP.iow1.arr[2]; +wire [79:0] Q_6 = ITOP.iow0.arr[3]; +wire [79:0] Q_7 = ITOP.iow1.arr[3]; +wire [79:0] Q_8 = ITOP.iow0.arr[4]; +wire [79:0] Q_9 = ITOP.iow1.arr[4]; +wire [79:0] Q_10 = ITOP.iow0.arr[5]; +wire [79:0] Q_11 = ITOP.iow1.arr[5]; +wire [79:0] Q_12 = ITOP.iow0.arr[6]; +wire [79:0] Q_13 = ITOP.iow1.arr[6]; +wire [79:0] Q_14 = ITOP.iow0.arr[7]; +wire [79:0] Q_15 = ITOP.iow1.arr[7]; +wire [79:0] Q_16 = ITOP.iow0.arr[8]; +wire [79:0] Q_17 = ITOP.iow1.arr[8]; +wire [79:0] Q_18 = ITOP.iow0.arr[9]; +wire [79:0] Q_19 = ITOP.iow1.arr[9]; +wire [79:0] Q_20 = ITOP.iow0.arr[10]; +wire [79:0] Q_21 = ITOP.iow1.arr[10]; +wire [79:0] Q_22 = ITOP.iow0.arr[11]; +wire [79:0] Q_23 = ITOP.iow1.arr[11]; +wire [79:0] Q_24 = ITOP.iow0.arr[12]; +wire [79:0] Q_25 = ITOP.iow1.arr[12]; +wire [79:0] Q_26 = ITOP.iow0.arr[13]; +wire [79:0] Q_27 = ITOP.iow1.arr[13]; +wire [79:0] Q_28 = ITOP.iow0.arr[14]; +wire [79:0] Q_29 = ITOP.iow1.arr[14]; +wire [79:0] Q_30 = ITOP.iow0.arr[15]; +wire [79:0] Q_31 = ITOP.iow1.arr[15]; +wire [79:0] Q_32 = ITOP.iow0.arr[16]; +wire [79:0] Q_33 = ITOP.iow1.arr[16]; +wire [79:0] Q_34 = ITOP.iow0.arr[17]; +wire [79:0] Q_35 = ITOP.iow1.arr[17]; +wire [79:0] Q_36 = ITOP.iow0.arr[18]; +wire [79:0] Q_37 = ITOP.iow1.arr[18]; +wire [79:0] Q_38 = ITOP.iow0.arr[19]; +wire [79:0] Q_39 = ITOP.iow1.arr[19]; +wire [79:0] Q_40 = ITOP.iow0.arr[20]; +wire [79:0] Q_41 = ITOP.iow1.arr[20]; +wire [79:0] Q_42 = ITOP.iow0.arr[21]; +wire [79:0] Q_43 = ITOP.iow1.arr[21]; +wire [79:0] Q_44 = ITOP.iow0.arr[22]; +wire [79:0] Q_45 = ITOP.iow1.arr[22]; +wire [79:0] Q_46 = ITOP.iow0.arr[23]; +wire [79:0] Q_47 = ITOP.iow1.arr[23]; +wire [79:0] Q_48 = ITOP.iow0.arr[24]; +wire [79:0] Q_49 = ITOP.iow1.arr[24]; +wire [79:0] Q_50 = ITOP.iow0.arr[25]; +wire [79:0] Q_51 = ITOP.iow1.arr[25]; +wire [79:0] Q_52 = ITOP.iow0.arr[26]; +wire [79:0] Q_53 = ITOP.iow1.arr[26]; +wire [79:0] Q_54 = ITOP.iow0.arr[27]; +wire [79:0] Q_55 = ITOP.iow1.arr[27]; +wire [79:0] Q_56 = ITOP.iow0.arr[28]; +wire [79:0] Q_57 = ITOP.iow1.arr[28]; +wire [79:0] Q_58 = ITOP.iow0.arr[29]; +wire [79:0] Q_59 = ITOP.iow1.arr[29]; +wire [79:0] Q_60 = ITOP.iow0.arr[30]; +wire [79:0] Q_61 = ITOP.iow1.arr[30]; +wire [79:0] Q_62 = ITOP.iow0.arr[31]; +wire [79:0] Q_63 = ITOP.iow1.arr[31]; +wire [79:0] Q_64 = ITOP.iow0.arr[32]; +wire [79:0] Q_65 = ITOP.iow1.arr[32]; +wire [79:0] Q_66 = ITOP.iow0.arr[33]; +wire [79:0] Q_67 = ITOP.iow1.arr[33]; +wire [79:0] Q_68 = ITOP.iow0.arr[34]; +wire [79:0] Q_69 = ITOP.iow1.arr[34]; +wire [79:0] Q_70 = ITOP.iow0.arr[35]; +wire [79:0] Q_71 = ITOP.iow1.arr[35]; +wire [79:0] Q_72 = ITOP.iow0.arr[36]; +wire [79:0] Q_73 = ITOP.iow1.arr[36]; +wire [79:0] Q_74 = ITOP.iow0.arr[37]; +wire [79:0] Q_75 = ITOP.iow1.arr[37]; +wire [79:0] Q_76 = ITOP.iow0.arr[38]; +wire [79:0] Q_77 = ITOP.iow1.arr[38]; +wire [79:0] Q_78 = ITOP.iow0.arr[39]; +wire [79:0] Q_79 = ITOP.iow1.arr[39]; +wire [79:0] Q_80 = ITOP.iow0.arr[40]; +wire [79:0] Q_81 = ITOP.iow1.arr[40]; +wire [79:0] Q_82 = ITOP.iow0.arr[41]; +wire [79:0] Q_83 = ITOP.iow1.arr[41]; +wire [79:0] Q_84 = ITOP.iow0.arr[42]; +wire [79:0] Q_85 = ITOP.iow1.arr[42]; +wire [79:0] Q_86 = ITOP.iow0.arr[43]; +wire [79:0] Q_87 = ITOP.iow1.arr[43]; +wire [79:0] Q_88 = ITOP.iow0.arr[44]; +wire [79:0] Q_89 = ITOP.iow1.arr[44]; +wire [79:0] Q_90 = ITOP.iow0.arr[45]; +wire [79:0] Q_91 = ITOP.iow1.arr[45]; +wire [79:0] Q_92 = ITOP.iow0.arr[46]; +wire [79:0] Q_93 = ITOP.iow1.arr[46]; +wire [79:0] Q_94 = ITOP.iow0.arr[47]; +wire [79:0] Q_95 = ITOP.iow1.arr[47]; +wire [79:0] Q_96 = ITOP.iow0.arr[48]; +wire [79:0] Q_97 = ITOP.iow1.arr[48]; +wire [79:0] Q_98 = ITOP.iow0.arr[49]; +wire [79:0] Q_99 = ITOP.iow1.arr[49]; +wire [79:0] Q_100 = ITOP.iow0.arr[50]; +wire [79:0] Q_101 = ITOP.iow1.arr[50]; +wire [79:0] Q_102 = ITOP.iow0.arr[51]; +wire [79:0] Q_103 = ITOP.iow1.arr[51]; +wire [79:0] Q_104 = ITOP.iow0.arr[52]; +wire [79:0] Q_105 = ITOP.iow1.arr[52]; +wire [79:0] Q_106 = ITOP.iow0.arr[53]; +wire [79:0] Q_107 = ITOP.iow1.arr[53]; +wire [79:0] Q_108 = ITOP.iow0.arr[54]; +wire [79:0] Q_109 = ITOP.iow1.arr[54]; +wire [79:0] Q_110 = ITOP.iow0.arr[55]; +wire [79:0] Q_111 = ITOP.iow1.arr[55]; +wire [79:0] Q_112 = ITOP.iow0.arr[56]; +wire [79:0] Q_113 = ITOP.iow1.arr[56]; +wire [79:0] Q_114 = ITOP.iow0.arr[57]; +wire [79:0] Q_115 = ITOP.iow1.arr[57]; +wire [79:0] Q_116 = ITOP.iow0.arr[58]; +wire [79:0] Q_117 = ITOP.iow1.arr[58]; +wire [79:0] Q_118 = ITOP.iow0.arr[59]; +wire [79:0] Q_119 = ITOP.iow1.arr[59]; +wire [79:0] Q_120 = ITOP.iow0.arr[60]; +wire [79:0] Q_121 = ITOP.iow1.arr[60]; +wire [79:0] Q_122 = ITOP.iow0.arr[61]; +wire [79:0] Q_123 = ITOP.iow1.arr[61]; +wire [79:0] Q_124 = ITOP.iow0.arr[62]; +wire [79:0] Q_125 = ITOP.iow1.arr[62]; +wire [79:0] Q_126 = ITOP.iow0.arr[63]; +wire [79:0] Q_127 = ITOP.iow1.arr[63]; +wire [79:0] Q_128 = ITOP.iow0.arr[64]; +wire [79:0] Q_129 = ITOP.iow1.arr[64]; +wire [79:0] Q_130 = ITOP.iow0.arr[65]; +wire [79:0] Q_131 = ITOP.iow1.arr[65]; +wire [79:0] Q_132 = ITOP.iow0.arr[66]; +wire [79:0] Q_133 = ITOP.iow1.arr[66]; +wire [79:0] Q_134 = ITOP.iow0.arr[67]; +wire [79:0] Q_135 = ITOP.iow1.arr[67]; +wire [79:0] Q_136 = ITOP.iow0.arr[68]; +wire [79:0] Q_137 = ITOP.iow1.arr[68]; +wire [79:0] Q_138 = ITOP.iow0.arr[69]; +wire [79:0] Q_139 = ITOP.iow1.arr[69]; +wire [79:0] Q_140 = ITOP.iow0.arr[70]; +wire [79:0] Q_141 = ITOP.iow1.arr[70]; +wire [79:0] Q_142 = ITOP.iow0.arr[71]; +wire [79:0] Q_143 = ITOP.iow1.arr[71]; +wire [79:0] Q_144 = ITOP.iow0.arr[72]; +wire [79:0] Q_145 = ITOP.iow1.arr[72]; +wire [79:0] Q_146 = ITOP.iow0.arr[73]; +wire [79:0] Q_147 = ITOP.iow1.arr[73]; +wire [79:0] Q_148 = ITOP.iow0.arr[74]; +wire [79:0] Q_149 = ITOP.iow1.arr[74]; +wire [79:0] Q_150 = ITOP.iow0.arr[75]; +wire [79:0] Q_151 = ITOP.iow1.arr[75]; +wire [79:0] Q_152 = ITOP.iow0.arr[76]; +wire [79:0] Q_153 = ITOP.iow1.arr[76]; +wire [79:0] Q_154 = ITOP.iow0.arr[77]; +wire [79:0] Q_155 = ITOP.iow1.arr[77]; +wire [79:0] Q_156 = ITOP.iow0.arr[78]; +wire [79:0] Q_157 = ITOP.iow1.arr[78]; +wire [79:0] Q_158 = ITOP.iow0.arr[79]; +wire [79:0] Q_159 = ITOP.iow1.arr[79]; +wire [79:0] Q_160 = ITOP.iow0.arr[80]; +wire [79:0] Q_161 = ITOP.iow1.arr[80]; +wire [79:0] Q_162 = ITOP.iow0.arr[81]; +wire [79:0] Q_163 = ITOP.iow1.arr[81]; +wire [79:0] Q_164 = ITOP.iow0.arr[82]; +wire [79:0] Q_165 = ITOP.iow1.arr[82]; +wire [79:0] Q_166 = ITOP.iow0.arr[83]; +wire [79:0] Q_167 = ITOP.iow1.arr[83]; +wire [79:0] Q_168 = ITOP.iow0.arr[84]; +wire [79:0] Q_169 = ITOP.iow1.arr[84]; +wire [79:0] Q_170 = ITOP.iow0.arr[85]; +wire [79:0] Q_171 = ITOP.iow1.arr[85]; +wire [79:0] Q_172 = ITOP.iow0.arr[86]; +wire [79:0] Q_173 = ITOP.iow1.arr[86]; +wire [79:0] Q_174 = ITOP.iow0.arr[87]; +wire [79:0] Q_175 = ITOP.iow1.arr[87]; +wire [79:0] Q_176 = ITOP.iow0.arr[88]; +wire [79:0] Q_177 = ITOP.iow1.arr[88]; +wire [79:0] Q_178 = ITOP.iow0.arr[89]; +wire [79:0] Q_179 = ITOP.iow1.arr[89]; +wire [79:0] Q_180 = ITOP.iow0.arr[90]; +wire [79:0] Q_181 = ITOP.iow1.arr[90]; +wire [79:0] Q_182 = ITOP.iow0.arr[91]; +wire [79:0] Q_183 = ITOP.iow1.arr[91]; +wire [79:0] Q_184 = ITOP.iow0.arr[92]; +wire [79:0] Q_185 = ITOP.iow1.arr[92]; +wire [79:0] Q_186 = ITOP.iow0.arr[93]; +wire [79:0] Q_187 = ITOP.iow1.arr[93]; +wire [79:0] Q_188 = ITOP.iow0.arr[94]; +wire [79:0] Q_189 = ITOP.iow1.arr[94]; +wire [79:0] Q_190 = ITOP.iow0.arr[95]; +wire [79:0] Q_191 = ITOP.iow1.arr[95]; +wire [79:0] Q_192 = ITOP.iow0.arr[96]; +wire [79:0] Q_193 = ITOP.iow1.arr[96]; +wire [79:0] Q_194 = ITOP.iow0.arr[97]; +wire [79:0] Q_195 = ITOP.iow1.arr[97]; +wire [79:0] Q_196 = ITOP.iow0.arr[98]; +wire [79:0] Q_197 = ITOP.iow1.arr[98]; +wire [79:0] Q_198 = ITOP.iow0.arr[99]; +wire [79:0] Q_199 = ITOP.iow1.arr[99]; +wire [79:0] Q_200 = ITOP.iow0.arr[100]; +wire [79:0] Q_201 = ITOP.iow1.arr[100]; +wire [79:0] Q_202 = ITOP.iow0.arr[101]; +wire [79:0] Q_203 = ITOP.iow1.arr[101]; +wire [79:0] Q_204 = ITOP.iow0.arr[102]; +wire [79:0] Q_205 = ITOP.iow1.arr[102]; +wire [79:0] Q_206 = ITOP.iow0.arr[103]; +wire [79:0] Q_207 = ITOP.iow1.arr[103]; +wire [79:0] Q_208 = ITOP.iow0.arr[104]; +wire [79:0] Q_209 = ITOP.iow1.arr[104]; +wire [79:0] Q_210 = ITOP.iow0.arr[105]; +wire [79:0] Q_211 = ITOP.iow1.arr[105]; +wire [79:0] Q_212 = ITOP.iow0.arr[106]; +wire [79:0] Q_213 = ITOP.iow1.arr[106]; +wire [79:0] Q_214 = ITOP.iow0.arr[107]; +wire [79:0] Q_215 = ITOP.iow1.arr[107]; +wire [79:0] Q_216 = ITOP.iow0.arr[108]; +wire [79:0] Q_217 = ITOP.iow1.arr[108]; +wire [79:0] Q_218 = ITOP.iow0.arr[109]; +wire [79:0] Q_219 = ITOP.iow1.arr[109]; +wire [79:0] Q_220 = ITOP.iow0.arr[110]; +wire [79:0] Q_221 = ITOP.iow1.arr[110]; +wire [79:0] Q_222 = ITOP.iow0.arr[111]; +wire [79:0] Q_223 = ITOP.iow1.arr[111]; +wire [79:0] Q_224 = ITOP.iow0.arr[112]; +wire [79:0] Q_225 = ITOP.iow1.arr[112]; +wire [79:0] Q_226 = ITOP.iow0.arr[113]; +wire [79:0] Q_227 = ITOP.iow1.arr[113]; +wire [79:0] Q_228 = ITOP.iow0.arr[114]; +wire [79:0] Q_229 = ITOP.iow1.arr[114]; +wire [79:0] Q_230 = ITOP.iow0.arr[115]; +wire [79:0] Q_231 = ITOP.iow1.arr[115]; +wire [79:0] Q_232 = ITOP.iow0.arr[116]; +wire [79:0] Q_233 = ITOP.iow1.arr[116]; +wire [79:0] Q_234 = ITOP.iow0.arr[117]; +wire [79:0] Q_235 = ITOP.iow1.arr[117]; +wire [79:0] Q_236 = ITOP.iow0.arr[118]; +wire [79:0] Q_237 = ITOP.iow1.arr[118]; +wire [79:0] Q_238 = ITOP.iow0.arr[119]; +wire [79:0] Q_239 = ITOP.iow1.arr[119]; +wire [79:0] Q_240 = ITOP.iow0.arr[120]; +wire [79:0] Q_241 = ITOP.iow1.arr[120]; +wire [79:0] Q_242 = ITOP.iow0.arr[121]; +wire [79:0] Q_243 = ITOP.iow1.arr[121]; +wire [79:0] Q_244 = ITOP.iow0.arr[122]; +wire [79:0] Q_245 = ITOP.iow1.arr[122]; +wire [79:0] Q_246 = ITOP.iow0.arr[123]; +wire [79:0] Q_247 = ITOP.iow1.arr[123]; +wire [79:0] Q_248 = ITOP.iow0.arr[124]; +wire [79:0] Q_249 = ITOP.iow1.arr[124]; +wire [79:0] Q_250 = ITOP.iow0.arr[125]; +wire [79:0] Q_251 = ITOP.iow1.arr[125]; +wire [79:0] Q_252 = ITOP.iow0.arr[126]; +wire [79:0] Q_253 = ITOP.iow1.arr[126]; +wire [79:0] Q_254 = ITOP.iow0.arr[127]; +wire [79:0] Q_255 = ITOP.iow1.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [79:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [79:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [79:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [79:0] WD_FF; + reg [79:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [79:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [79:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [79:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X80_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [79:0] WD; +input [7:0] RA, WA; +output [79:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [79:0] WDQ; + wire [79:0] WDBQ; + wire [79:0] WMNexp; + wire [79:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [79:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {80{1'b0}}; + assign SHFT = {80{1'b1}}; + reg [79:0] WDQ_pr; + wire [79:0] WDBQ_pr; + assign WMNexp = {80{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[79:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [79:0] dout; + wire [79:0] RD; + wire RD_rdnt; + wire [79:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [79:0] RDBYPASS = {80{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [79:0] force_x; +`ifndef SYNTHESIS + assign force_x = {80{1'bx}}; +`else + assign force_x = {80{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [79:0] rmuxd0, rmuxd1; + wire [79:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {80{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {80{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {80{RdClk0}} & ~dout0 ; + assign rmuxd1 = {80{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[79:0] <= (rmuxd0[79:0] | rmuxd1[79:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X80_GL_M2_D2_ram # (128, 80, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_256X80_GL_M2_D2_ram # (128, 80, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [79:0] data; + reg [79:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [79:0] mem_read_bank; +input [7:0] addr; +reg [79:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X80_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 80; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [79:0] val; + integer i; + begin + for (i=0; i<256; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [79:0] val; + integer i; + begin + val = {80{fill_bit}}; + for (i=0; i<256; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [7:0] addr; + reg [79:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [80-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {80 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {80 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[7:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [159:0] mem_phys_read_padr; +input [6:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [79:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=79; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [159:0] mem_phys_read_ladr; +input [7:0] addr; + reg [6:0] paddr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [79:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=79; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [159:0] mem_phys_read_pmasked; +input [7:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [79:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[7:1]) : 80'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[7:1]) : 80'bx; + for (i=0; i<=79; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [159:0] data; + reg [79:0] wr[1:0]; + integer i; + begin + for (i=0; i<=79; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [7:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [159:0] mon_bit_w; +input [6:0] addr; + reg [159:0] mon_row; + reg [79:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=79; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [159:0] mon_bit_r; +input [6:0] addr; + reg [159:0] mon_row; + reg [79:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=79; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [159:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [79:0] Q_0 = ITOP.iow0.arr[0]; +wire [79:0] Q_1 = ITOP.iow1.arr[0]; +wire [79:0] Q_2 = ITOP.iow0.arr[1]; +wire [79:0] Q_3 = ITOP.iow1.arr[1]; +wire [79:0] Q_4 = ITOP.iow0.arr[2]; +wire [79:0] Q_5 = ITOP.iow1.arr[2]; +wire [79:0] Q_6 = ITOP.iow0.arr[3]; +wire [79:0] Q_7 = ITOP.iow1.arr[3]; +wire [79:0] Q_8 = ITOP.iow0.arr[4]; +wire [79:0] Q_9 = ITOP.iow1.arr[4]; +wire [79:0] Q_10 = ITOP.iow0.arr[5]; +wire [79:0] Q_11 = ITOP.iow1.arr[5]; +wire [79:0] Q_12 = ITOP.iow0.arr[6]; +wire [79:0] Q_13 = ITOP.iow1.arr[6]; +wire [79:0] Q_14 = ITOP.iow0.arr[7]; +wire [79:0] Q_15 = ITOP.iow1.arr[7]; +wire [79:0] Q_16 = ITOP.iow0.arr[8]; +wire [79:0] Q_17 = ITOP.iow1.arr[8]; +wire [79:0] Q_18 = ITOP.iow0.arr[9]; +wire [79:0] Q_19 = ITOP.iow1.arr[9]; +wire [79:0] Q_20 = ITOP.iow0.arr[10]; +wire [79:0] Q_21 = ITOP.iow1.arr[10]; +wire [79:0] Q_22 = ITOP.iow0.arr[11]; +wire [79:0] Q_23 = ITOP.iow1.arr[11]; +wire [79:0] Q_24 = ITOP.iow0.arr[12]; +wire [79:0] Q_25 = ITOP.iow1.arr[12]; +wire [79:0] Q_26 = ITOP.iow0.arr[13]; +wire [79:0] Q_27 = ITOP.iow1.arr[13]; +wire [79:0] Q_28 = ITOP.iow0.arr[14]; +wire [79:0] Q_29 = ITOP.iow1.arr[14]; +wire [79:0] Q_30 = ITOP.iow0.arr[15]; +wire [79:0] Q_31 = ITOP.iow1.arr[15]; +wire [79:0] Q_32 = ITOP.iow0.arr[16]; +wire [79:0] Q_33 = ITOP.iow1.arr[16]; +wire [79:0] Q_34 = ITOP.iow0.arr[17]; +wire [79:0] Q_35 = ITOP.iow1.arr[17]; +wire [79:0] Q_36 = ITOP.iow0.arr[18]; +wire [79:0] Q_37 = ITOP.iow1.arr[18]; +wire [79:0] Q_38 = ITOP.iow0.arr[19]; +wire [79:0] Q_39 = ITOP.iow1.arr[19]; +wire [79:0] Q_40 = ITOP.iow0.arr[20]; +wire [79:0] Q_41 = ITOP.iow1.arr[20]; +wire [79:0] Q_42 = ITOP.iow0.arr[21]; +wire [79:0] Q_43 = ITOP.iow1.arr[21]; +wire [79:0] Q_44 = ITOP.iow0.arr[22]; +wire [79:0] Q_45 = ITOP.iow1.arr[22]; +wire [79:0] Q_46 = ITOP.iow0.arr[23]; +wire [79:0] Q_47 = ITOP.iow1.arr[23]; +wire [79:0] Q_48 = ITOP.iow0.arr[24]; +wire [79:0] Q_49 = ITOP.iow1.arr[24]; +wire [79:0] Q_50 = ITOP.iow0.arr[25]; +wire [79:0] Q_51 = ITOP.iow1.arr[25]; +wire [79:0] Q_52 = ITOP.iow0.arr[26]; +wire [79:0] Q_53 = ITOP.iow1.arr[26]; +wire [79:0] Q_54 = ITOP.iow0.arr[27]; +wire [79:0] Q_55 = ITOP.iow1.arr[27]; +wire [79:0] Q_56 = ITOP.iow0.arr[28]; +wire [79:0] Q_57 = ITOP.iow1.arr[28]; +wire [79:0] Q_58 = ITOP.iow0.arr[29]; +wire [79:0] Q_59 = ITOP.iow1.arr[29]; +wire [79:0] Q_60 = ITOP.iow0.arr[30]; +wire [79:0] Q_61 = ITOP.iow1.arr[30]; +wire [79:0] Q_62 = ITOP.iow0.arr[31]; +wire [79:0] Q_63 = ITOP.iow1.arr[31]; +wire [79:0] Q_64 = ITOP.iow0.arr[32]; +wire [79:0] Q_65 = ITOP.iow1.arr[32]; +wire [79:0] Q_66 = ITOP.iow0.arr[33]; +wire [79:0] Q_67 = ITOP.iow1.arr[33]; +wire [79:0] Q_68 = ITOP.iow0.arr[34]; +wire [79:0] Q_69 = ITOP.iow1.arr[34]; +wire [79:0] Q_70 = ITOP.iow0.arr[35]; +wire [79:0] Q_71 = ITOP.iow1.arr[35]; +wire [79:0] Q_72 = ITOP.iow0.arr[36]; +wire [79:0] Q_73 = ITOP.iow1.arr[36]; +wire [79:0] Q_74 = ITOP.iow0.arr[37]; +wire [79:0] Q_75 = ITOP.iow1.arr[37]; +wire [79:0] Q_76 = ITOP.iow0.arr[38]; +wire [79:0] Q_77 = ITOP.iow1.arr[38]; +wire [79:0] Q_78 = ITOP.iow0.arr[39]; +wire [79:0] Q_79 = ITOP.iow1.arr[39]; +wire [79:0] Q_80 = ITOP.iow0.arr[40]; +wire [79:0] Q_81 = ITOP.iow1.arr[40]; +wire [79:0] Q_82 = ITOP.iow0.arr[41]; +wire [79:0] Q_83 = ITOP.iow1.arr[41]; +wire [79:0] Q_84 = ITOP.iow0.arr[42]; +wire [79:0] Q_85 = ITOP.iow1.arr[42]; +wire [79:0] Q_86 = ITOP.iow0.arr[43]; +wire [79:0] Q_87 = ITOP.iow1.arr[43]; +wire [79:0] Q_88 = ITOP.iow0.arr[44]; +wire [79:0] Q_89 = ITOP.iow1.arr[44]; +wire [79:0] Q_90 = ITOP.iow0.arr[45]; +wire [79:0] Q_91 = ITOP.iow1.arr[45]; +wire [79:0] Q_92 = ITOP.iow0.arr[46]; +wire [79:0] Q_93 = ITOP.iow1.arr[46]; +wire [79:0] Q_94 = ITOP.iow0.arr[47]; +wire [79:0] Q_95 = ITOP.iow1.arr[47]; +wire [79:0] Q_96 = ITOP.iow0.arr[48]; +wire [79:0] Q_97 = ITOP.iow1.arr[48]; +wire [79:0] Q_98 = ITOP.iow0.arr[49]; +wire [79:0] Q_99 = ITOP.iow1.arr[49]; +wire [79:0] Q_100 = ITOP.iow0.arr[50]; +wire [79:0] Q_101 = ITOP.iow1.arr[50]; +wire [79:0] Q_102 = ITOP.iow0.arr[51]; +wire [79:0] Q_103 = ITOP.iow1.arr[51]; +wire [79:0] Q_104 = ITOP.iow0.arr[52]; +wire [79:0] Q_105 = ITOP.iow1.arr[52]; +wire [79:0] Q_106 = ITOP.iow0.arr[53]; +wire [79:0] Q_107 = ITOP.iow1.arr[53]; +wire [79:0] Q_108 = ITOP.iow0.arr[54]; +wire [79:0] Q_109 = ITOP.iow1.arr[54]; +wire [79:0] Q_110 = ITOP.iow0.arr[55]; +wire [79:0] Q_111 = ITOP.iow1.arr[55]; +wire [79:0] Q_112 = ITOP.iow0.arr[56]; +wire [79:0] Q_113 = ITOP.iow1.arr[56]; +wire [79:0] Q_114 = ITOP.iow0.arr[57]; +wire [79:0] Q_115 = ITOP.iow1.arr[57]; +wire [79:0] Q_116 = ITOP.iow0.arr[58]; +wire [79:0] Q_117 = ITOP.iow1.arr[58]; +wire [79:0] Q_118 = ITOP.iow0.arr[59]; +wire [79:0] Q_119 = ITOP.iow1.arr[59]; +wire [79:0] Q_120 = ITOP.iow0.arr[60]; +wire [79:0] Q_121 = ITOP.iow1.arr[60]; +wire [79:0] Q_122 = ITOP.iow0.arr[61]; +wire [79:0] Q_123 = ITOP.iow1.arr[61]; +wire [79:0] Q_124 = ITOP.iow0.arr[62]; +wire [79:0] Q_125 = ITOP.iow1.arr[62]; +wire [79:0] Q_126 = ITOP.iow0.arr[63]; +wire [79:0] Q_127 = ITOP.iow1.arr[63]; +wire [79:0] Q_128 = ITOP.iow0.arr[64]; +wire [79:0] Q_129 = ITOP.iow1.arr[64]; +wire [79:0] Q_130 = ITOP.iow0.arr[65]; +wire [79:0] Q_131 = ITOP.iow1.arr[65]; +wire [79:0] Q_132 = ITOP.iow0.arr[66]; +wire [79:0] Q_133 = ITOP.iow1.arr[66]; +wire [79:0] Q_134 = ITOP.iow0.arr[67]; +wire [79:0] Q_135 = ITOP.iow1.arr[67]; +wire [79:0] Q_136 = ITOP.iow0.arr[68]; +wire [79:0] Q_137 = ITOP.iow1.arr[68]; +wire [79:0] Q_138 = ITOP.iow0.arr[69]; +wire [79:0] Q_139 = ITOP.iow1.arr[69]; +wire [79:0] Q_140 = ITOP.iow0.arr[70]; +wire [79:0] Q_141 = ITOP.iow1.arr[70]; +wire [79:0] Q_142 = ITOP.iow0.arr[71]; +wire [79:0] Q_143 = ITOP.iow1.arr[71]; +wire [79:0] Q_144 = ITOP.iow0.arr[72]; +wire [79:0] Q_145 = ITOP.iow1.arr[72]; +wire [79:0] Q_146 = ITOP.iow0.arr[73]; +wire [79:0] Q_147 = ITOP.iow1.arr[73]; +wire [79:0] Q_148 = ITOP.iow0.arr[74]; +wire [79:0] Q_149 = ITOP.iow1.arr[74]; +wire [79:0] Q_150 = ITOP.iow0.arr[75]; +wire [79:0] Q_151 = ITOP.iow1.arr[75]; +wire [79:0] Q_152 = ITOP.iow0.arr[76]; +wire [79:0] Q_153 = ITOP.iow1.arr[76]; +wire [79:0] Q_154 = ITOP.iow0.arr[77]; +wire [79:0] Q_155 = ITOP.iow1.arr[77]; +wire [79:0] Q_156 = ITOP.iow0.arr[78]; +wire [79:0] Q_157 = ITOP.iow1.arr[78]; +wire [79:0] Q_158 = ITOP.iow0.arr[79]; +wire [79:0] Q_159 = ITOP.iow1.arr[79]; +wire [79:0] Q_160 = ITOP.iow0.arr[80]; +wire [79:0] Q_161 = ITOP.iow1.arr[80]; +wire [79:0] Q_162 = ITOP.iow0.arr[81]; +wire [79:0] Q_163 = ITOP.iow1.arr[81]; +wire [79:0] Q_164 = ITOP.iow0.arr[82]; +wire [79:0] Q_165 = ITOP.iow1.arr[82]; +wire [79:0] Q_166 = ITOP.iow0.arr[83]; +wire [79:0] Q_167 = ITOP.iow1.arr[83]; +wire [79:0] Q_168 = ITOP.iow0.arr[84]; +wire [79:0] Q_169 = ITOP.iow1.arr[84]; +wire [79:0] Q_170 = ITOP.iow0.arr[85]; +wire [79:0] Q_171 = ITOP.iow1.arr[85]; +wire [79:0] Q_172 = ITOP.iow0.arr[86]; +wire [79:0] Q_173 = ITOP.iow1.arr[86]; +wire [79:0] Q_174 = ITOP.iow0.arr[87]; +wire [79:0] Q_175 = ITOP.iow1.arr[87]; +wire [79:0] Q_176 = ITOP.iow0.arr[88]; +wire [79:0] Q_177 = ITOP.iow1.arr[88]; +wire [79:0] Q_178 = ITOP.iow0.arr[89]; +wire [79:0] Q_179 = ITOP.iow1.arr[89]; +wire [79:0] Q_180 = ITOP.iow0.arr[90]; +wire [79:0] Q_181 = ITOP.iow1.arr[90]; +wire [79:0] Q_182 = ITOP.iow0.arr[91]; +wire [79:0] Q_183 = ITOP.iow1.arr[91]; +wire [79:0] Q_184 = ITOP.iow0.arr[92]; +wire [79:0] Q_185 = ITOP.iow1.arr[92]; +wire [79:0] Q_186 = ITOP.iow0.arr[93]; +wire [79:0] Q_187 = ITOP.iow1.arr[93]; +wire [79:0] Q_188 = ITOP.iow0.arr[94]; +wire [79:0] Q_189 = ITOP.iow1.arr[94]; +wire [79:0] Q_190 = ITOP.iow0.arr[95]; +wire [79:0] Q_191 = ITOP.iow1.arr[95]; +wire [79:0] Q_192 = ITOP.iow0.arr[96]; +wire [79:0] Q_193 = ITOP.iow1.arr[96]; +wire [79:0] Q_194 = ITOP.iow0.arr[97]; +wire [79:0] Q_195 = ITOP.iow1.arr[97]; +wire [79:0] Q_196 = ITOP.iow0.arr[98]; +wire [79:0] Q_197 = ITOP.iow1.arr[98]; +wire [79:0] Q_198 = ITOP.iow0.arr[99]; +wire [79:0] Q_199 = ITOP.iow1.arr[99]; +wire [79:0] Q_200 = ITOP.iow0.arr[100]; +wire [79:0] Q_201 = ITOP.iow1.arr[100]; +wire [79:0] Q_202 = ITOP.iow0.arr[101]; +wire [79:0] Q_203 = ITOP.iow1.arr[101]; +wire [79:0] Q_204 = ITOP.iow0.arr[102]; +wire [79:0] Q_205 = ITOP.iow1.arr[102]; +wire [79:0] Q_206 = ITOP.iow0.arr[103]; +wire [79:0] Q_207 = ITOP.iow1.arr[103]; +wire [79:0] Q_208 = ITOP.iow0.arr[104]; +wire [79:0] Q_209 = ITOP.iow1.arr[104]; +wire [79:0] Q_210 = ITOP.iow0.arr[105]; +wire [79:0] Q_211 = ITOP.iow1.arr[105]; +wire [79:0] Q_212 = ITOP.iow0.arr[106]; +wire [79:0] Q_213 = ITOP.iow1.arr[106]; +wire [79:0] Q_214 = ITOP.iow0.arr[107]; +wire [79:0] Q_215 = ITOP.iow1.arr[107]; +wire [79:0] Q_216 = ITOP.iow0.arr[108]; +wire [79:0] Q_217 = ITOP.iow1.arr[108]; +wire [79:0] Q_218 = ITOP.iow0.arr[109]; +wire [79:0] Q_219 = ITOP.iow1.arr[109]; +wire [79:0] Q_220 = ITOP.iow0.arr[110]; +wire [79:0] Q_221 = ITOP.iow1.arr[110]; +wire [79:0] Q_222 = ITOP.iow0.arr[111]; +wire [79:0] Q_223 = ITOP.iow1.arr[111]; +wire [79:0] Q_224 = ITOP.iow0.arr[112]; +wire [79:0] Q_225 = ITOP.iow1.arr[112]; +wire [79:0] Q_226 = ITOP.iow0.arr[113]; +wire [79:0] Q_227 = ITOP.iow1.arr[113]; +wire [79:0] Q_228 = ITOP.iow0.arr[114]; +wire [79:0] Q_229 = ITOP.iow1.arr[114]; +wire [79:0] Q_230 = ITOP.iow0.arr[115]; +wire [79:0] Q_231 = ITOP.iow1.arr[115]; +wire [79:0] Q_232 = ITOP.iow0.arr[116]; +wire [79:0] Q_233 = ITOP.iow1.arr[116]; +wire [79:0] Q_234 = ITOP.iow0.arr[117]; +wire [79:0] Q_235 = ITOP.iow1.arr[117]; +wire [79:0] Q_236 = ITOP.iow0.arr[118]; +wire [79:0] Q_237 = ITOP.iow1.arr[118]; +wire [79:0] Q_238 = ITOP.iow0.arr[119]; +wire [79:0] Q_239 = ITOP.iow1.arr[119]; +wire [79:0] Q_240 = ITOP.iow0.arr[120]; +wire [79:0] Q_241 = ITOP.iow1.arr[120]; +wire [79:0] Q_242 = ITOP.iow0.arr[121]; +wire [79:0] Q_243 = ITOP.iow1.arr[121]; +wire [79:0] Q_244 = ITOP.iow0.arr[122]; +wire [79:0] Q_245 = ITOP.iow1.arr[122]; +wire [79:0] Q_246 = ITOP.iow0.arr[123]; +wire [79:0] Q_247 = ITOP.iow1.arr[123]; +wire [79:0] Q_248 = ITOP.iow0.arr[124]; +wire [79:0] Q_249 = ITOP.iow1.arr[124]; +wire [79:0] Q_250 = ITOP.iow0.arr[125]; +wire [79:0] Q_251 = ITOP.iow1.arr[125]; +wire [79:0] Q_252 = ITOP.iow0.arr[126]; +wire [79:0] Q_253 = ITOP.iow1.arr[126]; +wire [79:0] Q_254 = ITOP.iow0.arr[127]; +wire [79:0] Q_255 = ITOP.iow1.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [79:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [79:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [79:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [79:0] WD_FF; + reg [79:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [79:0] mem[255:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [79:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [79:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_256X80_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [79:0] WD; +input [7:0] RA, WA; +output [79:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [79:0] WDQ; + wire [79:0] WDBQ; + wire [79:0] WMNexp; + wire [79:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [79:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {80{1'b0}}; + assign SHFT = {80{1'b1}}; + reg [79:0] WDQ_pr; + wire [79:0] WDBQ_pr; + assign WMNexp = {80{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[79:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [79:0] dout; + wire [79:0] RD; + wire RD_rdnt; + wire [79:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [79:0] RDBYPASS = {80{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 256 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 256 --> ['1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [79:0] force_x; +`ifndef SYNTHESIS + assign force_x = {80{1'bx}}; +`else + assign force_x = {80{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [79:0] rmuxd0, rmuxd1; + wire [79:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {80{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {80{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {80{RdClk0}} & ~dout0 ; + assign rmuxd1 = {80{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[79:0] <= (rmuxd0[79:0] | rmuxd1[79:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_256X80_GL_M2_D2_ram # (128, 80, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_256X80_GL_M2_D2_ram # (128, 80, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [7:0] addr; + input [79:0] data; + reg [79:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[7:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[7:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [79:0] mem_read_bank; +input [7:0] addr; +reg [79:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[7:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[7:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_256X80_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 80; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [191:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [191:0] val; + integer i; + begin + val = {192{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [191:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [191:0] mem_phys_read_padr; +input [4:0] addr; + reg [191:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [191:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=191; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [191:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [191:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [191:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=191; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [191:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [191:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [191:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [191:0] data; + reg [191:0] wr[0:0]; + integer i; + begin + for (i=0; i<=191; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [191:0] mon_bit_w; +input [4:0] addr; + reg [191:0] mon_row; + reg [191:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=191; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [191:0] mon_bit_r; +input [4:0] addr; + reg [191:0] mon_row; + reg [191:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=191; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [191:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [191:0] Q_0 = ITOP.iow0.arr[0]; +wire [191:0] Q_1 = ITOP.iow0.arr[1]; +wire [191:0] Q_2 = ITOP.iow0.arr[2]; +wire [191:0] Q_3 = ITOP.iow0.arr[3]; +wire [191:0] Q_4 = ITOP.iow0.arr[4]; +wire [191:0] Q_5 = ITOP.iow0.arr[5]; +wire [191:0] Q_6 = ITOP.iow0.arr[6]; +wire [191:0] Q_7 = ITOP.iow0.arr[7]; +wire [191:0] Q_8 = ITOP.iow0.arr[8]; +wire [191:0] Q_9 = ITOP.iow0.arr[9]; +wire [191:0] Q_10 = ITOP.iow0.arr[10]; +wire [191:0] Q_11 = ITOP.iow0.arr[11]; +wire [191:0] Q_12 = ITOP.iow0.arr[12]; +wire [191:0] Q_13 = ITOP.iow0.arr[13]; +wire [191:0] Q_14 = ITOP.iow0.arr[14]; +wire [191:0] Q_15 = ITOP.iow0.arr[15]; +wire [191:0] Q_16 = ITOP.iow0.arr[16]; +wire [191:0] Q_17 = ITOP.iow0.arr[17]; +wire [191:0] Q_18 = ITOP.iow0.arr[18]; +wire [191:0] Q_19 = ITOP.iow0.arr[19]; +wire [191:0] Q_20 = ITOP.iow0.arr[20]; +wire [191:0] Q_21 = ITOP.iow0.arr[21]; +wire [191:0] Q_22 = ITOP.iow0.arr[22]; +wire [191:0] Q_23 = ITOP.iow0.arr[23]; +wire [191:0] Q_24 = ITOP.iow0.arr[24]; +wire [191:0] Q_25 = ITOP.iow0.arr[25]; +wire [191:0] Q_26 = ITOP.iow0.arr[26]; +wire [191:0] Q_27 = ITOP.iow0.arr[27]; +wire [191:0] Q_28 = ITOP.iow0.arr[28]; +wire [191:0] Q_29 = ITOP.iow0.arr[29]; +wire [191:0] Q_30 = ITOP.iow0.arr[30]; +wire [191:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [191:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [191:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [191:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [191:0] WD_FF; + reg [191:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [191:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [191:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [191:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X192_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [191:0] WD; +input [6:0] RA, WA; +output [191:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [191:0] WDQ; + wire [191:0] WDBQ; + wire [191:0] WMNexp; + wire [191:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [191:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {192{1'b0}}; + assign SHFT = {192{1'b1}}; + reg [191:0] WDQ_pr; + wire [191:0] WDBQ_pr; + assign WMNexp = {192{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[191:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [191:0] dout; + wire [191:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [191:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [191:0] RDBYPASS = {192{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [191:0] force_x; +`ifndef SYNTHESIS + assign force_x = {192{1'bx}}; +`else + assign force_x = {192{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [191:0] rmuxd0; + wire [191:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {192{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {192{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[191:0] <= (rmuxd0[191:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X192_GL_M1_D2_ram # (32, 192, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [191:0] data; + reg [191:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [191:0] mem_read_bank; +input [4:0] addr; +reg [191:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X192_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 192; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [191:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [191:0] val; + integer i; + begin + val = {192{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [191:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [191:0] mem_phys_read_padr; +input [4:0] addr; + reg [191:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [191:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=191; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [191:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [191:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [191:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=191; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [191:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [191:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [192-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {192 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {192 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [191:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [191:0] data; + reg [191:0] wr[0:0]; + integer i; + begin + for (i=0; i<=191; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [191:0] mon_bit_w; +input [4:0] addr; + reg [191:0] mon_row; + reg [191:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=191; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [191:0] mon_bit_r; +input [4:0] addr; + reg [191:0] mon_row; + reg [191:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=191; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [191:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<192; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [191:0] Q_0 = ITOP.iow0.arr[0]; +wire [191:0] Q_1 = ITOP.iow0.arr[1]; +wire [191:0] Q_2 = ITOP.iow0.arr[2]; +wire [191:0] Q_3 = ITOP.iow0.arr[3]; +wire [191:0] Q_4 = ITOP.iow0.arr[4]; +wire [191:0] Q_5 = ITOP.iow0.arr[5]; +wire [191:0] Q_6 = ITOP.iow0.arr[6]; +wire [191:0] Q_7 = ITOP.iow0.arr[7]; +wire [191:0] Q_8 = ITOP.iow0.arr[8]; +wire [191:0] Q_9 = ITOP.iow0.arr[9]; +wire [191:0] Q_10 = ITOP.iow0.arr[10]; +wire [191:0] Q_11 = ITOP.iow0.arr[11]; +wire [191:0] Q_12 = ITOP.iow0.arr[12]; +wire [191:0] Q_13 = ITOP.iow0.arr[13]; +wire [191:0] Q_14 = ITOP.iow0.arr[14]; +wire [191:0] Q_15 = ITOP.iow0.arr[15]; +wire [191:0] Q_16 = ITOP.iow0.arr[16]; +wire [191:0] Q_17 = ITOP.iow0.arr[17]; +wire [191:0] Q_18 = ITOP.iow0.arr[18]; +wire [191:0] Q_19 = ITOP.iow0.arr[19]; +wire [191:0] Q_20 = ITOP.iow0.arr[20]; +wire [191:0] Q_21 = ITOP.iow0.arr[21]; +wire [191:0] Q_22 = ITOP.iow0.arr[22]; +wire [191:0] Q_23 = ITOP.iow0.arr[23]; +wire [191:0] Q_24 = ITOP.iow0.arr[24]; +wire [191:0] Q_25 = ITOP.iow0.arr[25]; +wire [191:0] Q_26 = ITOP.iow0.arr[26]; +wire [191:0] Q_27 = ITOP.iow0.arr[27]; +wire [191:0] Q_28 = ITOP.iow0.arr[28]; +wire [191:0] Q_29 = ITOP.iow0.arr[29]; +wire [191:0] Q_30 = ITOP.iow0.arr[30]; +wire [191:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [191:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [191:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [191:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [191:0] WD_FF; + reg [191:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [191:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [191:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [191:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X192_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [191:0] WD; +input [6:0] RA, WA; +output [191:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [191:0] WDQ; + wire [191:0] WDBQ; + wire [191:0] WMNexp; + wire [191:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [191:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {192{1'b0}}; + assign SHFT = {192{1'b1}}; + reg [191:0] WDQ_pr; + wire [191:0] WDBQ_pr; + assign WMNexp = {192{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[191:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [191:0] dout; + wire [191:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [191:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [191:0] RDBYPASS = {192{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [191:0] force_x; +`ifndef SYNTHESIS + assign force_x = {192{1'bx}}; +`else + assign force_x = {192{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [191:0] rmuxd0; + wire [191:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {192{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {192{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[191:0] <= (rmuxd0[191:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X192_GL_M1_D2_ram # (32, 192, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [191:0] data; + reg [191:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [191:0] mem_read_bank; +input [4:0] addr; +reg [191:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X192_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 192; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [223:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [223:0] val; + integer i; + begin + val = {224{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [223:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [223:0] mem_phys_read_padr; +input [4:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [223:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [223:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [223:0] data; + reg [223:0] wr[0:0]; + integer i; + begin + for (i=0; i<=223; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [223:0] mon_bit_w; +input [4:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [223:0] mon_bit_r; +input [4:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [223:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [223:0] Q_0 = ITOP.iow0.arr[0]; +wire [223:0] Q_1 = ITOP.iow0.arr[1]; +wire [223:0] Q_2 = ITOP.iow0.arr[2]; +wire [223:0] Q_3 = ITOP.iow0.arr[3]; +wire [223:0] Q_4 = ITOP.iow0.arr[4]; +wire [223:0] Q_5 = ITOP.iow0.arr[5]; +wire [223:0] Q_6 = ITOP.iow0.arr[6]; +wire [223:0] Q_7 = ITOP.iow0.arr[7]; +wire [223:0] Q_8 = ITOP.iow0.arr[8]; +wire [223:0] Q_9 = ITOP.iow0.arr[9]; +wire [223:0] Q_10 = ITOP.iow0.arr[10]; +wire [223:0] Q_11 = ITOP.iow0.arr[11]; +wire [223:0] Q_12 = ITOP.iow0.arr[12]; +wire [223:0] Q_13 = ITOP.iow0.arr[13]; +wire [223:0] Q_14 = ITOP.iow0.arr[14]; +wire [223:0] Q_15 = ITOP.iow0.arr[15]; +wire [223:0] Q_16 = ITOP.iow0.arr[16]; +wire [223:0] Q_17 = ITOP.iow0.arr[17]; +wire [223:0] Q_18 = ITOP.iow0.arr[18]; +wire [223:0] Q_19 = ITOP.iow0.arr[19]; +wire [223:0] Q_20 = ITOP.iow0.arr[20]; +wire [223:0] Q_21 = ITOP.iow0.arr[21]; +wire [223:0] Q_22 = ITOP.iow0.arr[22]; +wire [223:0] Q_23 = ITOP.iow0.arr[23]; +wire [223:0] Q_24 = ITOP.iow0.arr[24]; +wire [223:0] Q_25 = ITOP.iow0.arr[25]; +wire [223:0] Q_26 = ITOP.iow0.arr[26]; +wire [223:0] Q_27 = ITOP.iow0.arr[27]; +wire [223:0] Q_28 = ITOP.iow0.arr[28]; +wire [223:0] Q_29 = ITOP.iow0.arr[29]; +wire [223:0] Q_30 = ITOP.iow0.arr[30]; +wire [223:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [223:0] WD_FF; + reg [223:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [223:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [223:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [223:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X224_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [223:0] WD; +input [6:0] RA, WA; +output [223:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [223:0] WDQ; + wire [223:0] WDBQ; + wire [223:0] WMNexp; + wire [223:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [223:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {224{1'b0}}; + assign SHFT = {224{1'b1}}; + reg [223:0] WDQ_pr; + wire [223:0] WDBQ_pr; + assign WMNexp = {224{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[223:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [223:0] dout; + wire [223:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [223:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [223:0] RDBYPASS = {224{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [223:0] force_x; +`ifndef SYNTHESIS + assign force_x = {224{1'bx}}; +`else + assign force_x = {224{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [223:0] rmuxd0; + wire [223:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {224{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {224{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[223:0] <= (rmuxd0[223:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X224_GL_M1_D2_ram # (32, 224, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [223:0] data; + reg [223:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [223:0] mem_read_bank; +input [4:0] addr; +reg [223:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X224_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 224; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [223:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [223:0] val; + integer i; + begin + val = {224{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [223:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [223:0] mem_phys_read_padr; +input [4:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [223:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [223:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [223:0] data; + reg [223:0] wr[0:0]; + integer i; + begin + for (i=0; i<=223; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [223:0] mon_bit_w; +input [4:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [223:0] mon_bit_r; +input [4:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [223:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [223:0] Q_0 = ITOP.iow0.arr[0]; +wire [223:0] Q_1 = ITOP.iow0.arr[1]; +wire [223:0] Q_2 = ITOP.iow0.arr[2]; +wire [223:0] Q_3 = ITOP.iow0.arr[3]; +wire [223:0] Q_4 = ITOP.iow0.arr[4]; +wire [223:0] Q_5 = ITOP.iow0.arr[5]; +wire [223:0] Q_6 = ITOP.iow0.arr[6]; +wire [223:0] Q_7 = ITOP.iow0.arr[7]; +wire [223:0] Q_8 = ITOP.iow0.arr[8]; +wire [223:0] Q_9 = ITOP.iow0.arr[9]; +wire [223:0] Q_10 = ITOP.iow0.arr[10]; +wire [223:0] Q_11 = ITOP.iow0.arr[11]; +wire [223:0] Q_12 = ITOP.iow0.arr[12]; +wire [223:0] Q_13 = ITOP.iow0.arr[13]; +wire [223:0] Q_14 = ITOP.iow0.arr[14]; +wire [223:0] Q_15 = ITOP.iow0.arr[15]; +wire [223:0] Q_16 = ITOP.iow0.arr[16]; +wire [223:0] Q_17 = ITOP.iow0.arr[17]; +wire [223:0] Q_18 = ITOP.iow0.arr[18]; +wire [223:0] Q_19 = ITOP.iow0.arr[19]; +wire [223:0] Q_20 = ITOP.iow0.arr[20]; +wire [223:0] Q_21 = ITOP.iow0.arr[21]; +wire [223:0] Q_22 = ITOP.iow0.arr[22]; +wire [223:0] Q_23 = ITOP.iow0.arr[23]; +wire [223:0] Q_24 = ITOP.iow0.arr[24]; +wire [223:0] Q_25 = ITOP.iow0.arr[25]; +wire [223:0] Q_26 = ITOP.iow0.arr[26]; +wire [223:0] Q_27 = ITOP.iow0.arr[27]; +wire [223:0] Q_28 = ITOP.iow0.arr[28]; +wire [223:0] Q_29 = ITOP.iow0.arr[29]; +wire [223:0] Q_30 = ITOP.iow0.arr[30]; +wire [223:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [223:0] WD_FF; + reg [223:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [223:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [223:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [223:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X224_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [223:0] WD; +input [6:0] RA, WA; +output [223:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [223:0] WDQ; + wire [223:0] WDBQ; + wire [223:0] WMNexp; + wire [223:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [223:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {224{1'b0}}; + assign SHFT = {224{1'b1}}; + reg [223:0] WDQ_pr; + wire [223:0] WDBQ_pr; + assign WMNexp = {224{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[223:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [223:0] dout; + wire [223:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [223:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [223:0] RDBYPASS = {224{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [223:0] force_x; +`ifndef SYNTHESIS + assign force_x = {224{1'bx}}; +`else + assign force_x = {224{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [223:0] rmuxd0; + wire [223:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {224{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {224{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[223:0] <= (rmuxd0[223:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X224_GL_M1_D2_ram # (32, 224, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [223:0] data; + reg [223:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [223:0] mem_read_bank; +input [4:0] addr; +reg [223:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X224_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 224; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [255:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [255:0] val; + integer i; + begin + val = {256{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [255:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [4:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [255:0] data; + reg [255:0] wr[0:0]; + integer i; + begin + for (i=0; i<=255; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [4:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [4:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [255:0] Q_0 = ITOP.iow0.arr[0]; +wire [255:0] Q_1 = ITOP.iow0.arr[1]; +wire [255:0] Q_2 = ITOP.iow0.arr[2]; +wire [255:0] Q_3 = ITOP.iow0.arr[3]; +wire [255:0] Q_4 = ITOP.iow0.arr[4]; +wire [255:0] Q_5 = ITOP.iow0.arr[5]; +wire [255:0] Q_6 = ITOP.iow0.arr[6]; +wire [255:0] Q_7 = ITOP.iow0.arr[7]; +wire [255:0] Q_8 = ITOP.iow0.arr[8]; +wire [255:0] Q_9 = ITOP.iow0.arr[9]; +wire [255:0] Q_10 = ITOP.iow0.arr[10]; +wire [255:0] Q_11 = ITOP.iow0.arr[11]; +wire [255:0] Q_12 = ITOP.iow0.arr[12]; +wire [255:0] Q_13 = ITOP.iow0.arr[13]; +wire [255:0] Q_14 = ITOP.iow0.arr[14]; +wire [255:0] Q_15 = ITOP.iow0.arr[15]; +wire [255:0] Q_16 = ITOP.iow0.arr[16]; +wire [255:0] Q_17 = ITOP.iow0.arr[17]; +wire [255:0] Q_18 = ITOP.iow0.arr[18]; +wire [255:0] Q_19 = ITOP.iow0.arr[19]; +wire [255:0] Q_20 = ITOP.iow0.arr[20]; +wire [255:0] Q_21 = ITOP.iow0.arr[21]; +wire [255:0] Q_22 = ITOP.iow0.arr[22]; +wire [255:0] Q_23 = ITOP.iow0.arr[23]; +wire [255:0] Q_24 = ITOP.iow0.arr[24]; +wire [255:0] Q_25 = ITOP.iow0.arr[25]; +wire [255:0] Q_26 = ITOP.iow0.arr[26]; +wire [255:0] Q_27 = ITOP.iow0.arr[27]; +wire [255:0] Q_28 = ITOP.iow0.arr[28]; +wire [255:0] Q_29 = ITOP.iow0.arr[29]; +wire [255:0] Q_30 = ITOP.iow0.arr[30]; +wire [255:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [255:0] WD_FF; + reg [255:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [255:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [255:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [255:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X256_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [255:0] WD; +input [6:0] RA, WA; +output [255:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [255:0] WDQ; + wire [255:0] WDBQ; + wire [255:0] WMNexp; + wire [255:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [255:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {256{1'b0}}; + assign SHFT = {256{1'b1}}; + reg [255:0] WDQ_pr; + wire [255:0] WDBQ_pr; + assign WMNexp = {256{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[255:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [255:0] dout; + wire [255:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [255:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [255:0] RDBYPASS = {256{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [255:0] force_x; +`ifndef SYNTHESIS + assign force_x = {256{1'bx}}; +`else + assign force_x = {256{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [255:0] rmuxd0; + wire [255:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {256{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {256{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[255:0] <= (rmuxd0[255:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X256_GL_M1_D2_ram # (32, 256, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [255:0] data; + reg [255:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [255:0] mem_read_bank; +input [4:0] addr; +reg [255:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X256_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 256; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [255:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [255:0] val; + integer i; + begin + val = {256{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [255:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [4:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [255:0] data; + reg [255:0] wr[0:0]; + integer i; + begin + for (i=0; i<=255; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [4:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [4:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [255:0] Q_0 = ITOP.iow0.arr[0]; +wire [255:0] Q_1 = ITOP.iow0.arr[1]; +wire [255:0] Q_2 = ITOP.iow0.arr[2]; +wire [255:0] Q_3 = ITOP.iow0.arr[3]; +wire [255:0] Q_4 = ITOP.iow0.arr[4]; +wire [255:0] Q_5 = ITOP.iow0.arr[5]; +wire [255:0] Q_6 = ITOP.iow0.arr[6]; +wire [255:0] Q_7 = ITOP.iow0.arr[7]; +wire [255:0] Q_8 = ITOP.iow0.arr[8]; +wire [255:0] Q_9 = ITOP.iow0.arr[9]; +wire [255:0] Q_10 = ITOP.iow0.arr[10]; +wire [255:0] Q_11 = ITOP.iow0.arr[11]; +wire [255:0] Q_12 = ITOP.iow0.arr[12]; +wire [255:0] Q_13 = ITOP.iow0.arr[13]; +wire [255:0] Q_14 = ITOP.iow0.arr[14]; +wire [255:0] Q_15 = ITOP.iow0.arr[15]; +wire [255:0] Q_16 = ITOP.iow0.arr[16]; +wire [255:0] Q_17 = ITOP.iow0.arr[17]; +wire [255:0] Q_18 = ITOP.iow0.arr[18]; +wire [255:0] Q_19 = ITOP.iow0.arr[19]; +wire [255:0] Q_20 = ITOP.iow0.arr[20]; +wire [255:0] Q_21 = ITOP.iow0.arr[21]; +wire [255:0] Q_22 = ITOP.iow0.arr[22]; +wire [255:0] Q_23 = ITOP.iow0.arr[23]; +wire [255:0] Q_24 = ITOP.iow0.arr[24]; +wire [255:0] Q_25 = ITOP.iow0.arr[25]; +wire [255:0] Q_26 = ITOP.iow0.arr[26]; +wire [255:0] Q_27 = ITOP.iow0.arr[27]; +wire [255:0] Q_28 = ITOP.iow0.arr[28]; +wire [255:0] Q_29 = ITOP.iow0.arr[29]; +wire [255:0] Q_30 = ITOP.iow0.arr[30]; +wire [255:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [255:0] WD_FF; + reg [255:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [255:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [255:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [255:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X256_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [255:0] WD; +input [6:0] RA, WA; +output [255:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [255:0] WDQ; + wire [255:0] WDBQ; + wire [255:0] WMNexp; + wire [255:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [255:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {256{1'b0}}; + assign SHFT = {256{1'b1}}; + reg [255:0] WDQ_pr; + wire [255:0] WDBQ_pr; + assign WMNexp = {256{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[255:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [255:0] dout; + wire [255:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [255:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [255:0] RDBYPASS = {256{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [255:0] force_x; +`ifndef SYNTHESIS + assign force_x = {256{1'bx}}; +`else + assign force_x = {256{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [255:0] rmuxd0; + wire [255:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {256{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {256{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[255:0] <= (rmuxd0[255:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X256_GL_M1_D2_ram # (32, 256, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [255:0] data; + reg [255:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [255:0] mem_read_bank; +input [4:0] addr; +reg [255:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X256_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 256; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [271:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [271:0] val; + integer i; + begin + val = {272{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [271:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [271:0] mem_phys_read_padr; +input [4:0] addr; + reg [271:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [271:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=271; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [271:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [271:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [271:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=271; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [271:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [271:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [271:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [271:0] data; + reg [271:0] wr[0:0]; + integer i; + begin + for (i=0; i<=271; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [271:0] mon_bit_w; +input [4:0] addr; + reg [271:0] mon_row; + reg [271:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=271; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [271:0] mon_bit_r; +input [4:0] addr; + reg [271:0] mon_row; + reg [271:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=271; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [271:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [271:0] Q_0 = ITOP.iow0.arr[0]; +wire [271:0] Q_1 = ITOP.iow0.arr[1]; +wire [271:0] Q_2 = ITOP.iow0.arr[2]; +wire [271:0] Q_3 = ITOP.iow0.arr[3]; +wire [271:0] Q_4 = ITOP.iow0.arr[4]; +wire [271:0] Q_5 = ITOP.iow0.arr[5]; +wire [271:0] Q_6 = ITOP.iow0.arr[6]; +wire [271:0] Q_7 = ITOP.iow0.arr[7]; +wire [271:0] Q_8 = ITOP.iow0.arr[8]; +wire [271:0] Q_9 = ITOP.iow0.arr[9]; +wire [271:0] Q_10 = ITOP.iow0.arr[10]; +wire [271:0] Q_11 = ITOP.iow0.arr[11]; +wire [271:0] Q_12 = ITOP.iow0.arr[12]; +wire [271:0] Q_13 = ITOP.iow0.arr[13]; +wire [271:0] Q_14 = ITOP.iow0.arr[14]; +wire [271:0] Q_15 = ITOP.iow0.arr[15]; +wire [271:0] Q_16 = ITOP.iow0.arr[16]; +wire [271:0] Q_17 = ITOP.iow0.arr[17]; +wire [271:0] Q_18 = ITOP.iow0.arr[18]; +wire [271:0] Q_19 = ITOP.iow0.arr[19]; +wire [271:0] Q_20 = ITOP.iow0.arr[20]; +wire [271:0] Q_21 = ITOP.iow0.arr[21]; +wire [271:0] Q_22 = ITOP.iow0.arr[22]; +wire [271:0] Q_23 = ITOP.iow0.arr[23]; +wire [271:0] Q_24 = ITOP.iow0.arr[24]; +wire [271:0] Q_25 = ITOP.iow0.arr[25]; +wire [271:0] Q_26 = ITOP.iow0.arr[26]; +wire [271:0] Q_27 = ITOP.iow0.arr[27]; +wire [271:0] Q_28 = ITOP.iow0.arr[28]; +wire [271:0] Q_29 = ITOP.iow0.arr[29]; +wire [271:0] Q_30 = ITOP.iow0.arr[30]; +wire [271:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [271:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [271:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [271:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [271:0] WD_FF; + reg [271:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [271:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [271:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [271:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X272_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [271:0] WD; +input [6:0] RA, WA; +output [271:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [271:0] WDQ; + wire [271:0] WDBQ; + wire [271:0] WMNexp; + wire [271:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [271:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {272{1'b0}}; + assign SHFT = {272{1'b1}}; + reg [271:0] WDQ_pr; + wire [271:0] WDBQ_pr; + assign WMNexp = {272{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[271:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [271:0] dout; + wire [271:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [271:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [271:0] RDBYPASS = {272{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [271:0] force_x; +`ifndef SYNTHESIS + assign force_x = {272{1'bx}}; +`else + assign force_x = {272{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [271:0] rmuxd0; + wire [271:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {272{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {272{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[271:0] <= (rmuxd0[271:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X272_GL_M1_D2_ram # (32, 272, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [271:0] data; + reg [271:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [271:0] mem_read_bank; +input [4:0] addr; +reg [271:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X272_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 272; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [271:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [271:0] val; + integer i; + begin + val = {272{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [271:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [271:0] mem_phys_read_padr; +input [4:0] addr; + reg [271:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [271:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=271; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [271:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [271:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [271:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=271; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [271:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [271:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [272-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {272 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {272 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [271:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [271:0] data; + reg [271:0] wr[0:0]; + integer i; + begin + for (i=0; i<=271; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [271:0] mon_bit_w; +input [4:0] addr; + reg [271:0] mon_row; + reg [271:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=271; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [271:0] mon_bit_r; +input [4:0] addr; + reg [271:0] mon_row; + reg [271:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=271; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [271:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<272; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [271:0] Q_0 = ITOP.iow0.arr[0]; +wire [271:0] Q_1 = ITOP.iow0.arr[1]; +wire [271:0] Q_2 = ITOP.iow0.arr[2]; +wire [271:0] Q_3 = ITOP.iow0.arr[3]; +wire [271:0] Q_4 = ITOP.iow0.arr[4]; +wire [271:0] Q_5 = ITOP.iow0.arr[5]; +wire [271:0] Q_6 = ITOP.iow0.arr[6]; +wire [271:0] Q_7 = ITOP.iow0.arr[7]; +wire [271:0] Q_8 = ITOP.iow0.arr[8]; +wire [271:0] Q_9 = ITOP.iow0.arr[9]; +wire [271:0] Q_10 = ITOP.iow0.arr[10]; +wire [271:0] Q_11 = ITOP.iow0.arr[11]; +wire [271:0] Q_12 = ITOP.iow0.arr[12]; +wire [271:0] Q_13 = ITOP.iow0.arr[13]; +wire [271:0] Q_14 = ITOP.iow0.arr[14]; +wire [271:0] Q_15 = ITOP.iow0.arr[15]; +wire [271:0] Q_16 = ITOP.iow0.arr[16]; +wire [271:0] Q_17 = ITOP.iow0.arr[17]; +wire [271:0] Q_18 = ITOP.iow0.arr[18]; +wire [271:0] Q_19 = ITOP.iow0.arr[19]; +wire [271:0] Q_20 = ITOP.iow0.arr[20]; +wire [271:0] Q_21 = ITOP.iow0.arr[21]; +wire [271:0] Q_22 = ITOP.iow0.arr[22]; +wire [271:0] Q_23 = ITOP.iow0.arr[23]; +wire [271:0] Q_24 = ITOP.iow0.arr[24]; +wire [271:0] Q_25 = ITOP.iow0.arr[25]; +wire [271:0] Q_26 = ITOP.iow0.arr[26]; +wire [271:0] Q_27 = ITOP.iow0.arr[27]; +wire [271:0] Q_28 = ITOP.iow0.arr[28]; +wire [271:0] Q_29 = ITOP.iow0.arr[29]; +wire [271:0] Q_30 = ITOP.iow0.arr[30]; +wire [271:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [271:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [271:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [271:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [271:0] WD_FF; + reg [271:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [271:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [271:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [271:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X272_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [271:0] WD; +input [6:0] RA, WA; +output [271:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [271:0] WDQ; + wire [271:0] WDBQ; + wire [271:0] WMNexp; + wire [271:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [271:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {272{1'b0}}; + assign SHFT = {272{1'b1}}; + reg [271:0] WDQ_pr; + wire [271:0] WDBQ_pr; + assign WMNexp = {272{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[271:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [271:0] dout; + wire [271:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [271:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [271:0] RDBYPASS = {272{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [271:0] force_x; +`ifndef SYNTHESIS + assign force_x = {272{1'bx}}; +`else + assign force_x = {272{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [271:0] rmuxd0; + wire [271:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {272{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {272{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[271:0] <= (rmuxd0[271:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X272_GL_M1_D2_ram # (32, 272, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [271:0] data; + reg [271:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [271:0] mem_read_bank; +input [4:0] addr; +reg [271:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X272_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 272; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [287:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [287:0] val; + integer i; + begin + val = {288{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [287:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [4:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [287:0] data; + reg [287:0] wr[0:0]; + integer i; + begin + for (i=0; i<=287; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [4:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [4:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [287:0] Q_0 = ITOP.iow0.arr[0]; +wire [287:0] Q_1 = ITOP.iow0.arr[1]; +wire [287:0] Q_2 = ITOP.iow0.arr[2]; +wire [287:0] Q_3 = ITOP.iow0.arr[3]; +wire [287:0] Q_4 = ITOP.iow0.arr[4]; +wire [287:0] Q_5 = ITOP.iow0.arr[5]; +wire [287:0] Q_6 = ITOP.iow0.arr[6]; +wire [287:0] Q_7 = ITOP.iow0.arr[7]; +wire [287:0] Q_8 = ITOP.iow0.arr[8]; +wire [287:0] Q_9 = ITOP.iow0.arr[9]; +wire [287:0] Q_10 = ITOP.iow0.arr[10]; +wire [287:0] Q_11 = ITOP.iow0.arr[11]; +wire [287:0] Q_12 = ITOP.iow0.arr[12]; +wire [287:0] Q_13 = ITOP.iow0.arr[13]; +wire [287:0] Q_14 = ITOP.iow0.arr[14]; +wire [287:0] Q_15 = ITOP.iow0.arr[15]; +wire [287:0] Q_16 = ITOP.iow0.arr[16]; +wire [287:0] Q_17 = ITOP.iow0.arr[17]; +wire [287:0] Q_18 = ITOP.iow0.arr[18]; +wire [287:0] Q_19 = ITOP.iow0.arr[19]; +wire [287:0] Q_20 = ITOP.iow0.arr[20]; +wire [287:0] Q_21 = ITOP.iow0.arr[21]; +wire [287:0] Q_22 = ITOP.iow0.arr[22]; +wire [287:0] Q_23 = ITOP.iow0.arr[23]; +wire [287:0] Q_24 = ITOP.iow0.arr[24]; +wire [287:0] Q_25 = ITOP.iow0.arr[25]; +wire [287:0] Q_26 = ITOP.iow0.arr[26]; +wire [287:0] Q_27 = ITOP.iow0.arr[27]; +wire [287:0] Q_28 = ITOP.iow0.arr[28]; +wire [287:0] Q_29 = ITOP.iow0.arr[29]; +wire [287:0] Q_30 = ITOP.iow0.arr[30]; +wire [287:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [287:0] WD_FF; + reg [287:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [287:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [287:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [287:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X288_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [287:0] WD; +input [6:0] RA, WA; +output [287:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [287:0] WDQ; + wire [287:0] WDBQ; + wire [287:0] WMNexp; + wire [287:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [287:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {288{1'b0}}; + assign SHFT = {288{1'b1}}; + reg [287:0] WDQ_pr; + wire [287:0] WDBQ_pr; + assign WMNexp = {288{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[287:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [287:0] dout; + wire [287:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [287:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [287:0] RDBYPASS = {288{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [287:0] force_x; +`ifndef SYNTHESIS + assign force_x = {288{1'bx}}; +`else + assign force_x = {288{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [287:0] rmuxd0; + wire [287:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {288{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {288{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[287:0] <= (rmuxd0[287:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X288_GL_M1_D2_ram # (32, 288, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [287:0] data; + reg [287:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [287:0] mem_read_bank; +input [4:0] addr; +reg [287:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X288_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 288; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [287:0] val; + integer i; + begin + for (i=0; i<32; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [287:0] val; + integer i; + begin + val = {288{fill_bit}}; + for (i=0; i<32; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [4:0] addr; + reg [287:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [4:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [4:0] addr; + reg [4:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [4:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [4:0] addr; +input [287:0] data; + reg [287:0] wr[0:0]; + integer i; + begin + for (i=0; i<=287; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [4:0] mem_log_to_phys_adr; +input [4:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [4:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [4:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [4:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=32;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<32; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [287:0] Q_0 = ITOP.iow0.arr[0]; +wire [287:0] Q_1 = ITOP.iow0.arr[1]; +wire [287:0] Q_2 = ITOP.iow0.arr[2]; +wire [287:0] Q_3 = ITOP.iow0.arr[3]; +wire [287:0] Q_4 = ITOP.iow0.arr[4]; +wire [287:0] Q_5 = ITOP.iow0.arr[5]; +wire [287:0] Q_6 = ITOP.iow0.arr[6]; +wire [287:0] Q_7 = ITOP.iow0.arr[7]; +wire [287:0] Q_8 = ITOP.iow0.arr[8]; +wire [287:0] Q_9 = ITOP.iow0.arr[9]; +wire [287:0] Q_10 = ITOP.iow0.arr[10]; +wire [287:0] Q_11 = ITOP.iow0.arr[11]; +wire [287:0] Q_12 = ITOP.iow0.arr[12]; +wire [287:0] Q_13 = ITOP.iow0.arr[13]; +wire [287:0] Q_14 = ITOP.iow0.arr[14]; +wire [287:0] Q_15 = ITOP.iow0.arr[15]; +wire [287:0] Q_16 = ITOP.iow0.arr[16]; +wire [287:0] Q_17 = ITOP.iow0.arr[17]; +wire [287:0] Q_18 = ITOP.iow0.arr[18]; +wire [287:0] Q_19 = ITOP.iow0.arr[19]; +wire [287:0] Q_20 = ITOP.iow0.arr[20]; +wire [287:0] Q_21 = ITOP.iow0.arr[21]; +wire [287:0] Q_22 = ITOP.iow0.arr[22]; +wire [287:0] Q_23 = ITOP.iow0.arr[23]; +wire [287:0] Q_24 = ITOP.iow0.arr[24]; +wire [287:0] Q_25 = ITOP.iow0.arr[25]; +wire [287:0] Q_26 = ITOP.iow0.arr[26]; +wire [287:0] Q_27 = ITOP.iow0.arr[27]; +wire [287:0] Q_28 = ITOP.iow0.arr[28]; +wire [287:0] Q_29 = ITOP.iow0.arr[29]; +wire [287:0] Q_30 = ITOP.iow0.arr[30]; +wire [287:0] Q_31 = ITOP.iow0.arr[31]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [287:0] WD_FF; + reg [287:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [287:0] mem[31:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [287:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [287:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_32X288_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [287:0] WD; +input [6:0] RA, WA; +output [287:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [287:0] WDQ; + wire [287:0] WDBQ; + wire [287:0] WMNexp; + wire [287:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [287:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {288{1'b0}}; + assign SHFT = {288{1'b1}}; + reg [287:0] WDQ_pr; + wire [287:0] WDBQ_pr; + assign WMNexp = {288{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[287:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [287:0] dout; + wire [287:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [287:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [287:0] RDBYPASS = {288{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 2 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 32 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:5]); +// Max address is 32 --> ['1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [287:0] force_x; +`ifndef SYNTHESIS + assign force_x = {288{1'bx}}; +`else + assign force_x = {288{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [287:0] rmuxd0; + wire [287:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {288{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {288{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[287:0] <= (rmuxd0[287:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_32X288_GL_M1_D2_ram # (32, 288, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [4:0] addr; + input [287:0] data; + reg [287:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[4:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [287:0] mem_read_bank; +input [4:0] addr; +reg [287:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_32X288_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 32; +parameter bits = 288; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [39:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [39:0] val; + integer i; + begin + val = {40{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [39:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [40-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {40 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {40 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [159:0] mem_phys_read_padr; +input [6:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [39:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=39; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [159:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [39:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=39; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [159:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [39:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 40'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 40'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 40'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 40'bx; + for (i=0; i<=39; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [159:0] data; + reg [39:0] wr[3:0]; + integer i; + begin + for (i=0; i<=39; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [159:0] mon_bit_w; +input [6:0] addr; + reg [159:0] mon_row; + reg [39:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=39; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [159:0] mon_bit_r; +input [6:0] addr; + reg [159:0] mon_row; + reg [39:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=39; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [159:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [39:0] Q_0 = ITOP.iow0.arr[0]; +wire [39:0] Q_1 = ITOP.iow1.arr[0]; +wire [39:0] Q_2 = ITOP.iow2.arr[0]; +wire [39:0] Q_3 = ITOP.iow3.arr[0]; +wire [39:0] Q_4 = ITOP.iow0.arr[1]; +wire [39:0] Q_5 = ITOP.iow1.arr[1]; +wire [39:0] Q_6 = ITOP.iow2.arr[1]; +wire [39:0] Q_7 = ITOP.iow3.arr[1]; +wire [39:0] Q_8 = ITOP.iow0.arr[2]; +wire [39:0] Q_9 = ITOP.iow1.arr[2]; +wire [39:0] Q_10 = ITOP.iow2.arr[2]; +wire [39:0] Q_11 = ITOP.iow3.arr[2]; +wire [39:0] Q_12 = ITOP.iow0.arr[3]; +wire [39:0] Q_13 = ITOP.iow1.arr[3]; +wire [39:0] Q_14 = ITOP.iow2.arr[3]; +wire [39:0] Q_15 = ITOP.iow3.arr[3]; +wire [39:0] Q_16 = ITOP.iow0.arr[4]; +wire [39:0] Q_17 = ITOP.iow1.arr[4]; +wire [39:0] Q_18 = ITOP.iow2.arr[4]; +wire [39:0] Q_19 = ITOP.iow3.arr[4]; +wire [39:0] Q_20 = ITOP.iow0.arr[5]; +wire [39:0] Q_21 = ITOP.iow1.arr[5]; +wire [39:0] Q_22 = ITOP.iow2.arr[5]; +wire [39:0] Q_23 = ITOP.iow3.arr[5]; +wire [39:0] Q_24 = ITOP.iow0.arr[6]; +wire [39:0] Q_25 = ITOP.iow1.arr[6]; +wire [39:0] Q_26 = ITOP.iow2.arr[6]; +wire [39:0] Q_27 = ITOP.iow3.arr[6]; +wire [39:0] Q_28 = ITOP.iow0.arr[7]; +wire [39:0] Q_29 = ITOP.iow1.arr[7]; +wire [39:0] Q_30 = ITOP.iow2.arr[7]; +wire [39:0] Q_31 = ITOP.iow3.arr[7]; +wire [39:0] Q_32 = ITOP.iow0.arr[8]; +wire [39:0] Q_33 = ITOP.iow1.arr[8]; +wire [39:0] Q_34 = ITOP.iow2.arr[8]; +wire [39:0] Q_35 = ITOP.iow3.arr[8]; +wire [39:0] Q_36 = ITOP.iow0.arr[9]; +wire [39:0] Q_37 = ITOP.iow1.arr[9]; +wire [39:0] Q_38 = ITOP.iow2.arr[9]; +wire [39:0] Q_39 = ITOP.iow3.arr[9]; +wire [39:0] Q_40 = ITOP.iow0.arr[10]; +wire [39:0] Q_41 = ITOP.iow1.arr[10]; +wire [39:0] Q_42 = ITOP.iow2.arr[10]; +wire [39:0] Q_43 = ITOP.iow3.arr[10]; +wire [39:0] Q_44 = ITOP.iow0.arr[11]; +wire [39:0] Q_45 = ITOP.iow1.arr[11]; +wire [39:0] Q_46 = ITOP.iow2.arr[11]; +wire [39:0] Q_47 = ITOP.iow3.arr[11]; +wire [39:0] Q_48 = ITOP.iow0.arr[12]; +wire [39:0] Q_49 = ITOP.iow1.arr[12]; +wire [39:0] Q_50 = ITOP.iow2.arr[12]; +wire [39:0] Q_51 = ITOP.iow3.arr[12]; +wire [39:0] Q_52 = ITOP.iow0.arr[13]; +wire [39:0] Q_53 = ITOP.iow1.arr[13]; +wire [39:0] Q_54 = ITOP.iow2.arr[13]; +wire [39:0] Q_55 = ITOP.iow3.arr[13]; +wire [39:0] Q_56 = ITOP.iow0.arr[14]; +wire [39:0] Q_57 = ITOP.iow1.arr[14]; +wire [39:0] Q_58 = ITOP.iow2.arr[14]; +wire [39:0] Q_59 = ITOP.iow3.arr[14]; +wire [39:0] Q_60 = ITOP.iow0.arr[15]; +wire [39:0] Q_61 = ITOP.iow1.arr[15]; +wire [39:0] Q_62 = ITOP.iow2.arr[15]; +wire [39:0] Q_63 = ITOP.iow3.arr[15]; +wire [39:0] Q_64 = ITOP.iow0.arr[16]; +wire [39:0] Q_65 = ITOP.iow1.arr[16]; +wire [39:0] Q_66 = ITOP.iow2.arr[16]; +wire [39:0] Q_67 = ITOP.iow3.arr[16]; +wire [39:0] Q_68 = ITOP.iow0.arr[17]; +wire [39:0] Q_69 = ITOP.iow1.arr[17]; +wire [39:0] Q_70 = ITOP.iow2.arr[17]; +wire [39:0] Q_71 = ITOP.iow3.arr[17]; +wire [39:0] Q_72 = ITOP.iow0.arr[18]; +wire [39:0] Q_73 = ITOP.iow1.arr[18]; +wire [39:0] Q_74 = ITOP.iow2.arr[18]; +wire [39:0] Q_75 = ITOP.iow3.arr[18]; +wire [39:0] Q_76 = ITOP.iow0.arr[19]; +wire [39:0] Q_77 = ITOP.iow1.arr[19]; +wire [39:0] Q_78 = ITOP.iow2.arr[19]; +wire [39:0] Q_79 = ITOP.iow3.arr[19]; +wire [39:0] Q_80 = ITOP.iow0.arr[20]; +wire [39:0] Q_81 = ITOP.iow1.arr[20]; +wire [39:0] Q_82 = ITOP.iow2.arr[20]; +wire [39:0] Q_83 = ITOP.iow3.arr[20]; +wire [39:0] Q_84 = ITOP.iow0.arr[21]; +wire [39:0] Q_85 = ITOP.iow1.arr[21]; +wire [39:0] Q_86 = ITOP.iow2.arr[21]; +wire [39:0] Q_87 = ITOP.iow3.arr[21]; +wire [39:0] Q_88 = ITOP.iow0.arr[22]; +wire [39:0] Q_89 = ITOP.iow1.arr[22]; +wire [39:0] Q_90 = ITOP.iow2.arr[22]; +wire [39:0] Q_91 = ITOP.iow3.arr[22]; +wire [39:0] Q_92 = ITOP.iow0.arr[23]; +wire [39:0] Q_93 = ITOP.iow1.arr[23]; +wire [39:0] Q_94 = ITOP.iow2.arr[23]; +wire [39:0] Q_95 = ITOP.iow3.arr[23]; +wire [39:0] Q_96 = ITOP.iow0.arr[24]; +wire [39:0] Q_97 = ITOP.iow1.arr[24]; +wire [39:0] Q_98 = ITOP.iow2.arr[24]; +wire [39:0] Q_99 = ITOP.iow3.arr[24]; +wire [39:0] Q_100 = ITOP.iow0.arr[25]; +wire [39:0] Q_101 = ITOP.iow1.arr[25]; +wire [39:0] Q_102 = ITOP.iow2.arr[25]; +wire [39:0] Q_103 = ITOP.iow3.arr[25]; +wire [39:0] Q_104 = ITOP.iow0.arr[26]; +wire [39:0] Q_105 = ITOP.iow1.arr[26]; +wire [39:0] Q_106 = ITOP.iow2.arr[26]; +wire [39:0] Q_107 = ITOP.iow3.arr[26]; +wire [39:0] Q_108 = ITOP.iow0.arr[27]; +wire [39:0] Q_109 = ITOP.iow1.arr[27]; +wire [39:0] Q_110 = ITOP.iow2.arr[27]; +wire [39:0] Q_111 = ITOP.iow3.arr[27]; +wire [39:0] Q_112 = ITOP.iow0.arr[28]; +wire [39:0] Q_113 = ITOP.iow1.arr[28]; +wire [39:0] Q_114 = ITOP.iow2.arr[28]; +wire [39:0] Q_115 = ITOP.iow3.arr[28]; +wire [39:0] Q_116 = ITOP.iow0.arr[29]; +wire [39:0] Q_117 = ITOP.iow1.arr[29]; +wire [39:0] Q_118 = ITOP.iow2.arr[29]; +wire [39:0] Q_119 = ITOP.iow3.arr[29]; +wire [39:0] Q_120 = ITOP.iow0.arr[30]; +wire [39:0] Q_121 = ITOP.iow1.arr[30]; +wire [39:0] Q_122 = ITOP.iow2.arr[30]; +wire [39:0] Q_123 = ITOP.iow3.arr[30]; +wire [39:0] Q_124 = ITOP.iow0.arr[31]; +wire [39:0] Q_125 = ITOP.iow1.arr[31]; +wire [39:0] Q_126 = ITOP.iow2.arr[31]; +wire [39:0] Q_127 = ITOP.iow3.arr[31]; +wire [39:0] Q_128 = ITOP.iow0.arr[32]; +wire [39:0] Q_129 = ITOP.iow1.arr[32]; +wire [39:0] Q_130 = ITOP.iow2.arr[32]; +wire [39:0] Q_131 = ITOP.iow3.arr[32]; +wire [39:0] Q_132 = ITOP.iow0.arr[33]; +wire [39:0] Q_133 = ITOP.iow1.arr[33]; +wire [39:0] Q_134 = ITOP.iow2.arr[33]; +wire [39:0] Q_135 = ITOP.iow3.arr[33]; +wire [39:0] Q_136 = ITOP.iow0.arr[34]; +wire [39:0] Q_137 = ITOP.iow1.arr[34]; +wire [39:0] Q_138 = ITOP.iow2.arr[34]; +wire [39:0] Q_139 = ITOP.iow3.arr[34]; +wire [39:0] Q_140 = ITOP.iow0.arr[35]; +wire [39:0] Q_141 = ITOP.iow1.arr[35]; +wire [39:0] Q_142 = ITOP.iow2.arr[35]; +wire [39:0] Q_143 = ITOP.iow3.arr[35]; +wire [39:0] Q_144 = ITOP.iow0.arr[36]; +wire [39:0] Q_145 = ITOP.iow1.arr[36]; +wire [39:0] Q_146 = ITOP.iow2.arr[36]; +wire [39:0] Q_147 = ITOP.iow3.arr[36]; +wire [39:0] Q_148 = ITOP.iow0.arr[37]; +wire [39:0] Q_149 = ITOP.iow1.arr[37]; +wire [39:0] Q_150 = ITOP.iow2.arr[37]; +wire [39:0] Q_151 = ITOP.iow3.arr[37]; +wire [39:0] Q_152 = ITOP.iow0.arr[38]; +wire [39:0] Q_153 = ITOP.iow1.arr[38]; +wire [39:0] Q_154 = ITOP.iow2.arr[38]; +wire [39:0] Q_155 = ITOP.iow3.arr[38]; +wire [39:0] Q_156 = ITOP.iow0.arr[39]; +wire [39:0] Q_157 = ITOP.iow1.arr[39]; +wire [39:0] Q_158 = ITOP.iow2.arr[39]; +wire [39:0] Q_159 = ITOP.iow3.arr[39]; +wire [39:0] Q_160 = ITOP.iow0.arr[40]; +wire [39:0] Q_161 = ITOP.iow1.arr[40]; +wire [39:0] Q_162 = ITOP.iow2.arr[40]; +wire [39:0] Q_163 = ITOP.iow3.arr[40]; +wire [39:0] Q_164 = ITOP.iow0.arr[41]; +wire [39:0] Q_165 = ITOP.iow1.arr[41]; +wire [39:0] Q_166 = ITOP.iow2.arr[41]; +wire [39:0] Q_167 = ITOP.iow3.arr[41]; +wire [39:0] Q_168 = ITOP.iow0.arr[42]; +wire [39:0] Q_169 = ITOP.iow1.arr[42]; +wire [39:0] Q_170 = ITOP.iow2.arr[42]; +wire [39:0] Q_171 = ITOP.iow3.arr[42]; +wire [39:0] Q_172 = ITOP.iow0.arr[43]; +wire [39:0] Q_173 = ITOP.iow1.arr[43]; +wire [39:0] Q_174 = ITOP.iow2.arr[43]; +wire [39:0] Q_175 = ITOP.iow3.arr[43]; +wire [39:0] Q_176 = ITOP.iow0.arr[44]; +wire [39:0] Q_177 = ITOP.iow1.arr[44]; +wire [39:0] Q_178 = ITOP.iow2.arr[44]; +wire [39:0] Q_179 = ITOP.iow3.arr[44]; +wire [39:0] Q_180 = ITOP.iow0.arr[45]; +wire [39:0] Q_181 = ITOP.iow1.arr[45]; +wire [39:0] Q_182 = ITOP.iow2.arr[45]; +wire [39:0] Q_183 = ITOP.iow3.arr[45]; +wire [39:0] Q_184 = ITOP.iow0.arr[46]; +wire [39:0] Q_185 = ITOP.iow1.arr[46]; +wire [39:0] Q_186 = ITOP.iow2.arr[46]; +wire [39:0] Q_187 = ITOP.iow3.arr[46]; +wire [39:0] Q_188 = ITOP.iow0.arr[47]; +wire [39:0] Q_189 = ITOP.iow1.arr[47]; +wire [39:0] Q_190 = ITOP.iow2.arr[47]; +wire [39:0] Q_191 = ITOP.iow3.arr[47]; +wire [39:0] Q_192 = ITOP.iow0.arr[48]; +wire [39:0] Q_193 = ITOP.iow1.arr[48]; +wire [39:0] Q_194 = ITOP.iow2.arr[48]; +wire [39:0] Q_195 = ITOP.iow3.arr[48]; +wire [39:0] Q_196 = ITOP.iow0.arr[49]; +wire [39:0] Q_197 = ITOP.iow1.arr[49]; +wire [39:0] Q_198 = ITOP.iow2.arr[49]; +wire [39:0] Q_199 = ITOP.iow3.arr[49]; +wire [39:0] Q_200 = ITOP.iow0.arr[50]; +wire [39:0] Q_201 = ITOP.iow1.arr[50]; +wire [39:0] Q_202 = ITOP.iow2.arr[50]; +wire [39:0] Q_203 = ITOP.iow3.arr[50]; +wire [39:0] Q_204 = ITOP.iow0.arr[51]; +wire [39:0] Q_205 = ITOP.iow1.arr[51]; +wire [39:0] Q_206 = ITOP.iow2.arr[51]; +wire [39:0] Q_207 = ITOP.iow3.arr[51]; +wire [39:0] Q_208 = ITOP.iow0.arr[52]; +wire [39:0] Q_209 = ITOP.iow1.arr[52]; +wire [39:0] Q_210 = ITOP.iow2.arr[52]; +wire [39:0] Q_211 = ITOP.iow3.arr[52]; +wire [39:0] Q_212 = ITOP.iow0.arr[53]; +wire [39:0] Q_213 = ITOP.iow1.arr[53]; +wire [39:0] Q_214 = ITOP.iow2.arr[53]; +wire [39:0] Q_215 = ITOP.iow3.arr[53]; +wire [39:0] Q_216 = ITOP.iow0.arr[54]; +wire [39:0] Q_217 = ITOP.iow1.arr[54]; +wire [39:0] Q_218 = ITOP.iow2.arr[54]; +wire [39:0] Q_219 = ITOP.iow3.arr[54]; +wire [39:0] Q_220 = ITOP.iow0.arr[55]; +wire [39:0] Q_221 = ITOP.iow1.arr[55]; +wire [39:0] Q_222 = ITOP.iow2.arr[55]; +wire [39:0] Q_223 = ITOP.iow3.arr[55]; +wire [39:0] Q_224 = ITOP.iow0.arr[56]; +wire [39:0] Q_225 = ITOP.iow1.arr[56]; +wire [39:0] Q_226 = ITOP.iow2.arr[56]; +wire [39:0] Q_227 = ITOP.iow3.arr[56]; +wire [39:0] Q_228 = ITOP.iow0.arr[57]; +wire [39:0] Q_229 = ITOP.iow1.arr[57]; +wire [39:0] Q_230 = ITOP.iow2.arr[57]; +wire [39:0] Q_231 = ITOP.iow3.arr[57]; +wire [39:0] Q_232 = ITOP.iow0.arr[58]; +wire [39:0] Q_233 = ITOP.iow1.arr[58]; +wire [39:0] Q_234 = ITOP.iow2.arr[58]; +wire [39:0] Q_235 = ITOP.iow3.arr[58]; +wire [39:0] Q_236 = ITOP.iow0.arr[59]; +wire [39:0] Q_237 = ITOP.iow1.arr[59]; +wire [39:0] Q_238 = ITOP.iow2.arr[59]; +wire [39:0] Q_239 = ITOP.iow3.arr[59]; +wire [39:0] Q_240 = ITOP.iow0.arr[60]; +wire [39:0] Q_241 = ITOP.iow1.arr[60]; +wire [39:0] Q_242 = ITOP.iow2.arr[60]; +wire [39:0] Q_243 = ITOP.iow3.arr[60]; +wire [39:0] Q_244 = ITOP.iow0.arr[61]; +wire [39:0] Q_245 = ITOP.iow1.arr[61]; +wire [39:0] Q_246 = ITOP.iow2.arr[61]; +wire [39:0] Q_247 = ITOP.iow3.arr[61]; +wire [39:0] Q_248 = ITOP.iow0.arr[62]; +wire [39:0] Q_249 = ITOP.iow1.arr[62]; +wire [39:0] Q_250 = ITOP.iow2.arr[62]; +wire [39:0] Q_251 = ITOP.iow3.arr[62]; +wire [39:0] Q_252 = ITOP.iow0.arr[63]; +wire [39:0] Q_253 = ITOP.iow1.arr[63]; +wire [39:0] Q_254 = ITOP.iow2.arr[63]; +wire [39:0] Q_255 = ITOP.iow3.arr[63]; +wire [39:0] Q_256 = ITOP.iow0.arr[64]; +wire [39:0] Q_257 = ITOP.iow1.arr[64]; +wire [39:0] Q_258 = ITOP.iow2.arr[64]; +wire [39:0] Q_259 = ITOP.iow3.arr[64]; +wire [39:0] Q_260 = ITOP.iow0.arr[65]; +wire [39:0] Q_261 = ITOP.iow1.arr[65]; +wire [39:0] Q_262 = ITOP.iow2.arr[65]; +wire [39:0] Q_263 = ITOP.iow3.arr[65]; +wire [39:0] Q_264 = ITOP.iow0.arr[66]; +wire [39:0] Q_265 = ITOP.iow1.arr[66]; +wire [39:0] Q_266 = ITOP.iow2.arr[66]; +wire [39:0] Q_267 = ITOP.iow3.arr[66]; +wire [39:0] Q_268 = ITOP.iow0.arr[67]; +wire [39:0] Q_269 = ITOP.iow1.arr[67]; +wire [39:0] Q_270 = ITOP.iow2.arr[67]; +wire [39:0] Q_271 = ITOP.iow3.arr[67]; +wire [39:0] Q_272 = ITOP.iow0.arr[68]; +wire [39:0] Q_273 = ITOP.iow1.arr[68]; +wire [39:0] Q_274 = ITOP.iow2.arr[68]; +wire [39:0] Q_275 = ITOP.iow3.arr[68]; +wire [39:0] Q_276 = ITOP.iow0.arr[69]; +wire [39:0] Q_277 = ITOP.iow1.arr[69]; +wire [39:0] Q_278 = ITOP.iow2.arr[69]; +wire [39:0] Q_279 = ITOP.iow3.arr[69]; +wire [39:0] Q_280 = ITOP.iow0.arr[70]; +wire [39:0] Q_281 = ITOP.iow1.arr[70]; +wire [39:0] Q_282 = ITOP.iow2.arr[70]; +wire [39:0] Q_283 = ITOP.iow3.arr[70]; +wire [39:0] Q_284 = ITOP.iow0.arr[71]; +wire [39:0] Q_285 = ITOP.iow1.arr[71]; +wire [39:0] Q_286 = ITOP.iow2.arr[71]; +wire [39:0] Q_287 = ITOP.iow3.arr[71]; +wire [39:0] Q_288 = ITOP.iow0.arr[72]; +wire [39:0] Q_289 = ITOP.iow1.arr[72]; +wire [39:0] Q_290 = ITOP.iow2.arr[72]; +wire [39:0] Q_291 = ITOP.iow3.arr[72]; +wire [39:0] Q_292 = ITOP.iow0.arr[73]; +wire [39:0] Q_293 = ITOP.iow1.arr[73]; +wire [39:0] Q_294 = ITOP.iow2.arr[73]; +wire [39:0] Q_295 = ITOP.iow3.arr[73]; +wire [39:0] Q_296 = ITOP.iow0.arr[74]; +wire [39:0] Q_297 = ITOP.iow1.arr[74]; +wire [39:0] Q_298 = ITOP.iow2.arr[74]; +wire [39:0] Q_299 = ITOP.iow3.arr[74]; +wire [39:0] Q_300 = ITOP.iow0.arr[75]; +wire [39:0] Q_301 = ITOP.iow1.arr[75]; +wire [39:0] Q_302 = ITOP.iow2.arr[75]; +wire [39:0] Q_303 = ITOP.iow3.arr[75]; +wire [39:0] Q_304 = ITOP.iow0.arr[76]; +wire [39:0] Q_305 = ITOP.iow1.arr[76]; +wire [39:0] Q_306 = ITOP.iow2.arr[76]; +wire [39:0] Q_307 = ITOP.iow3.arr[76]; +wire [39:0] Q_308 = ITOP.iow0.arr[77]; +wire [39:0] Q_309 = ITOP.iow1.arr[77]; +wire [39:0] Q_310 = ITOP.iow2.arr[77]; +wire [39:0] Q_311 = ITOP.iow3.arr[77]; +wire [39:0] Q_312 = ITOP.iow0.arr[78]; +wire [39:0] Q_313 = ITOP.iow1.arr[78]; +wire [39:0] Q_314 = ITOP.iow2.arr[78]; +wire [39:0] Q_315 = ITOP.iow3.arr[78]; +wire [39:0] Q_316 = ITOP.iow0.arr[79]; +wire [39:0] Q_317 = ITOP.iow1.arr[79]; +wire [39:0] Q_318 = ITOP.iow2.arr[79]; +wire [39:0] Q_319 = ITOP.iow3.arr[79]; +wire [39:0] Q_320 = ITOP.iow0.arr[80]; +wire [39:0] Q_321 = ITOP.iow1.arr[80]; +wire [39:0] Q_322 = ITOP.iow2.arr[80]; +wire [39:0] Q_323 = ITOP.iow3.arr[80]; +wire [39:0] Q_324 = ITOP.iow0.arr[81]; +wire [39:0] Q_325 = ITOP.iow1.arr[81]; +wire [39:0] Q_326 = ITOP.iow2.arr[81]; +wire [39:0] Q_327 = ITOP.iow3.arr[81]; +wire [39:0] Q_328 = ITOP.iow0.arr[82]; +wire [39:0] Q_329 = ITOP.iow1.arr[82]; +wire [39:0] Q_330 = ITOP.iow2.arr[82]; +wire [39:0] Q_331 = ITOP.iow3.arr[82]; +wire [39:0] Q_332 = ITOP.iow0.arr[83]; +wire [39:0] Q_333 = ITOP.iow1.arr[83]; +wire [39:0] Q_334 = ITOP.iow2.arr[83]; +wire [39:0] Q_335 = ITOP.iow3.arr[83]; +wire [39:0] Q_336 = ITOP.iow0.arr[84]; +wire [39:0] Q_337 = ITOP.iow1.arr[84]; +wire [39:0] Q_338 = ITOP.iow2.arr[84]; +wire [39:0] Q_339 = ITOP.iow3.arr[84]; +wire [39:0] Q_340 = ITOP.iow0.arr[85]; +wire [39:0] Q_341 = ITOP.iow1.arr[85]; +wire [39:0] Q_342 = ITOP.iow2.arr[85]; +wire [39:0] Q_343 = ITOP.iow3.arr[85]; +wire [39:0] Q_344 = ITOP.iow0.arr[86]; +wire [39:0] Q_345 = ITOP.iow1.arr[86]; +wire [39:0] Q_346 = ITOP.iow2.arr[86]; +wire [39:0] Q_347 = ITOP.iow3.arr[86]; +wire [39:0] Q_348 = ITOP.iow0.arr[87]; +wire [39:0] Q_349 = ITOP.iow1.arr[87]; +wire [39:0] Q_350 = ITOP.iow2.arr[87]; +wire [39:0] Q_351 = ITOP.iow3.arr[87]; +wire [39:0] Q_352 = ITOP.iow0.arr[88]; +wire [39:0] Q_353 = ITOP.iow1.arr[88]; +wire [39:0] Q_354 = ITOP.iow2.arr[88]; +wire [39:0] Q_355 = ITOP.iow3.arr[88]; +wire [39:0] Q_356 = ITOP.iow0.arr[89]; +wire [39:0] Q_357 = ITOP.iow1.arr[89]; +wire [39:0] Q_358 = ITOP.iow2.arr[89]; +wire [39:0] Q_359 = ITOP.iow3.arr[89]; +wire [39:0] Q_360 = ITOP.iow0.arr[90]; +wire [39:0] Q_361 = ITOP.iow1.arr[90]; +wire [39:0] Q_362 = ITOP.iow2.arr[90]; +wire [39:0] Q_363 = ITOP.iow3.arr[90]; +wire [39:0] Q_364 = ITOP.iow0.arr[91]; +wire [39:0] Q_365 = ITOP.iow1.arr[91]; +wire [39:0] Q_366 = ITOP.iow2.arr[91]; +wire [39:0] Q_367 = ITOP.iow3.arr[91]; +wire [39:0] Q_368 = ITOP.iow0.arr[92]; +wire [39:0] Q_369 = ITOP.iow1.arr[92]; +wire [39:0] Q_370 = ITOP.iow2.arr[92]; +wire [39:0] Q_371 = ITOP.iow3.arr[92]; +wire [39:0] Q_372 = ITOP.iow0.arr[93]; +wire [39:0] Q_373 = ITOP.iow1.arr[93]; +wire [39:0] Q_374 = ITOP.iow2.arr[93]; +wire [39:0] Q_375 = ITOP.iow3.arr[93]; +wire [39:0] Q_376 = ITOP.iow0.arr[94]; +wire [39:0] Q_377 = ITOP.iow1.arr[94]; +wire [39:0] Q_378 = ITOP.iow2.arr[94]; +wire [39:0] Q_379 = ITOP.iow3.arr[94]; +wire [39:0] Q_380 = ITOP.iow0.arr[95]; +wire [39:0] Q_381 = ITOP.iow1.arr[95]; +wire [39:0] Q_382 = ITOP.iow2.arr[95]; +wire [39:0] Q_383 = ITOP.iow3.arr[95]; +wire [39:0] Q_384 = ITOP.iow0.arr[96]; +wire [39:0] Q_385 = ITOP.iow1.arr[96]; +wire [39:0] Q_386 = ITOP.iow2.arr[96]; +wire [39:0] Q_387 = ITOP.iow3.arr[96]; +wire [39:0] Q_388 = ITOP.iow0.arr[97]; +wire [39:0] Q_389 = ITOP.iow1.arr[97]; +wire [39:0] Q_390 = ITOP.iow2.arr[97]; +wire [39:0] Q_391 = ITOP.iow3.arr[97]; +wire [39:0] Q_392 = ITOP.iow0.arr[98]; +wire [39:0] Q_393 = ITOP.iow1.arr[98]; +wire [39:0] Q_394 = ITOP.iow2.arr[98]; +wire [39:0] Q_395 = ITOP.iow3.arr[98]; +wire [39:0] Q_396 = ITOP.iow0.arr[99]; +wire [39:0] Q_397 = ITOP.iow1.arr[99]; +wire [39:0] Q_398 = ITOP.iow2.arr[99]; +wire [39:0] Q_399 = ITOP.iow3.arr[99]; +wire [39:0] Q_400 = ITOP.iow0.arr[100]; +wire [39:0] Q_401 = ITOP.iow1.arr[100]; +wire [39:0] Q_402 = ITOP.iow2.arr[100]; +wire [39:0] Q_403 = ITOP.iow3.arr[100]; +wire [39:0] Q_404 = ITOP.iow0.arr[101]; +wire [39:0] Q_405 = ITOP.iow1.arr[101]; +wire [39:0] Q_406 = ITOP.iow2.arr[101]; +wire [39:0] Q_407 = ITOP.iow3.arr[101]; +wire [39:0] Q_408 = ITOP.iow0.arr[102]; +wire [39:0] Q_409 = ITOP.iow1.arr[102]; +wire [39:0] Q_410 = ITOP.iow2.arr[102]; +wire [39:0] Q_411 = ITOP.iow3.arr[102]; +wire [39:0] Q_412 = ITOP.iow0.arr[103]; +wire [39:0] Q_413 = ITOP.iow1.arr[103]; +wire [39:0] Q_414 = ITOP.iow2.arr[103]; +wire [39:0] Q_415 = ITOP.iow3.arr[103]; +wire [39:0] Q_416 = ITOP.iow0.arr[104]; +wire [39:0] Q_417 = ITOP.iow1.arr[104]; +wire [39:0] Q_418 = ITOP.iow2.arr[104]; +wire [39:0] Q_419 = ITOP.iow3.arr[104]; +wire [39:0] Q_420 = ITOP.iow0.arr[105]; +wire [39:0] Q_421 = ITOP.iow1.arr[105]; +wire [39:0] Q_422 = ITOP.iow2.arr[105]; +wire [39:0] Q_423 = ITOP.iow3.arr[105]; +wire [39:0] Q_424 = ITOP.iow0.arr[106]; +wire [39:0] Q_425 = ITOP.iow1.arr[106]; +wire [39:0] Q_426 = ITOP.iow2.arr[106]; +wire [39:0] Q_427 = ITOP.iow3.arr[106]; +wire [39:0] Q_428 = ITOP.iow0.arr[107]; +wire [39:0] Q_429 = ITOP.iow1.arr[107]; +wire [39:0] Q_430 = ITOP.iow2.arr[107]; +wire [39:0] Q_431 = ITOP.iow3.arr[107]; +wire [39:0] Q_432 = ITOP.iow0.arr[108]; +wire [39:0] Q_433 = ITOP.iow1.arr[108]; +wire [39:0] Q_434 = ITOP.iow2.arr[108]; +wire [39:0] Q_435 = ITOP.iow3.arr[108]; +wire [39:0] Q_436 = ITOP.iow0.arr[109]; +wire [39:0] Q_437 = ITOP.iow1.arr[109]; +wire [39:0] Q_438 = ITOP.iow2.arr[109]; +wire [39:0] Q_439 = ITOP.iow3.arr[109]; +wire [39:0] Q_440 = ITOP.iow0.arr[110]; +wire [39:0] Q_441 = ITOP.iow1.arr[110]; +wire [39:0] Q_442 = ITOP.iow2.arr[110]; +wire [39:0] Q_443 = ITOP.iow3.arr[110]; +wire [39:0] Q_444 = ITOP.iow0.arr[111]; +wire [39:0] Q_445 = ITOP.iow1.arr[111]; +wire [39:0] Q_446 = ITOP.iow2.arr[111]; +wire [39:0] Q_447 = ITOP.iow3.arr[111]; +wire [39:0] Q_448 = ITOP.iow0.arr[112]; +wire [39:0] Q_449 = ITOP.iow1.arr[112]; +wire [39:0] Q_450 = ITOP.iow2.arr[112]; +wire [39:0] Q_451 = ITOP.iow3.arr[112]; +wire [39:0] Q_452 = ITOP.iow0.arr[113]; +wire [39:0] Q_453 = ITOP.iow1.arr[113]; +wire [39:0] Q_454 = ITOP.iow2.arr[113]; +wire [39:0] Q_455 = ITOP.iow3.arr[113]; +wire [39:0] Q_456 = ITOP.iow0.arr[114]; +wire [39:0] Q_457 = ITOP.iow1.arr[114]; +wire [39:0] Q_458 = ITOP.iow2.arr[114]; +wire [39:0] Q_459 = ITOP.iow3.arr[114]; +wire [39:0] Q_460 = ITOP.iow0.arr[115]; +wire [39:0] Q_461 = ITOP.iow1.arr[115]; +wire [39:0] Q_462 = ITOP.iow2.arr[115]; +wire [39:0] Q_463 = ITOP.iow3.arr[115]; +wire [39:0] Q_464 = ITOP.iow0.arr[116]; +wire [39:0] Q_465 = ITOP.iow1.arr[116]; +wire [39:0] Q_466 = ITOP.iow2.arr[116]; +wire [39:0] Q_467 = ITOP.iow3.arr[116]; +wire [39:0] Q_468 = ITOP.iow0.arr[117]; +wire [39:0] Q_469 = ITOP.iow1.arr[117]; +wire [39:0] Q_470 = ITOP.iow2.arr[117]; +wire [39:0] Q_471 = ITOP.iow3.arr[117]; +wire [39:0] Q_472 = ITOP.iow0.arr[118]; +wire [39:0] Q_473 = ITOP.iow1.arr[118]; +wire [39:0] Q_474 = ITOP.iow2.arr[118]; +wire [39:0] Q_475 = ITOP.iow3.arr[118]; +wire [39:0] Q_476 = ITOP.iow0.arr[119]; +wire [39:0] Q_477 = ITOP.iow1.arr[119]; +wire [39:0] Q_478 = ITOP.iow2.arr[119]; +wire [39:0] Q_479 = ITOP.iow3.arr[119]; +wire [39:0] Q_480 = ITOP.iow0.arr[120]; +wire [39:0] Q_481 = ITOP.iow1.arr[120]; +wire [39:0] Q_482 = ITOP.iow2.arr[120]; +wire [39:0] Q_483 = ITOP.iow3.arr[120]; +wire [39:0] Q_484 = ITOP.iow0.arr[121]; +wire [39:0] Q_485 = ITOP.iow1.arr[121]; +wire [39:0] Q_486 = ITOP.iow2.arr[121]; +wire [39:0] Q_487 = ITOP.iow3.arr[121]; +wire [39:0] Q_488 = ITOP.iow0.arr[122]; +wire [39:0] Q_489 = ITOP.iow1.arr[122]; +wire [39:0] Q_490 = ITOP.iow2.arr[122]; +wire [39:0] Q_491 = ITOP.iow3.arr[122]; +wire [39:0] Q_492 = ITOP.iow0.arr[123]; +wire [39:0] Q_493 = ITOP.iow1.arr[123]; +wire [39:0] Q_494 = ITOP.iow2.arr[123]; +wire [39:0] Q_495 = ITOP.iow3.arr[123]; +wire [39:0] Q_496 = ITOP.iow0.arr[124]; +wire [39:0] Q_497 = ITOP.iow1.arr[124]; +wire [39:0] Q_498 = ITOP.iow2.arr[124]; +wire [39:0] Q_499 = ITOP.iow3.arr[124]; +wire [39:0] Q_500 = ITOP.iow0.arr[125]; +wire [39:0] Q_501 = ITOP.iow1.arr[125]; +wire [39:0] Q_502 = ITOP.iow2.arr[125]; +wire [39:0] Q_503 = ITOP.iow3.arr[125]; +wire [39:0] Q_504 = ITOP.iow0.arr[126]; +wire [39:0] Q_505 = ITOP.iow1.arr[126]; +wire [39:0] Q_506 = ITOP.iow2.arr[126]; +wire [39:0] Q_507 = ITOP.iow3.arr[126]; +wire [39:0] Q_508 = ITOP.iow0.arr[127]; +wire [39:0] Q_509 = ITOP.iow1.arr[127]; +wire [39:0] Q_510 = ITOP.iow2.arr[127]; +wire [39:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [39:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [39:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [39:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [39:0] WD_FF; + reg [39:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [39:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [39:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [39:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X40_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [39:0] WD; +input [8:0] RA, WA; +output [39:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [39:0] WDQ; + wire [39:0] WDBQ; + wire [39:0] WMNexp; + wire [39:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [39:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {40{1'b0}}; + assign SHFT = {40{1'b1}}; + reg [39:0] WDQ_pr; + wire [39:0] WDBQ_pr; + assign WMNexp = {40{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[39:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [39:0] dout; + wire [39:0] RD; + wire RD_rdnt; + wire [39:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [39:0] RDBYPASS = {40{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [39:0] force_x; +`ifndef SYNTHESIS + assign force_x = {40{1'bx}}; +`else + assign force_x = {40{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [39:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [39:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {40{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {40{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {40{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {40{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {40{RdClk0}} & ~dout0; + assign rmuxd1 = {40{RdClk1}} & ~dout1; + assign rmuxd2 = {40{RdClk2}} & ~dout2; + assign rmuxd3 = {40{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[39:0] <= (rmuxd0[39:0] | rmuxd1[39:0] | rmuxd2[39:0] | rmuxd3[39:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [39:0] data; + reg [39:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [39:0] mem_read_bank; +input [8:0] addr; +reg [39:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X40_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 40; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [39:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [39:0] val; + integer i; + begin + val = {40{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [39:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [40-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {40 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {40 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [159:0] mem_phys_read_padr; +input [6:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [39:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=39; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [159:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [39:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=39; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [159:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [39:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 40'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 40'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 40'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 40'bx; + for (i=0; i<=39; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [159:0] data; + reg [39:0] wr[3:0]; + integer i; + begin + for (i=0; i<=39; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [159:0] mon_bit_w; +input [6:0] addr; + reg [159:0] mon_row; + reg [39:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=39; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [159:0] mon_bit_r; +input [6:0] addr; + reg [159:0] mon_row; + reg [39:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=39; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [159:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [39:0] Q_0 = ITOP.iow0.arr[0]; +wire [39:0] Q_1 = ITOP.iow1.arr[0]; +wire [39:0] Q_2 = ITOP.iow2.arr[0]; +wire [39:0] Q_3 = ITOP.iow3.arr[0]; +wire [39:0] Q_4 = ITOP.iow0.arr[1]; +wire [39:0] Q_5 = ITOP.iow1.arr[1]; +wire [39:0] Q_6 = ITOP.iow2.arr[1]; +wire [39:0] Q_7 = ITOP.iow3.arr[1]; +wire [39:0] Q_8 = ITOP.iow0.arr[2]; +wire [39:0] Q_9 = ITOP.iow1.arr[2]; +wire [39:0] Q_10 = ITOP.iow2.arr[2]; +wire [39:0] Q_11 = ITOP.iow3.arr[2]; +wire [39:0] Q_12 = ITOP.iow0.arr[3]; +wire [39:0] Q_13 = ITOP.iow1.arr[3]; +wire [39:0] Q_14 = ITOP.iow2.arr[3]; +wire [39:0] Q_15 = ITOP.iow3.arr[3]; +wire [39:0] Q_16 = ITOP.iow0.arr[4]; +wire [39:0] Q_17 = ITOP.iow1.arr[4]; +wire [39:0] Q_18 = ITOP.iow2.arr[4]; +wire [39:0] Q_19 = ITOP.iow3.arr[4]; +wire [39:0] Q_20 = ITOP.iow0.arr[5]; +wire [39:0] Q_21 = ITOP.iow1.arr[5]; +wire [39:0] Q_22 = ITOP.iow2.arr[5]; +wire [39:0] Q_23 = ITOP.iow3.arr[5]; +wire [39:0] Q_24 = ITOP.iow0.arr[6]; +wire [39:0] Q_25 = ITOP.iow1.arr[6]; +wire [39:0] Q_26 = ITOP.iow2.arr[6]; +wire [39:0] Q_27 = ITOP.iow3.arr[6]; +wire [39:0] Q_28 = ITOP.iow0.arr[7]; +wire [39:0] Q_29 = ITOP.iow1.arr[7]; +wire [39:0] Q_30 = ITOP.iow2.arr[7]; +wire [39:0] Q_31 = ITOP.iow3.arr[7]; +wire [39:0] Q_32 = ITOP.iow0.arr[8]; +wire [39:0] Q_33 = ITOP.iow1.arr[8]; +wire [39:0] Q_34 = ITOP.iow2.arr[8]; +wire [39:0] Q_35 = ITOP.iow3.arr[8]; +wire [39:0] Q_36 = ITOP.iow0.arr[9]; +wire [39:0] Q_37 = ITOP.iow1.arr[9]; +wire [39:0] Q_38 = ITOP.iow2.arr[9]; +wire [39:0] Q_39 = ITOP.iow3.arr[9]; +wire [39:0] Q_40 = ITOP.iow0.arr[10]; +wire [39:0] Q_41 = ITOP.iow1.arr[10]; +wire [39:0] Q_42 = ITOP.iow2.arr[10]; +wire [39:0] Q_43 = ITOP.iow3.arr[10]; +wire [39:0] Q_44 = ITOP.iow0.arr[11]; +wire [39:0] Q_45 = ITOP.iow1.arr[11]; +wire [39:0] Q_46 = ITOP.iow2.arr[11]; +wire [39:0] Q_47 = ITOP.iow3.arr[11]; +wire [39:0] Q_48 = ITOP.iow0.arr[12]; +wire [39:0] Q_49 = ITOP.iow1.arr[12]; +wire [39:0] Q_50 = ITOP.iow2.arr[12]; +wire [39:0] Q_51 = ITOP.iow3.arr[12]; +wire [39:0] Q_52 = ITOP.iow0.arr[13]; +wire [39:0] Q_53 = ITOP.iow1.arr[13]; +wire [39:0] Q_54 = ITOP.iow2.arr[13]; +wire [39:0] Q_55 = ITOP.iow3.arr[13]; +wire [39:0] Q_56 = ITOP.iow0.arr[14]; +wire [39:0] Q_57 = ITOP.iow1.arr[14]; +wire [39:0] Q_58 = ITOP.iow2.arr[14]; +wire [39:0] Q_59 = ITOP.iow3.arr[14]; +wire [39:0] Q_60 = ITOP.iow0.arr[15]; +wire [39:0] Q_61 = ITOP.iow1.arr[15]; +wire [39:0] Q_62 = ITOP.iow2.arr[15]; +wire [39:0] Q_63 = ITOP.iow3.arr[15]; +wire [39:0] Q_64 = ITOP.iow0.arr[16]; +wire [39:0] Q_65 = ITOP.iow1.arr[16]; +wire [39:0] Q_66 = ITOP.iow2.arr[16]; +wire [39:0] Q_67 = ITOP.iow3.arr[16]; +wire [39:0] Q_68 = ITOP.iow0.arr[17]; +wire [39:0] Q_69 = ITOP.iow1.arr[17]; +wire [39:0] Q_70 = ITOP.iow2.arr[17]; +wire [39:0] Q_71 = ITOP.iow3.arr[17]; +wire [39:0] Q_72 = ITOP.iow0.arr[18]; +wire [39:0] Q_73 = ITOP.iow1.arr[18]; +wire [39:0] Q_74 = ITOP.iow2.arr[18]; +wire [39:0] Q_75 = ITOP.iow3.arr[18]; +wire [39:0] Q_76 = ITOP.iow0.arr[19]; +wire [39:0] Q_77 = ITOP.iow1.arr[19]; +wire [39:0] Q_78 = ITOP.iow2.arr[19]; +wire [39:0] Q_79 = ITOP.iow3.arr[19]; +wire [39:0] Q_80 = ITOP.iow0.arr[20]; +wire [39:0] Q_81 = ITOP.iow1.arr[20]; +wire [39:0] Q_82 = ITOP.iow2.arr[20]; +wire [39:0] Q_83 = ITOP.iow3.arr[20]; +wire [39:0] Q_84 = ITOP.iow0.arr[21]; +wire [39:0] Q_85 = ITOP.iow1.arr[21]; +wire [39:0] Q_86 = ITOP.iow2.arr[21]; +wire [39:0] Q_87 = ITOP.iow3.arr[21]; +wire [39:0] Q_88 = ITOP.iow0.arr[22]; +wire [39:0] Q_89 = ITOP.iow1.arr[22]; +wire [39:0] Q_90 = ITOP.iow2.arr[22]; +wire [39:0] Q_91 = ITOP.iow3.arr[22]; +wire [39:0] Q_92 = ITOP.iow0.arr[23]; +wire [39:0] Q_93 = ITOP.iow1.arr[23]; +wire [39:0] Q_94 = ITOP.iow2.arr[23]; +wire [39:0] Q_95 = ITOP.iow3.arr[23]; +wire [39:0] Q_96 = ITOP.iow0.arr[24]; +wire [39:0] Q_97 = ITOP.iow1.arr[24]; +wire [39:0] Q_98 = ITOP.iow2.arr[24]; +wire [39:0] Q_99 = ITOP.iow3.arr[24]; +wire [39:0] Q_100 = ITOP.iow0.arr[25]; +wire [39:0] Q_101 = ITOP.iow1.arr[25]; +wire [39:0] Q_102 = ITOP.iow2.arr[25]; +wire [39:0] Q_103 = ITOP.iow3.arr[25]; +wire [39:0] Q_104 = ITOP.iow0.arr[26]; +wire [39:0] Q_105 = ITOP.iow1.arr[26]; +wire [39:0] Q_106 = ITOP.iow2.arr[26]; +wire [39:0] Q_107 = ITOP.iow3.arr[26]; +wire [39:0] Q_108 = ITOP.iow0.arr[27]; +wire [39:0] Q_109 = ITOP.iow1.arr[27]; +wire [39:0] Q_110 = ITOP.iow2.arr[27]; +wire [39:0] Q_111 = ITOP.iow3.arr[27]; +wire [39:0] Q_112 = ITOP.iow0.arr[28]; +wire [39:0] Q_113 = ITOP.iow1.arr[28]; +wire [39:0] Q_114 = ITOP.iow2.arr[28]; +wire [39:0] Q_115 = ITOP.iow3.arr[28]; +wire [39:0] Q_116 = ITOP.iow0.arr[29]; +wire [39:0] Q_117 = ITOP.iow1.arr[29]; +wire [39:0] Q_118 = ITOP.iow2.arr[29]; +wire [39:0] Q_119 = ITOP.iow3.arr[29]; +wire [39:0] Q_120 = ITOP.iow0.arr[30]; +wire [39:0] Q_121 = ITOP.iow1.arr[30]; +wire [39:0] Q_122 = ITOP.iow2.arr[30]; +wire [39:0] Q_123 = ITOP.iow3.arr[30]; +wire [39:0] Q_124 = ITOP.iow0.arr[31]; +wire [39:0] Q_125 = ITOP.iow1.arr[31]; +wire [39:0] Q_126 = ITOP.iow2.arr[31]; +wire [39:0] Q_127 = ITOP.iow3.arr[31]; +wire [39:0] Q_128 = ITOP.iow0.arr[32]; +wire [39:0] Q_129 = ITOP.iow1.arr[32]; +wire [39:0] Q_130 = ITOP.iow2.arr[32]; +wire [39:0] Q_131 = ITOP.iow3.arr[32]; +wire [39:0] Q_132 = ITOP.iow0.arr[33]; +wire [39:0] Q_133 = ITOP.iow1.arr[33]; +wire [39:0] Q_134 = ITOP.iow2.arr[33]; +wire [39:0] Q_135 = ITOP.iow3.arr[33]; +wire [39:0] Q_136 = ITOP.iow0.arr[34]; +wire [39:0] Q_137 = ITOP.iow1.arr[34]; +wire [39:0] Q_138 = ITOP.iow2.arr[34]; +wire [39:0] Q_139 = ITOP.iow3.arr[34]; +wire [39:0] Q_140 = ITOP.iow0.arr[35]; +wire [39:0] Q_141 = ITOP.iow1.arr[35]; +wire [39:0] Q_142 = ITOP.iow2.arr[35]; +wire [39:0] Q_143 = ITOP.iow3.arr[35]; +wire [39:0] Q_144 = ITOP.iow0.arr[36]; +wire [39:0] Q_145 = ITOP.iow1.arr[36]; +wire [39:0] Q_146 = ITOP.iow2.arr[36]; +wire [39:0] Q_147 = ITOP.iow3.arr[36]; +wire [39:0] Q_148 = ITOP.iow0.arr[37]; +wire [39:0] Q_149 = ITOP.iow1.arr[37]; +wire [39:0] Q_150 = ITOP.iow2.arr[37]; +wire [39:0] Q_151 = ITOP.iow3.arr[37]; +wire [39:0] Q_152 = ITOP.iow0.arr[38]; +wire [39:0] Q_153 = ITOP.iow1.arr[38]; +wire [39:0] Q_154 = ITOP.iow2.arr[38]; +wire [39:0] Q_155 = ITOP.iow3.arr[38]; +wire [39:0] Q_156 = ITOP.iow0.arr[39]; +wire [39:0] Q_157 = ITOP.iow1.arr[39]; +wire [39:0] Q_158 = ITOP.iow2.arr[39]; +wire [39:0] Q_159 = ITOP.iow3.arr[39]; +wire [39:0] Q_160 = ITOP.iow0.arr[40]; +wire [39:0] Q_161 = ITOP.iow1.arr[40]; +wire [39:0] Q_162 = ITOP.iow2.arr[40]; +wire [39:0] Q_163 = ITOP.iow3.arr[40]; +wire [39:0] Q_164 = ITOP.iow0.arr[41]; +wire [39:0] Q_165 = ITOP.iow1.arr[41]; +wire [39:0] Q_166 = ITOP.iow2.arr[41]; +wire [39:0] Q_167 = ITOP.iow3.arr[41]; +wire [39:0] Q_168 = ITOP.iow0.arr[42]; +wire [39:0] Q_169 = ITOP.iow1.arr[42]; +wire [39:0] Q_170 = ITOP.iow2.arr[42]; +wire [39:0] Q_171 = ITOP.iow3.arr[42]; +wire [39:0] Q_172 = ITOP.iow0.arr[43]; +wire [39:0] Q_173 = ITOP.iow1.arr[43]; +wire [39:0] Q_174 = ITOP.iow2.arr[43]; +wire [39:0] Q_175 = ITOP.iow3.arr[43]; +wire [39:0] Q_176 = ITOP.iow0.arr[44]; +wire [39:0] Q_177 = ITOP.iow1.arr[44]; +wire [39:0] Q_178 = ITOP.iow2.arr[44]; +wire [39:0] Q_179 = ITOP.iow3.arr[44]; +wire [39:0] Q_180 = ITOP.iow0.arr[45]; +wire [39:0] Q_181 = ITOP.iow1.arr[45]; +wire [39:0] Q_182 = ITOP.iow2.arr[45]; +wire [39:0] Q_183 = ITOP.iow3.arr[45]; +wire [39:0] Q_184 = ITOP.iow0.arr[46]; +wire [39:0] Q_185 = ITOP.iow1.arr[46]; +wire [39:0] Q_186 = ITOP.iow2.arr[46]; +wire [39:0] Q_187 = ITOP.iow3.arr[46]; +wire [39:0] Q_188 = ITOP.iow0.arr[47]; +wire [39:0] Q_189 = ITOP.iow1.arr[47]; +wire [39:0] Q_190 = ITOP.iow2.arr[47]; +wire [39:0] Q_191 = ITOP.iow3.arr[47]; +wire [39:0] Q_192 = ITOP.iow0.arr[48]; +wire [39:0] Q_193 = ITOP.iow1.arr[48]; +wire [39:0] Q_194 = ITOP.iow2.arr[48]; +wire [39:0] Q_195 = ITOP.iow3.arr[48]; +wire [39:0] Q_196 = ITOP.iow0.arr[49]; +wire [39:0] Q_197 = ITOP.iow1.arr[49]; +wire [39:0] Q_198 = ITOP.iow2.arr[49]; +wire [39:0] Q_199 = ITOP.iow3.arr[49]; +wire [39:0] Q_200 = ITOP.iow0.arr[50]; +wire [39:0] Q_201 = ITOP.iow1.arr[50]; +wire [39:0] Q_202 = ITOP.iow2.arr[50]; +wire [39:0] Q_203 = ITOP.iow3.arr[50]; +wire [39:0] Q_204 = ITOP.iow0.arr[51]; +wire [39:0] Q_205 = ITOP.iow1.arr[51]; +wire [39:0] Q_206 = ITOP.iow2.arr[51]; +wire [39:0] Q_207 = ITOP.iow3.arr[51]; +wire [39:0] Q_208 = ITOP.iow0.arr[52]; +wire [39:0] Q_209 = ITOP.iow1.arr[52]; +wire [39:0] Q_210 = ITOP.iow2.arr[52]; +wire [39:0] Q_211 = ITOP.iow3.arr[52]; +wire [39:0] Q_212 = ITOP.iow0.arr[53]; +wire [39:0] Q_213 = ITOP.iow1.arr[53]; +wire [39:0] Q_214 = ITOP.iow2.arr[53]; +wire [39:0] Q_215 = ITOP.iow3.arr[53]; +wire [39:0] Q_216 = ITOP.iow0.arr[54]; +wire [39:0] Q_217 = ITOP.iow1.arr[54]; +wire [39:0] Q_218 = ITOP.iow2.arr[54]; +wire [39:0] Q_219 = ITOP.iow3.arr[54]; +wire [39:0] Q_220 = ITOP.iow0.arr[55]; +wire [39:0] Q_221 = ITOP.iow1.arr[55]; +wire [39:0] Q_222 = ITOP.iow2.arr[55]; +wire [39:0] Q_223 = ITOP.iow3.arr[55]; +wire [39:0] Q_224 = ITOP.iow0.arr[56]; +wire [39:0] Q_225 = ITOP.iow1.arr[56]; +wire [39:0] Q_226 = ITOP.iow2.arr[56]; +wire [39:0] Q_227 = ITOP.iow3.arr[56]; +wire [39:0] Q_228 = ITOP.iow0.arr[57]; +wire [39:0] Q_229 = ITOP.iow1.arr[57]; +wire [39:0] Q_230 = ITOP.iow2.arr[57]; +wire [39:0] Q_231 = ITOP.iow3.arr[57]; +wire [39:0] Q_232 = ITOP.iow0.arr[58]; +wire [39:0] Q_233 = ITOP.iow1.arr[58]; +wire [39:0] Q_234 = ITOP.iow2.arr[58]; +wire [39:0] Q_235 = ITOP.iow3.arr[58]; +wire [39:0] Q_236 = ITOP.iow0.arr[59]; +wire [39:0] Q_237 = ITOP.iow1.arr[59]; +wire [39:0] Q_238 = ITOP.iow2.arr[59]; +wire [39:0] Q_239 = ITOP.iow3.arr[59]; +wire [39:0] Q_240 = ITOP.iow0.arr[60]; +wire [39:0] Q_241 = ITOP.iow1.arr[60]; +wire [39:0] Q_242 = ITOP.iow2.arr[60]; +wire [39:0] Q_243 = ITOP.iow3.arr[60]; +wire [39:0] Q_244 = ITOP.iow0.arr[61]; +wire [39:0] Q_245 = ITOP.iow1.arr[61]; +wire [39:0] Q_246 = ITOP.iow2.arr[61]; +wire [39:0] Q_247 = ITOP.iow3.arr[61]; +wire [39:0] Q_248 = ITOP.iow0.arr[62]; +wire [39:0] Q_249 = ITOP.iow1.arr[62]; +wire [39:0] Q_250 = ITOP.iow2.arr[62]; +wire [39:0] Q_251 = ITOP.iow3.arr[62]; +wire [39:0] Q_252 = ITOP.iow0.arr[63]; +wire [39:0] Q_253 = ITOP.iow1.arr[63]; +wire [39:0] Q_254 = ITOP.iow2.arr[63]; +wire [39:0] Q_255 = ITOP.iow3.arr[63]; +wire [39:0] Q_256 = ITOP.iow0.arr[64]; +wire [39:0] Q_257 = ITOP.iow1.arr[64]; +wire [39:0] Q_258 = ITOP.iow2.arr[64]; +wire [39:0] Q_259 = ITOP.iow3.arr[64]; +wire [39:0] Q_260 = ITOP.iow0.arr[65]; +wire [39:0] Q_261 = ITOP.iow1.arr[65]; +wire [39:0] Q_262 = ITOP.iow2.arr[65]; +wire [39:0] Q_263 = ITOP.iow3.arr[65]; +wire [39:0] Q_264 = ITOP.iow0.arr[66]; +wire [39:0] Q_265 = ITOP.iow1.arr[66]; +wire [39:0] Q_266 = ITOP.iow2.arr[66]; +wire [39:0] Q_267 = ITOP.iow3.arr[66]; +wire [39:0] Q_268 = ITOP.iow0.arr[67]; +wire [39:0] Q_269 = ITOP.iow1.arr[67]; +wire [39:0] Q_270 = ITOP.iow2.arr[67]; +wire [39:0] Q_271 = ITOP.iow3.arr[67]; +wire [39:0] Q_272 = ITOP.iow0.arr[68]; +wire [39:0] Q_273 = ITOP.iow1.arr[68]; +wire [39:0] Q_274 = ITOP.iow2.arr[68]; +wire [39:0] Q_275 = ITOP.iow3.arr[68]; +wire [39:0] Q_276 = ITOP.iow0.arr[69]; +wire [39:0] Q_277 = ITOP.iow1.arr[69]; +wire [39:0] Q_278 = ITOP.iow2.arr[69]; +wire [39:0] Q_279 = ITOP.iow3.arr[69]; +wire [39:0] Q_280 = ITOP.iow0.arr[70]; +wire [39:0] Q_281 = ITOP.iow1.arr[70]; +wire [39:0] Q_282 = ITOP.iow2.arr[70]; +wire [39:0] Q_283 = ITOP.iow3.arr[70]; +wire [39:0] Q_284 = ITOP.iow0.arr[71]; +wire [39:0] Q_285 = ITOP.iow1.arr[71]; +wire [39:0] Q_286 = ITOP.iow2.arr[71]; +wire [39:0] Q_287 = ITOP.iow3.arr[71]; +wire [39:0] Q_288 = ITOP.iow0.arr[72]; +wire [39:0] Q_289 = ITOP.iow1.arr[72]; +wire [39:0] Q_290 = ITOP.iow2.arr[72]; +wire [39:0] Q_291 = ITOP.iow3.arr[72]; +wire [39:0] Q_292 = ITOP.iow0.arr[73]; +wire [39:0] Q_293 = ITOP.iow1.arr[73]; +wire [39:0] Q_294 = ITOP.iow2.arr[73]; +wire [39:0] Q_295 = ITOP.iow3.arr[73]; +wire [39:0] Q_296 = ITOP.iow0.arr[74]; +wire [39:0] Q_297 = ITOP.iow1.arr[74]; +wire [39:0] Q_298 = ITOP.iow2.arr[74]; +wire [39:0] Q_299 = ITOP.iow3.arr[74]; +wire [39:0] Q_300 = ITOP.iow0.arr[75]; +wire [39:0] Q_301 = ITOP.iow1.arr[75]; +wire [39:0] Q_302 = ITOP.iow2.arr[75]; +wire [39:0] Q_303 = ITOP.iow3.arr[75]; +wire [39:0] Q_304 = ITOP.iow0.arr[76]; +wire [39:0] Q_305 = ITOP.iow1.arr[76]; +wire [39:0] Q_306 = ITOP.iow2.arr[76]; +wire [39:0] Q_307 = ITOP.iow3.arr[76]; +wire [39:0] Q_308 = ITOP.iow0.arr[77]; +wire [39:0] Q_309 = ITOP.iow1.arr[77]; +wire [39:0] Q_310 = ITOP.iow2.arr[77]; +wire [39:0] Q_311 = ITOP.iow3.arr[77]; +wire [39:0] Q_312 = ITOP.iow0.arr[78]; +wire [39:0] Q_313 = ITOP.iow1.arr[78]; +wire [39:0] Q_314 = ITOP.iow2.arr[78]; +wire [39:0] Q_315 = ITOP.iow3.arr[78]; +wire [39:0] Q_316 = ITOP.iow0.arr[79]; +wire [39:0] Q_317 = ITOP.iow1.arr[79]; +wire [39:0] Q_318 = ITOP.iow2.arr[79]; +wire [39:0] Q_319 = ITOP.iow3.arr[79]; +wire [39:0] Q_320 = ITOP.iow0.arr[80]; +wire [39:0] Q_321 = ITOP.iow1.arr[80]; +wire [39:0] Q_322 = ITOP.iow2.arr[80]; +wire [39:0] Q_323 = ITOP.iow3.arr[80]; +wire [39:0] Q_324 = ITOP.iow0.arr[81]; +wire [39:0] Q_325 = ITOP.iow1.arr[81]; +wire [39:0] Q_326 = ITOP.iow2.arr[81]; +wire [39:0] Q_327 = ITOP.iow3.arr[81]; +wire [39:0] Q_328 = ITOP.iow0.arr[82]; +wire [39:0] Q_329 = ITOP.iow1.arr[82]; +wire [39:0] Q_330 = ITOP.iow2.arr[82]; +wire [39:0] Q_331 = ITOP.iow3.arr[82]; +wire [39:0] Q_332 = ITOP.iow0.arr[83]; +wire [39:0] Q_333 = ITOP.iow1.arr[83]; +wire [39:0] Q_334 = ITOP.iow2.arr[83]; +wire [39:0] Q_335 = ITOP.iow3.arr[83]; +wire [39:0] Q_336 = ITOP.iow0.arr[84]; +wire [39:0] Q_337 = ITOP.iow1.arr[84]; +wire [39:0] Q_338 = ITOP.iow2.arr[84]; +wire [39:0] Q_339 = ITOP.iow3.arr[84]; +wire [39:0] Q_340 = ITOP.iow0.arr[85]; +wire [39:0] Q_341 = ITOP.iow1.arr[85]; +wire [39:0] Q_342 = ITOP.iow2.arr[85]; +wire [39:0] Q_343 = ITOP.iow3.arr[85]; +wire [39:0] Q_344 = ITOP.iow0.arr[86]; +wire [39:0] Q_345 = ITOP.iow1.arr[86]; +wire [39:0] Q_346 = ITOP.iow2.arr[86]; +wire [39:0] Q_347 = ITOP.iow3.arr[86]; +wire [39:0] Q_348 = ITOP.iow0.arr[87]; +wire [39:0] Q_349 = ITOP.iow1.arr[87]; +wire [39:0] Q_350 = ITOP.iow2.arr[87]; +wire [39:0] Q_351 = ITOP.iow3.arr[87]; +wire [39:0] Q_352 = ITOP.iow0.arr[88]; +wire [39:0] Q_353 = ITOP.iow1.arr[88]; +wire [39:0] Q_354 = ITOP.iow2.arr[88]; +wire [39:0] Q_355 = ITOP.iow3.arr[88]; +wire [39:0] Q_356 = ITOP.iow0.arr[89]; +wire [39:0] Q_357 = ITOP.iow1.arr[89]; +wire [39:0] Q_358 = ITOP.iow2.arr[89]; +wire [39:0] Q_359 = ITOP.iow3.arr[89]; +wire [39:0] Q_360 = ITOP.iow0.arr[90]; +wire [39:0] Q_361 = ITOP.iow1.arr[90]; +wire [39:0] Q_362 = ITOP.iow2.arr[90]; +wire [39:0] Q_363 = ITOP.iow3.arr[90]; +wire [39:0] Q_364 = ITOP.iow0.arr[91]; +wire [39:0] Q_365 = ITOP.iow1.arr[91]; +wire [39:0] Q_366 = ITOP.iow2.arr[91]; +wire [39:0] Q_367 = ITOP.iow3.arr[91]; +wire [39:0] Q_368 = ITOP.iow0.arr[92]; +wire [39:0] Q_369 = ITOP.iow1.arr[92]; +wire [39:0] Q_370 = ITOP.iow2.arr[92]; +wire [39:0] Q_371 = ITOP.iow3.arr[92]; +wire [39:0] Q_372 = ITOP.iow0.arr[93]; +wire [39:0] Q_373 = ITOP.iow1.arr[93]; +wire [39:0] Q_374 = ITOP.iow2.arr[93]; +wire [39:0] Q_375 = ITOP.iow3.arr[93]; +wire [39:0] Q_376 = ITOP.iow0.arr[94]; +wire [39:0] Q_377 = ITOP.iow1.arr[94]; +wire [39:0] Q_378 = ITOP.iow2.arr[94]; +wire [39:0] Q_379 = ITOP.iow3.arr[94]; +wire [39:0] Q_380 = ITOP.iow0.arr[95]; +wire [39:0] Q_381 = ITOP.iow1.arr[95]; +wire [39:0] Q_382 = ITOP.iow2.arr[95]; +wire [39:0] Q_383 = ITOP.iow3.arr[95]; +wire [39:0] Q_384 = ITOP.iow0.arr[96]; +wire [39:0] Q_385 = ITOP.iow1.arr[96]; +wire [39:0] Q_386 = ITOP.iow2.arr[96]; +wire [39:0] Q_387 = ITOP.iow3.arr[96]; +wire [39:0] Q_388 = ITOP.iow0.arr[97]; +wire [39:0] Q_389 = ITOP.iow1.arr[97]; +wire [39:0] Q_390 = ITOP.iow2.arr[97]; +wire [39:0] Q_391 = ITOP.iow3.arr[97]; +wire [39:0] Q_392 = ITOP.iow0.arr[98]; +wire [39:0] Q_393 = ITOP.iow1.arr[98]; +wire [39:0] Q_394 = ITOP.iow2.arr[98]; +wire [39:0] Q_395 = ITOP.iow3.arr[98]; +wire [39:0] Q_396 = ITOP.iow0.arr[99]; +wire [39:0] Q_397 = ITOP.iow1.arr[99]; +wire [39:0] Q_398 = ITOP.iow2.arr[99]; +wire [39:0] Q_399 = ITOP.iow3.arr[99]; +wire [39:0] Q_400 = ITOP.iow0.arr[100]; +wire [39:0] Q_401 = ITOP.iow1.arr[100]; +wire [39:0] Q_402 = ITOP.iow2.arr[100]; +wire [39:0] Q_403 = ITOP.iow3.arr[100]; +wire [39:0] Q_404 = ITOP.iow0.arr[101]; +wire [39:0] Q_405 = ITOP.iow1.arr[101]; +wire [39:0] Q_406 = ITOP.iow2.arr[101]; +wire [39:0] Q_407 = ITOP.iow3.arr[101]; +wire [39:0] Q_408 = ITOP.iow0.arr[102]; +wire [39:0] Q_409 = ITOP.iow1.arr[102]; +wire [39:0] Q_410 = ITOP.iow2.arr[102]; +wire [39:0] Q_411 = ITOP.iow3.arr[102]; +wire [39:0] Q_412 = ITOP.iow0.arr[103]; +wire [39:0] Q_413 = ITOP.iow1.arr[103]; +wire [39:0] Q_414 = ITOP.iow2.arr[103]; +wire [39:0] Q_415 = ITOP.iow3.arr[103]; +wire [39:0] Q_416 = ITOP.iow0.arr[104]; +wire [39:0] Q_417 = ITOP.iow1.arr[104]; +wire [39:0] Q_418 = ITOP.iow2.arr[104]; +wire [39:0] Q_419 = ITOP.iow3.arr[104]; +wire [39:0] Q_420 = ITOP.iow0.arr[105]; +wire [39:0] Q_421 = ITOP.iow1.arr[105]; +wire [39:0] Q_422 = ITOP.iow2.arr[105]; +wire [39:0] Q_423 = ITOP.iow3.arr[105]; +wire [39:0] Q_424 = ITOP.iow0.arr[106]; +wire [39:0] Q_425 = ITOP.iow1.arr[106]; +wire [39:0] Q_426 = ITOP.iow2.arr[106]; +wire [39:0] Q_427 = ITOP.iow3.arr[106]; +wire [39:0] Q_428 = ITOP.iow0.arr[107]; +wire [39:0] Q_429 = ITOP.iow1.arr[107]; +wire [39:0] Q_430 = ITOP.iow2.arr[107]; +wire [39:0] Q_431 = ITOP.iow3.arr[107]; +wire [39:0] Q_432 = ITOP.iow0.arr[108]; +wire [39:0] Q_433 = ITOP.iow1.arr[108]; +wire [39:0] Q_434 = ITOP.iow2.arr[108]; +wire [39:0] Q_435 = ITOP.iow3.arr[108]; +wire [39:0] Q_436 = ITOP.iow0.arr[109]; +wire [39:0] Q_437 = ITOP.iow1.arr[109]; +wire [39:0] Q_438 = ITOP.iow2.arr[109]; +wire [39:0] Q_439 = ITOP.iow3.arr[109]; +wire [39:0] Q_440 = ITOP.iow0.arr[110]; +wire [39:0] Q_441 = ITOP.iow1.arr[110]; +wire [39:0] Q_442 = ITOP.iow2.arr[110]; +wire [39:0] Q_443 = ITOP.iow3.arr[110]; +wire [39:0] Q_444 = ITOP.iow0.arr[111]; +wire [39:0] Q_445 = ITOP.iow1.arr[111]; +wire [39:0] Q_446 = ITOP.iow2.arr[111]; +wire [39:0] Q_447 = ITOP.iow3.arr[111]; +wire [39:0] Q_448 = ITOP.iow0.arr[112]; +wire [39:0] Q_449 = ITOP.iow1.arr[112]; +wire [39:0] Q_450 = ITOP.iow2.arr[112]; +wire [39:0] Q_451 = ITOP.iow3.arr[112]; +wire [39:0] Q_452 = ITOP.iow0.arr[113]; +wire [39:0] Q_453 = ITOP.iow1.arr[113]; +wire [39:0] Q_454 = ITOP.iow2.arr[113]; +wire [39:0] Q_455 = ITOP.iow3.arr[113]; +wire [39:0] Q_456 = ITOP.iow0.arr[114]; +wire [39:0] Q_457 = ITOP.iow1.arr[114]; +wire [39:0] Q_458 = ITOP.iow2.arr[114]; +wire [39:0] Q_459 = ITOP.iow3.arr[114]; +wire [39:0] Q_460 = ITOP.iow0.arr[115]; +wire [39:0] Q_461 = ITOP.iow1.arr[115]; +wire [39:0] Q_462 = ITOP.iow2.arr[115]; +wire [39:0] Q_463 = ITOP.iow3.arr[115]; +wire [39:0] Q_464 = ITOP.iow0.arr[116]; +wire [39:0] Q_465 = ITOP.iow1.arr[116]; +wire [39:0] Q_466 = ITOP.iow2.arr[116]; +wire [39:0] Q_467 = ITOP.iow3.arr[116]; +wire [39:0] Q_468 = ITOP.iow0.arr[117]; +wire [39:0] Q_469 = ITOP.iow1.arr[117]; +wire [39:0] Q_470 = ITOP.iow2.arr[117]; +wire [39:0] Q_471 = ITOP.iow3.arr[117]; +wire [39:0] Q_472 = ITOP.iow0.arr[118]; +wire [39:0] Q_473 = ITOP.iow1.arr[118]; +wire [39:0] Q_474 = ITOP.iow2.arr[118]; +wire [39:0] Q_475 = ITOP.iow3.arr[118]; +wire [39:0] Q_476 = ITOP.iow0.arr[119]; +wire [39:0] Q_477 = ITOP.iow1.arr[119]; +wire [39:0] Q_478 = ITOP.iow2.arr[119]; +wire [39:0] Q_479 = ITOP.iow3.arr[119]; +wire [39:0] Q_480 = ITOP.iow0.arr[120]; +wire [39:0] Q_481 = ITOP.iow1.arr[120]; +wire [39:0] Q_482 = ITOP.iow2.arr[120]; +wire [39:0] Q_483 = ITOP.iow3.arr[120]; +wire [39:0] Q_484 = ITOP.iow0.arr[121]; +wire [39:0] Q_485 = ITOP.iow1.arr[121]; +wire [39:0] Q_486 = ITOP.iow2.arr[121]; +wire [39:0] Q_487 = ITOP.iow3.arr[121]; +wire [39:0] Q_488 = ITOP.iow0.arr[122]; +wire [39:0] Q_489 = ITOP.iow1.arr[122]; +wire [39:0] Q_490 = ITOP.iow2.arr[122]; +wire [39:0] Q_491 = ITOP.iow3.arr[122]; +wire [39:0] Q_492 = ITOP.iow0.arr[123]; +wire [39:0] Q_493 = ITOP.iow1.arr[123]; +wire [39:0] Q_494 = ITOP.iow2.arr[123]; +wire [39:0] Q_495 = ITOP.iow3.arr[123]; +wire [39:0] Q_496 = ITOP.iow0.arr[124]; +wire [39:0] Q_497 = ITOP.iow1.arr[124]; +wire [39:0] Q_498 = ITOP.iow2.arr[124]; +wire [39:0] Q_499 = ITOP.iow3.arr[124]; +wire [39:0] Q_500 = ITOP.iow0.arr[125]; +wire [39:0] Q_501 = ITOP.iow1.arr[125]; +wire [39:0] Q_502 = ITOP.iow2.arr[125]; +wire [39:0] Q_503 = ITOP.iow3.arr[125]; +wire [39:0] Q_504 = ITOP.iow0.arr[126]; +wire [39:0] Q_505 = ITOP.iow1.arr[126]; +wire [39:0] Q_506 = ITOP.iow2.arr[126]; +wire [39:0] Q_507 = ITOP.iow3.arr[126]; +wire [39:0] Q_508 = ITOP.iow0.arr[127]; +wire [39:0] Q_509 = ITOP.iow1.arr[127]; +wire [39:0] Q_510 = ITOP.iow2.arr[127]; +wire [39:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [39:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [39:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [39:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [39:0] WD_FF; + reg [39:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [39:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [39:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [39:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X40_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [39:0] WD; +input [8:0] RA, WA; +output [39:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [39:0] WDQ; + wire [39:0] WDBQ; + wire [39:0] WMNexp; + wire [39:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [39:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {40{1'b0}}; + assign SHFT = {40{1'b1}}; + reg [39:0] WDQ_pr; + wire [39:0] WDBQ_pr; + assign WMNexp = {40{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[39:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [39:0] dout; + wire [39:0] RD; + wire RD_rdnt; + wire [39:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [39:0] RDBYPASS = {40{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [39:0] force_x; +`ifndef SYNTHESIS + assign force_x = {40{1'bx}}; +`else + assign force_x = {40{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [39:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [39:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {40{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {40{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {40{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {40{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {40{RdClk0}} & ~dout0; + assign rmuxd1 = {40{RdClk1}} & ~dout1; + assign rmuxd2 = {40{RdClk2}} & ~dout2; + assign rmuxd3 = {40{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[39:0] <= (rmuxd0[39:0] | rmuxd1[39:0] | rmuxd2[39:0] | rmuxd3[39:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X40_GL_M4_D2_ram # (128, 40, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [39:0] data; + reg [39:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [39:0] mem_read_bank; +input [8:0] addr; +reg [39:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X40_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 40; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 64'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 64'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 64'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 64'bx; + for (i=0; i<=63; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [255:0] data; + reg [63:0] wr[3:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [6:0] addr; + reg [255:0] mon_row; + reg [63:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [6:0] addr; + reg [255:0] mon_row; + reg [63:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow1.arr[0]; +wire [63:0] Q_2 = ITOP.iow2.arr[0]; +wire [63:0] Q_3 = ITOP.iow3.arr[0]; +wire [63:0] Q_4 = ITOP.iow0.arr[1]; +wire [63:0] Q_5 = ITOP.iow1.arr[1]; +wire [63:0] Q_6 = ITOP.iow2.arr[1]; +wire [63:0] Q_7 = ITOP.iow3.arr[1]; +wire [63:0] Q_8 = ITOP.iow0.arr[2]; +wire [63:0] Q_9 = ITOP.iow1.arr[2]; +wire [63:0] Q_10 = ITOP.iow2.arr[2]; +wire [63:0] Q_11 = ITOP.iow3.arr[2]; +wire [63:0] Q_12 = ITOP.iow0.arr[3]; +wire [63:0] Q_13 = ITOP.iow1.arr[3]; +wire [63:0] Q_14 = ITOP.iow2.arr[3]; +wire [63:0] Q_15 = ITOP.iow3.arr[3]; +wire [63:0] Q_16 = ITOP.iow0.arr[4]; +wire [63:0] Q_17 = ITOP.iow1.arr[4]; +wire [63:0] Q_18 = ITOP.iow2.arr[4]; +wire [63:0] Q_19 = ITOP.iow3.arr[4]; +wire [63:0] Q_20 = ITOP.iow0.arr[5]; +wire [63:0] Q_21 = ITOP.iow1.arr[5]; +wire [63:0] Q_22 = ITOP.iow2.arr[5]; +wire [63:0] Q_23 = ITOP.iow3.arr[5]; +wire [63:0] Q_24 = ITOP.iow0.arr[6]; +wire [63:0] Q_25 = ITOP.iow1.arr[6]; +wire [63:0] Q_26 = ITOP.iow2.arr[6]; +wire [63:0] Q_27 = ITOP.iow3.arr[6]; +wire [63:0] Q_28 = ITOP.iow0.arr[7]; +wire [63:0] Q_29 = ITOP.iow1.arr[7]; +wire [63:0] Q_30 = ITOP.iow2.arr[7]; +wire [63:0] Q_31 = ITOP.iow3.arr[7]; +wire [63:0] Q_32 = ITOP.iow0.arr[8]; +wire [63:0] Q_33 = ITOP.iow1.arr[8]; +wire [63:0] Q_34 = ITOP.iow2.arr[8]; +wire [63:0] Q_35 = ITOP.iow3.arr[8]; +wire [63:0] Q_36 = ITOP.iow0.arr[9]; +wire [63:0] Q_37 = ITOP.iow1.arr[9]; +wire [63:0] Q_38 = ITOP.iow2.arr[9]; +wire [63:0] Q_39 = ITOP.iow3.arr[9]; +wire [63:0] Q_40 = ITOP.iow0.arr[10]; +wire [63:0] Q_41 = ITOP.iow1.arr[10]; +wire [63:0] Q_42 = ITOP.iow2.arr[10]; +wire [63:0] Q_43 = ITOP.iow3.arr[10]; +wire [63:0] Q_44 = ITOP.iow0.arr[11]; +wire [63:0] Q_45 = ITOP.iow1.arr[11]; +wire [63:0] Q_46 = ITOP.iow2.arr[11]; +wire [63:0] Q_47 = ITOP.iow3.arr[11]; +wire [63:0] Q_48 = ITOP.iow0.arr[12]; +wire [63:0] Q_49 = ITOP.iow1.arr[12]; +wire [63:0] Q_50 = ITOP.iow2.arr[12]; +wire [63:0] Q_51 = ITOP.iow3.arr[12]; +wire [63:0] Q_52 = ITOP.iow0.arr[13]; +wire [63:0] Q_53 = ITOP.iow1.arr[13]; +wire [63:0] Q_54 = ITOP.iow2.arr[13]; +wire [63:0] Q_55 = ITOP.iow3.arr[13]; +wire [63:0] Q_56 = ITOP.iow0.arr[14]; +wire [63:0] Q_57 = ITOP.iow1.arr[14]; +wire [63:0] Q_58 = ITOP.iow2.arr[14]; +wire [63:0] Q_59 = ITOP.iow3.arr[14]; +wire [63:0] Q_60 = ITOP.iow0.arr[15]; +wire [63:0] Q_61 = ITOP.iow1.arr[15]; +wire [63:0] Q_62 = ITOP.iow2.arr[15]; +wire [63:0] Q_63 = ITOP.iow3.arr[15]; +wire [63:0] Q_64 = ITOP.iow0.arr[16]; +wire [63:0] Q_65 = ITOP.iow1.arr[16]; +wire [63:0] Q_66 = ITOP.iow2.arr[16]; +wire [63:0] Q_67 = ITOP.iow3.arr[16]; +wire [63:0] Q_68 = ITOP.iow0.arr[17]; +wire [63:0] Q_69 = ITOP.iow1.arr[17]; +wire [63:0] Q_70 = ITOP.iow2.arr[17]; +wire [63:0] Q_71 = ITOP.iow3.arr[17]; +wire [63:0] Q_72 = ITOP.iow0.arr[18]; +wire [63:0] Q_73 = ITOP.iow1.arr[18]; +wire [63:0] Q_74 = ITOP.iow2.arr[18]; +wire [63:0] Q_75 = ITOP.iow3.arr[18]; +wire [63:0] Q_76 = ITOP.iow0.arr[19]; +wire [63:0] Q_77 = ITOP.iow1.arr[19]; +wire [63:0] Q_78 = ITOP.iow2.arr[19]; +wire [63:0] Q_79 = ITOP.iow3.arr[19]; +wire [63:0] Q_80 = ITOP.iow0.arr[20]; +wire [63:0] Q_81 = ITOP.iow1.arr[20]; +wire [63:0] Q_82 = ITOP.iow2.arr[20]; +wire [63:0] Q_83 = ITOP.iow3.arr[20]; +wire [63:0] Q_84 = ITOP.iow0.arr[21]; +wire [63:0] Q_85 = ITOP.iow1.arr[21]; +wire [63:0] Q_86 = ITOP.iow2.arr[21]; +wire [63:0] Q_87 = ITOP.iow3.arr[21]; +wire [63:0] Q_88 = ITOP.iow0.arr[22]; +wire [63:0] Q_89 = ITOP.iow1.arr[22]; +wire [63:0] Q_90 = ITOP.iow2.arr[22]; +wire [63:0] Q_91 = ITOP.iow3.arr[22]; +wire [63:0] Q_92 = ITOP.iow0.arr[23]; +wire [63:0] Q_93 = ITOP.iow1.arr[23]; +wire [63:0] Q_94 = ITOP.iow2.arr[23]; +wire [63:0] Q_95 = ITOP.iow3.arr[23]; +wire [63:0] Q_96 = ITOP.iow0.arr[24]; +wire [63:0] Q_97 = ITOP.iow1.arr[24]; +wire [63:0] Q_98 = ITOP.iow2.arr[24]; +wire [63:0] Q_99 = ITOP.iow3.arr[24]; +wire [63:0] Q_100 = ITOP.iow0.arr[25]; +wire [63:0] Q_101 = ITOP.iow1.arr[25]; +wire [63:0] Q_102 = ITOP.iow2.arr[25]; +wire [63:0] Q_103 = ITOP.iow3.arr[25]; +wire [63:0] Q_104 = ITOP.iow0.arr[26]; +wire [63:0] Q_105 = ITOP.iow1.arr[26]; +wire [63:0] Q_106 = ITOP.iow2.arr[26]; +wire [63:0] Q_107 = ITOP.iow3.arr[26]; +wire [63:0] Q_108 = ITOP.iow0.arr[27]; +wire [63:0] Q_109 = ITOP.iow1.arr[27]; +wire [63:0] Q_110 = ITOP.iow2.arr[27]; +wire [63:0] Q_111 = ITOP.iow3.arr[27]; +wire [63:0] Q_112 = ITOP.iow0.arr[28]; +wire [63:0] Q_113 = ITOP.iow1.arr[28]; +wire [63:0] Q_114 = ITOP.iow2.arr[28]; +wire [63:0] Q_115 = ITOP.iow3.arr[28]; +wire [63:0] Q_116 = ITOP.iow0.arr[29]; +wire [63:0] Q_117 = ITOP.iow1.arr[29]; +wire [63:0] Q_118 = ITOP.iow2.arr[29]; +wire [63:0] Q_119 = ITOP.iow3.arr[29]; +wire [63:0] Q_120 = ITOP.iow0.arr[30]; +wire [63:0] Q_121 = ITOP.iow1.arr[30]; +wire [63:0] Q_122 = ITOP.iow2.arr[30]; +wire [63:0] Q_123 = ITOP.iow3.arr[30]; +wire [63:0] Q_124 = ITOP.iow0.arr[31]; +wire [63:0] Q_125 = ITOP.iow1.arr[31]; +wire [63:0] Q_126 = ITOP.iow2.arr[31]; +wire [63:0] Q_127 = ITOP.iow3.arr[31]; +wire [63:0] Q_128 = ITOP.iow0.arr[32]; +wire [63:0] Q_129 = ITOP.iow1.arr[32]; +wire [63:0] Q_130 = ITOP.iow2.arr[32]; +wire [63:0] Q_131 = ITOP.iow3.arr[32]; +wire [63:0] Q_132 = ITOP.iow0.arr[33]; +wire [63:0] Q_133 = ITOP.iow1.arr[33]; +wire [63:0] Q_134 = ITOP.iow2.arr[33]; +wire [63:0] Q_135 = ITOP.iow3.arr[33]; +wire [63:0] Q_136 = ITOP.iow0.arr[34]; +wire [63:0] Q_137 = ITOP.iow1.arr[34]; +wire [63:0] Q_138 = ITOP.iow2.arr[34]; +wire [63:0] Q_139 = ITOP.iow3.arr[34]; +wire [63:0] Q_140 = ITOP.iow0.arr[35]; +wire [63:0] Q_141 = ITOP.iow1.arr[35]; +wire [63:0] Q_142 = ITOP.iow2.arr[35]; +wire [63:0] Q_143 = ITOP.iow3.arr[35]; +wire [63:0] Q_144 = ITOP.iow0.arr[36]; +wire [63:0] Q_145 = ITOP.iow1.arr[36]; +wire [63:0] Q_146 = ITOP.iow2.arr[36]; +wire [63:0] Q_147 = ITOP.iow3.arr[36]; +wire [63:0] Q_148 = ITOP.iow0.arr[37]; +wire [63:0] Q_149 = ITOP.iow1.arr[37]; +wire [63:0] Q_150 = ITOP.iow2.arr[37]; +wire [63:0] Q_151 = ITOP.iow3.arr[37]; +wire [63:0] Q_152 = ITOP.iow0.arr[38]; +wire [63:0] Q_153 = ITOP.iow1.arr[38]; +wire [63:0] Q_154 = ITOP.iow2.arr[38]; +wire [63:0] Q_155 = ITOP.iow3.arr[38]; +wire [63:0] Q_156 = ITOP.iow0.arr[39]; +wire [63:0] Q_157 = ITOP.iow1.arr[39]; +wire [63:0] Q_158 = ITOP.iow2.arr[39]; +wire [63:0] Q_159 = ITOP.iow3.arr[39]; +wire [63:0] Q_160 = ITOP.iow0.arr[40]; +wire [63:0] Q_161 = ITOP.iow1.arr[40]; +wire [63:0] Q_162 = ITOP.iow2.arr[40]; +wire [63:0] Q_163 = ITOP.iow3.arr[40]; +wire [63:0] Q_164 = ITOP.iow0.arr[41]; +wire [63:0] Q_165 = ITOP.iow1.arr[41]; +wire [63:0] Q_166 = ITOP.iow2.arr[41]; +wire [63:0] Q_167 = ITOP.iow3.arr[41]; +wire [63:0] Q_168 = ITOP.iow0.arr[42]; +wire [63:0] Q_169 = ITOP.iow1.arr[42]; +wire [63:0] Q_170 = ITOP.iow2.arr[42]; +wire [63:0] Q_171 = ITOP.iow3.arr[42]; +wire [63:0] Q_172 = ITOP.iow0.arr[43]; +wire [63:0] Q_173 = ITOP.iow1.arr[43]; +wire [63:0] Q_174 = ITOP.iow2.arr[43]; +wire [63:0] Q_175 = ITOP.iow3.arr[43]; +wire [63:0] Q_176 = ITOP.iow0.arr[44]; +wire [63:0] Q_177 = ITOP.iow1.arr[44]; +wire [63:0] Q_178 = ITOP.iow2.arr[44]; +wire [63:0] Q_179 = ITOP.iow3.arr[44]; +wire [63:0] Q_180 = ITOP.iow0.arr[45]; +wire [63:0] Q_181 = ITOP.iow1.arr[45]; +wire [63:0] Q_182 = ITOP.iow2.arr[45]; +wire [63:0] Q_183 = ITOP.iow3.arr[45]; +wire [63:0] Q_184 = ITOP.iow0.arr[46]; +wire [63:0] Q_185 = ITOP.iow1.arr[46]; +wire [63:0] Q_186 = ITOP.iow2.arr[46]; +wire [63:0] Q_187 = ITOP.iow3.arr[46]; +wire [63:0] Q_188 = ITOP.iow0.arr[47]; +wire [63:0] Q_189 = ITOP.iow1.arr[47]; +wire [63:0] Q_190 = ITOP.iow2.arr[47]; +wire [63:0] Q_191 = ITOP.iow3.arr[47]; +wire [63:0] Q_192 = ITOP.iow0.arr[48]; +wire [63:0] Q_193 = ITOP.iow1.arr[48]; +wire [63:0] Q_194 = ITOP.iow2.arr[48]; +wire [63:0] Q_195 = ITOP.iow3.arr[48]; +wire [63:0] Q_196 = ITOP.iow0.arr[49]; +wire [63:0] Q_197 = ITOP.iow1.arr[49]; +wire [63:0] Q_198 = ITOP.iow2.arr[49]; +wire [63:0] Q_199 = ITOP.iow3.arr[49]; +wire [63:0] Q_200 = ITOP.iow0.arr[50]; +wire [63:0] Q_201 = ITOP.iow1.arr[50]; +wire [63:0] Q_202 = ITOP.iow2.arr[50]; +wire [63:0] Q_203 = ITOP.iow3.arr[50]; +wire [63:0] Q_204 = ITOP.iow0.arr[51]; +wire [63:0] Q_205 = ITOP.iow1.arr[51]; +wire [63:0] Q_206 = ITOP.iow2.arr[51]; +wire [63:0] Q_207 = ITOP.iow3.arr[51]; +wire [63:0] Q_208 = ITOP.iow0.arr[52]; +wire [63:0] Q_209 = ITOP.iow1.arr[52]; +wire [63:0] Q_210 = ITOP.iow2.arr[52]; +wire [63:0] Q_211 = ITOP.iow3.arr[52]; +wire [63:0] Q_212 = ITOP.iow0.arr[53]; +wire [63:0] Q_213 = ITOP.iow1.arr[53]; +wire [63:0] Q_214 = ITOP.iow2.arr[53]; +wire [63:0] Q_215 = ITOP.iow3.arr[53]; +wire [63:0] Q_216 = ITOP.iow0.arr[54]; +wire [63:0] Q_217 = ITOP.iow1.arr[54]; +wire [63:0] Q_218 = ITOP.iow2.arr[54]; +wire [63:0] Q_219 = ITOP.iow3.arr[54]; +wire [63:0] Q_220 = ITOP.iow0.arr[55]; +wire [63:0] Q_221 = ITOP.iow1.arr[55]; +wire [63:0] Q_222 = ITOP.iow2.arr[55]; +wire [63:0] Q_223 = ITOP.iow3.arr[55]; +wire [63:0] Q_224 = ITOP.iow0.arr[56]; +wire [63:0] Q_225 = ITOP.iow1.arr[56]; +wire [63:0] Q_226 = ITOP.iow2.arr[56]; +wire [63:0] Q_227 = ITOP.iow3.arr[56]; +wire [63:0] Q_228 = ITOP.iow0.arr[57]; +wire [63:0] Q_229 = ITOP.iow1.arr[57]; +wire [63:0] Q_230 = ITOP.iow2.arr[57]; +wire [63:0] Q_231 = ITOP.iow3.arr[57]; +wire [63:0] Q_232 = ITOP.iow0.arr[58]; +wire [63:0] Q_233 = ITOP.iow1.arr[58]; +wire [63:0] Q_234 = ITOP.iow2.arr[58]; +wire [63:0] Q_235 = ITOP.iow3.arr[58]; +wire [63:0] Q_236 = ITOP.iow0.arr[59]; +wire [63:0] Q_237 = ITOP.iow1.arr[59]; +wire [63:0] Q_238 = ITOP.iow2.arr[59]; +wire [63:0] Q_239 = ITOP.iow3.arr[59]; +wire [63:0] Q_240 = ITOP.iow0.arr[60]; +wire [63:0] Q_241 = ITOP.iow1.arr[60]; +wire [63:0] Q_242 = ITOP.iow2.arr[60]; +wire [63:0] Q_243 = ITOP.iow3.arr[60]; +wire [63:0] Q_244 = ITOP.iow0.arr[61]; +wire [63:0] Q_245 = ITOP.iow1.arr[61]; +wire [63:0] Q_246 = ITOP.iow2.arr[61]; +wire [63:0] Q_247 = ITOP.iow3.arr[61]; +wire [63:0] Q_248 = ITOP.iow0.arr[62]; +wire [63:0] Q_249 = ITOP.iow1.arr[62]; +wire [63:0] Q_250 = ITOP.iow2.arr[62]; +wire [63:0] Q_251 = ITOP.iow3.arr[62]; +wire [63:0] Q_252 = ITOP.iow0.arr[63]; +wire [63:0] Q_253 = ITOP.iow1.arr[63]; +wire [63:0] Q_254 = ITOP.iow2.arr[63]; +wire [63:0] Q_255 = ITOP.iow3.arr[63]; +wire [63:0] Q_256 = ITOP.iow0.arr[64]; +wire [63:0] Q_257 = ITOP.iow1.arr[64]; +wire [63:0] Q_258 = ITOP.iow2.arr[64]; +wire [63:0] Q_259 = ITOP.iow3.arr[64]; +wire [63:0] Q_260 = ITOP.iow0.arr[65]; +wire [63:0] Q_261 = ITOP.iow1.arr[65]; +wire [63:0] Q_262 = ITOP.iow2.arr[65]; +wire [63:0] Q_263 = ITOP.iow3.arr[65]; +wire [63:0] Q_264 = ITOP.iow0.arr[66]; +wire [63:0] Q_265 = ITOP.iow1.arr[66]; +wire [63:0] Q_266 = ITOP.iow2.arr[66]; +wire [63:0] Q_267 = ITOP.iow3.arr[66]; +wire [63:0] Q_268 = ITOP.iow0.arr[67]; +wire [63:0] Q_269 = ITOP.iow1.arr[67]; +wire [63:0] Q_270 = ITOP.iow2.arr[67]; +wire [63:0] Q_271 = ITOP.iow3.arr[67]; +wire [63:0] Q_272 = ITOP.iow0.arr[68]; +wire [63:0] Q_273 = ITOP.iow1.arr[68]; +wire [63:0] Q_274 = ITOP.iow2.arr[68]; +wire [63:0] Q_275 = ITOP.iow3.arr[68]; +wire [63:0] Q_276 = ITOP.iow0.arr[69]; +wire [63:0] Q_277 = ITOP.iow1.arr[69]; +wire [63:0] Q_278 = ITOP.iow2.arr[69]; +wire [63:0] Q_279 = ITOP.iow3.arr[69]; +wire [63:0] Q_280 = ITOP.iow0.arr[70]; +wire [63:0] Q_281 = ITOP.iow1.arr[70]; +wire [63:0] Q_282 = ITOP.iow2.arr[70]; +wire [63:0] Q_283 = ITOP.iow3.arr[70]; +wire [63:0] Q_284 = ITOP.iow0.arr[71]; +wire [63:0] Q_285 = ITOP.iow1.arr[71]; +wire [63:0] Q_286 = ITOP.iow2.arr[71]; +wire [63:0] Q_287 = ITOP.iow3.arr[71]; +wire [63:0] Q_288 = ITOP.iow0.arr[72]; +wire [63:0] Q_289 = ITOP.iow1.arr[72]; +wire [63:0] Q_290 = ITOP.iow2.arr[72]; +wire [63:0] Q_291 = ITOP.iow3.arr[72]; +wire [63:0] Q_292 = ITOP.iow0.arr[73]; +wire [63:0] Q_293 = ITOP.iow1.arr[73]; +wire [63:0] Q_294 = ITOP.iow2.arr[73]; +wire [63:0] Q_295 = ITOP.iow3.arr[73]; +wire [63:0] Q_296 = ITOP.iow0.arr[74]; +wire [63:0] Q_297 = ITOP.iow1.arr[74]; +wire [63:0] Q_298 = ITOP.iow2.arr[74]; +wire [63:0] Q_299 = ITOP.iow3.arr[74]; +wire [63:0] Q_300 = ITOP.iow0.arr[75]; +wire [63:0] Q_301 = ITOP.iow1.arr[75]; +wire [63:0] Q_302 = ITOP.iow2.arr[75]; +wire [63:0] Q_303 = ITOP.iow3.arr[75]; +wire [63:0] Q_304 = ITOP.iow0.arr[76]; +wire [63:0] Q_305 = ITOP.iow1.arr[76]; +wire [63:0] Q_306 = ITOP.iow2.arr[76]; +wire [63:0] Q_307 = ITOP.iow3.arr[76]; +wire [63:0] Q_308 = ITOP.iow0.arr[77]; +wire [63:0] Q_309 = ITOP.iow1.arr[77]; +wire [63:0] Q_310 = ITOP.iow2.arr[77]; +wire [63:0] Q_311 = ITOP.iow3.arr[77]; +wire [63:0] Q_312 = ITOP.iow0.arr[78]; +wire [63:0] Q_313 = ITOP.iow1.arr[78]; +wire [63:0] Q_314 = ITOP.iow2.arr[78]; +wire [63:0] Q_315 = ITOP.iow3.arr[78]; +wire [63:0] Q_316 = ITOP.iow0.arr[79]; +wire [63:0] Q_317 = ITOP.iow1.arr[79]; +wire [63:0] Q_318 = ITOP.iow2.arr[79]; +wire [63:0] Q_319 = ITOP.iow3.arr[79]; +wire [63:0] Q_320 = ITOP.iow0.arr[80]; +wire [63:0] Q_321 = ITOP.iow1.arr[80]; +wire [63:0] Q_322 = ITOP.iow2.arr[80]; +wire [63:0] Q_323 = ITOP.iow3.arr[80]; +wire [63:0] Q_324 = ITOP.iow0.arr[81]; +wire [63:0] Q_325 = ITOP.iow1.arr[81]; +wire [63:0] Q_326 = ITOP.iow2.arr[81]; +wire [63:0] Q_327 = ITOP.iow3.arr[81]; +wire [63:0] Q_328 = ITOP.iow0.arr[82]; +wire [63:0] Q_329 = ITOP.iow1.arr[82]; +wire [63:0] Q_330 = ITOP.iow2.arr[82]; +wire [63:0] Q_331 = ITOP.iow3.arr[82]; +wire [63:0] Q_332 = ITOP.iow0.arr[83]; +wire [63:0] Q_333 = ITOP.iow1.arr[83]; +wire [63:0] Q_334 = ITOP.iow2.arr[83]; +wire [63:0] Q_335 = ITOP.iow3.arr[83]; +wire [63:0] Q_336 = ITOP.iow0.arr[84]; +wire [63:0] Q_337 = ITOP.iow1.arr[84]; +wire [63:0] Q_338 = ITOP.iow2.arr[84]; +wire [63:0] Q_339 = ITOP.iow3.arr[84]; +wire [63:0] Q_340 = ITOP.iow0.arr[85]; +wire [63:0] Q_341 = ITOP.iow1.arr[85]; +wire [63:0] Q_342 = ITOP.iow2.arr[85]; +wire [63:0] Q_343 = ITOP.iow3.arr[85]; +wire [63:0] Q_344 = ITOP.iow0.arr[86]; +wire [63:0] Q_345 = ITOP.iow1.arr[86]; +wire [63:0] Q_346 = ITOP.iow2.arr[86]; +wire [63:0] Q_347 = ITOP.iow3.arr[86]; +wire [63:0] Q_348 = ITOP.iow0.arr[87]; +wire [63:0] Q_349 = ITOP.iow1.arr[87]; +wire [63:0] Q_350 = ITOP.iow2.arr[87]; +wire [63:0] Q_351 = ITOP.iow3.arr[87]; +wire [63:0] Q_352 = ITOP.iow0.arr[88]; +wire [63:0] Q_353 = ITOP.iow1.arr[88]; +wire [63:0] Q_354 = ITOP.iow2.arr[88]; +wire [63:0] Q_355 = ITOP.iow3.arr[88]; +wire [63:0] Q_356 = ITOP.iow0.arr[89]; +wire [63:0] Q_357 = ITOP.iow1.arr[89]; +wire [63:0] Q_358 = ITOP.iow2.arr[89]; +wire [63:0] Q_359 = ITOP.iow3.arr[89]; +wire [63:0] Q_360 = ITOP.iow0.arr[90]; +wire [63:0] Q_361 = ITOP.iow1.arr[90]; +wire [63:0] Q_362 = ITOP.iow2.arr[90]; +wire [63:0] Q_363 = ITOP.iow3.arr[90]; +wire [63:0] Q_364 = ITOP.iow0.arr[91]; +wire [63:0] Q_365 = ITOP.iow1.arr[91]; +wire [63:0] Q_366 = ITOP.iow2.arr[91]; +wire [63:0] Q_367 = ITOP.iow3.arr[91]; +wire [63:0] Q_368 = ITOP.iow0.arr[92]; +wire [63:0] Q_369 = ITOP.iow1.arr[92]; +wire [63:0] Q_370 = ITOP.iow2.arr[92]; +wire [63:0] Q_371 = ITOP.iow3.arr[92]; +wire [63:0] Q_372 = ITOP.iow0.arr[93]; +wire [63:0] Q_373 = ITOP.iow1.arr[93]; +wire [63:0] Q_374 = ITOP.iow2.arr[93]; +wire [63:0] Q_375 = ITOP.iow3.arr[93]; +wire [63:0] Q_376 = ITOP.iow0.arr[94]; +wire [63:0] Q_377 = ITOP.iow1.arr[94]; +wire [63:0] Q_378 = ITOP.iow2.arr[94]; +wire [63:0] Q_379 = ITOP.iow3.arr[94]; +wire [63:0] Q_380 = ITOP.iow0.arr[95]; +wire [63:0] Q_381 = ITOP.iow1.arr[95]; +wire [63:0] Q_382 = ITOP.iow2.arr[95]; +wire [63:0] Q_383 = ITOP.iow3.arr[95]; +wire [63:0] Q_384 = ITOP.iow0.arr[96]; +wire [63:0] Q_385 = ITOP.iow1.arr[96]; +wire [63:0] Q_386 = ITOP.iow2.arr[96]; +wire [63:0] Q_387 = ITOP.iow3.arr[96]; +wire [63:0] Q_388 = ITOP.iow0.arr[97]; +wire [63:0] Q_389 = ITOP.iow1.arr[97]; +wire [63:0] Q_390 = ITOP.iow2.arr[97]; +wire [63:0] Q_391 = ITOP.iow3.arr[97]; +wire [63:0] Q_392 = ITOP.iow0.arr[98]; +wire [63:0] Q_393 = ITOP.iow1.arr[98]; +wire [63:0] Q_394 = ITOP.iow2.arr[98]; +wire [63:0] Q_395 = ITOP.iow3.arr[98]; +wire [63:0] Q_396 = ITOP.iow0.arr[99]; +wire [63:0] Q_397 = ITOP.iow1.arr[99]; +wire [63:0] Q_398 = ITOP.iow2.arr[99]; +wire [63:0] Q_399 = ITOP.iow3.arr[99]; +wire [63:0] Q_400 = ITOP.iow0.arr[100]; +wire [63:0] Q_401 = ITOP.iow1.arr[100]; +wire [63:0] Q_402 = ITOP.iow2.arr[100]; +wire [63:0] Q_403 = ITOP.iow3.arr[100]; +wire [63:0] Q_404 = ITOP.iow0.arr[101]; +wire [63:0] Q_405 = ITOP.iow1.arr[101]; +wire [63:0] Q_406 = ITOP.iow2.arr[101]; +wire [63:0] Q_407 = ITOP.iow3.arr[101]; +wire [63:0] Q_408 = ITOP.iow0.arr[102]; +wire [63:0] Q_409 = ITOP.iow1.arr[102]; +wire [63:0] Q_410 = ITOP.iow2.arr[102]; +wire [63:0] Q_411 = ITOP.iow3.arr[102]; +wire [63:0] Q_412 = ITOP.iow0.arr[103]; +wire [63:0] Q_413 = ITOP.iow1.arr[103]; +wire [63:0] Q_414 = ITOP.iow2.arr[103]; +wire [63:0] Q_415 = ITOP.iow3.arr[103]; +wire [63:0] Q_416 = ITOP.iow0.arr[104]; +wire [63:0] Q_417 = ITOP.iow1.arr[104]; +wire [63:0] Q_418 = ITOP.iow2.arr[104]; +wire [63:0] Q_419 = ITOP.iow3.arr[104]; +wire [63:0] Q_420 = ITOP.iow0.arr[105]; +wire [63:0] Q_421 = ITOP.iow1.arr[105]; +wire [63:0] Q_422 = ITOP.iow2.arr[105]; +wire [63:0] Q_423 = ITOP.iow3.arr[105]; +wire [63:0] Q_424 = ITOP.iow0.arr[106]; +wire [63:0] Q_425 = ITOP.iow1.arr[106]; +wire [63:0] Q_426 = ITOP.iow2.arr[106]; +wire [63:0] Q_427 = ITOP.iow3.arr[106]; +wire [63:0] Q_428 = ITOP.iow0.arr[107]; +wire [63:0] Q_429 = ITOP.iow1.arr[107]; +wire [63:0] Q_430 = ITOP.iow2.arr[107]; +wire [63:0] Q_431 = ITOP.iow3.arr[107]; +wire [63:0] Q_432 = ITOP.iow0.arr[108]; +wire [63:0] Q_433 = ITOP.iow1.arr[108]; +wire [63:0] Q_434 = ITOP.iow2.arr[108]; +wire [63:0] Q_435 = ITOP.iow3.arr[108]; +wire [63:0] Q_436 = ITOP.iow0.arr[109]; +wire [63:0] Q_437 = ITOP.iow1.arr[109]; +wire [63:0] Q_438 = ITOP.iow2.arr[109]; +wire [63:0] Q_439 = ITOP.iow3.arr[109]; +wire [63:0] Q_440 = ITOP.iow0.arr[110]; +wire [63:0] Q_441 = ITOP.iow1.arr[110]; +wire [63:0] Q_442 = ITOP.iow2.arr[110]; +wire [63:0] Q_443 = ITOP.iow3.arr[110]; +wire [63:0] Q_444 = ITOP.iow0.arr[111]; +wire [63:0] Q_445 = ITOP.iow1.arr[111]; +wire [63:0] Q_446 = ITOP.iow2.arr[111]; +wire [63:0] Q_447 = ITOP.iow3.arr[111]; +wire [63:0] Q_448 = ITOP.iow0.arr[112]; +wire [63:0] Q_449 = ITOP.iow1.arr[112]; +wire [63:0] Q_450 = ITOP.iow2.arr[112]; +wire [63:0] Q_451 = ITOP.iow3.arr[112]; +wire [63:0] Q_452 = ITOP.iow0.arr[113]; +wire [63:0] Q_453 = ITOP.iow1.arr[113]; +wire [63:0] Q_454 = ITOP.iow2.arr[113]; +wire [63:0] Q_455 = ITOP.iow3.arr[113]; +wire [63:0] Q_456 = ITOP.iow0.arr[114]; +wire [63:0] Q_457 = ITOP.iow1.arr[114]; +wire [63:0] Q_458 = ITOP.iow2.arr[114]; +wire [63:0] Q_459 = ITOP.iow3.arr[114]; +wire [63:0] Q_460 = ITOP.iow0.arr[115]; +wire [63:0] Q_461 = ITOP.iow1.arr[115]; +wire [63:0] Q_462 = ITOP.iow2.arr[115]; +wire [63:0] Q_463 = ITOP.iow3.arr[115]; +wire [63:0] Q_464 = ITOP.iow0.arr[116]; +wire [63:0] Q_465 = ITOP.iow1.arr[116]; +wire [63:0] Q_466 = ITOP.iow2.arr[116]; +wire [63:0] Q_467 = ITOP.iow3.arr[116]; +wire [63:0] Q_468 = ITOP.iow0.arr[117]; +wire [63:0] Q_469 = ITOP.iow1.arr[117]; +wire [63:0] Q_470 = ITOP.iow2.arr[117]; +wire [63:0] Q_471 = ITOP.iow3.arr[117]; +wire [63:0] Q_472 = ITOP.iow0.arr[118]; +wire [63:0] Q_473 = ITOP.iow1.arr[118]; +wire [63:0] Q_474 = ITOP.iow2.arr[118]; +wire [63:0] Q_475 = ITOP.iow3.arr[118]; +wire [63:0] Q_476 = ITOP.iow0.arr[119]; +wire [63:0] Q_477 = ITOP.iow1.arr[119]; +wire [63:0] Q_478 = ITOP.iow2.arr[119]; +wire [63:0] Q_479 = ITOP.iow3.arr[119]; +wire [63:0] Q_480 = ITOP.iow0.arr[120]; +wire [63:0] Q_481 = ITOP.iow1.arr[120]; +wire [63:0] Q_482 = ITOP.iow2.arr[120]; +wire [63:0] Q_483 = ITOP.iow3.arr[120]; +wire [63:0] Q_484 = ITOP.iow0.arr[121]; +wire [63:0] Q_485 = ITOP.iow1.arr[121]; +wire [63:0] Q_486 = ITOP.iow2.arr[121]; +wire [63:0] Q_487 = ITOP.iow3.arr[121]; +wire [63:0] Q_488 = ITOP.iow0.arr[122]; +wire [63:0] Q_489 = ITOP.iow1.arr[122]; +wire [63:0] Q_490 = ITOP.iow2.arr[122]; +wire [63:0] Q_491 = ITOP.iow3.arr[122]; +wire [63:0] Q_492 = ITOP.iow0.arr[123]; +wire [63:0] Q_493 = ITOP.iow1.arr[123]; +wire [63:0] Q_494 = ITOP.iow2.arr[123]; +wire [63:0] Q_495 = ITOP.iow3.arr[123]; +wire [63:0] Q_496 = ITOP.iow0.arr[124]; +wire [63:0] Q_497 = ITOP.iow1.arr[124]; +wire [63:0] Q_498 = ITOP.iow2.arr[124]; +wire [63:0] Q_499 = ITOP.iow3.arr[124]; +wire [63:0] Q_500 = ITOP.iow0.arr[125]; +wire [63:0] Q_501 = ITOP.iow1.arr[125]; +wire [63:0] Q_502 = ITOP.iow2.arr[125]; +wire [63:0] Q_503 = ITOP.iow3.arr[125]; +wire [63:0] Q_504 = ITOP.iow0.arr[126]; +wire [63:0] Q_505 = ITOP.iow1.arr[126]; +wire [63:0] Q_506 = ITOP.iow2.arr[126]; +wire [63:0] Q_507 = ITOP.iow3.arr[126]; +wire [63:0] Q_508 = ITOP.iow0.arr[127]; +wire [63:0] Q_509 = ITOP.iow1.arr[127]; +wire [63:0] Q_510 = ITOP.iow2.arr[127]; +wire [63:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X64_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [8:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [63:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [63:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {64{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {64{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {64{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0; + assign rmuxd1 = {64{RdClk1}} & ~dout1; + assign rmuxd2 = {64{RdClk2}} & ~dout2; + assign rmuxd3 = {64{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0] | rmuxd1[63:0] | rmuxd2[63:0] | rmuxd3[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [8:0] addr; +reg [63:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X64_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 64'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 64'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 64'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 64'bx; + for (i=0; i<=63; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [255:0] data; + reg [63:0] wr[3:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [6:0] addr; + reg [255:0] mon_row; + reg [63:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [6:0] addr; + reg [255:0] mon_row; + reg [63:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow1.arr[0]; +wire [63:0] Q_2 = ITOP.iow2.arr[0]; +wire [63:0] Q_3 = ITOP.iow3.arr[0]; +wire [63:0] Q_4 = ITOP.iow0.arr[1]; +wire [63:0] Q_5 = ITOP.iow1.arr[1]; +wire [63:0] Q_6 = ITOP.iow2.arr[1]; +wire [63:0] Q_7 = ITOP.iow3.arr[1]; +wire [63:0] Q_8 = ITOP.iow0.arr[2]; +wire [63:0] Q_9 = ITOP.iow1.arr[2]; +wire [63:0] Q_10 = ITOP.iow2.arr[2]; +wire [63:0] Q_11 = ITOP.iow3.arr[2]; +wire [63:0] Q_12 = ITOP.iow0.arr[3]; +wire [63:0] Q_13 = ITOP.iow1.arr[3]; +wire [63:0] Q_14 = ITOP.iow2.arr[3]; +wire [63:0] Q_15 = ITOP.iow3.arr[3]; +wire [63:0] Q_16 = ITOP.iow0.arr[4]; +wire [63:0] Q_17 = ITOP.iow1.arr[4]; +wire [63:0] Q_18 = ITOP.iow2.arr[4]; +wire [63:0] Q_19 = ITOP.iow3.arr[4]; +wire [63:0] Q_20 = ITOP.iow0.arr[5]; +wire [63:0] Q_21 = ITOP.iow1.arr[5]; +wire [63:0] Q_22 = ITOP.iow2.arr[5]; +wire [63:0] Q_23 = ITOP.iow3.arr[5]; +wire [63:0] Q_24 = ITOP.iow0.arr[6]; +wire [63:0] Q_25 = ITOP.iow1.arr[6]; +wire [63:0] Q_26 = ITOP.iow2.arr[6]; +wire [63:0] Q_27 = ITOP.iow3.arr[6]; +wire [63:0] Q_28 = ITOP.iow0.arr[7]; +wire [63:0] Q_29 = ITOP.iow1.arr[7]; +wire [63:0] Q_30 = ITOP.iow2.arr[7]; +wire [63:0] Q_31 = ITOP.iow3.arr[7]; +wire [63:0] Q_32 = ITOP.iow0.arr[8]; +wire [63:0] Q_33 = ITOP.iow1.arr[8]; +wire [63:0] Q_34 = ITOP.iow2.arr[8]; +wire [63:0] Q_35 = ITOP.iow3.arr[8]; +wire [63:0] Q_36 = ITOP.iow0.arr[9]; +wire [63:0] Q_37 = ITOP.iow1.arr[9]; +wire [63:0] Q_38 = ITOP.iow2.arr[9]; +wire [63:0] Q_39 = ITOP.iow3.arr[9]; +wire [63:0] Q_40 = ITOP.iow0.arr[10]; +wire [63:0] Q_41 = ITOP.iow1.arr[10]; +wire [63:0] Q_42 = ITOP.iow2.arr[10]; +wire [63:0] Q_43 = ITOP.iow3.arr[10]; +wire [63:0] Q_44 = ITOP.iow0.arr[11]; +wire [63:0] Q_45 = ITOP.iow1.arr[11]; +wire [63:0] Q_46 = ITOP.iow2.arr[11]; +wire [63:0] Q_47 = ITOP.iow3.arr[11]; +wire [63:0] Q_48 = ITOP.iow0.arr[12]; +wire [63:0] Q_49 = ITOP.iow1.arr[12]; +wire [63:0] Q_50 = ITOP.iow2.arr[12]; +wire [63:0] Q_51 = ITOP.iow3.arr[12]; +wire [63:0] Q_52 = ITOP.iow0.arr[13]; +wire [63:0] Q_53 = ITOP.iow1.arr[13]; +wire [63:0] Q_54 = ITOP.iow2.arr[13]; +wire [63:0] Q_55 = ITOP.iow3.arr[13]; +wire [63:0] Q_56 = ITOP.iow0.arr[14]; +wire [63:0] Q_57 = ITOP.iow1.arr[14]; +wire [63:0] Q_58 = ITOP.iow2.arr[14]; +wire [63:0] Q_59 = ITOP.iow3.arr[14]; +wire [63:0] Q_60 = ITOP.iow0.arr[15]; +wire [63:0] Q_61 = ITOP.iow1.arr[15]; +wire [63:0] Q_62 = ITOP.iow2.arr[15]; +wire [63:0] Q_63 = ITOP.iow3.arr[15]; +wire [63:0] Q_64 = ITOP.iow0.arr[16]; +wire [63:0] Q_65 = ITOP.iow1.arr[16]; +wire [63:0] Q_66 = ITOP.iow2.arr[16]; +wire [63:0] Q_67 = ITOP.iow3.arr[16]; +wire [63:0] Q_68 = ITOP.iow0.arr[17]; +wire [63:0] Q_69 = ITOP.iow1.arr[17]; +wire [63:0] Q_70 = ITOP.iow2.arr[17]; +wire [63:0] Q_71 = ITOP.iow3.arr[17]; +wire [63:0] Q_72 = ITOP.iow0.arr[18]; +wire [63:0] Q_73 = ITOP.iow1.arr[18]; +wire [63:0] Q_74 = ITOP.iow2.arr[18]; +wire [63:0] Q_75 = ITOP.iow3.arr[18]; +wire [63:0] Q_76 = ITOP.iow0.arr[19]; +wire [63:0] Q_77 = ITOP.iow1.arr[19]; +wire [63:0] Q_78 = ITOP.iow2.arr[19]; +wire [63:0] Q_79 = ITOP.iow3.arr[19]; +wire [63:0] Q_80 = ITOP.iow0.arr[20]; +wire [63:0] Q_81 = ITOP.iow1.arr[20]; +wire [63:0] Q_82 = ITOP.iow2.arr[20]; +wire [63:0] Q_83 = ITOP.iow3.arr[20]; +wire [63:0] Q_84 = ITOP.iow0.arr[21]; +wire [63:0] Q_85 = ITOP.iow1.arr[21]; +wire [63:0] Q_86 = ITOP.iow2.arr[21]; +wire [63:0] Q_87 = ITOP.iow3.arr[21]; +wire [63:0] Q_88 = ITOP.iow0.arr[22]; +wire [63:0] Q_89 = ITOP.iow1.arr[22]; +wire [63:0] Q_90 = ITOP.iow2.arr[22]; +wire [63:0] Q_91 = ITOP.iow3.arr[22]; +wire [63:0] Q_92 = ITOP.iow0.arr[23]; +wire [63:0] Q_93 = ITOP.iow1.arr[23]; +wire [63:0] Q_94 = ITOP.iow2.arr[23]; +wire [63:0] Q_95 = ITOP.iow3.arr[23]; +wire [63:0] Q_96 = ITOP.iow0.arr[24]; +wire [63:0] Q_97 = ITOP.iow1.arr[24]; +wire [63:0] Q_98 = ITOP.iow2.arr[24]; +wire [63:0] Q_99 = ITOP.iow3.arr[24]; +wire [63:0] Q_100 = ITOP.iow0.arr[25]; +wire [63:0] Q_101 = ITOP.iow1.arr[25]; +wire [63:0] Q_102 = ITOP.iow2.arr[25]; +wire [63:0] Q_103 = ITOP.iow3.arr[25]; +wire [63:0] Q_104 = ITOP.iow0.arr[26]; +wire [63:0] Q_105 = ITOP.iow1.arr[26]; +wire [63:0] Q_106 = ITOP.iow2.arr[26]; +wire [63:0] Q_107 = ITOP.iow3.arr[26]; +wire [63:0] Q_108 = ITOP.iow0.arr[27]; +wire [63:0] Q_109 = ITOP.iow1.arr[27]; +wire [63:0] Q_110 = ITOP.iow2.arr[27]; +wire [63:0] Q_111 = ITOP.iow3.arr[27]; +wire [63:0] Q_112 = ITOP.iow0.arr[28]; +wire [63:0] Q_113 = ITOP.iow1.arr[28]; +wire [63:0] Q_114 = ITOP.iow2.arr[28]; +wire [63:0] Q_115 = ITOP.iow3.arr[28]; +wire [63:0] Q_116 = ITOP.iow0.arr[29]; +wire [63:0] Q_117 = ITOP.iow1.arr[29]; +wire [63:0] Q_118 = ITOP.iow2.arr[29]; +wire [63:0] Q_119 = ITOP.iow3.arr[29]; +wire [63:0] Q_120 = ITOP.iow0.arr[30]; +wire [63:0] Q_121 = ITOP.iow1.arr[30]; +wire [63:0] Q_122 = ITOP.iow2.arr[30]; +wire [63:0] Q_123 = ITOP.iow3.arr[30]; +wire [63:0] Q_124 = ITOP.iow0.arr[31]; +wire [63:0] Q_125 = ITOP.iow1.arr[31]; +wire [63:0] Q_126 = ITOP.iow2.arr[31]; +wire [63:0] Q_127 = ITOP.iow3.arr[31]; +wire [63:0] Q_128 = ITOP.iow0.arr[32]; +wire [63:0] Q_129 = ITOP.iow1.arr[32]; +wire [63:0] Q_130 = ITOP.iow2.arr[32]; +wire [63:0] Q_131 = ITOP.iow3.arr[32]; +wire [63:0] Q_132 = ITOP.iow0.arr[33]; +wire [63:0] Q_133 = ITOP.iow1.arr[33]; +wire [63:0] Q_134 = ITOP.iow2.arr[33]; +wire [63:0] Q_135 = ITOP.iow3.arr[33]; +wire [63:0] Q_136 = ITOP.iow0.arr[34]; +wire [63:0] Q_137 = ITOP.iow1.arr[34]; +wire [63:0] Q_138 = ITOP.iow2.arr[34]; +wire [63:0] Q_139 = ITOP.iow3.arr[34]; +wire [63:0] Q_140 = ITOP.iow0.arr[35]; +wire [63:0] Q_141 = ITOP.iow1.arr[35]; +wire [63:0] Q_142 = ITOP.iow2.arr[35]; +wire [63:0] Q_143 = ITOP.iow3.arr[35]; +wire [63:0] Q_144 = ITOP.iow0.arr[36]; +wire [63:0] Q_145 = ITOP.iow1.arr[36]; +wire [63:0] Q_146 = ITOP.iow2.arr[36]; +wire [63:0] Q_147 = ITOP.iow3.arr[36]; +wire [63:0] Q_148 = ITOP.iow0.arr[37]; +wire [63:0] Q_149 = ITOP.iow1.arr[37]; +wire [63:0] Q_150 = ITOP.iow2.arr[37]; +wire [63:0] Q_151 = ITOP.iow3.arr[37]; +wire [63:0] Q_152 = ITOP.iow0.arr[38]; +wire [63:0] Q_153 = ITOP.iow1.arr[38]; +wire [63:0] Q_154 = ITOP.iow2.arr[38]; +wire [63:0] Q_155 = ITOP.iow3.arr[38]; +wire [63:0] Q_156 = ITOP.iow0.arr[39]; +wire [63:0] Q_157 = ITOP.iow1.arr[39]; +wire [63:0] Q_158 = ITOP.iow2.arr[39]; +wire [63:0] Q_159 = ITOP.iow3.arr[39]; +wire [63:0] Q_160 = ITOP.iow0.arr[40]; +wire [63:0] Q_161 = ITOP.iow1.arr[40]; +wire [63:0] Q_162 = ITOP.iow2.arr[40]; +wire [63:0] Q_163 = ITOP.iow3.arr[40]; +wire [63:0] Q_164 = ITOP.iow0.arr[41]; +wire [63:0] Q_165 = ITOP.iow1.arr[41]; +wire [63:0] Q_166 = ITOP.iow2.arr[41]; +wire [63:0] Q_167 = ITOP.iow3.arr[41]; +wire [63:0] Q_168 = ITOP.iow0.arr[42]; +wire [63:0] Q_169 = ITOP.iow1.arr[42]; +wire [63:0] Q_170 = ITOP.iow2.arr[42]; +wire [63:0] Q_171 = ITOP.iow3.arr[42]; +wire [63:0] Q_172 = ITOP.iow0.arr[43]; +wire [63:0] Q_173 = ITOP.iow1.arr[43]; +wire [63:0] Q_174 = ITOP.iow2.arr[43]; +wire [63:0] Q_175 = ITOP.iow3.arr[43]; +wire [63:0] Q_176 = ITOP.iow0.arr[44]; +wire [63:0] Q_177 = ITOP.iow1.arr[44]; +wire [63:0] Q_178 = ITOP.iow2.arr[44]; +wire [63:0] Q_179 = ITOP.iow3.arr[44]; +wire [63:0] Q_180 = ITOP.iow0.arr[45]; +wire [63:0] Q_181 = ITOP.iow1.arr[45]; +wire [63:0] Q_182 = ITOP.iow2.arr[45]; +wire [63:0] Q_183 = ITOP.iow3.arr[45]; +wire [63:0] Q_184 = ITOP.iow0.arr[46]; +wire [63:0] Q_185 = ITOP.iow1.arr[46]; +wire [63:0] Q_186 = ITOP.iow2.arr[46]; +wire [63:0] Q_187 = ITOP.iow3.arr[46]; +wire [63:0] Q_188 = ITOP.iow0.arr[47]; +wire [63:0] Q_189 = ITOP.iow1.arr[47]; +wire [63:0] Q_190 = ITOP.iow2.arr[47]; +wire [63:0] Q_191 = ITOP.iow3.arr[47]; +wire [63:0] Q_192 = ITOP.iow0.arr[48]; +wire [63:0] Q_193 = ITOP.iow1.arr[48]; +wire [63:0] Q_194 = ITOP.iow2.arr[48]; +wire [63:0] Q_195 = ITOP.iow3.arr[48]; +wire [63:0] Q_196 = ITOP.iow0.arr[49]; +wire [63:0] Q_197 = ITOP.iow1.arr[49]; +wire [63:0] Q_198 = ITOP.iow2.arr[49]; +wire [63:0] Q_199 = ITOP.iow3.arr[49]; +wire [63:0] Q_200 = ITOP.iow0.arr[50]; +wire [63:0] Q_201 = ITOP.iow1.arr[50]; +wire [63:0] Q_202 = ITOP.iow2.arr[50]; +wire [63:0] Q_203 = ITOP.iow3.arr[50]; +wire [63:0] Q_204 = ITOP.iow0.arr[51]; +wire [63:0] Q_205 = ITOP.iow1.arr[51]; +wire [63:0] Q_206 = ITOP.iow2.arr[51]; +wire [63:0] Q_207 = ITOP.iow3.arr[51]; +wire [63:0] Q_208 = ITOP.iow0.arr[52]; +wire [63:0] Q_209 = ITOP.iow1.arr[52]; +wire [63:0] Q_210 = ITOP.iow2.arr[52]; +wire [63:0] Q_211 = ITOP.iow3.arr[52]; +wire [63:0] Q_212 = ITOP.iow0.arr[53]; +wire [63:0] Q_213 = ITOP.iow1.arr[53]; +wire [63:0] Q_214 = ITOP.iow2.arr[53]; +wire [63:0] Q_215 = ITOP.iow3.arr[53]; +wire [63:0] Q_216 = ITOP.iow0.arr[54]; +wire [63:0] Q_217 = ITOP.iow1.arr[54]; +wire [63:0] Q_218 = ITOP.iow2.arr[54]; +wire [63:0] Q_219 = ITOP.iow3.arr[54]; +wire [63:0] Q_220 = ITOP.iow0.arr[55]; +wire [63:0] Q_221 = ITOP.iow1.arr[55]; +wire [63:0] Q_222 = ITOP.iow2.arr[55]; +wire [63:0] Q_223 = ITOP.iow3.arr[55]; +wire [63:0] Q_224 = ITOP.iow0.arr[56]; +wire [63:0] Q_225 = ITOP.iow1.arr[56]; +wire [63:0] Q_226 = ITOP.iow2.arr[56]; +wire [63:0] Q_227 = ITOP.iow3.arr[56]; +wire [63:0] Q_228 = ITOP.iow0.arr[57]; +wire [63:0] Q_229 = ITOP.iow1.arr[57]; +wire [63:0] Q_230 = ITOP.iow2.arr[57]; +wire [63:0] Q_231 = ITOP.iow3.arr[57]; +wire [63:0] Q_232 = ITOP.iow0.arr[58]; +wire [63:0] Q_233 = ITOP.iow1.arr[58]; +wire [63:0] Q_234 = ITOP.iow2.arr[58]; +wire [63:0] Q_235 = ITOP.iow3.arr[58]; +wire [63:0] Q_236 = ITOP.iow0.arr[59]; +wire [63:0] Q_237 = ITOP.iow1.arr[59]; +wire [63:0] Q_238 = ITOP.iow2.arr[59]; +wire [63:0] Q_239 = ITOP.iow3.arr[59]; +wire [63:0] Q_240 = ITOP.iow0.arr[60]; +wire [63:0] Q_241 = ITOP.iow1.arr[60]; +wire [63:0] Q_242 = ITOP.iow2.arr[60]; +wire [63:0] Q_243 = ITOP.iow3.arr[60]; +wire [63:0] Q_244 = ITOP.iow0.arr[61]; +wire [63:0] Q_245 = ITOP.iow1.arr[61]; +wire [63:0] Q_246 = ITOP.iow2.arr[61]; +wire [63:0] Q_247 = ITOP.iow3.arr[61]; +wire [63:0] Q_248 = ITOP.iow0.arr[62]; +wire [63:0] Q_249 = ITOP.iow1.arr[62]; +wire [63:0] Q_250 = ITOP.iow2.arr[62]; +wire [63:0] Q_251 = ITOP.iow3.arr[62]; +wire [63:0] Q_252 = ITOP.iow0.arr[63]; +wire [63:0] Q_253 = ITOP.iow1.arr[63]; +wire [63:0] Q_254 = ITOP.iow2.arr[63]; +wire [63:0] Q_255 = ITOP.iow3.arr[63]; +wire [63:0] Q_256 = ITOP.iow0.arr[64]; +wire [63:0] Q_257 = ITOP.iow1.arr[64]; +wire [63:0] Q_258 = ITOP.iow2.arr[64]; +wire [63:0] Q_259 = ITOP.iow3.arr[64]; +wire [63:0] Q_260 = ITOP.iow0.arr[65]; +wire [63:0] Q_261 = ITOP.iow1.arr[65]; +wire [63:0] Q_262 = ITOP.iow2.arr[65]; +wire [63:0] Q_263 = ITOP.iow3.arr[65]; +wire [63:0] Q_264 = ITOP.iow0.arr[66]; +wire [63:0] Q_265 = ITOP.iow1.arr[66]; +wire [63:0] Q_266 = ITOP.iow2.arr[66]; +wire [63:0] Q_267 = ITOP.iow3.arr[66]; +wire [63:0] Q_268 = ITOP.iow0.arr[67]; +wire [63:0] Q_269 = ITOP.iow1.arr[67]; +wire [63:0] Q_270 = ITOP.iow2.arr[67]; +wire [63:0] Q_271 = ITOP.iow3.arr[67]; +wire [63:0] Q_272 = ITOP.iow0.arr[68]; +wire [63:0] Q_273 = ITOP.iow1.arr[68]; +wire [63:0] Q_274 = ITOP.iow2.arr[68]; +wire [63:0] Q_275 = ITOP.iow3.arr[68]; +wire [63:0] Q_276 = ITOP.iow0.arr[69]; +wire [63:0] Q_277 = ITOP.iow1.arr[69]; +wire [63:0] Q_278 = ITOP.iow2.arr[69]; +wire [63:0] Q_279 = ITOP.iow3.arr[69]; +wire [63:0] Q_280 = ITOP.iow0.arr[70]; +wire [63:0] Q_281 = ITOP.iow1.arr[70]; +wire [63:0] Q_282 = ITOP.iow2.arr[70]; +wire [63:0] Q_283 = ITOP.iow3.arr[70]; +wire [63:0] Q_284 = ITOP.iow0.arr[71]; +wire [63:0] Q_285 = ITOP.iow1.arr[71]; +wire [63:0] Q_286 = ITOP.iow2.arr[71]; +wire [63:0] Q_287 = ITOP.iow3.arr[71]; +wire [63:0] Q_288 = ITOP.iow0.arr[72]; +wire [63:0] Q_289 = ITOP.iow1.arr[72]; +wire [63:0] Q_290 = ITOP.iow2.arr[72]; +wire [63:0] Q_291 = ITOP.iow3.arr[72]; +wire [63:0] Q_292 = ITOP.iow0.arr[73]; +wire [63:0] Q_293 = ITOP.iow1.arr[73]; +wire [63:0] Q_294 = ITOP.iow2.arr[73]; +wire [63:0] Q_295 = ITOP.iow3.arr[73]; +wire [63:0] Q_296 = ITOP.iow0.arr[74]; +wire [63:0] Q_297 = ITOP.iow1.arr[74]; +wire [63:0] Q_298 = ITOP.iow2.arr[74]; +wire [63:0] Q_299 = ITOP.iow3.arr[74]; +wire [63:0] Q_300 = ITOP.iow0.arr[75]; +wire [63:0] Q_301 = ITOP.iow1.arr[75]; +wire [63:0] Q_302 = ITOP.iow2.arr[75]; +wire [63:0] Q_303 = ITOP.iow3.arr[75]; +wire [63:0] Q_304 = ITOP.iow0.arr[76]; +wire [63:0] Q_305 = ITOP.iow1.arr[76]; +wire [63:0] Q_306 = ITOP.iow2.arr[76]; +wire [63:0] Q_307 = ITOP.iow3.arr[76]; +wire [63:0] Q_308 = ITOP.iow0.arr[77]; +wire [63:0] Q_309 = ITOP.iow1.arr[77]; +wire [63:0] Q_310 = ITOP.iow2.arr[77]; +wire [63:0] Q_311 = ITOP.iow3.arr[77]; +wire [63:0] Q_312 = ITOP.iow0.arr[78]; +wire [63:0] Q_313 = ITOP.iow1.arr[78]; +wire [63:0] Q_314 = ITOP.iow2.arr[78]; +wire [63:0] Q_315 = ITOP.iow3.arr[78]; +wire [63:0] Q_316 = ITOP.iow0.arr[79]; +wire [63:0] Q_317 = ITOP.iow1.arr[79]; +wire [63:0] Q_318 = ITOP.iow2.arr[79]; +wire [63:0] Q_319 = ITOP.iow3.arr[79]; +wire [63:0] Q_320 = ITOP.iow0.arr[80]; +wire [63:0] Q_321 = ITOP.iow1.arr[80]; +wire [63:0] Q_322 = ITOP.iow2.arr[80]; +wire [63:0] Q_323 = ITOP.iow3.arr[80]; +wire [63:0] Q_324 = ITOP.iow0.arr[81]; +wire [63:0] Q_325 = ITOP.iow1.arr[81]; +wire [63:0] Q_326 = ITOP.iow2.arr[81]; +wire [63:0] Q_327 = ITOP.iow3.arr[81]; +wire [63:0] Q_328 = ITOP.iow0.arr[82]; +wire [63:0] Q_329 = ITOP.iow1.arr[82]; +wire [63:0] Q_330 = ITOP.iow2.arr[82]; +wire [63:0] Q_331 = ITOP.iow3.arr[82]; +wire [63:0] Q_332 = ITOP.iow0.arr[83]; +wire [63:0] Q_333 = ITOP.iow1.arr[83]; +wire [63:0] Q_334 = ITOP.iow2.arr[83]; +wire [63:0] Q_335 = ITOP.iow3.arr[83]; +wire [63:0] Q_336 = ITOP.iow0.arr[84]; +wire [63:0] Q_337 = ITOP.iow1.arr[84]; +wire [63:0] Q_338 = ITOP.iow2.arr[84]; +wire [63:0] Q_339 = ITOP.iow3.arr[84]; +wire [63:0] Q_340 = ITOP.iow0.arr[85]; +wire [63:0] Q_341 = ITOP.iow1.arr[85]; +wire [63:0] Q_342 = ITOP.iow2.arr[85]; +wire [63:0] Q_343 = ITOP.iow3.arr[85]; +wire [63:0] Q_344 = ITOP.iow0.arr[86]; +wire [63:0] Q_345 = ITOP.iow1.arr[86]; +wire [63:0] Q_346 = ITOP.iow2.arr[86]; +wire [63:0] Q_347 = ITOP.iow3.arr[86]; +wire [63:0] Q_348 = ITOP.iow0.arr[87]; +wire [63:0] Q_349 = ITOP.iow1.arr[87]; +wire [63:0] Q_350 = ITOP.iow2.arr[87]; +wire [63:0] Q_351 = ITOP.iow3.arr[87]; +wire [63:0] Q_352 = ITOP.iow0.arr[88]; +wire [63:0] Q_353 = ITOP.iow1.arr[88]; +wire [63:0] Q_354 = ITOP.iow2.arr[88]; +wire [63:0] Q_355 = ITOP.iow3.arr[88]; +wire [63:0] Q_356 = ITOP.iow0.arr[89]; +wire [63:0] Q_357 = ITOP.iow1.arr[89]; +wire [63:0] Q_358 = ITOP.iow2.arr[89]; +wire [63:0] Q_359 = ITOP.iow3.arr[89]; +wire [63:0] Q_360 = ITOP.iow0.arr[90]; +wire [63:0] Q_361 = ITOP.iow1.arr[90]; +wire [63:0] Q_362 = ITOP.iow2.arr[90]; +wire [63:0] Q_363 = ITOP.iow3.arr[90]; +wire [63:0] Q_364 = ITOP.iow0.arr[91]; +wire [63:0] Q_365 = ITOP.iow1.arr[91]; +wire [63:0] Q_366 = ITOP.iow2.arr[91]; +wire [63:0] Q_367 = ITOP.iow3.arr[91]; +wire [63:0] Q_368 = ITOP.iow0.arr[92]; +wire [63:0] Q_369 = ITOP.iow1.arr[92]; +wire [63:0] Q_370 = ITOP.iow2.arr[92]; +wire [63:0] Q_371 = ITOP.iow3.arr[92]; +wire [63:0] Q_372 = ITOP.iow0.arr[93]; +wire [63:0] Q_373 = ITOP.iow1.arr[93]; +wire [63:0] Q_374 = ITOP.iow2.arr[93]; +wire [63:0] Q_375 = ITOP.iow3.arr[93]; +wire [63:0] Q_376 = ITOP.iow0.arr[94]; +wire [63:0] Q_377 = ITOP.iow1.arr[94]; +wire [63:0] Q_378 = ITOP.iow2.arr[94]; +wire [63:0] Q_379 = ITOP.iow3.arr[94]; +wire [63:0] Q_380 = ITOP.iow0.arr[95]; +wire [63:0] Q_381 = ITOP.iow1.arr[95]; +wire [63:0] Q_382 = ITOP.iow2.arr[95]; +wire [63:0] Q_383 = ITOP.iow3.arr[95]; +wire [63:0] Q_384 = ITOP.iow0.arr[96]; +wire [63:0] Q_385 = ITOP.iow1.arr[96]; +wire [63:0] Q_386 = ITOP.iow2.arr[96]; +wire [63:0] Q_387 = ITOP.iow3.arr[96]; +wire [63:0] Q_388 = ITOP.iow0.arr[97]; +wire [63:0] Q_389 = ITOP.iow1.arr[97]; +wire [63:0] Q_390 = ITOP.iow2.arr[97]; +wire [63:0] Q_391 = ITOP.iow3.arr[97]; +wire [63:0] Q_392 = ITOP.iow0.arr[98]; +wire [63:0] Q_393 = ITOP.iow1.arr[98]; +wire [63:0] Q_394 = ITOP.iow2.arr[98]; +wire [63:0] Q_395 = ITOP.iow3.arr[98]; +wire [63:0] Q_396 = ITOP.iow0.arr[99]; +wire [63:0] Q_397 = ITOP.iow1.arr[99]; +wire [63:0] Q_398 = ITOP.iow2.arr[99]; +wire [63:0] Q_399 = ITOP.iow3.arr[99]; +wire [63:0] Q_400 = ITOP.iow0.arr[100]; +wire [63:0] Q_401 = ITOP.iow1.arr[100]; +wire [63:0] Q_402 = ITOP.iow2.arr[100]; +wire [63:0] Q_403 = ITOP.iow3.arr[100]; +wire [63:0] Q_404 = ITOP.iow0.arr[101]; +wire [63:0] Q_405 = ITOP.iow1.arr[101]; +wire [63:0] Q_406 = ITOP.iow2.arr[101]; +wire [63:0] Q_407 = ITOP.iow3.arr[101]; +wire [63:0] Q_408 = ITOP.iow0.arr[102]; +wire [63:0] Q_409 = ITOP.iow1.arr[102]; +wire [63:0] Q_410 = ITOP.iow2.arr[102]; +wire [63:0] Q_411 = ITOP.iow3.arr[102]; +wire [63:0] Q_412 = ITOP.iow0.arr[103]; +wire [63:0] Q_413 = ITOP.iow1.arr[103]; +wire [63:0] Q_414 = ITOP.iow2.arr[103]; +wire [63:0] Q_415 = ITOP.iow3.arr[103]; +wire [63:0] Q_416 = ITOP.iow0.arr[104]; +wire [63:0] Q_417 = ITOP.iow1.arr[104]; +wire [63:0] Q_418 = ITOP.iow2.arr[104]; +wire [63:0] Q_419 = ITOP.iow3.arr[104]; +wire [63:0] Q_420 = ITOP.iow0.arr[105]; +wire [63:0] Q_421 = ITOP.iow1.arr[105]; +wire [63:0] Q_422 = ITOP.iow2.arr[105]; +wire [63:0] Q_423 = ITOP.iow3.arr[105]; +wire [63:0] Q_424 = ITOP.iow0.arr[106]; +wire [63:0] Q_425 = ITOP.iow1.arr[106]; +wire [63:0] Q_426 = ITOP.iow2.arr[106]; +wire [63:0] Q_427 = ITOP.iow3.arr[106]; +wire [63:0] Q_428 = ITOP.iow0.arr[107]; +wire [63:0] Q_429 = ITOP.iow1.arr[107]; +wire [63:0] Q_430 = ITOP.iow2.arr[107]; +wire [63:0] Q_431 = ITOP.iow3.arr[107]; +wire [63:0] Q_432 = ITOP.iow0.arr[108]; +wire [63:0] Q_433 = ITOP.iow1.arr[108]; +wire [63:0] Q_434 = ITOP.iow2.arr[108]; +wire [63:0] Q_435 = ITOP.iow3.arr[108]; +wire [63:0] Q_436 = ITOP.iow0.arr[109]; +wire [63:0] Q_437 = ITOP.iow1.arr[109]; +wire [63:0] Q_438 = ITOP.iow2.arr[109]; +wire [63:0] Q_439 = ITOP.iow3.arr[109]; +wire [63:0] Q_440 = ITOP.iow0.arr[110]; +wire [63:0] Q_441 = ITOP.iow1.arr[110]; +wire [63:0] Q_442 = ITOP.iow2.arr[110]; +wire [63:0] Q_443 = ITOP.iow3.arr[110]; +wire [63:0] Q_444 = ITOP.iow0.arr[111]; +wire [63:0] Q_445 = ITOP.iow1.arr[111]; +wire [63:0] Q_446 = ITOP.iow2.arr[111]; +wire [63:0] Q_447 = ITOP.iow3.arr[111]; +wire [63:0] Q_448 = ITOP.iow0.arr[112]; +wire [63:0] Q_449 = ITOP.iow1.arr[112]; +wire [63:0] Q_450 = ITOP.iow2.arr[112]; +wire [63:0] Q_451 = ITOP.iow3.arr[112]; +wire [63:0] Q_452 = ITOP.iow0.arr[113]; +wire [63:0] Q_453 = ITOP.iow1.arr[113]; +wire [63:0] Q_454 = ITOP.iow2.arr[113]; +wire [63:0] Q_455 = ITOP.iow3.arr[113]; +wire [63:0] Q_456 = ITOP.iow0.arr[114]; +wire [63:0] Q_457 = ITOP.iow1.arr[114]; +wire [63:0] Q_458 = ITOP.iow2.arr[114]; +wire [63:0] Q_459 = ITOP.iow3.arr[114]; +wire [63:0] Q_460 = ITOP.iow0.arr[115]; +wire [63:0] Q_461 = ITOP.iow1.arr[115]; +wire [63:0] Q_462 = ITOP.iow2.arr[115]; +wire [63:0] Q_463 = ITOP.iow3.arr[115]; +wire [63:0] Q_464 = ITOP.iow0.arr[116]; +wire [63:0] Q_465 = ITOP.iow1.arr[116]; +wire [63:0] Q_466 = ITOP.iow2.arr[116]; +wire [63:0] Q_467 = ITOP.iow3.arr[116]; +wire [63:0] Q_468 = ITOP.iow0.arr[117]; +wire [63:0] Q_469 = ITOP.iow1.arr[117]; +wire [63:0] Q_470 = ITOP.iow2.arr[117]; +wire [63:0] Q_471 = ITOP.iow3.arr[117]; +wire [63:0] Q_472 = ITOP.iow0.arr[118]; +wire [63:0] Q_473 = ITOP.iow1.arr[118]; +wire [63:0] Q_474 = ITOP.iow2.arr[118]; +wire [63:0] Q_475 = ITOP.iow3.arr[118]; +wire [63:0] Q_476 = ITOP.iow0.arr[119]; +wire [63:0] Q_477 = ITOP.iow1.arr[119]; +wire [63:0] Q_478 = ITOP.iow2.arr[119]; +wire [63:0] Q_479 = ITOP.iow3.arr[119]; +wire [63:0] Q_480 = ITOP.iow0.arr[120]; +wire [63:0] Q_481 = ITOP.iow1.arr[120]; +wire [63:0] Q_482 = ITOP.iow2.arr[120]; +wire [63:0] Q_483 = ITOP.iow3.arr[120]; +wire [63:0] Q_484 = ITOP.iow0.arr[121]; +wire [63:0] Q_485 = ITOP.iow1.arr[121]; +wire [63:0] Q_486 = ITOP.iow2.arr[121]; +wire [63:0] Q_487 = ITOP.iow3.arr[121]; +wire [63:0] Q_488 = ITOP.iow0.arr[122]; +wire [63:0] Q_489 = ITOP.iow1.arr[122]; +wire [63:0] Q_490 = ITOP.iow2.arr[122]; +wire [63:0] Q_491 = ITOP.iow3.arr[122]; +wire [63:0] Q_492 = ITOP.iow0.arr[123]; +wire [63:0] Q_493 = ITOP.iow1.arr[123]; +wire [63:0] Q_494 = ITOP.iow2.arr[123]; +wire [63:0] Q_495 = ITOP.iow3.arr[123]; +wire [63:0] Q_496 = ITOP.iow0.arr[124]; +wire [63:0] Q_497 = ITOP.iow1.arr[124]; +wire [63:0] Q_498 = ITOP.iow2.arr[124]; +wire [63:0] Q_499 = ITOP.iow3.arr[124]; +wire [63:0] Q_500 = ITOP.iow0.arr[125]; +wire [63:0] Q_501 = ITOP.iow1.arr[125]; +wire [63:0] Q_502 = ITOP.iow2.arr[125]; +wire [63:0] Q_503 = ITOP.iow3.arr[125]; +wire [63:0] Q_504 = ITOP.iow0.arr[126]; +wire [63:0] Q_505 = ITOP.iow1.arr[126]; +wire [63:0] Q_506 = ITOP.iow2.arr[126]; +wire [63:0] Q_507 = ITOP.iow3.arr[126]; +wire [63:0] Q_508 = ITOP.iow0.arr[127]; +wire [63:0] Q_509 = ITOP.iow1.arr[127]; +wire [63:0] Q_510 = ITOP.iow2.arr[127]; +wire [63:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X64_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [8:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [63:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [63:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {64{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {64{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {64{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0; + assign rmuxd1 = {64{RdClk1}} & ~dout1; + assign rmuxd2 = {64{RdClk2}} & ~dout2; + assign rmuxd3 = {64{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0] | rmuxd1[63:0] | rmuxd2[63:0] | rmuxd3[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X64_GL_M4_D2_ram # (128, 64, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [8:0] addr; +reg [63:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X64_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [71:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [71:0] val; + integer i; + begin + val = {72{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [71:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 72'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 72'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 72'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 72'bx; + for (i=0; i<=71; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [71:0] wr[3:0]; + integer i; + begin + for (i=0; i<=71; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [71:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [71:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [71:0] Q_0 = ITOP.iow0.arr[0]; +wire [71:0] Q_1 = ITOP.iow1.arr[0]; +wire [71:0] Q_2 = ITOP.iow2.arr[0]; +wire [71:0] Q_3 = ITOP.iow3.arr[0]; +wire [71:0] Q_4 = ITOP.iow0.arr[1]; +wire [71:0] Q_5 = ITOP.iow1.arr[1]; +wire [71:0] Q_6 = ITOP.iow2.arr[1]; +wire [71:0] Q_7 = ITOP.iow3.arr[1]; +wire [71:0] Q_8 = ITOP.iow0.arr[2]; +wire [71:0] Q_9 = ITOP.iow1.arr[2]; +wire [71:0] Q_10 = ITOP.iow2.arr[2]; +wire [71:0] Q_11 = ITOP.iow3.arr[2]; +wire [71:0] Q_12 = ITOP.iow0.arr[3]; +wire [71:0] Q_13 = ITOP.iow1.arr[3]; +wire [71:0] Q_14 = ITOP.iow2.arr[3]; +wire [71:0] Q_15 = ITOP.iow3.arr[3]; +wire [71:0] Q_16 = ITOP.iow0.arr[4]; +wire [71:0] Q_17 = ITOP.iow1.arr[4]; +wire [71:0] Q_18 = ITOP.iow2.arr[4]; +wire [71:0] Q_19 = ITOP.iow3.arr[4]; +wire [71:0] Q_20 = ITOP.iow0.arr[5]; +wire [71:0] Q_21 = ITOP.iow1.arr[5]; +wire [71:0] Q_22 = ITOP.iow2.arr[5]; +wire [71:0] Q_23 = ITOP.iow3.arr[5]; +wire [71:0] Q_24 = ITOP.iow0.arr[6]; +wire [71:0] Q_25 = ITOP.iow1.arr[6]; +wire [71:0] Q_26 = ITOP.iow2.arr[6]; +wire [71:0] Q_27 = ITOP.iow3.arr[6]; +wire [71:0] Q_28 = ITOP.iow0.arr[7]; +wire [71:0] Q_29 = ITOP.iow1.arr[7]; +wire [71:0] Q_30 = ITOP.iow2.arr[7]; +wire [71:0] Q_31 = ITOP.iow3.arr[7]; +wire [71:0] Q_32 = ITOP.iow0.arr[8]; +wire [71:0] Q_33 = ITOP.iow1.arr[8]; +wire [71:0] Q_34 = ITOP.iow2.arr[8]; +wire [71:0] Q_35 = ITOP.iow3.arr[8]; +wire [71:0] Q_36 = ITOP.iow0.arr[9]; +wire [71:0] Q_37 = ITOP.iow1.arr[9]; +wire [71:0] Q_38 = ITOP.iow2.arr[9]; +wire [71:0] Q_39 = ITOP.iow3.arr[9]; +wire [71:0] Q_40 = ITOP.iow0.arr[10]; +wire [71:0] Q_41 = ITOP.iow1.arr[10]; +wire [71:0] Q_42 = ITOP.iow2.arr[10]; +wire [71:0] Q_43 = ITOP.iow3.arr[10]; +wire [71:0] Q_44 = ITOP.iow0.arr[11]; +wire [71:0] Q_45 = ITOP.iow1.arr[11]; +wire [71:0] Q_46 = ITOP.iow2.arr[11]; +wire [71:0] Q_47 = ITOP.iow3.arr[11]; +wire [71:0] Q_48 = ITOP.iow0.arr[12]; +wire [71:0] Q_49 = ITOP.iow1.arr[12]; +wire [71:0] Q_50 = ITOP.iow2.arr[12]; +wire [71:0] Q_51 = ITOP.iow3.arr[12]; +wire [71:0] Q_52 = ITOP.iow0.arr[13]; +wire [71:0] Q_53 = ITOP.iow1.arr[13]; +wire [71:0] Q_54 = ITOP.iow2.arr[13]; +wire [71:0] Q_55 = ITOP.iow3.arr[13]; +wire [71:0] Q_56 = ITOP.iow0.arr[14]; +wire [71:0] Q_57 = ITOP.iow1.arr[14]; +wire [71:0] Q_58 = ITOP.iow2.arr[14]; +wire [71:0] Q_59 = ITOP.iow3.arr[14]; +wire [71:0] Q_60 = ITOP.iow0.arr[15]; +wire [71:0] Q_61 = ITOP.iow1.arr[15]; +wire [71:0] Q_62 = ITOP.iow2.arr[15]; +wire [71:0] Q_63 = ITOP.iow3.arr[15]; +wire [71:0] Q_64 = ITOP.iow0.arr[16]; +wire [71:0] Q_65 = ITOP.iow1.arr[16]; +wire [71:0] Q_66 = ITOP.iow2.arr[16]; +wire [71:0] Q_67 = ITOP.iow3.arr[16]; +wire [71:0] Q_68 = ITOP.iow0.arr[17]; +wire [71:0] Q_69 = ITOP.iow1.arr[17]; +wire [71:0] Q_70 = ITOP.iow2.arr[17]; +wire [71:0] Q_71 = ITOP.iow3.arr[17]; +wire [71:0] Q_72 = ITOP.iow0.arr[18]; +wire [71:0] Q_73 = ITOP.iow1.arr[18]; +wire [71:0] Q_74 = ITOP.iow2.arr[18]; +wire [71:0] Q_75 = ITOP.iow3.arr[18]; +wire [71:0] Q_76 = ITOP.iow0.arr[19]; +wire [71:0] Q_77 = ITOP.iow1.arr[19]; +wire [71:0] Q_78 = ITOP.iow2.arr[19]; +wire [71:0] Q_79 = ITOP.iow3.arr[19]; +wire [71:0] Q_80 = ITOP.iow0.arr[20]; +wire [71:0] Q_81 = ITOP.iow1.arr[20]; +wire [71:0] Q_82 = ITOP.iow2.arr[20]; +wire [71:0] Q_83 = ITOP.iow3.arr[20]; +wire [71:0] Q_84 = ITOP.iow0.arr[21]; +wire [71:0] Q_85 = ITOP.iow1.arr[21]; +wire [71:0] Q_86 = ITOP.iow2.arr[21]; +wire [71:0] Q_87 = ITOP.iow3.arr[21]; +wire [71:0] Q_88 = ITOP.iow0.arr[22]; +wire [71:0] Q_89 = ITOP.iow1.arr[22]; +wire [71:0] Q_90 = ITOP.iow2.arr[22]; +wire [71:0] Q_91 = ITOP.iow3.arr[22]; +wire [71:0] Q_92 = ITOP.iow0.arr[23]; +wire [71:0] Q_93 = ITOP.iow1.arr[23]; +wire [71:0] Q_94 = ITOP.iow2.arr[23]; +wire [71:0] Q_95 = ITOP.iow3.arr[23]; +wire [71:0] Q_96 = ITOP.iow0.arr[24]; +wire [71:0] Q_97 = ITOP.iow1.arr[24]; +wire [71:0] Q_98 = ITOP.iow2.arr[24]; +wire [71:0] Q_99 = ITOP.iow3.arr[24]; +wire [71:0] Q_100 = ITOP.iow0.arr[25]; +wire [71:0] Q_101 = ITOP.iow1.arr[25]; +wire [71:0] Q_102 = ITOP.iow2.arr[25]; +wire [71:0] Q_103 = ITOP.iow3.arr[25]; +wire [71:0] Q_104 = ITOP.iow0.arr[26]; +wire [71:0] Q_105 = ITOP.iow1.arr[26]; +wire [71:0] Q_106 = ITOP.iow2.arr[26]; +wire [71:0] Q_107 = ITOP.iow3.arr[26]; +wire [71:0] Q_108 = ITOP.iow0.arr[27]; +wire [71:0] Q_109 = ITOP.iow1.arr[27]; +wire [71:0] Q_110 = ITOP.iow2.arr[27]; +wire [71:0] Q_111 = ITOP.iow3.arr[27]; +wire [71:0] Q_112 = ITOP.iow0.arr[28]; +wire [71:0] Q_113 = ITOP.iow1.arr[28]; +wire [71:0] Q_114 = ITOP.iow2.arr[28]; +wire [71:0] Q_115 = ITOP.iow3.arr[28]; +wire [71:0] Q_116 = ITOP.iow0.arr[29]; +wire [71:0] Q_117 = ITOP.iow1.arr[29]; +wire [71:0] Q_118 = ITOP.iow2.arr[29]; +wire [71:0] Q_119 = ITOP.iow3.arr[29]; +wire [71:0] Q_120 = ITOP.iow0.arr[30]; +wire [71:0] Q_121 = ITOP.iow1.arr[30]; +wire [71:0] Q_122 = ITOP.iow2.arr[30]; +wire [71:0] Q_123 = ITOP.iow3.arr[30]; +wire [71:0] Q_124 = ITOP.iow0.arr[31]; +wire [71:0] Q_125 = ITOP.iow1.arr[31]; +wire [71:0] Q_126 = ITOP.iow2.arr[31]; +wire [71:0] Q_127 = ITOP.iow3.arr[31]; +wire [71:0] Q_128 = ITOP.iow0.arr[32]; +wire [71:0] Q_129 = ITOP.iow1.arr[32]; +wire [71:0] Q_130 = ITOP.iow2.arr[32]; +wire [71:0] Q_131 = ITOP.iow3.arr[32]; +wire [71:0] Q_132 = ITOP.iow0.arr[33]; +wire [71:0] Q_133 = ITOP.iow1.arr[33]; +wire [71:0] Q_134 = ITOP.iow2.arr[33]; +wire [71:0] Q_135 = ITOP.iow3.arr[33]; +wire [71:0] Q_136 = ITOP.iow0.arr[34]; +wire [71:0] Q_137 = ITOP.iow1.arr[34]; +wire [71:0] Q_138 = ITOP.iow2.arr[34]; +wire [71:0] Q_139 = ITOP.iow3.arr[34]; +wire [71:0] Q_140 = ITOP.iow0.arr[35]; +wire [71:0] Q_141 = ITOP.iow1.arr[35]; +wire [71:0] Q_142 = ITOP.iow2.arr[35]; +wire [71:0] Q_143 = ITOP.iow3.arr[35]; +wire [71:0] Q_144 = ITOP.iow0.arr[36]; +wire [71:0] Q_145 = ITOP.iow1.arr[36]; +wire [71:0] Q_146 = ITOP.iow2.arr[36]; +wire [71:0] Q_147 = ITOP.iow3.arr[36]; +wire [71:0] Q_148 = ITOP.iow0.arr[37]; +wire [71:0] Q_149 = ITOP.iow1.arr[37]; +wire [71:0] Q_150 = ITOP.iow2.arr[37]; +wire [71:0] Q_151 = ITOP.iow3.arr[37]; +wire [71:0] Q_152 = ITOP.iow0.arr[38]; +wire [71:0] Q_153 = ITOP.iow1.arr[38]; +wire [71:0] Q_154 = ITOP.iow2.arr[38]; +wire [71:0] Q_155 = ITOP.iow3.arr[38]; +wire [71:0] Q_156 = ITOP.iow0.arr[39]; +wire [71:0] Q_157 = ITOP.iow1.arr[39]; +wire [71:0] Q_158 = ITOP.iow2.arr[39]; +wire [71:0] Q_159 = ITOP.iow3.arr[39]; +wire [71:0] Q_160 = ITOP.iow0.arr[40]; +wire [71:0] Q_161 = ITOP.iow1.arr[40]; +wire [71:0] Q_162 = ITOP.iow2.arr[40]; +wire [71:0] Q_163 = ITOP.iow3.arr[40]; +wire [71:0] Q_164 = ITOP.iow0.arr[41]; +wire [71:0] Q_165 = ITOP.iow1.arr[41]; +wire [71:0] Q_166 = ITOP.iow2.arr[41]; +wire [71:0] Q_167 = ITOP.iow3.arr[41]; +wire [71:0] Q_168 = ITOP.iow0.arr[42]; +wire [71:0] Q_169 = ITOP.iow1.arr[42]; +wire [71:0] Q_170 = ITOP.iow2.arr[42]; +wire [71:0] Q_171 = ITOP.iow3.arr[42]; +wire [71:0] Q_172 = ITOP.iow0.arr[43]; +wire [71:0] Q_173 = ITOP.iow1.arr[43]; +wire [71:0] Q_174 = ITOP.iow2.arr[43]; +wire [71:0] Q_175 = ITOP.iow3.arr[43]; +wire [71:0] Q_176 = ITOP.iow0.arr[44]; +wire [71:0] Q_177 = ITOP.iow1.arr[44]; +wire [71:0] Q_178 = ITOP.iow2.arr[44]; +wire [71:0] Q_179 = ITOP.iow3.arr[44]; +wire [71:0] Q_180 = ITOP.iow0.arr[45]; +wire [71:0] Q_181 = ITOP.iow1.arr[45]; +wire [71:0] Q_182 = ITOP.iow2.arr[45]; +wire [71:0] Q_183 = ITOP.iow3.arr[45]; +wire [71:0] Q_184 = ITOP.iow0.arr[46]; +wire [71:0] Q_185 = ITOP.iow1.arr[46]; +wire [71:0] Q_186 = ITOP.iow2.arr[46]; +wire [71:0] Q_187 = ITOP.iow3.arr[46]; +wire [71:0] Q_188 = ITOP.iow0.arr[47]; +wire [71:0] Q_189 = ITOP.iow1.arr[47]; +wire [71:0] Q_190 = ITOP.iow2.arr[47]; +wire [71:0] Q_191 = ITOP.iow3.arr[47]; +wire [71:0] Q_192 = ITOP.iow0.arr[48]; +wire [71:0] Q_193 = ITOP.iow1.arr[48]; +wire [71:0] Q_194 = ITOP.iow2.arr[48]; +wire [71:0] Q_195 = ITOP.iow3.arr[48]; +wire [71:0] Q_196 = ITOP.iow0.arr[49]; +wire [71:0] Q_197 = ITOP.iow1.arr[49]; +wire [71:0] Q_198 = ITOP.iow2.arr[49]; +wire [71:0] Q_199 = ITOP.iow3.arr[49]; +wire [71:0] Q_200 = ITOP.iow0.arr[50]; +wire [71:0] Q_201 = ITOP.iow1.arr[50]; +wire [71:0] Q_202 = ITOP.iow2.arr[50]; +wire [71:0] Q_203 = ITOP.iow3.arr[50]; +wire [71:0] Q_204 = ITOP.iow0.arr[51]; +wire [71:0] Q_205 = ITOP.iow1.arr[51]; +wire [71:0] Q_206 = ITOP.iow2.arr[51]; +wire [71:0] Q_207 = ITOP.iow3.arr[51]; +wire [71:0] Q_208 = ITOP.iow0.arr[52]; +wire [71:0] Q_209 = ITOP.iow1.arr[52]; +wire [71:0] Q_210 = ITOP.iow2.arr[52]; +wire [71:0] Q_211 = ITOP.iow3.arr[52]; +wire [71:0] Q_212 = ITOP.iow0.arr[53]; +wire [71:0] Q_213 = ITOP.iow1.arr[53]; +wire [71:0] Q_214 = ITOP.iow2.arr[53]; +wire [71:0] Q_215 = ITOP.iow3.arr[53]; +wire [71:0] Q_216 = ITOP.iow0.arr[54]; +wire [71:0] Q_217 = ITOP.iow1.arr[54]; +wire [71:0] Q_218 = ITOP.iow2.arr[54]; +wire [71:0] Q_219 = ITOP.iow3.arr[54]; +wire [71:0] Q_220 = ITOP.iow0.arr[55]; +wire [71:0] Q_221 = ITOP.iow1.arr[55]; +wire [71:0] Q_222 = ITOP.iow2.arr[55]; +wire [71:0] Q_223 = ITOP.iow3.arr[55]; +wire [71:0] Q_224 = ITOP.iow0.arr[56]; +wire [71:0] Q_225 = ITOP.iow1.arr[56]; +wire [71:0] Q_226 = ITOP.iow2.arr[56]; +wire [71:0] Q_227 = ITOP.iow3.arr[56]; +wire [71:0] Q_228 = ITOP.iow0.arr[57]; +wire [71:0] Q_229 = ITOP.iow1.arr[57]; +wire [71:0] Q_230 = ITOP.iow2.arr[57]; +wire [71:0] Q_231 = ITOP.iow3.arr[57]; +wire [71:0] Q_232 = ITOP.iow0.arr[58]; +wire [71:0] Q_233 = ITOP.iow1.arr[58]; +wire [71:0] Q_234 = ITOP.iow2.arr[58]; +wire [71:0] Q_235 = ITOP.iow3.arr[58]; +wire [71:0] Q_236 = ITOP.iow0.arr[59]; +wire [71:0] Q_237 = ITOP.iow1.arr[59]; +wire [71:0] Q_238 = ITOP.iow2.arr[59]; +wire [71:0] Q_239 = ITOP.iow3.arr[59]; +wire [71:0] Q_240 = ITOP.iow0.arr[60]; +wire [71:0] Q_241 = ITOP.iow1.arr[60]; +wire [71:0] Q_242 = ITOP.iow2.arr[60]; +wire [71:0] Q_243 = ITOP.iow3.arr[60]; +wire [71:0] Q_244 = ITOP.iow0.arr[61]; +wire [71:0] Q_245 = ITOP.iow1.arr[61]; +wire [71:0] Q_246 = ITOP.iow2.arr[61]; +wire [71:0] Q_247 = ITOP.iow3.arr[61]; +wire [71:0] Q_248 = ITOP.iow0.arr[62]; +wire [71:0] Q_249 = ITOP.iow1.arr[62]; +wire [71:0] Q_250 = ITOP.iow2.arr[62]; +wire [71:0] Q_251 = ITOP.iow3.arr[62]; +wire [71:0] Q_252 = ITOP.iow0.arr[63]; +wire [71:0] Q_253 = ITOP.iow1.arr[63]; +wire [71:0] Q_254 = ITOP.iow2.arr[63]; +wire [71:0] Q_255 = ITOP.iow3.arr[63]; +wire [71:0] Q_256 = ITOP.iow0.arr[64]; +wire [71:0] Q_257 = ITOP.iow1.arr[64]; +wire [71:0] Q_258 = ITOP.iow2.arr[64]; +wire [71:0] Q_259 = ITOP.iow3.arr[64]; +wire [71:0] Q_260 = ITOP.iow0.arr[65]; +wire [71:0] Q_261 = ITOP.iow1.arr[65]; +wire [71:0] Q_262 = ITOP.iow2.arr[65]; +wire [71:0] Q_263 = ITOP.iow3.arr[65]; +wire [71:0] Q_264 = ITOP.iow0.arr[66]; +wire [71:0] Q_265 = ITOP.iow1.arr[66]; +wire [71:0] Q_266 = ITOP.iow2.arr[66]; +wire [71:0] Q_267 = ITOP.iow3.arr[66]; +wire [71:0] Q_268 = ITOP.iow0.arr[67]; +wire [71:0] Q_269 = ITOP.iow1.arr[67]; +wire [71:0] Q_270 = ITOP.iow2.arr[67]; +wire [71:0] Q_271 = ITOP.iow3.arr[67]; +wire [71:0] Q_272 = ITOP.iow0.arr[68]; +wire [71:0] Q_273 = ITOP.iow1.arr[68]; +wire [71:0] Q_274 = ITOP.iow2.arr[68]; +wire [71:0] Q_275 = ITOP.iow3.arr[68]; +wire [71:0] Q_276 = ITOP.iow0.arr[69]; +wire [71:0] Q_277 = ITOP.iow1.arr[69]; +wire [71:0] Q_278 = ITOP.iow2.arr[69]; +wire [71:0] Q_279 = ITOP.iow3.arr[69]; +wire [71:0] Q_280 = ITOP.iow0.arr[70]; +wire [71:0] Q_281 = ITOP.iow1.arr[70]; +wire [71:0] Q_282 = ITOP.iow2.arr[70]; +wire [71:0] Q_283 = ITOP.iow3.arr[70]; +wire [71:0] Q_284 = ITOP.iow0.arr[71]; +wire [71:0] Q_285 = ITOP.iow1.arr[71]; +wire [71:0] Q_286 = ITOP.iow2.arr[71]; +wire [71:0] Q_287 = ITOP.iow3.arr[71]; +wire [71:0] Q_288 = ITOP.iow0.arr[72]; +wire [71:0] Q_289 = ITOP.iow1.arr[72]; +wire [71:0] Q_290 = ITOP.iow2.arr[72]; +wire [71:0] Q_291 = ITOP.iow3.arr[72]; +wire [71:0] Q_292 = ITOP.iow0.arr[73]; +wire [71:0] Q_293 = ITOP.iow1.arr[73]; +wire [71:0] Q_294 = ITOP.iow2.arr[73]; +wire [71:0] Q_295 = ITOP.iow3.arr[73]; +wire [71:0] Q_296 = ITOP.iow0.arr[74]; +wire [71:0] Q_297 = ITOP.iow1.arr[74]; +wire [71:0] Q_298 = ITOP.iow2.arr[74]; +wire [71:0] Q_299 = ITOP.iow3.arr[74]; +wire [71:0] Q_300 = ITOP.iow0.arr[75]; +wire [71:0] Q_301 = ITOP.iow1.arr[75]; +wire [71:0] Q_302 = ITOP.iow2.arr[75]; +wire [71:0] Q_303 = ITOP.iow3.arr[75]; +wire [71:0] Q_304 = ITOP.iow0.arr[76]; +wire [71:0] Q_305 = ITOP.iow1.arr[76]; +wire [71:0] Q_306 = ITOP.iow2.arr[76]; +wire [71:0] Q_307 = ITOP.iow3.arr[76]; +wire [71:0] Q_308 = ITOP.iow0.arr[77]; +wire [71:0] Q_309 = ITOP.iow1.arr[77]; +wire [71:0] Q_310 = ITOP.iow2.arr[77]; +wire [71:0] Q_311 = ITOP.iow3.arr[77]; +wire [71:0] Q_312 = ITOP.iow0.arr[78]; +wire [71:0] Q_313 = ITOP.iow1.arr[78]; +wire [71:0] Q_314 = ITOP.iow2.arr[78]; +wire [71:0] Q_315 = ITOP.iow3.arr[78]; +wire [71:0] Q_316 = ITOP.iow0.arr[79]; +wire [71:0] Q_317 = ITOP.iow1.arr[79]; +wire [71:0] Q_318 = ITOP.iow2.arr[79]; +wire [71:0] Q_319 = ITOP.iow3.arr[79]; +wire [71:0] Q_320 = ITOP.iow0.arr[80]; +wire [71:0] Q_321 = ITOP.iow1.arr[80]; +wire [71:0] Q_322 = ITOP.iow2.arr[80]; +wire [71:0] Q_323 = ITOP.iow3.arr[80]; +wire [71:0] Q_324 = ITOP.iow0.arr[81]; +wire [71:0] Q_325 = ITOP.iow1.arr[81]; +wire [71:0] Q_326 = ITOP.iow2.arr[81]; +wire [71:0] Q_327 = ITOP.iow3.arr[81]; +wire [71:0] Q_328 = ITOP.iow0.arr[82]; +wire [71:0] Q_329 = ITOP.iow1.arr[82]; +wire [71:0] Q_330 = ITOP.iow2.arr[82]; +wire [71:0] Q_331 = ITOP.iow3.arr[82]; +wire [71:0] Q_332 = ITOP.iow0.arr[83]; +wire [71:0] Q_333 = ITOP.iow1.arr[83]; +wire [71:0] Q_334 = ITOP.iow2.arr[83]; +wire [71:0] Q_335 = ITOP.iow3.arr[83]; +wire [71:0] Q_336 = ITOP.iow0.arr[84]; +wire [71:0] Q_337 = ITOP.iow1.arr[84]; +wire [71:0] Q_338 = ITOP.iow2.arr[84]; +wire [71:0] Q_339 = ITOP.iow3.arr[84]; +wire [71:0] Q_340 = ITOP.iow0.arr[85]; +wire [71:0] Q_341 = ITOP.iow1.arr[85]; +wire [71:0] Q_342 = ITOP.iow2.arr[85]; +wire [71:0] Q_343 = ITOP.iow3.arr[85]; +wire [71:0] Q_344 = ITOP.iow0.arr[86]; +wire [71:0] Q_345 = ITOP.iow1.arr[86]; +wire [71:0] Q_346 = ITOP.iow2.arr[86]; +wire [71:0] Q_347 = ITOP.iow3.arr[86]; +wire [71:0] Q_348 = ITOP.iow0.arr[87]; +wire [71:0] Q_349 = ITOP.iow1.arr[87]; +wire [71:0] Q_350 = ITOP.iow2.arr[87]; +wire [71:0] Q_351 = ITOP.iow3.arr[87]; +wire [71:0] Q_352 = ITOP.iow0.arr[88]; +wire [71:0] Q_353 = ITOP.iow1.arr[88]; +wire [71:0] Q_354 = ITOP.iow2.arr[88]; +wire [71:0] Q_355 = ITOP.iow3.arr[88]; +wire [71:0] Q_356 = ITOP.iow0.arr[89]; +wire [71:0] Q_357 = ITOP.iow1.arr[89]; +wire [71:0] Q_358 = ITOP.iow2.arr[89]; +wire [71:0] Q_359 = ITOP.iow3.arr[89]; +wire [71:0] Q_360 = ITOP.iow0.arr[90]; +wire [71:0] Q_361 = ITOP.iow1.arr[90]; +wire [71:0] Q_362 = ITOP.iow2.arr[90]; +wire [71:0] Q_363 = ITOP.iow3.arr[90]; +wire [71:0] Q_364 = ITOP.iow0.arr[91]; +wire [71:0] Q_365 = ITOP.iow1.arr[91]; +wire [71:0] Q_366 = ITOP.iow2.arr[91]; +wire [71:0] Q_367 = ITOP.iow3.arr[91]; +wire [71:0] Q_368 = ITOP.iow0.arr[92]; +wire [71:0] Q_369 = ITOP.iow1.arr[92]; +wire [71:0] Q_370 = ITOP.iow2.arr[92]; +wire [71:0] Q_371 = ITOP.iow3.arr[92]; +wire [71:0] Q_372 = ITOP.iow0.arr[93]; +wire [71:0] Q_373 = ITOP.iow1.arr[93]; +wire [71:0] Q_374 = ITOP.iow2.arr[93]; +wire [71:0] Q_375 = ITOP.iow3.arr[93]; +wire [71:0] Q_376 = ITOP.iow0.arr[94]; +wire [71:0] Q_377 = ITOP.iow1.arr[94]; +wire [71:0] Q_378 = ITOP.iow2.arr[94]; +wire [71:0] Q_379 = ITOP.iow3.arr[94]; +wire [71:0] Q_380 = ITOP.iow0.arr[95]; +wire [71:0] Q_381 = ITOP.iow1.arr[95]; +wire [71:0] Q_382 = ITOP.iow2.arr[95]; +wire [71:0] Q_383 = ITOP.iow3.arr[95]; +wire [71:0] Q_384 = ITOP.iow0.arr[96]; +wire [71:0] Q_385 = ITOP.iow1.arr[96]; +wire [71:0] Q_386 = ITOP.iow2.arr[96]; +wire [71:0] Q_387 = ITOP.iow3.arr[96]; +wire [71:0] Q_388 = ITOP.iow0.arr[97]; +wire [71:0] Q_389 = ITOP.iow1.arr[97]; +wire [71:0] Q_390 = ITOP.iow2.arr[97]; +wire [71:0] Q_391 = ITOP.iow3.arr[97]; +wire [71:0] Q_392 = ITOP.iow0.arr[98]; +wire [71:0] Q_393 = ITOP.iow1.arr[98]; +wire [71:0] Q_394 = ITOP.iow2.arr[98]; +wire [71:0] Q_395 = ITOP.iow3.arr[98]; +wire [71:0] Q_396 = ITOP.iow0.arr[99]; +wire [71:0] Q_397 = ITOP.iow1.arr[99]; +wire [71:0] Q_398 = ITOP.iow2.arr[99]; +wire [71:0] Q_399 = ITOP.iow3.arr[99]; +wire [71:0] Q_400 = ITOP.iow0.arr[100]; +wire [71:0] Q_401 = ITOP.iow1.arr[100]; +wire [71:0] Q_402 = ITOP.iow2.arr[100]; +wire [71:0] Q_403 = ITOP.iow3.arr[100]; +wire [71:0] Q_404 = ITOP.iow0.arr[101]; +wire [71:0] Q_405 = ITOP.iow1.arr[101]; +wire [71:0] Q_406 = ITOP.iow2.arr[101]; +wire [71:0] Q_407 = ITOP.iow3.arr[101]; +wire [71:0] Q_408 = ITOP.iow0.arr[102]; +wire [71:0] Q_409 = ITOP.iow1.arr[102]; +wire [71:0] Q_410 = ITOP.iow2.arr[102]; +wire [71:0] Q_411 = ITOP.iow3.arr[102]; +wire [71:0] Q_412 = ITOP.iow0.arr[103]; +wire [71:0] Q_413 = ITOP.iow1.arr[103]; +wire [71:0] Q_414 = ITOP.iow2.arr[103]; +wire [71:0] Q_415 = ITOP.iow3.arr[103]; +wire [71:0] Q_416 = ITOP.iow0.arr[104]; +wire [71:0] Q_417 = ITOP.iow1.arr[104]; +wire [71:0] Q_418 = ITOP.iow2.arr[104]; +wire [71:0] Q_419 = ITOP.iow3.arr[104]; +wire [71:0] Q_420 = ITOP.iow0.arr[105]; +wire [71:0] Q_421 = ITOP.iow1.arr[105]; +wire [71:0] Q_422 = ITOP.iow2.arr[105]; +wire [71:0] Q_423 = ITOP.iow3.arr[105]; +wire [71:0] Q_424 = ITOP.iow0.arr[106]; +wire [71:0] Q_425 = ITOP.iow1.arr[106]; +wire [71:0] Q_426 = ITOP.iow2.arr[106]; +wire [71:0] Q_427 = ITOP.iow3.arr[106]; +wire [71:0] Q_428 = ITOP.iow0.arr[107]; +wire [71:0] Q_429 = ITOP.iow1.arr[107]; +wire [71:0] Q_430 = ITOP.iow2.arr[107]; +wire [71:0] Q_431 = ITOP.iow3.arr[107]; +wire [71:0] Q_432 = ITOP.iow0.arr[108]; +wire [71:0] Q_433 = ITOP.iow1.arr[108]; +wire [71:0] Q_434 = ITOP.iow2.arr[108]; +wire [71:0] Q_435 = ITOP.iow3.arr[108]; +wire [71:0] Q_436 = ITOP.iow0.arr[109]; +wire [71:0] Q_437 = ITOP.iow1.arr[109]; +wire [71:0] Q_438 = ITOP.iow2.arr[109]; +wire [71:0] Q_439 = ITOP.iow3.arr[109]; +wire [71:0] Q_440 = ITOP.iow0.arr[110]; +wire [71:0] Q_441 = ITOP.iow1.arr[110]; +wire [71:0] Q_442 = ITOP.iow2.arr[110]; +wire [71:0] Q_443 = ITOP.iow3.arr[110]; +wire [71:0] Q_444 = ITOP.iow0.arr[111]; +wire [71:0] Q_445 = ITOP.iow1.arr[111]; +wire [71:0] Q_446 = ITOP.iow2.arr[111]; +wire [71:0] Q_447 = ITOP.iow3.arr[111]; +wire [71:0] Q_448 = ITOP.iow0.arr[112]; +wire [71:0] Q_449 = ITOP.iow1.arr[112]; +wire [71:0] Q_450 = ITOP.iow2.arr[112]; +wire [71:0] Q_451 = ITOP.iow3.arr[112]; +wire [71:0] Q_452 = ITOP.iow0.arr[113]; +wire [71:0] Q_453 = ITOP.iow1.arr[113]; +wire [71:0] Q_454 = ITOP.iow2.arr[113]; +wire [71:0] Q_455 = ITOP.iow3.arr[113]; +wire [71:0] Q_456 = ITOP.iow0.arr[114]; +wire [71:0] Q_457 = ITOP.iow1.arr[114]; +wire [71:0] Q_458 = ITOP.iow2.arr[114]; +wire [71:0] Q_459 = ITOP.iow3.arr[114]; +wire [71:0] Q_460 = ITOP.iow0.arr[115]; +wire [71:0] Q_461 = ITOP.iow1.arr[115]; +wire [71:0] Q_462 = ITOP.iow2.arr[115]; +wire [71:0] Q_463 = ITOP.iow3.arr[115]; +wire [71:0] Q_464 = ITOP.iow0.arr[116]; +wire [71:0] Q_465 = ITOP.iow1.arr[116]; +wire [71:0] Q_466 = ITOP.iow2.arr[116]; +wire [71:0] Q_467 = ITOP.iow3.arr[116]; +wire [71:0] Q_468 = ITOP.iow0.arr[117]; +wire [71:0] Q_469 = ITOP.iow1.arr[117]; +wire [71:0] Q_470 = ITOP.iow2.arr[117]; +wire [71:0] Q_471 = ITOP.iow3.arr[117]; +wire [71:0] Q_472 = ITOP.iow0.arr[118]; +wire [71:0] Q_473 = ITOP.iow1.arr[118]; +wire [71:0] Q_474 = ITOP.iow2.arr[118]; +wire [71:0] Q_475 = ITOP.iow3.arr[118]; +wire [71:0] Q_476 = ITOP.iow0.arr[119]; +wire [71:0] Q_477 = ITOP.iow1.arr[119]; +wire [71:0] Q_478 = ITOP.iow2.arr[119]; +wire [71:0] Q_479 = ITOP.iow3.arr[119]; +wire [71:0] Q_480 = ITOP.iow0.arr[120]; +wire [71:0] Q_481 = ITOP.iow1.arr[120]; +wire [71:0] Q_482 = ITOP.iow2.arr[120]; +wire [71:0] Q_483 = ITOP.iow3.arr[120]; +wire [71:0] Q_484 = ITOP.iow0.arr[121]; +wire [71:0] Q_485 = ITOP.iow1.arr[121]; +wire [71:0] Q_486 = ITOP.iow2.arr[121]; +wire [71:0] Q_487 = ITOP.iow3.arr[121]; +wire [71:0] Q_488 = ITOP.iow0.arr[122]; +wire [71:0] Q_489 = ITOP.iow1.arr[122]; +wire [71:0] Q_490 = ITOP.iow2.arr[122]; +wire [71:0] Q_491 = ITOP.iow3.arr[122]; +wire [71:0] Q_492 = ITOP.iow0.arr[123]; +wire [71:0] Q_493 = ITOP.iow1.arr[123]; +wire [71:0] Q_494 = ITOP.iow2.arr[123]; +wire [71:0] Q_495 = ITOP.iow3.arr[123]; +wire [71:0] Q_496 = ITOP.iow0.arr[124]; +wire [71:0] Q_497 = ITOP.iow1.arr[124]; +wire [71:0] Q_498 = ITOP.iow2.arr[124]; +wire [71:0] Q_499 = ITOP.iow3.arr[124]; +wire [71:0] Q_500 = ITOP.iow0.arr[125]; +wire [71:0] Q_501 = ITOP.iow1.arr[125]; +wire [71:0] Q_502 = ITOP.iow2.arr[125]; +wire [71:0] Q_503 = ITOP.iow3.arr[125]; +wire [71:0] Q_504 = ITOP.iow0.arr[126]; +wire [71:0] Q_505 = ITOP.iow1.arr[126]; +wire [71:0] Q_506 = ITOP.iow2.arr[126]; +wire [71:0] Q_507 = ITOP.iow3.arr[126]; +wire [71:0] Q_508 = ITOP.iow0.arr[127]; +wire [71:0] Q_509 = ITOP.iow1.arr[127]; +wire [71:0] Q_510 = ITOP.iow2.arr[127]; +wire [71:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [71:0] WD_FF; + reg [71:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [71:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [71:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [71:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X72_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [71:0] WD; +input [8:0] RA, WA; +output [71:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [71:0] WDQ; + wire [71:0] WDBQ; + wire [71:0] WMNexp; + wire [71:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [71:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {72{1'b0}}; + assign SHFT = {72{1'b1}}; + reg [71:0] WDQ_pr; + wire [71:0] WDBQ_pr; + assign WMNexp = {72{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[71:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [71:0] dout; + wire [71:0] RD; + wire RD_rdnt; + wire [71:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [71:0] RDBYPASS = {72{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [71:0] force_x; +`ifndef SYNTHESIS + assign force_x = {72{1'bx}}; +`else + assign force_x = {72{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [71:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [71:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {72{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {72{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {72{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {72{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {72{RdClk0}} & ~dout0; + assign rmuxd1 = {72{RdClk1}} & ~dout1; + assign rmuxd2 = {72{RdClk2}} & ~dout2; + assign rmuxd3 = {72{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[71:0] <= (rmuxd0[71:0] | rmuxd1[71:0] | rmuxd2[71:0] | rmuxd3[71:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [71:0] data; + reg [71:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [71:0] mem_read_bank; +input [8:0] addr; +reg [71:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X72_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 72; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [71:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [71:0] val; + integer i; + begin + val = {72{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [71:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 72'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 72'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 72'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 72'bx; + for (i=0; i<=71; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [71:0] wr[3:0]; + integer i; + begin + for (i=0; i<=71; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [71:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [71:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [71:0] Q_0 = ITOP.iow0.arr[0]; +wire [71:0] Q_1 = ITOP.iow1.arr[0]; +wire [71:0] Q_2 = ITOP.iow2.arr[0]; +wire [71:0] Q_3 = ITOP.iow3.arr[0]; +wire [71:0] Q_4 = ITOP.iow0.arr[1]; +wire [71:0] Q_5 = ITOP.iow1.arr[1]; +wire [71:0] Q_6 = ITOP.iow2.arr[1]; +wire [71:0] Q_7 = ITOP.iow3.arr[1]; +wire [71:0] Q_8 = ITOP.iow0.arr[2]; +wire [71:0] Q_9 = ITOP.iow1.arr[2]; +wire [71:0] Q_10 = ITOP.iow2.arr[2]; +wire [71:0] Q_11 = ITOP.iow3.arr[2]; +wire [71:0] Q_12 = ITOP.iow0.arr[3]; +wire [71:0] Q_13 = ITOP.iow1.arr[3]; +wire [71:0] Q_14 = ITOP.iow2.arr[3]; +wire [71:0] Q_15 = ITOP.iow3.arr[3]; +wire [71:0] Q_16 = ITOP.iow0.arr[4]; +wire [71:0] Q_17 = ITOP.iow1.arr[4]; +wire [71:0] Q_18 = ITOP.iow2.arr[4]; +wire [71:0] Q_19 = ITOP.iow3.arr[4]; +wire [71:0] Q_20 = ITOP.iow0.arr[5]; +wire [71:0] Q_21 = ITOP.iow1.arr[5]; +wire [71:0] Q_22 = ITOP.iow2.arr[5]; +wire [71:0] Q_23 = ITOP.iow3.arr[5]; +wire [71:0] Q_24 = ITOP.iow0.arr[6]; +wire [71:0] Q_25 = ITOP.iow1.arr[6]; +wire [71:0] Q_26 = ITOP.iow2.arr[6]; +wire [71:0] Q_27 = ITOP.iow3.arr[6]; +wire [71:0] Q_28 = ITOP.iow0.arr[7]; +wire [71:0] Q_29 = ITOP.iow1.arr[7]; +wire [71:0] Q_30 = ITOP.iow2.arr[7]; +wire [71:0] Q_31 = ITOP.iow3.arr[7]; +wire [71:0] Q_32 = ITOP.iow0.arr[8]; +wire [71:0] Q_33 = ITOP.iow1.arr[8]; +wire [71:0] Q_34 = ITOP.iow2.arr[8]; +wire [71:0] Q_35 = ITOP.iow3.arr[8]; +wire [71:0] Q_36 = ITOP.iow0.arr[9]; +wire [71:0] Q_37 = ITOP.iow1.arr[9]; +wire [71:0] Q_38 = ITOP.iow2.arr[9]; +wire [71:0] Q_39 = ITOP.iow3.arr[9]; +wire [71:0] Q_40 = ITOP.iow0.arr[10]; +wire [71:0] Q_41 = ITOP.iow1.arr[10]; +wire [71:0] Q_42 = ITOP.iow2.arr[10]; +wire [71:0] Q_43 = ITOP.iow3.arr[10]; +wire [71:0] Q_44 = ITOP.iow0.arr[11]; +wire [71:0] Q_45 = ITOP.iow1.arr[11]; +wire [71:0] Q_46 = ITOP.iow2.arr[11]; +wire [71:0] Q_47 = ITOP.iow3.arr[11]; +wire [71:0] Q_48 = ITOP.iow0.arr[12]; +wire [71:0] Q_49 = ITOP.iow1.arr[12]; +wire [71:0] Q_50 = ITOP.iow2.arr[12]; +wire [71:0] Q_51 = ITOP.iow3.arr[12]; +wire [71:0] Q_52 = ITOP.iow0.arr[13]; +wire [71:0] Q_53 = ITOP.iow1.arr[13]; +wire [71:0] Q_54 = ITOP.iow2.arr[13]; +wire [71:0] Q_55 = ITOP.iow3.arr[13]; +wire [71:0] Q_56 = ITOP.iow0.arr[14]; +wire [71:0] Q_57 = ITOP.iow1.arr[14]; +wire [71:0] Q_58 = ITOP.iow2.arr[14]; +wire [71:0] Q_59 = ITOP.iow3.arr[14]; +wire [71:0] Q_60 = ITOP.iow0.arr[15]; +wire [71:0] Q_61 = ITOP.iow1.arr[15]; +wire [71:0] Q_62 = ITOP.iow2.arr[15]; +wire [71:0] Q_63 = ITOP.iow3.arr[15]; +wire [71:0] Q_64 = ITOP.iow0.arr[16]; +wire [71:0] Q_65 = ITOP.iow1.arr[16]; +wire [71:0] Q_66 = ITOP.iow2.arr[16]; +wire [71:0] Q_67 = ITOP.iow3.arr[16]; +wire [71:0] Q_68 = ITOP.iow0.arr[17]; +wire [71:0] Q_69 = ITOP.iow1.arr[17]; +wire [71:0] Q_70 = ITOP.iow2.arr[17]; +wire [71:0] Q_71 = ITOP.iow3.arr[17]; +wire [71:0] Q_72 = ITOP.iow0.arr[18]; +wire [71:0] Q_73 = ITOP.iow1.arr[18]; +wire [71:0] Q_74 = ITOP.iow2.arr[18]; +wire [71:0] Q_75 = ITOP.iow3.arr[18]; +wire [71:0] Q_76 = ITOP.iow0.arr[19]; +wire [71:0] Q_77 = ITOP.iow1.arr[19]; +wire [71:0] Q_78 = ITOP.iow2.arr[19]; +wire [71:0] Q_79 = ITOP.iow3.arr[19]; +wire [71:0] Q_80 = ITOP.iow0.arr[20]; +wire [71:0] Q_81 = ITOP.iow1.arr[20]; +wire [71:0] Q_82 = ITOP.iow2.arr[20]; +wire [71:0] Q_83 = ITOP.iow3.arr[20]; +wire [71:0] Q_84 = ITOP.iow0.arr[21]; +wire [71:0] Q_85 = ITOP.iow1.arr[21]; +wire [71:0] Q_86 = ITOP.iow2.arr[21]; +wire [71:0] Q_87 = ITOP.iow3.arr[21]; +wire [71:0] Q_88 = ITOP.iow0.arr[22]; +wire [71:0] Q_89 = ITOP.iow1.arr[22]; +wire [71:0] Q_90 = ITOP.iow2.arr[22]; +wire [71:0] Q_91 = ITOP.iow3.arr[22]; +wire [71:0] Q_92 = ITOP.iow0.arr[23]; +wire [71:0] Q_93 = ITOP.iow1.arr[23]; +wire [71:0] Q_94 = ITOP.iow2.arr[23]; +wire [71:0] Q_95 = ITOP.iow3.arr[23]; +wire [71:0] Q_96 = ITOP.iow0.arr[24]; +wire [71:0] Q_97 = ITOP.iow1.arr[24]; +wire [71:0] Q_98 = ITOP.iow2.arr[24]; +wire [71:0] Q_99 = ITOP.iow3.arr[24]; +wire [71:0] Q_100 = ITOP.iow0.arr[25]; +wire [71:0] Q_101 = ITOP.iow1.arr[25]; +wire [71:0] Q_102 = ITOP.iow2.arr[25]; +wire [71:0] Q_103 = ITOP.iow3.arr[25]; +wire [71:0] Q_104 = ITOP.iow0.arr[26]; +wire [71:0] Q_105 = ITOP.iow1.arr[26]; +wire [71:0] Q_106 = ITOP.iow2.arr[26]; +wire [71:0] Q_107 = ITOP.iow3.arr[26]; +wire [71:0] Q_108 = ITOP.iow0.arr[27]; +wire [71:0] Q_109 = ITOP.iow1.arr[27]; +wire [71:0] Q_110 = ITOP.iow2.arr[27]; +wire [71:0] Q_111 = ITOP.iow3.arr[27]; +wire [71:0] Q_112 = ITOP.iow0.arr[28]; +wire [71:0] Q_113 = ITOP.iow1.arr[28]; +wire [71:0] Q_114 = ITOP.iow2.arr[28]; +wire [71:0] Q_115 = ITOP.iow3.arr[28]; +wire [71:0] Q_116 = ITOP.iow0.arr[29]; +wire [71:0] Q_117 = ITOP.iow1.arr[29]; +wire [71:0] Q_118 = ITOP.iow2.arr[29]; +wire [71:0] Q_119 = ITOP.iow3.arr[29]; +wire [71:0] Q_120 = ITOP.iow0.arr[30]; +wire [71:0] Q_121 = ITOP.iow1.arr[30]; +wire [71:0] Q_122 = ITOP.iow2.arr[30]; +wire [71:0] Q_123 = ITOP.iow3.arr[30]; +wire [71:0] Q_124 = ITOP.iow0.arr[31]; +wire [71:0] Q_125 = ITOP.iow1.arr[31]; +wire [71:0] Q_126 = ITOP.iow2.arr[31]; +wire [71:0] Q_127 = ITOP.iow3.arr[31]; +wire [71:0] Q_128 = ITOP.iow0.arr[32]; +wire [71:0] Q_129 = ITOP.iow1.arr[32]; +wire [71:0] Q_130 = ITOP.iow2.arr[32]; +wire [71:0] Q_131 = ITOP.iow3.arr[32]; +wire [71:0] Q_132 = ITOP.iow0.arr[33]; +wire [71:0] Q_133 = ITOP.iow1.arr[33]; +wire [71:0] Q_134 = ITOP.iow2.arr[33]; +wire [71:0] Q_135 = ITOP.iow3.arr[33]; +wire [71:0] Q_136 = ITOP.iow0.arr[34]; +wire [71:0] Q_137 = ITOP.iow1.arr[34]; +wire [71:0] Q_138 = ITOP.iow2.arr[34]; +wire [71:0] Q_139 = ITOP.iow3.arr[34]; +wire [71:0] Q_140 = ITOP.iow0.arr[35]; +wire [71:0] Q_141 = ITOP.iow1.arr[35]; +wire [71:0] Q_142 = ITOP.iow2.arr[35]; +wire [71:0] Q_143 = ITOP.iow3.arr[35]; +wire [71:0] Q_144 = ITOP.iow0.arr[36]; +wire [71:0] Q_145 = ITOP.iow1.arr[36]; +wire [71:0] Q_146 = ITOP.iow2.arr[36]; +wire [71:0] Q_147 = ITOP.iow3.arr[36]; +wire [71:0] Q_148 = ITOP.iow0.arr[37]; +wire [71:0] Q_149 = ITOP.iow1.arr[37]; +wire [71:0] Q_150 = ITOP.iow2.arr[37]; +wire [71:0] Q_151 = ITOP.iow3.arr[37]; +wire [71:0] Q_152 = ITOP.iow0.arr[38]; +wire [71:0] Q_153 = ITOP.iow1.arr[38]; +wire [71:0] Q_154 = ITOP.iow2.arr[38]; +wire [71:0] Q_155 = ITOP.iow3.arr[38]; +wire [71:0] Q_156 = ITOP.iow0.arr[39]; +wire [71:0] Q_157 = ITOP.iow1.arr[39]; +wire [71:0] Q_158 = ITOP.iow2.arr[39]; +wire [71:0] Q_159 = ITOP.iow3.arr[39]; +wire [71:0] Q_160 = ITOP.iow0.arr[40]; +wire [71:0] Q_161 = ITOP.iow1.arr[40]; +wire [71:0] Q_162 = ITOP.iow2.arr[40]; +wire [71:0] Q_163 = ITOP.iow3.arr[40]; +wire [71:0] Q_164 = ITOP.iow0.arr[41]; +wire [71:0] Q_165 = ITOP.iow1.arr[41]; +wire [71:0] Q_166 = ITOP.iow2.arr[41]; +wire [71:0] Q_167 = ITOP.iow3.arr[41]; +wire [71:0] Q_168 = ITOP.iow0.arr[42]; +wire [71:0] Q_169 = ITOP.iow1.arr[42]; +wire [71:0] Q_170 = ITOP.iow2.arr[42]; +wire [71:0] Q_171 = ITOP.iow3.arr[42]; +wire [71:0] Q_172 = ITOP.iow0.arr[43]; +wire [71:0] Q_173 = ITOP.iow1.arr[43]; +wire [71:0] Q_174 = ITOP.iow2.arr[43]; +wire [71:0] Q_175 = ITOP.iow3.arr[43]; +wire [71:0] Q_176 = ITOP.iow0.arr[44]; +wire [71:0] Q_177 = ITOP.iow1.arr[44]; +wire [71:0] Q_178 = ITOP.iow2.arr[44]; +wire [71:0] Q_179 = ITOP.iow3.arr[44]; +wire [71:0] Q_180 = ITOP.iow0.arr[45]; +wire [71:0] Q_181 = ITOP.iow1.arr[45]; +wire [71:0] Q_182 = ITOP.iow2.arr[45]; +wire [71:0] Q_183 = ITOP.iow3.arr[45]; +wire [71:0] Q_184 = ITOP.iow0.arr[46]; +wire [71:0] Q_185 = ITOP.iow1.arr[46]; +wire [71:0] Q_186 = ITOP.iow2.arr[46]; +wire [71:0] Q_187 = ITOP.iow3.arr[46]; +wire [71:0] Q_188 = ITOP.iow0.arr[47]; +wire [71:0] Q_189 = ITOP.iow1.arr[47]; +wire [71:0] Q_190 = ITOP.iow2.arr[47]; +wire [71:0] Q_191 = ITOP.iow3.arr[47]; +wire [71:0] Q_192 = ITOP.iow0.arr[48]; +wire [71:0] Q_193 = ITOP.iow1.arr[48]; +wire [71:0] Q_194 = ITOP.iow2.arr[48]; +wire [71:0] Q_195 = ITOP.iow3.arr[48]; +wire [71:0] Q_196 = ITOP.iow0.arr[49]; +wire [71:0] Q_197 = ITOP.iow1.arr[49]; +wire [71:0] Q_198 = ITOP.iow2.arr[49]; +wire [71:0] Q_199 = ITOP.iow3.arr[49]; +wire [71:0] Q_200 = ITOP.iow0.arr[50]; +wire [71:0] Q_201 = ITOP.iow1.arr[50]; +wire [71:0] Q_202 = ITOP.iow2.arr[50]; +wire [71:0] Q_203 = ITOP.iow3.arr[50]; +wire [71:0] Q_204 = ITOP.iow0.arr[51]; +wire [71:0] Q_205 = ITOP.iow1.arr[51]; +wire [71:0] Q_206 = ITOP.iow2.arr[51]; +wire [71:0] Q_207 = ITOP.iow3.arr[51]; +wire [71:0] Q_208 = ITOP.iow0.arr[52]; +wire [71:0] Q_209 = ITOP.iow1.arr[52]; +wire [71:0] Q_210 = ITOP.iow2.arr[52]; +wire [71:0] Q_211 = ITOP.iow3.arr[52]; +wire [71:0] Q_212 = ITOP.iow0.arr[53]; +wire [71:0] Q_213 = ITOP.iow1.arr[53]; +wire [71:0] Q_214 = ITOP.iow2.arr[53]; +wire [71:0] Q_215 = ITOP.iow3.arr[53]; +wire [71:0] Q_216 = ITOP.iow0.arr[54]; +wire [71:0] Q_217 = ITOP.iow1.arr[54]; +wire [71:0] Q_218 = ITOP.iow2.arr[54]; +wire [71:0] Q_219 = ITOP.iow3.arr[54]; +wire [71:0] Q_220 = ITOP.iow0.arr[55]; +wire [71:0] Q_221 = ITOP.iow1.arr[55]; +wire [71:0] Q_222 = ITOP.iow2.arr[55]; +wire [71:0] Q_223 = ITOP.iow3.arr[55]; +wire [71:0] Q_224 = ITOP.iow0.arr[56]; +wire [71:0] Q_225 = ITOP.iow1.arr[56]; +wire [71:0] Q_226 = ITOP.iow2.arr[56]; +wire [71:0] Q_227 = ITOP.iow3.arr[56]; +wire [71:0] Q_228 = ITOP.iow0.arr[57]; +wire [71:0] Q_229 = ITOP.iow1.arr[57]; +wire [71:0] Q_230 = ITOP.iow2.arr[57]; +wire [71:0] Q_231 = ITOP.iow3.arr[57]; +wire [71:0] Q_232 = ITOP.iow0.arr[58]; +wire [71:0] Q_233 = ITOP.iow1.arr[58]; +wire [71:0] Q_234 = ITOP.iow2.arr[58]; +wire [71:0] Q_235 = ITOP.iow3.arr[58]; +wire [71:0] Q_236 = ITOP.iow0.arr[59]; +wire [71:0] Q_237 = ITOP.iow1.arr[59]; +wire [71:0] Q_238 = ITOP.iow2.arr[59]; +wire [71:0] Q_239 = ITOP.iow3.arr[59]; +wire [71:0] Q_240 = ITOP.iow0.arr[60]; +wire [71:0] Q_241 = ITOP.iow1.arr[60]; +wire [71:0] Q_242 = ITOP.iow2.arr[60]; +wire [71:0] Q_243 = ITOP.iow3.arr[60]; +wire [71:0] Q_244 = ITOP.iow0.arr[61]; +wire [71:0] Q_245 = ITOP.iow1.arr[61]; +wire [71:0] Q_246 = ITOP.iow2.arr[61]; +wire [71:0] Q_247 = ITOP.iow3.arr[61]; +wire [71:0] Q_248 = ITOP.iow0.arr[62]; +wire [71:0] Q_249 = ITOP.iow1.arr[62]; +wire [71:0] Q_250 = ITOP.iow2.arr[62]; +wire [71:0] Q_251 = ITOP.iow3.arr[62]; +wire [71:0] Q_252 = ITOP.iow0.arr[63]; +wire [71:0] Q_253 = ITOP.iow1.arr[63]; +wire [71:0] Q_254 = ITOP.iow2.arr[63]; +wire [71:0] Q_255 = ITOP.iow3.arr[63]; +wire [71:0] Q_256 = ITOP.iow0.arr[64]; +wire [71:0] Q_257 = ITOP.iow1.arr[64]; +wire [71:0] Q_258 = ITOP.iow2.arr[64]; +wire [71:0] Q_259 = ITOP.iow3.arr[64]; +wire [71:0] Q_260 = ITOP.iow0.arr[65]; +wire [71:0] Q_261 = ITOP.iow1.arr[65]; +wire [71:0] Q_262 = ITOP.iow2.arr[65]; +wire [71:0] Q_263 = ITOP.iow3.arr[65]; +wire [71:0] Q_264 = ITOP.iow0.arr[66]; +wire [71:0] Q_265 = ITOP.iow1.arr[66]; +wire [71:0] Q_266 = ITOP.iow2.arr[66]; +wire [71:0] Q_267 = ITOP.iow3.arr[66]; +wire [71:0] Q_268 = ITOP.iow0.arr[67]; +wire [71:0] Q_269 = ITOP.iow1.arr[67]; +wire [71:0] Q_270 = ITOP.iow2.arr[67]; +wire [71:0] Q_271 = ITOP.iow3.arr[67]; +wire [71:0] Q_272 = ITOP.iow0.arr[68]; +wire [71:0] Q_273 = ITOP.iow1.arr[68]; +wire [71:0] Q_274 = ITOP.iow2.arr[68]; +wire [71:0] Q_275 = ITOP.iow3.arr[68]; +wire [71:0] Q_276 = ITOP.iow0.arr[69]; +wire [71:0] Q_277 = ITOP.iow1.arr[69]; +wire [71:0] Q_278 = ITOP.iow2.arr[69]; +wire [71:0] Q_279 = ITOP.iow3.arr[69]; +wire [71:0] Q_280 = ITOP.iow0.arr[70]; +wire [71:0] Q_281 = ITOP.iow1.arr[70]; +wire [71:0] Q_282 = ITOP.iow2.arr[70]; +wire [71:0] Q_283 = ITOP.iow3.arr[70]; +wire [71:0] Q_284 = ITOP.iow0.arr[71]; +wire [71:0] Q_285 = ITOP.iow1.arr[71]; +wire [71:0] Q_286 = ITOP.iow2.arr[71]; +wire [71:0] Q_287 = ITOP.iow3.arr[71]; +wire [71:0] Q_288 = ITOP.iow0.arr[72]; +wire [71:0] Q_289 = ITOP.iow1.arr[72]; +wire [71:0] Q_290 = ITOP.iow2.arr[72]; +wire [71:0] Q_291 = ITOP.iow3.arr[72]; +wire [71:0] Q_292 = ITOP.iow0.arr[73]; +wire [71:0] Q_293 = ITOP.iow1.arr[73]; +wire [71:0] Q_294 = ITOP.iow2.arr[73]; +wire [71:0] Q_295 = ITOP.iow3.arr[73]; +wire [71:0] Q_296 = ITOP.iow0.arr[74]; +wire [71:0] Q_297 = ITOP.iow1.arr[74]; +wire [71:0] Q_298 = ITOP.iow2.arr[74]; +wire [71:0] Q_299 = ITOP.iow3.arr[74]; +wire [71:0] Q_300 = ITOP.iow0.arr[75]; +wire [71:0] Q_301 = ITOP.iow1.arr[75]; +wire [71:0] Q_302 = ITOP.iow2.arr[75]; +wire [71:0] Q_303 = ITOP.iow3.arr[75]; +wire [71:0] Q_304 = ITOP.iow0.arr[76]; +wire [71:0] Q_305 = ITOP.iow1.arr[76]; +wire [71:0] Q_306 = ITOP.iow2.arr[76]; +wire [71:0] Q_307 = ITOP.iow3.arr[76]; +wire [71:0] Q_308 = ITOP.iow0.arr[77]; +wire [71:0] Q_309 = ITOP.iow1.arr[77]; +wire [71:0] Q_310 = ITOP.iow2.arr[77]; +wire [71:0] Q_311 = ITOP.iow3.arr[77]; +wire [71:0] Q_312 = ITOP.iow0.arr[78]; +wire [71:0] Q_313 = ITOP.iow1.arr[78]; +wire [71:0] Q_314 = ITOP.iow2.arr[78]; +wire [71:0] Q_315 = ITOP.iow3.arr[78]; +wire [71:0] Q_316 = ITOP.iow0.arr[79]; +wire [71:0] Q_317 = ITOP.iow1.arr[79]; +wire [71:0] Q_318 = ITOP.iow2.arr[79]; +wire [71:0] Q_319 = ITOP.iow3.arr[79]; +wire [71:0] Q_320 = ITOP.iow0.arr[80]; +wire [71:0] Q_321 = ITOP.iow1.arr[80]; +wire [71:0] Q_322 = ITOP.iow2.arr[80]; +wire [71:0] Q_323 = ITOP.iow3.arr[80]; +wire [71:0] Q_324 = ITOP.iow0.arr[81]; +wire [71:0] Q_325 = ITOP.iow1.arr[81]; +wire [71:0] Q_326 = ITOP.iow2.arr[81]; +wire [71:0] Q_327 = ITOP.iow3.arr[81]; +wire [71:0] Q_328 = ITOP.iow0.arr[82]; +wire [71:0] Q_329 = ITOP.iow1.arr[82]; +wire [71:0] Q_330 = ITOP.iow2.arr[82]; +wire [71:0] Q_331 = ITOP.iow3.arr[82]; +wire [71:0] Q_332 = ITOP.iow0.arr[83]; +wire [71:0] Q_333 = ITOP.iow1.arr[83]; +wire [71:0] Q_334 = ITOP.iow2.arr[83]; +wire [71:0] Q_335 = ITOP.iow3.arr[83]; +wire [71:0] Q_336 = ITOP.iow0.arr[84]; +wire [71:0] Q_337 = ITOP.iow1.arr[84]; +wire [71:0] Q_338 = ITOP.iow2.arr[84]; +wire [71:0] Q_339 = ITOP.iow3.arr[84]; +wire [71:0] Q_340 = ITOP.iow0.arr[85]; +wire [71:0] Q_341 = ITOP.iow1.arr[85]; +wire [71:0] Q_342 = ITOP.iow2.arr[85]; +wire [71:0] Q_343 = ITOP.iow3.arr[85]; +wire [71:0] Q_344 = ITOP.iow0.arr[86]; +wire [71:0] Q_345 = ITOP.iow1.arr[86]; +wire [71:0] Q_346 = ITOP.iow2.arr[86]; +wire [71:0] Q_347 = ITOP.iow3.arr[86]; +wire [71:0] Q_348 = ITOP.iow0.arr[87]; +wire [71:0] Q_349 = ITOP.iow1.arr[87]; +wire [71:0] Q_350 = ITOP.iow2.arr[87]; +wire [71:0] Q_351 = ITOP.iow3.arr[87]; +wire [71:0] Q_352 = ITOP.iow0.arr[88]; +wire [71:0] Q_353 = ITOP.iow1.arr[88]; +wire [71:0] Q_354 = ITOP.iow2.arr[88]; +wire [71:0] Q_355 = ITOP.iow3.arr[88]; +wire [71:0] Q_356 = ITOP.iow0.arr[89]; +wire [71:0] Q_357 = ITOP.iow1.arr[89]; +wire [71:0] Q_358 = ITOP.iow2.arr[89]; +wire [71:0] Q_359 = ITOP.iow3.arr[89]; +wire [71:0] Q_360 = ITOP.iow0.arr[90]; +wire [71:0] Q_361 = ITOP.iow1.arr[90]; +wire [71:0] Q_362 = ITOP.iow2.arr[90]; +wire [71:0] Q_363 = ITOP.iow3.arr[90]; +wire [71:0] Q_364 = ITOP.iow0.arr[91]; +wire [71:0] Q_365 = ITOP.iow1.arr[91]; +wire [71:0] Q_366 = ITOP.iow2.arr[91]; +wire [71:0] Q_367 = ITOP.iow3.arr[91]; +wire [71:0] Q_368 = ITOP.iow0.arr[92]; +wire [71:0] Q_369 = ITOP.iow1.arr[92]; +wire [71:0] Q_370 = ITOP.iow2.arr[92]; +wire [71:0] Q_371 = ITOP.iow3.arr[92]; +wire [71:0] Q_372 = ITOP.iow0.arr[93]; +wire [71:0] Q_373 = ITOP.iow1.arr[93]; +wire [71:0] Q_374 = ITOP.iow2.arr[93]; +wire [71:0] Q_375 = ITOP.iow3.arr[93]; +wire [71:0] Q_376 = ITOP.iow0.arr[94]; +wire [71:0] Q_377 = ITOP.iow1.arr[94]; +wire [71:0] Q_378 = ITOP.iow2.arr[94]; +wire [71:0] Q_379 = ITOP.iow3.arr[94]; +wire [71:0] Q_380 = ITOP.iow0.arr[95]; +wire [71:0] Q_381 = ITOP.iow1.arr[95]; +wire [71:0] Q_382 = ITOP.iow2.arr[95]; +wire [71:0] Q_383 = ITOP.iow3.arr[95]; +wire [71:0] Q_384 = ITOP.iow0.arr[96]; +wire [71:0] Q_385 = ITOP.iow1.arr[96]; +wire [71:0] Q_386 = ITOP.iow2.arr[96]; +wire [71:0] Q_387 = ITOP.iow3.arr[96]; +wire [71:0] Q_388 = ITOP.iow0.arr[97]; +wire [71:0] Q_389 = ITOP.iow1.arr[97]; +wire [71:0] Q_390 = ITOP.iow2.arr[97]; +wire [71:0] Q_391 = ITOP.iow3.arr[97]; +wire [71:0] Q_392 = ITOP.iow0.arr[98]; +wire [71:0] Q_393 = ITOP.iow1.arr[98]; +wire [71:0] Q_394 = ITOP.iow2.arr[98]; +wire [71:0] Q_395 = ITOP.iow3.arr[98]; +wire [71:0] Q_396 = ITOP.iow0.arr[99]; +wire [71:0] Q_397 = ITOP.iow1.arr[99]; +wire [71:0] Q_398 = ITOP.iow2.arr[99]; +wire [71:0] Q_399 = ITOP.iow3.arr[99]; +wire [71:0] Q_400 = ITOP.iow0.arr[100]; +wire [71:0] Q_401 = ITOP.iow1.arr[100]; +wire [71:0] Q_402 = ITOP.iow2.arr[100]; +wire [71:0] Q_403 = ITOP.iow3.arr[100]; +wire [71:0] Q_404 = ITOP.iow0.arr[101]; +wire [71:0] Q_405 = ITOP.iow1.arr[101]; +wire [71:0] Q_406 = ITOP.iow2.arr[101]; +wire [71:0] Q_407 = ITOP.iow3.arr[101]; +wire [71:0] Q_408 = ITOP.iow0.arr[102]; +wire [71:0] Q_409 = ITOP.iow1.arr[102]; +wire [71:0] Q_410 = ITOP.iow2.arr[102]; +wire [71:0] Q_411 = ITOP.iow3.arr[102]; +wire [71:0] Q_412 = ITOP.iow0.arr[103]; +wire [71:0] Q_413 = ITOP.iow1.arr[103]; +wire [71:0] Q_414 = ITOP.iow2.arr[103]; +wire [71:0] Q_415 = ITOP.iow3.arr[103]; +wire [71:0] Q_416 = ITOP.iow0.arr[104]; +wire [71:0] Q_417 = ITOP.iow1.arr[104]; +wire [71:0] Q_418 = ITOP.iow2.arr[104]; +wire [71:0] Q_419 = ITOP.iow3.arr[104]; +wire [71:0] Q_420 = ITOP.iow0.arr[105]; +wire [71:0] Q_421 = ITOP.iow1.arr[105]; +wire [71:0] Q_422 = ITOP.iow2.arr[105]; +wire [71:0] Q_423 = ITOP.iow3.arr[105]; +wire [71:0] Q_424 = ITOP.iow0.arr[106]; +wire [71:0] Q_425 = ITOP.iow1.arr[106]; +wire [71:0] Q_426 = ITOP.iow2.arr[106]; +wire [71:0] Q_427 = ITOP.iow3.arr[106]; +wire [71:0] Q_428 = ITOP.iow0.arr[107]; +wire [71:0] Q_429 = ITOP.iow1.arr[107]; +wire [71:0] Q_430 = ITOP.iow2.arr[107]; +wire [71:0] Q_431 = ITOP.iow3.arr[107]; +wire [71:0] Q_432 = ITOP.iow0.arr[108]; +wire [71:0] Q_433 = ITOP.iow1.arr[108]; +wire [71:0] Q_434 = ITOP.iow2.arr[108]; +wire [71:0] Q_435 = ITOP.iow3.arr[108]; +wire [71:0] Q_436 = ITOP.iow0.arr[109]; +wire [71:0] Q_437 = ITOP.iow1.arr[109]; +wire [71:0] Q_438 = ITOP.iow2.arr[109]; +wire [71:0] Q_439 = ITOP.iow3.arr[109]; +wire [71:0] Q_440 = ITOP.iow0.arr[110]; +wire [71:0] Q_441 = ITOP.iow1.arr[110]; +wire [71:0] Q_442 = ITOP.iow2.arr[110]; +wire [71:0] Q_443 = ITOP.iow3.arr[110]; +wire [71:0] Q_444 = ITOP.iow0.arr[111]; +wire [71:0] Q_445 = ITOP.iow1.arr[111]; +wire [71:0] Q_446 = ITOP.iow2.arr[111]; +wire [71:0] Q_447 = ITOP.iow3.arr[111]; +wire [71:0] Q_448 = ITOP.iow0.arr[112]; +wire [71:0] Q_449 = ITOP.iow1.arr[112]; +wire [71:0] Q_450 = ITOP.iow2.arr[112]; +wire [71:0] Q_451 = ITOP.iow3.arr[112]; +wire [71:0] Q_452 = ITOP.iow0.arr[113]; +wire [71:0] Q_453 = ITOP.iow1.arr[113]; +wire [71:0] Q_454 = ITOP.iow2.arr[113]; +wire [71:0] Q_455 = ITOP.iow3.arr[113]; +wire [71:0] Q_456 = ITOP.iow0.arr[114]; +wire [71:0] Q_457 = ITOP.iow1.arr[114]; +wire [71:0] Q_458 = ITOP.iow2.arr[114]; +wire [71:0] Q_459 = ITOP.iow3.arr[114]; +wire [71:0] Q_460 = ITOP.iow0.arr[115]; +wire [71:0] Q_461 = ITOP.iow1.arr[115]; +wire [71:0] Q_462 = ITOP.iow2.arr[115]; +wire [71:0] Q_463 = ITOP.iow3.arr[115]; +wire [71:0] Q_464 = ITOP.iow0.arr[116]; +wire [71:0] Q_465 = ITOP.iow1.arr[116]; +wire [71:0] Q_466 = ITOP.iow2.arr[116]; +wire [71:0] Q_467 = ITOP.iow3.arr[116]; +wire [71:0] Q_468 = ITOP.iow0.arr[117]; +wire [71:0] Q_469 = ITOP.iow1.arr[117]; +wire [71:0] Q_470 = ITOP.iow2.arr[117]; +wire [71:0] Q_471 = ITOP.iow3.arr[117]; +wire [71:0] Q_472 = ITOP.iow0.arr[118]; +wire [71:0] Q_473 = ITOP.iow1.arr[118]; +wire [71:0] Q_474 = ITOP.iow2.arr[118]; +wire [71:0] Q_475 = ITOP.iow3.arr[118]; +wire [71:0] Q_476 = ITOP.iow0.arr[119]; +wire [71:0] Q_477 = ITOP.iow1.arr[119]; +wire [71:0] Q_478 = ITOP.iow2.arr[119]; +wire [71:0] Q_479 = ITOP.iow3.arr[119]; +wire [71:0] Q_480 = ITOP.iow0.arr[120]; +wire [71:0] Q_481 = ITOP.iow1.arr[120]; +wire [71:0] Q_482 = ITOP.iow2.arr[120]; +wire [71:0] Q_483 = ITOP.iow3.arr[120]; +wire [71:0] Q_484 = ITOP.iow0.arr[121]; +wire [71:0] Q_485 = ITOP.iow1.arr[121]; +wire [71:0] Q_486 = ITOP.iow2.arr[121]; +wire [71:0] Q_487 = ITOP.iow3.arr[121]; +wire [71:0] Q_488 = ITOP.iow0.arr[122]; +wire [71:0] Q_489 = ITOP.iow1.arr[122]; +wire [71:0] Q_490 = ITOP.iow2.arr[122]; +wire [71:0] Q_491 = ITOP.iow3.arr[122]; +wire [71:0] Q_492 = ITOP.iow0.arr[123]; +wire [71:0] Q_493 = ITOP.iow1.arr[123]; +wire [71:0] Q_494 = ITOP.iow2.arr[123]; +wire [71:0] Q_495 = ITOP.iow3.arr[123]; +wire [71:0] Q_496 = ITOP.iow0.arr[124]; +wire [71:0] Q_497 = ITOP.iow1.arr[124]; +wire [71:0] Q_498 = ITOP.iow2.arr[124]; +wire [71:0] Q_499 = ITOP.iow3.arr[124]; +wire [71:0] Q_500 = ITOP.iow0.arr[125]; +wire [71:0] Q_501 = ITOP.iow1.arr[125]; +wire [71:0] Q_502 = ITOP.iow2.arr[125]; +wire [71:0] Q_503 = ITOP.iow3.arr[125]; +wire [71:0] Q_504 = ITOP.iow0.arr[126]; +wire [71:0] Q_505 = ITOP.iow1.arr[126]; +wire [71:0] Q_506 = ITOP.iow2.arr[126]; +wire [71:0] Q_507 = ITOP.iow3.arr[126]; +wire [71:0] Q_508 = ITOP.iow0.arr[127]; +wire [71:0] Q_509 = ITOP.iow1.arr[127]; +wire [71:0] Q_510 = ITOP.iow2.arr[127]; +wire [71:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [71:0] WD_FF; + reg [71:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [71:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [71:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [71:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X72_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [71:0] WD; +input [8:0] RA, WA; +output [71:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [71:0] WDQ; + wire [71:0] WDBQ; + wire [71:0] WMNexp; + wire [71:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [71:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {72{1'b0}}; + assign SHFT = {72{1'b1}}; + reg [71:0] WDQ_pr; + wire [71:0] WDBQ_pr; + assign WMNexp = {72{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[71:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [71:0] dout; + wire [71:0] RD; + wire RD_rdnt; + wire [71:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [71:0] RDBYPASS = {72{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [71:0] force_x; +`ifndef SYNTHESIS + assign force_x = {72{1'bx}}; +`else + assign force_x = {72{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [71:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [71:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {72{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {72{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {72{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {72{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {72{RdClk0}} & ~dout0; + assign rmuxd1 = {72{RdClk1}} & ~dout1; + assign rmuxd2 = {72{RdClk2}} & ~dout2; + assign rmuxd3 = {72{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[71:0] <= (rmuxd0[71:0] | rmuxd1[71:0] | rmuxd2[71:0] | rmuxd3[71:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X72_GL_M4_D2_ram # (128, 72, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [71:0] data; + reg [71:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [71:0] mem_read_bank; +input [8:0] addr; +reg [71:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X72_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 72; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [7:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [7:0] val; + integer i; + begin + val = {8{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [7:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [8-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {8 {1'b1}} `else { $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {8 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [31:0] mem_phys_read_padr; +input [6:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [7:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=7; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [31:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [7:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=7; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [31:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [7:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 8'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 8'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 8'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 8'bx; + for (i=0; i<=7; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [31:0] data; + reg [7:0] wr[3:0]; + integer i; + begin + for (i=0; i<=7; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [31:0] mon_bit_w; +input [6:0] addr; + reg [31:0] mon_row; + reg [7:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=7; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [31:0] mon_bit_r; +input [6:0] addr; + reg [31:0] mon_row; + reg [7:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=7; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [31:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [7:0] Q_0 = ITOP.iow0.arr[0]; +wire [7:0] Q_1 = ITOP.iow1.arr[0]; +wire [7:0] Q_2 = ITOP.iow2.arr[0]; +wire [7:0] Q_3 = ITOP.iow3.arr[0]; +wire [7:0] Q_4 = ITOP.iow0.arr[1]; +wire [7:0] Q_5 = ITOP.iow1.arr[1]; +wire [7:0] Q_6 = ITOP.iow2.arr[1]; +wire [7:0] Q_7 = ITOP.iow3.arr[1]; +wire [7:0] Q_8 = ITOP.iow0.arr[2]; +wire [7:0] Q_9 = ITOP.iow1.arr[2]; +wire [7:0] Q_10 = ITOP.iow2.arr[2]; +wire [7:0] Q_11 = ITOP.iow3.arr[2]; +wire [7:0] Q_12 = ITOP.iow0.arr[3]; +wire [7:0] Q_13 = ITOP.iow1.arr[3]; +wire [7:0] Q_14 = ITOP.iow2.arr[3]; +wire [7:0] Q_15 = ITOP.iow3.arr[3]; +wire [7:0] Q_16 = ITOP.iow0.arr[4]; +wire [7:0] Q_17 = ITOP.iow1.arr[4]; +wire [7:0] Q_18 = ITOP.iow2.arr[4]; +wire [7:0] Q_19 = ITOP.iow3.arr[4]; +wire [7:0] Q_20 = ITOP.iow0.arr[5]; +wire [7:0] Q_21 = ITOP.iow1.arr[5]; +wire [7:0] Q_22 = ITOP.iow2.arr[5]; +wire [7:0] Q_23 = ITOP.iow3.arr[5]; +wire [7:0] Q_24 = ITOP.iow0.arr[6]; +wire [7:0] Q_25 = ITOP.iow1.arr[6]; +wire [7:0] Q_26 = ITOP.iow2.arr[6]; +wire [7:0] Q_27 = ITOP.iow3.arr[6]; +wire [7:0] Q_28 = ITOP.iow0.arr[7]; +wire [7:0] Q_29 = ITOP.iow1.arr[7]; +wire [7:0] Q_30 = ITOP.iow2.arr[7]; +wire [7:0] Q_31 = ITOP.iow3.arr[7]; +wire [7:0] Q_32 = ITOP.iow0.arr[8]; +wire [7:0] Q_33 = ITOP.iow1.arr[8]; +wire [7:0] Q_34 = ITOP.iow2.arr[8]; +wire [7:0] Q_35 = ITOP.iow3.arr[8]; +wire [7:0] Q_36 = ITOP.iow0.arr[9]; +wire [7:0] Q_37 = ITOP.iow1.arr[9]; +wire [7:0] Q_38 = ITOP.iow2.arr[9]; +wire [7:0] Q_39 = ITOP.iow3.arr[9]; +wire [7:0] Q_40 = ITOP.iow0.arr[10]; +wire [7:0] Q_41 = ITOP.iow1.arr[10]; +wire [7:0] Q_42 = ITOP.iow2.arr[10]; +wire [7:0] Q_43 = ITOP.iow3.arr[10]; +wire [7:0] Q_44 = ITOP.iow0.arr[11]; +wire [7:0] Q_45 = ITOP.iow1.arr[11]; +wire [7:0] Q_46 = ITOP.iow2.arr[11]; +wire [7:0] Q_47 = ITOP.iow3.arr[11]; +wire [7:0] Q_48 = ITOP.iow0.arr[12]; +wire [7:0] Q_49 = ITOP.iow1.arr[12]; +wire [7:0] Q_50 = ITOP.iow2.arr[12]; +wire [7:0] Q_51 = ITOP.iow3.arr[12]; +wire [7:0] Q_52 = ITOP.iow0.arr[13]; +wire [7:0] Q_53 = ITOP.iow1.arr[13]; +wire [7:0] Q_54 = ITOP.iow2.arr[13]; +wire [7:0] Q_55 = ITOP.iow3.arr[13]; +wire [7:0] Q_56 = ITOP.iow0.arr[14]; +wire [7:0] Q_57 = ITOP.iow1.arr[14]; +wire [7:0] Q_58 = ITOP.iow2.arr[14]; +wire [7:0] Q_59 = ITOP.iow3.arr[14]; +wire [7:0] Q_60 = ITOP.iow0.arr[15]; +wire [7:0] Q_61 = ITOP.iow1.arr[15]; +wire [7:0] Q_62 = ITOP.iow2.arr[15]; +wire [7:0] Q_63 = ITOP.iow3.arr[15]; +wire [7:0] Q_64 = ITOP.iow0.arr[16]; +wire [7:0] Q_65 = ITOP.iow1.arr[16]; +wire [7:0] Q_66 = ITOP.iow2.arr[16]; +wire [7:0] Q_67 = ITOP.iow3.arr[16]; +wire [7:0] Q_68 = ITOP.iow0.arr[17]; +wire [7:0] Q_69 = ITOP.iow1.arr[17]; +wire [7:0] Q_70 = ITOP.iow2.arr[17]; +wire [7:0] Q_71 = ITOP.iow3.arr[17]; +wire [7:0] Q_72 = ITOP.iow0.arr[18]; +wire [7:0] Q_73 = ITOP.iow1.arr[18]; +wire [7:0] Q_74 = ITOP.iow2.arr[18]; +wire [7:0] Q_75 = ITOP.iow3.arr[18]; +wire [7:0] Q_76 = ITOP.iow0.arr[19]; +wire [7:0] Q_77 = ITOP.iow1.arr[19]; +wire [7:0] Q_78 = ITOP.iow2.arr[19]; +wire [7:0] Q_79 = ITOP.iow3.arr[19]; +wire [7:0] Q_80 = ITOP.iow0.arr[20]; +wire [7:0] Q_81 = ITOP.iow1.arr[20]; +wire [7:0] Q_82 = ITOP.iow2.arr[20]; +wire [7:0] Q_83 = ITOP.iow3.arr[20]; +wire [7:0] Q_84 = ITOP.iow0.arr[21]; +wire [7:0] Q_85 = ITOP.iow1.arr[21]; +wire [7:0] Q_86 = ITOP.iow2.arr[21]; +wire [7:0] Q_87 = ITOP.iow3.arr[21]; +wire [7:0] Q_88 = ITOP.iow0.arr[22]; +wire [7:0] Q_89 = ITOP.iow1.arr[22]; +wire [7:0] Q_90 = ITOP.iow2.arr[22]; +wire [7:0] Q_91 = ITOP.iow3.arr[22]; +wire [7:0] Q_92 = ITOP.iow0.arr[23]; +wire [7:0] Q_93 = ITOP.iow1.arr[23]; +wire [7:0] Q_94 = ITOP.iow2.arr[23]; +wire [7:0] Q_95 = ITOP.iow3.arr[23]; +wire [7:0] Q_96 = ITOP.iow0.arr[24]; +wire [7:0] Q_97 = ITOP.iow1.arr[24]; +wire [7:0] Q_98 = ITOP.iow2.arr[24]; +wire [7:0] Q_99 = ITOP.iow3.arr[24]; +wire [7:0] Q_100 = ITOP.iow0.arr[25]; +wire [7:0] Q_101 = ITOP.iow1.arr[25]; +wire [7:0] Q_102 = ITOP.iow2.arr[25]; +wire [7:0] Q_103 = ITOP.iow3.arr[25]; +wire [7:0] Q_104 = ITOP.iow0.arr[26]; +wire [7:0] Q_105 = ITOP.iow1.arr[26]; +wire [7:0] Q_106 = ITOP.iow2.arr[26]; +wire [7:0] Q_107 = ITOP.iow3.arr[26]; +wire [7:0] Q_108 = ITOP.iow0.arr[27]; +wire [7:0] Q_109 = ITOP.iow1.arr[27]; +wire [7:0] Q_110 = ITOP.iow2.arr[27]; +wire [7:0] Q_111 = ITOP.iow3.arr[27]; +wire [7:0] Q_112 = ITOP.iow0.arr[28]; +wire [7:0] Q_113 = ITOP.iow1.arr[28]; +wire [7:0] Q_114 = ITOP.iow2.arr[28]; +wire [7:0] Q_115 = ITOP.iow3.arr[28]; +wire [7:0] Q_116 = ITOP.iow0.arr[29]; +wire [7:0] Q_117 = ITOP.iow1.arr[29]; +wire [7:0] Q_118 = ITOP.iow2.arr[29]; +wire [7:0] Q_119 = ITOP.iow3.arr[29]; +wire [7:0] Q_120 = ITOP.iow0.arr[30]; +wire [7:0] Q_121 = ITOP.iow1.arr[30]; +wire [7:0] Q_122 = ITOP.iow2.arr[30]; +wire [7:0] Q_123 = ITOP.iow3.arr[30]; +wire [7:0] Q_124 = ITOP.iow0.arr[31]; +wire [7:0] Q_125 = ITOP.iow1.arr[31]; +wire [7:0] Q_126 = ITOP.iow2.arr[31]; +wire [7:0] Q_127 = ITOP.iow3.arr[31]; +wire [7:0] Q_128 = ITOP.iow0.arr[32]; +wire [7:0] Q_129 = ITOP.iow1.arr[32]; +wire [7:0] Q_130 = ITOP.iow2.arr[32]; +wire [7:0] Q_131 = ITOP.iow3.arr[32]; +wire [7:0] Q_132 = ITOP.iow0.arr[33]; +wire [7:0] Q_133 = ITOP.iow1.arr[33]; +wire [7:0] Q_134 = ITOP.iow2.arr[33]; +wire [7:0] Q_135 = ITOP.iow3.arr[33]; +wire [7:0] Q_136 = ITOP.iow0.arr[34]; +wire [7:0] Q_137 = ITOP.iow1.arr[34]; +wire [7:0] Q_138 = ITOP.iow2.arr[34]; +wire [7:0] Q_139 = ITOP.iow3.arr[34]; +wire [7:0] Q_140 = ITOP.iow0.arr[35]; +wire [7:0] Q_141 = ITOP.iow1.arr[35]; +wire [7:0] Q_142 = ITOP.iow2.arr[35]; +wire [7:0] Q_143 = ITOP.iow3.arr[35]; +wire [7:0] Q_144 = ITOP.iow0.arr[36]; +wire [7:0] Q_145 = ITOP.iow1.arr[36]; +wire [7:0] Q_146 = ITOP.iow2.arr[36]; +wire [7:0] Q_147 = ITOP.iow3.arr[36]; +wire [7:0] Q_148 = ITOP.iow0.arr[37]; +wire [7:0] Q_149 = ITOP.iow1.arr[37]; +wire [7:0] Q_150 = ITOP.iow2.arr[37]; +wire [7:0] Q_151 = ITOP.iow3.arr[37]; +wire [7:0] Q_152 = ITOP.iow0.arr[38]; +wire [7:0] Q_153 = ITOP.iow1.arr[38]; +wire [7:0] Q_154 = ITOP.iow2.arr[38]; +wire [7:0] Q_155 = ITOP.iow3.arr[38]; +wire [7:0] Q_156 = ITOP.iow0.arr[39]; +wire [7:0] Q_157 = ITOP.iow1.arr[39]; +wire [7:0] Q_158 = ITOP.iow2.arr[39]; +wire [7:0] Q_159 = ITOP.iow3.arr[39]; +wire [7:0] Q_160 = ITOP.iow0.arr[40]; +wire [7:0] Q_161 = ITOP.iow1.arr[40]; +wire [7:0] Q_162 = ITOP.iow2.arr[40]; +wire [7:0] Q_163 = ITOP.iow3.arr[40]; +wire [7:0] Q_164 = ITOP.iow0.arr[41]; +wire [7:0] Q_165 = ITOP.iow1.arr[41]; +wire [7:0] Q_166 = ITOP.iow2.arr[41]; +wire [7:0] Q_167 = ITOP.iow3.arr[41]; +wire [7:0] Q_168 = ITOP.iow0.arr[42]; +wire [7:0] Q_169 = ITOP.iow1.arr[42]; +wire [7:0] Q_170 = ITOP.iow2.arr[42]; +wire [7:0] Q_171 = ITOP.iow3.arr[42]; +wire [7:0] Q_172 = ITOP.iow0.arr[43]; +wire [7:0] Q_173 = ITOP.iow1.arr[43]; +wire [7:0] Q_174 = ITOP.iow2.arr[43]; +wire [7:0] Q_175 = ITOP.iow3.arr[43]; +wire [7:0] Q_176 = ITOP.iow0.arr[44]; +wire [7:0] Q_177 = ITOP.iow1.arr[44]; +wire [7:0] Q_178 = ITOP.iow2.arr[44]; +wire [7:0] Q_179 = ITOP.iow3.arr[44]; +wire [7:0] Q_180 = ITOP.iow0.arr[45]; +wire [7:0] Q_181 = ITOP.iow1.arr[45]; +wire [7:0] Q_182 = ITOP.iow2.arr[45]; +wire [7:0] Q_183 = ITOP.iow3.arr[45]; +wire [7:0] Q_184 = ITOP.iow0.arr[46]; +wire [7:0] Q_185 = ITOP.iow1.arr[46]; +wire [7:0] Q_186 = ITOP.iow2.arr[46]; +wire [7:0] Q_187 = ITOP.iow3.arr[46]; +wire [7:0] Q_188 = ITOP.iow0.arr[47]; +wire [7:0] Q_189 = ITOP.iow1.arr[47]; +wire [7:0] Q_190 = ITOP.iow2.arr[47]; +wire [7:0] Q_191 = ITOP.iow3.arr[47]; +wire [7:0] Q_192 = ITOP.iow0.arr[48]; +wire [7:0] Q_193 = ITOP.iow1.arr[48]; +wire [7:0] Q_194 = ITOP.iow2.arr[48]; +wire [7:0] Q_195 = ITOP.iow3.arr[48]; +wire [7:0] Q_196 = ITOP.iow0.arr[49]; +wire [7:0] Q_197 = ITOP.iow1.arr[49]; +wire [7:0] Q_198 = ITOP.iow2.arr[49]; +wire [7:0] Q_199 = ITOP.iow3.arr[49]; +wire [7:0] Q_200 = ITOP.iow0.arr[50]; +wire [7:0] Q_201 = ITOP.iow1.arr[50]; +wire [7:0] Q_202 = ITOP.iow2.arr[50]; +wire [7:0] Q_203 = ITOP.iow3.arr[50]; +wire [7:0] Q_204 = ITOP.iow0.arr[51]; +wire [7:0] Q_205 = ITOP.iow1.arr[51]; +wire [7:0] Q_206 = ITOP.iow2.arr[51]; +wire [7:0] Q_207 = ITOP.iow3.arr[51]; +wire [7:0] Q_208 = ITOP.iow0.arr[52]; +wire [7:0] Q_209 = ITOP.iow1.arr[52]; +wire [7:0] Q_210 = ITOP.iow2.arr[52]; +wire [7:0] Q_211 = ITOP.iow3.arr[52]; +wire [7:0] Q_212 = ITOP.iow0.arr[53]; +wire [7:0] Q_213 = ITOP.iow1.arr[53]; +wire [7:0] Q_214 = ITOP.iow2.arr[53]; +wire [7:0] Q_215 = ITOP.iow3.arr[53]; +wire [7:0] Q_216 = ITOP.iow0.arr[54]; +wire [7:0] Q_217 = ITOP.iow1.arr[54]; +wire [7:0] Q_218 = ITOP.iow2.arr[54]; +wire [7:0] Q_219 = ITOP.iow3.arr[54]; +wire [7:0] Q_220 = ITOP.iow0.arr[55]; +wire [7:0] Q_221 = ITOP.iow1.arr[55]; +wire [7:0] Q_222 = ITOP.iow2.arr[55]; +wire [7:0] Q_223 = ITOP.iow3.arr[55]; +wire [7:0] Q_224 = ITOP.iow0.arr[56]; +wire [7:0] Q_225 = ITOP.iow1.arr[56]; +wire [7:0] Q_226 = ITOP.iow2.arr[56]; +wire [7:0] Q_227 = ITOP.iow3.arr[56]; +wire [7:0] Q_228 = ITOP.iow0.arr[57]; +wire [7:0] Q_229 = ITOP.iow1.arr[57]; +wire [7:0] Q_230 = ITOP.iow2.arr[57]; +wire [7:0] Q_231 = ITOP.iow3.arr[57]; +wire [7:0] Q_232 = ITOP.iow0.arr[58]; +wire [7:0] Q_233 = ITOP.iow1.arr[58]; +wire [7:0] Q_234 = ITOP.iow2.arr[58]; +wire [7:0] Q_235 = ITOP.iow3.arr[58]; +wire [7:0] Q_236 = ITOP.iow0.arr[59]; +wire [7:0] Q_237 = ITOP.iow1.arr[59]; +wire [7:0] Q_238 = ITOP.iow2.arr[59]; +wire [7:0] Q_239 = ITOP.iow3.arr[59]; +wire [7:0] Q_240 = ITOP.iow0.arr[60]; +wire [7:0] Q_241 = ITOP.iow1.arr[60]; +wire [7:0] Q_242 = ITOP.iow2.arr[60]; +wire [7:0] Q_243 = ITOP.iow3.arr[60]; +wire [7:0] Q_244 = ITOP.iow0.arr[61]; +wire [7:0] Q_245 = ITOP.iow1.arr[61]; +wire [7:0] Q_246 = ITOP.iow2.arr[61]; +wire [7:0] Q_247 = ITOP.iow3.arr[61]; +wire [7:0] Q_248 = ITOP.iow0.arr[62]; +wire [7:0] Q_249 = ITOP.iow1.arr[62]; +wire [7:0] Q_250 = ITOP.iow2.arr[62]; +wire [7:0] Q_251 = ITOP.iow3.arr[62]; +wire [7:0] Q_252 = ITOP.iow0.arr[63]; +wire [7:0] Q_253 = ITOP.iow1.arr[63]; +wire [7:0] Q_254 = ITOP.iow2.arr[63]; +wire [7:0] Q_255 = ITOP.iow3.arr[63]; +wire [7:0] Q_256 = ITOP.iow0.arr[64]; +wire [7:0] Q_257 = ITOP.iow1.arr[64]; +wire [7:0] Q_258 = ITOP.iow2.arr[64]; +wire [7:0] Q_259 = ITOP.iow3.arr[64]; +wire [7:0] Q_260 = ITOP.iow0.arr[65]; +wire [7:0] Q_261 = ITOP.iow1.arr[65]; +wire [7:0] Q_262 = ITOP.iow2.arr[65]; +wire [7:0] Q_263 = ITOP.iow3.arr[65]; +wire [7:0] Q_264 = ITOP.iow0.arr[66]; +wire [7:0] Q_265 = ITOP.iow1.arr[66]; +wire [7:0] Q_266 = ITOP.iow2.arr[66]; +wire [7:0] Q_267 = ITOP.iow3.arr[66]; +wire [7:0] Q_268 = ITOP.iow0.arr[67]; +wire [7:0] Q_269 = ITOP.iow1.arr[67]; +wire [7:0] Q_270 = ITOP.iow2.arr[67]; +wire [7:0] Q_271 = ITOP.iow3.arr[67]; +wire [7:0] Q_272 = ITOP.iow0.arr[68]; +wire [7:0] Q_273 = ITOP.iow1.arr[68]; +wire [7:0] Q_274 = ITOP.iow2.arr[68]; +wire [7:0] Q_275 = ITOP.iow3.arr[68]; +wire [7:0] Q_276 = ITOP.iow0.arr[69]; +wire [7:0] Q_277 = ITOP.iow1.arr[69]; +wire [7:0] Q_278 = ITOP.iow2.arr[69]; +wire [7:0] Q_279 = ITOP.iow3.arr[69]; +wire [7:0] Q_280 = ITOP.iow0.arr[70]; +wire [7:0] Q_281 = ITOP.iow1.arr[70]; +wire [7:0] Q_282 = ITOP.iow2.arr[70]; +wire [7:0] Q_283 = ITOP.iow3.arr[70]; +wire [7:0] Q_284 = ITOP.iow0.arr[71]; +wire [7:0] Q_285 = ITOP.iow1.arr[71]; +wire [7:0] Q_286 = ITOP.iow2.arr[71]; +wire [7:0] Q_287 = ITOP.iow3.arr[71]; +wire [7:0] Q_288 = ITOP.iow0.arr[72]; +wire [7:0] Q_289 = ITOP.iow1.arr[72]; +wire [7:0] Q_290 = ITOP.iow2.arr[72]; +wire [7:0] Q_291 = ITOP.iow3.arr[72]; +wire [7:0] Q_292 = ITOP.iow0.arr[73]; +wire [7:0] Q_293 = ITOP.iow1.arr[73]; +wire [7:0] Q_294 = ITOP.iow2.arr[73]; +wire [7:0] Q_295 = ITOP.iow3.arr[73]; +wire [7:0] Q_296 = ITOP.iow0.arr[74]; +wire [7:0] Q_297 = ITOP.iow1.arr[74]; +wire [7:0] Q_298 = ITOP.iow2.arr[74]; +wire [7:0] Q_299 = ITOP.iow3.arr[74]; +wire [7:0] Q_300 = ITOP.iow0.arr[75]; +wire [7:0] Q_301 = ITOP.iow1.arr[75]; +wire [7:0] Q_302 = ITOP.iow2.arr[75]; +wire [7:0] Q_303 = ITOP.iow3.arr[75]; +wire [7:0] Q_304 = ITOP.iow0.arr[76]; +wire [7:0] Q_305 = ITOP.iow1.arr[76]; +wire [7:0] Q_306 = ITOP.iow2.arr[76]; +wire [7:0] Q_307 = ITOP.iow3.arr[76]; +wire [7:0] Q_308 = ITOP.iow0.arr[77]; +wire [7:0] Q_309 = ITOP.iow1.arr[77]; +wire [7:0] Q_310 = ITOP.iow2.arr[77]; +wire [7:0] Q_311 = ITOP.iow3.arr[77]; +wire [7:0] Q_312 = ITOP.iow0.arr[78]; +wire [7:0] Q_313 = ITOP.iow1.arr[78]; +wire [7:0] Q_314 = ITOP.iow2.arr[78]; +wire [7:0] Q_315 = ITOP.iow3.arr[78]; +wire [7:0] Q_316 = ITOP.iow0.arr[79]; +wire [7:0] Q_317 = ITOP.iow1.arr[79]; +wire [7:0] Q_318 = ITOP.iow2.arr[79]; +wire [7:0] Q_319 = ITOP.iow3.arr[79]; +wire [7:0] Q_320 = ITOP.iow0.arr[80]; +wire [7:0] Q_321 = ITOP.iow1.arr[80]; +wire [7:0] Q_322 = ITOP.iow2.arr[80]; +wire [7:0] Q_323 = ITOP.iow3.arr[80]; +wire [7:0] Q_324 = ITOP.iow0.arr[81]; +wire [7:0] Q_325 = ITOP.iow1.arr[81]; +wire [7:0] Q_326 = ITOP.iow2.arr[81]; +wire [7:0] Q_327 = ITOP.iow3.arr[81]; +wire [7:0] Q_328 = ITOP.iow0.arr[82]; +wire [7:0] Q_329 = ITOP.iow1.arr[82]; +wire [7:0] Q_330 = ITOP.iow2.arr[82]; +wire [7:0] Q_331 = ITOP.iow3.arr[82]; +wire [7:0] Q_332 = ITOP.iow0.arr[83]; +wire [7:0] Q_333 = ITOP.iow1.arr[83]; +wire [7:0] Q_334 = ITOP.iow2.arr[83]; +wire [7:0] Q_335 = ITOP.iow3.arr[83]; +wire [7:0] Q_336 = ITOP.iow0.arr[84]; +wire [7:0] Q_337 = ITOP.iow1.arr[84]; +wire [7:0] Q_338 = ITOP.iow2.arr[84]; +wire [7:0] Q_339 = ITOP.iow3.arr[84]; +wire [7:0] Q_340 = ITOP.iow0.arr[85]; +wire [7:0] Q_341 = ITOP.iow1.arr[85]; +wire [7:0] Q_342 = ITOP.iow2.arr[85]; +wire [7:0] Q_343 = ITOP.iow3.arr[85]; +wire [7:0] Q_344 = ITOP.iow0.arr[86]; +wire [7:0] Q_345 = ITOP.iow1.arr[86]; +wire [7:0] Q_346 = ITOP.iow2.arr[86]; +wire [7:0] Q_347 = ITOP.iow3.arr[86]; +wire [7:0] Q_348 = ITOP.iow0.arr[87]; +wire [7:0] Q_349 = ITOP.iow1.arr[87]; +wire [7:0] Q_350 = ITOP.iow2.arr[87]; +wire [7:0] Q_351 = ITOP.iow3.arr[87]; +wire [7:0] Q_352 = ITOP.iow0.arr[88]; +wire [7:0] Q_353 = ITOP.iow1.arr[88]; +wire [7:0] Q_354 = ITOP.iow2.arr[88]; +wire [7:0] Q_355 = ITOP.iow3.arr[88]; +wire [7:0] Q_356 = ITOP.iow0.arr[89]; +wire [7:0] Q_357 = ITOP.iow1.arr[89]; +wire [7:0] Q_358 = ITOP.iow2.arr[89]; +wire [7:0] Q_359 = ITOP.iow3.arr[89]; +wire [7:0] Q_360 = ITOP.iow0.arr[90]; +wire [7:0] Q_361 = ITOP.iow1.arr[90]; +wire [7:0] Q_362 = ITOP.iow2.arr[90]; +wire [7:0] Q_363 = ITOP.iow3.arr[90]; +wire [7:0] Q_364 = ITOP.iow0.arr[91]; +wire [7:0] Q_365 = ITOP.iow1.arr[91]; +wire [7:0] Q_366 = ITOP.iow2.arr[91]; +wire [7:0] Q_367 = ITOP.iow3.arr[91]; +wire [7:0] Q_368 = ITOP.iow0.arr[92]; +wire [7:0] Q_369 = ITOP.iow1.arr[92]; +wire [7:0] Q_370 = ITOP.iow2.arr[92]; +wire [7:0] Q_371 = ITOP.iow3.arr[92]; +wire [7:0] Q_372 = ITOP.iow0.arr[93]; +wire [7:0] Q_373 = ITOP.iow1.arr[93]; +wire [7:0] Q_374 = ITOP.iow2.arr[93]; +wire [7:0] Q_375 = ITOP.iow3.arr[93]; +wire [7:0] Q_376 = ITOP.iow0.arr[94]; +wire [7:0] Q_377 = ITOP.iow1.arr[94]; +wire [7:0] Q_378 = ITOP.iow2.arr[94]; +wire [7:0] Q_379 = ITOP.iow3.arr[94]; +wire [7:0] Q_380 = ITOP.iow0.arr[95]; +wire [7:0] Q_381 = ITOP.iow1.arr[95]; +wire [7:0] Q_382 = ITOP.iow2.arr[95]; +wire [7:0] Q_383 = ITOP.iow3.arr[95]; +wire [7:0] Q_384 = ITOP.iow0.arr[96]; +wire [7:0] Q_385 = ITOP.iow1.arr[96]; +wire [7:0] Q_386 = ITOP.iow2.arr[96]; +wire [7:0] Q_387 = ITOP.iow3.arr[96]; +wire [7:0] Q_388 = ITOP.iow0.arr[97]; +wire [7:0] Q_389 = ITOP.iow1.arr[97]; +wire [7:0] Q_390 = ITOP.iow2.arr[97]; +wire [7:0] Q_391 = ITOP.iow3.arr[97]; +wire [7:0] Q_392 = ITOP.iow0.arr[98]; +wire [7:0] Q_393 = ITOP.iow1.arr[98]; +wire [7:0] Q_394 = ITOP.iow2.arr[98]; +wire [7:0] Q_395 = ITOP.iow3.arr[98]; +wire [7:0] Q_396 = ITOP.iow0.arr[99]; +wire [7:0] Q_397 = ITOP.iow1.arr[99]; +wire [7:0] Q_398 = ITOP.iow2.arr[99]; +wire [7:0] Q_399 = ITOP.iow3.arr[99]; +wire [7:0] Q_400 = ITOP.iow0.arr[100]; +wire [7:0] Q_401 = ITOP.iow1.arr[100]; +wire [7:0] Q_402 = ITOP.iow2.arr[100]; +wire [7:0] Q_403 = ITOP.iow3.arr[100]; +wire [7:0] Q_404 = ITOP.iow0.arr[101]; +wire [7:0] Q_405 = ITOP.iow1.arr[101]; +wire [7:0] Q_406 = ITOP.iow2.arr[101]; +wire [7:0] Q_407 = ITOP.iow3.arr[101]; +wire [7:0] Q_408 = ITOP.iow0.arr[102]; +wire [7:0] Q_409 = ITOP.iow1.arr[102]; +wire [7:0] Q_410 = ITOP.iow2.arr[102]; +wire [7:0] Q_411 = ITOP.iow3.arr[102]; +wire [7:0] Q_412 = ITOP.iow0.arr[103]; +wire [7:0] Q_413 = ITOP.iow1.arr[103]; +wire [7:0] Q_414 = ITOP.iow2.arr[103]; +wire [7:0] Q_415 = ITOP.iow3.arr[103]; +wire [7:0] Q_416 = ITOP.iow0.arr[104]; +wire [7:0] Q_417 = ITOP.iow1.arr[104]; +wire [7:0] Q_418 = ITOP.iow2.arr[104]; +wire [7:0] Q_419 = ITOP.iow3.arr[104]; +wire [7:0] Q_420 = ITOP.iow0.arr[105]; +wire [7:0] Q_421 = ITOP.iow1.arr[105]; +wire [7:0] Q_422 = ITOP.iow2.arr[105]; +wire [7:0] Q_423 = ITOP.iow3.arr[105]; +wire [7:0] Q_424 = ITOP.iow0.arr[106]; +wire [7:0] Q_425 = ITOP.iow1.arr[106]; +wire [7:0] Q_426 = ITOP.iow2.arr[106]; +wire [7:0] Q_427 = ITOP.iow3.arr[106]; +wire [7:0] Q_428 = ITOP.iow0.arr[107]; +wire [7:0] Q_429 = ITOP.iow1.arr[107]; +wire [7:0] Q_430 = ITOP.iow2.arr[107]; +wire [7:0] Q_431 = ITOP.iow3.arr[107]; +wire [7:0] Q_432 = ITOP.iow0.arr[108]; +wire [7:0] Q_433 = ITOP.iow1.arr[108]; +wire [7:0] Q_434 = ITOP.iow2.arr[108]; +wire [7:0] Q_435 = ITOP.iow3.arr[108]; +wire [7:0] Q_436 = ITOP.iow0.arr[109]; +wire [7:0] Q_437 = ITOP.iow1.arr[109]; +wire [7:0] Q_438 = ITOP.iow2.arr[109]; +wire [7:0] Q_439 = ITOP.iow3.arr[109]; +wire [7:0] Q_440 = ITOP.iow0.arr[110]; +wire [7:0] Q_441 = ITOP.iow1.arr[110]; +wire [7:0] Q_442 = ITOP.iow2.arr[110]; +wire [7:0] Q_443 = ITOP.iow3.arr[110]; +wire [7:0] Q_444 = ITOP.iow0.arr[111]; +wire [7:0] Q_445 = ITOP.iow1.arr[111]; +wire [7:0] Q_446 = ITOP.iow2.arr[111]; +wire [7:0] Q_447 = ITOP.iow3.arr[111]; +wire [7:0] Q_448 = ITOP.iow0.arr[112]; +wire [7:0] Q_449 = ITOP.iow1.arr[112]; +wire [7:0] Q_450 = ITOP.iow2.arr[112]; +wire [7:0] Q_451 = ITOP.iow3.arr[112]; +wire [7:0] Q_452 = ITOP.iow0.arr[113]; +wire [7:0] Q_453 = ITOP.iow1.arr[113]; +wire [7:0] Q_454 = ITOP.iow2.arr[113]; +wire [7:0] Q_455 = ITOP.iow3.arr[113]; +wire [7:0] Q_456 = ITOP.iow0.arr[114]; +wire [7:0] Q_457 = ITOP.iow1.arr[114]; +wire [7:0] Q_458 = ITOP.iow2.arr[114]; +wire [7:0] Q_459 = ITOP.iow3.arr[114]; +wire [7:0] Q_460 = ITOP.iow0.arr[115]; +wire [7:0] Q_461 = ITOP.iow1.arr[115]; +wire [7:0] Q_462 = ITOP.iow2.arr[115]; +wire [7:0] Q_463 = ITOP.iow3.arr[115]; +wire [7:0] Q_464 = ITOP.iow0.arr[116]; +wire [7:0] Q_465 = ITOP.iow1.arr[116]; +wire [7:0] Q_466 = ITOP.iow2.arr[116]; +wire [7:0] Q_467 = ITOP.iow3.arr[116]; +wire [7:0] Q_468 = ITOP.iow0.arr[117]; +wire [7:0] Q_469 = ITOP.iow1.arr[117]; +wire [7:0] Q_470 = ITOP.iow2.arr[117]; +wire [7:0] Q_471 = ITOP.iow3.arr[117]; +wire [7:0] Q_472 = ITOP.iow0.arr[118]; +wire [7:0] Q_473 = ITOP.iow1.arr[118]; +wire [7:0] Q_474 = ITOP.iow2.arr[118]; +wire [7:0] Q_475 = ITOP.iow3.arr[118]; +wire [7:0] Q_476 = ITOP.iow0.arr[119]; +wire [7:0] Q_477 = ITOP.iow1.arr[119]; +wire [7:0] Q_478 = ITOP.iow2.arr[119]; +wire [7:0] Q_479 = ITOP.iow3.arr[119]; +wire [7:0] Q_480 = ITOP.iow0.arr[120]; +wire [7:0] Q_481 = ITOP.iow1.arr[120]; +wire [7:0] Q_482 = ITOP.iow2.arr[120]; +wire [7:0] Q_483 = ITOP.iow3.arr[120]; +wire [7:0] Q_484 = ITOP.iow0.arr[121]; +wire [7:0] Q_485 = ITOP.iow1.arr[121]; +wire [7:0] Q_486 = ITOP.iow2.arr[121]; +wire [7:0] Q_487 = ITOP.iow3.arr[121]; +wire [7:0] Q_488 = ITOP.iow0.arr[122]; +wire [7:0] Q_489 = ITOP.iow1.arr[122]; +wire [7:0] Q_490 = ITOP.iow2.arr[122]; +wire [7:0] Q_491 = ITOP.iow3.arr[122]; +wire [7:0] Q_492 = ITOP.iow0.arr[123]; +wire [7:0] Q_493 = ITOP.iow1.arr[123]; +wire [7:0] Q_494 = ITOP.iow2.arr[123]; +wire [7:0] Q_495 = ITOP.iow3.arr[123]; +wire [7:0] Q_496 = ITOP.iow0.arr[124]; +wire [7:0] Q_497 = ITOP.iow1.arr[124]; +wire [7:0] Q_498 = ITOP.iow2.arr[124]; +wire [7:0] Q_499 = ITOP.iow3.arr[124]; +wire [7:0] Q_500 = ITOP.iow0.arr[125]; +wire [7:0] Q_501 = ITOP.iow1.arr[125]; +wire [7:0] Q_502 = ITOP.iow2.arr[125]; +wire [7:0] Q_503 = ITOP.iow3.arr[125]; +wire [7:0] Q_504 = ITOP.iow0.arr[126]; +wire [7:0] Q_505 = ITOP.iow1.arr[126]; +wire [7:0] Q_506 = ITOP.iow2.arr[126]; +wire [7:0] Q_507 = ITOP.iow3.arr[126]; +wire [7:0] Q_508 = ITOP.iow0.arr[127]; +wire [7:0] Q_509 = ITOP.iow1.arr[127]; +wire [7:0] Q_510 = ITOP.iow2.arr[127]; +wire [7:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [7:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [7:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [7:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [7:0] WD_FF; + reg [7:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [7:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [7:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [7:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X8_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [7:0] WD; +input [8:0] RA, WA; +output [7:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [7:0] WDQ; + wire [7:0] WDBQ; + wire [7:0] WMNexp; + wire [7:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [7:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {8{1'b0}}; + assign SHFT = {8{1'b1}}; + reg [7:0] WDQ_pr; + wire [7:0] WDBQ_pr; + assign WMNexp = {8{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[7:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [7:0] dout; + wire [7:0] RD; + wire RD_rdnt; + wire [7:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [7:0] RDBYPASS = {8{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [7:0] force_x; +`ifndef SYNTHESIS + assign force_x = {8{1'bx}}; +`else + assign force_x = {8{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [7:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [7:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {8{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {8{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {8{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {8{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {8{RdClk0}} & ~dout0; + assign rmuxd1 = {8{RdClk1}} & ~dout1; + assign rmuxd2 = {8{RdClk2}} & ~dout2; + assign rmuxd3 = {8{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[7:0] <= (rmuxd0[7:0] | rmuxd1[7:0] | rmuxd2[7:0] | rmuxd3[7:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [7:0] data; + reg [7:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [7:0] mem_read_bank; +input [8:0] addr; +reg [7:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X8_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 8; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [7:0] val; + integer i; + begin + for (i=0; i<512; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [7:0] val; + integer i; + begin + val = {8{fill_bit}}; + for (i=0; i<512; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [8:0] addr; + reg [7:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [8-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {8 {1'b1}} `else { $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {8 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[1:0] == 2'b00) + rd = ITOP.iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + rd = ITOP.iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + rd = ITOP.iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + rd = ITOP.iow3.mem_read_raw_subbank(addr[8:2]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [31:0] mem_phys_read_padr; +input [6:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [7:0] rd[3:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(addr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(addr); + for (i=0; i<=7; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [31:0] mem_phys_read_ladr; +input [8:0] addr; + reg [6:0] paddr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [7:0] rd[3:0]; + integer i; + begin + paddr = (addr >> 2); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + rd[2] = ITOP.iow2.mem_read_raw_subbank(paddr); + rd[3] = ITOP.iow3.mem_read_raw_subbank(paddr); + for (i=0; i<=7; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [31:0] mem_phys_read_pmasked; +input [8:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [7:0] rd[3 : 0]; + integer i; + begin + rd[0] = (addr[1:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[8:2]) : 8'bx; + rd[1] = (addr[1:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[8:2]) : 8'bx; + rd[2] = (addr[1:0] === 2) ? ITOP.iow2.mem_read_raw_subbank(addr[8:2]) : 8'bx; + rd[3] = (addr[1:0] === 3) ? ITOP.iow3.mem_read_raw_subbank(addr[8:2]) : 8'bx; + for (i=0; i<=7; i=i+1) begin + rd_row[i*4+0] = rd[0][i]; + rd_row[i*4+1] = rd[1][i]; + rd_row[i*4+2] = rd[2][i]; + rd_row[i*4+3] = rd[3][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [31:0] data; + reg [7:0] wr[3:0]; + integer i; + begin + for (i=0; i<=7; i=i+1) begin + wr[0][i] = data[i*4+0]; + wr[1][i] = data[i*4+1]; + wr[2][i] = data[i*4+2]; + wr[3][i] = data[i*4+3]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + ITOP.iow2.mem_wr_raw_subbank(addr,wr[2]); + ITOP.iow3.mem_wr_raw_subbank(addr,wr[3]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [8:0] addr; + begin + mem_log_to_phys_adr = (addr >> 2) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + ITOP.iow2.monitor_on = 1'b1; + ITOP.iow3.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + ITOP.iow2.monitor_on = 1'b0; + ITOP.iow3.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [31:0] mon_bit_w; +input [6:0] addr; + reg [31:0] mon_row; + reg [7:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; + mon_word[2] = ITOP.iow2.bit_written[addr]; + mon_word[3] = ITOP.iow3.bit_written[addr]; +// combine all 4 words to a row + for (i=0; i<=7; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [31:0] mon_bit_r; +input [6:0] addr; + reg [31:0] mon_row; + reg [7:0] mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; + mon_word[2] = ITOP.iow2.bit_read[addr]; + mon_word[3] = ITOP.iow3.bit_read[addr]; +// combine all 4 words to a row + for (i=0; i<=7; i=i+1) begin + mon_row[i*4+0] = mon_word[0][i]; + mon_row[i*4+1] = mon_word[1][i]; + mon_row[i*4+2] = mon_word[2][i]; + mon_row[i*4+3] = mon_word[3][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; + mon_word[2] = ITOP.iow2.word_written[addr]; + mon_word[3] = ITOP.iow3.word_written[addr]; +// combine all 4 words to a row + mon_word_w = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[3:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; + mon_word[2] = ITOP.iow2.word_read[addr]; + mon_word[3] = ITOP.iow3.word_read[addr]; +// combine all 4 words to a row + mon_word_r = mon_word[0] | mon_word[1]| mon_word[2]| mon_word[3] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [31:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=128;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<128; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [7:0] Q_0 = ITOP.iow0.arr[0]; +wire [7:0] Q_1 = ITOP.iow1.arr[0]; +wire [7:0] Q_2 = ITOP.iow2.arr[0]; +wire [7:0] Q_3 = ITOP.iow3.arr[0]; +wire [7:0] Q_4 = ITOP.iow0.arr[1]; +wire [7:0] Q_5 = ITOP.iow1.arr[1]; +wire [7:0] Q_6 = ITOP.iow2.arr[1]; +wire [7:0] Q_7 = ITOP.iow3.arr[1]; +wire [7:0] Q_8 = ITOP.iow0.arr[2]; +wire [7:0] Q_9 = ITOP.iow1.arr[2]; +wire [7:0] Q_10 = ITOP.iow2.arr[2]; +wire [7:0] Q_11 = ITOP.iow3.arr[2]; +wire [7:0] Q_12 = ITOP.iow0.arr[3]; +wire [7:0] Q_13 = ITOP.iow1.arr[3]; +wire [7:0] Q_14 = ITOP.iow2.arr[3]; +wire [7:0] Q_15 = ITOP.iow3.arr[3]; +wire [7:0] Q_16 = ITOP.iow0.arr[4]; +wire [7:0] Q_17 = ITOP.iow1.arr[4]; +wire [7:0] Q_18 = ITOP.iow2.arr[4]; +wire [7:0] Q_19 = ITOP.iow3.arr[4]; +wire [7:0] Q_20 = ITOP.iow0.arr[5]; +wire [7:0] Q_21 = ITOP.iow1.arr[5]; +wire [7:0] Q_22 = ITOP.iow2.arr[5]; +wire [7:0] Q_23 = ITOP.iow3.arr[5]; +wire [7:0] Q_24 = ITOP.iow0.arr[6]; +wire [7:0] Q_25 = ITOP.iow1.arr[6]; +wire [7:0] Q_26 = ITOP.iow2.arr[6]; +wire [7:0] Q_27 = ITOP.iow3.arr[6]; +wire [7:0] Q_28 = ITOP.iow0.arr[7]; +wire [7:0] Q_29 = ITOP.iow1.arr[7]; +wire [7:0] Q_30 = ITOP.iow2.arr[7]; +wire [7:0] Q_31 = ITOP.iow3.arr[7]; +wire [7:0] Q_32 = ITOP.iow0.arr[8]; +wire [7:0] Q_33 = ITOP.iow1.arr[8]; +wire [7:0] Q_34 = ITOP.iow2.arr[8]; +wire [7:0] Q_35 = ITOP.iow3.arr[8]; +wire [7:0] Q_36 = ITOP.iow0.arr[9]; +wire [7:0] Q_37 = ITOP.iow1.arr[9]; +wire [7:0] Q_38 = ITOP.iow2.arr[9]; +wire [7:0] Q_39 = ITOP.iow3.arr[9]; +wire [7:0] Q_40 = ITOP.iow0.arr[10]; +wire [7:0] Q_41 = ITOP.iow1.arr[10]; +wire [7:0] Q_42 = ITOP.iow2.arr[10]; +wire [7:0] Q_43 = ITOP.iow3.arr[10]; +wire [7:0] Q_44 = ITOP.iow0.arr[11]; +wire [7:0] Q_45 = ITOP.iow1.arr[11]; +wire [7:0] Q_46 = ITOP.iow2.arr[11]; +wire [7:0] Q_47 = ITOP.iow3.arr[11]; +wire [7:0] Q_48 = ITOP.iow0.arr[12]; +wire [7:0] Q_49 = ITOP.iow1.arr[12]; +wire [7:0] Q_50 = ITOP.iow2.arr[12]; +wire [7:0] Q_51 = ITOP.iow3.arr[12]; +wire [7:0] Q_52 = ITOP.iow0.arr[13]; +wire [7:0] Q_53 = ITOP.iow1.arr[13]; +wire [7:0] Q_54 = ITOP.iow2.arr[13]; +wire [7:0] Q_55 = ITOP.iow3.arr[13]; +wire [7:0] Q_56 = ITOP.iow0.arr[14]; +wire [7:0] Q_57 = ITOP.iow1.arr[14]; +wire [7:0] Q_58 = ITOP.iow2.arr[14]; +wire [7:0] Q_59 = ITOP.iow3.arr[14]; +wire [7:0] Q_60 = ITOP.iow0.arr[15]; +wire [7:0] Q_61 = ITOP.iow1.arr[15]; +wire [7:0] Q_62 = ITOP.iow2.arr[15]; +wire [7:0] Q_63 = ITOP.iow3.arr[15]; +wire [7:0] Q_64 = ITOP.iow0.arr[16]; +wire [7:0] Q_65 = ITOP.iow1.arr[16]; +wire [7:0] Q_66 = ITOP.iow2.arr[16]; +wire [7:0] Q_67 = ITOP.iow3.arr[16]; +wire [7:0] Q_68 = ITOP.iow0.arr[17]; +wire [7:0] Q_69 = ITOP.iow1.arr[17]; +wire [7:0] Q_70 = ITOP.iow2.arr[17]; +wire [7:0] Q_71 = ITOP.iow3.arr[17]; +wire [7:0] Q_72 = ITOP.iow0.arr[18]; +wire [7:0] Q_73 = ITOP.iow1.arr[18]; +wire [7:0] Q_74 = ITOP.iow2.arr[18]; +wire [7:0] Q_75 = ITOP.iow3.arr[18]; +wire [7:0] Q_76 = ITOP.iow0.arr[19]; +wire [7:0] Q_77 = ITOP.iow1.arr[19]; +wire [7:0] Q_78 = ITOP.iow2.arr[19]; +wire [7:0] Q_79 = ITOP.iow3.arr[19]; +wire [7:0] Q_80 = ITOP.iow0.arr[20]; +wire [7:0] Q_81 = ITOP.iow1.arr[20]; +wire [7:0] Q_82 = ITOP.iow2.arr[20]; +wire [7:0] Q_83 = ITOP.iow3.arr[20]; +wire [7:0] Q_84 = ITOP.iow0.arr[21]; +wire [7:0] Q_85 = ITOP.iow1.arr[21]; +wire [7:0] Q_86 = ITOP.iow2.arr[21]; +wire [7:0] Q_87 = ITOP.iow3.arr[21]; +wire [7:0] Q_88 = ITOP.iow0.arr[22]; +wire [7:0] Q_89 = ITOP.iow1.arr[22]; +wire [7:0] Q_90 = ITOP.iow2.arr[22]; +wire [7:0] Q_91 = ITOP.iow3.arr[22]; +wire [7:0] Q_92 = ITOP.iow0.arr[23]; +wire [7:0] Q_93 = ITOP.iow1.arr[23]; +wire [7:0] Q_94 = ITOP.iow2.arr[23]; +wire [7:0] Q_95 = ITOP.iow3.arr[23]; +wire [7:0] Q_96 = ITOP.iow0.arr[24]; +wire [7:0] Q_97 = ITOP.iow1.arr[24]; +wire [7:0] Q_98 = ITOP.iow2.arr[24]; +wire [7:0] Q_99 = ITOP.iow3.arr[24]; +wire [7:0] Q_100 = ITOP.iow0.arr[25]; +wire [7:0] Q_101 = ITOP.iow1.arr[25]; +wire [7:0] Q_102 = ITOP.iow2.arr[25]; +wire [7:0] Q_103 = ITOP.iow3.arr[25]; +wire [7:0] Q_104 = ITOP.iow0.arr[26]; +wire [7:0] Q_105 = ITOP.iow1.arr[26]; +wire [7:0] Q_106 = ITOP.iow2.arr[26]; +wire [7:0] Q_107 = ITOP.iow3.arr[26]; +wire [7:0] Q_108 = ITOP.iow0.arr[27]; +wire [7:0] Q_109 = ITOP.iow1.arr[27]; +wire [7:0] Q_110 = ITOP.iow2.arr[27]; +wire [7:0] Q_111 = ITOP.iow3.arr[27]; +wire [7:0] Q_112 = ITOP.iow0.arr[28]; +wire [7:0] Q_113 = ITOP.iow1.arr[28]; +wire [7:0] Q_114 = ITOP.iow2.arr[28]; +wire [7:0] Q_115 = ITOP.iow3.arr[28]; +wire [7:0] Q_116 = ITOP.iow0.arr[29]; +wire [7:0] Q_117 = ITOP.iow1.arr[29]; +wire [7:0] Q_118 = ITOP.iow2.arr[29]; +wire [7:0] Q_119 = ITOP.iow3.arr[29]; +wire [7:0] Q_120 = ITOP.iow0.arr[30]; +wire [7:0] Q_121 = ITOP.iow1.arr[30]; +wire [7:0] Q_122 = ITOP.iow2.arr[30]; +wire [7:0] Q_123 = ITOP.iow3.arr[30]; +wire [7:0] Q_124 = ITOP.iow0.arr[31]; +wire [7:0] Q_125 = ITOP.iow1.arr[31]; +wire [7:0] Q_126 = ITOP.iow2.arr[31]; +wire [7:0] Q_127 = ITOP.iow3.arr[31]; +wire [7:0] Q_128 = ITOP.iow0.arr[32]; +wire [7:0] Q_129 = ITOP.iow1.arr[32]; +wire [7:0] Q_130 = ITOP.iow2.arr[32]; +wire [7:0] Q_131 = ITOP.iow3.arr[32]; +wire [7:0] Q_132 = ITOP.iow0.arr[33]; +wire [7:0] Q_133 = ITOP.iow1.arr[33]; +wire [7:0] Q_134 = ITOP.iow2.arr[33]; +wire [7:0] Q_135 = ITOP.iow3.arr[33]; +wire [7:0] Q_136 = ITOP.iow0.arr[34]; +wire [7:0] Q_137 = ITOP.iow1.arr[34]; +wire [7:0] Q_138 = ITOP.iow2.arr[34]; +wire [7:0] Q_139 = ITOP.iow3.arr[34]; +wire [7:0] Q_140 = ITOP.iow0.arr[35]; +wire [7:0] Q_141 = ITOP.iow1.arr[35]; +wire [7:0] Q_142 = ITOP.iow2.arr[35]; +wire [7:0] Q_143 = ITOP.iow3.arr[35]; +wire [7:0] Q_144 = ITOP.iow0.arr[36]; +wire [7:0] Q_145 = ITOP.iow1.arr[36]; +wire [7:0] Q_146 = ITOP.iow2.arr[36]; +wire [7:0] Q_147 = ITOP.iow3.arr[36]; +wire [7:0] Q_148 = ITOP.iow0.arr[37]; +wire [7:0] Q_149 = ITOP.iow1.arr[37]; +wire [7:0] Q_150 = ITOP.iow2.arr[37]; +wire [7:0] Q_151 = ITOP.iow3.arr[37]; +wire [7:0] Q_152 = ITOP.iow0.arr[38]; +wire [7:0] Q_153 = ITOP.iow1.arr[38]; +wire [7:0] Q_154 = ITOP.iow2.arr[38]; +wire [7:0] Q_155 = ITOP.iow3.arr[38]; +wire [7:0] Q_156 = ITOP.iow0.arr[39]; +wire [7:0] Q_157 = ITOP.iow1.arr[39]; +wire [7:0] Q_158 = ITOP.iow2.arr[39]; +wire [7:0] Q_159 = ITOP.iow3.arr[39]; +wire [7:0] Q_160 = ITOP.iow0.arr[40]; +wire [7:0] Q_161 = ITOP.iow1.arr[40]; +wire [7:0] Q_162 = ITOP.iow2.arr[40]; +wire [7:0] Q_163 = ITOP.iow3.arr[40]; +wire [7:0] Q_164 = ITOP.iow0.arr[41]; +wire [7:0] Q_165 = ITOP.iow1.arr[41]; +wire [7:0] Q_166 = ITOP.iow2.arr[41]; +wire [7:0] Q_167 = ITOP.iow3.arr[41]; +wire [7:0] Q_168 = ITOP.iow0.arr[42]; +wire [7:0] Q_169 = ITOP.iow1.arr[42]; +wire [7:0] Q_170 = ITOP.iow2.arr[42]; +wire [7:0] Q_171 = ITOP.iow3.arr[42]; +wire [7:0] Q_172 = ITOP.iow0.arr[43]; +wire [7:0] Q_173 = ITOP.iow1.arr[43]; +wire [7:0] Q_174 = ITOP.iow2.arr[43]; +wire [7:0] Q_175 = ITOP.iow3.arr[43]; +wire [7:0] Q_176 = ITOP.iow0.arr[44]; +wire [7:0] Q_177 = ITOP.iow1.arr[44]; +wire [7:0] Q_178 = ITOP.iow2.arr[44]; +wire [7:0] Q_179 = ITOP.iow3.arr[44]; +wire [7:0] Q_180 = ITOP.iow0.arr[45]; +wire [7:0] Q_181 = ITOP.iow1.arr[45]; +wire [7:0] Q_182 = ITOP.iow2.arr[45]; +wire [7:0] Q_183 = ITOP.iow3.arr[45]; +wire [7:0] Q_184 = ITOP.iow0.arr[46]; +wire [7:0] Q_185 = ITOP.iow1.arr[46]; +wire [7:0] Q_186 = ITOP.iow2.arr[46]; +wire [7:0] Q_187 = ITOP.iow3.arr[46]; +wire [7:0] Q_188 = ITOP.iow0.arr[47]; +wire [7:0] Q_189 = ITOP.iow1.arr[47]; +wire [7:0] Q_190 = ITOP.iow2.arr[47]; +wire [7:0] Q_191 = ITOP.iow3.arr[47]; +wire [7:0] Q_192 = ITOP.iow0.arr[48]; +wire [7:0] Q_193 = ITOP.iow1.arr[48]; +wire [7:0] Q_194 = ITOP.iow2.arr[48]; +wire [7:0] Q_195 = ITOP.iow3.arr[48]; +wire [7:0] Q_196 = ITOP.iow0.arr[49]; +wire [7:0] Q_197 = ITOP.iow1.arr[49]; +wire [7:0] Q_198 = ITOP.iow2.arr[49]; +wire [7:0] Q_199 = ITOP.iow3.arr[49]; +wire [7:0] Q_200 = ITOP.iow0.arr[50]; +wire [7:0] Q_201 = ITOP.iow1.arr[50]; +wire [7:0] Q_202 = ITOP.iow2.arr[50]; +wire [7:0] Q_203 = ITOP.iow3.arr[50]; +wire [7:0] Q_204 = ITOP.iow0.arr[51]; +wire [7:0] Q_205 = ITOP.iow1.arr[51]; +wire [7:0] Q_206 = ITOP.iow2.arr[51]; +wire [7:0] Q_207 = ITOP.iow3.arr[51]; +wire [7:0] Q_208 = ITOP.iow0.arr[52]; +wire [7:0] Q_209 = ITOP.iow1.arr[52]; +wire [7:0] Q_210 = ITOP.iow2.arr[52]; +wire [7:0] Q_211 = ITOP.iow3.arr[52]; +wire [7:0] Q_212 = ITOP.iow0.arr[53]; +wire [7:0] Q_213 = ITOP.iow1.arr[53]; +wire [7:0] Q_214 = ITOP.iow2.arr[53]; +wire [7:0] Q_215 = ITOP.iow3.arr[53]; +wire [7:0] Q_216 = ITOP.iow0.arr[54]; +wire [7:0] Q_217 = ITOP.iow1.arr[54]; +wire [7:0] Q_218 = ITOP.iow2.arr[54]; +wire [7:0] Q_219 = ITOP.iow3.arr[54]; +wire [7:0] Q_220 = ITOP.iow0.arr[55]; +wire [7:0] Q_221 = ITOP.iow1.arr[55]; +wire [7:0] Q_222 = ITOP.iow2.arr[55]; +wire [7:0] Q_223 = ITOP.iow3.arr[55]; +wire [7:0] Q_224 = ITOP.iow0.arr[56]; +wire [7:0] Q_225 = ITOP.iow1.arr[56]; +wire [7:0] Q_226 = ITOP.iow2.arr[56]; +wire [7:0] Q_227 = ITOP.iow3.arr[56]; +wire [7:0] Q_228 = ITOP.iow0.arr[57]; +wire [7:0] Q_229 = ITOP.iow1.arr[57]; +wire [7:0] Q_230 = ITOP.iow2.arr[57]; +wire [7:0] Q_231 = ITOP.iow3.arr[57]; +wire [7:0] Q_232 = ITOP.iow0.arr[58]; +wire [7:0] Q_233 = ITOP.iow1.arr[58]; +wire [7:0] Q_234 = ITOP.iow2.arr[58]; +wire [7:0] Q_235 = ITOP.iow3.arr[58]; +wire [7:0] Q_236 = ITOP.iow0.arr[59]; +wire [7:0] Q_237 = ITOP.iow1.arr[59]; +wire [7:0] Q_238 = ITOP.iow2.arr[59]; +wire [7:0] Q_239 = ITOP.iow3.arr[59]; +wire [7:0] Q_240 = ITOP.iow0.arr[60]; +wire [7:0] Q_241 = ITOP.iow1.arr[60]; +wire [7:0] Q_242 = ITOP.iow2.arr[60]; +wire [7:0] Q_243 = ITOP.iow3.arr[60]; +wire [7:0] Q_244 = ITOP.iow0.arr[61]; +wire [7:0] Q_245 = ITOP.iow1.arr[61]; +wire [7:0] Q_246 = ITOP.iow2.arr[61]; +wire [7:0] Q_247 = ITOP.iow3.arr[61]; +wire [7:0] Q_248 = ITOP.iow0.arr[62]; +wire [7:0] Q_249 = ITOP.iow1.arr[62]; +wire [7:0] Q_250 = ITOP.iow2.arr[62]; +wire [7:0] Q_251 = ITOP.iow3.arr[62]; +wire [7:0] Q_252 = ITOP.iow0.arr[63]; +wire [7:0] Q_253 = ITOP.iow1.arr[63]; +wire [7:0] Q_254 = ITOP.iow2.arr[63]; +wire [7:0] Q_255 = ITOP.iow3.arr[63]; +wire [7:0] Q_256 = ITOP.iow0.arr[64]; +wire [7:0] Q_257 = ITOP.iow1.arr[64]; +wire [7:0] Q_258 = ITOP.iow2.arr[64]; +wire [7:0] Q_259 = ITOP.iow3.arr[64]; +wire [7:0] Q_260 = ITOP.iow0.arr[65]; +wire [7:0] Q_261 = ITOP.iow1.arr[65]; +wire [7:0] Q_262 = ITOP.iow2.arr[65]; +wire [7:0] Q_263 = ITOP.iow3.arr[65]; +wire [7:0] Q_264 = ITOP.iow0.arr[66]; +wire [7:0] Q_265 = ITOP.iow1.arr[66]; +wire [7:0] Q_266 = ITOP.iow2.arr[66]; +wire [7:0] Q_267 = ITOP.iow3.arr[66]; +wire [7:0] Q_268 = ITOP.iow0.arr[67]; +wire [7:0] Q_269 = ITOP.iow1.arr[67]; +wire [7:0] Q_270 = ITOP.iow2.arr[67]; +wire [7:0] Q_271 = ITOP.iow3.arr[67]; +wire [7:0] Q_272 = ITOP.iow0.arr[68]; +wire [7:0] Q_273 = ITOP.iow1.arr[68]; +wire [7:0] Q_274 = ITOP.iow2.arr[68]; +wire [7:0] Q_275 = ITOP.iow3.arr[68]; +wire [7:0] Q_276 = ITOP.iow0.arr[69]; +wire [7:0] Q_277 = ITOP.iow1.arr[69]; +wire [7:0] Q_278 = ITOP.iow2.arr[69]; +wire [7:0] Q_279 = ITOP.iow3.arr[69]; +wire [7:0] Q_280 = ITOP.iow0.arr[70]; +wire [7:0] Q_281 = ITOP.iow1.arr[70]; +wire [7:0] Q_282 = ITOP.iow2.arr[70]; +wire [7:0] Q_283 = ITOP.iow3.arr[70]; +wire [7:0] Q_284 = ITOP.iow0.arr[71]; +wire [7:0] Q_285 = ITOP.iow1.arr[71]; +wire [7:0] Q_286 = ITOP.iow2.arr[71]; +wire [7:0] Q_287 = ITOP.iow3.arr[71]; +wire [7:0] Q_288 = ITOP.iow0.arr[72]; +wire [7:0] Q_289 = ITOP.iow1.arr[72]; +wire [7:0] Q_290 = ITOP.iow2.arr[72]; +wire [7:0] Q_291 = ITOP.iow3.arr[72]; +wire [7:0] Q_292 = ITOP.iow0.arr[73]; +wire [7:0] Q_293 = ITOP.iow1.arr[73]; +wire [7:0] Q_294 = ITOP.iow2.arr[73]; +wire [7:0] Q_295 = ITOP.iow3.arr[73]; +wire [7:0] Q_296 = ITOP.iow0.arr[74]; +wire [7:0] Q_297 = ITOP.iow1.arr[74]; +wire [7:0] Q_298 = ITOP.iow2.arr[74]; +wire [7:0] Q_299 = ITOP.iow3.arr[74]; +wire [7:0] Q_300 = ITOP.iow0.arr[75]; +wire [7:0] Q_301 = ITOP.iow1.arr[75]; +wire [7:0] Q_302 = ITOP.iow2.arr[75]; +wire [7:0] Q_303 = ITOP.iow3.arr[75]; +wire [7:0] Q_304 = ITOP.iow0.arr[76]; +wire [7:0] Q_305 = ITOP.iow1.arr[76]; +wire [7:0] Q_306 = ITOP.iow2.arr[76]; +wire [7:0] Q_307 = ITOP.iow3.arr[76]; +wire [7:0] Q_308 = ITOP.iow0.arr[77]; +wire [7:0] Q_309 = ITOP.iow1.arr[77]; +wire [7:0] Q_310 = ITOP.iow2.arr[77]; +wire [7:0] Q_311 = ITOP.iow3.arr[77]; +wire [7:0] Q_312 = ITOP.iow0.arr[78]; +wire [7:0] Q_313 = ITOP.iow1.arr[78]; +wire [7:0] Q_314 = ITOP.iow2.arr[78]; +wire [7:0] Q_315 = ITOP.iow3.arr[78]; +wire [7:0] Q_316 = ITOP.iow0.arr[79]; +wire [7:0] Q_317 = ITOP.iow1.arr[79]; +wire [7:0] Q_318 = ITOP.iow2.arr[79]; +wire [7:0] Q_319 = ITOP.iow3.arr[79]; +wire [7:0] Q_320 = ITOP.iow0.arr[80]; +wire [7:0] Q_321 = ITOP.iow1.arr[80]; +wire [7:0] Q_322 = ITOP.iow2.arr[80]; +wire [7:0] Q_323 = ITOP.iow3.arr[80]; +wire [7:0] Q_324 = ITOP.iow0.arr[81]; +wire [7:0] Q_325 = ITOP.iow1.arr[81]; +wire [7:0] Q_326 = ITOP.iow2.arr[81]; +wire [7:0] Q_327 = ITOP.iow3.arr[81]; +wire [7:0] Q_328 = ITOP.iow0.arr[82]; +wire [7:0] Q_329 = ITOP.iow1.arr[82]; +wire [7:0] Q_330 = ITOP.iow2.arr[82]; +wire [7:0] Q_331 = ITOP.iow3.arr[82]; +wire [7:0] Q_332 = ITOP.iow0.arr[83]; +wire [7:0] Q_333 = ITOP.iow1.arr[83]; +wire [7:0] Q_334 = ITOP.iow2.arr[83]; +wire [7:0] Q_335 = ITOP.iow3.arr[83]; +wire [7:0] Q_336 = ITOP.iow0.arr[84]; +wire [7:0] Q_337 = ITOP.iow1.arr[84]; +wire [7:0] Q_338 = ITOP.iow2.arr[84]; +wire [7:0] Q_339 = ITOP.iow3.arr[84]; +wire [7:0] Q_340 = ITOP.iow0.arr[85]; +wire [7:0] Q_341 = ITOP.iow1.arr[85]; +wire [7:0] Q_342 = ITOP.iow2.arr[85]; +wire [7:0] Q_343 = ITOP.iow3.arr[85]; +wire [7:0] Q_344 = ITOP.iow0.arr[86]; +wire [7:0] Q_345 = ITOP.iow1.arr[86]; +wire [7:0] Q_346 = ITOP.iow2.arr[86]; +wire [7:0] Q_347 = ITOP.iow3.arr[86]; +wire [7:0] Q_348 = ITOP.iow0.arr[87]; +wire [7:0] Q_349 = ITOP.iow1.arr[87]; +wire [7:0] Q_350 = ITOP.iow2.arr[87]; +wire [7:0] Q_351 = ITOP.iow3.arr[87]; +wire [7:0] Q_352 = ITOP.iow0.arr[88]; +wire [7:0] Q_353 = ITOP.iow1.arr[88]; +wire [7:0] Q_354 = ITOP.iow2.arr[88]; +wire [7:0] Q_355 = ITOP.iow3.arr[88]; +wire [7:0] Q_356 = ITOP.iow0.arr[89]; +wire [7:0] Q_357 = ITOP.iow1.arr[89]; +wire [7:0] Q_358 = ITOP.iow2.arr[89]; +wire [7:0] Q_359 = ITOP.iow3.arr[89]; +wire [7:0] Q_360 = ITOP.iow0.arr[90]; +wire [7:0] Q_361 = ITOP.iow1.arr[90]; +wire [7:0] Q_362 = ITOP.iow2.arr[90]; +wire [7:0] Q_363 = ITOP.iow3.arr[90]; +wire [7:0] Q_364 = ITOP.iow0.arr[91]; +wire [7:0] Q_365 = ITOP.iow1.arr[91]; +wire [7:0] Q_366 = ITOP.iow2.arr[91]; +wire [7:0] Q_367 = ITOP.iow3.arr[91]; +wire [7:0] Q_368 = ITOP.iow0.arr[92]; +wire [7:0] Q_369 = ITOP.iow1.arr[92]; +wire [7:0] Q_370 = ITOP.iow2.arr[92]; +wire [7:0] Q_371 = ITOP.iow3.arr[92]; +wire [7:0] Q_372 = ITOP.iow0.arr[93]; +wire [7:0] Q_373 = ITOP.iow1.arr[93]; +wire [7:0] Q_374 = ITOP.iow2.arr[93]; +wire [7:0] Q_375 = ITOP.iow3.arr[93]; +wire [7:0] Q_376 = ITOP.iow0.arr[94]; +wire [7:0] Q_377 = ITOP.iow1.arr[94]; +wire [7:0] Q_378 = ITOP.iow2.arr[94]; +wire [7:0] Q_379 = ITOP.iow3.arr[94]; +wire [7:0] Q_380 = ITOP.iow0.arr[95]; +wire [7:0] Q_381 = ITOP.iow1.arr[95]; +wire [7:0] Q_382 = ITOP.iow2.arr[95]; +wire [7:0] Q_383 = ITOP.iow3.arr[95]; +wire [7:0] Q_384 = ITOP.iow0.arr[96]; +wire [7:0] Q_385 = ITOP.iow1.arr[96]; +wire [7:0] Q_386 = ITOP.iow2.arr[96]; +wire [7:0] Q_387 = ITOP.iow3.arr[96]; +wire [7:0] Q_388 = ITOP.iow0.arr[97]; +wire [7:0] Q_389 = ITOP.iow1.arr[97]; +wire [7:0] Q_390 = ITOP.iow2.arr[97]; +wire [7:0] Q_391 = ITOP.iow3.arr[97]; +wire [7:0] Q_392 = ITOP.iow0.arr[98]; +wire [7:0] Q_393 = ITOP.iow1.arr[98]; +wire [7:0] Q_394 = ITOP.iow2.arr[98]; +wire [7:0] Q_395 = ITOP.iow3.arr[98]; +wire [7:0] Q_396 = ITOP.iow0.arr[99]; +wire [7:0] Q_397 = ITOP.iow1.arr[99]; +wire [7:0] Q_398 = ITOP.iow2.arr[99]; +wire [7:0] Q_399 = ITOP.iow3.arr[99]; +wire [7:0] Q_400 = ITOP.iow0.arr[100]; +wire [7:0] Q_401 = ITOP.iow1.arr[100]; +wire [7:0] Q_402 = ITOP.iow2.arr[100]; +wire [7:0] Q_403 = ITOP.iow3.arr[100]; +wire [7:0] Q_404 = ITOP.iow0.arr[101]; +wire [7:0] Q_405 = ITOP.iow1.arr[101]; +wire [7:0] Q_406 = ITOP.iow2.arr[101]; +wire [7:0] Q_407 = ITOP.iow3.arr[101]; +wire [7:0] Q_408 = ITOP.iow0.arr[102]; +wire [7:0] Q_409 = ITOP.iow1.arr[102]; +wire [7:0] Q_410 = ITOP.iow2.arr[102]; +wire [7:0] Q_411 = ITOP.iow3.arr[102]; +wire [7:0] Q_412 = ITOP.iow0.arr[103]; +wire [7:0] Q_413 = ITOP.iow1.arr[103]; +wire [7:0] Q_414 = ITOP.iow2.arr[103]; +wire [7:0] Q_415 = ITOP.iow3.arr[103]; +wire [7:0] Q_416 = ITOP.iow0.arr[104]; +wire [7:0] Q_417 = ITOP.iow1.arr[104]; +wire [7:0] Q_418 = ITOP.iow2.arr[104]; +wire [7:0] Q_419 = ITOP.iow3.arr[104]; +wire [7:0] Q_420 = ITOP.iow0.arr[105]; +wire [7:0] Q_421 = ITOP.iow1.arr[105]; +wire [7:0] Q_422 = ITOP.iow2.arr[105]; +wire [7:0] Q_423 = ITOP.iow3.arr[105]; +wire [7:0] Q_424 = ITOP.iow0.arr[106]; +wire [7:0] Q_425 = ITOP.iow1.arr[106]; +wire [7:0] Q_426 = ITOP.iow2.arr[106]; +wire [7:0] Q_427 = ITOP.iow3.arr[106]; +wire [7:0] Q_428 = ITOP.iow0.arr[107]; +wire [7:0] Q_429 = ITOP.iow1.arr[107]; +wire [7:0] Q_430 = ITOP.iow2.arr[107]; +wire [7:0] Q_431 = ITOP.iow3.arr[107]; +wire [7:0] Q_432 = ITOP.iow0.arr[108]; +wire [7:0] Q_433 = ITOP.iow1.arr[108]; +wire [7:0] Q_434 = ITOP.iow2.arr[108]; +wire [7:0] Q_435 = ITOP.iow3.arr[108]; +wire [7:0] Q_436 = ITOP.iow0.arr[109]; +wire [7:0] Q_437 = ITOP.iow1.arr[109]; +wire [7:0] Q_438 = ITOP.iow2.arr[109]; +wire [7:0] Q_439 = ITOP.iow3.arr[109]; +wire [7:0] Q_440 = ITOP.iow0.arr[110]; +wire [7:0] Q_441 = ITOP.iow1.arr[110]; +wire [7:0] Q_442 = ITOP.iow2.arr[110]; +wire [7:0] Q_443 = ITOP.iow3.arr[110]; +wire [7:0] Q_444 = ITOP.iow0.arr[111]; +wire [7:0] Q_445 = ITOP.iow1.arr[111]; +wire [7:0] Q_446 = ITOP.iow2.arr[111]; +wire [7:0] Q_447 = ITOP.iow3.arr[111]; +wire [7:0] Q_448 = ITOP.iow0.arr[112]; +wire [7:0] Q_449 = ITOP.iow1.arr[112]; +wire [7:0] Q_450 = ITOP.iow2.arr[112]; +wire [7:0] Q_451 = ITOP.iow3.arr[112]; +wire [7:0] Q_452 = ITOP.iow0.arr[113]; +wire [7:0] Q_453 = ITOP.iow1.arr[113]; +wire [7:0] Q_454 = ITOP.iow2.arr[113]; +wire [7:0] Q_455 = ITOP.iow3.arr[113]; +wire [7:0] Q_456 = ITOP.iow0.arr[114]; +wire [7:0] Q_457 = ITOP.iow1.arr[114]; +wire [7:0] Q_458 = ITOP.iow2.arr[114]; +wire [7:0] Q_459 = ITOP.iow3.arr[114]; +wire [7:0] Q_460 = ITOP.iow0.arr[115]; +wire [7:0] Q_461 = ITOP.iow1.arr[115]; +wire [7:0] Q_462 = ITOP.iow2.arr[115]; +wire [7:0] Q_463 = ITOP.iow3.arr[115]; +wire [7:0] Q_464 = ITOP.iow0.arr[116]; +wire [7:0] Q_465 = ITOP.iow1.arr[116]; +wire [7:0] Q_466 = ITOP.iow2.arr[116]; +wire [7:0] Q_467 = ITOP.iow3.arr[116]; +wire [7:0] Q_468 = ITOP.iow0.arr[117]; +wire [7:0] Q_469 = ITOP.iow1.arr[117]; +wire [7:0] Q_470 = ITOP.iow2.arr[117]; +wire [7:0] Q_471 = ITOP.iow3.arr[117]; +wire [7:0] Q_472 = ITOP.iow0.arr[118]; +wire [7:0] Q_473 = ITOP.iow1.arr[118]; +wire [7:0] Q_474 = ITOP.iow2.arr[118]; +wire [7:0] Q_475 = ITOP.iow3.arr[118]; +wire [7:0] Q_476 = ITOP.iow0.arr[119]; +wire [7:0] Q_477 = ITOP.iow1.arr[119]; +wire [7:0] Q_478 = ITOP.iow2.arr[119]; +wire [7:0] Q_479 = ITOP.iow3.arr[119]; +wire [7:0] Q_480 = ITOP.iow0.arr[120]; +wire [7:0] Q_481 = ITOP.iow1.arr[120]; +wire [7:0] Q_482 = ITOP.iow2.arr[120]; +wire [7:0] Q_483 = ITOP.iow3.arr[120]; +wire [7:0] Q_484 = ITOP.iow0.arr[121]; +wire [7:0] Q_485 = ITOP.iow1.arr[121]; +wire [7:0] Q_486 = ITOP.iow2.arr[121]; +wire [7:0] Q_487 = ITOP.iow3.arr[121]; +wire [7:0] Q_488 = ITOP.iow0.arr[122]; +wire [7:0] Q_489 = ITOP.iow1.arr[122]; +wire [7:0] Q_490 = ITOP.iow2.arr[122]; +wire [7:0] Q_491 = ITOP.iow3.arr[122]; +wire [7:0] Q_492 = ITOP.iow0.arr[123]; +wire [7:0] Q_493 = ITOP.iow1.arr[123]; +wire [7:0] Q_494 = ITOP.iow2.arr[123]; +wire [7:0] Q_495 = ITOP.iow3.arr[123]; +wire [7:0] Q_496 = ITOP.iow0.arr[124]; +wire [7:0] Q_497 = ITOP.iow1.arr[124]; +wire [7:0] Q_498 = ITOP.iow2.arr[124]; +wire [7:0] Q_499 = ITOP.iow3.arr[124]; +wire [7:0] Q_500 = ITOP.iow0.arr[125]; +wire [7:0] Q_501 = ITOP.iow1.arr[125]; +wire [7:0] Q_502 = ITOP.iow2.arr[125]; +wire [7:0] Q_503 = ITOP.iow3.arr[125]; +wire [7:0] Q_504 = ITOP.iow0.arr[126]; +wire [7:0] Q_505 = ITOP.iow1.arr[126]; +wire [7:0] Q_506 = ITOP.iow2.arr[126]; +wire [7:0] Q_507 = ITOP.iow3.arr[126]; +wire [7:0] Q_508 = ITOP.iow0.arr[127]; +wire [7:0] Q_509 = ITOP.iow1.arr[127]; +wire [7:0] Q_510 = ITOP.iow2.arr[127]; +wire [7:0] Q_511 = ITOP.iow3.arr[127]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [7:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + ITOP.iow2.mem_fault_no_write_subbank(fault_mask); + ITOP.iow3.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [7:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [7:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow2.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow3.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_0_subbank((r/4), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.set_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.set_bit_fault_stuck_1_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_0_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_0_subbank((r/4), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 4) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 2) + ITOP.iow2.clear_bit_fault_stuck_1_subbank((r/4), c); + else if ( (r % 4) == 3) + ITOP.iow3.clear_bit_fault_stuck_1_subbank((r/4), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [8:0] RAFF,WAFF; +// Data + reg [7:0] WD_FF; + reg [7:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [7:0] mem[511:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [7:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [7:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_512X8_GL_M4_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [7:0] WD; +input [8:0] RA, WA; +output [7:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [8:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [8:0] RADRSWI = RADR[8:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [8:0] ADR = {9{RWSEL}} & WAFF | ~{9{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [7:0] WDQ; + wire [7:0] WDBQ; + wire [7:0] WMNexp; + wire [7:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [7:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {8{1'b0}}; + assign SHFT = {8{1'b1}}; + reg [7:0] WDQ_pr; + wire [7:0] WDBQ_pr; + assign WMNexp = {8{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[7:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [7:0] dout; + wire [7:0] RD; + wire RD_rdnt; + wire [7:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [7:0] RDBYPASS = {8{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 2 #cmstep 1 #cm 4 #maxaddr 512 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 512 --> ['1', '1', '1', '1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [7:0] force_x; +`ifndef SYNTHESIS + assign force_x = {8{1'bx}}; +`else + assign force_x = {8{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0, RdClk1, RdClk2, RdClk3; + wire WrClk0, WrClk1, WrClk2, WrClk3; + assign RdClk0 = RECLK & ~RADRSWI[0] & ~RADRSWI[1]; + assign RdClk1 = RECLK & RADRSWI[0] & ~RADRSWI[1]; + assign RdClk2 = RECLK & ~RADRSWI[0] & RADRSWI[1]; + assign RdClk3 = RECLK & RADRSWI[0] & RADRSWI[1]; + assign WrClk0 = WECLK & ~WAFF[0] & ~WAFF[1] & legal; + assign WrClk1 = WECLK & WAFF[0] & ~WAFF[1] & legal; + assign WrClk2 = WECLK & ~WAFF[0] & WAFF[1] & legal; + assign WrClk3 = WECLK & WAFF[0] & WAFF[1] & legal; + wire [7:0] rmuxd0, rmuxd1, rmuxd2, rmuxd3; + wire [7:0] dout0, dout1, dout2, dout3; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {8{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {8{RdClk1}} & ~dout1 : force_x; +// assign rmuxd2 = legal ? {8{RdClk2}} & ~dout2 : force_x; +// assign rmuxd3 = legal ? {8{RdClk3}} & ~dout3 : force_x; + assign rmuxd0 = {8{RdClk0}} & ~dout0; + assign rmuxd1 = {8{RdClk1}} & ~dout1; + assign rmuxd2 = {8{RdClk2}} & ~dout2; + assign rmuxd3 = {8{RdClk3}} & ~dout3; + always @(RECLK or rmuxd0 or rmuxd1 or rmuxd2 or rmuxd3) + begin + if (RECLK) + begin + dout[7:0] <= (rmuxd0[7:0] | rmuxd1[7:0] | rmuxd2[7:0] | rmuxd3[7:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow0 ( + WAFF[8:2], + WrClk0, + WMNQ, + WDQ, + RADRSWI[8:2], + dout0 + ); + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow1 ( + WAFF[8:2], + WrClk1, + WMNQ, + WDQ, + RADRSWI[8:2], + dout1 + ); + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow2 ( + WAFF[8:2], + WrClk2, + WMNQ, + WDQ, + RADRSWI[8:2], + dout2 + ); + RAMPDP_512X8_GL_M4_D2_ram # (128, 8, 7) iow3 ( + WAFF[8:2], + WrClk3, + WMNQ, + WDQ, + RADRSWI[8:2], + dout3 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [8:0] addr; + input [7:0] data; + reg [7:0] wdat; + begin + wdat = data; + if (addr[1:0] == 2'b00) + iow0.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b01) + iow1.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b10) + iow2.mem_wr_raw_subbank(addr[8:2], wdat); + else if (addr[1:0] == 2'b11) + iow3.mem_wr_raw_subbank(addr[8:2], wdat); + end +endtask +// Ramgen function for reading the arrays +function [7:0] mem_read_bank; +input [8:0] addr; +reg [7:0] memout; + begin + if (addr[1:0] == 2'b00) + memout = iow0.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b01) + memout = iow1.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b10) + memout = iow2.mem_read_raw_subbank(addr[8:2]); + else if (addr[1:0] == 2'b11) + memout = iow3.mem_read_raw_subbank(addr[8:2]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_512X8_GL_M4_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 128; +parameter bits = 8; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [167:0] val; + integer i; + begin + for (i=0; i<60; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [167:0] val; + integer i; + begin + val = {168{fill_bit}}; + for (i=0; i<60; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [167:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [167:0] mem_phys_read_padr; +input [5:0] addr; + reg [167:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [167:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=167; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [167:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [167:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [167:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=167; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [167:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [167:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [167:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [167:0] data; + reg [167:0] wr[0:0]; + integer i; + begin + for (i=0; i<=167; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [167:0] mon_bit_w; +input [5:0] addr; + reg [167:0] mon_row; + reg [167:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=167; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [167:0] mon_bit_r; +input [5:0] addr; + reg [167:0] mon_row; + reg [167:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=167; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [167:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=60;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=60;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [167:0] Q_0 = ITOP.iow0.arr[0]; +wire [167:0] Q_1 = ITOP.iow0.arr[1]; +wire [167:0] Q_2 = ITOP.iow0.arr[2]; +wire [167:0] Q_3 = ITOP.iow0.arr[3]; +wire [167:0] Q_4 = ITOP.iow0.arr[4]; +wire [167:0] Q_5 = ITOP.iow0.arr[5]; +wire [167:0] Q_6 = ITOP.iow0.arr[6]; +wire [167:0] Q_7 = ITOP.iow0.arr[7]; +wire [167:0] Q_8 = ITOP.iow0.arr[8]; +wire [167:0] Q_9 = ITOP.iow0.arr[9]; +wire [167:0] Q_10 = ITOP.iow0.arr[10]; +wire [167:0] Q_11 = ITOP.iow0.arr[11]; +wire [167:0] Q_12 = ITOP.iow0.arr[12]; +wire [167:0] Q_13 = ITOP.iow0.arr[13]; +wire [167:0] Q_14 = ITOP.iow0.arr[14]; +wire [167:0] Q_15 = ITOP.iow0.arr[15]; +wire [167:0] Q_16 = ITOP.iow0.arr[16]; +wire [167:0] Q_17 = ITOP.iow0.arr[17]; +wire [167:0] Q_18 = ITOP.iow0.arr[18]; +wire [167:0] Q_19 = ITOP.iow0.arr[19]; +wire [167:0] Q_20 = ITOP.iow0.arr[20]; +wire [167:0] Q_21 = ITOP.iow0.arr[21]; +wire [167:0] Q_22 = ITOP.iow0.arr[22]; +wire [167:0] Q_23 = ITOP.iow0.arr[23]; +wire [167:0] Q_24 = ITOP.iow0.arr[24]; +wire [167:0] Q_25 = ITOP.iow0.arr[25]; +wire [167:0] Q_26 = ITOP.iow0.arr[26]; +wire [167:0] Q_27 = ITOP.iow0.arr[27]; +wire [167:0] Q_28 = ITOP.iow0.arr[28]; +wire [167:0] Q_29 = ITOP.iow0.arr[29]; +wire [167:0] Q_30 = ITOP.iow0.arr[30]; +wire [167:0] Q_31 = ITOP.iow0.arr[31]; +wire [167:0] Q_32 = ITOP.iow0.arr[32]; +wire [167:0] Q_33 = ITOP.iow0.arr[33]; +wire [167:0] Q_34 = ITOP.iow0.arr[34]; +wire [167:0] Q_35 = ITOP.iow0.arr[35]; +wire [167:0] Q_36 = ITOP.iow0.arr[36]; +wire [167:0] Q_37 = ITOP.iow0.arr[37]; +wire [167:0] Q_38 = ITOP.iow0.arr[38]; +wire [167:0] Q_39 = ITOP.iow0.arr[39]; +wire [167:0] Q_40 = ITOP.iow0.arr[40]; +wire [167:0] Q_41 = ITOP.iow0.arr[41]; +wire [167:0] Q_42 = ITOP.iow0.arr[42]; +wire [167:0] Q_43 = ITOP.iow0.arr[43]; +wire [167:0] Q_44 = ITOP.iow0.arr[44]; +wire [167:0] Q_45 = ITOP.iow0.arr[45]; +wire [167:0] Q_46 = ITOP.iow0.arr[46]; +wire [167:0] Q_47 = ITOP.iow0.arr[47]; +wire [167:0] Q_48 = ITOP.iow0.arr[48]; +wire [167:0] Q_49 = ITOP.iow0.arr[49]; +wire [167:0] Q_50 = ITOP.iow0.arr[50]; +wire [167:0] Q_51 = ITOP.iow0.arr[51]; +wire [167:0] Q_52 = ITOP.iow0.arr[52]; +wire [167:0] Q_53 = ITOP.iow0.arr[53]; +wire [167:0] Q_54 = ITOP.iow0.arr[54]; +wire [167:0] Q_55 = ITOP.iow0.arr[55]; +wire [167:0] Q_56 = ITOP.iow0.arr[56]; +wire [167:0] Q_57 = ITOP.iow0.arr[57]; +wire [167:0] Q_58 = ITOP.iow0.arr[58]; +wire [167:0] Q_59 = ITOP.iow0.arr[59]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [167:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [167:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [167:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [167:0] WD_FF; + reg [167:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [167:0] mem[59:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [167:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [167:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_60X168_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [167:0] WD; +input [6:0] RA, WA; +output [167:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [167:0] WDQ; + wire [167:0] WDBQ; + wire [167:0] WMNexp; + wire [167:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [167:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {168{1'b0}}; + assign SHFT = {168{1'b1}}; + reg [167:0] WDQ_pr; + wire [167:0] WDBQ_pr; + assign WMNexp = {168{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[167:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [167:0] dout; + wire [167:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [167:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [167:0] RDBYPASS = {168{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 60 --> ['1', '1', '1', '0', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[5] & ADR[4] & ADR[3] & ADR[2]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [167:0] force_x; +`ifndef SYNTHESIS + assign force_x = {168{1'bx}}; +`else + assign force_x = {168{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [167:0] rmuxd0; + wire [167:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {168{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {168{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[167:0] <= (rmuxd0[167:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_60X168_GL_M1_D2_ram # (60, 168, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [167:0] data; + reg [167:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [167:0] mem_read_bank; +input [5:0] addr; +reg [167:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_60X168_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 60; +parameter bits = 168; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [167:0] val; + integer i; + begin + for (i=0; i<60; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [167:0] val; + integer i; + begin + val = {168{fill_bit}}; + for (i=0; i<60; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [167:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [167:0] mem_phys_read_padr; +input [5:0] addr; + reg [167:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [167:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=167; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [167:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [167:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [167:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=167; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [167:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [167:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [168-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {168 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {168 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [167:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [167:0] data; + reg [167:0] wr[0:0]; + integer i; + begin + for (i=0; i<=167; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [167:0] mon_bit_w; +input [5:0] addr; + reg [167:0] mon_row; + reg [167:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=167; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [167:0] mon_bit_r; +input [5:0] addr; + reg [167:0] mon_row; + reg [167:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=167; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [167:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=60;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=60;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<60; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<168; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [167:0] Q_0 = ITOP.iow0.arr[0]; +wire [167:0] Q_1 = ITOP.iow0.arr[1]; +wire [167:0] Q_2 = ITOP.iow0.arr[2]; +wire [167:0] Q_3 = ITOP.iow0.arr[3]; +wire [167:0] Q_4 = ITOP.iow0.arr[4]; +wire [167:0] Q_5 = ITOP.iow0.arr[5]; +wire [167:0] Q_6 = ITOP.iow0.arr[6]; +wire [167:0] Q_7 = ITOP.iow0.arr[7]; +wire [167:0] Q_8 = ITOP.iow0.arr[8]; +wire [167:0] Q_9 = ITOP.iow0.arr[9]; +wire [167:0] Q_10 = ITOP.iow0.arr[10]; +wire [167:0] Q_11 = ITOP.iow0.arr[11]; +wire [167:0] Q_12 = ITOP.iow0.arr[12]; +wire [167:0] Q_13 = ITOP.iow0.arr[13]; +wire [167:0] Q_14 = ITOP.iow0.arr[14]; +wire [167:0] Q_15 = ITOP.iow0.arr[15]; +wire [167:0] Q_16 = ITOP.iow0.arr[16]; +wire [167:0] Q_17 = ITOP.iow0.arr[17]; +wire [167:0] Q_18 = ITOP.iow0.arr[18]; +wire [167:0] Q_19 = ITOP.iow0.arr[19]; +wire [167:0] Q_20 = ITOP.iow0.arr[20]; +wire [167:0] Q_21 = ITOP.iow0.arr[21]; +wire [167:0] Q_22 = ITOP.iow0.arr[22]; +wire [167:0] Q_23 = ITOP.iow0.arr[23]; +wire [167:0] Q_24 = ITOP.iow0.arr[24]; +wire [167:0] Q_25 = ITOP.iow0.arr[25]; +wire [167:0] Q_26 = ITOP.iow0.arr[26]; +wire [167:0] Q_27 = ITOP.iow0.arr[27]; +wire [167:0] Q_28 = ITOP.iow0.arr[28]; +wire [167:0] Q_29 = ITOP.iow0.arr[29]; +wire [167:0] Q_30 = ITOP.iow0.arr[30]; +wire [167:0] Q_31 = ITOP.iow0.arr[31]; +wire [167:0] Q_32 = ITOP.iow0.arr[32]; +wire [167:0] Q_33 = ITOP.iow0.arr[33]; +wire [167:0] Q_34 = ITOP.iow0.arr[34]; +wire [167:0] Q_35 = ITOP.iow0.arr[35]; +wire [167:0] Q_36 = ITOP.iow0.arr[36]; +wire [167:0] Q_37 = ITOP.iow0.arr[37]; +wire [167:0] Q_38 = ITOP.iow0.arr[38]; +wire [167:0] Q_39 = ITOP.iow0.arr[39]; +wire [167:0] Q_40 = ITOP.iow0.arr[40]; +wire [167:0] Q_41 = ITOP.iow0.arr[41]; +wire [167:0] Q_42 = ITOP.iow0.arr[42]; +wire [167:0] Q_43 = ITOP.iow0.arr[43]; +wire [167:0] Q_44 = ITOP.iow0.arr[44]; +wire [167:0] Q_45 = ITOP.iow0.arr[45]; +wire [167:0] Q_46 = ITOP.iow0.arr[46]; +wire [167:0] Q_47 = ITOP.iow0.arr[47]; +wire [167:0] Q_48 = ITOP.iow0.arr[48]; +wire [167:0] Q_49 = ITOP.iow0.arr[49]; +wire [167:0] Q_50 = ITOP.iow0.arr[50]; +wire [167:0] Q_51 = ITOP.iow0.arr[51]; +wire [167:0] Q_52 = ITOP.iow0.arr[52]; +wire [167:0] Q_53 = ITOP.iow0.arr[53]; +wire [167:0] Q_54 = ITOP.iow0.arr[54]; +wire [167:0] Q_55 = ITOP.iow0.arr[55]; +wire [167:0] Q_56 = ITOP.iow0.arr[56]; +wire [167:0] Q_57 = ITOP.iow0.arr[57]; +wire [167:0] Q_58 = ITOP.iow0.arr[58]; +wire [167:0] Q_59 = ITOP.iow0.arr[59]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [167:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [167:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [167:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [167:0] WD_FF; + reg [167:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [167:0] mem[59:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [167:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [167:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_60X168_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [167:0] WD; +input [6:0] RA, WA; +output [167:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [167:0] WDQ; + wire [167:0] WDBQ; + wire [167:0] WMNexp; + wire [167:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [167:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {168{1'b0}}; + assign SHFT = {168{1'b1}}; + reg [167:0] WDQ_pr; + wire [167:0] WDBQ_pr; + assign WMNexp = {168{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[167:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [167:0] dout; + wire [167:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [167:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [167:0] RDBYPASS = {168{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 60 --> ['1', '1', '1', '0', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[5] & ADR[4] & ADR[3] & ADR[2]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [167:0] force_x; +`ifndef SYNTHESIS + assign force_x = {168{1'bx}}; +`else + assign force_x = {168{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [167:0] rmuxd0; + wire [167:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {168{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {168{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[167:0] <= (rmuxd0[167:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_60X168_GL_M1_D2_ram # (60, 168, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [167:0] data; + reg [167:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [167:0] mem_read_bank; +input [5:0] addr; +reg [167:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_60X168_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 60; +parameter bits = 168; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [115:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [115:0] val; + integer i; + begin + val = {116{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [115:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [115:0] mem_phys_read_padr; +input [5:0] addr; + reg [115:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [115:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=115; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [115:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [115:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [115:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=115; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [115:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [115:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [115:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [115:0] data; + reg [115:0] wr[0:0]; + integer i; + begin + for (i=0; i<=115; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [115:0] mon_bit_w; +input [5:0] addr; + reg [115:0] mon_row; + reg [115:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=115; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [115:0] mon_bit_r; +input [5:0] addr; + reg [115:0] mon_row; + reg [115:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=115; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [115:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [115:0] Q_0 = ITOP.iow0.arr[0]; +wire [115:0] Q_1 = ITOP.iow0.arr[1]; +wire [115:0] Q_2 = ITOP.iow0.arr[2]; +wire [115:0] Q_3 = ITOP.iow0.arr[3]; +wire [115:0] Q_4 = ITOP.iow0.arr[4]; +wire [115:0] Q_5 = ITOP.iow0.arr[5]; +wire [115:0] Q_6 = ITOP.iow0.arr[6]; +wire [115:0] Q_7 = ITOP.iow0.arr[7]; +wire [115:0] Q_8 = ITOP.iow0.arr[8]; +wire [115:0] Q_9 = ITOP.iow0.arr[9]; +wire [115:0] Q_10 = ITOP.iow0.arr[10]; +wire [115:0] Q_11 = ITOP.iow0.arr[11]; +wire [115:0] Q_12 = ITOP.iow0.arr[12]; +wire [115:0] Q_13 = ITOP.iow0.arr[13]; +wire [115:0] Q_14 = ITOP.iow0.arr[14]; +wire [115:0] Q_15 = ITOP.iow0.arr[15]; +wire [115:0] Q_16 = ITOP.iow0.arr[16]; +wire [115:0] Q_17 = ITOP.iow0.arr[17]; +wire [115:0] Q_18 = ITOP.iow0.arr[18]; +wire [115:0] Q_19 = ITOP.iow0.arr[19]; +wire [115:0] Q_20 = ITOP.iow0.arr[20]; +wire [115:0] Q_21 = ITOP.iow0.arr[21]; +wire [115:0] Q_22 = ITOP.iow0.arr[22]; +wire [115:0] Q_23 = ITOP.iow0.arr[23]; +wire [115:0] Q_24 = ITOP.iow0.arr[24]; +wire [115:0] Q_25 = ITOP.iow0.arr[25]; +wire [115:0] Q_26 = ITOP.iow0.arr[26]; +wire [115:0] Q_27 = ITOP.iow0.arr[27]; +wire [115:0] Q_28 = ITOP.iow0.arr[28]; +wire [115:0] Q_29 = ITOP.iow0.arr[29]; +wire [115:0] Q_30 = ITOP.iow0.arr[30]; +wire [115:0] Q_31 = ITOP.iow0.arr[31]; +wire [115:0] Q_32 = ITOP.iow0.arr[32]; +wire [115:0] Q_33 = ITOP.iow0.arr[33]; +wire [115:0] Q_34 = ITOP.iow0.arr[34]; +wire [115:0] Q_35 = ITOP.iow0.arr[35]; +wire [115:0] Q_36 = ITOP.iow0.arr[36]; +wire [115:0] Q_37 = ITOP.iow0.arr[37]; +wire [115:0] Q_38 = ITOP.iow0.arr[38]; +wire [115:0] Q_39 = ITOP.iow0.arr[39]; +wire [115:0] Q_40 = ITOP.iow0.arr[40]; +wire [115:0] Q_41 = ITOP.iow0.arr[41]; +wire [115:0] Q_42 = ITOP.iow0.arr[42]; +wire [115:0] Q_43 = ITOP.iow0.arr[43]; +wire [115:0] Q_44 = ITOP.iow0.arr[44]; +wire [115:0] Q_45 = ITOP.iow0.arr[45]; +wire [115:0] Q_46 = ITOP.iow0.arr[46]; +wire [115:0] Q_47 = ITOP.iow0.arr[47]; +wire [115:0] Q_48 = ITOP.iow0.arr[48]; +wire [115:0] Q_49 = ITOP.iow0.arr[49]; +wire [115:0] Q_50 = ITOP.iow0.arr[50]; +wire [115:0] Q_51 = ITOP.iow0.arr[51]; +wire [115:0] Q_52 = ITOP.iow0.arr[52]; +wire [115:0] Q_53 = ITOP.iow0.arr[53]; +wire [115:0] Q_54 = ITOP.iow0.arr[54]; +wire [115:0] Q_55 = ITOP.iow0.arr[55]; +wire [115:0] Q_56 = ITOP.iow0.arr[56]; +wire [115:0] Q_57 = ITOP.iow0.arr[57]; +wire [115:0] Q_58 = ITOP.iow0.arr[58]; +wire [115:0] Q_59 = ITOP.iow0.arr[59]; +wire [115:0] Q_60 = ITOP.iow0.arr[60]; +wire [115:0] Q_61 = ITOP.iow0.arr[61]; +wire [115:0] Q_62 = ITOP.iow0.arr[62]; +wire [115:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [115:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [115:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [115:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [115:0] WD_FF; + reg [115:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [115:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [115:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [115:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X116_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [115:0] WD; +input [6:0] RA, WA; +output [115:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [115:0] WDQ; + wire [115:0] WDBQ; + wire [115:0] WMNexp; + wire [115:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [115:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {116{1'b0}}; + assign SHFT = {116{1'b1}}; + reg [115:0] WDQ_pr; + wire [115:0] WDBQ_pr; + assign WMNexp = {116{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[115:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [115:0] dout; + wire [115:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [115:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [115:0] RDBYPASS = {116{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [115:0] force_x; +`ifndef SYNTHESIS + assign force_x = {116{1'bx}}; +`else + assign force_x = {116{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [115:0] rmuxd0; + wire [115:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {116{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {116{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[115:0] <= (rmuxd0[115:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X116_GL_M1_D2_ram # (64, 116, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [115:0] data; + reg [115:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [115:0] mem_read_bank; +input [5:0] addr; +reg [115:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X116_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 116; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [115:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [115:0] val; + integer i; + begin + val = {116{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [115:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [115:0] mem_phys_read_padr; +input [5:0] addr; + reg [115:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [115:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=115; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [115:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [115:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [115:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=115; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [115:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [115:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [116-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {116 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{20{1'b1}}) } `endif ; + else raminit_fullval = {116 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [115:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [115:0] data; + reg [115:0] wr[0:0]; + integer i; + begin + for (i=0; i<=115; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [115:0] mon_bit_w; +input [5:0] addr; + reg [115:0] mon_row; + reg [115:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=115; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [115:0] mon_bit_r; +input [5:0] addr; + reg [115:0] mon_row; + reg [115:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=115; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [115:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<116; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [115:0] Q_0 = ITOP.iow0.arr[0]; +wire [115:0] Q_1 = ITOP.iow0.arr[1]; +wire [115:0] Q_2 = ITOP.iow0.arr[2]; +wire [115:0] Q_3 = ITOP.iow0.arr[3]; +wire [115:0] Q_4 = ITOP.iow0.arr[4]; +wire [115:0] Q_5 = ITOP.iow0.arr[5]; +wire [115:0] Q_6 = ITOP.iow0.arr[6]; +wire [115:0] Q_7 = ITOP.iow0.arr[7]; +wire [115:0] Q_8 = ITOP.iow0.arr[8]; +wire [115:0] Q_9 = ITOP.iow0.arr[9]; +wire [115:0] Q_10 = ITOP.iow0.arr[10]; +wire [115:0] Q_11 = ITOP.iow0.arr[11]; +wire [115:0] Q_12 = ITOP.iow0.arr[12]; +wire [115:0] Q_13 = ITOP.iow0.arr[13]; +wire [115:0] Q_14 = ITOP.iow0.arr[14]; +wire [115:0] Q_15 = ITOP.iow0.arr[15]; +wire [115:0] Q_16 = ITOP.iow0.arr[16]; +wire [115:0] Q_17 = ITOP.iow0.arr[17]; +wire [115:0] Q_18 = ITOP.iow0.arr[18]; +wire [115:0] Q_19 = ITOP.iow0.arr[19]; +wire [115:0] Q_20 = ITOP.iow0.arr[20]; +wire [115:0] Q_21 = ITOP.iow0.arr[21]; +wire [115:0] Q_22 = ITOP.iow0.arr[22]; +wire [115:0] Q_23 = ITOP.iow0.arr[23]; +wire [115:0] Q_24 = ITOP.iow0.arr[24]; +wire [115:0] Q_25 = ITOP.iow0.arr[25]; +wire [115:0] Q_26 = ITOP.iow0.arr[26]; +wire [115:0] Q_27 = ITOP.iow0.arr[27]; +wire [115:0] Q_28 = ITOP.iow0.arr[28]; +wire [115:0] Q_29 = ITOP.iow0.arr[29]; +wire [115:0] Q_30 = ITOP.iow0.arr[30]; +wire [115:0] Q_31 = ITOP.iow0.arr[31]; +wire [115:0] Q_32 = ITOP.iow0.arr[32]; +wire [115:0] Q_33 = ITOP.iow0.arr[33]; +wire [115:0] Q_34 = ITOP.iow0.arr[34]; +wire [115:0] Q_35 = ITOP.iow0.arr[35]; +wire [115:0] Q_36 = ITOP.iow0.arr[36]; +wire [115:0] Q_37 = ITOP.iow0.arr[37]; +wire [115:0] Q_38 = ITOP.iow0.arr[38]; +wire [115:0] Q_39 = ITOP.iow0.arr[39]; +wire [115:0] Q_40 = ITOP.iow0.arr[40]; +wire [115:0] Q_41 = ITOP.iow0.arr[41]; +wire [115:0] Q_42 = ITOP.iow0.arr[42]; +wire [115:0] Q_43 = ITOP.iow0.arr[43]; +wire [115:0] Q_44 = ITOP.iow0.arr[44]; +wire [115:0] Q_45 = ITOP.iow0.arr[45]; +wire [115:0] Q_46 = ITOP.iow0.arr[46]; +wire [115:0] Q_47 = ITOP.iow0.arr[47]; +wire [115:0] Q_48 = ITOP.iow0.arr[48]; +wire [115:0] Q_49 = ITOP.iow0.arr[49]; +wire [115:0] Q_50 = ITOP.iow0.arr[50]; +wire [115:0] Q_51 = ITOP.iow0.arr[51]; +wire [115:0] Q_52 = ITOP.iow0.arr[52]; +wire [115:0] Q_53 = ITOP.iow0.arr[53]; +wire [115:0] Q_54 = ITOP.iow0.arr[54]; +wire [115:0] Q_55 = ITOP.iow0.arr[55]; +wire [115:0] Q_56 = ITOP.iow0.arr[56]; +wire [115:0] Q_57 = ITOP.iow0.arr[57]; +wire [115:0] Q_58 = ITOP.iow0.arr[58]; +wire [115:0] Q_59 = ITOP.iow0.arr[59]; +wire [115:0] Q_60 = ITOP.iow0.arr[60]; +wire [115:0] Q_61 = ITOP.iow0.arr[61]; +wire [115:0] Q_62 = ITOP.iow0.arr[62]; +wire [115:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [115:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [115:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [115:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [115:0] WD_FF; + reg [115:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [115:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [115:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [115:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X116_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [115:0] WD; +input [6:0] RA, WA; +output [115:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [115:0] WDQ; + wire [115:0] WDBQ; + wire [115:0] WMNexp; + wire [115:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [115:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {116{1'b0}}; + assign SHFT = {116{1'b1}}; + reg [115:0] WDQ_pr; + wire [115:0] WDBQ_pr; + assign WMNexp = {116{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[115:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [115:0] dout; + wire [115:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [115:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [115:0] RDBYPASS = {116{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [115:0] force_x; +`ifndef SYNTHESIS + assign force_x = {116{1'bx}}; +`else + assign force_x = {116{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [115:0] rmuxd0; + wire [115:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {116{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {116{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[115:0] <= (rmuxd0[115:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X116_GL_M1_D2_ram # (64, 116, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [115:0] data; + reg [115:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [115:0] mem_read_bank; +input [5:0] addr; +reg [115:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X116_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 116; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [159:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [159:0] val; + integer i; + begin + val = {160{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [159:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [159:0] mem_phys_read_padr; +input [5:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [159:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=159; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [159:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [159:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=159; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [159:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [159:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [159:0] data; + reg [159:0] wr[0:0]; + integer i; + begin + for (i=0; i<=159; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [159:0] mon_bit_w; +input [5:0] addr; + reg [159:0] mon_row; + reg [159:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=159; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [159:0] mon_bit_r; +input [5:0] addr; + reg [159:0] mon_row; + reg [159:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=159; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [159:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [159:0] Q_0 = ITOP.iow0.arr[0]; +wire [159:0] Q_1 = ITOP.iow0.arr[1]; +wire [159:0] Q_2 = ITOP.iow0.arr[2]; +wire [159:0] Q_3 = ITOP.iow0.arr[3]; +wire [159:0] Q_4 = ITOP.iow0.arr[4]; +wire [159:0] Q_5 = ITOP.iow0.arr[5]; +wire [159:0] Q_6 = ITOP.iow0.arr[6]; +wire [159:0] Q_7 = ITOP.iow0.arr[7]; +wire [159:0] Q_8 = ITOP.iow0.arr[8]; +wire [159:0] Q_9 = ITOP.iow0.arr[9]; +wire [159:0] Q_10 = ITOP.iow0.arr[10]; +wire [159:0] Q_11 = ITOP.iow0.arr[11]; +wire [159:0] Q_12 = ITOP.iow0.arr[12]; +wire [159:0] Q_13 = ITOP.iow0.arr[13]; +wire [159:0] Q_14 = ITOP.iow0.arr[14]; +wire [159:0] Q_15 = ITOP.iow0.arr[15]; +wire [159:0] Q_16 = ITOP.iow0.arr[16]; +wire [159:0] Q_17 = ITOP.iow0.arr[17]; +wire [159:0] Q_18 = ITOP.iow0.arr[18]; +wire [159:0] Q_19 = ITOP.iow0.arr[19]; +wire [159:0] Q_20 = ITOP.iow0.arr[20]; +wire [159:0] Q_21 = ITOP.iow0.arr[21]; +wire [159:0] Q_22 = ITOP.iow0.arr[22]; +wire [159:0] Q_23 = ITOP.iow0.arr[23]; +wire [159:0] Q_24 = ITOP.iow0.arr[24]; +wire [159:0] Q_25 = ITOP.iow0.arr[25]; +wire [159:0] Q_26 = ITOP.iow0.arr[26]; +wire [159:0] Q_27 = ITOP.iow0.arr[27]; +wire [159:0] Q_28 = ITOP.iow0.arr[28]; +wire [159:0] Q_29 = ITOP.iow0.arr[29]; +wire [159:0] Q_30 = ITOP.iow0.arr[30]; +wire [159:0] Q_31 = ITOP.iow0.arr[31]; +wire [159:0] Q_32 = ITOP.iow0.arr[32]; +wire [159:0] Q_33 = ITOP.iow0.arr[33]; +wire [159:0] Q_34 = ITOP.iow0.arr[34]; +wire [159:0] Q_35 = ITOP.iow0.arr[35]; +wire [159:0] Q_36 = ITOP.iow0.arr[36]; +wire [159:0] Q_37 = ITOP.iow0.arr[37]; +wire [159:0] Q_38 = ITOP.iow0.arr[38]; +wire [159:0] Q_39 = ITOP.iow0.arr[39]; +wire [159:0] Q_40 = ITOP.iow0.arr[40]; +wire [159:0] Q_41 = ITOP.iow0.arr[41]; +wire [159:0] Q_42 = ITOP.iow0.arr[42]; +wire [159:0] Q_43 = ITOP.iow0.arr[43]; +wire [159:0] Q_44 = ITOP.iow0.arr[44]; +wire [159:0] Q_45 = ITOP.iow0.arr[45]; +wire [159:0] Q_46 = ITOP.iow0.arr[46]; +wire [159:0] Q_47 = ITOP.iow0.arr[47]; +wire [159:0] Q_48 = ITOP.iow0.arr[48]; +wire [159:0] Q_49 = ITOP.iow0.arr[49]; +wire [159:0] Q_50 = ITOP.iow0.arr[50]; +wire [159:0] Q_51 = ITOP.iow0.arr[51]; +wire [159:0] Q_52 = ITOP.iow0.arr[52]; +wire [159:0] Q_53 = ITOP.iow0.arr[53]; +wire [159:0] Q_54 = ITOP.iow0.arr[54]; +wire [159:0] Q_55 = ITOP.iow0.arr[55]; +wire [159:0] Q_56 = ITOP.iow0.arr[56]; +wire [159:0] Q_57 = ITOP.iow0.arr[57]; +wire [159:0] Q_58 = ITOP.iow0.arr[58]; +wire [159:0] Q_59 = ITOP.iow0.arr[59]; +wire [159:0] Q_60 = ITOP.iow0.arr[60]; +wire [159:0] Q_61 = ITOP.iow0.arr[61]; +wire [159:0] Q_62 = ITOP.iow0.arr[62]; +wire [159:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [159:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [159:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [159:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [159:0] WD_FF; + reg [159:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [159:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [159:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [159:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X160_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [159:0] WD; +input [6:0] RA, WA; +output [159:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [159:0] WDQ; + wire [159:0] WDBQ; + wire [159:0] WMNexp; + wire [159:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [159:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {160{1'b0}}; + assign SHFT = {160{1'b1}}; + reg [159:0] WDQ_pr; + wire [159:0] WDBQ_pr; + assign WMNexp = {160{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[159:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [159:0] dout; + wire [159:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [159:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [159:0] RDBYPASS = {160{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [159:0] force_x; +`ifndef SYNTHESIS + assign force_x = {160{1'bx}}; +`else + assign force_x = {160{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [159:0] rmuxd0; + wire [159:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {160{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {160{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[159:0] <= (rmuxd0[159:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X160_GL_M1_D2_ram # (64, 160, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [159:0] data; + reg [159:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [159:0] mem_read_bank; +input [5:0] addr; +reg [159:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X160_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 160; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [159:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [159:0] val; + integer i; + begin + val = {160{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [159:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [159:0] mem_phys_read_padr; +input [5:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [159:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=159; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [159:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [159:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=159; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [159:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [159:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [160-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {160 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {160 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [159:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [159:0] data; + reg [159:0] wr[0:0]; + integer i; + begin + for (i=0; i<=159; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [159:0] mon_bit_w; +input [5:0] addr; + reg [159:0] mon_row; + reg [159:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=159; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [159:0] mon_bit_r; +input [5:0] addr; + reg [159:0] mon_row; + reg [159:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=159; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [159:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<160; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [159:0] Q_0 = ITOP.iow0.arr[0]; +wire [159:0] Q_1 = ITOP.iow0.arr[1]; +wire [159:0] Q_2 = ITOP.iow0.arr[2]; +wire [159:0] Q_3 = ITOP.iow0.arr[3]; +wire [159:0] Q_4 = ITOP.iow0.arr[4]; +wire [159:0] Q_5 = ITOP.iow0.arr[5]; +wire [159:0] Q_6 = ITOP.iow0.arr[6]; +wire [159:0] Q_7 = ITOP.iow0.arr[7]; +wire [159:0] Q_8 = ITOP.iow0.arr[8]; +wire [159:0] Q_9 = ITOP.iow0.arr[9]; +wire [159:0] Q_10 = ITOP.iow0.arr[10]; +wire [159:0] Q_11 = ITOP.iow0.arr[11]; +wire [159:0] Q_12 = ITOP.iow0.arr[12]; +wire [159:0] Q_13 = ITOP.iow0.arr[13]; +wire [159:0] Q_14 = ITOP.iow0.arr[14]; +wire [159:0] Q_15 = ITOP.iow0.arr[15]; +wire [159:0] Q_16 = ITOP.iow0.arr[16]; +wire [159:0] Q_17 = ITOP.iow0.arr[17]; +wire [159:0] Q_18 = ITOP.iow0.arr[18]; +wire [159:0] Q_19 = ITOP.iow0.arr[19]; +wire [159:0] Q_20 = ITOP.iow0.arr[20]; +wire [159:0] Q_21 = ITOP.iow0.arr[21]; +wire [159:0] Q_22 = ITOP.iow0.arr[22]; +wire [159:0] Q_23 = ITOP.iow0.arr[23]; +wire [159:0] Q_24 = ITOP.iow0.arr[24]; +wire [159:0] Q_25 = ITOP.iow0.arr[25]; +wire [159:0] Q_26 = ITOP.iow0.arr[26]; +wire [159:0] Q_27 = ITOP.iow0.arr[27]; +wire [159:0] Q_28 = ITOP.iow0.arr[28]; +wire [159:0] Q_29 = ITOP.iow0.arr[29]; +wire [159:0] Q_30 = ITOP.iow0.arr[30]; +wire [159:0] Q_31 = ITOP.iow0.arr[31]; +wire [159:0] Q_32 = ITOP.iow0.arr[32]; +wire [159:0] Q_33 = ITOP.iow0.arr[33]; +wire [159:0] Q_34 = ITOP.iow0.arr[34]; +wire [159:0] Q_35 = ITOP.iow0.arr[35]; +wire [159:0] Q_36 = ITOP.iow0.arr[36]; +wire [159:0] Q_37 = ITOP.iow0.arr[37]; +wire [159:0] Q_38 = ITOP.iow0.arr[38]; +wire [159:0] Q_39 = ITOP.iow0.arr[39]; +wire [159:0] Q_40 = ITOP.iow0.arr[40]; +wire [159:0] Q_41 = ITOP.iow0.arr[41]; +wire [159:0] Q_42 = ITOP.iow0.arr[42]; +wire [159:0] Q_43 = ITOP.iow0.arr[43]; +wire [159:0] Q_44 = ITOP.iow0.arr[44]; +wire [159:0] Q_45 = ITOP.iow0.arr[45]; +wire [159:0] Q_46 = ITOP.iow0.arr[46]; +wire [159:0] Q_47 = ITOP.iow0.arr[47]; +wire [159:0] Q_48 = ITOP.iow0.arr[48]; +wire [159:0] Q_49 = ITOP.iow0.arr[49]; +wire [159:0] Q_50 = ITOP.iow0.arr[50]; +wire [159:0] Q_51 = ITOP.iow0.arr[51]; +wire [159:0] Q_52 = ITOP.iow0.arr[52]; +wire [159:0] Q_53 = ITOP.iow0.arr[53]; +wire [159:0] Q_54 = ITOP.iow0.arr[54]; +wire [159:0] Q_55 = ITOP.iow0.arr[55]; +wire [159:0] Q_56 = ITOP.iow0.arr[56]; +wire [159:0] Q_57 = ITOP.iow0.arr[57]; +wire [159:0] Q_58 = ITOP.iow0.arr[58]; +wire [159:0] Q_59 = ITOP.iow0.arr[59]; +wire [159:0] Q_60 = ITOP.iow0.arr[60]; +wire [159:0] Q_61 = ITOP.iow0.arr[61]; +wire [159:0] Q_62 = ITOP.iow0.arr[62]; +wire [159:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [159:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [159:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [159:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [159:0] WD_FF; + reg [159:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [159:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [159:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [159:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X160_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [159:0] WD; +input [6:0] RA, WA; +output [159:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [159:0] WDQ; + wire [159:0] WDBQ; + wire [159:0] WMNexp; + wire [159:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [159:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {160{1'b0}}; + assign SHFT = {160{1'b1}}; + reg [159:0] WDQ_pr; + wire [159:0] WDBQ_pr; + assign WMNexp = {160{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[159:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [159:0] dout; + wire [159:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [159:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [159:0] RDBYPASS = {160{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [159:0] force_x; +`ifndef SYNTHESIS + assign force_x = {160{1'bx}}; +`else + assign force_x = {160{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [159:0] rmuxd0; + wire [159:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {160{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {160{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[159:0] <= (rmuxd0[159:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X160_GL_M1_D2_ram # (64, 160, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [159:0] data; + reg [159:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [159:0] mem_read_bank; +input [5:0] addr; +reg [159:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X160_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 160; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [223:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [223:0] val; + integer i; + begin + val = {224{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [223:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [223:0] mem_phys_read_padr; +input [5:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [223:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [223:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [223:0] data; + reg [223:0] wr[0:0]; + integer i; + begin + for (i=0; i<=223; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [223:0] mon_bit_w; +input [5:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [223:0] mon_bit_r; +input [5:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [223:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [223:0] Q_0 = ITOP.iow0.arr[0]; +wire [223:0] Q_1 = ITOP.iow0.arr[1]; +wire [223:0] Q_2 = ITOP.iow0.arr[2]; +wire [223:0] Q_3 = ITOP.iow0.arr[3]; +wire [223:0] Q_4 = ITOP.iow0.arr[4]; +wire [223:0] Q_5 = ITOP.iow0.arr[5]; +wire [223:0] Q_6 = ITOP.iow0.arr[6]; +wire [223:0] Q_7 = ITOP.iow0.arr[7]; +wire [223:0] Q_8 = ITOP.iow0.arr[8]; +wire [223:0] Q_9 = ITOP.iow0.arr[9]; +wire [223:0] Q_10 = ITOP.iow0.arr[10]; +wire [223:0] Q_11 = ITOP.iow0.arr[11]; +wire [223:0] Q_12 = ITOP.iow0.arr[12]; +wire [223:0] Q_13 = ITOP.iow0.arr[13]; +wire [223:0] Q_14 = ITOP.iow0.arr[14]; +wire [223:0] Q_15 = ITOP.iow0.arr[15]; +wire [223:0] Q_16 = ITOP.iow0.arr[16]; +wire [223:0] Q_17 = ITOP.iow0.arr[17]; +wire [223:0] Q_18 = ITOP.iow0.arr[18]; +wire [223:0] Q_19 = ITOP.iow0.arr[19]; +wire [223:0] Q_20 = ITOP.iow0.arr[20]; +wire [223:0] Q_21 = ITOP.iow0.arr[21]; +wire [223:0] Q_22 = ITOP.iow0.arr[22]; +wire [223:0] Q_23 = ITOP.iow0.arr[23]; +wire [223:0] Q_24 = ITOP.iow0.arr[24]; +wire [223:0] Q_25 = ITOP.iow0.arr[25]; +wire [223:0] Q_26 = ITOP.iow0.arr[26]; +wire [223:0] Q_27 = ITOP.iow0.arr[27]; +wire [223:0] Q_28 = ITOP.iow0.arr[28]; +wire [223:0] Q_29 = ITOP.iow0.arr[29]; +wire [223:0] Q_30 = ITOP.iow0.arr[30]; +wire [223:0] Q_31 = ITOP.iow0.arr[31]; +wire [223:0] Q_32 = ITOP.iow0.arr[32]; +wire [223:0] Q_33 = ITOP.iow0.arr[33]; +wire [223:0] Q_34 = ITOP.iow0.arr[34]; +wire [223:0] Q_35 = ITOP.iow0.arr[35]; +wire [223:0] Q_36 = ITOP.iow0.arr[36]; +wire [223:0] Q_37 = ITOP.iow0.arr[37]; +wire [223:0] Q_38 = ITOP.iow0.arr[38]; +wire [223:0] Q_39 = ITOP.iow0.arr[39]; +wire [223:0] Q_40 = ITOP.iow0.arr[40]; +wire [223:0] Q_41 = ITOP.iow0.arr[41]; +wire [223:0] Q_42 = ITOP.iow0.arr[42]; +wire [223:0] Q_43 = ITOP.iow0.arr[43]; +wire [223:0] Q_44 = ITOP.iow0.arr[44]; +wire [223:0] Q_45 = ITOP.iow0.arr[45]; +wire [223:0] Q_46 = ITOP.iow0.arr[46]; +wire [223:0] Q_47 = ITOP.iow0.arr[47]; +wire [223:0] Q_48 = ITOP.iow0.arr[48]; +wire [223:0] Q_49 = ITOP.iow0.arr[49]; +wire [223:0] Q_50 = ITOP.iow0.arr[50]; +wire [223:0] Q_51 = ITOP.iow0.arr[51]; +wire [223:0] Q_52 = ITOP.iow0.arr[52]; +wire [223:0] Q_53 = ITOP.iow0.arr[53]; +wire [223:0] Q_54 = ITOP.iow0.arr[54]; +wire [223:0] Q_55 = ITOP.iow0.arr[55]; +wire [223:0] Q_56 = ITOP.iow0.arr[56]; +wire [223:0] Q_57 = ITOP.iow0.arr[57]; +wire [223:0] Q_58 = ITOP.iow0.arr[58]; +wire [223:0] Q_59 = ITOP.iow0.arr[59]; +wire [223:0] Q_60 = ITOP.iow0.arr[60]; +wire [223:0] Q_61 = ITOP.iow0.arr[61]; +wire [223:0] Q_62 = ITOP.iow0.arr[62]; +wire [223:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [223:0] WD_FF; + reg [223:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [223:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [223:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [223:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X224_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [223:0] WD; +input [6:0] RA, WA; +output [223:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [223:0] WDQ; + wire [223:0] WDBQ; + wire [223:0] WMNexp; + wire [223:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [223:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {224{1'b0}}; + assign SHFT = {224{1'b1}}; + reg [223:0] WDQ_pr; + wire [223:0] WDBQ_pr; + assign WMNexp = {224{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[223:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [223:0] dout; + wire [223:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [223:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [223:0] RDBYPASS = {224{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [223:0] force_x; +`ifndef SYNTHESIS + assign force_x = {224{1'bx}}; +`else + assign force_x = {224{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [223:0] rmuxd0; + wire [223:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {224{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {224{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[223:0] <= (rmuxd0[223:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X224_GL_M1_D2_ram # (64, 224, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [223:0] data; + reg [223:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [223:0] mem_read_bank; +input [5:0] addr; +reg [223:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X224_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 224; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [223:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [223:0] val; + integer i; + begin + val = {224{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [223:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [223:0] mem_phys_read_padr; +input [5:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [223:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=223; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [223:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [223:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [224-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {224 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {224 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [223:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [223:0] data; + reg [223:0] wr[0:0]; + integer i; + begin + for (i=0; i<=223; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [223:0] mon_bit_w; +input [5:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [223:0] mon_bit_r; +input [5:0] addr; + reg [223:0] mon_row; + reg [223:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=223; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [223:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<224; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [223:0] Q_0 = ITOP.iow0.arr[0]; +wire [223:0] Q_1 = ITOP.iow0.arr[1]; +wire [223:0] Q_2 = ITOP.iow0.arr[2]; +wire [223:0] Q_3 = ITOP.iow0.arr[3]; +wire [223:0] Q_4 = ITOP.iow0.arr[4]; +wire [223:0] Q_5 = ITOP.iow0.arr[5]; +wire [223:0] Q_6 = ITOP.iow0.arr[6]; +wire [223:0] Q_7 = ITOP.iow0.arr[7]; +wire [223:0] Q_8 = ITOP.iow0.arr[8]; +wire [223:0] Q_9 = ITOP.iow0.arr[9]; +wire [223:0] Q_10 = ITOP.iow0.arr[10]; +wire [223:0] Q_11 = ITOP.iow0.arr[11]; +wire [223:0] Q_12 = ITOP.iow0.arr[12]; +wire [223:0] Q_13 = ITOP.iow0.arr[13]; +wire [223:0] Q_14 = ITOP.iow0.arr[14]; +wire [223:0] Q_15 = ITOP.iow0.arr[15]; +wire [223:0] Q_16 = ITOP.iow0.arr[16]; +wire [223:0] Q_17 = ITOP.iow0.arr[17]; +wire [223:0] Q_18 = ITOP.iow0.arr[18]; +wire [223:0] Q_19 = ITOP.iow0.arr[19]; +wire [223:0] Q_20 = ITOP.iow0.arr[20]; +wire [223:0] Q_21 = ITOP.iow0.arr[21]; +wire [223:0] Q_22 = ITOP.iow0.arr[22]; +wire [223:0] Q_23 = ITOP.iow0.arr[23]; +wire [223:0] Q_24 = ITOP.iow0.arr[24]; +wire [223:0] Q_25 = ITOP.iow0.arr[25]; +wire [223:0] Q_26 = ITOP.iow0.arr[26]; +wire [223:0] Q_27 = ITOP.iow0.arr[27]; +wire [223:0] Q_28 = ITOP.iow0.arr[28]; +wire [223:0] Q_29 = ITOP.iow0.arr[29]; +wire [223:0] Q_30 = ITOP.iow0.arr[30]; +wire [223:0] Q_31 = ITOP.iow0.arr[31]; +wire [223:0] Q_32 = ITOP.iow0.arr[32]; +wire [223:0] Q_33 = ITOP.iow0.arr[33]; +wire [223:0] Q_34 = ITOP.iow0.arr[34]; +wire [223:0] Q_35 = ITOP.iow0.arr[35]; +wire [223:0] Q_36 = ITOP.iow0.arr[36]; +wire [223:0] Q_37 = ITOP.iow0.arr[37]; +wire [223:0] Q_38 = ITOP.iow0.arr[38]; +wire [223:0] Q_39 = ITOP.iow0.arr[39]; +wire [223:0] Q_40 = ITOP.iow0.arr[40]; +wire [223:0] Q_41 = ITOP.iow0.arr[41]; +wire [223:0] Q_42 = ITOP.iow0.arr[42]; +wire [223:0] Q_43 = ITOP.iow0.arr[43]; +wire [223:0] Q_44 = ITOP.iow0.arr[44]; +wire [223:0] Q_45 = ITOP.iow0.arr[45]; +wire [223:0] Q_46 = ITOP.iow0.arr[46]; +wire [223:0] Q_47 = ITOP.iow0.arr[47]; +wire [223:0] Q_48 = ITOP.iow0.arr[48]; +wire [223:0] Q_49 = ITOP.iow0.arr[49]; +wire [223:0] Q_50 = ITOP.iow0.arr[50]; +wire [223:0] Q_51 = ITOP.iow0.arr[51]; +wire [223:0] Q_52 = ITOP.iow0.arr[52]; +wire [223:0] Q_53 = ITOP.iow0.arr[53]; +wire [223:0] Q_54 = ITOP.iow0.arr[54]; +wire [223:0] Q_55 = ITOP.iow0.arr[55]; +wire [223:0] Q_56 = ITOP.iow0.arr[56]; +wire [223:0] Q_57 = ITOP.iow0.arr[57]; +wire [223:0] Q_58 = ITOP.iow0.arr[58]; +wire [223:0] Q_59 = ITOP.iow0.arr[59]; +wire [223:0] Q_60 = ITOP.iow0.arr[60]; +wire [223:0] Q_61 = ITOP.iow0.arr[61]; +wire [223:0] Q_62 = ITOP.iow0.arr[62]; +wire [223:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [223:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [223:0] WD_FF; + reg [223:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [223:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [223:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [223:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X224_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [223:0] WD; +input [6:0] RA, WA; +output [223:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [223:0] WDQ; + wire [223:0] WDBQ; + wire [223:0] WMNexp; + wire [223:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [223:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {224{1'b0}}; + assign SHFT = {224{1'b1}}; + reg [223:0] WDQ_pr; + wire [223:0] WDBQ_pr; + assign WMNexp = {224{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[223:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [223:0] dout; + wire [223:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [223:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [223:0] RDBYPASS = {224{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [223:0] force_x; +`ifndef SYNTHESIS + assign force_x = {224{1'bx}}; +`else + assign force_x = {224{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [223:0] rmuxd0; + wire [223:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {224{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {224{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[223:0] <= (rmuxd0[223:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X224_GL_M1_D2_ram # (64, 224, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [223:0] data; + reg [223:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [223:0] mem_read_bank; +input [5:0] addr; +reg [223:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X224_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 224; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [225:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [225:0] val; + integer i; + begin + val = {226{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [225:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [225:0] mem_phys_read_padr; +input [5:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [225:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [225:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [225:0] data; + reg [225:0] wr[0:0]; + integer i; + begin + for (i=0; i<=225; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [225:0] mon_bit_w; +input [5:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [225:0] mon_bit_r; +input [5:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [225:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [225:0] Q_0 = ITOP.iow0.arr[0]; +wire [225:0] Q_1 = ITOP.iow0.arr[1]; +wire [225:0] Q_2 = ITOP.iow0.arr[2]; +wire [225:0] Q_3 = ITOP.iow0.arr[3]; +wire [225:0] Q_4 = ITOP.iow0.arr[4]; +wire [225:0] Q_5 = ITOP.iow0.arr[5]; +wire [225:0] Q_6 = ITOP.iow0.arr[6]; +wire [225:0] Q_7 = ITOP.iow0.arr[7]; +wire [225:0] Q_8 = ITOP.iow0.arr[8]; +wire [225:0] Q_9 = ITOP.iow0.arr[9]; +wire [225:0] Q_10 = ITOP.iow0.arr[10]; +wire [225:0] Q_11 = ITOP.iow0.arr[11]; +wire [225:0] Q_12 = ITOP.iow0.arr[12]; +wire [225:0] Q_13 = ITOP.iow0.arr[13]; +wire [225:0] Q_14 = ITOP.iow0.arr[14]; +wire [225:0] Q_15 = ITOP.iow0.arr[15]; +wire [225:0] Q_16 = ITOP.iow0.arr[16]; +wire [225:0] Q_17 = ITOP.iow0.arr[17]; +wire [225:0] Q_18 = ITOP.iow0.arr[18]; +wire [225:0] Q_19 = ITOP.iow0.arr[19]; +wire [225:0] Q_20 = ITOP.iow0.arr[20]; +wire [225:0] Q_21 = ITOP.iow0.arr[21]; +wire [225:0] Q_22 = ITOP.iow0.arr[22]; +wire [225:0] Q_23 = ITOP.iow0.arr[23]; +wire [225:0] Q_24 = ITOP.iow0.arr[24]; +wire [225:0] Q_25 = ITOP.iow0.arr[25]; +wire [225:0] Q_26 = ITOP.iow0.arr[26]; +wire [225:0] Q_27 = ITOP.iow0.arr[27]; +wire [225:0] Q_28 = ITOP.iow0.arr[28]; +wire [225:0] Q_29 = ITOP.iow0.arr[29]; +wire [225:0] Q_30 = ITOP.iow0.arr[30]; +wire [225:0] Q_31 = ITOP.iow0.arr[31]; +wire [225:0] Q_32 = ITOP.iow0.arr[32]; +wire [225:0] Q_33 = ITOP.iow0.arr[33]; +wire [225:0] Q_34 = ITOP.iow0.arr[34]; +wire [225:0] Q_35 = ITOP.iow0.arr[35]; +wire [225:0] Q_36 = ITOP.iow0.arr[36]; +wire [225:0] Q_37 = ITOP.iow0.arr[37]; +wire [225:0] Q_38 = ITOP.iow0.arr[38]; +wire [225:0] Q_39 = ITOP.iow0.arr[39]; +wire [225:0] Q_40 = ITOP.iow0.arr[40]; +wire [225:0] Q_41 = ITOP.iow0.arr[41]; +wire [225:0] Q_42 = ITOP.iow0.arr[42]; +wire [225:0] Q_43 = ITOP.iow0.arr[43]; +wire [225:0] Q_44 = ITOP.iow0.arr[44]; +wire [225:0] Q_45 = ITOP.iow0.arr[45]; +wire [225:0] Q_46 = ITOP.iow0.arr[46]; +wire [225:0] Q_47 = ITOP.iow0.arr[47]; +wire [225:0] Q_48 = ITOP.iow0.arr[48]; +wire [225:0] Q_49 = ITOP.iow0.arr[49]; +wire [225:0] Q_50 = ITOP.iow0.arr[50]; +wire [225:0] Q_51 = ITOP.iow0.arr[51]; +wire [225:0] Q_52 = ITOP.iow0.arr[52]; +wire [225:0] Q_53 = ITOP.iow0.arr[53]; +wire [225:0] Q_54 = ITOP.iow0.arr[54]; +wire [225:0] Q_55 = ITOP.iow0.arr[55]; +wire [225:0] Q_56 = ITOP.iow0.arr[56]; +wire [225:0] Q_57 = ITOP.iow0.arr[57]; +wire [225:0] Q_58 = ITOP.iow0.arr[58]; +wire [225:0] Q_59 = ITOP.iow0.arr[59]; +wire [225:0] Q_60 = ITOP.iow0.arr[60]; +wire [225:0] Q_61 = ITOP.iow0.arr[61]; +wire [225:0] Q_62 = ITOP.iow0.arr[62]; +wire [225:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [225:0] WD_FF; + reg [225:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [225:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [225:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [225:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X226_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [225:0] WD; +input [6:0] RA, WA; +output [225:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [225:0] WDQ; + wire [225:0] WDBQ; + wire [225:0] WMNexp; + wire [225:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [225:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {226{1'b0}}; + assign SHFT = {226{1'b1}}; + reg [225:0] WDQ_pr; + wire [225:0] WDBQ_pr; + assign WMNexp = {226{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[225:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [225:0] dout; + wire [225:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [225:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [225:0] RDBYPASS = {226{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [225:0] force_x; +`ifndef SYNTHESIS + assign force_x = {226{1'bx}}; +`else + assign force_x = {226{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [225:0] rmuxd0; + wire [225:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {226{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {226{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[225:0] <= (rmuxd0[225:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X226_GL_M1_D2_ram # (64, 226, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [225:0] data; + reg [225:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [225:0] mem_read_bank; +input [5:0] addr; +reg [225:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X226_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 226; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [225:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [225:0] val; + integer i; + begin + val = {226{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [225:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [225:0] mem_phys_read_padr; +input [5:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [225:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [225:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [225:0] data; + reg [225:0] wr[0:0]; + integer i; + begin + for (i=0; i<=225; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [225:0] mon_bit_w; +input [5:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [225:0] mon_bit_r; +input [5:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [225:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [225:0] Q_0 = ITOP.iow0.arr[0]; +wire [225:0] Q_1 = ITOP.iow0.arr[1]; +wire [225:0] Q_2 = ITOP.iow0.arr[2]; +wire [225:0] Q_3 = ITOP.iow0.arr[3]; +wire [225:0] Q_4 = ITOP.iow0.arr[4]; +wire [225:0] Q_5 = ITOP.iow0.arr[5]; +wire [225:0] Q_6 = ITOP.iow0.arr[6]; +wire [225:0] Q_7 = ITOP.iow0.arr[7]; +wire [225:0] Q_8 = ITOP.iow0.arr[8]; +wire [225:0] Q_9 = ITOP.iow0.arr[9]; +wire [225:0] Q_10 = ITOP.iow0.arr[10]; +wire [225:0] Q_11 = ITOP.iow0.arr[11]; +wire [225:0] Q_12 = ITOP.iow0.arr[12]; +wire [225:0] Q_13 = ITOP.iow0.arr[13]; +wire [225:0] Q_14 = ITOP.iow0.arr[14]; +wire [225:0] Q_15 = ITOP.iow0.arr[15]; +wire [225:0] Q_16 = ITOP.iow0.arr[16]; +wire [225:0] Q_17 = ITOP.iow0.arr[17]; +wire [225:0] Q_18 = ITOP.iow0.arr[18]; +wire [225:0] Q_19 = ITOP.iow0.arr[19]; +wire [225:0] Q_20 = ITOP.iow0.arr[20]; +wire [225:0] Q_21 = ITOP.iow0.arr[21]; +wire [225:0] Q_22 = ITOP.iow0.arr[22]; +wire [225:0] Q_23 = ITOP.iow0.arr[23]; +wire [225:0] Q_24 = ITOP.iow0.arr[24]; +wire [225:0] Q_25 = ITOP.iow0.arr[25]; +wire [225:0] Q_26 = ITOP.iow0.arr[26]; +wire [225:0] Q_27 = ITOP.iow0.arr[27]; +wire [225:0] Q_28 = ITOP.iow0.arr[28]; +wire [225:0] Q_29 = ITOP.iow0.arr[29]; +wire [225:0] Q_30 = ITOP.iow0.arr[30]; +wire [225:0] Q_31 = ITOP.iow0.arr[31]; +wire [225:0] Q_32 = ITOP.iow0.arr[32]; +wire [225:0] Q_33 = ITOP.iow0.arr[33]; +wire [225:0] Q_34 = ITOP.iow0.arr[34]; +wire [225:0] Q_35 = ITOP.iow0.arr[35]; +wire [225:0] Q_36 = ITOP.iow0.arr[36]; +wire [225:0] Q_37 = ITOP.iow0.arr[37]; +wire [225:0] Q_38 = ITOP.iow0.arr[38]; +wire [225:0] Q_39 = ITOP.iow0.arr[39]; +wire [225:0] Q_40 = ITOP.iow0.arr[40]; +wire [225:0] Q_41 = ITOP.iow0.arr[41]; +wire [225:0] Q_42 = ITOP.iow0.arr[42]; +wire [225:0] Q_43 = ITOP.iow0.arr[43]; +wire [225:0] Q_44 = ITOP.iow0.arr[44]; +wire [225:0] Q_45 = ITOP.iow0.arr[45]; +wire [225:0] Q_46 = ITOP.iow0.arr[46]; +wire [225:0] Q_47 = ITOP.iow0.arr[47]; +wire [225:0] Q_48 = ITOP.iow0.arr[48]; +wire [225:0] Q_49 = ITOP.iow0.arr[49]; +wire [225:0] Q_50 = ITOP.iow0.arr[50]; +wire [225:0] Q_51 = ITOP.iow0.arr[51]; +wire [225:0] Q_52 = ITOP.iow0.arr[52]; +wire [225:0] Q_53 = ITOP.iow0.arr[53]; +wire [225:0] Q_54 = ITOP.iow0.arr[54]; +wire [225:0] Q_55 = ITOP.iow0.arr[55]; +wire [225:0] Q_56 = ITOP.iow0.arr[56]; +wire [225:0] Q_57 = ITOP.iow0.arr[57]; +wire [225:0] Q_58 = ITOP.iow0.arr[58]; +wire [225:0] Q_59 = ITOP.iow0.arr[59]; +wire [225:0] Q_60 = ITOP.iow0.arr[60]; +wire [225:0] Q_61 = ITOP.iow0.arr[61]; +wire [225:0] Q_62 = ITOP.iow0.arr[62]; +wire [225:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [225:0] WD_FF; + reg [225:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [225:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [225:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [225:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X226_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [225:0] WD; +input [6:0] RA, WA; +output [225:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [225:0] WDQ; + wire [225:0] WDBQ; + wire [225:0] WMNexp; + wire [225:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [225:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {226{1'b0}}; + assign SHFT = {226{1'b1}}; + reg [225:0] WDQ_pr; + wire [225:0] WDBQ_pr; + assign WMNexp = {226{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[225:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [225:0] dout; + wire [225:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [225:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [225:0] RDBYPASS = {226{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [225:0] force_x; +`ifndef SYNTHESIS + assign force_x = {226{1'bx}}; +`else + assign force_x = {226{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [225:0] rmuxd0; + wire [225:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {226{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {226{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[225:0] <= (rmuxd0[225:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X226_GL_M1_D2_ram # (64, 226, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [225:0] data; + reg [225:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [225:0] mem_read_bank; +input [5:0] addr; +reg [225:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X226_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 226; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [287:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [287:0] val; + integer i; + begin + val = {288{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [287:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [5:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [287:0] data; + reg [287:0] wr[0:0]; + integer i; + begin + for (i=0; i<=287; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [5:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [5:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [287:0] Q_0 = ITOP.iow0.arr[0]; +wire [287:0] Q_1 = ITOP.iow0.arr[1]; +wire [287:0] Q_2 = ITOP.iow0.arr[2]; +wire [287:0] Q_3 = ITOP.iow0.arr[3]; +wire [287:0] Q_4 = ITOP.iow0.arr[4]; +wire [287:0] Q_5 = ITOP.iow0.arr[5]; +wire [287:0] Q_6 = ITOP.iow0.arr[6]; +wire [287:0] Q_7 = ITOP.iow0.arr[7]; +wire [287:0] Q_8 = ITOP.iow0.arr[8]; +wire [287:0] Q_9 = ITOP.iow0.arr[9]; +wire [287:0] Q_10 = ITOP.iow0.arr[10]; +wire [287:0] Q_11 = ITOP.iow0.arr[11]; +wire [287:0] Q_12 = ITOP.iow0.arr[12]; +wire [287:0] Q_13 = ITOP.iow0.arr[13]; +wire [287:0] Q_14 = ITOP.iow0.arr[14]; +wire [287:0] Q_15 = ITOP.iow0.arr[15]; +wire [287:0] Q_16 = ITOP.iow0.arr[16]; +wire [287:0] Q_17 = ITOP.iow0.arr[17]; +wire [287:0] Q_18 = ITOP.iow0.arr[18]; +wire [287:0] Q_19 = ITOP.iow0.arr[19]; +wire [287:0] Q_20 = ITOP.iow0.arr[20]; +wire [287:0] Q_21 = ITOP.iow0.arr[21]; +wire [287:0] Q_22 = ITOP.iow0.arr[22]; +wire [287:0] Q_23 = ITOP.iow0.arr[23]; +wire [287:0] Q_24 = ITOP.iow0.arr[24]; +wire [287:0] Q_25 = ITOP.iow0.arr[25]; +wire [287:0] Q_26 = ITOP.iow0.arr[26]; +wire [287:0] Q_27 = ITOP.iow0.arr[27]; +wire [287:0] Q_28 = ITOP.iow0.arr[28]; +wire [287:0] Q_29 = ITOP.iow0.arr[29]; +wire [287:0] Q_30 = ITOP.iow0.arr[30]; +wire [287:0] Q_31 = ITOP.iow0.arr[31]; +wire [287:0] Q_32 = ITOP.iow0.arr[32]; +wire [287:0] Q_33 = ITOP.iow0.arr[33]; +wire [287:0] Q_34 = ITOP.iow0.arr[34]; +wire [287:0] Q_35 = ITOP.iow0.arr[35]; +wire [287:0] Q_36 = ITOP.iow0.arr[36]; +wire [287:0] Q_37 = ITOP.iow0.arr[37]; +wire [287:0] Q_38 = ITOP.iow0.arr[38]; +wire [287:0] Q_39 = ITOP.iow0.arr[39]; +wire [287:0] Q_40 = ITOP.iow0.arr[40]; +wire [287:0] Q_41 = ITOP.iow0.arr[41]; +wire [287:0] Q_42 = ITOP.iow0.arr[42]; +wire [287:0] Q_43 = ITOP.iow0.arr[43]; +wire [287:0] Q_44 = ITOP.iow0.arr[44]; +wire [287:0] Q_45 = ITOP.iow0.arr[45]; +wire [287:0] Q_46 = ITOP.iow0.arr[46]; +wire [287:0] Q_47 = ITOP.iow0.arr[47]; +wire [287:0] Q_48 = ITOP.iow0.arr[48]; +wire [287:0] Q_49 = ITOP.iow0.arr[49]; +wire [287:0] Q_50 = ITOP.iow0.arr[50]; +wire [287:0] Q_51 = ITOP.iow0.arr[51]; +wire [287:0] Q_52 = ITOP.iow0.arr[52]; +wire [287:0] Q_53 = ITOP.iow0.arr[53]; +wire [287:0] Q_54 = ITOP.iow0.arr[54]; +wire [287:0] Q_55 = ITOP.iow0.arr[55]; +wire [287:0] Q_56 = ITOP.iow0.arr[56]; +wire [287:0] Q_57 = ITOP.iow0.arr[57]; +wire [287:0] Q_58 = ITOP.iow0.arr[58]; +wire [287:0] Q_59 = ITOP.iow0.arr[59]; +wire [287:0] Q_60 = ITOP.iow0.arr[60]; +wire [287:0] Q_61 = ITOP.iow0.arr[61]; +wire [287:0] Q_62 = ITOP.iow0.arr[62]; +wire [287:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [287:0] WD_FF; + reg [287:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [287:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [287:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [287:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X288_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [287:0] WD; +input [6:0] RA, WA; +output [287:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [287:0] WDQ; + wire [287:0] WDBQ; + wire [287:0] WMNexp; + wire [287:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [287:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {288{1'b0}}; + assign SHFT = {288{1'b1}}; + reg [287:0] WDQ_pr; + wire [287:0] WDBQ_pr; + assign WMNexp = {288{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[287:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [287:0] dout; + wire [287:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [287:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [287:0] RDBYPASS = {288{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [287:0] force_x; +`ifndef SYNTHESIS + assign force_x = {288{1'bx}}; +`else + assign force_x = {288{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [287:0] rmuxd0; + wire [287:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {288{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {288{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[287:0] <= (rmuxd0[287:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X288_GL_M1_D2_ram # (64, 288, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [287:0] data; + reg [287:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [287:0] mem_read_bank; +input [5:0] addr; +reg [287:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X288_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 288; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [287:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [287:0] val; + integer i; + begin + val = {288{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [287:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [5:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [287:0] data; + reg [287:0] wr[0:0]; + integer i; + begin + for (i=0; i<=287; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [5:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [5:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [287:0] Q_0 = ITOP.iow0.arr[0]; +wire [287:0] Q_1 = ITOP.iow0.arr[1]; +wire [287:0] Q_2 = ITOP.iow0.arr[2]; +wire [287:0] Q_3 = ITOP.iow0.arr[3]; +wire [287:0] Q_4 = ITOP.iow0.arr[4]; +wire [287:0] Q_5 = ITOP.iow0.arr[5]; +wire [287:0] Q_6 = ITOP.iow0.arr[6]; +wire [287:0] Q_7 = ITOP.iow0.arr[7]; +wire [287:0] Q_8 = ITOP.iow0.arr[8]; +wire [287:0] Q_9 = ITOP.iow0.arr[9]; +wire [287:0] Q_10 = ITOP.iow0.arr[10]; +wire [287:0] Q_11 = ITOP.iow0.arr[11]; +wire [287:0] Q_12 = ITOP.iow0.arr[12]; +wire [287:0] Q_13 = ITOP.iow0.arr[13]; +wire [287:0] Q_14 = ITOP.iow0.arr[14]; +wire [287:0] Q_15 = ITOP.iow0.arr[15]; +wire [287:0] Q_16 = ITOP.iow0.arr[16]; +wire [287:0] Q_17 = ITOP.iow0.arr[17]; +wire [287:0] Q_18 = ITOP.iow0.arr[18]; +wire [287:0] Q_19 = ITOP.iow0.arr[19]; +wire [287:0] Q_20 = ITOP.iow0.arr[20]; +wire [287:0] Q_21 = ITOP.iow0.arr[21]; +wire [287:0] Q_22 = ITOP.iow0.arr[22]; +wire [287:0] Q_23 = ITOP.iow0.arr[23]; +wire [287:0] Q_24 = ITOP.iow0.arr[24]; +wire [287:0] Q_25 = ITOP.iow0.arr[25]; +wire [287:0] Q_26 = ITOP.iow0.arr[26]; +wire [287:0] Q_27 = ITOP.iow0.arr[27]; +wire [287:0] Q_28 = ITOP.iow0.arr[28]; +wire [287:0] Q_29 = ITOP.iow0.arr[29]; +wire [287:0] Q_30 = ITOP.iow0.arr[30]; +wire [287:0] Q_31 = ITOP.iow0.arr[31]; +wire [287:0] Q_32 = ITOP.iow0.arr[32]; +wire [287:0] Q_33 = ITOP.iow0.arr[33]; +wire [287:0] Q_34 = ITOP.iow0.arr[34]; +wire [287:0] Q_35 = ITOP.iow0.arr[35]; +wire [287:0] Q_36 = ITOP.iow0.arr[36]; +wire [287:0] Q_37 = ITOP.iow0.arr[37]; +wire [287:0] Q_38 = ITOP.iow0.arr[38]; +wire [287:0] Q_39 = ITOP.iow0.arr[39]; +wire [287:0] Q_40 = ITOP.iow0.arr[40]; +wire [287:0] Q_41 = ITOP.iow0.arr[41]; +wire [287:0] Q_42 = ITOP.iow0.arr[42]; +wire [287:0] Q_43 = ITOP.iow0.arr[43]; +wire [287:0] Q_44 = ITOP.iow0.arr[44]; +wire [287:0] Q_45 = ITOP.iow0.arr[45]; +wire [287:0] Q_46 = ITOP.iow0.arr[46]; +wire [287:0] Q_47 = ITOP.iow0.arr[47]; +wire [287:0] Q_48 = ITOP.iow0.arr[48]; +wire [287:0] Q_49 = ITOP.iow0.arr[49]; +wire [287:0] Q_50 = ITOP.iow0.arr[50]; +wire [287:0] Q_51 = ITOP.iow0.arr[51]; +wire [287:0] Q_52 = ITOP.iow0.arr[52]; +wire [287:0] Q_53 = ITOP.iow0.arr[53]; +wire [287:0] Q_54 = ITOP.iow0.arr[54]; +wire [287:0] Q_55 = ITOP.iow0.arr[55]; +wire [287:0] Q_56 = ITOP.iow0.arr[56]; +wire [287:0] Q_57 = ITOP.iow0.arr[57]; +wire [287:0] Q_58 = ITOP.iow0.arr[58]; +wire [287:0] Q_59 = ITOP.iow0.arr[59]; +wire [287:0] Q_60 = ITOP.iow0.arr[60]; +wire [287:0] Q_61 = ITOP.iow0.arr[61]; +wire [287:0] Q_62 = ITOP.iow0.arr[62]; +wire [287:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [287:0] WD_FF; + reg [287:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [287:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [287:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [287:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X288_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [287:0] WD; +input [6:0] RA, WA; +output [287:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [287:0] WDQ; + wire [287:0] WDBQ; + wire [287:0] WMNexp; + wire [287:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [287:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {288{1'b0}}; + assign SHFT = {288{1'b1}}; + reg [287:0] WDQ_pr; + wire [287:0] WDBQ_pr; + assign WMNexp = {288{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[287:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [287:0] dout; + wire [287:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [287:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [287:0] RDBYPASS = {288{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [287:0] force_x; +`ifndef SYNTHESIS + assign force_x = {288{1'bx}}; +`else + assign force_x = {288{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [287:0] rmuxd0; + wire [287:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {288{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {288{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[287:0] <= (rmuxd0[287:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X288_GL_M1_D2_ram # (64, 288, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [287:0] data; + reg [287:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [287:0] mem_read_bank; +input [5:0] addr; +reg [287:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X288_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 288; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [63:0] mem_phys_read_padr; +input [5:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [63:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [63:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [63:0] data; + reg [63:0] wr[0:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [63:0] mon_bit_w; +input [5:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [63:0] mon_bit_r; +input [5:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [63:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow0.arr[1]; +wire [63:0] Q_2 = ITOP.iow0.arr[2]; +wire [63:0] Q_3 = ITOP.iow0.arr[3]; +wire [63:0] Q_4 = ITOP.iow0.arr[4]; +wire [63:0] Q_5 = ITOP.iow0.arr[5]; +wire [63:0] Q_6 = ITOP.iow0.arr[6]; +wire [63:0] Q_7 = ITOP.iow0.arr[7]; +wire [63:0] Q_8 = ITOP.iow0.arr[8]; +wire [63:0] Q_9 = ITOP.iow0.arr[9]; +wire [63:0] Q_10 = ITOP.iow0.arr[10]; +wire [63:0] Q_11 = ITOP.iow0.arr[11]; +wire [63:0] Q_12 = ITOP.iow0.arr[12]; +wire [63:0] Q_13 = ITOP.iow0.arr[13]; +wire [63:0] Q_14 = ITOP.iow0.arr[14]; +wire [63:0] Q_15 = ITOP.iow0.arr[15]; +wire [63:0] Q_16 = ITOP.iow0.arr[16]; +wire [63:0] Q_17 = ITOP.iow0.arr[17]; +wire [63:0] Q_18 = ITOP.iow0.arr[18]; +wire [63:0] Q_19 = ITOP.iow0.arr[19]; +wire [63:0] Q_20 = ITOP.iow0.arr[20]; +wire [63:0] Q_21 = ITOP.iow0.arr[21]; +wire [63:0] Q_22 = ITOP.iow0.arr[22]; +wire [63:0] Q_23 = ITOP.iow0.arr[23]; +wire [63:0] Q_24 = ITOP.iow0.arr[24]; +wire [63:0] Q_25 = ITOP.iow0.arr[25]; +wire [63:0] Q_26 = ITOP.iow0.arr[26]; +wire [63:0] Q_27 = ITOP.iow0.arr[27]; +wire [63:0] Q_28 = ITOP.iow0.arr[28]; +wire [63:0] Q_29 = ITOP.iow0.arr[29]; +wire [63:0] Q_30 = ITOP.iow0.arr[30]; +wire [63:0] Q_31 = ITOP.iow0.arr[31]; +wire [63:0] Q_32 = ITOP.iow0.arr[32]; +wire [63:0] Q_33 = ITOP.iow0.arr[33]; +wire [63:0] Q_34 = ITOP.iow0.arr[34]; +wire [63:0] Q_35 = ITOP.iow0.arr[35]; +wire [63:0] Q_36 = ITOP.iow0.arr[36]; +wire [63:0] Q_37 = ITOP.iow0.arr[37]; +wire [63:0] Q_38 = ITOP.iow0.arr[38]; +wire [63:0] Q_39 = ITOP.iow0.arr[39]; +wire [63:0] Q_40 = ITOP.iow0.arr[40]; +wire [63:0] Q_41 = ITOP.iow0.arr[41]; +wire [63:0] Q_42 = ITOP.iow0.arr[42]; +wire [63:0] Q_43 = ITOP.iow0.arr[43]; +wire [63:0] Q_44 = ITOP.iow0.arr[44]; +wire [63:0] Q_45 = ITOP.iow0.arr[45]; +wire [63:0] Q_46 = ITOP.iow0.arr[46]; +wire [63:0] Q_47 = ITOP.iow0.arr[47]; +wire [63:0] Q_48 = ITOP.iow0.arr[48]; +wire [63:0] Q_49 = ITOP.iow0.arr[49]; +wire [63:0] Q_50 = ITOP.iow0.arr[50]; +wire [63:0] Q_51 = ITOP.iow0.arr[51]; +wire [63:0] Q_52 = ITOP.iow0.arr[52]; +wire [63:0] Q_53 = ITOP.iow0.arr[53]; +wire [63:0] Q_54 = ITOP.iow0.arr[54]; +wire [63:0] Q_55 = ITOP.iow0.arr[55]; +wire [63:0] Q_56 = ITOP.iow0.arr[56]; +wire [63:0] Q_57 = ITOP.iow0.arr[57]; +wire [63:0] Q_58 = ITOP.iow0.arr[58]; +wire [63:0] Q_59 = ITOP.iow0.arr[59]; +wire [63:0] Q_60 = ITOP.iow0.arr[60]; +wire [63:0] Q_61 = ITOP.iow0.arr[61]; +wire [63:0] Q_62 = ITOP.iow0.arr[62]; +wire [63:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X64_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [6:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [63:0] rmuxd0; + wire [63:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X64_GL_M1_D2_ram # (64, 64, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [5:0] addr; +reg [63:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X64_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [63:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [63:0] val; + integer i; + begin + val = {64{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [63:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [63:0] mem_phys_read_padr; +input [5:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [63:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=63; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [63:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [63:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [64-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {64 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {64 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [63:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [63:0] data; + reg [63:0] wr[0:0]; + integer i; + begin + for (i=0; i<=63; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [63:0] mon_bit_w; +input [5:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [63:0] mon_bit_r; +input [5:0] addr; + reg [63:0] mon_row; + reg [63:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=63; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [63:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<64; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [63:0] Q_0 = ITOP.iow0.arr[0]; +wire [63:0] Q_1 = ITOP.iow0.arr[1]; +wire [63:0] Q_2 = ITOP.iow0.arr[2]; +wire [63:0] Q_3 = ITOP.iow0.arr[3]; +wire [63:0] Q_4 = ITOP.iow0.arr[4]; +wire [63:0] Q_5 = ITOP.iow0.arr[5]; +wire [63:0] Q_6 = ITOP.iow0.arr[6]; +wire [63:0] Q_7 = ITOP.iow0.arr[7]; +wire [63:0] Q_8 = ITOP.iow0.arr[8]; +wire [63:0] Q_9 = ITOP.iow0.arr[9]; +wire [63:0] Q_10 = ITOP.iow0.arr[10]; +wire [63:0] Q_11 = ITOP.iow0.arr[11]; +wire [63:0] Q_12 = ITOP.iow0.arr[12]; +wire [63:0] Q_13 = ITOP.iow0.arr[13]; +wire [63:0] Q_14 = ITOP.iow0.arr[14]; +wire [63:0] Q_15 = ITOP.iow0.arr[15]; +wire [63:0] Q_16 = ITOP.iow0.arr[16]; +wire [63:0] Q_17 = ITOP.iow0.arr[17]; +wire [63:0] Q_18 = ITOP.iow0.arr[18]; +wire [63:0] Q_19 = ITOP.iow0.arr[19]; +wire [63:0] Q_20 = ITOP.iow0.arr[20]; +wire [63:0] Q_21 = ITOP.iow0.arr[21]; +wire [63:0] Q_22 = ITOP.iow0.arr[22]; +wire [63:0] Q_23 = ITOP.iow0.arr[23]; +wire [63:0] Q_24 = ITOP.iow0.arr[24]; +wire [63:0] Q_25 = ITOP.iow0.arr[25]; +wire [63:0] Q_26 = ITOP.iow0.arr[26]; +wire [63:0] Q_27 = ITOP.iow0.arr[27]; +wire [63:0] Q_28 = ITOP.iow0.arr[28]; +wire [63:0] Q_29 = ITOP.iow0.arr[29]; +wire [63:0] Q_30 = ITOP.iow0.arr[30]; +wire [63:0] Q_31 = ITOP.iow0.arr[31]; +wire [63:0] Q_32 = ITOP.iow0.arr[32]; +wire [63:0] Q_33 = ITOP.iow0.arr[33]; +wire [63:0] Q_34 = ITOP.iow0.arr[34]; +wire [63:0] Q_35 = ITOP.iow0.arr[35]; +wire [63:0] Q_36 = ITOP.iow0.arr[36]; +wire [63:0] Q_37 = ITOP.iow0.arr[37]; +wire [63:0] Q_38 = ITOP.iow0.arr[38]; +wire [63:0] Q_39 = ITOP.iow0.arr[39]; +wire [63:0] Q_40 = ITOP.iow0.arr[40]; +wire [63:0] Q_41 = ITOP.iow0.arr[41]; +wire [63:0] Q_42 = ITOP.iow0.arr[42]; +wire [63:0] Q_43 = ITOP.iow0.arr[43]; +wire [63:0] Q_44 = ITOP.iow0.arr[44]; +wire [63:0] Q_45 = ITOP.iow0.arr[45]; +wire [63:0] Q_46 = ITOP.iow0.arr[46]; +wire [63:0] Q_47 = ITOP.iow0.arr[47]; +wire [63:0] Q_48 = ITOP.iow0.arr[48]; +wire [63:0] Q_49 = ITOP.iow0.arr[49]; +wire [63:0] Q_50 = ITOP.iow0.arr[50]; +wire [63:0] Q_51 = ITOP.iow0.arr[51]; +wire [63:0] Q_52 = ITOP.iow0.arr[52]; +wire [63:0] Q_53 = ITOP.iow0.arr[53]; +wire [63:0] Q_54 = ITOP.iow0.arr[54]; +wire [63:0] Q_55 = ITOP.iow0.arr[55]; +wire [63:0] Q_56 = ITOP.iow0.arr[56]; +wire [63:0] Q_57 = ITOP.iow0.arr[57]; +wire [63:0] Q_58 = ITOP.iow0.arr[58]; +wire [63:0] Q_59 = ITOP.iow0.arr[59]; +wire [63:0] Q_60 = ITOP.iow0.arr[60]; +wire [63:0] Q_61 = ITOP.iow0.arr[61]; +wire [63:0] Q_62 = ITOP.iow0.arr[62]; +wire [63:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [63:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [63:0] WD_FF; + reg [63:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [63:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [63:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [63:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X64_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [63:0] WD; +input [6:0] RA, WA; +output [63:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [63:0] WDQ; + wire [63:0] WDBQ; + wire [63:0] WMNexp; + wire [63:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [63:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {64{1'b0}}; + assign SHFT = {64{1'b1}}; + reg [63:0] WDQ_pr; + wire [63:0] WDBQ_pr; + assign WMNexp = {64{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[63:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [63:0] dout; + wire [63:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [63:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [63:0] RDBYPASS = {64{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [63:0] force_x; +`ifndef SYNTHESIS + assign force_x = {64{1'bx}}; +`else + assign force_x = {64{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [63:0] rmuxd0; + wire [63:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {64{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {64{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[63:0] <= (rmuxd0[63:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X64_GL_M1_D2_ram # (64, 64, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [63:0] data; + reg [63:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [63:0] mem_read_bank; +input [5:0] addr; +reg [63:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X64_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 64; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [65:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [65:0] val; + integer i; + begin + val = {66{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [65:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [65:0] mem_phys_read_padr; +input [5:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [65:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [65:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [65:0] data; + reg [65:0] wr[0:0]; + integer i; + begin + for (i=0; i<=65; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [65:0] mon_bit_w; +input [5:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [65:0] mon_bit_r; +input [5:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [65:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [65:0] Q_0 = ITOP.iow0.arr[0]; +wire [65:0] Q_1 = ITOP.iow0.arr[1]; +wire [65:0] Q_2 = ITOP.iow0.arr[2]; +wire [65:0] Q_3 = ITOP.iow0.arr[3]; +wire [65:0] Q_4 = ITOP.iow0.arr[4]; +wire [65:0] Q_5 = ITOP.iow0.arr[5]; +wire [65:0] Q_6 = ITOP.iow0.arr[6]; +wire [65:0] Q_7 = ITOP.iow0.arr[7]; +wire [65:0] Q_8 = ITOP.iow0.arr[8]; +wire [65:0] Q_9 = ITOP.iow0.arr[9]; +wire [65:0] Q_10 = ITOP.iow0.arr[10]; +wire [65:0] Q_11 = ITOP.iow0.arr[11]; +wire [65:0] Q_12 = ITOP.iow0.arr[12]; +wire [65:0] Q_13 = ITOP.iow0.arr[13]; +wire [65:0] Q_14 = ITOP.iow0.arr[14]; +wire [65:0] Q_15 = ITOP.iow0.arr[15]; +wire [65:0] Q_16 = ITOP.iow0.arr[16]; +wire [65:0] Q_17 = ITOP.iow0.arr[17]; +wire [65:0] Q_18 = ITOP.iow0.arr[18]; +wire [65:0] Q_19 = ITOP.iow0.arr[19]; +wire [65:0] Q_20 = ITOP.iow0.arr[20]; +wire [65:0] Q_21 = ITOP.iow0.arr[21]; +wire [65:0] Q_22 = ITOP.iow0.arr[22]; +wire [65:0] Q_23 = ITOP.iow0.arr[23]; +wire [65:0] Q_24 = ITOP.iow0.arr[24]; +wire [65:0] Q_25 = ITOP.iow0.arr[25]; +wire [65:0] Q_26 = ITOP.iow0.arr[26]; +wire [65:0] Q_27 = ITOP.iow0.arr[27]; +wire [65:0] Q_28 = ITOP.iow0.arr[28]; +wire [65:0] Q_29 = ITOP.iow0.arr[29]; +wire [65:0] Q_30 = ITOP.iow0.arr[30]; +wire [65:0] Q_31 = ITOP.iow0.arr[31]; +wire [65:0] Q_32 = ITOP.iow0.arr[32]; +wire [65:0] Q_33 = ITOP.iow0.arr[33]; +wire [65:0] Q_34 = ITOP.iow0.arr[34]; +wire [65:0] Q_35 = ITOP.iow0.arr[35]; +wire [65:0] Q_36 = ITOP.iow0.arr[36]; +wire [65:0] Q_37 = ITOP.iow0.arr[37]; +wire [65:0] Q_38 = ITOP.iow0.arr[38]; +wire [65:0] Q_39 = ITOP.iow0.arr[39]; +wire [65:0] Q_40 = ITOP.iow0.arr[40]; +wire [65:0] Q_41 = ITOP.iow0.arr[41]; +wire [65:0] Q_42 = ITOP.iow0.arr[42]; +wire [65:0] Q_43 = ITOP.iow0.arr[43]; +wire [65:0] Q_44 = ITOP.iow0.arr[44]; +wire [65:0] Q_45 = ITOP.iow0.arr[45]; +wire [65:0] Q_46 = ITOP.iow0.arr[46]; +wire [65:0] Q_47 = ITOP.iow0.arr[47]; +wire [65:0] Q_48 = ITOP.iow0.arr[48]; +wire [65:0] Q_49 = ITOP.iow0.arr[49]; +wire [65:0] Q_50 = ITOP.iow0.arr[50]; +wire [65:0] Q_51 = ITOP.iow0.arr[51]; +wire [65:0] Q_52 = ITOP.iow0.arr[52]; +wire [65:0] Q_53 = ITOP.iow0.arr[53]; +wire [65:0] Q_54 = ITOP.iow0.arr[54]; +wire [65:0] Q_55 = ITOP.iow0.arr[55]; +wire [65:0] Q_56 = ITOP.iow0.arr[56]; +wire [65:0] Q_57 = ITOP.iow0.arr[57]; +wire [65:0] Q_58 = ITOP.iow0.arr[58]; +wire [65:0] Q_59 = ITOP.iow0.arr[59]; +wire [65:0] Q_60 = ITOP.iow0.arr[60]; +wire [65:0] Q_61 = ITOP.iow0.arr[61]; +wire [65:0] Q_62 = ITOP.iow0.arr[62]; +wire [65:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [65:0] WD_FF; + reg [65:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [65:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [65:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [65:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X66_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [65:0] WD; +input [6:0] RA, WA; +output [65:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [65:0] WDQ; + wire [65:0] WDBQ; + wire [65:0] WMNexp; + wire [65:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [65:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {66{1'b0}}; + assign SHFT = {66{1'b1}}; + reg [65:0] WDQ_pr; + wire [65:0] WDBQ_pr; + assign WMNexp = {66{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[65:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [65:0] dout; + wire [65:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [65:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [65:0] RDBYPASS = {66{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [65:0] force_x; +`ifndef SYNTHESIS + assign force_x = {66{1'bx}}; +`else + assign force_x = {66{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [65:0] rmuxd0; + wire [65:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {66{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {66{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[65:0] <= (rmuxd0[65:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X66_GL_M1_D2_ram # (64, 66, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [65:0] data; + reg [65:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [65:0] mem_read_bank; +input [5:0] addr; +reg [65:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X66_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 66; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [65:0] val; + integer i; + begin + for (i=0; i<64; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [65:0] val; + integer i; + begin + val = {66{fill_bit}}; + for (i=0; i<64; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [5:0] addr; + reg [65:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [65:0] mem_phys_read_padr; +input [5:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [65:0] mem_phys_read_ladr; +input [5:0] addr; + reg [5:0] paddr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [65:0] mem_phys_read_pmasked; +input [5:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [65:0] data; + reg [65:0] wr[0:0]; + integer i; + begin + for (i=0; i<=65; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [5:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [65:0] mon_bit_w; +input [5:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [65:0] mon_bit_r; +input [5:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [65:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=64;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<64; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [65:0] Q_0 = ITOP.iow0.arr[0]; +wire [65:0] Q_1 = ITOP.iow0.arr[1]; +wire [65:0] Q_2 = ITOP.iow0.arr[2]; +wire [65:0] Q_3 = ITOP.iow0.arr[3]; +wire [65:0] Q_4 = ITOP.iow0.arr[4]; +wire [65:0] Q_5 = ITOP.iow0.arr[5]; +wire [65:0] Q_6 = ITOP.iow0.arr[6]; +wire [65:0] Q_7 = ITOP.iow0.arr[7]; +wire [65:0] Q_8 = ITOP.iow0.arr[8]; +wire [65:0] Q_9 = ITOP.iow0.arr[9]; +wire [65:0] Q_10 = ITOP.iow0.arr[10]; +wire [65:0] Q_11 = ITOP.iow0.arr[11]; +wire [65:0] Q_12 = ITOP.iow0.arr[12]; +wire [65:0] Q_13 = ITOP.iow0.arr[13]; +wire [65:0] Q_14 = ITOP.iow0.arr[14]; +wire [65:0] Q_15 = ITOP.iow0.arr[15]; +wire [65:0] Q_16 = ITOP.iow0.arr[16]; +wire [65:0] Q_17 = ITOP.iow0.arr[17]; +wire [65:0] Q_18 = ITOP.iow0.arr[18]; +wire [65:0] Q_19 = ITOP.iow0.arr[19]; +wire [65:0] Q_20 = ITOP.iow0.arr[20]; +wire [65:0] Q_21 = ITOP.iow0.arr[21]; +wire [65:0] Q_22 = ITOP.iow0.arr[22]; +wire [65:0] Q_23 = ITOP.iow0.arr[23]; +wire [65:0] Q_24 = ITOP.iow0.arr[24]; +wire [65:0] Q_25 = ITOP.iow0.arr[25]; +wire [65:0] Q_26 = ITOP.iow0.arr[26]; +wire [65:0] Q_27 = ITOP.iow0.arr[27]; +wire [65:0] Q_28 = ITOP.iow0.arr[28]; +wire [65:0] Q_29 = ITOP.iow0.arr[29]; +wire [65:0] Q_30 = ITOP.iow0.arr[30]; +wire [65:0] Q_31 = ITOP.iow0.arr[31]; +wire [65:0] Q_32 = ITOP.iow0.arr[32]; +wire [65:0] Q_33 = ITOP.iow0.arr[33]; +wire [65:0] Q_34 = ITOP.iow0.arr[34]; +wire [65:0] Q_35 = ITOP.iow0.arr[35]; +wire [65:0] Q_36 = ITOP.iow0.arr[36]; +wire [65:0] Q_37 = ITOP.iow0.arr[37]; +wire [65:0] Q_38 = ITOP.iow0.arr[38]; +wire [65:0] Q_39 = ITOP.iow0.arr[39]; +wire [65:0] Q_40 = ITOP.iow0.arr[40]; +wire [65:0] Q_41 = ITOP.iow0.arr[41]; +wire [65:0] Q_42 = ITOP.iow0.arr[42]; +wire [65:0] Q_43 = ITOP.iow0.arr[43]; +wire [65:0] Q_44 = ITOP.iow0.arr[44]; +wire [65:0] Q_45 = ITOP.iow0.arr[45]; +wire [65:0] Q_46 = ITOP.iow0.arr[46]; +wire [65:0] Q_47 = ITOP.iow0.arr[47]; +wire [65:0] Q_48 = ITOP.iow0.arr[48]; +wire [65:0] Q_49 = ITOP.iow0.arr[49]; +wire [65:0] Q_50 = ITOP.iow0.arr[50]; +wire [65:0] Q_51 = ITOP.iow0.arr[51]; +wire [65:0] Q_52 = ITOP.iow0.arr[52]; +wire [65:0] Q_53 = ITOP.iow0.arr[53]; +wire [65:0] Q_54 = ITOP.iow0.arr[54]; +wire [65:0] Q_55 = ITOP.iow0.arr[55]; +wire [65:0] Q_56 = ITOP.iow0.arr[56]; +wire [65:0] Q_57 = ITOP.iow0.arr[57]; +wire [65:0] Q_58 = ITOP.iow0.arr[58]; +wire [65:0] Q_59 = ITOP.iow0.arr[59]; +wire [65:0] Q_60 = ITOP.iow0.arr[60]; +wire [65:0] Q_61 = ITOP.iow0.arr[61]; +wire [65:0] Q_62 = ITOP.iow0.arr[62]; +wire [65:0] Q_63 = ITOP.iow0.arr[63]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [65:0] WD_FF; + reg [65:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [65:0] mem[63:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [65:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [65:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_64X66_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [65:0] WD; +input [6:0] RA, WA; +output [65:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [65:0] WDQ; + wire [65:0] WDBQ; + wire [65:0] WMNexp; + wire [65:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [65:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {66{1'b0}}; + assign SHFT = {66{1'b1}}; + reg [65:0] WDQ_pr; + wire [65:0] WDBQ_pr; + assign WMNexp = {66{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[65:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [65:0] dout; + wire [65:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [65:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [65:0] RDBYPASS = {66{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 64 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[6:6]); +// Max address is 64 --> ['1', '1', '1', '1', '1', '1'] + assign empadd = 1'b0; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [65:0] force_x; +`ifndef SYNTHESIS + assign force_x = {66{1'bx}}; +`else + assign force_x = {66{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [65:0] rmuxd0; + wire [65:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {66{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {66{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[65:0] <= (rmuxd0[65:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_64X66_GL_M1_D2_ram # (64, 66, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [5:0] addr; + input [65:0] data; + reg [65:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[5:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [65:0] mem_read_bank; +input [5:0] addr; +reg [65:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_64X66_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 64; +parameter bits = 66; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [15:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [15:0] val; + integer i; + begin + val = {16{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [15:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [16-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {16 {1'b1}} `else { $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {16 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[6:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [31:0] mem_phys_read_padr; +input [5:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [31:0] mem_phys_read_ladr; +input [6:0] addr; + reg [5:0] paddr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [31:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[6:1]) : 16'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[6:1]) : 16'bx; + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [31:0] data; + reg [15:0] wr[1:0]; + integer i; + begin + for (i=0; i<=15; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [31:0] mon_bit_w; +input [5:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [31:0] mon_bit_r; +input [5:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [31:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=40;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=40;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [15:0] Q_0 = ITOP.iow0.arr[0]; +wire [15:0] Q_1 = ITOP.iow1.arr[0]; +wire [15:0] Q_2 = ITOP.iow0.arr[1]; +wire [15:0] Q_3 = ITOP.iow1.arr[1]; +wire [15:0] Q_4 = ITOP.iow0.arr[2]; +wire [15:0] Q_5 = ITOP.iow1.arr[2]; +wire [15:0] Q_6 = ITOP.iow0.arr[3]; +wire [15:0] Q_7 = ITOP.iow1.arr[3]; +wire [15:0] Q_8 = ITOP.iow0.arr[4]; +wire [15:0] Q_9 = ITOP.iow1.arr[4]; +wire [15:0] Q_10 = ITOP.iow0.arr[5]; +wire [15:0] Q_11 = ITOP.iow1.arr[5]; +wire [15:0] Q_12 = ITOP.iow0.arr[6]; +wire [15:0] Q_13 = ITOP.iow1.arr[6]; +wire [15:0] Q_14 = ITOP.iow0.arr[7]; +wire [15:0] Q_15 = ITOP.iow1.arr[7]; +wire [15:0] Q_16 = ITOP.iow0.arr[8]; +wire [15:0] Q_17 = ITOP.iow1.arr[8]; +wire [15:0] Q_18 = ITOP.iow0.arr[9]; +wire [15:0] Q_19 = ITOP.iow1.arr[9]; +wire [15:0] Q_20 = ITOP.iow0.arr[10]; +wire [15:0] Q_21 = ITOP.iow1.arr[10]; +wire [15:0] Q_22 = ITOP.iow0.arr[11]; +wire [15:0] Q_23 = ITOP.iow1.arr[11]; +wire [15:0] Q_24 = ITOP.iow0.arr[12]; +wire [15:0] Q_25 = ITOP.iow1.arr[12]; +wire [15:0] Q_26 = ITOP.iow0.arr[13]; +wire [15:0] Q_27 = ITOP.iow1.arr[13]; +wire [15:0] Q_28 = ITOP.iow0.arr[14]; +wire [15:0] Q_29 = ITOP.iow1.arr[14]; +wire [15:0] Q_30 = ITOP.iow0.arr[15]; +wire [15:0] Q_31 = ITOP.iow1.arr[15]; +wire [15:0] Q_32 = ITOP.iow0.arr[16]; +wire [15:0] Q_33 = ITOP.iow1.arr[16]; +wire [15:0] Q_34 = ITOP.iow0.arr[17]; +wire [15:0] Q_35 = ITOP.iow1.arr[17]; +wire [15:0] Q_36 = ITOP.iow0.arr[18]; +wire [15:0] Q_37 = ITOP.iow1.arr[18]; +wire [15:0] Q_38 = ITOP.iow0.arr[19]; +wire [15:0] Q_39 = ITOP.iow1.arr[19]; +wire [15:0] Q_40 = ITOP.iow0.arr[20]; +wire [15:0] Q_41 = ITOP.iow1.arr[20]; +wire [15:0] Q_42 = ITOP.iow0.arr[21]; +wire [15:0] Q_43 = ITOP.iow1.arr[21]; +wire [15:0] Q_44 = ITOP.iow0.arr[22]; +wire [15:0] Q_45 = ITOP.iow1.arr[22]; +wire [15:0] Q_46 = ITOP.iow0.arr[23]; +wire [15:0] Q_47 = ITOP.iow1.arr[23]; +wire [15:0] Q_48 = ITOP.iow0.arr[24]; +wire [15:0] Q_49 = ITOP.iow1.arr[24]; +wire [15:0] Q_50 = ITOP.iow0.arr[25]; +wire [15:0] Q_51 = ITOP.iow1.arr[25]; +wire [15:0] Q_52 = ITOP.iow0.arr[26]; +wire [15:0] Q_53 = ITOP.iow1.arr[26]; +wire [15:0] Q_54 = ITOP.iow0.arr[27]; +wire [15:0] Q_55 = ITOP.iow1.arr[27]; +wire [15:0] Q_56 = ITOP.iow0.arr[28]; +wire [15:0] Q_57 = ITOP.iow1.arr[28]; +wire [15:0] Q_58 = ITOP.iow0.arr[29]; +wire [15:0] Q_59 = ITOP.iow1.arr[29]; +wire [15:0] Q_60 = ITOP.iow0.arr[30]; +wire [15:0] Q_61 = ITOP.iow1.arr[30]; +wire [15:0] Q_62 = ITOP.iow0.arr[31]; +wire [15:0] Q_63 = ITOP.iow1.arr[31]; +wire [15:0] Q_64 = ITOP.iow0.arr[32]; +wire [15:0] Q_65 = ITOP.iow1.arr[32]; +wire [15:0] Q_66 = ITOP.iow0.arr[33]; +wire [15:0] Q_67 = ITOP.iow1.arr[33]; +wire [15:0] Q_68 = ITOP.iow0.arr[34]; +wire [15:0] Q_69 = ITOP.iow1.arr[34]; +wire [15:0] Q_70 = ITOP.iow0.arr[35]; +wire [15:0] Q_71 = ITOP.iow1.arr[35]; +wire [15:0] Q_72 = ITOP.iow0.arr[36]; +wire [15:0] Q_73 = ITOP.iow1.arr[36]; +wire [15:0] Q_74 = ITOP.iow0.arr[37]; +wire [15:0] Q_75 = ITOP.iow1.arr[37]; +wire [15:0] Q_76 = ITOP.iow0.arr[38]; +wire [15:0] Q_77 = ITOP.iow1.arr[38]; +wire [15:0] Q_78 = ITOP.iow0.arr[39]; +wire [15:0] Q_79 = ITOP.iow1.arr[39]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [15:0] WD_FF; + reg [15:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [15:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [15:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [15:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X16_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [15:0] WD; +input [7:0] RA, WA; +output [15:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [15:0] WDQ; + wire [15:0] WDBQ; + wire [15:0] WMNexp; + wire [15:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [15:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {16{1'b0}}; + assign SHFT = {16{1'b1}}; + reg [15:0] WDQ_pr; + wire [15:0] WDBQ_pr; + assign WMNexp = {16{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[15:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [15:0] dout; + wire [15:0] RD; + wire RD_rdnt; + wire [15:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [15:0] RDBYPASS = {16{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 128 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[7:7]); +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [15:0] force_x; +`ifndef SYNTHESIS + assign force_x = {16{1'bx}}; +`else + assign force_x = {16{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [15:0] rmuxd0, rmuxd1; + wire [15:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {16{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {16{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {16{RdClk0}} & ~dout0 ; + assign rmuxd1 = {16{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[15:0] <= (rmuxd0[15:0] | rmuxd1[15:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X16_GL_M2_D2_ram # (40, 16, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_80X16_GL_M2_D2_ram # (40, 16, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [15:0] data; + reg [15:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[6:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[6:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [15:0] mem_read_bank; +input [6:0] addr; +reg [15:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[6:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X16_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 40; +parameter bits = 16; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [15:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [15:0] val; + integer i; + begin + val = {16{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [15:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [16-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {16 {1'b1}} `else { $RollPLI(0,{16{1'b1}}) } `endif ; + else raminit_fullval = {16 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + if (addr[0] == 1'b0) + rd = ITOP.iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + rd = ITOP.iow1.mem_read_raw_subbank(addr[6:1]); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [31:0] mem_phys_read_padr; +input [5:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(addr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [31:0] mem_phys_read_ladr; +input [6:0] addr; + reg [5:0] paddr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1:0]; + integer i; + begin + paddr = (addr >> 1); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + rd[1] = ITOP.iow1.mem_read_raw_subbank(paddr); + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [31:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [31:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [32-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {32 {1'b1}} `else { $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {32 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [15:0] rd[1 : 0]; + integer i; + begin + rd[0] = (addr[0:0] === 0) ? ITOP.iow0.mem_read_raw_subbank(addr[6:1]) : 16'bx; + rd[1] = (addr[0:0] === 1) ? ITOP.iow1.mem_read_raw_subbank(addr[6:1]) : 16'bx; + for (i=0; i<=15; i=i+1) begin + rd_row[i*2+0] = rd[0][i]; + rd_row[i*2+1] = rd[1][i]; + end + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [5:0] addr; +input [31:0] data; + reg [15:0] wr[1:0]; + integer i; + begin + for (i=0; i<=15; i=i+1) begin + wr[0][i] = data[i*2+0]; + wr[1][i] = data[i*2+1]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + ITOP.iow1.mem_wr_raw_subbank(addr,wr[1]); + end +endtask +// Function to return a physical address given a logical address input. +function [5:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 1) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + ITOP.iow1.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + ITOP.iow1.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [31:0] mon_bit_w; +input [5:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; + mon_word[1] = ITOP.iow1.bit_written[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [31:0] mon_bit_r; +input [5:0] addr; + reg [31:0] mon_row; + reg [15:0] mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; + mon_word[1] = ITOP.iow1.bit_read[addr]; +// combine all 2 words to a row + for (i=0; i<=15; i=i+1) begin + mon_row[i*2+0] = mon_word[0][i]; + mon_row[i*2+1] = mon_word[1][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; + mon_word[1] = ITOP.iow1.word_written[addr]; +// combine all 2 words to a row + mon_word_w = mon_word[0] | mon_word[1] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [5:0] addr; + reg mon_word[1:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; + mon_word[1] = ITOP.iow1.word_read[addr]; +// combine all 2 words to a row + mon_word_r = mon_word[0] | mon_word[1] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [31:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=40;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=40;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<40; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<32; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [15:0] Q_0 = ITOP.iow0.arr[0]; +wire [15:0] Q_1 = ITOP.iow1.arr[0]; +wire [15:0] Q_2 = ITOP.iow0.arr[1]; +wire [15:0] Q_3 = ITOP.iow1.arr[1]; +wire [15:0] Q_4 = ITOP.iow0.arr[2]; +wire [15:0] Q_5 = ITOP.iow1.arr[2]; +wire [15:0] Q_6 = ITOP.iow0.arr[3]; +wire [15:0] Q_7 = ITOP.iow1.arr[3]; +wire [15:0] Q_8 = ITOP.iow0.arr[4]; +wire [15:0] Q_9 = ITOP.iow1.arr[4]; +wire [15:0] Q_10 = ITOP.iow0.arr[5]; +wire [15:0] Q_11 = ITOP.iow1.arr[5]; +wire [15:0] Q_12 = ITOP.iow0.arr[6]; +wire [15:0] Q_13 = ITOP.iow1.arr[6]; +wire [15:0] Q_14 = ITOP.iow0.arr[7]; +wire [15:0] Q_15 = ITOP.iow1.arr[7]; +wire [15:0] Q_16 = ITOP.iow0.arr[8]; +wire [15:0] Q_17 = ITOP.iow1.arr[8]; +wire [15:0] Q_18 = ITOP.iow0.arr[9]; +wire [15:0] Q_19 = ITOP.iow1.arr[9]; +wire [15:0] Q_20 = ITOP.iow0.arr[10]; +wire [15:0] Q_21 = ITOP.iow1.arr[10]; +wire [15:0] Q_22 = ITOP.iow0.arr[11]; +wire [15:0] Q_23 = ITOP.iow1.arr[11]; +wire [15:0] Q_24 = ITOP.iow0.arr[12]; +wire [15:0] Q_25 = ITOP.iow1.arr[12]; +wire [15:0] Q_26 = ITOP.iow0.arr[13]; +wire [15:0] Q_27 = ITOP.iow1.arr[13]; +wire [15:0] Q_28 = ITOP.iow0.arr[14]; +wire [15:0] Q_29 = ITOP.iow1.arr[14]; +wire [15:0] Q_30 = ITOP.iow0.arr[15]; +wire [15:0] Q_31 = ITOP.iow1.arr[15]; +wire [15:0] Q_32 = ITOP.iow0.arr[16]; +wire [15:0] Q_33 = ITOP.iow1.arr[16]; +wire [15:0] Q_34 = ITOP.iow0.arr[17]; +wire [15:0] Q_35 = ITOP.iow1.arr[17]; +wire [15:0] Q_36 = ITOP.iow0.arr[18]; +wire [15:0] Q_37 = ITOP.iow1.arr[18]; +wire [15:0] Q_38 = ITOP.iow0.arr[19]; +wire [15:0] Q_39 = ITOP.iow1.arr[19]; +wire [15:0] Q_40 = ITOP.iow0.arr[20]; +wire [15:0] Q_41 = ITOP.iow1.arr[20]; +wire [15:0] Q_42 = ITOP.iow0.arr[21]; +wire [15:0] Q_43 = ITOP.iow1.arr[21]; +wire [15:0] Q_44 = ITOP.iow0.arr[22]; +wire [15:0] Q_45 = ITOP.iow1.arr[22]; +wire [15:0] Q_46 = ITOP.iow0.arr[23]; +wire [15:0] Q_47 = ITOP.iow1.arr[23]; +wire [15:0] Q_48 = ITOP.iow0.arr[24]; +wire [15:0] Q_49 = ITOP.iow1.arr[24]; +wire [15:0] Q_50 = ITOP.iow0.arr[25]; +wire [15:0] Q_51 = ITOP.iow1.arr[25]; +wire [15:0] Q_52 = ITOP.iow0.arr[26]; +wire [15:0] Q_53 = ITOP.iow1.arr[26]; +wire [15:0] Q_54 = ITOP.iow0.arr[27]; +wire [15:0] Q_55 = ITOP.iow1.arr[27]; +wire [15:0] Q_56 = ITOP.iow0.arr[28]; +wire [15:0] Q_57 = ITOP.iow1.arr[28]; +wire [15:0] Q_58 = ITOP.iow0.arr[29]; +wire [15:0] Q_59 = ITOP.iow1.arr[29]; +wire [15:0] Q_60 = ITOP.iow0.arr[30]; +wire [15:0] Q_61 = ITOP.iow1.arr[30]; +wire [15:0] Q_62 = ITOP.iow0.arr[31]; +wire [15:0] Q_63 = ITOP.iow1.arr[31]; +wire [15:0] Q_64 = ITOP.iow0.arr[32]; +wire [15:0] Q_65 = ITOP.iow1.arr[32]; +wire [15:0] Q_66 = ITOP.iow0.arr[33]; +wire [15:0] Q_67 = ITOP.iow1.arr[33]; +wire [15:0] Q_68 = ITOP.iow0.arr[34]; +wire [15:0] Q_69 = ITOP.iow1.arr[34]; +wire [15:0] Q_70 = ITOP.iow0.arr[35]; +wire [15:0] Q_71 = ITOP.iow1.arr[35]; +wire [15:0] Q_72 = ITOP.iow0.arr[36]; +wire [15:0] Q_73 = ITOP.iow1.arr[36]; +wire [15:0] Q_74 = ITOP.iow0.arr[37]; +wire [15:0] Q_75 = ITOP.iow1.arr[37]; +wire [15:0] Q_76 = ITOP.iow0.arr[38]; +wire [15:0] Q_77 = ITOP.iow1.arr[38]; +wire [15:0] Q_78 = ITOP.iow0.arr[39]; +wire [15:0] Q_79 = ITOP.iow1.arr[39]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + ITOP.iow1.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [15:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + ITOP.iow1.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_0_subbank((r/2), c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.set_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.set_bit_fault_stuck_1_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_0_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_0_subbank((r/2), c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + if ( (r % 2) == 0) + ITOP.iow0.clear_bit_fault_stuck_1_subbank((r/2), c); + else if ( (r % 2) == 1) + ITOP.iow1.clear_bit_fault_stuck_1_subbank((r/2), c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [7:0] RAFF,WAFF; +// Data + reg [15:0] WD_FF; + reg [15:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [15:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [15:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [15:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X16_GL_M2_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [15:0] WD; +input [7:0] RA, WA; +output [15:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [7:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [7:0] RADRSWI = RADR[7:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [7:0] ADR = {8{RWSEL}} & WAFF | ~{8{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [15:0] WDQ; + wire [15:0] WDBQ; + wire [15:0] WMNexp; + wire [15:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [15:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {16{1'b0}}; + assign SHFT = {16{1'b1}}; + reg [15:0] WDQ_pr; + wire [15:0] WDBQ_pr; + assign WMNexp = {16{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[15:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [15:0] dout; + wire [15:0] RD; + wire RD_rdnt; + wire [15:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [15:0] RDBYPASS = {16{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 1 #lowcmidx 1 #cmstep 1 #cm 2 #maxaddr 128 + wire legal, tiedvalid, empadd; +// Tied off address bits +// This should always be 1 if the tie-off logic at the top-level is correct. + assign tiedvalid = ~(|ADR[7:7]); +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [15:0] force_x; +`ifndef SYNTHESIS + assign force_x = {16{1'bx}}; +`else + assign force_x = {16{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0,RdClk1; + wire WrClk0,WrClk1; + assign RdClk0 = RECLK & ~RADRSWI[0]; + assign RdClk1 = RECLK & RADRSWI[0]; + assign WrClk0 = WECLK & ~WAFF[0] & legal; + assign WrClk1 = WECLK & WAFF[0] & legal; + wire [15:0] rmuxd0, rmuxd1; + wire [15:0] dout0, dout1; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +// assign rmuxd0 = legal ? {16{RdClk0}} & ~dout0 : force_x; +// assign rmuxd1 = legal ? {16{RdClk1}} & ~dout1 : force_x; + assign rmuxd0 = {16{RdClk0}} & ~dout0 ; + assign rmuxd1 = {16{RdClk1}} & ~dout1 ; + always @(RECLK or rmuxd0 or rmuxd1) + begin + if (RECLK) + begin + dout[15:0] <= (rmuxd0[15:0] | rmuxd1[15:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X16_GL_M2_D2_ram # (40, 16, 7) iow0 ( + WAFF[7:1], + WrClk0, + WMNQ, + WDQ, + RADRSWI[7:1], + dout0 + ); + RAMPDP_80X16_GL_M2_D2_ram # (40, 16, 7) iow1 ( + WAFF[7:1], + WrClk1, + WMNQ, + WDQ, + RADRSWI[7:1], + dout1 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [15:0] data; + reg [15:0] wdat; + begin + wdat = data; + if (addr[0] == 1'b0) + iow0.mem_wr_raw_subbank(addr[6:1], wdat); + else if (addr[0] == 1'b1) + iow1.mem_wr_raw_subbank(addr[6:1], wdat); + end +endtask +// Ramgen function for reading the arrays +function [15:0] mem_read_bank; +input [6:0] addr; +reg [15:0] memout; + begin + if (addr[0] == 1'b0) + memout = iow0.mem_read_raw_subbank(addr[6:1]); + else if (addr[0] == 1'b1) + memout = iow1.mem_read_raw_subbank(addr[6:1]); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X16_GL_M2_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 40; +parameter bits = 16; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [225:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [225:0] val; + integer i; + begin + val = {226{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [225:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [225:0] mem_phys_read_padr; +input [6:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [225:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [225:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [225:0] data; + reg [225:0] wr[0:0]; + integer i; + begin + for (i=0; i<=225; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [225:0] mon_bit_w; +input [6:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [225:0] mon_bit_r; +input [6:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [225:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [225:0] Q_0 = ITOP.iow0.arr[0]; +wire [225:0] Q_1 = ITOP.iow0.arr[1]; +wire [225:0] Q_2 = ITOP.iow0.arr[2]; +wire [225:0] Q_3 = ITOP.iow0.arr[3]; +wire [225:0] Q_4 = ITOP.iow0.arr[4]; +wire [225:0] Q_5 = ITOP.iow0.arr[5]; +wire [225:0] Q_6 = ITOP.iow0.arr[6]; +wire [225:0] Q_7 = ITOP.iow0.arr[7]; +wire [225:0] Q_8 = ITOP.iow0.arr[8]; +wire [225:0] Q_9 = ITOP.iow0.arr[9]; +wire [225:0] Q_10 = ITOP.iow0.arr[10]; +wire [225:0] Q_11 = ITOP.iow0.arr[11]; +wire [225:0] Q_12 = ITOP.iow0.arr[12]; +wire [225:0] Q_13 = ITOP.iow0.arr[13]; +wire [225:0] Q_14 = ITOP.iow0.arr[14]; +wire [225:0] Q_15 = ITOP.iow0.arr[15]; +wire [225:0] Q_16 = ITOP.iow0.arr[16]; +wire [225:0] Q_17 = ITOP.iow0.arr[17]; +wire [225:0] Q_18 = ITOP.iow0.arr[18]; +wire [225:0] Q_19 = ITOP.iow0.arr[19]; +wire [225:0] Q_20 = ITOP.iow0.arr[20]; +wire [225:0] Q_21 = ITOP.iow0.arr[21]; +wire [225:0] Q_22 = ITOP.iow0.arr[22]; +wire [225:0] Q_23 = ITOP.iow0.arr[23]; +wire [225:0] Q_24 = ITOP.iow0.arr[24]; +wire [225:0] Q_25 = ITOP.iow0.arr[25]; +wire [225:0] Q_26 = ITOP.iow0.arr[26]; +wire [225:0] Q_27 = ITOP.iow0.arr[27]; +wire [225:0] Q_28 = ITOP.iow0.arr[28]; +wire [225:0] Q_29 = ITOP.iow0.arr[29]; +wire [225:0] Q_30 = ITOP.iow0.arr[30]; +wire [225:0] Q_31 = ITOP.iow0.arr[31]; +wire [225:0] Q_32 = ITOP.iow0.arr[32]; +wire [225:0] Q_33 = ITOP.iow0.arr[33]; +wire [225:0] Q_34 = ITOP.iow0.arr[34]; +wire [225:0] Q_35 = ITOP.iow0.arr[35]; +wire [225:0] Q_36 = ITOP.iow0.arr[36]; +wire [225:0] Q_37 = ITOP.iow0.arr[37]; +wire [225:0] Q_38 = ITOP.iow0.arr[38]; +wire [225:0] Q_39 = ITOP.iow0.arr[39]; +wire [225:0] Q_40 = ITOP.iow0.arr[40]; +wire [225:0] Q_41 = ITOP.iow0.arr[41]; +wire [225:0] Q_42 = ITOP.iow0.arr[42]; +wire [225:0] Q_43 = ITOP.iow0.arr[43]; +wire [225:0] Q_44 = ITOP.iow0.arr[44]; +wire [225:0] Q_45 = ITOP.iow0.arr[45]; +wire [225:0] Q_46 = ITOP.iow0.arr[46]; +wire [225:0] Q_47 = ITOP.iow0.arr[47]; +wire [225:0] Q_48 = ITOP.iow0.arr[48]; +wire [225:0] Q_49 = ITOP.iow0.arr[49]; +wire [225:0] Q_50 = ITOP.iow0.arr[50]; +wire [225:0] Q_51 = ITOP.iow0.arr[51]; +wire [225:0] Q_52 = ITOP.iow0.arr[52]; +wire [225:0] Q_53 = ITOP.iow0.arr[53]; +wire [225:0] Q_54 = ITOP.iow0.arr[54]; +wire [225:0] Q_55 = ITOP.iow0.arr[55]; +wire [225:0] Q_56 = ITOP.iow0.arr[56]; +wire [225:0] Q_57 = ITOP.iow0.arr[57]; +wire [225:0] Q_58 = ITOP.iow0.arr[58]; +wire [225:0] Q_59 = ITOP.iow0.arr[59]; +wire [225:0] Q_60 = ITOP.iow0.arr[60]; +wire [225:0] Q_61 = ITOP.iow0.arr[61]; +wire [225:0] Q_62 = ITOP.iow0.arr[62]; +wire [225:0] Q_63 = ITOP.iow0.arr[63]; +wire [225:0] Q_64 = ITOP.iow0.arr[64]; +wire [225:0] Q_65 = ITOP.iow0.arr[65]; +wire [225:0] Q_66 = ITOP.iow0.arr[66]; +wire [225:0] Q_67 = ITOP.iow0.arr[67]; +wire [225:0] Q_68 = ITOP.iow0.arr[68]; +wire [225:0] Q_69 = ITOP.iow0.arr[69]; +wire [225:0] Q_70 = ITOP.iow0.arr[70]; +wire [225:0] Q_71 = ITOP.iow0.arr[71]; +wire [225:0] Q_72 = ITOP.iow0.arr[72]; +wire [225:0] Q_73 = ITOP.iow0.arr[73]; +wire [225:0] Q_74 = ITOP.iow0.arr[74]; +wire [225:0] Q_75 = ITOP.iow0.arr[75]; +wire [225:0] Q_76 = ITOP.iow0.arr[76]; +wire [225:0] Q_77 = ITOP.iow0.arr[77]; +wire [225:0] Q_78 = ITOP.iow0.arr[78]; +wire [225:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [225:0] WD_FF; + reg [225:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [225:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [225:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [225:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X226_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [225:0] WD; +input [6:0] RA, WA; +output [225:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [225:0] WDQ; + wire [225:0] WDBQ; + wire [225:0] WMNexp; + wire [225:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [225:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {226{1'b0}}; + assign SHFT = {226{1'b1}}; + reg [225:0] WDQ_pr; + wire [225:0] WDBQ_pr; + assign WMNexp = {226{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[225:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [225:0] dout; + wire [225:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [225:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [225:0] RDBYPASS = {226{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [225:0] force_x; +`ifndef SYNTHESIS + assign force_x = {226{1'bx}}; +`else + assign force_x = {226{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [225:0] rmuxd0; + wire [225:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {226{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {226{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[225:0] <= (rmuxd0[225:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X226_GL_M1_D2_ram # (80, 226, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [225:0] data; + reg [225:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [225:0] mem_read_bank; +input [6:0] addr; +reg [225:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X226_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 226; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [225:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [225:0] val; + integer i; + begin + val = {226{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [225:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [225:0] mem_phys_read_padr; +input [6:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [225:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=225; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [225:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [225:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [226-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {226 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {226 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [225:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [225:0] data; + reg [225:0] wr[0:0]; + integer i; + begin + for (i=0; i<=225; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [225:0] mon_bit_w; +input [6:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [225:0] mon_bit_r; +input [6:0] addr; + reg [225:0] mon_row; + reg [225:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=225; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [225:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<226; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [225:0] Q_0 = ITOP.iow0.arr[0]; +wire [225:0] Q_1 = ITOP.iow0.arr[1]; +wire [225:0] Q_2 = ITOP.iow0.arr[2]; +wire [225:0] Q_3 = ITOP.iow0.arr[3]; +wire [225:0] Q_4 = ITOP.iow0.arr[4]; +wire [225:0] Q_5 = ITOP.iow0.arr[5]; +wire [225:0] Q_6 = ITOP.iow0.arr[6]; +wire [225:0] Q_7 = ITOP.iow0.arr[7]; +wire [225:0] Q_8 = ITOP.iow0.arr[8]; +wire [225:0] Q_9 = ITOP.iow0.arr[9]; +wire [225:0] Q_10 = ITOP.iow0.arr[10]; +wire [225:0] Q_11 = ITOP.iow0.arr[11]; +wire [225:0] Q_12 = ITOP.iow0.arr[12]; +wire [225:0] Q_13 = ITOP.iow0.arr[13]; +wire [225:0] Q_14 = ITOP.iow0.arr[14]; +wire [225:0] Q_15 = ITOP.iow0.arr[15]; +wire [225:0] Q_16 = ITOP.iow0.arr[16]; +wire [225:0] Q_17 = ITOP.iow0.arr[17]; +wire [225:0] Q_18 = ITOP.iow0.arr[18]; +wire [225:0] Q_19 = ITOP.iow0.arr[19]; +wire [225:0] Q_20 = ITOP.iow0.arr[20]; +wire [225:0] Q_21 = ITOP.iow0.arr[21]; +wire [225:0] Q_22 = ITOP.iow0.arr[22]; +wire [225:0] Q_23 = ITOP.iow0.arr[23]; +wire [225:0] Q_24 = ITOP.iow0.arr[24]; +wire [225:0] Q_25 = ITOP.iow0.arr[25]; +wire [225:0] Q_26 = ITOP.iow0.arr[26]; +wire [225:0] Q_27 = ITOP.iow0.arr[27]; +wire [225:0] Q_28 = ITOP.iow0.arr[28]; +wire [225:0] Q_29 = ITOP.iow0.arr[29]; +wire [225:0] Q_30 = ITOP.iow0.arr[30]; +wire [225:0] Q_31 = ITOP.iow0.arr[31]; +wire [225:0] Q_32 = ITOP.iow0.arr[32]; +wire [225:0] Q_33 = ITOP.iow0.arr[33]; +wire [225:0] Q_34 = ITOP.iow0.arr[34]; +wire [225:0] Q_35 = ITOP.iow0.arr[35]; +wire [225:0] Q_36 = ITOP.iow0.arr[36]; +wire [225:0] Q_37 = ITOP.iow0.arr[37]; +wire [225:0] Q_38 = ITOP.iow0.arr[38]; +wire [225:0] Q_39 = ITOP.iow0.arr[39]; +wire [225:0] Q_40 = ITOP.iow0.arr[40]; +wire [225:0] Q_41 = ITOP.iow0.arr[41]; +wire [225:0] Q_42 = ITOP.iow0.arr[42]; +wire [225:0] Q_43 = ITOP.iow0.arr[43]; +wire [225:0] Q_44 = ITOP.iow0.arr[44]; +wire [225:0] Q_45 = ITOP.iow0.arr[45]; +wire [225:0] Q_46 = ITOP.iow0.arr[46]; +wire [225:0] Q_47 = ITOP.iow0.arr[47]; +wire [225:0] Q_48 = ITOP.iow0.arr[48]; +wire [225:0] Q_49 = ITOP.iow0.arr[49]; +wire [225:0] Q_50 = ITOP.iow0.arr[50]; +wire [225:0] Q_51 = ITOP.iow0.arr[51]; +wire [225:0] Q_52 = ITOP.iow0.arr[52]; +wire [225:0] Q_53 = ITOP.iow0.arr[53]; +wire [225:0] Q_54 = ITOP.iow0.arr[54]; +wire [225:0] Q_55 = ITOP.iow0.arr[55]; +wire [225:0] Q_56 = ITOP.iow0.arr[56]; +wire [225:0] Q_57 = ITOP.iow0.arr[57]; +wire [225:0] Q_58 = ITOP.iow0.arr[58]; +wire [225:0] Q_59 = ITOP.iow0.arr[59]; +wire [225:0] Q_60 = ITOP.iow0.arr[60]; +wire [225:0] Q_61 = ITOP.iow0.arr[61]; +wire [225:0] Q_62 = ITOP.iow0.arr[62]; +wire [225:0] Q_63 = ITOP.iow0.arr[63]; +wire [225:0] Q_64 = ITOP.iow0.arr[64]; +wire [225:0] Q_65 = ITOP.iow0.arr[65]; +wire [225:0] Q_66 = ITOP.iow0.arr[66]; +wire [225:0] Q_67 = ITOP.iow0.arr[67]; +wire [225:0] Q_68 = ITOP.iow0.arr[68]; +wire [225:0] Q_69 = ITOP.iow0.arr[69]; +wire [225:0] Q_70 = ITOP.iow0.arr[70]; +wire [225:0] Q_71 = ITOP.iow0.arr[71]; +wire [225:0] Q_72 = ITOP.iow0.arr[72]; +wire [225:0] Q_73 = ITOP.iow0.arr[73]; +wire [225:0] Q_74 = ITOP.iow0.arr[74]; +wire [225:0] Q_75 = ITOP.iow0.arr[75]; +wire [225:0] Q_76 = ITOP.iow0.arr[76]; +wire [225:0] Q_77 = ITOP.iow0.arr[77]; +wire [225:0] Q_78 = ITOP.iow0.arr[78]; +wire [225:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [225:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [225:0] WD_FF; + reg [225:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [225:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [225:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [225:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X226_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [225:0] WD; +input [6:0] RA, WA; +output [225:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [225:0] WDQ; + wire [225:0] WDBQ; + wire [225:0] WMNexp; + wire [225:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [225:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {226{1'b0}}; + assign SHFT = {226{1'b1}}; + reg [225:0] WDQ_pr; + wire [225:0] WDBQ_pr; + assign WMNexp = {226{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[225:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [225:0] dout; + wire [225:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [225:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [225:0] RDBYPASS = {226{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [225:0] force_x; +`ifndef SYNTHESIS + assign force_x = {226{1'bx}}; +`else + assign force_x = {226{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [225:0] rmuxd0; + wire [225:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {226{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {226{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[225:0] <= (rmuxd0[225:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X226_GL_M1_D2_ram # (80, 226, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [225:0] data; + reg [225:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [225:0] mem_read_bank; +input [6:0] addr; +reg [225:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X226_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 226; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [255:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [255:0] val; + integer i; + begin + val = {256{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [255:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [255:0] data; + reg [255:0] wr[0:0]; + integer i; + begin + for (i=0; i<=255; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [255:0] Q_0 = ITOP.iow0.arr[0]; +wire [255:0] Q_1 = ITOP.iow0.arr[1]; +wire [255:0] Q_2 = ITOP.iow0.arr[2]; +wire [255:0] Q_3 = ITOP.iow0.arr[3]; +wire [255:0] Q_4 = ITOP.iow0.arr[4]; +wire [255:0] Q_5 = ITOP.iow0.arr[5]; +wire [255:0] Q_6 = ITOP.iow0.arr[6]; +wire [255:0] Q_7 = ITOP.iow0.arr[7]; +wire [255:0] Q_8 = ITOP.iow0.arr[8]; +wire [255:0] Q_9 = ITOP.iow0.arr[9]; +wire [255:0] Q_10 = ITOP.iow0.arr[10]; +wire [255:0] Q_11 = ITOP.iow0.arr[11]; +wire [255:0] Q_12 = ITOP.iow0.arr[12]; +wire [255:0] Q_13 = ITOP.iow0.arr[13]; +wire [255:0] Q_14 = ITOP.iow0.arr[14]; +wire [255:0] Q_15 = ITOP.iow0.arr[15]; +wire [255:0] Q_16 = ITOP.iow0.arr[16]; +wire [255:0] Q_17 = ITOP.iow0.arr[17]; +wire [255:0] Q_18 = ITOP.iow0.arr[18]; +wire [255:0] Q_19 = ITOP.iow0.arr[19]; +wire [255:0] Q_20 = ITOP.iow0.arr[20]; +wire [255:0] Q_21 = ITOP.iow0.arr[21]; +wire [255:0] Q_22 = ITOP.iow0.arr[22]; +wire [255:0] Q_23 = ITOP.iow0.arr[23]; +wire [255:0] Q_24 = ITOP.iow0.arr[24]; +wire [255:0] Q_25 = ITOP.iow0.arr[25]; +wire [255:0] Q_26 = ITOP.iow0.arr[26]; +wire [255:0] Q_27 = ITOP.iow0.arr[27]; +wire [255:0] Q_28 = ITOP.iow0.arr[28]; +wire [255:0] Q_29 = ITOP.iow0.arr[29]; +wire [255:0] Q_30 = ITOP.iow0.arr[30]; +wire [255:0] Q_31 = ITOP.iow0.arr[31]; +wire [255:0] Q_32 = ITOP.iow0.arr[32]; +wire [255:0] Q_33 = ITOP.iow0.arr[33]; +wire [255:0] Q_34 = ITOP.iow0.arr[34]; +wire [255:0] Q_35 = ITOP.iow0.arr[35]; +wire [255:0] Q_36 = ITOP.iow0.arr[36]; +wire [255:0] Q_37 = ITOP.iow0.arr[37]; +wire [255:0] Q_38 = ITOP.iow0.arr[38]; +wire [255:0] Q_39 = ITOP.iow0.arr[39]; +wire [255:0] Q_40 = ITOP.iow0.arr[40]; +wire [255:0] Q_41 = ITOP.iow0.arr[41]; +wire [255:0] Q_42 = ITOP.iow0.arr[42]; +wire [255:0] Q_43 = ITOP.iow0.arr[43]; +wire [255:0] Q_44 = ITOP.iow0.arr[44]; +wire [255:0] Q_45 = ITOP.iow0.arr[45]; +wire [255:0] Q_46 = ITOP.iow0.arr[46]; +wire [255:0] Q_47 = ITOP.iow0.arr[47]; +wire [255:0] Q_48 = ITOP.iow0.arr[48]; +wire [255:0] Q_49 = ITOP.iow0.arr[49]; +wire [255:0] Q_50 = ITOP.iow0.arr[50]; +wire [255:0] Q_51 = ITOP.iow0.arr[51]; +wire [255:0] Q_52 = ITOP.iow0.arr[52]; +wire [255:0] Q_53 = ITOP.iow0.arr[53]; +wire [255:0] Q_54 = ITOP.iow0.arr[54]; +wire [255:0] Q_55 = ITOP.iow0.arr[55]; +wire [255:0] Q_56 = ITOP.iow0.arr[56]; +wire [255:0] Q_57 = ITOP.iow0.arr[57]; +wire [255:0] Q_58 = ITOP.iow0.arr[58]; +wire [255:0] Q_59 = ITOP.iow0.arr[59]; +wire [255:0] Q_60 = ITOP.iow0.arr[60]; +wire [255:0] Q_61 = ITOP.iow0.arr[61]; +wire [255:0] Q_62 = ITOP.iow0.arr[62]; +wire [255:0] Q_63 = ITOP.iow0.arr[63]; +wire [255:0] Q_64 = ITOP.iow0.arr[64]; +wire [255:0] Q_65 = ITOP.iow0.arr[65]; +wire [255:0] Q_66 = ITOP.iow0.arr[66]; +wire [255:0] Q_67 = ITOP.iow0.arr[67]; +wire [255:0] Q_68 = ITOP.iow0.arr[68]; +wire [255:0] Q_69 = ITOP.iow0.arr[69]; +wire [255:0] Q_70 = ITOP.iow0.arr[70]; +wire [255:0] Q_71 = ITOP.iow0.arr[71]; +wire [255:0] Q_72 = ITOP.iow0.arr[72]; +wire [255:0] Q_73 = ITOP.iow0.arr[73]; +wire [255:0] Q_74 = ITOP.iow0.arr[74]; +wire [255:0] Q_75 = ITOP.iow0.arr[75]; +wire [255:0] Q_76 = ITOP.iow0.arr[76]; +wire [255:0] Q_77 = ITOP.iow0.arr[77]; +wire [255:0] Q_78 = ITOP.iow0.arr[78]; +wire [255:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [255:0] WD_FF; + reg [255:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [255:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [255:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [255:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X256_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [255:0] WD; +input [6:0] RA, WA; +output [255:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [255:0] WDQ; + wire [255:0] WDBQ; + wire [255:0] WMNexp; + wire [255:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [255:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {256{1'b0}}; + assign SHFT = {256{1'b1}}; + reg [255:0] WDQ_pr; + wire [255:0] WDBQ_pr; + assign WMNexp = {256{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[255:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [255:0] dout; + wire [255:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [255:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [255:0] RDBYPASS = {256{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [255:0] force_x; +`ifndef SYNTHESIS + assign force_x = {256{1'bx}}; +`else + assign force_x = {256{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [255:0] rmuxd0; + wire [255:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {256{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {256{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[255:0] <= (rmuxd0[255:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X256_GL_M1_D2_ram # (80, 256, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [255:0] data; + reg [255:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [255:0] mem_read_bank; +input [6:0] addr; +reg [255:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X256_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 256; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [255:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [255:0] val; + integer i; + begin + val = {256{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [255:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [255:0] mem_phys_read_padr; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [255:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=255; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [255:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [255:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [256-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {256 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {256 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [255:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [255:0] data; + reg [255:0] wr[0:0]; + integer i; + begin + for (i=0; i<=255; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [255:0] mon_bit_w; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [255:0] mon_bit_r; +input [6:0] addr; + reg [255:0] mon_row; + reg [255:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=255; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [255:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<256; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [255:0] Q_0 = ITOP.iow0.arr[0]; +wire [255:0] Q_1 = ITOP.iow0.arr[1]; +wire [255:0] Q_2 = ITOP.iow0.arr[2]; +wire [255:0] Q_3 = ITOP.iow0.arr[3]; +wire [255:0] Q_4 = ITOP.iow0.arr[4]; +wire [255:0] Q_5 = ITOP.iow0.arr[5]; +wire [255:0] Q_6 = ITOP.iow0.arr[6]; +wire [255:0] Q_7 = ITOP.iow0.arr[7]; +wire [255:0] Q_8 = ITOP.iow0.arr[8]; +wire [255:0] Q_9 = ITOP.iow0.arr[9]; +wire [255:0] Q_10 = ITOP.iow0.arr[10]; +wire [255:0] Q_11 = ITOP.iow0.arr[11]; +wire [255:0] Q_12 = ITOP.iow0.arr[12]; +wire [255:0] Q_13 = ITOP.iow0.arr[13]; +wire [255:0] Q_14 = ITOP.iow0.arr[14]; +wire [255:0] Q_15 = ITOP.iow0.arr[15]; +wire [255:0] Q_16 = ITOP.iow0.arr[16]; +wire [255:0] Q_17 = ITOP.iow0.arr[17]; +wire [255:0] Q_18 = ITOP.iow0.arr[18]; +wire [255:0] Q_19 = ITOP.iow0.arr[19]; +wire [255:0] Q_20 = ITOP.iow0.arr[20]; +wire [255:0] Q_21 = ITOP.iow0.arr[21]; +wire [255:0] Q_22 = ITOP.iow0.arr[22]; +wire [255:0] Q_23 = ITOP.iow0.arr[23]; +wire [255:0] Q_24 = ITOP.iow0.arr[24]; +wire [255:0] Q_25 = ITOP.iow0.arr[25]; +wire [255:0] Q_26 = ITOP.iow0.arr[26]; +wire [255:0] Q_27 = ITOP.iow0.arr[27]; +wire [255:0] Q_28 = ITOP.iow0.arr[28]; +wire [255:0] Q_29 = ITOP.iow0.arr[29]; +wire [255:0] Q_30 = ITOP.iow0.arr[30]; +wire [255:0] Q_31 = ITOP.iow0.arr[31]; +wire [255:0] Q_32 = ITOP.iow0.arr[32]; +wire [255:0] Q_33 = ITOP.iow0.arr[33]; +wire [255:0] Q_34 = ITOP.iow0.arr[34]; +wire [255:0] Q_35 = ITOP.iow0.arr[35]; +wire [255:0] Q_36 = ITOP.iow0.arr[36]; +wire [255:0] Q_37 = ITOP.iow0.arr[37]; +wire [255:0] Q_38 = ITOP.iow0.arr[38]; +wire [255:0] Q_39 = ITOP.iow0.arr[39]; +wire [255:0] Q_40 = ITOP.iow0.arr[40]; +wire [255:0] Q_41 = ITOP.iow0.arr[41]; +wire [255:0] Q_42 = ITOP.iow0.arr[42]; +wire [255:0] Q_43 = ITOP.iow0.arr[43]; +wire [255:0] Q_44 = ITOP.iow0.arr[44]; +wire [255:0] Q_45 = ITOP.iow0.arr[45]; +wire [255:0] Q_46 = ITOP.iow0.arr[46]; +wire [255:0] Q_47 = ITOP.iow0.arr[47]; +wire [255:0] Q_48 = ITOP.iow0.arr[48]; +wire [255:0] Q_49 = ITOP.iow0.arr[49]; +wire [255:0] Q_50 = ITOP.iow0.arr[50]; +wire [255:0] Q_51 = ITOP.iow0.arr[51]; +wire [255:0] Q_52 = ITOP.iow0.arr[52]; +wire [255:0] Q_53 = ITOP.iow0.arr[53]; +wire [255:0] Q_54 = ITOP.iow0.arr[54]; +wire [255:0] Q_55 = ITOP.iow0.arr[55]; +wire [255:0] Q_56 = ITOP.iow0.arr[56]; +wire [255:0] Q_57 = ITOP.iow0.arr[57]; +wire [255:0] Q_58 = ITOP.iow0.arr[58]; +wire [255:0] Q_59 = ITOP.iow0.arr[59]; +wire [255:0] Q_60 = ITOP.iow0.arr[60]; +wire [255:0] Q_61 = ITOP.iow0.arr[61]; +wire [255:0] Q_62 = ITOP.iow0.arr[62]; +wire [255:0] Q_63 = ITOP.iow0.arr[63]; +wire [255:0] Q_64 = ITOP.iow0.arr[64]; +wire [255:0] Q_65 = ITOP.iow0.arr[65]; +wire [255:0] Q_66 = ITOP.iow0.arr[66]; +wire [255:0] Q_67 = ITOP.iow0.arr[67]; +wire [255:0] Q_68 = ITOP.iow0.arr[68]; +wire [255:0] Q_69 = ITOP.iow0.arr[69]; +wire [255:0] Q_70 = ITOP.iow0.arr[70]; +wire [255:0] Q_71 = ITOP.iow0.arr[71]; +wire [255:0] Q_72 = ITOP.iow0.arr[72]; +wire [255:0] Q_73 = ITOP.iow0.arr[73]; +wire [255:0] Q_74 = ITOP.iow0.arr[74]; +wire [255:0] Q_75 = ITOP.iow0.arr[75]; +wire [255:0] Q_76 = ITOP.iow0.arr[76]; +wire [255:0] Q_77 = ITOP.iow0.arr[77]; +wire [255:0] Q_78 = ITOP.iow0.arr[78]; +wire [255:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [255:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [255:0] WD_FF; + reg [255:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [255:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [255:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [255:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X256_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [255:0] WD; +input [6:0] RA, WA; +output [255:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [255:0] WDQ; + wire [255:0] WDBQ; + wire [255:0] WMNexp; + wire [255:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [255:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {256{1'b0}}; + assign SHFT = {256{1'b1}}; + reg [255:0] WDQ_pr; + wire [255:0] WDBQ_pr; + assign WMNexp = {256{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[255:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [255:0] dout; + wire [255:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [255:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [255:0] RDBYPASS = {256{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [255:0] force_x; +`ifndef SYNTHESIS + assign force_x = {256{1'bx}}; +`else + assign force_x = {256{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [255:0] rmuxd0; + wire [255:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {256{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {256{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[255:0] <= (rmuxd0[255:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X256_GL_M1_D2_ram # (80, 256, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [255:0] data; + reg [255:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [255:0] mem_read_bank; +input [6:0] addr; +reg [255:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X256_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 256; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [287:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [287:0] val; + integer i; + begin + val = {288{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [287:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [287:0] wr[0:0]; + integer i; + begin + for (i=0; i<=287; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [287:0] Q_0 = ITOP.iow0.arr[0]; +wire [287:0] Q_1 = ITOP.iow0.arr[1]; +wire [287:0] Q_2 = ITOP.iow0.arr[2]; +wire [287:0] Q_3 = ITOP.iow0.arr[3]; +wire [287:0] Q_4 = ITOP.iow0.arr[4]; +wire [287:0] Q_5 = ITOP.iow0.arr[5]; +wire [287:0] Q_6 = ITOP.iow0.arr[6]; +wire [287:0] Q_7 = ITOP.iow0.arr[7]; +wire [287:0] Q_8 = ITOP.iow0.arr[8]; +wire [287:0] Q_9 = ITOP.iow0.arr[9]; +wire [287:0] Q_10 = ITOP.iow0.arr[10]; +wire [287:0] Q_11 = ITOP.iow0.arr[11]; +wire [287:0] Q_12 = ITOP.iow0.arr[12]; +wire [287:0] Q_13 = ITOP.iow0.arr[13]; +wire [287:0] Q_14 = ITOP.iow0.arr[14]; +wire [287:0] Q_15 = ITOP.iow0.arr[15]; +wire [287:0] Q_16 = ITOP.iow0.arr[16]; +wire [287:0] Q_17 = ITOP.iow0.arr[17]; +wire [287:0] Q_18 = ITOP.iow0.arr[18]; +wire [287:0] Q_19 = ITOP.iow0.arr[19]; +wire [287:0] Q_20 = ITOP.iow0.arr[20]; +wire [287:0] Q_21 = ITOP.iow0.arr[21]; +wire [287:0] Q_22 = ITOP.iow0.arr[22]; +wire [287:0] Q_23 = ITOP.iow0.arr[23]; +wire [287:0] Q_24 = ITOP.iow0.arr[24]; +wire [287:0] Q_25 = ITOP.iow0.arr[25]; +wire [287:0] Q_26 = ITOP.iow0.arr[26]; +wire [287:0] Q_27 = ITOP.iow0.arr[27]; +wire [287:0] Q_28 = ITOP.iow0.arr[28]; +wire [287:0] Q_29 = ITOP.iow0.arr[29]; +wire [287:0] Q_30 = ITOP.iow0.arr[30]; +wire [287:0] Q_31 = ITOP.iow0.arr[31]; +wire [287:0] Q_32 = ITOP.iow0.arr[32]; +wire [287:0] Q_33 = ITOP.iow0.arr[33]; +wire [287:0] Q_34 = ITOP.iow0.arr[34]; +wire [287:0] Q_35 = ITOP.iow0.arr[35]; +wire [287:0] Q_36 = ITOP.iow0.arr[36]; +wire [287:0] Q_37 = ITOP.iow0.arr[37]; +wire [287:0] Q_38 = ITOP.iow0.arr[38]; +wire [287:0] Q_39 = ITOP.iow0.arr[39]; +wire [287:0] Q_40 = ITOP.iow0.arr[40]; +wire [287:0] Q_41 = ITOP.iow0.arr[41]; +wire [287:0] Q_42 = ITOP.iow0.arr[42]; +wire [287:0] Q_43 = ITOP.iow0.arr[43]; +wire [287:0] Q_44 = ITOP.iow0.arr[44]; +wire [287:0] Q_45 = ITOP.iow0.arr[45]; +wire [287:0] Q_46 = ITOP.iow0.arr[46]; +wire [287:0] Q_47 = ITOP.iow0.arr[47]; +wire [287:0] Q_48 = ITOP.iow0.arr[48]; +wire [287:0] Q_49 = ITOP.iow0.arr[49]; +wire [287:0] Q_50 = ITOP.iow0.arr[50]; +wire [287:0] Q_51 = ITOP.iow0.arr[51]; +wire [287:0] Q_52 = ITOP.iow0.arr[52]; +wire [287:0] Q_53 = ITOP.iow0.arr[53]; +wire [287:0] Q_54 = ITOP.iow0.arr[54]; +wire [287:0] Q_55 = ITOP.iow0.arr[55]; +wire [287:0] Q_56 = ITOP.iow0.arr[56]; +wire [287:0] Q_57 = ITOP.iow0.arr[57]; +wire [287:0] Q_58 = ITOP.iow0.arr[58]; +wire [287:0] Q_59 = ITOP.iow0.arr[59]; +wire [287:0] Q_60 = ITOP.iow0.arr[60]; +wire [287:0] Q_61 = ITOP.iow0.arr[61]; +wire [287:0] Q_62 = ITOP.iow0.arr[62]; +wire [287:0] Q_63 = ITOP.iow0.arr[63]; +wire [287:0] Q_64 = ITOP.iow0.arr[64]; +wire [287:0] Q_65 = ITOP.iow0.arr[65]; +wire [287:0] Q_66 = ITOP.iow0.arr[66]; +wire [287:0] Q_67 = ITOP.iow0.arr[67]; +wire [287:0] Q_68 = ITOP.iow0.arr[68]; +wire [287:0] Q_69 = ITOP.iow0.arr[69]; +wire [287:0] Q_70 = ITOP.iow0.arr[70]; +wire [287:0] Q_71 = ITOP.iow0.arr[71]; +wire [287:0] Q_72 = ITOP.iow0.arr[72]; +wire [287:0] Q_73 = ITOP.iow0.arr[73]; +wire [287:0] Q_74 = ITOP.iow0.arr[74]; +wire [287:0] Q_75 = ITOP.iow0.arr[75]; +wire [287:0] Q_76 = ITOP.iow0.arr[76]; +wire [287:0] Q_77 = ITOP.iow0.arr[77]; +wire [287:0] Q_78 = ITOP.iow0.arr[78]; +wire [287:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [287:0] WD_FF; + reg [287:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [287:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [287:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [287:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X288_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [287:0] WD; +input [6:0] RA, WA; +output [287:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [287:0] WDQ; + wire [287:0] WDBQ; + wire [287:0] WMNexp; + wire [287:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [287:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {288{1'b0}}; + assign SHFT = {288{1'b1}}; + reg [287:0] WDQ_pr; + wire [287:0] WDBQ_pr; + assign WMNexp = {288{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[287:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [287:0] dout; + wire [287:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [287:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [287:0] RDBYPASS = {288{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [287:0] force_x; +`ifndef SYNTHESIS + assign force_x = {288{1'bx}}; +`else + assign force_x = {288{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [287:0] rmuxd0; + wire [287:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {288{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {288{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[287:0] <= (rmuxd0[287:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X288_GL_M1_D2_ram # (80, 288, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [287:0] data; + reg [287:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [287:0] mem_read_bank; +input [6:0] addr; +reg [287:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X288_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 288; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [287:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random, $random, $random, $random, $random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [287:0] val; + integer i; + begin + val = {288{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [287:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [287:0] mem_phys_read_padr; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [287:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=287; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [287:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [287:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [288-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {288 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}) } `endif ; + else raminit_fullval = {288 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [287:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [287:0] data; + reg [287:0] wr[0:0]; + integer i; + begin + for (i=0; i<=287; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [287:0] mon_bit_w; +input [6:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [287:0] mon_bit_r; +input [6:0] addr; + reg [287:0] mon_row; + reg [287:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=287; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [287:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<288; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [287:0] Q_0 = ITOP.iow0.arr[0]; +wire [287:0] Q_1 = ITOP.iow0.arr[1]; +wire [287:0] Q_2 = ITOP.iow0.arr[2]; +wire [287:0] Q_3 = ITOP.iow0.arr[3]; +wire [287:0] Q_4 = ITOP.iow0.arr[4]; +wire [287:0] Q_5 = ITOP.iow0.arr[5]; +wire [287:0] Q_6 = ITOP.iow0.arr[6]; +wire [287:0] Q_7 = ITOP.iow0.arr[7]; +wire [287:0] Q_8 = ITOP.iow0.arr[8]; +wire [287:0] Q_9 = ITOP.iow0.arr[9]; +wire [287:0] Q_10 = ITOP.iow0.arr[10]; +wire [287:0] Q_11 = ITOP.iow0.arr[11]; +wire [287:0] Q_12 = ITOP.iow0.arr[12]; +wire [287:0] Q_13 = ITOP.iow0.arr[13]; +wire [287:0] Q_14 = ITOP.iow0.arr[14]; +wire [287:0] Q_15 = ITOP.iow0.arr[15]; +wire [287:0] Q_16 = ITOP.iow0.arr[16]; +wire [287:0] Q_17 = ITOP.iow0.arr[17]; +wire [287:0] Q_18 = ITOP.iow0.arr[18]; +wire [287:0] Q_19 = ITOP.iow0.arr[19]; +wire [287:0] Q_20 = ITOP.iow0.arr[20]; +wire [287:0] Q_21 = ITOP.iow0.arr[21]; +wire [287:0] Q_22 = ITOP.iow0.arr[22]; +wire [287:0] Q_23 = ITOP.iow0.arr[23]; +wire [287:0] Q_24 = ITOP.iow0.arr[24]; +wire [287:0] Q_25 = ITOP.iow0.arr[25]; +wire [287:0] Q_26 = ITOP.iow0.arr[26]; +wire [287:0] Q_27 = ITOP.iow0.arr[27]; +wire [287:0] Q_28 = ITOP.iow0.arr[28]; +wire [287:0] Q_29 = ITOP.iow0.arr[29]; +wire [287:0] Q_30 = ITOP.iow0.arr[30]; +wire [287:0] Q_31 = ITOP.iow0.arr[31]; +wire [287:0] Q_32 = ITOP.iow0.arr[32]; +wire [287:0] Q_33 = ITOP.iow0.arr[33]; +wire [287:0] Q_34 = ITOP.iow0.arr[34]; +wire [287:0] Q_35 = ITOP.iow0.arr[35]; +wire [287:0] Q_36 = ITOP.iow0.arr[36]; +wire [287:0] Q_37 = ITOP.iow0.arr[37]; +wire [287:0] Q_38 = ITOP.iow0.arr[38]; +wire [287:0] Q_39 = ITOP.iow0.arr[39]; +wire [287:0] Q_40 = ITOP.iow0.arr[40]; +wire [287:0] Q_41 = ITOP.iow0.arr[41]; +wire [287:0] Q_42 = ITOP.iow0.arr[42]; +wire [287:0] Q_43 = ITOP.iow0.arr[43]; +wire [287:0] Q_44 = ITOP.iow0.arr[44]; +wire [287:0] Q_45 = ITOP.iow0.arr[45]; +wire [287:0] Q_46 = ITOP.iow0.arr[46]; +wire [287:0] Q_47 = ITOP.iow0.arr[47]; +wire [287:0] Q_48 = ITOP.iow0.arr[48]; +wire [287:0] Q_49 = ITOP.iow0.arr[49]; +wire [287:0] Q_50 = ITOP.iow0.arr[50]; +wire [287:0] Q_51 = ITOP.iow0.arr[51]; +wire [287:0] Q_52 = ITOP.iow0.arr[52]; +wire [287:0] Q_53 = ITOP.iow0.arr[53]; +wire [287:0] Q_54 = ITOP.iow0.arr[54]; +wire [287:0] Q_55 = ITOP.iow0.arr[55]; +wire [287:0] Q_56 = ITOP.iow0.arr[56]; +wire [287:0] Q_57 = ITOP.iow0.arr[57]; +wire [287:0] Q_58 = ITOP.iow0.arr[58]; +wire [287:0] Q_59 = ITOP.iow0.arr[59]; +wire [287:0] Q_60 = ITOP.iow0.arr[60]; +wire [287:0] Q_61 = ITOP.iow0.arr[61]; +wire [287:0] Q_62 = ITOP.iow0.arr[62]; +wire [287:0] Q_63 = ITOP.iow0.arr[63]; +wire [287:0] Q_64 = ITOP.iow0.arr[64]; +wire [287:0] Q_65 = ITOP.iow0.arr[65]; +wire [287:0] Q_66 = ITOP.iow0.arr[66]; +wire [287:0] Q_67 = ITOP.iow0.arr[67]; +wire [287:0] Q_68 = ITOP.iow0.arr[68]; +wire [287:0] Q_69 = ITOP.iow0.arr[69]; +wire [287:0] Q_70 = ITOP.iow0.arr[70]; +wire [287:0] Q_71 = ITOP.iow0.arr[71]; +wire [287:0] Q_72 = ITOP.iow0.arr[72]; +wire [287:0] Q_73 = ITOP.iow0.arr[73]; +wire [287:0] Q_74 = ITOP.iow0.arr[74]; +wire [287:0] Q_75 = ITOP.iow0.arr[75]; +wire [287:0] Q_76 = ITOP.iow0.arr[76]; +wire [287:0] Q_77 = ITOP.iow0.arr[77]; +wire [287:0] Q_78 = ITOP.iow0.arr[78]; +wire [287:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [287:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [287:0] WD_FF; + reg [287:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [287:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [287:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [287:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X288_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [287:0] WD; +input [6:0] RA, WA; +output [287:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [287:0] WDQ; + wire [287:0] WDBQ; + wire [287:0] WMNexp; + wire [287:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [287:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {288{1'b0}}; + assign SHFT = {288{1'b1}}; + reg [287:0] WDQ_pr; + wire [287:0] WDBQ_pr; + assign WMNexp = {288{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[287:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [287:0] dout; + wire [287:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [287:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [287:0] RDBYPASS = {288{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [287:0] force_x; +`ifndef SYNTHESIS + assign force_x = {288{1'bx}}; +`else + assign force_x = {288{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [287:0] rmuxd0; + wire [287:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {288{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {288{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[287:0] <= (rmuxd0[287:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X288_GL_M1_D2_ram # (80, 288, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [287:0] data; + reg [287:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [287:0] mem_read_bank; +input [6:0] addr; +reg [287:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X288_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 288; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [65:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [65:0] val; + integer i; + begin + val = {66{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [65:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [65:0] mem_phys_read_padr; +input [6:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [65:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [65:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [65:0] data; + reg [65:0] wr[0:0]; + integer i; + begin + for (i=0; i<=65; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [65:0] mon_bit_w; +input [6:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [65:0] mon_bit_r; +input [6:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [65:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [65:0] Q_0 = ITOP.iow0.arr[0]; +wire [65:0] Q_1 = ITOP.iow0.arr[1]; +wire [65:0] Q_2 = ITOP.iow0.arr[2]; +wire [65:0] Q_3 = ITOP.iow0.arr[3]; +wire [65:0] Q_4 = ITOP.iow0.arr[4]; +wire [65:0] Q_5 = ITOP.iow0.arr[5]; +wire [65:0] Q_6 = ITOP.iow0.arr[6]; +wire [65:0] Q_7 = ITOP.iow0.arr[7]; +wire [65:0] Q_8 = ITOP.iow0.arr[8]; +wire [65:0] Q_9 = ITOP.iow0.arr[9]; +wire [65:0] Q_10 = ITOP.iow0.arr[10]; +wire [65:0] Q_11 = ITOP.iow0.arr[11]; +wire [65:0] Q_12 = ITOP.iow0.arr[12]; +wire [65:0] Q_13 = ITOP.iow0.arr[13]; +wire [65:0] Q_14 = ITOP.iow0.arr[14]; +wire [65:0] Q_15 = ITOP.iow0.arr[15]; +wire [65:0] Q_16 = ITOP.iow0.arr[16]; +wire [65:0] Q_17 = ITOP.iow0.arr[17]; +wire [65:0] Q_18 = ITOP.iow0.arr[18]; +wire [65:0] Q_19 = ITOP.iow0.arr[19]; +wire [65:0] Q_20 = ITOP.iow0.arr[20]; +wire [65:0] Q_21 = ITOP.iow0.arr[21]; +wire [65:0] Q_22 = ITOP.iow0.arr[22]; +wire [65:0] Q_23 = ITOP.iow0.arr[23]; +wire [65:0] Q_24 = ITOP.iow0.arr[24]; +wire [65:0] Q_25 = ITOP.iow0.arr[25]; +wire [65:0] Q_26 = ITOP.iow0.arr[26]; +wire [65:0] Q_27 = ITOP.iow0.arr[27]; +wire [65:0] Q_28 = ITOP.iow0.arr[28]; +wire [65:0] Q_29 = ITOP.iow0.arr[29]; +wire [65:0] Q_30 = ITOP.iow0.arr[30]; +wire [65:0] Q_31 = ITOP.iow0.arr[31]; +wire [65:0] Q_32 = ITOP.iow0.arr[32]; +wire [65:0] Q_33 = ITOP.iow0.arr[33]; +wire [65:0] Q_34 = ITOP.iow0.arr[34]; +wire [65:0] Q_35 = ITOP.iow0.arr[35]; +wire [65:0] Q_36 = ITOP.iow0.arr[36]; +wire [65:0] Q_37 = ITOP.iow0.arr[37]; +wire [65:0] Q_38 = ITOP.iow0.arr[38]; +wire [65:0] Q_39 = ITOP.iow0.arr[39]; +wire [65:0] Q_40 = ITOP.iow0.arr[40]; +wire [65:0] Q_41 = ITOP.iow0.arr[41]; +wire [65:0] Q_42 = ITOP.iow0.arr[42]; +wire [65:0] Q_43 = ITOP.iow0.arr[43]; +wire [65:0] Q_44 = ITOP.iow0.arr[44]; +wire [65:0] Q_45 = ITOP.iow0.arr[45]; +wire [65:0] Q_46 = ITOP.iow0.arr[46]; +wire [65:0] Q_47 = ITOP.iow0.arr[47]; +wire [65:0] Q_48 = ITOP.iow0.arr[48]; +wire [65:0] Q_49 = ITOP.iow0.arr[49]; +wire [65:0] Q_50 = ITOP.iow0.arr[50]; +wire [65:0] Q_51 = ITOP.iow0.arr[51]; +wire [65:0] Q_52 = ITOP.iow0.arr[52]; +wire [65:0] Q_53 = ITOP.iow0.arr[53]; +wire [65:0] Q_54 = ITOP.iow0.arr[54]; +wire [65:0] Q_55 = ITOP.iow0.arr[55]; +wire [65:0] Q_56 = ITOP.iow0.arr[56]; +wire [65:0] Q_57 = ITOP.iow0.arr[57]; +wire [65:0] Q_58 = ITOP.iow0.arr[58]; +wire [65:0] Q_59 = ITOP.iow0.arr[59]; +wire [65:0] Q_60 = ITOP.iow0.arr[60]; +wire [65:0] Q_61 = ITOP.iow0.arr[61]; +wire [65:0] Q_62 = ITOP.iow0.arr[62]; +wire [65:0] Q_63 = ITOP.iow0.arr[63]; +wire [65:0] Q_64 = ITOP.iow0.arr[64]; +wire [65:0] Q_65 = ITOP.iow0.arr[65]; +wire [65:0] Q_66 = ITOP.iow0.arr[66]; +wire [65:0] Q_67 = ITOP.iow0.arr[67]; +wire [65:0] Q_68 = ITOP.iow0.arr[68]; +wire [65:0] Q_69 = ITOP.iow0.arr[69]; +wire [65:0] Q_70 = ITOP.iow0.arr[70]; +wire [65:0] Q_71 = ITOP.iow0.arr[71]; +wire [65:0] Q_72 = ITOP.iow0.arr[72]; +wire [65:0] Q_73 = ITOP.iow0.arr[73]; +wire [65:0] Q_74 = ITOP.iow0.arr[74]; +wire [65:0] Q_75 = ITOP.iow0.arr[75]; +wire [65:0] Q_76 = ITOP.iow0.arr[76]; +wire [65:0] Q_77 = ITOP.iow0.arr[77]; +wire [65:0] Q_78 = ITOP.iow0.arr[78]; +wire [65:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [65:0] WD_FF; + reg [65:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [65:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [65:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [65:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X66_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [65:0] WD; +input [6:0] RA, WA; +output [65:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [65:0] WDQ; + wire [65:0] WDBQ; + wire [65:0] WMNexp; + wire [65:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [65:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {66{1'b0}}; + assign SHFT = {66{1'b1}}; + reg [65:0] WDQ_pr; + wire [65:0] WDBQ_pr; + assign WMNexp = {66{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[65:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [65:0] dout; + wire [65:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [65:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [65:0] RDBYPASS = {66{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [65:0] force_x; +`ifndef SYNTHESIS + assign force_x = {66{1'bx}}; +`else + assign force_x = {66{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [65:0] rmuxd0; + wire [65:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {66{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {66{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[65:0] <= (rmuxd0[65:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X66_GL_M1_D2_ram # (80, 66, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [65:0] data; + reg [65:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [65:0] mem_read_bank; +input [6:0] addr; +reg [65:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X66_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 66; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [65:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [65:0] val; + integer i; + begin + val = {66{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [65:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [65:0] mem_phys_read_padr; +input [6:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [65:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=65; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [65:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [65:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [66-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {66 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{2{1'b1}}) } `endif ; + else raminit_fullval = {66 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [65:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [65:0] data; + reg [65:0] wr[0:0]; + integer i; + begin + for (i=0; i<=65; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [65:0] mon_bit_w; +input [6:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [65:0] mon_bit_r; +input [6:0] addr; + reg [65:0] mon_row; + reg [65:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=65; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [65:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<66; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [65:0] Q_0 = ITOP.iow0.arr[0]; +wire [65:0] Q_1 = ITOP.iow0.arr[1]; +wire [65:0] Q_2 = ITOP.iow0.arr[2]; +wire [65:0] Q_3 = ITOP.iow0.arr[3]; +wire [65:0] Q_4 = ITOP.iow0.arr[4]; +wire [65:0] Q_5 = ITOP.iow0.arr[5]; +wire [65:0] Q_6 = ITOP.iow0.arr[6]; +wire [65:0] Q_7 = ITOP.iow0.arr[7]; +wire [65:0] Q_8 = ITOP.iow0.arr[8]; +wire [65:0] Q_9 = ITOP.iow0.arr[9]; +wire [65:0] Q_10 = ITOP.iow0.arr[10]; +wire [65:0] Q_11 = ITOP.iow0.arr[11]; +wire [65:0] Q_12 = ITOP.iow0.arr[12]; +wire [65:0] Q_13 = ITOP.iow0.arr[13]; +wire [65:0] Q_14 = ITOP.iow0.arr[14]; +wire [65:0] Q_15 = ITOP.iow0.arr[15]; +wire [65:0] Q_16 = ITOP.iow0.arr[16]; +wire [65:0] Q_17 = ITOP.iow0.arr[17]; +wire [65:0] Q_18 = ITOP.iow0.arr[18]; +wire [65:0] Q_19 = ITOP.iow0.arr[19]; +wire [65:0] Q_20 = ITOP.iow0.arr[20]; +wire [65:0] Q_21 = ITOP.iow0.arr[21]; +wire [65:0] Q_22 = ITOP.iow0.arr[22]; +wire [65:0] Q_23 = ITOP.iow0.arr[23]; +wire [65:0] Q_24 = ITOP.iow0.arr[24]; +wire [65:0] Q_25 = ITOP.iow0.arr[25]; +wire [65:0] Q_26 = ITOP.iow0.arr[26]; +wire [65:0] Q_27 = ITOP.iow0.arr[27]; +wire [65:0] Q_28 = ITOP.iow0.arr[28]; +wire [65:0] Q_29 = ITOP.iow0.arr[29]; +wire [65:0] Q_30 = ITOP.iow0.arr[30]; +wire [65:0] Q_31 = ITOP.iow0.arr[31]; +wire [65:0] Q_32 = ITOP.iow0.arr[32]; +wire [65:0] Q_33 = ITOP.iow0.arr[33]; +wire [65:0] Q_34 = ITOP.iow0.arr[34]; +wire [65:0] Q_35 = ITOP.iow0.arr[35]; +wire [65:0] Q_36 = ITOP.iow0.arr[36]; +wire [65:0] Q_37 = ITOP.iow0.arr[37]; +wire [65:0] Q_38 = ITOP.iow0.arr[38]; +wire [65:0] Q_39 = ITOP.iow0.arr[39]; +wire [65:0] Q_40 = ITOP.iow0.arr[40]; +wire [65:0] Q_41 = ITOP.iow0.arr[41]; +wire [65:0] Q_42 = ITOP.iow0.arr[42]; +wire [65:0] Q_43 = ITOP.iow0.arr[43]; +wire [65:0] Q_44 = ITOP.iow0.arr[44]; +wire [65:0] Q_45 = ITOP.iow0.arr[45]; +wire [65:0] Q_46 = ITOP.iow0.arr[46]; +wire [65:0] Q_47 = ITOP.iow0.arr[47]; +wire [65:0] Q_48 = ITOP.iow0.arr[48]; +wire [65:0] Q_49 = ITOP.iow0.arr[49]; +wire [65:0] Q_50 = ITOP.iow0.arr[50]; +wire [65:0] Q_51 = ITOP.iow0.arr[51]; +wire [65:0] Q_52 = ITOP.iow0.arr[52]; +wire [65:0] Q_53 = ITOP.iow0.arr[53]; +wire [65:0] Q_54 = ITOP.iow0.arr[54]; +wire [65:0] Q_55 = ITOP.iow0.arr[55]; +wire [65:0] Q_56 = ITOP.iow0.arr[56]; +wire [65:0] Q_57 = ITOP.iow0.arr[57]; +wire [65:0] Q_58 = ITOP.iow0.arr[58]; +wire [65:0] Q_59 = ITOP.iow0.arr[59]; +wire [65:0] Q_60 = ITOP.iow0.arr[60]; +wire [65:0] Q_61 = ITOP.iow0.arr[61]; +wire [65:0] Q_62 = ITOP.iow0.arr[62]; +wire [65:0] Q_63 = ITOP.iow0.arr[63]; +wire [65:0] Q_64 = ITOP.iow0.arr[64]; +wire [65:0] Q_65 = ITOP.iow0.arr[65]; +wire [65:0] Q_66 = ITOP.iow0.arr[66]; +wire [65:0] Q_67 = ITOP.iow0.arr[67]; +wire [65:0] Q_68 = ITOP.iow0.arr[68]; +wire [65:0] Q_69 = ITOP.iow0.arr[69]; +wire [65:0] Q_70 = ITOP.iow0.arr[70]; +wire [65:0] Q_71 = ITOP.iow0.arr[71]; +wire [65:0] Q_72 = ITOP.iow0.arr[72]; +wire [65:0] Q_73 = ITOP.iow0.arr[73]; +wire [65:0] Q_74 = ITOP.iow0.arr[74]; +wire [65:0] Q_75 = ITOP.iow0.arr[75]; +wire [65:0] Q_76 = ITOP.iow0.arr[76]; +wire [65:0] Q_77 = ITOP.iow0.arr[77]; +wire [65:0] Q_78 = ITOP.iow0.arr[78]; +wire [65:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [65:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [65:0] WD_FF; + reg [65:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [65:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [65:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [65:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X66_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [65:0] WD; +input [6:0] RA, WA; +output [65:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [65:0] WDQ; + wire [65:0] WDBQ; + wire [65:0] WMNexp; + wire [65:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [65:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {66{1'b0}}; + assign SHFT = {66{1'b1}}; + reg [65:0] WDQ_pr; + wire [65:0] WDBQ_pr; + assign WMNexp = {66{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[65:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [65:0] dout; + wire [65:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [65:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [65:0] RDBYPASS = {66{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [65:0] force_x; +`ifndef SYNTHESIS + assign force_x = {66{1'bx}}; +`else + assign force_x = {66{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [65:0] rmuxd0; + wire [65:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {66{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {66{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[65:0] <= (rmuxd0[65:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X66_GL_M1_D2_ram # (80, 66, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [65:0] data; + reg [65:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [65:0] mem_read_bank; +input [6:0] addr; +reg [65:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X66_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 66; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [71:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [71:0] val; + integer i; + begin + val = {72{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [71:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [71:0] mem_phys_read_padr; +input [6:0] addr; + reg [71:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [71:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [71:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [71:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [71:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [71:0] data; + reg [71:0] wr[0:0]; + integer i; + begin + for (i=0; i<=71; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [71:0] mon_bit_w; +input [6:0] addr; + reg [71:0] mon_row; + reg [71:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [71:0] mon_bit_r; +input [6:0] addr; + reg [71:0] mon_row; + reg [71:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [71:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [71:0] Q_0 = ITOP.iow0.arr[0]; +wire [71:0] Q_1 = ITOP.iow0.arr[1]; +wire [71:0] Q_2 = ITOP.iow0.arr[2]; +wire [71:0] Q_3 = ITOP.iow0.arr[3]; +wire [71:0] Q_4 = ITOP.iow0.arr[4]; +wire [71:0] Q_5 = ITOP.iow0.arr[5]; +wire [71:0] Q_6 = ITOP.iow0.arr[6]; +wire [71:0] Q_7 = ITOP.iow0.arr[7]; +wire [71:0] Q_8 = ITOP.iow0.arr[8]; +wire [71:0] Q_9 = ITOP.iow0.arr[9]; +wire [71:0] Q_10 = ITOP.iow0.arr[10]; +wire [71:0] Q_11 = ITOP.iow0.arr[11]; +wire [71:0] Q_12 = ITOP.iow0.arr[12]; +wire [71:0] Q_13 = ITOP.iow0.arr[13]; +wire [71:0] Q_14 = ITOP.iow0.arr[14]; +wire [71:0] Q_15 = ITOP.iow0.arr[15]; +wire [71:0] Q_16 = ITOP.iow0.arr[16]; +wire [71:0] Q_17 = ITOP.iow0.arr[17]; +wire [71:0] Q_18 = ITOP.iow0.arr[18]; +wire [71:0] Q_19 = ITOP.iow0.arr[19]; +wire [71:0] Q_20 = ITOP.iow0.arr[20]; +wire [71:0] Q_21 = ITOP.iow0.arr[21]; +wire [71:0] Q_22 = ITOP.iow0.arr[22]; +wire [71:0] Q_23 = ITOP.iow0.arr[23]; +wire [71:0] Q_24 = ITOP.iow0.arr[24]; +wire [71:0] Q_25 = ITOP.iow0.arr[25]; +wire [71:0] Q_26 = ITOP.iow0.arr[26]; +wire [71:0] Q_27 = ITOP.iow0.arr[27]; +wire [71:0] Q_28 = ITOP.iow0.arr[28]; +wire [71:0] Q_29 = ITOP.iow0.arr[29]; +wire [71:0] Q_30 = ITOP.iow0.arr[30]; +wire [71:0] Q_31 = ITOP.iow0.arr[31]; +wire [71:0] Q_32 = ITOP.iow0.arr[32]; +wire [71:0] Q_33 = ITOP.iow0.arr[33]; +wire [71:0] Q_34 = ITOP.iow0.arr[34]; +wire [71:0] Q_35 = ITOP.iow0.arr[35]; +wire [71:0] Q_36 = ITOP.iow0.arr[36]; +wire [71:0] Q_37 = ITOP.iow0.arr[37]; +wire [71:0] Q_38 = ITOP.iow0.arr[38]; +wire [71:0] Q_39 = ITOP.iow0.arr[39]; +wire [71:0] Q_40 = ITOP.iow0.arr[40]; +wire [71:0] Q_41 = ITOP.iow0.arr[41]; +wire [71:0] Q_42 = ITOP.iow0.arr[42]; +wire [71:0] Q_43 = ITOP.iow0.arr[43]; +wire [71:0] Q_44 = ITOP.iow0.arr[44]; +wire [71:0] Q_45 = ITOP.iow0.arr[45]; +wire [71:0] Q_46 = ITOP.iow0.arr[46]; +wire [71:0] Q_47 = ITOP.iow0.arr[47]; +wire [71:0] Q_48 = ITOP.iow0.arr[48]; +wire [71:0] Q_49 = ITOP.iow0.arr[49]; +wire [71:0] Q_50 = ITOP.iow0.arr[50]; +wire [71:0] Q_51 = ITOP.iow0.arr[51]; +wire [71:0] Q_52 = ITOP.iow0.arr[52]; +wire [71:0] Q_53 = ITOP.iow0.arr[53]; +wire [71:0] Q_54 = ITOP.iow0.arr[54]; +wire [71:0] Q_55 = ITOP.iow0.arr[55]; +wire [71:0] Q_56 = ITOP.iow0.arr[56]; +wire [71:0] Q_57 = ITOP.iow0.arr[57]; +wire [71:0] Q_58 = ITOP.iow0.arr[58]; +wire [71:0] Q_59 = ITOP.iow0.arr[59]; +wire [71:0] Q_60 = ITOP.iow0.arr[60]; +wire [71:0] Q_61 = ITOP.iow0.arr[61]; +wire [71:0] Q_62 = ITOP.iow0.arr[62]; +wire [71:0] Q_63 = ITOP.iow0.arr[63]; +wire [71:0] Q_64 = ITOP.iow0.arr[64]; +wire [71:0] Q_65 = ITOP.iow0.arr[65]; +wire [71:0] Q_66 = ITOP.iow0.arr[66]; +wire [71:0] Q_67 = ITOP.iow0.arr[67]; +wire [71:0] Q_68 = ITOP.iow0.arr[68]; +wire [71:0] Q_69 = ITOP.iow0.arr[69]; +wire [71:0] Q_70 = ITOP.iow0.arr[70]; +wire [71:0] Q_71 = ITOP.iow0.arr[71]; +wire [71:0] Q_72 = ITOP.iow0.arr[72]; +wire [71:0] Q_73 = ITOP.iow0.arr[73]; +wire [71:0] Q_74 = ITOP.iow0.arr[74]; +wire [71:0] Q_75 = ITOP.iow0.arr[75]; +wire [71:0] Q_76 = ITOP.iow0.arr[76]; +wire [71:0] Q_77 = ITOP.iow0.arr[77]; +wire [71:0] Q_78 = ITOP.iow0.arr[78]; +wire [71:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [71:0] WD_FF; + reg [71:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [71:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [71:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [71:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X72_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [71:0] WD; +input [6:0] RA, WA; +output [71:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [71:0] WDQ; + wire [71:0] WDBQ; + wire [71:0] WMNexp; + wire [71:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [71:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {72{1'b0}}; + assign SHFT = {72{1'b1}}; + reg [71:0] WDQ_pr; + wire [71:0] WDBQ_pr; + assign WMNexp = {72{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[71:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [71:0] dout; + wire [71:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [71:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [71:0] RDBYPASS = {72{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [71:0] force_x; +`ifndef SYNTHESIS + assign force_x = {72{1'bx}}; +`else + assign force_x = {72{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [71:0] rmuxd0; + wire [71:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {72{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {72{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[71:0] <= (rmuxd0[71:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X72_GL_M1_D2_ram # (80, 72, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [71:0] data; + reg [71:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [71:0] mem_read_bank; +input [6:0] addr; +reg [71:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X72_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 72; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i 32, call it multiple times +// Old random fill fills all memory locations with same random value +task mem_fill_random; + reg [71:0] val; + integer i; + begin + for (i=0; i<80; i=i+1) begin + val = {$random, $random, $random}; + mem_wr_raw(i, val); + end + end +endtask +// Fill the memory with a given bit value +task mem_fill_value; + input fill_bit; + reg [71:0] val; + integer i; + begin + val = {72{fill_bit}}; + for (i=0; i<80; i=i+1) begin + mem_wr_raw(i, val); + end + end +endtask +// read logical address and feed into salat +task force_rd; +input [6:0] addr; + reg [71:0] rd; + `ifdef USE_RAMINIT_LIBS + reg raminit_active, raminit_argcheck, raminit_debug, raminit_enable, raminit_random, raminit_invert, + raminit_val, raminit_waitclock, raminit_use_force; + real raminit_delay_ns, raminit_waitclock_check_ns; + initial + begin + raminit_active = 0; // default is inactive (plusarg to active the ram init functionality) + raminit_argcheck = 0; // default is no plusargs check (apart from raminit_active and raminit_argcheck) + raminit_debug = 0; // default is no debug messages + raminit_enable = 0; // default is no init (variable indicating if the ram init functionality is enabled for this instance) + raminit_random = 0; // default is no random init + raminit_invert = 0; // default is not to invert the init value + raminit_val = 0; // default init value is zero + raminit_waitclock = 0; // default is not to wait to clock to be non-X + raminit_use_force = 1; // default is to use force/release + raminit_delay_ns = `ifdef NV_TOP_RESET_ON_DELAY (`NV_TOP_RESET_ON_DELAY+2) `else 3 `endif; // default is 2ns after nv_top_reset_ goes low or ram clock is not X + raminit_waitclock_check_ns = `ifdef NV_TOP_RESET_OFF_DELAY (`NV_TOP_RESET_OFF_DELAY) `else 0 `endif; // default is when nv_top_reset_ goes high + $value$plusargs("raminit_active=%d", raminit_active); + $value$plusargs("raminit_argcheck=%d", raminit_argcheck); + if (raminit_argcheck) + begin +// The following variables are not usually used as plusargs, but instead set through add_inst_array calls or the init_inst_file. + $value$plusargs("raminit_debug=%d", raminit_debug); + $value$plusargs("raminit_enable=%d", raminit_enable); + $value$plusargs("raminit_random=%d", raminit_random); + $value$plusargs("raminit_invert=%d", raminit_invert); + $value$plusargs("raminit_val=%d", raminit_val); + $value$plusargs("raminit_waitclock=%d", raminit_waitclock); + $value$plusargs("raminit_delay_ns=%f", raminit_delay_ns); + $value$plusargs("raminit_waitclock_check_ns=%f", raminit_waitclock_check_ns); + $value$plusargs("raminit_use_force=%d", raminit_use_force); + end + `ifdef INST_CHECK + `INST_CHECK(ram_inst_check0,raminit_active,raminit_debug,raminit_enable,raminit_random,raminit_val,raminit_invert,raminit_waitclock,raminit_delay_ns,raminit_waitclock_check_ns); + `endif + if (!raminit_active) raminit_enable = 0; + else if (raminit_enable) + begin + if (raminit_random) raminit_val = `ifdef NO_PLI 1'b0 `else $RollPLI(0,1) `endif; + if (raminit_invert) raminit_val = ~raminit_val; + end + if (raminit_debug) + begin + $display("%m: raminit_active = %d", raminit_active); + $display("%m: raminit_argcheck = %d", raminit_argcheck); + $display("%m: raminit_debug = %d", raminit_debug); + $display("%m: raminit_enable = %d", raminit_enable); + $display("%m: raminit_random = %d", raminit_random); + $display("%m: raminit_invert = %d", raminit_invert); + $display("%m: raminit_val = %d", raminit_val); + $display("%m: raminit_waitclock = %d", raminit_waitclock); + $display("%m: raminit_delay_ns = %f ns", raminit_delay_ns); + $display("%m: raminit_waitclock_check_ns = %f ns", raminit_waitclock_check_ns); + $display("%m: raminit_use_force = %d", raminit_use_force); + end + end + `endif + `ifdef USE_RAMINIT_LIBS +// init rd + task init_rd_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check0,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd; + rd = raminit_fullval; + end + end + endtask + initial begin init_rd_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + begin + rd = ITOP.iow0.mem_read_raw_subbank(addr); + ITOP.dout = rd; + end +endtask +`ifdef MEM_PHYS_INFO +//function for physical array read row, takes physical address +function [71:0] mem_phys_read_padr; +input [6:0] addr; + reg [71:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check1,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[0:0]; + integer i; + begin + rd[0] = ITOP.iow0.mem_read_raw_subbank(addr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_padr = rd_row; + end +endfunction +//function for physical array read row, takes logical address +function [71:0] mem_phys_read_ladr; +input [6:0] addr; + reg [6:0] paddr; + reg [71:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check2,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[0:0]; + integer i; + begin + paddr = (addr >> 0); + rd[0] = ITOP.iow0.mem_read_raw_subbank(paddr); + for (i=0; i<=71; i=i+1) begin + rd_row[i*1+0] = rd[0][i]; + end + mem_phys_read_ladr = rd_row; + end +endfunction +//function for physical array read row with column masking, takes logical address +function [71:0] mem_phys_read_pmasked; +input [6:0] addr; + reg [71:0] rd_row; + `ifdef USE_RAMINIT_LIBS +// init rd_row + task init_rd_row_regs; + begin + #0; // wait for raminit variables to be set + if (raminit_enable) + begin : raminit_val_blk + reg [72-1:0] raminit_fullval; + if (raminit_random) raminit_fullval = `ifdef NO_PLI {72 {1'b1}} `else { $RollPLI(0,{32{1'b1}}), $RollPLI(0,{32{1'b1}}), $RollPLI(0,{8{1'b1}}) } `endif ; + else raminit_fullval = {72 {raminit_val}}; + if (raminit_invert) raminit_fullval = ~raminit_fullval; + if (raminit_use_force) force rd_row = raminit_fullval; + if (raminit_waitclock) wait ( !== 1'bx); + #(raminit_delay_ns*100); + `ifdef INST_WAITCLOCK_CHECK + `INST_WAITCLOCK_CHECK(waitclock_inst_check3,raminit_waitclock,raminit_waitclock_check_ns,100) + `endif + if (raminit_use_force) release rd_row; + rd_row = raminit_fullval; + end + end + endtask + initial begin init_rd_row_regs(); end + `ifdef RAMINIT_TRIGGER + always @(`RAMINIT_TRIGGER) init_rd_row_regs(); + `endif + `endif // `ifdef USE_RAMINIT_LIBS + reg [71:0] rd[0 : 0]; + integer i; + begin + rd_row = ITOP.iow0.mem_read_raw_subbank(addr); + mem_phys_read_pmasked = rd_row; + end +endfunction +//Task for physical array write row, takes physical address +task mem_phys_write; +input [6:0] addr; +input [71:0] data; + reg [71:0] wr[0:0]; + integer i; + begin + for (i=0; i<=71; i=i+1) begin + wr[0][i] = data[i*1+0]; + end + ITOP.iow0.mem_wr_raw_subbank(addr,wr[0]); + end +endtask +// Function to return a physical address given a logical address input. +function [6:0] mem_log_to_phys_adr; +input [6:0] addr; + begin + mem_log_to_phys_adr = (addr >> 0) ; + end +endfunction +`endif //MEM_PHYS_INFO +`ifdef MONITOR +// Monitor dump trigger +reg dump_monitor_result; +initial begin : init_monitor + dump_monitor_result = 1'b0; +end +task monitor_on; + begin + ITOP.iow0.monitor_on = 1'b1; + end +endtask +task monitor_off; + begin + ITOP.iow0.monitor_on = 1'b0; + dump_monitor_result = 1'b1; + end +endtask +// read bit_written monitor row by physical address from subarray +function [71:0] mon_bit_w; +input [6:0] addr; + reg [71:0] mon_row; + reg [71:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_written[addr]; +// combine all 1 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_w = mon_row; + end +endfunction +// read bit_read monitor word by address from subarray +function [71:0] mon_bit_r; +input [6:0] addr; + reg [71:0] mon_row; + reg [71:0] mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.bit_read[addr]; +// combine all 1 words to a row + for (i=0; i<=71; i=i+1) begin + mon_row[i*1+0] = mon_word[0][i]; + end + mon_bit_r = mon_row; + end +endfunction +// read word_written monitor row by physical address from subarray +function mon_word_w; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_written[addr]; +// combine all 1 words to a row + mon_word_w = mon_word[0] ; + end +endfunction +// read word_read monitor row by physical address from subarray +function mon_word_r; +input [6:0] addr; + reg mon_word[0:0]; + integer i; + begin +// read all monitor words for a row + mon_word[0] = ITOP.iow0.word_read[addr]; +// combine all 1 words to a row + mon_word_r = mon_word[0] ; + end +endfunction +always @(dump_monitor_result) begin : dump_monitor + integer i; + integer j; + reg [71:0] tmp_row; + reg tmp_bit; + if (dump_monitor_result == 1'b1) begin + $display("Exercised coverage summary:"); + $display("\t%m rows unwritten:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_w(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m rows unread:"); + for(i=0;i<=80;i=i+1) begin + tmp_bit = mon_word_r(i); + if (tmp_bit !== 1) $display("\t\trow %d", i); + end + $display("\t%m bits not written as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not written as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_w(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 0:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b0 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + $display("\t%m bits not read as 1:"); + for (i=0; i<80; i=i+1) begin + tmp_row = mon_bit_r(i); + for (j=0; j<72; j=j+1) begin + if (tmp_row[j] !== 1'b1 && tmp_row[j] !== 1'bz) $display("\t\t[row,bit] [%d,%d]", i, j); + end + end + dump_monitor_result = 1'b0; + end +end +//VCS coverage on +`endif // MONITOR +`ifdef NV_RAM_EXPAND_ARRAY +wire [71:0] Q_0 = ITOP.iow0.arr[0]; +wire [71:0] Q_1 = ITOP.iow0.arr[1]; +wire [71:0] Q_2 = ITOP.iow0.arr[2]; +wire [71:0] Q_3 = ITOP.iow0.arr[3]; +wire [71:0] Q_4 = ITOP.iow0.arr[4]; +wire [71:0] Q_5 = ITOP.iow0.arr[5]; +wire [71:0] Q_6 = ITOP.iow0.arr[6]; +wire [71:0] Q_7 = ITOP.iow0.arr[7]; +wire [71:0] Q_8 = ITOP.iow0.arr[8]; +wire [71:0] Q_9 = ITOP.iow0.arr[9]; +wire [71:0] Q_10 = ITOP.iow0.arr[10]; +wire [71:0] Q_11 = ITOP.iow0.arr[11]; +wire [71:0] Q_12 = ITOP.iow0.arr[12]; +wire [71:0] Q_13 = ITOP.iow0.arr[13]; +wire [71:0] Q_14 = ITOP.iow0.arr[14]; +wire [71:0] Q_15 = ITOP.iow0.arr[15]; +wire [71:0] Q_16 = ITOP.iow0.arr[16]; +wire [71:0] Q_17 = ITOP.iow0.arr[17]; +wire [71:0] Q_18 = ITOP.iow0.arr[18]; +wire [71:0] Q_19 = ITOP.iow0.arr[19]; +wire [71:0] Q_20 = ITOP.iow0.arr[20]; +wire [71:0] Q_21 = ITOP.iow0.arr[21]; +wire [71:0] Q_22 = ITOP.iow0.arr[22]; +wire [71:0] Q_23 = ITOP.iow0.arr[23]; +wire [71:0] Q_24 = ITOP.iow0.arr[24]; +wire [71:0] Q_25 = ITOP.iow0.arr[25]; +wire [71:0] Q_26 = ITOP.iow0.arr[26]; +wire [71:0] Q_27 = ITOP.iow0.arr[27]; +wire [71:0] Q_28 = ITOP.iow0.arr[28]; +wire [71:0] Q_29 = ITOP.iow0.arr[29]; +wire [71:0] Q_30 = ITOP.iow0.arr[30]; +wire [71:0] Q_31 = ITOP.iow0.arr[31]; +wire [71:0] Q_32 = ITOP.iow0.arr[32]; +wire [71:0] Q_33 = ITOP.iow0.arr[33]; +wire [71:0] Q_34 = ITOP.iow0.arr[34]; +wire [71:0] Q_35 = ITOP.iow0.arr[35]; +wire [71:0] Q_36 = ITOP.iow0.arr[36]; +wire [71:0] Q_37 = ITOP.iow0.arr[37]; +wire [71:0] Q_38 = ITOP.iow0.arr[38]; +wire [71:0] Q_39 = ITOP.iow0.arr[39]; +wire [71:0] Q_40 = ITOP.iow0.arr[40]; +wire [71:0] Q_41 = ITOP.iow0.arr[41]; +wire [71:0] Q_42 = ITOP.iow0.arr[42]; +wire [71:0] Q_43 = ITOP.iow0.arr[43]; +wire [71:0] Q_44 = ITOP.iow0.arr[44]; +wire [71:0] Q_45 = ITOP.iow0.arr[45]; +wire [71:0] Q_46 = ITOP.iow0.arr[46]; +wire [71:0] Q_47 = ITOP.iow0.arr[47]; +wire [71:0] Q_48 = ITOP.iow0.arr[48]; +wire [71:0] Q_49 = ITOP.iow0.arr[49]; +wire [71:0] Q_50 = ITOP.iow0.arr[50]; +wire [71:0] Q_51 = ITOP.iow0.arr[51]; +wire [71:0] Q_52 = ITOP.iow0.arr[52]; +wire [71:0] Q_53 = ITOP.iow0.arr[53]; +wire [71:0] Q_54 = ITOP.iow0.arr[54]; +wire [71:0] Q_55 = ITOP.iow0.arr[55]; +wire [71:0] Q_56 = ITOP.iow0.arr[56]; +wire [71:0] Q_57 = ITOP.iow0.arr[57]; +wire [71:0] Q_58 = ITOP.iow0.arr[58]; +wire [71:0] Q_59 = ITOP.iow0.arr[59]; +wire [71:0] Q_60 = ITOP.iow0.arr[60]; +wire [71:0] Q_61 = ITOP.iow0.arr[61]; +wire [71:0] Q_62 = ITOP.iow0.arr[62]; +wire [71:0] Q_63 = ITOP.iow0.arr[63]; +wire [71:0] Q_64 = ITOP.iow0.arr[64]; +wire [71:0] Q_65 = ITOP.iow0.arr[65]; +wire [71:0] Q_66 = ITOP.iow0.arr[66]; +wire [71:0] Q_67 = ITOP.iow0.arr[67]; +wire [71:0] Q_68 = ITOP.iow0.arr[68]; +wire [71:0] Q_69 = ITOP.iow0.arr[69]; +wire [71:0] Q_70 = ITOP.iow0.arr[70]; +wire [71:0] Q_71 = ITOP.iow0.arr[71]; +wire [71:0] Q_72 = ITOP.iow0.arr[72]; +wire [71:0] Q_73 = ITOP.iow0.arr[73]; +wire [71:0] Q_74 = ITOP.iow0.arr[74]; +wire [71:0] Q_75 = ITOP.iow0.arr[75]; +wire [71:0] Q_76 = ITOP.iow0.arr[76]; +wire [71:0] Q_77 = ITOP.iow0.arr[77]; +wire [71:0] Q_78 = ITOP.iow0.arr[78]; +wire [71:0] Q_79 = ITOP.iow0.arr[79]; +`endif //NV_RAM_EXPAND_ARRAY +`endif //SYNTHESIS +`ifdef FAULT_INJECTION +// BIST stuck at tasks +// induce faults on columns +//VCS coverage off +task mem_fault_no_write; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_no_write_subbank(fault_mask); + end +endtask +task mem_fault_stuck_0; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_0_subbank(fault_mask); + end +endtask +task mem_fault_stuck_1; +input [71:0] fault_mask; + begin + ITOP.iow0.mem_fault_stuck_1_subbank(fault_mask); + end +endtask +task set_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_0_subbank(r, c); +endtask +task set_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.set_bit_fault_stuck_1_subbank(r, c); +endtask +task clear_bit_fault_stuck_0; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_0_subbank(r, c); +endtask +task clear_bit_fault_stuck_1; +input r; +input c; +integer r; +integer c; + ITOP.iow0.clear_bit_fault_stuck_1_subbank(r, c); +endtask +//VCS coverage on +`endif // STUCK +`else // EMULATION=1 +//VCS coverage off +// The emulation model is a simple model which models only basic functionality and contains no test logic or redundancy. +// The model also uses flops wherever possible. Latches are avoided to help close timing on the emulator. +// The unused pins are left floating in the model. +// Register declarations +// enables + reg RE_FF,WE_FF,RE_LAT,WE_LAT; +// Addresses + reg [6:0] RAFF,WAFF; +// Data + reg [71:0] WD_FF; + reg [71:0] RD_LAT; +// Latch the enables +//spyglass disable_block IntClock,W18 + always @(*) begin + if (!CLK) begin + RE_LAT <= RE; + WE_LAT <= WE; + end + end +//spyglass enable_block IntClock,W18 +// Flop the enables : RE/WE/RE_O + always @(posedge CLK) begin + RE_FF <= RE; //spyglass disable IntClock + WE_FF <= WE; //spyglass disable IntClock + end +// Gated clock for the read/write operations + wire RECLK = CLK & RE_LAT; //spyglass disable GatedClock + wire WECLK = CLK & WE_LAT; //spyglass disable GatedClock +// Flop the addresses/write data//mask + always @(posedge RECLK) + RAFF <= RA; //spyglass disable IntClock + always @(posedge WECLK) begin + WAFF <= WA; //spyglass disable IntClock + WD_FF <= WD; //spyglass disable IntClock + end +// Memory + reg [71:0] mem[79:0]; +// write into the memory on negative edge of clock + wire WRCLK = ~CLK & WE_FF ; //spyglass disable GatedClock + always @(posedge WRCLK) + mem[WAFF] <= WD_FF; //spyglass disable SYNTH_5130 +// Read + wire [71:0] dout; + assign dout = mem[RAFF]; //spyglass disable SYNTH_5130 + reg [71:0] dout_LAT; + always @(RECLK or dout) + if (RECLK) + dout_LAT <= dout; //spyglass disable W18 + assign RD = dout_LAT; +`endif // EMULATION +//VCS coverage on +`endif // end RAM_INTERFACE +endmodule +`endcelldefine +`ifndef RAM_INTERFACE +`ifndef EMULATION +//memory bank block +module RAM_BANK_RAMPDP_80X72_GL_M1_D2 ( WE, CLK, IDDQ, SVOP, WD, RD, RE, RA, WA +, SLEEP_EN +, RET_EN , clobber_array , clobber_flops +); +// Input/output port definitions +input WE, CLK, IDDQ , RE; +input [7:0] SVOP; +input [71:0] WD; +input [6:0] RA, WA; +output [71:0] RD; +input [7:0] SLEEP_EN; +input RET_EN , clobber_array , clobber_flops ; +// When there is no bypass requested, tie the internal bypass select to 0. + wire RDBYP = 1'b0; +//Definitions of latches and flops in the design +// *_LAT --> Latched value +// *_LATB --> inverted latch value +// *_FF --> Flopped version + reg RE_LATB, RE_FF, WE_LATB, WE_FF; + reg [6:0] RADR, WADR, WAFF; +// For non-pipelined rams , capture_dis is disabled + wire CAPT_DIS = 1'b0; +// Clamp the array access when IDDQ=1 + wire CLAMPB = ~IDDQ; + wire latffclk = CLK; +// Latch and flop the primary control enables. This is on the unconditional clock. +// spyglass disable_block W18 + always @(*) begin +// Latch part + if(!latffclk & !clobber_flops) begin + RE_LATB <= ~RE ; +// Write Enable + WE_LATB <= ~WE; // spyglass disable IntClock + end // end if + end // end always + always @(*) begin +// Flop part + if (latffclk & !clobber_flops) begin +// Flop outputs of the latches above + WE_FF <= ~WE_LATB; + RE_FF <= ~RE_LATB; + end // end if + end // end always +// spyglass enable_block W18 +// Conditional clock generation. +// Write enable and clock +// Clocks are generated when the write enable OR SE == 1 , but SHOLD == 0 + wire we_se = ~WE_LATB; + wire WRDCLK = we_se & latffclk & !clobber_flops; // spyglass disable GatedClock + wire WADRCLK = WRDCLK; +// Read enable and clock +// There is no SHOLD dependence on the read clocks because these are implemented using loopback flops +// Clocks are generated when the Read enable OR SE == 1 + wire re_se = ~RE_LATB; + wire RADRCLK = re_se & latffclk ; +// *** The model reads in A , writes in B *** +// Read clock to the memory is off the rising edge of clock +// CLk ==1 , when RE=1 or (SE=1 and SCRE=1) && (ACC_DIS == 1) +// SE=1 and SCRE=1 is needed to force known values into the latches for launch in testmodes. + wire RECLK = (~RE_LATB) & CLAMPB & !clobber_flops & !RET_EN & CLK; +// Writes are shifted to the low phase of the clock +// Flopped version of the enables are used to prevent glitches in the clock +// SCWI ==1 prevents writes into the memory + wire WECLK = WE_FF & CLAMPB & !clobber_flops & !RET_EN & ~CLK; + wire RWSEL = WE_FF & CLAMPB & ~CLK; +// Latch read addresses +// spyglass disable_block W18 + always @(*) begin + if(!RADRCLK & !clobber_flops) begin + RADR <= RA; + end // end if + end // end always +// Flop write address + always @(posedge WADRCLK) begin + WAFF <= WA ; + end +// spyglass enable_block W18 +// Force the MSB's to 0 in the SCRE mode. This makes sure that we will always read in from valid addresses for resetting the output latches. + wire [6:0] RADRSWI = RADR[6:0]; +// Select the read address when CLK=1 and write addresses when CLK=0 + wire [6:0] ADR = {7{RWSEL}} & WAFF | ~{7{RWSEL}} & RADRSWI; + wire [7:0] fusePDEC2; + wire [7:0] fusePDEC1; + wire [7:0] fusePDEC0; + wire fuseien; +// Non repairable rams + assign fusePDEC2 = {8{1'b0}}; + assign fusePDEC1 = {8{1'b0}}; + assign fusePDEC0 = {8{1'b0}}; + assign fuseien = 0; +//io part + wire [71:0] WDQ; + wire [71:0] WDBQ; + wire [71:0] WMNexp; + wire [71:0] WMNQ; +// Expand the fuse predec to 512 bits . It follows the 8x8x8 repeat pattern +// We will use only the ones needed for this particular ram configuration and ignore the rest + wire [511:0] PDEC2 = {{64{fusePDEC2[7]}}, {64{fusePDEC2[6]}}, {64{fusePDEC2[5]}}, {64{fusePDEC2[4]}}, {64{fusePDEC2[3]}}, {64{fusePDEC2[2]}}, {64{fusePDEC2[1]}}, {64{fusePDEC2[0]}}}; + wire [511:0] PDEC1 = {8{{8{fusePDEC1[7]}}, {8{fusePDEC1[6]}}, {8{fusePDEC1[5]}}, {8{fusePDEC1[4]}}, {8{fusePDEC1[3]}}, {8{fusePDEC1[2]}}, {8{fusePDEC1[1]}}, {8{fusePDEC1[0]}}}}; + wire [511:0] PDEC0 = {64{fusePDEC0[7:0]}}; + wire [71:0] BADBIT, SHFT; +// SHIFT<*> == 1 --> No repair at that bit , 0 --> repair at that bit . +// SHIFT == not(and Pdec*) & SHIFT + assign BADBIT = {72{1'b0}}; + assign SHFT = {72{1'b1}}; + reg [71:0] WDQ_pr; + wire [71:0] WDBQ_pr; + assign WMNexp = {72{1'b1}}; + always @(posedge WRDCLK) begin +// Flop write data + WDQ_pr[71:0] <= WD & WMNexp; + end + assign WDBQ_pr = ~WDQ_pr; + assign WMNQ = (WDQ | WDBQ); + assign WDQ = WDQ_pr; + assign WDBQ = WDBQ_pr; + reg [71:0] dout; + wire [71:0] RD; + wire RD_rdnt0,RD_rdnt1; + wire [71:0] sel_normal, sel_redun; +// Read bypass is not used for non custom ram + wire [71:0] RDBYPASS = {72{1'b0}}; +// Read bypass will override redunancy mux . + assign sel_redun = ~SHFT & ~RDBYPASS; + assign sel_normal = SHFT & ~RDBYPASS; +// Non pipelined Read out. This is a 2 to 1 mux with bypass taking priority + assign RD = sel_normal & dout | RDBYPASS & WDQ_pr; +// FOR SIMULATION ONLY. REMOVE WHEN ASSERTIONS ARE AVAILABLE! +// The following section figures out the unused address space and forces a X out on the reads/prevents writes +// #unusedbits 0 #lowcmidx 0 #cmstep 1 #cm 1 #maxaddr 128 + wire legal, tiedvalid, empadd; + assign tiedvalid = 1'b1; +// Max address is 80 --> ['1', '0', '0', '1', '1', '1', '1'] +// If the address falls within the space covered by valid address bits , but is > NE , then assign 1 to empadd to indicate it is an invalid address + assign empadd = ADR[6] & ADR[5] | + ADR[6] & ADR[4]; +// It is a legal input address if it does not fall in the empty space. + assign legal = tiedvalid & ~empadd ; + wire [71:0] force_x; +`ifndef SYNTHESIS + assign force_x = {72{1'bx}}; +`else + assign force_x = {72{1'b0}}; +`endif +// Generate the read and write clocks for the various CM banks + wire RdClk0; + wire WrClk0; + assign RdClk0 = RECLK; + assign WrClk0 = WECLK & legal; + wire [71:0] rmuxd0; + wire [71:0] dout0; +// Mux the way reads onto the final read busa +// Output X's if the address is invalid +//assign rmuxd0 = legal ? {72{RdClk0}} & ~dout0 : force_x; + assign rmuxd0 = {72{RdClk0}} & ~dout0 ; + always @(RECLK or rmuxd0) + begin + if (RECLK) + begin + dout[71:0] <= (rmuxd0[71:0]); // spyglass disable W18 + end + end +// Instantiate the memory banks. One for each CM . + RAMPDP_80X72_GL_M1_D2_ram # (80, 72, 7) iow0 ( + WAFF[6:0], + WrClk0, + WMNQ, + WDQ, + RADRSWI[6:0], + dout0 + ); +`ifndef SYNTHESIS +// Tasks for initializing the arrays +// Ramgen function for writing the arrays +//VCS coverage off +task mem_write_bank; + input [6:0] addr; + input [71:0] data; + reg [71:0] wdat; + begin + wdat = data; + iow0.mem_wr_raw_subbank(addr[6:0],wdat); + end +endtask +// Ramgen function for reading the arrays +function [71:0] mem_read_bank; +input [6:0] addr; +reg [71:0] memout; + begin + memout = iow0.mem_read_raw_subbank(addr); + mem_read_bank = memout; + end +endfunction +//VCS coverage on +`endif //SYNTHESIS +endmodule +`endif // end EMULATION +`endif // end RAM_INTERFACE +`ifndef RAM_INTERFACE +`ifndef EMULATION +module RAMPDP_80X72_GL_M1_D2_ram ( + wadr, + wrclk, + wrmaskn, + wrdata, + radr, + rout_B +); +// default parameters +parameter words = 80; +parameter bits = 72; +parameter addrs = 7; +// Write address +input [addrs-1:0] wadr; +// Write clock +input wrclk; +// Write data +input [bits-1:0] wrdata; +// Write Mask +input [bits-1:0] wrmaskn; +// Read address +input [addrs-1:0] radr; +// Read out +wire [bits-1:0] rdarr; +output [bits-1:0] rout_B; +// Memory . words X bits +reg [bits-1:0] arr[0:words-1]; +`ifdef SIM_and_FAULT +// regs for inducing faults +reg [bits-1:0] fault_no_write; // block writes to this column +reg [bits-1:0] fault_stuck_0; // column always reads as 0 +reg [bits-1:0] fault_stuck_1; // column always reads as 1 +reg [bits-1:0] bit_fault_stuck_0[0:words-1]; // column always reads as 0 +reg [bits-1:0] bit_fault_stuck_1[0:words-1]; // column always reads as 1 +initial begin : init_bit_fault_stuck + integer i; + integer j; + fault_no_write = {bits{1'b0}}; + fault_stuck_0 = {bits{1'b0}}; + fault_stuck_1 = {bits{1'b0}}; + for ( i =0; i <=words; i=i+1) begin + bit_fault_stuck_0[i] = {bits{1'b0}}; + bit_fault_stuck_1[i] = {bits{1'b0}}; + end +end +`endif // FAULT +`ifdef SIM_and_MONITOR +//VCS coverage off +// monitor variables +reg monitor_on; +reg [words-1:0] word_written; +reg [words-1:0] word_read; +reg [bits-1:0] bit_written[0:words-1]; +reg [bits-1:0] bit_read[0:words-1]; +initial begin : init_monitor + integer i; + monitor_on = 1'b0; + for(i=0;i<= words-1;i=i+1) begin + word_written[i] = 1'b0; + word_read[i] = 1'b0; + bit_written[i] = {bits{1'bx}}; + bit_read[i] = {bits{1'bx}}; + end +end +`endif // MONITOR +//VCS coverage on +// Bit write enable +// Write only when mask=1. Else hold the data. +`ifdef SIM_and_FAULT +// Include fault registers +wire [bits-1:0] bwe = wrmaskn & ~fault_no_write; +`else //SIM_and_FAULT +wire [bits-1:0] bwe = wrmaskn ; +`endif //SIM_and_FAULT +wire [bits-1:0] bitclk = {bits{wrclk}} & bwe ; +integer i; +`ifdef SIM_and_FAULT +always @(bitclk or wadr or wrdata) +`else +always @(wrclk or wadr or wrdata) +`endif +begin +`ifdef SIM_and_FAULT + for (i=0 ; i ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +//Updating the memory through write port w + `ifndef SYNTHESIS + if ( ( we ) === 1'b1 ) begin + `else + if ( ( we ) == 1'b1 ) begin + `endif + if (!(ret_en | (internal_sleep_en))) M[wa] <= di; + `ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + last_write_time[wa] = $time; + num_writes[wa] = num_writes[wa] + 1; + end + `endif + end +// spyglass enable_block SYNTH_5130 + `ifndef SYNTHESIS + end + `endif +end // always @ posedge clk +reg [4:0] ra_d; +reg re_d; +reg rd_x_clobber_r0 ; +initial rd_x_clobber_r0 = 1'b0; +wire dout_ram_writethrough = (we_d & re_d & (wa_d == ra_d)); +reg dout_ram_writethrough_d; +reg dout_ram_clobbered_d; +// Conditions to clobber dout +wire dout_ram_clobbered = {1{(internal_sleep_en)}} | (we_d & (wa_d == ra_d) & ~dout_ram_writethrough) | (~re_d & dout_ram_clobbered_d) | ({1{|(internal_sleep_en)}})| {1{rd_x_clobber_r0}} ; +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +`ifdef SYNTHESIS + wire [31:0] dout_ram = (internal_sleep_en) ? 32'b0 : M[ra_d]; +`else + wire [31:0] dout_ram = (internal_sleep_en) ? 32'b0 : dout_ram_clobbered ? {32{1'bx}} : M[ra_d]; +`endif +// spyglass enable_block SYNTH_5130 +wire [31:0] fbypass_dout_ram; +assign fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [31:0] dout_r; +assign dout = dout_r; +//always block for read functionality +always @( posedge clk ) begin + re_d <= ( re ) ; +//Clobber the dout if re = x or ra = x (when re = 1) + `ifndef SYNTHESIS + if ((re === 1'bx) ||((re)&&(^ra) === 1'bx) ) begin + rd_x_clobber_r0 <= 1'b1 ; + end + else begin + `else + begin + `endif +//Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( ( re) === 1'b1 ) begin + rd_x_clobber_r0 <= 1'b0 ; + `else + if ( ( re) == 1'b1 ) begin + `endif + ra_d <= ra; +`ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + if (last_read_time[ra] > last_write_time[ra]) begin +// no write after last read to this row, remove factor added from last read + liveness[ra] = liveness[ra] - (last_read_time[ra] - last_write_time[ra]); + end +// add the liveness from last write to this read + last_read_time[ra] = $time; + liveness[ra] = liveness[ra] + (last_read_time[ra] - last_write_time[ra]); + num_reads[ra] = num_reads[ra] + 1; + end // if liveness_logging_start +`endif + end + dout_ram_writethrough_d <= dout_ram_writethrough; + if(dout_ram_clobbered) begin + dout_ram_clobbered_d <= dout_ram_clobbered; + end else begin + dout_ram_clobbered_d <= 1'b0; + end + end +//Pipelined Read + if ( ore ) begin + dout_r <= fbypass_dout_ram; + end +end // always @ posedge clk +// expanded storage array +// verilint 528 off - variable set but not used +`ifdef NV_RAM_EXPAND_ARRAY +wire [31:0] Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; +wire [31:0] Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15; +wire [31:0] Q16, Q17, Q18; +// verilint 528 on +assign Q0 = M[0]; +assign Q1 = M[1]; +assign Q2 = M[2]; +assign Q3 = M[3]; +assign Q4 = M[4]; +assign Q5 = M[5]; +assign Q6 = M[6]; +assign Q7 = M[7]; +assign Q8 = M[8]; +assign Q9 = M[9]; +assign Q10 = M[10]; +assign Q11 = M[11]; +assign Q12 = M[12]; +assign Q13 = M[13]; +assign Q14 = M[14]; +assign Q15 = M[15]; +assign Q16 = M[16]; +assign Q17 = M[17]; +assign Q18 = M[18]; +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`ifdef RAMGEN_CLOBBER +nv_assert_never #(0,0,"clobbered high") clobbered_high (clk,sim_reset_, (dout_ram_clobbered == 1'b1)); +`endif +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[31:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_val; + input [4:0] row; + input [31:0] data; + begin + M[row] = data; + end +endtask +//This is only needed for latch arrays +task init_mem_commit; + begin + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +function [31:0] probe_mem_val; + input [4:0] row; + begin + probe_mem_val = M[row]; + end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,M); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [31:0] random_num; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 608); + row = random_num / 32; + bitnum = random_num % 32; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [4:0] row; +input [31:0] bitnum; +reg [31:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef NO_DO_WRITE_TASK +task do_write; //(wa, we, di); + input [4:0] wa; + input we; + input [31:0] di; + reg [31:0] d; + begin + d = M[wa]; + d = (we ? di : d); + M[wa] = d; + end +endtask +`endif +`ifdef NV_Functional_safety_liveness_logging_enabled +task average_liveness_time; +begin +integer i; +time sum; +time average; +real sum_rds; +real sum_wrs; +real ratio_rw; +sum = 0; +sum_rds = 0; +sum_wrs = 0; +for (i=0; i < 19; i=i+1) begin + sum = sum + liveness[i]; + sum_rds = sum_rds + num_reads[i]; + sum_wrs = sum_wrs + num_writes[i]; +end +average = sum/19; +ratio_rw = sum_rds/sum_wrs; +$display ("nv_ram %m: size 608 bits, AVF liveness %d", average); +$display ("nv_ram %m: AVF ratioRW %f, totalWrites %d, totalReads %d", ratio_rw, sum_wrs, sum_rds); +end +endtask +`endif +`ifdef GCS_COMPILE + `undef SYNTHESIS +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x32.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x32.v.vcp new file mode 100644 index 0000000..dd7ba50 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x32.v.vcp @@ -0,0 +1,466 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x32.v +`timescale 1ns / 10ps +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +module nv_ram_rwsthp_19x32 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [31:0] dout; +input [4:0] wa; +input we; +input [31:0] di; +input byp_sel; +input [31:0] dbyp; +input [31:0] pwrbus_ram_pd; + wire is_sram = 1'b1; +`ifdef GCS_COMPILE + `define SYNTHESIS +`endif +`ifndef SYNTHESIS +`ifdef RAMGEN_AVF_PRINTS + `define NV_Functional_safety_liveness_logging_enabled +`endif +`endif +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +integer l; +`ifdef NV_Functional_safety_liveness_logging_enabled +time liveness[18:0]; +time last_write_time[18:0]; +time last_read_time[18:0]; +reg liveness_logging_start; +integer num_writes[18:0]; +integer num_reads[18:0]; +integer ratio_rw[18:0]; +initial begin + for (l=0; l<19; l=l+1) begin + liveness[l] = 0; + last_write_time[l] = 0; + last_read_time[l] = 0; + ratio_rw[l] = 0; + num_writes[l] = 0; + num_reads[l] = 0; + end +end +always @(posedge liveness_logging_start) begin + for (l=0; l<19; l=l+1) last_write_time[l] = $time; +end +`endif +// Wires to check for wr-wr collision +// storage array +reg [31:0] M[18:0]; /* synthesis syn_rw_conflict_logic = 1 */ +wire internal_sleep_en; +`ifdef RAM_DISABLE_POWER_GATING_FPGA +assign internal_sleep_en = 1'b0; +`else +assign internal_sleep_en = (|sleep_en); +`endif +`ifndef SYNTHESIS +integer i; +//X out the content of the memory array when the array is put in sleep mode +always @(posedge internal_sleep_en) begin + if (!ret_en) begin + for(i=0;i<19;i=i+1) begin + M[i] <= #0.01 32'dx ; + end + end +end +`endif +reg [5 : 0 ] count ; +reg [4:0] wa_d; +reg we_d; +//always block for write functionality +always @( posedge clk ) begin + `ifndef SYNTHESIS +// Clobber the memory array if we = x or wa = x (when we = 1'b1) + if(((|we) === 1'bx || (((|we))&&(^wa)) === 1'bx)) begin + #1 + for(count=0;count<19;count=count+1) begin + M[count] <= 32'dx ; + end + end + else begin + `endif + we_d <= we; +// Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( (|we) === 1'b1 ) begin + `else + if ( (|we) == 1'b1 ) begin + `endif + wa_d <= wa; + end +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +//Updating the memory through write port w + `ifndef SYNTHESIS + if ( ( we ) === 1'b1 ) begin + `else + if ( ( we ) == 1'b1 ) begin + `endif + if (!(ret_en | (internal_sleep_en))) M[wa] <= di; + `ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + last_write_time[wa] = $time; + num_writes[wa] = num_writes[wa] + 1; + end + `endif + end +// spyglass enable_block SYNTH_5130 + `ifndef SYNTHESIS + end + `endif +end // always @ posedge clk +reg [4:0] ra_d; +reg re_d; +reg rd_x_clobber_r0 ; +initial rd_x_clobber_r0 = 1'b0; +wire dout_ram_writethrough = (we_d & re_d & (wa_d == ra_d)); +reg dout_ram_writethrough_d; +reg dout_ram_clobbered_d; +// Conditions to clobber dout +wire dout_ram_clobbered = {1{(internal_sleep_en)}} | (we_d & (wa_d == ra_d) & ~dout_ram_writethrough) | (~re_d & dout_ram_clobbered_d) | ({1{|(internal_sleep_en)}})| {1{rd_x_clobber_r0}} ; +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +`ifdef SYNTHESIS + wire [31:0] dout_ram = (internal_sleep_en) ? 32'b0 : M[ra_d]; +`else + wire [31:0] dout_ram = (internal_sleep_en) ? 32'b0 : dout_ram_clobbered ? {32{1'bx}} : M[ra_d]; +`endif +// spyglass enable_block SYNTH_5130 +wire [31:0] fbypass_dout_ram; +assign fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [31:0] dout_r; +assign dout = dout_r; +//always block for read functionality +always @( posedge clk ) begin + re_d <= ( re ) ; +//Clobber the dout if re = x or ra = x (when re = 1) + `ifndef SYNTHESIS + if ((re === 1'bx) ||((re)&&(^ra) === 1'bx) ) begin + rd_x_clobber_r0 <= 1'b1 ; + end + else begin + `else + begin + `endif +//Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( ( re) === 1'b1 ) begin + rd_x_clobber_r0 <= 1'b0 ; + `else + if ( ( re) == 1'b1 ) begin + `endif + ra_d <= ra; +`ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + if (last_read_time[ra] > last_write_time[ra]) begin +// no write after last read to this row, remove factor added from last read + liveness[ra] = liveness[ra] - (last_read_time[ra] - last_write_time[ra]); + end +// add the liveness from last write to this read + last_read_time[ra] = $time; + liveness[ra] = liveness[ra] + (last_read_time[ra] - last_write_time[ra]); + num_reads[ra] = num_reads[ra] + 1; + end // if liveness_logging_start +`endif + end + dout_ram_writethrough_d <= dout_ram_writethrough; + if(dout_ram_clobbered) begin + dout_ram_clobbered_d <= dout_ram_clobbered; + end else begin + dout_ram_clobbered_d <= 1'b0; + end + end +//Pipelined Read + if ( ore ) begin + dout_r <= fbypass_dout_ram; + end +end // always @ posedge clk +// expanded storage array +// verilint 528 off - variable set but not used +`ifdef NV_RAM_EXPAND_ARRAY +wire [31:0] Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; +wire [31:0] Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15; +wire [31:0] Q16, Q17, Q18; +// verilint 528 on +assign Q0 = M[0]; +assign Q1 = M[1]; +assign Q2 = M[2]; +assign Q3 = M[3]; +assign Q4 = M[4]; +assign Q5 = M[5]; +assign Q6 = M[6]; +assign Q7 = M[7]; +assign Q8 = M[8]; +assign Q9 = M[9]; +assign Q10 = M[10]; +assign Q11 = M[11]; +assign Q12 = M[12]; +assign Q13 = M[13]; +assign Q14 = M[14]; +assign Q15 = M[15]; +assign Q16 = M[16]; +assign Q17 = M[17]; +assign Q18 = M[18]; +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`ifdef RAMGEN_CLOBBER +nv_assert_never #(0,0,"clobbered high") clobbered_high (clk,sim_reset_, (dout_ram_clobbered == 1'b1)); +`endif +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[31:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_val; + input [4:0] row; + input [31:0] data; + begin + M[row] = data; + end +endtask +//This is only needed for latch arrays +task init_mem_commit; + begin + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +function [31:0] probe_mem_val; + input [4:0] row; + begin + probe_mem_val = M[row]; + end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,M); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [31:0] random_num; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 608); + row = random_num / 32; + bitnum = random_num % 32; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [4:0] row; +input [31:0] bitnum; +reg [31:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef NO_DO_WRITE_TASK +task do_write; //(wa, we, di); + input [4:0] wa; + input we; + input [31:0] di; + reg [31:0] d; + begin + d = M[wa]; + d = (we ? di : d); + M[wa] = d; + end +endtask +`endif +`ifdef NV_Functional_safety_liveness_logging_enabled +task average_liveness_time; +begin +integer i; +time sum; +time average; +real sum_rds; +real sum_wrs; +real ratio_rw; +sum = 0; +sum_rds = 0; +sum_wrs = 0; +for (i=0; i < 19; i=i+1) begin + sum = sum + liveness[i]; + sum_rds = sum_rds + num_reads[i]; + sum_wrs = sum_wrs + num_writes[i]; +end +average = sum/19; +ratio_rw = sum_rds/sum_wrs; +$display ("nv_ram %m: size 608 bits, AVF liveness %d", average); +$display ("nv_ram %m: AVF ratioRW %f, totalWrites %d, totalReads %d", ratio_rw, sum_wrs, sum_rds); +end +endtask +`endif +`ifdef GCS_COMPILE + `undef SYNTHESIS +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x4.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x4.v new file mode 100644 index 0000000..8e056da --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x4.v @@ -0,0 +1,438 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x4.v +`timescale 1ns / 10ps +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +module nv_ram_rwsthp_19x4 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [3:0] dout; +input [4:0] wa; +input we; +input [3:0] di; +input byp_sel; +input [3:0] dbyp; +input [31:0] pwrbus_ram_pd; + wire is_sram = 1'b0; +`ifdef GCS_COMPILE + `define SYNTHESIS +`endif +`ifndef SYNTHESIS +`ifdef RAMGEN_AVF_PRINTS + `define NV_Functional_safety_liveness_logging_enabled +`endif +`endif +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +integer l; +`ifdef NV_Functional_safety_liveness_logging_enabled +time liveness[18:0]; +time last_write_time[18:0]; +time last_read_time[18:0]; +reg liveness_logging_start; +integer num_writes[18:0]; +integer num_reads[18:0]; +integer ratio_rw[18:0]; +initial begin + for (l=0; l<19; l=l+1) begin + liveness[l] = 0; + last_write_time[l] = 0; + last_read_time[l] = 0; + ratio_rw[l] = 0; + num_writes[l] = 0; + num_reads[l] = 0; + end +end +always @(posedge liveness_logging_start) begin + for (l=0; l<19; l=l+1) last_write_time[l] = $time; +end +`endif +// Wires to check for wr-wr collision +// storage array +reg [3:0] M[18:0]; /* synthesis syn_rw_conflict_logic = 1 */ +wire internal_sleep_en; +`ifdef RAM_DISABLE_POWER_GATING_FPGA +assign internal_sleep_en = 1'b0; +`else +assign internal_sleep_en = (|sleep_en); +`endif +`ifndef SYNTHESIS +integer i; +//X out the content of the memory array when the array is put in sleep mode +always @(posedge internal_sleep_en) begin + if (!ret_en) begin + for(i=0;i<19;i=i+1) begin + M[i] <= #0.01 4'dx ; + end + end +end +`endif +reg [5 : 0 ] count ; +reg [4:0] wa_d; +reg we_d; +//always block for write functionality +always @( posedge clk ) begin + `ifndef SYNTHESIS +// Clobber the memory array if we = x or wa = x (when we = 1'b1) + if(((|we) === 1'bx || (((|we))&&(^wa)) === 1'bx)) begin + #1 + for(count=0;count<19;count=count+1) begin + M[count] <= 4'dx ; + end + end + else begin + `endif + we_d <= we; +// Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( (|we) === 1'b1 ) begin + `else + if ( (|we) == 1'b1 ) begin + `endif + wa_d <= wa; + end +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +//Updating the memory through write port w + `ifndef SYNTHESIS + if ( ( we ) === 1'b1 ) begin + `else + if ( ( we ) == 1'b1 ) begin + `endif + if (!(ret_en | (internal_sleep_en))) M[wa] <= di; + `ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + last_write_time[wa] = $time; + num_writes[wa] = num_writes[wa] + 1; + end + `endif + end +// spyglass enable_block SYNTH_5130 + `ifndef SYNTHESIS + end + `endif +end // always @ posedge clk +reg [4:0] ra_d; +reg re_d; +reg rd_x_clobber_r0 ; +initial rd_x_clobber_r0 = 1'b0; +wire dout_ram_writethrough = (we_d & re_d & (wa_d == ra_d)); +reg dout_ram_writethrough_d; +reg dout_ram_clobbered_d; +// Conditions to clobber dout +wire dout_ram_clobbered = {1{(internal_sleep_en)}} | (we_d & (wa_d == ra_d) & ~dout_ram_writethrough) | (~re_d & dout_ram_clobbered_d)| {1{rd_x_clobber_r0}} ; +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +`ifdef SYNTHESIS + wire [3:0] dout_ram = (internal_sleep_en) ? 4'b0 : M[ra_d]; +`else + wire [3:0] dout_ram = (internal_sleep_en) ? 4'b0 : dout_ram_clobbered ? {4{1'bx}} : M[ra_d]; +`endif +// spyglass enable_block SYNTH_5130 +wire [3:0] fbypass_dout_ram; +assign fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [3:0] dout_r; +assign dout = dout_r; +//always block for read functionality +always @( posedge clk ) begin + re_d <= ( re ) ; +//Clobber the dout if re = x or ra = x (when re = 1) + `ifndef SYNTHESIS + if ((re === 1'bx) ||((re)&&(^ra) === 1'bx) ) begin + rd_x_clobber_r0 <= 1'b1 ; + end + else begin + `else + begin + `endif +//Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( ( re) === 1'b1 ) begin + rd_x_clobber_r0 <= 1'b0 ; + `else + if ( ( re) == 1'b1 ) begin + `endif + ra_d <= ra; +`ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + if (last_read_time[ra] > last_write_time[ra]) begin +// no write after last read to this row, remove factor added from last read + liveness[ra] = liveness[ra] - (last_read_time[ra] - last_write_time[ra]); + end +// add the liveness from last write to this read + last_read_time[ra] = $time; + liveness[ra] = liveness[ra] + (last_read_time[ra] - last_write_time[ra]); + num_reads[ra] = num_reads[ra] + 1; + end // if liveness_logging_start +`endif + end + dout_ram_writethrough_d <= dout_ram_writethrough; + if(dout_ram_clobbered) begin + dout_ram_clobbered_d <= dout_ram_clobbered; + end else begin + dout_ram_clobbered_d <= 1'b0; + end + end +//Pipelined Read + if ( ore ) begin + dout_r <= fbypass_dout_ram; + end +end // always @ posedge clk +// expanded storage array +// verilint 528 off - variable set but not used +`ifdef NV_RAM_EXPAND_ARRAY +wire [3:0] Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; +wire [3:0] Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15; +wire [3:0] Q16, Q17, Q18; +// verilint 528 on +assign Q0 = M[0]; +assign Q1 = M[1]; +assign Q2 = M[2]; +assign Q3 = M[3]; +assign Q4 = M[4]; +assign Q5 = M[5]; +assign Q6 = M[6]; +assign Q7 = M[7]; +assign Q8 = M[8]; +assign Q9 = M[9]; +assign Q10 = M[10]; +assign Q11 = M[11]; +assign Q12 = M[12]; +assign Q13 = M[13]; +assign Q14 = M[14]; +assign Q15 = M[15]; +assign Q16 = M[16]; +assign Q17 = M[17]; +assign Q18 = M[18]; +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`ifdef RAMGEN_CLOBBER +nv_assert_never #(0,0,"clobbered high") clobbered_high (clk,sim_reset_, (dout_ram_clobbered == 1'b1)); +`endif +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[3:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_val; + input [4:0] row; + input [3:0] data; + begin + M[row] = data; + end +endtask +//This is only needed for latch arrays +task init_mem_commit; + begin + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +function [3:0] probe_mem_val; + input [4:0] row; + begin + probe_mem_val = M[row]; + end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,M); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [3:0] random_num; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 76); + row = random_num / 4; + bitnum = random_num % 4; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [4:0] row; +input [3:0] bitnum; +reg [3:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef NO_DO_WRITE_TASK +task do_write; //(wa, we, di); + input [4:0] wa; + input we; + input [3:0] di; + reg [3:0] d; + begin + d = M[wa]; + d = (we ? di : d); + M[wa] = d; + end +endtask +`endif +`ifdef NV_Functional_safety_liveness_logging_enabled +task average_liveness_time; +begin +integer i; +time sum; +time average; +real sum_rds; +real sum_wrs; +real ratio_rw; +sum = 0; +sum_rds = 0; +sum_wrs = 0; +for (i=0; i < 19; i=i+1) begin + sum = sum + liveness[i]; + sum_rds = sum_rds + num_reads[i]; + sum_wrs = sum_wrs + num_writes[i]; +end +average = sum/19; +ratio_rw = sum_rds/sum_wrs; +$display ("nv_ram %m: size 76 bits, AVF liveness %d", average); +$display ("nv_ram %m: AVF ratioRW %f, totalWrites %d, totalReads %d", ratio_rw, sum_wrs, sum_rds); +end +endtask +`endif +`ifdef GCS_COMPILE + `undef SYNTHESIS +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x4.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x4.v.vcp new file mode 100644 index 0000000..8e056da --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x4.v.vcp @@ -0,0 +1,438 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x4.v +`timescale 1ns / 10ps +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +module nv_ram_rwsthp_19x4 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [3:0] dout; +input [4:0] wa; +input we; +input [3:0] di; +input byp_sel; +input [3:0] dbyp; +input [31:0] pwrbus_ram_pd; + wire is_sram = 1'b0; +`ifdef GCS_COMPILE + `define SYNTHESIS +`endif +`ifndef SYNTHESIS +`ifdef RAMGEN_AVF_PRINTS + `define NV_Functional_safety_liveness_logging_enabled +`endif +`endif +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +integer l; +`ifdef NV_Functional_safety_liveness_logging_enabled +time liveness[18:0]; +time last_write_time[18:0]; +time last_read_time[18:0]; +reg liveness_logging_start; +integer num_writes[18:0]; +integer num_reads[18:0]; +integer ratio_rw[18:0]; +initial begin + for (l=0; l<19; l=l+1) begin + liveness[l] = 0; + last_write_time[l] = 0; + last_read_time[l] = 0; + ratio_rw[l] = 0; + num_writes[l] = 0; + num_reads[l] = 0; + end +end +always @(posedge liveness_logging_start) begin + for (l=0; l<19; l=l+1) last_write_time[l] = $time; +end +`endif +// Wires to check for wr-wr collision +// storage array +reg [3:0] M[18:0]; /* synthesis syn_rw_conflict_logic = 1 */ +wire internal_sleep_en; +`ifdef RAM_DISABLE_POWER_GATING_FPGA +assign internal_sleep_en = 1'b0; +`else +assign internal_sleep_en = (|sleep_en); +`endif +`ifndef SYNTHESIS +integer i; +//X out the content of the memory array when the array is put in sleep mode +always @(posedge internal_sleep_en) begin + if (!ret_en) begin + for(i=0;i<19;i=i+1) begin + M[i] <= #0.01 4'dx ; + end + end +end +`endif +reg [5 : 0 ] count ; +reg [4:0] wa_d; +reg we_d; +//always block for write functionality +always @( posedge clk ) begin + `ifndef SYNTHESIS +// Clobber the memory array if we = x or wa = x (when we = 1'b1) + if(((|we) === 1'bx || (((|we))&&(^wa)) === 1'bx)) begin + #1 + for(count=0;count<19;count=count+1) begin + M[count] <= 4'dx ; + end + end + else begin + `endif + we_d <= we; +// Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( (|we) === 1'b1 ) begin + `else + if ( (|we) == 1'b1 ) begin + `endif + wa_d <= wa; + end +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +//Updating the memory through write port w + `ifndef SYNTHESIS + if ( ( we ) === 1'b1 ) begin + `else + if ( ( we ) == 1'b1 ) begin + `endif + if (!(ret_en | (internal_sleep_en))) M[wa] <= di; + `ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + last_write_time[wa] = $time; + num_writes[wa] = num_writes[wa] + 1; + end + `endif + end +// spyglass enable_block SYNTH_5130 + `ifndef SYNTHESIS + end + `endif +end // always @ posedge clk +reg [4:0] ra_d; +reg re_d; +reg rd_x_clobber_r0 ; +initial rd_x_clobber_r0 = 1'b0; +wire dout_ram_writethrough = (we_d & re_d & (wa_d == ra_d)); +reg dout_ram_writethrough_d; +reg dout_ram_clobbered_d; +// Conditions to clobber dout +wire dout_ram_clobbered = {1{(internal_sleep_en)}} | (we_d & (wa_d == ra_d) & ~dout_ram_writethrough) | (~re_d & dout_ram_clobbered_d)| {1{rd_x_clobber_r0}} ; +// Disable the addr > ram depth. An assert will flag this +// spyglass disable_block SYNTH_5130 +`ifdef SYNTHESIS + wire [3:0] dout_ram = (internal_sleep_en) ? 4'b0 : M[ra_d]; +`else + wire [3:0] dout_ram = (internal_sleep_en) ? 4'b0 : dout_ram_clobbered ? {4{1'bx}} : M[ra_d]; +`endif +// spyglass enable_block SYNTH_5130 +wire [3:0] fbypass_dout_ram; +assign fbypass_dout_ram = (byp_sel ? dbyp : dout_ram); +reg [3:0] dout_r; +assign dout = dout_r; +//always block for read functionality +always @( posedge clk ) begin + re_d <= ( re ) ; +//Clobber the dout if re = x or ra = x (when re = 1) + `ifndef SYNTHESIS + if ((re === 1'bx) ||((re)&&(^ra) === 1'bx) ) begin + rd_x_clobber_r0 <= 1'b1 ; + end + else begin + `else + begin + `endif +//Use == for synthesis and === for non-synthesis model + `ifndef SYNTHESIS + if ( ( re) === 1'b1 ) begin + rd_x_clobber_r0 <= 1'b0 ; + `else + if ( ( re) == 1'b1 ) begin + `endif + ra_d <= ra; +`ifdef NV_Functional_safety_liveness_logging_enabled + if (liveness_logging_start) begin + if (last_read_time[ra] > last_write_time[ra]) begin +// no write after last read to this row, remove factor added from last read + liveness[ra] = liveness[ra] - (last_read_time[ra] - last_write_time[ra]); + end +// add the liveness from last write to this read + last_read_time[ra] = $time; + liveness[ra] = liveness[ra] + (last_read_time[ra] - last_write_time[ra]); + num_reads[ra] = num_reads[ra] + 1; + end // if liveness_logging_start +`endif + end + dout_ram_writethrough_d <= dout_ram_writethrough; + if(dout_ram_clobbered) begin + dout_ram_clobbered_d <= dout_ram_clobbered; + end else begin + dout_ram_clobbered_d <= 1'b0; + end + end +//Pipelined Read + if ( ore ) begin + dout_r <= fbypass_dout_ram; + end +end // always @ posedge clk +// expanded storage array +// verilint 528 off - variable set but not used +`ifdef NV_RAM_EXPAND_ARRAY +wire [3:0] Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; +wire [3:0] Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15; +wire [3:0] Q16, Q17, Q18; +// verilint 528 on +assign Q0 = M[0]; +assign Q1 = M[1]; +assign Q2 = M[2]; +assign Q3 = M[3]; +assign Q4 = M[4]; +assign Q5 = M[5]; +assign Q6 = M[6]; +assign Q7 = M[7]; +assign Q8 = M[8]; +assign Q9 = M[9]; +assign Q10 = M[10]; +assign Q11 = M[11]; +assign Q12 = M[12]; +assign Q13 = M[13]; +assign Q14 = M[14]; +assign Q15 = M[15]; +assign Q16 = M[16]; +assign Q17 = M[17]; +assign Q18 = M[18]; +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`ifdef RAMGEN_CLOBBER +nv_assert_never #(0,0,"clobbered high") clobbered_high (clk,sim_reset_, (dout_ram_clobbered == 1'b1)); +`endif +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[3:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_val; + input [4:0] row; + input [3:0] data; + begin + M[row] = data; + end +endtask +//This is only needed for latch arrays +task init_mem_commit; + begin + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +function [3:0] probe_mem_val; + input [4:0] row; + begin + probe_mem_val = M[row]; + end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,M); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [3:0] random_num; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 76); + row = random_num / 4; + bitnum = random_num % 4; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [4:0] row; +input [3:0] bitnum; +reg [3:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef NO_DO_WRITE_TASK +task do_write; //(wa, we, di); + input [4:0] wa; + input we; + input [3:0] di; + reg [3:0] d; + begin + d = M[wa]; + d = (we ? di : d); + M[wa] = d; + end +endtask +`endif +`ifdef NV_Functional_safety_liveness_logging_enabled +task average_liveness_time; +begin +integer i; +time sum; +time average; +real sum_rds; +real sum_wrs; +real ratio_rw; +sum = 0; +sum_rds = 0; +sum_wrs = 0; +for (i=0; i < 19; i=i+1) begin + sum = sum + liveness[i]; + sum_rds = sum_rds + num_reads[i]; + sum_wrs = sum_wrs + num_writes[i]; +end +average = sum/19; +ratio_rw = sum_rds/sum_wrs; +$display ("nv_ram %m: size 76 bits, AVF liveness %d", average); +$display ("nv_ram %m: AVF ratioRW %f, totalWrites %d, totalReads %d", ratio_rw, sum_wrs, sum_rds); +end +endtask +`endif +`ifdef GCS_COMPILE + `undef SYNTHESIS +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80.v new file mode 100644 index 0000000..16dbe48 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80.v @@ -0,0 +1,700 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x80.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_19x80 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [79:0] dout; +input [4:0] wa; +input we; +input [79:0] di; +input byp_sel; +input [79:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_20X80_GL_M1_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [4:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [4:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [79:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_22 (.A(mbist_Do_r0_int_net[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_23 (.A(mbist_Do_r0_int_net[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_24 (.A(mbist_Do_r0_int_net[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_25 (.A(mbist_Do_r0_int_net[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_26 (.A(mbist_Do_r0_int_net[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_27 (.A(mbist_Do_r0_int_net[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_28 (.A(mbist_Do_r0_int_net[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_29 (.A(mbist_Do_r0_int_net[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_30 (.A(mbist_Do_r0_int_net[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_31 (.A(mbist_Do_r0_int_net[31])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_32 (.A(mbist_Do_r0_int_net[32])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_33 (.A(mbist_Do_r0_int_net[33])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_34 (.A(mbist_Do_r0_int_net[34])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_35 (.A(mbist_Do_r0_int_net[35])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_36 (.A(mbist_Do_r0_int_net[36])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_37 (.A(mbist_Do_r0_int_net[37])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_38 (.A(mbist_Do_r0_int_net[38])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_39 (.A(mbist_Do_r0_int_net[39])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_40 (.A(mbist_Do_r0_int_net[40])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_41 (.A(mbist_Do_r0_int_net[41])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_42 (.A(mbist_Do_r0_int_net[42])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_43 (.A(mbist_Do_r0_int_net[43])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_44 (.A(mbist_Do_r0_int_net[44])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_45 (.A(mbist_Do_r0_int_net[45])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_46 (.A(mbist_Do_r0_int_net[46])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_47 (.A(mbist_Do_r0_int_net[47])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_48 (.A(mbist_Do_r0_int_net[48])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_49 (.A(mbist_Do_r0_int_net[49])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_50 (.A(mbist_Do_r0_int_net[50])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_51 (.A(mbist_Do_r0_int_net[51])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_52 (.A(mbist_Do_r0_int_net[52])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_53 (.A(mbist_Do_r0_int_net[53])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_54 (.A(mbist_Do_r0_int_net[54])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_55 (.A(mbist_Do_r0_int_net[55])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_56 (.A(mbist_Do_r0_int_net[56])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_57 (.A(mbist_Do_r0_int_net[57])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_58 (.A(mbist_Do_r0_int_net[58])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_59 (.A(mbist_Do_r0_int_net[59])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_60 (.A(mbist_Do_r0_int_net[60])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_61 (.A(mbist_Do_r0_int_net[61])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_62 (.A(mbist_Do_r0_int_net[62])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_63 (.A(mbist_Do_r0_int_net[63])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_64 (.A(mbist_Do_r0_int_net[64])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_65 (.A(mbist_Do_r0_int_net[65])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_66 (.A(mbist_Do_r0_int_net[66])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_67 (.A(mbist_Do_r0_int_net[67])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_68 (.A(mbist_Do_r0_int_net[68])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_69 (.A(mbist_Do_r0_int_net[69])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_70 (.A(mbist_Do_r0_int_net[70])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_71 (.A(mbist_Do_r0_int_net[71])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_72 (.A(mbist_Do_r0_int_net[72])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_73 (.A(mbist_Do_r0_int_net[73])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_74 (.A(mbist_Do_r0_int_net[74])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_75 (.A(mbist_Do_r0_int_net[75])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_76 (.A(mbist_Do_r0_int_net[76])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_77 (.A(mbist_Do_r0_int_net[77])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_78 (.A(mbist_Do_r0_int_net[78])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_79 (.A(mbist_Do_r0_int_net[79])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_19x80_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_19x80 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[79:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + arrangment_string[32] = 32 ; + arrangment_string[33] = 33 ; + arrangment_string[34] = 34 ; + arrangment_string[35] = 35 ; + arrangment_string[36] = 36 ; + arrangment_string[37] = 37 ; + arrangment_string[38] = 38 ; + arrangment_string[39] = 39 ; + arrangment_string[40] = 40 ; + arrangment_string[41] = 41 ; + arrangment_string[42] = 42 ; + arrangment_string[43] = 43 ; + arrangment_string[44] = 44 ; + arrangment_string[45] = 45 ; + arrangment_string[46] = 46 ; + arrangment_string[47] = 47 ; + arrangment_string[48] = 48 ; + arrangment_string[49] = 49 ; + arrangment_string[50] = 50 ; + arrangment_string[51] = 51 ; + arrangment_string[52] = 52 ; + arrangment_string[53] = 53 ; + arrangment_string[54] = 54 ; + arrangment_string[55] = 55 ; + arrangment_string[56] = 56 ; + arrangment_string[57] = 57 ; + arrangment_string[58] = 58 ; + arrangment_string[59] = 59 ; + arrangment_string[60] = 60 ; + arrangment_string[61] = 61 ; + arrangment_string[62] = 62 ; + arrangment_string[63] = 63 ; + arrangment_string[64] = 64 ; + arrangment_string[65] = 65 ; + arrangment_string[66] = 66 ; + arrangment_string[67] = 67 ; + arrangment_string[68] = 68 ; + arrangment_string[69] = 69 ; + arrangment_string[70] = 70 ; + arrangment_string[71] = 71 ; + arrangment_string[72] = 72 ; + arrangment_string[73] = 73 ; + arrangment_string[74] = 74 ; + arrangment_string[75] = 75 ; + arrangment_string[76] = 76 ; + arrangment_string[77] = 77 ; + arrangment_string[78] = 78 ; + arrangment_string[79] = 79 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [18:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [79:0] shadow_mem [18:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [79:0] shadow_mem_row0 = shadow_mem[0]; +wire [79:0] shadow_mem_row1 = shadow_mem[1]; +wire [79:0] shadow_mem_row2 = shadow_mem[2]; +wire [79:0] shadow_mem_row3 = shadow_mem[3]; +wire [79:0] shadow_mem_row4 = shadow_mem[4]; +wire [79:0] shadow_mem_row5 = shadow_mem[5]; +wire [79:0] shadow_mem_row6 = shadow_mem[6]; +wire [79:0] shadow_mem_row7 = shadow_mem[7]; +wire [79:0] shadow_mem_row8 = shadow_mem[8]; +wire [79:0] shadow_mem_row9 = shadow_mem[9]; +wire [79:0] shadow_mem_row10 = shadow_mem[10]; +wire [79:0] shadow_mem_row11 = shadow_mem[11]; +wire [79:0] shadow_mem_row12 = shadow_mem[12]; +wire [79:0] shadow_mem_row13 = shadow_mem[13]; +wire [79:0] shadow_mem_row14 = shadow_mem[14]; +wire [79:0] shadow_mem_row15 = shadow_mem[15]; +wire [79:0] shadow_mem_row16 = shadow_mem[16]; +wire [79:0] shadow_mem_row17 = shadow_mem[17]; +wire [79:0] shadow_mem_row18 = shadow_mem[18]; +`endif +task init_mem_val; + input [4:0] row; + input [79:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_20X80_GL_M1_E2 +for (row = 0; row < 19; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_19x80.ram_Inst_19X80.mem_write(row - 0, shadow_mem[row][79:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [4:0] wa; + input we; + input [79:0] di; + reg [79:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [79:0] probe_mem_val; +input [4:0] row; +reg [79:0] data; +begin +// probing RAMDP_20X80_GL_M1_E2 + if (row >= 0 && row < 19) data[79:0] = r_nv_ram_rwsthp_19x80.ram_Inst_19X80.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 19; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +RANDFUNC rf1 (); +RANDFUNC rf2 (); +task init_mem_random; +reg [79:0] random_num; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff),rf1.rollpli(0,32'hffffffff),rf2.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 1520); + row = random_num / 80; + bitnum = random_num % 80; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [4:0] row; +input [79:0] bitnum; +reg [79:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80.v.vcp new file mode 100644 index 0000000..16dbe48 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80.v.vcp @@ -0,0 +1,700 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x80.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_19x80 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [4:0] ra; +input re; +input ore; +output [79:0] dout; +input [4:0] wa; +input we; +input [79:0] di; +input byp_sel; +input [79:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_20X80_GL_M1_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [4:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [4:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [79:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_22 (.A(mbist_Do_r0_int_net[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_23 (.A(mbist_Do_r0_int_net[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_24 (.A(mbist_Do_r0_int_net[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_25 (.A(mbist_Do_r0_int_net[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_26 (.A(mbist_Do_r0_int_net[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_27 (.A(mbist_Do_r0_int_net[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_28 (.A(mbist_Do_r0_int_net[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_29 (.A(mbist_Do_r0_int_net[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_30 (.A(mbist_Do_r0_int_net[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_31 (.A(mbist_Do_r0_int_net[31])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_32 (.A(mbist_Do_r0_int_net[32])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_33 (.A(mbist_Do_r0_int_net[33])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_34 (.A(mbist_Do_r0_int_net[34])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_35 (.A(mbist_Do_r0_int_net[35])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_36 (.A(mbist_Do_r0_int_net[36])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_37 (.A(mbist_Do_r0_int_net[37])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_38 (.A(mbist_Do_r0_int_net[38])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_39 (.A(mbist_Do_r0_int_net[39])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_40 (.A(mbist_Do_r0_int_net[40])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_41 (.A(mbist_Do_r0_int_net[41])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_42 (.A(mbist_Do_r0_int_net[42])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_43 (.A(mbist_Do_r0_int_net[43])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_44 (.A(mbist_Do_r0_int_net[44])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_45 (.A(mbist_Do_r0_int_net[45])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_46 (.A(mbist_Do_r0_int_net[46])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_47 (.A(mbist_Do_r0_int_net[47])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_48 (.A(mbist_Do_r0_int_net[48])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_49 (.A(mbist_Do_r0_int_net[49])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_50 (.A(mbist_Do_r0_int_net[50])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_51 (.A(mbist_Do_r0_int_net[51])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_52 (.A(mbist_Do_r0_int_net[52])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_53 (.A(mbist_Do_r0_int_net[53])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_54 (.A(mbist_Do_r0_int_net[54])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_55 (.A(mbist_Do_r0_int_net[55])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_56 (.A(mbist_Do_r0_int_net[56])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_57 (.A(mbist_Do_r0_int_net[57])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_58 (.A(mbist_Do_r0_int_net[58])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_59 (.A(mbist_Do_r0_int_net[59])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_60 (.A(mbist_Do_r0_int_net[60])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_61 (.A(mbist_Do_r0_int_net[61])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_62 (.A(mbist_Do_r0_int_net[62])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_63 (.A(mbist_Do_r0_int_net[63])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_64 (.A(mbist_Do_r0_int_net[64])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_65 (.A(mbist_Do_r0_int_net[65])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_66 (.A(mbist_Do_r0_int_net[66])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_67 (.A(mbist_Do_r0_int_net[67])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_68 (.A(mbist_Do_r0_int_net[68])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_69 (.A(mbist_Do_r0_int_net[69])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_70 (.A(mbist_Do_r0_int_net[70])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_71 (.A(mbist_Do_r0_int_net[71])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_72 (.A(mbist_Do_r0_int_net[72])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_73 (.A(mbist_Do_r0_int_net[73])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_74 (.A(mbist_Do_r0_int_net[74])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_75 (.A(mbist_Do_r0_int_net[75])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_76 (.A(mbist_Do_r0_int_net[76])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_77 (.A(mbist_Do_r0_int_net[77])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_78 (.A(mbist_Do_r0_int_net[78])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_79 (.A(mbist_Do_r0_int_net[79])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_19x80_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_19x80 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[79:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + arrangment_string[32] = 32 ; + arrangment_string[33] = 33 ; + arrangment_string[34] = 34 ; + arrangment_string[35] = 35 ; + arrangment_string[36] = 36 ; + arrangment_string[37] = 37 ; + arrangment_string[38] = 38 ; + arrangment_string[39] = 39 ; + arrangment_string[40] = 40 ; + arrangment_string[41] = 41 ; + arrangment_string[42] = 42 ; + arrangment_string[43] = 43 ; + arrangment_string[44] = 44 ; + arrangment_string[45] = 45 ; + arrangment_string[46] = 46 ; + arrangment_string[47] = 47 ; + arrangment_string[48] = 48 ; + arrangment_string[49] = 49 ; + arrangment_string[50] = 50 ; + arrangment_string[51] = 51 ; + arrangment_string[52] = 52 ; + arrangment_string[53] = 53 ; + arrangment_string[54] = 54 ; + arrangment_string[55] = 55 ; + arrangment_string[56] = 56 ; + arrangment_string[57] = 57 ; + arrangment_string[58] = 58 ; + arrangment_string[59] = 59 ; + arrangment_string[60] = 60 ; + arrangment_string[61] = 61 ; + arrangment_string[62] = 62 ; + arrangment_string[63] = 63 ; + arrangment_string[64] = 64 ; + arrangment_string[65] = 65 ; + arrangment_string[66] = 66 ; + arrangment_string[67] = 67 ; + arrangment_string[68] = 68 ; + arrangment_string[69] = 69 ; + arrangment_string[70] = 70 ; + arrangment_string[71] = 71 ; + arrangment_string[72] = 72 ; + arrangment_string[73] = 73 ; + arrangment_string[74] = 74 ; + arrangment_string[75] = 75 ; + arrangment_string[76] = 76 ; + arrangment_string[77] = 77 ; + arrangment_string[78] = 78 ; + arrangment_string[79] = 79 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [18:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [79:0] shadow_mem [18:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [79:0] shadow_mem_row0 = shadow_mem[0]; +wire [79:0] shadow_mem_row1 = shadow_mem[1]; +wire [79:0] shadow_mem_row2 = shadow_mem[2]; +wire [79:0] shadow_mem_row3 = shadow_mem[3]; +wire [79:0] shadow_mem_row4 = shadow_mem[4]; +wire [79:0] shadow_mem_row5 = shadow_mem[5]; +wire [79:0] shadow_mem_row6 = shadow_mem[6]; +wire [79:0] shadow_mem_row7 = shadow_mem[7]; +wire [79:0] shadow_mem_row8 = shadow_mem[8]; +wire [79:0] shadow_mem_row9 = shadow_mem[9]; +wire [79:0] shadow_mem_row10 = shadow_mem[10]; +wire [79:0] shadow_mem_row11 = shadow_mem[11]; +wire [79:0] shadow_mem_row12 = shadow_mem[12]; +wire [79:0] shadow_mem_row13 = shadow_mem[13]; +wire [79:0] shadow_mem_row14 = shadow_mem[14]; +wire [79:0] shadow_mem_row15 = shadow_mem[15]; +wire [79:0] shadow_mem_row16 = shadow_mem[16]; +wire [79:0] shadow_mem_row17 = shadow_mem[17]; +wire [79:0] shadow_mem_row18 = shadow_mem[18]; +`endif +task init_mem_val; + input [4:0] row; + input [79:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_20X80_GL_M1_E2 +for (row = 0; row < 19; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_19x80.ram_Inst_19X80.mem_write(row - 0, shadow_mem[row][79:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [4:0] wa; + input we; + input [79:0] di; + reg [79:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [79:0] probe_mem_val; +input [4:0] row; +reg [79:0] data; +begin +// probing RAMDP_20X80_GL_M1_E2 + if (row >= 0 && row < 19) data[79:0] = r_nv_ram_rwsthp_19x80.ram_Inst_19X80.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 19; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +RANDFUNC rf1 (); +RANDFUNC rf2 (); +task init_mem_random; +reg [79:0] random_num; +integer i; +begin + for (i = 0; i < 19; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff),rf1.rollpli(0,32'hffffffff),rf2.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 1520); + row = random_num / 80; + bitnum = random_num % 80; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [4:0] row; +input [79:0] bitnum; +reg [79:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80_logic.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80_logic.v new file mode 100644 index 0000000..8e6fe54 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80_logic.v @@ -0,0 +1,708 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x80_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_19x80_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [79:0] dbyp; +input debug_mode; +input [79:0] di; +output [79:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [79:0] mbist_Do_r0_int_net; +input [4:0] mbist_Ra_r0; +input [4:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [4:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [4:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [4:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [79:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [79:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [79:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [79:0] pre_muxed_Di_w0; +wire [79:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[79:0]; +assign pre_muxed_Di_w0_B = {{40{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {80{`tick_x_or_0}}; + endcase +reg [79:0] muxed_Di_w0; +wire [79:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[79:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {80{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [4:0] pre_Wa_reg_w0; +reg [4:0] Wa_reg_w0; +wire [4:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {5{`tick_x_or_0}}; +endcase +reg [4:0] muxed_Wa_w0; +wire [4:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {5{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [4:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [4:0] pre_Ra_reg_r0; +reg [4:0] Ra_reg_r0; +wire [4:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {5{`tick_x_or_0}}; +endcase +wire [4:0] D_Ra_reg_r0; +reg [4:0] muxed_Ra_r0; +wire [4:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {5{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [4:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_20X80_GL_M1_E2 (RamCell) +// Covers Addresses from 0 to 19 Addressrange: [4:0] +// Data Bit range: [79:0] (80 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [4:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[4:0]; +// Write Data in bus +wire [79:0] Wdata; +assign Wdata = muxed_Di_w0[79:0]; +assign we_0_0 = we; +// Read Address bus +wire [4:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[4:0]; +// Read DataOut bus +wire [79:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_20X80_GL_M1_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [79:0] ramDataOut; +assign dout_0_0[79:0] = ramDataOut[79:0]; +RAMDP_20X80_GL_M1_E2 ram_Inst_19X80 ( + .CLK_W (gated_clk_core) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_79 (Wdata[79]) + , .WD_78 (Wdata[78]) + , .WD_77 (Wdata[77]) + , .WD_76 (Wdata[76]) + , .WD_75 (Wdata[75]) + , .WD_74 (Wdata[74]) + , .WD_73 (Wdata[73]) + , .WD_72 (Wdata[72]) + , .WD_71 (Wdata[71]) + , .WD_70 (Wdata[70]) + , .WD_69 (Wdata[69]) + , .WD_68 (Wdata[68]) + , .WD_67 (Wdata[67]) + , .WD_66 (Wdata[66]) + , .WD_65 (Wdata[65]) + , .WD_64 (Wdata[64]) + , .WD_63 (Wdata[63]) + , .WD_62 (Wdata[62]) + , .WD_61 (Wdata[61]) + , .WD_60 (Wdata[60]) + , .WD_59 (Wdata[59]) + , .WD_58 (Wdata[58]) + , .WD_57 (Wdata[57]) + , .WD_56 (Wdata[56]) + , .WD_55 (Wdata[55]) + , .WD_54 (Wdata[54]) + , .WD_53 (Wdata[53]) + , .WD_52 (Wdata[52]) + , .WD_51 (Wdata[51]) + , .WD_50 (Wdata[50]) + , .WD_49 (Wdata[49]) + , .WD_48 (Wdata[48]) + , .WD_47 (Wdata[47]) + , .WD_46 (Wdata[46]) + , .WD_45 (Wdata[45]) + , .WD_44 (Wdata[44]) + , .WD_43 (Wdata[43]) + , .WD_42 (Wdata[42]) + , .WD_41 (Wdata[41]) + , .WD_40 (Wdata[40]) + , .WD_39 (Wdata[39]) + , .WD_38 (Wdata[38]) + , .WD_37 (Wdata[37]) + , .WD_36 (Wdata[36]) + , .WD_35 (Wdata[35]) + , .WD_34 (Wdata[34]) + , .WD_33 (Wdata[33]) + , .WD_32 (Wdata[32]) + , .WD_31 (Wdata[31]) + , .WD_30 (Wdata[30]) + , .WD_29 (Wdata[29]) + , .WD_28 (Wdata[28]) + , .WD_27 (Wdata[27]) + , .WD_26 (Wdata[26]) + , .WD_25 (Wdata[25]) + , .WD_24 (Wdata[24]) + , .WD_23 (Wdata[23]) + , .WD_22 (Wdata[22]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_4 (ra_0_0 [4] & !test_mode) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_79 (ramDataOut[79]) + , .RD_78 (ramDataOut[78]) + , .RD_77 (ramDataOut[77]) + , .RD_76 (ramDataOut[76]) + , .RD_75 (ramDataOut[75]) + , .RD_74 (ramDataOut[74]) + , .RD_73 (ramDataOut[73]) + , .RD_72 (ramDataOut[72]) + , .RD_71 (ramDataOut[71]) + , .RD_70 (ramDataOut[70]) + , .RD_69 (ramDataOut[69]) + , .RD_68 (ramDataOut[68]) + , .RD_67 (ramDataOut[67]) + , .RD_66 (ramDataOut[66]) + , .RD_65 (ramDataOut[65]) + , .RD_64 (ramDataOut[64]) + , .RD_63 (ramDataOut[63]) + , .RD_62 (ramDataOut[62]) + , .RD_61 (ramDataOut[61]) + , .RD_60 (ramDataOut[60]) + , .RD_59 (ramDataOut[59]) + , .RD_58 (ramDataOut[58]) + , .RD_57 (ramDataOut[57]) + , .RD_56 (ramDataOut[56]) + , .RD_55 (ramDataOut[55]) + , .RD_54 (ramDataOut[54]) + , .RD_53 (ramDataOut[53]) + , .RD_52 (ramDataOut[52]) + , .RD_51 (ramDataOut[51]) + , .RD_50 (ramDataOut[50]) + , .RD_49 (ramDataOut[49]) + , .RD_48 (ramDataOut[48]) + , .RD_47 (ramDataOut[47]) + , .RD_46 (ramDataOut[46]) + , .RD_45 (ramDataOut[45]) + , .RD_44 (ramDataOut[44]) + , .RD_43 (ramDataOut[43]) + , .RD_42 (ramDataOut[42]) + , .RD_41 (ramDataOut[41]) + , .RD_40 (ramDataOut[40]) + , .RD_39 (ramDataOut[39]) + , .RD_38 (ramDataOut[38]) + , .RD_37 (ramDataOut[37]) + , .RD_36 (ramDataOut[36]) + , .RD_35 (ramDataOut[35]) + , .RD_34 (ramDataOut[34]) + , .RD_33 (ramDataOut[33]) + , .RD_32 (ramDataOut[32]) + , .RD_31 (ramDataOut[31]) + , .RD_30 (ramDataOut[30]) + , .RD_29 (ramDataOut[29]) + , .RD_28 (ramDataOut[28]) + , .RD_27 (ramDataOut[27]) + , .RD_26 (ramDataOut[26]) + , .RD_25 (ramDataOut[25]) + , .RD_24 (ramDataOut[24]) + , .RD_23 (ramDataOut[23]) + , .RD_22 (ramDataOut[22]) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [79:0] ram_r0_OutputMuxDataOut; +//For bitEnd 79, only one piece RAMDP_20X80_GL_M1_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[79:0] or muxed_Di_w0[79:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[79:0] = (ram_bypass) ? muxed_Di_w0[79:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[79:0] = ram_r0_OutputMuxDataOut[79:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [79:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [79:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 79 LSB 0 and total rambit is 80 and dsize is 80 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [79:0]data_regq; +assign Data_reg_r0[79:0] = data_regq[79:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[80-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(5, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(5, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(80, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[79:0]), .Q(data_regq[79:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80_logic.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80_logic.v.vcp new file mode 100644 index 0000000..8e6fe54 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_19x80_logic.v.vcp @@ -0,0 +1,708 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_19x80_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_19x80_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [79:0] dbyp; +input debug_mode; +input [79:0] di; +output [79:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [79:0] mbist_Do_r0_int_net; +input [4:0] mbist_Ra_r0; +input [4:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [4:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [4:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [4:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [79:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [79:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [79:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [79:0] pre_muxed_Di_w0; +wire [79:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[79:0]; +assign pre_muxed_Di_w0_B = {{40{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {80{`tick_x_or_0}}; + endcase +reg [79:0] muxed_Di_w0; +wire [79:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[79:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {80{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [4:0] pre_Wa_reg_w0; +reg [4:0] Wa_reg_w0; +wire [4:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {5{`tick_x_or_0}}; +endcase +reg [4:0] muxed_Wa_w0; +wire [4:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {5{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [4:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [4:0] pre_Ra_reg_r0; +reg [4:0] Ra_reg_r0; +wire [4:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {5{`tick_x_or_0}}; +endcase +wire [4:0] D_Ra_reg_r0; +reg [4:0] muxed_Ra_r0; +wire [4:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {5{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [4:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_20X80_GL_M1_E2 (RamCell) +// Covers Addresses from 0 to 19 Addressrange: [4:0] +// Data Bit range: [79:0] (80 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [4:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[4:0]; +// Write Data in bus +wire [79:0] Wdata; +assign Wdata = muxed_Di_w0[79:0]; +assign we_0_0 = we; +// Read Address bus +wire [4:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[4:0]; +// Read DataOut bus +wire [79:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_20X80_GL_M1_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [79:0] ramDataOut; +assign dout_0_0[79:0] = ramDataOut[79:0]; +RAMDP_20X80_GL_M1_E2 ram_Inst_19X80 ( + .CLK_W (gated_clk_core) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_79 (Wdata[79]) + , .WD_78 (Wdata[78]) + , .WD_77 (Wdata[77]) + , .WD_76 (Wdata[76]) + , .WD_75 (Wdata[75]) + , .WD_74 (Wdata[74]) + , .WD_73 (Wdata[73]) + , .WD_72 (Wdata[72]) + , .WD_71 (Wdata[71]) + , .WD_70 (Wdata[70]) + , .WD_69 (Wdata[69]) + , .WD_68 (Wdata[68]) + , .WD_67 (Wdata[67]) + , .WD_66 (Wdata[66]) + , .WD_65 (Wdata[65]) + , .WD_64 (Wdata[64]) + , .WD_63 (Wdata[63]) + , .WD_62 (Wdata[62]) + , .WD_61 (Wdata[61]) + , .WD_60 (Wdata[60]) + , .WD_59 (Wdata[59]) + , .WD_58 (Wdata[58]) + , .WD_57 (Wdata[57]) + , .WD_56 (Wdata[56]) + , .WD_55 (Wdata[55]) + , .WD_54 (Wdata[54]) + , .WD_53 (Wdata[53]) + , .WD_52 (Wdata[52]) + , .WD_51 (Wdata[51]) + , .WD_50 (Wdata[50]) + , .WD_49 (Wdata[49]) + , .WD_48 (Wdata[48]) + , .WD_47 (Wdata[47]) + , .WD_46 (Wdata[46]) + , .WD_45 (Wdata[45]) + , .WD_44 (Wdata[44]) + , .WD_43 (Wdata[43]) + , .WD_42 (Wdata[42]) + , .WD_41 (Wdata[41]) + , .WD_40 (Wdata[40]) + , .WD_39 (Wdata[39]) + , .WD_38 (Wdata[38]) + , .WD_37 (Wdata[37]) + , .WD_36 (Wdata[36]) + , .WD_35 (Wdata[35]) + , .WD_34 (Wdata[34]) + , .WD_33 (Wdata[33]) + , .WD_32 (Wdata[32]) + , .WD_31 (Wdata[31]) + , .WD_30 (Wdata[30]) + , .WD_29 (Wdata[29]) + , .WD_28 (Wdata[28]) + , .WD_27 (Wdata[27]) + , .WD_26 (Wdata[26]) + , .WD_25 (Wdata[25]) + , .WD_24 (Wdata[24]) + , .WD_23 (Wdata[23]) + , .WD_22 (Wdata[22]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_4 (ra_0_0 [4] & !test_mode) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_79 (ramDataOut[79]) + , .RD_78 (ramDataOut[78]) + , .RD_77 (ramDataOut[77]) + , .RD_76 (ramDataOut[76]) + , .RD_75 (ramDataOut[75]) + , .RD_74 (ramDataOut[74]) + , .RD_73 (ramDataOut[73]) + , .RD_72 (ramDataOut[72]) + , .RD_71 (ramDataOut[71]) + , .RD_70 (ramDataOut[70]) + , .RD_69 (ramDataOut[69]) + , .RD_68 (ramDataOut[68]) + , .RD_67 (ramDataOut[67]) + , .RD_66 (ramDataOut[66]) + , .RD_65 (ramDataOut[65]) + , .RD_64 (ramDataOut[64]) + , .RD_63 (ramDataOut[63]) + , .RD_62 (ramDataOut[62]) + , .RD_61 (ramDataOut[61]) + , .RD_60 (ramDataOut[60]) + , .RD_59 (ramDataOut[59]) + , .RD_58 (ramDataOut[58]) + , .RD_57 (ramDataOut[57]) + , .RD_56 (ramDataOut[56]) + , .RD_55 (ramDataOut[55]) + , .RD_54 (ramDataOut[54]) + , .RD_53 (ramDataOut[53]) + , .RD_52 (ramDataOut[52]) + , .RD_51 (ramDataOut[51]) + , .RD_50 (ramDataOut[50]) + , .RD_49 (ramDataOut[49]) + , .RD_48 (ramDataOut[48]) + , .RD_47 (ramDataOut[47]) + , .RD_46 (ramDataOut[46]) + , .RD_45 (ramDataOut[45]) + , .RD_44 (ramDataOut[44]) + , .RD_43 (ramDataOut[43]) + , .RD_42 (ramDataOut[42]) + , .RD_41 (ramDataOut[41]) + , .RD_40 (ramDataOut[40]) + , .RD_39 (ramDataOut[39]) + , .RD_38 (ramDataOut[38]) + , .RD_37 (ramDataOut[37]) + , .RD_36 (ramDataOut[36]) + , .RD_35 (ramDataOut[35]) + , .RD_34 (ramDataOut[34]) + , .RD_33 (ramDataOut[33]) + , .RD_32 (ramDataOut[32]) + , .RD_31 (ramDataOut[31]) + , .RD_30 (ramDataOut[30]) + , .RD_29 (ramDataOut[29]) + , .RD_28 (ramDataOut[28]) + , .RD_27 (ramDataOut[27]) + , .RD_26 (ramDataOut[26]) + , .RD_25 (ramDataOut[25]) + , .RD_24 (ramDataOut[24]) + , .RD_23 (ramDataOut[23]) + , .RD_22 (ramDataOut[22]) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [79:0] ram_r0_OutputMuxDataOut; +//For bitEnd 79, only one piece RAMDP_20X80_GL_M1_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[79:0] or muxed_Di_w0[79:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[79:0] = (ram_bypass) ? muxed_Di_w0[79:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[79:0] = ram_r0_OutputMuxDataOut[79:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [79:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [79:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 79 LSB 0 and total rambit is 80 and dsize is 80 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [79:0]data_regq; +assign Data_reg_r0[79:0] = data_regq[79:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[80-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(5, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(5, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(80, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[79:0]), .Q(data_regq[79:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168.v new file mode 100644 index 0000000..e2b011d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168.v @@ -0,0 +1,1108 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x168.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_60x168 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [167:0] dout; +input [5:0] wa; +input we; +input [167:0] di; +input byp_sel; +input [167:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMPDP_60X168_GL_M1_D2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [5:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [5:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [167:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [7:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_22 (.A(mbist_Do_r0_int_net[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_23 (.A(mbist_Do_r0_int_net[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_24 (.A(mbist_Do_r0_int_net[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_25 (.A(mbist_Do_r0_int_net[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_26 (.A(mbist_Do_r0_int_net[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_27 (.A(mbist_Do_r0_int_net[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_28 (.A(mbist_Do_r0_int_net[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_29 (.A(mbist_Do_r0_int_net[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_30 (.A(mbist_Do_r0_int_net[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_31 (.A(mbist_Do_r0_int_net[31])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_32 (.A(mbist_Do_r0_int_net[32])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_33 (.A(mbist_Do_r0_int_net[33])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_34 (.A(mbist_Do_r0_int_net[34])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_35 (.A(mbist_Do_r0_int_net[35])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_36 (.A(mbist_Do_r0_int_net[36])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_37 (.A(mbist_Do_r0_int_net[37])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_38 (.A(mbist_Do_r0_int_net[38])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_39 (.A(mbist_Do_r0_int_net[39])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_40 (.A(mbist_Do_r0_int_net[40])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_41 (.A(mbist_Do_r0_int_net[41])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_42 (.A(mbist_Do_r0_int_net[42])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_43 (.A(mbist_Do_r0_int_net[43])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_44 (.A(mbist_Do_r0_int_net[44])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_45 (.A(mbist_Do_r0_int_net[45])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_46 (.A(mbist_Do_r0_int_net[46])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_47 (.A(mbist_Do_r0_int_net[47])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_48 (.A(mbist_Do_r0_int_net[48])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_49 (.A(mbist_Do_r0_int_net[49])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_50 (.A(mbist_Do_r0_int_net[50])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_51 (.A(mbist_Do_r0_int_net[51])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_52 (.A(mbist_Do_r0_int_net[52])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_53 (.A(mbist_Do_r0_int_net[53])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_54 (.A(mbist_Do_r0_int_net[54])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_55 (.A(mbist_Do_r0_int_net[55])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_56 (.A(mbist_Do_r0_int_net[56])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_57 (.A(mbist_Do_r0_int_net[57])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_58 (.A(mbist_Do_r0_int_net[58])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_59 (.A(mbist_Do_r0_int_net[59])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_60 (.A(mbist_Do_r0_int_net[60])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_61 (.A(mbist_Do_r0_int_net[61])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_62 (.A(mbist_Do_r0_int_net[62])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_63 (.A(mbist_Do_r0_int_net[63])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_64 (.A(mbist_Do_r0_int_net[64])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_65 (.A(mbist_Do_r0_int_net[65])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_66 (.A(mbist_Do_r0_int_net[66])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_67 (.A(mbist_Do_r0_int_net[67])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_68 (.A(mbist_Do_r0_int_net[68])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_69 (.A(mbist_Do_r0_int_net[69])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_70 (.A(mbist_Do_r0_int_net[70])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_71 (.A(mbist_Do_r0_int_net[71])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_72 (.A(mbist_Do_r0_int_net[72])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_73 (.A(mbist_Do_r0_int_net[73])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_74 (.A(mbist_Do_r0_int_net[74])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_75 (.A(mbist_Do_r0_int_net[75])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_76 (.A(mbist_Do_r0_int_net[76])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_77 (.A(mbist_Do_r0_int_net[77])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_78 (.A(mbist_Do_r0_int_net[78])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_79 (.A(mbist_Do_r0_int_net[79])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_80 (.A(mbist_Do_r0_int_net[80])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_81 (.A(mbist_Do_r0_int_net[81])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_82 (.A(mbist_Do_r0_int_net[82])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_83 (.A(mbist_Do_r0_int_net[83])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_84 (.A(mbist_Do_r0_int_net[84])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_85 (.A(mbist_Do_r0_int_net[85])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_86 (.A(mbist_Do_r0_int_net[86])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_87 (.A(mbist_Do_r0_int_net[87])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_88 (.A(mbist_Do_r0_int_net[88])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_89 (.A(mbist_Do_r0_int_net[89])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_90 (.A(mbist_Do_r0_int_net[90])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_91 (.A(mbist_Do_r0_int_net[91])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_92 (.A(mbist_Do_r0_int_net[92])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_93 (.A(mbist_Do_r0_int_net[93])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_94 (.A(mbist_Do_r0_int_net[94])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_95 (.A(mbist_Do_r0_int_net[95])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_96 (.A(mbist_Do_r0_int_net[96])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_97 (.A(mbist_Do_r0_int_net[97])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_98 (.A(mbist_Do_r0_int_net[98])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_99 (.A(mbist_Do_r0_int_net[99])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_100 (.A(mbist_Do_r0_int_net[100])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_101 (.A(mbist_Do_r0_int_net[101])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_102 (.A(mbist_Do_r0_int_net[102])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_103 (.A(mbist_Do_r0_int_net[103])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_104 (.A(mbist_Do_r0_int_net[104])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_105 (.A(mbist_Do_r0_int_net[105])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_106 (.A(mbist_Do_r0_int_net[106])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_107 (.A(mbist_Do_r0_int_net[107])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_108 (.A(mbist_Do_r0_int_net[108])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_109 (.A(mbist_Do_r0_int_net[109])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_110 (.A(mbist_Do_r0_int_net[110])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_111 (.A(mbist_Do_r0_int_net[111])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_112 (.A(mbist_Do_r0_int_net[112])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_113 (.A(mbist_Do_r0_int_net[113])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_114 (.A(mbist_Do_r0_int_net[114])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_115 (.A(mbist_Do_r0_int_net[115])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_116 (.A(mbist_Do_r0_int_net[116])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_117 (.A(mbist_Do_r0_int_net[117])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_118 (.A(mbist_Do_r0_int_net[118])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_119 (.A(mbist_Do_r0_int_net[119])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_120 (.A(mbist_Do_r0_int_net[120])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_121 (.A(mbist_Do_r0_int_net[121])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_122 (.A(mbist_Do_r0_int_net[122])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_123 (.A(mbist_Do_r0_int_net[123])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_124 (.A(mbist_Do_r0_int_net[124])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_125 (.A(mbist_Do_r0_int_net[125])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_126 (.A(mbist_Do_r0_int_net[126])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_127 (.A(mbist_Do_r0_int_net[127])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_128 (.A(mbist_Do_r0_int_net[128])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_129 (.A(mbist_Do_r0_int_net[129])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_130 (.A(mbist_Do_r0_int_net[130])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_131 (.A(mbist_Do_r0_int_net[131])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_132 (.A(mbist_Do_r0_int_net[132])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_133 (.A(mbist_Do_r0_int_net[133])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_134 (.A(mbist_Do_r0_int_net[134])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_135 (.A(mbist_Do_r0_int_net[135])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_136 (.A(mbist_Do_r0_int_net[136])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_137 (.A(mbist_Do_r0_int_net[137])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_138 (.A(mbist_Do_r0_int_net[138])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_139 (.A(mbist_Do_r0_int_net[139])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_140 (.A(mbist_Do_r0_int_net[140])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_141 (.A(mbist_Do_r0_int_net[141])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_142 (.A(mbist_Do_r0_int_net[142])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_143 (.A(mbist_Do_r0_int_net[143])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_144 (.A(mbist_Do_r0_int_net[144])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_145 (.A(mbist_Do_r0_int_net[145])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_146 (.A(mbist_Do_r0_int_net[146])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_147 (.A(mbist_Do_r0_int_net[147])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_148 (.A(mbist_Do_r0_int_net[148])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_149 (.A(mbist_Do_r0_int_net[149])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_150 (.A(mbist_Do_r0_int_net[150])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_151 (.A(mbist_Do_r0_int_net[151])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_152 (.A(mbist_Do_r0_int_net[152])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_153 (.A(mbist_Do_r0_int_net[153])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_154 (.A(mbist_Do_r0_int_net[154])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_155 (.A(mbist_Do_r0_int_net[155])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_156 (.A(mbist_Do_r0_int_net[156])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_157 (.A(mbist_Do_r0_int_net[157])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_158 (.A(mbist_Do_r0_int_net[158])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_159 (.A(mbist_Do_r0_int_net[159])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_160 (.A(mbist_Do_r0_int_net[160])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_161 (.A(mbist_Do_r0_int_net[161])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_162 (.A(mbist_Do_r0_int_net[162])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_163 (.A(mbist_Do_r0_int_net[163])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_164 (.A(mbist_Do_r0_int_net[164])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_165 (.A(mbist_Do_r0_int_net[165])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_166 (.A(mbist_Do_r0_int_net[166])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_167 (.A(mbist_Do_r0_int_net[167])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +NV_BLKBOX_SRC0 testInst_svop_2 (.Y(svop[2])); +NV_BLKBOX_SRC0 testInst_svop_3 (.Y(svop[3])); +NV_BLKBOX_SRC0 testInst_svop_4 (.Y(svop[4])); +NV_BLKBOX_SRC0 testInst_svop_5 (.Y(svop[5])); +NV_BLKBOX_SRC0 testInst_svop_6 (.Y(svop[6])); +NV_BLKBOX_SRC0 testInst_svop_7 (.Y(svop[7])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_60x168_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_60x168 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[167:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + arrangment_string[32] = 32 ; + arrangment_string[33] = 33 ; + arrangment_string[34] = 34 ; + arrangment_string[35] = 35 ; + arrangment_string[36] = 36 ; + arrangment_string[37] = 37 ; + arrangment_string[38] = 38 ; + arrangment_string[39] = 39 ; + arrangment_string[40] = 40 ; + arrangment_string[41] = 41 ; + arrangment_string[42] = 42 ; + arrangment_string[43] = 43 ; + arrangment_string[44] = 44 ; + arrangment_string[45] = 45 ; + arrangment_string[46] = 46 ; + arrangment_string[47] = 47 ; + arrangment_string[48] = 48 ; + arrangment_string[49] = 49 ; + arrangment_string[50] = 50 ; + arrangment_string[51] = 51 ; + arrangment_string[52] = 52 ; + arrangment_string[53] = 53 ; + arrangment_string[54] = 54 ; + arrangment_string[55] = 55 ; + arrangment_string[56] = 56 ; + arrangment_string[57] = 57 ; + arrangment_string[58] = 58 ; + arrangment_string[59] = 59 ; + arrangment_string[60] = 60 ; + arrangment_string[61] = 61 ; + arrangment_string[62] = 62 ; + arrangment_string[63] = 63 ; + arrangment_string[64] = 64 ; + arrangment_string[65] = 65 ; + arrangment_string[66] = 66 ; + arrangment_string[67] = 67 ; + arrangment_string[68] = 68 ; + arrangment_string[69] = 69 ; + arrangment_string[70] = 70 ; + arrangment_string[71] = 71 ; + arrangment_string[72] = 72 ; + arrangment_string[73] = 73 ; + arrangment_string[74] = 74 ; + arrangment_string[75] = 75 ; + arrangment_string[76] = 76 ; + arrangment_string[77] = 77 ; + arrangment_string[78] = 78 ; + arrangment_string[79] = 79 ; + arrangment_string[80] = 80 ; + arrangment_string[81] = 81 ; + arrangment_string[82] = 82 ; + arrangment_string[83] = 83 ; + arrangment_string[84] = 84 ; + arrangment_string[85] = 85 ; + arrangment_string[86] = 86 ; + arrangment_string[87] = 87 ; + arrangment_string[88] = 88 ; + arrangment_string[89] = 89 ; + arrangment_string[90] = 90 ; + arrangment_string[91] = 91 ; + arrangment_string[92] = 92 ; + arrangment_string[93] = 93 ; + arrangment_string[94] = 94 ; + arrangment_string[95] = 95 ; + arrangment_string[96] = 96 ; + arrangment_string[97] = 97 ; + arrangment_string[98] = 98 ; + arrangment_string[99] = 99 ; + arrangment_string[100] = 100 ; + arrangment_string[101] = 101 ; + arrangment_string[102] = 102 ; + arrangment_string[103] = 103 ; + arrangment_string[104] = 104 ; + arrangment_string[105] = 105 ; + arrangment_string[106] = 106 ; + arrangment_string[107] = 107 ; + arrangment_string[108] = 108 ; + arrangment_string[109] = 109 ; + arrangment_string[110] = 110 ; + arrangment_string[111] = 111 ; + arrangment_string[112] = 112 ; + arrangment_string[113] = 113 ; + arrangment_string[114] = 114 ; + arrangment_string[115] = 115 ; + arrangment_string[116] = 116 ; + arrangment_string[117] = 117 ; + arrangment_string[118] = 118 ; + arrangment_string[119] = 119 ; + arrangment_string[120] = 120 ; + arrangment_string[121] = 121 ; + arrangment_string[122] = 122 ; + arrangment_string[123] = 123 ; + arrangment_string[124] = 124 ; + arrangment_string[125] = 125 ; + arrangment_string[126] = 126 ; + arrangment_string[127] = 127 ; + arrangment_string[128] = 128 ; + arrangment_string[129] = 129 ; + arrangment_string[130] = 130 ; + arrangment_string[131] = 131 ; + arrangment_string[132] = 132 ; + arrangment_string[133] = 133 ; + arrangment_string[134] = 134 ; + arrangment_string[135] = 135 ; + arrangment_string[136] = 136 ; + arrangment_string[137] = 137 ; + arrangment_string[138] = 138 ; + arrangment_string[139] = 139 ; + arrangment_string[140] = 140 ; + arrangment_string[141] = 141 ; + arrangment_string[142] = 142 ; + arrangment_string[143] = 143 ; + arrangment_string[144] = 144 ; + arrangment_string[145] = 145 ; + arrangment_string[146] = 146 ; + arrangment_string[147] = 147 ; + arrangment_string[148] = 148 ; + arrangment_string[149] = 149 ; + arrangment_string[150] = 150 ; + arrangment_string[151] = 151 ; + arrangment_string[152] = 152 ; + arrangment_string[153] = 153 ; + arrangment_string[154] = 154 ; + arrangment_string[155] = 155 ; + arrangment_string[156] = 156 ; + arrangment_string[157] = 157 ; + arrangment_string[158] = 158 ; + arrangment_string[159] = 159 ; + arrangment_string[160] = 160 ; + arrangment_string[161] = 161 ; + arrangment_string[162] = 162 ; + arrangment_string[163] = 163 ; + arrangment_string[164] = 164 ; + arrangment_string[165] = 165 ; + arrangment_string[166] = 166 ; + arrangment_string[167] = 167 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [59:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [167:0] shadow_mem [59:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [167:0] shadow_mem_row0 = shadow_mem[0]; +wire [167:0] shadow_mem_row1 = shadow_mem[1]; +wire [167:0] shadow_mem_row2 = shadow_mem[2]; +wire [167:0] shadow_mem_row3 = shadow_mem[3]; +wire [167:0] shadow_mem_row4 = shadow_mem[4]; +wire [167:0] shadow_mem_row5 = shadow_mem[5]; +wire [167:0] shadow_mem_row6 = shadow_mem[6]; +wire [167:0] shadow_mem_row7 = shadow_mem[7]; +wire [167:0] shadow_mem_row8 = shadow_mem[8]; +wire [167:0] shadow_mem_row9 = shadow_mem[9]; +wire [167:0] shadow_mem_row10 = shadow_mem[10]; +wire [167:0] shadow_mem_row11 = shadow_mem[11]; +wire [167:0] shadow_mem_row12 = shadow_mem[12]; +wire [167:0] shadow_mem_row13 = shadow_mem[13]; +wire [167:0] shadow_mem_row14 = shadow_mem[14]; +wire [167:0] shadow_mem_row15 = shadow_mem[15]; +wire [167:0] shadow_mem_row16 = shadow_mem[16]; +wire [167:0] shadow_mem_row17 = shadow_mem[17]; +wire [167:0] shadow_mem_row18 = shadow_mem[18]; +wire [167:0] shadow_mem_row19 = shadow_mem[19]; +wire [167:0] shadow_mem_row20 = shadow_mem[20]; +wire [167:0] shadow_mem_row21 = shadow_mem[21]; +wire [167:0] shadow_mem_row22 = shadow_mem[22]; +wire [167:0] shadow_mem_row23 = shadow_mem[23]; +wire [167:0] shadow_mem_row24 = shadow_mem[24]; +wire [167:0] shadow_mem_row25 = shadow_mem[25]; +wire [167:0] shadow_mem_row26 = shadow_mem[26]; +wire [167:0] shadow_mem_row27 = shadow_mem[27]; +wire [167:0] shadow_mem_row28 = shadow_mem[28]; +wire [167:0] shadow_mem_row29 = shadow_mem[29]; +wire [167:0] shadow_mem_row30 = shadow_mem[30]; +wire [167:0] shadow_mem_row31 = shadow_mem[31]; +wire [167:0] shadow_mem_row32 = shadow_mem[32]; +wire [167:0] shadow_mem_row33 = shadow_mem[33]; +wire [167:0] shadow_mem_row34 = shadow_mem[34]; +wire [167:0] shadow_mem_row35 = shadow_mem[35]; +wire [167:0] shadow_mem_row36 = shadow_mem[36]; +wire [167:0] shadow_mem_row37 = shadow_mem[37]; +wire [167:0] shadow_mem_row38 = shadow_mem[38]; +wire [167:0] shadow_mem_row39 = shadow_mem[39]; +wire [167:0] shadow_mem_row40 = shadow_mem[40]; +wire [167:0] shadow_mem_row41 = shadow_mem[41]; +wire [167:0] shadow_mem_row42 = shadow_mem[42]; +wire [167:0] shadow_mem_row43 = shadow_mem[43]; +wire [167:0] shadow_mem_row44 = shadow_mem[44]; +wire [167:0] shadow_mem_row45 = shadow_mem[45]; +wire [167:0] shadow_mem_row46 = shadow_mem[46]; +wire [167:0] shadow_mem_row47 = shadow_mem[47]; +wire [167:0] shadow_mem_row48 = shadow_mem[48]; +wire [167:0] shadow_mem_row49 = shadow_mem[49]; +wire [167:0] shadow_mem_row50 = shadow_mem[50]; +wire [167:0] shadow_mem_row51 = shadow_mem[51]; +wire [167:0] shadow_mem_row52 = shadow_mem[52]; +wire [167:0] shadow_mem_row53 = shadow_mem[53]; +wire [167:0] shadow_mem_row54 = shadow_mem[54]; +wire [167:0] shadow_mem_row55 = shadow_mem[55]; +wire [167:0] shadow_mem_row56 = shadow_mem[56]; +wire [167:0] shadow_mem_row57 = shadow_mem[57]; +wire [167:0] shadow_mem_row58 = shadow_mem[58]; +wire [167:0] shadow_mem_row59 = shadow_mem[59]; +`endif +task init_mem_val; + input [5:0] row; + input [167:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMPDP_60X168_GL_M1_D2 +for (row = 0; row < 60; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_60x168.ram_Inst_60X168.mem_write(row - 0, shadow_mem[row][167:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [5:0] wa; + input we; + input [167:0] di; + reg [167:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [167:0] probe_mem_val; +input [5:0] row; +reg [167:0] data; +begin +// probing RAMPDP_60X168_GL_M1_D2 + if (row >= 0 && row < 60) data[167:0] = r_nv_ram_rwsthp_60x168.ram_Inst_60X168.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 60; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +RANDFUNC rf1 (); +RANDFUNC rf2 (); +RANDFUNC rf3 (); +RANDFUNC rf4 (); +RANDFUNC rf5 (); +task init_mem_random; +reg [167:0] random_num; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff),rf1.rollpli(0,32'hffffffff),rf2.rollpli(0,32'hffffffff),rf3.rollpli(0,32'hffffffff),rf4.rollpli(0,32'hffffffff),rf5.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 10080); + row = random_num / 168; + bitnum = random_num % 168; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [5:0] row; +input [167:0] bitnum; +reg [167:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168.v.vcp new file mode 100644 index 0000000..e2b011d --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168.v.vcp @@ -0,0 +1,1108 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x168.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_60x168 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [167:0] dout; +input [5:0] wa; +input we; +input [167:0] di; +input byp_sel; +input [167:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMPDP_60X168_GL_M1_D2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [5:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [5:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [167:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [7:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_22 (.A(mbist_Do_r0_int_net[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_23 (.A(mbist_Do_r0_int_net[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_24 (.A(mbist_Do_r0_int_net[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_25 (.A(mbist_Do_r0_int_net[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_26 (.A(mbist_Do_r0_int_net[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_27 (.A(mbist_Do_r0_int_net[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_28 (.A(mbist_Do_r0_int_net[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_29 (.A(mbist_Do_r0_int_net[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_30 (.A(mbist_Do_r0_int_net[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_31 (.A(mbist_Do_r0_int_net[31])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_32 (.A(mbist_Do_r0_int_net[32])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_33 (.A(mbist_Do_r0_int_net[33])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_34 (.A(mbist_Do_r0_int_net[34])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_35 (.A(mbist_Do_r0_int_net[35])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_36 (.A(mbist_Do_r0_int_net[36])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_37 (.A(mbist_Do_r0_int_net[37])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_38 (.A(mbist_Do_r0_int_net[38])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_39 (.A(mbist_Do_r0_int_net[39])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_40 (.A(mbist_Do_r0_int_net[40])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_41 (.A(mbist_Do_r0_int_net[41])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_42 (.A(mbist_Do_r0_int_net[42])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_43 (.A(mbist_Do_r0_int_net[43])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_44 (.A(mbist_Do_r0_int_net[44])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_45 (.A(mbist_Do_r0_int_net[45])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_46 (.A(mbist_Do_r0_int_net[46])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_47 (.A(mbist_Do_r0_int_net[47])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_48 (.A(mbist_Do_r0_int_net[48])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_49 (.A(mbist_Do_r0_int_net[49])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_50 (.A(mbist_Do_r0_int_net[50])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_51 (.A(mbist_Do_r0_int_net[51])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_52 (.A(mbist_Do_r0_int_net[52])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_53 (.A(mbist_Do_r0_int_net[53])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_54 (.A(mbist_Do_r0_int_net[54])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_55 (.A(mbist_Do_r0_int_net[55])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_56 (.A(mbist_Do_r0_int_net[56])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_57 (.A(mbist_Do_r0_int_net[57])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_58 (.A(mbist_Do_r0_int_net[58])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_59 (.A(mbist_Do_r0_int_net[59])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_60 (.A(mbist_Do_r0_int_net[60])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_61 (.A(mbist_Do_r0_int_net[61])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_62 (.A(mbist_Do_r0_int_net[62])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_63 (.A(mbist_Do_r0_int_net[63])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_64 (.A(mbist_Do_r0_int_net[64])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_65 (.A(mbist_Do_r0_int_net[65])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_66 (.A(mbist_Do_r0_int_net[66])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_67 (.A(mbist_Do_r0_int_net[67])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_68 (.A(mbist_Do_r0_int_net[68])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_69 (.A(mbist_Do_r0_int_net[69])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_70 (.A(mbist_Do_r0_int_net[70])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_71 (.A(mbist_Do_r0_int_net[71])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_72 (.A(mbist_Do_r0_int_net[72])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_73 (.A(mbist_Do_r0_int_net[73])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_74 (.A(mbist_Do_r0_int_net[74])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_75 (.A(mbist_Do_r0_int_net[75])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_76 (.A(mbist_Do_r0_int_net[76])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_77 (.A(mbist_Do_r0_int_net[77])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_78 (.A(mbist_Do_r0_int_net[78])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_79 (.A(mbist_Do_r0_int_net[79])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_80 (.A(mbist_Do_r0_int_net[80])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_81 (.A(mbist_Do_r0_int_net[81])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_82 (.A(mbist_Do_r0_int_net[82])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_83 (.A(mbist_Do_r0_int_net[83])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_84 (.A(mbist_Do_r0_int_net[84])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_85 (.A(mbist_Do_r0_int_net[85])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_86 (.A(mbist_Do_r0_int_net[86])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_87 (.A(mbist_Do_r0_int_net[87])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_88 (.A(mbist_Do_r0_int_net[88])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_89 (.A(mbist_Do_r0_int_net[89])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_90 (.A(mbist_Do_r0_int_net[90])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_91 (.A(mbist_Do_r0_int_net[91])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_92 (.A(mbist_Do_r0_int_net[92])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_93 (.A(mbist_Do_r0_int_net[93])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_94 (.A(mbist_Do_r0_int_net[94])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_95 (.A(mbist_Do_r0_int_net[95])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_96 (.A(mbist_Do_r0_int_net[96])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_97 (.A(mbist_Do_r0_int_net[97])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_98 (.A(mbist_Do_r0_int_net[98])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_99 (.A(mbist_Do_r0_int_net[99])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_100 (.A(mbist_Do_r0_int_net[100])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_101 (.A(mbist_Do_r0_int_net[101])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_102 (.A(mbist_Do_r0_int_net[102])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_103 (.A(mbist_Do_r0_int_net[103])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_104 (.A(mbist_Do_r0_int_net[104])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_105 (.A(mbist_Do_r0_int_net[105])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_106 (.A(mbist_Do_r0_int_net[106])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_107 (.A(mbist_Do_r0_int_net[107])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_108 (.A(mbist_Do_r0_int_net[108])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_109 (.A(mbist_Do_r0_int_net[109])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_110 (.A(mbist_Do_r0_int_net[110])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_111 (.A(mbist_Do_r0_int_net[111])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_112 (.A(mbist_Do_r0_int_net[112])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_113 (.A(mbist_Do_r0_int_net[113])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_114 (.A(mbist_Do_r0_int_net[114])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_115 (.A(mbist_Do_r0_int_net[115])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_116 (.A(mbist_Do_r0_int_net[116])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_117 (.A(mbist_Do_r0_int_net[117])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_118 (.A(mbist_Do_r0_int_net[118])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_119 (.A(mbist_Do_r0_int_net[119])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_120 (.A(mbist_Do_r0_int_net[120])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_121 (.A(mbist_Do_r0_int_net[121])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_122 (.A(mbist_Do_r0_int_net[122])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_123 (.A(mbist_Do_r0_int_net[123])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_124 (.A(mbist_Do_r0_int_net[124])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_125 (.A(mbist_Do_r0_int_net[125])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_126 (.A(mbist_Do_r0_int_net[126])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_127 (.A(mbist_Do_r0_int_net[127])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_128 (.A(mbist_Do_r0_int_net[128])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_129 (.A(mbist_Do_r0_int_net[129])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_130 (.A(mbist_Do_r0_int_net[130])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_131 (.A(mbist_Do_r0_int_net[131])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_132 (.A(mbist_Do_r0_int_net[132])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_133 (.A(mbist_Do_r0_int_net[133])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_134 (.A(mbist_Do_r0_int_net[134])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_135 (.A(mbist_Do_r0_int_net[135])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_136 (.A(mbist_Do_r0_int_net[136])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_137 (.A(mbist_Do_r0_int_net[137])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_138 (.A(mbist_Do_r0_int_net[138])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_139 (.A(mbist_Do_r0_int_net[139])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_140 (.A(mbist_Do_r0_int_net[140])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_141 (.A(mbist_Do_r0_int_net[141])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_142 (.A(mbist_Do_r0_int_net[142])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_143 (.A(mbist_Do_r0_int_net[143])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_144 (.A(mbist_Do_r0_int_net[144])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_145 (.A(mbist_Do_r0_int_net[145])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_146 (.A(mbist_Do_r0_int_net[146])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_147 (.A(mbist_Do_r0_int_net[147])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_148 (.A(mbist_Do_r0_int_net[148])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_149 (.A(mbist_Do_r0_int_net[149])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_150 (.A(mbist_Do_r0_int_net[150])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_151 (.A(mbist_Do_r0_int_net[151])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_152 (.A(mbist_Do_r0_int_net[152])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_153 (.A(mbist_Do_r0_int_net[153])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_154 (.A(mbist_Do_r0_int_net[154])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_155 (.A(mbist_Do_r0_int_net[155])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_156 (.A(mbist_Do_r0_int_net[156])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_157 (.A(mbist_Do_r0_int_net[157])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_158 (.A(mbist_Do_r0_int_net[158])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_159 (.A(mbist_Do_r0_int_net[159])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_160 (.A(mbist_Do_r0_int_net[160])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_161 (.A(mbist_Do_r0_int_net[161])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_162 (.A(mbist_Do_r0_int_net[162])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_163 (.A(mbist_Do_r0_int_net[163])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_164 (.A(mbist_Do_r0_int_net[164])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_165 (.A(mbist_Do_r0_int_net[165])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_166 (.A(mbist_Do_r0_int_net[166])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_167 (.A(mbist_Do_r0_int_net[167])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +NV_BLKBOX_SRC0 testInst_svop_2 (.Y(svop[2])); +NV_BLKBOX_SRC0 testInst_svop_3 (.Y(svop[3])); +NV_BLKBOX_SRC0 testInst_svop_4 (.Y(svop[4])); +NV_BLKBOX_SRC0 testInst_svop_5 (.Y(svop[5])); +NV_BLKBOX_SRC0 testInst_svop_6 (.Y(svop[6])); +NV_BLKBOX_SRC0 testInst_svop_7 (.Y(svop[7])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_60x168_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_60x168 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[167:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + arrangment_string[32] = 32 ; + arrangment_string[33] = 33 ; + arrangment_string[34] = 34 ; + arrangment_string[35] = 35 ; + arrangment_string[36] = 36 ; + arrangment_string[37] = 37 ; + arrangment_string[38] = 38 ; + arrangment_string[39] = 39 ; + arrangment_string[40] = 40 ; + arrangment_string[41] = 41 ; + arrangment_string[42] = 42 ; + arrangment_string[43] = 43 ; + arrangment_string[44] = 44 ; + arrangment_string[45] = 45 ; + arrangment_string[46] = 46 ; + arrangment_string[47] = 47 ; + arrangment_string[48] = 48 ; + arrangment_string[49] = 49 ; + arrangment_string[50] = 50 ; + arrangment_string[51] = 51 ; + arrangment_string[52] = 52 ; + arrangment_string[53] = 53 ; + arrangment_string[54] = 54 ; + arrangment_string[55] = 55 ; + arrangment_string[56] = 56 ; + arrangment_string[57] = 57 ; + arrangment_string[58] = 58 ; + arrangment_string[59] = 59 ; + arrangment_string[60] = 60 ; + arrangment_string[61] = 61 ; + arrangment_string[62] = 62 ; + arrangment_string[63] = 63 ; + arrangment_string[64] = 64 ; + arrangment_string[65] = 65 ; + arrangment_string[66] = 66 ; + arrangment_string[67] = 67 ; + arrangment_string[68] = 68 ; + arrangment_string[69] = 69 ; + arrangment_string[70] = 70 ; + arrangment_string[71] = 71 ; + arrangment_string[72] = 72 ; + arrangment_string[73] = 73 ; + arrangment_string[74] = 74 ; + arrangment_string[75] = 75 ; + arrangment_string[76] = 76 ; + arrangment_string[77] = 77 ; + arrangment_string[78] = 78 ; + arrangment_string[79] = 79 ; + arrangment_string[80] = 80 ; + arrangment_string[81] = 81 ; + arrangment_string[82] = 82 ; + arrangment_string[83] = 83 ; + arrangment_string[84] = 84 ; + arrangment_string[85] = 85 ; + arrangment_string[86] = 86 ; + arrangment_string[87] = 87 ; + arrangment_string[88] = 88 ; + arrangment_string[89] = 89 ; + arrangment_string[90] = 90 ; + arrangment_string[91] = 91 ; + arrangment_string[92] = 92 ; + arrangment_string[93] = 93 ; + arrangment_string[94] = 94 ; + arrangment_string[95] = 95 ; + arrangment_string[96] = 96 ; + arrangment_string[97] = 97 ; + arrangment_string[98] = 98 ; + arrangment_string[99] = 99 ; + arrangment_string[100] = 100 ; + arrangment_string[101] = 101 ; + arrangment_string[102] = 102 ; + arrangment_string[103] = 103 ; + arrangment_string[104] = 104 ; + arrangment_string[105] = 105 ; + arrangment_string[106] = 106 ; + arrangment_string[107] = 107 ; + arrangment_string[108] = 108 ; + arrangment_string[109] = 109 ; + arrangment_string[110] = 110 ; + arrangment_string[111] = 111 ; + arrangment_string[112] = 112 ; + arrangment_string[113] = 113 ; + arrangment_string[114] = 114 ; + arrangment_string[115] = 115 ; + arrangment_string[116] = 116 ; + arrangment_string[117] = 117 ; + arrangment_string[118] = 118 ; + arrangment_string[119] = 119 ; + arrangment_string[120] = 120 ; + arrangment_string[121] = 121 ; + arrangment_string[122] = 122 ; + arrangment_string[123] = 123 ; + arrangment_string[124] = 124 ; + arrangment_string[125] = 125 ; + arrangment_string[126] = 126 ; + arrangment_string[127] = 127 ; + arrangment_string[128] = 128 ; + arrangment_string[129] = 129 ; + arrangment_string[130] = 130 ; + arrangment_string[131] = 131 ; + arrangment_string[132] = 132 ; + arrangment_string[133] = 133 ; + arrangment_string[134] = 134 ; + arrangment_string[135] = 135 ; + arrangment_string[136] = 136 ; + arrangment_string[137] = 137 ; + arrangment_string[138] = 138 ; + arrangment_string[139] = 139 ; + arrangment_string[140] = 140 ; + arrangment_string[141] = 141 ; + arrangment_string[142] = 142 ; + arrangment_string[143] = 143 ; + arrangment_string[144] = 144 ; + arrangment_string[145] = 145 ; + arrangment_string[146] = 146 ; + arrangment_string[147] = 147 ; + arrangment_string[148] = 148 ; + arrangment_string[149] = 149 ; + arrangment_string[150] = 150 ; + arrangment_string[151] = 151 ; + arrangment_string[152] = 152 ; + arrangment_string[153] = 153 ; + arrangment_string[154] = 154 ; + arrangment_string[155] = 155 ; + arrangment_string[156] = 156 ; + arrangment_string[157] = 157 ; + arrangment_string[158] = 158 ; + arrangment_string[159] = 159 ; + arrangment_string[160] = 160 ; + arrangment_string[161] = 161 ; + arrangment_string[162] = 162 ; + arrangment_string[163] = 163 ; + arrangment_string[164] = 164 ; + arrangment_string[165] = 165 ; + arrangment_string[166] = 166 ; + arrangment_string[167] = 167 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [59:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [167:0] shadow_mem [59:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [167:0] shadow_mem_row0 = shadow_mem[0]; +wire [167:0] shadow_mem_row1 = shadow_mem[1]; +wire [167:0] shadow_mem_row2 = shadow_mem[2]; +wire [167:0] shadow_mem_row3 = shadow_mem[3]; +wire [167:0] shadow_mem_row4 = shadow_mem[4]; +wire [167:0] shadow_mem_row5 = shadow_mem[5]; +wire [167:0] shadow_mem_row6 = shadow_mem[6]; +wire [167:0] shadow_mem_row7 = shadow_mem[7]; +wire [167:0] shadow_mem_row8 = shadow_mem[8]; +wire [167:0] shadow_mem_row9 = shadow_mem[9]; +wire [167:0] shadow_mem_row10 = shadow_mem[10]; +wire [167:0] shadow_mem_row11 = shadow_mem[11]; +wire [167:0] shadow_mem_row12 = shadow_mem[12]; +wire [167:0] shadow_mem_row13 = shadow_mem[13]; +wire [167:0] shadow_mem_row14 = shadow_mem[14]; +wire [167:0] shadow_mem_row15 = shadow_mem[15]; +wire [167:0] shadow_mem_row16 = shadow_mem[16]; +wire [167:0] shadow_mem_row17 = shadow_mem[17]; +wire [167:0] shadow_mem_row18 = shadow_mem[18]; +wire [167:0] shadow_mem_row19 = shadow_mem[19]; +wire [167:0] shadow_mem_row20 = shadow_mem[20]; +wire [167:0] shadow_mem_row21 = shadow_mem[21]; +wire [167:0] shadow_mem_row22 = shadow_mem[22]; +wire [167:0] shadow_mem_row23 = shadow_mem[23]; +wire [167:0] shadow_mem_row24 = shadow_mem[24]; +wire [167:0] shadow_mem_row25 = shadow_mem[25]; +wire [167:0] shadow_mem_row26 = shadow_mem[26]; +wire [167:0] shadow_mem_row27 = shadow_mem[27]; +wire [167:0] shadow_mem_row28 = shadow_mem[28]; +wire [167:0] shadow_mem_row29 = shadow_mem[29]; +wire [167:0] shadow_mem_row30 = shadow_mem[30]; +wire [167:0] shadow_mem_row31 = shadow_mem[31]; +wire [167:0] shadow_mem_row32 = shadow_mem[32]; +wire [167:0] shadow_mem_row33 = shadow_mem[33]; +wire [167:0] shadow_mem_row34 = shadow_mem[34]; +wire [167:0] shadow_mem_row35 = shadow_mem[35]; +wire [167:0] shadow_mem_row36 = shadow_mem[36]; +wire [167:0] shadow_mem_row37 = shadow_mem[37]; +wire [167:0] shadow_mem_row38 = shadow_mem[38]; +wire [167:0] shadow_mem_row39 = shadow_mem[39]; +wire [167:0] shadow_mem_row40 = shadow_mem[40]; +wire [167:0] shadow_mem_row41 = shadow_mem[41]; +wire [167:0] shadow_mem_row42 = shadow_mem[42]; +wire [167:0] shadow_mem_row43 = shadow_mem[43]; +wire [167:0] shadow_mem_row44 = shadow_mem[44]; +wire [167:0] shadow_mem_row45 = shadow_mem[45]; +wire [167:0] shadow_mem_row46 = shadow_mem[46]; +wire [167:0] shadow_mem_row47 = shadow_mem[47]; +wire [167:0] shadow_mem_row48 = shadow_mem[48]; +wire [167:0] shadow_mem_row49 = shadow_mem[49]; +wire [167:0] shadow_mem_row50 = shadow_mem[50]; +wire [167:0] shadow_mem_row51 = shadow_mem[51]; +wire [167:0] shadow_mem_row52 = shadow_mem[52]; +wire [167:0] shadow_mem_row53 = shadow_mem[53]; +wire [167:0] shadow_mem_row54 = shadow_mem[54]; +wire [167:0] shadow_mem_row55 = shadow_mem[55]; +wire [167:0] shadow_mem_row56 = shadow_mem[56]; +wire [167:0] shadow_mem_row57 = shadow_mem[57]; +wire [167:0] shadow_mem_row58 = shadow_mem[58]; +wire [167:0] shadow_mem_row59 = shadow_mem[59]; +`endif +task init_mem_val; + input [5:0] row; + input [167:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMPDP_60X168_GL_M1_D2 +for (row = 0; row < 60; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_60x168.ram_Inst_60X168.mem_write(row - 0, shadow_mem[row][167:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [5:0] wa; + input we; + input [167:0] di; + reg [167:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [167:0] probe_mem_val; +input [5:0] row; +reg [167:0] data; +begin +// probing RAMPDP_60X168_GL_M1_D2 + if (row >= 0 && row < 60) data[167:0] = r_nv_ram_rwsthp_60x168.ram_Inst_60X168.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 60; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +RANDFUNC rf1 (); +RANDFUNC rf2 (); +RANDFUNC rf3 (); +RANDFUNC rf4 (); +RANDFUNC rf5 (); +task init_mem_random; +reg [167:0] random_num; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff),rf1.rollpli(0,32'hffffffff),rf2.rollpli(0,32'hffffffff),rf3.rollpli(0,32'hffffffff),rf4.rollpli(0,32'hffffffff),rf5.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 10080); + row = random_num / 168; + bitnum = random_num % 168; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [5:0] row; +input [167:0] bitnum; +reg [167:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168_logic.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168_logic.v new file mode 100644 index 0000000..b8002ec --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168_logic.v @@ -0,0 +1,891 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x168_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_60x168_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [167:0] dbyp; +input debug_mode; +input [167:0] di; +output [167:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [167:0] mbist_Do_r0_int_net; +input [5:0] mbist_Ra_r0; +input [5:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [5:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [7:0] svop; +input test_mode; +input updateDR; +input [5:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [5:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [167:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [167:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [167:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [167:0] pre_muxed_Di_w0; +wire [167:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[167:0]; +assign pre_muxed_Di_w0_B = {{84{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {168{`tick_x_or_0}}; + endcase +reg [167:0] muxed_Di_w0; +wire [167:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[167:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {168{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [5:0] pre_Wa_reg_w0; +reg [5:0] Wa_reg_w0; +wire [5:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {6{`tick_x_or_0}}; +endcase +reg [5:0] muxed_Wa_w0; +wire [5:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {6{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [5:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [5:0] pre_Ra_reg_r0; +reg [5:0] Ra_reg_r0; +wire [5:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {6{`tick_x_or_0}}; +endcase +wire [5:0] D_Ra_reg_r0; +reg [5:0] muxed_Ra_r0; +wire [5:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {6{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [5:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMPDP_60X168_GL_M1_D2 (RamCell) +// Covers Addresses from 0 to 59 Addressrange: [5:0] +// Data Bit range: [167:0] (168 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [5:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[5:0]; +// Write Data in bus +wire [167:0] Wdata; +assign Wdata = muxed_Di_w0[167:0]; +assign we_0_0 = we; +// Read Address bus +wire [5:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[5:0]; +// Read DataOut bus +wire [167:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMPDP_60X168_GL_M1_D2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = !(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [167:0] ramDataOut; +assign dout_0_0[167:0] = ramDataOut[167:0]; +RAMPDP_60X168_GL_M1_D2 ram_Inst_60X168 ( + .CLK (gated_clk_core) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_167 (Wdata[167]) + , .WD_166 (Wdata[166]) + , .WD_165 (Wdata[165]) + , .WD_164 (Wdata[164]) + , .WD_163 (Wdata[163]) + , .WD_162 (Wdata[162]) + , .WD_161 (Wdata[161]) + , .WD_160 (Wdata[160]) + , .WD_159 (Wdata[159]) + , .WD_158 (Wdata[158]) + , .WD_157 (Wdata[157]) + , .WD_156 (Wdata[156]) + , .WD_155 (Wdata[155]) + , .WD_154 (Wdata[154]) + , .WD_153 (Wdata[153]) + , .WD_152 (Wdata[152]) + , .WD_151 (Wdata[151]) + , .WD_150 (Wdata[150]) + , .WD_149 (Wdata[149]) + , .WD_148 (Wdata[148]) + , .WD_147 (Wdata[147]) + , .WD_146 (Wdata[146]) + , .WD_145 (Wdata[145]) + , .WD_144 (Wdata[144]) + , .WD_143 (Wdata[143]) + , .WD_142 (Wdata[142]) + , .WD_141 (Wdata[141]) + , .WD_140 (Wdata[140]) + , .WD_139 (Wdata[139]) + , .WD_138 (Wdata[138]) + , .WD_137 (Wdata[137]) + , .WD_136 (Wdata[136]) + , .WD_135 (Wdata[135]) + , .WD_134 (Wdata[134]) + , .WD_133 (Wdata[133]) + , .WD_132 (Wdata[132]) + , .WD_131 (Wdata[131]) + , .WD_130 (Wdata[130]) + , .WD_129 (Wdata[129]) + , .WD_128 (Wdata[128]) + , .WD_127 (Wdata[127]) + , .WD_126 (Wdata[126]) + , .WD_125 (Wdata[125]) + , .WD_124 (Wdata[124]) + , .WD_123 (Wdata[123]) + , .WD_122 (Wdata[122]) + , .WD_121 (Wdata[121]) + , .WD_120 (Wdata[120]) + , .WD_119 (Wdata[119]) + , .WD_118 (Wdata[118]) + , .WD_117 (Wdata[117]) + , .WD_116 (Wdata[116]) + , .WD_115 (Wdata[115]) + , .WD_114 (Wdata[114]) + , .WD_113 (Wdata[113]) + , .WD_112 (Wdata[112]) + , .WD_111 (Wdata[111]) + , .WD_110 (Wdata[110]) + , .WD_109 (Wdata[109]) + , .WD_108 (Wdata[108]) + , .WD_107 (Wdata[107]) + , .WD_106 (Wdata[106]) + , .WD_105 (Wdata[105]) + , .WD_104 (Wdata[104]) + , .WD_103 (Wdata[103]) + , .WD_102 (Wdata[102]) + , .WD_101 (Wdata[101]) + , .WD_100 (Wdata[100]) + , .WD_99 (Wdata[99]) + , .WD_98 (Wdata[98]) + , .WD_97 (Wdata[97]) + , .WD_96 (Wdata[96]) + , .WD_95 (Wdata[95]) + , .WD_94 (Wdata[94]) + , .WD_93 (Wdata[93]) + , .WD_92 (Wdata[92]) + , .WD_91 (Wdata[91]) + , .WD_90 (Wdata[90]) + , .WD_89 (Wdata[89]) + , .WD_88 (Wdata[88]) + , .WD_87 (Wdata[87]) + , .WD_86 (Wdata[86]) + , .WD_85 (Wdata[85]) + , .WD_84 (Wdata[84]) + , .WD_83 (Wdata[83]) + , .WD_82 (Wdata[82]) + , .WD_81 (Wdata[81]) + , .WD_80 (Wdata[80]) + , .WD_79 (Wdata[79]) + , .WD_78 (Wdata[78]) + , .WD_77 (Wdata[77]) + , .WD_76 (Wdata[76]) + , .WD_75 (Wdata[75]) + , .WD_74 (Wdata[74]) + , .WD_73 (Wdata[73]) + , .WD_72 (Wdata[72]) + , .WD_71 (Wdata[71]) + , .WD_70 (Wdata[70]) + , .WD_69 (Wdata[69]) + , .WD_68 (Wdata[68]) + , .WD_67 (Wdata[67]) + , .WD_66 (Wdata[66]) + , .WD_65 (Wdata[65]) + , .WD_64 (Wdata[64]) + , .WD_63 (Wdata[63]) + , .WD_62 (Wdata[62]) + , .WD_61 (Wdata[61]) + , .WD_60 (Wdata[60]) + , .WD_59 (Wdata[59]) + , .WD_58 (Wdata[58]) + , .WD_57 (Wdata[57]) + , .WD_56 (Wdata[56]) + , .WD_55 (Wdata[55]) + , .WD_54 (Wdata[54]) + , .WD_53 (Wdata[53]) + , .WD_52 (Wdata[52]) + , .WD_51 (Wdata[51]) + , .WD_50 (Wdata[50]) + , .WD_49 (Wdata[49]) + , .WD_48 (Wdata[48]) + , .WD_47 (Wdata[47]) + , .WD_46 (Wdata[46]) + , .WD_45 (Wdata[45]) + , .WD_44 (Wdata[44]) + , .WD_43 (Wdata[43]) + , .WD_42 (Wdata[42]) + , .WD_41 (Wdata[41]) + , .WD_40 (Wdata[40]) + , .WD_39 (Wdata[39]) + , .WD_38 (Wdata[38]) + , .WD_37 (Wdata[37]) + , .WD_36 (Wdata[36]) + , .WD_35 (Wdata[35]) + , .WD_34 (Wdata[34]) + , .WD_33 (Wdata[33]) + , .WD_32 (Wdata[32]) + , .WD_31 (Wdata[31]) + , .WD_30 (Wdata[30]) + , .WD_29 (Wdata[29]) + , .WD_28 (Wdata[28]) + , .WD_27 (Wdata[27]) + , .WD_26 (Wdata[26]) + , .WD_25 (Wdata[25]) + , .WD_24 (Wdata[24]) + , .WD_23 (Wdata[23]) + , .WD_22 (Wdata[22]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .RADR_5 (ra_0_0 [5] & !test_mode) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_167 (ramDataOut[167]) + , .RD_166 (ramDataOut[166]) + , .RD_165 (ramDataOut[165]) + , .RD_164 (ramDataOut[164]) + , .RD_163 (ramDataOut[163]) + , .RD_162 (ramDataOut[162]) + , .RD_161 (ramDataOut[161]) + , .RD_160 (ramDataOut[160]) + , .RD_159 (ramDataOut[159]) + , .RD_158 (ramDataOut[158]) + , .RD_157 (ramDataOut[157]) + , .RD_156 (ramDataOut[156]) + , .RD_155 (ramDataOut[155]) + , .RD_154 (ramDataOut[154]) + , .RD_153 (ramDataOut[153]) + , .RD_152 (ramDataOut[152]) + , .RD_151 (ramDataOut[151]) + , .RD_150 (ramDataOut[150]) + , .RD_149 (ramDataOut[149]) + , .RD_148 (ramDataOut[148]) + , .RD_147 (ramDataOut[147]) + , .RD_146 (ramDataOut[146]) + , .RD_145 (ramDataOut[145]) + , .RD_144 (ramDataOut[144]) + , .RD_143 (ramDataOut[143]) + , .RD_142 (ramDataOut[142]) + , .RD_141 (ramDataOut[141]) + , .RD_140 (ramDataOut[140]) + , .RD_139 (ramDataOut[139]) + , .RD_138 (ramDataOut[138]) + , .RD_137 (ramDataOut[137]) + , .RD_136 (ramDataOut[136]) + , .RD_135 (ramDataOut[135]) + , .RD_134 (ramDataOut[134]) + , .RD_133 (ramDataOut[133]) + , .RD_132 (ramDataOut[132]) + , .RD_131 (ramDataOut[131]) + , .RD_130 (ramDataOut[130]) + , .RD_129 (ramDataOut[129]) + , .RD_128 (ramDataOut[128]) + , .RD_127 (ramDataOut[127]) + , .RD_126 (ramDataOut[126]) + , .RD_125 (ramDataOut[125]) + , .RD_124 (ramDataOut[124]) + , .RD_123 (ramDataOut[123]) + , .RD_122 (ramDataOut[122]) + , .RD_121 (ramDataOut[121]) + , .RD_120 (ramDataOut[120]) + , .RD_119 (ramDataOut[119]) + , .RD_118 (ramDataOut[118]) + , .RD_117 (ramDataOut[117]) + , .RD_116 (ramDataOut[116]) + , .RD_115 (ramDataOut[115]) + , .RD_114 (ramDataOut[114]) + , .RD_113 (ramDataOut[113]) + , .RD_112 (ramDataOut[112]) + , .RD_111 (ramDataOut[111]) + , .RD_110 (ramDataOut[110]) + , .RD_109 (ramDataOut[109]) + , .RD_108 (ramDataOut[108]) + , .RD_107 (ramDataOut[107]) + , .RD_106 (ramDataOut[106]) + , .RD_105 (ramDataOut[105]) + , .RD_104 (ramDataOut[104]) + , .RD_103 (ramDataOut[103]) + , .RD_102 (ramDataOut[102]) + , .RD_101 (ramDataOut[101]) + , .RD_100 (ramDataOut[100]) + , .RD_99 (ramDataOut[99]) + , .RD_98 (ramDataOut[98]) + , .RD_97 (ramDataOut[97]) + , .RD_96 (ramDataOut[96]) + , .RD_95 (ramDataOut[95]) + , .RD_94 (ramDataOut[94]) + , .RD_93 (ramDataOut[93]) + , .RD_92 (ramDataOut[92]) + , .RD_91 (ramDataOut[91]) + , .RD_90 (ramDataOut[90]) + , .RD_89 (ramDataOut[89]) + , .RD_88 (ramDataOut[88]) + , .RD_87 (ramDataOut[87]) + , .RD_86 (ramDataOut[86]) + , .RD_85 (ramDataOut[85]) + , .RD_84 (ramDataOut[84]) + , .RD_83 (ramDataOut[83]) + , .RD_82 (ramDataOut[82]) + , .RD_81 (ramDataOut[81]) + , .RD_80 (ramDataOut[80]) + , .RD_79 (ramDataOut[79]) + , .RD_78 (ramDataOut[78]) + , .RD_77 (ramDataOut[77]) + , .RD_76 (ramDataOut[76]) + , .RD_75 (ramDataOut[75]) + , .RD_74 (ramDataOut[74]) + , .RD_73 (ramDataOut[73]) + , .RD_72 (ramDataOut[72]) + , .RD_71 (ramDataOut[71]) + , .RD_70 (ramDataOut[70]) + , .RD_69 (ramDataOut[69]) + , .RD_68 (ramDataOut[68]) + , .RD_67 (ramDataOut[67]) + , .RD_66 (ramDataOut[66]) + , .RD_65 (ramDataOut[65]) + , .RD_64 (ramDataOut[64]) + , .RD_63 (ramDataOut[63]) + , .RD_62 (ramDataOut[62]) + , .RD_61 (ramDataOut[61]) + , .RD_60 (ramDataOut[60]) + , .RD_59 (ramDataOut[59]) + , .RD_58 (ramDataOut[58]) + , .RD_57 (ramDataOut[57]) + , .RD_56 (ramDataOut[56]) + , .RD_55 (ramDataOut[55]) + , .RD_54 (ramDataOut[54]) + , .RD_53 (ramDataOut[53]) + , .RD_52 (ramDataOut[52]) + , .RD_51 (ramDataOut[51]) + , .RD_50 (ramDataOut[50]) + , .RD_49 (ramDataOut[49]) + , .RD_48 (ramDataOut[48]) + , .RD_47 (ramDataOut[47]) + , .RD_46 (ramDataOut[46]) + , .RD_45 (ramDataOut[45]) + , .RD_44 (ramDataOut[44]) + , .RD_43 (ramDataOut[43]) + , .RD_42 (ramDataOut[42]) + , .RD_41 (ramDataOut[41]) + , .RD_40 (ramDataOut[40]) + , .RD_39 (ramDataOut[39]) + , .RD_38 (ramDataOut[38]) + , .RD_37 (ramDataOut[37]) + , .RD_36 (ramDataOut[36]) + , .RD_35 (ramDataOut[35]) + , .RD_34 (ramDataOut[34]) + , .RD_33 (ramDataOut[33]) + , .RD_32 (ramDataOut[32]) + , .RD_31 (ramDataOut[31]) + , .RD_30 (ramDataOut[30]) + , .RD_29 (ramDataOut[29]) + , .RD_28 (ramDataOut[28]) + , .RD_27 (ramDataOut[27]) + , .RD_26 (ramDataOut[26]) + , .RD_25 (ramDataOut[25]) + , .RD_24 (ramDataOut[24]) + , .RD_23 (ramDataOut[23]) + , .RD_22 (ramDataOut[22]) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .SVOP_2 (svop[2]) + , .SVOP_3 (svop[3]) + , .SVOP_4 (svop[4]) + , .SVOP_5 (svop[5]) + , .SVOP_6 (svop[6]) + , .SVOP_7 (svop[7]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [167:0] ram_r0_OutputMuxDataOut; +//For bitEnd 167, only one piece RAMPDP_60X168_GL_M1_D2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[167:0] or muxed_Di_w0[167:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[167:0] = (ram_bypass) ? muxed_Di_w0[167:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[167:0] = ram_r0_OutputMuxDataOut[167:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [167:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [167:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 167 LSB 0 and total rambit is 168 and dsize is 168 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [167:0]data_regq; +assign Data_reg_r0[167:0] = data_regq[167:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[168-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(168, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[167:0]), .Q(data_regq[167:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168_logic.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168_logic.v.vcp new file mode 100644 index 0000000..b8002ec --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x168_logic.v.vcp @@ -0,0 +1,891 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x168_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_60x168_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [167:0] dbyp; +input debug_mode; +input [167:0] di; +output [167:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [167:0] mbist_Do_r0_int_net; +input [5:0] mbist_Ra_r0; +input [5:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [5:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [7:0] svop; +input test_mode; +input updateDR; +input [5:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [5:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [167:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [167:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [167:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [167:0] pre_muxed_Di_w0; +wire [167:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[167:0]; +assign pre_muxed_Di_w0_B = {{84{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {168{`tick_x_or_0}}; + endcase +reg [167:0] muxed_Di_w0; +wire [167:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[167:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {168{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [5:0] pre_Wa_reg_w0; +reg [5:0] Wa_reg_w0; +wire [5:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {6{`tick_x_or_0}}; +endcase +reg [5:0] muxed_Wa_w0; +wire [5:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {6{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [5:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [5:0] pre_Ra_reg_r0; +reg [5:0] Ra_reg_r0; +wire [5:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {6{`tick_x_or_0}}; +endcase +wire [5:0] D_Ra_reg_r0; +reg [5:0] muxed_Ra_r0; +wire [5:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {6{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [5:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMPDP_60X168_GL_M1_D2 (RamCell) +// Covers Addresses from 0 to 59 Addressrange: [5:0] +// Data Bit range: [167:0] (168 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [5:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[5:0]; +// Write Data in bus +wire [167:0] Wdata; +assign Wdata = muxed_Di_w0[167:0]; +assign we_0_0 = we; +// Read Address bus +wire [5:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[5:0]; +// Read DataOut bus +wire [167:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMPDP_60X168_GL_M1_D2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = !(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [167:0] ramDataOut; +assign dout_0_0[167:0] = ramDataOut[167:0]; +RAMPDP_60X168_GL_M1_D2 ram_Inst_60X168 ( + .CLK (gated_clk_core) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_167 (Wdata[167]) + , .WD_166 (Wdata[166]) + , .WD_165 (Wdata[165]) + , .WD_164 (Wdata[164]) + , .WD_163 (Wdata[163]) + , .WD_162 (Wdata[162]) + , .WD_161 (Wdata[161]) + , .WD_160 (Wdata[160]) + , .WD_159 (Wdata[159]) + , .WD_158 (Wdata[158]) + , .WD_157 (Wdata[157]) + , .WD_156 (Wdata[156]) + , .WD_155 (Wdata[155]) + , .WD_154 (Wdata[154]) + , .WD_153 (Wdata[153]) + , .WD_152 (Wdata[152]) + , .WD_151 (Wdata[151]) + , .WD_150 (Wdata[150]) + , .WD_149 (Wdata[149]) + , .WD_148 (Wdata[148]) + , .WD_147 (Wdata[147]) + , .WD_146 (Wdata[146]) + , .WD_145 (Wdata[145]) + , .WD_144 (Wdata[144]) + , .WD_143 (Wdata[143]) + , .WD_142 (Wdata[142]) + , .WD_141 (Wdata[141]) + , .WD_140 (Wdata[140]) + , .WD_139 (Wdata[139]) + , .WD_138 (Wdata[138]) + , .WD_137 (Wdata[137]) + , .WD_136 (Wdata[136]) + , .WD_135 (Wdata[135]) + , .WD_134 (Wdata[134]) + , .WD_133 (Wdata[133]) + , .WD_132 (Wdata[132]) + , .WD_131 (Wdata[131]) + , .WD_130 (Wdata[130]) + , .WD_129 (Wdata[129]) + , .WD_128 (Wdata[128]) + , .WD_127 (Wdata[127]) + , .WD_126 (Wdata[126]) + , .WD_125 (Wdata[125]) + , .WD_124 (Wdata[124]) + , .WD_123 (Wdata[123]) + , .WD_122 (Wdata[122]) + , .WD_121 (Wdata[121]) + , .WD_120 (Wdata[120]) + , .WD_119 (Wdata[119]) + , .WD_118 (Wdata[118]) + , .WD_117 (Wdata[117]) + , .WD_116 (Wdata[116]) + , .WD_115 (Wdata[115]) + , .WD_114 (Wdata[114]) + , .WD_113 (Wdata[113]) + , .WD_112 (Wdata[112]) + , .WD_111 (Wdata[111]) + , .WD_110 (Wdata[110]) + , .WD_109 (Wdata[109]) + , .WD_108 (Wdata[108]) + , .WD_107 (Wdata[107]) + , .WD_106 (Wdata[106]) + , .WD_105 (Wdata[105]) + , .WD_104 (Wdata[104]) + , .WD_103 (Wdata[103]) + , .WD_102 (Wdata[102]) + , .WD_101 (Wdata[101]) + , .WD_100 (Wdata[100]) + , .WD_99 (Wdata[99]) + , .WD_98 (Wdata[98]) + , .WD_97 (Wdata[97]) + , .WD_96 (Wdata[96]) + , .WD_95 (Wdata[95]) + , .WD_94 (Wdata[94]) + , .WD_93 (Wdata[93]) + , .WD_92 (Wdata[92]) + , .WD_91 (Wdata[91]) + , .WD_90 (Wdata[90]) + , .WD_89 (Wdata[89]) + , .WD_88 (Wdata[88]) + , .WD_87 (Wdata[87]) + , .WD_86 (Wdata[86]) + , .WD_85 (Wdata[85]) + , .WD_84 (Wdata[84]) + , .WD_83 (Wdata[83]) + , .WD_82 (Wdata[82]) + , .WD_81 (Wdata[81]) + , .WD_80 (Wdata[80]) + , .WD_79 (Wdata[79]) + , .WD_78 (Wdata[78]) + , .WD_77 (Wdata[77]) + , .WD_76 (Wdata[76]) + , .WD_75 (Wdata[75]) + , .WD_74 (Wdata[74]) + , .WD_73 (Wdata[73]) + , .WD_72 (Wdata[72]) + , .WD_71 (Wdata[71]) + , .WD_70 (Wdata[70]) + , .WD_69 (Wdata[69]) + , .WD_68 (Wdata[68]) + , .WD_67 (Wdata[67]) + , .WD_66 (Wdata[66]) + , .WD_65 (Wdata[65]) + , .WD_64 (Wdata[64]) + , .WD_63 (Wdata[63]) + , .WD_62 (Wdata[62]) + , .WD_61 (Wdata[61]) + , .WD_60 (Wdata[60]) + , .WD_59 (Wdata[59]) + , .WD_58 (Wdata[58]) + , .WD_57 (Wdata[57]) + , .WD_56 (Wdata[56]) + , .WD_55 (Wdata[55]) + , .WD_54 (Wdata[54]) + , .WD_53 (Wdata[53]) + , .WD_52 (Wdata[52]) + , .WD_51 (Wdata[51]) + , .WD_50 (Wdata[50]) + , .WD_49 (Wdata[49]) + , .WD_48 (Wdata[48]) + , .WD_47 (Wdata[47]) + , .WD_46 (Wdata[46]) + , .WD_45 (Wdata[45]) + , .WD_44 (Wdata[44]) + , .WD_43 (Wdata[43]) + , .WD_42 (Wdata[42]) + , .WD_41 (Wdata[41]) + , .WD_40 (Wdata[40]) + , .WD_39 (Wdata[39]) + , .WD_38 (Wdata[38]) + , .WD_37 (Wdata[37]) + , .WD_36 (Wdata[36]) + , .WD_35 (Wdata[35]) + , .WD_34 (Wdata[34]) + , .WD_33 (Wdata[33]) + , .WD_32 (Wdata[32]) + , .WD_31 (Wdata[31]) + , .WD_30 (Wdata[30]) + , .WD_29 (Wdata[29]) + , .WD_28 (Wdata[28]) + , .WD_27 (Wdata[27]) + , .WD_26 (Wdata[26]) + , .WD_25 (Wdata[25]) + , .WD_24 (Wdata[24]) + , .WD_23 (Wdata[23]) + , .WD_22 (Wdata[22]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .RADR_5 (ra_0_0 [5] & !test_mode) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_167 (ramDataOut[167]) + , .RD_166 (ramDataOut[166]) + , .RD_165 (ramDataOut[165]) + , .RD_164 (ramDataOut[164]) + , .RD_163 (ramDataOut[163]) + , .RD_162 (ramDataOut[162]) + , .RD_161 (ramDataOut[161]) + , .RD_160 (ramDataOut[160]) + , .RD_159 (ramDataOut[159]) + , .RD_158 (ramDataOut[158]) + , .RD_157 (ramDataOut[157]) + , .RD_156 (ramDataOut[156]) + , .RD_155 (ramDataOut[155]) + , .RD_154 (ramDataOut[154]) + , .RD_153 (ramDataOut[153]) + , .RD_152 (ramDataOut[152]) + , .RD_151 (ramDataOut[151]) + , .RD_150 (ramDataOut[150]) + , .RD_149 (ramDataOut[149]) + , .RD_148 (ramDataOut[148]) + , .RD_147 (ramDataOut[147]) + , .RD_146 (ramDataOut[146]) + , .RD_145 (ramDataOut[145]) + , .RD_144 (ramDataOut[144]) + , .RD_143 (ramDataOut[143]) + , .RD_142 (ramDataOut[142]) + , .RD_141 (ramDataOut[141]) + , .RD_140 (ramDataOut[140]) + , .RD_139 (ramDataOut[139]) + , .RD_138 (ramDataOut[138]) + , .RD_137 (ramDataOut[137]) + , .RD_136 (ramDataOut[136]) + , .RD_135 (ramDataOut[135]) + , .RD_134 (ramDataOut[134]) + , .RD_133 (ramDataOut[133]) + , .RD_132 (ramDataOut[132]) + , .RD_131 (ramDataOut[131]) + , .RD_130 (ramDataOut[130]) + , .RD_129 (ramDataOut[129]) + , .RD_128 (ramDataOut[128]) + , .RD_127 (ramDataOut[127]) + , .RD_126 (ramDataOut[126]) + , .RD_125 (ramDataOut[125]) + , .RD_124 (ramDataOut[124]) + , .RD_123 (ramDataOut[123]) + , .RD_122 (ramDataOut[122]) + , .RD_121 (ramDataOut[121]) + , .RD_120 (ramDataOut[120]) + , .RD_119 (ramDataOut[119]) + , .RD_118 (ramDataOut[118]) + , .RD_117 (ramDataOut[117]) + , .RD_116 (ramDataOut[116]) + , .RD_115 (ramDataOut[115]) + , .RD_114 (ramDataOut[114]) + , .RD_113 (ramDataOut[113]) + , .RD_112 (ramDataOut[112]) + , .RD_111 (ramDataOut[111]) + , .RD_110 (ramDataOut[110]) + , .RD_109 (ramDataOut[109]) + , .RD_108 (ramDataOut[108]) + , .RD_107 (ramDataOut[107]) + , .RD_106 (ramDataOut[106]) + , .RD_105 (ramDataOut[105]) + , .RD_104 (ramDataOut[104]) + , .RD_103 (ramDataOut[103]) + , .RD_102 (ramDataOut[102]) + , .RD_101 (ramDataOut[101]) + , .RD_100 (ramDataOut[100]) + , .RD_99 (ramDataOut[99]) + , .RD_98 (ramDataOut[98]) + , .RD_97 (ramDataOut[97]) + , .RD_96 (ramDataOut[96]) + , .RD_95 (ramDataOut[95]) + , .RD_94 (ramDataOut[94]) + , .RD_93 (ramDataOut[93]) + , .RD_92 (ramDataOut[92]) + , .RD_91 (ramDataOut[91]) + , .RD_90 (ramDataOut[90]) + , .RD_89 (ramDataOut[89]) + , .RD_88 (ramDataOut[88]) + , .RD_87 (ramDataOut[87]) + , .RD_86 (ramDataOut[86]) + , .RD_85 (ramDataOut[85]) + , .RD_84 (ramDataOut[84]) + , .RD_83 (ramDataOut[83]) + , .RD_82 (ramDataOut[82]) + , .RD_81 (ramDataOut[81]) + , .RD_80 (ramDataOut[80]) + , .RD_79 (ramDataOut[79]) + , .RD_78 (ramDataOut[78]) + , .RD_77 (ramDataOut[77]) + , .RD_76 (ramDataOut[76]) + , .RD_75 (ramDataOut[75]) + , .RD_74 (ramDataOut[74]) + , .RD_73 (ramDataOut[73]) + , .RD_72 (ramDataOut[72]) + , .RD_71 (ramDataOut[71]) + , .RD_70 (ramDataOut[70]) + , .RD_69 (ramDataOut[69]) + , .RD_68 (ramDataOut[68]) + , .RD_67 (ramDataOut[67]) + , .RD_66 (ramDataOut[66]) + , .RD_65 (ramDataOut[65]) + , .RD_64 (ramDataOut[64]) + , .RD_63 (ramDataOut[63]) + , .RD_62 (ramDataOut[62]) + , .RD_61 (ramDataOut[61]) + , .RD_60 (ramDataOut[60]) + , .RD_59 (ramDataOut[59]) + , .RD_58 (ramDataOut[58]) + , .RD_57 (ramDataOut[57]) + , .RD_56 (ramDataOut[56]) + , .RD_55 (ramDataOut[55]) + , .RD_54 (ramDataOut[54]) + , .RD_53 (ramDataOut[53]) + , .RD_52 (ramDataOut[52]) + , .RD_51 (ramDataOut[51]) + , .RD_50 (ramDataOut[50]) + , .RD_49 (ramDataOut[49]) + , .RD_48 (ramDataOut[48]) + , .RD_47 (ramDataOut[47]) + , .RD_46 (ramDataOut[46]) + , .RD_45 (ramDataOut[45]) + , .RD_44 (ramDataOut[44]) + , .RD_43 (ramDataOut[43]) + , .RD_42 (ramDataOut[42]) + , .RD_41 (ramDataOut[41]) + , .RD_40 (ramDataOut[40]) + , .RD_39 (ramDataOut[39]) + , .RD_38 (ramDataOut[38]) + , .RD_37 (ramDataOut[37]) + , .RD_36 (ramDataOut[36]) + , .RD_35 (ramDataOut[35]) + , .RD_34 (ramDataOut[34]) + , .RD_33 (ramDataOut[33]) + , .RD_32 (ramDataOut[32]) + , .RD_31 (ramDataOut[31]) + , .RD_30 (ramDataOut[30]) + , .RD_29 (ramDataOut[29]) + , .RD_28 (ramDataOut[28]) + , .RD_27 (ramDataOut[27]) + , .RD_26 (ramDataOut[26]) + , .RD_25 (ramDataOut[25]) + , .RD_24 (ramDataOut[24]) + , .RD_23 (ramDataOut[23]) + , .RD_22 (ramDataOut[22]) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .SVOP_2 (svop[2]) + , .SVOP_3 (svop[3]) + , .SVOP_4 (svop[4]) + , .SVOP_5 (svop[5]) + , .SVOP_6 (svop[6]) + , .SVOP_7 (svop[7]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [167:0] ram_r0_OutputMuxDataOut; +//For bitEnd 167, only one piece RAMPDP_60X168_GL_M1_D2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[167:0] or muxed_Di_w0[167:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[167:0] = (ram_bypass) ? muxed_Di_w0[167:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[167:0] = ram_r0_OutputMuxDataOut[167:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [167:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [167:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 167 LSB 0 and total rambit is 168 and dsize is 168 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [167:0]data_regq; +assign Data_reg_r0[167:0] = data_regq[167:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[168-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(168, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[167:0]), .Q(data_regq[167:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21.v new file mode 100644 index 0000000..79926be --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21.v @@ -0,0 +1,512 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x21.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_60x21 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [20:0] dout; +input [5:0] wa; +input we; +input [20:0] di; +input byp_sel; +input [20:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_60X22_GL_M1_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [5:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [5:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [21:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_60x21_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_60x21 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[20:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [59:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [20:0] shadow_mem [59:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [20:0] shadow_mem_row0 = shadow_mem[0]; +wire [20:0] shadow_mem_row1 = shadow_mem[1]; +wire [20:0] shadow_mem_row2 = shadow_mem[2]; +wire [20:0] shadow_mem_row3 = shadow_mem[3]; +wire [20:0] shadow_mem_row4 = shadow_mem[4]; +wire [20:0] shadow_mem_row5 = shadow_mem[5]; +wire [20:0] shadow_mem_row6 = shadow_mem[6]; +wire [20:0] shadow_mem_row7 = shadow_mem[7]; +wire [20:0] shadow_mem_row8 = shadow_mem[8]; +wire [20:0] shadow_mem_row9 = shadow_mem[9]; +wire [20:0] shadow_mem_row10 = shadow_mem[10]; +wire [20:0] shadow_mem_row11 = shadow_mem[11]; +wire [20:0] shadow_mem_row12 = shadow_mem[12]; +wire [20:0] shadow_mem_row13 = shadow_mem[13]; +wire [20:0] shadow_mem_row14 = shadow_mem[14]; +wire [20:0] shadow_mem_row15 = shadow_mem[15]; +wire [20:0] shadow_mem_row16 = shadow_mem[16]; +wire [20:0] shadow_mem_row17 = shadow_mem[17]; +wire [20:0] shadow_mem_row18 = shadow_mem[18]; +wire [20:0] shadow_mem_row19 = shadow_mem[19]; +wire [20:0] shadow_mem_row20 = shadow_mem[20]; +wire [20:0] shadow_mem_row21 = shadow_mem[21]; +wire [20:0] shadow_mem_row22 = shadow_mem[22]; +wire [20:0] shadow_mem_row23 = shadow_mem[23]; +wire [20:0] shadow_mem_row24 = shadow_mem[24]; +wire [20:0] shadow_mem_row25 = shadow_mem[25]; +wire [20:0] shadow_mem_row26 = shadow_mem[26]; +wire [20:0] shadow_mem_row27 = shadow_mem[27]; +wire [20:0] shadow_mem_row28 = shadow_mem[28]; +wire [20:0] shadow_mem_row29 = shadow_mem[29]; +wire [20:0] shadow_mem_row30 = shadow_mem[30]; +wire [20:0] shadow_mem_row31 = shadow_mem[31]; +wire [20:0] shadow_mem_row32 = shadow_mem[32]; +wire [20:0] shadow_mem_row33 = shadow_mem[33]; +wire [20:0] shadow_mem_row34 = shadow_mem[34]; +wire [20:0] shadow_mem_row35 = shadow_mem[35]; +wire [20:0] shadow_mem_row36 = shadow_mem[36]; +wire [20:0] shadow_mem_row37 = shadow_mem[37]; +wire [20:0] shadow_mem_row38 = shadow_mem[38]; +wire [20:0] shadow_mem_row39 = shadow_mem[39]; +wire [20:0] shadow_mem_row40 = shadow_mem[40]; +wire [20:0] shadow_mem_row41 = shadow_mem[41]; +wire [20:0] shadow_mem_row42 = shadow_mem[42]; +wire [20:0] shadow_mem_row43 = shadow_mem[43]; +wire [20:0] shadow_mem_row44 = shadow_mem[44]; +wire [20:0] shadow_mem_row45 = shadow_mem[45]; +wire [20:0] shadow_mem_row46 = shadow_mem[46]; +wire [20:0] shadow_mem_row47 = shadow_mem[47]; +wire [20:0] shadow_mem_row48 = shadow_mem[48]; +wire [20:0] shadow_mem_row49 = shadow_mem[49]; +wire [20:0] shadow_mem_row50 = shadow_mem[50]; +wire [20:0] shadow_mem_row51 = shadow_mem[51]; +wire [20:0] shadow_mem_row52 = shadow_mem[52]; +wire [20:0] shadow_mem_row53 = shadow_mem[53]; +wire [20:0] shadow_mem_row54 = shadow_mem[54]; +wire [20:0] shadow_mem_row55 = shadow_mem[55]; +wire [20:0] shadow_mem_row56 = shadow_mem[56]; +wire [20:0] shadow_mem_row57 = shadow_mem[57]; +wire [20:0] shadow_mem_row58 = shadow_mem[58]; +wire [20:0] shadow_mem_row59 = shadow_mem[59]; +`endif +task init_mem_val; + input [5:0] row; + input [20:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_60X22_GL_M1_E2 +for (row = 0; row < 60; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_60x21.ram_Inst_60X22.mem_write(row - 0, shadow_mem[row][20:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [5:0] wa; + input we; + input [20:0] di; + reg [20:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [20:0] probe_mem_val; +input [5:0] row; +reg [20:0] data; +begin +// probing RAMDP_60X22_GL_M1_E2 + if (row >= 0 && row < 60) data[20:0] = r_nv_ram_rwsthp_60x21.ram_Inst_60X22.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 60; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [20:0] random_num; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 1260); + row = random_num / 21; + bitnum = random_num % 21; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [5:0] row; +input [20:0] bitnum; +reg [20:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21.v.vcp new file mode 100644 index 0000000..79926be --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21.v.vcp @@ -0,0 +1,512 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x21.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_60x21 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [5:0] ra; +input re; +input ore; +output [20:0] dout; +input [5:0] wa; +input we; +input [20:0] di; +input byp_sel; +input [20:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_60X22_GL_M1_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [5:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [5:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [21:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_60x21_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_60x21 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[20:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [59:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [20:0] shadow_mem [59:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [20:0] shadow_mem_row0 = shadow_mem[0]; +wire [20:0] shadow_mem_row1 = shadow_mem[1]; +wire [20:0] shadow_mem_row2 = shadow_mem[2]; +wire [20:0] shadow_mem_row3 = shadow_mem[3]; +wire [20:0] shadow_mem_row4 = shadow_mem[4]; +wire [20:0] shadow_mem_row5 = shadow_mem[5]; +wire [20:0] shadow_mem_row6 = shadow_mem[6]; +wire [20:0] shadow_mem_row7 = shadow_mem[7]; +wire [20:0] shadow_mem_row8 = shadow_mem[8]; +wire [20:0] shadow_mem_row9 = shadow_mem[9]; +wire [20:0] shadow_mem_row10 = shadow_mem[10]; +wire [20:0] shadow_mem_row11 = shadow_mem[11]; +wire [20:0] shadow_mem_row12 = shadow_mem[12]; +wire [20:0] shadow_mem_row13 = shadow_mem[13]; +wire [20:0] shadow_mem_row14 = shadow_mem[14]; +wire [20:0] shadow_mem_row15 = shadow_mem[15]; +wire [20:0] shadow_mem_row16 = shadow_mem[16]; +wire [20:0] shadow_mem_row17 = shadow_mem[17]; +wire [20:0] shadow_mem_row18 = shadow_mem[18]; +wire [20:0] shadow_mem_row19 = shadow_mem[19]; +wire [20:0] shadow_mem_row20 = shadow_mem[20]; +wire [20:0] shadow_mem_row21 = shadow_mem[21]; +wire [20:0] shadow_mem_row22 = shadow_mem[22]; +wire [20:0] shadow_mem_row23 = shadow_mem[23]; +wire [20:0] shadow_mem_row24 = shadow_mem[24]; +wire [20:0] shadow_mem_row25 = shadow_mem[25]; +wire [20:0] shadow_mem_row26 = shadow_mem[26]; +wire [20:0] shadow_mem_row27 = shadow_mem[27]; +wire [20:0] shadow_mem_row28 = shadow_mem[28]; +wire [20:0] shadow_mem_row29 = shadow_mem[29]; +wire [20:0] shadow_mem_row30 = shadow_mem[30]; +wire [20:0] shadow_mem_row31 = shadow_mem[31]; +wire [20:0] shadow_mem_row32 = shadow_mem[32]; +wire [20:0] shadow_mem_row33 = shadow_mem[33]; +wire [20:0] shadow_mem_row34 = shadow_mem[34]; +wire [20:0] shadow_mem_row35 = shadow_mem[35]; +wire [20:0] shadow_mem_row36 = shadow_mem[36]; +wire [20:0] shadow_mem_row37 = shadow_mem[37]; +wire [20:0] shadow_mem_row38 = shadow_mem[38]; +wire [20:0] shadow_mem_row39 = shadow_mem[39]; +wire [20:0] shadow_mem_row40 = shadow_mem[40]; +wire [20:0] shadow_mem_row41 = shadow_mem[41]; +wire [20:0] shadow_mem_row42 = shadow_mem[42]; +wire [20:0] shadow_mem_row43 = shadow_mem[43]; +wire [20:0] shadow_mem_row44 = shadow_mem[44]; +wire [20:0] shadow_mem_row45 = shadow_mem[45]; +wire [20:0] shadow_mem_row46 = shadow_mem[46]; +wire [20:0] shadow_mem_row47 = shadow_mem[47]; +wire [20:0] shadow_mem_row48 = shadow_mem[48]; +wire [20:0] shadow_mem_row49 = shadow_mem[49]; +wire [20:0] shadow_mem_row50 = shadow_mem[50]; +wire [20:0] shadow_mem_row51 = shadow_mem[51]; +wire [20:0] shadow_mem_row52 = shadow_mem[52]; +wire [20:0] shadow_mem_row53 = shadow_mem[53]; +wire [20:0] shadow_mem_row54 = shadow_mem[54]; +wire [20:0] shadow_mem_row55 = shadow_mem[55]; +wire [20:0] shadow_mem_row56 = shadow_mem[56]; +wire [20:0] shadow_mem_row57 = shadow_mem[57]; +wire [20:0] shadow_mem_row58 = shadow_mem[58]; +wire [20:0] shadow_mem_row59 = shadow_mem[59]; +`endif +task init_mem_val; + input [5:0] row; + input [20:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_60X22_GL_M1_E2 +for (row = 0; row < 60; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_60x21.ram_Inst_60X22.mem_write(row - 0, shadow_mem[row][20:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [5:0] wa; + input we; + input [20:0] di; + reg [20:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [20:0] probe_mem_val; +input [5:0] row; +reg [20:0] data; +begin +// probing RAMDP_60X22_GL_M1_E2 + if (row >= 0 && row < 60) data[20:0] = r_nv_ram_rwsthp_60x21.ram_Inst_60X22.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 60; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [20:0] random_num; +integer i; +begin + for (i = 0; i < 60; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 1260); + row = random_num / 21; + bitnum = random_num % 21; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [5:0] row; +input [20:0] bitnum; +reg [20:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21_logic.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21_logic.v new file mode 100644 index 0000000..71e4711 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21_logic.v @@ -0,0 +1,598 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x21_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_60x21_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [20:0] dbyp; +input debug_mode; +input [20:0] di; +output [20:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [21:0] mbist_Do_r0_int_net; +input [5:0] mbist_Ra_r0; +input [5:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [5:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [5:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [5:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [21:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [21:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [20:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [21:0] pre_muxed_Di_w0; +wire [21:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[21:0]; +assign pre_muxed_Di_w0_B = {{11{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {22{`tick_x_or_0}}; + endcase +reg [21:0] muxed_Di_w0; +wire [21:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {{1{1'b0}},di[20:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {22{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [5:0] pre_Wa_reg_w0; +reg [5:0] Wa_reg_w0; +wire [5:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {6{`tick_x_or_0}}; +endcase +reg [5:0] muxed_Wa_w0; +wire [5:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {6{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [5:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [5:0] pre_Ra_reg_r0; +reg [5:0] Ra_reg_r0; +wire [5:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {6{`tick_x_or_0}}; +endcase +wire [5:0] D_Ra_reg_r0; +reg [5:0] muxed_Ra_r0; +wire [5:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {6{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [5:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_60X22_GL_M1_E2 (RamCell) +// Covers Addresses from 0 to 59 Addressrange: [5:0] +// Data Bit range: [20:0] (22 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [5:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[5:0]; +// Write Data in bus +wire [21:0] Wdata; +assign Wdata = muxed_Di_w0[21:0]; +assign we_0_0 = we; +// Read Address bus +wire [5:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[5:0]; +// Read DataOut bus +wire [21:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_60X22_GL_M1_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [21:0] ramDataOut; +assign dout_0_0[21:0] = ramDataOut[21:0]; +// verilint 210 off - Too few module ports +// verilint 287 off - Unconnected port +RAMDP_60X22_GL_M1_E2 ram_Inst_60X22 ( + .CLK_W (gated_clk_core) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_5 (ra_0_0 [5] & !test_mode) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +// verilint 210 on - Too few module ports +// verilint 287 on - Unconnected port +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [21:0] ram_r0_OutputMuxDataOut; +//For bitEnd 20, only one piece RAMDP_60X22_GL_M1_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[21:0] or muxed_Di_w0[21:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[21:0] = (ram_bypass) ? muxed_Di_w0[21:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[21:0] = ram_r0_OutputMuxDataOut[21:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [21:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? {{1{1'b0}},dbyp} : {{1{1'b0}},wthru_di}; +wire [21:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 21 LSB 0 and total rambit is 22 and dsize is 22 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [21:0]data_regq; +assign Data_reg_r0[21:0] = data_regq[21:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0[20:0]; +assign mbist_Do_r0_int_net = Data_reg_r0[22-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(22, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[21:0]), .Q(data_regq[21:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21_logic.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21_logic.v.vcp new file mode 100644 index 0000000..71e4711 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_60x21_logic.v.vcp @@ -0,0 +1,598 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_60x21_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_60x21_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [20:0] dbyp; +input debug_mode; +input [20:0] di; +output [20:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [21:0] mbist_Do_r0_int_net; +input [5:0] mbist_Ra_r0; +input [5:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [5:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [5:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [5:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [21:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [21:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [20:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [21:0] pre_muxed_Di_w0; +wire [21:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[21:0]; +assign pre_muxed_Di_w0_B = {{11{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {22{`tick_x_or_0}}; + endcase +reg [21:0] muxed_Di_w0; +wire [21:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {{1{1'b0}},di[20:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {22{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [5:0] pre_Wa_reg_w0; +reg [5:0] Wa_reg_w0; +wire [5:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {6{`tick_x_or_0}}; +endcase +reg [5:0] muxed_Wa_w0; +wire [5:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {6{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [5:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [5:0] pre_Ra_reg_r0; +reg [5:0] Ra_reg_r0; +wire [5:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {6{`tick_x_or_0}}; +endcase +wire [5:0] D_Ra_reg_r0; +reg [5:0] muxed_Ra_r0; +wire [5:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {6{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [5:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_60X22_GL_M1_E2 (RamCell) +// Covers Addresses from 0 to 59 Addressrange: [5:0] +// Data Bit range: [20:0] (22 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [5:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[5:0]; +// Write Data in bus +wire [21:0] Wdata; +assign Wdata = muxed_Di_w0[21:0]; +assign we_0_0 = we; +// Read Address bus +wire [5:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[5:0]; +// Read DataOut bus +wire [21:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_60X22_GL_M1_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [21:0] ramDataOut; +assign dout_0_0[21:0] = ramDataOut[21:0]; +// verilint 210 off - Too few module ports +// verilint 287 off - Unconnected port +RAMDP_60X22_GL_M1_E2 ram_Inst_60X22 ( + .CLK_W (gated_clk_core) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_5 (ra_0_0 [5] & !test_mode) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +// verilint 210 on - Too few module ports +// verilint 287 on - Unconnected port +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [21:0] ram_r0_OutputMuxDataOut; +//For bitEnd 20, only one piece RAMDP_60X22_GL_M1_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[21:0] or muxed_Di_w0[21:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[21:0] = (ram_bypass) ? muxed_Di_w0[21:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[21:0] = ram_r0_OutputMuxDataOut[21:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [21:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? {{1{1'b0}},dbyp} : {{1{1'b0}},wthru_di}; +wire [21:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 21 LSB 0 and total rambit is 22 and dsize is 22 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [21:0]data_regq; +assign Data_reg_r0[21:0] = data_regq[21:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0[20:0]; +assign mbist_Do_r0_int_net = Data_reg_r0[22-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(6, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(22, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[21:0]), .Q(data_regq[21:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15.v new file mode 100644 index 0000000..a41c2af --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15.v @@ -0,0 +1,511 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x15.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_80x15 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [14:0] dout; +input [6:0] wa; +input we; +input [14:0] di; +input byp_sel; +input [14:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_80X15_GL_M2_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [6:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [6:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [14:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_6 (.Y(pre_mbist_Wa_w0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_6 (.Z(mbist_Wa_w0[6]), .A1(pre_mbist_Wa_w0_6), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_6 (.Y(pre_mbist_Ra_r0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_6 (.Z(mbist_Ra_r0[6]), .A1(pre_mbist_Ra_r0_6), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_80x15_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_80x15 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[14:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [79:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [14:0] shadow_mem [79:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [14:0] shadow_mem_row0 = shadow_mem[0]; +wire [14:0] shadow_mem_row1 = shadow_mem[1]; +wire [14:0] shadow_mem_row2 = shadow_mem[2]; +wire [14:0] shadow_mem_row3 = shadow_mem[3]; +wire [14:0] shadow_mem_row4 = shadow_mem[4]; +wire [14:0] shadow_mem_row5 = shadow_mem[5]; +wire [14:0] shadow_mem_row6 = shadow_mem[6]; +wire [14:0] shadow_mem_row7 = shadow_mem[7]; +wire [14:0] shadow_mem_row8 = shadow_mem[8]; +wire [14:0] shadow_mem_row9 = shadow_mem[9]; +wire [14:0] shadow_mem_row10 = shadow_mem[10]; +wire [14:0] shadow_mem_row11 = shadow_mem[11]; +wire [14:0] shadow_mem_row12 = shadow_mem[12]; +wire [14:0] shadow_mem_row13 = shadow_mem[13]; +wire [14:0] shadow_mem_row14 = shadow_mem[14]; +wire [14:0] shadow_mem_row15 = shadow_mem[15]; +wire [14:0] shadow_mem_row16 = shadow_mem[16]; +wire [14:0] shadow_mem_row17 = shadow_mem[17]; +wire [14:0] shadow_mem_row18 = shadow_mem[18]; +wire [14:0] shadow_mem_row19 = shadow_mem[19]; +wire [14:0] shadow_mem_row20 = shadow_mem[20]; +wire [14:0] shadow_mem_row21 = shadow_mem[21]; +wire [14:0] shadow_mem_row22 = shadow_mem[22]; +wire [14:0] shadow_mem_row23 = shadow_mem[23]; +wire [14:0] shadow_mem_row24 = shadow_mem[24]; +wire [14:0] shadow_mem_row25 = shadow_mem[25]; +wire [14:0] shadow_mem_row26 = shadow_mem[26]; +wire [14:0] shadow_mem_row27 = shadow_mem[27]; +wire [14:0] shadow_mem_row28 = shadow_mem[28]; +wire [14:0] shadow_mem_row29 = shadow_mem[29]; +wire [14:0] shadow_mem_row30 = shadow_mem[30]; +wire [14:0] shadow_mem_row31 = shadow_mem[31]; +wire [14:0] shadow_mem_row32 = shadow_mem[32]; +wire [14:0] shadow_mem_row33 = shadow_mem[33]; +wire [14:0] shadow_mem_row34 = shadow_mem[34]; +wire [14:0] shadow_mem_row35 = shadow_mem[35]; +wire [14:0] shadow_mem_row36 = shadow_mem[36]; +wire [14:0] shadow_mem_row37 = shadow_mem[37]; +wire [14:0] shadow_mem_row38 = shadow_mem[38]; +wire [14:0] shadow_mem_row39 = shadow_mem[39]; +wire [14:0] shadow_mem_row40 = shadow_mem[40]; +wire [14:0] shadow_mem_row41 = shadow_mem[41]; +wire [14:0] shadow_mem_row42 = shadow_mem[42]; +wire [14:0] shadow_mem_row43 = shadow_mem[43]; +wire [14:0] shadow_mem_row44 = shadow_mem[44]; +wire [14:0] shadow_mem_row45 = shadow_mem[45]; +wire [14:0] shadow_mem_row46 = shadow_mem[46]; +wire [14:0] shadow_mem_row47 = shadow_mem[47]; +wire [14:0] shadow_mem_row48 = shadow_mem[48]; +wire [14:0] shadow_mem_row49 = shadow_mem[49]; +wire [14:0] shadow_mem_row50 = shadow_mem[50]; +wire [14:0] shadow_mem_row51 = shadow_mem[51]; +wire [14:0] shadow_mem_row52 = shadow_mem[52]; +wire [14:0] shadow_mem_row53 = shadow_mem[53]; +wire [14:0] shadow_mem_row54 = shadow_mem[54]; +wire [14:0] shadow_mem_row55 = shadow_mem[55]; +wire [14:0] shadow_mem_row56 = shadow_mem[56]; +wire [14:0] shadow_mem_row57 = shadow_mem[57]; +wire [14:0] shadow_mem_row58 = shadow_mem[58]; +wire [14:0] shadow_mem_row59 = shadow_mem[59]; +wire [14:0] shadow_mem_row60 = shadow_mem[60]; +wire [14:0] shadow_mem_row61 = shadow_mem[61]; +wire [14:0] shadow_mem_row62 = shadow_mem[62]; +wire [14:0] shadow_mem_row63 = shadow_mem[63]; +wire [14:0] shadow_mem_row64 = shadow_mem[64]; +wire [14:0] shadow_mem_row65 = shadow_mem[65]; +wire [14:0] shadow_mem_row66 = shadow_mem[66]; +wire [14:0] shadow_mem_row67 = shadow_mem[67]; +wire [14:0] shadow_mem_row68 = shadow_mem[68]; +wire [14:0] shadow_mem_row69 = shadow_mem[69]; +wire [14:0] shadow_mem_row70 = shadow_mem[70]; +wire [14:0] shadow_mem_row71 = shadow_mem[71]; +wire [14:0] shadow_mem_row72 = shadow_mem[72]; +wire [14:0] shadow_mem_row73 = shadow_mem[73]; +wire [14:0] shadow_mem_row74 = shadow_mem[74]; +wire [14:0] shadow_mem_row75 = shadow_mem[75]; +wire [14:0] shadow_mem_row76 = shadow_mem[76]; +wire [14:0] shadow_mem_row77 = shadow_mem[77]; +wire [14:0] shadow_mem_row78 = shadow_mem[78]; +wire [14:0] shadow_mem_row79 = shadow_mem[79]; +`endif +task init_mem_val; + input [6:0] row; + input [14:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_80X15_GL_M2_E2 +for (row = 0; row < 80; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_80x15.ram_Inst_80X15.mem_write(row - 0, shadow_mem[row][14:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [6:0] wa; + input we; + input [14:0] di; + reg [14:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [14:0] probe_mem_val; +input [6:0] row; +reg [14:0] data; +begin +// probing RAMDP_80X15_GL_M2_E2 + if (row >= 0 && row < 80) data[14:0] = r_nv_ram_rwsthp_80x15.ram_Inst_80X15.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 80; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [14:0] random_num; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 1200); + row = random_num / 15; + bitnum = random_num % 15; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [6:0] row; +input [14:0] bitnum; +reg [14:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15.v.vcp new file mode 100644 index 0000000..a41c2af --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15.v.vcp @@ -0,0 +1,511 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x15.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_80x15 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [14:0] dout; +input [6:0] wa; +input we; +input [14:0] di; +input byp_sel; +input [14:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_80X15_GL_M2_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [6:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [6:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [14:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_6 (.Y(pre_mbist_Wa_w0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_6 (.Z(mbist_Wa_w0[6]), .A1(pre_mbist_Wa_w0_6), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_6 (.Y(pre_mbist_Ra_r0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_6 (.Z(mbist_Ra_r0[6]), .A1(pre_mbist_Ra_r0_6), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_80x15_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_80x15 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[14:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [79:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [14:0] shadow_mem [79:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [14:0] shadow_mem_row0 = shadow_mem[0]; +wire [14:0] shadow_mem_row1 = shadow_mem[1]; +wire [14:0] shadow_mem_row2 = shadow_mem[2]; +wire [14:0] shadow_mem_row3 = shadow_mem[3]; +wire [14:0] shadow_mem_row4 = shadow_mem[4]; +wire [14:0] shadow_mem_row5 = shadow_mem[5]; +wire [14:0] shadow_mem_row6 = shadow_mem[6]; +wire [14:0] shadow_mem_row7 = shadow_mem[7]; +wire [14:0] shadow_mem_row8 = shadow_mem[8]; +wire [14:0] shadow_mem_row9 = shadow_mem[9]; +wire [14:0] shadow_mem_row10 = shadow_mem[10]; +wire [14:0] shadow_mem_row11 = shadow_mem[11]; +wire [14:0] shadow_mem_row12 = shadow_mem[12]; +wire [14:0] shadow_mem_row13 = shadow_mem[13]; +wire [14:0] shadow_mem_row14 = shadow_mem[14]; +wire [14:0] shadow_mem_row15 = shadow_mem[15]; +wire [14:0] shadow_mem_row16 = shadow_mem[16]; +wire [14:0] shadow_mem_row17 = shadow_mem[17]; +wire [14:0] shadow_mem_row18 = shadow_mem[18]; +wire [14:0] shadow_mem_row19 = shadow_mem[19]; +wire [14:0] shadow_mem_row20 = shadow_mem[20]; +wire [14:0] shadow_mem_row21 = shadow_mem[21]; +wire [14:0] shadow_mem_row22 = shadow_mem[22]; +wire [14:0] shadow_mem_row23 = shadow_mem[23]; +wire [14:0] shadow_mem_row24 = shadow_mem[24]; +wire [14:0] shadow_mem_row25 = shadow_mem[25]; +wire [14:0] shadow_mem_row26 = shadow_mem[26]; +wire [14:0] shadow_mem_row27 = shadow_mem[27]; +wire [14:0] shadow_mem_row28 = shadow_mem[28]; +wire [14:0] shadow_mem_row29 = shadow_mem[29]; +wire [14:0] shadow_mem_row30 = shadow_mem[30]; +wire [14:0] shadow_mem_row31 = shadow_mem[31]; +wire [14:0] shadow_mem_row32 = shadow_mem[32]; +wire [14:0] shadow_mem_row33 = shadow_mem[33]; +wire [14:0] shadow_mem_row34 = shadow_mem[34]; +wire [14:0] shadow_mem_row35 = shadow_mem[35]; +wire [14:0] shadow_mem_row36 = shadow_mem[36]; +wire [14:0] shadow_mem_row37 = shadow_mem[37]; +wire [14:0] shadow_mem_row38 = shadow_mem[38]; +wire [14:0] shadow_mem_row39 = shadow_mem[39]; +wire [14:0] shadow_mem_row40 = shadow_mem[40]; +wire [14:0] shadow_mem_row41 = shadow_mem[41]; +wire [14:0] shadow_mem_row42 = shadow_mem[42]; +wire [14:0] shadow_mem_row43 = shadow_mem[43]; +wire [14:0] shadow_mem_row44 = shadow_mem[44]; +wire [14:0] shadow_mem_row45 = shadow_mem[45]; +wire [14:0] shadow_mem_row46 = shadow_mem[46]; +wire [14:0] shadow_mem_row47 = shadow_mem[47]; +wire [14:0] shadow_mem_row48 = shadow_mem[48]; +wire [14:0] shadow_mem_row49 = shadow_mem[49]; +wire [14:0] shadow_mem_row50 = shadow_mem[50]; +wire [14:0] shadow_mem_row51 = shadow_mem[51]; +wire [14:0] shadow_mem_row52 = shadow_mem[52]; +wire [14:0] shadow_mem_row53 = shadow_mem[53]; +wire [14:0] shadow_mem_row54 = shadow_mem[54]; +wire [14:0] shadow_mem_row55 = shadow_mem[55]; +wire [14:0] shadow_mem_row56 = shadow_mem[56]; +wire [14:0] shadow_mem_row57 = shadow_mem[57]; +wire [14:0] shadow_mem_row58 = shadow_mem[58]; +wire [14:0] shadow_mem_row59 = shadow_mem[59]; +wire [14:0] shadow_mem_row60 = shadow_mem[60]; +wire [14:0] shadow_mem_row61 = shadow_mem[61]; +wire [14:0] shadow_mem_row62 = shadow_mem[62]; +wire [14:0] shadow_mem_row63 = shadow_mem[63]; +wire [14:0] shadow_mem_row64 = shadow_mem[64]; +wire [14:0] shadow_mem_row65 = shadow_mem[65]; +wire [14:0] shadow_mem_row66 = shadow_mem[66]; +wire [14:0] shadow_mem_row67 = shadow_mem[67]; +wire [14:0] shadow_mem_row68 = shadow_mem[68]; +wire [14:0] shadow_mem_row69 = shadow_mem[69]; +wire [14:0] shadow_mem_row70 = shadow_mem[70]; +wire [14:0] shadow_mem_row71 = shadow_mem[71]; +wire [14:0] shadow_mem_row72 = shadow_mem[72]; +wire [14:0] shadow_mem_row73 = shadow_mem[73]; +wire [14:0] shadow_mem_row74 = shadow_mem[74]; +wire [14:0] shadow_mem_row75 = shadow_mem[75]; +wire [14:0] shadow_mem_row76 = shadow_mem[76]; +wire [14:0] shadow_mem_row77 = shadow_mem[77]; +wire [14:0] shadow_mem_row78 = shadow_mem[78]; +wire [14:0] shadow_mem_row79 = shadow_mem[79]; +`endif +task init_mem_val; + input [6:0] row; + input [14:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_80X15_GL_M2_E2 +for (row = 0; row < 80; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_80x15.ram_Inst_80X15.mem_write(row - 0, shadow_mem[row][14:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [6:0] wa; + input we; + input [14:0] di; + reg [14:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [14:0] probe_mem_val; +input [6:0] row; +reg [14:0] data; +begin +// probing RAMDP_80X15_GL_M2_E2 + if (row >= 0 && row < 80) data[14:0] = r_nv_ram_rwsthp_80x15.ram_Inst_80X15.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 80; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [14:0] random_num; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 1200); + row = random_num / 15; + bitnum = random_num % 15; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [6:0] row; +input [14:0] bitnum; +reg [14:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15_logic.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15_logic.v new file mode 100644 index 0000000..afc3dbc --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15_logic.v @@ -0,0 +1,582 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x15_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_80x15_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [14:0] dbyp; +input debug_mode; +input [14:0] di; +output [14:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [14:0] mbist_Do_r0_int_net; +input [6:0] mbist_Ra_r0; +input [6:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [6:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [6:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [6:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [14:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [14:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [14:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [14:0] pre_muxed_Di_w0; +wire [14:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[14:0]; +assign pre_muxed_Di_w0_B = {mbist_Di_w0[0], {7{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {15{`tick_x_or_0}}; + endcase +reg [14:0] muxed_Di_w0; +wire [14:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[14:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {15{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [6:0] pre_Wa_reg_w0; +reg [6:0] Wa_reg_w0; +wire [6:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {7{`tick_x_or_0}}; +endcase +reg [6:0] muxed_Wa_w0; +wire [6:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {7{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [6:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [6:0] pre_Ra_reg_r0; +reg [6:0] Ra_reg_r0; +wire [6:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {7{`tick_x_or_0}}; +endcase +wire [6:0] D_Ra_reg_r0; +reg [6:0] muxed_Ra_r0; +wire [6:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {7{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [6:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_80X15_GL_M2_E2 (RamCell) +// Covers Addresses from 0 to 79 Addressrange: [6:0] +// Data Bit range: [14:0] (15 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [6:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[6:0]; +// Write Data in bus +wire [14:0] Wdata; +assign Wdata = muxed_Di_w0[14:0]; +assign we_0_0 = we; +// Read Address bus +wire [6:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[6:0]; +// Read DataOut bus +wire [14:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_80X15_GL_M2_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [14:0] ramDataOut; +assign dout_0_0[14:0] = ramDataOut[14:0]; +RAMDP_80X15_GL_M2_E2 ram_Inst_80X15 ( + .CLK_W (gated_clk_core) + , .WADR_6 (wa_0_0[6]) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_6 (ra_0_0 [6] & !test_mode) + , .RADR_5 (ra_0_0 [5]) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [14:0] ram_r0_OutputMuxDataOut; +//For bitEnd 14, only one piece RAMDP_80X15_GL_M2_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[14:0] or muxed_Di_w0[14:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[14:0] = (ram_bypass) ? muxed_Di_w0[14:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[14:0] = ram_r0_OutputMuxDataOut[14:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [14:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [14:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 14 LSB 0 and total rambit is 15 and dsize is 15 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [14:0]data_regq; +assign Data_reg_r0[14:0] = data_regq[14:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[15-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(15, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[14:0]), .Q(data_regq[14:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15_logic.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15_logic.v.vcp new file mode 100644 index 0000000..afc3dbc --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x15_logic.v.vcp @@ -0,0 +1,582 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x15_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_80x15_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [14:0] dbyp; +input debug_mode; +input [14:0] di; +output [14:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [14:0] mbist_Do_r0_int_net; +input [6:0] mbist_Ra_r0; +input [6:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [6:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [6:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [6:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [14:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [14:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [14:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [14:0] pre_muxed_Di_w0; +wire [14:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[14:0]; +assign pre_muxed_Di_w0_B = {mbist_Di_w0[0], {7{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {15{`tick_x_or_0}}; + endcase +reg [14:0] muxed_Di_w0; +wire [14:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[14:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {15{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [6:0] pre_Wa_reg_w0; +reg [6:0] Wa_reg_w0; +wire [6:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {7{`tick_x_or_0}}; +endcase +reg [6:0] muxed_Wa_w0; +wire [6:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {7{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [6:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [6:0] pre_Ra_reg_r0; +reg [6:0] Ra_reg_r0; +wire [6:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {7{`tick_x_or_0}}; +endcase +wire [6:0] D_Ra_reg_r0; +reg [6:0] muxed_Ra_r0; +wire [6:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {7{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [6:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_80X15_GL_M2_E2 (RamCell) +// Covers Addresses from 0 to 79 Addressrange: [6:0] +// Data Bit range: [14:0] (15 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [6:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[6:0]; +// Write Data in bus +wire [14:0] Wdata; +assign Wdata = muxed_Di_w0[14:0]; +assign we_0_0 = we; +// Read Address bus +wire [6:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[6:0]; +// Read DataOut bus +wire [14:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_80X15_GL_M2_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [14:0] ramDataOut; +assign dout_0_0[14:0] = ramDataOut[14:0]; +RAMDP_80X15_GL_M2_E2 ram_Inst_80X15 ( + .CLK_W (gated_clk_core) + , .WADR_6 (wa_0_0[6]) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_6 (ra_0_0 [6] & !test_mode) + , .RADR_5 (ra_0_0 [5]) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [14:0] ram_r0_OutputMuxDataOut; +//For bitEnd 14, only one piece RAMDP_80X15_GL_M2_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[14:0] or muxed_Di_w0[14:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[14:0] = (ram_bypass) ? muxed_Di_w0[14:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[14:0] = ram_r0_OutputMuxDataOut[14:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [14:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [14:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 14 LSB 0 and total rambit is 15 and dsize is 15 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [14:0]data_regq; +assign Data_reg_r0[14:0] = data_regq[14:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[15-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(15, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[14:0]), .Q(data_regq[14:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72.v new file mode 100644 index 0000000..90176b1 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72.v @@ -0,0 +1,747 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x72.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_80x72 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [71:0] dout; +input [6:0] wa; +input we; +input [71:0] di; +input byp_sel; +input [71:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMPDP_80X72_GL_M1_D2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [6:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [6:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [71:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [7:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_6 (.Y(pre_mbist_Wa_w0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_6 (.Z(mbist_Wa_w0[6]), .A1(pre_mbist_Wa_w0_6), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_6 (.Y(pre_mbist_Ra_r0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_6 (.Z(mbist_Ra_r0[6]), .A1(pre_mbist_Ra_r0_6), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_22 (.A(mbist_Do_r0_int_net[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_23 (.A(mbist_Do_r0_int_net[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_24 (.A(mbist_Do_r0_int_net[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_25 (.A(mbist_Do_r0_int_net[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_26 (.A(mbist_Do_r0_int_net[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_27 (.A(mbist_Do_r0_int_net[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_28 (.A(mbist_Do_r0_int_net[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_29 (.A(mbist_Do_r0_int_net[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_30 (.A(mbist_Do_r0_int_net[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_31 (.A(mbist_Do_r0_int_net[31])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_32 (.A(mbist_Do_r0_int_net[32])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_33 (.A(mbist_Do_r0_int_net[33])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_34 (.A(mbist_Do_r0_int_net[34])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_35 (.A(mbist_Do_r0_int_net[35])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_36 (.A(mbist_Do_r0_int_net[36])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_37 (.A(mbist_Do_r0_int_net[37])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_38 (.A(mbist_Do_r0_int_net[38])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_39 (.A(mbist_Do_r0_int_net[39])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_40 (.A(mbist_Do_r0_int_net[40])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_41 (.A(mbist_Do_r0_int_net[41])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_42 (.A(mbist_Do_r0_int_net[42])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_43 (.A(mbist_Do_r0_int_net[43])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_44 (.A(mbist_Do_r0_int_net[44])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_45 (.A(mbist_Do_r0_int_net[45])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_46 (.A(mbist_Do_r0_int_net[46])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_47 (.A(mbist_Do_r0_int_net[47])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_48 (.A(mbist_Do_r0_int_net[48])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_49 (.A(mbist_Do_r0_int_net[49])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_50 (.A(mbist_Do_r0_int_net[50])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_51 (.A(mbist_Do_r0_int_net[51])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_52 (.A(mbist_Do_r0_int_net[52])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_53 (.A(mbist_Do_r0_int_net[53])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_54 (.A(mbist_Do_r0_int_net[54])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_55 (.A(mbist_Do_r0_int_net[55])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_56 (.A(mbist_Do_r0_int_net[56])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_57 (.A(mbist_Do_r0_int_net[57])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_58 (.A(mbist_Do_r0_int_net[58])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_59 (.A(mbist_Do_r0_int_net[59])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_60 (.A(mbist_Do_r0_int_net[60])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_61 (.A(mbist_Do_r0_int_net[61])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_62 (.A(mbist_Do_r0_int_net[62])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_63 (.A(mbist_Do_r0_int_net[63])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_64 (.A(mbist_Do_r0_int_net[64])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_65 (.A(mbist_Do_r0_int_net[65])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_66 (.A(mbist_Do_r0_int_net[66])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_67 (.A(mbist_Do_r0_int_net[67])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_68 (.A(mbist_Do_r0_int_net[68])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_69 (.A(mbist_Do_r0_int_net[69])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_70 (.A(mbist_Do_r0_int_net[70])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_71 (.A(mbist_Do_r0_int_net[71])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +NV_BLKBOX_SRC0 testInst_svop_2 (.Y(svop[2])); +NV_BLKBOX_SRC0 testInst_svop_3 (.Y(svop[3])); +NV_BLKBOX_SRC0 testInst_svop_4 (.Y(svop[4])); +NV_BLKBOX_SRC0 testInst_svop_5 (.Y(svop[5])); +NV_BLKBOX_SRC0 testInst_svop_6 (.Y(svop[6])); +NV_BLKBOX_SRC0 testInst_svop_7 (.Y(svop[7])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_80x72_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_80x72 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[71:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + arrangment_string[32] = 32 ; + arrangment_string[33] = 33 ; + arrangment_string[34] = 34 ; + arrangment_string[35] = 35 ; + arrangment_string[36] = 36 ; + arrangment_string[37] = 37 ; + arrangment_string[38] = 38 ; + arrangment_string[39] = 39 ; + arrangment_string[40] = 40 ; + arrangment_string[41] = 41 ; + arrangment_string[42] = 42 ; + arrangment_string[43] = 43 ; + arrangment_string[44] = 44 ; + arrangment_string[45] = 45 ; + arrangment_string[46] = 46 ; + arrangment_string[47] = 47 ; + arrangment_string[48] = 48 ; + arrangment_string[49] = 49 ; + arrangment_string[50] = 50 ; + arrangment_string[51] = 51 ; + arrangment_string[52] = 52 ; + arrangment_string[53] = 53 ; + arrangment_string[54] = 54 ; + arrangment_string[55] = 55 ; + arrangment_string[56] = 56 ; + arrangment_string[57] = 57 ; + arrangment_string[58] = 58 ; + arrangment_string[59] = 59 ; + arrangment_string[60] = 60 ; + arrangment_string[61] = 61 ; + arrangment_string[62] = 62 ; + arrangment_string[63] = 63 ; + arrangment_string[64] = 64 ; + arrangment_string[65] = 65 ; + arrangment_string[66] = 66 ; + arrangment_string[67] = 67 ; + arrangment_string[68] = 68 ; + arrangment_string[69] = 69 ; + arrangment_string[70] = 70 ; + arrangment_string[71] = 71 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [79:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [71:0] shadow_mem [79:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [71:0] shadow_mem_row0 = shadow_mem[0]; +wire [71:0] shadow_mem_row1 = shadow_mem[1]; +wire [71:0] shadow_mem_row2 = shadow_mem[2]; +wire [71:0] shadow_mem_row3 = shadow_mem[3]; +wire [71:0] shadow_mem_row4 = shadow_mem[4]; +wire [71:0] shadow_mem_row5 = shadow_mem[5]; +wire [71:0] shadow_mem_row6 = shadow_mem[6]; +wire [71:0] shadow_mem_row7 = shadow_mem[7]; +wire [71:0] shadow_mem_row8 = shadow_mem[8]; +wire [71:0] shadow_mem_row9 = shadow_mem[9]; +wire [71:0] shadow_mem_row10 = shadow_mem[10]; +wire [71:0] shadow_mem_row11 = shadow_mem[11]; +wire [71:0] shadow_mem_row12 = shadow_mem[12]; +wire [71:0] shadow_mem_row13 = shadow_mem[13]; +wire [71:0] shadow_mem_row14 = shadow_mem[14]; +wire [71:0] shadow_mem_row15 = shadow_mem[15]; +wire [71:0] shadow_mem_row16 = shadow_mem[16]; +wire [71:0] shadow_mem_row17 = shadow_mem[17]; +wire [71:0] shadow_mem_row18 = shadow_mem[18]; +wire [71:0] shadow_mem_row19 = shadow_mem[19]; +wire [71:0] shadow_mem_row20 = shadow_mem[20]; +wire [71:0] shadow_mem_row21 = shadow_mem[21]; +wire [71:0] shadow_mem_row22 = shadow_mem[22]; +wire [71:0] shadow_mem_row23 = shadow_mem[23]; +wire [71:0] shadow_mem_row24 = shadow_mem[24]; +wire [71:0] shadow_mem_row25 = shadow_mem[25]; +wire [71:0] shadow_mem_row26 = shadow_mem[26]; +wire [71:0] shadow_mem_row27 = shadow_mem[27]; +wire [71:0] shadow_mem_row28 = shadow_mem[28]; +wire [71:0] shadow_mem_row29 = shadow_mem[29]; +wire [71:0] shadow_mem_row30 = shadow_mem[30]; +wire [71:0] shadow_mem_row31 = shadow_mem[31]; +wire [71:0] shadow_mem_row32 = shadow_mem[32]; +wire [71:0] shadow_mem_row33 = shadow_mem[33]; +wire [71:0] shadow_mem_row34 = shadow_mem[34]; +wire [71:0] shadow_mem_row35 = shadow_mem[35]; +wire [71:0] shadow_mem_row36 = shadow_mem[36]; +wire [71:0] shadow_mem_row37 = shadow_mem[37]; +wire [71:0] shadow_mem_row38 = shadow_mem[38]; +wire [71:0] shadow_mem_row39 = shadow_mem[39]; +wire [71:0] shadow_mem_row40 = shadow_mem[40]; +wire [71:0] shadow_mem_row41 = shadow_mem[41]; +wire [71:0] shadow_mem_row42 = shadow_mem[42]; +wire [71:0] shadow_mem_row43 = shadow_mem[43]; +wire [71:0] shadow_mem_row44 = shadow_mem[44]; +wire [71:0] shadow_mem_row45 = shadow_mem[45]; +wire [71:0] shadow_mem_row46 = shadow_mem[46]; +wire [71:0] shadow_mem_row47 = shadow_mem[47]; +wire [71:0] shadow_mem_row48 = shadow_mem[48]; +wire [71:0] shadow_mem_row49 = shadow_mem[49]; +wire [71:0] shadow_mem_row50 = shadow_mem[50]; +wire [71:0] shadow_mem_row51 = shadow_mem[51]; +wire [71:0] shadow_mem_row52 = shadow_mem[52]; +wire [71:0] shadow_mem_row53 = shadow_mem[53]; +wire [71:0] shadow_mem_row54 = shadow_mem[54]; +wire [71:0] shadow_mem_row55 = shadow_mem[55]; +wire [71:0] shadow_mem_row56 = shadow_mem[56]; +wire [71:0] shadow_mem_row57 = shadow_mem[57]; +wire [71:0] shadow_mem_row58 = shadow_mem[58]; +wire [71:0] shadow_mem_row59 = shadow_mem[59]; +wire [71:0] shadow_mem_row60 = shadow_mem[60]; +wire [71:0] shadow_mem_row61 = shadow_mem[61]; +wire [71:0] shadow_mem_row62 = shadow_mem[62]; +wire [71:0] shadow_mem_row63 = shadow_mem[63]; +wire [71:0] shadow_mem_row64 = shadow_mem[64]; +wire [71:0] shadow_mem_row65 = shadow_mem[65]; +wire [71:0] shadow_mem_row66 = shadow_mem[66]; +wire [71:0] shadow_mem_row67 = shadow_mem[67]; +wire [71:0] shadow_mem_row68 = shadow_mem[68]; +wire [71:0] shadow_mem_row69 = shadow_mem[69]; +wire [71:0] shadow_mem_row70 = shadow_mem[70]; +wire [71:0] shadow_mem_row71 = shadow_mem[71]; +wire [71:0] shadow_mem_row72 = shadow_mem[72]; +wire [71:0] shadow_mem_row73 = shadow_mem[73]; +wire [71:0] shadow_mem_row74 = shadow_mem[74]; +wire [71:0] shadow_mem_row75 = shadow_mem[75]; +wire [71:0] shadow_mem_row76 = shadow_mem[76]; +wire [71:0] shadow_mem_row77 = shadow_mem[77]; +wire [71:0] shadow_mem_row78 = shadow_mem[78]; +wire [71:0] shadow_mem_row79 = shadow_mem[79]; +`endif +task init_mem_val; + input [6:0] row; + input [71:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMPDP_80X72_GL_M1_D2 +for (row = 0; row < 80; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_80x72.ram_Inst_80X72.mem_write(row - 0, shadow_mem[row][71:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [6:0] wa; + input we; + input [71:0] di; + reg [71:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [71:0] probe_mem_val; +input [6:0] row; +reg [71:0] data; +begin +// probing RAMPDP_80X72_GL_M1_D2 + if (row >= 0 && row < 80) data[71:0] = r_nv_ram_rwsthp_80x72.ram_Inst_80X72.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 80; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +RANDFUNC rf1 (); +RANDFUNC rf2 (); +task init_mem_random; +reg [71:0] random_num; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff),rf1.rollpli(0,32'hffffffff),rf2.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 5760); + row = random_num / 72; + bitnum = random_num % 72; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [6:0] row; +input [71:0] bitnum; +reg [71:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72.v.vcp new file mode 100644 index 0000000..90176b1 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72.v.vcp @@ -0,0 +1,747 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x72.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_80x72 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [71:0] dout; +input [6:0] wa; +input we; +input [71:0] di; +input byp_sel; +input [71:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMPDP_80X72_GL_M1_D2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [6:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [6:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [71:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [7:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_6 (.Y(pre_mbist_Wa_w0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_6 (.Z(mbist_Wa_w0[6]), .A1(pre_mbist_Wa_w0_6), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_6 (.Y(pre_mbist_Ra_r0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_6 (.Z(mbist_Ra_r0[6]), .A1(pre_mbist_Ra_r0_6), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_9 (.A(mbist_Do_r0_int_net[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_10 (.A(mbist_Do_r0_int_net[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_11 (.A(mbist_Do_r0_int_net[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_12 (.A(mbist_Do_r0_int_net[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_13 (.A(mbist_Do_r0_int_net[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_14 (.A(mbist_Do_r0_int_net[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_15 (.A(mbist_Do_r0_int_net[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_16 (.A(mbist_Do_r0_int_net[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_17 (.A(mbist_Do_r0_int_net[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_18 (.A(mbist_Do_r0_int_net[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_19 (.A(mbist_Do_r0_int_net[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_20 (.A(mbist_Do_r0_int_net[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_21 (.A(mbist_Do_r0_int_net[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_22 (.A(mbist_Do_r0_int_net[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_23 (.A(mbist_Do_r0_int_net[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_24 (.A(mbist_Do_r0_int_net[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_25 (.A(mbist_Do_r0_int_net[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_26 (.A(mbist_Do_r0_int_net[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_27 (.A(mbist_Do_r0_int_net[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_28 (.A(mbist_Do_r0_int_net[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_29 (.A(mbist_Do_r0_int_net[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_30 (.A(mbist_Do_r0_int_net[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_31 (.A(mbist_Do_r0_int_net[31])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_32 (.A(mbist_Do_r0_int_net[32])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_33 (.A(mbist_Do_r0_int_net[33])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_34 (.A(mbist_Do_r0_int_net[34])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_35 (.A(mbist_Do_r0_int_net[35])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_36 (.A(mbist_Do_r0_int_net[36])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_37 (.A(mbist_Do_r0_int_net[37])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_38 (.A(mbist_Do_r0_int_net[38])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_39 (.A(mbist_Do_r0_int_net[39])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_40 (.A(mbist_Do_r0_int_net[40])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_41 (.A(mbist_Do_r0_int_net[41])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_42 (.A(mbist_Do_r0_int_net[42])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_43 (.A(mbist_Do_r0_int_net[43])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_44 (.A(mbist_Do_r0_int_net[44])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_45 (.A(mbist_Do_r0_int_net[45])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_46 (.A(mbist_Do_r0_int_net[46])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_47 (.A(mbist_Do_r0_int_net[47])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_48 (.A(mbist_Do_r0_int_net[48])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_49 (.A(mbist_Do_r0_int_net[49])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_50 (.A(mbist_Do_r0_int_net[50])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_51 (.A(mbist_Do_r0_int_net[51])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_52 (.A(mbist_Do_r0_int_net[52])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_53 (.A(mbist_Do_r0_int_net[53])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_54 (.A(mbist_Do_r0_int_net[54])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_55 (.A(mbist_Do_r0_int_net[55])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_56 (.A(mbist_Do_r0_int_net[56])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_57 (.A(mbist_Do_r0_int_net[57])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_58 (.A(mbist_Do_r0_int_net[58])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_59 (.A(mbist_Do_r0_int_net[59])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_60 (.A(mbist_Do_r0_int_net[60])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_61 (.A(mbist_Do_r0_int_net[61])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_62 (.A(mbist_Do_r0_int_net[62])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_63 (.A(mbist_Do_r0_int_net[63])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_64 (.A(mbist_Do_r0_int_net[64])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_65 (.A(mbist_Do_r0_int_net[65])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_66 (.A(mbist_Do_r0_int_net[66])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_67 (.A(mbist_Do_r0_int_net[67])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_68 (.A(mbist_Do_r0_int_net[68])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_69 (.A(mbist_Do_r0_int_net[69])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_70 (.A(mbist_Do_r0_int_net[70])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_71 (.A(mbist_Do_r0_int_net[71])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +NV_BLKBOX_SRC0 testInst_svop_2 (.Y(svop[2])); +NV_BLKBOX_SRC0 testInst_svop_3 (.Y(svop[3])); +NV_BLKBOX_SRC0 testInst_svop_4 (.Y(svop[4])); +NV_BLKBOX_SRC0 testInst_svop_5 (.Y(svop[5])); +NV_BLKBOX_SRC0 testInst_svop_6 (.Y(svop[6])); +NV_BLKBOX_SRC0 testInst_svop_7 (.Y(svop[7])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_80x72_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_80x72 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[71:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + arrangment_string[9] = 9 ; + arrangment_string[10] = 10 ; + arrangment_string[11] = 11 ; + arrangment_string[12] = 12 ; + arrangment_string[13] = 13 ; + arrangment_string[14] = 14 ; + arrangment_string[15] = 15 ; + arrangment_string[16] = 16 ; + arrangment_string[17] = 17 ; + arrangment_string[18] = 18 ; + arrangment_string[19] = 19 ; + arrangment_string[20] = 20 ; + arrangment_string[21] = 21 ; + arrangment_string[22] = 22 ; + arrangment_string[23] = 23 ; + arrangment_string[24] = 24 ; + arrangment_string[25] = 25 ; + arrangment_string[26] = 26 ; + arrangment_string[27] = 27 ; + arrangment_string[28] = 28 ; + arrangment_string[29] = 29 ; + arrangment_string[30] = 30 ; + arrangment_string[31] = 31 ; + arrangment_string[32] = 32 ; + arrangment_string[33] = 33 ; + arrangment_string[34] = 34 ; + arrangment_string[35] = 35 ; + arrangment_string[36] = 36 ; + arrangment_string[37] = 37 ; + arrangment_string[38] = 38 ; + arrangment_string[39] = 39 ; + arrangment_string[40] = 40 ; + arrangment_string[41] = 41 ; + arrangment_string[42] = 42 ; + arrangment_string[43] = 43 ; + arrangment_string[44] = 44 ; + arrangment_string[45] = 45 ; + arrangment_string[46] = 46 ; + arrangment_string[47] = 47 ; + arrangment_string[48] = 48 ; + arrangment_string[49] = 49 ; + arrangment_string[50] = 50 ; + arrangment_string[51] = 51 ; + arrangment_string[52] = 52 ; + arrangment_string[53] = 53 ; + arrangment_string[54] = 54 ; + arrangment_string[55] = 55 ; + arrangment_string[56] = 56 ; + arrangment_string[57] = 57 ; + arrangment_string[58] = 58 ; + arrangment_string[59] = 59 ; + arrangment_string[60] = 60 ; + arrangment_string[61] = 61 ; + arrangment_string[62] = 62 ; + arrangment_string[63] = 63 ; + arrangment_string[64] = 64 ; + arrangment_string[65] = 65 ; + arrangment_string[66] = 66 ; + arrangment_string[67] = 67 ; + arrangment_string[68] = 68 ; + arrangment_string[69] = 69 ; + arrangment_string[70] = 70 ; + arrangment_string[71] = 71 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [79:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [71:0] shadow_mem [79:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [71:0] shadow_mem_row0 = shadow_mem[0]; +wire [71:0] shadow_mem_row1 = shadow_mem[1]; +wire [71:0] shadow_mem_row2 = shadow_mem[2]; +wire [71:0] shadow_mem_row3 = shadow_mem[3]; +wire [71:0] shadow_mem_row4 = shadow_mem[4]; +wire [71:0] shadow_mem_row5 = shadow_mem[5]; +wire [71:0] shadow_mem_row6 = shadow_mem[6]; +wire [71:0] shadow_mem_row7 = shadow_mem[7]; +wire [71:0] shadow_mem_row8 = shadow_mem[8]; +wire [71:0] shadow_mem_row9 = shadow_mem[9]; +wire [71:0] shadow_mem_row10 = shadow_mem[10]; +wire [71:0] shadow_mem_row11 = shadow_mem[11]; +wire [71:0] shadow_mem_row12 = shadow_mem[12]; +wire [71:0] shadow_mem_row13 = shadow_mem[13]; +wire [71:0] shadow_mem_row14 = shadow_mem[14]; +wire [71:0] shadow_mem_row15 = shadow_mem[15]; +wire [71:0] shadow_mem_row16 = shadow_mem[16]; +wire [71:0] shadow_mem_row17 = shadow_mem[17]; +wire [71:0] shadow_mem_row18 = shadow_mem[18]; +wire [71:0] shadow_mem_row19 = shadow_mem[19]; +wire [71:0] shadow_mem_row20 = shadow_mem[20]; +wire [71:0] shadow_mem_row21 = shadow_mem[21]; +wire [71:0] shadow_mem_row22 = shadow_mem[22]; +wire [71:0] shadow_mem_row23 = shadow_mem[23]; +wire [71:0] shadow_mem_row24 = shadow_mem[24]; +wire [71:0] shadow_mem_row25 = shadow_mem[25]; +wire [71:0] shadow_mem_row26 = shadow_mem[26]; +wire [71:0] shadow_mem_row27 = shadow_mem[27]; +wire [71:0] shadow_mem_row28 = shadow_mem[28]; +wire [71:0] shadow_mem_row29 = shadow_mem[29]; +wire [71:0] shadow_mem_row30 = shadow_mem[30]; +wire [71:0] shadow_mem_row31 = shadow_mem[31]; +wire [71:0] shadow_mem_row32 = shadow_mem[32]; +wire [71:0] shadow_mem_row33 = shadow_mem[33]; +wire [71:0] shadow_mem_row34 = shadow_mem[34]; +wire [71:0] shadow_mem_row35 = shadow_mem[35]; +wire [71:0] shadow_mem_row36 = shadow_mem[36]; +wire [71:0] shadow_mem_row37 = shadow_mem[37]; +wire [71:0] shadow_mem_row38 = shadow_mem[38]; +wire [71:0] shadow_mem_row39 = shadow_mem[39]; +wire [71:0] shadow_mem_row40 = shadow_mem[40]; +wire [71:0] shadow_mem_row41 = shadow_mem[41]; +wire [71:0] shadow_mem_row42 = shadow_mem[42]; +wire [71:0] shadow_mem_row43 = shadow_mem[43]; +wire [71:0] shadow_mem_row44 = shadow_mem[44]; +wire [71:0] shadow_mem_row45 = shadow_mem[45]; +wire [71:0] shadow_mem_row46 = shadow_mem[46]; +wire [71:0] shadow_mem_row47 = shadow_mem[47]; +wire [71:0] shadow_mem_row48 = shadow_mem[48]; +wire [71:0] shadow_mem_row49 = shadow_mem[49]; +wire [71:0] shadow_mem_row50 = shadow_mem[50]; +wire [71:0] shadow_mem_row51 = shadow_mem[51]; +wire [71:0] shadow_mem_row52 = shadow_mem[52]; +wire [71:0] shadow_mem_row53 = shadow_mem[53]; +wire [71:0] shadow_mem_row54 = shadow_mem[54]; +wire [71:0] shadow_mem_row55 = shadow_mem[55]; +wire [71:0] shadow_mem_row56 = shadow_mem[56]; +wire [71:0] shadow_mem_row57 = shadow_mem[57]; +wire [71:0] shadow_mem_row58 = shadow_mem[58]; +wire [71:0] shadow_mem_row59 = shadow_mem[59]; +wire [71:0] shadow_mem_row60 = shadow_mem[60]; +wire [71:0] shadow_mem_row61 = shadow_mem[61]; +wire [71:0] shadow_mem_row62 = shadow_mem[62]; +wire [71:0] shadow_mem_row63 = shadow_mem[63]; +wire [71:0] shadow_mem_row64 = shadow_mem[64]; +wire [71:0] shadow_mem_row65 = shadow_mem[65]; +wire [71:0] shadow_mem_row66 = shadow_mem[66]; +wire [71:0] shadow_mem_row67 = shadow_mem[67]; +wire [71:0] shadow_mem_row68 = shadow_mem[68]; +wire [71:0] shadow_mem_row69 = shadow_mem[69]; +wire [71:0] shadow_mem_row70 = shadow_mem[70]; +wire [71:0] shadow_mem_row71 = shadow_mem[71]; +wire [71:0] shadow_mem_row72 = shadow_mem[72]; +wire [71:0] shadow_mem_row73 = shadow_mem[73]; +wire [71:0] shadow_mem_row74 = shadow_mem[74]; +wire [71:0] shadow_mem_row75 = shadow_mem[75]; +wire [71:0] shadow_mem_row76 = shadow_mem[76]; +wire [71:0] shadow_mem_row77 = shadow_mem[77]; +wire [71:0] shadow_mem_row78 = shadow_mem[78]; +wire [71:0] shadow_mem_row79 = shadow_mem[79]; +`endif +task init_mem_val; + input [6:0] row; + input [71:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMPDP_80X72_GL_M1_D2 +for (row = 0; row < 80; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_80x72.ram_Inst_80X72.mem_write(row - 0, shadow_mem[row][71:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [6:0] wa; + input we; + input [71:0] di; + reg [71:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [71:0] probe_mem_val; +input [6:0] row; +reg [71:0] data; +begin +// probing RAMPDP_80X72_GL_M1_D2 + if (row >= 0 && row < 80) data[71:0] = r_nv_ram_rwsthp_80x72.ram_Inst_80X72.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 80; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +RANDFUNC rf1 (); +RANDFUNC rf2 (); +task init_mem_random; +reg [71:0] random_num; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff),rf1.rollpli(0,32'hffffffff),rf2.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 5760); + row = random_num / 72; + bitnum = random_num % 72; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [6:0] row; +input [71:0] bitnum; +reg [71:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72_logic.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72_logic.v new file mode 100644 index 0000000..cadf6d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72_logic.v @@ -0,0 +1,701 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x72_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_80x72_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [71:0] dbyp; +input debug_mode; +input [71:0] di; +output [71:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [71:0] mbist_Do_r0_int_net; +input [6:0] mbist_Ra_r0; +input [6:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [6:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [7:0] svop; +input test_mode; +input updateDR; +input [6:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [6:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [71:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [71:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [71:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [71:0] pre_muxed_Di_w0; +wire [71:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[71:0]; +assign pre_muxed_Di_w0_B = {{36{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {72{`tick_x_or_0}}; + endcase +reg [71:0] muxed_Di_w0; +wire [71:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[71:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {72{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [6:0] pre_Wa_reg_w0; +reg [6:0] Wa_reg_w0; +wire [6:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {7{`tick_x_or_0}}; +endcase +reg [6:0] muxed_Wa_w0; +wire [6:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {7{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [6:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [6:0] pre_Ra_reg_r0; +reg [6:0] Ra_reg_r0; +wire [6:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {7{`tick_x_or_0}}; +endcase +wire [6:0] D_Ra_reg_r0; +reg [6:0] muxed_Ra_r0; +wire [6:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {7{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [6:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMPDP_80X72_GL_M1_D2 (RamCell) +// Covers Addresses from 0 to 79 Addressrange: [6:0] +// Data Bit range: [71:0] (72 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [6:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[6:0]; +// Write Data in bus +wire [71:0] Wdata; +assign Wdata = muxed_Di_w0[71:0]; +assign we_0_0 = we; +// Read Address bus +wire [6:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[6:0]; +// Read DataOut bus +wire [71:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMPDP_80X72_GL_M1_D2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = !(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [71:0] ramDataOut; +assign dout_0_0[71:0] = ramDataOut[71:0]; +RAMPDP_80X72_GL_M1_D2 ram_Inst_80X72 ( + .CLK (gated_clk_core) + , .WADR_6 (wa_0_0[6]) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_71 (Wdata[71]) + , .WD_70 (Wdata[70]) + , .WD_69 (Wdata[69]) + , .WD_68 (Wdata[68]) + , .WD_67 (Wdata[67]) + , .WD_66 (Wdata[66]) + , .WD_65 (Wdata[65]) + , .WD_64 (Wdata[64]) + , .WD_63 (Wdata[63]) + , .WD_62 (Wdata[62]) + , .WD_61 (Wdata[61]) + , .WD_60 (Wdata[60]) + , .WD_59 (Wdata[59]) + , .WD_58 (Wdata[58]) + , .WD_57 (Wdata[57]) + , .WD_56 (Wdata[56]) + , .WD_55 (Wdata[55]) + , .WD_54 (Wdata[54]) + , .WD_53 (Wdata[53]) + , .WD_52 (Wdata[52]) + , .WD_51 (Wdata[51]) + , .WD_50 (Wdata[50]) + , .WD_49 (Wdata[49]) + , .WD_48 (Wdata[48]) + , .WD_47 (Wdata[47]) + , .WD_46 (Wdata[46]) + , .WD_45 (Wdata[45]) + , .WD_44 (Wdata[44]) + , .WD_43 (Wdata[43]) + , .WD_42 (Wdata[42]) + , .WD_41 (Wdata[41]) + , .WD_40 (Wdata[40]) + , .WD_39 (Wdata[39]) + , .WD_38 (Wdata[38]) + , .WD_37 (Wdata[37]) + , .WD_36 (Wdata[36]) + , .WD_35 (Wdata[35]) + , .WD_34 (Wdata[34]) + , .WD_33 (Wdata[33]) + , .WD_32 (Wdata[32]) + , .WD_31 (Wdata[31]) + , .WD_30 (Wdata[30]) + , .WD_29 (Wdata[29]) + , .WD_28 (Wdata[28]) + , .WD_27 (Wdata[27]) + , .WD_26 (Wdata[26]) + , .WD_25 (Wdata[25]) + , .WD_24 (Wdata[24]) + , .WD_23 (Wdata[23]) + , .WD_22 (Wdata[22]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .RADR_6 (ra_0_0 [6] & !test_mode) + , .RADR_5 (ra_0_0 [5]) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_71 (ramDataOut[71]) + , .RD_70 (ramDataOut[70]) + , .RD_69 (ramDataOut[69]) + , .RD_68 (ramDataOut[68]) + , .RD_67 (ramDataOut[67]) + , .RD_66 (ramDataOut[66]) + , .RD_65 (ramDataOut[65]) + , .RD_64 (ramDataOut[64]) + , .RD_63 (ramDataOut[63]) + , .RD_62 (ramDataOut[62]) + , .RD_61 (ramDataOut[61]) + , .RD_60 (ramDataOut[60]) + , .RD_59 (ramDataOut[59]) + , .RD_58 (ramDataOut[58]) + , .RD_57 (ramDataOut[57]) + , .RD_56 (ramDataOut[56]) + , .RD_55 (ramDataOut[55]) + , .RD_54 (ramDataOut[54]) + , .RD_53 (ramDataOut[53]) + , .RD_52 (ramDataOut[52]) + , .RD_51 (ramDataOut[51]) + , .RD_50 (ramDataOut[50]) + , .RD_49 (ramDataOut[49]) + , .RD_48 (ramDataOut[48]) + , .RD_47 (ramDataOut[47]) + , .RD_46 (ramDataOut[46]) + , .RD_45 (ramDataOut[45]) + , .RD_44 (ramDataOut[44]) + , .RD_43 (ramDataOut[43]) + , .RD_42 (ramDataOut[42]) + , .RD_41 (ramDataOut[41]) + , .RD_40 (ramDataOut[40]) + , .RD_39 (ramDataOut[39]) + , .RD_38 (ramDataOut[38]) + , .RD_37 (ramDataOut[37]) + , .RD_36 (ramDataOut[36]) + , .RD_35 (ramDataOut[35]) + , .RD_34 (ramDataOut[34]) + , .RD_33 (ramDataOut[33]) + , .RD_32 (ramDataOut[32]) + , .RD_31 (ramDataOut[31]) + , .RD_30 (ramDataOut[30]) + , .RD_29 (ramDataOut[29]) + , .RD_28 (ramDataOut[28]) + , .RD_27 (ramDataOut[27]) + , .RD_26 (ramDataOut[26]) + , .RD_25 (ramDataOut[25]) + , .RD_24 (ramDataOut[24]) + , .RD_23 (ramDataOut[23]) + , .RD_22 (ramDataOut[22]) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .SVOP_2 (svop[2]) + , .SVOP_3 (svop[3]) + , .SVOP_4 (svop[4]) + , .SVOP_5 (svop[5]) + , .SVOP_6 (svop[6]) + , .SVOP_7 (svop[7]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [71:0] ram_r0_OutputMuxDataOut; +//For bitEnd 71, only one piece RAMPDP_80X72_GL_M1_D2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[71:0] or muxed_Di_w0[71:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[71:0] = (ram_bypass) ? muxed_Di_w0[71:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[71:0] = ram_r0_OutputMuxDataOut[71:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [71:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [71:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 71 LSB 0 and total rambit is 72 and dsize is 72 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [71:0]data_regq; +assign Data_reg_r0[71:0] = data_regq[71:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[72-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(72, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[71:0]), .Q(data_regq[71:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72_logic.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72_logic.v.vcp new file mode 100644 index 0000000..cadf6d2 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x72_logic.v.vcp @@ -0,0 +1,701 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x72_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_80x72_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [71:0] dbyp; +input debug_mode; +input [71:0] di; +output [71:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [71:0] mbist_Do_r0_int_net; +input [6:0] mbist_Ra_r0; +input [6:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [6:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [7:0] svop; +input test_mode; +input updateDR; +input [6:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [6:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [71:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [71:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [71:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [71:0] pre_muxed_Di_w0; +wire [71:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[71:0]; +assign pre_muxed_Di_w0_B = {{36{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {72{`tick_x_or_0}}; + endcase +reg [71:0] muxed_Di_w0; +wire [71:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[71:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {72{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [6:0] pre_Wa_reg_w0; +reg [6:0] Wa_reg_w0; +wire [6:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {7{`tick_x_or_0}}; +endcase +reg [6:0] muxed_Wa_w0; +wire [6:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {7{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [6:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [6:0] pre_Ra_reg_r0; +reg [6:0] Ra_reg_r0; +wire [6:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {7{`tick_x_or_0}}; +endcase +wire [6:0] D_Ra_reg_r0; +reg [6:0] muxed_Ra_r0; +wire [6:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {7{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [6:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMPDP_80X72_GL_M1_D2 (RamCell) +// Covers Addresses from 0 to 79 Addressrange: [6:0] +// Data Bit range: [71:0] (72 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [6:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[6:0]; +// Write Data in bus +wire [71:0] Wdata; +assign Wdata = muxed_Di_w0[71:0]; +assign we_0_0 = we; +// Read Address bus +wire [6:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[6:0]; +// Read DataOut bus +wire [71:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMPDP_80X72_GL_M1_D2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = !(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [71:0] ramDataOut; +assign dout_0_0[71:0] = ramDataOut[71:0]; +RAMPDP_80X72_GL_M1_D2 ram_Inst_80X72 ( + .CLK (gated_clk_core) + , .WADR_6 (wa_0_0[6]) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_71 (Wdata[71]) + , .WD_70 (Wdata[70]) + , .WD_69 (Wdata[69]) + , .WD_68 (Wdata[68]) + , .WD_67 (Wdata[67]) + , .WD_66 (Wdata[66]) + , .WD_65 (Wdata[65]) + , .WD_64 (Wdata[64]) + , .WD_63 (Wdata[63]) + , .WD_62 (Wdata[62]) + , .WD_61 (Wdata[61]) + , .WD_60 (Wdata[60]) + , .WD_59 (Wdata[59]) + , .WD_58 (Wdata[58]) + , .WD_57 (Wdata[57]) + , .WD_56 (Wdata[56]) + , .WD_55 (Wdata[55]) + , .WD_54 (Wdata[54]) + , .WD_53 (Wdata[53]) + , .WD_52 (Wdata[52]) + , .WD_51 (Wdata[51]) + , .WD_50 (Wdata[50]) + , .WD_49 (Wdata[49]) + , .WD_48 (Wdata[48]) + , .WD_47 (Wdata[47]) + , .WD_46 (Wdata[46]) + , .WD_45 (Wdata[45]) + , .WD_44 (Wdata[44]) + , .WD_43 (Wdata[43]) + , .WD_42 (Wdata[42]) + , .WD_41 (Wdata[41]) + , .WD_40 (Wdata[40]) + , .WD_39 (Wdata[39]) + , .WD_38 (Wdata[38]) + , .WD_37 (Wdata[37]) + , .WD_36 (Wdata[36]) + , .WD_35 (Wdata[35]) + , .WD_34 (Wdata[34]) + , .WD_33 (Wdata[33]) + , .WD_32 (Wdata[32]) + , .WD_31 (Wdata[31]) + , .WD_30 (Wdata[30]) + , .WD_29 (Wdata[29]) + , .WD_28 (Wdata[28]) + , .WD_27 (Wdata[27]) + , .WD_26 (Wdata[26]) + , .WD_25 (Wdata[25]) + , .WD_24 (Wdata[24]) + , .WD_23 (Wdata[23]) + , .WD_22 (Wdata[22]) + , .WD_21 (Wdata[21]) + , .WD_20 (Wdata[20]) + , .WD_19 (Wdata[19]) + , .WD_18 (Wdata[18]) + , .WD_17 (Wdata[17]) + , .WD_16 (Wdata[16]) + , .WD_15 (Wdata[15]) + , .WD_14 (Wdata[14]) + , .WD_13 (Wdata[13]) + , .WD_12 (Wdata[12]) + , .WD_11 (Wdata[11]) + , .WD_10 (Wdata[10]) + , .WD_9 (Wdata[9]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .RADR_6 (ra_0_0 [6] & !test_mode) + , .RADR_5 (ra_0_0 [5]) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_71 (ramDataOut[71]) + , .RD_70 (ramDataOut[70]) + , .RD_69 (ramDataOut[69]) + , .RD_68 (ramDataOut[68]) + , .RD_67 (ramDataOut[67]) + , .RD_66 (ramDataOut[66]) + , .RD_65 (ramDataOut[65]) + , .RD_64 (ramDataOut[64]) + , .RD_63 (ramDataOut[63]) + , .RD_62 (ramDataOut[62]) + , .RD_61 (ramDataOut[61]) + , .RD_60 (ramDataOut[60]) + , .RD_59 (ramDataOut[59]) + , .RD_58 (ramDataOut[58]) + , .RD_57 (ramDataOut[57]) + , .RD_56 (ramDataOut[56]) + , .RD_55 (ramDataOut[55]) + , .RD_54 (ramDataOut[54]) + , .RD_53 (ramDataOut[53]) + , .RD_52 (ramDataOut[52]) + , .RD_51 (ramDataOut[51]) + , .RD_50 (ramDataOut[50]) + , .RD_49 (ramDataOut[49]) + , .RD_48 (ramDataOut[48]) + , .RD_47 (ramDataOut[47]) + , .RD_46 (ramDataOut[46]) + , .RD_45 (ramDataOut[45]) + , .RD_44 (ramDataOut[44]) + , .RD_43 (ramDataOut[43]) + , .RD_42 (ramDataOut[42]) + , .RD_41 (ramDataOut[41]) + , .RD_40 (ramDataOut[40]) + , .RD_39 (ramDataOut[39]) + , .RD_38 (ramDataOut[38]) + , .RD_37 (ramDataOut[37]) + , .RD_36 (ramDataOut[36]) + , .RD_35 (ramDataOut[35]) + , .RD_34 (ramDataOut[34]) + , .RD_33 (ramDataOut[33]) + , .RD_32 (ramDataOut[32]) + , .RD_31 (ramDataOut[31]) + , .RD_30 (ramDataOut[30]) + , .RD_29 (ramDataOut[29]) + , .RD_28 (ramDataOut[28]) + , .RD_27 (ramDataOut[27]) + , .RD_26 (ramDataOut[26]) + , .RD_25 (ramDataOut[25]) + , .RD_24 (ramDataOut[24]) + , .RD_23 (ramDataOut[23]) + , .RD_22 (ramDataOut[22]) + , .RD_21 (ramDataOut[21]) + , .RD_20 (ramDataOut[20]) + , .RD_19 (ramDataOut[19]) + , .RD_18 (ramDataOut[18]) + , .RD_17 (ramDataOut[17]) + , .RD_16 (ramDataOut[16]) + , .RD_15 (ramDataOut[15]) + , .RD_14 (ramDataOut[14]) + , .RD_13 (ramDataOut[13]) + , .RD_12 (ramDataOut[12]) + , .RD_11 (ramDataOut[11]) + , .RD_10 (ramDataOut[10]) + , .RD_9 (ramDataOut[9]) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .SVOP_2 (svop[2]) + , .SVOP_3 (svop[3]) + , .SVOP_4 (svop[4]) + , .SVOP_5 (svop[5]) + , .SVOP_6 (svop[6]) + , .SVOP_7 (svop[7]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [71:0] ram_r0_OutputMuxDataOut; +//For bitEnd 71, only one piece RAMPDP_80X72_GL_M1_D2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[71:0] or muxed_Di_w0[71:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[71:0] = (ram_bypass) ? muxed_Di_w0[71:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[71:0] = ram_r0_OutputMuxDataOut[71:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [71:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [71:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 71 LSB 0 and total rambit is 72 and dsize is 72 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [71:0]data_regq; +assign Data_reg_r0[71:0] = data_regq[71:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[72-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(72, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[71:0]), .Q(data_regq[71:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9.v new file mode 100644 index 0000000..5152b34 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9.v @@ -0,0 +1,487 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x9.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_80x9 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [8:0] dout; +input [6:0] wa; +input we; +input [8:0] di; +input byp_sel; +input [8:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_80X9_GL_M2_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [6:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [6:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [8:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_6 (.Y(pre_mbist_Wa_w0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_6 (.Z(mbist_Wa_w0[6]), .A1(pre_mbist_Wa_w0_6), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_6 (.Y(pre_mbist_Ra_r0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_6 (.Z(mbist_Ra_r0[6]), .A1(pre_mbist_Ra_r0_6), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_80x9_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_80x9 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[8:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [79:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [8:0] shadow_mem [79:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [8:0] shadow_mem_row0 = shadow_mem[0]; +wire [8:0] shadow_mem_row1 = shadow_mem[1]; +wire [8:0] shadow_mem_row2 = shadow_mem[2]; +wire [8:0] shadow_mem_row3 = shadow_mem[3]; +wire [8:0] shadow_mem_row4 = shadow_mem[4]; +wire [8:0] shadow_mem_row5 = shadow_mem[5]; +wire [8:0] shadow_mem_row6 = shadow_mem[6]; +wire [8:0] shadow_mem_row7 = shadow_mem[7]; +wire [8:0] shadow_mem_row8 = shadow_mem[8]; +wire [8:0] shadow_mem_row9 = shadow_mem[9]; +wire [8:0] shadow_mem_row10 = shadow_mem[10]; +wire [8:0] shadow_mem_row11 = shadow_mem[11]; +wire [8:0] shadow_mem_row12 = shadow_mem[12]; +wire [8:0] shadow_mem_row13 = shadow_mem[13]; +wire [8:0] shadow_mem_row14 = shadow_mem[14]; +wire [8:0] shadow_mem_row15 = shadow_mem[15]; +wire [8:0] shadow_mem_row16 = shadow_mem[16]; +wire [8:0] shadow_mem_row17 = shadow_mem[17]; +wire [8:0] shadow_mem_row18 = shadow_mem[18]; +wire [8:0] shadow_mem_row19 = shadow_mem[19]; +wire [8:0] shadow_mem_row20 = shadow_mem[20]; +wire [8:0] shadow_mem_row21 = shadow_mem[21]; +wire [8:0] shadow_mem_row22 = shadow_mem[22]; +wire [8:0] shadow_mem_row23 = shadow_mem[23]; +wire [8:0] shadow_mem_row24 = shadow_mem[24]; +wire [8:0] shadow_mem_row25 = shadow_mem[25]; +wire [8:0] shadow_mem_row26 = shadow_mem[26]; +wire [8:0] shadow_mem_row27 = shadow_mem[27]; +wire [8:0] shadow_mem_row28 = shadow_mem[28]; +wire [8:0] shadow_mem_row29 = shadow_mem[29]; +wire [8:0] shadow_mem_row30 = shadow_mem[30]; +wire [8:0] shadow_mem_row31 = shadow_mem[31]; +wire [8:0] shadow_mem_row32 = shadow_mem[32]; +wire [8:0] shadow_mem_row33 = shadow_mem[33]; +wire [8:0] shadow_mem_row34 = shadow_mem[34]; +wire [8:0] shadow_mem_row35 = shadow_mem[35]; +wire [8:0] shadow_mem_row36 = shadow_mem[36]; +wire [8:0] shadow_mem_row37 = shadow_mem[37]; +wire [8:0] shadow_mem_row38 = shadow_mem[38]; +wire [8:0] shadow_mem_row39 = shadow_mem[39]; +wire [8:0] shadow_mem_row40 = shadow_mem[40]; +wire [8:0] shadow_mem_row41 = shadow_mem[41]; +wire [8:0] shadow_mem_row42 = shadow_mem[42]; +wire [8:0] shadow_mem_row43 = shadow_mem[43]; +wire [8:0] shadow_mem_row44 = shadow_mem[44]; +wire [8:0] shadow_mem_row45 = shadow_mem[45]; +wire [8:0] shadow_mem_row46 = shadow_mem[46]; +wire [8:0] shadow_mem_row47 = shadow_mem[47]; +wire [8:0] shadow_mem_row48 = shadow_mem[48]; +wire [8:0] shadow_mem_row49 = shadow_mem[49]; +wire [8:0] shadow_mem_row50 = shadow_mem[50]; +wire [8:0] shadow_mem_row51 = shadow_mem[51]; +wire [8:0] shadow_mem_row52 = shadow_mem[52]; +wire [8:0] shadow_mem_row53 = shadow_mem[53]; +wire [8:0] shadow_mem_row54 = shadow_mem[54]; +wire [8:0] shadow_mem_row55 = shadow_mem[55]; +wire [8:0] shadow_mem_row56 = shadow_mem[56]; +wire [8:0] shadow_mem_row57 = shadow_mem[57]; +wire [8:0] shadow_mem_row58 = shadow_mem[58]; +wire [8:0] shadow_mem_row59 = shadow_mem[59]; +wire [8:0] shadow_mem_row60 = shadow_mem[60]; +wire [8:0] shadow_mem_row61 = shadow_mem[61]; +wire [8:0] shadow_mem_row62 = shadow_mem[62]; +wire [8:0] shadow_mem_row63 = shadow_mem[63]; +wire [8:0] shadow_mem_row64 = shadow_mem[64]; +wire [8:0] shadow_mem_row65 = shadow_mem[65]; +wire [8:0] shadow_mem_row66 = shadow_mem[66]; +wire [8:0] shadow_mem_row67 = shadow_mem[67]; +wire [8:0] shadow_mem_row68 = shadow_mem[68]; +wire [8:0] shadow_mem_row69 = shadow_mem[69]; +wire [8:0] shadow_mem_row70 = shadow_mem[70]; +wire [8:0] shadow_mem_row71 = shadow_mem[71]; +wire [8:0] shadow_mem_row72 = shadow_mem[72]; +wire [8:0] shadow_mem_row73 = shadow_mem[73]; +wire [8:0] shadow_mem_row74 = shadow_mem[74]; +wire [8:0] shadow_mem_row75 = shadow_mem[75]; +wire [8:0] shadow_mem_row76 = shadow_mem[76]; +wire [8:0] shadow_mem_row77 = shadow_mem[77]; +wire [8:0] shadow_mem_row78 = shadow_mem[78]; +wire [8:0] shadow_mem_row79 = shadow_mem[79]; +`endif +task init_mem_val; + input [6:0] row; + input [8:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_80X9_GL_M2_E2 +for (row = 0; row < 80; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_80x9.ram_Inst_80X9.mem_write(row - 0, shadow_mem[row][8:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [6:0] wa; + input we; + input [8:0] di; + reg [8:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [8:0] probe_mem_val; +input [6:0] row; +reg [8:0] data; +begin +// probing RAMDP_80X9_GL_M2_E2 + if (row >= 0 && row < 80) data[8:0] = r_nv_ram_rwsthp_80x9.ram_Inst_80X9.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 80; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [8:0] random_num; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 720); + row = random_num / 9; + bitnum = random_num % 9; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [6:0] row; +input [8:0] bitnum; +reg [8:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9.v.vcp new file mode 100644 index 0000000..5152b34 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9.v.vcp @@ -0,0 +1,487 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x9.v +`timescale 1ns / 10ps +module nv_ram_rwsthp_80x9 ( + clk, + ra, + re, + ore, + dout, + wa, + we, + di, + byp_sel, + dbyp, + pwrbus_ram_pd + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list +input clk; +input [6:0] ra; +input re; +input ore; +output [8:0] dout; +input [6:0] wa; +input we; +input [8:0] di; +input byp_sel; +input [8:0] dbyp; +input [31:0] pwrbus_ram_pd; +// This wrapper consists of : 1 Ram cells: RAMDP_80X9_GL_M2_E2 ; +//Wires for Misc Ports +wire DFT_clamp; +//Wires for Mbist Ports +wire [6:0] mbist_Wa_w0; +wire [1:0] mbist_Di_w0; +wire mbist_we_w0; +wire [6:0] mbist_Ra_r0; +// verilint 528 off - Variable set but not used +wire [8:0] mbist_Do_r0_int_net; +// verilint 528 on - Variable set but not used +wire mbist_ce_r0; +wire mbist_en_sync; +//Wires for RamAccess Ports +wire SI; +// verilint 528 off - Variable set but not used +wire SO_int_net; +// verilint 528 on - Variable set but not used +wire shiftDR; +wire updateDR; +wire debug_mode; +//Wires for Misc Ports +wire mbist_ramaccess_rst_; +wire ary_atpg_ctl; +wire write_inh; +wire scan_ramtms; +wire iddq_mode; +wire jtag_readonly_mode; +wire ary_read_inh; +wire test_mode; +wire scan_en; +wire [1:0] svop; +// Use Bbox and clamps to clamp and tie off the DFT signals in the wrapper +NV_BLKBOX_SRC0 UI_enableDFTmode_async_ld_buf (.Y(DFT_clamp)); +wire pre_mbist_Wa_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_0 (.Y(pre_mbist_Wa_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_0 (.Z(mbist_Wa_w0[0]), .A1(pre_mbist_Wa_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_1 (.Y(pre_mbist_Wa_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_1 (.Z(mbist_Wa_w0[1]), .A1(pre_mbist_Wa_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_2 (.Y(pre_mbist_Wa_w0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_2 (.Z(mbist_Wa_w0[2]), .A1(pre_mbist_Wa_w0_2), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_3 (.Y(pre_mbist_Wa_w0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_3 (.Z(mbist_Wa_w0[3]), .A1(pre_mbist_Wa_w0_3), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_4 (.Y(pre_mbist_Wa_w0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_4 (.Z(mbist_Wa_w0[4]), .A1(pre_mbist_Wa_w0_4), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_5 (.Y(pre_mbist_Wa_w0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_5 (.Z(mbist_Wa_w0[5]), .A1(pre_mbist_Wa_w0_5), .A2(DFT_clamp) ); +wire pre_mbist_Wa_w0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Wa_w0_6 (.Y(pre_mbist_Wa_w0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Wa_w0_6 (.Z(mbist_Wa_w0[6]), .A1(pre_mbist_Wa_w0_6), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_0 (.Y(pre_mbist_Di_w0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_0 (.Z(mbist_Di_w0[0]), .A1(pre_mbist_Di_w0_0), .A2(DFT_clamp) ); +wire pre_mbist_Di_w0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Di_w0_1 (.Y(pre_mbist_Di_w0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Di_w0_1 (.Z(mbist_Di_w0[1]), .A1(pre_mbist_Di_w0_1), .A2(DFT_clamp) ); +wire pre_mbist_we_w0; +NV_BLKBOX_SRC0_X testInst_mbist_we_w0 (.Y(pre_mbist_we_w0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_we_w0 (.Z(mbist_we_w0), .A1(pre_mbist_we_w0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_0; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_0 (.Y(pre_mbist_Ra_r0_0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_0 (.Z(mbist_Ra_r0[0]), .A1(pre_mbist_Ra_r0_0), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_1; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_1 (.Y(pre_mbist_Ra_r0_1)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_1 (.Z(mbist_Ra_r0[1]), .A1(pre_mbist_Ra_r0_1), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_2; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_2 (.Y(pre_mbist_Ra_r0_2)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_2 (.Z(mbist_Ra_r0[2]), .A1(pre_mbist_Ra_r0_2), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_3; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_3 (.Y(pre_mbist_Ra_r0_3)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_3 (.Z(mbist_Ra_r0[3]), .A1(pre_mbist_Ra_r0_3), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_4; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_4 (.Y(pre_mbist_Ra_r0_4)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_4 (.Z(mbist_Ra_r0[4]), .A1(pre_mbist_Ra_r0_4), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_5; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_5 (.Y(pre_mbist_Ra_r0_5)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_5 (.Z(mbist_Ra_r0[5]), .A1(pre_mbist_Ra_r0_5), .A2(DFT_clamp) ); +wire pre_mbist_Ra_r0_6; +NV_BLKBOX_SRC0_X testInst_mbist_Ra_r0_6 (.Y(pre_mbist_Ra_r0_6)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_Ra_r0_6 (.Z(mbist_Ra_r0[6]), .A1(pre_mbist_Ra_r0_6), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_0 (.A(mbist_Do_r0_int_net[0])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_1 (.A(mbist_Do_r0_int_net[1])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_2 (.A(mbist_Do_r0_int_net[2])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_3 (.A(mbist_Do_r0_int_net[3])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_4 (.A(mbist_Do_r0_int_net[4])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_5 (.A(mbist_Do_r0_int_net[5])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_6 (.A(mbist_Do_r0_int_net[6])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_7 (.A(mbist_Do_r0_int_net[7])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK testInst_mbist_Do_r0_8 (.A(mbist_Do_r0_int_net[8])); +`endif +wire pre_mbist_ce_r0; +NV_BLKBOX_SRC0_X testInst_mbist_ce_r0 (.Y(pre_mbist_ce_r0)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ce_r0 (.Z(mbist_ce_r0), .A1(pre_mbist_ce_r0), .A2(DFT_clamp) ); +wire pre_mbist_en_sync; +NV_BLKBOX_SRC0_X testInst_mbist_en_sync (.Y(pre_mbist_en_sync)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_en_sync (.Z(mbist_en_sync), .A1(pre_mbist_en_sync), .A2(DFT_clamp) ); +wire pre_SI; +NV_BLKBOX_SRC0_X testInst_SI (.Y(pre_SI)); +AN2D4PO4 UJ_DFTQUALIFIER_SI (.Z(SI), .A1(pre_SI), .A2(DFT_clamp) ); +`ifndef FPGA +NV_BLKBOX_SINK testInst_SO (.A(SO_int_net)); +`endif +wire pre_shiftDR; +NV_BLKBOX_SRC0_X testInst_shiftDR (.Y(pre_shiftDR)); +AN2D4PO4 UJ_DFTQUALIFIER_shiftDR (.Z(shiftDR), .A1(pre_shiftDR), .A2(DFT_clamp) ); +wire pre_updateDR; +NV_BLKBOX_SRC0_X testInst_updateDR (.Y(pre_updateDR)); +AN2D4PO4 UJ_DFTQUALIFIER_updateDR (.Z(updateDR), .A1(pre_updateDR), .A2(DFT_clamp) ); +wire pre_debug_mode; +NV_BLKBOX_SRC0_X testInst_debug_mode (.Y(pre_debug_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_debug_mode (.Z(debug_mode), .A1(pre_debug_mode), .A2(DFT_clamp) ); +wire pre_mbist_ramaccess_rst_; +NV_BLKBOX_SRC0_X testInst_mbist_ramaccess_rst_ (.Y(pre_mbist_ramaccess_rst_)); +AN2D4PO4 UJ_DFTQUALIFIER_mbist_ramaccess_rst_ (.Z(mbist_ramaccess_rst_), .A1(pre_mbist_ramaccess_rst_), .A2(DFT_clamp) ); +wire pre_ary_atpg_ctl; +NV_BLKBOX_SRC0_X testInst_ary_atpg_ctl (.Y(pre_ary_atpg_ctl)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_atpg_ctl (.Z(ary_atpg_ctl), .A1(pre_ary_atpg_ctl), .A2(DFT_clamp) ); +wire pre_write_inh; +NV_BLKBOX_SRC0_X testInst_write_inh (.Y(pre_write_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_write_inh (.Z(write_inh), .A1(pre_write_inh), .A2(DFT_clamp) ); +wire pre_scan_ramtms; +NV_BLKBOX_SRC0_X testInst_scan_ramtms (.Y(pre_scan_ramtms)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_ramtms (.Z(scan_ramtms), .A1(pre_scan_ramtms), .A2(DFT_clamp) ); +wire pre_iddq_mode; +NV_BLKBOX_SRC0_X testInst_iddq_mode (.Y(pre_iddq_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_iddq_mode (.Z(iddq_mode), .A1(pre_iddq_mode), .A2(DFT_clamp) ); +wire pre_jtag_readonly_mode; +NV_BLKBOX_SRC0_X testInst_jtag_readonly_mode (.Y(pre_jtag_readonly_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_jtag_readonly_mode (.Z(jtag_readonly_mode), .A1(pre_jtag_readonly_mode), .A2(DFT_clamp) ); +wire pre_ary_read_inh; +NV_BLKBOX_SRC0_X testInst_ary_read_inh (.Y(pre_ary_read_inh)); +AN2D4PO4 UJ_DFTQUALIFIER_ary_read_inh (.Z(ary_read_inh), .A1(pre_ary_read_inh), .A2(DFT_clamp) ); +wire pre_test_mode; +NV_BLKBOX_SRC0_X testInst_test_mode (.Y(pre_test_mode)); +AN2D4PO4 UJ_DFTQUALIFIER_test_mode (.Z(test_mode), .A1(pre_test_mode), .A2(DFT_clamp) ); +wire pre_scan_en; +NV_BLKBOX_SRC0_X testInst_scan_en (.Y(pre_scan_en)); +AN2D4PO4 UJ_DFTQUALIFIER_scan_en (.Z(scan_en), .A1(pre_scan_en), .A2(DFT_clamp) ); +NV_BLKBOX_SRC0 testInst_svop_0 (.Y(svop[0])); +NV_BLKBOX_SRC0 testInst_svop_1 (.Y(svop[1])); +// Declare the wires for test signals +// Instantiating the internal logic module now +// verilint 402 off - inferred Reset must be a module port +nv_ram_rwsthp_80x9_logic #(FORCE_CONTENTION_ASSERTION_RESET_ACTIVE) r_nv_ram_rwsthp_80x9 ( + .SI(SI), .SO_int_net(SO_int_net), + .ary_atpg_ctl(ary_atpg_ctl), + .ary_read_inh(ary_read_inh), .byp_sel(byp_sel), + .clk(clk), .dbyp(dbyp), .debug_mode(debug_mode), + .di(di), .dout(dout), .iddq_mode(iddq_mode), + .jtag_readonly_mode(jtag_readonly_mode), + .mbist_Di_w0(mbist_Di_w0), + .mbist_Do_r0_int_net(mbist_Do_r0_int_net), + .mbist_Ra_r0(mbist_Ra_r0), .mbist_Wa_w0(mbist_Wa_w0), + .mbist_ce_r0(mbist_ce_r0), + .mbist_en_sync(mbist_en_sync), + .mbist_ramaccess_rst_(mbist_ramaccess_rst_), + .mbist_we_w0(mbist_we_w0), .ore(ore), + .pwrbus_ram_pd(pwrbus_ram_pd), .ra(ra), .re(re), + .scan_en(scan_en), .scan_ramtms(scan_ramtms), + .shiftDR(shiftDR), .svop(svop), .test_mode(test_mode), + .updateDR(updateDR), .wa(wa), .we(we), + .write_inh(write_inh) ); +// verilint 402 on - inferred Reset must be a module port +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +`ifndef SYNTHESIS +task arrangement (output integer arrangment_string[8:0]); + begin + arrangment_string[0] = 0 ; + arrangment_string[1] = 1 ; + arrangment_string[2] = 2 ; + arrangment_string[3] = 3 ; + arrangment_string[4] = 4 ; + arrangment_string[5] = 5 ; + arrangment_string[6] = 6 ; + arrangment_string[7] = 7 ; + arrangment_string[8] = 8 ; + end +endtask +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +// Bit vector indicating which shadow addresses have been written +reg [79:0] shadow_written = 'b0; +// Shadow ram array used to store initialization values +reg [8:0] shadow_mem [79:0]; +`ifdef NV_RAM_EXPAND_ARRAY +wire [8:0] shadow_mem_row0 = shadow_mem[0]; +wire [8:0] shadow_mem_row1 = shadow_mem[1]; +wire [8:0] shadow_mem_row2 = shadow_mem[2]; +wire [8:0] shadow_mem_row3 = shadow_mem[3]; +wire [8:0] shadow_mem_row4 = shadow_mem[4]; +wire [8:0] shadow_mem_row5 = shadow_mem[5]; +wire [8:0] shadow_mem_row6 = shadow_mem[6]; +wire [8:0] shadow_mem_row7 = shadow_mem[7]; +wire [8:0] shadow_mem_row8 = shadow_mem[8]; +wire [8:0] shadow_mem_row9 = shadow_mem[9]; +wire [8:0] shadow_mem_row10 = shadow_mem[10]; +wire [8:0] shadow_mem_row11 = shadow_mem[11]; +wire [8:0] shadow_mem_row12 = shadow_mem[12]; +wire [8:0] shadow_mem_row13 = shadow_mem[13]; +wire [8:0] shadow_mem_row14 = shadow_mem[14]; +wire [8:0] shadow_mem_row15 = shadow_mem[15]; +wire [8:0] shadow_mem_row16 = shadow_mem[16]; +wire [8:0] shadow_mem_row17 = shadow_mem[17]; +wire [8:0] shadow_mem_row18 = shadow_mem[18]; +wire [8:0] shadow_mem_row19 = shadow_mem[19]; +wire [8:0] shadow_mem_row20 = shadow_mem[20]; +wire [8:0] shadow_mem_row21 = shadow_mem[21]; +wire [8:0] shadow_mem_row22 = shadow_mem[22]; +wire [8:0] shadow_mem_row23 = shadow_mem[23]; +wire [8:0] shadow_mem_row24 = shadow_mem[24]; +wire [8:0] shadow_mem_row25 = shadow_mem[25]; +wire [8:0] shadow_mem_row26 = shadow_mem[26]; +wire [8:0] shadow_mem_row27 = shadow_mem[27]; +wire [8:0] shadow_mem_row28 = shadow_mem[28]; +wire [8:0] shadow_mem_row29 = shadow_mem[29]; +wire [8:0] shadow_mem_row30 = shadow_mem[30]; +wire [8:0] shadow_mem_row31 = shadow_mem[31]; +wire [8:0] shadow_mem_row32 = shadow_mem[32]; +wire [8:0] shadow_mem_row33 = shadow_mem[33]; +wire [8:0] shadow_mem_row34 = shadow_mem[34]; +wire [8:0] shadow_mem_row35 = shadow_mem[35]; +wire [8:0] shadow_mem_row36 = shadow_mem[36]; +wire [8:0] shadow_mem_row37 = shadow_mem[37]; +wire [8:0] shadow_mem_row38 = shadow_mem[38]; +wire [8:0] shadow_mem_row39 = shadow_mem[39]; +wire [8:0] shadow_mem_row40 = shadow_mem[40]; +wire [8:0] shadow_mem_row41 = shadow_mem[41]; +wire [8:0] shadow_mem_row42 = shadow_mem[42]; +wire [8:0] shadow_mem_row43 = shadow_mem[43]; +wire [8:0] shadow_mem_row44 = shadow_mem[44]; +wire [8:0] shadow_mem_row45 = shadow_mem[45]; +wire [8:0] shadow_mem_row46 = shadow_mem[46]; +wire [8:0] shadow_mem_row47 = shadow_mem[47]; +wire [8:0] shadow_mem_row48 = shadow_mem[48]; +wire [8:0] shadow_mem_row49 = shadow_mem[49]; +wire [8:0] shadow_mem_row50 = shadow_mem[50]; +wire [8:0] shadow_mem_row51 = shadow_mem[51]; +wire [8:0] shadow_mem_row52 = shadow_mem[52]; +wire [8:0] shadow_mem_row53 = shadow_mem[53]; +wire [8:0] shadow_mem_row54 = shadow_mem[54]; +wire [8:0] shadow_mem_row55 = shadow_mem[55]; +wire [8:0] shadow_mem_row56 = shadow_mem[56]; +wire [8:0] shadow_mem_row57 = shadow_mem[57]; +wire [8:0] shadow_mem_row58 = shadow_mem[58]; +wire [8:0] shadow_mem_row59 = shadow_mem[59]; +wire [8:0] shadow_mem_row60 = shadow_mem[60]; +wire [8:0] shadow_mem_row61 = shadow_mem[61]; +wire [8:0] shadow_mem_row62 = shadow_mem[62]; +wire [8:0] shadow_mem_row63 = shadow_mem[63]; +wire [8:0] shadow_mem_row64 = shadow_mem[64]; +wire [8:0] shadow_mem_row65 = shadow_mem[65]; +wire [8:0] shadow_mem_row66 = shadow_mem[66]; +wire [8:0] shadow_mem_row67 = shadow_mem[67]; +wire [8:0] shadow_mem_row68 = shadow_mem[68]; +wire [8:0] shadow_mem_row69 = shadow_mem[69]; +wire [8:0] shadow_mem_row70 = shadow_mem[70]; +wire [8:0] shadow_mem_row71 = shadow_mem[71]; +wire [8:0] shadow_mem_row72 = shadow_mem[72]; +wire [8:0] shadow_mem_row73 = shadow_mem[73]; +wire [8:0] shadow_mem_row74 = shadow_mem[74]; +wire [8:0] shadow_mem_row75 = shadow_mem[75]; +wire [8:0] shadow_mem_row76 = shadow_mem[76]; +wire [8:0] shadow_mem_row77 = shadow_mem[77]; +wire [8:0] shadow_mem_row78 = shadow_mem[78]; +wire [8:0] shadow_mem_row79 = shadow_mem[79]; +`endif +task init_mem_val; + input [6:0] row; + input [8:0] data; + begin + shadow_mem[row] = data; + shadow_written[row] = 1'b1; + end +endtask +task init_mem_commit; +integer row; +begin +// initializing RAMDP_80X9_GL_M2_E2 +for (row = 0; row < 80; row = row + 1) + if (shadow_written[row]) r_nv_ram_rwsthp_80x9.ram_Inst_80X9.mem_write(row - 0, shadow_mem[row][8:0]); +shadow_written = 'b0; +end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +task do_write; //(wa, we, di); + input [6:0] wa; + input we; + input [8:0] di; + reg [8:0] d; + begin + d = probe_mem_val(wa); + d = (we ? di : d); + init_mem_val(wa,d); + end +endtask +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef MEM_REG_NAME + `define MEM_REG_NAME MX.mem +`endif +function [8:0] probe_mem_val; +input [6:0] row; +reg [8:0] data; +begin +// probing RAMDP_80X9_GL_M2_E2 + if (row >= 0 && row < 80) data[8:0] = r_nv_ram_rwsthp_80x9.ram_Inst_80X9.mem_read(row - 0); + probe_mem_val = data; +end +endfunction +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_CLEAR_MEM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +reg disable_clear_mem = 0; +task clear_mem; +integer i; +begin + if (!disable_clear_mem) + begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'bx); + end + init_mem_commit(); + end +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_ZERO_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +task init_mem_zero; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + init_mem_val(i, 'b0); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_VAL_TASKS +`ifndef NO_INIT_MEM_FROM_FILE_TASK +task init_mem_from_file; +input string init_file; +integer i; +begin + $readmemh(init_file,shadow_mem); + for (i = 0; i < 80; i = i + 1) + begin + shadow_written[i] = 1'b1; + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_INIT_MEM_RANDOM_TASK +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rf0 (); +task init_mem_random; +reg [8:0] random_num; +integer i; +begin + for (i = 0; i < 80; i = i + 1) + begin + random_num = {rf0.rollpli(0,32'hffffffff)}; + init_mem_val(i, random_num); + end + init_mem_commit(); +end +endtask +`endif +`endif +`endif +`ifndef SYNTHESIS +`ifndef NO_FLIP_TASKS +`ifndef NO_INIT_MEM_VAL_TASKS +RANDFUNC rflip (); +task random_flip; +integer random_num; +integer row; +integer bitnum; +begin + random_num = rflip.rollpli(0, 720); + row = random_num / 9; + bitnum = random_num % 9; + target_flip(row, bitnum); +end +endtask +task target_flip; +input [6:0] row; +input [8:0] bitnum; +reg [8:0] data; +begin + if(!$test$plusargs("no_display_target_flips")) + $display("%m: flipping row %d bit %d at time %t", row, bitnum, $time); + data = probe_mem_val(row); + data[bitnum] = ~data[bitnum]; + init_mem_val(row, data); + init_mem_commit(); +end +endtask +`endif +`endif +`endif +// The main module is done +endmodule +//******************************************************************************** diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9_logic.v b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9_logic.v new file mode 100644 index 0000000..01ca076 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9_logic.v @@ -0,0 +1,570 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x9_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_80x9_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [8:0] dbyp; +input debug_mode; +input [8:0] di; +output [8:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [8:0] mbist_Do_r0_int_net; +input [6:0] mbist_Ra_r0; +input [6:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [6:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [6:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [6:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [8:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [8:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [8:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [8:0] pre_muxed_Di_w0; +wire [8:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[8:0]; +assign pre_muxed_Di_w0_B = {mbist_Di_w0[0], {4{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {9{`tick_x_or_0}}; + endcase +reg [8:0] muxed_Di_w0; +wire [8:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[8:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {9{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [6:0] pre_Wa_reg_w0; +reg [6:0] Wa_reg_w0; +wire [6:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {7{`tick_x_or_0}}; +endcase +reg [6:0] muxed_Wa_w0; +wire [6:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {7{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [6:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [6:0] pre_Ra_reg_r0; +reg [6:0] Ra_reg_r0; +wire [6:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {7{`tick_x_or_0}}; +endcase +wire [6:0] D_Ra_reg_r0; +reg [6:0] muxed_Ra_r0; +wire [6:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {7{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [6:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_80X9_GL_M2_E2 (RamCell) +// Covers Addresses from 0 to 79 Addressrange: [6:0] +// Data Bit range: [8:0] (9 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [6:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[6:0]; +// Write Data in bus +wire [8:0] Wdata; +assign Wdata = muxed_Di_w0[8:0]; +assign we_0_0 = we; +// Read Address bus +wire [6:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[6:0]; +// Read DataOut bus +wire [8:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_80X9_GL_M2_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [8:0] ramDataOut; +assign dout_0_0[8:0] = ramDataOut[8:0]; +RAMDP_80X9_GL_M2_E2 ram_Inst_80X9 ( + .CLK_W (gated_clk_core) + , .WADR_6 (wa_0_0[6]) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_6 (ra_0_0 [6] & !test_mode) + , .RADR_5 (ra_0_0 [5]) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [8:0] ram_r0_OutputMuxDataOut; +//For bitEnd 8, only one piece RAMDP_80X9_GL_M2_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[8:0] or muxed_Di_w0[8:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[8:0] = (ram_bypass) ? muxed_Di_w0[8:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[8:0] = ram_r0_OutputMuxDataOut[8:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [8:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [8:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 8 LSB 0 and total rambit is 9 and dsize is 9 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [8:0]data_regq; +assign Data_reg_r0[8:0] = data_regq[8:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[9-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(9, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[8:0]), .Q(data_regq[8:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9_logic.v.vcp b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9_logic.v.vcp new file mode 100644 index 0000000..01ca076 --- /dev/null +++ b/designs/src/NVDLA/vmod/rams/synth/nv_ram_rwsthp_80x9_logic.v.vcp @@ -0,0 +1,570 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_ram_rwsthp_80x9_logic.v +`ifdef _SIMULATE_X_VH_ +`else +`ifndef SYNTHESIS +`define tick_x_or_0 1'bx +`define tick_x_or_1 1'bx +`else +`define tick_x_or_0 1'b0 +`define tick_x_or_1 1'b1 +`endif +`endif +// verilint 549 off - async flop inferred +// verilint 446 off - reading from output port +// verilint 389 off - multiple clocks in module +// verilint 287 off - unconnected ports +// verilint 401 off - Clock is not an input to the module (we use gated clk) +// verilint 257 off - delays ignored by synth tools +// verilint 240 off - Unused input +// verilint 542 off - enabled flop inferred +// verilint 210 off - too few module ports +// verilint 280 off - delay in non-blocking assignment +// verilint 332 off - not all possible cases covered, but default case exists +// verilint 390 off - multiple resets in this module +// verilint 396 off - flop w/o async reset +// verilint 69 off - case without default, all cases covered +// verilint 34 off - unused macro +// verilint 528 off - variable set but not used +// verilint 530 off - flop inferred +// verilint 550 off - mux inferred +// verilint 113 off - multiple drivers to flop +// leda ELB072 off +`timescale 1ns / 10ps +`define TSMC_CM_UNIT_DELAY +`define TSMC_CM_NO_WARNING +module nv_ram_rwsthp_80x9_logic ( + SI, + SO_int_net, + ary_atpg_ctl, + ary_read_inh, + byp_sel, + clk, + dbyp, + debug_mode, + di, + dout, + iddq_mode, + jtag_readonly_mode, + mbist_Di_w0, + mbist_Do_r0_int_net, + mbist_Ra_r0, + mbist_Wa_w0, + mbist_ce_r0, + mbist_en_sync, + mbist_ramaccess_rst_, + mbist_we_w0, + ore, + pwrbus_ram_pd, + ra, + re, + scan_en, + scan_ramtms, + shiftDR, + svop, + test_mode, + updateDR, + wa, + we, + write_inh + ); +parameter FORCE_CONTENTION_ASSERTION_RESET_ACTIVE=1'b0; +// port list for submodule +input SI; +output SO_int_net; +input ary_atpg_ctl; +input ary_read_inh; +input byp_sel; +input clk; +input [8:0] dbyp; +input debug_mode; +input [8:0] di; +output [8:0] dout; +input iddq_mode; +input jtag_readonly_mode; +input [1:0] mbist_Di_w0; +output [8:0] mbist_Do_r0_int_net; +input [6:0] mbist_Ra_r0; +input [6:0] mbist_Wa_w0; +input mbist_ce_r0; +input mbist_en_sync; +input mbist_ramaccess_rst_; +input mbist_we_w0; +input ore; +input [31:0] pwrbus_ram_pd; +input [6:0] ra; +input re; +input scan_en; +input scan_ramtms; +input shiftDR; +input [1:0] svop; +input test_mode; +input updateDR; +input [6:0] wa; +input we; +input write_inh; +wire [7:0] sleep_en = pwrbus_ram_pd[7:0]; +wire ret_en = pwrbus_ram_pd[8]; +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_9 (.A(pwrbus_ram_pd[9])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_10 (.A(pwrbus_ram_pd[10])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_11 (.A(pwrbus_ram_pd[11])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_12 (.A(pwrbus_ram_pd[12])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_13 (.A(pwrbus_ram_pd[13])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_14 (.A(pwrbus_ram_pd[14])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_15 (.A(pwrbus_ram_pd[15])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_16 (.A(pwrbus_ram_pd[16])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_17 (.A(pwrbus_ram_pd[17])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_18 (.A(pwrbus_ram_pd[18])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_19 (.A(pwrbus_ram_pd[19])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_20 (.A(pwrbus_ram_pd[20])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_21 (.A(pwrbus_ram_pd[21])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_22 (.A(pwrbus_ram_pd[22])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_23 (.A(pwrbus_ram_pd[23])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_24 (.A(pwrbus_ram_pd[24])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_25 (.A(pwrbus_ram_pd[25])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_26 (.A(pwrbus_ram_pd[26])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_27 (.A(pwrbus_ram_pd[27])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_28 (.A(pwrbus_ram_pd[28])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_29 (.A(pwrbus_ram_pd[29])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_30 (.A(pwrbus_ram_pd[30])); +`endif +`ifndef FPGA +NV_BLKBOX_SINK UJ_BBOX2UNIT_UNUSED_pwrbus_31 (.A(pwrbus_ram_pd[31])); +`endif +wire wthru; +reg wthru_en; +// DFT ATPG signals +wire ram_bypass = (scan_ramtms | ary_read_inh); +wire la_bist_clkw0; +wire la_bist_clkr0; +assign la_bist_clkr0 = la_bist_clkw0; +wire updateDR_sync; +sync2d_c_pp updateDR_synchronizer (.d(updateDR), .clk(la_bist_clkw0), .q(updateDR_sync), .clr_(mbist_ramaccess_rst_)); +reg updateDR_sync_1p; +always @(posedge la_bist_clkr0 or negedge mbist_ramaccess_rst_) begin + if (!mbist_ramaccess_rst_) + updateDR_sync_1p <= 1'b0; + else + updateDR_sync_1p <= updateDR_sync; +end +wire debug_mode_sync; +wire dft_rst_gated_clk; +CKLNQD12PO4 CLK_GATE_clk (.Q(dft_rst_gated_clk), .CP(clk), .E(mbist_ramaccess_rst_), .TE(scan_en)); +sync2d_c_pp debug_mode_synchronizer (.d(debug_mode), .clk(dft_rst_gated_clk), .q(debug_mode_sync), .clr_(mbist_ramaccess_rst_)); +reg [6:0] Ra_array_reg_r0; +wire mbist_en_r; +// hardcode mbist_en_r stdcell flop to avoid x bash recoverability issue described in bug 1803479 comment #7 +p_SDFCNQD1PO4 mbist_en_flop(.D(mbist_en_sync), .CP(dft_rst_gated_clk), .Q(mbist_en_r), .CDN(mbist_ramaccess_rst_)); +// Declare the Data_reg signal beforehand +wire [8:0] Data_reg_r0; +// Data out bus for read port r0 for Output Mux +wire [8:0] r0_OutputMuxDataOut; +CKLNQD12PO4 UJ_la_bist_clkw0_gate (.Q(la_bist_clkw0), .CP(clk), .E(mbist_en_r | debug_mode_sync), .TE(scan_en)); +assign wthru = ((ra == wa) & re & we & !debug_mode_sync & !mbist_en_r); +// verilint 548 off - Synchronous flipflop is inferred +always @(posedge clk) begin + wthru_en <= (wthru | (wthru_en & !re)) & !debug_mode_sync & !mbist_en_r; +end +// verilint 548 on +reg [8:0] wthru_di; +always @(posedge clk) begin + if (wthru) + wthru_di <= di; +end +// Write enable bus +wire we_0_0; +// Read enable bus +wire re_0_0; +// start of predeclareNvregSignals +wire ctx_ctrl_we; +wire clk_en_core = (re_0_0 | (|we_0_0)); +wire gated_clk_core; +CKLNQD12PO4 UJ_clk_gate_core (.Q(gated_clk_core), .CP(clk), .E(clk_en_core), .TE(1'b0 | mbist_en_r | debug_mode_sync | scan_en)); +wire shiftDR_en; +reg [8:0] pre_muxed_Di_w0; +wire [8:0] pre_muxed_Di_w0_A, pre_muxed_Di_w0_B; +wire pre_muxed_Di_w0_S; +assign pre_muxed_Di_w0_S = !debug_mode_sync; +assign pre_muxed_Di_w0_A = Data_reg_r0[8:0]; +assign pre_muxed_Di_w0_B = {mbist_Di_w0[0], {4{mbist_Di_w0}}}; +always @(pre_muxed_Di_w0_S or pre_muxed_Di_w0_A or pre_muxed_Di_w0_B) + case(pre_muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : pre_muxed_Di_w0 = pre_muxed_Di_w0_A; + 1'b1 : pre_muxed_Di_w0 = pre_muxed_Di_w0_B; + default : pre_muxed_Di_w0 = {9{`tick_x_or_0}}; + endcase +reg [8:0] muxed_Di_w0; +wire [8:0] muxed_Di_w0_A, muxed_Di_w0_B; +assign muxed_Di_w0_A = {di[8:0]}; +assign muxed_Di_w0_B = pre_muxed_Di_w0; +wire muxed_Di_w0_S = debug_mode_sync | mbist_en_r; +always @(muxed_Di_w0_S or muxed_Di_w0_A or muxed_Di_w0_B) + case(muxed_Di_w0_S) // synopsys infer_mux + 1'b0 : muxed_Di_w0 = muxed_Di_w0_A; + 1'b1 : muxed_Di_w0 = muxed_Di_w0_B; + default : muxed_Di_w0 = {9{`tick_x_or_0}}; + endcase +wire posedge_updateDR_sync = updateDR_sync & !updateDR_sync_1p; +wire access_en_w = posedge_updateDR_sync; +// ATPG logic: capture for non-data regs +wire dft_capdr_w = ary_atpg_ctl; +wire [6:0] pre_Wa_reg_w0; +reg [6:0] Wa_reg_w0; +wire [6:0] Wa_reg_w0_A, Wa_reg_w0_B; +wire Wa_reg_w0_S; +assign Wa_reg_w0_S = (!debug_mode_sync); +assign Wa_reg_w0_A = pre_Wa_reg_w0; +assign Wa_reg_w0_B = mbist_Wa_w0; +always @(Wa_reg_w0_S or Wa_reg_w0_A or Wa_reg_w0_B) +case(Wa_reg_w0_S) // synopsys infer_mux + 1'b0 : Wa_reg_w0 = Wa_reg_w0_A; + 1'b1 : Wa_reg_w0 = Wa_reg_w0_B; + default : Wa_reg_w0 = {7{`tick_x_or_0}}; +endcase +reg [6:0] muxed_Wa_w0; +wire [6:0] muxed_Wa_w0_A, muxed_Wa_w0_B; +wire muxed_Wa_w0_S; +assign muxed_Wa_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_Wa_w0_A = wa; +assign muxed_Wa_w0_B = Wa_reg_w0; +always @(muxed_Wa_w0_S or muxed_Wa_w0_A or muxed_Wa_w0_B) + case(muxed_Wa_w0_S) // synopsys infer_mux + 1'b0 : muxed_Wa_w0 = muxed_Wa_w0_A; + 1'b1 : muxed_Wa_w0 = muxed_Wa_w0_B; + default : muxed_Wa_w0 = {7{`tick_x_or_0}}; + endcase +// testInst_*reg* for address and enable capture the signals going into RAM instance input +// 4.2.3.1 of bob's doc +wire Wa_reg_SO_w0; +wire [6:0]wadr_q; +assign pre_Wa_reg_w0 = wadr_q ; +wire we_reg_SO_w0; +wire re_reg_SO_r0; +wire we_reg_w0; +wire pre_we_w0; +assign pre_we_w0 = debug_mode_sync ? + ({1{posedge_updateDR_sync}} & we_reg_w0) : + {1{(mbist_en_r & mbist_we_w0)}}; +reg muxed_we_w0; +wire muxed_we_w0_A, muxed_we_w0_B; +wire muxed_we_w0_S; +assign muxed_we_w0_S = debug_mode_sync | mbist_en_r; +assign muxed_we_w0_A = we_0_0; +assign muxed_we_w0_B = pre_we_w0; +always @(muxed_we_w0_S or muxed_we_w0_A or muxed_we_w0_B) +case(muxed_we_w0_S) // synopsys infer_mux + 1'b0 : muxed_we_w0 = muxed_we_w0_A; + 1'b1 : muxed_we_w0 = muxed_we_w0_B; + default : muxed_we_w0 = {1{`tick_x_or_0}}; +endcase +wire we_q; +assign we_reg_w0 = we_q ; +// ATPG logic: capture for non-data regs +wire dft_capdr_r = ary_atpg_ctl; +// ATPG logic: capture for non-data regs +wire [6:0] pre_Ra_reg_r0; +reg [6:0] Ra_reg_r0; +wire [6:0] Ra_reg_r0_A, Ra_reg_r0_B; +wire Ra_reg_r0_S; +assign Ra_reg_r0_S = (!debug_mode_sync); +assign Ra_reg_r0_A = pre_Ra_reg_r0; +assign Ra_reg_r0_B = mbist_Ra_r0; +always @(Ra_reg_r0_S or Ra_reg_r0_A or Ra_reg_r0_B) +case(Ra_reg_r0_S) // synopsys infer_mux + 1'b0 : Ra_reg_r0 = Ra_reg_r0_A; + 1'b1 : Ra_reg_r0 = Ra_reg_r0_B; + default : Ra_reg_r0 = {7{`tick_x_or_0}}; +endcase +wire [6:0] D_Ra_reg_r0; +reg [6:0] muxed_Ra_r0; +wire [6:0] muxed_Ra_r0_A, muxed_Ra_r0_B; +wire muxed_Ra_r0_S; +assign muxed_Ra_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_Ra_r0_A = ra; +assign muxed_Ra_r0_B = Ra_reg_r0; +always @(muxed_Ra_r0_S or muxed_Ra_r0_A or muxed_Ra_r0_B) +case(muxed_Ra_r0_S) // synopsys infer_mux + 1'b0 : muxed_Ra_r0 = muxed_Ra_r0_A; + 1'b1 : muxed_Ra_r0 = muxed_Ra_r0_B; + default : muxed_Ra_r0 = {7{`tick_x_or_0}}; +endcase +assign D_Ra_reg_r0 = muxed_Ra_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire Ra_reg_SO_r0; +wire [6:0]radr_q; +assign pre_Ra_reg_r0 = radr_q ; +wire re_reg_r0; +wire access_en_r = posedge_updateDR_sync & re_reg_r0; +reg access_en_r_1p; +always @(posedge la_bist_clkw0 or negedge mbist_ramaccess_rst_) + if (!mbist_ramaccess_rst_) + access_en_r_1p <= 1'b0; + else + access_en_r_1p <= access_en_r; +wire pre_re_r0; +assign pre_re_r0 = (debug_mode_sync) ? + (posedge_updateDR_sync & re_reg_r0) : + (mbist_en_r & mbist_ce_r0); +reg muxed_re_r0; +wire muxed_re_r0_A, muxed_re_r0_B; +wire muxed_re_r0_S; +assign muxed_re_r0_S = debug_mode_sync | mbist_en_r; +assign muxed_re_r0_A = re; +assign muxed_re_r0_B = pre_re_r0; +always @(muxed_re_r0_S or muxed_re_r0_A or muxed_re_r0_B) +case(muxed_re_r0_S) // synopsys infer_mux + 1'b0 : muxed_re_r0 = muxed_re_r0_A; + 1'b1 : muxed_re_r0 = muxed_re_r0_B; + default : muxed_re_r0 = `tick_x_or_0; +endcase +wire re_q; +assign re_reg_r0 = re_q ; +// ------------------ START PIECE ---------------------------------- +// Suffix : Piece RAMDP_80X9_GL_M2_E2 (RamCell) +// Covers Addresses from 0 to 79 Addressrange: [6:0] +// Data Bit range: [8:0] (9 bits) +// Enables: 1 Enable range: +// Write Address bus +wire [6:0] wa_0_0; +assign wa_0_0 = muxed_Wa_w0[6:0]; +// Write Data in bus +wire [8:0] Wdata; +assign Wdata = muxed_Di_w0[8:0]; +assign we_0_0 = we; +// Read Address bus +wire [6:0] ra_0_0; +assign ra_0_0 = muxed_Ra_r0[6:0]; +// Read DataOut bus +wire [8:0] dout_0_0; +assign re_0_0 = re; +// Doing Global setup for all ram pieces +// Following control signals are shared by all ram pieces +// Done global setup for ram pieces +//----------------------------------------------------------- +// Declare the Bist logic\n +// Declare some mbist control signals +//-------------------------------------------------- +// Vlint doesn't understand paramaters? +// verilint 110 off - Incompatible width +//-------------------------------------------------- +// Turn the verilint warnings on +// verilint 110 on - Incompatible width +// ----------------- begin Ram Cell RAMDP_80X9_GL_M2_E2 ------------- +// Write Port Stuff ----- +// Declare the Write address bus +wire web = ~(|muxed_we_w0) | write_inh; +// Read Port Stuff ----- +// Declare the Read address bus +// Read enable +wire piece_re = muxed_re_r0 | ( scan_en & jtag_readonly_mode ); +wire reb = !piece_re; +// Declare the ramOutData which connects to the ram directly +wire [8:0] ramDataOut; +assign dout_0_0[8:0] = ramDataOut[8:0]; +RAMDP_80X9_GL_M2_E2 ram_Inst_80X9 ( + .CLK_W (gated_clk_core) + , .WADR_6 (wa_0_0[6]) + , .WADR_5 (wa_0_0[5]) + , .WADR_4 (wa_0_0[4]) + , .WADR_3 (wa_0_0[3]) + , .WADR_2 (wa_0_0[2]) + , .WADR_1 (wa_0_0[1]) + , .WADR_0 (wa_0_0[0]) + , .WD_8 (Wdata[8]) + , .WD_7 (Wdata[7]) + , .WD_6 (Wdata[6]) + , .WD_5 (Wdata[5]) + , .WD_4 (Wdata[4]) + , .WD_3 (Wdata[3]) + , .WD_2 (Wdata[2]) + , .WD_1 (Wdata[1]) + , .WD_0 (Wdata[0]) + , .WE (!web) + , .CLK_R (gated_clk_core) + , .RADR_6 (ra_0_0 [6] & !test_mode) + , .RADR_5 (ra_0_0 [5]) + , .RADR_4 (ra_0_0 [4]) + , .RADR_3 (ra_0_0 [3]) + , .RADR_2 (ra_0_0 [2]) + , .RADR_1 (ra_0_0 [1]) + , .RADR_0 (ra_0_0 [0]) + , .RE (!reb) + , .RD_8 (ramDataOut[8]) + , .RD_7 (ramDataOut[7]) + , .RD_6 (ramDataOut[6]) + , .RD_5 (ramDataOut[5]) + , .RD_4 (ramDataOut[4]) + , .RD_3 (ramDataOut[3]) + , .RD_2 (ramDataOut[2]) + , .RD_1 (ramDataOut[1]) + , .RD_0 (ramDataOut[0]) + , .SVOP_0 (svop[0]) + , .SVOP_1 (svop[1]) + , .IDDQ (iddq_mode) + , .SLEEP_EN_0 (sleep_en[0]) + , .SLEEP_EN_1 (sleep_en[1]) + , .SLEEP_EN_2 (sleep_en[2]) + , .SLEEP_EN_3 (sleep_en[3]) + , .SLEEP_EN_4 (sleep_en[4]) + , .SLEEP_EN_5 (sleep_en[5]) + , .SLEEP_EN_6 (sleep_en[6]) + , .SLEEP_EN_7 (sleep_en[7]) + , .RET_EN (ret_en) + ); +//-------------------------------------------------- +// THIS IS ONLY FOR TESTING. REMOVE THIS LATER +// verilint 97 on - undefined instance errors turned on +//-------------------------------------------------- +// --------------------------------------------- +// Declare the interface wires for Output Mux logic +// verilint 552 off - Different bits of a net are driven in different blocks (harmless, +// but some synthesis tools generate a warning for this) +reg [8:0] ram_r0_OutputMuxDataOut; +//For bitEnd 8, only one piece RAMDP_80X9_GL_M2_E2 in the column. +// verilint 17 off - Range (rather than full vector) in the sensitivity list +always @(dout_0_0[8:0] or muxed_Di_w0[8:0] or ram_bypass) +begin + ram_r0_OutputMuxDataOut[8:0] = (ram_bypass) ? muxed_Di_w0[8:0]: dout_0_0; +end +assign r0_OutputMuxDataOut[8:0] = ram_r0_OutputMuxDataOut[8:0]; +// verilint 17 on - Range (rather than full vector) in the sensitivity list +// --------------------- Output Mbist Interface logic ------------- +wire [8:0] functional_byp_muxed_r0_OutputMuxDataOut = (byp_sel & !debug_mode_sync & !mbist_en_r) ? dbyp : wthru_di; +wire [8:0] muxed_r0_OutputMuxDataOut; +assign muxed_r0_OutputMuxDataOut = (!mbist_en_r & !debug_mode_sync & wthru_en | (byp_sel & !debug_mode_sync & !mbist_en_r)) ? functional_byp_muxed_r0_OutputMuxDataOut : r0_OutputMuxDataOut; +reg mbist_ce_r0_1p; +always @(posedge la_bist_clkw0) mbist_ce_r0_1p <= mbist_ce_r0; +wire captureDR_r0 = dft_capdr_r | ((((ore)) & !mbist_en_r & !debug_mode_sync) || ( debug_mode_sync ? (1'b1& (access_en_r_1p)) : ((mbist_en_r & (mbist_ce_r0_1p) & !1'b0)))); +////MSB 8 LSB 0 and total rambit is 9 and dsize is 9 +wire Data_reg_SO_r0; +// verilint 110 off - Incompatible width +// verilint 630 off - Port connected to a NULL expression +// These are used for registering Ra in case of Latch arrays as well (i.e. +// used in functional path as well) +wire [8:0]data_regq; +assign Data_reg_r0[8:0] = data_regq[8:0] ; +// verilint 110 on - Incompatible width +// verilint 630 on - Port connected to a NULL expression +assign dout = Data_reg_r0; +assign mbist_Do_r0_int_net = Data_reg_r0[9-1:0]; +// Declare the SO which goes out finally +`ifndef EMU +`ifndef FPGA +`define NO_EMU_NO_FPGA +// lock-up latch for ram_access SO +LNQD1PO4 testInst_ram_access_lockup ( + .Q(SO_int_net), + .D(Data_reg_SO_r0), + .EN(la_bist_clkw0)); +`endif +`endif +`ifndef NO_EMU_NO_FPGA +// no latch allow during emulation synthesis +assign SO_int_net = Data_reg_SO_r0; +`endif +// Ram access scan chain +wire gated_clk_jtag_Wa_reg_w0; +CKLNQD12PO4 UJ_clk_jtag_Wa_reg_w0 (.Q(gated_clk_jtag_Wa_reg_w0), .CP(clk), .E(debug_mode_sync ? (( 1'b0 | shiftDR ) ) : (1'b0 | 1'b0 | mbist_en_r | ( 1'b0 | ary_atpg_ctl) ) ), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Wa_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Wa_w0), .Q(wadr_q), + .scanin(SI), .scanout(Wa_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_we_reg_w0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_we_w0), .Q(we_q), + .scanin(Wa_reg_SO_w0), .scanout(we_reg_SO_w0) ); +ScanShareSel_JTAG_reg_ext_cg #(7, 0, 0) testInst_Ra_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_Ra_r0), .Q(radr_q), + .scanin(we_reg_SO_w0), .scanout(Ra_reg_SO_r0) ); +ScanShareSel_JTAG_reg_ext_cg #(1, 0, 0) testInst_re_reg_r0 ( + .clk(gated_clk_jtag_Wa_reg_w0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_re_r0), .Q(re_q), + .scanin(Ra_reg_SO_r0), .scanout(re_reg_SO_r0) ); +wire gated_clk_jtag_Data_reg_r0; +CKLNQD12PO4 UJ_clk_jtag_Data_reg_r0 (.Q(gated_clk_jtag_Data_reg_r0), .CP(clk), .E(captureDR_r0 | (debug_mode_sync & shiftDR)), .TE(scan_en)); +ScanShareSel_JTAG_reg_ext_cg #(9, 0, 0) testInst_Data_reg_r0 ( + .clk(gated_clk_jtag_Data_reg_r0), .sel(debug_mode), + .shiftDR(shiftDR), + .reset_(1'b1), .D(muxed_r0_OutputMuxDataOut[8:0]), .Q(data_regq[8:0]), + .scanin(re_reg_SO_r0), .scanout(Data_reg_SO_r0) ); +`ifdef ASSERT_ON +`ifndef SYNTHESIS +reg sim_reset_; +initial sim_reset_ = 0; +always @(posedge clk) sim_reset_ <= 1'b1; +wire start_of_sim = sim_reset_; +wire disable_clk_x_test = $test$plusargs ("disable_clk_x_test") ? 1'b1 : 1'b0; +nv_assert_no_x #(1,1,0," Try Reading Ram when clock is x for read port r0") _clk_x_test_read (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|re===1'b1 )), clk); +nv_assert_no_x #(1,1,0," Try Writing Ram when clock is x for write port w0") _clk_x_test_write (clk, sim_reset_, ((disable_clk_x_test===1'b0) && (|we===1'b1)), clk); +`endif // SYNTHESIS +`endif // ASSERT_ON +`ifdef ASSERT_ON +`ifndef SYNTHESIS +`endif +`endif +`ifdef ASSERT_ON +`ifndef SYNTHESIS +wire pwrbus_assertion_not_x_while_active = $test$plusargs ("pwrbus_assertion_not_x_while_active"); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_we ( we, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +nv_assert_never #(0, 0, "Power bus cannot be X when read/write enable is set") _pwrbus_assertion_not_x_while_active_re ( re, sim_reset_ && !pwrbus_assertion_not_x_while_active, ^pwrbus_ram_pd === 1'bx); +`endif +`endif +// submodule done +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/AN2D4PO4.v b/designs/src/NVDLA/vmod/vlibs/AN2D4PO4.v new file mode 100644 index 0000000..31c1243 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/AN2D4PO4.v @@ -0,0 +1,17 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: AN2D4PO4.v +module AN2D4PO4( +A1, +A2, +Z +); +input A1,A2; +output Z; +assign Z = A1 & A2; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/AN2D4PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/AN2D4PO4.v.vcp new file mode 100644 index 0000000..31c1243 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/AN2D4PO4.v.vcp @@ -0,0 +1,17 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: AN2D4PO4.v +module AN2D4PO4( +A1, +A2, +Z +); +input A1,A2; +output Z; +assign Z = A1 & A2; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/CKLNQD12.v b/designs/src/NVDLA/vmod/vlibs/CKLNQD12.v new file mode 100644 index 0000000..1bb159c --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/CKLNQD12.v @@ -0,0 +1,23 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: CKLNQD12.v +module CKLNQD12 ( + TE + ,E + ,CP + ,Q + ); +input TE ; +input E ; +input CP ; +output Q ; +reg qd; +always @(negedge CP) + qd <= TE | E; +assign Q = CP & qd; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/CKLNQD12.v.vcp b/designs/src/NVDLA/vmod/vlibs/CKLNQD12.v.vcp new file mode 100644 index 0000000..1bb159c --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/CKLNQD12.v.vcp @@ -0,0 +1,23 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: CKLNQD12.v +module CKLNQD12 ( + TE + ,E + ,CP + ,Q + ); +input TE ; +input E ; +input CP ; +output Q ; +reg qd; +always @(negedge CP) + qd <= TE | E; +assign Q = CP & qd; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/CKLNQD12PO4.v b/designs/src/NVDLA/vmod/vlibs/CKLNQD12PO4.v new file mode 100644 index 0000000..bd06389 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/CKLNQD12PO4.v @@ -0,0 +1,23 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: CKLNQD12PO4.v +module CKLNQD12PO4 ( + TE + ,E + ,CP + ,Q + ); +input TE ; +input E ; +input CP ; +output Q ; +reg qd; +always @(negedge CP) + qd <= TE | E; +assign Q = CP & qd; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/CKLNQD12PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/CKLNQD12PO4.v.vcp new file mode 100644 index 0000000..bd06389 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/CKLNQD12PO4.v.vcp @@ -0,0 +1,23 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: CKLNQD12PO4.v +module CKLNQD12PO4 ( + TE + ,E + ,CP + ,Q + ); +input TE ; +input E ; +input CP ; +output Q ; +reg qd; +always @(negedge CP) + qd <= TE | E; +assign Q = CP & qd; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_cdp_icvt.v b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_icvt.v new file mode 100644 index 0000000..e493523 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_icvt.v @@ -0,0 +1,731 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_cdp_icvt.v +module HLS_cdp_icvt ( + cfg_alu_in_rsc_z //|< i + ,cfg_mul_in_rsc_z //|< i + ,cfg_truncate_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [7:0] cfg_alu_in_rsc_z; +input [15:0] cfg_mul_in_rsc_z; +input [4:0] cfg_truncate_rsc_z; +input chn_data_in_rsc_vz; +input [7:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [8:0] chn_data_out_rsc_z; +wire [8:0] cfg_alu_ext; +wire [7:0] cfg_alu_in; +wire [15:0] cfg_mul_in; +wire [4:0] cfg_truncate; +wire [8:0] chn_data_ext; +wire [7:0] chn_data_in; +wire [8:0] chn_data_out; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire mon_sub_c; +wire [24:0] mul_data_out; +wire [24:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [8:0] sub_data_out; +wire [8:0] sub_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire [8:0] tru_dout; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign chn_data_in[7:0] = chn_data_in_rsc_z[7:0]; +assign cfg_alu_in[7:0] = cfg_alu_in_rsc_z[7:0]; +assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0]; +assign cfg_truncate[4:0] = cfg_truncate_rsc_z[4:0]; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +assign chn_data_out_rsc_z[8:0] = chn_data_out[8:0]; +//cvt +assign chn_data_ext[8:0] = {{1{chn_data_in[7]}}, chn_data_in[7:0]}; +assign cfg_alu_ext[8:0] = {{1{cfg_alu_in[7]}}, cfg_alu_in[7:0]}; +//sub +assign {mon_sub_c,sub_dout[8:0]} = $signed(chn_data_ext[8:0]) -$signed(cfg_alu_ext[8:0]); +HLS_cdp_ICVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_in_pvld (chn_in_pvld) //|< w + ,.sub_dout (sub_dout[8:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_in_prdy (chn_in_prdy) //|> w + ,.sub_data_out (sub_data_out[8:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[24:0] = $signed(sub_data_out[8:0]) * $signed(cfg_mul_in[15:0]); +HLS_cdp_ICVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[24:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[24:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 9 ),.OUT_WIDTH(9 ),.SHIFT_WIDTH(5 )) shiftright_su ( + .data_in (mul_data_out[24:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< w + ,.data_out (tru_dout[8:0]) //|> w + ); +//signed +//unsigned +HLS_cdp_ICVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.tru_dout (tru_dout[8:0]) //|< w + ,.chn_data_out (chn_data_out[8:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.mul_out_prdy (mul_out_prdy) //|> w + ); +endmodule // HLS_cdp_icvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[8:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[8:0] (chn_in_pvld,chn_in_prdy) +// ************************************************************************************************************** +module HLS_cdp_ICVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_in_pvld + ,sub_dout + ,sub_out_prdy + ,chn_in_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_in_pvld; +input [8:0] sub_dout; +input sub_out_prdy; +output chn_in_prdy; +output [8:0] sub_data_out; +output sub_out_pvld; +reg chn_in_prdy; +reg [8:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [8:0] p1_skid_data; +reg [8:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [8:0] sub_data_out; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + chn_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[8:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_in_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[8:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[8:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_in_pvld^chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_in_pvld && !chn_in_prdy), (chn_in_pvld), (chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_ICVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[24:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[24:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_ICVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [24:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [24:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [24:0] mul_data_out; +reg mul_out_pvld; +reg [24:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [24:0] p2_skid_data; +reg [24:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[24:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[24:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[24:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_ICVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[8:0] (chn_out_pvld,chn_out_prdy) <= tru_dout[8:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_ICVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_out_prdy + ,mul_out_pvld + ,tru_dout + ,chn_data_out + ,chn_out_pvld + ,mul_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_out_prdy; +input mul_out_pvld; +input [8:0] tru_dout; +output [8:0] chn_data_out; +output chn_out_pvld; +output mul_out_prdy; +reg [8:0] chn_data_out; +reg chn_out_pvld; +reg mul_out_prdy; +reg [8:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [8:0] p3_skid_data; +reg [8:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + mul_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? tru_dout[8:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_out_pvld + or p3_skid_valid + or tru_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? tru_dout[8:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or chn_out_prdy + or p3_pipe_data + ) begin + chn_out_pvld = p3_pipe_valid; + p3_pipe_ready = chn_out_prdy; + chn_data_out[8:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_ICVT_pipe_p3 diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_cdp_icvt.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_icvt.v.vcp new file mode 100644 index 0000000..e493523 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_icvt.v.vcp @@ -0,0 +1,731 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_cdp_icvt.v +module HLS_cdp_icvt ( + cfg_alu_in_rsc_z //|< i + ,cfg_mul_in_rsc_z //|< i + ,cfg_truncate_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [7:0] cfg_alu_in_rsc_z; +input [15:0] cfg_mul_in_rsc_z; +input [4:0] cfg_truncate_rsc_z; +input chn_data_in_rsc_vz; +input [7:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [8:0] chn_data_out_rsc_z; +wire [8:0] cfg_alu_ext; +wire [7:0] cfg_alu_in; +wire [15:0] cfg_mul_in; +wire [4:0] cfg_truncate; +wire [8:0] chn_data_ext; +wire [7:0] chn_data_in; +wire [8:0] chn_data_out; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire mon_sub_c; +wire [24:0] mul_data_out; +wire [24:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [8:0] sub_data_out; +wire [8:0] sub_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire [8:0] tru_dout; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign chn_data_in[7:0] = chn_data_in_rsc_z[7:0]; +assign cfg_alu_in[7:0] = cfg_alu_in_rsc_z[7:0]; +assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0]; +assign cfg_truncate[4:0] = cfg_truncate_rsc_z[4:0]; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +assign chn_data_out_rsc_z[8:0] = chn_data_out[8:0]; +//cvt +assign chn_data_ext[8:0] = {{1{chn_data_in[7]}}, chn_data_in[7:0]}; +assign cfg_alu_ext[8:0] = {{1{cfg_alu_in[7]}}, cfg_alu_in[7:0]}; +//sub +assign {mon_sub_c,sub_dout[8:0]} = $signed(chn_data_ext[8:0]) -$signed(cfg_alu_ext[8:0]); +HLS_cdp_ICVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_in_pvld (chn_in_pvld) //|< w + ,.sub_dout (sub_dout[8:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_in_prdy (chn_in_prdy) //|> w + ,.sub_data_out (sub_data_out[8:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[24:0] = $signed(sub_data_out[8:0]) * $signed(cfg_mul_in[15:0]); +HLS_cdp_ICVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[24:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[24:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 9 ),.OUT_WIDTH(9 ),.SHIFT_WIDTH(5 )) shiftright_su ( + .data_in (mul_data_out[24:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< w + ,.data_out (tru_dout[8:0]) //|> w + ); +//signed +//unsigned +HLS_cdp_ICVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.tru_dout (tru_dout[8:0]) //|< w + ,.chn_data_out (chn_data_out[8:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.mul_out_prdy (mul_out_prdy) //|> w + ); +endmodule // HLS_cdp_icvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[8:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[8:0] (chn_in_pvld,chn_in_prdy) +// ************************************************************************************************************** +module HLS_cdp_ICVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_in_pvld + ,sub_dout + ,sub_out_prdy + ,chn_in_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_in_pvld; +input [8:0] sub_dout; +input sub_out_prdy; +output chn_in_prdy; +output [8:0] sub_data_out; +output sub_out_pvld; +reg chn_in_prdy; +reg [8:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [8:0] p1_skid_data; +reg [8:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [8:0] sub_data_out; +reg sub_out_pvld; +//## pipe (1) skid buffer +always @( + chn_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? sub_dout[8:0] : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_in_pvld + or p1_skid_valid + or sub_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? sub_dout[8:0] : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_out_prdy + or p1_pipe_data + ) begin + sub_out_pvld = p1_pipe_valid; + p1_pipe_ready = sub_out_prdy; + sub_data_out[8:0] = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_in_pvld^chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_in_pvld && !chn_in_prdy), (chn_in_pvld), (chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_ICVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[24:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[24:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_ICVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [24:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [24:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [24:0] mul_data_out; +reg mul_out_pvld; +reg [24:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [24:0] p2_skid_data; +reg [24:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_out_prdy; +//## pipe (2) skid buffer +always @( + sub_out_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_out_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_out_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? mul_dout[24:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_out_pvld + or p2_skid_valid + or mul_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_out_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? mul_dout[24:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_out_prdy + or p2_pipe_data + ) begin + mul_out_pvld = p2_pipe_valid; + p2_pipe_ready = mul_out_prdy; + mul_data_out[24:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_ICVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[8:0] (chn_out_pvld,chn_out_prdy) <= tru_dout[8:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_ICVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_out_prdy + ,mul_out_pvld + ,tru_dout + ,chn_data_out + ,chn_out_pvld + ,mul_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_out_prdy; +input mul_out_pvld; +input [8:0] tru_dout; +output [8:0] chn_data_out; +output chn_out_pvld; +output mul_out_prdy; +reg [8:0] chn_data_out; +reg chn_out_pvld; +reg mul_out_prdy; +reg [8:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [8:0] p3_skid_data; +reg [8:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +//## pipe (3) skid buffer +always @( + mul_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? tru_dout[8:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_out_pvld + or p3_skid_valid + or tru_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? tru_dout[8:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or chn_out_prdy + or p3_pipe_data + ) begin + chn_out_pvld = p3_pipe_valid; + p3_pipe_ready = chn_out_prdy; + chn_data_out[8:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_ICVT_pipe_p3 diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_cdp_ocvt.v b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_ocvt.v new file mode 100644 index 0000000..f806a69 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_ocvt.v @@ -0,0 +1,958 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_cdp_ocvt.v +module HLS_cdp_ocvt ( + cfg_alu_in_rsc_z //|< i + ,cfg_mul_in_rsc_z //|< i + ,cfg_truncate_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [24:0] cfg_alu_in_rsc_z; +input [15:0] cfg_mul_in_rsc_z; +input [5:0] cfg_truncate_rsc_z; +input chn_data_in_rsc_vz; +input [24:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [7:0] chn_data_out_rsc_z; +wire [24:0] cfg_alu_in; +wire [24:0] cfg_alu_reg; +wire [15:0] cfg_mul_in; +wire [5:0] cfg_truncate; +wire [25:0] chn_alu_ext; +wire [25:0] chn_data_ext; +wire [24:0] chn_data_in; +wire [7:0] chn_data_out; +wire [24:0] chn_data_reg; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire mon_sub_c; +wire [41:0] mul_data_out; +wire [41:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [25:0] sub_data_out; +wire [25:0] sub_dout; +wire sub_in_prdy; +wire sub_in_pvld; +wire sub_out_prdy; +wire sub_out_pvld; +wire [7:0] tru_dout; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign chn_data_in[24:0] = chn_data_in_rsc_z[24:0]; +assign cfg_alu_in[24:0] = cfg_alu_in_rsc_z[24:0]; +assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0]; +assign cfg_truncate[5:0] = cfg_truncate_rsc_z[5:0]; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +assign chn_data_out_rsc_z[7:0] = chn_data_out[7:0]; +HLS_cdp_OCVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_alu_in (cfg_alu_in[24:0]) //|< w + ,.chn_data_in (chn_data_in[24:0]) //|< w + ,.chn_in_pvld (chn_in_pvld) //|< w + ,.sub_in_prdy (sub_in_prdy) //|< w + ,.cfg_alu_reg (cfg_alu_reg[24:0]) //|> w + ,.chn_data_reg (chn_data_reg[24:0]) //|> w + ,.chn_in_prdy (chn_in_prdy) //|> w + ,.sub_in_pvld (sub_in_pvld) //|> w + ); +//covert +assign chn_data_ext[25:0] = {{1{chn_data_reg[24]}}, chn_data_reg[24:0]}; +assign chn_alu_ext[25:0] = {{1{cfg_alu_reg[24]}}, cfg_alu_reg[24:0]}; +//sub +assign {mon_sub_c,sub_dout[25:0]} = $signed(chn_data_ext[25:0]) -$signed(chn_alu_ext[25:0]); +HLS_cdp_OCVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sub_dout (sub_dout[25:0]) //|< w + ,.sub_in_pvld (sub_in_pvld) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.sub_data_out (sub_data_out[25:0]) //|> w + ,.sub_in_prdy (sub_in_prdy) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[41:0] = $signed(sub_data_out[25:0]) * $signed(cfg_mul_in[15:0]); +HLS_cdp_OCVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[41:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[41:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 26 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(6 )) shiftright_su ( + .data_in (mul_data_out[41:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< w + ,.data_out (tru_dout[7:0]) //|> w + ); +//signed +//unsigned +HLS_cdp_OCVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.tru_dout (tru_dout[7:0]) //|< w + ,.chn_data_out (chn_data_out[7:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.mul_out_prdy (mul_out_prdy) //|> w + ); +endmodule // HLS_cdp_ocvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {chn_data_reg[24:0],cfg_alu_reg[24:0]} (sub_in_pvld,sub_in_prdy) <= {chn_data_in[24:0],cfg_alu_in[24:0]} (chn_in_pvld,chn_in_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_alu_in + ,chn_data_in + ,chn_in_pvld + ,sub_in_prdy + ,cfg_alu_reg + ,chn_data_reg + ,chn_in_prdy + ,sub_in_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [24:0] cfg_alu_in; +input [24:0] chn_data_in; +input chn_in_pvld; +input sub_in_prdy; +output [24:0] cfg_alu_reg; +output [24:0] chn_data_reg; +output chn_in_prdy; +output sub_in_pvld; +reg [24:0] cfg_alu_reg; +reg [24:0] chn_data_reg; +reg chn_in_prdy; +reg [49:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [49:0] p1_skid_data; +reg [49:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg sub_in_pvld; +//## pipe (1) skid buffer +always @( + chn_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {chn_data_in[24:0],cfg_alu_in[24:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_in_pvld + or p1_skid_valid + or chn_data_in + or cfg_alu_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {chn_data_in[24:0],cfg_alu_in[24:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_in_prdy + or p1_pipe_data + ) begin + sub_in_pvld = p1_pipe_valid; + p1_pipe_ready = sub_in_prdy; + {chn_data_reg[24:0],cfg_alu_reg[24:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_in_pvld^sub_in_prdy^chn_in_pvld^chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_in_pvld && !chn_in_prdy), (chn_in_pvld), (chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[25:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[25:0] (sub_in_pvld,sub_in_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sub_dout + ,sub_in_pvld + ,sub_out_prdy + ,sub_data_out + ,sub_in_prdy + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [25:0] sub_dout; +input sub_in_pvld; +input sub_out_prdy; +output [25:0] sub_data_out; +output sub_in_prdy; +output sub_out_pvld; +reg [25:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [25:0] p2_skid_data; +reg [25:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg [25:0] sub_data_out; +reg sub_in_prdy; +reg sub_out_pvld; +//## pipe (2) skid buffer +always @( + sub_in_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_in_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_in_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_in_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? sub_dout[25:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_in_pvld + or p2_skid_valid + or sub_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_in_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? sub_dout[25:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or sub_out_prdy + or p2_pipe_data + ) begin + sub_out_pvld = p2_pipe_valid; + p2_pipe_ready = sub_out_prdy; + sub_data_out[25:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^sub_in_pvld^sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_in_pvld && !sub_in_prdy), (sub_in_pvld), (sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[41:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[41:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [41:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [41:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [41:0] mul_data_out; +reg mul_out_pvld; +reg [41:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [41:0] p3_skid_data; +reg [41:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg sub_out_prdy; +//## pipe (3) skid buffer +always @( + sub_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = sub_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + sub_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? mul_dout[41:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or sub_out_pvld + or p3_skid_valid + or mul_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? sub_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? mul_dout[41:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or mul_out_prdy + or p3_pipe_data + ) begin + mul_out_pvld = p3_pipe_valid; + p3_pipe_ready = mul_out_prdy; + mul_data_out[41:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[7:0] (chn_out_pvld,chn_out_prdy) <= tru_dout[7:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_out_prdy + ,mul_out_pvld + ,tru_dout + ,chn_data_out + ,chn_out_pvld + ,mul_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_out_prdy; +input mul_out_pvld; +input [7:0] tru_dout; +output [7:0] chn_data_out; +output chn_out_pvld; +output mul_out_prdy; +reg [7:0] chn_data_out; +reg chn_out_pvld; +reg mul_out_prdy; +reg [7:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [7:0] p4_skid_data; +reg [7:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + mul_out_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = mul_out_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + mul_out_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? tru_dout[7:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or mul_out_pvld + or p4_skid_valid + or tru_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? mul_out_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? tru_dout[7:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or chn_out_prdy + or p4_pipe_data + ) begin + chn_out_pvld = p4_pipe_valid; + p4_pipe_ready = chn_out_prdy; + chn_data_out[7:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_cdp_ocvt.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_ocvt.v.vcp new file mode 100644 index 0000000..f806a69 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_cdp_ocvt.v.vcp @@ -0,0 +1,958 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_cdp_ocvt.v +module HLS_cdp_ocvt ( + cfg_alu_in_rsc_z //|< i + ,cfg_mul_in_rsc_z //|< i + ,cfg_truncate_rsc_z //|< i + ,chn_data_in_rsc_vz //|< i + ,chn_data_in_rsc_z //|< i + ,chn_data_out_rsc_vz //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_in_rsc_lz //|> o + ,chn_data_out_rsc_lz //|> o + ,chn_data_out_rsc_z //|> o + ); +input [24:0] cfg_alu_in_rsc_z; +input [15:0] cfg_mul_in_rsc_z; +input [5:0] cfg_truncate_rsc_z; +input chn_data_in_rsc_vz; +input [24:0] chn_data_in_rsc_z; +input chn_data_out_rsc_vz; +input nvdla_core_clk; +input nvdla_core_rstn; +output chn_data_in_rsc_lz; +output chn_data_out_rsc_lz; +output [7:0] chn_data_out_rsc_z; +wire [24:0] cfg_alu_in; +wire [24:0] cfg_alu_reg; +wire [15:0] cfg_mul_in; +wire [5:0] cfg_truncate; +wire [25:0] chn_alu_ext; +wire [25:0] chn_data_ext; +wire [24:0] chn_data_in; +wire [7:0] chn_data_out; +wire [24:0] chn_data_reg; +wire chn_in_prdy; +wire chn_in_pvld; +wire chn_out_prdy; +wire chn_out_pvld; +wire mon_sub_c; +wire [41:0] mul_data_out; +wire [41:0] mul_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire [25:0] sub_data_out; +wire [25:0] sub_dout; +wire sub_in_prdy; +wire sub_in_pvld; +wire sub_out_prdy; +wire sub_out_pvld; +wire [7:0] tru_dout; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign chn_in_pvld = chn_data_in_rsc_vz; +assign chn_out_prdy = chn_data_out_rsc_vz; +assign chn_data_in[24:0] = chn_data_in_rsc_z[24:0]; +assign cfg_alu_in[24:0] = cfg_alu_in_rsc_z[24:0]; +assign cfg_mul_in[15:0] = cfg_mul_in_rsc_z[15:0]; +assign cfg_truncate[5:0] = cfg_truncate_rsc_z[5:0]; +assign chn_data_in_rsc_lz = chn_in_prdy; +assign chn_data_out_rsc_lz = chn_out_pvld; +assign chn_data_out_rsc_z[7:0] = chn_data_out[7:0]; +HLS_cdp_OCVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.cfg_alu_in (cfg_alu_in[24:0]) //|< w + ,.chn_data_in (chn_data_in[24:0]) //|< w + ,.chn_in_pvld (chn_in_pvld) //|< w + ,.sub_in_prdy (sub_in_prdy) //|< w + ,.cfg_alu_reg (cfg_alu_reg[24:0]) //|> w + ,.chn_data_reg (chn_data_reg[24:0]) //|> w + ,.chn_in_prdy (chn_in_prdy) //|> w + ,.sub_in_pvld (sub_in_pvld) //|> w + ); +//covert +assign chn_data_ext[25:0] = {{1{chn_data_reg[24]}}, chn_data_reg[24:0]}; +assign chn_alu_ext[25:0] = {{1{cfg_alu_reg[24]}}, cfg_alu_reg[24:0]}; +//sub +assign {mon_sub_c,sub_dout[25:0]} = $signed(chn_data_ext[25:0]) -$signed(chn_alu_ext[25:0]); +HLS_cdp_OCVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.sub_dout (sub_dout[25:0]) //|< w + ,.sub_in_pvld (sub_in_pvld) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.sub_data_out (sub_data_out[25:0]) //|> w + ,.sub_in_prdy (sub_in_prdy) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[41:0] = $signed(sub_data_out[25:0]) * $signed(cfg_mul_in[15:0]); +HLS_cdp_OCVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[41:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[41:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 26 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(6 )) shiftright_su ( + .data_in (mul_data_out[41:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< w + ,.data_out (tru_dout[7:0]) //|> w + ); +//signed +//unsigned +HLS_cdp_OCVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_out_prdy (chn_out_prdy) //|< w + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.tru_dout (tru_dout[7:0]) //|< w + ,.chn_data_out (chn_data_out[7:0]) //|> w + ,.chn_out_pvld (chn_out_pvld) //|> w + ,.mul_out_prdy (mul_out_prdy) //|> w + ); +endmodule // HLS_cdp_ocvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {chn_data_reg[24:0],cfg_alu_reg[24:0]} (sub_in_pvld,sub_in_prdy) <= {chn_data_in[24:0],cfg_alu_in[24:0]} (chn_in_pvld,chn_in_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,cfg_alu_in + ,chn_data_in + ,chn_in_pvld + ,sub_in_prdy + ,cfg_alu_reg + ,chn_data_reg + ,chn_in_prdy + ,sub_in_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [24:0] cfg_alu_in; +input [24:0] chn_data_in; +input chn_in_pvld; +input sub_in_prdy; +output [24:0] cfg_alu_reg; +output [24:0] chn_data_reg; +output chn_in_prdy; +output sub_in_pvld; +reg [24:0] cfg_alu_reg; +reg [24:0] chn_data_reg; +reg chn_in_prdy; +reg [49:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [49:0] p1_skid_data; +reg [49:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg sub_in_pvld; +//## pipe (1) skid buffer +always @( + chn_in_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_in_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_in_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_in_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {chn_data_in[24:0],cfg_alu_in[24:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_in_pvld + or p1_skid_valid + or chn_data_in + or cfg_alu_in + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_in_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {chn_data_in[24:0],cfg_alu_in[24:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_in_prdy + or p1_pipe_data + ) begin + sub_in_pvld = p1_pipe_valid; + p1_pipe_ready = sub_in_prdy; + {chn_data_reg[24:0],cfg_alu_reg[24:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_in_pvld^sub_in_prdy^chn_in_pvld^chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_in_pvld && !chn_in_prdy), (chn_in_pvld), (chn_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[25:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[25:0] (sub_in_pvld,sub_in_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,sub_dout + ,sub_in_pvld + ,sub_out_prdy + ,sub_data_out + ,sub_in_prdy + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [25:0] sub_dout; +input sub_in_pvld; +input sub_out_prdy; +output [25:0] sub_data_out; +output sub_in_prdy; +output sub_out_pvld; +reg [25:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [25:0] p2_skid_data; +reg [25:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg [25:0] sub_data_out; +reg sub_in_prdy; +reg sub_out_pvld; +//## pipe (2) skid buffer +always @( + sub_in_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_in_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_in_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_in_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? sub_dout[25:0] : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_in_pvld + or p2_skid_valid + or sub_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_in_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? sub_dout[25:0] : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or sub_out_prdy + or p2_pipe_data + ) begin + sub_out_pvld = p2_pipe_valid; + p2_pipe_ready = sub_out_prdy; + sub_data_out[25:0] = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^sub_in_pvld^sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_in_pvld && !sub_in_prdy), (sub_in_pvld), (sub_in_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[41:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[41:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [41:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [41:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [41:0] mul_data_out; +reg mul_out_pvld; +reg [41:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [41:0] p3_skid_data; +reg [41:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg sub_out_prdy; +//## pipe (3) skid buffer +always @( + sub_out_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = sub_out_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + sub_out_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? mul_dout[41:0] : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or sub_out_pvld + or p3_skid_valid + or mul_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? sub_out_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? mul_dout[41:0] : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or mul_out_prdy + or p3_pipe_data + ) begin + mul_out_pvld = p3_pipe_valid; + p3_pipe_ready = mul_out_prdy; + mul_data_out[41:0] = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[7:0] (chn_out_pvld,chn_out_prdy) <= tru_dout[7:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module HLS_cdp_OCVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_out_prdy + ,mul_out_pvld + ,tru_dout + ,chn_data_out + ,chn_out_pvld + ,mul_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_out_prdy; +input mul_out_pvld; +input [7:0] tru_dout; +output [7:0] chn_data_out; +output chn_out_pvld; +output mul_out_prdy; +reg [7:0] chn_data_out; +reg chn_out_pvld; +reg mul_out_prdy; +reg [7:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [7:0] p4_skid_data; +reg [7:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +//## pipe (4) skid buffer +always @( + mul_out_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = mul_out_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + mul_out_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? tru_dout[7:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or mul_out_pvld + or p4_skid_valid + or tru_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? mul_out_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? tru_dout[7:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or chn_out_prdy + or p4_pipe_data + ) begin + chn_out_pvld = p4_pipe_valid; + p4_pipe_ready = chn_out_prdy; + chn_data_out[7:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // HLS_cdp_OCVT_pipe_p4 diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp17.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp17.v new file mode 100644 index 0000000..534cd50 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp17.v @@ -0,0 +1,894 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp16_to_fp17.v +module FP16_TO_FP17_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP16_TO_FP17_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP16_TO_FP17_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP16_TO_FP17_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-197 +// Generated date: Tue Nov 15 18:05:52 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP17_leading_sign_10_0 +// ------------------------------------------------------------------ +module FP16_TO_FP17_leading_sign_10_0 ( + mantissa, rtn +); + input [9:0] mantissa; + output [3:0] rtn; +// Interconnect Declarations + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1; + wire c_h_1_2; + wire c_h_1_3; + wire IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc; + wire[0:0] IntLeadZero_10U_leading_sign_10_0_rtn_and_31_nl; + wire[0:0] IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_or_nl; + wire[0:0] IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_nor_6_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[7:6]!=2'b00)); + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[9:8]!=2'b00)); + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[5:4]!=2'b00)); + assign c_h_1_2 = IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[3:2]==2'b00) + & IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1; + assign c_h_1_3 = c_h_1_2 & IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc = (mantissa[1:0]==2'b00) + & c_h_1_3; + assign IntLeadZero_10U_leading_sign_10_0_rtn_and_31_nl = c_h_1_2 & (~ IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3); + assign IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_or_nl + = (IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1 & (IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1 + | (~ IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2)) & (~ c_h_1_3)) + | IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc; + assign IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_nor_6_nl + = ~((mantissa[9]) | (~((mantissa[8:7]!=2'b01))) | (((mantissa[5]) | (~((mantissa[4:3]!=2'b01)))) + & c_h_1_2) | ((mantissa[1]) & c_h_1_3) | IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc); + assign rtn = {c_h_1_3 , (IntLeadZero_10U_leading_sign_10_0_rtn_and_31_nl) , (IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_or_nl) + , (IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_nor_6_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:08:26 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP17_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP17_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP17_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP17_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp16_to_fp17_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp16_to_fp17_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_staller +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [15:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [15:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [15:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_16_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 16'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [15:0] MUX_v_16_2_2; + input [15:0] input_0; + input [15:0] input_1; + input [0:0] sel; + reg [15:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_16_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP17_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [15:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [15:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP17_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd16)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [15:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [3:0] chn_o_rsci_d_13_10; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_15; + reg chn_o_rsci_d_14; + wire [1:0] fsm_output; + wire IsDenorm_5U_10U_or_tmp; + wire and_dcpl_2; + wire and_dcpl_8; + wire and_dcpl_9; + wire and_dcpl_13; + wire or_dcpl_8; + wire and_dcpl_19; + wire and_38_cse; + wire and_4_mdf; + wire IsDenorm_5U_10U_land_lpi_1_dfm; + wire IsInf_5U_10U_land_lpi_1_dfm; + wire IsInf_5U_10U_IsInf_5U_10U_and_cse_sva; + wire IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva; + wire chn_o_and_1_cse; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire and_6_cse; + wire chn_o_rsci_d_9_0_mx0c1; + wire FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse; + wire [9:0] FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_itm; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire [4:0] FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva; + wire [5:0] nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva; + wire IsNaN_5U_10U_land_lpi_1_dfm; + wire [3:0] libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_mux_2_nl; + wire[0:0] FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_nl; + wire[9:0] FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_or_1_nl; + wire[0:0] nand_8_nl; + wire[3:0] FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_mux1h_nl; +// Interconnect Declarations for Component Instantiations + wire [8:0] nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_a; + assign nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_a = chn_a_rsci_d_mxwt[8:0]; + wire [5:0] nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_s; + assign nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_s = conv_u2u_4_5(libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1) + + 5'b1; + wire [9:0] nl_leading_sign_10_0_rg_mantissa; + assign nl_leading_sign_10_0_rg_mantissa = chn_a_rsci_d_mxwt[9:0]; + wire [16:0] nl_HLS_fp16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 + , chn_o_rsci_d_15 , chn_o_rsci_d_14 , chn_o_rsci_d_13_10 , chn_o_rsci_d_9_0}; + FP16_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd9), + .signd_a(32'sd1), + .width_s(32'sd5), + .width_z(32'sd10)) FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg ( + .a(nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_a[8:0]), + .s(nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_s[4:0]), + .z(FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_itm) + ); + FP16_TO_FP17_leading_sign_10_0 leading_sign_10_0_rg ( + .mantissa(nl_leading_sign_10_0_rg_mantissa[9:0]), + .rtn(libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1) + ); + HLS_fp16_to_fp17_core_chn_a_rsci HLS_fp16_to_fp17_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp16_to_fp17_core_chn_o_rsci HLS_fp16_to_fp17_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp16_to_fp17_core_staller HLS_fp16_to_fp17_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp16_to_fp17_core_core_fsm HLS_fp16_to_fp17_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign and_6_cse = and_4_mdf & (fsm_output[1]); + assign iExpoWidth_oExpoWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, and_6_cse)), fsm_output[1]); +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 477 +// PSL HLS_fp16_to_fp17_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign chn_o_and_1_cse = core_wen & (~(and_38_cse | (fsm_output[0]))); + assign nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva = ({1'b1 , (~ libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1)}) + + 5'b10001; + assign FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva = nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva[4:0]; + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse + = ~(IsDenorm_5U_10U_land_lpi_1_dfm | IsInf_5U_10U_land_lpi_1_dfm); + assign IsInf_5U_10U_land_lpi_1_dfm = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000) + | (~ IsInf_5U_10U_IsInf_5U_10U_and_cse_sva)); + assign IsNaN_5U_10U_land_lpi_1_dfm = IsDenorm_5U_10U_or_tmp & IsInf_5U_10U_IsInf_5U_10U_and_cse_sva; + assign IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva = ~((chn_a_rsci_d_mxwt[14:10]!=5'b00000)); + assign IsDenorm_5U_10U_land_lpi_1_dfm = IsDenorm_5U_10U_or_tmp & IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva; + assign IsDenorm_5U_10U_or_tmp = (chn_a_rsci_d_mxwt[9:0]!=10'b0000000000); + assign IsInf_5U_10U_IsInf_5U_10U_and_cse_sva = (chn_a_rsci_d_mxwt[14:10]==5'b11111); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_8 = (chn_a_rsci_d_mxwt[14:12]==3'b111) & IsDenorm_5U_10U_or_tmp; + assign and_dcpl_9 = (chn_a_rsci_d_mxwt[11:10]==2'b11); + assign and_dcpl_13 = and_dcpl_2 & chn_a_rsci_bawt; + assign or_dcpl_8 = (chn_a_rsci_d_mxwt[12:10]!=3'b111) | (~((chn_a_rsci_d_mxwt[14:13]==2'b11) + & IsDenorm_5U_10U_or_tmp)); + assign and_dcpl_19 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_38_cse = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = (or_dcpl_8 & or_cse & chn_a_rsci_bawt & (fsm_output[1])) + | (or_dcpl_8 & and_dcpl_13); + assign chn_a_rsci_oswt_unreg = and_6_cse; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= and_6_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_14 <= 1'b0; + end + else if ( core_wen & (~(and_38_cse | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_14 <= (FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_mux_2_nl) | IsInf_5U_10U_land_lpi_1_dfm + | IsNaN_5U_10U_land_lpi_1_dfm; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15 <= 1'b0; + chn_o_rsci_d_13_10 <= 4'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_15 <= chn_a_rsci_d_mxwt[14]; + chn_o_rsci_d_13_10 <= MUX_v_4_2_2((FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_mux1h_nl), + 4'b1111, IsNaN_5U_10U_land_lpi_1_dfm); + chn_o_rsci_d_16 <= chn_a_rsci_d_mxwt[15]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((and_4_mdf & and_dcpl_9 & and_dcpl_8 & (fsm_output[1])) + | (and_dcpl_13 & and_dcpl_9 & and_dcpl_8) | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_or_1_nl), + (chn_a_rsci_d_mxwt[9:0]), nand_8_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_6_cse | and_dcpl_19) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_19; + end + end + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_nl + = ~((chn_a_rsci_d_mxwt[14]) | (~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000) | + (~ IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva)))); + assign FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_mux_2_nl = MUX_s_1_2_2((FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_nl), + (FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva[4]), IsDenorm_5U_10U_land_lpi_1_dfm); + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_mux1h_nl = + MUX1HOT_v_4_3_2((chn_a_rsci_d_mxwt[13:10]), (FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva[3:0]), + 4'b1110, {FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse + , IsDenorm_5U_10U_land_lpi_1_dfm , IsInf_5U_10U_land_lpi_1_dfm}); + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_or_1_nl = + MUX_v_10_2_2(FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_itm, 10'b1111111111, + IsInf_5U_10U_land_lpi_1_dfm); + assign nand_8_nl = ~((~ FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse) + & chn_o_rsci_d_9_0_mx0c1); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [3:0] MUX1HOT_v_4_3_2; + input [3:0] input_2; + input [3:0] input_1; + input [3:0] input_0; + input [2:0] sel; + reg [3:0] result; + begin + result = input_0 & {4{sel[0]}}; + result = result | ( input_1 & {4{sel[1]}}); + result = result | ( input_2 & {4{sel[2]}}); + MUX1HOT_v_4_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [4:0] conv_u2u_4_5 ; + input [3:0] vector ; + begin + conv_u2u_4_5 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17 +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP17_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP16_TO_FP17_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp16_to_fp17_core HLS_fp16_to_fp17_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp17.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp17.v.vcp new file mode 100644 index 0000000..534cd50 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp17.v.vcp @@ -0,0 +1,894 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp16_to_fp17.v +module FP16_TO_FP17_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP16_TO_FP17_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP16_TO_FP17_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP16_TO_FP17_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-197 +// Generated date: Tue Nov 15 18:05:52 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP17_leading_sign_10_0 +// ------------------------------------------------------------------ +module FP16_TO_FP17_leading_sign_10_0 ( + mantissa, rtn +); + input [9:0] mantissa; + output [3:0] rtn; +// Interconnect Declarations + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1; + wire c_h_1_2; + wire c_h_1_3; + wire IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc; + wire[0:0] IntLeadZero_10U_leading_sign_10_0_rtn_and_31_nl; + wire[0:0] IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_or_nl; + wire[0:0] IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_nor_6_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[7:6]!=2'b00)); + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[9:8]!=2'b00)); + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[5:4]!=2'b00)); + assign c_h_1_2 = IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[3:2]==2'b00) + & IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1; + assign c_h_1_3 = c_h_1_2 & IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc = (mantissa[1:0]==2'b00) + & c_h_1_3; + assign IntLeadZero_10U_leading_sign_10_0_rtn_and_31_nl = c_h_1_2 & (~ IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_18_3_sdt_3); + assign IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_or_nl + = (IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_1 & (IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_14_2_sdt_1 + | (~ IntLeadZero_10U_leading_sign_10_0_rtn_wrs_c_6_2_sdt_2)) & (~ c_h_1_3)) + | IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc; + assign IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_nor_6_nl + = ~((mantissa[9]) | (~((mantissa[8:7]!=2'b01))) | (((mantissa[5]) | (~((mantissa[4:3]!=2'b01)))) + & c_h_1_2) | ((mantissa[1]) & c_h_1_3) | IntLeadZero_10U_leading_sign_10_0_rtn_and_35_ssc); + assign rtn = {c_h_1_3 , (IntLeadZero_10U_leading_sign_10_0_rtn_and_31_nl) , (IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_or_nl) + , (IntLeadZero_10U_leading_sign_10_0_rtn_IntLeadZero_10U_leading_sign_10_0_rtn_nor_6_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:08:26 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP17_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP17_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP17_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP17_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp16_to_fp17_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp16_to_fp17_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_staller +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [15:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [15:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [15:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_16_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 16'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [15:0] MUX_v_16_2_2; + input [15:0] input_0; + input [15:0] input_1; + input [0:0] sel; + reg [15:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_16_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP17_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp HLS_fp16_to_fp17_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [15:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [15:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP17_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd16)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp HLS_fp16_to_fp17_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17_core +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [15:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [3:0] chn_o_rsci_d_13_10; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_15; + reg chn_o_rsci_d_14; + wire [1:0] fsm_output; + wire IsDenorm_5U_10U_or_tmp; + wire and_dcpl_2; + wire and_dcpl_8; + wire and_dcpl_9; + wire and_dcpl_13; + wire or_dcpl_8; + wire and_dcpl_19; + wire and_38_cse; + wire and_4_mdf; + wire IsDenorm_5U_10U_land_lpi_1_dfm; + wire IsInf_5U_10U_land_lpi_1_dfm; + wire IsInf_5U_10U_IsInf_5U_10U_and_cse_sva; + wire IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva; + wire chn_o_and_1_cse; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire and_6_cse; + wire chn_o_rsci_d_9_0_mx0c1; + wire FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse; + wire [9:0] FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_itm; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire [4:0] FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva; + wire [5:0] nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva; + wire IsNaN_5U_10U_land_lpi_1_dfm; + wire [3:0] libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_mux_2_nl; + wire[0:0] FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_nl; + wire[9:0] FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_or_1_nl; + wire[0:0] nand_8_nl; + wire[3:0] FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_mux1h_nl; +// Interconnect Declarations for Component Instantiations + wire [8:0] nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_a; + assign nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_a = chn_a_rsci_d_mxwt[8:0]; + wire [5:0] nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_s; + assign nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_s = conv_u2u_4_5(libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1) + + 5'b1; + wire [9:0] nl_leading_sign_10_0_rg_mantissa; + assign nl_leading_sign_10_0_rg_mantissa = chn_a_rsci_d_mxwt[9:0]; + wire [16:0] nl_HLS_fp16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 + , chn_o_rsci_d_15 , chn_o_rsci_d_14 , chn_o_rsci_d_13_10 , chn_o_rsci_d_9_0}; + FP16_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd9), + .signd_a(32'sd1), + .width_s(32'sd5), + .width_z(32'sd10)) FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg ( + .a(nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_a[8:0]), + .s(nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_rg_s[4:0]), + .z(FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_itm) + ); + FP16_TO_FP17_leading_sign_10_0 leading_sign_10_0_rg ( + .mantissa(nl_leading_sign_10_0_rg_mantissa[9:0]), + .rtn(libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1) + ); + HLS_fp16_to_fp17_core_chn_a_rsci HLS_fp16_to_fp17_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp16_to_fp17_core_chn_o_rsci HLS_fp16_to_fp17_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp16_to_fp17_core_staller HLS_fp16_to_fp17_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp16_to_fp17_core_core_fsm HLS_fp16_to_fp17_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign and_6_cse = and_4_mdf & (fsm_output[1]); + assign iExpoWidth_oExpoWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, and_6_cse)), fsm_output[1]); +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 477 +// PSL HLS_fp16_to_fp17_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign chn_o_and_1_cse = core_wen & (~(and_38_cse | (fsm_output[0]))); + assign nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva = ({1'b1 , (~ libraries_leading_sign_10_0_9ac8f64992538a762a5a05a903e0d3de3d5a_1)}) + + 5'b10001; + assign FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva = nl_FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva[4:0]; + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse + = ~(IsDenorm_5U_10U_land_lpi_1_dfm | IsInf_5U_10U_land_lpi_1_dfm); + assign IsInf_5U_10U_land_lpi_1_dfm = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000) + | (~ IsInf_5U_10U_IsInf_5U_10U_and_cse_sva)); + assign IsNaN_5U_10U_land_lpi_1_dfm = IsDenorm_5U_10U_or_tmp & IsInf_5U_10U_IsInf_5U_10U_and_cse_sva; + assign IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva = ~((chn_a_rsci_d_mxwt[14:10]!=5'b00000)); + assign IsDenorm_5U_10U_land_lpi_1_dfm = IsDenorm_5U_10U_or_tmp & IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva; + assign IsDenorm_5U_10U_or_tmp = (chn_a_rsci_d_mxwt[9:0]!=10'b0000000000); + assign IsInf_5U_10U_IsInf_5U_10U_and_cse_sva = (chn_a_rsci_d_mxwt[14:10]==5'b11111); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_8 = (chn_a_rsci_d_mxwt[14:12]==3'b111) & IsDenorm_5U_10U_or_tmp; + assign and_dcpl_9 = (chn_a_rsci_d_mxwt[11:10]==2'b11); + assign and_dcpl_13 = and_dcpl_2 & chn_a_rsci_bawt; + assign or_dcpl_8 = (chn_a_rsci_d_mxwt[12:10]!=3'b111) | (~((chn_a_rsci_d_mxwt[14:13]==2'b11) + & IsDenorm_5U_10U_or_tmp)); + assign and_dcpl_19 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_38_cse = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = (or_dcpl_8 & or_cse & chn_a_rsci_bawt & (fsm_output[1])) + | (or_dcpl_8 & and_dcpl_13); + assign chn_a_rsci_oswt_unreg = and_6_cse; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= and_6_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_14 <= 1'b0; + end + else if ( core_wen & (~(and_38_cse | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_14 <= (FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_mux_2_nl) | IsInf_5U_10U_land_lpi_1_dfm + | IsNaN_5U_10U_land_lpi_1_dfm; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15 <= 1'b0; + chn_o_rsci_d_13_10 <= 4'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_15 <= chn_a_rsci_d_mxwt[14]; + chn_o_rsci_d_13_10 <= MUX_v_4_2_2((FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_mux1h_nl), + 4'b1111, IsNaN_5U_10U_land_lpi_1_dfm); + chn_o_rsci_d_16 <= chn_a_rsci_d_mxwt[15]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((and_4_mdf & and_dcpl_9 & and_dcpl_8 & (fsm_output[1])) + | (and_dcpl_13 & and_dcpl_9 & and_dcpl_8) | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_or_1_nl), + (chn_a_rsci_d_mxwt[9:0]), nand_8_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_6_cse | and_dcpl_19) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_19; + end + end + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_nl + = ~((chn_a_rsci_d_mxwt[14]) | (~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000) | + (~ IsZero_5U_10U_IsZero_5U_10U_nor_cse_sva)))); + assign FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_mux_2_nl = MUX_s_1_2_2((FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_nl), + (FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva[4]), IsDenorm_5U_10U_land_lpi_1_dfm); + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_mux1h_nl = + MUX1HOT_v_4_3_2((chn_a_rsci_d_mxwt[13:10]), (FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_acc_psp_sva[3:0]), + 4'b1110, {FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse + , IsDenorm_5U_10U_land_lpi_1_dfm , IsInf_5U_10U_land_lpi_1_dfm}); + assign FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_or_1_nl = + MUX_v_10_2_2(FpExpoWidthInc_5U_6U_10U_1U_1U_if_1_if_lshift_itm, 10'b1111111111, + IsInf_5U_10U_land_lpi_1_dfm); + assign nand_8_nl = ~((~ FpExpoWidthInc_5U_6U_10U_1U_1U_FpExpoWidthInc_5U_6U_10U_1U_1U_nor_1_cse) + & chn_o_rsci_d_9_0_mx0c1); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [3:0] MUX1HOT_v_4_3_2; + input [3:0] input_2; + input [3:0] input_1; + input [3:0] input_0; + input [2:0] sel; + reg [3:0] result; + begin + result = input_0 & {4{sel[0]}}; + result = result | ( input_1 & {4{sel[1]}}); + result = result | ( input_2 & {4{sel[2]}}); + MUX1HOT_v_4_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [4:0] conv_u2u_4_5 ; + input [3:0] vector ; + begin + conv_u2u_4_5 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp17 +// ------------------------------------------------------------------ +module HLS_fp16_to_fp17 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP17_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP16_TO_FP17_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp16_to_fp17_core HLS_fp16_to_fp17_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp32.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp32.v new file mode 100644 index 0000000..53d15a2 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp32.v @@ -0,0 +1,1051 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp16_to_fp32.v +module FP16_TO_FP32_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP16_TO_FP32_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP16_TO_FP32_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP16_TO_FP32_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-197 +// Generated date: Tue Nov 15 18:08:42 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP32_leading_sign_23_0 +// ------------------------------------------------------------------ +module FP16_TO_FP32_leading_sign_23_0 ( + mantissa, rtn +); + input [22:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_10; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[20:19]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[18:17]!=2'b00)); + assign c_h_1_2 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[16:15]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[12:11]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[10:9]!=2'b00)); + assign c_h_1_5 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[8:7]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[4:3]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 = ~((mantissa[2:1]!=2'b00)); + assign c_h_1_9 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + assign c_h_1_10 = c_h_1_6 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl = c_h_1_6 & (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3)) & (c_h_1_9 | (~ c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2)))) & c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl + = ((~((mantissa[22]) | (~((mantissa[21:20]!=2'b01))))) & (~(((mantissa[18]) + | (~((mantissa[17:16]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[14]) | (~((mantissa[13:12]!=2'b01))))) + & (~(((mantissa[10]) | (~((mantissa[9:8]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[6]) | (~((mantissa[5:4]!=2'b01))))) & (~((~((mantissa[2:1]==2'b01))) + & c_h_1_9)))) & c_h_1_10))) | ((~ (mantissa[0])) & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + & c_h_1_9 & c_h_1_10); + assign rtn = {c_h_1_10 , (IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl) + , (IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:09:04 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP32_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP32_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP32_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP32_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp16_to_fp32_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp16_to_fp32_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_staller +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [15:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [15:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [15:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_16_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 16'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [15:0] MUX_v_16_2_2; + input [15:0] input_0; + input [15:0] input_1; + input [0:0] sel; + reg [15:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_16_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP32_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [15:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [15:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP32_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd16)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [15:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [3:0] chn_o_rsci_d_26_23; + reg [9:0] chn_o_rsci_d_22_13; + reg [2:0] chn_o_rsci_d_12_10; + reg [9:0] chn_o_rsci_d_9_0; + reg [1:0] chn_o_rsci_d_30_29; + reg [1:0] chn_o_rsci_d_28_27; + wire [1:0] fsm_output; + wire IsNaN_5U_23U_nor_tmp; + wire and_dcpl_2; + wire and_dcpl_7; + wire and_dcpl_10; + wire or_dcpl_8; + wire and_dcpl_23; + wire or_tmp_19; + wire and_42_cse; + wire and_46_cse; + wire and_48_cse; + wire and_4_mdf; + wire IsDenorm_5U_23U_land_lpi_1_dfm; + wire IsInf_5U_23U_land_lpi_1_dfm; + wire IsNaN_5U_23U_IsNaN_5U_23U_nand_cse; + wire IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva; + wire [9:0] FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm; + wire [9:0] FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm; + wire chn_o_and_1_cse; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire chn_o_rsci_d_9_0_mx0c1; + wire [22:0] FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2; + wire FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc; + wire [5:0] z_out; + wire [6:0] nl_z_out; + wire HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire [5:0] FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva; + wire [6:0] nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva; + wire IsNaN_5U_23U_land_lpi_1_dfm; + wire FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0; + wire [4:0] libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb_1; + wire[0:0] iExpoWidth_oExpoWidth_prb_1; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_mux_6_nl; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_2_nl; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_mux_8_nl; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_5_nl; + wire[9:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_4_nl; + wire[0:0] or_35_nl; + wire[2:0] FpExpoWidthInc_5U_8U_23U_1U_1U_if_3_nor_nl; + wire[2:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_4_nl; + wire[0:0] not_nl; + wire[9:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_5_nl; + wire[0:0] or_36_nl; + wire[3:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_mux1h_nl; + wire[0:0] and_6_nl; + wire[0:0] IsNaN_5U_23U_aelse_not_2_nl; + wire[4:0] FpExpoWidthInc_5U_8U_23U_1U_1U_else_mux_1_nl; + wire[0:0] FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_and_1_nl; +// Interconnect Declarations for Component Instantiations + wire [21:0] nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_a; + assign nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_a = {(chn_a_rsci_d_mxwt[8:0]) + , 13'b0}; + wire [5:0] nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_s; + assign nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_s = z_out; + wire [22:0] nl_leading_sign_23_0_rg_mantissa; + assign nl_leading_sign_23_0_rg_mantissa = {(chn_a_rsci_d_mxwt[9:0]) , 13'b0}; + wire [31:0] nl_HLS_fp16_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp16_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 + , chn_o_rsci_d_30_29 , chn_o_rsci_d_28_27 , chn_o_rsci_d_26_23 , chn_o_rsci_d_22_13 + , chn_o_rsci_d_12_10 , chn_o_rsci_d_9_0}; + FP16_TO_FP32_mgc_shift_l_v4 #(.width_a(32'sd22), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd23)) FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg ( + .a(nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_a[21:0]), + .s(nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_s[5:0]), + .z(FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2) + ); + FP16_TO_FP32_leading_sign_23_0 leading_sign_23_0_rg ( + .mantissa(nl_leading_sign_23_0_rg_mantissa[22:0]), + .rtn(libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1) + ); + HLS_fp16_to_fp32_core_chn_a_rsci HLS_fp16_to_fp32_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp16_to_fp32_core_chn_o_rsci HLS_fp16_to_fp32_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp16_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp16_to_fp32_core_staller HLS_fp16_to_fp32_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp16_to_fp32_core_core_fsm HLS_fp16_to_fp32_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iExpoWidth_oExpoWidth_prb = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 596 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln596_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 597 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln597_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb_1 = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 550 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln550_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb_1 } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb_1 = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 477 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb_1 } @rose(nvdla_core_clk); + assign chn_o_and_1_cse = core_wen & (~(and_42_cse | (fsm_output[0]))); + assign and_6_nl = and_4_mdf & (fsm_output[1]); + assign HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_6_nl)), fsm_output[1]); + assign nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva = ({1'b1 , (~ libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1)}) + + 6'b110001; + assign FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva = nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva[5:0]; + assign FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), IsNaN_5U_23U_land_lpi_1_dfm); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc = + ~(IsDenorm_5U_23U_land_lpi_1_dfm | IsInf_5U_23U_land_lpi_1_dfm); + assign IsInf_5U_23U_land_lpi_1_dfm = ~((FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm!=10'b0000000000) + | (FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm!=10'b0000000000) | + IsNaN_5U_23U_IsNaN_5U_23U_nand_cse); + assign IsNaN_5U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign IsNaN_5U_23U_land_lpi_1_dfm = ~(IsNaN_5U_23U_nor_tmp | IsNaN_5U_23U_IsNaN_5U_23U_nand_cse); + assign IsDenorm_5U_23U_land_lpi_1_dfm = ((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)) + & IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva; + assign IsNaN_5U_23U_aelse_not_2_nl = ~ IsNaN_5U_23U_land_lpi_1_dfm; + assign FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), (IsNaN_5U_23U_aelse_not_2_nl)); + assign IsNaN_5U_23U_IsNaN_5U_23U_nand_cse = ~((chn_a_rsci_d_mxwt[14:10]==5'b11111)); + assign IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva = ~((chn_a_rsci_d_mxwt[14:10]!=5'b00000)); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0 = (chn_a_rsci_d_mxwt[9:0]!=10'b0000000000) + | (~ IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva); + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_7 = (chn_a_rsci_d_mxwt[14:13]==2'b11); + assign and_dcpl_10 = (chn_a_rsci_d_mxwt[12:10]==3'b111); + assign or_dcpl_8 = (chn_a_rsci_d_mxwt[14:10]!=5'b11111) | IsNaN_5U_23U_nor_tmp; + assign and_dcpl_23 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_42_cse = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign and_46_cse = and_dcpl_10 & or_cse & and_dcpl_7 & (~ IsNaN_5U_23U_nor_tmp) + & chn_a_rsci_bawt & (fsm_output[1]); + assign and_48_cse = or_dcpl_8 & or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign or_tmp_19 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = and_48_cse | (or_dcpl_8 & and_dcpl_2 & chn_a_rsci_bawt); + assign chn_a_rsci_oswt_unreg = or_tmp_19; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= or_tmp_19; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_28_27 <= 2'b0; + end + else if ( core_wen & (~(and_42_cse | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_28_27 <= (FpExpoWidthInc_5U_8U_23U_1U_1U_mux_6_nl) | ({{1{IsInf_5U_23U_land_lpi_1_dfm}}, + IsInf_5U_23U_land_lpi_1_dfm}) | ({{1{IsNaN_5U_23U_land_lpi_1_dfm}}, IsNaN_5U_23U_land_lpi_1_dfm}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_29 <= 2'b0; + chn_o_rsci_d_12_10 <= 3'b0; + chn_o_rsci_d_26_23 <= 4'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_30_29 <= (FpExpoWidthInc_5U_8U_23U_1U_1U_mux_8_nl) | ({{1{IsInf_5U_23U_land_lpi_1_dfm}}, + IsInf_5U_23U_land_lpi_1_dfm}) | ({{1{IsNaN_5U_23U_land_lpi_1_dfm}}, IsNaN_5U_23U_land_lpi_1_dfm}); + chn_o_rsci_d_12_10 <= ~(MUX_v_3_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_if_3_nor_nl), + 3'b111, IsNaN_5U_23U_land_lpi_1_dfm)); + chn_o_rsci_d_26_23 <= MUX_v_4_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_mux1h_nl), + 4'b1111, IsNaN_5U_23U_land_lpi_1_dfm); + chn_o_rsci_d_31 <= chn_a_rsci_d_mxwt[15]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & (and_46_cse | (and_dcpl_10 & and_dcpl_7 & (~ IsNaN_5U_23U_nor_tmp) + & chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse & chn_a_rsci_bawt) | + chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_4_nl), + FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm, or_35_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_13 <= 10'b0; + end + else if ( core_wen & (and_46_cse | and_48_cse) ) begin + chn_o_rsci_d_22_13 <= MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_5_nl), + FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm, or_36_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (or_tmp_19 | and_dcpl_23) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_23; + end + end + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_2_nl = + MUX_v_2_2_2(2'b00, ({{1{FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0}}, FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0}), + (z_out[0])); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_mux_6_nl = MUX_v_2_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva[5:4]), + (FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_2_nl), FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_5_nl = + MUX_v_2_2_2(2'b00, (z_out[3:2]), FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_mux_8_nl = MUX_v_2_2_2(2'b1, (FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_5_nl), + FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc); + assign not_nl = ~ FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc; + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_4_nl = + MUX_v_3_2_2(3'b000, (FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2[12:10]), (not_nl)); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_if_3_nor_nl = ~(MUX_v_3_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_4_nl), + 3'b111, IsInf_5U_23U_land_lpi_1_dfm)); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_mux1h_nl = + MUX1HOT_v_4_3_2((chn_a_rsci_d_mxwt[13:10]), (FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva[3:0]), + 4'b1110, {FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc + , IsDenorm_5U_23U_land_lpi_1_dfm , IsInf_5U_23U_land_lpi_1_dfm}); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_4_nl = + MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2[9:0]), 10'b1111111111, + IsInf_5U_23U_land_lpi_1_dfm); + assign or_35_nl = FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc + | (~ chn_o_rsci_d_9_0_mx0c1); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_5_nl = + MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2[22:13]), 10'b1111111111, + IsInf_5U_23U_land_lpi_1_dfm); + assign or_36_nl = FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc + | (~ and_48_cse); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_and_1_nl = (fsm_output[1]) & (chn_a_rsci_d_mxwt[14:10]==5'b00000); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_else_mux_1_nl = MUX_v_5_2_2(({4'b11 , (chn_a_rsci_d_mxwt[14])}), + libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1, FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_and_1_nl); + assign nl_z_out = conv_u2u_5_6(FpExpoWidthInc_5U_8U_23U_1U_1U_else_mux_1_nl) + + 6'b1; + assign z_out = nl_z_out[5:0]; + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [3:0] MUX1HOT_v_4_3_2; + input [3:0] input_2; + input [3:0] input_1; + input [3:0] input_0; + input [2:0] sel; + reg [3:0] result; + begin + result = input_0 & {4{sel[0]}}; + result = result | ( input_1 & {4{sel[1]}}); + result = result | ( input_2 & {4{sel[2]}}); + MUX1HOT_v_4_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [1:0] MUX_v_2_2_2; + input [1:0] input_0; + input [1:0] input_1; + input [0:0] sel; + reg [1:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_2_2_2 = result; + end + endfunction + function [2:0] MUX_v_3_2_2; + input [2:0] input_0; + input [2:0] input_1; + input [0:0] sel; + reg [2:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_3_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [5:0] conv_u2u_5_6 ; + input [4:0] vector ; + begin + conv_u2u_5_6 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32 +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP32_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP16_TO_FP32_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp16_to_fp32_core HLS_fp16_to_fp32_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp32.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp32.v.vcp new file mode 100644 index 0000000..53d15a2 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp16_to_fp32.v.vcp @@ -0,0 +1,1051 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp16_to_fp32.v +module FP16_TO_FP32_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP16_TO_FP32_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP16_TO_FP32_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP16_TO_FP32_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-197 +// Generated date: Tue Nov 15 18:08:42 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP32_leading_sign_23_0 +// ------------------------------------------------------------------ +module FP16_TO_FP32_leading_sign_23_0 ( + mantissa, rtn +); + input [22:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_10; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[20:19]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[18:17]!=2'b00)); + assign c_h_1_2 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[16:15]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[12:11]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[10:9]!=2'b00)); + assign c_h_1_5 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[8:7]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[4:3]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 = ~((mantissa[2:1]!=2'b00)); + assign c_h_1_9 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + assign c_h_1_10 = c_h_1_6 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl = c_h_1_6 & (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3)) & (c_h_1_9 | (~ c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2)))) & c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl + = ((~((mantissa[22]) | (~((mantissa[21:20]!=2'b01))))) & (~(((mantissa[18]) + | (~((mantissa[17:16]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[14]) | (~((mantissa[13:12]!=2'b01))))) + & (~(((mantissa[10]) | (~((mantissa[9:8]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[6]) | (~((mantissa[5:4]!=2'b01))))) & (~((~((mantissa[2:1]==2'b01))) + & c_h_1_9)))) & c_h_1_10))) | ((~ (mantissa[0])) & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + & c_h_1_9 & c_h_1_10); + assign rtn = {c_h_1_10 , (IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl) + , (IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:09:04 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP32_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP32_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP16_TO_FP32_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP16_TO_FP32_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp16_to_fp32_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp16_to_fp32_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_staller +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [15:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [15:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [15:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_16_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 16'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [15:0] MUX_v_16_2_2; + input [15:0] input_0; + input [15:0] input_1; + input [0:0] sel; + reg [15:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_16_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP32_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp HLS_fp16_to_fp32_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [15:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [15:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP32_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd16)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp HLS_fp16_to_fp32_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32_core +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [15:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [3:0] chn_o_rsci_d_26_23; + reg [9:0] chn_o_rsci_d_22_13; + reg [2:0] chn_o_rsci_d_12_10; + reg [9:0] chn_o_rsci_d_9_0; + reg [1:0] chn_o_rsci_d_30_29; + reg [1:0] chn_o_rsci_d_28_27; + wire [1:0] fsm_output; + wire IsNaN_5U_23U_nor_tmp; + wire and_dcpl_2; + wire and_dcpl_7; + wire and_dcpl_10; + wire or_dcpl_8; + wire and_dcpl_23; + wire or_tmp_19; + wire and_42_cse; + wire and_46_cse; + wire and_48_cse; + wire and_4_mdf; + wire IsDenorm_5U_23U_land_lpi_1_dfm; + wire IsInf_5U_23U_land_lpi_1_dfm; + wire IsNaN_5U_23U_IsNaN_5U_23U_nand_cse; + wire IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva; + wire [9:0] FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm; + wire [9:0] FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm; + wire chn_o_and_1_cse; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire chn_o_rsci_d_9_0_mx0c1; + wire [22:0] FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2; + wire FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc; + wire [5:0] z_out; + wire [6:0] nl_z_out; + wire HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire [5:0] FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva; + wire [6:0] nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva; + wire IsNaN_5U_23U_land_lpi_1_dfm; + wire FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0; + wire [4:0] libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb_1; + wire[0:0] iExpoWidth_oExpoWidth_prb_1; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_mux_6_nl; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_2_nl; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_mux_8_nl; + wire[1:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_5_nl; + wire[9:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_4_nl; + wire[0:0] or_35_nl; + wire[2:0] FpExpoWidthInc_5U_8U_23U_1U_1U_if_3_nor_nl; + wire[2:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_4_nl; + wire[0:0] not_nl; + wire[9:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_5_nl; + wire[0:0] or_36_nl; + wire[3:0] FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_mux1h_nl; + wire[0:0] and_6_nl; + wire[0:0] IsNaN_5U_23U_aelse_not_2_nl; + wire[4:0] FpExpoWidthInc_5U_8U_23U_1U_1U_else_mux_1_nl; + wire[0:0] FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_and_1_nl; +// Interconnect Declarations for Component Instantiations + wire [21:0] nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_a; + assign nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_a = {(chn_a_rsci_d_mxwt[8:0]) + , 13'b0}; + wire [5:0] nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_s; + assign nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_s = z_out; + wire [22:0] nl_leading_sign_23_0_rg_mantissa; + assign nl_leading_sign_23_0_rg_mantissa = {(chn_a_rsci_d_mxwt[9:0]) , 13'b0}; + wire [31:0] nl_HLS_fp16_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp16_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 + , chn_o_rsci_d_30_29 , chn_o_rsci_d_28_27 , chn_o_rsci_d_26_23 , chn_o_rsci_d_22_13 + , chn_o_rsci_d_12_10 , chn_o_rsci_d_9_0}; + FP16_TO_FP32_mgc_shift_l_v4 #(.width_a(32'sd22), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd23)) FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg ( + .a(nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_a[21:0]), + .s(nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_lshift_rg_s[5:0]), + .z(FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2) + ); + FP16_TO_FP32_leading_sign_23_0 leading_sign_23_0_rg ( + .mantissa(nl_leading_sign_23_0_rg_mantissa[22:0]), + .rtn(libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1) + ); + HLS_fp16_to_fp32_core_chn_a_rsci HLS_fp16_to_fp32_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp16_to_fp32_core_chn_o_rsci HLS_fp16_to_fp32_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp16_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp16_to_fp32_core_staller HLS_fp16_to_fp32_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp16_to_fp32_core_core_fsm HLS_fp16_to_fp32_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iExpoWidth_oExpoWidth_prb = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 596 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln596_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 597 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln597_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb_1 = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 550 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln550_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb_1 } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb_1 = HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 477 +// PSL HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb_1 } @rose(nvdla_core_clk); + assign chn_o_and_1_cse = core_wen & (~(and_42_cse | (fsm_output[0]))); + assign and_6_nl = and_4_mdf & (fsm_output[1]); + assign HLS_fp16_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_6_nl)), fsm_output[1]); + assign nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva = ({1'b1 , (~ libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1)}) + + 6'b110001; + assign FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva = nl_FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva[5:0]; + assign FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), IsNaN_5U_23U_land_lpi_1_dfm); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc = + ~(IsDenorm_5U_23U_land_lpi_1_dfm | IsInf_5U_23U_land_lpi_1_dfm); + assign IsInf_5U_23U_land_lpi_1_dfm = ~((FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm!=10'b0000000000) + | (FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm!=10'b0000000000) | + IsNaN_5U_23U_IsNaN_5U_23U_nand_cse); + assign IsNaN_5U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign IsNaN_5U_23U_land_lpi_1_dfm = ~(IsNaN_5U_23U_nor_tmp | IsNaN_5U_23U_IsNaN_5U_23U_nand_cse); + assign IsDenorm_5U_23U_land_lpi_1_dfm = ((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)) + & IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva; + assign IsNaN_5U_23U_aelse_not_2_nl = ~ IsNaN_5U_23U_land_lpi_1_dfm; + assign FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), (IsNaN_5U_23U_aelse_not_2_nl)); + assign IsNaN_5U_23U_IsNaN_5U_23U_nand_cse = ~((chn_a_rsci_d_mxwt[14:10]==5'b11111)); + assign IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva = ~((chn_a_rsci_d_mxwt[14:10]!=5'b00000)); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0 = (chn_a_rsci_d_mxwt[9:0]!=10'b0000000000) + | (~ IsZero_5U_23U_IsZero_5U_23U_nor_cse_sva); + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_7 = (chn_a_rsci_d_mxwt[14:13]==2'b11); + assign and_dcpl_10 = (chn_a_rsci_d_mxwt[12:10]==3'b111); + assign or_dcpl_8 = (chn_a_rsci_d_mxwt[14:10]!=5'b11111) | IsNaN_5U_23U_nor_tmp; + assign and_dcpl_23 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_42_cse = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign and_46_cse = and_dcpl_10 & or_cse & and_dcpl_7 & (~ IsNaN_5U_23U_nor_tmp) + & chn_a_rsci_bawt & (fsm_output[1]); + assign and_48_cse = or_dcpl_8 & or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign or_tmp_19 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = and_48_cse | (or_dcpl_8 & and_dcpl_2 & chn_a_rsci_bawt); + assign chn_a_rsci_oswt_unreg = or_tmp_19; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= or_tmp_19; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_28_27 <= 2'b0; + end + else if ( core_wen & (~(and_42_cse | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_28_27 <= (FpExpoWidthInc_5U_8U_23U_1U_1U_mux_6_nl) | ({{1{IsInf_5U_23U_land_lpi_1_dfm}}, + IsInf_5U_23U_land_lpi_1_dfm}) | ({{1{IsNaN_5U_23U_land_lpi_1_dfm}}, IsNaN_5U_23U_land_lpi_1_dfm}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_29 <= 2'b0; + chn_o_rsci_d_12_10 <= 3'b0; + chn_o_rsci_d_26_23 <= 4'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_30_29 <= (FpExpoWidthInc_5U_8U_23U_1U_1U_mux_8_nl) | ({{1{IsInf_5U_23U_land_lpi_1_dfm}}, + IsInf_5U_23U_land_lpi_1_dfm}) | ({{1{IsNaN_5U_23U_land_lpi_1_dfm}}, IsNaN_5U_23U_land_lpi_1_dfm}); + chn_o_rsci_d_12_10 <= ~(MUX_v_3_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_if_3_nor_nl), + 3'b111, IsNaN_5U_23U_land_lpi_1_dfm)); + chn_o_rsci_d_26_23 <= MUX_v_4_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_mux1h_nl), + 4'b1111, IsNaN_5U_23U_land_lpi_1_dfm); + chn_o_rsci_d_31 <= chn_a_rsci_d_mxwt[15]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & (and_46_cse | (and_dcpl_10 & and_dcpl_7 & (~ IsNaN_5U_23U_nor_tmp) + & chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse & chn_a_rsci_bawt) | + chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_4_nl), + FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_9_0_lpi_1_dfm, or_35_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_13 <= 10'b0; + end + else if ( core_wen & (and_46_cse | and_48_cse) ) begin + chn_o_rsci_d_22_13 <= MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_5_nl), + FpMantWidthInc_5U_10U_23U_1U_1U_o_mant_22_13_lpi_1_dfm, or_36_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (or_tmp_19 | and_dcpl_23) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_23; + end + end + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_2_nl = + MUX_v_2_2_2(2'b00, ({{1{FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0}}, FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0}), + (z_out[0])); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_mux_6_nl = MUX_v_2_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva[5:4]), + (FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_2_nl), FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_5_nl = + MUX_v_2_2_2(2'b00, (z_out[3:2]), FpExpoWidthInc_5U_8U_23U_1U_1U_exs_10_0); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_mux_8_nl = MUX_v_2_2_2(2'b1, (FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_5_nl), + FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc); + assign not_nl = ~ FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc; + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_4_nl = + MUX_v_3_2_2(3'b000, (FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2[12:10]), (not_nl)); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_if_3_nor_nl = ~(MUX_v_3_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_and_4_nl), + 3'b111, IsInf_5U_23U_land_lpi_1_dfm)); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_mux1h_nl = + MUX1HOT_v_4_3_2((chn_a_rsci_d_mxwt[13:10]), (FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_acc_psp_sva[3:0]), + 4'b1110, {FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc + , IsDenorm_5U_23U_land_lpi_1_dfm , IsInf_5U_23U_land_lpi_1_dfm}); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_4_nl = + MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2[9:0]), 10'b1111111111, + IsInf_5U_23U_land_lpi_1_dfm); + assign or_35_nl = FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc + | (~ chn_o_rsci_d_9_0_mx0c1); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_or_5_nl = + MUX_v_10_2_2((FpExpoWidthInc_5U_8U_23U_1U_1U_o_mant_sva_2[22:13]), 10'b1111111111, + IsInf_5U_23U_land_lpi_1_dfm); + assign or_36_nl = FpExpoWidthInc_5U_8U_23U_1U_1U_FpExpoWidthInc_5U_8U_23U_1U_1U_nor_ssc + | (~ and_48_cse); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_and_1_nl = (fsm_output[1]) & (chn_a_rsci_d_mxwt[14:10]==5'b00000); + assign FpExpoWidthInc_5U_8U_23U_1U_1U_else_mux_1_nl = MUX_v_5_2_2(({4'b11 , (chn_a_rsci_d_mxwt[14])}), + libraries_leading_sign_23_0_4073cf0915bb058d810f74a52f4b9b365444_1, FpExpoWidthInc_5U_8U_23U_1U_1U_if_1_if_and_1_nl); + assign nl_z_out = conv_u2u_5_6(FpExpoWidthInc_5U_8U_23U_1U_1U_else_mux_1_nl) + + 6'b1; + assign z_out = nl_z_out[5:0]; + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [3:0] MUX1HOT_v_4_3_2; + input [3:0] input_2; + input [3:0] input_1; + input [3:0] input_0; + input [2:0] sel; + reg [3:0] result; + begin + result = input_0 & {4{sel[0]}}; + result = result | ( input_1 & {4{sel[1]}}); + result = result | ( input_2 & {4{sel[2]}}); + MUX1HOT_v_4_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [1:0] MUX_v_2_2_2; + input [1:0] input_0; + input [1:0] input_1; + input [0:0] sel; + reg [1:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_2_2_2 = result; + end + endfunction + function [2:0] MUX_v_3_2_2; + input [2:0] input_0; + input [2:0] input_1; + input [0:0] sel; + reg [2:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_3_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [5:0] conv_u2u_5_6 ; + input [4:0] vector ; + begin + conv_u2u_5_6 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp16_to_fp32 +// ------------------------------------------------------------------ +module HLS_fp16_to_fp32 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP16_TO_FP32_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP16_TO_FP32_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp16_to_fp32_core HLS_fp16_to_fp32_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_add.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_add.v new file mode 100644 index 0000000..ea65f62 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_add.v @@ -0,0 +1,1796 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_add.v +module FP17_ADD_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_ADD_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_ADD_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ../td_ccore_solutions/leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-144 +// Generated date: Sun Dec 11 16:48:02 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_leading_sign_23_0 +// ------------------------------------------------------------------ +module FP17_ADD_leading_sign_23_0 ( + mantissa, rtn +); + input [22:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_10; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[20:19]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[18:17]!=2'b00)); + assign c_h_1_2 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[16:15]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[12:11]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[10:9]!=2'b00)); + assign c_h_1_5 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[8:7]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[4:3]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 = ~((mantissa[2:1]!=2'b00)); + assign c_h_1_9 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + assign c_h_1_10 = c_h_1_6 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl = c_h_1_6 & (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3)) & (c_h_1_9 | (~ c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2)))) & c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl + = ((~((mantissa[22]) | (~((mantissa[21:20]!=2'b01))))) & (~(((mantissa[18]) + | (~((mantissa[17:16]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[14]) | (~((mantissa[13:12]!=2'b01))))) + & (~(((mantissa[10]) | (~((mantissa[9:8]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[6]) | (~((mantissa[5:4]!=2'b01))))) & (~((~((mantissa[2:1]==2'b01))) + & c_h_1_9)))) & c_h_1_10))) | ((~ (mantissa[0])) & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + & c_h_1_9 & c_h_1_10); + assign rtn = {c_h_1_10 , (IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl) + , (IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl)}; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP17_ADD_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP17_ADD_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:49:51 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_ADD_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP17_ADD_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_ADD_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_add_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_add_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_add_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_add_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [16:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [16:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [16:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_17_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 17'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_ADD_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [16:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [16:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core +// ------------------------------------------------------------------ +module HLS_fp17_add_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [16:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [5:0] chn_o_rsci_d_15_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + wire FpAdd_6U_10U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_23U_11U_else_and_tmp; + wire IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + wire nor_tmp_1; + wire mux_tmp_2; + wire or_tmp_10; + wire mux_tmp_6; + wire mux_tmp_8; + wire or_tmp_25; + wire nor_tmp_8; + wire or_tmp_43; + wire not_tmp_34; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_38; + wire or_tmp_47; + wire or_tmp_53; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_4; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_5; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_6; + reg [23:0] FpAdd_6U_10U_int_mant_p1_sva_3; + reg FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_4; + reg [5:0] FpAdd_6U_10U_o_expo_lpi_1_dfm_10; + reg FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + reg FpMantRNE_23U_11U_else_carry_sva_2; + reg FpMantRNE_23U_11U_else_and_svs_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_6; + reg FpAdd_6U_10U_IsZero_6U_10U_or_itm_2; + reg [6:0] FpAdd_6U_10U_a_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_a_left_shift_acc_itm_2; + reg FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2; + reg [6:0] FpAdd_6U_10U_b_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_b_left_shift_acc_itm_2; + reg [9:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3; + reg [9:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4; + reg FpAdd_6U_10U_mux_13_itm_4; + reg FpAdd_6U_10U_mux_13_itm_5; + reg FpAdd_6U_10U_mux_13_itm_6; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_4; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_5; + reg [15:0] FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1; + reg [15:0] FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1; + wire main_stage_en_1; + wire FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + wire and_58_m1c; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_24_cse; + wire FpAdd_6U_10U_or_cse; + wire nor_3_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_61_cse; + wire or_5_cse; + wire nor_7_cse; + wire and_41_cse; + wire FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt; + wire FpAdd_6U_10U_and_1_rgt; + wire FpAdd_6U_10U_and_2_rgt; + wire and_47_rgt; + wire and_51_rgt; + wire FpSignedBitsToFloat_6U_10U_or_1_rgt; + wire [22:0] FpNormalize_6U_23U_else_lshift_itm; + wire FpAdd_6U_10U_a_right_shift_qelse_and_tmp; + wire [5:0] z_out; + wire FpAdd_6U_10U_if_2_and_tmp; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire FpMantRNE_23U_11U_else_carry_sva_mx0w0; + wire FpAdd_6U_10U_and_tmp; + wire [22:0] FpAdd_6U_10U_addend_larger_asn_1_mx0w1; + wire [22:0] FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_a_int_mant_p1_sva; + wire [21:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0; + wire [22:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1; + wire FpNormalize_6U_23U_oelse_not_3; + wire [4:0] libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1; + wire IsNaN_6U_10U_aelse_and_cse; + wire FpAdd_6U_10U_and_8_cse; + wire IsNaN_6U_10U_1_aelse_and_cse; + wire FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse; + reg reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse; + wire mux_24_cse; + wire or_75_cse; + wire nand_cse; + wire FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + wire FpAdd_6U_10U_if_3_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_if_4_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1; + wire[9:0] FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl; + wire[9:0] FpMantRNE_23U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_23U_11U_else_acc_nl; + wire[0:0] FpSignedBitsToFloat_6U_10U_1_and_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_nl; + wire[0:0] FpAdd_6U_10U_and_nl; + wire[0:0] FpAdd_6U_10U_and_3_nl; + wire[0:0] FpAdd_6U_10U_and_7_nl; + wire[24:0] acc_1_nl; + wire[25:0] nl_acc_1_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_2_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_3_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_35_nl; + wire[0:0] nor_36_nl; + wire[5:0] FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl; + wire[5:0] FpNormalize_6U_23U_else_acc_nl; + wire[7:0] nl_FpNormalize_6U_23U_else_acc_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_nl; + wire[0:0] mux_10_nl; + wire[0:0] mux_9_nl; + wire[0:0] and_11_nl; + wire[0:0] or_18_nl; + wire[0:0] mux_14_nl; + wire[0:0] mux_12_nl; + wire[0:0] mux_11_nl; + wire[0:0] mux_13_nl; + wire[0:0] nor_25_nl; + wire[0:0] and_84_nl; + wire[0:0] mux_16_nl; + wire[0:0] or_31_nl; + wire[0:0] mux_15_nl; + wire[0:0] nor_23_nl; + wire[0:0] mux_18_nl; + wire[0:0] or_35_nl; + wire[0:0] mux_17_nl; + wire[0:0] nor_22_nl; + wire[0:0] and_82_nl; + wire[0:0] or_1_nl; + wire[0:0] mux_nl; + wire[0:0] nor_39_nl; + wire[5:0] FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[5:0] FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[0:0] FpAdd_6U_10U_is_a_greater_oelse_not_5_nl; + wire[0:0] mux_33_nl; + wire[0:0] mux_32_nl; + wire[0:0] mux_31_nl; + wire[0:0] and_91_nl; + wire[0:0] mux_35_nl; + wire[0:0] mux_34_nl; + wire[0:0] or_44_nl; + wire[6:0] FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[8:0] nl_FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[0:0] FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl; + wire[6:0] FpNormalize_6U_23U_acc_nl; + wire[8:0] nl_FpNormalize_6U_23U_acc_nl; + wire[0:0] or_3_nl; + wire[0:0] nor_38_nl; + wire[0:0] nor_33_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_34_nl; + wire[0:0] mux_7_nl; + wire[0:0] or_13_nl; + wire[0:0] mux_4_nl; + wire[0:0] nor_31_nl; + wire[0:0] nor_32_nl; + wire[10:0] FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[12:0] nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[6:0] acc_nl; + wire[7:0] nl_acc_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_2_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_3_nl; +// Interconnect Declarations for Component Instantiations + wire [22:0] nl_leading_sign_23_0_rg_mantissa; + assign nl_leading_sign_23_0_rg_mantissa = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [10:0] nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 + , (FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1[9:0])}; + wire [10:0] nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 + , (FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1[9:0])}; + wire [22:0] nl_FpNormalize_6U_23U_else_lshift_rg_a; + assign nl_FpNormalize_6U_23U_else_lshift_rg_a = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [16:0] nl_HLS_fp17_add_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_add_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 , chn_o_rsci_d_15_10 + , chn_o_rsci_d_9_0}; + FP17_ADD_leading_sign_23_0 leading_sign_23_0_rg ( + .mantissa(nl_leading_sign_23_0_rg_mantissa[22:0]), + .rtn(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + ); + FP17_ADD_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_b_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_addend_larger_asn_1_mx0w1) + ); + FP17_ADD_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_a_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_a_int_mant_p1_sva) + ); + FP17_ADD_mgc_shift_l_v4 #(.width_a(32'sd23), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd23)) FpNormalize_6U_23U_else_lshift_rg ( + .a(nl_FpNormalize_6U_23U_else_lshift_rg_a[22:0]), + .s(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1), + .z(FpNormalize_6U_23U_else_lshift_itm) + ); + HLS_fp17_add_core_chn_a_rsci HLS_fp17_add_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_add_core_chn_b_rsci HLS_fp17_add_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp17_add_core_chn_o_rsci HLS_fp17_add_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_add_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp17_add_core_staller HLS_fp17_add_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_add_core_core_fsm HLS_fp17_add_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_6U_10U_or_cse = IsNaN_6U_10U_1_land_lpi_1_dfm_6 | IsNaN_6U_10U_land_lpi_1_dfm_6; + assign IsNaN_6U_10U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_24_cse; + assign FpAdd_6U_10U_and_8_cse = core_wen & (~ and_dcpl_7) & mux_tmp_2; + assign and_41_cse = or_5_cse & main_stage_v_2; + assign nor_3_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23]))); + assign or_5_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + | and_dcpl_7); + assign FpAdd_6U_10U_and_1_rgt = (~ FpAdd_6U_10U_if_3_if_acc_1_itm_5_1) & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign FpAdd_6U_10U_and_2_rgt = FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign nor_24_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23])) + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign and_47_rgt = (~(IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_5)) + & or_5_cse; + assign or_31_nl = nor_7_cse | main_stage_v_2; + assign nor_23_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_15_nl = MUX_s_1_2_2((nor_23_nl), main_stage_v_2, chn_o_rsci_bawt); + assign mux_16_nl = MUX_s_1_2_2((mux_15_nl), (or_31_nl), main_stage_v_3); + assign IsNaN_6U_10U_1_aelse_and_cse = core_wen & (~ and_dcpl_7) & (mux_16_nl); + assign nor_7_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_61_cse = (FpAdd_6U_10U_is_a_greater_oif_equal_tmp & (~ FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1)) + | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + assign and_51_rgt = or_5_cse & (~ FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1) & ((~ + FpAdd_6U_10U_is_a_greater_oif_equal_tmp) | FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1); + assign or_1_nl = nor_7_cse | nor_tmp_1; + assign nor_39_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_1)); + assign mux_nl = MUX_s_1_2_2((nor_39_nl), nor_tmp_1, chn_o_rsci_bawt); + assign mux_24_cse = MUX_s_1_2_2((mux_nl), (or_1_nl), main_stage_v_1); + assign FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse = (or_5_cse + & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_4)) | and_dcpl_38; + assign or_75_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | nor_tmp_8; + assign and_58_m1c = or_5_cse & (~(IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp)); + assign FpSignedBitsToFloat_6U_10U_or_1_rgt = (or_5_cse & (~ IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) + & IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp) | ((~ or_61_cse) & and_58_m1c); + assign FpAdd_6U_10U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[15:10]) == + (chn_b_rsci_d_mxwt[15:10]); + assign IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_a_rsci_d_mxwt[15:10]!=6'b111111)); + assign FpMantRNE_23U_11U_else_carry_sva_mx0w0 = (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[11]) + & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[0]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[1]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[2]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[3]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[4]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[5]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[6]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[7]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[8]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[9]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[10]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[12])); + assign FpMantRNE_23U_11U_else_and_tmp = FpMantRNE_23U_11U_else_carry_sva_mx0w0 + & (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]==10'b1111111111) & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[22]) + | (FpAdd_6U_10U_int_mant_p1_sva_3[23])); + assign IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp = ~((~((chn_b_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_b_rsci_d_mxwt[15:10]!=6'b111111)); + assign nl_FpAdd_6U_10U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[15:10])}) + + conv_u2u_6_7(~ (chn_a_rsci_d_mxwt[15:10])) + 7'b1; + assign FpAdd_6U_10U_is_a_greater_acc_1_nl = nl_FpAdd_6U_10U_is_a_greater_acc_1_nl[6:0]; + assign FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1 = readslicef_7_1_6((FpAdd_6U_10U_is_a_greater_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_qr_lpi_1_dfm_4[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_1_nl = nl_FpAdd_6U_10U_if_3_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_3_if_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_o_expo_lpi_1_dfm_10[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_1_nl = nl_FpAdd_6U_10U_if_4_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_4_if_acc_1_nl)); + assign FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_4 + | (~ FpAdd_6U_10U_if_4_if_acc_1_itm_5_1); + assign FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_6U_10U_is_inf_lpi_1_dfm_4, + (FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl), FpMantRNE_23U_11U_else_and_svs_2); + assign FpAdd_6U_10U_and_tmp = FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 & FpMantRNE_23U_11U_else_and_svs_2; + assign FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c = ~(IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_5_cse; + assign FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_asn_1_mx0w1, + FpAdd_6U_10U_a_int_mant_p1_sva, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_a_int_mant_p1_sva, + FpAdd_6U_10U_addend_larger_asn_1_mx0w1, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0 = MUX_v_22_2_2((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[21:0]), + (FpAdd_6U_10U_int_mant_p1_sva_3[22:1]), FpAdd_6U_10U_int_mant_p1_sva_3[23]); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1 = MUX_v_23_2_2(23'b00000000000000000000000, + FpNormalize_6U_23U_else_lshift_itm, FpNormalize_6U_23U_oelse_not_3); + assign nl_FpNormalize_6U_23U_acc_nl = ({1'b1 , (~ FpAdd_6U_10U_qr_lpi_1_dfm_4)}) + + conv_u2s_5_7(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + + 7'b1; + assign FpNormalize_6U_23U_acc_nl = nl_FpNormalize_6U_23U_acc_nl[6:0]; + assign FpNormalize_6U_23U_oelse_not_3 = ((FpAdd_6U_10U_int_mant_p1_sva_3[22:0]!=23'b00000000000000000000000)) + & (readslicef_7_1_6((FpNormalize_6U_23U_acc_nl))); + assign nor_tmp_1 = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_3_nl = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | main_stage_v_2; + assign nor_38_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2))); + assign mux_tmp_2 = MUX_s_1_2_2((nor_38_nl), (or_3_nl), main_stage_v_1); + assign or_tmp_10 = IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_5; + assign nor_34_nl = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) | (~ or_5_cse)); + assign mux_5_nl = MUX_s_1_2_2((nor_34_nl), or_5_cse, FpAdd_6U_10U_if_3_if_acc_1_itm_5_1); + assign nor_33_nl = ~(or_tmp_10 | (~ (mux_5_nl))); + assign mux_tmp_6 = MUX_s_1_2_2((nor_33_nl), or_5_cse, FpMantRNE_23U_11U_else_and_tmp); + assign nor_31_nl = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & or_5_cse))); + assign mux_4_nl = MUX_s_1_2_2((nor_31_nl), or_5_cse, or_tmp_10); + assign or_13_nl = FpMantRNE_23U_11U_else_and_tmp | (~ (mux_4_nl)); + assign mux_7_nl = MUX_s_1_2_2(mux_tmp_6, (or_13_nl), main_stage_v_3); + assign nor_32_nl = ~((~ main_stage_v_3) | (~ reg_chn_o_rsci_ld_core_psct_cse) | + chn_o_rsci_bawt); + assign mux_tmp_8 = MUX_s_1_2_2((nor_32_nl), (mux_7_nl), main_stage_v_2); + assign or_tmp_25 = main_stage_v_2 | (~ or_5_cse); + assign nor_tmp_8 = or_tmp_10 & main_stage_v_2; + assign nand_cse = ~(reg_chn_o_rsci_ld_core_psct_cse & nor_tmp_8); + assign or_tmp_43 = chn_o_rsci_bawt | nand_cse; + assign not_tmp_34 = ~(chn_o_rsci_bawt | nand_cse); + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_5_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign and_dcpl_38 = or_5_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_4; + assign or_tmp_47 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_53 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_5_cse & (fsm_output[1]); + assign chn_o_rsci_d_9_0_mx0c1 = or_5_cse & main_stage_v_3 & (~ IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_b_rsci_bawt & chn_a_rsci_bawt)) & or_5_cse + & main_stage_v_1; + assign main_stage_v_2_mx0c1 = or_5_cse & main_stage_v_2 & (~ main_stage_v_1); + assign main_stage_v_3_mx0c1 = or_5_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[9:0])}) + + conv_u2u_10_11(~ (chn_b_rsci_d_mxwt[9:0])) + 11'b1; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl[10:0]; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 = readslicef_11_1_10((FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_53; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + assign FpAdd_6U_10U_a_right_shift_qelse_and_tmp = (fsm_output[1]) & (~((~(FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 + | (~ FpAdd_6U_10U_is_a_greater_oif_equal_tmp))) | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1)); + assign FpAdd_6U_10U_if_2_and_tmp = (fsm_output[1]) & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_47 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_47; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_3 & IsNaN_6U_10U_land_lpi_1_dfm_6) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4, + (FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl), FpSignedBitsToFloat_6U_10U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15_10 <= 6'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_15_10 <= MUX1HOT_v_6_4_2(FpAdd_6U_10U_o_expo_lpi_1_dfm_10, (FpAdd_6U_10U_if_4_if_acc_nl), + 6'b111110, FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4, + {(FpAdd_6U_10U_and_nl) , (FpAdd_6U_10U_and_3_nl) , (FpAdd_6U_10U_and_7_nl) + , FpAdd_6U_10U_or_cse}); + chn_o_rsci_d_16 <= FpAdd_6U_10U_mux_13_itm_6; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_53 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= 1'b0; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse <= + 1'b0; + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= 1'b0; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= 1'b0; + FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= 7'b0; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= 1'b0; + FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= 7'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_aelse_and_cse ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse <= + ~((chn_a_rsci_d_mxwt[16]) ^ (chn_b_rsci_d_mxwt[16])); + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= or_61_cse; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[15:0]!=16'b0000000000000000); + FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1 <= chn_b_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_b_left_shift_acc_itm_2[6:0]; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= (chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000); + FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1 <= chn_a_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_a_left_shift_acc_itm_2[6:0]; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= 6'b0; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= 1'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_5 <= 1'b0; + end + else if ( FpAdd_6U_10U_and_8_cse ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= FpAdd_6U_10U_qr_lpi_1_dfm_3; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= IsNaN_6U_10U_land_lpi_1_dfm_st_4; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= IsNaN_6U_10U_1_land_lpi_1_dfm_4; + FpAdd_6U_10U_mux_13_itm_5 <= FpAdd_6U_10U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= 24'b0; + end + else if ( core_wen & (~((~(or_5_cse & (~ reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse))) + & (~(or_5_cse & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse)))) + & mux_tmp_2 ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= readslicef_25_24_1((acc_1_nl)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & (and_41_cse | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_3_nl) ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= FpMantRNE_23U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= 6'b0; + end + else if ( core_wen & (FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt | FpAdd_6U_10U_and_1_rgt + | FpAdd_6U_10U_and_2_rgt) & (mux_10_nl) ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= MUX1HOT_v_6_3_2((FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl), + FpAdd_6U_10U_qr_lpi_1_dfm_4, (FpAdd_6U_10U_if_3_if_acc_nl), {FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt + , FpAdd_6U_10U_and_1_rgt , FpAdd_6U_10U_and_2_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4 + <= 10'b0; + end + else if ( core_wen & ((or_tmp_10 & or_5_cse) | and_47_rgt) & (mux_14_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4 + <= MUX_v_10_2_2(FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3, + (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]), and_47_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_6 <= 1'b0; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= 1'b0; + FpMantRNE_23U_11U_else_and_svs_2 <= 1'b0; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_1_aelse_and_cse ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= IsNaN_6U_10U_1_land_lpi_1_dfm_5; + FpAdd_6U_10U_mux_13_itm_6 <= FpAdd_6U_10U_mux_13_itm_5; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= IsNaN_6U_10U_land_lpi_1_dfm_st_5; + FpMantRNE_23U_11U_else_and_svs_2 <= FpMantRNE_23U_11U_else_and_tmp; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= nor_3_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= 6'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_18_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= 6'b0; + end + else if ( core_wen & ((or_61_cse & or_5_cse) | and_51_rgt) & mux_24_cse ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), (chn_b_rsci_d_mxwt[15:10]), + and_51_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3 + <= 10'b0; + end + else if ( core_wen & FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse + & (mux_33_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3 + <= MUX_v_10_2_2((FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1[9:0]), + (FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1[9:0]), and_dcpl_38); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= 6'b0; + end + else if ( core_wen & FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse + & (mux_35_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= MUX_v_6_2_2((FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1[15:10]), + (FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1[15:10]), and_dcpl_38); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_mux_13_itm_4 <= 1'b0; + end + else if ( core_wen & ((or_5_cse & IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) | (or_61_cse + & and_58_m1c) | FpSignedBitsToFloat_6U_10U_or_1_rgt) & mux_24_cse ) begin + FpAdd_6U_10U_mux_13_itm_4 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[16]), (chn_b_rsci_d_mxwt[16]), + FpSignedBitsToFloat_6U_10U_or_1_rgt); + end + end + assign nl_FpMantRNE_23U_11U_else_acc_nl = FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4 + + conv_u2u_1_10(FpMantRNE_23U_11U_else_carry_sva_2); + assign FpMantRNE_23U_11U_else_acc_nl = nl_FpMantRNE_23U_11U_else_acc_nl[9:0]; + assign FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl = MUX_v_10_2_2((FpMantRNE_23U_11U_else_acc_nl), + 10'b1111111111, FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0); + assign FpSignedBitsToFloat_6U_10U_1_and_nl = (~ IsNaN_6U_10U_1_land_lpi_1_dfm_6) + & chn_o_rsci_d_9_0_mx0c1; + assign nl_FpAdd_6U_10U_if_4_if_acc_nl = FpAdd_6U_10U_o_expo_lpi_1_dfm_10 + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_nl = nl_FpAdd_6U_10U_if_4_if_acc_nl[5:0]; + assign FpAdd_6U_10U_and_nl = (~(FpAdd_6U_10U_and_tmp | FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_3_nl = FpAdd_6U_10U_and_tmp & (~ FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_7_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, or_61_cse)); + assign nl_FpAdd_6U_10U_b_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_is_a_greater_oelse_not_5_nl = ~ or_61_cse; + assign FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, (FpAdd_6U_10U_is_a_greater_oelse_not_5_nl))); + assign nl_FpAdd_6U_10U_a_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_else_2_mux_2_nl = MUX_v_23_2_2((~ FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0), + FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign FpAdd_6U_10U_else_2_mux_3_nl = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, + FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign nl_acc_1_nl = ({(~ FpAdd_6U_10U_if_2_and_tmp) , (FpAdd_6U_10U_else_2_mux_2_nl) + , (~ FpAdd_6U_10U_if_2_and_tmp)}) + conv_u2u_24_25({(FpAdd_6U_10U_else_2_mux_3_nl) + , 1'b1}); + assign acc_1_nl = nl_acc_1_nl[24:0]; + assign nor_35_nl = ~(nor_3_cse | (~ main_stage_v_2) | IsNaN_6U_10U_land_lpi_1_dfm_st_5 + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign nor_36_nl = ~((~ main_stage_v_3) | IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4); + assign mux_3_nl = MUX_s_1_2_2((nor_36_nl), (nor_35_nl), or_5_cse); + assign nl_FpNormalize_6U_23U_else_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + ({1'b1 + , (~ libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1)}) + + 6'b1; + assign FpNormalize_6U_23U_else_acc_nl = nl_FpNormalize_6U_23U_else_acc_nl[5:0]; + assign FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl = MUX_v_6_2_2(6'b000000, (FpNormalize_6U_23U_else_acc_nl), + FpNormalize_6U_23U_oelse_not_3); + assign nl_FpAdd_6U_10U_if_3_if_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_nl = nl_FpAdd_6U_10U_if_3_if_acc_nl[5:0]; + assign and_11_nl = main_stage_v_2 & mux_tmp_6; + assign or_18_nl = IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + assign mux_9_nl = MUX_s_1_2_2(mux_tmp_8, (and_11_nl), or_18_nl); + assign mux_10_nl = MUX_s_1_2_2((mux_9_nl), mux_tmp_8, FpMantRNE_23U_11U_else_and_svs_2); + assign mux_11_nl = MUX_s_1_2_2(or_tmp_25, (~ or_5_cse), nor_24_cse); + assign mux_12_nl = MUX_s_1_2_2((mux_11_nl), or_tmp_25, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign nor_25_nl = ~(nor_24_cse | (~ and_41_cse)); + assign mux_13_nl = MUX_s_1_2_2((nor_25_nl), and_41_cse, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign and_84_nl = ((~ FpAdd_6U_10U_is_inf_lpi_1_dfm_4) | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6) & main_stage_v_3; + assign mux_14_nl = MUX_s_1_2_2((mux_13_nl), (mux_12_nl), and_84_nl); + assign or_35_nl = nor_7_cse | nor_tmp_8; + assign nor_22_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_8)); + assign mux_17_nl = MUX_s_1_2_2((nor_22_nl), nor_tmp_8, chn_o_rsci_bawt); + assign and_82_nl = FpAdd_6U_10U_or_cse & main_stage_v_3; + assign mux_18_nl = MUX_s_1_2_2((mux_17_nl), (or_35_nl), and_82_nl); + assign and_91_nl = (~ nor_tmp_8) & reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign mux_31_nl = MUX_s_1_2_2(or_tmp_43, (and_91_nl), IsNaN_6U_10U_1_land_lpi_1_dfm_4); + assign mux_32_nl = MUX_s_1_2_2((~ (mux_31_nl)), or_75_cse, IsNaN_6U_10U_land_lpi_1_dfm_st_4); + assign mux_33_nl = MUX_s_1_2_2((~ or_tmp_43), (mux_32_nl), main_stage_v_1); + assign or_44_nl = IsNaN_6U_10U_land_lpi_1_dfm_st_4 | IsNaN_6U_10U_1_land_lpi_1_dfm_4; + assign mux_34_nl = MUX_s_1_2_2(not_tmp_34, or_75_cse, or_44_nl); + assign mux_35_nl = MUX_s_1_2_2(not_tmp_34, (mux_34_nl), main_stage_v_1); + assign FpAdd_6U_10U_b_right_shift_qif_mux_2_nl = MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), + (chn_b_rsci_d_mxwt[15:10]), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign FpAdd_6U_10U_b_right_shift_qif_mux_3_nl = MUX_v_6_2_2((~ (chn_b_rsci_d_mxwt[15:10])), + (~ (chn_a_rsci_d_mxwt[15:10])), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign nl_acc_nl = ({(FpAdd_6U_10U_b_right_shift_qif_mux_2_nl) , 1'b1}) + ({(FpAdd_6U_10U_b_right_shift_qif_mux_3_nl) + , 1'b1}); + assign acc_nl = nl_acc_nl[6:0]; + assign z_out = readslicef_7_6_1((acc_nl)); + function [5:0] MUX1HOT_v_6_3_2; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [2:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + MUX1HOT_v_6_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_4_2; + input [5:0] input_3; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [3:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + result = result | ( input_3 & {6{sel[3]}}); + MUX1HOT_v_6_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [21:0] MUX_v_22_2_2; + input [21:0] input_0; + input [21:0] input_1; + input [0:0] sel; + reg [21:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_22_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [5:0] MUX_v_6_2_2; + input [5:0] input_0; + input [5:0] input_1; + input [0:0] sel; + reg [5:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_6_2_2 = result; + end + endfunction + function [0:0] readslicef_11_1_10; + input [10:0] vector; + reg [10:0] tmp; + begin + tmp = vector >> 10; + readslicef_11_1_10 = tmp[0:0]; + end + endfunction + function [23:0] readslicef_25_24_1; + input [24:0] vector; + reg [24:0] tmp; + begin + tmp = vector >> 1; + readslicef_25_24_1 = tmp[23:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [5:0] readslicef_7_6_1; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 1; + readslicef_7_6_1 = tmp[5:0]; + end + endfunction + function [6:0] conv_u2s_5_7 ; + input [4:0] vector ; + begin + conv_u2s_5_7 = {{2{1'b0}}, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [6:0] conv_u2u_6_7 ; + input [5:0] vector ; + begin + conv_u2u_6_7 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_10_11 ; + input [9:0] vector ; + begin + conv_u2u_10_11 = {1'b0, vector}; + end + endfunction + function [24:0] conv_u2u_24_25 ; + input [23:0] vector ; + begin + conv_u2u_24_25 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add +// ------------------------------------------------------------------ +module HLS_fp17_add ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP17_ADD_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP17_ADD_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP17_ADD_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_add_core HLS_fp17_add_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_add.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_add.v.vcp new file mode 100644 index 0000000..ea65f62 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_add.v.vcp @@ -0,0 +1,1796 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_add.v +module FP17_ADD_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_ADD_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_ADD_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ../td_ccore_solutions/leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-144 +// Generated date: Sun Dec 11 16:48:02 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_leading_sign_23_0 +// ------------------------------------------------------------------ +module FP17_ADD_leading_sign_23_0 ( + mantissa, rtn +); + input [22:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_10; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[20:19]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[18:17]!=2'b00)); + assign c_h_1_2 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[16:15]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[12:11]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[10:9]!=2'b00)); + assign c_h_1_5 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[8:7]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[4:3]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 = ~((mantissa[2:1]!=2'b00)); + assign c_h_1_9 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + assign c_h_1_10 = c_h_1_6 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl = c_h_1_6 & (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3)) & (c_h_1_9 | (~ c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2)))) & c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl + = ((~((mantissa[22]) | (~((mantissa[21:20]!=2'b01))))) & (~(((mantissa[18]) + | (~((mantissa[17:16]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[14]) | (~((mantissa[13:12]!=2'b01))))) + & (~(((mantissa[10]) | (~((mantissa[9:8]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[6]) | (~((mantissa[5:4]!=2'b01))))) & (~((~((mantissa[2:1]==2'b01))) + & c_h_1_9)))) & c_h_1_10))) | ((~ (mantissa[0])) & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + & c_h_1_9 & c_h_1_10); + assign rtn = {c_h_1_10 , (IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl) + , (IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl)}; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP17_ADD_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP17_ADD_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:49:51 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_ADD_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP17_ADD_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_ADD_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_ADD_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_add_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_add_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_add_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_add_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [16:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [16:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [16:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_17_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 17'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_ADD_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_add_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_add_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [16:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [16:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp17_add_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp HLS_fp17_add_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_add_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_add_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_add_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add_core +// ------------------------------------------------------------------ +module HLS_fp17_add_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [16:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [5:0] chn_o_rsci_d_15_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + wire FpAdd_6U_10U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_23U_11U_else_and_tmp; + wire IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + wire nor_tmp_1; + wire mux_tmp_2; + wire or_tmp_10; + wire mux_tmp_6; + wire mux_tmp_8; + wire or_tmp_25; + wire nor_tmp_8; + wire or_tmp_43; + wire not_tmp_34; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_38; + wire or_tmp_47; + wire or_tmp_53; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_4; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_5; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_6; + reg [23:0] FpAdd_6U_10U_int_mant_p1_sva_3; + reg FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_4; + reg [5:0] FpAdd_6U_10U_o_expo_lpi_1_dfm_10; + reg FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + reg FpMantRNE_23U_11U_else_carry_sva_2; + reg FpMantRNE_23U_11U_else_and_svs_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_6; + reg FpAdd_6U_10U_IsZero_6U_10U_or_itm_2; + reg [6:0] FpAdd_6U_10U_a_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_a_left_shift_acc_itm_2; + reg FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2; + reg [6:0] FpAdd_6U_10U_b_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_b_left_shift_acc_itm_2; + reg [9:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3; + reg [9:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4; + reg FpAdd_6U_10U_mux_13_itm_4; + reg FpAdd_6U_10U_mux_13_itm_5; + reg FpAdd_6U_10U_mux_13_itm_6; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_4; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_5; + reg [15:0] FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1; + reg [15:0] FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1; + wire main_stage_en_1; + wire FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + wire and_58_m1c; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_24_cse; + wire FpAdd_6U_10U_or_cse; + wire nor_3_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_61_cse; + wire or_5_cse; + wire nor_7_cse; + wire and_41_cse; + wire FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt; + wire FpAdd_6U_10U_and_1_rgt; + wire FpAdd_6U_10U_and_2_rgt; + wire and_47_rgt; + wire and_51_rgt; + wire FpSignedBitsToFloat_6U_10U_or_1_rgt; + wire [22:0] FpNormalize_6U_23U_else_lshift_itm; + wire FpAdd_6U_10U_a_right_shift_qelse_and_tmp; + wire [5:0] z_out; + wire FpAdd_6U_10U_if_2_and_tmp; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire FpMantRNE_23U_11U_else_carry_sva_mx0w0; + wire FpAdd_6U_10U_and_tmp; + wire [22:0] FpAdd_6U_10U_addend_larger_asn_1_mx0w1; + wire [22:0] FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_a_int_mant_p1_sva; + wire [21:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0; + wire [22:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1; + wire FpNormalize_6U_23U_oelse_not_3; + wire [4:0] libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1; + wire IsNaN_6U_10U_aelse_and_cse; + wire FpAdd_6U_10U_and_8_cse; + wire IsNaN_6U_10U_1_aelse_and_cse; + wire FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse; + reg reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse; + wire mux_24_cse; + wire or_75_cse; + wire nand_cse; + wire FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + wire FpAdd_6U_10U_if_3_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_if_4_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1; + wire[9:0] FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl; + wire[9:0] FpMantRNE_23U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_23U_11U_else_acc_nl; + wire[0:0] FpSignedBitsToFloat_6U_10U_1_and_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_nl; + wire[0:0] FpAdd_6U_10U_and_nl; + wire[0:0] FpAdd_6U_10U_and_3_nl; + wire[0:0] FpAdd_6U_10U_and_7_nl; + wire[24:0] acc_1_nl; + wire[25:0] nl_acc_1_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_2_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_3_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_35_nl; + wire[0:0] nor_36_nl; + wire[5:0] FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl; + wire[5:0] FpNormalize_6U_23U_else_acc_nl; + wire[7:0] nl_FpNormalize_6U_23U_else_acc_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_nl; + wire[0:0] mux_10_nl; + wire[0:0] mux_9_nl; + wire[0:0] and_11_nl; + wire[0:0] or_18_nl; + wire[0:0] mux_14_nl; + wire[0:0] mux_12_nl; + wire[0:0] mux_11_nl; + wire[0:0] mux_13_nl; + wire[0:0] nor_25_nl; + wire[0:0] and_84_nl; + wire[0:0] mux_16_nl; + wire[0:0] or_31_nl; + wire[0:0] mux_15_nl; + wire[0:0] nor_23_nl; + wire[0:0] mux_18_nl; + wire[0:0] or_35_nl; + wire[0:0] mux_17_nl; + wire[0:0] nor_22_nl; + wire[0:0] and_82_nl; + wire[0:0] or_1_nl; + wire[0:0] mux_nl; + wire[0:0] nor_39_nl; + wire[5:0] FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[5:0] FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[0:0] FpAdd_6U_10U_is_a_greater_oelse_not_5_nl; + wire[0:0] mux_33_nl; + wire[0:0] mux_32_nl; + wire[0:0] mux_31_nl; + wire[0:0] and_91_nl; + wire[0:0] mux_35_nl; + wire[0:0] mux_34_nl; + wire[0:0] or_44_nl; + wire[6:0] FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[8:0] nl_FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[0:0] FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl; + wire[6:0] FpNormalize_6U_23U_acc_nl; + wire[8:0] nl_FpNormalize_6U_23U_acc_nl; + wire[0:0] or_3_nl; + wire[0:0] nor_38_nl; + wire[0:0] nor_33_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_34_nl; + wire[0:0] mux_7_nl; + wire[0:0] or_13_nl; + wire[0:0] mux_4_nl; + wire[0:0] nor_31_nl; + wire[0:0] nor_32_nl; + wire[10:0] FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[12:0] nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[6:0] acc_nl; + wire[7:0] nl_acc_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_2_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_3_nl; +// Interconnect Declarations for Component Instantiations + wire [22:0] nl_leading_sign_23_0_rg_mantissa; + assign nl_leading_sign_23_0_rg_mantissa = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [10:0] nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 + , (FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1[9:0])}; + wire [10:0] nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 + , (FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1[9:0])}; + wire [22:0] nl_FpNormalize_6U_23U_else_lshift_rg_a; + assign nl_FpNormalize_6U_23U_else_lshift_rg_a = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [16:0] nl_HLS_fp17_add_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_add_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 , chn_o_rsci_d_15_10 + , chn_o_rsci_d_9_0}; + FP17_ADD_leading_sign_23_0 leading_sign_23_0_rg ( + .mantissa(nl_leading_sign_23_0_rg_mantissa[22:0]), + .rtn(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + ); + FP17_ADD_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_b_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_addend_larger_asn_1_mx0w1) + ); + FP17_ADD_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_a_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_a_int_mant_p1_sva) + ); + FP17_ADD_mgc_shift_l_v4 #(.width_a(32'sd23), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd23)) FpNormalize_6U_23U_else_lshift_rg ( + .a(nl_FpNormalize_6U_23U_else_lshift_rg_a[22:0]), + .s(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1), + .z(FpNormalize_6U_23U_else_lshift_itm) + ); + HLS_fp17_add_core_chn_a_rsci HLS_fp17_add_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_add_core_chn_b_rsci HLS_fp17_add_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp17_add_core_chn_o_rsci HLS_fp17_add_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_add_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp17_add_core_staller HLS_fp17_add_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_add_core_core_fsm HLS_fp17_add_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_6U_10U_or_cse = IsNaN_6U_10U_1_land_lpi_1_dfm_6 | IsNaN_6U_10U_land_lpi_1_dfm_6; + assign IsNaN_6U_10U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_24_cse; + assign FpAdd_6U_10U_and_8_cse = core_wen & (~ and_dcpl_7) & mux_tmp_2; + assign and_41_cse = or_5_cse & main_stage_v_2; + assign nor_3_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23]))); + assign or_5_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + | and_dcpl_7); + assign FpAdd_6U_10U_and_1_rgt = (~ FpAdd_6U_10U_if_3_if_acc_1_itm_5_1) & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign FpAdd_6U_10U_and_2_rgt = FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign nor_24_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23])) + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign and_47_rgt = (~(IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_5)) + & or_5_cse; + assign or_31_nl = nor_7_cse | main_stage_v_2; + assign nor_23_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_15_nl = MUX_s_1_2_2((nor_23_nl), main_stage_v_2, chn_o_rsci_bawt); + assign mux_16_nl = MUX_s_1_2_2((mux_15_nl), (or_31_nl), main_stage_v_3); + assign IsNaN_6U_10U_1_aelse_and_cse = core_wen & (~ and_dcpl_7) & (mux_16_nl); + assign nor_7_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_61_cse = (FpAdd_6U_10U_is_a_greater_oif_equal_tmp & (~ FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1)) + | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + assign and_51_rgt = or_5_cse & (~ FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1) & ((~ + FpAdd_6U_10U_is_a_greater_oif_equal_tmp) | FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1); + assign or_1_nl = nor_7_cse | nor_tmp_1; + assign nor_39_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_1)); + assign mux_nl = MUX_s_1_2_2((nor_39_nl), nor_tmp_1, chn_o_rsci_bawt); + assign mux_24_cse = MUX_s_1_2_2((mux_nl), (or_1_nl), main_stage_v_1); + assign FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse = (or_5_cse + & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_4)) | and_dcpl_38; + assign or_75_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | nor_tmp_8; + assign and_58_m1c = or_5_cse & (~(IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp)); + assign FpSignedBitsToFloat_6U_10U_or_1_rgt = (or_5_cse & (~ IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) + & IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp) | ((~ or_61_cse) & and_58_m1c); + assign FpAdd_6U_10U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[15:10]) == + (chn_b_rsci_d_mxwt[15:10]); + assign IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_a_rsci_d_mxwt[15:10]!=6'b111111)); + assign FpMantRNE_23U_11U_else_carry_sva_mx0w0 = (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[11]) + & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[0]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[1]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[2]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[3]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[4]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[5]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[6]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[7]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[8]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[9]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[10]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[12])); + assign FpMantRNE_23U_11U_else_and_tmp = FpMantRNE_23U_11U_else_carry_sva_mx0w0 + & (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]==10'b1111111111) & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[22]) + | (FpAdd_6U_10U_int_mant_p1_sva_3[23])); + assign IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp = ~((~((chn_b_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_b_rsci_d_mxwt[15:10]!=6'b111111)); + assign nl_FpAdd_6U_10U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[15:10])}) + + conv_u2u_6_7(~ (chn_a_rsci_d_mxwt[15:10])) + 7'b1; + assign FpAdd_6U_10U_is_a_greater_acc_1_nl = nl_FpAdd_6U_10U_is_a_greater_acc_1_nl[6:0]; + assign FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1 = readslicef_7_1_6((FpAdd_6U_10U_is_a_greater_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_qr_lpi_1_dfm_4[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_1_nl = nl_FpAdd_6U_10U_if_3_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_3_if_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_o_expo_lpi_1_dfm_10[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_1_nl = nl_FpAdd_6U_10U_if_4_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_4_if_acc_1_nl)); + assign FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_4 + | (~ FpAdd_6U_10U_if_4_if_acc_1_itm_5_1); + assign FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_6U_10U_is_inf_lpi_1_dfm_4, + (FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl), FpMantRNE_23U_11U_else_and_svs_2); + assign FpAdd_6U_10U_and_tmp = FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 & FpMantRNE_23U_11U_else_and_svs_2; + assign FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c = ~(IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_5_cse; + assign FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_asn_1_mx0w1, + FpAdd_6U_10U_a_int_mant_p1_sva, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_a_int_mant_p1_sva, + FpAdd_6U_10U_addend_larger_asn_1_mx0w1, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0 = MUX_v_22_2_2((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[21:0]), + (FpAdd_6U_10U_int_mant_p1_sva_3[22:1]), FpAdd_6U_10U_int_mant_p1_sva_3[23]); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1 = MUX_v_23_2_2(23'b00000000000000000000000, + FpNormalize_6U_23U_else_lshift_itm, FpNormalize_6U_23U_oelse_not_3); + assign nl_FpNormalize_6U_23U_acc_nl = ({1'b1 , (~ FpAdd_6U_10U_qr_lpi_1_dfm_4)}) + + conv_u2s_5_7(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + + 7'b1; + assign FpNormalize_6U_23U_acc_nl = nl_FpNormalize_6U_23U_acc_nl[6:0]; + assign FpNormalize_6U_23U_oelse_not_3 = ((FpAdd_6U_10U_int_mant_p1_sva_3[22:0]!=23'b00000000000000000000000)) + & (readslicef_7_1_6((FpNormalize_6U_23U_acc_nl))); + assign nor_tmp_1 = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_3_nl = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | main_stage_v_2; + assign nor_38_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2))); + assign mux_tmp_2 = MUX_s_1_2_2((nor_38_nl), (or_3_nl), main_stage_v_1); + assign or_tmp_10 = IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_5; + assign nor_34_nl = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) | (~ or_5_cse)); + assign mux_5_nl = MUX_s_1_2_2((nor_34_nl), or_5_cse, FpAdd_6U_10U_if_3_if_acc_1_itm_5_1); + assign nor_33_nl = ~(or_tmp_10 | (~ (mux_5_nl))); + assign mux_tmp_6 = MUX_s_1_2_2((nor_33_nl), or_5_cse, FpMantRNE_23U_11U_else_and_tmp); + assign nor_31_nl = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & or_5_cse))); + assign mux_4_nl = MUX_s_1_2_2((nor_31_nl), or_5_cse, or_tmp_10); + assign or_13_nl = FpMantRNE_23U_11U_else_and_tmp | (~ (mux_4_nl)); + assign mux_7_nl = MUX_s_1_2_2(mux_tmp_6, (or_13_nl), main_stage_v_3); + assign nor_32_nl = ~((~ main_stage_v_3) | (~ reg_chn_o_rsci_ld_core_psct_cse) | + chn_o_rsci_bawt); + assign mux_tmp_8 = MUX_s_1_2_2((nor_32_nl), (mux_7_nl), main_stage_v_2); + assign or_tmp_25 = main_stage_v_2 | (~ or_5_cse); + assign nor_tmp_8 = or_tmp_10 & main_stage_v_2; + assign nand_cse = ~(reg_chn_o_rsci_ld_core_psct_cse & nor_tmp_8); + assign or_tmp_43 = chn_o_rsci_bawt | nand_cse; + assign not_tmp_34 = ~(chn_o_rsci_bawt | nand_cse); + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_5_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign and_dcpl_38 = or_5_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_4; + assign or_tmp_47 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_53 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_5_cse & (fsm_output[1]); + assign chn_o_rsci_d_9_0_mx0c1 = or_5_cse & main_stage_v_3 & (~ IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_b_rsci_bawt & chn_a_rsci_bawt)) & or_5_cse + & main_stage_v_1; + assign main_stage_v_2_mx0c1 = or_5_cse & main_stage_v_2 & (~ main_stage_v_1); + assign main_stage_v_3_mx0c1 = or_5_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[9:0])}) + + conv_u2u_10_11(~ (chn_b_rsci_d_mxwt[9:0])) + 11'b1; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl[10:0]; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 = readslicef_11_1_10((FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_53; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + assign FpAdd_6U_10U_a_right_shift_qelse_and_tmp = (fsm_output[1]) & (~((~(FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 + | (~ FpAdd_6U_10U_is_a_greater_oif_equal_tmp))) | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1)); + assign FpAdd_6U_10U_if_2_and_tmp = (fsm_output[1]) & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_47 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_47; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_3 & IsNaN_6U_10U_land_lpi_1_dfm_6) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4, + (FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl), FpSignedBitsToFloat_6U_10U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15_10 <= 6'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_15_10 <= MUX1HOT_v_6_4_2(FpAdd_6U_10U_o_expo_lpi_1_dfm_10, (FpAdd_6U_10U_if_4_if_acc_nl), + 6'b111110, FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4, + {(FpAdd_6U_10U_and_nl) , (FpAdd_6U_10U_and_3_nl) , (FpAdd_6U_10U_and_7_nl) + , FpAdd_6U_10U_or_cse}); + chn_o_rsci_d_16 <= FpAdd_6U_10U_mux_13_itm_6; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_53 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= 1'b0; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse <= + 1'b0; + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= 1'b0; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= 1'b0; + FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= 7'b0; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= 1'b0; + FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= 7'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_aelse_and_cse ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse <= + ~((chn_a_rsci_d_mxwt[16]) ^ (chn_b_rsci_d_mxwt[16])); + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= or_61_cse; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[15:0]!=16'b0000000000000000); + FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1 <= chn_b_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_b_left_shift_acc_itm_2[6:0]; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= (chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000); + FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1 <= chn_a_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_a_left_shift_acc_itm_2[6:0]; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= 6'b0; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= 1'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_5 <= 1'b0; + end + else if ( FpAdd_6U_10U_and_8_cse ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= FpAdd_6U_10U_qr_lpi_1_dfm_3; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= IsNaN_6U_10U_land_lpi_1_dfm_st_4; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= IsNaN_6U_10U_1_land_lpi_1_dfm_4; + FpAdd_6U_10U_mux_13_itm_5 <= FpAdd_6U_10U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= 24'b0; + end + else if ( core_wen & (~((~(or_5_cse & (~ reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse))) + & (~(or_5_cse & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xnor_svs_st_1_cse)))) + & mux_tmp_2 ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= readslicef_25_24_1((acc_1_nl)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & (and_41_cse | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_3_nl) ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= FpMantRNE_23U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= 6'b0; + end + else if ( core_wen & (FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt | FpAdd_6U_10U_and_1_rgt + | FpAdd_6U_10U_and_2_rgt) & (mux_10_nl) ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= MUX1HOT_v_6_3_2((FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl), + FpAdd_6U_10U_qr_lpi_1_dfm_4, (FpAdd_6U_10U_if_3_if_acc_nl), {FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt + , FpAdd_6U_10U_and_1_rgt , FpAdd_6U_10U_and_2_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4 + <= 10'b0; + end + else if ( core_wen & ((or_tmp_10 & or_5_cse) | and_47_rgt) & (mux_14_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4 + <= MUX_v_10_2_2(FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3, + (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]), and_47_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_6 <= 1'b0; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= 1'b0; + FpMantRNE_23U_11U_else_and_svs_2 <= 1'b0; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_1_aelse_and_cse ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= IsNaN_6U_10U_1_land_lpi_1_dfm_5; + FpAdd_6U_10U_mux_13_itm_6 <= FpAdd_6U_10U_mux_13_itm_5; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= IsNaN_6U_10U_land_lpi_1_dfm_st_5; + FpMantRNE_23U_11U_else_and_svs_2 <= FpMantRNE_23U_11U_else_and_tmp; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= nor_3_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= 6'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_18_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= 6'b0; + end + else if ( core_wen & ((or_61_cse & or_5_cse) | and_51_rgt) & mux_24_cse ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), (chn_b_rsci_d_mxwt[15:10]), + and_51_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3 + <= 10'b0; + end + else if ( core_wen & FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse + & (mux_33_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_3 + <= MUX_v_10_2_2((FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1[9:0]), + (FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1[9:0]), and_dcpl_38); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= 6'b0; + end + else if ( core_wen & FpSignedBitsToFloat_6U_10U_1_FpSignedBitsToFloat_6U_10U_1_or_1_cse + & (mux_35_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= MUX_v_6_2_2((FpSignedBitsToFloat_6U_10U_bits_1_sva_1_15_0_1[15:10]), + (FpSignedBitsToFloat_6U_10U_bits_sva_1_15_0_1[15:10]), and_dcpl_38); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_mux_13_itm_4 <= 1'b0; + end + else if ( core_wen & ((or_5_cse & IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) | (or_61_cse + & and_58_m1c) | FpSignedBitsToFloat_6U_10U_or_1_rgt) & mux_24_cse ) begin + FpAdd_6U_10U_mux_13_itm_4 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[16]), (chn_b_rsci_d_mxwt[16]), + FpSignedBitsToFloat_6U_10U_or_1_rgt); + end + end + assign nl_FpMantRNE_23U_11U_else_acc_nl = FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_4 + + conv_u2u_1_10(FpMantRNE_23U_11U_else_carry_sva_2); + assign FpMantRNE_23U_11U_else_acc_nl = nl_FpMantRNE_23U_11U_else_acc_nl[9:0]; + assign FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl = MUX_v_10_2_2((FpMantRNE_23U_11U_else_acc_nl), + 10'b1111111111, FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0); + assign FpSignedBitsToFloat_6U_10U_1_and_nl = (~ IsNaN_6U_10U_1_land_lpi_1_dfm_6) + & chn_o_rsci_d_9_0_mx0c1; + assign nl_FpAdd_6U_10U_if_4_if_acc_nl = FpAdd_6U_10U_o_expo_lpi_1_dfm_10 + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_nl = nl_FpAdd_6U_10U_if_4_if_acc_nl[5:0]; + assign FpAdd_6U_10U_and_nl = (~(FpAdd_6U_10U_and_tmp | FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_3_nl = FpAdd_6U_10U_and_tmp & (~ FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_7_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, or_61_cse)); + assign nl_FpAdd_6U_10U_b_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_is_a_greater_oelse_not_5_nl = ~ or_61_cse; + assign FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, (FpAdd_6U_10U_is_a_greater_oelse_not_5_nl))); + assign nl_FpAdd_6U_10U_a_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_else_2_mux_2_nl = MUX_v_23_2_2((~ FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0), + FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign FpAdd_6U_10U_else_2_mux_3_nl = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, + FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign nl_acc_1_nl = ({(~ FpAdd_6U_10U_if_2_and_tmp) , (FpAdd_6U_10U_else_2_mux_2_nl) + , (~ FpAdd_6U_10U_if_2_and_tmp)}) + conv_u2u_24_25({(FpAdd_6U_10U_else_2_mux_3_nl) + , 1'b1}); + assign acc_1_nl = nl_acc_1_nl[24:0]; + assign nor_35_nl = ~(nor_3_cse | (~ main_stage_v_2) | IsNaN_6U_10U_land_lpi_1_dfm_st_5 + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign nor_36_nl = ~((~ main_stage_v_3) | IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4); + assign mux_3_nl = MUX_s_1_2_2((nor_36_nl), (nor_35_nl), or_5_cse); + assign nl_FpNormalize_6U_23U_else_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + ({1'b1 + , (~ libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1)}) + + 6'b1; + assign FpNormalize_6U_23U_else_acc_nl = nl_FpNormalize_6U_23U_else_acc_nl[5:0]; + assign FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl = MUX_v_6_2_2(6'b000000, (FpNormalize_6U_23U_else_acc_nl), + FpNormalize_6U_23U_oelse_not_3); + assign nl_FpAdd_6U_10U_if_3_if_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_nl = nl_FpAdd_6U_10U_if_3_if_acc_nl[5:0]; + assign and_11_nl = main_stage_v_2 & mux_tmp_6; + assign or_18_nl = IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + assign mux_9_nl = MUX_s_1_2_2(mux_tmp_8, (and_11_nl), or_18_nl); + assign mux_10_nl = MUX_s_1_2_2((mux_9_nl), mux_tmp_8, FpMantRNE_23U_11U_else_and_svs_2); + assign mux_11_nl = MUX_s_1_2_2(or_tmp_25, (~ or_5_cse), nor_24_cse); + assign mux_12_nl = MUX_s_1_2_2((mux_11_nl), or_tmp_25, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign nor_25_nl = ~(nor_24_cse | (~ and_41_cse)); + assign mux_13_nl = MUX_s_1_2_2((nor_25_nl), and_41_cse, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign and_84_nl = ((~ FpAdd_6U_10U_is_inf_lpi_1_dfm_4) | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6) & main_stage_v_3; + assign mux_14_nl = MUX_s_1_2_2((mux_13_nl), (mux_12_nl), and_84_nl); + assign or_35_nl = nor_7_cse | nor_tmp_8; + assign nor_22_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_8)); + assign mux_17_nl = MUX_s_1_2_2((nor_22_nl), nor_tmp_8, chn_o_rsci_bawt); + assign and_82_nl = FpAdd_6U_10U_or_cse & main_stage_v_3; + assign mux_18_nl = MUX_s_1_2_2((mux_17_nl), (or_35_nl), and_82_nl); + assign and_91_nl = (~ nor_tmp_8) & reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign mux_31_nl = MUX_s_1_2_2(or_tmp_43, (and_91_nl), IsNaN_6U_10U_1_land_lpi_1_dfm_4); + assign mux_32_nl = MUX_s_1_2_2((~ (mux_31_nl)), or_75_cse, IsNaN_6U_10U_land_lpi_1_dfm_st_4); + assign mux_33_nl = MUX_s_1_2_2((~ or_tmp_43), (mux_32_nl), main_stage_v_1); + assign or_44_nl = IsNaN_6U_10U_land_lpi_1_dfm_st_4 | IsNaN_6U_10U_1_land_lpi_1_dfm_4; + assign mux_34_nl = MUX_s_1_2_2(not_tmp_34, or_75_cse, or_44_nl); + assign mux_35_nl = MUX_s_1_2_2(not_tmp_34, (mux_34_nl), main_stage_v_1); + assign FpAdd_6U_10U_b_right_shift_qif_mux_2_nl = MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), + (chn_b_rsci_d_mxwt[15:10]), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign FpAdd_6U_10U_b_right_shift_qif_mux_3_nl = MUX_v_6_2_2((~ (chn_b_rsci_d_mxwt[15:10])), + (~ (chn_a_rsci_d_mxwt[15:10])), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign nl_acc_nl = ({(FpAdd_6U_10U_b_right_shift_qif_mux_2_nl) , 1'b1}) + ({(FpAdd_6U_10U_b_right_shift_qif_mux_3_nl) + , 1'b1}); + assign acc_nl = nl_acc_nl[6:0]; + assign z_out = readslicef_7_6_1((acc_nl)); + function [5:0] MUX1HOT_v_6_3_2; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [2:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + MUX1HOT_v_6_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_4_2; + input [5:0] input_3; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [3:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + result = result | ( input_3 & {6{sel[3]}}); + MUX1HOT_v_6_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [21:0] MUX_v_22_2_2; + input [21:0] input_0; + input [21:0] input_1; + input [0:0] sel; + reg [21:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_22_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [5:0] MUX_v_6_2_2; + input [5:0] input_0; + input [5:0] input_1; + input [0:0] sel; + reg [5:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_6_2_2 = result; + end + endfunction + function [0:0] readslicef_11_1_10; + input [10:0] vector; + reg [10:0] tmp; + begin + tmp = vector >> 10; + readslicef_11_1_10 = tmp[0:0]; + end + endfunction + function [23:0] readslicef_25_24_1; + input [24:0] vector; + reg [24:0] tmp; + begin + tmp = vector >> 1; + readslicef_25_24_1 = tmp[23:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [5:0] readslicef_7_6_1; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 1; + readslicef_7_6_1 = tmp[5:0]; + end + endfunction + function [6:0] conv_u2s_5_7 ; + input [4:0] vector ; + begin + conv_u2s_5_7 = {{2{1'b0}}, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [6:0] conv_u2u_6_7 ; + input [5:0] vector ; + begin + conv_u2u_6_7 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_10_11 ; + input [9:0] vector ; + begin + conv_u2u_10_11 = {1'b0, vector}; + end + endfunction + function [24:0] conv_u2u_24_25 ; + input [23:0] vector ; + begin + conv_u2u_24_25 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_add +// ------------------------------------------------------------------ +module HLS_fp17_add ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP17_ADD_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP17_ADD_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP17_ADD_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_add_core HLS_fp17_add_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_mul.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_mul.v new file mode 100644 index 0000000..8fafe54 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_mul.v @@ -0,0 +1,1532 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_mul.v +module FP17_MUL_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_MUL_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_MUL_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:52:26 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_MUL_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_MUL_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_MUL_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP17_MUL_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_MUL_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_MUL_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_mul_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_mul_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [16:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [16:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [16:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_17_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 17'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_MUL_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [16:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [16:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core +// ------------------------------------------------------------------ +module HLS_fp17_mul_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [16:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [5:0] chn_o_rsci_d_15_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire IsNaN_6U_10U_nor_tmp; + wire FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp; + wire [21:0] FpMul_6U_10U_p_mant_p1_mul_tmp; + wire IsNaN_6U_10U_1_nor_tmp; + wire nor_tmp_1; + wire or_tmp_4; + wire mux_tmp_3; + wire or_tmp_7; + wire or_tmp_16; + wire mux_tmp_6; + wire mux_tmp_7; + wire nor_tmp_11; + wire or_tmp_32; + wire or_tmp_40; + wire mux_tmp_21; + wire mux_tmp_23; + wire or_tmp_48; + wire or_tmp_49; + wire or_tmp_52; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire or_tmp_56; + wire or_tmp_62; + wire or_tmp_68; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs; + reg [21:0] FpMul_6U_10U_p_mant_p1_sva; + reg main_stage_v_1; + reg main_stage_v_2; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_3; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_4; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_3; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_4; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4; + reg [21:0] FpMul_6U_10U_p_mant_p1_sva_2; + reg [5:0] FpMul_6U_10U_p_expo_sva_5; + wire [6:0] nl_FpMul_6U_10U_p_expo_sva_5; + reg IsNaN_6U_10U_land_lpi_1_dfm_4; + reg [5:0] FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2; + reg FpMul_6U_10U_mux_10_itm_3; + reg FpMul_6U_10U_mux_10_itm_4; + reg [9:0] FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_st_3; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_st_4; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4; + reg FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_3; + reg [15:0] FpMul_6U_10U_ua_sva_1_15_0_1; + reg [15:0] FpMul_6U_10U_ub_sva_1_15_0_1; + wire main_stage_en_1; + wire FpMantRNE_22U_11U_else_and_svs; + wire FpMul_6U_10U_is_inf_lpi_1_dfm_2; + wire FpMantRNE_22U_11U_else_carry_sva; + wire [5:0] FpMul_6U_10U_o_expo_lpi_1_dfm; + wire FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp; + wire [5:0] FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1; + wire [6:0] nl_FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1; + wire [19:0] FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_cse; + wire nor_42_cse; + wire or_65_cse; + wire nor_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_68_cse; + wire or_5_cse; + wire nand_cse; + wire FpMul_6U_10U_or_2_cse; + wire IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse; + wire nand_7_cse; + wire nand_6_cse; + wire and_40_rgt; + wire and_45_rgt; + wire and_52_rgt; + wire and_60_rgt; + wire and_61_rgt; + wire chn_o_rsci_d_15_10_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire [5:0] FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0; + wire FpMul_6U_10U_lor_2_lpi_1_dfm; + wire IsNaN_6U_10U_aelse_and_cse; + wire IsNaN_6U_10U_1_aelse_and_cse; + wire FpMul_6U_10U_oelse_1_and_1_cse; + wire FpBitsToFloat_6U_10U_1_and_1_cse; + wire FpMul_6U_10U_else_2_if_acc_itm_6_1; + wire FpMul_6U_10U_oelse_1_acc_itm_7_1; + wire FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[9:0] FpMul_6U_10U_FpMul_6U_10U_FpMul_6U_10U_nor_1_nl; + wire[9:0] FpMul_6U_10U_nor_nl; + wire[9:0] mux_37_nl; + wire[9:0] FpMantRNE_22U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_22U_11U_else_acc_nl; + wire[0:0] or_nl; + wire[5:0] FpMul_6U_10U_FpMul_6U_10U_and_2_nl; + wire[0:0] FpMul_6U_10U_oelse_2_not_1_nl; + wire[0:0] FpBitsToFloat_6U_10U_1_and_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_2_nl; + wire[0:0] mux_1_nl; + wire[0:0] mux_nl; + wire[5:0] FpMul_6U_10U_else_2_else_acc_2_nl; + wire[6:0] nl_FpMul_6U_10U_else_2_else_acc_2_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_41_nl; + wire[0:0] mux_4_nl; + wire[0:0] nor_43_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_39_nl; + wire[0:0] mux_8_nl; + wire[0:0] mux_11_nl; + wire[0:0] nor_38_nl; + wire[0:0] mux_10_nl; + wire[0:0] nor_6_nl; + wire[0:0] mux_13_nl; + wire[0:0] or_25_nl; + wire[0:0] mux_12_nl; + wire[0:0] nor_37_nl; + wire[0:0] and_97_nl; + wire[0:0] mux_17_nl; + wire[0:0] mux_16_nl; + wire[0:0] nor_35_nl; + wire[0:0] or_35_nl; + wire[0:0] nor_15_nl; + wire[0:0] mux_20_nl; + wire[0:0] or_38_nl; + wire[0:0] mux_19_nl; + wire[0:0] mux_18_nl; + wire[0:0] mux_35_nl; + wire[0:0] and_91_nl; + wire[0:0] FpMul_6U_10U_xor_1_nl; + wire[0:0] mux_29_nl; + wire[0:0] mux_26_nl; + wire[0:0] mux_25_nl; + wire[0:0] mux_28_nl; + wire[0:0] mux_27_nl; + wire[0:0] mux_33_nl; + wire[0:0] mux_31_nl; + wire[0:0] mux_30_nl; + wire[0:0] mux_32_nl; + wire[0:0] nor_33_nl; + wire[6:0] FpMul_6U_10U_else_2_if_acc_nl; + wire[7:0] nl_FpMul_6U_10U_else_2_if_acc_nl; + wire[6:0] FpMul_6U_10U_else_2_acc_1_nl; + wire[7:0] nl_FpMul_6U_10U_else_2_acc_1_nl; + wire[7:0] FpMul_6U_10U_oelse_1_acc_nl; + wire[8:0] nl_FpMul_6U_10U_oelse_1_acc_nl; + wire[6:0] FpMul_6U_10U_oelse_1_acc_1_nl; + wire[7:0] nl_FpMul_6U_10U_oelse_1_acc_1_nl; + wire[5:0] FpMul_6U_10U_else_2_else_if_if_acc_1_nl; + wire[6:0] nl_FpMul_6U_10U_else_2_else_if_if_acc_1_nl; + wire[5:0] FpMul_6U_10U_else_2_else_if_if_acc_nl; + wire[6:0] nl_FpMul_6U_10U_else_2_else_if_if_acc_nl; + wire[0:0] and_62_nl; + wire[0:0] mux_36_nl; + wire[0:0] FpMul_6U_10U_FpMul_6U_10U_nor_1_nl; + wire[0:0] FpMul_6U_10U_or_1_nl; + wire[0:0] FpMantWidthDec_6U_21U_10U_0U_0U_and_1_nl; + wire[0:0] nor_40_nl; + wire[0:0] and_93_nl; + wire[0:0] mux_22_nl; + wire[0:0] and_94_nl; + wire[0:0] nor_34_nl; +// Interconnect Declarations for Component Instantiations + wire [16:0] nl_HLS_fp17_mul_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_mul_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 , chn_o_rsci_d_15_10 + , chn_o_rsci_d_9_0}; + HLS_fp17_mul_core_chn_a_rsci HLS_fp17_mul_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_mul_core_chn_b_rsci HLS_fp17_mul_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp17_mul_core_chn_o_rsci HLS_fp17_mul_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_mul_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp17_mul_core_staller HLS_fp17_mul_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_mul_core_core_fsm HLS_fp17_mul_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, main_stage_en_1 & (fsm_output[1]))), fsm_output[1]); +// assert(iMantWidth > oMantWidth) - ../include/nvdla_float.h: line 386 +// PSL HLS_fp17_mul_core_nvdla_float_h_ln386_assert_iMantWidth_gt_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_2))); + assign FpMul_6U_10U_or_2_cse = IsNaN_6U_10U_1_land_lpi_1_dfm_4 | IsNaN_6U_10U_land_lpi_1_dfm_4; + assign nor_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign IsNaN_6U_10U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_tmp_3; + assign nor_42_cse = ~((~ main_stage_v_2) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | + (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4)); + assign or_5_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign or_65_cse = FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3); + assign and_40_rgt = or_5_cse & or_65_cse; + assign or_25_nl = nor_cse | nor_tmp_11; + assign nor_37_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_11)); + assign mux_12_nl = MUX_s_1_2_2((nor_37_nl), nor_tmp_11, chn_o_rsci_bawt); + assign and_97_nl = FpMul_6U_10U_or_2_cse & main_stage_v_2; + assign mux_13_nl = MUX_s_1_2_2((mux_12_nl), (or_25_nl), and_97_nl); + assign FpBitsToFloat_6U_10U_1_and_1_cse = core_wen & ((or_5_cse & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_3)) + | and_dcpl_28) & (mux_13_nl); + assign IsNaN_6U_10U_1_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_tmp_7; + assign nor_35_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ or_tmp_32)); + assign mux_16_nl = MUX_s_1_2_2((nor_35_nl), or_tmp_32, chn_o_rsci_bawt); + assign or_35_nl = nor_cse | IsNaN_6U_10U_1_land_lpi_1_dfm_3 | IsNaN_6U_10U_land_lpi_1_dfm_st_3 + | (~ main_stage_v_1); + assign nor_15_nl = ~(IsNaN_6U_10U_1_land_lpi_1_dfm_4 | IsNaN_6U_10U_land_lpi_1_dfm_4 + | (~ main_stage_v_2)); + assign mux_17_nl = MUX_s_1_2_2((or_35_nl), (mux_16_nl), nor_15_nl); + assign FpMul_6U_10U_oelse_1_and_1_cse = core_wen & (~ and_dcpl_7) & (~ (mux_17_nl)); + assign or_68_cse = FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | FpMul_6U_10U_oelse_1_acc_itm_7_1; + assign and_45_rgt = or_68_cse & or_5_cse; + assign IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse = ~((chn_b_rsci_d_mxwt[15:10]==6'b111111)); + assign nand_cse = ~((chn_a_rsci_d_mxwt[15:10]==6'b111111)); + assign and_52_rgt = or_5_cse & (chn_a_rsci_d_mxwt[15:10]==6'b111111) & (~ IsNaN_6U_10U_nor_tmp); + assign and_60_rgt = ((chn_a_rsci_d_mxwt[15:10]!=6'b111111) | IsNaN_6U_10U_nor_tmp) + & (chn_b_rsci_d_mxwt[15:10]==6'b111111) & (~ IsNaN_6U_10U_1_nor_tmp) & or_5_cse; + assign and_91_nl = nand_cse & or_tmp_56; + assign mux_35_nl = MUX_s_1_2_2((and_91_nl), or_tmp_56, IsNaN_6U_10U_nor_tmp); + assign and_61_rgt = (mux_35_nl) & or_5_cse; + assign nand_7_cse = ~(FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 + & main_stage_v_1); + assign nand_6_cse = ~(chn_a_rsci_bawt & chn_b_rsci_bawt); + assign nl_FpMul_6U_10U_else_2_acc_1_nl = conv_u2u_6_7(chn_a_rsci_d_mxwt[15:10]) + + conv_u2u_6_7(chn_b_rsci_d_mxwt[15:10]); + assign FpMul_6U_10U_else_2_acc_1_nl = nl_FpMul_6U_10U_else_2_acc_1_nl[6:0]; + assign nl_FpMul_6U_10U_else_2_if_acc_nl = conv_u2u_6_7(readslicef_7_6_1((FpMul_6U_10U_else_2_acc_1_nl))) + + 7'b1010001; + assign FpMul_6U_10U_else_2_if_acc_nl = nl_FpMul_6U_10U_else_2_if_acc_nl[6:0]; + assign FpMul_6U_10U_else_2_if_acc_itm_6_1 = readslicef_7_1_6((FpMul_6U_10U_else_2_if_acc_nl)); + assign IsNaN_6U_10U_nor_tmp = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign FpMul_6U_10U_p_mant_p1_mul_tmp = conv_u2u_22_22(({1'b1 , (FpMul_6U_10U_ua_sva_1_15_0_1[9:0])}) + * ({1'b1 , (FpMul_6U_10U_ub_sva_1_15_0_1[9:0])})); + assign IsNaN_6U_10U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign nl_FpMul_6U_10U_oelse_1_acc_1_nl = conv_u2s_6_7(chn_b_rsci_d_mxwt[15:10]) + + 7'b1100001; + assign FpMul_6U_10U_oelse_1_acc_1_nl = nl_FpMul_6U_10U_oelse_1_acc_1_nl[6:0]; + assign nl_FpMul_6U_10U_oelse_1_acc_nl = conv_s2s_7_8(FpMul_6U_10U_oelse_1_acc_1_nl) + + conv_u2s_6_8(chn_a_rsci_d_mxwt[15:10]); + assign FpMul_6U_10U_oelse_1_acc_nl = nl_FpMul_6U_10U_oelse_1_acc_nl[7:0]; + assign FpMul_6U_10U_oelse_1_acc_itm_7_1 = readslicef_8_1_7((FpMul_6U_10U_oelse_1_acc_nl)); + assign FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp = (~((chn_b_rsci_d_mxwt[15:0]!=16'b0000000000000000))) + | (~((chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000))); + assign nl_FpMul_6U_10U_else_2_else_if_if_acc_1_nl = ({1'b1 , (FpMul_6U_10U_p_expo_sva_5[5:1])}) + + 6'b1; + assign FpMul_6U_10U_else_2_else_if_if_acc_1_nl = nl_FpMul_6U_10U_else_2_else_if_if_acc_1_nl[5:0]; + assign FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1 = readslicef_6_1_5((FpMul_6U_10U_else_2_else_if_if_acc_1_nl)); + assign nl_FpMul_6U_10U_else_2_else_if_if_acc_nl = FpMul_6U_10U_p_expo_sva_5 + 6'b1; + assign FpMul_6U_10U_else_2_else_if_if_acc_nl = nl_FpMul_6U_10U_else_2_else_if_if_acc_nl[5:0]; + assign mux_36_nl = MUX_s_1_2_2((~ FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2), + FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2, FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1); + assign and_62_nl = (mux_36_nl) & (FpMul_6U_10U_p_mant_p1_sva_2[21]); + assign FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0 = MUX_v_6_2_2(FpMul_6U_10U_p_expo_sva_5, + (FpMul_6U_10U_else_2_else_if_if_acc_nl), and_62_nl); + assign FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp = ~((FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1==6'b111111)); + assign nl_FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1 = FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0 + + 6'b1; + assign FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1 = nl_FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1[5:0]; + assign FpMantRNE_22U_11U_else_and_svs = FpMantRNE_22U_11U_else_carry_sva & (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[19:10]==10'b1111111111); + assign FpMantRNE_22U_11U_else_carry_sva = (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[9]) + & (((FpMul_6U_10U_p_mant_p1_sva_2[0]) & (FpMul_6U_10U_p_mant_p1_sva_2[21])) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[0]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[1]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[2]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[3]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[4]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[5]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[6]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[7]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[8]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[10])); + assign FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0 = MUX_v_20_2_2((FpMul_6U_10U_p_mant_p1_sva_2[19:0]), + (FpMul_6U_10U_p_mant_p1_sva_2[20:1]), FpMul_6U_10U_p_mant_p1_sva_2[21]); + assign FpMul_6U_10U_FpMul_6U_10U_nor_1_nl = ~(FpMantRNE_22U_11U_else_and_svs | + FpMul_6U_10U_is_inf_lpi_1_dfm_2); + assign FpMul_6U_10U_or_1_nl = ((~ FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp) + & FpMantRNE_22U_11U_else_and_svs) | FpMul_6U_10U_is_inf_lpi_1_dfm_2; + assign FpMantWidthDec_6U_21U_10U_0U_0U_and_1_nl = FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp + & FpMantRNE_22U_11U_else_and_svs & (~ FpMul_6U_10U_is_inf_lpi_1_dfm_2); + assign FpMul_6U_10U_o_expo_lpi_1_dfm = MUX1HOT_v_6_3_2(FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0, + 6'b111110, FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1, {(FpMul_6U_10U_FpMul_6U_10U_nor_1_nl) + , (FpMul_6U_10U_or_1_nl) , (FpMantWidthDec_6U_21U_10U_0U_0U_and_1_nl)}); + assign FpMul_6U_10U_lor_2_lpi_1_dfm = (~((FpMul_6U_10U_o_expo_lpi_1_dfm!=6'b000000))) + | FpMul_6U_10U_lor_1_lpi_1_dfm_4; + assign FpMul_6U_10U_is_inf_lpi_1_dfm_2 = ~(((FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1 + | (~ (FpMul_6U_10U_p_mant_p1_sva_2[21]))) & FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4) + | FpMul_6U_10U_lor_1_lpi_1_dfm_4); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_5_cse; + assign nor_tmp_1 = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_tmp_4 = FpMul_6U_10U_oelse_1_acc_itm_7_1 | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp + | (~ nor_tmp_1); + assign mux_tmp_3 = MUX_s_1_2_2(nor_tmp_1, main_stage_v_1, nor_cse); + assign or_tmp_7 = IsNaN_6U_10U_land_lpi_1_dfm_st_3 | IsNaN_6U_10U_1_land_lpi_1_dfm_3; + assign or_tmp_16 = nor_cse | main_stage_v_1; + assign nor_40_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_1)); + assign mux_tmp_6 = MUX_s_1_2_2((nor_40_nl), main_stage_v_1, chn_o_rsci_bawt); + assign mux_tmp_7 = MUX_s_1_2_2(mux_tmp_6, or_tmp_16, main_stage_v_2); + assign nor_tmp_11 = or_tmp_7 & main_stage_v_1; + assign or_tmp_32 = or_tmp_7 | (~ main_stage_v_1); + assign or_tmp_40 = (~ FpMul_6U_10U_else_2_if_acc_itm_6_1) | FpMul_6U_10U_oelse_1_acc_itm_7_1 + | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | (~ nor_tmp_1); + assign and_93_nl = nand_cse & nor_tmp_1; + assign mux_tmp_21 = MUX_s_1_2_2((and_93_nl), nor_tmp_1, IsNaN_6U_10U_nor_tmp); + assign and_94_nl = IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse & mux_tmp_21; + assign mux_22_nl = MUX_s_1_2_2((and_94_nl), mux_tmp_21, IsNaN_6U_10U_1_nor_tmp); + assign nor_34_nl = ~((~ main_stage_v_1) | IsNaN_6U_10U_land_lpi_1_dfm_st_3 | IsNaN_6U_10U_1_land_lpi_1_dfm_3); + assign mux_tmp_23 = MUX_s_1_2_2((nor_34_nl), (mux_22_nl), or_5_cse); + assign or_tmp_48 = IsNaN_6U_10U_1_nor_tmp | (~((chn_b_rsci_d_mxwt[15:10]==6'b111111) + & mux_tmp_21)); + assign or_tmp_49 = FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | nand_7_cse; + assign or_tmp_52 = IsNaN_6U_10U_nor_tmp | (~((chn_a_rsci_d_mxwt[15:10]==6'b111111) + & chn_a_rsci_bawt & chn_b_rsci_bawt)); + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_5_cse & main_stage_v_2; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_2); + assign and_dcpl_28 = or_5_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_3; + assign or_tmp_56 = IsNaN_6U_10U_1_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse; + assign or_tmp_62 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_68 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_5_cse & (fsm_output[1]); + assign chn_o_rsci_d_15_10_mx0c1 = or_5_cse & main_stage_v_2 & (~ IsNaN_6U_10U_land_lpi_1_dfm_4); + assign main_stage_v_1_mx0c1 = nand_6_cse & main_stage_v_1 & or_5_cse; + assign main_stage_v_2_mx0c1 = or_5_cse & (~ main_stage_v_1) & main_stage_v_2; + assign chn_a_rsci_oswt_unreg_pff = or_tmp_68; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_62 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_62; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpMul_6U_10U_FpMul_6U_10U_FpMul_6U_10U_nor_1_nl), + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2, FpMul_6U_10U_or_2_cse); + chn_o_rsci_d_16 <= FpMul_6U_10U_mux_10_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15_10 <= 6'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_2 & IsNaN_6U_10U_land_lpi_1_dfm_4) + | chn_o_rsci_d_15_10_mx0c1) ) begin + chn_o_rsci_d_15_10 <= MUX_v_6_2_2(FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2, + (FpMul_6U_10U_FpMul_6U_10U_and_2_nl), FpBitsToFloat_6U_10U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_68 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (~ (mux_2_nl)) ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 <= FpMul_6U_10U_else_2_if_acc_itm_6_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_3 <= 1'b0; + FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 <= 1'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_3 <= 1'b0; + end + else if ( IsNaN_6U_10U_aelse_and_cse ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_3 <= ~(IsNaN_6U_10U_nor_tmp | nand_cse); + FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 <= or_68_cse; + IsNaN_6U_10U_1_land_lpi_1_dfm_3 <= ~(IsNaN_6U_10U_1_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_p_expo_sva_5 <= 6'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_5_nl) ) begin + FpMul_6U_10U_p_expo_sva_5 <= nl_FpMul_6U_10U_p_expo_sva_5[5:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_p_mant_p1_sva_2 <= 22'b0; + end + else if ( core_wen & ((or_5_cse & (~ FpMul_6U_10U_lor_1_lpi_1_dfm_st_3) & FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3) + | and_40_rgt) & mux_tmp_7 ) begin + FpMul_6U_10U_p_mant_p1_sva_2 <= MUX_v_22_2_2(FpMul_6U_10U_p_mant_p1_mul_tmp, + FpMul_6U_10U_p_mant_p1_sva, and_40_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_9_nl) ) begin + FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2 <= FpMul_6U_10U_p_mant_p1_mul_tmp[21]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_11_nl) ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4 <= FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2 <= 6'b0; + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2 <= 10'b0; + end + else if ( FpBitsToFloat_6U_10U_1_and_1_cse ) begin + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2 <= MUX_v_6_2_2((FpMul_6U_10U_ub_sva_1_15_0_1[15:10]), + (FpMul_6U_10U_ua_sva_1_15_0_1[15:10]), and_dcpl_28); + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2 <= MUX_v_10_2_2((FpMul_6U_10U_ub_sva_1_15_0_1[9:0]), + (FpMul_6U_10U_ua_sva_1_15_0_1[9:0]), and_dcpl_28); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= 1'b0; + FpMul_6U_10U_mux_10_itm_4 <= 1'b0; + IsNaN_6U_10U_land_lpi_1_dfm_4 <= 1'b0; + FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_1_aelse_and_cse ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= IsNaN_6U_10U_1_land_lpi_1_dfm_3; + FpMul_6U_10U_mux_10_itm_4 <= FpMul_6U_10U_mux_10_itm_3; + IsNaN_6U_10U_land_lpi_1_dfm_4 <= IsNaN_6U_10U_land_lpi_1_dfm_st_3; + FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 <= FpMul_6U_10U_lor_1_lpi_1_dfm_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_4 <= 1'b0; + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4 <= 1'b0; + end + else if ( FpMul_6U_10U_oelse_1_and_1_cse ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_4 <= FpMul_6U_10U_lor_1_lpi_1_dfm_3; + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4 <= FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_p_mant_p1_sva <= 22'b0; + end + else if ( core_wen & (~ (fsm_output[0])) & (~((~ main_stage_v_1) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 + | (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3))) + & (mux_20_nl) ) begin + FpMul_6U_10U_p_mant_p1_sva <= FpMul_6U_10U_p_mant_p1_mul_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_3 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & mux_tmp_23 ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_3 <= or_68_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3 <= 1'b0; + end + else if ( core_wen & (((~(FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | FpMul_6U_10U_oelse_1_acc_itm_7_1)) + & or_5_cse) | and_45_rgt) & mux_tmp_23 ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3 <= MUX_s_1_2_2(FpMul_6U_10U_else_2_if_acc_itm_6_1, + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs, and_45_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_mux_10_itm_3 <= 1'b0; + end + else if ( core_wen & (and_52_rgt | and_60_rgt | and_61_rgt) & mux_tmp_3 ) begin + FpMul_6U_10U_mux_10_itm_3 <= MUX1HOT_s_1_3_2((chn_a_rsci_d_mxwt[16]), (chn_b_rsci_d_mxwt[16]), + (FpMul_6U_10U_xor_1_nl), {and_52_rgt , and_60_rgt , and_61_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_ub_sva_1_15_0_1 <= 16'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (~ (mux_29_nl)) ) begin + FpMul_6U_10U_ub_sva_1_15_0_1 <= chn_b_rsci_d_mxwt[15:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_ua_sva_1_15_0_1 <= 16'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_33_nl) ) begin + FpMul_6U_10U_ua_sva_1_15_0_1 <= chn_a_rsci_d_mxwt[15:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs <= 1'b0; + end + else if ( core_wen & (~(nand_6_cse | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp + | and_dcpl_7 | FpMul_6U_10U_oelse_1_acc_itm_7_1 | (fsm_output[0]))) ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs <= FpMul_6U_10U_else_2_if_acc_itm_6_1; + end + end + assign nl_FpMantRNE_22U_11U_else_acc_nl = (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[19:10]) + + conv_u2u_1_10(FpMantRNE_22U_11U_else_carry_sva); + assign FpMantRNE_22U_11U_else_acc_nl = nl_FpMantRNE_22U_11U_else_acc_nl[9:0]; + assign or_nl = FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp | (~ FpMantRNE_22U_11U_else_and_svs); + assign mux_37_nl = MUX_v_10_2_2((signext_10_1(~ FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp)), + (FpMantRNE_22U_11U_else_acc_nl), or_nl); + assign FpMul_6U_10U_nor_nl = ~(MUX_v_10_2_2((mux_37_nl), 10'b1111111111, FpMul_6U_10U_is_inf_lpi_1_dfm_2)); + assign FpMul_6U_10U_FpMul_6U_10U_FpMul_6U_10U_nor_1_nl = ~(MUX_v_10_2_2((FpMul_6U_10U_nor_nl), + 10'b1111111111, FpMul_6U_10U_lor_2_lpi_1_dfm)); + assign FpMul_6U_10U_oelse_2_not_1_nl = ~ FpMul_6U_10U_lor_2_lpi_1_dfm; + assign FpMul_6U_10U_FpMul_6U_10U_and_2_nl = MUX_v_6_2_2(6'b000000, FpMul_6U_10U_o_expo_lpi_1_dfm, + (FpMul_6U_10U_oelse_2_not_1_nl)); + assign FpBitsToFloat_6U_10U_1_and_nl = (~ IsNaN_6U_10U_1_land_lpi_1_dfm_4) & chn_o_rsci_d_15_10_mx0c1; + assign or_2_nl = nor_cse | FpMul_6U_10U_oelse_1_acc_itm_7_1 | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp + | (~ nor_tmp_1); + assign mux_nl = MUX_s_1_2_2(or_tmp_4, (~ main_stage_v_1), reg_chn_o_rsci_ld_core_psct_cse); + assign mux_1_nl = MUX_s_1_2_2((mux_nl), or_tmp_4, chn_o_rsci_bawt); + assign mux_2_nl = MUX_s_1_2_2((mux_1_nl), (or_2_nl), FpMul_6U_10U_lor_1_lpi_1_dfm_st_3); + assign nl_FpMul_6U_10U_else_2_else_acc_2_nl = (FpMul_6U_10U_ub_sva_1_15_0_1[15:10]) + + 6'b100001; + assign FpMul_6U_10U_else_2_else_acc_2_nl = nl_FpMul_6U_10U_else_2_else_acc_2_nl[5:0]; + assign nl_FpMul_6U_10U_p_expo_sva_5 = (FpMul_6U_10U_else_2_else_acc_2_nl) + (FpMul_6U_10U_ua_sva_1_15_0_1[15:10]); + assign nor_41_nl = ~((~ main_stage_v_1) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | (~(FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 + & ((FpMul_6U_10U_p_mant_p1_mul_tmp[21]) | (~ or_tmp_7))))); + assign nor_43_nl = ~(FpMul_6U_10U_or_2_cse | (FpMul_6U_10U_p_mant_p1_sva_2[21]) + | (~ main_stage_v_2) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4)); + assign mux_4_nl = MUX_s_1_2_2((nor_43_nl), nor_42_cse, FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2); + assign mux_5_nl = MUX_s_1_2_2((mux_4_nl), (nor_41_nl), or_5_cse); + assign nor_39_nl = ~((~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4) + | FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ main_stage_v_2) | chn_o_rsci_bawt + | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign mux_8_nl = MUX_s_1_2_2(mux_tmp_6, or_tmp_16, nor_42_cse); + assign mux_9_nl = MUX_s_1_2_2((mux_8_nl), (nor_39_nl), or_65_cse); + assign nor_38_nl = ~(FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ main_stage_v_2) | chn_o_rsci_bawt + | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign nor_6_nl = ~(FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ main_stage_v_2)); + assign mux_10_nl = MUX_s_1_2_2(mux_tmp_6, or_tmp_16, nor_6_nl); + assign mux_11_nl = MUX_s_1_2_2((mux_10_nl), (nor_38_nl), FpMul_6U_10U_lor_1_lpi_1_dfm_st_3); + assign or_38_nl = nor_cse | (~ FpMul_6U_10U_else_2_if_acc_itm_6_1) | FpMul_6U_10U_oelse_1_acc_itm_7_1 + | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | (~ nor_tmp_1); + assign mux_18_nl = MUX_s_1_2_2(or_tmp_40, (~ main_stage_v_1), reg_chn_o_rsci_ld_core_psct_cse); + assign mux_19_nl = MUX_s_1_2_2((mux_18_nl), or_tmp_40, chn_o_rsci_bawt); + assign mux_20_nl = MUX_s_1_2_2((mux_19_nl), (or_38_nl), or_65_cse); + assign FpMul_6U_10U_xor_1_nl = (chn_a_rsci_d_mxwt[16]) ^ (chn_b_rsci_d_mxwt[16]); + assign mux_25_nl = MUX_s_1_2_2(or_tmp_48, (~ nor_tmp_1), FpMul_6U_10U_else_2_if_acc_itm_6_1); + assign mux_26_nl = MUX_s_1_2_2((mux_25_nl), or_tmp_48, or_68_cse); + assign mux_27_nl = MUX_s_1_2_2(or_tmp_49, (~ main_stage_v_1), IsNaN_6U_10U_1_land_lpi_1_dfm_3); + assign mux_28_nl = MUX_s_1_2_2((mux_27_nl), or_tmp_49, IsNaN_6U_10U_land_lpi_1_dfm_st_3); + assign mux_29_nl = MUX_s_1_2_2((mux_28_nl), (mux_26_nl), or_5_cse); + assign mux_30_nl = MUX_s_1_2_2(or_tmp_52, nand_6_cse, FpMul_6U_10U_else_2_if_acc_itm_6_1); + assign mux_31_nl = MUX_s_1_2_2((mux_30_nl), or_tmp_52, or_68_cse); + assign nor_33_nl = ~(FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | nand_7_cse); + assign mux_32_nl = MUX_s_1_2_2((nor_33_nl), main_stage_v_1, IsNaN_6U_10U_land_lpi_1_dfm_st_3); + assign mux_33_nl = MUX_s_1_2_2((mux_32_nl), (~ (mux_31_nl)), or_5_cse); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_3_2; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [2:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + MUX1HOT_v_6_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [19:0] MUX_v_20_2_2; + input [19:0] input_0; + input [19:0] input_1; + input [0:0] sel; + reg [19:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_20_2_2 = result; + end + endfunction + function [21:0] MUX_v_22_2_2; + input [21:0] input_0; + input [21:0] input_1; + input [0:0] sel; + reg [21:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_22_2_2 = result; + end + endfunction + function [5:0] MUX_v_6_2_2; + input [5:0] input_0; + input [5:0] input_1; + input [0:0] sel; + reg [5:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_6_2_2 = result; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [5:0] readslicef_7_6_1; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 1; + readslicef_7_6_1 = tmp[5:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [9:0] signext_10_1; + input [0:0] vector; + begin + signext_10_1= {{9{vector[0]}}, vector}; + end + endfunction + function [7:0] conv_s2s_7_8 ; + input [6:0] vector ; + begin + conv_s2s_7_8 = {vector[6], vector}; + end + endfunction + function [6:0] conv_u2s_6_7 ; + input [5:0] vector ; + begin + conv_u2s_6_7 = {1'b0, vector}; + end + endfunction + function [7:0] conv_u2s_6_8 ; + input [5:0] vector ; + begin + conv_u2s_6_8 = {{2{1'b0}}, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [6:0] conv_u2u_6_7 ; + input [5:0] vector ; + begin + conv_u2u_6_7 = {1'b0, vector}; + end + endfunction + function [21:0] conv_u2u_22_22 ; + input [21:0] vector ; + begin + conv_u2u_22_22 = vector; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul +// ------------------------------------------------------------------ +module HLS_fp17_mul ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP17_MUL_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP17_MUL_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP17_MUL_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_mul_core HLS_fp17_mul_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_mul.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_mul.v.vcp new file mode 100644 index 0000000..8fafe54 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_mul.v.vcp @@ -0,0 +1,1532 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_mul.v +module FP17_MUL_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_MUL_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_MUL_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:52:26 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_MUL_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_MUL_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_MUL_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP17_MUL_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_MUL_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_MUL_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_mul_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_mul_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [16:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [16:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [16:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_17_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 17'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_MUL_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_mul_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [16:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [16:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp HLS_fp17_mul_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_mul_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_mul_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul_core +// ------------------------------------------------------------------ +module HLS_fp17_mul_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [16:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [5:0] chn_o_rsci_d_15_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire IsNaN_6U_10U_nor_tmp; + wire FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp; + wire [21:0] FpMul_6U_10U_p_mant_p1_mul_tmp; + wire IsNaN_6U_10U_1_nor_tmp; + wire nor_tmp_1; + wire or_tmp_4; + wire mux_tmp_3; + wire or_tmp_7; + wire or_tmp_16; + wire mux_tmp_6; + wire mux_tmp_7; + wire nor_tmp_11; + wire or_tmp_32; + wire or_tmp_40; + wire mux_tmp_21; + wire mux_tmp_23; + wire or_tmp_48; + wire or_tmp_49; + wire or_tmp_52; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire or_tmp_56; + wire or_tmp_62; + wire or_tmp_68; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs; + reg [21:0] FpMul_6U_10U_p_mant_p1_sva; + reg main_stage_v_1; + reg main_stage_v_2; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_3; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_4; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_3; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_4; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4; + reg [21:0] FpMul_6U_10U_p_mant_p1_sva_2; + reg [5:0] FpMul_6U_10U_p_expo_sva_5; + wire [6:0] nl_FpMul_6U_10U_p_expo_sva_5; + reg IsNaN_6U_10U_land_lpi_1_dfm_4; + reg [5:0] FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2; + reg FpMul_6U_10U_mux_10_itm_3; + reg FpMul_6U_10U_mux_10_itm_4; + reg [9:0] FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_st_3; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3; + reg FpMul_6U_10U_lor_1_lpi_1_dfm_st_4; + reg FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4; + reg FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_3; + reg [15:0] FpMul_6U_10U_ua_sva_1_15_0_1; + reg [15:0] FpMul_6U_10U_ub_sva_1_15_0_1; + wire main_stage_en_1; + wire FpMantRNE_22U_11U_else_and_svs; + wire FpMul_6U_10U_is_inf_lpi_1_dfm_2; + wire FpMantRNE_22U_11U_else_carry_sva; + wire [5:0] FpMul_6U_10U_o_expo_lpi_1_dfm; + wire FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp; + wire [5:0] FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1; + wire [6:0] nl_FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1; + wire [19:0] FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_cse; + wire nor_42_cse; + wire or_65_cse; + wire nor_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_68_cse; + wire or_5_cse; + wire nand_cse; + wire FpMul_6U_10U_or_2_cse; + wire IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse; + wire nand_7_cse; + wire nand_6_cse; + wire and_40_rgt; + wire and_45_rgt; + wire and_52_rgt; + wire and_60_rgt; + wire and_61_rgt; + wire chn_o_rsci_d_15_10_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire [5:0] FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0; + wire FpMul_6U_10U_lor_2_lpi_1_dfm; + wire IsNaN_6U_10U_aelse_and_cse; + wire IsNaN_6U_10U_1_aelse_and_cse; + wire FpMul_6U_10U_oelse_1_and_1_cse; + wire FpBitsToFloat_6U_10U_1_and_1_cse; + wire FpMul_6U_10U_else_2_if_acc_itm_6_1; + wire FpMul_6U_10U_oelse_1_acc_itm_7_1; + wire FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[9:0] FpMul_6U_10U_FpMul_6U_10U_FpMul_6U_10U_nor_1_nl; + wire[9:0] FpMul_6U_10U_nor_nl; + wire[9:0] mux_37_nl; + wire[9:0] FpMantRNE_22U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_22U_11U_else_acc_nl; + wire[0:0] or_nl; + wire[5:0] FpMul_6U_10U_FpMul_6U_10U_and_2_nl; + wire[0:0] FpMul_6U_10U_oelse_2_not_1_nl; + wire[0:0] FpBitsToFloat_6U_10U_1_and_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_2_nl; + wire[0:0] mux_1_nl; + wire[0:0] mux_nl; + wire[5:0] FpMul_6U_10U_else_2_else_acc_2_nl; + wire[6:0] nl_FpMul_6U_10U_else_2_else_acc_2_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_41_nl; + wire[0:0] mux_4_nl; + wire[0:0] nor_43_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_39_nl; + wire[0:0] mux_8_nl; + wire[0:0] mux_11_nl; + wire[0:0] nor_38_nl; + wire[0:0] mux_10_nl; + wire[0:0] nor_6_nl; + wire[0:0] mux_13_nl; + wire[0:0] or_25_nl; + wire[0:0] mux_12_nl; + wire[0:0] nor_37_nl; + wire[0:0] and_97_nl; + wire[0:0] mux_17_nl; + wire[0:0] mux_16_nl; + wire[0:0] nor_35_nl; + wire[0:0] or_35_nl; + wire[0:0] nor_15_nl; + wire[0:0] mux_20_nl; + wire[0:0] or_38_nl; + wire[0:0] mux_19_nl; + wire[0:0] mux_18_nl; + wire[0:0] mux_35_nl; + wire[0:0] and_91_nl; + wire[0:0] FpMul_6U_10U_xor_1_nl; + wire[0:0] mux_29_nl; + wire[0:0] mux_26_nl; + wire[0:0] mux_25_nl; + wire[0:0] mux_28_nl; + wire[0:0] mux_27_nl; + wire[0:0] mux_33_nl; + wire[0:0] mux_31_nl; + wire[0:0] mux_30_nl; + wire[0:0] mux_32_nl; + wire[0:0] nor_33_nl; + wire[6:0] FpMul_6U_10U_else_2_if_acc_nl; + wire[7:0] nl_FpMul_6U_10U_else_2_if_acc_nl; + wire[6:0] FpMul_6U_10U_else_2_acc_1_nl; + wire[7:0] nl_FpMul_6U_10U_else_2_acc_1_nl; + wire[7:0] FpMul_6U_10U_oelse_1_acc_nl; + wire[8:0] nl_FpMul_6U_10U_oelse_1_acc_nl; + wire[6:0] FpMul_6U_10U_oelse_1_acc_1_nl; + wire[7:0] nl_FpMul_6U_10U_oelse_1_acc_1_nl; + wire[5:0] FpMul_6U_10U_else_2_else_if_if_acc_1_nl; + wire[6:0] nl_FpMul_6U_10U_else_2_else_if_if_acc_1_nl; + wire[5:0] FpMul_6U_10U_else_2_else_if_if_acc_nl; + wire[6:0] nl_FpMul_6U_10U_else_2_else_if_if_acc_nl; + wire[0:0] and_62_nl; + wire[0:0] mux_36_nl; + wire[0:0] FpMul_6U_10U_FpMul_6U_10U_nor_1_nl; + wire[0:0] FpMul_6U_10U_or_1_nl; + wire[0:0] FpMantWidthDec_6U_21U_10U_0U_0U_and_1_nl; + wire[0:0] nor_40_nl; + wire[0:0] and_93_nl; + wire[0:0] mux_22_nl; + wire[0:0] and_94_nl; + wire[0:0] nor_34_nl; +// Interconnect Declarations for Component Instantiations + wire [16:0] nl_HLS_fp17_mul_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_mul_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 , chn_o_rsci_d_15_10 + , chn_o_rsci_d_9_0}; + HLS_fp17_mul_core_chn_a_rsci HLS_fp17_mul_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_mul_core_chn_b_rsci HLS_fp17_mul_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp17_mul_core_chn_o_rsci HLS_fp17_mul_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_mul_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp17_mul_core_staller HLS_fp17_mul_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_mul_core_core_fsm HLS_fp17_mul_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, main_stage_en_1 & (fsm_output[1]))), fsm_output[1]); +// assert(iMantWidth > oMantWidth) - ../include/nvdla_float.h: line 386 +// PSL HLS_fp17_mul_core_nvdla_float_h_ln386_assert_iMantWidth_gt_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_2))); + assign FpMul_6U_10U_or_2_cse = IsNaN_6U_10U_1_land_lpi_1_dfm_4 | IsNaN_6U_10U_land_lpi_1_dfm_4; + assign nor_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign IsNaN_6U_10U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_tmp_3; + assign nor_42_cse = ~((~ main_stage_v_2) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | + (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4)); + assign or_5_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign or_65_cse = FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3); + assign and_40_rgt = or_5_cse & or_65_cse; + assign or_25_nl = nor_cse | nor_tmp_11; + assign nor_37_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_11)); + assign mux_12_nl = MUX_s_1_2_2((nor_37_nl), nor_tmp_11, chn_o_rsci_bawt); + assign and_97_nl = FpMul_6U_10U_or_2_cse & main_stage_v_2; + assign mux_13_nl = MUX_s_1_2_2((mux_12_nl), (or_25_nl), and_97_nl); + assign FpBitsToFloat_6U_10U_1_and_1_cse = core_wen & ((or_5_cse & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_3)) + | and_dcpl_28) & (mux_13_nl); + assign IsNaN_6U_10U_1_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_tmp_7; + assign nor_35_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ or_tmp_32)); + assign mux_16_nl = MUX_s_1_2_2((nor_35_nl), or_tmp_32, chn_o_rsci_bawt); + assign or_35_nl = nor_cse | IsNaN_6U_10U_1_land_lpi_1_dfm_3 | IsNaN_6U_10U_land_lpi_1_dfm_st_3 + | (~ main_stage_v_1); + assign nor_15_nl = ~(IsNaN_6U_10U_1_land_lpi_1_dfm_4 | IsNaN_6U_10U_land_lpi_1_dfm_4 + | (~ main_stage_v_2)); + assign mux_17_nl = MUX_s_1_2_2((or_35_nl), (mux_16_nl), nor_15_nl); + assign FpMul_6U_10U_oelse_1_and_1_cse = core_wen & (~ and_dcpl_7) & (~ (mux_17_nl)); + assign or_68_cse = FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | FpMul_6U_10U_oelse_1_acc_itm_7_1; + assign and_45_rgt = or_68_cse & or_5_cse; + assign IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse = ~((chn_b_rsci_d_mxwt[15:10]==6'b111111)); + assign nand_cse = ~((chn_a_rsci_d_mxwt[15:10]==6'b111111)); + assign and_52_rgt = or_5_cse & (chn_a_rsci_d_mxwt[15:10]==6'b111111) & (~ IsNaN_6U_10U_nor_tmp); + assign and_60_rgt = ((chn_a_rsci_d_mxwt[15:10]!=6'b111111) | IsNaN_6U_10U_nor_tmp) + & (chn_b_rsci_d_mxwt[15:10]==6'b111111) & (~ IsNaN_6U_10U_1_nor_tmp) & or_5_cse; + assign and_91_nl = nand_cse & or_tmp_56; + assign mux_35_nl = MUX_s_1_2_2((and_91_nl), or_tmp_56, IsNaN_6U_10U_nor_tmp); + assign and_61_rgt = (mux_35_nl) & or_5_cse; + assign nand_7_cse = ~(FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 + & main_stage_v_1); + assign nand_6_cse = ~(chn_a_rsci_bawt & chn_b_rsci_bawt); + assign nl_FpMul_6U_10U_else_2_acc_1_nl = conv_u2u_6_7(chn_a_rsci_d_mxwt[15:10]) + + conv_u2u_6_7(chn_b_rsci_d_mxwt[15:10]); + assign FpMul_6U_10U_else_2_acc_1_nl = nl_FpMul_6U_10U_else_2_acc_1_nl[6:0]; + assign nl_FpMul_6U_10U_else_2_if_acc_nl = conv_u2u_6_7(readslicef_7_6_1((FpMul_6U_10U_else_2_acc_1_nl))) + + 7'b1010001; + assign FpMul_6U_10U_else_2_if_acc_nl = nl_FpMul_6U_10U_else_2_if_acc_nl[6:0]; + assign FpMul_6U_10U_else_2_if_acc_itm_6_1 = readslicef_7_1_6((FpMul_6U_10U_else_2_if_acc_nl)); + assign IsNaN_6U_10U_nor_tmp = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign FpMul_6U_10U_p_mant_p1_mul_tmp = conv_u2u_22_22(({1'b1 , (FpMul_6U_10U_ua_sva_1_15_0_1[9:0])}) + * ({1'b1 , (FpMul_6U_10U_ub_sva_1_15_0_1[9:0])})); + assign IsNaN_6U_10U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign nl_FpMul_6U_10U_oelse_1_acc_1_nl = conv_u2s_6_7(chn_b_rsci_d_mxwt[15:10]) + + 7'b1100001; + assign FpMul_6U_10U_oelse_1_acc_1_nl = nl_FpMul_6U_10U_oelse_1_acc_1_nl[6:0]; + assign nl_FpMul_6U_10U_oelse_1_acc_nl = conv_s2s_7_8(FpMul_6U_10U_oelse_1_acc_1_nl) + + conv_u2s_6_8(chn_a_rsci_d_mxwt[15:10]); + assign FpMul_6U_10U_oelse_1_acc_nl = nl_FpMul_6U_10U_oelse_1_acc_nl[7:0]; + assign FpMul_6U_10U_oelse_1_acc_itm_7_1 = readslicef_8_1_7((FpMul_6U_10U_oelse_1_acc_nl)); + assign FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp = (~((chn_b_rsci_d_mxwt[15:0]!=16'b0000000000000000))) + | (~((chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000))); + assign nl_FpMul_6U_10U_else_2_else_if_if_acc_1_nl = ({1'b1 , (FpMul_6U_10U_p_expo_sva_5[5:1])}) + + 6'b1; + assign FpMul_6U_10U_else_2_else_if_if_acc_1_nl = nl_FpMul_6U_10U_else_2_else_if_if_acc_1_nl[5:0]; + assign FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1 = readslicef_6_1_5((FpMul_6U_10U_else_2_else_if_if_acc_1_nl)); + assign nl_FpMul_6U_10U_else_2_else_if_if_acc_nl = FpMul_6U_10U_p_expo_sva_5 + 6'b1; + assign FpMul_6U_10U_else_2_else_if_if_acc_nl = nl_FpMul_6U_10U_else_2_else_if_if_acc_nl[5:0]; + assign mux_36_nl = MUX_s_1_2_2((~ FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2), + FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2, FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1); + assign and_62_nl = (mux_36_nl) & (FpMul_6U_10U_p_mant_p1_sva_2[21]); + assign FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0 = MUX_v_6_2_2(FpMul_6U_10U_p_expo_sva_5, + (FpMul_6U_10U_else_2_else_if_if_acc_nl), and_62_nl); + assign FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp = ~((FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1==6'b111111)); + assign nl_FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1 = FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0 + + 6'b1; + assign FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1 = nl_FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1[5:0]; + assign FpMantRNE_22U_11U_else_and_svs = FpMantRNE_22U_11U_else_carry_sva & (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[19:10]==10'b1111111111); + assign FpMantRNE_22U_11U_else_carry_sva = (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[9]) + & (((FpMul_6U_10U_p_mant_p1_sva_2[0]) & (FpMul_6U_10U_p_mant_p1_sva_2[21])) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[0]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[1]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[2]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[3]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[4]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[5]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[6]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[7]) + | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[8]) | (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[10])); + assign FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0 = MUX_v_20_2_2((FpMul_6U_10U_p_mant_p1_sva_2[19:0]), + (FpMul_6U_10U_p_mant_p1_sva_2[20:1]), FpMul_6U_10U_p_mant_p1_sva_2[21]); + assign FpMul_6U_10U_FpMul_6U_10U_nor_1_nl = ~(FpMantRNE_22U_11U_else_and_svs | + FpMul_6U_10U_is_inf_lpi_1_dfm_2); + assign FpMul_6U_10U_or_1_nl = ((~ FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp) + & FpMantRNE_22U_11U_else_and_svs) | FpMul_6U_10U_is_inf_lpi_1_dfm_2; + assign FpMantWidthDec_6U_21U_10U_0U_0U_and_1_nl = FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp + & FpMantRNE_22U_11U_else_and_svs & (~ FpMul_6U_10U_is_inf_lpi_1_dfm_2); + assign FpMul_6U_10U_o_expo_lpi_1_dfm = MUX1HOT_v_6_3_2(FpMul_6U_10U_p_expo_lpi_1_dfm_1_mx0, + 6'b111110, FpMantWidthDec_6U_21U_10U_0U_0U_o_expo_sva_1, {(FpMul_6U_10U_FpMul_6U_10U_nor_1_nl) + , (FpMul_6U_10U_or_1_nl) , (FpMantWidthDec_6U_21U_10U_0U_0U_and_1_nl)}); + assign FpMul_6U_10U_lor_2_lpi_1_dfm = (~((FpMul_6U_10U_o_expo_lpi_1_dfm!=6'b000000))) + | FpMul_6U_10U_lor_1_lpi_1_dfm_4; + assign FpMul_6U_10U_is_inf_lpi_1_dfm_2 = ~(((FpMul_6U_10U_else_2_else_if_if_acc_1_itm_5_1 + | (~ (FpMul_6U_10U_p_mant_p1_sva_2[21]))) & FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4) + | FpMul_6U_10U_lor_1_lpi_1_dfm_4); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_5_cse; + assign nor_tmp_1 = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_tmp_4 = FpMul_6U_10U_oelse_1_acc_itm_7_1 | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp + | (~ nor_tmp_1); + assign mux_tmp_3 = MUX_s_1_2_2(nor_tmp_1, main_stage_v_1, nor_cse); + assign or_tmp_7 = IsNaN_6U_10U_land_lpi_1_dfm_st_3 | IsNaN_6U_10U_1_land_lpi_1_dfm_3; + assign or_tmp_16 = nor_cse | main_stage_v_1; + assign nor_40_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_1)); + assign mux_tmp_6 = MUX_s_1_2_2((nor_40_nl), main_stage_v_1, chn_o_rsci_bawt); + assign mux_tmp_7 = MUX_s_1_2_2(mux_tmp_6, or_tmp_16, main_stage_v_2); + assign nor_tmp_11 = or_tmp_7 & main_stage_v_1; + assign or_tmp_32 = or_tmp_7 | (~ main_stage_v_1); + assign or_tmp_40 = (~ FpMul_6U_10U_else_2_if_acc_itm_6_1) | FpMul_6U_10U_oelse_1_acc_itm_7_1 + | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | (~ nor_tmp_1); + assign and_93_nl = nand_cse & nor_tmp_1; + assign mux_tmp_21 = MUX_s_1_2_2((and_93_nl), nor_tmp_1, IsNaN_6U_10U_nor_tmp); + assign and_94_nl = IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse & mux_tmp_21; + assign mux_22_nl = MUX_s_1_2_2((and_94_nl), mux_tmp_21, IsNaN_6U_10U_1_nor_tmp); + assign nor_34_nl = ~((~ main_stage_v_1) | IsNaN_6U_10U_land_lpi_1_dfm_st_3 | IsNaN_6U_10U_1_land_lpi_1_dfm_3); + assign mux_tmp_23 = MUX_s_1_2_2((nor_34_nl), (mux_22_nl), or_5_cse); + assign or_tmp_48 = IsNaN_6U_10U_1_nor_tmp | (~((chn_b_rsci_d_mxwt[15:10]==6'b111111) + & mux_tmp_21)); + assign or_tmp_49 = FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | nand_7_cse; + assign or_tmp_52 = IsNaN_6U_10U_nor_tmp | (~((chn_a_rsci_d_mxwt[15:10]==6'b111111) + & chn_a_rsci_bawt & chn_b_rsci_bawt)); + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_5_cse & main_stage_v_2; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_2); + assign and_dcpl_28 = or_5_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_3; + assign or_tmp_56 = IsNaN_6U_10U_1_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse; + assign or_tmp_62 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_68 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_5_cse & (fsm_output[1]); + assign chn_o_rsci_d_15_10_mx0c1 = or_5_cse & main_stage_v_2 & (~ IsNaN_6U_10U_land_lpi_1_dfm_4); + assign main_stage_v_1_mx0c1 = nand_6_cse & main_stage_v_1 & or_5_cse; + assign main_stage_v_2_mx0c1 = or_5_cse & (~ main_stage_v_1) & main_stage_v_2; + assign chn_a_rsci_oswt_unreg_pff = or_tmp_68; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_62 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_62; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpMul_6U_10U_FpMul_6U_10U_FpMul_6U_10U_nor_1_nl), + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2, FpMul_6U_10U_or_2_cse); + chn_o_rsci_d_16 <= FpMul_6U_10U_mux_10_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15_10 <= 6'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_2 & IsNaN_6U_10U_land_lpi_1_dfm_4) + | chn_o_rsci_d_15_10_mx0c1) ) begin + chn_o_rsci_d_15_10 <= MUX_v_6_2_2(FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2, + (FpMul_6U_10U_FpMul_6U_10U_and_2_nl), FpBitsToFloat_6U_10U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_68 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (~ (mux_2_nl)) ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 <= FpMul_6U_10U_else_2_if_acc_itm_6_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_3 <= 1'b0; + FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 <= 1'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_3 <= 1'b0; + end + else if ( IsNaN_6U_10U_aelse_and_cse ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_3 <= ~(IsNaN_6U_10U_nor_tmp | nand_cse); + FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 <= or_68_cse; + IsNaN_6U_10U_1_land_lpi_1_dfm_3 <= ~(IsNaN_6U_10U_1_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nand_cse); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_5_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_p_expo_sva_5 <= 6'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_5_nl) ) begin + FpMul_6U_10U_p_expo_sva_5 <= nl_FpMul_6U_10U_p_expo_sva_5[5:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_p_mant_p1_sva_2 <= 22'b0; + end + else if ( core_wen & ((or_5_cse & (~ FpMul_6U_10U_lor_1_lpi_1_dfm_st_3) & FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3) + | and_40_rgt) & mux_tmp_7 ) begin + FpMul_6U_10U_p_mant_p1_sva_2 <= MUX_v_22_2_2(FpMul_6U_10U_p_mant_p1_mul_tmp, + FpMul_6U_10U_p_mant_p1_sva, and_40_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_9_nl) ) begin + FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2 <= FpMul_6U_10U_p_mant_p1_mul_tmp[21]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_11_nl) ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4 <= FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2 <= 6'b0; + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2 <= 10'b0; + end + else if ( FpBitsToFloat_6U_10U_1_and_1_cse ) begin + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_15_10_itm_2 <= MUX_v_6_2_2((FpMul_6U_10U_ub_sva_1_15_0_1[15:10]), + (FpMul_6U_10U_ua_sva_1_15_0_1[15:10]), and_dcpl_28); + FpBitsToFloat_6U_10U_1_slc_FpBitsToFloat_6U_10U_ubits_1_9_0_itm_2 <= MUX_v_10_2_2((FpMul_6U_10U_ub_sva_1_15_0_1[9:0]), + (FpMul_6U_10U_ua_sva_1_15_0_1[9:0]), and_dcpl_28); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= 1'b0; + FpMul_6U_10U_mux_10_itm_4 <= 1'b0; + IsNaN_6U_10U_land_lpi_1_dfm_4 <= 1'b0; + FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_1_aelse_and_cse ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= IsNaN_6U_10U_1_land_lpi_1_dfm_3; + FpMul_6U_10U_mux_10_itm_4 <= FpMul_6U_10U_mux_10_itm_3; + IsNaN_6U_10U_land_lpi_1_dfm_4 <= IsNaN_6U_10U_land_lpi_1_dfm_st_3; + FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 <= FpMul_6U_10U_lor_1_lpi_1_dfm_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_4 <= 1'b0; + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4 <= 1'b0; + end + else if ( FpMul_6U_10U_oelse_1_and_1_cse ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_4 <= FpMul_6U_10U_lor_1_lpi_1_dfm_3; + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_4 <= FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_p_mant_p1_sva <= 22'b0; + end + else if ( core_wen & (~ (fsm_output[0])) & (~((~ main_stage_v_1) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 + | (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3))) + & (mux_20_nl) ) begin + FpMul_6U_10U_p_mant_p1_sva <= FpMul_6U_10U_p_mant_p1_mul_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_3 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & mux_tmp_23 ) begin + FpMul_6U_10U_lor_1_lpi_1_dfm_3 <= or_68_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3 <= 1'b0; + end + else if ( core_wen & (((~(FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | FpMul_6U_10U_oelse_1_acc_itm_7_1)) + & or_5_cse) | and_45_rgt) & mux_tmp_23 ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_3 <= MUX_s_1_2_2(FpMul_6U_10U_else_2_if_acc_itm_6_1, + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs, and_45_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_mux_10_itm_3 <= 1'b0; + end + else if ( core_wen & (and_52_rgt | and_60_rgt | and_61_rgt) & mux_tmp_3 ) begin + FpMul_6U_10U_mux_10_itm_3 <= MUX1HOT_s_1_3_2((chn_a_rsci_d_mxwt[16]), (chn_b_rsci_d_mxwt[16]), + (FpMul_6U_10U_xor_1_nl), {and_52_rgt , and_60_rgt , and_61_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_ub_sva_1_15_0_1 <= 16'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (~ (mux_29_nl)) ) begin + FpMul_6U_10U_ub_sva_1_15_0_1 <= chn_b_rsci_d_mxwt[15:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_ua_sva_1_15_0_1 <= 16'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_33_nl) ) begin + FpMul_6U_10U_ua_sva_1_15_0_1 <= chn_a_rsci_d_mxwt[15:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs <= 1'b0; + end + else if ( core_wen & (~(nand_6_cse | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp + | and_dcpl_7 | FpMul_6U_10U_oelse_1_acc_itm_7_1 | (fsm_output[0]))) ) begin + FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs <= FpMul_6U_10U_else_2_if_acc_itm_6_1; + end + end + assign nl_FpMantRNE_22U_11U_else_acc_nl = (FpMul_6U_10U_p_mant_20_1_lpi_1_dfm_3_mx0[19:10]) + + conv_u2u_1_10(FpMantRNE_22U_11U_else_carry_sva); + assign FpMantRNE_22U_11U_else_acc_nl = nl_FpMantRNE_22U_11U_else_acc_nl[9:0]; + assign or_nl = FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp | (~ FpMantRNE_22U_11U_else_and_svs); + assign mux_37_nl = MUX_v_10_2_2((signext_10_1(~ FpMantWidthDec_6U_21U_10U_0U_0U_if_1_unequal_tmp)), + (FpMantRNE_22U_11U_else_acc_nl), or_nl); + assign FpMul_6U_10U_nor_nl = ~(MUX_v_10_2_2((mux_37_nl), 10'b1111111111, FpMul_6U_10U_is_inf_lpi_1_dfm_2)); + assign FpMul_6U_10U_FpMul_6U_10U_FpMul_6U_10U_nor_1_nl = ~(MUX_v_10_2_2((FpMul_6U_10U_nor_nl), + 10'b1111111111, FpMul_6U_10U_lor_2_lpi_1_dfm)); + assign FpMul_6U_10U_oelse_2_not_1_nl = ~ FpMul_6U_10U_lor_2_lpi_1_dfm; + assign FpMul_6U_10U_FpMul_6U_10U_and_2_nl = MUX_v_6_2_2(6'b000000, FpMul_6U_10U_o_expo_lpi_1_dfm, + (FpMul_6U_10U_oelse_2_not_1_nl)); + assign FpBitsToFloat_6U_10U_1_and_nl = (~ IsNaN_6U_10U_1_land_lpi_1_dfm_4) & chn_o_rsci_d_15_10_mx0c1; + assign or_2_nl = nor_cse | FpMul_6U_10U_oelse_1_acc_itm_7_1 | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp + | (~ nor_tmp_1); + assign mux_nl = MUX_s_1_2_2(or_tmp_4, (~ main_stage_v_1), reg_chn_o_rsci_ld_core_psct_cse); + assign mux_1_nl = MUX_s_1_2_2((mux_nl), or_tmp_4, chn_o_rsci_bawt); + assign mux_2_nl = MUX_s_1_2_2((mux_1_nl), (or_2_nl), FpMul_6U_10U_lor_1_lpi_1_dfm_st_3); + assign nl_FpMul_6U_10U_else_2_else_acc_2_nl = (FpMul_6U_10U_ub_sva_1_15_0_1[15:10]) + + 6'b100001; + assign FpMul_6U_10U_else_2_else_acc_2_nl = nl_FpMul_6U_10U_else_2_else_acc_2_nl[5:0]; + assign nl_FpMul_6U_10U_p_expo_sva_5 = (FpMul_6U_10U_else_2_else_acc_2_nl) + (FpMul_6U_10U_ua_sva_1_15_0_1[15:10]); + assign nor_41_nl = ~((~ main_stage_v_1) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | (~(FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_3 + & ((FpMul_6U_10U_p_mant_p1_mul_tmp[21]) | (~ or_tmp_7))))); + assign nor_43_nl = ~(FpMul_6U_10U_or_2_cse | (FpMul_6U_10U_p_mant_p1_sva_2[21]) + | (~ main_stage_v_2) | FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4)); + assign mux_4_nl = MUX_s_1_2_2((nor_43_nl), nor_42_cse, FpMul_6U_10U_else_2_else_slc_FpMul_6U_10U_p_mant_p1_21_itm_2); + assign mux_5_nl = MUX_s_1_2_2((mux_4_nl), (nor_41_nl), or_5_cse); + assign nor_39_nl = ~((~ FpMul_6U_10U_else_2_if_slc_FpMul_6U_10U_else_2_if_acc_6_svs_st_4) + | FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ main_stage_v_2) | chn_o_rsci_bawt + | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign mux_8_nl = MUX_s_1_2_2(mux_tmp_6, or_tmp_16, nor_42_cse); + assign mux_9_nl = MUX_s_1_2_2((mux_8_nl), (nor_39_nl), or_65_cse); + assign nor_38_nl = ~(FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ main_stage_v_2) | chn_o_rsci_bawt + | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign nor_6_nl = ~(FpMul_6U_10U_lor_1_lpi_1_dfm_st_4 | (~ main_stage_v_2)); + assign mux_10_nl = MUX_s_1_2_2(mux_tmp_6, or_tmp_16, nor_6_nl); + assign mux_11_nl = MUX_s_1_2_2((mux_10_nl), (nor_38_nl), FpMul_6U_10U_lor_1_lpi_1_dfm_st_3); + assign or_38_nl = nor_cse | (~ FpMul_6U_10U_else_2_if_acc_itm_6_1) | FpMul_6U_10U_oelse_1_acc_itm_7_1 + | FpMul_6U_10U_if_2_FpMul_6U_10U_if_2_or_tmp | (~ nor_tmp_1); + assign mux_18_nl = MUX_s_1_2_2(or_tmp_40, (~ main_stage_v_1), reg_chn_o_rsci_ld_core_psct_cse); + assign mux_19_nl = MUX_s_1_2_2((mux_18_nl), or_tmp_40, chn_o_rsci_bawt); + assign mux_20_nl = MUX_s_1_2_2((mux_19_nl), (or_38_nl), or_65_cse); + assign FpMul_6U_10U_xor_1_nl = (chn_a_rsci_d_mxwt[16]) ^ (chn_b_rsci_d_mxwt[16]); + assign mux_25_nl = MUX_s_1_2_2(or_tmp_48, (~ nor_tmp_1), FpMul_6U_10U_else_2_if_acc_itm_6_1); + assign mux_26_nl = MUX_s_1_2_2((mux_25_nl), or_tmp_48, or_68_cse); + assign mux_27_nl = MUX_s_1_2_2(or_tmp_49, (~ main_stage_v_1), IsNaN_6U_10U_1_land_lpi_1_dfm_3); + assign mux_28_nl = MUX_s_1_2_2((mux_27_nl), or_tmp_49, IsNaN_6U_10U_land_lpi_1_dfm_st_3); + assign mux_29_nl = MUX_s_1_2_2((mux_28_nl), (mux_26_nl), or_5_cse); + assign mux_30_nl = MUX_s_1_2_2(or_tmp_52, nand_6_cse, FpMul_6U_10U_else_2_if_acc_itm_6_1); + assign mux_31_nl = MUX_s_1_2_2((mux_30_nl), or_tmp_52, or_68_cse); + assign nor_33_nl = ~(FpMul_6U_10U_lor_1_lpi_1_dfm_st_3 | nand_7_cse); + assign mux_32_nl = MUX_s_1_2_2((nor_33_nl), main_stage_v_1, IsNaN_6U_10U_land_lpi_1_dfm_st_3); + assign mux_33_nl = MUX_s_1_2_2((mux_32_nl), (~ (mux_31_nl)), or_5_cse); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_3_2; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [2:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + MUX1HOT_v_6_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [19:0] MUX_v_20_2_2; + input [19:0] input_0; + input [19:0] input_1; + input [0:0] sel; + reg [19:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_20_2_2 = result; + end + endfunction + function [21:0] MUX_v_22_2_2; + input [21:0] input_0; + input [21:0] input_1; + input [0:0] sel; + reg [21:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_22_2_2 = result; + end + endfunction + function [5:0] MUX_v_6_2_2; + input [5:0] input_0; + input [5:0] input_1; + input [0:0] sel; + reg [5:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_6_2_2 = result; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [5:0] readslicef_7_6_1; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 1; + readslicef_7_6_1 = tmp[5:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [9:0] signext_10_1; + input [0:0] vector; + begin + signext_10_1= {{9{vector[0]}}, vector}; + end + endfunction + function [7:0] conv_s2s_7_8 ; + input [6:0] vector ; + begin + conv_s2s_7_8 = {vector[6], vector}; + end + endfunction + function [6:0] conv_u2s_6_7 ; + input [5:0] vector ; + begin + conv_u2s_6_7 = {1'b0, vector}; + end + endfunction + function [7:0] conv_u2s_6_8 ; + input [5:0] vector ; + begin + conv_u2s_6_8 = {{2{1'b0}}, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [6:0] conv_u2u_6_7 ; + input [5:0] vector ; + begin + conv_u2u_6_7 = {1'b0, vector}; + end + endfunction + function [21:0] conv_u2u_22_22 ; + input [21:0] vector ; + begin + conv_u2u_22_22 = vector; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_mul +// ------------------------------------------------------------------ +module HLS_fp17_mul ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP17_MUL_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP17_MUL_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP17_MUL_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_mul_core HLS_fp17_mul_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_sub.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_sub.v new file mode 100644 index 0000000..a479199 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_sub.v @@ -0,0 +1,1829 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_sub.v +module FP17_SUB_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_SUB_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_SUB_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ../td_ccore_solutions/leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-144 +// Generated date: Sun Dec 11 16:48:02 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_leading_sign_23_0 +// ------------------------------------------------------------------ +module FP17_SUB_leading_sign_23_0 ( + mantissa, rtn +); + input [22:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_10; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[20:19]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[18:17]!=2'b00)); + assign c_h_1_2 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[16:15]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[12:11]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[10:9]!=2'b00)); + assign c_h_1_5 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[8:7]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[4:3]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 = ~((mantissa[2:1]!=2'b00)); + assign c_h_1_9 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + assign c_h_1_10 = c_h_1_6 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl = c_h_1_6 & (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3)) & (c_h_1_9 | (~ c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2)))) & c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl + = ((~((mantissa[22]) | (~((mantissa[21:20]!=2'b01))))) & (~(((mantissa[18]) + | (~((mantissa[17:16]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[14]) | (~((mantissa[13:12]!=2'b01))))) + & (~(((mantissa[10]) | (~((mantissa[9:8]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[6]) | (~((mantissa[5:4]!=2'b01))))) & (~((~((mantissa[2:1]==2'b01))) + & c_h_1_9)))) & c_h_1_10))) | ((~ (mantissa[0])) & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + & c_h_1_9 & c_h_1_10); + assign rtn = {c_h_1_10 , (IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl) + , (IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl)}; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP17_SUB_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP17_SUB_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:51:59 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_SUB_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP17_SUB_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_SUB_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_sub_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_sub_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [16:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [16:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [16:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_17_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 17'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_SUB_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [16:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [16:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core +// ------------------------------------------------------------------ +module HLS_fp17_sub_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [16:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [5:0] chn_o_rsci_d_15_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + wire FpAdd_6U_10U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_23U_11U_else_and_tmp; + wire IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + wire nor_tmp_1; + wire mux_tmp_1; + wire mux_tmp_2; + wire or_tmp_11; + wire and_tmp; + wire or_tmp_22; + wire mux_tmp_10; + wire mux_tmp_12; + wire and_tmp_3; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire or_tmp_46; + wire or_tmp_52; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_4; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_5; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_6; + reg [23:0] FpAdd_6U_10U_int_mant_p1_sva_3; + reg FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_4; + reg [5:0] FpAdd_6U_10U_o_expo_lpi_1_dfm_10; + reg FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + reg FpMantRNE_23U_11U_else_carry_sva_2; + reg FpMantRNE_23U_11U_else_and_svs_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_6; + reg FpAdd_6U_10U_IsZero_6U_10U_or_itm_2; + reg [6:0] FpAdd_6U_10U_a_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_a_left_shift_acc_itm_2; + reg FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2; + reg [6:0] FpAdd_6U_10U_b_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_b_left_shift_acc_itm_2; + reg [9:0] FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2; + reg [9:0] FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3; + reg FpAdd_6U_10U_mux_13_itm_4; + reg FpAdd_6U_10U_mux_13_itm_5; + reg FpAdd_6U_10U_mux_13_itm_6; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4; + reg [9:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_4; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_5; + reg [15:0] b_sva_1_15_0_1; + reg [15:0] FpAdd_6U_10U_a_sva_1_15_0_1; + wire main_stage_en_1; + wire FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + wire and_65_m1c; + reg reg_chn_a_rsci_iswt0_cse; + reg reg_chn_a_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_37_cse; + wire FpAdd_6U_10U_or_cse; + wire nor_4_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_17_cse; + wire nor_7_cse; + wire or_60_cse; + wire [21:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0; + wire and_47_rgt; + wire and_48_rgt; + wire and_50_rgt; + wire FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt; + wire FpAdd_6U_10U_and_1_rgt; + wire FpAdd_6U_10U_and_2_rgt; + wire and_58_rgt; + wire and_60_rgt; + wire FpSignedBitsToFloat_6U_10U_1_or_1_rgt; + wire [22:0] FpNormalize_6U_23U_else_lshift_itm; + wire FpAdd_6U_10U_a_right_shift_qelse_and_tmp; + wire [5:0] z_out; + wire FpAdd_6U_10U_if_2_and_tmp; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire FpMantRNE_23U_11U_else_carry_sva_mx0w0; + wire FpAdd_6U_10U_and_tmp; + wire [22:0] FpAdd_6U_10U_addend_larger_asn_1_mx0w1; + wire [22:0] FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_a_int_mant_p1_sva; + wire [22:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1; + wire FpNormalize_6U_23U_oelse_not_3; + wire [4:0] libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1; + wire IsNaN_6U_10U_aelse_and_cse; + wire FpAdd_6U_10U_and_8_cse; + wire IsNaN_6U_10U_1_aelse_and_cse; + reg reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse; + wire FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + wire FpAdd_6U_10U_if_3_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_if_4_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1; + wire[9:0] FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl; + wire[9:0] FpMantRNE_23U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_23U_11U_else_acc_nl; + wire[0:0] FpMantRNE_23U_11U_else_o_mant_and_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_nl; + wire[0:0] FpAdd_6U_10U_and_nl; + wire[0:0] FpAdd_6U_10U_and_3_nl; + wire[0:0] FpAdd_6U_10U_and_7_nl; + wire[24:0] acc_1_nl; + wire[25:0] nl_acc_1_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_2_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_3_nl; + wire[0:0] mux_6_nl; + wire[0:0] mux_4_nl; + wire[0:0] mux_3_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_38_nl; + wire[0:0] and_91_nl; + wire[0:0] mux_7_nl; + wire[0:0] nor_34_nl; + wire[0:0] nor_35_nl; + wire[5:0] FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl; + wire[5:0] FpNormalize_6U_23U_else_acc_nl; + wire[7:0] nl_FpNormalize_6U_23U_else_acc_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_nl; + wire[0:0] mux_14_nl; + wire[0:0] mux_13_nl; + wire[0:0] and_12_nl; + wire[0:0] or_30_nl; + wire[0:0] mux_16_nl; + wire[0:0] or_31_nl; + wire[0:0] mux_15_nl; + wire[0:0] nor_29_nl; + wire[0:0] mux_18_nl; + wire[0:0] or_35_nl; + wire[0:0] mux_17_nl; + wire[0:0] nor_28_nl; + wire[0:0] and_90_nl; + wire[0:0] mux_23_nl; + wire[0:0] nor_53_nl; + wire[0:0] and_99_nl; + wire[5:0] FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[5:0] FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[0:0] FpAdd_6U_10U_is_a_greater_oelse_not_5_nl; + wire[0:0] mux_29_nl; + wire[0:0] or_73_nl; + wire[0:0] nor_24_nl; + wire[0:0] and_89_nl; + wire[0:0] mux_30_nl; + wire[0:0] nand_1_nl; + wire[0:0] nor_23_nl; + wire[0:0] and_88_nl; + wire[6:0] FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[8:0] nl_FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[0:0] FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl; + wire[6:0] FpNormalize_6U_23U_acc_nl; + wire[8:0] nl_FpNormalize_6U_23U_acc_nl; + wire[0:0] or_1_nl; + wire[0:0] mux_nl; + wire[0:0] nor_45_nl; + wire[0:0] or_3_nl; + wire[0:0] nor_44_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_33_nl; + wire[0:0] mux_11_nl; + wire[0:0] or_25_nl; + wire[0:0] mux_8_nl; + wire[0:0] nor_30_nl; + wire[0:0] nor_31_nl; + wire[10:0] FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[12:0] nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[6:0] acc_nl; + wire[7:0] nl_acc_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_2_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_3_nl; +// Interconnect Declarations for Component Instantiations + wire [22:0] nl_leading_sign_23_0_rg_mantissa; + assign nl_leading_sign_23_0_rg_mantissa = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [10:0] nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 + , (b_sva_1_15_0_1[9:0])}; + wire [10:0] nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 + , (FpAdd_6U_10U_a_sva_1_15_0_1[9:0])}; + wire [22:0] nl_FpNormalize_6U_23U_else_lshift_rg_a; + assign nl_FpNormalize_6U_23U_else_lshift_rg_a = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [16:0] nl_HLS_fp17_sub_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_sub_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 , chn_o_rsci_d_15_10 + , chn_o_rsci_d_9_0}; + FP17_SUB_leading_sign_23_0 leading_sign_23_0_rg ( + .mantissa(nl_leading_sign_23_0_rg_mantissa[22:0]), + .rtn(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + ); + FP17_SUB_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_b_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_addend_larger_asn_1_mx0w1) + ); + FP17_SUB_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_a_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_a_int_mant_p1_sva) + ); + FP17_SUB_mgc_shift_l_v4 #(.width_a(32'sd23), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd23)) FpNormalize_6U_23U_else_lshift_rg ( + .a(nl_FpNormalize_6U_23U_else_lshift_rg_a[22:0]), + .s(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1), + .z(FpNormalize_6U_23U_else_lshift_itm) + ); + HLS_fp17_sub_core_chn_a_rsci HLS_fp17_sub_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_sub_core_chn_b_rsci HLS_fp17_sub_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp17_sub_core_chn_o_rsci HLS_fp17_sub_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_sub_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp17_sub_core_staller HLS_fp17_sub_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_sub_core_core_fsm HLS_fp17_sub_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_6U_10U_or_cse = IsNaN_6U_10U_1_land_lpi_1_dfm_6 | IsNaN_6U_10U_land_lpi_1_dfm_6; + assign IsNaN_6U_10U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_tmp_1; + assign FpAdd_6U_10U_and_8_cse = core_wen & (~ and_dcpl_7) & mux_tmp_2; + assign nor_37_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23])) + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign and_47_rgt = (~ IsNaN_6U_10U_land_lpi_1_dfm_st_5) & (~ IsNaN_6U_10U_1_land_lpi_1_dfm_5) + & or_17_cse; + assign and_48_rgt = or_17_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_5; + assign and_50_rgt = (~ IsNaN_6U_10U_land_lpi_1_dfm_st_5) & IsNaN_6U_10U_1_land_lpi_1_dfm_5 + & or_17_cse; + assign nor_4_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23]))); + assign or_17_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + | and_dcpl_7); + assign FpAdd_6U_10U_and_1_rgt = (~ FpAdd_6U_10U_if_3_if_acc_1_itm_5_1) & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign FpAdd_6U_10U_and_2_rgt = FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign or_31_nl = nor_7_cse | main_stage_v_2; + assign nor_29_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_15_nl = MUX_s_1_2_2((nor_29_nl), main_stage_v_2, chn_o_rsci_bawt); + assign mux_16_nl = MUX_s_1_2_2((mux_15_nl), (or_31_nl), main_stage_v_3); + assign IsNaN_6U_10U_1_aelse_and_cse = core_wen & (~ and_dcpl_7) & (mux_16_nl); + assign nor_7_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_60_cse = (FpAdd_6U_10U_is_a_greater_oif_equal_tmp & (~ FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1)) + | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + assign and_58_rgt = or_17_cse & (~ FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1) & ((~ + FpAdd_6U_10U_is_a_greater_oif_equal_tmp) | FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1); + assign and_60_rgt = or_17_cse & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_4); + assign and_65_m1c = or_17_cse & (~(IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp)); + assign FpSignedBitsToFloat_6U_10U_1_or_1_rgt = (or_17_cse & (~ IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) + & IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp) | ((~ or_60_cse) & and_65_m1c); + assign FpAdd_6U_10U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[15:10]) == + (chn_b_rsci_d_mxwt[15:10]); + assign IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_a_rsci_d_mxwt[15:10]!=6'b111111)); + assign FpMantRNE_23U_11U_else_carry_sva_mx0w0 = (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[11]) + & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[0]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[1]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[2]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[3]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[4]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[5]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[6]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[7]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[8]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[9]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[10]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[12])); + assign FpMantRNE_23U_11U_else_and_tmp = FpMantRNE_23U_11U_else_carry_sva_mx0w0 + & (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]==10'b1111111111) & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[22]) + | (FpAdd_6U_10U_int_mant_p1_sva_3[23])); + assign IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp = ~((~((chn_b_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_b_rsci_d_mxwt[15:10]!=6'b111111)); + assign nl_FpAdd_6U_10U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[15:10])}) + + conv_u2u_6_7(~ (chn_a_rsci_d_mxwt[15:10])) + 7'b1; + assign FpAdd_6U_10U_is_a_greater_acc_1_nl = nl_FpAdd_6U_10U_is_a_greater_acc_1_nl[6:0]; + assign FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1 = readslicef_7_1_6((FpAdd_6U_10U_is_a_greater_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_qr_lpi_1_dfm_4[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_1_nl = nl_FpAdd_6U_10U_if_3_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_3_if_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_o_expo_lpi_1_dfm_10[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_1_nl = nl_FpAdd_6U_10U_if_4_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_4_if_acc_1_nl)); + assign FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_4 + | (~ FpAdd_6U_10U_if_4_if_acc_1_itm_5_1); + assign FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_6U_10U_is_inf_lpi_1_dfm_4, + (FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl), FpMantRNE_23U_11U_else_and_svs_2); + assign FpAdd_6U_10U_and_tmp = FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 & FpMantRNE_23U_11U_else_and_svs_2; + assign FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c = ~(IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_en_1 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_17_cse; + assign FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_asn_1_mx0w1, + FpAdd_6U_10U_a_int_mant_p1_sva, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_a_int_mant_p1_sva, + FpAdd_6U_10U_addend_larger_asn_1_mx0w1, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0 = MUX_v_22_2_2((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[21:0]), + (FpAdd_6U_10U_int_mant_p1_sva_3[22:1]), FpAdd_6U_10U_int_mant_p1_sva_3[23]); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1 = MUX_v_23_2_2(23'b00000000000000000000000, + FpNormalize_6U_23U_else_lshift_itm, FpNormalize_6U_23U_oelse_not_3); + assign nl_FpNormalize_6U_23U_acc_nl = ({1'b1 , (~ FpAdd_6U_10U_qr_lpi_1_dfm_4)}) + + conv_u2s_5_7(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + + 7'b1; + assign FpNormalize_6U_23U_acc_nl = nl_FpNormalize_6U_23U_acc_nl[6:0]; + assign FpNormalize_6U_23U_oelse_not_3 = ((FpAdd_6U_10U_int_mant_p1_sva_3[22:0]!=23'b00000000000000000000000)) + & (readslicef_7_1_6((FpNormalize_6U_23U_acc_nl))); + assign nor_tmp_1 = chn_b_rsci_bawt & chn_a_rsci_bawt; + assign or_1_nl = nor_7_cse | nor_tmp_1; + assign nor_45_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_1)); + assign mux_nl = MUX_s_1_2_2((nor_45_nl), nor_tmp_1, chn_o_rsci_bawt); + assign mux_tmp_1 = MUX_s_1_2_2((mux_nl), (or_1_nl), main_stage_v_1); + assign or_3_nl = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | main_stage_v_2; + assign nor_44_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2))); + assign mux_tmp_2 = MUX_s_1_2_2((nor_44_nl), (or_3_nl), main_stage_v_1); + assign or_tmp_11 = main_stage_v_2 | (~ or_17_cse); + assign and_tmp = main_stage_v_2 & or_17_cse; + assign or_tmp_22 = IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_5; + assign nor_33_nl = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) | (~ or_17_cse)); + assign mux_9_nl = MUX_s_1_2_2((nor_33_nl), or_17_cse, FpAdd_6U_10U_if_3_if_acc_1_itm_5_1); + assign nor_32_nl = ~(or_tmp_22 | (~ (mux_9_nl))); + assign mux_tmp_10 = MUX_s_1_2_2((nor_32_nl), or_17_cse, FpMantRNE_23U_11U_else_and_tmp); + assign nor_30_nl = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & or_17_cse))); + assign mux_8_nl = MUX_s_1_2_2((nor_30_nl), or_17_cse, or_tmp_22); + assign or_25_nl = FpMantRNE_23U_11U_else_and_tmp | (~ (mux_8_nl)); + assign mux_11_nl = MUX_s_1_2_2(mux_tmp_10, (or_25_nl), main_stage_v_3); + assign nor_31_nl = ~((~ main_stage_v_3) | (~ reg_chn_o_rsci_ld_core_psct_cse) | + chn_o_rsci_bawt); + assign mux_tmp_12 = MUX_s_1_2_2((nor_31_nl), (mux_11_nl), main_stage_v_2); + assign and_tmp_3 = main_stage_v_2 & or_tmp_22; + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_17_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign or_tmp_46 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_52 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_17_cse & (fsm_output[1]); + assign chn_o_rsci_d_9_0_mx0c1 = or_17_cse & main_stage_v_3 & (~ IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_a_rsci_bawt & chn_b_rsci_bawt)) & or_17_cse + & main_stage_v_1; + assign main_stage_v_2_mx0c1 = or_17_cse & main_stage_v_2 & (~ main_stage_v_1); + assign main_stage_v_3_mx0c1 = or_17_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[9:0])}) + + conv_u2u_10_11(~ (chn_b_rsci_d_mxwt[9:0])) + 11'b1; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl[10:0]; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 = readslicef_11_1_10((FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_52; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + assign FpAdd_6U_10U_a_right_shift_qelse_and_tmp = (fsm_output[1]) & (~((~(FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 + | (~ FpAdd_6U_10U_is_a_greater_oif_equal_tmp))) | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1)); + assign FpAdd_6U_10U_if_2_and_tmp = (fsm_output[1]) & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_a_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_46 ) begin + reg_chn_a_rsci_ld_core_psct_cse <= or_tmp_46; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_17_cse & main_stage_v_3 & IsNaN_6U_10U_land_lpi_1_dfm_6) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3, + (FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl), FpMantRNE_23U_11U_else_o_mant_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15_10 <= 6'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_15_10 <= MUX1HOT_v_6_4_2(FpAdd_6U_10U_o_expo_lpi_1_dfm_10, (FpAdd_6U_10U_if_4_if_acc_nl), + 6'b111110, FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4, + {(FpAdd_6U_10U_and_nl) , (FpAdd_6U_10U_and_3_nl) , (FpAdd_6U_10U_and_7_nl) + , FpAdd_6U_10U_or_cse}); + chn_o_rsci_d_16 <= FpAdd_6U_10U_mux_13_itm_6; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_52 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= 1'b0; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse + <= 1'b0; + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= 1'b0; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= 1'b0; + b_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= 7'b0; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= 1'b0; + FpAdd_6U_10U_a_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= 7'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_aelse_and_cse ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse + <= (chn_a_rsci_d_mxwt[16]) ^ (chn_b_rsci_d_mxwt[16]); + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= or_60_cse; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[15:0]!=16'b0000000000000000); + b_sva_1_15_0_1 <= chn_b_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_b_left_shift_acc_itm_2[6:0]; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= (chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000); + FpAdd_6U_10U_a_sva_1_15_0_1 <= chn_a_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_a_left_shift_acc_itm_2[6:0]; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_17_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) + begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= 6'b0; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= 1'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_5 <= 1'b0; + end + else if ( FpAdd_6U_10U_and_8_cse ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= FpAdd_6U_10U_qr_lpi_1_dfm_3; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= IsNaN_6U_10U_land_lpi_1_dfm_st_4; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= IsNaN_6U_10U_1_land_lpi_1_dfm_4; + FpAdd_6U_10U_mux_13_itm_5 <= FpAdd_6U_10U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= 24'b0; + end + else if ( core_wen & (~((~(or_17_cse & (~ reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse))) + & (~(or_17_cse & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse)))) + & mux_tmp_2 ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= readslicef_25_24_1((acc_1_nl)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & (and_tmp | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3 <= + 10'b0; + end + else if ( core_wen & (and_47_rgt | and_48_rgt | and_50_rgt) & (mux_6_nl) ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3 <= + MUX1HOT_v_10_3_2((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]), + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2, + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2, + {and_47_rgt , and_48_rgt , and_50_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_7_nl) ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= FpMantRNE_23U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= 6'b0; + end + else if ( core_wen & (FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt | FpAdd_6U_10U_and_1_rgt + | FpAdd_6U_10U_and_2_rgt) & (mux_14_nl) ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= MUX1HOT_v_6_3_2((FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl), + FpAdd_6U_10U_qr_lpi_1_dfm_4, (FpAdd_6U_10U_if_3_if_acc_nl), {FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt + , FpAdd_6U_10U_and_1_rgt , FpAdd_6U_10U_and_2_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_6 <= 1'b0; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= 1'b0; + FpMantRNE_23U_11U_else_and_svs_2 <= 1'b0; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_1_aelse_and_cse ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= IsNaN_6U_10U_1_land_lpi_1_dfm_5; + FpAdd_6U_10U_mux_13_itm_6 <= FpAdd_6U_10U_mux_13_itm_5; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= IsNaN_6U_10U_land_lpi_1_dfm_st_5; + FpMantRNE_23U_11U_else_and_svs_2 <= FpMantRNE_23U_11U_else_and_tmp; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= nor_4_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= 6'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_18_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2 <= + 10'b0; + end + else if ( core_wen & ((and_tmp & (~(IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_4))) + | (or_17_cse & IsNaN_6U_10U_1_land_lpi_1_dfm_4)) & (mux_23_nl) ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2 <= + b_sva_1_15_0_1[9:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= 6'b0; + end + else if ( core_wen & ((or_60_cse & or_17_cse) | and_58_rgt) & mux_tmp_1 ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), (chn_b_rsci_d_mxwt[15:10]), + and_58_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= 6'b0; + end + else if ( core_wen & ((or_17_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_4) | and_60_rgt) + & (mux_29_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= MUX_v_6_2_2((FpAdd_6U_10U_a_sva_1_15_0_1[15:10]), (b_sva_1_15_0_1[15:10]), + and_60_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2 + <= 10'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_30_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2 + <= FpAdd_6U_10U_a_sva_1_15_0_1[9:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_mux_13_itm_4 <= 1'b0; + end + else if ( core_wen & ((or_17_cse & IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) | (or_60_cse + & and_65_m1c) | FpSignedBitsToFloat_6U_10U_1_or_1_rgt) & mux_tmp_1 ) begin + FpAdd_6U_10U_mux_13_itm_4 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[16]), (~ (chn_b_rsci_d_mxwt[16])), + FpSignedBitsToFloat_6U_10U_1_or_1_rgt); + end + end + assign nl_FpMantRNE_23U_11U_else_acc_nl = FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3 + + conv_u2u_1_10(FpMantRNE_23U_11U_else_carry_sva_2); + assign FpMantRNE_23U_11U_else_acc_nl = nl_FpMantRNE_23U_11U_else_acc_nl[9:0]; + assign FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl = MUX_v_10_2_2((FpMantRNE_23U_11U_else_acc_nl), + 10'b1111111111, FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0); + assign FpMantRNE_23U_11U_else_o_mant_and_nl = (~ IsNaN_6U_10U_1_land_lpi_1_dfm_6) + & chn_o_rsci_d_9_0_mx0c1; + assign nl_FpAdd_6U_10U_if_4_if_acc_nl = FpAdd_6U_10U_o_expo_lpi_1_dfm_10 + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_nl = nl_FpAdd_6U_10U_if_4_if_acc_nl[5:0]; + assign FpAdd_6U_10U_and_nl = (~(FpAdd_6U_10U_and_tmp | FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_3_nl = FpAdd_6U_10U_and_tmp & (~ FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_7_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, or_60_cse)); + assign nl_FpAdd_6U_10U_b_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_is_a_greater_oelse_not_5_nl = ~ or_60_cse; + assign FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, (FpAdd_6U_10U_is_a_greater_oelse_not_5_nl))); + assign nl_FpAdd_6U_10U_a_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_else_2_mux_2_nl = MUX_v_23_2_2((~ FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0), + FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign FpAdd_6U_10U_else_2_mux_3_nl = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, + FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign nl_acc_1_nl = ({(~ FpAdd_6U_10U_if_2_and_tmp) , (FpAdd_6U_10U_else_2_mux_2_nl) + , (~ FpAdd_6U_10U_if_2_and_tmp)}) + conv_u2u_24_25({(FpAdd_6U_10U_else_2_mux_3_nl) + , 1'b1}); + assign acc_1_nl = nl_acc_1_nl[24:0]; + assign mux_3_nl = MUX_s_1_2_2(or_tmp_11, (~ or_17_cse), nor_37_cse); + assign mux_4_nl = MUX_s_1_2_2((mux_3_nl), or_tmp_11, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign nor_38_nl = ~(nor_37_cse | (~ and_tmp)); + assign mux_5_nl = MUX_s_1_2_2((nor_38_nl), and_tmp, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign and_91_nl = ((~ FpAdd_6U_10U_is_inf_lpi_1_dfm_4) | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6) & main_stage_v_3; + assign mux_6_nl = MUX_s_1_2_2((mux_5_nl), (mux_4_nl), and_91_nl); + assign nor_34_nl = ~(nor_4_cse | (~ main_stage_v_2) | IsNaN_6U_10U_land_lpi_1_dfm_st_5 + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign nor_35_nl = ~((~ main_stage_v_3) | IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4); + assign mux_7_nl = MUX_s_1_2_2((nor_35_nl), (nor_34_nl), or_17_cse); + assign nl_FpNormalize_6U_23U_else_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + ({1'b1 + , (~ libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1)}) + + 6'b1; + assign FpNormalize_6U_23U_else_acc_nl = nl_FpNormalize_6U_23U_else_acc_nl[5:0]; + assign FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl = MUX_v_6_2_2(6'b000000, (FpNormalize_6U_23U_else_acc_nl), + FpNormalize_6U_23U_oelse_not_3); + assign nl_FpAdd_6U_10U_if_3_if_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_nl = nl_FpAdd_6U_10U_if_3_if_acc_nl[5:0]; + assign and_12_nl = main_stage_v_2 & mux_tmp_10; + assign or_30_nl = IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + assign mux_13_nl = MUX_s_1_2_2(mux_tmp_12, (and_12_nl), or_30_nl); + assign mux_14_nl = MUX_s_1_2_2((mux_13_nl), mux_tmp_12, FpMantRNE_23U_11U_else_and_svs_2); + assign or_35_nl = nor_7_cse | and_tmp_3; + assign nor_28_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ and_tmp_3)); + assign mux_17_nl = MUX_s_1_2_2((nor_28_nl), and_tmp_3, chn_o_rsci_bawt); + assign and_90_nl = FpAdd_6U_10U_or_cse & main_stage_v_3; + assign mux_18_nl = MUX_s_1_2_2((mux_17_nl), (or_35_nl), and_90_nl); + assign nor_53_nl = ~((~ IsNaN_6U_10U_1_land_lpi_1_dfm_4) | (~ main_stage_v_1) | + IsNaN_6U_10U_land_lpi_1_dfm_st_4); + assign and_99_nl = IsNaN_6U_10U_1_land_lpi_1_dfm_5 & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_5) + & main_stage_v_2; + assign mux_23_nl = MUX_s_1_2_2((and_99_nl), (nor_53_nl), or_17_cse); + assign or_73_nl = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | and_tmp_3; + assign nor_24_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2 + & or_tmp_22))); + assign and_89_nl = (IsNaN_6U_10U_land_lpi_1_dfm_st_4 | IsNaN_6U_10U_1_land_lpi_1_dfm_4) + & main_stage_v_1; + assign mux_29_nl = MUX_s_1_2_2((nor_24_nl), (or_73_nl), and_89_nl); + assign nand_1_nl = ~(nor_7_cse & (~(main_stage_v_2 & IsNaN_6U_10U_land_lpi_1_dfm_st_5))); + assign nor_23_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2 + & IsNaN_6U_10U_land_lpi_1_dfm_st_5))); + assign and_88_nl = IsNaN_6U_10U_land_lpi_1_dfm_st_4 & main_stage_v_1; + assign mux_30_nl = MUX_s_1_2_2((nor_23_nl), (nand_1_nl), and_88_nl); + assign FpAdd_6U_10U_b_right_shift_qif_mux_2_nl = MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), + (chn_b_rsci_d_mxwt[15:10]), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign FpAdd_6U_10U_b_right_shift_qif_mux_3_nl = MUX_v_6_2_2((~ (chn_b_rsci_d_mxwt[15:10])), + (~ (chn_a_rsci_d_mxwt[15:10])), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign nl_acc_nl = ({(FpAdd_6U_10U_b_right_shift_qif_mux_2_nl) , 1'b1}) + ({(FpAdd_6U_10U_b_right_shift_qif_mux_3_nl) + , 1'b1}); + assign acc_nl = nl_acc_nl[6:0]; + assign z_out = readslicef_7_6_1((acc_nl)); + function [9:0] MUX1HOT_v_10_3_2; + input [9:0] input_2; + input [9:0] input_1; + input [9:0] input_0; + input [2:0] sel; + reg [9:0] result; + begin + result = input_0 & {10{sel[0]}}; + result = result | ( input_1 & {10{sel[1]}}); + result = result | ( input_2 & {10{sel[2]}}); + MUX1HOT_v_10_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_3_2; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [2:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + MUX1HOT_v_6_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_4_2; + input [5:0] input_3; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [3:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + result = result | ( input_3 & {6{sel[3]}}); + MUX1HOT_v_6_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [21:0] MUX_v_22_2_2; + input [21:0] input_0; + input [21:0] input_1; + input [0:0] sel; + reg [21:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_22_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [5:0] MUX_v_6_2_2; + input [5:0] input_0; + input [5:0] input_1; + input [0:0] sel; + reg [5:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_6_2_2 = result; + end + endfunction + function [0:0] readslicef_11_1_10; + input [10:0] vector; + reg [10:0] tmp; + begin + tmp = vector >> 10; + readslicef_11_1_10 = tmp[0:0]; + end + endfunction + function [23:0] readslicef_25_24_1; + input [24:0] vector; + reg [24:0] tmp; + begin + tmp = vector >> 1; + readslicef_25_24_1 = tmp[23:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [5:0] readslicef_7_6_1; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 1; + readslicef_7_6_1 = tmp[5:0]; + end + endfunction + function [6:0] conv_u2s_5_7 ; + input [4:0] vector ; + begin + conv_u2s_5_7 = {{2{1'b0}}, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [6:0] conv_u2u_6_7 ; + input [5:0] vector ; + begin + conv_u2u_6_7 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_10_11 ; + input [9:0] vector ; + begin + conv_u2u_10_11 = {1'b0, vector}; + end + endfunction + function [24:0] conv_u2u_24_25 ; + input [23:0] vector ; + begin + conv_u2u_24_25 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub +// ------------------------------------------------------------------ +module HLS_fp17_sub ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP17_SUB_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP17_SUB_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP17_SUB_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_sub_core HLS_fp17_sub_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_sub.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_sub.v.vcp new file mode 100644 index 0000000..a479199 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_sub.v.vcp @@ -0,0 +1,1829 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_sub.v +module FP17_SUB_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_SUB_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_SUB_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ../td_ccore_solutions/leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-144 +// Generated date: Sun Dec 11 16:48:02 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_leading_sign_23_0 +// ------------------------------------------------------------------ +module FP17_SUB_leading_sign_23_0 ( + mantissa, rtn +); + input [22:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_10; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl; + wire[0:0] IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[20:19]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[18:17]!=2'b00)); + assign c_h_1_2 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[16:15]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[12:11]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[10:9]!=2'b00)); + assign c_h_1_5 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[8:7]==2'b00) + & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[4:3]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 = ~((mantissa[2:1]!=2'b00)); + assign c_h_1_9 = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2; + assign c_h_1_10 = c_h_1_6 & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl = c_h_1_6 & (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_42_4_sdt_4); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_18_3_sdt_3)) & (c_h_1_9 | (~ c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl = IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + | (~ IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_50_2_sdt_2)))) & c_h_1_10)); + assign IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl + = ((~((mantissa[22]) | (~((mantissa[21:20]!=2'b01))))) & (~(((mantissa[18]) + | (~((mantissa[17:16]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[14]) | (~((mantissa[13:12]!=2'b01))))) + & (~(((mantissa[10]) | (~((mantissa[9:8]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[6]) | (~((mantissa[5:4]!=2'b01))))) & (~((~((mantissa[2:1]==2'b01))) + & c_h_1_9)))) & c_h_1_10))) | ((~ (mantissa[0])) & IntLeadZero_23U_leading_sign_23_0_rtn_wrs_c_56_2_sdt_1 + & c_h_1_9 & c_h_1_10); + assign rtn = {c_h_1_10 , (IntLeadZero_23U_leading_sign_23_0_rtn_and_85_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_and_83_nl) + , (IntLeadZero_23U_leading_sign_23_0_rtn_and_90_nl) , (IntLeadZero_23U_leading_sign_23_0_rtn_IntLeadZero_23U_leading_sign_23_0_rtn_or_2_nl)}; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP17_SUB_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP17_SUB_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:51:59 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_SUB_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP17_SUB_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_SUB_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_SUB_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_sub_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_sub_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [16:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [16:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [16:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_17_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 17'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_SUB_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_sub_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [16:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [16:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp HLS_fp17_sub_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_sub_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_sub_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub_core +// ------------------------------------------------------------------ +module HLS_fp17_sub_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [16:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [5:0] chn_o_rsci_d_15_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + wire FpAdd_6U_10U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_23U_11U_else_and_tmp; + wire IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + wire nor_tmp_1; + wire mux_tmp_1; + wire mux_tmp_2; + wire or_tmp_11; + wire and_tmp; + wire or_tmp_22; + wire mux_tmp_10; + wire mux_tmp_12; + wire and_tmp_3; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire or_tmp_46; + wire or_tmp_52; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_4; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_5; + reg IsNaN_6U_10U_1_land_lpi_1_dfm_6; + reg [23:0] FpAdd_6U_10U_int_mant_p1_sva_3; + reg FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_3; + reg [5:0] FpAdd_6U_10U_qr_lpi_1_dfm_4; + reg [5:0] FpAdd_6U_10U_o_expo_lpi_1_dfm_10; + reg FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + reg FpMantRNE_23U_11U_else_carry_sva_2; + reg FpMantRNE_23U_11U_else_and_svs_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_6; + reg FpAdd_6U_10U_IsZero_6U_10U_or_itm_2; + reg [6:0] FpAdd_6U_10U_a_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_a_left_shift_acc_itm_2; + reg FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2; + reg [6:0] FpAdd_6U_10U_b_left_shift_acc_itm_2; + wire [7:0] nl_FpAdd_6U_10U_b_left_shift_acc_itm_2; + reg [9:0] FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2; + reg [9:0] FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3; + reg FpAdd_6U_10U_mux_13_itm_4; + reg FpAdd_6U_10U_mux_13_itm_5; + reg FpAdd_6U_10U_mux_13_itm_6; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + reg [5:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4; + reg [9:0] FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_4; + reg IsNaN_6U_10U_land_lpi_1_dfm_st_5; + reg [15:0] b_sva_1_15_0_1; + reg [15:0] FpAdd_6U_10U_a_sva_1_15_0_1; + wire main_stage_en_1; + wire FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + wire and_65_m1c; + reg reg_chn_a_rsci_iswt0_cse; + reg reg_chn_a_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_37_cse; + wire FpAdd_6U_10U_or_cse; + wire nor_4_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_17_cse; + wire nor_7_cse; + wire or_60_cse; + wire [21:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0; + wire and_47_rgt; + wire and_48_rgt; + wire and_50_rgt; + wire FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt; + wire FpAdd_6U_10U_and_1_rgt; + wire FpAdd_6U_10U_and_2_rgt; + wire and_58_rgt; + wire and_60_rgt; + wire FpSignedBitsToFloat_6U_10U_1_or_1_rgt; + wire [22:0] FpNormalize_6U_23U_else_lshift_itm; + wire FpAdd_6U_10U_a_right_shift_qelse_and_tmp; + wire [5:0] z_out; + wire FpAdd_6U_10U_if_2_and_tmp; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire FpMantRNE_23U_11U_else_carry_sva_mx0w0; + wire FpAdd_6U_10U_and_tmp; + wire [22:0] FpAdd_6U_10U_addend_larger_asn_1_mx0w1; + wire [22:0] FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [22:0] FpAdd_6U_10U_a_int_mant_p1_sva; + wire [22:0] FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1; + wire FpNormalize_6U_23U_oelse_not_3; + wire [4:0] libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1; + wire IsNaN_6U_10U_aelse_and_cse; + wire FpAdd_6U_10U_and_8_cse; + wire IsNaN_6U_10U_1_aelse_and_cse; + reg reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse; + wire FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + wire FpAdd_6U_10U_if_3_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_if_4_if_acc_1_itm_5_1; + wire FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1; + wire[9:0] FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl; + wire[9:0] FpMantRNE_23U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_23U_11U_else_acc_nl; + wire[0:0] FpMantRNE_23U_11U_else_o_mant_and_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_nl; + wire[0:0] FpAdd_6U_10U_and_nl; + wire[0:0] FpAdd_6U_10U_and_3_nl; + wire[0:0] FpAdd_6U_10U_and_7_nl; + wire[24:0] acc_1_nl; + wire[25:0] nl_acc_1_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_2_nl; + wire[22:0] FpAdd_6U_10U_else_2_mux_3_nl; + wire[0:0] mux_6_nl; + wire[0:0] mux_4_nl; + wire[0:0] mux_3_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_38_nl; + wire[0:0] and_91_nl; + wire[0:0] mux_7_nl; + wire[0:0] nor_34_nl; + wire[0:0] nor_35_nl; + wire[5:0] FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl; + wire[5:0] FpNormalize_6U_23U_else_acc_nl; + wire[7:0] nl_FpNormalize_6U_23U_else_acc_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_nl; + wire[0:0] mux_14_nl; + wire[0:0] mux_13_nl; + wire[0:0] and_12_nl; + wire[0:0] or_30_nl; + wire[0:0] mux_16_nl; + wire[0:0] or_31_nl; + wire[0:0] mux_15_nl; + wire[0:0] nor_29_nl; + wire[0:0] mux_18_nl; + wire[0:0] or_35_nl; + wire[0:0] mux_17_nl; + wire[0:0] nor_28_nl; + wire[0:0] and_90_nl; + wire[0:0] mux_23_nl; + wire[0:0] nor_53_nl; + wire[0:0] and_99_nl; + wire[5:0] FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[5:0] FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl; + wire[0:0] FpAdd_6U_10U_is_a_greater_oelse_not_5_nl; + wire[0:0] mux_29_nl; + wire[0:0] or_73_nl; + wire[0:0] nor_24_nl; + wire[0:0] and_89_nl; + wire[0:0] mux_30_nl; + wire[0:0] nand_1_nl; + wire[0:0] nor_23_nl; + wire[0:0] and_88_nl; + wire[6:0] FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[8:0] nl_FpAdd_6U_10U_is_a_greater_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_3_if_acc_1_nl; + wire[5:0] FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[6:0] nl_FpAdd_6U_10U_if_4_if_acc_1_nl; + wire[0:0] FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl; + wire[6:0] FpNormalize_6U_23U_acc_nl; + wire[8:0] nl_FpNormalize_6U_23U_acc_nl; + wire[0:0] or_1_nl; + wire[0:0] mux_nl; + wire[0:0] nor_45_nl; + wire[0:0] or_3_nl; + wire[0:0] nor_44_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_33_nl; + wire[0:0] mux_11_nl; + wire[0:0] or_25_nl; + wire[0:0] mux_8_nl; + wire[0:0] nor_30_nl; + wire[0:0] nor_31_nl; + wire[10:0] FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[12:0] nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl; + wire[6:0] acc_nl; + wire[7:0] nl_acc_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_2_nl; + wire[5:0] FpAdd_6U_10U_b_right_shift_qif_mux_3_nl; +// Interconnect Declarations for Component Instantiations + wire [22:0] nl_leading_sign_23_0_rg_mantissa; + assign nl_leading_sign_23_0_rg_mantissa = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [10:0] nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 + , (b_sva_1_15_0_1[9:0])}; + wire [10:0] nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a = {FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 + , (FpAdd_6U_10U_a_sva_1_15_0_1[9:0])}; + wire [22:0] nl_FpNormalize_6U_23U_else_lshift_rg_a; + assign nl_FpNormalize_6U_23U_else_lshift_rg_a = FpAdd_6U_10U_int_mant_p1_sva_3[22:0]; + wire [16:0] nl_HLS_fp17_sub_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_sub_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 , chn_o_rsci_d_15_10 + , chn_o_rsci_d_9_0}; + FP17_SUB_leading_sign_23_0 leading_sign_23_0_rg ( + .mantissa(nl_leading_sign_23_0_rg_mantissa[22:0]), + .rtn(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + ); + FP17_SUB_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_b_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_b_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_addend_larger_asn_1_mx0w1) + ); + FP17_SUB_mgc_shift_bl_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd7), + .width_z(32'sd23)) FpAdd_6U_10U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_6U_10U_a_int_mant_p1_lshift_rg_a[10:0]), + .s(FpAdd_6U_10U_a_left_shift_acc_itm_2), + .z(FpAdd_6U_10U_a_int_mant_p1_sva) + ); + FP17_SUB_mgc_shift_l_v4 #(.width_a(32'sd23), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd23)) FpNormalize_6U_23U_else_lshift_rg ( + .a(nl_FpNormalize_6U_23U_else_lshift_rg_a[22:0]), + .s(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1), + .z(FpNormalize_6U_23U_else_lshift_itm) + ); + HLS_fp17_sub_core_chn_a_rsci HLS_fp17_sub_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_sub_core_chn_b_rsci HLS_fp17_sub_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp17_sub_core_chn_o_rsci HLS_fp17_sub_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_sub_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp17_sub_core_staller HLS_fp17_sub_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_sub_core_core_fsm HLS_fp17_sub_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_6U_10U_or_cse = IsNaN_6U_10U_1_land_lpi_1_dfm_6 | IsNaN_6U_10U_land_lpi_1_dfm_6; + assign IsNaN_6U_10U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_tmp_1; + assign FpAdd_6U_10U_and_8_cse = core_wen & (~ and_dcpl_7) & mux_tmp_2; + assign nor_37_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23])) + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign and_47_rgt = (~ IsNaN_6U_10U_land_lpi_1_dfm_st_5) & (~ IsNaN_6U_10U_1_land_lpi_1_dfm_5) + & or_17_cse; + assign and_48_rgt = or_17_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_5; + assign and_50_rgt = (~ IsNaN_6U_10U_land_lpi_1_dfm_st_5) & IsNaN_6U_10U_1_land_lpi_1_dfm_5 + & or_17_cse; + assign nor_4_cse = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~ (FpAdd_6U_10U_int_mant_p1_sva_3[23]))); + assign or_17_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + | and_dcpl_7); + assign FpAdd_6U_10U_and_1_rgt = (~ FpAdd_6U_10U_if_3_if_acc_1_itm_5_1) & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign FpAdd_6U_10U_and_2_rgt = FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 & (FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & (~ and_dcpl_7); + assign or_31_nl = nor_7_cse | main_stage_v_2; + assign nor_29_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_15_nl = MUX_s_1_2_2((nor_29_nl), main_stage_v_2, chn_o_rsci_bawt); + assign mux_16_nl = MUX_s_1_2_2((mux_15_nl), (or_31_nl), main_stage_v_3); + assign IsNaN_6U_10U_1_aelse_and_cse = core_wen & (~ and_dcpl_7) & (mux_16_nl); + assign nor_7_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_60_cse = (FpAdd_6U_10U_is_a_greater_oif_equal_tmp & (~ FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1)) + | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1; + assign and_58_rgt = or_17_cse & (~ FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1) & ((~ + FpAdd_6U_10U_is_a_greater_oif_equal_tmp) | FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1); + assign and_60_rgt = or_17_cse & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_4); + assign and_65_m1c = or_17_cse & (~(IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp | IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp)); + assign FpSignedBitsToFloat_6U_10U_1_or_1_rgt = (or_17_cse & (~ IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) + & IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp) | ((~ or_60_cse) & and_65_m1c); + assign FpAdd_6U_10U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[15:10]) == + (chn_b_rsci_d_mxwt[15:10]); + assign IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_a_rsci_d_mxwt[15:10]!=6'b111111)); + assign FpMantRNE_23U_11U_else_carry_sva_mx0w0 = (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[11]) + & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[0]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[1]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[2]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[3]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[4]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[5]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[6]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[7]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[8]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[9]) + | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[10]) | (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[12])); + assign FpMantRNE_23U_11U_else_and_tmp = FpMantRNE_23U_11U_else_carry_sva_mx0w0 + & (FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]==10'b1111111111) & ((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[22]) + | (FpAdd_6U_10U_int_mant_p1_sva_3[23])); + assign IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp = ~((~((chn_b_rsci_d_mxwt[9:0]!=10'b0000000000))) + | (chn_b_rsci_d_mxwt[15:10]!=6'b111111)); + assign nl_FpAdd_6U_10U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[15:10])}) + + conv_u2u_6_7(~ (chn_a_rsci_d_mxwt[15:10])) + 7'b1; + assign FpAdd_6U_10U_is_a_greater_acc_1_nl = nl_FpAdd_6U_10U_is_a_greater_acc_1_nl[6:0]; + assign FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1 = readslicef_7_1_6((FpAdd_6U_10U_is_a_greater_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_qr_lpi_1_dfm_4[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_1_nl = nl_FpAdd_6U_10U_if_3_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_3_if_acc_1_nl)); + assign nl_FpAdd_6U_10U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_6U_10U_o_expo_lpi_1_dfm_10[5:1])}) + + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_1_nl = nl_FpAdd_6U_10U_if_4_if_acc_1_nl[5:0]; + assign FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 = readslicef_6_1_5((FpAdd_6U_10U_if_4_if_acc_1_nl)); + assign FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_4 + | (~ FpAdd_6U_10U_if_4_if_acc_1_itm_5_1); + assign FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_6U_10U_is_inf_lpi_1_dfm_4, + (FpAdd_6U_10U_if_4_FpAdd_6U_10U_if_4_or_1_nl), FpMantRNE_23U_11U_else_and_svs_2); + assign FpAdd_6U_10U_and_tmp = FpAdd_6U_10U_if_4_if_acc_1_itm_5_1 & FpMantRNE_23U_11U_else_and_svs_2; + assign FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c = ~(IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_en_1 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_17_cse; + assign FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_asn_1_mx0w1, + FpAdd_6U_10U_a_int_mant_p1_sva, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_23_2_2(FpAdd_6U_10U_a_int_mant_p1_sva, + FpAdd_6U_10U_addend_larger_asn_1_mx0w1, FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0 = MUX_v_22_2_2((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1[21:0]), + (FpAdd_6U_10U_int_mant_p1_sva_3[22:1]), FpAdd_6U_10U_int_mant_p1_sva_3[23]); + assign FpAdd_6U_10U_int_mant_1_lpi_1_dfm_1 = MUX_v_23_2_2(23'b00000000000000000000000, + FpNormalize_6U_23U_else_lshift_itm, FpNormalize_6U_23U_oelse_not_3); + assign nl_FpNormalize_6U_23U_acc_nl = ({1'b1 , (~ FpAdd_6U_10U_qr_lpi_1_dfm_4)}) + + conv_u2s_5_7(libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1) + + 7'b1; + assign FpNormalize_6U_23U_acc_nl = nl_FpNormalize_6U_23U_acc_nl[6:0]; + assign FpNormalize_6U_23U_oelse_not_3 = ((FpAdd_6U_10U_int_mant_p1_sva_3[22:0]!=23'b00000000000000000000000)) + & (readslicef_7_1_6((FpNormalize_6U_23U_acc_nl))); + assign nor_tmp_1 = chn_b_rsci_bawt & chn_a_rsci_bawt; + assign or_1_nl = nor_7_cse | nor_tmp_1; + assign nor_45_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_1)); + assign mux_nl = MUX_s_1_2_2((nor_45_nl), nor_tmp_1, chn_o_rsci_bawt); + assign mux_tmp_1 = MUX_s_1_2_2((mux_nl), (or_1_nl), main_stage_v_1); + assign or_3_nl = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | main_stage_v_2; + assign nor_44_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2))); + assign mux_tmp_2 = MUX_s_1_2_2((nor_44_nl), (or_3_nl), main_stage_v_1); + assign or_tmp_11 = main_stage_v_2 | (~ or_17_cse); + assign and_tmp = main_stage_v_2 & or_17_cse; + assign or_tmp_22 = IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_5; + assign nor_33_nl = ~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) | (~ or_17_cse)); + assign mux_9_nl = MUX_s_1_2_2((nor_33_nl), or_17_cse, FpAdd_6U_10U_if_3_if_acc_1_itm_5_1); + assign nor_32_nl = ~(or_tmp_22 | (~ (mux_9_nl))); + assign mux_tmp_10 = MUX_s_1_2_2((nor_32_nl), or_17_cse, FpMantRNE_23U_11U_else_and_tmp); + assign nor_30_nl = ~(FpAdd_6U_10U_if_3_if_acc_1_itm_5_1 | (~((FpAdd_6U_10U_int_mant_p1_sva_3[23]) + & or_17_cse))); + assign mux_8_nl = MUX_s_1_2_2((nor_30_nl), or_17_cse, or_tmp_22); + assign or_25_nl = FpMantRNE_23U_11U_else_and_tmp | (~ (mux_8_nl)); + assign mux_11_nl = MUX_s_1_2_2(mux_tmp_10, (or_25_nl), main_stage_v_3); + assign nor_31_nl = ~((~ main_stage_v_3) | (~ reg_chn_o_rsci_ld_core_psct_cse) | + chn_o_rsci_bawt); + assign mux_tmp_12 = MUX_s_1_2_2((nor_31_nl), (mux_11_nl), main_stage_v_2); + assign and_tmp_3 = main_stage_v_2 & or_tmp_22; + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_17_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign or_tmp_46 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_52 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_17_cse & (fsm_output[1]); + assign chn_o_rsci_d_9_0_mx0c1 = or_17_cse & main_stage_v_3 & (~ IsNaN_6U_10U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_a_rsci_bawt & chn_b_rsci_bawt)) & or_17_cse + & main_stage_v_1; + assign main_stage_v_2_mx0c1 = or_17_cse & main_stage_v_2 & (~ main_stage_v_1); + assign main_stage_v_3_mx0c1 = or_17_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[9:0])}) + + conv_u2u_10_11(~ (chn_b_rsci_d_mxwt[9:0])) + 11'b1; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl[10:0]; + assign FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 = readslicef_11_1_10((FpAdd_6U_10U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_52; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + assign FpAdd_6U_10U_a_right_shift_qelse_and_tmp = (fsm_output[1]) & (~((~(FpAdd_6U_10U_is_a_greater_oif_aelse_acc_itm_10_1 + | (~ FpAdd_6U_10U_is_a_greater_oif_equal_tmp))) | FpAdd_6U_10U_is_a_greater_acc_1_itm_6_1)); + assign FpAdd_6U_10U_if_2_and_tmp = (fsm_output[1]) & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_a_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_46 ) begin + reg_chn_a_rsci_ld_core_psct_cse <= or_tmp_46; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_17_cse & main_stage_v_3 & IsNaN_6U_10U_land_lpi_1_dfm_6) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3, + (FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl), FpMantRNE_23U_11U_else_o_mant_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_15_10 <= 6'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_15_10 <= MUX1HOT_v_6_4_2(FpAdd_6U_10U_o_expo_lpi_1_dfm_10, (FpAdd_6U_10U_if_4_if_acc_nl), + 6'b111110, FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4, + {(FpAdd_6U_10U_and_nl) , (FpAdd_6U_10U_and_3_nl) , (FpAdd_6U_10U_and_7_nl) + , FpAdd_6U_10U_or_cse}); + chn_o_rsci_d_16 <= FpAdd_6U_10U_mux_13_itm_6; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_52 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= 1'b0; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse + <= 1'b0; + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= 1'b0; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= 1'b0; + b_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= 7'b0; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= 1'b0; + FpAdd_6U_10U_a_sva_1_15_0_1 <= 16'b0; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= 7'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_aelse_and_cse ) begin + IsNaN_6U_10U_land_lpi_1_dfm_st_4 <= IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp; + reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse + <= (chn_a_rsci_d_mxwt[16]) ^ (chn_b_rsci_d_mxwt[16]); + FpAdd_6U_10U_is_a_greater_lor_lpi_1_dfm_3 <= or_60_cse; + FpAdd_6U_10U_IsZero_6U_10U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[15:0]!=16'b0000000000000000); + b_sva_1_15_0_1 <= chn_b_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_b_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_b_left_shift_acc_itm_2[6:0]; + FpAdd_6U_10U_IsZero_6U_10U_or_itm_2 <= (chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000); + FpAdd_6U_10U_a_sva_1_15_0_1 <= chn_a_rsci_d_mxwt[15:0]; + FpAdd_6U_10U_a_left_shift_acc_itm_2 <= nl_FpAdd_6U_10U_a_left_shift_acc_itm_2[6:0]; + IsNaN_6U_10U_1_land_lpi_1_dfm_4 <= IsNaN_6U_10U_1_IsNaN_6U_10U_1_nor_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_17_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) + begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= 6'b0; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= 1'b0; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_5 <= 1'b0; + end + else if ( FpAdd_6U_10U_and_8_cse ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_4 <= FpAdd_6U_10U_qr_lpi_1_dfm_3; + IsNaN_6U_10U_land_lpi_1_dfm_st_5 <= IsNaN_6U_10U_land_lpi_1_dfm_st_4; + IsNaN_6U_10U_1_land_lpi_1_dfm_5 <= IsNaN_6U_10U_1_land_lpi_1_dfm_4; + FpAdd_6U_10U_mux_13_itm_5 <= FpAdd_6U_10U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= 24'b0; + end + else if ( core_wen & (~((~(or_17_cse & (~ reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse))) + & (~(or_17_cse & reg_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_FpAdd_6U_10U_is_addition_xor_svs_st_1_cse)))) + & mux_tmp_2 ) begin + FpAdd_6U_10U_int_mant_p1_sva_3 <= readslicef_25_24_1((acc_1_nl)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & (and_tmp | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3 <= + 10'b0; + end + else if ( core_wen & (and_47_rgt | and_48_rgt | and_50_rgt) & (mux_6_nl) ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3 <= + MUX1HOT_v_10_3_2((FpAdd_6U_10U_int_mant_1_lpi_1_dfm_2_21_0_mx0[21:12]), + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2, + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2, + {and_47_rgt , and_48_rgt , and_50_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_7_nl) ) begin + FpMantRNE_23U_11U_else_carry_sva_2 <= FpMantRNE_23U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= 6'b0; + end + else if ( core_wen & (FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt | FpAdd_6U_10U_and_1_rgt + | FpAdd_6U_10U_and_2_rgt) & (mux_14_nl) ) begin + FpAdd_6U_10U_o_expo_lpi_1_dfm_10 <= MUX1HOT_v_6_3_2((FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl), + FpAdd_6U_10U_qr_lpi_1_dfm_4, (FpAdd_6U_10U_if_3_if_acc_nl), {FpAdd_6U_10U_o_expo_FpAdd_6U_10U_o_expo_nor_rgt + , FpAdd_6U_10U_and_1_rgt , FpAdd_6U_10U_and_2_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= 1'b0; + FpAdd_6U_10U_mux_13_itm_6 <= 1'b0; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= 1'b0; + FpMantRNE_23U_11U_else_and_svs_2 <= 1'b0; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= 1'b0; + end + else if ( IsNaN_6U_10U_1_aelse_and_cse ) begin + IsNaN_6U_10U_1_land_lpi_1_dfm_6 <= IsNaN_6U_10U_1_land_lpi_1_dfm_5; + FpAdd_6U_10U_mux_13_itm_6 <= FpAdd_6U_10U_mux_13_itm_5; + IsNaN_6U_10U_land_lpi_1_dfm_6 <= IsNaN_6U_10U_land_lpi_1_dfm_st_5; + FpMantRNE_23U_11U_else_and_svs_2 <= FpMantRNE_23U_11U_else_and_tmp; + FpAdd_6U_10U_is_inf_lpi_1_dfm_4 <= nor_4_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= 6'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_18_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_4 + <= FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2 <= + 10'b0; + end + else if ( core_wen & ((and_tmp & (~(IsNaN_6U_10U_land_lpi_1_dfm_st_5 | IsNaN_6U_10U_1_land_lpi_1_dfm_4))) + | (or_17_cse & IsNaN_6U_10U_1_land_lpi_1_dfm_4)) & (mux_23_nl) ) begin + FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_2 <= + b_sva_1_15_0_1[9:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= 6'b0; + end + else if ( core_wen & ((or_60_cse & or_17_cse) | and_58_rgt) & mux_tmp_1 ) begin + FpAdd_6U_10U_qr_lpi_1_dfm_3 <= MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), (chn_b_rsci_d_mxwt[15:10]), + and_58_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= 6'b0; + end + else if ( core_wen & ((or_17_cse & IsNaN_6U_10U_land_lpi_1_dfm_st_4) | and_60_rgt) + & (mux_29_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_15_10_itm_3 + <= MUX_v_6_2_2((FpAdd_6U_10U_a_sva_1_15_0_1[15:10]), (b_sva_1_15_0_1[15:10]), + and_60_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2 + <= 10'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_30_nl) ) begin + FpSignedBitsToFloat_6U_10U_1_slc_FpSignedBitsToFloat_6U_10U_1_ubits_9_0_itm_2 + <= FpAdd_6U_10U_a_sva_1_15_0_1[9:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_6U_10U_mux_13_itm_4 <= 1'b0; + end + else if ( core_wen & ((or_17_cse & IsNaN_6U_10U_IsNaN_6U_10U_nor_tmp) | (or_60_cse + & and_65_m1c) | FpSignedBitsToFloat_6U_10U_1_or_1_rgt) & mux_tmp_1 ) begin + FpAdd_6U_10U_mux_13_itm_4 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[16]), (~ (chn_b_rsci_d_mxwt[16])), + FpSignedBitsToFloat_6U_10U_1_or_1_rgt); + end + end + assign nl_FpMantRNE_23U_11U_else_acc_nl = FpMantRNE_23U_11U_else_o_mant_slc_FpMantRNE_23U_11U_i_data_22_12_2_itm_3 + + conv_u2u_1_10(FpMantRNE_23U_11U_else_carry_sva_2); + assign FpMantRNE_23U_11U_else_acc_nl = nl_FpMantRNE_23U_11U_else_acc_nl[9:0]; + assign FpAdd_6U_10U_FpAdd_6U_10U_or_2_nl = MUX_v_10_2_2((FpMantRNE_23U_11U_else_acc_nl), + 10'b1111111111, FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0); + assign FpMantRNE_23U_11U_else_o_mant_and_nl = (~ IsNaN_6U_10U_1_land_lpi_1_dfm_6) + & chn_o_rsci_d_9_0_mx0c1; + assign nl_FpAdd_6U_10U_if_4_if_acc_nl = FpAdd_6U_10U_o_expo_lpi_1_dfm_10 + 6'b1; + assign FpAdd_6U_10U_if_4_if_acc_nl = nl_FpAdd_6U_10U_if_4_if_acc_nl[5:0]; + assign FpAdd_6U_10U_and_nl = (~(FpAdd_6U_10U_and_tmp | FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_3_nl = FpAdd_6U_10U_and_tmp & (~ FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_and_7_nl = FpAdd_6U_10U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_6U_10U_FpAdd_6U_10U_nor_2_m1c; + assign FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, or_60_cse)); + assign nl_FpAdd_6U_10U_b_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_b_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_is_a_greater_oelse_not_5_nl = ~ or_60_cse; + assign FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl = ~(MUX_v_6_2_2(6'b000000, + z_out, (FpAdd_6U_10U_is_a_greater_oelse_not_5_nl))); + assign nl_FpAdd_6U_10U_a_left_shift_acc_itm_2 = ({1'b1 , (FpAdd_6U_10U_a_left_shift_FpAdd_6U_10U_a_right_shift_nand_nl)}) + + 7'b1101; + assign FpAdd_6U_10U_else_2_mux_2_nl = MUX_v_23_2_2((~ FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0), + FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign FpAdd_6U_10U_else_2_mux_3_nl = MUX_v_23_2_2(FpAdd_6U_10U_addend_larger_qr_lpi_1_dfm_mx0, + FpAdd_6U_10U_addend_smaller_qr_lpi_1_dfm_mx0, FpAdd_6U_10U_if_2_and_tmp); + assign nl_acc_1_nl = ({(~ FpAdd_6U_10U_if_2_and_tmp) , (FpAdd_6U_10U_else_2_mux_2_nl) + , (~ FpAdd_6U_10U_if_2_and_tmp)}) + conv_u2u_24_25({(FpAdd_6U_10U_else_2_mux_3_nl) + , 1'b1}); + assign acc_1_nl = nl_acc_1_nl[24:0]; + assign mux_3_nl = MUX_s_1_2_2(or_tmp_11, (~ or_17_cse), nor_37_cse); + assign mux_4_nl = MUX_s_1_2_2((mux_3_nl), or_tmp_11, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign nor_38_nl = ~(nor_37_cse | (~ and_tmp)); + assign mux_5_nl = MUX_s_1_2_2((nor_38_nl), and_tmp, IsNaN_6U_10U_land_lpi_1_dfm_st_5); + assign and_91_nl = ((~ FpAdd_6U_10U_is_inf_lpi_1_dfm_4) | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | IsNaN_6U_10U_land_lpi_1_dfm_6) & main_stage_v_3; + assign mux_6_nl = MUX_s_1_2_2((mux_5_nl), (mux_4_nl), and_91_nl); + assign nor_34_nl = ~(nor_4_cse | (~ main_stage_v_2) | IsNaN_6U_10U_land_lpi_1_dfm_st_5 + | IsNaN_6U_10U_1_land_lpi_1_dfm_5); + assign nor_35_nl = ~((~ main_stage_v_3) | IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4); + assign mux_7_nl = MUX_s_1_2_2((nor_35_nl), (nor_34_nl), or_17_cse); + assign nl_FpNormalize_6U_23U_else_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + ({1'b1 + , (~ libraries_leading_sign_23_0_b9d2f049d7a95593b985a5e76dea79445444_1)}) + + 6'b1; + assign FpNormalize_6U_23U_else_acc_nl = nl_FpNormalize_6U_23U_else_acc_nl[5:0]; + assign FpNormalize_6U_23U_FpNormalize_6U_23U_and_nl = MUX_v_6_2_2(6'b000000, (FpNormalize_6U_23U_else_acc_nl), + FpNormalize_6U_23U_oelse_not_3); + assign nl_FpAdd_6U_10U_if_3_if_acc_nl = FpAdd_6U_10U_qr_lpi_1_dfm_4 + 6'b1; + assign FpAdd_6U_10U_if_3_if_acc_nl = nl_FpAdd_6U_10U_if_3_if_acc_nl[5:0]; + assign and_12_nl = main_stage_v_2 & mux_tmp_10; + assign or_30_nl = IsNaN_6U_10U_land_lpi_1_dfm_6 | IsNaN_6U_10U_1_land_lpi_1_dfm_6 + | FpAdd_6U_10U_is_inf_lpi_1_dfm_4; + assign mux_13_nl = MUX_s_1_2_2(mux_tmp_12, (and_12_nl), or_30_nl); + assign mux_14_nl = MUX_s_1_2_2((mux_13_nl), mux_tmp_12, FpMantRNE_23U_11U_else_and_svs_2); + assign or_35_nl = nor_7_cse | and_tmp_3; + assign nor_28_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ and_tmp_3)); + assign mux_17_nl = MUX_s_1_2_2((nor_28_nl), and_tmp_3, chn_o_rsci_bawt); + assign and_90_nl = FpAdd_6U_10U_or_cse & main_stage_v_3; + assign mux_18_nl = MUX_s_1_2_2((mux_17_nl), (or_35_nl), and_90_nl); + assign nor_53_nl = ~((~ IsNaN_6U_10U_1_land_lpi_1_dfm_4) | (~ main_stage_v_1) | + IsNaN_6U_10U_land_lpi_1_dfm_st_4); + assign and_99_nl = IsNaN_6U_10U_1_land_lpi_1_dfm_5 & (~ IsNaN_6U_10U_land_lpi_1_dfm_st_5) + & main_stage_v_2; + assign mux_23_nl = MUX_s_1_2_2((and_99_nl), (nor_53_nl), or_17_cse); + assign or_73_nl = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse) | and_tmp_3; + assign nor_24_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2 + & or_tmp_22))); + assign and_89_nl = (IsNaN_6U_10U_land_lpi_1_dfm_st_4 | IsNaN_6U_10U_1_land_lpi_1_dfm_4) + & main_stage_v_1; + assign mux_29_nl = MUX_s_1_2_2((nor_24_nl), (or_73_nl), and_89_nl); + assign nand_1_nl = ~(nor_7_cse & (~(main_stage_v_2 & IsNaN_6U_10U_land_lpi_1_dfm_st_5))); + assign nor_23_nl = ~(chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_2 + & IsNaN_6U_10U_land_lpi_1_dfm_st_5))); + assign and_88_nl = IsNaN_6U_10U_land_lpi_1_dfm_st_4 & main_stage_v_1; + assign mux_30_nl = MUX_s_1_2_2((nor_23_nl), (nand_1_nl), and_88_nl); + assign FpAdd_6U_10U_b_right_shift_qif_mux_2_nl = MUX_v_6_2_2((chn_a_rsci_d_mxwt[15:10]), + (chn_b_rsci_d_mxwt[15:10]), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign FpAdd_6U_10U_b_right_shift_qif_mux_3_nl = MUX_v_6_2_2((~ (chn_b_rsci_d_mxwt[15:10])), + (~ (chn_a_rsci_d_mxwt[15:10])), FpAdd_6U_10U_a_right_shift_qelse_and_tmp); + assign nl_acc_nl = ({(FpAdd_6U_10U_b_right_shift_qif_mux_2_nl) , 1'b1}) + ({(FpAdd_6U_10U_b_right_shift_qif_mux_3_nl) + , 1'b1}); + assign acc_nl = nl_acc_nl[6:0]; + assign z_out = readslicef_7_6_1((acc_nl)); + function [9:0] MUX1HOT_v_10_3_2; + input [9:0] input_2; + input [9:0] input_1; + input [9:0] input_0; + input [2:0] sel; + reg [9:0] result; + begin + result = input_0 & {10{sel[0]}}; + result = result | ( input_1 & {10{sel[1]}}); + result = result | ( input_2 & {10{sel[2]}}); + MUX1HOT_v_10_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_3_2; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [2:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + MUX1HOT_v_6_3_2 = result; + end + endfunction + function [5:0] MUX1HOT_v_6_4_2; + input [5:0] input_3; + input [5:0] input_2; + input [5:0] input_1; + input [5:0] input_0; + input [3:0] sel; + reg [5:0] result; + begin + result = input_0 & {6{sel[0]}}; + result = result | ( input_1 & {6{sel[1]}}); + result = result | ( input_2 & {6{sel[2]}}); + result = result | ( input_3 & {6{sel[3]}}); + MUX1HOT_v_6_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [21:0] MUX_v_22_2_2; + input [21:0] input_0; + input [21:0] input_1; + input [0:0] sel; + reg [21:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_22_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [5:0] MUX_v_6_2_2; + input [5:0] input_0; + input [5:0] input_1; + input [0:0] sel; + reg [5:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_6_2_2 = result; + end + endfunction + function [0:0] readslicef_11_1_10; + input [10:0] vector; + reg [10:0] tmp; + begin + tmp = vector >> 10; + readslicef_11_1_10 = tmp[0:0]; + end + endfunction + function [23:0] readslicef_25_24_1; + input [24:0] vector; + reg [24:0] tmp; + begin + tmp = vector >> 1; + readslicef_25_24_1 = tmp[23:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [5:0] readslicef_7_6_1; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 1; + readslicef_7_6_1 = tmp[5:0]; + end + endfunction + function [6:0] conv_u2s_5_7 ; + input [4:0] vector ; + begin + conv_u2s_5_7 = {{2{1'b0}}, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [6:0] conv_u2u_6_7 ; + input [5:0] vector ; + begin + conv_u2u_6_7 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_10_11 ; + input [9:0] vector ; + begin + conv_u2u_10_11 = {1'b0, vector}; + end + endfunction + function [24:0] conv_u2u_24_25 ; + input [23:0] vector ; + begin + conv_u2u_24_25 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_sub +// ------------------------------------------------------------------ +module HLS_fp17_sub ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [16:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP17_SUB_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP17_SUB_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP17_SUB_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_sub_core HLS_fp17_sub_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp16.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp16.v new file mode 100644 index 0000000..3c4ddea --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp16.v @@ -0,0 +1,1201 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_to_fp16.v +module FP17_TO_FP16_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_TO_FP16_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_TO_FP16_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_r_beh_v4.v +module FP17_TO_FP16_mgc_shift_r_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshr_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshr_u(a,s,1'b0); + end + endgenerate +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP17_TO_FP16_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP17_TO_FP16_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:08:09 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP16_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP16_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP16_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP16_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_to_fp16_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_to_fp16_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [15:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP16_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd16)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP16_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_15; + reg chn_o_rsci_d_14; + reg [3:0] chn_o_rsci_d_13_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire mux_tmp; + wire and_tmp_1; + wire or_tmp_7; + wire or_tmp_8; + wire and_dcpl_6; + wire and_dcpl_8; + wire and_dcpl_11; + wire and_dcpl_14; + wire or_tmp_19; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs; + reg main_stage_v_1; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2; + reg [2:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2; + wire [3:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2; + reg IsNaN_6U_10U_nor_itm_2; + reg IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1; + reg [14:0] FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1; + wire and_6_mdf; + wire chn_o_and_1_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire nor_5_cse; + wire or_cse; + wire and_35_rgt; + wire and_37_rgt; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_itm; + wire mux_1_itm; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva; + wire [11:0] nl_FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva; + wire [9:0] FpMantDecShiftRight_10U_6U_10U_guard_bits_9_0_sva; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_guard_mask_sva; + wire [9:0] FpMantDecShiftRight_10U_6U_10U_stick_bits_9_0_sva; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_stick_mask_sva; + wire [11:0] nl_FpMantDecShiftRight_10U_6U_10U_stick_mask_sva; + wire [9:0] FpMantDecShiftRight_10U_6U_10U_least_bits_9_0_sva; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_least_mask_sva; + wire Fp17ToFp16_and_cse; + wire FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1; + wire FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + wire FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] shift_0_prb; + wire[0:0] and_9; + wire[9:0] FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl; + wire[9:0] FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl; + wire[9:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_nl; + wire[0:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_16_nl; + wire[3:0] FpExpoWidthDec_6U_5U_10U_1U_1U_mux_6_nl; + wire[3:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_FpExpoWidthDec_6U_5U_10U_1U_1U_else_and_2_nl; + wire[3:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_6_nl; + wire[0:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_15_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_7_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_6_nl; + wire[0:0] or_3_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_nl; + wire[0:0] mux_4_nl; + wire[0:0] or_10_nl; + wire[0:0] mux_6_nl; + wire[0:0] and_60_nl; + wire[6:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl; + wire[7:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl; + wire[5:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl; + wire[6:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl; + wire[6:0] FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl; + wire[7:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl; + wire[0:0] FpMantDecShiftRight_10U_6U_10U_carry_and_nl; + wire[0:0] or_2_nl; +// Interconnect Declarations for Component Instantiations + wire [10:0] nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_a; + assign nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_a = {1'b1 , (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0])}; + wire [3:0] nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_s; + assign nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_s = {FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + , (~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10]))}; + wire [5:0] nl_FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg_s = conv_u2s_4_5({FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + , (~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10]))}) + 5'b11111; + wire [3:0] nl_FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg_s = {FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + , (~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10]))}; + wire [15:0] nl_HLS_fp17_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_15 + , chn_o_rsci_d_14 , chn_o_rsci_d_13_10 , chn_o_rsci_d_9_0}; + FP17_TO_FP16_mgc_shift_r_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd11)) FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg ( + .a(nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_a[10:0]), + .s(nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_s[3:0]), + .z(FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_itm) + ); + FP17_TO_FP16_mgc_shift_bl_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd11)) FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg_s[4:0]), + .z(FpMantDecShiftRight_10U_6U_10U_guard_mask_sva) + ); + FP17_TO_FP16_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd11)) FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg_s[3:0]), + .z(FpMantDecShiftRight_10U_6U_10U_least_mask_sva) + ); + HLS_fp17_to_fp16_core_chn_a_rsci HLS_fp17_to_fp16_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_to_fp16_core_chn_o_rsci HLS_fp17_to_fp16_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d[15:0]) + ); + HLS_fp17_to_fp16_core_staller HLS_fp17_to_fp16_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_to_fp16_core_core_fsm HLS_fp17_to_fp16_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iExpoWidth_oExpoWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, and_6_mdf & (fsm_output[1]))), fsm_output[1]); +// assert(iExpoWidth > oExpoWidth) - ../include/nvdla_float.h: line 630 +// PSL HLS_fp17_to_fp16_core_nvdla_float_h_ln630_assert_iExpoWidth_gt_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign and_9 = or_cse & FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2 + & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2) + & main_stage_v_1 & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2); + assign shift_0_prb = MUX1HOT_s_1_1_2(readslicef_5_1_4((({1'b1 , (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2) + , (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10])}) + 5'b1)), and_9); +// assert(shift > 0) - ../include/nvdla_float.h: line 340 +// PSL HLS_fp17_to_fp16_core_nvdla_float_h_ln340_assert_shift_gt_0 : assert { shift_0_prb } @rose(nvdla_core_clk); + assign nor_5_cse = ~(IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 | IsNaN_6U_10U_nor_itm_2); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_8 | (~ main_stage_v_1))); + assign Fp17ToFp16_and_cse = core_wen & (~ and_dcpl_8) & mux_tmp; + assign and_35_rgt = or_cse & ((~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) | + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1); + assign and_37_rgt = or_cse & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl = ({1'b1 , (~ (chn_a_rsci_d_mxwt[15:10]))}) + + 7'b10001; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl = nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl[6:0]; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1 = readslicef_7_1_6((FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl)); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl = conv_u2u_5_6(chn_a_rsci_d_mxwt[15:11]) + + 6'b111101; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl = nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl[5:0]; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 = readslicef_6_1_5((FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl)); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl = conv_u2s_6_7(chn_a_rsci_d_mxwt[15:10]) + + 7'b1010001; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl = nl_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl[6:0]; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 = readslicef_7_1_6((FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl)); + assign FpMantDecShiftRight_10U_6U_10U_carry_and_nl = ((FpMantDecShiftRight_10U_6U_10U_guard_bits_9_0_sva!=10'b0000000000) + | (FpMantDecShiftRight_10U_6U_10U_guard_mask_sva[10])) & ((FpMantDecShiftRight_10U_6U_10U_stick_bits_9_0_sva!=10'b0000000000) + | (FpMantDecShiftRight_10U_6U_10U_stick_mask_sva[10]) | (FpMantDecShiftRight_10U_6U_10U_least_bits_9_0_sva!=10'b0000000000) + | (FpMantDecShiftRight_10U_6U_10U_least_mask_sva[10])); + assign nl_FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva = FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_itm + + conv_u2u_1_11(FpMantDecShiftRight_10U_6U_10U_carry_and_nl); + assign FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva = nl_FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva[10:0]; + assign FpMantDecShiftRight_10U_6U_10U_guard_bits_9_0_sva = (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]) + & (FpMantDecShiftRight_10U_6U_10U_guard_mask_sva[9:0]); + assign FpMantDecShiftRight_10U_6U_10U_stick_bits_9_0_sva = (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]) + & (FpMantDecShiftRight_10U_6U_10U_stick_mask_sva[9:0]); + assign nl_FpMantDecShiftRight_10U_6U_10U_stick_mask_sva = FpMantDecShiftRight_10U_6U_10U_guard_mask_sva + + 11'b11111111111; + assign FpMantDecShiftRight_10U_6U_10U_stick_mask_sva = nl_FpMantDecShiftRight_10U_6U_10U_stick_mask_sva[10:0]; + assign FpMantDecShiftRight_10U_6U_10U_least_bits_9_0_sva = (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]) + & (FpMantDecShiftRight_10U_6U_10U_least_mask_sva[9:0]); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_6_mdf = chn_a_rsci_bawt & or_cse; + assign or_2_nl = chn_a_rsci_bawt | (~ or_cse); + assign mux_tmp = MUX_s_1_2_2(and_6_mdf, (or_2_nl), main_stage_v_1); + assign and_tmp_1 = FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 & chn_a_rsci_bawt + & or_cse; + assign or_tmp_7 = (~ FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2) + | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign or_tmp_8 = ~((~(FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 & chn_a_rsci_bawt)) + & or_cse); + assign mux_1_itm = MUX_s_1_2_2(and_tmp_1, or_tmp_8, FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2); + assign and_dcpl_6 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_8 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_11 = or_cse & main_stage_v_1; + assign and_dcpl_14 = and_dcpl_6 & (~ main_stage_v_1); + assign or_tmp_19 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_6_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = and_dcpl_11 & (IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 + | IsNaN_6U_10U_nor_itm_2); + assign main_stage_v_1_mx0c1 = or_cse & (~ chn_a_rsci_bawt) & main_stage_v_1; + assign chn_a_rsci_oswt_unreg = or_tmp_19; + assign chn_o_rsci_oswt_unreg = and_dcpl_6; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_6_mdf) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_11; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((and_dcpl_11 & nor_5_cse) | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]), + (FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl), + chn_o_rsci_d_9_0_mx0c1); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_13_10 <= 4'b0; + chn_o_rsci_d_14 <= 1'b0; + chn_o_rsci_d_15 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_13_10 <= MUX_v_4_2_2((FpExpoWidthDec_6U_5U_10U_1U_1U_mux_6_nl), + 4'b1111, nor_5_cse); + chn_o_rsci_d_14 <= ((~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[14])) + & FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2 + & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2)) + | (~ FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2) + | nor_5_cse; + chn_o_rsci_d_15 <= FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_11 | and_dcpl_14) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_14; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_19 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1 <= 15'b0; + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1 <= 1'b0; + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2 + <= 1'b0; + IsNaN_6U_10U_nor_itm_2 <= 1'b0; + IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 <= 1'b0; + end + else if ( Fp17ToFp16_and_cse ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1 <= chn_a_rsci_d_mxwt[14:0]; + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1 <= chn_a_rsci_d_mxwt[16]; + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2 + <= FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1; + IsNaN_6U_10U_nor_itm_2 <= ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 <= ~((chn_a_rsci_d_mxwt[15:10]==6'b111111)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 <= 3'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_3_nl) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 <= nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2[2:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_5_nl) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2 + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2 + <= 1'b0; + end + else if ( core_wen & ((or_cse & FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 & + (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1)) | and_35_rgt) & mux_tmp + ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2 + <= MUX_s_1_2_2(FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1, FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs, + and_35_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2 + <= 1'b0; + end + else if ( core_wen & ((or_cse & FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) | + and_37_rgt) & mux_tmp ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2 + <= MUX_s_1_2_2(FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1, FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs, + and_37_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_6_nl) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2 + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs + <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_8 | (~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) + | (~ chn_a_rsci_bawt) | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 + | (fsm_output[0]))) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs + <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_8 | (~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) + | (~ chn_a_rsci_bawt) | (fsm_output[0]))) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + end + end + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_nl = MUX_v_10_2_2((FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva[9:0]), + (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]), FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_16_nl = ~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl = ~(MUX_v_10_2_2(10'b0000000000, + (FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_nl), (FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_16_nl))); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl + = ~(MUX_v_10_2_2(10'b0000000000, (FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl), + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2)); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_6_nl = MUX_v_4_2_2(({3'b0 , + (FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva[10])}), (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[13:10]), + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_15_nl = ~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_FpExpoWidthDec_6U_5U_10U_1U_1U_else_and_2_nl + = MUX_v_4_2_2(4'b0000, (FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_6_nl), + (FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_15_nl)); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_mux_6_nl = MUX_v_4_2_2(4'b1110, (FpExpoWidthDec_6U_5U_10U_1U_1U_else_FpExpoWidthDec_6U_5U_10U_1U_1U_else_and_2_nl), + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + = (~ (chn_a_rsci_d_mxwt[13:11])) + 3'b1; + assign nor_7_nl = ~(FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1 | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 + | (~ and_tmp_1)); + assign or_6_nl = FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1 | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + assign mux_2_nl = MUX_s_1_2_2(mux_1_itm, (~ or_tmp_7), or_6_nl); + assign or_3_nl = FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2 + | (~ main_stage_v_1) | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2; + assign mux_3_nl = MUX_s_1_2_2((mux_2_nl), (nor_7_nl), or_3_nl); + assign nor_nl = ~(FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 | (~ and_tmp_1)); + assign mux_4_nl = MUX_s_1_2_2(mux_1_itm, (~ or_tmp_7), FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1); + assign or_10_nl = (~ main_stage_v_1) | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2; + assign mux_5_nl = MUX_s_1_2_2((mux_4_nl), (nor_nl), or_10_nl); + assign and_60_nl = main_stage_v_1 & FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2; + assign mux_6_nl = MUX_s_1_2_2(and_tmp_1, or_tmp_8, and_60_nl); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [4:0] conv_u2s_4_5 ; + input [3:0] vector ; + begin + conv_u2s_4_5 = {1'b0, vector}; + end + endfunction + function [6:0] conv_u2s_6_7 ; + input [5:0] vector ; + begin + conv_u2s_6_7 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [5:0] conv_u2u_5_6 ; + input [4:0] vector ; + begin + conv_u2u_5_6 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16 +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP16_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP17_TO_FP16_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_to_fp16_core HLS_fp17_to_fp16_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp16.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp16.v.vcp new file mode 100644 index 0000000..3c4ddea --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp16.v.vcp @@ -0,0 +1,1201 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_to_fp16.v +module FP17_TO_FP16_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_TO_FP16_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_TO_FP16_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_r_beh_v4.v +module FP17_TO_FP16_mgc_shift_r_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshr_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshr_u(a,s,1'b0); + end + endgenerate +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP17_TO_FP16_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP17_TO_FP16_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:08:09 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP16_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP16_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP16_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP16_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_to_fp16_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_to_fp16_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [15:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP16_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd16)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_to_fp16_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP16_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_to_fp16_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16_core +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_15; + reg chn_o_rsci_d_14; + reg [3:0] chn_o_rsci_d_13_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire mux_tmp; + wire and_tmp_1; + wire or_tmp_7; + wire or_tmp_8; + wire and_dcpl_6; + wire and_dcpl_8; + wire and_dcpl_11; + wire and_dcpl_14; + wire or_tmp_19; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs; + reg main_stage_v_1; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2; + reg [2:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2; + wire [3:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2; + reg IsNaN_6U_10U_nor_itm_2; + reg IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2; + reg FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1; + reg [14:0] FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1; + wire and_6_mdf; + wire chn_o_and_1_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire nor_5_cse; + wire or_cse; + wire and_35_rgt; + wire and_37_rgt; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_itm; + wire mux_1_itm; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva; + wire [11:0] nl_FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva; + wire [9:0] FpMantDecShiftRight_10U_6U_10U_guard_bits_9_0_sva; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_guard_mask_sva; + wire [9:0] FpMantDecShiftRight_10U_6U_10U_stick_bits_9_0_sva; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_stick_mask_sva; + wire [11:0] nl_FpMantDecShiftRight_10U_6U_10U_stick_mask_sva; + wire [9:0] FpMantDecShiftRight_10U_6U_10U_least_bits_9_0_sva; + wire [10:0] FpMantDecShiftRight_10U_6U_10U_least_mask_sva; + wire Fp17ToFp16_and_cse; + wire FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1; + wire FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + wire FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] shift_0_prb; + wire[0:0] and_9; + wire[9:0] FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl; + wire[9:0] FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl; + wire[9:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_nl; + wire[0:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_16_nl; + wire[3:0] FpExpoWidthDec_6U_5U_10U_1U_1U_mux_6_nl; + wire[3:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_FpExpoWidthDec_6U_5U_10U_1U_1U_else_and_2_nl; + wire[3:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_6_nl; + wire[0:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_15_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_7_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_6_nl; + wire[0:0] or_3_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_nl; + wire[0:0] mux_4_nl; + wire[0:0] or_10_nl; + wire[0:0] mux_6_nl; + wire[0:0] and_60_nl; + wire[6:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl; + wire[7:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl; + wire[5:0] FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl; + wire[6:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl; + wire[6:0] FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl; + wire[7:0] nl_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl; + wire[0:0] FpMantDecShiftRight_10U_6U_10U_carry_and_nl; + wire[0:0] or_2_nl; +// Interconnect Declarations for Component Instantiations + wire [10:0] nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_a; + assign nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_a = {1'b1 , (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0])}; + wire [3:0] nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_s; + assign nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_s = {FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + , (~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10]))}; + wire [5:0] nl_FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg_s = conv_u2s_4_5({FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + , (~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10]))}) + 5'b11111; + wire [3:0] nl_FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg_s = {FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + , (~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10]))}; + wire [15:0] nl_HLS_fp17_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_15 + , chn_o_rsci_d_14 , chn_o_rsci_d_13_10 , chn_o_rsci_d_9_0}; + FP17_TO_FP16_mgc_shift_r_v4 #(.width_a(32'sd11), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd11)) FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg ( + .a(nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_a[10:0]), + .s(nl_FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_rg_s[3:0]), + .z(FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_itm) + ); + FP17_TO_FP16_mgc_shift_bl_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd11)) FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_10U_6U_10U_guard_mask_lshift_rg_s[4:0]), + .z(FpMantDecShiftRight_10U_6U_10U_guard_mask_sva) + ); + FP17_TO_FP16_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd11)) FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_10U_6U_10U_least_mask_lshift_rg_s[3:0]), + .z(FpMantDecShiftRight_10U_6U_10U_least_mask_sva) + ); + HLS_fp17_to_fp16_core_chn_a_rsci HLS_fp17_to_fp16_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_to_fp16_core_chn_o_rsci HLS_fp17_to_fp16_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d[15:0]) + ); + HLS_fp17_to_fp16_core_staller HLS_fp17_to_fp16_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_to_fp16_core_core_fsm HLS_fp17_to_fp16_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iExpoWidth_oExpoWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, and_6_mdf & (fsm_output[1]))), fsm_output[1]); +// assert(iExpoWidth > oExpoWidth) - ../include/nvdla_float.h: line 630 +// PSL HLS_fp17_to_fp16_core_nvdla_float_h_ln630_assert_iExpoWidth_gt_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign and_9 = or_cse & FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2 + & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2) + & main_stage_v_1 & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2); + assign shift_0_prb = MUX1HOT_s_1_1_2(readslicef_5_1_4((({1'b1 , (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2) + , (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[10])}) + 5'b1)), and_9); +// assert(shift > 0) - ../include/nvdla_float.h: line 340 +// PSL HLS_fp17_to_fp16_core_nvdla_float_h_ln340_assert_shift_gt_0 : assert { shift_0_prb } @rose(nvdla_core_clk); + assign nor_5_cse = ~(IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 | IsNaN_6U_10U_nor_itm_2); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_8 | (~ main_stage_v_1))); + assign Fp17ToFp16_and_cse = core_wen & (~ and_dcpl_8) & mux_tmp; + assign and_35_rgt = or_cse & ((~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) | + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1); + assign and_37_rgt = or_cse & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl = ({1'b1 , (~ (chn_a_rsci_d_mxwt[15:10]))}) + + 7'b10001; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl = nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl[6:0]; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1 = readslicef_7_1_6((FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_nl)); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl = conv_u2u_5_6(chn_a_rsci_d_mxwt[15:11]) + + 6'b111101; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl = nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl[5:0]; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 = readslicef_6_1_5((FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_nl)); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl = conv_u2s_6_7(chn_a_rsci_d_mxwt[15:10]) + + 7'b1010001; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl = nl_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl[6:0]; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 = readslicef_7_1_6((FpExpoWidthDec_6U_5U_10U_1U_1U_acc_nl)); + assign FpMantDecShiftRight_10U_6U_10U_carry_and_nl = ((FpMantDecShiftRight_10U_6U_10U_guard_bits_9_0_sva!=10'b0000000000) + | (FpMantDecShiftRight_10U_6U_10U_guard_mask_sva[10])) & ((FpMantDecShiftRight_10U_6U_10U_stick_bits_9_0_sva!=10'b0000000000) + | (FpMantDecShiftRight_10U_6U_10U_stick_mask_sva[10]) | (FpMantDecShiftRight_10U_6U_10U_least_bits_9_0_sva!=10'b0000000000) + | (FpMantDecShiftRight_10U_6U_10U_least_mask_sva[10])); + assign nl_FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva = FpMantDecShiftRight_10U_6U_10U_i_mant_s_rshift_itm + + conv_u2u_1_11(FpMantDecShiftRight_10U_6U_10U_carry_and_nl); + assign FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva = nl_FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva[10:0]; + assign FpMantDecShiftRight_10U_6U_10U_guard_bits_9_0_sva = (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]) + & (FpMantDecShiftRight_10U_6U_10U_guard_mask_sva[9:0]); + assign FpMantDecShiftRight_10U_6U_10U_stick_bits_9_0_sva = (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]) + & (FpMantDecShiftRight_10U_6U_10U_stick_mask_sva[9:0]); + assign nl_FpMantDecShiftRight_10U_6U_10U_stick_mask_sva = FpMantDecShiftRight_10U_6U_10U_guard_mask_sva + + 11'b11111111111; + assign FpMantDecShiftRight_10U_6U_10U_stick_mask_sva = nl_FpMantDecShiftRight_10U_6U_10U_stick_mask_sva[10:0]; + assign FpMantDecShiftRight_10U_6U_10U_least_bits_9_0_sva = (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]) + & (FpMantDecShiftRight_10U_6U_10U_least_mask_sva[9:0]); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_6_mdf = chn_a_rsci_bawt & or_cse; + assign or_2_nl = chn_a_rsci_bawt | (~ or_cse); + assign mux_tmp = MUX_s_1_2_2(and_6_mdf, (or_2_nl), main_stage_v_1); + assign and_tmp_1 = FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 & chn_a_rsci_bawt + & or_cse; + assign or_tmp_7 = (~ FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2) + | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign or_tmp_8 = ~((~(FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 & chn_a_rsci_bawt)) + & or_cse); + assign mux_1_itm = MUX_s_1_2_2(and_tmp_1, or_tmp_8, FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2); + assign and_dcpl_6 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_8 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_11 = or_cse & main_stage_v_1; + assign and_dcpl_14 = and_dcpl_6 & (~ main_stage_v_1); + assign or_tmp_19 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_6_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = and_dcpl_11 & (IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 + | IsNaN_6U_10U_nor_itm_2); + assign main_stage_v_1_mx0c1 = or_cse & (~ chn_a_rsci_bawt) & main_stage_v_1; + assign chn_a_rsci_oswt_unreg = or_tmp_19; + assign chn_o_rsci_oswt_unreg = and_dcpl_6; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_6_mdf) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_11; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((and_dcpl_11 & nor_5_cse) | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2((FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]), + (FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl), + chn_o_rsci_d_9_0_mx0c1); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_13_10 <= 4'b0; + chn_o_rsci_d_14 <= 1'b0; + chn_o_rsci_d_15 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_13_10 <= MUX_v_4_2_2((FpExpoWidthDec_6U_5U_10U_1U_1U_mux_6_nl), + 4'b1111, nor_5_cse); + chn_o_rsci_d_14 <= ((~ (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[14])) + & FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2 + & (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2)) + | (~ FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2) + | nor_5_cse; + chn_o_rsci_d_15 <= FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_11 | and_dcpl_14) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_14; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_19 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1 <= 15'b0; + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1 <= 1'b0; + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2 + <= 1'b0; + IsNaN_6U_10U_nor_itm_2 <= 1'b0; + IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 <= 1'b0; + end + else if ( Fp17ToFp16_and_cse ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1 <= chn_a_rsci_d_mxwt[14:0]; + FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_16_1 <= chn_a_rsci_d_mxwt[16]; + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2 + <= FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1; + IsNaN_6U_10U_nor_itm_2 <= ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + IsNaN_6U_10U_IsNaN_6U_10U_nand_itm_2 <= ~((chn_a_rsci_d_mxwt[15:10]==6'b111111)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 <= 3'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_3_nl) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 <= nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2[2:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_5_nl) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2 + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2 + <= 1'b0; + end + else if ( core_wen & ((or_cse & FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1 & + (~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1)) | and_35_rgt) & mux_tmp + ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2 + <= MUX_s_1_2_2(FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1, FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs, + and_35_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2 + <= 1'b0; + end + else if ( core_wen & ((or_cse & FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) | + and_37_rgt) & mux_tmp ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2 + <= MUX_s_1_2_2(FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1, FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs, + and_37_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_6_nl) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2 + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs + <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_8 | (~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) + | (~ chn_a_rsci_bawt) | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 + | (fsm_output[0]))) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs + <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_8 | (~ FpExpoWidthDec_6U_5U_10U_1U_1U_acc_itm_6_1) + | (~ chn_a_rsci_bawt) | (fsm_output[0]))) ) begin + FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs + <= FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + end + end + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_nl = MUX_v_10_2_2((FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva[9:0]), + (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[9:0]), FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_16_nl = ~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl = ~(MUX_v_10_2_2(10'b0000000000, + (FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_nl), (FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_16_nl))); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl + = ~(MUX_v_10_2_2(10'b0000000000, (FpExpoWidthDec_6U_5U_10U_1U_1U_nand_nl), + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2)); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_6_nl = MUX_v_4_2_2(({3'b0 , + (FpMantDecShiftRight_10U_6U_10U_o_mant_sum_sva[10])}), (FpExpoWidthDec_6U_5U_10U_1U_1U_bits_sva_1_14_0_1[13:10]), + FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_2); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_15_nl = ~ FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_2; + assign FpExpoWidthDec_6U_5U_10U_1U_1U_else_FpExpoWidthDec_6U_5U_10U_1U_1U_else_and_2_nl + = MUX_v_4_2_2(4'b0000, (FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_mux_6_nl), + (FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_not_15_nl)); + assign FpExpoWidthDec_6U_5U_10U_1U_1U_mux_6_nl = MUX_v_4_2_2(4'b1110, (FpExpoWidthDec_6U_5U_10U_1U_1U_else_FpExpoWidthDec_6U_5U_10U_1U_1U_else_and_2_nl), + FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2); + assign nl_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_if_i_shift_acc_psp_1_sva_2 + = (~ (chn_a_rsci_d_mxwt[13:11])) + 3'b1; + assign nor_7_nl = ~(FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1 | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 + | (~ and_tmp_1)); + assign or_6_nl = FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_itm_6_1 | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1; + assign mux_2_nl = MUX_s_1_2_2(mux_1_itm, (~ or_tmp_7), or_6_nl); + assign or_3_nl = FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_else_acc_6_svs_st_2 + | (~ main_stage_v_1) | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2; + assign mux_3_nl = MUX_s_1_2_2((mux_2_nl), (nor_7_nl), or_3_nl); + assign nor_nl = ~(FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1 | (~ and_tmp_1)); + assign mux_4_nl = MUX_s_1_2_2(mux_1_itm, (~ or_tmp_7), FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_itm_5_1); + assign or_10_nl = (~ main_stage_v_1) | FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_else_if_acc_5_svs_st_2; + assign mux_5_nl = MUX_s_1_2_2((mux_4_nl), (nor_nl), or_10_nl); + assign and_60_nl = main_stage_v_1 & FpExpoWidthDec_6U_5U_10U_1U_1U_if_slc_FpExpoWidthDec_6U_5U_10U_1U_1U_acc_6_svs_2; + assign mux_6_nl = MUX_s_1_2_2(and_tmp_1, or_tmp_8, and_60_nl); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_7_1_6; + input [6:0] vector; + reg [6:0] tmp; + begin + tmp = vector >> 6; + readslicef_7_1_6 = tmp[0:0]; + end + endfunction + function [4:0] conv_u2s_4_5 ; + input [3:0] vector ; + begin + conv_u2s_4_5 = {1'b0, vector}; + end + endfunction + function [6:0] conv_u2s_6_7 ; + input [5:0] vector ; + begin + conv_u2s_6_7 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [5:0] conv_u2u_5_6 ; + input [4:0] vector ; + begin + conv_u2u_5_6 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp16 +// ------------------------------------------------------------------ +module HLS_fp17_to_fp16 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP16_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP17_TO_FP16_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_to_fp16_core HLS_fp17_to_fp16_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp32.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp32.v new file mode 100644 index 0000000..3b06af2 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp32.v @@ -0,0 +1,817 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_to_fp32.v +module FP17_TO_FP32_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_TO_FP32_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_TO_FP32_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:09:21 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP32_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP32_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP32_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP32_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_to_fp32_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_to_fp32_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP32_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP32_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [2:0] chn_o_rsci_d_30_28; + reg [4:0] chn_o_rsci_d_27_23; + reg [9:0] chn_o_rsci_d_22_13; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_10; + wire [1:0] fsm_output; + wire IsNaN_6U_23U_nor_tmp; + wire and_dcpl_2; + wire or_dcpl_3; + wire and_dcpl_7; + wire and_dcpl_11; + wire or_dcpl_9; + wire and_dcpl_25; + wire or_tmp_18; + wire and_46_cse; + wire and_48_cse; + wire and_4_mdf; + wire IsNaN_6U_23U_IsNaN_6U_23U_nand_cse; + wire [9:0] FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm; + wire [9:0] FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm; + wire chn_o_and_4_cse; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire chn_o_rsci_d_9_0_mx0c1; + wire IsInf_6U_23U_land_lpi_1_dfm_mx1w0; + wire HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire IsNaN_6U_23U_land_lpi_1_dfm; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb_1; + wire[0:0] iExpoWidth_oExpoWidth_prb_1; + wire[0:0] nand_11_nl; + wire[0:0] nand_10_nl; + wire[4:0] FpExpoWidthInc_6U_8U_23U_0U_1U_mux_5_nl; + wire[2:0] FpExpoWidthInc_6U_8U_23U_0U_1U_FpExpoWidthInc_6U_8U_23U_0U_1U_and_nl; + wire[2:0] FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl; + wire[3:0] nl_FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl; + wire[0:0] IsZero_6U_23U_aelse_IsZero_6U_23U_or_nl; + wire[0:0] and_6_nl; + wire[0:0] IsNaN_6U_23U_aelse_not_2_nl; +// Interconnect Declarations for Component Instantiations + wire [31:0] nl_HLS_fp17_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 + , chn_o_rsci_d_30_28 , chn_o_rsci_d_27_23 , chn_o_rsci_d_22_13 , ({{2{chn_o_rsci_d_10}}, + chn_o_rsci_d_10}) , chn_o_rsci_d_9_0}; + HLS_fp17_to_fp32_core_chn_a_rsci HLS_fp17_to_fp32_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_to_fp32_core_chn_o_rsci HLS_fp17_to_fp32_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp17_to_fp32_core_staller HLS_fp17_to_fp32_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_to_fp32_core_core_fsm HLS_fp17_to_fp32_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iExpoWidth_oExpoWidth_prb = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 596 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln596_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 597 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln597_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb_1 = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 550 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln550_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb_1 } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb_1 = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 477 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb_1 } @rose(nvdla_core_clk); + assign chn_o_and_4_cse = core_wen & (~(or_dcpl_3 | (fsm_output[0]))); + assign and_6_nl = and_4_mdf & (fsm_output[1]); + assign HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_6_nl)), fsm_output[1]); + assign IsInf_6U_23U_land_lpi_1_dfm_mx1w0 = ~((FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm!=10'b0000000000) + | (FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm!=10'b0000000000) | + IsNaN_6U_23U_IsNaN_6U_23U_nand_cse); + assign FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), IsNaN_6U_23U_land_lpi_1_dfm); + assign IsNaN_6U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign IsNaN_6U_23U_land_lpi_1_dfm = ~(IsNaN_6U_23U_nor_tmp | IsNaN_6U_23U_IsNaN_6U_23U_nand_cse); + assign IsNaN_6U_23U_aelse_not_2_nl = ~ IsNaN_6U_23U_land_lpi_1_dfm; + assign FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), (IsNaN_6U_23U_aelse_not_2_nl)); + assign IsNaN_6U_23U_IsNaN_6U_23U_nand_cse = ~((chn_a_rsci_d_mxwt[15:10]==6'b111111)); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign or_dcpl_3 = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign and_dcpl_7 = (chn_a_rsci_d_mxwt[14:13]==2'b11); + assign and_dcpl_11 = (chn_a_rsci_d_mxwt[12:10]==3'b111); + assign or_dcpl_9 = (chn_a_rsci_d_mxwt[15:10]!=6'b111111) | IsNaN_6U_23U_nor_tmp; + assign and_dcpl_25 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_46_cse = and_dcpl_11 & or_cse & and_dcpl_7 & (chn_a_rsci_d_mxwt[15]) + & (~ IsNaN_6U_23U_nor_tmp) & chn_a_rsci_bawt & (fsm_output[1]); + assign and_48_cse = or_dcpl_9 & or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign or_tmp_18 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = and_48_cse | (or_dcpl_9 & and_dcpl_2 & chn_a_rsci_bawt); + assign chn_a_rsci_oswt_unreg = or_tmp_18; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= or_tmp_18; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_10 <= 1'b0; + end + else if ( core_wen & (~ (fsm_output[0])) & (~ or_dcpl_3) ) begin + chn_o_rsci_d_10 <= IsInf_6U_23U_land_lpi_1_dfm_mx1w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & (and_46_cse | (and_dcpl_11 & and_dcpl_7 & (chn_a_rsci_d_mxwt[15]) + & (~ IsNaN_6U_23U_nor_tmp) & chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt) | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(({{9{IsInf_6U_23U_land_lpi_1_dfm_mx1w0}}, + IsInf_6U_23U_land_lpi_1_dfm_mx1w0}), FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm, + nand_11_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_13 <= 10'b0; + end + else if ( core_wen & (and_46_cse | and_48_cse) ) begin + chn_o_rsci_d_22_13 <= MUX_v_10_2_2(({{9{IsInf_6U_23U_land_lpi_1_dfm_mx1w0}}, + IsInf_6U_23U_land_lpi_1_dfm_mx1w0}), FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm, + nand_10_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_27_23 <= 5'b0; + end + else if ( core_wen & (~(or_dcpl_3 | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_27_23 <= MUX_v_5_2_2((FpExpoWidthInc_6U_8U_23U_0U_1U_mux_5_nl), + 5'b11111, IsNaN_6U_23U_land_lpi_1_dfm); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_28 <= 3'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_4_cse ) begin + chn_o_rsci_d_30_28 <= (FpExpoWidthInc_6U_8U_23U_0U_1U_FpExpoWidthInc_6U_8U_23U_0U_1U_and_nl) + | ({{2{IsInf_6U_23U_land_lpi_1_dfm_mx1w0}}, IsInf_6U_23U_land_lpi_1_dfm_mx1w0}) + | ({{2{IsNaN_6U_23U_land_lpi_1_dfm}}, IsNaN_6U_23U_land_lpi_1_dfm}); + chn_o_rsci_d_31 <= chn_a_rsci_d_mxwt[16]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (or_tmp_18 | and_dcpl_25) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_25; + end + end + assign nand_11_nl = ~(IsInf_6U_23U_land_lpi_1_dfm_mx1w0 & chn_o_rsci_d_9_0_mx0c1); + assign nand_10_nl = ~(IsInf_6U_23U_land_lpi_1_dfm_mx1w0 & and_48_cse); + assign FpExpoWidthInc_6U_8U_23U_0U_1U_mux_5_nl = MUX_v_5_2_2((chn_a_rsci_d_mxwt[14:10]), + 5'b11110, IsInf_6U_23U_land_lpi_1_dfm_mx1w0); + assign nl_FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl = conv_u2u_2_3({1'b1 , (chn_a_rsci_d_mxwt[15])}) + + 3'b1; + assign FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl = nl_FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl[2:0]; + assign IsZero_6U_23U_aelse_IsZero_6U_23U_or_nl = (chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000); + assign FpExpoWidthInc_6U_8U_23U_0U_1U_FpExpoWidthInc_6U_8U_23U_0U_1U_and_nl = MUX_v_3_2_2(3'b000, + (FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl), (IsZero_6U_23U_aelse_IsZero_6U_23U_or_nl)); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [2:0] MUX_v_3_2_2; + input [2:0] input_0; + input [2:0] input_1; + input [0:0] sel; + reg [2:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_3_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [2:0] conv_u2u_2_3 ; + input [1:0] vector ; + begin + conv_u2u_2_3 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32 +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP32_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP17_TO_FP32_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_to_fp32_core HLS_fp17_to_fp32_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp32.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp32.v.vcp new file mode 100644 index 0000000..3b06af2 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp17_to_fp32.v.vcp @@ -0,0 +1,817 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp17_to_fp32.v +module FP17_TO_FP32_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP17_TO_FP32_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP17_TO_FP32_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-084 +// Generated date: Mon Mar 20 14:09:21 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP32_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP32_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP17_TO_FP32_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP17_TO_FP32_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp17_to_fp32_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp17_to_fp32_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_staller +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [16:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [16:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [16:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_17_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 17'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [16:0] MUX_v_17_2_2; + input [16:0] input_0; + input [16:0] input_1; + input [0:0] sel; + reg [16:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_17_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP32_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp HLS_fp17_to_fp32_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [16:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [16:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP32_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd17)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp HLS_fp17_to_fp32_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32_core +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [16:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [2:0] chn_o_rsci_d_30_28; + reg [4:0] chn_o_rsci_d_27_23; + reg [9:0] chn_o_rsci_d_22_13; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_10; + wire [1:0] fsm_output; + wire IsNaN_6U_23U_nor_tmp; + wire and_dcpl_2; + wire or_dcpl_3; + wire and_dcpl_7; + wire and_dcpl_11; + wire or_dcpl_9; + wire and_dcpl_25; + wire or_tmp_18; + wire and_46_cse; + wire and_48_cse; + wire and_4_mdf; + wire IsNaN_6U_23U_IsNaN_6U_23U_nand_cse; + wire [9:0] FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm; + wire [9:0] FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm; + wire chn_o_and_4_cse; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire chn_o_rsci_d_9_0_mx0c1; + wire IsInf_6U_23U_land_lpi_1_dfm_mx1w0; + wire HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire IsNaN_6U_23U_land_lpi_1_dfm; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iMantWidth_oMantWidth_prb_1; + wire[0:0] iExpoWidth_oExpoWidth_prb_1; + wire[0:0] nand_11_nl; + wire[0:0] nand_10_nl; + wire[4:0] FpExpoWidthInc_6U_8U_23U_0U_1U_mux_5_nl; + wire[2:0] FpExpoWidthInc_6U_8U_23U_0U_1U_FpExpoWidthInc_6U_8U_23U_0U_1U_and_nl; + wire[2:0] FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl; + wire[3:0] nl_FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl; + wire[0:0] IsZero_6U_23U_aelse_IsZero_6U_23U_or_nl; + wire[0:0] and_6_nl; + wire[0:0] IsNaN_6U_23U_aelse_not_2_nl; +// Interconnect Declarations for Component Instantiations + wire [31:0] nl_HLS_fp17_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp17_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 + , chn_o_rsci_d_30_28 , chn_o_rsci_d_27_23 , chn_o_rsci_d_22_13 , ({{2{chn_o_rsci_d_10}}, + chn_o_rsci_d_10}) , chn_o_rsci_d_9_0}; + HLS_fp17_to_fp32_core_chn_a_rsci HLS_fp17_to_fp32_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp17_to_fp32_core_chn_o_rsci HLS_fp17_to_fp32_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp17_to_fp32_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp17_to_fp32_core_staller HLS_fp17_to_fp32_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp17_to_fp32_core_core_fsm HLS_fp17_to_fp32_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iExpoWidth_oExpoWidth_prb = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 596 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln596_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 597 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln597_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iMantWidth_oMantWidth_prb_1 = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iMantWidth <= oMantWidth) - ../include/nvdla_float.h: line 550 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln550_assert_iMantWidth_le_oMantWidth : assert { iMantWidth_oMantWidth_prb_1 } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb_1 = HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0; +// assert(iExpoWidth <= oExpoWidth) - ../include/nvdla_float.h: line 477 +// PSL HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb_1 } @rose(nvdla_core_clk); + assign chn_o_and_4_cse = core_wen & (~(or_dcpl_3 | (fsm_output[0]))); + assign and_6_nl = and_4_mdf & (fsm_output[1]); + assign HLS_fp17_to_fp32_core_nvdla_float_h_ln477_assert_iExpoWidth_le_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_6_nl)), fsm_output[1]); + assign IsInf_6U_23U_land_lpi_1_dfm_mx1w0 = ~((FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm!=10'b0000000000) + | (FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm!=10'b0000000000) | + IsNaN_6U_23U_IsNaN_6U_23U_nand_cse); + assign FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), IsNaN_6U_23U_land_lpi_1_dfm); + assign IsNaN_6U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[9:0]!=10'b0000000000)); + assign IsNaN_6U_23U_land_lpi_1_dfm = ~(IsNaN_6U_23U_nor_tmp | IsNaN_6U_23U_IsNaN_6U_23U_nand_cse); + assign IsNaN_6U_23U_aelse_not_2_nl = ~ IsNaN_6U_23U_land_lpi_1_dfm; + assign FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm = MUX_v_10_2_2(10'b0000000000, + (chn_a_rsci_d_mxwt[9:0]), (IsNaN_6U_23U_aelse_not_2_nl)); + assign IsNaN_6U_23U_IsNaN_6U_23U_nand_cse = ~((chn_a_rsci_d_mxwt[15:10]==6'b111111)); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign or_dcpl_3 = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign and_dcpl_7 = (chn_a_rsci_d_mxwt[14:13]==2'b11); + assign and_dcpl_11 = (chn_a_rsci_d_mxwt[12:10]==3'b111); + assign or_dcpl_9 = (chn_a_rsci_d_mxwt[15:10]!=6'b111111) | IsNaN_6U_23U_nor_tmp; + assign and_dcpl_25 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_46_cse = and_dcpl_11 & or_cse & and_dcpl_7 & (chn_a_rsci_d_mxwt[15]) + & (~ IsNaN_6U_23U_nor_tmp) & chn_a_rsci_bawt & (fsm_output[1]); + assign and_48_cse = or_dcpl_9 & or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign or_tmp_18 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = and_48_cse | (or_dcpl_9 & and_dcpl_2 & chn_a_rsci_bawt); + assign chn_a_rsci_oswt_unreg = or_tmp_18; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= or_tmp_18; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_10 <= 1'b0; + end + else if ( core_wen & (~ (fsm_output[0])) & (~ or_dcpl_3) ) begin + chn_o_rsci_d_10 <= IsInf_6U_23U_land_lpi_1_dfm_mx1w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & (and_46_cse | (and_dcpl_11 & and_dcpl_7 & (chn_a_rsci_d_mxwt[15]) + & (~ IsNaN_6U_23U_nor_tmp) & chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt) | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(({{9{IsInf_6U_23U_land_lpi_1_dfm_mx1w0}}, + IsInf_6U_23U_land_lpi_1_dfm_mx1w0}), FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_9_0_lpi_1_dfm, + nand_11_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_13 <= 10'b0; + end + else if ( core_wen & (and_46_cse | and_48_cse) ) begin + chn_o_rsci_d_22_13 <= MUX_v_10_2_2(({{9{IsInf_6U_23U_land_lpi_1_dfm_mx1w0}}, + IsInf_6U_23U_land_lpi_1_dfm_mx1w0}), FpMantWidthInc_6U_10U_23U_0U_1U_o_mant_22_13_lpi_1_dfm, + nand_10_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_27_23 <= 5'b0; + end + else if ( core_wen & (~(or_dcpl_3 | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_27_23 <= MUX_v_5_2_2((FpExpoWidthInc_6U_8U_23U_0U_1U_mux_5_nl), + 5'b11111, IsNaN_6U_23U_land_lpi_1_dfm); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_28 <= 3'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_4_cse ) begin + chn_o_rsci_d_30_28 <= (FpExpoWidthInc_6U_8U_23U_0U_1U_FpExpoWidthInc_6U_8U_23U_0U_1U_and_nl) + | ({{2{IsInf_6U_23U_land_lpi_1_dfm_mx1w0}}, IsInf_6U_23U_land_lpi_1_dfm_mx1w0}) + | ({{2{IsNaN_6U_23U_land_lpi_1_dfm}}, IsNaN_6U_23U_land_lpi_1_dfm}); + chn_o_rsci_d_31 <= chn_a_rsci_d_mxwt[16]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (or_tmp_18 | and_dcpl_25) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_25; + end + end + assign nand_11_nl = ~(IsInf_6U_23U_land_lpi_1_dfm_mx1w0 & chn_o_rsci_d_9_0_mx0c1); + assign nand_10_nl = ~(IsInf_6U_23U_land_lpi_1_dfm_mx1w0 & and_48_cse); + assign FpExpoWidthInc_6U_8U_23U_0U_1U_mux_5_nl = MUX_v_5_2_2((chn_a_rsci_d_mxwt[14:10]), + 5'b11110, IsInf_6U_23U_land_lpi_1_dfm_mx1w0); + assign nl_FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl = conv_u2u_2_3({1'b1 , (chn_a_rsci_d_mxwt[15])}) + + 3'b1; + assign FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl = nl_FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl[2:0]; + assign IsZero_6U_23U_aelse_IsZero_6U_23U_or_nl = (chn_a_rsci_d_mxwt[15:0]!=16'b0000000000000000); + assign FpExpoWidthInc_6U_8U_23U_0U_1U_FpExpoWidthInc_6U_8U_23U_0U_1U_and_nl = MUX_v_3_2_2(3'b000, + (FpExpoWidthInc_6U_8U_23U_0U_1U_else_acc_nl), (IsZero_6U_23U_aelse_IsZero_6U_23U_or_nl)); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [2:0] MUX_v_3_2_2; + input [2:0] input_0; + input [2:0] input_1; + input [0:0] sel; + reg [2:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_3_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [2:0] conv_u2u_2_3 ; + input [1:0] vector ; + begin + conv_u2u_2_3 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp17_to_fp32 +// ------------------------------------------------------------------ +module HLS_fp17_to_fp32 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [16:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP17_TO_FP32_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP17_TO_FP32_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp17_to_fp32_core HLS_fp17_to_fp32_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_add.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_add.v new file mode 100644 index 0000000..e28c3ef --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_add.v @@ -0,0 +1,1815 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_add.v +module FP32_ADD_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_ADD_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_ADD_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP32_ADD_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_ADD_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:52:55 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_leading_sign_49_0 +// ------------------------------------------------------------------ +module FP32_ADD_leading_sign_49_0 ( + mantissa, rtn +); + input [48:0] mantissa; + output [5:0] rtn; +// Interconnect Declarations + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_12; + wire c_h_1_13; + wire c_h_1_14; + wire c_h_1_17; + wire c_h_1_20; + wire c_h_1_21; + wire c_h_1_22; + wire c_h_1_23; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[46:45]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[48:47]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[44:43]!=2'b00)); + assign c_h_1_2 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[42:41]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[38:37]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[40:39]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[36:35]!=2'b00)); + assign c_h_1_5 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[34:33]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[30:29]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[32:31]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 = ~((mantissa[28:27]!=2'b00)); + assign c_h_1_9 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3 = (mantissa[26:25]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 = ~((mantissa[24:23]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 = ~((mantissa[20:19]!=2'b00)); + assign c_h_1_12 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + assign c_h_1_13 = c_h_1_9 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + assign c_h_1_14 = c_h_1_6 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5 = (mantissa[18:17]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 & c_h_1_12 & c_h_1_13; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 = ~((mantissa[16:15]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 = ~((mantissa[12:11]!=2'b00)); + assign c_h_1_17 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3 = (mantissa[10:9]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 = ~((mantissa[8:7]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 = ~((mantissa[4:3]!=2'b00)); + assign c_h_1_20 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + assign c_h_1_21 = c_h_1_17 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4 = (mantissa[2:1]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 & c_h_1_20; + assign c_h_1_22 = c_h_1_21 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + assign c_h_1_23 = c_h_1_14 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl = c_h_1_14 & (c_h_1_22 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl = c_h_1_6 & (c_h_1_13 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4)) & (~((~(c_h_1_21 + & (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4))) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl = c_h_1_2 & (c_h_1_5 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3)) & (~((~(c_h_1_9 + & (c_h_1_12 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3)))) + & c_h_1_14)) & (~(((~(c_h_1_17 & (c_h_1_20 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2)) & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2)))) + & c_h_1_13)))) & c_h_1_14)) & (~(((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2)))) & c_h_1_21)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl + = ((~((mantissa[48]) | (~((mantissa[47:46]!=2'b01))))) & (~(((mantissa[44]) + | (~((mantissa[43:42]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[40]) | (~((mantissa[39:38]!=2'b01))))) + & (~(((mantissa[36]) | (~((mantissa[35:34]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[32]) | (~((mantissa[31:30]!=2'b01))))) & (~(((mantissa[28]) + | (~((mantissa[27:26]!=2'b01)))) & c_h_1_9)) & (~((~((~((mantissa[24]) | (~((mantissa[23:22]!=2'b01))))) + & (~(((mantissa[20]) | (~((mantissa[19:18]!=2'b01)))) & c_h_1_12)))) & c_h_1_13)))) + & c_h_1_14)) & (~(((~((~((mantissa[16]) | (~((mantissa[15:14]!=2'b01))))) & + (~(((mantissa[12]) | (~((mantissa[11:10]!=2'b01)))) & c_h_1_17)) & (~((~((~((mantissa[8]) + | (~((mantissa[7:6]!=2'b01))))) & (~(((mantissa[4]) | (~((mantissa[3:2]!=2'b01)))) + & c_h_1_20)))) & c_h_1_21)))) | c_h_1_22) & c_h_1_23))) | ((~ (mantissa[0])) + & c_h_1_22 & c_h_1_23); + assign rtn = {c_h_1_23 , (IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:53:04 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_ADD_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP32_ADD_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_ADD_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_add_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_add_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_add_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_add_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [31:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [31:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [31:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_32_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 32'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_ADD_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [31:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [31:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core +// ------------------------------------------------------------------ +module HLS_fp32_add_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [31:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [7:0] chn_o_rsci_d_30_23; + reg [22:0] chn_o_rsci_d_22_0; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + wire FpAdd_8U_23U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_49U_24U_else_and_tmp; + wire IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + wire IsNaN_8U_23U_1_nor_tmp; + wire nor_tmp_1; + wire or_tmp_3; + wire mux_tmp_5; + wire nor_tmp_11; + wire or_tmp_16; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire and_dcpl_29; + wire and_dcpl_33; + wire or_tmp_29; + wire or_tmp_35; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_4; + reg [31:0] FpSignedBitsToFloat_8U_23U_bits_sva_36; + reg [31:0] FpSignedBitsToFloat_8U_23U_bits_1_sva_36; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_4; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_6; + reg [48:0] FpAdd_8U_23U_a_int_mant_p1_sva_2; + reg [48:0] FpAdd_8U_23U_b_int_mant_p1_sva_2; + reg FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3; + reg [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2; + reg IsNaN_8U_23U_land_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_6; + reg FpAdd_8U_23U_IsZero_8U_23U_or_itm_2; + reg FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2; + reg FpNormalize_8U_49U_if_or_itm_2; + reg IsNaN_8U_23U_1_nor_itm_2; + reg IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4; + reg FpAdd_8U_23U_mux_1_itm_2; + reg FpAdd_8U_23U_mux_13_itm_3; + reg FpAdd_8U_23U_mux_13_itm_4; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4; + reg IsNaN_8U_23U_land_lpi_1_dfm_st_4; + wire FpAdd_8U_23U_mux_2_tmp_49; + wire main_stage_en_1; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm; + wire [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + wire [7:0] FpAdd_8U_23U_o_expo_lpi_1_dfm_2; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_36_cse; + wire FpAdd_8U_23U_or_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + wire FpSignedBitsToFloat_8U_23U_and_rgt; + wire FpSignedBitsToFloat_8U_23U_and_1_rgt; + wire [48:0] FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + wire [48:0] FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + wire [48:0] FpNormalize_8U_49U_else_lshift_itm; + wire chn_o_rsci_d_22_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + wire [48:0] FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0; + wire [48:0] FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [49:0] FpAdd_8U_23U_asn_5_mx0w0; + wire [50:0] nl_FpAdd_8U_23U_asn_5_mx0w0; + wire [49:0] FpAdd_8U_23U_asn_4_mx0w1; + wire [51:0] nl_FpAdd_8U_23U_asn_4_mx0w1; + wire [48:0] FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0; + wire FpMantRNE_49U_24U_else_carry_sva; + wire FpAdd_8U_23U_and_tmp; + wire [7:0] FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm; + wire [7:0] FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm; + wire FpNormalize_8U_49U_oelse_not_3; + wire [5:0] libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1; + wire FpAdd_8U_23U_is_addition_and_cse; + wire FpAdd_8U_23U_and_8_cse; + wire IsNaN_8U_23U_aelse_and_cse; + wire FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse; + wire FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse; + wire IsNaN_8U_23U_1_and_cse; + reg reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse; + wire mux_13_cse; + wire mux_4_cse; + wire FpSignedBitsToFloat_8U_23U_1_and_1_cse; + wire FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + wire FpAdd_8U_23U_if_3_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_if_4_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1; + wire[22:0] FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl; + wire[22:0] FpMantRNE_49U_24U_else_acc_nl; + wire[23:0] nl_FpMantRNE_49U_24U_else_acc_nl; + wire[0:0] FpSignedBitsToFloat_8U_23U_1_and_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_nl; + wire[0:0] FpAdd_8U_23U_and_3_nl; + wire[0:0] FpAdd_8U_23U_and_7_nl; + wire[0:0] mux_6_nl; + wire[0:0] mux_8_nl; + wire[0:0] mux_7_nl; + wire[0:0] nor_37_nl; + wire[0:0] nor_7_nl; + wire[0:0] mux_10_nl; + wire[0:0] or_10_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_34_nl; + wire[0:0] and_67_nl; + wire[0:0] mux_23_nl; + wire[0:0] mux_22_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_25_nl; + wire[0:0] mux_24_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_27_nl; + wire[0:0] nor_28_nl; + wire[0:0] nor_29_nl; + wire[0:0] mux_28_nl; + wire[0:0] nor_26_nl; + wire[0:0] nor_27_nl; + wire[8:0] FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[10:0] nl_FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[7:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl; + wire[7:0] FpNormalize_8U_49U_else_acc_nl; + wire[9:0] nl_FpNormalize_8U_49U_else_acc_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_1_nl; + wire[0:0] FpAdd_8U_23U_and_2_nl; + wire[48:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl; + wire[0:0] FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[7:0] FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[7:0] FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[0:0] FpAdd_8U_23U_is_a_greater_oelse_not_5_nl; + wire[8:0] FpNormalize_8U_49U_acc_nl; + wire[10:0] nl_FpNormalize_8U_49U_acc_nl; + wire[0:0] nor_38_nl; + wire[23:0] FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; + wire[25:0] nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 + , (FpSignedBitsToFloat_8U_23U_bits_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_a_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_a_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_a_left_shift_acc_nl = nl_FpAdd_8U_23U_a_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_a_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[0]))}; + wire [23:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 + , (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_b_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_b_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_b_left_shift_acc_nl = nl_FpAdd_8U_23U_b_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_b_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[0]))}; + wire [48:0] nl_FpNormalize_8U_49U_else_lshift_rg_a; + assign nl_FpNormalize_8U_49U_else_lshift_rg_a = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [48:0] nl_leading_sign_49_0_rg_mantissa; + assign nl_leading_sign_49_0_rg_mantissa = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [31:0] nl_HLS_fp32_add_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_add_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 , chn_o_rsci_d_30_23 + , chn_o_rsci_d_22_0}; + FP32_ADD_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_a_int_mant_p1_lshift_itm) + ); + FP32_ADD_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_b_int_mant_p1_lshift_itm) + ); + FP32_ADD_mgc_shift_l_v4 #(.width_a(32'sd49), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd49)) FpNormalize_8U_49U_else_lshift_rg ( + .a(nl_FpNormalize_8U_49U_else_lshift_rg_a[48:0]), + .s(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1), + .z(FpNormalize_8U_49U_else_lshift_itm) + ); + FP32_ADD_leading_sign_49_0 leading_sign_49_0_rg ( + .mantissa(nl_leading_sign_49_0_rg_mantissa[48:0]), + .rtn(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + ); + HLS_fp32_add_core_chn_a_rsci HLS_fp32_add_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_add_core_chn_b_rsci HLS_fp32_add_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp32_add_core_chn_o_rsci HLS_fp32_add_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_add_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp32_add_core_staller HLS_fp32_add_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_add_core_core_fsm HLS_fp32_add_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_8U_23U_or_cse = IsNaN_8U_23U_1_land_lpi_1_dfm_4 | IsNaN_8U_23U_land_lpi_1_dfm_6; + assign IsNaN_8U_23U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_13_cse; + assign FpAdd_8U_23U_is_addition_and_cse = core_wen & (~ and_dcpl_7) & mux_4_cse; + assign mux_4_cse = MUX_s_1_2_2(main_stage_v_1, main_stage_v_2, nor_36_cse); + assign mux_6_nl = MUX_s_1_2_2(mux_tmp_5, or_tmp_3, main_stage_v_3); + assign FpAdd_8U_23U_and_8_cse = core_wen & (~ and_dcpl_7) & (mux_6_nl); + assign nor_36_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_10_nl = nor_36_cse | nor_tmp_11; + assign nor_34_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_11)); + assign mux_9_nl = MUX_s_1_2_2((nor_34_nl), nor_tmp_11, chn_o_rsci_bawt); + assign and_67_nl = FpAdd_8U_23U_or_cse & main_stage_v_3; + assign mux_10_nl = MUX_s_1_2_2((mux_9_nl), (or_10_nl), and_67_nl); + assign FpSignedBitsToFloat_8U_23U_1_and_1_cse = core_wen & (~ and_dcpl_7) & (mux_10_nl); + assign FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse = ((~ FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1) + & FpAdd_8U_23U_is_a_greater_oif_equal_tmp) | FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + assign mux_13_cse = MUX_s_1_2_2(nor_tmp_1, main_stage_v_1, nor_36_cse); + assign FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse = and_dcpl_28 + | and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_and_rgt = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0) + & and_dcpl_28; + assign FpSignedBitsToFloat_8U_23U_and_1_rgt = IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 + & and_dcpl_28; + assign FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse = (FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse + & or_cse) | and_dcpl_33; + assign nor_26_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~ main_stage_v_1)); + assign nor_27_nl = ~(IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_28_nl = MUX_s_1_2_2((nor_27_nl), (nor_26_nl), nor_36_cse); + assign IsNaN_8U_23U_1_and_cse = core_wen & (~ and_dcpl_7) & (mux_28_nl); + assign IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000))) + | (chn_a_rsci_d_mxwt[30:23]!=8'b11111111)); + assign FpAdd_8U_23U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[30:23]) == + (chn_b_rsci_d_mxwt[30:23]); + assign IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2); + assign IsNaN_8U_23U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp = ~((chn_b_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpAdd_8U_23U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[30:23])}) + + conv_u2u_8_9(~ (chn_a_rsci_d_mxwt[30:23])) + 9'b1; + assign FpAdd_8U_23U_is_a_greater_acc_1_nl = nl_FpAdd_8U_23U_is_a_greater_acc_1_nl[8:0]; + assign FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1 = readslicef_9_1_8((FpAdd_8U_23U_is_a_greater_acc_1_nl)); + assign FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_b_int_mant_p1_sva_2, + FpAdd_8U_23U_a_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_a_int_mant_p1_sva_2, + FpAdd_8U_23U_b_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign nl_FpAdd_8U_23U_asn_5_mx0w0 = conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + + conv_u2u_49_50(FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0); + assign FpAdd_8U_23U_asn_5_mx0w0 = nl_FpAdd_8U_23U_asn_5_mx0w0[49:0]; + assign nl_FpAdd_8U_23U_asn_4_mx0w1 = ({1'b1 , (~ FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0)}) + + conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + 50'b1; + assign FpAdd_8U_23U_asn_4_mx0w1 = nl_FpAdd_8U_23U_asn_4_mx0w1[49:0]; + assign FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0 = MUX_v_50_2_2(FpAdd_8U_23U_asn_4_mx0w1, + FpAdd_8U_23U_asn_5_mx0w0, reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse); + assign nl_FpAdd_8U_23U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_qr_lpi_1_dfm_6[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_1_nl = nl_FpAdd_8U_23U_if_3_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_3_if_acc_1_nl)); + assign nl_FpNormalize_8U_49U_else_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + ({2'b11 + , (~ libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1)}) + + 8'b1; + assign FpNormalize_8U_49U_else_acc_nl = nl_FpNormalize_8U_49U_else_acc_nl[7:0]; + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl = MUX_v_8_2_2(8'b00000000, + (FpNormalize_8U_49U_else_acc_nl), FpNormalize_8U_49U_oelse_not_3); + assign nl_FpAdd_8U_23U_if_3_if_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_nl = nl_FpAdd_8U_23U_if_3_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_1_nl = (~ FpAdd_8U_23U_if_3_if_acc_1_itm_7_1) & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_and_2_nl = FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_o_expo_lpi_1_dfm_2 = MUX1HOT_v_8_3_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl), + FpAdd_8U_23U_qr_lpi_1_dfm_6, (FpAdd_8U_23U_if_3_if_acc_nl), {(~ (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49])) + , (FpAdd_8U_23U_and_1_nl) , (FpAdd_8U_23U_and_2_nl)}); + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl = MUX_v_49_2_2(49'b0000000000000000000000000000000000000000000000000, + FpNormalize_8U_49U_else_lshift_itm, FpNormalize_8U_49U_oelse_not_3); + assign FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0 = MUX_v_49_2_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl), + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49:1]), FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpMantRNE_49U_24U_else_carry_sva = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[24]) + & ((FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[0]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[1]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[2]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[3]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[4]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[5]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[6]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[7]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[8]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[9]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[10]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[11]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[12]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[13]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[14]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[15]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[16]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[17]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[18]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[19]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[20]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[21]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[22]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[23]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[25])); + assign FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm + | (~ FpAdd_8U_23U_if_4_if_acc_1_itm_7_1); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_8U_23U_is_inf_lpi_1_dfm, + (FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl), FpMantRNE_49U_24U_else_and_tmp); + assign nl_FpAdd_8U_23U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_o_expo_lpi_1_dfm_2[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_1_nl = nl_FpAdd_8U_23U_if_4_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_4_if_acc_1_nl)); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm = ~(FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 | (~ + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]))); + assign FpAdd_8U_23U_and_tmp = FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 & FpMantRNE_49U_24U_else_and_tmp; + assign FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c = ~(IsNaN_8U_23U_1_land_lpi_1_dfm_4 + | IsNaN_8U_23U_land_lpi_1_dfm_6); + assign FpMantRNE_49U_24U_else_and_tmp = FpMantRNE_49U_24U_else_carry_sva & (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[48:25]==24'b111111111111111111111111); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_cse; + assign nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl = (FpSignedBitsToFloat_8U_23U_bits_sva_36[30:23]) + - (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[30:23]); + assign FpAdd_8U_23U_b_right_shift_qif_acc_nl = nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl[7:0]; + assign FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_b_right_shift_qif_acc_nl), + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4); + assign nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl = (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[30:23]) + - (FpSignedBitsToFloat_8U_23U_bits_sva_36[30:23]); + assign FpAdd_8U_23U_a_right_shift_qelse_acc_nl = nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl[7:0]; + assign FpAdd_8U_23U_is_a_greater_oelse_not_5_nl = ~ FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + assign FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_a_right_shift_qelse_acc_nl), + (FpAdd_8U_23U_is_a_greater_oelse_not_5_nl)); + assign nl_FpNormalize_8U_49U_acc_nl = ({1'b1 , (~ FpAdd_8U_23U_qr_lpi_1_dfm_6)}) + + conv_u2s_6_9(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + + 9'b1; + assign FpNormalize_8U_49U_acc_nl = nl_FpNormalize_8U_49U_acc_nl[8:0]; + assign FpNormalize_8U_49U_oelse_not_3 = FpNormalize_8U_49U_if_or_itm_2 & (readslicef_9_1_8((FpNormalize_8U_49U_acc_nl))); + assign FpAdd_8U_23U_mux_2_tmp_49 = MUX_s_1_2_2((FpAdd_8U_23U_asn_4_mx0w1[49]), + (FpAdd_8U_23U_asn_5_mx0w0[49]), reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse); + assign nor_tmp_1 = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_tmp_3 = nor_36_cse | main_stage_v_2; + assign nor_38_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_tmp_5 = MUX_s_1_2_2((nor_38_nl), main_stage_v_2, chn_o_rsci_bawt); + assign nor_tmp_11 = (IsNaN_8U_23U_1_land_lpi_1_dfm_3 | IsNaN_8U_23U_land_lpi_1_dfm_5) + & main_stage_v_2; + assign or_tmp_16 = IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign and_dcpl_28 = or_cse & (~ IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign and_dcpl_29 = or_cse & IsNaN_8U_23U_land_lpi_1_dfm_st_4; + assign and_dcpl_33 = or_cse & (~ FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1) & (FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 + | (~ FpAdd_8U_23U_is_a_greater_oif_equal_tmp)); + assign or_tmp_29 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_35 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_cse & (fsm_output[1]); + assign chn_o_rsci_d_22_0_mx0c1 = or_cse & main_stage_v_3 & (~ IsNaN_8U_23U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_b_rsci_bawt & chn_a_rsci_bawt)) & main_stage_v_1 + & or_cse; + assign main_stage_v_2_mx0c1 = main_stage_v_2 & (~ main_stage_v_1) & or_cse; + assign main_stage_v_3_mx0c1 = or_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[22:0])}) + + conv_u2u_23_24(~ (chn_b_rsci_d_mxwt[22:0])) + 24'b1; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl[23:0]; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 = readslicef_24_1_23((FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_35; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_29 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_29; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_0 <= 23'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_3 & IsNaN_8U_23U_land_lpi_1_dfm_6) + | chn_o_rsci_d_22_0_mx0c1) ) begin + chn_o_rsci_d_22_0 <= MUX_v_23_2_2(FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4, + (FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl), FpSignedBitsToFloat_8U_23U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_23 <= 8'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_30_23 <= MUX1HOT_v_8_4_2(FpAdd_8U_23U_o_expo_lpi_1_dfm_2, (FpAdd_8U_23U_if_4_if_acc_nl), + 8'b11111110, FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4, + {(FpAdd_8U_23U_and_nl) , (FpAdd_8U_23U_and_3_nl) , (FpAdd_8U_23U_and_7_nl) + , FpAdd_8U_23U_or_cse}); + chn_o_rsci_d_31 <= FpAdd_8U_23U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_35 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= 1'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3 <= 1'b0; + FpSignedBitsToFloat_8U_23U_bits_sva_36 <= 32'b0; + FpSignedBitsToFloat_8U_23U_bits_1_sva_36 <= 32'b0; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= 1'b0; + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_aelse_and_cse ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3 <= ~((chn_a_rsci_d_mxwt[31]) + ^ (chn_b_rsci_d_mxwt[31])); + FpSignedBitsToFloat_8U_23U_bits_sva_36 <= chn_a_rsci_d_mxwt; + FpSignedBitsToFloat_8U_23U_bits_1_sva_36 <= chn_b_rsci_d_mxwt; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= (chn_a_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse <= 1'b0; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= 1'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= 1'b0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= 8'b0; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= 1'b0; + end + else if ( FpAdd_8U_23U_is_addition_and_cse ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse <= FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= FpAdd_8U_23U_qr_lpi_1_dfm_4; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= IsNaN_8U_23U_land_lpi_1_dfm_st_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_2) | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= 8'b0; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= 50'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_mux_13_itm_4 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= 1'b0; + end + else if ( FpAdd_8U_23U_and_8_cse ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= FpAdd_8U_23U_qr_lpi_1_dfm_5; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= IsNaN_8U_23U_1_land_lpi_1_dfm_3; + FpAdd_8U_23U_mux_13_itm_4 <= FpAdd_8U_23U_mux_13_itm_3; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= IsNaN_8U_23U_land_lpi_1_dfm_5; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpNormalize_8U_49U_if_or_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_8_nl) ) begin + FpNormalize_8U_49U_if_or_itm_2 <= (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0[48:0]!=49'b0000000000000000000000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= 23'b0; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= 8'b0; + end + else if ( FpSignedBitsToFloat_8U_23U_1_and_1_cse ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= 23'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_23_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= MUX_v_23_2_2((FpSignedBitsToFloat_8U_23U_bits_1_sva_36[22:0]), (FpSignedBitsToFloat_8U_23U_bits_sva_36[22:0]), + and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_25_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= MUX_v_8_2_2((FpSignedBitsToFloat_8U_23U_bits_1_sva_36[30:23]), (FpSignedBitsToFloat_8U_23U_bits_sva_36[30:23]), + and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_13_itm_3 <= 1'b0; + end + else if ( core_wen & (and_dcpl_29 | FpSignedBitsToFloat_8U_23U_and_rgt | FpSignedBitsToFloat_8U_23U_and_1_rgt) + & mux_4_cse ) begin + FpAdd_8U_23U_mux_13_itm_3 <= MUX1HOT_s_1_3_2((FpSignedBitsToFloat_8U_23U_bits_sva_36[31]), + FpAdd_8U_23U_mux_1_itm_2, (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[31]), + {and_dcpl_29 , FpSignedBitsToFloat_8U_23U_and_rgt , FpSignedBitsToFloat_8U_23U_and_1_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse & mux_13_cse + ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= MUX_v_8_2_2((chn_a_rsci_d_mxwt[30:23]), (chn_b_rsci_d_mxwt[30:23]), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_1_itm_2 <= 1'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse & (mux_27_nl) + ) begin + FpAdd_8U_23U_mux_1_itm_2 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[31]), (chn_b_rsci_d_mxwt[31]), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_1_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_1_and_cse ) begin + IsNaN_8U_23U_1_nor_itm_2 <= IsNaN_8U_23U_1_nor_tmp; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + end + end + assign nl_FpMantRNE_49U_24U_else_acc_nl = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[47:25]) + + conv_u2u_1_23(FpMantRNE_49U_24U_else_carry_sva); + assign FpMantRNE_49U_24U_else_acc_nl = nl_FpMantRNE_49U_24U_else_acc_nl[22:0]; + assign FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl = MUX_v_23_2_2((FpMantRNE_49U_24U_else_acc_nl), + 23'b11111111111111111111111, FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0); + assign FpSignedBitsToFloat_8U_23U_1_and_nl = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_4) + & chn_o_rsci_d_22_0_mx0c1; + assign nl_FpAdd_8U_23U_if_4_if_acc_nl = FpAdd_8U_23U_o_expo_lpi_1_dfm_2 + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_nl = nl_FpAdd_8U_23U_if_4_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_nl = (~(FpAdd_8U_23U_and_tmp | FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_3_nl = FpAdd_8U_23U_and_tmp & (~ FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_7_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign mux_7_nl = MUX_s_1_2_2(or_tmp_3, nor_36_cse, FpAdd_8U_23U_mux_2_tmp_49); + assign nor_37_nl = ~(FpAdd_8U_23U_mux_2_tmp_49 | (~ mux_tmp_5)); + assign nor_7_nl = ~((FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]) | (~ main_stage_v_3)); + assign mux_8_nl = MUX_s_1_2_2((nor_37_nl), (mux_7_nl), nor_7_nl); + assign nor_31_nl = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 + | (~ main_stage_v_1)); + assign mux_22_nl = MUX_s_1_2_2((nor_31_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_23_nl = MUX_s_1_2_2((mux_22_nl), nor_tmp_11, nor_36_cse); + assign nor_32_nl = ~(or_tmp_16 | (~ main_stage_v_1)); + assign mux_24_nl = MUX_s_1_2_2((nor_32_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_25_nl = MUX_s_1_2_2((mux_24_nl), nor_tmp_11, nor_36_cse); + assign nor_28_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~(or_tmp_16 & main_stage_v_1))); + assign nor_29_nl = ~((~(IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp | IsNaN_8U_23U_1_nor_tmp)) + | IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_27_nl = MUX_s_1_2_2((nor_29_nl), (nor_28_nl), nor_36_cse); + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_3_2; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [2:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + MUX1HOT_v_8_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_4_2; + input [7:0] input_3; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [3:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + result = result | ( input_3 & {8{sel[3]}}); + MUX1HOT_v_8_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [48:0] MUX_v_49_2_2; + input [48:0] input_0; + input [48:0] input_1; + input [0:0] sel; + reg [48:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_49_2_2 = result; + end + endfunction + function [49:0] MUX_v_50_2_2; + input [49:0] input_0; + input [49:0] input_1; + input [0:0] sel; + reg [49:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_50_2_2 = result; + end + endfunction + function [7:0] MUX_v_8_2_2; + input [7:0] input_0; + input [7:0] input_1; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + function [0:0] readslicef_24_1_23; + input [23:0] vector; + reg [23:0] tmp; + begin + tmp = vector >> 23; + readslicef_24_1_23 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [8:0] conv_u2s_6_9 ; + input [5:0] vector ; + begin + conv_u2s_6_9 = {{3{1'b0}}, vector}; + end + endfunction + function [22:0] conv_u2u_1_23 ; + input [0:0] vector ; + begin + conv_u2u_1_23 = {{22{1'b0}}, vector}; + end + endfunction + function [8:0] conv_u2u_8_9 ; + input [7:0] vector ; + begin + conv_u2u_8_9 = {1'b0, vector}; + end + endfunction + function [23:0] conv_u2u_23_24 ; + input [22:0] vector ; + begin + conv_u2u_23_24 = {1'b0, vector}; + end + endfunction + function [49:0] conv_u2u_49_50 ; + input [48:0] vector ; + begin + conv_u2u_49_50 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add +// ------------------------------------------------------------------ +module HLS_fp32_add ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP32_ADD_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP32_ADD_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP32_ADD_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_add_core HLS_fp32_add_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_add.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_add.v.vcp new file mode 100644 index 0000000..e28c3ef --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_add.v.vcp @@ -0,0 +1,1815 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_add.v +module FP32_ADD_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_ADD_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_ADD_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP32_ADD_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_ADD_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:52:55 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_leading_sign_49_0 +// ------------------------------------------------------------------ +module FP32_ADD_leading_sign_49_0 ( + mantissa, rtn +); + input [48:0] mantissa; + output [5:0] rtn; +// Interconnect Declarations + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_12; + wire c_h_1_13; + wire c_h_1_14; + wire c_h_1_17; + wire c_h_1_20; + wire c_h_1_21; + wire c_h_1_22; + wire c_h_1_23; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[46:45]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[48:47]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[44:43]!=2'b00)); + assign c_h_1_2 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[42:41]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[38:37]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[40:39]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[36:35]!=2'b00)); + assign c_h_1_5 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[34:33]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[30:29]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[32:31]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 = ~((mantissa[28:27]!=2'b00)); + assign c_h_1_9 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3 = (mantissa[26:25]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 = ~((mantissa[24:23]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 = ~((mantissa[20:19]!=2'b00)); + assign c_h_1_12 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + assign c_h_1_13 = c_h_1_9 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + assign c_h_1_14 = c_h_1_6 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5 = (mantissa[18:17]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 & c_h_1_12 & c_h_1_13; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 = ~((mantissa[16:15]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 = ~((mantissa[12:11]!=2'b00)); + assign c_h_1_17 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3 = (mantissa[10:9]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 = ~((mantissa[8:7]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 = ~((mantissa[4:3]!=2'b00)); + assign c_h_1_20 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + assign c_h_1_21 = c_h_1_17 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4 = (mantissa[2:1]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 & c_h_1_20; + assign c_h_1_22 = c_h_1_21 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + assign c_h_1_23 = c_h_1_14 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl = c_h_1_14 & (c_h_1_22 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl = c_h_1_6 & (c_h_1_13 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4)) & (~((~(c_h_1_21 + & (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4))) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl = c_h_1_2 & (c_h_1_5 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3)) & (~((~(c_h_1_9 + & (c_h_1_12 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3)))) + & c_h_1_14)) & (~(((~(c_h_1_17 & (c_h_1_20 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2)) & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2)))) + & c_h_1_13)))) & c_h_1_14)) & (~(((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2)))) & c_h_1_21)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl + = ((~((mantissa[48]) | (~((mantissa[47:46]!=2'b01))))) & (~(((mantissa[44]) + | (~((mantissa[43:42]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[40]) | (~((mantissa[39:38]!=2'b01))))) + & (~(((mantissa[36]) | (~((mantissa[35:34]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[32]) | (~((mantissa[31:30]!=2'b01))))) & (~(((mantissa[28]) + | (~((mantissa[27:26]!=2'b01)))) & c_h_1_9)) & (~((~((~((mantissa[24]) | (~((mantissa[23:22]!=2'b01))))) + & (~(((mantissa[20]) | (~((mantissa[19:18]!=2'b01)))) & c_h_1_12)))) & c_h_1_13)))) + & c_h_1_14)) & (~(((~((~((mantissa[16]) | (~((mantissa[15:14]!=2'b01))))) & + (~(((mantissa[12]) | (~((mantissa[11:10]!=2'b01)))) & c_h_1_17)) & (~((~((~((mantissa[8]) + | (~((mantissa[7:6]!=2'b01))))) & (~(((mantissa[4]) | (~((mantissa[3:2]!=2'b01)))) + & c_h_1_20)))) & c_h_1_21)))) | c_h_1_22) & c_h_1_23))) | ((~ (mantissa[0])) + & c_h_1_22 & c_h_1_23); + assign rtn = {c_h_1_23 , (IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:53:04 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_ADD_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP32_ADD_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_ADD_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_ADD_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_add_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_add_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_add_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_add_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [31:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [31:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [31:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_32_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 32'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_ADD_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_add_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_add_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [31:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [31:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp32_add_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp HLS_fp32_add_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_add_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_ADD_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_add_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_add_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add_core +// ------------------------------------------------------------------ +module HLS_fp32_add_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [31:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [7:0] chn_o_rsci_d_30_23; + reg [22:0] chn_o_rsci_d_22_0; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + wire FpAdd_8U_23U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_49U_24U_else_and_tmp; + wire IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + wire IsNaN_8U_23U_1_nor_tmp; + wire nor_tmp_1; + wire or_tmp_3; + wire mux_tmp_5; + wire nor_tmp_11; + wire or_tmp_16; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire and_dcpl_29; + wire and_dcpl_33; + wire or_tmp_29; + wire or_tmp_35; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_4; + reg [31:0] FpSignedBitsToFloat_8U_23U_bits_sva_36; + reg [31:0] FpSignedBitsToFloat_8U_23U_bits_1_sva_36; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_4; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_6; + reg [48:0] FpAdd_8U_23U_a_int_mant_p1_sva_2; + reg [48:0] FpAdd_8U_23U_b_int_mant_p1_sva_2; + reg FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3; + reg [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2; + reg IsNaN_8U_23U_land_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_6; + reg FpAdd_8U_23U_IsZero_8U_23U_or_itm_2; + reg FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2; + reg FpNormalize_8U_49U_if_or_itm_2; + reg IsNaN_8U_23U_1_nor_itm_2; + reg IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4; + reg FpAdd_8U_23U_mux_1_itm_2; + reg FpAdd_8U_23U_mux_13_itm_3; + reg FpAdd_8U_23U_mux_13_itm_4; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4; + reg IsNaN_8U_23U_land_lpi_1_dfm_st_4; + wire FpAdd_8U_23U_mux_2_tmp_49; + wire main_stage_en_1; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm; + wire [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + wire [7:0] FpAdd_8U_23U_o_expo_lpi_1_dfm_2; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_36_cse; + wire FpAdd_8U_23U_or_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + wire FpSignedBitsToFloat_8U_23U_and_rgt; + wire FpSignedBitsToFloat_8U_23U_and_1_rgt; + wire [48:0] FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + wire [48:0] FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + wire [48:0] FpNormalize_8U_49U_else_lshift_itm; + wire chn_o_rsci_d_22_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + wire [48:0] FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0; + wire [48:0] FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [49:0] FpAdd_8U_23U_asn_5_mx0w0; + wire [50:0] nl_FpAdd_8U_23U_asn_5_mx0w0; + wire [49:0] FpAdd_8U_23U_asn_4_mx0w1; + wire [51:0] nl_FpAdd_8U_23U_asn_4_mx0w1; + wire [48:0] FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0; + wire FpMantRNE_49U_24U_else_carry_sva; + wire FpAdd_8U_23U_and_tmp; + wire [7:0] FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm; + wire [7:0] FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm; + wire FpNormalize_8U_49U_oelse_not_3; + wire [5:0] libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1; + wire FpAdd_8U_23U_is_addition_and_cse; + wire FpAdd_8U_23U_and_8_cse; + wire IsNaN_8U_23U_aelse_and_cse; + wire FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse; + wire FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse; + wire IsNaN_8U_23U_1_and_cse; + reg reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse; + wire mux_13_cse; + wire mux_4_cse; + wire FpSignedBitsToFloat_8U_23U_1_and_1_cse; + wire FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + wire FpAdd_8U_23U_if_3_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_if_4_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1; + wire[22:0] FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl; + wire[22:0] FpMantRNE_49U_24U_else_acc_nl; + wire[23:0] nl_FpMantRNE_49U_24U_else_acc_nl; + wire[0:0] FpSignedBitsToFloat_8U_23U_1_and_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_nl; + wire[0:0] FpAdd_8U_23U_and_3_nl; + wire[0:0] FpAdd_8U_23U_and_7_nl; + wire[0:0] mux_6_nl; + wire[0:0] mux_8_nl; + wire[0:0] mux_7_nl; + wire[0:0] nor_37_nl; + wire[0:0] nor_7_nl; + wire[0:0] mux_10_nl; + wire[0:0] or_10_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_34_nl; + wire[0:0] and_67_nl; + wire[0:0] mux_23_nl; + wire[0:0] mux_22_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_25_nl; + wire[0:0] mux_24_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_27_nl; + wire[0:0] nor_28_nl; + wire[0:0] nor_29_nl; + wire[0:0] mux_28_nl; + wire[0:0] nor_26_nl; + wire[0:0] nor_27_nl; + wire[8:0] FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[10:0] nl_FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[7:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl; + wire[7:0] FpNormalize_8U_49U_else_acc_nl; + wire[9:0] nl_FpNormalize_8U_49U_else_acc_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_1_nl; + wire[0:0] FpAdd_8U_23U_and_2_nl; + wire[48:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl; + wire[0:0] FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[7:0] FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[7:0] FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[0:0] FpAdd_8U_23U_is_a_greater_oelse_not_5_nl; + wire[8:0] FpNormalize_8U_49U_acc_nl; + wire[10:0] nl_FpNormalize_8U_49U_acc_nl; + wire[0:0] nor_38_nl; + wire[23:0] FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; + wire[25:0] nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 + , (FpSignedBitsToFloat_8U_23U_bits_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_a_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_a_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_a_left_shift_acc_nl = nl_FpAdd_8U_23U_a_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_a_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[0]))}; + wire [23:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 + , (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_b_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_b_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_b_left_shift_acc_nl = nl_FpAdd_8U_23U_b_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_b_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[0]))}; + wire [48:0] nl_FpNormalize_8U_49U_else_lshift_rg_a; + assign nl_FpNormalize_8U_49U_else_lshift_rg_a = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [48:0] nl_leading_sign_49_0_rg_mantissa; + assign nl_leading_sign_49_0_rg_mantissa = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [31:0] nl_HLS_fp32_add_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_add_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 , chn_o_rsci_d_30_23 + , chn_o_rsci_d_22_0}; + FP32_ADD_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_a_int_mant_p1_lshift_itm) + ); + FP32_ADD_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_b_int_mant_p1_lshift_itm) + ); + FP32_ADD_mgc_shift_l_v4 #(.width_a(32'sd49), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd49)) FpNormalize_8U_49U_else_lshift_rg ( + .a(nl_FpNormalize_8U_49U_else_lshift_rg_a[48:0]), + .s(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1), + .z(FpNormalize_8U_49U_else_lshift_itm) + ); + FP32_ADD_leading_sign_49_0 leading_sign_49_0_rg ( + .mantissa(nl_leading_sign_49_0_rg_mantissa[48:0]), + .rtn(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + ); + HLS_fp32_add_core_chn_a_rsci HLS_fp32_add_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_add_core_chn_b_rsci HLS_fp32_add_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp32_add_core_chn_o_rsci HLS_fp32_add_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_add_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp32_add_core_staller HLS_fp32_add_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_add_core_core_fsm HLS_fp32_add_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_8U_23U_or_cse = IsNaN_8U_23U_1_land_lpi_1_dfm_4 | IsNaN_8U_23U_land_lpi_1_dfm_6; + assign IsNaN_8U_23U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_13_cse; + assign FpAdd_8U_23U_is_addition_and_cse = core_wen & (~ and_dcpl_7) & mux_4_cse; + assign mux_4_cse = MUX_s_1_2_2(main_stage_v_1, main_stage_v_2, nor_36_cse); + assign mux_6_nl = MUX_s_1_2_2(mux_tmp_5, or_tmp_3, main_stage_v_3); + assign FpAdd_8U_23U_and_8_cse = core_wen & (~ and_dcpl_7) & (mux_6_nl); + assign nor_36_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_10_nl = nor_36_cse | nor_tmp_11; + assign nor_34_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_11)); + assign mux_9_nl = MUX_s_1_2_2((nor_34_nl), nor_tmp_11, chn_o_rsci_bawt); + assign and_67_nl = FpAdd_8U_23U_or_cse & main_stage_v_3; + assign mux_10_nl = MUX_s_1_2_2((mux_9_nl), (or_10_nl), and_67_nl); + assign FpSignedBitsToFloat_8U_23U_1_and_1_cse = core_wen & (~ and_dcpl_7) & (mux_10_nl); + assign FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse = ((~ FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1) + & FpAdd_8U_23U_is_a_greater_oif_equal_tmp) | FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + assign mux_13_cse = MUX_s_1_2_2(nor_tmp_1, main_stage_v_1, nor_36_cse); + assign FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse = and_dcpl_28 + | and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_and_rgt = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0) + & and_dcpl_28; + assign FpSignedBitsToFloat_8U_23U_and_1_rgt = IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 + & and_dcpl_28; + assign FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse = (FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse + & or_cse) | and_dcpl_33; + assign nor_26_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~ main_stage_v_1)); + assign nor_27_nl = ~(IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_28_nl = MUX_s_1_2_2((nor_27_nl), (nor_26_nl), nor_36_cse); + assign IsNaN_8U_23U_1_and_cse = core_wen & (~ and_dcpl_7) & (mux_28_nl); + assign IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000))) + | (chn_a_rsci_d_mxwt[30:23]!=8'b11111111)); + assign FpAdd_8U_23U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[30:23]) == + (chn_b_rsci_d_mxwt[30:23]); + assign IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2); + assign IsNaN_8U_23U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp = ~((chn_b_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpAdd_8U_23U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[30:23])}) + + conv_u2u_8_9(~ (chn_a_rsci_d_mxwt[30:23])) + 9'b1; + assign FpAdd_8U_23U_is_a_greater_acc_1_nl = nl_FpAdd_8U_23U_is_a_greater_acc_1_nl[8:0]; + assign FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1 = readslicef_9_1_8((FpAdd_8U_23U_is_a_greater_acc_1_nl)); + assign FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_b_int_mant_p1_sva_2, + FpAdd_8U_23U_a_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_a_int_mant_p1_sva_2, + FpAdd_8U_23U_b_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign nl_FpAdd_8U_23U_asn_5_mx0w0 = conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + + conv_u2u_49_50(FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0); + assign FpAdd_8U_23U_asn_5_mx0w0 = nl_FpAdd_8U_23U_asn_5_mx0w0[49:0]; + assign nl_FpAdd_8U_23U_asn_4_mx0w1 = ({1'b1 , (~ FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0)}) + + conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + 50'b1; + assign FpAdd_8U_23U_asn_4_mx0w1 = nl_FpAdd_8U_23U_asn_4_mx0w1[49:0]; + assign FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0 = MUX_v_50_2_2(FpAdd_8U_23U_asn_4_mx0w1, + FpAdd_8U_23U_asn_5_mx0w0, reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse); + assign nl_FpAdd_8U_23U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_qr_lpi_1_dfm_6[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_1_nl = nl_FpAdd_8U_23U_if_3_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_3_if_acc_1_nl)); + assign nl_FpNormalize_8U_49U_else_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + ({2'b11 + , (~ libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1)}) + + 8'b1; + assign FpNormalize_8U_49U_else_acc_nl = nl_FpNormalize_8U_49U_else_acc_nl[7:0]; + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl = MUX_v_8_2_2(8'b00000000, + (FpNormalize_8U_49U_else_acc_nl), FpNormalize_8U_49U_oelse_not_3); + assign nl_FpAdd_8U_23U_if_3_if_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_nl = nl_FpAdd_8U_23U_if_3_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_1_nl = (~ FpAdd_8U_23U_if_3_if_acc_1_itm_7_1) & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_and_2_nl = FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_o_expo_lpi_1_dfm_2 = MUX1HOT_v_8_3_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl), + FpAdd_8U_23U_qr_lpi_1_dfm_6, (FpAdd_8U_23U_if_3_if_acc_nl), {(~ (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49])) + , (FpAdd_8U_23U_and_1_nl) , (FpAdd_8U_23U_and_2_nl)}); + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl = MUX_v_49_2_2(49'b0000000000000000000000000000000000000000000000000, + FpNormalize_8U_49U_else_lshift_itm, FpNormalize_8U_49U_oelse_not_3); + assign FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0 = MUX_v_49_2_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl), + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49:1]), FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpMantRNE_49U_24U_else_carry_sva = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[24]) + & ((FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[0]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[1]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[2]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[3]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[4]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[5]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[6]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[7]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[8]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[9]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[10]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[11]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[12]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[13]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[14]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[15]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[16]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[17]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[18]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[19]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[20]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[21]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[22]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[23]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[25])); + assign FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm + | (~ FpAdd_8U_23U_if_4_if_acc_1_itm_7_1); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_8U_23U_is_inf_lpi_1_dfm, + (FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl), FpMantRNE_49U_24U_else_and_tmp); + assign nl_FpAdd_8U_23U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_o_expo_lpi_1_dfm_2[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_1_nl = nl_FpAdd_8U_23U_if_4_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_4_if_acc_1_nl)); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm = ~(FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 | (~ + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]))); + assign FpAdd_8U_23U_and_tmp = FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 & FpMantRNE_49U_24U_else_and_tmp; + assign FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c = ~(IsNaN_8U_23U_1_land_lpi_1_dfm_4 + | IsNaN_8U_23U_land_lpi_1_dfm_6); + assign FpMantRNE_49U_24U_else_and_tmp = FpMantRNE_49U_24U_else_carry_sva & (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[48:25]==24'b111111111111111111111111); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_cse; + assign nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl = (FpSignedBitsToFloat_8U_23U_bits_sva_36[30:23]) + - (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[30:23]); + assign FpAdd_8U_23U_b_right_shift_qif_acc_nl = nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl[7:0]; + assign FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_b_right_shift_qif_acc_nl), + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4); + assign nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl = (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[30:23]) + - (FpSignedBitsToFloat_8U_23U_bits_sva_36[30:23]); + assign FpAdd_8U_23U_a_right_shift_qelse_acc_nl = nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl[7:0]; + assign FpAdd_8U_23U_is_a_greater_oelse_not_5_nl = ~ FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + assign FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_a_right_shift_qelse_acc_nl), + (FpAdd_8U_23U_is_a_greater_oelse_not_5_nl)); + assign nl_FpNormalize_8U_49U_acc_nl = ({1'b1 , (~ FpAdd_8U_23U_qr_lpi_1_dfm_6)}) + + conv_u2s_6_9(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + + 9'b1; + assign FpNormalize_8U_49U_acc_nl = nl_FpNormalize_8U_49U_acc_nl[8:0]; + assign FpNormalize_8U_49U_oelse_not_3 = FpNormalize_8U_49U_if_or_itm_2 & (readslicef_9_1_8((FpNormalize_8U_49U_acc_nl))); + assign FpAdd_8U_23U_mux_2_tmp_49 = MUX_s_1_2_2((FpAdd_8U_23U_asn_4_mx0w1[49]), + (FpAdd_8U_23U_asn_5_mx0w0[49]), reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse); + assign nor_tmp_1 = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_tmp_3 = nor_36_cse | main_stage_v_2; + assign nor_38_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_tmp_5 = MUX_s_1_2_2((nor_38_nl), main_stage_v_2, chn_o_rsci_bawt); + assign nor_tmp_11 = (IsNaN_8U_23U_1_land_lpi_1_dfm_3 | IsNaN_8U_23U_land_lpi_1_dfm_5) + & main_stage_v_2; + assign or_tmp_16 = IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign and_dcpl_28 = or_cse & (~ IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign and_dcpl_29 = or_cse & IsNaN_8U_23U_land_lpi_1_dfm_st_4; + assign and_dcpl_33 = or_cse & (~ FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1) & (FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 + | (~ FpAdd_8U_23U_is_a_greater_oif_equal_tmp)); + assign or_tmp_29 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_35 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_cse & (fsm_output[1]); + assign chn_o_rsci_d_22_0_mx0c1 = or_cse & main_stage_v_3 & (~ IsNaN_8U_23U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_b_rsci_bawt & chn_a_rsci_bawt)) & main_stage_v_1 + & or_cse; + assign main_stage_v_2_mx0c1 = main_stage_v_2 & (~ main_stage_v_1) & or_cse; + assign main_stage_v_3_mx0c1 = or_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[22:0])}) + + conv_u2u_23_24(~ (chn_b_rsci_d_mxwt[22:0])) + 24'b1; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl[23:0]; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 = readslicef_24_1_23((FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_35; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_29 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_29; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_0 <= 23'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_3 & IsNaN_8U_23U_land_lpi_1_dfm_6) + | chn_o_rsci_d_22_0_mx0c1) ) begin + chn_o_rsci_d_22_0 <= MUX_v_23_2_2(FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4, + (FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl), FpSignedBitsToFloat_8U_23U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_23 <= 8'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_30_23 <= MUX1HOT_v_8_4_2(FpAdd_8U_23U_o_expo_lpi_1_dfm_2, (FpAdd_8U_23U_if_4_if_acc_nl), + 8'b11111110, FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4, + {(FpAdd_8U_23U_and_nl) , (FpAdd_8U_23U_and_3_nl) , (FpAdd_8U_23U_and_7_nl) + , FpAdd_8U_23U_or_cse}); + chn_o_rsci_d_31 <= FpAdd_8U_23U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_35 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= 1'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3 <= 1'b0; + FpSignedBitsToFloat_8U_23U_bits_sva_36 <= 32'b0; + FpSignedBitsToFloat_8U_23U_bits_1_sva_36 <= 32'b0; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= 1'b0; + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_aelse_and_cse ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3 <= ~((chn_a_rsci_d_mxwt[31]) + ^ (chn_b_rsci_d_mxwt[31])); + FpSignedBitsToFloat_8U_23U_bits_sva_36 <= chn_a_rsci_d_mxwt; + FpSignedBitsToFloat_8U_23U_bits_1_sva_36 <= chn_b_rsci_d_mxwt; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= (chn_a_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse <= 1'b0; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= 1'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= 1'b0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= 8'b0; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= 1'b0; + end + else if ( FpAdd_8U_23U_is_addition_and_cse ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_2_cse <= FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xnor_svs_3; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= FpAdd_8U_23U_qr_lpi_1_dfm_4; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= IsNaN_8U_23U_land_lpi_1_dfm_st_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_2) | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= 8'b0; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= 50'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_mux_13_itm_4 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= 1'b0; + end + else if ( FpAdd_8U_23U_and_8_cse ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= FpAdd_8U_23U_qr_lpi_1_dfm_5; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= IsNaN_8U_23U_1_land_lpi_1_dfm_3; + FpAdd_8U_23U_mux_13_itm_4 <= FpAdd_8U_23U_mux_13_itm_3; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= IsNaN_8U_23U_land_lpi_1_dfm_5; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpNormalize_8U_49U_if_or_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_8_nl) ) begin + FpNormalize_8U_49U_if_or_itm_2 <= (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0[48:0]!=49'b0000000000000000000000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= 23'b0; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= 8'b0; + end + else if ( FpSignedBitsToFloat_8U_23U_1_and_1_cse ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= 23'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_23_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= MUX_v_23_2_2((FpSignedBitsToFloat_8U_23U_bits_1_sva_36[22:0]), (FpSignedBitsToFloat_8U_23U_bits_sva_36[22:0]), + and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_25_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= MUX_v_8_2_2((FpSignedBitsToFloat_8U_23U_bits_1_sva_36[30:23]), (FpSignedBitsToFloat_8U_23U_bits_sva_36[30:23]), + and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_13_itm_3 <= 1'b0; + end + else if ( core_wen & (and_dcpl_29 | FpSignedBitsToFloat_8U_23U_and_rgt | FpSignedBitsToFloat_8U_23U_and_1_rgt) + & mux_4_cse ) begin + FpAdd_8U_23U_mux_13_itm_3 <= MUX1HOT_s_1_3_2((FpSignedBitsToFloat_8U_23U_bits_sva_36[31]), + FpAdd_8U_23U_mux_1_itm_2, (FpSignedBitsToFloat_8U_23U_bits_1_sva_36[31]), + {and_dcpl_29 , FpSignedBitsToFloat_8U_23U_and_rgt , FpSignedBitsToFloat_8U_23U_and_1_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse & mux_13_cse + ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= MUX_v_8_2_2((chn_a_rsci_d_mxwt[30:23]), (chn_b_rsci_d_mxwt[30:23]), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_1_itm_2 <= 1'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_FpAdd_8U_23U_or_1_cse & (mux_27_nl) + ) begin + FpAdd_8U_23U_mux_1_itm_2 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[31]), (chn_b_rsci_d_mxwt[31]), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_1_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_1_and_cse ) begin + IsNaN_8U_23U_1_nor_itm_2 <= IsNaN_8U_23U_1_nor_tmp; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + end + end + assign nl_FpMantRNE_49U_24U_else_acc_nl = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[47:25]) + + conv_u2u_1_23(FpMantRNE_49U_24U_else_carry_sva); + assign FpMantRNE_49U_24U_else_acc_nl = nl_FpMantRNE_49U_24U_else_acc_nl[22:0]; + assign FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl = MUX_v_23_2_2((FpMantRNE_49U_24U_else_acc_nl), + 23'b11111111111111111111111, FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0); + assign FpSignedBitsToFloat_8U_23U_1_and_nl = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_4) + & chn_o_rsci_d_22_0_mx0c1; + assign nl_FpAdd_8U_23U_if_4_if_acc_nl = FpAdd_8U_23U_o_expo_lpi_1_dfm_2 + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_nl = nl_FpAdd_8U_23U_if_4_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_nl = (~(FpAdd_8U_23U_and_tmp | FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_3_nl = FpAdd_8U_23U_and_tmp & (~ FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_7_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign mux_7_nl = MUX_s_1_2_2(or_tmp_3, nor_36_cse, FpAdd_8U_23U_mux_2_tmp_49); + assign nor_37_nl = ~(FpAdd_8U_23U_mux_2_tmp_49 | (~ mux_tmp_5)); + assign nor_7_nl = ~((FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]) | (~ main_stage_v_3)); + assign mux_8_nl = MUX_s_1_2_2((nor_37_nl), (mux_7_nl), nor_7_nl); + assign nor_31_nl = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 + | (~ main_stage_v_1)); + assign mux_22_nl = MUX_s_1_2_2((nor_31_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_23_nl = MUX_s_1_2_2((mux_22_nl), nor_tmp_11, nor_36_cse); + assign nor_32_nl = ~(or_tmp_16 | (~ main_stage_v_1)); + assign mux_24_nl = MUX_s_1_2_2((nor_32_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_25_nl = MUX_s_1_2_2((mux_24_nl), nor_tmp_11, nor_36_cse); + assign nor_28_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~(or_tmp_16 & main_stage_v_1))); + assign nor_29_nl = ~((~(IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp | IsNaN_8U_23U_1_nor_tmp)) + | IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_27_nl = MUX_s_1_2_2((nor_29_nl), (nor_28_nl), nor_36_cse); + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_3_2; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [2:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + MUX1HOT_v_8_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_4_2; + input [7:0] input_3; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [3:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + result = result | ( input_3 & {8{sel[3]}}); + MUX1HOT_v_8_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [48:0] MUX_v_49_2_2; + input [48:0] input_0; + input [48:0] input_1; + input [0:0] sel; + reg [48:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_49_2_2 = result; + end + endfunction + function [49:0] MUX_v_50_2_2; + input [49:0] input_0; + input [49:0] input_1; + input [0:0] sel; + reg [49:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_50_2_2 = result; + end + endfunction + function [7:0] MUX_v_8_2_2; + input [7:0] input_0; + input [7:0] input_1; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + function [0:0] readslicef_24_1_23; + input [23:0] vector; + reg [23:0] tmp; + begin + tmp = vector >> 23; + readslicef_24_1_23 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [8:0] conv_u2s_6_9 ; + input [5:0] vector ; + begin + conv_u2s_6_9 = {{3{1'b0}}, vector}; + end + endfunction + function [22:0] conv_u2u_1_23 ; + input [0:0] vector ; + begin + conv_u2u_1_23 = {{22{1'b0}}, vector}; + end + endfunction + function [8:0] conv_u2u_8_9 ; + input [7:0] vector ; + begin + conv_u2u_8_9 = {1'b0, vector}; + end + endfunction + function [23:0] conv_u2u_23_24 ; + input [22:0] vector ; + begin + conv_u2u_23_24 = {1'b0, vector}; + end + endfunction + function [49:0] conv_u2u_49_50 ; + input [48:0] vector ; + begin + conv_u2u_49_50 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_add +// ------------------------------------------------------------------ +module HLS_fp32_add ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP32_ADD_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP32_ADD_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP32_ADD_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_add_core HLS_fp32_add_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_mul.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_mul.v new file mode 100644 index 0000000..f82c5ee --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_mul.v @@ -0,0 +1,1536 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_mul.v +module FP32_MUL_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_MUL_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_MUL_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:53:54 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_MUL_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_MUL_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_MUL_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP32_MUL_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_MUL_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_MUL_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_mul_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_mul_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [31:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [31:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [31:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_32_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 32'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_MUL_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [31:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [31:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core +// ------------------------------------------------------------------ +module HLS_fp32_mul_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [31:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [7:0] chn_o_rsci_d_30_23; + reg [22:0] chn_o_rsci_d_22_0; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_nor_tmp; + wire FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp; + wire [47:0] FpMul_8U_23U_p_mant_p1_mul_tmp; + wire IsNaN_8U_23U_1_nor_tmp; + wire mux_tmp; + wire mux_tmp_1; + wire or_tmp_24; + wire mux_tmp_4; + wire not_tmp_9; + wire or_tmp_32; + wire mux_tmp_9; + wire mux_tmp_10; + wire or_tmp_36; + wire mux_tmp_14; + wire or_tmp_51; + wire and_dcpl_3; + wire and_dcpl_6; + wire and_dcpl_12; + wire and_dcpl_13; + wire and_dcpl_16; + wire and_dcpl_26; + wire or_tmp_55; + wire or_tmp_59; + wire or_tmp_65; + reg FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs; + reg [47:0] FpMul_8U_23U_p_mant_p1_sva; + reg main_stage_v_1; + reg main_stage_v_2; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_4; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_3; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_4; + reg FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2; + reg [47:0] FpMul_8U_23U_p_mant_p1_sva_2; + reg [7:0] FpMul_8U_23U_p_expo_sva_5; + wire [8:0] nl_FpMul_8U_23U_p_expo_sva_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_4; + reg [7:0] FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2; + reg [7:0] FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2; + reg FpMul_8U_23U_mux_10_itm_3; + reg FpMul_8U_23U_mux_10_itm_4; + reg [22:0] FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_st_4; + reg FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2; + reg FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2; + reg IsNaN_8U_23U_land_lpi_1_dfm_st_3; + reg [30:0] FpMul_8U_23U_ua_sva_1_30_0_1; + reg [30:0] FpMul_8U_23U_ub_sva_1_30_0_1; + wire main_stage_en_1; + wire FpMantRNE_48U_24U_else_and_svs; + wire FpMul_8U_23U_is_inf_lpi_1_dfm_2; + wire FpMantRNE_48U_24U_else_carry_sva; + wire [7:0] FpMul_8U_23U_o_expo_lpi_1_dfm; + wire FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp; + wire [7:0] FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1; + wire [8:0] nl_FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1; + wire [45:0] FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_10_cse; + wire nand_8_cse; + wire nand_cse; + wire or_45_cse; + wire FpMul_8U_23U_or_2_cse; + wire nor_4_cse; + wire and_cse; + wire or_65_cse; + wire or_29_cse; + wire mux_24_cse; + wire and_41_rgt; + wire and_45_rgt; + wire and_54_rgt; + wire and_64_rgt; + wire and_65_rgt; + wire mux_20_itm; + wire chn_o_rsci_d_30_23_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire [7:0] FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0; + wire FpMul_8U_23U_lor_2_lpi_1_dfm; + wire IsNaN_8U_23U_aelse_and_cse; + wire IsNaN_8U_23U_1_aelse_and_cse; + wire FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse; + wire FpMul_8U_23U_else_2_if_acc_itm_8_1; + wire FpMul_8U_23U_oelse_1_acc_itm_9_1; + wire FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[22:0] FpMul_8U_23U_FpMul_8U_23U_FpMul_8U_23U_nor_1_nl; + wire[22:0] FpMul_8U_23U_nor_nl; + wire[22:0] mux_34_nl; + wire[22:0] FpMantRNE_48U_24U_else_acc_nl; + wire[23:0] nl_FpMantRNE_48U_24U_else_acc_nl; + wire[0:0] or_nl; + wire[7:0] FpMul_8U_23U_FpMul_8U_23U_and_2_nl; + wire[0:0] FpMul_8U_23U_oelse_2_not_1_nl; + wire[0:0] FpBitsToFloat_8U_23U_1_and_nl; + wire[8:0] FpMul_8U_23U_else_2_acc_1_nl; + wire[9:0] nl_FpMul_8U_23U_else_2_acc_1_nl; + wire[7:0] FpMul_8U_23U_else_2_else_acc_2_nl; + wire[8:0] nl_FpMul_8U_23U_else_2_else_acc_2_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_24_nl; + wire[0:0] mux_2_nl; + wire[0:0] nor_26_nl; + wire[0:0] nor_27_nl; + wire[0:0] mux_6_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_5_nl; + wire[0:0] or_25_nl; + wire[0:0] mux_8_nl; + wire[0:0] nor_23_nl; + wire[0:0] mux_7_nl; + wire[0:0] mux_13_nl; + wire[0:0] mux_12_nl; + wire[0:0] mux_11_nl; + wire[0:0] or_33_nl; + wire[0:0] and_10_nl; + wire[0:0] mux_17_nl; + wire[0:0] mux_16_nl; + wire[0:0] mux_15_nl; + wire[0:0] and_11_nl; + wire[0:0] mux_23_nl; + wire[0:0] mux_22_nl; + wire[0:0] and_93_nl; + wire[0:0] nor_21_nl; + wire[0:0] mux_33_nl; + wire[0:0] and_90_nl; + wire[0:0] FpMul_8U_23U_xor_1_nl; + wire[0:0] and_95_nl; + wire[0:0] mux_28_nl; + wire[0:0] mux_25_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_27_nl; + wire[0:0] mux_26_nl; + wire[0:0] mux_31_nl; + wire[0:0] mux_30_nl; + wire[0:0] mux_29_nl; + wire[0:0] and_91_nl; + wire[0:0] nand_6_nl; + wire[8:0] FpMul_8U_23U_else_2_if_acc_nl; + wire[9:0] nl_FpMul_8U_23U_else_2_if_acc_nl; + wire[9:0] FpMul_8U_23U_oelse_1_acc_nl; + wire[10:0] nl_FpMul_8U_23U_oelse_1_acc_nl; + wire[8:0] FpMul_8U_23U_oelse_1_acc_1_nl; + wire[9:0] nl_FpMul_8U_23U_oelse_1_acc_1_nl; + wire[7:0] FpMul_8U_23U_else_2_else_if_if_acc_1_nl; + wire[8:0] nl_FpMul_8U_23U_else_2_else_if_if_acc_1_nl; + wire[7:0] FpMul_8U_23U_else_2_else_if_if_acc_nl; + wire[8:0] nl_FpMul_8U_23U_else_2_else_if_if_acc_nl; + wire[0:0] asn_FpMul_8U_23U_p_expo_lpi_1_dfm_1_FpMul_8U_23U_else_2_else_and_nl; + wire[0:0] FpMul_8U_23U_FpMul_8U_23U_nor_1_nl; + wire[0:0] FpMul_8U_23U_or_1_nl; + wire[0:0] FpMantWidthDec_8U_47U_23U_0U_0U_and_1_nl; + wire[0:0] or_3_nl; + wire[0:0] nor_nl; + wire[0:0] or_1_nl; + wire[0:0] or_7_nl; + wire[0:0] nor_28_nl; + wire[0:0] or_22_nl; + wire[0:0] nor_22_nl; + wire[0:0] or_39_nl; + wire[0:0] mux_19_nl; + wire[0:0] mux_18_nl; +// Interconnect Declarations for Component Instantiations + wire [31:0] nl_HLS_fp32_mul_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_mul_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 , chn_o_rsci_d_30_23 + , chn_o_rsci_d_22_0}; + HLS_fp32_mul_core_chn_a_rsci HLS_fp32_mul_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_mul_core_chn_b_rsci HLS_fp32_mul_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp32_mul_core_chn_o_rsci HLS_fp32_mul_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_mul_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp32_mul_core_staller HLS_fp32_mul_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_mul_core_core_fsm HLS_fp32_mul_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, main_stage_en_1 & (fsm_output[1]))), fsm_output[1]); +// assert(iMantWidth > oMantWidth) - ../include/nvdla_float.h: line 386 +// PSL HLS_fp32_mul_core_nvdla_float_h_ln386_assert_iMantWidth_gt_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_6 | (~ main_stage_v_2))); + assign FpMul_8U_23U_or_2_cse = IsNaN_8U_23U_1_land_lpi_1_dfm_4 | IsNaN_8U_23U_land_lpi_1_dfm_4; + assign IsNaN_8U_23U_aelse_and_cse = core_wen & (~ and_dcpl_6) & mux_tmp_1; + assign or_10_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign and_41_rgt = or_10_cse & or_29_cse; + assign or_29_cse = (~ FpMul_8U_23U_else_2_if_acc_itm_8_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + assign nor_4_cse = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_3 | (~ IsNaN_8U_23U_1_land_lpi_1_dfm_3)); + assign FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse = (or_10_cse & (~ IsNaN_8U_23U_land_lpi_1_dfm_st_3)) + | and_dcpl_26; + assign IsNaN_8U_23U_1_aelse_and_cse = core_wen & (~ and_dcpl_6) & mux_tmp_4; + assign and_45_rgt = or_10_cse & FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + assign or_65_cse = (~ main_stage_v_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + assign nand_8_cse = ~((chn_b_rsci_d_mxwt[30:23]==8'b11111111)); + assign nand_cse = ~((chn_a_rsci_d_mxwt[30:23]==8'b11111111)); + assign and_54_rgt = or_10_cse & (chn_a_rsci_d_mxwt[30:23]==8'b11111111) & (~ IsNaN_8U_23U_nor_tmp); + assign and_64_rgt = ((chn_a_rsci_d_mxwt[30:23]!=8'b11111111) | IsNaN_8U_23U_nor_tmp) + & (chn_b_rsci_d_mxwt[30:23]==8'b11111111) & (~ IsNaN_8U_23U_1_nor_tmp) & or_10_cse; + assign and_90_nl = nand_cse & or_tmp_55; + assign mux_33_nl = MUX_s_1_2_2((and_90_nl), or_tmp_55, IsNaN_8U_23U_nor_tmp); + assign and_65_rgt = (mux_33_nl) & or_10_cse; + assign or_45_cse = FpMul_8U_23U_oelse_1_acc_itm_9_1 | FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp; + assign and_95_nl = nand_cse & and_cse; + assign mux_24_cse = MUX_s_1_2_2((and_95_nl), and_cse, IsNaN_8U_23U_nor_tmp); + assign IsNaN_8U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign FpMul_8U_23U_p_mant_p1_mul_tmp = conv_u2u_48_48(({1'b1 , (FpMul_8U_23U_ua_sva_1_30_0_1[22:0])}) + * ({1'b1 , (FpMul_8U_23U_ub_sva_1_30_0_1[22:0])})); + assign nl_FpMul_8U_23U_else_2_if_acc_nl = conv_u2u_8_9(FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2) + + 9'b101000001; + assign FpMul_8U_23U_else_2_if_acc_nl = nl_FpMul_8U_23U_else_2_if_acc_nl[8:0]; + assign FpMul_8U_23U_else_2_if_acc_itm_8_1 = readslicef_9_1_8((FpMul_8U_23U_else_2_if_acc_nl)); + assign IsNaN_8U_23U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign nl_FpMul_8U_23U_oelse_1_acc_1_nl = conv_u2s_8_9(chn_b_rsci_d_mxwt[30:23]) + + 9'b110000001; + assign FpMul_8U_23U_oelse_1_acc_1_nl = nl_FpMul_8U_23U_oelse_1_acc_1_nl[8:0]; + assign nl_FpMul_8U_23U_oelse_1_acc_nl = conv_s2s_9_10(FpMul_8U_23U_oelse_1_acc_1_nl) + + conv_u2s_8_10(chn_a_rsci_d_mxwt[30:23]); + assign FpMul_8U_23U_oelse_1_acc_nl = nl_FpMul_8U_23U_oelse_1_acc_nl[9:0]; + assign FpMul_8U_23U_oelse_1_acc_itm_9_1 = readslicef_10_1_9((FpMul_8U_23U_oelse_1_acc_nl)); + assign FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp = (~((chn_b_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000))) + | (~((chn_a_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000))); + assign nl_FpMul_8U_23U_else_2_else_if_if_acc_1_nl = ({1'b1 , (FpMul_8U_23U_p_expo_sva_5[7:1])}) + + 8'b1; + assign FpMul_8U_23U_else_2_else_if_if_acc_1_nl = nl_FpMul_8U_23U_else_2_else_if_if_acc_1_nl[7:0]; + assign FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1 = readslicef_8_1_7((FpMul_8U_23U_else_2_else_if_if_acc_1_nl)); + assign nl_FpMul_8U_23U_else_2_else_if_if_acc_nl = FpMul_8U_23U_p_expo_sva_5 + 8'b1; + assign FpMul_8U_23U_else_2_else_if_if_acc_nl = nl_FpMul_8U_23U_else_2_else_if_if_acc_nl[7:0]; + assign asn_FpMul_8U_23U_p_expo_lpi_1_dfm_1_FpMul_8U_23U_else_2_else_and_nl = FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1 + & (FpMul_8U_23U_p_mant_p1_sva_2[47]); + assign FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0 = MUX_v_8_2_2(FpMul_8U_23U_p_expo_sva_5, + (FpMul_8U_23U_else_2_else_if_if_acc_nl), asn_FpMul_8U_23U_p_expo_lpi_1_dfm_1_FpMul_8U_23U_else_2_else_and_nl); + assign FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp = ~((FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1==8'b11111111)); + assign nl_FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1 = FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0 + + 8'b1; + assign FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1 = nl_FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1[7:0]; + assign FpMantRNE_48U_24U_else_and_svs = FpMantRNE_48U_24U_else_carry_sva & (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[45:23]==23'b11111111111111111111111); + assign FpMantRNE_48U_24U_else_carry_sva = (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[22]) + & (((FpMul_8U_23U_p_mant_p1_sva_2[0]) & (FpMul_8U_23U_p_mant_p1_sva_2[47])) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[0]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[1]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[2]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[3]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[4]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[5]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[6]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[7]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[8]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[9]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[10]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[11]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[12]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[13]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[14]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[15]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[16]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[17]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[18]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[19]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[20]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[21]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[23])); + assign FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0 = MUX_v_46_2_2((FpMul_8U_23U_p_mant_p1_sva_2[45:0]), + (FpMul_8U_23U_p_mant_p1_sva_2[46:1]), FpMul_8U_23U_p_mant_p1_sva_2[47]); + assign FpMul_8U_23U_FpMul_8U_23U_nor_1_nl = ~(FpMantRNE_48U_24U_else_and_svs | + FpMul_8U_23U_is_inf_lpi_1_dfm_2); + assign FpMul_8U_23U_or_1_nl = ((~ FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp) + & FpMantRNE_48U_24U_else_and_svs) | FpMul_8U_23U_is_inf_lpi_1_dfm_2; + assign FpMantWidthDec_8U_47U_23U_0U_0U_and_1_nl = FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp + & FpMantRNE_48U_24U_else_and_svs & (~ FpMul_8U_23U_is_inf_lpi_1_dfm_2); + assign FpMul_8U_23U_o_expo_lpi_1_dfm = MUX1HOT_v_8_3_2(FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0, + 8'b11111110, FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1, {(FpMul_8U_23U_FpMul_8U_23U_nor_1_nl) + , (FpMul_8U_23U_or_1_nl) , (FpMantWidthDec_8U_47U_23U_0U_0U_and_1_nl)}); + assign FpMul_8U_23U_lor_2_lpi_1_dfm = (~((FpMul_8U_23U_o_expo_lpi_1_dfm!=8'b00000000))) + | FpMul_8U_23U_lor_1_lpi_1_dfm_4; + assign FpMul_8U_23U_is_inf_lpi_1_dfm_2 = ~(((FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1 + | (~ (FpMul_8U_23U_p_mant_p1_sva_2[47]))) & FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2) + | FpMul_8U_23U_lor_1_lpi_1_dfm_4); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_10_cse; + assign or_3_nl = FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | (~ main_stage_v_1) | chn_o_rsci_bawt + | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign nor_nl = ~((~(FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | (~ main_stage_v_1))) | + chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_1_nl = (~ chn_a_rsci_bawt) | (~ chn_b_rsci_bawt) | FpMul_8U_23U_oelse_1_acc_itm_9_1 + | FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp; + assign mux_tmp = MUX_s_1_2_2((nor_nl), (or_3_nl), or_1_nl); + assign and_cse = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_7_nl = main_stage_v_1 | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign nor_28_nl = ~((~ main_stage_v_1) | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign mux_tmp_1 = MUX_s_1_2_2((nor_28_nl), (or_7_nl), and_cse); + assign or_tmp_24 = (~ main_stage_v_2) | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign or_22_nl = main_stage_v_2 | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign mux_tmp_4 = MUX_s_1_2_2((~ or_tmp_24), (or_22_nl), main_stage_v_1); + assign not_tmp_9 = ~(main_stage_v_1 & or_10_cse); + assign or_tmp_32 = (~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse))) | + IsNaN_8U_23U_land_lpi_1_dfm_st_3; + assign nor_22_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ IsNaN_8U_23U_land_lpi_1_dfm_st_3)); + assign mux_tmp_9 = MUX_s_1_2_2((nor_22_nl), IsNaN_8U_23U_land_lpi_1_dfm_st_3, chn_o_rsci_bawt); + assign mux_tmp_10 = MUX_s_1_2_2(mux_tmp_9, or_10_cse, nor_4_cse); + assign or_tmp_36 = IsNaN_8U_23U_1_land_lpi_1_dfm_3 | or_tmp_32; + assign mux_tmp_14 = MUX_s_1_2_2(mux_tmp_9, or_10_cse, IsNaN_8U_23U_1_land_lpi_1_dfm_3); + assign or_39_nl = (~ main_stage_v_1) | IsNaN_8U_23U_1_land_lpi_1_dfm_3 | or_tmp_32; + assign mux_18_nl = MUX_s_1_2_2(or_tmp_36, mux_tmp_14, main_stage_v_2); + assign mux_19_nl = MUX_s_1_2_2(or_tmp_24, (mux_18_nl), main_stage_v_1); + assign mux_20_itm = MUX_s_1_2_2((mux_19_nl), (or_39_nl), FpMul_8U_23U_or_2_cse); + assign or_tmp_51 = FpMul_8U_23U_oelse_1_acc_itm_9_1 | FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp + | (~ and_cse); + assign and_dcpl_3 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_6 = (~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_12 = or_10_cse & main_stage_v_2; + assign and_dcpl_13 = and_dcpl_3 & (~ main_stage_v_2); + assign and_dcpl_16 = or_10_cse & main_stage_v_1; + assign and_dcpl_26 = or_10_cse & IsNaN_8U_23U_land_lpi_1_dfm_st_3; + assign or_tmp_55 = IsNaN_8U_23U_1_nor_tmp | nand_8_cse; + assign or_tmp_59 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_65 = or_10_cse & chn_b_rsci_bawt & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_o_rsci_d_30_23_mx0c1 = or_10_cse & main_stage_v_2 & (~ IsNaN_8U_23U_land_lpi_1_dfm_4); + assign main_stage_v_1_mx0c1 = and_dcpl_16 & (~(chn_b_rsci_bawt & chn_a_rsci_bawt)); + assign main_stage_v_2_mx0c1 = or_10_cse & main_stage_v_2 & (~ main_stage_v_1); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_65; + assign chn_o_rsci_oswt_unreg = and_dcpl_3; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_12; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_59 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_59; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_0 <= 23'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_22_0 <= MUX_v_23_2_2((FpMul_8U_23U_FpMul_8U_23U_FpMul_8U_23U_nor_1_nl), + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2, FpMul_8U_23U_or_2_cse); + chn_o_rsci_d_31 <= FpMul_8U_23U_mux_10_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_23 <= 8'b0; + end + else if ( core_wen & ((or_10_cse & main_stage_v_2 & IsNaN_8U_23U_land_lpi_1_dfm_4) + | chn_o_rsci_d_30_23_mx0c1) ) begin + chn_o_rsci_d_30_23 <= MUX_v_8_2_2(FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2, + (FpMul_8U_23U_FpMul_8U_23U_and_2_nl), FpBitsToFloat_8U_23U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_12 | and_dcpl_13) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_65 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2 <= 8'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (~ mux_tmp) ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2 <= readslicef_9_8_1((FpMul_8U_23U_else_2_acc_1_nl)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_3 <= 1'b0; + FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 <= 1'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= 1'b0; + end + else if ( IsNaN_8U_23U_aelse_and_cse ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_3 <= ~(IsNaN_8U_23U_nor_tmp | nand_cse); + FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 <= or_45_cse; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= ~(IsNaN_8U_23U_1_nor_tmp | nand_8_cse); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & (and_dcpl_16 | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_p_expo_sva_5 <= 8'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_3_nl) ) begin + FpMul_8U_23U_p_expo_sva_5 <= nl_FpMul_8U_23U_p_expo_sva_5[7:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_p_mant_p1_sva_2 <= 48'b0; + end + else if ( core_wen & ((or_10_cse & (~ FpMul_8U_23U_lor_1_lpi_1_dfm_st_3) & FpMul_8U_23U_else_2_if_acc_itm_8_1) + | and_41_rgt) & mux_tmp_4 ) begin + FpMul_8U_23U_p_mant_p1_sva_2 <= MUX_v_48_2_2(FpMul_8U_23U_p_mant_p1_mul_tmp, + FpMul_8U_23U_p_mant_p1_sva, and_41_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_6_nl) ) begin + FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2 <= FpMul_8U_23U_p_mant_p1_mul_tmp[47]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_8_nl) ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2 <= FpMul_8U_23U_else_2_if_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2 <= 8'b0; + end + else if ( core_wen & FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse & (mux_13_nl) + ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2 <= MUX_v_8_2_2((FpMul_8U_23U_ub_sva_1_30_0_1[30:23]), + (FpMul_8U_23U_ua_sva_1_30_0_1[30:23]), and_dcpl_26); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= 1'b0; + FpMul_8U_23U_mux_10_itm_4 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_4 <= 1'b0; + FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 <= 1'b0; + end + else if ( IsNaN_8U_23U_1_aelse_and_cse ) begin + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= IsNaN_8U_23U_1_land_lpi_1_dfm_3; + FpMul_8U_23U_mux_10_itm_4 <= FpMul_8U_23U_mux_10_itm_3; + IsNaN_8U_23U_land_lpi_1_dfm_4 <= IsNaN_8U_23U_land_lpi_1_dfm_st_3; + FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 <= FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2 <= 23'b0; + end + else if ( core_wen & FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse & (mux_17_nl) + ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2 <= MUX_v_23_2_2((FpMul_8U_23U_ub_sva_1_30_0_1[22:0]), + (FpMul_8U_23U_ua_sva_1_30_0_1[22:0]), and_dcpl_26); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_4 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (~ mux_20_itm) ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_4 <= FpMul_8U_23U_lor_1_lpi_1_dfm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2 <= 1'b0; + end + else if ( core_wen & ((or_10_cse & (~ FpMul_8U_23U_lor_1_lpi_1_dfm_st_3)) | and_45_rgt) + & (~ mux_20_itm) ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2 <= MUX_s_1_2_2(FpMul_8U_23U_else_2_if_acc_itm_8_1, + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs, and_45_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_p_mant_p1_sva <= 48'b0; + end + else if ( core_wen & (~(and_dcpl_6 | (~ main_stage_v_1) | or_29_cse)) ) begin + FpMul_8U_23U_p_mant_p1_sva <= FpMul_8U_23U_p_mant_p1_mul_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs <= 1'b0; + end + else if ( core_wen & (~ (fsm_output[0])) & (~ or_65_cse) & mux_tmp ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs <= FpMul_8U_23U_else_2_if_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_3 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_23_nl) ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_3 <= or_45_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_mux_10_itm_3 <= 1'b0; + end + else if ( core_wen & (and_54_rgt | and_64_rgt | and_65_rgt) & mux_tmp_1 ) begin + FpMul_8U_23U_mux_10_itm_3 <= MUX1HOT_s_1_3_2((chn_a_rsci_d_mxwt[31]), (chn_b_rsci_d_mxwt[31]), + (FpMul_8U_23U_xor_1_nl), {and_54_rgt , and_64_rgt , and_65_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_ub_sva_1_30_0_1 <= 31'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_28_nl) ) begin + FpMul_8U_23U_ub_sva_1_30_0_1 <= chn_b_rsci_d_mxwt[30:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_ua_sva_1_30_0_1 <= 31'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (~ (mux_31_nl)) ) begin + FpMul_8U_23U_ua_sva_1_30_0_1 <= chn_a_rsci_d_mxwt[30:0]; + end + end + assign nl_FpMantRNE_48U_24U_else_acc_nl = (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[45:23]) + + conv_u2u_1_23(FpMantRNE_48U_24U_else_carry_sva); + assign FpMantRNE_48U_24U_else_acc_nl = nl_FpMantRNE_48U_24U_else_acc_nl[22:0]; + assign or_nl = FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp | (~ FpMantRNE_48U_24U_else_and_svs); + assign mux_34_nl = MUX_v_23_2_2((signext_23_1(~ FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp)), + (FpMantRNE_48U_24U_else_acc_nl), or_nl); + assign FpMul_8U_23U_nor_nl = ~(MUX_v_23_2_2((mux_34_nl), 23'b11111111111111111111111, + FpMul_8U_23U_is_inf_lpi_1_dfm_2)); + assign FpMul_8U_23U_FpMul_8U_23U_FpMul_8U_23U_nor_1_nl = ~(MUX_v_23_2_2((FpMul_8U_23U_nor_nl), + 23'b11111111111111111111111, FpMul_8U_23U_lor_2_lpi_1_dfm)); + assign FpMul_8U_23U_oelse_2_not_1_nl = ~ FpMul_8U_23U_lor_2_lpi_1_dfm; + assign FpMul_8U_23U_FpMul_8U_23U_and_2_nl = MUX_v_8_2_2(8'b00000000, FpMul_8U_23U_o_expo_lpi_1_dfm, + (FpMul_8U_23U_oelse_2_not_1_nl)); + assign FpBitsToFloat_8U_23U_1_and_nl = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_4) & chn_o_rsci_d_30_23_mx0c1; + assign nl_FpMul_8U_23U_else_2_acc_1_nl = conv_u2u_8_9(chn_a_rsci_d_mxwt[30:23]) + + conv_u2u_8_9(chn_b_rsci_d_mxwt[30:23]); + assign FpMul_8U_23U_else_2_acc_1_nl = nl_FpMul_8U_23U_else_2_acc_1_nl[8:0]; + assign nl_FpMul_8U_23U_else_2_else_acc_2_nl = (FpMul_8U_23U_ub_sva_1_30_0_1[30:23]) + + 8'b10000001; + assign FpMul_8U_23U_else_2_else_acc_2_nl = nl_FpMul_8U_23U_else_2_else_acc_2_nl[7:0]; + assign nl_FpMul_8U_23U_p_expo_sva_5 = (FpMul_8U_23U_else_2_else_acc_2_nl) + (FpMul_8U_23U_ua_sva_1_30_0_1[30:23]); + assign nor_24_nl = ~((~ main_stage_v_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | (~(FpMul_8U_23U_else_2_if_acc_itm_8_1 + & ((FpMul_8U_23U_p_mant_p1_mul_tmp[47]) | (~(IsNaN_8U_23U_land_lpi_1_dfm_st_3 + | IsNaN_8U_23U_1_land_lpi_1_dfm_3)))))); + assign nor_26_nl = ~((~ main_stage_v_2) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 | (~ + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2)); + assign nor_27_nl = ~(FpMul_8U_23U_or_2_cse | (FpMul_8U_23U_p_mant_p1_sva_2[47]) + | (~ main_stage_v_2) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 | (~ FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2)); + assign mux_2_nl = MUX_s_1_2_2((nor_27_nl), (nor_26_nl), FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2); + assign mux_3_nl = MUX_s_1_2_2((mux_2_nl), (nor_24_nl), or_10_cse); + assign nor_32_nl = ~((~ FpMul_8U_23U_else_2_if_acc_itm_8_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 + | not_tmp_9); + assign mux_5_nl = MUX_s_1_2_2(mux_tmp_4, (~ or_tmp_24), or_29_cse); + assign or_25_nl = (~ FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2) + | FpMul_8U_23U_lor_1_lpi_1_dfm_st_4; + assign mux_6_nl = MUX_s_1_2_2((mux_5_nl), (nor_32_nl), or_25_nl); + assign nor_23_nl = ~(FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | not_tmp_9); + assign mux_7_nl = MUX_s_1_2_2(mux_tmp_4, (~ or_tmp_24), FpMul_8U_23U_lor_1_lpi_1_dfm_st_3); + assign mux_8_nl = MUX_s_1_2_2((mux_7_nl), (nor_23_nl), FpMul_8U_23U_lor_1_lpi_1_dfm_st_4); + assign or_33_nl = nor_4_cse | or_tmp_32; + assign mux_11_nl = MUX_s_1_2_2(mux_tmp_10, (or_33_nl), main_stage_v_2); + assign mux_12_nl = MUX_s_1_2_2((~ or_tmp_24), (mux_11_nl), main_stage_v_1); + assign and_10_nl = main_stage_v_1 & mux_tmp_10; + assign mux_13_nl = MUX_s_1_2_2((and_10_nl), (mux_12_nl), FpMul_8U_23U_or_2_cse); + assign mux_15_nl = MUX_s_1_2_2(mux_tmp_14, or_tmp_36, main_stage_v_2); + assign mux_16_nl = MUX_s_1_2_2((~ or_tmp_24), (mux_15_nl), main_stage_v_1); + assign and_11_nl = main_stage_v_1 & mux_tmp_14; + assign mux_17_nl = MUX_s_1_2_2((and_11_nl), (mux_16_nl), FpMul_8U_23U_or_2_cse); + assign and_93_nl = nand_8_cse & mux_24_cse; + assign mux_22_nl = MUX_s_1_2_2((and_93_nl), mux_24_cse, IsNaN_8U_23U_1_nor_tmp); + assign nor_21_nl = ~((~ main_stage_v_1) | IsNaN_8U_23U_land_lpi_1_dfm_st_3 | IsNaN_8U_23U_1_land_lpi_1_dfm_3); + assign mux_23_nl = MUX_s_1_2_2((nor_21_nl), (mux_22_nl), or_10_cse); + assign FpMul_8U_23U_xor_1_nl = (chn_a_rsci_d_mxwt[31]) ^ (chn_b_rsci_d_mxwt[31]); + assign nor_31_nl = ~(IsNaN_8U_23U_1_nor_tmp | (~((chn_b_rsci_d_mxwt[30:23]==8'b11111111) + & mux_24_cse))); + assign mux_25_nl = MUX_s_1_2_2(and_cse, (nor_31_nl), or_45_cse); + assign mux_26_nl = MUX_s_1_2_2(or_65_cse, (~ main_stage_v_1), IsNaN_8U_23U_1_land_lpi_1_dfm_3); + assign mux_27_nl = MUX_s_1_2_2((mux_26_nl), or_65_cse, IsNaN_8U_23U_land_lpi_1_dfm_st_3); + assign mux_28_nl = MUX_s_1_2_2((~ (mux_27_nl)), (mux_25_nl), or_10_cse); + assign and_91_nl = (chn_a_rsci_d_mxwt[30:23]==8'b11111111); + assign mux_29_nl = MUX_s_1_2_2(or_tmp_51, (~ and_cse), and_91_nl); + assign mux_30_nl = MUX_s_1_2_2((mux_29_nl), or_tmp_51, IsNaN_8U_23U_nor_tmp); + assign nand_6_nl = ~(((~ FpMul_8U_23U_lor_1_lpi_1_dfm_st_3) | IsNaN_8U_23U_land_lpi_1_dfm_st_3) + & main_stage_v_1); + assign mux_31_nl = MUX_s_1_2_2((nand_6_nl), (mux_30_nl), or_10_cse); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_3_2; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [2:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + MUX1HOT_v_8_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [45:0] MUX_v_46_2_2; + input [45:0] input_0; + input [45:0] input_1; + input [0:0] sel; + reg [45:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_46_2_2 = result; + end + endfunction + function [47:0] MUX_v_48_2_2; + input [47:0] input_0; + input [47:0] input_1; + input [0:0] sel; + reg [47:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_48_2_2 = result; + end + endfunction + function [7:0] MUX_v_8_2_2; + input [7:0] input_0; + input [7:0] input_1; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + function [0:0] readslicef_10_1_9; + input [9:0] vector; + reg [9:0] tmp; + begin + tmp = vector >> 9; + readslicef_10_1_9 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [7:0] readslicef_9_8_1; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 1; + readslicef_9_8_1 = tmp[7:0]; + end + endfunction + function [22:0] signext_23_1; + input [0:0] vector; + begin + signext_23_1= {{22{vector[0]}}, vector}; + end + endfunction + function [9:0] conv_s2s_9_10 ; + input [8:0] vector ; + begin + conv_s2s_9_10 = {vector[8], vector}; + end + endfunction + function [8:0] conv_u2s_8_9 ; + input [7:0] vector ; + begin + conv_u2s_8_9 = {1'b0, vector}; + end + endfunction + function [9:0] conv_u2s_8_10 ; + input [7:0] vector ; + begin + conv_u2s_8_10 = {{2{1'b0}}, vector}; + end + endfunction + function [22:0] conv_u2u_1_23 ; + input [0:0] vector ; + begin + conv_u2u_1_23 = {{22{1'b0}}, vector}; + end + endfunction + function [8:0] conv_u2u_8_9 ; + input [7:0] vector ; + begin + conv_u2u_8_9 = {1'b0, vector}; + end + endfunction + function [47:0] conv_u2u_48_48 ; + input [47:0] vector ; + begin + conv_u2u_48_48 = vector; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul +// ------------------------------------------------------------------ +module HLS_fp32_mul ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP32_MUL_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP32_MUL_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP32_MUL_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_mul_core HLS_fp32_mul_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_mul.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_mul.v.vcp new file mode 100644 index 0000000..f82c5ee --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_mul.v.vcp @@ -0,0 +1,1536 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_mul.v +module FP32_MUL_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_MUL_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_MUL_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:53:54 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_MUL_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_MUL_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_MUL_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP32_MUL_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_MUL_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_MUL_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_mul_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_mul_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [31:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [31:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [31:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_32_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 32'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_MUL_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_mul_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [31:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [31:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp HLS_fp32_mul_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_mul_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_MUL_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_mul_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul_core +// ------------------------------------------------------------------ +module HLS_fp32_mul_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [31:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [7:0] chn_o_rsci_d_30_23; + reg [22:0] chn_o_rsci_d_22_0; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_nor_tmp; + wire FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp; + wire [47:0] FpMul_8U_23U_p_mant_p1_mul_tmp; + wire IsNaN_8U_23U_1_nor_tmp; + wire mux_tmp; + wire mux_tmp_1; + wire or_tmp_24; + wire mux_tmp_4; + wire not_tmp_9; + wire or_tmp_32; + wire mux_tmp_9; + wire mux_tmp_10; + wire or_tmp_36; + wire mux_tmp_14; + wire or_tmp_51; + wire and_dcpl_3; + wire and_dcpl_6; + wire and_dcpl_12; + wire and_dcpl_13; + wire and_dcpl_16; + wire and_dcpl_26; + wire or_tmp_55; + wire or_tmp_59; + wire or_tmp_65; + reg FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs; + reg [47:0] FpMul_8U_23U_p_mant_p1_sva; + reg main_stage_v_1; + reg main_stage_v_2; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_4; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_3; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_4; + reg FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2; + reg [47:0] FpMul_8U_23U_p_mant_p1_sva_2; + reg [7:0] FpMul_8U_23U_p_expo_sva_5; + wire [8:0] nl_FpMul_8U_23U_p_expo_sva_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_4; + reg [7:0] FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2; + reg [7:0] FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2; + reg FpMul_8U_23U_mux_10_itm_3; + reg FpMul_8U_23U_mux_10_itm_4; + reg [22:0] FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + reg FpMul_8U_23U_lor_1_lpi_1_dfm_st_4; + reg FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2; + reg FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2; + reg IsNaN_8U_23U_land_lpi_1_dfm_st_3; + reg [30:0] FpMul_8U_23U_ua_sva_1_30_0_1; + reg [30:0] FpMul_8U_23U_ub_sva_1_30_0_1; + wire main_stage_en_1; + wire FpMantRNE_48U_24U_else_and_svs; + wire FpMul_8U_23U_is_inf_lpi_1_dfm_2; + wire FpMantRNE_48U_24U_else_carry_sva; + wire [7:0] FpMul_8U_23U_o_expo_lpi_1_dfm; + wire FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp; + wire [7:0] FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1; + wire [8:0] nl_FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1; + wire [45:0] FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0; + reg reg_chn_b_rsci_iswt0_cse; + reg reg_chn_b_rsci_ld_core_psct_cse; + wire chn_o_and_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_10_cse; + wire nand_8_cse; + wire nand_cse; + wire or_45_cse; + wire FpMul_8U_23U_or_2_cse; + wire nor_4_cse; + wire and_cse; + wire or_65_cse; + wire or_29_cse; + wire mux_24_cse; + wire and_41_rgt; + wire and_45_rgt; + wire and_54_rgt; + wire and_64_rgt; + wire and_65_rgt; + wire mux_20_itm; + wire chn_o_rsci_d_30_23_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire [7:0] FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0; + wire FpMul_8U_23U_lor_2_lpi_1_dfm; + wire IsNaN_8U_23U_aelse_and_cse; + wire IsNaN_8U_23U_1_aelse_and_cse; + wire FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse; + wire FpMul_8U_23U_else_2_if_acc_itm_8_1; + wire FpMul_8U_23U_oelse_1_acc_itm_9_1; + wire FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[22:0] FpMul_8U_23U_FpMul_8U_23U_FpMul_8U_23U_nor_1_nl; + wire[22:0] FpMul_8U_23U_nor_nl; + wire[22:0] mux_34_nl; + wire[22:0] FpMantRNE_48U_24U_else_acc_nl; + wire[23:0] nl_FpMantRNE_48U_24U_else_acc_nl; + wire[0:0] or_nl; + wire[7:0] FpMul_8U_23U_FpMul_8U_23U_and_2_nl; + wire[0:0] FpMul_8U_23U_oelse_2_not_1_nl; + wire[0:0] FpBitsToFloat_8U_23U_1_and_nl; + wire[8:0] FpMul_8U_23U_else_2_acc_1_nl; + wire[9:0] nl_FpMul_8U_23U_else_2_acc_1_nl; + wire[7:0] FpMul_8U_23U_else_2_else_acc_2_nl; + wire[8:0] nl_FpMul_8U_23U_else_2_else_acc_2_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_24_nl; + wire[0:0] mux_2_nl; + wire[0:0] nor_26_nl; + wire[0:0] nor_27_nl; + wire[0:0] mux_6_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_5_nl; + wire[0:0] or_25_nl; + wire[0:0] mux_8_nl; + wire[0:0] nor_23_nl; + wire[0:0] mux_7_nl; + wire[0:0] mux_13_nl; + wire[0:0] mux_12_nl; + wire[0:0] mux_11_nl; + wire[0:0] or_33_nl; + wire[0:0] and_10_nl; + wire[0:0] mux_17_nl; + wire[0:0] mux_16_nl; + wire[0:0] mux_15_nl; + wire[0:0] and_11_nl; + wire[0:0] mux_23_nl; + wire[0:0] mux_22_nl; + wire[0:0] and_93_nl; + wire[0:0] nor_21_nl; + wire[0:0] mux_33_nl; + wire[0:0] and_90_nl; + wire[0:0] FpMul_8U_23U_xor_1_nl; + wire[0:0] and_95_nl; + wire[0:0] mux_28_nl; + wire[0:0] mux_25_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_27_nl; + wire[0:0] mux_26_nl; + wire[0:0] mux_31_nl; + wire[0:0] mux_30_nl; + wire[0:0] mux_29_nl; + wire[0:0] and_91_nl; + wire[0:0] nand_6_nl; + wire[8:0] FpMul_8U_23U_else_2_if_acc_nl; + wire[9:0] nl_FpMul_8U_23U_else_2_if_acc_nl; + wire[9:0] FpMul_8U_23U_oelse_1_acc_nl; + wire[10:0] nl_FpMul_8U_23U_oelse_1_acc_nl; + wire[8:0] FpMul_8U_23U_oelse_1_acc_1_nl; + wire[9:0] nl_FpMul_8U_23U_oelse_1_acc_1_nl; + wire[7:0] FpMul_8U_23U_else_2_else_if_if_acc_1_nl; + wire[8:0] nl_FpMul_8U_23U_else_2_else_if_if_acc_1_nl; + wire[7:0] FpMul_8U_23U_else_2_else_if_if_acc_nl; + wire[8:0] nl_FpMul_8U_23U_else_2_else_if_if_acc_nl; + wire[0:0] asn_FpMul_8U_23U_p_expo_lpi_1_dfm_1_FpMul_8U_23U_else_2_else_and_nl; + wire[0:0] FpMul_8U_23U_FpMul_8U_23U_nor_1_nl; + wire[0:0] FpMul_8U_23U_or_1_nl; + wire[0:0] FpMantWidthDec_8U_47U_23U_0U_0U_and_1_nl; + wire[0:0] or_3_nl; + wire[0:0] nor_nl; + wire[0:0] or_1_nl; + wire[0:0] or_7_nl; + wire[0:0] nor_28_nl; + wire[0:0] or_22_nl; + wire[0:0] nor_22_nl; + wire[0:0] or_39_nl; + wire[0:0] mux_19_nl; + wire[0:0] mux_18_nl; +// Interconnect Declarations for Component Instantiations + wire [31:0] nl_HLS_fp32_mul_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_mul_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 , chn_o_rsci_d_30_23 + , chn_o_rsci_d_22_0}; + HLS_fp32_mul_core_chn_a_rsci HLS_fp32_mul_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_mul_core_chn_b_rsci HLS_fp32_mul_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_b_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_b_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp32_mul_core_chn_o_rsci HLS_fp32_mul_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_mul_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp32_mul_core_staller HLS_fp32_mul_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_mul_core_core_fsm HLS_fp32_mul_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), + (MUX1HOT_s_1_1_2(1'b1, main_stage_en_1 & (fsm_output[1]))), fsm_output[1]); +// assert(iMantWidth > oMantWidth) - ../include/nvdla_float.h: line 386 +// PSL HLS_fp32_mul_core_nvdla_float_h_ln386_assert_iMantWidth_gt_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_6 | (~ main_stage_v_2))); + assign FpMul_8U_23U_or_2_cse = IsNaN_8U_23U_1_land_lpi_1_dfm_4 | IsNaN_8U_23U_land_lpi_1_dfm_4; + assign IsNaN_8U_23U_aelse_and_cse = core_wen & (~ and_dcpl_6) & mux_tmp_1; + assign or_10_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign and_41_rgt = or_10_cse & or_29_cse; + assign or_29_cse = (~ FpMul_8U_23U_else_2_if_acc_itm_8_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + assign nor_4_cse = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_3 | (~ IsNaN_8U_23U_1_land_lpi_1_dfm_3)); + assign FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse = (or_10_cse & (~ IsNaN_8U_23U_land_lpi_1_dfm_st_3)) + | and_dcpl_26; + assign IsNaN_8U_23U_1_aelse_and_cse = core_wen & (~ and_dcpl_6) & mux_tmp_4; + assign and_45_rgt = or_10_cse & FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + assign or_65_cse = (~ main_stage_v_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + assign nand_8_cse = ~((chn_b_rsci_d_mxwt[30:23]==8'b11111111)); + assign nand_cse = ~((chn_a_rsci_d_mxwt[30:23]==8'b11111111)); + assign and_54_rgt = or_10_cse & (chn_a_rsci_d_mxwt[30:23]==8'b11111111) & (~ IsNaN_8U_23U_nor_tmp); + assign and_64_rgt = ((chn_a_rsci_d_mxwt[30:23]!=8'b11111111) | IsNaN_8U_23U_nor_tmp) + & (chn_b_rsci_d_mxwt[30:23]==8'b11111111) & (~ IsNaN_8U_23U_1_nor_tmp) & or_10_cse; + assign and_90_nl = nand_cse & or_tmp_55; + assign mux_33_nl = MUX_s_1_2_2((and_90_nl), or_tmp_55, IsNaN_8U_23U_nor_tmp); + assign and_65_rgt = (mux_33_nl) & or_10_cse; + assign or_45_cse = FpMul_8U_23U_oelse_1_acc_itm_9_1 | FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp; + assign and_95_nl = nand_cse & and_cse; + assign mux_24_cse = MUX_s_1_2_2((and_95_nl), and_cse, IsNaN_8U_23U_nor_tmp); + assign IsNaN_8U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign FpMul_8U_23U_p_mant_p1_mul_tmp = conv_u2u_48_48(({1'b1 , (FpMul_8U_23U_ua_sva_1_30_0_1[22:0])}) + * ({1'b1 , (FpMul_8U_23U_ub_sva_1_30_0_1[22:0])})); + assign nl_FpMul_8U_23U_else_2_if_acc_nl = conv_u2u_8_9(FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2) + + 9'b101000001; + assign FpMul_8U_23U_else_2_if_acc_nl = nl_FpMul_8U_23U_else_2_if_acc_nl[8:0]; + assign FpMul_8U_23U_else_2_if_acc_itm_8_1 = readslicef_9_1_8((FpMul_8U_23U_else_2_if_acc_nl)); + assign IsNaN_8U_23U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign nl_FpMul_8U_23U_oelse_1_acc_1_nl = conv_u2s_8_9(chn_b_rsci_d_mxwt[30:23]) + + 9'b110000001; + assign FpMul_8U_23U_oelse_1_acc_1_nl = nl_FpMul_8U_23U_oelse_1_acc_1_nl[8:0]; + assign nl_FpMul_8U_23U_oelse_1_acc_nl = conv_s2s_9_10(FpMul_8U_23U_oelse_1_acc_1_nl) + + conv_u2s_8_10(chn_a_rsci_d_mxwt[30:23]); + assign FpMul_8U_23U_oelse_1_acc_nl = nl_FpMul_8U_23U_oelse_1_acc_nl[9:0]; + assign FpMul_8U_23U_oelse_1_acc_itm_9_1 = readslicef_10_1_9((FpMul_8U_23U_oelse_1_acc_nl)); + assign FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp = (~((chn_b_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000))) + | (~((chn_a_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000))); + assign nl_FpMul_8U_23U_else_2_else_if_if_acc_1_nl = ({1'b1 , (FpMul_8U_23U_p_expo_sva_5[7:1])}) + + 8'b1; + assign FpMul_8U_23U_else_2_else_if_if_acc_1_nl = nl_FpMul_8U_23U_else_2_else_if_if_acc_1_nl[7:0]; + assign FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1 = readslicef_8_1_7((FpMul_8U_23U_else_2_else_if_if_acc_1_nl)); + assign nl_FpMul_8U_23U_else_2_else_if_if_acc_nl = FpMul_8U_23U_p_expo_sva_5 + 8'b1; + assign FpMul_8U_23U_else_2_else_if_if_acc_nl = nl_FpMul_8U_23U_else_2_else_if_if_acc_nl[7:0]; + assign asn_FpMul_8U_23U_p_expo_lpi_1_dfm_1_FpMul_8U_23U_else_2_else_and_nl = FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1 + & (FpMul_8U_23U_p_mant_p1_sva_2[47]); + assign FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0 = MUX_v_8_2_2(FpMul_8U_23U_p_expo_sva_5, + (FpMul_8U_23U_else_2_else_if_if_acc_nl), asn_FpMul_8U_23U_p_expo_lpi_1_dfm_1_FpMul_8U_23U_else_2_else_and_nl); + assign FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp = ~((FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1==8'b11111111)); + assign nl_FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1 = FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0 + + 8'b1; + assign FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1 = nl_FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1[7:0]; + assign FpMantRNE_48U_24U_else_and_svs = FpMantRNE_48U_24U_else_carry_sva & (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[45:23]==23'b11111111111111111111111); + assign FpMantRNE_48U_24U_else_carry_sva = (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[22]) + & (((FpMul_8U_23U_p_mant_p1_sva_2[0]) & (FpMul_8U_23U_p_mant_p1_sva_2[47])) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[0]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[1]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[2]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[3]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[4]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[5]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[6]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[7]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[8]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[9]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[10]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[11]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[12]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[13]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[14]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[15]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[16]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[17]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[18]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[19]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[20]) | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[21]) + | (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[23])); + assign FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0 = MUX_v_46_2_2((FpMul_8U_23U_p_mant_p1_sva_2[45:0]), + (FpMul_8U_23U_p_mant_p1_sva_2[46:1]), FpMul_8U_23U_p_mant_p1_sva_2[47]); + assign FpMul_8U_23U_FpMul_8U_23U_nor_1_nl = ~(FpMantRNE_48U_24U_else_and_svs | + FpMul_8U_23U_is_inf_lpi_1_dfm_2); + assign FpMul_8U_23U_or_1_nl = ((~ FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp) + & FpMantRNE_48U_24U_else_and_svs) | FpMul_8U_23U_is_inf_lpi_1_dfm_2; + assign FpMantWidthDec_8U_47U_23U_0U_0U_and_1_nl = FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp + & FpMantRNE_48U_24U_else_and_svs & (~ FpMul_8U_23U_is_inf_lpi_1_dfm_2); + assign FpMul_8U_23U_o_expo_lpi_1_dfm = MUX1HOT_v_8_3_2(FpMul_8U_23U_p_expo_lpi_1_dfm_1_mx0, + 8'b11111110, FpMantWidthDec_8U_47U_23U_0U_0U_o_expo_sva_1, {(FpMul_8U_23U_FpMul_8U_23U_nor_1_nl) + , (FpMul_8U_23U_or_1_nl) , (FpMantWidthDec_8U_47U_23U_0U_0U_and_1_nl)}); + assign FpMul_8U_23U_lor_2_lpi_1_dfm = (~((FpMul_8U_23U_o_expo_lpi_1_dfm!=8'b00000000))) + | FpMul_8U_23U_lor_1_lpi_1_dfm_4; + assign FpMul_8U_23U_is_inf_lpi_1_dfm_2 = ~(((FpMul_8U_23U_else_2_else_if_if_acc_1_itm_7_1 + | (~ (FpMul_8U_23U_p_mant_p1_sva_2[47]))) & FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2) + | FpMul_8U_23U_lor_1_lpi_1_dfm_4); + assign main_stage_en_1 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_10_cse; + assign or_3_nl = FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | (~ main_stage_v_1) | chn_o_rsci_bawt + | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign nor_nl = ~((~(FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | (~ main_stage_v_1))) | + chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_1_nl = (~ chn_a_rsci_bawt) | (~ chn_b_rsci_bawt) | FpMul_8U_23U_oelse_1_acc_itm_9_1 + | FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp; + assign mux_tmp = MUX_s_1_2_2((nor_nl), (or_3_nl), or_1_nl); + assign and_cse = chn_a_rsci_bawt & chn_b_rsci_bawt; + assign or_7_nl = main_stage_v_1 | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign nor_28_nl = ~((~ main_stage_v_1) | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign mux_tmp_1 = MUX_s_1_2_2((nor_28_nl), (or_7_nl), and_cse); + assign or_tmp_24 = (~ main_stage_v_2) | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign or_22_nl = main_stage_v_2 | chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign mux_tmp_4 = MUX_s_1_2_2((~ or_tmp_24), (or_22_nl), main_stage_v_1); + assign not_tmp_9 = ~(main_stage_v_1 & or_10_cse); + assign or_tmp_32 = (~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse))) | + IsNaN_8U_23U_land_lpi_1_dfm_st_3; + assign nor_22_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ IsNaN_8U_23U_land_lpi_1_dfm_st_3)); + assign mux_tmp_9 = MUX_s_1_2_2((nor_22_nl), IsNaN_8U_23U_land_lpi_1_dfm_st_3, chn_o_rsci_bawt); + assign mux_tmp_10 = MUX_s_1_2_2(mux_tmp_9, or_10_cse, nor_4_cse); + assign or_tmp_36 = IsNaN_8U_23U_1_land_lpi_1_dfm_3 | or_tmp_32; + assign mux_tmp_14 = MUX_s_1_2_2(mux_tmp_9, or_10_cse, IsNaN_8U_23U_1_land_lpi_1_dfm_3); + assign or_39_nl = (~ main_stage_v_1) | IsNaN_8U_23U_1_land_lpi_1_dfm_3 | or_tmp_32; + assign mux_18_nl = MUX_s_1_2_2(or_tmp_36, mux_tmp_14, main_stage_v_2); + assign mux_19_nl = MUX_s_1_2_2(or_tmp_24, (mux_18_nl), main_stage_v_1); + assign mux_20_itm = MUX_s_1_2_2((mux_19_nl), (or_39_nl), FpMul_8U_23U_or_2_cse); + assign or_tmp_51 = FpMul_8U_23U_oelse_1_acc_itm_9_1 | FpMul_8U_23U_if_2_FpMul_8U_23U_if_2_or_tmp + | (~ and_cse); + assign and_dcpl_3 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_6 = (~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_12 = or_10_cse & main_stage_v_2; + assign and_dcpl_13 = and_dcpl_3 & (~ main_stage_v_2); + assign and_dcpl_16 = or_10_cse & main_stage_v_1; + assign and_dcpl_26 = or_10_cse & IsNaN_8U_23U_land_lpi_1_dfm_st_3; + assign or_tmp_55 = IsNaN_8U_23U_1_nor_tmp | nand_8_cse; + assign or_tmp_59 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_65 = or_10_cse & chn_b_rsci_bawt & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_o_rsci_d_30_23_mx0c1 = or_10_cse & main_stage_v_2 & (~ IsNaN_8U_23U_land_lpi_1_dfm_4); + assign main_stage_v_1_mx0c1 = and_dcpl_16 & (~(chn_b_rsci_bawt & chn_a_rsci_bawt)); + assign main_stage_v_2_mx0c1 = or_10_cse & main_stage_v_2 & (~ main_stage_v_1); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_65; + assign chn_o_rsci_oswt_unreg = and_dcpl_3; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_b_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_12; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_b_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_59 ) begin + reg_chn_b_rsci_ld_core_psct_cse <= or_tmp_59; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_0 <= 23'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_22_0 <= MUX_v_23_2_2((FpMul_8U_23U_FpMul_8U_23U_FpMul_8U_23U_nor_1_nl), + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2, FpMul_8U_23U_or_2_cse); + chn_o_rsci_d_31 <= FpMul_8U_23U_mux_10_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_23 <= 8'b0; + end + else if ( core_wen & ((or_10_cse & main_stage_v_2 & IsNaN_8U_23U_land_lpi_1_dfm_4) + | chn_o_rsci_d_30_23_mx0c1) ) begin + chn_o_rsci_d_30_23 <= MUX_v_8_2_2(FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2, + (FpMul_8U_23U_FpMul_8U_23U_and_2_nl), FpBitsToFloat_8U_23U_1_and_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_12 | and_dcpl_13) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_65 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2 <= 8'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (~ mux_tmp) ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_acc_1_sdt_8_1_itm_2 <= readslicef_9_8_1((FpMul_8U_23U_else_2_acc_1_nl)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_3 <= 1'b0; + FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 <= 1'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= 1'b0; + end + else if ( IsNaN_8U_23U_aelse_and_cse ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_3 <= ~(IsNaN_8U_23U_nor_tmp | nand_cse); + FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 <= or_45_cse; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= ~(IsNaN_8U_23U_1_nor_tmp | nand_8_cse); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & (and_dcpl_16 | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_p_expo_sva_5 <= 8'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_3_nl) ) begin + FpMul_8U_23U_p_expo_sva_5 <= nl_FpMul_8U_23U_p_expo_sva_5[7:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_p_mant_p1_sva_2 <= 48'b0; + end + else if ( core_wen & ((or_10_cse & (~ FpMul_8U_23U_lor_1_lpi_1_dfm_st_3) & FpMul_8U_23U_else_2_if_acc_itm_8_1) + | and_41_rgt) & mux_tmp_4 ) begin + FpMul_8U_23U_p_mant_p1_sva_2 <= MUX_v_48_2_2(FpMul_8U_23U_p_mant_p1_mul_tmp, + FpMul_8U_23U_p_mant_p1_sva, and_41_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_6_nl) ) begin + FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2 <= FpMul_8U_23U_p_mant_p1_mul_tmp[47]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_8_nl) ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2 <= FpMul_8U_23U_else_2_if_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2 <= 8'b0; + end + else if ( core_wen & FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse & (mux_13_nl) + ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_30_23_itm_2 <= MUX_v_8_2_2((FpMul_8U_23U_ub_sva_1_30_0_1[30:23]), + (FpMul_8U_23U_ua_sva_1_30_0_1[30:23]), and_dcpl_26); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= 1'b0; + FpMul_8U_23U_mux_10_itm_4 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_4 <= 1'b0; + FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 <= 1'b0; + end + else if ( IsNaN_8U_23U_1_aelse_and_cse ) begin + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= IsNaN_8U_23U_1_land_lpi_1_dfm_3; + FpMul_8U_23U_mux_10_itm_4 <= FpMul_8U_23U_mux_10_itm_3; + IsNaN_8U_23U_land_lpi_1_dfm_4 <= IsNaN_8U_23U_land_lpi_1_dfm_st_3; + FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 <= FpMul_8U_23U_lor_1_lpi_1_dfm_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2 <= 23'b0; + end + else if ( core_wen & FpMul_8U_23U_ub_FpBitsToFloat_8U_23U_1_or_1_cse & (mux_17_nl) + ) begin + FpBitsToFloat_8U_23U_1_slc_FpBitsToFloat_8U_23U_ubits_1_22_0_itm_2 <= MUX_v_23_2_2((FpMul_8U_23U_ub_sva_1_30_0_1[22:0]), + (FpMul_8U_23U_ua_sva_1_30_0_1[22:0]), and_dcpl_26); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_4 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (~ mux_20_itm) ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_4 <= FpMul_8U_23U_lor_1_lpi_1_dfm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2 <= 1'b0; + end + else if ( core_wen & ((or_10_cse & (~ FpMul_8U_23U_lor_1_lpi_1_dfm_st_3)) | and_45_rgt) + & (~ mux_20_itm) ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_2 <= MUX_s_1_2_2(FpMul_8U_23U_else_2_if_acc_itm_8_1, + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs, and_45_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_p_mant_p1_sva <= 48'b0; + end + else if ( core_wen & (~(and_dcpl_6 | (~ main_stage_v_1) | or_29_cse)) ) begin + FpMul_8U_23U_p_mant_p1_sva <= FpMul_8U_23U_p_mant_p1_mul_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs <= 1'b0; + end + else if ( core_wen & (~ (fsm_output[0])) & (~ or_65_cse) & mux_tmp ) begin + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs <= FpMul_8U_23U_else_2_if_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_3 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_23_nl) ) begin + FpMul_8U_23U_lor_1_lpi_1_dfm_3 <= or_45_cse; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_mux_10_itm_3 <= 1'b0; + end + else if ( core_wen & (and_54_rgt | and_64_rgt | and_65_rgt) & mux_tmp_1 ) begin + FpMul_8U_23U_mux_10_itm_3 <= MUX1HOT_s_1_3_2((chn_a_rsci_d_mxwt[31]), (chn_b_rsci_d_mxwt[31]), + (FpMul_8U_23U_xor_1_nl), {and_54_rgt , and_64_rgt , and_65_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_ub_sva_1_30_0_1 <= 31'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (mux_28_nl) ) begin + FpMul_8U_23U_ub_sva_1_30_0_1 <= chn_b_rsci_d_mxwt[30:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMul_8U_23U_ua_sva_1_30_0_1 <= 31'b0; + end + else if ( core_wen & (~ and_dcpl_6) & (~ (mux_31_nl)) ) begin + FpMul_8U_23U_ua_sva_1_30_0_1 <= chn_a_rsci_d_mxwt[30:0]; + end + end + assign nl_FpMantRNE_48U_24U_else_acc_nl = (FpMul_8U_23U_p_mant_46_1_lpi_1_dfm_3_mx0[45:23]) + + conv_u2u_1_23(FpMantRNE_48U_24U_else_carry_sva); + assign FpMantRNE_48U_24U_else_acc_nl = nl_FpMantRNE_48U_24U_else_acc_nl[22:0]; + assign or_nl = FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp | (~ FpMantRNE_48U_24U_else_and_svs); + assign mux_34_nl = MUX_v_23_2_2((signext_23_1(~ FpMantWidthDec_8U_47U_23U_0U_0U_if_1_unequal_tmp)), + (FpMantRNE_48U_24U_else_acc_nl), or_nl); + assign FpMul_8U_23U_nor_nl = ~(MUX_v_23_2_2((mux_34_nl), 23'b11111111111111111111111, + FpMul_8U_23U_is_inf_lpi_1_dfm_2)); + assign FpMul_8U_23U_FpMul_8U_23U_FpMul_8U_23U_nor_1_nl = ~(MUX_v_23_2_2((FpMul_8U_23U_nor_nl), + 23'b11111111111111111111111, FpMul_8U_23U_lor_2_lpi_1_dfm)); + assign FpMul_8U_23U_oelse_2_not_1_nl = ~ FpMul_8U_23U_lor_2_lpi_1_dfm; + assign FpMul_8U_23U_FpMul_8U_23U_and_2_nl = MUX_v_8_2_2(8'b00000000, FpMul_8U_23U_o_expo_lpi_1_dfm, + (FpMul_8U_23U_oelse_2_not_1_nl)); + assign FpBitsToFloat_8U_23U_1_and_nl = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_4) & chn_o_rsci_d_30_23_mx0c1; + assign nl_FpMul_8U_23U_else_2_acc_1_nl = conv_u2u_8_9(chn_a_rsci_d_mxwt[30:23]) + + conv_u2u_8_9(chn_b_rsci_d_mxwt[30:23]); + assign FpMul_8U_23U_else_2_acc_1_nl = nl_FpMul_8U_23U_else_2_acc_1_nl[8:0]; + assign nl_FpMul_8U_23U_else_2_else_acc_2_nl = (FpMul_8U_23U_ub_sva_1_30_0_1[30:23]) + + 8'b10000001; + assign FpMul_8U_23U_else_2_else_acc_2_nl = nl_FpMul_8U_23U_else_2_else_acc_2_nl[7:0]; + assign nl_FpMul_8U_23U_p_expo_sva_5 = (FpMul_8U_23U_else_2_else_acc_2_nl) + (FpMul_8U_23U_ua_sva_1_30_0_1[30:23]); + assign nor_24_nl = ~((~ main_stage_v_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | (~(FpMul_8U_23U_else_2_if_acc_itm_8_1 + & ((FpMul_8U_23U_p_mant_p1_mul_tmp[47]) | (~(IsNaN_8U_23U_land_lpi_1_dfm_st_3 + | IsNaN_8U_23U_1_land_lpi_1_dfm_3)))))); + assign nor_26_nl = ~((~ main_stage_v_2) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 | (~ + FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2)); + assign nor_27_nl = ~(FpMul_8U_23U_or_2_cse | (FpMul_8U_23U_p_mant_p1_sva_2[47]) + | (~ main_stage_v_2) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_4 | (~ FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2)); + assign mux_2_nl = MUX_s_1_2_2((nor_27_nl), (nor_26_nl), FpMul_8U_23U_else_2_else_slc_FpMul_8U_23U_p_mant_p1_47_itm_2); + assign mux_3_nl = MUX_s_1_2_2((mux_2_nl), (nor_24_nl), or_10_cse); + assign nor_32_nl = ~((~ FpMul_8U_23U_else_2_if_acc_itm_8_1) | FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 + | not_tmp_9); + assign mux_5_nl = MUX_s_1_2_2(mux_tmp_4, (~ or_tmp_24), or_29_cse); + assign or_25_nl = (~ FpMul_8U_23U_else_2_if_slc_FpMul_8U_23U_else_2_if_acc_8_svs_st_2) + | FpMul_8U_23U_lor_1_lpi_1_dfm_st_4; + assign mux_6_nl = MUX_s_1_2_2((mux_5_nl), (nor_32_nl), or_25_nl); + assign nor_23_nl = ~(FpMul_8U_23U_lor_1_lpi_1_dfm_st_3 | not_tmp_9); + assign mux_7_nl = MUX_s_1_2_2(mux_tmp_4, (~ or_tmp_24), FpMul_8U_23U_lor_1_lpi_1_dfm_st_3); + assign mux_8_nl = MUX_s_1_2_2((mux_7_nl), (nor_23_nl), FpMul_8U_23U_lor_1_lpi_1_dfm_st_4); + assign or_33_nl = nor_4_cse | or_tmp_32; + assign mux_11_nl = MUX_s_1_2_2(mux_tmp_10, (or_33_nl), main_stage_v_2); + assign mux_12_nl = MUX_s_1_2_2((~ or_tmp_24), (mux_11_nl), main_stage_v_1); + assign and_10_nl = main_stage_v_1 & mux_tmp_10; + assign mux_13_nl = MUX_s_1_2_2((and_10_nl), (mux_12_nl), FpMul_8U_23U_or_2_cse); + assign mux_15_nl = MUX_s_1_2_2(mux_tmp_14, or_tmp_36, main_stage_v_2); + assign mux_16_nl = MUX_s_1_2_2((~ or_tmp_24), (mux_15_nl), main_stage_v_1); + assign and_11_nl = main_stage_v_1 & mux_tmp_14; + assign mux_17_nl = MUX_s_1_2_2((and_11_nl), (mux_16_nl), FpMul_8U_23U_or_2_cse); + assign and_93_nl = nand_8_cse & mux_24_cse; + assign mux_22_nl = MUX_s_1_2_2((and_93_nl), mux_24_cse, IsNaN_8U_23U_1_nor_tmp); + assign nor_21_nl = ~((~ main_stage_v_1) | IsNaN_8U_23U_land_lpi_1_dfm_st_3 | IsNaN_8U_23U_1_land_lpi_1_dfm_3); + assign mux_23_nl = MUX_s_1_2_2((nor_21_nl), (mux_22_nl), or_10_cse); + assign FpMul_8U_23U_xor_1_nl = (chn_a_rsci_d_mxwt[31]) ^ (chn_b_rsci_d_mxwt[31]); + assign nor_31_nl = ~(IsNaN_8U_23U_1_nor_tmp | (~((chn_b_rsci_d_mxwt[30:23]==8'b11111111) + & mux_24_cse))); + assign mux_25_nl = MUX_s_1_2_2(and_cse, (nor_31_nl), or_45_cse); + assign mux_26_nl = MUX_s_1_2_2(or_65_cse, (~ main_stage_v_1), IsNaN_8U_23U_1_land_lpi_1_dfm_3); + assign mux_27_nl = MUX_s_1_2_2((mux_26_nl), or_65_cse, IsNaN_8U_23U_land_lpi_1_dfm_st_3); + assign mux_28_nl = MUX_s_1_2_2((~ (mux_27_nl)), (mux_25_nl), or_10_cse); + assign and_91_nl = (chn_a_rsci_d_mxwt[30:23]==8'b11111111); + assign mux_29_nl = MUX_s_1_2_2(or_tmp_51, (~ and_cse), and_91_nl); + assign mux_30_nl = MUX_s_1_2_2((mux_29_nl), or_tmp_51, IsNaN_8U_23U_nor_tmp); + assign nand_6_nl = ~(((~ FpMul_8U_23U_lor_1_lpi_1_dfm_st_3) | IsNaN_8U_23U_land_lpi_1_dfm_st_3) + & main_stage_v_1); + assign mux_31_nl = MUX_s_1_2_2((nand_6_nl), (mux_30_nl), or_10_cse); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_3_2; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [2:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + MUX1HOT_v_8_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [45:0] MUX_v_46_2_2; + input [45:0] input_0; + input [45:0] input_1; + input [0:0] sel; + reg [45:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_46_2_2 = result; + end + endfunction + function [47:0] MUX_v_48_2_2; + input [47:0] input_0; + input [47:0] input_1; + input [0:0] sel; + reg [47:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_48_2_2 = result; + end + endfunction + function [7:0] MUX_v_8_2_2; + input [7:0] input_0; + input [7:0] input_1; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + function [0:0] readslicef_10_1_9; + input [9:0] vector; + reg [9:0] tmp; + begin + tmp = vector >> 9; + readslicef_10_1_9 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [7:0] readslicef_9_8_1; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 1; + readslicef_9_8_1 = tmp[7:0]; + end + endfunction + function [22:0] signext_23_1; + input [0:0] vector; + begin + signext_23_1= {{22{vector[0]}}, vector}; + end + endfunction + function [9:0] conv_s2s_9_10 ; + input [8:0] vector ; + begin + conv_s2s_9_10 = {vector[8], vector}; + end + endfunction + function [8:0] conv_u2s_8_9 ; + input [7:0] vector ; + begin + conv_u2s_8_9 = {1'b0, vector}; + end + endfunction + function [9:0] conv_u2s_8_10 ; + input [7:0] vector ; + begin + conv_u2s_8_10 = {{2{1'b0}}, vector}; + end + endfunction + function [22:0] conv_u2u_1_23 ; + input [0:0] vector ; + begin + conv_u2u_1_23 = {{22{1'b0}}, vector}; + end + endfunction + function [8:0] conv_u2u_8_9 ; + input [7:0] vector ; + begin + conv_u2u_8_9 = {1'b0, vector}; + end + endfunction + function [47:0] conv_u2u_48_48 ; + input [47:0] vector ; + begin + conv_u2u_48_48 = vector; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_mul +// ------------------------------------------------------------------ +module HLS_fp32_mul ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP32_MUL_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP32_MUL_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP32_MUL_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_mul_core HLS_fp32_mul_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_sub.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_sub.v new file mode 100644 index 0000000..59ccae9 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_sub.v @@ -0,0 +1,1815 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_sub.v +module FP32_SUB_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_SUB_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_SUB_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP32_SUB_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_SUB_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:52:55 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_leading_sign_49_0 +// ------------------------------------------------------------------ +module FP32_SUB_leading_sign_49_0 ( + mantissa, rtn +); + input [48:0] mantissa; + output [5:0] rtn; +// Interconnect Declarations + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_12; + wire c_h_1_13; + wire c_h_1_14; + wire c_h_1_17; + wire c_h_1_20; + wire c_h_1_21; + wire c_h_1_22; + wire c_h_1_23; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[46:45]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[48:47]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[44:43]!=2'b00)); + assign c_h_1_2 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[42:41]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[38:37]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[40:39]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[36:35]!=2'b00)); + assign c_h_1_5 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[34:33]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[30:29]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[32:31]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 = ~((mantissa[28:27]!=2'b00)); + assign c_h_1_9 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3 = (mantissa[26:25]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 = ~((mantissa[24:23]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 = ~((mantissa[20:19]!=2'b00)); + assign c_h_1_12 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + assign c_h_1_13 = c_h_1_9 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + assign c_h_1_14 = c_h_1_6 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5 = (mantissa[18:17]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 & c_h_1_12 & c_h_1_13; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 = ~((mantissa[16:15]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 = ~((mantissa[12:11]!=2'b00)); + assign c_h_1_17 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3 = (mantissa[10:9]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 = ~((mantissa[8:7]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 = ~((mantissa[4:3]!=2'b00)); + assign c_h_1_20 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + assign c_h_1_21 = c_h_1_17 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4 = (mantissa[2:1]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 & c_h_1_20; + assign c_h_1_22 = c_h_1_21 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + assign c_h_1_23 = c_h_1_14 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl = c_h_1_14 & (c_h_1_22 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl = c_h_1_6 & (c_h_1_13 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4)) & (~((~(c_h_1_21 + & (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4))) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl = c_h_1_2 & (c_h_1_5 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3)) & (~((~(c_h_1_9 + & (c_h_1_12 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3)))) + & c_h_1_14)) & (~(((~(c_h_1_17 & (c_h_1_20 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2)) & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2)))) + & c_h_1_13)))) & c_h_1_14)) & (~(((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2)))) & c_h_1_21)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl + = ((~((mantissa[48]) | (~((mantissa[47:46]!=2'b01))))) & (~(((mantissa[44]) + | (~((mantissa[43:42]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[40]) | (~((mantissa[39:38]!=2'b01))))) + & (~(((mantissa[36]) | (~((mantissa[35:34]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[32]) | (~((mantissa[31:30]!=2'b01))))) & (~(((mantissa[28]) + | (~((mantissa[27:26]!=2'b01)))) & c_h_1_9)) & (~((~((~((mantissa[24]) | (~((mantissa[23:22]!=2'b01))))) + & (~(((mantissa[20]) | (~((mantissa[19:18]!=2'b01)))) & c_h_1_12)))) & c_h_1_13)))) + & c_h_1_14)) & (~(((~((~((mantissa[16]) | (~((mantissa[15:14]!=2'b01))))) & + (~(((mantissa[12]) | (~((mantissa[11:10]!=2'b01)))) & c_h_1_17)) & (~((~((~((mantissa[8]) + | (~((mantissa[7:6]!=2'b01))))) & (~(((mantissa[4]) | (~((mantissa[3:2]!=2'b01)))) + & c_h_1_20)))) & c_h_1_21)))) | c_h_1_22) & c_h_1_23))) | ((~ (mantissa[0])) + & c_h_1_22 & c_h_1_23); + assign rtn = {c_h_1_23 , (IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:53:28 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_SUB_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP32_SUB_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_SUB_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_sub_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_sub_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [31:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [31:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [31:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_32_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 32'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_SUB_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [31:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [31:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core +// ------------------------------------------------------------------ +module HLS_fp32_sub_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [31:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [7:0] chn_o_rsci_d_30_23; + reg [22:0] chn_o_rsci_d_22_0; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + wire FpAdd_8U_23U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_49U_24U_else_and_tmp; + wire IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + wire IsNaN_8U_23U_1_nor_tmp; + wire nor_tmp_1; + wire or_tmp_3; + wire mux_tmp_5; + wire nor_tmp_11; + wire or_tmp_16; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire and_dcpl_29; + wire and_dcpl_33; + wire or_tmp_29; + wire or_tmp_35; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_4; + reg [31:0] b_sva_36; + reg [31:0] FpAdd_8U_23U_a_sva_36; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_4; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_6; + reg [48:0] FpAdd_8U_23U_a_int_mant_p1_sva_2; + reg [48:0] FpAdd_8U_23U_b_int_mant_p1_sva_2; + reg FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3; + reg [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2; + reg IsNaN_8U_23U_land_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_6; + reg FpAdd_8U_23U_IsZero_8U_23U_or_itm_2; + reg FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2; + reg FpNormalize_8U_49U_if_or_itm_2; + reg IsNaN_8U_23U_1_nor_itm_2; + reg IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + reg FpAdd_8U_23U_mux_1_itm_2; + reg FpAdd_8U_23U_mux_13_itm_3; + reg FpAdd_8U_23U_mux_13_itm_4; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4; + reg IsNaN_8U_23U_land_lpi_1_dfm_st_4; + wire FpAdd_8U_23U_mux_2_tmp_49; + wire main_stage_en_1; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm; + wire [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + wire [7:0] FpAdd_8U_23U_o_expo_lpi_1_dfm_2; + reg reg_chn_a_rsci_iswt0_cse; + reg reg_chn_a_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_36_cse; + wire FpAdd_8U_23U_or_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + wire FpSignedBitsToFloat_8U_23U_1_and_rgt; + wire FpSignedBitsToFloat_8U_23U_1_and_1_rgt; + wire [48:0] FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + wire [48:0] FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + wire [48:0] FpNormalize_8U_49U_else_lshift_itm; + wire chn_o_rsci_d_22_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + wire [48:0] FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0; + wire [48:0] FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [49:0] FpAdd_8U_23U_asn_5_mx0w0; + wire [50:0] nl_FpAdd_8U_23U_asn_5_mx0w0; + wire [49:0] FpAdd_8U_23U_asn_4_mx0w1; + wire [51:0] nl_FpAdd_8U_23U_asn_4_mx0w1; + wire [48:0] FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0; + wire FpMantRNE_49U_24U_else_carry_sva; + wire FpAdd_8U_23U_and_tmp; + wire [7:0] FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm; + wire [7:0] FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm; + wire FpNormalize_8U_49U_oelse_not_3; + wire [5:0] libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1; + wire FpAdd_8U_23U_is_addition_and_cse; + wire FpAdd_8U_23U_and_8_cse; + wire IsNaN_8U_23U_aelse_and_cse; + wire FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse; + wire FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse; + wire IsNaN_8U_23U_1_and_cse; + reg reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse; + wire mux_13_cse; + wire mux_4_cse; + wire FpSignedBitsToFloat_8U_23U_1_and_3_cse; + wire FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + wire FpAdd_8U_23U_if_3_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_if_4_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1; + wire[22:0] FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl; + wire[22:0] FpMantRNE_49U_24U_else_acc_nl; + wire[23:0] nl_FpMantRNE_49U_24U_else_acc_nl; + wire[0:0] FpSignedBitsToFloat_8U_23U_1_and_2_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_nl; + wire[0:0] FpAdd_8U_23U_and_3_nl; + wire[0:0] FpAdd_8U_23U_and_7_nl; + wire[0:0] mux_6_nl; + wire[0:0] mux_8_nl; + wire[0:0] mux_7_nl; + wire[0:0] nor_37_nl; + wire[0:0] nor_7_nl; + wire[0:0] mux_10_nl; + wire[0:0] or_10_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_34_nl; + wire[0:0] and_67_nl; + wire[0:0] mux_23_nl; + wire[0:0] mux_22_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_25_nl; + wire[0:0] mux_24_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_27_nl; + wire[0:0] nor_28_nl; + wire[0:0] nor_29_nl; + wire[0:0] mux_28_nl; + wire[0:0] nor_26_nl; + wire[0:0] nor_27_nl; + wire[8:0] FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[10:0] nl_FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[7:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl; + wire[7:0] FpNormalize_8U_49U_else_acc_nl; + wire[9:0] nl_FpNormalize_8U_49U_else_acc_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_1_nl; + wire[0:0] FpAdd_8U_23U_and_2_nl; + wire[48:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl; + wire[0:0] FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[7:0] FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[7:0] FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[0:0] FpAdd_8U_23U_is_a_greater_oelse_not_5_nl; + wire[8:0] FpNormalize_8U_49U_acc_nl; + wire[10:0] nl_FpNormalize_8U_49U_acc_nl; + wire[0:0] nor_38_nl; + wire[23:0] FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; + wire[25:0] nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 + , (FpAdd_8U_23U_a_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_a_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_a_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_a_left_shift_acc_nl = nl_FpAdd_8U_23U_a_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_a_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[0]))}; + wire [23:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 + , (b_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_b_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_b_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_b_left_shift_acc_nl = nl_FpAdd_8U_23U_b_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_b_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[0]))}; + wire [48:0] nl_FpNormalize_8U_49U_else_lshift_rg_a; + assign nl_FpNormalize_8U_49U_else_lshift_rg_a = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [48:0] nl_leading_sign_49_0_rg_mantissa; + assign nl_leading_sign_49_0_rg_mantissa = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [31:0] nl_HLS_fp32_sub_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_sub_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 , chn_o_rsci_d_30_23 + , chn_o_rsci_d_22_0}; + FP32_SUB_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_a_int_mant_p1_lshift_itm) + ); + FP32_SUB_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_b_int_mant_p1_lshift_itm) + ); + FP32_SUB_mgc_shift_l_v4 #(.width_a(32'sd49), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd49)) FpNormalize_8U_49U_else_lshift_rg ( + .a(nl_FpNormalize_8U_49U_else_lshift_rg_a[48:0]), + .s(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1), + .z(FpNormalize_8U_49U_else_lshift_itm) + ); + FP32_SUB_leading_sign_49_0 leading_sign_49_0_rg ( + .mantissa(nl_leading_sign_49_0_rg_mantissa[48:0]), + .rtn(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + ); + HLS_fp32_sub_core_chn_a_rsci HLS_fp32_sub_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_sub_core_chn_b_rsci HLS_fp32_sub_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp32_sub_core_chn_o_rsci HLS_fp32_sub_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_sub_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp32_sub_core_staller HLS_fp32_sub_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_sub_core_core_fsm HLS_fp32_sub_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_8U_23U_or_cse = IsNaN_8U_23U_1_land_lpi_1_dfm_4 | IsNaN_8U_23U_land_lpi_1_dfm_6; + assign IsNaN_8U_23U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_13_cse; + assign FpAdd_8U_23U_is_addition_and_cse = core_wen & (~ and_dcpl_7) & mux_4_cse; + assign mux_4_cse = MUX_s_1_2_2(main_stage_v_1, main_stage_v_2, nor_36_cse); + assign mux_6_nl = MUX_s_1_2_2(mux_tmp_5, or_tmp_3, main_stage_v_3); + assign FpAdd_8U_23U_and_8_cse = core_wen & (~ and_dcpl_7) & (mux_6_nl); + assign nor_36_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_10_nl = nor_36_cse | nor_tmp_11; + assign nor_34_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_11)); + assign mux_9_nl = MUX_s_1_2_2((nor_34_nl), nor_tmp_11, chn_o_rsci_bawt); + assign and_67_nl = FpAdd_8U_23U_or_cse & main_stage_v_3; + assign mux_10_nl = MUX_s_1_2_2((mux_9_nl), (or_10_nl), and_67_nl); + assign FpSignedBitsToFloat_8U_23U_1_and_3_cse = core_wen & (~ and_dcpl_7) & (mux_10_nl); + assign FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse = ((~ FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1) + & FpAdd_8U_23U_is_a_greater_oif_equal_tmp) | FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + assign mux_13_cse = MUX_s_1_2_2(nor_tmp_1, main_stage_v_1, nor_36_cse); + assign FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse = and_dcpl_28 + | and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_1_and_rgt = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0) + & and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_1_and_1_rgt = IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 + & and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse = (FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse + & or_cse) | and_dcpl_33; + assign nor_26_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~ main_stage_v_1)); + assign nor_27_nl = ~(IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_28_nl = MUX_s_1_2_2((nor_27_nl), (nor_26_nl), nor_36_cse); + assign IsNaN_8U_23U_1_and_cse = core_wen & (~ and_dcpl_7) & (mux_28_nl); + assign IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000))) + | (chn_a_rsci_d_mxwt[30:23]!=8'b11111111)); + assign FpAdd_8U_23U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[30:23]) == + (chn_b_rsci_d_mxwt[30:23]); + assign IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2); + assign IsNaN_8U_23U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp = ~((chn_b_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpAdd_8U_23U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[30:23])}) + + conv_u2u_8_9(~ (chn_a_rsci_d_mxwt[30:23])) + 9'b1; + assign FpAdd_8U_23U_is_a_greater_acc_1_nl = nl_FpAdd_8U_23U_is_a_greater_acc_1_nl[8:0]; + assign FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1 = readslicef_9_1_8((FpAdd_8U_23U_is_a_greater_acc_1_nl)); + assign FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_b_int_mant_p1_sva_2, + FpAdd_8U_23U_a_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_a_int_mant_p1_sva_2, + FpAdd_8U_23U_b_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign nl_FpAdd_8U_23U_asn_5_mx0w0 = conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + + conv_u2u_49_50(FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0); + assign FpAdd_8U_23U_asn_5_mx0w0 = nl_FpAdd_8U_23U_asn_5_mx0w0[49:0]; + assign nl_FpAdd_8U_23U_asn_4_mx0w1 = ({1'b1 , (~ FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0)}) + + conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + 50'b1; + assign FpAdd_8U_23U_asn_4_mx0w1 = nl_FpAdd_8U_23U_asn_4_mx0w1[49:0]; + assign FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0 = MUX_v_50_2_2(FpAdd_8U_23U_asn_4_mx0w1, + FpAdd_8U_23U_asn_5_mx0w0, reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse); + assign nl_FpAdd_8U_23U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_qr_lpi_1_dfm_6[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_1_nl = nl_FpAdd_8U_23U_if_3_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_3_if_acc_1_nl)); + assign nl_FpNormalize_8U_49U_else_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + ({2'b11 + , (~ libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1)}) + + 8'b1; + assign FpNormalize_8U_49U_else_acc_nl = nl_FpNormalize_8U_49U_else_acc_nl[7:0]; + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl = MUX_v_8_2_2(8'b00000000, + (FpNormalize_8U_49U_else_acc_nl), FpNormalize_8U_49U_oelse_not_3); + assign nl_FpAdd_8U_23U_if_3_if_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_nl = nl_FpAdd_8U_23U_if_3_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_1_nl = (~ FpAdd_8U_23U_if_3_if_acc_1_itm_7_1) & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_and_2_nl = FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_o_expo_lpi_1_dfm_2 = MUX1HOT_v_8_3_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl), + FpAdd_8U_23U_qr_lpi_1_dfm_6, (FpAdd_8U_23U_if_3_if_acc_nl), {(~ (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49])) + , (FpAdd_8U_23U_and_1_nl) , (FpAdd_8U_23U_and_2_nl)}); + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl = MUX_v_49_2_2(49'b0000000000000000000000000000000000000000000000000, + FpNormalize_8U_49U_else_lshift_itm, FpNormalize_8U_49U_oelse_not_3); + assign FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0 = MUX_v_49_2_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl), + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49:1]), FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpMantRNE_49U_24U_else_carry_sva = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[24]) + & ((FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[0]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[1]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[2]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[3]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[4]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[5]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[6]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[7]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[8]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[9]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[10]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[11]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[12]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[13]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[14]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[15]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[16]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[17]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[18]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[19]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[20]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[21]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[22]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[23]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[25])); + assign FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm + | (~ FpAdd_8U_23U_if_4_if_acc_1_itm_7_1); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_8U_23U_is_inf_lpi_1_dfm, + (FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl), FpMantRNE_49U_24U_else_and_tmp); + assign nl_FpAdd_8U_23U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_o_expo_lpi_1_dfm_2[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_1_nl = nl_FpAdd_8U_23U_if_4_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_4_if_acc_1_nl)); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm = ~(FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 | (~ + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]))); + assign FpAdd_8U_23U_and_tmp = FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 & FpMantRNE_49U_24U_else_and_tmp; + assign FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c = ~(IsNaN_8U_23U_1_land_lpi_1_dfm_4 + | IsNaN_8U_23U_land_lpi_1_dfm_6); + assign FpMantRNE_49U_24U_else_and_tmp = FpMantRNE_49U_24U_else_carry_sva & (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[48:25]==24'b111111111111111111111111); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign main_stage_en_1 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_cse; + assign nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl = (FpAdd_8U_23U_a_sva_36[30:23]) + - (b_sva_36[30:23]); + assign FpAdd_8U_23U_b_right_shift_qif_acc_nl = nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl[7:0]; + assign FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_b_right_shift_qif_acc_nl), + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4); + assign nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl = (b_sva_36[30:23]) - (FpAdd_8U_23U_a_sva_36[30:23]); + assign FpAdd_8U_23U_a_right_shift_qelse_acc_nl = nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl[7:0]; + assign FpAdd_8U_23U_is_a_greater_oelse_not_5_nl = ~ FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + assign FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_a_right_shift_qelse_acc_nl), + (FpAdd_8U_23U_is_a_greater_oelse_not_5_nl)); + assign nl_FpNormalize_8U_49U_acc_nl = ({1'b1 , (~ FpAdd_8U_23U_qr_lpi_1_dfm_6)}) + + conv_u2s_6_9(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + + 9'b1; + assign FpNormalize_8U_49U_acc_nl = nl_FpNormalize_8U_49U_acc_nl[8:0]; + assign FpNormalize_8U_49U_oelse_not_3 = FpNormalize_8U_49U_if_or_itm_2 & (readslicef_9_1_8((FpNormalize_8U_49U_acc_nl))); + assign FpAdd_8U_23U_mux_2_tmp_49 = MUX_s_1_2_2((FpAdd_8U_23U_asn_4_mx0w1[49]), + (FpAdd_8U_23U_asn_5_mx0w0[49]), reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse); + assign nor_tmp_1 = chn_b_rsci_bawt & chn_a_rsci_bawt; + assign or_tmp_3 = nor_36_cse | main_stage_v_2; + assign nor_38_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_tmp_5 = MUX_s_1_2_2((nor_38_nl), main_stage_v_2, chn_o_rsci_bawt); + assign nor_tmp_11 = (IsNaN_8U_23U_1_land_lpi_1_dfm_3 | IsNaN_8U_23U_land_lpi_1_dfm_5) + & main_stage_v_2; + assign or_tmp_16 = IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign and_dcpl_28 = or_cse & IsNaN_8U_23U_land_lpi_1_dfm_st_4; + assign and_dcpl_29 = or_cse & (~ IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign and_dcpl_33 = or_cse & (~ FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1) & (FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 + | (~ FpAdd_8U_23U_is_a_greater_oif_equal_tmp)); + assign or_tmp_29 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_35 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_cse & (fsm_output[1]); + assign chn_o_rsci_d_22_0_mx0c1 = or_cse & main_stage_v_3 & (~ IsNaN_8U_23U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_a_rsci_bawt & chn_b_rsci_bawt)) & main_stage_v_1 + & or_cse; + assign main_stage_v_2_mx0c1 = main_stage_v_2 & (~ main_stage_v_1) & or_cse; + assign main_stage_v_3_mx0c1 = or_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[22:0])}) + + conv_u2u_23_24(~ (chn_b_rsci_d_mxwt[22:0])) + 24'b1; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl[23:0]; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 = readslicef_24_1_23((FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_35; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_a_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_29 ) begin + reg_chn_a_rsci_ld_core_psct_cse <= or_tmp_29; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_0 <= 23'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_3 & IsNaN_8U_23U_land_lpi_1_dfm_6) + | chn_o_rsci_d_22_0_mx0c1) ) begin + chn_o_rsci_d_22_0 <= MUX_v_23_2_2(FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4, + (FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl), FpSignedBitsToFloat_8U_23U_1_and_2_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_23 <= 8'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_30_23 <= MUX1HOT_v_8_4_2(FpAdd_8U_23U_o_expo_lpi_1_dfm_2, (FpAdd_8U_23U_if_4_if_acc_nl), + 8'b11111110, FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4, + {(FpAdd_8U_23U_and_nl) , (FpAdd_8U_23U_and_3_nl) , (FpAdd_8U_23U_and_7_nl) + , FpAdd_8U_23U_or_cse}); + chn_o_rsci_d_31 <= FpAdd_8U_23U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_35 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= 1'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3 + <= 1'b0; + FpAdd_8U_23U_a_sva_36 <= 32'b0; + b_sva_36 <= 32'b0; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= 1'b0; + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_aelse_and_cse ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3 + <= (chn_a_rsci_d_mxwt[31]) ^ (chn_b_rsci_d_mxwt[31]); + FpAdd_8U_23U_a_sva_36 <= chn_a_rsci_d_mxwt; + b_sva_36 <= chn_b_rsci_d_mxwt; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= (chn_a_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse + <= 1'b0; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= 1'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= 1'b0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= 8'b0; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= 1'b0; + end + else if ( FpAdd_8U_23U_is_addition_and_cse ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse + <= FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= FpAdd_8U_23U_qr_lpi_1_dfm_4; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= IsNaN_8U_23U_land_lpi_1_dfm_st_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_2) | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= 8'b0; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= 50'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_mux_13_itm_4 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= 1'b0; + end + else if ( FpAdd_8U_23U_and_8_cse ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= FpAdd_8U_23U_qr_lpi_1_dfm_5; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= IsNaN_8U_23U_1_land_lpi_1_dfm_3; + FpAdd_8U_23U_mux_13_itm_4 <= FpAdd_8U_23U_mux_13_itm_3; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= IsNaN_8U_23U_land_lpi_1_dfm_5; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpNormalize_8U_49U_if_or_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_8_nl) ) begin + FpNormalize_8U_49U_if_or_itm_2 <= (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0[48:0]!=49'b0000000000000000000000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= 23'b0; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= 8'b0; + end + else if ( FpSignedBitsToFloat_8U_23U_1_and_3_cse ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_23_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= MUX_v_8_2_2((FpAdd_8U_23U_a_sva_36[30:23]), (b_sva_36[30:23]), and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= 23'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_25_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= MUX_v_23_2_2((FpAdd_8U_23U_a_sva_36[22:0]), (b_sva_36[22:0]), and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_13_itm_3 <= 1'b0; + end + else if ( core_wen & (and_dcpl_28 | FpSignedBitsToFloat_8U_23U_1_and_rgt | FpSignedBitsToFloat_8U_23U_1_and_1_rgt) + & mux_4_cse ) begin + FpAdd_8U_23U_mux_13_itm_3 <= MUX1HOT_s_1_3_2((FpAdd_8U_23U_a_sva_36[31]), FpAdd_8U_23U_mux_1_itm_2, + (~ (b_sva_36[31])), {and_dcpl_28 , FpSignedBitsToFloat_8U_23U_1_and_rgt + , FpSignedBitsToFloat_8U_23U_1_and_1_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse & mux_13_cse + ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= MUX_v_8_2_2((chn_a_rsci_d_mxwt[30:23]), (chn_b_rsci_d_mxwt[30:23]), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_1_itm_2 <= 1'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse & (mux_27_nl) + ) begin + FpAdd_8U_23U_mux_1_itm_2 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[31]), (~ (chn_b_rsci_d_mxwt[31])), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_1_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_1_and_cse ) begin + IsNaN_8U_23U_1_nor_itm_2 <= IsNaN_8U_23U_1_nor_tmp; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + end + end + assign nl_FpMantRNE_49U_24U_else_acc_nl = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[47:25]) + + conv_u2u_1_23(FpMantRNE_49U_24U_else_carry_sva); + assign FpMantRNE_49U_24U_else_acc_nl = nl_FpMantRNE_49U_24U_else_acc_nl[22:0]; + assign FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl = MUX_v_23_2_2((FpMantRNE_49U_24U_else_acc_nl), + 23'b11111111111111111111111, FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0); + assign FpSignedBitsToFloat_8U_23U_1_and_2_nl = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_4) + & chn_o_rsci_d_22_0_mx0c1; + assign nl_FpAdd_8U_23U_if_4_if_acc_nl = FpAdd_8U_23U_o_expo_lpi_1_dfm_2 + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_nl = nl_FpAdd_8U_23U_if_4_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_nl = (~(FpAdd_8U_23U_and_tmp | FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_3_nl = FpAdd_8U_23U_and_tmp & (~ FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_7_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign mux_7_nl = MUX_s_1_2_2(or_tmp_3, nor_36_cse, FpAdd_8U_23U_mux_2_tmp_49); + assign nor_37_nl = ~(FpAdd_8U_23U_mux_2_tmp_49 | (~ mux_tmp_5)); + assign nor_7_nl = ~((FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]) | (~ main_stage_v_3)); + assign mux_8_nl = MUX_s_1_2_2((nor_37_nl), (mux_7_nl), nor_7_nl); + assign nor_32_nl = ~(or_tmp_16 | (~ main_stage_v_1)); + assign mux_22_nl = MUX_s_1_2_2((nor_32_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_23_nl = MUX_s_1_2_2((mux_22_nl), nor_tmp_11, nor_36_cse); + assign nor_31_nl = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 + | (~ main_stage_v_1)); + assign mux_24_nl = MUX_s_1_2_2((nor_31_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_25_nl = MUX_s_1_2_2((mux_24_nl), nor_tmp_11, nor_36_cse); + assign nor_28_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~(or_tmp_16 & main_stage_v_1))); + assign nor_29_nl = ~((~(IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp | IsNaN_8U_23U_1_nor_tmp)) + | IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_27_nl = MUX_s_1_2_2((nor_29_nl), (nor_28_nl), nor_36_cse); + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_3_2; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [2:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + MUX1HOT_v_8_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_4_2; + input [7:0] input_3; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [3:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + result = result | ( input_3 & {8{sel[3]}}); + MUX1HOT_v_8_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [48:0] MUX_v_49_2_2; + input [48:0] input_0; + input [48:0] input_1; + input [0:0] sel; + reg [48:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_49_2_2 = result; + end + endfunction + function [49:0] MUX_v_50_2_2; + input [49:0] input_0; + input [49:0] input_1; + input [0:0] sel; + reg [49:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_50_2_2 = result; + end + endfunction + function [7:0] MUX_v_8_2_2; + input [7:0] input_0; + input [7:0] input_1; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + function [0:0] readslicef_24_1_23; + input [23:0] vector; + reg [23:0] tmp; + begin + tmp = vector >> 23; + readslicef_24_1_23 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [8:0] conv_u2s_6_9 ; + input [5:0] vector ; + begin + conv_u2s_6_9 = {{3{1'b0}}, vector}; + end + endfunction + function [22:0] conv_u2u_1_23 ; + input [0:0] vector ; + begin + conv_u2u_1_23 = {{22{1'b0}}, vector}; + end + endfunction + function [8:0] conv_u2u_8_9 ; + input [7:0] vector ; + begin + conv_u2u_8_9 = {1'b0, vector}; + end + endfunction + function [23:0] conv_u2u_23_24 ; + input [22:0] vector ; + begin + conv_u2u_23_24 = {1'b0, vector}; + end + endfunction + function [49:0] conv_u2u_49_50 ; + input [48:0] vector ; + begin + conv_u2u_49_50 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub +// ------------------------------------------------------------------ +module HLS_fp32_sub ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP32_SUB_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP32_SUB_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP32_SUB_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_sub_core HLS_fp32_sub_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_sub.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_sub.v.vcp new file mode 100644 index 0000000..59ccae9 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_sub.v.vcp @@ -0,0 +1,1815 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_sub.v +module FP32_SUB_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_SUB_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_SUB_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_bl_beh_v4.v +module FP32_SUB_mgc_shift_bl_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate if ( signd_a ) + begin: SIGNED + assign z = fshl_s(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_s(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +//Shift left - signed shift argument + function [width_z-1:0] fshl_s; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + reg [width_a:0] sbit_arg1; + begin +// Ignoring the possibility that arg2[width_s-1] could be X +// because of customer complaints regarding X'es in simulation results + if ( arg2[width_s-1] == 1'b0 ) + begin + sbit_arg1[width_a:0] = {(width_a+1){1'b0}}; + fshl_s = fshl_u(arg1, arg2, sbit); + end + else + begin + sbit_arg1[width_a] = sbit; + sbit_arg1[width_a-1:0] = arg1; + fshl_s = fshr_u(sbit_arg1[width_a:1], ~arg2, sbit); + end + end + endfunction +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_SUB_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:52:55 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_leading_sign_49_0 +// ------------------------------------------------------------------ +module FP32_SUB_leading_sign_49_0 ( + mantissa, rtn +); + input [48:0] mantissa; + output [5:0] rtn; +// Interconnect Declarations + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1; + wire IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire c_h_1_9; + wire c_h_1_12; + wire c_h_1_13; + wire c_h_1_14; + wire c_h_1_17; + wire c_h_1_20; + wire c_h_1_21; + wire c_h_1_22; + wire c_h_1_23; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl; + wire[0:0] IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[46:45]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[48:47]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[44:43]!=2'b00)); + assign c_h_1_2 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[42:41]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[38:37]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[40:39]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[36:35]!=2'b00)); + assign c_h_1_5 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4 = (mantissa[34:33]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2 = ~((mantissa[30:29]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 = ~((mantissa[32:31]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 = ~((mantissa[28:27]!=2'b00)); + assign c_h_1_9 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3 = (mantissa[26:25]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2 = ~((mantissa[22:21]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 = ~((mantissa[24:23]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 = ~((mantissa[20:19]!=2'b00)); + assign c_h_1_12 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2; + assign c_h_1_13 = c_h_1_9 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3; + assign c_h_1_14 = c_h_1_6 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5 = (mantissa[18:17]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 & c_h_1_12 & c_h_1_13; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2 = ~((mantissa[14:13]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 = ~((mantissa[16:15]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 = ~((mantissa[12:11]!=2'b00)); + assign c_h_1_17 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3 = (mantissa[10:9]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2 = ~((mantissa[6:5]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 = ~((mantissa[8:7]!=2'b00)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 = ~((mantissa[4:3]!=2'b00)); + assign c_h_1_20 = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2; + assign c_h_1_21 = c_h_1_17 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3; + assign IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4 = (mantissa[2:1]==2'b00) + & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 & c_h_1_20; + assign c_h_1_22 = c_h_1_21 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4; + assign c_h_1_23 = c_h_1_14 & IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5; + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl = c_h_1_14 & (c_h_1_22 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_90_5_sdt_5)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl = c_h_1_6 & (c_h_1_13 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_42_4_sdt_4)) & (~((~(c_h_1_21 + & (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_134_4_sdt_4))) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl = c_h_1_2 & (c_h_1_5 | + (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_18_3_sdt_3)) & (~((~(c_h_1_9 + & (c_h_1_12 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_62_3_sdt_3)))) + & c_h_1_14)) & (~(((~(c_h_1_17 & (c_h_1_20 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_110_3_sdt_3)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl = IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_58_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_50_2_sdt_2)) & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_78_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_70_2_sdt_2)))) + & c_h_1_13)))) & c_h_1_14)) & (~(((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_1 + & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_106_2_sdt_1 | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_98_2_sdt_2)) + & (~((~(IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_1 & (IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_126_2_sdt_1 + | (~ IntLeadZero_49U_leading_sign_49_0_rtn_wrs_c_118_2_sdt_2)))) & c_h_1_21)))) + | c_h_1_22) & c_h_1_23)); + assign IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl + = ((~((mantissa[48]) | (~((mantissa[47:46]!=2'b01))))) & (~(((mantissa[44]) + | (~((mantissa[43:42]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[40]) | (~((mantissa[39:38]!=2'b01))))) + & (~(((mantissa[36]) | (~((mantissa[35:34]!=2'b01)))) & c_h_1_5)))) & c_h_1_6)) + & (~((~((~((mantissa[32]) | (~((mantissa[31:30]!=2'b01))))) & (~(((mantissa[28]) + | (~((mantissa[27:26]!=2'b01)))) & c_h_1_9)) & (~((~((~((mantissa[24]) | (~((mantissa[23:22]!=2'b01))))) + & (~(((mantissa[20]) | (~((mantissa[19:18]!=2'b01)))) & c_h_1_12)))) & c_h_1_13)))) + & c_h_1_14)) & (~(((~((~((mantissa[16]) | (~((mantissa[15:14]!=2'b01))))) & + (~(((mantissa[12]) | (~((mantissa[11:10]!=2'b01)))) & c_h_1_17)) & (~((~((~((mantissa[8]) + | (~((mantissa[7:6]!=2'b01))))) & (~(((mantissa[4]) | (~((mantissa[3:2]!=2'b01)))) + & c_h_1_20)))) & c_h_1_21)))) | c_h_1_22) & c_h_1_23))) | ((~ (mantissa[0])) + & c_h_1_22 & c_h_1_23); + assign rtn = {c_h_1_23 , (IntLeadZero_49U_leading_sign_49_0_rtn_and_189_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_187_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_and_194_nl) , (IntLeadZero_49U_leading_sign_49_0_rtn_and_195_nl) + , (IntLeadZero_49U_leading_sign_49_0_rtn_IntLeadZero_49U_leading_sign_49_0_rtn_or_1_nl)}; +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-184 +// Generated date: Fri Jun 16 21:53:28 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_SUB_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_chn_b_rsci_unreg +// ------------------------------------------------------------------ +module FP32_SUB_chn_b_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_SUB_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_SUB_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_sub_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_sub_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_b_rsci_wen_comp, + chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_b_rsci_wen_comp; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_b_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_d_mxwt, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + output [31:0] chn_b_rsci_d_mxwt; + input chn_b_rsci_biwt; + input chn_b_rsci_bdwt; + input [31:0] chn_b_rsci_d; +// Interconnect Declarations + reg chn_b_rsci_bcwt; + reg [31:0] chn_b_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_bawt = chn_b_rsci_biwt | chn_b_rsci_bcwt; + assign chn_b_rsci_wen_comp = (~ chn_b_rsci_oswt) | chn_b_rsci_bawt; + assign chn_b_rsci_d_mxwt = MUX_v_32_2_2(chn_b_rsci_d, chn_b_rsci_d_bfwt, chn_b_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_bcwt <= 1'b0; + chn_b_rsci_d_bfwt <= 32'b0; + end + else begin + chn_b_rsci_bcwt <= ~((~(chn_b_rsci_bcwt | chn_b_rsci_biwt)) | chn_b_rsci_bdwt); + chn_b_rsci_d_bfwt <= chn_b_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsci_oswt, core_wen, core_wten, chn_b_rsci_iswt0, + chn_b_rsci_ld_core_psct, chn_b_rsci_biwt, chn_b_rsci_bdwt, chn_b_rsci_ld_core_sct, + chn_b_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + input chn_b_rsci_ld_core_psct; + output chn_b_rsci_biwt; + output chn_b_rsci_bdwt; + output chn_b_rsci_ld_core_sct; + input chn_b_rsci_vd; +// Interconnect Declarations + wire chn_b_rsci_ogwt; + wire chn_b_rsci_pdswt0; + reg chn_b_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_b_rsci_pdswt0 = (~ core_wten) & chn_b_rsci_iswt0; + assign chn_b_rsci_biwt = chn_b_rsci_ogwt & chn_b_rsci_vd; + assign chn_b_rsci_ogwt = chn_b_rsci_pdswt0 | chn_b_rsci_icwt; + assign chn_b_rsci_bdwt = chn_b_rsci_oswt & core_wen; + assign chn_b_rsci_ld_core_sct = chn_b_rsci_ld_core_psct & chn_b_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_b_rsci_icwt <= 1'b0; + end + else begin + chn_b_rsci_icwt <= ~((~(chn_b_rsci_icwt | chn_b_rsci_pdswt0)) | chn_b_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [31:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_SUB_mgc_out_stdreg_wait_v1 #(.rscid(32'sd3), + .width(32'sd32)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_sub_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_b_rsci +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_b_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_b_rsc_z, chn_b_rsc_vz, chn_b_rsc_lz, chn_b_rsci_oswt, + core_wen, core_wten, chn_b_rsci_iswt0, chn_b_rsci_bawt, chn_b_rsci_wen_comp, + chn_b_rsci_ld_core_psct, chn_b_rsci_d_mxwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + input chn_b_rsci_oswt; + input core_wen; + input core_wten; + input chn_b_rsci_iswt0; + output chn_b_rsci_bawt; + output chn_b_rsci_wen_comp; + input chn_b_rsci_ld_core_psct; + output [31:0] chn_b_rsci_d_mxwt; +// Interconnect Declarations + wire chn_b_rsci_biwt; + wire chn_b_rsci_bdwt; + wire chn_b_rsci_ld_core_sct; + wire chn_b_rsci_vd; + wire [31:0] chn_b_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd2), + .width(32'sd32)) chn_b_rsci ( + .ld(chn_b_rsci_ld_core_sct), + .vd(chn_b_rsci_vd), + .d(chn_b_rsci_d), + .lz(chn_b_rsc_lz), + .vz(chn_b_rsc_vz), + .z(chn_b_rsc_z) + ); + HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(chn_b_rsci_iswt0), + .chn_b_rsci_ld_core_psct(chn_b_rsci_ld_core_psct), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_ld_core_sct(chn_b_rsci_ld_core_sct), + .chn_b_rsci_vd(chn_b_rsci_vd) + ); + HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp HLS_fp32_sub_core_chn_b_rsci_chn_b_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt), + .chn_b_rsci_biwt(chn_b_rsci_biwt), + .chn_b_rsci_bdwt(chn_b_rsci_bdwt), + .chn_b_rsci_d(chn_b_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_sub_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_SUB_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_sub_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub_core +// ------------------------------------------------------------------ +module HLS_fp32_sub_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, + chn_b_rsci_oswt, chn_o_rsci_oswt, chn_o_rsci_oswt_unreg, chn_a_rsci_oswt_unreg_pff +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + input chn_b_rsci_oswt; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; + output chn_a_rsci_oswt_unreg_pff; +// Interconnect Declarations + wire core_wen; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_b_rsci_bawt; + wire chn_b_rsci_wen_comp; + wire [31:0] chn_b_rsci_d_mxwt; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_31; + reg [7:0] chn_o_rsci_d_30_23; + reg [22:0] chn_o_rsci_d_22_0; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + wire FpAdd_8U_23U_is_a_greater_oif_equal_tmp; + wire FpMantRNE_49U_24U_else_and_tmp; + wire IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + wire IsNaN_8U_23U_1_nor_tmp; + wire nor_tmp_1; + wire or_tmp_3; + wire mux_tmp_5; + wire nor_tmp_11; + wire or_tmp_16; + wire and_dcpl_7; + wire and_dcpl_13; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire and_dcpl_29; + wire and_dcpl_33; + wire or_tmp_29; + wire or_tmp_35; + reg main_stage_v_1; + reg main_stage_v_2; + reg main_stage_v_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_3; + reg IsNaN_8U_23U_1_land_lpi_1_dfm_4; + reg [31:0] b_sva_36; + reg [31:0] FpAdd_8U_23U_a_sva_36; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + reg FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_4; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_5; + reg [7:0] FpAdd_8U_23U_qr_lpi_1_dfm_6; + reg [48:0] FpAdd_8U_23U_a_int_mant_p1_sva_2; + reg [48:0] FpAdd_8U_23U_b_int_mant_p1_sva_2; + reg FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3; + reg [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2; + reg IsNaN_8U_23U_land_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_6; + reg FpAdd_8U_23U_IsZero_8U_23U_or_itm_2; + reg FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2; + reg FpNormalize_8U_49U_if_or_itm_2; + reg IsNaN_8U_23U_1_nor_itm_2; + reg IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + reg FpAdd_8U_23U_mux_1_itm_2; + reg FpAdd_8U_23U_mux_13_itm_3; + reg FpAdd_8U_23U_mux_13_itm_4; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + reg [7:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + reg [22:0] FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4; + reg IsNaN_8U_23U_land_lpi_1_dfm_st_4; + wire FpAdd_8U_23U_mux_2_tmp_49; + wire main_stage_en_1; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0; + wire FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + wire FpAdd_8U_23U_is_inf_lpi_1_dfm; + wire [49:0] FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + wire [7:0] FpAdd_8U_23U_o_expo_lpi_1_dfm_2; + reg reg_chn_a_rsci_iswt0_cse; + reg reg_chn_a_rsci_ld_core_psct_cse; + wire chn_o_and_1_cse; + wire nor_36_cse; + wire FpAdd_8U_23U_or_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + wire FpSignedBitsToFloat_8U_23U_1_and_rgt; + wire FpSignedBitsToFloat_8U_23U_1_and_1_rgt; + wire [48:0] FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + wire [48:0] FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + wire [48:0] FpNormalize_8U_49U_else_lshift_itm; + wire chn_o_rsci_d_22_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire main_stage_v_2_mx0c1; + wire main_stage_v_3_mx0c1; + wire IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + wire [48:0] FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0; + wire [48:0] FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0; + wire [49:0] FpAdd_8U_23U_asn_5_mx0w0; + wire [50:0] nl_FpAdd_8U_23U_asn_5_mx0w0; + wire [49:0] FpAdd_8U_23U_asn_4_mx0w1; + wire [51:0] nl_FpAdd_8U_23U_asn_4_mx0w1; + wire [48:0] FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0; + wire FpMantRNE_49U_24U_else_carry_sva; + wire FpAdd_8U_23U_and_tmp; + wire [7:0] FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm; + wire [7:0] FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm; + wire FpNormalize_8U_49U_oelse_not_3; + wire [5:0] libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1; + wire FpAdd_8U_23U_is_addition_and_cse; + wire FpAdd_8U_23U_and_8_cse; + wire IsNaN_8U_23U_aelse_and_cse; + wire FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse; + wire FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse; + wire IsNaN_8U_23U_1_and_cse; + reg reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse; + wire mux_13_cse; + wire mux_4_cse; + wire FpSignedBitsToFloat_8U_23U_1_and_3_cse; + wire FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + wire FpAdd_8U_23U_if_3_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_if_4_if_acc_1_itm_7_1; + wire FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1; + wire[22:0] FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl; + wire[22:0] FpMantRNE_49U_24U_else_acc_nl; + wire[23:0] nl_FpMantRNE_49U_24U_else_acc_nl; + wire[0:0] FpSignedBitsToFloat_8U_23U_1_and_2_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_nl; + wire[0:0] FpAdd_8U_23U_and_3_nl; + wire[0:0] FpAdd_8U_23U_and_7_nl; + wire[0:0] mux_6_nl; + wire[0:0] mux_8_nl; + wire[0:0] mux_7_nl; + wire[0:0] nor_37_nl; + wire[0:0] nor_7_nl; + wire[0:0] mux_10_nl; + wire[0:0] or_10_nl; + wire[0:0] mux_9_nl; + wire[0:0] nor_34_nl; + wire[0:0] and_67_nl; + wire[0:0] mux_23_nl; + wire[0:0] mux_22_nl; + wire[0:0] nor_32_nl; + wire[0:0] mux_25_nl; + wire[0:0] mux_24_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_27_nl; + wire[0:0] nor_28_nl; + wire[0:0] nor_29_nl; + wire[0:0] mux_28_nl; + wire[0:0] nor_26_nl; + wire[0:0] nor_27_nl; + wire[8:0] FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[10:0] nl_FpAdd_8U_23U_is_a_greater_acc_1_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_1_nl; + wire[7:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl; + wire[7:0] FpNormalize_8U_49U_else_acc_nl; + wire[9:0] nl_FpNormalize_8U_49U_else_acc_nl; + wire[7:0] FpAdd_8U_23U_if_3_if_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_if_3_if_acc_nl; + wire[0:0] FpAdd_8U_23U_and_1_nl; + wire[0:0] FpAdd_8U_23U_and_2_nl; + wire[48:0] FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl; + wire[0:0] FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl; + wire[7:0] FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[8:0] nl_FpAdd_8U_23U_if_4_if_acc_1_nl; + wire[7:0] FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl; + wire[7:0] FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl; + wire[0:0] FpAdd_8U_23U_is_a_greater_oelse_not_5_nl; + wire[8:0] FpNormalize_8U_49U_acc_nl; + wire[10:0] nl_FpNormalize_8U_49U_acc_nl; + wire[0:0] nor_38_nl; + wire[23:0] FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; + wire[25:0] nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 + , (FpAdd_8U_23U_a_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_a_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_a_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_a_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_a_left_shift_acc_nl = nl_FpAdd_8U_23U_a_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_a_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm[0]))}; + wire [23:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a = {FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 + , (b_sva_36[22:0])}; + wire[7:0] FpAdd_8U_23U_b_left_shift_acc_nl; + wire[8:0] nl_FpAdd_8U_23U_b_left_shift_acc_nl; + wire [8:0] nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s; + assign nl_FpAdd_8U_23U_b_left_shift_acc_nl = ({1'b1 , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[7:1]))}) + + 8'b1101; + assign FpAdd_8U_23U_b_left_shift_acc_nl = nl_FpAdd_8U_23U_b_left_shift_acc_nl[7:0]; + assign nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s = {(FpAdd_8U_23U_b_left_shift_acc_nl) + , (~ (FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm[0]))}; + wire [48:0] nl_FpNormalize_8U_49U_else_lshift_rg_a; + assign nl_FpNormalize_8U_49U_else_lshift_rg_a = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [48:0] nl_leading_sign_49_0_rg_mantissa; + assign nl_leading_sign_49_0_rg_mantissa = FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[48:0]; + wire [31:0] nl_HLS_fp32_sub_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_sub_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_31 , chn_o_rsci_d_30_23 + , chn_o_rsci_d_22_0}; + FP32_SUB_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_a_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_a_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_a_int_mant_p1_lshift_itm) + ); + FP32_SUB_mgc_shift_bl_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd9), + .width_z(32'sd49)) FpAdd_8U_23U_b_int_mant_p1_lshift_rg ( + .a(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_a[23:0]), + .s(nl_FpAdd_8U_23U_b_int_mant_p1_lshift_rg_s[8:0]), + .z(FpAdd_8U_23U_b_int_mant_p1_lshift_itm) + ); + FP32_SUB_mgc_shift_l_v4 #(.width_a(32'sd49), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd49)) FpNormalize_8U_49U_else_lshift_rg ( + .a(nl_FpNormalize_8U_49U_else_lshift_rg_a[48:0]), + .s(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1), + .z(FpNormalize_8U_49U_else_lshift_itm) + ); + FP32_SUB_leading_sign_49_0 leading_sign_49_0_rg ( + .mantissa(nl_leading_sign_49_0_rg_mantissa[48:0]), + .rtn(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + ); + HLS_fp32_sub_core_chn_a_rsci HLS_fp32_sub_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_sub_core_chn_b_rsci HLS_fp32_sub_core_chn_b_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_b_rsci_iswt0(reg_chn_a_rsci_iswt0_cse), + .chn_b_rsci_bawt(chn_b_rsci_bawt), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_b_rsci_ld_core_psct(reg_chn_a_rsci_ld_core_psct_cse), + .chn_b_rsci_d_mxwt(chn_b_rsci_d_mxwt) + ); + HLS_fp32_sub_core_chn_o_rsci HLS_fp32_sub_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_sub_core_chn_o_rsci_inst_chn_o_rsci_d[31:0]) + ); + HLS_fp32_sub_core_staller HLS_fp32_sub_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_b_rsci_wen_comp(chn_b_rsci_wen_comp), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_sub_core_core_fsm HLS_fp32_sub_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign chn_o_and_1_cse = core_wen & (~(and_dcpl_7 | (~ main_stage_v_3))); + assign FpAdd_8U_23U_or_cse = IsNaN_8U_23U_1_land_lpi_1_dfm_4 | IsNaN_8U_23U_land_lpi_1_dfm_6; + assign IsNaN_8U_23U_aelse_and_cse = core_wen & (~ and_dcpl_7) & mux_13_cse; + assign FpAdd_8U_23U_is_addition_and_cse = core_wen & (~ and_dcpl_7) & mux_4_cse; + assign mux_4_cse = MUX_s_1_2_2(main_stage_v_1, main_stage_v_2, nor_36_cse); + assign mux_6_nl = MUX_s_1_2_2(mux_tmp_5, or_tmp_3, main_stage_v_3); + assign FpAdd_8U_23U_and_8_cse = core_wen & (~ and_dcpl_7) & (mux_6_nl); + assign nor_36_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign or_10_nl = nor_36_cse | nor_tmp_11; + assign nor_34_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ nor_tmp_11)); + assign mux_9_nl = MUX_s_1_2_2((nor_34_nl), nor_tmp_11, chn_o_rsci_bawt); + assign and_67_nl = FpAdd_8U_23U_or_cse & main_stage_v_3; + assign mux_10_nl = MUX_s_1_2_2((mux_9_nl), (or_10_nl), and_67_nl); + assign FpSignedBitsToFloat_8U_23U_1_and_3_cse = core_wen & (~ and_dcpl_7) & (mux_10_nl); + assign FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse = ((~ FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1) + & FpAdd_8U_23U_is_a_greater_oif_equal_tmp) | FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1; + assign mux_13_cse = MUX_s_1_2_2(nor_tmp_1, main_stage_v_1, nor_36_cse); + assign FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse = and_dcpl_28 + | and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_1_and_rgt = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0) + & and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_1_and_1_rgt = IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 + & and_dcpl_29; + assign FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse = (FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse + & or_cse) | and_dcpl_33; + assign nor_26_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~ main_stage_v_1)); + assign nor_27_nl = ~(IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_28_nl = MUX_s_1_2_2((nor_27_nl), (nor_26_nl), nor_36_cse); + assign IsNaN_8U_23U_1_and_cse = core_wen & (~ and_dcpl_7) & (mux_28_nl); + assign IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp = ~((~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000))) + | (chn_a_rsci_d_mxwt[30:23]!=8'b11111111)); + assign FpAdd_8U_23U_is_a_greater_oif_equal_tmp = (chn_a_rsci_d_mxwt[30:23]) == + (chn_b_rsci_d_mxwt[30:23]); + assign IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0 = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2); + assign IsNaN_8U_23U_1_nor_tmp = ~((chn_b_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp = ~((chn_b_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpAdd_8U_23U_is_a_greater_acc_1_nl = ({1'b1 , (chn_b_rsci_d_mxwt[30:23])}) + + conv_u2u_8_9(~ (chn_a_rsci_d_mxwt[30:23])) + 9'b1; + assign FpAdd_8U_23U_is_a_greater_acc_1_nl = nl_FpAdd_8U_23U_is_a_greater_acc_1_nl[8:0]; + assign FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1 = readslicef_9_1_8((FpAdd_8U_23U_is_a_greater_acc_1_nl)); + assign FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_b_int_mant_p1_sva_2, + FpAdd_8U_23U_a_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0 = MUX_v_49_2_2(FpAdd_8U_23U_a_int_mant_p1_sva_2, + FpAdd_8U_23U_b_int_mant_p1_sva_2, FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5); + assign nl_FpAdd_8U_23U_asn_5_mx0w0 = conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + + conv_u2u_49_50(FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0); + assign FpAdd_8U_23U_asn_5_mx0w0 = nl_FpAdd_8U_23U_asn_5_mx0w0[49:0]; + assign nl_FpAdd_8U_23U_asn_4_mx0w1 = ({1'b1 , (~ FpAdd_8U_23U_addend_smaller_qr_lpi_1_dfm_mx0)}) + + conv_u2u_49_50(FpAdd_8U_23U_addend_larger_qr_lpi_1_dfm_mx0) + 50'b1; + assign FpAdd_8U_23U_asn_4_mx0w1 = nl_FpAdd_8U_23U_asn_4_mx0w1[49:0]; + assign FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0 = MUX_v_50_2_2(FpAdd_8U_23U_asn_4_mx0w1, + FpAdd_8U_23U_asn_5_mx0w0, reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse); + assign nl_FpAdd_8U_23U_if_3_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_qr_lpi_1_dfm_6[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_1_nl = nl_FpAdd_8U_23U_if_3_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_3_if_acc_1_nl)); + assign nl_FpNormalize_8U_49U_else_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + ({2'b11 + , (~ libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1)}) + + 8'b1; + assign FpNormalize_8U_49U_else_acc_nl = nl_FpNormalize_8U_49U_else_acc_nl[7:0]; + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl = MUX_v_8_2_2(8'b00000000, + (FpNormalize_8U_49U_else_acc_nl), FpNormalize_8U_49U_oelse_not_3); + assign nl_FpAdd_8U_23U_if_3_if_acc_nl = FpAdd_8U_23U_qr_lpi_1_dfm_6 + 8'b1; + assign FpAdd_8U_23U_if_3_if_acc_nl = nl_FpAdd_8U_23U_if_3_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_1_nl = (~ FpAdd_8U_23U_if_3_if_acc_1_itm_7_1) & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_and_2_nl = FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 & (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpAdd_8U_23U_o_expo_lpi_1_dfm_2 = MUX1HOT_v_8_3_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_nl), + FpAdd_8U_23U_qr_lpi_1_dfm_6, (FpAdd_8U_23U_if_3_if_acc_nl), {(~ (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49])) + , (FpAdd_8U_23U_and_1_nl) , (FpAdd_8U_23U_and_2_nl)}); + assign FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl = MUX_v_49_2_2(49'b0000000000000000000000000000000000000000000000000, + FpNormalize_8U_49U_else_lshift_itm, FpNormalize_8U_49U_oelse_not_3); + assign FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0 = MUX_v_49_2_2((FpNormalize_8U_49U_FpNormalize_8U_49U_and_1_nl), + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49:1]), FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]); + assign FpMantRNE_49U_24U_else_carry_sva = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[24]) + & ((FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[0]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[1]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[2]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[3]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[4]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[5]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[6]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[7]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[8]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[9]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[10]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[11]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[12]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[13]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[14]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[15]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[16]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[17]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[18]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[19]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[20]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[21]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[22]) | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[23]) + | (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[25])); + assign FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm + | (~ FpAdd_8U_23U_if_4_if_acc_1_itm_7_1); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 = MUX_s_1_2_2(FpAdd_8U_23U_is_inf_lpi_1_dfm, + (FpAdd_8U_23U_if_4_FpAdd_8U_23U_if_4_or_nl), FpMantRNE_49U_24U_else_and_tmp); + assign nl_FpAdd_8U_23U_if_4_if_acc_1_nl = ({1'b1 , (FpAdd_8U_23U_o_expo_lpi_1_dfm_2[7:1])}) + + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_1_nl = nl_FpAdd_8U_23U_if_4_if_acc_1_nl[7:0]; + assign FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 = readslicef_8_1_7((FpAdd_8U_23U_if_4_if_acc_1_nl)); + assign FpAdd_8U_23U_is_inf_lpi_1_dfm = ~(FpAdd_8U_23U_if_3_if_acc_1_itm_7_1 | (~ + (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]))); + assign FpAdd_8U_23U_and_tmp = FpAdd_8U_23U_if_4_if_acc_1_itm_7_1 & FpMantRNE_49U_24U_else_and_tmp; + assign FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c = ~(IsNaN_8U_23U_1_land_lpi_1_dfm_4 + | IsNaN_8U_23U_land_lpi_1_dfm_6); + assign FpMantRNE_49U_24U_else_and_tmp = FpMantRNE_49U_24U_else_carry_sva & (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[48:25]==24'b111111111111111111111111); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign main_stage_en_1 = chn_b_rsci_bawt & chn_a_rsci_bawt & or_cse; + assign nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl = (FpAdd_8U_23U_a_sva_36[30:23]) + - (b_sva_36[30:23]); + assign FpAdd_8U_23U_b_right_shift_qif_acc_nl = nl_FpAdd_8U_23U_b_right_shift_qif_acc_nl[7:0]; + assign FpAdd_8U_23U_b_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_b_right_shift_qif_acc_nl), + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4); + assign nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl = (b_sva_36[30:23]) - (FpAdd_8U_23U_a_sva_36[30:23]); + assign FpAdd_8U_23U_a_right_shift_qelse_acc_nl = nl_FpAdd_8U_23U_a_right_shift_qelse_acc_nl[7:0]; + assign FpAdd_8U_23U_is_a_greater_oelse_not_5_nl = ~ FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + assign FpAdd_8U_23U_a_right_shift_qr_lpi_1_dfm = MUX_v_8_2_2(8'b00000000, (FpAdd_8U_23U_a_right_shift_qelse_acc_nl), + (FpAdd_8U_23U_is_a_greater_oelse_not_5_nl)); + assign nl_FpNormalize_8U_49U_acc_nl = ({1'b1 , (~ FpAdd_8U_23U_qr_lpi_1_dfm_6)}) + + conv_u2s_6_9(libraries_leading_sign_49_0_e47cea887f8a82708c2da9a42282cded83a3_1) + + 9'b1; + assign FpNormalize_8U_49U_acc_nl = nl_FpNormalize_8U_49U_acc_nl[8:0]; + assign FpNormalize_8U_49U_oelse_not_3 = FpNormalize_8U_49U_if_or_itm_2 & (readslicef_9_1_8((FpNormalize_8U_49U_acc_nl))); + assign FpAdd_8U_23U_mux_2_tmp_49 = MUX_s_1_2_2((FpAdd_8U_23U_asn_4_mx0w1[49]), + (FpAdd_8U_23U_asn_5_mx0w0[49]), reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse); + assign nor_tmp_1 = chn_b_rsci_bawt & chn_a_rsci_bawt; + assign or_tmp_3 = nor_36_cse | main_stage_v_2; + assign nor_38_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ main_stage_v_2)); + assign mux_tmp_5 = MUX_s_1_2_2((nor_38_nl), main_stage_v_2, chn_o_rsci_bawt); + assign nor_tmp_11 = (IsNaN_8U_23U_1_land_lpi_1_dfm_3 | IsNaN_8U_23U_land_lpi_1_dfm_5) + & main_stage_v_2; + assign or_tmp_16 = IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2; + assign and_dcpl_7 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_13 = or_cse & main_stage_v_3; + assign and_dcpl_14 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_15 = and_dcpl_14 & (~ main_stage_v_3); + assign and_dcpl_28 = or_cse & IsNaN_8U_23U_land_lpi_1_dfm_st_4; + assign and_dcpl_29 = or_cse & (~ IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign and_dcpl_33 = or_cse & (~ FpAdd_8U_23U_is_a_greater_acc_1_itm_8_1) & (FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 + | (~ FpAdd_8U_23U_is_a_greater_oif_equal_tmp)); + assign or_tmp_29 = main_stage_en_1 | (fsm_output[0]); + assign or_tmp_35 = chn_a_rsci_bawt & chn_b_rsci_bawt & or_cse & (fsm_output[1]); + assign chn_o_rsci_d_22_0_mx0c1 = or_cse & main_stage_v_3 & (~ IsNaN_8U_23U_land_lpi_1_dfm_6); + assign main_stage_v_1_mx0c1 = (~(chn_a_rsci_bawt & chn_b_rsci_bawt)) & main_stage_v_1 + & or_cse; + assign main_stage_v_2_mx0c1 = main_stage_v_2 & (~ main_stage_v_1) & or_cse; + assign main_stage_v_3_mx0c1 = or_cse & (~ main_stage_v_2) & main_stage_v_3; + assign nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = ({1'b1 , (chn_a_rsci_d_mxwt[22:0])}) + + conv_u2u_23_24(~ (chn_b_rsci_d_mxwt[22:0])) + 24'b1; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl = nl_FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl[23:0]; + assign FpAdd_8U_23U_is_a_greater_oif_aelse_acc_itm_23_1 = readslicef_24_1_23((FpAdd_8U_23U_is_a_greater_oif_aelse_acc_nl)); + assign chn_a_rsci_oswt_unreg_pff = or_tmp_35; + assign chn_o_rsci_oswt_unreg = and_dcpl_14; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_iswt0_cse <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + reg_chn_a_rsci_iswt0_cse <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_13; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_a_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & or_tmp_29 ) begin + reg_chn_a_rsci_ld_core_psct_cse <= or_tmp_29; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_22_0 <= 23'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_3 & IsNaN_8U_23U_land_lpi_1_dfm_6) + | chn_o_rsci_d_22_0_mx0c1) ) begin + chn_o_rsci_d_22_0 <= MUX_v_23_2_2(FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4, + (FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl), FpSignedBitsToFloat_8U_23U_1_and_2_nl); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_30_23 <= 8'b0; + chn_o_rsci_d_31 <= 1'b0; + end + else if ( chn_o_and_1_cse ) begin + chn_o_rsci_d_30_23 <= MUX1HOT_v_8_4_2(FpAdd_8U_23U_o_expo_lpi_1_dfm_2, (FpAdd_8U_23U_if_4_if_acc_nl), + 8'b11111110, FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4, + {(FpAdd_8U_23U_and_nl) , (FpAdd_8U_23U_and_3_nl) , (FpAdd_8U_23U_and_7_nl) + , FpAdd_8U_23U_or_cse}); + chn_o_rsci_d_31 <= FpAdd_8U_23U_mux_13_itm_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_13 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_35 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= 1'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3 + <= 1'b0; + FpAdd_8U_23U_a_sva_36 <= 32'b0; + b_sva_36 <= 32'b0; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= 1'b0; + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_aelse_and_cse ) begin + IsNaN_8U_23U_land_lpi_1_dfm_st_4 <= IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4 <= FpAdd_8U_23U_is_a_greater_FpAdd_8U_23U_is_a_greater_or_cse; + FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3 + <= (chn_a_rsci_d_mxwt[31]) ^ (chn_b_rsci_d_mxwt[31]); + FpAdd_8U_23U_a_sva_36 <= chn_a_rsci_d_mxwt; + b_sva_36 <= chn_b_rsci_d_mxwt; + FpAdd_8U_23U_IsZero_8U_23U_1_or_itm_2 <= (chn_b_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + FpAdd_8U_23U_IsZero_8U_23U_or_itm_2 <= (chn_a_rsci_d_mxwt[30:0]!=31'b0000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_1) | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse + <= 1'b0; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= 49'b0; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= 1'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= 1'b0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= 8'b0; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= 1'b0; + end + else if ( FpAdd_8U_23U_is_addition_and_cse ) begin + reg_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_2_cse + <= FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_FpAdd_8U_23U_is_addition_xor_svs_3; + FpAdd_8U_23U_a_int_mant_p1_sva_2 <= FpAdd_8U_23U_a_int_mant_p1_lshift_itm; + FpAdd_8U_23U_b_int_mant_p1_sva_2 <= FpAdd_8U_23U_b_int_mant_p1_lshift_itm; + FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_5 <= FpAdd_8U_23U_is_a_greater_lor_lpi_1_dfm_4; + IsNaN_8U_23U_1_land_lpi_1_dfm_3 <= IsNaN_8U_23U_1_land_lpi_1_dfm_mx0w0; + FpAdd_8U_23U_qr_lpi_1_dfm_5 <= FpAdd_8U_23U_qr_lpi_1_dfm_4; + IsNaN_8U_23U_land_lpi_1_dfm_5 <= IsNaN_8U_23U_land_lpi_1_dfm_st_4; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_3 <= 1'b0; + end + else if ( core_wen & ((or_cse & main_stage_v_2) | main_stage_v_3_mx0c1) ) begin + main_stage_v_3 <= ~ main_stage_v_3_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= 8'b0; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= 50'b0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= 1'b0; + FpAdd_8U_23U_mux_13_itm_4 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= 1'b0; + end + else if ( FpAdd_8U_23U_and_8_cse ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_6 <= FpAdd_8U_23U_qr_lpi_1_dfm_5; + FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2 <= FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0; + IsNaN_8U_23U_1_land_lpi_1_dfm_4 <= IsNaN_8U_23U_1_land_lpi_1_dfm_3; + FpAdd_8U_23U_mux_13_itm_4 <= FpAdd_8U_23U_mux_13_itm_3; + IsNaN_8U_23U_land_lpi_1_dfm_6 <= IsNaN_8U_23U_land_lpi_1_dfm_5; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpNormalize_8U_49U_if_or_itm_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_7) & (mux_8_nl) ) begin + FpNormalize_8U_49U_if_or_itm_2 <= (FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_mx0[48:0]!=49'b0000000000000000000000000000000000000000000000000); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= 23'b0; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= 8'b0; + end + else if ( FpSignedBitsToFloat_8U_23U_1_and_3_cse ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3; + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_4 + <= FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_23_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_30_23_itm_3 + <= MUX_v_8_2_2((FpAdd_8U_23U_a_sva_36[30:23]), (b_sva_36[30:23]), and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= 23'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpSignedBitsToFloat_8U_23U_1_or_1_cse + & (mux_25_nl) ) begin + FpSignedBitsToFloat_8U_23U_1_slc_FpSignedBitsToFloat_8U_23U_1_ubits_22_0_itm_3 + <= MUX_v_23_2_2((FpAdd_8U_23U_a_sva_36[22:0]), (b_sva_36[22:0]), and_dcpl_29); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_13_itm_3 <= 1'b0; + end + else if ( core_wen & (and_dcpl_28 | FpSignedBitsToFloat_8U_23U_1_and_rgt | FpSignedBitsToFloat_8U_23U_1_and_1_rgt) + & mux_4_cse ) begin + FpAdd_8U_23U_mux_13_itm_3 <= MUX1HOT_s_1_3_2((FpAdd_8U_23U_a_sva_36[31]), FpAdd_8U_23U_mux_1_itm_2, + (~ (b_sva_36[31])), {and_dcpl_28 , FpSignedBitsToFloat_8U_23U_1_and_rgt + , FpSignedBitsToFloat_8U_23U_1_and_1_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= 8'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse & mux_13_cse + ) begin + FpAdd_8U_23U_qr_lpi_1_dfm_4 <= MUX_v_8_2_2((chn_a_rsci_d_mxwt[30:23]), (chn_b_rsci_d_mxwt[30:23]), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpAdd_8U_23U_mux_1_itm_2 <= 1'b0; + end + else if ( core_wen & FpSignedBitsToFloat_8U_23U_1_FpAdd_8U_23U_or_1_cse & (mux_27_nl) + ) begin + FpAdd_8U_23U_mux_1_itm_2 <= MUX_s_1_2_2((chn_a_rsci_d_mxwt[31]), (~ (chn_b_rsci_d_mxwt[31])), + and_dcpl_33); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + IsNaN_8U_23U_1_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= 1'b0; + end + else if ( IsNaN_8U_23U_1_and_cse ) begin + IsNaN_8U_23U_1_nor_itm_2 <= IsNaN_8U_23U_1_nor_tmp; + IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 <= IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp; + end + end + assign nl_FpMantRNE_49U_24U_else_acc_nl = (FpAdd_8U_23U_int_mant_1_lpi_1_dfm_2_mx0[47:25]) + + conv_u2u_1_23(FpMantRNE_49U_24U_else_carry_sva); + assign FpMantRNE_49U_24U_else_acc_nl = nl_FpMantRNE_49U_24U_else_acc_nl[22:0]; + assign FpAdd_8U_23U_FpAdd_8U_23U_or_1_nl = MUX_v_23_2_2((FpMantRNE_49U_24U_else_acc_nl), + 23'b11111111111111111111111, FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0); + assign FpSignedBitsToFloat_8U_23U_1_and_2_nl = (~ IsNaN_8U_23U_1_land_lpi_1_dfm_4) + & chn_o_rsci_d_22_0_mx0c1; + assign nl_FpAdd_8U_23U_if_4_if_acc_nl = FpAdd_8U_23U_o_expo_lpi_1_dfm_2 + 8'b1; + assign FpAdd_8U_23U_if_4_if_acc_nl = nl_FpAdd_8U_23U_if_4_if_acc_nl[7:0]; + assign FpAdd_8U_23U_and_nl = (~(FpAdd_8U_23U_and_tmp | FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0)) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_3_nl = FpAdd_8U_23U_and_tmp & (~ FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0) + & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign FpAdd_8U_23U_and_7_nl = FpAdd_8U_23U_is_inf_lpi_1_dfm_2_mx0 & FpAdd_8U_23U_FpAdd_8U_23U_nor_2_m1c; + assign mux_7_nl = MUX_s_1_2_2(or_tmp_3, nor_36_cse, FpAdd_8U_23U_mux_2_tmp_49); + assign nor_37_nl = ~(FpAdd_8U_23U_mux_2_tmp_49 | (~ mux_tmp_5)); + assign nor_7_nl = ~((FpAdd_8U_23U_int_mant_p1_lpi_1_dfm_2[49]) | (~ main_stage_v_3)); + assign mux_8_nl = MUX_s_1_2_2((nor_37_nl), (mux_7_nl), nor_7_nl); + assign nor_32_nl = ~(or_tmp_16 | (~ main_stage_v_1)); + assign mux_22_nl = MUX_s_1_2_2((nor_32_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_23_nl = MUX_s_1_2_2((mux_22_nl), nor_tmp_11, nor_36_cse); + assign nor_31_nl = ~(IsNaN_8U_23U_1_nor_itm_2 | IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_itm_2 + | (~ main_stage_v_1)); + assign mux_24_nl = MUX_s_1_2_2((nor_31_nl), main_stage_v_1, IsNaN_8U_23U_land_lpi_1_dfm_st_4); + assign mux_25_nl = MUX_s_1_2_2((mux_24_nl), nor_tmp_11, nor_36_cse); + assign nor_28_nl = ~(IsNaN_8U_23U_land_lpi_1_dfm_st_4 | (~(or_tmp_16 & main_stage_v_1))); + assign nor_29_nl = ~((~(IsNaN_8U_23U_1_IsNaN_8U_23U_1_nand_tmp | IsNaN_8U_23U_1_nor_tmp)) + | IsNaN_8U_23U_IsNaN_8U_23U_nor_tmp | (~ nor_tmp_1)); + assign mux_27_nl = MUX_s_1_2_2((nor_29_nl), (nor_28_nl), nor_36_cse); + function [0:0] MUX1HOT_s_1_3_2; + input [0:0] input_2; + input [0:0] input_1; + input [0:0] input_0; + input [2:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + result = result | ( input_1 & {1{sel[1]}}); + result = result | ( input_2 & {1{sel[2]}}); + MUX1HOT_s_1_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_3_2; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [2:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + MUX1HOT_v_8_3_2 = result; + end + endfunction + function [7:0] MUX1HOT_v_8_4_2; + input [7:0] input_3; + input [7:0] input_2; + input [7:0] input_1; + input [7:0] input_0; + input [3:0] sel; + reg [7:0] result; + begin + result = input_0 & {8{sel[0]}}; + result = result | ( input_1 & {8{sel[1]}}); + result = result | ( input_2 & {8{sel[2]}}); + result = result | ( input_3 & {8{sel[3]}}); + MUX1HOT_v_8_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [48:0] MUX_v_49_2_2; + input [48:0] input_0; + input [48:0] input_1; + input [0:0] sel; + reg [48:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_49_2_2 = result; + end + endfunction + function [49:0] MUX_v_50_2_2; + input [49:0] input_0; + input [49:0] input_1; + input [0:0] sel; + reg [49:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_50_2_2 = result; + end + endfunction + function [7:0] MUX_v_8_2_2; + input [7:0] input_0; + input [7:0] input_1; + input [0:0] sel; + reg [7:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_8_2_2 = result; + end + endfunction + function [0:0] readslicef_24_1_23; + input [23:0] vector; + reg [23:0] tmp; + begin + tmp = vector >> 23; + readslicef_24_1_23 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [8:0] conv_u2s_6_9 ; + input [5:0] vector ; + begin + conv_u2s_6_9 = {{3{1'b0}}, vector}; + end + endfunction + function [22:0] conv_u2u_1_23 ; + input [0:0] vector ; + begin + conv_u2u_1_23 = {{22{1'b0}}, vector}; + end + endfunction + function [8:0] conv_u2u_8_9 ; + input [7:0] vector ; + begin + conv_u2u_8_9 = {1'b0, vector}; + end + endfunction + function [23:0] conv_u2u_23_24 ; + input [22:0] vector ; + begin + conv_u2u_23_24 = {1'b0, vector}; + end + endfunction + function [49:0] conv_u2u_49_50 ; + input [48:0] vector ; + begin + conv_u2u_49_50 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_sub +// ------------------------------------------------------------------ +module HLS_fp32_sub ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_b_rsc_z, + chn_b_rsc_vz, chn_b_rsc_lz, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input [31:0] chn_b_rsc_z; + input chn_b_rsc_vz; + output chn_b_rsc_lz; + output [31:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_b_rsci_oswt; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; + wire chn_a_rsci_oswt_unreg_iff; +// Interconnect Declarations for Component Instantiations + FP32_SUB_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_a_rsci_oswt) + ); + FP32_SUB_chn_b_rsci_unreg chn_b_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg_iff), + .outsig(chn_b_rsci_oswt) + ); + FP32_SUB_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_sub_core HLS_fp32_sub_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_b_rsc_z(chn_b_rsc_z), + .chn_b_rsc_vz(chn_b_rsc_vz), + .chn_b_rsc_lz(chn_b_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_b_rsci_oswt(chn_b_rsci_oswt), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg), + .chn_a_rsci_oswt_unreg_pff(chn_a_rsci_oswt_unreg_iff) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp16.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp16.v new file mode 100644 index 0000000..f745cd8 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp16.v @@ -0,0 +1,1445 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_to_fp16.v +module FP32_TO_FP16_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_TO_FP16_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_TO_FP16_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_r_beh_v4.v +module FP32_TO_FP16_mgc_shift_r_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshr_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshr_u(a,s,1'b0); + end + endgenerate +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_TO_FP16_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-159 +// Generated date: Mon Jul 3 21:37:29 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP16_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP16_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP16_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP16_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_to_fp16_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_to_fp16_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [15:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP16_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd16)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP16_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_15; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_14; + reg [3:0] chn_o_rsci_d_13_10; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + wire IsNaN_8U_23U_nor_tmp; + wire or_tmp_2; + wire mux_tmp; + wire mux_tmp_1; + wire and_tmp; + wire or_tmp_7; + wire or_tmp_9; + wire or_tmp_25; + wire or_tmp_26; + wire mux_tmp_16; + wire mux_tmp_19; + wire and_dcpl_6; + wire and_dcpl_8; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire or_dcpl_11; + wire or_tmp_53; + reg FpMantRNE_24U_11U_else_and_svs; + reg main_stage_v_1; + reg main_stage_v_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4; + reg [2:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + wire [3:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + reg FpMantRNE_24U_11U_else_carry_sva_2; + reg FpMantRNE_24U_11U_else_and_svs_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_2; + reg [10:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2; + reg FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2; + reg IsNaN_8U_23U_nor_itm_2; + reg IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4; + reg FpMantRNE_24U_11U_else_and_svs_st_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1; + reg [3:0] FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1; + reg [27:0] FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1; + reg [9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1; + wire main_stage_en_1; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp; + wire FpMantRNE_24U_11U_else_carry_sva_mx0w0; + wire [4:0] FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4; + wire [5:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4; + wire chn_o_and_cse; + wire or_7_cse; + wire nor_15_cse; + wire and_72_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire and_74_cse; + wire nor_2_cse; + wire and_37_cse; + wire and_43_rgt; + wire and_49_rgt; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm; + wire FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp; + wire [22:0] z_out; + wire [23:0] nl_z_out; + wire HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire FpMantRNE_24U_11U_else_and_svs_mx0w0; + wire main_stage_v_2_mx0c1; + wire [10:0] FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire [11:0] nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_least_mask_sva; + wire [4:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse; + wire Fp32ToFp16_and_1_cse; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_if_and_cse; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] shift_0_prb; + wire[0:0] and_11; + wire[3:0] FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_and_nl; + wire[3:0] FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_mux1h_nl; + wire[0:0] FpWidthDec_8U_23U_5U_10U_1U_1U_and_1_nl; + wire[0:0] FpWidthDec_8U_23U_5U_10U_1U_1U_is_zero_not_2_nl; + wire[9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_2_nl; + wire[9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_nl; + wire[9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_mux_1_nl; + wire[0:0] mux_4_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_2_nl; + wire[0:0] nor_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_7_nl; + wire[0:0] and_76_nl; + wire[0:0] mux_6_nl; + wire[0:0] nor_26_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_27_nl; + wire[0:0] or_12_nl; + wire[0:0] mux_9_nl; + wire[0:0] mux_8_nl; + wire[0:0] or_15_nl; + wire[0:0] nor_25_nl; + wire[0:0] nor_4_nl; + wire[0:0] mux_11_nl; + wire[0:0] mux_10_nl; + wire[0:0] nor_24_nl; + wire[0:0] nor_5_nl; + wire[0:0] mux_12_nl; + wire[0:0] mux_14_nl; + wire[0:0] nor_21_nl; + wire[0:0] nor_34_nl; + wire[0:0] mux_18_nl; + wire[0:0] nor_20_nl; + wire[0:0] mux_17_nl; + wire[0:0] mux_21_nl; + wire[0:0] mux_20_nl; + wire[0:0] nor_19_nl; + wire[0:0] and_73_nl; + wire[0:0] mux_22_nl; + wire[0:0] nor_17_nl; + wire[0:0] nor_18_nl; + wire[0:0] mux_23_nl; + wire[0:0] nor_16_nl; + wire[0:0] and_70_nl; + wire[0:0] and_19_nl; + wire[8:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl; + wire[7:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl; + wire[8:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl; + wire[8:0] FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_28_nl; + wire[0:0] mux_15_nl; + wire[0:0] and_75_nl; + wire[22:0] FpMantRNE_24U_11U_else_mux_4_nl; + wire[0:0] FpMantRNE_24U_11U_else_FpMantRNE_24U_11U_else_or_2_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a = {1'b1 , (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0])}; + wire [3:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s = {FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[23]))}; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s = FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva + + 5'b11111; + wire [15:0] nl_HLS_fp32_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_15 + , chn_o_rsci_d_14 , chn_o_rsci_d_13_10 , chn_o_rsci_d_9_0}; + FP32_TO_FP16_mgc_shift_r_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg ( + .a(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a[23:0]), + .s(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s[3:0]), + .z(FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm) + ); + FP32_TO_FP16_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s[4:0]), + .z(FpMantDecShiftRight_23U_8U_10U_guard_mask_sva) + ); + FP32_TO_FP16_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_least_mask_lshift_rg ( + .a(1'b1), + .s(FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva), + .z(FpMantDecShiftRight_23U_8U_10U_least_mask_sva) + ); + HLS_fp32_to_fp16_core_chn_a_rsci HLS_fp32_to_fp16_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_to_fp16_core_chn_o_rsci HLS_fp32_to_fp16_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d[15:0]) + ); + HLS_fp32_to_fp16_core_staller HLS_fp32_to_fp16_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_to_fp16_core_core_fsm HLS_fp32_to_fp16_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iMantWidth >= oMantWidth) - ../include/nvdla_float.h: line 669 +// PSL HLS_fp32_to_fp16_core_nvdla_float_h_ln669_assert_iMantWidth_ge_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb = HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iExpoWidth >= oExpoWidth) - ../include/nvdla_float.h: line 670 +// PSL HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign and_11 = and_37_cse & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3) + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3); + assign shift_0_prb = MUX1HOT_s_1_1_2(readslicef_5_1_4((({1'b1 , (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2) + , (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[23])}) + 5'b1)), and_11); +// assert(shift > 0) - ../include/nvdla_float.h: line 286 +// PSL HLS_fp32_to_fp16_core_nvdla_float_h_ln286_assert_shift_gt_0 : assert { shift_0_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_8 | (~ main_stage_v_2))); + assign or_7_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_and_cse = core_wen & (~ and_dcpl_8) & + mux_tmp; + assign and_37_cse = or_7_cse & main_stage_v_1; + assign nor_21_nl = ~((~ or_tmp_9) | (~ main_stage_v_1) | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3); + assign nor_34_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + | (~ main_stage_v_2) | IsNaN_8U_23U_land_lpi_1_dfm_2 | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4); + assign mux_14_nl = MUX_s_1_2_2((nor_34_nl), (nor_21_nl), or_7_cse); + assign FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse = core_wen & (~ and_dcpl_8) + & (mux_14_nl); + assign Fp32ToFp16_and_1_cse = core_wen & (~ and_dcpl_8) & mux_tmp_19; + assign nor_15_cse = ~(IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 | IsNaN_8U_23U_nor_itm_2); + assign and_72_cse = (FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4==5'b11111) & FpMantRNE_24U_11U_else_and_svs_2; + assign and_74_cse = FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4 + & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4; + assign and_43_rgt = or_7_cse & or_tmp_9; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse + = (or_7_cse & FpMantRNE_24U_11U_else_and_svs_2) | and_dcpl_28; + assign and_49_rgt = or_dcpl_11 & or_7_cse; + assign and_19_nl = main_stage_en_1 & (fsm_output[1]); + assign HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_19_nl)), fsm_output[1]); + assign FpMantRNE_24U_11U_else_and_svs_mx0w0 = FpMantRNE_24U_11U_else_carry_sva_mx0w0 + & (chn_a_rsci_d_mxwt[22:13]==10'b1111111111); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl = ({1'b1 , (~ (chn_a_rsci_d_mxwt[30:23]))}) + + 9'b1110001; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl[8:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl)); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl = conv_u2u_7_8(chn_a_rsci_d_mxwt[30:24]) + + 8'b11001101; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl[7:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 = readslicef_8_1_7((FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl)); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl = conv_u2s_8_9(chn_a_rsci_d_mxwt[30:23]) + + 9'b101110001; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl[8:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl)); + assign FpMantRNE_24U_11U_else_carry_sva_mx0w0 = (chn_a_rsci_d_mxwt[12]) & ((chn_a_rsci_d_mxwt[0]) + | (chn_a_rsci_d_mxwt[1]) | (chn_a_rsci_d_mxwt[2]) | (chn_a_rsci_d_mxwt[3]) + | (chn_a_rsci_d_mxwt[4]) | (chn_a_rsci_d_mxwt[5]) | (chn_a_rsci_d_mxwt[6]) + | (chn_a_rsci_d_mxwt[7]) | (chn_a_rsci_d_mxwt[8]) | (chn_a_rsci_d_mxwt[9]) + | (chn_a_rsci_d_mxwt[10]) | (chn_a_rsci_d_mxwt[11]) | (chn_a_rsci_d_mxwt[13])); + assign IsNaN_8U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp = ~((chn_a_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + + conv_u2u_1_11(FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2); + assign FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc = + ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp = FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4); + assign main_stage_en_1 = chn_a_rsci_bawt & or_7_cse; + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4 = ({(~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[27])) + , (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[26:23])}) + 5'b1; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4 = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4[4:0]; + assign FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva = (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]); + assign FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva = (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0]) + & z_out; + assign FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva = (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[22:0]); + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = conv_u2u_4_5({FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[23]))}) + 5'b1101; + assign FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva[4:0]; + assign or_tmp_2 = chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_1)); + assign nor_2_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign mux_tmp = MUX_s_1_2_2(chn_a_rsci_bawt, main_stage_v_1, nor_2_cse); + assign mux_tmp_1 = MUX_s_1_2_2((~ or_tmp_2), mux_tmp, FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1); + assign nor_28_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ chn_a_rsci_bawt)); + assign mux_3_nl = MUX_s_1_2_2((nor_28_nl), chn_a_rsci_bawt, chn_o_rsci_bawt); + assign and_tmp = FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 & (mux_3_nl); + assign or_tmp_7 = IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp | IsNaN_8U_23U_nor_tmp; + assign or_tmp_9 = IsNaN_8U_23U_nor_itm_2 | IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + assign or_tmp_25 = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + & main_stage_v_2 & (~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse); + assign or_tmp_26 = nor_2_cse | main_stage_v_1; + assign and_75_nl = FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + & main_stage_v_2; + assign mux_15_nl = MUX_s_1_2_2(and_37_cse, or_tmp_26, and_75_nl); + assign mux_tmp_16 = MUX_s_1_2_2((~ or_tmp_25), (mux_15_nl), FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3); + assign mux_tmp_19 = MUX_s_1_2_2(and_37_cse, or_tmp_26, main_stage_v_2); + assign and_dcpl_6 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_8 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_14 = or_7_cse & main_stage_v_2; + assign and_dcpl_15 = and_dcpl_6 & (~ main_stage_v_2); + assign and_dcpl_28 = or_7_cse & (~ FpMantRNE_24U_11U_else_and_svs_2); + assign or_dcpl_11 = (~ FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1) | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1); + assign or_tmp_53 = or_7_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = main_stage_en_1 | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = or_7_cse & main_stage_v_2 & (~ IsNaN_8U_23U_land_lpi_1_dfm_2); + assign main_stage_v_1_mx0c1 = or_7_cse & main_stage_v_1 & (~ chn_a_rsci_bawt); + assign main_stage_v_2_mx0c1 = or_7_cse & (~ main_stage_v_1) & main_stage_v_2; + assign chn_a_rsci_oswt_unreg = or_tmp_53; + assign chn_o_rsci_oswt_unreg = and_dcpl_6; + assign FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp = (fsm_output[1]) & (~ + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_14; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_13_10 <= 4'b0; + chn_o_rsci_d_14 <= 1'b0; + chn_o_rsci_d_15 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_13_10 <= MUX_v_4_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_and_nl), + 4'b1111, IsNaN_8U_23U_land_lpi_1_dfm_2); + chn_o_rsci_d_14 <= (~((~((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc)) + | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5)) | and_74_cse)) | + IsNaN_8U_23U_land_lpi_1_dfm_2; + chn_o_rsci_d_15 <= FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_7_cse & main_stage_v_2 & IsNaN_8U_23U_land_lpi_1_dfm_2) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1, + (FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_2_nl), + chn_o_rsci_d_9_0_mx0c1); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_14 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_53 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= 3'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_4_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2[2:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1 <= 28'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_7_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1 <= chn_a_rsci_d_mxwt[27:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_9_nl) ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_11_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_12_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1 <= 1'b0; + IsNaN_8U_23U_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= 1'b0; + end + else if ( FpWidthDec_8U_23U_5U_10U_1U_1U_if_and_cse ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1 <= chn_a_rsci_d_mxwt[31]; + IsNaN_8U_23U_nor_itm_2 <= IsNaN_8U_23U_nor_tmp; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & (and_37_cse | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= 11'b0; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= 1'b0; + end + else if ( FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm[23:13]; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= ((FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[23])) & ((FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[23])); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_18_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & mux_tmp_16 ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1 <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_2 <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + <= 1'b0; + end + else if ( Fp32ToFp16_and_1_cse ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1 <= FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3; + FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 <= ~((~((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4==5'b11111) + & FpMantRNE_24U_11U_else_and_svs_2 & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3))) + & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3); + IsNaN_8U_23U_land_lpi_1_dfm_2 <= nor_15_cse; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3; + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1 <= 10'b0; + end + else if ( core_wen & ((or_7_cse & nor_15_cse) | and_43_rgt) & (mux_21_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1 <= MUX_v_10_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[9:0]), + (z_out[9:0]), and_43_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1 <= 1'b0; + end + else if ( core_wen & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse + & mux_tmp_19 ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1 <= MUX_s_1_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4[4]), + (~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[27])), and_dcpl_28); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1 <= 4'b0; + end + else if ( core_wen & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse + & (mux_22_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1 <= MUX_v_4_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4[3:0]), + (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[26:23]), and_dcpl_28); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= 1'b0; + end + else if ( core_wen & ((or_7_cse & FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1) & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) + | and_49_rgt) & mux_tmp ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= MUX_s_1_2_2(FpMantRNE_24U_11U_else_and_svs_mx0w0, + FpMantRNE_24U_11U_else_and_svs, and_49_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_23_nl) ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= FpMantRNE_24U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_8 | (~ chn_a_rsci_bawt) | or_dcpl_11 | (fsm_output[0]))) + ) begin + FpMantRNE_24U_11U_else_and_svs <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + assign FpWidthDec_8U_23U_5U_10U_1U_1U_and_1_nl = FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_mux1h_nl = + MUX1HOT_v_4_3_2(({3'b0 , (FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10])}), + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1, 4'b1110, {FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc + , (FpWidthDec_8U_23U_5U_10U_1U_1U_and_1_nl) , FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5}); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_is_zero_not_2_nl = ~ and_74_cse; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_and_nl + = MUX_v_4_2_2(4'b0000, (FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_mux1h_nl), + (FpWidthDec_8U_23U_5U_10U_1U_1U_is_zero_not_2_nl)); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_mux_1_nl = MUX_v_10_2_2((FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[9:0]), + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1, FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_nl = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_mux_1_nl), + 10'b1111111111, FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5)); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_2_nl + = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_nl), 10'b1111111111, + and_74_cse)); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + = (~ (chn_a_rsci_d_mxwt[26:24])) + 3'b1; + assign or_2_nl = FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + assign mux_2_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_2), or_2_nl); + assign nor_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 + | (~ and_tmp)); + assign nor_31_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3)); + assign mux_4_nl = MUX_s_1_2_2((nor_nl), (mux_2_nl), nor_31_nl); + assign and_76_nl = chn_a_rsci_bawt & (~(or_tmp_7 & (FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1)))); + assign nor_27_nl = ~(FpMantRNE_24U_11U_else_and_svs_2 | (~ main_stage_v_1)); + assign or_12_nl = (~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3))) + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3) + | FpMantRNE_24U_11U_else_and_svs_st_2; + assign mux_5_nl = MUX_s_1_2_2((nor_27_nl), main_stage_v_1, or_12_nl); + assign nor_26_nl = ~((~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ (mux_5_nl))); + assign mux_6_nl = MUX_s_1_2_2(main_stage_v_1, (nor_26_nl), or_tmp_9); + assign mux_7_nl = MUX_s_1_2_2((mux_6_nl), (and_76_nl), or_7_cse); + assign or_15_nl = (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + assign mux_8_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_2), or_15_nl); + assign nor_25_nl = ~((~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) | + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_4_nl = ~((~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3)); + assign mux_9_nl = MUX_s_1_2_2((nor_25_nl), (mux_8_nl), nor_4_nl); + assign mux_10_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_2), FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1); + assign nor_24_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_5_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3)); + assign mux_11_nl = MUX_s_1_2_2((nor_24_nl), (mux_10_nl), nor_5_nl); + assign mux_12_nl = MUX_s_1_2_2(and_tmp, mux_tmp_1, FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3); + assign nor_20_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~(FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & and_37_cse))); + assign mux_17_nl = MUX_s_1_2_2(mux_tmp_16, (~ or_tmp_25), FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3); + assign mux_18_nl = MUX_s_1_2_2((mux_17_nl), (nor_20_nl), FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4); + assign nor_19_nl = ~(and_72_cse | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + | (~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + & main_stage_v_1))); + assign mux_20_nl = MUX_s_1_2_2(main_stage_v_1, (nor_19_nl), or_tmp_9); + assign and_73_nl = ((~(and_74_cse | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4))) + | IsNaN_8U_23U_land_lpi_1_dfm_2) & main_stage_v_2; + assign mux_21_nl = MUX_s_1_2_2((and_73_nl), (mux_20_nl), or_7_cse); + assign nor_17_nl = ~(and_72_cse | (~(or_tmp_9 & main_stage_v_1 & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3) + & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3))); + assign nor_18_nl = ~((~ main_stage_v_2) | IsNaN_8U_23U_land_lpi_1_dfm_2 | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4); + assign mux_22_nl = MUX_s_1_2_2((nor_18_nl), (nor_17_nl), or_7_cse); + assign nor_16_nl = ~((~ or_tmp_7) | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 | (~(FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 + & chn_a_rsci_bawt))); + assign and_70_nl = or_tmp_9 & main_stage_v_1 & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3) + & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3) + & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3; + assign mux_23_nl = MUX_s_1_2_2((and_70_nl), (nor_16_nl), or_7_cse); + assign FpMantRNE_24U_11U_else_mux_4_nl = MUX_v_23_2_2((signext_23_10(FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:13])), + (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]), FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp); + assign FpMantRNE_24U_11U_else_FpMantRNE_24U_11U_else_or_2_nl = FpMantRNE_24U_11U_else_carry_sva_2 + | FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp; + assign nl_z_out = (FpMantRNE_24U_11U_else_mux_4_nl) + conv_s2u_2_23({FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp + , (FpMantRNE_24U_11U_else_FpMantRNE_24U_11U_else_or_2_nl)}); + assign z_out = nl_z_out[22:0]; + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [3:0] MUX1HOT_v_4_3_2; + input [3:0] input_2; + input [3:0] input_1; + input [3:0] input_0; + input [2:0] sel; + reg [3:0] result; + begin + result = input_0 & {4{sel[0]}}; + result = result | ( input_1 & {4{sel[1]}}); + result = result | ( input_2 & {4{sel[2]}}); + MUX1HOT_v_4_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [22:0] signext_23_10; + input [9:0] vector; + begin + signext_23_10= {{13{vector[9]}}, vector}; + end + endfunction + function [22:0] conv_s2u_2_23 ; + input [1:0] vector ; + begin + conv_s2u_2_23 = {{21{vector[1]}}, vector}; + end + endfunction + function [8:0] conv_u2s_8_9 ; + input [7:0] vector ; + begin + conv_u2s_8_9 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [4:0] conv_u2u_4_5 ; + input [3:0] vector ; + begin + conv_u2u_4_5 = {1'b0, vector}; + end + endfunction + function [7:0] conv_u2u_7_8 ; + input [6:0] vector ; + begin + conv_u2u_7_8 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16 +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP16_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP32_TO_FP16_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_to_fp16_core HLS_fp32_to_fp16_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp16.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp16.v.vcp new file mode 100644 index 0000000..f745cd8 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp16.v.vcp @@ -0,0 +1,1445 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_to_fp16.v +module FP32_TO_FP16_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_TO_FP16_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_TO_FP16_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_r_beh_v4.v +module FP32_TO_FP16_mgc_shift_r_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshr_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshr_u(a,s,1'b0); + end + endgenerate +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_TO_FP16_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-159 +// Generated date: Mon Jul 3 21:37:29 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP16_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP16_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP16_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP16_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_to_fp16_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_to_fp16_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [15:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP16_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd16)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_to_fp16_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP16_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_to_fp16_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16_core +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_15; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_14; + reg [3:0] chn_o_rsci_d_13_10; + wire [1:0] fsm_output; + wire IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + wire IsNaN_8U_23U_nor_tmp; + wire or_tmp_2; + wire mux_tmp; + wire mux_tmp_1; + wire and_tmp; + wire or_tmp_7; + wire or_tmp_9; + wire or_tmp_25; + wire or_tmp_26; + wire mux_tmp_16; + wire mux_tmp_19; + wire and_dcpl_6; + wire and_dcpl_8; + wire and_dcpl_14; + wire and_dcpl_15; + wire and_dcpl_28; + wire or_dcpl_11; + wire or_tmp_53; + reg FpMantRNE_24U_11U_else_and_svs; + reg main_stage_v_1; + reg main_stage_v_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4; + reg [2:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + wire [3:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + reg FpMantRNE_24U_11U_else_carry_sva_2; + reg FpMantRNE_24U_11U_else_and_svs_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_2; + reg [10:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2; + reg FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2; + reg IsNaN_8U_23U_nor_itm_2; + reg IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4; + reg FpMantRNE_24U_11U_else_and_svs_st_2; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1; + reg [3:0] FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1; + reg [27:0] FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1; + reg FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1; + reg [9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1; + wire main_stage_en_1; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp; + wire FpMantRNE_24U_11U_else_carry_sva_mx0w0; + wire [4:0] FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4; + wire [5:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4; + wire chn_o_and_cse; + wire or_7_cse; + wire nor_15_cse; + wire and_72_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire and_74_cse; + wire nor_2_cse; + wire and_37_cse; + wire and_43_rgt; + wire and_49_rgt; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm; + wire FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp; + wire [22:0] z_out; + wire [23:0] nl_z_out; + wire HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire FpMantRNE_24U_11U_else_and_svs_mx0w0; + wire main_stage_v_2_mx0c1; + wire [10:0] FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire [11:0] nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_least_mask_sva; + wire [4:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse; + wire Fp32ToFp16_and_1_cse; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_if_and_cse; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + wire FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] shift_0_prb; + wire[0:0] and_11; + wire[3:0] FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_and_nl; + wire[3:0] FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_mux1h_nl; + wire[0:0] FpWidthDec_8U_23U_5U_10U_1U_1U_and_1_nl; + wire[0:0] FpWidthDec_8U_23U_5U_10U_1U_1U_is_zero_not_2_nl; + wire[9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_2_nl; + wire[9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_nl; + wire[9:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_mux_1_nl; + wire[0:0] mux_4_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_2_nl; + wire[0:0] nor_nl; + wire[0:0] nor_31_nl; + wire[0:0] mux_7_nl; + wire[0:0] and_76_nl; + wire[0:0] mux_6_nl; + wire[0:0] nor_26_nl; + wire[0:0] mux_5_nl; + wire[0:0] nor_27_nl; + wire[0:0] or_12_nl; + wire[0:0] mux_9_nl; + wire[0:0] mux_8_nl; + wire[0:0] or_15_nl; + wire[0:0] nor_25_nl; + wire[0:0] nor_4_nl; + wire[0:0] mux_11_nl; + wire[0:0] mux_10_nl; + wire[0:0] nor_24_nl; + wire[0:0] nor_5_nl; + wire[0:0] mux_12_nl; + wire[0:0] mux_14_nl; + wire[0:0] nor_21_nl; + wire[0:0] nor_34_nl; + wire[0:0] mux_18_nl; + wire[0:0] nor_20_nl; + wire[0:0] mux_17_nl; + wire[0:0] mux_21_nl; + wire[0:0] mux_20_nl; + wire[0:0] nor_19_nl; + wire[0:0] and_73_nl; + wire[0:0] mux_22_nl; + wire[0:0] nor_17_nl; + wire[0:0] nor_18_nl; + wire[0:0] mux_23_nl; + wire[0:0] nor_16_nl; + wire[0:0] and_70_nl; + wire[0:0] and_19_nl; + wire[8:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl; + wire[7:0] FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl; + wire[8:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl; + wire[8:0] FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl; + wire[0:0] mux_3_nl; + wire[0:0] nor_28_nl; + wire[0:0] mux_15_nl; + wire[0:0] and_75_nl; + wire[22:0] FpMantRNE_24U_11U_else_mux_4_nl; + wire[0:0] FpMantRNE_24U_11U_else_FpMantRNE_24U_11U_else_or_2_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a = {1'b1 , (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0])}; + wire [3:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s = {FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[23]))}; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s = FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva + + 5'b11111; + wire [15:0] nl_HLS_fp32_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_15 + , chn_o_rsci_d_14 , chn_o_rsci_d_13_10 , chn_o_rsci_d_9_0}; + FP32_TO_FP16_mgc_shift_r_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg ( + .a(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a[23:0]), + .s(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s[3:0]), + .z(FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm) + ); + FP32_TO_FP16_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s[4:0]), + .z(FpMantDecShiftRight_23U_8U_10U_guard_mask_sva) + ); + FP32_TO_FP16_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_least_mask_lshift_rg ( + .a(1'b1), + .s(FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva), + .z(FpMantDecShiftRight_23U_8U_10U_least_mask_sva) + ); + HLS_fp32_to_fp16_core_chn_a_rsci HLS_fp32_to_fp16_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_to_fp16_core_chn_o_rsci HLS_fp32_to_fp16_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_to_fp16_core_chn_o_rsci_inst_chn_o_rsci_d[15:0]) + ); + HLS_fp32_to_fp16_core_staller HLS_fp32_to_fp16_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_to_fp16_core_core_fsm HLS_fp32_to_fp16_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iMantWidth >= oMantWidth) - ../include/nvdla_float.h: line 669 +// PSL HLS_fp32_to_fp16_core_nvdla_float_h_ln669_assert_iMantWidth_ge_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb = HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iExpoWidth >= oExpoWidth) - ../include/nvdla_float.h: line 670 +// PSL HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign and_11 = and_37_cse & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3) + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3); + assign shift_0_prb = MUX1HOT_s_1_1_2(readslicef_5_1_4((({1'b1 , (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2) + , (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[23])}) + 5'b1)), and_11); +// assert(shift > 0) - ../include/nvdla_float.h: line 286 +// PSL HLS_fp32_to_fp16_core_nvdla_float_h_ln286_assert_shift_gt_0 : assert { shift_0_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_8 | (~ main_stage_v_2))); + assign or_7_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_and_cse = core_wen & (~ and_dcpl_8) & + mux_tmp; + assign and_37_cse = or_7_cse & main_stage_v_1; + assign nor_21_nl = ~((~ or_tmp_9) | (~ main_stage_v_1) | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3); + assign nor_34_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + | (~ main_stage_v_2) | IsNaN_8U_23U_land_lpi_1_dfm_2 | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4); + assign mux_14_nl = MUX_s_1_2_2((nor_34_nl), (nor_21_nl), or_7_cse); + assign FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse = core_wen & (~ and_dcpl_8) + & (mux_14_nl); + assign Fp32ToFp16_and_1_cse = core_wen & (~ and_dcpl_8) & mux_tmp_19; + assign nor_15_cse = ~(IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 | IsNaN_8U_23U_nor_itm_2); + assign and_72_cse = (FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4==5'b11111) & FpMantRNE_24U_11U_else_and_svs_2; + assign and_74_cse = FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4 + & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4; + assign and_43_rgt = or_7_cse & or_tmp_9; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse + = (or_7_cse & FpMantRNE_24U_11U_else_and_svs_2) | and_dcpl_28; + assign and_49_rgt = or_dcpl_11 & or_7_cse; + assign and_19_nl = main_stage_en_1 & (fsm_output[1]); + assign HLS_fp32_to_fp16_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_19_nl)), fsm_output[1]); + assign FpMantRNE_24U_11U_else_and_svs_mx0w0 = FpMantRNE_24U_11U_else_carry_sva_mx0w0 + & (chn_a_rsci_d_mxwt[22:13]==10'b1111111111); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl = ({1'b1 , (~ (chn_a_rsci_d_mxwt[30:23]))}) + + 9'b1110001; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl[8:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_nl)); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl = conv_u2u_7_8(chn_a_rsci_d_mxwt[30:24]) + + 8'b11001101; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl[7:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 = readslicef_8_1_7((FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_nl)); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl = conv_u2s_8_9(chn_a_rsci_d_mxwt[30:23]) + + 9'b101110001; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl[8:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_5U_10U_1U_1U_acc_nl)); + assign FpMantRNE_24U_11U_else_carry_sva_mx0w0 = (chn_a_rsci_d_mxwt[12]) & ((chn_a_rsci_d_mxwt[0]) + | (chn_a_rsci_d_mxwt[1]) | (chn_a_rsci_d_mxwt[2]) | (chn_a_rsci_d_mxwt[3]) + | (chn_a_rsci_d_mxwt[4]) | (chn_a_rsci_d_mxwt[5]) | (chn_a_rsci_d_mxwt[6]) + | (chn_a_rsci_d_mxwt[7]) | (chn_a_rsci_d_mxwt[8]) | (chn_a_rsci_d_mxwt[9]) + | (chn_a_rsci_d_mxwt[10]) | (chn_a_rsci_d_mxwt[11]) | (chn_a_rsci_d_mxwt[13])); + assign IsNaN_8U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp = ~((chn_a_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + + conv_u2u_1_11(FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2); + assign FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10:0]; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc = + ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp = FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4); + assign main_stage_en_1 = chn_a_rsci_bawt & or_7_cse; + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4 = ({(~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[27])) + , (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[26:23])}) + 5'b1; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4 = nl_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4[4:0]; + assign FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva = (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]); + assign FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva = (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0]) + & z_out; + assign FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva = (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[22:0]); + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = conv_u2u_4_5({FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[23]))}) + 5'b1101; + assign FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva[4:0]; + assign or_tmp_2 = chn_o_rsci_bawt | (~(reg_chn_o_rsci_ld_core_psct_cse & main_stage_v_1)); + assign nor_2_cse = ~(chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse)); + assign mux_tmp = MUX_s_1_2_2(chn_a_rsci_bawt, main_stage_v_1, nor_2_cse); + assign mux_tmp_1 = MUX_s_1_2_2((~ or_tmp_2), mux_tmp, FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1); + assign nor_28_nl = ~(reg_chn_o_rsci_ld_core_psct_cse | (~ chn_a_rsci_bawt)); + assign mux_3_nl = MUX_s_1_2_2((nor_28_nl), chn_a_rsci_bawt, chn_o_rsci_bawt); + assign and_tmp = FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 & (mux_3_nl); + assign or_tmp_7 = IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp | IsNaN_8U_23U_nor_tmp; + assign or_tmp_9 = IsNaN_8U_23U_nor_itm_2 | IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + assign or_tmp_25 = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + & main_stage_v_2 & (~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse); + assign or_tmp_26 = nor_2_cse | main_stage_v_1; + assign and_75_nl = FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + & main_stage_v_2; + assign mux_15_nl = MUX_s_1_2_2(and_37_cse, or_tmp_26, and_75_nl); + assign mux_tmp_16 = MUX_s_1_2_2((~ or_tmp_25), (mux_15_nl), FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3); + assign mux_tmp_19 = MUX_s_1_2_2(and_37_cse, or_tmp_26, main_stage_v_2); + assign and_dcpl_6 = reg_chn_o_rsci_ld_core_psct_cse & chn_o_rsci_bawt; + assign and_dcpl_8 = reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign and_dcpl_14 = or_7_cse & main_stage_v_2; + assign and_dcpl_15 = and_dcpl_6 & (~ main_stage_v_2); + assign and_dcpl_28 = or_7_cse & (~ FpMantRNE_24U_11U_else_and_svs_2); + assign or_dcpl_11 = (~ FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1) | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1); + assign or_tmp_53 = or_7_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = main_stage_en_1 | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = or_7_cse & main_stage_v_2 & (~ IsNaN_8U_23U_land_lpi_1_dfm_2); + assign main_stage_v_1_mx0c1 = or_7_cse & main_stage_v_1 & (~ chn_a_rsci_bawt); + assign main_stage_v_2_mx0c1 = or_7_cse & (~ main_stage_v_1) & main_stage_v_2; + assign chn_a_rsci_oswt_unreg = or_tmp_53; + assign chn_o_rsci_oswt_unreg = and_dcpl_6; + assign FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp = (fsm_output[1]) & (~ + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_14; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_13_10 <= 4'b0; + chn_o_rsci_d_14 <= 1'b0; + chn_o_rsci_d_15 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_13_10 <= MUX_v_4_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_and_nl), + 4'b1111, IsNaN_8U_23U_land_lpi_1_dfm_2); + chn_o_rsci_d_14 <= (~((~((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc)) + | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5)) | and_74_cse)) | + IsNaN_8U_23U_land_lpi_1_dfm_2; + chn_o_rsci_d_15 <= FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_7_cse & main_stage_v_2 & IsNaN_8U_23U_land_lpi_1_dfm_2) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1, + (FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_2_nl), + chn_o_rsci_d_9_0_mx0c1); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_14 | and_dcpl_15) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_53 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= 3'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_4_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2[2:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1 <= 28'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_7_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1 <= chn_a_rsci_d_mxwt[27:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_9_nl) ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_11_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_12_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1 <= 1'b0; + IsNaN_8U_23U_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= 1'b0; + end + else if ( FpWidthDec_8U_23U_5U_10U_1U_1U_if_and_cse ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1 <= chn_a_rsci_d_mxwt[31]; + IsNaN_8U_23U_nor_itm_2 <= IsNaN_8U_23U_nor_tmp; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & (and_37_cse | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= 11'b0; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= 1'b0; + end + else if ( FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm[23:13]; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= ((FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[23])) & ((FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[23])); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_18_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & mux_tmp_16 ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1 <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_2 <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4 + <= 1'b0; + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + <= 1'b0; + end + else if ( Fp32ToFp16_and_1_cse ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_31_1 <= FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_31_1; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3; + FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 <= ~((~((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4==5'b11111) + & FpMantRNE_24U_11U_else_and_svs_2 & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3))) + & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3); + IsNaN_8U_23U_land_lpi_1_dfm_2 <= nor_15_cse; + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3; + FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_4 + <= FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1 <= 10'b0; + end + else if ( core_wen & ((or_7_cse & nor_15_cse) | and_43_rgt) & (mux_21_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1 <= MUX_v_10_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[9:0]), + (z_out[9:0]), and_43_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1 <= 1'b0; + end + else if ( core_wen & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse + & mux_tmp_19 ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_4_1 <= MUX_s_1_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4[4]), + (~ (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[27])), and_dcpl_28); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1 <= 4'b0; + end + else if ( core_wen & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_else_if_if_FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_or_cse + & (mux_22_nl) ) begin + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1 <= MUX_v_4_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_sva_4[3:0]), + (FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[26:23]), and_dcpl_28); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= 1'b0; + end + else if ( core_wen & ((or_7_cse & FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1) & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) + | and_49_rgt) & mux_tmp ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= MUX_s_1_2_2(FpMantRNE_24U_11U_else_and_svs_mx0w0, + FpMantRNE_24U_11U_else_and_svs, and_49_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_8) & (mux_23_nl) ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= FpMantRNE_24U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_8 | (~ chn_a_rsci_bawt) | or_dcpl_11 | (fsm_output[0]))) + ) begin + FpMantRNE_24U_11U_else_and_svs <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + assign FpWidthDec_8U_23U_5U_10U_1U_1U_and_1_nl = FpWidthDec_8U_23U_5U_10U_1U_1U_else_and_tmp + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_mux1h_nl = + MUX1HOT_v_4_3_2(({3'b0 , (FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10])}), + FpWidthDec_8U_23U_5U_10U_1U_1U_o_expo_lpi_1_dfm_8_3_0_1, 4'b1110, {FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_nor_ssc + , (FpWidthDec_8U_23U_5U_10U_1U_1U_and_1_nl) , FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5}); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_is_zero_not_2_nl = ~ and_74_cse; + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_and_nl + = MUX_v_4_2_2(4'b0000, (FpWidthDec_8U_23U_5U_10U_1U_1U_FpWidthDec_8U_23U_5U_10U_1U_1U_mux1h_nl), + (FpWidthDec_8U_23U_5U_10U_1U_1U_is_zero_not_2_nl)); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_mux_1_nl = MUX_v_10_2_2((FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[9:0]), + FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_2_9_0_1, FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_nl = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_mux_1_nl), + 10'b1111111111, FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5)); + assign FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_2_nl + = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_5U_10U_1U_1U_if_2_nor_nl), 10'b1111111111, + and_74_cse)); + assign nl_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + = (~ (chn_a_rsci_d_mxwt[26:24])) + 3'b1; + assign or_2_nl = FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + assign mux_2_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_2), or_2_nl); + assign nor_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 + | (~ and_tmp)); + assign nor_31_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3)); + assign mux_4_nl = MUX_s_1_2_2((nor_nl), (mux_2_nl), nor_31_nl); + assign and_76_nl = chn_a_rsci_bawt & (~(or_tmp_7 & (FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1)))); + assign nor_27_nl = ~(FpMantRNE_24U_11U_else_and_svs_2 | (~ main_stage_v_1)); + assign or_12_nl = (~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3))) + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3) + | FpMantRNE_24U_11U_else_and_svs_st_2; + assign mux_5_nl = MUX_s_1_2_2((nor_27_nl), main_stage_v_1, or_12_nl); + assign nor_26_nl = ~((~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ (mux_5_nl))); + assign mux_6_nl = MUX_s_1_2_2(main_stage_v_1, (nor_26_nl), or_tmp_9); + assign mux_7_nl = MUX_s_1_2_2((mux_6_nl), (and_76_nl), or_7_cse); + assign or_15_nl = (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1; + assign mux_8_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_2), or_15_nl); + assign nor_25_nl = ~((~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) | + FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_4_nl = ~((~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3)); + assign mux_9_nl = MUX_s_1_2_2((nor_25_nl), (mux_8_nl), nor_4_nl); + assign mux_10_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_2), FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1); + assign nor_24_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_5_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3)); + assign mux_11_nl = MUX_s_1_2_2((nor_24_nl), (mux_10_nl), nor_5_nl); + assign mux_12_nl = MUX_s_1_2_2(and_tmp, mux_tmp_1, FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3); + assign nor_20_nl = ~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3 + | (~(FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & and_37_cse))); + assign mux_17_nl = MUX_s_1_2_2(mux_tmp_16, (~ or_tmp_25), FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3); + assign mux_18_nl = MUX_s_1_2_2((mux_17_nl), (nor_20_nl), FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_4); + assign nor_19_nl = ~(and_72_cse | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3 + | (~(FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3 + & main_stage_v_1))); + assign mux_20_nl = MUX_s_1_2_2(main_stage_v_1, (nor_19_nl), or_tmp_9); + assign and_73_nl = ((~(and_74_cse | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4))) + | IsNaN_8U_23U_land_lpi_1_dfm_2) & main_stage_v_2; + assign mux_21_nl = MUX_s_1_2_2((and_73_nl), (mux_20_nl), or_7_cse); + assign nor_17_nl = ~(and_72_cse | (~(or_tmp_9 & main_stage_v_1 & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3) + & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3))); + assign nor_18_nl = ~((~ main_stage_v_2) | IsNaN_8U_23U_land_lpi_1_dfm_2 | FpWidthDec_8U_23U_5U_10U_1U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_4) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_4); + assign mux_22_nl = MUX_s_1_2_2((nor_18_nl), (nor_17_nl), or_7_cse); + assign nor_16_nl = ~((~ or_tmp_7) | (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_itm_8_1) + | FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_itm_7_1 | (~(FpWidthDec_8U_23U_5U_10U_1U_1U_acc_itm_8_1 + & chn_a_rsci_bawt))); + assign and_70_nl = or_tmp_9 & main_stage_v_1 & FpWidthDec_8U_23U_5U_10U_1U_1U_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_st_3) + & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_if_acc_7_mdf_sva_3) + & FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_if_slc_FpWidthDec_8U_23U_5U_10U_1U_1U_else_else_acc_8_svs_3; + assign mux_23_nl = MUX_s_1_2_2((and_70_nl), (nor_16_nl), or_7_cse); + assign FpMantRNE_24U_11U_else_mux_4_nl = MUX_v_23_2_2((signext_23_10(FpWidthDec_8U_23U_5U_10U_1U_1U_bits_sva_1_27_0_1[22:13])), + (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]), FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp); + assign FpMantRNE_24U_11U_else_FpMantRNE_24U_11U_else_or_2_nl = FpMantRNE_24U_11U_else_carry_sva_2 + | FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp; + assign nl_z_out = (FpMantRNE_24U_11U_else_mux_4_nl) + conv_s2u_2_23({FpMantDecShiftRight_23U_8U_10U_stick_mask_and_tmp + , (FpMantRNE_24U_11U_else_FpMantRNE_24U_11U_else_or_2_nl)}); + assign z_out = nl_z_out[22:0]; + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [3:0] MUX1HOT_v_4_3_2; + input [3:0] input_2; + input [3:0] input_1; + input [3:0] input_0; + input [2:0] sel; + reg [3:0] result; + begin + result = input_0 & {4{sel[0]}}; + result = result | ( input_1 & {4{sel[1]}}); + result = result | ( input_2 & {4{sel[2]}}); + MUX1HOT_v_4_3_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [22:0] MUX_v_23_2_2; + input [22:0] input_0; + input [22:0] input_1; + input [0:0] sel; + reg [22:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_23_2_2 = result; + end + endfunction + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [22:0] signext_23_10; + input [9:0] vector; + begin + signext_23_10= {{13{vector[9]}}, vector}; + end + endfunction + function [22:0] conv_s2u_2_23 ; + input [1:0] vector ; + begin + conv_s2u_2_23 = {{21{vector[1]}}, vector}; + end + endfunction + function [8:0] conv_u2s_8_9 ; + input [7:0] vector ; + begin + conv_u2s_8_9 = {1'b0, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [4:0] conv_u2u_4_5 ; + input [3:0] vector ; + begin + conv_u2u_4_5 = {1'b0, vector}; + end + endfunction + function [7:0] conv_u2u_7_8 ; + input [6:0] vector ; + begin + conv_u2u_7_8 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp16 +// ------------------------------------------------------------------ +module HLS_fp32_to_fp16 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [15:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP16_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP32_TO_FP16_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_to_fp16_core HLS_fp32_to_fp16_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp17.v b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp17.v new file mode 100644 index 0000000..720316a --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp17.v @@ -0,0 +1,1457 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_to_fp17.v +module FP32_TO_FP17_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_TO_FP17_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_TO_FP17_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_r_beh_v4.v +module FP32_TO_FP17_mgc_shift_r_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshr_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshr_u(a,s,1'b0); + end + endgenerate +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_TO_FP17_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-159 +// Generated date: Mon Jul 3 21:36:12 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP17_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP17_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP17_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP17_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_to_fp17_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_to_fp17_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP17_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP17_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_15; + reg [4:0] chn_o_rsci_d_14_10; + wire [1:0] fsm_output; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp; + wire IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + wire IsNaN_8U_23U_nor_tmp; + wire or_tmp_3; + wire mux_tmp; + wire mux_tmp_1; + wire and_tmp; + wire or_tmp_9; + wire or_tmp_11; + wire or_tmp_24; + wire mux_tmp_13; + wire or_tmp_28; + wire not_tmp_20; + wire mux_tmp_18; + wire and_dcpl_9; + wire and_dcpl_15; + wire and_dcpl_16; + wire and_dcpl_17; + wire and_dcpl_29; + wire or_dcpl_11; + wire or_tmp_50; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs; + reg FpMantRNE_24U_11U_else_and_svs; + reg main_stage_v_1; + reg main_stage_v_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4; + reg [2:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + wire [3:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + reg FpMantRNE_24U_11U_else_carry_sva_2; + reg FpMantRNE_24U_11U_else_and_svs_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_2; + reg [10:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2; + reg FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2; + reg IsNaN_8U_23U_nor_itm_2; + reg IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4; + reg FpMantRNE_24U_11U_else_and_svs_st_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1; + reg [28:0] FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1; + reg [9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1; + reg [4:0] FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1; + wire main_stage_en_1; + wire FpMantRNE_24U_11U_else_carry_sva_mx0w0; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp; + wire [10:0] FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire [11:0] nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire chn_o_and_cse; + wire or_9_cse; + wire nor_16_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire nor_20_cse; + wire and_77_cse; + wire and_42_cse; + wire and_48_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt; + wire and_50_rgt; + wire and_53_rgt; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm; + wire HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire FpMantRNE_24U_11U_else_and_svs_mx0w0; + wire main_stage_v_2_mx0c1; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2; + wire [5:0] FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3; + wire [6:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_least_mask_sva; + wire [4:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c; + wire FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse; + wire Fp32ToFp17_and_1_cse; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_if_and_cse; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] shift_0_prb; + wire[0:0] and_11; + wire[4:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_and_nl; + wire[0:0] FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_not_3_nl; + wire[9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_1_nl; + wire[9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_nl; + wire[9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_mux_1_nl; + wire[0:0] mux_3_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_2_nl; + wire[0:0] nor_nl; + wire[0:0] nor_33_nl; + wire[0:0] mux_5_nl; + wire[0:0] and_nl; + wire[0:0] mux_4_nl; + wire[0:0] nor_32_nl; + wire[0:0] and_82_nl; + wire[0:0] mux_7_nl; + wire[0:0] mux_6_nl; + wire[0:0] or_16_nl; + wire[0:0] nor_28_nl; + wire[0:0] nor_5_nl; + wire[0:0] mux_9_nl; + wire[0:0] mux_8_nl; + wire[0:0] nor_27_nl; + wire[0:0] nor_6_nl; + wire[0:0] mux_10_nl; + wire[0:0] mux_11_nl; + wire[0:0] nor_25_nl; + wire[0:0] nor_26_nl; + wire[0:0] mux_15_nl; + wire[0:0] nor_23_nl; + wire[0:0] mux_14_nl; + wire[0:0] and_14_nl; + wire[0:0] mux_16_nl; + wire[9:0] FpMantRNE_24U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_24U_11U_else_acc_nl; + wire[0:0] mux_19_nl; + wire[0:0] nand_5_nl; + wire[0:0] nor_19_nl; + wire[0:0] and_76_nl; + wire[0:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_else_mux_2_nl; + wire[0:0] mux_20_nl; + wire[0:0] nor_17_nl; + wire[0:0] and_86_nl; + wire[0:0] and_22_nl; + wire[8:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl; + wire[7:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl; + wire[8:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl; + wire[8:0] FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl; + wire[22:0] FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl; + wire[23:0] nl_FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl; + wire[0:0] mux_12_nl; + wire[0:0] and_80_nl; + wire[0:0] and_81_nl; + wire[0:0] nand_6_nl; + wire[0:0] nor_21_nl; + wire[0:0] nor_9_nl; + wire[0:0] or_34_nl; + wire[0:0] nand_9_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a = {1'b1 , (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0])}; + wire [3:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s = {FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[23]))}; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s = FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva + + 5'b11111; + wire [16:0] nl_HLS_fp32_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 + , chn_o_rsci_d_15 , chn_o_rsci_d_14_10 , chn_o_rsci_d_9_0}; + FP32_TO_FP17_mgc_shift_r_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg ( + .a(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a[23:0]), + .s(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s[3:0]), + .z(FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm) + ); + FP32_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s[4:0]), + .z(FpMantDecShiftRight_23U_8U_10U_guard_mask_sva) + ); + FP32_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_least_mask_lshift_rg ( + .a(1'b1), + .s(FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva), + .z(FpMantDecShiftRight_23U_8U_10U_least_mask_sva) + ); + HLS_fp32_to_fp17_core_chn_a_rsci HLS_fp32_to_fp17_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_to_fp17_core_chn_o_rsci HLS_fp32_to_fp17_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp32_to_fp17_core_staller HLS_fp32_to_fp17_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_to_fp17_core_core_fsm HLS_fp32_to_fp17_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iMantWidth >= oMantWidth) - ../include/nvdla_float.h: line 669 +// PSL HLS_fp32_to_fp17_core_nvdla_float_h_ln669_assert_iMantWidth_ge_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb = HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iExpoWidth >= oExpoWidth) - ../include/nvdla_float.h: line 670 +// PSL HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign and_11 = and_42_cse & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3) + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3); + assign shift_0_prb = MUX1HOT_s_1_1_2(readslicef_5_1_4((({1'b1 , (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2) + , (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[23])}) + 5'b1)), and_11); +// assert(shift > 0) - ../include/nvdla_float.h: line 286 +// PSL HLS_fp32_to_fp17_core_nvdla_float_h_ln286_assert_shift_gt_0 : assert { shift_0_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_9 | (~ main_stage_v_2))); + assign or_9_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_if_and_cse = core_wen & (~ and_dcpl_9) & + mux_tmp; + assign and_42_cse = or_9_cse & main_stage_v_1; + assign nor_25_nl = ~((~ main_stage_v_1) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3); + assign nor_26_nl = ~((~ main_stage_v_2) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4); + assign mux_11_nl = MUX_s_1_2_2((nor_26_nl), (nor_25_nl), or_9_cse); + assign FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse = core_wen & (~ and_dcpl_9) + & (mux_11_nl); + assign mux_16_nl = MUX_s_1_2_2(and_42_cse, or_tmp_24, main_stage_v_2); + assign Fp32ToFp17_and_1_cse = core_wen & (~ and_dcpl_9) & (mux_16_nl); + assign nor_16_cse = ~(IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 | IsNaN_8U_23U_nor_itm_2); + assign nor_20_cse = ~((~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt); + assign and_77_cse = FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4 + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4; + assign and_48_rgt = or_tmp_11 & or_9_cse; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt = FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc + & (~ and_dcpl_9); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt = (~ FpMantRNE_24U_11U_else_and_svs_2) + & FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c & (~ and_dcpl_9); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt = FpMantRNE_24U_11U_else_and_svs_2 + & FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c & (~ and_dcpl_9); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt = FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0 + & (~ and_dcpl_9); + assign and_50_rgt = or_9_cse & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1); + assign and_53_rgt = or_dcpl_11 & or_9_cse; + assign and_22_nl = main_stage_en_1 & (fsm_output[1]); + assign HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_22_nl)), fsm_output[1]); + assign FpMantRNE_24U_11U_else_and_svs_mx0w0 = FpMantRNE_24U_11U_else_carry_sva_mx0w0 + & (chn_a_rsci_d_mxwt[22:13]==10'b1111111111); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl = ({1'b1 , (~ (chn_a_rsci_d_mxwt[30:23]))}) + + 9'b1100001; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl[8:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl)); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl = conv_u2u_7_8(chn_a_rsci_d_mxwt[30:24]) + + 8'b11010101; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl[7:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 = readslicef_8_1_7((FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl)); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl = conv_u2s_8_9(chn_a_rsci_d_mxwt[30:23]) + + 9'b101100001; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl[8:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp = ~((FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3==6'b111111) + & FpMantRNE_24U_11U_else_and_svs_2 & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0 = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3); + assign FpMantRNE_24U_11U_else_carry_sva_mx0w0 = (chn_a_rsci_d_mxwt[12]) & ((chn_a_rsci_d_mxwt[0]) + | (chn_a_rsci_d_mxwt[1]) | (chn_a_rsci_d_mxwt[2]) | (chn_a_rsci_d_mxwt[3]) + | (chn_a_rsci_d_mxwt[4]) | (chn_a_rsci_d_mxwt[5]) | (chn_a_rsci_d_mxwt[6]) + | (chn_a_rsci_d_mxwt[7]) | (chn_a_rsci_d_mxwt[8]) | (chn_a_rsci_d_mxwt[9]) + | (chn_a_rsci_d_mxwt[10]) | (chn_a_rsci_d_mxwt[11]) | (chn_a_rsci_d_mxwt[13])); + assign IsNaN_8U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp = ~((chn_a_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + + conv_u2u_1_11(FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2); + assign FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2 = ((~((FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10]) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4)) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4) + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4; + assign main_stage_en_1 = chn_a_rsci_bawt & or_9_cse; + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3 = ({(~ (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[28])) + , (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[27:23])}) + 6'b1; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3 = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3[5:0]; + assign FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]); + assign nl_FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl = (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]) + + 23'b11111111111111111111111; + assign FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl = nl_FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl[22:0]; + assign FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl); + assign FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[22:0]); + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = conv_u2u_4_5({FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[23]))}) + 5'b1101; + assign FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva[4:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc = + ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp | FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c = FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp = FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3); + assign or_tmp_3 = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt | (~ main_stage_v_1); + assign mux_tmp = MUX_s_1_2_2(main_stage_v_1, chn_a_rsci_bawt, or_9_cse); + assign mux_tmp_1 = MUX_s_1_2_2((~ or_tmp_3), mux_tmp, FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1); + assign and_tmp = FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1 & or_9_cse & chn_a_rsci_bawt; + assign or_tmp_9 = IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp | IsNaN_8U_23U_nor_tmp; + assign or_tmp_11 = IsNaN_8U_23U_nor_itm_2 | IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + assign or_tmp_24 = nor_20_cse | main_stage_v_1; + assign and_80_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + & main_stage_v_2; + assign mux_12_nl = MUX_s_1_2_2(and_42_cse, or_tmp_24, and_80_nl); + assign and_81_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + & main_stage_v_2 & reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign mux_tmp_13 = MUX_s_1_2_2((and_81_nl), (mux_12_nl), FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3); + assign or_tmp_28 = (FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3) + | (~(main_stage_v_1 & or_tmp_11)); + assign nand_6_nl = ~(or_9_cse & or_tmp_28); + assign nor_21_nl = ~(nor_20_cse | or_tmp_28); + assign nor_9_nl = ~(and_77_cse | IsNaN_8U_23U_land_lpi_1_dfm_2 | (~ main_stage_v_2)); + assign not_tmp_20 = MUX_s_1_2_2((nor_21_nl), (nand_6_nl), nor_9_nl); + assign or_34_nl = (~ main_stage_v_1) | IsNaN_8U_23U_nor_itm_2 | IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + assign nand_9_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3)); + assign mux_tmp_18 = MUX_s_1_2_2((~ main_stage_v_1), (or_34_nl), nand_9_nl); + assign and_dcpl_9 = (~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_15 = or_9_cse & main_stage_v_2; + assign and_dcpl_16 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_17 = and_dcpl_16 & (~ main_stage_v_2); + assign and_dcpl_29 = or_9_cse & FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1; + assign or_dcpl_11 = (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1) | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1); + assign or_tmp_50 = or_9_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = main_stage_en_1 | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = or_9_cse & main_stage_v_2 & (~ IsNaN_8U_23U_land_lpi_1_dfm_2); + assign main_stage_v_1_mx0c1 = main_stage_v_1 & (~ chn_a_rsci_bawt) & or_9_cse; + assign main_stage_v_2_mx0c1 = or_9_cse & (~ main_stage_v_1) & main_stage_v_2; + assign chn_a_rsci_oswt_unreg = or_tmp_50; + assign chn_o_rsci_oswt_unreg = and_dcpl_16; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_14_10 <= 5'b0; + chn_o_rsci_d_15 <= 1'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_14_10 <= MUX_v_5_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_and_nl), + 5'b11111, IsNaN_8U_23U_land_lpi_1_dfm_2); + chn_o_rsci_d_15 <= (FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2)) | IsNaN_8U_23U_land_lpi_1_dfm_2; + chn_o_rsci_d_16 <= FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_9_cse & main_stage_v_2 & IsNaN_8U_23U_land_lpi_1_dfm_2) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1, + (FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_1_nl), + chn_o_rsci_d_9_0_mx0c1); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_15 | and_dcpl_17) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_17; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_50 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= 3'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_3_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2[2:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1 <= 29'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_5_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1 <= chn_a_rsci_d_mxwt[28:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_7_nl) ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_9_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_10_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1 <= 1'b0; + IsNaN_8U_23U_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= 1'b0; + end + else if ( FpWidthDec_8U_23U_6U_10U_0U_1U_if_and_cse ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1; + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1 <= chn_a_rsci_d_mxwt[31]; + IsNaN_8U_23U_nor_itm_2 <= IsNaN_8U_23U_nor_tmp; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & (and_42_cse | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= 11'b0; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= 1'b0; + end + else if ( FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm[23:13]; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= ((FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[23])) & ((FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[23])); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_15_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & mux_tmp_13 ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1 <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4 + <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_2 <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + <= 1'b0; + end + else if ( Fp32ToFp17_and_1_cse ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1 <= FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3; + IsNaN_8U_23U_land_lpi_1_dfm_2 <= nor_16_cse; + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1 + <= ((FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_else_mux_2_nl) & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc)) + | FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3; + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & not_tmp_20 ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5 <= FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1 <= 10'b0; + end + else if ( core_wen & ((nor_16_cse & or_9_cse) | and_48_rgt) & (mux_19_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1 <= MUX_v_10_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[9:0]), + (FpMantRNE_24U_11U_else_acc_nl), and_48_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1 + <= 5'b0; + end + else if ( core_wen & (FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt | FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt + | FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt | FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt) + & not_tmp_20 ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1 + <= MUX1HOT_v_5_4_2(5'b1, (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[27:23]), + (FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3[4:0]), 5'b11110, {FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt + , FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt , FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt + , FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3 + <= 1'b0; + end + else if ( core_wen & (and_dcpl_29 | and_50_rgt) & mux_tmp ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3 + <= MUX_s_1_2_2(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1, FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs, + and_50_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_20_nl) ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= FpMantRNE_24U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= 1'b0; + end + else if ( core_wen & ((and_dcpl_29 & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1) + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) | and_53_rgt) & mux_tmp + ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= MUX_s_1_2_2(FpMantRNE_24U_11U_else_and_svs_mx0w0, + FpMantRNE_24U_11U_else_and_svs, and_53_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_9 | (~ chn_a_rsci_bawt) | or_dcpl_11 | (fsm_output[0]))) + ) begin + FpMantRNE_24U_11U_else_and_svs <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs + <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_9 | (~ chn_a_rsci_bawt) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1) + | (fsm_output[0]))) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + end + end + assign FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_not_3_nl = ~ FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_and_nl + = MUX_v_5_2_2(5'b00000, FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1, + (FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_not_3_nl)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_mux_1_nl = MUX_v_10_2_2((FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[9:0]), + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1, FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_nl = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_mux_1_nl), + 10'b1111111111, FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_1_nl + = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_nl), 10'b1111111111, + FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2)); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + = (~ (chn_a_rsci_d_mxwt[26:24])) + 3'b1; + assign or_2_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + assign mux_2_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_3), or_2_nl); + assign nor_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 + | (~ and_tmp)); + assign nor_33_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3)); + assign mux_3_nl = MUX_s_1_2_2((nor_nl), (mux_2_nl), nor_33_nl); + assign and_nl = chn_a_rsci_bawt & (~(or_tmp_9 & FpMantRNE_24U_11U_else_and_svs + & (FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1)))); + assign nor_32_nl = ~((~((~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3))) + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3) + | FpMantRNE_24U_11U_else_and_svs_st_2)) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ main_stage_v_1)); + assign and_82_nl = or_tmp_11 & FpMantRNE_24U_11U_else_and_svs_2; + assign mux_4_nl = MUX_s_1_2_2(main_stage_v_1, (nor_32_nl), and_82_nl); + assign mux_5_nl = MUX_s_1_2_2((mux_4_nl), (and_nl), or_9_cse); + assign or_16_nl = (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + assign mux_6_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_3), or_16_nl); + assign nor_28_nl = ~((~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) | + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_5_nl = ~((~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3)); + assign mux_7_nl = MUX_s_1_2_2((nor_28_nl), (mux_6_nl), nor_5_nl); + assign mux_8_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_3), FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1); + assign nor_27_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_6_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3)); + assign mux_9_nl = MUX_s_1_2_2((nor_27_nl), (mux_8_nl), nor_6_nl); + assign mux_10_nl = MUX_s_1_2_2(and_tmp, mux_tmp_1, FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3); + assign nor_23_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4) + | (~ main_stage_v_2) | (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt); + assign and_14_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & and_42_cse; + assign mux_14_nl = MUX_s_1_2_2(mux_tmp_13, (and_14_nl), FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4); + assign mux_15_nl = MUX_s_1_2_2((mux_14_nl), (nor_23_nl), FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_else_mux_2_nl = MUX_s_1_2_2((~ + (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[28])), (FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3[5]), + FpMantRNE_24U_11U_else_and_svs_2); + assign nl_FpMantRNE_24U_11U_else_acc_nl = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:13]) + + conv_u2u_1_10(FpMantRNE_24U_11U_else_carry_sva_2); + assign FpMantRNE_24U_11U_else_acc_nl = nl_FpMantRNE_24U_11U_else_acc_nl[9:0]; + assign nand_5_nl = ~(or_9_cse & mux_tmp_18); + assign nor_19_nl = ~(nor_20_cse | mux_tmp_18); + assign and_76_nl = ((~(and_77_cse | FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4))) + | IsNaN_8U_23U_land_lpi_1_dfm_2) & main_stage_v_2; + assign mux_19_nl = MUX_s_1_2_2((nor_19_nl), (nand_5_nl), and_76_nl); + assign nor_17_nl = ~((~ or_tmp_9) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~(FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1 + & chn_a_rsci_bawt))); + assign and_86_nl = or_tmp_11 & main_stage_v_1 & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3) + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3) + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3; + assign mux_20_nl = MUX_s_1_2_2((and_86_nl), (nor_17_nl), or_9_cse); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [4:0] MUX1HOT_v_5_4_2; + input [4:0] input_3; + input [4:0] input_2; + input [4:0] input_1; + input [4:0] input_0; + input [3:0] sel; + reg [4:0] result; + begin + result = input_0 & {5{sel[0]}}; + result = result | ( input_1 & {5{sel[1]}}); + result = result | ( input_2 & {5{sel[2]}}); + result = result | ( input_3 & {5{sel[3]}}); + MUX1HOT_v_5_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [8:0] conv_u2s_8_9 ; + input [7:0] vector ; + begin + conv_u2s_8_9 = {1'b0, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [4:0] conv_u2u_4_5 ; + input [3:0] vector ; + begin + conv_u2u_4_5 = {1'b0, vector}; + end + endfunction + function [7:0] conv_u2u_7_8 ; + input [6:0] vector ; + begin + conv_u2u_7_8 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17 +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP17_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP32_TO_FP17_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_to_fp17_core HLS_fp32_to_fp17_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp17.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp17.v.vcp new file mode 100644 index 0000000..720316a --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_fp32_to_fp17.v.vcp @@ -0,0 +1,1457 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_fp32_to_fp17.v +module FP32_TO_FP17_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/FP32_TO_FP17_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module FP32_TO_FP17_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_r_beh_v4.v +module FP32_TO_FP17_mgc_shift_r_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshr_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshr_u(a,s,1'b0); + end + endgenerate +//Shift right - unsigned shift argument + function [width_z-1:0] fshr_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = signd_a ? width_a : width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg signed [len-1:0] result; + reg signed [len-1:0] result_t; + begin + result_t = $signed( {(len){sbit}} ); + result_t[width_a-1:0] = arg1; + result = result_t >>> arg2; + fshr_u = result[olen-1:0]; + end + endfunction // fshl_u +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module FP32_TO_FP17_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-159 +// Generated date: Mon Jul 3 21:36:12 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP17_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP17_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: FP32_TO_FP17_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module FP32_TO_FP17_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_fp32_to_fp17_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_fp32_to_fp17_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_staller +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [31:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [31:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [31:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_32_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 32'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [31:0] MUX_v_32_2_2; + input [31:0] input_0; + input [31:0] input_1; + input [0:0] sel; + reg [31:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_32_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP17_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(chn_o_rsci_d), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp HLS_fp32_to_fp17_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [31:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [31:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP17_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd32)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp HLS_fp32_to_fp17_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17_core +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [31:0] chn_a_rsci_d_mxwt; + wire core_wten; + reg chn_o_rsci_iswt0; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg chn_o_rsci_d_16; + reg [9:0] chn_o_rsci_d_9_0; + reg chn_o_rsci_d_15; + reg [4:0] chn_o_rsci_d_14_10; + wire [1:0] fsm_output; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp; + wire IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + wire IsNaN_8U_23U_nor_tmp; + wire or_tmp_3; + wire mux_tmp; + wire mux_tmp_1; + wire and_tmp; + wire or_tmp_9; + wire or_tmp_11; + wire or_tmp_24; + wire mux_tmp_13; + wire or_tmp_28; + wire not_tmp_20; + wire mux_tmp_18; + wire and_dcpl_9; + wire and_dcpl_15; + wire and_dcpl_16; + wire and_dcpl_17; + wire and_dcpl_29; + wire or_dcpl_11; + wire or_tmp_50; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs; + reg FpMantRNE_24U_11U_else_and_svs; + reg main_stage_v_1; + reg main_stage_v_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4; + reg [2:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + wire [3:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2; + reg FpMantRNE_24U_11U_else_carry_sva_2; + reg FpMantRNE_24U_11U_else_and_svs_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5; + reg IsNaN_8U_23U_land_lpi_1_dfm_2; + reg [10:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2; + reg FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2; + reg IsNaN_8U_23U_nor_itm_2; + reg IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4; + reg FpMantRNE_24U_11U_else_and_svs_st_2; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1; + reg [28:0] FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1; + reg [9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1; + reg FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1; + reg [4:0] FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1; + wire main_stage_en_1; + wire FpMantRNE_24U_11U_else_carry_sva_mx0w0; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp; + wire [10:0] FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire [11:0] nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva; + wire chn_o_and_cse; + wire or_9_cse; + wire nor_16_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire nor_20_cse; + wire and_77_cse; + wire and_42_cse; + wire and_48_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt; + wire and_50_rgt; + wire and_53_rgt; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm; + wire HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire chn_o_rsci_d_9_0_mx0c1; + wire main_stage_v_1_mx0c1; + wire FpMantRNE_24U_11U_else_and_svs_mx0w0; + wire main_stage_v_2_mx0c1; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2; + wire [5:0] FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3; + wire [6:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva; + wire [22:0] FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva; + wire [23:0] FpMantDecShiftRight_23U_8U_10U_least_mask_sva; + wire [4:0] FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c; + wire FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse; + wire Fp32ToFp17_and_1_cse; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_if_and_cse; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + wire FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1; + wire[0:0] iMantWidth_oMantWidth_prb; + wire[0:0] iExpoWidth_oExpoWidth_prb; + wire[0:0] shift_0_prb; + wire[0:0] and_11; + wire[4:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_and_nl; + wire[0:0] FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_not_3_nl; + wire[9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_1_nl; + wire[9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_nl; + wire[9:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_mux_1_nl; + wire[0:0] mux_3_nl; + wire[0:0] mux_2_nl; + wire[0:0] or_2_nl; + wire[0:0] nor_nl; + wire[0:0] nor_33_nl; + wire[0:0] mux_5_nl; + wire[0:0] and_nl; + wire[0:0] mux_4_nl; + wire[0:0] nor_32_nl; + wire[0:0] and_82_nl; + wire[0:0] mux_7_nl; + wire[0:0] mux_6_nl; + wire[0:0] or_16_nl; + wire[0:0] nor_28_nl; + wire[0:0] nor_5_nl; + wire[0:0] mux_9_nl; + wire[0:0] mux_8_nl; + wire[0:0] nor_27_nl; + wire[0:0] nor_6_nl; + wire[0:0] mux_10_nl; + wire[0:0] mux_11_nl; + wire[0:0] nor_25_nl; + wire[0:0] nor_26_nl; + wire[0:0] mux_15_nl; + wire[0:0] nor_23_nl; + wire[0:0] mux_14_nl; + wire[0:0] and_14_nl; + wire[0:0] mux_16_nl; + wire[9:0] FpMantRNE_24U_11U_else_acc_nl; + wire[10:0] nl_FpMantRNE_24U_11U_else_acc_nl; + wire[0:0] mux_19_nl; + wire[0:0] nand_5_nl; + wire[0:0] nor_19_nl; + wire[0:0] and_76_nl; + wire[0:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_else_mux_2_nl; + wire[0:0] mux_20_nl; + wire[0:0] nor_17_nl; + wire[0:0] and_86_nl; + wire[0:0] and_22_nl; + wire[8:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl; + wire[7:0] FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl; + wire[8:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl; + wire[8:0] FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl; + wire[9:0] nl_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl; + wire[22:0] FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl; + wire[23:0] nl_FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl; + wire[0:0] mux_12_nl; + wire[0:0] and_80_nl; + wire[0:0] and_81_nl; + wire[0:0] nand_6_nl; + wire[0:0] nor_21_nl; + wire[0:0] nor_9_nl; + wire[0:0] or_34_nl; + wire[0:0] nand_9_nl; +// Interconnect Declarations for Component Instantiations + wire [23:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a = {1'b1 , (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0])}; + wire [3:0] nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s = {FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[23]))}; + wire [5:0] nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s; + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s = FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva + + 5'b11111; + wire [16:0] nl_HLS_fp32_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_fp32_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d = {chn_o_rsci_d_16 + , chn_o_rsci_d_15 , chn_o_rsci_d_14_10 , chn_o_rsci_d_9_0}; + FP32_TO_FP17_mgc_shift_r_v4 #(.width_a(32'sd24), + .signd_a(32'sd0), + .width_s(32'sd4), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg ( + .a(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_a[23:0]), + .s(nl_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_rg_s[3:0]), + .z(FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm) + ); + FP32_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg ( + .a(1'b1), + .s(nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_lshift_rg_s[4:0]), + .z(FpMantDecShiftRight_23U_8U_10U_guard_mask_sva) + ); + FP32_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd1), + .signd_a(32'sd0), + .width_s(32'sd5), + .width_z(32'sd24)) FpMantDecShiftRight_23U_8U_10U_least_mask_lshift_rg ( + .a(1'b1), + .s(FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva), + .z(FpMantDecShiftRight_23U_8U_10U_least_mask_sva) + ); + HLS_fp32_to_fp17_core_chn_a_rsci HLS_fp32_to_fp17_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_fp32_to_fp17_core_chn_o_rsci HLS_fp32_to_fp17_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_fp32_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_fp32_to_fp17_core_staller HLS_fp32_to_fp17_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_fp32_to_fp17_core_core_fsm HLS_fp32_to_fp17_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign iMantWidth_oMantWidth_prb = HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iMantWidth >= oMantWidth) - ../include/nvdla_float.h: line 669 +// PSL HLS_fp32_to_fp17_core_nvdla_float_h_ln669_assert_iMantWidth_ge_oMantWidth : assert { iMantWidth_oMantWidth_prb } @rose(nvdla_core_clk); + assign iExpoWidth_oExpoWidth_prb = HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0; +// assert(iExpoWidth >= oExpoWidth) - ../include/nvdla_float.h: line 670 +// PSL HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth : assert { iExpoWidth_oExpoWidth_prb } @rose(nvdla_core_clk); + assign and_11 = and_42_cse & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3) + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3); + assign shift_0_prb = MUX1HOT_s_1_1_2(readslicef_5_1_4((({1'b1 , (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2) + , (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[23])}) + 5'b1)), and_11); +// assert(shift > 0) - ../include/nvdla_float.h: line 286 +// PSL HLS_fp32_to_fp17_core_nvdla_float_h_ln286_assert_shift_gt_0 : assert { shift_0_prb } @rose(nvdla_core_clk); + assign chn_o_and_cse = core_wen & (~(and_dcpl_9 | (~ main_stage_v_2))); + assign or_9_cse = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_if_and_cse = core_wen & (~ and_dcpl_9) & + mux_tmp; + assign and_42_cse = or_9_cse & main_stage_v_1; + assign nor_25_nl = ~((~ main_stage_v_1) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3); + assign nor_26_nl = ~((~ main_stage_v_2) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4); + assign mux_11_nl = MUX_s_1_2_2((nor_26_nl), (nor_25_nl), or_9_cse); + assign FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse = core_wen & (~ and_dcpl_9) + & (mux_11_nl); + assign mux_16_nl = MUX_s_1_2_2(and_42_cse, or_tmp_24, main_stage_v_2); + assign Fp32ToFp17_and_1_cse = core_wen & (~ and_dcpl_9) & (mux_16_nl); + assign nor_16_cse = ~(IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 | IsNaN_8U_23U_nor_itm_2); + assign nor_20_cse = ~((~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt); + assign and_77_cse = FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4 + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4; + assign and_48_rgt = or_tmp_11 & or_9_cse; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt = FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc + & (~ and_dcpl_9); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt = (~ FpMantRNE_24U_11U_else_and_svs_2) + & FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c & (~ and_dcpl_9); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt = FpMantRNE_24U_11U_else_and_svs_2 + & FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c & (~ and_dcpl_9); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt = FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0 + & (~ and_dcpl_9); + assign and_50_rgt = or_9_cse & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1); + assign and_53_rgt = or_dcpl_11 & or_9_cse; + assign and_22_nl = main_stage_en_1 & (fsm_output[1]); + assign HLS_fp32_to_fp17_core_nvdla_float_h_ln670_assert_iExpoWidth_ge_oExpoWidth_sig_mx0 + = MUX_s_1_2_2((MUX1HOT_s_1_1_2(1'b1, fsm_output[0])), (MUX1HOT_s_1_1_2(1'b1, + and_22_nl)), fsm_output[1]); + assign FpMantRNE_24U_11U_else_and_svs_mx0w0 = FpMantRNE_24U_11U_else_carry_sva_mx0w0 + & (chn_a_rsci_d_mxwt[22:13]==10'b1111111111); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl = ({1'b1 , (~ (chn_a_rsci_d_mxwt[30:23]))}) + + 9'b1100001; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl[8:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_nl)); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl = conv_u2u_7_8(chn_a_rsci_d_mxwt[30:24]) + + 8'b11010101; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl[7:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 = readslicef_8_1_7((FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_nl)); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl = conv_u2s_8_9(chn_a_rsci_d_mxwt[30:23]) + + 9'b101100001; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl[8:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1 = readslicef_9_1_8((FpWidthDec_8U_23U_6U_10U_0U_1U_acc_nl)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp = ~((FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3==6'b111111) + & FpMantRNE_24U_11U_else_and_svs_2 & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0 = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3); + assign FpMantRNE_24U_11U_else_carry_sva_mx0w0 = (chn_a_rsci_d_mxwt[12]) & ((chn_a_rsci_d_mxwt[0]) + | (chn_a_rsci_d_mxwt[1]) | (chn_a_rsci_d_mxwt[2]) | (chn_a_rsci_d_mxwt[3]) + | (chn_a_rsci_d_mxwt[4]) | (chn_a_rsci_d_mxwt[5]) | (chn_a_rsci_d_mxwt[6]) + | (chn_a_rsci_d_mxwt[7]) | (chn_a_rsci_d_mxwt[8]) | (chn_a_rsci_d_mxwt[9]) + | (chn_a_rsci_d_mxwt[10]) | (chn_a_rsci_d_mxwt[11]) | (chn_a_rsci_d_mxwt[13])); + assign IsNaN_8U_23U_nor_tmp = ~((chn_a_rsci_d_mxwt[22:0]!=23'b00000000000000000000000)); + assign IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp = ~((chn_a_rsci_d_mxwt[30:23]==8'b11111111)); + assign nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + + conv_u2u_1_11(FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2); + assign FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva = nl_FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2 = ((~((FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[10]) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4)) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4) + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4; + assign main_stage_en_1 = chn_a_rsci_bawt & or_9_cse; + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3 = ({(~ (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[28])) + , (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[27:23])}) + 6'b1; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3 = nl_FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3[5:0]; + assign FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]); + assign nl_FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl = (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[22:0]) + + 23'b11111111111111111111111; + assign FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl = nl_FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl[22:0]; + assign FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_stick_mask_acc_nl); + assign FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:0]) + & (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[22:0]); + assign nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = conv_u2u_4_5({FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + , (~ (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[23]))}) + 5'b1101; + assign FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva = nl_FpMantDecShiftRight_23U_8U_10U_guard_mask_acc_1_psp_sva[4:0]; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc = + ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp | FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_and_1_m1c = FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_and_tmp = FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3); + assign or_tmp_3 = (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt | (~ main_stage_v_1); + assign mux_tmp = MUX_s_1_2_2(main_stage_v_1, chn_a_rsci_bawt, or_9_cse); + assign mux_tmp_1 = MUX_s_1_2_2((~ or_tmp_3), mux_tmp, FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1); + assign and_tmp = FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1 & or_9_cse & chn_a_rsci_bawt; + assign or_tmp_9 = IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp | IsNaN_8U_23U_nor_tmp; + assign or_tmp_11 = IsNaN_8U_23U_nor_itm_2 | IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + assign or_tmp_24 = nor_20_cse | main_stage_v_1; + assign and_80_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + & main_stage_v_2; + assign mux_12_nl = MUX_s_1_2_2(and_42_cse, or_tmp_24, and_80_nl); + assign and_81_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + & main_stage_v_2 & reg_chn_o_rsci_ld_core_psct_cse & (~ chn_o_rsci_bawt); + assign mux_tmp_13 = MUX_s_1_2_2((and_81_nl), (mux_12_nl), FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3); + assign or_tmp_28 = (FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3) + | (~(main_stage_v_1 & or_tmp_11)); + assign nand_6_nl = ~(or_9_cse & or_tmp_28); + assign nor_21_nl = ~(nor_20_cse | or_tmp_28); + assign nor_9_nl = ~(and_77_cse | IsNaN_8U_23U_land_lpi_1_dfm_2 | (~ main_stage_v_2)); + assign not_tmp_20 = MUX_s_1_2_2((nor_21_nl), (nand_6_nl), nor_9_nl); + assign or_34_nl = (~ main_stage_v_1) | IsNaN_8U_23U_nor_itm_2 | IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2; + assign nand_9_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_nand_tmp & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3)); + assign mux_tmp_18 = MUX_s_1_2_2((~ main_stage_v_1), (or_34_nl), nand_9_nl); + assign and_dcpl_9 = (~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_15 = or_9_cse & main_stage_v_2; + assign and_dcpl_16 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign and_dcpl_17 = and_dcpl_16 & (~ main_stage_v_2); + assign and_dcpl_29 = or_9_cse & FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1; + assign or_dcpl_11 = (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1) | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1); + assign or_tmp_50 = or_9_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = main_stage_en_1 | (fsm_output[0]); + assign chn_o_rsci_d_9_0_mx0c1 = or_9_cse & main_stage_v_2 & (~ IsNaN_8U_23U_land_lpi_1_dfm_2); + assign main_stage_v_1_mx0c1 = main_stage_v_1 & (~ chn_a_rsci_bawt) & or_9_cse; + assign main_stage_v_2_mx0c1 = or_9_cse & (~ main_stage_v_1) & main_stage_v_2; + assign chn_a_rsci_oswt_unreg = or_tmp_50; + assign chn_o_rsci_oswt_unreg = and_dcpl_16; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + chn_o_rsci_iswt0 <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ main_stage_en_1) & (fsm_output[1])); + chn_o_rsci_iswt0 <= and_dcpl_15; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_14_10 <= 5'b0; + chn_o_rsci_d_15 <= 1'b0; + chn_o_rsci_d_16 <= 1'b0; + end + else if ( chn_o_and_cse ) begin + chn_o_rsci_d_14_10 <= MUX_v_5_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_and_nl), + 5'b11111, IsNaN_8U_23U_land_lpi_1_dfm_2); + chn_o_rsci_d_15 <= (FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2)) | IsNaN_8U_23U_land_lpi_1_dfm_2; + chn_o_rsci_d_16 <= FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & ((or_9_cse & main_stage_v_2 & IsNaN_8U_23U_land_lpi_1_dfm_2) + | chn_o_rsci_d_9_0_mx0c1) ) begin + chn_o_rsci_d_9_0 <= MUX_v_10_2_2(FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1, + (FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_1_nl), + chn_o_rsci_d_9_0_mx0c1); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (and_dcpl_15 | and_dcpl_17) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_17; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_1 <= 1'b0; + end + else if ( core_wen & (or_tmp_50 | main_stage_v_1_mx0c1) ) begin + main_stage_v_1 <= ~ main_stage_v_1_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= 3'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_3_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 <= nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2[2:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1 <= 29'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_5_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1 <= chn_a_rsci_d_mxwt[28:0]; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_7_nl) ) begin + FpMantRNE_24U_11U_else_and_svs_st_2 <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_9_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_10_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1 <= 1'b0; + IsNaN_8U_23U_nor_itm_2 <= 1'b0; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= 1'b0; + end + else if ( FpWidthDec_8U_23U_6U_10U_0U_1U_if_and_cse ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1; + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1 <= chn_a_rsci_d_mxwt[31]; + IsNaN_8U_23U_nor_itm_2 <= IsNaN_8U_23U_nor_tmp; + IsNaN_8U_23U_IsNaN_8U_23U_nand_itm_2 <= IsNaN_8U_23U_IsNaN_8U_23U_nand_tmp; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + main_stage_v_2 <= 1'b0; + end + else if ( core_wen & (and_42_cse | main_stage_v_2_mx0c1) ) begin + main_stage_v_2 <= ~ main_stage_v_2_mx0c1; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= 11'b0; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= 1'b0; + end + else if ( FpMantDecShiftRight_23U_8U_10U_i_mant_s_and_cse ) begin + FpMantDecShiftRight_23U_8U_10U_i_mant_s_slc_FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_23_13_itm_2 + <= FpMantDecShiftRight_23U_8U_10U_i_mant_s_rshift_itm[23:13]; + FpMantDecShiftRight_23U_8U_10U_carry_and_itm_2 <= ((FpMantDecShiftRight_23U_8U_10U_guard_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_guard_mask_sva[23])) & ((FpMantDecShiftRight_23U_8U_10U_stick_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_bits_22_0_sva!=23'b00000000000000000000000) + | (FpMantDecShiftRight_23U_8U_10U_least_mask_sva[23])); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_15_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & mux_tmp_13 ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1 <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4 + <= 1'b0; + IsNaN_8U_23U_land_lpi_1_dfm_2 <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4 + <= 1'b0; + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + <= 1'b0; + end + else if ( Fp32ToFp17_and_1_cse ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_31_1 <= FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_31_1; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3; + IsNaN_8U_23U_land_lpi_1_dfm_2 <= nor_16_cse; + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_5_1 + <= ((FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_else_mux_2_nl) & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_nor_ssc)) + | FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0; + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3; + FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4 + <= FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & not_tmp_20 ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5 <= FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_3_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1 <= 10'b0; + end + else if ( core_wen & ((nor_16_cse & or_9_cse) | and_48_rgt) & (mux_19_nl) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1 <= MUX_v_10_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[9:0]), + (FpMantRNE_24U_11U_else_acc_nl), and_48_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1 + <= 5'b0; + end + else if ( core_wen & (FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt | FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt + | FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt | FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt) + & not_tmp_20 ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1 + <= MUX1HOT_v_5_4_2(5'b1, (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[27:23]), + (FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3[4:0]), 5'b11110, {FpWidthDec_8U_23U_6U_10U_0U_1U_and_4_rgt + , FpWidthDec_8U_23U_6U_10U_0U_1U_and_2_rgt , FpWidthDec_8U_23U_6U_10U_0U_1U_and_3_rgt + , FpWidthDec_8U_23U_6U_10U_0U_1U_and_5_rgt}); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3 + <= 1'b0; + end + else if ( core_wen & (and_dcpl_29 | and_50_rgt) & mux_tmp ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3 + <= MUX_s_1_2_2(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1, FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs, + and_50_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= 1'b0; + end + else if ( core_wen & (~ and_dcpl_9) & (mux_20_nl) ) begin + FpMantRNE_24U_11U_else_carry_sva_2 <= FpMantRNE_24U_11U_else_carry_sva_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= 1'b0; + end + else if ( core_wen & ((and_dcpl_29 & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1) + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) | and_53_rgt) & mux_tmp + ) begin + FpMantRNE_24U_11U_else_and_svs_2 <= MUX_s_1_2_2(FpMantRNE_24U_11U_else_and_svs_mx0w0, + FpMantRNE_24U_11U_else_and_svs, and_53_rgt); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_24U_11U_else_and_svs <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_9 | (~ chn_a_rsci_bawt) | or_dcpl_11 | (fsm_output[0]))) + ) begin + FpMantRNE_24U_11U_else_and_svs <= FpMantRNE_24U_11U_else_and_svs_mx0w0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs + <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_9 | (~ chn_a_rsci_bawt) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1) + | (fsm_output[0]))) ) begin + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs + <= FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + end + end + assign FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_not_3_nl = ~ FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2; + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_and_nl + = MUX_v_5_2_2(5'b00000, FpWidthDec_8U_23U_6U_10U_0U_1U_FpWidthDec_8U_23U_6U_10U_0U_1U_mux1h_itm_1_4_0_1, + (FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_not_3_nl)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_mux_1_nl = MUX_v_10_2_2((FpMantDecShiftRight_23U_8U_10U_o_mant_sum_sva[9:0]), + FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_2_9_0_1, FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_nl = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_mux_1_nl), + 10'b1111111111, FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5)); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_1_nl + = ~(MUX_v_10_2_2((FpWidthDec_8U_23U_6U_10U_0U_1U_else_2_nor_nl), 10'b1111111111, + FpWidthDec_8U_23U_6U_10U_0U_1U_is_zero_lpi_1_dfm_2)); + assign nl_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_i_shift_acc_psp_1_sva_2 + = (~ (chn_a_rsci_d_mxwt[26:24])) + 3'b1; + assign or_2_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + assign mux_2_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_3), or_2_nl); + assign nor_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1 | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 + | (~ and_tmp)); + assign nor_33_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3)); + assign mux_3_nl = MUX_s_1_2_2((nor_nl), (mux_2_nl), nor_33_nl); + assign and_nl = chn_a_rsci_bawt & (~(or_tmp_9 & FpMantRNE_24U_11U_else_and_svs + & (FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1)))); + assign nor_32_nl = ~((~((~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3))) + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3) + | FpMantRNE_24U_11U_else_and_svs_st_2)) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ main_stage_v_1)); + assign and_82_nl = or_tmp_11 & FpMantRNE_24U_11U_else_and_svs_2; + assign mux_4_nl = MUX_s_1_2_2(main_stage_v_1, (nor_32_nl), and_82_nl); + assign mux_5_nl = MUX_s_1_2_2((mux_4_nl), (and_nl), or_9_cse); + assign or_16_nl = (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1; + assign mux_6_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_3), or_16_nl); + assign nor_28_nl = ~((~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) | + FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_5_nl = ~((~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3)); + assign mux_7_nl = MUX_s_1_2_2((nor_28_nl), (mux_6_nl), nor_5_nl); + assign mux_8_nl = MUX_s_1_2_2(mux_tmp_1, (~ or_tmp_3), FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1); + assign nor_27_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~ and_tmp)); + assign nor_6_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3)); + assign mux_9_nl = MUX_s_1_2_2((nor_27_nl), (mux_8_nl), nor_6_nl); + assign mux_10_nl = MUX_s_1_2_2(and_tmp, mux_tmp_1, FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3); + assign nor_23_nl = ~(FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_4) + | (~ main_stage_v_2) | (~ reg_chn_o_rsci_ld_core_psct_cse) | chn_o_rsci_bawt); + assign and_14_nl = FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & and_42_cse; + assign mux_14_nl = MUX_s_1_2_2(mux_tmp_13, (and_14_nl), FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_4); + assign mux_15_nl = MUX_s_1_2_2((mux_14_nl), (nor_23_nl), FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3); + assign FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_else_mux_2_nl = MUX_s_1_2_2((~ + (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[28])), (FpWidthDec_8U_23U_6U_10U_0U_1U_o_expo_sva_3[5]), + FpMantRNE_24U_11U_else_and_svs_2); + assign nl_FpMantRNE_24U_11U_else_acc_nl = (FpWidthDec_8U_23U_6U_10U_0U_1U_bits_sva_1_28_0_1[22:13]) + + conv_u2u_1_10(FpMantRNE_24U_11U_else_carry_sva_2); + assign FpMantRNE_24U_11U_else_acc_nl = nl_FpMantRNE_24U_11U_else_acc_nl[9:0]; + assign nand_5_nl = ~(or_9_cse & mux_tmp_18); + assign nor_19_nl = ~(nor_20_cse | mux_tmp_18); + assign and_76_nl = ((~(and_77_cse | FpWidthDec_8U_23U_6U_10U_0U_1U_is_inf_lpi_1_dfm_5 + | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_4))) + | IsNaN_8U_23U_land_lpi_1_dfm_2) & main_stage_v_2; + assign mux_19_nl = MUX_s_1_2_2((nor_19_nl), (nand_5_nl), and_76_nl); + assign nor_17_nl = ~((~ or_tmp_9) | (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_itm_8_1) + | FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_itm_7_1 | (~(FpWidthDec_8U_23U_6U_10U_0U_1U_acc_itm_8_1 + & chn_a_rsci_bawt))); + assign and_86_nl = or_tmp_11 & main_stage_v_1 & FpWidthDec_8U_23U_6U_10U_0U_1U_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_st_3) + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_st_3 + & (~ FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_if_acc_7_svs_3) + & FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_if_slc_FpWidthDec_8U_23U_6U_10U_0U_1U_else_else_acc_8_svs_3; + assign mux_20_nl = MUX_s_1_2_2((and_86_nl), (nor_17_nl), or_9_cse); + function [0:0] MUX1HOT_s_1_1_2; + input [0:0] input_0; + input [0:0] sel; + reg [0:0] result; + begin + result = input_0 & {1{sel[0]}}; + MUX1HOT_s_1_1_2 = result; + end + endfunction + function [4:0] MUX1HOT_v_5_4_2; + input [4:0] input_3; + input [4:0] input_2; + input [4:0] input_1; + input [4:0] input_0; + input [3:0] sel; + reg [4:0] result; + begin + result = input_0 & {5{sel[0]}}; + result = result | ( input_1 & {5{sel[1]}}); + result = result | ( input_2 & {5{sel[2]}}); + result = result | ( input_3 & {5{sel[3]}}); + MUX1HOT_v_5_4_2 = result; + end + endfunction + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_8_1_7; + input [7:0] vector; + reg [7:0] tmp; + begin + tmp = vector >> 7; + readslicef_8_1_7 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_9_1_8; + input [8:0] vector; + reg [8:0] tmp; + begin + tmp = vector >> 8; + readslicef_9_1_8 = tmp[0:0]; + end + endfunction + function [8:0] conv_u2s_8_9 ; + input [7:0] vector ; + begin + conv_u2s_8_9 = {1'b0, vector}; + end + endfunction + function [9:0] conv_u2u_1_10 ; + input [0:0] vector ; + begin + conv_u2u_1_10 = {{9{1'b0}}, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [4:0] conv_u2u_4_5 ; + input [3:0] vector ; + begin + conv_u2u_4_5 = {1'b0, vector}; + end + endfunction + function [7:0] conv_u2u_7_8 ; + input [6:0] vector ; + begin + conv_u2u_7_8 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_fp32_to_fp17 +// ------------------------------------------------------------------ +module HLS_fp32_to_fp17 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [31:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + FP32_TO_FP17_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + FP32_TO_FP17_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_fp32_to_fp17_core HLS_fp32_to_fp17_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_uint16_to_fp17.v b/designs/src/NVDLA/vmod/vlibs/HLS_uint16_to_fp17.v new file mode 100644 index 0000000..9f99161 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_uint16_to_fp17.v @@ -0,0 +1,935 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_uint16_to_fp17.v +module UINT16_TO_FP17_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/UINT16_TO_FP17_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module UINT16_TO_FP17_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module UINT16_TO_FP17_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-176 +// Generated date: Wed Nov 23 14:25:06 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: UINT16_TO_FP17_leading_sign_16_0 +// ------------------------------------------------------------------ +module UINT16_TO_FP17_leading_sign_16_0 ( + mantissa, rtn +); + input [15:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire[3:0] IntLeadZero_16U_leading_sign_16_0_rtn_IntLeadZero_16U_leading_sign_16_0_rtn_and_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_and_55_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_and_53_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_and_60_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_not_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[13:12]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[15:14]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[11:10]!=2'b00)); + assign c_h_1_2 = IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[9:8]==2'b00) + & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[5:4]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[7:6]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[3:2]!=2'b00)); + assign c_h_1_5 = IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4 = (mantissa[1:0]==2'b00) + & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5 & c_h_1_6; + assign IntLeadZero_16U_leading_sign_16_0_rtn_and_55_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_and_53_nl = IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_and_60_nl = (~((mantissa[15]) | (~((mantissa[14:13]!=2'b01))))) + & (~(((mantissa[11]) | (~((mantissa[10:9]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[7]) + | (~((mantissa[6:5]!=2'b01))))) & (~(((mantissa[3]) | (~((mantissa[2:1]!=2'b01)))) + & c_h_1_5)))) & c_h_1_6)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_not_nl = ~ IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4; + assign IntLeadZero_16U_leading_sign_16_0_rtn_IntLeadZero_16U_leading_sign_16_0_rtn_and_nl + = MUX_v_4_2_2(4'b0000, ({c_h_1_6 , (IntLeadZero_16U_leading_sign_16_0_rtn_and_55_nl) + , (IntLeadZero_16U_leading_sign_16_0_rtn_and_53_nl) , (IntLeadZero_16U_leading_sign_16_0_rtn_and_60_nl)}), + (IntLeadZero_16U_leading_sign_16_0_rtn_not_nl)); + assign rtn = {IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4 , (IntLeadZero_16U_leading_sign_16_0_rtn_IntLeadZero_16U_leading_sign_16_0_rtn_and_nl)}; + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-173 +// Generated date: Mon Jun 12 22:24:10 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: UINT16_TO_FP17_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module UINT16_TO_FP17_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: UINT16_TO_FP17_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module UINT16_TO_FP17_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_uint16_to_fp17_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_uint16_to_fp17_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_staller +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [15:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [15:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [15:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_16_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 16'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [15:0] MUX_v_16_2_2; + input [15:0] input_0; + input [15:0] input_1; + input [0:0] sel; + reg [15:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_16_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + wire [16:0] nl_chn_o_rsci_d; + assign nl_chn_o_rsci_d = {2'b0 , (chn_o_rsci_d[14:0])}; + UINT16_TO_FP17_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(nl_chn_o_rsci_d[16:0]), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [15:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [15:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + UINT16_TO_FP17_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd16)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [15:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg [4:0] chn_o_rsci_d_14_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire and_dcpl_2; + wire or_dcpl_1; + wire and_dcpl_7; + wire and_dcpl_22; + wire or_tmp_7; + reg FpMantRNE_17U_11U_else_and_svs; + wire and_4_mdf; + wire FpMantRNE_17U_11U_else_and_svs_mx1; + wire FpFractionToFloat_16U_6U_10U_unequal_tmp; + wire FpMantRNE_17U_11U_else_carry_sva; + wire [16:0] FpMantRNE_17U_11U_i_data_sva; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire [10:0] FpMantRNE_17U_11U_else_ac_int_cctor_sva; + wire [11:0] nl_FpMantRNE_17U_11U_else_ac_int_cctor_sva; + wire nand_tmp; + wire mux_tmp; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire FpMantRNE_17U_11U_else_and_svs_mx0w0; + wire FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1; + wire [4:0] libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1; + wire FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1; + wire FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1; + wire[0:0] nor_9_nl; + wire[0:0] nand_8_nl; + wire[9:0] mux_4_nl; + wire[0:0] and_53_nl; + wire[4:0] and_nl; + wire[4:0] mux_3_nl; + wire[4:0] FpFractionToFloat_16U_6U_10U_nor_1_nl; + wire[4:0] FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl; + wire[5:0] nl_FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl; + wire[0:0] FpFractionToFloat_16U_6U_10U_if_else_else_not_2_nl; + wire[0:0] and_52_nl; + wire[0:0] not_41_nl; + wire[5:0] FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl; + wire[6:0] nl_FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl; + wire[4:0] FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl; + wire[5:0] nl_FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl; + wire[0:0] FpFractionToFloat_16U_6U_10U_if_else_mux_1_nl; +// Interconnect Declarations for Component Instantiations + wire [6:0] nl_FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg_s; + assign nl_FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg_s = conv_u2u_5_6(libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1) + + 6'b1; + wire [16:0] nl_HLS_uint16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_uint16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d = {2'b0 , chn_o_rsci_d_14_10 + , chn_o_rsci_d_9_0}; + UINT16_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd16), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd17)) FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg ( + .a(chn_a_rsci_d_mxwt), + .s(nl_FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg_s[5:0]), + .z(FpMantRNE_17U_11U_i_data_sva) + ); + UINT16_TO_FP17_leading_sign_16_0 leading_sign_16_0_rg ( + .mantissa(chn_a_rsci_d_mxwt), + .rtn(libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1) + ); + HLS_uint16_to_fp17_core_chn_a_rsci HLS_uint16_to_fp17_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_uint16_to_fp17_core_chn_o_rsci HLS_uint16_to_fp17_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_uint16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_uint16_to_fp17_core_staller HLS_uint16_to_fp17_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_uint16_to_fp17_core_core_fsm HLS_uint16_to_fp17_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign nor_9_nl = ~(FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1 | (~ FpMantRNE_17U_11U_else_and_svs_mx1)); + assign nand_8_nl = ~(FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1 & FpMantRNE_17U_11U_else_and_svs_mx1); + assign mux_tmp = MUX_s_1_2_2((nand_8_nl), (nor_9_nl), FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1); + assign nand_tmp = ~((~(FpMantRNE_17U_11U_else_and_svs_mx1 & (~ FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1))) + & FpFractionToFloat_16U_6U_10U_unequal_tmp); + assign FpMantRNE_17U_11U_else_and_svs_mx0w0 = FpMantRNE_17U_11U_else_carry_sva + & (FpMantRNE_17U_11U_i_data_sva[16:6]==11'b11111111111); + assign FpMantRNE_17U_11U_else_and_svs_mx1 = MUX_s_1_2_2(FpMantRNE_17U_11U_else_and_svs_mx0w0, + FpMantRNE_17U_11U_else_and_svs, and_dcpl_22); + assign nl_FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl = ({1'b1 , libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1}) + + 6'b1; + assign FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl = nl_FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl[5:0]; + assign FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1 = readslicef_6_1_5((FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl)); + assign nl_FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl = ({1'b1 , (libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1[4:1])}) + + 5'b1; + assign FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl = nl_FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl[4:0]; + assign FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1 = readslicef_5_1_4((FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl)); + assign nl_FpMantRNE_17U_11U_else_ac_int_cctor_sva = (FpMantRNE_17U_11U_i_data_sva[16:6]) + + conv_u2u_1_11(FpMantRNE_17U_11U_else_carry_sva); + assign FpMantRNE_17U_11U_else_ac_int_cctor_sva = nl_FpMantRNE_17U_11U_else_ac_int_cctor_sva[10:0]; + assign FpMantRNE_17U_11U_else_carry_sva = (FpMantRNE_17U_11U_i_data_sva[5]) & ((FpMantRNE_17U_11U_i_data_sva[0]) + | (FpMantRNE_17U_11U_i_data_sva[1]) | (FpMantRNE_17U_11U_i_data_sva[2]) | (FpMantRNE_17U_11U_i_data_sva[3]) + | (FpMantRNE_17U_11U_i_data_sva[4]) | (FpMantRNE_17U_11U_i_data_sva[6])); + assign FpFractionToFloat_16U_6U_10U_unequal_tmp = (chn_a_rsci_d_mxwt!=16'b0000000000000000); + assign FpFractionToFloat_16U_6U_10U_if_else_mux_1_nl = MUX_s_1_2_2(FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1, + FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1, FpMantRNE_17U_11U_else_and_svs_mx1); + assign FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1 = ~((FpFractionToFloat_16U_6U_10U_if_else_mux_1_nl) + & FpFractionToFloat_16U_6U_10U_unequal_tmp); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign or_dcpl_1 = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign and_dcpl_7 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_dcpl_22 = (chn_a_rsci_d_mxwt==16'b0000000000000000); + assign or_tmp_7 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_a_rsci_oswt_unreg = or_tmp_7; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= or_tmp_7; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & (~(or_dcpl_1 | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_9_0 <= (mux_4_nl) & (signext_10_1(~ mux_tmp)) & ({{9{FpFractionToFloat_16U_6U_10U_unequal_tmp}}, + FpFractionToFloat_16U_6U_10U_unequal_tmp}) & (signext_10_1(~ FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_14_10 <= 5'b0; + end + else if ( core_wen & (~(or_dcpl_1 | (fsm_output[0]))) ) begin + chn_o_rsci_d_14_10 <= ~(MUX_v_5_2_2((and_nl), 5'b11111, FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (or_tmp_7 | and_dcpl_7) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_7; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_17U_11U_else_and_svs <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_22 | or_dcpl_1 | (fsm_output[0]))) ) begin + FpMantRNE_17U_11U_else_and_svs <= FpMantRNE_17U_11U_else_and_svs_mx0w0; + end + end + assign and_53_nl = FpMantRNE_17U_11U_else_and_svs_mx1 & (~ mux_tmp); + assign mux_4_nl = MUX_v_10_2_2((FpMantRNE_17U_11U_else_ac_int_cctor_sva[9:0]), + (FpMantRNE_17U_11U_else_ac_int_cctor_sva[10:1]), and_53_nl); + assign nl_FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl = (~ libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1) + + 5'b11111; + assign FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl = nl_FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl[4:0]; + assign FpFractionToFloat_16U_6U_10U_if_else_else_not_2_nl = ~ FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1; + assign FpFractionToFloat_16U_6U_10U_nor_1_nl = ~(MUX_v_5_2_2((FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl), + 5'b11111, (FpFractionToFloat_16U_6U_10U_if_else_else_not_2_nl))); + assign and_52_nl = FpMantRNE_17U_11U_else_and_svs_mx1 & (~ nand_tmp); + assign mux_3_nl = MUX_v_5_2_2((FpFractionToFloat_16U_6U_10U_nor_1_nl), libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1, + and_52_nl); + assign not_41_nl = ~ nand_tmp; + assign and_nl = MUX_v_5_2_2(5'b00000, (mux_3_nl), (not_41_nl)); + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [9:0] signext_10_1; + input [0:0] vector; + begin + signext_10_1= {{9{vector[0]}}, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [5:0] conv_u2u_5_6 ; + input [4:0] vector ; + begin + conv_u2u_5_6 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17 +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + UINT16_TO_FP17_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + UINT16_TO_FP17_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_uint16_to_fp17_core HLS_uint16_to_fp17_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/HLS_uint16_to_fp17.v.vcp b/designs/src/NVDLA/vmod/vlibs/HLS_uint16_to_fp17.v.vcp new file mode 100644 index 0000000..9f99161 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/HLS_uint16_to_fp17.v.vcp @@ -0,0 +1,935 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: HLS_uint16_to_fp17.v +module UINT16_TO_FP17_mgc_in_wire_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + output [width-1:0] d; + output lz; + input vz; + input [width-1:0] z; + wire vd; + wire [width-1:0] d; + wire lz; + assign d = z; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/UINT16_TO_FP17_mgc_out_stdreg_wait_v1.v +//------------------------------------------------------------------------------ +// Catapult Synthesis - Sample I/O Port Library +// +// Copyright (c) 2003-2015 Mentor Graphics Corp. +// All Rights Reserved +// +// This document may be used and distributed without restriction provided that +// this copyright statement is not removed from the file and that any derivative +// work contains this copyright notice. +// +// The design information contained in this file is intended to be an example +// of the functionality which the end user may study in preparation for creating +// their own custom interfaces. This design does not necessarily present a +// complete implementation of the named protocol or standard. +// +//------------------------------------------------------------------------------ +module UINT16_TO_FP17_mgc_out_stdreg_wait_v1 (ld, vd, d, lz, vz, z); + parameter integer rscid = 1; + parameter integer width = 8; + input ld; + output vd; + input [width-1:0] d; + output lz; + input vz; + output [width-1:0] z; + wire vd; + wire lz; + wire [width-1:0] z; + assign z = d; + assign lz = ld; + assign vd = vz; +endmodule +//------> /home/tools/calypto/catapult-10.0-264918/Mgc_home/pkgs/siflibs/mgc_shift_l_beh_v4.v +module UINT16_TO_FP17_mgc_shift_l_v4(a,s,z); + parameter width_a = 4; + parameter signd_a = 1; + parameter width_s = 2; + parameter width_z = 8; + input [width_a-1:0] a; + input [width_s-1:0] s; + output [width_z -1:0] z; + generate + if (signd_a) + begin: SIGNED + assign z = fshl_u(a,s,a[width_a-1]); + end + else + begin: UNSIGNED + assign z = fshl_u(a,s,1'b0); + end + endgenerate +//Shift-left - unsigned shift argument one bit more + function [width_z-1:0] fshl_u_1; + input [width_a :0] arg1; + input [width_s-1:0] arg2; + input sbit; + parameter olen = width_z; + parameter ilen = width_a+1; + parameter len = (ilen >= olen) ? ilen : olen; + reg [len-1:0] result; + reg [len-1:0] result_t; + begin + result_t = {(len){sbit}}; + result_t[ilen-1:0] = arg1; + result = result_t <<< arg2; + fshl_u_1 = result[olen-1:0]; + end + endfunction // fshl_u +//Shift-left - unsigned shift argument + function [width_z-1:0] fshl_u; + input [width_a-1:0] arg1; + input [width_s-1:0] arg2; + input sbit; + fshl_u = fshl_u_1({sbit,arg1} ,arg2, sbit); + endfunction // fshl_u +endmodule +//------> ../td_ccore_solutions/leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_0/rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-10-176 +// Generated date: Wed Nov 23 14:25:06 2016 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: UINT16_TO_FP17_leading_sign_16_0 +// ------------------------------------------------------------------ +module UINT16_TO_FP17_leading_sign_16_0 ( + mantissa, rtn +); + input [15:0] mantissa; + output [4:0] rtn; +// Interconnect Declarations + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1; + wire IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1; + wire c_h_1_2; + wire c_h_1_5; + wire c_h_1_6; + wire[3:0] IntLeadZero_16U_leading_sign_16_0_rtn_IntLeadZero_16U_leading_sign_16_0_rtn_and_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_and_55_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_and_53_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_and_60_nl; + wire[0:0] IntLeadZero_16U_leading_sign_16_0_rtn_not_nl; +// Interconnect Declarations for Component Instantiations + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2 = ~((mantissa[13:12]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1 = ~((mantissa[15:14]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1 = ~((mantissa[11:10]!=2'b00)); + assign c_h_1_2 = IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1 & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2; + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3 = (mantissa[9:8]==2'b00) + & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1; + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2 = ~((mantissa[5:4]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1 = ~((mantissa[7:6]!=2'b00)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1 = ~((mantissa[3:2]!=2'b00)); + assign c_h_1_5 = IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1 & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2; + assign c_h_1_6 = c_h_1_2 & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3; + assign IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4 = (mantissa[1:0]==2'b00) + & IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1 & c_h_1_5 & c_h_1_6; + assign IntLeadZero_16U_leading_sign_16_0_rtn_and_55_nl = c_h_1_2 & (c_h_1_5 | (~ + IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_18_3_sdt_3)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_and_53_nl = IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_1 + & (IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_14_2_sdt_1 | (~ IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_6_2_sdt_2)) + & (~((~(IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_1 & (IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_34_2_sdt_1 + | (~ IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_26_2_sdt_2)))) & c_h_1_6)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_and_60_nl = (~((mantissa[15]) | (~((mantissa[14:13]!=2'b01))))) + & (~(((mantissa[11]) | (~((mantissa[10:9]!=2'b01)))) & c_h_1_2)) & (~((~((~((mantissa[7]) + | (~((mantissa[6:5]!=2'b01))))) & (~(((mantissa[3]) | (~((mantissa[2:1]!=2'b01)))) + & c_h_1_5)))) & c_h_1_6)); + assign IntLeadZero_16U_leading_sign_16_0_rtn_not_nl = ~ IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4; + assign IntLeadZero_16U_leading_sign_16_0_rtn_IntLeadZero_16U_leading_sign_16_0_rtn_and_nl + = MUX_v_4_2_2(4'b0000, ({c_h_1_6 , (IntLeadZero_16U_leading_sign_16_0_rtn_and_55_nl) + , (IntLeadZero_16U_leading_sign_16_0_rtn_and_53_nl) , (IntLeadZero_16U_leading_sign_16_0_rtn_and_60_nl)}), + (IntLeadZero_16U_leading_sign_16_0_rtn_not_nl)); + assign rtn = {IntLeadZero_16U_leading_sign_16_0_rtn_wrs_c_44_4_sdt_4 , (IntLeadZero_16U_leading_sign_16_0_rtn_IntLeadZero_16U_leading_sign_16_0_rtn_and_nl)}; + function [3:0] MUX_v_4_2_2; + input [3:0] input_0; + input [3:0] input_1; + input [0:0] sel; + reg [3:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_4_2_2 = result; + end + endfunction +endmodule +//------> ./rtl.v +// ---------------------------------------------------------------------- +// HLS HDL: Verilog Netlister +// HLS Version: 10.0/264918 Production Release +// HLS Date: Mon Aug 8 13:35:54 PDT 2016 +// +// Generated by: ezhang@hk-sim-11-173 +// Generated date: Mon Jun 12 22:24:10 2017 +// ---------------------------------------------------------------------- +// +// ------------------------------------------------------------------ +// Design Unit: UINT16_TO_FP17_chn_o_rsci_unreg +// ------------------------------------------------------------------ +module UINT16_TO_FP17_chn_o_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: UINT16_TO_FP17_chn_a_rsci_unreg +// ------------------------------------------------------------------ +module UINT16_TO_FP17_chn_a_rsci_unreg ( + in_0, outsig +); + input in_0; + output outsig; +// Interconnect Declarations for Component Instantiations + assign outsig = in_0; +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_core_fsm +// FSM Module +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_core_fsm ( + nvdla_core_clk, nvdla_core_rstn, core_wen, fsm_output +); + input nvdla_core_clk; + input nvdla_core_rstn; + input core_wen; + output [1:0] fsm_output; + reg [1:0] fsm_output; +// FSM State Type Declaration for HLS_uint16_to_fp17_core_core_fsm_1 + parameter + core_rlp_C_0 = 1'd0, + main_C_0 = 1'd1; + reg [0:0] state_var; + reg [0:0] state_var_NS; +// Interconnect Declarations for Component Instantiations + always @(*) + begin : HLS_uint16_to_fp17_core_core_fsm_1 + case (state_var) + main_C_0 : begin + fsm_output = 2'b10; + state_var_NS = main_C_0; + end +// core_rlp_C_0 + default : begin + fsm_output = 2'b1; + state_var_NS = main_C_0; + end + endcase + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + state_var <= core_rlp_C_0; + end + else if ( core_wen ) begin + state_var <= state_var_NS; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_staller +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_staller ( + nvdla_core_clk, nvdla_core_rstn, core_wen, chn_a_rsci_wen_comp, core_wten, chn_o_rsci_wen_comp +); + input nvdla_core_clk; + input nvdla_core_rstn; + output core_wen; + input chn_a_rsci_wen_comp; + output core_wten; + reg core_wten; + input chn_o_rsci_wen_comp; +// Interconnect Declarations for Component Instantiations + assign core_wen = chn_a_rsci_wen_comp & chn_o_rsci_wen_comp; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + core_wten <= 1'b0; + end + else begin + core_wten <= ~ core_wen; + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_biwt, chn_o_rsci_bdwt +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_biwt; + input chn_o_rsci_bdwt; +// Interconnect Declarations + reg chn_o_rsci_bcwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_bawt = chn_o_rsci_biwt | chn_o_rsci_bcwt; + assign chn_o_rsci_wen_comp = (~ chn_o_rsci_oswt) | chn_o_rsci_bawt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_bcwt <= 1'b0; + end + else begin + chn_o_rsci_bcwt <= ~((~(chn_o_rsci_bcwt | chn_o_rsci_biwt)) | chn_o_rsci_bdwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsci_oswt, core_wen, core_wten, chn_o_rsci_iswt0, + chn_o_rsci_ld_core_psct, chn_o_rsci_biwt, chn_o_rsci_bdwt, chn_o_rsci_ld_core_sct, + chn_o_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + input chn_o_rsci_ld_core_psct; + output chn_o_rsci_biwt; + output chn_o_rsci_bdwt; + output chn_o_rsci_ld_core_sct; + input chn_o_rsci_vd; +// Interconnect Declarations + wire chn_o_rsci_ogwt; + wire chn_o_rsci_pdswt0; + reg chn_o_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_o_rsci_pdswt0 = (~ core_wten) & chn_o_rsci_iswt0; + assign chn_o_rsci_biwt = chn_o_rsci_ogwt & chn_o_rsci_vd; + assign chn_o_rsci_ogwt = chn_o_rsci_pdswt0 | chn_o_rsci_icwt; + assign chn_o_rsci_bdwt = chn_o_rsci_oswt & core_wen; + assign chn_o_rsci_ld_core_sct = chn_o_rsci_ld_core_psct & chn_o_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_icwt <= 1'b0; + end + else begin + chn_o_rsci_icwt <= ~((~(chn_o_rsci_icwt | chn_o_rsci_pdswt0)) | chn_o_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, chn_a_rsci_bawt, chn_a_rsci_wen_comp, + chn_a_rsci_d_mxwt, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + output [15:0] chn_a_rsci_d_mxwt; + input chn_a_rsci_biwt; + input chn_a_rsci_bdwt; + input [15:0] chn_a_rsci_d; +// Interconnect Declarations + reg chn_a_rsci_bcwt; + reg [15:0] chn_a_rsci_d_bfwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_bawt = chn_a_rsci_biwt | chn_a_rsci_bcwt; + assign chn_a_rsci_wen_comp = (~ chn_a_rsci_oswt) | chn_a_rsci_bawt; + assign chn_a_rsci_d_mxwt = MUX_v_16_2_2(chn_a_rsci_d, chn_a_rsci_d_bfwt, chn_a_rsci_bcwt); + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_bcwt <= 1'b0; + chn_a_rsci_d_bfwt <= 16'b0; + end + else begin + chn_a_rsci_bcwt <= ~((~(chn_a_rsci_bcwt | chn_a_rsci_biwt)) | chn_a_rsci_bdwt); + chn_a_rsci_d_bfwt <= chn_a_rsci_d_mxwt; + end + end + function [15:0] MUX_v_16_2_2; + input [15:0] input_0; + input [15:0] input_1; + input [0:0] sel; + reg [15:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_16_2_2 = result; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsci_oswt, core_wen, chn_a_rsci_iswt0, chn_a_rsci_ld_core_psct, + core_wten, chn_a_rsci_biwt, chn_a_rsci_bdwt, chn_a_rsci_ld_core_sct, chn_a_rsci_vd +); + input nvdla_core_clk; + input nvdla_core_rstn; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + input chn_a_rsci_ld_core_psct; + input core_wten; + output chn_a_rsci_biwt; + output chn_a_rsci_bdwt; + output chn_a_rsci_ld_core_sct; + input chn_a_rsci_vd; +// Interconnect Declarations + wire chn_a_rsci_ogwt; + wire chn_a_rsci_pdswt0; + reg chn_a_rsci_icwt; +// Interconnect Declarations for Component Instantiations + assign chn_a_rsci_pdswt0 = (~ core_wten) & chn_a_rsci_iswt0; + assign chn_a_rsci_biwt = chn_a_rsci_ogwt & chn_a_rsci_vd; + assign chn_a_rsci_ogwt = chn_a_rsci_pdswt0 | chn_a_rsci_icwt; + assign chn_a_rsci_bdwt = chn_a_rsci_oswt & core_wen; + assign chn_a_rsci_ld_core_sct = chn_a_rsci_ld_core_psct & chn_a_rsci_ogwt; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_icwt <= 1'b0; + end + else begin + chn_a_rsci_icwt <= ~((~(chn_a_rsci_icwt | chn_a_rsci_pdswt0)) | chn_a_rsci_biwt); + end + end +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_o_rsci +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_o_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_o_rsc_z, chn_o_rsc_vz, chn_o_rsc_lz, chn_o_rsci_oswt, + core_wen, core_wten, chn_o_rsci_iswt0, chn_o_rsci_bawt, chn_o_rsci_wen_comp, + chn_o_rsci_ld_core_psct, chn_o_rsci_d +); + input nvdla_core_clk; + input nvdla_core_rstn; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_o_rsci_oswt; + input core_wen; + input core_wten; + input chn_o_rsci_iswt0; + output chn_o_rsci_bawt; + output chn_o_rsci_wen_comp; + input chn_o_rsci_ld_core_psct; + input [16:0] chn_o_rsci_d; +// Interconnect Declarations + wire chn_o_rsci_biwt; + wire chn_o_rsci_bdwt; + wire chn_o_rsci_ld_core_sct; + wire chn_o_rsci_vd; +// Interconnect Declarations for Component Instantiations + wire [16:0] nl_chn_o_rsci_d; + assign nl_chn_o_rsci_d = {2'b0 , (chn_o_rsci_d[14:0])}; + UINT16_TO_FP17_mgc_out_stdreg_wait_v1 #(.rscid(32'sd2), + .width(32'sd17)) chn_o_rsci ( + .ld(chn_o_rsci_ld_core_sct), + .vd(chn_o_rsci_vd), + .d(nl_chn_o_rsci_d[16:0]), + .lz(chn_o_rsc_lz), + .vz(chn_o_rsc_vz), + .z(chn_o_rsc_z) + ); + HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(chn_o_rsci_iswt0), + .chn_o_rsci_ld_core_psct(chn_o_rsci_ld_core_psct), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt), + .chn_o_rsci_ld_core_sct(chn_o_rsci_ld_core_sct), + .chn_o_rsci_vd(chn_o_rsci_vd) + ); + HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp HLS_uint16_to_fp17_core_chn_o_rsci_chn_o_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_biwt(chn_o_rsci_biwt), + .chn_o_rsci_bdwt(chn_o_rsci_bdwt) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core_chn_a_rsci +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core_chn_a_rsci ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_a_rsci_oswt, + core_wen, chn_a_rsci_iswt0, chn_a_rsci_bawt, chn_a_rsci_wen_comp, chn_a_rsci_ld_core_psct, + chn_a_rsci_d_mxwt, core_wten +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + input chn_a_rsci_oswt; + input core_wen; + input chn_a_rsci_iswt0; + output chn_a_rsci_bawt; + output chn_a_rsci_wen_comp; + input chn_a_rsci_ld_core_psct; + output [15:0] chn_a_rsci_d_mxwt; + input core_wten; +// Interconnect Declarations + wire chn_a_rsci_biwt; + wire chn_a_rsci_bdwt; + wire chn_a_rsci_ld_core_sct; + wire chn_a_rsci_vd; + wire [15:0] chn_a_rsci_d; +// Interconnect Declarations for Component Instantiations + UINT16_TO_FP17_mgc_in_wire_wait_v1 #(.rscid(32'sd1), + .width(32'sd16)) chn_a_rsci ( + .ld(chn_a_rsci_ld_core_sct), + .vd(chn_a_rsci_vd), + .d(chn_a_rsci_d), + .lz(chn_a_rsc_lz), + .vz(chn_a_rsc_vz), + .z(chn_a_rsc_z) + ); + HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_ctrl_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .core_wten(core_wten), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_ld_core_sct(chn_a_rsci_ld_core_sct), + .chn_a_rsci_vd(chn_a_rsci_vd) + ); + HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp HLS_uint16_to_fp17_core_chn_a_rsci_chn_a_wait_dp_inst + ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .chn_a_rsci_biwt(chn_a_rsci_biwt), + .chn_a_rsci_bdwt(chn_a_rsci_bdwt), + .chn_a_rsci_d(chn_a_rsci_d) + ); +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17_core +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17_core ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz, chn_a_rsci_oswt, chn_a_rsci_oswt_unreg, chn_o_rsci_oswt, + chn_o_rsci_oswt_unreg +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; + input chn_a_rsci_oswt; + output chn_a_rsci_oswt_unreg; + input chn_o_rsci_oswt; + output chn_o_rsci_oswt_unreg; +// Interconnect Declarations + wire core_wen; + reg chn_a_rsci_iswt0; + wire chn_a_rsci_bawt; + wire chn_a_rsci_wen_comp; + reg chn_a_rsci_ld_core_psct; + wire [15:0] chn_a_rsci_d_mxwt; + wire core_wten; + wire chn_o_rsci_bawt; + wire chn_o_rsci_wen_comp; + reg [4:0] chn_o_rsci_d_14_10; + reg [9:0] chn_o_rsci_d_9_0; + wire [1:0] fsm_output; + wire and_dcpl_2; + wire or_dcpl_1; + wire and_dcpl_7; + wire and_dcpl_22; + wire or_tmp_7; + reg FpMantRNE_17U_11U_else_and_svs; + wire and_4_mdf; + wire FpMantRNE_17U_11U_else_and_svs_mx1; + wire FpFractionToFloat_16U_6U_10U_unequal_tmp; + wire FpMantRNE_17U_11U_else_carry_sva; + wire [16:0] FpMantRNE_17U_11U_i_data_sva; + reg reg_chn_o_rsci_iswt0_cse; + reg reg_chn_o_rsci_ld_core_psct_cse; + wire or_cse; + wire [10:0] FpMantRNE_17U_11U_else_ac_int_cctor_sva; + wire [11:0] nl_FpMantRNE_17U_11U_else_ac_int_cctor_sva; + wire nand_tmp; + wire mux_tmp; + wire chn_a_rsci_ld_core_psct_mx0c0; + wire FpMantRNE_17U_11U_else_and_svs_mx0w0; + wire FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1; + wire [4:0] libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1; + wire FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1; + wire FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1; + wire[0:0] nor_9_nl; + wire[0:0] nand_8_nl; + wire[9:0] mux_4_nl; + wire[0:0] and_53_nl; + wire[4:0] and_nl; + wire[4:0] mux_3_nl; + wire[4:0] FpFractionToFloat_16U_6U_10U_nor_1_nl; + wire[4:0] FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl; + wire[5:0] nl_FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl; + wire[0:0] FpFractionToFloat_16U_6U_10U_if_else_else_not_2_nl; + wire[0:0] and_52_nl; + wire[0:0] not_41_nl; + wire[5:0] FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl; + wire[6:0] nl_FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl; + wire[4:0] FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl; + wire[5:0] nl_FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl; + wire[0:0] FpFractionToFloat_16U_6U_10U_if_else_mux_1_nl; +// Interconnect Declarations for Component Instantiations + wire [6:0] nl_FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg_s; + assign nl_FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg_s = conv_u2u_5_6(libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1) + + 6'b1; + wire [16:0] nl_HLS_uint16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d; + assign nl_HLS_uint16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d = {2'b0 , chn_o_rsci_d_14_10 + , chn_o_rsci_d_9_0}; + UINT16_TO_FP17_mgc_shift_l_v4 #(.width_a(32'sd16), + .signd_a(32'sd0), + .width_s(32'sd6), + .width_z(32'sd17)) FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg ( + .a(chn_a_rsci_d_mxwt), + .s(nl_FpFractionToFloat_16U_6U_10U_if_shifted_frac_p1_lshift_rg_s[5:0]), + .z(FpMantRNE_17U_11U_i_data_sva) + ); + UINT16_TO_FP17_leading_sign_16_0 leading_sign_16_0_rg ( + .mantissa(chn_a_rsci_d_mxwt), + .rtn(libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1) + ); + HLS_uint16_to_fp17_core_chn_a_rsci HLS_uint16_to_fp17_core_chn_a_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .core_wen(core_wen), + .chn_a_rsci_iswt0(chn_a_rsci_iswt0), + .chn_a_rsci_bawt(chn_a_rsci_bawt), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .chn_a_rsci_ld_core_psct(chn_a_rsci_ld_core_psct), + .chn_a_rsci_d_mxwt(chn_a_rsci_d_mxwt), + .core_wten(core_wten) + ); + HLS_uint16_to_fp17_core_chn_o_rsci HLS_uint16_to_fp17_core_chn_o_rsci_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .core_wen(core_wen), + .core_wten(core_wten), + .chn_o_rsci_iswt0(reg_chn_o_rsci_iswt0_cse), + .chn_o_rsci_bawt(chn_o_rsci_bawt), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp), + .chn_o_rsci_ld_core_psct(reg_chn_o_rsci_ld_core_psct_cse), + .chn_o_rsci_d(nl_HLS_uint16_to_fp17_core_chn_o_rsci_inst_chn_o_rsci_d[16:0]) + ); + HLS_uint16_to_fp17_core_staller HLS_uint16_to_fp17_core_staller_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .chn_a_rsci_wen_comp(chn_a_rsci_wen_comp), + .core_wten(core_wten), + .chn_o_rsci_wen_comp(chn_o_rsci_wen_comp) + ); + HLS_uint16_to_fp17_core_core_fsm HLS_uint16_to_fp17_core_core_fsm_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .core_wen(core_wen), + .fsm_output(fsm_output) + ); + assign nor_9_nl = ~(FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1 | (~ FpMantRNE_17U_11U_else_and_svs_mx1)); + assign nand_8_nl = ~(FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1 & FpMantRNE_17U_11U_else_and_svs_mx1); + assign mux_tmp = MUX_s_1_2_2((nand_8_nl), (nor_9_nl), FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1); + assign nand_tmp = ~((~(FpMantRNE_17U_11U_else_and_svs_mx1 & (~ FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1))) + & FpFractionToFloat_16U_6U_10U_unequal_tmp); + assign FpMantRNE_17U_11U_else_and_svs_mx0w0 = FpMantRNE_17U_11U_else_carry_sva + & (FpMantRNE_17U_11U_i_data_sva[16:6]==11'b11111111111); + assign FpMantRNE_17U_11U_else_and_svs_mx1 = MUX_s_1_2_2(FpMantRNE_17U_11U_else_and_svs_mx0w0, + FpMantRNE_17U_11U_else_and_svs, and_dcpl_22); + assign nl_FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl = ({1'b1 , libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1}) + + 6'b1; + assign FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl = nl_FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl[5:0]; + assign FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1 = readslicef_6_1_5((FpFractionToFloat_16U_6U_10U_if_else_if_acc_nl)); + assign nl_FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl = ({1'b1 , (libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1[4:1])}) + + 5'b1; + assign FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl = nl_FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl[4:0]; + assign FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1 = readslicef_5_1_4((FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_nl)); + assign nl_FpMantRNE_17U_11U_else_ac_int_cctor_sva = (FpMantRNE_17U_11U_i_data_sva[16:6]) + + conv_u2u_1_11(FpMantRNE_17U_11U_else_carry_sva); + assign FpMantRNE_17U_11U_else_ac_int_cctor_sva = nl_FpMantRNE_17U_11U_else_ac_int_cctor_sva[10:0]; + assign FpMantRNE_17U_11U_else_carry_sva = (FpMantRNE_17U_11U_i_data_sva[5]) & ((FpMantRNE_17U_11U_i_data_sva[0]) + | (FpMantRNE_17U_11U_i_data_sva[1]) | (FpMantRNE_17U_11U_i_data_sva[2]) | (FpMantRNE_17U_11U_i_data_sva[3]) + | (FpMantRNE_17U_11U_i_data_sva[4]) | (FpMantRNE_17U_11U_i_data_sva[6])); + assign FpFractionToFloat_16U_6U_10U_unequal_tmp = (chn_a_rsci_d_mxwt!=16'b0000000000000000); + assign FpFractionToFloat_16U_6U_10U_if_else_mux_1_nl = MUX_s_1_2_2(FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1, + FpFractionToFloat_16U_6U_10U_if_else_if_acc_itm_5_1, FpMantRNE_17U_11U_else_and_svs_mx1); + assign FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1 = ~((FpFractionToFloat_16U_6U_10U_if_else_mux_1_nl) + & FpFractionToFloat_16U_6U_10U_unequal_tmp); + assign or_cse = chn_o_rsci_bawt | (~ reg_chn_o_rsci_ld_core_psct_cse); + assign and_4_mdf = chn_a_rsci_bawt & or_cse; + assign and_dcpl_2 = chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse; + assign or_dcpl_1 = ~((~((~ chn_o_rsci_bawt) & reg_chn_o_rsci_ld_core_psct_cse)) + & chn_a_rsci_bawt); + assign and_dcpl_7 = and_dcpl_2 & (~ chn_a_rsci_bawt); + assign and_dcpl_22 = (chn_a_rsci_d_mxwt==16'b0000000000000000); + assign or_tmp_7 = or_cse & chn_a_rsci_bawt & (fsm_output[1]); + assign chn_a_rsci_ld_core_psct_mx0c0 = and_4_mdf | (fsm_output[0]); + assign chn_a_rsci_oswt_unreg = or_tmp_7; + assign chn_o_rsci_oswt_unreg = and_dcpl_2; + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_iswt0 <= 1'b0; + reg_chn_o_rsci_iswt0_cse <= 1'b0; + end + else if ( core_wen ) begin + chn_a_rsci_iswt0 <= ~((~ and_4_mdf) & (fsm_output[1])); + reg_chn_o_rsci_iswt0_cse <= or_tmp_7; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_a_rsci_ld_core_psct <= 1'b0; + end + else if ( core_wen & chn_a_rsci_ld_core_psct_mx0c0 ) begin + chn_a_rsci_ld_core_psct <= chn_a_rsci_ld_core_psct_mx0c0; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_9_0 <= 10'b0; + end + else if ( core_wen & (~(or_dcpl_1 | ((~(chn_o_rsci_bawt & reg_chn_o_rsci_ld_core_psct_cse + & chn_a_rsci_bawt)) & (fsm_output[0])))) ) begin + chn_o_rsci_d_9_0 <= (mux_4_nl) & (signext_10_1(~ mux_tmp)) & ({{9{FpFractionToFloat_16U_6U_10U_unequal_tmp}}, + FpFractionToFloat_16U_6U_10U_unequal_tmp}) & (signext_10_1(~ FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + chn_o_rsci_d_14_10 <= 5'b0; + end + else if ( core_wen & (~(or_dcpl_1 | (fsm_output[0]))) ) begin + chn_o_rsci_d_14_10 <= ~(MUX_v_5_2_2((and_nl), 5'b11111, FpFractionToFloat_16U_6U_10U_is_zero_lpi_1_dfm_1)); + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + reg_chn_o_rsci_ld_core_psct_cse <= 1'b0; + end + else if ( core_wen & (or_tmp_7 | and_dcpl_7) ) begin + reg_chn_o_rsci_ld_core_psct_cse <= ~ and_dcpl_7; + end + end + always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if ( ~ nvdla_core_rstn ) begin + FpMantRNE_17U_11U_else_and_svs <= 1'b0; + end + else if ( core_wen & (~(and_dcpl_22 | or_dcpl_1 | (fsm_output[0]))) ) begin + FpMantRNE_17U_11U_else_and_svs <= FpMantRNE_17U_11U_else_and_svs_mx0w0; + end + end + assign and_53_nl = FpMantRNE_17U_11U_else_and_svs_mx1 & (~ mux_tmp); + assign mux_4_nl = MUX_v_10_2_2((FpMantRNE_17U_11U_else_ac_int_cctor_sva[9:0]), + (FpMantRNE_17U_11U_else_ac_int_cctor_sva[10:1]), and_53_nl); + assign nl_FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl = (~ libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1) + + 5'b11111; + assign FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl = nl_FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl[4:0]; + assign FpFractionToFloat_16U_6U_10U_if_else_else_not_2_nl = ~ FpFractionToFloat_16U_6U_10U_if_else_else_if_acc_itm_4_1; + assign FpFractionToFloat_16U_6U_10U_nor_1_nl = ~(MUX_v_5_2_2((FpFractionToFloat_16U_6U_10U_if_else_else_else_acc_nl), + 5'b11111, (FpFractionToFloat_16U_6U_10U_if_else_else_not_2_nl))); + assign and_52_nl = FpMantRNE_17U_11U_else_and_svs_mx1 & (~ nand_tmp); + assign mux_3_nl = MUX_v_5_2_2((FpFractionToFloat_16U_6U_10U_nor_1_nl), libraries_leading_sign_16_0_584ce9c19228fa5400845cefe3e6770649bb_1, + and_52_nl); + assign not_41_nl = ~ nand_tmp; + assign and_nl = MUX_v_5_2_2(5'b00000, (mux_3_nl), (not_41_nl)); + function [0:0] MUX_s_1_2_2; + input [0:0] input_0; + input [0:0] input_1; + input [0:0] sel; + reg [0:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_s_1_2_2 = result; + end + endfunction + function [9:0] MUX_v_10_2_2; + input [9:0] input_0; + input [9:0] input_1; + input [0:0] sel; + reg [9:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_10_2_2 = result; + end + endfunction + function [4:0] MUX_v_5_2_2; + input [4:0] input_0; + input [4:0] input_1; + input [0:0] sel; + reg [4:0] result; + begin + case (sel) + 1'b0 : begin + result = input_0; + end + default : begin + result = input_1; + end + endcase + MUX_v_5_2_2 = result; + end + endfunction + function [0:0] readslicef_5_1_4; + input [4:0] vector; + reg [4:0] tmp; + begin + tmp = vector >> 4; + readslicef_5_1_4 = tmp[0:0]; + end + endfunction + function [0:0] readslicef_6_1_5; + input [5:0] vector; + reg [5:0] tmp; + begin + tmp = vector >> 5; + readslicef_6_1_5 = tmp[0:0]; + end + endfunction + function [9:0] signext_10_1; + input [0:0] vector; + begin + signext_10_1= {{9{vector[0]}}, vector}; + end + endfunction + function [10:0] conv_u2u_1_11 ; + input [0:0] vector ; + begin + conv_u2u_1_11 = {{10{1'b0}}, vector}; + end + endfunction + function [5:0] conv_u2u_5_6 ; + input [4:0] vector ; + begin + conv_u2u_5_6 = {1'b0, vector}; + end + endfunction +endmodule +// ------------------------------------------------------------------ +// Design Unit: HLS_uint16_to_fp17 +// ------------------------------------------------------------------ +module HLS_uint16_to_fp17 ( + nvdla_core_clk, nvdla_core_rstn, chn_a_rsc_z, chn_a_rsc_vz, chn_a_rsc_lz, chn_o_rsc_z, + chn_o_rsc_vz, chn_o_rsc_lz +); + input nvdla_core_clk; + input nvdla_core_rstn; + input [15:0] chn_a_rsc_z; + input chn_a_rsc_vz; + output chn_a_rsc_lz; + output [16:0] chn_o_rsc_z; + input chn_o_rsc_vz; + output chn_o_rsc_lz; +// Interconnect Declarations + wire chn_a_rsci_oswt; + wire chn_a_rsci_oswt_unreg; + wire chn_o_rsci_oswt; + wire chn_o_rsci_oswt_unreg; +// Interconnect Declarations for Component Instantiations + UINT16_TO_FP17_chn_a_rsci_unreg chn_a_rsci_unreg_inst ( + .in_0(chn_a_rsci_oswt_unreg), + .outsig(chn_a_rsci_oswt) + ); + UINT16_TO_FP17_chn_o_rsci_unreg chn_o_rsci_unreg_inst ( + .in_0(chn_o_rsci_oswt_unreg), + .outsig(chn_o_rsci_oswt) + ); + HLS_uint16_to_fp17_core HLS_uint16_to_fp17_core_inst ( + .nvdla_core_clk(nvdla_core_clk), + .nvdla_core_rstn(nvdla_core_rstn), + .chn_a_rsc_z(chn_a_rsc_z), + .chn_a_rsc_vz(chn_a_rsc_vz), + .chn_a_rsc_lz(chn_a_rsc_lz), + .chn_o_rsc_z(chn_o_rsc_z), + .chn_o_rsc_vz(chn_o_rsc_vz), + .chn_o_rsc_lz(chn_o_rsc_lz), + .chn_a_rsci_oswt(chn_a_rsci_oswt), + .chn_a_rsci_oswt_unreg(chn_a_rsci_oswt_unreg), + .chn_o_rsci_oswt(chn_o_rsci_oswt), + .chn_o_rsci_oswt_unreg(chn_o_rsci_oswt_unreg) + ); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/LNQD1PO4.v b/designs/src/NVDLA/vmod/vlibs/LNQD1PO4.v new file mode 100644 index 0000000..baa43ad --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/LNQD1PO4.v @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: LNQD1PO4.v +module LNQD1PO4 ( + D + ,EN + ,Q + ); +input D ; +input EN ; +output Q ; +reg Q; +always @(negedge EN) + Q <= D; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/LNQD1PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/LNQD1PO4.v.vcp new file mode 100644 index 0000000..baa43ad --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/LNQD1PO4.v.vcp @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: LNQD1PO4.v +module LNQD1PO4 ( + D + ,EN + ,Q + ); +input D ; +input EN ; +output Q ; +reg Q; +always @(negedge EN) + Q <= D; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/MUX2D4.v b/designs/src/NVDLA/vmod/vlibs/MUX2D4.v new file mode 100644 index 0000000..af53e92 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/MUX2D4.v @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: MUX2D4.v +module MUX2D4 ( + I0 + ,I1 + ,S + ,Z + ); +input I0 ; +input I1 ; +input S ; +output Z ; +assign Z = S ? I1 : I0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/MUX2D4.v.vcp b/designs/src/NVDLA/vmod/vlibs/MUX2D4.v.vcp new file mode 100644 index 0000000..af53e92 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/MUX2D4.v.vcp @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: MUX2D4.v +module MUX2D4 ( + I0 + ,I1 + ,S + ,Z + ); +input I0 ; +input I1 ; +input S ; +output Z ; +assign Z = S ? I1 : I0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/MUX2HDD2.v b/designs/src/NVDLA/vmod/vlibs/MUX2HDD2.v new file mode 100644 index 0000000..b059567 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/MUX2HDD2.v @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: MUX2HDD2.v +module MUX2HDD2 ( + I0 + ,I1 + ,S + ,Z + ); +input I0 ; +input I1 ; +input S ; +output Z ; +assign Z = S ? I1 : I0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/MUX2HDD2.v.vcp b/designs/src/NVDLA/vmod/vlibs/MUX2HDD2.v.vcp new file mode 100644 index 0000000..b059567 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/MUX2HDD2.v.vcp @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: MUX2HDD2.v +module MUX2HDD2 ( + I0 + ,I1 + ,S + ,Z + ); +input I0 ; +input I1 ; +input S ; +output Z ; +assign Z = S ? I1 : I0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_BUFFER.v b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_BUFFER.v new file mode 100644 index 0000000..20c4969 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_BUFFER.v @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_BUFFER.v +module NV_BLKBOX_BUFFER ( + Y + ,A + ); +output Y ; +input A ; +assign Y = A; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_BUFFER.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_BUFFER.v.vcp new file mode 100644 index 0000000..20c4969 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_BUFFER.v.vcp @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_BUFFER.v +module NV_BLKBOX_BUFFER ( + Y + ,A + ); +output Y ; +input A ; +assign Y = A; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SINK.v b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SINK.v new file mode 100644 index 0000000..0ee3883 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SINK.v @@ -0,0 +1,13 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_SINK.v +module NV_BLKBOX_SINK ( + A + ); +input A ; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SINK.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SINK.v.vcp new file mode 100644 index 0000000..0ee3883 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SINK.v.vcp @@ -0,0 +1,13 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_SINK.v +module NV_BLKBOX_SINK ( + A + ); +input A ; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0.v b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0.v new file mode 100644 index 0000000..14e0fa2 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0.v @@ -0,0 +1,14 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_SRC0.v +module NV_BLKBOX_SRC0 ( + Y + ); +output Y ; +assign Y = 1'b0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0.v.vcp new file mode 100644 index 0000000..14e0fa2 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0.v.vcp @@ -0,0 +1,14 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_SRC0.v +module NV_BLKBOX_SRC0 ( + Y + ); +output Y ; +assign Y = 1'b0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0_X.v b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0_X.v new file mode 100644 index 0000000..e4bf28c --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0_X.v @@ -0,0 +1,14 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_SRC0_X.v +module NV_BLKBOX_SRC0_X( +Y +); +output Y; +assign Y = 1'b0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0_X.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0_X.v.vcp new file mode 100644 index 0000000..e4bf28c --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_BLKBOX_SRC0_X.v.vcp @@ -0,0 +1,14 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_BLKBOX_SRC0_X.v +module NV_BLKBOX_SRC0_X( +Y +); +output Y; +assign Y = 1'b0; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_CLK_gate_power.v b/designs/src/NVDLA/vmod/vlibs/NV_CLK_gate_power.v new file mode 100644 index 0000000..88922af --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_CLK_gate_power.v @@ -0,0 +1,30 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_CLK_gate_power.v +module NV_CLK_gate_power (clk, reset_, clk_en, clk_gated); +input clk, reset_, clk_en; +output clk_gated; +`ifdef VLIB_BYPASS_POWER_CG +assign clk_gated = clk; +`else +CKLNQD12 p_clkgate (.TE(1'b0), .CP(clk), .E(clk_en), .Q(clk_gated)); +`endif // VLIB_BYPASS_POWER_CG +// the gated clk better not be x after reset +// +`ifdef VERILINT +`else +// synopsys translate_off +reg disable_asserts; initial disable_asserts = $test$plusargs( "disable_nv_clk_gate_asserts" ) != 0; +nv_assert_no_x #(0, 1, 0, "clk_gated is X after reset" ) + clk_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_gated ) ); +// Above assert is not reliable for catching X on clk_en. See bug 872824. +nv_assert_no_x #(0, 1, 0, "clk_en is X after reset" ) + clk_en_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_en ) ); +// synopsys translate_on +`endif +endmodule // NV_CLK_gate diff --git a/designs/src/NVDLA/vmod/vlibs/NV_CLK_gate_power.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_CLK_gate_power.v.vcp new file mode 100644 index 0000000..88922af --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_CLK_gate_power.v.vcp @@ -0,0 +1,30 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_CLK_gate_power.v +module NV_CLK_gate_power (clk, reset_, clk_en, clk_gated); +input clk, reset_, clk_en; +output clk_gated; +`ifdef VLIB_BYPASS_POWER_CG +assign clk_gated = clk; +`else +CKLNQD12 p_clkgate (.TE(1'b0), .CP(clk), .E(clk_en), .Q(clk_gated)); +`endif // VLIB_BYPASS_POWER_CG +// the gated clk better not be x after reset +// +`ifdef VERILINT +`else +// synopsys translate_off +reg disable_asserts; initial disable_asserts = $test$plusargs( "disable_nv_clk_gate_asserts" ) != 0; +nv_assert_no_x #(0, 1, 0, "clk_gated is X after reset" ) + clk_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_gated ) ); +// Above assert is not reliable for catching X on clk_en. See bug 872824. +nv_assert_no_x #(0, 1, 0, "clk_en is X after reset" ) + clk_en_not_x( .clk( clk ), .reset_( reset_ || disable_asserts ), .start_event( 1'b1 ), .test_expr( clk_en ) ); +// synopsys translate_on +`endif +endmodule // NV_CLK_gate diff --git a/designs/src/NVDLA/vmod/vlibs/NV_DW02_tree.v b/designs/src/NVDLA/vmod/vlibs/NV_DW02_tree.v new file mode 100644 index 0000000..69028f9 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_DW02_tree.v @@ -0,0 +1,41 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_DW02_tree.v +module NV_DW02_tree( INPUT, OUT0, OUT1 ); +parameter num_inputs = 8; +parameter input_width = 8; +input [num_inputs*input_width-1 : 0] INPUT; +output [input_width-1:0] OUT0, OUT1; +reg [input_width-1 : 0] input_array [num_inputs-1 : 0]; +reg [input_width-1 : 0] temp_array [num_inputs-1 : 0]; +reg [input_width-1 : 0] input_slice; +integer num_in; +integer i, j; +always @ (INPUT) begin + for (i=0 ; i < num_inputs ; i=i+1) begin + for (j=0 ; j < input_width ; j=j+1) begin + input_slice[j] = INPUT[i*input_width+j]; + end + input_array[i] = input_slice; + end + for (num_in = num_inputs; num_in > 2 ; num_in = num_in - (num_in/3)) begin + for (i=0 ; i < (num_in/3) ; i = i+1) begin + temp_array[i*2] = input_array[i*3] ^ input_array[i*3+1] ^ input_array[i*3+2]; //get partial sum + temp_array[i*2+1] = ((input_array[i*3] & input_array[i*3+1]) |(input_array[i*3+1] & input_array[i*3+2]) | (input_array[i*3] & input_array[i*3+2])) << 1; //get shift carry + end + if ((num_in % 3) > 0) begin + for (i=0 ; i < (num_in % 3) ; i = i + 1) + temp_array[2 * (num_in/3) + i] = input_array[3 * (num_in/3) + i]; + end + for (i=0 ; i < num_in ; i = i + 1) + input_array[i] = temp_array[i]; //update input array. + end +end +assign OUT0 = input_array[0]; +assign OUT1 = input_array[1]; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_DW02_tree.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_DW02_tree.v.vcp new file mode 100644 index 0000000..69028f9 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_DW02_tree.v.vcp @@ -0,0 +1,41 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_DW02_tree.v +module NV_DW02_tree( INPUT, OUT0, OUT1 ); +parameter num_inputs = 8; +parameter input_width = 8; +input [num_inputs*input_width-1 : 0] INPUT; +output [input_width-1:0] OUT0, OUT1; +reg [input_width-1 : 0] input_array [num_inputs-1 : 0]; +reg [input_width-1 : 0] temp_array [num_inputs-1 : 0]; +reg [input_width-1 : 0] input_slice; +integer num_in; +integer i, j; +always @ (INPUT) begin + for (i=0 ; i < num_inputs ; i=i+1) begin + for (j=0 ; j < input_width ; j=j+1) begin + input_slice[j] = INPUT[i*input_width+j]; + end + input_array[i] = input_slice; + end + for (num_in = num_inputs; num_in > 2 ; num_in = num_in - (num_in/3)) begin + for (i=0 ; i < (num_in/3) ; i = i+1) begin + temp_array[i*2] = input_array[i*3] ^ input_array[i*3+1] ^ input_array[i*3+2]; //get partial sum + temp_array[i*2+1] = ((input_array[i*3] & input_array[i*3+1]) |(input_array[i*3+1] & input_array[i*3+2]) | (input_array[i*3] & input_array[i*3+2])) << 1; //get shift carry + end + if ((num_in % 3) > 0) begin + for (i=0 ; i < (num_in % 3) ; i = i + 1) + temp_array[2 * (num_in/3) + i] = input_array[3 * (num_in/3) + i]; + end + for (i=0 ; i < num_in ; i = i + 1) + input_array[i] = temp_array[i]; //update input array. + end +end +assign OUT0 = input_array[0]; +assign OUT1 = input_array[1]; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_DW_lsd.v b/designs/src/NVDLA/vmod/vlibs/NV_DW_lsd.v new file mode 100644 index 0000000..b0bc487 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_DW_lsd.v @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_DW_lsd.v +module NV_DW_lsd (a, dec, enc); + parameter a_width = 8; + parameter b_width = a_width-1; + localparam enc_width = ((a_width>16)?((a_width>64)?((a_width>128)?8:7):((a_width>32)?6:5)):((a_width>4)?((a_width>8)?4:3):((a_width>2)?2:1))); + input [a_width-1:0] a; + output [a_width-1:0] dec; + output [enc_width-1:0] enc; +//get the encoded output: the number of sign bits. +function [enc_width-1:0] DWF_lsd_enc (input [a_width-1:0] A); + reg [enc_width-1:0] temp_enc; + reg [enc_width-1:0] i; + reg done; + begin + done =0; + temp_enc = a_width-1; + for (i=a_width-2; done==0; i=i-1) begin + if (A[i+1] != A[i]) begin + temp_enc = a_width - i -2; + done =1; + end + else if(i==0) begin + temp_enc = a_width-1; + done =1; + end + end + DWF_lsd_enc = temp_enc; + end +endfunction +//get the sign bit position of input. +function [a_width-1:0] DWF_lsd (input [a_width-1:0] A); + reg [enc_width-1:0] temp_enc; + reg [a_width-1:0] temp_dec; + reg [enc_width-1:0] temp; + temp_enc = DWF_lsd_enc (A); + temp_dec = {a_width{1'b0}}; + temp = b_width - temp_enc; + temp_dec[temp] = 1'b1; + DWF_lsd = temp_dec; +endfunction +assign enc = DWF_lsd_enc (a); +assign dec = DWF_lsd (a); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_DW_lsd.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_DW_lsd.v.vcp new file mode 100644 index 0000000..b0bc487 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_DW_lsd.v.vcp @@ -0,0 +1,50 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_DW_lsd.v +module NV_DW_lsd (a, dec, enc); + parameter a_width = 8; + parameter b_width = a_width-1; + localparam enc_width = ((a_width>16)?((a_width>64)?((a_width>128)?8:7):((a_width>32)?6:5)):((a_width>4)?((a_width>8)?4:3):((a_width>2)?2:1))); + input [a_width-1:0] a; + output [a_width-1:0] dec; + output [enc_width-1:0] enc; +//get the encoded output: the number of sign bits. +function [enc_width-1:0] DWF_lsd_enc (input [a_width-1:0] A); + reg [enc_width-1:0] temp_enc; + reg [enc_width-1:0] i; + reg done; + begin + done =0; + temp_enc = a_width-1; + for (i=a_width-2; done==0; i=i-1) begin + if (A[i+1] != A[i]) begin + temp_enc = a_width - i -2; + done =1; + end + else if(i==0) begin + temp_enc = a_width-1; + done =1; + end + end + DWF_lsd_enc = temp_enc; + end +endfunction +//get the sign bit position of input. +function [a_width-1:0] DWF_lsd (input [a_width-1:0] A); + reg [enc_width-1:0] temp_enc; + reg [a_width-1:0] temp_dec; + reg [enc_width-1:0] temp; + temp_enc = DWF_lsd_enc (A); + temp_dec = {a_width{1'b0}}; + temp = b_width - temp_enc; + temp_dec[temp] = 1'b1; + DWF_lsd = temp_dec; +endfunction +assign enc = DWF_lsd_enc (a); +assign dec = DWF_lsd (a); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_DW_minmax.v b/designs/src/NVDLA/vmod/vlibs/NV_DW_minmax.v new file mode 100644 index 0000000..a11a947 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_DW_minmax.v @@ -0,0 +1,114 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_DW_minmax.v +module NV_DW_minmax (a ,tc ,min_max ,value ,index); + parameter width = 8; + parameter num_inputs = 2; + localparam index_width = ((num_inputs>8)? ((num_inputs> 32)? 6 : ((num_inputs>16)? 5 : 4)) : ((num_inputs>4)? 3 : ((num_inputs>2)? 2 : 1))); + input [num_inputs*width-1 : 0] a; + input tc; //dangle, only support unsigned. + input min_max; + output [width-1 : 0] value; + output [index_width-1 : 0] index; + reg [width-1 : 0] value; + reg [index_width-1 : 0] index; + wire tc_NC; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets + assign tc_NC = tc; + function [width-1 : 0] max_unsigned_value; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [width-1 : 0] value_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b0}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v >= value_v) begin + value_v = a_v; + end + end + max_unsigned_value = value_v; + end + endfunction + function [index_width-1 : 0] max_unsigned_index; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [index_width-1 : 0] index_v; + reg [width-1 : 0] value_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b0}}; + index_v = {index_width{1'b0}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v >= value_v) begin + value_v = a_v; + index_v = k[index_width-1 : 0]; + end + end + max_unsigned_index = index_v; + end + endfunction + function [width-1 : 0] min_unsigned_value; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [width-1 : 0] value_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b1}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v < value_v) begin + value_v = a_v; + end + end + min_unsigned_value = value_v; + end + endfunction + function [index_width-1 : 0] min_unsigned_index; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [width-1 : 0] value_v; + reg [index_width-1 : 0] index_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b1}}; + index_v = {index_width{1'b0}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v < value_v) begin + value_v = a_v; + index_v = k[index_width-1 : 0]; + end + end + min_unsigned_index = index_v; + end + endfunction + always @(a or min_max) begin + if (min_max == 1'b0) begin + value = min_unsigned_value (a); + index = min_unsigned_index (a); + end + else begin + value = max_unsigned_value (a); + index = max_unsigned_index (a); + end + end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_DW_minmax.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_DW_minmax.v.vcp new file mode 100644 index 0000000..a11a947 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_DW_minmax.v.vcp @@ -0,0 +1,114 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_DW_minmax.v +module NV_DW_minmax (a ,tc ,min_max ,value ,index); + parameter width = 8; + parameter num_inputs = 2; + localparam index_width = ((num_inputs>8)? ((num_inputs> 32)? 6 : ((num_inputs>16)? 5 : 4)) : ((num_inputs>4)? 3 : ((num_inputs>2)? 2 : 1))); + input [num_inputs*width-1 : 0] a; + input tc; //dangle, only support unsigned. + input min_max; + output [width-1 : 0] value; + output [index_width-1 : 0] index; + reg [width-1 : 0] value; + reg [index_width-1 : 0] index; + wire tc_NC; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets + assign tc_NC = tc; + function [width-1 : 0] max_unsigned_value; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [width-1 : 0] value_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b0}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v >= value_v) begin + value_v = a_v; + end + end + max_unsigned_value = value_v; + end + endfunction + function [index_width-1 : 0] max_unsigned_index; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [index_width-1 : 0] index_v; + reg [width-1 : 0] value_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b0}}; + index_v = {index_width{1'b0}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v >= value_v) begin + value_v = a_v; + index_v = k[index_width-1 : 0]; + end + end + max_unsigned_index = index_v; + end + endfunction + function [width-1 : 0] min_unsigned_value; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [width-1 : 0] value_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b1}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v < value_v) begin + value_v = a_v; + end + end + min_unsigned_value = value_v; + end + endfunction + function [index_width-1 : 0] min_unsigned_index; + input [num_inputs*width-1 : 0] a; + reg [width-1 : 0] a_v; + reg [width-1 : 0] value_v; + reg [index_width-1 : 0] index_v; + reg [index_width : 0] k; + begin + value_v = {width{1'b1}}; + index_v = {index_width{1'b0}}; + for (k = 0; k < num_inputs; k = k+1) begin + a_v = a[width-1 : 0]; + a = a >> width; + if (a_v < value_v) begin + value_v = a_v; + index_v = k[index_width-1 : 0]; + end + end + min_unsigned_index = index_v; + end + endfunction + always @(a or min_max) begin + if (min_max == 1'b0) begin + value = min_unsigned_value (a); + index = min_unsigned_index (a); + end + else begin + value = max_unsigned_value (a); + index = max_unsigned_index (a); + end + end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_icvt.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_icvt.v new file mode 100644 index 0000000..89a3975 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_icvt.v @@ -0,0 +1,1456 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_HLS_icvt.v +module NV_NVDLA_CDP_HLS_icvt ( + cfg_alu_in //|< i + ,cfg_mul_in //|< i + ,cfg_precision //|< i + ,cfg_truncate //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_out_pvld //|> o + ); +input [15:0] cfg_alu_in; +input [15:0] cfg_mul_in; +input [1:0] cfg_precision; +input [4:0] cfg_truncate; +input [15:0] chn_data_in; +input chn_in_pvld; +input chn_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [17:0] chn_data_out; +output chn_in_prdy; +output chn_out_pvld; +wire [8:0] cfg_alu_ext; +wire [7:0] chn_data_lsb; +wire [7:0] chn_data_msb; +wire [17:0] chn_dout; +wire [17:0] chn_int16_dout; +wire chn_int16_prdy; +wire chn_int16_pvld; +wire [17:0] chn_int8_dout; +wire chn_int8_prdy; +wire chn_int8_pvld; +wire [8:0] data_lsb_ext; +wire [8:0] data_msb_ext; +wire mon_sub_lc; +wire mon_sub_mc; +wire [32:0] mul_data_out; +wire [32:0] mul_dout; +wire [24:0] mul_lsb_data_out; +wire [24:0] mul_lsb_dout; +wire [24:0] mul_msb_data_out; +wire [24:0] mul_msb_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire mul_outh_prdy; +wire mul_outh_pvld; +wire [16:0] sub_data_out; +wire [16:0] sub_dout; +wire [8:0] sub_lsb_data_out; +wire [8:0] sub_lsb_dout; +wire [8:0] sub_msb_data_out; +wire [8:0] sub_msb_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire sub_outh_prdy; +wire sub_outh_pvld; +wire [16:0] tru_data_out; +wire [16:0] tru_dout; +wire tru_final_prdy; +wire tru_final_pvld; +wire [8:0] tru_lsb_data_out; +wire [8:0] tru_lsb_dout; +wire [8:0] tru_msb_data_out; +wire [8:0] tru_msb_dout; +wire tru_out_prdy; +wire tru_out_pvld; +wire tru_outh_prdy; +wire tru_outh_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//int8 cvt +assign chn_data_lsb[7:0] = chn_data_in[7:0]; +assign chn_data_msb[7:0] = chn_data_in[15:8]; +assign data_lsb_ext[8:0] = {1'b0,chn_data_lsb[7:0]}; +assign data_msb_ext[8:0] = {1'b0,chn_data_msb[7:0]}; +assign cfg_alu_ext[8:0] = {cfg_alu_in[8 -1],cfg_alu_in[7:0]}; +//sub +assign {mon_sub_lc,sub_lsb_dout[8:0]} = $signed(data_lsb_ext[8:0]) -$signed(cfg_alu_ext[8:0]); +assign {mon_sub_mc,sub_msb_dout[8:0]} = $signed(data_msb_ext[8:0]) -$signed(cfg_alu_ext[8:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int8_pvld (chn_int8_pvld) //|< w + ,.sub_lsb_dout (sub_lsb_dout[8:0]) //|< w + ,.sub_msb_dout (sub_msb_dout[8:0]) //|< w + ,.sub_outh_prdy (sub_outh_prdy) //|< w + ,.chn_int8_prdy (chn_int8_prdy) //|> w + ,.sub_lsb_data_out (sub_lsb_data_out[8:0]) //|> w + ,.sub_msb_data_out (sub_msb_data_out[8:0]) //|> w + ,.sub_outh_pvld (sub_outh_pvld) //|> w + ); +//mul +assign mul_lsb_dout[24:0] = $signed(sub_lsb_data_out[8:0]) * $signed(cfg_mul_in[15:0]); +assign mul_msb_dout[24:0] = $signed(sub_msb_data_out[8:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_lsb_dout (mul_lsb_dout[24:0]) //|< w + ,.mul_msb_dout (mul_msb_dout[24:0]) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|< w + ,.sub_outh_pvld (sub_outh_pvld) //|< w + ,.mul_lsb_data_out (mul_lsb_data_out[24:0]) //|> w + ,.mul_msb_data_out (mul_msb_data_out[24:0]) //|> w + ,.mul_outh_pvld (mul_outh_pvld) //|> w + ,.sub_outh_prdy (sub_outh_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 9 ),.OUT_WIDTH(9 ),.SHIFT_WIDTH(5 )) shiftright_su_lsb ( + .data_in (mul_lsb_data_out[24:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< i + ,.data_out (tru_lsb_dout[8:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 9 ),.OUT_WIDTH(9 ),.SHIFT_WIDTH(5 )) shiftright_su_msb ( + .data_in (mul_msb_data_out[24:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< i + ,.data_out (tru_msb_dout[8:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_CDP_HLS_ICVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_outh_pvld (mul_outh_pvld) //|< w + ,.tru_lsb_dout (tru_lsb_dout[8:0]) //|< w + ,.tru_msb_dout (tru_msb_dout[8:0]) //|< w + ,.tru_outh_prdy (tru_outh_prdy) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|> w + ,.tru_lsb_data_out (tru_lsb_data_out[8:0]) //|> w + ,.tru_msb_data_out (tru_msb_data_out[8:0]) //|> w + ,.tru_outh_pvld (tru_outh_pvld) //|> w + ); +assign chn_int8_dout[17:0] = {tru_msb_data_out[8:0],tru_lsb_data_out[8:0]}; +/////////int16 covert +//sub +assign sub_dout[16:0] = $signed(chn_data_in[15:0]) -$signed(cfg_alu_in[15:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int16_pvld (chn_int16_pvld) //|< w + ,.sub_dout (sub_dout[16:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_int16_prdy (chn_int16_prdy) //|> w + ,.sub_data_out (sub_data_out[16:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[32:0] = $signed(sub_data_out[16:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[32:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[32:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 17 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(5 )) shiftright_su ( + .data_in (mul_data_out[32:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< i + ,.data_out (tru_dout[16:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_CDP_HLS_ICVT_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.tru_dout (tru_dout[16:0]) //|< w + ,.tru_out_prdy (tru_out_prdy) //|< w + ,.mul_out_prdy (mul_out_prdy) //|> w + ,.tru_data_out (tru_data_out[16:0]) //|> w + ,.tru_out_pvld (tru_out_pvld) //|> w + ); +assign chn_int16_dout[17:0] = {{1{tru_data_out[16]}}, tru_data_out[16:0]}; +//mux int16 and int8 final data out +assign chn_in_prdy = (cfg_precision[1:0] == 1 ) ? chn_int16_prdy : chn_int8_prdy; +assign chn_int8_pvld = (cfg_precision[1:0] == 1 ) ? 1'b0 : chn_in_pvld; +assign chn_int16_pvld = (cfg_precision[1:0] == 1 ) ? chn_in_pvld : 1'b0; +assign tru_final_pvld = (cfg_precision[1:0] == 1 ) ? tru_out_pvld : tru_outh_pvld; +assign tru_out_prdy = (cfg_precision[1:0] == 1 ) ? tru_final_prdy : 1'b1; +assign tru_outh_prdy = (cfg_precision[1:0] == 1 ) ? 1'b1: tru_final_prdy; +assign chn_dout[17:0] = (cfg_precision[1:0] == 1 ) ? chn_int16_dout[17:0] : chn_int8_dout[17:0]; +assign chn_data_out[17:0] = chn_dout[17:0]; +assign chn_out_pvld = tru_final_pvld; +assign tru_final_prdy = chn_out_prdy; +endmodule // NV_NVDLA_CDP_HLS_icvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sub_msb_data_out[8:0],sub_lsb_data_out[8:0]} (sub_outh_pvld,sub_outh_prdy) <= {sub_msb_dout[8:0],sub_lsb_dout[8:0]} (chn_int8_pvld,chn_int8_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int8_pvld + ,sub_lsb_dout + ,sub_msb_dout + ,sub_outh_prdy + ,chn_int8_prdy + ,sub_lsb_data_out + ,sub_msb_data_out + ,sub_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int8_pvld; +input [8:0] sub_lsb_dout; +input [8:0] sub_msb_dout; +input sub_outh_prdy; +output chn_int8_prdy; +output [8:0] sub_lsb_data_out; +output [8:0] sub_msb_data_out; +output sub_outh_pvld; +reg chn_int8_prdy; +reg [17:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [17:0] p1_skid_data; +reg [17:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [8:0] sub_lsb_data_out; +reg [8:0] sub_msb_data_out; +reg sub_outh_pvld; +//## pipe (1) skid buffer +always @( + chn_int8_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_int8_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_int8_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_int8_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {sub_msb_dout[8:0],sub_lsb_dout[8:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_int8_pvld + or p1_skid_valid + or sub_msb_dout + or sub_lsb_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_int8_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {sub_msb_dout[8:0],sub_lsb_dout[8:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_outh_prdy + or p1_pipe_data + ) begin + sub_outh_pvld = p1_pipe_valid; + p1_pipe_ready = sub_outh_prdy; + {sub_msb_data_out[8:0],sub_lsb_data_out[8:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_outh_pvld^sub_outh_prdy^chn_int8_pvld^chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_int8_pvld && !chn_int8_prdy), (chn_int8_pvld), (chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_msb_data_out[24:0],mul_lsb_data_out[24:0]} (mul_outh_pvld,mul_outh_prdy) <= {mul_msb_dout[24:0],mul_lsb_dout[24:0]} (sub_outh_pvld,sub_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_lsb_dout + ,mul_msb_dout + ,mul_outh_prdy + ,sub_outh_pvld + ,mul_lsb_data_out + ,mul_msb_data_out + ,mul_outh_pvld + ,sub_outh_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [24:0] mul_lsb_dout; +input [24:0] mul_msb_dout; +input mul_outh_prdy; +input sub_outh_pvld; +output [24:0] mul_lsb_data_out; +output [24:0] mul_msb_data_out; +output mul_outh_pvld; +output sub_outh_prdy; +reg [24:0] mul_lsb_data_out; +reg [24:0] mul_msb_data_out; +reg mul_outh_pvld; +reg [49:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [49:0] p2_skid_data; +reg [49:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_outh_prdy; +//## pipe (2) skid buffer +always @( + sub_outh_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_outh_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_outh_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_outh_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {mul_msb_dout[24:0],mul_lsb_dout[24:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_outh_pvld + or p2_skid_valid + or mul_msb_dout + or mul_lsb_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_outh_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {mul_msb_dout[24:0],mul_lsb_dout[24:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_outh_prdy + or p2_pipe_data + ) begin + mul_outh_pvld = p2_pipe_valid; + p2_pipe_ready = mul_outh_prdy; + {mul_msb_data_out[24:0],mul_lsb_data_out[24:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_outh_pvld^mul_outh_prdy^sub_outh_pvld^sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_outh_pvld && !sub_outh_prdy), (sub_outh_pvld), (sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {tru_msb_data_out[8:0],tru_lsb_data_out[8:0]} (tru_outh_pvld,tru_outh_prdy) <= {tru_msb_dout[8:0],tru_lsb_dout[8:0]} (mul_outh_pvld,mul_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_outh_pvld + ,tru_lsb_dout + ,tru_msb_dout + ,tru_outh_prdy + ,mul_outh_prdy + ,tru_lsb_data_out + ,tru_msb_data_out + ,tru_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_outh_pvld; +input [8:0] tru_lsb_dout; +input [8:0] tru_msb_dout; +input tru_outh_prdy; +output mul_outh_prdy; +output [8:0] tru_lsb_data_out; +output [8:0] tru_msb_data_out; +output tru_outh_pvld; +reg mul_outh_prdy; +reg [17:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [17:0] p3_skid_data; +reg [17:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg [8:0] tru_lsb_data_out; +reg [8:0] tru_msb_data_out; +reg tru_outh_pvld; +//## pipe (3) skid buffer +always @( + mul_outh_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_outh_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_outh_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_outh_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {tru_msb_dout[8:0],tru_lsb_dout[8:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_outh_pvld + or p3_skid_valid + or tru_msb_dout + or tru_lsb_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_outh_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {tru_msb_dout[8:0],tru_lsb_dout[8:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tru_outh_prdy + or p3_pipe_data + ) begin + tru_outh_pvld = p3_pipe_valid; + p3_pipe_ready = tru_outh_prdy; + {tru_msb_data_out[8:0],tru_lsb_data_out[8:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_outh_pvld^tru_outh_prdy^mul_outh_pvld^mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_outh_pvld && !mul_outh_prdy), (mul_outh_pvld), (mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[16:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[16:0] (chn_int16_pvld,chn_int16_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int16_pvld + ,sub_dout + ,sub_out_prdy + ,chn_int16_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int16_pvld; +input [16:0] sub_dout; +input sub_out_prdy; +output chn_int16_prdy; +output [16:0] sub_data_out; +output sub_out_pvld; +reg chn_int16_prdy; +reg [16:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [16:0] p4_skid_data; +reg [16:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +reg [16:0] sub_data_out; +reg sub_out_pvld; +//## pipe (4) skid buffer +always @( + chn_int16_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = chn_int16_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + chn_int16_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + chn_int16_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? sub_dout[16:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or chn_int16_pvld + or p4_skid_valid + or sub_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? chn_int16_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? sub_dout[16:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or sub_out_prdy + or p4_pipe_data + ) begin + sub_out_pvld = p4_pipe_valid; + p4_pipe_ready = sub_out_prdy; + sub_data_out[16:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_int16_pvld^chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (chn_int16_pvld && !chn_int16_prdy), (chn_int16_pvld), (chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[32:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[32:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [32:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [32:0] mul_data_out; +reg mul_out_pvld; +reg [32:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [32:0] p5_skid_data; +reg [32:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +reg sub_out_prdy; +//## pipe (5) skid buffer +always @( + sub_out_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = sub_out_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + sub_out_prdy <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? mul_dout[32:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or sub_out_pvld + or p5_skid_valid + or mul_dout + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? sub_out_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? mul_dout[32:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mul_out_prdy + or p5_pipe_data + ) begin + mul_out_pvld = p5_pipe_valid; + p5_pipe_ready = mul_out_prdy; + mul_data_out[32:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is tru_data_out[16:0] (tru_out_pvld,tru_out_prdy) <= tru_dout[16:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,tru_dout + ,tru_out_prdy + ,mul_out_prdy + ,tru_data_out + ,tru_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input [16:0] tru_dout; +input tru_out_prdy; +output mul_out_prdy; +output [16:0] tru_data_out; +output tru_out_pvld; +reg mul_out_prdy; +reg [16:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg p6_skid_catch; +reg [16:0] p6_skid_data; +reg [16:0] p6_skid_pipe_data; +reg p6_skid_pipe_ready; +reg p6_skid_pipe_valid; +reg p6_skid_ready; +reg p6_skid_ready_flop; +reg p6_skid_valid; +reg [16:0] tru_data_out; +reg tru_out_pvld; +//## pipe (6) skid buffer +always @( + mul_out_pvld + or p6_skid_ready_flop + or p6_skid_pipe_ready + or p6_skid_valid + ) begin + p6_skid_catch = mul_out_pvld && p6_skid_ready_flop && !p6_skid_pipe_ready; + p6_skid_ready = (p6_skid_valid)? p6_skid_pipe_ready : !p6_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_skid_valid <= 1'b0; + p6_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p6_skid_valid <= (p6_skid_valid)? !p6_skid_pipe_ready : p6_skid_catch; + p6_skid_ready_flop <= p6_skid_ready; + mul_out_prdy <= p6_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_skid_data <= (p6_skid_catch)? tru_dout[16:0] : p6_skid_data; +// VCS sop_coverage_off end +end +always @( + p6_skid_ready_flop + or mul_out_pvld + or p6_skid_valid + or tru_dout + or p6_skid_data + ) begin + p6_skid_pipe_valid = (p6_skid_ready_flop)? mul_out_pvld : p6_skid_valid; +// VCS sop_coverage_off start + p6_skid_pipe_data = (p6_skid_ready_flop)? tru_dout[16:0] : p6_skid_data; +// VCS sop_coverage_off end +end +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? p6_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && p6_skid_pipe_valid)? p6_skid_pipe_data : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + p6_skid_pipe_ready = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or tru_out_prdy + or p6_pipe_data + ) begin + tru_out_pvld = p6_pipe_valid; + p6_pipe_ready = tru_out_prdy; + tru_data_out[16:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_out_pvld^tru_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p6 diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_icvt.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_icvt.v.vcp new file mode 100644 index 0000000..89a3975 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_icvt.v.vcp @@ -0,0 +1,1456 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_HLS_icvt.v +module NV_NVDLA_CDP_HLS_icvt ( + cfg_alu_in //|< i + ,cfg_mul_in //|< i + ,cfg_precision //|< i + ,cfg_truncate //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_out_pvld //|> o + ); +input [15:0] cfg_alu_in; +input [15:0] cfg_mul_in; +input [1:0] cfg_precision; +input [4:0] cfg_truncate; +input [15:0] chn_data_in; +input chn_in_pvld; +input chn_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [17:0] chn_data_out; +output chn_in_prdy; +output chn_out_pvld; +wire [8:0] cfg_alu_ext; +wire [7:0] chn_data_lsb; +wire [7:0] chn_data_msb; +wire [17:0] chn_dout; +wire [17:0] chn_int16_dout; +wire chn_int16_prdy; +wire chn_int16_pvld; +wire [17:0] chn_int8_dout; +wire chn_int8_prdy; +wire chn_int8_pvld; +wire [8:0] data_lsb_ext; +wire [8:0] data_msb_ext; +wire mon_sub_lc; +wire mon_sub_mc; +wire [32:0] mul_data_out; +wire [32:0] mul_dout; +wire [24:0] mul_lsb_data_out; +wire [24:0] mul_lsb_dout; +wire [24:0] mul_msb_data_out; +wire [24:0] mul_msb_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire mul_outh_prdy; +wire mul_outh_pvld; +wire [16:0] sub_data_out; +wire [16:0] sub_dout; +wire [8:0] sub_lsb_data_out; +wire [8:0] sub_lsb_dout; +wire [8:0] sub_msb_data_out; +wire [8:0] sub_msb_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire sub_outh_prdy; +wire sub_outh_pvld; +wire [16:0] tru_data_out; +wire [16:0] tru_dout; +wire tru_final_prdy; +wire tru_final_pvld; +wire [8:0] tru_lsb_data_out; +wire [8:0] tru_lsb_dout; +wire [8:0] tru_msb_data_out; +wire [8:0] tru_msb_dout; +wire tru_out_prdy; +wire tru_out_pvld; +wire tru_outh_prdy; +wire tru_outh_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//int8 cvt +assign chn_data_lsb[7:0] = chn_data_in[7:0]; +assign chn_data_msb[7:0] = chn_data_in[15:8]; +assign data_lsb_ext[8:0] = {1'b0,chn_data_lsb[7:0]}; +assign data_msb_ext[8:0] = {1'b0,chn_data_msb[7:0]}; +assign cfg_alu_ext[8:0] = {cfg_alu_in[8 -1],cfg_alu_in[7:0]}; +//sub +assign {mon_sub_lc,sub_lsb_dout[8:0]} = $signed(data_lsb_ext[8:0]) -$signed(cfg_alu_ext[8:0]); +assign {mon_sub_mc,sub_msb_dout[8:0]} = $signed(data_msb_ext[8:0]) -$signed(cfg_alu_ext[8:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int8_pvld (chn_int8_pvld) //|< w + ,.sub_lsb_dout (sub_lsb_dout[8:0]) //|< w + ,.sub_msb_dout (sub_msb_dout[8:0]) //|< w + ,.sub_outh_prdy (sub_outh_prdy) //|< w + ,.chn_int8_prdy (chn_int8_prdy) //|> w + ,.sub_lsb_data_out (sub_lsb_data_out[8:0]) //|> w + ,.sub_msb_data_out (sub_msb_data_out[8:0]) //|> w + ,.sub_outh_pvld (sub_outh_pvld) //|> w + ); +//mul +assign mul_lsb_dout[24:0] = $signed(sub_lsb_data_out[8:0]) * $signed(cfg_mul_in[15:0]); +assign mul_msb_dout[24:0] = $signed(sub_msb_data_out[8:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_lsb_dout (mul_lsb_dout[24:0]) //|< w + ,.mul_msb_dout (mul_msb_dout[24:0]) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|< w + ,.sub_outh_pvld (sub_outh_pvld) //|< w + ,.mul_lsb_data_out (mul_lsb_data_out[24:0]) //|> w + ,.mul_msb_data_out (mul_msb_data_out[24:0]) //|> w + ,.mul_outh_pvld (mul_outh_pvld) //|> w + ,.sub_outh_prdy (sub_outh_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 9 ),.OUT_WIDTH(9 ),.SHIFT_WIDTH(5 )) shiftright_su_lsb ( + .data_in (mul_lsb_data_out[24:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< i + ,.data_out (tru_lsb_dout[8:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 9 ),.OUT_WIDTH(9 ),.SHIFT_WIDTH(5 )) shiftright_su_msb ( + .data_in (mul_msb_data_out[24:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< i + ,.data_out (tru_msb_dout[8:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_CDP_HLS_ICVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_outh_pvld (mul_outh_pvld) //|< w + ,.tru_lsb_dout (tru_lsb_dout[8:0]) //|< w + ,.tru_msb_dout (tru_msb_dout[8:0]) //|< w + ,.tru_outh_prdy (tru_outh_prdy) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|> w + ,.tru_lsb_data_out (tru_lsb_data_out[8:0]) //|> w + ,.tru_msb_data_out (tru_msb_data_out[8:0]) //|> w + ,.tru_outh_pvld (tru_outh_pvld) //|> w + ); +assign chn_int8_dout[17:0] = {tru_msb_data_out[8:0],tru_lsb_data_out[8:0]}; +/////////int16 covert +//sub +assign sub_dout[16:0] = $signed(chn_data_in[15:0]) -$signed(cfg_alu_in[15:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int16_pvld (chn_int16_pvld) //|< w + ,.sub_dout (sub_dout[16:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_int16_prdy (chn_int16_prdy) //|> w + ,.sub_data_out (sub_data_out[16:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[32:0] = $signed(sub_data_out[16:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_ICVT_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[32:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[32:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsu #(.IN_WIDTH(16 + 17 ),.OUT_WIDTH(17 ),.SHIFT_WIDTH(5 )) shiftright_su ( + .data_in (mul_data_out[32:0]) //|< w + ,.shift_num (cfg_truncate[4:0]) //|< i + ,.data_out (tru_dout[16:0]) //|> w + ); +//signed +//unsigned +NV_NVDLA_CDP_HLS_ICVT_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.tru_dout (tru_dout[16:0]) //|< w + ,.tru_out_prdy (tru_out_prdy) //|< w + ,.mul_out_prdy (mul_out_prdy) //|> w + ,.tru_data_out (tru_data_out[16:0]) //|> w + ,.tru_out_pvld (tru_out_pvld) //|> w + ); +assign chn_int16_dout[17:0] = {{1{tru_data_out[16]}}, tru_data_out[16:0]}; +//mux int16 and int8 final data out +assign chn_in_prdy = (cfg_precision[1:0] == 1 ) ? chn_int16_prdy : chn_int8_prdy; +assign chn_int8_pvld = (cfg_precision[1:0] == 1 ) ? 1'b0 : chn_in_pvld; +assign chn_int16_pvld = (cfg_precision[1:0] == 1 ) ? chn_in_pvld : 1'b0; +assign tru_final_pvld = (cfg_precision[1:0] == 1 ) ? tru_out_pvld : tru_outh_pvld; +assign tru_out_prdy = (cfg_precision[1:0] == 1 ) ? tru_final_prdy : 1'b1; +assign tru_outh_prdy = (cfg_precision[1:0] == 1 ) ? 1'b1: tru_final_prdy; +assign chn_dout[17:0] = (cfg_precision[1:0] == 1 ) ? chn_int16_dout[17:0] : chn_int8_dout[17:0]; +assign chn_data_out[17:0] = chn_dout[17:0]; +assign chn_out_pvld = tru_final_pvld; +assign tru_final_prdy = chn_out_prdy; +endmodule // NV_NVDLA_CDP_HLS_icvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sub_msb_data_out[8:0],sub_lsb_data_out[8:0]} (sub_outh_pvld,sub_outh_prdy) <= {sub_msb_dout[8:0],sub_lsb_dout[8:0]} (chn_int8_pvld,chn_int8_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int8_pvld + ,sub_lsb_dout + ,sub_msb_dout + ,sub_outh_prdy + ,chn_int8_prdy + ,sub_lsb_data_out + ,sub_msb_data_out + ,sub_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int8_pvld; +input [8:0] sub_lsb_dout; +input [8:0] sub_msb_dout; +input sub_outh_prdy; +output chn_int8_prdy; +output [8:0] sub_lsb_data_out; +output [8:0] sub_msb_data_out; +output sub_outh_pvld; +reg chn_int8_prdy; +reg [17:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [17:0] p1_skid_data; +reg [17:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [8:0] sub_lsb_data_out; +reg [8:0] sub_msb_data_out; +reg sub_outh_pvld; +//## pipe (1) skid buffer +always @( + chn_int8_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_int8_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_int8_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_int8_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {sub_msb_dout[8:0],sub_lsb_dout[8:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_int8_pvld + or p1_skid_valid + or sub_msb_dout + or sub_lsb_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_int8_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {sub_msb_dout[8:0],sub_lsb_dout[8:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_outh_prdy + or p1_pipe_data + ) begin + sub_outh_pvld = p1_pipe_valid; + p1_pipe_ready = sub_outh_prdy; + {sub_msb_data_out[8:0],sub_lsb_data_out[8:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_outh_pvld^sub_outh_prdy^chn_int8_pvld^chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_int8_pvld && !chn_int8_prdy), (chn_int8_pvld), (chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_msb_data_out[24:0],mul_lsb_data_out[24:0]} (mul_outh_pvld,mul_outh_prdy) <= {mul_msb_dout[24:0],mul_lsb_dout[24:0]} (sub_outh_pvld,sub_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_lsb_dout + ,mul_msb_dout + ,mul_outh_prdy + ,sub_outh_pvld + ,mul_lsb_data_out + ,mul_msb_data_out + ,mul_outh_pvld + ,sub_outh_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [24:0] mul_lsb_dout; +input [24:0] mul_msb_dout; +input mul_outh_prdy; +input sub_outh_pvld; +output [24:0] mul_lsb_data_out; +output [24:0] mul_msb_data_out; +output mul_outh_pvld; +output sub_outh_prdy; +reg [24:0] mul_lsb_data_out; +reg [24:0] mul_msb_data_out; +reg mul_outh_pvld; +reg [49:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [49:0] p2_skid_data; +reg [49:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_outh_prdy; +//## pipe (2) skid buffer +always @( + sub_outh_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_outh_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_outh_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_outh_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {mul_msb_dout[24:0],mul_lsb_dout[24:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_outh_pvld + or p2_skid_valid + or mul_msb_dout + or mul_lsb_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_outh_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {mul_msb_dout[24:0],mul_lsb_dout[24:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_outh_prdy + or p2_pipe_data + ) begin + mul_outh_pvld = p2_pipe_valid; + p2_pipe_ready = mul_outh_prdy; + {mul_msb_data_out[24:0],mul_lsb_data_out[24:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_outh_pvld^mul_outh_prdy^sub_outh_pvld^sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_outh_pvld && !sub_outh_prdy), (sub_outh_pvld), (sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {tru_msb_data_out[8:0],tru_lsb_data_out[8:0]} (tru_outh_pvld,tru_outh_prdy) <= {tru_msb_dout[8:0],tru_lsb_dout[8:0]} (mul_outh_pvld,mul_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_outh_pvld + ,tru_lsb_dout + ,tru_msb_dout + ,tru_outh_prdy + ,mul_outh_prdy + ,tru_lsb_data_out + ,tru_msb_data_out + ,tru_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_outh_pvld; +input [8:0] tru_lsb_dout; +input [8:0] tru_msb_dout; +input tru_outh_prdy; +output mul_outh_prdy; +output [8:0] tru_lsb_data_out; +output [8:0] tru_msb_data_out; +output tru_outh_pvld; +reg mul_outh_prdy; +reg [17:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [17:0] p3_skid_data; +reg [17:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg [8:0] tru_lsb_data_out; +reg [8:0] tru_msb_data_out; +reg tru_outh_pvld; +//## pipe (3) skid buffer +always @( + mul_outh_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_outh_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_outh_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_outh_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {tru_msb_dout[8:0],tru_lsb_dout[8:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_outh_pvld + or p3_skid_valid + or tru_msb_dout + or tru_lsb_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_outh_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {tru_msb_dout[8:0],tru_lsb_dout[8:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tru_outh_prdy + or p3_pipe_data + ) begin + tru_outh_pvld = p3_pipe_valid; + p3_pipe_ready = tru_outh_prdy; + {tru_msb_data_out[8:0],tru_lsb_data_out[8:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_outh_pvld^tru_outh_prdy^mul_outh_pvld^mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_outh_pvld && !mul_outh_prdy), (mul_outh_pvld), (mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[16:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[16:0] (chn_int16_pvld,chn_int16_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int16_pvld + ,sub_dout + ,sub_out_prdy + ,chn_int16_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int16_pvld; +input [16:0] sub_dout; +input sub_out_prdy; +output chn_int16_prdy; +output [16:0] sub_data_out; +output sub_out_pvld; +reg chn_int16_prdy; +reg [16:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [16:0] p4_skid_data; +reg [16:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +reg [16:0] sub_data_out; +reg sub_out_pvld; +//## pipe (4) skid buffer +always @( + chn_int16_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = chn_int16_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + chn_int16_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + chn_int16_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? sub_dout[16:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or chn_int16_pvld + or p4_skid_valid + or sub_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? chn_int16_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? sub_dout[16:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or sub_out_prdy + or p4_pipe_data + ) begin + sub_out_pvld = p4_pipe_valid; + p4_pipe_ready = sub_out_prdy; + sub_data_out[16:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_int16_pvld^chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (chn_int16_pvld && !chn_int16_prdy), (chn_int16_pvld), (chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[32:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[32:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [32:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [32:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [32:0] mul_data_out; +reg mul_out_pvld; +reg [32:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [32:0] p5_skid_data; +reg [32:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +reg sub_out_prdy; +//## pipe (5) skid buffer +always @( + sub_out_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = sub_out_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + sub_out_prdy <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? mul_dout[32:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or sub_out_pvld + or p5_skid_valid + or mul_dout + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? sub_out_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? mul_dout[32:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mul_out_prdy + or p5_pipe_data + ) begin + mul_out_pvld = p5_pipe_valid; + p5_pipe_ready = mul_out_prdy; + mul_data_out[32:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is tru_data_out[16:0] (tru_out_pvld,tru_out_prdy) <= tru_dout[16:0] (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_ICVT_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,tru_dout + ,tru_out_prdy + ,mul_out_prdy + ,tru_data_out + ,tru_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input [16:0] tru_dout; +input tru_out_prdy; +output mul_out_prdy; +output [16:0] tru_data_out; +output tru_out_pvld; +reg mul_out_prdy; +reg [16:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg p6_skid_catch; +reg [16:0] p6_skid_data; +reg [16:0] p6_skid_pipe_data; +reg p6_skid_pipe_ready; +reg p6_skid_pipe_valid; +reg p6_skid_ready; +reg p6_skid_ready_flop; +reg p6_skid_valid; +reg [16:0] tru_data_out; +reg tru_out_pvld; +//## pipe (6) skid buffer +always @( + mul_out_pvld + or p6_skid_ready_flop + or p6_skid_pipe_ready + or p6_skid_valid + ) begin + p6_skid_catch = mul_out_pvld && p6_skid_ready_flop && !p6_skid_pipe_ready; + p6_skid_ready = (p6_skid_valid)? p6_skid_pipe_ready : !p6_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_skid_valid <= 1'b0; + p6_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p6_skid_valid <= (p6_skid_valid)? !p6_skid_pipe_ready : p6_skid_catch; + p6_skid_ready_flop <= p6_skid_ready; + mul_out_prdy <= p6_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_skid_data <= (p6_skid_catch)? tru_dout[16:0] : p6_skid_data; +// VCS sop_coverage_off end +end +always @( + p6_skid_ready_flop + or mul_out_pvld + or p6_skid_valid + or tru_dout + or p6_skid_data + ) begin + p6_skid_pipe_valid = (p6_skid_ready_flop)? mul_out_pvld : p6_skid_valid; +// VCS sop_coverage_off start + p6_skid_pipe_data = (p6_skid_ready_flop)? tru_dout[16:0] : p6_skid_data; +// VCS sop_coverage_off end +end +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? p6_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && p6_skid_pipe_valid)? p6_skid_pipe_data : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + p6_skid_pipe_ready = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or tru_out_prdy + or p6_pipe_data + ) begin + tru_out_pvld = p6_pipe_valid; + p6_pipe_ready = tru_out_prdy; + tru_data_out[16:0] = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_out_pvld^tru_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_ICVT_pipe_p6 diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_ocvt.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_ocvt.v new file mode 100644 index 0000000..bd64b42 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_ocvt.v @@ -0,0 +1,1698 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_HLS_ocvt.v +module NV_NVDLA_CDP_HLS_ocvt ( + cfg_alu_in //|< i + ,cfg_mul_in //|< i + ,cfg_precision //|< i + ,cfg_truncate //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_out_pvld //|> o + ); +input [31:0] cfg_alu_in; +input [15:0] cfg_mul_in; +input [1:0] cfg_precision; +input [5:0] cfg_truncate; +input [49:0] chn_data_in; +input chn_in_pvld; +input chn_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [17:0] chn_data_out; +output chn_in_prdy; +output chn_out_pvld; +wire [25:0] cfg_alu_ext; +wire [33:0] chn_alu_ext; +wire [33:0] chn_data_ext; +wire [24:0] chn_data_lsb; +wire [24:0] chn_data_msb; +wire [32:0] chn_data_tmp; +wire [17:0] chn_dout; +wire [15:0] chn_int16_dout; +wire chn_int16_prdy; +wire chn_int16_pvld; +wire [1:0] chn_int16_sat; +wire [15:0] chn_int8_dout; +wire chn_int8_prdy; +wire chn_int8_pvld; +wire [1:0] chn_int8_sat; +wire [25:0] data_lsb_ext; +wire [25:0] data_msb_ext; +wire mon_sub_c; +wire mon_sub_lc; +wire mon_sub_mc; +wire [49:0] mul_data_out; +wire [49:0] mul_dout; +wire [41:0] mul_lsb_data_out; +wire [41:0] mul_lsb_dout; +wire [41:0] mul_msb_data_out; +wire [41:0] mul_msb_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire mul_outh_prdy; +wire mul_outh_pvld; +wire sat_data_out; +wire sat_dout; +wire [1:0] sat_int8_data_out; +wire [1:0] sat_int8_dout; +wire sat_lsb_dout; +wire sat_msb_dout; +wire [33:0] sub_data_out; +wire [33:0] sub_dout; +wire [25:0] sub_lsb_data_out; +wire [25:0] sub_lsb_dout; +wire [25:0] sub_msb_data_out; +wire [25:0] sub_msb_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire sub_outh_prdy; +wire sub_outh_pvld; +wire [15:0] tru_data_out; +wire [15:0] tru_dout; +wire tru_final_prdy; +wire tru_final_pvld; +wire [15:0] tru_int8_data_out; +wire [15:0] tru_int8_dout; +wire [7:0] tru_lsb_dout; +wire [7:0] tru_msb_dout; +wire tru_out_prdy; +wire tru_out_pvld; +wire tru_outh_prdy; +wire tru_outh_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//int8 cvt +assign chn_data_lsb[24:0] = chn_data_in[24:0]; +assign chn_data_msb[24:0] = chn_data_in[49:25]; +assign data_lsb_ext[25:0] = {{1{chn_data_lsb[24]}}, chn_data_lsb[24:0]}; +assign data_msb_ext[25:0] = {{1{chn_data_msb[24]}}, chn_data_msb[24:0]}; +assign cfg_alu_ext[25:0] = {{1{cfg_alu_in[24]}}, cfg_alu_in[24:0]}; +//sub +assign {mon_sub_lc,sub_lsb_dout[25:0]} = $signed(data_lsb_ext[25:0]) -$signed(cfg_alu_ext[25:0]); +assign {mon_sub_mc,sub_msb_dout[25:0]} = $signed(data_msb_ext[25:0]) -$signed(cfg_alu_ext[25:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int8_pvld (chn_int8_pvld) //|< w + ,.sub_lsb_dout (sub_lsb_dout[25:0]) //|< w + ,.sub_msb_dout (sub_msb_dout[25:0]) //|< w + ,.sub_outh_prdy (sub_outh_prdy) //|< w + ,.chn_int8_prdy (chn_int8_prdy) //|> w + ,.sub_lsb_data_out (sub_lsb_data_out[25:0]) //|> w + ,.sub_msb_data_out (sub_msb_data_out[25:0]) //|> w + ,.sub_outh_pvld (sub_outh_pvld) //|> w + ); +//mul +assign mul_lsb_dout[41:0] = $signed(sub_lsb_data_out[25:0]) * $signed(cfg_mul_in[15:0]); +assign mul_msb_dout[41:0] = $signed(sub_msb_data_out[25:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_lsb_dout (mul_lsb_dout[41:0]) //|< w + ,.mul_msb_dout (mul_msb_dout[41:0]) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|< w + ,.sub_outh_pvld (sub_outh_pvld) //|< w + ,.mul_lsb_data_out (mul_lsb_data_out[41:0]) //|> w + ,.mul_msb_data_out (mul_msb_data_out[41:0]) //|> w + ,.mul_outh_pvld (mul_outh_pvld) //|> w + ,.sub_outh_prdy (sub_outh_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(16 + 26 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(6 )) shiftrightsat_su_lsb ( + .data_in (mul_lsb_data_out[41:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_lsb_dout[7:0]) //|> w + ,.sat_out (sat_lsb_dout) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(16 + 26 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(6 )) shiftrightsat_su_msb ( + .data_in (mul_msb_data_out[41:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_msb_dout[7:0]) //|> w + ,.sat_out (sat_msb_dout) //|> w + ); +//signed +//unsigned +assign tru_int8_dout[15:0] = {tru_msb_dout[7:0],tru_lsb_dout[7:0]}; +assign sat_int8_dout[1:0] = {sat_msb_dout,sat_lsb_dout}; +NV_NVDLA_CDP_HLS_OCVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_outh_pvld (mul_outh_pvld) //|< w + ,.sat_int8_dout (sat_int8_dout[1:0]) //|< w + ,.tru_int8_dout (tru_int8_dout[15:0]) //|< w + ,.tru_outh_prdy (tru_outh_prdy) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|> w + ,.sat_int8_data_out (sat_int8_data_out[1:0]) //|> w + ,.tru_int8_data_out (tru_int8_data_out[15:0]) //|> w + ,.tru_outh_pvld (tru_outh_pvld) //|> w + ); +assign chn_int8_dout[15:0] = tru_int8_data_out[15:0]; +assign chn_int8_sat[1:0] = sat_int8_data_out[1:0]; +/////////int16 covert +assign chn_data_tmp[32:0] = chn_data_in[32:0]; +assign chn_data_ext[33:0] = {{1{chn_data_tmp[32]}}, chn_data_tmp[32:0]}; +assign chn_alu_ext[33:0] = {{2{cfg_alu_in[31]}}, cfg_alu_in[31:0]}; +//sub +assign {mon_sub_c,sub_dout[33:0]} = $signed(chn_data_ext[33:0]) -$signed(chn_alu_ext[33:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int16_pvld (chn_int16_pvld) //|< w + ,.sub_dout (sub_dout[33:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_int16_prdy (chn_int16_prdy) //|> w + ,.sub_data_out (sub_data_out[33:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[49:0] = $signed(sub_data_out[33:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[49:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[49:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(16 + 34 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(6 )) shiftrightsat_su ( + .data_in (mul_data_out[49:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_dout[15:0]) //|> w + ,.sat_out (sat_dout) //|> w + ); +//signed +//unsigned +NV_NVDLA_CDP_HLS_OCVT_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.sat_dout (sat_dout) //|< w + ,.tru_dout (tru_dout[15:0]) //|< w + ,.tru_out_prdy (tru_out_prdy) //|< w + ,.mul_out_prdy (mul_out_prdy) //|> w + ,.sat_data_out (sat_data_out) //|> w + ,.tru_data_out (tru_data_out[15:0]) //|> w + ,.tru_out_pvld (tru_out_pvld) //|> w + ); +assign chn_int16_dout[15:0] = tru_data_out; +assign chn_int16_sat[1:0] = {1'b0,sat_data_out}; +//mux int16 and int8 final data out +assign chn_in_prdy = (cfg_precision[1:0] == 1 ) ? chn_int16_prdy : chn_int8_prdy; +assign chn_int8_pvld = (cfg_precision[1:0] == 1 ) ? 1'b0 : chn_in_pvld; +assign chn_int16_pvld = (cfg_precision[1:0] == 1 ) ? chn_in_pvld : 1'b0; +assign tru_final_pvld = (cfg_precision[1:0] == 1 ) ? tru_out_pvld : tru_outh_pvld; +assign tru_out_prdy = (cfg_precision[1:0] == 1 ) ? tru_final_prdy : 1'b1; +assign tru_outh_prdy = (cfg_precision[1:0] == 1 ) ? 1'b1: tru_final_prdy; +assign chn_dout[17:0] = (cfg_precision[1:0] == 1 ) ? {chn_int16_sat[1:0],chn_int16_dout[15:0]} : {chn_int8_sat[1:0],chn_int8_dout[15:0]}; +NV_NVDLA_CDP_HLS_OCVT_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_dout (chn_dout[17:0]) //|< w + ,.chn_out_prdy (chn_out_prdy) //|< i + ,.tru_final_pvld (tru_final_pvld) //|< w + ,.chn_data_out (chn_data_out[17:0]) //|> o + ,.chn_out_pvld (chn_out_pvld) //|> o + ,.tru_final_prdy (tru_final_prdy) //|> w + ); +endmodule // NV_NVDLA_CDP_HLS_ocvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sub_msb_data_out[25:0],sub_lsb_data_out[25:0]} (sub_outh_pvld,sub_outh_prdy) <= {sub_msb_dout[25:0],sub_lsb_dout[25:0]} (chn_int8_pvld,chn_int8_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int8_pvld + ,sub_lsb_dout + ,sub_msb_dout + ,sub_outh_prdy + ,chn_int8_prdy + ,sub_lsb_data_out + ,sub_msb_data_out + ,sub_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int8_pvld; +input [25:0] sub_lsb_dout; +input [25:0] sub_msb_dout; +input sub_outh_prdy; +output chn_int8_prdy; +output [25:0] sub_lsb_data_out; +output [25:0] sub_msb_data_out; +output sub_outh_pvld; +reg chn_int8_prdy; +reg [51:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [51:0] p1_skid_data; +reg [51:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [25:0] sub_lsb_data_out; +reg [25:0] sub_msb_data_out; +reg sub_outh_pvld; +//## pipe (1) skid buffer +always @( + chn_int8_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_int8_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_int8_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_int8_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {sub_msb_dout[25:0],sub_lsb_dout[25:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_int8_pvld + or p1_skid_valid + or sub_msb_dout + or sub_lsb_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_int8_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {sub_msb_dout[25:0],sub_lsb_dout[25:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_outh_prdy + or p1_pipe_data + ) begin + sub_outh_pvld = p1_pipe_valid; + p1_pipe_ready = sub_outh_prdy; + {sub_msb_data_out[25:0],sub_lsb_data_out[25:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_outh_pvld^sub_outh_prdy^chn_int8_pvld^chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_int8_pvld && !chn_int8_prdy), (chn_int8_pvld), (chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_msb_data_out[41:0],mul_lsb_data_out[41:0]} (mul_outh_pvld,mul_outh_prdy) <= {mul_msb_dout[41:0],mul_lsb_dout[41:0]} (sub_outh_pvld,sub_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_lsb_dout + ,mul_msb_dout + ,mul_outh_prdy + ,sub_outh_pvld + ,mul_lsb_data_out + ,mul_msb_data_out + ,mul_outh_pvld + ,sub_outh_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [41:0] mul_lsb_dout; +input [41:0] mul_msb_dout; +input mul_outh_prdy; +input sub_outh_pvld; +output [41:0] mul_lsb_data_out; +output [41:0] mul_msb_data_out; +output mul_outh_pvld; +output sub_outh_prdy; +reg [41:0] mul_lsb_data_out; +reg [41:0] mul_msb_data_out; +reg mul_outh_pvld; +reg [83:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [83:0] p2_skid_data; +reg [83:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_outh_prdy; +//## pipe (2) skid buffer +always @( + sub_outh_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_outh_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_outh_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_outh_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {mul_msb_dout[41:0],mul_lsb_dout[41:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_outh_pvld + or p2_skid_valid + or mul_msb_dout + or mul_lsb_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_outh_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {mul_msb_dout[41:0],mul_lsb_dout[41:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_outh_prdy + or p2_pipe_data + ) begin + mul_outh_pvld = p2_pipe_valid; + p2_pipe_ready = mul_outh_prdy; + {mul_msb_data_out[41:0],mul_lsb_data_out[41:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_outh_pvld^mul_outh_prdy^sub_outh_pvld^sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_outh_pvld && !sub_outh_prdy), (sub_outh_pvld), (sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sat_int8_data_out[1:0],tru_int8_data_out[15:0]} (tru_outh_pvld,tru_outh_prdy) <= {sat_int8_dout[1:0],tru_int8_dout[15:0]} (mul_outh_pvld,mul_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_outh_pvld + ,sat_int8_dout + ,tru_int8_dout + ,tru_outh_prdy + ,mul_outh_prdy + ,sat_int8_data_out + ,tru_int8_data_out + ,tru_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_outh_pvld; +input [1:0] sat_int8_dout; +input [15:0] tru_int8_dout; +input tru_outh_prdy; +output mul_outh_prdy; +output [1:0] sat_int8_data_out; +output [15:0] tru_int8_data_out; +output tru_outh_pvld; +reg mul_outh_prdy; +reg [17:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [17:0] p3_skid_data; +reg [17:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg [1:0] sat_int8_data_out; +reg [15:0] tru_int8_data_out; +reg tru_outh_pvld; +//## pipe (3) skid buffer +always @( + mul_outh_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_outh_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_outh_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_outh_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {sat_int8_dout[1:0],tru_int8_dout[15:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_outh_pvld + or p3_skid_valid + or sat_int8_dout + or tru_int8_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_outh_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {sat_int8_dout[1:0],tru_int8_dout[15:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tru_outh_prdy + or p3_pipe_data + ) begin + tru_outh_pvld = p3_pipe_valid; + p3_pipe_ready = tru_outh_prdy; + {sat_int8_data_out[1:0],tru_int8_data_out[15:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_outh_pvld^tru_outh_prdy^mul_outh_pvld^mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_outh_pvld && !mul_outh_prdy), (mul_outh_pvld), (mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[33:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[33:0] (chn_int16_pvld,chn_int16_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int16_pvld + ,sub_dout + ,sub_out_prdy + ,chn_int16_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int16_pvld; +input [33:0] sub_dout; +input sub_out_prdy; +output chn_int16_prdy; +output [33:0] sub_data_out; +output sub_out_pvld; +reg chn_int16_prdy; +reg [33:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [33:0] p4_skid_data; +reg [33:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +reg [33:0] sub_data_out; +reg sub_out_pvld; +//## pipe (4) skid buffer +always @( + chn_int16_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = chn_int16_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + chn_int16_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + chn_int16_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? sub_dout[33:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or chn_int16_pvld + or p4_skid_valid + or sub_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? chn_int16_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? sub_dout[33:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or sub_out_prdy + or p4_pipe_data + ) begin + sub_out_pvld = p4_pipe_valid; + p4_pipe_ready = sub_out_prdy; + sub_data_out[33:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_int16_pvld^chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (chn_int16_pvld && !chn_int16_prdy), (chn_int16_pvld), (chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[49:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[49:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [49:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [49:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [49:0] mul_data_out; +reg mul_out_pvld; +reg [49:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [49:0] p5_skid_data; +reg [49:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +reg sub_out_prdy; +//## pipe (5) skid buffer +always @( + sub_out_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = sub_out_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + sub_out_prdy <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? mul_dout[49:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or sub_out_pvld + or p5_skid_valid + or mul_dout + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? sub_out_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? mul_dout[49:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mul_out_prdy + or p5_pipe_data + ) begin + mul_out_pvld = p5_pipe_valid; + p5_pipe_ready = mul_out_prdy; + mul_data_out[49:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sat_data_out,tru_data_out[15:0]} (tru_out_pvld,tru_out_prdy) <= {sat_dout,tru_dout[15:0]} (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,sat_dout + ,tru_dout + ,tru_out_prdy + ,mul_out_prdy + ,sat_data_out + ,tru_data_out + ,tru_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input sat_dout; +input [15:0] tru_dout; +input tru_out_prdy; +output mul_out_prdy; +output sat_data_out; +output [15:0] tru_data_out; +output tru_out_pvld; +reg mul_out_prdy; +reg [16:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg p6_skid_catch; +reg [16:0] p6_skid_data; +reg [16:0] p6_skid_pipe_data; +reg p6_skid_pipe_ready; +reg p6_skid_pipe_valid; +reg p6_skid_ready; +reg p6_skid_ready_flop; +reg p6_skid_valid; +reg sat_data_out; +reg [15:0] tru_data_out; +reg tru_out_pvld; +//## pipe (6) skid buffer +always @( + mul_out_pvld + or p6_skid_ready_flop + or p6_skid_pipe_ready + or p6_skid_valid + ) begin + p6_skid_catch = mul_out_pvld && p6_skid_ready_flop && !p6_skid_pipe_ready; + p6_skid_ready = (p6_skid_valid)? p6_skid_pipe_ready : !p6_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_skid_valid <= 1'b0; + p6_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p6_skid_valid <= (p6_skid_valid)? !p6_skid_pipe_ready : p6_skid_catch; + p6_skid_ready_flop <= p6_skid_ready; + mul_out_prdy <= p6_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_skid_data <= (p6_skid_catch)? {sat_dout,tru_dout[15:0]} : p6_skid_data; +// VCS sop_coverage_off end +end +always @( + p6_skid_ready_flop + or mul_out_pvld + or p6_skid_valid + or sat_dout + or tru_dout + or p6_skid_data + ) begin + p6_skid_pipe_valid = (p6_skid_ready_flop)? mul_out_pvld : p6_skid_valid; +// VCS sop_coverage_off start + p6_skid_pipe_data = (p6_skid_ready_flop)? {sat_dout,tru_dout[15:0]} : p6_skid_data; +// VCS sop_coverage_off end +end +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? p6_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && p6_skid_pipe_valid)? p6_skid_pipe_data : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + p6_skid_pipe_ready = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or tru_out_prdy + or p6_pipe_data + ) begin + tru_out_pvld = p6_pipe_valid; + p6_pipe_ready = tru_out_prdy; + {sat_data_out,tru_data_out[15:0]} = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_out_pvld^tru_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[17:0] (chn_out_pvld,chn_out_prdy) <= chn_dout[17:0] (tru_final_pvld,tru_final_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_dout + ,chn_out_prdy + ,tru_final_pvld + ,chn_data_out + ,chn_out_pvld + ,tru_final_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [17:0] chn_dout; +input chn_out_prdy; +input tru_final_pvld; +output [17:0] chn_data_out; +output chn_out_pvld; +output tru_final_prdy; +reg [17:0] chn_data_out; +reg chn_out_pvld; +reg [17:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +reg p7_skid_catch; +reg [17:0] p7_skid_data; +reg [17:0] p7_skid_pipe_data; +reg p7_skid_pipe_ready; +reg p7_skid_pipe_valid; +reg p7_skid_ready; +reg p7_skid_ready_flop; +reg p7_skid_valid; +reg tru_final_prdy; +//## pipe (7) skid buffer +always @( + tru_final_pvld + or p7_skid_ready_flop + or p7_skid_pipe_ready + or p7_skid_valid + ) begin + p7_skid_catch = tru_final_pvld && p7_skid_ready_flop && !p7_skid_pipe_ready; + p7_skid_ready = (p7_skid_valid)? p7_skid_pipe_ready : !p7_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_skid_valid <= 1'b0; + p7_skid_ready_flop <= 1'b1; + tru_final_prdy <= 1'b1; + end else begin + p7_skid_valid <= (p7_skid_valid)? !p7_skid_pipe_ready : p7_skid_catch; + p7_skid_ready_flop <= p7_skid_ready; + tru_final_prdy <= p7_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_skid_data <= (p7_skid_catch)? chn_dout[17:0] : p7_skid_data; +// VCS sop_coverage_off end +end +always @( + p7_skid_ready_flop + or tru_final_pvld + or p7_skid_valid + or chn_dout + or p7_skid_data + ) begin + p7_skid_pipe_valid = (p7_skid_ready_flop)? tru_final_pvld : p7_skid_valid; +// VCS sop_coverage_off start + p7_skid_pipe_data = (p7_skid_ready_flop)? chn_dout[17:0] : p7_skid_data; +// VCS sop_coverage_off end +end +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? p7_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && p7_skid_pipe_valid)? p7_skid_pipe_data : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + p7_skid_pipe_ready = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or chn_out_prdy + or p7_pipe_data + ) begin + chn_out_pvld = p7_pipe_valid; + p7_pipe_ready = chn_out_prdy; + chn_data_out[17:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^tru_final_pvld^tru_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (tru_final_pvld && !tru_final_prdy), (tru_final_pvld), (tru_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p7 diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_ocvt.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_ocvt.v.vcp new file mode 100644 index 0000000..bd64b42 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_CDP_HLS_ocvt.v.vcp @@ -0,0 +1,1698 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_CDP_HLS_ocvt.v +module NV_NVDLA_CDP_HLS_ocvt ( + cfg_alu_in //|< i + ,cfg_mul_in //|< i + ,cfg_precision //|< i + ,cfg_truncate //|< i + ,chn_data_in //|< i + ,chn_in_pvld //|< i + ,chn_out_prdy //|< i + ,nvdla_core_clk //|< i + ,nvdla_core_rstn //|< i + ,chn_data_out //|> o + ,chn_in_prdy //|> o + ,chn_out_pvld //|> o + ); +input [31:0] cfg_alu_in; +input [15:0] cfg_mul_in; +input [1:0] cfg_precision; +input [5:0] cfg_truncate; +input [49:0] chn_data_in; +input chn_in_pvld; +input chn_out_prdy; +input nvdla_core_clk; +input nvdla_core_rstn; +output [17:0] chn_data_out; +output chn_in_prdy; +output chn_out_pvld; +wire [25:0] cfg_alu_ext; +wire [33:0] chn_alu_ext; +wire [33:0] chn_data_ext; +wire [24:0] chn_data_lsb; +wire [24:0] chn_data_msb; +wire [32:0] chn_data_tmp; +wire [17:0] chn_dout; +wire [15:0] chn_int16_dout; +wire chn_int16_prdy; +wire chn_int16_pvld; +wire [1:0] chn_int16_sat; +wire [15:0] chn_int8_dout; +wire chn_int8_prdy; +wire chn_int8_pvld; +wire [1:0] chn_int8_sat; +wire [25:0] data_lsb_ext; +wire [25:0] data_msb_ext; +wire mon_sub_c; +wire mon_sub_lc; +wire mon_sub_mc; +wire [49:0] mul_data_out; +wire [49:0] mul_dout; +wire [41:0] mul_lsb_data_out; +wire [41:0] mul_lsb_dout; +wire [41:0] mul_msb_data_out; +wire [41:0] mul_msb_dout; +wire mul_out_prdy; +wire mul_out_pvld; +wire mul_outh_prdy; +wire mul_outh_pvld; +wire sat_data_out; +wire sat_dout; +wire [1:0] sat_int8_data_out; +wire [1:0] sat_int8_dout; +wire sat_lsb_dout; +wire sat_msb_dout; +wire [33:0] sub_data_out; +wire [33:0] sub_dout; +wire [25:0] sub_lsb_data_out; +wire [25:0] sub_lsb_dout; +wire [25:0] sub_msb_data_out; +wire [25:0] sub_msb_dout; +wire sub_out_prdy; +wire sub_out_pvld; +wire sub_outh_prdy; +wire sub_outh_pvld; +wire [15:0] tru_data_out; +wire [15:0] tru_dout; +wire tru_final_prdy; +wire tru_final_pvld; +wire [15:0] tru_int8_data_out; +wire [15:0] tru_int8_dout; +wire [7:0] tru_lsb_dout; +wire [7:0] tru_msb_dout; +wire tru_out_prdy; +wire tru_out_pvld; +wire tru_outh_prdy; +wire tru_outh_pvld; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//int8 cvt +assign chn_data_lsb[24:0] = chn_data_in[24:0]; +assign chn_data_msb[24:0] = chn_data_in[49:25]; +assign data_lsb_ext[25:0] = {{1{chn_data_lsb[24]}}, chn_data_lsb[24:0]}; +assign data_msb_ext[25:0] = {{1{chn_data_msb[24]}}, chn_data_msb[24:0]}; +assign cfg_alu_ext[25:0] = {{1{cfg_alu_in[24]}}, cfg_alu_in[24:0]}; +//sub +assign {mon_sub_lc,sub_lsb_dout[25:0]} = $signed(data_lsb_ext[25:0]) -$signed(cfg_alu_ext[25:0]); +assign {mon_sub_mc,sub_msb_dout[25:0]} = $signed(data_msb_ext[25:0]) -$signed(cfg_alu_ext[25:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p1 pipe_p1 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int8_pvld (chn_int8_pvld) //|< w + ,.sub_lsb_dout (sub_lsb_dout[25:0]) //|< w + ,.sub_msb_dout (sub_msb_dout[25:0]) //|< w + ,.sub_outh_prdy (sub_outh_prdy) //|< w + ,.chn_int8_prdy (chn_int8_prdy) //|> w + ,.sub_lsb_data_out (sub_lsb_data_out[25:0]) //|> w + ,.sub_msb_data_out (sub_msb_data_out[25:0]) //|> w + ,.sub_outh_pvld (sub_outh_pvld) //|> w + ); +//mul +assign mul_lsb_dout[41:0] = $signed(sub_lsb_data_out[25:0]) * $signed(cfg_mul_in[15:0]); +assign mul_msb_dout[41:0] = $signed(sub_msb_data_out[25:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p2 pipe_p2 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_lsb_dout (mul_lsb_dout[41:0]) //|< w + ,.mul_msb_dout (mul_msb_dout[41:0]) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|< w + ,.sub_outh_pvld (sub_outh_pvld) //|< w + ,.mul_lsb_data_out (mul_lsb_data_out[41:0]) //|> w + ,.mul_msb_data_out (mul_msb_data_out[41:0]) //|> w + ,.mul_outh_pvld (mul_outh_pvld) //|> w + ,.sub_outh_prdy (sub_outh_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(16 + 26 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(6 )) shiftrightsat_su_lsb ( + .data_in (mul_lsb_data_out[41:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_lsb_dout[7:0]) //|> w + ,.sat_out (sat_lsb_dout) //|> w + ); +//signed +//unsigned +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(16 + 26 ),.OUT_WIDTH(8 ),.SHIFT_WIDTH(6 )) shiftrightsat_su_msb ( + .data_in (mul_msb_data_out[41:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_msb_dout[7:0]) //|> w + ,.sat_out (sat_msb_dout) //|> w + ); +//signed +//unsigned +assign tru_int8_dout[15:0] = {tru_msb_dout[7:0],tru_lsb_dout[7:0]}; +assign sat_int8_dout[1:0] = {sat_msb_dout,sat_lsb_dout}; +NV_NVDLA_CDP_HLS_OCVT_pipe_p3 pipe_p3 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_outh_pvld (mul_outh_pvld) //|< w + ,.sat_int8_dout (sat_int8_dout[1:0]) //|< w + ,.tru_int8_dout (tru_int8_dout[15:0]) //|< w + ,.tru_outh_prdy (tru_outh_prdy) //|< w + ,.mul_outh_prdy (mul_outh_prdy) //|> w + ,.sat_int8_data_out (sat_int8_data_out[1:0]) //|> w + ,.tru_int8_data_out (tru_int8_data_out[15:0]) //|> w + ,.tru_outh_pvld (tru_outh_pvld) //|> w + ); +assign chn_int8_dout[15:0] = tru_int8_data_out[15:0]; +assign chn_int8_sat[1:0] = sat_int8_data_out[1:0]; +/////////int16 covert +assign chn_data_tmp[32:0] = chn_data_in[32:0]; +assign chn_data_ext[33:0] = {{1{chn_data_tmp[32]}}, chn_data_tmp[32:0]}; +assign chn_alu_ext[33:0] = {{2{cfg_alu_in[31]}}, cfg_alu_in[31:0]}; +//sub +assign {mon_sub_c,sub_dout[33:0]} = $signed(chn_data_ext[33:0]) -$signed(chn_alu_ext[33:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p4 pipe_p4 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_int16_pvld (chn_int16_pvld) //|< w + ,.sub_dout (sub_dout[33:0]) //|< w + ,.sub_out_prdy (sub_out_prdy) //|< w + ,.chn_int16_prdy (chn_int16_prdy) //|> w + ,.sub_data_out (sub_data_out[33:0]) //|> w + ,.sub_out_pvld (sub_out_pvld) //|> w + ); +//mul +assign mul_dout[49:0] = $signed(sub_data_out[33:0]) * $signed(cfg_mul_in[15:0]); +NV_NVDLA_CDP_HLS_OCVT_pipe_p5 pipe_p5 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_dout (mul_dout[49:0]) //|< w + ,.mul_out_prdy (mul_out_prdy) //|< w + ,.sub_out_pvld (sub_out_pvld) //|< w + ,.mul_data_out (mul_data_out[49:0]) //|> w + ,.mul_out_pvld (mul_out_pvld) //|> w + ,.sub_out_prdy (sub_out_prdy) //|> w + ); +//truncate +NV_NVDLA_HLS_shiftrightsatsu #(.IN_WIDTH(16 + 34 ),.OUT_WIDTH(16 ),.SHIFT_WIDTH(6 )) shiftrightsat_su ( + .data_in (mul_data_out[49:0]) //|< w + ,.shift_num (cfg_truncate[5:0]) //|< i + ,.data_out (tru_dout[15:0]) //|> w + ,.sat_out (sat_dout) //|> w + ); +//signed +//unsigned +NV_NVDLA_CDP_HLS_OCVT_pipe_p6 pipe_p6 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.mul_out_pvld (mul_out_pvld) //|< w + ,.sat_dout (sat_dout) //|< w + ,.tru_dout (tru_dout[15:0]) //|< w + ,.tru_out_prdy (tru_out_prdy) //|< w + ,.mul_out_prdy (mul_out_prdy) //|> w + ,.sat_data_out (sat_data_out) //|> w + ,.tru_data_out (tru_data_out[15:0]) //|> w + ,.tru_out_pvld (tru_out_pvld) //|> w + ); +assign chn_int16_dout[15:0] = tru_data_out; +assign chn_int16_sat[1:0] = {1'b0,sat_data_out}; +//mux int16 and int8 final data out +assign chn_in_prdy = (cfg_precision[1:0] == 1 ) ? chn_int16_prdy : chn_int8_prdy; +assign chn_int8_pvld = (cfg_precision[1:0] == 1 ) ? 1'b0 : chn_in_pvld; +assign chn_int16_pvld = (cfg_precision[1:0] == 1 ) ? chn_in_pvld : 1'b0; +assign tru_final_pvld = (cfg_precision[1:0] == 1 ) ? tru_out_pvld : tru_outh_pvld; +assign tru_out_prdy = (cfg_precision[1:0] == 1 ) ? tru_final_prdy : 1'b1; +assign tru_outh_prdy = (cfg_precision[1:0] == 1 ) ? 1'b1: tru_final_prdy; +assign chn_dout[17:0] = (cfg_precision[1:0] == 1 ) ? {chn_int16_sat[1:0],chn_int16_dout[15:0]} : {chn_int8_sat[1:0],chn_int8_dout[15:0]}; +NV_NVDLA_CDP_HLS_OCVT_pipe_p7 pipe_p7 ( + .nvdla_core_clk (nvdla_core_clk) //|< i + ,.nvdla_core_rstn (nvdla_core_rstn) //|< i + ,.chn_dout (chn_dout[17:0]) //|< w + ,.chn_out_prdy (chn_out_prdy) //|< i + ,.tru_final_pvld (tru_final_pvld) //|< w + ,.chn_data_out (chn_data_out[17:0]) //|> o + ,.chn_out_pvld (chn_out_pvld) //|> o + ,.tru_final_prdy (tru_final_prdy) //|> w + ); +endmodule // NV_NVDLA_CDP_HLS_ocvt +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sub_msb_data_out[25:0],sub_lsb_data_out[25:0]} (sub_outh_pvld,sub_outh_prdy) <= {sub_msb_dout[25:0],sub_lsb_dout[25:0]} (chn_int8_pvld,chn_int8_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p1 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int8_pvld + ,sub_lsb_dout + ,sub_msb_dout + ,sub_outh_prdy + ,chn_int8_prdy + ,sub_lsb_data_out + ,sub_msb_data_out + ,sub_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int8_pvld; +input [25:0] sub_lsb_dout; +input [25:0] sub_msb_dout; +input sub_outh_prdy; +output chn_int8_prdy; +output [25:0] sub_lsb_data_out; +output [25:0] sub_msb_data_out; +output sub_outh_pvld; +reg chn_int8_prdy; +reg [51:0] p1_pipe_data; +reg p1_pipe_ready; +reg p1_pipe_ready_bc; +reg p1_pipe_valid; +reg p1_skid_catch; +reg [51:0] p1_skid_data; +reg [51:0] p1_skid_pipe_data; +reg p1_skid_pipe_ready; +reg p1_skid_pipe_valid; +reg p1_skid_ready; +reg p1_skid_ready_flop; +reg p1_skid_valid; +reg [25:0] sub_lsb_data_out; +reg [25:0] sub_msb_data_out; +reg sub_outh_pvld; +//## pipe (1) skid buffer +always @( + chn_int8_pvld + or p1_skid_ready_flop + or p1_skid_pipe_ready + or p1_skid_valid + ) begin + p1_skid_catch = chn_int8_pvld && p1_skid_ready_flop && !p1_skid_pipe_ready; + p1_skid_ready = (p1_skid_valid)? p1_skid_pipe_ready : !p1_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_skid_valid <= 1'b0; + p1_skid_ready_flop <= 1'b1; + chn_int8_prdy <= 1'b1; + end else begin + p1_skid_valid <= (p1_skid_valid)? !p1_skid_pipe_ready : p1_skid_catch; + p1_skid_ready_flop <= p1_skid_ready; + chn_int8_prdy <= p1_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_skid_data <= (p1_skid_catch)? {sub_msb_dout[25:0],sub_lsb_dout[25:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +always @( + p1_skid_ready_flop + or chn_int8_pvld + or p1_skid_valid + or sub_msb_dout + or sub_lsb_dout + or p1_skid_data + ) begin + p1_skid_pipe_valid = (p1_skid_ready_flop)? chn_int8_pvld : p1_skid_valid; +// VCS sop_coverage_off start + p1_skid_pipe_data = (p1_skid_ready_flop)? {sub_msb_dout[25:0],sub_lsb_dout[25:0]} : p1_skid_data; +// VCS sop_coverage_off end +end +//## pipe (1) valid-ready-bubble-collapse +always @( + p1_pipe_ready + or p1_pipe_valid + ) begin + p1_pipe_ready_bc = p1_pipe_ready || !p1_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p1_pipe_valid <= 1'b0; + end else begin + p1_pipe_valid <= (p1_pipe_ready_bc)? p1_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p1_pipe_data <= (p1_pipe_ready_bc && p1_skid_pipe_valid)? p1_skid_pipe_data : p1_pipe_data; +// VCS sop_coverage_off end +end +always @( + p1_pipe_ready_bc + ) begin + p1_skid_pipe_ready = p1_pipe_ready_bc; +end +//## pipe (1) output +always @( + p1_pipe_valid + or sub_outh_prdy + or p1_pipe_data + ) begin + sub_outh_pvld = p1_pipe_valid; + p1_pipe_ready = sub_outh_prdy; + {sub_msb_data_out[25:0],sub_lsb_data_out[25:0]} = p1_pipe_data; +end +//## pipe (1) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p1_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_1x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_outh_pvld^sub_outh_prdy^chn_int8_pvld^chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_2x (nvdla_core_clk, `ASSERT_RESET, (chn_int8_pvld && !chn_int8_prdy), (chn_int8_pvld), (chn_int8_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p1 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {mul_msb_data_out[41:0],mul_lsb_data_out[41:0]} (mul_outh_pvld,mul_outh_prdy) <= {mul_msb_dout[41:0],mul_lsb_dout[41:0]} (sub_outh_pvld,sub_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p2 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_lsb_dout + ,mul_msb_dout + ,mul_outh_prdy + ,sub_outh_pvld + ,mul_lsb_data_out + ,mul_msb_data_out + ,mul_outh_pvld + ,sub_outh_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [41:0] mul_lsb_dout; +input [41:0] mul_msb_dout; +input mul_outh_prdy; +input sub_outh_pvld; +output [41:0] mul_lsb_data_out; +output [41:0] mul_msb_data_out; +output mul_outh_pvld; +output sub_outh_prdy; +reg [41:0] mul_lsb_data_out; +reg [41:0] mul_msb_data_out; +reg mul_outh_pvld; +reg [83:0] p2_pipe_data; +reg p2_pipe_ready; +reg p2_pipe_ready_bc; +reg p2_pipe_valid; +reg p2_skid_catch; +reg [83:0] p2_skid_data; +reg [83:0] p2_skid_pipe_data; +reg p2_skid_pipe_ready; +reg p2_skid_pipe_valid; +reg p2_skid_ready; +reg p2_skid_ready_flop; +reg p2_skid_valid; +reg sub_outh_prdy; +//## pipe (2) skid buffer +always @( + sub_outh_pvld + or p2_skid_ready_flop + or p2_skid_pipe_ready + or p2_skid_valid + ) begin + p2_skid_catch = sub_outh_pvld && p2_skid_ready_flop && !p2_skid_pipe_ready; + p2_skid_ready = (p2_skid_valid)? p2_skid_pipe_ready : !p2_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_skid_valid <= 1'b0; + p2_skid_ready_flop <= 1'b1; + sub_outh_prdy <= 1'b1; + end else begin + p2_skid_valid <= (p2_skid_valid)? !p2_skid_pipe_ready : p2_skid_catch; + p2_skid_ready_flop <= p2_skid_ready; + sub_outh_prdy <= p2_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_skid_data <= (p2_skid_catch)? {mul_msb_dout[41:0],mul_lsb_dout[41:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +always @( + p2_skid_ready_flop + or sub_outh_pvld + or p2_skid_valid + or mul_msb_dout + or mul_lsb_dout + or p2_skid_data + ) begin + p2_skid_pipe_valid = (p2_skid_ready_flop)? sub_outh_pvld : p2_skid_valid; +// VCS sop_coverage_off start + p2_skid_pipe_data = (p2_skid_ready_flop)? {mul_msb_dout[41:0],mul_lsb_dout[41:0]} : p2_skid_data; +// VCS sop_coverage_off end +end +//## pipe (2) valid-ready-bubble-collapse +always @( + p2_pipe_ready + or p2_pipe_valid + ) begin + p2_pipe_ready_bc = p2_pipe_ready || !p2_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p2_pipe_valid <= 1'b0; + end else begin + p2_pipe_valid <= (p2_pipe_ready_bc)? p2_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p2_pipe_data <= (p2_pipe_ready_bc && p2_skid_pipe_valid)? p2_skid_pipe_data : p2_pipe_data; +// VCS sop_coverage_off end +end +always @( + p2_pipe_ready_bc + ) begin + p2_skid_pipe_ready = p2_pipe_ready_bc; +end +//## pipe (2) output +always @( + p2_pipe_valid + or mul_outh_prdy + or p2_pipe_data + ) begin + mul_outh_pvld = p2_pipe_valid; + p2_pipe_ready = mul_outh_prdy; + {mul_msb_data_out[41:0],mul_lsb_data_out[41:0]} = p2_pipe_data; +end +//## pipe (2) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p2_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_3x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_outh_pvld^mul_outh_prdy^sub_outh_pvld^sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_4x (nvdla_core_clk, `ASSERT_RESET, (sub_outh_pvld && !sub_outh_prdy), (sub_outh_pvld), (sub_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p2 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sat_int8_data_out[1:0],tru_int8_data_out[15:0]} (tru_outh_pvld,tru_outh_prdy) <= {sat_int8_dout[1:0],tru_int8_dout[15:0]} (mul_outh_pvld,mul_outh_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p3 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_outh_pvld + ,sat_int8_dout + ,tru_int8_dout + ,tru_outh_prdy + ,mul_outh_prdy + ,sat_int8_data_out + ,tru_int8_data_out + ,tru_outh_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_outh_pvld; +input [1:0] sat_int8_dout; +input [15:0] tru_int8_dout; +input tru_outh_prdy; +output mul_outh_prdy; +output [1:0] sat_int8_data_out; +output [15:0] tru_int8_data_out; +output tru_outh_pvld; +reg mul_outh_prdy; +reg [17:0] p3_pipe_data; +reg p3_pipe_ready; +reg p3_pipe_ready_bc; +reg p3_pipe_valid; +reg p3_skid_catch; +reg [17:0] p3_skid_data; +reg [17:0] p3_skid_pipe_data; +reg p3_skid_pipe_ready; +reg p3_skid_pipe_valid; +reg p3_skid_ready; +reg p3_skid_ready_flop; +reg p3_skid_valid; +reg [1:0] sat_int8_data_out; +reg [15:0] tru_int8_data_out; +reg tru_outh_pvld; +//## pipe (3) skid buffer +always @( + mul_outh_pvld + or p3_skid_ready_flop + or p3_skid_pipe_ready + or p3_skid_valid + ) begin + p3_skid_catch = mul_outh_pvld && p3_skid_ready_flop && !p3_skid_pipe_ready; + p3_skid_ready = (p3_skid_valid)? p3_skid_pipe_ready : !p3_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_skid_valid <= 1'b0; + p3_skid_ready_flop <= 1'b1; + mul_outh_prdy <= 1'b1; + end else begin + p3_skid_valid <= (p3_skid_valid)? !p3_skid_pipe_ready : p3_skid_catch; + p3_skid_ready_flop <= p3_skid_ready; + mul_outh_prdy <= p3_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_skid_data <= (p3_skid_catch)? {sat_int8_dout[1:0],tru_int8_dout[15:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +always @( + p3_skid_ready_flop + or mul_outh_pvld + or p3_skid_valid + or sat_int8_dout + or tru_int8_dout + or p3_skid_data + ) begin + p3_skid_pipe_valid = (p3_skid_ready_flop)? mul_outh_pvld : p3_skid_valid; +// VCS sop_coverage_off start + p3_skid_pipe_data = (p3_skid_ready_flop)? {sat_int8_dout[1:0],tru_int8_dout[15:0]} : p3_skid_data; +// VCS sop_coverage_off end +end +//## pipe (3) valid-ready-bubble-collapse +always @( + p3_pipe_ready + or p3_pipe_valid + ) begin + p3_pipe_ready_bc = p3_pipe_ready || !p3_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p3_pipe_valid <= 1'b0; + end else begin + p3_pipe_valid <= (p3_pipe_ready_bc)? p3_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p3_pipe_data <= (p3_pipe_ready_bc && p3_skid_pipe_valid)? p3_skid_pipe_data : p3_pipe_data; +// VCS sop_coverage_off end +end +always @( + p3_pipe_ready_bc + ) begin + p3_skid_pipe_ready = p3_pipe_ready_bc; +end +//## pipe (3) output +always @( + p3_pipe_valid + or tru_outh_prdy + or p3_pipe_data + ) begin + tru_outh_pvld = p3_pipe_valid; + p3_pipe_ready = tru_outh_prdy; + {sat_int8_data_out[1:0],tru_int8_data_out[15:0]} = p3_pipe_data; +end +//## pipe (3) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p3_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_5x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_outh_pvld^tru_outh_prdy^mul_outh_pvld^mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_6x (nvdla_core_clk, `ASSERT_RESET, (mul_outh_pvld && !mul_outh_prdy), (mul_outh_pvld), (mul_outh_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p3 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is sub_data_out[33:0] (sub_out_pvld,sub_out_prdy) <= sub_dout[33:0] (chn_int16_pvld,chn_int16_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p4 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_int16_pvld + ,sub_dout + ,sub_out_prdy + ,chn_int16_prdy + ,sub_data_out + ,sub_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input chn_int16_pvld; +input [33:0] sub_dout; +input sub_out_prdy; +output chn_int16_prdy; +output [33:0] sub_data_out; +output sub_out_pvld; +reg chn_int16_prdy; +reg [33:0] p4_pipe_data; +reg p4_pipe_ready; +reg p4_pipe_ready_bc; +reg p4_pipe_valid; +reg p4_skid_catch; +reg [33:0] p4_skid_data; +reg [33:0] p4_skid_pipe_data; +reg p4_skid_pipe_ready; +reg p4_skid_pipe_valid; +reg p4_skid_ready; +reg p4_skid_ready_flop; +reg p4_skid_valid; +reg [33:0] sub_data_out; +reg sub_out_pvld; +//## pipe (4) skid buffer +always @( + chn_int16_pvld + or p4_skid_ready_flop + or p4_skid_pipe_ready + or p4_skid_valid + ) begin + p4_skid_catch = chn_int16_pvld && p4_skid_ready_flop && !p4_skid_pipe_ready; + p4_skid_ready = (p4_skid_valid)? p4_skid_pipe_ready : !p4_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_skid_valid <= 1'b0; + p4_skid_ready_flop <= 1'b1; + chn_int16_prdy <= 1'b1; + end else begin + p4_skid_valid <= (p4_skid_valid)? !p4_skid_pipe_ready : p4_skid_catch; + p4_skid_ready_flop <= p4_skid_ready; + chn_int16_prdy <= p4_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_skid_data <= (p4_skid_catch)? sub_dout[33:0] : p4_skid_data; +// VCS sop_coverage_off end +end +always @( + p4_skid_ready_flop + or chn_int16_pvld + or p4_skid_valid + or sub_dout + or p4_skid_data + ) begin + p4_skid_pipe_valid = (p4_skid_ready_flop)? chn_int16_pvld : p4_skid_valid; +// VCS sop_coverage_off start + p4_skid_pipe_data = (p4_skid_ready_flop)? sub_dout[33:0] : p4_skid_data; +// VCS sop_coverage_off end +end +//## pipe (4) valid-ready-bubble-collapse +always @( + p4_pipe_ready + or p4_pipe_valid + ) begin + p4_pipe_ready_bc = p4_pipe_ready || !p4_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p4_pipe_valid <= 1'b0; + end else begin + p4_pipe_valid <= (p4_pipe_ready_bc)? p4_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p4_pipe_data <= (p4_pipe_ready_bc && p4_skid_pipe_valid)? p4_skid_pipe_data : p4_pipe_data; +// VCS sop_coverage_off end +end +always @( + p4_pipe_ready_bc + ) begin + p4_skid_pipe_ready = p4_pipe_ready_bc; +end +//## pipe (4) output +always @( + p4_pipe_valid + or sub_out_prdy + or p4_pipe_data + ) begin + sub_out_pvld = p4_pipe_valid; + p4_pipe_ready = sub_out_prdy; + sub_data_out[33:0] = p4_pipe_data; +end +//## pipe (4) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p4_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_7x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (sub_out_pvld^sub_out_prdy^chn_int16_pvld^chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_8x (nvdla_core_clk, `ASSERT_RESET, (chn_int16_pvld && !chn_int16_prdy), (chn_int16_pvld), (chn_int16_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p4 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is mul_data_out[49:0] (mul_out_pvld,mul_out_prdy) <= mul_dout[49:0] (sub_out_pvld,sub_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p5 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_dout + ,mul_out_prdy + ,sub_out_pvld + ,mul_data_out + ,mul_out_pvld + ,sub_out_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [49:0] mul_dout; +input mul_out_prdy; +input sub_out_pvld; +output [49:0] mul_data_out; +output mul_out_pvld; +output sub_out_prdy; +reg [49:0] mul_data_out; +reg mul_out_pvld; +reg [49:0] p5_pipe_data; +reg p5_pipe_ready; +reg p5_pipe_ready_bc; +reg p5_pipe_valid; +reg p5_skid_catch; +reg [49:0] p5_skid_data; +reg [49:0] p5_skid_pipe_data; +reg p5_skid_pipe_ready; +reg p5_skid_pipe_valid; +reg p5_skid_ready; +reg p5_skid_ready_flop; +reg p5_skid_valid; +reg sub_out_prdy; +//## pipe (5) skid buffer +always @( + sub_out_pvld + or p5_skid_ready_flop + or p5_skid_pipe_ready + or p5_skid_valid + ) begin + p5_skid_catch = sub_out_pvld && p5_skid_ready_flop && !p5_skid_pipe_ready; + p5_skid_ready = (p5_skid_valid)? p5_skid_pipe_ready : !p5_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_skid_valid <= 1'b0; + p5_skid_ready_flop <= 1'b1; + sub_out_prdy <= 1'b1; + end else begin + p5_skid_valid <= (p5_skid_valid)? !p5_skid_pipe_ready : p5_skid_catch; + p5_skid_ready_flop <= p5_skid_ready; + sub_out_prdy <= p5_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_skid_data <= (p5_skid_catch)? mul_dout[49:0] : p5_skid_data; +// VCS sop_coverage_off end +end +always @( + p5_skid_ready_flop + or sub_out_pvld + or p5_skid_valid + or mul_dout + or p5_skid_data + ) begin + p5_skid_pipe_valid = (p5_skid_ready_flop)? sub_out_pvld : p5_skid_valid; +// VCS sop_coverage_off start + p5_skid_pipe_data = (p5_skid_ready_flop)? mul_dout[49:0] : p5_skid_data; +// VCS sop_coverage_off end +end +//## pipe (5) valid-ready-bubble-collapse +always @( + p5_pipe_ready + or p5_pipe_valid + ) begin + p5_pipe_ready_bc = p5_pipe_ready || !p5_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p5_pipe_valid <= 1'b0; + end else begin + p5_pipe_valid <= (p5_pipe_ready_bc)? p5_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p5_pipe_data <= (p5_pipe_ready_bc && p5_skid_pipe_valid)? p5_skid_pipe_data : p5_pipe_data; +// VCS sop_coverage_off end +end +always @( + p5_pipe_ready_bc + ) begin + p5_skid_pipe_ready = p5_pipe_ready_bc; +end +//## pipe (5) output +always @( + p5_pipe_valid + or mul_out_prdy + or p5_pipe_data + ) begin + mul_out_pvld = p5_pipe_valid; + p5_pipe_ready = mul_out_prdy; + mul_data_out[49:0] = p5_pipe_data; +end +//## pipe (5) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p5_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_9x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (mul_out_pvld^mul_out_prdy^sub_out_pvld^sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_10x (nvdla_core_clk, `ASSERT_RESET, (sub_out_pvld && !sub_out_prdy), (sub_out_pvld), (sub_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p5 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is {sat_data_out,tru_data_out[15:0]} (tru_out_pvld,tru_out_prdy) <= {sat_dout,tru_dout[15:0]} (mul_out_pvld,mul_out_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p6 ( + nvdla_core_clk + ,nvdla_core_rstn + ,mul_out_pvld + ,sat_dout + ,tru_dout + ,tru_out_prdy + ,mul_out_prdy + ,sat_data_out + ,tru_data_out + ,tru_out_pvld + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input mul_out_pvld; +input sat_dout; +input [15:0] tru_dout; +input tru_out_prdy; +output mul_out_prdy; +output sat_data_out; +output [15:0] tru_data_out; +output tru_out_pvld; +reg mul_out_prdy; +reg [16:0] p6_pipe_data; +reg p6_pipe_ready; +reg p6_pipe_ready_bc; +reg p6_pipe_valid; +reg p6_skid_catch; +reg [16:0] p6_skid_data; +reg [16:0] p6_skid_pipe_data; +reg p6_skid_pipe_ready; +reg p6_skid_pipe_valid; +reg p6_skid_ready; +reg p6_skid_ready_flop; +reg p6_skid_valid; +reg sat_data_out; +reg [15:0] tru_data_out; +reg tru_out_pvld; +//## pipe (6) skid buffer +always @( + mul_out_pvld + or p6_skid_ready_flop + or p6_skid_pipe_ready + or p6_skid_valid + ) begin + p6_skid_catch = mul_out_pvld && p6_skid_ready_flop && !p6_skid_pipe_ready; + p6_skid_ready = (p6_skid_valid)? p6_skid_pipe_ready : !p6_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_skid_valid <= 1'b0; + p6_skid_ready_flop <= 1'b1; + mul_out_prdy <= 1'b1; + end else begin + p6_skid_valid <= (p6_skid_valid)? !p6_skid_pipe_ready : p6_skid_catch; + p6_skid_ready_flop <= p6_skid_ready; + mul_out_prdy <= p6_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_skid_data <= (p6_skid_catch)? {sat_dout,tru_dout[15:0]} : p6_skid_data; +// VCS sop_coverage_off end +end +always @( + p6_skid_ready_flop + or mul_out_pvld + or p6_skid_valid + or sat_dout + or tru_dout + or p6_skid_data + ) begin + p6_skid_pipe_valid = (p6_skid_ready_flop)? mul_out_pvld : p6_skid_valid; +// VCS sop_coverage_off start + p6_skid_pipe_data = (p6_skid_ready_flop)? {sat_dout,tru_dout[15:0]} : p6_skid_data; +// VCS sop_coverage_off end +end +//## pipe (6) valid-ready-bubble-collapse +always @( + p6_pipe_ready + or p6_pipe_valid + ) begin + p6_pipe_ready_bc = p6_pipe_ready || !p6_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p6_pipe_valid <= 1'b0; + end else begin + p6_pipe_valid <= (p6_pipe_ready_bc)? p6_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p6_pipe_data <= (p6_pipe_ready_bc && p6_skid_pipe_valid)? p6_skid_pipe_data : p6_pipe_data; +// VCS sop_coverage_off end +end +always @( + p6_pipe_ready_bc + ) begin + p6_skid_pipe_ready = p6_pipe_ready_bc; +end +//## pipe (6) output +always @( + p6_pipe_valid + or tru_out_prdy + or p6_pipe_data + ) begin + tru_out_pvld = p6_pipe_valid; + p6_pipe_ready = tru_out_prdy; + {sat_data_out,tru_data_out[15:0]} = p6_pipe_data; +end +//## pipe (6) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p6_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_11x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (tru_out_pvld^tru_out_prdy^mul_out_pvld^mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_12x (nvdla_core_clk, `ASSERT_RESET, (mul_out_pvld && !mul_out_prdy), (mul_out_pvld), (mul_out_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p6 +// ************************************************************************************************************** +// Generated by ::pipe -m -bc -rand none -is chn_data_out[17:0] (chn_out_pvld,chn_out_prdy) <= chn_dout[17:0] (tru_final_pvld,tru_final_prdy) +// ************************************************************************************************************** +module NV_NVDLA_CDP_HLS_OCVT_pipe_p7 ( + nvdla_core_clk + ,nvdla_core_rstn + ,chn_dout + ,chn_out_prdy + ,tru_final_pvld + ,chn_data_out + ,chn_out_pvld + ,tru_final_prdy + ); +input nvdla_core_clk; +input nvdla_core_rstn; +input [17:0] chn_dout; +input chn_out_prdy; +input tru_final_pvld; +output [17:0] chn_data_out; +output chn_out_pvld; +output tru_final_prdy; +reg [17:0] chn_data_out; +reg chn_out_pvld; +reg [17:0] p7_pipe_data; +reg p7_pipe_ready; +reg p7_pipe_ready_bc; +reg p7_pipe_valid; +reg p7_skid_catch; +reg [17:0] p7_skid_data; +reg [17:0] p7_skid_pipe_data; +reg p7_skid_pipe_ready; +reg p7_skid_pipe_valid; +reg p7_skid_ready; +reg p7_skid_ready_flop; +reg p7_skid_valid; +reg tru_final_prdy; +//## pipe (7) skid buffer +always @( + tru_final_pvld + or p7_skid_ready_flop + or p7_skid_pipe_ready + or p7_skid_valid + ) begin + p7_skid_catch = tru_final_pvld && p7_skid_ready_flop && !p7_skid_pipe_ready; + p7_skid_ready = (p7_skid_valid)? p7_skid_pipe_ready : !p7_skid_catch; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_skid_valid <= 1'b0; + p7_skid_ready_flop <= 1'b1; + tru_final_prdy <= 1'b1; + end else begin + p7_skid_valid <= (p7_skid_valid)? !p7_skid_pipe_ready : p7_skid_catch; + p7_skid_ready_flop <= p7_skid_ready; + tru_final_prdy <= p7_skid_ready; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_skid_data <= (p7_skid_catch)? chn_dout[17:0] : p7_skid_data; +// VCS sop_coverage_off end +end +always @( + p7_skid_ready_flop + or tru_final_pvld + or p7_skid_valid + or chn_dout + or p7_skid_data + ) begin + p7_skid_pipe_valid = (p7_skid_ready_flop)? tru_final_pvld : p7_skid_valid; +// VCS sop_coverage_off start + p7_skid_pipe_data = (p7_skid_ready_flop)? chn_dout[17:0] : p7_skid_data; +// VCS sop_coverage_off end +end +//## pipe (7) valid-ready-bubble-collapse +always @( + p7_pipe_ready + or p7_pipe_valid + ) begin + p7_pipe_ready_bc = p7_pipe_ready || !p7_pipe_valid; +end +always @(posedge nvdla_core_clk or negedge nvdla_core_rstn) begin + if (!nvdla_core_rstn) begin + p7_pipe_valid <= 1'b0; + end else begin + p7_pipe_valid <= (p7_pipe_ready_bc)? p7_skid_pipe_valid : 1'd1; + end +end +always @(posedge nvdla_core_clk) begin +// VCS sop_coverage_off start + p7_pipe_data <= (p7_pipe_ready_bc && p7_skid_pipe_valid)? p7_skid_pipe_data : p7_pipe_data; +// VCS sop_coverage_off end +end +always @( + p7_pipe_ready_bc + ) begin + p7_skid_pipe_ready = p7_pipe_ready_bc; +end +//## pipe (7) output +always @( + p7_pipe_valid + or chn_out_prdy + or p7_pipe_data + ) begin + chn_out_pvld = p7_pipe_valid; + p7_pipe_ready = chn_out_prdy; + chn_data_out[17:0] = p7_pipe_data; +end +//## pipe (7) assertions/testpoints +`ifndef VIVA_PLUGIN_PIPE_DISABLE_ASSERTIONS +wire p7_assert_clk = nvdla_core_clk; +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`ifndef SYNTHESIS +// VCS coverage off + nv_assert_no_x #(0,1,0,"No X's allowed on control signals") zzz_assert_no_x_13x (nvdla_core_clk, `ASSERT_RESET, nvdla_core_rstn, (chn_out_pvld^chn_out_prdy^tru_final_pvld^tru_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`endif +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass disable_block NoWidthInBasedNum-ML +// spyglass disable_block STARC-2.10.3.2a +// spyglass disable_block STARC05-2.1.3.1 +// spyglass disable_block STARC-2.1.4.6 +// spyglass disable_block W116 +// spyglass disable_block W154 +// spyglass disable_block W239 +// spyglass disable_block W362 +// spyglass disable_block WRN_58 +// spyglass disable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`ifdef ASSERT_ON +`ifdef FV_ASSERT_ON +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef SYNTHESIS +`define ASSERT_RESET nvdla_core_rstn +`else +`ifdef ASSERT_OFF_RESET_IS_X +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b0 : nvdla_core_rstn) +`else +`define ASSERT_RESET ((1'bx === nvdla_core_rstn) ? 1'b1 : nvdla_core_rstn) +`endif // ASSERT_OFF_RESET_IS_X +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +// VCS coverage off + nv_assert_hold_throughout_event_interval #(0,1,0,"valid removed before ready") zzz_assert_hold_throughout_event_interval_14x (nvdla_core_clk, `ASSERT_RESET, (tru_final_pvld && !tru_final_prdy), (tru_final_pvld), (tru_final_prdy)); // spyglass disable W504 SelfDeterminedExpr-ML +// VCS coverage on +`undef ASSERT_RESET +`endif // ASSERT_ON +`ifdef SPYGLASS_ASSERT_ON +`else +// spyglass enable_block NoWidthInBasedNum-ML +// spyglass enable_block STARC-2.10.3.2a +// spyglass enable_block STARC05-2.1.3.1 +// spyglass enable_block STARC-2.1.4.6 +// spyglass enable_block W116 +// spyglass enable_block W154 +// spyglass enable_block W239 +// spyglass enable_block W362 +// spyglass enable_block WRN_58 +// spyglass enable_block WRN_61 +`endif // SPYGLASS_ASSERT_ON +`endif +endmodule // NV_NVDLA_CDP_HLS_OCVT_pipe_p7 diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_saturate.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_saturate.v new file mode 100644 index 0000000..10736a5 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_saturate.v @@ -0,0 +1,33 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_saturate.v +module NV_NVDLA_HLS_saturate ( + data_in + ,data_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +input [IN_WIDTH-1:0] data_in; +output [OUT_WIDTH-1:0] data_out; +wire [OUT_WIDTH-1:0] data_max; +wire data_sign; +wire tru_need_sat; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign tru_need_sat = ( data_sign & ~(&data_in[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_in[IN_WIDTH-2:OUT_WIDTH-1])); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = tru_need_sat ? data_max : data_in[((OUT_WIDTH) - 1):0]; +endmodule // NV_NVDLA_HLS_saturate diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_saturate.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_saturate.v.vcp new file mode 100644 index 0000000..10736a5 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_saturate.v.vcp @@ -0,0 +1,33 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_saturate.v +module NV_NVDLA_HLS_saturate ( + data_in + ,data_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +input [IN_WIDTH-1:0] data_in; +output [OUT_WIDTH-1:0] data_out; +wire [OUT_WIDTH-1:0] data_max; +wire data_sign; +wire tru_need_sat; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign tru_need_sat = ( data_sign & ~(&data_in[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_in[IN_WIDTH-2:OUT_WIDTH-1])); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = tru_need_sat ? data_max : data_in[((OUT_WIDTH) - 1):0]; +endmodule // NV_NVDLA_HLS_saturate diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftleftsu.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftleftsu.v new file mode 100644 index 0000000..dcdfa3b --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftleftsu.v @@ -0,0 +1,40 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftleftsu.v +module NV_NVDLA_HLS_shiftleftsu ( + data_in + ,shift_num + ,data_out + ); +parameter IN_WIDTH = 16; +parameter OUT_WIDTH = 32; +parameter SHIFT_WIDTH = 6; +parameter SHIFT_MAX = (1<> shift_num[((SHIFT_WIDTH) - 1):0]; +//assign {data_shift[::range(IN_WIDTH)], guide, stick[::range(IN_WIDTH-1)]} = ($signed({data_in,{IN_WIDTH{1'b0}}}) >>> shift_num[::range(SHIFT_WIDTH)]); +assign point5 = guide & (~data_sign | (|stick)); +assign {mon_round_c,data_round[((OUT_WIDTH) - 1):0]} = data_shift[((OUT_WIDTH) - 1):0] + point5; +assign tru_need_sat = ( data_sign & ~(&data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (&{data_shift[((OUT_WIDTH-1) - 1):0], point5})); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = (shift_num >= IN_WIDTH) ? {(OUT_WIDTH){1'b0}} : tru_need_sat ? data_max : data_round; +assign sat_out = (shift_num >= IN_WIDTH) ? 1'b0: tru_need_sat; +endmodule // NV_NVDLA_HLS_shiftrightsatsu diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsatsu.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsatsu.v.vcp new file mode 100644 index 0000000..11c944d --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsatsu.v.vcp @@ -0,0 +1,51 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightsatsu.v +module NV_NVDLA_HLS_shiftrightsatsu ( + data_in + ,shift_num + ,data_out + ,sat_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter SHIFT_WIDTH = 6; +input [IN_WIDTH-1:0] data_in; +input [SHIFT_WIDTH-1:0] shift_num; +output [OUT_WIDTH-1:0] data_out; +output sat_out; +wire [IN_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_shift; +wire [IN_WIDTH-2:0] stick; +wire [OUT_WIDTH-1:0] data_max; +wire [OUT_WIDTH-1:0] data_round; +wire data_sign; +wire guide; +wire point5; +wire mon_round_c; +wire tru_need_sat; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign {data_high[((IN_WIDTH) - 1):0], data_shift[((IN_WIDTH) - 1):0], guide, stick[((IN_WIDTH-1) - 1):0]} = {{IN_WIDTH{data_sign}},data_in,{IN_WIDTH{1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +//assign {data_shift[::range(IN_WIDTH)], guide, stick[::range(IN_WIDTH-1)]} = ($signed({data_in,{IN_WIDTH{1'b0}}}) >>> shift_num[::range(SHIFT_WIDTH)]); +assign point5 = guide & (~data_sign | (|stick)); +assign {mon_round_c,data_round[((OUT_WIDTH) - 1):0]} = data_shift[((OUT_WIDTH) - 1):0] + point5; +assign tru_need_sat = ( data_sign & ~(&data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (&{data_shift[((OUT_WIDTH-1) - 1):0], point5})); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = (shift_num >= IN_WIDTH) ? {(OUT_WIDTH){1'b0}} : tru_need_sat ? data_max : data_round; +assign sat_out = (shift_num >= IN_WIDTH) ? 1'b0: tru_need_sat; +endmodule // NV_NVDLA_HLS_shiftrightsatsu diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightss.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightss.v new file mode 100644 index 0000000..dfe2443 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightss.v @@ -0,0 +1,64 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightss.v +module NV_NVDLA_HLS_shiftrightss ( + data_in + ,shift_num + ,data_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter SHIFT_WIDTH = 6; +parameter SHIFT_MAX = 1<<(SHIFT_WIDTH-1); +parameter HIGH_WIDTH = SHIFT_MAX+IN_WIDTH-OUT_WIDTH; +input [IN_WIDTH-1:0] data_in; //signed +input [SHIFT_WIDTH-1:0] shift_num; //signed +output [OUT_WIDTH-1:0] data_out; +wire [OUT_WIDTH-1:0] data_shift_l; +wire [HIGH_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_highr; +wire [IN_WIDTH-1:0] data_shift_rt; +wire [IN_WIDTH-1:0] data_shift_r; +wire [IN_WIDTH-2:0] stick; +wire [OUT_WIDTH-1:0] data_max; +wire [OUT_WIDTH-1:0] data_round; +wire shift_sign; +wire data_sign; +wire guide; +wire point5; +wire mon_round_c; +wire left_shift_sat; +wire right_shift_sat; +wire [5:0] shift_num_abs; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign shift_sign = shift_num[SHIFT_WIDTH-1]; +//shift left +assign shift_num_abs[SHIFT_WIDTH-1:0] = ~shift_num[SHIFT_WIDTH-1:0] + 1; +assign {data_high[((HIGH_WIDTH) - 1):0],data_shift_l[((OUT_WIDTH) - 1):0]} = {{SHIFT_MAX{data_sign}},data_in} << shift_num_abs[((SHIFT_WIDTH) - 1):0]; +assign left_shift_sat = shift_sign & {data_high,data_shift_l[OUT_WIDTH-1]} != {(HIGH_WIDTH+1){data_sign}}; +//shift right +assign {data_highr[((IN_WIDTH) - 1):0],data_shift_rt[((IN_WIDTH) - 1):0], guide, stick[((IN_WIDTH-1) - 1):0]} = {{IN_WIDTH{data_sign}},data_in,{IN_WIDTH{1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +//assign {data_shift_rt[::range(IN_WIDTH)], guide, stick[::range(IN_WIDTH-1)]} = ($signed({data_in,{IN_WIDTH{1'b0}}}) >>> shift_num[::range(SHIFT_WIDTH)]); +assign data_shift_r[((IN_WIDTH) - 1):0] = shift_num >= IN_WIDTH ? {IN_WIDTH{1'b0}} : data_shift_rt[((IN_WIDTH) - 1):0]; +assign point5 = shift_num >= IN_WIDTH ? 1'b0 : guide & (~data_sign | (|stick)); +assign {mon_round_c,data_round[((OUT_WIDTH) - 1):0]} = data_shift_r[((OUT_WIDTH) - 1):0] + point5; +assign right_shift_sat = !shift_sign & + (( data_sign & ~(&data_shift_r[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_shift_r[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (&{data_shift_r[((OUT_WIDTH-1) - 1):0], point5}))); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = (left_shift_sat | right_shift_sat) ? data_max : shift_sign ? data_shift_l : data_round; +endmodule // NV_NVDLA_HLS_shiftrightss diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightss.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightss.v.vcp new file mode 100644 index 0000000..dfe2443 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightss.v.vcp @@ -0,0 +1,64 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightss.v +module NV_NVDLA_HLS_shiftrightss ( + data_in + ,shift_num + ,data_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter SHIFT_WIDTH = 6; +parameter SHIFT_MAX = 1<<(SHIFT_WIDTH-1); +parameter HIGH_WIDTH = SHIFT_MAX+IN_WIDTH-OUT_WIDTH; +input [IN_WIDTH-1:0] data_in; //signed +input [SHIFT_WIDTH-1:0] shift_num; //signed +output [OUT_WIDTH-1:0] data_out; +wire [OUT_WIDTH-1:0] data_shift_l; +wire [HIGH_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_highr; +wire [IN_WIDTH-1:0] data_shift_rt; +wire [IN_WIDTH-1:0] data_shift_r; +wire [IN_WIDTH-2:0] stick; +wire [OUT_WIDTH-1:0] data_max; +wire [OUT_WIDTH-1:0] data_round; +wire shift_sign; +wire data_sign; +wire guide; +wire point5; +wire mon_round_c; +wire left_shift_sat; +wire right_shift_sat; +wire [5:0] shift_num_abs; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign shift_sign = shift_num[SHIFT_WIDTH-1]; +//shift left +assign shift_num_abs[SHIFT_WIDTH-1:0] = ~shift_num[SHIFT_WIDTH-1:0] + 1; +assign {data_high[((HIGH_WIDTH) - 1):0],data_shift_l[((OUT_WIDTH) - 1):0]} = {{SHIFT_MAX{data_sign}},data_in} << shift_num_abs[((SHIFT_WIDTH) - 1):0]; +assign left_shift_sat = shift_sign & {data_high,data_shift_l[OUT_WIDTH-1]} != {(HIGH_WIDTH+1){data_sign}}; +//shift right +assign {data_highr[((IN_WIDTH) - 1):0],data_shift_rt[((IN_WIDTH) - 1):0], guide, stick[((IN_WIDTH-1) - 1):0]} = {{IN_WIDTH{data_sign}},data_in,{IN_WIDTH{1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +//assign {data_shift_rt[::range(IN_WIDTH)], guide, stick[::range(IN_WIDTH-1)]} = ($signed({data_in,{IN_WIDTH{1'b0}}}) >>> shift_num[::range(SHIFT_WIDTH)]); +assign data_shift_r[((IN_WIDTH) - 1):0] = shift_num >= IN_WIDTH ? {IN_WIDTH{1'b0}} : data_shift_rt[((IN_WIDTH) - 1):0]; +assign point5 = shift_num >= IN_WIDTH ? 1'b0 : guide & (~data_sign | (|stick)); +assign {mon_round_c,data_round[((OUT_WIDTH) - 1):0]} = data_shift_r[((OUT_WIDTH) - 1):0] + point5; +assign right_shift_sat = !shift_sign & + (( data_sign & ~(&data_shift_r[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_shift_r[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (&{data_shift_r[((OUT_WIDTH-1) - 1):0], point5}))); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = (left_shift_sat | right_shift_sat) ? data_max : shift_sign ? data_shift_l : data_round; +endmodule // NV_NVDLA_HLS_shiftrightss diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v new file mode 100644 index 0000000..3cf645e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v @@ -0,0 +1,48 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightsu.v +module NV_NVDLA_HLS_shiftrightsu ( + data_in + ,shift_num + ,data_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter SHIFT_WIDTH = 6; +input [IN_WIDTH-1:0] data_in; +input [SHIFT_WIDTH-1:0] shift_num; +output [OUT_WIDTH-1:0] data_out; +wire [IN_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_shift; +wire [IN_WIDTH-2:0] stick; +wire [OUT_WIDTH-1:0] data_max; +wire [OUT_WIDTH-1:0] data_round; +wire data_sign; +wire guide; +wire point5; +wire mon_round_c; +wire tru_need_sat; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign {data_high[((IN_WIDTH) - 1):0], data_shift[((IN_WIDTH) - 1):0], guide, stick[((IN_WIDTH-1) - 1):0]} = {{IN_WIDTH{data_sign}},data_in,{IN_WIDTH{1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +//assign {data_shift[::range(IN_WIDTH)], guide, stick[::range(IN_WIDTH-1)]} = ($signed({data_in,{IN_WIDTH{1'b0}}}) >>> shift_num[::range(SHIFT_WIDTH)]); +assign point5 = guide & (~data_sign | (|stick)); +assign {mon_round_c,data_round[((OUT_WIDTH) - 1):0]} = data_shift[((OUT_WIDTH) - 1):0] + point5; +assign tru_need_sat = ( data_sign & ~(&data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (&{data_shift[((OUT_WIDTH-1) - 1):0], point5})); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = (shift_num >= IN_WIDTH) ? {(OUT_WIDTH){1'b0}} : tru_need_sat ? data_max : data_round; +endmodule // NV_NVDLA_HLS_shiftrightsu diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v.vcp new file mode 100644 index 0000000..3cf645e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v.vcp @@ -0,0 +1,48 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightsu.v +module NV_NVDLA_HLS_shiftrightsu ( + data_in + ,shift_num + ,data_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter SHIFT_WIDTH = 6; +input [IN_WIDTH-1:0] data_in; +input [SHIFT_WIDTH-1:0] shift_num; +output [OUT_WIDTH-1:0] data_out; +wire [IN_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_shift; +wire [IN_WIDTH-2:0] stick; +wire [OUT_WIDTH-1:0] data_max; +wire [OUT_WIDTH-1:0] data_round; +wire data_sign; +wire guide; +wire point5; +wire mon_round_c; +wire tru_need_sat; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +assign data_sign = data_in[IN_WIDTH-1]; +assign {data_high[((IN_WIDTH) - 1):0], data_shift[((IN_WIDTH) - 1):0], guide, stick[((IN_WIDTH-1) - 1):0]} = {{IN_WIDTH{data_sign}},data_in,{IN_WIDTH{1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +//assign {data_shift[::range(IN_WIDTH)], guide, stick[::range(IN_WIDTH-1)]} = ($signed({data_in,{IN_WIDTH{1'b0}}}) >>> shift_num[::range(SHIFT_WIDTH)]); +assign point5 = guide & (~data_sign | (|stick)); +assign {mon_round_c,data_round[((OUT_WIDTH) - 1):0]} = data_shift[((OUT_WIDTH) - 1):0] + point5; +assign tru_need_sat = ( data_sign & ~(&data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (|data_shift[IN_WIDTH-2:OUT_WIDTH-1])) | + (~data_sign & (&{data_shift[((OUT_WIDTH-1) - 1):0], point5})); +assign data_max = data_sign ? {1'b1, {(OUT_WIDTH-1){1'b0}}} : ~{1'b1, {(OUT_WIDTH-1){1'b0}}}; +assign data_out = (shift_num >= IN_WIDTH) ? {(OUT_WIDTH){1'b0}} : tru_need_sat ? data_max : data_round; +endmodule // NV_NVDLA_HLS_shiftrightsu diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightusz.v b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightusz.v new file mode 100644 index 0000000..789449e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightusz.v @@ -0,0 +1,54 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightusz.v +module NV_NVDLA_HLS_shiftrightusz ( + data_in + ,shift_num + ,data_out + ,frac_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter FRAC_WIDTH = 35; //suppose FRAC_WIDTH > IN_WIDTH > OUT_WIDTH +parameter SHIFT_WIDTH = 6; +parameter SHIFT_MAX = 1<<(SHIFT_WIDTH-1); +parameter HIGH_WIDTH = SHIFT_MAX+IN_WIDTH-OUT_WIDTH; +input [IN_WIDTH-1:0] data_in; //unsigned int +input [SHIFT_WIDTH-1:0] shift_num; //signed int +output [OUT_WIDTH-1:0] data_out; +output [FRAC_WIDTH-1:0] frac_out; +wire [SHIFT_WIDTH-1:0] shift_num_abs; +wire [OUT_WIDTH-1:0] data_shift_l; +wire [HIGH_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_shift_r; +wire [FRAC_WIDTH-1:0] frac_shift; +wire [OUT_WIDTH-1:0] data_max; +wire left_shift_sat; +wire right_shift_sat; +wire shift_sign; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//shift left +assign shift_sign = shift_num[SHIFT_WIDTH-1]; +assign shift_num_abs[SHIFT_WIDTH-1:0] = ~shift_num[SHIFT_WIDTH-1:0] + 1; +assign {data_high[((HIGH_WIDTH) - 1):0],data_shift_l[((OUT_WIDTH) - 1):0]} = {{SHIFT_MAX{1'b0}},data_in} << shift_num_abs[((SHIFT_WIDTH) - 1):0]; +assign left_shift_sat = shift_sign & {data_high[((HIGH_WIDTH) - 1):0],data_shift_l[OUT_WIDTH-1]} != {(HIGH_WIDTH+1){1'b0}}; +//shift right +assign {data_shift_r[((IN_WIDTH) - 1):0],frac_shift[((FRAC_WIDTH) - 1):0]} = {data_in[((IN_WIDTH) - 1):0],{(FRAC_WIDTH){1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +assign right_shift_sat = !shift_sign & (|data_shift_r[IN_WIDTH-1:OUT_WIDTH]); +assign data_max = {(OUT_WIDTH){1'b1}}; +//final out +assign data_out[((OUT_WIDTH) - 1):0] = (left_shift_sat | right_shift_sat) ? data_max : shift_sign ? data_shift_l[((OUT_WIDTH) - 1):0] : data_shift_r[((OUT_WIDTH) - 1):0]; +assign frac_out[((FRAC_WIDTH) - 1):0] = shift_sign ? {FRAC_WIDTH{1'b0}} : frac_shift[((FRAC_WIDTH) - 1):0]; +endmodule // NV_NVDLA_HLS_shiftrightusz diff --git a/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightusz.v.vcp b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightusz.v.vcp new file mode 100644 index 0000000..789449e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/NV_NVDLA_HLS_shiftrightusz.v.vcp @@ -0,0 +1,54 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: NV_NVDLA_HLS_shiftrightusz.v +module NV_NVDLA_HLS_shiftrightusz ( + data_in + ,shift_num + ,data_out + ,frac_out + ); +parameter IN_WIDTH = 49; +parameter OUT_WIDTH = 32; +parameter FRAC_WIDTH = 35; //suppose FRAC_WIDTH > IN_WIDTH > OUT_WIDTH +parameter SHIFT_WIDTH = 6; +parameter SHIFT_MAX = 1<<(SHIFT_WIDTH-1); +parameter HIGH_WIDTH = SHIFT_MAX+IN_WIDTH-OUT_WIDTH; +input [IN_WIDTH-1:0] data_in; //unsigned int +input [SHIFT_WIDTH-1:0] shift_num; //signed int +output [OUT_WIDTH-1:0] data_out; +output [FRAC_WIDTH-1:0] frac_out; +wire [SHIFT_WIDTH-1:0] shift_num_abs; +wire [OUT_WIDTH-1:0] data_shift_l; +wire [HIGH_WIDTH-1:0] data_high; +wire [IN_WIDTH-1:0] data_shift_r; +wire [FRAC_WIDTH-1:0] frac_shift; +wire [OUT_WIDTH-1:0] data_max; +wire left_shift_sat; +wire right_shift_sat; +wire shift_sign; +// synoff nets +// monitor nets +// debug nets +// tie high nets +// tie low nets +// no connect nets +// not all bits used nets +// todo nets +//shift left +assign shift_sign = shift_num[SHIFT_WIDTH-1]; +assign shift_num_abs[SHIFT_WIDTH-1:0] = ~shift_num[SHIFT_WIDTH-1:0] + 1; +assign {data_high[((HIGH_WIDTH) - 1):0],data_shift_l[((OUT_WIDTH) - 1):0]} = {{SHIFT_MAX{1'b0}},data_in} << shift_num_abs[((SHIFT_WIDTH) - 1):0]; +assign left_shift_sat = shift_sign & {data_high[((HIGH_WIDTH) - 1):0],data_shift_l[OUT_WIDTH-1]} != {(HIGH_WIDTH+1){1'b0}}; +//shift right +assign {data_shift_r[((IN_WIDTH) - 1):0],frac_shift[((FRAC_WIDTH) - 1):0]} = {data_in[((IN_WIDTH) - 1):0],{(FRAC_WIDTH){1'b0}}} >> shift_num[((SHIFT_WIDTH) - 1):0]; +assign right_shift_sat = !shift_sign & (|data_shift_r[IN_WIDTH-1:OUT_WIDTH]); +assign data_max = {(OUT_WIDTH){1'b1}}; +//final out +assign data_out[((OUT_WIDTH) - 1):0] = (left_shift_sat | right_shift_sat) ? data_max : shift_sign ? data_shift_l[((OUT_WIDTH) - 1):0] : data_shift_r[((OUT_WIDTH) - 1):0]; +assign frac_out[((FRAC_WIDTH) - 1):0] = shift_sign ? {FRAC_WIDTH{1'b0}} : frac_shift[((FRAC_WIDTH) - 1):0]; +endmodule // NV_NVDLA_HLS_shiftrightusz diff --git a/designs/src/NVDLA/vmod/vlibs/OR2D1.v b/designs/src/NVDLA/vmod/vlibs/OR2D1.v new file mode 100644 index 0000000..79230df --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/OR2D1.v @@ -0,0 +1,18 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: OR2D1.v +module OR2D1 ( + A1 + ,A2 + ,Z + ); +input A1 ; +input A2 ; +output Z ; +assign Z = A1 | A2; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/OR2D1.v.vcp b/designs/src/NVDLA/vmod/vlibs/OR2D1.v.vcp new file mode 100644 index 0000000..79230df --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/OR2D1.v.vcp @@ -0,0 +1,18 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: OR2D1.v +module OR2D1 ( + A1 + ,A2 + ,Z + ); +input A1 ; +input A2 ; +output Z ; +assign Z = A1 | A2; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/PGAOPV_AN2D2PO4.v b/designs/src/NVDLA/vmod/vlibs/PGAOPV_AN2D2PO4.v new file mode 100644 index 0000000..2c9bfe0 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/PGAOPV_AN2D2PO4.v @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: PGAOPV_AN2D2PO4.v +module PGAOPV_AN2D2PO4 ( + A1 + ,A2 + ,Z + ); +//--------------------------------------- +//IO DECLARATIONS +input A1 ; +input A2 ; +output Z ; +assign Z = A1 & A2; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/PGAOPV_AN2D2PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/PGAOPV_AN2D2PO4.v.vcp new file mode 100644 index 0000000..2c9bfe0 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/PGAOPV_AN2D2PO4.v.vcp @@ -0,0 +1,20 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: PGAOPV_AN2D2PO4.v +module PGAOPV_AN2D2PO4 ( + A1 + ,A2 + ,Z + ); +//--------------------------------------- +//IO DECLARATIONS +input A1 ; +input A2 ; +output Z ; +assign Z = A1 & A2; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/PGAOPV_DFCNQD2PO4.v b/designs/src/NVDLA/vmod/vlibs/PGAOPV_DFCNQD2PO4.v new file mode 100644 index 0000000..d1b6b26 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/PGAOPV_DFCNQD2PO4.v @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: PGAOPV_DFCNQD2PO4.v +module PGAOPV_DFCNQD2PO4 ( + D + ,CP + ,CDN + ,Q + ); +//--------------------------------------- +//IO DECLARATIONS +input D ; +input CP ; +input CDN ; +output Q ; +reg Q; +always @(posedge CP or negedge CDN) +begin + if(~CDN) + Q <= 1'b0; + else + Q <= D; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/PGAOPV_DFCNQD2PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/PGAOPV_DFCNQD2PO4.v.vcp new file mode 100644 index 0000000..d1b6b26 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/PGAOPV_DFCNQD2PO4.v.vcp @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: PGAOPV_DFCNQD2PO4.v +module PGAOPV_DFCNQD2PO4 ( + D + ,CP + ,CDN + ,Q + ); +//--------------------------------------- +//IO DECLARATIONS +input D ; +input CP ; +input CDN ; +output Q ; +reg Q; +always @(posedge CP or negedge CDN) +begin + if(~CDN) + Q <= 1'b0; + else + Q <= D; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/PGAOPV_INVD2PO4.v b/designs/src/NVDLA/vmod/vlibs/PGAOPV_INVD2PO4.v new file mode 100644 index 0000000..559e557 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/PGAOPV_INVD2PO4.v @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: PGAOPV_INVD2PO4.v +module PGAOPV_INVD2PO4 ( + I + ,ZN + ); +input I ; +output ZN ; +assign ZN = ~I; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/PGAOPV_INVD2PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/PGAOPV_INVD2PO4.v.vcp new file mode 100644 index 0000000..559e557 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/PGAOPV_INVD2PO4.v.vcp @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: PGAOPV_INVD2PO4.v +module PGAOPV_INVD2PO4 ( + I + ,ZN + ); +input I ; +output ZN ; +assign ZN = ~I; +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/RANDFUNC.vlib b/designs/src/NVDLA/vmod/vlibs/RANDFUNC.vlib new file mode 100644 index 0000000..984acac --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/RANDFUNC.vlib @@ -0,0 +1,156 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: RANDFUNC.vlib +`ifdef NV_HWACC + `include "NV_HWACC_VLIB_tick_defines.vh" +`endif +`celldefine +`ifndef FLATGATES // REGEN_MONOLITHIC_MARK1 +// Model: RANDFUNC - cell_lib Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/cell_db/common/R/RANDFUNC/RANDFUNC_nonpg.vlib#8 +// RIP_START - RANDFUNC.v +// Model: RANDFUNC - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/RANDFUNC.v#4 +// Model: header - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/lib.header#1 +`define RANDFUNC_MODNAME_LEN (32) +module RANDFUNC; +reg [47:0] seed; +reg initialized; +`ifndef PRAND_VERILOG +// hash_combine(). +// Combine hash values. k=key. v=variable +function [31:0] hash_combine; +input [31:0] k, v; +begin +// Mixing function taken from boost + hash_combine = k ^ (v + 32'h9e3779b9 + (k<<6) + (k>>2)); +end +endfunction +// hash_get(). Use "hg" to minimize impact on module name path. +// Function to generate a hash based on module name and seed. +function [31:0] hg; +input in1; +reg [(`RANDFUNC_MODNAME_LEN*8)-1:0] modName; +reg [31:0] hash, arg; +integer i; +begin +// hash = 32'h9e3779b9; + hash = 0; +// Convert current module hierarchical name to a reg. +// Note $sformatf() converts strings right to left. i.e. +// Return value contains data from right most data of the string. + modName = int'($sformatf ("%m")); +// Create hash from module name. + for (i = 0; i < (`RANDFUNC_MODNAME_LEN/4); i = i + 1) begin + hash = hash_combine (hash, modName >> (i * 32)); + end +// Also hash in seed command line options. + if($value$plusargs("seed0=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed1=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed2=%d", arg)) + hash = hash_combine(hash, arg); + hg = hash; +end +endfunction +`endif +// Verilog replacement for rollpli. +function [31:0] rollpli; +input [31:0] min; +input [31:0] max; +reg [32:0] diff; +begin + if(initialized !== 1'b1) begin + `ifdef PRAND_VERILOG + seed = {$prand_get_seed(0), 16'b0}; + `else + seed = {hg(1), 16'b0}; + `endif + initialized = 1'b1; + end + diff = max - min + 1; + rollpli = min + seed[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) +// seed = seed * 48'd25214903917 + 48'd11; + seed = seed * 48'h5deece66d + 48'hb; // Hex version +end +endfunction +endmodule +// RIP_END - RANDFUNC.v +`else // ifdef FLATGATES // REGEN_MONOLITHIC_MARK2 +// Model: RANDFUNC - cell_lib Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/cell_db/common/R/RANDFUNC/RANDFUNC_nonpg.vlib#8 +// RIP_START - RANDFUNC.v +// Model: RANDFUNC - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/RANDFUNC.v#4 +// Model: header - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/lib.header#1 +`define RANDFUNC_MODNAME_LEN (32) +module RANDFUNC; +reg [47:0] seed; +reg initialized; +`ifndef PRAND_VERILOG +// hash_combine(). +// Combine hash values. k=key. v=variable +function [31:0] hash_combine; +input [31:0] k, v; +begin +// Mixing function taken from boost + hash_combine = k ^ (v + 32'h9e3779b9 + (k<<6) + (k>>2)); +end +endfunction +// hash_get(). Use "hg" to minimize impact on module name path. +// Function to generate a hash based on module name and seed. +function [31:0] hg; +input in1; +reg [(`RANDFUNC_MODNAME_LEN*8)-1:0] modName; +reg [31:0] hash, arg; +integer i; +begin +// hash = 32'h9e3779b9; + hash = 0; +// Convert current module hierarchical name to a reg. +// Note $sformatf() converts strings right to left. i.e. +// Return value contains data from right most data of the string. + modName = int'($sformatf ("%m")); +// Create hash from module name. + for (i = 0; i < (`RANDFUNC_MODNAME_LEN/4); i = i + 1) begin + hash = hash_combine (hash, modName >> (i * 32)); + end +// Also hash in seed command line options. + if($value$plusargs("seed0=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed1=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed2=%d", arg)) + hash = hash_combine(hash, arg); + hg = hash; +end +endfunction +`endif +// Verilog replacement for rollpli. +function [31:0] rollpli; +input [31:0] min; +input [31:0] max; +reg [32:0] diff; +begin + if(initialized !== 1'b1) begin + `ifdef PRAND_VERILOG + seed = {$prand_get_seed(0), 16'b0}; + `else + seed = {hg(1), 16'b0}; + `endif + initialized = 1'b1; + end + diff = max - min + 1; + rollpli = min + seed[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) +// seed = seed * 48'd25214903917 + 48'd11; + seed = seed * 48'h5deece66d + 48'hb; // Hex version +end +endfunction +endmodule +// RIP_END - RANDFUNC.v +`endif // ifdef FLATGATES // REGEN_MONOLITHIC_MARK3 +`endcelldefine diff --git a/designs/src/NVDLA/vmod/vlibs/RANDFUNC.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/RANDFUNC.vlib.vcp new file mode 100644 index 0000000..984acac --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/RANDFUNC.vlib.vcp @@ -0,0 +1,156 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: RANDFUNC.vlib +`ifdef NV_HWACC + `include "NV_HWACC_VLIB_tick_defines.vh" +`endif +`celldefine +`ifndef FLATGATES // REGEN_MONOLITHIC_MARK1 +// Model: RANDFUNC - cell_lib Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/cell_db/common/R/RANDFUNC/RANDFUNC_nonpg.vlib#8 +// RIP_START - RANDFUNC.v +// Model: RANDFUNC - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/RANDFUNC.v#4 +// Model: header - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/lib.header#1 +`define RANDFUNC_MODNAME_LEN (32) +module RANDFUNC; +reg [47:0] seed; +reg initialized; +`ifndef PRAND_VERILOG +// hash_combine(). +// Combine hash values. k=key. v=variable +function [31:0] hash_combine; +input [31:0] k, v; +begin +// Mixing function taken from boost + hash_combine = k ^ (v + 32'h9e3779b9 + (k<<6) + (k>>2)); +end +endfunction +// hash_get(). Use "hg" to minimize impact on module name path. +// Function to generate a hash based on module name and seed. +function [31:0] hg; +input in1; +reg [(`RANDFUNC_MODNAME_LEN*8)-1:0] modName; +reg [31:0] hash, arg; +integer i; +begin +// hash = 32'h9e3779b9; + hash = 0; +// Convert current module hierarchical name to a reg. +// Note $sformatf() converts strings right to left. i.e. +// Return value contains data from right most data of the string. + modName = int'($sformatf ("%m")); +// Create hash from module name. + for (i = 0; i < (`RANDFUNC_MODNAME_LEN/4); i = i + 1) begin + hash = hash_combine (hash, modName >> (i * 32)); + end +// Also hash in seed command line options. + if($value$plusargs("seed0=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed1=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed2=%d", arg)) + hash = hash_combine(hash, arg); + hg = hash; +end +endfunction +`endif +// Verilog replacement for rollpli. +function [31:0] rollpli; +input [31:0] min; +input [31:0] max; +reg [32:0] diff; +begin + if(initialized !== 1'b1) begin + `ifdef PRAND_VERILOG + seed = {$prand_get_seed(0), 16'b0}; + `else + seed = {hg(1), 16'b0}; + `endif + initialized = 1'b1; + end + diff = max - min + 1; + rollpli = min + seed[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) +// seed = seed * 48'd25214903917 + 48'd11; + seed = seed * 48'h5deece66d + 48'hb; // Hex version +end +endfunction +endmodule +// RIP_END - RANDFUNC.v +`else // ifdef FLATGATES // REGEN_MONOLITHIC_MARK2 +// Model: RANDFUNC - cell_lib Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/cell_db/common/R/RANDFUNC/RANDFUNC_nonpg.vlib#8 +// RIP_START - RANDFUNC.v +// Model: RANDFUNC - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/RANDFUNC.v#4 +// Model: header - rtl Source : //tsmc16ff/libs/tsmc16ff/std_cell/nvidia/v1.0/rtl/lib.header#1 +`define RANDFUNC_MODNAME_LEN (32) +module RANDFUNC; +reg [47:0] seed; +reg initialized; +`ifndef PRAND_VERILOG +// hash_combine(). +// Combine hash values. k=key. v=variable +function [31:0] hash_combine; +input [31:0] k, v; +begin +// Mixing function taken from boost + hash_combine = k ^ (v + 32'h9e3779b9 + (k<<6) + (k>>2)); +end +endfunction +// hash_get(). Use "hg" to minimize impact on module name path. +// Function to generate a hash based on module name and seed. +function [31:0] hg; +input in1; +reg [(`RANDFUNC_MODNAME_LEN*8)-1:0] modName; +reg [31:0] hash, arg; +integer i; +begin +// hash = 32'h9e3779b9; + hash = 0; +// Convert current module hierarchical name to a reg. +// Note $sformatf() converts strings right to left. i.e. +// Return value contains data from right most data of the string. + modName = int'($sformatf ("%m")); +// Create hash from module name. + for (i = 0; i < (`RANDFUNC_MODNAME_LEN/4); i = i + 1) begin + hash = hash_combine (hash, modName >> (i * 32)); + end +// Also hash in seed command line options. + if($value$plusargs("seed0=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed1=%d", arg)) + hash = hash_combine(hash, arg); + if($value$plusargs("seed2=%d", arg)) + hash = hash_combine(hash, arg); + hg = hash; +end +endfunction +`endif +// Verilog replacement for rollpli. +function [31:0] rollpli; +input [31:0] min; +input [31:0] max; +reg [32:0] diff; +begin + if(initialized !== 1'b1) begin + `ifdef PRAND_VERILOG + seed = {$prand_get_seed(0), 16'b0}; + `else + seed = {hg(1), 16'b0}; + `endif + initialized = 1'b1; + end + diff = max - min + 1; + rollpli = min + seed[47:16] % diff; +// magic numbers taken from Java's random class (same as lrand48) +// seed = seed * 48'd25214903917 + 48'd11; + seed = seed * 48'h5deece66d + 48'hb; // Hex version +end +endfunction +endmodule +// RIP_END - RANDFUNC.v +`endif // ifdef FLATGATES // REGEN_MONOLITHIC_MARK3 +`endcelldefine diff --git a/designs/src/NVDLA/vmod/vlibs/SDFCNQD1.v b/designs/src/NVDLA/vmod/vlibs/SDFCNQD1.v new file mode 100644 index 0000000..aec8048 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/SDFCNQD1.v @@ -0,0 +1,32 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: SDFCNQD1.v +module SDFCNQD1 ( + SI + ,D + ,SE + ,CP + ,CDN + ,Q + ); +input SI ; +input D ; +input SE ; +input CP ; +input CDN ; +output Q ; +reg Q; +assign sel = SE ? SI : D; +always @(posedge CP or negedge CDN) +begin + if(~CDN) + Q <= 1'b0; + else + Q <= sel; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/SDFCNQD1.v.vcp b/designs/src/NVDLA/vmod/vlibs/SDFCNQD1.v.vcp new file mode 100644 index 0000000..aec8048 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/SDFCNQD1.v.vcp @@ -0,0 +1,32 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: SDFCNQD1.v +module SDFCNQD1 ( + SI + ,D + ,SE + ,CP + ,CDN + ,Q + ); +input SI ; +input D ; +input SE ; +input CP ; +input CDN ; +output Q ; +reg Q; +assign sel = SE ? SI : D; +always @(posedge CP or negedge CDN) +begin + if(~CDN) + Q <= 1'b0; + else + Q <= sel; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/SDFQD1.v b/designs/src/NVDLA/vmod/vlibs/SDFQD1.v new file mode 100644 index 0000000..54a2efb --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/SDFQD1.v @@ -0,0 +1,27 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: SDFQD1.v +module SDFQD1 ( + SI + ,D + ,SE + ,CP + ,Q + ); +input SI ; +input D ; +input SE ; +input CP ; +output Q ; +reg Q; +assign sel = SE ? SI : D; +always @(posedge CP) +begin + Q <= sel; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/SDFQD1.v.vcp b/designs/src/NVDLA/vmod/vlibs/SDFQD1.v.vcp new file mode 100644 index 0000000..54a2efb --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/SDFQD1.v.vcp @@ -0,0 +1,27 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: SDFQD1.v +module SDFQD1 ( + SI + ,D + ,SE + ,CP + ,Q + ); +input SI ; +input D ; +input SE ; +input CP ; +output Q ; +reg Q; +assign sel = SE ? SI : D; +always @(posedge CP) +begin + Q <= sel; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/SDFSNQD1.v b/designs/src/NVDLA/vmod/vlibs/SDFSNQD1.v new file mode 100644 index 0000000..943d6b5 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/SDFSNQD1.v @@ -0,0 +1,32 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: SDFSNQD1.v +module SDFSNQD1 ( + SI + ,D + ,SE + ,CP + ,SDN + ,Q + ); +input SI ; +input D ; +input SE ; +input CP ; +input SDN ; +output Q ; +reg Q; +assign sel = SE ? SI : D; +always @(posedge CP or negedge SDN) +begin + if(~SDN) + Q <= 1'b1; + else + Q <= sel; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/SDFSNQD1.v.vcp b/designs/src/NVDLA/vmod/vlibs/SDFSNQD1.v.vcp new file mode 100644 index 0000000..943d6b5 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/SDFSNQD1.v.vcp @@ -0,0 +1,32 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: SDFSNQD1.v +module SDFSNQD1 ( + SI + ,D + ,SE + ,CP + ,SDN + ,Q + ); +input SI ; +input D ; +input SE ; +input CP ; +input SDN ; +output Q ; +reg Q; +assign sel = SE ? SI : D; +always @(posedge CP or negedge SDN) +begin + if(~SDN) + Q <= 1'b1; + else + Q <= sel; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/ScanShareSel_JTAG_reg_ext_cg.v b/designs/src/NVDLA/vmod/vlibs/ScanShareSel_JTAG_reg_ext_cg.v new file mode 100644 index 0000000..ec3ba4e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/ScanShareSel_JTAG_reg_ext_cg.v @@ -0,0 +1,66 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: ScanShareSel_JTAG_reg_ext_cg.v +`timescale 1ps/1ps +module ScanShareSel_JTAG_reg_ext_cg ( + D + ,clk + ,reset_ + ,scanin + ,sel + ,shiftDR + ,Q + ,scanout + ); +input clk; +input reset_; +input scanin; +input sel; +input shiftDR; +output scanout; +// synopsys template +// These parameters should be overridden by the module that instantiates this +parameter JTAG_REG_WIDTH = 16; +parameter HAS_RESET = 0; //default is to use 1'b1 as reset_ +parameter [JTAG_REG_WIDTH-1:0] RESET_VALUE = {JTAG_REG_WIDTH{1'b0}}; // spyglass disable W557a -- default to all 0's at reset +input [JTAG_REG_WIDTH-1:0] D; +output [JTAG_REG_WIDTH-1:0] Q; +wire [JTAG_REG_WIDTH-1:0] Q_conn; +wire [JTAG_REG_WIDTH-1:0] next_Q; +wire scanen_wire; +wire scanin_wire; +wire scanout_wire; +NV_BLKBOX_SRC0 UJ_testInst_ess_scanin_buf (.Y(scanin_wire)); +NV_BLKBOX_SRC0 UJ_testInst_ess_scanen_buf (.Y(scanen_wire)); +NV_BLKBOX_BUFFER UJ_testInst_ess_scanout_buf (.A(scanout_wire), .Y(scanout)); +// synopsys dc_tcl_script_begin +// synopsys dc_tcl_script_end +wire qualified_scanin_wire = sel ? scanin : scanin_wire; +wire qualified_scanen_wire = sel ? shiftDR : scanen_wire; +wire clk_wire; +assign next_Q = D; +assign clk_wire = clk; +genvar i; +generate +if (JTAG_REG_WIDTH == 1) begin: sg + assign Q_conn[0] = qualified_scanin_wire; +end else begin: mul + assign Q_conn[JTAG_REG_WIDTH-1:0] = {qualified_scanin_wire, Q[JTAG_REG_WIDTH-1:1]}; +end +for(i=0; istart_assertion_check)) begin + if + ( + (severity_level == 0) + || (severity_level == 2 && !unit_asserts_are_warnings_on) + || (severity_level == 3 && !full_chip_asserts_are_warnings_on) + ) begin + is_error = asserts_are_warnings_on ? 0 : 1; + end + else begin + is_error = 0; + end + if (is_error) begin + error_count = error_count + 1; + supress_msg = error_count > `ASSERT_MAX_REPORT_ERROR ? 1 : 0; + end + else begin + warning_count = warning_count + 1; + supress_msg = warning_count > `ASSERT_MAX_REPORT_WARN ? 1 : 0; + end + `ifdef NV_ERROR_PLI + if (!supress_msg) begin + if (severity_level == 3) begin + $display("COVER : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + else if (is_error) begin + $Error("ERROR : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + else begin + $Warning("WARNING : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + end + `else + if (!supress_msg) begin + if (is_error) begin + $display("ERROR : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + #`ASSERT_ERROR_FINISH_DELAY; + $display("Exiting after assertion failure in module %m"); + $finish; + end + else begin + $display("WARNING : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + end + `endif + end + end +endtask +// assertion_error w/ err_msg param uses more memory (several hundred MB across all assertions on gf100) +task assertion_error_msg; + input [8*15:0] err_msg; + reg supress_msg; + reg is_error; + begin + if ( !assertion_off && ($time>start_assertion_check)) begin + if + ( + (severity_level == 0) + || (severity_level == 2 && !unit_asserts_are_warnings_on) + || (severity_level == 3 && !full_chip_asserts_are_warnings_on) + ) begin + is_error = asserts_are_warnings_on ? 0 : 1; + end + else begin + is_error = 0; + end + if (is_error) begin + error_count = error_count + 1; + supress_msg = error_count > `ASSERT_MAX_REPORT_ERROR ? 1 : 0; + end + else begin + warning_count = warning_count + 1; + supress_msg = warning_count > `ASSERT_MAX_REPORT_WARN ? 1 : 0; + end + `ifdef NV_ERROR_PLI + if (!supress_msg) begin + if (severity_level == 3) begin + $display("COVER : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + else if (is_error) begin + $Error("ERROR : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + else begin + $Warning("WARNING : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + end + `else + if (!supress_msg) begin + if (is_error) begin + $display("ERROR : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + #`ASSERT_ERROR_FINISH_DELAY; + $display("Exiting after assertion failure in module %m"); + $finish; + end + else begin + $display("WARNING : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + end + `endif + end + end +endtask +task assertion_init_msg; + begin + if ( !assertion_off ) begin + $display("ASSERTION_NOTE: initialized @ %m Severity: %0d, Message: %s", + severity_level, msg); + end + end +endtask diff --git a/designs/src/NVDLA/vmod/vlibs/assertion_task.vh.vcp b/designs/src/NVDLA/vmod/vlibs/assertion_task.vh.vcp new file mode 100644 index 0000000..eeb2f90 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/assertion_task.vh.vcp @@ -0,0 +1,178 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: assertion_task.vh +`define ASSERT_MAX_REPORT_ERROR 10 +`define ASSERT_MAX_REPORT_WARN 10 +`define ASSERT_ERROR_FINISH_DELAY 10000 +integer warning_count; +initial warning_count = 0; +reg assertion_off; +initial begin + if ( $test$plusargs( "assertion_off" ) ) begin + assertion_off = 1'b1; + end else begin + assertion_off = 1'b0; + end +end +reg asserts_are_warnings_on; +initial begin + if ( $test$plusargs( "asserts_are_warnings" ) ) begin + asserts_are_warnings_on = 1'b1; + end else begin + asserts_are_warnings_on = 1'b0; + end +end +reg unit_asserts_are_warnings_on; +initial begin + if ( $test$plusargs( "unit_asserts_are_warnings" ) ) begin + unit_asserts_are_warnings_on = 1'b1; + end else begin + unit_asserts_are_warnings_on = 1'b0; + end +end +reg full_chip_asserts_are_warnings_on; +initial begin + if ( $test$plusargs( "full_chip_asserts_are_warnings" ) ) begin + full_chip_asserts_are_warnings_on = 1'b1; + end else begin + full_chip_asserts_are_warnings_on = 1'b0; + end +end +integer start_assertion_check; +initial begin + start_assertion_check=0; + #1; + if ($value$plusargs("ASSERT_START_TIME=%d", start_assertion_check)) begin +//$display("Assertions start getting checked from time %0d",start_assertion_check); + end +end +// assertion_error optimized for memory usage +task assertion_error; + reg supress_msg; + reg is_error; + begin + if ( !assertion_off && ($time>start_assertion_check)) begin + if + ( + (severity_level == 0) + || (severity_level == 2 && !unit_asserts_are_warnings_on) + || (severity_level == 3 && !full_chip_asserts_are_warnings_on) + ) begin + is_error = asserts_are_warnings_on ? 0 : 1; + end + else begin + is_error = 0; + end + if (is_error) begin + error_count = error_count + 1; + supress_msg = error_count > `ASSERT_MAX_REPORT_ERROR ? 1 : 0; + end + else begin + warning_count = warning_count + 1; + supress_msg = warning_count > `ASSERT_MAX_REPORT_WARN ? 1 : 0; + end + `ifdef NV_ERROR_PLI + if (!supress_msg) begin + if (severity_level == 3) begin + $display("COVER : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + else if (is_error) begin + $Error("ERROR : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + else begin + $Warning("WARNING : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + end + `else + if (!supress_msg) begin + if (is_error) begin + $display("ERROR : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + #`ASSERT_ERROR_FINISH_DELAY; + $display("Exiting after assertion failure in module %m"); + $finish; + end + else begin + $display("WARNING : %s : : severity %0d : time %0t : %m", + msg, severity_level, $time); + end + end + `endif + end + end +endtask +// assertion_error w/ err_msg param uses more memory (several hundred MB across all assertions on gf100) +task assertion_error_msg; + input [8*15:0] err_msg; + reg supress_msg; + reg is_error; + begin + if ( !assertion_off && ($time>start_assertion_check)) begin + if + ( + (severity_level == 0) + || (severity_level == 2 && !unit_asserts_are_warnings_on) + || (severity_level == 3 && !full_chip_asserts_are_warnings_on) + ) begin + is_error = asserts_are_warnings_on ? 0 : 1; + end + else begin + is_error = 0; + end + if (is_error) begin + error_count = error_count + 1; + supress_msg = error_count > `ASSERT_MAX_REPORT_ERROR ? 1 : 0; + end + else begin + warning_count = warning_count + 1; + supress_msg = warning_count > `ASSERT_MAX_REPORT_WARN ? 1 : 0; + end + `ifdef NV_ERROR_PLI + if (!supress_msg) begin + if (severity_level == 3) begin + $display("COVER : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + else if (is_error) begin + $Error("ERROR : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + else begin + $Warning("WARNING : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + end + `else + if (!supress_msg) begin + if (is_error) begin + $display("ERROR : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + #`ASSERT_ERROR_FINISH_DELAY; + $display("Exiting after assertion failure in module %m"); + $finish; + end + else begin + $display("WARNING : %s : %0s : severity %0d : time %0t : %m", + msg, err_msg, severity_level, $time); + end + end + `endif + end + end +endtask +task assertion_init_msg; + begin + if ( !assertion_off ) begin + $display("ASSERTION_NOTE: initialized @ %m Severity: %0d, Message: %s", + severity_level, msg); + end + end +endtask diff --git a/designs/src/NVDLA/vmod/vlibs/no_lib_cells.vlib b/designs/src/NVDLA/vmod/vlibs/no_lib_cells.vlib new file mode 100644 index 0000000..4c890fc --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/no_lib_cells.vlib @@ -0,0 +1,8 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: no_lib_cells.vlib diff --git a/designs/src/NVDLA/vmod/vlibs/no_lib_cells.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/no_lib_cells.vlib.vcp new file mode 100644 index 0000000..4c890fc --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/no_lib_cells.vlib.vcp @@ -0,0 +1,8 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: no_lib_cells.vlib diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_always.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_always.vlib new file mode 100644 index 0000000..ec8606e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_always.vlib @@ -0,0 +1,126 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_always.vlib +`ifdef MACROMODULE +macromodule nv_assert_always ( +`else +module nv_assert_always ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module + parameter severity_level = 0; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_, test_expr; +`ifdef ASSERT_ENABLE_ZERROR +`ifndef SYNTHESIS +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_ALWAYS + wire err = !test_expr; +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS + integer error_count; + initial error_count = 0; + `include "assertion_task.vh" + `include "assertion_header.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif // ASSERT_INIT_MSG +`ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (test_expr === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end +`endif +// there is a `define to set reset_ to 1 outside this checker. +// ASSERT_RESET ((1'bx === c0nc_powered_up) ? 1'b1 : c0nc_powered_up) +// however, reset_ is initalized to 0 by VCS. so reset_occurred is 1 although reset_ is 1 all the time + reg reset_reg_; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + reset_reg_ <= reset_; + end + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_reg_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || test_expr === 1'bx + `endif + ) + ) begin + assertion_error; + end + end + end +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_ALWAYS +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_always*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_always*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_always.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_always.vlib.vcp new file mode 100644 index 0000000..ec8606e --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_always.vlib.vcp @@ -0,0 +1,126 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_always.vlib +`ifdef MACROMODULE +macromodule nv_assert_always ( +`else +module nv_assert_always ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module + parameter severity_level = 0; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_, test_expr; +`ifdef ASSERT_ENABLE_ZERROR +`ifndef SYNTHESIS +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_ALWAYS + wire err = !test_expr; +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS + integer error_count; + initial error_count = 0; + `include "assertion_task.vh" + `include "assertion_header.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif // ASSERT_INIT_MSG +`ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (test_expr === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end +`endif +// there is a `define to set reset_ to 1 outside this checker. +// ASSERT_RESET ((1'bx === c0nc_powered_up) ? 1'b1 : c0nc_powered_up) +// however, reset_ is initalized to 0 by VCS. so reset_occurred is 1 although reset_ is 1 all the time + reg reset_reg_; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + reset_reg_ <= reset_; + end + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_reg_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || test_expr === 1'bx + `endif + ) + ) begin + assertion_error; + end + end + end +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_ALWAYS +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_always*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_always*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_at_time_interval.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_at_time_interval.vlib new file mode 100644 index 0000000..b09df21 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_at_time_interval.vlib @@ -0,0 +1,145 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_at_time_interval.vlib +module nv_assert_at_time_interval ( + clk, + reset_, + start_event, + test_expr +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter num_cks=1; + parameter check_overlapping=1; + parameter only_if=0; // if 1, test_expr can only appear if a corresponding +// start_event occurs + parameter options = 0; + parameter msg="VIOLATION"; + input clk, reset_, start_event, test_expr; +`ifndef EMU + reg [((num_cks>0)?num_cks-1:0):0] monitor; + wire [((num_cks>0)?num_cks-1:0):0] monitor_1 = (monitor << 1); +`ifdef FV_ASSERT_ON + output err; + reg err; +`else +`ifndef SYNTHESIS + initial begin + if (num_cks <= 0) begin + `ifndef SYNTHESIS + assertion_error_msg("num_cks parameter<=0"); + `else + begin + end + `endif + end + end + parameter assert_name = "ASSERT_AT_TIME_INTERVAL"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (test_expr === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + if (start_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected start_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif + initial monitor = 0; +`endif +`endif +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + monitor <= 0; + `ifdef FV_ASSERT_ON + err <= 1'b0; + `endif + end else begin + monitor <= (monitor_1 | start_event); + if ((check_overlapping == 0) && (monitor_1 != 0) && start_event) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + `ifndef SYNTHESIS + assertion_error_msg("illegal overlapping condition detected"); + `else + begin + end + `endif + `endif + end + else if (only_if && ~monitor[num_cks-1] && test_expr) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + `ifndef SYNTHESIS + assertion_error_msg("test_expr without start_event"); + `else + begin + end + `endif + `endif + end + else if (monitor[num_cks-1] && ~test_expr) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + `ifndef SYNTHESIS + assertion_error_msg("start_event without test_expr"); + `else + begin + end + `endif + `endif + end + end + end // always +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_at_time_interval*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_at_time_interval*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_at_time_interval.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_at_time_interval.vlib.vcp new file mode 100644 index 0000000..b09df21 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_at_time_interval.vlib.vcp @@ -0,0 +1,145 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_at_time_interval.vlib +module nv_assert_at_time_interval ( + clk, + reset_, + start_event, + test_expr +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter num_cks=1; + parameter check_overlapping=1; + parameter only_if=0; // if 1, test_expr can only appear if a corresponding +// start_event occurs + parameter options = 0; + parameter msg="VIOLATION"; + input clk, reset_, start_event, test_expr; +`ifndef EMU + reg [((num_cks>0)?num_cks-1:0):0] monitor; + wire [((num_cks>0)?num_cks-1:0):0] monitor_1 = (monitor << 1); +`ifdef FV_ASSERT_ON + output err; + reg err; +`else +`ifndef SYNTHESIS + initial begin + if (num_cks <= 0) begin + `ifndef SYNTHESIS + assertion_error_msg("num_cks parameter<=0"); + `else + begin + end + `endif + end + end + parameter assert_name = "ASSERT_AT_TIME_INTERVAL"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (test_expr === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + if (start_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected start_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif + initial monitor = 0; +`endif +`endif +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + monitor <= 0; + `ifdef FV_ASSERT_ON + err <= 1'b0; + `endif + end else begin + monitor <= (monitor_1 | start_event); + if ((check_overlapping == 0) && (monitor_1 != 0) && start_event) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + `ifndef SYNTHESIS + assertion_error_msg("illegal overlapping condition detected"); + `else + begin + end + `endif + `endif + end + else if (only_if && ~monitor[num_cks-1] && test_expr) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + `ifndef SYNTHESIS + assertion_error_msg("test_expr without start_event"); + `else + begin + end + `endif + `endif + end + else if (monitor[num_cks-1] && ~test_expr) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + `ifndef SYNTHESIS + assertion_error_msg("start_event without test_expr"); + `else + begin + end + `endif + `endif + end + end + end // always +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_at_time_interval*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_at_time_interval*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_fifo.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_fifo.vlib new file mode 100644 index 0000000..501f5a5 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_fifo.vlib @@ -0,0 +1,131 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_fifo.vlib +`ifdef MACROMODULE +macromodule nv_assert_fifo ( +`else +module nv_assert_fifo ( +`endif + clk, + reset_, + push, + pop +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module + parameter severity_level = 0; + parameter depth=7; + parameter initial_cnt=0; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk; + input reset_; + input push; + input pop; +`ifndef EMU +`ifdef FV_ASSERT_ON + output err; + reg err; +`else +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_FIFO"; + integer error_count; + initial error_count = 0; + `include "assertion_task.vh" + `include "assertion_header.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (push === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected push to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + if (pop === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected pop to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +`endif +`endif +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`define LOG2_DEPTH (depth>=64 ? 32: (depth>=32 ? 6: (depth>=16 ? 5: (depth>=8 ? 4: (depth>=4 ? 3: (depth>=2 ? 2: 1 )))))) + reg [`LOG2_DEPTH-1:0] cnt; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + cnt<= initial_cnt; + `ifdef FV_ASSERT_ON + err <= 1'b0; + `endif + end else begin + cnt <= cnt + push - pop; + if ( (cnt==depth & push & !pop) || + (cnt==0 & !push & pop) ) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + assertion_error; + `endif + end + end + end +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_fifo*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_fifo*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_fifo.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_fifo.vlib.vcp new file mode 100644 index 0000000..501f5a5 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_fifo.vlib.vcp @@ -0,0 +1,131 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_fifo.vlib +`ifdef MACROMODULE +macromodule nv_assert_fifo ( +`else +module nv_assert_fifo ( +`endif + clk, + reset_, + push, + pop +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module + parameter severity_level = 0; + parameter depth=7; + parameter initial_cnt=0; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk; + input reset_; + input push; + input pop; +`ifndef EMU +`ifdef FV_ASSERT_ON + output err; + reg err; +`else +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_FIFO"; + integer error_count; + initial error_count = 0; + `include "assertion_task.vh" + `include "assertion_header.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (push === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected push to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + if (pop === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected pop to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +`endif +`endif +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`define LOG2_DEPTH (depth>=64 ? 32: (depth>=32 ? 6: (depth>=16 ? 5: (depth>=8 ? 4: (depth>=4 ? 3: (depth>=2 ? 2: 1 )))))) + reg [`LOG2_DEPTH-1:0] cnt; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + cnt<= initial_cnt; + `ifdef FV_ASSERT_ON + err <= 1'b0; + `endif + end else begin + cnt <= cnt + push - pop; + if ( (cnt==depth & push & !pop) || + (cnt==0 & !push & pop) ) begin + `ifdef FV_ASSERT_ON + err <= 1'b1; + `else + assertion_error; + `endif + end + end + end +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_fifo*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_fifo*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_hold_throughout_event_interval.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_hold_throughout_event_interval.vlib new file mode 100644 index 0000000..d34403f --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_hold_throughout_event_interval.vlib @@ -0,0 +1,178 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_hold_throughout_event_interval.vlib +`ifdef MACROMODULE +macromodule nv_assert_hold_throughout_event_interval ( +`else +module nv_assert_hold_throughout_event_interval ( +`endif + clk, + reset_, + start_event, + test_expr, + end_event +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level=0; + parameter width=1; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk; + input reset_; + input start_event; + input [width-1:0] test_expr; + input end_event; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU + reg r_change; + reg [width-1:0] r_test_expr; + reg r_state; + parameter WIN_UNCHANGE_START = 1'b0; + parameter WIN_UNCHANGE_CHECK = 1'b1; +`ifdef FV_ASSERT_ON + output err; +//reg err; +`else +`ifndef SYNTHESIS +// parameter assert_name = "nv_assert_hold_throughout_event_interval"; + initial begin + r_state=WIN_UNCHANGE_START; + r_change=1'b0; + end + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (end_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected end_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + initial begin + #1000; + if (start_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected start_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +`endif +`endif +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + r_state<=WIN_UNCHANGE_START; + r_change<=1'b0; + `ifdef FV_ASSERT_ON +// err <= 1'b0; + `endif + end else begin + if (reset_ != 0) begin // active low reset + case (r_state) + WIN_UNCHANGE_START: + if (start_event == 1'b1) begin + r_change <= 1'b0; + r_state <= WIN_UNCHANGE_CHECK; + r_test_expr <= test_expr; + end + WIN_UNCHANGE_CHECK: + begin + if (r_test_expr != test_expr) begin + r_change <= 1'b1; + end +// go to start state on last check + if (end_event == 1'b1) begin + r_state <= WIN_UNCHANGE_START; + end +// Check that the property is true + if ((r_change == 1'b1) || + (r_test_expr != test_expr)) begin + `ifdef FV_ASSERT_ON +//err <= 1'b1; + `else + assertion_error; + `endif + end + r_test_expr <= test_expr; + end + endcase + end + end + end // always +// no delay for err, so SV09 won't treat it as weekly embeddeing. used for +// SFV + `ifdef FV_ASSERT_ON + assign err = ((r_state == WIN_UNCHANGE_CHECK) && (r_test_expr != test_expr)); + `endif +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_hold_throughout_event_interval*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_hold_throughout_event_interval*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_hold_throughout_event_interval.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_hold_throughout_event_interval.vlib.vcp new file mode 100644 index 0000000..d34403f --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_hold_throughout_event_interval.vlib.vcp @@ -0,0 +1,178 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_hold_throughout_event_interval.vlib +`ifdef MACROMODULE +macromodule nv_assert_hold_throughout_event_interval ( +`else +module nv_assert_hold_throughout_event_interval ( +`endif + clk, + reset_, + start_event, + test_expr, + end_event +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level=0; + parameter width=1; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk; + input reset_; + input start_event; + input [width-1:0] test_expr; + input end_event; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU + reg r_change; + reg [width-1:0] r_test_expr; + reg r_state; + parameter WIN_UNCHANGE_START = 1'b0; + parameter WIN_UNCHANGE_CHECK = 1'b1; +`ifdef FV_ASSERT_ON + output err; +//reg err; +`else +`ifndef SYNTHESIS +// parameter assert_name = "nv_assert_hold_throughout_event_interval"; + initial begin + r_state=WIN_UNCHANGE_START; + r_change=1'b0; + end + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (end_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected end_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + initial begin + #1000; + if (start_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected start_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +`endif +`endif +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + r_state<=WIN_UNCHANGE_START; + r_change<=1'b0; + `ifdef FV_ASSERT_ON +// err <= 1'b0; + `endif + end else begin + if (reset_ != 0) begin // active low reset + case (r_state) + WIN_UNCHANGE_START: + if (start_event == 1'b1) begin + r_change <= 1'b0; + r_state <= WIN_UNCHANGE_CHECK; + r_test_expr <= test_expr; + end + WIN_UNCHANGE_CHECK: + begin + if (r_test_expr != test_expr) begin + r_change <= 1'b1; + end +// go to start state on last check + if (end_event == 1'b1) begin + r_state <= WIN_UNCHANGE_START; + end +// Check that the property is true + if ((r_change == 1'b1) || + (r_test_expr != test_expr)) begin + `ifdef FV_ASSERT_ON +//err <= 1'b1; + `else + assertion_error; + `endif + end + r_test_expr <= test_expr; + end + endcase + end + end + end // always +// no delay for err, so SV09 won't treat it as weekly embeddeing. used for +// SFV + `ifdef FV_ASSERT_ON + assign err = ((r_state == WIN_UNCHANGE_CHECK) && (r_test_expr != test_expr)); + `endif +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_hold_throughout_event_interval*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_hold_throughout_event_interval*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_never.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_never.vlib new file mode 100644 index 0000000..62f4e74 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_never.vlib @@ -0,0 +1,128 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_never.vlib +`ifdef MACROMODULE +macromodule nv_assert_never ( +`else +module nv_assert_never ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_, test_expr; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_NEVER + wire err = test_expr; +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_NEVER"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (test_expr === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +// there is a `define to set reset_ to 1 outside this checker. +// ASSERT_RESET ((1'bx === c0nc_powered_up) ? 1'b1 : c0nc_powered_up) +// however, reset_ is initalized to 0 by VCS. so reset_occurred is 1 although reset_ is 1 all the time + reg reset_reg_; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + reset_reg_ <= reset_; + end + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_reg_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || test_expr === 1'bx + `endif + ) + ) begin + assertion_error; + end + end + end // always +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_NEVER +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_never*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_never*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_never.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_never.vlib.vcp new file mode 100644 index 0000000..62f4e74 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_never.vlib.vcp @@ -0,0 +1,128 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_never.vlib +`ifdef MACROMODULE +macromodule nv_assert_never ( +`else +module nv_assert_never ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_, test_expr; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_NEVER + wire err = test_expr; +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_NEVER"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (test_expr === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +// there is a `define to set reset_ to 1 outside this checker. +// ASSERT_RESET ((1'bx === c0nc_powered_up) ? 1'b1 : c0nc_powered_up) +// however, reset_ is initalized to 0 by VCS. so reset_occurred is 1 although reset_ is 1 all the time + reg reset_reg_; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + reset_reg_ <= reset_; + end + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_reg_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || test_expr === 1'bx + `endif + ) + ) begin + assertion_error; + end + end + end // always +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_NEVER +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_never*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_never*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_no_x.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_no_x.vlib new file mode 100644 index 0000000..34eeecc --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_no_x.vlib @@ -0,0 +1,119 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_no_x.vlib +`ifdef MACROMODULE +macromodule nv_assert_no_x (clk, reset_, start_event, test_expr); +`else +module nv_assert_no_x (clk, reset_, start_event, test_expr); +`endif +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter width=32; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_; + input [width-1:0] test_expr; + input start_event; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef DISABLE_ASSERT_NO_X +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_NO_X"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (start_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected start_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + `endif + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_ == 0); + reset_occurred = 1'b1; + end + wire start_event_qual = reset_occurred & start_event; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (reset_ != 1'b0) begin + if (start_event_qual && (^test_expr === 1'bx)) begin + assertion_error; + if (!assertion_off && ($time>start_assertion_check) && + (error_count <= `ASSERT_MAX_REPORT_ERROR) && (warning_count <= `ASSERT_MAX_REPORT_WARN)) begin + $display("%m: Value of the signal = %d`h%h", width, test_expr); + end + end + end + end // always +`endif // SYNTHESIS +`endif // DISABLE_ASSERT_NO_X +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_no_x*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_no_x*] } +`endif // ifdef EMU +// no_x check should not be done by FV. err in the include file is not defined here +//`ifdef FV_ASSERT_ON +// `include "common_sva_assert.sva" +//`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_no_x.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_no_x.vlib.vcp new file mode 100644 index 0000000..34eeecc --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_no_x.vlib.vcp @@ -0,0 +1,119 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_no_x.vlib +`ifdef MACROMODULE +macromodule nv_assert_no_x (clk, reset_, start_event, test_expr); +`else +module nv_assert_no_x (clk, reset_, start_event, test_expr); +`endif +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter width=32; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_; + input [width-1:0] test_expr; + input start_event; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef DISABLE_ASSERT_NO_X +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_NO_X"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (start_event === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected start_event to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + `endif + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_ == 0); + reset_occurred = 1'b1; + end + wire start_event_qual = reset_occurred & start_event; +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (reset_ != 1'b0) begin + if (start_event_qual && (^test_expr === 1'bx)) begin + assertion_error; + if (!assertion_off && ($time>start_assertion_check) && + (error_count <= `ASSERT_MAX_REPORT_ERROR) && (warning_count <= `ASSERT_MAX_REPORT_WARN)) begin + $display("%m: Value of the signal = %d`h%h", width, test_expr); + end + end + end + end // always +`endif // SYNTHESIS +`endif // DISABLE_ASSERT_NO_X +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_no_x*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_no_x*] } +`endif // ifdef EMU +// no_x check should not be done by FV. err in the include file is not defined here +//`ifdef FV_ASSERT_ON +// `include "common_sva_assert.sva" +//`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_one_hot.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_one_hot.vlib new file mode 100644 index 0000000..bc3a1e6 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_one_hot.vlib @@ -0,0 +1,122 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_one_hot.vlib +`ifdef MACROMODULE +macromodule nv_assert_one_hot ( +`else +module nv_assert_one_hot ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter width=32; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_; + input [width-1:0] test_expr; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_ONE_HOT + wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1}; + wire err = (|(test_expr & test_expr_1)) || !(|test_expr); +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_ONE_HOT"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + `endif + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || (^test_expr === 1'bx) + `endif + ) + ) begin + assertion_error; + end + end + end +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_ONE_HOT +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_one_hot*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_one_hot*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_one_hot.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_one_hot.vlib.vcp new file mode 100644 index 0000000..bc3a1e6 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_one_hot.vlib.vcp @@ -0,0 +1,122 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_one_hot.vlib +`ifdef MACROMODULE +macromodule nv_assert_one_hot ( +`else +module nv_assert_one_hot ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter width=32; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_; + input [width-1:0] test_expr; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_ONE_HOT + wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1}; + wire err = (|(test_expr & test_expr_1)) || !(|test_expr); +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_ONE_HOT"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + `endif + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || (^test_expr === 1'bx) + `endif + ) + ) begin + assertion_error; + end + end + end +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_ONE_HOT +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_one_hot*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_one_hot*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_vld_credit_max.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_vld_credit_max.vlib new file mode 100644 index 0000000..2bbb628 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_vld_credit_max.vlib @@ -0,0 +1,134 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_vld_credit_max.vlib +`ifdef MACROMODULE +macromodule nv_assert_vld_credit_max ( +`else +module nv_assert_vld_credit_max ( +`endif + clk, + reset_, + vld, + credit +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module + parameter severity_level = 0; + parameter init_credits = 1; + parameter credits_max = 65; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk; + input reset_; + input vld; + input credit; +`ifndef EMU +`ifdef FV_ASSERT_ON + output err; + wire err; + reg reg_err; +`else +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_VLD_CREDIT_MAX"; + integer error_count; + initial error_count = 0; + `include "assertion_task.vh" + `include "assertion_header.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (vld === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected vld to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + if (credit === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected credit to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +`endif +`endif + `define LOG2_CREDITS_MAX (credits_max>=64 ? 32: (credits_max>=32 ? 6: (credits_max>=16 ? 5: (credits_max>=8 ? 4: (credits_max>=4 ? 3: (credits_max>=2 ? 2: 1 )))))) + reg [`LOG2_CREDITS_MAX-1:0] credits; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + credits <= init_credits; + `ifdef FV_ASSERT_ON + reg_err <= 1'b0; + `endif + end else begin + credits <= credits + credit - vld; + if (vld && credits==0 && !credit) begin + `ifdef FV_ASSERT_ON + reg_err <= 1'b1; + `else + assertion_error; + `endif + end + end + end +`ifdef FV_ASSERT_ON +assign err = reg_err || (options==1 && vld && credits==0 && !credit); +`endif +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_vld_credit_max*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_vld_credit_max*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_vld_credit_max.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_vld_credit_max.vlib.vcp new file mode 100644 index 0000000..2bbb628 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_vld_credit_max.vlib.vcp @@ -0,0 +1,134 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_vld_credit_max.vlib +`ifdef MACROMODULE +macromodule nv_assert_vld_credit_max ( +`else +module nv_assert_vld_credit_max ( +`endif + clk, + reset_, + vld, + credit +`ifdef FV_ASSERT_ON + , err +`endif +); +//VCS coverage exclude_module + parameter severity_level = 0; + parameter init_credits = 1; + parameter credits_max = 65; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk; + input reset_; + input vld; + input credit; +`ifndef EMU +`ifdef FV_ASSERT_ON + output err; + wire err; + reg reg_err; +`else +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_VLD_CREDIT_MAX"; + integer error_count; + initial error_count = 0; + `include "assertion_task.vh" + `include "assertion_header.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + if (vld === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected vld to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + initial begin + #1000; + if (credit === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected credit to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + `endif +`endif +`endif + `define LOG2_CREDITS_MAX (credits_max>=64 ? 32: (credits_max>=32 ? 6: (credits_max>=16 ? 5: (credits_max>=8 ? 4: (credits_max>=4 ? 3: (credits_max>=2 ? 2: 1 )))))) + reg [`LOG2_CREDITS_MAX-1:0] credits; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if (~reset_) begin + credits <= init_credits; + `ifdef FV_ASSERT_ON + reg_err <= 1'b0; + `endif + end else begin + credits <= credits + credit - vld; + if (vld && credits==0 && !credit) begin + `ifdef FV_ASSERT_ON + reg_err <= 1'b1; + `else + assertion_error; + `endif + end + end + end +`ifdef FV_ASSERT_ON +assign err = reg_err || (options==1 && vld && credits==0 && !credit); +`endif +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_vld_credit_max*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_vld_credit_max*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_zero_one_hot.vlib b/designs/src/NVDLA/vmod/vlibs/nv_assert_zero_one_hot.vlib new file mode 100644 index 0000000..308a428 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_zero_one_hot.vlib @@ -0,0 +1,122 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_zero_one_hot.vlib +`ifdef MACROMODULE +macromodule nv_assert_zero_one_hot ( +`else +module nv_assert_zero_one_hot ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter width=32; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_; + input [width-1:0] test_expr; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_ZERO_ONE_HOT + wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1}; + wire err = |(test_expr & test_expr_1); +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_ZERO_ONE_HOT"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + `endif + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || (^test_expr === 1'bx) + `endif + ) + ) begin + assertion_error; + end + end + end +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_ZERO_ONE_HOT +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_zero_one_hot*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_zero_one_hot*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/nv_assert_zero_one_hot.vlib.vcp b/designs/src/NVDLA/vmod/vlibs/nv_assert_zero_one_hot.vlib.vcp new file mode 100644 index 0000000..308a428 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/nv_assert_zero_one_hot.vlib.vcp @@ -0,0 +1,122 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: nv_assert_zero_one_hot.vlib +`ifdef MACROMODULE +macromodule nv_assert_zero_one_hot ( +`else +module nv_assert_zero_one_hot ( +`endif + clk, + reset_, + test_expr +); +//VCS coverage exclude_module +// synopsys template + parameter severity_level = 0; + parameter width=32; + parameter options = 0; +`ifdef DISABLE_ASSERT_MSG + parameter [0:0] msg=""; +`else + `ifdef TRUNCATE_ASSERT_MSG + parameter [64*8-1:0] msg="VIOLATION"; + `else + parameter msg="VIOLATION"; + `endif +`endif + input clk, reset_; + input [width-1:0] test_expr; +`ifndef SYNTHESIS +`ifdef ASSERT_ENABLE_ZERROR +initial begin + #1000; + if ((reset_ === 1'bz)) begin + $display("ZERROR: %m (%t) : Fix the unconnected reset to this assertion.", $time); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end +end +`endif +`endif +`ifndef EMU +`ifndef DISABLE_ASSERT_ZERO_ONE_HOT + wire [width-1:0] test_expr_1 = test_expr - {{width-1{1'b0}},1'b1}; + wire err = |(test_expr & test_expr_1); +`ifndef FV_ASSERT_ON +`ifndef SYNTHESIS +// parameter assert_name = "ASSERT_ZERO_ONE_HOT"; + integer error_count; + initial error_count = 0; + `include "assertion_header.vh" + `include "assertion_task.vh" + `ifdef ASSERT_INIT_MSG + initial + assertion_init_msg; // Call the User Defined Init Message Routine + `endif + `ifdef ASSERT_ENABLE_ZERROR + initial begin + #1000; + for (integer i=0; i<= (width-1); i=i+1) begin + if (test_expr[i] === 1'bz) begin + $display("ZERROR: %m (%t) : Fix the unconnected test_expr[%d] to this assertion.", $time, i); + `ifdef ASSERT_EXIT_ON_ZERROR + $finish; + `endif + end + end + end + `endif + reg reset_occurred; + initial + begin + reset_occurred = 1'b0; + wait (reset_ == 0); + reset_occurred = 1'b1; + end +`ifdef FV_ASSERT_SYNCH_RESET +always @(posedge clk) begin +`else +always @(posedge clk or negedge reset_) begin +`endif + if ( reset_ === 1'b0 + || reset_ === 1'bx + || reset_ === 1'bz) begin + end else begin + if ( reset_occurred + && ( err + `ifdef ASSERT_XCHECK_ON + || (^test_expr === 1'bx) + `endif + ) + ) begin + assertion_error; + end + end + end +`endif // SYNTHESIS +`endif // FV_ASSERT_ON +`endif // DISABLE_ASSERT_ZERO_ONE_HOT +`endif // EMU +// Instantiating a dummy buffer +// CKBD4 UI_DummyBuf (.I(clk), .Z()); +// inside the assertion vlib, so that +// the assertion module is NOT optimized away +// during DC & RC emulation physical synthesis +// Also adding embedded DC and RC dont-touch settings +// on the assertion module +`ifdef EMU + CKBD4 UI_DummyBuf (.I(clk), .Z()); +// synopsys dc_script_begin +// synopsys dc_script_end +// g2c if { [find / -null_ok -subdesign nv_assert_zero_one_hot*] != {} } { set_attr preserve 1 [find / -subdesign nv_assert_zero_one_hot*] } +`endif // ifdef EMU +`ifdef FV_ASSERT_ON + `include "common_sva_assert.sva" +`endif +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_read_clock.v b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_read_clock.v new file mode 100644 index 0000000..69a6f48 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_read_clock.v @@ -0,0 +1,28 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: oneHotClk_async_read_clock.v +`timescale 1ps/1ps +module oneHotClk_async_read_clock ( + enable_r + ); +output enable_r; +// If one_hot_enable = 0, (functional mode, i.e. enable_w = 1 & enable_r = 1) +// If one_hot_enable = 1, (test mode, i.e. enable_w = TP & enable_r = ~TP) due to ANDing with functional enable either read or write CG will be off for the pattern. +// enable_w = ~one_hot_enable | TP +// enable_w & func_en +// enable_r = ~one_hot_enable | ~TP +// enable_r & func_en +wire one_hot_enable; +wire tp; +// synopsys template +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_asyncfifo_onehotclk_read (.Y(one_hot_enable)); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_asyncfifo_onehotclk_read (.Y(tp)); +assign enable_r = ((!one_hot_enable) || (!tp)); +// synopsys dc_script_begin +// synopsys dc_script_end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_read_clock.v.vcp b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_read_clock.v.vcp new file mode 100644 index 0000000..69a6f48 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_read_clock.v.vcp @@ -0,0 +1,28 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: oneHotClk_async_read_clock.v +`timescale 1ps/1ps +module oneHotClk_async_read_clock ( + enable_r + ); +output enable_r; +// If one_hot_enable = 0, (functional mode, i.e. enable_w = 1 & enable_r = 1) +// If one_hot_enable = 1, (test mode, i.e. enable_w = TP & enable_r = ~TP) due to ANDing with functional enable either read or write CG will be off for the pattern. +// enable_w = ~one_hot_enable | TP +// enable_w & func_en +// enable_r = ~one_hot_enable | ~TP +// enable_r & func_en +wire one_hot_enable; +wire tp; +// synopsys template +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_asyncfifo_onehotclk_read (.Y(one_hot_enable)); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_asyncfifo_onehotclk_read (.Y(tp)); +assign enable_r = ((!one_hot_enable) || (!tp)); +// synopsys dc_script_begin +// synopsys dc_script_end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_write_clock.v b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_write_clock.v new file mode 100644 index 0000000..f1d8830 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_write_clock.v @@ -0,0 +1,28 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: oneHotClk_async_write_clock.v +`timescale 1ps/1ps +module oneHotClk_async_write_clock ( + enable_w + ); +output enable_w; +// If one_hot_enable = 0, (functional mode, i.e. enable_w = 1 & enable_r = 1) +// If one_hot_enable = 1, (test mode, i.e. enable_w = TP & enable_r = ~TP) due to ANDing with functional enable either read or write CG will be off for the pattern. +// enable_w = ~one_hot_enable | TP +// enable_w & func_en +// enable_r = ~one_hot_enable | ~TP +// enable_r & func_en +wire one_hot_enable; +wire tp; +// synopsys template +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_asyncfifo_onehotclk_write (.Y(one_hot_enable)); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_asyncfifo_onehotclk_write (.Y(tp)); +assign enable_w = ((!one_hot_enable) || tp ); +// synopsys dc_script_begin +// synopsys dc_script_end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_write_clock.v.vcp b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_write_clock.v.vcp new file mode 100644 index 0000000..f1d8830 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/oneHotClk_async_write_clock.v.vcp @@ -0,0 +1,28 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: oneHotClk_async_write_clock.v +`timescale 1ps/1ps +module oneHotClk_async_write_clock ( + enable_w + ); +output enable_w; +// If one_hot_enable = 0, (functional mode, i.e. enable_w = 1 & enable_r = 1) +// If one_hot_enable = 1, (test mode, i.e. enable_w = TP & enable_r = ~TP) due to ANDing with functional enable either read or write CG will be off for the pattern. +// enable_w = ~one_hot_enable | TP +// enable_w & func_en +// enable_r = ~one_hot_enable | ~TP +// enable_r & func_en +wire one_hot_enable; +wire tp; +// synopsys template +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_asyncfifo_onehotclk_write (.Y(one_hot_enable)); +NV_BLKBOX_SRC0 UJ_dft_xclamp_scan_asyncfifo_onehotclk_write (.Y(tp)); +assign enable_w = ((!one_hot_enable) || tp ); +// synopsys dc_script_begin +// synopsys dc_script_end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SDFCNQD1PO4.v b/designs/src/NVDLA/vmod/vlibs/p_SDFCNQD1PO4.v new file mode 100644 index 0000000..6922fd0 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SDFCNQD1PO4.v @@ -0,0 +1,22 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SDFCNQD1PO4.v +module p_SDFCNQD1PO4 (D,CP,CDN,Q); +input D; +input CP; +input CDN; +output Q; +reg Q; +always @(posedge CP or negedge CDN) +begin + if(~CDN) + Q <= 1'b0; + else + Q <= D; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SDFCNQD1PO4.v.vcp b/designs/src/NVDLA/vmod/vlibs/p_SDFCNQD1PO4.v.vcp new file mode 100644 index 0000000..6922fd0 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SDFCNQD1PO4.v.vcp @@ -0,0 +1,22 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SDFCNQD1PO4.v +module p_SDFCNQD1PO4 (D,CP,CDN,Q); +input D; +input CP; +input CDN; +output Q; +reg Q; +always @(posedge CP or negedge CDN) +begin + if(~CDN) + Q <= 1'b0; + else + Q <= D; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC2DO_C_PP.v b/designs/src/NVDLA/vmod/vlibs/p_SSYNC2DO_C_PP.v new file mode 100644 index 0000000..3ef9a64 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC2DO_C_PP.v @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC2DO_C_PP.v +module p_SSYNC2DO_C_PP ( + clk + ,d + ,clr_ + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +input clr_ ; +output q ; +reg q,d0; +always @(posedge clk or negedge clr_) +begin + if(~clr_) + {q,d0} <= 2'd0; + else + {q,d0} <= {d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC2DO_C_PP.v.vcp b/designs/src/NVDLA/vmod/vlibs/p_SSYNC2DO_C_PP.v.vcp new file mode 100644 index 0000000..3ef9a64 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC2DO_C_PP.v.vcp @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC2DO_C_PP.v +module p_SSYNC2DO_C_PP ( + clk + ,d + ,clr_ + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +input clr_ ; +output q ; +reg q,d0; +always @(posedge clk or negedge clr_) +begin + if(~clr_) + {q,d0} <= 2'd0; + else + {q,d0} <= {d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO.v b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO.v new file mode 100644 index 0000000..0d4de31 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO.v @@ -0,0 +1,24 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC3DO.v +module p_SSYNC3DO ( + clk + ,d + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +output q ; +reg q, d1, d0; +always @(posedge clk) +begin + {q,d1,d0} <= {d1,d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO.v.vcp b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO.v.vcp new file mode 100644 index 0000000..0d4de31 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO.v.vcp @@ -0,0 +1,24 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC3DO.v +module p_SSYNC3DO ( + clk + ,d + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +output q ; +reg q, d1, d0; +always @(posedge clk) +begin + {q,d1,d0} <= {d1,d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_C_PPP.v b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_C_PPP.v new file mode 100644 index 0000000..8d29329 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_C_PPP.v @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC3DO_C_PPP.v +module p_SSYNC3DO_C_PPP ( + clk + ,d + ,clr_ + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +input clr_ ; +output q ; +reg q,d1,d0; +always @(posedge clk or negedge clr_) +begin + if(~clr_) + {q,d1,d0} <= 3'd0; + else + {q,d1,d0} <= {d1,d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_C_PPP.v.vcp b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_C_PPP.v.vcp new file mode 100644 index 0000000..8d29329 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_C_PPP.v.vcp @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC3DO_C_PPP.v +module p_SSYNC3DO_C_PPP ( + clk + ,d + ,clr_ + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +input clr_ ; +output q ; +reg q,d1,d0; +always @(posedge clk or negedge clr_) +begin + if(~clr_) + {q,d1,d0} <= 3'd0; + else + {q,d1,d0} <= {d1,d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_S_PPP.v b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_S_PPP.v new file mode 100644 index 0000000..bb05df7 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_S_PPP.v @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC3DO_S_PPP.v +module p_SSYNC3DO_S_PPP ( + clk + ,d + ,set_ + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +input set_ ; +output q ; +reg q,d1,d0; +always @(posedge clk or negedge set_) +begin + if(~set_) + {q,d1,d0} <= 3'b111; + else + {q,d1,d0} <= {d1,d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_S_PPP.v.vcp b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_S_PPP.v.vcp new file mode 100644 index 0000000..bb05df7 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_SSYNC3DO_S_PPP.v.vcp @@ -0,0 +1,29 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_SSYNC3DO_S_PPP.v +module p_SSYNC3DO_S_PPP ( + clk + ,d + ,set_ + ,q + ); +//--------------------------------------- +//IO DECLARATIONS +input clk ; +input d ; +input set_ ; +output q ; +reg q,d1,d0; +always @(posedge clk or negedge set_) +begin + if(~set_) + {q,d1,d0} <= 3'b111; + else + {q,d1,d0} <= {d1,d0,d}; +end +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v b/designs/src/NVDLA/vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v new file mode 100644 index 0000000..4ddecc8 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v @@ -0,0 +1,51 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_STRICTSYNC3DOTM_C_PPP.v +module p_STRICTSYNC3DOTM_C_PPP ( + SRC_D_NEXT + ,SRC_CLK + ,SRC_CLRN + ,DST_CLK + ,DST_CLRN + ,SRC_D + ,DST_Q + ,ATPG_CTL + ,TEST_MODE + ); +input SRC_D_NEXT ; +input SRC_CLK ; +input SRC_CLRN ; +input DST_CLK ; +input DST_CLRN ; +output SRC_D ; +output DST_Q ; +input ATPG_CTL ; +input TEST_MODE ; +wire src_sel,dst_sel; +reg src_d_f; +//reg dst_d2,dst_d1,dst_d0; +assign src_sel = SRC_D_NEXT; +always @(posedge SRC_CLK or negedge SRC_CLRN) +begin + if(~SRC_CLRN) + src_d_f <= 1'b0; + else + src_d_f <= src_sel; +end +assign SRC_D = src_d_f; +assign dst_sel = src_d_f; +//always @(posedge DST_CLK or negedge DST_CLRN) +//begin +// if(~DST_CLRN) +// {dst_d2,dst_d1,dst_d0} <= 3'd0; +// else +// {dst_d2,dst_d1,dst_d0} <= {dst_d1,dst_d0,dst_sel}; +//end +//assign DST_Q = dst_d2; +p_SSYNC3DO_C_PPP sync3d(.clk (DST_CLK),.d (dst_sel), .clr_ (DST_CLRN) ,.q(DST_Q)); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v.vcp b/designs/src/NVDLA/vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v.vcp new file mode 100644 index 0000000..4ddecc8 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/p_STRICTSYNC3DOTM_C_PPP.v.vcp @@ -0,0 +1,51 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: p_STRICTSYNC3DOTM_C_PPP.v +module p_STRICTSYNC3DOTM_C_PPP ( + SRC_D_NEXT + ,SRC_CLK + ,SRC_CLRN + ,DST_CLK + ,DST_CLRN + ,SRC_D + ,DST_Q + ,ATPG_CTL + ,TEST_MODE + ); +input SRC_D_NEXT ; +input SRC_CLK ; +input SRC_CLRN ; +input DST_CLK ; +input DST_CLRN ; +output SRC_D ; +output DST_Q ; +input ATPG_CTL ; +input TEST_MODE ; +wire src_sel,dst_sel; +reg src_d_f; +//reg dst_d2,dst_d1,dst_d0; +assign src_sel = SRC_D_NEXT; +always @(posedge SRC_CLK or negedge SRC_CLRN) +begin + if(~SRC_CLRN) + src_d_f <= 1'b0; + else + src_d_f <= src_sel; +end +assign SRC_D = src_d_f; +assign dst_sel = src_d_f; +//always @(posedge DST_CLK or negedge DST_CLRN) +//begin +// if(~DST_CLRN) +// {dst_d2,dst_d1,dst_d0} <= 3'd0; +// else +// {dst_d2,dst_d1,dst_d0} <= {dst_d1,dst_d0,dst_sel}; +//end +//assign DST_Q = dst_d2; +p_SSYNC3DO_C_PPP sync3d(.clk (DST_CLK),.d (dst_sel), .clr_ (DST_CLRN) ,.q(DST_Q)); +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync2d_c_pp.v b/designs/src/NVDLA/vmod/vlibs/sync2d_c_pp.v new file mode 100644 index 0000000..ada97f7 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync2d_c_pp.v @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync2d_c_pp.v +module sync2d_c_pp ( d, clk, clr_, q ); +input d, clk, clr_; +output q; + p_SSYNC2DO_C_PP NV_GENERIC_CELL( .d(d), .clk (clk), .clr_(clr_), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync2d_c_pp] != {} } { set_attr preserve 1 [find / -subdesign sync2d_c_pp] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync2d_c_pp.v.vcp b/designs/src/NVDLA/vmod/vlibs/sync2d_c_pp.v.vcp new file mode 100644 index 0000000..ada97f7 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync2d_c_pp.v.vcp @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync2d_c_pp.v +module sync2d_c_pp ( d, clk, clr_, q ); +input d, clk, clr_; +output q; + p_SSYNC2DO_C_PP NV_GENERIC_CELL( .d(d), .clk (clk), .clr_(clr_), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync2d_c_pp] != {} } { set_attr preserve 1 [find / -subdesign sync2d_c_pp] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync3d.v b/designs/src/NVDLA/vmod/vlibs/sync3d.v new file mode 100644 index 0000000..3d834b9 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync3d.v @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync3d.v +module sync3d ( d, clk, q); +input d, clk; +output q; + p_SSYNC3DO NV_GENERIC_CELL( .d(d), .clk(clk), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync3d] != {} } { set_attr preserve 1 [find / -subdesign sync3d] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync3d.v.vcp b/designs/src/NVDLA/vmod/vlibs/sync3d.v.vcp new file mode 100644 index 0000000..3d834b9 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync3d.v.vcp @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync3d.v +module sync3d ( d, clk, q); +input d, clk; +output q; + p_SSYNC3DO NV_GENERIC_CELL( .d(d), .clk(clk), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync3d] != {} } { set_attr preserve 1 [find / -subdesign sync3d] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync3d_c_ppp.v b/designs/src/NVDLA/vmod/vlibs/sync3d_c_ppp.v new file mode 100644 index 0000000..b2abb37 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync3d_c_ppp.v @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync3d_c_ppp.v +module sync3d_c_ppp ( d, clk, clr_, q ); +input d, clk, clr_; +output q; + p_SSYNC3DO_C_PPP NV_GENERIC_CELL( .d(d), .clk(clk), .clr_(clr_), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync3d_c_ppp] != {} } { set_attr preserve 1 [find / -subdesign sync3d_c_ppp] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync3d_c_ppp.v.vcp b/designs/src/NVDLA/vmod/vlibs/sync3d_c_ppp.v.vcp new file mode 100644 index 0000000..b2abb37 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync3d_c_ppp.v.vcp @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync3d_c_ppp.v +module sync3d_c_ppp ( d, clk, clr_, q ); +input d, clk, clr_; +output q; + p_SSYNC3DO_C_PPP NV_GENERIC_CELL( .d(d), .clk(clk), .clr_(clr_), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync3d_c_ppp] != {} } { set_attr preserve 1 [find / -subdesign sync3d_c_ppp] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync3d_s_ppp.v b/designs/src/NVDLA/vmod/vlibs/sync3d_s_ppp.v new file mode 100644 index 0000000..6b8eeaf --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync3d_s_ppp.v @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync3d_s_ppp.v +module sync3d_s_ppp ( d, clk, set_, q); +input d, clk, set_; +output q; + p_SSYNC3DO_S_PPP NV_GENERIC_CELL( .d(d), .clk(clk), .set_(set_), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync3d_s_ppp] != {} } { set_attr preserve 1 [find / -subdesign sync3d_s_ppp] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync3d_s_ppp.v.vcp b/designs/src/NVDLA/vmod/vlibs/sync3d_s_ppp.v.vcp new file mode 100644 index 0000000..6b8eeaf --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync3d_s_ppp.v.vcp @@ -0,0 +1,16 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync3d_s_ppp.v +module sync3d_s_ppp ( d, clk, set_, q); +input d, clk, set_; +output q; + p_SSYNC3DO_S_PPP NV_GENERIC_CELL( .d(d), .clk(clk), .set_(set_), .q(q) ); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync3d_s_ppp] != {} } { set_attr preserve 1 [find / -subdesign sync3d_s_ppp] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync_reset.v b/designs/src/NVDLA/vmod/vlibs/sync_reset.v new file mode 100644 index 0000000..4bdf553 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync_reset.v @@ -0,0 +1,25 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync_reset.v +module sync_reset ( clk , inreset_ , direct_reset_ , test_mode , outreset_); +input clk; +input inreset_, direct_reset_, test_mode; +output outreset_; + wire reset_, inreset_tm_; +wire inreset_xclamp_, dft_xclamp_ctrl_cdc_sync_reset; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_cdc_sync_reset(.Y(dft_xclamp_ctrl_cdc_sync_reset)); +OR2D1 UJ_inreset_x_clamp (.A1(inreset_), + .A2(dft_xclamp_ctrl_cdc_sync_reset), + .Z (inreset_xclamp_)); + MUX2D4 UI_test_mode_inmux (.S(test_mode),.I1(direct_reset_),.I0(inreset_),.Z(inreset_tm_)); + p_SSYNC2DO_C_PP NV_GENERIC_CELL (.clk(clk), .clr_(inreset_tm_), .d(inreset_xclamp_), .q(reset_)); + MUX2D4 UI_test_mode_outmux (.S(test_mode),.I1(direct_reset_),.I0(reset_),.Z(outreset_)); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync_reset] != {} } { set_attr preserve 1 [find / -subdesign sync_reset] } +endmodule diff --git a/designs/src/NVDLA/vmod/vlibs/sync_reset.v.vcp b/designs/src/NVDLA/vmod/vlibs/sync_reset.v.vcp new file mode 100644 index 0000000..4bdf553 --- /dev/null +++ b/designs/src/NVDLA/vmod/vlibs/sync_reset.v.vcp @@ -0,0 +1,25 @@ +// ================================================================ +// NVDLA Open Source Project +// +// Copyright(c) 2016 - 2017 NVIDIA Corporation. Licensed under the +// NVDLA Open Hardware License; Check "LICENSE" which comes with +// this distribution for more information. +// ================================================================ +// File Name: sync_reset.v +module sync_reset ( clk , inreset_ , direct_reset_ , test_mode , outreset_); +input clk; +input inreset_, direct_reset_, test_mode; +output outreset_; + wire reset_, inreset_tm_; +wire inreset_xclamp_, dft_xclamp_ctrl_cdc_sync_reset; +NV_BLKBOX_SRC0 UJ_dft_xclamp_ctrl_cdc_sync_reset(.Y(dft_xclamp_ctrl_cdc_sync_reset)); +OR2D1 UJ_inreset_x_clamp (.A1(inreset_), + .A2(dft_xclamp_ctrl_cdc_sync_reset), + .Z (inreset_xclamp_)); + MUX2D4 UI_test_mode_inmux (.S(test_mode),.I1(direct_reset_),.I0(inreset_),.Z(inreset_tm_)); + p_SSYNC2DO_C_PP NV_GENERIC_CELL (.clk(clk), .clr_(inreset_tm_), .d(inreset_xclamp_), .q(reset_)); + MUX2D4 UI_test_mode_outmux (.S(test_mode),.I1(direct_reset_),.I0(reset_),.Z(outreset_)); +// synopsys dc_script_begin +// synopsys dc_script_end +//g2c if {[find / -null_ok -subdesign sync_reset] != {} } { set_attr preserve 1 [find / -subdesign sync_reset] } +endmodule diff --git a/designs/src/NyuziProcessor/NyuziProcessor.v b/designs/src/NyuziProcessor/NyuziProcessor.v deleted file mode 100644 index 54684fc..0000000 --- a/designs/src/NyuziProcessor/NyuziProcessor.v +++ /dev/null @@ -1,7723 +0,0 @@ -module cache_lru ( - clk, - reset, - fill_en, - fill_set, - fill_way, - access_en, - access_set, - update_en, - update_way -); - reg _sv2v_0; - parameter NUM_SETS = 1; - parameter NUM_WAYS = 4; - parameter SET_INDEX_WIDTH = $clog2(NUM_SETS); - parameter WAY_INDEX_WIDTH = $clog2(NUM_WAYS); - input clk; - input reset; - input fill_en; - input [SET_INDEX_WIDTH - 1:0] fill_set; - output reg [WAY_INDEX_WIDTH - 1:0] fill_way; - input access_en; - input [SET_INDEX_WIDTH - 1:0] access_set; - input update_en; - input [WAY_INDEX_WIDTH - 1:0] update_way; - localparam LRU_FLAG_BITS = (NUM_WAYS == 1 ? 1 : (NUM_WAYS == 2 ? 1 : (NUM_WAYS == 4 ? 3 : 7))); - wire [LRU_FLAG_BITS - 1:0] lru_flags; - wire update_lru_en; - reg [SET_INDEX_WIDTH - 1:0] update_set; - reg [LRU_FLAG_BITS - 1:0] update_flags; - wire [SET_INDEX_WIDTH - 1:0] read_set; - wire read_en; - reg was_fill; - wire [WAY_INDEX_WIDTH - 1:0] new_mru; - assign read_en = access_en || fill_en; - assign read_set = (fill_en ? fill_set : access_set); - assign new_mru = (was_fill ? fill_way : update_way); - assign update_lru_en = was_fill || update_en; - reg [LRU_FLAG_BITS - 1:0] pass_thru_dat; - reg [LRU_FLAG_BITS - 1:0] mem; - reg pass_through_en; - always @(posedge clk) begin - pass_through_en <= (update_lru_en && read_en) && (read_set == update_set); - pass_thru_dat <= update_flags; - if (update_lru_en) - mem <= update_flags; - end - assign lru_flags = (pass_through_en ? pass_thru_dat : mem); - generate - case (NUM_WAYS) - 1: begin : genblk1 - wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4850; - assign sv2v_tmp_F4850 = 0; - always @(*) fill_way = sv2v_tmp_F4850; - wire [LRU_FLAG_BITS:1] sv2v_tmp_6C66A; - assign sv2v_tmp_6C66A = 0; - always @(*) update_flags = sv2v_tmp_6C66A; - end - 2: begin : genblk1 - wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4B2A; - assign sv2v_tmp_F4B2A = !lru_flags[0]; - always @(*) fill_way = sv2v_tmp_F4B2A; - wire [1:1] sv2v_tmp_0C2DF; - assign sv2v_tmp_0C2DF = !new_mru; - always @(*) update_flags[0] = sv2v_tmp_0C2DF; - end - 4: begin : genblk1 - always @(*) begin - if (_sv2v_0) - ; - casez (lru_flags) - 3'b00z: fill_way = 0; - 3'b10z: fill_way = 1; - 3'bz10: fill_way = 2; - 3'bz11: fill_way = 3; - default: fill_way = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - case (new_mru) - 2'd0: update_flags = {2'b11, lru_flags[0]}; - 2'd1: update_flags = {2'b01, lru_flags[0]}; - 2'd2: update_flags = {lru_flags[2], 2'b01}; - 2'd3: update_flags = {lru_flags[2], 2'b00}; - default: update_flags = 1'sb0; - endcase - end - end - 8: begin : genblk1 - always @(*) begin - if (_sv2v_0) - ; - casez (lru_flags) - 7'b00z0zzz: fill_way = 0; - 7'b10z0zzz: fill_way = 1; - 7'bz100zzz: fill_way = 2; - 7'bz110zzz: fill_way = 3; - 7'bzzz100z: fill_way = 4; - 7'bzzz110z: fill_way = 5; - 7'bzzz1z10: fill_way = 6; - 7'bzzz1z11: fill_way = 7; - default: fill_way = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - case (new_mru) - 3'd0: update_flags = {2'b11, lru_flags[5], 1'b1, lru_flags[2:0]}; - 3'd1: update_flags = {2'b01, lru_flags[5], 1'b1, lru_flags[2:0]}; - 3'd2: update_flags = {lru_flags[6], 3'b011, lru_flags[2:0]}; - 3'd3: update_flags = {lru_flags[6], 3'b001, lru_flags[2:0]}; - 3'd4: update_flags = {lru_flags[6:4], 3'b011, lru_flags[0]}; - 3'd5: update_flags = {lru_flags[6:4], 3'b001, lru_flags[0]}; - 3'd6: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b01}; - 3'd7: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b00}; - default: update_flags = 1'sb0; - endcase - end - end - default: begin : genblk1 - initial begin - $display("%m invalid number of ways"); - $finish; - end - end - endcase - endgenerate - always @(posedge clk) begin - update_set <= read_set; - was_fill <= fill_en; - end - initial _sv2v_0 = 0; -endmodule -module cam ( - clk, - reset, - lookup_key, - lookup_idx, - lookup_hit, - update_en, - update_key, - update_idx, - update_valid -); - parameter NUM_ENTRIES = 2; - parameter KEY_WIDTH = 32; - parameter INDEX_WIDTH = $clog2(NUM_ENTRIES); - input clk; - input reset; - input [KEY_WIDTH - 1:0] lookup_key; - output wire [INDEX_WIDTH - 1:0] lookup_idx; - output wire lookup_hit; - input update_en; - input [KEY_WIDTH - 1:0] update_key; - input [INDEX_WIDTH - 1:0] update_idx; - input update_valid; - reg [KEY_WIDTH - 1:0] lookup_table [0:NUM_ENTRIES - 1]; - reg [NUM_ENTRIES - 1:0] entry_valid; - wire [NUM_ENTRIES - 1:0] hit_oh; - genvar _gv_test_index_1; - generate - for (_gv_test_index_1 = 0; _gv_test_index_1 < NUM_ENTRIES; _gv_test_index_1 = _gv_test_index_1 + 1) begin : lookup_gen - localparam test_index = _gv_test_index_1; - assign hit_oh[test_index] = entry_valid[test_index] && (lookup_table[test_index] == lookup_key); - end - endgenerate - assign lookup_hit = |hit_oh; - oh_to_idx #(.NUM_SIGNALS(NUM_ENTRIES)) oh_to_idx_hit( - .one_hot(hit_oh), - .index(lookup_idx) - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < NUM_ENTRIES; i = i + 1) - entry_valid[i] <= 1'b0; - end - else if (update_en) - entry_valid[update_idx] <= update_valid; - always @(posedge clk) - if (update_en) - lookup_table[update_idx] <= update_key; -endmodule -module control_registers ( - clk, - reset, - interrupt_req, - cr_eret_address, - cr_mmu_en, - cr_supervisor_en, - cr_current_asid, - cr_suspend_thread, - cr_resume_thread, - cr_interrupt_pending, - cr_interrupt_en, - dt_thread_idx, - dd_creg_write_en, - dd_creg_read_en, - dd_creg_index, - dd_creg_write_val, - wb_trap, - wb_eret, - wb_trap_cause, - wb_trap_pc, - wb_trap_access_vaddr, - wb_rollback_thread_idx, - wb_trap_subcycle, - wb_syscall_index, - cr_creg_read_val, - cr_eret_subcycle, - cr_trap_handler, - cr_tlb_miss_handler, - cr_perf_event_select0, - cr_perf_event_select1, - perf_event_count0, - perf_event_count1, - ocd_data_from_host, - ocd_data_update, - cr_data_to_host -); - parameter CORE_ID = 0; - parameter NUM_INTERRUPTS = 16; - parameter NUM_PERF_EVENTS = 8; - parameter EVENT_IDX_WIDTH = $clog2(NUM_PERF_EVENTS); - input clk; - input reset; - input [NUM_INTERRUPTS - 1:0] interrupt_req; - output wire [127:0] cr_eret_address; - output wire [0:3] cr_mmu_en; - output wire [0:3] cr_supervisor_en; - localparam defines_ASID_WIDTH = 8; - output reg [31:0] cr_current_asid; - localparam defines_TOTAL_THREADS = 4; - output reg [3:0] cr_suspend_thread; - output reg [3:0] cr_resume_thread; - output wire [3:0] cr_interrupt_pending; - output wire [3:0] cr_interrupt_en; - input wire [1:0] dt_thread_idx; - input dd_creg_write_en; - input dd_creg_read_en; - input wire [4:0] dd_creg_index; - input wire [31:0] dd_creg_write_val; - input wb_trap; - input wb_eret; - input wire [5:0] wb_trap_cause; - input wire [31:0] wb_trap_pc; - input wire [31:0] wb_trap_access_vaddr; - input wire [1:0] wb_rollback_thread_idx; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [3:0] wb_trap_subcycle; - input wire [14:0] wb_syscall_index; - output reg [31:0] cr_creg_read_val; - output wire [15:0] cr_eret_subcycle; - output reg [31:0] cr_trap_handler; - output reg [31:0] cr_tlb_miss_handler; - output reg [EVENT_IDX_WIDTH - 1:0] cr_perf_event_select0; - output reg [EVENT_IDX_WIDTH - 1:0] cr_perf_event_select1; - input [63:0] perf_event_count0; - input [63:0] perf_event_count1; - input wire [31:0] ocd_data_from_host; - input ocd_data_update; - output wire [31:0] cr_data_to_host; - localparam TRAP_LEVELS = 3; - reg [155:0] trap_state [0:3][0:2]; - reg [31:0] page_dir_base [0:3]; - reg [31:0] cycle_count; - reg [NUM_INTERRUPTS - 1:0] interrupt_mask [0:3]; - wire [NUM_INTERRUPTS - 1:0] interrupt_pending [0:3]; - reg [NUM_INTERRUPTS - 1:0] interrupt_edge_latched [0:3]; - reg [NUM_INTERRUPTS - 1:0] int_trigger_type; - reg [NUM_INTERRUPTS - 1:0] interrupt_req_prev; - wire [NUM_INTERRUPTS - 1:0] interrupt_edge; - reg [31:0] jtag_data; - assign cr_data_to_host = jtag_data; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - function automatic [3:0] sv2v_cast_60D1B; - input reg [3:0] inp; - sv2v_cast_60D1B = inp; - endfunction - always @(posedge clk or posedge reset) - if (reset) begin - begin : sv2v_autoblock_1 - reg signed [31:0] thread_idx; - for (thread_idx = 0; thread_idx < 4; thread_idx = thread_idx + 1) - begin - trap_state[thread_idx][0] <= 1'sb0; - trap_state[thread_idx][0][155] <= 1'b1; - cr_current_asid[(3 - thread_idx) * 8+:8] <= 1'sb0; - page_dir_base[thread_idx] <= 1'sb0; - interrupt_mask[thread_idx] <= 1'sb0; - end - end - jtag_data <= 1'sb0; - cr_tlb_miss_handler <= 1'sb0; - cr_trap_handler <= 1'sb0; - cycle_count <= 1'sb0; - int_trigger_type <= 1'sb0; - cr_suspend_thread <= 1'sb0; - cr_resume_thread <= 1'sb0; - cr_perf_event_select0 <= 1'sb0; - cr_perf_event_select1 <= 1'sb0; - end - else begin - cycle_count <= cycle_count + 1; - if (wb_trap) begin - begin : sv2v_autoblock_2 - reg signed [31:0] level; - for (level = 0; level < 2; level = level + 1) - trap_state[wb_rollback_thread_idx][level + 1] <= trap_state[wb_rollback_thread_idx][level]; - end - trap_state[wb_rollback_thread_idx][0][88-:6] <= wb_trap_cause; - trap_state[wb_rollback_thread_idx][0][82-:32] <= wb_trap_pc; - trap_state[wb_rollback_thread_idx][0][50-:32] <= wb_trap_access_vaddr; - trap_state[wb_rollback_thread_idx][0][14-:15] <= wb_syscall_index; - trap_state[wb_rollback_thread_idx][0][18-:4] <= wb_trap_subcycle; - trap_state[wb_rollback_thread_idx][0][153] <= 0; - trap_state[wb_rollback_thread_idx][0][155] <= 1; - if (wb_trap_cause[3-:4] == 4'd7) - trap_state[wb_rollback_thread_idx][0][154] <= 0; - end - if (wb_eret) begin : sv2v_autoblock_3 - reg signed [31:0] level; - for (level = 0; level < 2; level = level + 1) - trap_state[wb_rollback_thread_idx][level] <= trap_state[wb_rollback_thread_idx][level + 1]; - end - cr_suspend_thread <= 1'sb0; - cr_resume_thread <= 1'sb0; - if (dd_creg_write_en) - (* full_case, parallel_case *) - case (dd_creg_index) - 5'd4: trap_state[dt_thread_idx][0][155-:3] <= sv2v_cast_3(dd_creg_write_val); - 5'd8: trap_state[dt_thread_idx][1][155-:3] <= sv2v_cast_3(dd_creg_write_val); - 5'd2: trap_state[dt_thread_idx][0][82-:32] <= dd_creg_write_val; - 5'd1: cr_trap_handler <= dd_creg_write_val; - 5'd7: cr_tlb_miss_handler <= dd_creg_write_val; - 5'd11: trap_state[dt_thread_idx][0][152-:32] <= dd_creg_write_val; - 5'd12: trap_state[dt_thread_idx][0][120-:32] <= dd_creg_write_val; - 5'd13: trap_state[dt_thread_idx][0][18-:4] <= sv2v_cast_60D1B(dd_creg_write_val); - 5'd9: cr_current_asid[(3 - dt_thread_idx) * 8+:8] <= dd_creg_write_val[7:0]; - 5'd10: page_dir_base[dt_thread_idx] <= dd_creg_write_val; - 5'd14: interrupt_mask[dt_thread_idx] <= dd_creg_write_val[NUM_INTERRUPTS - 1:0]; - 5'd17: int_trigger_type <= dd_creg_write_val[NUM_INTERRUPTS - 1:0]; - 5'd18: jtag_data <= dd_creg_write_val; - 5'd20: cr_suspend_thread <= dd_creg_write_val[3:0]; - 5'd21: cr_resume_thread <= dd_creg_write_val[3:0]; - 5'd22: cr_perf_event_select0 <= dd_creg_write_val[EVENT_IDX_WIDTH - 1:0]; - 5'd23: cr_perf_event_select1 <= dd_creg_write_val[EVENT_IDX_WIDTH - 1:0]; - default: - ; - endcase - else if (ocd_data_update) - jtag_data <= ocd_data_from_host; - end - always @(posedge clk or posedge reset) - if (reset) - interrupt_req_prev <= 1'sb0; - else - interrupt_req_prev <= interrupt_req; - assign interrupt_edge = interrupt_req & ~interrupt_req_prev; - genvar _gv_thread_idx_1; - generate - for (_gv_thread_idx_1 = 0; _gv_thread_idx_1 < 4; _gv_thread_idx_1 = _gv_thread_idx_1 + 1) begin : interrupt_gen - localparam thread_idx = _gv_thread_idx_1; - wire [NUM_INTERRUPTS - 1:0] interrupt_ack; - wire do_interrupt_ack; - assign do_interrupt_ack = ((dt_thread_idx == thread_idx) && dd_creg_write_en) && (dd_creg_index == 5'd15); - assign interrupt_ack = {NUM_INTERRUPTS {do_interrupt_ack}} & dd_creg_write_val[NUM_INTERRUPTS - 1:0]; - assign cr_interrupt_en[thread_idx] = trap_state[thread_idx][0][153]; - assign cr_supervisor_en[thread_idx] = trap_state[thread_idx][0][155]; - assign cr_mmu_en[thread_idx] = trap_state[thread_idx][0][154]; - assign cr_eret_subcycle[(3 - thread_idx) * 4+:4] = trap_state[thread_idx][0][18-:4]; - assign cr_eret_address[(3 - thread_idx) * 32+:32] = trap_state[thread_idx][0][82-:32]; - always @(posedge clk or posedge reset) - if (reset) - interrupt_edge_latched[thread_idx] <= 1'sb0; - else - interrupt_edge_latched[thread_idx] <= (interrupt_edge_latched[thread_idx] & ~interrupt_ack) | interrupt_edge; - assign interrupt_pending[thread_idx] = (int_trigger_type & interrupt_req) | (~int_trigger_type & interrupt_edge_latched[thread_idx]); - assign cr_interrupt_pending[thread_idx] = |(interrupt_pending[thread_idx] & interrupt_mask[thread_idx]); - end - endgenerate - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(posedge clk) - if (dd_creg_read_en) - (* full_case, parallel_case *) - case (dd_creg_index) - 5'd4: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][155-:3]); - 5'd8: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][1][155-:3]); - 5'd0: cr_creg_read_val <= sv2v_cast_32({CORE_ID, dt_thread_idx}); - 5'd2: cr_creg_read_val <= trap_state[dt_thread_idx][0][82-:32]; - 5'd3: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][88-:6]); - 5'd1: cr_creg_read_val <= cr_trap_handler; - 5'd5: cr_creg_read_val <= trap_state[dt_thread_idx][0][50-:32]; - 5'd7: cr_creg_read_val <= cr_tlb_miss_handler; - 5'd6: cr_creg_read_val <= cycle_count; - 5'd11: cr_creg_read_val <= trap_state[dt_thread_idx][0][152-:32]; - 5'd12: cr_creg_read_val <= trap_state[dt_thread_idx][0][120-:32]; - 5'd13: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][18-:4]); - 5'd9: cr_creg_read_val <= sv2v_cast_32(cr_current_asid[(3 - dt_thread_idx) * 8+:8]); - 5'd10: cr_creg_read_val <= page_dir_base[dt_thread_idx]; - 5'd16: cr_creg_read_val <= sv2v_cast_32(interrupt_pending[dt_thread_idx] & interrupt_mask[dt_thread_idx]); - 5'd14: cr_creg_read_val <= sv2v_cast_32(interrupt_mask[dt_thread_idx]); - 5'd17: cr_creg_read_val <= sv2v_cast_32(int_trigger_type); - 5'd18: cr_creg_read_val <= jtag_data; - 5'd19: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][14-:15]); - 5'd24: cr_creg_read_val <= perf_event_count0[31:0]; - 5'd25: cr_creg_read_val <= perf_event_count0[63:32]; - 5'd26: cr_creg_read_val <= perf_event_count1[31:0]; - 5'd27: cr_creg_read_val <= perf_event_count1[63:32]; - default: cr_creg_read_val <= 32'hffffffff; - endcase -endmodule -module core ( - clk, - reset, - thread_en, - interrupt_req, - l2_ready, - l2_response_valid, - l2_response, - l2i_request_valid, - l2i_request, - ii_ready, - ii_response_valid, - ii_response, - ior_request_valid, - ior_request, - ocd_halt, - ocd_thread, - ocd_core, - ocd_inject_inst, - ocd_inject_en, - injected_complete, - injected_rollback, - ocd_data_from_host, - ocd_data_update, - cr_data_to_host, - cr_suspend_thread, - cr_resume_thread -); - parameter CORE_ID = 1'sb0; - parameter RESET_PC = 1'sb0; - parameter NUM_INTERRUPTS = 16; - input clk; - input reset; - input wire [3:0] thread_en; - input [NUM_INTERRUPTS - 1:0] interrupt_req; - input l2_ready; - input l2_response_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [548:0] l2_response; - output wire l2i_request_valid; - output wire [611:0] l2i_request; - input ii_ready; - input ii_response_valid; - input wire [37:0] ii_response; - output wire ior_request_valid; - output wire [66:0] ior_request; - input ocd_halt; - input wire [1:0] ocd_thread; - input wire [3:0] ocd_core; - input wire [31:0] ocd_inject_inst; - input ocd_inject_en; - output reg injected_complete; - output reg injected_rollback; - input wire [31:0] ocd_data_from_host; - input ocd_data_update; - output wire [31:0] cr_data_to_host; - localparam defines_TOTAL_THREADS = 4; - output wire [3:0] cr_suspend_thread; - output wire [3:0] cr_resume_thread; - localparam defines_CORE_PERF_EVENTS = 14; - localparam EVENT_IDX_WIDTH = 4; - localparam NUM_PERF_COUNTERS = 2; - wire core_selected_debug; - wire [13:0] perf_events; - wire [7:0] perf_event_select; - wire [31:0] cr_creg_read_val; - localparam defines_ASID_WIDTH = 8; - wire [31:0] cr_current_asid; - wire [127:0] cr_eret_address; - wire [15:0] cr_eret_subcycle; - wire [3:0] cr_interrupt_en; - wire [3:0] cr_interrupt_pending; - wire [0:3] cr_mmu_en; - wire [0:3] cr_supervisor_en; - wire [31:0] cr_tlb_miss_handler; - wire [31:0] cr_trap_handler; - wire dd_cache_miss; - wire [25:0] dd_cache_miss_addr; - wire dd_cache_miss_sync; - wire [1:0] dd_cache_miss_thread_idx; - wire [4:0] dd_creg_index; - wire dd_creg_read_en; - wire dd_creg_write_en; - wire [31:0] dd_creg_write_val; - wire dd_dinvalidate_en; - wire dd_flush_en; - wire dd_iinvalidate_en; - wire [141:0] dd_instruction; - wire dd_instruction_valid; - wire dd_io_access; - wire [31:0] dd_io_addr; - wire dd_io_read_en; - wire [1:0] dd_io_thread_idx; - wire dd_io_write_en; - wire [31:0] dd_io_write_value; - wire [15:0] dd_lane_mask; - wire [511:0] dd_load_data; - wire [3:0] dd_load_sync_pending; - wire dd_membar_en; - wire dd_perf_dcache_hit; - wire dd_perf_dcache_miss; - wire dd_perf_dtlb_miss; - localparam defines_DCACHE_TAG_BITS = 20; - wire [31:0] dd_request_vaddr; - wire dd_rollback_en; - wire [31:0] dd_rollback_pc; - wire [25:0] dd_store_addr; - wire [25:0] dd_store_bypass_addr; - wire [1:0] dd_store_bypass_thread_idx; - wire [511:0] dd_store_data; - wire dd_store_en; - wire [63:0] dd_store_mask; - wire dd_store_sync; - wire [1:0] dd_store_thread_idx; - wire [3:0] dd_subcycle; - wire dd_suspend_thread; - wire [1:0] dd_thread_idx; - wire dd_trap; - wire [5:0] dd_trap_cause; - wire dd_update_lru_en; - wire [1:0] dd_update_lru_way; - wire [1:0] dt_fill_lru; - wire [141:0] dt_instruction; - wire dt_instruction_valid; - wire dt_invalidate_tlb_all_en; - wire dt_invalidate_tlb_en; - wire [15:0] dt_mask_value; - wire [31:0] dt_request_paddr; - wire [31:0] dt_request_vaddr; - wire [79:0] dt_snoop_tag; - wire [0:3] dt_snoop_valid; - wire [511:0] dt_store_value; - wire [3:0] dt_subcycle; - wire [79:0] dt_tag; - wire [1:0] dt_thread_idx; - wire dt_tlb_hit; - wire dt_tlb_present; - wire dt_tlb_supervisor; - wire dt_tlb_writable; - wire [7:0] dt_update_itlb_asid; - wire dt_update_itlb_en; - wire dt_update_itlb_executable; - wire dt_update_itlb_global; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_ppage_idx; - wire dt_update_itlb_present; - wire dt_update_itlb_supervisor; - wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_vpage_idx; - wire [0:3] dt_valid; - wire [127:0] fx1_add_exponent; - wire [15:0] fx1_add_result_sign; - wire [15:0] fx1_equal; - wire [95:0] fx1_ftoi_lshift; - wire [141:0] fx1_instruction; - wire fx1_instruction_valid; - wire [15:0] fx1_logical_subtract; - wire [15:0] fx1_mask_value; - wire [127:0] fx1_mul_exponent; - wire [15:0] fx1_mul_sign; - wire [15:0] fx1_mul_underflow; - wire [511:0] fx1_multiplicand; - wire [511:0] fx1_multiplier; - wire [15:0] fx1_result_inf; - wire [15:0] fx1_result_nan; - wire [95:0] fx1_se_align_shift; - wire [511:0] fx1_significand_le; - wire [511:0] fx1_significand_se; - wire [3:0] fx1_subcycle; - wire [1:0] fx1_thread_idx; - wire [127:0] fx2_add_exponent; - wire [15:0] fx2_add_result_sign; - wire [15:0] fx2_equal; - wire [95:0] fx2_ftoi_lshift; - wire [15:0] fx2_guard; - wire [141:0] fx2_instruction; - wire fx2_instruction_valid; - wire [15:0] fx2_logical_subtract; - wire [15:0] fx2_mask_value; - wire [127:0] fx2_mul_exponent; - wire [15:0] fx2_mul_sign; - wire [15:0] fx2_mul_underflow; - wire [15:0] fx2_result_inf; - wire [15:0] fx2_result_nan; - wire [15:0] fx2_round; - wire [511:0] fx2_significand_le; - wire [1023:0] fx2_significand_product; - wire [511:0] fx2_significand_se; - wire [15:0] fx2_sticky; - wire [3:0] fx2_subcycle; - wire [1:0] fx2_thread_idx; - wire [127:0] fx3_add_exponent; - wire [15:0] fx3_add_result_sign; - wire [511:0] fx3_add_significand; - wire [15:0] fx3_equal; - wire [95:0] fx3_ftoi_lshift; - wire [141:0] fx3_instruction; - wire fx3_instruction_valid; - wire [15:0] fx3_logical_subtract; - wire [15:0] fx3_mask_value; - wire [127:0] fx3_mul_exponent; - wire [15:0] fx3_mul_sign; - wire [15:0] fx3_mul_underflow; - wire [15:0] fx3_result_inf; - wire [15:0] fx3_result_nan; - wire [1023:0] fx3_significand_product; - wire [3:0] fx3_subcycle; - wire [1:0] fx3_thread_idx; - wire [127:0] fx4_add_exponent; - wire [15:0] fx4_add_result_sign; - wire [511:0] fx4_add_significand; - wire [15:0] fx4_equal; - wire [141:0] fx4_instruction; - wire fx4_instruction_valid; - wire [15:0] fx4_logical_subtract; - wire [15:0] fx4_mask_value; - wire [127:0] fx4_mul_exponent; - wire [15:0] fx4_mul_sign; - wire [15:0] fx4_mul_underflow; - wire [95:0] fx4_norm_shift; - wire [15:0] fx4_result_inf; - wire [15:0] fx4_result_nan; - wire [1023:0] fx4_significand_product; - wire [3:0] fx4_subcycle; - wire [1:0] fx4_thread_idx; - wire [141:0] fx5_instruction; - wire fx5_instruction_valid; - wire [15:0] fx5_mask_value; - wire [511:0] fx5_result; - wire [3:0] fx5_subcycle; - wire [1:0] fx5_thread_idx; - wire [141:0] id_instruction; - wire id_instruction_valid; - wire [1:0] id_thread_idx; - wire ifd_alignment_fault; - wire ifd_cache_miss; - wire [25:0] ifd_cache_miss_paddr; - wire [1:0] ifd_cache_miss_thread_idx; - wire ifd_executable_fault; - wire ifd_inst_injected; - wire [31:0] ifd_instruction; - wire ifd_instruction_valid; - wire ifd_near_miss; - wire ifd_page_fault; - wire [31:0] ifd_pc; - wire ifd_perf_icache_hit; - wire ifd_perf_icache_miss; - wire ifd_perf_itlb_miss; - wire ifd_supervisor_fault; - wire [1:0] ifd_thread_idx; - wire ifd_tlb_miss; - wire ifd_update_lru_en; - wire [1:0] ifd_update_lru_way; - wire [1:0] ift_fill_lru; - wire ift_instruction_requested; - localparam defines_ICACHE_TAG_BITS = 20; - wire [31:0] ift_pc_paddr; - wire [31:0] ift_pc_vaddr; - wire [79:0] ift_tag; - wire [1:0] ift_thread_idx; - wire ift_tlb_executable; - wire ift_tlb_hit; - wire ift_tlb_present; - wire ift_tlb_supervisor; - wire [0:3] ift_valid; - wire [3:0] ior_pending; - wire [31:0] ior_read_value; - wire ior_rollback_en; - wire [3:0] ior_wake_bitmap; - wire [141:0] ix_instruction; - wire ix_instruction_valid; - wire [15:0] ix_mask_value; - wire ix_perf_cond_branch_not_taken; - wire ix_perf_cond_branch_taken; - wire ix_perf_uncond_branch; - wire ix_privileged_op_fault; - wire [511:0] ix_result; - wire ix_rollback_en; - wire [31:0] ix_rollback_pc; - wire [3:0] ix_subcycle; - wire [1:0] ix_thread_idx; - wire l2i_dcache_lru_fill_en; - wire [5:0] l2i_dcache_lru_fill_set; - wire [3:0] l2i_dcache_wake_bitmap; - wire [511:0] l2i_ddata_update_data; - wire l2i_ddata_update_en; - wire [5:0] l2i_ddata_update_set; - wire [1:0] l2i_ddata_update_way; - wire [3:0] l2i_dtag_update_en_oh; - wire [5:0] l2i_dtag_update_set; - wire [19:0] l2i_dtag_update_tag; - wire l2i_dtag_update_valid; - wire l2i_icache_lru_fill_en; - wire [5:0] l2i_icache_lru_fill_set; - wire [3:0] l2i_icache_wake_bitmap; - wire [511:0] l2i_idata_update_data; - wire l2i_idata_update_en; - wire [5:0] l2i_idata_update_set; - wire [1:0] l2i_idata_update_way; - wire [3:0] l2i_itag_update_en; - wire [5:0] l2i_itag_update_set; - wire [19:0] l2i_itag_update_tag; - wire l2i_itag_update_valid; - wire l2i_perf_store; - wire l2i_snoop_en; - wire [5:0] l2i_snoop_set; - wire [141:0] of_instruction; - wire of_instruction_valid; - wire [15:0] of_mask_value; - wire [511:0] of_operand1; - wire [511:0] of_operand2; - wire [511:0] of_store_value; - wire [3:0] of_subcycle; - wire [1:0] of_thread_idx; - wire [127:0] perf_event_count; - wire sq_rollback_en; - wire [511:0] sq_store_bypass_data; - wire [63:0] sq_store_bypass_mask; - wire [3:0] sq_store_sync_pending; - wire sq_store_sync_success; - wire [3:0] ts_fetch_en; - wire [141:0] ts_instruction; - wire ts_instruction_valid; - wire ts_perf_instruction_issue; - wire [3:0] ts_subcycle; - wire [1:0] ts_thread_idx; - wire wb_eret; - wire wb_inst_injected; - wire wb_perf_instruction_retire; - wire wb_perf_interrupt; - wire wb_perf_store_rollback; - wire wb_rollback_en; - wire [31:0] wb_rollback_pc; - wire [1:0] wb_rollback_pipeline; - wire [3:0] wb_rollback_subcycle; - wire [1:0] wb_rollback_thread_idx; - wire [3:0] wb_suspend_thread_oh; - wire [14:0] wb_syscall_index; - wire wb_trap; - wire [31:0] wb_trap_access_vaddr; - wire [5:0] wb_trap_cause; - wire [31:0] wb_trap_pc; - wire [3:0] wb_trap_subcycle; - wire wb_writeback_en; - wire wb_writeback_last_subcycle; - wire [15:0] wb_writeback_mask; - wire [4:0] wb_writeback_reg; - wire [1:0] wb_writeback_thread_idx; - wire [511:0] wb_writeback_value; - wire wb_writeback_vector; - ifetch_tag_stage #(.RESET_PC(RESET_PC)) ifetch_tag_stage( - .clk(clk), - .reset(reset), - .ifd_update_lru_en(ifd_update_lru_en), - .ifd_update_lru_way(ifd_update_lru_way), - .ifd_cache_miss(ifd_cache_miss), - .ifd_near_miss(ifd_near_miss), - .ifd_cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .ift_instruction_requested(ift_instruction_requested), - .ift_pc_paddr(ift_pc_paddr), - .ift_pc_vaddr(ift_pc_vaddr), - .ift_thread_idx(ift_thread_idx), - .ift_tlb_hit(ift_tlb_hit), - .ift_tlb_present(ift_tlb_present), - .ift_tlb_executable(ift_tlb_executable), - .ift_tlb_supervisor(ift_tlb_supervisor), - .ift_tag(ift_tag), - .ift_valid(ift_valid), - .l2i_icache_lru_fill_en(l2i_icache_lru_fill_en), - .l2i_icache_lru_fill_set(l2i_icache_lru_fill_set), - .l2i_itag_update_en(l2i_itag_update_en), - .l2i_itag_update_set(l2i_itag_update_set), - .l2i_itag_update_tag(l2i_itag_update_tag), - .l2i_itag_update_valid(l2i_itag_update_valid), - .l2i_icache_wake_bitmap(l2i_icache_wake_bitmap), - .ift_fill_lru(ift_fill_lru), - .cr_mmu_en(cr_mmu_en), - .cr_current_asid(cr_current_asid), - .dt_invalidate_tlb_en(dt_invalidate_tlb_en), - .dt_invalidate_tlb_all_en(dt_invalidate_tlb_all_en), - .dt_update_itlb_asid(dt_update_itlb_asid), - .dt_update_itlb_vpage_idx(dt_update_itlb_vpage_idx), - .dt_update_itlb_en(dt_update_itlb_en), - .dt_update_itlb_supervisor(dt_update_itlb_supervisor), - .dt_update_itlb_global(dt_update_itlb_global), - .dt_update_itlb_present(dt_update_itlb_present), - .dt_update_itlb_executable(dt_update_itlb_executable), - .dt_update_itlb_ppage_idx(dt_update_itlb_ppage_idx), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pc(wb_rollback_pc), - .ts_fetch_en(ts_fetch_en), - .ocd_halt(ocd_halt), - .ocd_thread(ocd_thread) - ); - ifetch_data_stage ifetch_data_stage( - .clk(clk), - .reset(reset), - .ift_instruction_requested(ift_instruction_requested), - .ift_pc_paddr(ift_pc_paddr), - .ift_pc_vaddr(ift_pc_vaddr), - .ift_thread_idx(ift_thread_idx), - .ift_tlb_hit(ift_tlb_hit), - .ift_tlb_present(ift_tlb_present), - .ift_tlb_executable(ift_tlb_executable), - .ift_tlb_supervisor(ift_tlb_supervisor), - .ift_tag(ift_tag), - .ift_valid(ift_valid), - .ifd_update_lru_en(ifd_update_lru_en), - .ifd_update_lru_way(ifd_update_lru_way), - .ifd_near_miss(ifd_near_miss), - .l2i_idata_update_en(l2i_idata_update_en), - .l2i_idata_update_way(l2i_idata_update_way), - .l2i_idata_update_set(l2i_idata_update_set), - .l2i_idata_update_data(l2i_idata_update_data), - .l2i_itag_update_en(l2i_itag_update_en), - .l2i_itag_update_set(l2i_itag_update_set), - .l2i_itag_update_tag(l2i_itag_update_tag), - .ifd_cache_miss(ifd_cache_miss), - .ifd_cache_miss_paddr(ifd_cache_miss_paddr), - .ifd_cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .cr_supervisor_en(cr_supervisor_en), - .ifd_instruction(ifd_instruction), - .ifd_instruction_valid(ifd_instruction_valid), - .ifd_pc(ifd_pc), - .ifd_thread_idx(ifd_thread_idx), - .ifd_alignment_fault(ifd_alignment_fault), - .ifd_tlb_miss(ifd_tlb_miss), - .ifd_supervisor_fault(ifd_supervisor_fault), - .ifd_page_fault(ifd_page_fault), - .ifd_executable_fault(ifd_executable_fault), - .ifd_inst_injected(ifd_inst_injected), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .ifd_perf_icache_hit(ifd_perf_icache_hit), - .ifd_perf_icache_miss(ifd_perf_icache_miss), - .ifd_perf_itlb_miss(ifd_perf_itlb_miss), - .core_selected_debug(core_selected_debug), - .ocd_halt(ocd_halt), - .ocd_inject_inst(ocd_inject_inst), - .ocd_inject_en(ocd_inject_en), - .ocd_thread(ocd_thread) - ); - instruction_decode_stage instruction_decode_stage( - .clk(clk), - .reset(reset), - .ifd_instruction_valid(ifd_instruction_valid), - .ifd_instruction(ifd_instruction), - .ifd_inst_injected(ifd_inst_injected), - .ifd_pc(ifd_pc), - .ifd_thread_idx(ifd_thread_idx), - .ifd_alignment_fault(ifd_alignment_fault), - .ifd_supervisor_fault(ifd_supervisor_fault), - .ifd_page_fault(ifd_page_fault), - .ifd_executable_fault(ifd_executable_fault), - .ifd_tlb_miss(ifd_tlb_miss), - .dd_load_sync_pending(dd_load_sync_pending), - .sq_store_sync_pending(sq_store_sync_pending), - .id_instruction(id_instruction), - .id_instruction_valid(id_instruction_valid), - .id_thread_idx(id_thread_idx), - .ior_pending(ior_pending), - .cr_interrupt_en(cr_interrupt_en), - .cr_interrupt_pending(cr_interrupt_pending), - .ocd_halt(ocd_halt), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx) - ); - thread_select_stage thread_select_stage( - .clk(clk), - .reset(reset), - .id_instruction(id_instruction), - .id_instruction_valid(id_instruction_valid), - .id_thread_idx(id_thread_idx), - .ts_fetch_en(ts_fetch_en), - .ts_instruction_valid(ts_instruction_valid), - .ts_instruction(ts_instruction), - .ts_thread_idx(ts_thread_idx), - .ts_subcycle(ts_subcycle), - .wb_writeback_en(wb_writeback_en), - .wb_writeback_thread_idx(wb_writeback_thread_idx), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_reg(wb_writeback_reg), - .wb_writeback_last_subcycle(wb_writeback_last_subcycle), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_pipeline(wb_rollback_pipeline), - .wb_rollback_subcycle(wb_rollback_subcycle), - .thread_en(thread_en), - .wb_suspend_thread_oh(wb_suspend_thread_oh), - .l2i_dcache_wake_bitmap(l2i_dcache_wake_bitmap), - .ior_wake_bitmap(ior_wake_bitmap), - .ts_perf_instruction_issue(ts_perf_instruction_issue) - ); - operand_fetch_stage operand_fetch_stage( - .clk(clk), - .reset(reset), - .ts_instruction_valid(ts_instruction_valid), - .ts_instruction(ts_instruction), - .ts_thread_idx(ts_thread_idx), - .ts_subcycle(ts_subcycle), - .of_operand1(of_operand1), - .of_operand2(of_operand2), - .of_mask_value(of_mask_value), - .of_store_value(of_store_value), - .of_instruction(of_instruction), - .of_instruction_valid(of_instruction_valid), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_writeback_en(wb_writeback_en), - .wb_writeback_thread_idx(wb_writeback_thread_idx), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_value(wb_writeback_value), - .wb_writeback_mask(wb_writeback_mask), - .wb_writeback_reg(wb_writeback_reg) - ); - dcache_data_stage dcache_data_stage( - .clk(clk), - .reset(reset), - .dd_load_sync_pending(dd_load_sync_pending), - .dt_instruction_valid(dt_instruction_valid), - .dt_instruction(dt_instruction), - .dt_mask_value(dt_mask_value), - .dt_thread_idx(dt_thread_idx), - .dt_request_vaddr(dt_request_vaddr), - .dt_request_paddr(dt_request_paddr), - .dt_tlb_hit(dt_tlb_hit), - .dt_tlb_present(dt_tlb_present), - .dt_tlb_supervisor(dt_tlb_supervisor), - .dt_tlb_writable(dt_tlb_writable), - .dt_store_value(dt_store_value), - .dt_subcycle(dt_subcycle), - .dt_valid(dt_valid), - .dt_tag(dt_tag), - .dd_update_lru_en(dd_update_lru_en), - .dd_update_lru_way(dd_update_lru_way), - .dd_io_write_en(dd_io_write_en), - .dd_io_read_en(dd_io_read_en), - .dd_io_thread_idx(dd_io_thread_idx), - .dd_io_addr(dd_io_addr), - .dd_io_write_value(dd_io_write_value), - .dd_instruction_valid(dd_instruction_valid), - .dd_instruction(dd_instruction), - .dd_lane_mask(dd_lane_mask), - .dd_thread_idx(dd_thread_idx), - .dd_request_vaddr(dd_request_vaddr), - .dd_subcycle(dd_subcycle), - .dd_rollback_en(dd_rollback_en), - .dd_rollback_pc(dd_rollback_pc), - .dd_load_data(dd_load_data), - .dd_suspend_thread(dd_suspend_thread), - .dd_io_access(dd_io_access), - .dd_trap(dd_trap), - .dd_trap_cause(dd_trap_cause), - .cr_supervisor_en(cr_supervisor_en), - .dd_creg_write_en(dd_creg_write_en), - .dd_creg_read_en(dd_creg_read_en), - .dd_creg_index(dd_creg_index), - .dd_creg_write_val(dd_creg_write_val), - .l2i_ddata_update_en(l2i_ddata_update_en), - .l2i_ddata_update_way(l2i_ddata_update_way), - .l2i_ddata_update_set(l2i_ddata_update_set), - .l2i_ddata_update_data(l2i_ddata_update_data), - .l2i_dtag_update_en_oh(l2i_dtag_update_en_oh), - .l2i_dtag_update_set(l2i_dtag_update_set), - .l2i_dtag_update_tag(l2i_dtag_update_tag), - .dd_cache_miss(dd_cache_miss), - .dd_cache_miss_addr(dd_cache_miss_addr), - .dd_cache_miss_thread_idx(dd_cache_miss_thread_idx), - .dd_cache_miss_sync(dd_cache_miss_sync), - .dd_store_en(dd_store_en), - .dd_flush_en(dd_flush_en), - .dd_membar_en(dd_membar_en), - .dd_iinvalidate_en(dd_iinvalidate_en), - .dd_dinvalidate_en(dd_dinvalidate_en), - .dd_store_mask(dd_store_mask), - .dd_store_addr(dd_store_addr), - .dd_store_data(dd_store_data), - .dd_store_thread_idx(dd_store_thread_idx), - .dd_store_sync(dd_store_sync), - .dd_store_bypass_addr(dd_store_bypass_addr), - .dd_store_bypass_thread_idx(dd_store_bypass_thread_idx), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pipeline(wb_rollback_pipeline), - .dd_perf_dcache_hit(dd_perf_dcache_hit), - .dd_perf_dcache_miss(dd_perf_dcache_miss), - .dd_perf_dtlb_miss(dd_perf_dtlb_miss) - ); - dcache_tag_stage dcache_tag_stage( - .clk(clk), - .reset(reset), - .of_operand1(of_operand1), - .of_mask_value(of_mask_value), - .of_store_value(of_store_value), - .of_instruction_valid(of_instruction_valid), - .of_instruction(of_instruction), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .dd_update_lru_en(dd_update_lru_en), - .dd_update_lru_way(dd_update_lru_way), - .dt_instruction_valid(dt_instruction_valid), - .dt_instruction(dt_instruction), - .dt_mask_value(dt_mask_value), - .dt_thread_idx(dt_thread_idx), - .dt_request_vaddr(dt_request_vaddr), - .dt_request_paddr(dt_request_paddr), - .dt_tlb_hit(dt_tlb_hit), - .dt_tlb_writable(dt_tlb_writable), - .dt_store_value(dt_store_value), - .dt_subcycle(dt_subcycle), - .dt_valid(dt_valid), - .dt_tag(dt_tag), - .dt_tlb_supervisor(dt_tlb_supervisor), - .dt_tlb_present(dt_tlb_present), - .dt_invalidate_tlb_en(dt_invalidate_tlb_en), - .dt_invalidate_tlb_all_en(dt_invalidate_tlb_all_en), - .dt_update_itlb_en(dt_update_itlb_en), - .dt_update_itlb_asid(dt_update_itlb_asid), - .dt_update_itlb_vpage_idx(dt_update_itlb_vpage_idx), - .dt_update_itlb_ppage_idx(dt_update_itlb_ppage_idx), - .dt_update_itlb_present(dt_update_itlb_present), - .dt_update_itlb_supervisor(dt_update_itlb_supervisor), - .dt_update_itlb_global(dt_update_itlb_global), - .dt_update_itlb_executable(dt_update_itlb_executable), - .l2i_dcache_lru_fill_en(l2i_dcache_lru_fill_en), - .l2i_dcache_lru_fill_set(l2i_dcache_lru_fill_set), - .l2i_dtag_update_en_oh(l2i_dtag_update_en_oh), - .l2i_dtag_update_set(l2i_dtag_update_set), - .l2i_dtag_update_tag(l2i_dtag_update_tag), - .l2i_dtag_update_valid(l2i_dtag_update_valid), - .l2i_snoop_en(l2i_snoop_en), - .l2i_snoop_set(l2i_snoop_set), - .dt_snoop_valid(dt_snoop_valid), - .dt_snoop_tag(dt_snoop_tag), - .dt_fill_lru(dt_fill_lru), - .cr_mmu_en(cr_mmu_en), - .cr_supervisor_en(cr_supervisor_en), - .cr_current_asid(cr_current_asid), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx) - ); - int_execute_stage int_execute_stage( - .clk(clk), - .reset(reset), - .of_operand1(of_operand1), - .of_operand2(of_operand2), - .of_mask_value(of_mask_value), - .of_instruction_valid(of_instruction_valid), - .of_instruction(of_instruction), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .ix_instruction_valid(ix_instruction_valid), - .ix_instruction(ix_instruction), - .ix_result(ix_result), - .ix_mask_value(ix_mask_value), - .ix_thread_idx(ix_thread_idx), - .ix_rollback_en(ix_rollback_en), - .ix_rollback_pc(ix_rollback_pc), - .ix_subcycle(ix_subcycle), - .ix_privileged_op_fault(ix_privileged_op_fault), - .cr_eret_address(cr_eret_address), - .cr_supervisor_en(cr_supervisor_en), - .ix_perf_uncond_branch(ix_perf_uncond_branch), - .ix_perf_cond_branch_taken(ix_perf_cond_branch_taken), - .ix_perf_cond_branch_not_taken(ix_perf_cond_branch_not_taken) - ); - fp_execute_stage1 fp_execute_stage1( - .clk(clk), - .reset(reset), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .of_operand1(of_operand1), - .of_operand2(of_operand2), - .of_mask_value(of_mask_value), - .of_instruction_valid(of_instruction_valid), - .of_instruction(of_instruction), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .fx1_instruction_valid(fx1_instruction_valid), - .fx1_instruction(fx1_instruction), - .fx1_mask_value(fx1_mask_value), - .fx1_thread_idx(fx1_thread_idx), - .fx1_subcycle(fx1_subcycle), - .fx1_result_inf(fx1_result_inf), - .fx1_result_nan(fx1_result_nan), - .fx1_equal(fx1_equal), - .fx1_ftoi_lshift(fx1_ftoi_lshift), - .fx1_significand_le(fx1_significand_le), - .fx1_significand_se(fx1_significand_se), - .fx1_se_align_shift(fx1_se_align_shift), - .fx1_add_exponent(fx1_add_exponent), - .fx1_logical_subtract(fx1_logical_subtract), - .fx1_add_result_sign(fx1_add_result_sign), - .fx1_multiplicand(fx1_multiplicand), - .fx1_multiplier(fx1_multiplier), - .fx1_mul_exponent(fx1_mul_exponent), - .fx1_mul_underflow(fx1_mul_underflow), - .fx1_mul_sign(fx1_mul_sign) - ); - fp_execute_stage2 fp_execute_stage2( - .clk(clk), - .reset(reset), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pipeline(wb_rollback_pipeline), - .fx1_mask_value(fx1_mask_value), - .fx1_instruction_valid(fx1_instruction_valid), - .fx1_instruction(fx1_instruction), - .fx1_thread_idx(fx1_thread_idx), - .fx1_subcycle(fx1_subcycle), - .fx1_result_inf(fx1_result_inf), - .fx1_result_nan(fx1_result_nan), - .fx1_equal(fx1_equal), - .fx1_ftoi_lshift(fx1_ftoi_lshift), - .fx1_significand_le(fx1_significand_le), - .fx1_significand_se(fx1_significand_se), - .fx1_logical_subtract(fx1_logical_subtract), - .fx1_se_align_shift(fx1_se_align_shift), - .fx1_add_exponent(fx1_add_exponent), - .fx1_add_result_sign(fx1_add_result_sign), - .fx1_mul_exponent(fx1_mul_exponent), - .fx1_mul_sign(fx1_mul_sign), - .fx1_multiplicand(fx1_multiplicand), - .fx1_multiplier(fx1_multiplier), - .fx1_mul_underflow(fx1_mul_underflow), - .fx2_instruction_valid(fx2_instruction_valid), - .fx2_instruction(fx2_instruction), - .fx2_mask_value(fx2_mask_value), - .fx2_thread_idx(fx2_thread_idx), - .fx2_subcycle(fx2_subcycle), - .fx2_result_inf(fx2_result_inf), - .fx2_result_nan(fx2_result_nan), - .fx2_equal(fx2_equal), - .fx2_ftoi_lshift(fx2_ftoi_lshift), - .fx2_logical_subtract(fx2_logical_subtract), - .fx2_add_result_sign(fx2_add_result_sign), - .fx2_significand_le(fx2_significand_le), - .fx2_significand_se(fx2_significand_se), - .fx2_add_exponent(fx2_add_exponent), - .fx2_guard(fx2_guard), - .fx2_round(fx2_round), - .fx2_sticky(fx2_sticky), - .fx2_significand_product(fx2_significand_product), - .fx2_mul_exponent(fx2_mul_exponent), - .fx2_mul_underflow(fx2_mul_underflow), - .fx2_mul_sign(fx2_mul_sign) - ); - fp_execute_stage3 fp_execute_stage3( - .clk(clk), - .reset(reset), - .fx2_mask_value(fx2_mask_value), - .fx2_instruction_valid(fx2_instruction_valid), - .fx2_instruction(fx2_instruction), - .fx2_thread_idx(fx2_thread_idx), - .fx2_subcycle(fx2_subcycle), - .fx2_result_inf(fx2_result_inf), - .fx2_result_nan(fx2_result_nan), - .fx2_equal(fx2_equal), - .fx2_ftoi_lshift(fx2_ftoi_lshift), - .fx2_significand_le(fx2_significand_le), - .fx2_significand_se(fx2_significand_se), - .fx2_logical_subtract(fx2_logical_subtract), - .fx2_add_exponent(fx2_add_exponent), - .fx2_add_result_sign(fx2_add_result_sign), - .fx2_guard(fx2_guard), - .fx2_round(fx2_round), - .fx2_sticky(fx2_sticky), - .fx2_significand_product(fx2_significand_product), - .fx2_mul_exponent(fx2_mul_exponent), - .fx2_mul_underflow(fx2_mul_underflow), - .fx2_mul_sign(fx2_mul_sign), - .fx3_instruction_valid(fx3_instruction_valid), - .fx3_instruction(fx3_instruction), - .fx3_mask_value(fx3_mask_value), - .fx3_thread_idx(fx3_thread_idx), - .fx3_subcycle(fx3_subcycle), - .fx3_result_inf(fx3_result_inf), - .fx3_result_nan(fx3_result_nan), - .fx3_equal(fx3_equal), - .fx3_ftoi_lshift(fx3_ftoi_lshift), - .fx3_add_significand(fx3_add_significand), - .fx3_add_exponent(fx3_add_exponent), - .fx3_add_result_sign(fx3_add_result_sign), - .fx3_logical_subtract(fx3_logical_subtract), - .fx3_significand_product(fx3_significand_product), - .fx3_mul_exponent(fx3_mul_exponent), - .fx3_mul_underflow(fx3_mul_underflow), - .fx3_mul_sign(fx3_mul_sign) - ); - fp_execute_stage4 fp_execute_stage4( - .clk(clk), - .reset(reset), - .fx3_mask_value(fx3_mask_value), - .fx3_instruction_valid(fx3_instruction_valid), - .fx3_instruction(fx3_instruction), - .fx3_thread_idx(fx3_thread_idx), - .fx3_subcycle(fx3_subcycle), - .fx3_result_inf(fx3_result_inf), - .fx3_result_nan(fx3_result_nan), - .fx3_equal(fx3_equal), - .fx3_ftoi_lshift(fx3_ftoi_lshift), - .fx3_add_significand(fx3_add_significand), - .fx3_add_exponent(fx3_add_exponent), - .fx3_add_result_sign(fx3_add_result_sign), - .fx3_logical_subtract(fx3_logical_subtract), - .fx3_significand_product(fx3_significand_product), - .fx3_mul_exponent(fx3_mul_exponent), - .fx3_mul_underflow(fx3_mul_underflow), - .fx3_mul_sign(fx3_mul_sign), - .fx4_instruction_valid(fx4_instruction_valid), - .fx4_instruction(fx4_instruction), - .fx4_mask_value(fx4_mask_value), - .fx4_thread_idx(fx4_thread_idx), - .fx4_subcycle(fx4_subcycle), - .fx4_result_inf(fx4_result_inf), - .fx4_result_nan(fx4_result_nan), - .fx4_equal(fx4_equal), - .fx4_add_exponent(fx4_add_exponent), - .fx4_add_significand(fx4_add_significand), - .fx4_add_result_sign(fx4_add_result_sign), - .fx4_logical_subtract(fx4_logical_subtract), - .fx4_norm_shift(fx4_norm_shift), - .fx4_significand_product(fx4_significand_product), - .fx4_mul_exponent(fx4_mul_exponent), - .fx4_mul_underflow(fx4_mul_underflow), - .fx4_mul_sign(fx4_mul_sign) - ); - fp_execute_stage5 fp_execute_stage5( - .clk(clk), - .reset(reset), - .fx4_mask_value(fx4_mask_value), - .fx4_instruction_valid(fx4_instruction_valid), - .fx4_instruction(fx4_instruction), - .fx4_thread_idx(fx4_thread_idx), - .fx4_subcycle(fx4_subcycle), - .fx4_result_inf(fx4_result_inf), - .fx4_result_nan(fx4_result_nan), - .fx4_equal(fx4_equal), - .fx4_add_exponent(fx4_add_exponent), - .fx4_add_significand(fx4_add_significand), - .fx4_add_result_sign(fx4_add_result_sign), - .fx4_logical_subtract(fx4_logical_subtract), - .fx4_norm_shift(fx4_norm_shift), - .fx4_significand_product(fx4_significand_product), - .fx4_mul_exponent(fx4_mul_exponent), - .fx4_mul_underflow(fx4_mul_underflow), - .fx4_mul_sign(fx4_mul_sign), - .fx5_instruction_valid(fx5_instruction_valid), - .fx5_instruction(fx5_instruction), - .fx5_mask_value(fx5_mask_value), - .fx5_thread_idx(fx5_thread_idx), - .fx5_subcycle(fx5_subcycle), - .fx5_result(fx5_result) - ); - writeback_stage writeback_stage( - .clk(clk), - .reset(reset), - .fx5_instruction_valid(fx5_instruction_valid), - .fx5_instruction(fx5_instruction), - .fx5_result(fx5_result), - .fx5_mask_value(fx5_mask_value), - .fx5_thread_idx(fx5_thread_idx), - .fx5_subcycle(fx5_subcycle), - .ix_instruction_valid(ix_instruction_valid), - .ix_instruction(ix_instruction), - .ix_result(ix_result), - .ix_thread_idx(ix_thread_idx), - .ix_mask_value(ix_mask_value), - .ix_rollback_en(ix_rollback_en), - .ix_rollback_pc(ix_rollback_pc), - .ix_subcycle(ix_subcycle), - .ix_privileged_op_fault(ix_privileged_op_fault), - .dd_instruction_valid(dd_instruction_valid), - .dd_instruction(dd_instruction), - .dd_lane_mask(dd_lane_mask), - .dd_thread_idx(dd_thread_idx), - .dd_request_vaddr(dd_request_vaddr), - .dd_subcycle(dd_subcycle), - .dd_rollback_en(dd_rollback_en), - .dd_rollback_pc(dd_rollback_pc), - .dd_load_data(dd_load_data), - .dd_suspend_thread(dd_suspend_thread), - .dd_io_access(dd_io_access), - .dd_trap(dd_trap), - .dd_trap_cause(dd_trap_cause), - .sq_store_bypass_mask(sq_store_bypass_mask), - .sq_store_bypass_data(sq_store_bypass_data), - .sq_store_sync_success(sq_store_sync_success), - .sq_rollback_en(sq_rollback_en), - .ior_read_value(ior_read_value), - .ior_rollback_en(ior_rollback_en), - .cr_creg_read_val(cr_creg_read_val), - .cr_trap_handler(cr_trap_handler), - .cr_tlb_miss_handler(cr_tlb_miss_handler), - .cr_eret_subcycle(cr_eret_subcycle), - .wb_trap(wb_trap), - .wb_trap_cause(wb_trap_cause), - .wb_trap_pc(wb_trap_pc), - .wb_trap_access_vaddr(wb_trap_access_vaddr), - .wb_trap_subcycle(wb_trap_subcycle), - .wb_syscall_index(wb_syscall_index), - .wb_eret(wb_eret), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pc(wb_rollback_pc), - .wb_rollback_pipeline(wb_rollback_pipeline), - .wb_rollback_subcycle(wb_rollback_subcycle), - .wb_writeback_en(wb_writeback_en), - .wb_writeback_thread_idx(wb_writeback_thread_idx), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_value(wb_writeback_value), - .wb_writeback_mask(wb_writeback_mask), - .wb_writeback_reg(wb_writeback_reg), - .wb_writeback_last_subcycle(wb_writeback_last_subcycle), - .wb_suspend_thread_oh(wb_suspend_thread_oh), - .wb_inst_injected(wb_inst_injected), - .wb_perf_instruction_retire(wb_perf_instruction_retire), - .wb_perf_store_rollback(wb_perf_store_rollback), - .wb_perf_interrupt(wb_perf_interrupt) - ); - control_registers #( - .CORE_ID(CORE_ID), - .NUM_INTERRUPTS(NUM_INTERRUPTS), - .NUM_PERF_EVENTS(defines_CORE_PERF_EVENTS) - ) control_registers( - .cr_perf_event_select0(perf_event_select[0+:4]), - .cr_perf_event_select1(perf_event_select[4+:4]), - .perf_event_count0(perf_event_count[0+:64]), - .perf_event_count1(perf_event_count[64+:64]), - .clk(clk), - .reset(reset), - .interrupt_req(interrupt_req), - .cr_eret_address(cr_eret_address), - .cr_mmu_en(cr_mmu_en), - .cr_supervisor_en(cr_supervisor_en), - .cr_current_asid(cr_current_asid), - .cr_suspend_thread(cr_suspend_thread), - .cr_resume_thread(cr_resume_thread), - .cr_interrupt_pending(cr_interrupt_pending), - .cr_interrupt_en(cr_interrupt_en), - .dt_thread_idx(dt_thread_idx), - .dd_creg_write_en(dd_creg_write_en), - .dd_creg_read_en(dd_creg_read_en), - .dd_creg_index(dd_creg_index), - .dd_creg_write_val(dd_creg_write_val), - .wb_trap(wb_trap), - .wb_eret(wb_eret), - .wb_trap_cause(wb_trap_cause), - .wb_trap_pc(wb_trap_pc), - .wb_trap_access_vaddr(wb_trap_access_vaddr), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_trap_subcycle(wb_trap_subcycle), - .wb_syscall_index(wb_syscall_index), - .cr_creg_read_val(cr_creg_read_val), - .cr_eret_subcycle(cr_eret_subcycle), - .cr_trap_handler(cr_trap_handler), - .cr_tlb_miss_handler(cr_tlb_miss_handler), - .ocd_data_from_host(ocd_data_from_host), - .ocd_data_update(ocd_data_update), - .cr_data_to_host(cr_data_to_host) - ); - l1_l2_interface #(.CORE_ID(CORE_ID)) l1_l2_interface( - .clk(clk), - .reset(reset), - .l2_ready(l2_ready), - .l2_response_valid(l2_response_valid), - .l2_response(l2_response), - .l2i_request_valid(l2i_request_valid), - .l2i_request(l2i_request), - .l2i_icache_lru_fill_en(l2i_icache_lru_fill_en), - .l2i_icache_lru_fill_set(l2i_icache_lru_fill_set), - .l2i_itag_update_en(l2i_itag_update_en), - .l2i_itag_update_set(l2i_itag_update_set), - .l2i_itag_update_tag(l2i_itag_update_tag), - .l2i_itag_update_valid(l2i_itag_update_valid), - .sq_store_sync_pending(sq_store_sync_pending), - .ift_fill_lru(ift_fill_lru), - .ifd_cache_miss(ifd_cache_miss), - .ifd_cache_miss_paddr(ifd_cache_miss_paddr), - .ifd_cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .l2i_idata_update_en(l2i_idata_update_en), - .l2i_idata_update_way(l2i_idata_update_way), - .l2i_idata_update_set(l2i_idata_update_set), - .l2i_idata_update_data(l2i_idata_update_data), - .l2i_dcache_wake_bitmap(l2i_dcache_wake_bitmap), - .l2i_icache_wake_bitmap(l2i_icache_wake_bitmap), - .dt_snoop_valid(dt_snoop_valid), - .dt_snoop_tag(dt_snoop_tag), - .dt_fill_lru(dt_fill_lru), - .l2i_snoop_en(l2i_snoop_en), - .l2i_snoop_set(l2i_snoop_set), - .l2i_dtag_update_en_oh(l2i_dtag_update_en_oh), - .l2i_dtag_update_set(l2i_dtag_update_set), - .l2i_dtag_update_tag(l2i_dtag_update_tag), - .l2i_dtag_update_valid(l2i_dtag_update_valid), - .l2i_dcache_lru_fill_en(l2i_dcache_lru_fill_en), - .l2i_dcache_lru_fill_set(l2i_dcache_lru_fill_set), - .dd_cache_miss(dd_cache_miss), - .dd_cache_miss_addr(dd_cache_miss_addr), - .dd_cache_miss_thread_idx(dd_cache_miss_thread_idx), - .dd_cache_miss_sync(dd_cache_miss_sync), - .dd_store_en(dd_store_en), - .dd_flush_en(dd_flush_en), - .dd_membar_en(dd_membar_en), - .dd_iinvalidate_en(dd_iinvalidate_en), - .dd_dinvalidate_en(dd_dinvalidate_en), - .dd_store_mask(dd_store_mask), - .dd_store_addr(dd_store_addr), - .dd_store_data(dd_store_data), - .dd_store_thread_idx(dd_store_thread_idx), - .dd_store_sync(dd_store_sync), - .dd_store_bypass_addr(dd_store_bypass_addr), - .dd_store_bypass_thread_idx(dd_store_bypass_thread_idx), - .l2i_ddata_update_en(l2i_ddata_update_en), - .l2i_ddata_update_way(l2i_ddata_update_way), - .l2i_ddata_update_set(l2i_ddata_update_set), - .l2i_ddata_update_data(l2i_ddata_update_data), - .sq_store_bypass_mask(sq_store_bypass_mask), - .sq_store_sync_success(sq_store_sync_success), - .sq_store_bypass_data(sq_store_bypass_data), - .sq_rollback_en(sq_rollback_en), - .l2i_perf_store(l2i_perf_store) - ); - io_request_queue #(.CORE_ID(CORE_ID)) io_request_queue( - .clk(clk), - .reset(reset), - .dd_io_write_en(dd_io_write_en), - .dd_io_read_en(dd_io_read_en), - .dd_io_thread_idx(dd_io_thread_idx), - .dd_io_addr(dd_io_addr), - .dd_io_write_value(dd_io_write_value), - .ior_read_value(ior_read_value), - .ior_rollback_en(ior_rollback_en), - .ior_pending(ior_pending), - .ior_wake_bitmap(ior_wake_bitmap), - .ii_ready(ii_ready), - .ii_response_valid(ii_response_valid), - .ii_response(ii_response), - .ior_request_valid(ior_request_valid), - .ior_request(ior_request) - ); - assign core_selected_debug = CORE_ID == ocd_core; - always @(posedge clk) begin - injected_complete <= wb_inst_injected & !wb_rollback_en; - injected_rollback <= wb_inst_injected & wb_rollback_en; - end - assign perf_events = {ix_perf_cond_branch_not_taken, ix_perf_cond_branch_taken, ix_perf_uncond_branch, dd_perf_dtlb_miss, dd_perf_dcache_hit, dd_perf_dcache_miss, ifd_perf_itlb_miss, ifd_perf_icache_hit, ifd_perf_icache_miss, ts_perf_instruction_issue, wb_perf_instruction_retire, l2i_perf_store, wb_perf_store_rollback, wb_perf_interrupt}; - performance_counters #( - .NUM_EVENTS(defines_CORE_PERF_EVENTS), - .NUM_COUNTERS(2) - ) performance_counters( - .clk(clk), - .reset(reset), - .perf_events(perf_events), - .perf_event_select(perf_event_select), - .perf_event_count(perf_event_count) - ); -endmodule -module dcache_data_stage ( - clk, - reset, - dd_load_sync_pending, - dt_instruction_valid, - dt_instruction, - dt_mask_value, - dt_thread_idx, - dt_request_vaddr, - dt_request_paddr, - dt_tlb_hit, - dt_tlb_present, - dt_tlb_supervisor, - dt_tlb_writable, - dt_store_value, - dt_subcycle, - dt_valid, - dt_tag, - dd_update_lru_en, - dd_update_lru_way, - dd_io_write_en, - dd_io_read_en, - dd_io_thread_idx, - dd_io_addr, - dd_io_write_value, - dd_instruction_valid, - dd_instruction, - dd_lane_mask, - dd_thread_idx, - dd_request_vaddr, - dd_subcycle, - dd_rollback_en, - dd_rollback_pc, - dd_load_data, - dd_suspend_thread, - dd_io_access, - dd_trap, - dd_trap_cause, - cr_supervisor_en, - dd_creg_write_en, - dd_creg_read_en, - dd_creg_index, - dd_creg_write_val, - l2i_ddata_update_en, - l2i_ddata_update_way, - l2i_ddata_update_set, - l2i_ddata_update_data, - l2i_dtag_update_en_oh, - l2i_dtag_update_set, - l2i_dtag_update_tag, - dd_cache_miss, - dd_cache_miss_addr, - dd_cache_miss_thread_idx, - dd_cache_miss_sync, - dd_store_en, - dd_flush_en, - dd_membar_en, - dd_iinvalidate_en, - dd_dinvalidate_en, - dd_store_mask, - dd_store_addr, - dd_store_data, - dd_store_thread_idx, - dd_store_sync, - dd_store_bypass_addr, - dd_store_bypass_thread_idx, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pipeline, - dd_perf_dcache_hit, - dd_perf_dcache_miss, - dd_perf_dtlb_miss -); - reg _sv2v_0; - input clk; - input reset; - output reg [3:0] dd_load_sync_pending; - input dt_instruction_valid; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] dt_instruction; - input wire [15:0] dt_mask_value; - input wire [1:0] dt_thread_idx; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_DCACHE_TAG_BITS = 20; - input wire [31:0] dt_request_vaddr; - input wire [31:0] dt_request_paddr; - input dt_tlb_hit; - input dt_tlb_present; - input dt_tlb_supervisor; - input dt_tlb_writable; - input wire [511:0] dt_store_value; - input wire [3:0] dt_subcycle; - input [0:3] dt_valid; - input wire [79:0] dt_tag; - output wire dd_update_lru_en; - output wire [1:0] dd_update_lru_way; - output wire dd_io_write_en; - output wire dd_io_read_en; - output wire [1:0] dd_io_thread_idx; - output wire [31:0] dd_io_addr; - output wire [31:0] dd_io_write_value; - output reg dd_instruction_valid; - output reg [141:0] dd_instruction; - output reg [15:0] dd_lane_mask; - output reg [1:0] dd_thread_idx; - output reg [31:0] dd_request_vaddr; - output reg [3:0] dd_subcycle; - output reg dd_rollback_en; - output reg [31:0] dd_rollback_pc; - localparam defines_CACHE_LINE_BITS = 512; - output wire [511:0] dd_load_data; - output reg dd_suspend_thread; - output reg dd_io_access; - output reg dd_trap; - output reg [5:0] dd_trap_cause; - input wire [0:3] cr_supervisor_en; - output wire dd_creg_write_en; - output wire dd_creg_read_en; - output wire [4:0] dd_creg_index; - output wire [31:0] dd_creg_write_val; - input l2i_ddata_update_en; - input wire [1:0] l2i_ddata_update_way; - input wire [5:0] l2i_ddata_update_set; - input wire [511:0] l2i_ddata_update_data; - input [3:0] l2i_dtag_update_en_oh; - input wire [5:0] l2i_dtag_update_set; - input wire [19:0] l2i_dtag_update_tag; - output wire dd_cache_miss; - output wire [25:0] dd_cache_miss_addr; - output wire [1:0] dd_cache_miss_thread_idx; - output wire dd_cache_miss_sync; - output wire dd_store_en; - output wire dd_flush_en; - output wire dd_membar_en; - output wire dd_iinvalidate_en; - output wire dd_dinvalidate_en; - output wire [63:0] dd_store_mask; - output wire [25:0] dd_store_addr; - output reg [511:0] dd_store_data; - output wire [1:0] dd_store_thread_idx; - output wire dd_store_sync; - output wire [25:0] dd_store_bypass_addr; - output wire [1:0] dd_store_bypass_thread_idx; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wire [1:0] wb_rollback_pipeline; - output reg dd_perf_dcache_hit; - output reg dd_perf_dcache_miss; - output reg dd_perf_dtlb_miss; - wire memory_access_req; - wire cached_access_req; - wire cached_load_req; - wire cached_store_req; - wire creg_access_req; - wire io_access_req; - wire sync_access_req; - wire cache_control_req; - wire tlb_update_req; - wire flush_req; - wire iinvalidate_req; - wire dinvalidate_req; - wire membar_req; - wire addr_in_io_region; - reg unaligned_address; - wire supervisor_fault; - wire alignment_fault; - wire privileged_op_fault; - wire write_fault; - wire tlb_miss; - wire page_fault; - wire any_fault; - reg [15:0] word_store_mask; - reg [3:0] byte_store_mask; - localparam defines_CACHE_LINE_WORDS = 16; - wire [3:0] cache_lane_idx; - wire [511:0] endian_twiddled_data; - wire [31:0] lane_store_value; - wire [15:0] cache_lane_mask; - wire [15:0] subcycle_mask; - wire [3:0] way_hit_oh; - wire [1:0] way_hit_idx; - wire cache_hit; - wire [31:0] dcache_request_addr; - wire squash_instruction; - wire cache_near_miss; - wire [3:0] scgath_lane; - reg tlb_read; - wire fault_store_flag; - wire lane_enabled; - assign squash_instruction = (wb_rollback_en && (wb_rollback_thread_idx == dt_thread_idx)) && (wb_rollback_pipeline == 2'd0); - assign scgath_lane = ~dt_subcycle; - idx_to_oh #( - .NUM_SIGNALS(defines_CACHE_LINE_WORDS), - .DIRECTION("LSB0") - ) idx_to_oh_subcycle( - .one_hot(subcycle_mask), - .index(dt_subcycle) - ); - assign lane_enabled = (!dt_instruction[19] || (dt_instruction[18-:4] != 4'b1110)) || ((dt_mask_value & subcycle_mask) != 0); - assign addr_in_io_region = (dt_request_paddr | 32'h0000ffff) == 32'hffffffff; - assign sync_access_req = dt_instruction[18-:4] == 4'b0101; - assign memory_access_req = (((dt_instruction_valid && !squash_instruction) && dt_instruction[19]) && (dt_instruction[18-:4] != 4'b0110)) && lane_enabled; - assign io_access_req = memory_access_req && addr_in_io_region; - assign cached_access_req = memory_access_req && !addr_in_io_region; - assign cached_load_req = cached_access_req && dt_instruction[14]; - assign cached_store_req = cached_access_req && !dt_instruction[14]; - assign cache_control_req = (dt_instruction_valid && !squash_instruction) && dt_instruction[3]; - assign flush_req = (cache_control_req && (dt_instruction[2-:3] == 3'b010)) && !addr_in_io_region; - assign iinvalidate_req = (cache_control_req && (dt_instruction[2-:3] == 3'b011)) && !addr_in_io_region; - assign dinvalidate_req = (cache_control_req && (dt_instruction[2-:3] == 3'b001)) && !addr_in_io_region; - assign membar_req = cache_control_req && (dt_instruction[2-:3] == 3'b100); - assign tlb_update_req = cache_control_req && ((((dt_instruction[2-:3] == 3'b000) || (dt_instruction[2-:3] == 3'b111)) || (dt_instruction[2-:3] == 3'b101)) || (dt_instruction[2-:3] == 3'b110)); - assign creg_access_req = ((dt_instruction_valid && !squash_instruction) && dt_instruction[19]) && (dt_instruction[18-:4] == 4'b0110); - always @(*) begin - if (_sv2v_0) - ; - tlb_read = 0; - if (dt_instruction_valid && !squash_instruction) begin - if (dt_instruction[19]) - tlb_read = (dt_instruction[18-:4] != 4'b0110) && lane_enabled; - else if (dt_instruction[3]) - tlb_read = (dt_instruction[2-:3] == 3'b010) || (dt_instruction[2-:3] == 3'b001); - end - end - assign tlb_miss = tlb_read && !dt_tlb_hit; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dt_instruction[18-:4]) - 4'b0010, 4'b0011: unaligned_address = dt_request_paddr[0]; - 4'b0100, 4'b0101, 4'b1101, 4'b1110: unaligned_address = |dt_request_paddr[1:0]; - 4'b0111, 4'b1000: unaligned_address = dt_request_paddr[5-:defines_CACHE_LINE_OFFSET_WIDTH] != 0; - default: unaligned_address = 0; - endcase - end - assign alignment_fault = (cached_access_req || io_access_req) && unaligned_address; - assign privileged_op_fault = ((creg_access_req || tlb_update_req) || dinvalidate_req) && !cr_supervisor_en[dt_thread_idx]; - assign page_fault = (memory_access_req && dt_tlb_hit) && !dt_tlb_present; - assign supervisor_fault = (((memory_access_req && dt_tlb_hit) && dt_tlb_present) && dt_tlb_supervisor) && !cr_supervisor_en[dt_thread_idx]; - assign write_fault = ((((cached_store_req || (io_access_req && !dt_instruction[14])) && dt_tlb_hit) && dt_tlb_present) && !supervisor_fault) && !dt_tlb_writable; - assign any_fault = (((alignment_fault || privileged_op_fault) || page_fault) || supervisor_fault) || write_fault; - assign dd_store_en = (cached_store_req && !tlb_miss) && !any_fault; - assign dcache_request_addr = {dt_request_paddr[31:defines_CACHE_LINE_OFFSET_WIDTH], {defines_CACHE_LINE_OFFSET_WIDTH {1'b0}}}; - assign cache_lane_idx = dt_request_paddr[5:2]; - assign dd_store_bypass_addr = dt_request_paddr[31:defines_CACHE_LINE_OFFSET_WIDTH]; - assign dd_store_bypass_thread_idx = dt_thread_idx; - assign dd_store_addr = dt_request_paddr[31:defines_CACHE_LINE_OFFSET_WIDTH]; - assign dd_store_sync = sync_access_req; - assign dd_store_thread_idx = dt_thread_idx; - assign dd_io_write_en = ((io_access_req && !dt_instruction[14]) && !tlb_miss) && !any_fault; - assign dd_io_read_en = ((io_access_req && dt_instruction[14]) && !tlb_miss) && !any_fault; - assign dd_io_write_value = dt_store_value[0+:32]; - assign dd_io_thread_idx = dt_thread_idx; - assign dd_io_addr = {16'd0, dt_request_paddr[15:0]}; - assign dd_creg_write_en = (creg_access_req && !dt_instruction[14]) && !any_fault; - assign dd_creg_read_en = (creg_access_req && dt_instruction[14]) && !any_fault; - assign dd_creg_write_val = dt_store_value[0+:32]; - assign dd_creg_index = dt_instruction[8-:5]; - assign dd_flush_en = (((flush_req && dt_tlb_hit) && dt_tlb_present) && !io_access_req) && !any_fault; - assign dd_iinvalidate_en = (((iinvalidate_req && dt_tlb_hit) && dt_tlb_present) && !io_access_req) && !any_fault; - assign dd_dinvalidate_en = (((dinvalidate_req && dt_tlb_hit) && dt_tlb_present) && !io_access_req) && !any_fault; - assign dd_membar_en = membar_req && (dt_instruction[2-:3] == 3'b100); - genvar _gv_way_idx_1; - generate - for (_gv_way_idx_1 = 0; _gv_way_idx_1 < 4; _gv_way_idx_1 = _gv_way_idx_1 + 1) begin : hit_check_gen - localparam way_idx = _gv_way_idx_1; - assign way_hit_oh[way_idx] = (dt_request_paddr[31-:20] == dt_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS]) && dt_valid[way_idx]; - end - endgenerate - assign cache_hit = (|way_hit_oh && (!sync_access_req || dd_load_sync_pending[dt_thread_idx])) && dt_tlb_hit; - idx_to_oh #( - .NUM_SIGNALS(defines_CACHE_LINE_WORDS), - .DIRECTION("LSB0") - ) idx_to_oh_cache_lane( - .one_hot(cache_lane_mask), - .index(cache_lane_idx) - ); - always @(*) begin - if (_sv2v_0) - ; - word_store_mask = 0; - (* full_case, parallel_case *) - case (dt_instruction[18-:4]) - 4'b0111, 4'b1000: word_store_mask = dt_mask_value; - 4'b1101, 4'b1110: - if ((dt_mask_value & subcycle_mask) != 0) - word_store_mask = cache_lane_mask; - else - word_store_mask = 0; - default: word_store_mask = cache_lane_mask; - endcase - end - genvar _gv_swap_word_1; - generate - for (_gv_swap_word_1 = 0; _gv_swap_word_1 < 16; _gv_swap_word_1 = _gv_swap_word_1 + 1) begin : swap_word_gen - localparam swap_word = _gv_swap_word_1; - assign endian_twiddled_data[swap_word * 32+:8] = dt_store_value[(swap_word * 32) + 24+:8]; - assign endian_twiddled_data[(swap_word * 32) + 8+:8] = dt_store_value[(swap_word * 32) + 16+:8]; - assign endian_twiddled_data[(swap_word * 32) + 16+:8] = dt_store_value[(swap_word * 32) + 8+:8]; - assign endian_twiddled_data[(swap_word * 32) + 24+:8] = dt_store_value[swap_word * 32+:8]; - end - endgenerate - assign lane_store_value = dt_store_value[scgath_lane * 32+:32]; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dt_instruction[18-:4]) - 4'b0000, 4'b0001: begin - dd_store_data = {64 {dt_store_value[7-:8]}}; - case (dt_request_paddr[1:0]) - 2'd0: byte_store_mask = 4'b1000; - 2'd1: byte_store_mask = 4'b0100; - 2'd2: byte_store_mask = 4'b0010; - 2'd3: byte_store_mask = 4'b0001; - default: byte_store_mask = 4'b0000; - endcase - end - 4'b0010, 4'b0011: begin - dd_store_data = {32 {dt_store_value[7-:8], dt_store_value[15-:8]}}; - if (dt_request_paddr[1] == 1'b0) - byte_store_mask = 4'b1100; - else - byte_store_mask = 4'b0011; - end - 4'b0100, 4'b0101: begin - byte_store_mask = 4'b1111; - dd_store_data = {defines_CACHE_LINE_WORDS {dt_store_value[7-:8], dt_store_value[15-:8], dt_store_value[23-:8], dt_store_value[31-:8]}}; - end - 4'b1101, 4'b1110: begin - byte_store_mask = 4'b1111; - dd_store_data = {defines_CACHE_LINE_WORDS {lane_store_value[7:0], lane_store_value[15:8], lane_store_value[23:16], lane_store_value[31:24]}}; - end - default: begin - byte_store_mask = 4'b1111; - dd_store_data = endian_twiddled_data; - end - endcase - end - genvar _gv_mask_idx_1; - generate - for (_gv_mask_idx_1 = 0; _gv_mask_idx_1 < defines_CACHE_LINE_BYTES; _gv_mask_idx_1 = _gv_mask_idx_1 + 1) begin : store_mask_gen - localparam mask_idx = _gv_mask_idx_1; - assign dd_store_mask[mask_idx] = word_store_mask[((defines_CACHE_LINE_BYTES - mask_idx) - 1) / 4] & byte_store_mask[mask_idx & 3]; - end - endgenerate - oh_to_idx #(.NUM_SIGNALS(4)) encode_hit_way( - .one_hot(way_hit_oh), - .index(way_hit_idx) - ); - fakeram_1r1w_512x256 #( - .DATA_WIDTH(defines_CACHE_LINE_BITS), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) l1d_data( - .read_en(cache_hit && cached_load_req), - .read_addr({way_hit_idx, dt_request_paddr[11-:6]}), - .read_data(dd_load_data), - .write_en(l2i_ddata_update_en), - .write_addr({l2i_ddata_update_way, l2i_ddata_update_set}), - .write_data(l2i_ddata_update_data), - .* - ); - assign cache_near_miss = ((((((!cache_hit && dt_tlb_hit) && cached_load_req) && |l2i_dtag_update_en_oh) && (l2i_dtag_update_set == dt_request_paddr[11-:6])) && (l2i_dtag_update_tag == dt_request_paddr[31-:20])) && !sync_access_req) && !any_fault; - assign dd_cache_miss = (((cached_load_req && !cache_hit) && dt_tlb_hit) && !cache_near_miss) && !any_fault; - assign dd_cache_miss_addr = dcache_request_addr[31:defines_CACHE_LINE_OFFSET_WIDTH]; - assign dd_cache_miss_thread_idx = dt_thread_idx; - assign dd_cache_miss_sync = sync_access_req; - assign dd_update_lru_en = (cache_hit && cached_access_req) && !any_fault; - assign dd_update_lru_way = way_hit_idx; - genvar _gv_thread_idx_2; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_2 = 0; _gv_thread_idx_2 < 4; _gv_thread_idx_2 = _gv_thread_idx_2 + 1) begin : sync_pending_gen - localparam thread_idx = _gv_thread_idx_2; - always @(posedge clk or posedge reset) - if (reset) - dd_load_sync_pending[thread_idx] <= 0; - else if ((cached_load_req && sync_access_req) && (dt_thread_idx == sv2v_cast_2(thread_idx))) - dd_load_sync_pending[thread_idx] <= !dd_load_sync_pending[thread_idx]; - end - endgenerate - assign fault_store_flag = dt_instruction[19] && !dt_instruction[14]; - always @(posedge clk) begin - dd_instruction <= dt_instruction; - dd_lane_mask <= dt_mask_value; - dd_thread_idx <= dt_thread_idx; - dd_request_vaddr <= dt_request_vaddr; - dd_subcycle <= dt_subcycle; - dd_rollback_pc <= dt_instruction[141-:32]; - dd_io_access <= io_access_req; - if (tlb_miss) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd7}; - else if (page_fault) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd6}; - else if (supervisor_fault) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd9}; - else if (alignment_fault) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd5}; - else if (privileged_op_fault) - dd_trap_cause <= 6'h02; - else - dd_trap_cause <= 6'h38; - end - always @(posedge clk or posedge reset) - if (reset) begin - dd_instruction_valid <= 1'sb0; - dd_perf_dcache_hit <= 1'sb0; - dd_perf_dcache_miss <= 1'sb0; - dd_perf_dtlb_miss <= 1'sb0; - dd_rollback_en <= 1'sb0; - dd_suspend_thread <= 1'sb0; - dd_trap <= 1'sb0; - end - else begin - dd_instruction_valid <= dt_instruction_valid && !squash_instruction; - dd_rollback_en <= ((cached_load_req && !cache_hit) && dt_tlb_hit) && !any_fault; - dd_suspend_thread <= (((cached_load_req && dt_tlb_hit) && !cache_hit) && !cache_near_miss) && !any_fault; - dd_trap <= any_fault || tlb_miss; - dd_perf_dcache_hit <= ((cached_load_req && !any_fault) && !tlb_miss) && cache_hit; - dd_perf_dcache_miss <= ((cached_load_req && !any_fault) && !tlb_miss) && !cache_hit; - dd_perf_dtlb_miss <= tlb_miss; - end - initial _sv2v_0 = 0; -endmodule -module dcache_tag_stage ( - clk, - reset, - of_operand1, - of_mask_value, - of_store_value, - of_instruction_valid, - of_instruction, - of_thread_idx, - of_subcycle, - dd_update_lru_en, - dd_update_lru_way, - dt_instruction_valid, - dt_instruction, - dt_mask_value, - dt_thread_idx, - dt_request_vaddr, - dt_request_paddr, - dt_tlb_hit, - dt_tlb_writable, - dt_store_value, - dt_subcycle, - dt_valid, - dt_tag, - dt_tlb_supervisor, - dt_tlb_present, - dt_invalidate_tlb_en, - dt_invalidate_tlb_all_en, - dt_update_itlb_en, - dt_update_itlb_asid, - dt_update_itlb_vpage_idx, - dt_update_itlb_ppage_idx, - dt_update_itlb_present, - dt_update_itlb_supervisor, - dt_update_itlb_global, - dt_update_itlb_executable, - l2i_dcache_lru_fill_en, - l2i_dcache_lru_fill_set, - l2i_dtag_update_en_oh, - l2i_dtag_update_set, - l2i_dtag_update_tag, - l2i_dtag_update_valid, - l2i_snoop_en, - l2i_snoop_set, - dt_snoop_valid, - dt_snoop_tag, - dt_fill_lru, - cr_mmu_en, - cr_supervisor_en, - cr_current_asid, - wb_rollback_en, - wb_rollback_thread_idx -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [511:0] of_operand1; - input wire [15:0] of_mask_value; - input wire [511:0] of_store_value; - input of_instruction_valid; - input wire [141:0] of_instruction; - input wire [1:0] of_thread_idx; - input wire [3:0] of_subcycle; - input dd_update_lru_en; - input wire [1:0] dd_update_lru_way; - output reg dt_instruction_valid; - output reg [141:0] dt_instruction; - output reg [15:0] dt_mask_value; - output reg [1:0] dt_thread_idx; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_DCACHE_TAG_BITS = 20; - output wire [31:0] dt_request_vaddr; - output wire [31:0] dt_request_paddr; - output reg dt_tlb_hit; - output reg dt_tlb_writable; - output reg [511:0] dt_store_value; - output reg [3:0] dt_subcycle; - output reg [0:3] dt_valid; - output wire [79:0] dt_tag; - output reg dt_tlb_supervisor; - output reg dt_tlb_present; - output wire dt_invalidate_tlb_en; - output wire dt_invalidate_tlb_all_en; - output wire dt_update_itlb_en; - localparam defines_ASID_WIDTH = 8; - output wire [7:0] dt_update_itlb_asid; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - output wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_vpage_idx; - output wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_ppage_idx; - output wire dt_update_itlb_present; - output wire dt_update_itlb_supervisor; - output wire dt_update_itlb_global; - output wire dt_update_itlb_executable; - input l2i_dcache_lru_fill_en; - input wire [5:0] l2i_dcache_lru_fill_set; - input [3:0] l2i_dtag_update_en_oh; - input wire [5:0] l2i_dtag_update_set; - input wire [19:0] l2i_dtag_update_tag; - input l2i_dtag_update_valid; - input l2i_snoop_en; - input wire [5:0] l2i_snoop_set; - output reg [0:3] dt_snoop_valid; - output wire [79:0] dt_snoop_tag; - output wire [1:0] dt_fill_lru; - input [0:3] cr_mmu_en; - input wire [0:3] cr_supervisor_en; - input [31:0] cr_current_asid; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - wire [31:0] request_addr_nxt; - wire cache_load_en; - wire instruction_valid; - wire [3:0] scgath_lane; - wire [defines_PAGE_NUM_BITS - 1:0] tlb_ppage_idx; - wire tlb_hit; - reg [defines_PAGE_NUM_BITS - 1:0] ppage_idx; - reg [31:0] fetched_addr; - wire tlb_lookup_en; - wire valid_cache_control; - wire update_dtlb_en; - wire tlb_writable; - wire tlb_present; - wire tlb_supervisor; - wire [(defines_PAGE_NUM_BITS + (32 - (defines_PAGE_NUM_BITS + 5))) + 4:0] new_tlb_value; - assign instruction_valid = (of_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != of_thread_idx))) && (of_instruction[21-:2] == 2'd0); - assign valid_cache_control = instruction_valid && of_instruction[3]; - assign cache_load_en = ((instruction_valid && (of_instruction[18-:4] != 4'b0110)) && of_instruction[19]) && of_instruction[14]; - assign scgath_lane = ~of_subcycle; - assign request_addr_nxt = of_operand1[scgath_lane * 32+:32] + of_instruction[58-:32]; - assign new_tlb_value = of_store_value[0+:32]; - assign dt_invalidate_tlb_en = (valid_cache_control && (of_instruction[2-:3] == 3'b101)) && cr_supervisor_en[of_thread_idx]; - assign dt_invalidate_tlb_all_en = (valid_cache_control && (of_instruction[2-:3] == 3'b110)) && cr_supervisor_en[of_thread_idx]; - assign update_dtlb_en = (valid_cache_control && (of_instruction[2-:3] == 3'b000)) && cr_supervisor_en[of_thread_idx]; - assign dt_update_itlb_en = (valid_cache_control && (of_instruction[2-:3] == 3'b111)) && cr_supervisor_en[of_thread_idx]; - assign dt_update_itlb_supervisor = new_tlb_value[3]; - assign dt_update_itlb_global = new_tlb_value[4]; - assign dt_update_itlb_present = new_tlb_value[0]; - assign tlb_lookup_en = (((instruction_valid && (of_instruction[18-:4] != 4'b0110)) && !update_dtlb_en) && !dt_invalidate_tlb_en) && !dt_invalidate_tlb_all_en; - assign dt_update_itlb_vpage_idx = of_operand1[31-:defines_PAGE_NUM_BITS]; - assign dt_update_itlb_ppage_idx = new_tlb_value[defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))-:((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) >= (37 - (defines_PAGE_NUM_BITS + 5)) ? ((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) - (37 - (defines_PAGE_NUM_BITS + 5))) + 1 : ((37 - (defines_PAGE_NUM_BITS + 5)) - (defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5)))) + 1)]; - assign dt_update_itlb_executable = new_tlb_value[2]; - assign dt_update_itlb_asid = cr_current_asid[(3 - of_thread_idx) * 8+:8]; - genvar _gv_way_idx_2; - generate - for (_gv_way_idx_2 = 0; _gv_way_idx_2 < 4; _gv_way_idx_2 = _gv_way_idx_2 + 1) begin : way_tag_gen - localparam way_idx = _gv_way_idx_2; - reg line_valid [0:63]; - fakeram_2r1w_20x64 #( - .DATA_WIDTH(defines_DCACHE_TAG_BITS), - .SIZE(64), - .READ_DURING_WRITE("NEW_DATA") - ) sram_tags( - .read1_en(cache_load_en), - .read1_addr(request_addr_nxt[11-:6]), - .read1_data(dt_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS]), - .read2_en(l2i_snoop_en), - .read2_addr(l2i_snoop_set), - .read2_data(dt_snoop_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS]), - .write_en(l2i_dtag_update_en_oh[way_idx]), - .write_addr(l2i_dtag_update_set), - .write_data(l2i_dtag_update_tag), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < 64; set_idx = set_idx + 1) - line_valid[set_idx] <= 0; - end - else if (l2i_dtag_update_en_oh[way_idx]) - line_valid[l2i_dtag_update_set] <= l2i_dtag_update_valid; - always @(posedge clk) begin - if (cache_load_en) begin - if (l2i_dtag_update_en_oh[way_idx] && (l2i_dtag_update_set == request_addr_nxt[11-:6])) - dt_valid[way_idx] <= l2i_dtag_update_valid; - else - dt_valid[way_idx] <= line_valid[request_addr_nxt[11-:6]]; - end - if (l2i_snoop_en) begin - if (l2i_dtag_update_en_oh[way_idx] && (l2i_dtag_update_set == l2i_snoop_set)) - dt_snoop_valid[way_idx] <= l2i_dtag_update_valid; - else - dt_snoop_valid[way_idx] <= line_valid[l2i_snoop_set]; - end - end - end - endgenerate - tlb #( - .NUM_ENTRIES(64), - .NUM_WAYS(4) - ) dtlb( - .lookup_en(tlb_lookup_en), - .update_en(update_dtlb_en), - .invalidate_en(dt_invalidate_tlb_en), - .invalidate_all_en(dt_invalidate_tlb_all_en), - .request_vpage_idx(request_addr_nxt[31-:defines_PAGE_NUM_BITS]), - .request_asid(cr_current_asid[(3 - of_thread_idx) * 8+:8]), - .update_ppage_idx(new_tlb_value[defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))-:((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) >= (37 - (defines_PAGE_NUM_BITS + 5)) ? ((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) - (37 - (defines_PAGE_NUM_BITS + 5))) + 1 : ((37 - (defines_PAGE_NUM_BITS + 5)) - (defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5)))) + 1)]), - .update_present(new_tlb_value[0]), - .update_exe_writable(new_tlb_value[1]), - .update_supervisor(new_tlb_value[3]), - .update_global(new_tlb_value[4]), - .lookup_ppage_idx(tlb_ppage_idx), - .lookup_hit(tlb_hit), - .lookup_present(tlb_present), - .lookup_exe_writable(tlb_writable), - .lookup_supervisor(tlb_supervisor), - .clk(clk), - .reset(reset) - ); - always @(*) begin - if (_sv2v_0) - ; - if (cr_mmu_en[dt_thread_idx]) begin - dt_tlb_hit = tlb_hit; - dt_tlb_writable = tlb_writable; - dt_tlb_present = tlb_present; - dt_tlb_supervisor = tlb_supervisor; - ppage_idx = tlb_ppage_idx; - end - else begin - dt_tlb_hit = 1; - dt_tlb_writable = 1; - dt_tlb_present = 1; - dt_tlb_supervisor = 0; - ppage_idx = fetched_addr[31-:defines_PAGE_NUM_BITS]; - end - end - cache_lru #( - .NUM_WAYS(4), - .NUM_SETS(64) - ) lru( - .fill_en(l2i_dcache_lru_fill_en), - .fill_set(l2i_dcache_lru_fill_set), - .fill_way(dt_fill_lru), - .access_en(instruction_valid), - .access_set(request_addr_nxt[11-:6]), - .update_en(dd_update_lru_en), - .update_way(dd_update_lru_way), - .clk(clk), - .reset(reset) - ); - always @(posedge clk) begin - dt_instruction <= of_instruction; - dt_mask_value <= of_mask_value; - dt_thread_idx <= of_thread_idx; - dt_store_value <= of_store_value; - dt_subcycle <= of_subcycle; - fetched_addr <= request_addr_nxt; - end - always @(posedge clk or posedge reset) - if (reset) - dt_instruction_valid <= 1'sb0; - else - dt_instruction_valid <= instruction_valid; - assign dt_request_paddr = {ppage_idx, fetched_addr[31 - defines_PAGE_NUM_BITS:0]}; - assign dt_request_vaddr = fetched_addr; - initial _sv2v_0 = 0; -endmodule -module fp_execute_stage1 ( - clk, - reset, - wb_rollback_en, - wb_rollback_thread_idx, - of_operand1, - of_operand2, - of_mask_value, - of_instruction_valid, - of_instruction, - of_thread_idx, - of_subcycle, - fx1_instruction_valid, - fx1_instruction, - fx1_mask_value, - fx1_thread_idx, - fx1_subcycle, - fx1_result_inf, - fx1_result_nan, - fx1_equal, - fx1_ftoi_lshift, - fx1_significand_le, - fx1_significand_se, - fx1_se_align_shift, - fx1_add_exponent, - fx1_logical_subtract, - fx1_add_result_sign, - fx1_multiplicand, - fx1_multiplier, - fx1_mul_exponent, - fx1_mul_underflow, - fx1_mul_sign -); - reg _sv2v_0; - input clk; - input reset; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [511:0] of_operand1; - input wire [511:0] of_operand2; - input wire [15:0] of_mask_value; - input of_instruction_valid; - input wire [141:0] of_instruction; - input wire [1:0] of_thread_idx; - input wire [3:0] of_subcycle; - output reg fx1_instruction_valid; - output reg [141:0] fx1_instruction; - output reg [15:0] fx1_mask_value; - output reg [1:0] fx1_thread_idx; - output reg [3:0] fx1_subcycle; - output reg [15:0] fx1_result_inf; - output reg [15:0] fx1_result_nan; - output reg [15:0] fx1_equal; - output reg [95:0] fx1_ftoi_lshift; - output reg [511:0] fx1_significand_le; - output reg [511:0] fx1_significand_se; - output reg [95:0] fx1_se_align_shift; - output reg [127:0] fx1_add_exponent; - output reg [15:0] fx1_logical_subtract; - output reg [15:0] fx1_add_result_sign; - output reg [511:0] fx1_multiplicand; - output reg [511:0] fx1_multiplier; - output reg [127:0] fx1_mul_exponent; - output reg [15:0] fx1_mul_underflow; - output reg [15:0] fx1_mul_sign; - wire fmul; - wire imul; - wire ftoi; - wire itof; - wire compare; - assign fmul = of_instruction[70-:6] == 6'b100010; - assign imul = ((of_instruction[70-:6] == 6'b000111) || (of_instruction[70-:6] == 6'b001000)) || (of_instruction[70-:6] == 6'b011111); - assign ftoi = of_instruction[70-:6] == 6'b011011; - assign itof = of_instruction[70-:6] == 6'b101010; - assign compare = (((((of_instruction[70-:6] == 6'b101100) || (of_instruction[70-:6] == 6'b101110)) || (of_instruction[70-:6] == 6'b101101)) || (of_instruction[70-:6] == 6'b101111)) || (of_instruction[70-:6] == 6'b110000)) || (of_instruction[70-:6] == 6'b110001); - genvar _gv_lane_idx_1; - localparam defines_FLOAT32_EXP_WIDTH = 8; - localparam defines_FLOAT32_SIG_WIDTH = 23; - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - generate - for (_gv_lane_idx_1 = 0; _gv_lane_idx_1 < defines_NUM_VECTOR_LANES; _gv_lane_idx_1 = _gv_lane_idx_1 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_1; - wire [31:0] fop1; - wire [31:0] fop2; - wire [defines_FLOAT32_SIG_WIDTH:0] full_significand1; - wire [defines_FLOAT32_SIG_WIDTH:0] full_significand2; - wire op1_hidden_bit; - wire op2_hidden_bit; - wire op1_larger; - wire [7:0] exp_difference; - wire subtract; - wire [7:0] mul_exponent; - wire fop1_inf; - wire fop1_nan; - wire fop2_inf; - wire fop2_nan; - reg logical_subtract; - reg result_nan; - wire equal; - wire mul_exponent_underflow; - wire mul_exponent_carry; - reg [5:0] ftoi_rshift; - reg [5:0] ftoi_lshift_nxt; - assign fop1 = of_operand1[lane_idx * 32+:32]; - assign fop2 = of_operand2[lane_idx * 32+:32]; - assign op1_hidden_bit = fop1[30-:8] != 0; - assign op2_hidden_bit = fop2[30-:8] != 0; - assign full_significand1 = {op1_hidden_bit, fop1[22-:defines_FLOAT32_SIG_WIDTH]}; - assign full_significand2 = {op2_hidden_bit, fop2[22-:defines_FLOAT32_SIG_WIDTH]}; - assign subtract = of_instruction[70-:6] != 6'b100000; - assign fop1_inf = (fop1[30-:8] == 8'hff) && (fop1[22-:defines_FLOAT32_SIG_WIDTH] == 0); - assign fop1_nan = (fop1[30-:8] == 8'hff) && (fop1[22-:defines_FLOAT32_SIG_WIDTH] != 0); - assign fop2_inf = (fop2[30-:8] == 8'hff) && (fop2[22-:defines_FLOAT32_SIG_WIDTH] == 0); - assign fop2_nan = (fop2[30-:8] == 8'hff) && (fop2[22-:defines_FLOAT32_SIG_WIDTH] != 0); - always @(*) begin - if (_sv2v_0) - ; - if (fop2[30-:8] < 8'd118) begin - ftoi_rshift = 6'd32; - ftoi_lshift_nxt = 0; - end - else if (fop2[30-:8] < 8'd150) begin - ftoi_rshift = sv2v_cast_6(8'd150 - fop2[30-:8]); - ftoi_lshift_nxt = 0; - end - else begin - ftoi_rshift = 6'd0; - ftoi_lshift_nxt = sv2v_cast_6(fop2[30-:8] - 8'd150); - end - end - always @(*) begin - if (_sv2v_0) - ; - if (itof) - logical_subtract = of_operand2[(lane_idx * 32) + 31]; - else if (ftoi) - logical_subtract = fop2[31]; - else - logical_subtract = (fop1[31] ^ fop2[31]) ^ subtract; - end - always @(*) begin - if (_sv2v_0) - ; - if (itof) - result_nan = 0; - else if (fmul) - result_nan = ((fop1_nan || fop2_nan) || (fop1_inf && (of_operand2[lane_idx * 32+:32] == 0))) || (fop2_inf && (of_operand1[lane_idx * 32+:32] == 0)); - else if (ftoi) - result_nan = (fop2_nan || fop2_inf) || (fop2[30-:8] >= 8'd159); - else if (compare) - result_nan = fop1_nan || fop2_nan; - else - result_nan = (fop1_nan || fop2_nan) || ((fop1_inf && fop2_inf) && logical_subtract); - end - assign equal = ((fop1_inf && fop2_inf) && (fop1[31] == fop2[31])) || ((!fop1_inf && !fop2_inf) && (fop1 == fop2)); - assign {mul_exponent_underflow, mul_exponent_carry, mul_exponent} = ({2'd0, fop1[30-:8]} + {2'd0, fop2[30-:8]}) - 10'd127; - assign op1_larger = (fop1[30-:8] > fop2[30-:8]) || ((fop1[30-:8] == fop2[30-:8]) && (full_significand1 >= full_significand2)); - assign exp_difference = (op1_larger ? fop1[30-:8] - fop2[30-:8] : fop2[30-:8] - fop1[30-:8]); - always @(posedge clk) begin - fx1_result_nan[lane_idx] <= result_nan; - fx1_result_inf[lane_idx] <= (!itof && !result_nan) && ((fop1_inf || fop2_inf) || ((fmul && mul_exponent_carry) && !mul_exponent_underflow)); - fx1_equal[lane_idx] <= equal; - fx1_mul_underflow[lane_idx] <= mul_exponent_underflow; - if ((op1_larger || ftoi) || itof) begin - if (ftoi || itof) - fx1_significand_le[lane_idx * 32+:32] <= 0; - else - fx1_significand_le[lane_idx * 32+:32] <= sv2v_cast_32(full_significand1); - if (itof) begin - fx1_significand_se[lane_idx * 32+:32] <= of_operand2[lane_idx * 32+:32]; - fx1_add_exponent[lane_idx * 8+:8] <= 8'd127 + 8'd23; - fx1_add_result_sign[lane_idx] <= of_operand2[(lane_idx * 32) + 31]; - end - else begin - fx1_significand_se[lane_idx * 32+:32] <= sv2v_cast_32(full_significand2); - fx1_add_exponent[lane_idx * 8+:8] <= fop1[30-:8]; - fx1_add_result_sign[lane_idx] <= fop1[31]; - end - end - else begin - fx1_significand_le[lane_idx * 32+:32] <= sv2v_cast_32(full_significand2); - fx1_significand_se[lane_idx * 32+:32] <= sv2v_cast_32(full_significand1); - fx1_add_exponent[lane_idx * 8+:8] <= fop2[30-:8]; - fx1_add_result_sign[lane_idx] <= fop2[31] ^ subtract; - end - fx1_logical_subtract[lane_idx] <= logical_subtract; - if (itof) - fx1_se_align_shift[lane_idx * 6+:6] <= 0; - else if (ftoi) - fx1_se_align_shift[lane_idx * 6+:6] <= ftoi_rshift[5:0]; - else - fx1_se_align_shift[lane_idx * 6+:6] <= (exp_difference < 8'd27 ? sv2v_cast_6(exp_difference) : 6'd27); - fx1_ftoi_lshift[lane_idx * 6+:6] <= ftoi_lshift_nxt; - if (imul) begin - fx1_multiplicand[lane_idx * 32+:32] <= of_operand1[lane_idx * 32+:32]; - fx1_multiplier[lane_idx * 32+:32] <= of_operand2[lane_idx * 32+:32]; - end - else begin - fx1_multiplicand[lane_idx * 32+:32] <= sv2v_cast_32(full_significand1); - fx1_multiplier[lane_idx * 32+:32] <= sv2v_cast_32(full_significand2); - end - fx1_mul_exponent[lane_idx * 8+:8] <= mul_exponent; - fx1_mul_sign[lane_idx] <= fop1[31] ^ fop2[31]; - end - end - endgenerate - always @(posedge clk) begin - fx1_instruction <= of_instruction; - fx1_mask_value <= of_mask_value; - fx1_thread_idx <= of_thread_idx; - fx1_subcycle <= of_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx1_instruction_valid <= 1'sb0; - else - fx1_instruction_valid <= (of_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != of_thread_idx))) && (of_instruction[21-:2] == 2'd2); - initial _sv2v_0 = 0; -endmodule -module fp_execute_stage2 ( - clk, - reset, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pipeline, - fx1_mask_value, - fx1_instruction_valid, - fx1_instruction, - fx1_thread_idx, - fx1_subcycle, - fx1_result_inf, - fx1_result_nan, - fx1_equal, - fx1_ftoi_lshift, - fx1_significand_le, - fx1_significand_se, - fx1_logical_subtract, - fx1_se_align_shift, - fx1_add_exponent, - fx1_add_result_sign, - fx1_mul_exponent, - fx1_mul_sign, - fx1_multiplicand, - fx1_multiplier, - fx1_mul_underflow, - fx2_instruction_valid, - fx2_instruction, - fx2_mask_value, - fx2_thread_idx, - fx2_subcycle, - fx2_result_inf, - fx2_result_nan, - fx2_equal, - fx2_ftoi_lshift, - fx2_logical_subtract, - fx2_add_result_sign, - fx2_significand_le, - fx2_significand_se, - fx2_add_exponent, - fx2_guard, - fx2_round, - fx2_sticky, - fx2_significand_product, - fx2_mul_exponent, - fx2_mul_underflow, - fx2_mul_sign -); - input clk; - input reset; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wire [1:0] wb_rollback_pipeline; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx1_mask_value; - input fx1_instruction_valid; - input wire [141:0] fx1_instruction; - input wire [1:0] fx1_thread_idx; - input wire [3:0] fx1_subcycle; - input [15:0] fx1_result_inf; - input [15:0] fx1_result_nan; - input [15:0] fx1_equal; - input [95:0] fx1_ftoi_lshift; - input wire [511:0] fx1_significand_le; - input wire [511:0] fx1_significand_se; - input [15:0] fx1_logical_subtract; - input [95:0] fx1_se_align_shift; - input [127:0] fx1_add_exponent; - input [15:0] fx1_add_result_sign; - input [127:0] fx1_mul_exponent; - input [15:0] fx1_mul_sign; - input [511:0] fx1_multiplicand; - input [511:0] fx1_multiplier; - input [15:0] fx1_mul_underflow; - output reg fx2_instruction_valid; - output reg [141:0] fx2_instruction; - output reg [15:0] fx2_mask_value; - output reg [1:0] fx2_thread_idx; - output reg [3:0] fx2_subcycle; - output reg [15:0] fx2_result_inf; - output reg [15:0] fx2_result_nan; - output reg [15:0] fx2_equal; - output reg [95:0] fx2_ftoi_lshift; - output reg [15:0] fx2_logical_subtract; - output reg [15:0] fx2_add_result_sign; - output reg [511:0] fx2_significand_le; - output reg [511:0] fx2_significand_se; - output reg [127:0] fx2_add_exponent; - output reg [15:0] fx2_guard; - output reg [15:0] fx2_round; - output reg [15:0] fx2_sticky; - output reg [1023:0] fx2_significand_product; - output reg [127:0] fx2_mul_exponent; - output reg [15:0] fx2_mul_underflow; - output reg [15:0] fx2_mul_sign; - wire imulhs; - assign imulhs = fx1_instruction[70-:6] == 6'b011111; - genvar _gv_lane_idx_2; - generate - for (_gv_lane_idx_2 = 0; _gv_lane_idx_2 < defines_NUM_VECTOR_LANES; _gv_lane_idx_2 = _gv_lane_idx_2 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_2; - wire [31:0] aligned_significand; - wire guard; - wire round; - wire [24:0] sticky_bits; - wire sticky; - wire [63:0] sext_multiplicand; - wire [63:0] sext_multiplier; - assign {aligned_significand, guard, round, sticky_bits} = {fx1_significand_se[lane_idx * 32+:32], 27'd0} >> fx1_se_align_shift[lane_idx * 6+:6]; - assign sticky = |sticky_bits; - assign sext_multiplicand = {{32 {fx1_multiplicand[(lane_idx * 32) + 31] && imulhs}}, fx1_multiplicand[lane_idx * 32+:32]}; - assign sext_multiplier = {{32 {fx1_multiplier[(lane_idx * 32) + 31] && imulhs}}, fx1_multiplier[lane_idx * 32+:32]}; - always @(posedge clk) begin - fx2_significand_le[lane_idx * 32+:32] <= fx1_significand_le[lane_idx * 32+:32]; - fx2_significand_se[lane_idx * 32+:32] <= aligned_significand; - fx2_add_exponent[lane_idx * 8+:8] <= fx1_add_exponent[lane_idx * 8+:8]; - fx2_logical_subtract[lane_idx] <= fx1_logical_subtract[lane_idx]; - fx2_add_result_sign[lane_idx] <= fx1_add_result_sign[lane_idx]; - fx2_guard[lane_idx] <= guard; - fx2_round[lane_idx] <= round; - fx2_sticky[lane_idx] <= sticky; - fx2_mul_exponent[lane_idx * 8+:8] <= fx1_mul_exponent[lane_idx * 8+:8]; - fx2_mul_underflow[lane_idx] <= fx1_mul_underflow[lane_idx]; - fx2_mul_sign[lane_idx] <= fx1_mul_sign[lane_idx]; - fx2_result_inf[lane_idx] <= fx1_result_inf[lane_idx]; - fx2_result_nan[lane_idx] <= fx1_result_nan[lane_idx]; - fx2_equal[lane_idx] <= fx1_equal[lane_idx]; - fx2_ftoi_lshift[lane_idx * 6+:6] <= fx1_ftoi_lshift[lane_idx * 6+:6]; - fx2_significand_product[lane_idx * 64+:64] <= sext_multiplicand * sext_multiplier; - end - end - endgenerate - always @(posedge clk) begin - fx2_instruction <= fx1_instruction; - fx2_mask_value <= fx1_mask_value; - fx2_thread_idx <= fx1_thread_idx; - fx2_subcycle <= fx1_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx2_instruction_valid <= 1'sb0; - else - fx2_instruction_valid <= fx1_instruction_valid && ((!wb_rollback_en || (wb_rollback_thread_idx != fx1_thread_idx)) || (wb_rollback_pipeline != 2'd0)); -endmodule -module fp_execute_stage3 ( - clk, - reset, - fx2_mask_value, - fx2_instruction_valid, - fx2_instruction, - fx2_thread_idx, - fx2_subcycle, - fx2_result_inf, - fx2_result_nan, - fx2_equal, - fx2_ftoi_lshift, - fx2_significand_le, - fx2_significand_se, - fx2_logical_subtract, - fx2_add_exponent, - fx2_add_result_sign, - fx2_guard, - fx2_round, - fx2_sticky, - fx2_significand_product, - fx2_mul_exponent, - fx2_mul_underflow, - fx2_mul_sign, - fx3_instruction_valid, - fx3_instruction, - fx3_mask_value, - fx3_thread_idx, - fx3_subcycle, - fx3_result_inf, - fx3_result_nan, - fx3_equal, - fx3_ftoi_lshift, - fx3_add_significand, - fx3_add_exponent, - fx3_add_result_sign, - fx3_logical_subtract, - fx3_significand_product, - fx3_mul_exponent, - fx3_mul_underflow, - fx3_mul_sign -); - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx2_mask_value; - input fx2_instruction_valid; - input wire [141:0] fx2_instruction; - input wire [1:0] fx2_thread_idx; - input wire [3:0] fx2_subcycle; - input [15:0] fx2_result_inf; - input [15:0] fx2_result_nan; - input [15:0] fx2_equal; - input [95:0] fx2_ftoi_lshift; - input wire [511:0] fx2_significand_le; - input wire [511:0] fx2_significand_se; - input [15:0] fx2_logical_subtract; - input [127:0] fx2_add_exponent; - input [15:0] fx2_add_result_sign; - input [15:0] fx2_guard; - input [15:0] fx2_round; - input [15:0] fx2_sticky; - input [1023:0] fx2_significand_product; - input [127:0] fx2_mul_exponent; - input [15:0] fx2_mul_underflow; - input [15:0] fx2_mul_sign; - output reg fx3_instruction_valid; - output reg [141:0] fx3_instruction; - output reg [15:0] fx3_mask_value; - output reg [1:0] fx3_thread_idx; - output reg [3:0] fx3_subcycle; - output reg [15:0] fx3_result_inf; - output reg [15:0] fx3_result_nan; - output reg [15:0] fx3_equal; - output reg [95:0] fx3_ftoi_lshift; - output reg [511:0] fx3_add_significand; - output reg [127:0] fx3_add_exponent; - output reg [15:0] fx3_add_result_sign; - output reg [15:0] fx3_logical_subtract; - output reg [1023:0] fx3_significand_product; - output reg [127:0] fx3_mul_exponent; - output reg [15:0] fx3_mul_underflow; - output reg [15:0] fx3_mul_sign; - wire ftoi; - assign ftoi = fx2_instruction[70-:6] == 6'b011011; - genvar _gv_lane_idx_3; - generate - for (_gv_lane_idx_3 = 0; _gv_lane_idx_3 < defines_NUM_VECTOR_LANES; _gv_lane_idx_3 = _gv_lane_idx_3 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_3; - wire carry_in; - wire [31:0] unnormalized_sum; - wire sum_odd; - wire round_up; - wire round_tie; - wire do_round; - wire _unused; - assign sum_odd = fx2_significand_le[lane_idx * 32] ^ fx2_significand_se[lane_idx * 32]; - assign round_tie = fx2_guard[lane_idx] && !(fx2_round[lane_idx] || fx2_sticky[lane_idx]); - assign round_up = fx2_guard[lane_idx] && (fx2_round[lane_idx] || fx2_sticky[lane_idx]); - assign do_round = round_up || (sum_odd && round_tie); - assign carry_in = fx2_logical_subtract[lane_idx] ^ (do_round && !ftoi); - assign {unnormalized_sum, _unused} = {fx2_significand_le[lane_idx * 32+:32], 1'b1} + {fx2_significand_se[lane_idx * 32+:32] ^ {32 {fx2_logical_subtract[lane_idx]}}, carry_in}; - always @(posedge clk) begin - fx3_result_inf[lane_idx] <= fx2_result_inf[lane_idx]; - fx3_result_nan[lane_idx] <= fx2_result_nan[lane_idx]; - fx3_equal[lane_idx] <= fx2_equal[lane_idx]; - fx3_equal[lane_idx] <= fx2_equal[lane_idx]; - fx3_ftoi_lshift[lane_idx * 6+:6] <= fx2_ftoi_lshift[lane_idx * 6+:6]; - fx3_add_significand[lane_idx * 32+:32] <= unnormalized_sum; - fx3_add_exponent[lane_idx * 8+:8] <= fx2_add_exponent[lane_idx * 8+:8]; - fx3_logical_subtract[lane_idx] <= fx2_logical_subtract[lane_idx]; - fx3_add_result_sign[lane_idx] <= fx2_add_result_sign[lane_idx]; - fx3_significand_product[lane_idx * 64+:64] <= fx2_significand_product[lane_idx * 64+:64]; - fx3_mul_exponent[lane_idx * 8+:8] <= fx2_mul_exponent[lane_idx * 8+:8]; - fx3_mul_underflow[lane_idx] <= fx2_mul_underflow[lane_idx]; - fx3_mul_sign[lane_idx] <= fx2_mul_sign[lane_idx]; - end - end - endgenerate - always @(posedge clk) begin - fx3_instruction <= fx2_instruction; - fx3_mask_value <= fx2_mask_value; - fx3_thread_idx <= fx2_thread_idx; - fx3_subcycle <= fx2_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx3_instruction_valid <= 1'sb0; - else - fx3_instruction_valid <= fx2_instruction_valid; -endmodule -module fp_execute_stage4 ( - clk, - reset, - fx3_mask_value, - fx3_instruction_valid, - fx3_instruction, - fx3_thread_idx, - fx3_subcycle, - fx3_result_inf, - fx3_result_nan, - fx3_equal, - fx3_ftoi_lshift, - fx3_add_significand, - fx3_add_exponent, - fx3_add_result_sign, - fx3_logical_subtract, - fx3_significand_product, - fx3_mul_exponent, - fx3_mul_underflow, - fx3_mul_sign, - fx4_instruction_valid, - fx4_instruction, - fx4_mask_value, - fx4_thread_idx, - fx4_subcycle, - fx4_result_inf, - fx4_result_nan, - fx4_equal, - fx4_add_exponent, - fx4_add_significand, - fx4_add_result_sign, - fx4_logical_subtract, - fx4_norm_shift, - fx4_significand_product, - fx4_mul_exponent, - fx4_mul_underflow, - fx4_mul_sign -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx3_mask_value; - input fx3_instruction_valid; - input wire [141:0] fx3_instruction; - input wire [1:0] fx3_thread_idx; - input wire [3:0] fx3_subcycle; - input [15:0] fx3_result_inf; - input [15:0] fx3_result_nan; - input [15:0] fx3_equal; - input [95:0] fx3_ftoi_lshift; - input wire [511:0] fx3_add_significand; - input [127:0] fx3_add_exponent; - input [15:0] fx3_add_result_sign; - input [15:0] fx3_logical_subtract; - input [1023:0] fx3_significand_product; - input [127:0] fx3_mul_exponent; - input [15:0] fx3_mul_underflow; - input [15:0] fx3_mul_sign; - output reg fx4_instruction_valid; - output reg [141:0] fx4_instruction; - output reg [15:0] fx4_mask_value; - output reg [1:0] fx4_thread_idx; - output reg [3:0] fx4_subcycle; - output reg [15:0] fx4_result_inf; - output reg [15:0] fx4_result_nan; - output reg [15:0] fx4_equal; - output reg [127:0] fx4_add_exponent; - output reg [511:0] fx4_add_significand; - output reg [15:0] fx4_add_result_sign; - output reg [15:0] fx4_logical_subtract; - output reg [95:0] fx4_norm_shift; - output reg [1023:0] fx4_significand_product; - output reg [127:0] fx4_mul_exponent; - output reg [15:0] fx4_mul_underflow; - output reg [15:0] fx4_mul_sign; - wire ftoi; - assign ftoi = fx3_instruction[70-:6] == 6'b011011; - genvar _gv_lane_idx_4; - generate - for (_gv_lane_idx_4 = 0; _gv_lane_idx_4 < defines_NUM_VECTOR_LANES; _gv_lane_idx_4 = _gv_lane_idx_4 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_4; - reg [5:0] leading_zeroes; - always @(*) begin - if (_sv2v_0) - ; - leading_zeroes = 0; - (* full_case, parallel_case *) - casez (fx3_add_significand[lane_idx * 32+:32]) - 32'b1zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 0; - 32'b01zzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 1; - 32'b001zzzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 2; - 32'b0001zzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 3; - 32'b00001zzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 4; - 32'b000001zzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 5; - 32'b0000001zzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 6; - 32'b00000001zzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 7; - 32'b000000001zzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 8; - 32'b0000000001zzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 9; - 32'b00000000001zzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 10; - 32'b000000000001zzzzzzzzzzzzzzzzzzzz: leading_zeroes = 11; - 32'b0000000000001zzzzzzzzzzzzzzzzzzz: leading_zeroes = 12; - 32'b00000000000001zzzzzzzzzzzzzzzzzz: leading_zeroes = 13; - 32'b000000000000001zzzzzzzzzzzzzzzzz: leading_zeroes = 14; - 32'b0000000000000001zzzzzzzzzzzzzzzz: leading_zeroes = 15; - 32'b00000000000000001zzzzzzzzzzzzzzz: leading_zeroes = 16; - 32'b000000000000000001zzzzzzzzzzzzzz: leading_zeroes = 17; - 32'b0000000000000000001zzzzzzzzzzzzz: leading_zeroes = 18; - 32'b00000000000000000001zzzzzzzzzzzz: leading_zeroes = 19; - 32'b000000000000000000001zzzzzzzzzzz: leading_zeroes = 20; - 32'b0000000000000000000001zzzzzzzzzz: leading_zeroes = 21; - 32'b00000000000000000000001zzzzzzzzz: leading_zeroes = 22; - 32'b000000000000000000000001zzzzzzzz: leading_zeroes = 23; - 32'b0000000000000000000000001zzzzzzz: leading_zeroes = 24; - 32'b00000000000000000000000001zzzzzz: leading_zeroes = 25; - 32'b000000000000000000000000001zzzzz: leading_zeroes = 26; - 32'b0000000000000000000000000001zzzz: leading_zeroes = 27; - 32'b00000000000000000000000000001zzz: leading_zeroes = 28; - 32'b000000000000000000000000000001zz: leading_zeroes = 29; - 32'b0000000000000000000000000000001z: leading_zeroes = 30; - 32'b00000000000000000000000000000001: leading_zeroes = 31; - 32'b00000000000000000000000000000000: leading_zeroes = 32; - default: leading_zeroes = 0; - endcase - end - always @(posedge clk) begin - fx4_add_significand[lane_idx * 32+:32] <= fx3_add_significand[lane_idx * 32+:32]; - fx4_norm_shift[lane_idx * 6+:6] <= (ftoi ? fx3_ftoi_lshift[lane_idx * 6+:6] : leading_zeroes); - fx4_add_exponent[lane_idx * 8+:8] <= fx3_add_exponent[lane_idx * 8+:8]; - fx4_add_result_sign[lane_idx] <= fx3_add_result_sign[lane_idx]; - fx4_logical_subtract[lane_idx] <= fx3_logical_subtract[lane_idx]; - fx4_significand_product[lane_idx * 64+:64] <= fx3_significand_product[lane_idx * 64+:64]; - fx4_mul_exponent[lane_idx * 8+:8] <= fx3_mul_exponent[lane_idx * 8+:8]; - fx4_mul_underflow[lane_idx] <= fx3_mul_underflow[lane_idx]; - fx4_mul_sign[lane_idx] <= fx3_mul_sign[lane_idx]; - fx4_result_inf[lane_idx] <= fx3_result_inf[lane_idx]; - fx4_result_nan[lane_idx] <= fx3_result_nan[lane_idx]; - fx4_equal[lane_idx] <= fx3_equal[lane_idx]; - end - end - endgenerate - always @(posedge clk) begin - fx4_instruction <= fx3_instruction; - fx4_mask_value <= fx3_mask_value; - fx4_thread_idx <= fx3_thread_idx; - fx4_subcycle <= fx3_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx4_instruction_valid <= 1'sb0; - else - fx4_instruction_valid <= fx3_instruction_valid; - initial _sv2v_0 = 0; -endmodule -module fp_execute_stage5 ( - clk, - reset, - fx4_mask_value, - fx4_instruction_valid, - fx4_instruction, - fx4_thread_idx, - fx4_subcycle, - fx4_result_inf, - fx4_result_nan, - fx4_equal, - fx4_add_exponent, - fx4_add_significand, - fx4_add_result_sign, - fx4_logical_subtract, - fx4_norm_shift, - fx4_significand_product, - fx4_mul_exponent, - fx4_mul_underflow, - fx4_mul_sign, - fx5_instruction_valid, - fx5_instruction, - fx5_mask_value, - fx5_thread_idx, - fx5_subcycle, - fx5_result -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx4_mask_value; - input fx4_instruction_valid; - input wire [141:0] fx4_instruction; - input wire [1:0] fx4_thread_idx; - input wire [3:0] fx4_subcycle; - input [15:0] fx4_result_inf; - input [15:0] fx4_result_nan; - input [15:0] fx4_equal; - input [127:0] fx4_add_exponent; - input wire [511:0] fx4_add_significand; - input [15:0] fx4_add_result_sign; - input [15:0] fx4_logical_subtract; - input [95:0] fx4_norm_shift; - input [1023:0] fx4_significand_product; - input [127:0] fx4_mul_exponent; - input [15:0] fx4_mul_underflow; - input [15:0] fx4_mul_sign; - output reg fx5_instruction_valid; - output reg [141:0] fx5_instruction; - output reg [15:0] fx5_mask_value; - output reg [1:0] fx5_thread_idx; - output reg [3:0] fx5_subcycle; - output reg [511:0] fx5_result; - wire fmul; - wire imull; - wire imulh; - wire ftoi; - assign fmul = fx4_instruction[70-:6] == 6'b100010; - assign imull = fx4_instruction[70-:6] == 6'b000111; - assign imulh = (fx4_instruction[70-:6] == 6'b001000) || (fx4_instruction[70-:6] == 6'b011111); - assign ftoi = fx4_instruction[70-:6] == 6'b011011; - genvar _gv_lane_idx_5; - localparam defines_FLOAT32_EXP_WIDTH = 8; - localparam defines_FLOAT32_SIG_WIDTH = 23; - function automatic [7:0] sv2v_cast_8; - input reg [7:0] inp; - sv2v_cast_8 = inp; - endfunction - function automatic [22:0] sv2v_cast_23; - input reg [22:0] inp; - sv2v_cast_23 = inp; - endfunction - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - generate - for (_gv_lane_idx_5 = 0; _gv_lane_idx_5 < defines_NUM_VECTOR_LANES; _gv_lane_idx_5 = _gv_lane_idx_5 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_5; - wire [22:0] add_result_significand; - wire [7:0] add_result_exponent; - wire [7:0] adjusted_add_exponent; - wire [31:0] shifted_significand; - wire add_subnormal; - reg [31:0] add_result; - wire add_round; - wire add_overflow; - wire mul_normalize_shift; - wire [22:0] mul_normalized_significand; - wire [22:0] mul_rounded_significand; - reg [31:0] fmul_result; - reg [7:0] mul_exponent; - wire mul_guard; - wire mul_round; - wire [21:0] mul_sticky_bits; - wire mul_sticky; - wire mul_round_tie; - wire mul_round_up; - wire mul_do_round; - reg compare_result; - wire sum_zero; - wire mul_hidden_bit; - wire mul_round_overflow; - assign adjusted_add_exponent = (fx4_add_exponent[lane_idx * 8+:8] - sv2v_cast_8(fx4_norm_shift[lane_idx * 6+:6])) + 8'sd8; - assign add_subnormal = (fx4_add_exponent[lane_idx * 8+:8] == 0) || (fx4_add_significand[lane_idx * 32+:32] == 0); - assign shifted_significand = fx4_add_significand[lane_idx * 32+:32] << fx4_norm_shift[lane_idx * 6+:6]; - assign add_round = (shifted_significand[7] && shifted_significand[8]) && !fx4_logical_subtract[lane_idx]; - assign add_result_significand = (add_subnormal ? fx4_add_significand[(lane_idx * 32) + 22-:23] : shifted_significand[30:8] + sv2v_cast_23(add_round)); - assign add_result_exponent = (add_subnormal ? {8 {1'sb0}} : adjusted_add_exponent); - assign add_overflow = (add_result_exponent == 8'hff) && !fx4_result_nan[lane_idx]; - always @(*) begin - if (_sv2v_0) - ; - if (fx4_result_inf[lane_idx] || add_overflow) - add_result = {fx4_add_result_sign[lane_idx], 31'h7f800000}; - else if (fx4_result_nan[lane_idx]) - add_result = 32'h7fffffff; - else if ((add_result_significand == 0) && add_subnormal) - add_result = 0; - else - add_result = {fx4_add_result_sign[lane_idx], add_result_exponent, add_result_significand}; - end - assign sum_zero = add_subnormal && (add_result_significand == 0); - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (fx4_instruction[70-:6]) - 6'b101100: compare_result = (!fx4_add_result_sign[lane_idx] && !fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b101101: compare_result = (!fx4_add_result_sign[lane_idx] || fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b101110: compare_result = (fx4_add_result_sign[lane_idx] && !fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b101111: compare_result = (fx4_add_result_sign[lane_idx] || fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b110000: compare_result = fx4_equal[lane_idx] && !fx4_result_nan[lane_idx]; - 6'b110001: compare_result = !fx4_equal[lane_idx] || fx4_result_nan[lane_idx]; - default: compare_result = 0; - endcase - end - assign mul_normalize_shift = !fx4_significand_product[(lane_idx * 64) + 47]; - assign {mul_normalized_significand, mul_guard, mul_round, mul_sticky_bits} = (mul_normalize_shift ? {fx4_significand_product[(lane_idx * 64) + 45-:46], 1'b0} : fx4_significand_product[(lane_idx * 64) + 46-:47]); - assign mul_sticky = |mul_sticky_bits; - assign mul_round_tie = mul_guard && !(mul_round || mul_sticky); - assign mul_round_up = mul_guard && (mul_round || mul_sticky); - assign mul_do_round = mul_round_up || (mul_round_tie && mul_normalized_significand[0]); - assign mul_rounded_significand = mul_normalized_significand + sv2v_cast_23(mul_do_round); - assign mul_hidden_bit = (mul_normalize_shift ? fx4_significand_product[(lane_idx * 64) + 46] : 1'b1); - assign mul_round_overflow = mul_do_round && (mul_rounded_significand == 0); - always @(*) begin - if (_sv2v_0) - ; - if (!mul_hidden_bit) - mul_exponent = 0; - else if (mul_normalize_shift && !mul_round_overflow) - mul_exponent = fx4_mul_exponent[lane_idx * 8+:8]; - else - mul_exponent = fx4_mul_exponent[lane_idx * 8+:8] + 8'sd1; - end - always @(*) begin - if (_sv2v_0) - ; - if (fx4_result_inf[lane_idx]) - fmul_result = {fx4_mul_sign[lane_idx], 31'h7f800000}; - else if (fx4_result_nan[lane_idx]) - fmul_result = 32'h7fffffff; - else - fmul_result = {fx4_mul_sign[lane_idx], mul_exponent, mul_rounded_significand}; - end - always @(posedge clk) - if (ftoi) begin - if (fx4_result_nan[lane_idx]) - fx5_result[lane_idx * 32+:32] <= 32'h80000000; - else - fx5_result[lane_idx * 32+:32] <= shifted_significand; - end - else if (fx4_instruction[13]) - fx5_result[lane_idx * 32+:32] <= sv2v_cast_32(compare_result); - else if (imull) - fx5_result[lane_idx * 32+:32] <= fx4_significand_product[(lane_idx * 64) + 31-:32]; - else if (imulh) - fx5_result[lane_idx * 32+:32] <= fx4_significand_product[(lane_idx * 64) + 63-:32]; - else if (fmul) - fx5_result[lane_idx * 32+:32] <= (fx4_mul_underflow[lane_idx] ? 32'h00000000 : fmul_result); - else - fx5_result[lane_idx * 32+:32] <= add_result; - end - endgenerate - always @(posedge clk) begin - fx5_instruction <= fx4_instruction; - fx5_mask_value <= fx4_mask_value; - fx5_thread_idx <= fx4_thread_idx; - fx5_subcycle <= fx4_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx5_instruction_valid <= 1'sb0; - else - fx5_instruction_valid <= fx4_instruction_valid; - initial _sv2v_0 = 0; -endmodule -module idx_to_oh ( - one_hot, - index -); - reg _sv2v_0; - parameter NUM_SIGNALS = 4; - parameter DIRECTION = "LSB0"; - parameter INDEX_WIDTH = $clog2(NUM_SIGNALS); - output reg [NUM_SIGNALS - 1:0] one_hot; - input [INDEX_WIDTH - 1:0] index; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(*) begin : convert - if (_sv2v_0) - ; - one_hot = 0; - if (DIRECTION == "LSB0") - one_hot[index] = 1'b1; - else - one_hot[(NUM_SIGNALS - sv2v_cast_32(index)) - 1] = 1'b1; - end - initial _sv2v_0 = 0; -endmodule -module ifetch_data_stage ( - clk, - reset, - ift_instruction_requested, - ift_pc_paddr, - ift_pc_vaddr, - ift_thread_idx, - ift_tlb_hit, - ift_tlb_present, - ift_tlb_executable, - ift_tlb_supervisor, - ift_tag, - ift_valid, - ifd_update_lru_en, - ifd_update_lru_way, - ifd_near_miss, - l2i_idata_update_en, - l2i_idata_update_way, - l2i_idata_update_set, - l2i_idata_update_data, - l2i_itag_update_en, - l2i_itag_update_set, - l2i_itag_update_tag, - ifd_cache_miss, - ifd_cache_miss_paddr, - ifd_cache_miss_thread_idx, - cr_supervisor_en, - ifd_instruction, - ifd_instruction_valid, - ifd_pc, - ifd_thread_idx, - ifd_alignment_fault, - ifd_tlb_miss, - ifd_supervisor_fault, - ifd_page_fault, - ifd_executable_fault, - ifd_inst_injected, - wb_rollback_en, - wb_rollback_thread_idx, - ifd_perf_icache_hit, - ifd_perf_icache_miss, - ifd_perf_itlb_miss, - core_selected_debug, - ocd_halt, - ocd_inject_inst, - ocd_inject_en, - ocd_thread -); - input clk; - input reset; - input ift_instruction_requested; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_ICACHE_TAG_BITS = 20; - input wire [31:0] ift_pc_paddr; - input wire [31:0] ift_pc_vaddr; - input wire [1:0] ift_thread_idx; - input ift_tlb_hit; - input ift_tlb_present; - input ift_tlb_executable; - input ift_tlb_supervisor; - input wire [79:0] ift_tag; - input [0:3] ift_valid; - output wire ifd_update_lru_en; - output wire [1:0] ifd_update_lru_way; - output wire ifd_near_miss; - input l2i_idata_update_en; - input wire [1:0] l2i_idata_update_way; - input wire [5:0] l2i_idata_update_set; - localparam defines_CACHE_LINE_BITS = 512; - input wire [511:0] l2i_idata_update_data; - input [3:0] l2i_itag_update_en; - input wire [5:0] l2i_itag_update_set; - input wire [19:0] l2i_itag_update_tag; - output wire ifd_cache_miss; - output wire [25:0] ifd_cache_miss_paddr; - output wire [1:0] ifd_cache_miss_thread_idx; - input wire [0:3] cr_supervisor_en; - output wire [31:0] ifd_instruction; - output reg ifd_instruction_valid; - output reg [31:0] ifd_pc; - output reg [1:0] ifd_thread_idx; - output reg ifd_alignment_fault; - output reg ifd_tlb_miss; - output reg ifd_supervisor_fault; - output reg ifd_page_fault; - output reg ifd_executable_fault; - output reg ifd_inst_injected; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - output reg ifd_perf_icache_hit; - output reg ifd_perf_icache_miss; - output reg ifd_perf_itlb_miss; - input core_selected_debug; - input ocd_halt; - input wire [31:0] ocd_inject_inst; - input wire ocd_inject_en; - input wire [1:0] ocd_thread; - wire cache_hit; - wire [3:0] way_hit_oh; - wire [1:0] way_hit_idx; - wire [511:0] fetched_cache_line; - wire [31:0] fetched_word; - localparam defines_CACHE_LINE_WORDS = 16; - wire [3:0] cache_lane_idx; - wire alignment_fault; - wire squash_instruction; - reg ocd_halt_latched; - assign squash_instruction = wb_rollback_en && (wb_rollback_thread_idx == ift_thread_idx); - genvar _gv_way_idx_3; - generate - for (_gv_way_idx_3 = 0; _gv_way_idx_3 < 4; _gv_way_idx_3 = _gv_way_idx_3 + 1) begin : hit_check_gen - localparam way_idx = _gv_way_idx_3; - assign way_hit_oh[way_idx] = (ift_pc_paddr[31-:20] == ift_tag[(3 - way_idx) * defines_ICACHE_TAG_BITS+:defines_ICACHE_TAG_BITS]) && ift_valid[way_idx]; - end - endgenerate - assign cache_hit = |way_hit_oh && ift_tlb_hit; - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_hit_way( - .one_hot(way_hit_oh), - .index(way_hit_idx) - ); - assign ifd_near_miss = ((((!cache_hit && ift_tlb_hit) && ift_instruction_requested) && |l2i_itag_update_en) && (l2i_itag_update_set == ift_pc_paddr[11-:6])) && (l2i_itag_update_tag == ift_pc_paddr[31-:20]); - assign ifd_cache_miss = (((!cache_hit && ift_tlb_hit) && ift_instruction_requested) && !ifd_near_miss) && !squash_instruction; - assign ifd_cache_miss_paddr = {ift_pc_paddr[31-:20], ift_pc_paddr[11-:6]}; - assign ifd_cache_miss_thread_idx = ift_thread_idx; - assign alignment_fault = ift_pc_paddr[1:0] != 0; - fakeram_1r1w_512x256 #( - .DATA_WIDTH(defines_CACHE_LINE_BITS), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) sram_l1i_data( - .read_en(cache_hit && ift_instruction_requested), - .read_addr({way_hit_idx, ift_pc_paddr[11-:6]}), - .read_data(fetched_cache_line), - .write_en(l2i_idata_update_en), - .write_addr({l2i_idata_update_way, l2i_idata_update_set}), - .write_data(l2i_idata_update_data), - .* - ); - assign cache_lane_idx = ~ifd_pc[5:2]; - assign fetched_word = fetched_cache_line[32 * cache_lane_idx+:32]; - assign ifd_instruction = (ocd_halt_latched ? ocd_inject_inst : {fetched_word[7:0], fetched_word[15:8], fetched_word[23:16], fetched_word[31:24]}); - assign ifd_update_lru_en = cache_hit && ift_instruction_requested; - assign ifd_update_lru_way = way_hit_idx; - always @(posedge clk) begin - ifd_pc <= ift_pc_vaddr; - ifd_thread_idx <= (ocd_halt ? ocd_thread : ift_thread_idx); - end - always @(posedge clk or posedge reset) - if (reset) begin - ifd_alignment_fault <= 1'sb0; - ifd_executable_fault <= 1'sb0; - ifd_inst_injected <= 1'sb0; - ifd_instruction_valid <= 1'sb0; - ifd_page_fault <= 1'sb0; - ifd_perf_icache_hit <= 1'sb0; - ifd_perf_icache_miss <= 1'sb0; - ifd_perf_itlb_miss <= 1'sb0; - ifd_supervisor_fault <= 1'sb0; - ifd_tlb_miss <= 1'sb0; - ocd_halt_latched <= 1'sb0; - end - else begin - ocd_halt_latched <= ocd_halt; - if (ocd_halt) begin - ifd_instruction_valid <= ocd_inject_en && core_selected_debug; - ifd_inst_injected <= 1; - ifd_alignment_fault <= 0; - ifd_supervisor_fault <= 0; - ifd_tlb_miss <= 0; - ifd_page_fault <= 0; - ifd_executable_fault <= 0; - end - else begin - ifd_instruction_valid <= ((ift_instruction_requested && !squash_instruction) && cache_hit) && ift_tlb_hit; - ifd_inst_injected <= 0; - ifd_alignment_fault <= (ift_instruction_requested && !squash_instruction) && alignment_fault; - ifd_supervisor_fault <= ((((ift_instruction_requested && !squash_instruction) && ift_tlb_hit) && ift_tlb_present) && ift_tlb_supervisor) && !cr_supervisor_en[ift_thread_idx]; - ifd_tlb_miss <= (ift_instruction_requested && !squash_instruction) && !ift_tlb_hit; - ifd_page_fault <= ((ift_instruction_requested && !squash_instruction) && ift_tlb_hit) && !ift_tlb_present; - ifd_executable_fault <= (((ift_instruction_requested && !squash_instruction) && ift_tlb_hit) && ift_tlb_present) && !ift_tlb_executable; - ifd_perf_icache_hit <= cache_hit && ift_instruction_requested; - ifd_perf_icache_miss <= ((!cache_hit && ift_tlb_hit) && ift_instruction_requested) && !squash_instruction; - ifd_perf_itlb_miss <= ift_instruction_requested && !ift_tlb_hit; - end - end -endmodule -module ifetch_tag_stage ( - clk, - reset, - ifd_update_lru_en, - ifd_update_lru_way, - ifd_cache_miss, - ifd_near_miss, - ifd_cache_miss_thread_idx, - ift_instruction_requested, - ift_pc_paddr, - ift_pc_vaddr, - ift_thread_idx, - ift_tlb_hit, - ift_tlb_present, - ift_tlb_executable, - ift_tlb_supervisor, - ift_tag, - ift_valid, - l2i_icache_lru_fill_en, - l2i_icache_lru_fill_set, - l2i_itag_update_en, - l2i_itag_update_set, - l2i_itag_update_tag, - l2i_itag_update_valid, - l2i_icache_wake_bitmap, - ift_fill_lru, - cr_mmu_en, - cr_current_asid, - dt_invalidate_tlb_en, - dt_invalidate_tlb_all_en, - dt_update_itlb_asid, - dt_update_itlb_vpage_idx, - dt_update_itlb_en, - dt_update_itlb_supervisor, - dt_update_itlb_global, - dt_update_itlb_present, - dt_update_itlb_executable, - dt_update_itlb_ppage_idx, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pc, - ts_fetch_en, - ocd_halt, - ocd_thread -); - reg _sv2v_0; - parameter RESET_PC = 0; - input clk; - input reset; - input ifd_update_lru_en; - input wire [1:0] ifd_update_lru_way; - input ifd_cache_miss; - input ifd_near_miss; - input wire [1:0] ifd_cache_miss_thread_idx; - output reg ift_instruction_requested; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_ICACHE_TAG_BITS = 20; - output wire [31:0] ift_pc_paddr; - output wire [31:0] ift_pc_vaddr; - output reg [1:0] ift_thread_idx; - output reg ift_tlb_hit; - output reg ift_tlb_present; - output reg ift_tlb_executable; - output reg ift_tlb_supervisor; - output wire [79:0] ift_tag; - output reg [0:3] ift_valid; - input l2i_icache_lru_fill_en; - input wire [5:0] l2i_icache_lru_fill_set; - input [3:0] l2i_itag_update_en; - input wire [5:0] l2i_itag_update_set; - input wire [19:0] l2i_itag_update_tag; - input l2i_itag_update_valid; - input wire [3:0] l2i_icache_wake_bitmap; - output wire [1:0] ift_fill_lru; - input [0:3] cr_mmu_en; - localparam defines_ASID_WIDTH = 8; - input [31:0] cr_current_asid; - input dt_invalidate_tlb_en; - input dt_invalidate_tlb_all_en; - input [7:0] dt_update_itlb_asid; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - input wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_vpage_idx; - input dt_update_itlb_en; - input dt_update_itlb_supervisor; - input dt_update_itlb_global; - input dt_update_itlb_present; - input dt_update_itlb_executable; - input wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_ppage_idx; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wire [31:0] wb_rollback_pc; - input wire [3:0] ts_fetch_en; - input ocd_halt; - input wire [1:0] ocd_thread; - reg [31:0] next_program_counter [0:3]; - wire [1:0] selected_thread_idx; - reg [31:0] last_selected_pc; - wire [31:0] pc_to_fetch; - wire [3:0] can_fetch_thread_bitmap; - wire [3:0] selected_thread_oh; - reg [3:0] last_selected_thread_oh; - reg [3:0] icache_wait_threads; - wire [3:0] icache_wait_threads_nxt; - wire [3:0] cache_miss_thread_oh; - wire [3:0] thread_sleep_mask_oh; - wire cache_fetch_en; - wire [defines_PAGE_NUM_BITS - 1:0] tlb_ppage_idx; - reg [defines_PAGE_NUM_BITS - 1:0] ppage_idx; - wire tlb_hit; - wire tlb_supervisor; - wire tlb_present; - wire tlb_executable; - reg [defines_PAGE_NUM_BITS - 1:0] request_vpage_idx; - reg [7:0] request_asid; - assign can_fetch_thread_bitmap = ts_fetch_en & ~icache_wait_threads; - assign cache_fetch_en = (((|can_fetch_thread_bitmap && !dt_update_itlb_en) && !dt_invalidate_tlb_en) && !dt_invalidate_tlb_all_en) && !ocd_halt; - rr_arbiter #(.NUM_REQUESTERS(4)) thread_select_arbiter( - .request(can_fetch_thread_bitmap), - .update_lru(cache_fetch_en), - .grant_oh(selected_thread_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_selected_thread( - .one_hot(selected_thread_oh), - .index(selected_thread_idx) - ); - genvar _gv_thread_idx_3; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_3 = 0; _gv_thread_idx_3 < 4; _gv_thread_idx_3 = _gv_thread_idx_3 + 1) begin : pc_logic_gen - localparam thread_idx = _gv_thread_idx_3; - always @(posedge clk or posedge reset) - if (reset) - next_program_counter[thread_idx] <= RESET_PC; - else if (wb_rollback_en && (wb_rollback_thread_idx == sv2v_cast_2(thread_idx))) - next_program_counter[thread_idx] <= wb_rollback_pc; - else if ((ifd_cache_miss || ifd_near_miss) && last_selected_thread_oh[thread_idx]) - next_program_counter[thread_idx] <= next_program_counter[thread_idx] - 4; - else if (selected_thread_oh[thread_idx] && cache_fetch_en) - next_program_counter[thread_idx] <= next_program_counter[thread_idx] + 4; - end - endgenerate - assign pc_to_fetch = next_program_counter[(ocd_halt ? ocd_thread : selected_thread_idx)]; - genvar _gv_way_idx_4; - generate - for (_gv_way_idx_4 = 0; _gv_way_idx_4 < 4; _gv_way_idx_4 = _gv_way_idx_4 + 1) begin : way_tag_gen - localparam way_idx = _gv_way_idx_4; - reg line_valid [0:63]; - fakeram_1r1w_20x64 #( - .DATA_WIDTH(defines_ICACHE_TAG_BITS), - .SIZE(64), - .READ_DURING_WRITE("NEW_DATA") - ) sram_tags( - .read_en(cache_fetch_en), - .read_addr(pc_to_fetch[11-:6]), - .read_data(ift_tag[(3 - way_idx) * defines_ICACHE_TAG_BITS+:defines_ICACHE_TAG_BITS]), - .write_en(l2i_itag_update_en[way_idx]), - .write_addr(l2i_itag_update_set), - .write_data(l2i_itag_update_tag), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < 64; set_idx = set_idx + 1) - line_valid[set_idx] <= 0; - end - else if (l2i_itag_update_en[way_idx]) - line_valid[l2i_itag_update_set] <= l2i_itag_update_valid; - always @(posedge clk) - if (l2i_itag_update_en[way_idx] && (l2i_itag_update_set == pc_to_fetch[11-:6])) - ift_valid[way_idx] <= l2i_itag_update_valid; - else - ift_valid[way_idx] <= line_valid[pc_to_fetch[11-:6]]; - end - endgenerate - always @(*) begin - if (_sv2v_0) - ; - if (cache_fetch_en) begin - request_vpage_idx = pc_to_fetch[31-:defines_PAGE_NUM_BITS]; - request_asid = cr_current_asid[(3 - selected_thread_idx) * 8+:8]; - end - else begin - request_vpage_idx = dt_update_itlb_vpage_idx; - request_asid = dt_update_itlb_asid; - end - end - tlb #( - .NUM_ENTRIES(64), - .NUM_WAYS(4) - ) itlb( - .lookup_en(cache_fetch_en), - .update_en(dt_update_itlb_en), - .update_present(dt_update_itlb_present), - .update_exe_writable(dt_update_itlb_executable), - .update_supervisor(dt_update_itlb_supervisor), - .update_global(dt_update_itlb_global), - .invalidate_en(dt_invalidate_tlb_en), - .invalidate_all_en(dt_invalidate_tlb_all_en), - .update_ppage_idx(dt_update_itlb_ppage_idx), - .lookup_ppage_idx(tlb_ppage_idx), - .lookup_hit(tlb_hit), - .lookup_exe_writable(tlb_executable), - .lookup_present(tlb_present), - .lookup_supervisor(tlb_supervisor), - .clk(clk), - .reset(reset), - .request_vpage_idx(request_vpage_idx), - .request_asid(request_asid) - ); - always @(*) begin - if (_sv2v_0) - ; - if (cr_mmu_en[ift_thread_idx]) begin - ift_tlb_hit = tlb_hit; - ift_tlb_present = tlb_present; - ift_tlb_executable = tlb_executable; - ift_tlb_supervisor = tlb_supervisor; - ppage_idx = tlb_ppage_idx; - end - else begin - ift_tlb_hit = 1; - ift_tlb_present = 1; - ift_tlb_executable = 1; - ift_tlb_supervisor = 0; - ppage_idx = last_selected_pc[31-:defines_PAGE_NUM_BITS]; - end - end - cache_lru #( - .NUM_WAYS(4), - .NUM_SETS(64) - ) cache_lru( - .fill_en(l2i_icache_lru_fill_en), - .fill_set(l2i_icache_lru_fill_set), - .fill_way(ift_fill_lru), - .access_en(cache_fetch_en), - .access_set(pc_to_fetch[11-:6]), - .update_en(ifd_update_lru_en), - .update_way(ifd_update_lru_way), - .clk(clk), - .reset(reset) - ); - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_miss_thread( - .one_hot(cache_miss_thread_oh), - .index(ifd_cache_miss_thread_idx) - ); - assign thread_sleep_mask_oh = cache_miss_thread_oh & {4 {ifd_cache_miss}}; - assign icache_wait_threads_nxt = (icache_wait_threads | thread_sleep_mask_oh) & ~l2i_icache_wake_bitmap; - always @(posedge clk or posedge reset) - if (reset) begin - icache_wait_threads <= 1'sb0; - ift_instruction_requested <= 1'sb0; - end - else begin - icache_wait_threads <= icache_wait_threads_nxt; - ift_instruction_requested <= (cache_fetch_en && !((ifd_cache_miss || ifd_near_miss) && (ifd_cache_miss_thread_idx == selected_thread_idx))) && !(wb_rollback_en && (wb_rollback_thread_idx == selected_thread_idx)); - end - always @(posedge clk) begin - last_selected_pc <= pc_to_fetch; - ift_thread_idx <= selected_thread_idx; - last_selected_thread_oh <= selected_thread_oh; - end - assign ift_pc_paddr = {ppage_idx, last_selected_pc[31 - defines_PAGE_NUM_BITS:0]}; - assign ift_pc_vaddr = last_selected_pc; - initial _sv2v_0 = 0; -endmodule -module instruction_decode_stage ( - clk, - reset, - ifd_instruction_valid, - ifd_instruction, - ifd_inst_injected, - ifd_pc, - ifd_thread_idx, - ifd_alignment_fault, - ifd_supervisor_fault, - ifd_page_fault, - ifd_executable_fault, - ifd_tlb_miss, - dd_load_sync_pending, - sq_store_sync_pending, - id_instruction, - id_instruction_valid, - id_thread_idx, - ior_pending, - cr_interrupt_en, - cr_interrupt_pending, - ocd_halt, - wb_rollback_en, - wb_rollback_thread_idx -); - reg _sv2v_0; - input clk; - input reset; - input ifd_instruction_valid; - input wire [31:0] ifd_instruction; - input ifd_inst_injected; - input wire [31:0] ifd_pc; - input wire [1:0] ifd_thread_idx; - input ifd_alignment_fault; - input ifd_supervisor_fault; - input ifd_page_fault; - input ifd_executable_fault; - input ifd_tlb_miss; - input wire [3:0] dd_load_sync_pending; - input wire [3:0] sq_store_sync_pending; - localparam defines_NUM_VECTOR_LANES = 16; - output reg [141:0] id_instruction; - output reg id_instruction_valid; - output reg [1:0] id_thread_idx; - input wire [3:0] ior_pending; - input wire [3:0] cr_interrupt_en; - input wire [3:0] cr_interrupt_pending; - input ocd_halt; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - localparam T = 1'b1; - localparam F = 1'b0; - reg [20:0] dlut_out; - reg [141:0] decoded_instr_nxt; - wire nop; - wire fmt_r; - wire fmt_i; - wire fmt_m; - wire getlane; - wire compare; - reg [5:0] alu_op; - wire [3:0] memory_access_type; - reg [4:0] scalar_sel2; - wire has_trap; - wire syscall; - wire breakpoint; - wire raise_interrupt; - wire [3:0] masked_interrupt_flags; - wire unary_arith; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - casez (ifd_instruction[31:25]) - 7'b110000z: dlut_out = {F, F, T, 8'h11, F, F, F, F, 4'h2, F, F}; - 7'b110001z: dlut_out = {F, T, T, 8'h11, T, F, F, T, 4'h2, F, F}; - 7'b110010z: dlut_out = {F, T, T, 8'h09, T, F, F, T, 4'h0, F, F}; - 7'b110100z: dlut_out = {F, T, T, 8'h08, T, T, F, T, 4'h6, F, F}; - 7'b110101z: dlut_out = {F, T, T, 8'h12, T, T, F, T, 4'h5, F, F}; - 7'b000zzzz: dlut_out = {F, F, T, 8'h50, F, F, F, F, 4'ha, F, F}; - 7'b001zzzz: dlut_out = {F, T, T, 8'h50, T, F, F, T, 4'ha, F, F}; - 7'b010zzzz: dlut_out = {F, F, T, 8'hf0, F, F, F, F, 4'ha, F, F}; - 7'b011zzzz: dlut_out = {F, T, T, 8'h32, T, F, F, T, 4'h9, F, F}; - 7'b1000000: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000001: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000010: dlut_out = {F, F, F, 8'h93, T, F, T, F, 4'ha, F, F}; - 7'b1000011: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000100: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000101: dlut_out = {F, F, T, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000110: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000111: dlut_out = {F, F, F, 8'h90, F, T, T, F, 4'ha, T, F}; - 7'b1001000: dlut_out = {F, F, F, 8'h72, F, T, T, F, 4'h9, T, F}; - 7'b1001101: dlut_out = {F, F, F, 8'h90, T, T, T, T, 4'ha, T, F}; - 7'b1001110: dlut_out = {F, F, F, 8'h72, T, T, T, T, 4'h9, T, F}; - 7'b1010000: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010001: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010010: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010011: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010100: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010101: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010110: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010111: dlut_out = {F, T, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1011000: dlut_out = {F, T, T, 8'h72, T, F, F, F, 4'h9, F, F}; - 7'b1011101: dlut_out = {F, T, T, 8'h90, T, T, F, T, 4'ha, F, F}; - 7'b1011110: dlut_out = {F, T, T, 8'h72, T, T, F, T, 4'h9, F, F}; - 7'b1110000: dlut_out = {F, F, F, 8'h73, F, F, F, F, 4'ha, F, F}; - 7'b1110001: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110010: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110011: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110100: dlut_out = {F, F, F, 8'h60, F, F, F, F, 4'ha, F, F}; - 7'b1110101: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110110: dlut_out = {F, F, F, 8'h60, F, F, F, F, 4'ha, F, F}; - 7'b1110111: dlut_out = {F, F, F, 8'h73, F, F, F, F, 4'ha, F, F}; - 7'b1111000: dlut_out = {F, F, F, 8'hb0, F, F, F, F, 4'ha, F, F}; - 7'b1111001: dlut_out = {F, F, F, 8'hb0, F, F, F, F, 4'ha, F, F}; - 7'b1111010: dlut_out = {F, F, F, 8'hb0, F, F, F, F, 4'ha, F, F}; - 7'b1111011: dlut_out = {F, F, F, 8'hc0, F, F, F, F, 4'ha, F, F}; - 7'b1111100: dlut_out = {F, F, T, 8'hc0, F, F, F, F, 4'h2, F, T}; - 7'b1111110: dlut_out = {F, F, T, 8'hb0, F, F, F, F, 4'h2, F, T}; - 7'b1111111: dlut_out = {F, F, T, 8'hb0, F, F, F, F, 4'h2, F, F}; - default: dlut_out = {T, F, F, 8'h00, F, F, F, F, 4'ha, F, F}; - endcase - end - assign fmt_r = ifd_instruction[31:29] == 3'b110; - assign fmt_i = ifd_instruction[31] == 1'b0; - assign fmt_m = ifd_instruction[31:30] == 2'b10; - assign getlane = (fmt_r || fmt_i) && (alu_op == 6'b011010); - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - assign syscall = fmt_i && (sv2v_cast_6(ifd_instruction[28:24]) == 6'b000010); - assign breakpoint = fmt_r && (ifd_instruction[25:20] == 6'b111110); - localparam defines_INSTRUCTION_NOP = 32'd0; - assign nop = ifd_instruction == defines_INSTRUCTION_NOP; - assign has_trap = (((((ifd_instruction_valid && (((dlut_out[20] || syscall) || breakpoint) || raise_interrupt)) || ifd_alignment_fault) || ifd_tlb_miss) || ifd_supervisor_fault) || ifd_page_fault) || ifd_executable_fault; - always @(*) begin - if (_sv2v_0) - ; - if (raise_interrupt) - decoded_instr_nxt[107-:6] = 6'h03; - else if (ifd_tlb_miss) - decoded_instr_nxt[107-:6] = 6'h07; - else if (ifd_page_fault) - decoded_instr_nxt[107-:6] = 6'h06; - else if (ifd_supervisor_fault) - decoded_instr_nxt[107-:6] = 6'h09; - else if (ifd_alignment_fault) - decoded_instr_nxt[107-:6] = 6'h05; - else if (ifd_executable_fault) - decoded_instr_nxt[107-:6] = 6'h0a; - else if (dlut_out[20]) - decoded_instr_nxt[107-:6] = 6'h01; - else if (syscall) - decoded_instr_nxt[107-:6] = 6'h04; - else if (breakpoint) - decoded_instr_nxt[107-:6] = 6'h0b; - else - decoded_instr_nxt[107-:6] = 6'h00; - end - wire [1:1] sv2v_tmp_B134F; - assign sv2v_tmp_B134F = ifd_inst_injected; - always @(*) decoded_instr_nxt[109] = sv2v_tmp_B134F; - assign masked_interrupt_flags = (((cr_interrupt_pending & cr_interrupt_en) & ~ior_pending) & ~dd_load_sync_pending) & ~sq_store_sync_pending; - assign raise_interrupt = masked_interrupt_flags[ifd_thread_idx] && !ocd_halt; - wire [1:1] sv2v_tmp_C4036; - assign sv2v_tmp_C4036 = has_trap; - always @(*) decoded_instr_nxt[108] = sv2v_tmp_C4036; - assign unary_arith = (fmt_r && ((((((((alu_op == 6'b001100) || (alu_op == 6'b001110)) || (alu_op == 6'b001111)) || (alu_op == 6'b011011)) || (alu_op == 6'b011100)) || (alu_op == 6'b011101)) || (alu_op == 6'b011110)) || (alu_op == 6'b101010))) && (dlut_out[3-:2] != 2'd0); - wire [1:1] sv2v_tmp_B589F; - assign sv2v_tmp_B589F = (((dlut_out[14-:2] != 2'd0) && !nop) && !has_trap) && !unary_arith; - always @(*) decoded_instr_nxt[101] = sv2v_tmp_B589F; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dlut_out[14-:2]) - 2'd1: decoded_instr_nxt[100-:5] = ifd_instruction[14:10]; - default: decoded_instr_nxt[100-:5] = ifd_instruction[4:0]; - endcase - end - wire [1:1] sv2v_tmp_D8F29; - assign sv2v_tmp_D8F29 = ((dlut_out[12-:3] != 3'd0) && !nop) && !has_trap; - always @(*) decoded_instr_nxt[95] = sv2v_tmp_D8F29; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dlut_out[12-:3]) - 3'd2: scalar_sel2 = ifd_instruction[14:10]; - 3'd1: scalar_sel2 = ifd_instruction[19:15]; - 3'd3: scalar_sel2 = ifd_instruction[9:5]; - default: scalar_sel2 = 0; - endcase - end - wire [5:1] sv2v_tmp_1FBF8; - assign sv2v_tmp_1FBF8 = scalar_sel2; - always @(*) decoded_instr_nxt[94-:5] = sv2v_tmp_1FBF8; - wire [1:1] sv2v_tmp_A0273; - assign sv2v_tmp_A0273 = (dlut_out[9] && !nop) && !has_trap; - always @(*) decoded_instr_nxt[89] = sv2v_tmp_A0273; - wire [5:1] sv2v_tmp_1F848; - assign sv2v_tmp_1F848 = ifd_instruction[4:0]; - always @(*) decoded_instr_nxt[88-:5] = sv2v_tmp_1F848; - wire [1:1] sv2v_tmp_1AA29; - assign sv2v_tmp_1AA29 = (dlut_out[8] && !nop) && !has_trap; - always @(*) decoded_instr_nxt[83] = sv2v_tmp_1AA29; - always @(*) begin - if (_sv2v_0) - ; - if (dlut_out[7]) - decoded_instr_nxt[82-:5] = ifd_instruction[9:5]; - else - decoded_instr_nxt[82-:5] = ifd_instruction[19:15]; - end - wire [1:1] sv2v_tmp_EBF04; - assign sv2v_tmp_EBF04 = (dlut_out[18] && !nop) && !has_trap; - always @(*) decoded_instr_nxt[77] = sv2v_tmp_EBF04; - wire [1:1] sv2v_tmp_C4837; - assign sv2v_tmp_C4837 = (dlut_out[19] && !compare) && !getlane; - always @(*) decoded_instr_nxt[76] = sv2v_tmp_C4837; - localparam defines_REG_RA = 5'd31; - wire [5:1] sv2v_tmp_245AC; - assign sv2v_tmp_245AC = (dlut_out[0] ? defines_REG_RA : ifd_instruction[9:5]); - always @(*) decoded_instr_nxt[75-:5] = sv2v_tmp_245AC; - wire [1:1] sv2v_tmp_E98EC; - assign sv2v_tmp_E98EC = dlut_out[0]; - always @(*) decoded_instr_nxt[22] = sv2v_tmp_E98EC; - always @(*) begin - if (_sv2v_0) - ; - if (fmt_i) - alu_op = sv2v_cast_6({1'b0, ifd_instruction[28:24]}); - else if (dlut_out[0]) - alu_op = 6'b001111; - else - alu_op = ifd_instruction[25:20]; - end - wire [6:1] sv2v_tmp_78B01; - assign sv2v_tmp_78B01 = alu_op; - always @(*) decoded_instr_nxt[70-:6] = sv2v_tmp_78B01; - wire [2:1] sv2v_tmp_990C6; - assign sv2v_tmp_990C6 = dlut_out[3-:2]; - always @(*) decoded_instr_nxt[64-:2] = sv2v_tmp_990C6; - wire [1:1] sv2v_tmp_C2D78; - assign sv2v_tmp_C2D78 = dlut_out[1]; - always @(*) decoded_instr_nxt[59] = sv2v_tmp_C2D78; - always @(*) begin - if (_sv2v_0) - ; - if (dlut_out[6]) - decoded_instr_nxt[62] = 1'd0; - else - decoded_instr_nxt[62] = 1'd1; - end - wire [2:1] sv2v_tmp_EE17C; - assign sv2v_tmp_EE17C = dlut_out[5-:2]; - always @(*) decoded_instr_nxt[61-:2] = sv2v_tmp_EE17C; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dlut_out[17-:3]) - 3'd7: decoded_instr_nxt[58-:32] = {ifd_instruction[23:10], ifd_instruction[4:0], 13'd0}; - 3'd1: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[23:15])); - 3'd2: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[23:10])); - 3'd3: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[24:15])); - 3'd4: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[24:10])); - 3'd5: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed({ifd_instruction[24:5], 2'b00})); - 3'd6: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed({ifd_instruction[24:0], 2'b00})); - default: decoded_instr_nxt[58-:32] = 0; - endcase - end - wire [3:1] sv2v_tmp_1A26C; - assign sv2v_tmp_1A26C = ifd_instruction[27:25]; - always @(*) decoded_instr_nxt[25-:3] = sv2v_tmp_1A26C; - wire [1:1] sv2v_tmp_86CFB; - assign sv2v_tmp_86CFB = (ifd_instruction[31:28] == 4'b1111) && !has_trap; - always @(*) decoded_instr_nxt[26] = sv2v_tmp_86CFB; - wire [32:1] sv2v_tmp_B397D; - assign sv2v_tmp_B397D = ifd_pc; - always @(*) decoded_instr_nxt[141-:32] = sv2v_tmp_B397D; - always @(*) begin - if (_sv2v_0) - ; - if (has_trap) - decoded_instr_nxt[21-:2] = 2'd1; - else if (fmt_r || fmt_i) begin - if ((((alu_op[5] || (alu_op == 6'b000111)) || (alu_op == 6'b001000)) || (alu_op == 6'b011111)) || (alu_op == 6'b011011)) - decoded_instr_nxt[21-:2] = 2'd2; - else - decoded_instr_nxt[21-:2] = 2'd1; - end - else if (ifd_instruction[31:28] == 4'b1111) - decoded_instr_nxt[21-:2] = 2'd1; - else - decoded_instr_nxt[21-:2] = 2'd0; - end - assign memory_access_type = ifd_instruction[28:25]; - wire [4:1] sv2v_tmp_D35EA; - assign sv2v_tmp_D35EA = memory_access_type; - always @(*) decoded_instr_nxt[18-:4] = sv2v_tmp_D35EA; - wire [1:1] sv2v_tmp_D0F69; - assign sv2v_tmp_D0F69 = (ifd_instruction[31:30] == 2'b10) && !has_trap; - always @(*) decoded_instr_nxt[19] = sv2v_tmp_D0F69; - wire [1:1] sv2v_tmp_0C594; - assign sv2v_tmp_0C594 = ifd_instruction[29] && fmt_m; - always @(*) decoded_instr_nxt[14] = sv2v_tmp_0C594; - wire [1:1] sv2v_tmp_0363D; - assign sv2v_tmp_0363D = (ifd_instruction[31:28] == 4'b1110) && !has_trap; - always @(*) decoded_instr_nxt[3] = sv2v_tmp_0363D; - wire [3:1] sv2v_tmp_8C9C3; - assign sv2v_tmp_8C9C3 = ifd_instruction[27:25]; - always @(*) decoded_instr_nxt[2-:3] = sv2v_tmp_8C9C3; - function automatic [3:0] sv2v_cast_60D1B; - input reg [3:0] inp; - sv2v_cast_60D1B = inp; - endfunction - always @(*) begin - if (_sv2v_0) - ; - if ((ifd_instruction[31:30] == 2'b10) && ((memory_access_type == 4'b1101) || (memory_access_type == 4'b1110))) - decoded_instr_nxt[12-:4] = sv2v_cast_60D1B(15); - else - decoded_instr_nxt[12-:4] = 0; - end - wire [5:1] sv2v_tmp_E1483; - assign sv2v_tmp_E1483 = ifd_instruction[4:0]; - always @(*) decoded_instr_nxt[8-:5] = sv2v_tmp_E1483; - assign compare = (fmt_r || fmt_i) && ((((((((((((((((alu_op == 6'b010000) || (alu_op == 6'b010001)) || (alu_op == 6'b010010)) || (alu_op == 6'b010011)) || (alu_op == 6'b010100)) || (alu_op == 6'b010101)) || (alu_op == 6'b010110)) || (alu_op == 6'b010111)) || (alu_op == 6'b011000)) || (alu_op == 6'b011001)) || (alu_op == 6'b101100)) || (alu_op == 6'b101110)) || (alu_op == 6'b101101)) || (alu_op == 6'b101111)) || (alu_op == 6'b110000)) || (alu_op == 6'b110001)); - wire [1:1] sv2v_tmp_DE7AB; - assign sv2v_tmp_DE7AB = compare; - always @(*) decoded_instr_nxt[13] = sv2v_tmp_DE7AB; - always @(posedge clk) begin - id_instruction <= decoded_instr_nxt; - id_thread_idx <= ifd_thread_idx; - end - always @(posedge clk or posedge reset) - if (reset) - id_instruction_valid <= 1'sb0; - else - id_instruction_valid <= (ifd_instruction_valid || has_trap) && (!wb_rollback_en || (wb_rollback_thread_idx != ifd_thread_idx)); - initial _sv2v_0 = 0; -endmodule -module int_execute_stage ( - clk, - reset, - of_operand1, - of_operand2, - of_mask_value, - of_instruction_valid, - of_instruction, - of_thread_idx, - of_subcycle, - wb_rollback_en, - wb_rollback_thread_idx, - ix_instruction_valid, - ix_instruction, - ix_result, - ix_mask_value, - ix_thread_idx, - ix_rollback_en, - ix_rollback_pc, - ix_subcycle, - ix_privileged_op_fault, - cr_eret_address, - cr_supervisor_en, - ix_perf_uncond_branch, - ix_perf_cond_branch_taken, - ix_perf_cond_branch_not_taken -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [511:0] of_operand1; - input wire [511:0] of_operand2; - input wire [15:0] of_mask_value; - input of_instruction_valid; - input wire [141:0] of_instruction; - input wire [1:0] of_thread_idx; - input wire [3:0] of_subcycle; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - output reg ix_instruction_valid; - output reg [141:0] ix_instruction; - output reg [511:0] ix_result; - output reg [15:0] ix_mask_value; - output reg [1:0] ix_thread_idx; - output reg ix_rollback_en; - output reg [31:0] ix_rollback_pc; - output reg [3:0] ix_subcycle; - output reg ix_privileged_op_fault; - input wire [127:0] cr_eret_address; - input [0:3] cr_supervisor_en; - output reg ix_perf_uncond_branch; - output reg ix_perf_cond_branch_taken; - output reg ix_perf_cond_branch_not_taken; - wire [511:0] vector_result; - wire eret; - wire privileged_op_fault; - reg branch_taken; - reg conditional_branch; - wire valid_instruction; - genvar _gv_lane_1; - localparam defines_FLOAT32_EXP_WIDTH = 8; - localparam defines_FLOAT32_SIG_WIDTH = 23; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - function automatic [7:0] sv2v_cast_8; - input reg [7:0] inp; - sv2v_cast_8 = inp; - endfunction - generate - for (_gv_lane_1 = 0; _gv_lane_1 < defines_NUM_VECTOR_LANES; _gv_lane_1 = _gv_lane_1 + 1) begin : lane_alu_gen - localparam lane = _gv_lane_1; - wire [31:0] lane_operand1; - wire [31:0] lane_operand2; - reg [31:0] lane_result; - wire [31:0] difference; - wire borrow; - wire negative; - wire overflow; - wire zero; - wire signed_gtr; - wire [5:0] lz; - wire [5:0] tz; - reg [31:0] reciprocal; - wire [31:0] fp_operand; - wire [5:0] reciprocal_estimate; - wire shift_in_sign; - wire [31:0] rshift; - assign lane_operand1 = of_operand1[lane * 32+:32]; - assign lane_operand2 = of_operand2[lane * 32+:32]; - assign {borrow, difference} = {1'b0, lane_operand1} - {1'b0, lane_operand2}; - assign negative = difference[31]; - assign overflow = (lane_operand2[31] == negative) && (lane_operand1[31] != lane_operand2[31]); - assign zero = difference == 0; - assign signed_gtr = overflow == negative; - function automatic [5:0] count_lz; - input [31:0] val; - integer i; - reg found; - begin - count_lz = 32; - found = 0; - for (i = 31; i >= 0; i = i - 1) - if (!found && val[i]) begin - count_lz = 31 - i; - found = 1; - end - end - endfunction - function automatic [5:0] count_tz; - input [31:0] val; - integer i; - reg found; - begin - count_tz = 32; - found = 0; - for (i = 0; i < 32; i = i + 1) - if (!found && val[i]) begin - count_tz = i; - found = 1; - end - end - endfunction - assign lz = count_lz(lane_operand2); - assign tz = count_tz(lane_operand2); - assign shift_in_sign = (of_instruction[70-:6] == 6'b001001 ? lane_operand1[31] : 1'd0); - assign rshift = sv2v_cast_32({{32 {shift_in_sign}}, lane_operand1} >> lane_operand2[4:0]); - assign fp_operand = lane_operand2; - reciprocal_rom rom( - .significand(fp_operand[22:17]), - .reciprocal_estimate(reciprocal_estimate) - ); - always @(*) begin - if (_sv2v_0) - ; - if (fp_operand[30-:8] == 0) - reciprocal = {fp_operand[31], 31'h7f800000}; - else if (fp_operand[30-:8] == 8'hff) begin - if (fp_operand[22-:defines_FLOAT32_SIG_WIDTH] != 0) - reciprocal = 32'h7fffffff; - else - reciprocal = {fp_operand[31], 31'h00000000}; - end - else - reciprocal = {fp_operand[31], (8'd253 - fp_operand[30-:8]) + sv2v_cast_8(fp_operand[22:17] == 0), reciprocal_estimate, {17 {1'b0}}}; - end - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (of_instruction[70-:6]) - 6'b001001, 6'b001010: lane_result = rshift; - 6'b001011: lane_result = lane_operand1 << lane_operand2[4:0]; - 6'b001111: lane_result = lane_operand2; - 6'b000000: lane_result = lane_operand1 | lane_operand2; - 6'b001100: lane_result = sv2v_cast_32(lz); - 6'b001110: lane_result = sv2v_cast_32(tz); - 6'b000001: lane_result = lane_operand1 & lane_operand2; - 6'b000011: lane_result = lane_operand1 ^ lane_operand2; - 6'b000101: lane_result = lane_operand1 + lane_operand2; - 6'b000110: lane_result = difference; - 6'b010000: lane_result = {{31 {1'b0}}, zero}; - 6'b010001: lane_result = {{31 {1'b0}}, !zero}; - 6'b010010: lane_result = {{31 {1'b0}}, signed_gtr && !zero}; - 6'b010011: lane_result = {{31 {1'b0}}, signed_gtr || zero}; - 6'b010100: lane_result = {{31 {1'b0}}, !signed_gtr && !zero}; - 6'b010101: lane_result = {{31 {1'b0}}, !signed_gtr || zero}; - 6'b010110: lane_result = {{31 {1'b0}}, !borrow && !zero}; - 6'b010111: lane_result = {{31 {1'b0}}, !borrow || zero}; - 6'b011000: lane_result = {{31 {1'b0}}, borrow && !zero}; - 6'b011001: lane_result = {{31 {1'b0}}, borrow || zero}; - 6'b011101: lane_result = sv2v_cast_32($signed(lane_operand2[7:0])); - 6'b011110: lane_result = sv2v_cast_32($signed(lane_operand2[15:0])); - 6'b001101, 6'b011010: lane_result = of_operand1[~lane_operand2 * 32+:32]; - 6'b011100: lane_result = reciprocal; - default: lane_result = 0; - endcase - end - assign vector_result[lane * 32+:32] = lane_result; - end - endgenerate - assign valid_instruction = (of_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != of_thread_idx))) && (of_instruction[21-:2] == 2'd1); - assign eret = (valid_instruction && of_instruction[26]) && (of_instruction[25-:3] == 3'b111); - assign privileged_op_fault = eret && !cr_supervisor_en[of_thread_idx]; - always @(*) begin - if (_sv2v_0) - ; - branch_taken = 0; - conditional_branch = 0; - if ((valid_instruction && of_instruction[26]) && !privileged_op_fault) - (* full_case, parallel_case *) - case (of_instruction[25-:3]) - 3'b001: begin - branch_taken = of_operand1[0+:32] == 0; - conditional_branch = 1; - end - 3'b010: begin - branch_taken = of_operand1[0+:32] != 0; - conditional_branch = 1; - end - 3'b011, 3'b100, 3'b110, 3'b000, 3'b111: branch_taken = 1; - default: - ; - endcase - end - always @(posedge clk) begin - ix_instruction <= of_instruction; - ix_result <= vector_result; - ix_mask_value <= of_mask_value; - ix_thread_idx <= of_thread_idx; - ix_subcycle <= of_subcycle; - (* full_case, parallel_case *) - case (of_instruction[25-:3]) - 3'b110, 3'b000: ix_rollback_pc <= of_operand1[0+:32]; - 3'b111: ix_rollback_pc <= cr_eret_address[(3 - of_thread_idx) * 32+:32]; - default: ix_rollback_pc <= of_instruction[141-:32] + of_instruction[58-:32]; - endcase - end - always @(posedge clk or posedge reset) - if (reset) begin - ix_instruction_valid <= 1'sb0; - ix_perf_cond_branch_not_taken <= 1'sb0; - ix_perf_cond_branch_taken <= 1'sb0; - ix_perf_uncond_branch <= 1'sb0; - ix_privileged_op_fault <= 1'sb0; - ix_rollback_en <= 1'sb0; - end - else begin - if (valid_instruction) begin - ix_instruction_valid <= 1; - ix_privileged_op_fault <= privileged_op_fault; - ix_rollback_en <= branch_taken; - end - else begin - ix_instruction_valid <= 0; - ix_rollback_en <= 0; - end - ix_perf_uncond_branch <= !conditional_branch && branch_taken; - ix_perf_cond_branch_taken <= conditional_branch && branch_taken; - ix_perf_cond_branch_not_taken <= conditional_branch && !branch_taken; - end - initial _sv2v_0 = 0; -endmodule -module io_request_queue ( - clk, - reset, - dd_io_write_en, - dd_io_read_en, - dd_io_thread_idx, - dd_io_addr, - dd_io_write_value, - ior_read_value, - ior_rollback_en, - ior_pending, - ior_wake_bitmap, - ii_ready, - ii_response_valid, - ii_response, - ior_request_valid, - ior_request -); - parameter CORE_ID = 0; - input clk; - input reset; - input dd_io_write_en; - input dd_io_read_en; - input wire [1:0] dd_io_thread_idx; - input wire [31:0] dd_io_addr; - input wire [31:0] dd_io_write_value; - output reg [31:0] ior_read_value; - output reg ior_rollback_en; - output wire [3:0] ior_pending; - output wire [3:0] ior_wake_bitmap; - input ii_ready; - input ii_response_valid; - input wire [37:0] ii_response; - output wire ior_request_valid; - output wire [66:0] ior_request; - reg [66:0] pending_request [0:3]; - wire [3:0] wake_thread_oh; - wire [3:0] send_request; - wire [3:0] send_grant_oh; - wire [1:0] send_grant_idx; - genvar _gv_thread_idx_4; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_4 = 0; _gv_thread_idx_4 < 4; _gv_thread_idx_4 = _gv_thread_idx_4 + 1) begin : io_request_gen - localparam thread_idx = _gv_thread_idx_4; - assign send_request[thread_idx] = pending_request[thread_idx][66] && !pending_request[thread_idx][65]; - assign ior_pending[thread_idx] = (pending_request[thread_idx][66] && pending_request[thread_idx][65]) || send_grant_oh[thread_idx]; - always @(posedge clk or posedge reset) - if (reset) - pending_request[thread_idx] <= 0; - else begin - if ((dd_io_write_en | dd_io_read_en) && (dd_io_thread_idx == sv2v_cast_2(thread_idx))) begin - if (pending_request[thread_idx][66]) - pending_request[thread_idx][66] <= 0; - else begin - pending_request[thread_idx][66] <= 1; - pending_request[thread_idx][64] <= dd_io_write_en; - pending_request[thread_idx][63-:32] <= dd_io_addr; - pending_request[thread_idx][31-:32] <= dd_io_write_value; - pending_request[thread_idx][65] <= 0; - end - end - if ((ii_response_valid && (ii_response[37-:4] == CORE_ID)) && (ii_response[33-:2] == sv2v_cast_2(thread_idx))) - pending_request[thread_idx][31-:32] <= ii_response[31-:32]; - if ((ii_ready && |send_grant_oh) && (send_grant_idx == sv2v_cast_2(thread_idx))) - pending_request[thread_idx][65] <= 1; - end - end - endgenerate - rr_arbiter #(.NUM_REQUESTERS(4)) request_arbiter( - .request(send_request), - .update_lru(1'b1), - .grant_oh(send_grant_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_send_thread( - .one_hot(send_grant_oh), - .index(send_grant_idx) - ); - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_wake_thread( - .index(ii_response[33-:2]), - .one_hot(wake_thread_oh) - ); - assign ior_wake_bitmap = (ii_response_valid && (ii_response[37-:4] == CORE_ID) ? wake_thread_oh : 4'd0); - assign ior_request_valid = |send_request; - assign ior_request[66] = pending_request[send_grant_idx][64]; - assign ior_request[63-:32] = pending_request[send_grant_idx][63-:32]; - assign ior_request[31-:32] = pending_request[send_grant_idx][31-:32]; - assign ior_request[65-:2] = send_grant_idx; - always @(posedge clk or posedge reset) - if (reset) - ior_rollback_en <= 1'sb0; - else if ((dd_io_write_en || dd_io_read_en) && !pending_request[dd_io_thread_idx][66]) - ior_rollback_en <= 1; - else - ior_rollback_en <= 0; - always @(posedge clk) ior_read_value <= pending_request[dd_io_thread_idx][31-:32]; -endmodule -module l1_l2_interface ( - clk, - reset, - l2_ready, - l2_response_valid, - l2_response, - l2i_request_valid, - l2i_request, - l2i_icache_lru_fill_en, - l2i_icache_lru_fill_set, - l2i_itag_update_en, - l2i_itag_update_set, - l2i_itag_update_tag, - l2i_itag_update_valid, - sq_store_sync_pending, - ift_fill_lru, - ifd_cache_miss, - ifd_cache_miss_paddr, - ifd_cache_miss_thread_idx, - l2i_idata_update_en, - l2i_idata_update_way, - l2i_idata_update_set, - l2i_idata_update_data, - l2i_dcache_wake_bitmap, - l2i_icache_wake_bitmap, - dt_snoop_valid, - dt_snoop_tag, - dt_fill_lru, - l2i_snoop_en, - l2i_snoop_set, - l2i_dtag_update_en_oh, - l2i_dtag_update_set, - l2i_dtag_update_tag, - l2i_dtag_update_valid, - l2i_dcache_lru_fill_en, - l2i_dcache_lru_fill_set, - dd_cache_miss, - dd_cache_miss_addr, - dd_cache_miss_thread_idx, - dd_cache_miss_sync, - dd_store_en, - dd_flush_en, - dd_membar_en, - dd_iinvalidate_en, - dd_dinvalidate_en, - dd_store_mask, - dd_store_addr, - dd_store_data, - dd_store_thread_idx, - dd_store_sync, - dd_store_bypass_addr, - dd_store_bypass_thread_idx, - l2i_ddata_update_en, - l2i_ddata_update_way, - l2i_ddata_update_set, - l2i_ddata_update_data, - sq_store_bypass_mask, - sq_store_sync_success, - sq_store_bypass_data, - sq_rollback_en, - l2i_perf_store -); - reg _sv2v_0; - parameter CORE_ID = 0; - input clk; - input reset; - input l2_ready; - input l2_response_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [548:0] l2_response; - output reg l2i_request_valid; - output reg [611:0] l2i_request; - output wire l2i_icache_lru_fill_en; - output wire [5:0] l2i_icache_lru_fill_set; - output wire [3:0] l2i_itag_update_en; - output wire [5:0] l2i_itag_update_set; - localparam defines_ICACHE_TAG_BITS = 20; - output wire [19:0] l2i_itag_update_tag; - output wire l2i_itag_update_valid; - output wire [3:0] sq_store_sync_pending; - input wire [1:0] ift_fill_lru; - input wire ifd_cache_miss; - input wire [25:0] ifd_cache_miss_paddr; - input wire [1:0] ifd_cache_miss_thread_idx; - output reg l2i_idata_update_en; - output reg [1:0] l2i_idata_update_way; - output reg [5:0] l2i_idata_update_set; - output reg [511:0] l2i_idata_update_data; - output wire [3:0] l2i_dcache_wake_bitmap; - output wire [3:0] l2i_icache_wake_bitmap; - input wire [0:3] dt_snoop_valid; - localparam defines_DCACHE_TAG_BITS = 20; - input wire [79:0] dt_snoop_tag; - input wire [1:0] dt_fill_lru; - output wire l2i_snoop_en; - output wire [5:0] l2i_snoop_set; - output wire [3:0] l2i_dtag_update_en_oh; - output wire [5:0] l2i_dtag_update_set; - output wire [19:0] l2i_dtag_update_tag; - output wire l2i_dtag_update_valid; - output wire l2i_dcache_lru_fill_en; - output wire [5:0] l2i_dcache_lru_fill_set; - input dd_cache_miss; - input wire [25:0] dd_cache_miss_addr; - input wire [1:0] dd_cache_miss_thread_idx; - input dd_cache_miss_sync; - input dd_store_en; - input dd_flush_en; - input dd_membar_en; - input dd_iinvalidate_en; - input dd_dinvalidate_en; - input [63:0] dd_store_mask; - input wire [25:0] dd_store_addr; - input wire [511:0] dd_store_data; - input wire [1:0] dd_store_thread_idx; - input dd_store_sync; - input wire [25:0] dd_store_bypass_addr; - input wire [1:0] dd_store_bypass_thread_idx; - output reg l2i_ddata_update_en; - output reg [1:0] l2i_ddata_update_way; - output reg [5:0] l2i_ddata_update_set; - output reg [511:0] l2i_ddata_update_data; - output wire [63:0] sq_store_bypass_mask; - output wire sq_store_sync_success; - output wire [511:0] sq_store_bypass_data; - output wire sq_rollback_en; - output reg l2i_perf_store; - wire [3:0] snoop_hit_way_oh; - wire [1:0] snoop_hit_way_idx; - wire [3:0] ifill_way_oh; - wire [3:0] dupdate_way_oh; - reg [1:0] dupdate_way_idx; - wire ack_for_me; - wire icache_update_en; - wire dcache_update_en; - wire dcache_l2_response_valid; - wire [1:0] dcache_l2_response_idx; - wire icache_l2_response_valid; - wire [1:0] icache_l2_response_idx; - wire storebuf_l2_response_valid; - wire [1:0] storebuf_l2_response_idx; - wire [3:0] dcache_miss_wake_bitmap; - reg storebuf_dequeue_ack; - wire icache_dequeue_ready; - reg icache_dequeue_ack; - wire dcache_dequeue_ready; - reg dcache_dequeue_ack; - wire [25:0] dcache_dequeue_addr; - wire dcache_dequeue_sync; - wire [25:0] icache_dequeue_addr; - wire [1:0] dcache_dequeue_idx; - wire [1:0] icache_dequeue_idx; - reg response_stage2_valid; - reg [548:0] response_stage2; - wire [5:0] dcache_set_stage1; - wire [5:0] icache_set_stage1; - wire [5:0] dcache_set_stage2; - wire [5:0] icache_set_stage2; - wire [19:0] dcache_tag_stage2; - wire [19:0] icache_tag_stage2; - wire storebuf_l2_sync_success; - wire response_iinvalidate; - wire response_dinvalidate; - wire [25:0] sq_dequeue_addr; - wire [511:0] sq_dequeue_data; - wire sq_dequeue_dinvalidate; - wire sq_dequeue_flush; - wire [1:0] sq_dequeue_idx; - wire sq_dequeue_iinvalidate; - wire [63:0] sq_dequeue_mask; - wire sq_dequeue_ready; - wire sq_dequeue_sync; - wire [3:0] sq_wake_bitmap; - l1_store_queue l1_store_queue( - .clk(clk), - .reset(reset), - .sq_store_sync_pending(sq_store_sync_pending), - .dd_store_en(dd_store_en), - .dd_flush_en(dd_flush_en), - .dd_membar_en(dd_membar_en), - .dd_iinvalidate_en(dd_iinvalidate_en), - .dd_dinvalidate_en(dd_dinvalidate_en), - .dd_store_addr(dd_store_addr), - .dd_store_mask(dd_store_mask), - .dd_store_data(dd_store_data), - .dd_store_sync(dd_store_sync), - .dd_store_thread_idx(dd_store_thread_idx), - .dd_store_bypass_addr(dd_store_bypass_addr), - .dd_store_bypass_thread_idx(dd_store_bypass_thread_idx), - .sq_store_bypass_mask(sq_store_bypass_mask), - .sq_store_bypass_data(sq_store_bypass_data), - .sq_store_sync_success(sq_store_sync_success), - .storebuf_dequeue_ack(storebuf_dequeue_ack), - .storebuf_l2_response_valid(storebuf_l2_response_valid), - .storebuf_l2_response_idx(storebuf_l2_response_idx), - .storebuf_l2_sync_success(storebuf_l2_sync_success), - .sq_dequeue_ready(sq_dequeue_ready), - .sq_dequeue_addr(sq_dequeue_addr), - .sq_dequeue_idx(sq_dequeue_idx), - .sq_dequeue_mask(sq_dequeue_mask), - .sq_dequeue_data(sq_dequeue_data), - .sq_dequeue_sync(sq_dequeue_sync), - .sq_dequeue_flush(sq_dequeue_flush), - .sq_dequeue_iinvalidate(sq_dequeue_iinvalidate), - .sq_dequeue_dinvalidate(sq_dequeue_dinvalidate), - .sq_rollback_en(sq_rollback_en), - .sq_wake_bitmap(sq_wake_bitmap) - ); - l1_load_miss_queue l1_load_miss_queue_dcache( - .cache_miss(dd_cache_miss), - .cache_miss_addr(dd_cache_miss_addr), - .cache_miss_thread_idx(dd_cache_miss_thread_idx), - .cache_miss_sync(dd_cache_miss_sync), - .dequeue_ready(dcache_dequeue_ready), - .dequeue_ack(dcache_dequeue_ack), - .dequeue_addr(dcache_dequeue_addr), - .dequeue_idx(dcache_dequeue_idx), - .dequeue_sync(dcache_dequeue_sync), - .l2_response_valid(dcache_l2_response_valid), - .l2_response_idx(dcache_l2_response_idx), - .wake_bitmap(dcache_miss_wake_bitmap), - .clk(clk), - .reset(reset) - ); - assign l2i_dcache_wake_bitmap = dcache_miss_wake_bitmap | sq_wake_bitmap; - localparam [0:0] sv2v_uu_l1_load_miss_queue_icache_ext_cache_miss_sync_0 = 1'sb0; - l1_load_miss_queue l1_load_miss_queue_icache( - .cache_miss(ifd_cache_miss), - .cache_miss_addr(ifd_cache_miss_paddr), - .cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .cache_miss_sync(sv2v_uu_l1_load_miss_queue_icache_ext_cache_miss_sync_0), - .dequeue_ready(icache_dequeue_ready), - .dequeue_ack(icache_dequeue_ack), - .dequeue_addr(icache_dequeue_addr), - .dequeue_idx(icache_dequeue_idx), - .dequeue_sync(), - .l2_response_valid(icache_l2_response_valid), - .l2_response_idx(icache_l2_response_idx), - .wake_bitmap(l2i_icache_wake_bitmap), - .clk(clk), - .reset(reset) - ); - assign dcache_set_stage1 = l2_response[517:512]; - assign icache_set_stage1 = l2_response[517:512]; - assign l2i_snoop_en = l2_response_valid && (l2_response[538] == 1'd1); - assign l2i_snoop_set = dcache_set_stage1; - assign l2i_dcache_lru_fill_en = ((l2_response_valid && (l2_response[538] == 1'd1)) && (l2_response[541-:3] == 3'd0)) && (l2_response[547-:4] == CORE_ID); - assign l2i_dcache_lru_fill_set = dcache_set_stage1; - assign l2i_icache_lru_fill_en = ((l2_response_valid && (l2_response[538] == 1'd0)) && (l2_response[541-:3] == 3'd0)) && (l2_response[547-:4] == CORE_ID); - assign l2i_icache_lru_fill_set = icache_set_stage1; - always @(posedge clk or posedge reset) - if (reset) - response_stage2_valid <= 0; - else - response_stage2_valid <= l2_response_valid; - always @(posedge clk) response_stage2 <= l2_response; - assign {icache_tag_stage2, icache_set_stage2} = response_stage2[537-:26]; - assign {dcache_tag_stage2, dcache_set_stage2} = response_stage2[537-:26]; - genvar _gv_way_idx_5; - generate - for (_gv_way_idx_5 = 0; _gv_way_idx_5 < 4; _gv_way_idx_5 = _gv_way_idx_5 + 1) begin : snoop_hit_check_gen - localparam way_idx = _gv_way_idx_5; - assign snoop_hit_way_oh[way_idx] = (dt_snoop_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS] == dcache_tag_stage2) && dt_snoop_valid[way_idx]; - end - endgenerate - oh_to_idx #(.NUM_SIGNALS(4)) convert_snoop_request_pending( - .index(snoop_hit_way_idx), - .one_hot(snoop_hit_way_oh) - ); - always @(*) begin - if (_sv2v_0) - ; - if (|snoop_hit_way_oh) - dupdate_way_idx = snoop_hit_way_idx; - else - dupdate_way_idx = dt_fill_lru; - end - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_dfill_way( - .index(dupdate_way_idx), - .one_hot(dupdate_way_oh) - ); - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_ifill_way( - .index(ift_fill_lru), - .one_hot(ifill_way_oh) - ); - assign ack_for_me = response_stage2_valid && (response_stage2[547-:4] == CORE_ID); - assign response_dinvalidate = response_stage2[541-:3] == 3'd4; - assign dcache_update_en = (ack_for_me && (((response_stage2[541-:3] == 3'd0) && (response_stage2[538] == 1'd1)) || (response_stage2[541-:3] == 3'd1))) || ((response_stage2_valid && response_dinvalidate) && |snoop_hit_way_oh); - assign l2i_dtag_update_en_oh = dupdate_way_oh & {4 {dcache_update_en}}; - assign l2i_dtag_update_tag = dcache_tag_stage2; - assign l2i_dtag_update_set = dcache_set_stage2; - assign l2i_dtag_update_valid = !response_dinvalidate; - assign response_iinvalidate = response_stage2_valid && (response_stage2[541-:3] == 3'd3); - assign icache_update_en = (ack_for_me && (response_stage2[538] == 1'd0)) || response_iinvalidate; - assign l2i_itag_update_en = (response_iinvalidate ? {4 {1'b1}} : ifill_way_oh & {4 {icache_update_en}}); - assign l2i_itag_update_tag = icache_tag_stage2; - assign l2i_itag_update_set = icache_set_stage2; - assign l2i_itag_update_valid = !response_iinvalidate; - assign icache_l2_response_valid = ack_for_me && (response_stage2[538] == 1'd0); - assign dcache_l2_response_valid = (ack_for_me && (response_stage2[541-:3] == 3'd0)) && (response_stage2[538] == 1'd1); - assign storebuf_l2_response_valid = ack_for_me && ((((response_stage2[541-:3] == 3'd1) || (response_stage2[541-:3] == 3'd2)) || (response_stage2[541-:3] == 3'd3)) || (response_stage2[541-:3] == 3'd4)); - assign dcache_l2_response_idx = response_stage2[543-:2]; - assign icache_l2_response_idx = response_stage2[543-:2]; - assign storebuf_l2_response_idx = response_stage2[543-:2]; - assign storebuf_l2_sync_success = response_stage2[548]; - always @(posedge clk) begin - l2i_ddata_update_way <= dupdate_way_idx; - l2i_ddata_update_set <= dcache_set_stage2; - l2i_ddata_update_data <= response_stage2[511-:defines_CACHE_LINE_BITS]; - l2i_idata_update_way <= ift_fill_lru; - l2i_idata_update_set <= icache_set_stage2; - l2i_idata_update_data <= response_stage2[511-:defines_CACHE_LINE_BITS]; - end - always @(posedge clk or posedge reset) - if (reset) begin - l2i_ddata_update_en <= 1'sb0; - l2i_idata_update_en <= 1'sb0; - end - else begin - l2i_ddata_update_en <= dcache_update_en || ((|snoop_hit_way_oh && response_stage2_valid) && (response_stage2[541-:3] == 3'd1)); - l2i_idata_update_en <= icache_update_en; - end - always @(*) begin - if (_sv2v_0) - ; - l2i_request_valid = 0; - l2i_request = 0; - storebuf_dequeue_ack = 0; - icache_dequeue_ack = 0; - dcache_dequeue_ack = 0; - l2i_perf_store = 0; - l2i_request[611-:4] = CORE_ID; - if (dcache_dequeue_ready) begin - l2i_request_valid = 1; - l2i_request[605-:3] = (dcache_dequeue_sync ? 3'd1 : 3'd0); - l2i_request[607-:2] = dcache_dequeue_idx; - l2i_request[601-:26] = dcache_dequeue_addr; - l2i_request[602] = 1'd1; - if (l2_ready) - dcache_dequeue_ack = 1; - end - else if (icache_dequeue_ready) begin - l2i_request_valid = 1; - l2i_request[605-:3] = 3'd0; - l2i_request[607-:2] = icache_dequeue_idx; - l2i_request[601-:26] = icache_dequeue_addr; - l2i_request[602] = 1'd0; - if (l2_ready) - icache_dequeue_ack = 1; - end - else if (sq_dequeue_ready) begin - l2i_request_valid = 1; - if (sq_dequeue_flush) - l2i_request[605-:3] = 3'd4; - else if (sq_dequeue_sync) - l2i_request[605-:3] = 3'd3; - else if (sq_dequeue_iinvalidate) - l2i_request[605-:3] = 3'd5; - else if (sq_dequeue_dinvalidate) - l2i_request[605-:3] = 3'd6; - else - l2i_request[605-:3] = 3'd2; - l2i_request[607-:2] = sq_dequeue_idx; - l2i_request[601-:26] = sq_dequeue_addr; - l2i_request[511-:defines_CACHE_LINE_BITS] = sq_dequeue_data; - l2i_request[575-:64] = sq_dequeue_mask; - l2i_request[602] = 1'd1; - if (l2_ready) begin - storebuf_dequeue_ack = 1; - l2i_perf_store = l2i_request[605-:3] == 3'd2; - end - end - end - initial _sv2v_0 = 0; -endmodule -module l1_load_miss_queue ( - clk, - reset, - cache_miss, - cache_miss_addr, - cache_miss_thread_idx, - cache_miss_sync, - dequeue_ready, - dequeue_ack, - dequeue_addr, - dequeue_idx, - dequeue_sync, - l2_response_valid, - l2_response_idx, - wake_bitmap -); - input clk; - input reset; - input cache_miss; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [25:0] cache_miss_addr; - input wire [1:0] cache_miss_thread_idx; - input cache_miss_sync; - output wire dequeue_ready; - input dequeue_ack; - output wire [25:0] dequeue_addr; - output wire [1:0] dequeue_idx; - output wire dequeue_sync; - input l2_response_valid; - input wire [1:0] l2_response_idx; - output wire [3:0] wake_bitmap; - reg [32:0] pending_entries [0:3]; - wire [3:0] collided_miss_oh; - wire [3:0] miss_thread_oh; - wire request_unique; - wire [3:0] send_grant_oh; - wire [3:0] arbiter_request; - wire [1:0] send_grant_idx; - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_miss_thread( - .index(cache_miss_thread_idx), - .one_hot(miss_thread_oh) - ); - rr_arbiter #(.NUM_REQUESTERS(4)) request_arbiter( - .request(arbiter_request), - .update_lru(1'b1), - .grant_oh(send_grant_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_send_grant( - .index(send_grant_idx), - .one_hot(send_grant_oh) - ); - assign dequeue_ready = |arbiter_request; - assign dequeue_addr = pending_entries[send_grant_idx][26-:26]; - assign dequeue_idx = send_grant_idx; - assign dequeue_sync = pending_entries[send_grant_idx][0]; - assign request_unique = !(|collided_miss_oh); - assign wake_bitmap = (l2_response_valid ? pending_entries[l2_response_idx][30-:4] : 4'd0); - genvar _gv_wait_entry_1; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_wait_entry_1 = 0; _gv_wait_entry_1 < 4; _gv_wait_entry_1 = _gv_wait_entry_1 + 1) begin : wait_logic_gen - localparam wait_entry = _gv_wait_entry_1; - assign collided_miss_oh[wait_entry] = ((pending_entries[wait_entry][32] && (pending_entries[wait_entry][26-:26] == cache_miss_addr)) && !pending_entries[wait_entry][0]) && !cache_miss_sync; - assign arbiter_request[wait_entry] = pending_entries[wait_entry][32] && !pending_entries[wait_entry][31]; - always @(posedge clk or posedge reset) - if (reset) - pending_entries[wait_entry] <= 0; - else begin - if (dequeue_ack && send_grant_oh[wait_entry]) - pending_entries[wait_entry][31] <= 1; - else if ((cache_miss && miss_thread_oh[wait_entry]) && request_unique) begin - pending_entries[wait_entry][30-:4] <= miss_thread_oh; - pending_entries[wait_entry][32] <= 1; - pending_entries[wait_entry][26-:26] <= cache_miss_addr; - pending_entries[wait_entry][31] <= 0; - pending_entries[wait_entry][0] <= cache_miss_sync; - end - else if (l2_response_valid && (l2_response_idx == sv2v_cast_2(wait_entry))) - pending_entries[wait_entry][32] <= 0; - if (cache_miss && collided_miss_oh[wait_entry]) - pending_entries[wait_entry][30-:4] <= pending_entries[wait_entry][30-:4] | miss_thread_oh; - end - end - endgenerate -endmodule -module l1_store_queue ( - clk, - reset, - sq_store_sync_pending, - dd_store_en, - dd_flush_en, - dd_membar_en, - dd_iinvalidate_en, - dd_dinvalidate_en, - dd_store_addr, - dd_store_mask, - dd_store_data, - dd_store_sync, - dd_store_thread_idx, - dd_store_bypass_addr, - dd_store_bypass_thread_idx, - sq_store_bypass_mask, - sq_store_bypass_data, - sq_store_sync_success, - storebuf_dequeue_ack, - storebuf_l2_response_valid, - storebuf_l2_response_idx, - storebuf_l2_sync_success, - sq_dequeue_ready, - sq_dequeue_addr, - sq_dequeue_idx, - sq_dequeue_mask, - sq_dequeue_data, - sq_dequeue_sync, - sq_dequeue_flush, - sq_dequeue_iinvalidate, - sq_dequeue_dinvalidate, - sq_rollback_en, - sq_wake_bitmap -); - reg _sv2v_0; - input clk; - input reset; - output wire [3:0] sq_store_sync_pending; - input dd_store_en; - input dd_flush_en; - input dd_membar_en; - input dd_iinvalidate_en; - input dd_dinvalidate_en; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [25:0] dd_store_addr; - input [63:0] dd_store_mask; - localparam defines_CACHE_LINE_BITS = 512; - input wire [511:0] dd_store_data; - input dd_store_sync; - input wire [1:0] dd_store_thread_idx; - input wire [25:0] dd_store_bypass_addr; - input wire [1:0] dd_store_bypass_thread_idx; - output reg [63:0] sq_store_bypass_mask; - output reg [511:0] sq_store_bypass_data; - output reg sq_store_sync_success; - input storebuf_dequeue_ack; - input storebuf_l2_response_valid; - input wire [1:0] storebuf_l2_response_idx; - input storebuf_l2_sync_success; - output wire sq_dequeue_ready; - output wire [25:0] sq_dequeue_addr; - output wire [1:0] sq_dequeue_idx; - output wire [63:0] sq_dequeue_mask; - output wire [511:0] sq_dequeue_data; - output wire sq_dequeue_sync; - output wire sq_dequeue_flush; - output wire sq_dequeue_iinvalidate; - output wire sq_dequeue_dinvalidate; - output reg sq_rollback_en; - output wire [3:0] sq_wake_bitmap; - reg [610:0] pending_stores [0:3]; - reg [3:0] rollback; - wire [3:0] send_request; - wire [1:0] send_grant_idx; - wire [3:0] send_grant_oh; - rr_arbiter #(.NUM_REQUESTERS(4)) request_arbiter( - .request(send_request), - .update_lru(1'b1), - .grant_oh(send_grant_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_send_grant( - .index(send_grant_idx), - .one_hot(send_grant_oh) - ); - genvar _gv_thread_idx_5; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_5 = 0; _gv_thread_idx_5 < 4; _gv_thread_idx_5 = _gv_thread_idx_5 + 1) begin : thread_store_buf_gen - localparam thread_idx = _gv_thread_idx_5; - wire update_store_entry; - wire can_write_combine; - wire store_requested_this_entry; - wire send_this_cycle; - wire restarted_sync_request; - wire got_response_this_entry; - wire membar_requested_this_entry; - wire enqueue_cache_control; - assign send_request[thread_idx] = pending_stores[thread_idx][602] && !pending_stores[thread_idx][606]; - assign store_requested_this_entry = dd_store_en && (dd_store_thread_idx == sv2v_cast_2(thread_idx)); - assign membar_requested_this_entry = dd_membar_en && (dd_store_thread_idx == sv2v_cast_2(thread_idx)); - assign send_this_cycle = send_grant_oh[thread_idx] && storebuf_dequeue_ack; - assign can_write_combine = (((((((((pending_stores[thread_idx][602] && (pending_stores[thread_idx][25-:26] == dd_store_addr)) && !pending_stores[thread_idx][609]) && !pending_stores[thread_idx][608]) && !pending_stores[thread_idx][607]) && !dd_store_sync) && !pending_stores[thread_idx][606]) && !send_this_cycle) && !dd_flush_en) && !dd_iinvalidate_en) && !dd_dinvalidate_en; - assign restarted_sync_request = (pending_stores[thread_idx][602] && pending_stores[thread_idx][605]) && pending_stores[thread_idx][610]; - assign update_store_entry = (store_requested_this_entry && ((!pending_stores[thread_idx][602] || can_write_combine) || got_response_this_entry)) && !restarted_sync_request; - assign got_response_this_entry = storebuf_l2_response_valid && (storebuf_l2_response_idx == sv2v_cast_2(thread_idx)); - assign sq_wake_bitmap[thread_idx] = got_response_this_entry && pending_stores[thread_idx][603]; - assign enqueue_cache_control = ((dd_store_thread_idx == sv2v_cast_2(thread_idx)) && (!pending_stores[thread_idx][602] || got_response_this_entry)) && ((dd_flush_en || dd_dinvalidate_en) || dd_iinvalidate_en); - assign sq_store_sync_pending[thread_idx] = pending_stores[thread_idx][602] && pending_stores[thread_idx][610]; - always @(*) begin - if (_sv2v_0) - ; - rollback[thread_idx] = 0; - if ((dd_store_thread_idx == sv2v_cast_2(thread_idx)) && (((dd_flush_en || dd_dinvalidate_en) || dd_iinvalidate_en) || dd_store_en)) begin - if (dd_store_sync) - rollback[thread_idx] = !restarted_sync_request; - else if ((pending_stores[thread_idx][602] && !can_write_combine) && !got_response_this_entry) - rollback[thread_idx] = 1; - end - else if ((membar_requested_this_entry && pending_stores[thread_idx][602]) && !got_response_this_entry) - rollback[thread_idx] = 1; - end - always @(posedge clk or posedge reset) - if (reset) - pending_stores[thread_idx] <= 0; - else begin - if (((((dd_store_en || dd_flush_en) || dd_membar_en) || dd_iinvalidate_en) || dd_dinvalidate_en) && (dd_store_thread_idx == thread_idx)) - ; - if (((dd_store_en && (dd_store_thread_idx == thread_idx)) && pending_stores[thread_idx][610]) && pending_stores[thread_idx][602]) - ; - if (send_this_cycle) - pending_stores[thread_idx][606] <= 1; - if (update_store_entry) begin - begin : sv2v_autoblock_1 - reg signed [31:0] byte_lane; - for (byte_lane = 0; byte_lane < defines_CACHE_LINE_BYTES; byte_lane = byte_lane + 1) - if (dd_store_mask[byte_lane]) - pending_stores[thread_idx][90 + (byte_lane * 8)+:8] <= dd_store_data[byte_lane * 8+:8]; - end - if (can_write_combine) - pending_stores[thread_idx][89-:64] <= pending_stores[thread_idx][89-:64] | dd_store_mask; - else - pending_stores[thread_idx][89-:64] <= dd_store_mask; - end - if (sq_wake_bitmap[thread_idx]) - pending_stores[thread_idx][603] <= 0; - else if (rollback[thread_idx]) - pending_stores[thread_idx][603] <= 1; - if (store_requested_this_entry) begin - if (restarted_sync_request) - pending_stores[thread_idx][602] <= 0; - else if (update_store_entry && !can_write_combine) begin - pending_stores[thread_idx][602] <= 1; - pending_stores[thread_idx][25-:26] <= dd_store_addr; - pending_stores[thread_idx][610] <= dd_store_sync; - pending_stores[thread_idx][609] <= 0; - pending_stores[thread_idx][608] <= 0; - pending_stores[thread_idx][607] <= 0; - pending_stores[thread_idx][606] <= 0; - pending_stores[thread_idx][605] <= 0; - end - end - else if (enqueue_cache_control) begin - pending_stores[thread_idx][602] <= 1; - pending_stores[thread_idx][25-:26] <= dd_store_addr; - pending_stores[thread_idx][610] <= 0; - pending_stores[thread_idx][609] <= dd_flush_en; - pending_stores[thread_idx][608] <= dd_iinvalidate_en; - pending_stores[thread_idx][607] <= dd_dinvalidate_en; - pending_stores[thread_idx][606] <= 0; - pending_stores[thread_idx][605] <= 0; - end - if ((got_response_this_entry && (!store_requested_this_entry || !update_store_entry)) && !enqueue_cache_control) begin - if (pending_stores[thread_idx][610]) begin - pending_stores[thread_idx][605] <= 1; - pending_stores[thread_idx][604] <= storebuf_l2_sync_success; - end - else - pending_stores[thread_idx][602] <= 0; - end - end - end - endgenerate - assign sq_dequeue_ready = |send_grant_oh; - assign sq_dequeue_idx = send_grant_idx; - assign sq_dequeue_addr = pending_stores[send_grant_idx][25-:26]; - assign sq_dequeue_mask = pending_stores[send_grant_idx][89-:64]; - assign sq_dequeue_data = pending_stores[send_grant_idx][601-:512]; - assign sq_dequeue_sync = pending_stores[send_grant_idx][610]; - assign sq_dequeue_flush = pending_stores[send_grant_idx][609]; - assign sq_dequeue_iinvalidate = pending_stores[send_grant_idx][608]; - assign sq_dequeue_dinvalidate = pending_stores[send_grant_idx][607]; - always @(posedge clk) begin - sq_store_bypass_data <= pending_stores[dd_store_bypass_thread_idx][601-:512]; - if (((((dd_store_bypass_addr == pending_stores[dd_store_bypass_thread_idx][25-:26]) && pending_stores[dd_store_bypass_thread_idx][602]) && !pending_stores[dd_store_bypass_thread_idx][609]) && !pending_stores[dd_store_bypass_thread_idx][608]) && !pending_stores[dd_store_bypass_thread_idx][607]) - sq_store_bypass_mask <= pending_stores[dd_store_bypass_thread_idx][89-:64]; - else - sq_store_bypass_mask <= 0; - sq_store_sync_success <= pending_stores[dd_store_thread_idx][604]; - end - always @(posedge clk or posedge reset) - if (reset) - sq_rollback_en <= 1'sb0; - else - sq_rollback_en <= |rollback; - initial _sv2v_0 = 0; -endmodule -module l2_cache_arb_stage ( - clk, - reset, - l2i_request_valid, - l2i_request, - l2_ready, - l2a_request_valid, - l2a_request, - l2a_data_from_memory, - l2a_l2_fill, - l2a_restarted_flush, - l2bi_request_valid, - l2bi_request, - l2bi_data_from_memory, - l2bi_stall, - l2bi_collided_miss -); - input clk; - input reset; - input [0:0] l2i_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2i_request; - output wire [0:0] l2_ready; - output reg l2a_request_valid; - output reg [611:0] l2a_request; - output reg [511:0] l2a_data_from_memory; - output reg l2a_l2_fill; - output reg l2a_restarted_flush; - input l2bi_request_valid; - input wire [611:0] l2bi_request; - input wire [511:0] l2bi_data_from_memory; - input l2bi_stall; - input l2bi_collided_miss; - wire can_accept_request; - wire [611:0] grant_request; - wire [0:0] grant_oh; - wire restarted_flush; - assign can_accept_request = !l2bi_request_valid && !l2bi_stall; - assign restarted_flush = l2bi_request[605-:3] == 3'd4; - genvar _gv_request_idx_2; - generate - for (_gv_request_idx_2 = 0; _gv_request_idx_2 < 1; _gv_request_idx_2 = _gv_request_idx_2 + 1) begin : handshake_gen - localparam request_idx = _gv_request_idx_2; - assign l2_ready[request_idx] = grant_oh[request_idx] && can_accept_request; - end - endgenerate - localparam defines_CORE_ID_WIDTH = 0; - generate - if (1) begin : genblk2 - assign grant_oh[0] = l2i_request_valid[0]; - assign grant_request = l2i_request[0+:612]; - end - endgenerate - always @(posedge clk) begin - l2a_data_from_memory <= l2bi_data_from_memory; - if (l2bi_request_valid) begin - l2a_request <= l2bi_request; - l2a_l2_fill <= !l2bi_collided_miss && !restarted_flush; - l2a_restarted_flush <= restarted_flush; - end - else begin - l2a_request <= grant_request; - l2a_l2_fill <= 0; - l2a_restarted_flush <= 0; - end - end - always @(posedge clk or posedge reset) - if (reset) - l2a_request_valid <= 0; - else if (l2bi_request_valid) - l2a_request_valid <= 1; - else if (|l2i_request_valid && can_accept_request) - l2a_request_valid <= 1; - else - l2a_request_valid <= 0; -endmodule -module l2_cache_pending_miss_cam ( - clk, - reset, - request_valid, - request_addr, - enqueue_fill_request, - l2r_l2_fill, - duplicate_request -); - parameter QUEUE_SIZE = 16; - parameter QUEUE_ADDR_WIDTH = $clog2(QUEUE_SIZE); - input clk; - input reset; - input request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [25:0] request_addr; - input enqueue_fill_request; - input l2r_l2_fill; - output wire duplicate_request; - wire [QUEUE_ADDR_WIDTH - 1:0] cam_hit_entry; - wire cam_hit; - reg [QUEUE_SIZE - 1:0] empty_entries; - wire [QUEUE_SIZE - 1:0] next_empty_oh; - wire [QUEUE_ADDR_WIDTH - 1:0] next_empty; - function automatic signed [QUEUE_SIZE - 1:0] sv2v_cast_C61BA_signed; - input reg signed [QUEUE_SIZE - 1:0] inp; - sv2v_cast_C61BA_signed = inp; - endfunction - assign next_empty_oh = empty_entries & ~(empty_entries - sv2v_cast_C61BA_signed(1)); - oh_to_idx #(.NUM_SIGNALS(QUEUE_SIZE)) oh_to_idx_next_empty( - .one_hot(next_empty_oh), - .index(next_empty) - ); - assign duplicate_request = cam_hit && !l2r_l2_fill; - cam #( - .NUM_ENTRIES(QUEUE_SIZE), - .KEY_WIDTH(26) - ) cam_pending_miss( - .clk(clk), - .reset(reset), - .lookup_key(request_addr), - .lookup_idx(cam_hit_entry), - .lookup_hit(cam_hit), - .update_en(request_valid && (cam_hit ? l2r_l2_fill : enqueue_fill_request)), - .update_key(request_addr), - .update_idx((cam_hit ? cam_hit_entry : next_empty)), - .update_valid((cam_hit ? !l2r_l2_fill : enqueue_fill_request)) - ); - always @(posedge clk or posedge reset) - if (reset) - empty_entries <= {QUEUE_SIZE {1'b1}}; - else if (cam_hit & l2r_l2_fill) - empty_entries[cam_hit_entry] <= 1'b1; - else if (!cam_hit && enqueue_fill_request) - empty_entries[next_empty] <= 1'b0; -endmodule -module l2_cache_read_stage ( - clk, - reset, - l2t_request_valid, - l2t_request, - l2t_valid, - l2t_tag, - l2t_dirty, - l2t_l2_fill, - l2t_restarted_flush, - l2t_fill_way, - l2t_data_from_memory, - l2r_update_dirty_en, - l2r_update_dirty_set, - l2r_update_dirty_value, - l2r_update_tag_en, - l2r_update_tag_set, - l2r_update_tag_valid, - l2r_update_tag_value, - l2r_update_lru_en, - l2r_update_lru_hit_way, - l2u_write_en, - l2u_write_addr, - l2u_write_data, - l2r_request_valid, - l2r_request, - l2r_data, - l2r_cache_hit, - l2r_hit_cache_idx, - l2r_l2_fill, - l2r_restarted_flush, - l2r_data_from_memory, - l2r_store_sync_success, - l2r_writeback_tag, - l2r_needs_writeback, - l2r_perf_l2_miss, - l2r_perf_l2_hit -); - input clk; - input reset; - input l2t_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2t_request; - input [0:7] l2t_valid; - input wire [143:0] l2t_tag; - input [0:7] l2t_dirty; - input l2t_l2_fill; - input l2t_restarted_flush; - input wire [2:0] l2t_fill_way; - input wire [511:0] l2t_data_from_memory; - output wire [7:0] l2r_update_dirty_en; - output wire [7:0] l2r_update_dirty_set; - output wire l2r_update_dirty_value; - output wire [7:0] l2r_update_tag_en; - output wire [7:0] l2r_update_tag_set; - output wire l2r_update_tag_valid; - output wire [17:0] l2r_update_tag_value; - output wire l2r_update_lru_en; - output wire [2:0] l2r_update_lru_hit_way; - input l2u_write_en; - input [10:0] l2u_write_addr; - input wire [511:0] l2u_write_data; - output reg l2r_request_valid; - output reg [611:0] l2r_request; - output wire [511:0] l2r_data; - output reg l2r_cache_hit; - output reg [10:0] l2r_hit_cache_idx; - output reg l2r_l2_fill; - output reg l2r_restarted_flush; - output reg [511:0] l2r_data_from_memory; - output reg l2r_store_sync_success; - output reg [17:0] l2r_writeback_tag; - output reg l2r_needs_writeback; - output reg l2r_perf_l2_miss; - output reg l2r_perf_l2_hit; - localparam defines_TOTAL_THREADS = 4; - localparam GLOBAL_THREAD_IDX_WIDTH = 2; - reg [25:0] load_sync_address [0:3]; - reg load_sync_address_valid [0:3]; - wire can_store_sync; - wire [7:0] hit_way_oh; - wire cache_hit; - wire [2:0] hit_way_idx; - wire [10:0] read_address; - wire load; - wire store; - wire update_dirty; - wire update_tag; - wire flush_first_pass; - wire [2:0] writeback_way; - wire hit_or_miss; - wire dinvalidate; - wire [2:0] tag_update_way; - wire [1:0] request_sync_slot; - assign load = (l2t_request[605-:3] == 3'd0) || (l2t_request[605-:3] == 3'd1); - assign store = (l2t_request[605-:3] == 3'd2) || (l2t_request[605-:3] == 3'd3); - assign writeback_way = (l2t_request[605-:3] == 3'd4 ? hit_way_idx : l2t_fill_way); - assign dinvalidate = l2t_request[605-:3] == 3'd6; - genvar _gv_way_idx_6; - generate - for (_gv_way_idx_6 = 0; _gv_way_idx_6 < 8; _gv_way_idx_6 = _gv_way_idx_6 + 1) begin : hit_way_gen - localparam way_idx = _gv_way_idx_6; - assign hit_way_oh[way_idx] = (l2t_request[601-:18] == l2t_tag[0 + ((7 - way_idx) * 18)+:18]) && l2t_valid[way_idx]; - end - endgenerate - assign cache_hit = |hit_way_oh && l2t_request_valid; - oh_to_idx #(.NUM_SIGNALS(8)) oh_to_idx_hit_way( - .one_hot(hit_way_oh), - .index(hit_way_idx) - ); - assign read_address = {(l2t_l2_fill ? l2t_fill_way : hit_way_idx), l2t_request[583-:8]}; - fakeram_1r1w_512x2048 #( - .DATA_WIDTH(defines_CACHE_LINE_BITS), - .SIZE(2048), - .READ_DURING_WRITE("NEW_DATA") - ) sram_l2_data( - .read_en(l2t_request_valid && (cache_hit || l2t_l2_fill)), - .read_addr(read_address), - .read_data(l2r_data), - .write_en(l2u_write_en), - .write_addr(l2u_write_addr), - .write_data(l2u_write_data), - .* - ); - assign flush_first_pass = (l2t_request[605-:3] == 3'd4) && !l2t_restarted_flush; - assign update_dirty = l2t_request_valid && (l2t_l2_fill || (cache_hit && (store || flush_first_pass))); - assign l2r_update_dirty_set = l2t_request[583-:8]; - assign l2r_update_dirty_value = store; - genvar _gv_dirty_update_idx_1; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - generate - for (_gv_dirty_update_idx_1 = 0; _gv_dirty_update_idx_1 < 8; _gv_dirty_update_idx_1 = _gv_dirty_update_idx_1 + 1) begin : dirty_update_gen - localparam dirty_update_idx = _gv_dirty_update_idx_1; - assign l2r_update_dirty_en[dirty_update_idx] = update_dirty && (l2t_l2_fill ? l2t_fill_way == sv2v_cast_3(dirty_update_idx) : hit_way_oh[dirty_update_idx]); - end - endgenerate - assign update_tag = l2t_l2_fill || (cache_hit && dinvalidate); - assign tag_update_way = (l2t_l2_fill ? l2t_fill_way : hit_way_idx); - genvar _gv_tag_idx_1; - generate - for (_gv_tag_idx_1 = 0; _gv_tag_idx_1 < 8; _gv_tag_idx_1 = _gv_tag_idx_1 + 1) begin : tag_update_gen - localparam tag_idx = _gv_tag_idx_1; - assign l2r_update_tag_en[tag_idx] = update_tag && (tag_update_way == sv2v_cast_3(tag_idx)); - end - endgenerate - assign l2r_update_tag_set = l2t_request[583-:8]; - assign l2r_update_tag_valid = !dinvalidate; - assign l2r_update_tag_value = l2t_request[601-:18]; - assign l2r_update_lru_en = cache_hit && (load || store); - assign l2r_update_lru_hit_way = hit_way_idx; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - assign request_sync_slot = sv2v_cast_2({l2t_request[611-:4], l2t_request[607-:2]}); - assign can_store_sync = ((load_sync_address[request_sync_slot] == {l2t_request[601-:18], l2t_request[583-:8]}) && load_sync_address_valid[request_sync_slot]) && (l2t_request[605-:3] == 3'd3); - assign hit_or_miss = (l2t_request_valid && (((l2t_request[605-:3] == 3'd2) || can_store_sync) || (l2t_request[605-:3] == 3'd0))) && !l2t_l2_fill; - always @(posedge clk) begin - l2r_request <= l2t_request; - l2r_cache_hit <= cache_hit; - l2r_l2_fill <= l2t_l2_fill; - l2r_writeback_tag <= l2t_tag[0 + ((7 - writeback_way) * 18)+:18]; - l2r_needs_writeback <= l2t_dirty[writeback_way] && l2t_valid[writeback_way]; - l2r_data_from_memory <= l2t_data_from_memory; - l2r_hit_cache_idx <= read_address; - l2r_restarted_flush <= l2t_restarted_flush; - end - always @(posedge clk or posedge reset) - if (reset) begin - begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < defines_TOTAL_THREADS; i = i + 1) - begin - load_sync_address_valid[i] <= 1'sb0; - load_sync_address[i] <= 1'sb0; - end - end - l2r_perf_l2_hit <= 1'sb0; - l2r_perf_l2_miss <= 1'sb0; - l2r_request_valid <= 1'sb0; - l2r_store_sync_success <= 1'sb0; - end - else begin - l2r_request_valid <= l2t_request_valid; - if (l2t_request_valid && (cache_hit || l2t_l2_fill)) begin - (* full_case, parallel_case *) - case (l2t_request[605-:3]) - 3'd1: begin - load_sync_address[request_sync_slot] <= {l2t_request[601-:18], l2t_request[583-:8]}; - load_sync_address_valid[request_sync_slot] <= 1; - end - 3'd2, 3'd3: - if ((l2t_request[605-:3] == 3'd2) || can_store_sync) begin : sv2v_autoblock_2 - reg signed [31:0] entry_idx; - for (entry_idx = 0; entry_idx < defines_TOTAL_THREADS; entry_idx = entry_idx + 1) - if (load_sync_address[entry_idx] == {l2t_request[601-:18], l2t_request[583-:8]}) - load_sync_address_valid[entry_idx] <= 0; - end - default: - ; - endcase - l2r_store_sync_success <= can_store_sync; - end - else - l2r_store_sync_success <= 0; - l2r_perf_l2_miss <= hit_or_miss && !(|hit_way_oh); - l2r_perf_l2_hit <= hit_or_miss && |hit_way_oh; - end -endmodule -module l2_cache_tag_stage ( - clk, - reset, - l2a_request_valid, - l2a_request, - l2a_data_from_memory, - l2a_l2_fill, - l2a_restarted_flush, - l2r_update_dirty_en, - l2r_update_dirty_set, - l2r_update_dirty_value, - l2r_update_tag_en, - l2r_update_tag_set, - l2r_update_tag_valid, - l2r_update_tag_value, - l2r_update_lru_en, - l2r_update_lru_hit_way, - l2t_request_valid, - l2t_request, - l2t_valid, - l2t_tag, - l2t_dirty, - l2t_l2_fill, - l2t_fill_way, - l2t_data_from_memory, - l2t_restarted_flush -); - input clk; - input reset; - input l2a_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2a_request; - input wire [511:0] l2a_data_from_memory; - input l2a_l2_fill; - input l2a_restarted_flush; - input [7:0] l2r_update_dirty_en; - input wire [7:0] l2r_update_dirty_set; - input l2r_update_dirty_value; - input [7:0] l2r_update_tag_en; - input wire [7:0] l2r_update_tag_set; - input l2r_update_tag_valid; - input wire [17:0] l2r_update_tag_value; - input l2r_update_lru_en; - input wire [2:0] l2r_update_lru_hit_way; - output reg l2t_request_valid; - output reg [611:0] l2t_request; - output reg [0:7] l2t_valid; - output wire [143:0] l2t_tag; - output wire [0:7] l2t_dirty; - output reg l2t_l2_fill; - output wire [2:0] l2t_fill_way; - output reg [511:0] l2t_data_from_memory; - output reg l2t_restarted_flush; - cache_lru #( - .NUM_SETS(256), - .NUM_WAYS(8) - ) cache_lru( - .fill_en(l2a_l2_fill), - .fill_set(l2a_request[583-:8]), - .fill_way(l2t_fill_way), - .access_en(l2a_request_valid), - .access_set(l2a_request[583-:8]), - .update_en(l2r_update_lru_en), - .update_way(l2r_update_lru_hit_way), - .clk(clk), - .reset(reset) - ); - genvar _gv_way_idx_7; - generate - for (_gv_way_idx_7 = 0; _gv_way_idx_7 < 8; _gv_way_idx_7 = _gv_way_idx_7 + 1) begin : way_tags_gen - localparam way_idx = _gv_way_idx_7; - reg line_valid [0:255]; - fakeram_1r1w_18x256 #( - .DATA_WIDTH(18), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) sram_tags( - .read_en(l2a_request_valid), - .read_addr(l2a_request[583-:8]), - .read_data(l2t_tag[0 + ((7 - way_idx) * 18)+:18]), - .write_en(l2r_update_tag_en[way_idx]), - .write_addr(l2r_update_tag_set), - .write_data(l2r_update_tag_value), - .* - ); - fakeram_1r1w_1x256 #( - .DATA_WIDTH(1), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) sram_dirty_flags( - .read_en(l2a_request_valid), - .read_addr(l2a_request[583-:8]), - .read_data(l2t_dirty[way_idx]), - .write_en(l2r_update_dirty_en[way_idx]), - .write_addr(l2r_update_dirty_set), - .write_data(l2r_update_dirty_value), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < 256; set_idx = set_idx + 1) - line_valid[set_idx] <= 0; - end - else if (l2r_update_tag_en[way_idx]) - line_valid[l2r_update_tag_set] <= l2r_update_tag_valid; - always @(posedge clk) - if (l2a_request_valid) begin - if (l2r_update_tag_en[way_idx] && (l2r_update_tag_set == l2a_request[583-:8])) - l2t_valid[way_idx] <= l2r_update_tag_valid; - else - l2t_valid[way_idx] <= line_valid[l2a_request[583-:8]]; - end - end - endgenerate - always @(posedge clk) begin - l2t_data_from_memory <= l2a_data_from_memory; - l2t_request <= l2a_request; - l2t_l2_fill <= l2a_l2_fill; - l2t_restarted_flush <= l2a_restarted_flush; - end - always @(posedge clk or posedge reset) - if (reset) - l2t_request_valid <= 0; - else - l2t_request_valid <= l2a_request_valid; -endmodule -module l2_cache_update_stage ( - clk, - reset, - l2r_request_valid, - l2r_request, - l2r_data, - l2r_cache_hit, - l2r_hit_cache_idx, - l2r_l2_fill, - l2r_restarted_flush, - l2r_data_from_memory, - l2r_store_sync_success, - l2r_needs_writeback, - l2u_write_en, - l2u_write_addr, - l2u_write_data, - l2_response_valid, - l2_response -); - reg _sv2v_0; - input clk; - input reset; - input l2r_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2r_request; - input wire [511:0] l2r_data; - input l2r_cache_hit; - input wire [10:0] l2r_hit_cache_idx; - input l2r_l2_fill; - input l2r_restarted_flush; - input wire [511:0] l2r_data_from_memory; - input l2r_store_sync_success; - input l2r_needs_writeback; - output wire l2u_write_en; - output wire [10:0] l2u_write_addr; - output wire [511:0] l2u_write_data; - output reg l2_response_valid; - output reg [548:0] l2_response; - wire [511:0] original_data; - wire update_data; - reg [2:0] response_type; - wire completed_flush; - assign original_data = (l2r_l2_fill ? l2r_data_from_memory : l2r_data); - assign update_data = (l2r_request[605-:3] == 3'd2) || ((l2r_request[605-:3] == 3'd3) && l2r_store_sync_success); - genvar _gv_byte_lane_1; - generate - for (_gv_byte_lane_1 = 0; _gv_byte_lane_1 < defines_CACHE_LINE_BYTES; _gv_byte_lane_1 = _gv_byte_lane_1 + 1) begin : lane_mask_gen - localparam byte_lane = _gv_byte_lane_1; - assign l2u_write_data[byte_lane * 8+:8] = (l2r_request[512 + byte_lane] && update_data ? l2r_request[0 + (byte_lane * 8)+:8] : original_data[byte_lane * 8+:8]); - end - endgenerate - assign l2u_write_en = l2r_request_valid && (l2r_l2_fill || (l2r_cache_hit && ((l2r_request[605-:3] == 3'd2) || (l2r_request[605-:3] == 3'd3)))); - assign l2u_write_addr = l2r_hit_cache_idx; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (l2r_request[605-:3]) - 3'd0, 3'd1: response_type = 3'd0; - 3'd2, 3'd3: response_type = 3'd1; - 3'd4: response_type = 3'd2; - 3'd5: response_type = 3'd3; - 3'd6: response_type = 3'd4; - default: response_type = 3'd0; - endcase - end - assign completed_flush = (l2r_request[605-:3] == 3'd4) && ((l2r_restarted_flush || !l2r_cache_hit) || !l2r_needs_writeback); - always @(posedge clk or posedge reset) - if (reset) - l2_response_valid <= 0; - else if (l2r_request_valid && (((((l2r_cache_hit && (l2r_request[605-:3] != 3'd4)) || l2r_l2_fill) || completed_flush) || (l2r_request[605-:3] == 3'd6)) || (l2r_request[605-:3] == 3'd5))) - l2_response_valid <= 1; - else - l2_response_valid <= 0; - always @(posedge clk) begin - l2_response[548] <= (l2r_request[605-:3] == 3'd3 ? l2r_store_sync_success : 1'b1); - l2_response[547-:4] <= l2r_request[611-:4]; - l2_response[543-:2] <= l2r_request[607-:2]; - l2_response[541-:3] <= response_type; - l2_response[538] <= l2r_request[602]; - l2_response[511-:defines_CACHE_LINE_BITS] <= l2u_write_data; - l2_response[537-:26] <= l2r_request[601-:26]; - end - initial _sv2v_0 = 0; -endmodule -module oh_to_idx ( - one_hot, - index -); - reg _sv2v_0; - parameter NUM_SIGNALS = 4; - parameter DIRECTION = "LSB0"; - parameter INDEX_WIDTH = $clog2(NUM_SIGNALS); - input [NUM_SIGNALS - 1:0] one_hot; - output reg [INDEX_WIDTH - 1:0] index; - function automatic signed [INDEX_WIDTH - 1:0] sv2v_cast_BBE12_signed; - input reg signed [INDEX_WIDTH - 1:0] inp; - sv2v_cast_BBE12_signed = inp; - endfunction - always @(*) begin : convert - if (_sv2v_0) - ; - index = 0; - begin : sv2v_autoblock_1 - reg signed [31:0] oh_index; - for (oh_index = 0; oh_index < NUM_SIGNALS; oh_index = oh_index + 1) - if (one_hot[oh_index]) begin - if (DIRECTION == "LSB0") - index = index | oh_index[INDEX_WIDTH - 1:0]; - else - index = index | sv2v_cast_BBE12_signed((NUM_SIGNALS - oh_index) - 1); - end - end - end - initial _sv2v_0 = 0; -endmodule -module operand_fetch_stage ( - clk, - reset, - ts_instruction_valid, - ts_instruction, - ts_thread_idx, - ts_subcycle, - of_operand1, - of_operand2, - of_mask_value, - of_store_value, - of_instruction, - of_instruction_valid, - of_thread_idx, - of_subcycle, - wb_rollback_en, - wb_rollback_thread_idx, - wb_writeback_en, - wb_writeback_thread_idx, - wb_writeback_vector, - wb_writeback_value, - wb_writeback_mask, - wb_writeback_reg -); - reg _sv2v_0; - input clk; - input reset; - input ts_instruction_valid; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] ts_instruction; - input wire [1:0] ts_thread_idx; - input wire [3:0] ts_subcycle; - output reg [511:0] of_operand1; - output reg [511:0] of_operand2; - output reg [15:0] of_mask_value; - output wire [511:0] of_store_value; - output reg [141:0] of_instruction; - output reg of_instruction_valid; - output reg [1:0] of_thread_idx; - output reg [3:0] of_subcycle; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wb_writeback_en; - input wire [1:0] wb_writeback_thread_idx; - input wb_writeback_vector; - input wire [511:0] wb_writeback_value; - input wire [15:0] wb_writeback_mask; - input wire [4:0] wb_writeback_reg; - wire [31:0] scalar_val1; - wire [31:0] scalar_val2; - wire [511:0] vector_val1; - wire [511:0] vector_val2; - fakeram_2r1w_32x128 #( - .DATA_WIDTH(32), - .SIZE(128), - .READ_DURING_WRITE("DONT_CARE") - ) scalar_registers( - .read1_en(ts_instruction_valid && ts_instruction[101]), - .read1_addr({ts_thread_idx, ts_instruction[100-:5]}), - .read1_data(scalar_val1), - .read2_en(ts_instruction_valid && ts_instruction[95]), - .read2_addr({ts_thread_idx, ts_instruction[94-:5]}), - .read2_data(scalar_val2), - .write_en(wb_writeback_en && !wb_writeback_vector), - .write_addr({wb_writeback_thread_idx, wb_writeback_reg}), - .write_data(wb_writeback_value[0+:32]), - .* - ); - genvar _gv_lane_2; - generate - for (_gv_lane_2 = 0; _gv_lane_2 < defines_NUM_VECTOR_LANES; _gv_lane_2 = _gv_lane_2 + 1) begin : vector_lane_gen - localparam lane = _gv_lane_2; - fakeram_2r1w_32x128 #( - .DATA_WIDTH(32), - .SIZE(128), - .READ_DURING_WRITE("DONT_CARE") - ) vector_registers( - .read1_en(ts_instruction[89]), - .read1_addr({ts_thread_idx, ts_instruction[88-:5]}), - .read1_data(vector_val1[lane * 32+:32]), - .read2_en(ts_instruction[83]), - .read2_addr({ts_thread_idx, ts_instruction[82-:5]}), - .read2_data(vector_val2[lane * 32+:32]), - .write_en((wb_writeback_en && wb_writeback_vector) && wb_writeback_mask[(defines_NUM_VECTOR_LANES - lane) - 1]), - .write_addr({wb_writeback_thread_idx, wb_writeback_reg}), - .write_data(wb_writeback_value[lane * 32+:32]), - .* - ); - end - endgenerate - always @(posedge clk or posedge reset) - if (reset) - of_instruction_valid <= 0; - else - of_instruction_valid <= ts_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != ts_thread_idx)); - always @(posedge clk) begin - of_instruction <= ts_instruction; - of_thread_idx <= ts_thread_idx; - of_subcycle <= ts_subcycle; - end - assign of_store_value = (of_instruction[59] ? vector_val2 : {{15 {32'd0}}, scalar_val2}); - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (of_instruction[62]) - 1'd0: of_operand1 = vector_val1; - default: of_operand1 = {defines_NUM_VECTOR_LANES {scalar_val1}}; - endcase - (* full_case, parallel_case *) - case (of_instruction[61-:2]) - 2'd0: of_operand2 = {defines_NUM_VECTOR_LANES {scalar_val2}}; - 2'd1: of_operand2 = vector_val2; - default: of_operand2 = {defines_NUM_VECTOR_LANES {of_instruction[58-:32]}}; - endcase - (* full_case, parallel_case *) - case (of_instruction[64-:2]) - 2'd0: of_mask_value = scalar_val1[15:0]; - 2'd1: of_mask_value = scalar_val2[15:0]; - default: of_mask_value = {defines_NUM_VECTOR_LANES {1'b1}}; - endcase - end - initial _sv2v_0 = 0; -endmodule -module performance_counters ( - clk, - reset, - perf_events, - perf_event_select, - perf_event_count -); - parameter NUM_EVENTS = 1; - parameter EVENT_IDX_WIDTH = $clog2(NUM_EVENTS); - parameter NUM_COUNTERS = 2; - parameter COUNTER_IDX_WIDTH = $clog2(NUM_COUNTERS); - input clk; - input reset; - input [NUM_EVENTS - 1:0] perf_events; - input [(NUM_COUNTERS * EVENT_IDX_WIDTH) - 1:0] perf_event_select; - output reg [(NUM_COUNTERS * 64) - 1:0] perf_event_count; - always @(posedge clk or posedge reset) begin : update - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < NUM_COUNTERS; i = i + 1) - perf_event_count[i * 64+:64] <= 0; - end - else begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 0; i < NUM_COUNTERS; i = i + 1) - if (perf_events[perf_event_select[i * EVENT_IDX_WIDTH+:EVENT_IDX_WIDTH]]) - perf_event_count[i * 64+:64] <= perf_event_count[i * 64+:64] + 1; - end - end -endmodule -module reciprocal_rom ( - significand, - reciprocal_estimate -); - reg _sv2v_0; - input [5:0] significand; - output reg [5:0] reciprocal_estimate; - always @(*) begin - if (_sv2v_0) - ; - case (significand) - 6'h00: reciprocal_estimate = 6'h00; - 6'h01: reciprocal_estimate = 6'h3e; - 6'h02: reciprocal_estimate = 6'h3c; - 6'h03: reciprocal_estimate = 6'h3a; - 6'h04: reciprocal_estimate = 6'h38; - 6'h05: reciprocal_estimate = 6'h36; - 6'h06: reciprocal_estimate = 6'h35; - 6'h07: reciprocal_estimate = 6'h33; - 6'h08: reciprocal_estimate = 6'h31; - 6'h09: reciprocal_estimate = 6'h30; - 6'h0a: reciprocal_estimate = 6'h2e; - 6'h0b: reciprocal_estimate = 6'h2d; - 6'h0c: reciprocal_estimate = 6'h2b; - 6'h0d: reciprocal_estimate = 6'h2a; - 6'h0e: reciprocal_estimate = 6'h29; - 6'h0f: reciprocal_estimate = 6'h27; - 6'h10: reciprocal_estimate = 6'h26; - 6'h11: reciprocal_estimate = 6'h25; - 6'h12: reciprocal_estimate = 6'h23; - 6'h13: reciprocal_estimate = 6'h22; - 6'h14: reciprocal_estimate = 6'h21; - 6'h15: reciprocal_estimate = 6'h20; - 6'h16: reciprocal_estimate = 6'h1f; - 6'h17: reciprocal_estimate = 6'h1e; - 6'h18: reciprocal_estimate = 6'h1d; - 6'h19: reciprocal_estimate = 6'h1c; - 6'h1a: reciprocal_estimate = 6'h1b; - 6'h1b: reciprocal_estimate = 6'h1a; - 6'h1c: reciprocal_estimate = 6'h19; - 6'h1d: reciprocal_estimate = 6'h18; - 6'h1e: reciprocal_estimate = 6'h17; - 6'h1f: reciprocal_estimate = 6'h16; - 6'h20: reciprocal_estimate = 6'h15; - 6'h21: reciprocal_estimate = 6'h14; - 6'h22: reciprocal_estimate = 6'h13; - 6'h23: reciprocal_estimate = 6'h12; - 6'h24: reciprocal_estimate = 6'h11; - 6'h25: reciprocal_estimate = 6'h11; - 6'h26: reciprocal_estimate = 6'h10; - 6'h27: reciprocal_estimate = 6'h0f; - 6'h28: reciprocal_estimate = 6'h0e; - 6'h29: reciprocal_estimate = 6'h0e; - 6'h2a: reciprocal_estimate = 6'h0d; - 6'h2b: reciprocal_estimate = 6'h0c; - 6'h2c: reciprocal_estimate = 6'h0b; - 6'h2d: reciprocal_estimate = 6'h0b; - 6'h2e: reciprocal_estimate = 6'h0a; - 6'h2f: reciprocal_estimate = 6'h09; - 6'h30: reciprocal_estimate = 6'h09; - 6'h31: reciprocal_estimate = 6'h08; - 6'h32: reciprocal_estimate = 6'h07; - 6'h33: reciprocal_estimate = 6'h07; - 6'h34: reciprocal_estimate = 6'h06; - 6'h35: reciprocal_estimate = 6'h06; - 6'h36: reciprocal_estimate = 6'h05; - 6'h37: reciprocal_estimate = 6'h04; - 6'h38: reciprocal_estimate = 6'h04; - 6'h39: reciprocal_estimate = 6'h03; - 6'h3a: reciprocal_estimate = 6'h03; - 6'h3b: reciprocal_estimate = 6'h02; - 6'h3c: reciprocal_estimate = 6'h02; - 6'h3d: reciprocal_estimate = 6'h01; - 6'h3e: reciprocal_estimate = 6'h01; - 6'h3f: reciprocal_estimate = 6'h00; - default: reciprocal_estimate = 6'h00; - endcase - end - initial _sv2v_0 = 0; -endmodule -module rr_arbiter ( - clk, - reset, - request, - update_lru, - grant_oh -); - reg _sv2v_0; - parameter NUM_REQUESTERS = 4; - input clk; - input reset; - input [NUM_REQUESTERS - 1:0] request; - input update_lru; - output reg [NUM_REQUESTERS - 1:0] grant_oh; - wire [NUM_REQUESTERS - 1:0] priority_oh_nxt; - reg [NUM_REQUESTERS - 1:0] priority_oh; - localparam BIT_IDX_WIDTH = $clog2(NUM_REQUESTERS); - always @(*) begin - if (_sv2v_0) - ; - begin : sv2v_autoblock_1 - reg signed [31:0] grant_idx; - for (grant_idx = 0; grant_idx < NUM_REQUESTERS; grant_idx = grant_idx + 1) - begin - grant_oh[grant_idx] = 0; - begin : sv2v_autoblock_2 - reg signed [31:0] priority_idx; - for (priority_idx = 0; priority_idx < NUM_REQUESTERS; priority_idx = priority_idx + 1) - begin : sv2v_autoblock_3 - reg granted; - granted = request[grant_idx] & priority_oh[priority_idx]; - begin : sv2v_autoblock_4 - reg [BIT_IDX_WIDTH - 1:0] bit_idx; - for (bit_idx = priority_idx[BIT_IDX_WIDTH - 1:0] % NUM_REQUESTERS; bit_idx != grant_idx[BIT_IDX_WIDTH - 1:0]; bit_idx = (bit_idx + 1) % NUM_REQUESTERS) - granted = granted & !request[bit_idx]; - end - grant_oh[grant_idx] = grant_oh[grant_idx] | granted; - end - end - end - end - end - assign priority_oh_nxt = {grant_oh[NUM_REQUESTERS - 2:0], grant_oh[NUM_REQUESTERS - 1]}; - always @(posedge clk or posedge reset) - if (reset) - priority_oh <= 1; - else if ((request != 0) && update_lru) - priority_oh <= priority_oh_nxt; - initial _sv2v_0 = 0; -endmodule -module scoreboard ( - clk, - reset, - next_instruction, - scoreboard_can_issue, - will_issue, - writeback_en, - wb_writeback_vector, - wb_writeback_reg, - rollback_en, - wb_rollback_pipeline -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] next_instruction; - output wire scoreboard_can_issue; - input will_issue; - input writeback_en; - input wb_writeback_vector; - input wire [4:0] wb_writeback_reg; - input rollback_en; - input wire [1:0] wb_rollback_pipeline; - localparam defines_NUM_REGISTERS = 32; - localparam SCOREBOARD_ENTRIES = 64; - localparam ROLLBACK_STAGES = 4; - reg [3:0] has_writeback; - reg [5:0] writeback_reg [0:3]; - reg [63:0] scoreboard_regs; - wire [63:0] scoreboard_regs_nxt; - reg [63:0] dest_bitmap; - reg [63:0] dep_bitmap; - reg [63:0] rollback_bitmap; - reg [63:0] writeback_bitmap; - wire [63:0] clear_bitmap; - wire [63:0] set_bitmap; - always @(*) begin - if (_sv2v_0) - ; - rollback_bitmap = 0; - if (rollback_en) begin - begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < 3; i = i + 1) - if (has_writeback[i]) - rollback_bitmap[writeback_reg[i]] = 1; - end - if (has_writeback[3] && (wb_rollback_pipeline == 2'd0)) - rollback_bitmap[writeback_reg[3]] = 1; - end - end - always @(*) begin - if (_sv2v_0) - ; - dep_bitmap = 0; - if (next_instruction[77]) begin - if (next_instruction[76]) - dep_bitmap[{1'b1, next_instruction[75-:5]}] = 1; - else - dep_bitmap[{1'b0, next_instruction[75-:5]}] = 1; - end - if (next_instruction[101]) - dep_bitmap[{1'b0, next_instruction[100-:5]}] = 1; - if (next_instruction[95]) - dep_bitmap[{1'b0, next_instruction[94-:5]}] = 1; - if (next_instruction[89]) - dep_bitmap[{1'b1, next_instruction[88-:5]}] = 1; - if (next_instruction[83]) - dep_bitmap[{1'b1, next_instruction[82-:5]}] = 1; - end - always @(*) begin - if (_sv2v_0) - ; - dest_bitmap = 0; - if (next_instruction[77]) begin - if (next_instruction[76]) - dest_bitmap[{1'b1, next_instruction[75-:5]}] = 1; - else - dest_bitmap[{1'b0, next_instruction[75-:5]}] = 1; - end - end - always @(*) begin - if (_sv2v_0) - ; - writeback_bitmap = 0; - if (writeback_en) begin - if (wb_writeback_vector) - writeback_bitmap[{1'b1, wb_writeback_reg}] = 1; - else - writeback_bitmap[{1'b0, wb_writeback_reg}] = 1; - end - end - assign clear_bitmap = rollback_bitmap | writeback_bitmap; - assign set_bitmap = dest_bitmap & {SCOREBOARD_ENTRIES {will_issue}}; - assign scoreboard_regs_nxt = (scoreboard_regs & ~clear_bitmap) | set_bitmap; - assign scoreboard_can_issue = (scoreboard_regs & dep_bitmap) == 0; - always @(posedge clk or posedge reset) - if (reset) begin - scoreboard_regs <= 1'sb0; - has_writeback <= 1'sb0; - end - else begin - scoreboard_regs <= scoreboard_regs_nxt; - has_writeback <= {has_writeback[2:0], will_issue && next_instruction[77]}; - end - always @(posedge clk) begin - if (will_issue) - writeback_reg[0] <= {next_instruction[76], next_instruction[75-:5]}; - begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 1; i < ROLLBACK_STAGES; i = i + 1) - writeback_reg[i] <= writeback_reg[i - 1]; - end - end - initial _sv2v_0 = 0; -endmodule -module sync_fifo ( - clk, - reset, - flush_en, - full, - almost_full, - enqueue_en, - enqueue_value, - empty, - almost_empty, - dequeue_en, - dequeue_value -); - parameter WIDTH = 64; - parameter SIZE = 4; - parameter ALMOST_FULL_THRESHOLD = SIZE; - parameter ALMOST_EMPTY_THRESHOLD = 1; - input clk; - input reset; - input flush_en; - output wire full; - output wire almost_full; - input enqueue_en; - input [WIDTH - 1:0] enqueue_value; - output wire empty; - output wire almost_empty; - input dequeue_en; - output wire [WIDTH - 1:0] dequeue_value; - localparam ADDR_WIDTH = $clog2(SIZE); - reg [ADDR_WIDTH - 1:0] head; - reg [ADDR_WIDTH - 1:0] tail; - reg [ADDR_WIDTH:0] count; - reg [WIDTH - 1:0] data [0:SIZE - 1]; - function automatic signed [((ADDR_WIDTH + 0) >= 0 ? ADDR_WIDTH + 1 : 1 - (ADDR_WIDTH + 0)) - 1:0] sv2v_cast_D7FEC_signed; - input reg signed [((ADDR_WIDTH + 0) >= 0 ? ADDR_WIDTH + 1 : 1 - (ADDR_WIDTH + 0)) - 1:0] inp; - sv2v_cast_D7FEC_signed = inp; - endfunction - assign almost_full = count >= sv2v_cast_D7FEC_signed(ALMOST_FULL_THRESHOLD); - assign almost_empty = count <= sv2v_cast_D7FEC_signed(ALMOST_EMPTY_THRESHOLD); - assign full = count == SIZE; - assign empty = count == 0; - assign dequeue_value = data[head]; - always @(posedge clk or posedge reset) - if (reset) begin - head <= 0; - tail <= 0; - count <= 0; - end - else if (flush_en) begin - head <= 0; - tail <= 0; - count <= 0; - end - else begin - if (enqueue_en) begin - tail <= tail + 1; - data[tail] <= enqueue_value; - end - if (dequeue_en) - head <= head + 1; - if (enqueue_en && !dequeue_en) - count <= count + 1; - else if (dequeue_en && !enqueue_en) - count <= count - 1; - end -endmodule -module synchronizer ( - clk, - reset, - data_o, - data_i -); - parameter WIDTH = 1; - parameter RESET_STATE = 0; - input clk; - input reset; - output reg [WIDTH - 1:0] data_o; - input [WIDTH - 1:0] data_i; - reg [WIDTH - 1:0] sync0; - reg [WIDTH - 1:0] sync1; - function automatic signed [WIDTH - 1:0] sv2v_cast_E6D93_signed; - input reg signed [WIDTH - 1:0] inp; - sv2v_cast_E6D93_signed = inp; - endfunction - always @(posedge clk or posedge reset) - if (reset) begin - sync0 <= sv2v_cast_E6D93_signed(RESET_STATE); - sync1 <= sv2v_cast_E6D93_signed(RESET_STATE); - data_o <= sv2v_cast_E6D93_signed(RESET_STATE); - end - else begin - sync0 <= data_i; - sync1 <= sync0; - data_o <= sync1; - end -endmodule -module thread_select_stage ( - clk, - reset, - id_instruction, - id_instruction_valid, - id_thread_idx, - ts_fetch_en, - ts_instruction_valid, - ts_instruction, - ts_thread_idx, - ts_subcycle, - wb_writeback_en, - wb_writeback_thread_idx, - wb_writeback_vector, - wb_writeback_reg, - wb_writeback_last_subcycle, - wb_rollback_thread_idx, - wb_rollback_en, - wb_rollback_pipeline, - wb_rollback_subcycle, - thread_en, - wb_suspend_thread_oh, - l2i_dcache_wake_bitmap, - ior_wake_bitmap, - ts_perf_instruction_issue -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] id_instruction; - input id_instruction_valid; - input wire [1:0] id_thread_idx; - output wire [3:0] ts_fetch_en; - output reg ts_instruction_valid; - output reg [141:0] ts_instruction; - output reg [1:0] ts_thread_idx; - output reg [3:0] ts_subcycle; - input wb_writeback_en; - input wire [1:0] wb_writeback_thread_idx; - input wb_writeback_vector; - input wire [4:0] wb_writeback_reg; - input wb_writeback_last_subcycle; - input wire [1:0] wb_rollback_thread_idx; - input wb_rollback_en; - input wire [1:0] wb_rollback_pipeline; - input wire [3:0] wb_rollback_subcycle; - input wire [3:0] thread_en; - input wire [3:0] wb_suspend_thread_oh; - input wire [3:0] l2i_dcache_wake_bitmap; - input wire [3:0] ior_wake_bitmap; - output reg ts_perf_instruction_issue; - localparam THREAD_FIFO_SIZE = 8; - localparam WRITEBACK_ALLOC_STAGES = 4; - wire [141:0] thread_instr [0:3]; - wire [141:0] issue_instr; - reg [3:0] thread_blocked; - wire [3:0] can_issue_thread; - wire [3:0] thread_issue_oh; - wire [1:0] issue_thread_idx; - reg [3:0] writeback_allocate; - reg [3:0] writeback_allocate_nxt; - reg [3:0] current_subcycle [0:3]; - wire issue_last_subcycle [0:3]; - genvar _gv_thread_idx_6; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - function automatic [3:0] sv2v_cast_60D1B; - input reg [3:0] inp; - sv2v_cast_60D1B = inp; - endfunction - generate - for (_gv_thread_idx_6 = 0; _gv_thread_idx_6 < 4; _gv_thread_idx_6 = _gv_thread_idx_6 + 1) begin : thread_logic_gen - localparam thread_idx = _gv_thread_idx_6; - wire ififo_almost_full; - wire ififo_empty; - reg writeback_conflict; - wire rollback_this_thread; - wire enqueue_this_thread; - wire writeback_this_thread; - wire scoreboard_can_issue; - assign enqueue_this_thread = id_instruction_valid && (id_thread_idx == sv2v_cast_2(thread_idx)); - sync_fifo #( - .WIDTH(142), - .SIZE(THREAD_FIFO_SIZE), - .ALMOST_FULL_THRESHOLD(5) - ) instruction_fifo( - .flush_en(rollback_this_thread), - .full(), - .almost_full(ififo_almost_full), - .enqueue_en(enqueue_this_thread), - .enqueue_value(id_instruction), - .empty(ififo_empty), - .almost_empty(), - .dequeue_en(issue_last_subcycle[thread_idx]), - .dequeue_value(thread_instr[thread_idx]), - .clk(clk), - .reset(reset) - ); - assign writeback_this_thread = (wb_writeback_en && (wb_writeback_thread_idx == sv2v_cast_2(thread_idx))) && wb_writeback_last_subcycle; - assign rollback_this_thread = wb_rollback_en && (wb_rollback_thread_idx == sv2v_cast_2(thread_idx)); - scoreboard scoreboard( - .next_instruction(thread_instr[thread_idx]), - .will_issue(thread_issue_oh[thread_idx]), - .writeback_en(writeback_this_thread), - .rollback_en(rollback_this_thread), - .clk(clk), - .reset(reset), - .scoreboard_can_issue(scoreboard_can_issue), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_reg(wb_writeback_reg), - .wb_rollback_pipeline(wb_rollback_pipeline) - ); - assign ts_fetch_en[thread_idx] = !ififo_almost_full && thread_en[thread_idx]; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (thread_instr[thread_idx][21-:2]) - 2'd1: writeback_conflict = writeback_allocate[0]; - 2'd0: writeback_conflict = writeback_allocate[1]; - default: writeback_conflict = 0; - endcase - end - assign can_issue_thread[thread_idx] = ((((!ififo_empty && (scoreboard_can_issue || (current_subcycle[thread_idx] != 0))) && thread_en[thread_idx]) && !rollback_this_thread) && !writeback_conflict) && !thread_blocked[thread_idx]; - assign issue_last_subcycle[thread_idx] = thread_issue_oh[thread_idx] && (current_subcycle[thread_idx] == thread_instr[thread_idx][12-:4]); - always @(posedge clk or posedge reset) - if (reset) - current_subcycle[thread_idx] <= 0; - else if (wb_rollback_en && (wb_rollback_thread_idx == sv2v_cast_2(thread_idx))) - current_subcycle[thread_idx] <= wb_rollback_subcycle; - else if (issue_last_subcycle[thread_idx]) - current_subcycle[thread_idx] <= 0; - else if (thread_issue_oh[thread_idx]) - current_subcycle[thread_idx] <= current_subcycle[thread_idx] + sv2v_cast_60D1B(1); - end - endgenerate - always @(*) begin - if (_sv2v_0) - ; - writeback_allocate_nxt = {1'b0, writeback_allocate[3:1]}; - if (|thread_issue_oh) - (* full_case, parallel_case *) - case (issue_instr[21-:2]) - 2'd2: writeback_allocate_nxt[3] = 1'b1; - 2'd0: writeback_allocate_nxt[0] = 1'b1; - default: - ; - endcase - end - rr_arbiter #(.NUM_REQUESTERS(4)) thread_select_arbiter( - .request(can_issue_thread), - .update_lru(1'b1), - .grant_oh(thread_issue_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) thread_oh_to_idx( - .one_hot(thread_issue_oh), - .index(issue_thread_idx) - ); - assign issue_instr = thread_instr[issue_thread_idx]; - always @(posedge clk) begin - ts_instruction <= issue_instr; - ts_thread_idx <= issue_thread_idx; - ts_subcycle <= current_subcycle[issue_thread_idx]; - end - always @(posedge clk or posedge reset) - if (reset) begin - thread_blocked <= 1'sb0; - ts_instruction_valid <= 1'sb0; - ts_perf_instruction_issue <= 1'sb0; - writeback_allocate <= 1'sb0; - end - else begin - ts_instruction_valid <= |thread_issue_oh; - thread_blocked <= (thread_blocked | wb_suspend_thread_oh) & ~(l2i_dcache_wake_bitmap | ior_wake_bitmap); - writeback_allocate <= writeback_allocate_nxt; - ts_perf_instruction_issue <= |thread_issue_oh; - end - initial _sv2v_0 = 0; -endmodule -module tlb ( - clk, - reset, - lookup_en, - update_en, - invalidate_en, - invalidate_all_en, - request_vpage_idx, - request_asid, - update_ppage_idx, - update_present, - update_exe_writable, - update_supervisor, - update_global, - lookup_ppage_idx, - lookup_hit, - lookup_present, - lookup_exe_writable, - lookup_supervisor -); - reg _sv2v_0; - parameter NUM_ENTRIES = 64; - parameter NUM_WAYS = 4; - input clk; - input reset; - input lookup_en; - input update_en; - input invalidate_en; - input invalidate_all_en; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - input wire [defines_PAGE_NUM_BITS - 1:0] request_vpage_idx; - localparam defines_ASID_WIDTH = 8; - input [7:0] request_asid; - input wire [defines_PAGE_NUM_BITS - 1:0] update_ppage_idx; - input update_present; - input update_exe_writable; - input update_supervisor; - input update_global; - output reg [defines_PAGE_NUM_BITS - 1:0] lookup_ppage_idx; - output wire lookup_hit; - output reg lookup_present; - output reg lookup_exe_writable; - output reg lookup_supervisor; - localparam NUM_SETS = NUM_ENTRIES / NUM_WAYS; - localparam SET_INDEX_WIDTH = $clog2(NUM_SETS); - localparam WAY_INDEX_WIDTH = $clog2(NUM_WAYS); - wire [NUM_WAYS - 1:0] way_hit_oh; - wire [defines_PAGE_NUM_BITS - 1:0] way_ppage_idx [0:NUM_WAYS - 1]; - wire way_present [0:NUM_WAYS - 1]; - wire way_exe_writable [0:NUM_WAYS - 1]; - wire way_supervisor [0:NUM_WAYS - 1]; - reg [defines_PAGE_NUM_BITS - 1:0] request_vpage_idx_latched; - reg [defines_PAGE_NUM_BITS - 1:0] update_ppage_idx_latched; - wire [SET_INDEX_WIDTH - 1:0] request_set_idx; - wire [SET_INDEX_WIDTH - 1:0] update_set_idx; - reg update_en_latched; - wire update_valid; - reg invalidate_en_latched; - wire tlb_read_en; - reg [NUM_WAYS - 1:0] way_update_oh; - reg [NUM_WAYS - 1:0] next_way_oh; - reg update_present_latched; - reg update_exe_writable_latched; - reg update_supervisor_latched; - reg update_global_latched; - reg [7:0] request_asid_latched; - assign request_set_idx = request_vpage_idx[SET_INDEX_WIDTH - 1:0]; - assign update_set_idx = request_vpage_idx_latched[SET_INDEX_WIDTH - 1:0]; - assign tlb_read_en = (lookup_en || update_en) || invalidate_en; - genvar _gv_way_idx_8; - generate - for (_gv_way_idx_8 = 0; _gv_way_idx_8 < NUM_WAYS; _gv_way_idx_8 = _gv_way_idx_8 + 1) begin : way_gen - localparam way_idx = _gv_way_idx_8; - wire [defines_PAGE_NUM_BITS - 1:0] way_vpage_idx; - reg way_valid; - reg entry_valid [0:NUM_SETS - 1]; - wire [7:0] way_asid; - wire way_global; - fakeram_1r1w_16x52 #( - .SIZE(NUM_SETS), - .DATA_WIDTH(((defines_PAGE_NUM_BITS * 2) + 4) + defines_ASID_WIDTH), - .READ_DURING_WRITE("NEW_DATA") - ) tlb_paddr_sram( - .read_en(tlb_read_en), - .read_addr(request_set_idx), - .read_data({way_vpage_idx, way_asid, way_ppage_idx[way_idx], way_present[way_idx], way_exe_writable[way_idx], way_supervisor[way_idx], way_global}), - .write_en(way_update_oh[way_idx]), - .write_addr(update_set_idx), - .write_data({request_vpage_idx_latched, request_asid_latched, update_ppage_idx_latched, update_present_latched, update_exe_writable_latched, update_supervisor_latched, update_global_latched}), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < NUM_SETS; set_idx = set_idx + 1) - entry_valid[set_idx] <= 0; - end - else if (invalidate_all_en) begin : sv2v_autoblock_2 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < NUM_SETS; set_idx = set_idx + 1) - entry_valid[set_idx] <= 0; - end - else if (way_update_oh[way_idx]) - entry_valid[update_set_idx] <= update_valid; - always @(posedge clk) - if (!tlb_read_en) - way_valid <= 0; - else if (way_update_oh[way_idx] && (update_set_idx == request_set_idx)) - way_valid <= update_valid; - else - way_valid <= entry_valid[request_set_idx]; - assign way_hit_oh[way_idx] = (way_valid && (way_vpage_idx == request_vpage_idx_latched)) && (((way_asid == request_asid_latched) || way_global) || (update_en_latched && update_global_latched)); - end - endgenerate - always @(posedge clk) begin - update_ppage_idx_latched <= update_ppage_idx; - update_present_latched <= update_present; - update_exe_writable_latched <= update_exe_writable; - update_supervisor_latched <= update_supervisor; - update_global_latched <= update_global; - request_asid_latched <= request_asid; - request_vpage_idx_latched <= request_vpage_idx; - end - always @(posedge clk or posedge reset) - if (reset) begin - invalidate_en_latched <= 1'sb0; - update_en_latched <= 1'sb0; - end - else begin - update_en_latched <= update_en; - invalidate_en_latched <= invalidate_en; - end - assign lookup_hit = |way_hit_oh; - always @(*) begin - if (_sv2v_0) - ; - lookup_ppage_idx = 0; - lookup_present = 0; - lookup_exe_writable = 0; - lookup_supervisor = 0; - begin : sv2v_autoblock_3 - reg signed [31:0] way; - for (way = 0; way < NUM_WAYS; way = way + 1) - if (way_hit_oh[way]) begin - lookup_ppage_idx = lookup_ppage_idx | way_ppage_idx[way]; - lookup_present = lookup_present | way_present[way]; - lookup_exe_writable = lookup_exe_writable | way_exe_writable[way]; - lookup_supervisor = lookup_supervisor | way_supervisor[way]; - end - end - end - always @(*) begin - if (_sv2v_0) - ; - if (update_en_latched || invalidate_en_latched) begin - if (lookup_hit) - way_update_oh = way_hit_oh; - else - way_update_oh = next_way_oh; - end - else - way_update_oh = 1'sb0; - end - assign update_valid = update_en_latched; - function automatic signed [NUM_WAYS - 1:0] sv2v_cast_5B59D_signed; - input reg signed [NUM_WAYS - 1:0] inp; - sv2v_cast_5B59D_signed = inp; - endfunction - always @(posedge clk or posedge reset) - if (reset) - next_way_oh <= sv2v_cast_5B59D_signed(1); - else if (update_en) - next_way_oh <= {next_way_oh[NUM_WAYS - 2:0], next_way_oh[NUM_WAYS - 1]}; - initial _sv2v_0 = 0; -endmodule -module writeback_stage ( - clk, - reset, - fx5_instruction_valid, - fx5_instruction, - fx5_result, - fx5_mask_value, - fx5_thread_idx, - fx5_subcycle, - ix_instruction_valid, - ix_instruction, - ix_result, - ix_thread_idx, - ix_mask_value, - ix_rollback_en, - ix_rollback_pc, - ix_subcycle, - ix_privileged_op_fault, - dd_instruction_valid, - dd_instruction, - dd_lane_mask, - dd_thread_idx, - dd_request_vaddr, - dd_subcycle, - dd_rollback_en, - dd_rollback_pc, - dd_load_data, - dd_suspend_thread, - dd_io_access, - dd_trap, - dd_trap_cause, - sq_store_bypass_mask, - sq_store_bypass_data, - sq_store_sync_success, - sq_rollback_en, - ior_read_value, - ior_rollback_en, - cr_creg_read_val, - cr_trap_handler, - cr_tlb_miss_handler, - cr_eret_subcycle, - wb_trap, - wb_trap_cause, - wb_trap_pc, - wb_trap_access_vaddr, - wb_trap_subcycle, - wb_syscall_index, - wb_eret, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pc, - wb_rollback_pipeline, - wb_rollback_subcycle, - wb_writeback_en, - wb_writeback_thread_idx, - wb_writeback_vector, - wb_writeback_value, - wb_writeback_mask, - wb_writeback_reg, - wb_writeback_last_subcycle, - wb_suspend_thread_oh, - wb_inst_injected, - wb_perf_instruction_retire, - wb_perf_store_rollback, - wb_perf_interrupt -); - reg _sv2v_0; - input clk; - input reset; - input fx5_instruction_valid; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] fx5_instruction; - input wire [511:0] fx5_result; - input wire [15:0] fx5_mask_value; - input wire [1:0] fx5_thread_idx; - input wire [3:0] fx5_subcycle; - input ix_instruction_valid; - input wire [141:0] ix_instruction; - input wire [511:0] ix_result; - input wire [1:0] ix_thread_idx; - input wire [15:0] ix_mask_value; - input wire ix_rollback_en; - input wire [31:0] ix_rollback_pc; - input wire [3:0] ix_subcycle; - input ix_privileged_op_fault; - input dd_instruction_valid; - input wire [141:0] dd_instruction; - input wire [15:0] dd_lane_mask; - input wire [1:0] dd_thread_idx; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_DCACHE_TAG_BITS = 20; - input wire [31:0] dd_request_vaddr; - input wire [3:0] dd_subcycle; - input dd_rollback_en; - input wire [31:0] dd_rollback_pc; - localparam defines_CACHE_LINE_BITS = 512; - input wire [511:0] dd_load_data; - input dd_suspend_thread; - input dd_io_access; - input wire dd_trap; - input wire [5:0] dd_trap_cause; - input [63:0] sq_store_bypass_mask; - input wire [511:0] sq_store_bypass_data; - input sq_store_sync_success; - input sq_rollback_en; - input wire [31:0] ior_read_value; - input wire ior_rollback_en; - input wire [31:0] cr_creg_read_val; - input wire [31:0] cr_trap_handler; - input wire [31:0] cr_tlb_miss_handler; - input wire [15:0] cr_eret_subcycle; - output reg wb_trap; - output reg [5:0] wb_trap_cause; - output reg [31:0] wb_trap_pc; - output reg [31:0] wb_trap_access_vaddr; - output reg [3:0] wb_trap_subcycle; - output wire [14:0] wb_syscall_index; - output reg wb_eret; - output reg wb_rollback_en; - output reg [1:0] wb_rollback_thread_idx; - output reg [31:0] wb_rollback_pc; - output reg [1:0] wb_rollback_pipeline; - output reg [3:0] wb_rollback_subcycle; - output reg wb_writeback_en; - output reg [1:0] wb_writeback_thread_idx; - output reg wb_writeback_vector; - output reg [511:0] wb_writeback_value; - output reg [15:0] wb_writeback_mask; - output reg [4:0] wb_writeback_reg; - output reg wb_writeback_last_subcycle; - output wire [3:0] wb_suspend_thread_oh; - output reg wb_inst_injected; - output reg wb_perf_instruction_retire; - output reg wb_perf_store_rollback; - output reg wb_perf_interrupt; - wire [31:0] mem_load_lane; - localparam defines_CACHE_LINE_WORDS = 16; - wire [3:0] mem_load_lane_idx; - reg [7:0] byte_aligned; - reg [15:0] half_aligned; - wire [31:0] swapped_word_value; - wire [3:0] memory_op; - wire [511:0] endian_twiddled_data; - wire [15:0] scycle_vcompare_result; - wire [15:0] mcycle_vcompare_result; - wire [15:0] dd_vector_lane_oh; - wire [511:0] bypassed_read_data; - wire [3:0] thread_dd_oh; - wire last_subcycle_dd; - wire last_subcycle_ix; - wire last_subcycle_fx; - reg writeback_en_nxt; - reg [1:0] writeback_thread_idx_nxt; - reg writeback_vector_nxt; - reg [511:0] writeback_value_nxt; - reg [15:0] writeback_mask_nxt; - reg [4:0] writeback_reg_nxt; - reg writeback_last_subcycle_nxt; - always @(*) begin - if (_sv2v_0) - ; - wb_rollback_en = 0; - wb_rollback_pc = 0; - wb_rollback_thread_idx = 0; - wb_rollback_pipeline = 2'd1; - wb_trap = 0; - wb_trap_cause = 6'h00; - wb_rollback_subcycle = 0; - wb_trap_pc = 0; - wb_trap_access_vaddr = 0; - wb_trap_subcycle = dd_subcycle; - wb_eret = 0; - if (ix_instruction_valid && (ix_instruction[108] || ix_privileged_op_fault)) begin - wb_rollback_en = 1; - if (ix_instruction[105-:4] == 4'd7) - wb_rollback_pc = cr_tlb_miss_handler; - else - wb_rollback_pc = cr_trap_handler; - wb_rollback_thread_idx = ix_thread_idx; - wb_rollback_pipeline = 2'd1; - wb_trap = 1; - if (ix_privileged_op_fault) - wb_trap_cause = 6'h02; - else - wb_trap_cause = ix_instruction[107-:6]; - wb_trap_pc = ix_instruction[141-:32]; - wb_trap_access_vaddr = ix_instruction[141-:32]; - wb_trap_subcycle = ix_subcycle; - end - else if (dd_instruction_valid && dd_trap) begin - wb_rollback_en = 1'b1; - if (dd_trap_cause[3-:4] == 4'd7) - wb_rollback_pc = cr_tlb_miss_handler; - else - wb_rollback_pc = cr_trap_handler; - wb_rollback_thread_idx = dd_thread_idx; - wb_rollback_pipeline = 2'd0; - wb_trap = 1; - wb_trap_cause = dd_trap_cause; - wb_trap_pc = dd_instruction[141-:32]; - wb_trap_access_vaddr = dd_request_vaddr; - end - else if (ix_instruction_valid && ix_rollback_en) begin - wb_rollback_en = 1; - wb_rollback_pc = ix_rollback_pc; - wb_rollback_thread_idx = ix_thread_idx; - wb_rollback_pipeline = 2'd1; - if (ix_instruction[25-:3] == 3'b111) begin - wb_eret = 1; - wb_rollback_subcycle = cr_eret_subcycle[(3 - ix_thread_idx) * 4+:4]; - end - else - wb_rollback_subcycle = ix_subcycle; - end - else if (dd_instruction_valid && ((dd_rollback_en || sq_rollback_en) || ior_rollback_en)) begin - wb_rollback_en = 1; - wb_rollback_pc = dd_rollback_pc; - wb_rollback_thread_idx = dd_thread_idx; - wb_rollback_pipeline = 2'd0; - wb_rollback_subcycle = dd_subcycle; - end - end - function automatic [14:0] sv2v_cast_15; - input reg [14:0] inp; - sv2v_cast_15 = inp; - endfunction - assign wb_syscall_index = sv2v_cast_15(ix_instruction[58-:32]); - always @(*) begin - if (_sv2v_0) - ; - if (ix_instruction_valid) - wb_inst_injected = ix_instruction[109]; - else if (dd_instruction_valid) - wb_inst_injected = dd_instruction[109]; - else if (fx5_instruction_valid) - wb_inst_injected = fx5_instruction[109]; - else - wb_inst_injected = 0; - end - idx_to_oh #( - .NUM_SIGNALS(4), - .DIRECTION("LSB0") - ) idx_to_oh_thread( - .one_hot(thread_dd_oh), - .index(dd_thread_idx) - ); - assign wb_suspend_thread_oh = ((dd_suspend_thread || sq_rollback_en) || ior_rollback_en ? thread_dd_oh : 4'd0); - genvar _gv_byte_lane_2; - generate - for (_gv_byte_lane_2 = 0; _gv_byte_lane_2 < defines_CACHE_LINE_BYTES; _gv_byte_lane_2 = _gv_byte_lane_2 + 1) begin : lane_bypass_gen - localparam byte_lane = _gv_byte_lane_2; - assign bypassed_read_data[byte_lane * 8+:8] = (sq_store_bypass_mask[byte_lane] ? sq_store_bypass_data[byte_lane * 8+:8] : dd_load_data[byte_lane * 8+:8]); - end - endgenerate - assign memory_op = dd_instruction[18-:4]; - assign mem_load_lane_idx = ~dd_request_vaddr[2+:4]; - assign mem_load_lane = bypassed_read_data[mem_load_lane_idx * 32+:32]; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dd_request_vaddr[1:0]) - 2'd0: byte_aligned = mem_load_lane[31:24]; - 2'd1: byte_aligned = mem_load_lane[23:16]; - 2'd2: byte_aligned = mem_load_lane[15:8]; - 2'd3: byte_aligned = mem_load_lane[7:0]; - default: byte_aligned = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dd_request_vaddr[1]) - 1'd0: half_aligned = {mem_load_lane[23:16], mem_load_lane[31:24]}; - 1'd1: half_aligned = {mem_load_lane[7:0], mem_load_lane[15:8]}; - default: half_aligned = 1'sb0; - endcase - end - assign swapped_word_value = {mem_load_lane[7:0], mem_load_lane[15:8], mem_load_lane[23:16], mem_load_lane[31:24]}; - genvar _gv_swap_word_2; - generate - for (_gv_swap_word_2 = 0; _gv_swap_word_2 < 16; _gv_swap_word_2 = _gv_swap_word_2 + 1) begin : swap_word_gen - localparam swap_word = _gv_swap_word_2; - assign endian_twiddled_data[swap_word * 32+:8] = bypassed_read_data[(swap_word * 32) + 24+:8]; - assign endian_twiddled_data[(swap_word * 32) + 8+:8] = bypassed_read_data[(swap_word * 32) + 16+:8]; - assign endian_twiddled_data[(swap_word * 32) + 16+:8] = bypassed_read_data[(swap_word * 32) + 8+:8]; - assign endian_twiddled_data[(swap_word * 32) + 24+:8] = bypassed_read_data[swap_word * 32+:8]; - end - endgenerate - genvar _gv_mask_lane_1; - generate - for (_gv_mask_lane_1 = 0; _gv_mask_lane_1 < defines_NUM_VECTOR_LANES; _gv_mask_lane_1 = _gv_mask_lane_1 + 1) begin : compare_result_gen - localparam mask_lane = _gv_mask_lane_1; - assign scycle_vcompare_result[mask_lane] = ix_result[((defines_NUM_VECTOR_LANES - mask_lane) - 1) * 32]; - assign mcycle_vcompare_result[mask_lane] = fx5_result[((defines_NUM_VECTOR_LANES - mask_lane) - 1) * 32]; - end - endgenerate - idx_to_oh #( - .NUM_SIGNALS(defines_NUM_VECTOR_LANES), - .DIRECTION("LSB0") - ) convert_dd_lane( - .one_hot(dd_vector_lane_oh), - .index(dd_subcycle) - ); - assign last_subcycle_dd = dd_subcycle == dd_instruction[12-:4]; - assign last_subcycle_ix = ix_subcycle == ix_instruction[12-:4]; - assign last_subcycle_fx = fx5_subcycle == fx5_instruction[12-:4]; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(*) begin - if (_sv2v_0) - ; - writeback_en_nxt = 0; - writeback_thread_idx_nxt = 0; - writeback_mask_nxt = 0; - writeback_value_nxt = 0; - writeback_vector_nxt = 0; - writeback_reg_nxt = 0; - writeback_last_subcycle_nxt = 0; - if (fx5_instruction_valid) begin - if (fx5_instruction[77] && !wb_rollback_en) - writeback_en_nxt = 1; - writeback_thread_idx_nxt = fx5_thread_idx; - writeback_mask_nxt = fx5_mask_value; - if (fx5_instruction[13]) - writeback_value_nxt[0+:32] = {16'd0, mcycle_vcompare_result}; - else - writeback_value_nxt = fx5_result; - writeback_vector_nxt = fx5_instruction[76]; - writeback_reg_nxt = fx5_instruction[75-:5]; - writeback_last_subcycle_nxt = last_subcycle_fx; - end - else if (ix_instruction_valid) begin - if (ix_instruction[26] && ((ix_instruction[25-:3] == 3'b100) || (ix_instruction[25-:3] == 3'b110))) - writeback_en_nxt = 1; - else if (ix_instruction[77] && !wb_rollback_en) - writeback_en_nxt = 1; - writeback_thread_idx_nxt = ix_thread_idx; - writeback_mask_nxt = ix_mask_value; - if (ix_instruction[22]) - writeback_value_nxt[0+:32] = ix_instruction[141-:32] + 32'd4; - else if (ix_instruction[13]) - writeback_value_nxt[0+:32] = {16'd0, scycle_vcompare_result}; - else - writeback_value_nxt = ix_result; - writeback_vector_nxt = ix_instruction[76]; - writeback_reg_nxt = ix_instruction[75-:5]; - writeback_last_subcycle_nxt = last_subcycle_ix; - end - else if (dd_instruction_valid) begin - writeback_en_nxt = dd_instruction[77] && !wb_rollback_en; - writeback_thread_idx_nxt = dd_thread_idx; - if (!dd_instruction[3]) begin - if (dd_instruction[14]) - (* full_case, parallel_case *) - case (memory_op) - 4'b0000: writeback_value_nxt[0+:32] = sv2v_cast_32(byte_aligned); - 4'b0001: writeback_value_nxt[0+:32] = sv2v_cast_32($signed(byte_aligned)); - 4'b0010: writeback_value_nxt[0+:32] = sv2v_cast_32(half_aligned); - 4'b0011: writeback_value_nxt[0+:32] = sv2v_cast_32($signed(half_aligned)); - 4'b0101: writeback_value_nxt[0+:32] = swapped_word_value; - 4'b0100: - if (dd_io_access) begin - writeback_mask_nxt = {defines_NUM_VECTOR_LANES {1'b1}}; - writeback_value_nxt[0+:32] = ior_read_value; - end - else begin - writeback_mask_nxt = {defines_NUM_VECTOR_LANES {1'b1}}; - writeback_value_nxt[0+:32] = swapped_word_value; - end - 4'b0110: begin - writeback_mask_nxt = {defines_NUM_VECTOR_LANES {1'b1}}; - writeback_value_nxt[0+:32] = cr_creg_read_val; - end - 4'b0111, 4'b1000: begin - writeback_mask_nxt = dd_lane_mask; - writeback_value_nxt = endian_twiddled_data; - end - default: begin - writeback_mask_nxt = dd_vector_lane_oh & dd_lane_mask; - writeback_value_nxt = {defines_NUM_VECTOR_LANES {swapped_word_value}}; - end - endcase - else if (memory_op == 4'b0101) - writeback_value_nxt[0+:32] = sv2v_cast_32(sq_store_sync_success); - end - writeback_vector_nxt = dd_instruction[76]; - writeback_reg_nxt = dd_instruction[75-:5]; - writeback_last_subcycle_nxt = last_subcycle_dd; - end - end - always @(posedge clk) begin - wb_writeback_thread_idx <= writeback_thread_idx_nxt; - wb_writeback_mask <= writeback_mask_nxt; - wb_writeback_value <= writeback_value_nxt; - wb_writeback_vector <= writeback_vector_nxt; - wb_writeback_reg <= writeback_reg_nxt; - wb_writeback_last_subcycle <= writeback_last_subcycle_nxt; - end - always @(posedge clk or posedge reset) - if (reset) - wb_writeback_en <= 0; - else begin - if (dd_instruction_valid && !dd_instruction[3]) begin - if (dd_instruction[14]) begin - if (((((((memory_op == 4'b0000) || (memory_op == 4'b0001)) || (memory_op == 4'b0010)) || (memory_op == 4'b0011)) || (memory_op == 4'b0101)) || (memory_op == 4'b0100)) || (memory_op == 4'b0110)) - ; - end - else if (memory_op == 4'b0101) - ; - end - wb_writeback_en <= writeback_en_nxt; - wb_perf_instruction_retire <= ((fx5_instruction_valid || ix_instruction_valid) || dd_instruction_valid) && (!wb_rollback_en || ((ix_instruction_valid && ix_instruction[26]) && !ix_privileged_op_fault)); - wb_perf_store_rollback <= sq_rollback_en; - wb_perf_interrupt <= (ix_instruction_valid && ix_instruction[108]) && (ix_instruction[105-:4] == 4'd3); - end - initial _sv2v_0 = 0; -endmodule -module NyuziProcessor ( - clk, - reset, - m_aclk, - m_aresetn, - m_awaddr, - m_awlen, - m_awprot, - m_awvalid, - s_awready, - m_wdata, - m_wlast, - m_wvalid, - s_wready, - s_bvalid, - m_bready, - m_araddr, - m_arlen, - m_arprot, - m_arvalid, - s_arready, - s_rdata, - s_rvalid, - m_rready, - io_write_en, - io_read_en, - io_address, - io_write_data, - io_read_data, - jtag_tck, - jtag_trst_n, - jtag_tdi, - jtag_tms, - jtag_tdo, - interrupt_req -); - parameter signed [31:0] RESET_PC = 0; - parameter signed [31:0] NUM_INTERRUPTS = 16; - input wire clk; - input wire reset; - output wire m_aclk; - output wire m_aresetn; - localparam defines_AXI_ADDR_WIDTH = 32; - output wire [31:0] m_awaddr; - output wire [7:0] m_awlen; - output wire [2:0] m_awprot; - output wire m_awvalid; - input wire s_awready; - output wire [31:0] m_wdata; - output wire m_wlast; - output wire m_wvalid; - input wire s_wready; - input wire s_bvalid; - output wire m_bready; - output wire [31:0] m_araddr; - output wire [7:0] m_arlen; - output wire [2:0] m_arprot; - output wire m_arvalid; - input wire s_arready; - input wire [31:0] s_rdata; - input wire s_rvalid; - output wire m_rready; - output wire io_write_en; - output wire io_read_en; - output wire [31:0] io_address; - output wire [31:0] io_write_data; - input wire [31:0] io_read_data; - input wire jtag_tck; - input wire jtag_trst_n; - input wire jtag_tdi; - input wire jtag_tms; - output wire jtag_tdo; - input wire [NUM_INTERRUPTS - 1:0] interrupt_req; - generate - if (1) begin : axi_bus - wire m_aclk; - wire m_aresetn; - localparam defines_AXI_ADDR_WIDTH = 32; - reg [31:0] m_awaddr; - wire [7:0] m_awlen; - wire [2:0] m_awprot; - reg m_awvalid; - wire s_awready; - reg [31:0] m_wdata; - reg m_wlast; - reg m_wvalid; - wire s_wready; - wire s_bvalid; - wire m_bready; - reg [31:0] m_araddr; - wire [7:0] m_arlen; - wire [2:0] m_arprot; - reg m_arvalid; - wire s_arready; - wire [31:0] s_rdata; - wire s_rvalid; - reg m_rready; - end - if (1) begin : io_bus - wire write_en; - wire read_en; - wire [31:0] address; - wire [31:0] write_data; - wire [31:0] read_data; - end - if (1) begin : jtag - wire tck; - wire trst_n; - wire tdi; - reg tdo; - wire tms; - end - endgenerate - assign m_aclk = axi_bus.m_aclk; - assign m_aresetn = axi_bus.m_aresetn; - assign m_awaddr = axi_bus.m_awaddr; - assign m_awlen = axi_bus.m_awlen; - assign m_awprot = axi_bus.m_awprot; - assign m_awvalid = axi_bus.m_awvalid; - assign axi_bus.s_awready = s_awready; - assign m_wdata = axi_bus.m_wdata; - assign m_wlast = axi_bus.m_wlast; - assign m_wvalid = axi_bus.m_wvalid; - assign axi_bus.s_wready = s_wready; - assign axi_bus.s_bvalid = s_bvalid; - assign m_bready = axi_bus.m_bready; - assign m_araddr = axi_bus.m_araddr; - assign m_arlen = axi_bus.m_arlen; - assign m_arprot = axi_bus.m_arprot; - assign m_arvalid = axi_bus.m_arvalid; - assign axi_bus.s_arready = s_arready; - assign axi_bus.s_rdata = s_rdata; - assign axi_bus.s_rvalid = s_rvalid; - assign m_rready = axi_bus.m_rready; - assign io_write_en = io_bus.write_en; - assign io_read_en = io_bus.read_en; - assign io_address = io_bus.address; - assign io_write_data = io_bus.write_data; - assign io_bus.read_data = io_read_data; - assign jtag.tck = jtag_tck; - assign jtag.trst_n = jtag_trst_n; - assign jtag.tdi = jtag_tdi; - assign jtag.tms = jtag_tms; - assign jtag_tdo = jtag.tdo; - localparam _param_D9EB5_RESET_PC = RESET_PC; - localparam _param_D9EB5_NUM_INTERRUPTS = NUM_INTERRUPTS; - function automatic [6:0] sv2v_cast_7; - input reg [6:0] inp; - sv2v_cast_7 = inp; - endfunction - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - function automatic [3:0] sv2v_cast_4; - input reg [3:0] inp; - sv2v_cast_4 = inp; - endfunction - generate - if (1) begin : u_nyuzi - localparam RESET_PC = _param_D9EB5_RESET_PC; - localparam NUM_INTERRUPTS = _param_D9EB5_NUM_INTERRUPTS; - wire clk; - wire reset; - wire [NUM_INTERRUPTS - 1:0] interrupt_req; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - wire [611:0] l2i_request; - wire [0:0] l2i_request_valid; - wire [66:0] ior_request; - wire [0:0] ior_request_valid; - localparam defines_TOTAL_THREADS = 4; - reg [3:0] thread_en; - wire [31:0] cr_data_to_host [0:0]; - wire [31:0] data_to_host; - wire [0:0] core_injected_complete; - wire [0:0] core_injected_rollback; - wire [3:0] core_suspend_thread; - wire [3:0] core_resume_thread; - reg [3:0] thread_suspend_mask; - reg [3:0] thread_resume_mask; - wire [0:0] ii_ready; - wire [37:0] ii_response; - wire ii_response_valid; - wire [0:0] l2_ready; - wire [548:0] l2_response; - wire l2_response_valid; - wire [3:0] ocd_core; - wire [31:0] ocd_data_from_host; - wire ocd_data_update; - wire ocd_halt; - wire ocd_inject_en; - wire [31:0] ocd_inject_inst; - wire [1:0] ocd_thread; - localparam defines_CORE_ID_WIDTH = 0; - always @(*) begin - thread_suspend_mask = 1'sb0; - thread_resume_mask = 1'sb0; - begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < 1; i = i + 1) - begin - thread_suspend_mask = thread_suspend_mask | core_suspend_thread[i * 4+:4]; - thread_resume_mask = thread_resume_mask | core_resume_thread[i * 4+:4]; - end - end - end - always @(posedge clk or posedge reset) - if (reset) - thread_en <= 1; - else - thread_en <= (thread_en | thread_resume_mask) & ~thread_suspend_mask; - if (1) begin : l2_cache - wire clk; - wire reset; - wire [0:0] l2i_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - wire [611:0] l2i_request; - wire [0:0] l2_ready; - wire l2_response_valid; - wire [548:0] l2_response; - localparam defines_L2_PERF_EVENTS = 3; - wire [2:0] l2_perf_events; - wire [511:0] l2a_data_from_memory; - wire l2a_l2_fill; - wire [611:0] l2a_request; - wire l2a_request_valid; - wire l2a_restarted_flush; - wire l2bi_collided_miss; - wire [511:0] l2bi_data_from_memory; - wire l2bi_perf_l2_writeback; - wire [611:0] l2bi_request; - wire l2bi_request_valid; - wire l2bi_stall; - wire l2r_cache_hit; - wire [511:0] l2r_data; - wire [511:0] l2r_data_from_memory; - wire [10:0] l2r_hit_cache_idx; - wire l2r_l2_fill; - wire l2r_needs_writeback; - wire l2r_perf_l2_hit; - wire l2r_perf_l2_miss; - wire [611:0] l2r_request; - wire l2r_request_valid; - wire l2r_restarted_flush; - wire l2r_store_sync_success; - wire [7:0] l2r_update_dirty_en; - wire [7:0] l2r_update_dirty_set; - wire l2r_update_dirty_value; - wire l2r_update_lru_en; - wire [2:0] l2r_update_lru_hit_way; - wire [7:0] l2r_update_tag_en; - wire [7:0] l2r_update_tag_set; - wire l2r_update_tag_valid; - wire [17:0] l2r_update_tag_value; - wire [17:0] l2r_writeback_tag; - wire [511:0] l2t_data_from_memory; - wire [0:7] l2t_dirty; - wire [2:0] l2t_fill_way; - wire l2t_l2_fill; - wire [611:0] l2t_request; - wire l2t_request_valid; - wire l2t_restarted_flush; - wire [143:0] l2t_tag; - wire [0:7] l2t_valid; - wire [10:0] l2u_write_addr; - wire [511:0] l2u_write_data; - wire l2u_write_en; - l2_cache_arb_stage l2_cache_arb_stage( - .clk(clk), - .reset(reset), - .l2i_request_valid(l2i_request_valid), - .l2i_request(l2i_request), - .l2_ready(l2_ready), - .l2a_request_valid(l2a_request_valid), - .l2a_request(l2a_request), - .l2a_data_from_memory(l2a_data_from_memory), - .l2a_l2_fill(l2a_l2_fill), - .l2a_restarted_flush(l2a_restarted_flush), - .l2bi_request_valid(l2bi_request_valid), - .l2bi_request(l2bi_request), - .l2bi_data_from_memory(l2bi_data_from_memory), - .l2bi_stall(l2bi_stall), - .l2bi_collided_miss(l2bi_collided_miss) - ); - l2_cache_tag_stage l2_cache_tag_stage( - .clk(clk), - .reset(reset), - .l2a_request_valid(l2a_request_valid), - .l2a_request(l2a_request), - .l2a_data_from_memory(l2a_data_from_memory), - .l2a_l2_fill(l2a_l2_fill), - .l2a_restarted_flush(l2a_restarted_flush), - .l2r_update_dirty_en(l2r_update_dirty_en), - .l2r_update_dirty_set(l2r_update_dirty_set), - .l2r_update_dirty_value(l2r_update_dirty_value), - .l2r_update_tag_en(l2r_update_tag_en), - .l2r_update_tag_set(l2r_update_tag_set), - .l2r_update_tag_valid(l2r_update_tag_valid), - .l2r_update_tag_value(l2r_update_tag_value), - .l2r_update_lru_en(l2r_update_lru_en), - .l2r_update_lru_hit_way(l2r_update_lru_hit_way), - .l2t_request_valid(l2t_request_valid), - .l2t_request(l2t_request), - .l2t_valid(l2t_valid), - .l2t_tag(l2t_tag), - .l2t_dirty(l2t_dirty), - .l2t_l2_fill(l2t_l2_fill), - .l2t_fill_way(l2t_fill_way), - .l2t_data_from_memory(l2t_data_from_memory), - .l2t_restarted_flush(l2t_restarted_flush) - ); - l2_cache_read_stage l2_cache_read_stage( - .clk(clk), - .reset(reset), - .l2t_request_valid(l2t_request_valid), - .l2t_request(l2t_request), - .l2t_valid(l2t_valid), - .l2t_tag(l2t_tag), - .l2t_dirty(l2t_dirty), - .l2t_l2_fill(l2t_l2_fill), - .l2t_restarted_flush(l2t_restarted_flush), - .l2t_fill_way(l2t_fill_way), - .l2t_data_from_memory(l2t_data_from_memory), - .l2r_update_dirty_en(l2r_update_dirty_en), - .l2r_update_dirty_set(l2r_update_dirty_set), - .l2r_update_dirty_value(l2r_update_dirty_value), - .l2r_update_tag_en(l2r_update_tag_en), - .l2r_update_tag_set(l2r_update_tag_set), - .l2r_update_tag_valid(l2r_update_tag_valid), - .l2r_update_tag_value(l2r_update_tag_value), - .l2r_update_lru_en(l2r_update_lru_en), - .l2r_update_lru_hit_way(l2r_update_lru_hit_way), - .l2u_write_en(l2u_write_en), - .l2u_write_addr(l2u_write_addr), - .l2u_write_data(l2u_write_data), - .l2r_request_valid(l2r_request_valid), - .l2r_request(l2r_request), - .l2r_data(l2r_data), - .l2r_cache_hit(l2r_cache_hit), - .l2r_hit_cache_idx(l2r_hit_cache_idx), - .l2r_l2_fill(l2r_l2_fill), - .l2r_restarted_flush(l2r_restarted_flush), - .l2r_data_from_memory(l2r_data_from_memory), - .l2r_store_sync_success(l2r_store_sync_success), - .l2r_writeback_tag(l2r_writeback_tag), - .l2r_needs_writeback(l2r_needs_writeback), - .l2r_perf_l2_miss(l2r_perf_l2_miss), - .l2r_perf_l2_hit(l2r_perf_l2_hit) - ); - l2_cache_update_stage l2_cache_update_stage( - .clk(clk), - .reset(reset), - .l2r_request_valid(l2r_request_valid), - .l2r_request(l2r_request), - .l2r_data(l2r_data), - .l2r_cache_hit(l2r_cache_hit), - .l2r_hit_cache_idx(l2r_hit_cache_idx), - .l2r_l2_fill(l2r_l2_fill), - .l2r_restarted_flush(l2r_restarted_flush), - .l2r_data_from_memory(l2r_data_from_memory), - .l2r_store_sync_success(l2r_store_sync_success), - .l2r_needs_writeback(l2r_needs_writeback), - .l2u_write_en(l2u_write_en), - .l2u_write_addr(l2u_write_addr), - .l2u_write_data(l2u_write_data), - .l2_response_valid(l2_response_valid), - .l2_response(l2_response) - ); - if (1) begin : l2_axi_bus_interface - reg _sv2v_0; - wire clk; - wire reset; - reg l2bi_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - reg [611:0] l2bi_request; - wire [511:0] l2bi_data_from_memory; - wire l2bi_stall; - wire l2bi_collided_miss; - wire l2r_needs_writeback; - wire [17:0] l2r_writeback_tag; - wire [511:0] l2r_data; - wire l2r_l2_fill; - wire l2r_restarted_flush; - wire l2r_cache_hit; - wire l2r_request_valid; - wire [611:0] l2r_request; - reg l2bi_perf_l2_writeback; - localparam FIFO_SIZE = 8; - localparam L2REQ_LATENCY = 4; - localparam BURST_BEATS = 16; - localparam BURST_OFFSET_WIDTH = 4; - wire [25:0] miss_addr; - wire [25:0] writeback_address; - wire enqueue_writeback_request; - wire enqueue_fill_request; - wire duplicate_request; - wire [511:0] writeback_data; - wire [31:0] writeback_lanes [0:15]; - wire writeback_fifo_empty; - wire fill_queue_empty; - wire fill_request_pending; - wire writeback_pending; - reg writeback_complete; - wire writeback_fifo_almost_full; - wire fill_queue_almost_full; - reg [31:0] state_ff; - reg [31:0] state_nxt; - reg [3:0] burst_offset_ff; - reg [3:0] burst_offset_nxt; - reg [31:0] fill_buffer [0:15]; - reg restart_flush_request; - reg fill_dequeue_en; - wire [611:0] lmq_out_request; - wire [544:0] writeback_fifo_in; - wire [544:0] writeback_fifo_out; - assign miss_addr = l2r_request[601-:26]; - assign enqueue_writeback_request = (l2r_request_valid && l2r_needs_writeback) && ((((l2r_request[605-:3] == 3'd4) && l2r_cache_hit) && !l2r_restarted_flush) || l2r_l2_fill); - assign enqueue_fill_request = ((l2r_request_valid && !l2r_cache_hit) && !l2r_l2_fill) && ((((l2r_request[605-:3] == 3'd0) || (l2r_request[605-:3] == 3'd2)) || (l2r_request[605-:3] == 3'd1)) || (l2r_request[605-:3] == 3'd3)); - assign writeback_pending = !writeback_fifo_empty; - assign fill_request_pending = !fill_queue_empty; - l2_cache_pending_miss_cam l2_cache_pending_miss_cam( - .request_valid(l2r_request_valid), - .request_addr({miss_addr[25-:18], miss_addr[7-:8]}), - .clk(clk), - .reset(reset), - .enqueue_fill_request(enqueue_fill_request), - .l2r_l2_fill(l2r_l2_fill), - .duplicate_request(duplicate_request) - ); - assign writeback_fifo_in[544-:26] = {l2r_writeback_tag, miss_addr[7-:8]}; - assign writeback_fifo_in[518-:512] = l2r_data; - assign writeback_fifo_in[6] = l2r_request[605-:3] == 3'd4; - assign writeback_fifo_in[5-:4] = l2r_request[611-:4]; - assign writeback_fifo_in[1-:2] = l2r_request[607-:2]; - sync_fifo #( - .WIDTH(545), - .SIZE(FIFO_SIZE), - .ALMOST_FULL_THRESHOLD(4) - ) pending_writeback_fifo( - .clk(clk), - .reset(reset), - .flush_en(1'b0), - .almost_full(writeback_fifo_almost_full), - .enqueue_en(enqueue_writeback_request), - .enqueue_value(writeback_fifo_in), - .almost_empty(), - .empty(writeback_fifo_empty), - .dequeue_en(writeback_complete), - .dequeue_value(writeback_fifo_out), - .full() - ); - assign writeback_address = writeback_fifo_out[544-:26]; - assign writeback_data = writeback_fifo_out[518-:512]; - sync_fifo #( - .WIDTH(613), - .SIZE(FIFO_SIZE), - .ALMOST_FULL_THRESHOLD(4) - ) pending_fill_fifo( - .clk(clk), - .reset(reset), - .flush_en(1'b0), - .almost_full(fill_queue_almost_full), - .enqueue_en(enqueue_fill_request), - .enqueue_value({duplicate_request, l2r_request}), - .empty(fill_queue_empty), - .almost_empty(), - .dequeue_en(fill_dequeue_en), - .dequeue_value({l2bi_collided_miss, lmq_out_request}), - .full() - ); - assign l2bi_stall = fill_queue_almost_full || writeback_fifo_almost_full; - assign NyuziProcessor.axi_bus.m_awlen = 8'sd15; - assign NyuziProcessor.axi_bus.m_arlen = 8'sd15; - assign NyuziProcessor.axi_bus.m_bready = 1'b1; - assign NyuziProcessor.axi_bus.m_awprot = 3'b000; - assign NyuziProcessor.axi_bus.m_arprot = 3'b000; - assign NyuziProcessor.axi_bus.m_aclk = clk; - assign NyuziProcessor.axi_bus.m_aresetn = !reset; - genvar _gv_fill_buffer_idx_1; - for (_gv_fill_buffer_idx_1 = 0; _gv_fill_buffer_idx_1 < BURST_BEATS; _gv_fill_buffer_idx_1 = _gv_fill_buffer_idx_1 + 1) begin : mem_lane_gen - localparam fill_buffer_idx = _gv_fill_buffer_idx_1; - assign l2bi_data_from_memory[fill_buffer_idx * 32+:32] = fill_buffer[(BURST_BEATS - fill_buffer_idx) - 1]; - end - reg wait_axi_write_response; - always @(*) begin - if (_sv2v_0) - ; - state_nxt = state_ff; - fill_dequeue_en = 0; - burst_offset_nxt = burst_offset_ff; - writeback_complete = 0; - restart_flush_request = 0; - (* full_case, parallel_case *) - case (state_ff) - 32'd0: - if (writeback_pending) begin - if (!wait_axi_write_response) - state_nxt = 32'd1; - end - else if (fill_request_pending) begin - if (l2bi_collided_miss || ((lmq_out_request[575-:64] == {defines_CACHE_LINE_BYTES {1'b1}}) && (lmq_out_request[605-:3] == 3'd2))) - state_nxt = 32'd5; - else - state_nxt = 32'd3; - end - 32'd1: begin - burst_offset_nxt = 0; - if (NyuziProcessor.axi_bus.s_awready) - state_nxt = 32'd2; - end - 32'd2: - if (NyuziProcessor.axi_bus.s_wready) begin - if (burst_offset_ff == {BURST_OFFSET_WIDTH {1'b1}}) begin - writeback_complete = 1; - restart_flush_request = writeback_fifo_out[6]; - state_nxt = 32'd0; - end - burst_offset_nxt = burst_offset_ff + 4'sd1; - end - 32'd3: begin - burst_offset_nxt = 0; - if (NyuziProcessor.axi_bus.s_arready) - state_nxt = 32'd4; - end - 32'd4: - if (NyuziProcessor.axi_bus.s_rvalid) begin - if (burst_offset_ff == {BURST_OFFSET_WIDTH {1'b1}}) - state_nxt = 32'd5; - burst_offset_nxt = burst_offset_ff + 4'sd1; - end - 32'd5: begin - state_nxt = 32'd0; - fill_dequeue_en = 1'b1; - end - endcase - end - genvar _gv_writeback_lane_1; - for (_gv_writeback_lane_1 = 0; _gv_writeback_lane_1 < BURST_BEATS; _gv_writeback_lane_1 = _gv_writeback_lane_1 + 1) begin : writeback_lane_gen - localparam writeback_lane = _gv_writeback_lane_1; - assign writeback_lanes[writeback_lane] = writeback_data[writeback_lane * 32+:32]; - end - always @(*) begin - if (_sv2v_0) - ; - l2bi_request = lmq_out_request; - if (restart_flush_request) begin - l2bi_request_valid = 1'b1; - l2bi_request[605-:3] = 3'd4; - l2bi_request[611-:4] = writeback_fifo_out[5-:4]; - l2bi_request[607-:2] = writeback_fifo_out[1-:2]; - l2bi_request[602] = 1'd1; - end - else - l2bi_request_valid = fill_dequeue_en; - end - always @(posedge clk or posedge reset) begin : update - if (reset) begin - state_ff <= 32'd0; - NyuziProcessor.axi_bus.m_arvalid <= 1'sb0; - NyuziProcessor.axi_bus.m_awvalid <= 1'sb0; - NyuziProcessor.axi_bus.m_rready <= 1'sb0; - NyuziProcessor.axi_bus.m_wlast <= 1'sb0; - NyuziProcessor.axi_bus.m_wvalid <= 1'sb0; - burst_offset_ff <= 1'sb0; - l2bi_perf_l2_writeback <= 1'sb0; - wait_axi_write_response <= 1'sb0; - end - else begin - state_ff <= state_nxt; - burst_offset_ff <= burst_offset_nxt; - if (state_ff == 32'd1) - wait_axi_write_response <= 1; - else if (NyuziProcessor.axi_bus.s_bvalid) - wait_axi_write_response <= 0; - NyuziProcessor.axi_bus.m_arvalid <= state_nxt == 32'd3; - NyuziProcessor.axi_bus.m_rready <= state_nxt == 32'd4; - NyuziProcessor.axi_bus.m_awvalid <= state_nxt == 32'd1; - NyuziProcessor.axi_bus.m_wvalid <= state_nxt == 32'd2; - NyuziProcessor.axi_bus.m_wlast <= (state_nxt == 32'd2) && (burst_offset_nxt == 4'sd15); - l2bi_perf_l2_writeback <= enqueue_writeback_request && !writeback_fifo_almost_full; - end - end - always @(posedge clk) begin - if ((state_ff == 32'd4) && NyuziProcessor.axi_bus.s_rvalid) - fill_buffer[burst_offset_ff] <= NyuziProcessor.axi_bus.s_rdata; - NyuziProcessor.axi_bus.m_araddr <= {l2bi_request[601-:26], {defines_CACHE_LINE_OFFSET_WIDTH {1'b0}}}; - NyuziProcessor.axi_bus.m_awaddr <= {writeback_address, {defines_CACHE_LINE_OFFSET_WIDTH {1'b0}}}; - NyuziProcessor.axi_bus.m_wdata <= writeback_lanes[~burst_offset_nxt]; - end - initial _sv2v_0 = 0; - end - assign l2_axi_bus_interface.clk = clk; - assign l2_axi_bus_interface.reset = reset; - assign l2bi_request_valid = l2_axi_bus_interface.l2bi_request_valid; - assign l2bi_request = l2_axi_bus_interface.l2bi_request; - assign l2bi_data_from_memory = l2_axi_bus_interface.l2bi_data_from_memory; - assign l2bi_stall = l2_axi_bus_interface.l2bi_stall; - assign l2bi_collided_miss = l2_axi_bus_interface.l2bi_collided_miss; - assign l2_axi_bus_interface.l2r_needs_writeback = l2r_needs_writeback; - assign l2_axi_bus_interface.l2r_writeback_tag = l2r_writeback_tag; - assign l2_axi_bus_interface.l2r_data = l2r_data; - assign l2_axi_bus_interface.l2r_l2_fill = l2r_l2_fill; - assign l2_axi_bus_interface.l2r_restarted_flush = l2r_restarted_flush; - assign l2_axi_bus_interface.l2r_cache_hit = l2r_cache_hit; - assign l2_axi_bus_interface.l2r_request_valid = l2r_request_valid; - assign l2_axi_bus_interface.l2r_request = l2r_request; - assign l2bi_perf_l2_writeback = l2_axi_bus_interface.l2bi_perf_l2_writeback; - assign l2_perf_events = {l2r_perf_l2_hit, l2r_perf_l2_miss, l2bi_perf_l2_writeback}; - end - assign l2_cache.clk = clk; - assign l2_cache.reset = reset; - assign l2_cache.l2i_request_valid = l2i_request_valid; - assign l2_cache.l2i_request = l2i_request; - assign l2_ready = l2_cache.l2_ready; - assign l2_response_valid = l2_cache.l2_response_valid; - assign l2_response = l2_cache.l2_response; - if (1) begin : io_interconnect - wire clk; - wire reset; - wire [0:0] ior_request_valid; - wire [66:0] ior_request; - wire [0:0] ii_ready; - reg ii_response_valid; - reg [37:0] ii_response; - wire [3:0] grant_idx; - wire [0:0] grant_oh; - reg request_sent; - reg [3:0] request_core; - reg [1:0] request_thread_idx; - wire [66:0] grant_request; - genvar _gv_request_idx_1; - for (_gv_request_idx_1 = 0; _gv_request_idx_1 < 1; _gv_request_idx_1 = _gv_request_idx_1 + 1) begin : handshake_gen - localparam request_idx = _gv_request_idx_1; - assign ii_ready[request_idx] = grant_oh[request_idx]; - end - genvar _gv_grant_idx_bit_1; - localparam defines_CORE_ID_WIDTH = 0; - if (1) begin : genblk2 - assign grant_oh[0] = ior_request_valid[0]; - assign grant_idx = 0; - assign grant_request = ior_request[0+:67]; - end - assign NyuziProcessor.io_bus.write_en = |grant_oh && grant_request[66]; - assign NyuziProcessor.io_bus.read_en = |grant_oh && !grant_request[66]; - assign NyuziProcessor.io_bus.write_data = grant_request[31-:32]; - assign NyuziProcessor.io_bus.address = grant_request[63-:32]; - always @(posedge clk) begin - ii_response[37-:4] <= request_core; - ii_response[33-:2] <= request_thread_idx; - ii_response[31-:32] <= NyuziProcessor.io_bus.read_data; - if (|ior_request_valid) begin - request_core <= grant_idx; - request_thread_idx <= grant_request[65-:2]; - end - end - always @(posedge clk or posedge reset) - if (reset) begin - ii_response_valid <= 1'sb0; - request_sent <= 1'sb0; - end - else begin - request_sent <= |ior_request_valid; - ii_response_valid <= request_sent; - end - end - assign io_interconnect.clk = clk; - assign io_interconnect.reset = reset; - assign io_interconnect.ior_request_valid = ior_request_valid; - assign io_interconnect.ior_request = ior_request; - assign ii_ready = io_interconnect.ii_ready; - assign ii_response_valid = io_interconnect.ii_response_valid; - assign ii_response = io_interconnect.ii_response; - if (1) begin : on_chip_debugger - wire clk; - wire reset; - wire ocd_halt; - wire [1:0] ocd_thread; - wire [3:0] ocd_core; - reg [31:0] ocd_inject_inst; - wire ocd_inject_en; - wire [31:0] ocd_data_from_host; - wire ocd_data_update; - wire [31:0] data_to_host; - wire injected_complete; - wire injected_rollback; - localparam JTAG_IDCODE = 32'h4d20dffb; - wire data_shift_val; - reg [31:0] data_shift_reg; - reg [6:0] control; - reg [1:0] machine_inst_status; - wire capture_dr; - wire [3:0] jtag_instruction; - wire shift_dr; - wire update_dr; - wire update_ir; - assign ocd_halt = control[0]; - assign ocd_thread = control[2-:2]; - assign ocd_core = control[6-:4]; - localparam _param_C3F75_INSTRUCTION_WIDTH = 4; - if (1) begin : jtag_tap_controller - reg _sv2v_0; - localparam INSTRUCTION_WIDTH = _param_C3F75_INSTRUCTION_WIDTH; - wire clk; - wire reset; - wire data_shift_val; - wire capture_dr; - wire shift_dr; - wire update_dr; - reg [3:0] jtag_instruction; - wire update_ir; - reg signed [31:0] state_ff; - reg signed [31:0] state_nxt; - reg last_tck; - wire tck_rising_edge; - wire tck_falling_edge; - wire tck_sync; - wire tms_sync; - wire tdi_sync; - wire trst_sync_n; - always @(*) begin - if (_sv2v_0) - ; - state_nxt = state_ff; - (* full_case, parallel_case *) - case (state_ff) - 32'sd1: - if (tms_sync) - state_nxt = 32'sd2; - 32'sd2: - if (tms_sync) - state_nxt = 32'sd9; - else - state_nxt = 32'sd3; - 32'sd3: - if (tms_sync) - state_nxt = 32'sd5; - else - state_nxt = 32'sd4; - 32'sd4: - if (tms_sync) - state_nxt = 32'sd5; - 32'sd5: - if (tms_sync) - state_nxt = 32'sd8; - else - state_nxt = 32'sd6; - 32'sd6: - if (tms_sync) - state_nxt = 32'sd7; - 32'sd7: - if (tms_sync) - state_nxt = 32'sd8; - else - state_nxt = 32'sd4; - 32'sd8: state_nxt = 32'sd1; - 32'sd9: - if (tms_sync) - state_nxt = 32'sd1; - else - state_nxt = 32'sd10; - 32'sd10: - if (tms_sync) - state_nxt = 32'sd12; - else - state_nxt = 32'sd11; - 32'sd11: - if (tms_sync) - state_nxt = 32'sd12; - 32'sd12: - if (tms_sync) - state_nxt = 32'sd15; - else - state_nxt = 32'sd13; - 32'sd13: - if (tms_sync) - state_nxt = 32'sd14; - 32'sd14: - if (tms_sync) - state_nxt = 32'sd15; - else - state_nxt = 32'sd11; - 32'sd15: - if (tms_sync) - state_nxt = 32'sd2; - else - state_nxt = 32'sd1; - 32'sd0: - if (!tms_sync) - state_nxt = 32'sd1; - default: state_nxt = 32'sd0; - endcase - end - synchronizer #(.WIDTH(4)) synchronizer( - .data_i({NyuziProcessor.jtag.tck, NyuziProcessor.jtag.tms, NyuziProcessor.jtag.tdi, NyuziProcessor.jtag.trst_n}), - .data_o({tck_sync, tms_sync, tdi_sync, trst_sync_n}), - .clk(clk), - .reset(reset) - ); - assign tck_rising_edge = !last_tck && tck_sync; - assign tck_falling_edge = last_tck && !tck_sync; - assign update_ir = (state_ff == 32'sd15) && tck_rising_edge; - assign capture_dr = (state_ff == 32'sd3) && tck_rising_edge; - assign shift_dr = (state_ff == 32'sd4) && tck_rising_edge; - assign update_dr = (state_ff == 32'sd8) && tck_rising_edge; - always @(posedge clk or posedge reset) - if (reset) begin - state_ff <= 32'sd0; - NyuziProcessor.jtag.tdo <= 1'sb0; - jtag_instruction <= 1'sb0; - last_tck <= 1'sb0; - end - else if (!trst_sync_n) - state_ff <= 32'sd0; - else begin - if (state_ff == 32'sd0) - jtag_instruction <= 1'sb0; - last_tck <= tck_sync; - if (tck_rising_edge) begin - state_ff <= state_nxt; - if (state_ff == 32'sd11) - jtag_instruction <= {tdi_sync, jtag_instruction[3:1]}; - end - else if (tck_falling_edge) - NyuziProcessor.jtag.tdo <= (state_ff == 32'sd11 ? jtag_instruction[0] : data_shift_val); - end - initial _sv2v_0 = 0; - end - assign jtag_tap_controller.clk = clk; - assign jtag_tap_controller.reset = reset; - assign jtag_tap_controller.data_shift_val = data_shift_val; - assign capture_dr = jtag_tap_controller.capture_dr; - assign shift_dr = jtag_tap_controller.shift_dr; - assign update_dr = jtag_tap_controller.update_dr; - assign jtag_instruction = jtag_tap_controller.jtag_instruction; - assign update_ir = jtag_tap_controller.update_ir; - assign data_shift_val = data_shift_reg[0]; - assign ocd_inject_en = update_dr && (jtag_instruction == 4'd4); - always @(posedge clk or posedge reset) - if (reset) begin - control <= 1'sb0; - machine_inst_status <= 2'd0; - end - else begin - if (update_dr && (jtag_instruction == 4'd3)) - control <= sv2v_cast_7(data_shift_reg); - if (injected_rollback) - machine_inst_status <= 2'd2; - else if (injected_complete) - machine_inst_status <= 2'd0; - else if (update_dr && (jtag_instruction == 4'd4)) - machine_inst_status <= 2'd1; - end - assign ocd_data_from_host = data_shift_reg; - assign ocd_data_update = update_dr && (jtag_instruction == 4'd5); - always @(posedge clk) - if (capture_dr) - (* full_case, parallel_case *) - case (jtag_instruction) - 4'd0: data_shift_reg <= JTAG_IDCODE; - 4'd3: data_shift_reg <= sv2v_cast_32(control); - 4'd5: data_shift_reg <= data_to_host; - 4'd6: data_shift_reg <= sv2v_cast_32(machine_inst_status); - default: data_shift_reg <= 1'sb0; - endcase - else if (shift_dr) - (* full_case, parallel_case *) - case (jtag_instruction) - 4'd15: data_shift_reg <= sv2v_cast_32(NyuziProcessor.jtag.tdi); - 4'd3: data_shift_reg <= sv2v_cast_32({NyuziProcessor.jtag.tdi, data_shift_reg[6:1]}); - 4'd6: data_shift_reg <= sv2v_cast_32({NyuziProcessor.jtag.tdi, data_shift_reg[1:1]}); - default: data_shift_reg <= sv2v_cast_32({NyuziProcessor.jtag.tdi, data_shift_reg[31:1]}); - endcase - else if (update_dr) begin - if (jtag_instruction == 4'd4) - ocd_inject_inst <= data_shift_reg; - end - end - assign on_chip_debugger.injected_complete = |core_injected_complete; - assign on_chip_debugger.injected_rollback = |core_injected_rollback; - assign on_chip_debugger.clk = clk; - assign on_chip_debugger.reset = reset; - assign ocd_halt = on_chip_debugger.ocd_halt; - assign ocd_thread = on_chip_debugger.ocd_thread; - assign ocd_core = on_chip_debugger.ocd_core; - assign ocd_inject_inst = on_chip_debugger.ocd_inject_inst; - assign ocd_inject_en = on_chip_debugger.ocd_inject_en; - assign ocd_data_from_host = on_chip_debugger.ocd_data_from_host; - assign ocd_data_update = on_chip_debugger.ocd_data_update; - assign on_chip_debugger.data_to_host = data_to_host; - if (1) begin : genblk1 - assign data_to_host = cr_data_to_host[0]; - end - genvar _gv_core_idx_1; - for (_gv_core_idx_1 = 0; _gv_core_idx_1 < 1; _gv_core_idx_1 = _gv_core_idx_1 + 1) begin : core_gen - localparam core_idx = _gv_core_idx_1; - core #( - .CORE_ID(sv2v_cast_4(core_idx)), - .NUM_INTERRUPTS(NUM_INTERRUPTS), - .RESET_PC(RESET_PC) - ) core( - .l2i_request_valid(l2i_request_valid[core_idx]), - .l2i_request(l2i_request[core_idx * 612+:612]), - .l2_ready(l2_ready[core_idx]), - .thread_en(thread_en[core_idx * 4+:4]), - .ior_request_valid(ior_request_valid[core_idx]), - .ior_request(ior_request[core_idx * 67+:67]), - .ii_ready(ii_ready[core_idx]), - .ii_response(ii_response), - .cr_data_to_host(cr_data_to_host[core_idx]), - .injected_complete(core_injected_complete[core_idx]), - .injected_rollback(core_injected_rollback[core_idx]), - .cr_suspend_thread(core_suspend_thread[core_idx * 4+:4]), - .cr_resume_thread(core_resume_thread[core_idx * 4+:4]), - .clk(clk), - .reset(reset), - .interrupt_req(interrupt_req), - .l2_response_valid(l2_response_valid), - .l2_response(l2_response), - .ii_response_valid(ii_response_valid), - .ocd_halt(ocd_halt), - .ocd_thread(ocd_thread), - .ocd_core(ocd_core), - .ocd_inject_inst(ocd_inject_inst), - .ocd_inject_en(ocd_inject_en), - .ocd_data_from_host(ocd_data_from_host), - .ocd_data_update(ocd_data_update) - ); - end - end - endgenerate - assign u_nyuzi.clk = clk; - assign u_nyuzi.reset = reset; - assign u_nyuzi.interrupt_req = interrupt_req; -endmodule \ No newline at end of file diff --git a/designs/src/NyuziProcessor/dev/NyuziProcessor.v b/designs/src/NyuziProcessor/dev/NyuziProcessor.v deleted file mode 100644 index 54684fc..0000000 --- a/designs/src/NyuziProcessor/dev/NyuziProcessor.v +++ /dev/null @@ -1,7723 +0,0 @@ -module cache_lru ( - clk, - reset, - fill_en, - fill_set, - fill_way, - access_en, - access_set, - update_en, - update_way -); - reg _sv2v_0; - parameter NUM_SETS = 1; - parameter NUM_WAYS = 4; - parameter SET_INDEX_WIDTH = $clog2(NUM_SETS); - parameter WAY_INDEX_WIDTH = $clog2(NUM_WAYS); - input clk; - input reset; - input fill_en; - input [SET_INDEX_WIDTH - 1:0] fill_set; - output reg [WAY_INDEX_WIDTH - 1:0] fill_way; - input access_en; - input [SET_INDEX_WIDTH - 1:0] access_set; - input update_en; - input [WAY_INDEX_WIDTH - 1:0] update_way; - localparam LRU_FLAG_BITS = (NUM_WAYS == 1 ? 1 : (NUM_WAYS == 2 ? 1 : (NUM_WAYS == 4 ? 3 : 7))); - wire [LRU_FLAG_BITS - 1:0] lru_flags; - wire update_lru_en; - reg [SET_INDEX_WIDTH - 1:0] update_set; - reg [LRU_FLAG_BITS - 1:0] update_flags; - wire [SET_INDEX_WIDTH - 1:0] read_set; - wire read_en; - reg was_fill; - wire [WAY_INDEX_WIDTH - 1:0] new_mru; - assign read_en = access_en || fill_en; - assign read_set = (fill_en ? fill_set : access_set); - assign new_mru = (was_fill ? fill_way : update_way); - assign update_lru_en = was_fill || update_en; - reg [LRU_FLAG_BITS - 1:0] pass_thru_dat; - reg [LRU_FLAG_BITS - 1:0] mem; - reg pass_through_en; - always @(posedge clk) begin - pass_through_en <= (update_lru_en && read_en) && (read_set == update_set); - pass_thru_dat <= update_flags; - if (update_lru_en) - mem <= update_flags; - end - assign lru_flags = (pass_through_en ? pass_thru_dat : mem); - generate - case (NUM_WAYS) - 1: begin : genblk1 - wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4850; - assign sv2v_tmp_F4850 = 0; - always @(*) fill_way = sv2v_tmp_F4850; - wire [LRU_FLAG_BITS:1] sv2v_tmp_6C66A; - assign sv2v_tmp_6C66A = 0; - always @(*) update_flags = sv2v_tmp_6C66A; - end - 2: begin : genblk1 - wire [WAY_INDEX_WIDTH:1] sv2v_tmp_F4B2A; - assign sv2v_tmp_F4B2A = !lru_flags[0]; - always @(*) fill_way = sv2v_tmp_F4B2A; - wire [1:1] sv2v_tmp_0C2DF; - assign sv2v_tmp_0C2DF = !new_mru; - always @(*) update_flags[0] = sv2v_tmp_0C2DF; - end - 4: begin : genblk1 - always @(*) begin - if (_sv2v_0) - ; - casez (lru_flags) - 3'b00z: fill_way = 0; - 3'b10z: fill_way = 1; - 3'bz10: fill_way = 2; - 3'bz11: fill_way = 3; - default: fill_way = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - case (new_mru) - 2'd0: update_flags = {2'b11, lru_flags[0]}; - 2'd1: update_flags = {2'b01, lru_flags[0]}; - 2'd2: update_flags = {lru_flags[2], 2'b01}; - 2'd3: update_flags = {lru_flags[2], 2'b00}; - default: update_flags = 1'sb0; - endcase - end - end - 8: begin : genblk1 - always @(*) begin - if (_sv2v_0) - ; - casez (lru_flags) - 7'b00z0zzz: fill_way = 0; - 7'b10z0zzz: fill_way = 1; - 7'bz100zzz: fill_way = 2; - 7'bz110zzz: fill_way = 3; - 7'bzzz100z: fill_way = 4; - 7'bzzz110z: fill_way = 5; - 7'bzzz1z10: fill_way = 6; - 7'bzzz1z11: fill_way = 7; - default: fill_way = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - case (new_mru) - 3'd0: update_flags = {2'b11, lru_flags[5], 1'b1, lru_flags[2:0]}; - 3'd1: update_flags = {2'b01, lru_flags[5], 1'b1, lru_flags[2:0]}; - 3'd2: update_flags = {lru_flags[6], 3'b011, lru_flags[2:0]}; - 3'd3: update_flags = {lru_flags[6], 3'b001, lru_flags[2:0]}; - 3'd4: update_flags = {lru_flags[6:4], 3'b011, lru_flags[0]}; - 3'd5: update_flags = {lru_flags[6:4], 3'b001, lru_flags[0]}; - 3'd6: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b01}; - 3'd7: update_flags = {lru_flags[6:4], 1'b0, lru_flags[2], 2'b00}; - default: update_flags = 1'sb0; - endcase - end - end - default: begin : genblk1 - initial begin - $display("%m invalid number of ways"); - $finish; - end - end - endcase - endgenerate - always @(posedge clk) begin - update_set <= read_set; - was_fill <= fill_en; - end - initial _sv2v_0 = 0; -endmodule -module cam ( - clk, - reset, - lookup_key, - lookup_idx, - lookup_hit, - update_en, - update_key, - update_idx, - update_valid -); - parameter NUM_ENTRIES = 2; - parameter KEY_WIDTH = 32; - parameter INDEX_WIDTH = $clog2(NUM_ENTRIES); - input clk; - input reset; - input [KEY_WIDTH - 1:0] lookup_key; - output wire [INDEX_WIDTH - 1:0] lookup_idx; - output wire lookup_hit; - input update_en; - input [KEY_WIDTH - 1:0] update_key; - input [INDEX_WIDTH - 1:0] update_idx; - input update_valid; - reg [KEY_WIDTH - 1:0] lookup_table [0:NUM_ENTRIES - 1]; - reg [NUM_ENTRIES - 1:0] entry_valid; - wire [NUM_ENTRIES - 1:0] hit_oh; - genvar _gv_test_index_1; - generate - for (_gv_test_index_1 = 0; _gv_test_index_1 < NUM_ENTRIES; _gv_test_index_1 = _gv_test_index_1 + 1) begin : lookup_gen - localparam test_index = _gv_test_index_1; - assign hit_oh[test_index] = entry_valid[test_index] && (lookup_table[test_index] == lookup_key); - end - endgenerate - assign lookup_hit = |hit_oh; - oh_to_idx #(.NUM_SIGNALS(NUM_ENTRIES)) oh_to_idx_hit( - .one_hot(hit_oh), - .index(lookup_idx) - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < NUM_ENTRIES; i = i + 1) - entry_valid[i] <= 1'b0; - end - else if (update_en) - entry_valid[update_idx] <= update_valid; - always @(posedge clk) - if (update_en) - lookup_table[update_idx] <= update_key; -endmodule -module control_registers ( - clk, - reset, - interrupt_req, - cr_eret_address, - cr_mmu_en, - cr_supervisor_en, - cr_current_asid, - cr_suspend_thread, - cr_resume_thread, - cr_interrupt_pending, - cr_interrupt_en, - dt_thread_idx, - dd_creg_write_en, - dd_creg_read_en, - dd_creg_index, - dd_creg_write_val, - wb_trap, - wb_eret, - wb_trap_cause, - wb_trap_pc, - wb_trap_access_vaddr, - wb_rollback_thread_idx, - wb_trap_subcycle, - wb_syscall_index, - cr_creg_read_val, - cr_eret_subcycle, - cr_trap_handler, - cr_tlb_miss_handler, - cr_perf_event_select0, - cr_perf_event_select1, - perf_event_count0, - perf_event_count1, - ocd_data_from_host, - ocd_data_update, - cr_data_to_host -); - parameter CORE_ID = 0; - parameter NUM_INTERRUPTS = 16; - parameter NUM_PERF_EVENTS = 8; - parameter EVENT_IDX_WIDTH = $clog2(NUM_PERF_EVENTS); - input clk; - input reset; - input [NUM_INTERRUPTS - 1:0] interrupt_req; - output wire [127:0] cr_eret_address; - output wire [0:3] cr_mmu_en; - output wire [0:3] cr_supervisor_en; - localparam defines_ASID_WIDTH = 8; - output reg [31:0] cr_current_asid; - localparam defines_TOTAL_THREADS = 4; - output reg [3:0] cr_suspend_thread; - output reg [3:0] cr_resume_thread; - output wire [3:0] cr_interrupt_pending; - output wire [3:0] cr_interrupt_en; - input wire [1:0] dt_thread_idx; - input dd_creg_write_en; - input dd_creg_read_en; - input wire [4:0] dd_creg_index; - input wire [31:0] dd_creg_write_val; - input wb_trap; - input wb_eret; - input wire [5:0] wb_trap_cause; - input wire [31:0] wb_trap_pc; - input wire [31:0] wb_trap_access_vaddr; - input wire [1:0] wb_rollback_thread_idx; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [3:0] wb_trap_subcycle; - input wire [14:0] wb_syscall_index; - output reg [31:0] cr_creg_read_val; - output wire [15:0] cr_eret_subcycle; - output reg [31:0] cr_trap_handler; - output reg [31:0] cr_tlb_miss_handler; - output reg [EVENT_IDX_WIDTH - 1:0] cr_perf_event_select0; - output reg [EVENT_IDX_WIDTH - 1:0] cr_perf_event_select1; - input [63:0] perf_event_count0; - input [63:0] perf_event_count1; - input wire [31:0] ocd_data_from_host; - input ocd_data_update; - output wire [31:0] cr_data_to_host; - localparam TRAP_LEVELS = 3; - reg [155:0] trap_state [0:3][0:2]; - reg [31:0] page_dir_base [0:3]; - reg [31:0] cycle_count; - reg [NUM_INTERRUPTS - 1:0] interrupt_mask [0:3]; - wire [NUM_INTERRUPTS - 1:0] interrupt_pending [0:3]; - reg [NUM_INTERRUPTS - 1:0] interrupt_edge_latched [0:3]; - reg [NUM_INTERRUPTS - 1:0] int_trigger_type; - reg [NUM_INTERRUPTS - 1:0] interrupt_req_prev; - wire [NUM_INTERRUPTS - 1:0] interrupt_edge; - reg [31:0] jtag_data; - assign cr_data_to_host = jtag_data; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - function automatic [3:0] sv2v_cast_60D1B; - input reg [3:0] inp; - sv2v_cast_60D1B = inp; - endfunction - always @(posedge clk or posedge reset) - if (reset) begin - begin : sv2v_autoblock_1 - reg signed [31:0] thread_idx; - for (thread_idx = 0; thread_idx < 4; thread_idx = thread_idx + 1) - begin - trap_state[thread_idx][0] <= 1'sb0; - trap_state[thread_idx][0][155] <= 1'b1; - cr_current_asid[(3 - thread_idx) * 8+:8] <= 1'sb0; - page_dir_base[thread_idx] <= 1'sb0; - interrupt_mask[thread_idx] <= 1'sb0; - end - end - jtag_data <= 1'sb0; - cr_tlb_miss_handler <= 1'sb0; - cr_trap_handler <= 1'sb0; - cycle_count <= 1'sb0; - int_trigger_type <= 1'sb0; - cr_suspend_thread <= 1'sb0; - cr_resume_thread <= 1'sb0; - cr_perf_event_select0 <= 1'sb0; - cr_perf_event_select1 <= 1'sb0; - end - else begin - cycle_count <= cycle_count + 1; - if (wb_trap) begin - begin : sv2v_autoblock_2 - reg signed [31:0] level; - for (level = 0; level < 2; level = level + 1) - trap_state[wb_rollback_thread_idx][level + 1] <= trap_state[wb_rollback_thread_idx][level]; - end - trap_state[wb_rollback_thread_idx][0][88-:6] <= wb_trap_cause; - trap_state[wb_rollback_thread_idx][0][82-:32] <= wb_trap_pc; - trap_state[wb_rollback_thread_idx][0][50-:32] <= wb_trap_access_vaddr; - trap_state[wb_rollback_thread_idx][0][14-:15] <= wb_syscall_index; - trap_state[wb_rollback_thread_idx][0][18-:4] <= wb_trap_subcycle; - trap_state[wb_rollback_thread_idx][0][153] <= 0; - trap_state[wb_rollback_thread_idx][0][155] <= 1; - if (wb_trap_cause[3-:4] == 4'd7) - trap_state[wb_rollback_thread_idx][0][154] <= 0; - end - if (wb_eret) begin : sv2v_autoblock_3 - reg signed [31:0] level; - for (level = 0; level < 2; level = level + 1) - trap_state[wb_rollback_thread_idx][level] <= trap_state[wb_rollback_thread_idx][level + 1]; - end - cr_suspend_thread <= 1'sb0; - cr_resume_thread <= 1'sb0; - if (dd_creg_write_en) - (* full_case, parallel_case *) - case (dd_creg_index) - 5'd4: trap_state[dt_thread_idx][0][155-:3] <= sv2v_cast_3(dd_creg_write_val); - 5'd8: trap_state[dt_thread_idx][1][155-:3] <= sv2v_cast_3(dd_creg_write_val); - 5'd2: trap_state[dt_thread_idx][0][82-:32] <= dd_creg_write_val; - 5'd1: cr_trap_handler <= dd_creg_write_val; - 5'd7: cr_tlb_miss_handler <= dd_creg_write_val; - 5'd11: trap_state[dt_thread_idx][0][152-:32] <= dd_creg_write_val; - 5'd12: trap_state[dt_thread_idx][0][120-:32] <= dd_creg_write_val; - 5'd13: trap_state[dt_thread_idx][0][18-:4] <= sv2v_cast_60D1B(dd_creg_write_val); - 5'd9: cr_current_asid[(3 - dt_thread_idx) * 8+:8] <= dd_creg_write_val[7:0]; - 5'd10: page_dir_base[dt_thread_idx] <= dd_creg_write_val; - 5'd14: interrupt_mask[dt_thread_idx] <= dd_creg_write_val[NUM_INTERRUPTS - 1:0]; - 5'd17: int_trigger_type <= dd_creg_write_val[NUM_INTERRUPTS - 1:0]; - 5'd18: jtag_data <= dd_creg_write_val; - 5'd20: cr_suspend_thread <= dd_creg_write_val[3:0]; - 5'd21: cr_resume_thread <= dd_creg_write_val[3:0]; - 5'd22: cr_perf_event_select0 <= dd_creg_write_val[EVENT_IDX_WIDTH - 1:0]; - 5'd23: cr_perf_event_select1 <= dd_creg_write_val[EVENT_IDX_WIDTH - 1:0]; - default: - ; - endcase - else if (ocd_data_update) - jtag_data <= ocd_data_from_host; - end - always @(posedge clk or posedge reset) - if (reset) - interrupt_req_prev <= 1'sb0; - else - interrupt_req_prev <= interrupt_req; - assign interrupt_edge = interrupt_req & ~interrupt_req_prev; - genvar _gv_thread_idx_1; - generate - for (_gv_thread_idx_1 = 0; _gv_thread_idx_1 < 4; _gv_thread_idx_1 = _gv_thread_idx_1 + 1) begin : interrupt_gen - localparam thread_idx = _gv_thread_idx_1; - wire [NUM_INTERRUPTS - 1:0] interrupt_ack; - wire do_interrupt_ack; - assign do_interrupt_ack = ((dt_thread_idx == thread_idx) && dd_creg_write_en) && (dd_creg_index == 5'd15); - assign interrupt_ack = {NUM_INTERRUPTS {do_interrupt_ack}} & dd_creg_write_val[NUM_INTERRUPTS - 1:0]; - assign cr_interrupt_en[thread_idx] = trap_state[thread_idx][0][153]; - assign cr_supervisor_en[thread_idx] = trap_state[thread_idx][0][155]; - assign cr_mmu_en[thread_idx] = trap_state[thread_idx][0][154]; - assign cr_eret_subcycle[(3 - thread_idx) * 4+:4] = trap_state[thread_idx][0][18-:4]; - assign cr_eret_address[(3 - thread_idx) * 32+:32] = trap_state[thread_idx][0][82-:32]; - always @(posedge clk or posedge reset) - if (reset) - interrupt_edge_latched[thread_idx] <= 1'sb0; - else - interrupt_edge_latched[thread_idx] <= (interrupt_edge_latched[thread_idx] & ~interrupt_ack) | interrupt_edge; - assign interrupt_pending[thread_idx] = (int_trigger_type & interrupt_req) | (~int_trigger_type & interrupt_edge_latched[thread_idx]); - assign cr_interrupt_pending[thread_idx] = |(interrupt_pending[thread_idx] & interrupt_mask[thread_idx]); - end - endgenerate - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(posedge clk) - if (dd_creg_read_en) - (* full_case, parallel_case *) - case (dd_creg_index) - 5'd4: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][155-:3]); - 5'd8: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][1][155-:3]); - 5'd0: cr_creg_read_val <= sv2v_cast_32({CORE_ID, dt_thread_idx}); - 5'd2: cr_creg_read_val <= trap_state[dt_thread_idx][0][82-:32]; - 5'd3: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][88-:6]); - 5'd1: cr_creg_read_val <= cr_trap_handler; - 5'd5: cr_creg_read_val <= trap_state[dt_thread_idx][0][50-:32]; - 5'd7: cr_creg_read_val <= cr_tlb_miss_handler; - 5'd6: cr_creg_read_val <= cycle_count; - 5'd11: cr_creg_read_val <= trap_state[dt_thread_idx][0][152-:32]; - 5'd12: cr_creg_read_val <= trap_state[dt_thread_idx][0][120-:32]; - 5'd13: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][18-:4]); - 5'd9: cr_creg_read_val <= sv2v_cast_32(cr_current_asid[(3 - dt_thread_idx) * 8+:8]); - 5'd10: cr_creg_read_val <= page_dir_base[dt_thread_idx]; - 5'd16: cr_creg_read_val <= sv2v_cast_32(interrupt_pending[dt_thread_idx] & interrupt_mask[dt_thread_idx]); - 5'd14: cr_creg_read_val <= sv2v_cast_32(interrupt_mask[dt_thread_idx]); - 5'd17: cr_creg_read_val <= sv2v_cast_32(int_trigger_type); - 5'd18: cr_creg_read_val <= jtag_data; - 5'd19: cr_creg_read_val <= sv2v_cast_32(trap_state[dt_thread_idx][0][14-:15]); - 5'd24: cr_creg_read_val <= perf_event_count0[31:0]; - 5'd25: cr_creg_read_val <= perf_event_count0[63:32]; - 5'd26: cr_creg_read_val <= perf_event_count1[31:0]; - 5'd27: cr_creg_read_val <= perf_event_count1[63:32]; - default: cr_creg_read_val <= 32'hffffffff; - endcase -endmodule -module core ( - clk, - reset, - thread_en, - interrupt_req, - l2_ready, - l2_response_valid, - l2_response, - l2i_request_valid, - l2i_request, - ii_ready, - ii_response_valid, - ii_response, - ior_request_valid, - ior_request, - ocd_halt, - ocd_thread, - ocd_core, - ocd_inject_inst, - ocd_inject_en, - injected_complete, - injected_rollback, - ocd_data_from_host, - ocd_data_update, - cr_data_to_host, - cr_suspend_thread, - cr_resume_thread -); - parameter CORE_ID = 1'sb0; - parameter RESET_PC = 1'sb0; - parameter NUM_INTERRUPTS = 16; - input clk; - input reset; - input wire [3:0] thread_en; - input [NUM_INTERRUPTS - 1:0] interrupt_req; - input l2_ready; - input l2_response_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [548:0] l2_response; - output wire l2i_request_valid; - output wire [611:0] l2i_request; - input ii_ready; - input ii_response_valid; - input wire [37:0] ii_response; - output wire ior_request_valid; - output wire [66:0] ior_request; - input ocd_halt; - input wire [1:0] ocd_thread; - input wire [3:0] ocd_core; - input wire [31:0] ocd_inject_inst; - input ocd_inject_en; - output reg injected_complete; - output reg injected_rollback; - input wire [31:0] ocd_data_from_host; - input ocd_data_update; - output wire [31:0] cr_data_to_host; - localparam defines_TOTAL_THREADS = 4; - output wire [3:0] cr_suspend_thread; - output wire [3:0] cr_resume_thread; - localparam defines_CORE_PERF_EVENTS = 14; - localparam EVENT_IDX_WIDTH = 4; - localparam NUM_PERF_COUNTERS = 2; - wire core_selected_debug; - wire [13:0] perf_events; - wire [7:0] perf_event_select; - wire [31:0] cr_creg_read_val; - localparam defines_ASID_WIDTH = 8; - wire [31:0] cr_current_asid; - wire [127:0] cr_eret_address; - wire [15:0] cr_eret_subcycle; - wire [3:0] cr_interrupt_en; - wire [3:0] cr_interrupt_pending; - wire [0:3] cr_mmu_en; - wire [0:3] cr_supervisor_en; - wire [31:0] cr_tlb_miss_handler; - wire [31:0] cr_trap_handler; - wire dd_cache_miss; - wire [25:0] dd_cache_miss_addr; - wire dd_cache_miss_sync; - wire [1:0] dd_cache_miss_thread_idx; - wire [4:0] dd_creg_index; - wire dd_creg_read_en; - wire dd_creg_write_en; - wire [31:0] dd_creg_write_val; - wire dd_dinvalidate_en; - wire dd_flush_en; - wire dd_iinvalidate_en; - wire [141:0] dd_instruction; - wire dd_instruction_valid; - wire dd_io_access; - wire [31:0] dd_io_addr; - wire dd_io_read_en; - wire [1:0] dd_io_thread_idx; - wire dd_io_write_en; - wire [31:0] dd_io_write_value; - wire [15:0] dd_lane_mask; - wire [511:0] dd_load_data; - wire [3:0] dd_load_sync_pending; - wire dd_membar_en; - wire dd_perf_dcache_hit; - wire dd_perf_dcache_miss; - wire dd_perf_dtlb_miss; - localparam defines_DCACHE_TAG_BITS = 20; - wire [31:0] dd_request_vaddr; - wire dd_rollback_en; - wire [31:0] dd_rollback_pc; - wire [25:0] dd_store_addr; - wire [25:0] dd_store_bypass_addr; - wire [1:0] dd_store_bypass_thread_idx; - wire [511:0] dd_store_data; - wire dd_store_en; - wire [63:0] dd_store_mask; - wire dd_store_sync; - wire [1:0] dd_store_thread_idx; - wire [3:0] dd_subcycle; - wire dd_suspend_thread; - wire [1:0] dd_thread_idx; - wire dd_trap; - wire [5:0] dd_trap_cause; - wire dd_update_lru_en; - wire [1:0] dd_update_lru_way; - wire [1:0] dt_fill_lru; - wire [141:0] dt_instruction; - wire dt_instruction_valid; - wire dt_invalidate_tlb_all_en; - wire dt_invalidate_tlb_en; - wire [15:0] dt_mask_value; - wire [31:0] dt_request_paddr; - wire [31:0] dt_request_vaddr; - wire [79:0] dt_snoop_tag; - wire [0:3] dt_snoop_valid; - wire [511:0] dt_store_value; - wire [3:0] dt_subcycle; - wire [79:0] dt_tag; - wire [1:0] dt_thread_idx; - wire dt_tlb_hit; - wire dt_tlb_present; - wire dt_tlb_supervisor; - wire dt_tlb_writable; - wire [7:0] dt_update_itlb_asid; - wire dt_update_itlb_en; - wire dt_update_itlb_executable; - wire dt_update_itlb_global; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_ppage_idx; - wire dt_update_itlb_present; - wire dt_update_itlb_supervisor; - wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_vpage_idx; - wire [0:3] dt_valid; - wire [127:0] fx1_add_exponent; - wire [15:0] fx1_add_result_sign; - wire [15:0] fx1_equal; - wire [95:0] fx1_ftoi_lshift; - wire [141:0] fx1_instruction; - wire fx1_instruction_valid; - wire [15:0] fx1_logical_subtract; - wire [15:0] fx1_mask_value; - wire [127:0] fx1_mul_exponent; - wire [15:0] fx1_mul_sign; - wire [15:0] fx1_mul_underflow; - wire [511:0] fx1_multiplicand; - wire [511:0] fx1_multiplier; - wire [15:0] fx1_result_inf; - wire [15:0] fx1_result_nan; - wire [95:0] fx1_se_align_shift; - wire [511:0] fx1_significand_le; - wire [511:0] fx1_significand_se; - wire [3:0] fx1_subcycle; - wire [1:0] fx1_thread_idx; - wire [127:0] fx2_add_exponent; - wire [15:0] fx2_add_result_sign; - wire [15:0] fx2_equal; - wire [95:0] fx2_ftoi_lshift; - wire [15:0] fx2_guard; - wire [141:0] fx2_instruction; - wire fx2_instruction_valid; - wire [15:0] fx2_logical_subtract; - wire [15:0] fx2_mask_value; - wire [127:0] fx2_mul_exponent; - wire [15:0] fx2_mul_sign; - wire [15:0] fx2_mul_underflow; - wire [15:0] fx2_result_inf; - wire [15:0] fx2_result_nan; - wire [15:0] fx2_round; - wire [511:0] fx2_significand_le; - wire [1023:0] fx2_significand_product; - wire [511:0] fx2_significand_se; - wire [15:0] fx2_sticky; - wire [3:0] fx2_subcycle; - wire [1:0] fx2_thread_idx; - wire [127:0] fx3_add_exponent; - wire [15:0] fx3_add_result_sign; - wire [511:0] fx3_add_significand; - wire [15:0] fx3_equal; - wire [95:0] fx3_ftoi_lshift; - wire [141:0] fx3_instruction; - wire fx3_instruction_valid; - wire [15:0] fx3_logical_subtract; - wire [15:0] fx3_mask_value; - wire [127:0] fx3_mul_exponent; - wire [15:0] fx3_mul_sign; - wire [15:0] fx3_mul_underflow; - wire [15:0] fx3_result_inf; - wire [15:0] fx3_result_nan; - wire [1023:0] fx3_significand_product; - wire [3:0] fx3_subcycle; - wire [1:0] fx3_thread_idx; - wire [127:0] fx4_add_exponent; - wire [15:0] fx4_add_result_sign; - wire [511:0] fx4_add_significand; - wire [15:0] fx4_equal; - wire [141:0] fx4_instruction; - wire fx4_instruction_valid; - wire [15:0] fx4_logical_subtract; - wire [15:0] fx4_mask_value; - wire [127:0] fx4_mul_exponent; - wire [15:0] fx4_mul_sign; - wire [15:0] fx4_mul_underflow; - wire [95:0] fx4_norm_shift; - wire [15:0] fx4_result_inf; - wire [15:0] fx4_result_nan; - wire [1023:0] fx4_significand_product; - wire [3:0] fx4_subcycle; - wire [1:0] fx4_thread_idx; - wire [141:0] fx5_instruction; - wire fx5_instruction_valid; - wire [15:0] fx5_mask_value; - wire [511:0] fx5_result; - wire [3:0] fx5_subcycle; - wire [1:0] fx5_thread_idx; - wire [141:0] id_instruction; - wire id_instruction_valid; - wire [1:0] id_thread_idx; - wire ifd_alignment_fault; - wire ifd_cache_miss; - wire [25:0] ifd_cache_miss_paddr; - wire [1:0] ifd_cache_miss_thread_idx; - wire ifd_executable_fault; - wire ifd_inst_injected; - wire [31:0] ifd_instruction; - wire ifd_instruction_valid; - wire ifd_near_miss; - wire ifd_page_fault; - wire [31:0] ifd_pc; - wire ifd_perf_icache_hit; - wire ifd_perf_icache_miss; - wire ifd_perf_itlb_miss; - wire ifd_supervisor_fault; - wire [1:0] ifd_thread_idx; - wire ifd_tlb_miss; - wire ifd_update_lru_en; - wire [1:0] ifd_update_lru_way; - wire [1:0] ift_fill_lru; - wire ift_instruction_requested; - localparam defines_ICACHE_TAG_BITS = 20; - wire [31:0] ift_pc_paddr; - wire [31:0] ift_pc_vaddr; - wire [79:0] ift_tag; - wire [1:0] ift_thread_idx; - wire ift_tlb_executable; - wire ift_tlb_hit; - wire ift_tlb_present; - wire ift_tlb_supervisor; - wire [0:3] ift_valid; - wire [3:0] ior_pending; - wire [31:0] ior_read_value; - wire ior_rollback_en; - wire [3:0] ior_wake_bitmap; - wire [141:0] ix_instruction; - wire ix_instruction_valid; - wire [15:0] ix_mask_value; - wire ix_perf_cond_branch_not_taken; - wire ix_perf_cond_branch_taken; - wire ix_perf_uncond_branch; - wire ix_privileged_op_fault; - wire [511:0] ix_result; - wire ix_rollback_en; - wire [31:0] ix_rollback_pc; - wire [3:0] ix_subcycle; - wire [1:0] ix_thread_idx; - wire l2i_dcache_lru_fill_en; - wire [5:0] l2i_dcache_lru_fill_set; - wire [3:0] l2i_dcache_wake_bitmap; - wire [511:0] l2i_ddata_update_data; - wire l2i_ddata_update_en; - wire [5:0] l2i_ddata_update_set; - wire [1:0] l2i_ddata_update_way; - wire [3:0] l2i_dtag_update_en_oh; - wire [5:0] l2i_dtag_update_set; - wire [19:0] l2i_dtag_update_tag; - wire l2i_dtag_update_valid; - wire l2i_icache_lru_fill_en; - wire [5:0] l2i_icache_lru_fill_set; - wire [3:0] l2i_icache_wake_bitmap; - wire [511:0] l2i_idata_update_data; - wire l2i_idata_update_en; - wire [5:0] l2i_idata_update_set; - wire [1:0] l2i_idata_update_way; - wire [3:0] l2i_itag_update_en; - wire [5:0] l2i_itag_update_set; - wire [19:0] l2i_itag_update_tag; - wire l2i_itag_update_valid; - wire l2i_perf_store; - wire l2i_snoop_en; - wire [5:0] l2i_snoop_set; - wire [141:0] of_instruction; - wire of_instruction_valid; - wire [15:0] of_mask_value; - wire [511:0] of_operand1; - wire [511:0] of_operand2; - wire [511:0] of_store_value; - wire [3:0] of_subcycle; - wire [1:0] of_thread_idx; - wire [127:0] perf_event_count; - wire sq_rollback_en; - wire [511:0] sq_store_bypass_data; - wire [63:0] sq_store_bypass_mask; - wire [3:0] sq_store_sync_pending; - wire sq_store_sync_success; - wire [3:0] ts_fetch_en; - wire [141:0] ts_instruction; - wire ts_instruction_valid; - wire ts_perf_instruction_issue; - wire [3:0] ts_subcycle; - wire [1:0] ts_thread_idx; - wire wb_eret; - wire wb_inst_injected; - wire wb_perf_instruction_retire; - wire wb_perf_interrupt; - wire wb_perf_store_rollback; - wire wb_rollback_en; - wire [31:0] wb_rollback_pc; - wire [1:0] wb_rollback_pipeline; - wire [3:0] wb_rollback_subcycle; - wire [1:0] wb_rollback_thread_idx; - wire [3:0] wb_suspend_thread_oh; - wire [14:0] wb_syscall_index; - wire wb_trap; - wire [31:0] wb_trap_access_vaddr; - wire [5:0] wb_trap_cause; - wire [31:0] wb_trap_pc; - wire [3:0] wb_trap_subcycle; - wire wb_writeback_en; - wire wb_writeback_last_subcycle; - wire [15:0] wb_writeback_mask; - wire [4:0] wb_writeback_reg; - wire [1:0] wb_writeback_thread_idx; - wire [511:0] wb_writeback_value; - wire wb_writeback_vector; - ifetch_tag_stage #(.RESET_PC(RESET_PC)) ifetch_tag_stage( - .clk(clk), - .reset(reset), - .ifd_update_lru_en(ifd_update_lru_en), - .ifd_update_lru_way(ifd_update_lru_way), - .ifd_cache_miss(ifd_cache_miss), - .ifd_near_miss(ifd_near_miss), - .ifd_cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .ift_instruction_requested(ift_instruction_requested), - .ift_pc_paddr(ift_pc_paddr), - .ift_pc_vaddr(ift_pc_vaddr), - .ift_thread_idx(ift_thread_idx), - .ift_tlb_hit(ift_tlb_hit), - .ift_tlb_present(ift_tlb_present), - .ift_tlb_executable(ift_tlb_executable), - .ift_tlb_supervisor(ift_tlb_supervisor), - .ift_tag(ift_tag), - .ift_valid(ift_valid), - .l2i_icache_lru_fill_en(l2i_icache_lru_fill_en), - .l2i_icache_lru_fill_set(l2i_icache_lru_fill_set), - .l2i_itag_update_en(l2i_itag_update_en), - .l2i_itag_update_set(l2i_itag_update_set), - .l2i_itag_update_tag(l2i_itag_update_tag), - .l2i_itag_update_valid(l2i_itag_update_valid), - .l2i_icache_wake_bitmap(l2i_icache_wake_bitmap), - .ift_fill_lru(ift_fill_lru), - .cr_mmu_en(cr_mmu_en), - .cr_current_asid(cr_current_asid), - .dt_invalidate_tlb_en(dt_invalidate_tlb_en), - .dt_invalidate_tlb_all_en(dt_invalidate_tlb_all_en), - .dt_update_itlb_asid(dt_update_itlb_asid), - .dt_update_itlb_vpage_idx(dt_update_itlb_vpage_idx), - .dt_update_itlb_en(dt_update_itlb_en), - .dt_update_itlb_supervisor(dt_update_itlb_supervisor), - .dt_update_itlb_global(dt_update_itlb_global), - .dt_update_itlb_present(dt_update_itlb_present), - .dt_update_itlb_executable(dt_update_itlb_executable), - .dt_update_itlb_ppage_idx(dt_update_itlb_ppage_idx), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pc(wb_rollback_pc), - .ts_fetch_en(ts_fetch_en), - .ocd_halt(ocd_halt), - .ocd_thread(ocd_thread) - ); - ifetch_data_stage ifetch_data_stage( - .clk(clk), - .reset(reset), - .ift_instruction_requested(ift_instruction_requested), - .ift_pc_paddr(ift_pc_paddr), - .ift_pc_vaddr(ift_pc_vaddr), - .ift_thread_idx(ift_thread_idx), - .ift_tlb_hit(ift_tlb_hit), - .ift_tlb_present(ift_tlb_present), - .ift_tlb_executable(ift_tlb_executable), - .ift_tlb_supervisor(ift_tlb_supervisor), - .ift_tag(ift_tag), - .ift_valid(ift_valid), - .ifd_update_lru_en(ifd_update_lru_en), - .ifd_update_lru_way(ifd_update_lru_way), - .ifd_near_miss(ifd_near_miss), - .l2i_idata_update_en(l2i_idata_update_en), - .l2i_idata_update_way(l2i_idata_update_way), - .l2i_idata_update_set(l2i_idata_update_set), - .l2i_idata_update_data(l2i_idata_update_data), - .l2i_itag_update_en(l2i_itag_update_en), - .l2i_itag_update_set(l2i_itag_update_set), - .l2i_itag_update_tag(l2i_itag_update_tag), - .ifd_cache_miss(ifd_cache_miss), - .ifd_cache_miss_paddr(ifd_cache_miss_paddr), - .ifd_cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .cr_supervisor_en(cr_supervisor_en), - .ifd_instruction(ifd_instruction), - .ifd_instruction_valid(ifd_instruction_valid), - .ifd_pc(ifd_pc), - .ifd_thread_idx(ifd_thread_idx), - .ifd_alignment_fault(ifd_alignment_fault), - .ifd_tlb_miss(ifd_tlb_miss), - .ifd_supervisor_fault(ifd_supervisor_fault), - .ifd_page_fault(ifd_page_fault), - .ifd_executable_fault(ifd_executable_fault), - .ifd_inst_injected(ifd_inst_injected), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .ifd_perf_icache_hit(ifd_perf_icache_hit), - .ifd_perf_icache_miss(ifd_perf_icache_miss), - .ifd_perf_itlb_miss(ifd_perf_itlb_miss), - .core_selected_debug(core_selected_debug), - .ocd_halt(ocd_halt), - .ocd_inject_inst(ocd_inject_inst), - .ocd_inject_en(ocd_inject_en), - .ocd_thread(ocd_thread) - ); - instruction_decode_stage instruction_decode_stage( - .clk(clk), - .reset(reset), - .ifd_instruction_valid(ifd_instruction_valid), - .ifd_instruction(ifd_instruction), - .ifd_inst_injected(ifd_inst_injected), - .ifd_pc(ifd_pc), - .ifd_thread_idx(ifd_thread_idx), - .ifd_alignment_fault(ifd_alignment_fault), - .ifd_supervisor_fault(ifd_supervisor_fault), - .ifd_page_fault(ifd_page_fault), - .ifd_executable_fault(ifd_executable_fault), - .ifd_tlb_miss(ifd_tlb_miss), - .dd_load_sync_pending(dd_load_sync_pending), - .sq_store_sync_pending(sq_store_sync_pending), - .id_instruction(id_instruction), - .id_instruction_valid(id_instruction_valid), - .id_thread_idx(id_thread_idx), - .ior_pending(ior_pending), - .cr_interrupt_en(cr_interrupt_en), - .cr_interrupt_pending(cr_interrupt_pending), - .ocd_halt(ocd_halt), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx) - ); - thread_select_stage thread_select_stage( - .clk(clk), - .reset(reset), - .id_instruction(id_instruction), - .id_instruction_valid(id_instruction_valid), - .id_thread_idx(id_thread_idx), - .ts_fetch_en(ts_fetch_en), - .ts_instruction_valid(ts_instruction_valid), - .ts_instruction(ts_instruction), - .ts_thread_idx(ts_thread_idx), - .ts_subcycle(ts_subcycle), - .wb_writeback_en(wb_writeback_en), - .wb_writeback_thread_idx(wb_writeback_thread_idx), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_reg(wb_writeback_reg), - .wb_writeback_last_subcycle(wb_writeback_last_subcycle), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_pipeline(wb_rollback_pipeline), - .wb_rollback_subcycle(wb_rollback_subcycle), - .thread_en(thread_en), - .wb_suspend_thread_oh(wb_suspend_thread_oh), - .l2i_dcache_wake_bitmap(l2i_dcache_wake_bitmap), - .ior_wake_bitmap(ior_wake_bitmap), - .ts_perf_instruction_issue(ts_perf_instruction_issue) - ); - operand_fetch_stage operand_fetch_stage( - .clk(clk), - .reset(reset), - .ts_instruction_valid(ts_instruction_valid), - .ts_instruction(ts_instruction), - .ts_thread_idx(ts_thread_idx), - .ts_subcycle(ts_subcycle), - .of_operand1(of_operand1), - .of_operand2(of_operand2), - .of_mask_value(of_mask_value), - .of_store_value(of_store_value), - .of_instruction(of_instruction), - .of_instruction_valid(of_instruction_valid), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_writeback_en(wb_writeback_en), - .wb_writeback_thread_idx(wb_writeback_thread_idx), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_value(wb_writeback_value), - .wb_writeback_mask(wb_writeback_mask), - .wb_writeback_reg(wb_writeback_reg) - ); - dcache_data_stage dcache_data_stage( - .clk(clk), - .reset(reset), - .dd_load_sync_pending(dd_load_sync_pending), - .dt_instruction_valid(dt_instruction_valid), - .dt_instruction(dt_instruction), - .dt_mask_value(dt_mask_value), - .dt_thread_idx(dt_thread_idx), - .dt_request_vaddr(dt_request_vaddr), - .dt_request_paddr(dt_request_paddr), - .dt_tlb_hit(dt_tlb_hit), - .dt_tlb_present(dt_tlb_present), - .dt_tlb_supervisor(dt_tlb_supervisor), - .dt_tlb_writable(dt_tlb_writable), - .dt_store_value(dt_store_value), - .dt_subcycle(dt_subcycle), - .dt_valid(dt_valid), - .dt_tag(dt_tag), - .dd_update_lru_en(dd_update_lru_en), - .dd_update_lru_way(dd_update_lru_way), - .dd_io_write_en(dd_io_write_en), - .dd_io_read_en(dd_io_read_en), - .dd_io_thread_idx(dd_io_thread_idx), - .dd_io_addr(dd_io_addr), - .dd_io_write_value(dd_io_write_value), - .dd_instruction_valid(dd_instruction_valid), - .dd_instruction(dd_instruction), - .dd_lane_mask(dd_lane_mask), - .dd_thread_idx(dd_thread_idx), - .dd_request_vaddr(dd_request_vaddr), - .dd_subcycle(dd_subcycle), - .dd_rollback_en(dd_rollback_en), - .dd_rollback_pc(dd_rollback_pc), - .dd_load_data(dd_load_data), - .dd_suspend_thread(dd_suspend_thread), - .dd_io_access(dd_io_access), - .dd_trap(dd_trap), - .dd_trap_cause(dd_trap_cause), - .cr_supervisor_en(cr_supervisor_en), - .dd_creg_write_en(dd_creg_write_en), - .dd_creg_read_en(dd_creg_read_en), - .dd_creg_index(dd_creg_index), - .dd_creg_write_val(dd_creg_write_val), - .l2i_ddata_update_en(l2i_ddata_update_en), - .l2i_ddata_update_way(l2i_ddata_update_way), - .l2i_ddata_update_set(l2i_ddata_update_set), - .l2i_ddata_update_data(l2i_ddata_update_data), - .l2i_dtag_update_en_oh(l2i_dtag_update_en_oh), - .l2i_dtag_update_set(l2i_dtag_update_set), - .l2i_dtag_update_tag(l2i_dtag_update_tag), - .dd_cache_miss(dd_cache_miss), - .dd_cache_miss_addr(dd_cache_miss_addr), - .dd_cache_miss_thread_idx(dd_cache_miss_thread_idx), - .dd_cache_miss_sync(dd_cache_miss_sync), - .dd_store_en(dd_store_en), - .dd_flush_en(dd_flush_en), - .dd_membar_en(dd_membar_en), - .dd_iinvalidate_en(dd_iinvalidate_en), - .dd_dinvalidate_en(dd_dinvalidate_en), - .dd_store_mask(dd_store_mask), - .dd_store_addr(dd_store_addr), - .dd_store_data(dd_store_data), - .dd_store_thread_idx(dd_store_thread_idx), - .dd_store_sync(dd_store_sync), - .dd_store_bypass_addr(dd_store_bypass_addr), - .dd_store_bypass_thread_idx(dd_store_bypass_thread_idx), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pipeline(wb_rollback_pipeline), - .dd_perf_dcache_hit(dd_perf_dcache_hit), - .dd_perf_dcache_miss(dd_perf_dcache_miss), - .dd_perf_dtlb_miss(dd_perf_dtlb_miss) - ); - dcache_tag_stage dcache_tag_stage( - .clk(clk), - .reset(reset), - .of_operand1(of_operand1), - .of_mask_value(of_mask_value), - .of_store_value(of_store_value), - .of_instruction_valid(of_instruction_valid), - .of_instruction(of_instruction), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .dd_update_lru_en(dd_update_lru_en), - .dd_update_lru_way(dd_update_lru_way), - .dt_instruction_valid(dt_instruction_valid), - .dt_instruction(dt_instruction), - .dt_mask_value(dt_mask_value), - .dt_thread_idx(dt_thread_idx), - .dt_request_vaddr(dt_request_vaddr), - .dt_request_paddr(dt_request_paddr), - .dt_tlb_hit(dt_tlb_hit), - .dt_tlb_writable(dt_tlb_writable), - .dt_store_value(dt_store_value), - .dt_subcycle(dt_subcycle), - .dt_valid(dt_valid), - .dt_tag(dt_tag), - .dt_tlb_supervisor(dt_tlb_supervisor), - .dt_tlb_present(dt_tlb_present), - .dt_invalidate_tlb_en(dt_invalidate_tlb_en), - .dt_invalidate_tlb_all_en(dt_invalidate_tlb_all_en), - .dt_update_itlb_en(dt_update_itlb_en), - .dt_update_itlb_asid(dt_update_itlb_asid), - .dt_update_itlb_vpage_idx(dt_update_itlb_vpage_idx), - .dt_update_itlb_ppage_idx(dt_update_itlb_ppage_idx), - .dt_update_itlb_present(dt_update_itlb_present), - .dt_update_itlb_supervisor(dt_update_itlb_supervisor), - .dt_update_itlb_global(dt_update_itlb_global), - .dt_update_itlb_executable(dt_update_itlb_executable), - .l2i_dcache_lru_fill_en(l2i_dcache_lru_fill_en), - .l2i_dcache_lru_fill_set(l2i_dcache_lru_fill_set), - .l2i_dtag_update_en_oh(l2i_dtag_update_en_oh), - .l2i_dtag_update_set(l2i_dtag_update_set), - .l2i_dtag_update_tag(l2i_dtag_update_tag), - .l2i_dtag_update_valid(l2i_dtag_update_valid), - .l2i_snoop_en(l2i_snoop_en), - .l2i_snoop_set(l2i_snoop_set), - .dt_snoop_valid(dt_snoop_valid), - .dt_snoop_tag(dt_snoop_tag), - .dt_fill_lru(dt_fill_lru), - .cr_mmu_en(cr_mmu_en), - .cr_supervisor_en(cr_supervisor_en), - .cr_current_asid(cr_current_asid), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx) - ); - int_execute_stage int_execute_stage( - .clk(clk), - .reset(reset), - .of_operand1(of_operand1), - .of_operand2(of_operand2), - .of_mask_value(of_mask_value), - .of_instruction_valid(of_instruction_valid), - .of_instruction(of_instruction), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .ix_instruction_valid(ix_instruction_valid), - .ix_instruction(ix_instruction), - .ix_result(ix_result), - .ix_mask_value(ix_mask_value), - .ix_thread_idx(ix_thread_idx), - .ix_rollback_en(ix_rollback_en), - .ix_rollback_pc(ix_rollback_pc), - .ix_subcycle(ix_subcycle), - .ix_privileged_op_fault(ix_privileged_op_fault), - .cr_eret_address(cr_eret_address), - .cr_supervisor_en(cr_supervisor_en), - .ix_perf_uncond_branch(ix_perf_uncond_branch), - .ix_perf_cond_branch_taken(ix_perf_cond_branch_taken), - .ix_perf_cond_branch_not_taken(ix_perf_cond_branch_not_taken) - ); - fp_execute_stage1 fp_execute_stage1( - .clk(clk), - .reset(reset), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .of_operand1(of_operand1), - .of_operand2(of_operand2), - .of_mask_value(of_mask_value), - .of_instruction_valid(of_instruction_valid), - .of_instruction(of_instruction), - .of_thread_idx(of_thread_idx), - .of_subcycle(of_subcycle), - .fx1_instruction_valid(fx1_instruction_valid), - .fx1_instruction(fx1_instruction), - .fx1_mask_value(fx1_mask_value), - .fx1_thread_idx(fx1_thread_idx), - .fx1_subcycle(fx1_subcycle), - .fx1_result_inf(fx1_result_inf), - .fx1_result_nan(fx1_result_nan), - .fx1_equal(fx1_equal), - .fx1_ftoi_lshift(fx1_ftoi_lshift), - .fx1_significand_le(fx1_significand_le), - .fx1_significand_se(fx1_significand_se), - .fx1_se_align_shift(fx1_se_align_shift), - .fx1_add_exponent(fx1_add_exponent), - .fx1_logical_subtract(fx1_logical_subtract), - .fx1_add_result_sign(fx1_add_result_sign), - .fx1_multiplicand(fx1_multiplicand), - .fx1_multiplier(fx1_multiplier), - .fx1_mul_exponent(fx1_mul_exponent), - .fx1_mul_underflow(fx1_mul_underflow), - .fx1_mul_sign(fx1_mul_sign) - ); - fp_execute_stage2 fp_execute_stage2( - .clk(clk), - .reset(reset), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pipeline(wb_rollback_pipeline), - .fx1_mask_value(fx1_mask_value), - .fx1_instruction_valid(fx1_instruction_valid), - .fx1_instruction(fx1_instruction), - .fx1_thread_idx(fx1_thread_idx), - .fx1_subcycle(fx1_subcycle), - .fx1_result_inf(fx1_result_inf), - .fx1_result_nan(fx1_result_nan), - .fx1_equal(fx1_equal), - .fx1_ftoi_lshift(fx1_ftoi_lshift), - .fx1_significand_le(fx1_significand_le), - .fx1_significand_se(fx1_significand_se), - .fx1_logical_subtract(fx1_logical_subtract), - .fx1_se_align_shift(fx1_se_align_shift), - .fx1_add_exponent(fx1_add_exponent), - .fx1_add_result_sign(fx1_add_result_sign), - .fx1_mul_exponent(fx1_mul_exponent), - .fx1_mul_sign(fx1_mul_sign), - .fx1_multiplicand(fx1_multiplicand), - .fx1_multiplier(fx1_multiplier), - .fx1_mul_underflow(fx1_mul_underflow), - .fx2_instruction_valid(fx2_instruction_valid), - .fx2_instruction(fx2_instruction), - .fx2_mask_value(fx2_mask_value), - .fx2_thread_idx(fx2_thread_idx), - .fx2_subcycle(fx2_subcycle), - .fx2_result_inf(fx2_result_inf), - .fx2_result_nan(fx2_result_nan), - .fx2_equal(fx2_equal), - .fx2_ftoi_lshift(fx2_ftoi_lshift), - .fx2_logical_subtract(fx2_logical_subtract), - .fx2_add_result_sign(fx2_add_result_sign), - .fx2_significand_le(fx2_significand_le), - .fx2_significand_se(fx2_significand_se), - .fx2_add_exponent(fx2_add_exponent), - .fx2_guard(fx2_guard), - .fx2_round(fx2_round), - .fx2_sticky(fx2_sticky), - .fx2_significand_product(fx2_significand_product), - .fx2_mul_exponent(fx2_mul_exponent), - .fx2_mul_underflow(fx2_mul_underflow), - .fx2_mul_sign(fx2_mul_sign) - ); - fp_execute_stage3 fp_execute_stage3( - .clk(clk), - .reset(reset), - .fx2_mask_value(fx2_mask_value), - .fx2_instruction_valid(fx2_instruction_valid), - .fx2_instruction(fx2_instruction), - .fx2_thread_idx(fx2_thread_idx), - .fx2_subcycle(fx2_subcycle), - .fx2_result_inf(fx2_result_inf), - .fx2_result_nan(fx2_result_nan), - .fx2_equal(fx2_equal), - .fx2_ftoi_lshift(fx2_ftoi_lshift), - .fx2_significand_le(fx2_significand_le), - .fx2_significand_se(fx2_significand_se), - .fx2_logical_subtract(fx2_logical_subtract), - .fx2_add_exponent(fx2_add_exponent), - .fx2_add_result_sign(fx2_add_result_sign), - .fx2_guard(fx2_guard), - .fx2_round(fx2_round), - .fx2_sticky(fx2_sticky), - .fx2_significand_product(fx2_significand_product), - .fx2_mul_exponent(fx2_mul_exponent), - .fx2_mul_underflow(fx2_mul_underflow), - .fx2_mul_sign(fx2_mul_sign), - .fx3_instruction_valid(fx3_instruction_valid), - .fx3_instruction(fx3_instruction), - .fx3_mask_value(fx3_mask_value), - .fx3_thread_idx(fx3_thread_idx), - .fx3_subcycle(fx3_subcycle), - .fx3_result_inf(fx3_result_inf), - .fx3_result_nan(fx3_result_nan), - .fx3_equal(fx3_equal), - .fx3_ftoi_lshift(fx3_ftoi_lshift), - .fx3_add_significand(fx3_add_significand), - .fx3_add_exponent(fx3_add_exponent), - .fx3_add_result_sign(fx3_add_result_sign), - .fx3_logical_subtract(fx3_logical_subtract), - .fx3_significand_product(fx3_significand_product), - .fx3_mul_exponent(fx3_mul_exponent), - .fx3_mul_underflow(fx3_mul_underflow), - .fx3_mul_sign(fx3_mul_sign) - ); - fp_execute_stage4 fp_execute_stage4( - .clk(clk), - .reset(reset), - .fx3_mask_value(fx3_mask_value), - .fx3_instruction_valid(fx3_instruction_valid), - .fx3_instruction(fx3_instruction), - .fx3_thread_idx(fx3_thread_idx), - .fx3_subcycle(fx3_subcycle), - .fx3_result_inf(fx3_result_inf), - .fx3_result_nan(fx3_result_nan), - .fx3_equal(fx3_equal), - .fx3_ftoi_lshift(fx3_ftoi_lshift), - .fx3_add_significand(fx3_add_significand), - .fx3_add_exponent(fx3_add_exponent), - .fx3_add_result_sign(fx3_add_result_sign), - .fx3_logical_subtract(fx3_logical_subtract), - .fx3_significand_product(fx3_significand_product), - .fx3_mul_exponent(fx3_mul_exponent), - .fx3_mul_underflow(fx3_mul_underflow), - .fx3_mul_sign(fx3_mul_sign), - .fx4_instruction_valid(fx4_instruction_valid), - .fx4_instruction(fx4_instruction), - .fx4_mask_value(fx4_mask_value), - .fx4_thread_idx(fx4_thread_idx), - .fx4_subcycle(fx4_subcycle), - .fx4_result_inf(fx4_result_inf), - .fx4_result_nan(fx4_result_nan), - .fx4_equal(fx4_equal), - .fx4_add_exponent(fx4_add_exponent), - .fx4_add_significand(fx4_add_significand), - .fx4_add_result_sign(fx4_add_result_sign), - .fx4_logical_subtract(fx4_logical_subtract), - .fx4_norm_shift(fx4_norm_shift), - .fx4_significand_product(fx4_significand_product), - .fx4_mul_exponent(fx4_mul_exponent), - .fx4_mul_underflow(fx4_mul_underflow), - .fx4_mul_sign(fx4_mul_sign) - ); - fp_execute_stage5 fp_execute_stage5( - .clk(clk), - .reset(reset), - .fx4_mask_value(fx4_mask_value), - .fx4_instruction_valid(fx4_instruction_valid), - .fx4_instruction(fx4_instruction), - .fx4_thread_idx(fx4_thread_idx), - .fx4_subcycle(fx4_subcycle), - .fx4_result_inf(fx4_result_inf), - .fx4_result_nan(fx4_result_nan), - .fx4_equal(fx4_equal), - .fx4_add_exponent(fx4_add_exponent), - .fx4_add_significand(fx4_add_significand), - .fx4_add_result_sign(fx4_add_result_sign), - .fx4_logical_subtract(fx4_logical_subtract), - .fx4_norm_shift(fx4_norm_shift), - .fx4_significand_product(fx4_significand_product), - .fx4_mul_exponent(fx4_mul_exponent), - .fx4_mul_underflow(fx4_mul_underflow), - .fx4_mul_sign(fx4_mul_sign), - .fx5_instruction_valid(fx5_instruction_valid), - .fx5_instruction(fx5_instruction), - .fx5_mask_value(fx5_mask_value), - .fx5_thread_idx(fx5_thread_idx), - .fx5_subcycle(fx5_subcycle), - .fx5_result(fx5_result) - ); - writeback_stage writeback_stage( - .clk(clk), - .reset(reset), - .fx5_instruction_valid(fx5_instruction_valid), - .fx5_instruction(fx5_instruction), - .fx5_result(fx5_result), - .fx5_mask_value(fx5_mask_value), - .fx5_thread_idx(fx5_thread_idx), - .fx5_subcycle(fx5_subcycle), - .ix_instruction_valid(ix_instruction_valid), - .ix_instruction(ix_instruction), - .ix_result(ix_result), - .ix_thread_idx(ix_thread_idx), - .ix_mask_value(ix_mask_value), - .ix_rollback_en(ix_rollback_en), - .ix_rollback_pc(ix_rollback_pc), - .ix_subcycle(ix_subcycle), - .ix_privileged_op_fault(ix_privileged_op_fault), - .dd_instruction_valid(dd_instruction_valid), - .dd_instruction(dd_instruction), - .dd_lane_mask(dd_lane_mask), - .dd_thread_idx(dd_thread_idx), - .dd_request_vaddr(dd_request_vaddr), - .dd_subcycle(dd_subcycle), - .dd_rollback_en(dd_rollback_en), - .dd_rollback_pc(dd_rollback_pc), - .dd_load_data(dd_load_data), - .dd_suspend_thread(dd_suspend_thread), - .dd_io_access(dd_io_access), - .dd_trap(dd_trap), - .dd_trap_cause(dd_trap_cause), - .sq_store_bypass_mask(sq_store_bypass_mask), - .sq_store_bypass_data(sq_store_bypass_data), - .sq_store_sync_success(sq_store_sync_success), - .sq_rollback_en(sq_rollback_en), - .ior_read_value(ior_read_value), - .ior_rollback_en(ior_rollback_en), - .cr_creg_read_val(cr_creg_read_val), - .cr_trap_handler(cr_trap_handler), - .cr_tlb_miss_handler(cr_tlb_miss_handler), - .cr_eret_subcycle(cr_eret_subcycle), - .wb_trap(wb_trap), - .wb_trap_cause(wb_trap_cause), - .wb_trap_pc(wb_trap_pc), - .wb_trap_access_vaddr(wb_trap_access_vaddr), - .wb_trap_subcycle(wb_trap_subcycle), - .wb_syscall_index(wb_syscall_index), - .wb_eret(wb_eret), - .wb_rollback_en(wb_rollback_en), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_rollback_pc(wb_rollback_pc), - .wb_rollback_pipeline(wb_rollback_pipeline), - .wb_rollback_subcycle(wb_rollback_subcycle), - .wb_writeback_en(wb_writeback_en), - .wb_writeback_thread_idx(wb_writeback_thread_idx), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_value(wb_writeback_value), - .wb_writeback_mask(wb_writeback_mask), - .wb_writeback_reg(wb_writeback_reg), - .wb_writeback_last_subcycle(wb_writeback_last_subcycle), - .wb_suspend_thread_oh(wb_suspend_thread_oh), - .wb_inst_injected(wb_inst_injected), - .wb_perf_instruction_retire(wb_perf_instruction_retire), - .wb_perf_store_rollback(wb_perf_store_rollback), - .wb_perf_interrupt(wb_perf_interrupt) - ); - control_registers #( - .CORE_ID(CORE_ID), - .NUM_INTERRUPTS(NUM_INTERRUPTS), - .NUM_PERF_EVENTS(defines_CORE_PERF_EVENTS) - ) control_registers( - .cr_perf_event_select0(perf_event_select[0+:4]), - .cr_perf_event_select1(perf_event_select[4+:4]), - .perf_event_count0(perf_event_count[0+:64]), - .perf_event_count1(perf_event_count[64+:64]), - .clk(clk), - .reset(reset), - .interrupt_req(interrupt_req), - .cr_eret_address(cr_eret_address), - .cr_mmu_en(cr_mmu_en), - .cr_supervisor_en(cr_supervisor_en), - .cr_current_asid(cr_current_asid), - .cr_suspend_thread(cr_suspend_thread), - .cr_resume_thread(cr_resume_thread), - .cr_interrupt_pending(cr_interrupt_pending), - .cr_interrupt_en(cr_interrupt_en), - .dt_thread_idx(dt_thread_idx), - .dd_creg_write_en(dd_creg_write_en), - .dd_creg_read_en(dd_creg_read_en), - .dd_creg_index(dd_creg_index), - .dd_creg_write_val(dd_creg_write_val), - .wb_trap(wb_trap), - .wb_eret(wb_eret), - .wb_trap_cause(wb_trap_cause), - .wb_trap_pc(wb_trap_pc), - .wb_trap_access_vaddr(wb_trap_access_vaddr), - .wb_rollback_thread_idx(wb_rollback_thread_idx), - .wb_trap_subcycle(wb_trap_subcycle), - .wb_syscall_index(wb_syscall_index), - .cr_creg_read_val(cr_creg_read_val), - .cr_eret_subcycle(cr_eret_subcycle), - .cr_trap_handler(cr_trap_handler), - .cr_tlb_miss_handler(cr_tlb_miss_handler), - .ocd_data_from_host(ocd_data_from_host), - .ocd_data_update(ocd_data_update), - .cr_data_to_host(cr_data_to_host) - ); - l1_l2_interface #(.CORE_ID(CORE_ID)) l1_l2_interface( - .clk(clk), - .reset(reset), - .l2_ready(l2_ready), - .l2_response_valid(l2_response_valid), - .l2_response(l2_response), - .l2i_request_valid(l2i_request_valid), - .l2i_request(l2i_request), - .l2i_icache_lru_fill_en(l2i_icache_lru_fill_en), - .l2i_icache_lru_fill_set(l2i_icache_lru_fill_set), - .l2i_itag_update_en(l2i_itag_update_en), - .l2i_itag_update_set(l2i_itag_update_set), - .l2i_itag_update_tag(l2i_itag_update_tag), - .l2i_itag_update_valid(l2i_itag_update_valid), - .sq_store_sync_pending(sq_store_sync_pending), - .ift_fill_lru(ift_fill_lru), - .ifd_cache_miss(ifd_cache_miss), - .ifd_cache_miss_paddr(ifd_cache_miss_paddr), - .ifd_cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .l2i_idata_update_en(l2i_idata_update_en), - .l2i_idata_update_way(l2i_idata_update_way), - .l2i_idata_update_set(l2i_idata_update_set), - .l2i_idata_update_data(l2i_idata_update_data), - .l2i_dcache_wake_bitmap(l2i_dcache_wake_bitmap), - .l2i_icache_wake_bitmap(l2i_icache_wake_bitmap), - .dt_snoop_valid(dt_snoop_valid), - .dt_snoop_tag(dt_snoop_tag), - .dt_fill_lru(dt_fill_lru), - .l2i_snoop_en(l2i_snoop_en), - .l2i_snoop_set(l2i_snoop_set), - .l2i_dtag_update_en_oh(l2i_dtag_update_en_oh), - .l2i_dtag_update_set(l2i_dtag_update_set), - .l2i_dtag_update_tag(l2i_dtag_update_tag), - .l2i_dtag_update_valid(l2i_dtag_update_valid), - .l2i_dcache_lru_fill_en(l2i_dcache_lru_fill_en), - .l2i_dcache_lru_fill_set(l2i_dcache_lru_fill_set), - .dd_cache_miss(dd_cache_miss), - .dd_cache_miss_addr(dd_cache_miss_addr), - .dd_cache_miss_thread_idx(dd_cache_miss_thread_idx), - .dd_cache_miss_sync(dd_cache_miss_sync), - .dd_store_en(dd_store_en), - .dd_flush_en(dd_flush_en), - .dd_membar_en(dd_membar_en), - .dd_iinvalidate_en(dd_iinvalidate_en), - .dd_dinvalidate_en(dd_dinvalidate_en), - .dd_store_mask(dd_store_mask), - .dd_store_addr(dd_store_addr), - .dd_store_data(dd_store_data), - .dd_store_thread_idx(dd_store_thread_idx), - .dd_store_sync(dd_store_sync), - .dd_store_bypass_addr(dd_store_bypass_addr), - .dd_store_bypass_thread_idx(dd_store_bypass_thread_idx), - .l2i_ddata_update_en(l2i_ddata_update_en), - .l2i_ddata_update_way(l2i_ddata_update_way), - .l2i_ddata_update_set(l2i_ddata_update_set), - .l2i_ddata_update_data(l2i_ddata_update_data), - .sq_store_bypass_mask(sq_store_bypass_mask), - .sq_store_sync_success(sq_store_sync_success), - .sq_store_bypass_data(sq_store_bypass_data), - .sq_rollback_en(sq_rollback_en), - .l2i_perf_store(l2i_perf_store) - ); - io_request_queue #(.CORE_ID(CORE_ID)) io_request_queue( - .clk(clk), - .reset(reset), - .dd_io_write_en(dd_io_write_en), - .dd_io_read_en(dd_io_read_en), - .dd_io_thread_idx(dd_io_thread_idx), - .dd_io_addr(dd_io_addr), - .dd_io_write_value(dd_io_write_value), - .ior_read_value(ior_read_value), - .ior_rollback_en(ior_rollback_en), - .ior_pending(ior_pending), - .ior_wake_bitmap(ior_wake_bitmap), - .ii_ready(ii_ready), - .ii_response_valid(ii_response_valid), - .ii_response(ii_response), - .ior_request_valid(ior_request_valid), - .ior_request(ior_request) - ); - assign core_selected_debug = CORE_ID == ocd_core; - always @(posedge clk) begin - injected_complete <= wb_inst_injected & !wb_rollback_en; - injected_rollback <= wb_inst_injected & wb_rollback_en; - end - assign perf_events = {ix_perf_cond_branch_not_taken, ix_perf_cond_branch_taken, ix_perf_uncond_branch, dd_perf_dtlb_miss, dd_perf_dcache_hit, dd_perf_dcache_miss, ifd_perf_itlb_miss, ifd_perf_icache_hit, ifd_perf_icache_miss, ts_perf_instruction_issue, wb_perf_instruction_retire, l2i_perf_store, wb_perf_store_rollback, wb_perf_interrupt}; - performance_counters #( - .NUM_EVENTS(defines_CORE_PERF_EVENTS), - .NUM_COUNTERS(2) - ) performance_counters( - .clk(clk), - .reset(reset), - .perf_events(perf_events), - .perf_event_select(perf_event_select), - .perf_event_count(perf_event_count) - ); -endmodule -module dcache_data_stage ( - clk, - reset, - dd_load_sync_pending, - dt_instruction_valid, - dt_instruction, - dt_mask_value, - dt_thread_idx, - dt_request_vaddr, - dt_request_paddr, - dt_tlb_hit, - dt_tlb_present, - dt_tlb_supervisor, - dt_tlb_writable, - dt_store_value, - dt_subcycle, - dt_valid, - dt_tag, - dd_update_lru_en, - dd_update_lru_way, - dd_io_write_en, - dd_io_read_en, - dd_io_thread_idx, - dd_io_addr, - dd_io_write_value, - dd_instruction_valid, - dd_instruction, - dd_lane_mask, - dd_thread_idx, - dd_request_vaddr, - dd_subcycle, - dd_rollback_en, - dd_rollback_pc, - dd_load_data, - dd_suspend_thread, - dd_io_access, - dd_trap, - dd_trap_cause, - cr_supervisor_en, - dd_creg_write_en, - dd_creg_read_en, - dd_creg_index, - dd_creg_write_val, - l2i_ddata_update_en, - l2i_ddata_update_way, - l2i_ddata_update_set, - l2i_ddata_update_data, - l2i_dtag_update_en_oh, - l2i_dtag_update_set, - l2i_dtag_update_tag, - dd_cache_miss, - dd_cache_miss_addr, - dd_cache_miss_thread_idx, - dd_cache_miss_sync, - dd_store_en, - dd_flush_en, - dd_membar_en, - dd_iinvalidate_en, - dd_dinvalidate_en, - dd_store_mask, - dd_store_addr, - dd_store_data, - dd_store_thread_idx, - dd_store_sync, - dd_store_bypass_addr, - dd_store_bypass_thread_idx, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pipeline, - dd_perf_dcache_hit, - dd_perf_dcache_miss, - dd_perf_dtlb_miss -); - reg _sv2v_0; - input clk; - input reset; - output reg [3:0] dd_load_sync_pending; - input dt_instruction_valid; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] dt_instruction; - input wire [15:0] dt_mask_value; - input wire [1:0] dt_thread_idx; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_DCACHE_TAG_BITS = 20; - input wire [31:0] dt_request_vaddr; - input wire [31:0] dt_request_paddr; - input dt_tlb_hit; - input dt_tlb_present; - input dt_tlb_supervisor; - input dt_tlb_writable; - input wire [511:0] dt_store_value; - input wire [3:0] dt_subcycle; - input [0:3] dt_valid; - input wire [79:0] dt_tag; - output wire dd_update_lru_en; - output wire [1:0] dd_update_lru_way; - output wire dd_io_write_en; - output wire dd_io_read_en; - output wire [1:0] dd_io_thread_idx; - output wire [31:0] dd_io_addr; - output wire [31:0] dd_io_write_value; - output reg dd_instruction_valid; - output reg [141:0] dd_instruction; - output reg [15:0] dd_lane_mask; - output reg [1:0] dd_thread_idx; - output reg [31:0] dd_request_vaddr; - output reg [3:0] dd_subcycle; - output reg dd_rollback_en; - output reg [31:0] dd_rollback_pc; - localparam defines_CACHE_LINE_BITS = 512; - output wire [511:0] dd_load_data; - output reg dd_suspend_thread; - output reg dd_io_access; - output reg dd_trap; - output reg [5:0] dd_trap_cause; - input wire [0:3] cr_supervisor_en; - output wire dd_creg_write_en; - output wire dd_creg_read_en; - output wire [4:0] dd_creg_index; - output wire [31:0] dd_creg_write_val; - input l2i_ddata_update_en; - input wire [1:0] l2i_ddata_update_way; - input wire [5:0] l2i_ddata_update_set; - input wire [511:0] l2i_ddata_update_data; - input [3:0] l2i_dtag_update_en_oh; - input wire [5:0] l2i_dtag_update_set; - input wire [19:0] l2i_dtag_update_tag; - output wire dd_cache_miss; - output wire [25:0] dd_cache_miss_addr; - output wire [1:0] dd_cache_miss_thread_idx; - output wire dd_cache_miss_sync; - output wire dd_store_en; - output wire dd_flush_en; - output wire dd_membar_en; - output wire dd_iinvalidate_en; - output wire dd_dinvalidate_en; - output wire [63:0] dd_store_mask; - output wire [25:0] dd_store_addr; - output reg [511:0] dd_store_data; - output wire [1:0] dd_store_thread_idx; - output wire dd_store_sync; - output wire [25:0] dd_store_bypass_addr; - output wire [1:0] dd_store_bypass_thread_idx; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wire [1:0] wb_rollback_pipeline; - output reg dd_perf_dcache_hit; - output reg dd_perf_dcache_miss; - output reg dd_perf_dtlb_miss; - wire memory_access_req; - wire cached_access_req; - wire cached_load_req; - wire cached_store_req; - wire creg_access_req; - wire io_access_req; - wire sync_access_req; - wire cache_control_req; - wire tlb_update_req; - wire flush_req; - wire iinvalidate_req; - wire dinvalidate_req; - wire membar_req; - wire addr_in_io_region; - reg unaligned_address; - wire supervisor_fault; - wire alignment_fault; - wire privileged_op_fault; - wire write_fault; - wire tlb_miss; - wire page_fault; - wire any_fault; - reg [15:0] word_store_mask; - reg [3:0] byte_store_mask; - localparam defines_CACHE_LINE_WORDS = 16; - wire [3:0] cache_lane_idx; - wire [511:0] endian_twiddled_data; - wire [31:0] lane_store_value; - wire [15:0] cache_lane_mask; - wire [15:0] subcycle_mask; - wire [3:0] way_hit_oh; - wire [1:0] way_hit_idx; - wire cache_hit; - wire [31:0] dcache_request_addr; - wire squash_instruction; - wire cache_near_miss; - wire [3:0] scgath_lane; - reg tlb_read; - wire fault_store_flag; - wire lane_enabled; - assign squash_instruction = (wb_rollback_en && (wb_rollback_thread_idx == dt_thread_idx)) && (wb_rollback_pipeline == 2'd0); - assign scgath_lane = ~dt_subcycle; - idx_to_oh #( - .NUM_SIGNALS(defines_CACHE_LINE_WORDS), - .DIRECTION("LSB0") - ) idx_to_oh_subcycle( - .one_hot(subcycle_mask), - .index(dt_subcycle) - ); - assign lane_enabled = (!dt_instruction[19] || (dt_instruction[18-:4] != 4'b1110)) || ((dt_mask_value & subcycle_mask) != 0); - assign addr_in_io_region = (dt_request_paddr | 32'h0000ffff) == 32'hffffffff; - assign sync_access_req = dt_instruction[18-:4] == 4'b0101; - assign memory_access_req = (((dt_instruction_valid && !squash_instruction) && dt_instruction[19]) && (dt_instruction[18-:4] != 4'b0110)) && lane_enabled; - assign io_access_req = memory_access_req && addr_in_io_region; - assign cached_access_req = memory_access_req && !addr_in_io_region; - assign cached_load_req = cached_access_req && dt_instruction[14]; - assign cached_store_req = cached_access_req && !dt_instruction[14]; - assign cache_control_req = (dt_instruction_valid && !squash_instruction) && dt_instruction[3]; - assign flush_req = (cache_control_req && (dt_instruction[2-:3] == 3'b010)) && !addr_in_io_region; - assign iinvalidate_req = (cache_control_req && (dt_instruction[2-:3] == 3'b011)) && !addr_in_io_region; - assign dinvalidate_req = (cache_control_req && (dt_instruction[2-:3] == 3'b001)) && !addr_in_io_region; - assign membar_req = cache_control_req && (dt_instruction[2-:3] == 3'b100); - assign tlb_update_req = cache_control_req && ((((dt_instruction[2-:3] == 3'b000) || (dt_instruction[2-:3] == 3'b111)) || (dt_instruction[2-:3] == 3'b101)) || (dt_instruction[2-:3] == 3'b110)); - assign creg_access_req = ((dt_instruction_valid && !squash_instruction) && dt_instruction[19]) && (dt_instruction[18-:4] == 4'b0110); - always @(*) begin - if (_sv2v_0) - ; - tlb_read = 0; - if (dt_instruction_valid && !squash_instruction) begin - if (dt_instruction[19]) - tlb_read = (dt_instruction[18-:4] != 4'b0110) && lane_enabled; - else if (dt_instruction[3]) - tlb_read = (dt_instruction[2-:3] == 3'b010) || (dt_instruction[2-:3] == 3'b001); - end - end - assign tlb_miss = tlb_read && !dt_tlb_hit; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dt_instruction[18-:4]) - 4'b0010, 4'b0011: unaligned_address = dt_request_paddr[0]; - 4'b0100, 4'b0101, 4'b1101, 4'b1110: unaligned_address = |dt_request_paddr[1:0]; - 4'b0111, 4'b1000: unaligned_address = dt_request_paddr[5-:defines_CACHE_LINE_OFFSET_WIDTH] != 0; - default: unaligned_address = 0; - endcase - end - assign alignment_fault = (cached_access_req || io_access_req) && unaligned_address; - assign privileged_op_fault = ((creg_access_req || tlb_update_req) || dinvalidate_req) && !cr_supervisor_en[dt_thread_idx]; - assign page_fault = (memory_access_req && dt_tlb_hit) && !dt_tlb_present; - assign supervisor_fault = (((memory_access_req && dt_tlb_hit) && dt_tlb_present) && dt_tlb_supervisor) && !cr_supervisor_en[dt_thread_idx]; - assign write_fault = ((((cached_store_req || (io_access_req && !dt_instruction[14])) && dt_tlb_hit) && dt_tlb_present) && !supervisor_fault) && !dt_tlb_writable; - assign any_fault = (((alignment_fault || privileged_op_fault) || page_fault) || supervisor_fault) || write_fault; - assign dd_store_en = (cached_store_req && !tlb_miss) && !any_fault; - assign dcache_request_addr = {dt_request_paddr[31:defines_CACHE_LINE_OFFSET_WIDTH], {defines_CACHE_LINE_OFFSET_WIDTH {1'b0}}}; - assign cache_lane_idx = dt_request_paddr[5:2]; - assign dd_store_bypass_addr = dt_request_paddr[31:defines_CACHE_LINE_OFFSET_WIDTH]; - assign dd_store_bypass_thread_idx = dt_thread_idx; - assign dd_store_addr = dt_request_paddr[31:defines_CACHE_LINE_OFFSET_WIDTH]; - assign dd_store_sync = sync_access_req; - assign dd_store_thread_idx = dt_thread_idx; - assign dd_io_write_en = ((io_access_req && !dt_instruction[14]) && !tlb_miss) && !any_fault; - assign dd_io_read_en = ((io_access_req && dt_instruction[14]) && !tlb_miss) && !any_fault; - assign dd_io_write_value = dt_store_value[0+:32]; - assign dd_io_thread_idx = dt_thread_idx; - assign dd_io_addr = {16'd0, dt_request_paddr[15:0]}; - assign dd_creg_write_en = (creg_access_req && !dt_instruction[14]) && !any_fault; - assign dd_creg_read_en = (creg_access_req && dt_instruction[14]) && !any_fault; - assign dd_creg_write_val = dt_store_value[0+:32]; - assign dd_creg_index = dt_instruction[8-:5]; - assign dd_flush_en = (((flush_req && dt_tlb_hit) && dt_tlb_present) && !io_access_req) && !any_fault; - assign dd_iinvalidate_en = (((iinvalidate_req && dt_tlb_hit) && dt_tlb_present) && !io_access_req) && !any_fault; - assign dd_dinvalidate_en = (((dinvalidate_req && dt_tlb_hit) && dt_tlb_present) && !io_access_req) && !any_fault; - assign dd_membar_en = membar_req && (dt_instruction[2-:3] == 3'b100); - genvar _gv_way_idx_1; - generate - for (_gv_way_idx_1 = 0; _gv_way_idx_1 < 4; _gv_way_idx_1 = _gv_way_idx_1 + 1) begin : hit_check_gen - localparam way_idx = _gv_way_idx_1; - assign way_hit_oh[way_idx] = (dt_request_paddr[31-:20] == dt_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS]) && dt_valid[way_idx]; - end - endgenerate - assign cache_hit = (|way_hit_oh && (!sync_access_req || dd_load_sync_pending[dt_thread_idx])) && dt_tlb_hit; - idx_to_oh #( - .NUM_SIGNALS(defines_CACHE_LINE_WORDS), - .DIRECTION("LSB0") - ) idx_to_oh_cache_lane( - .one_hot(cache_lane_mask), - .index(cache_lane_idx) - ); - always @(*) begin - if (_sv2v_0) - ; - word_store_mask = 0; - (* full_case, parallel_case *) - case (dt_instruction[18-:4]) - 4'b0111, 4'b1000: word_store_mask = dt_mask_value; - 4'b1101, 4'b1110: - if ((dt_mask_value & subcycle_mask) != 0) - word_store_mask = cache_lane_mask; - else - word_store_mask = 0; - default: word_store_mask = cache_lane_mask; - endcase - end - genvar _gv_swap_word_1; - generate - for (_gv_swap_word_1 = 0; _gv_swap_word_1 < 16; _gv_swap_word_1 = _gv_swap_word_1 + 1) begin : swap_word_gen - localparam swap_word = _gv_swap_word_1; - assign endian_twiddled_data[swap_word * 32+:8] = dt_store_value[(swap_word * 32) + 24+:8]; - assign endian_twiddled_data[(swap_word * 32) + 8+:8] = dt_store_value[(swap_word * 32) + 16+:8]; - assign endian_twiddled_data[(swap_word * 32) + 16+:8] = dt_store_value[(swap_word * 32) + 8+:8]; - assign endian_twiddled_data[(swap_word * 32) + 24+:8] = dt_store_value[swap_word * 32+:8]; - end - endgenerate - assign lane_store_value = dt_store_value[scgath_lane * 32+:32]; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dt_instruction[18-:4]) - 4'b0000, 4'b0001: begin - dd_store_data = {64 {dt_store_value[7-:8]}}; - case (dt_request_paddr[1:0]) - 2'd0: byte_store_mask = 4'b1000; - 2'd1: byte_store_mask = 4'b0100; - 2'd2: byte_store_mask = 4'b0010; - 2'd3: byte_store_mask = 4'b0001; - default: byte_store_mask = 4'b0000; - endcase - end - 4'b0010, 4'b0011: begin - dd_store_data = {32 {dt_store_value[7-:8], dt_store_value[15-:8]}}; - if (dt_request_paddr[1] == 1'b0) - byte_store_mask = 4'b1100; - else - byte_store_mask = 4'b0011; - end - 4'b0100, 4'b0101: begin - byte_store_mask = 4'b1111; - dd_store_data = {defines_CACHE_LINE_WORDS {dt_store_value[7-:8], dt_store_value[15-:8], dt_store_value[23-:8], dt_store_value[31-:8]}}; - end - 4'b1101, 4'b1110: begin - byte_store_mask = 4'b1111; - dd_store_data = {defines_CACHE_LINE_WORDS {lane_store_value[7:0], lane_store_value[15:8], lane_store_value[23:16], lane_store_value[31:24]}}; - end - default: begin - byte_store_mask = 4'b1111; - dd_store_data = endian_twiddled_data; - end - endcase - end - genvar _gv_mask_idx_1; - generate - for (_gv_mask_idx_1 = 0; _gv_mask_idx_1 < defines_CACHE_LINE_BYTES; _gv_mask_idx_1 = _gv_mask_idx_1 + 1) begin : store_mask_gen - localparam mask_idx = _gv_mask_idx_1; - assign dd_store_mask[mask_idx] = word_store_mask[((defines_CACHE_LINE_BYTES - mask_idx) - 1) / 4] & byte_store_mask[mask_idx & 3]; - end - endgenerate - oh_to_idx #(.NUM_SIGNALS(4)) encode_hit_way( - .one_hot(way_hit_oh), - .index(way_hit_idx) - ); - fakeram_1r1w_512x256 #( - .DATA_WIDTH(defines_CACHE_LINE_BITS), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) l1d_data( - .read_en(cache_hit && cached_load_req), - .read_addr({way_hit_idx, dt_request_paddr[11-:6]}), - .read_data(dd_load_data), - .write_en(l2i_ddata_update_en), - .write_addr({l2i_ddata_update_way, l2i_ddata_update_set}), - .write_data(l2i_ddata_update_data), - .* - ); - assign cache_near_miss = ((((((!cache_hit && dt_tlb_hit) && cached_load_req) && |l2i_dtag_update_en_oh) && (l2i_dtag_update_set == dt_request_paddr[11-:6])) && (l2i_dtag_update_tag == dt_request_paddr[31-:20])) && !sync_access_req) && !any_fault; - assign dd_cache_miss = (((cached_load_req && !cache_hit) && dt_tlb_hit) && !cache_near_miss) && !any_fault; - assign dd_cache_miss_addr = dcache_request_addr[31:defines_CACHE_LINE_OFFSET_WIDTH]; - assign dd_cache_miss_thread_idx = dt_thread_idx; - assign dd_cache_miss_sync = sync_access_req; - assign dd_update_lru_en = (cache_hit && cached_access_req) && !any_fault; - assign dd_update_lru_way = way_hit_idx; - genvar _gv_thread_idx_2; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_2 = 0; _gv_thread_idx_2 < 4; _gv_thread_idx_2 = _gv_thread_idx_2 + 1) begin : sync_pending_gen - localparam thread_idx = _gv_thread_idx_2; - always @(posedge clk or posedge reset) - if (reset) - dd_load_sync_pending[thread_idx] <= 0; - else if ((cached_load_req && sync_access_req) && (dt_thread_idx == sv2v_cast_2(thread_idx))) - dd_load_sync_pending[thread_idx] <= !dd_load_sync_pending[thread_idx]; - end - endgenerate - assign fault_store_flag = dt_instruction[19] && !dt_instruction[14]; - always @(posedge clk) begin - dd_instruction <= dt_instruction; - dd_lane_mask <= dt_mask_value; - dd_thread_idx <= dt_thread_idx; - dd_request_vaddr <= dt_request_vaddr; - dd_subcycle <= dt_subcycle; - dd_rollback_pc <= dt_instruction[141-:32]; - dd_io_access <= io_access_req; - if (tlb_miss) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd7}; - else if (page_fault) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd6}; - else if (supervisor_fault) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd9}; - else if (alignment_fault) - dd_trap_cause <= {1'b1, fault_store_flag, 4'd5}; - else if (privileged_op_fault) - dd_trap_cause <= 6'h02; - else - dd_trap_cause <= 6'h38; - end - always @(posedge clk or posedge reset) - if (reset) begin - dd_instruction_valid <= 1'sb0; - dd_perf_dcache_hit <= 1'sb0; - dd_perf_dcache_miss <= 1'sb0; - dd_perf_dtlb_miss <= 1'sb0; - dd_rollback_en <= 1'sb0; - dd_suspend_thread <= 1'sb0; - dd_trap <= 1'sb0; - end - else begin - dd_instruction_valid <= dt_instruction_valid && !squash_instruction; - dd_rollback_en <= ((cached_load_req && !cache_hit) && dt_tlb_hit) && !any_fault; - dd_suspend_thread <= (((cached_load_req && dt_tlb_hit) && !cache_hit) && !cache_near_miss) && !any_fault; - dd_trap <= any_fault || tlb_miss; - dd_perf_dcache_hit <= ((cached_load_req && !any_fault) && !tlb_miss) && cache_hit; - dd_perf_dcache_miss <= ((cached_load_req && !any_fault) && !tlb_miss) && !cache_hit; - dd_perf_dtlb_miss <= tlb_miss; - end - initial _sv2v_0 = 0; -endmodule -module dcache_tag_stage ( - clk, - reset, - of_operand1, - of_mask_value, - of_store_value, - of_instruction_valid, - of_instruction, - of_thread_idx, - of_subcycle, - dd_update_lru_en, - dd_update_lru_way, - dt_instruction_valid, - dt_instruction, - dt_mask_value, - dt_thread_idx, - dt_request_vaddr, - dt_request_paddr, - dt_tlb_hit, - dt_tlb_writable, - dt_store_value, - dt_subcycle, - dt_valid, - dt_tag, - dt_tlb_supervisor, - dt_tlb_present, - dt_invalidate_tlb_en, - dt_invalidate_tlb_all_en, - dt_update_itlb_en, - dt_update_itlb_asid, - dt_update_itlb_vpage_idx, - dt_update_itlb_ppage_idx, - dt_update_itlb_present, - dt_update_itlb_supervisor, - dt_update_itlb_global, - dt_update_itlb_executable, - l2i_dcache_lru_fill_en, - l2i_dcache_lru_fill_set, - l2i_dtag_update_en_oh, - l2i_dtag_update_set, - l2i_dtag_update_tag, - l2i_dtag_update_valid, - l2i_snoop_en, - l2i_snoop_set, - dt_snoop_valid, - dt_snoop_tag, - dt_fill_lru, - cr_mmu_en, - cr_supervisor_en, - cr_current_asid, - wb_rollback_en, - wb_rollback_thread_idx -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [511:0] of_operand1; - input wire [15:0] of_mask_value; - input wire [511:0] of_store_value; - input of_instruction_valid; - input wire [141:0] of_instruction; - input wire [1:0] of_thread_idx; - input wire [3:0] of_subcycle; - input dd_update_lru_en; - input wire [1:0] dd_update_lru_way; - output reg dt_instruction_valid; - output reg [141:0] dt_instruction; - output reg [15:0] dt_mask_value; - output reg [1:0] dt_thread_idx; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_DCACHE_TAG_BITS = 20; - output wire [31:0] dt_request_vaddr; - output wire [31:0] dt_request_paddr; - output reg dt_tlb_hit; - output reg dt_tlb_writable; - output reg [511:0] dt_store_value; - output reg [3:0] dt_subcycle; - output reg [0:3] dt_valid; - output wire [79:0] dt_tag; - output reg dt_tlb_supervisor; - output reg dt_tlb_present; - output wire dt_invalidate_tlb_en; - output wire dt_invalidate_tlb_all_en; - output wire dt_update_itlb_en; - localparam defines_ASID_WIDTH = 8; - output wire [7:0] dt_update_itlb_asid; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - output wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_vpage_idx; - output wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_ppage_idx; - output wire dt_update_itlb_present; - output wire dt_update_itlb_supervisor; - output wire dt_update_itlb_global; - output wire dt_update_itlb_executable; - input l2i_dcache_lru_fill_en; - input wire [5:0] l2i_dcache_lru_fill_set; - input [3:0] l2i_dtag_update_en_oh; - input wire [5:0] l2i_dtag_update_set; - input wire [19:0] l2i_dtag_update_tag; - input l2i_dtag_update_valid; - input l2i_snoop_en; - input wire [5:0] l2i_snoop_set; - output reg [0:3] dt_snoop_valid; - output wire [79:0] dt_snoop_tag; - output wire [1:0] dt_fill_lru; - input [0:3] cr_mmu_en; - input wire [0:3] cr_supervisor_en; - input [31:0] cr_current_asid; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - wire [31:0] request_addr_nxt; - wire cache_load_en; - wire instruction_valid; - wire [3:0] scgath_lane; - wire [defines_PAGE_NUM_BITS - 1:0] tlb_ppage_idx; - wire tlb_hit; - reg [defines_PAGE_NUM_BITS - 1:0] ppage_idx; - reg [31:0] fetched_addr; - wire tlb_lookup_en; - wire valid_cache_control; - wire update_dtlb_en; - wire tlb_writable; - wire tlb_present; - wire tlb_supervisor; - wire [(defines_PAGE_NUM_BITS + (32 - (defines_PAGE_NUM_BITS + 5))) + 4:0] new_tlb_value; - assign instruction_valid = (of_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != of_thread_idx))) && (of_instruction[21-:2] == 2'd0); - assign valid_cache_control = instruction_valid && of_instruction[3]; - assign cache_load_en = ((instruction_valid && (of_instruction[18-:4] != 4'b0110)) && of_instruction[19]) && of_instruction[14]; - assign scgath_lane = ~of_subcycle; - assign request_addr_nxt = of_operand1[scgath_lane * 32+:32] + of_instruction[58-:32]; - assign new_tlb_value = of_store_value[0+:32]; - assign dt_invalidate_tlb_en = (valid_cache_control && (of_instruction[2-:3] == 3'b101)) && cr_supervisor_en[of_thread_idx]; - assign dt_invalidate_tlb_all_en = (valid_cache_control && (of_instruction[2-:3] == 3'b110)) && cr_supervisor_en[of_thread_idx]; - assign update_dtlb_en = (valid_cache_control && (of_instruction[2-:3] == 3'b000)) && cr_supervisor_en[of_thread_idx]; - assign dt_update_itlb_en = (valid_cache_control && (of_instruction[2-:3] == 3'b111)) && cr_supervisor_en[of_thread_idx]; - assign dt_update_itlb_supervisor = new_tlb_value[3]; - assign dt_update_itlb_global = new_tlb_value[4]; - assign dt_update_itlb_present = new_tlb_value[0]; - assign tlb_lookup_en = (((instruction_valid && (of_instruction[18-:4] != 4'b0110)) && !update_dtlb_en) && !dt_invalidate_tlb_en) && !dt_invalidate_tlb_all_en; - assign dt_update_itlb_vpage_idx = of_operand1[31-:defines_PAGE_NUM_BITS]; - assign dt_update_itlb_ppage_idx = new_tlb_value[defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))-:((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) >= (37 - (defines_PAGE_NUM_BITS + 5)) ? ((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) - (37 - (defines_PAGE_NUM_BITS + 5))) + 1 : ((37 - (defines_PAGE_NUM_BITS + 5)) - (defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5)))) + 1)]; - assign dt_update_itlb_executable = new_tlb_value[2]; - assign dt_update_itlb_asid = cr_current_asid[(3 - of_thread_idx) * 8+:8]; - genvar _gv_way_idx_2; - generate - for (_gv_way_idx_2 = 0; _gv_way_idx_2 < 4; _gv_way_idx_2 = _gv_way_idx_2 + 1) begin : way_tag_gen - localparam way_idx = _gv_way_idx_2; - reg line_valid [0:63]; - fakeram_2r1w_20x64 #( - .DATA_WIDTH(defines_DCACHE_TAG_BITS), - .SIZE(64), - .READ_DURING_WRITE("NEW_DATA") - ) sram_tags( - .read1_en(cache_load_en), - .read1_addr(request_addr_nxt[11-:6]), - .read1_data(dt_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS]), - .read2_en(l2i_snoop_en), - .read2_addr(l2i_snoop_set), - .read2_data(dt_snoop_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS]), - .write_en(l2i_dtag_update_en_oh[way_idx]), - .write_addr(l2i_dtag_update_set), - .write_data(l2i_dtag_update_tag), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < 64; set_idx = set_idx + 1) - line_valid[set_idx] <= 0; - end - else if (l2i_dtag_update_en_oh[way_idx]) - line_valid[l2i_dtag_update_set] <= l2i_dtag_update_valid; - always @(posedge clk) begin - if (cache_load_en) begin - if (l2i_dtag_update_en_oh[way_idx] && (l2i_dtag_update_set == request_addr_nxt[11-:6])) - dt_valid[way_idx] <= l2i_dtag_update_valid; - else - dt_valid[way_idx] <= line_valid[request_addr_nxt[11-:6]]; - end - if (l2i_snoop_en) begin - if (l2i_dtag_update_en_oh[way_idx] && (l2i_dtag_update_set == l2i_snoop_set)) - dt_snoop_valid[way_idx] <= l2i_dtag_update_valid; - else - dt_snoop_valid[way_idx] <= line_valid[l2i_snoop_set]; - end - end - end - endgenerate - tlb #( - .NUM_ENTRIES(64), - .NUM_WAYS(4) - ) dtlb( - .lookup_en(tlb_lookup_en), - .update_en(update_dtlb_en), - .invalidate_en(dt_invalidate_tlb_en), - .invalidate_all_en(dt_invalidate_tlb_all_en), - .request_vpage_idx(request_addr_nxt[31-:defines_PAGE_NUM_BITS]), - .request_asid(cr_current_asid[(3 - of_thread_idx) * 8+:8]), - .update_ppage_idx(new_tlb_value[defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))-:((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) >= (37 - (defines_PAGE_NUM_BITS + 5)) ? ((defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5))) - (37 - (defines_PAGE_NUM_BITS + 5))) + 1 : ((37 - (defines_PAGE_NUM_BITS + 5)) - (defines_PAGE_NUM_BITS + (36 - (defines_PAGE_NUM_BITS + 5)))) + 1)]), - .update_present(new_tlb_value[0]), - .update_exe_writable(new_tlb_value[1]), - .update_supervisor(new_tlb_value[3]), - .update_global(new_tlb_value[4]), - .lookup_ppage_idx(tlb_ppage_idx), - .lookup_hit(tlb_hit), - .lookup_present(tlb_present), - .lookup_exe_writable(tlb_writable), - .lookup_supervisor(tlb_supervisor), - .clk(clk), - .reset(reset) - ); - always @(*) begin - if (_sv2v_0) - ; - if (cr_mmu_en[dt_thread_idx]) begin - dt_tlb_hit = tlb_hit; - dt_tlb_writable = tlb_writable; - dt_tlb_present = tlb_present; - dt_tlb_supervisor = tlb_supervisor; - ppage_idx = tlb_ppage_idx; - end - else begin - dt_tlb_hit = 1; - dt_tlb_writable = 1; - dt_tlb_present = 1; - dt_tlb_supervisor = 0; - ppage_idx = fetched_addr[31-:defines_PAGE_NUM_BITS]; - end - end - cache_lru #( - .NUM_WAYS(4), - .NUM_SETS(64) - ) lru( - .fill_en(l2i_dcache_lru_fill_en), - .fill_set(l2i_dcache_lru_fill_set), - .fill_way(dt_fill_lru), - .access_en(instruction_valid), - .access_set(request_addr_nxt[11-:6]), - .update_en(dd_update_lru_en), - .update_way(dd_update_lru_way), - .clk(clk), - .reset(reset) - ); - always @(posedge clk) begin - dt_instruction <= of_instruction; - dt_mask_value <= of_mask_value; - dt_thread_idx <= of_thread_idx; - dt_store_value <= of_store_value; - dt_subcycle <= of_subcycle; - fetched_addr <= request_addr_nxt; - end - always @(posedge clk or posedge reset) - if (reset) - dt_instruction_valid <= 1'sb0; - else - dt_instruction_valid <= instruction_valid; - assign dt_request_paddr = {ppage_idx, fetched_addr[31 - defines_PAGE_NUM_BITS:0]}; - assign dt_request_vaddr = fetched_addr; - initial _sv2v_0 = 0; -endmodule -module fp_execute_stage1 ( - clk, - reset, - wb_rollback_en, - wb_rollback_thread_idx, - of_operand1, - of_operand2, - of_mask_value, - of_instruction_valid, - of_instruction, - of_thread_idx, - of_subcycle, - fx1_instruction_valid, - fx1_instruction, - fx1_mask_value, - fx1_thread_idx, - fx1_subcycle, - fx1_result_inf, - fx1_result_nan, - fx1_equal, - fx1_ftoi_lshift, - fx1_significand_le, - fx1_significand_se, - fx1_se_align_shift, - fx1_add_exponent, - fx1_logical_subtract, - fx1_add_result_sign, - fx1_multiplicand, - fx1_multiplier, - fx1_mul_exponent, - fx1_mul_underflow, - fx1_mul_sign -); - reg _sv2v_0; - input clk; - input reset; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [511:0] of_operand1; - input wire [511:0] of_operand2; - input wire [15:0] of_mask_value; - input of_instruction_valid; - input wire [141:0] of_instruction; - input wire [1:0] of_thread_idx; - input wire [3:0] of_subcycle; - output reg fx1_instruction_valid; - output reg [141:0] fx1_instruction; - output reg [15:0] fx1_mask_value; - output reg [1:0] fx1_thread_idx; - output reg [3:0] fx1_subcycle; - output reg [15:0] fx1_result_inf; - output reg [15:0] fx1_result_nan; - output reg [15:0] fx1_equal; - output reg [95:0] fx1_ftoi_lshift; - output reg [511:0] fx1_significand_le; - output reg [511:0] fx1_significand_se; - output reg [95:0] fx1_se_align_shift; - output reg [127:0] fx1_add_exponent; - output reg [15:0] fx1_logical_subtract; - output reg [15:0] fx1_add_result_sign; - output reg [511:0] fx1_multiplicand; - output reg [511:0] fx1_multiplier; - output reg [127:0] fx1_mul_exponent; - output reg [15:0] fx1_mul_underflow; - output reg [15:0] fx1_mul_sign; - wire fmul; - wire imul; - wire ftoi; - wire itof; - wire compare; - assign fmul = of_instruction[70-:6] == 6'b100010; - assign imul = ((of_instruction[70-:6] == 6'b000111) || (of_instruction[70-:6] == 6'b001000)) || (of_instruction[70-:6] == 6'b011111); - assign ftoi = of_instruction[70-:6] == 6'b011011; - assign itof = of_instruction[70-:6] == 6'b101010; - assign compare = (((((of_instruction[70-:6] == 6'b101100) || (of_instruction[70-:6] == 6'b101110)) || (of_instruction[70-:6] == 6'b101101)) || (of_instruction[70-:6] == 6'b101111)) || (of_instruction[70-:6] == 6'b110000)) || (of_instruction[70-:6] == 6'b110001); - genvar _gv_lane_idx_1; - localparam defines_FLOAT32_EXP_WIDTH = 8; - localparam defines_FLOAT32_SIG_WIDTH = 23; - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - generate - for (_gv_lane_idx_1 = 0; _gv_lane_idx_1 < defines_NUM_VECTOR_LANES; _gv_lane_idx_1 = _gv_lane_idx_1 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_1; - wire [31:0] fop1; - wire [31:0] fop2; - wire [defines_FLOAT32_SIG_WIDTH:0] full_significand1; - wire [defines_FLOAT32_SIG_WIDTH:0] full_significand2; - wire op1_hidden_bit; - wire op2_hidden_bit; - wire op1_larger; - wire [7:0] exp_difference; - wire subtract; - wire [7:0] mul_exponent; - wire fop1_inf; - wire fop1_nan; - wire fop2_inf; - wire fop2_nan; - reg logical_subtract; - reg result_nan; - wire equal; - wire mul_exponent_underflow; - wire mul_exponent_carry; - reg [5:0] ftoi_rshift; - reg [5:0] ftoi_lshift_nxt; - assign fop1 = of_operand1[lane_idx * 32+:32]; - assign fop2 = of_operand2[lane_idx * 32+:32]; - assign op1_hidden_bit = fop1[30-:8] != 0; - assign op2_hidden_bit = fop2[30-:8] != 0; - assign full_significand1 = {op1_hidden_bit, fop1[22-:defines_FLOAT32_SIG_WIDTH]}; - assign full_significand2 = {op2_hidden_bit, fop2[22-:defines_FLOAT32_SIG_WIDTH]}; - assign subtract = of_instruction[70-:6] != 6'b100000; - assign fop1_inf = (fop1[30-:8] == 8'hff) && (fop1[22-:defines_FLOAT32_SIG_WIDTH] == 0); - assign fop1_nan = (fop1[30-:8] == 8'hff) && (fop1[22-:defines_FLOAT32_SIG_WIDTH] != 0); - assign fop2_inf = (fop2[30-:8] == 8'hff) && (fop2[22-:defines_FLOAT32_SIG_WIDTH] == 0); - assign fop2_nan = (fop2[30-:8] == 8'hff) && (fop2[22-:defines_FLOAT32_SIG_WIDTH] != 0); - always @(*) begin - if (_sv2v_0) - ; - if (fop2[30-:8] < 8'd118) begin - ftoi_rshift = 6'd32; - ftoi_lshift_nxt = 0; - end - else if (fop2[30-:8] < 8'd150) begin - ftoi_rshift = sv2v_cast_6(8'd150 - fop2[30-:8]); - ftoi_lshift_nxt = 0; - end - else begin - ftoi_rshift = 6'd0; - ftoi_lshift_nxt = sv2v_cast_6(fop2[30-:8] - 8'd150); - end - end - always @(*) begin - if (_sv2v_0) - ; - if (itof) - logical_subtract = of_operand2[(lane_idx * 32) + 31]; - else if (ftoi) - logical_subtract = fop2[31]; - else - logical_subtract = (fop1[31] ^ fop2[31]) ^ subtract; - end - always @(*) begin - if (_sv2v_0) - ; - if (itof) - result_nan = 0; - else if (fmul) - result_nan = ((fop1_nan || fop2_nan) || (fop1_inf && (of_operand2[lane_idx * 32+:32] == 0))) || (fop2_inf && (of_operand1[lane_idx * 32+:32] == 0)); - else if (ftoi) - result_nan = (fop2_nan || fop2_inf) || (fop2[30-:8] >= 8'd159); - else if (compare) - result_nan = fop1_nan || fop2_nan; - else - result_nan = (fop1_nan || fop2_nan) || ((fop1_inf && fop2_inf) && logical_subtract); - end - assign equal = ((fop1_inf && fop2_inf) && (fop1[31] == fop2[31])) || ((!fop1_inf && !fop2_inf) && (fop1 == fop2)); - assign {mul_exponent_underflow, mul_exponent_carry, mul_exponent} = ({2'd0, fop1[30-:8]} + {2'd0, fop2[30-:8]}) - 10'd127; - assign op1_larger = (fop1[30-:8] > fop2[30-:8]) || ((fop1[30-:8] == fop2[30-:8]) && (full_significand1 >= full_significand2)); - assign exp_difference = (op1_larger ? fop1[30-:8] - fop2[30-:8] : fop2[30-:8] - fop1[30-:8]); - always @(posedge clk) begin - fx1_result_nan[lane_idx] <= result_nan; - fx1_result_inf[lane_idx] <= (!itof && !result_nan) && ((fop1_inf || fop2_inf) || ((fmul && mul_exponent_carry) && !mul_exponent_underflow)); - fx1_equal[lane_idx] <= equal; - fx1_mul_underflow[lane_idx] <= mul_exponent_underflow; - if ((op1_larger || ftoi) || itof) begin - if (ftoi || itof) - fx1_significand_le[lane_idx * 32+:32] <= 0; - else - fx1_significand_le[lane_idx * 32+:32] <= sv2v_cast_32(full_significand1); - if (itof) begin - fx1_significand_se[lane_idx * 32+:32] <= of_operand2[lane_idx * 32+:32]; - fx1_add_exponent[lane_idx * 8+:8] <= 8'd127 + 8'd23; - fx1_add_result_sign[lane_idx] <= of_operand2[(lane_idx * 32) + 31]; - end - else begin - fx1_significand_se[lane_idx * 32+:32] <= sv2v_cast_32(full_significand2); - fx1_add_exponent[lane_idx * 8+:8] <= fop1[30-:8]; - fx1_add_result_sign[lane_idx] <= fop1[31]; - end - end - else begin - fx1_significand_le[lane_idx * 32+:32] <= sv2v_cast_32(full_significand2); - fx1_significand_se[lane_idx * 32+:32] <= sv2v_cast_32(full_significand1); - fx1_add_exponent[lane_idx * 8+:8] <= fop2[30-:8]; - fx1_add_result_sign[lane_idx] <= fop2[31] ^ subtract; - end - fx1_logical_subtract[lane_idx] <= logical_subtract; - if (itof) - fx1_se_align_shift[lane_idx * 6+:6] <= 0; - else if (ftoi) - fx1_se_align_shift[lane_idx * 6+:6] <= ftoi_rshift[5:0]; - else - fx1_se_align_shift[lane_idx * 6+:6] <= (exp_difference < 8'd27 ? sv2v_cast_6(exp_difference) : 6'd27); - fx1_ftoi_lshift[lane_idx * 6+:6] <= ftoi_lshift_nxt; - if (imul) begin - fx1_multiplicand[lane_idx * 32+:32] <= of_operand1[lane_idx * 32+:32]; - fx1_multiplier[lane_idx * 32+:32] <= of_operand2[lane_idx * 32+:32]; - end - else begin - fx1_multiplicand[lane_idx * 32+:32] <= sv2v_cast_32(full_significand1); - fx1_multiplier[lane_idx * 32+:32] <= sv2v_cast_32(full_significand2); - end - fx1_mul_exponent[lane_idx * 8+:8] <= mul_exponent; - fx1_mul_sign[lane_idx] <= fop1[31] ^ fop2[31]; - end - end - endgenerate - always @(posedge clk) begin - fx1_instruction <= of_instruction; - fx1_mask_value <= of_mask_value; - fx1_thread_idx <= of_thread_idx; - fx1_subcycle <= of_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx1_instruction_valid <= 1'sb0; - else - fx1_instruction_valid <= (of_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != of_thread_idx))) && (of_instruction[21-:2] == 2'd2); - initial _sv2v_0 = 0; -endmodule -module fp_execute_stage2 ( - clk, - reset, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pipeline, - fx1_mask_value, - fx1_instruction_valid, - fx1_instruction, - fx1_thread_idx, - fx1_subcycle, - fx1_result_inf, - fx1_result_nan, - fx1_equal, - fx1_ftoi_lshift, - fx1_significand_le, - fx1_significand_se, - fx1_logical_subtract, - fx1_se_align_shift, - fx1_add_exponent, - fx1_add_result_sign, - fx1_mul_exponent, - fx1_mul_sign, - fx1_multiplicand, - fx1_multiplier, - fx1_mul_underflow, - fx2_instruction_valid, - fx2_instruction, - fx2_mask_value, - fx2_thread_idx, - fx2_subcycle, - fx2_result_inf, - fx2_result_nan, - fx2_equal, - fx2_ftoi_lshift, - fx2_logical_subtract, - fx2_add_result_sign, - fx2_significand_le, - fx2_significand_se, - fx2_add_exponent, - fx2_guard, - fx2_round, - fx2_sticky, - fx2_significand_product, - fx2_mul_exponent, - fx2_mul_underflow, - fx2_mul_sign -); - input clk; - input reset; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wire [1:0] wb_rollback_pipeline; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx1_mask_value; - input fx1_instruction_valid; - input wire [141:0] fx1_instruction; - input wire [1:0] fx1_thread_idx; - input wire [3:0] fx1_subcycle; - input [15:0] fx1_result_inf; - input [15:0] fx1_result_nan; - input [15:0] fx1_equal; - input [95:0] fx1_ftoi_lshift; - input wire [511:0] fx1_significand_le; - input wire [511:0] fx1_significand_se; - input [15:0] fx1_logical_subtract; - input [95:0] fx1_se_align_shift; - input [127:0] fx1_add_exponent; - input [15:0] fx1_add_result_sign; - input [127:0] fx1_mul_exponent; - input [15:0] fx1_mul_sign; - input [511:0] fx1_multiplicand; - input [511:0] fx1_multiplier; - input [15:0] fx1_mul_underflow; - output reg fx2_instruction_valid; - output reg [141:0] fx2_instruction; - output reg [15:0] fx2_mask_value; - output reg [1:0] fx2_thread_idx; - output reg [3:0] fx2_subcycle; - output reg [15:0] fx2_result_inf; - output reg [15:0] fx2_result_nan; - output reg [15:0] fx2_equal; - output reg [95:0] fx2_ftoi_lshift; - output reg [15:0] fx2_logical_subtract; - output reg [15:0] fx2_add_result_sign; - output reg [511:0] fx2_significand_le; - output reg [511:0] fx2_significand_se; - output reg [127:0] fx2_add_exponent; - output reg [15:0] fx2_guard; - output reg [15:0] fx2_round; - output reg [15:0] fx2_sticky; - output reg [1023:0] fx2_significand_product; - output reg [127:0] fx2_mul_exponent; - output reg [15:0] fx2_mul_underflow; - output reg [15:0] fx2_mul_sign; - wire imulhs; - assign imulhs = fx1_instruction[70-:6] == 6'b011111; - genvar _gv_lane_idx_2; - generate - for (_gv_lane_idx_2 = 0; _gv_lane_idx_2 < defines_NUM_VECTOR_LANES; _gv_lane_idx_2 = _gv_lane_idx_2 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_2; - wire [31:0] aligned_significand; - wire guard; - wire round; - wire [24:0] sticky_bits; - wire sticky; - wire [63:0] sext_multiplicand; - wire [63:0] sext_multiplier; - assign {aligned_significand, guard, round, sticky_bits} = {fx1_significand_se[lane_idx * 32+:32], 27'd0} >> fx1_se_align_shift[lane_idx * 6+:6]; - assign sticky = |sticky_bits; - assign sext_multiplicand = {{32 {fx1_multiplicand[(lane_idx * 32) + 31] && imulhs}}, fx1_multiplicand[lane_idx * 32+:32]}; - assign sext_multiplier = {{32 {fx1_multiplier[(lane_idx * 32) + 31] && imulhs}}, fx1_multiplier[lane_idx * 32+:32]}; - always @(posedge clk) begin - fx2_significand_le[lane_idx * 32+:32] <= fx1_significand_le[lane_idx * 32+:32]; - fx2_significand_se[lane_idx * 32+:32] <= aligned_significand; - fx2_add_exponent[lane_idx * 8+:8] <= fx1_add_exponent[lane_idx * 8+:8]; - fx2_logical_subtract[lane_idx] <= fx1_logical_subtract[lane_idx]; - fx2_add_result_sign[lane_idx] <= fx1_add_result_sign[lane_idx]; - fx2_guard[lane_idx] <= guard; - fx2_round[lane_idx] <= round; - fx2_sticky[lane_idx] <= sticky; - fx2_mul_exponent[lane_idx * 8+:8] <= fx1_mul_exponent[lane_idx * 8+:8]; - fx2_mul_underflow[lane_idx] <= fx1_mul_underflow[lane_idx]; - fx2_mul_sign[lane_idx] <= fx1_mul_sign[lane_idx]; - fx2_result_inf[lane_idx] <= fx1_result_inf[lane_idx]; - fx2_result_nan[lane_idx] <= fx1_result_nan[lane_idx]; - fx2_equal[lane_idx] <= fx1_equal[lane_idx]; - fx2_ftoi_lshift[lane_idx * 6+:6] <= fx1_ftoi_lshift[lane_idx * 6+:6]; - fx2_significand_product[lane_idx * 64+:64] <= sext_multiplicand * sext_multiplier; - end - end - endgenerate - always @(posedge clk) begin - fx2_instruction <= fx1_instruction; - fx2_mask_value <= fx1_mask_value; - fx2_thread_idx <= fx1_thread_idx; - fx2_subcycle <= fx1_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx2_instruction_valid <= 1'sb0; - else - fx2_instruction_valid <= fx1_instruction_valid && ((!wb_rollback_en || (wb_rollback_thread_idx != fx1_thread_idx)) || (wb_rollback_pipeline != 2'd0)); -endmodule -module fp_execute_stage3 ( - clk, - reset, - fx2_mask_value, - fx2_instruction_valid, - fx2_instruction, - fx2_thread_idx, - fx2_subcycle, - fx2_result_inf, - fx2_result_nan, - fx2_equal, - fx2_ftoi_lshift, - fx2_significand_le, - fx2_significand_se, - fx2_logical_subtract, - fx2_add_exponent, - fx2_add_result_sign, - fx2_guard, - fx2_round, - fx2_sticky, - fx2_significand_product, - fx2_mul_exponent, - fx2_mul_underflow, - fx2_mul_sign, - fx3_instruction_valid, - fx3_instruction, - fx3_mask_value, - fx3_thread_idx, - fx3_subcycle, - fx3_result_inf, - fx3_result_nan, - fx3_equal, - fx3_ftoi_lshift, - fx3_add_significand, - fx3_add_exponent, - fx3_add_result_sign, - fx3_logical_subtract, - fx3_significand_product, - fx3_mul_exponent, - fx3_mul_underflow, - fx3_mul_sign -); - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx2_mask_value; - input fx2_instruction_valid; - input wire [141:0] fx2_instruction; - input wire [1:0] fx2_thread_idx; - input wire [3:0] fx2_subcycle; - input [15:0] fx2_result_inf; - input [15:0] fx2_result_nan; - input [15:0] fx2_equal; - input [95:0] fx2_ftoi_lshift; - input wire [511:0] fx2_significand_le; - input wire [511:0] fx2_significand_se; - input [15:0] fx2_logical_subtract; - input [127:0] fx2_add_exponent; - input [15:0] fx2_add_result_sign; - input [15:0] fx2_guard; - input [15:0] fx2_round; - input [15:0] fx2_sticky; - input [1023:0] fx2_significand_product; - input [127:0] fx2_mul_exponent; - input [15:0] fx2_mul_underflow; - input [15:0] fx2_mul_sign; - output reg fx3_instruction_valid; - output reg [141:0] fx3_instruction; - output reg [15:0] fx3_mask_value; - output reg [1:0] fx3_thread_idx; - output reg [3:0] fx3_subcycle; - output reg [15:0] fx3_result_inf; - output reg [15:0] fx3_result_nan; - output reg [15:0] fx3_equal; - output reg [95:0] fx3_ftoi_lshift; - output reg [511:0] fx3_add_significand; - output reg [127:0] fx3_add_exponent; - output reg [15:0] fx3_add_result_sign; - output reg [15:0] fx3_logical_subtract; - output reg [1023:0] fx3_significand_product; - output reg [127:0] fx3_mul_exponent; - output reg [15:0] fx3_mul_underflow; - output reg [15:0] fx3_mul_sign; - wire ftoi; - assign ftoi = fx2_instruction[70-:6] == 6'b011011; - genvar _gv_lane_idx_3; - generate - for (_gv_lane_idx_3 = 0; _gv_lane_idx_3 < defines_NUM_VECTOR_LANES; _gv_lane_idx_3 = _gv_lane_idx_3 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_3; - wire carry_in; - wire [31:0] unnormalized_sum; - wire sum_odd; - wire round_up; - wire round_tie; - wire do_round; - wire _unused; - assign sum_odd = fx2_significand_le[lane_idx * 32] ^ fx2_significand_se[lane_idx * 32]; - assign round_tie = fx2_guard[lane_idx] && !(fx2_round[lane_idx] || fx2_sticky[lane_idx]); - assign round_up = fx2_guard[lane_idx] && (fx2_round[lane_idx] || fx2_sticky[lane_idx]); - assign do_round = round_up || (sum_odd && round_tie); - assign carry_in = fx2_logical_subtract[lane_idx] ^ (do_round && !ftoi); - assign {unnormalized_sum, _unused} = {fx2_significand_le[lane_idx * 32+:32], 1'b1} + {fx2_significand_se[lane_idx * 32+:32] ^ {32 {fx2_logical_subtract[lane_idx]}}, carry_in}; - always @(posedge clk) begin - fx3_result_inf[lane_idx] <= fx2_result_inf[lane_idx]; - fx3_result_nan[lane_idx] <= fx2_result_nan[lane_idx]; - fx3_equal[lane_idx] <= fx2_equal[lane_idx]; - fx3_equal[lane_idx] <= fx2_equal[lane_idx]; - fx3_ftoi_lshift[lane_idx * 6+:6] <= fx2_ftoi_lshift[lane_idx * 6+:6]; - fx3_add_significand[lane_idx * 32+:32] <= unnormalized_sum; - fx3_add_exponent[lane_idx * 8+:8] <= fx2_add_exponent[lane_idx * 8+:8]; - fx3_logical_subtract[lane_idx] <= fx2_logical_subtract[lane_idx]; - fx3_add_result_sign[lane_idx] <= fx2_add_result_sign[lane_idx]; - fx3_significand_product[lane_idx * 64+:64] <= fx2_significand_product[lane_idx * 64+:64]; - fx3_mul_exponent[lane_idx * 8+:8] <= fx2_mul_exponent[lane_idx * 8+:8]; - fx3_mul_underflow[lane_idx] <= fx2_mul_underflow[lane_idx]; - fx3_mul_sign[lane_idx] <= fx2_mul_sign[lane_idx]; - end - end - endgenerate - always @(posedge clk) begin - fx3_instruction <= fx2_instruction; - fx3_mask_value <= fx2_mask_value; - fx3_thread_idx <= fx2_thread_idx; - fx3_subcycle <= fx2_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx3_instruction_valid <= 1'sb0; - else - fx3_instruction_valid <= fx2_instruction_valid; -endmodule -module fp_execute_stage4 ( - clk, - reset, - fx3_mask_value, - fx3_instruction_valid, - fx3_instruction, - fx3_thread_idx, - fx3_subcycle, - fx3_result_inf, - fx3_result_nan, - fx3_equal, - fx3_ftoi_lshift, - fx3_add_significand, - fx3_add_exponent, - fx3_add_result_sign, - fx3_logical_subtract, - fx3_significand_product, - fx3_mul_exponent, - fx3_mul_underflow, - fx3_mul_sign, - fx4_instruction_valid, - fx4_instruction, - fx4_mask_value, - fx4_thread_idx, - fx4_subcycle, - fx4_result_inf, - fx4_result_nan, - fx4_equal, - fx4_add_exponent, - fx4_add_significand, - fx4_add_result_sign, - fx4_logical_subtract, - fx4_norm_shift, - fx4_significand_product, - fx4_mul_exponent, - fx4_mul_underflow, - fx4_mul_sign -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx3_mask_value; - input fx3_instruction_valid; - input wire [141:0] fx3_instruction; - input wire [1:0] fx3_thread_idx; - input wire [3:0] fx3_subcycle; - input [15:0] fx3_result_inf; - input [15:0] fx3_result_nan; - input [15:0] fx3_equal; - input [95:0] fx3_ftoi_lshift; - input wire [511:0] fx3_add_significand; - input [127:0] fx3_add_exponent; - input [15:0] fx3_add_result_sign; - input [15:0] fx3_logical_subtract; - input [1023:0] fx3_significand_product; - input [127:0] fx3_mul_exponent; - input [15:0] fx3_mul_underflow; - input [15:0] fx3_mul_sign; - output reg fx4_instruction_valid; - output reg [141:0] fx4_instruction; - output reg [15:0] fx4_mask_value; - output reg [1:0] fx4_thread_idx; - output reg [3:0] fx4_subcycle; - output reg [15:0] fx4_result_inf; - output reg [15:0] fx4_result_nan; - output reg [15:0] fx4_equal; - output reg [127:0] fx4_add_exponent; - output reg [511:0] fx4_add_significand; - output reg [15:0] fx4_add_result_sign; - output reg [15:0] fx4_logical_subtract; - output reg [95:0] fx4_norm_shift; - output reg [1023:0] fx4_significand_product; - output reg [127:0] fx4_mul_exponent; - output reg [15:0] fx4_mul_underflow; - output reg [15:0] fx4_mul_sign; - wire ftoi; - assign ftoi = fx3_instruction[70-:6] == 6'b011011; - genvar _gv_lane_idx_4; - generate - for (_gv_lane_idx_4 = 0; _gv_lane_idx_4 < defines_NUM_VECTOR_LANES; _gv_lane_idx_4 = _gv_lane_idx_4 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_4; - reg [5:0] leading_zeroes; - always @(*) begin - if (_sv2v_0) - ; - leading_zeroes = 0; - (* full_case, parallel_case *) - casez (fx3_add_significand[lane_idx * 32+:32]) - 32'b1zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 0; - 32'b01zzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 1; - 32'b001zzzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 2; - 32'b0001zzzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 3; - 32'b00001zzzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 4; - 32'b000001zzzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 5; - 32'b0000001zzzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 6; - 32'b00000001zzzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 7; - 32'b000000001zzzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 8; - 32'b0000000001zzzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 9; - 32'b00000000001zzzzzzzzzzzzzzzzzzzzz: leading_zeroes = 10; - 32'b000000000001zzzzzzzzzzzzzzzzzzzz: leading_zeroes = 11; - 32'b0000000000001zzzzzzzzzzzzzzzzzzz: leading_zeroes = 12; - 32'b00000000000001zzzzzzzzzzzzzzzzzz: leading_zeroes = 13; - 32'b000000000000001zzzzzzzzzzzzzzzzz: leading_zeroes = 14; - 32'b0000000000000001zzzzzzzzzzzzzzzz: leading_zeroes = 15; - 32'b00000000000000001zzzzzzzzzzzzzzz: leading_zeroes = 16; - 32'b000000000000000001zzzzzzzzzzzzzz: leading_zeroes = 17; - 32'b0000000000000000001zzzzzzzzzzzzz: leading_zeroes = 18; - 32'b00000000000000000001zzzzzzzzzzzz: leading_zeroes = 19; - 32'b000000000000000000001zzzzzzzzzzz: leading_zeroes = 20; - 32'b0000000000000000000001zzzzzzzzzz: leading_zeroes = 21; - 32'b00000000000000000000001zzzzzzzzz: leading_zeroes = 22; - 32'b000000000000000000000001zzzzzzzz: leading_zeroes = 23; - 32'b0000000000000000000000001zzzzzzz: leading_zeroes = 24; - 32'b00000000000000000000000001zzzzzz: leading_zeroes = 25; - 32'b000000000000000000000000001zzzzz: leading_zeroes = 26; - 32'b0000000000000000000000000001zzzz: leading_zeroes = 27; - 32'b00000000000000000000000000001zzz: leading_zeroes = 28; - 32'b000000000000000000000000000001zz: leading_zeroes = 29; - 32'b0000000000000000000000000000001z: leading_zeroes = 30; - 32'b00000000000000000000000000000001: leading_zeroes = 31; - 32'b00000000000000000000000000000000: leading_zeroes = 32; - default: leading_zeroes = 0; - endcase - end - always @(posedge clk) begin - fx4_add_significand[lane_idx * 32+:32] <= fx3_add_significand[lane_idx * 32+:32]; - fx4_norm_shift[lane_idx * 6+:6] <= (ftoi ? fx3_ftoi_lshift[lane_idx * 6+:6] : leading_zeroes); - fx4_add_exponent[lane_idx * 8+:8] <= fx3_add_exponent[lane_idx * 8+:8]; - fx4_add_result_sign[lane_idx] <= fx3_add_result_sign[lane_idx]; - fx4_logical_subtract[lane_idx] <= fx3_logical_subtract[lane_idx]; - fx4_significand_product[lane_idx * 64+:64] <= fx3_significand_product[lane_idx * 64+:64]; - fx4_mul_exponent[lane_idx * 8+:8] <= fx3_mul_exponent[lane_idx * 8+:8]; - fx4_mul_underflow[lane_idx] <= fx3_mul_underflow[lane_idx]; - fx4_mul_sign[lane_idx] <= fx3_mul_sign[lane_idx]; - fx4_result_inf[lane_idx] <= fx3_result_inf[lane_idx]; - fx4_result_nan[lane_idx] <= fx3_result_nan[lane_idx]; - fx4_equal[lane_idx] <= fx3_equal[lane_idx]; - end - end - endgenerate - always @(posedge clk) begin - fx4_instruction <= fx3_instruction; - fx4_mask_value <= fx3_mask_value; - fx4_thread_idx <= fx3_thread_idx; - fx4_subcycle <= fx3_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx4_instruction_valid <= 1'sb0; - else - fx4_instruction_valid <= fx3_instruction_valid; - initial _sv2v_0 = 0; -endmodule -module fp_execute_stage5 ( - clk, - reset, - fx4_mask_value, - fx4_instruction_valid, - fx4_instruction, - fx4_thread_idx, - fx4_subcycle, - fx4_result_inf, - fx4_result_nan, - fx4_equal, - fx4_add_exponent, - fx4_add_significand, - fx4_add_result_sign, - fx4_logical_subtract, - fx4_norm_shift, - fx4_significand_product, - fx4_mul_exponent, - fx4_mul_underflow, - fx4_mul_sign, - fx5_instruction_valid, - fx5_instruction, - fx5_mask_value, - fx5_thread_idx, - fx5_subcycle, - fx5_result -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [15:0] fx4_mask_value; - input fx4_instruction_valid; - input wire [141:0] fx4_instruction; - input wire [1:0] fx4_thread_idx; - input wire [3:0] fx4_subcycle; - input [15:0] fx4_result_inf; - input [15:0] fx4_result_nan; - input [15:0] fx4_equal; - input [127:0] fx4_add_exponent; - input wire [511:0] fx4_add_significand; - input [15:0] fx4_add_result_sign; - input [15:0] fx4_logical_subtract; - input [95:0] fx4_norm_shift; - input [1023:0] fx4_significand_product; - input [127:0] fx4_mul_exponent; - input [15:0] fx4_mul_underflow; - input [15:0] fx4_mul_sign; - output reg fx5_instruction_valid; - output reg [141:0] fx5_instruction; - output reg [15:0] fx5_mask_value; - output reg [1:0] fx5_thread_idx; - output reg [3:0] fx5_subcycle; - output reg [511:0] fx5_result; - wire fmul; - wire imull; - wire imulh; - wire ftoi; - assign fmul = fx4_instruction[70-:6] == 6'b100010; - assign imull = fx4_instruction[70-:6] == 6'b000111; - assign imulh = (fx4_instruction[70-:6] == 6'b001000) || (fx4_instruction[70-:6] == 6'b011111); - assign ftoi = fx4_instruction[70-:6] == 6'b011011; - genvar _gv_lane_idx_5; - localparam defines_FLOAT32_EXP_WIDTH = 8; - localparam defines_FLOAT32_SIG_WIDTH = 23; - function automatic [7:0] sv2v_cast_8; - input reg [7:0] inp; - sv2v_cast_8 = inp; - endfunction - function automatic [22:0] sv2v_cast_23; - input reg [22:0] inp; - sv2v_cast_23 = inp; - endfunction - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - generate - for (_gv_lane_idx_5 = 0; _gv_lane_idx_5 < defines_NUM_VECTOR_LANES; _gv_lane_idx_5 = _gv_lane_idx_5 + 1) begin : lane_logic_gen - localparam lane_idx = _gv_lane_idx_5; - wire [22:0] add_result_significand; - wire [7:0] add_result_exponent; - wire [7:0] adjusted_add_exponent; - wire [31:0] shifted_significand; - wire add_subnormal; - reg [31:0] add_result; - wire add_round; - wire add_overflow; - wire mul_normalize_shift; - wire [22:0] mul_normalized_significand; - wire [22:0] mul_rounded_significand; - reg [31:0] fmul_result; - reg [7:0] mul_exponent; - wire mul_guard; - wire mul_round; - wire [21:0] mul_sticky_bits; - wire mul_sticky; - wire mul_round_tie; - wire mul_round_up; - wire mul_do_round; - reg compare_result; - wire sum_zero; - wire mul_hidden_bit; - wire mul_round_overflow; - assign adjusted_add_exponent = (fx4_add_exponent[lane_idx * 8+:8] - sv2v_cast_8(fx4_norm_shift[lane_idx * 6+:6])) + 8'sd8; - assign add_subnormal = (fx4_add_exponent[lane_idx * 8+:8] == 0) || (fx4_add_significand[lane_idx * 32+:32] == 0); - assign shifted_significand = fx4_add_significand[lane_idx * 32+:32] << fx4_norm_shift[lane_idx * 6+:6]; - assign add_round = (shifted_significand[7] && shifted_significand[8]) && !fx4_logical_subtract[lane_idx]; - assign add_result_significand = (add_subnormal ? fx4_add_significand[(lane_idx * 32) + 22-:23] : shifted_significand[30:8] + sv2v_cast_23(add_round)); - assign add_result_exponent = (add_subnormal ? {8 {1'sb0}} : adjusted_add_exponent); - assign add_overflow = (add_result_exponent == 8'hff) && !fx4_result_nan[lane_idx]; - always @(*) begin - if (_sv2v_0) - ; - if (fx4_result_inf[lane_idx] || add_overflow) - add_result = {fx4_add_result_sign[lane_idx], 31'h7f800000}; - else if (fx4_result_nan[lane_idx]) - add_result = 32'h7fffffff; - else if ((add_result_significand == 0) && add_subnormal) - add_result = 0; - else - add_result = {fx4_add_result_sign[lane_idx], add_result_exponent, add_result_significand}; - end - assign sum_zero = add_subnormal && (add_result_significand == 0); - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (fx4_instruction[70-:6]) - 6'b101100: compare_result = (!fx4_add_result_sign[lane_idx] && !fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b101101: compare_result = (!fx4_add_result_sign[lane_idx] || fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b101110: compare_result = (fx4_add_result_sign[lane_idx] && !fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b101111: compare_result = (fx4_add_result_sign[lane_idx] || fx4_equal[lane_idx]) && !fx4_result_nan[lane_idx]; - 6'b110000: compare_result = fx4_equal[lane_idx] && !fx4_result_nan[lane_idx]; - 6'b110001: compare_result = !fx4_equal[lane_idx] || fx4_result_nan[lane_idx]; - default: compare_result = 0; - endcase - end - assign mul_normalize_shift = !fx4_significand_product[(lane_idx * 64) + 47]; - assign {mul_normalized_significand, mul_guard, mul_round, mul_sticky_bits} = (mul_normalize_shift ? {fx4_significand_product[(lane_idx * 64) + 45-:46], 1'b0} : fx4_significand_product[(lane_idx * 64) + 46-:47]); - assign mul_sticky = |mul_sticky_bits; - assign mul_round_tie = mul_guard && !(mul_round || mul_sticky); - assign mul_round_up = mul_guard && (mul_round || mul_sticky); - assign mul_do_round = mul_round_up || (mul_round_tie && mul_normalized_significand[0]); - assign mul_rounded_significand = mul_normalized_significand + sv2v_cast_23(mul_do_round); - assign mul_hidden_bit = (mul_normalize_shift ? fx4_significand_product[(lane_idx * 64) + 46] : 1'b1); - assign mul_round_overflow = mul_do_round && (mul_rounded_significand == 0); - always @(*) begin - if (_sv2v_0) - ; - if (!mul_hidden_bit) - mul_exponent = 0; - else if (mul_normalize_shift && !mul_round_overflow) - mul_exponent = fx4_mul_exponent[lane_idx * 8+:8]; - else - mul_exponent = fx4_mul_exponent[lane_idx * 8+:8] + 8'sd1; - end - always @(*) begin - if (_sv2v_0) - ; - if (fx4_result_inf[lane_idx]) - fmul_result = {fx4_mul_sign[lane_idx], 31'h7f800000}; - else if (fx4_result_nan[lane_idx]) - fmul_result = 32'h7fffffff; - else - fmul_result = {fx4_mul_sign[lane_idx], mul_exponent, mul_rounded_significand}; - end - always @(posedge clk) - if (ftoi) begin - if (fx4_result_nan[lane_idx]) - fx5_result[lane_idx * 32+:32] <= 32'h80000000; - else - fx5_result[lane_idx * 32+:32] <= shifted_significand; - end - else if (fx4_instruction[13]) - fx5_result[lane_idx * 32+:32] <= sv2v_cast_32(compare_result); - else if (imull) - fx5_result[lane_idx * 32+:32] <= fx4_significand_product[(lane_idx * 64) + 31-:32]; - else if (imulh) - fx5_result[lane_idx * 32+:32] <= fx4_significand_product[(lane_idx * 64) + 63-:32]; - else if (fmul) - fx5_result[lane_idx * 32+:32] <= (fx4_mul_underflow[lane_idx] ? 32'h00000000 : fmul_result); - else - fx5_result[lane_idx * 32+:32] <= add_result; - end - endgenerate - always @(posedge clk) begin - fx5_instruction <= fx4_instruction; - fx5_mask_value <= fx4_mask_value; - fx5_thread_idx <= fx4_thread_idx; - fx5_subcycle <= fx4_subcycle; - end - always @(posedge clk or posedge reset) - if (reset) - fx5_instruction_valid <= 1'sb0; - else - fx5_instruction_valid <= fx4_instruction_valid; - initial _sv2v_0 = 0; -endmodule -module idx_to_oh ( - one_hot, - index -); - reg _sv2v_0; - parameter NUM_SIGNALS = 4; - parameter DIRECTION = "LSB0"; - parameter INDEX_WIDTH = $clog2(NUM_SIGNALS); - output reg [NUM_SIGNALS - 1:0] one_hot; - input [INDEX_WIDTH - 1:0] index; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(*) begin : convert - if (_sv2v_0) - ; - one_hot = 0; - if (DIRECTION == "LSB0") - one_hot[index] = 1'b1; - else - one_hot[(NUM_SIGNALS - sv2v_cast_32(index)) - 1] = 1'b1; - end - initial _sv2v_0 = 0; -endmodule -module ifetch_data_stage ( - clk, - reset, - ift_instruction_requested, - ift_pc_paddr, - ift_pc_vaddr, - ift_thread_idx, - ift_tlb_hit, - ift_tlb_present, - ift_tlb_executable, - ift_tlb_supervisor, - ift_tag, - ift_valid, - ifd_update_lru_en, - ifd_update_lru_way, - ifd_near_miss, - l2i_idata_update_en, - l2i_idata_update_way, - l2i_idata_update_set, - l2i_idata_update_data, - l2i_itag_update_en, - l2i_itag_update_set, - l2i_itag_update_tag, - ifd_cache_miss, - ifd_cache_miss_paddr, - ifd_cache_miss_thread_idx, - cr_supervisor_en, - ifd_instruction, - ifd_instruction_valid, - ifd_pc, - ifd_thread_idx, - ifd_alignment_fault, - ifd_tlb_miss, - ifd_supervisor_fault, - ifd_page_fault, - ifd_executable_fault, - ifd_inst_injected, - wb_rollback_en, - wb_rollback_thread_idx, - ifd_perf_icache_hit, - ifd_perf_icache_miss, - ifd_perf_itlb_miss, - core_selected_debug, - ocd_halt, - ocd_inject_inst, - ocd_inject_en, - ocd_thread -); - input clk; - input reset; - input ift_instruction_requested; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_ICACHE_TAG_BITS = 20; - input wire [31:0] ift_pc_paddr; - input wire [31:0] ift_pc_vaddr; - input wire [1:0] ift_thread_idx; - input ift_tlb_hit; - input ift_tlb_present; - input ift_tlb_executable; - input ift_tlb_supervisor; - input wire [79:0] ift_tag; - input [0:3] ift_valid; - output wire ifd_update_lru_en; - output wire [1:0] ifd_update_lru_way; - output wire ifd_near_miss; - input l2i_idata_update_en; - input wire [1:0] l2i_idata_update_way; - input wire [5:0] l2i_idata_update_set; - localparam defines_CACHE_LINE_BITS = 512; - input wire [511:0] l2i_idata_update_data; - input [3:0] l2i_itag_update_en; - input wire [5:0] l2i_itag_update_set; - input wire [19:0] l2i_itag_update_tag; - output wire ifd_cache_miss; - output wire [25:0] ifd_cache_miss_paddr; - output wire [1:0] ifd_cache_miss_thread_idx; - input wire [0:3] cr_supervisor_en; - output wire [31:0] ifd_instruction; - output reg ifd_instruction_valid; - output reg [31:0] ifd_pc; - output reg [1:0] ifd_thread_idx; - output reg ifd_alignment_fault; - output reg ifd_tlb_miss; - output reg ifd_supervisor_fault; - output reg ifd_page_fault; - output reg ifd_executable_fault; - output reg ifd_inst_injected; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - output reg ifd_perf_icache_hit; - output reg ifd_perf_icache_miss; - output reg ifd_perf_itlb_miss; - input core_selected_debug; - input ocd_halt; - input wire [31:0] ocd_inject_inst; - input wire ocd_inject_en; - input wire [1:0] ocd_thread; - wire cache_hit; - wire [3:0] way_hit_oh; - wire [1:0] way_hit_idx; - wire [511:0] fetched_cache_line; - wire [31:0] fetched_word; - localparam defines_CACHE_LINE_WORDS = 16; - wire [3:0] cache_lane_idx; - wire alignment_fault; - wire squash_instruction; - reg ocd_halt_latched; - assign squash_instruction = wb_rollback_en && (wb_rollback_thread_idx == ift_thread_idx); - genvar _gv_way_idx_3; - generate - for (_gv_way_idx_3 = 0; _gv_way_idx_3 < 4; _gv_way_idx_3 = _gv_way_idx_3 + 1) begin : hit_check_gen - localparam way_idx = _gv_way_idx_3; - assign way_hit_oh[way_idx] = (ift_pc_paddr[31-:20] == ift_tag[(3 - way_idx) * defines_ICACHE_TAG_BITS+:defines_ICACHE_TAG_BITS]) && ift_valid[way_idx]; - end - endgenerate - assign cache_hit = |way_hit_oh && ift_tlb_hit; - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_hit_way( - .one_hot(way_hit_oh), - .index(way_hit_idx) - ); - assign ifd_near_miss = ((((!cache_hit && ift_tlb_hit) && ift_instruction_requested) && |l2i_itag_update_en) && (l2i_itag_update_set == ift_pc_paddr[11-:6])) && (l2i_itag_update_tag == ift_pc_paddr[31-:20]); - assign ifd_cache_miss = (((!cache_hit && ift_tlb_hit) && ift_instruction_requested) && !ifd_near_miss) && !squash_instruction; - assign ifd_cache_miss_paddr = {ift_pc_paddr[31-:20], ift_pc_paddr[11-:6]}; - assign ifd_cache_miss_thread_idx = ift_thread_idx; - assign alignment_fault = ift_pc_paddr[1:0] != 0; - fakeram_1r1w_512x256 #( - .DATA_WIDTH(defines_CACHE_LINE_BITS), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) sram_l1i_data( - .read_en(cache_hit && ift_instruction_requested), - .read_addr({way_hit_idx, ift_pc_paddr[11-:6]}), - .read_data(fetched_cache_line), - .write_en(l2i_idata_update_en), - .write_addr({l2i_idata_update_way, l2i_idata_update_set}), - .write_data(l2i_idata_update_data), - .* - ); - assign cache_lane_idx = ~ifd_pc[5:2]; - assign fetched_word = fetched_cache_line[32 * cache_lane_idx+:32]; - assign ifd_instruction = (ocd_halt_latched ? ocd_inject_inst : {fetched_word[7:0], fetched_word[15:8], fetched_word[23:16], fetched_word[31:24]}); - assign ifd_update_lru_en = cache_hit && ift_instruction_requested; - assign ifd_update_lru_way = way_hit_idx; - always @(posedge clk) begin - ifd_pc <= ift_pc_vaddr; - ifd_thread_idx <= (ocd_halt ? ocd_thread : ift_thread_idx); - end - always @(posedge clk or posedge reset) - if (reset) begin - ifd_alignment_fault <= 1'sb0; - ifd_executable_fault <= 1'sb0; - ifd_inst_injected <= 1'sb0; - ifd_instruction_valid <= 1'sb0; - ifd_page_fault <= 1'sb0; - ifd_perf_icache_hit <= 1'sb0; - ifd_perf_icache_miss <= 1'sb0; - ifd_perf_itlb_miss <= 1'sb0; - ifd_supervisor_fault <= 1'sb0; - ifd_tlb_miss <= 1'sb0; - ocd_halt_latched <= 1'sb0; - end - else begin - ocd_halt_latched <= ocd_halt; - if (ocd_halt) begin - ifd_instruction_valid <= ocd_inject_en && core_selected_debug; - ifd_inst_injected <= 1; - ifd_alignment_fault <= 0; - ifd_supervisor_fault <= 0; - ifd_tlb_miss <= 0; - ifd_page_fault <= 0; - ifd_executable_fault <= 0; - end - else begin - ifd_instruction_valid <= ((ift_instruction_requested && !squash_instruction) && cache_hit) && ift_tlb_hit; - ifd_inst_injected <= 0; - ifd_alignment_fault <= (ift_instruction_requested && !squash_instruction) && alignment_fault; - ifd_supervisor_fault <= ((((ift_instruction_requested && !squash_instruction) && ift_tlb_hit) && ift_tlb_present) && ift_tlb_supervisor) && !cr_supervisor_en[ift_thread_idx]; - ifd_tlb_miss <= (ift_instruction_requested && !squash_instruction) && !ift_tlb_hit; - ifd_page_fault <= ((ift_instruction_requested && !squash_instruction) && ift_tlb_hit) && !ift_tlb_present; - ifd_executable_fault <= (((ift_instruction_requested && !squash_instruction) && ift_tlb_hit) && ift_tlb_present) && !ift_tlb_executable; - ifd_perf_icache_hit <= cache_hit && ift_instruction_requested; - ifd_perf_icache_miss <= ((!cache_hit && ift_tlb_hit) && ift_instruction_requested) && !squash_instruction; - ifd_perf_itlb_miss <= ift_instruction_requested && !ift_tlb_hit; - end - end -endmodule -module ifetch_tag_stage ( - clk, - reset, - ifd_update_lru_en, - ifd_update_lru_way, - ifd_cache_miss, - ifd_near_miss, - ifd_cache_miss_thread_idx, - ift_instruction_requested, - ift_pc_paddr, - ift_pc_vaddr, - ift_thread_idx, - ift_tlb_hit, - ift_tlb_present, - ift_tlb_executable, - ift_tlb_supervisor, - ift_tag, - ift_valid, - l2i_icache_lru_fill_en, - l2i_icache_lru_fill_set, - l2i_itag_update_en, - l2i_itag_update_set, - l2i_itag_update_tag, - l2i_itag_update_valid, - l2i_icache_wake_bitmap, - ift_fill_lru, - cr_mmu_en, - cr_current_asid, - dt_invalidate_tlb_en, - dt_invalidate_tlb_all_en, - dt_update_itlb_asid, - dt_update_itlb_vpage_idx, - dt_update_itlb_en, - dt_update_itlb_supervisor, - dt_update_itlb_global, - dt_update_itlb_present, - dt_update_itlb_executable, - dt_update_itlb_ppage_idx, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pc, - ts_fetch_en, - ocd_halt, - ocd_thread -); - reg _sv2v_0; - parameter RESET_PC = 0; - input clk; - input reset; - input ifd_update_lru_en; - input wire [1:0] ifd_update_lru_way; - input ifd_cache_miss; - input ifd_near_miss; - input wire [1:0] ifd_cache_miss_thread_idx; - output reg ift_instruction_requested; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_ICACHE_TAG_BITS = 20; - output wire [31:0] ift_pc_paddr; - output wire [31:0] ift_pc_vaddr; - output reg [1:0] ift_thread_idx; - output reg ift_tlb_hit; - output reg ift_tlb_present; - output reg ift_tlb_executable; - output reg ift_tlb_supervisor; - output wire [79:0] ift_tag; - output reg [0:3] ift_valid; - input l2i_icache_lru_fill_en; - input wire [5:0] l2i_icache_lru_fill_set; - input [3:0] l2i_itag_update_en; - input wire [5:0] l2i_itag_update_set; - input wire [19:0] l2i_itag_update_tag; - input l2i_itag_update_valid; - input wire [3:0] l2i_icache_wake_bitmap; - output wire [1:0] ift_fill_lru; - input [0:3] cr_mmu_en; - localparam defines_ASID_WIDTH = 8; - input [31:0] cr_current_asid; - input dt_invalidate_tlb_en; - input dt_invalidate_tlb_all_en; - input [7:0] dt_update_itlb_asid; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - input wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_vpage_idx; - input dt_update_itlb_en; - input dt_update_itlb_supervisor; - input dt_update_itlb_global; - input dt_update_itlb_present; - input dt_update_itlb_executable; - input wire [defines_PAGE_NUM_BITS - 1:0] dt_update_itlb_ppage_idx; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wire [31:0] wb_rollback_pc; - input wire [3:0] ts_fetch_en; - input ocd_halt; - input wire [1:0] ocd_thread; - reg [31:0] next_program_counter [0:3]; - wire [1:0] selected_thread_idx; - reg [31:0] last_selected_pc; - wire [31:0] pc_to_fetch; - wire [3:0] can_fetch_thread_bitmap; - wire [3:0] selected_thread_oh; - reg [3:0] last_selected_thread_oh; - reg [3:0] icache_wait_threads; - wire [3:0] icache_wait_threads_nxt; - wire [3:0] cache_miss_thread_oh; - wire [3:0] thread_sleep_mask_oh; - wire cache_fetch_en; - wire [defines_PAGE_NUM_BITS - 1:0] tlb_ppage_idx; - reg [defines_PAGE_NUM_BITS - 1:0] ppage_idx; - wire tlb_hit; - wire tlb_supervisor; - wire tlb_present; - wire tlb_executable; - reg [defines_PAGE_NUM_BITS - 1:0] request_vpage_idx; - reg [7:0] request_asid; - assign can_fetch_thread_bitmap = ts_fetch_en & ~icache_wait_threads; - assign cache_fetch_en = (((|can_fetch_thread_bitmap && !dt_update_itlb_en) && !dt_invalidate_tlb_en) && !dt_invalidate_tlb_all_en) && !ocd_halt; - rr_arbiter #(.NUM_REQUESTERS(4)) thread_select_arbiter( - .request(can_fetch_thread_bitmap), - .update_lru(cache_fetch_en), - .grant_oh(selected_thread_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_selected_thread( - .one_hot(selected_thread_oh), - .index(selected_thread_idx) - ); - genvar _gv_thread_idx_3; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_3 = 0; _gv_thread_idx_3 < 4; _gv_thread_idx_3 = _gv_thread_idx_3 + 1) begin : pc_logic_gen - localparam thread_idx = _gv_thread_idx_3; - always @(posedge clk or posedge reset) - if (reset) - next_program_counter[thread_idx] <= RESET_PC; - else if (wb_rollback_en && (wb_rollback_thread_idx == sv2v_cast_2(thread_idx))) - next_program_counter[thread_idx] <= wb_rollback_pc; - else if ((ifd_cache_miss || ifd_near_miss) && last_selected_thread_oh[thread_idx]) - next_program_counter[thread_idx] <= next_program_counter[thread_idx] - 4; - else if (selected_thread_oh[thread_idx] && cache_fetch_en) - next_program_counter[thread_idx] <= next_program_counter[thread_idx] + 4; - end - endgenerate - assign pc_to_fetch = next_program_counter[(ocd_halt ? ocd_thread : selected_thread_idx)]; - genvar _gv_way_idx_4; - generate - for (_gv_way_idx_4 = 0; _gv_way_idx_4 < 4; _gv_way_idx_4 = _gv_way_idx_4 + 1) begin : way_tag_gen - localparam way_idx = _gv_way_idx_4; - reg line_valid [0:63]; - fakeram_1r1w_20x64 #( - .DATA_WIDTH(defines_ICACHE_TAG_BITS), - .SIZE(64), - .READ_DURING_WRITE("NEW_DATA") - ) sram_tags( - .read_en(cache_fetch_en), - .read_addr(pc_to_fetch[11-:6]), - .read_data(ift_tag[(3 - way_idx) * defines_ICACHE_TAG_BITS+:defines_ICACHE_TAG_BITS]), - .write_en(l2i_itag_update_en[way_idx]), - .write_addr(l2i_itag_update_set), - .write_data(l2i_itag_update_tag), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < 64; set_idx = set_idx + 1) - line_valid[set_idx] <= 0; - end - else if (l2i_itag_update_en[way_idx]) - line_valid[l2i_itag_update_set] <= l2i_itag_update_valid; - always @(posedge clk) - if (l2i_itag_update_en[way_idx] && (l2i_itag_update_set == pc_to_fetch[11-:6])) - ift_valid[way_idx] <= l2i_itag_update_valid; - else - ift_valid[way_idx] <= line_valid[pc_to_fetch[11-:6]]; - end - endgenerate - always @(*) begin - if (_sv2v_0) - ; - if (cache_fetch_en) begin - request_vpage_idx = pc_to_fetch[31-:defines_PAGE_NUM_BITS]; - request_asid = cr_current_asid[(3 - selected_thread_idx) * 8+:8]; - end - else begin - request_vpage_idx = dt_update_itlb_vpage_idx; - request_asid = dt_update_itlb_asid; - end - end - tlb #( - .NUM_ENTRIES(64), - .NUM_WAYS(4) - ) itlb( - .lookup_en(cache_fetch_en), - .update_en(dt_update_itlb_en), - .update_present(dt_update_itlb_present), - .update_exe_writable(dt_update_itlb_executable), - .update_supervisor(dt_update_itlb_supervisor), - .update_global(dt_update_itlb_global), - .invalidate_en(dt_invalidate_tlb_en), - .invalidate_all_en(dt_invalidate_tlb_all_en), - .update_ppage_idx(dt_update_itlb_ppage_idx), - .lookup_ppage_idx(tlb_ppage_idx), - .lookup_hit(tlb_hit), - .lookup_exe_writable(tlb_executable), - .lookup_present(tlb_present), - .lookup_supervisor(tlb_supervisor), - .clk(clk), - .reset(reset), - .request_vpage_idx(request_vpage_idx), - .request_asid(request_asid) - ); - always @(*) begin - if (_sv2v_0) - ; - if (cr_mmu_en[ift_thread_idx]) begin - ift_tlb_hit = tlb_hit; - ift_tlb_present = tlb_present; - ift_tlb_executable = tlb_executable; - ift_tlb_supervisor = tlb_supervisor; - ppage_idx = tlb_ppage_idx; - end - else begin - ift_tlb_hit = 1; - ift_tlb_present = 1; - ift_tlb_executable = 1; - ift_tlb_supervisor = 0; - ppage_idx = last_selected_pc[31-:defines_PAGE_NUM_BITS]; - end - end - cache_lru #( - .NUM_WAYS(4), - .NUM_SETS(64) - ) cache_lru( - .fill_en(l2i_icache_lru_fill_en), - .fill_set(l2i_icache_lru_fill_set), - .fill_way(ift_fill_lru), - .access_en(cache_fetch_en), - .access_set(pc_to_fetch[11-:6]), - .update_en(ifd_update_lru_en), - .update_way(ifd_update_lru_way), - .clk(clk), - .reset(reset) - ); - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_miss_thread( - .one_hot(cache_miss_thread_oh), - .index(ifd_cache_miss_thread_idx) - ); - assign thread_sleep_mask_oh = cache_miss_thread_oh & {4 {ifd_cache_miss}}; - assign icache_wait_threads_nxt = (icache_wait_threads | thread_sleep_mask_oh) & ~l2i_icache_wake_bitmap; - always @(posedge clk or posedge reset) - if (reset) begin - icache_wait_threads <= 1'sb0; - ift_instruction_requested <= 1'sb0; - end - else begin - icache_wait_threads <= icache_wait_threads_nxt; - ift_instruction_requested <= (cache_fetch_en && !((ifd_cache_miss || ifd_near_miss) && (ifd_cache_miss_thread_idx == selected_thread_idx))) && !(wb_rollback_en && (wb_rollback_thread_idx == selected_thread_idx)); - end - always @(posedge clk) begin - last_selected_pc <= pc_to_fetch; - ift_thread_idx <= selected_thread_idx; - last_selected_thread_oh <= selected_thread_oh; - end - assign ift_pc_paddr = {ppage_idx, last_selected_pc[31 - defines_PAGE_NUM_BITS:0]}; - assign ift_pc_vaddr = last_selected_pc; - initial _sv2v_0 = 0; -endmodule -module instruction_decode_stage ( - clk, - reset, - ifd_instruction_valid, - ifd_instruction, - ifd_inst_injected, - ifd_pc, - ifd_thread_idx, - ifd_alignment_fault, - ifd_supervisor_fault, - ifd_page_fault, - ifd_executable_fault, - ifd_tlb_miss, - dd_load_sync_pending, - sq_store_sync_pending, - id_instruction, - id_instruction_valid, - id_thread_idx, - ior_pending, - cr_interrupt_en, - cr_interrupt_pending, - ocd_halt, - wb_rollback_en, - wb_rollback_thread_idx -); - reg _sv2v_0; - input clk; - input reset; - input ifd_instruction_valid; - input wire [31:0] ifd_instruction; - input ifd_inst_injected; - input wire [31:0] ifd_pc; - input wire [1:0] ifd_thread_idx; - input ifd_alignment_fault; - input ifd_supervisor_fault; - input ifd_page_fault; - input ifd_executable_fault; - input ifd_tlb_miss; - input wire [3:0] dd_load_sync_pending; - input wire [3:0] sq_store_sync_pending; - localparam defines_NUM_VECTOR_LANES = 16; - output reg [141:0] id_instruction; - output reg id_instruction_valid; - output reg [1:0] id_thread_idx; - input wire [3:0] ior_pending; - input wire [3:0] cr_interrupt_en; - input wire [3:0] cr_interrupt_pending; - input ocd_halt; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - localparam T = 1'b1; - localparam F = 1'b0; - reg [20:0] dlut_out; - reg [141:0] decoded_instr_nxt; - wire nop; - wire fmt_r; - wire fmt_i; - wire fmt_m; - wire getlane; - wire compare; - reg [5:0] alu_op; - wire [3:0] memory_access_type; - reg [4:0] scalar_sel2; - wire has_trap; - wire syscall; - wire breakpoint; - wire raise_interrupt; - wire [3:0] masked_interrupt_flags; - wire unary_arith; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - casez (ifd_instruction[31:25]) - 7'b110000z: dlut_out = {F, F, T, 8'h11, F, F, F, F, 4'h2, F, F}; - 7'b110001z: dlut_out = {F, T, T, 8'h11, T, F, F, T, 4'h2, F, F}; - 7'b110010z: dlut_out = {F, T, T, 8'h09, T, F, F, T, 4'h0, F, F}; - 7'b110100z: dlut_out = {F, T, T, 8'h08, T, T, F, T, 4'h6, F, F}; - 7'b110101z: dlut_out = {F, T, T, 8'h12, T, T, F, T, 4'h5, F, F}; - 7'b000zzzz: dlut_out = {F, F, T, 8'h50, F, F, F, F, 4'ha, F, F}; - 7'b001zzzz: dlut_out = {F, T, T, 8'h50, T, F, F, T, 4'ha, F, F}; - 7'b010zzzz: dlut_out = {F, F, T, 8'hf0, F, F, F, F, 4'ha, F, F}; - 7'b011zzzz: dlut_out = {F, T, T, 8'h32, T, F, F, T, 4'h9, F, F}; - 7'b1000000: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000001: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000010: dlut_out = {F, F, F, 8'h93, T, F, T, F, 4'ha, F, F}; - 7'b1000011: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000100: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000101: dlut_out = {F, F, T, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000110: dlut_out = {F, F, F, 8'h93, F, F, T, F, 4'ha, F, F}; - 7'b1000111: dlut_out = {F, F, F, 8'h90, F, T, T, F, 4'ha, T, F}; - 7'b1001000: dlut_out = {F, F, F, 8'h72, F, T, T, F, 4'h9, T, F}; - 7'b1001101: dlut_out = {F, F, F, 8'h90, T, T, T, T, 4'ha, T, F}; - 7'b1001110: dlut_out = {F, F, F, 8'h72, T, T, T, T, 4'h9, T, F}; - 7'b1010000: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010001: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010010: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010011: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010100: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010101: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010110: dlut_out = {F, F, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1010111: dlut_out = {F, T, T, 8'h90, T, F, F, F, 4'ha, F, F}; - 7'b1011000: dlut_out = {F, T, T, 8'h72, T, F, F, F, 4'h9, F, F}; - 7'b1011101: dlut_out = {F, T, T, 8'h90, T, T, F, T, 4'ha, F, F}; - 7'b1011110: dlut_out = {F, T, T, 8'h72, T, T, F, T, 4'h9, F, F}; - 7'b1110000: dlut_out = {F, F, F, 8'h73, F, F, F, F, 4'ha, F, F}; - 7'b1110001: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110010: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110011: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110100: dlut_out = {F, F, F, 8'h60, F, F, F, F, 4'ha, F, F}; - 7'b1110101: dlut_out = {F, F, F, 8'h70, F, F, F, F, 4'ha, F, F}; - 7'b1110110: dlut_out = {F, F, F, 8'h60, F, F, F, F, 4'ha, F, F}; - 7'b1110111: dlut_out = {F, F, F, 8'h73, F, F, F, F, 4'ha, F, F}; - 7'b1111000: dlut_out = {F, F, F, 8'hb0, F, F, F, F, 4'ha, F, F}; - 7'b1111001: dlut_out = {F, F, F, 8'hb0, F, F, F, F, 4'ha, F, F}; - 7'b1111010: dlut_out = {F, F, F, 8'hb0, F, F, F, F, 4'ha, F, F}; - 7'b1111011: dlut_out = {F, F, F, 8'hc0, F, F, F, F, 4'ha, F, F}; - 7'b1111100: dlut_out = {F, F, T, 8'hc0, F, F, F, F, 4'h2, F, T}; - 7'b1111110: dlut_out = {F, F, T, 8'hb0, F, F, F, F, 4'h2, F, T}; - 7'b1111111: dlut_out = {F, F, T, 8'hb0, F, F, F, F, 4'h2, F, F}; - default: dlut_out = {T, F, F, 8'h00, F, F, F, F, 4'ha, F, F}; - endcase - end - assign fmt_r = ifd_instruction[31:29] == 3'b110; - assign fmt_i = ifd_instruction[31] == 1'b0; - assign fmt_m = ifd_instruction[31:30] == 2'b10; - assign getlane = (fmt_r || fmt_i) && (alu_op == 6'b011010); - function automatic [5:0] sv2v_cast_6; - input reg [5:0] inp; - sv2v_cast_6 = inp; - endfunction - assign syscall = fmt_i && (sv2v_cast_6(ifd_instruction[28:24]) == 6'b000010); - assign breakpoint = fmt_r && (ifd_instruction[25:20] == 6'b111110); - localparam defines_INSTRUCTION_NOP = 32'd0; - assign nop = ifd_instruction == defines_INSTRUCTION_NOP; - assign has_trap = (((((ifd_instruction_valid && (((dlut_out[20] || syscall) || breakpoint) || raise_interrupt)) || ifd_alignment_fault) || ifd_tlb_miss) || ifd_supervisor_fault) || ifd_page_fault) || ifd_executable_fault; - always @(*) begin - if (_sv2v_0) - ; - if (raise_interrupt) - decoded_instr_nxt[107-:6] = 6'h03; - else if (ifd_tlb_miss) - decoded_instr_nxt[107-:6] = 6'h07; - else if (ifd_page_fault) - decoded_instr_nxt[107-:6] = 6'h06; - else if (ifd_supervisor_fault) - decoded_instr_nxt[107-:6] = 6'h09; - else if (ifd_alignment_fault) - decoded_instr_nxt[107-:6] = 6'h05; - else if (ifd_executable_fault) - decoded_instr_nxt[107-:6] = 6'h0a; - else if (dlut_out[20]) - decoded_instr_nxt[107-:6] = 6'h01; - else if (syscall) - decoded_instr_nxt[107-:6] = 6'h04; - else if (breakpoint) - decoded_instr_nxt[107-:6] = 6'h0b; - else - decoded_instr_nxt[107-:6] = 6'h00; - end - wire [1:1] sv2v_tmp_B134F; - assign sv2v_tmp_B134F = ifd_inst_injected; - always @(*) decoded_instr_nxt[109] = sv2v_tmp_B134F; - assign masked_interrupt_flags = (((cr_interrupt_pending & cr_interrupt_en) & ~ior_pending) & ~dd_load_sync_pending) & ~sq_store_sync_pending; - assign raise_interrupt = masked_interrupt_flags[ifd_thread_idx] && !ocd_halt; - wire [1:1] sv2v_tmp_C4036; - assign sv2v_tmp_C4036 = has_trap; - always @(*) decoded_instr_nxt[108] = sv2v_tmp_C4036; - assign unary_arith = (fmt_r && ((((((((alu_op == 6'b001100) || (alu_op == 6'b001110)) || (alu_op == 6'b001111)) || (alu_op == 6'b011011)) || (alu_op == 6'b011100)) || (alu_op == 6'b011101)) || (alu_op == 6'b011110)) || (alu_op == 6'b101010))) && (dlut_out[3-:2] != 2'd0); - wire [1:1] sv2v_tmp_B589F; - assign sv2v_tmp_B589F = (((dlut_out[14-:2] != 2'd0) && !nop) && !has_trap) && !unary_arith; - always @(*) decoded_instr_nxt[101] = sv2v_tmp_B589F; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dlut_out[14-:2]) - 2'd1: decoded_instr_nxt[100-:5] = ifd_instruction[14:10]; - default: decoded_instr_nxt[100-:5] = ifd_instruction[4:0]; - endcase - end - wire [1:1] sv2v_tmp_D8F29; - assign sv2v_tmp_D8F29 = ((dlut_out[12-:3] != 3'd0) && !nop) && !has_trap; - always @(*) decoded_instr_nxt[95] = sv2v_tmp_D8F29; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dlut_out[12-:3]) - 3'd2: scalar_sel2 = ifd_instruction[14:10]; - 3'd1: scalar_sel2 = ifd_instruction[19:15]; - 3'd3: scalar_sel2 = ifd_instruction[9:5]; - default: scalar_sel2 = 0; - endcase - end - wire [5:1] sv2v_tmp_1FBF8; - assign sv2v_tmp_1FBF8 = scalar_sel2; - always @(*) decoded_instr_nxt[94-:5] = sv2v_tmp_1FBF8; - wire [1:1] sv2v_tmp_A0273; - assign sv2v_tmp_A0273 = (dlut_out[9] && !nop) && !has_trap; - always @(*) decoded_instr_nxt[89] = sv2v_tmp_A0273; - wire [5:1] sv2v_tmp_1F848; - assign sv2v_tmp_1F848 = ifd_instruction[4:0]; - always @(*) decoded_instr_nxt[88-:5] = sv2v_tmp_1F848; - wire [1:1] sv2v_tmp_1AA29; - assign sv2v_tmp_1AA29 = (dlut_out[8] && !nop) && !has_trap; - always @(*) decoded_instr_nxt[83] = sv2v_tmp_1AA29; - always @(*) begin - if (_sv2v_0) - ; - if (dlut_out[7]) - decoded_instr_nxt[82-:5] = ifd_instruction[9:5]; - else - decoded_instr_nxt[82-:5] = ifd_instruction[19:15]; - end - wire [1:1] sv2v_tmp_EBF04; - assign sv2v_tmp_EBF04 = (dlut_out[18] && !nop) && !has_trap; - always @(*) decoded_instr_nxt[77] = sv2v_tmp_EBF04; - wire [1:1] sv2v_tmp_C4837; - assign sv2v_tmp_C4837 = (dlut_out[19] && !compare) && !getlane; - always @(*) decoded_instr_nxt[76] = sv2v_tmp_C4837; - localparam defines_REG_RA = 5'd31; - wire [5:1] sv2v_tmp_245AC; - assign sv2v_tmp_245AC = (dlut_out[0] ? defines_REG_RA : ifd_instruction[9:5]); - always @(*) decoded_instr_nxt[75-:5] = sv2v_tmp_245AC; - wire [1:1] sv2v_tmp_E98EC; - assign sv2v_tmp_E98EC = dlut_out[0]; - always @(*) decoded_instr_nxt[22] = sv2v_tmp_E98EC; - always @(*) begin - if (_sv2v_0) - ; - if (fmt_i) - alu_op = sv2v_cast_6({1'b0, ifd_instruction[28:24]}); - else if (dlut_out[0]) - alu_op = 6'b001111; - else - alu_op = ifd_instruction[25:20]; - end - wire [6:1] sv2v_tmp_78B01; - assign sv2v_tmp_78B01 = alu_op; - always @(*) decoded_instr_nxt[70-:6] = sv2v_tmp_78B01; - wire [2:1] sv2v_tmp_990C6; - assign sv2v_tmp_990C6 = dlut_out[3-:2]; - always @(*) decoded_instr_nxt[64-:2] = sv2v_tmp_990C6; - wire [1:1] sv2v_tmp_C2D78; - assign sv2v_tmp_C2D78 = dlut_out[1]; - always @(*) decoded_instr_nxt[59] = sv2v_tmp_C2D78; - always @(*) begin - if (_sv2v_0) - ; - if (dlut_out[6]) - decoded_instr_nxt[62] = 1'd0; - else - decoded_instr_nxt[62] = 1'd1; - end - wire [2:1] sv2v_tmp_EE17C; - assign sv2v_tmp_EE17C = dlut_out[5-:2]; - always @(*) decoded_instr_nxt[61-:2] = sv2v_tmp_EE17C; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dlut_out[17-:3]) - 3'd7: decoded_instr_nxt[58-:32] = {ifd_instruction[23:10], ifd_instruction[4:0], 13'd0}; - 3'd1: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[23:15])); - 3'd2: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[23:10])); - 3'd3: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[24:15])); - 3'd4: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed(ifd_instruction[24:10])); - 3'd5: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed({ifd_instruction[24:5], 2'b00})); - 3'd6: decoded_instr_nxt[58-:32] = sv2v_cast_32($signed({ifd_instruction[24:0], 2'b00})); - default: decoded_instr_nxt[58-:32] = 0; - endcase - end - wire [3:1] sv2v_tmp_1A26C; - assign sv2v_tmp_1A26C = ifd_instruction[27:25]; - always @(*) decoded_instr_nxt[25-:3] = sv2v_tmp_1A26C; - wire [1:1] sv2v_tmp_86CFB; - assign sv2v_tmp_86CFB = (ifd_instruction[31:28] == 4'b1111) && !has_trap; - always @(*) decoded_instr_nxt[26] = sv2v_tmp_86CFB; - wire [32:1] sv2v_tmp_B397D; - assign sv2v_tmp_B397D = ifd_pc; - always @(*) decoded_instr_nxt[141-:32] = sv2v_tmp_B397D; - always @(*) begin - if (_sv2v_0) - ; - if (has_trap) - decoded_instr_nxt[21-:2] = 2'd1; - else if (fmt_r || fmt_i) begin - if ((((alu_op[5] || (alu_op == 6'b000111)) || (alu_op == 6'b001000)) || (alu_op == 6'b011111)) || (alu_op == 6'b011011)) - decoded_instr_nxt[21-:2] = 2'd2; - else - decoded_instr_nxt[21-:2] = 2'd1; - end - else if (ifd_instruction[31:28] == 4'b1111) - decoded_instr_nxt[21-:2] = 2'd1; - else - decoded_instr_nxt[21-:2] = 2'd0; - end - assign memory_access_type = ifd_instruction[28:25]; - wire [4:1] sv2v_tmp_D35EA; - assign sv2v_tmp_D35EA = memory_access_type; - always @(*) decoded_instr_nxt[18-:4] = sv2v_tmp_D35EA; - wire [1:1] sv2v_tmp_D0F69; - assign sv2v_tmp_D0F69 = (ifd_instruction[31:30] == 2'b10) && !has_trap; - always @(*) decoded_instr_nxt[19] = sv2v_tmp_D0F69; - wire [1:1] sv2v_tmp_0C594; - assign sv2v_tmp_0C594 = ifd_instruction[29] && fmt_m; - always @(*) decoded_instr_nxt[14] = sv2v_tmp_0C594; - wire [1:1] sv2v_tmp_0363D; - assign sv2v_tmp_0363D = (ifd_instruction[31:28] == 4'b1110) && !has_trap; - always @(*) decoded_instr_nxt[3] = sv2v_tmp_0363D; - wire [3:1] sv2v_tmp_8C9C3; - assign sv2v_tmp_8C9C3 = ifd_instruction[27:25]; - always @(*) decoded_instr_nxt[2-:3] = sv2v_tmp_8C9C3; - function automatic [3:0] sv2v_cast_60D1B; - input reg [3:0] inp; - sv2v_cast_60D1B = inp; - endfunction - always @(*) begin - if (_sv2v_0) - ; - if ((ifd_instruction[31:30] == 2'b10) && ((memory_access_type == 4'b1101) || (memory_access_type == 4'b1110))) - decoded_instr_nxt[12-:4] = sv2v_cast_60D1B(15); - else - decoded_instr_nxt[12-:4] = 0; - end - wire [5:1] sv2v_tmp_E1483; - assign sv2v_tmp_E1483 = ifd_instruction[4:0]; - always @(*) decoded_instr_nxt[8-:5] = sv2v_tmp_E1483; - assign compare = (fmt_r || fmt_i) && ((((((((((((((((alu_op == 6'b010000) || (alu_op == 6'b010001)) || (alu_op == 6'b010010)) || (alu_op == 6'b010011)) || (alu_op == 6'b010100)) || (alu_op == 6'b010101)) || (alu_op == 6'b010110)) || (alu_op == 6'b010111)) || (alu_op == 6'b011000)) || (alu_op == 6'b011001)) || (alu_op == 6'b101100)) || (alu_op == 6'b101110)) || (alu_op == 6'b101101)) || (alu_op == 6'b101111)) || (alu_op == 6'b110000)) || (alu_op == 6'b110001)); - wire [1:1] sv2v_tmp_DE7AB; - assign sv2v_tmp_DE7AB = compare; - always @(*) decoded_instr_nxt[13] = sv2v_tmp_DE7AB; - always @(posedge clk) begin - id_instruction <= decoded_instr_nxt; - id_thread_idx <= ifd_thread_idx; - end - always @(posedge clk or posedge reset) - if (reset) - id_instruction_valid <= 1'sb0; - else - id_instruction_valid <= (ifd_instruction_valid || has_trap) && (!wb_rollback_en || (wb_rollback_thread_idx != ifd_thread_idx)); - initial _sv2v_0 = 0; -endmodule -module int_execute_stage ( - clk, - reset, - of_operand1, - of_operand2, - of_mask_value, - of_instruction_valid, - of_instruction, - of_thread_idx, - of_subcycle, - wb_rollback_en, - wb_rollback_thread_idx, - ix_instruction_valid, - ix_instruction, - ix_result, - ix_mask_value, - ix_thread_idx, - ix_rollback_en, - ix_rollback_pc, - ix_subcycle, - ix_privileged_op_fault, - cr_eret_address, - cr_supervisor_en, - ix_perf_uncond_branch, - ix_perf_cond_branch_taken, - ix_perf_cond_branch_not_taken -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [511:0] of_operand1; - input wire [511:0] of_operand2; - input wire [15:0] of_mask_value; - input of_instruction_valid; - input wire [141:0] of_instruction; - input wire [1:0] of_thread_idx; - input wire [3:0] of_subcycle; - input wire wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - output reg ix_instruction_valid; - output reg [141:0] ix_instruction; - output reg [511:0] ix_result; - output reg [15:0] ix_mask_value; - output reg [1:0] ix_thread_idx; - output reg ix_rollback_en; - output reg [31:0] ix_rollback_pc; - output reg [3:0] ix_subcycle; - output reg ix_privileged_op_fault; - input wire [127:0] cr_eret_address; - input [0:3] cr_supervisor_en; - output reg ix_perf_uncond_branch; - output reg ix_perf_cond_branch_taken; - output reg ix_perf_cond_branch_not_taken; - wire [511:0] vector_result; - wire eret; - wire privileged_op_fault; - reg branch_taken; - reg conditional_branch; - wire valid_instruction; - genvar _gv_lane_1; - localparam defines_FLOAT32_EXP_WIDTH = 8; - localparam defines_FLOAT32_SIG_WIDTH = 23; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - function automatic [7:0] sv2v_cast_8; - input reg [7:0] inp; - sv2v_cast_8 = inp; - endfunction - generate - for (_gv_lane_1 = 0; _gv_lane_1 < defines_NUM_VECTOR_LANES; _gv_lane_1 = _gv_lane_1 + 1) begin : lane_alu_gen - localparam lane = _gv_lane_1; - wire [31:0] lane_operand1; - wire [31:0] lane_operand2; - reg [31:0] lane_result; - wire [31:0] difference; - wire borrow; - wire negative; - wire overflow; - wire zero; - wire signed_gtr; - wire [5:0] lz; - wire [5:0] tz; - reg [31:0] reciprocal; - wire [31:0] fp_operand; - wire [5:0] reciprocal_estimate; - wire shift_in_sign; - wire [31:0] rshift; - assign lane_operand1 = of_operand1[lane * 32+:32]; - assign lane_operand2 = of_operand2[lane * 32+:32]; - assign {borrow, difference} = {1'b0, lane_operand1} - {1'b0, lane_operand2}; - assign negative = difference[31]; - assign overflow = (lane_operand2[31] == negative) && (lane_operand1[31] != lane_operand2[31]); - assign zero = difference == 0; - assign signed_gtr = overflow == negative; - function automatic [5:0] count_lz; - input [31:0] val; - integer i; - reg found; - begin - count_lz = 32; - found = 0; - for (i = 31; i >= 0; i = i - 1) - if (!found && val[i]) begin - count_lz = 31 - i; - found = 1; - end - end - endfunction - function automatic [5:0] count_tz; - input [31:0] val; - integer i; - reg found; - begin - count_tz = 32; - found = 0; - for (i = 0; i < 32; i = i + 1) - if (!found && val[i]) begin - count_tz = i; - found = 1; - end - end - endfunction - assign lz = count_lz(lane_operand2); - assign tz = count_tz(lane_operand2); - assign shift_in_sign = (of_instruction[70-:6] == 6'b001001 ? lane_operand1[31] : 1'd0); - assign rshift = sv2v_cast_32({{32 {shift_in_sign}}, lane_operand1} >> lane_operand2[4:0]); - assign fp_operand = lane_operand2; - reciprocal_rom rom( - .significand(fp_operand[22:17]), - .reciprocal_estimate(reciprocal_estimate) - ); - always @(*) begin - if (_sv2v_0) - ; - if (fp_operand[30-:8] == 0) - reciprocal = {fp_operand[31], 31'h7f800000}; - else if (fp_operand[30-:8] == 8'hff) begin - if (fp_operand[22-:defines_FLOAT32_SIG_WIDTH] != 0) - reciprocal = 32'h7fffffff; - else - reciprocal = {fp_operand[31], 31'h00000000}; - end - else - reciprocal = {fp_operand[31], (8'd253 - fp_operand[30-:8]) + sv2v_cast_8(fp_operand[22:17] == 0), reciprocal_estimate, {17 {1'b0}}}; - end - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (of_instruction[70-:6]) - 6'b001001, 6'b001010: lane_result = rshift; - 6'b001011: lane_result = lane_operand1 << lane_operand2[4:0]; - 6'b001111: lane_result = lane_operand2; - 6'b000000: lane_result = lane_operand1 | lane_operand2; - 6'b001100: lane_result = sv2v_cast_32(lz); - 6'b001110: lane_result = sv2v_cast_32(tz); - 6'b000001: lane_result = lane_operand1 & lane_operand2; - 6'b000011: lane_result = lane_operand1 ^ lane_operand2; - 6'b000101: lane_result = lane_operand1 + lane_operand2; - 6'b000110: lane_result = difference; - 6'b010000: lane_result = {{31 {1'b0}}, zero}; - 6'b010001: lane_result = {{31 {1'b0}}, !zero}; - 6'b010010: lane_result = {{31 {1'b0}}, signed_gtr && !zero}; - 6'b010011: lane_result = {{31 {1'b0}}, signed_gtr || zero}; - 6'b010100: lane_result = {{31 {1'b0}}, !signed_gtr && !zero}; - 6'b010101: lane_result = {{31 {1'b0}}, !signed_gtr || zero}; - 6'b010110: lane_result = {{31 {1'b0}}, !borrow && !zero}; - 6'b010111: lane_result = {{31 {1'b0}}, !borrow || zero}; - 6'b011000: lane_result = {{31 {1'b0}}, borrow && !zero}; - 6'b011001: lane_result = {{31 {1'b0}}, borrow || zero}; - 6'b011101: lane_result = sv2v_cast_32($signed(lane_operand2[7:0])); - 6'b011110: lane_result = sv2v_cast_32($signed(lane_operand2[15:0])); - 6'b001101, 6'b011010: lane_result = of_operand1[~lane_operand2 * 32+:32]; - 6'b011100: lane_result = reciprocal; - default: lane_result = 0; - endcase - end - assign vector_result[lane * 32+:32] = lane_result; - end - endgenerate - assign valid_instruction = (of_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != of_thread_idx))) && (of_instruction[21-:2] == 2'd1); - assign eret = (valid_instruction && of_instruction[26]) && (of_instruction[25-:3] == 3'b111); - assign privileged_op_fault = eret && !cr_supervisor_en[of_thread_idx]; - always @(*) begin - if (_sv2v_0) - ; - branch_taken = 0; - conditional_branch = 0; - if ((valid_instruction && of_instruction[26]) && !privileged_op_fault) - (* full_case, parallel_case *) - case (of_instruction[25-:3]) - 3'b001: begin - branch_taken = of_operand1[0+:32] == 0; - conditional_branch = 1; - end - 3'b010: begin - branch_taken = of_operand1[0+:32] != 0; - conditional_branch = 1; - end - 3'b011, 3'b100, 3'b110, 3'b000, 3'b111: branch_taken = 1; - default: - ; - endcase - end - always @(posedge clk) begin - ix_instruction <= of_instruction; - ix_result <= vector_result; - ix_mask_value <= of_mask_value; - ix_thread_idx <= of_thread_idx; - ix_subcycle <= of_subcycle; - (* full_case, parallel_case *) - case (of_instruction[25-:3]) - 3'b110, 3'b000: ix_rollback_pc <= of_operand1[0+:32]; - 3'b111: ix_rollback_pc <= cr_eret_address[(3 - of_thread_idx) * 32+:32]; - default: ix_rollback_pc <= of_instruction[141-:32] + of_instruction[58-:32]; - endcase - end - always @(posedge clk or posedge reset) - if (reset) begin - ix_instruction_valid <= 1'sb0; - ix_perf_cond_branch_not_taken <= 1'sb0; - ix_perf_cond_branch_taken <= 1'sb0; - ix_perf_uncond_branch <= 1'sb0; - ix_privileged_op_fault <= 1'sb0; - ix_rollback_en <= 1'sb0; - end - else begin - if (valid_instruction) begin - ix_instruction_valid <= 1; - ix_privileged_op_fault <= privileged_op_fault; - ix_rollback_en <= branch_taken; - end - else begin - ix_instruction_valid <= 0; - ix_rollback_en <= 0; - end - ix_perf_uncond_branch <= !conditional_branch && branch_taken; - ix_perf_cond_branch_taken <= conditional_branch && branch_taken; - ix_perf_cond_branch_not_taken <= conditional_branch && !branch_taken; - end - initial _sv2v_0 = 0; -endmodule -module io_request_queue ( - clk, - reset, - dd_io_write_en, - dd_io_read_en, - dd_io_thread_idx, - dd_io_addr, - dd_io_write_value, - ior_read_value, - ior_rollback_en, - ior_pending, - ior_wake_bitmap, - ii_ready, - ii_response_valid, - ii_response, - ior_request_valid, - ior_request -); - parameter CORE_ID = 0; - input clk; - input reset; - input dd_io_write_en; - input dd_io_read_en; - input wire [1:0] dd_io_thread_idx; - input wire [31:0] dd_io_addr; - input wire [31:0] dd_io_write_value; - output reg [31:0] ior_read_value; - output reg ior_rollback_en; - output wire [3:0] ior_pending; - output wire [3:0] ior_wake_bitmap; - input ii_ready; - input ii_response_valid; - input wire [37:0] ii_response; - output wire ior_request_valid; - output wire [66:0] ior_request; - reg [66:0] pending_request [0:3]; - wire [3:0] wake_thread_oh; - wire [3:0] send_request; - wire [3:0] send_grant_oh; - wire [1:0] send_grant_idx; - genvar _gv_thread_idx_4; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_4 = 0; _gv_thread_idx_4 < 4; _gv_thread_idx_4 = _gv_thread_idx_4 + 1) begin : io_request_gen - localparam thread_idx = _gv_thread_idx_4; - assign send_request[thread_idx] = pending_request[thread_idx][66] && !pending_request[thread_idx][65]; - assign ior_pending[thread_idx] = (pending_request[thread_idx][66] && pending_request[thread_idx][65]) || send_grant_oh[thread_idx]; - always @(posedge clk or posedge reset) - if (reset) - pending_request[thread_idx] <= 0; - else begin - if ((dd_io_write_en | dd_io_read_en) && (dd_io_thread_idx == sv2v_cast_2(thread_idx))) begin - if (pending_request[thread_idx][66]) - pending_request[thread_idx][66] <= 0; - else begin - pending_request[thread_idx][66] <= 1; - pending_request[thread_idx][64] <= dd_io_write_en; - pending_request[thread_idx][63-:32] <= dd_io_addr; - pending_request[thread_idx][31-:32] <= dd_io_write_value; - pending_request[thread_idx][65] <= 0; - end - end - if ((ii_response_valid && (ii_response[37-:4] == CORE_ID)) && (ii_response[33-:2] == sv2v_cast_2(thread_idx))) - pending_request[thread_idx][31-:32] <= ii_response[31-:32]; - if ((ii_ready && |send_grant_oh) && (send_grant_idx == sv2v_cast_2(thread_idx))) - pending_request[thread_idx][65] <= 1; - end - end - endgenerate - rr_arbiter #(.NUM_REQUESTERS(4)) request_arbiter( - .request(send_request), - .update_lru(1'b1), - .grant_oh(send_grant_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_send_thread( - .one_hot(send_grant_oh), - .index(send_grant_idx) - ); - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_wake_thread( - .index(ii_response[33-:2]), - .one_hot(wake_thread_oh) - ); - assign ior_wake_bitmap = (ii_response_valid && (ii_response[37-:4] == CORE_ID) ? wake_thread_oh : 4'd0); - assign ior_request_valid = |send_request; - assign ior_request[66] = pending_request[send_grant_idx][64]; - assign ior_request[63-:32] = pending_request[send_grant_idx][63-:32]; - assign ior_request[31-:32] = pending_request[send_grant_idx][31-:32]; - assign ior_request[65-:2] = send_grant_idx; - always @(posedge clk or posedge reset) - if (reset) - ior_rollback_en <= 1'sb0; - else if ((dd_io_write_en || dd_io_read_en) && !pending_request[dd_io_thread_idx][66]) - ior_rollback_en <= 1; - else - ior_rollback_en <= 0; - always @(posedge clk) ior_read_value <= pending_request[dd_io_thread_idx][31-:32]; -endmodule -module l1_l2_interface ( - clk, - reset, - l2_ready, - l2_response_valid, - l2_response, - l2i_request_valid, - l2i_request, - l2i_icache_lru_fill_en, - l2i_icache_lru_fill_set, - l2i_itag_update_en, - l2i_itag_update_set, - l2i_itag_update_tag, - l2i_itag_update_valid, - sq_store_sync_pending, - ift_fill_lru, - ifd_cache_miss, - ifd_cache_miss_paddr, - ifd_cache_miss_thread_idx, - l2i_idata_update_en, - l2i_idata_update_way, - l2i_idata_update_set, - l2i_idata_update_data, - l2i_dcache_wake_bitmap, - l2i_icache_wake_bitmap, - dt_snoop_valid, - dt_snoop_tag, - dt_fill_lru, - l2i_snoop_en, - l2i_snoop_set, - l2i_dtag_update_en_oh, - l2i_dtag_update_set, - l2i_dtag_update_tag, - l2i_dtag_update_valid, - l2i_dcache_lru_fill_en, - l2i_dcache_lru_fill_set, - dd_cache_miss, - dd_cache_miss_addr, - dd_cache_miss_thread_idx, - dd_cache_miss_sync, - dd_store_en, - dd_flush_en, - dd_membar_en, - dd_iinvalidate_en, - dd_dinvalidate_en, - dd_store_mask, - dd_store_addr, - dd_store_data, - dd_store_thread_idx, - dd_store_sync, - dd_store_bypass_addr, - dd_store_bypass_thread_idx, - l2i_ddata_update_en, - l2i_ddata_update_way, - l2i_ddata_update_set, - l2i_ddata_update_data, - sq_store_bypass_mask, - sq_store_sync_success, - sq_store_bypass_data, - sq_rollback_en, - l2i_perf_store -); - reg _sv2v_0; - parameter CORE_ID = 0; - input clk; - input reset; - input l2_ready; - input l2_response_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [548:0] l2_response; - output reg l2i_request_valid; - output reg [611:0] l2i_request; - output wire l2i_icache_lru_fill_en; - output wire [5:0] l2i_icache_lru_fill_set; - output wire [3:0] l2i_itag_update_en; - output wire [5:0] l2i_itag_update_set; - localparam defines_ICACHE_TAG_BITS = 20; - output wire [19:0] l2i_itag_update_tag; - output wire l2i_itag_update_valid; - output wire [3:0] sq_store_sync_pending; - input wire [1:0] ift_fill_lru; - input wire ifd_cache_miss; - input wire [25:0] ifd_cache_miss_paddr; - input wire [1:0] ifd_cache_miss_thread_idx; - output reg l2i_idata_update_en; - output reg [1:0] l2i_idata_update_way; - output reg [5:0] l2i_idata_update_set; - output reg [511:0] l2i_idata_update_data; - output wire [3:0] l2i_dcache_wake_bitmap; - output wire [3:0] l2i_icache_wake_bitmap; - input wire [0:3] dt_snoop_valid; - localparam defines_DCACHE_TAG_BITS = 20; - input wire [79:0] dt_snoop_tag; - input wire [1:0] dt_fill_lru; - output wire l2i_snoop_en; - output wire [5:0] l2i_snoop_set; - output wire [3:0] l2i_dtag_update_en_oh; - output wire [5:0] l2i_dtag_update_set; - output wire [19:0] l2i_dtag_update_tag; - output wire l2i_dtag_update_valid; - output wire l2i_dcache_lru_fill_en; - output wire [5:0] l2i_dcache_lru_fill_set; - input dd_cache_miss; - input wire [25:0] dd_cache_miss_addr; - input wire [1:0] dd_cache_miss_thread_idx; - input dd_cache_miss_sync; - input dd_store_en; - input dd_flush_en; - input dd_membar_en; - input dd_iinvalidate_en; - input dd_dinvalidate_en; - input [63:0] dd_store_mask; - input wire [25:0] dd_store_addr; - input wire [511:0] dd_store_data; - input wire [1:0] dd_store_thread_idx; - input dd_store_sync; - input wire [25:0] dd_store_bypass_addr; - input wire [1:0] dd_store_bypass_thread_idx; - output reg l2i_ddata_update_en; - output reg [1:0] l2i_ddata_update_way; - output reg [5:0] l2i_ddata_update_set; - output reg [511:0] l2i_ddata_update_data; - output wire [63:0] sq_store_bypass_mask; - output wire sq_store_sync_success; - output wire [511:0] sq_store_bypass_data; - output wire sq_rollback_en; - output reg l2i_perf_store; - wire [3:0] snoop_hit_way_oh; - wire [1:0] snoop_hit_way_idx; - wire [3:0] ifill_way_oh; - wire [3:0] dupdate_way_oh; - reg [1:0] dupdate_way_idx; - wire ack_for_me; - wire icache_update_en; - wire dcache_update_en; - wire dcache_l2_response_valid; - wire [1:0] dcache_l2_response_idx; - wire icache_l2_response_valid; - wire [1:0] icache_l2_response_idx; - wire storebuf_l2_response_valid; - wire [1:0] storebuf_l2_response_idx; - wire [3:0] dcache_miss_wake_bitmap; - reg storebuf_dequeue_ack; - wire icache_dequeue_ready; - reg icache_dequeue_ack; - wire dcache_dequeue_ready; - reg dcache_dequeue_ack; - wire [25:0] dcache_dequeue_addr; - wire dcache_dequeue_sync; - wire [25:0] icache_dequeue_addr; - wire [1:0] dcache_dequeue_idx; - wire [1:0] icache_dequeue_idx; - reg response_stage2_valid; - reg [548:0] response_stage2; - wire [5:0] dcache_set_stage1; - wire [5:0] icache_set_stage1; - wire [5:0] dcache_set_stage2; - wire [5:0] icache_set_stage2; - wire [19:0] dcache_tag_stage2; - wire [19:0] icache_tag_stage2; - wire storebuf_l2_sync_success; - wire response_iinvalidate; - wire response_dinvalidate; - wire [25:0] sq_dequeue_addr; - wire [511:0] sq_dequeue_data; - wire sq_dequeue_dinvalidate; - wire sq_dequeue_flush; - wire [1:0] sq_dequeue_idx; - wire sq_dequeue_iinvalidate; - wire [63:0] sq_dequeue_mask; - wire sq_dequeue_ready; - wire sq_dequeue_sync; - wire [3:0] sq_wake_bitmap; - l1_store_queue l1_store_queue( - .clk(clk), - .reset(reset), - .sq_store_sync_pending(sq_store_sync_pending), - .dd_store_en(dd_store_en), - .dd_flush_en(dd_flush_en), - .dd_membar_en(dd_membar_en), - .dd_iinvalidate_en(dd_iinvalidate_en), - .dd_dinvalidate_en(dd_dinvalidate_en), - .dd_store_addr(dd_store_addr), - .dd_store_mask(dd_store_mask), - .dd_store_data(dd_store_data), - .dd_store_sync(dd_store_sync), - .dd_store_thread_idx(dd_store_thread_idx), - .dd_store_bypass_addr(dd_store_bypass_addr), - .dd_store_bypass_thread_idx(dd_store_bypass_thread_idx), - .sq_store_bypass_mask(sq_store_bypass_mask), - .sq_store_bypass_data(sq_store_bypass_data), - .sq_store_sync_success(sq_store_sync_success), - .storebuf_dequeue_ack(storebuf_dequeue_ack), - .storebuf_l2_response_valid(storebuf_l2_response_valid), - .storebuf_l2_response_idx(storebuf_l2_response_idx), - .storebuf_l2_sync_success(storebuf_l2_sync_success), - .sq_dequeue_ready(sq_dequeue_ready), - .sq_dequeue_addr(sq_dequeue_addr), - .sq_dequeue_idx(sq_dequeue_idx), - .sq_dequeue_mask(sq_dequeue_mask), - .sq_dequeue_data(sq_dequeue_data), - .sq_dequeue_sync(sq_dequeue_sync), - .sq_dequeue_flush(sq_dequeue_flush), - .sq_dequeue_iinvalidate(sq_dequeue_iinvalidate), - .sq_dequeue_dinvalidate(sq_dequeue_dinvalidate), - .sq_rollback_en(sq_rollback_en), - .sq_wake_bitmap(sq_wake_bitmap) - ); - l1_load_miss_queue l1_load_miss_queue_dcache( - .cache_miss(dd_cache_miss), - .cache_miss_addr(dd_cache_miss_addr), - .cache_miss_thread_idx(dd_cache_miss_thread_idx), - .cache_miss_sync(dd_cache_miss_sync), - .dequeue_ready(dcache_dequeue_ready), - .dequeue_ack(dcache_dequeue_ack), - .dequeue_addr(dcache_dequeue_addr), - .dequeue_idx(dcache_dequeue_idx), - .dequeue_sync(dcache_dequeue_sync), - .l2_response_valid(dcache_l2_response_valid), - .l2_response_idx(dcache_l2_response_idx), - .wake_bitmap(dcache_miss_wake_bitmap), - .clk(clk), - .reset(reset) - ); - assign l2i_dcache_wake_bitmap = dcache_miss_wake_bitmap | sq_wake_bitmap; - localparam [0:0] sv2v_uu_l1_load_miss_queue_icache_ext_cache_miss_sync_0 = 1'sb0; - l1_load_miss_queue l1_load_miss_queue_icache( - .cache_miss(ifd_cache_miss), - .cache_miss_addr(ifd_cache_miss_paddr), - .cache_miss_thread_idx(ifd_cache_miss_thread_idx), - .cache_miss_sync(sv2v_uu_l1_load_miss_queue_icache_ext_cache_miss_sync_0), - .dequeue_ready(icache_dequeue_ready), - .dequeue_ack(icache_dequeue_ack), - .dequeue_addr(icache_dequeue_addr), - .dequeue_idx(icache_dequeue_idx), - .dequeue_sync(), - .l2_response_valid(icache_l2_response_valid), - .l2_response_idx(icache_l2_response_idx), - .wake_bitmap(l2i_icache_wake_bitmap), - .clk(clk), - .reset(reset) - ); - assign dcache_set_stage1 = l2_response[517:512]; - assign icache_set_stage1 = l2_response[517:512]; - assign l2i_snoop_en = l2_response_valid && (l2_response[538] == 1'd1); - assign l2i_snoop_set = dcache_set_stage1; - assign l2i_dcache_lru_fill_en = ((l2_response_valid && (l2_response[538] == 1'd1)) && (l2_response[541-:3] == 3'd0)) && (l2_response[547-:4] == CORE_ID); - assign l2i_dcache_lru_fill_set = dcache_set_stage1; - assign l2i_icache_lru_fill_en = ((l2_response_valid && (l2_response[538] == 1'd0)) && (l2_response[541-:3] == 3'd0)) && (l2_response[547-:4] == CORE_ID); - assign l2i_icache_lru_fill_set = icache_set_stage1; - always @(posedge clk or posedge reset) - if (reset) - response_stage2_valid <= 0; - else - response_stage2_valid <= l2_response_valid; - always @(posedge clk) response_stage2 <= l2_response; - assign {icache_tag_stage2, icache_set_stage2} = response_stage2[537-:26]; - assign {dcache_tag_stage2, dcache_set_stage2} = response_stage2[537-:26]; - genvar _gv_way_idx_5; - generate - for (_gv_way_idx_5 = 0; _gv_way_idx_5 < 4; _gv_way_idx_5 = _gv_way_idx_5 + 1) begin : snoop_hit_check_gen - localparam way_idx = _gv_way_idx_5; - assign snoop_hit_way_oh[way_idx] = (dt_snoop_tag[(3 - way_idx) * defines_DCACHE_TAG_BITS+:defines_DCACHE_TAG_BITS] == dcache_tag_stage2) && dt_snoop_valid[way_idx]; - end - endgenerate - oh_to_idx #(.NUM_SIGNALS(4)) convert_snoop_request_pending( - .index(snoop_hit_way_idx), - .one_hot(snoop_hit_way_oh) - ); - always @(*) begin - if (_sv2v_0) - ; - if (|snoop_hit_way_oh) - dupdate_way_idx = snoop_hit_way_idx; - else - dupdate_way_idx = dt_fill_lru; - end - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_dfill_way( - .index(dupdate_way_idx), - .one_hot(dupdate_way_oh) - ); - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_ifill_way( - .index(ift_fill_lru), - .one_hot(ifill_way_oh) - ); - assign ack_for_me = response_stage2_valid && (response_stage2[547-:4] == CORE_ID); - assign response_dinvalidate = response_stage2[541-:3] == 3'd4; - assign dcache_update_en = (ack_for_me && (((response_stage2[541-:3] == 3'd0) && (response_stage2[538] == 1'd1)) || (response_stage2[541-:3] == 3'd1))) || ((response_stage2_valid && response_dinvalidate) && |snoop_hit_way_oh); - assign l2i_dtag_update_en_oh = dupdate_way_oh & {4 {dcache_update_en}}; - assign l2i_dtag_update_tag = dcache_tag_stage2; - assign l2i_dtag_update_set = dcache_set_stage2; - assign l2i_dtag_update_valid = !response_dinvalidate; - assign response_iinvalidate = response_stage2_valid && (response_stage2[541-:3] == 3'd3); - assign icache_update_en = (ack_for_me && (response_stage2[538] == 1'd0)) || response_iinvalidate; - assign l2i_itag_update_en = (response_iinvalidate ? {4 {1'b1}} : ifill_way_oh & {4 {icache_update_en}}); - assign l2i_itag_update_tag = icache_tag_stage2; - assign l2i_itag_update_set = icache_set_stage2; - assign l2i_itag_update_valid = !response_iinvalidate; - assign icache_l2_response_valid = ack_for_me && (response_stage2[538] == 1'd0); - assign dcache_l2_response_valid = (ack_for_me && (response_stage2[541-:3] == 3'd0)) && (response_stage2[538] == 1'd1); - assign storebuf_l2_response_valid = ack_for_me && ((((response_stage2[541-:3] == 3'd1) || (response_stage2[541-:3] == 3'd2)) || (response_stage2[541-:3] == 3'd3)) || (response_stage2[541-:3] == 3'd4)); - assign dcache_l2_response_idx = response_stage2[543-:2]; - assign icache_l2_response_idx = response_stage2[543-:2]; - assign storebuf_l2_response_idx = response_stage2[543-:2]; - assign storebuf_l2_sync_success = response_stage2[548]; - always @(posedge clk) begin - l2i_ddata_update_way <= dupdate_way_idx; - l2i_ddata_update_set <= dcache_set_stage2; - l2i_ddata_update_data <= response_stage2[511-:defines_CACHE_LINE_BITS]; - l2i_idata_update_way <= ift_fill_lru; - l2i_idata_update_set <= icache_set_stage2; - l2i_idata_update_data <= response_stage2[511-:defines_CACHE_LINE_BITS]; - end - always @(posedge clk or posedge reset) - if (reset) begin - l2i_ddata_update_en <= 1'sb0; - l2i_idata_update_en <= 1'sb0; - end - else begin - l2i_ddata_update_en <= dcache_update_en || ((|snoop_hit_way_oh && response_stage2_valid) && (response_stage2[541-:3] == 3'd1)); - l2i_idata_update_en <= icache_update_en; - end - always @(*) begin - if (_sv2v_0) - ; - l2i_request_valid = 0; - l2i_request = 0; - storebuf_dequeue_ack = 0; - icache_dequeue_ack = 0; - dcache_dequeue_ack = 0; - l2i_perf_store = 0; - l2i_request[611-:4] = CORE_ID; - if (dcache_dequeue_ready) begin - l2i_request_valid = 1; - l2i_request[605-:3] = (dcache_dequeue_sync ? 3'd1 : 3'd0); - l2i_request[607-:2] = dcache_dequeue_idx; - l2i_request[601-:26] = dcache_dequeue_addr; - l2i_request[602] = 1'd1; - if (l2_ready) - dcache_dequeue_ack = 1; - end - else if (icache_dequeue_ready) begin - l2i_request_valid = 1; - l2i_request[605-:3] = 3'd0; - l2i_request[607-:2] = icache_dequeue_idx; - l2i_request[601-:26] = icache_dequeue_addr; - l2i_request[602] = 1'd0; - if (l2_ready) - icache_dequeue_ack = 1; - end - else if (sq_dequeue_ready) begin - l2i_request_valid = 1; - if (sq_dequeue_flush) - l2i_request[605-:3] = 3'd4; - else if (sq_dequeue_sync) - l2i_request[605-:3] = 3'd3; - else if (sq_dequeue_iinvalidate) - l2i_request[605-:3] = 3'd5; - else if (sq_dequeue_dinvalidate) - l2i_request[605-:3] = 3'd6; - else - l2i_request[605-:3] = 3'd2; - l2i_request[607-:2] = sq_dequeue_idx; - l2i_request[601-:26] = sq_dequeue_addr; - l2i_request[511-:defines_CACHE_LINE_BITS] = sq_dequeue_data; - l2i_request[575-:64] = sq_dequeue_mask; - l2i_request[602] = 1'd1; - if (l2_ready) begin - storebuf_dequeue_ack = 1; - l2i_perf_store = l2i_request[605-:3] == 3'd2; - end - end - end - initial _sv2v_0 = 0; -endmodule -module l1_load_miss_queue ( - clk, - reset, - cache_miss, - cache_miss_addr, - cache_miss_thread_idx, - cache_miss_sync, - dequeue_ready, - dequeue_ack, - dequeue_addr, - dequeue_idx, - dequeue_sync, - l2_response_valid, - l2_response_idx, - wake_bitmap -); - input clk; - input reset; - input cache_miss; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [25:0] cache_miss_addr; - input wire [1:0] cache_miss_thread_idx; - input cache_miss_sync; - output wire dequeue_ready; - input dequeue_ack; - output wire [25:0] dequeue_addr; - output wire [1:0] dequeue_idx; - output wire dequeue_sync; - input l2_response_valid; - input wire [1:0] l2_response_idx; - output wire [3:0] wake_bitmap; - reg [32:0] pending_entries [0:3]; - wire [3:0] collided_miss_oh; - wire [3:0] miss_thread_oh; - wire request_unique; - wire [3:0] send_grant_oh; - wire [3:0] arbiter_request; - wire [1:0] send_grant_idx; - idx_to_oh #(.NUM_SIGNALS(4)) idx_to_oh_miss_thread( - .index(cache_miss_thread_idx), - .one_hot(miss_thread_oh) - ); - rr_arbiter #(.NUM_REQUESTERS(4)) request_arbiter( - .request(arbiter_request), - .update_lru(1'b1), - .grant_oh(send_grant_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_send_grant( - .index(send_grant_idx), - .one_hot(send_grant_oh) - ); - assign dequeue_ready = |arbiter_request; - assign dequeue_addr = pending_entries[send_grant_idx][26-:26]; - assign dequeue_idx = send_grant_idx; - assign dequeue_sync = pending_entries[send_grant_idx][0]; - assign request_unique = !(|collided_miss_oh); - assign wake_bitmap = (l2_response_valid ? pending_entries[l2_response_idx][30-:4] : 4'd0); - genvar _gv_wait_entry_1; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_wait_entry_1 = 0; _gv_wait_entry_1 < 4; _gv_wait_entry_1 = _gv_wait_entry_1 + 1) begin : wait_logic_gen - localparam wait_entry = _gv_wait_entry_1; - assign collided_miss_oh[wait_entry] = ((pending_entries[wait_entry][32] && (pending_entries[wait_entry][26-:26] == cache_miss_addr)) && !pending_entries[wait_entry][0]) && !cache_miss_sync; - assign arbiter_request[wait_entry] = pending_entries[wait_entry][32] && !pending_entries[wait_entry][31]; - always @(posedge clk or posedge reset) - if (reset) - pending_entries[wait_entry] <= 0; - else begin - if (dequeue_ack && send_grant_oh[wait_entry]) - pending_entries[wait_entry][31] <= 1; - else if ((cache_miss && miss_thread_oh[wait_entry]) && request_unique) begin - pending_entries[wait_entry][30-:4] <= miss_thread_oh; - pending_entries[wait_entry][32] <= 1; - pending_entries[wait_entry][26-:26] <= cache_miss_addr; - pending_entries[wait_entry][31] <= 0; - pending_entries[wait_entry][0] <= cache_miss_sync; - end - else if (l2_response_valid && (l2_response_idx == sv2v_cast_2(wait_entry))) - pending_entries[wait_entry][32] <= 0; - if (cache_miss && collided_miss_oh[wait_entry]) - pending_entries[wait_entry][30-:4] <= pending_entries[wait_entry][30-:4] | miss_thread_oh; - end - end - endgenerate -endmodule -module l1_store_queue ( - clk, - reset, - sq_store_sync_pending, - dd_store_en, - dd_flush_en, - dd_membar_en, - dd_iinvalidate_en, - dd_dinvalidate_en, - dd_store_addr, - dd_store_mask, - dd_store_data, - dd_store_sync, - dd_store_thread_idx, - dd_store_bypass_addr, - dd_store_bypass_thread_idx, - sq_store_bypass_mask, - sq_store_bypass_data, - sq_store_sync_success, - storebuf_dequeue_ack, - storebuf_l2_response_valid, - storebuf_l2_response_idx, - storebuf_l2_sync_success, - sq_dequeue_ready, - sq_dequeue_addr, - sq_dequeue_idx, - sq_dequeue_mask, - sq_dequeue_data, - sq_dequeue_sync, - sq_dequeue_flush, - sq_dequeue_iinvalidate, - sq_dequeue_dinvalidate, - sq_rollback_en, - sq_wake_bitmap -); - reg _sv2v_0; - input clk; - input reset; - output wire [3:0] sq_store_sync_pending; - input dd_store_en; - input dd_flush_en; - input dd_membar_en; - input dd_iinvalidate_en; - input dd_dinvalidate_en; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [25:0] dd_store_addr; - input [63:0] dd_store_mask; - localparam defines_CACHE_LINE_BITS = 512; - input wire [511:0] dd_store_data; - input dd_store_sync; - input wire [1:0] dd_store_thread_idx; - input wire [25:0] dd_store_bypass_addr; - input wire [1:0] dd_store_bypass_thread_idx; - output reg [63:0] sq_store_bypass_mask; - output reg [511:0] sq_store_bypass_data; - output reg sq_store_sync_success; - input storebuf_dequeue_ack; - input storebuf_l2_response_valid; - input wire [1:0] storebuf_l2_response_idx; - input storebuf_l2_sync_success; - output wire sq_dequeue_ready; - output wire [25:0] sq_dequeue_addr; - output wire [1:0] sq_dequeue_idx; - output wire [63:0] sq_dequeue_mask; - output wire [511:0] sq_dequeue_data; - output wire sq_dequeue_sync; - output wire sq_dequeue_flush; - output wire sq_dequeue_iinvalidate; - output wire sq_dequeue_dinvalidate; - output reg sq_rollback_en; - output wire [3:0] sq_wake_bitmap; - reg [610:0] pending_stores [0:3]; - reg [3:0] rollback; - wire [3:0] send_request; - wire [1:0] send_grant_idx; - wire [3:0] send_grant_oh; - rr_arbiter #(.NUM_REQUESTERS(4)) request_arbiter( - .request(send_request), - .update_lru(1'b1), - .grant_oh(send_grant_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) oh_to_idx_send_grant( - .index(send_grant_idx), - .one_hot(send_grant_oh) - ); - genvar _gv_thread_idx_5; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - generate - for (_gv_thread_idx_5 = 0; _gv_thread_idx_5 < 4; _gv_thread_idx_5 = _gv_thread_idx_5 + 1) begin : thread_store_buf_gen - localparam thread_idx = _gv_thread_idx_5; - wire update_store_entry; - wire can_write_combine; - wire store_requested_this_entry; - wire send_this_cycle; - wire restarted_sync_request; - wire got_response_this_entry; - wire membar_requested_this_entry; - wire enqueue_cache_control; - assign send_request[thread_idx] = pending_stores[thread_idx][602] && !pending_stores[thread_idx][606]; - assign store_requested_this_entry = dd_store_en && (dd_store_thread_idx == sv2v_cast_2(thread_idx)); - assign membar_requested_this_entry = dd_membar_en && (dd_store_thread_idx == sv2v_cast_2(thread_idx)); - assign send_this_cycle = send_grant_oh[thread_idx] && storebuf_dequeue_ack; - assign can_write_combine = (((((((((pending_stores[thread_idx][602] && (pending_stores[thread_idx][25-:26] == dd_store_addr)) && !pending_stores[thread_idx][609]) && !pending_stores[thread_idx][608]) && !pending_stores[thread_idx][607]) && !dd_store_sync) && !pending_stores[thread_idx][606]) && !send_this_cycle) && !dd_flush_en) && !dd_iinvalidate_en) && !dd_dinvalidate_en; - assign restarted_sync_request = (pending_stores[thread_idx][602] && pending_stores[thread_idx][605]) && pending_stores[thread_idx][610]; - assign update_store_entry = (store_requested_this_entry && ((!pending_stores[thread_idx][602] || can_write_combine) || got_response_this_entry)) && !restarted_sync_request; - assign got_response_this_entry = storebuf_l2_response_valid && (storebuf_l2_response_idx == sv2v_cast_2(thread_idx)); - assign sq_wake_bitmap[thread_idx] = got_response_this_entry && pending_stores[thread_idx][603]; - assign enqueue_cache_control = ((dd_store_thread_idx == sv2v_cast_2(thread_idx)) && (!pending_stores[thread_idx][602] || got_response_this_entry)) && ((dd_flush_en || dd_dinvalidate_en) || dd_iinvalidate_en); - assign sq_store_sync_pending[thread_idx] = pending_stores[thread_idx][602] && pending_stores[thread_idx][610]; - always @(*) begin - if (_sv2v_0) - ; - rollback[thread_idx] = 0; - if ((dd_store_thread_idx == sv2v_cast_2(thread_idx)) && (((dd_flush_en || dd_dinvalidate_en) || dd_iinvalidate_en) || dd_store_en)) begin - if (dd_store_sync) - rollback[thread_idx] = !restarted_sync_request; - else if ((pending_stores[thread_idx][602] && !can_write_combine) && !got_response_this_entry) - rollback[thread_idx] = 1; - end - else if ((membar_requested_this_entry && pending_stores[thread_idx][602]) && !got_response_this_entry) - rollback[thread_idx] = 1; - end - always @(posedge clk or posedge reset) - if (reset) - pending_stores[thread_idx] <= 0; - else begin - if (((((dd_store_en || dd_flush_en) || dd_membar_en) || dd_iinvalidate_en) || dd_dinvalidate_en) && (dd_store_thread_idx == thread_idx)) - ; - if (((dd_store_en && (dd_store_thread_idx == thread_idx)) && pending_stores[thread_idx][610]) && pending_stores[thread_idx][602]) - ; - if (send_this_cycle) - pending_stores[thread_idx][606] <= 1; - if (update_store_entry) begin - begin : sv2v_autoblock_1 - reg signed [31:0] byte_lane; - for (byte_lane = 0; byte_lane < defines_CACHE_LINE_BYTES; byte_lane = byte_lane + 1) - if (dd_store_mask[byte_lane]) - pending_stores[thread_idx][90 + (byte_lane * 8)+:8] <= dd_store_data[byte_lane * 8+:8]; - end - if (can_write_combine) - pending_stores[thread_idx][89-:64] <= pending_stores[thread_idx][89-:64] | dd_store_mask; - else - pending_stores[thread_idx][89-:64] <= dd_store_mask; - end - if (sq_wake_bitmap[thread_idx]) - pending_stores[thread_idx][603] <= 0; - else if (rollback[thread_idx]) - pending_stores[thread_idx][603] <= 1; - if (store_requested_this_entry) begin - if (restarted_sync_request) - pending_stores[thread_idx][602] <= 0; - else if (update_store_entry && !can_write_combine) begin - pending_stores[thread_idx][602] <= 1; - pending_stores[thread_idx][25-:26] <= dd_store_addr; - pending_stores[thread_idx][610] <= dd_store_sync; - pending_stores[thread_idx][609] <= 0; - pending_stores[thread_idx][608] <= 0; - pending_stores[thread_idx][607] <= 0; - pending_stores[thread_idx][606] <= 0; - pending_stores[thread_idx][605] <= 0; - end - end - else if (enqueue_cache_control) begin - pending_stores[thread_idx][602] <= 1; - pending_stores[thread_idx][25-:26] <= dd_store_addr; - pending_stores[thread_idx][610] <= 0; - pending_stores[thread_idx][609] <= dd_flush_en; - pending_stores[thread_idx][608] <= dd_iinvalidate_en; - pending_stores[thread_idx][607] <= dd_dinvalidate_en; - pending_stores[thread_idx][606] <= 0; - pending_stores[thread_idx][605] <= 0; - end - if ((got_response_this_entry && (!store_requested_this_entry || !update_store_entry)) && !enqueue_cache_control) begin - if (pending_stores[thread_idx][610]) begin - pending_stores[thread_idx][605] <= 1; - pending_stores[thread_idx][604] <= storebuf_l2_sync_success; - end - else - pending_stores[thread_idx][602] <= 0; - end - end - end - endgenerate - assign sq_dequeue_ready = |send_grant_oh; - assign sq_dequeue_idx = send_grant_idx; - assign sq_dequeue_addr = pending_stores[send_grant_idx][25-:26]; - assign sq_dequeue_mask = pending_stores[send_grant_idx][89-:64]; - assign sq_dequeue_data = pending_stores[send_grant_idx][601-:512]; - assign sq_dequeue_sync = pending_stores[send_grant_idx][610]; - assign sq_dequeue_flush = pending_stores[send_grant_idx][609]; - assign sq_dequeue_iinvalidate = pending_stores[send_grant_idx][608]; - assign sq_dequeue_dinvalidate = pending_stores[send_grant_idx][607]; - always @(posedge clk) begin - sq_store_bypass_data <= pending_stores[dd_store_bypass_thread_idx][601-:512]; - if (((((dd_store_bypass_addr == pending_stores[dd_store_bypass_thread_idx][25-:26]) && pending_stores[dd_store_bypass_thread_idx][602]) && !pending_stores[dd_store_bypass_thread_idx][609]) && !pending_stores[dd_store_bypass_thread_idx][608]) && !pending_stores[dd_store_bypass_thread_idx][607]) - sq_store_bypass_mask <= pending_stores[dd_store_bypass_thread_idx][89-:64]; - else - sq_store_bypass_mask <= 0; - sq_store_sync_success <= pending_stores[dd_store_thread_idx][604]; - end - always @(posedge clk or posedge reset) - if (reset) - sq_rollback_en <= 1'sb0; - else - sq_rollback_en <= |rollback; - initial _sv2v_0 = 0; -endmodule -module l2_cache_arb_stage ( - clk, - reset, - l2i_request_valid, - l2i_request, - l2_ready, - l2a_request_valid, - l2a_request, - l2a_data_from_memory, - l2a_l2_fill, - l2a_restarted_flush, - l2bi_request_valid, - l2bi_request, - l2bi_data_from_memory, - l2bi_stall, - l2bi_collided_miss -); - input clk; - input reset; - input [0:0] l2i_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2i_request; - output wire [0:0] l2_ready; - output reg l2a_request_valid; - output reg [611:0] l2a_request; - output reg [511:0] l2a_data_from_memory; - output reg l2a_l2_fill; - output reg l2a_restarted_flush; - input l2bi_request_valid; - input wire [611:0] l2bi_request; - input wire [511:0] l2bi_data_from_memory; - input l2bi_stall; - input l2bi_collided_miss; - wire can_accept_request; - wire [611:0] grant_request; - wire [0:0] grant_oh; - wire restarted_flush; - assign can_accept_request = !l2bi_request_valid && !l2bi_stall; - assign restarted_flush = l2bi_request[605-:3] == 3'd4; - genvar _gv_request_idx_2; - generate - for (_gv_request_idx_2 = 0; _gv_request_idx_2 < 1; _gv_request_idx_2 = _gv_request_idx_2 + 1) begin : handshake_gen - localparam request_idx = _gv_request_idx_2; - assign l2_ready[request_idx] = grant_oh[request_idx] && can_accept_request; - end - endgenerate - localparam defines_CORE_ID_WIDTH = 0; - generate - if (1) begin : genblk2 - assign grant_oh[0] = l2i_request_valid[0]; - assign grant_request = l2i_request[0+:612]; - end - endgenerate - always @(posedge clk) begin - l2a_data_from_memory <= l2bi_data_from_memory; - if (l2bi_request_valid) begin - l2a_request <= l2bi_request; - l2a_l2_fill <= !l2bi_collided_miss && !restarted_flush; - l2a_restarted_flush <= restarted_flush; - end - else begin - l2a_request <= grant_request; - l2a_l2_fill <= 0; - l2a_restarted_flush <= 0; - end - end - always @(posedge clk or posedge reset) - if (reset) - l2a_request_valid <= 0; - else if (l2bi_request_valid) - l2a_request_valid <= 1; - else if (|l2i_request_valid && can_accept_request) - l2a_request_valid <= 1; - else - l2a_request_valid <= 0; -endmodule -module l2_cache_pending_miss_cam ( - clk, - reset, - request_valid, - request_addr, - enqueue_fill_request, - l2r_l2_fill, - duplicate_request -); - parameter QUEUE_SIZE = 16; - parameter QUEUE_ADDR_WIDTH = $clog2(QUEUE_SIZE); - input clk; - input reset; - input request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [25:0] request_addr; - input enqueue_fill_request; - input l2r_l2_fill; - output wire duplicate_request; - wire [QUEUE_ADDR_WIDTH - 1:0] cam_hit_entry; - wire cam_hit; - reg [QUEUE_SIZE - 1:0] empty_entries; - wire [QUEUE_SIZE - 1:0] next_empty_oh; - wire [QUEUE_ADDR_WIDTH - 1:0] next_empty; - function automatic signed [QUEUE_SIZE - 1:0] sv2v_cast_C61BA_signed; - input reg signed [QUEUE_SIZE - 1:0] inp; - sv2v_cast_C61BA_signed = inp; - endfunction - assign next_empty_oh = empty_entries & ~(empty_entries - sv2v_cast_C61BA_signed(1)); - oh_to_idx #(.NUM_SIGNALS(QUEUE_SIZE)) oh_to_idx_next_empty( - .one_hot(next_empty_oh), - .index(next_empty) - ); - assign duplicate_request = cam_hit && !l2r_l2_fill; - cam #( - .NUM_ENTRIES(QUEUE_SIZE), - .KEY_WIDTH(26) - ) cam_pending_miss( - .clk(clk), - .reset(reset), - .lookup_key(request_addr), - .lookup_idx(cam_hit_entry), - .lookup_hit(cam_hit), - .update_en(request_valid && (cam_hit ? l2r_l2_fill : enqueue_fill_request)), - .update_key(request_addr), - .update_idx((cam_hit ? cam_hit_entry : next_empty)), - .update_valid((cam_hit ? !l2r_l2_fill : enqueue_fill_request)) - ); - always @(posedge clk or posedge reset) - if (reset) - empty_entries <= {QUEUE_SIZE {1'b1}}; - else if (cam_hit & l2r_l2_fill) - empty_entries[cam_hit_entry] <= 1'b1; - else if (!cam_hit && enqueue_fill_request) - empty_entries[next_empty] <= 1'b0; -endmodule -module l2_cache_read_stage ( - clk, - reset, - l2t_request_valid, - l2t_request, - l2t_valid, - l2t_tag, - l2t_dirty, - l2t_l2_fill, - l2t_restarted_flush, - l2t_fill_way, - l2t_data_from_memory, - l2r_update_dirty_en, - l2r_update_dirty_set, - l2r_update_dirty_value, - l2r_update_tag_en, - l2r_update_tag_set, - l2r_update_tag_valid, - l2r_update_tag_value, - l2r_update_lru_en, - l2r_update_lru_hit_way, - l2u_write_en, - l2u_write_addr, - l2u_write_data, - l2r_request_valid, - l2r_request, - l2r_data, - l2r_cache_hit, - l2r_hit_cache_idx, - l2r_l2_fill, - l2r_restarted_flush, - l2r_data_from_memory, - l2r_store_sync_success, - l2r_writeback_tag, - l2r_needs_writeback, - l2r_perf_l2_miss, - l2r_perf_l2_hit -); - input clk; - input reset; - input l2t_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2t_request; - input [0:7] l2t_valid; - input wire [143:0] l2t_tag; - input [0:7] l2t_dirty; - input l2t_l2_fill; - input l2t_restarted_flush; - input wire [2:0] l2t_fill_way; - input wire [511:0] l2t_data_from_memory; - output wire [7:0] l2r_update_dirty_en; - output wire [7:0] l2r_update_dirty_set; - output wire l2r_update_dirty_value; - output wire [7:0] l2r_update_tag_en; - output wire [7:0] l2r_update_tag_set; - output wire l2r_update_tag_valid; - output wire [17:0] l2r_update_tag_value; - output wire l2r_update_lru_en; - output wire [2:0] l2r_update_lru_hit_way; - input l2u_write_en; - input [10:0] l2u_write_addr; - input wire [511:0] l2u_write_data; - output reg l2r_request_valid; - output reg [611:0] l2r_request; - output wire [511:0] l2r_data; - output reg l2r_cache_hit; - output reg [10:0] l2r_hit_cache_idx; - output reg l2r_l2_fill; - output reg l2r_restarted_flush; - output reg [511:0] l2r_data_from_memory; - output reg l2r_store_sync_success; - output reg [17:0] l2r_writeback_tag; - output reg l2r_needs_writeback; - output reg l2r_perf_l2_miss; - output reg l2r_perf_l2_hit; - localparam defines_TOTAL_THREADS = 4; - localparam GLOBAL_THREAD_IDX_WIDTH = 2; - reg [25:0] load_sync_address [0:3]; - reg load_sync_address_valid [0:3]; - wire can_store_sync; - wire [7:0] hit_way_oh; - wire cache_hit; - wire [2:0] hit_way_idx; - wire [10:0] read_address; - wire load; - wire store; - wire update_dirty; - wire update_tag; - wire flush_first_pass; - wire [2:0] writeback_way; - wire hit_or_miss; - wire dinvalidate; - wire [2:0] tag_update_way; - wire [1:0] request_sync_slot; - assign load = (l2t_request[605-:3] == 3'd0) || (l2t_request[605-:3] == 3'd1); - assign store = (l2t_request[605-:3] == 3'd2) || (l2t_request[605-:3] == 3'd3); - assign writeback_way = (l2t_request[605-:3] == 3'd4 ? hit_way_idx : l2t_fill_way); - assign dinvalidate = l2t_request[605-:3] == 3'd6; - genvar _gv_way_idx_6; - generate - for (_gv_way_idx_6 = 0; _gv_way_idx_6 < 8; _gv_way_idx_6 = _gv_way_idx_6 + 1) begin : hit_way_gen - localparam way_idx = _gv_way_idx_6; - assign hit_way_oh[way_idx] = (l2t_request[601-:18] == l2t_tag[0 + ((7 - way_idx) * 18)+:18]) && l2t_valid[way_idx]; - end - endgenerate - assign cache_hit = |hit_way_oh && l2t_request_valid; - oh_to_idx #(.NUM_SIGNALS(8)) oh_to_idx_hit_way( - .one_hot(hit_way_oh), - .index(hit_way_idx) - ); - assign read_address = {(l2t_l2_fill ? l2t_fill_way : hit_way_idx), l2t_request[583-:8]}; - fakeram_1r1w_512x2048 #( - .DATA_WIDTH(defines_CACHE_LINE_BITS), - .SIZE(2048), - .READ_DURING_WRITE("NEW_DATA") - ) sram_l2_data( - .read_en(l2t_request_valid && (cache_hit || l2t_l2_fill)), - .read_addr(read_address), - .read_data(l2r_data), - .write_en(l2u_write_en), - .write_addr(l2u_write_addr), - .write_data(l2u_write_data), - .* - ); - assign flush_first_pass = (l2t_request[605-:3] == 3'd4) && !l2t_restarted_flush; - assign update_dirty = l2t_request_valid && (l2t_l2_fill || (cache_hit && (store || flush_first_pass))); - assign l2r_update_dirty_set = l2t_request[583-:8]; - assign l2r_update_dirty_value = store; - genvar _gv_dirty_update_idx_1; - function automatic [2:0] sv2v_cast_3; - input reg [2:0] inp; - sv2v_cast_3 = inp; - endfunction - generate - for (_gv_dirty_update_idx_1 = 0; _gv_dirty_update_idx_1 < 8; _gv_dirty_update_idx_1 = _gv_dirty_update_idx_1 + 1) begin : dirty_update_gen - localparam dirty_update_idx = _gv_dirty_update_idx_1; - assign l2r_update_dirty_en[dirty_update_idx] = update_dirty && (l2t_l2_fill ? l2t_fill_way == sv2v_cast_3(dirty_update_idx) : hit_way_oh[dirty_update_idx]); - end - endgenerate - assign update_tag = l2t_l2_fill || (cache_hit && dinvalidate); - assign tag_update_way = (l2t_l2_fill ? l2t_fill_way : hit_way_idx); - genvar _gv_tag_idx_1; - generate - for (_gv_tag_idx_1 = 0; _gv_tag_idx_1 < 8; _gv_tag_idx_1 = _gv_tag_idx_1 + 1) begin : tag_update_gen - localparam tag_idx = _gv_tag_idx_1; - assign l2r_update_tag_en[tag_idx] = update_tag && (tag_update_way == sv2v_cast_3(tag_idx)); - end - endgenerate - assign l2r_update_tag_set = l2t_request[583-:8]; - assign l2r_update_tag_valid = !dinvalidate; - assign l2r_update_tag_value = l2t_request[601-:18]; - assign l2r_update_lru_en = cache_hit && (load || store); - assign l2r_update_lru_hit_way = hit_way_idx; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - assign request_sync_slot = sv2v_cast_2({l2t_request[611-:4], l2t_request[607-:2]}); - assign can_store_sync = ((load_sync_address[request_sync_slot] == {l2t_request[601-:18], l2t_request[583-:8]}) && load_sync_address_valid[request_sync_slot]) && (l2t_request[605-:3] == 3'd3); - assign hit_or_miss = (l2t_request_valid && (((l2t_request[605-:3] == 3'd2) || can_store_sync) || (l2t_request[605-:3] == 3'd0))) && !l2t_l2_fill; - always @(posedge clk) begin - l2r_request <= l2t_request; - l2r_cache_hit <= cache_hit; - l2r_l2_fill <= l2t_l2_fill; - l2r_writeback_tag <= l2t_tag[0 + ((7 - writeback_way) * 18)+:18]; - l2r_needs_writeback <= l2t_dirty[writeback_way] && l2t_valid[writeback_way]; - l2r_data_from_memory <= l2t_data_from_memory; - l2r_hit_cache_idx <= read_address; - l2r_restarted_flush <= l2t_restarted_flush; - end - always @(posedge clk or posedge reset) - if (reset) begin - begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < defines_TOTAL_THREADS; i = i + 1) - begin - load_sync_address_valid[i] <= 1'sb0; - load_sync_address[i] <= 1'sb0; - end - end - l2r_perf_l2_hit <= 1'sb0; - l2r_perf_l2_miss <= 1'sb0; - l2r_request_valid <= 1'sb0; - l2r_store_sync_success <= 1'sb0; - end - else begin - l2r_request_valid <= l2t_request_valid; - if (l2t_request_valid && (cache_hit || l2t_l2_fill)) begin - (* full_case, parallel_case *) - case (l2t_request[605-:3]) - 3'd1: begin - load_sync_address[request_sync_slot] <= {l2t_request[601-:18], l2t_request[583-:8]}; - load_sync_address_valid[request_sync_slot] <= 1; - end - 3'd2, 3'd3: - if ((l2t_request[605-:3] == 3'd2) || can_store_sync) begin : sv2v_autoblock_2 - reg signed [31:0] entry_idx; - for (entry_idx = 0; entry_idx < defines_TOTAL_THREADS; entry_idx = entry_idx + 1) - if (load_sync_address[entry_idx] == {l2t_request[601-:18], l2t_request[583-:8]}) - load_sync_address_valid[entry_idx] <= 0; - end - default: - ; - endcase - l2r_store_sync_success <= can_store_sync; - end - else - l2r_store_sync_success <= 0; - l2r_perf_l2_miss <= hit_or_miss && !(|hit_way_oh); - l2r_perf_l2_hit <= hit_or_miss && |hit_way_oh; - end -endmodule -module l2_cache_tag_stage ( - clk, - reset, - l2a_request_valid, - l2a_request, - l2a_data_from_memory, - l2a_l2_fill, - l2a_restarted_flush, - l2r_update_dirty_en, - l2r_update_dirty_set, - l2r_update_dirty_value, - l2r_update_tag_en, - l2r_update_tag_set, - l2r_update_tag_valid, - l2r_update_tag_value, - l2r_update_lru_en, - l2r_update_lru_hit_way, - l2t_request_valid, - l2t_request, - l2t_valid, - l2t_tag, - l2t_dirty, - l2t_l2_fill, - l2t_fill_way, - l2t_data_from_memory, - l2t_restarted_flush -); - input clk; - input reset; - input l2a_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2a_request; - input wire [511:0] l2a_data_from_memory; - input l2a_l2_fill; - input l2a_restarted_flush; - input [7:0] l2r_update_dirty_en; - input wire [7:0] l2r_update_dirty_set; - input l2r_update_dirty_value; - input [7:0] l2r_update_tag_en; - input wire [7:0] l2r_update_tag_set; - input l2r_update_tag_valid; - input wire [17:0] l2r_update_tag_value; - input l2r_update_lru_en; - input wire [2:0] l2r_update_lru_hit_way; - output reg l2t_request_valid; - output reg [611:0] l2t_request; - output reg [0:7] l2t_valid; - output wire [143:0] l2t_tag; - output wire [0:7] l2t_dirty; - output reg l2t_l2_fill; - output wire [2:0] l2t_fill_way; - output reg [511:0] l2t_data_from_memory; - output reg l2t_restarted_flush; - cache_lru #( - .NUM_SETS(256), - .NUM_WAYS(8) - ) cache_lru( - .fill_en(l2a_l2_fill), - .fill_set(l2a_request[583-:8]), - .fill_way(l2t_fill_way), - .access_en(l2a_request_valid), - .access_set(l2a_request[583-:8]), - .update_en(l2r_update_lru_en), - .update_way(l2r_update_lru_hit_way), - .clk(clk), - .reset(reset) - ); - genvar _gv_way_idx_7; - generate - for (_gv_way_idx_7 = 0; _gv_way_idx_7 < 8; _gv_way_idx_7 = _gv_way_idx_7 + 1) begin : way_tags_gen - localparam way_idx = _gv_way_idx_7; - reg line_valid [0:255]; - fakeram_1r1w_18x256 #( - .DATA_WIDTH(18), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) sram_tags( - .read_en(l2a_request_valid), - .read_addr(l2a_request[583-:8]), - .read_data(l2t_tag[0 + ((7 - way_idx) * 18)+:18]), - .write_en(l2r_update_tag_en[way_idx]), - .write_addr(l2r_update_tag_set), - .write_data(l2r_update_tag_value), - .* - ); - fakeram_1r1w_1x256 #( - .DATA_WIDTH(1), - .SIZE(256), - .READ_DURING_WRITE("NEW_DATA") - ) sram_dirty_flags( - .read_en(l2a_request_valid), - .read_addr(l2a_request[583-:8]), - .read_data(l2t_dirty[way_idx]), - .write_en(l2r_update_dirty_en[way_idx]), - .write_addr(l2r_update_dirty_set), - .write_data(l2r_update_dirty_value), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < 256; set_idx = set_idx + 1) - line_valid[set_idx] <= 0; - end - else if (l2r_update_tag_en[way_idx]) - line_valid[l2r_update_tag_set] <= l2r_update_tag_valid; - always @(posedge clk) - if (l2a_request_valid) begin - if (l2r_update_tag_en[way_idx] && (l2r_update_tag_set == l2a_request[583-:8])) - l2t_valid[way_idx] <= l2r_update_tag_valid; - else - l2t_valid[way_idx] <= line_valid[l2a_request[583-:8]]; - end - end - endgenerate - always @(posedge clk) begin - l2t_data_from_memory <= l2a_data_from_memory; - l2t_request <= l2a_request; - l2t_l2_fill <= l2a_l2_fill; - l2t_restarted_flush <= l2a_restarted_flush; - end - always @(posedge clk or posedge reset) - if (reset) - l2t_request_valid <= 0; - else - l2t_request_valid <= l2a_request_valid; -endmodule -module l2_cache_update_stage ( - clk, - reset, - l2r_request_valid, - l2r_request, - l2r_data, - l2r_cache_hit, - l2r_hit_cache_idx, - l2r_l2_fill, - l2r_restarted_flush, - l2r_data_from_memory, - l2r_store_sync_success, - l2r_needs_writeback, - l2u_write_en, - l2u_write_addr, - l2u_write_data, - l2_response_valid, - l2_response -); - reg _sv2v_0; - input clk; - input reset; - input l2r_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - input wire [611:0] l2r_request; - input wire [511:0] l2r_data; - input l2r_cache_hit; - input wire [10:0] l2r_hit_cache_idx; - input l2r_l2_fill; - input l2r_restarted_flush; - input wire [511:0] l2r_data_from_memory; - input l2r_store_sync_success; - input l2r_needs_writeback; - output wire l2u_write_en; - output wire [10:0] l2u_write_addr; - output wire [511:0] l2u_write_data; - output reg l2_response_valid; - output reg [548:0] l2_response; - wire [511:0] original_data; - wire update_data; - reg [2:0] response_type; - wire completed_flush; - assign original_data = (l2r_l2_fill ? l2r_data_from_memory : l2r_data); - assign update_data = (l2r_request[605-:3] == 3'd2) || ((l2r_request[605-:3] == 3'd3) && l2r_store_sync_success); - genvar _gv_byte_lane_1; - generate - for (_gv_byte_lane_1 = 0; _gv_byte_lane_1 < defines_CACHE_LINE_BYTES; _gv_byte_lane_1 = _gv_byte_lane_1 + 1) begin : lane_mask_gen - localparam byte_lane = _gv_byte_lane_1; - assign l2u_write_data[byte_lane * 8+:8] = (l2r_request[512 + byte_lane] && update_data ? l2r_request[0 + (byte_lane * 8)+:8] : original_data[byte_lane * 8+:8]); - end - endgenerate - assign l2u_write_en = l2r_request_valid && (l2r_l2_fill || (l2r_cache_hit && ((l2r_request[605-:3] == 3'd2) || (l2r_request[605-:3] == 3'd3)))); - assign l2u_write_addr = l2r_hit_cache_idx; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (l2r_request[605-:3]) - 3'd0, 3'd1: response_type = 3'd0; - 3'd2, 3'd3: response_type = 3'd1; - 3'd4: response_type = 3'd2; - 3'd5: response_type = 3'd3; - 3'd6: response_type = 3'd4; - default: response_type = 3'd0; - endcase - end - assign completed_flush = (l2r_request[605-:3] == 3'd4) && ((l2r_restarted_flush || !l2r_cache_hit) || !l2r_needs_writeback); - always @(posedge clk or posedge reset) - if (reset) - l2_response_valid <= 0; - else if (l2r_request_valid && (((((l2r_cache_hit && (l2r_request[605-:3] != 3'd4)) || l2r_l2_fill) || completed_flush) || (l2r_request[605-:3] == 3'd6)) || (l2r_request[605-:3] == 3'd5))) - l2_response_valid <= 1; - else - l2_response_valid <= 0; - always @(posedge clk) begin - l2_response[548] <= (l2r_request[605-:3] == 3'd3 ? l2r_store_sync_success : 1'b1); - l2_response[547-:4] <= l2r_request[611-:4]; - l2_response[543-:2] <= l2r_request[607-:2]; - l2_response[541-:3] <= response_type; - l2_response[538] <= l2r_request[602]; - l2_response[511-:defines_CACHE_LINE_BITS] <= l2u_write_data; - l2_response[537-:26] <= l2r_request[601-:26]; - end - initial _sv2v_0 = 0; -endmodule -module oh_to_idx ( - one_hot, - index -); - reg _sv2v_0; - parameter NUM_SIGNALS = 4; - parameter DIRECTION = "LSB0"; - parameter INDEX_WIDTH = $clog2(NUM_SIGNALS); - input [NUM_SIGNALS - 1:0] one_hot; - output reg [INDEX_WIDTH - 1:0] index; - function automatic signed [INDEX_WIDTH - 1:0] sv2v_cast_BBE12_signed; - input reg signed [INDEX_WIDTH - 1:0] inp; - sv2v_cast_BBE12_signed = inp; - endfunction - always @(*) begin : convert - if (_sv2v_0) - ; - index = 0; - begin : sv2v_autoblock_1 - reg signed [31:0] oh_index; - for (oh_index = 0; oh_index < NUM_SIGNALS; oh_index = oh_index + 1) - if (one_hot[oh_index]) begin - if (DIRECTION == "LSB0") - index = index | oh_index[INDEX_WIDTH - 1:0]; - else - index = index | sv2v_cast_BBE12_signed((NUM_SIGNALS - oh_index) - 1); - end - end - end - initial _sv2v_0 = 0; -endmodule -module operand_fetch_stage ( - clk, - reset, - ts_instruction_valid, - ts_instruction, - ts_thread_idx, - ts_subcycle, - of_operand1, - of_operand2, - of_mask_value, - of_store_value, - of_instruction, - of_instruction_valid, - of_thread_idx, - of_subcycle, - wb_rollback_en, - wb_rollback_thread_idx, - wb_writeback_en, - wb_writeback_thread_idx, - wb_writeback_vector, - wb_writeback_value, - wb_writeback_mask, - wb_writeback_reg -); - reg _sv2v_0; - input clk; - input reset; - input ts_instruction_valid; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] ts_instruction; - input wire [1:0] ts_thread_idx; - input wire [3:0] ts_subcycle; - output reg [511:0] of_operand1; - output reg [511:0] of_operand2; - output reg [15:0] of_mask_value; - output wire [511:0] of_store_value; - output reg [141:0] of_instruction; - output reg of_instruction_valid; - output reg [1:0] of_thread_idx; - output reg [3:0] of_subcycle; - input wb_rollback_en; - input wire [1:0] wb_rollback_thread_idx; - input wb_writeback_en; - input wire [1:0] wb_writeback_thread_idx; - input wb_writeback_vector; - input wire [511:0] wb_writeback_value; - input wire [15:0] wb_writeback_mask; - input wire [4:0] wb_writeback_reg; - wire [31:0] scalar_val1; - wire [31:0] scalar_val2; - wire [511:0] vector_val1; - wire [511:0] vector_val2; - fakeram_2r1w_32x128 #( - .DATA_WIDTH(32), - .SIZE(128), - .READ_DURING_WRITE("DONT_CARE") - ) scalar_registers( - .read1_en(ts_instruction_valid && ts_instruction[101]), - .read1_addr({ts_thread_idx, ts_instruction[100-:5]}), - .read1_data(scalar_val1), - .read2_en(ts_instruction_valid && ts_instruction[95]), - .read2_addr({ts_thread_idx, ts_instruction[94-:5]}), - .read2_data(scalar_val2), - .write_en(wb_writeback_en && !wb_writeback_vector), - .write_addr({wb_writeback_thread_idx, wb_writeback_reg}), - .write_data(wb_writeback_value[0+:32]), - .* - ); - genvar _gv_lane_2; - generate - for (_gv_lane_2 = 0; _gv_lane_2 < defines_NUM_VECTOR_LANES; _gv_lane_2 = _gv_lane_2 + 1) begin : vector_lane_gen - localparam lane = _gv_lane_2; - fakeram_2r1w_32x128 #( - .DATA_WIDTH(32), - .SIZE(128), - .READ_DURING_WRITE("DONT_CARE") - ) vector_registers( - .read1_en(ts_instruction[89]), - .read1_addr({ts_thread_idx, ts_instruction[88-:5]}), - .read1_data(vector_val1[lane * 32+:32]), - .read2_en(ts_instruction[83]), - .read2_addr({ts_thread_idx, ts_instruction[82-:5]}), - .read2_data(vector_val2[lane * 32+:32]), - .write_en((wb_writeback_en && wb_writeback_vector) && wb_writeback_mask[(defines_NUM_VECTOR_LANES - lane) - 1]), - .write_addr({wb_writeback_thread_idx, wb_writeback_reg}), - .write_data(wb_writeback_value[lane * 32+:32]), - .* - ); - end - endgenerate - always @(posedge clk or posedge reset) - if (reset) - of_instruction_valid <= 0; - else - of_instruction_valid <= ts_instruction_valid && (!wb_rollback_en || (wb_rollback_thread_idx != ts_thread_idx)); - always @(posedge clk) begin - of_instruction <= ts_instruction; - of_thread_idx <= ts_thread_idx; - of_subcycle <= ts_subcycle; - end - assign of_store_value = (of_instruction[59] ? vector_val2 : {{15 {32'd0}}, scalar_val2}); - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (of_instruction[62]) - 1'd0: of_operand1 = vector_val1; - default: of_operand1 = {defines_NUM_VECTOR_LANES {scalar_val1}}; - endcase - (* full_case, parallel_case *) - case (of_instruction[61-:2]) - 2'd0: of_operand2 = {defines_NUM_VECTOR_LANES {scalar_val2}}; - 2'd1: of_operand2 = vector_val2; - default: of_operand2 = {defines_NUM_VECTOR_LANES {of_instruction[58-:32]}}; - endcase - (* full_case, parallel_case *) - case (of_instruction[64-:2]) - 2'd0: of_mask_value = scalar_val1[15:0]; - 2'd1: of_mask_value = scalar_val2[15:0]; - default: of_mask_value = {defines_NUM_VECTOR_LANES {1'b1}}; - endcase - end - initial _sv2v_0 = 0; -endmodule -module performance_counters ( - clk, - reset, - perf_events, - perf_event_select, - perf_event_count -); - parameter NUM_EVENTS = 1; - parameter EVENT_IDX_WIDTH = $clog2(NUM_EVENTS); - parameter NUM_COUNTERS = 2; - parameter COUNTER_IDX_WIDTH = $clog2(NUM_COUNTERS); - input clk; - input reset; - input [NUM_EVENTS - 1:0] perf_events; - input [(NUM_COUNTERS * EVENT_IDX_WIDTH) - 1:0] perf_event_select; - output reg [(NUM_COUNTERS * 64) - 1:0] perf_event_count; - always @(posedge clk or posedge reset) begin : update - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < NUM_COUNTERS; i = i + 1) - perf_event_count[i * 64+:64] <= 0; - end - else begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 0; i < NUM_COUNTERS; i = i + 1) - if (perf_events[perf_event_select[i * EVENT_IDX_WIDTH+:EVENT_IDX_WIDTH]]) - perf_event_count[i * 64+:64] <= perf_event_count[i * 64+:64] + 1; - end - end -endmodule -module reciprocal_rom ( - significand, - reciprocal_estimate -); - reg _sv2v_0; - input [5:0] significand; - output reg [5:0] reciprocal_estimate; - always @(*) begin - if (_sv2v_0) - ; - case (significand) - 6'h00: reciprocal_estimate = 6'h00; - 6'h01: reciprocal_estimate = 6'h3e; - 6'h02: reciprocal_estimate = 6'h3c; - 6'h03: reciprocal_estimate = 6'h3a; - 6'h04: reciprocal_estimate = 6'h38; - 6'h05: reciprocal_estimate = 6'h36; - 6'h06: reciprocal_estimate = 6'h35; - 6'h07: reciprocal_estimate = 6'h33; - 6'h08: reciprocal_estimate = 6'h31; - 6'h09: reciprocal_estimate = 6'h30; - 6'h0a: reciprocal_estimate = 6'h2e; - 6'h0b: reciprocal_estimate = 6'h2d; - 6'h0c: reciprocal_estimate = 6'h2b; - 6'h0d: reciprocal_estimate = 6'h2a; - 6'h0e: reciprocal_estimate = 6'h29; - 6'h0f: reciprocal_estimate = 6'h27; - 6'h10: reciprocal_estimate = 6'h26; - 6'h11: reciprocal_estimate = 6'h25; - 6'h12: reciprocal_estimate = 6'h23; - 6'h13: reciprocal_estimate = 6'h22; - 6'h14: reciprocal_estimate = 6'h21; - 6'h15: reciprocal_estimate = 6'h20; - 6'h16: reciprocal_estimate = 6'h1f; - 6'h17: reciprocal_estimate = 6'h1e; - 6'h18: reciprocal_estimate = 6'h1d; - 6'h19: reciprocal_estimate = 6'h1c; - 6'h1a: reciprocal_estimate = 6'h1b; - 6'h1b: reciprocal_estimate = 6'h1a; - 6'h1c: reciprocal_estimate = 6'h19; - 6'h1d: reciprocal_estimate = 6'h18; - 6'h1e: reciprocal_estimate = 6'h17; - 6'h1f: reciprocal_estimate = 6'h16; - 6'h20: reciprocal_estimate = 6'h15; - 6'h21: reciprocal_estimate = 6'h14; - 6'h22: reciprocal_estimate = 6'h13; - 6'h23: reciprocal_estimate = 6'h12; - 6'h24: reciprocal_estimate = 6'h11; - 6'h25: reciprocal_estimate = 6'h11; - 6'h26: reciprocal_estimate = 6'h10; - 6'h27: reciprocal_estimate = 6'h0f; - 6'h28: reciprocal_estimate = 6'h0e; - 6'h29: reciprocal_estimate = 6'h0e; - 6'h2a: reciprocal_estimate = 6'h0d; - 6'h2b: reciprocal_estimate = 6'h0c; - 6'h2c: reciprocal_estimate = 6'h0b; - 6'h2d: reciprocal_estimate = 6'h0b; - 6'h2e: reciprocal_estimate = 6'h0a; - 6'h2f: reciprocal_estimate = 6'h09; - 6'h30: reciprocal_estimate = 6'h09; - 6'h31: reciprocal_estimate = 6'h08; - 6'h32: reciprocal_estimate = 6'h07; - 6'h33: reciprocal_estimate = 6'h07; - 6'h34: reciprocal_estimate = 6'h06; - 6'h35: reciprocal_estimate = 6'h06; - 6'h36: reciprocal_estimate = 6'h05; - 6'h37: reciprocal_estimate = 6'h04; - 6'h38: reciprocal_estimate = 6'h04; - 6'h39: reciprocal_estimate = 6'h03; - 6'h3a: reciprocal_estimate = 6'h03; - 6'h3b: reciprocal_estimate = 6'h02; - 6'h3c: reciprocal_estimate = 6'h02; - 6'h3d: reciprocal_estimate = 6'h01; - 6'h3e: reciprocal_estimate = 6'h01; - 6'h3f: reciprocal_estimate = 6'h00; - default: reciprocal_estimate = 6'h00; - endcase - end - initial _sv2v_0 = 0; -endmodule -module rr_arbiter ( - clk, - reset, - request, - update_lru, - grant_oh -); - reg _sv2v_0; - parameter NUM_REQUESTERS = 4; - input clk; - input reset; - input [NUM_REQUESTERS - 1:0] request; - input update_lru; - output reg [NUM_REQUESTERS - 1:0] grant_oh; - wire [NUM_REQUESTERS - 1:0] priority_oh_nxt; - reg [NUM_REQUESTERS - 1:0] priority_oh; - localparam BIT_IDX_WIDTH = $clog2(NUM_REQUESTERS); - always @(*) begin - if (_sv2v_0) - ; - begin : sv2v_autoblock_1 - reg signed [31:0] grant_idx; - for (grant_idx = 0; grant_idx < NUM_REQUESTERS; grant_idx = grant_idx + 1) - begin - grant_oh[grant_idx] = 0; - begin : sv2v_autoblock_2 - reg signed [31:0] priority_idx; - for (priority_idx = 0; priority_idx < NUM_REQUESTERS; priority_idx = priority_idx + 1) - begin : sv2v_autoblock_3 - reg granted; - granted = request[grant_idx] & priority_oh[priority_idx]; - begin : sv2v_autoblock_4 - reg [BIT_IDX_WIDTH - 1:0] bit_idx; - for (bit_idx = priority_idx[BIT_IDX_WIDTH - 1:0] % NUM_REQUESTERS; bit_idx != grant_idx[BIT_IDX_WIDTH - 1:0]; bit_idx = (bit_idx + 1) % NUM_REQUESTERS) - granted = granted & !request[bit_idx]; - end - grant_oh[grant_idx] = grant_oh[grant_idx] | granted; - end - end - end - end - end - assign priority_oh_nxt = {grant_oh[NUM_REQUESTERS - 2:0], grant_oh[NUM_REQUESTERS - 1]}; - always @(posedge clk or posedge reset) - if (reset) - priority_oh <= 1; - else if ((request != 0) && update_lru) - priority_oh <= priority_oh_nxt; - initial _sv2v_0 = 0; -endmodule -module scoreboard ( - clk, - reset, - next_instruction, - scoreboard_can_issue, - will_issue, - writeback_en, - wb_writeback_vector, - wb_writeback_reg, - rollback_en, - wb_rollback_pipeline -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] next_instruction; - output wire scoreboard_can_issue; - input will_issue; - input writeback_en; - input wb_writeback_vector; - input wire [4:0] wb_writeback_reg; - input rollback_en; - input wire [1:0] wb_rollback_pipeline; - localparam defines_NUM_REGISTERS = 32; - localparam SCOREBOARD_ENTRIES = 64; - localparam ROLLBACK_STAGES = 4; - reg [3:0] has_writeback; - reg [5:0] writeback_reg [0:3]; - reg [63:0] scoreboard_regs; - wire [63:0] scoreboard_regs_nxt; - reg [63:0] dest_bitmap; - reg [63:0] dep_bitmap; - reg [63:0] rollback_bitmap; - reg [63:0] writeback_bitmap; - wire [63:0] clear_bitmap; - wire [63:0] set_bitmap; - always @(*) begin - if (_sv2v_0) - ; - rollback_bitmap = 0; - if (rollback_en) begin - begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < 3; i = i + 1) - if (has_writeback[i]) - rollback_bitmap[writeback_reg[i]] = 1; - end - if (has_writeback[3] && (wb_rollback_pipeline == 2'd0)) - rollback_bitmap[writeback_reg[3]] = 1; - end - end - always @(*) begin - if (_sv2v_0) - ; - dep_bitmap = 0; - if (next_instruction[77]) begin - if (next_instruction[76]) - dep_bitmap[{1'b1, next_instruction[75-:5]}] = 1; - else - dep_bitmap[{1'b0, next_instruction[75-:5]}] = 1; - end - if (next_instruction[101]) - dep_bitmap[{1'b0, next_instruction[100-:5]}] = 1; - if (next_instruction[95]) - dep_bitmap[{1'b0, next_instruction[94-:5]}] = 1; - if (next_instruction[89]) - dep_bitmap[{1'b1, next_instruction[88-:5]}] = 1; - if (next_instruction[83]) - dep_bitmap[{1'b1, next_instruction[82-:5]}] = 1; - end - always @(*) begin - if (_sv2v_0) - ; - dest_bitmap = 0; - if (next_instruction[77]) begin - if (next_instruction[76]) - dest_bitmap[{1'b1, next_instruction[75-:5]}] = 1; - else - dest_bitmap[{1'b0, next_instruction[75-:5]}] = 1; - end - end - always @(*) begin - if (_sv2v_0) - ; - writeback_bitmap = 0; - if (writeback_en) begin - if (wb_writeback_vector) - writeback_bitmap[{1'b1, wb_writeback_reg}] = 1; - else - writeback_bitmap[{1'b0, wb_writeback_reg}] = 1; - end - end - assign clear_bitmap = rollback_bitmap | writeback_bitmap; - assign set_bitmap = dest_bitmap & {SCOREBOARD_ENTRIES {will_issue}}; - assign scoreboard_regs_nxt = (scoreboard_regs & ~clear_bitmap) | set_bitmap; - assign scoreboard_can_issue = (scoreboard_regs & dep_bitmap) == 0; - always @(posedge clk or posedge reset) - if (reset) begin - scoreboard_regs <= 1'sb0; - has_writeback <= 1'sb0; - end - else begin - scoreboard_regs <= scoreboard_regs_nxt; - has_writeback <= {has_writeback[2:0], will_issue && next_instruction[77]}; - end - always @(posedge clk) begin - if (will_issue) - writeback_reg[0] <= {next_instruction[76], next_instruction[75-:5]}; - begin : sv2v_autoblock_2 - reg signed [31:0] i; - for (i = 1; i < ROLLBACK_STAGES; i = i + 1) - writeback_reg[i] <= writeback_reg[i - 1]; - end - end - initial _sv2v_0 = 0; -endmodule -module sync_fifo ( - clk, - reset, - flush_en, - full, - almost_full, - enqueue_en, - enqueue_value, - empty, - almost_empty, - dequeue_en, - dequeue_value -); - parameter WIDTH = 64; - parameter SIZE = 4; - parameter ALMOST_FULL_THRESHOLD = SIZE; - parameter ALMOST_EMPTY_THRESHOLD = 1; - input clk; - input reset; - input flush_en; - output wire full; - output wire almost_full; - input enqueue_en; - input [WIDTH - 1:0] enqueue_value; - output wire empty; - output wire almost_empty; - input dequeue_en; - output wire [WIDTH - 1:0] dequeue_value; - localparam ADDR_WIDTH = $clog2(SIZE); - reg [ADDR_WIDTH - 1:0] head; - reg [ADDR_WIDTH - 1:0] tail; - reg [ADDR_WIDTH:0] count; - reg [WIDTH - 1:0] data [0:SIZE - 1]; - function automatic signed [((ADDR_WIDTH + 0) >= 0 ? ADDR_WIDTH + 1 : 1 - (ADDR_WIDTH + 0)) - 1:0] sv2v_cast_D7FEC_signed; - input reg signed [((ADDR_WIDTH + 0) >= 0 ? ADDR_WIDTH + 1 : 1 - (ADDR_WIDTH + 0)) - 1:0] inp; - sv2v_cast_D7FEC_signed = inp; - endfunction - assign almost_full = count >= sv2v_cast_D7FEC_signed(ALMOST_FULL_THRESHOLD); - assign almost_empty = count <= sv2v_cast_D7FEC_signed(ALMOST_EMPTY_THRESHOLD); - assign full = count == SIZE; - assign empty = count == 0; - assign dequeue_value = data[head]; - always @(posedge clk or posedge reset) - if (reset) begin - head <= 0; - tail <= 0; - count <= 0; - end - else if (flush_en) begin - head <= 0; - tail <= 0; - count <= 0; - end - else begin - if (enqueue_en) begin - tail <= tail + 1; - data[tail] <= enqueue_value; - end - if (dequeue_en) - head <= head + 1; - if (enqueue_en && !dequeue_en) - count <= count + 1; - else if (dequeue_en && !enqueue_en) - count <= count - 1; - end -endmodule -module synchronizer ( - clk, - reset, - data_o, - data_i -); - parameter WIDTH = 1; - parameter RESET_STATE = 0; - input clk; - input reset; - output reg [WIDTH - 1:0] data_o; - input [WIDTH - 1:0] data_i; - reg [WIDTH - 1:0] sync0; - reg [WIDTH - 1:0] sync1; - function automatic signed [WIDTH - 1:0] sv2v_cast_E6D93_signed; - input reg signed [WIDTH - 1:0] inp; - sv2v_cast_E6D93_signed = inp; - endfunction - always @(posedge clk or posedge reset) - if (reset) begin - sync0 <= sv2v_cast_E6D93_signed(RESET_STATE); - sync1 <= sv2v_cast_E6D93_signed(RESET_STATE); - data_o <= sv2v_cast_E6D93_signed(RESET_STATE); - end - else begin - sync0 <= data_i; - sync1 <= sync0; - data_o <= sync1; - end -endmodule -module thread_select_stage ( - clk, - reset, - id_instruction, - id_instruction_valid, - id_thread_idx, - ts_fetch_en, - ts_instruction_valid, - ts_instruction, - ts_thread_idx, - ts_subcycle, - wb_writeback_en, - wb_writeback_thread_idx, - wb_writeback_vector, - wb_writeback_reg, - wb_writeback_last_subcycle, - wb_rollback_thread_idx, - wb_rollback_en, - wb_rollback_pipeline, - wb_rollback_subcycle, - thread_en, - wb_suspend_thread_oh, - l2i_dcache_wake_bitmap, - ior_wake_bitmap, - ts_perf_instruction_issue -); - reg _sv2v_0; - input clk; - input reset; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] id_instruction; - input id_instruction_valid; - input wire [1:0] id_thread_idx; - output wire [3:0] ts_fetch_en; - output reg ts_instruction_valid; - output reg [141:0] ts_instruction; - output reg [1:0] ts_thread_idx; - output reg [3:0] ts_subcycle; - input wb_writeback_en; - input wire [1:0] wb_writeback_thread_idx; - input wb_writeback_vector; - input wire [4:0] wb_writeback_reg; - input wb_writeback_last_subcycle; - input wire [1:0] wb_rollback_thread_idx; - input wb_rollback_en; - input wire [1:0] wb_rollback_pipeline; - input wire [3:0] wb_rollback_subcycle; - input wire [3:0] thread_en; - input wire [3:0] wb_suspend_thread_oh; - input wire [3:0] l2i_dcache_wake_bitmap; - input wire [3:0] ior_wake_bitmap; - output reg ts_perf_instruction_issue; - localparam THREAD_FIFO_SIZE = 8; - localparam WRITEBACK_ALLOC_STAGES = 4; - wire [141:0] thread_instr [0:3]; - wire [141:0] issue_instr; - reg [3:0] thread_blocked; - wire [3:0] can_issue_thread; - wire [3:0] thread_issue_oh; - wire [1:0] issue_thread_idx; - reg [3:0] writeback_allocate; - reg [3:0] writeback_allocate_nxt; - reg [3:0] current_subcycle [0:3]; - wire issue_last_subcycle [0:3]; - genvar _gv_thread_idx_6; - function automatic [1:0] sv2v_cast_2; - input reg [1:0] inp; - sv2v_cast_2 = inp; - endfunction - function automatic [3:0] sv2v_cast_60D1B; - input reg [3:0] inp; - sv2v_cast_60D1B = inp; - endfunction - generate - for (_gv_thread_idx_6 = 0; _gv_thread_idx_6 < 4; _gv_thread_idx_6 = _gv_thread_idx_6 + 1) begin : thread_logic_gen - localparam thread_idx = _gv_thread_idx_6; - wire ififo_almost_full; - wire ififo_empty; - reg writeback_conflict; - wire rollback_this_thread; - wire enqueue_this_thread; - wire writeback_this_thread; - wire scoreboard_can_issue; - assign enqueue_this_thread = id_instruction_valid && (id_thread_idx == sv2v_cast_2(thread_idx)); - sync_fifo #( - .WIDTH(142), - .SIZE(THREAD_FIFO_SIZE), - .ALMOST_FULL_THRESHOLD(5) - ) instruction_fifo( - .flush_en(rollback_this_thread), - .full(), - .almost_full(ififo_almost_full), - .enqueue_en(enqueue_this_thread), - .enqueue_value(id_instruction), - .empty(ififo_empty), - .almost_empty(), - .dequeue_en(issue_last_subcycle[thread_idx]), - .dequeue_value(thread_instr[thread_idx]), - .clk(clk), - .reset(reset) - ); - assign writeback_this_thread = (wb_writeback_en && (wb_writeback_thread_idx == sv2v_cast_2(thread_idx))) && wb_writeback_last_subcycle; - assign rollback_this_thread = wb_rollback_en && (wb_rollback_thread_idx == sv2v_cast_2(thread_idx)); - scoreboard scoreboard( - .next_instruction(thread_instr[thread_idx]), - .will_issue(thread_issue_oh[thread_idx]), - .writeback_en(writeback_this_thread), - .rollback_en(rollback_this_thread), - .clk(clk), - .reset(reset), - .scoreboard_can_issue(scoreboard_can_issue), - .wb_writeback_vector(wb_writeback_vector), - .wb_writeback_reg(wb_writeback_reg), - .wb_rollback_pipeline(wb_rollback_pipeline) - ); - assign ts_fetch_en[thread_idx] = !ififo_almost_full && thread_en[thread_idx]; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (thread_instr[thread_idx][21-:2]) - 2'd1: writeback_conflict = writeback_allocate[0]; - 2'd0: writeback_conflict = writeback_allocate[1]; - default: writeback_conflict = 0; - endcase - end - assign can_issue_thread[thread_idx] = ((((!ififo_empty && (scoreboard_can_issue || (current_subcycle[thread_idx] != 0))) && thread_en[thread_idx]) && !rollback_this_thread) && !writeback_conflict) && !thread_blocked[thread_idx]; - assign issue_last_subcycle[thread_idx] = thread_issue_oh[thread_idx] && (current_subcycle[thread_idx] == thread_instr[thread_idx][12-:4]); - always @(posedge clk or posedge reset) - if (reset) - current_subcycle[thread_idx] <= 0; - else if (wb_rollback_en && (wb_rollback_thread_idx == sv2v_cast_2(thread_idx))) - current_subcycle[thread_idx] <= wb_rollback_subcycle; - else if (issue_last_subcycle[thread_idx]) - current_subcycle[thread_idx] <= 0; - else if (thread_issue_oh[thread_idx]) - current_subcycle[thread_idx] <= current_subcycle[thread_idx] + sv2v_cast_60D1B(1); - end - endgenerate - always @(*) begin - if (_sv2v_0) - ; - writeback_allocate_nxt = {1'b0, writeback_allocate[3:1]}; - if (|thread_issue_oh) - (* full_case, parallel_case *) - case (issue_instr[21-:2]) - 2'd2: writeback_allocate_nxt[3] = 1'b1; - 2'd0: writeback_allocate_nxt[0] = 1'b1; - default: - ; - endcase - end - rr_arbiter #(.NUM_REQUESTERS(4)) thread_select_arbiter( - .request(can_issue_thread), - .update_lru(1'b1), - .grant_oh(thread_issue_oh), - .clk(clk), - .reset(reset) - ); - oh_to_idx #(.NUM_SIGNALS(4)) thread_oh_to_idx( - .one_hot(thread_issue_oh), - .index(issue_thread_idx) - ); - assign issue_instr = thread_instr[issue_thread_idx]; - always @(posedge clk) begin - ts_instruction <= issue_instr; - ts_thread_idx <= issue_thread_idx; - ts_subcycle <= current_subcycle[issue_thread_idx]; - end - always @(posedge clk or posedge reset) - if (reset) begin - thread_blocked <= 1'sb0; - ts_instruction_valid <= 1'sb0; - ts_perf_instruction_issue <= 1'sb0; - writeback_allocate <= 1'sb0; - end - else begin - ts_instruction_valid <= |thread_issue_oh; - thread_blocked <= (thread_blocked | wb_suspend_thread_oh) & ~(l2i_dcache_wake_bitmap | ior_wake_bitmap); - writeback_allocate <= writeback_allocate_nxt; - ts_perf_instruction_issue <= |thread_issue_oh; - end - initial _sv2v_0 = 0; -endmodule -module tlb ( - clk, - reset, - lookup_en, - update_en, - invalidate_en, - invalidate_all_en, - request_vpage_idx, - request_asid, - update_ppage_idx, - update_present, - update_exe_writable, - update_supervisor, - update_global, - lookup_ppage_idx, - lookup_hit, - lookup_present, - lookup_exe_writable, - lookup_supervisor -); - reg _sv2v_0; - parameter NUM_ENTRIES = 64; - parameter NUM_WAYS = 4; - input clk; - input reset; - input lookup_en; - input update_en; - input invalidate_en; - input invalidate_all_en; - localparam defines_PAGE_SIZE = 'h1000; - localparam defines_PAGE_NUM_BITS = 32 - $clog2('h1000); - input wire [defines_PAGE_NUM_BITS - 1:0] request_vpage_idx; - localparam defines_ASID_WIDTH = 8; - input [7:0] request_asid; - input wire [defines_PAGE_NUM_BITS - 1:0] update_ppage_idx; - input update_present; - input update_exe_writable; - input update_supervisor; - input update_global; - output reg [defines_PAGE_NUM_BITS - 1:0] lookup_ppage_idx; - output wire lookup_hit; - output reg lookup_present; - output reg lookup_exe_writable; - output reg lookup_supervisor; - localparam NUM_SETS = NUM_ENTRIES / NUM_WAYS; - localparam SET_INDEX_WIDTH = $clog2(NUM_SETS); - localparam WAY_INDEX_WIDTH = $clog2(NUM_WAYS); - wire [NUM_WAYS - 1:0] way_hit_oh; - wire [defines_PAGE_NUM_BITS - 1:0] way_ppage_idx [0:NUM_WAYS - 1]; - wire way_present [0:NUM_WAYS - 1]; - wire way_exe_writable [0:NUM_WAYS - 1]; - wire way_supervisor [0:NUM_WAYS - 1]; - reg [defines_PAGE_NUM_BITS - 1:0] request_vpage_idx_latched; - reg [defines_PAGE_NUM_BITS - 1:0] update_ppage_idx_latched; - wire [SET_INDEX_WIDTH - 1:0] request_set_idx; - wire [SET_INDEX_WIDTH - 1:0] update_set_idx; - reg update_en_latched; - wire update_valid; - reg invalidate_en_latched; - wire tlb_read_en; - reg [NUM_WAYS - 1:0] way_update_oh; - reg [NUM_WAYS - 1:0] next_way_oh; - reg update_present_latched; - reg update_exe_writable_latched; - reg update_supervisor_latched; - reg update_global_latched; - reg [7:0] request_asid_latched; - assign request_set_idx = request_vpage_idx[SET_INDEX_WIDTH - 1:0]; - assign update_set_idx = request_vpage_idx_latched[SET_INDEX_WIDTH - 1:0]; - assign tlb_read_en = (lookup_en || update_en) || invalidate_en; - genvar _gv_way_idx_8; - generate - for (_gv_way_idx_8 = 0; _gv_way_idx_8 < NUM_WAYS; _gv_way_idx_8 = _gv_way_idx_8 + 1) begin : way_gen - localparam way_idx = _gv_way_idx_8; - wire [defines_PAGE_NUM_BITS - 1:0] way_vpage_idx; - reg way_valid; - reg entry_valid [0:NUM_SETS - 1]; - wire [7:0] way_asid; - wire way_global; - fakeram_1r1w_16x52 #( - .SIZE(NUM_SETS), - .DATA_WIDTH(((defines_PAGE_NUM_BITS * 2) + 4) + defines_ASID_WIDTH), - .READ_DURING_WRITE("NEW_DATA") - ) tlb_paddr_sram( - .read_en(tlb_read_en), - .read_addr(request_set_idx), - .read_data({way_vpage_idx, way_asid, way_ppage_idx[way_idx], way_present[way_idx], way_exe_writable[way_idx], way_supervisor[way_idx], way_global}), - .write_en(way_update_oh[way_idx]), - .write_addr(update_set_idx), - .write_data({request_vpage_idx_latched, request_asid_latched, update_ppage_idx_latched, update_present_latched, update_exe_writable_latched, update_supervisor_latched, update_global_latched}), - .* - ); - always @(posedge clk or posedge reset) - if (reset) begin : sv2v_autoblock_1 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < NUM_SETS; set_idx = set_idx + 1) - entry_valid[set_idx] <= 0; - end - else if (invalidate_all_en) begin : sv2v_autoblock_2 - reg signed [31:0] set_idx; - for (set_idx = 0; set_idx < NUM_SETS; set_idx = set_idx + 1) - entry_valid[set_idx] <= 0; - end - else if (way_update_oh[way_idx]) - entry_valid[update_set_idx] <= update_valid; - always @(posedge clk) - if (!tlb_read_en) - way_valid <= 0; - else if (way_update_oh[way_idx] && (update_set_idx == request_set_idx)) - way_valid <= update_valid; - else - way_valid <= entry_valid[request_set_idx]; - assign way_hit_oh[way_idx] = (way_valid && (way_vpage_idx == request_vpage_idx_latched)) && (((way_asid == request_asid_latched) || way_global) || (update_en_latched && update_global_latched)); - end - endgenerate - always @(posedge clk) begin - update_ppage_idx_latched <= update_ppage_idx; - update_present_latched <= update_present; - update_exe_writable_latched <= update_exe_writable; - update_supervisor_latched <= update_supervisor; - update_global_latched <= update_global; - request_asid_latched <= request_asid; - request_vpage_idx_latched <= request_vpage_idx; - end - always @(posedge clk or posedge reset) - if (reset) begin - invalidate_en_latched <= 1'sb0; - update_en_latched <= 1'sb0; - end - else begin - update_en_latched <= update_en; - invalidate_en_latched <= invalidate_en; - end - assign lookup_hit = |way_hit_oh; - always @(*) begin - if (_sv2v_0) - ; - lookup_ppage_idx = 0; - lookup_present = 0; - lookup_exe_writable = 0; - lookup_supervisor = 0; - begin : sv2v_autoblock_3 - reg signed [31:0] way; - for (way = 0; way < NUM_WAYS; way = way + 1) - if (way_hit_oh[way]) begin - lookup_ppage_idx = lookup_ppage_idx | way_ppage_idx[way]; - lookup_present = lookup_present | way_present[way]; - lookup_exe_writable = lookup_exe_writable | way_exe_writable[way]; - lookup_supervisor = lookup_supervisor | way_supervisor[way]; - end - end - end - always @(*) begin - if (_sv2v_0) - ; - if (update_en_latched || invalidate_en_latched) begin - if (lookup_hit) - way_update_oh = way_hit_oh; - else - way_update_oh = next_way_oh; - end - else - way_update_oh = 1'sb0; - end - assign update_valid = update_en_latched; - function automatic signed [NUM_WAYS - 1:0] sv2v_cast_5B59D_signed; - input reg signed [NUM_WAYS - 1:0] inp; - sv2v_cast_5B59D_signed = inp; - endfunction - always @(posedge clk or posedge reset) - if (reset) - next_way_oh <= sv2v_cast_5B59D_signed(1); - else if (update_en) - next_way_oh <= {next_way_oh[NUM_WAYS - 2:0], next_way_oh[NUM_WAYS - 1]}; - initial _sv2v_0 = 0; -endmodule -module writeback_stage ( - clk, - reset, - fx5_instruction_valid, - fx5_instruction, - fx5_result, - fx5_mask_value, - fx5_thread_idx, - fx5_subcycle, - ix_instruction_valid, - ix_instruction, - ix_result, - ix_thread_idx, - ix_mask_value, - ix_rollback_en, - ix_rollback_pc, - ix_subcycle, - ix_privileged_op_fault, - dd_instruction_valid, - dd_instruction, - dd_lane_mask, - dd_thread_idx, - dd_request_vaddr, - dd_subcycle, - dd_rollback_en, - dd_rollback_pc, - dd_load_data, - dd_suspend_thread, - dd_io_access, - dd_trap, - dd_trap_cause, - sq_store_bypass_mask, - sq_store_bypass_data, - sq_store_sync_success, - sq_rollback_en, - ior_read_value, - ior_rollback_en, - cr_creg_read_val, - cr_trap_handler, - cr_tlb_miss_handler, - cr_eret_subcycle, - wb_trap, - wb_trap_cause, - wb_trap_pc, - wb_trap_access_vaddr, - wb_trap_subcycle, - wb_syscall_index, - wb_eret, - wb_rollback_en, - wb_rollback_thread_idx, - wb_rollback_pc, - wb_rollback_pipeline, - wb_rollback_subcycle, - wb_writeback_en, - wb_writeback_thread_idx, - wb_writeback_vector, - wb_writeback_value, - wb_writeback_mask, - wb_writeback_reg, - wb_writeback_last_subcycle, - wb_suspend_thread_oh, - wb_inst_injected, - wb_perf_instruction_retire, - wb_perf_store_rollback, - wb_perf_interrupt -); - reg _sv2v_0; - input clk; - input reset; - input fx5_instruction_valid; - localparam defines_NUM_VECTOR_LANES = 16; - input wire [141:0] fx5_instruction; - input wire [511:0] fx5_result; - input wire [15:0] fx5_mask_value; - input wire [1:0] fx5_thread_idx; - input wire [3:0] fx5_subcycle; - input ix_instruction_valid; - input wire [141:0] ix_instruction; - input wire [511:0] ix_result; - input wire [1:0] ix_thread_idx; - input wire [15:0] ix_mask_value; - input wire ix_rollback_en; - input wire [31:0] ix_rollback_pc; - input wire [3:0] ix_subcycle; - input ix_privileged_op_fault; - input dd_instruction_valid; - input wire [141:0] dd_instruction; - input wire [15:0] dd_lane_mask; - input wire [1:0] dd_thread_idx; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - localparam defines_DCACHE_TAG_BITS = 20; - input wire [31:0] dd_request_vaddr; - input wire [3:0] dd_subcycle; - input dd_rollback_en; - input wire [31:0] dd_rollback_pc; - localparam defines_CACHE_LINE_BITS = 512; - input wire [511:0] dd_load_data; - input dd_suspend_thread; - input dd_io_access; - input wire dd_trap; - input wire [5:0] dd_trap_cause; - input [63:0] sq_store_bypass_mask; - input wire [511:0] sq_store_bypass_data; - input sq_store_sync_success; - input sq_rollback_en; - input wire [31:0] ior_read_value; - input wire ior_rollback_en; - input wire [31:0] cr_creg_read_val; - input wire [31:0] cr_trap_handler; - input wire [31:0] cr_tlb_miss_handler; - input wire [15:0] cr_eret_subcycle; - output reg wb_trap; - output reg [5:0] wb_trap_cause; - output reg [31:0] wb_trap_pc; - output reg [31:0] wb_trap_access_vaddr; - output reg [3:0] wb_trap_subcycle; - output wire [14:0] wb_syscall_index; - output reg wb_eret; - output reg wb_rollback_en; - output reg [1:0] wb_rollback_thread_idx; - output reg [31:0] wb_rollback_pc; - output reg [1:0] wb_rollback_pipeline; - output reg [3:0] wb_rollback_subcycle; - output reg wb_writeback_en; - output reg [1:0] wb_writeback_thread_idx; - output reg wb_writeback_vector; - output reg [511:0] wb_writeback_value; - output reg [15:0] wb_writeback_mask; - output reg [4:0] wb_writeback_reg; - output reg wb_writeback_last_subcycle; - output wire [3:0] wb_suspend_thread_oh; - output reg wb_inst_injected; - output reg wb_perf_instruction_retire; - output reg wb_perf_store_rollback; - output reg wb_perf_interrupt; - wire [31:0] mem_load_lane; - localparam defines_CACHE_LINE_WORDS = 16; - wire [3:0] mem_load_lane_idx; - reg [7:0] byte_aligned; - reg [15:0] half_aligned; - wire [31:0] swapped_word_value; - wire [3:0] memory_op; - wire [511:0] endian_twiddled_data; - wire [15:0] scycle_vcompare_result; - wire [15:0] mcycle_vcompare_result; - wire [15:0] dd_vector_lane_oh; - wire [511:0] bypassed_read_data; - wire [3:0] thread_dd_oh; - wire last_subcycle_dd; - wire last_subcycle_ix; - wire last_subcycle_fx; - reg writeback_en_nxt; - reg [1:0] writeback_thread_idx_nxt; - reg writeback_vector_nxt; - reg [511:0] writeback_value_nxt; - reg [15:0] writeback_mask_nxt; - reg [4:0] writeback_reg_nxt; - reg writeback_last_subcycle_nxt; - always @(*) begin - if (_sv2v_0) - ; - wb_rollback_en = 0; - wb_rollback_pc = 0; - wb_rollback_thread_idx = 0; - wb_rollback_pipeline = 2'd1; - wb_trap = 0; - wb_trap_cause = 6'h00; - wb_rollback_subcycle = 0; - wb_trap_pc = 0; - wb_trap_access_vaddr = 0; - wb_trap_subcycle = dd_subcycle; - wb_eret = 0; - if (ix_instruction_valid && (ix_instruction[108] || ix_privileged_op_fault)) begin - wb_rollback_en = 1; - if (ix_instruction[105-:4] == 4'd7) - wb_rollback_pc = cr_tlb_miss_handler; - else - wb_rollback_pc = cr_trap_handler; - wb_rollback_thread_idx = ix_thread_idx; - wb_rollback_pipeline = 2'd1; - wb_trap = 1; - if (ix_privileged_op_fault) - wb_trap_cause = 6'h02; - else - wb_trap_cause = ix_instruction[107-:6]; - wb_trap_pc = ix_instruction[141-:32]; - wb_trap_access_vaddr = ix_instruction[141-:32]; - wb_trap_subcycle = ix_subcycle; - end - else if (dd_instruction_valid && dd_trap) begin - wb_rollback_en = 1'b1; - if (dd_trap_cause[3-:4] == 4'd7) - wb_rollback_pc = cr_tlb_miss_handler; - else - wb_rollback_pc = cr_trap_handler; - wb_rollback_thread_idx = dd_thread_idx; - wb_rollback_pipeline = 2'd0; - wb_trap = 1; - wb_trap_cause = dd_trap_cause; - wb_trap_pc = dd_instruction[141-:32]; - wb_trap_access_vaddr = dd_request_vaddr; - end - else if (ix_instruction_valid && ix_rollback_en) begin - wb_rollback_en = 1; - wb_rollback_pc = ix_rollback_pc; - wb_rollback_thread_idx = ix_thread_idx; - wb_rollback_pipeline = 2'd1; - if (ix_instruction[25-:3] == 3'b111) begin - wb_eret = 1; - wb_rollback_subcycle = cr_eret_subcycle[(3 - ix_thread_idx) * 4+:4]; - end - else - wb_rollback_subcycle = ix_subcycle; - end - else if (dd_instruction_valid && ((dd_rollback_en || sq_rollback_en) || ior_rollback_en)) begin - wb_rollback_en = 1; - wb_rollback_pc = dd_rollback_pc; - wb_rollback_thread_idx = dd_thread_idx; - wb_rollback_pipeline = 2'd0; - wb_rollback_subcycle = dd_subcycle; - end - end - function automatic [14:0] sv2v_cast_15; - input reg [14:0] inp; - sv2v_cast_15 = inp; - endfunction - assign wb_syscall_index = sv2v_cast_15(ix_instruction[58-:32]); - always @(*) begin - if (_sv2v_0) - ; - if (ix_instruction_valid) - wb_inst_injected = ix_instruction[109]; - else if (dd_instruction_valid) - wb_inst_injected = dd_instruction[109]; - else if (fx5_instruction_valid) - wb_inst_injected = fx5_instruction[109]; - else - wb_inst_injected = 0; - end - idx_to_oh #( - .NUM_SIGNALS(4), - .DIRECTION("LSB0") - ) idx_to_oh_thread( - .one_hot(thread_dd_oh), - .index(dd_thread_idx) - ); - assign wb_suspend_thread_oh = ((dd_suspend_thread || sq_rollback_en) || ior_rollback_en ? thread_dd_oh : 4'd0); - genvar _gv_byte_lane_2; - generate - for (_gv_byte_lane_2 = 0; _gv_byte_lane_2 < defines_CACHE_LINE_BYTES; _gv_byte_lane_2 = _gv_byte_lane_2 + 1) begin : lane_bypass_gen - localparam byte_lane = _gv_byte_lane_2; - assign bypassed_read_data[byte_lane * 8+:8] = (sq_store_bypass_mask[byte_lane] ? sq_store_bypass_data[byte_lane * 8+:8] : dd_load_data[byte_lane * 8+:8]); - end - endgenerate - assign memory_op = dd_instruction[18-:4]; - assign mem_load_lane_idx = ~dd_request_vaddr[2+:4]; - assign mem_load_lane = bypassed_read_data[mem_load_lane_idx * 32+:32]; - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dd_request_vaddr[1:0]) - 2'd0: byte_aligned = mem_load_lane[31:24]; - 2'd1: byte_aligned = mem_load_lane[23:16]; - 2'd2: byte_aligned = mem_load_lane[15:8]; - 2'd3: byte_aligned = mem_load_lane[7:0]; - default: byte_aligned = 1'sb0; - endcase - end - always @(*) begin - if (_sv2v_0) - ; - (* full_case, parallel_case *) - case (dd_request_vaddr[1]) - 1'd0: half_aligned = {mem_load_lane[23:16], mem_load_lane[31:24]}; - 1'd1: half_aligned = {mem_load_lane[7:0], mem_load_lane[15:8]}; - default: half_aligned = 1'sb0; - endcase - end - assign swapped_word_value = {mem_load_lane[7:0], mem_load_lane[15:8], mem_load_lane[23:16], mem_load_lane[31:24]}; - genvar _gv_swap_word_2; - generate - for (_gv_swap_word_2 = 0; _gv_swap_word_2 < 16; _gv_swap_word_2 = _gv_swap_word_2 + 1) begin : swap_word_gen - localparam swap_word = _gv_swap_word_2; - assign endian_twiddled_data[swap_word * 32+:8] = bypassed_read_data[(swap_word * 32) + 24+:8]; - assign endian_twiddled_data[(swap_word * 32) + 8+:8] = bypassed_read_data[(swap_word * 32) + 16+:8]; - assign endian_twiddled_data[(swap_word * 32) + 16+:8] = bypassed_read_data[(swap_word * 32) + 8+:8]; - assign endian_twiddled_data[(swap_word * 32) + 24+:8] = bypassed_read_data[swap_word * 32+:8]; - end - endgenerate - genvar _gv_mask_lane_1; - generate - for (_gv_mask_lane_1 = 0; _gv_mask_lane_1 < defines_NUM_VECTOR_LANES; _gv_mask_lane_1 = _gv_mask_lane_1 + 1) begin : compare_result_gen - localparam mask_lane = _gv_mask_lane_1; - assign scycle_vcompare_result[mask_lane] = ix_result[((defines_NUM_VECTOR_LANES - mask_lane) - 1) * 32]; - assign mcycle_vcompare_result[mask_lane] = fx5_result[((defines_NUM_VECTOR_LANES - mask_lane) - 1) * 32]; - end - endgenerate - idx_to_oh #( - .NUM_SIGNALS(defines_NUM_VECTOR_LANES), - .DIRECTION("LSB0") - ) convert_dd_lane( - .one_hot(dd_vector_lane_oh), - .index(dd_subcycle) - ); - assign last_subcycle_dd = dd_subcycle == dd_instruction[12-:4]; - assign last_subcycle_ix = ix_subcycle == ix_instruction[12-:4]; - assign last_subcycle_fx = fx5_subcycle == fx5_instruction[12-:4]; - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - always @(*) begin - if (_sv2v_0) - ; - writeback_en_nxt = 0; - writeback_thread_idx_nxt = 0; - writeback_mask_nxt = 0; - writeback_value_nxt = 0; - writeback_vector_nxt = 0; - writeback_reg_nxt = 0; - writeback_last_subcycle_nxt = 0; - if (fx5_instruction_valid) begin - if (fx5_instruction[77] && !wb_rollback_en) - writeback_en_nxt = 1; - writeback_thread_idx_nxt = fx5_thread_idx; - writeback_mask_nxt = fx5_mask_value; - if (fx5_instruction[13]) - writeback_value_nxt[0+:32] = {16'd0, mcycle_vcompare_result}; - else - writeback_value_nxt = fx5_result; - writeback_vector_nxt = fx5_instruction[76]; - writeback_reg_nxt = fx5_instruction[75-:5]; - writeback_last_subcycle_nxt = last_subcycle_fx; - end - else if (ix_instruction_valid) begin - if (ix_instruction[26] && ((ix_instruction[25-:3] == 3'b100) || (ix_instruction[25-:3] == 3'b110))) - writeback_en_nxt = 1; - else if (ix_instruction[77] && !wb_rollback_en) - writeback_en_nxt = 1; - writeback_thread_idx_nxt = ix_thread_idx; - writeback_mask_nxt = ix_mask_value; - if (ix_instruction[22]) - writeback_value_nxt[0+:32] = ix_instruction[141-:32] + 32'd4; - else if (ix_instruction[13]) - writeback_value_nxt[0+:32] = {16'd0, scycle_vcompare_result}; - else - writeback_value_nxt = ix_result; - writeback_vector_nxt = ix_instruction[76]; - writeback_reg_nxt = ix_instruction[75-:5]; - writeback_last_subcycle_nxt = last_subcycle_ix; - end - else if (dd_instruction_valid) begin - writeback_en_nxt = dd_instruction[77] && !wb_rollback_en; - writeback_thread_idx_nxt = dd_thread_idx; - if (!dd_instruction[3]) begin - if (dd_instruction[14]) - (* full_case, parallel_case *) - case (memory_op) - 4'b0000: writeback_value_nxt[0+:32] = sv2v_cast_32(byte_aligned); - 4'b0001: writeback_value_nxt[0+:32] = sv2v_cast_32($signed(byte_aligned)); - 4'b0010: writeback_value_nxt[0+:32] = sv2v_cast_32(half_aligned); - 4'b0011: writeback_value_nxt[0+:32] = sv2v_cast_32($signed(half_aligned)); - 4'b0101: writeback_value_nxt[0+:32] = swapped_word_value; - 4'b0100: - if (dd_io_access) begin - writeback_mask_nxt = {defines_NUM_VECTOR_LANES {1'b1}}; - writeback_value_nxt[0+:32] = ior_read_value; - end - else begin - writeback_mask_nxt = {defines_NUM_VECTOR_LANES {1'b1}}; - writeback_value_nxt[0+:32] = swapped_word_value; - end - 4'b0110: begin - writeback_mask_nxt = {defines_NUM_VECTOR_LANES {1'b1}}; - writeback_value_nxt[0+:32] = cr_creg_read_val; - end - 4'b0111, 4'b1000: begin - writeback_mask_nxt = dd_lane_mask; - writeback_value_nxt = endian_twiddled_data; - end - default: begin - writeback_mask_nxt = dd_vector_lane_oh & dd_lane_mask; - writeback_value_nxt = {defines_NUM_VECTOR_LANES {swapped_word_value}}; - end - endcase - else if (memory_op == 4'b0101) - writeback_value_nxt[0+:32] = sv2v_cast_32(sq_store_sync_success); - end - writeback_vector_nxt = dd_instruction[76]; - writeback_reg_nxt = dd_instruction[75-:5]; - writeback_last_subcycle_nxt = last_subcycle_dd; - end - end - always @(posedge clk) begin - wb_writeback_thread_idx <= writeback_thread_idx_nxt; - wb_writeback_mask <= writeback_mask_nxt; - wb_writeback_value <= writeback_value_nxt; - wb_writeback_vector <= writeback_vector_nxt; - wb_writeback_reg <= writeback_reg_nxt; - wb_writeback_last_subcycle <= writeback_last_subcycle_nxt; - end - always @(posedge clk or posedge reset) - if (reset) - wb_writeback_en <= 0; - else begin - if (dd_instruction_valid && !dd_instruction[3]) begin - if (dd_instruction[14]) begin - if (((((((memory_op == 4'b0000) || (memory_op == 4'b0001)) || (memory_op == 4'b0010)) || (memory_op == 4'b0011)) || (memory_op == 4'b0101)) || (memory_op == 4'b0100)) || (memory_op == 4'b0110)) - ; - end - else if (memory_op == 4'b0101) - ; - end - wb_writeback_en <= writeback_en_nxt; - wb_perf_instruction_retire <= ((fx5_instruction_valid || ix_instruction_valid) || dd_instruction_valid) && (!wb_rollback_en || ((ix_instruction_valid && ix_instruction[26]) && !ix_privileged_op_fault)); - wb_perf_store_rollback <= sq_rollback_en; - wb_perf_interrupt <= (ix_instruction_valid && ix_instruction[108]) && (ix_instruction[105-:4] == 4'd3); - end - initial _sv2v_0 = 0; -endmodule -module NyuziProcessor ( - clk, - reset, - m_aclk, - m_aresetn, - m_awaddr, - m_awlen, - m_awprot, - m_awvalid, - s_awready, - m_wdata, - m_wlast, - m_wvalid, - s_wready, - s_bvalid, - m_bready, - m_araddr, - m_arlen, - m_arprot, - m_arvalid, - s_arready, - s_rdata, - s_rvalid, - m_rready, - io_write_en, - io_read_en, - io_address, - io_write_data, - io_read_data, - jtag_tck, - jtag_trst_n, - jtag_tdi, - jtag_tms, - jtag_tdo, - interrupt_req -); - parameter signed [31:0] RESET_PC = 0; - parameter signed [31:0] NUM_INTERRUPTS = 16; - input wire clk; - input wire reset; - output wire m_aclk; - output wire m_aresetn; - localparam defines_AXI_ADDR_WIDTH = 32; - output wire [31:0] m_awaddr; - output wire [7:0] m_awlen; - output wire [2:0] m_awprot; - output wire m_awvalid; - input wire s_awready; - output wire [31:0] m_wdata; - output wire m_wlast; - output wire m_wvalid; - input wire s_wready; - input wire s_bvalid; - output wire m_bready; - output wire [31:0] m_araddr; - output wire [7:0] m_arlen; - output wire [2:0] m_arprot; - output wire m_arvalid; - input wire s_arready; - input wire [31:0] s_rdata; - input wire s_rvalid; - output wire m_rready; - output wire io_write_en; - output wire io_read_en; - output wire [31:0] io_address; - output wire [31:0] io_write_data; - input wire [31:0] io_read_data; - input wire jtag_tck; - input wire jtag_trst_n; - input wire jtag_tdi; - input wire jtag_tms; - output wire jtag_tdo; - input wire [NUM_INTERRUPTS - 1:0] interrupt_req; - generate - if (1) begin : axi_bus - wire m_aclk; - wire m_aresetn; - localparam defines_AXI_ADDR_WIDTH = 32; - reg [31:0] m_awaddr; - wire [7:0] m_awlen; - wire [2:0] m_awprot; - reg m_awvalid; - wire s_awready; - reg [31:0] m_wdata; - reg m_wlast; - reg m_wvalid; - wire s_wready; - wire s_bvalid; - wire m_bready; - reg [31:0] m_araddr; - wire [7:0] m_arlen; - wire [2:0] m_arprot; - reg m_arvalid; - wire s_arready; - wire [31:0] s_rdata; - wire s_rvalid; - reg m_rready; - end - if (1) begin : io_bus - wire write_en; - wire read_en; - wire [31:0] address; - wire [31:0] write_data; - wire [31:0] read_data; - end - if (1) begin : jtag - wire tck; - wire trst_n; - wire tdi; - reg tdo; - wire tms; - end - endgenerate - assign m_aclk = axi_bus.m_aclk; - assign m_aresetn = axi_bus.m_aresetn; - assign m_awaddr = axi_bus.m_awaddr; - assign m_awlen = axi_bus.m_awlen; - assign m_awprot = axi_bus.m_awprot; - assign m_awvalid = axi_bus.m_awvalid; - assign axi_bus.s_awready = s_awready; - assign m_wdata = axi_bus.m_wdata; - assign m_wlast = axi_bus.m_wlast; - assign m_wvalid = axi_bus.m_wvalid; - assign axi_bus.s_wready = s_wready; - assign axi_bus.s_bvalid = s_bvalid; - assign m_bready = axi_bus.m_bready; - assign m_araddr = axi_bus.m_araddr; - assign m_arlen = axi_bus.m_arlen; - assign m_arprot = axi_bus.m_arprot; - assign m_arvalid = axi_bus.m_arvalid; - assign axi_bus.s_arready = s_arready; - assign axi_bus.s_rdata = s_rdata; - assign axi_bus.s_rvalid = s_rvalid; - assign m_rready = axi_bus.m_rready; - assign io_write_en = io_bus.write_en; - assign io_read_en = io_bus.read_en; - assign io_address = io_bus.address; - assign io_write_data = io_bus.write_data; - assign io_bus.read_data = io_read_data; - assign jtag.tck = jtag_tck; - assign jtag.trst_n = jtag_trst_n; - assign jtag.tdi = jtag_tdi; - assign jtag.tms = jtag_tms; - assign jtag_tdo = jtag.tdo; - localparam _param_D9EB5_RESET_PC = RESET_PC; - localparam _param_D9EB5_NUM_INTERRUPTS = NUM_INTERRUPTS; - function automatic [6:0] sv2v_cast_7; - input reg [6:0] inp; - sv2v_cast_7 = inp; - endfunction - function automatic [31:0] sv2v_cast_32; - input reg [31:0] inp; - sv2v_cast_32 = inp; - endfunction - function automatic [3:0] sv2v_cast_4; - input reg [3:0] inp; - sv2v_cast_4 = inp; - endfunction - generate - if (1) begin : u_nyuzi - localparam RESET_PC = _param_D9EB5_RESET_PC; - localparam NUM_INTERRUPTS = _param_D9EB5_NUM_INTERRUPTS; - wire clk; - wire reset; - wire [NUM_INTERRUPTS - 1:0] interrupt_req; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - wire [611:0] l2i_request; - wire [0:0] l2i_request_valid; - wire [66:0] ior_request; - wire [0:0] ior_request_valid; - localparam defines_TOTAL_THREADS = 4; - reg [3:0] thread_en; - wire [31:0] cr_data_to_host [0:0]; - wire [31:0] data_to_host; - wire [0:0] core_injected_complete; - wire [0:0] core_injected_rollback; - wire [3:0] core_suspend_thread; - wire [3:0] core_resume_thread; - reg [3:0] thread_suspend_mask; - reg [3:0] thread_resume_mask; - wire [0:0] ii_ready; - wire [37:0] ii_response; - wire ii_response_valid; - wire [0:0] l2_ready; - wire [548:0] l2_response; - wire l2_response_valid; - wire [3:0] ocd_core; - wire [31:0] ocd_data_from_host; - wire ocd_data_update; - wire ocd_halt; - wire ocd_inject_en; - wire [31:0] ocd_inject_inst; - wire [1:0] ocd_thread; - localparam defines_CORE_ID_WIDTH = 0; - always @(*) begin - thread_suspend_mask = 1'sb0; - thread_resume_mask = 1'sb0; - begin : sv2v_autoblock_1 - reg signed [31:0] i; - for (i = 0; i < 1; i = i + 1) - begin - thread_suspend_mask = thread_suspend_mask | core_suspend_thread[i * 4+:4]; - thread_resume_mask = thread_resume_mask | core_resume_thread[i * 4+:4]; - end - end - end - always @(posedge clk or posedge reset) - if (reset) - thread_en <= 1; - else - thread_en <= (thread_en | thread_resume_mask) & ~thread_suspend_mask; - if (1) begin : l2_cache - wire clk; - wire reset; - wire [0:0] l2i_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - wire [611:0] l2i_request; - wire [0:0] l2_ready; - wire l2_response_valid; - wire [548:0] l2_response; - localparam defines_L2_PERF_EVENTS = 3; - wire [2:0] l2_perf_events; - wire [511:0] l2a_data_from_memory; - wire l2a_l2_fill; - wire [611:0] l2a_request; - wire l2a_request_valid; - wire l2a_restarted_flush; - wire l2bi_collided_miss; - wire [511:0] l2bi_data_from_memory; - wire l2bi_perf_l2_writeback; - wire [611:0] l2bi_request; - wire l2bi_request_valid; - wire l2bi_stall; - wire l2r_cache_hit; - wire [511:0] l2r_data; - wire [511:0] l2r_data_from_memory; - wire [10:0] l2r_hit_cache_idx; - wire l2r_l2_fill; - wire l2r_needs_writeback; - wire l2r_perf_l2_hit; - wire l2r_perf_l2_miss; - wire [611:0] l2r_request; - wire l2r_request_valid; - wire l2r_restarted_flush; - wire l2r_store_sync_success; - wire [7:0] l2r_update_dirty_en; - wire [7:0] l2r_update_dirty_set; - wire l2r_update_dirty_value; - wire l2r_update_lru_en; - wire [2:0] l2r_update_lru_hit_way; - wire [7:0] l2r_update_tag_en; - wire [7:0] l2r_update_tag_set; - wire l2r_update_tag_valid; - wire [17:0] l2r_update_tag_value; - wire [17:0] l2r_writeback_tag; - wire [511:0] l2t_data_from_memory; - wire [0:7] l2t_dirty; - wire [2:0] l2t_fill_way; - wire l2t_l2_fill; - wire [611:0] l2t_request; - wire l2t_request_valid; - wire l2t_restarted_flush; - wire [143:0] l2t_tag; - wire [0:7] l2t_valid; - wire [10:0] l2u_write_addr; - wire [511:0] l2u_write_data; - wire l2u_write_en; - l2_cache_arb_stage l2_cache_arb_stage( - .clk(clk), - .reset(reset), - .l2i_request_valid(l2i_request_valid), - .l2i_request(l2i_request), - .l2_ready(l2_ready), - .l2a_request_valid(l2a_request_valid), - .l2a_request(l2a_request), - .l2a_data_from_memory(l2a_data_from_memory), - .l2a_l2_fill(l2a_l2_fill), - .l2a_restarted_flush(l2a_restarted_flush), - .l2bi_request_valid(l2bi_request_valid), - .l2bi_request(l2bi_request), - .l2bi_data_from_memory(l2bi_data_from_memory), - .l2bi_stall(l2bi_stall), - .l2bi_collided_miss(l2bi_collided_miss) - ); - l2_cache_tag_stage l2_cache_tag_stage( - .clk(clk), - .reset(reset), - .l2a_request_valid(l2a_request_valid), - .l2a_request(l2a_request), - .l2a_data_from_memory(l2a_data_from_memory), - .l2a_l2_fill(l2a_l2_fill), - .l2a_restarted_flush(l2a_restarted_flush), - .l2r_update_dirty_en(l2r_update_dirty_en), - .l2r_update_dirty_set(l2r_update_dirty_set), - .l2r_update_dirty_value(l2r_update_dirty_value), - .l2r_update_tag_en(l2r_update_tag_en), - .l2r_update_tag_set(l2r_update_tag_set), - .l2r_update_tag_valid(l2r_update_tag_valid), - .l2r_update_tag_value(l2r_update_tag_value), - .l2r_update_lru_en(l2r_update_lru_en), - .l2r_update_lru_hit_way(l2r_update_lru_hit_way), - .l2t_request_valid(l2t_request_valid), - .l2t_request(l2t_request), - .l2t_valid(l2t_valid), - .l2t_tag(l2t_tag), - .l2t_dirty(l2t_dirty), - .l2t_l2_fill(l2t_l2_fill), - .l2t_fill_way(l2t_fill_way), - .l2t_data_from_memory(l2t_data_from_memory), - .l2t_restarted_flush(l2t_restarted_flush) - ); - l2_cache_read_stage l2_cache_read_stage( - .clk(clk), - .reset(reset), - .l2t_request_valid(l2t_request_valid), - .l2t_request(l2t_request), - .l2t_valid(l2t_valid), - .l2t_tag(l2t_tag), - .l2t_dirty(l2t_dirty), - .l2t_l2_fill(l2t_l2_fill), - .l2t_restarted_flush(l2t_restarted_flush), - .l2t_fill_way(l2t_fill_way), - .l2t_data_from_memory(l2t_data_from_memory), - .l2r_update_dirty_en(l2r_update_dirty_en), - .l2r_update_dirty_set(l2r_update_dirty_set), - .l2r_update_dirty_value(l2r_update_dirty_value), - .l2r_update_tag_en(l2r_update_tag_en), - .l2r_update_tag_set(l2r_update_tag_set), - .l2r_update_tag_valid(l2r_update_tag_valid), - .l2r_update_tag_value(l2r_update_tag_value), - .l2r_update_lru_en(l2r_update_lru_en), - .l2r_update_lru_hit_way(l2r_update_lru_hit_way), - .l2u_write_en(l2u_write_en), - .l2u_write_addr(l2u_write_addr), - .l2u_write_data(l2u_write_data), - .l2r_request_valid(l2r_request_valid), - .l2r_request(l2r_request), - .l2r_data(l2r_data), - .l2r_cache_hit(l2r_cache_hit), - .l2r_hit_cache_idx(l2r_hit_cache_idx), - .l2r_l2_fill(l2r_l2_fill), - .l2r_restarted_flush(l2r_restarted_flush), - .l2r_data_from_memory(l2r_data_from_memory), - .l2r_store_sync_success(l2r_store_sync_success), - .l2r_writeback_tag(l2r_writeback_tag), - .l2r_needs_writeback(l2r_needs_writeback), - .l2r_perf_l2_miss(l2r_perf_l2_miss), - .l2r_perf_l2_hit(l2r_perf_l2_hit) - ); - l2_cache_update_stage l2_cache_update_stage( - .clk(clk), - .reset(reset), - .l2r_request_valid(l2r_request_valid), - .l2r_request(l2r_request), - .l2r_data(l2r_data), - .l2r_cache_hit(l2r_cache_hit), - .l2r_hit_cache_idx(l2r_hit_cache_idx), - .l2r_l2_fill(l2r_l2_fill), - .l2r_restarted_flush(l2r_restarted_flush), - .l2r_data_from_memory(l2r_data_from_memory), - .l2r_store_sync_success(l2r_store_sync_success), - .l2r_needs_writeback(l2r_needs_writeback), - .l2u_write_en(l2u_write_en), - .l2u_write_addr(l2u_write_addr), - .l2u_write_data(l2u_write_data), - .l2_response_valid(l2_response_valid), - .l2_response(l2_response) - ); - if (1) begin : l2_axi_bus_interface - reg _sv2v_0; - wire clk; - wire reset; - reg l2bi_request_valid; - localparam defines_NUM_VECTOR_LANES = 16; - localparam defines_CACHE_LINE_BYTES = 64; - localparam defines_CACHE_LINE_BITS = 512; - localparam defines_CACHE_LINE_OFFSET_WIDTH = 6; - reg [611:0] l2bi_request; - wire [511:0] l2bi_data_from_memory; - wire l2bi_stall; - wire l2bi_collided_miss; - wire l2r_needs_writeback; - wire [17:0] l2r_writeback_tag; - wire [511:0] l2r_data; - wire l2r_l2_fill; - wire l2r_restarted_flush; - wire l2r_cache_hit; - wire l2r_request_valid; - wire [611:0] l2r_request; - reg l2bi_perf_l2_writeback; - localparam FIFO_SIZE = 8; - localparam L2REQ_LATENCY = 4; - localparam BURST_BEATS = 16; - localparam BURST_OFFSET_WIDTH = 4; - wire [25:0] miss_addr; - wire [25:0] writeback_address; - wire enqueue_writeback_request; - wire enqueue_fill_request; - wire duplicate_request; - wire [511:0] writeback_data; - wire [31:0] writeback_lanes [0:15]; - wire writeback_fifo_empty; - wire fill_queue_empty; - wire fill_request_pending; - wire writeback_pending; - reg writeback_complete; - wire writeback_fifo_almost_full; - wire fill_queue_almost_full; - reg [31:0] state_ff; - reg [31:0] state_nxt; - reg [3:0] burst_offset_ff; - reg [3:0] burst_offset_nxt; - reg [31:0] fill_buffer [0:15]; - reg restart_flush_request; - reg fill_dequeue_en; - wire [611:0] lmq_out_request; - wire [544:0] writeback_fifo_in; - wire [544:0] writeback_fifo_out; - assign miss_addr = l2r_request[601-:26]; - assign enqueue_writeback_request = (l2r_request_valid && l2r_needs_writeback) && ((((l2r_request[605-:3] == 3'd4) && l2r_cache_hit) && !l2r_restarted_flush) || l2r_l2_fill); - assign enqueue_fill_request = ((l2r_request_valid && !l2r_cache_hit) && !l2r_l2_fill) && ((((l2r_request[605-:3] == 3'd0) || (l2r_request[605-:3] == 3'd2)) || (l2r_request[605-:3] == 3'd1)) || (l2r_request[605-:3] == 3'd3)); - assign writeback_pending = !writeback_fifo_empty; - assign fill_request_pending = !fill_queue_empty; - l2_cache_pending_miss_cam l2_cache_pending_miss_cam( - .request_valid(l2r_request_valid), - .request_addr({miss_addr[25-:18], miss_addr[7-:8]}), - .clk(clk), - .reset(reset), - .enqueue_fill_request(enqueue_fill_request), - .l2r_l2_fill(l2r_l2_fill), - .duplicate_request(duplicate_request) - ); - assign writeback_fifo_in[544-:26] = {l2r_writeback_tag, miss_addr[7-:8]}; - assign writeback_fifo_in[518-:512] = l2r_data; - assign writeback_fifo_in[6] = l2r_request[605-:3] == 3'd4; - assign writeback_fifo_in[5-:4] = l2r_request[611-:4]; - assign writeback_fifo_in[1-:2] = l2r_request[607-:2]; - sync_fifo #( - .WIDTH(545), - .SIZE(FIFO_SIZE), - .ALMOST_FULL_THRESHOLD(4) - ) pending_writeback_fifo( - .clk(clk), - .reset(reset), - .flush_en(1'b0), - .almost_full(writeback_fifo_almost_full), - .enqueue_en(enqueue_writeback_request), - .enqueue_value(writeback_fifo_in), - .almost_empty(), - .empty(writeback_fifo_empty), - .dequeue_en(writeback_complete), - .dequeue_value(writeback_fifo_out), - .full() - ); - assign writeback_address = writeback_fifo_out[544-:26]; - assign writeback_data = writeback_fifo_out[518-:512]; - sync_fifo #( - .WIDTH(613), - .SIZE(FIFO_SIZE), - .ALMOST_FULL_THRESHOLD(4) - ) pending_fill_fifo( - .clk(clk), - .reset(reset), - .flush_en(1'b0), - .almost_full(fill_queue_almost_full), - .enqueue_en(enqueue_fill_request), - .enqueue_value({duplicate_request, l2r_request}), - .empty(fill_queue_empty), - .almost_empty(), - .dequeue_en(fill_dequeue_en), - .dequeue_value({l2bi_collided_miss, lmq_out_request}), - .full() - ); - assign l2bi_stall = fill_queue_almost_full || writeback_fifo_almost_full; - assign NyuziProcessor.axi_bus.m_awlen = 8'sd15; - assign NyuziProcessor.axi_bus.m_arlen = 8'sd15; - assign NyuziProcessor.axi_bus.m_bready = 1'b1; - assign NyuziProcessor.axi_bus.m_awprot = 3'b000; - assign NyuziProcessor.axi_bus.m_arprot = 3'b000; - assign NyuziProcessor.axi_bus.m_aclk = clk; - assign NyuziProcessor.axi_bus.m_aresetn = !reset; - genvar _gv_fill_buffer_idx_1; - for (_gv_fill_buffer_idx_1 = 0; _gv_fill_buffer_idx_1 < BURST_BEATS; _gv_fill_buffer_idx_1 = _gv_fill_buffer_idx_1 + 1) begin : mem_lane_gen - localparam fill_buffer_idx = _gv_fill_buffer_idx_1; - assign l2bi_data_from_memory[fill_buffer_idx * 32+:32] = fill_buffer[(BURST_BEATS - fill_buffer_idx) - 1]; - end - reg wait_axi_write_response; - always @(*) begin - if (_sv2v_0) - ; - state_nxt = state_ff; - fill_dequeue_en = 0; - burst_offset_nxt = burst_offset_ff; - writeback_complete = 0; - restart_flush_request = 0; - (* full_case, parallel_case *) - case (state_ff) - 32'd0: - if (writeback_pending) begin - if (!wait_axi_write_response) - state_nxt = 32'd1; - end - else if (fill_request_pending) begin - if (l2bi_collided_miss || ((lmq_out_request[575-:64] == {defines_CACHE_LINE_BYTES {1'b1}}) && (lmq_out_request[605-:3] == 3'd2))) - state_nxt = 32'd5; - else - state_nxt = 32'd3; - end - 32'd1: begin - burst_offset_nxt = 0; - if (NyuziProcessor.axi_bus.s_awready) - state_nxt = 32'd2; - end - 32'd2: - if (NyuziProcessor.axi_bus.s_wready) begin - if (burst_offset_ff == {BURST_OFFSET_WIDTH {1'b1}}) begin - writeback_complete = 1; - restart_flush_request = writeback_fifo_out[6]; - state_nxt = 32'd0; - end - burst_offset_nxt = burst_offset_ff + 4'sd1; - end - 32'd3: begin - burst_offset_nxt = 0; - if (NyuziProcessor.axi_bus.s_arready) - state_nxt = 32'd4; - end - 32'd4: - if (NyuziProcessor.axi_bus.s_rvalid) begin - if (burst_offset_ff == {BURST_OFFSET_WIDTH {1'b1}}) - state_nxt = 32'd5; - burst_offset_nxt = burst_offset_ff + 4'sd1; - end - 32'd5: begin - state_nxt = 32'd0; - fill_dequeue_en = 1'b1; - end - endcase - end - genvar _gv_writeback_lane_1; - for (_gv_writeback_lane_1 = 0; _gv_writeback_lane_1 < BURST_BEATS; _gv_writeback_lane_1 = _gv_writeback_lane_1 + 1) begin : writeback_lane_gen - localparam writeback_lane = _gv_writeback_lane_1; - assign writeback_lanes[writeback_lane] = writeback_data[writeback_lane * 32+:32]; - end - always @(*) begin - if (_sv2v_0) - ; - l2bi_request = lmq_out_request; - if (restart_flush_request) begin - l2bi_request_valid = 1'b1; - l2bi_request[605-:3] = 3'd4; - l2bi_request[611-:4] = writeback_fifo_out[5-:4]; - l2bi_request[607-:2] = writeback_fifo_out[1-:2]; - l2bi_request[602] = 1'd1; - end - else - l2bi_request_valid = fill_dequeue_en; - end - always @(posedge clk or posedge reset) begin : update - if (reset) begin - state_ff <= 32'd0; - NyuziProcessor.axi_bus.m_arvalid <= 1'sb0; - NyuziProcessor.axi_bus.m_awvalid <= 1'sb0; - NyuziProcessor.axi_bus.m_rready <= 1'sb0; - NyuziProcessor.axi_bus.m_wlast <= 1'sb0; - NyuziProcessor.axi_bus.m_wvalid <= 1'sb0; - burst_offset_ff <= 1'sb0; - l2bi_perf_l2_writeback <= 1'sb0; - wait_axi_write_response <= 1'sb0; - end - else begin - state_ff <= state_nxt; - burst_offset_ff <= burst_offset_nxt; - if (state_ff == 32'd1) - wait_axi_write_response <= 1; - else if (NyuziProcessor.axi_bus.s_bvalid) - wait_axi_write_response <= 0; - NyuziProcessor.axi_bus.m_arvalid <= state_nxt == 32'd3; - NyuziProcessor.axi_bus.m_rready <= state_nxt == 32'd4; - NyuziProcessor.axi_bus.m_awvalid <= state_nxt == 32'd1; - NyuziProcessor.axi_bus.m_wvalid <= state_nxt == 32'd2; - NyuziProcessor.axi_bus.m_wlast <= (state_nxt == 32'd2) && (burst_offset_nxt == 4'sd15); - l2bi_perf_l2_writeback <= enqueue_writeback_request && !writeback_fifo_almost_full; - end - end - always @(posedge clk) begin - if ((state_ff == 32'd4) && NyuziProcessor.axi_bus.s_rvalid) - fill_buffer[burst_offset_ff] <= NyuziProcessor.axi_bus.s_rdata; - NyuziProcessor.axi_bus.m_araddr <= {l2bi_request[601-:26], {defines_CACHE_LINE_OFFSET_WIDTH {1'b0}}}; - NyuziProcessor.axi_bus.m_awaddr <= {writeback_address, {defines_CACHE_LINE_OFFSET_WIDTH {1'b0}}}; - NyuziProcessor.axi_bus.m_wdata <= writeback_lanes[~burst_offset_nxt]; - end - initial _sv2v_0 = 0; - end - assign l2_axi_bus_interface.clk = clk; - assign l2_axi_bus_interface.reset = reset; - assign l2bi_request_valid = l2_axi_bus_interface.l2bi_request_valid; - assign l2bi_request = l2_axi_bus_interface.l2bi_request; - assign l2bi_data_from_memory = l2_axi_bus_interface.l2bi_data_from_memory; - assign l2bi_stall = l2_axi_bus_interface.l2bi_stall; - assign l2bi_collided_miss = l2_axi_bus_interface.l2bi_collided_miss; - assign l2_axi_bus_interface.l2r_needs_writeback = l2r_needs_writeback; - assign l2_axi_bus_interface.l2r_writeback_tag = l2r_writeback_tag; - assign l2_axi_bus_interface.l2r_data = l2r_data; - assign l2_axi_bus_interface.l2r_l2_fill = l2r_l2_fill; - assign l2_axi_bus_interface.l2r_restarted_flush = l2r_restarted_flush; - assign l2_axi_bus_interface.l2r_cache_hit = l2r_cache_hit; - assign l2_axi_bus_interface.l2r_request_valid = l2r_request_valid; - assign l2_axi_bus_interface.l2r_request = l2r_request; - assign l2bi_perf_l2_writeback = l2_axi_bus_interface.l2bi_perf_l2_writeback; - assign l2_perf_events = {l2r_perf_l2_hit, l2r_perf_l2_miss, l2bi_perf_l2_writeback}; - end - assign l2_cache.clk = clk; - assign l2_cache.reset = reset; - assign l2_cache.l2i_request_valid = l2i_request_valid; - assign l2_cache.l2i_request = l2i_request; - assign l2_ready = l2_cache.l2_ready; - assign l2_response_valid = l2_cache.l2_response_valid; - assign l2_response = l2_cache.l2_response; - if (1) begin : io_interconnect - wire clk; - wire reset; - wire [0:0] ior_request_valid; - wire [66:0] ior_request; - wire [0:0] ii_ready; - reg ii_response_valid; - reg [37:0] ii_response; - wire [3:0] grant_idx; - wire [0:0] grant_oh; - reg request_sent; - reg [3:0] request_core; - reg [1:0] request_thread_idx; - wire [66:0] grant_request; - genvar _gv_request_idx_1; - for (_gv_request_idx_1 = 0; _gv_request_idx_1 < 1; _gv_request_idx_1 = _gv_request_idx_1 + 1) begin : handshake_gen - localparam request_idx = _gv_request_idx_1; - assign ii_ready[request_idx] = grant_oh[request_idx]; - end - genvar _gv_grant_idx_bit_1; - localparam defines_CORE_ID_WIDTH = 0; - if (1) begin : genblk2 - assign grant_oh[0] = ior_request_valid[0]; - assign grant_idx = 0; - assign grant_request = ior_request[0+:67]; - end - assign NyuziProcessor.io_bus.write_en = |grant_oh && grant_request[66]; - assign NyuziProcessor.io_bus.read_en = |grant_oh && !grant_request[66]; - assign NyuziProcessor.io_bus.write_data = grant_request[31-:32]; - assign NyuziProcessor.io_bus.address = grant_request[63-:32]; - always @(posedge clk) begin - ii_response[37-:4] <= request_core; - ii_response[33-:2] <= request_thread_idx; - ii_response[31-:32] <= NyuziProcessor.io_bus.read_data; - if (|ior_request_valid) begin - request_core <= grant_idx; - request_thread_idx <= grant_request[65-:2]; - end - end - always @(posedge clk or posedge reset) - if (reset) begin - ii_response_valid <= 1'sb0; - request_sent <= 1'sb0; - end - else begin - request_sent <= |ior_request_valid; - ii_response_valid <= request_sent; - end - end - assign io_interconnect.clk = clk; - assign io_interconnect.reset = reset; - assign io_interconnect.ior_request_valid = ior_request_valid; - assign io_interconnect.ior_request = ior_request; - assign ii_ready = io_interconnect.ii_ready; - assign ii_response_valid = io_interconnect.ii_response_valid; - assign ii_response = io_interconnect.ii_response; - if (1) begin : on_chip_debugger - wire clk; - wire reset; - wire ocd_halt; - wire [1:0] ocd_thread; - wire [3:0] ocd_core; - reg [31:0] ocd_inject_inst; - wire ocd_inject_en; - wire [31:0] ocd_data_from_host; - wire ocd_data_update; - wire [31:0] data_to_host; - wire injected_complete; - wire injected_rollback; - localparam JTAG_IDCODE = 32'h4d20dffb; - wire data_shift_val; - reg [31:0] data_shift_reg; - reg [6:0] control; - reg [1:0] machine_inst_status; - wire capture_dr; - wire [3:0] jtag_instruction; - wire shift_dr; - wire update_dr; - wire update_ir; - assign ocd_halt = control[0]; - assign ocd_thread = control[2-:2]; - assign ocd_core = control[6-:4]; - localparam _param_C3F75_INSTRUCTION_WIDTH = 4; - if (1) begin : jtag_tap_controller - reg _sv2v_0; - localparam INSTRUCTION_WIDTH = _param_C3F75_INSTRUCTION_WIDTH; - wire clk; - wire reset; - wire data_shift_val; - wire capture_dr; - wire shift_dr; - wire update_dr; - reg [3:0] jtag_instruction; - wire update_ir; - reg signed [31:0] state_ff; - reg signed [31:0] state_nxt; - reg last_tck; - wire tck_rising_edge; - wire tck_falling_edge; - wire tck_sync; - wire tms_sync; - wire tdi_sync; - wire trst_sync_n; - always @(*) begin - if (_sv2v_0) - ; - state_nxt = state_ff; - (* full_case, parallel_case *) - case (state_ff) - 32'sd1: - if (tms_sync) - state_nxt = 32'sd2; - 32'sd2: - if (tms_sync) - state_nxt = 32'sd9; - else - state_nxt = 32'sd3; - 32'sd3: - if (tms_sync) - state_nxt = 32'sd5; - else - state_nxt = 32'sd4; - 32'sd4: - if (tms_sync) - state_nxt = 32'sd5; - 32'sd5: - if (tms_sync) - state_nxt = 32'sd8; - else - state_nxt = 32'sd6; - 32'sd6: - if (tms_sync) - state_nxt = 32'sd7; - 32'sd7: - if (tms_sync) - state_nxt = 32'sd8; - else - state_nxt = 32'sd4; - 32'sd8: state_nxt = 32'sd1; - 32'sd9: - if (tms_sync) - state_nxt = 32'sd1; - else - state_nxt = 32'sd10; - 32'sd10: - if (tms_sync) - state_nxt = 32'sd12; - else - state_nxt = 32'sd11; - 32'sd11: - if (tms_sync) - state_nxt = 32'sd12; - 32'sd12: - if (tms_sync) - state_nxt = 32'sd15; - else - state_nxt = 32'sd13; - 32'sd13: - if (tms_sync) - state_nxt = 32'sd14; - 32'sd14: - if (tms_sync) - state_nxt = 32'sd15; - else - state_nxt = 32'sd11; - 32'sd15: - if (tms_sync) - state_nxt = 32'sd2; - else - state_nxt = 32'sd1; - 32'sd0: - if (!tms_sync) - state_nxt = 32'sd1; - default: state_nxt = 32'sd0; - endcase - end - synchronizer #(.WIDTH(4)) synchronizer( - .data_i({NyuziProcessor.jtag.tck, NyuziProcessor.jtag.tms, NyuziProcessor.jtag.tdi, NyuziProcessor.jtag.trst_n}), - .data_o({tck_sync, tms_sync, tdi_sync, trst_sync_n}), - .clk(clk), - .reset(reset) - ); - assign tck_rising_edge = !last_tck && tck_sync; - assign tck_falling_edge = last_tck && !tck_sync; - assign update_ir = (state_ff == 32'sd15) && tck_rising_edge; - assign capture_dr = (state_ff == 32'sd3) && tck_rising_edge; - assign shift_dr = (state_ff == 32'sd4) && tck_rising_edge; - assign update_dr = (state_ff == 32'sd8) && tck_rising_edge; - always @(posedge clk or posedge reset) - if (reset) begin - state_ff <= 32'sd0; - NyuziProcessor.jtag.tdo <= 1'sb0; - jtag_instruction <= 1'sb0; - last_tck <= 1'sb0; - end - else if (!trst_sync_n) - state_ff <= 32'sd0; - else begin - if (state_ff == 32'sd0) - jtag_instruction <= 1'sb0; - last_tck <= tck_sync; - if (tck_rising_edge) begin - state_ff <= state_nxt; - if (state_ff == 32'sd11) - jtag_instruction <= {tdi_sync, jtag_instruction[3:1]}; - end - else if (tck_falling_edge) - NyuziProcessor.jtag.tdo <= (state_ff == 32'sd11 ? jtag_instruction[0] : data_shift_val); - end - initial _sv2v_0 = 0; - end - assign jtag_tap_controller.clk = clk; - assign jtag_tap_controller.reset = reset; - assign jtag_tap_controller.data_shift_val = data_shift_val; - assign capture_dr = jtag_tap_controller.capture_dr; - assign shift_dr = jtag_tap_controller.shift_dr; - assign update_dr = jtag_tap_controller.update_dr; - assign jtag_instruction = jtag_tap_controller.jtag_instruction; - assign update_ir = jtag_tap_controller.update_ir; - assign data_shift_val = data_shift_reg[0]; - assign ocd_inject_en = update_dr && (jtag_instruction == 4'd4); - always @(posedge clk or posedge reset) - if (reset) begin - control <= 1'sb0; - machine_inst_status <= 2'd0; - end - else begin - if (update_dr && (jtag_instruction == 4'd3)) - control <= sv2v_cast_7(data_shift_reg); - if (injected_rollback) - machine_inst_status <= 2'd2; - else if (injected_complete) - machine_inst_status <= 2'd0; - else if (update_dr && (jtag_instruction == 4'd4)) - machine_inst_status <= 2'd1; - end - assign ocd_data_from_host = data_shift_reg; - assign ocd_data_update = update_dr && (jtag_instruction == 4'd5); - always @(posedge clk) - if (capture_dr) - (* full_case, parallel_case *) - case (jtag_instruction) - 4'd0: data_shift_reg <= JTAG_IDCODE; - 4'd3: data_shift_reg <= sv2v_cast_32(control); - 4'd5: data_shift_reg <= data_to_host; - 4'd6: data_shift_reg <= sv2v_cast_32(machine_inst_status); - default: data_shift_reg <= 1'sb0; - endcase - else if (shift_dr) - (* full_case, parallel_case *) - case (jtag_instruction) - 4'd15: data_shift_reg <= sv2v_cast_32(NyuziProcessor.jtag.tdi); - 4'd3: data_shift_reg <= sv2v_cast_32({NyuziProcessor.jtag.tdi, data_shift_reg[6:1]}); - 4'd6: data_shift_reg <= sv2v_cast_32({NyuziProcessor.jtag.tdi, data_shift_reg[1:1]}); - default: data_shift_reg <= sv2v_cast_32({NyuziProcessor.jtag.tdi, data_shift_reg[31:1]}); - endcase - else if (update_dr) begin - if (jtag_instruction == 4'd4) - ocd_inject_inst <= data_shift_reg; - end - end - assign on_chip_debugger.injected_complete = |core_injected_complete; - assign on_chip_debugger.injected_rollback = |core_injected_rollback; - assign on_chip_debugger.clk = clk; - assign on_chip_debugger.reset = reset; - assign ocd_halt = on_chip_debugger.ocd_halt; - assign ocd_thread = on_chip_debugger.ocd_thread; - assign ocd_core = on_chip_debugger.ocd_core; - assign ocd_inject_inst = on_chip_debugger.ocd_inject_inst; - assign ocd_inject_en = on_chip_debugger.ocd_inject_en; - assign ocd_data_from_host = on_chip_debugger.ocd_data_from_host; - assign ocd_data_update = on_chip_debugger.ocd_data_update; - assign on_chip_debugger.data_to_host = data_to_host; - if (1) begin : genblk1 - assign data_to_host = cr_data_to_host[0]; - end - genvar _gv_core_idx_1; - for (_gv_core_idx_1 = 0; _gv_core_idx_1 < 1; _gv_core_idx_1 = _gv_core_idx_1 + 1) begin : core_gen - localparam core_idx = _gv_core_idx_1; - core #( - .CORE_ID(sv2v_cast_4(core_idx)), - .NUM_INTERRUPTS(NUM_INTERRUPTS), - .RESET_PC(RESET_PC) - ) core( - .l2i_request_valid(l2i_request_valid[core_idx]), - .l2i_request(l2i_request[core_idx * 612+:612]), - .l2_ready(l2_ready[core_idx]), - .thread_en(thread_en[core_idx * 4+:4]), - .ior_request_valid(ior_request_valid[core_idx]), - .ior_request(ior_request[core_idx * 67+:67]), - .ii_ready(ii_ready[core_idx]), - .ii_response(ii_response), - .cr_data_to_host(cr_data_to_host[core_idx]), - .injected_complete(core_injected_complete[core_idx]), - .injected_rollback(core_injected_rollback[core_idx]), - .cr_suspend_thread(core_suspend_thread[core_idx * 4+:4]), - .cr_resume_thread(core_resume_thread[core_idx * 4+:4]), - .clk(clk), - .reset(reset), - .interrupt_req(interrupt_req), - .l2_response_valid(l2_response_valid), - .l2_response(l2_response), - .ii_response_valid(ii_response_valid), - .ocd_halt(ocd_halt), - .ocd_thread(ocd_thread), - .ocd_core(ocd_core), - .ocd_inject_inst(ocd_inject_inst), - .ocd_inject_en(ocd_inject_en), - .ocd_data_from_host(ocd_data_from_host), - .ocd_data_update(ocd_data_update) - ); - end - end - endgenerate - assign u_nyuzi.clk = clk; - assign u_nyuzi.reset = reset; - assign u_nyuzi.interrupt_req = interrupt_req; -endmodule \ No newline at end of file diff --git a/designs/src/NyuziProcessor/dev/nyuziTop.sv b/designs/src/NyuziProcessor/dev/nyuziTop.sv deleted file mode 100644 index ef7e0f6..0000000 --- a/designs/src/NyuziProcessor/dev/nyuziTop.sv +++ /dev/null @@ -1,124 +0,0 @@ -`include "repo/hardware/core/defines.svh" -import defines::*; - -module NyuziProcessor #( - parameter int RESET_PC = 0, - parameter int NUM_INTERRUPTS = 16 -)( - input logic clk, - input logic reset, - - // Global - output logic m_aclk, - output logic m_aresetn, - - // Write address - output logic [AXI_ADDR_WIDTH-1:0] m_awaddr, - output logic [7:0] m_awlen, - output logic [2:0] m_awprot, - output logic m_awvalid, - input logic s_awready, - - // Write data - output logic [`AXI_DATA_WIDTH-1:0] m_wdata, - output logic m_wlast, - output logic m_wvalid, - input logic s_wready, - - // Write response - input logic s_bvalid, - output logic m_bready, - - // Read address - output logic [AXI_ADDR_WIDTH-1:0] m_araddr, - output logic [7:0] m_arlen, - output logic [2:0] m_arprot, - output logic m_arvalid, - input logic s_arready, - - // Read data - input logic [`AXI_DATA_WIDTH-1:0] s_rdata, - input logic s_rvalid, - output logic m_rready, - - output logic io_write_en, - output logic io_read_en, - output scalar_t io_address, - output scalar_t io_write_data, - input scalar_t io_read_data, - - input logic jtag_tck, - input logic jtag_trst_n, - input logic jtag_tdi, - input logic jtag_tms, - output logic jtag_tdo, - - - input logic [NUM_INTERRUPTS-1:0] interrupt_req -); - - // Interface - axi4_interface axi_bus(); - io_bus_interface io_bus(); - jtag_interface jtag(); - - - // Global - assign m_aclk = axi_bus.m_aclk; - assign m_aresetn = axi_bus.m_aresetn; - - // Write address - assign m_awaddr = axi_bus.m_awaddr; - assign m_awlen = axi_bus.m_awlen; - assign m_awprot = axi_bus.m_awprot; - assign m_awvalid = axi_bus.m_awvalid; - assign axi_bus.s_awready = s_awready; - - // Write data - assign m_wdata = axi_bus.m_wdata; - assign m_wlast = axi_bus.m_wlast; - assign m_wvalid = axi_bus.m_wvalid; - assign axi_bus.s_wready = s_wready; - - // Write response - assign axi_bus.s_bvalid = s_bvalid; - assign m_bready = axi_bus.m_bready; - - // Read address - assign m_araddr = axi_bus.m_araddr; - assign m_arlen = axi_bus.m_arlen; - assign m_arprot = axi_bus.m_arprot; - assign m_arvalid = axi_bus.m_arvalid; - assign axi_bus.s_arready = s_arready; - - // Read data - assign axi_bus.s_rdata = s_rdata; - assign axi_bus.s_rvalid = s_rvalid; - assign m_rready = axi_bus.m_rready; - - assign io_write_en = io_bus.write_en; - assign io_read_en = io_bus.read_en; - assign io_address = io_bus.address; - assign io_write_data = io_bus.write_data; - assign io_bus.read_data = io_read_data; - - - assign jtag.tck = jtag_tck; - assign jtag.trst_n = jtag_trst_n; - assign jtag.tdi = jtag_tdi; - assign jtag.tms = jtag_tms; - assign jtag_tdo = jtag.tdo; - - nyuzi #( - .RESET_PC(RESET_PC), - .NUM_INTERRUPTS(NUM_INTERRUPTS) - ) u_nyuzi ( - .clk (clk), - .reset (reset), - .axi_bus (axi_bus.master), - .io_bus (io_bus.master), - .jtag (jtag.target), - .interrupt_req(interrupt_req) - ); - -endmodule \ No newline at end of file diff --git a/designs/src/NyuziProcessor/dev/patch-all.patch b/designs/src/NyuziProcessor/dev/patch-all.patch deleted file mode 100644 index c0ac378..0000000 --- a/designs/src/NyuziProcessor/dev/patch-all.patch +++ /dev/null @@ -1,266 +0,0 @@ ---- cache_lru.sv 2025-07-09 22:39:35.321468016 +0000 -+++ cache_lru_fix.sv 2025-07-09 22:41:13.034912461 +0000 -@@ -112,7 +112,7 @@ - // be evicted. A strict LRU would take three cycles for the node to move to the - // LRU. So, this is close enough to LRU to work well, but much simpler to implement. - // -- sram_1r1w #( -+ fakeram_1r1w_3x1 #( - .DATA_WIDTH(LRU_FLAG_BITS), - .SIZE(NUM_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- dcache_data_stage.sv 2025-07-09 22:42:54.320385140 +0000 -+++ dcache_data_stage_fix.sv 2025-07-09 22:42:52.093373519 +0000 -@@ -472,7 +472,7 @@ - .one_hot(way_hit_oh), - .index(way_hit_idx)); - -- sram_1r1w #( -+ fakeram_1r1w_512x256 #( - .DATA_WIDTH(CACHE_LINE_BITS), - .SIZE(`L1D_WAYS * `L1D_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- dcache_tag_stage.sv 2025-07-09 22:44:07.942766681 +0000 -+++ dcache_tag_stage_fix.sv 2025-07-09 22:43:50.793678251 +0000 -@@ -177,7 +177,7 @@ - // to all be cleared on reset. - logic line_valid[`L1D_SETS]; - -- sram_2r1w #( -+ fakeram_2r1w_20x64 #( - .DATA_WIDTH($bits(l1d_tag_t)), - .SIZE(`L1D_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- ifetch_data_stage.sv 2025-07-09 22:14:25.832128443 +0000 -+++ ifetch_data_stage_fix.sv 2025-07-09 22:16:31.971567357 +0000 -@@ -152,7 +152,7 @@ - // - // Cache data - // -- sram_1r1w #( -+ fakeram_1r1w_512x256 #( - .DATA_WIDTH(CACHE_LINE_BITS), - .SIZE(`L1I_WAYS * `L1I_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- ifetch_tag_stage.sv 2025-07-09 22:50:10.217586731 +0000 -+++ ifetch_tag_stage_fix.sv 2025-07-09 22:49:59.507533958 +0000 -@@ -179,7 +179,7 @@ - // to simultaneously be cleared on reset. - logic line_valid[`L1I_SETS]; - -- sram_1r1w #( -+ fakeram_1r1w_20x64 #( - .DATA_WIDTH($bits(l1i_tag_t)), - .SIZE(`L1I_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- int_execute_stage.sv 2025-07-09 01:05:59.672070430 +0000 -+++ int_execute_stage_fix.sv 2025-07-09 19:58:46.419523214 +0000 -@@ -101,87 +101,40 @@ - assign zero = difference == 0; - assign signed_gtr = overflow == negative; - -- // Count leading zeroes -- always_comb -- begin -- unique casez (lane_operand2) -- 32'b1???????????????????????????????: lz = 0; -- 32'b01??????????????????????????????: lz = 1; -- 32'b001?????????????????????????????: lz = 2; -- 32'b0001????????????????????????????: lz = 3; -- 32'b00001???????????????????????????: lz = 4; -- 32'b000001??????????????????????????: lz = 5; -- 32'b0000001?????????????????????????: lz = 6; -- 32'b00000001????????????????????????: lz = 7; -- 32'b000000001???????????????????????: lz = 8; -- 32'b0000000001??????????????????????: lz = 9; -- 32'b00000000001?????????????????????: lz = 10; -- 32'b000000000001????????????????????: lz = 11; -- 32'b0000000000001???????????????????: lz = 12; -- 32'b00000000000001??????????????????: lz = 13; -- 32'b000000000000001?????????????????: lz = 14; -- 32'b0000000000000001????????????????: lz = 15; -- 32'b00000000000000001???????????????: lz = 16; -- 32'b000000000000000001??????????????: lz = 17; -- 32'b0000000000000000001?????????????: lz = 18; -- 32'b00000000000000000001????????????: lz = 19; -- 32'b000000000000000000001???????????: lz = 20; -- 32'b0000000000000000000001??????????: lz = 21; -- 32'b00000000000000000000001?????????: lz = 22; -- 32'b000000000000000000000001????????: lz = 23; -- 32'b0000000000000000000000001???????: lz = 24; -- 32'b00000000000000000000000001??????: lz = 25; -- 32'b000000000000000000000000001?????: lz = 26; -- 32'b0000000000000000000000000001????: lz = 27; -- 32'b00000000000000000000000000001???: lz = 28; -- 32'b000000000000000000000000000001??: lz = 29; -- 32'b0000000000000000000000000000001?: lz = 30; -- 32'b00000000000000000000000000000001: lz = 31; -- 32'b00000000000000000000000000000000: lz = 32; -- default: lz = 0; -- endcase -- end -+ function automatic [5:0] count_lz; -+ input [31:0] val; -+ integer i; -+ reg found; -+ begin -+ count_lz = 32; -+ found = 0; -+ for (i = 31; i >= 0; i = i - 1) begin -+ if (!found && val[i]) begin -+ count_lz = 31 - i; -+ found = 1; -+ end -+ end -+ end -+ endfunction - -- // Count trailing zeroes -- always_comb -- begin -- unique casez (lane_operand2) -- 32'b00000000000000000000000000000000: tz = 32; -- 32'b10000000000000000000000000000000: tz = 31; -- 32'b?1000000000000000000000000000000: tz = 30; -- 32'b??100000000000000000000000000000: tz = 29; -- 32'b???10000000000000000000000000000: tz = 28; -- 32'b????1000000000000000000000000000: tz = 27; -- 32'b?????100000000000000000000000000: tz = 26; -- 32'b??????10000000000000000000000000: tz = 25; -- 32'b???????1000000000000000000000000: tz = 24; -- 32'b????????100000000000000000000000: tz = 23; -- 32'b?????????10000000000000000000000: tz = 22; -- 32'b??????????1000000000000000000000: tz = 21; -- 32'b???????????100000000000000000000: tz = 20; -- 32'b????????????10000000000000000000: tz = 19; -- 32'b?????????????1000000000000000000: tz = 18; -- 32'b??????????????100000000000000000: tz = 17; -- 32'b???????????????10000000000000000: tz = 16; -- 32'b????????????????1000000000000000: tz = 15; -- 32'b?????????????????100000000000000: tz = 14; -- 32'b??????????????????10000000000000: tz = 13; -- 32'b???????????????????1000000000000: tz = 12; -- 32'b????????????????????100000000000: tz = 11; -- 32'b?????????????????????10000000000: tz = 10; -- 32'b??????????????????????1000000000: tz = 9; -- 32'b???????????????????????100000000: tz = 8; -- 32'b????????????????????????10000000: tz = 7; -- 32'b?????????????????????????1000000: tz = 6; -- 32'b??????????????????????????100000: tz = 5; -- 32'b???????????????????????????10000: tz = 4; -- 32'b????????????????????????????1000: tz = 3; -- 32'b?????????????????????????????100: tz = 2; -- 32'b??????????????????????????????10: tz = 1; -- 32'b???????????????????????????????1: tz = 0; -- default: tz = 0; -- endcase -- end -+ function automatic [5:0] count_tz; -+ input [31:0] val; -+ integer i; -+ reg found; -+ begin -+ count_tz = 32; -+ found = 0; -+ for (i = 0; i < 32; i = i + 1) begin -+ if (!found && val[i]) begin -+ count_tz = i; -+ found = 1; -+ end -+ end -+ end -+ endfunction -+ -+ assign lz = count_lz(lane_operand2); -+ assign tz = count_tz(lane_operand2); - - // Right shift - assign shift_in_sign = of_instruction.alu_op == OP_ASHR ? lane_operand1[31] : 1'd0; ---- l2_cache_read_stage.sv 2025-07-09 22:52:04.261145832 +0000 -+++ l2_cache_read_stage_fix.sv 2025-07-09 22:51:12.391892153 +0000 -@@ -143,7 +143,7 @@ - // - // Cache memory - // -- sram_1r1w #( -+ fakeram_1r1w_512x2048 #( - .DATA_WIDTH(CACHE_LINE_BITS), - .SIZE(`L2_WAYS * `L2_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- l2_cache_tag_stage.sv 2025-07-09 22:53:16.175496050 +0000 -+++ l2_cache_tag_stage_fix.sv 2025-07-09 22:53:08.300457778 +0000 -@@ -84,7 +84,7 @@ - begin : way_tags_gen - logic line_valid[`L2_SETS]; - -- sram_1r1w #( -+ fakeram_1r1w_18x256 #( - .DATA_WIDTH($bits(l2_tag_t)), - .SIZE(`L2_SETS), - .READ_DURING_WRITE("NEW_DATA") -@@ -97,7 +97,7 @@ - .write_data(l2r_update_tag_value), - .*); - -- sram_1r1w #( -+ fakeram_1r1w_1x256 #( - .DATA_WIDTH(1), - .SIZE(`L2_SETS), - .READ_DURING_WRITE("NEW_DATA") ---- operand_fetch_stage.sv 2025-07-09 22:45:53.872307594 +0000 -+++ operand_fetch_stage_fix.sv 2025-07-09 22:54:32.955868282 +0000 -@@ -58,7 +58,7 @@ - vector_t vector_val1; - vector_t vector_val2; - -- sram_2r1w #( -+ fakeram_2r1w_32x128 #( - .DATA_WIDTH($bits(scalar_t)), - .SIZE(32 * `THREADS_PER_CORE), - .READ_DURING_WRITE("DONT_CARE") -@@ -78,7 +78,7 @@ - generate - for (lane = 0; lane < NUM_VECTOR_LANES; lane++) - begin : vector_lane_gen -- sram_2r1w #( -+ fakeram_2r1w_32x128 #( - .DATA_WIDTH($bits(scalar_t)), - .SIZE(32 * `THREADS_PER_CORE), - .READ_DURING_WRITE("DONT_CARE") ---- rr_arbiter.sv 2025-07-09 01:05:59.698070566 +0000 -+++ rr_arbiter_fixed.sv 2025-07-09 20:02:02.221433548 +0000 -@@ -48,8 +48,8 @@ - logic granted; - - granted = request[grant_idx] & priority_oh[priority_idx]; -- for (logic[BIT_IDX_WIDTH - 1:0] bit_idx = priority_idx[BIT_IDX_WIDTH - 1:0]; -- bit_idx != grant_idx[BIT_IDX_WIDTH - 1:0]; bit_idx++) -+ for (logic[BIT_IDX_WIDTH - 1:0] bit_idx = priority_idx[BIT_IDX_WIDTH - 1:0] % NUM_REQUESTERS; -+ bit_idx != grant_idx[BIT_IDX_WIDTH - 1:0]; bit_idx= (bit_idx + 1) % NUM_REQUESTERS) - begin - granted &= !request[bit_idx]; - end ---- sync_fifo.sv 2025-07-09 22:58:56.848137411 +0000 -+++ sync_fifo_fix.sv 2025-07-09 22:58:48.638098119 +0000 -@@ -134,10 +134,5 @@ - end - end - -- initial -- begin -- if ($test$plusargs("dumpmems") != 0) -- $display("sync_fifo %d %d", WIDTH, SIZE); -- end - `endif - endmodule ---- tlb.sv 2025-07-09 22:48:59.312236398 +0000 -+++ tlb_fix.sv 2025-07-09 22:48:52.022200246 +0000 -@@ -93,7 +93,7 @@ - logic[ASID_WIDTH - 1:0] way_asid; - logic way_global; - -- sram_1r1w #( -+ fakeram_1r1w_16x52 #( - .SIZE(NUM_SETS), - .DATA_WIDTH(PAGE_NUM_BITS * 2 + 4 + ASID_WIDTH), - .READ_DURING_WRITE("NEW_DATA") diff --git a/designs/src/NyuziProcessor/dev/repo b/designs/src/NyuziProcessor/dev/repo deleted file mode 160000 index ed5c1a5..0000000 --- a/designs/src/NyuziProcessor/dev/repo +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ed5c1a50b77af80e54800e21bd8b62822c3f496a diff --git a/designs/src/NyuziProcessor/macros.v b/designs/src/NyuziProcessor/macros.v deleted file mode 100644 index 113239f..0000000 --- a/designs/src/NyuziProcessor/macros.v +++ /dev/null @@ -1,276 +0,0 @@ -module fakeram_1r1w_1x256 ( - clk, - read_en, - read_addr, - read_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 1; - parameter SIZE = 256; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read_en; - input [ADDR_WIDTH - 1:0] read_addr; - output reg [DATA_WIDTH - 1:0] read_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_1x256_1r1w sram ( - .r0_clk (clk), - .w0_clk (clk), - .r0_rd_out (read_data), - .r0_addr_in (read_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_1r1w_18x256 ( - clk, - read_en, - read_addr, - read_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 18; - parameter SIZE = 256; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read_en; - input [ADDR_WIDTH - 1:0] read_addr; - output reg [DATA_WIDTH - 1:0] read_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_18x256_1r1w sram ( - .r0_clk (clk), - .w0_clk (clk), - .r0_rd_out (read_data), - .r0_addr_in (read_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_1r1w_16x52 ( - clk, - read_en, - read_addr, - read_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 16; - parameter SIZE = 52; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read_en; - input [ADDR_WIDTH - 1:0] read_addr; - output reg [DATA_WIDTH - 1:0] read_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_16x52_1r1w sram ( - .r0_clk (clk), - .w0_clk (clk), - .r0_rd_out (read_data), - .r0_addr_in (read_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_1r1w_20x64 ( - clk, - read_en, - read_addr, - read_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 20; - parameter SIZE = 64; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read_en; - input [ADDR_WIDTH - 1:0] read_addr; - output reg [DATA_WIDTH - 1:0] read_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_20x64_1r1w sram ( - .r0_clk (clk), - .w0_clk (clk), - .r0_rd_out (read_data), - .r0_addr_in (read_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_1r1w_512x256 ( - clk, - read_en, - read_addr, - read_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 512; - parameter SIZE = 256; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read_en; - input [ADDR_WIDTH - 1:0] read_addr; - output reg [DATA_WIDTH - 1:0] read_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_512x256_1r1w sram ( - .r0_clk (clk), - .w0_clk (clk), - .r0_rd_out (read_data), - .r0_addr_in (read_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_1r1w_512x2048 ( - clk, - read_en, - read_addr, - read_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 512; - parameter SIZE = 2048; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read_en; - input [ADDR_WIDTH - 1:0] read_addr; - output reg [DATA_WIDTH - 1:0] read_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_512x2048_1r1w sram ( - .r0_clk (clk), - .w0_clk (clk), - .r0_rd_out (read_data), - .r0_addr_in (read_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_2r1w_20x64 ( - clk, - read1_en, - read1_addr, - read1_data, - read2_en, - read2_addr, - read2_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 20; - parameter SIZE = 64; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read1_en; - input [ADDR_WIDTH - 1:0] read1_addr; - output reg [DATA_WIDTH - 1:0] read1_data; - input read2_en; - input [ADDR_WIDTH - 1:0] read2_addr; - output reg [DATA_WIDTH - 1:0] read2_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_20x64_2r1w sram ( - .r0_clk (clk), - .r1_clk (clk), - .w0_clk (clk), - .r0_rd_out (read1_data), - .r1_rd_out (read2_data), - .r0_addr_in (read1_addr), - .r1_addr_in (read2_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read1_en), - .r1_ce_in (read2_en), - .w0_ce_in (1'b1) - ); -endmodule -module fakeram_2r1w_32x128 ( - clk, - read1_en, - read1_addr, - read1_data, - read2_en, - read2_addr, - read2_data, - write_en, - write_addr, - write_data -); - parameter DATA_WIDTH = 32; - parameter SIZE = 128; - parameter READ_DURING_WRITE = "NEW_DATA"; - parameter ADDR_WIDTH = $clog2(SIZE); - input clk; - input read1_en; - input [ADDR_WIDTH - 1:0] read1_addr; - output reg [DATA_WIDTH - 1:0] read1_data; - input read2_en; - input [ADDR_WIDTH - 1:0] read2_addr; - output reg [DATA_WIDTH - 1:0] read2_data; - input write_en; - input [ADDR_WIDTH - 1:0] write_addr; - input [DATA_WIDTH - 1:0] write_data; - fakeram_32x128_2r1w sram ( - .r0_clk (clk), - .r1_clk (clk), - .w0_clk (clk), - .r0_rd_out (read1_data), - .r1_rd_out (read2_data), - .r0_addr_in (read1_addr), - .r1_addr_in (read2_addr), - .w0_addr_in (write_addr), - .w0_we_in (write_en), - .w0_wd_in (write_data), - .r0_ce_in (read1_en), - .r1_ce_in (read2_en), - .w0_ce_in (1'b1) - ); -endmodule \ No newline at end of file diff --git a/designs/src/NyuziProcessor/verilog.mk b/designs/src/NyuziProcessor/verilog.mk deleted file mode 100644 index c029e6e..0000000 --- a/designs/src/NyuziProcessor/verilog.mk +++ /dev/null @@ -1,29 +0,0 @@ -ifneq ($(wildcard $(DEV_FLAG)),) -export DEV_SRC = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/nyuziTop.v \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo -REPO_SRC_DIR = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo/hardware/core -ALL_REPO_FILES = $(wildcard $(REPO_SRC_DIR)/*.sv) \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/nyuziTop.sv -REPO_FILES = $(filter-out \ - $(REPO_SRC_DIR)/sram_1r1w.sv \ - $(REPO_SRC_DIR)/sram_2r1w.sv, \ - $(ALL_REPO_FILES)) -REPO_INCLUDE_FILES = $(REPO_SRC_DIR)/defines.svh - -TARGET_DEV_FILE = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/NyuziProcessor.v - -$(TARGET_DEV_FILE) : $(REPO_FILES) - # Bypass error if patch has already been applied (prone to fail if repo code has changed) -#patch -p0 -N --silent --directory=$(REPO_SRC_DIR) < $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/patch-all.patch > /dev/null 2>&1 || [[ $$? == 1 ]] - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/sv2v --top NyuziProcessor -w $@ -I $(REPO_INCLUDE_FILES) $(REPO_FILES) - -export VERILOG_FILES = $(TARGET_DEV_FILE) \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v - -else -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/NyuziProcessor.v \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v -endif - -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/NyuziProcessor.v \ - $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/macros.v \ No newline at end of file diff --git a/designs/src/bp_processor/LICENSE b/designs/src/bp_processor/LICENSE new file mode 100644 index 0000000..9b3db23 --- /dev/null +++ b/designs/src/bp_processor/LICENSE @@ -0,0 +1,24 @@ +Copyright (c) 2019, University of Washington +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the University of Washington nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL UNIVERSITY OF WASHINGTON BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. \ No newline at end of file diff --git a/designs/src/bp_processor/verilog.mk b/designs/src/bp_processor/verilog.mk index 4081969..131ff7d 100644 --- a/designs/src/bp_processor/verilog.mk +++ b/designs/src/bp_processor/verilog.mk @@ -9,7 +9,7 @@ BP_RELEASE_RTL := $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v # Use 'rm -rf designs/src/bp_processor/dev/generated' to manually clean. export DEV_SRC := -ifneq ($(wildcard $(DEV_FLAG)),) +ifeq ($(DO_UPDATE),1) $(BP_DEV_RTL): $(BP_DEV_DIR)/setup.sh @echo "Generating Black-Parrot RTL via setup.sh" @cd $(BP_DEV_DIR) && bash setup.sh diff --git a/designs/src/cnn/verilog.mk b/designs/src/cnn/verilog.mk index 7252851..b29d885 100644 --- a/designs/src/cnn/verilog.mk +++ b/designs/src/cnn/verilog.mk @@ -8,9 +8,8 @@ CNN_RELEASE_RTL := $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/cnn.v CNN_RELEASE_FAKE_RTL = $(sort $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/fakeram_*.v)) # Allow clean_design to prune dev-generated artifacts when desired. -export DEV_SRC := $(CNN_BUILD_DIR) -ifneq ($(wildcard $(DEV_FLAG)),) +ifeq ($(DO_UPDATE),1) $(CNN_DEV_RTL): $(CNN_GEN_SCRIPT) @echo "Generating CNN RTL via $(CNN_GEN_SCRIPT)" @cd $(CNN_DEV_DIR) && ./generate_cnn_verilog.sh diff --git a/designs/src/coralnpu/CoreMiniAxi.v b/designs/src/coralnpu/CoreMiniAxi.v new file mode 100644 index 0000000..06536af --- /dev/null +++ b/designs/src/coralnpu/CoreMiniAxi.v @@ -0,0 +1,21840 @@ +module CoreCSR ( + clock, + reset, + io_fabric_readDataAddr_bits, + io_fabric_readData_valid, + io_fabric_readData_bits, + io_fabric_writeDataAddr_valid, + io_fabric_writeDataAddr_bits, + io_fabric_writeDataBits, + io_fabric_writeResp, + io_reset, + io_cg, + io_pcStart, + io_halted, + io_fault, + io_coralnpu_csr_value_0, + io_coralnpu_csr_value_1, + io_coralnpu_csr_value_2, + io_coralnpu_csr_value_3, + io_coralnpu_csr_value_4, + io_coralnpu_csr_value_5, + io_coralnpu_csr_value_6, + io_coralnpu_csr_value_7, + io_coralnpu_csr_value_8 +); + input clock; + input reset; + input [31:0] io_fabric_readDataAddr_bits; + output wire io_fabric_readData_valid; + output wire [127:0] io_fabric_readData_bits; + input io_fabric_writeDataAddr_valid; + input [31:0] io_fabric_writeDataAddr_bits; + input [127:0] io_fabric_writeDataBits; + output wire io_fabric_writeResp; + output wire io_reset; + output wire io_cg; + output wire [31:0] io_pcStart; + input io_halted; + input io_fault; + input [31:0] io_coralnpu_csr_value_0; + input [31:0] io_coralnpu_csr_value_1; + input [31:0] io_coralnpu_csr_value_2; + input [31:0] io_coralnpu_csr_value_3; + input [31:0] io_coralnpu_csr_value_4; + input [31:0] io_coralnpu_csr_value_5; + input [31:0] io_coralnpu_csr_value_6; + input [31:0] io_coralnpu_csr_value_7; + input [31:0] io_coralnpu_csr_value_8; + reg [31:0] resetReg; + reg [31:0] pcStartReg; + reg [31:0] statusReg; + wire readDataValid = (((((((((((io_fabric_readDataAddr_bits == 32'h0000010c) | (io_fabric_readDataAddr_bits == 32'h00000008)) | (io_fabric_readDataAddr_bits == 32'h00000110)) | (io_fabric_readDataAddr_bits == 32'h00000118)) | (io_fabric_readDataAddr_bits == 32'h00000100)) | (io_fabric_readDataAddr_bits == 32'h0000011c)) | (io_fabric_readDataAddr_bits == 32'h00000104)) | (io_fabric_readDataAddr_bits == 32'h00000108)) | (io_fabric_readDataAddr_bits == 32'h00000004)) | (io_fabric_readDataAddr_bits == 32'h00000114)) | (io_fabric_readDataAddr_bits == 32'h00000000)) | (io_fabric_readDataAddr_bits == 32'h00000120); + reg readDataNext_pipe_v; + reg [127:0] readDataNext_pipe_b; + wire _io_fabric_writeResp_T_1 = io_fabric_writeDataAddr_bits == 32'h00000000; + wire _io_fabric_writeResp_T_2 = io_fabric_writeDataAddr_bits == 32'h00000004; + always @(posedge clock or posedge reset) + if (reset) begin + resetReg <= 32'h00000003; + pcStartReg <= 32'h00000000; + statusReg <= 32'h00000000; + readDataNext_pipe_v <= 1'h0; + end + else begin + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_1) + resetReg <= io_fabric_writeDataBits[31:0]; + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_2) + pcStartReg <= io_fabric_writeDataBits[63:32]; + statusReg <= {30'h00000000, io_fault, io_halted}; + readDataNext_pipe_v <= readDataValid; + end + wire _GEN = io_fabric_readDataAddr_bits[31:4] == 28'h0000000; + wire _GEN_0 = io_fabric_readDataAddr_bits[31:4] == 28'h0000010; + wire _GEN_1 = io_fabric_readDataAddr_bits[31:4] == 28'h0000011; + always @(posedge clock) + if (readDataValid) + readDataNext_pipe_b <= {(_GEN_1 ? io_coralnpu_csr_value_7 : (_GEN_0 ? io_coralnpu_csr_value_3 : 32'h00000000)), (_GEN_1 ? io_coralnpu_csr_value_6 : (_GEN_0 ? io_coralnpu_csr_value_2 : (_GEN ? statusReg : 32'h00000000))), (_GEN_1 ? io_coralnpu_csr_value_5 : (_GEN_0 ? io_coralnpu_csr_value_1 : (_GEN ? pcStartReg : 32'h00000000))), (_GEN_1 ? io_coralnpu_csr_value_4 : (_GEN_0 ? io_coralnpu_csr_value_0 : (io_fabric_readDataAddr_bits[31:4] == 28'h0000012 ? io_coralnpu_csr_value_8 : (_GEN ? resetReg : 32'h00000000))))}; + assign io_fabric_readData_valid = readDataNext_pipe_v; + assign io_fabric_readData_bits = readDataNext_pipe_b; + assign io_fabric_writeResp = io_fabric_writeDataAddr_valid & (_io_fabric_writeResp_T_2 | _io_fabric_writeResp_T_1); + assign io_reset = resetReg[0]; + assign io_cg = resetReg[1]; + assign io_pcStart = pcStartReg; +endmodule +module Regfile ( + clock, + reset, + io_readAddr_0_valid, + io_readAddr_0_addr, + io_readAddr_1_valid, + io_readAddr_1_addr, + io_readAddr_2_valid, + io_readAddr_2_addr, + io_readAddr_3_valid, + io_readAddr_3_addr, + io_readAddr_4_valid, + io_readAddr_4_addr, + io_readAddr_5_valid, + io_readAddr_5_addr, + io_readAddr_6_valid, + io_readAddr_6_addr, + io_readAddr_7_valid, + io_readAddr_7_addr, + io_readSet_0_valid, + io_readSet_0_value, + io_readSet_1_valid, + io_readSet_1_value, + io_readSet_2_valid, + io_readSet_2_value, + io_readSet_3_valid, + io_readSet_3_value, + io_readSet_4_valid, + io_readSet_4_value, + io_readSet_5_valid, + io_readSet_5_value, + io_readSet_6_valid, + io_readSet_6_value, + io_readSet_7_valid, + io_readSet_7_value, + io_writeAddr_0_valid, + io_writeAddr_0_addr, + io_writeAddr_1_valid, + io_writeAddr_1_addr, + io_writeAddr_2_valid, + io_writeAddr_2_addr, + io_writeAddr_3_valid, + io_writeAddr_3_addr, + io_busAddr_0_bypass, + io_busAddr_0_immen, + io_busAddr_0_immed, + io_busAddr_1_bypass, + io_busAddr_1_immed, + io_busAddr_2_bypass, + io_busAddr_2_immed, + io_busAddr_3_bypass, + io_busAddr_3_immed, + io_target_0_data, + io_target_1_data, + io_target_2_data, + io_target_3_data, + io_busPort_addr_0, + io_busPort_addr_1, + io_busPort_addr_2, + io_busPort_addr_3, + io_busPort_data_0, + io_busPort_data_1, + io_busPort_data_2, + io_busPort_data_3, + io_readData_0_valid, + io_readData_0_data, + io_readData_1_valid, + io_readData_1_data, + io_readData_2_valid, + io_readData_2_data, + io_readData_3_valid, + io_readData_3_data, + io_readData_4_valid, + io_readData_4_data, + io_readData_5_valid, + io_readData_5_data, + io_readData_6_valid, + io_readData_6_data, + io_readData_7_valid, + io_readData_7_data, + io_writeData_0_valid, + io_writeData_0_bits_addr, + io_writeData_0_bits_data, + io_writeData_1_valid, + io_writeData_1_bits_addr, + io_writeData_1_bits_data, + io_writeData_2_valid, + io_writeData_2_bits_addr, + io_writeData_2_bits_data, + io_writeData_3_valid, + io_writeData_3_bits_addr, + io_writeData_3_bits_data, + io_writeData_4_valid, + io_writeData_4_bits_addr, + io_writeData_4_bits_data, + io_writeData_5_valid, + io_writeData_5_bits_addr, + io_writeData_5_bits_data, + io_writeMask_1_valid, + io_writeMask_2_valid, + io_writeMask_3_valid, + io_writeMask_5_valid, + io_scoreboard_regd, + io_scoreboard_comb +); + input clock; + input reset; + input io_readAddr_0_valid; + input [4:0] io_readAddr_0_addr; + input io_readAddr_1_valid; + input [4:0] io_readAddr_1_addr; + input io_readAddr_2_valid; + input [4:0] io_readAddr_2_addr; + input io_readAddr_3_valid; + input [4:0] io_readAddr_3_addr; + input io_readAddr_4_valid; + input [4:0] io_readAddr_4_addr; + input io_readAddr_5_valid; + input [4:0] io_readAddr_5_addr; + input io_readAddr_6_valid; + input [4:0] io_readAddr_6_addr; + input io_readAddr_7_valid; + input [4:0] io_readAddr_7_addr; + input io_readSet_0_valid; + input [31:0] io_readSet_0_value; + input io_readSet_1_valid; + input [31:0] io_readSet_1_value; + input io_readSet_2_valid; + input [31:0] io_readSet_2_value; + input io_readSet_3_valid; + input [31:0] io_readSet_3_value; + input io_readSet_4_valid; + input [31:0] io_readSet_4_value; + input io_readSet_5_valid; + input [31:0] io_readSet_5_value; + input io_readSet_6_valid; + input [31:0] io_readSet_6_value; + input io_readSet_7_valid; + input [31:0] io_readSet_7_value; + input io_writeAddr_0_valid; + input [4:0] io_writeAddr_0_addr; + input io_writeAddr_1_valid; + input [4:0] io_writeAddr_1_addr; + input io_writeAddr_2_valid; + input [4:0] io_writeAddr_2_addr; + input io_writeAddr_3_valid; + input [4:0] io_writeAddr_3_addr; + input io_busAddr_0_bypass; + input io_busAddr_0_immen; + input [31:0] io_busAddr_0_immed; + input io_busAddr_1_bypass; + input [31:0] io_busAddr_1_immed; + input io_busAddr_2_bypass; + input [31:0] io_busAddr_2_immed; + input io_busAddr_3_bypass; + input [31:0] io_busAddr_3_immed; + output wire [31:0] io_target_0_data; + output wire [31:0] io_target_1_data; + output wire [31:0] io_target_2_data; + output wire [31:0] io_target_3_data; + output wire [31:0] io_busPort_addr_0; + output wire [31:0] io_busPort_addr_1; + output wire [31:0] io_busPort_addr_2; + output wire [31:0] io_busPort_addr_3; + output wire [31:0] io_busPort_data_0; + output wire [31:0] io_busPort_data_1; + output wire [31:0] io_busPort_data_2; + output wire [31:0] io_busPort_data_3; + output wire io_readData_0_valid; + output wire [31:0] io_readData_0_data; + output wire io_readData_1_valid; + output wire [31:0] io_readData_1_data; + output wire io_readData_2_valid; + output wire [31:0] io_readData_2_data; + output wire io_readData_3_valid; + output wire [31:0] io_readData_3_data; + output wire io_readData_4_valid; + output wire [31:0] io_readData_4_data; + output wire io_readData_5_valid; + output wire [31:0] io_readData_5_data; + output wire io_readData_6_valid; + output wire [31:0] io_readData_6_data; + output wire io_readData_7_valid; + output wire [31:0] io_readData_7_data; + input io_writeData_0_valid; + input [4:0] io_writeData_0_bits_addr; + input [31:0] io_writeData_0_bits_data; + input io_writeData_1_valid; + input [4:0] io_writeData_1_bits_addr; + input [31:0] io_writeData_1_bits_data; + input io_writeData_2_valid; + input [4:0] io_writeData_2_bits_addr; + input [31:0] io_writeData_2_bits_data; + input io_writeData_3_valid; + input [4:0] io_writeData_3_bits_addr; + input [31:0] io_writeData_3_bits_data; + input io_writeData_4_valid; + input [4:0] io_writeData_4_bits_addr; + input [31:0] io_writeData_4_bits_data; + input io_writeData_5_valid; + input [4:0] io_writeData_5_bits_addr; + input [31:0] io_writeData_5_bits_data; + input io_writeMask_1_valid; + input io_writeMask_2_valid; + input io_writeMask_3_valid; + input io_writeMask_5_valid; + output wire [31:0] io_scoreboard_regd; + output wire [31:0] io_scoreboard_comb; + reg [31:0] regfile_1; + reg [31:0] regfile_2; + reg [31:0] regfile_3; + reg [31:0] regfile_4; + reg [31:0] regfile_5; + reg [31:0] regfile_6; + reg [31:0] regfile_7; + reg [31:0] regfile_8; + reg [31:0] regfile_9; + reg [31:0] regfile_10; + reg [31:0] regfile_11; + reg [31:0] regfile_12; + reg [31:0] regfile_13; + reg [31:0] regfile_14; + reg [31:0] regfile_15; + reg [31:0] regfile_16; + reg [31:0] regfile_17; + reg [31:0] regfile_18; + reg [31:0] regfile_19; + reg [31:0] regfile_20; + reg [31:0] regfile_21; + reg [31:0] regfile_22; + reg [31:0] regfile_23; + reg [31:0] regfile_24; + reg [31:0] regfile_25; + reg [31:0] regfile_26; + reg [31:0] regfile_27; + reg [31:0] regfile_28; + reg [31:0] regfile_29; + reg [31:0] regfile_30; + reg [31:0] regfile_31; + reg [31:0] scoreboard; + wire [31:0] _scoreboard_clr0_T_1 = 32'h00000001 << io_writeData_0_bits_addr; + wire [31:0] _scoreboard_clr0_T_4 = 32'h00000001 << io_writeData_1_bits_addr; + wire [31:0] _scoreboard_clr0_T_7 = 32'h00000001 << io_writeData_2_bits_addr; + wire [31:0] _scoreboard_clr0_T_10 = 32'h00000001 << io_writeData_3_bits_addr; + wire [31:0] _scoreboard_clr0_T_13 = 32'h00000001 << io_writeData_4_bits_addr; + wire [31:0] _scoreboard_clr0_T_16 = 32'h00000001 << io_writeData_5_bits_addr; + wire [30:0] scoreboard_clr0 = (((((io_writeData_0_valid ? _scoreboard_clr0_T_1[31:1] : 31'h00000000) | (io_writeData_1_valid ? _scoreboard_clr0_T_4[31:1] : 31'h00000000)) | (io_writeData_2_valid ? _scoreboard_clr0_T_7[31:1] : 31'h00000000)) | (io_writeData_3_valid ? _scoreboard_clr0_T_10[31:1] : 31'h00000000)) | (io_writeData_4_valid ? _scoreboard_clr0_T_13[31:1] : 31'h00000000)) | (io_writeData_5_valid ? _scoreboard_clr0_T_16[31:1] : 31'h00000000); + reg readDataReady_0; + reg readDataReady_1; + reg readDataReady_2; + reg readDataReady_3; + reg readDataReady_4; + reg readDataReady_5; + reg readDataReady_6; + reg readDataReady_7; + reg [31:0] readDataBits_0; + reg [31:0] readDataBits_1; + reg [31:0] readDataBits_2; + reg [31:0] readDataBits_3; + reg [31:0] readDataBits_4; + reg [31:0] readDataBits_5; + reg [31:0] readDataBits_6; + reg [31:0] readDataBits_7; + wire _valid_T = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h01); + wire valid_1 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h01)) & ~io_writeMask_1_valid; + wire valid_2 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h01)) & ~io_writeMask_2_valid; + wire valid_3 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h01)) & ~io_writeMask_3_valid; + wire _valid_T_8 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h01); + wire valid_5 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h01)) & ~io_writeMask_5_valid; + wire [31:0] data = (((((_valid_T ? io_writeData_0_bits_data : 32'h00000000) | (valid_1 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_8 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_1_T = {_valid_T, valid_1, valid_2, valid_3, _valid_T_8, valid_5}; + wire _valid_T_12 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h02); + wire valid_1_1 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h02)) & ~io_writeMask_1_valid; + wire valid_2_1 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h02)) & ~io_writeMask_2_valid; + wire valid_3_1 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h02)) & ~io_writeMask_3_valid; + wire _valid_T_20 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h02); + wire valid_5_1 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h02)) & ~io_writeMask_5_valid; + wire [31:0] data_1 = (((((_valid_T_12 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_1 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_1 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_1 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_20 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_1 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_2_T = {_valid_T_12, valid_1_1, valid_2_1, valid_3_1, _valid_T_20, valid_5_1}; + wire _valid_T_24 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h03); + wire valid_1_2 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h03)) & ~io_writeMask_1_valid; + wire valid_2_2 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h03)) & ~io_writeMask_2_valid; + wire valid_3_2 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h03)) & ~io_writeMask_3_valid; + wire _valid_T_32 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h03); + wire valid_5_2 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h03)) & ~io_writeMask_5_valid; + wire [31:0] data_2 = (((((_valid_T_24 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_2 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_2 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_2 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_32 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_2 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_3_T = {_valid_T_24, valid_1_2, valid_2_2, valid_3_2, _valid_T_32, valid_5_2}; + wire _valid_T_36 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h04); + wire valid_1_3 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h04)) & ~io_writeMask_1_valid; + wire valid_2_3 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h04)) & ~io_writeMask_2_valid; + wire valid_3_3 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h04)) & ~io_writeMask_3_valid; + wire _valid_T_44 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h04); + wire valid_5_3 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h04)) & ~io_writeMask_5_valid; + wire [31:0] data_3 = (((((_valid_T_36 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_3 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_3 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_3 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_44 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_3 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_4_T = {_valid_T_36, valid_1_3, valid_2_3, valid_3_3, _valid_T_44, valid_5_3}; + wire _valid_T_48 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h05); + wire valid_1_4 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h05)) & ~io_writeMask_1_valid; + wire valid_2_4 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h05)) & ~io_writeMask_2_valid; + wire valid_3_4 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h05)) & ~io_writeMask_3_valid; + wire _valid_T_56 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h05); + wire valid_5_4 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h05)) & ~io_writeMask_5_valid; + wire [31:0] data_4 = (((((_valid_T_48 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_4 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_4 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_4 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_56 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_4 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_5_T = {_valid_T_48, valid_1_4, valid_2_4, valid_3_4, _valid_T_56, valid_5_4}; + wire _valid_T_60 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h06); + wire valid_1_5 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h06)) & ~io_writeMask_1_valid; + wire valid_2_5 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h06)) & ~io_writeMask_2_valid; + wire valid_3_5 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h06)) & ~io_writeMask_3_valid; + wire _valid_T_68 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h06); + wire valid_5_5 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h06)) & ~io_writeMask_5_valid; + wire [31:0] data_5 = (((((_valid_T_60 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_5 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_5 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_5 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_68 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_5 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_6_T = {_valid_T_60, valid_1_5, valid_2_5, valid_3_5, _valid_T_68, valid_5_5}; + wire _valid_T_72 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h07); + wire valid_1_6 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h07)) & ~io_writeMask_1_valid; + wire valid_2_6 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h07)) & ~io_writeMask_2_valid; + wire valid_3_6 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h07)) & ~io_writeMask_3_valid; + wire _valid_T_80 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h07); + wire valid_5_6 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h07)) & ~io_writeMask_5_valid; + wire [31:0] data_6 = (((((_valid_T_72 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_6 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_6 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_6 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_80 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_6 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_7_T = {_valid_T_72, valid_1_6, valid_2_6, valid_3_6, _valid_T_80, valid_5_6}; + wire _valid_T_84 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h08); + wire valid_1_7 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h08)) & ~io_writeMask_1_valid; + wire valid_2_7 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h08)) & ~io_writeMask_2_valid; + wire valid_3_7 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h08)) & ~io_writeMask_3_valid; + wire _valid_T_92 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h08); + wire valid_5_7 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h08)) & ~io_writeMask_5_valid; + wire [31:0] data_7 = (((((_valid_T_84 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_7 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_7 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_7 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_92 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_7 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_8_T = {_valid_T_84, valid_1_7, valid_2_7, valid_3_7, _valid_T_92, valid_5_7}; + wire _valid_T_96 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h09); + wire valid_1_8 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h09)) & ~io_writeMask_1_valid; + wire valid_2_8 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h09)) & ~io_writeMask_2_valid; + wire valid_3_8 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h09)) & ~io_writeMask_3_valid; + wire _valid_T_104 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h09); + wire valid_5_8 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h09)) & ~io_writeMask_5_valid; + wire [31:0] data_8 = (((((_valid_T_96 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_8 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_8 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_8 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_104 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_8 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_9_T = {_valid_T_96, valid_1_8, valid_2_8, valid_3_8, _valid_T_104, valid_5_8}; + wire _valid_T_108 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h0a); + wire valid_1_9 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h0a)) & ~io_writeMask_1_valid; + wire valid_2_9 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h0a)) & ~io_writeMask_2_valid; + wire valid_3_9 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h0a)) & ~io_writeMask_3_valid; + wire _valid_T_116 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h0a); + wire valid_5_9 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h0a)) & ~io_writeMask_5_valid; + wire [31:0] data_9 = (((((_valid_T_108 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_9 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_9 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_9 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_116 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_9 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_10_T = {_valid_T_108, valid_1_9, valid_2_9, valid_3_9, _valid_T_116, valid_5_9}; + wire _valid_T_120 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h0b); + wire valid_1_10 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h0b)) & ~io_writeMask_1_valid; + wire valid_2_10 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h0b)) & ~io_writeMask_2_valid; + wire valid_3_10 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h0b)) & ~io_writeMask_3_valid; + wire _valid_T_128 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h0b); + wire valid_5_10 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h0b)) & ~io_writeMask_5_valid; + wire [31:0] data_10 = (((((_valid_T_120 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_10 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_10 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_10 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_128 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_10 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_11_T = {_valid_T_120, valid_1_10, valid_2_10, valid_3_10, _valid_T_128, valid_5_10}; + wire _valid_T_132 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h0c); + wire valid_1_11 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h0c)) & ~io_writeMask_1_valid; + wire valid_2_11 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h0c)) & ~io_writeMask_2_valid; + wire valid_3_11 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h0c)) & ~io_writeMask_3_valid; + wire _valid_T_140 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h0c); + wire valid_5_11 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h0c)) & ~io_writeMask_5_valid; + wire [31:0] data_11 = (((((_valid_T_132 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_11 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_11 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_11 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_140 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_11 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_12_T = {_valid_T_132, valid_1_11, valid_2_11, valid_3_11, _valid_T_140, valid_5_11}; + wire _valid_T_144 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h0d); + wire valid_1_12 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h0d)) & ~io_writeMask_1_valid; + wire valid_2_12 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h0d)) & ~io_writeMask_2_valid; + wire valid_3_12 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h0d)) & ~io_writeMask_3_valid; + wire _valid_T_152 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h0d); + wire valid_5_12 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h0d)) & ~io_writeMask_5_valid; + wire [31:0] data_12 = (((((_valid_T_144 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_12 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_12 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_12 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_152 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_12 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_13_T = {_valid_T_144, valid_1_12, valid_2_12, valid_3_12, _valid_T_152, valid_5_12}; + wire _valid_T_156 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h0e); + wire valid_1_13 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h0e)) & ~io_writeMask_1_valid; + wire valid_2_13 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h0e)) & ~io_writeMask_2_valid; + wire valid_3_13 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h0e)) & ~io_writeMask_3_valid; + wire _valid_T_164 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h0e); + wire valid_5_13 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h0e)) & ~io_writeMask_5_valid; + wire [31:0] data_13 = (((((_valid_T_156 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_13 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_13 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_13 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_164 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_13 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_14_T = {_valid_T_156, valid_1_13, valid_2_13, valid_3_13, _valid_T_164, valid_5_13}; + wire _valid_T_168 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h0f); + wire valid_1_14 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h0f)) & ~io_writeMask_1_valid; + wire valid_2_14 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h0f)) & ~io_writeMask_2_valid; + wire valid_3_14 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h0f)) & ~io_writeMask_3_valid; + wire _valid_T_176 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h0f); + wire valid_5_14 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h0f)) & ~io_writeMask_5_valid; + wire [31:0] data_14 = (((((_valid_T_168 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_14 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_14 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_14 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_176 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_14 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_15_T = {_valid_T_168, valid_1_14, valid_2_14, valid_3_14, _valid_T_176, valid_5_14}; + wire _valid_T_180 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h10); + wire valid_1_15 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h10)) & ~io_writeMask_1_valid; + wire valid_2_15 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h10)) & ~io_writeMask_2_valid; + wire valid_3_15 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h10)) & ~io_writeMask_3_valid; + wire _valid_T_188 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h10); + wire valid_5_15 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h10)) & ~io_writeMask_5_valid; + wire [31:0] data_15 = (((((_valid_T_180 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_15 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_15 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_15 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_188 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_15 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_16_T = {_valid_T_180, valid_1_15, valid_2_15, valid_3_15, _valid_T_188, valid_5_15}; + wire _valid_T_192 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h11); + wire valid_1_16 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h11)) & ~io_writeMask_1_valid; + wire valid_2_16 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h11)) & ~io_writeMask_2_valid; + wire valid_3_16 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h11)) & ~io_writeMask_3_valid; + wire _valid_T_200 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h11); + wire valid_5_16 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h11)) & ~io_writeMask_5_valid; + wire [31:0] data_16 = (((((_valid_T_192 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_16 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_16 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_16 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_200 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_16 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_17_T = {_valid_T_192, valid_1_16, valid_2_16, valid_3_16, _valid_T_200, valid_5_16}; + wire _valid_T_204 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h12); + wire valid_1_17 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h12)) & ~io_writeMask_1_valid; + wire valid_2_17 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h12)) & ~io_writeMask_2_valid; + wire valid_3_17 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h12)) & ~io_writeMask_3_valid; + wire _valid_T_212 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h12); + wire valid_5_17 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h12)) & ~io_writeMask_5_valid; + wire [31:0] data_17 = (((((_valid_T_204 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_17 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_17 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_17 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_212 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_17 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_18_T = {_valid_T_204, valid_1_17, valid_2_17, valid_3_17, _valid_T_212, valid_5_17}; + wire _valid_T_216 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h13); + wire valid_1_18 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h13)) & ~io_writeMask_1_valid; + wire valid_2_18 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h13)) & ~io_writeMask_2_valid; + wire valid_3_18 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h13)) & ~io_writeMask_3_valid; + wire _valid_T_224 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h13); + wire valid_5_18 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h13)) & ~io_writeMask_5_valid; + wire [31:0] data_18 = (((((_valid_T_216 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_18 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_18 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_18 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_224 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_18 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_19_T = {_valid_T_216, valid_1_18, valid_2_18, valid_3_18, _valid_T_224, valid_5_18}; + wire _valid_T_228 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h14); + wire valid_1_19 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h14)) & ~io_writeMask_1_valid; + wire valid_2_19 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h14)) & ~io_writeMask_2_valid; + wire valid_3_19 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h14)) & ~io_writeMask_3_valid; + wire _valid_T_236 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h14); + wire valid_5_19 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h14)) & ~io_writeMask_5_valid; + wire [31:0] data_19 = (((((_valid_T_228 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_19 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_19 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_19 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_236 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_19 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_20_T = {_valid_T_228, valid_1_19, valid_2_19, valid_3_19, _valid_T_236, valid_5_19}; + wire _valid_T_240 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h15); + wire valid_1_20 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h15)) & ~io_writeMask_1_valid; + wire valid_2_20 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h15)) & ~io_writeMask_2_valid; + wire valid_3_20 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h15)) & ~io_writeMask_3_valid; + wire _valid_T_248 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h15); + wire valid_5_20 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h15)) & ~io_writeMask_5_valid; + wire [31:0] data_20 = (((((_valid_T_240 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_20 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_20 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_20 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_248 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_20 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_21_T = {_valid_T_240, valid_1_20, valid_2_20, valid_3_20, _valid_T_248, valid_5_20}; + wire _valid_T_252 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h16); + wire valid_1_21 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h16)) & ~io_writeMask_1_valid; + wire valid_2_21 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h16)) & ~io_writeMask_2_valid; + wire valid_3_21 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h16)) & ~io_writeMask_3_valid; + wire _valid_T_260 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h16); + wire valid_5_21 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h16)) & ~io_writeMask_5_valid; + wire [31:0] data_21 = (((((_valid_T_252 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_21 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_21 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_21 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_260 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_21 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_22_T = {_valid_T_252, valid_1_21, valid_2_21, valid_3_21, _valid_T_260, valid_5_21}; + wire _valid_T_264 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h17); + wire valid_1_22 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h17)) & ~io_writeMask_1_valid; + wire valid_2_22 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h17)) & ~io_writeMask_2_valid; + wire valid_3_22 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h17)) & ~io_writeMask_3_valid; + wire _valid_T_272 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h17); + wire valid_5_22 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h17)) & ~io_writeMask_5_valid; + wire [31:0] data_22 = (((((_valid_T_264 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_22 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_22 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_22 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_272 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_22 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_23_T = {_valid_T_264, valid_1_22, valid_2_22, valid_3_22, _valid_T_272, valid_5_22}; + wire _valid_T_276 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h18); + wire valid_1_23 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h18)) & ~io_writeMask_1_valid; + wire valid_2_23 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h18)) & ~io_writeMask_2_valid; + wire valid_3_23 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h18)) & ~io_writeMask_3_valid; + wire _valid_T_284 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h18); + wire valid_5_23 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h18)) & ~io_writeMask_5_valid; + wire [31:0] data_23 = (((((_valid_T_276 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_23 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_23 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_23 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_284 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_23 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_24_T = {_valid_T_276, valid_1_23, valid_2_23, valid_3_23, _valid_T_284, valid_5_23}; + wire _valid_T_288 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h19); + wire valid_1_24 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h19)) & ~io_writeMask_1_valid; + wire valid_2_24 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h19)) & ~io_writeMask_2_valid; + wire valid_3_24 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h19)) & ~io_writeMask_3_valid; + wire _valid_T_296 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h19); + wire valid_5_24 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h19)) & ~io_writeMask_5_valid; + wire [31:0] data_24 = (((((_valid_T_288 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_24 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_24 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_24 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_296 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_24 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_25_T = {_valid_T_288, valid_1_24, valid_2_24, valid_3_24, _valid_T_296, valid_5_24}; + wire _valid_T_300 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h1a); + wire valid_1_25 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h1a)) & ~io_writeMask_1_valid; + wire valid_2_25 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h1a)) & ~io_writeMask_2_valid; + wire valid_3_25 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h1a)) & ~io_writeMask_3_valid; + wire _valid_T_308 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h1a); + wire valid_5_25 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h1a)) & ~io_writeMask_5_valid; + wire [31:0] data_25 = (((((_valid_T_300 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_25 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_25 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_25 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_308 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_25 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_26_T = {_valid_T_300, valid_1_25, valid_2_25, valid_3_25, _valid_T_308, valid_5_25}; + wire _valid_T_312 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h1b); + wire valid_1_26 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h1b)) & ~io_writeMask_1_valid; + wire valid_2_26 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h1b)) & ~io_writeMask_2_valid; + wire valid_3_26 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h1b)) & ~io_writeMask_3_valid; + wire _valid_T_320 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h1b); + wire valid_5_26 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h1b)) & ~io_writeMask_5_valid; + wire [31:0] data_26 = (((((_valid_T_312 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_26 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_26 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_26 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_320 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_26 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_27_T = {_valid_T_312, valid_1_26, valid_2_26, valid_3_26, _valid_T_320, valid_5_26}; + wire _valid_T_324 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h1c); + wire valid_1_27 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h1c)) & ~io_writeMask_1_valid; + wire valid_2_27 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h1c)) & ~io_writeMask_2_valid; + wire valid_3_27 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h1c)) & ~io_writeMask_3_valid; + wire _valid_T_332 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h1c); + wire valid_5_27 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h1c)) & ~io_writeMask_5_valid; + wire [31:0] data_27 = (((((_valid_T_324 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_27 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_27 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_27 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_332 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_27 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_28_T = {_valid_T_324, valid_1_27, valid_2_27, valid_3_27, _valid_T_332, valid_5_27}; + wire _valid_T_336 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h1d); + wire valid_1_28 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h1d)) & ~io_writeMask_1_valid; + wire valid_2_28 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h1d)) & ~io_writeMask_2_valid; + wire valid_3_28 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h1d)) & ~io_writeMask_3_valid; + wire _valid_T_344 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h1d); + wire valid_5_28 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h1d)) & ~io_writeMask_5_valid; + wire [31:0] data_28 = (((((_valid_T_336 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_28 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_28 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_28 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_344 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_28 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_29_T = {_valid_T_336, valid_1_28, valid_2_28, valid_3_28, _valid_T_344, valid_5_28}; + wire _valid_T_348 = io_writeData_0_valid & (io_writeData_0_bits_addr == 5'h1e); + wire valid_1_29 = (io_writeData_1_valid & (io_writeData_1_bits_addr == 5'h1e)) & ~io_writeMask_1_valid; + wire valid_2_29 = (io_writeData_2_valid & (io_writeData_2_bits_addr == 5'h1e)) & ~io_writeMask_2_valid; + wire valid_3_29 = (io_writeData_3_valid & (io_writeData_3_bits_addr == 5'h1e)) & ~io_writeMask_3_valid; + wire _valid_T_356 = io_writeData_4_valid & (io_writeData_4_bits_addr == 5'h1e); + wire valid_5_29 = (io_writeData_5_valid & (io_writeData_5_bits_addr == 5'h1e)) & ~io_writeMask_5_valid; + wire [31:0] data_29 = (((((_valid_T_348 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_29 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_29 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_29 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_356 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_29 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_30_T = {_valid_T_348, valid_1_29, valid_2_29, valid_3_29, _valid_T_356, valid_5_29}; + wire _valid_T_360 = io_writeData_0_valid & (&io_writeData_0_bits_addr); + wire valid_1_30 = (io_writeData_1_valid & (&io_writeData_1_bits_addr)) & ~io_writeMask_1_valid; + wire valid_2_30 = (io_writeData_2_valid & (&io_writeData_2_bits_addr)) & ~io_writeMask_2_valid; + wire valid_3_30 = (io_writeData_3_valid & (&io_writeData_3_bits_addr)) & ~io_writeMask_3_valid; + wire _valid_T_368 = io_writeData_4_valid & (&io_writeData_4_bits_addr); + wire valid_5_30 = (io_writeData_5_valid & (&io_writeData_5_bits_addr)) & ~io_writeMask_5_valid; + wire [31:0] data_30 = (((((_valid_T_360 ? io_writeData_0_bits_data : 32'h00000000) | (valid_1_30 ? io_writeData_1_bits_data : 32'h00000000)) | (valid_2_30 ? io_writeData_2_bits_data : 32'h00000000)) | (valid_3_30 ? io_writeData_3_bits_data : 32'h00000000)) | (_valid_T_368 ? io_writeData_4_bits_data : 32'h00000000)) | (valid_5_30 ? io_writeData_5_bits_data : 32'h00000000); + wire [5:0] _writeValid_31_T = {_valid_T_360, valid_1_30, valid_2_30, valid_3_30, _valid_T_368, valid_5_30}; + wire _wdata_0_value_1_T = io_readAddr_0_addr == 5'h01; + wire _wdata_0_value_2_T = io_readAddr_0_addr == 5'h02; + wire _wdata_0_value_3_T = io_readAddr_0_addr == 5'h03; + wire _wdata_0_value_4_T = io_readAddr_0_addr == 5'h04; + wire _wdata_0_value_5_T = io_readAddr_0_addr == 5'h05; + wire _wdata_0_value_6_T = io_readAddr_0_addr == 5'h06; + wire _wdata_0_value_7_T = io_readAddr_0_addr == 5'h07; + wire _wdata_0_value_8_T = io_readAddr_0_addr == 5'h08; + wire _wdata_0_value_9_T = io_readAddr_0_addr == 5'h09; + wire _wdata_0_value_10_T = io_readAddr_0_addr == 5'h0a; + wire _wdata_0_value_11_T = io_readAddr_0_addr == 5'h0b; + wire _wdata_0_value_12_T = io_readAddr_0_addr == 5'h0c; + wire _wdata_0_value_13_T = io_readAddr_0_addr == 5'h0d; + wire _wdata_0_value_14_T = io_readAddr_0_addr == 5'h0e; + wire _wdata_0_value_15_T = io_readAddr_0_addr == 5'h0f; + wire _wdata_0_value_16_T = io_readAddr_0_addr == 5'h10; + wire _wdata_0_value_17_T = io_readAddr_0_addr == 5'h11; + wire _wdata_0_value_18_T = io_readAddr_0_addr == 5'h12; + wire _wdata_0_value_19_T = io_readAddr_0_addr == 5'h13; + wire _wdata_0_value_20_T = io_readAddr_0_addr == 5'h14; + wire _wdata_0_value_21_T = io_readAddr_0_addr == 5'h15; + wire _wdata_0_value_22_T = io_readAddr_0_addr == 5'h16; + wire _wdata_0_value_23_T = io_readAddr_0_addr == 5'h17; + wire _wdata_0_value_24_T = io_readAddr_0_addr == 5'h18; + wire _wdata_0_value_25_T = io_readAddr_0_addr == 5'h19; + wire _wdata_0_value_26_T = io_readAddr_0_addr == 5'h1a; + wire _wdata_0_value_27_T = io_readAddr_0_addr == 5'h1b; + wire _wdata_0_value_28_T = io_readAddr_0_addr == 5'h1c; + wire _wdata_0_value_29_T = io_readAddr_0_addr == 5'h1d; + wire _wdata_0_value_30_T = io_readAddr_0_addr == 5'h1e; + wire [31:0] rdata_0_value_5_0 = ((((((((((((((((((((((((((((((_wdata_0_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_0_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_0_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_0_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_0_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_0_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_0_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_0_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_0_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_0_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_0_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_0_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_0_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_0_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_0_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_0_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_0_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_0_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_0_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_0_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_0_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_0_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_0_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_0_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_0_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_0_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_0_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_0_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_0_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_0_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_0_addr ? regfile_31 : 32'h00000000); + wire [31:0] rwdata_0 = ((((((((((((((((((((((((((((((((io_readAddr_0_addr == 5'h00) | (_wdata_0_value_1_T & |_writeValid_1_T)) | (_wdata_0_value_2_T & |_writeValid_2_T)) | (_wdata_0_value_3_T & |_writeValid_3_T)) | (_wdata_0_value_4_T & |_writeValid_4_T)) | (_wdata_0_value_5_T & |_writeValid_5_T)) | (_wdata_0_value_6_T & |_writeValid_6_T)) | (_wdata_0_value_7_T & |_writeValid_7_T)) | (_wdata_0_value_8_T & |_writeValid_8_T)) | (_wdata_0_value_9_T & |_writeValid_9_T)) | (_wdata_0_value_10_T & |_writeValid_10_T)) | (_wdata_0_value_11_T & |_writeValid_11_T)) | (_wdata_0_value_12_T & |_writeValid_12_T)) | (_wdata_0_value_13_T & |_writeValid_13_T)) | (_wdata_0_value_14_T & |_writeValid_14_T)) | (_wdata_0_value_15_T & |_writeValid_15_T)) | (_wdata_0_value_16_T & |_writeValid_16_T)) | (_wdata_0_value_17_T & |_writeValid_17_T)) | (_wdata_0_value_18_T & |_writeValid_18_T)) | (_wdata_0_value_19_T & |_writeValid_19_T)) | (_wdata_0_value_20_T & |_writeValid_20_T)) | (_wdata_0_value_21_T & |_writeValid_21_T)) | (_wdata_0_value_22_T & |_writeValid_22_T)) | (_wdata_0_value_23_T & |_writeValid_23_T)) | (_wdata_0_value_24_T & |_writeValid_24_T)) | (_wdata_0_value_25_T & |_writeValid_25_T)) | (_wdata_0_value_26_T & |_writeValid_26_T)) | (_wdata_0_value_27_T & |_writeValid_27_T)) | (_wdata_0_value_28_T & |_writeValid_28_T)) | (_wdata_0_value_29_T & |_writeValid_29_T)) | (_wdata_0_value_30_T & |_writeValid_30_T)) | (&io_readAddr_0_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_0_value_1_T ? data : 32'h00000000) | (_wdata_0_value_2_T ? data_1 : 32'h00000000)) | (_wdata_0_value_3_T ? data_2 : 32'h00000000)) | (_wdata_0_value_4_T ? data_3 : 32'h00000000)) | (_wdata_0_value_5_T ? data_4 : 32'h00000000)) | (_wdata_0_value_6_T ? data_5 : 32'h00000000)) | (_wdata_0_value_7_T ? data_6 : 32'h00000000)) | (_wdata_0_value_8_T ? data_7 : 32'h00000000)) | (_wdata_0_value_9_T ? data_8 : 32'h00000000)) | (_wdata_0_value_10_T ? data_9 : 32'h00000000)) | (_wdata_0_value_11_T ? data_10 : 32'h00000000)) | (_wdata_0_value_12_T ? data_11 : 32'h00000000)) | (_wdata_0_value_13_T ? data_12 : 32'h00000000)) | (_wdata_0_value_14_T ? data_13 : 32'h00000000)) | (_wdata_0_value_15_T ? data_14 : 32'h00000000)) | (_wdata_0_value_16_T ? data_15 : 32'h00000000)) | (_wdata_0_value_17_T ? data_16 : 32'h00000000)) | (_wdata_0_value_18_T ? data_17 : 32'h00000000)) | (_wdata_0_value_19_T ? data_18 : 32'h00000000)) | (_wdata_0_value_20_T ? data_19 : 32'h00000000)) | (_wdata_0_value_21_T ? data_20 : 32'h00000000)) | (_wdata_0_value_22_T ? data_21 : 32'h00000000)) | (_wdata_0_value_23_T ? data_22 : 32'h00000000)) | (_wdata_0_value_24_T ? data_23 : 32'h00000000)) | (_wdata_0_value_25_T ? data_24 : 32'h00000000)) | (_wdata_0_value_26_T ? data_25 : 32'h00000000)) | (_wdata_0_value_27_T ? data_26 : 32'h00000000)) | (_wdata_0_value_28_T ? data_27 : 32'h00000000)) | (_wdata_0_value_29_T ? data_28 : 32'h00000000)) | (_wdata_0_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_0_addr ? data_30 : 32'h00000000) : rdata_0_value_5_0); + wire _wdata_1_value_1_T = io_readAddr_1_addr == 5'h01; + wire _wdata_1_value_2_T = io_readAddr_1_addr == 5'h02; + wire _wdata_1_value_3_T = io_readAddr_1_addr == 5'h03; + wire _wdata_1_value_4_T = io_readAddr_1_addr == 5'h04; + wire _wdata_1_value_5_T = io_readAddr_1_addr == 5'h05; + wire _wdata_1_value_6_T = io_readAddr_1_addr == 5'h06; + wire _wdata_1_value_7_T = io_readAddr_1_addr == 5'h07; + wire _wdata_1_value_8_T = io_readAddr_1_addr == 5'h08; + wire _wdata_1_value_9_T = io_readAddr_1_addr == 5'h09; + wire _wdata_1_value_10_T = io_readAddr_1_addr == 5'h0a; + wire _wdata_1_value_11_T = io_readAddr_1_addr == 5'h0b; + wire _wdata_1_value_12_T = io_readAddr_1_addr == 5'h0c; + wire _wdata_1_value_13_T = io_readAddr_1_addr == 5'h0d; + wire _wdata_1_value_14_T = io_readAddr_1_addr == 5'h0e; + wire _wdata_1_value_15_T = io_readAddr_1_addr == 5'h0f; + wire _wdata_1_value_16_T = io_readAddr_1_addr == 5'h10; + wire _wdata_1_value_17_T = io_readAddr_1_addr == 5'h11; + wire _wdata_1_value_18_T = io_readAddr_1_addr == 5'h12; + wire _wdata_1_value_19_T = io_readAddr_1_addr == 5'h13; + wire _wdata_1_value_20_T = io_readAddr_1_addr == 5'h14; + wire _wdata_1_value_21_T = io_readAddr_1_addr == 5'h15; + wire _wdata_1_value_22_T = io_readAddr_1_addr == 5'h16; + wire _wdata_1_value_23_T = io_readAddr_1_addr == 5'h17; + wire _wdata_1_value_24_T = io_readAddr_1_addr == 5'h18; + wire _wdata_1_value_25_T = io_readAddr_1_addr == 5'h19; + wire _wdata_1_value_26_T = io_readAddr_1_addr == 5'h1a; + wire _wdata_1_value_27_T = io_readAddr_1_addr == 5'h1b; + wire _wdata_1_value_28_T = io_readAddr_1_addr == 5'h1c; + wire _wdata_1_value_29_T = io_readAddr_1_addr == 5'h1d; + wire _wdata_1_value_30_T = io_readAddr_1_addr == 5'h1e; + wire [31:0] rwdata_1 = ((((((((((((((((((((((((((((((((io_readAddr_1_addr == 5'h00) | (_wdata_1_value_1_T & |_writeValid_1_T)) | (_wdata_1_value_2_T & |_writeValid_2_T)) | (_wdata_1_value_3_T & |_writeValid_3_T)) | (_wdata_1_value_4_T & |_writeValid_4_T)) | (_wdata_1_value_5_T & |_writeValid_5_T)) | (_wdata_1_value_6_T & |_writeValid_6_T)) | (_wdata_1_value_7_T & |_writeValid_7_T)) | (_wdata_1_value_8_T & |_writeValid_8_T)) | (_wdata_1_value_9_T & |_writeValid_9_T)) | (_wdata_1_value_10_T & |_writeValid_10_T)) | (_wdata_1_value_11_T & |_writeValid_11_T)) | (_wdata_1_value_12_T & |_writeValid_12_T)) | (_wdata_1_value_13_T & |_writeValid_13_T)) | (_wdata_1_value_14_T & |_writeValid_14_T)) | (_wdata_1_value_15_T & |_writeValid_15_T)) | (_wdata_1_value_16_T & |_writeValid_16_T)) | (_wdata_1_value_17_T & |_writeValid_17_T)) | (_wdata_1_value_18_T & |_writeValid_18_T)) | (_wdata_1_value_19_T & |_writeValid_19_T)) | (_wdata_1_value_20_T & |_writeValid_20_T)) | (_wdata_1_value_21_T & |_writeValid_21_T)) | (_wdata_1_value_22_T & |_writeValid_22_T)) | (_wdata_1_value_23_T & |_writeValid_23_T)) | (_wdata_1_value_24_T & |_writeValid_24_T)) | (_wdata_1_value_25_T & |_writeValid_25_T)) | (_wdata_1_value_26_T & |_writeValid_26_T)) | (_wdata_1_value_27_T & |_writeValid_27_T)) | (_wdata_1_value_28_T & |_writeValid_28_T)) | (_wdata_1_value_29_T & |_writeValid_29_T)) | (_wdata_1_value_30_T & |_writeValid_30_T)) | (&io_readAddr_1_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_1_value_1_T ? data : 32'h00000000) | (_wdata_1_value_2_T ? data_1 : 32'h00000000)) | (_wdata_1_value_3_T ? data_2 : 32'h00000000)) | (_wdata_1_value_4_T ? data_3 : 32'h00000000)) | (_wdata_1_value_5_T ? data_4 : 32'h00000000)) | (_wdata_1_value_6_T ? data_5 : 32'h00000000)) | (_wdata_1_value_7_T ? data_6 : 32'h00000000)) | (_wdata_1_value_8_T ? data_7 : 32'h00000000)) | (_wdata_1_value_9_T ? data_8 : 32'h00000000)) | (_wdata_1_value_10_T ? data_9 : 32'h00000000)) | (_wdata_1_value_11_T ? data_10 : 32'h00000000)) | (_wdata_1_value_12_T ? data_11 : 32'h00000000)) | (_wdata_1_value_13_T ? data_12 : 32'h00000000)) | (_wdata_1_value_14_T ? data_13 : 32'h00000000)) | (_wdata_1_value_15_T ? data_14 : 32'h00000000)) | (_wdata_1_value_16_T ? data_15 : 32'h00000000)) | (_wdata_1_value_17_T ? data_16 : 32'h00000000)) | (_wdata_1_value_18_T ? data_17 : 32'h00000000)) | (_wdata_1_value_19_T ? data_18 : 32'h00000000)) | (_wdata_1_value_20_T ? data_19 : 32'h00000000)) | (_wdata_1_value_21_T ? data_20 : 32'h00000000)) | (_wdata_1_value_22_T ? data_21 : 32'h00000000)) | (_wdata_1_value_23_T ? data_22 : 32'h00000000)) | (_wdata_1_value_24_T ? data_23 : 32'h00000000)) | (_wdata_1_value_25_T ? data_24 : 32'h00000000)) | (_wdata_1_value_26_T ? data_25 : 32'h00000000)) | (_wdata_1_value_27_T ? data_26 : 32'h00000000)) | (_wdata_1_value_28_T ? data_27 : 32'h00000000)) | (_wdata_1_value_29_T ? data_28 : 32'h00000000)) | (_wdata_1_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_1_addr ? data_30 : 32'h00000000) : ((((((((((((((((((((((((((((((_wdata_1_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_1_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_1_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_1_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_1_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_1_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_1_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_1_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_1_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_1_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_1_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_1_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_1_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_1_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_1_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_1_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_1_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_1_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_1_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_1_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_1_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_1_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_1_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_1_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_1_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_1_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_1_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_1_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_1_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_1_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_1_addr ? regfile_31 : 32'h00000000)); + wire _wdata_2_value_1_T = io_readAddr_2_addr == 5'h01; + wire _wdata_2_value_2_T = io_readAddr_2_addr == 5'h02; + wire _wdata_2_value_3_T = io_readAddr_2_addr == 5'h03; + wire _wdata_2_value_4_T = io_readAddr_2_addr == 5'h04; + wire _wdata_2_value_5_T = io_readAddr_2_addr == 5'h05; + wire _wdata_2_value_6_T = io_readAddr_2_addr == 5'h06; + wire _wdata_2_value_7_T = io_readAddr_2_addr == 5'h07; + wire _wdata_2_value_8_T = io_readAddr_2_addr == 5'h08; + wire _wdata_2_value_9_T = io_readAddr_2_addr == 5'h09; + wire _wdata_2_value_10_T = io_readAddr_2_addr == 5'h0a; + wire _wdata_2_value_11_T = io_readAddr_2_addr == 5'h0b; + wire _wdata_2_value_12_T = io_readAddr_2_addr == 5'h0c; + wire _wdata_2_value_13_T = io_readAddr_2_addr == 5'h0d; + wire _wdata_2_value_14_T = io_readAddr_2_addr == 5'h0e; + wire _wdata_2_value_15_T = io_readAddr_2_addr == 5'h0f; + wire _wdata_2_value_16_T = io_readAddr_2_addr == 5'h10; + wire _wdata_2_value_17_T = io_readAddr_2_addr == 5'h11; + wire _wdata_2_value_18_T = io_readAddr_2_addr == 5'h12; + wire _wdata_2_value_19_T = io_readAddr_2_addr == 5'h13; + wire _wdata_2_value_20_T = io_readAddr_2_addr == 5'h14; + wire _wdata_2_value_21_T = io_readAddr_2_addr == 5'h15; + wire _wdata_2_value_22_T = io_readAddr_2_addr == 5'h16; + wire _wdata_2_value_23_T = io_readAddr_2_addr == 5'h17; + wire _wdata_2_value_24_T = io_readAddr_2_addr == 5'h18; + wire _wdata_2_value_25_T = io_readAddr_2_addr == 5'h19; + wire _wdata_2_value_26_T = io_readAddr_2_addr == 5'h1a; + wire _wdata_2_value_27_T = io_readAddr_2_addr == 5'h1b; + wire _wdata_2_value_28_T = io_readAddr_2_addr == 5'h1c; + wire _wdata_2_value_29_T = io_readAddr_2_addr == 5'h1d; + wire _wdata_2_value_30_T = io_readAddr_2_addr == 5'h1e; + wire [31:0] rdata_2_value_5_0 = ((((((((((((((((((((((((((((((_wdata_2_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_2_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_2_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_2_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_2_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_2_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_2_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_2_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_2_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_2_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_2_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_2_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_2_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_2_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_2_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_2_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_2_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_2_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_2_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_2_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_2_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_2_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_2_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_2_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_2_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_2_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_2_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_2_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_2_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_2_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_2_addr ? regfile_31 : 32'h00000000); + wire [31:0] rwdata_2 = ((((((((((((((((((((((((((((((((io_readAddr_2_addr == 5'h00) | (_wdata_2_value_1_T & |_writeValid_1_T)) | (_wdata_2_value_2_T & |_writeValid_2_T)) | (_wdata_2_value_3_T & |_writeValid_3_T)) | (_wdata_2_value_4_T & |_writeValid_4_T)) | (_wdata_2_value_5_T & |_writeValid_5_T)) | (_wdata_2_value_6_T & |_writeValid_6_T)) | (_wdata_2_value_7_T & |_writeValid_7_T)) | (_wdata_2_value_8_T & |_writeValid_8_T)) | (_wdata_2_value_9_T & |_writeValid_9_T)) | (_wdata_2_value_10_T & |_writeValid_10_T)) | (_wdata_2_value_11_T & |_writeValid_11_T)) | (_wdata_2_value_12_T & |_writeValid_12_T)) | (_wdata_2_value_13_T & |_writeValid_13_T)) | (_wdata_2_value_14_T & |_writeValid_14_T)) | (_wdata_2_value_15_T & |_writeValid_15_T)) | (_wdata_2_value_16_T & |_writeValid_16_T)) | (_wdata_2_value_17_T & |_writeValid_17_T)) | (_wdata_2_value_18_T & |_writeValid_18_T)) | (_wdata_2_value_19_T & |_writeValid_19_T)) | (_wdata_2_value_20_T & |_writeValid_20_T)) | (_wdata_2_value_21_T & |_writeValid_21_T)) | (_wdata_2_value_22_T & |_writeValid_22_T)) | (_wdata_2_value_23_T & |_writeValid_23_T)) | (_wdata_2_value_24_T & |_writeValid_24_T)) | (_wdata_2_value_25_T & |_writeValid_25_T)) | (_wdata_2_value_26_T & |_writeValid_26_T)) | (_wdata_2_value_27_T & |_writeValid_27_T)) | (_wdata_2_value_28_T & |_writeValid_28_T)) | (_wdata_2_value_29_T & |_writeValid_29_T)) | (_wdata_2_value_30_T & |_writeValid_30_T)) | (&io_readAddr_2_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_2_value_1_T ? data : 32'h00000000) | (_wdata_2_value_2_T ? data_1 : 32'h00000000)) | (_wdata_2_value_3_T ? data_2 : 32'h00000000)) | (_wdata_2_value_4_T ? data_3 : 32'h00000000)) | (_wdata_2_value_5_T ? data_4 : 32'h00000000)) | (_wdata_2_value_6_T ? data_5 : 32'h00000000)) | (_wdata_2_value_7_T ? data_6 : 32'h00000000)) | (_wdata_2_value_8_T ? data_7 : 32'h00000000)) | (_wdata_2_value_9_T ? data_8 : 32'h00000000)) | (_wdata_2_value_10_T ? data_9 : 32'h00000000)) | (_wdata_2_value_11_T ? data_10 : 32'h00000000)) | (_wdata_2_value_12_T ? data_11 : 32'h00000000)) | (_wdata_2_value_13_T ? data_12 : 32'h00000000)) | (_wdata_2_value_14_T ? data_13 : 32'h00000000)) | (_wdata_2_value_15_T ? data_14 : 32'h00000000)) | (_wdata_2_value_16_T ? data_15 : 32'h00000000)) | (_wdata_2_value_17_T ? data_16 : 32'h00000000)) | (_wdata_2_value_18_T ? data_17 : 32'h00000000)) | (_wdata_2_value_19_T ? data_18 : 32'h00000000)) | (_wdata_2_value_20_T ? data_19 : 32'h00000000)) | (_wdata_2_value_21_T ? data_20 : 32'h00000000)) | (_wdata_2_value_22_T ? data_21 : 32'h00000000)) | (_wdata_2_value_23_T ? data_22 : 32'h00000000)) | (_wdata_2_value_24_T ? data_23 : 32'h00000000)) | (_wdata_2_value_25_T ? data_24 : 32'h00000000)) | (_wdata_2_value_26_T ? data_25 : 32'h00000000)) | (_wdata_2_value_27_T ? data_26 : 32'h00000000)) | (_wdata_2_value_28_T ? data_27 : 32'h00000000)) | (_wdata_2_value_29_T ? data_28 : 32'h00000000)) | (_wdata_2_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_2_addr ? data_30 : 32'h00000000) : rdata_2_value_5_0); + wire _wdata_3_value_1_T = io_readAddr_3_addr == 5'h01; + wire _wdata_3_value_2_T = io_readAddr_3_addr == 5'h02; + wire _wdata_3_value_3_T = io_readAddr_3_addr == 5'h03; + wire _wdata_3_value_4_T = io_readAddr_3_addr == 5'h04; + wire _wdata_3_value_5_T = io_readAddr_3_addr == 5'h05; + wire _wdata_3_value_6_T = io_readAddr_3_addr == 5'h06; + wire _wdata_3_value_7_T = io_readAddr_3_addr == 5'h07; + wire _wdata_3_value_8_T = io_readAddr_3_addr == 5'h08; + wire _wdata_3_value_9_T = io_readAddr_3_addr == 5'h09; + wire _wdata_3_value_10_T = io_readAddr_3_addr == 5'h0a; + wire _wdata_3_value_11_T = io_readAddr_3_addr == 5'h0b; + wire _wdata_3_value_12_T = io_readAddr_3_addr == 5'h0c; + wire _wdata_3_value_13_T = io_readAddr_3_addr == 5'h0d; + wire _wdata_3_value_14_T = io_readAddr_3_addr == 5'h0e; + wire _wdata_3_value_15_T = io_readAddr_3_addr == 5'h0f; + wire _wdata_3_value_16_T = io_readAddr_3_addr == 5'h10; + wire _wdata_3_value_17_T = io_readAddr_3_addr == 5'h11; + wire _wdata_3_value_18_T = io_readAddr_3_addr == 5'h12; + wire _wdata_3_value_19_T = io_readAddr_3_addr == 5'h13; + wire _wdata_3_value_20_T = io_readAddr_3_addr == 5'h14; + wire _wdata_3_value_21_T = io_readAddr_3_addr == 5'h15; + wire _wdata_3_value_22_T = io_readAddr_3_addr == 5'h16; + wire _wdata_3_value_23_T = io_readAddr_3_addr == 5'h17; + wire _wdata_3_value_24_T = io_readAddr_3_addr == 5'h18; + wire _wdata_3_value_25_T = io_readAddr_3_addr == 5'h19; + wire _wdata_3_value_26_T = io_readAddr_3_addr == 5'h1a; + wire _wdata_3_value_27_T = io_readAddr_3_addr == 5'h1b; + wire _wdata_3_value_28_T = io_readAddr_3_addr == 5'h1c; + wire _wdata_3_value_29_T = io_readAddr_3_addr == 5'h1d; + wire _wdata_3_value_30_T = io_readAddr_3_addr == 5'h1e; + wire [31:0] rwdata_3 = ((((((((((((((((((((((((((((((((io_readAddr_3_addr == 5'h00) | (_wdata_3_value_1_T & |_writeValid_1_T)) | (_wdata_3_value_2_T & |_writeValid_2_T)) | (_wdata_3_value_3_T & |_writeValid_3_T)) | (_wdata_3_value_4_T & |_writeValid_4_T)) | (_wdata_3_value_5_T & |_writeValid_5_T)) | (_wdata_3_value_6_T & |_writeValid_6_T)) | (_wdata_3_value_7_T & |_writeValid_7_T)) | (_wdata_3_value_8_T & |_writeValid_8_T)) | (_wdata_3_value_9_T & |_writeValid_9_T)) | (_wdata_3_value_10_T & |_writeValid_10_T)) | (_wdata_3_value_11_T & |_writeValid_11_T)) | (_wdata_3_value_12_T & |_writeValid_12_T)) | (_wdata_3_value_13_T & |_writeValid_13_T)) | (_wdata_3_value_14_T & |_writeValid_14_T)) | (_wdata_3_value_15_T & |_writeValid_15_T)) | (_wdata_3_value_16_T & |_writeValid_16_T)) | (_wdata_3_value_17_T & |_writeValid_17_T)) | (_wdata_3_value_18_T & |_writeValid_18_T)) | (_wdata_3_value_19_T & |_writeValid_19_T)) | (_wdata_3_value_20_T & |_writeValid_20_T)) | (_wdata_3_value_21_T & |_writeValid_21_T)) | (_wdata_3_value_22_T & |_writeValid_22_T)) | (_wdata_3_value_23_T & |_writeValid_23_T)) | (_wdata_3_value_24_T & |_writeValid_24_T)) | (_wdata_3_value_25_T & |_writeValid_25_T)) | (_wdata_3_value_26_T & |_writeValid_26_T)) | (_wdata_3_value_27_T & |_writeValid_27_T)) | (_wdata_3_value_28_T & |_writeValid_28_T)) | (_wdata_3_value_29_T & |_writeValid_29_T)) | (_wdata_3_value_30_T & |_writeValid_30_T)) | (&io_readAddr_3_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_3_value_1_T ? data : 32'h00000000) | (_wdata_3_value_2_T ? data_1 : 32'h00000000)) | (_wdata_3_value_3_T ? data_2 : 32'h00000000)) | (_wdata_3_value_4_T ? data_3 : 32'h00000000)) | (_wdata_3_value_5_T ? data_4 : 32'h00000000)) | (_wdata_3_value_6_T ? data_5 : 32'h00000000)) | (_wdata_3_value_7_T ? data_6 : 32'h00000000)) | (_wdata_3_value_8_T ? data_7 : 32'h00000000)) | (_wdata_3_value_9_T ? data_8 : 32'h00000000)) | (_wdata_3_value_10_T ? data_9 : 32'h00000000)) | (_wdata_3_value_11_T ? data_10 : 32'h00000000)) | (_wdata_3_value_12_T ? data_11 : 32'h00000000)) | (_wdata_3_value_13_T ? data_12 : 32'h00000000)) | (_wdata_3_value_14_T ? data_13 : 32'h00000000)) | (_wdata_3_value_15_T ? data_14 : 32'h00000000)) | (_wdata_3_value_16_T ? data_15 : 32'h00000000)) | (_wdata_3_value_17_T ? data_16 : 32'h00000000)) | (_wdata_3_value_18_T ? data_17 : 32'h00000000)) | (_wdata_3_value_19_T ? data_18 : 32'h00000000)) | (_wdata_3_value_20_T ? data_19 : 32'h00000000)) | (_wdata_3_value_21_T ? data_20 : 32'h00000000)) | (_wdata_3_value_22_T ? data_21 : 32'h00000000)) | (_wdata_3_value_23_T ? data_22 : 32'h00000000)) | (_wdata_3_value_24_T ? data_23 : 32'h00000000)) | (_wdata_3_value_25_T ? data_24 : 32'h00000000)) | (_wdata_3_value_26_T ? data_25 : 32'h00000000)) | (_wdata_3_value_27_T ? data_26 : 32'h00000000)) | (_wdata_3_value_28_T ? data_27 : 32'h00000000)) | (_wdata_3_value_29_T ? data_28 : 32'h00000000)) | (_wdata_3_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_3_addr ? data_30 : 32'h00000000) : ((((((((((((((((((((((((((((((_wdata_3_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_3_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_3_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_3_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_3_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_3_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_3_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_3_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_3_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_3_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_3_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_3_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_3_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_3_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_3_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_3_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_3_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_3_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_3_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_3_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_3_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_3_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_3_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_3_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_3_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_3_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_3_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_3_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_3_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_3_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_3_addr ? regfile_31 : 32'h00000000)); + wire _wdata_4_value_1_T = io_readAddr_4_addr == 5'h01; + wire _wdata_4_value_2_T = io_readAddr_4_addr == 5'h02; + wire _wdata_4_value_3_T = io_readAddr_4_addr == 5'h03; + wire _wdata_4_value_4_T = io_readAddr_4_addr == 5'h04; + wire _wdata_4_value_5_T = io_readAddr_4_addr == 5'h05; + wire _wdata_4_value_6_T = io_readAddr_4_addr == 5'h06; + wire _wdata_4_value_7_T = io_readAddr_4_addr == 5'h07; + wire _wdata_4_value_8_T = io_readAddr_4_addr == 5'h08; + wire _wdata_4_value_9_T = io_readAddr_4_addr == 5'h09; + wire _wdata_4_value_10_T = io_readAddr_4_addr == 5'h0a; + wire _wdata_4_value_11_T = io_readAddr_4_addr == 5'h0b; + wire _wdata_4_value_12_T = io_readAddr_4_addr == 5'h0c; + wire _wdata_4_value_13_T = io_readAddr_4_addr == 5'h0d; + wire _wdata_4_value_14_T = io_readAddr_4_addr == 5'h0e; + wire _wdata_4_value_15_T = io_readAddr_4_addr == 5'h0f; + wire _wdata_4_value_16_T = io_readAddr_4_addr == 5'h10; + wire _wdata_4_value_17_T = io_readAddr_4_addr == 5'h11; + wire _wdata_4_value_18_T = io_readAddr_4_addr == 5'h12; + wire _wdata_4_value_19_T = io_readAddr_4_addr == 5'h13; + wire _wdata_4_value_20_T = io_readAddr_4_addr == 5'h14; + wire _wdata_4_value_21_T = io_readAddr_4_addr == 5'h15; + wire _wdata_4_value_22_T = io_readAddr_4_addr == 5'h16; + wire _wdata_4_value_23_T = io_readAddr_4_addr == 5'h17; + wire _wdata_4_value_24_T = io_readAddr_4_addr == 5'h18; + wire _wdata_4_value_25_T = io_readAddr_4_addr == 5'h19; + wire _wdata_4_value_26_T = io_readAddr_4_addr == 5'h1a; + wire _wdata_4_value_27_T = io_readAddr_4_addr == 5'h1b; + wire _wdata_4_value_28_T = io_readAddr_4_addr == 5'h1c; + wire _wdata_4_value_29_T = io_readAddr_4_addr == 5'h1d; + wire _wdata_4_value_30_T = io_readAddr_4_addr == 5'h1e; + wire [31:0] rdata_4_value_5_0 = ((((((((((((((((((((((((((((((_wdata_4_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_4_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_4_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_4_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_4_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_4_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_4_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_4_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_4_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_4_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_4_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_4_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_4_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_4_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_4_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_4_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_4_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_4_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_4_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_4_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_4_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_4_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_4_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_4_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_4_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_4_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_4_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_4_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_4_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_4_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_4_addr ? regfile_31 : 32'h00000000); + wire [31:0] rwdata_4 = ((((((((((((((((((((((((((((((((io_readAddr_4_addr == 5'h00) | (_wdata_4_value_1_T & |_writeValid_1_T)) | (_wdata_4_value_2_T & |_writeValid_2_T)) | (_wdata_4_value_3_T & |_writeValid_3_T)) | (_wdata_4_value_4_T & |_writeValid_4_T)) | (_wdata_4_value_5_T & |_writeValid_5_T)) | (_wdata_4_value_6_T & |_writeValid_6_T)) | (_wdata_4_value_7_T & |_writeValid_7_T)) | (_wdata_4_value_8_T & |_writeValid_8_T)) | (_wdata_4_value_9_T & |_writeValid_9_T)) | (_wdata_4_value_10_T & |_writeValid_10_T)) | (_wdata_4_value_11_T & |_writeValid_11_T)) | (_wdata_4_value_12_T & |_writeValid_12_T)) | (_wdata_4_value_13_T & |_writeValid_13_T)) | (_wdata_4_value_14_T & |_writeValid_14_T)) | (_wdata_4_value_15_T & |_writeValid_15_T)) | (_wdata_4_value_16_T & |_writeValid_16_T)) | (_wdata_4_value_17_T & |_writeValid_17_T)) | (_wdata_4_value_18_T & |_writeValid_18_T)) | (_wdata_4_value_19_T & |_writeValid_19_T)) | (_wdata_4_value_20_T & |_writeValid_20_T)) | (_wdata_4_value_21_T & |_writeValid_21_T)) | (_wdata_4_value_22_T & |_writeValid_22_T)) | (_wdata_4_value_23_T & |_writeValid_23_T)) | (_wdata_4_value_24_T & |_writeValid_24_T)) | (_wdata_4_value_25_T & |_writeValid_25_T)) | (_wdata_4_value_26_T & |_writeValid_26_T)) | (_wdata_4_value_27_T & |_writeValid_27_T)) | (_wdata_4_value_28_T & |_writeValid_28_T)) | (_wdata_4_value_29_T & |_writeValid_29_T)) | (_wdata_4_value_30_T & |_writeValid_30_T)) | (&io_readAddr_4_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_4_value_1_T ? data : 32'h00000000) | (_wdata_4_value_2_T ? data_1 : 32'h00000000)) | (_wdata_4_value_3_T ? data_2 : 32'h00000000)) | (_wdata_4_value_4_T ? data_3 : 32'h00000000)) | (_wdata_4_value_5_T ? data_4 : 32'h00000000)) | (_wdata_4_value_6_T ? data_5 : 32'h00000000)) | (_wdata_4_value_7_T ? data_6 : 32'h00000000)) | (_wdata_4_value_8_T ? data_7 : 32'h00000000)) | (_wdata_4_value_9_T ? data_8 : 32'h00000000)) | (_wdata_4_value_10_T ? data_9 : 32'h00000000)) | (_wdata_4_value_11_T ? data_10 : 32'h00000000)) | (_wdata_4_value_12_T ? data_11 : 32'h00000000)) | (_wdata_4_value_13_T ? data_12 : 32'h00000000)) | (_wdata_4_value_14_T ? data_13 : 32'h00000000)) | (_wdata_4_value_15_T ? data_14 : 32'h00000000)) | (_wdata_4_value_16_T ? data_15 : 32'h00000000)) | (_wdata_4_value_17_T ? data_16 : 32'h00000000)) | (_wdata_4_value_18_T ? data_17 : 32'h00000000)) | (_wdata_4_value_19_T ? data_18 : 32'h00000000)) | (_wdata_4_value_20_T ? data_19 : 32'h00000000)) | (_wdata_4_value_21_T ? data_20 : 32'h00000000)) | (_wdata_4_value_22_T ? data_21 : 32'h00000000)) | (_wdata_4_value_23_T ? data_22 : 32'h00000000)) | (_wdata_4_value_24_T ? data_23 : 32'h00000000)) | (_wdata_4_value_25_T ? data_24 : 32'h00000000)) | (_wdata_4_value_26_T ? data_25 : 32'h00000000)) | (_wdata_4_value_27_T ? data_26 : 32'h00000000)) | (_wdata_4_value_28_T ? data_27 : 32'h00000000)) | (_wdata_4_value_29_T ? data_28 : 32'h00000000)) | (_wdata_4_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_4_addr ? data_30 : 32'h00000000) : rdata_4_value_5_0); + wire _wdata_5_value_1_T = io_readAddr_5_addr == 5'h01; + wire _wdata_5_value_2_T = io_readAddr_5_addr == 5'h02; + wire _wdata_5_value_3_T = io_readAddr_5_addr == 5'h03; + wire _wdata_5_value_4_T = io_readAddr_5_addr == 5'h04; + wire _wdata_5_value_5_T = io_readAddr_5_addr == 5'h05; + wire _wdata_5_value_6_T = io_readAddr_5_addr == 5'h06; + wire _wdata_5_value_7_T = io_readAddr_5_addr == 5'h07; + wire _wdata_5_value_8_T = io_readAddr_5_addr == 5'h08; + wire _wdata_5_value_9_T = io_readAddr_5_addr == 5'h09; + wire _wdata_5_value_10_T = io_readAddr_5_addr == 5'h0a; + wire _wdata_5_value_11_T = io_readAddr_5_addr == 5'h0b; + wire _wdata_5_value_12_T = io_readAddr_5_addr == 5'h0c; + wire _wdata_5_value_13_T = io_readAddr_5_addr == 5'h0d; + wire _wdata_5_value_14_T = io_readAddr_5_addr == 5'h0e; + wire _wdata_5_value_15_T = io_readAddr_5_addr == 5'h0f; + wire _wdata_5_value_16_T = io_readAddr_5_addr == 5'h10; + wire _wdata_5_value_17_T = io_readAddr_5_addr == 5'h11; + wire _wdata_5_value_18_T = io_readAddr_5_addr == 5'h12; + wire _wdata_5_value_19_T = io_readAddr_5_addr == 5'h13; + wire _wdata_5_value_20_T = io_readAddr_5_addr == 5'h14; + wire _wdata_5_value_21_T = io_readAddr_5_addr == 5'h15; + wire _wdata_5_value_22_T = io_readAddr_5_addr == 5'h16; + wire _wdata_5_value_23_T = io_readAddr_5_addr == 5'h17; + wire _wdata_5_value_24_T = io_readAddr_5_addr == 5'h18; + wire _wdata_5_value_25_T = io_readAddr_5_addr == 5'h19; + wire _wdata_5_value_26_T = io_readAddr_5_addr == 5'h1a; + wire _wdata_5_value_27_T = io_readAddr_5_addr == 5'h1b; + wire _wdata_5_value_28_T = io_readAddr_5_addr == 5'h1c; + wire _wdata_5_value_29_T = io_readAddr_5_addr == 5'h1d; + wire _wdata_5_value_30_T = io_readAddr_5_addr == 5'h1e; + wire [31:0] rwdata_5 = ((((((((((((((((((((((((((((((((io_readAddr_5_addr == 5'h00) | (_wdata_5_value_1_T & |_writeValid_1_T)) | (_wdata_5_value_2_T & |_writeValid_2_T)) | (_wdata_5_value_3_T & |_writeValid_3_T)) | (_wdata_5_value_4_T & |_writeValid_4_T)) | (_wdata_5_value_5_T & |_writeValid_5_T)) | (_wdata_5_value_6_T & |_writeValid_6_T)) | (_wdata_5_value_7_T & |_writeValid_7_T)) | (_wdata_5_value_8_T & |_writeValid_8_T)) | (_wdata_5_value_9_T & |_writeValid_9_T)) | (_wdata_5_value_10_T & |_writeValid_10_T)) | (_wdata_5_value_11_T & |_writeValid_11_T)) | (_wdata_5_value_12_T & |_writeValid_12_T)) | (_wdata_5_value_13_T & |_writeValid_13_T)) | (_wdata_5_value_14_T & |_writeValid_14_T)) | (_wdata_5_value_15_T & |_writeValid_15_T)) | (_wdata_5_value_16_T & |_writeValid_16_T)) | (_wdata_5_value_17_T & |_writeValid_17_T)) | (_wdata_5_value_18_T & |_writeValid_18_T)) | (_wdata_5_value_19_T & |_writeValid_19_T)) | (_wdata_5_value_20_T & |_writeValid_20_T)) | (_wdata_5_value_21_T & |_writeValid_21_T)) | (_wdata_5_value_22_T & |_writeValid_22_T)) | (_wdata_5_value_23_T & |_writeValid_23_T)) | (_wdata_5_value_24_T & |_writeValid_24_T)) | (_wdata_5_value_25_T & |_writeValid_25_T)) | (_wdata_5_value_26_T & |_writeValid_26_T)) | (_wdata_5_value_27_T & |_writeValid_27_T)) | (_wdata_5_value_28_T & |_writeValid_28_T)) | (_wdata_5_value_29_T & |_writeValid_29_T)) | (_wdata_5_value_30_T & |_writeValid_30_T)) | (&io_readAddr_5_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_5_value_1_T ? data : 32'h00000000) | (_wdata_5_value_2_T ? data_1 : 32'h00000000)) | (_wdata_5_value_3_T ? data_2 : 32'h00000000)) | (_wdata_5_value_4_T ? data_3 : 32'h00000000)) | (_wdata_5_value_5_T ? data_4 : 32'h00000000)) | (_wdata_5_value_6_T ? data_5 : 32'h00000000)) | (_wdata_5_value_7_T ? data_6 : 32'h00000000)) | (_wdata_5_value_8_T ? data_7 : 32'h00000000)) | (_wdata_5_value_9_T ? data_8 : 32'h00000000)) | (_wdata_5_value_10_T ? data_9 : 32'h00000000)) | (_wdata_5_value_11_T ? data_10 : 32'h00000000)) | (_wdata_5_value_12_T ? data_11 : 32'h00000000)) | (_wdata_5_value_13_T ? data_12 : 32'h00000000)) | (_wdata_5_value_14_T ? data_13 : 32'h00000000)) | (_wdata_5_value_15_T ? data_14 : 32'h00000000)) | (_wdata_5_value_16_T ? data_15 : 32'h00000000)) | (_wdata_5_value_17_T ? data_16 : 32'h00000000)) | (_wdata_5_value_18_T ? data_17 : 32'h00000000)) | (_wdata_5_value_19_T ? data_18 : 32'h00000000)) | (_wdata_5_value_20_T ? data_19 : 32'h00000000)) | (_wdata_5_value_21_T ? data_20 : 32'h00000000)) | (_wdata_5_value_22_T ? data_21 : 32'h00000000)) | (_wdata_5_value_23_T ? data_22 : 32'h00000000)) | (_wdata_5_value_24_T ? data_23 : 32'h00000000)) | (_wdata_5_value_25_T ? data_24 : 32'h00000000)) | (_wdata_5_value_26_T ? data_25 : 32'h00000000)) | (_wdata_5_value_27_T ? data_26 : 32'h00000000)) | (_wdata_5_value_28_T ? data_27 : 32'h00000000)) | (_wdata_5_value_29_T ? data_28 : 32'h00000000)) | (_wdata_5_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_5_addr ? data_30 : 32'h00000000) : ((((((((((((((((((((((((((((((_wdata_5_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_5_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_5_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_5_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_5_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_5_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_5_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_5_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_5_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_5_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_5_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_5_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_5_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_5_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_5_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_5_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_5_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_5_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_5_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_5_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_5_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_5_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_5_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_5_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_5_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_5_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_5_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_5_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_5_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_5_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_5_addr ? regfile_31 : 32'h00000000)); + wire _wdata_6_value_1_T = io_readAddr_6_addr == 5'h01; + wire _wdata_6_value_2_T = io_readAddr_6_addr == 5'h02; + wire _wdata_6_value_3_T = io_readAddr_6_addr == 5'h03; + wire _wdata_6_value_4_T = io_readAddr_6_addr == 5'h04; + wire _wdata_6_value_5_T = io_readAddr_6_addr == 5'h05; + wire _wdata_6_value_6_T = io_readAddr_6_addr == 5'h06; + wire _wdata_6_value_7_T = io_readAddr_6_addr == 5'h07; + wire _wdata_6_value_8_T = io_readAddr_6_addr == 5'h08; + wire _wdata_6_value_9_T = io_readAddr_6_addr == 5'h09; + wire _wdata_6_value_10_T = io_readAddr_6_addr == 5'h0a; + wire _wdata_6_value_11_T = io_readAddr_6_addr == 5'h0b; + wire _wdata_6_value_12_T = io_readAddr_6_addr == 5'h0c; + wire _wdata_6_value_13_T = io_readAddr_6_addr == 5'h0d; + wire _wdata_6_value_14_T = io_readAddr_6_addr == 5'h0e; + wire _wdata_6_value_15_T = io_readAddr_6_addr == 5'h0f; + wire _wdata_6_value_16_T = io_readAddr_6_addr == 5'h10; + wire _wdata_6_value_17_T = io_readAddr_6_addr == 5'h11; + wire _wdata_6_value_18_T = io_readAddr_6_addr == 5'h12; + wire _wdata_6_value_19_T = io_readAddr_6_addr == 5'h13; + wire _wdata_6_value_20_T = io_readAddr_6_addr == 5'h14; + wire _wdata_6_value_21_T = io_readAddr_6_addr == 5'h15; + wire _wdata_6_value_22_T = io_readAddr_6_addr == 5'h16; + wire _wdata_6_value_23_T = io_readAddr_6_addr == 5'h17; + wire _wdata_6_value_24_T = io_readAddr_6_addr == 5'h18; + wire _wdata_6_value_25_T = io_readAddr_6_addr == 5'h19; + wire _wdata_6_value_26_T = io_readAddr_6_addr == 5'h1a; + wire _wdata_6_value_27_T = io_readAddr_6_addr == 5'h1b; + wire _wdata_6_value_28_T = io_readAddr_6_addr == 5'h1c; + wire _wdata_6_value_29_T = io_readAddr_6_addr == 5'h1d; + wire _wdata_6_value_30_T = io_readAddr_6_addr == 5'h1e; + wire [31:0] rdata_6_value_5_0 = ((((((((((((((((((((((((((((((_wdata_6_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_6_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_6_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_6_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_6_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_6_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_6_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_6_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_6_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_6_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_6_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_6_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_6_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_6_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_6_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_6_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_6_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_6_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_6_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_6_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_6_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_6_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_6_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_6_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_6_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_6_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_6_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_6_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_6_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_6_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_6_addr ? regfile_31 : 32'h00000000); + wire [31:0] rwdata_6 = ((((((((((((((((((((((((((((((((io_readAddr_6_addr == 5'h00) | (_wdata_6_value_1_T & |_writeValid_1_T)) | (_wdata_6_value_2_T & |_writeValid_2_T)) | (_wdata_6_value_3_T & |_writeValid_3_T)) | (_wdata_6_value_4_T & |_writeValid_4_T)) | (_wdata_6_value_5_T & |_writeValid_5_T)) | (_wdata_6_value_6_T & |_writeValid_6_T)) | (_wdata_6_value_7_T & |_writeValid_7_T)) | (_wdata_6_value_8_T & |_writeValid_8_T)) | (_wdata_6_value_9_T & |_writeValid_9_T)) | (_wdata_6_value_10_T & |_writeValid_10_T)) | (_wdata_6_value_11_T & |_writeValid_11_T)) | (_wdata_6_value_12_T & |_writeValid_12_T)) | (_wdata_6_value_13_T & |_writeValid_13_T)) | (_wdata_6_value_14_T & |_writeValid_14_T)) | (_wdata_6_value_15_T & |_writeValid_15_T)) | (_wdata_6_value_16_T & |_writeValid_16_T)) | (_wdata_6_value_17_T & |_writeValid_17_T)) | (_wdata_6_value_18_T & |_writeValid_18_T)) | (_wdata_6_value_19_T & |_writeValid_19_T)) | (_wdata_6_value_20_T & |_writeValid_20_T)) | (_wdata_6_value_21_T & |_writeValid_21_T)) | (_wdata_6_value_22_T & |_writeValid_22_T)) | (_wdata_6_value_23_T & |_writeValid_23_T)) | (_wdata_6_value_24_T & |_writeValid_24_T)) | (_wdata_6_value_25_T & |_writeValid_25_T)) | (_wdata_6_value_26_T & |_writeValid_26_T)) | (_wdata_6_value_27_T & |_writeValid_27_T)) | (_wdata_6_value_28_T & |_writeValid_28_T)) | (_wdata_6_value_29_T & |_writeValid_29_T)) | (_wdata_6_value_30_T & |_writeValid_30_T)) | (&io_readAddr_6_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_6_value_1_T ? data : 32'h00000000) | (_wdata_6_value_2_T ? data_1 : 32'h00000000)) | (_wdata_6_value_3_T ? data_2 : 32'h00000000)) | (_wdata_6_value_4_T ? data_3 : 32'h00000000)) | (_wdata_6_value_5_T ? data_4 : 32'h00000000)) | (_wdata_6_value_6_T ? data_5 : 32'h00000000)) | (_wdata_6_value_7_T ? data_6 : 32'h00000000)) | (_wdata_6_value_8_T ? data_7 : 32'h00000000)) | (_wdata_6_value_9_T ? data_8 : 32'h00000000)) | (_wdata_6_value_10_T ? data_9 : 32'h00000000)) | (_wdata_6_value_11_T ? data_10 : 32'h00000000)) | (_wdata_6_value_12_T ? data_11 : 32'h00000000)) | (_wdata_6_value_13_T ? data_12 : 32'h00000000)) | (_wdata_6_value_14_T ? data_13 : 32'h00000000)) | (_wdata_6_value_15_T ? data_14 : 32'h00000000)) | (_wdata_6_value_16_T ? data_15 : 32'h00000000)) | (_wdata_6_value_17_T ? data_16 : 32'h00000000)) | (_wdata_6_value_18_T ? data_17 : 32'h00000000)) | (_wdata_6_value_19_T ? data_18 : 32'h00000000)) | (_wdata_6_value_20_T ? data_19 : 32'h00000000)) | (_wdata_6_value_21_T ? data_20 : 32'h00000000)) | (_wdata_6_value_22_T ? data_21 : 32'h00000000)) | (_wdata_6_value_23_T ? data_22 : 32'h00000000)) | (_wdata_6_value_24_T ? data_23 : 32'h00000000)) | (_wdata_6_value_25_T ? data_24 : 32'h00000000)) | (_wdata_6_value_26_T ? data_25 : 32'h00000000)) | (_wdata_6_value_27_T ? data_26 : 32'h00000000)) | (_wdata_6_value_28_T ? data_27 : 32'h00000000)) | (_wdata_6_value_29_T ? data_28 : 32'h00000000)) | (_wdata_6_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_6_addr ? data_30 : 32'h00000000) : rdata_6_value_5_0); + wire _wdata_7_value_1_T = io_readAddr_7_addr == 5'h01; + wire _wdata_7_value_2_T = io_readAddr_7_addr == 5'h02; + wire _wdata_7_value_3_T = io_readAddr_7_addr == 5'h03; + wire _wdata_7_value_4_T = io_readAddr_7_addr == 5'h04; + wire _wdata_7_value_5_T = io_readAddr_7_addr == 5'h05; + wire _wdata_7_value_6_T = io_readAddr_7_addr == 5'h06; + wire _wdata_7_value_7_T = io_readAddr_7_addr == 5'h07; + wire _wdata_7_value_8_T = io_readAddr_7_addr == 5'h08; + wire _wdata_7_value_9_T = io_readAddr_7_addr == 5'h09; + wire _wdata_7_value_10_T = io_readAddr_7_addr == 5'h0a; + wire _wdata_7_value_11_T = io_readAddr_7_addr == 5'h0b; + wire _wdata_7_value_12_T = io_readAddr_7_addr == 5'h0c; + wire _wdata_7_value_13_T = io_readAddr_7_addr == 5'h0d; + wire _wdata_7_value_14_T = io_readAddr_7_addr == 5'h0e; + wire _wdata_7_value_15_T = io_readAddr_7_addr == 5'h0f; + wire _wdata_7_value_16_T = io_readAddr_7_addr == 5'h10; + wire _wdata_7_value_17_T = io_readAddr_7_addr == 5'h11; + wire _wdata_7_value_18_T = io_readAddr_7_addr == 5'h12; + wire _wdata_7_value_19_T = io_readAddr_7_addr == 5'h13; + wire _wdata_7_value_20_T = io_readAddr_7_addr == 5'h14; + wire _wdata_7_value_21_T = io_readAddr_7_addr == 5'h15; + wire _wdata_7_value_22_T = io_readAddr_7_addr == 5'h16; + wire _wdata_7_value_23_T = io_readAddr_7_addr == 5'h17; + wire _wdata_7_value_24_T = io_readAddr_7_addr == 5'h18; + wire _wdata_7_value_25_T = io_readAddr_7_addr == 5'h19; + wire _wdata_7_value_26_T = io_readAddr_7_addr == 5'h1a; + wire _wdata_7_value_27_T = io_readAddr_7_addr == 5'h1b; + wire _wdata_7_value_28_T = io_readAddr_7_addr == 5'h1c; + wire _wdata_7_value_29_T = io_readAddr_7_addr == 5'h1d; + wire _wdata_7_value_30_T = io_readAddr_7_addr == 5'h1e; + wire [31:0] rwdata_7 = ((((((((((((((((((((((((((((((((io_readAddr_7_addr == 5'h00) | (_wdata_7_value_1_T & |_writeValid_1_T)) | (_wdata_7_value_2_T & |_writeValid_2_T)) | (_wdata_7_value_3_T & |_writeValid_3_T)) | (_wdata_7_value_4_T & |_writeValid_4_T)) | (_wdata_7_value_5_T & |_writeValid_5_T)) | (_wdata_7_value_6_T & |_writeValid_6_T)) | (_wdata_7_value_7_T & |_writeValid_7_T)) | (_wdata_7_value_8_T & |_writeValid_8_T)) | (_wdata_7_value_9_T & |_writeValid_9_T)) | (_wdata_7_value_10_T & |_writeValid_10_T)) | (_wdata_7_value_11_T & |_writeValid_11_T)) | (_wdata_7_value_12_T & |_writeValid_12_T)) | (_wdata_7_value_13_T & |_writeValid_13_T)) | (_wdata_7_value_14_T & |_writeValid_14_T)) | (_wdata_7_value_15_T & |_writeValid_15_T)) | (_wdata_7_value_16_T & |_writeValid_16_T)) | (_wdata_7_value_17_T & |_writeValid_17_T)) | (_wdata_7_value_18_T & |_writeValid_18_T)) | (_wdata_7_value_19_T & |_writeValid_19_T)) | (_wdata_7_value_20_T & |_writeValid_20_T)) | (_wdata_7_value_21_T & |_writeValid_21_T)) | (_wdata_7_value_22_T & |_writeValid_22_T)) | (_wdata_7_value_23_T & |_writeValid_23_T)) | (_wdata_7_value_24_T & |_writeValid_24_T)) | (_wdata_7_value_25_T & |_writeValid_25_T)) | (_wdata_7_value_26_T & |_writeValid_26_T)) | (_wdata_7_value_27_T & |_writeValid_27_T)) | (_wdata_7_value_28_T & |_writeValid_28_T)) | (_wdata_7_value_29_T & |_writeValid_29_T)) | (_wdata_7_value_30_T & |_writeValid_30_T)) | (&io_readAddr_7_addr & |_writeValid_31_T) ? ((((((((((((((((((((((((((((((_wdata_7_value_1_T ? data : 32'h00000000) | (_wdata_7_value_2_T ? data_1 : 32'h00000000)) | (_wdata_7_value_3_T ? data_2 : 32'h00000000)) | (_wdata_7_value_4_T ? data_3 : 32'h00000000)) | (_wdata_7_value_5_T ? data_4 : 32'h00000000)) | (_wdata_7_value_6_T ? data_5 : 32'h00000000)) | (_wdata_7_value_7_T ? data_6 : 32'h00000000)) | (_wdata_7_value_8_T ? data_7 : 32'h00000000)) | (_wdata_7_value_9_T ? data_8 : 32'h00000000)) | (_wdata_7_value_10_T ? data_9 : 32'h00000000)) | (_wdata_7_value_11_T ? data_10 : 32'h00000000)) | (_wdata_7_value_12_T ? data_11 : 32'h00000000)) | (_wdata_7_value_13_T ? data_12 : 32'h00000000)) | (_wdata_7_value_14_T ? data_13 : 32'h00000000)) | (_wdata_7_value_15_T ? data_14 : 32'h00000000)) | (_wdata_7_value_16_T ? data_15 : 32'h00000000)) | (_wdata_7_value_17_T ? data_16 : 32'h00000000)) | (_wdata_7_value_18_T ? data_17 : 32'h00000000)) | (_wdata_7_value_19_T ? data_18 : 32'h00000000)) | (_wdata_7_value_20_T ? data_19 : 32'h00000000)) | (_wdata_7_value_21_T ? data_20 : 32'h00000000)) | (_wdata_7_value_22_T ? data_21 : 32'h00000000)) | (_wdata_7_value_23_T ? data_22 : 32'h00000000)) | (_wdata_7_value_24_T ? data_23 : 32'h00000000)) | (_wdata_7_value_25_T ? data_24 : 32'h00000000)) | (_wdata_7_value_26_T ? data_25 : 32'h00000000)) | (_wdata_7_value_27_T ? data_26 : 32'h00000000)) | (_wdata_7_value_28_T ? data_27 : 32'h00000000)) | (_wdata_7_value_29_T ? data_28 : 32'h00000000)) | (_wdata_7_value_30_T ? data_29 : 32'h00000000)) | (&io_readAddr_7_addr ? data_30 : 32'h00000000) : ((((((((((((((((((((((((((((((_wdata_7_value_1_T ? regfile_1 : 32'h00000000) | (_wdata_7_value_2_T ? regfile_2 : 32'h00000000)) | (_wdata_7_value_3_T ? regfile_3 : 32'h00000000)) | (_wdata_7_value_4_T ? regfile_4 : 32'h00000000)) | (_wdata_7_value_5_T ? regfile_5 : 32'h00000000)) | (_wdata_7_value_6_T ? regfile_6 : 32'h00000000)) | (_wdata_7_value_7_T ? regfile_7 : 32'h00000000)) | (_wdata_7_value_8_T ? regfile_8 : 32'h00000000)) | (_wdata_7_value_9_T ? regfile_9 : 32'h00000000)) | (_wdata_7_value_10_T ? regfile_10 : 32'h00000000)) | (_wdata_7_value_11_T ? regfile_11 : 32'h00000000)) | (_wdata_7_value_12_T ? regfile_12 : 32'h00000000)) | (_wdata_7_value_13_T ? regfile_13 : 32'h00000000)) | (_wdata_7_value_14_T ? regfile_14 : 32'h00000000)) | (_wdata_7_value_15_T ? regfile_15 : 32'h00000000)) | (_wdata_7_value_16_T ? regfile_16 : 32'h00000000)) | (_wdata_7_value_17_T ? regfile_17 : 32'h00000000)) | (_wdata_7_value_18_T ? regfile_18 : 32'h00000000)) | (_wdata_7_value_19_T ? regfile_19 : 32'h00000000)) | (_wdata_7_value_20_T ? regfile_20 : 32'h00000000)) | (_wdata_7_value_21_T ? regfile_21 : 32'h00000000)) | (_wdata_7_value_22_T ? regfile_22 : 32'h00000000)) | (_wdata_7_value_23_T ? regfile_23 : 32'h00000000)) | (_wdata_7_value_24_T ? regfile_24 : 32'h00000000)) | (_wdata_7_value_25_T ? regfile_25 : 32'h00000000)) | (_wdata_7_value_26_T ? regfile_26 : 32'h00000000)) | (_wdata_7_value_27_T ? regfile_27 : 32'h00000000)) | (_wdata_7_value_28_T ? regfile_28 : 32'h00000000)) | (_wdata_7_value_29_T ? regfile_29 : 32'h00000000)) | (_wdata_7_value_30_T ? regfile_30 : 32'h00000000)) | (&io_readAddr_7_addr ? regfile_31 : 32'h00000000)); + wire [31:0] busAddr_0 = (io_busAddr_0_bypass ? rwdata_0 : (io_busAddr_0_immen ? rdata_0_value_5_0 + io_busAddr_0_immed : rdata_0_value_5_0)); + wire [31:0] busAddr_1 = (io_busAddr_1_bypass ? rwdata_2 : rdata_2_value_5_0 + io_busAddr_1_immed); + wire [31:0] busAddr_2 = (io_busAddr_2_bypass ? rwdata_4 : rdata_4_value_5_0 + io_busAddr_2_immed); + wire [31:0] busAddr_3 = (io_busAddr_3_bypass ? rwdata_6 : rdata_6_value_5_0 + io_busAddr_3_immed); + reg write_fail; + reg write_fail_1; + reg write_fail_2; + reg write_fail_3; + reg write_fail_4; + reg write_fail_5; + reg write_fail_6; + reg write_fail_7; + reg write_fail_8; + reg write_fail_9; + reg write_fail_10; + reg write_fail_11; + reg write_fail_12; + reg write_fail_13; + reg write_fail_14; + reg scoreboard_error; + wire [31:0] scoreboard_set = (((io_writeAddr_0_valid ? 32'h00000001 << io_writeAddr_0_addr : 32'h00000000) | (io_writeAddr_1_valid ? 32'h00000001 << io_writeAddr_1_addr : 32'h00000000)) | (io_writeAddr_2_valid ? 32'h00000001 << io_writeAddr_2_addr : 32'h00000000)) | (io_writeAddr_3_valid ? 32'h00000001 << io_writeAddr_3_addr : 32'h00000000); + wire [31:0] scoreboard_clr = {scoreboard_clr0, 1'h0}; + always @(posedge clock or posedge reset) + if (reset) begin + regfile_1 <= 32'h00000000; + regfile_2 <= 32'h00000000; + regfile_3 <= 32'h00000000; + regfile_4 <= 32'h00000000; + regfile_5 <= 32'h00000000; + regfile_6 <= 32'h00000000; + regfile_7 <= 32'h00000000; + regfile_8 <= 32'h00000000; + regfile_9 <= 32'h00000000; + regfile_10 <= 32'h00000000; + regfile_11 <= 32'h00000000; + regfile_12 <= 32'h00000000; + regfile_13 <= 32'h00000000; + regfile_14 <= 32'h00000000; + regfile_15 <= 32'h00000000; + regfile_16 <= 32'h00000000; + regfile_17 <= 32'h00000000; + regfile_18 <= 32'h00000000; + regfile_19 <= 32'h00000000; + regfile_20 <= 32'h00000000; + regfile_21 <= 32'h00000000; + regfile_22 <= 32'h00000000; + regfile_23 <= 32'h00000000; + regfile_24 <= 32'h00000000; + regfile_25 <= 32'h00000000; + regfile_26 <= 32'h00000000; + regfile_27 <= 32'h00000000; + regfile_28 <= 32'h00000000; + regfile_29 <= 32'h00000000; + regfile_30 <= 32'h00000000; + regfile_31 <= 32'h00000000; + scoreboard <= 32'h00000000; + readDataReady_0 <= 1'h0; + readDataReady_1 <= 1'h0; + readDataReady_2 <= 1'h0; + readDataReady_3 <= 1'h0; + readDataReady_4 <= 1'h0; + readDataReady_5 <= 1'h0; + readDataReady_6 <= 1'h0; + readDataReady_7 <= 1'h0; + readDataBits_0 <= 32'h00000000; + readDataBits_1 <= 32'h00000000; + readDataBits_2 <= 32'h00000000; + readDataBits_3 <= 32'h00000000; + readDataBits_4 <= 32'h00000000; + readDataBits_5 <= 32'h00000000; + readDataBits_6 <= 32'h00000000; + readDataBits_7 <= 32'h00000000; + write_fail <= 1'h0; + write_fail_1 <= 1'h0; + write_fail_2 <= 1'h0; + write_fail_3 <= 1'h0; + write_fail_4 <= 1'h0; + write_fail_5 <= 1'h0; + write_fail_6 <= 1'h0; + write_fail_7 <= 1'h0; + write_fail_8 <= 1'h0; + write_fail_9 <= 1'h0; + write_fail_10 <= 1'h0; + write_fail_11 <= 1'h0; + write_fail_12 <= 1'h0; + write_fail_13 <= 1'h0; + write_fail_14 <= 1'h0; + scoreboard_error <= 1'h0; + end + else begin + if (|_writeValid_1_T) + regfile_1 <= data; + if (|_writeValid_2_T) + regfile_2 <= data_1; + if (|_writeValid_3_T) + regfile_3 <= data_2; + if (|_writeValid_4_T) + regfile_4 <= data_3; + if (|_writeValid_5_T) + regfile_5 <= data_4; + if (|_writeValid_6_T) + regfile_6 <= data_5; + if (|_writeValid_7_T) + regfile_7 <= data_6; + if (|_writeValid_8_T) + regfile_8 <= data_7; + if (|_writeValid_9_T) + regfile_9 <= data_8; + if (|_writeValid_10_T) + regfile_10 <= data_9; + if (|_writeValid_11_T) + regfile_11 <= data_10; + if (|_writeValid_12_T) + regfile_12 <= data_11; + if (|_writeValid_13_T) + regfile_13 <= data_12; + if (|_writeValid_14_T) + regfile_14 <= data_13; + if (|_writeValid_15_T) + regfile_15 <= data_14; + if (|_writeValid_16_T) + regfile_16 <= data_15; + if (|_writeValid_17_T) + regfile_17 <= data_16; + if (|_writeValid_18_T) + regfile_18 <= data_17; + if (|_writeValid_19_T) + regfile_19 <= data_18; + if (|_writeValid_20_T) + regfile_20 <= data_19; + if (|_writeValid_21_T) + regfile_21 <= data_20; + if (|_writeValid_22_T) + regfile_22 <= data_21; + if (|_writeValid_23_T) + regfile_23 <= data_22; + if (|_writeValid_24_T) + regfile_24 <= data_23; + if (|_writeValid_25_T) + regfile_25 <= data_24; + if (|_writeValid_26_T) + regfile_26 <= data_25; + if (|_writeValid_27_T) + regfile_27 <= data_26; + if (|_writeValid_28_T) + regfile_28 <= data_27; + if (|_writeValid_29_T) + regfile_29 <= data_28; + if (|_writeValid_30_T) + regfile_30 <= data_29; + if (|_writeValid_31_T) + regfile_31 <= data_30; + if (|{scoreboard_set, scoreboard_clr0}) + scoreboard <= {(scoreboard[31:1] & ~scoreboard_clr0) | scoreboard_set[31:1], 1'h0}; + readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid; + readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid; + readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid; + readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid; + readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid; + readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid; + readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid; + readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid; + if (io_readSet_0_valid) + readDataBits_0 <= io_readSet_0_value; + else if (io_readAddr_0_valid) + readDataBits_0 <= rwdata_0; + if (io_readSet_1_valid) + readDataBits_1 <= io_readSet_1_value; + else if (io_readAddr_1_valid) + readDataBits_1 <= rwdata_1; + if (io_readSet_2_valid) + readDataBits_2 <= io_readSet_2_value; + else if (io_readAddr_2_valid) + readDataBits_2 <= rwdata_2; + if (io_readSet_3_valid) + readDataBits_3 <= io_readSet_3_value; + else if (io_readAddr_3_valid) + readDataBits_3 <= rwdata_3; + if (io_readSet_4_valid) + readDataBits_4 <= io_readSet_4_value; + else if (io_readAddr_4_valid) + readDataBits_4 <= rwdata_4; + if (io_readSet_5_valid) + readDataBits_5 <= io_readSet_5_value; + else if (io_readAddr_5_valid) + readDataBits_5 <= rwdata_5; + if (io_readSet_6_valid) + readDataBits_6 <= io_readSet_6_value; + else if (io_readAddr_6_valid) + readDataBits_6 <= rwdata_6; + if (io_readSet_7_valid) + readDataBits_7 <= io_readSet_7_value; + else if (io_readAddr_7_valid) + readDataBits_7 <= rwdata_7; + write_fail <= ((io_writeData_0_valid & io_writeData_1_valid) & (io_writeData_0_bits_addr == io_writeData_1_bits_addr)) & |io_writeData_0_bits_addr; + write_fail_1 <= ((io_writeData_0_valid & io_writeData_2_valid) & (io_writeData_0_bits_addr == io_writeData_2_bits_addr)) & |io_writeData_0_bits_addr; + write_fail_2 <= ((io_writeData_0_valid & io_writeData_3_valid) & (io_writeData_0_bits_addr == io_writeData_3_bits_addr)) & |io_writeData_0_bits_addr; + write_fail_3 <= ((io_writeData_0_valid & io_writeData_4_valid) & (io_writeData_0_bits_addr == io_writeData_4_bits_addr)) & |io_writeData_0_bits_addr; + write_fail_4 <= ((io_writeData_0_valid & io_writeData_5_valid) & (io_writeData_0_bits_addr == io_writeData_5_bits_addr)) & |io_writeData_0_bits_addr; + write_fail_5 <= ((io_writeData_1_valid & io_writeData_2_valid) & (io_writeData_1_bits_addr == io_writeData_2_bits_addr)) & |io_writeData_1_bits_addr; + write_fail_6 <= ((io_writeData_1_valid & io_writeData_3_valid) & (io_writeData_1_bits_addr == io_writeData_3_bits_addr)) & |io_writeData_1_bits_addr; + write_fail_7 <= ((io_writeData_1_valid & io_writeData_4_valid) & (io_writeData_1_bits_addr == io_writeData_4_bits_addr)) & |io_writeData_1_bits_addr; + write_fail_8 <= ((io_writeData_1_valid & io_writeData_5_valid) & (io_writeData_1_bits_addr == io_writeData_5_bits_addr)) & |io_writeData_1_bits_addr; + write_fail_9 <= ((io_writeData_2_valid & io_writeData_3_valid) & (io_writeData_2_bits_addr == io_writeData_3_bits_addr)) & |io_writeData_2_bits_addr; + write_fail_10 <= ((io_writeData_2_valid & io_writeData_4_valid) & (io_writeData_2_bits_addr == io_writeData_4_bits_addr)) & |io_writeData_2_bits_addr; + write_fail_11 <= ((io_writeData_2_valid & io_writeData_5_valid) & (io_writeData_2_bits_addr == io_writeData_5_bits_addr)) & |io_writeData_2_bits_addr; + write_fail_12 <= ((io_writeData_3_valid & io_writeData_4_valid) & (io_writeData_3_bits_addr == io_writeData_4_bits_addr)) & |io_writeData_3_bits_addr; + write_fail_13 <= ((io_writeData_3_valid & io_writeData_5_valid) & (io_writeData_3_bits_addr == io_writeData_5_bits_addr)) & |io_writeData_3_bits_addr; + write_fail_14 <= ((io_writeData_4_valid & io_writeData_5_valid) & (io_writeData_4_bits_addr == io_writeData_5_bits_addr)) & |io_writeData_4_bits_addr; + scoreboard_error <= (scoreboard & scoreboard_clr) != scoreboard_clr; + end + assign io_target_0_data = busAddr_0; + assign io_target_1_data = busAddr_1; + assign io_target_2_data = busAddr_2; + assign io_target_3_data = busAddr_3; + assign io_busPort_addr_0 = busAddr_0; + assign io_busPort_addr_1 = busAddr_1; + assign io_busPort_addr_2 = busAddr_2; + assign io_busPort_addr_3 = busAddr_3; + assign io_busPort_data_0 = (io_readSet_1_valid ? io_readSet_1_value : rwdata_1); + assign io_busPort_data_1 = (io_readSet_3_valid ? io_readSet_3_value : rwdata_3); + assign io_busPort_data_2 = (io_readSet_5_valid ? io_readSet_5_value : rwdata_5); + assign io_busPort_data_3 = (io_readSet_7_valid ? io_readSet_7_value : rwdata_7); + assign io_readData_0_valid = readDataReady_0; + assign io_readData_0_data = readDataBits_0; + assign io_readData_1_valid = readDataReady_1; + assign io_readData_1_data = readDataBits_1; + assign io_readData_2_valid = readDataReady_2; + assign io_readData_2_data = readDataBits_2; + assign io_readData_3_valid = readDataReady_3; + assign io_readData_3_data = readDataBits_3; + assign io_readData_4_valid = readDataReady_4; + assign io_readData_4_data = readDataBits_4; + assign io_readData_5_valid = readDataReady_5; + assign io_readData_5_data = readDataBits_5; + assign io_readData_6_valid = readDataReady_6; + assign io_readData_6_data = readDataBits_6; + assign io_readData_7_valid = readDataReady_7; + assign io_readData_7_data = readDataBits_7; + assign io_scoreboard_regd = scoreboard; + assign io_scoreboard_comb = scoreboard & {~scoreboard_clr0, 1'h1}; +endmodule +module FetchControl ( + clock, + reset, + io_fetchFault_valid, + io_fetchFault_bits, + io_csr_value_0, + io_iflush_valid, + io_iflush_bits, + io_branch_valid, + io_branch_bits, + io_fetchData_valid, + io_fetchData_bits_addr, + io_fetchData_bits_inst_0, + io_fetchData_bits_inst_1, + io_fetchData_bits_inst_2, + io_fetchData_bits_inst_3, + io_fetchData_bits_fault, + io_fetchAddr_valid, + io_fetchAddr_bits, + io_bufferRequest_nValid, + io_bufferRequest_bits_0_addr, + io_bufferRequest_bits_0_inst, + io_bufferRequest_bits_0_brchFwd, + io_bufferRequest_bits_1_addr, + io_bufferRequest_bits_1_inst, + io_bufferRequest_bits_1_brchFwd, + io_bufferRequest_bits_2_addr, + io_bufferRequest_bits_2_inst, + io_bufferRequest_bits_2_brchFwd, + io_bufferRequest_bits_3_addr, + io_bufferRequest_bits_3_inst, + io_bufferRequest_bits_3_brchFwd, + io_bufferSpaces +); + input clock; + input reset; + output wire io_fetchFault_valid; + output wire [31:0] io_fetchFault_bits; + input [31:0] io_csr_value_0; + input io_iflush_valid; + input [31:0] io_iflush_bits; + input io_branch_valid; + input [31:0] io_branch_bits; + input io_fetchData_valid; + input [31:0] io_fetchData_bits_addr; + input [31:0] io_fetchData_bits_inst_0; + input [31:0] io_fetchData_bits_inst_1; + input [31:0] io_fetchData_bits_inst_2; + input [31:0] io_fetchData_bits_inst_3; + input io_fetchData_bits_fault; + output wire io_fetchAddr_valid; + output wire [31:0] io_fetchAddr_bits; + output wire [2:0] io_bufferRequest_nValid; + output wire [31:0] io_bufferRequest_bits_0_addr; + output wire [31:0] io_bufferRequest_bits_0_inst; + output wire io_bufferRequest_bits_0_brchFwd; + output wire [31:0] io_bufferRequest_bits_1_addr; + output wire [31:0] io_bufferRequest_bits_1_inst; + output wire io_bufferRequest_bits_1_brchFwd; + output wire [31:0] io_bufferRequest_bits_2_addr; + output wire [31:0] io_bufferRequest_bits_2_inst; + output wire io_bufferRequest_bits_2_brchFwd; + output wire [31:0] io_bufferRequest_bits_3_addr; + output wire [31:0] io_bufferRequest_bits_3_inst; + output wire io_bufferRequest_bits_3_brchFwd; + input [3:0] io_bufferSpaces; + wire [127:0] predecode_insts_shifted = {io_fetchData_bits_inst_3, io_fetchData_bits_inst_2, io_fetchData_bits_inst_1, io_fetchData_bits_inst_0} >> {121'h0000000000000000000000000000000, io_fetchData_bits_addr[3:2], 5'h00}; + wire [31:0] predecode_addrs_1 = io_fetchData_bits_addr + 32'h00000004; + wire [31:0] predecode_addrs_2 = io_fetchData_bits_addr + 32'h00000008; + wire [31:0] predecode_addrs_3 = io_fetchData_bits_addr + 32'h0000000c; + wire [2:0] _predecode_validsIn_T_9 = 3'h4 - {1'h0, io_fetchData_bits_addr[3:2]}; + wire predecode_validsIn_2 = _predecode_validsIn_T_9 > 3'h2; + wire predecode_jumped_0 = |_predecode_validsIn_T_9 & ((predecode_insts_shifted[6:0] == 7'h6f) | (((predecode_insts_shifted[6:0] == 7'h63) & predecode_insts_shifted[31]) & (predecode_insts_shifted[14:13] != 2'h1))); + wire predecode_jumped_1 = |_predecode_validsIn_T_9[2:1] & ((predecode_insts_shifted[38:32] == 7'h6f) | (((predecode_insts_shifted[38:32] == 7'h63) & predecode_insts_shifted[63]) & (predecode_insts_shifted[46:45] != 2'h1))); + wire predecode_jumped_2 = predecode_validsIn_2 & ((predecode_insts_shifted[70:64] == 7'h6f) | (((predecode_insts_shifted[70:64] == 7'h63) & predecode_insts_shifted[95]) & (predecode_insts_shifted[78:77] != 2'h1))); + wire predecode_jumped_3 = _predecode_validsIn_T_9[2] & ((predecode_insts_shifted[102:96] == 7'h6f) | (((predecode_insts_shifted[102:96] == 7'h63) & predecode_insts_shifted[127]) & (predecode_insts_shifted[110:109] != 2'h1))); + wire [3:0] predecode_firstJumpOH_enc = (predecode_jumped_0 ? 4'h1 : (predecode_jumped_1 ? 4'h2 : (predecode_jumped_2 ? 4'h4 : {predecode_jumped_3, 3'h0}))); + wire predecode_hasJumpedBefore_2 = predecode_jumped_0 | predecode_jumped_1; + reg pastBranchOrFlush; + wire currentBranchOrFlush = io_iflush_valid | io_branch_valid; + wire ongoingBranchOrFlush = pastBranchOrFlush | currentBranchOrFlush; + reg faulted; + wire fetchFaultValid = (faulted | (io_fetchData_valid & io_fetchData_bits_fault)) & ~io_branch_valid; + wire writeToBuffer = (io_fetchData_valid & ~fetchFaultValid) & ~ongoingBranchOrFlush; + wire [3:0] nValid = (writeToBuffer ? {1'h0, {1'h0, {1'h0, |_predecode_validsIn_T_9} + {1'h0, |_predecode_validsIn_T_9[2:1] & ~predecode_jumped_0}} + {1'h0, {1'h0, predecode_validsIn_2 & ~predecode_hasJumpedBefore_2} + {1'h0, _predecode_validsIn_T_9[2] & ~(predecode_hasJumpedBefore_2 | predecode_jumped_2)}}} : 4'h0); + reg pc_valid; + reg [31:0] pc_bits; + wire blockNewFetch = (((~pc_valid | io_fetchData_valid) | currentBranchOrFlush) | ({1'h0, io_bufferSpaces} < ({1'h0, nValid} + 5'h04))) | fetchFaultValid; + always @(posedge clock or posedge reset) + if (reset) begin + pastBranchOrFlush <= 1'h0; + faulted <= 1'h0; + pc_valid <= 1'h0; + pc_bits <= 32'h00000000; + end + else begin + pastBranchOrFlush <= ongoingBranchOrFlush & blockNewFetch; + faulted <= fetchFaultValid; + pc_valid <= 1'h1; + if (pc_valid) begin + if (io_iflush_valid) + pc_bits <= io_iflush_bits; + else if (io_branch_valid) + pc_bits <= io_branch_bits; + else if (writeToBuffer) + pc_bits <= ((((predecode_firstJumpOH_enc[0] ? io_fetchData_bits_addr + {{12 {predecode_insts_shifted[31]}}, (predecode_insts_shifted[2] ? {predecode_insts_shifted[19:12], predecode_insts_shifted[20], predecode_insts_shifted[30:21]} : {{8 {predecode_insts_shifted[31]}}, predecode_insts_shifted[7], predecode_insts_shifted[30:25], predecode_insts_shifted[11:8]}), 1'h0} : 32'h00000000) | (predecode_firstJumpOH_enc[1] ? predecode_addrs_1 + {{12 {predecode_insts_shifted[63]}}, (predecode_insts_shifted[34] ? {predecode_insts_shifted[51:44], predecode_insts_shifted[52], predecode_insts_shifted[62:53]} : {{8 {predecode_insts_shifted[63]}}, predecode_insts_shifted[39], predecode_insts_shifted[62:57], predecode_insts_shifted[43:40]}), 1'h0} : 32'h00000000)) | (predecode_firstJumpOH_enc[2] ? predecode_addrs_2 + {{12 {predecode_insts_shifted[95]}}, (predecode_insts_shifted[66] ? {predecode_insts_shifted[83:76], predecode_insts_shifted[84], predecode_insts_shifted[94:85]} : {{8 {predecode_insts_shifted[95]}}, predecode_insts_shifted[71], predecode_insts_shifted[94:89], predecode_insts_shifted[75:72]}), 1'h0} : 32'h00000000)) | (predecode_firstJumpOH_enc[3] ? predecode_addrs_3 + {{12 {predecode_insts_shifted[127]}}, (predecode_insts_shifted[98] ? {predecode_insts_shifted[115:108], predecode_insts_shifted[116], predecode_insts_shifted[126:117]} : {{8 {predecode_insts_shifted[127]}}, predecode_insts_shifted[103], predecode_insts_shifted[126:121], predecode_insts_shifted[107:104]}), 1'h0} : 32'h00000000)) | (predecode_firstJumpOH_enc == 4'h0 ? {io_fetchData_bits_addr[31:4] + 28'h0000001, 4'h0} : 32'h00000000); + end + else + pc_bits <= {io_csr_value_0[31:2], 2'h0}; + end + assign io_fetchFault_valid = fetchFaultValid; + assign io_fetchFault_bits = io_fetchData_bits_addr; + assign io_fetchAddr_valid = ~blockNewFetch; + assign io_fetchAddr_bits = (blockNewFetch ? 32'h00000000 : pc_bits); + assign io_bufferRequest_nValid = nValid[2:0]; + assign io_bufferRequest_bits_0_addr = io_fetchData_bits_addr; + assign io_bufferRequest_bits_0_inst = predecode_insts_shifted[31:0]; + assign io_bufferRequest_bits_0_brchFwd = predecode_jumped_0; + assign io_bufferRequest_bits_1_addr = predecode_addrs_1; + assign io_bufferRequest_bits_1_inst = predecode_insts_shifted[63:32]; + assign io_bufferRequest_bits_1_brchFwd = predecode_jumped_1; + assign io_bufferRequest_bits_2_addr = predecode_addrs_2; + assign io_bufferRequest_bits_2_inst = predecode_insts_shifted[95:64]; + assign io_bufferRequest_bits_2_brchFwd = predecode_jumped_2; + assign io_bufferRequest_bits_3_addr = predecode_addrs_3; + assign io_bufferRequest_bits_3_inst = predecode_insts_shifted[127:96]; + assign io_bufferRequest_bits_3_brchFwd = predecode_jumped_3; +endmodule +module Fetcher ( + clock, + reset, + io_ctrl_valid, + io_ctrl_bits, + io_fetch_valid, + io_fetch_bits_addr, + io_fetch_bits_inst_0, + io_fetch_bits_inst_1, + io_fetch_bits_inst_2, + io_fetch_bits_inst_3, + io_fetch_bits_fault, + io_ibus_valid, + io_ibus_ready, + io_ibus_addr, + io_ibus_rdata, + io_ibus_fault_valid +); + input clock; + input reset; + input io_ctrl_valid; + input [31:0] io_ctrl_bits; + output wire io_fetch_valid; + output wire [31:0] io_fetch_bits_addr; + output wire [31:0] io_fetch_bits_inst_0; + output wire [31:0] io_fetch_bits_inst_1; + output wire [31:0] io_fetch_bits_inst_2; + output wire [31:0] io_fetch_bits_inst_3; + output wire io_fetch_bits_fault; + output wire io_ibus_valid; + input io_ibus_ready; + output wire [31:0] io_ibus_addr; + input [127:0] io_ibus_rdata; + input io_ibus_fault_valid; + reg ibusCmd_valid; + reg [31:0] ibusCmd_bits; + reg fault; + wire ibusFired = io_ctrl_valid & io_ibus_ready; + always @(posedge clock or posedge reset) + if (reset) begin + ibusCmd_valid <= 1'h0; + ibusCmd_bits <= 32'h00000000; + fault <= 1'h0; + end + else begin + ibusCmd_valid <= ibusFired; + ibusCmd_bits <= (ibusFired ? io_ctrl_bits : 32'h00000000); + fault <= io_ibus_fault_valid; + end + assign io_fetch_valid = ibusCmd_valid; + assign io_fetch_bits_addr = ibusCmd_bits; + assign io_fetch_bits_inst_0 = io_ibus_rdata[31:0]; + assign io_fetch_bits_inst_1 = io_ibus_rdata[63:32]; + assign io_fetch_bits_inst_2 = io_ibus_rdata[95:64]; + assign io_fetch_bits_inst_3 = io_ibus_rdata[127:96]; + assign io_fetch_bits_fault = fault; + assign io_ibus_valid = io_ctrl_valid; + assign io_ibus_addr = {io_ctrl_bits[31:4], 4'h0}; +endmodule +module CircularBufferMulti ( + clock, + reset, + io_enqValid, + io_enqData_0_addr, + io_enqData_0_inst, + io_enqData_0_brchFwd, + io_enqData_1_addr, + io_enqData_1_inst, + io_enqData_1_brchFwd, + io_enqData_2_addr, + io_enqData_2_inst, + io_enqData_2_brchFwd, + io_enqData_3_addr, + io_enqData_3_inst, + io_enqData_3_brchFwd, + io_nEnqueued, + io_nSpace, + io_dataOut_0_addr, + io_dataOut_0_inst, + io_dataOut_0_brchFwd, + io_dataOut_1_addr, + io_dataOut_1_inst, + io_dataOut_1_brchFwd, + io_dataOut_2_addr, + io_dataOut_2_inst, + io_dataOut_2_brchFwd, + io_dataOut_3_addr, + io_dataOut_3_inst, + io_dataOut_3_brchFwd, + io_deqReady, + io_flush +); + input clock; + input reset; + input [2:0] io_enqValid; + input [31:0] io_enqData_0_addr; + input [31:0] io_enqData_0_inst; + input io_enqData_0_brchFwd; + input [31:0] io_enqData_1_addr; + input [31:0] io_enqData_1_inst; + input io_enqData_1_brchFwd; + input [31:0] io_enqData_2_addr; + input [31:0] io_enqData_2_inst; + input io_enqData_2_brchFwd; + input [31:0] io_enqData_3_addr; + input [31:0] io_enqData_3_inst; + input io_enqData_3_brchFwd; + output wire [3:0] io_nEnqueued; + output wire [3:0] io_nSpace; + output wire [31:0] io_dataOut_0_addr; + output wire [31:0] io_dataOut_0_inst; + output wire io_dataOut_0_brchFwd; + output wire [31:0] io_dataOut_1_addr; + output wire [31:0] io_dataOut_1_inst; + output wire io_dataOut_1_brchFwd; + output wire [31:0] io_dataOut_2_addr; + output wire [31:0] io_dataOut_2_inst; + output wire io_dataOut_2_brchFwd; + output wire [31:0] io_dataOut_3_addr; + output wire [31:0] io_dataOut_3_inst; + output wire io_dataOut_3_brchFwd; + input [2:0] io_deqReady; + input io_flush; + reg [31:0] buffer_0_addr; + reg [31:0] buffer_0_inst; + reg buffer_0_brchFwd; + reg [31:0] buffer_1_addr; + reg [31:0] buffer_1_inst; + reg buffer_1_brchFwd; + reg [31:0] buffer_2_addr; + reg [31:0] buffer_2_inst; + reg buffer_2_brchFwd; + reg [31:0] buffer_3_addr; + reg [31:0] buffer_3_inst; + reg buffer_3_brchFwd; + reg [31:0] buffer_4_addr; + reg [31:0] buffer_4_inst; + reg buffer_4_brchFwd; + reg [31:0] buffer_5_addr; + reg [31:0] buffer_5_inst; + reg buffer_5_brchFwd; + reg [31:0] buffer_6_addr; + reg [31:0] buffer_6_inst; + reg buffer_6_brchFwd; + reg [31:0] buffer_7_addr; + reg [31:0] buffer_7_inst; + reg buffer_7_brchFwd; + reg [2:0] enqPtr; + reg [2:0] deqPtr; + reg [3:0] nEnqueued; + wire [9:0] _outputBufferView_rotated_T_9 = {7'h00, deqPtr} * 10'h041; + wire [519:0] _outputBufferView_rotated_T_23 = (_outputBufferView_rotated_T_9[0] ? {buffer_0_brchFwd, buffer_7_addr, buffer_7_inst, buffer_7_brchFwd, buffer_6_addr, buffer_6_inst, buffer_6_brchFwd, buffer_5_addr, buffer_5_inst, buffer_5_brchFwd, buffer_4_addr, buffer_4_inst, buffer_4_brchFwd, buffer_3_addr, buffer_3_inst, buffer_3_brchFwd, buffer_2_addr, buffer_2_inst, buffer_2_brchFwd, buffer_1_addr, buffer_1_inst, buffer_1_brchFwd, buffer_0_addr, buffer_0_inst} : {buffer_7_addr, buffer_7_inst, buffer_7_brchFwd, buffer_6_addr, buffer_6_inst, buffer_6_brchFwd, buffer_5_addr, buffer_5_inst, buffer_5_brchFwd, buffer_4_addr, buffer_4_inst, buffer_4_brchFwd, buffer_3_addr, buffer_3_inst, buffer_3_brchFwd, buffer_2_addr, buffer_2_inst, buffer_2_brchFwd, buffer_1_addr, buffer_1_inst, buffer_1_brchFwd, buffer_0_addr, buffer_0_inst, buffer_0_brchFwd}); + wire [519:0] _outputBufferView_rotated_T_27 = (_outputBufferView_rotated_T_9[1] ? {_outputBufferView_rotated_T_23[1:0], _outputBufferView_rotated_T_23[519:2]} : _outputBufferView_rotated_T_23); + wire [519:0] _outputBufferView_rotated_T_31 = (_outputBufferView_rotated_T_9[2] ? {_outputBufferView_rotated_T_27[3:0], _outputBufferView_rotated_T_27[519:4]} : _outputBufferView_rotated_T_27); + wire [519:0] _outputBufferView_rotated_T_35 = (_outputBufferView_rotated_T_9[3] ? {_outputBufferView_rotated_T_31[7:0], _outputBufferView_rotated_T_31[519:8]} : _outputBufferView_rotated_T_31); + wire [519:0] _outputBufferView_rotated_T_39 = (_outputBufferView_rotated_T_9[4] ? {_outputBufferView_rotated_T_35[15:0], _outputBufferView_rotated_T_35[519:16]} : _outputBufferView_rotated_T_35); + wire [519:0] _outputBufferView_rotated_T_43 = (_outputBufferView_rotated_T_9[5] ? {_outputBufferView_rotated_T_39[31:0], _outputBufferView_rotated_T_39[519:32]} : _outputBufferView_rotated_T_39); + wire [519:0] _outputBufferView_rotated_T_47 = (_outputBufferView_rotated_T_9[6] ? {_outputBufferView_rotated_T_43[63:0], _outputBufferView_rotated_T_43[519:64]} : _outputBufferView_rotated_T_43); + wire [519:0] _outputBufferView_rotated_T_51 = (_outputBufferView_rotated_T_9[7] ? {_outputBufferView_rotated_T_47[127:0], _outputBufferView_rotated_T_47[519:128]} : _outputBufferView_rotated_T_47); + wire [519:0] _outputBufferView_rotated_T_55 = (_outputBufferView_rotated_T_9[8] ? {_outputBufferView_rotated_T_51[255:0], _outputBufferView_rotated_T_51[519:256]} : _outputBufferView_rotated_T_51); + wire [259:0] outputBufferView_rotated = (_outputBufferView_rotated_T_9[9] ? {_outputBufferView_rotated_T_55[251:0], _outputBufferView_rotated_T_55[519:512]} : _outputBufferView_rotated_T_55[259:0]); + wire expandedInput_2_ret_valid = io_enqValid > 3'h2; + wire [9:0] _rotatedInput_rotated_T_17 = {7'h00, enqPtr} * 10'h042; + wire [527:0] _rotatedInput_rotated_T_31 = (_rotatedInput_rotated_T_17[0] ? {263'h0, io_enqValid[2], io_enqData_3_addr, io_enqData_3_inst, io_enqData_3_brchFwd, expandedInput_2_ret_valid, io_enqData_2_addr, io_enqData_2_inst, io_enqData_2_brchFwd, |io_enqValid[2:1], io_enqData_1_addr, io_enqData_1_inst, io_enqData_1_brchFwd, |io_enqValid, io_enqData_0_addr, io_enqData_0_inst, io_enqData_0_brchFwd, 1'h0} : {264'h0, io_enqValid[2], io_enqData_3_addr, io_enqData_3_inst, io_enqData_3_brchFwd, expandedInput_2_ret_valid, io_enqData_2_addr, io_enqData_2_inst, io_enqData_2_brchFwd, |io_enqValid[2:1], io_enqData_1_addr, io_enqData_1_inst, io_enqData_1_brchFwd, |io_enqValid, io_enqData_0_addr, io_enqData_0_inst, io_enqData_0_brchFwd}); + wire [527:0] _rotatedInput_rotated_T_35 = (_rotatedInput_rotated_T_17[1] ? {_rotatedInput_rotated_T_31[525:0], _rotatedInput_rotated_T_31[527:526]} : _rotatedInput_rotated_T_31); + wire [527:0] _rotatedInput_rotated_T_39 = (_rotatedInput_rotated_T_17[2] ? {_rotatedInput_rotated_T_35[523:0], _rotatedInput_rotated_T_35[527:524]} : _rotatedInput_rotated_T_35); + wire [527:0] _rotatedInput_rotated_T_43 = (_rotatedInput_rotated_T_17[3] ? {_rotatedInput_rotated_T_39[519:0], _rotatedInput_rotated_T_39[527:520]} : _rotatedInput_rotated_T_39); + wire [527:0] _rotatedInput_rotated_T_47 = (_rotatedInput_rotated_T_17[4] ? {_rotatedInput_rotated_T_43[511:0], _rotatedInput_rotated_T_43[527:512]} : _rotatedInput_rotated_T_43); + wire [527:0] _rotatedInput_rotated_T_51 = (_rotatedInput_rotated_T_17[5] ? {_rotatedInput_rotated_T_47[495:0], _rotatedInput_rotated_T_47[527:496]} : _rotatedInput_rotated_T_47); + wire [527:0] _rotatedInput_rotated_T_55 = (_rotatedInput_rotated_T_17[6] ? {_rotatedInput_rotated_T_51[463:0], _rotatedInput_rotated_T_51[527:464]} : _rotatedInput_rotated_T_51); + wire [527:0] _rotatedInput_rotated_T_59 = (_rotatedInput_rotated_T_17[7] ? {_rotatedInput_rotated_T_55[399:0], _rotatedInput_rotated_T_55[527:400]} : _rotatedInput_rotated_T_55); + wire [527:0] _rotatedInput_rotated_T_63 = (_rotatedInput_rotated_T_17[8] ? {_rotatedInput_rotated_T_59[271:0], _rotatedInput_rotated_T_59[527:272]} : _rotatedInput_rotated_T_59); + wire [527:0] rotatedInput_rotated = (_rotatedInput_rotated_T_17[9] ? {_rotatedInput_rotated_T_63[15:0], _rotatedInput_rotated_T_63[527:16]} : _rotatedInput_rotated_T_63); + always @(posedge clock or posedge reset) + if (reset) begin + buffer_0_addr <= 32'h00000000; + buffer_0_inst <= 32'h00000000; + buffer_0_brchFwd <= 1'h0; + buffer_1_addr <= 32'h00000000; + buffer_1_inst <= 32'h00000000; + buffer_1_brchFwd <= 1'h0; + buffer_2_addr <= 32'h00000000; + buffer_2_inst <= 32'h00000000; + buffer_2_brchFwd <= 1'h0; + buffer_3_addr <= 32'h00000000; + buffer_3_inst <= 32'h00000000; + buffer_3_brchFwd <= 1'h0; + buffer_4_addr <= 32'h00000000; + buffer_4_inst <= 32'h00000000; + buffer_4_brchFwd <= 1'h0; + buffer_5_addr <= 32'h00000000; + buffer_5_inst <= 32'h00000000; + buffer_5_brchFwd <= 1'h0; + buffer_6_addr <= 32'h00000000; + buffer_6_inst <= 32'h00000000; + buffer_6_brchFwd <= 1'h0; + buffer_7_addr <= 32'h00000000; + buffer_7_inst <= 32'h00000000; + buffer_7_brchFwd <= 1'h0; + enqPtr <= 3'h0; + deqPtr <= 3'h0; + nEnqueued <= 4'h0; + end + else begin + if (rotatedInput_rotated[65]) begin + buffer_0_addr <= rotatedInput_rotated[64:33]; + buffer_0_inst <= rotatedInput_rotated[32:1]; + buffer_0_brchFwd <= rotatedInput_rotated[0]; + end + if (rotatedInput_rotated[131]) begin + buffer_1_addr <= rotatedInput_rotated[130:99]; + buffer_1_inst <= rotatedInput_rotated[98:67]; + buffer_1_brchFwd <= rotatedInput_rotated[66]; + end + if (rotatedInput_rotated[197]) begin + buffer_2_addr <= rotatedInput_rotated[196:165]; + buffer_2_inst <= rotatedInput_rotated[164:133]; + buffer_2_brchFwd <= rotatedInput_rotated[132]; + end + if (rotatedInput_rotated[263]) begin + buffer_3_addr <= rotatedInput_rotated[262:231]; + buffer_3_inst <= rotatedInput_rotated[230:199]; + buffer_3_brchFwd <= rotatedInput_rotated[198]; + end + if (rotatedInput_rotated[329]) begin + buffer_4_addr <= rotatedInput_rotated[328:297]; + buffer_4_inst <= rotatedInput_rotated[296:265]; + buffer_4_brchFwd <= rotatedInput_rotated[264]; + end + if (rotatedInput_rotated[395]) begin + buffer_5_addr <= rotatedInput_rotated[394:363]; + buffer_5_inst <= rotatedInput_rotated[362:331]; + buffer_5_brchFwd <= rotatedInput_rotated[330]; + end + if (rotatedInput_rotated[461]) begin + buffer_6_addr <= rotatedInput_rotated[460:429]; + buffer_6_inst <= rotatedInput_rotated[428:397]; + buffer_6_brchFwd <= rotatedInput_rotated[396]; + end + if (rotatedInput_rotated[527]) begin + buffer_7_addr <= rotatedInput_rotated[526:495]; + buffer_7_inst <= rotatedInput_rotated[494:463]; + buffer_7_brchFwd <= rotatedInput_rotated[462]; + end + enqPtr <= (io_flush ? 3'h0 : enqPtr + io_enqValid); + deqPtr <= (io_flush ? 3'h0 : deqPtr + io_deqReady); + nEnqueued <= (io_flush ? 4'h0 : (nEnqueued + {1'h0, io_enqValid}) - {1'h0, io_deqReady}); + end + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 4'h8 - nEnqueued; + assign io_dataOut_0_addr = outputBufferView_rotated[64:33]; + assign io_dataOut_0_inst = outputBufferView_rotated[32:1]; + assign io_dataOut_0_brchFwd = outputBufferView_rotated[0]; + assign io_dataOut_1_addr = outputBufferView_rotated[129:98]; + assign io_dataOut_1_inst = outputBufferView_rotated[97:66]; + assign io_dataOut_1_brchFwd = outputBufferView_rotated[65]; + assign io_dataOut_2_addr = outputBufferView_rotated[194:163]; + assign io_dataOut_2_inst = outputBufferView_rotated[162:131]; + assign io_dataOut_2_brchFwd = outputBufferView_rotated[130]; + assign io_dataOut_3_addr = outputBufferView_rotated[259:228]; + assign io_dataOut_3_inst = outputBufferView_rotated[227:196]; + assign io_dataOut_3_brchFwd = outputBufferView_rotated[195]; +endmodule +module InstructionBuffer ( + clock, + reset, + io_feedIn_nReady, + io_feedIn_nValid, + io_feedIn_bits_0_addr, + io_feedIn_bits_0_inst, + io_feedIn_bits_0_brchFwd, + io_feedIn_bits_1_addr, + io_feedIn_bits_1_inst, + io_feedIn_bits_1_brchFwd, + io_feedIn_bits_2_addr, + io_feedIn_bits_2_inst, + io_feedIn_bits_2_brchFwd, + io_feedIn_bits_3_addr, + io_feedIn_bits_3_inst, + io_feedIn_bits_3_brchFwd, + io_out_0_ready, + io_out_0_valid, + io_out_0_bits_addr, + io_out_0_bits_inst, + io_out_0_bits_brchFwd, + io_out_1_ready, + io_out_1_valid, + io_out_1_bits_addr, + io_out_1_bits_inst, + io_out_1_bits_brchFwd, + io_out_2_ready, + io_out_2_valid, + io_out_2_bits_addr, + io_out_2_bits_inst, + io_out_2_bits_brchFwd, + io_out_3_ready, + io_out_3_valid, + io_out_3_bits_addr, + io_out_3_bits_inst, + io_out_3_bits_brchFwd, + io_flush, + io_nEnqueued, + io_nSpace +); + input clock; + input reset; + output wire [2:0] io_feedIn_nReady; + input [2:0] io_feedIn_nValid; + input [31:0] io_feedIn_bits_0_addr; + input [31:0] io_feedIn_bits_0_inst; + input io_feedIn_bits_0_brchFwd; + input [31:0] io_feedIn_bits_1_addr; + input [31:0] io_feedIn_bits_1_inst; + input io_feedIn_bits_1_brchFwd; + input [31:0] io_feedIn_bits_2_addr; + input [31:0] io_feedIn_bits_2_inst; + input io_feedIn_bits_2_brchFwd; + input [31:0] io_feedIn_bits_3_addr; + input [31:0] io_feedIn_bits_3_inst; + input io_feedIn_bits_3_brchFwd; + input io_out_0_ready; + output wire io_out_0_valid; + output wire [31:0] io_out_0_bits_addr; + output wire [31:0] io_out_0_bits_inst; + output wire io_out_0_bits_brchFwd; + input io_out_1_ready; + output wire io_out_1_valid; + output wire [31:0] io_out_1_bits_addr; + output wire [31:0] io_out_1_bits_inst; + output wire io_out_1_bits_brchFwd; + input io_out_2_ready; + output wire io_out_2_valid; + output wire [31:0] io_out_2_bits_addr; + output wire [31:0] io_out_2_bits_inst; + output wire io_out_2_bits_brchFwd; + input io_out_3_ready; + output wire io_out_3_valid; + output wire [31:0] io_out_3_bits_addr; + output wire [31:0] io_out_3_bits_inst; + output wire io_out_3_bits_brchFwd; + input io_flush; + output wire [3:0] io_nEnqueued; + output wire [3:0] io_nSpace; + wire [3:0] _circularBuffer_io_nEnqueued; + wire [3:0] _circularBuffer_io_nSpace; + wire io_out_0_valid_0 = |_circularBuffer_io_nEnqueued & ~io_flush; + wire io_out_1_valid_0 = |_circularBuffer_io_nEnqueued[3:1] & ~io_flush; + wire io_out_2_valid_0 = (_circularBuffer_io_nEnqueued > 4'h2) & ~io_flush; + wire io_out_3_valid_0 = |_circularBuffer_io_nEnqueued[3:2] & ~io_flush; + wire _nReady_T = io_out_0_ready & io_out_0_valid_0; + wire _nReady_T_1 = io_out_1_ready & io_out_1_valid_0; + wire _nReady_T_2 = io_out_2_ready & io_out_2_valid_0; + wire _nReady_T_3 = io_out_3_ready & io_out_3_valid_0; + CircularBufferMulti circularBuffer( + .clock(clock), + .reset(reset), + .io_enqValid(io_feedIn_nValid), + .io_enqData_0_addr(io_feedIn_bits_0_addr), + .io_enqData_0_inst(io_feedIn_bits_0_inst), + .io_enqData_0_brchFwd(io_feedIn_bits_0_brchFwd), + .io_enqData_1_addr(io_feedIn_bits_1_addr), + .io_enqData_1_inst(io_feedIn_bits_1_inst), + .io_enqData_1_brchFwd(io_feedIn_bits_1_brchFwd), + .io_enqData_2_addr(io_feedIn_bits_2_addr), + .io_enqData_2_inst(io_feedIn_bits_2_inst), + .io_enqData_2_brchFwd(io_feedIn_bits_2_brchFwd), + .io_enqData_3_addr(io_feedIn_bits_3_addr), + .io_enqData_3_inst(io_feedIn_bits_3_inst), + .io_enqData_3_brchFwd(io_feedIn_bits_3_brchFwd), + .io_nEnqueued(_circularBuffer_io_nEnqueued), + .io_nSpace(_circularBuffer_io_nSpace), + .io_dataOut_0_addr(io_out_0_bits_addr), + .io_dataOut_0_inst(io_out_0_bits_inst), + .io_dataOut_0_brchFwd(io_out_0_bits_brchFwd), + .io_dataOut_1_addr(io_out_1_bits_addr), + .io_dataOut_1_inst(io_out_1_bits_inst), + .io_dataOut_1_brchFwd(io_out_1_bits_brchFwd), + .io_dataOut_2_addr(io_out_2_bits_addr), + .io_dataOut_2_inst(io_out_2_bits_inst), + .io_dataOut_2_brchFwd(io_out_2_bits_brchFwd), + .io_dataOut_3_addr(io_out_3_bits_addr), + .io_dataOut_3_inst(io_out_3_bits_inst), + .io_dataOut_3_brchFwd(io_out_3_bits_brchFwd), + .io_deqReady({1'h0, {1'h0, _nReady_T} + {1'h0, _nReady_T_1}} + {1'h0, {1'h0, _nReady_T_2} + {1'h0, _nReady_T_3}}), + .io_flush(io_flush) + ); + assign io_feedIn_nReady = (_circularBuffer_io_nSpace < 4'h4 ? _circularBuffer_io_nSpace[2:0] : 3'h4); + assign io_out_0_valid = io_out_0_valid_0; + assign io_out_1_valid = io_out_1_valid_0; + assign io_out_2_valid = io_out_2_valid_0; + assign io_out_3_valid = io_out_3_valid_0; + assign io_nEnqueued = _circularBuffer_io_nEnqueued; + assign io_nSpace = _circularBuffer_io_nSpace; +endmodule +module UncachedFetch ( + clock, + reset, + io_csr_value_0, + io_ibus_valid, + io_ibus_ready, + io_ibus_addr, + io_ibus_rdata, + io_ibus_fault_valid, + io_inst_lanes_0_ready, + io_inst_lanes_0_valid, + io_inst_lanes_0_bits_addr, + io_inst_lanes_0_bits_inst, + io_inst_lanes_0_bits_brchFwd, + io_inst_lanes_1_ready, + io_inst_lanes_1_valid, + io_inst_lanes_1_bits_addr, + io_inst_lanes_1_bits_inst, + io_inst_lanes_1_bits_brchFwd, + io_inst_lanes_2_ready, + io_inst_lanes_2_valid, + io_inst_lanes_2_bits_addr, + io_inst_lanes_2_bits_inst, + io_inst_lanes_2_bits_brchFwd, + io_inst_lanes_3_ready, + io_inst_lanes_3_valid, + io_inst_lanes_3_bits_addr, + io_inst_lanes_3_bits_inst, + io_inst_lanes_3_bits_brchFwd, + io_branch_0_valid, + io_branch_0_value, + io_branch_1_valid, + io_branch_1_value, + io_branch_2_valid, + io_branch_2_value, + io_branch_3_valid, + io_branch_3_value, + io_iflush_valid, + io_iflush_pcNext, + io_pc, + io_fault_valid, + io_fault_bits +); + input clock; + input reset; + input [31:0] io_csr_value_0; + output wire io_ibus_valid; + input io_ibus_ready; + output wire [31:0] io_ibus_addr; + input [127:0] io_ibus_rdata; + input io_ibus_fault_valid; + input io_inst_lanes_0_ready; + output wire io_inst_lanes_0_valid; + output wire [31:0] io_inst_lanes_0_bits_addr; + output wire [31:0] io_inst_lanes_0_bits_inst; + output wire io_inst_lanes_0_bits_brchFwd; + input io_inst_lanes_1_ready; + output wire io_inst_lanes_1_valid; + output wire [31:0] io_inst_lanes_1_bits_addr; + output wire [31:0] io_inst_lanes_1_bits_inst; + output wire io_inst_lanes_1_bits_brchFwd; + input io_inst_lanes_2_ready; + output wire io_inst_lanes_2_valid; + output wire [31:0] io_inst_lanes_2_bits_addr; + output wire [31:0] io_inst_lanes_2_bits_inst; + output wire io_inst_lanes_2_bits_brchFwd; + input io_inst_lanes_3_ready; + output wire io_inst_lanes_3_valid; + output wire [31:0] io_inst_lanes_3_bits_addr; + output wire [31:0] io_inst_lanes_3_bits_inst; + output wire io_inst_lanes_3_bits_brchFwd; + input io_branch_0_valid; + input [31:0] io_branch_0_value; + input io_branch_1_valid; + input [31:0] io_branch_1_value; + input io_branch_2_valid; + input [31:0] io_branch_2_value; + input io_branch_3_valid; + input [31:0] io_branch_3_value; + input io_iflush_valid; + input [31:0] io_iflush_pcNext; + output wire [31:0] io_pc; + output wire io_fault_valid; + output wire [31:0] io_fault_bits; + wire _instructionBuffer_io_out_0_valid; + wire [31:0] _instructionBuffer_io_out_0_bits_addr; + wire [3:0] _instructionBuffer_io_nSpace; + wire _fetcher_io_fetch_valid; + wire [31:0] _fetcher_io_fetch_bits_addr; + wire [31:0] _fetcher_io_fetch_bits_inst_0; + wire [31:0] _fetcher_io_fetch_bits_inst_1; + wire [31:0] _fetcher_io_fetch_bits_inst_2; + wire [31:0] _fetcher_io_fetch_bits_inst_3; + wire _fetcher_io_fetch_bits_fault; + wire _ctrl_io_fetchAddr_valid; + wire [31:0] _ctrl_io_fetchAddr_bits; + wire [2:0] _ctrl_io_bufferRequest_nValid; + wire [31:0] _ctrl_io_bufferRequest_bits_0_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_0_inst; + wire _ctrl_io_bufferRequest_bits_0_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_1_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_1_inst; + wire _ctrl_io_bufferRequest_bits_1_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_2_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_2_inst; + wire _ctrl_io_bufferRequest_bits_2_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_3_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_3_inst; + wire _ctrl_io_bufferRequest_bits_3_brchFwd; + wire branch_valid = ((io_branch_0_valid | io_branch_1_valid) | io_branch_2_valid) | io_branch_3_valid; + reg [31:0] pc; + always @(posedge clock or posedge reset) + if (reset) + pc <= 32'h00000000; + else if (_instructionBuffer_io_out_0_valid) + pc <= _instructionBuffer_io_out_0_bits_addr; + FetchControl ctrl( + .clock(clock), + .reset(reset), + .io_fetchFault_valid(io_fault_valid), + .io_fetchFault_bits(io_fault_bits), + .io_csr_value_0(io_csr_value_0), + .io_iflush_valid(io_iflush_valid), + .io_iflush_bits((io_iflush_valid ? io_iflush_pcNext : 32'h00000000)), + .io_branch_valid(branch_valid), + .io_branch_bits((io_branch_0_valid ? io_branch_0_value : (io_branch_1_valid ? io_branch_1_value : (io_branch_2_valid ? io_branch_2_value : (io_branch_3_valid ? io_branch_3_value : 32'h00000000))))), + .io_fetchData_valid(_fetcher_io_fetch_valid), + .io_fetchData_bits_addr(_fetcher_io_fetch_bits_addr), + .io_fetchData_bits_inst_0(_fetcher_io_fetch_bits_inst_0), + .io_fetchData_bits_inst_1(_fetcher_io_fetch_bits_inst_1), + .io_fetchData_bits_inst_2(_fetcher_io_fetch_bits_inst_2), + .io_fetchData_bits_inst_3(_fetcher_io_fetch_bits_inst_3), + .io_fetchData_bits_fault(_fetcher_io_fetch_bits_fault), + .io_fetchAddr_valid(_ctrl_io_fetchAddr_valid), + .io_fetchAddr_bits(_ctrl_io_fetchAddr_bits), + .io_bufferRequest_nValid(_ctrl_io_bufferRequest_nValid), + .io_bufferRequest_bits_0_addr(_ctrl_io_bufferRequest_bits_0_addr), + .io_bufferRequest_bits_0_inst(_ctrl_io_bufferRequest_bits_0_inst), + .io_bufferRequest_bits_0_brchFwd(_ctrl_io_bufferRequest_bits_0_brchFwd), + .io_bufferRequest_bits_1_addr(_ctrl_io_bufferRequest_bits_1_addr), + .io_bufferRequest_bits_1_inst(_ctrl_io_bufferRequest_bits_1_inst), + .io_bufferRequest_bits_1_brchFwd(_ctrl_io_bufferRequest_bits_1_brchFwd), + .io_bufferRequest_bits_2_addr(_ctrl_io_bufferRequest_bits_2_addr), + .io_bufferRequest_bits_2_inst(_ctrl_io_bufferRequest_bits_2_inst), + .io_bufferRequest_bits_2_brchFwd(_ctrl_io_bufferRequest_bits_2_brchFwd), + .io_bufferRequest_bits_3_addr(_ctrl_io_bufferRequest_bits_3_addr), + .io_bufferRequest_bits_3_inst(_ctrl_io_bufferRequest_bits_3_inst), + .io_bufferRequest_bits_3_brchFwd(_ctrl_io_bufferRequest_bits_3_brchFwd), + .io_bufferSpaces(_instructionBuffer_io_nSpace) + ); + Fetcher fetcher( + .clock(clock), + .reset(reset), + .io_ctrl_valid(_ctrl_io_fetchAddr_valid), + .io_ctrl_bits(_ctrl_io_fetchAddr_bits), + .io_fetch_valid(_fetcher_io_fetch_valid), + .io_fetch_bits_addr(_fetcher_io_fetch_bits_addr), + .io_fetch_bits_inst_0(_fetcher_io_fetch_bits_inst_0), + .io_fetch_bits_inst_1(_fetcher_io_fetch_bits_inst_1), + .io_fetch_bits_inst_2(_fetcher_io_fetch_bits_inst_2), + .io_fetch_bits_inst_3(_fetcher_io_fetch_bits_inst_3), + .io_fetch_bits_fault(_fetcher_io_fetch_bits_fault), + .io_ibus_valid(io_ibus_valid), + .io_ibus_ready(io_ibus_ready), + .io_ibus_addr(io_ibus_addr), + .io_ibus_rdata(io_ibus_rdata), + .io_ibus_fault_valid(io_ibus_fault_valid) + ); + InstructionBuffer instructionBuffer( + .clock(clock), + .reset(reset), + .io_feedIn_nReady(), + .io_feedIn_nValid(_ctrl_io_bufferRequest_nValid), + .io_feedIn_bits_0_addr(_ctrl_io_bufferRequest_bits_0_addr), + .io_feedIn_bits_0_inst(_ctrl_io_bufferRequest_bits_0_inst), + .io_feedIn_bits_0_brchFwd(_ctrl_io_bufferRequest_bits_0_brchFwd), + .io_feedIn_bits_1_addr(_ctrl_io_bufferRequest_bits_1_addr), + .io_feedIn_bits_1_inst(_ctrl_io_bufferRequest_bits_1_inst), + .io_feedIn_bits_1_brchFwd(_ctrl_io_bufferRequest_bits_1_brchFwd), + .io_feedIn_bits_2_addr(_ctrl_io_bufferRequest_bits_2_addr), + .io_feedIn_bits_2_inst(_ctrl_io_bufferRequest_bits_2_inst), + .io_feedIn_bits_2_brchFwd(_ctrl_io_bufferRequest_bits_2_brchFwd), + .io_feedIn_bits_3_addr(_ctrl_io_bufferRequest_bits_3_addr), + .io_feedIn_bits_3_inst(_ctrl_io_bufferRequest_bits_3_inst), + .io_feedIn_bits_3_brchFwd(_ctrl_io_bufferRequest_bits_3_brchFwd), + .io_out_0_ready(io_inst_lanes_0_ready), + .io_out_0_valid(_instructionBuffer_io_out_0_valid), + .io_out_0_bits_addr(_instructionBuffer_io_out_0_bits_addr), + .io_out_0_bits_inst(io_inst_lanes_0_bits_inst), + .io_out_0_bits_brchFwd(io_inst_lanes_0_bits_brchFwd), + .io_out_1_ready(io_inst_lanes_1_ready), + .io_out_1_valid(io_inst_lanes_1_valid), + .io_out_1_bits_addr(io_inst_lanes_1_bits_addr), + .io_out_1_bits_inst(io_inst_lanes_1_bits_inst), + .io_out_1_bits_brchFwd(io_inst_lanes_1_bits_brchFwd), + .io_out_2_ready(io_inst_lanes_2_ready), + .io_out_2_valid(io_inst_lanes_2_valid), + .io_out_2_bits_addr(io_inst_lanes_2_bits_addr), + .io_out_2_bits_inst(io_inst_lanes_2_bits_inst), + .io_out_2_bits_brchFwd(io_inst_lanes_2_bits_brchFwd), + .io_out_3_ready(io_inst_lanes_3_ready), + .io_out_3_valid(io_inst_lanes_3_valid), + .io_out_3_bits_addr(io_inst_lanes_3_bits_addr), + .io_out_3_bits_inst(io_inst_lanes_3_bits_inst), + .io_out_3_bits_brchFwd(io_inst_lanes_3_bits_brchFwd), + .io_flush(io_iflush_valid | branch_valid), + .io_nEnqueued(), + .io_nSpace(_instructionBuffer_io_nSpace) + ); + assign io_inst_lanes_0_valid = _instructionBuffer_io_out_0_valid; + assign io_inst_lanes_0_bits_addr = _instructionBuffer_io_out_0_bits_addr; + assign io_pc = pc; +endmodule +module Csr ( + clock, + reset, + io_csr_in_value_12, + io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + io_csr_out_value_8, + io_req_valid, + io_req_bits_addr, + io_req_bits_index, + io_req_bits_rs1, + io_req_bits_op, + io_rs1_valid, + io_rs1_data, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data, + io_bru_in_mode_valid, + io_bru_in_mode_bits, + io_bru_in_mcause_valid, + io_bru_in_mcause_bits, + io_bru_in_mepc_valid, + io_bru_in_mepc_bits, + io_bru_in_mtval_valid, + io_bru_in_mtval_bits, + io_bru_in_halt, + io_bru_in_fault, + io_bru_in_wfi, + io_bru_out_mode, + io_bru_out_mepc, + io_bru_out_mtvec, + io_float_in_fflags_valid, + io_float_in_fflags_bits, + io_float_out_frm, + io_counters_nRetired, + io_halted, + io_fault, + io_wfi, + io_irq +); + input clock; + input reset; + input [31:0] io_csr_in_value_12; + output wire [31:0] io_csr_out_value_0; + output wire [31:0] io_csr_out_value_1; + output wire [31:0] io_csr_out_value_2; + output wire [31:0] io_csr_out_value_3; + output wire [31:0] io_csr_out_value_4; + output wire [31:0] io_csr_out_value_5; + output wire [31:0] io_csr_out_value_6; + output wire [31:0] io_csr_out_value_7; + output wire [31:0] io_csr_out_value_8; + input io_req_valid; + input [4:0] io_req_bits_addr; + input [11:0] io_req_bits_index; + input [4:0] io_req_bits_rs1; + input [1:0] io_req_bits_op; + input io_rs1_valid; + input [31:0] io_rs1_data; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + input io_bru_in_mode_valid; + input [1:0] io_bru_in_mode_bits; + input io_bru_in_mcause_valid; + input [31:0] io_bru_in_mcause_bits; + input io_bru_in_mepc_valid; + input [31:0] io_bru_in_mepc_bits; + input io_bru_in_mtval_valid; + input [31:0] io_bru_in_mtval_bits; + input io_bru_in_halt; + input io_bru_in_fault; + input io_bru_in_wfi; + output wire [1:0] io_bru_out_mode; + output wire [31:0] io_bru_out_mepc; + output wire [31:0] io_bru_out_mtvec; + input io_float_in_fflags_valid; + input [4:0] io_float_in_fflags_bits; + output wire [2:0] io_float_out_frm; + input [3:0] io_counters_nRetired; + output wire io_halted; + output wire io_fault; + output wire io_wfi; + input io_irq; + reg req_valid; + reg [4:0] req_bits_addr; + reg [11:0] req_bits_index; + reg [4:0] req_bits_rs1; + reg [1:0] req_bits_op; + reg halted; + reg fault; + reg wfi; + reg [1:0] mode; + reg [31:0] mpc; + reg [31:0] msp; + reg [31:0] mcause; + reg [31:0] mtval; + reg [31:0] mcontext0; + reg [31:0] mcontext1; + reg [31:0] mcontext2; + reg [31:0] mcontext3; + reg [31:0] mcontext4; + reg [31:0] mcontext5; + reg [31:0] mcontext6; + reg [31:0] mcontext7; + reg [4:0] fflags; + reg [2:0] frm; + reg mie; + reg [31:0] mtvec; + reg [31:0] mscratch; + reg [31:0] mepc; + reg [1:0] mpp; + reg [63:0] mcycle; + reg [63:0] minstret; + wire fflagsEn = req_bits_index == 12'h001; + wire frmEn = req_bits_index == 12'h002; + wire fcsrEn = req_bits_index == 12'h003; + wire mstatusEn = req_bits_index == 12'h300; + wire misaEn = req_bits_index == 12'h301; + wire mieEn = req_bits_index == 12'h304; + wire mtvecEn = req_bits_index == 12'h305; + wire mscratchEn = req_bits_index == 12'h340; + wire mepcEn = req_bits_index == 12'h341; + wire mcauseEn = req_bits_index == 12'h342; + wire mtvalEn = req_bits_index == 12'h343; + wire mcontext0En = req_bits_index == 12'h7c0; + wire mcontext1En = req_bits_index == 12'h7c1; + wire mcontext2En = req_bits_index == 12'h7c2; + wire mcontext3En = req_bits_index == 12'h7c3; + wire mcontext4En = req_bits_index == 12'h7c4; + wire mcontext5En = req_bits_index == 12'h7c5; + wire mcontext6En = req_bits_index == 12'h7c6; + wire mcontext7En = req_bits_index == 12'h7c7; + wire mpcEn = req_bits_index == 12'h7e0; + wire mspEn = req_bits_index == 12'h7e1; + wire mcycleEn = req_bits_index == 12'hb00; + wire minstretEn = req_bits_index == 12'hb02; + wire mcyclehEn = req_bits_index == 12'hb80; + wire minstrethEn = req_bits_index == 12'hb82; + wire mvendoridEn = req_bits_index == 12'hf11; + wire kscm0En = req_bits_index == 12'hfc4; + wire kscm1En = req_bits_index == 12'hfc8; + wire kscm2En = req_bits_index == 12'hfcc; + wire kscm3En = req_bits_index == 12'hfd0; + wire kscm4En = req_bits_index == 12'hfd4; + wire [31:0] rdata = ((((((((((((((((((((((((((((((fflagsEn ? {27'h0000000, fflags} : 32'h00000000) | (frmEn ? {29'h00000000, frm} : 32'h00000000)) | (fcsrEn ? {24'h000000, frm, fflags} : 32'h00000000)) | (mstatusEn ? {19'h00001, mpp, 11'h000} : 32'h00000000)) | (misaEn ? 32'h40001120 : 32'h00000000)) | (mieEn ? {31'h00000000, mie} : 32'h00000000)) | (mtvecEn ? mtvec : 32'h00000000)) | (mscratchEn ? mscratch : 32'h00000000)) | (mepcEn ? mepc : 32'h00000000)) | (mcauseEn ? mcause : 32'h00000000)) | (mtvalEn ? mtval : 32'h00000000)) | (mcontext0En ? mcontext0 : 32'h00000000)) | (mcontext1En ? mcontext1 : 32'h00000000)) | (mcontext2En ? mcontext2 : 32'h00000000)) | (mcontext3En ? mcontext3 : 32'h00000000)) | (mcontext4En ? mcontext4 : 32'h00000000)) | (mcontext5En ? mcontext5 : 32'h00000000)) | (mcontext6En ? mcontext6 : 32'h00000000)) | (mcontext7En ? mcontext7 : 32'h00000000)) | (mpcEn ? mpc : 32'h00000000)) | (mspEn ? msp : 32'h00000000)) | (mcycleEn ? mcycle[31:0] : 32'h00000000)) | (mcyclehEn ? mcycle[63:32] : 32'h00000000)) | (minstretEn ? minstret[31:0] : 32'h00000000)) | (minstrethEn ? minstret[63:32] : 32'h00000000)) | (mvendoridEn ? 32'h00000426 : 32'h00000000)) | (kscm0En ? 32'h74deff88 : 32'h00000000)) | (kscm1En ? 32'hd2253c49 : 32'h00000000)) | (kscm2En ? 32'h8097dcda : 32'h00000000)) | (kscm3En ? 32'h70ac9a28 : 32'h00000000)) | (kscm4En ? 32'h7731fd6e : 32'h00000000); + wire [127:0] _GEN = {32'h00000000, rdata & ~io_rs1_data, rdata | io_rs1_data, io_rs1_data}; + wire [31:0] wdata = _GEN[req_bits_op * 32+:32]; + wire is_csr_write = req_valid & ~(|{req_bits_op == 2'h2, req_bits_op == 2'h1} & (req_bits_rs1 == 5'h00)); + always @(posedge clock or posedge reset) + if (reset) begin + req_valid <= 1'h0; + req_bits_addr <= 5'h00; + req_bits_index <= 12'h000; + req_bits_rs1 <= 5'h00; + req_bits_op <= 2'h0; + halted <= 1'h0; + fault <= 1'h0; + wfi <= 1'h0; + mode <= 2'h0; + mpc <= 32'h00000000; + msp <= 32'h00000000; + mcause <= 32'h00000000; + mtval <= 32'h00000000; + mcontext0 <= 32'h00000000; + mcontext1 <= 32'h00000000; + mcontext2 <= 32'h00000000; + mcontext3 <= 32'h00000000; + mcontext4 <= 32'h00000000; + mcontext5 <= 32'h00000000; + mcontext6 <= 32'h00000000; + mcontext7 <= 32'h00000000; + fflags <= 5'h00; + frm <= 3'h0; + mie <= 1'h0; + mtvec <= 32'h00000000; + mscratch <= 32'h00000000; + mepc <= 32'h00000000; + mpp <= 2'h0; + mcycle <= 64'h0000000000000000; + minstret <= 64'h0000000000000000; + end + else begin + req_valid <= io_req_valid; + if (io_req_valid) begin + req_bits_addr <= io_req_bits_addr; + req_bits_index <= io_req_bits_index; + req_bits_rs1 <= io_req_bits_rs1; + req_bits_op <= io_req_bits_op; + end + halted <= io_bru_in_halt | halted; + fault <= io_bru_in_fault | fault; + if (wfi) + wfi <= ~io_irq; + else + wfi <= io_bru_in_wfi; + if (io_bru_in_mode_valid) + mode <= io_bru_in_mode_bits; + if (req_valid & mpcEn) + mpc <= wdata; + if (req_valid & mspEn) + msp <= wdata; + if (io_bru_in_mcause_valid) + mcause <= io_bru_in_mcause_bits; + else if (req_valid & mcauseEn) + mcause <= wdata; + if (io_bru_in_mtval_valid) + mtval <= io_bru_in_mtval_bits; + else if (req_valid & mtvalEn) + mtval <= wdata; + if (req_valid & mcontext0En) + mcontext0 <= wdata; + if (req_valid & mcontext1En) + mcontext1 <= wdata; + if (req_valid & mcontext2En) + mcontext2 <= wdata; + if (req_valid & mcontext3En) + mcontext3 <= wdata; + if (req_valid & mcontext4En) + mcontext4 <= wdata; + if (req_valid & mcontext5En) + mcontext5 <= wdata; + if (req_valid & mcontext6En) + mcontext6 <= wdata; + if (req_valid & mcontext7En) + mcontext7 <= wdata; + if (io_float_in_fflags_valid) + fflags <= io_float_in_fflags_bits | fflags; + else if (req_valid) begin + if (fcsrEn) + fflags <= wdata[4:0]; + else if (fflagsEn) + fflags <= wdata[4:0]; + end + if (req_valid) begin + if (fcsrEn) + frm <= wdata[7:5]; + else if (frmEn) + frm <= wdata[2:0]; + end + if (req_valid & mieEn) + mie <= wdata[0]; + if (req_valid & mtvecEn) + mtvec <= wdata; + if (req_valid & mscratchEn) + mscratch <= wdata; + if (io_bru_in_mepc_valid) + mepc <= io_bru_in_mepc_bits; + else if (req_valid & mepcEn) + mepc <= wdata; + if (req_valid & mstatusEn) + mpp <= wdata[12:11]; + mcycle <= (is_csr_write & (mcycleEn | mcyclehEn) ? {(mcyclehEn ? wdata : mcycle[63:32]), (mcycleEn ? wdata : mcycle[31:0])} : mcycle + 64'h0000000000000001); + minstret <= (is_csr_write & (minstretEn | minstrethEn) ? {(minstrethEn ? wdata : minstret[63:32]), (minstretEn ? wdata : minstret[31:0])} : minstret + {60'h000000000000000, io_counters_nRetired}); + end + assign io_csr_out_value_0 = io_csr_in_value_12; + assign io_csr_out_value_1 = mepc; + assign io_csr_out_value_2 = mtval; + assign io_csr_out_value_3 = mcause; + assign io_csr_out_value_4 = mcycle[31:0]; + assign io_csr_out_value_5 = mcycle[63:32]; + assign io_csr_out_value_6 = minstret[31:0]; + assign io_csr_out_value_7 = minstret[63:32]; + assign io_csr_out_value_8 = mcontext0; + assign io_rd_valid = req_valid; + assign io_rd_bits_addr = req_bits_addr; + assign io_rd_bits_data = rdata; + assign io_bru_out_mode = mode; + assign io_bru_out_mepc = (mepcEn & req_valid ? wdata : mepc); + assign io_bru_out_mtvec = (mtvecEn & req_valid ? wdata : mtvec); + assign io_float_out_frm = (frmEn & req_valid ? wdata[2:0] : frm); + assign io_halted = halted; + assign io_fault = fault; + assign io_wfi = wfi; +endmodule +module DispatchV2 ( + clock, + reset, + io_halted, + io_lsuActive, + io_scoreboard_regd, + io_scoreboard_comb, + io_fscoreboard, + io_branchTaken, + io_csrFault_0, + io_jalFault_0, + io_jalFault_1, + io_jalFault_2, + io_jalFault_3, + io_jalrFault_0, + io_jalrFault_1, + io_jalrFault_2, + io_jalrFault_3, + io_bxxFault_0, + io_bxxFault_1, + io_bxxFault_2, + io_bxxFault_3, + io_undefFault_0, + io_bruTarget_0, + io_bruTarget_1, + io_bruTarget_2, + io_bruTarget_3, + io_jalrTarget_0_data, + io_jalrTarget_1_data, + io_jalrTarget_2_data, + io_jalrTarget_3_data, + io_interlock, + io_inst_0_ready, + io_inst_0_valid, + io_inst_0_bits_addr, + io_inst_0_bits_inst, + io_inst_0_bits_brchFwd, + io_inst_1_ready, + io_inst_1_valid, + io_inst_1_bits_addr, + io_inst_1_bits_inst, + io_inst_1_bits_brchFwd, + io_inst_2_ready, + io_inst_2_valid, + io_inst_2_bits_addr, + io_inst_2_bits_inst, + io_inst_2_bits_brchFwd, + io_inst_3_ready, + io_inst_3_valid, + io_inst_3_bits_addr, + io_inst_3_bits_inst, + io_inst_3_bits_brchFwd, + io_rs1Read_0_valid, + io_rs1Read_0_addr, + io_rs1Read_1_valid, + io_rs1Read_1_addr, + io_rs1Read_2_valid, + io_rs1Read_2_addr, + io_rs1Read_3_valid, + io_rs1Read_3_addr, + io_rs1Set_0_valid, + io_rs1Set_0_value, + io_rs1Set_1_valid, + io_rs1Set_1_value, + io_rs1Set_2_valid, + io_rs1Set_2_value, + io_rs1Set_3_valid, + io_rs1Set_3_value, + io_rs2Read_0_valid, + io_rs2Read_0_addr, + io_rs2Read_1_valid, + io_rs2Read_1_addr, + io_rs2Read_2_valid, + io_rs2Read_2_addr, + io_rs2Read_3_valid, + io_rs2Read_3_addr, + io_rs2Set_0_valid, + io_rs2Set_0_value, + io_rs2Set_1_valid, + io_rs2Set_1_value, + io_rs2Set_2_valid, + io_rs2Set_2_value, + io_rs2Set_3_valid, + io_rs2Set_3_value, + io_rdMark_0_valid, + io_rdMark_0_addr, + io_rdMark_1_valid, + io_rdMark_1_addr, + io_rdMark_2_valid, + io_rdMark_2_addr, + io_rdMark_3_valid, + io_rdMark_3_addr, + io_busRead_0_bypass, + io_busRead_0_immen, + io_busRead_0_immed, + io_busRead_1_bypass, + io_busRead_1_immed, + io_busRead_2_bypass, + io_busRead_2_immed, + io_busRead_3_bypass, + io_busRead_3_immed, + io_rdMark_flt_valid, + io_rdMark_flt_addr, + io_alu_0_valid, + io_alu_0_bits_addr, + io_alu_0_bits_op, + io_alu_1_valid, + io_alu_1_bits_addr, + io_alu_1_bits_op, + io_alu_2_valid, + io_alu_2_bits_addr, + io_alu_2_bits_op, + io_alu_3_valid, + io_alu_3_bits_addr, + io_alu_3_bits_op, + io_bru_0_valid, + io_bru_0_bits_fwd, + io_bru_0_bits_op, + io_bru_0_bits_pc, + io_bru_0_bits_target, + io_bru_0_bits_link, + io_bru_1_valid, + io_bru_1_bits_fwd, + io_bru_1_bits_op, + io_bru_1_bits_pc, + io_bru_1_bits_target, + io_bru_1_bits_link, + io_bru_2_valid, + io_bru_2_bits_fwd, + io_bru_2_bits_op, + io_bru_2_bits_pc, + io_bru_2_bits_target, + io_bru_2_bits_link, + io_bru_3_valid, + io_bru_3_bits_fwd, + io_bru_3_bits_op, + io_bru_3_bits_pc, + io_bru_3_bits_target, + io_bru_3_bits_link, + io_csr_valid, + io_csr_bits_addr, + io_csr_bits_index, + io_csr_bits_rs1, + io_csr_bits_op, + io_lsu_0_ready, + io_lsu_0_valid, + io_lsu_0_bits_store, + io_lsu_0_bits_addr, + io_lsu_0_bits_op, + io_lsu_0_bits_pc, + io_lsu_1_ready, + io_lsu_1_valid, + io_lsu_1_bits_store, + io_lsu_1_bits_addr, + io_lsu_1_bits_op, + io_lsu_1_bits_pc, + io_lsu_2_ready, + io_lsu_2_valid, + io_lsu_2_bits_store, + io_lsu_2_bits_addr, + io_lsu_2_bits_op, + io_lsu_2_bits_pc, + io_lsu_3_ready, + io_lsu_3_valid, + io_lsu_3_bits_store, + io_lsu_3_bits_addr, + io_lsu_3_bits_op, + io_lsu_3_bits_pc, + io_lsuQueueCapacity, + io_mlu_0_valid, + io_mlu_0_bits_addr, + io_mlu_0_bits_op, + io_mlu_1_ready, + io_mlu_1_valid, + io_mlu_1_bits_addr, + io_mlu_1_bits_op, + io_mlu_2_ready, + io_mlu_2_valid, + io_mlu_2_bits_addr, + io_mlu_2_bits_op, + io_mlu_3_ready, + io_mlu_3_valid, + io_mlu_3_bits_addr, + io_mlu_3_bits_op, + io_dvu_0_ready, + io_dvu_0_valid, + io_dvu_0_bits_addr, + io_dvu_0_bits_op, + io_float_ready, + io_float_valid, + io_float_bits_opcode, + io_float_bits_funct5, + io_float_bits_rs3, + io_float_bits_rs2, + io_float_bits_rs1, + io_float_bits_rm, + io_float_bits_inst, + io_float_bits_pc, + io_float_bits_scalar_rd, + io_float_bits_scalar_rs1, + io_float_bits_float_rs1, + io_float_bits_rd, + io_float_bits_uses_rs3, + io_float_bits_uses_rs2, + io_csrFrm, + io_fbusPortAddr, + io_retirement_buffer_nSpace, + io_retirement_buffer_empty, + io_retirement_buffer_trap_pending, + io_branch_0, + io_branch_1, + io_branch_2, + io_branch_3, + io_jump_0, + io_jump_1, + io_jump_2, + io_jump_3 +); + input clock; + input reset; + input io_halted; + input io_lsuActive; + input [31:0] io_scoreboard_regd; + input [31:0] io_scoreboard_comb; + input [31:0] io_fscoreboard; + input io_branchTaken; + output wire io_csrFault_0; + output wire io_jalFault_0; + output wire io_jalFault_1; + output wire io_jalFault_2; + output wire io_jalFault_3; + output wire io_jalrFault_0; + output wire io_jalrFault_1; + output wire io_jalrFault_2; + output wire io_jalrFault_3; + output wire io_bxxFault_0; + output wire io_bxxFault_1; + output wire io_bxxFault_2; + output wire io_bxxFault_3; + output wire io_undefFault_0; + output wire [31:0] io_bruTarget_0; + output wire [31:0] io_bruTarget_1; + output wire [31:0] io_bruTarget_2; + output wire [31:0] io_bruTarget_3; + input [31:0] io_jalrTarget_0_data; + input [31:0] io_jalrTarget_1_data; + input [31:0] io_jalrTarget_2_data; + input [31:0] io_jalrTarget_3_data; + input io_interlock; + output wire io_inst_0_ready; + input io_inst_0_valid; + input [31:0] io_inst_0_bits_addr; + input [31:0] io_inst_0_bits_inst; + input io_inst_0_bits_brchFwd; + output wire io_inst_1_ready; + input io_inst_1_valid; + input [31:0] io_inst_1_bits_addr; + input [31:0] io_inst_1_bits_inst; + input io_inst_1_bits_brchFwd; + output wire io_inst_2_ready; + input io_inst_2_valid; + input [31:0] io_inst_2_bits_addr; + input [31:0] io_inst_2_bits_inst; + input io_inst_2_bits_brchFwd; + output wire io_inst_3_ready; + input io_inst_3_valid; + input [31:0] io_inst_3_bits_addr; + input [31:0] io_inst_3_bits_inst; + input io_inst_3_bits_brchFwd; + output wire io_rs1Read_0_valid; + output wire [4:0] io_rs1Read_0_addr; + output wire io_rs1Read_1_valid; + output wire [4:0] io_rs1Read_1_addr; + output wire io_rs1Read_2_valid; + output wire [4:0] io_rs1Read_2_addr; + output wire io_rs1Read_3_valid; + output wire [4:0] io_rs1Read_3_addr; + output wire io_rs1Set_0_valid; + output wire [31:0] io_rs1Set_0_value; + output wire io_rs1Set_1_valid; + output wire [31:0] io_rs1Set_1_value; + output wire io_rs1Set_2_valid; + output wire [31:0] io_rs1Set_2_value; + output wire io_rs1Set_3_valid; + output wire [31:0] io_rs1Set_3_value; + output wire io_rs2Read_0_valid; + output wire [4:0] io_rs2Read_0_addr; + output wire io_rs2Read_1_valid; + output wire [4:0] io_rs2Read_1_addr; + output wire io_rs2Read_2_valid; + output wire [4:0] io_rs2Read_2_addr; + output wire io_rs2Read_3_valid; + output wire [4:0] io_rs2Read_3_addr; + output wire io_rs2Set_0_valid; + output wire [31:0] io_rs2Set_0_value; + output wire io_rs2Set_1_valid; + output wire [31:0] io_rs2Set_1_value; + output wire io_rs2Set_2_valid; + output wire [31:0] io_rs2Set_2_value; + output wire io_rs2Set_3_valid; + output wire [31:0] io_rs2Set_3_value; + output wire io_rdMark_0_valid; + output wire [4:0] io_rdMark_0_addr; + output wire io_rdMark_1_valid; + output wire [4:0] io_rdMark_1_addr; + output wire io_rdMark_2_valid; + output wire [4:0] io_rdMark_2_addr; + output wire io_rdMark_3_valid; + output wire [4:0] io_rdMark_3_addr; + output wire io_busRead_0_bypass; + output wire io_busRead_0_immen; + output wire [31:0] io_busRead_0_immed; + output wire io_busRead_1_bypass; + output wire [31:0] io_busRead_1_immed; + output wire io_busRead_2_bypass; + output wire [31:0] io_busRead_2_immed; + output wire io_busRead_3_bypass; + output wire [31:0] io_busRead_3_immed; + output wire io_rdMark_flt_valid; + output wire [4:0] io_rdMark_flt_addr; + output wire io_alu_0_valid; + output wire [4:0] io_alu_0_bits_addr; + output wire [4:0] io_alu_0_bits_op; + output wire io_alu_1_valid; + output wire [4:0] io_alu_1_bits_addr; + output wire [4:0] io_alu_1_bits_op; + output wire io_alu_2_valid; + output wire [4:0] io_alu_2_bits_addr; + output wire [4:0] io_alu_2_bits_op; + output wire io_alu_3_valid; + output wire [4:0] io_alu_3_bits_addr; + output wire [4:0] io_alu_3_bits_op; + output wire io_bru_0_valid; + output wire io_bru_0_bits_fwd; + output wire [3:0] io_bru_0_bits_op; + output wire [31:0] io_bru_0_bits_pc; + output wire [31:0] io_bru_0_bits_target; + output wire [4:0] io_bru_0_bits_link; + output wire io_bru_1_valid; + output wire io_bru_1_bits_fwd; + output wire [3:0] io_bru_1_bits_op; + output wire [31:0] io_bru_1_bits_pc; + output wire [31:0] io_bru_1_bits_target; + output wire [4:0] io_bru_1_bits_link; + output wire io_bru_2_valid; + output wire io_bru_2_bits_fwd; + output wire [3:0] io_bru_2_bits_op; + output wire [31:0] io_bru_2_bits_pc; + output wire [31:0] io_bru_2_bits_target; + output wire [4:0] io_bru_2_bits_link; + output wire io_bru_3_valid; + output wire io_bru_3_bits_fwd; + output wire [3:0] io_bru_3_bits_op; + output wire [31:0] io_bru_3_bits_pc; + output wire [31:0] io_bru_3_bits_target; + output wire [4:0] io_bru_3_bits_link; + output wire io_csr_valid; + output wire [4:0] io_csr_bits_addr; + output wire [11:0] io_csr_bits_index; + output wire [4:0] io_csr_bits_rs1; + output wire [1:0] io_csr_bits_op; + input io_lsu_0_ready; + output wire io_lsu_0_valid; + output wire io_lsu_0_bits_store; + output wire [4:0] io_lsu_0_bits_addr; + output wire [4:0] io_lsu_0_bits_op; + output wire [31:0] io_lsu_0_bits_pc; + input io_lsu_1_ready; + output wire io_lsu_1_valid; + output wire io_lsu_1_bits_store; + output wire [4:0] io_lsu_1_bits_addr; + output wire [4:0] io_lsu_1_bits_op; + output wire [31:0] io_lsu_1_bits_pc; + input io_lsu_2_ready; + output wire io_lsu_2_valid; + output wire io_lsu_2_bits_store; + output wire [4:0] io_lsu_2_bits_addr; + output wire [4:0] io_lsu_2_bits_op; + output wire [31:0] io_lsu_2_bits_pc; + input io_lsu_3_ready; + output wire io_lsu_3_valid; + output wire io_lsu_3_bits_store; + output wire [4:0] io_lsu_3_bits_addr; + output wire [4:0] io_lsu_3_bits_op; + output wire [31:0] io_lsu_3_bits_pc; + input [2:0] io_lsuQueueCapacity; + output wire io_mlu_0_valid; + output wire [4:0] io_mlu_0_bits_addr; + output wire [2:0] io_mlu_0_bits_op; + input io_mlu_1_ready; + output wire io_mlu_1_valid; + output wire [4:0] io_mlu_1_bits_addr; + output wire [2:0] io_mlu_1_bits_op; + input io_mlu_2_ready; + output wire io_mlu_2_valid; + output wire [4:0] io_mlu_2_bits_addr; + output wire [2:0] io_mlu_2_bits_op; + input io_mlu_3_ready; + output wire io_mlu_3_valid; + output wire [4:0] io_mlu_3_bits_addr; + output wire [2:0] io_mlu_3_bits_op; + input io_dvu_0_ready; + output wire io_dvu_0_valid; + output wire [4:0] io_dvu_0_bits_addr; + output wire [1:0] io_dvu_0_bits_op; + input io_float_ready; + output wire io_float_valid; + output wire [2:0] io_float_bits_opcode; + output wire [4:0] io_float_bits_funct5; + output wire [4:0] io_float_bits_rs3; + output wire [4:0] io_float_bits_rs2; + output wire [4:0] io_float_bits_rs1; + output wire [2:0] io_float_bits_rm; + output wire [31:0] io_float_bits_inst; + output wire [31:0] io_float_bits_pc; + output wire io_float_bits_scalar_rd; + output wire io_float_bits_scalar_rs1; + output wire io_float_bits_float_rs1; + output wire [4:0] io_float_bits_rd; + output wire io_float_bits_uses_rs3; + output wire io_float_bits_uses_rs2; + input [2:0] io_csrFrm; + output wire [4:0] io_fbusPortAddr; + input [4:0] io_retirement_buffer_nSpace; + input io_retirement_buffer_empty; + input io_retirement_buffer_trap_pending; + output wire io_branch_0; + output wire io_branch_1; + output wire io_branch_2; + output wire io_branch_3; + output wire io_jump_0; + output wire io_jump_1; + output wire io_jump_2; + output wire io_jump_3; + wire [19:0] _decodedInsts_d_imm12_T_1 = {20 {io_inst_0_bits_inst[31]}}; + wire [31:0] decodedInsts_0_immcsr = {27'h0000000, io_inst_0_bits_inst[19:15]}; + wire decodedInsts_0_lui = io_inst_0_bits_inst[6:0] == 7'h37; + wire decodedInsts_0_auipc = io_inst_0_bits_inst[6:0] == 7'h17; + wire decodedInsts_0_jal = io_inst_0_bits_inst[6:0] == 7'h6f; + wire [9:0] _GEN = {io_inst_0_bits_inst[14:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_jalr = _GEN == 10'h067; + wire decodedInsts_0_beq = _GEN == 10'h063; + wire decodedInsts_0_bne = _GEN == 10'h0e3; + wire decodedInsts_0_blt = _GEN == 10'h263; + wire decodedInsts_0_bge = _GEN == 10'h2e3; + wire decodedInsts_0_bltu = _GEN == 10'h363; + wire decodedInsts_0_bgeu = _GEN == 10'h3e3; + wire [8:0] _GEN_0 = {io_inst_0_bits_inst[13:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_csrrw = _GEN_0 == 9'h0f3; + wire decodedInsts_0_csrrs = _GEN_0 == 9'h173; + wire decodedInsts_0_csrrc = _GEN_0 == 9'h1f3; + wire decodedInsts_0_lb = _GEN == 10'h003; + wire decodedInsts_0_lh = _GEN == 10'h083; + wire decodedInsts_0_lw = _GEN == 10'h103; + wire decodedInsts_0_lbu = _GEN == 10'h203; + wire decodedInsts_0_lhu = _GEN == 10'h283; + wire decodedInsts_0_sb = _GEN == 10'h023; + wire decodedInsts_0_sh = _GEN == 10'h0a3; + wire decodedInsts_0_sw = _GEN == 10'h123; + wire decodedInsts_0_fence = {io_inst_0_bits_inst[31:28], io_inst_0_bits_inst[19:0]} == 24'h00000f; + wire decodedInsts_0_addi = _GEN == 10'h013; + wire decodedInsts_0_slti = _GEN == 10'h113; + wire decodedInsts_0_sltiu = _GEN == 10'h193; + wire decodedInsts_0_xori = _GEN == 10'h213; + wire decodedInsts_0_ori = _GEN == 10'h313; + wire decodedInsts_0_andi = _GEN == 10'h393; + wire [16:0] _GEN_1 = {io_inst_0_bits_inst[31:25], io_inst_0_bits_inst[14:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_slli = _GEN_1 == 17'h00093; + wire decodedInsts_0_srli = _GEN_1 == 17'h00293; + wire decodedInsts_0_srai = _GEN_1 == 17'h08293; + wire decodedInsts_0_add = _GEN_1 == 17'h00033; + wire decodedInsts_0_sub = _GEN_1 == 17'h08033; + wire decodedInsts_0_slt = _GEN_1 == 17'h00133; + wire decodedInsts_0_sltu = _GEN_1 == 17'h001b3; + wire decodedInsts_0_xor = _GEN_1 == 17'h00233; + wire decodedInsts_0_or = _GEN_1 == 17'h00333; + wire decodedInsts_0_and = _GEN_1 == 17'h003b3; + wire decodedInsts_0_sll = _GEN_1 == 17'h000b3; + wire decodedInsts_0_srl = _GEN_1 == 17'h002b3; + wire decodedInsts_0_sra = _GEN_1 == 17'h082b3; + wire decodedInsts_0_mul = _GEN_1 == 17'h00433; + wire decodedInsts_0_mulh = _GEN_1 == 17'h004b3; + wire decodedInsts_0_mulhsu = _GEN_1 == 17'h00533; + wire decodedInsts_0_mulhu = _GEN_1 == 17'h005b3; + wire decodedInsts_0_div = _GEN_1 == 17'h00633; + wire decodedInsts_0_divu = _GEN_1 == 17'h006b3; + wire decodedInsts_0_rem = _GEN_1 == 17'h00733; + wire decodedInsts_0_remu = _GEN_1 == 17'h007b3; + wire decodedInsts_0_andn = _GEN_1 == 17'h083b3; + wire decodedInsts_0_orn = _GEN_1 == 17'h08333; + wire decodedInsts_0_xnor = _GEN_1 == 17'h08233; + wire [21:0] _GEN_2 = {io_inst_0_bits_inst[31:20], io_inst_0_bits_inst[14:12], io_inst_0_bits_inst[6:0]}; + wire decodedInsts_0_clz = _GEN_2 == 22'h180093; + wire decodedInsts_0_ctz = _GEN_2 == 22'h180493; + wire decodedInsts_0_cpop = _GEN_2 == 22'h180893; + wire decodedInsts_0_max = _GEN_1 == 17'h01733; + wire decodedInsts_0_maxu = _GEN_1 == 17'h017b3; + wire decodedInsts_0_min = _GEN_1 == 17'h01633; + wire decodedInsts_0_minu = _GEN_1 == 17'h016b3; + wire decodedInsts_0_sextb = _GEN_2 == 22'h181093; + wire decodedInsts_0_sexth = _GEN_2 == 22'h181493; + wire decodedInsts_0_rol = _GEN_1 == 17'h0c0b3; + wire decodedInsts_0_ror = _GEN_1 == 17'h0c2b3; + wire decodedInsts_0_orcb = _GEN_2 == 22'h0a1e93; + wire decodedInsts_0_rev8 = _GEN_2 == 22'h1a6293; + wire decodedInsts_0_zexth = _GEN_2 == 22'h020233; + wire decodedInsts_0_rori = _GEN_1 == 17'h0c293; + wire decodedInsts_0_ebreak = io_inst_0_bits_inst == 32'h00100073; + wire decodedInsts_0_ecall = io_inst_0_bits_inst == 32'h00000073; + wire decodedInsts_0_mpause = io_inst_0_bits_inst == 32'h08000073; + wire decodedInsts_0_mret = io_inst_0_bits_inst == 32'h30200073; + wire decodedInsts_0_wfi = io_inst_0_bits_inst == 32'h10500073; + wire decodedInsts_0_fencei = io_inst_0_bits_inst == 32'h0000100f; + wire decodedInsts_0_flushat = ({io_inst_0_bits_inst[31:28], io_inst_0_bits_inst[24:20], io_inst_0_bits_inst[14:0]} == 24'h200077) & |io_inst_0_bits_inst[19:15]; + wire decodedInsts_0_flushall = {io_inst_0_bits_inst[31:28], io_inst_0_bits_inst[24:0]} == 29'h04000077; + wire decodedInsts_float_load_store_rm_valid = (io_inst_0_bits_inst[14:12] == 3'h1) | (io_inst_0_bits_inst[14:12] == 3'h2); + wire _decodedInsts_float_opcode_T_4 = io_inst_0_bits_inst[6:2] == 5'h09; + wire _decodedInsts_float_opcode_T_6 = io_inst_0_bits_inst[6:2] == 5'h14; + wire _decodedInsts_float_opcode_T_8 = io_inst_0_bits_inst[6:2] == 5'h10; + wire _decodedInsts_float_opcode_T_10 = io_inst_0_bits_inst[6:2] == 5'h11; + wire _decodedInsts_float_opcode_T_12 = io_inst_0_bits_inst[6:2] == 5'h12; + wire _decodedInsts_float_opcode_T_14 = io_inst_0_bits_inst[6:2] == 5'h13; + wire [2:0] decodedInsts_float_bits_opcode = (_decodedInsts_float_opcode_T_14 ? 3'h5 : (_decodedInsts_float_opcode_T_12 ? 3'h6 : (_decodedInsts_float_opcode_T_10 ? 3'h4 : (_decodedInsts_float_opcode_T_8 ? 3'h3 : (_decodedInsts_float_opcode_T_6 ? 3'h2 : {2'h0, _decodedInsts_float_opcode_T_4 & decodedInsts_float_load_store_rm_valid}))))); + wire _decodedInsts_float_uses_rs2_T_5 = io_inst_0_bits_inst[31:27] == 5'h1c; + wire _decodedInsts_float_uses_rs2_T_7 = io_inst_0_bits_inst[31:27] == 5'h18; + wire _decodedInsts_float_uses_rs2_T_2 = decodedInsts_float_bits_opcode == 3'h2; + wire decodedInsts_float_scalar_rd = ((_decodedInsts_float_uses_rs2_T_7 | _decodedInsts_float_uses_rs2_T_5) | (io_inst_0_bits_inst[31:27] == 5'h14)) & _decodedInsts_float_uses_rs2_T_2; + wire _decodedInsts_float_uses_rs2_T_9 = io_inst_0_bits_inst[31:27] == 5'h1e; + wire _decodedInsts_float_uses_rs2_T_11 = io_inst_0_bits_inst[31:27] == 5'h1a; + wire decodedInsts_float_scalar_rs1 = _decodedInsts_float_uses_rs2_T_11 | _decodedInsts_float_uses_rs2_T_9; + wire [3:0] _decodedInsts_float_uses_rs3_T_4 = {decodedInsts_float_bits_opcode == 3'h6, decodedInsts_float_bits_opcode == 3'h5, decodedInsts_float_bits_opcode == 3'h4, decodedInsts_float_bits_opcode == 3'h3}; + wire _decodedInsts_float_T_1 = decodedInsts_float_bits_opcode == 3'h1; + wire decodedInsts_float_uses_rs2 = _decodedInsts_float_T_1 | ((_decodedInsts_float_uses_rs2_T_2 & ~(((((io_inst_0_bits_inst[31:27] == 5'h0b) | _decodedInsts_float_uses_rs2_T_11) | _decodedInsts_float_uses_rs2_T_9) | _decodedInsts_float_uses_rs2_T_7) | _decodedInsts_float_uses_rs2_T_5)) & (io_inst_0_bits_inst[31:27] != 5'h1c)); + wire _decodedInsts_float_T = decodedInsts_float_bits_opcode == 3'h0; + wire decodedInsts_float_float_rs1 = ({_decodedInsts_float_T, _decodedInsts_float_T_1} == 2'h0) & ~decodedInsts_float_scalar_rs1; + wire decodedInsts_floatValid = ((((((_decodedInsts_float_opcode_T_14 | _decodedInsts_float_opcode_T_12) | _decodedInsts_float_opcode_T_10) | _decodedInsts_float_opcode_T_8) | _decodedInsts_float_opcode_T_6) | ((_decodedInsts_float_opcode_T_4 | (io_inst_0_bits_inst[6:2] == 5'h01)) & decodedInsts_float_load_store_rm_valid)) & ((_decodedInsts_float_T | _decodedInsts_float_T_1) | (io_inst_0_bits_inst[26:25] == 2'h0))) & ((~(|{decodedInsts_float_bits_opcode == 3'h5, decodedInsts_float_bits_opcode == 3'h6, decodedInsts_float_bits_opcode == 3'h4, decodedInsts_float_bits_opcode == 3'h3} | ((decodedInsts_float_bits_opcode == 3'h2) & ((((((io_inst_0_bits_inst[31:27] == 5'h00) | (io_inst_0_bits_inst[31:27] == 5'h01)) | (io_inst_0_bits_inst[31:27] == 5'h02)) | (io_inst_0_bits_inst[31:27] == 5'h03)) | (io_inst_0_bits_inst[31:27] == 5'h04)) | (io_inst_0_bits_inst[31:27] == 5'h1a)))) | (io_inst_0_bits_inst[14:12] < 3'h5)) | (&io_inst_0_bits_inst[14:12] & (io_csrFrm < 3'h5))); + wire [19:0] _decodedInsts_d_imm12_T_5 = {20 {io_inst_1_bits_inst[31]}}; + wire decodedInsts_1_lui = io_inst_1_bits_inst[6:0] == 7'h37; + wire decodedInsts_1_auipc = io_inst_1_bits_inst[6:0] == 7'h17; + wire decodedInsts_1_jal = io_inst_1_bits_inst[6:0] == 7'h6f; + wire [9:0] _GEN_3 = {io_inst_1_bits_inst[14:12], io_inst_1_bits_inst[6:0]}; + wire decodedInsts_1_jalr = _GEN_3 == 10'h067; + wire decodedInsts_1_beq = _GEN_3 == 10'h063; + wire decodedInsts_1_bne = _GEN_3 == 10'h0e3; + wire decodedInsts_1_blt = _GEN_3 == 10'h263; + wire decodedInsts_1_bge = _GEN_3 == 10'h2e3; + wire decodedInsts_1_bltu = _GEN_3 == 10'h363; + wire decodedInsts_1_bgeu = _GEN_3 == 10'h3e3; + wire decodedInsts_1_lb = _GEN_3 == 10'h003; + wire decodedInsts_1_lh = _GEN_3 == 10'h083; + wire decodedInsts_1_lw = _GEN_3 == 10'h103; + wire decodedInsts_1_lbu = _GEN_3 == 10'h203; + wire decodedInsts_1_lhu = _GEN_3 == 10'h283; + wire decodedInsts_1_sb = _GEN_3 == 10'h023; + wire decodedInsts_1_sh = _GEN_3 == 10'h0a3; + wire decodedInsts_1_sw = _GEN_3 == 10'h123; + wire decodedInsts_1_addi = _GEN_3 == 10'h013; + wire decodedInsts_1_slti = _GEN_3 == 10'h113; + wire decodedInsts_1_sltiu = _GEN_3 == 10'h193; + wire decodedInsts_1_xori = _GEN_3 == 10'h213; + wire decodedInsts_1_ori = _GEN_3 == 10'h313; + wire decodedInsts_1_andi = _GEN_3 == 10'h393; + wire [16:0] _GEN_4 = {io_inst_1_bits_inst[31:25], io_inst_1_bits_inst[14:12], io_inst_1_bits_inst[6:0]}; + wire decodedInsts_1_slli = _GEN_4 == 17'h00093; + wire decodedInsts_1_srli = _GEN_4 == 17'h00293; + wire decodedInsts_1_srai = _GEN_4 == 17'h08293; + wire decodedInsts_1_add = _GEN_4 == 17'h00033; + wire decodedInsts_1_sub = _GEN_4 == 17'h08033; + wire decodedInsts_1_slt = _GEN_4 == 17'h00133; + wire decodedInsts_1_sltu = _GEN_4 == 17'h001b3; + wire decodedInsts_1_xor = _GEN_4 == 17'h00233; + wire decodedInsts_1_or = _GEN_4 == 17'h00333; + wire decodedInsts_1_and = _GEN_4 == 17'h003b3; + wire decodedInsts_1_sll = _GEN_4 == 17'h000b3; + wire decodedInsts_1_srl = _GEN_4 == 17'h002b3; + wire decodedInsts_1_sra = _GEN_4 == 17'h082b3; + wire decodedInsts_1_mul = _GEN_4 == 17'h00433; + wire decodedInsts_1_mulh = _GEN_4 == 17'h004b3; + wire decodedInsts_1_mulhsu = _GEN_4 == 17'h00533; + wire decodedInsts_1_mulhu = _GEN_4 == 17'h005b3; + wire decodedInsts_1_andn = _GEN_4 == 17'h083b3; + wire decodedInsts_1_orn = _GEN_4 == 17'h08333; + wire decodedInsts_1_xnor = _GEN_4 == 17'h08233; + wire [21:0] _GEN_5 = {io_inst_1_bits_inst[31:20], io_inst_1_bits_inst[14:12], io_inst_1_bits_inst[6:0]}; + wire decodedInsts_1_clz = _GEN_5 == 22'h180093; + wire decodedInsts_1_ctz = _GEN_5 == 22'h180493; + wire decodedInsts_1_cpop = _GEN_5 == 22'h180893; + wire decodedInsts_1_max = _GEN_4 == 17'h01733; + wire decodedInsts_1_maxu = _GEN_4 == 17'h017b3; + wire decodedInsts_1_min = _GEN_4 == 17'h01633; + wire decodedInsts_1_minu = _GEN_4 == 17'h016b3; + wire decodedInsts_1_sextb = _GEN_5 == 22'h181093; + wire decodedInsts_1_sexth = _GEN_5 == 22'h181493; + wire decodedInsts_1_rol = _GEN_4 == 17'h0c0b3; + wire decodedInsts_1_ror = _GEN_4 == 17'h0c2b3; + wire decodedInsts_1_orcb = _GEN_5 == 22'h0a1e93; + wire decodedInsts_1_rev8 = _GEN_5 == 22'h1a6293; + wire decodedInsts_1_zexth = _GEN_5 == 22'h020233; + wire decodedInsts_1_rori = _GEN_4 == 17'h0c293; + wire [19:0] _decodedInsts_d_imm12_T_9 = {20 {io_inst_2_bits_inst[31]}}; + wire decodedInsts_2_lui = io_inst_2_bits_inst[6:0] == 7'h37; + wire decodedInsts_2_auipc = io_inst_2_bits_inst[6:0] == 7'h17; + wire decodedInsts_2_jal = io_inst_2_bits_inst[6:0] == 7'h6f; + wire [9:0] _GEN_6 = {io_inst_2_bits_inst[14:12], io_inst_2_bits_inst[6:0]}; + wire decodedInsts_2_jalr = _GEN_6 == 10'h067; + wire decodedInsts_2_beq = _GEN_6 == 10'h063; + wire decodedInsts_2_bne = _GEN_6 == 10'h0e3; + wire decodedInsts_2_blt = _GEN_6 == 10'h263; + wire decodedInsts_2_bge = _GEN_6 == 10'h2e3; + wire decodedInsts_2_bltu = _GEN_6 == 10'h363; + wire decodedInsts_2_bgeu = _GEN_6 == 10'h3e3; + wire decodedInsts_2_lb = _GEN_6 == 10'h003; + wire decodedInsts_2_lh = _GEN_6 == 10'h083; + wire decodedInsts_2_lw = _GEN_6 == 10'h103; + wire decodedInsts_2_lbu = _GEN_6 == 10'h203; + wire decodedInsts_2_lhu = _GEN_6 == 10'h283; + wire decodedInsts_2_sb = _GEN_6 == 10'h023; + wire decodedInsts_2_sh = _GEN_6 == 10'h0a3; + wire decodedInsts_2_sw = _GEN_6 == 10'h123; + wire decodedInsts_2_addi = _GEN_6 == 10'h013; + wire decodedInsts_2_slti = _GEN_6 == 10'h113; + wire decodedInsts_2_sltiu = _GEN_6 == 10'h193; + wire decodedInsts_2_xori = _GEN_6 == 10'h213; + wire decodedInsts_2_ori = _GEN_6 == 10'h313; + wire decodedInsts_2_andi = _GEN_6 == 10'h393; + wire [16:0] _GEN_7 = {io_inst_2_bits_inst[31:25], io_inst_2_bits_inst[14:12], io_inst_2_bits_inst[6:0]}; + wire decodedInsts_2_slli = _GEN_7 == 17'h00093; + wire decodedInsts_2_srli = _GEN_7 == 17'h00293; + wire decodedInsts_2_srai = _GEN_7 == 17'h08293; + wire decodedInsts_2_add = _GEN_7 == 17'h00033; + wire decodedInsts_2_sub = _GEN_7 == 17'h08033; + wire decodedInsts_2_slt = _GEN_7 == 17'h00133; + wire decodedInsts_2_sltu = _GEN_7 == 17'h001b3; + wire decodedInsts_2_xor = _GEN_7 == 17'h00233; + wire decodedInsts_2_or = _GEN_7 == 17'h00333; + wire decodedInsts_2_and = _GEN_7 == 17'h003b3; + wire decodedInsts_2_sll = _GEN_7 == 17'h000b3; + wire decodedInsts_2_srl = _GEN_7 == 17'h002b3; + wire decodedInsts_2_sra = _GEN_7 == 17'h082b3; + wire decodedInsts_2_mul = _GEN_7 == 17'h00433; + wire decodedInsts_2_mulh = _GEN_7 == 17'h004b3; + wire decodedInsts_2_mulhsu = _GEN_7 == 17'h00533; + wire decodedInsts_2_mulhu = _GEN_7 == 17'h005b3; + wire decodedInsts_2_andn = _GEN_7 == 17'h083b3; + wire decodedInsts_2_orn = _GEN_7 == 17'h08333; + wire decodedInsts_2_xnor = _GEN_7 == 17'h08233; + wire [21:0] _GEN_8 = {io_inst_2_bits_inst[31:20], io_inst_2_bits_inst[14:12], io_inst_2_bits_inst[6:0]}; + wire decodedInsts_2_clz = _GEN_8 == 22'h180093; + wire decodedInsts_2_ctz = _GEN_8 == 22'h180493; + wire decodedInsts_2_cpop = _GEN_8 == 22'h180893; + wire decodedInsts_2_max = _GEN_7 == 17'h01733; + wire decodedInsts_2_maxu = _GEN_7 == 17'h017b3; + wire decodedInsts_2_min = _GEN_7 == 17'h01633; + wire decodedInsts_2_minu = _GEN_7 == 17'h016b3; + wire decodedInsts_2_sextb = _GEN_8 == 22'h181093; + wire decodedInsts_2_sexth = _GEN_8 == 22'h181493; + wire decodedInsts_2_rol = _GEN_7 == 17'h0c0b3; + wire decodedInsts_2_ror = _GEN_7 == 17'h0c2b3; + wire decodedInsts_2_orcb = _GEN_8 == 22'h0a1e93; + wire decodedInsts_2_rev8 = _GEN_8 == 22'h1a6293; + wire decodedInsts_2_zexth = _GEN_8 == 22'h020233; + wire decodedInsts_2_rori = _GEN_7 == 17'h0c293; + wire [19:0] _decodedInsts_d_imm12_T_13 = {20 {io_inst_3_bits_inst[31]}}; + wire decodedInsts_3_lui = io_inst_3_bits_inst[6:0] == 7'h37; + wire decodedInsts_3_auipc = io_inst_3_bits_inst[6:0] == 7'h17; + wire decodedInsts_3_jal = io_inst_3_bits_inst[6:0] == 7'h6f; + wire [9:0] _GEN_9 = {io_inst_3_bits_inst[14:12], io_inst_3_bits_inst[6:0]}; + wire decodedInsts_3_jalr = _GEN_9 == 10'h067; + wire decodedInsts_3_beq = _GEN_9 == 10'h063; + wire decodedInsts_3_bne = _GEN_9 == 10'h0e3; + wire decodedInsts_3_blt = _GEN_9 == 10'h263; + wire decodedInsts_3_bge = _GEN_9 == 10'h2e3; + wire decodedInsts_3_bltu = _GEN_9 == 10'h363; + wire decodedInsts_3_bgeu = _GEN_9 == 10'h3e3; + wire decodedInsts_3_lb = _GEN_9 == 10'h003; + wire decodedInsts_3_lh = _GEN_9 == 10'h083; + wire decodedInsts_3_lw = _GEN_9 == 10'h103; + wire decodedInsts_3_lbu = _GEN_9 == 10'h203; + wire decodedInsts_3_lhu = _GEN_9 == 10'h283; + wire decodedInsts_3_sb = _GEN_9 == 10'h023; + wire decodedInsts_3_sh = _GEN_9 == 10'h0a3; + wire decodedInsts_3_sw = _GEN_9 == 10'h123; + wire decodedInsts_3_addi = _GEN_9 == 10'h013; + wire decodedInsts_3_slti = _GEN_9 == 10'h113; + wire decodedInsts_3_sltiu = _GEN_9 == 10'h193; + wire decodedInsts_3_xori = _GEN_9 == 10'h213; + wire decodedInsts_3_ori = _GEN_9 == 10'h313; + wire decodedInsts_3_andi = _GEN_9 == 10'h393; + wire [16:0] _GEN_10 = {io_inst_3_bits_inst[31:25], io_inst_3_bits_inst[14:12], io_inst_3_bits_inst[6:0]}; + wire decodedInsts_3_slli = _GEN_10 == 17'h00093; + wire decodedInsts_3_srli = _GEN_10 == 17'h00293; + wire decodedInsts_3_srai = _GEN_10 == 17'h08293; + wire decodedInsts_3_add = _GEN_10 == 17'h00033; + wire decodedInsts_3_sub = _GEN_10 == 17'h08033; + wire decodedInsts_3_slt = _GEN_10 == 17'h00133; + wire decodedInsts_3_sltu = _GEN_10 == 17'h001b3; + wire decodedInsts_3_xor = _GEN_10 == 17'h00233; + wire decodedInsts_3_or = _GEN_10 == 17'h00333; + wire decodedInsts_3_and = _GEN_10 == 17'h003b3; + wire decodedInsts_3_sll = _GEN_10 == 17'h000b3; + wire decodedInsts_3_srl = _GEN_10 == 17'h002b3; + wire decodedInsts_3_sra = _GEN_10 == 17'h082b3; + wire decodedInsts_3_mul = _GEN_10 == 17'h00433; + wire decodedInsts_3_mulh = _GEN_10 == 17'h004b3; + wire decodedInsts_3_mulhsu = _GEN_10 == 17'h00533; + wire decodedInsts_3_mulhu = _GEN_10 == 17'h005b3; + wire decodedInsts_3_andn = _GEN_10 == 17'h083b3; + wire decodedInsts_3_orn = _GEN_10 == 17'h08333; + wire decodedInsts_3_xnor = _GEN_10 == 17'h08233; + wire [21:0] _GEN_11 = {io_inst_3_bits_inst[31:20], io_inst_3_bits_inst[14:12], io_inst_3_bits_inst[6:0]}; + wire decodedInsts_3_clz = _GEN_11 == 22'h180093; + wire decodedInsts_3_ctz = _GEN_11 == 22'h180493; + wire decodedInsts_3_cpop = _GEN_11 == 22'h180893; + wire decodedInsts_3_max = _GEN_10 == 17'h01733; + wire decodedInsts_3_maxu = _GEN_10 == 17'h017b3; + wire decodedInsts_3_min = _GEN_10 == 17'h01633; + wire decodedInsts_3_minu = _GEN_10 == 17'h016b3; + wire decodedInsts_3_sextb = _GEN_11 == 22'h181093; + wire decodedInsts_3_sexth = _GEN_11 == 22'h181493; + wire decodedInsts_3_rol = _GEN_10 == 17'h0c0b3; + wire decodedInsts_3_ror = _GEN_10 == 17'h0c2b3; + wire decodedInsts_3_orcb = _GEN_11 == 22'h0a1e93; + wire decodedInsts_3_rev8 = _GEN_11 == 22'h1a6293; + wire decodedInsts_3_zexth = _GEN_11 == 22'h020233; + wire decodedInsts_3_rori = _GEN_10 == 17'h0c293; + wire _bru_defaultSel_T = decodedInsts_0_jal | decodedInsts_0_jalr; + wire _slot0Interlock_T_36 = decodedInsts_0_fencei | decodedInsts_0_ebreak; + wire isJump_0 = ((((((_bru_defaultSel_T | decodedInsts_0_ecall) | decodedInsts_0_mpause) | decodedInsts_0_mret) | _slot0Interlock_T_36) | decodedInsts_0_wfi) | decodedInsts_0_flushat) | decodedInsts_0_flushall; + wire isJump_1 = decodedInsts_1_jal | decodedInsts_1_jalr; + wire isJump_2 = decodedInsts_2_jal | decodedInsts_2_jalr; + wire jumped_2 = isJump_0 | isJump_1; + wire _io_rs2Read_0_valid_T_1 = decodedInsts_0_beq | decodedInsts_0_bne; + wire isBranch_0 = (((_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt) | decodedInsts_0_bge) | decodedInsts_0_bltu) | decodedInsts_0_bgeu; + wire _io_rs2Read_1_valid_T_1 = decodedInsts_1_beq | decodedInsts_1_bne; + wire isBranch_1 = (((_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu; + wire _io_rs2Read_2_valid_T_1 = decodedInsts_2_beq | decodedInsts_2_bne; + wire isBranch_2 = (((_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu; + wire _io_rs2Read_3_valid_T_1 = decodedInsts_3_beq | decodedInsts_3_bne; + wire branched_2 = isBranch_0 | isBranch_1; + wire _io_rs2Read_0_valid_T_25 = decodedInsts_0_sb | decodedInsts_0_sh; + wire _writesFloatRd_T = decodedInsts_floatValid & decodedInsts_float_scalar_rd; + wire _io_rs2Read_1_valid_T_25 = decodedInsts_1_sb | decodedInsts_1_sh; + wire _io_rs2Read_2_valid_T_25 = decodedInsts_2_sb | decodedInsts_2_sh; + wire _io_rs2Read_3_valid_T_25 = decodedInsts_3_sb | decodedInsts_3_sh; + wire [31:0] _GEN_12 = {27'h0000000, io_inst_0_bits_inst[11:7]}; + wire [31:0] rdScoreboard_0 = ((~(_io_rs2Read_0_valid_T_25 | decodedInsts_0_sw) & ~((((_io_rs2Read_0_valid_T_1 | decodedInsts_0_blt) | decodedInsts_0_bge) | decodedInsts_0_bltu) | decodedInsts_0_bgeu)) | _writesFloatRd_T ? 32'h00000001 << _GEN_12 : 32'h00000000); + wire [31:0] rdScoreboard_1 = ((((((_io_rs2Read_1_valid_T_25 | decodedInsts_1_sw) | _io_rs2Read_1_valid_T_1) | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu ? 32'h00000000 : 32'h00000001 << io_inst_1_bits_inst[11:7]); + wire [31:0] rdScoreboard_2 = ((((((_io_rs2Read_2_valid_T_25 | decodedInsts_2_sw) | _io_rs2Read_2_valid_T_1) | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu ? 32'h00000000 : 32'h00000001 << io_inst_2_bits_inst[11:7]); + wire [31:0] scoreboardScan_2 = rdScoreboard_0 | rdScoreboard_1; + wire [31:0] scoreboardScan_3 = scoreboardScan_2 | rdScoreboard_2; + wire [31:0] comb_1 = rdScoreboard_0 | io_scoreboard_comb; + wire [31:0] comb_2 = scoreboardScan_2 | io_scoreboard_comb; + wire [31:0] comb_3 = scoreboardScan_3 | io_scoreboard_comb; + wire _rdMark_valid_T_5 = decodedInsts_0_lb | decodedInsts_0_lh; + wire _rdMark_flt_valid_T_4 = decodedInsts_float_bits_opcode == 3'h0; + wire _io_float_valid_T_3 = decodedInsts_float_bits_opcode == 3'h1; + wire _rdMark_valid_T_28 = decodedInsts_1_lb | decodedInsts_1_lh; + wire _rdMark_valid_T_49 = decodedInsts_2_lb | decodedInsts_2_lh; + wire _rdMark_valid_T_70 = decodedInsts_3_lb | decodedInsts_3_lh; + wire [31:0] _GEN_13 = {27'h0000000, io_inst_0_bits_inst[24:20]}; + wire [31:0] _GEN_14 = {27'h0000000, io_inst_1_bits_inst[19:15]}; + wire [31:0] _GEN_15 = {27'h0000000, io_inst_1_bits_inst[24:20]}; + wire [31:0] _GEN_16 = {27'h0000000, io_inst_2_bits_inst[19:15]}; + wire [31:0] _GEN_17 = {27'h0000000, io_inst_2_bits_inst[24:20]}; + wire [31:0] _GEN_18 = {27'h0000000, io_inst_3_bits_inst[19:15]}; + wire [31:0] _GEN_19 = {27'h0000000, io_inst_3_bits_inst[24:20]}; + wire _io_rs2Read_0_valid_T_6 = decodedInsts_0_add | decodedInsts_0_sub; + wire _io_rs2Set_0_valid_T_6 = decodedInsts_0_addi | decodedInsts_0_slti; + wire _io_rs2Set_0_valid_T_16 = decodedInsts_0_clz | decodedInsts_0_ctz; + wire _io_rs2Read_0_valid_T_19 = decodedInsts_0_min | decodedInsts_0_minu; + wire _io_rs2Set_0_valid_T_1 = decodedInsts_0_csrrw | decodedInsts_0_csrrs; + wire _io_rs2Read_0_valid_T_34 = decodedInsts_0_mul | decodedInsts_0_mulh; + wire _io_rs2Read_0_valid_T_38 = decodedInsts_0_div | decodedInsts_0_divu; + wire _io_rs1Read_0_valid_T_56 = decodedInsts_floatValid & decodedInsts_float_scalar_rs1; + wire _io_rs2Read_1_valid_T_6 = decodedInsts_1_add | decodedInsts_1_sub; + wire _io_rs2Set_1_valid_T_6 = decodedInsts_1_addi | decodedInsts_1_slti; + wire _io_rs2Set_1_valid_T_16 = decodedInsts_1_clz | decodedInsts_1_ctz; + wire _io_rs2Read_1_valid_T_19 = decodedInsts_1_min | decodedInsts_1_minu; + wire _io_rs2Read_1_valid_T_34 = decodedInsts_1_mul | decodedInsts_1_mulh; + wire _io_rs2Read_2_valid_T_6 = decodedInsts_2_add | decodedInsts_2_sub; + wire _io_rs2Set_2_valid_T_6 = decodedInsts_2_addi | decodedInsts_2_slti; + wire _io_rs2Set_2_valid_T_16 = decodedInsts_2_clz | decodedInsts_2_ctz; + wire _io_rs2Read_2_valid_T_19 = decodedInsts_2_min | decodedInsts_2_minu; + wire _io_rs2Read_2_valid_T_34 = decodedInsts_2_mul | decodedInsts_2_mulh; + wire _io_rs2Read_3_valid_T_6 = decodedInsts_3_add | decodedInsts_3_sub; + wire _io_rs2Set_3_valid_T_6 = decodedInsts_3_addi | decodedInsts_3_slti; + wire _io_rs2Set_3_valid_T_16 = decodedInsts_3_clz | decodedInsts_3_ctz; + wire _io_rs2Read_3_valid_T_19 = decodedInsts_3_min | decodedInsts_3_minu; + wire _io_rs2Read_3_valid_T_34 = decodedInsts_3_mul | decodedInsts_3_mulh; + wire isLsu_0 = ((((((((_rdMark_valid_T_5 | decodedInsts_0_lw) | decodedInsts_0_lbu) | decodedInsts_0_lhu) | _io_rs2Read_0_valid_T_25) | decodedInsts_0_sw) | decodedInsts_0_flushat) | decodedInsts_0_flushall) | (decodedInsts_floatValid & _rdMark_flt_valid_T_4)) | (decodedInsts_floatValid & _io_float_valid_T_3); + wire [3:0] _isLsuCount_T_1 = {3'h0, isLsu_0} + {3'h0, ((((_rdMark_valid_T_28 | decodedInsts_1_lw) | decodedInsts_1_lbu) | decodedInsts_1_lhu) | _io_rs2Read_1_valid_T_25) | decodedInsts_1_sw}; + wire [3:0] _GEN_20 = {1'h0, io_lsuQueueCapacity}; + wire _alu_T_158 = (decodedInsts_0_auipc | decodedInsts_0_addi) | decodedInsts_0_add; + wire _alu_T_160 = decodedInsts_0_slti | decodedInsts_0_slt; + wire _alu_T_161 = decodedInsts_0_sltiu | decodedInsts_0_sltu; + wire _alu_T_162 = decodedInsts_0_xori | decodedInsts_0_xor; + wire _alu_T_163 = decodedInsts_0_ori | decodedInsts_0_or; + wire _alu_T_164 = decodedInsts_0_andi | decodedInsts_0_and; + wire _alu_T_165 = decodedInsts_0_slli | decodedInsts_0_sll; + wire _alu_T_166 = decodedInsts_0_srli | decodedInsts_0_srl; + wire _alu_T_167 = decodedInsts_0_srai | decodedInsts_0_sra; + wire io_alu_0_valid_0 = tryDispatch & ((((((((((((((((((((((((((((_alu_T_158 | decodedInsts_0_sub) | _alu_T_160) | _alu_T_161) | _alu_T_162) | _alu_T_163) | _alu_T_164) | _alu_T_165) | _alu_T_166) | _alu_T_167) | decodedInsts_0_lui) | decodedInsts_0_andn) | decodedInsts_0_orn) | decodedInsts_0_xnor) | decodedInsts_0_clz) | decodedInsts_0_ctz) | decodedInsts_0_cpop) | decodedInsts_0_max) | decodedInsts_0_maxu) | decodedInsts_0_min) | decodedInsts_0_minu) | decodedInsts_0_sextb) | decodedInsts_0_sexth) | decodedInsts_0_rol) | decodedInsts_0_ror) | decodedInsts_0_orcb) | decodedInsts_0_rev8) | decodedInsts_0_zexth) | decodedInsts_0_rori); + wire [3:0] _bru_T_67 = (((((((((({3'h0, decodedInsts_0_jalr} | {2'h0, decodedInsts_0_beq, 1'h0}) | (decodedInsts_0_bne ? 4'h3 : 4'h0)) | {1'h0, decodedInsts_0_blt, 2'h0}) | (decodedInsts_0_bge ? 4'h5 : 4'h0)) | (decodedInsts_0_bltu ? 4'h6 : 4'h0)) | (decodedInsts_0_bgeu ? 4'h7 : 4'h0)) | {decodedInsts_0_ebreak, 3'h0}) | (decodedInsts_0_ecall ? 4'h9 : 4'h0)) | (decodedInsts_0_mpause ? 4'ha : 4'h0)) | (decodedInsts_0_mret ? 4'hb : 4'h0)) | (decodedInsts_0_wfi ? 4'hc : 4'h0); + wire [31:0] _bru_target_T_2 = io_inst_0_bits_addr + {{12 {io_inst_0_bits_inst[31]}}, (io_inst_0_bits_inst[2] ? {io_inst_0_bits_inst[19:12], io_inst_0_bits_inst[20], io_inst_0_bits_inst[30:21]} : {{8 {io_inst_0_bits_inst[31]}}, io_inst_0_bits_inst[7], io_inst_0_bits_inst[30:25], io_inst_0_bits_inst[11:8]}), 1'h0}; + wire _io_bru_0_valid_T = tryDispatch & ((((((((((((decodedInsts_0_jal | decodedInsts_0_jalr) | decodedInsts_0_beq) | decodedInsts_0_bne) | decodedInsts_0_blt) | decodedInsts_0_bge) | decodedInsts_0_bltu) | decodedInsts_0_bgeu) | decodedInsts_0_ebreak) | decodedInsts_0_ecall) | decodedInsts_0_mpause) | decodedInsts_0_mret) | decodedInsts_0_wfi); + wire jalFault = ((_io_bru_0_valid_T & (_bru_T_67 == 4'h0)) & |_bru_target_T_2[1:0]) & ~io_branchTaken; + wire jalrFault = ((_io_bru_0_valid_T & (_bru_T_67 == 4'h1)) & io_jalrTarget_0_data[1]) & ~io_branchTaken; + wire bxxFault = ((_io_bru_0_valid_T & |{_bru_T_67 == 4'h7, _bru_T_67 == 4'h6, _bru_T_67 == 4'h5, _bru_T_67 == 4'h4, _bru_T_67 == 4'h3, _bru_T_67 == 4'h2}) & |_bru_target_T_2[1:0]) & ~io_branchTaken; + wire io_bru_0_valid_0 = _io_bru_0_valid_T & ~((jalFault | jalrFault) | bxxFault); + wire io_mlu_0_valid_0 = tryDispatch & (((decodedInsts_0_mul | decodedInsts_0_mulh) | decodedInsts_0_mulhsu) | decodedInsts_0_mulhu); + wire io_dvu_0_valid_0 = tryDispatch & (((decodedInsts_0_div | decodedInsts_0_divu) | decodedInsts_0_rem) | decodedInsts_0_remu); + wire _lsu_T_85 = (decodedInsts_floatValid & _rdMark_flt_valid_T_4) | (decodedInsts_floatValid & _io_float_valid_T_3); + wire io_lsu_0_valid_0 = tryDispatch & ((((((((((((decodedInsts_0_lb | decodedInsts_0_lh) | decodedInsts_0_lw) | decodedInsts_0_lbu) | decodedInsts_0_lhu) | decodedInsts_0_sb) | decodedInsts_0_sh) | decodedInsts_0_sw) | decodedInsts_0_wfi) | decodedInsts_0_fencei) | decodedInsts_0_flushat) | decodedInsts_0_flushall) | _lsu_T_85); + wire csr_valid = (decodedInsts_0_csrrw | decodedInsts_0_csrrs) | decodedInsts_0_csrrc; + wire csr_address_valid = (((((((((((((((((((((((((((((((((((((((((((((((((io_inst_0_bits_inst[31:20] == 12'h000) | (io_inst_0_bits_inst[31:20] == 12'h001)) | (io_inst_0_bits_inst[31:20] == 12'h002)) | (io_inst_0_bits_inst[31:20] == 12'h003)) | (io_inst_0_bits_inst[31:20] == 12'h008)) | (io_inst_0_bits_inst[31:20] == 12'h009)) | (io_inst_0_bits_inst[31:20] == 12'h00a)) | (io_inst_0_bits_inst[31:20] == 12'h300)) | (io_inst_0_bits_inst[31:20] == 12'h301)) | (io_inst_0_bits_inst[31:20] == 12'h304)) | (io_inst_0_bits_inst[31:20] == 12'h305)) | (io_inst_0_bits_inst[31:20] == 12'h340)) | (io_inst_0_bits_inst[31:20] == 12'h341)) | (io_inst_0_bits_inst[31:20] == 12'h342)) | (io_inst_0_bits_inst[31:20] == 12'h343)) | (io_inst_0_bits_inst[31:20] == 12'h7a0)) | (io_inst_0_bits_inst[31:20] == 12'h7a1)) | (io_inst_0_bits_inst[31:20] == 12'h7a2)) | (io_inst_0_bits_inst[31:20] == 12'h7a4)) | (io_inst_0_bits_inst[31:20] == 12'h7b0)) | (io_inst_0_bits_inst[31:20] == 12'h7b1)) | (io_inst_0_bits_inst[31:20] == 12'h7b2)) | (io_inst_0_bits_inst[31:20] == 12'h7b3)) | (io_inst_0_bits_inst[31:20] == 12'h7c0)) | (io_inst_0_bits_inst[31:20] == 12'h7c1)) | (io_inst_0_bits_inst[31:20] == 12'h7c2)) | (io_inst_0_bits_inst[31:20] == 12'h7c3)) | (io_inst_0_bits_inst[31:20] == 12'h7c4)) | (io_inst_0_bits_inst[31:20] == 12'h7c5)) | (io_inst_0_bits_inst[31:20] == 12'h7c6)) | (io_inst_0_bits_inst[31:20] == 12'h7c7)) | (io_inst_0_bits_inst[31:20] == 12'h7e0)) | (io_inst_0_bits_inst[31:20] == 12'h7e1)) | (io_inst_0_bits_inst[31:20] == 12'hb00)) | (io_inst_0_bits_inst[31:20] == 12'hb02)) | (io_inst_0_bits_inst[31:20] == 12'hb80)) | (io_inst_0_bits_inst[31:20] == 12'hb82)) | (io_inst_0_bits_inst[31:20] == 12'hc20)) | (io_inst_0_bits_inst[31:20] == 12'hc21)) | (io_inst_0_bits_inst[31:20] == 12'hc22)) | (io_inst_0_bits_inst[31:20] == 12'hf11)) | (io_inst_0_bits_inst[31:20] == 12'hf12)) | (io_inst_0_bits_inst[31:20] == 12'hf13)) | (io_inst_0_bits_inst[31:20] == 12'hf14)) | (io_inst_0_bits_inst[31:20] == 12'hfc0)) | (io_inst_0_bits_inst[31:20] == 12'hfc4)) | (io_inst_0_bits_inst[31:20] == 12'hfc8)) | (io_inst_0_bits_inst[31:20] == 12'hfcc)) | (io_inst_0_bits_inst[31:20] == 12'hfd0)) | (io_inst_0_bits_inst[31:20] == 12'hfd4); + wire io_csr_valid_0 = ((tryDispatch & csr_valid) & csr_address_valid) & io_float_ready; + wire io_float_valid_0 = (tryDispatch & decodedInsts_floatValid) & ~((decodedInsts_floatValid & _rdMark_flt_valid_T_4) | (decodedInsts_floatValid & _io_float_valid_T_3)); + wire dispatched_3 = io_dvu_0_ready & io_dvu_0_valid_0; + wire dispatched_4 = io_lsu_0_ready & io_lsu_0_valid_0; + wire dispatched_8 = io_float_ready & io_float_valid_0; + wire tryDispatch_1 = (((((((((((lastReady_1 & ~io_halted) & ~io_interlock) & io_inst_1_valid) & ~isJump_0) & ({(((((((decodedInsts_1_jalr | _rdMark_valid_T_28) | decodedInsts_1_lw) | decodedInsts_1_lbu) | decodedInsts_1_lhu) | _io_rs2Read_1_valid_T_25) | decodedInsts_1_sw ? 32'h00000001 << _GEN_14 : 32'h00000000) | (_io_rs2Read_1_valid_T_25 | decodedInsts_1_sw ? 32'h00000001 << _GEN_15 : 32'h00000000)) & (rdScoreboard_0 | io_scoreboard_regd), ((((((((((((((((((((((((((((((((((((((((((_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu) | _io_rs2Read_1_valid_T_6) | decodedInsts_1_slt) | decodedInsts_1_sltu) | decodedInsts_1_xor) | decodedInsts_1_or) | decodedInsts_1_and) | decodedInsts_1_xnor) | decodedInsts_1_orn) | decodedInsts_1_andn) | decodedInsts_1_sll) | decodedInsts_1_srl) | decodedInsts_1_sra) | _io_rs2Set_1_valid_T_6) | decodedInsts_1_sltiu) | decodedInsts_1_xori) | decodedInsts_1_ori) | decodedInsts_1_andi) | decodedInsts_1_slli) | decodedInsts_1_srli) | decodedInsts_1_srai) | decodedInsts_1_rori) | _io_rs2Set_1_valid_T_16) | decodedInsts_1_cpop) | decodedInsts_1_sextb) | decodedInsts_1_sexth) | decodedInsts_1_zexth) | decodedInsts_1_orcb) | decodedInsts_1_rev8) | _io_rs2Read_1_valid_T_19) | decodedInsts_1_max) | decodedInsts_1_maxu) | decodedInsts_1_rol) | decodedInsts_1_ror) | _io_rs2Read_1_valid_T_34) | decodedInsts_1_mulhsu) | decodedInsts_1_mulhu) | decodedInsts_1_jalr ? 32'h00000001 << _GEN_14 : 32'h00000000) | ((((((((((((((((((((((((((_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu) | _io_rs2Read_1_valid_T_6) | decodedInsts_1_slt) | decodedInsts_1_sltu) | decodedInsts_1_xor) | decodedInsts_1_or) | decodedInsts_1_and) | decodedInsts_1_xnor) | decodedInsts_1_orn) | decodedInsts_1_andn) | decodedInsts_1_sll) | decodedInsts_1_srl) | decodedInsts_1_sra) | _io_rs2Read_1_valid_T_19) | decodedInsts_1_max) | decodedInsts_1_maxu) | decodedInsts_1_rol) | decodedInsts_1_ror) | _io_rs2Read_1_valid_T_25) | decodedInsts_1_sw) | _io_rs2Read_1_valid_T_34) | decodedInsts_1_mulhsu) | decodedInsts_1_mulhu ? 32'h00000001 << _GEN_15 : 32'h00000000)) & comb_1} == 64'h0000000000000000)) & ((rdScoreboard_1 & comb_1) == 32'h00000000)) & ~isBranch_0) & ~((((((_slot0Interlock_T_36 | decodedInsts_0_wfi) | decodedInsts_0_mpause) | decodedInsts_0_flushat) | decodedInsts_0_flushall) | _io_rs2Set_0_valid_T_1) | decodedInsts_0_csrrc)) & ({3'h0, isLsu_0} < _GEN_20)) & |{decodedInsts_1_lui, decodedInsts_1_auipc, decodedInsts_1_jal, decodedInsts_1_jalr, decodedInsts_1_beq, decodedInsts_1_bne, decodedInsts_1_blt, decodedInsts_1_bge, decodedInsts_1_bltu, decodedInsts_1_bgeu, decodedInsts_1_lb, decodedInsts_1_lh, decodedInsts_1_lw, decodedInsts_1_lbu, decodedInsts_1_lhu, decodedInsts_1_sb, decodedInsts_1_sh, decodedInsts_1_sw, decodedInsts_1_addi, decodedInsts_1_slti, decodedInsts_1_sltiu, decodedInsts_1_xori, decodedInsts_1_ori, decodedInsts_1_andi, decodedInsts_1_add, decodedInsts_1_sub, decodedInsts_1_slt, decodedInsts_1_sltu, decodedInsts_1_xor, decodedInsts_1_or, decodedInsts_1_and, decodedInsts_1_xnor, decodedInsts_1_orn, decodedInsts_1_andn, decodedInsts_1_slli, decodedInsts_1_srli, decodedInsts_1_srai, decodedInsts_1_sll, decodedInsts_1_srl, decodedInsts_1_sra, decodedInsts_1_mul, decodedInsts_1_mulh, decodedInsts_1_mulhsu, decodedInsts_1_mulhu, decodedInsts_1_clz, decodedInsts_1_ctz, decodedInsts_1_cpop, decodedInsts_1_min, decodedInsts_1_minu, decodedInsts_1_max, decodedInsts_1_maxu, decodedInsts_1_sextb, decodedInsts_1_sexth, decodedInsts_1_zexth, decodedInsts_1_rol, decodedInsts_1_ror, decodedInsts_1_orcb, decodedInsts_1_rev8, decodedInsts_1_rori}) & |io_retirement_buffer_nSpace[4:1]) & ~io_retirement_buffer_trap_pending; + wire _alu_T_376 = (decodedInsts_1_auipc | decodedInsts_1_addi) | decodedInsts_1_add; + wire _alu_T_378 = decodedInsts_1_slti | decodedInsts_1_slt; + wire _alu_T_379 = decodedInsts_1_sltiu | decodedInsts_1_sltu; + wire _alu_T_380 = decodedInsts_1_xori | decodedInsts_1_xor; + wire _alu_T_381 = decodedInsts_1_ori | decodedInsts_1_or; + wire _alu_T_382 = decodedInsts_1_andi | decodedInsts_1_and; + wire _alu_T_383 = decodedInsts_1_slli | decodedInsts_1_sll; + wire _alu_T_384 = decodedInsts_1_srli | decodedInsts_1_srl; + wire _alu_T_385 = decodedInsts_1_srai | decodedInsts_1_sra; + wire io_alu_1_valid_0 = tryDispatch_1 & ((((((((((((((((((((((((((((_alu_T_376 | decodedInsts_1_sub) | _alu_T_378) | _alu_T_379) | _alu_T_380) | _alu_T_381) | _alu_T_382) | _alu_T_383) | _alu_T_384) | _alu_T_385) | decodedInsts_1_lui) | decodedInsts_1_andn) | decodedInsts_1_orn) | decodedInsts_1_xnor) | decodedInsts_1_clz) | decodedInsts_1_ctz) | decodedInsts_1_cpop) | decodedInsts_1_max) | decodedInsts_1_maxu) | decodedInsts_1_min) | decodedInsts_1_minu) | decodedInsts_1_sextb) | decodedInsts_1_sexth) | decodedInsts_1_rol) | decodedInsts_1_ror) | decodedInsts_1_orcb) | decodedInsts_1_rev8) | decodedInsts_1_zexth) | decodedInsts_1_rori); + wire [3:0] _bru_T_163 = ((((({3'h0, decodedInsts_1_jalr} | {2'h0, decodedInsts_1_beq, 1'h0}) | (decodedInsts_1_bne ? 4'h3 : 4'h0)) | {1'h0, decodedInsts_1_blt, 2'h0}) | (decodedInsts_1_bge ? 4'h5 : 4'h0)) | (decodedInsts_1_bltu ? 4'h6 : 4'h0)) | (decodedInsts_1_bgeu ? 4'h7 : 4'h0); + wire [31:0] _bru_target_T_5 = io_inst_1_bits_addr + {{12 {io_inst_1_bits_inst[31]}}, (io_inst_1_bits_inst[2] ? {io_inst_1_bits_inst[19:12], io_inst_1_bits_inst[20], io_inst_1_bits_inst[30:21]} : {{8 {io_inst_1_bits_inst[31]}}, io_inst_1_bits_inst[7], io_inst_1_bits_inst[30:25], io_inst_1_bits_inst[11:8]}), 1'h0}; + wire _io_bru_1_valid_T = tryDispatch_1 & (((((((decodedInsts_1_jal | decodedInsts_1_jalr) | decodedInsts_1_beq) | decodedInsts_1_bne) | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu); + wire jalFault_1 = ((_io_bru_1_valid_T & (_bru_T_163[2:0] == 3'h0)) & |_bru_target_T_5[1:0]) & ~io_branchTaken; + wire jalrFault_1 = ((_io_bru_1_valid_T & (_bru_T_163[2:0] == 3'h1)) & io_jalrTarget_1_data[1]) & ~io_branchTaken; + wire bxxFault_1 = ((_io_bru_1_valid_T & |{&_bru_T_163[2:0], _bru_T_163[2:0] == 3'h6, _bru_T_163[2:0] == 3'h5, _bru_T_163[2:0] == 3'h4, _bru_T_163[2:0] == 3'h3, _bru_T_163[2:0] == 3'h2}) & |_bru_target_T_5[1:0]) & ~io_branchTaken; + wire io_bru_1_valid_0 = _io_bru_1_valid_T & ~((jalFault_1 | jalrFault_1) | bxxFault_1); + wire io_mlu_1_valid_0 = tryDispatch_1 & (((decodedInsts_1_mul | decodedInsts_1_mulh) | decodedInsts_1_mulhsu) | decodedInsts_1_mulhu); + wire io_lsu_1_valid_0 = tryDispatch_1 & (((((((decodedInsts_1_lb | decodedInsts_1_lh) | decodedInsts_1_lw) | decodedInsts_1_lbu) | decodedInsts_1_lhu) | decodedInsts_1_sb) | decodedInsts_1_sh) | decodedInsts_1_sw); + wire dispatched_2_1 = io_mlu_1_ready & io_mlu_1_valid_0; + wire dispatched_4_1 = io_lsu_1_ready & io_lsu_1_valid_0; + wire lastReady_2 = ((io_alu_1_valid_0 | io_bru_1_valid_0) | dispatched_2_1) | dispatched_4_1; + wire tryDispatch_2 = (((((((((((lastReady_2 & ~io_halted) & ~io_interlock) & io_inst_2_valid) & ~jumped_2) & ({(((((((decodedInsts_2_jalr | _rdMark_valid_T_49) | decodedInsts_2_lw) | decodedInsts_2_lbu) | decodedInsts_2_lhu) | _io_rs2Read_2_valid_T_25) | decodedInsts_2_sw ? 32'h00000001 << _GEN_16 : 32'h00000000) | (_io_rs2Read_2_valid_T_25 | decodedInsts_2_sw ? 32'h00000001 << _GEN_17 : 32'h00000000)) & (scoreboardScan_2 | io_scoreboard_regd), ((((((((((((((((((((((((((((((((((((((((((_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu) | _io_rs2Read_2_valid_T_6) | decodedInsts_2_slt) | decodedInsts_2_sltu) | decodedInsts_2_xor) | decodedInsts_2_or) | decodedInsts_2_and) | decodedInsts_2_xnor) | decodedInsts_2_orn) | decodedInsts_2_andn) | decodedInsts_2_sll) | decodedInsts_2_srl) | decodedInsts_2_sra) | _io_rs2Set_2_valid_T_6) | decodedInsts_2_sltiu) | decodedInsts_2_xori) | decodedInsts_2_ori) | decodedInsts_2_andi) | decodedInsts_2_slli) | decodedInsts_2_srli) | decodedInsts_2_srai) | decodedInsts_2_rori) | _io_rs2Set_2_valid_T_16) | decodedInsts_2_cpop) | decodedInsts_2_sextb) | decodedInsts_2_sexth) | decodedInsts_2_zexth) | decodedInsts_2_orcb) | decodedInsts_2_rev8) | _io_rs2Read_2_valid_T_19) | decodedInsts_2_max) | decodedInsts_2_maxu) | decodedInsts_2_rol) | decodedInsts_2_ror) | _io_rs2Read_2_valid_T_34) | decodedInsts_2_mulhsu) | decodedInsts_2_mulhu) | decodedInsts_2_jalr ? 32'h00000001 << _GEN_16 : 32'h00000000) | ((((((((((((((((((((((((((_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu) | _io_rs2Read_2_valid_T_6) | decodedInsts_2_slt) | decodedInsts_2_sltu) | decodedInsts_2_xor) | decodedInsts_2_or) | decodedInsts_2_and) | decodedInsts_2_xnor) | decodedInsts_2_orn) | decodedInsts_2_andn) | decodedInsts_2_sll) | decodedInsts_2_srl) | decodedInsts_2_sra) | _io_rs2Read_2_valid_T_19) | decodedInsts_2_max) | decodedInsts_2_maxu) | decodedInsts_2_rol) | decodedInsts_2_ror) | _io_rs2Read_2_valid_T_25) | decodedInsts_2_sw) | _io_rs2Read_2_valid_T_34) | decodedInsts_2_mulhsu) | decodedInsts_2_mulhu ? 32'h00000001 << _GEN_17 : 32'h00000000)) & comb_2} == 64'h0000000000000000)) & ((rdScoreboard_2 & comb_2) == 32'h00000000)) & ~branched_2) & ~((((((_slot0Interlock_T_36 | decodedInsts_0_wfi) | decodedInsts_0_mpause) | decodedInsts_0_flushat) | decodedInsts_0_flushall) | _io_rs2Set_0_valid_T_1) | decodedInsts_0_csrrc)) & (_isLsuCount_T_1 < _GEN_20)) & |{decodedInsts_2_lui, decodedInsts_2_auipc, decodedInsts_2_jal, decodedInsts_2_jalr, decodedInsts_2_beq, decodedInsts_2_bne, decodedInsts_2_blt, decodedInsts_2_bge, decodedInsts_2_bltu, decodedInsts_2_bgeu, decodedInsts_2_lb, decodedInsts_2_lh, decodedInsts_2_lw, decodedInsts_2_lbu, decodedInsts_2_lhu, decodedInsts_2_sb, decodedInsts_2_sh, decodedInsts_2_sw, decodedInsts_2_addi, decodedInsts_2_slti, decodedInsts_2_sltiu, decodedInsts_2_xori, decodedInsts_2_ori, decodedInsts_2_andi, decodedInsts_2_add, decodedInsts_2_sub, decodedInsts_2_slt, decodedInsts_2_sltu, decodedInsts_2_xor, decodedInsts_2_or, decodedInsts_2_and, decodedInsts_2_xnor, decodedInsts_2_orn, decodedInsts_2_andn, decodedInsts_2_slli, decodedInsts_2_srli, decodedInsts_2_srai, decodedInsts_2_sll, decodedInsts_2_srl, decodedInsts_2_sra, decodedInsts_2_mul, decodedInsts_2_mulh, decodedInsts_2_mulhsu, decodedInsts_2_mulhu, decodedInsts_2_clz, decodedInsts_2_ctz, decodedInsts_2_cpop, decodedInsts_2_min, decodedInsts_2_minu, decodedInsts_2_max, decodedInsts_2_maxu, decodedInsts_2_sextb, decodedInsts_2_sexth, decodedInsts_2_zexth, decodedInsts_2_rol, decodedInsts_2_ror, decodedInsts_2_orcb, decodedInsts_2_rev8, decodedInsts_2_rori}) & (io_retirement_buffer_nSpace > 5'h02)) & ~io_retirement_buffer_trap_pending; + wire _alu_T_594 = (decodedInsts_2_auipc | decodedInsts_2_addi) | decodedInsts_2_add; + wire _alu_T_596 = decodedInsts_2_slti | decodedInsts_2_slt; + wire _alu_T_597 = decodedInsts_2_sltiu | decodedInsts_2_sltu; + wire _alu_T_598 = decodedInsts_2_xori | decodedInsts_2_xor; + wire _alu_T_599 = decodedInsts_2_ori | decodedInsts_2_or; + wire _alu_T_600 = decodedInsts_2_andi | decodedInsts_2_and; + wire _alu_T_601 = decodedInsts_2_slli | decodedInsts_2_sll; + wire _alu_T_602 = decodedInsts_2_srli | decodedInsts_2_srl; + wire _alu_T_603 = decodedInsts_2_srai | decodedInsts_2_sra; + wire io_alu_2_valid_0 = tryDispatch_2 & ((((((((((((((((((((((((((((_alu_T_594 | decodedInsts_2_sub) | _alu_T_596) | _alu_T_597) | _alu_T_598) | _alu_T_599) | _alu_T_600) | _alu_T_601) | _alu_T_602) | _alu_T_603) | decodedInsts_2_lui) | decodedInsts_2_andn) | decodedInsts_2_orn) | decodedInsts_2_xnor) | decodedInsts_2_clz) | decodedInsts_2_ctz) | decodedInsts_2_cpop) | decodedInsts_2_max) | decodedInsts_2_maxu) | decodedInsts_2_min) | decodedInsts_2_minu) | decodedInsts_2_sextb) | decodedInsts_2_sexth) | decodedInsts_2_rol) | decodedInsts_2_ror) | decodedInsts_2_orcb) | decodedInsts_2_rev8) | decodedInsts_2_zexth) | decodedInsts_2_rori); + wire [3:0] _bru_T_259 = ((((({3'h0, decodedInsts_2_jalr} | {2'h0, decodedInsts_2_beq, 1'h0}) | (decodedInsts_2_bne ? 4'h3 : 4'h0)) | {1'h0, decodedInsts_2_blt, 2'h0}) | (decodedInsts_2_bge ? 4'h5 : 4'h0)) | (decodedInsts_2_bltu ? 4'h6 : 4'h0)) | (decodedInsts_2_bgeu ? 4'h7 : 4'h0); + wire [31:0] _bru_target_T_8 = io_inst_2_bits_addr + {{12 {io_inst_2_bits_inst[31]}}, (io_inst_2_bits_inst[2] ? {io_inst_2_bits_inst[19:12], io_inst_2_bits_inst[20], io_inst_2_bits_inst[30:21]} : {{8 {io_inst_2_bits_inst[31]}}, io_inst_2_bits_inst[7], io_inst_2_bits_inst[30:25], io_inst_2_bits_inst[11:8]}), 1'h0}; + wire _io_bru_2_valid_T = tryDispatch_2 & (((((((decodedInsts_2_jal | decodedInsts_2_jalr) | decodedInsts_2_beq) | decodedInsts_2_bne) | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu); + wire jalFault_2 = ((_io_bru_2_valid_T & (_bru_T_259[2:0] == 3'h0)) & |_bru_target_T_8[1:0]) & ~io_branchTaken; + wire jalrFault_2 = ((_io_bru_2_valid_T & (_bru_T_259[2:0] == 3'h1)) & io_jalrTarget_2_data[1]) & ~io_branchTaken; + wire bxxFault_2 = ((_io_bru_2_valid_T & |{&_bru_T_259[2:0], _bru_T_259[2:0] == 3'h6, _bru_T_259[2:0] == 3'h5, _bru_T_259[2:0] == 3'h4, _bru_T_259[2:0] == 3'h3, _bru_T_259[2:0] == 3'h2}) & |_bru_target_T_8[1:0]) & ~io_branchTaken; + wire io_bru_2_valid_0 = _io_bru_2_valid_T & ~((jalFault_2 | jalrFault_2) | bxxFault_2); + wire io_mlu_2_valid_0 = tryDispatch_2 & (((decodedInsts_2_mul | decodedInsts_2_mulh) | decodedInsts_2_mulhsu) | decodedInsts_2_mulhu); + wire io_lsu_2_valid_0 = tryDispatch_2 & (((((((decodedInsts_2_lb | decodedInsts_2_lh) | decodedInsts_2_lw) | decodedInsts_2_lbu) | decodedInsts_2_lhu) | decodedInsts_2_sb) | decodedInsts_2_sh) | decodedInsts_2_sw); + wire dispatched_2_2 = io_mlu_2_ready & io_mlu_2_valid_0; + wire dispatched_4_2 = io_lsu_2_ready & io_lsu_2_valid_0; + wire lastReady_3 = ((io_alu_2_valid_0 | io_bru_2_valid_0) | dispatched_2_2) | dispatched_4_2; + wire tryDispatch_3 = (((((((((((lastReady_3 & ~io_halted) & ~io_interlock) & io_inst_3_valid) & ~(jumped_2 | isJump_2)) & ({(((((((decodedInsts_3_jalr | _rdMark_valid_T_70) | decodedInsts_3_lw) | decodedInsts_3_lbu) | decodedInsts_3_lhu) | _io_rs2Read_3_valid_T_25) | decodedInsts_3_sw ? 32'h00000001 << _GEN_18 : 32'h00000000) | (_io_rs2Read_3_valid_T_25 | decodedInsts_3_sw ? 32'h00000001 << _GEN_19 : 32'h00000000)) & (scoreboardScan_3 | io_scoreboard_regd), ((((((((((((((((((((((((((((((((((((((((((_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu) | _io_rs2Read_3_valid_T_6) | decodedInsts_3_slt) | decodedInsts_3_sltu) | decodedInsts_3_xor) | decodedInsts_3_or) | decodedInsts_3_and) | decodedInsts_3_xnor) | decodedInsts_3_orn) | decodedInsts_3_andn) | decodedInsts_3_sll) | decodedInsts_3_srl) | decodedInsts_3_sra) | _io_rs2Set_3_valid_T_6) | decodedInsts_3_sltiu) | decodedInsts_3_xori) | decodedInsts_3_ori) | decodedInsts_3_andi) | decodedInsts_3_slli) | decodedInsts_3_srli) | decodedInsts_3_srai) | decodedInsts_3_rori) | _io_rs2Set_3_valid_T_16) | decodedInsts_3_cpop) | decodedInsts_3_sextb) | decodedInsts_3_sexth) | decodedInsts_3_zexth) | decodedInsts_3_orcb) | decodedInsts_3_rev8) | _io_rs2Read_3_valid_T_19) | decodedInsts_3_max) | decodedInsts_3_maxu) | decodedInsts_3_rol) | decodedInsts_3_ror) | _io_rs2Read_3_valid_T_34) | decodedInsts_3_mulhsu) | decodedInsts_3_mulhu) | decodedInsts_3_jalr ? 32'h00000001 << _GEN_18 : 32'h00000000) | ((((((((((((((((((((((((((_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu) | _io_rs2Read_3_valid_T_6) | decodedInsts_3_slt) | decodedInsts_3_sltu) | decodedInsts_3_xor) | decodedInsts_3_or) | decodedInsts_3_and) | decodedInsts_3_xnor) | decodedInsts_3_orn) | decodedInsts_3_andn) | decodedInsts_3_sll) | decodedInsts_3_srl) | decodedInsts_3_sra) | _io_rs2Read_3_valid_T_19) | decodedInsts_3_max) | decodedInsts_3_maxu) | decodedInsts_3_rol) | decodedInsts_3_ror) | _io_rs2Read_3_valid_T_25) | decodedInsts_3_sw) | _io_rs2Read_3_valid_T_34) | decodedInsts_3_mulhsu) | decodedInsts_3_mulhu ? 32'h00000001 << _GEN_19 : 32'h00000000)) & comb_3} == 64'h0000000000000000)) & ((((((((_io_rs2Read_3_valid_T_25 | decodedInsts_3_sw) | _io_rs2Read_3_valid_T_1) | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu ? 32'h00000000 : 32'h00000001 << io_inst_3_bits_inst[11:7]) & comb_3) == 32'h00000000)) & ~(branched_2 | isBranch_2)) & ~((((((_slot0Interlock_T_36 | decodedInsts_0_wfi) | decodedInsts_0_mpause) | decodedInsts_0_flushat) | decodedInsts_0_flushall) | _io_rs2Set_0_valid_T_1) | decodedInsts_0_csrrc)) & ((_isLsuCount_T_1 + {3'h0, ((((_rdMark_valid_T_49 | decodedInsts_2_lw) | decodedInsts_2_lbu) | decodedInsts_2_lhu) | _io_rs2Read_2_valid_T_25) | decodedInsts_2_sw}) < _GEN_20)) & |{decodedInsts_3_lui, decodedInsts_3_auipc, decodedInsts_3_jal, decodedInsts_3_jalr, decodedInsts_3_beq, decodedInsts_3_bne, decodedInsts_3_blt, decodedInsts_3_bge, decodedInsts_3_bltu, decodedInsts_3_bgeu, decodedInsts_3_lb, decodedInsts_3_lh, decodedInsts_3_lw, decodedInsts_3_lbu, decodedInsts_3_lhu, decodedInsts_3_sb, decodedInsts_3_sh, decodedInsts_3_sw, decodedInsts_3_addi, decodedInsts_3_slti, decodedInsts_3_sltiu, decodedInsts_3_xori, decodedInsts_3_ori, decodedInsts_3_andi, decodedInsts_3_add, decodedInsts_3_sub, decodedInsts_3_slt, decodedInsts_3_sltu, decodedInsts_3_xor, decodedInsts_3_or, decodedInsts_3_and, decodedInsts_3_xnor, decodedInsts_3_orn, decodedInsts_3_andn, decodedInsts_3_slli, decodedInsts_3_srli, decodedInsts_3_srai, decodedInsts_3_sll, decodedInsts_3_srl, decodedInsts_3_sra, decodedInsts_3_mul, decodedInsts_3_mulh, decodedInsts_3_mulhsu, decodedInsts_3_mulhu, decodedInsts_3_clz, decodedInsts_3_ctz, decodedInsts_3_cpop, decodedInsts_3_min, decodedInsts_3_minu, decodedInsts_3_max, decodedInsts_3_maxu, decodedInsts_3_sextb, decodedInsts_3_sexth, decodedInsts_3_zexth, decodedInsts_3_rol, decodedInsts_3_ror, decodedInsts_3_orcb, decodedInsts_3_rev8, decodedInsts_3_rori}) & |io_retirement_buffer_nSpace[4:2]) & ~io_retirement_buffer_trap_pending; + wire _alu_T_812 = (decodedInsts_3_auipc | decodedInsts_3_addi) | decodedInsts_3_add; + wire _alu_T_814 = decodedInsts_3_slti | decodedInsts_3_slt; + wire _alu_T_815 = decodedInsts_3_sltiu | decodedInsts_3_sltu; + wire _alu_T_816 = decodedInsts_3_xori | decodedInsts_3_xor; + wire _alu_T_817 = decodedInsts_3_ori | decodedInsts_3_or; + wire _alu_T_818 = decodedInsts_3_andi | decodedInsts_3_and; + wire _alu_T_819 = decodedInsts_3_slli | decodedInsts_3_sll; + wire _alu_T_820 = decodedInsts_3_srli | decodedInsts_3_srl; + wire _alu_T_821 = decodedInsts_3_srai | decodedInsts_3_sra; + wire io_alu_3_valid_0 = tryDispatch_3 & ((((((((((((((((((((((((((((_alu_T_812 | decodedInsts_3_sub) | _alu_T_814) | _alu_T_815) | _alu_T_816) | _alu_T_817) | _alu_T_818) | _alu_T_819) | _alu_T_820) | _alu_T_821) | decodedInsts_3_lui) | decodedInsts_3_andn) | decodedInsts_3_orn) | decodedInsts_3_xnor) | decodedInsts_3_clz) | decodedInsts_3_ctz) | decodedInsts_3_cpop) | decodedInsts_3_max) | decodedInsts_3_maxu) | decodedInsts_3_min) | decodedInsts_3_minu) | decodedInsts_3_sextb) | decodedInsts_3_sexth) | decodedInsts_3_rol) | decodedInsts_3_ror) | decodedInsts_3_orcb) | decodedInsts_3_rev8) | decodedInsts_3_zexth) | decodedInsts_3_rori); + wire [3:0] _bru_T_355 = ((((({3'h0, decodedInsts_3_jalr} | {2'h0, decodedInsts_3_beq, 1'h0}) | (decodedInsts_3_bne ? 4'h3 : 4'h0)) | {1'h0, decodedInsts_3_blt, 2'h0}) | (decodedInsts_3_bge ? 4'h5 : 4'h0)) | (decodedInsts_3_bltu ? 4'h6 : 4'h0)) | (decodedInsts_3_bgeu ? 4'h7 : 4'h0); + wire [31:0] _bru_target_T_11 = io_inst_3_bits_addr + {{12 {io_inst_3_bits_inst[31]}}, (io_inst_3_bits_inst[2] ? {io_inst_3_bits_inst[19:12], io_inst_3_bits_inst[20], io_inst_3_bits_inst[30:21]} : {{8 {io_inst_3_bits_inst[31]}}, io_inst_3_bits_inst[7], io_inst_3_bits_inst[30:25], io_inst_3_bits_inst[11:8]}), 1'h0}; + wire _io_bru_3_valid_T = tryDispatch_3 & (((((((decodedInsts_3_jal | decodedInsts_3_jalr) | decodedInsts_3_beq) | decodedInsts_3_bne) | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu); + wire jalFault_3 = ((_io_bru_3_valid_T & (_bru_T_355[2:0] == 3'h0)) & |_bru_target_T_11[1:0]) & ~io_branchTaken; + wire jalrFault_3 = ((_io_bru_3_valid_T & (_bru_T_355[2:0] == 3'h1)) & io_jalrTarget_3_data[1]) & ~io_branchTaken; + wire bxxFault_3 = ((_io_bru_3_valid_T & |{&_bru_T_355[2:0], _bru_T_355[2:0] == 3'h6, _bru_T_355[2:0] == 3'h5, _bru_T_355[2:0] == 3'h4, _bru_T_355[2:0] == 3'h3, _bru_T_355[2:0] == 3'h2}) & |_bru_target_T_11[1:0]) & ~io_branchTaken; + wire io_bru_3_valid_0 = _io_bru_3_valid_T & ~((jalFault_3 | jalrFault_3) | bxxFault_3); + wire io_mlu_3_valid_0 = tryDispatch_3 & (((decodedInsts_3_mul | decodedInsts_3_mulh) | decodedInsts_3_mulhsu) | decodedInsts_3_mulhu); + wire io_lsu_3_valid_0 = tryDispatch_3 & (((((((decodedInsts_3_lb | decodedInsts_3_lh) | decodedInsts_3_lw) | decodedInsts_3_lbu) | decodedInsts_3_lhu) | decodedInsts_3_sb) | decodedInsts_3_sh) | decodedInsts_3_sw); + wire dispatched_2_3 = io_mlu_3_ready & io_mlu_3_valid_0; + wire dispatched_4_3 = io_lsu_3_ready & io_lsu_3_valid_0; + wire lastReady_4 = ((io_alu_3_valid_0 | io_bru_3_valid_0) | dispatched_2_3) | dispatched_4_3; + wire _io_rs2Set_0_valid_T = lastReady_1 & io_inst_0_valid; + wire _io_rs2Set_1_valid_T = lastReady_2 & io_inst_1_valid; + wire _io_rs2Set_2_valid_T = lastReady_3 & io_inst_2_valid; + wire _io_rs2Set_3_valid_T = lastReady_4 & io_inst_3_valid; + assign io_csrFault_0 = (csr_valid & ~csr_address_valid) & tryDispatch; + assign io_jalFault_0 = jalFault; + assign io_jalFault_1 = jalFault_1; + assign io_jalFault_2 = jalFault_2; + assign io_jalFault_3 = jalFault_3; + assign io_jalrFault_0 = jalrFault; + assign io_jalrFault_1 = jalrFault_1; + assign io_jalrFault_2 = jalrFault_2; + assign io_jalrFault_3 = jalrFault_3; + assign io_bxxFault_0 = bxxFault; + assign io_bxxFault_1 = bxxFault_1; + assign io_bxxFault_2 = bxxFault_2; + assign io_bxxFault_3 = bxxFault_3; + assign io_bruTarget_0 = _bru_target_T_2; + assign io_bruTarget_1 = _bru_target_T_5; + assign io_bruTarget_2 = _bru_target_T_8; + assign io_bruTarget_3 = _bru_target_T_11; + assign io_inst_0_ready = lastReady_1; + assign io_inst_1_ready = lastReady_2; + assign io_inst_2_ready = lastReady_3; + assign io_inst_3_ready = lastReady_4; + assign io_rs1Read_0_addr = (io_inst_0_bits_inst[0] ? io_inst_0_bits_inst[19:15] : {4'h0, io_inst_0_bits_inst[27]}); + assign io_rs1Read_1_valid = _io_rs2Set_1_valid_T & (((((((((((((((((((((((((((((((((((((((((_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu) | _io_rs2Read_1_valid_T_6) | decodedInsts_1_slt) | decodedInsts_1_sltu) | decodedInsts_1_xor) | decodedInsts_1_or) | decodedInsts_1_and) | decodedInsts_1_xnor) | decodedInsts_1_orn) | decodedInsts_1_andn) | decodedInsts_1_sll) | decodedInsts_1_srl) | decodedInsts_1_sra) | _io_rs2Set_1_valid_T_6) | decodedInsts_1_sltiu) | decodedInsts_1_xori) | decodedInsts_1_ori) | decodedInsts_1_andi) | decodedInsts_1_slli) | decodedInsts_1_srli) | decodedInsts_1_srai) | decodedInsts_1_rori) | _io_rs2Set_1_valid_T_16) | decodedInsts_1_cpop) | decodedInsts_1_sextb) | decodedInsts_1_sexth) | decodedInsts_1_zexth) | decodedInsts_1_orcb) | decodedInsts_1_rev8) | _io_rs2Read_1_valid_T_19) | decodedInsts_1_max) | decodedInsts_1_maxu) | decodedInsts_1_rol) | decodedInsts_1_ror) | _io_rs2Read_1_valid_T_34) | decodedInsts_1_mulhsu) | decodedInsts_1_mulhu) | decodedInsts_1_jalr); + assign io_rs1Read_1_addr = (io_inst_1_bits_inst[0] ? io_inst_1_bits_inst[19:15] : {4'h0, io_inst_1_bits_inst[28]}); + assign io_rs1Read_2_valid = _io_rs2Set_2_valid_T & (((((((((((((((((((((((((((((((((((((((((_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu) | _io_rs2Read_2_valid_T_6) | decodedInsts_2_slt) | decodedInsts_2_sltu) | decodedInsts_2_xor) | decodedInsts_2_or) | decodedInsts_2_and) | decodedInsts_2_xnor) | decodedInsts_2_orn) | decodedInsts_2_andn) | decodedInsts_2_sll) | decodedInsts_2_srl) | decodedInsts_2_sra) | _io_rs2Set_2_valid_T_6) | decodedInsts_2_sltiu) | decodedInsts_2_xori) | decodedInsts_2_ori) | decodedInsts_2_andi) | decodedInsts_2_slli) | decodedInsts_2_srli) | decodedInsts_2_srai) | decodedInsts_2_rori) | _io_rs2Set_2_valid_T_16) | decodedInsts_2_cpop) | decodedInsts_2_sextb) | decodedInsts_2_sexth) | decodedInsts_2_zexth) | decodedInsts_2_orcb) | decodedInsts_2_rev8) | _io_rs2Read_2_valid_T_19) | decodedInsts_2_max) | decodedInsts_2_maxu) | decodedInsts_2_rol) | decodedInsts_2_ror) | _io_rs2Read_2_valid_T_34) | decodedInsts_2_mulhsu) | decodedInsts_2_mulhu) | decodedInsts_2_jalr); + assign io_rs1Read_2_addr = (io_inst_2_bits_inst[0] ? io_inst_2_bits_inst[19:15] : {4'h0, io_inst_2_bits_inst[29]}); + assign io_rs1Read_3_valid = _io_rs2Set_3_valid_T & (((((((((((((((((((((((((((((((((((((((((_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu) | _io_rs2Read_3_valid_T_6) | decodedInsts_3_slt) | decodedInsts_3_sltu) | decodedInsts_3_xor) | decodedInsts_3_or) | decodedInsts_3_and) | decodedInsts_3_xnor) | decodedInsts_3_orn) | decodedInsts_3_andn) | decodedInsts_3_sll) | decodedInsts_3_srl) | decodedInsts_3_sra) | _io_rs2Set_3_valid_T_6) | decodedInsts_3_sltiu) | decodedInsts_3_xori) | decodedInsts_3_ori) | decodedInsts_3_andi) | decodedInsts_3_slli) | decodedInsts_3_srli) | decodedInsts_3_srai) | decodedInsts_3_rori) | _io_rs2Set_3_valid_T_16) | decodedInsts_3_cpop) | decodedInsts_3_sextb) | decodedInsts_3_sexth) | decodedInsts_3_zexth) | decodedInsts_3_orcb) | decodedInsts_3_rev8) | _io_rs2Read_3_valid_T_19) | decodedInsts_3_max) | decodedInsts_3_maxu) | decodedInsts_3_rol) | decodedInsts_3_ror) | _io_rs2Read_3_valid_T_34) | decodedInsts_3_mulhsu) | decodedInsts_3_mulhu) | decodedInsts_3_jalr); + assign io_rs1Read_3_addr = (io_inst_3_bits_inst[0] ? io_inst_3_bits_inst[19:15] : {4'h0, io_inst_3_bits_inst[30]}); + assign io_rs1Set_0_valid = _io_rs2Set_0_valid_T & (decodedInsts_0_auipc | ((_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) & io_inst_0_bits_inst[14])); + assign io_rs1Set_0_value = (_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc ? decodedInsts_0_immcsr : io_inst_0_bits_addr); + assign io_rs1Set_1_valid = _io_rs2Set_1_valid_T & decodedInsts_1_auipc; + assign io_rs1Set_1_value = io_inst_1_bits_addr; + assign io_rs1Set_2_valid = _io_rs2Set_2_valid_T & decodedInsts_2_auipc; + assign io_rs1Set_2_value = io_inst_2_bits_addr; + assign io_rs1Set_3_valid = _io_rs2Set_3_valid_T & decodedInsts_3_auipc; + assign io_rs1Set_3_value = io_inst_3_bits_addr; + assign io_rs2Read_0_addr = io_inst_0_bits_inst[24:20]; + assign io_rs2Read_1_valid = _io_rs2Set_1_valid_T & ((((((((((((((((((((((((((_io_rs2Read_1_valid_T_1 | decodedInsts_1_blt) | decodedInsts_1_bge) | decodedInsts_1_bltu) | decodedInsts_1_bgeu) | _io_rs2Read_1_valid_T_6) | decodedInsts_1_slt) | decodedInsts_1_sltu) | decodedInsts_1_xor) | decodedInsts_1_or) | decodedInsts_1_and) | decodedInsts_1_xnor) | decodedInsts_1_orn) | decodedInsts_1_andn) | decodedInsts_1_sll) | decodedInsts_1_srl) | decodedInsts_1_sra) | _io_rs2Read_1_valid_T_19) | decodedInsts_1_max) | decodedInsts_1_maxu) | decodedInsts_1_rol) | decodedInsts_1_ror) | _io_rs2Read_1_valid_T_25) | decodedInsts_1_sw) | _io_rs2Read_1_valid_T_34) | decodedInsts_1_mulhsu) | decodedInsts_1_mulhu); + assign io_rs2Read_1_addr = io_inst_1_bits_inst[24:20]; + assign io_rs2Read_2_valid = _io_rs2Set_2_valid_T & ((((((((((((((((((((((((((_io_rs2Read_2_valid_T_1 | decodedInsts_2_blt) | decodedInsts_2_bge) | decodedInsts_2_bltu) | decodedInsts_2_bgeu) | _io_rs2Read_2_valid_T_6) | decodedInsts_2_slt) | decodedInsts_2_sltu) | decodedInsts_2_xor) | decodedInsts_2_or) | decodedInsts_2_and) | decodedInsts_2_xnor) | decodedInsts_2_orn) | decodedInsts_2_andn) | decodedInsts_2_sll) | decodedInsts_2_srl) | decodedInsts_2_sra) | _io_rs2Read_2_valid_T_19) | decodedInsts_2_max) | decodedInsts_2_maxu) | decodedInsts_2_rol) | decodedInsts_2_ror) | _io_rs2Read_2_valid_T_25) | decodedInsts_2_sw) | _io_rs2Read_2_valid_T_34) | decodedInsts_2_mulhsu) | decodedInsts_2_mulhu); + assign io_rs2Read_2_addr = io_inst_2_bits_inst[24:20]; + assign io_rs2Read_3_valid = _io_rs2Set_3_valid_T & ((((((((((((((((((((((((((_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu) | _io_rs2Read_3_valid_T_6) | decodedInsts_3_slt) | decodedInsts_3_sltu) | decodedInsts_3_xor) | decodedInsts_3_or) | decodedInsts_3_and) | decodedInsts_3_xnor) | decodedInsts_3_orn) | decodedInsts_3_andn) | decodedInsts_3_sll) | decodedInsts_3_srl) | decodedInsts_3_sra) | _io_rs2Read_3_valid_T_19) | decodedInsts_3_max) | decodedInsts_3_maxu) | decodedInsts_3_rol) | decodedInsts_3_ror) | _io_rs2Read_3_valid_T_25) | decodedInsts_3_sw) | _io_rs2Read_3_valid_T_34) | decodedInsts_3_mulhsu) | decodedInsts_3_mulhu); + assign io_rs2Read_3_addr = io_inst_3_bits_inst[24:20]; + assign io_rs2Set_0_valid = _io_rs2Set_0_valid_T & ((((((((((((((((((decodedInsts_0_auipc | ((_io_rs2Set_0_valid_T_1 | decodedInsts_0_csrrc) & io_inst_0_bits_inst[14])) | _io_rs2Set_0_valid_T_6) | decodedInsts_0_sltiu) | decodedInsts_0_xori) | decodedInsts_0_ori) | decodedInsts_0_andi) | decodedInsts_0_slli) | decodedInsts_0_srli) | decodedInsts_0_srai) | decodedInsts_0_rori) | _io_rs2Set_0_valid_T_16) | decodedInsts_0_cpop) | decodedInsts_0_sextb) | decodedInsts_0_sexth) | decodedInsts_0_zexth) | decodedInsts_0_orcb) | decodedInsts_0_rev8) | decodedInsts_0_lui); + assign io_rs2Set_0_value = (decodedInsts_0_auipc | decodedInsts_0_lui ? {io_inst_0_bits_inst[31:12], 12'h000} : {_decodedInsts_d_imm12_T_1, io_inst_0_bits_inst[31:20]}); + assign io_rs2Set_1_valid = _io_rs2Set_1_valid_T & (((((((((((((((((decodedInsts_1_auipc | _io_rs2Set_1_valid_T_6) | decodedInsts_1_sltiu) | decodedInsts_1_xori) | decodedInsts_1_ori) | decodedInsts_1_andi) | decodedInsts_1_slli) | decodedInsts_1_srli) | decodedInsts_1_srai) | decodedInsts_1_rori) | _io_rs2Set_1_valid_T_16) | decodedInsts_1_cpop) | decodedInsts_1_sextb) | decodedInsts_1_sexth) | decodedInsts_1_zexth) | decodedInsts_1_orcb) | decodedInsts_1_rev8) | decodedInsts_1_lui); + assign io_rs2Set_1_value = (decodedInsts_1_auipc | decodedInsts_1_lui ? {io_inst_1_bits_inst[31:12], 12'h000} : {_decodedInsts_d_imm12_T_5, io_inst_1_bits_inst[31:20]}); + assign io_rs2Set_2_valid = _io_rs2Set_2_valid_T & (((((((((((((((((decodedInsts_2_auipc | _io_rs2Set_2_valid_T_6) | decodedInsts_2_sltiu) | decodedInsts_2_xori) | decodedInsts_2_ori) | decodedInsts_2_andi) | decodedInsts_2_slli) | decodedInsts_2_srli) | decodedInsts_2_srai) | decodedInsts_2_rori) | _io_rs2Set_2_valid_T_16) | decodedInsts_2_cpop) | decodedInsts_2_sextb) | decodedInsts_2_sexth) | decodedInsts_2_zexth) | decodedInsts_2_orcb) | decodedInsts_2_rev8) | decodedInsts_2_lui); + assign io_rs2Set_2_value = (decodedInsts_2_auipc | decodedInsts_2_lui ? {io_inst_2_bits_inst[31:12], 12'h000} : {_decodedInsts_d_imm12_T_9, io_inst_2_bits_inst[31:20]}); + assign io_rs2Set_3_valid = _io_rs2Set_3_valid_T & (((((((((((((((((decodedInsts_3_auipc | _io_rs2Set_3_valid_T_6) | decodedInsts_3_sltiu) | decodedInsts_3_xori) | decodedInsts_3_ori) | decodedInsts_3_andi) | decodedInsts_3_slli) | decodedInsts_3_srli) | decodedInsts_3_srai) | decodedInsts_3_rori) | _io_rs2Set_3_valid_T_16) | decodedInsts_3_cpop) | decodedInsts_3_sextb) | decodedInsts_3_sexth) | decodedInsts_3_zexth) | decodedInsts_3_orcb) | decodedInsts_3_rev8) | decodedInsts_3_lui); + assign io_rs2Set_3_value = (decodedInsts_3_auipc | decodedInsts_3_lui ? {io_inst_3_bits_inst[31:12], 12'h000} : {_decodedInsts_d_imm12_T_13, io_inst_3_bits_inst[31:20]}); + assign io_rdMark_0_valid = (((((io_alu_0_valid_0 | io_mlu_0_valid_0) | dispatched_3) | (dispatched_4 & (((_rdMark_valid_T_5 | decodedInsts_0_lw) | decodedInsts_0_lbu) | decodedInsts_0_lhu))) | io_csr_valid_0) | (dispatched_8 & decodedInsts_float_scalar_rd)) | ((io_bru_0_valid_0 & |{_bru_T_67 == 4'h1, _bru_T_67 == 4'h0}) & |io_inst_0_bits_inst[11:7]); + assign io_rdMark_0_addr = io_inst_0_bits_inst[11:7]; + assign io_rdMark_1_valid = ((io_alu_1_valid_0 | dispatched_2_1) | (dispatched_4_1 & (((_rdMark_valid_T_28 | decodedInsts_1_lw) | decodedInsts_1_lbu) | decodedInsts_1_lhu))) | ((io_bru_1_valid_0 & |{_bru_T_163[2:0] == 3'h1, _bru_T_163[2:0] == 3'h0}) & |io_inst_1_bits_inst[11:7]); + assign io_rdMark_1_addr = io_inst_1_bits_inst[11:7]; + assign io_rdMark_2_valid = ((io_alu_2_valid_0 | dispatched_2_2) | (dispatched_4_2 & (((_rdMark_valid_T_49 | decodedInsts_2_lw) | decodedInsts_2_lbu) | decodedInsts_2_lhu))) | ((io_bru_2_valid_0 & |{_bru_T_259[2:0] == 3'h1, _bru_T_259[2:0] == 3'h0}) & |io_inst_2_bits_inst[11:7]); + assign io_rdMark_2_addr = io_inst_2_bits_inst[11:7]; + assign io_rdMark_3_valid = ((io_alu_3_valid_0 | dispatched_2_3) | (dispatched_4_3 & (((_rdMark_valid_T_70 | decodedInsts_3_lw) | decodedInsts_3_lbu) | decodedInsts_3_lhu))) | ((io_bru_3_valid_0 & |{_bru_T_355[2:0] == 3'h1, _bru_T_355[2:0] == 3'h0}) & |io_inst_3_bits_inst[11:7]); + assign io_rdMark_3_addr = io_inst_3_bits_inst[11:7]; + assign io_busRead_0_bypass = (io_inst_0_bits_inst[31:25] == 7'h00) & (~io_inst_0_bits_inst[5] | io_inst_0_bits_inst[6] ? io_inst_0_bits_inst[24:20] == 5'h00 : io_inst_0_bits_inst[11:7] == 5'h00); + assign io_busRead_0_immen = ~decodedInsts_0_flushat; + assign io_busRead_0_immed = {_decodedInsts_d_imm12_T_1, io_inst_0_bits_inst[31:25], ((io_inst_0_bits_inst[6:3] == 4'h4) & (&io_inst_0_bits_inst[1:0]) ? io_inst_0_bits_inst[11:7] : io_inst_0_bits_inst[24:20])}; + assign io_busRead_1_bypass = (io_inst_1_bits_inst[31:25] == 7'h00) & (~io_inst_1_bits_inst[5] | io_inst_1_bits_inst[6] ? io_inst_1_bits_inst[24:20] == 5'h00 : io_inst_1_bits_inst[11:7] == 5'h00); + assign io_busRead_1_immed = {_decodedInsts_d_imm12_T_5, io_inst_1_bits_inst[31:25], ((io_inst_1_bits_inst[6:3] == 4'h4) & (&io_inst_1_bits_inst[1:0]) ? io_inst_1_bits_inst[11:7] : io_inst_1_bits_inst[24:20])}; + assign io_busRead_2_bypass = (io_inst_2_bits_inst[31:25] == 7'h00) & (~io_inst_2_bits_inst[5] | io_inst_2_bits_inst[6] ? io_inst_2_bits_inst[24:20] == 5'h00 : io_inst_2_bits_inst[11:7] == 5'h00); + assign io_busRead_2_immed = {_decodedInsts_d_imm12_T_9, io_inst_2_bits_inst[31:25], ((io_inst_2_bits_inst[6:3] == 4'h4) & (&io_inst_2_bits_inst[1:0]) ? io_inst_2_bits_inst[11:7] : io_inst_2_bits_inst[24:20])}; + assign io_busRead_3_bypass = (io_inst_3_bits_inst[31:25] == 7'h00) & (~io_inst_3_bits_inst[5] | io_inst_3_bits_inst[6] ? io_inst_3_bits_inst[24:20] == 5'h00 : io_inst_3_bits_inst[11:7] == 5'h00); + assign io_busRead_3_immed = {_decodedInsts_d_imm12_T_13, io_inst_3_bits_inst[31:25], ((io_inst_3_bits_inst[6:3] == 4'h4) & (&io_inst_3_bits_inst[1:0]) ? io_inst_3_bits_inst[11:7] : io_inst_3_bits_inst[24:20])}; + assign io_rdMark_flt_valid = (dispatched_8 & ~decodedInsts_float_scalar_rd) | ((dispatched_4 & decodedInsts_floatValid) & _rdMark_flt_valid_T_4); + assign io_rdMark_flt_addr = io_inst_0_bits_inst[11:7]; + assign io_alu_0_valid = io_alu_0_valid_0; + assign io_alu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_alu_0_bits_op = (((((((((((((((((((((((((({4'h0, decodedInsts_0_sub} | {3'h0, _alu_T_160, 1'h0}) | (_alu_T_161 ? 5'h03 : 5'h00)) | {2'h0, _alu_T_162, 2'h0}) | (_alu_T_163 ? 5'h05 : 5'h00)) | (_alu_T_164 ? 5'h06 : 5'h00)) | (_alu_T_165 ? 5'h07 : 5'h00)) | {1'h0, _alu_T_166, 3'h0}) | (_alu_T_167 ? 5'h09 : 5'h00)) | (decodedInsts_0_lui ? 5'h0a : 5'h00)) | (decodedInsts_0_andn ? 5'h0b : 5'h00)) | (decodedInsts_0_orn ? 5'h0c : 5'h00)) | (decodedInsts_0_xnor ? 5'h0d : 5'h00)) | (decodedInsts_0_clz ? 5'h0e : 5'h00)) | (decodedInsts_0_ctz ? 5'h0f : 5'h00)) | {decodedInsts_0_cpop, 4'h0}) | (decodedInsts_0_max ? 5'h11 : 5'h00)) | (decodedInsts_0_maxu ? 5'h12 : 5'h00)) | (decodedInsts_0_min ? 5'h13 : 5'h00)) | (decodedInsts_0_minu ? 5'h14 : 5'h00)) | (decodedInsts_0_sextb ? 5'h15 : 5'h00)) | (decodedInsts_0_sexth ? 5'h16 : 5'h00)) | (decodedInsts_0_rol ? 5'h17 : 5'h00)) | (decodedInsts_0_ror ? 5'h18 : 5'h00)) | (decodedInsts_0_orcb ? 5'h19 : 5'h00)) | (decodedInsts_0_rev8 ? 5'h1a : 5'h00)) | (decodedInsts_0_zexth ? 5'h1b : 5'h00)) | (decodedInsts_0_rori ? 5'h18 : 5'h00); + assign io_alu_1_valid = io_alu_1_valid_0; + assign io_alu_1_bits_addr = io_inst_1_bits_inst[11:7]; + assign io_alu_1_bits_op = (((((((((((((((((((((((((({4'h0, decodedInsts_1_sub} | {3'h0, _alu_T_378, 1'h0}) | (_alu_T_379 ? 5'h03 : 5'h00)) | {2'h0, _alu_T_380, 2'h0}) | (_alu_T_381 ? 5'h05 : 5'h00)) | (_alu_T_382 ? 5'h06 : 5'h00)) | (_alu_T_383 ? 5'h07 : 5'h00)) | {1'h0, _alu_T_384, 3'h0}) | (_alu_T_385 ? 5'h09 : 5'h00)) | (decodedInsts_1_lui ? 5'h0a : 5'h00)) | (decodedInsts_1_andn ? 5'h0b : 5'h00)) | (decodedInsts_1_orn ? 5'h0c : 5'h00)) | (decodedInsts_1_xnor ? 5'h0d : 5'h00)) | (decodedInsts_1_clz ? 5'h0e : 5'h00)) | (decodedInsts_1_ctz ? 5'h0f : 5'h00)) | {decodedInsts_1_cpop, 4'h0}) | (decodedInsts_1_max ? 5'h11 : 5'h00)) | (decodedInsts_1_maxu ? 5'h12 : 5'h00)) | (decodedInsts_1_min ? 5'h13 : 5'h00)) | (decodedInsts_1_minu ? 5'h14 : 5'h00)) | (decodedInsts_1_sextb ? 5'h15 : 5'h00)) | (decodedInsts_1_sexth ? 5'h16 : 5'h00)) | (decodedInsts_1_rol ? 5'h17 : 5'h00)) | (decodedInsts_1_ror ? 5'h18 : 5'h00)) | (decodedInsts_1_orcb ? 5'h19 : 5'h00)) | (decodedInsts_1_rev8 ? 5'h1a : 5'h00)) | (decodedInsts_1_zexth ? 5'h1b : 5'h00)) | (decodedInsts_1_rori ? 5'h18 : 5'h00); + assign io_alu_2_valid = io_alu_2_valid_0; + assign io_alu_2_bits_addr = io_inst_2_bits_inst[11:7]; + assign io_alu_2_bits_op = (((((((((((((((((((((((((({4'h0, decodedInsts_2_sub} | {3'h0, _alu_T_596, 1'h0}) | (_alu_T_597 ? 5'h03 : 5'h00)) | {2'h0, _alu_T_598, 2'h0}) | (_alu_T_599 ? 5'h05 : 5'h00)) | (_alu_T_600 ? 5'h06 : 5'h00)) | (_alu_T_601 ? 5'h07 : 5'h00)) | {1'h0, _alu_T_602, 3'h0}) | (_alu_T_603 ? 5'h09 : 5'h00)) | (decodedInsts_2_lui ? 5'h0a : 5'h00)) | (decodedInsts_2_andn ? 5'h0b : 5'h00)) | (decodedInsts_2_orn ? 5'h0c : 5'h00)) | (decodedInsts_2_xnor ? 5'h0d : 5'h00)) | (decodedInsts_2_clz ? 5'h0e : 5'h00)) | (decodedInsts_2_ctz ? 5'h0f : 5'h00)) | {decodedInsts_2_cpop, 4'h0}) | (decodedInsts_2_max ? 5'h11 : 5'h00)) | (decodedInsts_2_maxu ? 5'h12 : 5'h00)) | (decodedInsts_2_min ? 5'h13 : 5'h00)) | (decodedInsts_2_minu ? 5'h14 : 5'h00)) | (decodedInsts_2_sextb ? 5'h15 : 5'h00)) | (decodedInsts_2_sexth ? 5'h16 : 5'h00)) | (decodedInsts_2_rol ? 5'h17 : 5'h00)) | (decodedInsts_2_ror ? 5'h18 : 5'h00)) | (decodedInsts_2_orcb ? 5'h19 : 5'h00)) | (decodedInsts_2_rev8 ? 5'h1a : 5'h00)) | (decodedInsts_2_zexth ? 5'h1b : 5'h00)) | (decodedInsts_2_rori ? 5'h18 : 5'h00); + assign io_alu_3_valid = io_alu_3_valid_0; + assign io_alu_3_bits_addr = io_inst_3_bits_inst[11:7]; + assign io_alu_3_bits_op = (((((((((((((((((((((((((({4'h0, decodedInsts_3_sub} | {3'h0, _alu_T_814, 1'h0}) | (_alu_T_815 ? 5'h03 : 5'h00)) | {2'h0, _alu_T_816, 2'h0}) | (_alu_T_817 ? 5'h05 : 5'h00)) | (_alu_T_818 ? 5'h06 : 5'h00)) | (_alu_T_819 ? 5'h07 : 5'h00)) | {1'h0, _alu_T_820, 3'h0}) | (_alu_T_821 ? 5'h09 : 5'h00)) | (decodedInsts_3_lui ? 5'h0a : 5'h00)) | (decodedInsts_3_andn ? 5'h0b : 5'h00)) | (decodedInsts_3_orn ? 5'h0c : 5'h00)) | (decodedInsts_3_xnor ? 5'h0d : 5'h00)) | (decodedInsts_3_clz ? 5'h0e : 5'h00)) | (decodedInsts_3_ctz ? 5'h0f : 5'h00)) | {decodedInsts_3_cpop, 4'h0}) | (decodedInsts_3_max ? 5'h11 : 5'h00)) | (decodedInsts_3_maxu ? 5'h12 : 5'h00)) | (decodedInsts_3_min ? 5'h13 : 5'h00)) | (decodedInsts_3_minu ? 5'h14 : 5'h00)) | (decodedInsts_3_sextb ? 5'h15 : 5'h00)) | (decodedInsts_3_sexth ? 5'h16 : 5'h00)) | (decodedInsts_3_rol ? 5'h17 : 5'h00)) | (decodedInsts_3_ror ? 5'h18 : 5'h00)) | (decodedInsts_3_orcb ? 5'h19 : 5'h00)) | (decodedInsts_3_rev8 ? 5'h1a : 5'h00)) | (decodedInsts_3_zexth ? 5'h1b : 5'h00)) | (decodedInsts_3_rori ? 5'h18 : 5'h00); + assign io_bru_0_valid = io_bru_0_valid_0; + assign io_bru_0_bits_fwd = io_inst_0_bits_brchFwd; + assign io_bru_0_bits_op = _bru_T_67; + assign io_bru_0_bits_pc = io_inst_0_bits_addr; + assign io_bru_0_bits_target = _bru_target_T_2; + assign io_bru_0_bits_link = io_inst_0_bits_inst[11:7]; + assign io_bru_1_valid = io_bru_1_valid_0; + assign io_bru_1_bits_fwd = io_inst_1_bits_brchFwd; + assign io_bru_1_bits_op = _bru_T_163; + assign io_bru_1_bits_pc = io_inst_1_bits_addr; + assign io_bru_1_bits_target = _bru_target_T_5; + assign io_bru_1_bits_link = io_inst_1_bits_inst[11:7]; + assign io_bru_2_valid = io_bru_2_valid_0; + assign io_bru_2_bits_fwd = io_inst_2_bits_brchFwd; + assign io_bru_2_bits_op = _bru_T_259; + assign io_bru_2_bits_pc = io_inst_2_bits_addr; + assign io_bru_2_bits_target = _bru_target_T_8; + assign io_bru_2_bits_link = io_inst_2_bits_inst[11:7]; + assign io_bru_3_valid = io_bru_3_valid_0; + assign io_bru_3_bits_fwd = io_inst_3_bits_brchFwd; + assign io_bru_3_bits_op = _bru_T_355; + assign io_bru_3_bits_pc = io_inst_3_bits_addr; + assign io_bru_3_bits_target = _bru_target_T_11; + assign io_bru_3_bits_link = io_inst_3_bits_inst[11:7]; + assign io_csr_valid = io_csr_valid_0; + assign io_csr_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_csr_bits_index = io_inst_0_bits_inst[31:20]; + assign io_csr_bits_rs1 = io_inst_0_bits_inst[19:15]; + assign io_csr_bits_op = {1'h0, decodedInsts_0_csrrs} | {decodedInsts_0_csrrc, 1'h0}; + assign io_lsu_0_valid = io_lsu_0_valid_0; + assign io_lsu_0_bits_store = io_inst_0_bits_inst[5]; + assign io_lsu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_lsu_0_bits_op = (((((((((({4'h0, decodedInsts_0_lh} | {3'h0, decodedInsts_0_lw, 1'h0}) | (decodedInsts_0_lbu ? 5'h03 : 5'h00)) | {2'h0, decodedInsts_0_lhu, 2'h0}) | (decodedInsts_0_sb ? 5'h05 : 5'h00)) | (decodedInsts_0_sh ? 5'h06 : 5'h00)) | (decodedInsts_0_sw ? 5'h07 : 5'h00)) | {1'h0, decodedInsts_0_wfi, 3'h0}) | {1'h0, decodedInsts_0_fencei, 3'h0}) | (decodedInsts_0_flushat ? 5'h09 : 5'h00)) | (decodedInsts_0_flushall ? 5'h0a : 5'h00)) | (_lsu_T_85 ? 5'h0c : 5'h00); + assign io_lsu_0_bits_pc = io_inst_0_bits_addr; + assign io_lsu_1_valid = io_lsu_1_valid_0; + assign io_lsu_1_bits_store = io_inst_1_bits_inst[5]; + assign io_lsu_1_bits_addr = io_inst_1_bits_inst[11:7]; + assign io_lsu_1_bits_op = ((((({4'h0, decodedInsts_1_lh} | {3'h0, decodedInsts_1_lw, 1'h0}) | (decodedInsts_1_lbu ? 5'h03 : 5'h00)) | {2'h0, decodedInsts_1_lhu, 2'h0}) | (decodedInsts_1_sb ? 5'h05 : 5'h00)) | (decodedInsts_1_sh ? 5'h06 : 5'h00)) | (decodedInsts_1_sw ? 5'h07 : 5'h00); + assign io_lsu_1_bits_pc = io_inst_1_bits_addr; + assign io_lsu_2_valid = io_lsu_2_valid_0; + assign io_lsu_2_bits_store = io_inst_2_bits_inst[5]; + assign io_lsu_2_bits_addr = io_inst_2_bits_inst[11:7]; + assign io_lsu_2_bits_op = ((((({4'h0, decodedInsts_2_lh} | {3'h0, decodedInsts_2_lw, 1'h0}) | (decodedInsts_2_lbu ? 5'h03 : 5'h00)) | {2'h0, decodedInsts_2_lhu, 2'h0}) | (decodedInsts_2_sb ? 5'h05 : 5'h00)) | (decodedInsts_2_sh ? 5'h06 : 5'h00)) | (decodedInsts_2_sw ? 5'h07 : 5'h00); + assign io_lsu_2_bits_pc = io_inst_2_bits_addr; + assign io_lsu_3_valid = io_lsu_3_valid_0; + assign io_lsu_3_bits_store = io_inst_3_bits_inst[5]; + assign io_lsu_3_bits_addr = io_inst_3_bits_inst[11:7]; + assign io_lsu_3_bits_op = ((((({4'h0, decodedInsts_3_lh} | {3'h0, decodedInsts_3_lw, 1'h0}) | (decodedInsts_3_lbu ? 5'h03 : 5'h00)) | {2'h0, decodedInsts_3_lhu, 2'h0}) | (decodedInsts_3_sb ? 5'h05 : 5'h00)) | (decodedInsts_3_sh ? 5'h06 : 5'h00)) | (decodedInsts_3_sw ? 5'h07 : 5'h00); + assign io_lsu_3_bits_pc = io_inst_3_bits_addr; + assign io_mlu_0_valid = io_mlu_0_valid_0; + assign io_mlu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_mlu_0_bits_op = ({2'h0, decodedInsts_0_mulh} | {1'h0, decodedInsts_0_mulhsu, 1'h0}) | (decodedInsts_0_mulhu ? 3'h3 : 3'h0); + assign io_mlu_1_valid = io_mlu_1_valid_0; + assign io_mlu_1_bits_addr = io_inst_1_bits_inst[11:7]; + assign io_mlu_1_bits_op = ({2'h0, decodedInsts_1_mulh} | {1'h0, decodedInsts_1_mulhsu, 1'h0}) | (decodedInsts_1_mulhu ? 3'h3 : 3'h0); + assign io_mlu_2_valid = io_mlu_2_valid_0; + assign io_mlu_2_bits_addr = io_inst_2_bits_inst[11:7]; + assign io_mlu_2_bits_op = ({2'h0, decodedInsts_2_mulh} | {1'h0, decodedInsts_2_mulhsu, 1'h0}) | (decodedInsts_2_mulhu ? 3'h3 : 3'h0); + assign io_mlu_3_valid = io_mlu_3_valid_0; + assign io_mlu_3_bits_addr = io_inst_3_bits_inst[11:7]; + assign io_mlu_3_bits_op = ({2'h0, decodedInsts_3_mulh} | {1'h0, decodedInsts_3_mulhsu, 1'h0}) | (decodedInsts_3_mulhu ? 3'h3 : 3'h0); + assign io_dvu_0_valid = io_dvu_0_valid_0; + assign io_dvu_0_bits_addr = io_inst_0_bits_inst[11:7]; + assign io_dvu_0_bits_op = ({1'h0, decodedInsts_0_divu} | {decodedInsts_0_rem, 1'h0}) | {2 {decodedInsts_0_remu}}; + assign io_float_valid = io_float_valid_0; + assign io_float_bits_opcode = decodedInsts_float_bits_opcode; + assign io_float_bits_funct5 = io_inst_0_bits_inst[31:27]; + assign io_float_bits_rs3 = io_inst_0_bits_inst[31:27]; + assign io_float_bits_rs2 = io_inst_0_bits_inst[24:20]; + assign io_float_bits_rs1 = io_inst_0_bits_inst[19:15]; + assign io_float_bits_rm = io_inst_0_bits_inst[14:12]; + assign io_float_bits_inst = io_inst_0_bits_inst; + assign io_float_bits_pc = io_inst_0_bits_addr; + assign io_float_bits_scalar_rd = decodedInsts_float_scalar_rd; + assign io_float_bits_scalar_rs1 = decodedInsts_float_scalar_rs1; + assign io_float_bits_float_rs1 = decodedInsts_float_float_rs1; + assign io_float_bits_rd = io_inst_0_bits_inst[11:7]; + assign io_float_bits_uses_rs3 = |_decodedInsts_float_uses_rs3_T_4; + assign io_float_bits_uses_rs2 = decodedInsts_float_uses_rs2; + assign io_fbusPortAddr = io_inst_0_bits_inst[24:20]; + assign io_branch_0 = isBranch_0; + assign io_branch_1 = isBranch_1; + assign io_branch_2 = isBranch_2; + assign io_branch_3 = (((_io_rs2Read_3_valid_T_1 | decodedInsts_3_blt) | decodedInsts_3_bge) | decodedInsts_3_bltu) | decodedInsts_3_bgeu; + assign io_jump_0 = (((((_bru_defaultSel_T | decodedInsts_0_ebreak) | decodedInsts_0_ecall) | decodedInsts_0_mpause) | decodedInsts_0_mret) & ~decodedInsts_0_ecall) & ~decodedInsts_0_mret; + assign io_jump_1 = isJump_1; + assign io_jump_2 = isJump_2; + assign io_jump_3 = decodedInsts_3_jal | decodedInsts_3_jalr; +endmodule +module CircularBufferMulti_1 ( + clock, + reset, + io_enqValid, + io_enqData_0_store, + io_enqData_0_rd, + io_enqData_0_op, + io_enqData_0_pc, + io_enqData_0_addr, + io_enqData_0_data, + io_enqData_1_store, + io_enqData_1_rd, + io_enqData_1_op, + io_enqData_1_pc, + io_enqData_1_addr, + io_enqData_1_data, + io_enqData_2_store, + io_enqData_2_rd, + io_enqData_2_op, + io_enqData_2_pc, + io_enqData_2_addr, + io_enqData_2_data, + io_enqData_3_store, + io_enqData_3_rd, + io_enqData_3_op, + io_enqData_3_pc, + io_enqData_3_addr, + io_enqData_3_data, + io_nEnqueued, + io_nSpace, + io_dataOut_0_store, + io_dataOut_0_rd, + io_dataOut_0_op, + io_dataOut_0_pc, + io_dataOut_0_addr, + io_dataOut_0_data, + io_dataOut_1_store, + io_dataOut_1_rd, + io_dataOut_1_op, + io_dataOut_1_pc, + io_dataOut_1_addr, + io_dataOut_1_data, + io_dataOut_2_store, + io_dataOut_2_rd, + io_dataOut_2_op, + io_dataOut_2_pc, + io_dataOut_2_addr, + io_dataOut_2_data, + io_dataOut_3_store, + io_dataOut_3_rd, + io_dataOut_3_op, + io_dataOut_3_pc, + io_dataOut_3_addr, + io_dataOut_3_data, + io_deqReady, + io_flush +); + input clock; + input reset; + input [2:0] io_enqValid; + input io_enqData_0_store; + input [4:0] io_enqData_0_rd; + input [4:0] io_enqData_0_op; + input [31:0] io_enqData_0_pc; + input [31:0] io_enqData_0_addr; + input [31:0] io_enqData_0_data; + input io_enqData_1_store; + input [4:0] io_enqData_1_rd; + input [4:0] io_enqData_1_op; + input [31:0] io_enqData_1_pc; + input [31:0] io_enqData_1_addr; + input [31:0] io_enqData_1_data; + input io_enqData_2_store; + input [4:0] io_enqData_2_rd; + input [4:0] io_enqData_2_op; + input [31:0] io_enqData_2_pc; + input [31:0] io_enqData_2_addr; + input [31:0] io_enqData_2_data; + input io_enqData_3_store; + input [4:0] io_enqData_3_rd; + input [4:0] io_enqData_3_op; + input [31:0] io_enqData_3_pc; + input [31:0] io_enqData_3_addr; + input [31:0] io_enqData_3_data; + output wire [2:0] io_nEnqueued; + output wire [2:0] io_nSpace; + output wire io_dataOut_0_store; + output wire [4:0] io_dataOut_0_rd; + output wire [4:0] io_dataOut_0_op; + output wire [31:0] io_dataOut_0_pc; + output wire [31:0] io_dataOut_0_addr; + output wire [31:0] io_dataOut_0_data; + output wire io_dataOut_1_store; + output wire [4:0] io_dataOut_1_rd; + output wire [4:0] io_dataOut_1_op; + output wire [31:0] io_dataOut_1_pc; + output wire [31:0] io_dataOut_1_addr; + output wire [31:0] io_dataOut_1_data; + output wire io_dataOut_2_store; + output wire [4:0] io_dataOut_2_rd; + output wire [4:0] io_dataOut_2_op; + output wire [31:0] io_dataOut_2_pc; + output wire [31:0] io_dataOut_2_addr; + output wire [31:0] io_dataOut_2_data; + output wire io_dataOut_3_store; + output wire [4:0] io_dataOut_3_rd; + output wire [4:0] io_dataOut_3_op; + output wire [31:0] io_dataOut_3_pc; + output wire [31:0] io_dataOut_3_addr; + output wire [31:0] io_dataOut_3_data; + input [2:0] io_deqReady; + input io_flush; + reg buffer_0_store; + reg [4:0] buffer_0_rd; + reg [4:0] buffer_0_op; + reg [31:0] buffer_0_pc; + reg [31:0] buffer_0_addr; + reg [31:0] buffer_0_data; + reg buffer_1_store; + reg [4:0] buffer_1_rd; + reg [4:0] buffer_1_op; + reg [31:0] buffer_1_pc; + reg [31:0] buffer_1_addr; + reg [31:0] buffer_1_data; + reg buffer_2_store; + reg [4:0] buffer_2_rd; + reg [4:0] buffer_2_op; + reg [31:0] buffer_2_pc; + reg [31:0] buffer_2_addr; + reg [31:0] buffer_2_data; + reg buffer_3_store; + reg [4:0] buffer_3_rd; + reg [4:0] buffer_3_op; + reg [31:0] buffer_3_pc; + reg [31:0] buffer_3_addr; + reg [31:0] buffer_3_data; + reg [1:0] enqPtr; + reg [1:0] deqPtr; + reg [2:0] nEnqueued; + wire [8:0] _outputBufferView_rotated_T_9 = {7'h00, deqPtr} * 9'h06b; + wire [427:0] _outputBufferView_rotated_T_22 = (_outputBufferView_rotated_T_9[0] ? {buffer_0_data[0], buffer_3_store, buffer_3_rd, buffer_3_op, buffer_3_pc, buffer_3_addr, buffer_3_data, buffer_2_store, buffer_2_rd, buffer_2_op, buffer_2_pc, buffer_2_addr, buffer_2_data, buffer_1_store, buffer_1_rd, buffer_1_op, buffer_1_pc, buffer_1_addr, buffer_1_data, buffer_0_store, buffer_0_rd, buffer_0_op, buffer_0_pc, buffer_0_addr, buffer_0_data[31:1]} : {buffer_3_store, buffer_3_rd, buffer_3_op, buffer_3_pc, buffer_3_addr, buffer_3_data, buffer_2_store, buffer_2_rd, buffer_2_op, buffer_2_pc, buffer_2_addr, buffer_2_data, buffer_1_store, buffer_1_rd, buffer_1_op, buffer_1_pc, buffer_1_addr, buffer_1_data, buffer_0_store, buffer_0_rd, buffer_0_op, buffer_0_pc, buffer_0_addr, buffer_0_data}); + wire [427:0] _outputBufferView_rotated_T_26 = (_outputBufferView_rotated_T_9[1] ? {_outputBufferView_rotated_T_22[1:0], _outputBufferView_rotated_T_22[427:2]} : _outputBufferView_rotated_T_22); + wire [427:0] _outputBufferView_rotated_T_30 = (_outputBufferView_rotated_T_9[2] ? {_outputBufferView_rotated_T_26[3:0], _outputBufferView_rotated_T_26[427:4]} : _outputBufferView_rotated_T_26); + wire [427:0] _outputBufferView_rotated_T_34 = (_outputBufferView_rotated_T_9[3] ? {_outputBufferView_rotated_T_30[7:0], _outputBufferView_rotated_T_30[427:8]} : _outputBufferView_rotated_T_30); + wire [427:0] _outputBufferView_rotated_T_38 = (_outputBufferView_rotated_T_9[4] ? {_outputBufferView_rotated_T_34[15:0], _outputBufferView_rotated_T_34[427:16]} : _outputBufferView_rotated_T_34); + wire [427:0] _outputBufferView_rotated_T_42 = (_outputBufferView_rotated_T_9[5] ? {_outputBufferView_rotated_T_38[31:0], _outputBufferView_rotated_T_38[427:32]} : _outputBufferView_rotated_T_38); + wire [427:0] _outputBufferView_rotated_T_46 = (_outputBufferView_rotated_T_9[6] ? {_outputBufferView_rotated_T_42[63:0], _outputBufferView_rotated_T_42[427:64]} : _outputBufferView_rotated_T_42); + wire [427:0] _outputBufferView_rotated_T_50 = (_outputBufferView_rotated_T_9[7] ? {_outputBufferView_rotated_T_46[127:0], _outputBufferView_rotated_T_46[427:128]} : _outputBufferView_rotated_T_46); + wire [427:0] outputBufferView_rotated = (_outputBufferView_rotated_T_9[8] ? {_outputBufferView_rotated_T_50[255:0], _outputBufferView_rotated_T_50[427:256]} : _outputBufferView_rotated_T_50); + wire expandedInput_2_ret_valid = io_enqValid > 3'h2; + wire [8:0] _rotatedInput_rotated_T_13 = {7'h00, enqPtr} * 9'h06c; + wire [431:0] _rotatedInput_rotated_T_26 = (_rotatedInput_rotated_T_13[0] ? {io_enqData_3_store, io_enqData_3_rd, io_enqData_3_op, io_enqData_3_pc, io_enqData_3_addr, io_enqData_3_data, expandedInput_2_ret_valid, io_enqData_2_store, io_enqData_2_rd, io_enqData_2_op, io_enqData_2_pc, io_enqData_2_addr, io_enqData_2_data, |io_enqValid[2:1], io_enqData_1_store, io_enqData_1_rd, io_enqData_1_op, io_enqData_1_pc, io_enqData_1_addr, io_enqData_1_data, |io_enqValid, io_enqData_0_store, io_enqData_0_rd, io_enqData_0_op, io_enqData_0_pc, io_enqData_0_addr, io_enqData_0_data, io_enqValid[2]} : {io_enqValid[2], io_enqData_3_store, io_enqData_3_rd, io_enqData_3_op, io_enqData_3_pc, io_enqData_3_addr, io_enqData_3_data, expandedInput_2_ret_valid, io_enqData_2_store, io_enqData_2_rd, io_enqData_2_op, io_enqData_2_pc, io_enqData_2_addr, io_enqData_2_data, |io_enqValid[2:1], io_enqData_1_store, io_enqData_1_rd, io_enqData_1_op, io_enqData_1_pc, io_enqData_1_addr, io_enqData_1_data, |io_enqValid, io_enqData_0_store, io_enqData_0_rd, io_enqData_0_op, io_enqData_0_pc, io_enqData_0_addr, io_enqData_0_data}); + wire [431:0] _rotatedInput_rotated_T_30 = (_rotatedInput_rotated_T_13[1] ? {_rotatedInput_rotated_T_26[429:0], _rotatedInput_rotated_T_26[431:430]} : _rotatedInput_rotated_T_26); + wire [431:0] _rotatedInput_rotated_T_34 = (_rotatedInput_rotated_T_13[2] ? {_rotatedInput_rotated_T_30[427:0], _rotatedInput_rotated_T_30[431:428]} : _rotatedInput_rotated_T_30); + wire [431:0] _rotatedInput_rotated_T_38 = (_rotatedInput_rotated_T_13[3] ? {_rotatedInput_rotated_T_34[423:0], _rotatedInput_rotated_T_34[431:424]} : _rotatedInput_rotated_T_34); + wire [431:0] _rotatedInput_rotated_T_42 = (_rotatedInput_rotated_T_13[4] ? {_rotatedInput_rotated_T_38[415:0], _rotatedInput_rotated_T_38[431:416]} : _rotatedInput_rotated_T_38); + wire [431:0] _rotatedInput_rotated_T_46 = (_rotatedInput_rotated_T_13[5] ? {_rotatedInput_rotated_T_42[399:0], _rotatedInput_rotated_T_42[431:400]} : _rotatedInput_rotated_T_42); + wire [431:0] _rotatedInput_rotated_T_50 = (_rotatedInput_rotated_T_13[6] ? {_rotatedInput_rotated_T_46[367:0], _rotatedInput_rotated_T_46[431:368]} : _rotatedInput_rotated_T_46); + wire [431:0] _rotatedInput_rotated_T_54 = (_rotatedInput_rotated_T_13[7] ? {_rotatedInput_rotated_T_50[303:0], _rotatedInput_rotated_T_50[431:304]} : _rotatedInput_rotated_T_50); + wire [431:0] rotatedInput_rotated = (_rotatedInput_rotated_T_13[8] ? {_rotatedInput_rotated_T_54[175:0], _rotatedInput_rotated_T_54[431:176]} : _rotatedInput_rotated_T_54); + always @(posedge clock or posedge reset) + if (reset) begin + buffer_0_store <= 1'h0; + buffer_0_rd <= 5'h00; + buffer_0_op <= 5'h00; + buffer_0_pc <= 32'h00000000; + buffer_0_addr <= 32'h00000000; + buffer_0_data <= 32'h00000000; + buffer_1_store <= 1'h0; + buffer_1_rd <= 5'h00; + buffer_1_op <= 5'h00; + buffer_1_pc <= 32'h00000000; + buffer_1_addr <= 32'h00000000; + buffer_1_data <= 32'h00000000; + buffer_2_store <= 1'h0; + buffer_2_rd <= 5'h00; + buffer_2_op <= 5'h00; + buffer_2_pc <= 32'h00000000; + buffer_2_addr <= 32'h00000000; + buffer_2_data <= 32'h00000000; + buffer_3_store <= 1'h0; + buffer_3_rd <= 5'h00; + buffer_3_op <= 5'h00; + buffer_3_pc <= 32'h00000000; + buffer_3_addr <= 32'h00000000; + buffer_3_data <= 32'h00000000; + enqPtr <= 2'h0; + deqPtr <= 2'h0; + nEnqueued <= 3'h0; + end + else begin + if (rotatedInput_rotated[107]) begin + buffer_0_store <= rotatedInput_rotated[106]; + buffer_0_rd <= rotatedInput_rotated[105:101]; + buffer_0_op <= rotatedInput_rotated[100:96]; + buffer_0_pc <= rotatedInput_rotated[95:64]; + buffer_0_addr <= rotatedInput_rotated[63:32]; + buffer_0_data <= rotatedInput_rotated[31:0]; + end + if (rotatedInput_rotated[215]) begin + buffer_1_store <= rotatedInput_rotated[214]; + buffer_1_rd <= rotatedInput_rotated[213:209]; + buffer_1_op <= rotatedInput_rotated[208:204]; + buffer_1_pc <= rotatedInput_rotated[203:172]; + buffer_1_addr <= rotatedInput_rotated[171:140]; + buffer_1_data <= rotatedInput_rotated[139:108]; + end + if (rotatedInput_rotated[323]) begin + buffer_2_store <= rotatedInput_rotated[322]; + buffer_2_rd <= rotatedInput_rotated[321:317]; + buffer_2_op <= rotatedInput_rotated[316:312]; + buffer_2_pc <= rotatedInput_rotated[311:280]; + buffer_2_addr <= rotatedInput_rotated[279:248]; + buffer_2_data <= rotatedInput_rotated[247:216]; + end + if (rotatedInput_rotated[431]) begin + buffer_3_store <= rotatedInput_rotated[430]; + buffer_3_rd <= rotatedInput_rotated[429:425]; + buffer_3_op <= rotatedInput_rotated[424:420]; + buffer_3_pc <= rotatedInput_rotated[419:388]; + buffer_3_addr <= rotatedInput_rotated[387:356]; + buffer_3_data <= rotatedInput_rotated[355:324]; + end + enqPtr <= (io_flush ? 2'h0 : enqPtr + io_enqValid[1:0]); + deqPtr <= (io_flush ? 2'h0 : deqPtr + io_deqReady[1:0]); + nEnqueued <= (io_flush ? 3'h0 : (nEnqueued + io_enqValid) - io_deqReady); + end + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 3'h4 - nEnqueued; + assign io_dataOut_0_store = outputBufferView_rotated[106]; + assign io_dataOut_0_rd = outputBufferView_rotated[105:101]; + assign io_dataOut_0_op = outputBufferView_rotated[100:96]; + assign io_dataOut_0_pc = outputBufferView_rotated[95:64]; + assign io_dataOut_0_addr = outputBufferView_rotated[63:32]; + assign io_dataOut_0_data = outputBufferView_rotated[31:0]; + assign io_dataOut_1_store = outputBufferView_rotated[213]; + assign io_dataOut_1_rd = outputBufferView_rotated[212:208]; + assign io_dataOut_1_op = outputBufferView_rotated[207:203]; + assign io_dataOut_1_pc = outputBufferView_rotated[202:171]; + assign io_dataOut_1_addr = outputBufferView_rotated[170:139]; + assign io_dataOut_1_data = outputBufferView_rotated[138:107]; + assign io_dataOut_2_store = outputBufferView_rotated[320]; + assign io_dataOut_2_rd = outputBufferView_rotated[319:315]; + assign io_dataOut_2_op = outputBufferView_rotated[314:310]; + assign io_dataOut_2_pc = outputBufferView_rotated[309:278]; + assign io_dataOut_2_addr = outputBufferView_rotated[277:246]; + assign io_dataOut_2_data = outputBufferView_rotated[245:214]; + assign io_dataOut_3_store = outputBufferView_rotated[427]; + assign io_dataOut_3_rd = outputBufferView_rotated[426:422]; + assign io_dataOut_3_op = outputBufferView_rotated[421:417]; + assign io_dataOut_3_pc = outputBufferView_rotated[416:385]; + assign io_dataOut_3_addr = outputBufferView_rotated[384:353]; + assign io_dataOut_3_data = outputBufferView_rotated[352:321]; +endmodule +module LsuV2 ( + clock, + reset, + io_req_0_ready, + io_req_0_valid, + io_req_0_bits_store, + io_req_0_bits_addr, + io_req_0_bits_op, + io_req_0_bits_pc, + io_req_1_ready, + io_req_1_valid, + io_req_1_bits_store, + io_req_1_bits_addr, + io_req_1_bits_op, + io_req_1_bits_pc, + io_req_2_ready, + io_req_2_valid, + io_req_2_bits_store, + io_req_2_bits_addr, + io_req_2_bits_op, + io_req_2_bits_pc, + io_req_3_ready, + io_req_3_valid, + io_req_3_bits_store, + io_req_3_bits_addr, + io_req_3_bits_op, + io_req_3_bits_pc, + io_busPort_addr_0, + io_busPort_addr_1, + io_busPort_addr_2, + io_busPort_addr_3, + io_busPort_data_0, + io_busPort_data_1, + io_busPort_data_2, + io_busPort_data_3, + io_busPort_flt_data_0, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data, + io_rd_flt_valid, + io_rd_flt_bits_addr, + io_rd_flt_bits_data, + io_ibus_valid, + io_ibus_ready, + io_ibus_addr, + io_ibus_rdata, + io_dbus_valid, + io_dbus_write, + io_dbus_addr, + io_dbus_wdata, + io_dbus_wmask, + io_dbus_rdata, + io_flush_valid, + io_flush_ready, + io_flush_fencei, + io_flush_pcNext, + io_fault_valid, + io_fault_bits_write, + io_fault_bits_addr, + io_fault_bits_epc, + io_ebus_dbus_valid, + io_ebus_dbus_ready, + io_ebus_dbus_write, + io_ebus_dbus_pc, + io_ebus_dbus_addr, + io_ebus_dbus_size, + io_ebus_dbus_wdata, + io_ebus_dbus_wmask, + io_ebus_dbus_rdata, + io_ebus_fault_valid, + io_ebus_fault_bits_write, + io_ebus_fault_bits_addr, + io_ebus_fault_bits_epc, + io_queueCapacity, + io_active, + io_storeComplete_valid, + io_storeComplete_bits +); + input clock; + input reset; + output wire io_req_0_ready; + input io_req_0_valid; + input io_req_0_bits_store; + input [4:0] io_req_0_bits_addr; + input [4:0] io_req_0_bits_op; + input [31:0] io_req_0_bits_pc; + output wire io_req_1_ready; + input io_req_1_valid; + input io_req_1_bits_store; + input [4:0] io_req_1_bits_addr; + input [4:0] io_req_1_bits_op; + input [31:0] io_req_1_bits_pc; + output wire io_req_2_ready; + input io_req_2_valid; + input io_req_2_bits_store; + input [4:0] io_req_2_bits_addr; + input [4:0] io_req_2_bits_op; + input [31:0] io_req_2_bits_pc; + output wire io_req_3_ready; + input io_req_3_valid; + input io_req_3_bits_store; + input [4:0] io_req_3_bits_addr; + input [4:0] io_req_3_bits_op; + input [31:0] io_req_3_bits_pc; + input [31:0] io_busPort_addr_0; + input [31:0] io_busPort_addr_1; + input [31:0] io_busPort_addr_2; + input [31:0] io_busPort_addr_3; + input [31:0] io_busPort_data_0; + input [31:0] io_busPort_data_1; + input [31:0] io_busPort_data_2; + input [31:0] io_busPort_data_3; + input [31:0] io_busPort_flt_data_0; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + output wire io_rd_flt_valid; + output wire [4:0] io_rd_flt_bits_addr; + output wire [31:0] io_rd_flt_bits_data; + output wire io_ibus_valid; + input io_ibus_ready; + output wire [31:0] io_ibus_addr; + input [127:0] io_ibus_rdata; + output wire io_dbus_valid; + output wire io_dbus_write; + output wire [31:0] io_dbus_addr; + output wire [127:0] io_dbus_wdata; + output wire [15:0] io_dbus_wmask; + input [127:0] io_dbus_rdata; + output wire io_flush_valid; + input io_flush_ready; + output wire io_flush_fencei; + output wire [31:0] io_flush_pcNext; + output wire io_fault_valid; + output wire io_fault_bits_write; + output wire [31:0] io_fault_bits_addr; + output wire [31:0] io_fault_bits_epc; + output wire io_ebus_dbus_valid; + input io_ebus_dbus_ready; + output wire io_ebus_dbus_write; + output wire [31:0] io_ebus_dbus_pc; + output wire [31:0] io_ebus_dbus_addr; + output wire [4:0] io_ebus_dbus_size; + output wire [127:0] io_ebus_dbus_wdata; + output wire [15:0] io_ebus_dbus_wmask; + input [127:0] io_ebus_dbus_rdata; + input io_ebus_fault_valid; + input io_ebus_fault_bits_write; + input [31:0] io_ebus_fault_bits_addr; + input [31:0] io_ebus_fault_bits_epc; + output wire [2:0] io_queueCapacity; + output wire io_active; + output wire io_storeComplete_valid; + output wire [31:0] io_storeComplete_bits; + wire io_req_0_ready_0; + wire _alignedOps_aligner_out_0_valid; + wire [106:0] _alignedOps_aligner_out_0_bits; + wire _alignedOps_aligner_out_1_valid; + wire [106:0] _alignedOps_aligner_out_1_bits; + wire _alignedOps_aligner_out_2_valid; + wire [106:0] _alignedOps_aligner_out_2_bits; + wire _alignedOps_aligner_out_3_valid; + wire [106:0] _alignedOps_aligner_out_3_bits; + wire [2:0] _opQueue_io_nEnqueued; + wire [2:0] _opQueue_io_nSpace; + wire _opQueue_io_dataOut_0_store; + wire [4:0] _opQueue_io_dataOut_0_rd; + wire [4:0] _opQueue_io_dataOut_0_op; + wire [31:0] _opQueue_io_dataOut_0_pc; + wire [31:0] _opQueue_io_dataOut_0_addr; + wire [31:0] _opQueue_io_dataOut_0_data; + reg flushCmd_valid; + reg flushCmd_bits_fencei; + reg [31:0] flushCmd_bits_pcNext; + wire _ops_T = io_req_0_ready_0 & io_req_0_valid; + wire flushCmd_result_fencei = io_req_0_bits_op == 5'h08; + wire _ops_T_2 = io_req_0_bits_op == 5'h09; + wire _ops_T_3 = io_req_0_bits_op == 5'h0a; + wire [2:0] _validSum_T_1 = {2'h0, io_req_0_valid} + {2'h0, io_req_1_valid}; + assign io_req_0_ready_0 = |_opQueue_io_nSpace & ~flushCmd_valid; + wire io_req_1_ready_0 = ({2'h0, io_req_0_valid} < _opQueue_io_nSpace) & ~flushCmd_valid; + wire io_req_2_ready_0 = (_validSum_T_1 < _opQueue_io_nSpace) & ~flushCmd_valid; + wire io_req_3_ready_0 = ((_validSum_T_1 + {2'h0, io_req_2_valid}) < _opQueue_io_nSpace) & ~flushCmd_valid; + wire [2:0] opQueue_io_enqValid = {1'h0, {1'h0, _alignedOps_aligner_out_0_valid} + {1'h0, _alignedOps_aligner_out_1_valid}} + {1'h0, {1'h0, _alignedOps_aligner_out_2_valid} + {1'h0, _alignedOps_aligner_out_3_valid}}; + wire _nextSlot_result_elemStride_T = _opQueue_io_dataOut_0_op == 5'h0d; + wire _nextSlot_T_16 = _opQueue_io_dataOut_0_op == 5'h0e; + wire _nextSlot_unitStride_T = _opQueue_io_dataOut_0_op == 5'h0f; + wire _nextSlot_unitStride_T_1 = _opQueue_io_dataOut_0_op == 5'h10; + wire _nextSlot_result_elemStride_T_1 = _opQueue_io_dataOut_0_op == 5'h11; + wire _nextSlot_T_17 = _opQueue_io_dataOut_0_op == 5'h12; + wire _nextSlot_unitStride_T_2 = _opQueue_io_dataOut_0_op == 5'h13; + wire _nextSlot_unitStride_T_3 = _opQueue_io_dataOut_0_op == 5'h14; + wire [2:0] _nextSlot_active_T_3 = {_opQueue_io_dataOut_0_op == 5'h05, _opQueue_io_dataOut_0_op == 5'h03, _opQueue_io_dataOut_0_op == 5'h00}; + wire [2:0] _nextSlot_active_T_8 = {_opQueue_io_dataOut_0_op == 5'h06, _opQueue_io_dataOut_0_op == 5'h04, _opQueue_io_dataOut_0_op == 5'h01}; + wire [2:0] _nextSlot_active_T_13 = {_opQueue_io_dataOut_0_op == 5'h0c, _opQueue_io_dataOut_0_op == 5'h07, _opQueue_io_dataOut_0_op == 5'h02}; + reg readFired_valid; + reg [1:0] readFired_bits_bus; + reg [27:0] readFired_bits_lineAddr; + reg [4:0] slot_op; + reg [4:0] slot_rd; + reg slot_store; + reg [31:0] slot_pc; + reg slot_active_0; + reg slot_active_1; + reg slot_active_2; + reg slot_active_3; + reg slot_active_4; + reg slot_active_5; + reg slot_active_6; + reg slot_active_7; + reg slot_active_8; + reg slot_active_9; + reg slot_active_10; + reg slot_active_11; + reg slot_active_12; + reg slot_active_13; + reg slot_active_14; + reg slot_active_15; + reg [31:0] slot_addrs_0; + reg [31:0] slot_addrs_1; + reg [31:0] slot_addrs_2; + reg [31:0] slot_addrs_3; + reg [31:0] slot_addrs_4; + reg [31:0] slot_addrs_5; + reg [31:0] slot_addrs_6; + reg [31:0] slot_addrs_7; + reg [31:0] slot_addrs_8; + reg [31:0] slot_addrs_9; + reg [31:0] slot_addrs_10; + reg [31:0] slot_addrs_11; + reg [31:0] slot_addrs_12; + reg [31:0] slot_addrs_13; + reg [31:0] slot_addrs_14; + reg [31:0] slot_addrs_15; + reg [7:0] slot_data_0; + reg [7:0] slot_data_1; + reg [7:0] slot_data_2; + reg [7:0] slot_data_3; + reg [7:0] slot_data_4; + reg [7:0] slot_data_5; + reg [7:0] slot_data_6; + reg [7:0] slot_data_7; + reg [7:0] slot_data_8; + reg [7:0] slot_data_9; + reg [7:0] slot_data_10; + reg [7:0] slot_data_11; + reg [7:0] slot_data_12; + reg [7:0] slot_data_13; + reg [7:0] slot_data_14; + reg [7:0] slot_data_15; + reg slot_pendingWriteback; + reg [2:0] slot_elemWidth; + reg [2:0] slot_vectorLoop_subvector_curr; + reg [2:0] slot_vectorLoop_subvector_max; + reg [3:0] slot_vectorLoop_segment_curr; + reg [3:0] slot_vectorLoop_segment_max; + reg [3:0] slot_vectorLoop_lmul_curr; + reg [3:0] slot_vectorLoop_lmul_max; + reg [4:0] slot_vectorLoop_rdStart; + reg [4:0] slot_vectorLoop_rd; + reg faultReg_valid; + reg faultReg_bits_info_write; + reg [31:0] faultReg_bits_info_addr; + reg [31:0] faultReg_bits_info_epc; + reg [4:0] faultReg_bits_rd; + reg [4:0] faultReg_bits_op; + reg faultReg_bits_store; + wire loadUpdatedSlot_lineActive_0 = slot_active_0 & (slot_addrs_0[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_1 = slot_active_1 & (slot_addrs_1[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_2 = slot_active_2 & (slot_addrs_2[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_3 = slot_active_3 & (slot_addrs_3[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_4 = slot_active_4 & (slot_addrs_4[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_5 = slot_active_5 & (slot_addrs_5[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_6 = slot_active_6 & (slot_addrs_6[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_7 = slot_active_7 & (slot_addrs_7[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_8 = slot_active_8 & (slot_addrs_8[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_9 = slot_active_9 & (slot_addrs_9[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_10 = slot_active_10 & (slot_addrs_10[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_11 = slot_active_11 & (slot_addrs_11[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_12 = slot_active_12 & (slot_addrs_12[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_13 = slot_active_13 & (slot_addrs_13[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_14 = slot_active_14 & (slot_addrs_14[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_lineActive_15 = slot_active_15 & (slot_addrs_15[31:4] == readFired_bits_lineAddr); + wire loadUpdatedSlot_active_0 = (~readFired_valid | ~loadUpdatedSlot_lineActive_0) & slot_active_0; + wire loadUpdatedSlot_active_1 = (~readFired_valid | ~loadUpdatedSlot_lineActive_1) & slot_active_1; + wire loadUpdatedSlot_active_2 = (~readFired_valid | ~loadUpdatedSlot_lineActive_2) & slot_active_2; + wire loadUpdatedSlot_active_3 = (~readFired_valid | ~loadUpdatedSlot_lineActive_3) & slot_active_3; + wire loadUpdatedSlot_active_4 = (~readFired_valid | ~loadUpdatedSlot_lineActive_4) & slot_active_4; + wire loadUpdatedSlot_active_5 = (~readFired_valid | ~loadUpdatedSlot_lineActive_5) & slot_active_5; + wire loadUpdatedSlot_active_6 = (~readFired_valid | ~loadUpdatedSlot_lineActive_6) & slot_active_6; + wire loadUpdatedSlot_active_7 = (~readFired_valid | ~loadUpdatedSlot_lineActive_7) & slot_active_7; + wire loadUpdatedSlot_active_8 = (~readFired_valid | ~loadUpdatedSlot_lineActive_8) & slot_active_8; + wire loadUpdatedSlot_active_9 = (~readFired_valid | ~loadUpdatedSlot_lineActive_9) & slot_active_9; + wire loadUpdatedSlot_active_10 = (~readFired_valid | ~loadUpdatedSlot_lineActive_10) & slot_active_10; + wire loadUpdatedSlot_active_11 = (~readFired_valid | ~loadUpdatedSlot_lineActive_11) & slot_active_11; + wire loadUpdatedSlot_active_12 = (~readFired_valid | ~loadUpdatedSlot_lineActive_12) & slot_active_12; + wire loadUpdatedSlot_active_13 = (~readFired_valid | ~loadUpdatedSlot_lineActive_13) & slot_active_13; + wire loadUpdatedSlot_active_14 = (~readFired_valid | ~loadUpdatedSlot_lineActive_14) & slot_active_14; + wire loadUpdatedSlot_active_15 = (~readFired_valid | ~loadUpdatedSlot_lineActive_15) & slot_active_15; + wire [31:0] targetAddress_bits = (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_0) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_0[31:4])) ? slot_addrs_0 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_1) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_1[31:4])) ? slot_addrs_1 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_2) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_2[31:4])) ? slot_addrs_2 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_3) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_3[31:4])) ? slot_addrs_3 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_4) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_4[31:4])) ? slot_addrs_4 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_5) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_5[31:4])) ? slot_addrs_5 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_6) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_6[31:4])) ? slot_addrs_6 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_7) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_7[31:4])) ? slot_addrs_7 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_8) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_8[31:4])) ? slot_addrs_8 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_9) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_9[31:4])) ? slot_addrs_9 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_10) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_10[31:4])) ? slot_addrs_10 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_11) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_11[31:4])) ? slot_addrs_11 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_12) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_12[31:4])) ? slot_addrs_12 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_13) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_13[31:4])) ? slot_addrs_13 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_14) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_14[31:4])) ? slot_addrs_14 : (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & loadUpdatedSlot_active_15) & (~readFired_valid | (readFired_bits_lineAddr != slot_addrs_15[31:4])) ? slot_addrs_15 : 32'h00000000)))))))))))))))); + wire [31:0] targetLineAddr = {targetAddress_bits[31:4], 4'h0}; + wire itcm = targetLineAddr < 32'h00002000; + wire dtcm = |targetAddress_bits[31:16] & (targetLineAddr < 32'h00018000); + wire peri = (targetLineAddr > 32'h0002ffff) & (targetLineAddr < 32'h00031000); + wire _writebackUpdatedSlot_result_baseAddr_T_1 = slot_op == 5'h0d; + wire _writebackUpdatedSlot_result_baseAddr_T_10 = slot_op == 5'h0e; + wire _scalarStoreComplete_T_58 = slot_op == 5'h0f; + wire _scalarStoreComplete_T_59 = slot_op == 5'h10; + wire _writebackUpdatedSlot_result_baseAddr_T_2 = slot_op == 5'h11; + wire _writebackUpdatedSlot_result_baseAddr_T_11 = slot_op == 5'h12; + wire _scalarStoreComplete_T_62 = slot_op == 5'h13; + wire _scalarStoreComplete_T_63 = slot_op == 5'h14; + wire canScatter = slot_store & (({_scalarStoreComplete_T_63, _scalarStoreComplete_T_62, _writebackUpdatedSlot_result_baseAddr_T_11, _writebackUpdatedSlot_result_baseAddr_T_2, _scalarStoreComplete_T_59, _scalarStoreComplete_T_58, _writebackUpdatedSlot_result_baseAddr_T_10, _writebackUpdatedSlot_result_baseAddr_T_1} == 8'h00) | (slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max)); + wire lineActive_0 = (canScatter & slot_active_0) & (slot_addrs_0[31:4] == targetAddress_bits[31:4]); + wire lineActive_1 = (canScatter & slot_active_1) & (slot_addrs_1[31:4] == targetAddress_bits[31:4]); + wire lineActive_2 = (canScatter & slot_active_2) & (slot_addrs_2[31:4] == targetAddress_bits[31:4]); + wire lineActive_3 = (canScatter & slot_active_3) & (slot_addrs_3[31:4] == targetAddress_bits[31:4]); + wire lineActive_4 = (canScatter & slot_active_4) & (slot_addrs_4[31:4] == targetAddress_bits[31:4]); + wire lineActive_5 = (canScatter & slot_active_5) & (slot_addrs_5[31:4] == targetAddress_bits[31:4]); + wire lineActive_6 = (canScatter & slot_active_6) & (slot_addrs_6[31:4] == targetAddress_bits[31:4]); + wire lineActive_7 = (canScatter & slot_active_7) & (slot_addrs_7[31:4] == targetAddress_bits[31:4]); + wire lineActive_8 = (canScatter & slot_active_8) & (slot_addrs_8[31:4] == targetAddress_bits[31:4]); + wire lineActive_9 = (canScatter & slot_active_9) & (slot_addrs_9[31:4] == targetAddress_bits[31:4]); + wire lineActive_10 = (canScatter & slot_active_10) & (slot_addrs_10[31:4] == targetAddress_bits[31:4]); + wire lineActive_11 = (canScatter & slot_active_11) & (slot_addrs_11[31:4] == targetAddress_bits[31:4]); + wire lineActive_12 = (canScatter & slot_active_12) & (slot_addrs_12[31:4] == targetAddress_bits[31:4]); + wire lineActive_13 = (canScatter & slot_active_13) & (slot_addrs_13[31:4] == targetAddress_bits[31:4]); + wire lineActive_14 = (canScatter & slot_active_14) & (slot_addrs_14[31:4] == targetAddress_bits[31:4]); + wire lineActive_15 = (canScatter & slot_active_15) & (slot_addrs_15[31:4] == targetAddress_bits[31:4]); + wire [15:0] valueSet_1 = (lineActive_0 ? 16'h0001 << slot_addrs_0[3:0] : 16'h0000); + wire [15:0] validMatrix_1 = (lineActive_1 ? 16'h0001 << slot_addrs_1[3:0] : 16'h0000); + wire [15:0] validMatrix_2 = (lineActive_2 ? 16'h0001 << slot_addrs_2[3:0] : 16'h0000); + wire [15:0] validMatrix_3 = (lineActive_3 ? 16'h0001 << slot_addrs_3[3:0] : 16'h0000); + wire [15:0] validMatrix_4 = (lineActive_4 ? 16'h0001 << slot_addrs_4[3:0] : 16'h0000); + wire [15:0] validMatrix_5 = (lineActive_5 ? 16'h0001 << slot_addrs_5[3:0] : 16'h0000); + wire [15:0] validMatrix_6 = (lineActive_6 ? 16'h0001 << slot_addrs_6[3:0] : 16'h0000); + wire [15:0] validMatrix_7 = (lineActive_7 ? 16'h0001 << slot_addrs_7[3:0] : 16'h0000); + wire [15:0] validMatrix_8 = (lineActive_8 ? 16'h0001 << slot_addrs_8[3:0] : 16'h0000); + wire [15:0] validMatrix_9 = (lineActive_9 ? 16'h0001 << slot_addrs_9[3:0] : 16'h0000); + wire [15:0] validMatrix_10 = (lineActive_10 ? 16'h0001 << slot_addrs_10[3:0] : 16'h0000); + wire [15:0] validMatrix_11 = (lineActive_11 ? 16'h0001 << slot_addrs_11[3:0] : 16'h0000); + wire [15:0] validMatrix_12 = (lineActive_12 ? 16'h0001 << slot_addrs_12[3:0] : 16'h0000); + wire [15:0] validMatrix_13 = (lineActive_13 ? 16'h0001 << slot_addrs_13[3:0] : 16'h0000); + wire [15:0] validMatrix_14 = (lineActive_14 ? 16'h0001 << slot_addrs_14[3:0] : 16'h0000); + wire [15:0] valueSet_2 = valueSet_1 | validMatrix_1; + wire [15:0] valueSet_3 = valueSet_2 | validMatrix_2; + wire [15:0] valueSet_4 = valueSet_3 | validMatrix_3; + wire [15:0] valueSet_5 = valueSet_4 | validMatrix_4; + wire [15:0] valueSet_6 = valueSet_5 | validMatrix_5; + wire [15:0] valueSet_7 = valueSet_6 | validMatrix_6; + wire [15:0] valueSet_8 = valueSet_7 | validMatrix_7; + wire [15:0] valueSet_9 = valueSet_8 | validMatrix_8; + wire [15:0] valueSet_10 = valueSet_9 | validMatrix_9; + wire [15:0] valueSet_11 = valueSet_10 | validMatrix_10; + wire [15:0] valueSet_12 = valueSet_11 | validMatrix_11; + wire [15:0] valueSet_13 = valueSet_12 | validMatrix_12; + wire [15:0] valueSet_14 = valueSet_13 | validMatrix_13; + wire [15:0] selectionMatrix_1 = validMatrix_1 & ~valueSet_1; + wire [15:0] selectionMatrix_2 = validMatrix_2 & ~valueSet_2; + wire [15:0] selectionMatrix_3 = validMatrix_3 & ~valueSet_3; + wire [15:0] selectionMatrix_4 = validMatrix_4 & ~valueSet_4; + wire [15:0] selectionMatrix_5 = validMatrix_5 & ~valueSet_5; + wire [15:0] selectionMatrix_6 = validMatrix_6 & ~valueSet_6; + wire [15:0] selectionMatrix_7 = validMatrix_7 & ~valueSet_7; + wire [15:0] selectionMatrix_8 = validMatrix_8 & ~valueSet_8; + wire [15:0] selectionMatrix_9 = validMatrix_9 & ~valueSet_9; + wire [15:0] selectionMatrix_10 = validMatrix_10 & ~valueSet_10; + wire [15:0] selectionMatrix_11 = validMatrix_11 & ~valueSet_11; + wire [15:0] selectionMatrix_12 = validMatrix_12 & ~valueSet_12; + wire [15:0] selectionMatrix_13 = validMatrix_13 & ~valueSet_13; + wire [15:0] selectionMatrix_14 = validMatrix_14 & ~valueSet_14; + wire [15:0] selectionMatrix_15 = (lineActive_15 ? 16'h0001 << slot_addrs_15[3:0] : 16'h0000) & ~(valueSet_14 | validMatrix_14); + wire [15:0] _resultMask_T_14 = ((((((((((((((valueSet_1 | selectionMatrix_1) | selectionMatrix_2) | selectionMatrix_3) | selectionMatrix_4) | selectionMatrix_5) | selectionMatrix_6) | selectionMatrix_7) | selectionMatrix_8) | selectionMatrix_9) | selectionMatrix_10) | selectionMatrix_11) | selectionMatrix_12) | selectionMatrix_13) | selectionMatrix_14) | selectionMatrix_15; + wire [7:0] wdata_0 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h0) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h0) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h0) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h0) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h0) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h0) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h0) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h0) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h0) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h0) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h0) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h0) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h0) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h0) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h0) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h0) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_1 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h1) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h1) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h1) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h1) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h1) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h1) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h1) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h1) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h1) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h1) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h1) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h1) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h1) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h1) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h1) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h1) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_2 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h2) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h2) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h2) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h2) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h2) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h2) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h2) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h2) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h2) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h2) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h2) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h2) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h2) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h2) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h2) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h2) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_3 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h3) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h3) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h3) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h3) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h3) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h3) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h3) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h3) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h3) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h3) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h3) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h3) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h3) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h3) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h3) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h3) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_4 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h4) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h4) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h4) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h4) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h4) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h4) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h4) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h4) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h4) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h4) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h4) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h4) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h4) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h4) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h4) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h4) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_5 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h5) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h5) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h5) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h5) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h5) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h5) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h5) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h5) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h5) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h5) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h5) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h5) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h5) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h5) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h5) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h5) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_6 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h6) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h6) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h6) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h6) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h6) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h6) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h6) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h6) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h6) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h6) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h6) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h6) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h6) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h6) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h6) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h6) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_7 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h7) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h7) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h7) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h7) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h7) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h7) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h7) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h7) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h7) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h7) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h7) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h7) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h7) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h7) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h7) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h7) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_8 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h8) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h8) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h8) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h8) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h8) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h8) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h8) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h8) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h8) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h8) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h8) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h8) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h8) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h8) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h8) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h8) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_9 = (lineActive_0 & (slot_addrs_0[3:0] == 4'h9) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'h9) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'h9) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'h9) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'h9) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'h9) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'h9) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'h9) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'h9) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'h9) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'h9) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'h9) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'h9) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'h9) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'h9) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'h9) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_10 = (lineActive_0 & (slot_addrs_0[3:0] == 4'ha) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'ha) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'ha) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'ha) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'ha) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'ha) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'ha) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'ha) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'ha) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'ha) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'ha) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'ha) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'ha) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'ha) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'ha) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'ha) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_11 = (lineActive_0 & (slot_addrs_0[3:0] == 4'hb) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'hb) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'hb) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'hb) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'hb) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'hb) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'hb) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'hb) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'hb) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'hb) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'hb) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'hb) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'hb) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'hb) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'hb) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'hb) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_12 = (lineActive_0 & (slot_addrs_0[3:0] == 4'hc) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'hc) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'hc) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'hc) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'hc) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'hc) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'hc) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'hc) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'hc) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'hc) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'hc) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'hc) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'hc) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'hc) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'hc) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'hc) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_13 = (lineActive_0 & (slot_addrs_0[3:0] == 4'hd) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'hd) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'hd) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'hd) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'hd) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'hd) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'hd) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'hd) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'hd) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'hd) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'hd) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'hd) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'hd) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'hd) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'hd) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'hd) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_14 = (lineActive_0 & (slot_addrs_0[3:0] == 4'he) ? slot_data_0 : (lineActive_1 & (slot_addrs_1[3:0] == 4'he) ? slot_data_1 : (lineActive_2 & (slot_addrs_2[3:0] == 4'he) ? slot_data_2 : (lineActive_3 & (slot_addrs_3[3:0] == 4'he) ? slot_data_3 : (lineActive_4 & (slot_addrs_4[3:0] == 4'he) ? slot_data_4 : (lineActive_5 & (slot_addrs_5[3:0] == 4'he) ? slot_data_5 : (lineActive_6 & (slot_addrs_6[3:0] == 4'he) ? slot_data_6 : (lineActive_7 & (slot_addrs_7[3:0] == 4'he) ? slot_data_7 : (lineActive_8 & (slot_addrs_8[3:0] == 4'he) ? slot_data_8 : (lineActive_9 & (slot_addrs_9[3:0] == 4'he) ? slot_data_9 : (lineActive_10 & (slot_addrs_10[3:0] == 4'he) ? slot_data_10 : (lineActive_11 & (slot_addrs_11[3:0] == 4'he) ? slot_data_11 : (lineActive_12 & (slot_addrs_12[3:0] == 4'he) ? slot_data_12 : (lineActive_13 & (slot_addrs_13[3:0] == 4'he) ? slot_data_13 : (lineActive_14 & (slot_addrs_14[3:0] == 4'he) ? slot_data_14 : (lineActive_15 & (slot_addrs_15[3:0] == 4'he) ? slot_data_15 : 8'h00)))))))))))))))); + wire [7:0] wdata_15 = (lineActive_0 & (&slot_addrs_0[3:0]) ? slot_data_0 : (lineActive_1 & (&slot_addrs_1[3:0]) ? slot_data_1 : (lineActive_2 & (&slot_addrs_2[3:0]) ? slot_data_2 : (lineActive_3 & (&slot_addrs_3[3:0]) ? slot_data_3 : (lineActive_4 & (&slot_addrs_4[3:0]) ? slot_data_4 : (lineActive_5 & (&slot_addrs_5[3:0]) ? slot_data_5 : (lineActive_6 & (&slot_addrs_6[3:0]) ? slot_data_6 : (lineActive_7 & (&slot_addrs_7[3:0]) ? slot_data_7 : (lineActive_8 & (&slot_addrs_8[3:0]) ? slot_data_8 : (lineActive_9 & (&slot_addrs_9[3:0]) ? slot_data_9 : (lineActive_10 & (&slot_addrs_10[3:0]) ? slot_data_10 : (lineActive_11 & (&slot_addrs_11[3:0]) ? slot_data_11 : (lineActive_12 & (&slot_addrs_12[3:0]) ? slot_data_12 : (lineActive_13 & (&slot_addrs_13[3:0]) ? slot_data_13 : (lineActive_14 & (&slot_addrs_14[3:0]) ? slot_data_14 : (lineActive_15 & (&slot_addrs_15[3:0]) ? slot_data_15 : 8'h00)))))))))))))))); + wire wordAligned = targetAddress_bits[1:0] == 2'h0; + wire _alignedAddress_T_1 = slot_op == 5'h03; + wire _alignedAddress_T_2 = slot_op == 5'h05; + wire [2:0] _size_T_3 = {_alignedAddress_T_2, _alignedAddress_T_1, ~(|slot_op)}; + wire _alignedAddress_T_5 = slot_op == 5'h01; + wire _alignedAddress_T_6 = slot_op == 5'h04; + wire _alignedAddress_T_7 = slot_op == 5'h06; + wire [2:0] _size_T_8 = {_alignedAddress_T_7, _alignedAddress_T_6, _alignedAddress_T_5}; + wire _alignedAddress_T_11 = slot_op == 5'h02; + wire _alignedAddress_T_12 = slot_op == 5'h07; + wire _alignedAddress_T_13 = slot_op == 5'h0c; + wire [2:0] _size_T_14 = {_alignedAddress_T_13, _alignedAddress_T_12, _alignedAddress_T_11}; + wire [7:0] _size_T_25 = {_scalarStoreComplete_T_63, _scalarStoreComplete_T_62, _writebackUpdatedSlot_result_baseAddr_T_11, _writebackUpdatedSlot_result_baseAddr_T_2, _scalarStoreComplete_T_59, _scalarStoreComplete_T_58, _writebackUpdatedSlot_result_baseAddr_T_10, _writebackUpdatedSlot_result_baseAddr_T_1}; + wire [2:0] _alignedAddress_T_3 = {_alignedAddress_T_2, _alignedAddress_T_1, ~(|slot_op)}; + wire _alignedAddress_T_10 = |{_alignedAddress_T_7, _alignedAddress_T_6, _alignedAddress_T_5} & ~targetAddress_bits[0]; + wire _alignedAddress_T_16 = |{_alignedAddress_T_13, _alignedAddress_T_12, _alignedAddress_T_11} & wordAligned; + wire _ibusFault_valid_T_3 = loadUpdatedSlot_active_0 | loadUpdatedSlot_active_1; + wire io_ibus_valid_0 = ((((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_ibusFault_valid_T_3 | loadUpdatedSlot_active_2) | loadUpdatedSlot_active_3) | loadUpdatedSlot_active_4) | loadUpdatedSlot_active_5) | loadUpdatedSlot_active_6) | loadUpdatedSlot_active_7) | loadUpdatedSlot_active_8) | loadUpdatedSlot_active_9) | loadUpdatedSlot_active_10) | loadUpdatedSlot_active_11) | loadUpdatedSlot_active_12) | loadUpdatedSlot_active_13) | loadUpdatedSlot_active_14) | loadUpdatedSlot_active_15)) & itcm) & ~slot_store) & ~faultReg_valid; + wire _io_active_T = slot_active_0 | slot_active_1; + wire io_dbus_valid_0 = (dtcm & (slot_store ? (slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15) : (slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_ibusFault_valid_T_3 | loadUpdatedSlot_active_2) | loadUpdatedSlot_active_3) | loadUpdatedSlot_active_4) | loadUpdatedSlot_active_5) | loadUpdatedSlot_active_6) | loadUpdatedSlot_active_7) | loadUpdatedSlot_active_8) | loadUpdatedSlot_active_9) | loadUpdatedSlot_active_10) | loadUpdatedSlot_active_11) | loadUpdatedSlot_active_12) | loadUpdatedSlot_active_13) | loadUpdatedSlot_active_14) | loadUpdatedSlot_active_15))) & ~faultReg_valid; + wire io_ebus_dbus_valid_0 = ((~((itcm | dtcm) | peri) | peri) & (slot_store ? (slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15) : (slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_ibusFault_valid_T_3 | loadUpdatedSlot_active_2) | loadUpdatedSlot_active_3) | loadUpdatedSlot_active_4) | loadUpdatedSlot_active_5) | loadUpdatedSlot_active_6) | loadUpdatedSlot_active_7) | loadUpdatedSlot_active_8) | loadUpdatedSlot_active_9) | loadUpdatedSlot_active_10) | loadUpdatedSlot_active_11) | loadUpdatedSlot_active_12) | loadUpdatedSlot_active_13) | loadUpdatedSlot_active_14) | loadUpdatedSlot_active_15))) & ~faultReg_valid; + wire ibusFired = io_ibus_valid_0 & io_ibus_ready; + wire ebusFired = io_ebus_dbus_valid_0 & io_ebus_dbus_ready; + wire slotFired = (ebusFired | io_dbus_valid_0) | ibusFired; + wire transactionUpdatedSlot_active_0 = (slot_store ? slot_active_0 & ~(slotFired & |valueSet_1) : loadUpdatedSlot_active_0); + wire transactionUpdatedSlot_active_1 = (slot_store ? slot_active_1 & ~(slotFired & |selectionMatrix_1) : loadUpdatedSlot_active_1); + wire transactionUpdatedSlot_active_2 = (slot_store ? slot_active_2 & ~(slotFired & |selectionMatrix_2) : loadUpdatedSlot_active_2); + wire transactionUpdatedSlot_active_3 = (slot_store ? slot_active_3 & ~(slotFired & |selectionMatrix_3) : loadUpdatedSlot_active_3); + wire transactionUpdatedSlot_active_4 = (slot_store ? slot_active_4 & ~(slotFired & |selectionMatrix_4) : loadUpdatedSlot_active_4); + wire transactionUpdatedSlot_active_5 = (slot_store ? slot_active_5 & ~(slotFired & |selectionMatrix_5) : loadUpdatedSlot_active_5); + wire transactionUpdatedSlot_active_6 = (slot_store ? slot_active_6 & ~(slotFired & |selectionMatrix_6) : loadUpdatedSlot_active_6); + wire transactionUpdatedSlot_active_7 = (slot_store ? slot_active_7 & ~(slotFired & |selectionMatrix_7) : loadUpdatedSlot_active_7); + wire transactionUpdatedSlot_active_8 = (slot_store ? slot_active_8 & ~(slotFired & |selectionMatrix_8) : loadUpdatedSlot_active_8); + wire transactionUpdatedSlot_active_9 = (slot_store ? slot_active_9 & ~(slotFired & |selectionMatrix_9) : loadUpdatedSlot_active_9); + wire transactionUpdatedSlot_active_10 = (slot_store ? slot_active_10 & ~(slotFired & |selectionMatrix_10) : loadUpdatedSlot_active_10); + wire transactionUpdatedSlot_active_11 = (slot_store ? slot_active_11 & ~(slotFired & |selectionMatrix_11) : loadUpdatedSlot_active_11); + wire transactionUpdatedSlot_active_12 = (slot_store ? slot_active_12 & ~(slotFired & |selectionMatrix_12) : loadUpdatedSlot_active_12); + wire transactionUpdatedSlot_active_13 = (slot_store ? slot_active_13 & ~(slotFired & |selectionMatrix_13) : loadUpdatedSlot_active_13); + wire transactionUpdatedSlot_active_14 = (slot_store ? slot_active_14 & ~(slotFired & |selectionMatrix_14) : loadUpdatedSlot_active_14); + wire transactionUpdatedSlot_active_15 = (slot_store ? slot_active_15 & ~(slotFired & |selectionMatrix_15) : loadUpdatedSlot_active_15); + wire io_storeComplete_valid_0 = ((((slotFired & slot_store) & ((((((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15) | slot_pendingWriteback) | (slot_vectorLoop_subvector_curr != slot_vectorLoop_subvector_max)) | (slot_vectorLoop_segment_curr != slot_vectorLoop_segment_max)) | (slot_vectorLoop_lmul_curr != slot_vectorLoop_lmul_max))) & ~(((((((((((((((((((transactionUpdatedSlot_active_0 | transactionUpdatedSlot_active_1) | transactionUpdatedSlot_active_2) | transactionUpdatedSlot_active_3) | transactionUpdatedSlot_active_4) | transactionUpdatedSlot_active_5) | transactionUpdatedSlot_active_6) | transactionUpdatedSlot_active_7) | transactionUpdatedSlot_active_8) | transactionUpdatedSlot_active_9) | transactionUpdatedSlot_active_10) | transactionUpdatedSlot_active_11) | transactionUpdatedSlot_active_12) | transactionUpdatedSlot_active_13) | transactionUpdatedSlot_active_14) | transactionUpdatedSlot_active_15) | slot_pendingWriteback) | (slot_vectorLoop_subvector_curr != slot_vectorLoop_subvector_max)) | (slot_vectorLoop_segment_curr != slot_vectorLoop_segment_max)) | (slot_vectorLoop_lmul_curr != slot_vectorLoop_lmul_max))) & ({_scalarStoreComplete_T_63, _scalarStoreComplete_T_62, _writebackUpdatedSlot_result_baseAddr_T_11, _writebackUpdatedSlot_result_baseAddr_T_2, _scalarStoreComplete_T_59, _scalarStoreComplete_T_58, _writebackUpdatedSlot_result_baseAddr_T_10, _writebackUpdatedSlot_result_baseAddr_T_1} == 8'h00)) & ~io_ebus_fault_valid; + wire [4:0] currentOp = (faultReg_valid ? faultReg_bits_op : slot_op); + wire io_rd_valid_0 = ((faultReg_valid & |{faultReg_bits_op == 5'h02, faultReg_bits_op == 5'h04, faultReg_bits_op == 5'h01, faultReg_bits_op == 5'h03, faultReg_bits_op == 5'h00}) | (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ~((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15)) & slot_pendingWriteback)) & |{currentOp == 5'h02, currentOp == 5'h04, currentOp == 5'h01, currentOp == 5'h03, currentOp == 5'h00}; + wire [31:0] io_rd_bits_data_halfSigned = {{16 {slot_data_1[7]}}, slot_data_1, slot_data_0}; + wire [31:0] io_rd_bits_data_byteSigned = {{24 {slot_data_0[7]}}, slot_data_0}; + wire [31:0] _GEN = {24'h000000, slot_data_0}; + wire [31:0] _GEN_0 = {16'h0000, slot_data_1, slot_data_0}; + wire [4:0] io_rd_bits_addr_0 = (faultReg_valid ? faultReg_bits_rd : slot_rd); + wire io_rd_flt_valid_0 = ((faultReg_valid & ~(faultReg_valid ? faultReg_bits_store : slot_store)) | (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ~((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15)) & slot_pendingWriteback)) & (currentOp == 5'h0c); + wire writebackFired = io_rd_valid_0 | io_rd_flt_valid_0; + wire [1:0] _nextSlot_T_18 = {_nextSlot_T_17, _nextSlot_T_16}; + wire _flushCmd_T_6 = _ops_T & |{_ops_T_3, _ops_T_2, flushCmd_result_fencei}; + wire _flushCmd_T_7 = flushCmd_valid & io_flush_ready; + wire [15:0] nextSlot_active = ({15'h0000, |_nextSlot_active_T_3} | (|_nextSlot_active_T_8 ? 16'h0003 : 16'h0000)) | (|_nextSlot_active_T_13 ? 16'h000f : 16'h0000); + wire [511:0] _GEN_1 = {128'h00000000000000000000000000000000, io_ebus_dbus_rdata, io_dbus_rdata, io_ibus_rdata}; + wire [127:0] readData = _GEN_1[readFired_bits_bus * 128+:128]; + wire [127:0] _GEN_2 = {readData[127:120], readData[119:112], readData[111:104], readData[103:96], readData[95:88], readData[87:80], readData[79:72], readData[71:64], readData[63:56], readData[55:48], readData[47:40], readData[39:32], readData[31:24], readData[23:16], readData[15:8], readData[7:0]}; + wire _readFired_T_1 = io_dbus_valid_0 & ~slot_store; + wire _readFired_T_3 = ebusFired & ~slot_store; + wire ibusFault_valid = (((slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_ibusFault_valid_T_3 | loadUpdatedSlot_active_2) | loadUpdatedSlot_active_3) | loadUpdatedSlot_active_4) | loadUpdatedSlot_active_5) | loadUpdatedSlot_active_6) | loadUpdatedSlot_active_7) | loadUpdatedSlot_active_8) | loadUpdatedSlot_active_9) | loadUpdatedSlot_active_10) | loadUpdatedSlot_active_11) | loadUpdatedSlot_active_12) | loadUpdatedSlot_active_13) | loadUpdatedSlot_active_14) | loadUpdatedSlot_active_15)) & itcm) & slot_store; + wire _io_active_T_18 = slot_vectorLoop_segment_curr == slot_vectorLoop_segment_max; + wire _io_active_T_21 = slot_vectorLoop_lmul_curr == slot_vectorLoop_lmul_max; + wire [3:0] _writebackUpdatedSlot_vectorLoopNext_result_rd_T_2 = slot_vectorLoop_lmul_curr + 4'h1; + wire [3:0] writebackUpdatedSlot_vectorLoopNext_result_lmul_y = (_io_active_T_21 ? 4'h0 : _writebackUpdatedSlot_vectorLoopNext_result_rd_T_2); + wire [3:0] writebackUpdatedSlot_vectorLoopNext_lmul_curr = (_io_active_T_18 ? writebackUpdatedSlot_vectorLoopNext_result_lmul_y : slot_vectorLoop_lmul_curr); + wire [4:0] writebackUpdatedSlot_vectorLoopNext_rd = (_io_active_T_18 ? slot_vectorLoop_rdStart + {1'h0, (_io_active_T_21 ? 4'h0 : _writebackUpdatedSlot_vectorLoopNext_result_rd_T_2)} : slot_vectorLoop_rd + {1'h0, slot_vectorLoop_lmul_max}); + wire writebackUpdatedSlot_finished = writebackUpdatedSlot_vectorLoopNext_lmul_curr == slot_vectorLoop_lmul_max; + wire _slotNext_T_27 = ~((((((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15) | slot_pendingWriteback) | (slot_vectorLoop_subvector_curr != slot_vectorLoop_subvector_max)) | (slot_vectorLoop_segment_curr != slot_vectorLoop_segment_max)) | (slot_vectorLoop_lmul_curr != slot_vectorLoop_lmul_max)) & |_opQueue_io_nEnqueued; + wire _slotNext_T_46 = (slot_vectorLoop_subvector_curr == slot_vectorLoop_subvector_max) & ((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15); + wire _GEN_3 = _slotNext_T_46 | ~writebackFired; + always @(posedge clock or posedge reset) + if (reset) begin + flushCmd_valid <= 1'h0; + flushCmd_bits_fencei <= 1'h0; + flushCmd_bits_pcNext <= 32'h00000000; + readFired_valid <= 1'h0; + readFired_bits_bus <= 2'h0; + readFired_bits_lineAddr <= 28'h0000000; + slot_op <= 5'h00; + slot_rd <= 5'h00; + slot_store <= 1'h0; + slot_pc <= 32'h00000000; + slot_active_0 <= 1'h0; + slot_active_1 <= 1'h0; + slot_active_2 <= 1'h0; + slot_active_3 <= 1'h0; + slot_active_4 <= 1'h0; + slot_active_5 <= 1'h0; + slot_active_6 <= 1'h0; + slot_active_7 <= 1'h0; + slot_active_8 <= 1'h0; + slot_active_9 <= 1'h0; + slot_active_10 <= 1'h0; + slot_active_11 <= 1'h0; + slot_active_12 <= 1'h0; + slot_active_13 <= 1'h0; + slot_active_14 <= 1'h0; + slot_active_15 <= 1'h0; + slot_addrs_0 <= 32'h00000000; + slot_addrs_1 <= 32'h00000000; + slot_addrs_2 <= 32'h00000000; + slot_addrs_3 <= 32'h00000000; + slot_addrs_4 <= 32'h00000000; + slot_addrs_5 <= 32'h00000000; + slot_addrs_6 <= 32'h00000000; + slot_addrs_7 <= 32'h00000000; + slot_addrs_8 <= 32'h00000000; + slot_addrs_9 <= 32'h00000000; + slot_addrs_10 <= 32'h00000000; + slot_addrs_11 <= 32'h00000000; + slot_addrs_12 <= 32'h00000000; + slot_addrs_13 <= 32'h00000000; + slot_addrs_14 <= 32'h00000000; + slot_addrs_15 <= 32'h00000000; + slot_data_0 <= 8'h00; + slot_data_1 <= 8'h00; + slot_data_2 <= 8'h00; + slot_data_3 <= 8'h00; + slot_data_4 <= 8'h00; + slot_data_5 <= 8'h00; + slot_data_6 <= 8'h00; + slot_data_7 <= 8'h00; + slot_data_8 <= 8'h00; + slot_data_9 <= 8'h00; + slot_data_10 <= 8'h00; + slot_data_11 <= 8'h00; + slot_data_12 <= 8'h00; + slot_data_13 <= 8'h00; + slot_data_14 <= 8'h00; + slot_data_15 <= 8'h00; + slot_pendingWriteback <= 1'h0; + slot_elemWidth <= 3'h0; + slot_vectorLoop_subvector_curr <= 3'h0; + slot_vectorLoop_subvector_max <= 3'h0; + slot_vectorLoop_segment_curr <= 4'h0; + slot_vectorLoop_segment_max <= 4'h0; + slot_vectorLoop_lmul_curr <= 4'h0; + slot_vectorLoop_lmul_max <= 4'h0; + slot_vectorLoop_rdStart <= 5'h00; + slot_vectorLoop_rd <= 5'h00; + faultReg_valid <= 1'h0; + faultReg_bits_info_write <= 1'h0; + faultReg_bits_info_addr <= 32'h00000000; + faultReg_bits_info_epc <= 32'h00000000; + faultReg_bits_rd <= 5'h00; + faultReg_bits_op <= 5'h00; + faultReg_bits_store <= 1'h0; + end + else begin + flushCmd_valid <= _flushCmd_T_6 | (~_flushCmd_T_7 & flushCmd_valid); + flushCmd_bits_fencei <= (_flushCmd_T_6 ? flushCmd_result_fencei : ~_flushCmd_T_7 & flushCmd_bits_fencei); + if (_flushCmd_T_6) + flushCmd_bits_pcNext <= io_req_0_bits_pc + 32'h00000004; + else if (_flushCmd_T_7) + flushCmd_bits_pcNext <= 32'h00000000; + readFired_valid <= (ibusFired | (io_dbus_valid_0 & ~slot_store)) | (ebusFired & ~slot_store); + if (ibusFired) + readFired_bits_bus <= 2'h0; + else if (_readFired_T_1) + readFired_bits_bus <= 2'h1; + else if (_readFired_T_3) + readFired_bits_bus <= 2'h2; + if ((ibusFired | _readFired_T_1) | _readFired_T_3) + readFired_bits_lineAddr <= targetAddress_bits[31:4]; + if (faultReg_valid) begin + slot_op <= 5'h00; + slot_rd <= 5'h00; + slot_pc <= 32'h00000000; + slot_addrs_0 <= 32'h00000000; + slot_addrs_1 <= 32'h00000000; + slot_addrs_2 <= 32'h00000000; + slot_addrs_3 <= 32'h00000000; + slot_addrs_4 <= 32'h00000000; + slot_addrs_5 <= 32'h00000000; + slot_addrs_6 <= 32'h00000000; + slot_addrs_7 <= 32'h00000000; + slot_addrs_8 <= 32'h00000000; + slot_addrs_9 <= 32'h00000000; + slot_addrs_10 <= 32'h00000000; + slot_addrs_11 <= 32'h00000000; + slot_addrs_12 <= 32'h00000000; + slot_addrs_13 <= 32'h00000000; + slot_addrs_14 <= 32'h00000000; + slot_addrs_15 <= 32'h00000000; + slot_data_0 <= 8'h00; + slot_data_1 <= 8'h00; + slot_data_2 <= 8'h00; + slot_data_3 <= 8'h00; + end + else if (_slotNext_T_27) begin + slot_op <= _opQueue_io_dataOut_0_op; + slot_rd <= _opQueue_io_dataOut_0_rd; + slot_pc <= _opQueue_io_dataOut_0_pc; + slot_addrs_0 <= _opQueue_io_dataOut_0_addr; + slot_addrs_1 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + _opQueue_io_dataOut_0_data : _opQueue_io_dataOut_0_addr + 32'h00000001); + slot_addrs_2 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + {_opQueue_io_dataOut_0_data[30:0], 1'h0} : _opQueue_io_dataOut_0_addr + 32'h00000002); + slot_addrs_3 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h00000003) : _opQueue_io_dataOut_0_addr + 32'h00000003); + slot_addrs_4 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + {_opQueue_io_dataOut_0_data[29:0], 2'h0} : _opQueue_io_dataOut_0_addr + 32'h00000004); + slot_addrs_5 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h00000005) : _opQueue_io_dataOut_0_addr + 32'h00000005); + slot_addrs_6 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h00000006) : _opQueue_io_dataOut_0_addr + 32'h00000006); + slot_addrs_7 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h00000007) : _opQueue_io_dataOut_0_addr + 32'h00000007); + slot_addrs_8 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + {_opQueue_io_dataOut_0_data[28:0], 3'h0} : _opQueue_io_dataOut_0_addr + 32'h00000008); + slot_addrs_9 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h00000009) : _opQueue_io_dataOut_0_addr + 32'h00000009); + slot_addrs_10 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h0000000a) : _opQueue_io_dataOut_0_addr + 32'h0000000a); + slot_addrs_11 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h0000000b) : _opQueue_io_dataOut_0_addr + 32'h0000000b); + slot_addrs_12 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h0000000c) : _opQueue_io_dataOut_0_addr + 32'h0000000c); + slot_addrs_13 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h0000000d) : _opQueue_io_dataOut_0_addr + 32'h0000000d); + slot_addrs_14 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h0000000e) : _opQueue_io_dataOut_0_addr + 32'h0000000e); + slot_addrs_15 <= (|_nextSlot_T_18 ? _opQueue_io_dataOut_0_addr + (_opQueue_io_dataOut_0_data * 32'h0000000f) : _opQueue_io_dataOut_0_addr + 32'h0000000f); + slot_data_0 <= _opQueue_io_dataOut_0_data[7:0]; + slot_data_1 <= _opQueue_io_dataOut_0_data[15:8]; + slot_data_2 <= _opQueue_io_dataOut_0_data[23:16]; + slot_data_3 <= _opQueue_io_dataOut_0_data[31:24]; + end + else begin + if (_GEN_3) + ; + else + slot_rd <= (writebackUpdatedSlot_finished ? slot_vectorLoop_rd : writebackUpdatedSlot_vectorLoopNext_rd); + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_0)) + ; + else + slot_data_0 <= _GEN_2[slot_addrs_0[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_1)) + ; + else + slot_data_1 <= _GEN_2[slot_addrs_1[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_2)) + ; + else + slot_data_2 <= _GEN_2[slot_addrs_2[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_3)) + ; + else + slot_data_3 <= _GEN_2[slot_addrs_3[3:0] * 8+:8]; + end + slot_store <= ~faultReg_valid & (_slotNext_T_27 ? _opQueue_io_dataOut_0_store : slot_store); + slot_active_0 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[0] : (_slotNext_T_46 ? transactionUpdatedSlot_active_0 : slot_active_0)); + slot_active_1 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[1] : (_slotNext_T_46 ? transactionUpdatedSlot_active_1 : slot_active_1)); + slot_active_2 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[2] : (_slotNext_T_46 ? transactionUpdatedSlot_active_2 : slot_active_2)); + slot_active_3 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[3] : (_slotNext_T_46 ? transactionUpdatedSlot_active_3 : slot_active_3)); + slot_active_4 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[4] : (_slotNext_T_46 ? transactionUpdatedSlot_active_4 : slot_active_4)); + slot_active_5 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[5] : (_slotNext_T_46 ? transactionUpdatedSlot_active_5 : slot_active_5)); + slot_active_6 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[6] : (_slotNext_T_46 ? transactionUpdatedSlot_active_6 : slot_active_6)); + slot_active_7 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[7] : (_slotNext_T_46 ? transactionUpdatedSlot_active_7 : slot_active_7)); + slot_active_8 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[8] : (_slotNext_T_46 ? transactionUpdatedSlot_active_8 : slot_active_8)); + slot_active_9 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[9] : (_slotNext_T_46 ? transactionUpdatedSlot_active_9 : slot_active_9)); + slot_active_10 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[10] : (_slotNext_T_46 ? transactionUpdatedSlot_active_10 : slot_active_10)); + slot_active_11 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[11] : (_slotNext_T_46 ? transactionUpdatedSlot_active_11 : slot_active_11)); + slot_active_12 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[12] : (_slotNext_T_46 ? transactionUpdatedSlot_active_12 : slot_active_12)); + slot_active_13 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[13] : (_slotNext_T_46 ? transactionUpdatedSlot_active_13 : slot_active_13)); + slot_active_14 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[14] : (_slotNext_T_46 ? transactionUpdatedSlot_active_14 : slot_active_14)); + slot_active_15 <= ~faultReg_valid & (_slotNext_T_27 ? nextSlot_active[15] : (_slotNext_T_46 ? transactionUpdatedSlot_active_15 : slot_active_15)); + if (faultReg_valid | _slotNext_T_27) begin + slot_data_4 <= 8'h00; + slot_data_5 <= 8'h00; + slot_data_6 <= 8'h00; + slot_data_7 <= 8'h00; + slot_data_8 <= 8'h00; + slot_data_9 <= 8'h00; + slot_data_10 <= 8'h00; + slot_data_11 <= 8'h00; + slot_data_12 <= 8'h00; + slot_data_13 <= 8'h00; + slot_data_14 <= 8'h00; + slot_data_15 <= 8'h00; + slot_elemWidth <= 3'h0; + slot_vectorLoop_subvector_curr <= 3'h0; + slot_vectorLoop_subvector_max <= 3'h0; + slot_vectorLoop_segment_curr <= 4'h0; + slot_vectorLoop_segment_max <= 4'h0; + slot_vectorLoop_lmul_curr <= 4'h0; + slot_vectorLoop_lmul_max <= 4'h0; + slot_vectorLoop_rdStart <= 5'h00; + slot_vectorLoop_rd <= 5'h00; + end + else begin + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_4)) + ; + else + slot_data_4 <= _GEN_2[slot_addrs_4[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_5)) + ; + else + slot_data_5 <= _GEN_2[slot_addrs_5[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_6)) + ; + else + slot_data_6 <= _GEN_2[slot_addrs_6[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_7)) + ; + else + slot_data_7 <= _GEN_2[slot_addrs_7[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_8)) + ; + else + slot_data_8 <= _GEN_2[slot_addrs_8[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_9)) + ; + else + slot_data_9 <= _GEN_2[slot_addrs_9[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_10)) + ; + else + slot_data_10 <= _GEN_2[slot_addrs_10[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_11)) + ; + else + slot_data_11 <= _GEN_2[slot_addrs_11[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_12)) + ; + else + slot_data_12 <= _GEN_2[slot_addrs_12[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_13)) + ; + else + slot_data_13 <= _GEN_2[slot_addrs_13[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_14)) + ; + else + slot_data_14 <= _GEN_2[slot_addrs_14[3:0] * 8+:8]; + if ((~_slotNext_T_46 | slot_store) | ~(readFired_valid & loadUpdatedSlot_lineActive_15)) + ; + else + slot_data_15 <= _GEN_2[slot_addrs_15[3:0] * 8+:8]; + if (_GEN_3) + ; + else begin + slot_vectorLoop_subvector_curr <= (writebackUpdatedSlot_finished ? slot_vectorLoop_subvector_max : 3'h0); + slot_vectorLoop_segment_curr <= (writebackUpdatedSlot_finished ? slot_vectorLoop_segment_max : (_io_active_T_18 ? 4'h0 : slot_vectorLoop_segment_curr + 4'h1)); + if (writebackUpdatedSlot_finished) + slot_vectorLoop_lmul_curr <= slot_vectorLoop_lmul_max; + else if (_io_active_T_18) + slot_vectorLoop_lmul_curr <= writebackUpdatedSlot_vectorLoopNext_result_lmul_y; + end + if ((_slotNext_T_46 | ~writebackFired) | writebackUpdatedSlot_finished) + ; + else + slot_vectorLoop_rd <= writebackUpdatedSlot_vectorLoopNext_rd; + end + slot_pendingWriteback <= ~faultReg_valid & (_slotNext_T_27 ? |{~_opQueue_io_dataOut_0_store, _nextSlot_unitStride_T_3, _nextSlot_unitStride_T_2, _nextSlot_T_17, _nextSlot_result_elemStride_T_1, _nextSlot_unitStride_T_1, _nextSlot_unitStride_T, _nextSlot_T_16, _nextSlot_result_elemStride_T} : (_GEN_3 ? slot_pendingWriteback : writebackUpdatedSlot_vectorLoopNext_lmul_curr != slot_vectorLoop_lmul_max)); + faultReg_valid <= (io_ebus_fault_valid ? io_ebus_fault_valid : ibusFault_valid); + faultReg_bits_info_write <= (io_ebus_fault_valid ? io_ebus_fault_bits_write : ibusFault_valid); + faultReg_bits_info_addr <= (io_ebus_fault_valid ? io_ebus_fault_bits_addr : (ibusFault_valid ? targetLineAddr : 32'h00000000)); + faultReg_bits_info_epc <= (io_ebus_fault_valid ? io_ebus_fault_bits_epc : (ibusFault_valid ? slot_pc : 32'h00000000)); + faultReg_bits_rd <= slot_rd; + faultReg_bits_op <= slot_op; + faultReg_bits_store <= slot_store; + end + CircularBufferMulti_1 opQueue( + .clock(clock), + .reset(reset), + .io_enqValid(opQueue_io_enqValid), + .io_enqData_0_store(_alignedOps_aligner_out_0_bits[106]), + .io_enqData_0_rd(_alignedOps_aligner_out_0_bits[105:101]), + .io_enqData_0_op(_alignedOps_aligner_out_0_bits[100:96]), + .io_enqData_0_pc(_alignedOps_aligner_out_0_bits[95:64]), + .io_enqData_0_addr(_alignedOps_aligner_out_0_bits[63:32]), + .io_enqData_0_data(_alignedOps_aligner_out_0_bits[31:0]), + .io_enqData_1_store(_alignedOps_aligner_out_1_bits[106]), + .io_enqData_1_rd(_alignedOps_aligner_out_1_bits[105:101]), + .io_enqData_1_op(_alignedOps_aligner_out_1_bits[100:96]), + .io_enqData_1_pc(_alignedOps_aligner_out_1_bits[95:64]), + .io_enqData_1_addr(_alignedOps_aligner_out_1_bits[63:32]), + .io_enqData_1_data(_alignedOps_aligner_out_1_bits[31:0]), + .io_enqData_2_store(_alignedOps_aligner_out_2_bits[106]), + .io_enqData_2_rd(_alignedOps_aligner_out_2_bits[105:101]), + .io_enqData_2_op(_alignedOps_aligner_out_2_bits[100:96]), + .io_enqData_2_pc(_alignedOps_aligner_out_2_bits[95:64]), + .io_enqData_2_addr(_alignedOps_aligner_out_2_bits[63:32]), + .io_enqData_2_data(_alignedOps_aligner_out_2_bits[31:0]), + .io_enqData_3_store(_alignedOps_aligner_out_3_bits[106]), + .io_enqData_3_rd(_alignedOps_aligner_out_3_bits[105:101]), + .io_enqData_3_op(_alignedOps_aligner_out_3_bits[100:96]), + .io_enqData_3_pc(_alignedOps_aligner_out_3_bits[95:64]), + .io_enqData_3_addr(_alignedOps_aligner_out_3_bits[63:32]), + .io_enqData_3_data(_alignedOps_aligner_out_3_bits[31:0]), + .io_nEnqueued(_opQueue_io_nEnqueued), + .io_nSpace(_opQueue_io_nSpace), + .io_dataOut_0_store(_opQueue_io_dataOut_0_store), + .io_dataOut_0_rd(_opQueue_io_dataOut_0_rd), + .io_dataOut_0_op(_opQueue_io_dataOut_0_op), + .io_dataOut_0_pc(_opQueue_io_dataOut_0_pc), + .io_dataOut_0_addr(_opQueue_io_dataOut_0_addr), + .io_dataOut_0_data(_opQueue_io_dataOut_0_data), + .io_dataOut_1_store(), + .io_dataOut_1_rd(), + .io_dataOut_1_op(), + .io_dataOut_1_pc(), + .io_dataOut_1_addr(), + .io_dataOut_1_data(), + .io_dataOut_2_store(), + .io_dataOut_2_rd(), + .io_dataOut_2_op(), + .io_dataOut_2_pc(), + .io_dataOut_2_addr(), + .io_dataOut_2_data(), + .io_dataOut_3_store(), + .io_dataOut_3_rd(), + .io_dataOut_3_op(), + .io_dataOut_3_pc(), + .io_dataOut_3_addr(), + .io_dataOut_3_data(), + .io_deqReady({2'h0, ~((((((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15) | slot_pendingWriteback) | (slot_vectorLoop_subvector_curr != slot_vectorLoop_subvector_max)) | (slot_vectorLoop_segment_curr != slot_vectorLoop_segment_max)) | (slot_vectorLoop_lmul_curr != slot_vectorLoop_lmul_max)) & |_opQueue_io_nEnqueued}), + .io_flush(1'h0) + ); + Aligner_107_4 alignedOps_aligner( + .in_0_valid(_ops_T & ({_ops_T_3, _ops_T_2, flushCmd_result_fencei} == 3'h0)), + .in_0_bits({io_req_0_bits_store, io_req_0_bits_addr, io_req_0_bits_op, io_req_0_bits_pc, io_busPort_addr_0, (io_req_0_bits_op == 5'h0c ? io_busPort_flt_data_0 : io_busPort_data_0)}), + .in_1_valid((io_req_1_ready_0 & io_req_1_valid) & ({io_req_1_bits_op == 5'h0a, io_req_1_bits_op == 5'h09, io_req_1_bits_op == 5'h08} == 3'h0)), + .in_1_bits({io_req_1_bits_store, io_req_1_bits_addr, io_req_1_bits_op, io_req_1_bits_pc, io_busPort_addr_1, (io_req_1_bits_op == 5'h0c ? 32'h00000000 : io_busPort_data_1)}), + .in_2_valid((io_req_2_ready_0 & io_req_2_valid) & ({io_req_2_bits_op == 5'h0a, io_req_2_bits_op == 5'h09, io_req_2_bits_op == 5'h08} == 3'h0)), + .in_2_bits({io_req_2_bits_store, io_req_2_bits_addr, io_req_2_bits_op, io_req_2_bits_pc, io_busPort_addr_2, (io_req_2_bits_op == 5'h0c ? 32'h00000000 : io_busPort_data_2)}), + .in_3_valid((io_req_3_ready_0 & io_req_3_valid) & ({io_req_3_bits_op == 5'h0a, io_req_3_bits_op == 5'h09, io_req_3_bits_op == 5'h08} == 3'h0)), + .in_3_bits({io_req_3_bits_store, io_req_3_bits_addr, io_req_3_bits_op, io_req_3_bits_pc, io_busPort_addr_3, (io_req_3_bits_op == 5'h0c ? 32'h00000000 : io_busPort_data_3)}), + .out_0_valid(_alignedOps_aligner_out_0_valid), + .out_0_bits(_alignedOps_aligner_out_0_bits), + .out_1_valid(_alignedOps_aligner_out_1_valid), + .out_1_bits(_alignedOps_aligner_out_1_bits), + .out_2_valid(_alignedOps_aligner_out_2_valid), + .out_2_bits(_alignedOps_aligner_out_2_bits), + .out_3_valid(_alignedOps_aligner_out_3_valid), + .out_3_bits(_alignedOps_aligner_out_3_bits) + ); + assign io_req_0_ready = io_req_0_ready_0; + assign io_req_1_ready = io_req_1_ready_0; + assign io_req_2_ready = io_req_2_ready_0; + assign io_req_3_ready = io_req_3_ready_0; + assign io_rd_valid = io_rd_valid_0; + assign io_rd_bits_addr = io_rd_bits_addr_0; + assign io_rd_bits_data = ((slot_op == 5'h0c) | (slot_op == 5'h02) ? {slot_data_3, slot_data_2, slot_data_1, slot_data_0} : (slot_op == 5'h04 ? _GEN_0 : (slot_op == 5'h01 ? io_rd_bits_data_halfSigned : (slot_op == 5'h03 ? _GEN : (|slot_op ? 32'h00000000 : io_rd_bits_data_byteSigned))))); + assign io_rd_flt_valid = io_rd_flt_valid_0; + assign io_rd_flt_bits_addr = io_rd_bits_addr_0; + assign io_rd_flt_bits_data = ((slot_op == 5'h0c) | (slot_op == 5'h02) ? {slot_data_3, slot_data_2, slot_data_1, slot_data_0} : (slot_op == 5'h04 ? _GEN_0 : (slot_op == 5'h01 ? io_rd_bits_data_halfSigned : (slot_op == 5'h03 ? _GEN : (|slot_op ? 32'h00000000 : io_rd_bits_data_byteSigned))))); + assign io_ibus_valid = io_ibus_valid_0; + assign io_ibus_addr = targetLineAddr; + assign io_dbus_valid = io_dbus_valid_0; + assign io_dbus_write = slot_store; + assign io_dbus_addr = targetLineAddr; + assign io_dbus_wdata = {wdata_15, wdata_14, wdata_13, wdata_12, wdata_11, wdata_10, wdata_9, wdata_8, wdata_7, wdata_6, wdata_5, wdata_4, wdata_3, wdata_2, wdata_1, wdata_0}; + assign io_dbus_wmask = _resultMask_T_14; + assign io_flush_valid = flushCmd_valid; + assign io_flush_fencei = flushCmd_bits_fencei; + assign io_flush_pcNext = flushCmd_bits_pcNext; + assign io_fault_valid = faultReg_valid; + assign io_fault_bits_write = faultReg_bits_info_write; + assign io_fault_bits_addr = faultReg_bits_info_addr; + assign io_fault_bits_epc = faultReg_bits_info_epc; + assign io_ebus_dbus_valid = io_ebus_dbus_valid_0; + assign io_ebus_dbus_write = slot_store; + assign io_ebus_dbus_pc = slot_pc; + assign io_ebus_dbus_addr = (((|_alignedAddress_T_3 ? targetAddress_bits : 32'h00000000) | (_alignedAddress_T_10 ? {targetAddress_bits[31:1], 1'h0} : 32'h00000000)) | (_alignedAddress_T_16 ? {targetAddress_bits[31:2], 2'h0} : 32'h00000000)) | ((|_alignedAddress_T_3 | _alignedAddress_T_10) | _alignedAddress_T_16 ? 32'h00000000 : {targetAddress_bits[31:4], 4'h0}); + assign io_ebus_dbus_size = ((({4'h0, |_size_T_3} | (|_size_T_8 ? (targetAddress_bits[0] ? 5'h10 : 5'h02) : 5'h00)) | (|_size_T_14 ? (wordAligned ? 5'h04 : 5'h10) : 5'h00)) | {|_size_T_25, 4'h0}) | {{_alignedAddress_T_2, _alignedAddress_T_1, ~(|slot_op), _alignedAddress_T_7, _alignedAddress_T_6, _alignedAddress_T_5, _alignedAddress_T_13, _alignedAddress_T_12, _alignedAddress_T_11, _scalarStoreComplete_T_63, _scalarStoreComplete_T_62, _writebackUpdatedSlot_result_baseAddr_T_11, _writebackUpdatedSlot_result_baseAddr_T_2, _scalarStoreComplete_T_59, _scalarStoreComplete_T_58, _writebackUpdatedSlot_result_baseAddr_T_10, _writebackUpdatedSlot_result_baseAddr_T_1} == 17'h00000, 4'h0}; + assign io_ebus_dbus_wdata = {wdata_15, wdata_14, wdata_13, wdata_12, wdata_11, wdata_10, wdata_9, wdata_8, wdata_7, wdata_6, wdata_5, wdata_4, wdata_3, wdata_2, wdata_1, wdata_0}; + assign io_ebus_dbus_wmask = _resultMask_T_14; + assign io_queueCapacity = _opQueue_io_nSpace; + assign io_active = |{(((((((((((((((((_io_active_T | slot_active_2) | slot_active_3) | slot_active_4) | slot_active_5) | slot_active_6) | slot_active_7) | slot_active_8) | slot_active_9) | slot_active_10) | slot_active_11) | slot_active_12) | slot_active_13) | slot_active_14) | slot_active_15) | slot_pendingWriteback) | (slot_vectorLoop_subvector_curr != slot_vectorLoop_subvector_max)) | (slot_vectorLoop_segment_curr != slot_vectorLoop_segment_max)) | (slot_vectorLoop_lmul_curr != slot_vectorLoop_lmul_max), _opQueue_io_nEnqueued}; + assign io_storeComplete_valid = io_storeComplete_valid_0; + assign io_storeComplete_bits = (io_storeComplete_valid_0 ? slot_pc : 32'h00000000); +endmodule +module FaultManager ( + io_in_fault_0_csr, + io_in_fault_0_jal, + io_in_fault_0_jalr, + io_in_fault_0_bxx, + io_in_fault_0_undef, + io_in_fault_1_jal, + io_in_fault_1_jalr, + io_in_fault_1_bxx, + io_in_fault_2_jal, + io_in_fault_2_jalr, + io_in_fault_2_bxx, + io_in_fault_3_jal, + io_in_fault_3_jalr, + io_in_fault_3_bxx, + io_in_pc_0_pc, + io_in_pc_1_pc, + io_in_pc_2_pc, + io_in_pc_3_pc, + io_in_memory_fault_valid, + io_in_memory_fault_bits_write, + io_in_memory_fault_bits_addr, + io_in_memory_fault_bits_epc, + io_in_undef_0_inst, + io_in_undef_1_inst, + io_in_undef_2_inst, + io_in_undef_3_inst, + io_in_jal_0_target, + io_in_jal_1_target, + io_in_jal_2_target, + io_in_jal_3_target, + io_in_jalr_0_target, + io_in_jalr_1_target, + io_in_jalr_2_target, + io_in_jalr_3_target, + io_in_fetchFault_valid, + io_in_fetchFault_bits, + io_out_valid, + io_out_bits_mepc, + io_out_bits_mtval, + io_out_bits_mcause, + io_out_bits_decode +); + input io_in_fault_0_csr; + input io_in_fault_0_jal; + input io_in_fault_0_jalr; + input io_in_fault_0_bxx; + input io_in_fault_0_undef; + input io_in_fault_1_jal; + input io_in_fault_1_jalr; + input io_in_fault_1_bxx; + input io_in_fault_2_jal; + input io_in_fault_2_jalr; + input io_in_fault_2_bxx; + input io_in_fault_3_jal; + input io_in_fault_3_jalr; + input io_in_fault_3_bxx; + input [31:0] io_in_pc_0_pc; + input [31:0] io_in_pc_1_pc; + input [31:0] io_in_pc_2_pc; + input [31:0] io_in_pc_3_pc; + input io_in_memory_fault_valid; + input io_in_memory_fault_bits_write; + input [31:0] io_in_memory_fault_bits_addr; + input [31:0] io_in_memory_fault_bits_epc; + input [31:0] io_in_undef_0_inst; + input [31:0] io_in_undef_1_inst; + input [31:0] io_in_undef_2_inst; + input [31:0] io_in_undef_3_inst; + input [31:0] io_in_jal_0_target; + input [31:0] io_in_jal_1_target; + input [31:0] io_in_jal_2_target; + input [31:0] io_in_jal_3_target; + input [31:0] io_in_jalr_0_target; + input [31:0] io_in_jalr_1_target; + input [31:0] io_in_jalr_2_target; + input [31:0] io_in_jalr_3_target; + input io_in_fetchFault_valid; + input [31:0] io_in_fetchFault_bits; + output wire io_out_valid; + output wire [31:0] io_out_bits_mepc; + output wire [31:0] io_out_bits_mtval; + output wire [31:0] io_out_bits_mcause; + output wire io_out_bits_decode; + wire faults_0 = (((io_in_fault_0_csr | io_in_fault_0_jal) | io_in_fault_0_jalr) | io_in_fault_0_bxx) | io_in_fault_0_undef; + wire faults_1 = (io_in_fault_1_jal | io_in_fault_1_jalr) | io_in_fault_1_bxx; + wire faults_2 = (io_in_fault_2_jal | io_in_fault_2_jalr) | io_in_fault_2_bxx; + wire fault = ((((faults_0 | faults_1) | faults_2) | io_in_fault_3_jal) | io_in_fault_3_jalr) | io_in_fault_3_bxx; + wire [1:0] first_fault = (faults_0 ? 2'h0 : (faults_1 ? 2'h1 : {1'h1, ~faults_2})); + wire [1:0] undef_fault_idx = (io_in_fault_0_undef ? 2'h0 : 2'h3); + wire [1:0] jal_fault_idx = (io_in_fault_0_jal ? 2'h0 : (io_in_fault_1_jal ? 2'h1 : {1'h1, ~io_in_fault_2_jal})); + wire [1:0] jalr_fault_idx = (io_in_fault_0_jalr ? 2'h0 : (io_in_fault_1_jalr ? 2'h1 : {1'h1, ~io_in_fault_2_jalr})); + wire load_fault = io_in_memory_fault_valid & ~io_in_memory_fault_bits_write; + wire store_fault = io_in_memory_fault_valid & io_in_memory_fault_bits_write; + wire [127:0] _GEN = {io_in_pc_3_pc, io_in_pc_2_pc, io_in_pc_1_pc, io_in_pc_0_pc}; + wire _GEN_0 = load_fault | store_fault; + wire first_fault_is_csr = io_in_fault_0_csr & ((io_in_fault_0_csr ? 2'h0 : 2'h3) == first_fault); + wire first_fault_is_jal = (((io_in_fault_0_jal | io_in_fault_1_jal) | io_in_fault_2_jal) | io_in_fault_3_jal) & (jal_fault_idx == first_fault); + wire first_fault_is_jalr = (((io_in_fault_0_jalr | io_in_fault_1_jalr) | io_in_fault_2_jalr) | io_in_fault_3_jalr) & (jalr_fault_idx == first_fault); + wire first_fault_is_bxx = (((io_in_fault_0_bxx | io_in_fault_1_bxx) | io_in_fault_2_bxx) | io_in_fault_3_bxx) & ((io_in_fault_0_bxx ? 2'h0 : (io_in_fault_1_bxx ? 2'h1 : {1'h1, ~io_in_fault_2_bxx})) == first_fault); + wire first_fault_is_undef = io_in_fault_0_undef & (undef_fault_idx == first_fault); + wire _GEN_1 = (first_fault_is_jal | first_fault_is_jalr) | first_fault_is_bxx; + wire [127:0] _GEN_2 = {io_in_jalr_3_target, io_in_jalr_2_target, io_in_jalr_1_target, io_in_jalr_0_target}; + wire [127:0] _GEN_3 = {io_in_undef_3_inst, io_in_undef_2_inst, io_in_undef_1_inst, io_in_undef_0_inst}; + wire [127:0] _GEN_4 = {io_in_jal_3_target, io_in_jal_2_target, io_in_jal_1_target, io_in_jal_0_target}; + assign io_out_valid = ((fault | io_in_fetchFault_valid) | load_fault) | store_fault; + assign io_out_bits_mepc = (_GEN_0 ? io_in_memory_fault_bits_epc : (fault ? _GEN[first_fault * 32+:32] : (io_in_fetchFault_valid ? io_in_fetchFault_bits : 32'h00000000))); + assign io_out_bits_mtval = (_GEN_0 ? io_in_memory_fault_bits_addr : (first_fault_is_csr ? 32'h00000000 : (first_fault_is_jal ? _GEN_4[jal_fault_idx * 32+:32] : (first_fault_is_jalr ? _GEN_2[jalr_fault_idx * 32+:32] & 32'hfffffffe : (first_fault_is_bxx | ~first_fault_is_undef ? 32'h00000000 : _GEN_3[undef_fault_idx * 32+:32]))))); + assign io_out_bits_mcause = (load_fault ? 32'h00000005 : (store_fault ? 32'h00000007 : (first_fault_is_csr ? 32'h00000002 : (_GEN_1 ? 32'h00000000 : (first_fault_is_undef ? 32'h00000002 : {31'h00000000, io_in_fetchFault_valid}))))); + assign io_out_bits_decode = (first_fault_is_csr | _GEN_1) | first_fault_is_undef; +endmodule +module CircularBufferMulti_2 ( + clock, + reset, + io_enqValid, + io_enqData_0_addr, + io_enqData_0_idx, + io_enqData_0_trap, + io_enqData_0_isControlFlow, + io_enqData_0_isBranch, + io_enqData_0_isVector, + io_enqData_0_linkOk, + io_enqData_0_isEcall, + io_enqData_0_isMpause, + io_enqData_1_addr, + io_enqData_1_idx, + io_enqData_1_trap, + io_enqData_1_isControlFlow, + io_enqData_1_isBranch, + io_enqData_1_isVector, + io_enqData_1_linkOk, + io_enqData_1_isEcall, + io_enqData_1_isMpause, + io_enqData_2_addr, + io_enqData_2_idx, + io_enqData_2_trap, + io_enqData_2_isControlFlow, + io_enqData_2_isBranch, + io_enqData_2_isVector, + io_enqData_2_linkOk, + io_enqData_2_isEcall, + io_enqData_2_isMpause, + io_enqData_3_addr, + io_enqData_3_idx, + io_enqData_3_trap, + io_enqData_3_isControlFlow, + io_enqData_3_isBranch, + io_enqData_3_isVector, + io_enqData_3_linkOk, + io_enqData_3_isEcall, + io_enqData_3_isMpause, + io_enqData_4_addr, + io_enqData_4_idx, + io_enqData_4_trap, + io_enqData_4_isControlFlow, + io_enqData_4_isBranch, + io_enqData_4_isVector, + io_enqData_4_linkOk, + io_enqData_4_isEcall, + io_enqData_4_isMpause, + io_enqData_5_addr, + io_enqData_5_idx, + io_enqData_5_trap, + io_enqData_5_isControlFlow, + io_enqData_5_isBranch, + io_enqData_5_isVector, + io_enqData_5_linkOk, + io_enqData_5_isEcall, + io_enqData_5_isMpause, + io_enqData_6_addr, + io_enqData_6_idx, + io_enqData_6_trap, + io_enqData_6_isControlFlow, + io_enqData_6_isBranch, + io_enqData_6_isVector, + io_enqData_6_linkOk, + io_enqData_6_isEcall, + io_enqData_6_isMpause, + io_enqData_7_addr, + io_enqData_7_idx, + io_enqData_7_trap, + io_enqData_7_isControlFlow, + io_enqData_7_isBranch, + io_enqData_7_isVector, + io_enqData_7_linkOk, + io_enqData_7_isEcall, + io_enqData_7_isMpause, + io_nEnqueued, + io_nSpace, + io_dataOut_0_addr, + io_dataOut_0_idx, + io_dataOut_0_trap, + io_dataOut_0_isControlFlow, + io_dataOut_0_isBranch, + io_dataOut_0_isVector, + io_dataOut_0_linkOk, + io_dataOut_0_isEcall, + io_dataOut_0_isMpause, + io_dataOut_1_addr, + io_dataOut_1_idx, + io_dataOut_1_trap, + io_dataOut_1_isControlFlow, + io_dataOut_1_isBranch, + io_dataOut_1_isVector, + io_dataOut_1_linkOk, + io_dataOut_1_isEcall, + io_dataOut_1_isMpause, + io_dataOut_2_addr, + io_dataOut_2_idx, + io_dataOut_2_trap, + io_dataOut_2_isControlFlow, + io_dataOut_2_isBranch, + io_dataOut_2_isVector, + io_dataOut_2_linkOk, + io_dataOut_2_isEcall, + io_dataOut_2_isMpause, + io_dataOut_3_addr, + io_dataOut_3_idx, + io_dataOut_3_trap, + io_dataOut_3_isControlFlow, + io_dataOut_3_isBranch, + io_dataOut_3_isVector, + io_dataOut_3_linkOk, + io_dataOut_3_isEcall, + io_dataOut_3_isMpause, + io_dataOut_4_addr, + io_dataOut_4_idx, + io_dataOut_4_trap, + io_dataOut_4_isControlFlow, + io_dataOut_4_isBranch, + io_dataOut_4_isVector, + io_dataOut_4_linkOk, + io_dataOut_4_isEcall, + io_dataOut_4_isMpause, + io_dataOut_5_addr, + io_dataOut_5_idx, + io_dataOut_5_trap, + io_dataOut_5_isControlFlow, + io_dataOut_5_isBranch, + io_dataOut_5_isVector, + io_dataOut_5_linkOk, + io_dataOut_5_isEcall, + io_dataOut_5_isMpause, + io_dataOut_6_addr, + io_dataOut_6_idx, + io_dataOut_6_trap, + io_dataOut_6_isControlFlow, + io_dataOut_6_isBranch, + io_dataOut_6_isVector, + io_dataOut_6_linkOk, + io_dataOut_6_isEcall, + io_dataOut_6_isMpause, + io_dataOut_7_addr, + io_dataOut_7_idx, + io_dataOut_7_trap, + io_dataOut_7_isControlFlow, + io_dataOut_7_isBranch, + io_dataOut_7_isVector, + io_dataOut_7_linkOk, + io_dataOut_7_isEcall, + io_dataOut_7_isMpause, + io_deqReady, + io_flush +); + input clock; + input reset; + input [3:0] io_enqValid; + input [31:0] io_enqData_0_addr; + input [6:0] io_enqData_0_idx; + input io_enqData_0_trap; + input io_enqData_0_isControlFlow; + input io_enqData_0_isBranch; + input io_enqData_0_isVector; + input io_enqData_0_linkOk; + input io_enqData_0_isEcall; + input io_enqData_0_isMpause; + input [31:0] io_enqData_1_addr; + input [6:0] io_enqData_1_idx; + input io_enqData_1_trap; + input io_enqData_1_isControlFlow; + input io_enqData_1_isBranch; + input io_enqData_1_isVector; + input io_enqData_1_linkOk; + input io_enqData_1_isEcall; + input io_enqData_1_isMpause; + input [31:0] io_enqData_2_addr; + input [6:0] io_enqData_2_idx; + input io_enqData_2_trap; + input io_enqData_2_isControlFlow; + input io_enqData_2_isBranch; + input io_enqData_2_isVector; + input io_enqData_2_linkOk; + input io_enqData_2_isEcall; + input io_enqData_2_isMpause; + input [31:0] io_enqData_3_addr; + input [6:0] io_enqData_3_idx; + input io_enqData_3_trap; + input io_enqData_3_isControlFlow; + input io_enqData_3_isBranch; + input io_enqData_3_isVector; + input io_enqData_3_linkOk; + input io_enqData_3_isEcall; + input io_enqData_3_isMpause; + input [31:0] io_enqData_4_addr; + input [6:0] io_enqData_4_idx; + input io_enqData_4_trap; + input io_enqData_4_isControlFlow; + input io_enqData_4_isBranch; + input io_enqData_4_isVector; + input io_enqData_4_linkOk; + input io_enqData_4_isEcall; + input io_enqData_4_isMpause; + input [31:0] io_enqData_5_addr; + input [6:0] io_enqData_5_idx; + input io_enqData_5_trap; + input io_enqData_5_isControlFlow; + input io_enqData_5_isBranch; + input io_enqData_5_isVector; + input io_enqData_5_linkOk; + input io_enqData_5_isEcall; + input io_enqData_5_isMpause; + input [31:0] io_enqData_6_addr; + input [6:0] io_enqData_6_idx; + input io_enqData_6_trap; + input io_enqData_6_isControlFlow; + input io_enqData_6_isBranch; + input io_enqData_6_isVector; + input io_enqData_6_linkOk; + input io_enqData_6_isEcall; + input io_enqData_6_isMpause; + input [31:0] io_enqData_7_addr; + input [6:0] io_enqData_7_idx; + input io_enqData_7_trap; + input io_enqData_7_isControlFlow; + input io_enqData_7_isBranch; + input io_enqData_7_isVector; + input io_enqData_7_linkOk; + input io_enqData_7_isEcall; + input io_enqData_7_isMpause; + output wire [3:0] io_nEnqueued; + output wire [3:0] io_nSpace; + output wire [31:0] io_dataOut_0_addr; + output wire [6:0] io_dataOut_0_idx; + output wire io_dataOut_0_trap; + output wire io_dataOut_0_isControlFlow; + output wire io_dataOut_0_isBranch; + output wire io_dataOut_0_isVector; + output wire io_dataOut_0_linkOk; + output wire io_dataOut_0_isEcall; + output wire io_dataOut_0_isMpause; + output wire [31:0] io_dataOut_1_addr; + output wire [6:0] io_dataOut_1_idx; + output wire io_dataOut_1_trap; + output wire io_dataOut_1_isControlFlow; + output wire io_dataOut_1_isBranch; + output wire io_dataOut_1_isVector; + output wire io_dataOut_1_linkOk; + output wire io_dataOut_1_isEcall; + output wire io_dataOut_1_isMpause; + output wire [31:0] io_dataOut_2_addr; + output wire [6:0] io_dataOut_2_idx; + output wire io_dataOut_2_trap; + output wire io_dataOut_2_isControlFlow; + output wire io_dataOut_2_isBranch; + output wire io_dataOut_2_isVector; + output wire io_dataOut_2_linkOk; + output wire io_dataOut_2_isEcall; + output wire io_dataOut_2_isMpause; + output wire [31:0] io_dataOut_3_addr; + output wire [6:0] io_dataOut_3_idx; + output wire io_dataOut_3_trap; + output wire io_dataOut_3_isControlFlow; + output wire io_dataOut_3_isBranch; + output wire io_dataOut_3_isVector; + output wire io_dataOut_3_linkOk; + output wire io_dataOut_3_isEcall; + output wire io_dataOut_3_isMpause; + output wire [31:0] io_dataOut_4_addr; + output wire [6:0] io_dataOut_4_idx; + output wire io_dataOut_4_trap; + output wire io_dataOut_4_isControlFlow; + output wire io_dataOut_4_isBranch; + output wire io_dataOut_4_isVector; + output wire io_dataOut_4_linkOk; + output wire io_dataOut_4_isEcall; + output wire io_dataOut_4_isMpause; + output wire [31:0] io_dataOut_5_addr; + output wire [6:0] io_dataOut_5_idx; + output wire io_dataOut_5_trap; + output wire io_dataOut_5_isControlFlow; + output wire io_dataOut_5_isBranch; + output wire io_dataOut_5_isVector; + output wire io_dataOut_5_linkOk; + output wire io_dataOut_5_isEcall; + output wire io_dataOut_5_isMpause; + output wire [31:0] io_dataOut_6_addr; + output wire [6:0] io_dataOut_6_idx; + output wire io_dataOut_6_trap; + output wire io_dataOut_6_isControlFlow; + output wire io_dataOut_6_isBranch; + output wire io_dataOut_6_isVector; + output wire io_dataOut_6_linkOk; + output wire io_dataOut_6_isEcall; + output wire io_dataOut_6_isMpause; + output wire [31:0] io_dataOut_7_addr; + output wire [6:0] io_dataOut_7_idx; + output wire io_dataOut_7_trap; + output wire io_dataOut_7_isControlFlow; + output wire io_dataOut_7_isBranch; + output wire io_dataOut_7_isVector; + output wire io_dataOut_7_linkOk; + output wire io_dataOut_7_isEcall; + output wire io_dataOut_7_isMpause; + input [3:0] io_deqReady; + input io_flush; + reg [31:0] buffer_0_addr; + reg [6:0] buffer_0_idx; + reg buffer_0_trap; + reg buffer_0_isControlFlow; + reg buffer_0_isBranch; + reg buffer_0_isVector; + reg buffer_0_linkOk; + reg buffer_0_isEcall; + reg buffer_0_isMpause; + reg [31:0] buffer_1_addr; + reg [6:0] buffer_1_idx; + reg buffer_1_trap; + reg buffer_1_isControlFlow; + reg buffer_1_isBranch; + reg buffer_1_isVector; + reg buffer_1_linkOk; + reg buffer_1_isEcall; + reg buffer_1_isMpause; + reg [31:0] buffer_2_addr; + reg [6:0] buffer_2_idx; + reg buffer_2_trap; + reg buffer_2_isControlFlow; + reg buffer_2_isBranch; + reg buffer_2_isVector; + reg buffer_2_linkOk; + reg buffer_2_isEcall; + reg buffer_2_isMpause; + reg [31:0] buffer_3_addr; + reg [6:0] buffer_3_idx; + reg buffer_3_trap; + reg buffer_3_isControlFlow; + reg buffer_3_isBranch; + reg buffer_3_isVector; + reg buffer_3_linkOk; + reg buffer_3_isEcall; + reg buffer_3_isMpause; + reg [31:0] buffer_4_addr; + reg [6:0] buffer_4_idx; + reg buffer_4_trap; + reg buffer_4_isControlFlow; + reg buffer_4_isBranch; + reg buffer_4_isVector; + reg buffer_4_linkOk; + reg buffer_4_isEcall; + reg buffer_4_isMpause; + reg [31:0] buffer_5_addr; + reg [6:0] buffer_5_idx; + reg buffer_5_trap; + reg buffer_5_isControlFlow; + reg buffer_5_isBranch; + reg buffer_5_isVector; + reg buffer_5_linkOk; + reg buffer_5_isEcall; + reg buffer_5_isMpause; + reg [31:0] buffer_6_addr; + reg [6:0] buffer_6_idx; + reg buffer_6_trap; + reg buffer_6_isControlFlow; + reg buffer_6_isBranch; + reg buffer_6_isVector; + reg buffer_6_linkOk; + reg buffer_6_isEcall; + reg buffer_6_isMpause; + reg [31:0] buffer_7_addr; + reg [6:0] buffer_7_idx; + reg buffer_7_trap; + reg buffer_7_isControlFlow; + reg buffer_7_isBranch; + reg buffer_7_isVector; + reg buffer_7_linkOk; + reg buffer_7_isEcall; + reg buffer_7_isMpause; + reg [2:0] enqPtr; + reg [2:0] deqPtr; + reg [3:0] nEnqueued; + wire [8:0] _outputBufferView_rotated_T_9 = {6'h00, deqPtr} * 9'h02e; + wire [367:0] _outputBufferView_rotated_T_22 = (_outputBufferView_rotated_T_9[0] ? {buffer_0_isMpause, buffer_7_addr, buffer_7_idx, buffer_7_trap, buffer_7_isControlFlow, buffer_7_isBranch, buffer_7_isVector, buffer_7_linkOk, buffer_7_isEcall, buffer_7_isMpause, buffer_6_addr, buffer_6_idx, buffer_6_trap, buffer_6_isControlFlow, buffer_6_isBranch, buffer_6_isVector, buffer_6_linkOk, buffer_6_isEcall, buffer_6_isMpause, buffer_5_addr, buffer_5_idx, buffer_5_trap, buffer_5_isControlFlow, buffer_5_isBranch, buffer_5_isVector, buffer_5_linkOk, buffer_5_isEcall, buffer_5_isMpause, buffer_4_addr, buffer_4_idx, buffer_4_trap, buffer_4_isControlFlow, buffer_4_isBranch, buffer_4_isVector, buffer_4_linkOk, buffer_4_isEcall, buffer_4_isMpause, buffer_3_addr, buffer_3_idx, buffer_3_trap, buffer_3_isControlFlow, buffer_3_isBranch, buffer_3_isVector, buffer_3_linkOk, buffer_3_isEcall, buffer_3_isMpause, buffer_2_addr, buffer_2_idx, buffer_2_trap, buffer_2_isControlFlow, buffer_2_isBranch, buffer_2_isVector, buffer_2_linkOk, buffer_2_isEcall, buffer_2_isMpause, buffer_1_addr, buffer_1_idx, buffer_1_trap, buffer_1_isControlFlow, buffer_1_isBranch, buffer_1_isVector, buffer_1_linkOk, buffer_1_isEcall, buffer_1_isMpause, buffer_0_addr, buffer_0_idx, buffer_0_trap, buffer_0_isControlFlow, buffer_0_isBranch, buffer_0_isVector, buffer_0_linkOk, buffer_0_isEcall} : {buffer_7_addr, buffer_7_idx, buffer_7_trap, buffer_7_isControlFlow, buffer_7_isBranch, buffer_7_isVector, buffer_7_linkOk, buffer_7_isEcall, buffer_7_isMpause, buffer_6_addr, buffer_6_idx, buffer_6_trap, buffer_6_isControlFlow, buffer_6_isBranch, buffer_6_isVector, buffer_6_linkOk, buffer_6_isEcall, buffer_6_isMpause, buffer_5_addr, buffer_5_idx, buffer_5_trap, buffer_5_isControlFlow, buffer_5_isBranch, buffer_5_isVector, buffer_5_linkOk, buffer_5_isEcall, buffer_5_isMpause, buffer_4_addr, buffer_4_idx, buffer_4_trap, buffer_4_isControlFlow, buffer_4_isBranch, buffer_4_isVector, buffer_4_linkOk, buffer_4_isEcall, buffer_4_isMpause, buffer_3_addr, buffer_3_idx, buffer_3_trap, buffer_3_isControlFlow, buffer_3_isBranch, buffer_3_isVector, buffer_3_linkOk, buffer_3_isEcall, buffer_3_isMpause, buffer_2_addr, buffer_2_idx, buffer_2_trap, buffer_2_isControlFlow, buffer_2_isBranch, buffer_2_isVector, buffer_2_linkOk, buffer_2_isEcall, buffer_2_isMpause, buffer_1_addr, buffer_1_idx, buffer_1_trap, buffer_1_isControlFlow, buffer_1_isBranch, buffer_1_isVector, buffer_1_linkOk, buffer_1_isEcall, buffer_1_isMpause, buffer_0_addr, buffer_0_idx, buffer_0_trap, buffer_0_isControlFlow, buffer_0_isBranch, buffer_0_isVector, buffer_0_linkOk, buffer_0_isEcall, buffer_0_isMpause}); + wire [367:0] _outputBufferView_rotated_T_26 = (_outputBufferView_rotated_T_9[1] ? {_outputBufferView_rotated_T_22[1:0], _outputBufferView_rotated_T_22[367:2]} : _outputBufferView_rotated_T_22); + wire [367:0] _outputBufferView_rotated_T_30 = (_outputBufferView_rotated_T_9[2] ? {_outputBufferView_rotated_T_26[3:0], _outputBufferView_rotated_T_26[367:4]} : _outputBufferView_rotated_T_26); + wire [367:0] _outputBufferView_rotated_T_34 = (_outputBufferView_rotated_T_9[3] ? {_outputBufferView_rotated_T_30[7:0], _outputBufferView_rotated_T_30[367:8]} : _outputBufferView_rotated_T_30); + wire [367:0] _outputBufferView_rotated_T_38 = (_outputBufferView_rotated_T_9[4] ? {_outputBufferView_rotated_T_34[15:0], _outputBufferView_rotated_T_34[367:16]} : _outputBufferView_rotated_T_34); + wire [367:0] _outputBufferView_rotated_T_42 = (_outputBufferView_rotated_T_9[5] ? {_outputBufferView_rotated_T_38[31:0], _outputBufferView_rotated_T_38[367:32]} : _outputBufferView_rotated_T_38); + wire [367:0] _outputBufferView_rotated_T_46 = (_outputBufferView_rotated_T_9[6] ? {_outputBufferView_rotated_T_42[63:0], _outputBufferView_rotated_T_42[367:64]} : _outputBufferView_rotated_T_42); + wire [367:0] _outputBufferView_rotated_T_50 = (_outputBufferView_rotated_T_9[7] ? {_outputBufferView_rotated_T_46[127:0], _outputBufferView_rotated_T_46[367:128]} : _outputBufferView_rotated_T_46); + wire [367:0] outputBufferView_rotated = (_outputBufferView_rotated_T_9[8] ? {_outputBufferView_rotated_T_50[255:0], _outputBufferView_rotated_T_50[367:256]} : _outputBufferView_rotated_T_50); + wire expandedInput_2_ret_valid = io_enqValid > 4'h2; + wire expandedInput_4_ret_valid = io_enqValid > 4'h4; + wire expandedInput_5_ret_valid = io_enqValid > 4'h5; + wire expandedInput_6_ret_valid = io_enqValid > 4'h6; + wire [8:0] _rotatedInput_rotated_T_17 = {6'h00, enqPtr} * 9'h02f; + wire [375:0] _rotatedInput_rotated_T_30 = (_rotatedInput_rotated_T_17[0] ? {io_enqData_7_addr, io_enqData_7_idx, io_enqData_7_trap, io_enqData_7_isControlFlow, io_enqData_7_isBranch, io_enqData_7_isVector, io_enqData_7_linkOk, io_enqData_7_isEcall, io_enqData_7_isMpause, expandedInput_6_ret_valid, io_enqData_6_addr, io_enqData_6_idx, io_enqData_6_trap, io_enqData_6_isControlFlow, io_enqData_6_isBranch, io_enqData_6_isVector, io_enqData_6_linkOk, io_enqData_6_isEcall, io_enqData_6_isMpause, expandedInput_5_ret_valid, io_enqData_5_addr, io_enqData_5_idx, io_enqData_5_trap, io_enqData_5_isControlFlow, io_enqData_5_isBranch, io_enqData_5_isVector, io_enqData_5_linkOk, io_enqData_5_isEcall, io_enqData_5_isMpause, expandedInput_4_ret_valid, io_enqData_4_addr, io_enqData_4_idx, io_enqData_4_trap, io_enqData_4_isControlFlow, io_enqData_4_isBranch, io_enqData_4_isVector, io_enqData_4_linkOk, io_enqData_4_isEcall, io_enqData_4_isMpause, |io_enqValid[3:2], io_enqData_3_addr, io_enqData_3_idx, io_enqData_3_trap, io_enqData_3_isControlFlow, io_enqData_3_isBranch, io_enqData_3_isVector, io_enqData_3_linkOk, io_enqData_3_isEcall, io_enqData_3_isMpause, expandedInput_2_ret_valid, io_enqData_2_addr, io_enqData_2_idx, io_enqData_2_trap, io_enqData_2_isControlFlow, io_enqData_2_isBranch, io_enqData_2_isVector, io_enqData_2_linkOk, io_enqData_2_isEcall, io_enqData_2_isMpause, |io_enqValid[3:1], io_enqData_1_addr, io_enqData_1_idx, io_enqData_1_trap, io_enqData_1_isControlFlow, io_enqData_1_isBranch, io_enqData_1_isVector, io_enqData_1_linkOk, io_enqData_1_isEcall, io_enqData_1_isMpause, |io_enqValid, io_enqData_0_addr, io_enqData_0_idx, io_enqData_0_trap, io_enqData_0_isControlFlow, io_enqData_0_isBranch, io_enqData_0_isVector, io_enqData_0_linkOk, io_enqData_0_isEcall, io_enqData_0_isMpause, io_enqValid[3]} : {io_enqValid[3], io_enqData_7_addr, io_enqData_7_idx, io_enqData_7_trap, io_enqData_7_isControlFlow, io_enqData_7_isBranch, io_enqData_7_isVector, io_enqData_7_linkOk, io_enqData_7_isEcall, io_enqData_7_isMpause, expandedInput_6_ret_valid, io_enqData_6_addr, io_enqData_6_idx, io_enqData_6_trap, io_enqData_6_isControlFlow, io_enqData_6_isBranch, io_enqData_6_isVector, io_enqData_6_linkOk, io_enqData_6_isEcall, io_enqData_6_isMpause, expandedInput_5_ret_valid, io_enqData_5_addr, io_enqData_5_idx, io_enqData_5_trap, io_enqData_5_isControlFlow, io_enqData_5_isBranch, io_enqData_5_isVector, io_enqData_5_linkOk, io_enqData_5_isEcall, io_enqData_5_isMpause, expandedInput_4_ret_valid, io_enqData_4_addr, io_enqData_4_idx, io_enqData_4_trap, io_enqData_4_isControlFlow, io_enqData_4_isBranch, io_enqData_4_isVector, io_enqData_4_linkOk, io_enqData_4_isEcall, io_enqData_4_isMpause, |io_enqValid[3:2], io_enqData_3_addr, io_enqData_3_idx, io_enqData_3_trap, io_enqData_3_isControlFlow, io_enqData_3_isBranch, io_enqData_3_isVector, io_enqData_3_linkOk, io_enqData_3_isEcall, io_enqData_3_isMpause, expandedInput_2_ret_valid, io_enqData_2_addr, io_enqData_2_idx, io_enqData_2_trap, io_enqData_2_isControlFlow, io_enqData_2_isBranch, io_enqData_2_isVector, io_enqData_2_linkOk, io_enqData_2_isEcall, io_enqData_2_isMpause, |io_enqValid[3:1], io_enqData_1_addr, io_enqData_1_idx, io_enqData_1_trap, io_enqData_1_isControlFlow, io_enqData_1_isBranch, io_enqData_1_isVector, io_enqData_1_linkOk, io_enqData_1_isEcall, io_enqData_1_isMpause, |io_enqValid, io_enqData_0_addr, io_enqData_0_idx, io_enqData_0_trap, io_enqData_0_isControlFlow, io_enqData_0_isBranch, io_enqData_0_isVector, io_enqData_0_linkOk, io_enqData_0_isEcall, io_enqData_0_isMpause}); + wire [375:0] _rotatedInput_rotated_T_34 = (_rotatedInput_rotated_T_17[1] ? {_rotatedInput_rotated_T_30[373:0], _rotatedInput_rotated_T_30[375:374]} : _rotatedInput_rotated_T_30); + wire [375:0] _rotatedInput_rotated_T_38 = (_rotatedInput_rotated_T_17[2] ? {_rotatedInput_rotated_T_34[371:0], _rotatedInput_rotated_T_34[375:372]} : _rotatedInput_rotated_T_34); + wire [375:0] _rotatedInput_rotated_T_42 = (_rotatedInput_rotated_T_17[3] ? {_rotatedInput_rotated_T_38[367:0], _rotatedInput_rotated_T_38[375:368]} : _rotatedInput_rotated_T_38); + wire [375:0] _rotatedInput_rotated_T_46 = (_rotatedInput_rotated_T_17[4] ? {_rotatedInput_rotated_T_42[359:0], _rotatedInput_rotated_T_42[375:360]} : _rotatedInput_rotated_T_42); + wire [375:0] _rotatedInput_rotated_T_50 = (_rotatedInput_rotated_T_17[5] ? {_rotatedInput_rotated_T_46[343:0], _rotatedInput_rotated_T_46[375:344]} : _rotatedInput_rotated_T_46); + wire [375:0] _rotatedInput_rotated_T_54 = (_rotatedInput_rotated_T_17[6] ? {_rotatedInput_rotated_T_50[311:0], _rotatedInput_rotated_T_50[375:312]} : _rotatedInput_rotated_T_50); + wire [375:0] _rotatedInput_rotated_T_58 = (_rotatedInput_rotated_T_17[7] ? {_rotatedInput_rotated_T_54[247:0], _rotatedInput_rotated_T_54[375:248]} : _rotatedInput_rotated_T_54); + wire [375:0] rotatedInput_rotated = (_rotatedInput_rotated_T_17[8] ? {_rotatedInput_rotated_T_58[119:0], _rotatedInput_rotated_T_58[375:120]} : _rotatedInput_rotated_T_58); + always @(posedge clock or posedge reset) + if (reset) begin + buffer_0_addr <= 32'h00000000; + buffer_0_idx <= 7'h00; + buffer_0_trap <= 1'h0; + buffer_0_isControlFlow <= 1'h0; + buffer_0_isBranch <= 1'h0; + buffer_0_isVector <= 1'h0; + buffer_0_linkOk <= 1'h0; + buffer_0_isEcall <= 1'h0; + buffer_0_isMpause <= 1'h0; + buffer_1_addr <= 32'h00000000; + buffer_1_idx <= 7'h00; + buffer_1_trap <= 1'h0; + buffer_1_isControlFlow <= 1'h0; + buffer_1_isBranch <= 1'h0; + buffer_1_isVector <= 1'h0; + buffer_1_linkOk <= 1'h0; + buffer_1_isEcall <= 1'h0; + buffer_1_isMpause <= 1'h0; + buffer_2_addr <= 32'h00000000; + buffer_2_idx <= 7'h00; + buffer_2_trap <= 1'h0; + buffer_2_isControlFlow <= 1'h0; + buffer_2_isBranch <= 1'h0; + buffer_2_isVector <= 1'h0; + buffer_2_linkOk <= 1'h0; + buffer_2_isEcall <= 1'h0; + buffer_2_isMpause <= 1'h0; + buffer_3_addr <= 32'h00000000; + buffer_3_idx <= 7'h00; + buffer_3_trap <= 1'h0; + buffer_3_isControlFlow <= 1'h0; + buffer_3_isBranch <= 1'h0; + buffer_3_isVector <= 1'h0; + buffer_3_linkOk <= 1'h0; + buffer_3_isEcall <= 1'h0; + buffer_3_isMpause <= 1'h0; + buffer_4_addr <= 32'h00000000; + buffer_4_idx <= 7'h00; + buffer_4_trap <= 1'h0; + buffer_4_isControlFlow <= 1'h0; + buffer_4_isBranch <= 1'h0; + buffer_4_isVector <= 1'h0; + buffer_4_linkOk <= 1'h0; + buffer_4_isEcall <= 1'h0; + buffer_4_isMpause <= 1'h0; + buffer_5_addr <= 32'h00000000; + buffer_5_idx <= 7'h00; + buffer_5_trap <= 1'h0; + buffer_5_isControlFlow <= 1'h0; + buffer_5_isBranch <= 1'h0; + buffer_5_isVector <= 1'h0; + buffer_5_linkOk <= 1'h0; + buffer_5_isEcall <= 1'h0; + buffer_5_isMpause <= 1'h0; + buffer_6_addr <= 32'h00000000; + buffer_6_idx <= 7'h00; + buffer_6_trap <= 1'h0; + buffer_6_isControlFlow <= 1'h0; + buffer_6_isBranch <= 1'h0; + buffer_6_isVector <= 1'h0; + buffer_6_linkOk <= 1'h0; + buffer_6_isEcall <= 1'h0; + buffer_6_isMpause <= 1'h0; + buffer_7_addr <= 32'h00000000; + buffer_7_idx <= 7'h00; + buffer_7_trap <= 1'h0; + buffer_7_isControlFlow <= 1'h0; + buffer_7_isBranch <= 1'h0; + buffer_7_isVector <= 1'h0; + buffer_7_linkOk <= 1'h0; + buffer_7_isEcall <= 1'h0; + buffer_7_isMpause <= 1'h0; + enqPtr <= 3'h0; + deqPtr <= 3'h0; + nEnqueued <= 4'h0; + end + else begin + if (rotatedInput_rotated[46]) begin + buffer_0_addr <= rotatedInput_rotated[45:14]; + buffer_0_idx <= rotatedInput_rotated[13:7]; + buffer_0_trap <= rotatedInput_rotated[6]; + buffer_0_isControlFlow <= rotatedInput_rotated[5]; + buffer_0_isBranch <= rotatedInput_rotated[4]; + buffer_0_isVector <= rotatedInput_rotated[3]; + buffer_0_linkOk <= rotatedInput_rotated[2]; + buffer_0_isEcall <= rotatedInput_rotated[1]; + buffer_0_isMpause <= rotatedInput_rotated[0]; + end + if (rotatedInput_rotated[93]) begin + buffer_1_addr <= rotatedInput_rotated[92:61]; + buffer_1_idx <= rotatedInput_rotated[60:54]; + buffer_1_trap <= rotatedInput_rotated[53]; + buffer_1_isControlFlow <= rotatedInput_rotated[52]; + buffer_1_isBranch <= rotatedInput_rotated[51]; + buffer_1_isVector <= rotatedInput_rotated[50]; + buffer_1_linkOk <= rotatedInput_rotated[49]; + buffer_1_isEcall <= rotatedInput_rotated[48]; + buffer_1_isMpause <= rotatedInput_rotated[47]; + end + if (rotatedInput_rotated[140]) begin + buffer_2_addr <= rotatedInput_rotated[139:108]; + buffer_2_idx <= rotatedInput_rotated[107:101]; + buffer_2_trap <= rotatedInput_rotated[100]; + buffer_2_isControlFlow <= rotatedInput_rotated[99]; + buffer_2_isBranch <= rotatedInput_rotated[98]; + buffer_2_isVector <= rotatedInput_rotated[97]; + buffer_2_linkOk <= rotatedInput_rotated[96]; + buffer_2_isEcall <= rotatedInput_rotated[95]; + buffer_2_isMpause <= rotatedInput_rotated[94]; + end + if (rotatedInput_rotated[187]) begin + buffer_3_addr <= rotatedInput_rotated[186:155]; + buffer_3_idx <= rotatedInput_rotated[154:148]; + buffer_3_trap <= rotatedInput_rotated[147]; + buffer_3_isControlFlow <= rotatedInput_rotated[146]; + buffer_3_isBranch <= rotatedInput_rotated[145]; + buffer_3_isVector <= rotatedInput_rotated[144]; + buffer_3_linkOk <= rotatedInput_rotated[143]; + buffer_3_isEcall <= rotatedInput_rotated[142]; + buffer_3_isMpause <= rotatedInput_rotated[141]; + end + if (rotatedInput_rotated[234]) begin + buffer_4_addr <= rotatedInput_rotated[233:202]; + buffer_4_idx <= rotatedInput_rotated[201:195]; + buffer_4_trap <= rotatedInput_rotated[194]; + buffer_4_isControlFlow <= rotatedInput_rotated[193]; + buffer_4_isBranch <= rotatedInput_rotated[192]; + buffer_4_isVector <= rotatedInput_rotated[191]; + buffer_4_linkOk <= rotatedInput_rotated[190]; + buffer_4_isEcall <= rotatedInput_rotated[189]; + buffer_4_isMpause <= rotatedInput_rotated[188]; + end + if (rotatedInput_rotated[281]) begin + buffer_5_addr <= rotatedInput_rotated[280:249]; + buffer_5_idx <= rotatedInput_rotated[248:242]; + buffer_5_trap <= rotatedInput_rotated[241]; + buffer_5_isControlFlow <= rotatedInput_rotated[240]; + buffer_5_isBranch <= rotatedInput_rotated[239]; + buffer_5_isVector <= rotatedInput_rotated[238]; + buffer_5_linkOk <= rotatedInput_rotated[237]; + buffer_5_isEcall <= rotatedInput_rotated[236]; + buffer_5_isMpause <= rotatedInput_rotated[235]; + end + if (rotatedInput_rotated[328]) begin + buffer_6_addr <= rotatedInput_rotated[327:296]; + buffer_6_idx <= rotatedInput_rotated[295:289]; + buffer_6_trap <= rotatedInput_rotated[288]; + buffer_6_isControlFlow <= rotatedInput_rotated[287]; + buffer_6_isBranch <= rotatedInput_rotated[286]; + buffer_6_isVector <= rotatedInput_rotated[285]; + buffer_6_linkOk <= rotatedInput_rotated[284]; + buffer_6_isEcall <= rotatedInput_rotated[283]; + buffer_6_isMpause <= rotatedInput_rotated[282]; + end + if (rotatedInput_rotated[375]) begin + buffer_7_addr <= rotatedInput_rotated[374:343]; + buffer_7_idx <= rotatedInput_rotated[342:336]; + buffer_7_trap <= rotatedInput_rotated[335]; + buffer_7_isControlFlow <= rotatedInput_rotated[334]; + buffer_7_isBranch <= rotatedInput_rotated[333]; + buffer_7_isVector <= rotatedInput_rotated[332]; + buffer_7_linkOk <= rotatedInput_rotated[331]; + buffer_7_isEcall <= rotatedInput_rotated[330]; + buffer_7_isMpause <= rotatedInput_rotated[329]; + end + enqPtr <= (io_flush ? 3'h0 : enqPtr + io_enqValid[2:0]); + deqPtr <= (io_flush ? 3'h0 : deqPtr + io_deqReady[2:0]); + nEnqueued <= (io_flush ? 4'h0 : (nEnqueued + io_enqValid) - io_deqReady); + end + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 4'h8 - nEnqueued; + assign io_dataOut_0_addr = outputBufferView_rotated[45:14]; + assign io_dataOut_0_idx = outputBufferView_rotated[13:7]; + assign io_dataOut_0_trap = outputBufferView_rotated[6]; + assign io_dataOut_0_isControlFlow = outputBufferView_rotated[5]; + assign io_dataOut_0_isBranch = outputBufferView_rotated[4]; + assign io_dataOut_0_isVector = outputBufferView_rotated[3]; + assign io_dataOut_0_linkOk = outputBufferView_rotated[2]; + assign io_dataOut_0_isEcall = outputBufferView_rotated[1]; + assign io_dataOut_0_isMpause = outputBufferView_rotated[0]; + assign io_dataOut_1_addr = outputBufferView_rotated[91:60]; + assign io_dataOut_1_idx = outputBufferView_rotated[59:53]; + assign io_dataOut_1_trap = outputBufferView_rotated[52]; + assign io_dataOut_1_isControlFlow = outputBufferView_rotated[51]; + assign io_dataOut_1_isBranch = outputBufferView_rotated[50]; + assign io_dataOut_1_isVector = outputBufferView_rotated[49]; + assign io_dataOut_1_linkOk = outputBufferView_rotated[48]; + assign io_dataOut_1_isEcall = outputBufferView_rotated[47]; + assign io_dataOut_1_isMpause = outputBufferView_rotated[46]; + assign io_dataOut_2_addr = outputBufferView_rotated[137:106]; + assign io_dataOut_2_idx = outputBufferView_rotated[105:99]; + assign io_dataOut_2_trap = outputBufferView_rotated[98]; + assign io_dataOut_2_isControlFlow = outputBufferView_rotated[97]; + assign io_dataOut_2_isBranch = outputBufferView_rotated[96]; + assign io_dataOut_2_isVector = outputBufferView_rotated[95]; + assign io_dataOut_2_linkOk = outputBufferView_rotated[94]; + assign io_dataOut_2_isEcall = outputBufferView_rotated[93]; + assign io_dataOut_2_isMpause = outputBufferView_rotated[92]; + assign io_dataOut_3_addr = outputBufferView_rotated[183:152]; + assign io_dataOut_3_idx = outputBufferView_rotated[151:145]; + assign io_dataOut_3_trap = outputBufferView_rotated[144]; + assign io_dataOut_3_isControlFlow = outputBufferView_rotated[143]; + assign io_dataOut_3_isBranch = outputBufferView_rotated[142]; + assign io_dataOut_3_isVector = outputBufferView_rotated[141]; + assign io_dataOut_3_linkOk = outputBufferView_rotated[140]; + assign io_dataOut_3_isEcall = outputBufferView_rotated[139]; + assign io_dataOut_3_isMpause = outputBufferView_rotated[138]; + assign io_dataOut_4_addr = outputBufferView_rotated[229:198]; + assign io_dataOut_4_idx = outputBufferView_rotated[197:191]; + assign io_dataOut_4_trap = outputBufferView_rotated[190]; + assign io_dataOut_4_isControlFlow = outputBufferView_rotated[189]; + assign io_dataOut_4_isBranch = outputBufferView_rotated[188]; + assign io_dataOut_4_isVector = outputBufferView_rotated[187]; + assign io_dataOut_4_linkOk = outputBufferView_rotated[186]; + assign io_dataOut_4_isEcall = outputBufferView_rotated[185]; + assign io_dataOut_4_isMpause = outputBufferView_rotated[184]; + assign io_dataOut_5_addr = outputBufferView_rotated[275:244]; + assign io_dataOut_5_idx = outputBufferView_rotated[243:237]; + assign io_dataOut_5_trap = outputBufferView_rotated[236]; + assign io_dataOut_5_isControlFlow = outputBufferView_rotated[235]; + assign io_dataOut_5_isBranch = outputBufferView_rotated[234]; + assign io_dataOut_5_isVector = outputBufferView_rotated[233]; + assign io_dataOut_5_linkOk = outputBufferView_rotated[232]; + assign io_dataOut_5_isEcall = outputBufferView_rotated[231]; + assign io_dataOut_5_isMpause = outputBufferView_rotated[230]; + assign io_dataOut_6_addr = outputBufferView_rotated[321:290]; + assign io_dataOut_6_idx = outputBufferView_rotated[289:283]; + assign io_dataOut_6_trap = outputBufferView_rotated[282]; + assign io_dataOut_6_isControlFlow = outputBufferView_rotated[281]; + assign io_dataOut_6_isBranch = outputBufferView_rotated[280]; + assign io_dataOut_6_isVector = outputBufferView_rotated[279]; + assign io_dataOut_6_linkOk = outputBufferView_rotated[278]; + assign io_dataOut_6_isEcall = outputBufferView_rotated[277]; + assign io_dataOut_6_isMpause = outputBufferView_rotated[276]; + assign io_dataOut_7_addr = outputBufferView_rotated[367:336]; + assign io_dataOut_7_idx = outputBufferView_rotated[335:329]; + assign io_dataOut_7_trap = outputBufferView_rotated[328]; + assign io_dataOut_7_isControlFlow = outputBufferView_rotated[327]; + assign io_dataOut_7_isBranch = outputBufferView_rotated[326]; + assign io_dataOut_7_isVector = outputBufferView_rotated[325]; + assign io_dataOut_7_linkOk = outputBufferView_rotated[324]; + assign io_dataOut_7_isEcall = outputBufferView_rotated[323]; + assign io_dataOut_7_isMpause = outputBufferView_rotated[322]; +endmodule +module RetirementBuffer ( + clock, + reset, + io_inst_0_ready, + io_inst_0_valid, + io_inst_0_bits_addr, + io_inst_0_bits_inst, + io_inst_1_ready, + io_inst_1_valid, + io_inst_1_bits_addr, + io_inst_1_bits_inst, + io_inst_2_ready, + io_inst_2_valid, + io_inst_2_bits_addr, + io_inst_2_bits_inst, + io_inst_3_ready, + io_inst_3_valid, + io_inst_3_bits_addr, + io_inst_3_bits_inst, + io_targets_0, + io_targets_1, + io_targets_2, + io_targets_3, + io_jalrTargets_0, + io_jalrTargets_1, + io_jalrTargets_2, + io_jalrTargets_3, + io_jump_0, + io_jump_1, + io_jump_2, + io_jump_3, + io_branch_0, + io_branch_1, + io_branch_2, + io_branch_3, + io_storeComplete_valid, + io_storeComplete_bits, + io_writeAddrScalar_0_valid, + io_writeAddrScalar_0_addr, + io_writeAddrScalar_1_valid, + io_writeAddrScalar_1_addr, + io_writeAddrScalar_2_valid, + io_writeAddrScalar_2_addr, + io_writeAddrScalar_3_valid, + io_writeAddrScalar_3_addr, + io_writeDataScalar_0_valid, + io_writeDataScalar_0_bits_addr, + io_writeDataScalar_1_valid, + io_writeDataScalar_1_bits_addr, + io_writeDataScalar_2_valid, + io_writeDataScalar_2_bits_addr, + io_writeDataScalar_3_valid, + io_writeDataScalar_3_bits_addr, + io_writeDataScalar_4_valid, + io_writeDataScalar_4_bits_addr, + io_writeDataScalar_5_valid, + io_writeDataScalar_5_bits_addr, + io_writeAddrFloat_valid, + io_writeAddrFloat_addr, + io_writeDataFloat_0_valid, + io_writeDataFloat_0_bits_addr, + io_writeDataFloat_1_valid, + io_writeDataFloat_1_bits_addr, + io_fault_valid, + io_fault_bits_mepc, + io_fault_bits_mcause, + io_fault_bits_decode, + io_nSpace, + io_nRetired, + io_empty, + io_trapPending, +); + input clock; + input reset; + input io_inst_0_ready; + input io_inst_0_valid; + input [31:0] io_inst_0_bits_addr; + input [31:0] io_inst_0_bits_inst; + input io_inst_1_ready; + input io_inst_1_valid; + input [31:0] io_inst_1_bits_addr; + input [31:0] io_inst_1_bits_inst; + input io_inst_2_ready; + input io_inst_2_valid; + input [31:0] io_inst_2_bits_addr; + input [31:0] io_inst_2_bits_inst; + input io_inst_3_ready; + input io_inst_3_valid; + input [31:0] io_inst_3_bits_addr; + input [31:0] io_inst_3_bits_inst; + input [31:0] io_targets_0; + input [31:0] io_targets_1; + input [31:0] io_targets_2; + input [31:0] io_targets_3; + input [31:0] io_jalrTargets_0; + input [31:0] io_jalrTargets_1; + input [31:0] io_jalrTargets_2; + input [31:0] io_jalrTargets_3; + input io_jump_0; + input io_jump_1; + input io_jump_2; + input io_jump_3; + input io_branch_0; + input io_branch_1; + input io_branch_2; + input io_branch_3; + input io_storeComplete_valid; + input [31:0] io_storeComplete_bits; + input io_writeAddrScalar_0_valid; + input [4:0] io_writeAddrScalar_0_addr; + input io_writeAddrScalar_1_valid; + input [4:0] io_writeAddrScalar_1_addr; + input io_writeAddrScalar_2_valid; + input [4:0] io_writeAddrScalar_2_addr; + input io_writeAddrScalar_3_valid; + input [4:0] io_writeAddrScalar_3_addr; + input io_writeDataScalar_0_valid; + input [4:0] io_writeDataScalar_0_bits_addr; + input io_writeDataScalar_1_valid; + input [4:0] io_writeDataScalar_1_bits_addr; + input io_writeDataScalar_2_valid; + input [4:0] io_writeDataScalar_2_bits_addr; + input io_writeDataScalar_3_valid; + input [4:0] io_writeDataScalar_3_bits_addr; + input io_writeDataScalar_4_valid; + input [4:0] io_writeDataScalar_4_bits_addr; + input io_writeDataScalar_5_valid; + input [4:0] io_writeDataScalar_5_bits_addr; + input io_writeAddrFloat_valid; + input [4:0] io_writeAddrFloat_addr; + input io_writeDataFloat_0_valid; + input [4:0] io_writeDataFloat_0_bits_addr; + input io_writeDataFloat_1_valid; + input [4:0] io_writeDataFloat_1_bits_addr; + input io_fault_valid; + input [31:0] io_fault_bits_mepc; + input [31:0] io_fault_bits_mcause; + input io_fault_bits_decode; + output wire [31:0] io_nSpace; + output wire [3:0] io_nRetired; + output wire io_empty; + output wire io_trapPending; + wire [3:0] _instBuffer_io_nEnqueued; + wire [3:0] _instBuffer_io_nSpace; + wire [31:0] _instBuffer_io_dataOut_0_addr; + wire [6:0] _instBuffer_io_dataOut_0_idx; + wire _instBuffer_io_dataOut_0_trap; + wire _instBuffer_io_dataOut_0_isControlFlow; + wire _instBuffer_io_dataOut_0_isBranch; + wire _instBuffer_io_dataOut_0_isEcall; + wire _instBuffer_io_dataOut_0_isMpause; + wire [31:0] _instBuffer_io_dataOut_1_addr; + wire [6:0] _instBuffer_io_dataOut_1_idx; + wire _instBuffer_io_dataOut_1_trap; + wire _instBuffer_io_dataOut_1_isControlFlow; + wire _instBuffer_io_dataOut_1_isBranch; + wire _instBuffer_io_dataOut_1_linkOk; + wire _instBuffer_io_dataOut_1_isEcall; + wire _instBuffer_io_dataOut_1_isMpause; + wire [31:0] _instBuffer_io_dataOut_2_addr; + wire [6:0] _instBuffer_io_dataOut_2_idx; + wire _instBuffer_io_dataOut_2_trap; + wire _instBuffer_io_dataOut_2_isControlFlow; + wire _instBuffer_io_dataOut_2_isBranch; + wire _instBuffer_io_dataOut_2_linkOk; + wire _instBuffer_io_dataOut_2_isEcall; + wire _instBuffer_io_dataOut_2_isMpause; + wire [31:0] _instBuffer_io_dataOut_3_addr; + wire [6:0] _instBuffer_io_dataOut_3_idx; + wire _instBuffer_io_dataOut_3_trap; + wire _instBuffer_io_dataOut_3_isControlFlow; + wire _instBuffer_io_dataOut_3_isBranch; + wire _instBuffer_io_dataOut_3_linkOk; + wire _instBuffer_io_dataOut_3_isEcall; + wire _instBuffer_io_dataOut_3_isMpause; + wire [31:0] _instBuffer_io_dataOut_4_addr; + wire [6:0] _instBuffer_io_dataOut_4_idx; + wire _instBuffer_io_dataOut_4_trap; + wire _instBuffer_io_dataOut_4_isControlFlow; + wire _instBuffer_io_dataOut_4_isBranch; + wire _instBuffer_io_dataOut_4_linkOk; + wire _instBuffer_io_dataOut_4_isEcall; + wire _instBuffer_io_dataOut_4_isMpause; + wire [31:0] _instBuffer_io_dataOut_5_addr; + wire [6:0] _instBuffer_io_dataOut_5_idx; + wire _instBuffer_io_dataOut_5_trap; + wire _instBuffer_io_dataOut_5_isControlFlow; + wire _instBuffer_io_dataOut_5_isBranch; + wire _instBuffer_io_dataOut_5_linkOk; + wire _instBuffer_io_dataOut_5_isEcall; + wire _instBuffer_io_dataOut_5_isMpause; + wire [31:0] _instBuffer_io_dataOut_6_addr; + wire [6:0] _instBuffer_io_dataOut_6_idx; + wire _instBuffer_io_dataOut_6_trap; + wire _instBuffer_io_dataOut_6_isControlFlow; + wire _instBuffer_io_dataOut_6_isBranch; + wire _instBuffer_io_dataOut_6_linkOk; + wire _instBuffer_io_dataOut_6_isEcall; + wire _instBuffer_io_dataOut_6_isMpause; + wire [31:0] _instBuffer_io_dataOut_7_addr; + wire [6:0] _instBuffer_io_dataOut_7_idx; + wire _instBuffer_io_dataOut_7_trap; + wire _instBuffer_io_dataOut_7_isControlFlow; + wire _instBuffer_io_dataOut_7_isBranch; + wire _instBuffer_io_dataOut_7_linkOk; + wire _instBuffer_io_dataOut_7_isEcall; + wire _instBuffer_io_dataOut_7_isMpause; + reg storeComplete_pipe_v; + reg [31:0] storeComplete_pipe_b; + wire instFires_0 = io_inst_0_ready & io_inst_0_valid; + wire instFires_1 = io_inst_1_ready & io_inst_1_valid; + wire instFires_2 = io_inst_2_ready & io_inst_2_valid; + wire instFires_3 = io_inst_3_ready & io_inst_3_valid; + wire decodeFaultValid = io_fault_valid & io_fault_bits_decode; + wire noFire0Fault = ((io_fault_valid & ~instFires_0) & (io_fault_bits_mcause != 32'h00000007)) & (io_fault_bits_mcause != 32'h00000005); + reg [31:0] regLastTarget; + reg [31:0] regLastAddr; + reg regLastIsBranch; + wire _lane0LinkOk_T_35 = io_inst_0_bits_addr == regLastTarget; + wire [31:0] _faultLinkOk_T_36 = regLastAddr + 32'h00000004; + wire insts_instr_isVector = (io_inst_0_bits_inst[6:0] == 7'h27) & (((~(|io_inst_0_bits_inst[14:12]) | (io_inst_0_bits_inst[14:12] == 3'h5)) | (io_inst_0_bits_inst[14:12] == 3'h6)) | &io_inst_0_bits_inst[14:12]); + wire [6:0] _GEN = {2'h0, io_writeAddrScalar_0_addr}; + wire insts_vectorStore = (io_inst_0_bits_inst[6:0] == 7'h27) & (((~(|io_inst_0_bits_inst[14:12]) | (io_inst_0_bits_inst[14:12] == 3'h5)) | (io_inst_0_bits_inst[14:12] == 3'h6)) | &io_inst_0_bits_inst[14:12]); + wire insts_1_isVector = (io_inst_1_bits_inst[6:0] == 7'h27) & ((((io_inst_1_bits_inst[14:12] == 3'h0) | (io_inst_1_bits_inst[14:12] == 3'h5)) | (io_inst_1_bits_inst[14:12] == 3'h6)) | &io_inst_1_bits_inst[14:12]); + wire insts_2_isVector = (io_inst_2_bits_inst[6:0] == 7'h27) & ((((io_inst_2_bits_inst[14:12] == 3'h0) | (io_inst_2_bits_inst[14:12] == 3'h5)) | (io_inst_2_bits_inst[14:12] == 3'h6)) | &io_inst_2_bits_inst[14:12]); + wire insts_3_isVector = (io_inst_3_bits_inst[6:0] == 7'h27) & ((((io_inst_3_bits_inst[14:12] == 3'h0) | (io_inst_3_bits_inst[14:12] == 3'h5)) | (io_inst_3_bits_inst[14:12] == 3'h6)) | &io_inst_3_bits_inst[14:12]); + reg resultBuffer_0_valid; + reg resultBuffer_0_bits_trap; + reg resultBuffer_0_bits_cfDone; + reg resultBuffer_1_valid; + reg resultBuffer_1_bits_trap; + reg resultBuffer_1_bits_cfDone; + reg resultBuffer_2_valid; + reg resultBuffer_2_bits_trap; + reg resultBuffer_2_bits_cfDone; + reg resultBuffer_3_valid; + reg resultBuffer_3_bits_trap; + reg resultBuffer_3_bits_cfDone; + reg resultBuffer_4_valid; + reg resultBuffer_4_bits_trap; + reg resultBuffer_4_bits_cfDone; + reg resultBuffer_5_valid; + reg resultBuffer_5_bits_trap; + reg resultBuffer_5_bits_cfDone; + reg resultBuffer_6_valid; + reg resultBuffer_6_bits_trap; + reg resultBuffer_6_bits_cfDone; + reg resultBuffer_7_valid; + reg resultBuffer_7_bits_trap; + reg resultBuffer_7_bits_cfDone; + wire [6:0] _GEN_0 = {2'h0, io_writeDataScalar_0_bits_addr}; + wire [6:0] _GEN_1 = {2'h0, io_writeDataScalar_1_bits_addr}; + wire [6:0] _GEN_2 = {2'h0, io_writeDataScalar_2_bits_addr}; + wire [6:0] _GEN_3 = {2'h0, io_writeDataScalar_3_bits_addr}; + wire [6:0] _GEN_4 = {2'h0, io_writeDataScalar_4_bits_addr}; + wire [6:0] _GEN_5 = {2'h0, io_writeDataScalar_5_bits_addr}; + wire [6:0] _floatWriteIdxMap_T_28 = {2'h0, io_writeDataFloat_0_bits_addr} + 7'h20; + wire [6:0] _floatWriteIdxMap_T_30 = {2'h0, io_writeDataFloat_1_bits_addr} + 7'h20; + wire nextAddrValid = (|_instBuffer_io_nEnqueued[3:1] | noFire0Fault) | io_inst_0_valid; + wire _faultLinkOk_T_35 = io_fault_bits_mepc == regLastTarget; + wire newCfDone = |_instBuffer_io_nEnqueued & (~_instBuffer_io_dataOut_0_isControlFlow | nextAddrValid); + wire hi = ((resultBuffer_0_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_0_addr == io_fault_bits_mepc))) | (|_instBuffer_io_nEnqueued & _instBuffer_io_dataOut_0_trap)) | (((_instBuffer_io_dataOut_0_isControlFlow & newCfDone) & (~(nextAddrValid & ((|_instBuffer_io_nEnqueued[3:1] ? _instBuffer_io_dataOut_1_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_0_isBranch & ((|_instBuffer_io_nEnqueued[3:1] ? _instBuffer_io_dataOut_1_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_1_addr))) == (_instBuffer_io_dataOut_0_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_0_isMpause); + wire currentDataDone = resultBuffer_0_valid | ((|_instBuffer_io_nEnqueued & ~resultBuffer_0_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_0_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_0_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_0_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_0_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_0_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_0_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_0_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_0_idx))) | &_instBuffer_io_dataOut_0_idx) | (((_instBuffer_io_dataOut_0_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_0_addr))) | hi)); + wire currentCfDone = (resultBuffer_0_valid & resultBuffer_0_bits_cfDone) | newCfDone; + wire nextValid_1 = _instBuffer_io_nEnqueued > 4'h2; + wire nextAddrValid_1 = (nextValid_1 | noFire0Fault) | io_inst_0_valid; + wire newCfDone_1 = |_instBuffer_io_nEnqueued[3:1] & (~_instBuffer_io_dataOut_1_isControlFlow | nextAddrValid_1); + wire currentTrap_1 = ((resultBuffer_1_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_1_addr == io_fault_bits_mepc))) | (|_instBuffer_io_nEnqueued[3:1] & _instBuffer_io_dataOut_1_trap)) | (((_instBuffer_io_dataOut_1_isControlFlow & newCfDone_1) & (~(nextAddrValid_1 & ((nextValid_1 ? _instBuffer_io_dataOut_2_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_1_isBranch & ((nextValid_1 ? _instBuffer_io_dataOut_2_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_2_addr))) == (_instBuffer_io_dataOut_1_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_1_isMpause); + wire currentDataDone_1 = resultBuffer_1_valid | ((|_instBuffer_io_nEnqueued[3:1] & ~resultBuffer_1_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_1_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_1_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_1_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_1_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_1_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_1_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_1_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_1_idx))) | &_instBuffer_io_dataOut_1_idx) | (((_instBuffer_io_dataOut_1_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_1_addr))) | currentTrap_1)); + wire currentCfDone_1 = (resultBuffer_1_valid & resultBuffer_1_bits_cfDone) | newCfDone_1; + wire validBufferEntry_2 = _instBuffer_io_nEnqueued > 4'h2; + wire nextAddrValid_2 = (|_instBuffer_io_nEnqueued[3:2] | noFire0Fault) | io_inst_0_valid; + wire newCfDone_2 = validBufferEntry_2 & (~_instBuffer_io_dataOut_2_isControlFlow | nextAddrValid_2); + wire currentTrap_2 = ((resultBuffer_2_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_2_addr == io_fault_bits_mepc))) | (validBufferEntry_2 & _instBuffer_io_dataOut_2_trap)) | (((_instBuffer_io_dataOut_2_isControlFlow & newCfDone_2) & (~(nextAddrValid_2 & ((|_instBuffer_io_nEnqueued[3:2] ? _instBuffer_io_dataOut_3_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_2_isBranch & ((|_instBuffer_io_nEnqueued[3:2] ? _instBuffer_io_dataOut_3_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_3_addr))) == (_instBuffer_io_dataOut_2_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_2_isMpause); + wire currentDataDone_2 = resultBuffer_2_valid | ((validBufferEntry_2 & ~resultBuffer_2_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_2_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_2_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_2_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_2_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_2_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_2_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_2_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_2_idx))) | &_instBuffer_io_dataOut_2_idx) | (((_instBuffer_io_dataOut_2_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_2_addr))) | currentTrap_2)); + wire currentCfDone_2 = (resultBuffer_2_valid & resultBuffer_2_bits_cfDone) | newCfDone_2; + wire nextValid_3 = _instBuffer_io_nEnqueued > 4'h4; + wire nextAddrValid_3 = (nextValid_3 | noFire0Fault) | io_inst_0_valid; + wire newCfDone_3 = |_instBuffer_io_nEnqueued[3:2] & (~_instBuffer_io_dataOut_3_isControlFlow | nextAddrValid_3); + wire currentTrap_3 = ((resultBuffer_3_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_3_addr == io_fault_bits_mepc))) | (|_instBuffer_io_nEnqueued[3:2] & _instBuffer_io_dataOut_3_trap)) | (((_instBuffer_io_dataOut_3_isControlFlow & newCfDone_3) & (~(nextAddrValid_3 & ((nextValid_3 ? _instBuffer_io_dataOut_4_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_3_isBranch & ((nextValid_3 ? _instBuffer_io_dataOut_4_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_4_addr))) == (_instBuffer_io_dataOut_3_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_3_isMpause); + wire currentDataDone_3 = resultBuffer_3_valid | ((|_instBuffer_io_nEnqueued[3:2] & ~resultBuffer_3_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_3_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_3_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_3_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_3_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_3_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_3_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_3_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_3_idx))) | &_instBuffer_io_dataOut_3_idx) | (((_instBuffer_io_dataOut_3_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_3_addr))) | currentTrap_3)); + wire currentCfDone_3 = (resultBuffer_3_valid & resultBuffer_3_bits_cfDone) | newCfDone_3; + wire validBufferEntry_4 = _instBuffer_io_nEnqueued > 4'h4; + wire nextValid_4 = _instBuffer_io_nEnqueued > 4'h5; + wire nextAddrValid_4 = (nextValid_4 | noFire0Fault) | io_inst_0_valid; + wire newCfDone_4 = validBufferEntry_4 & (~_instBuffer_io_dataOut_4_isControlFlow | nextAddrValid_4); + wire currentTrap_4 = ((resultBuffer_4_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_4_addr == io_fault_bits_mepc))) | (validBufferEntry_4 & _instBuffer_io_dataOut_4_trap)) | (((_instBuffer_io_dataOut_4_isControlFlow & newCfDone_4) & (~(nextAddrValid_4 & ((nextValid_4 ? _instBuffer_io_dataOut_5_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_4_isBranch & ((nextValid_4 ? _instBuffer_io_dataOut_5_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_5_addr))) == (_instBuffer_io_dataOut_4_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_4_isMpause); + wire currentDataDone_4 = resultBuffer_4_valid | ((validBufferEntry_4 & ~resultBuffer_4_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_4_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_4_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_4_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_4_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_4_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_4_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_4_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_4_idx))) | &_instBuffer_io_dataOut_4_idx) | (((_instBuffer_io_dataOut_4_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_4_addr))) | currentTrap_4)); + wire currentCfDone_4 = (resultBuffer_4_valid & resultBuffer_4_bits_cfDone) | newCfDone_4; + wire validBufferEntry_5 = _instBuffer_io_nEnqueued > 4'h5; + wire nextValid_5 = _instBuffer_io_nEnqueued > 4'h6; + wire nextAddrValid_5 = (nextValid_5 | noFire0Fault) | io_inst_0_valid; + wire newCfDone_5 = validBufferEntry_5 & (~_instBuffer_io_dataOut_5_isControlFlow | nextAddrValid_5); + wire currentTrap_5 = ((resultBuffer_5_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_5_addr == io_fault_bits_mepc))) | (validBufferEntry_5 & _instBuffer_io_dataOut_5_trap)) | (((_instBuffer_io_dataOut_5_isControlFlow & newCfDone_5) & (~(nextAddrValid_5 & ((nextValid_5 ? _instBuffer_io_dataOut_6_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_5_isBranch & ((nextValid_5 ? _instBuffer_io_dataOut_6_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_6_addr))) == (_instBuffer_io_dataOut_5_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_5_isMpause); + wire currentDataDone_5 = resultBuffer_5_valid | ((validBufferEntry_5 & ~resultBuffer_5_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_5_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_5_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_5_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_5_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_5_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_5_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_5_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_5_idx))) | &_instBuffer_io_dataOut_5_idx) | (((_instBuffer_io_dataOut_5_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_5_addr))) | currentTrap_5)); + wire currentCfDone_5 = (resultBuffer_5_valid & resultBuffer_5_bits_cfDone) | newCfDone_5; + wire validBufferEntry_6 = _instBuffer_io_nEnqueued > 4'h6; + wire nextAddrValid_6 = (_instBuffer_io_nEnqueued[3] | noFire0Fault) | io_inst_0_valid; + wire newCfDone_6 = validBufferEntry_6 & (~_instBuffer_io_dataOut_6_isControlFlow | nextAddrValid_6); + wire currentTrap_6 = ((resultBuffer_6_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_6_addr == io_fault_bits_mepc))) | (validBufferEntry_6 & _instBuffer_io_dataOut_6_trap)) | (((_instBuffer_io_dataOut_6_isControlFlow & newCfDone_6) & (~(nextAddrValid_6 & ((_instBuffer_io_nEnqueued[3] ? _instBuffer_io_dataOut_7_linkOk : (noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))) | (_instBuffer_io_dataOut_6_isBranch & ((_instBuffer_io_nEnqueued[3] ? _instBuffer_io_dataOut_7_addr : (noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : _instBuffer_io_dataOut_7_addr))) == (_instBuffer_io_dataOut_6_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_6_isMpause); + wire currentDataDone_6 = resultBuffer_6_valid | ((validBufferEntry_6 & ~resultBuffer_6_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_6_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_6_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_6_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_6_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_6_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_6_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_6_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_6_idx))) | &_instBuffer_io_dataOut_6_idx) | (((_instBuffer_io_dataOut_6_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_6_addr))) | currentTrap_6)); + wire currentCfDone_6 = (resultBuffer_6_valid & resultBuffer_6_bits_cfDone) | newCfDone_6; + wire nextAddrValid_7 = noFire0Fault | io_inst_0_valid; + wire newCfDone_7 = _instBuffer_io_nEnqueued[3] & (~_instBuffer_io_dataOut_7_isControlFlow | nextAddrValid_7); + wire currentTrap_7 = ((resultBuffer_7_bits_trap | (io_fault_valid & (_instBuffer_io_dataOut_7_addr == io_fault_bits_mepc))) | (_instBuffer_io_nEnqueued[3] & _instBuffer_io_dataOut_7_trap)) | (((_instBuffer_io_dataOut_7_isControlFlow & newCfDone_7) & (~(nextAddrValid_7 & ((noFire0Fault ? _faultLinkOk_T_35 | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : (~io_inst_0_valid | _lane0LinkOk_T_35) | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36))) | (_instBuffer_io_dataOut_7_isBranch & ((noFire0Fault ? io_fault_bits_mepc : (io_inst_0_valid ? io_inst_0_bits_addr : 32'h00000000)) == (_instBuffer_io_dataOut_7_addr + 32'h00000004))))) | noFire0Fault)) & ~_instBuffer_io_dataOut_7_isMpause); + wire currentDataDone_7 = resultBuffer_7_valid | ((_instBuffer_io_nEnqueued[3] & ~resultBuffer_7_valid) & (((((((((((io_writeDataScalar_0_valid & (_GEN_0 == _instBuffer_io_dataOut_7_idx)) | (io_writeDataScalar_1_valid & (_GEN_1 == _instBuffer_io_dataOut_7_idx))) | (io_writeDataScalar_2_valid & (_GEN_2 == _instBuffer_io_dataOut_7_idx))) | (io_writeDataScalar_3_valid & (_GEN_3 == _instBuffer_io_dataOut_7_idx))) | (io_writeDataScalar_4_valid & (_GEN_4 == _instBuffer_io_dataOut_7_idx))) | (io_writeDataScalar_5_valid & (_GEN_5 == _instBuffer_io_dataOut_7_idx))) | (io_writeDataFloat_0_valid & (_floatWriteIdxMap_T_28 == _instBuffer_io_dataOut_7_idx))) | (io_writeDataFloat_1_valid & (_floatWriteIdxMap_T_30 == _instBuffer_io_dataOut_7_idx))) | &_instBuffer_io_dataOut_7_idx) | (((_instBuffer_io_dataOut_7_idx == 7'h7e) & storeComplete_pipe_v) & (storeComplete_pipe_b == _instBuffer_io_dataOut_7_addr))) | currentTrap_7)); + wire currentCfDone_7 = (resultBuffer_7_valid & resultBuffer_7_bits_cfDone) | newCfDone_7; + wire trapDetected_0 = currentDataDone & hi; + wire trapDetected_1 = currentDataDone_1 & currentTrap_1; + wire trapDetected_2 = currentDataDone_2 & currentTrap_2; + wire trapDetected_3 = currentDataDone_3 & currentTrap_3; + wire trapDetected_4 = currentDataDone_4 & currentTrap_4; + wire trapDetected_5 = currentDataDone_5 & currentTrap_5; + wire trapDetected_6 = currentDataDone_6 & currentTrap_6; + wire hasTrap = ((((((trapDetected_0 | trapDetected_1) | trapDetected_2) | trapDetected_3) | trapDetected_4) | trapDetected_5) | trapDetected_6) | (currentDataDone_7 & currentTrap_7); + wire [7:0] _countValid_T_9 = ~{currentDataDone_7 & currentCfDone_7, currentDataDone_6 & currentCfDone_6, currentDataDone_5 & currentCfDone_5, currentDataDone_4 & currentCfDone_4, currentDataDone_3 & currentCfDone_3, currentDataDone_2 & currentCfDone_2, currentDataDone_1 & currentCfDone_1, currentDataDone & currentCfDone}; + wire [3:0] countValid = (_countValid_T_9[0] ? 4'h0 : (_countValid_T_9[1] ? 4'h1 : (_countValid_T_9[2] ? 4'h2 : (_countValid_T_9[3] ? 4'h3 : (_countValid_T_9[4] ? 4'h4 : (_countValid_T_9[5] ? 4'h5 : (_countValid_T_9[6] ? 4'h6 : (_countValid_T_9[7] ? 4'h7 : 4'h8)))))))); + wire [3:0] _GEN_6 = {1'h0, (trapDetected_0 ? 3'h0 : (trapDetected_1 ? 3'h1 : (trapDetected_2 ? 3'h2 : (trapDetected_3 ? 3'h3 : (trapDetected_4 ? 3'h4 : (trapDetected_5 ? 3'h5 : {2'h3, ~trapDetected_6})))))) + 3'h1}; + wire trapReadyToRetire = hasTrap & (_GEN_6 <= countValid); + wire [3:0] deqReady = (trapReadyToRetire ? _GEN_6 : countValid); + reg io_trapPending_REG; + wire valid_2 = deqReady > 4'h2; + wire valid_4 = deqReady > 4'h4; + wire valid_5 = deqReady > 4'h5; + wire valid_6 = deqReady > 4'h6; + wire [23:0] shifted = {currentDataDone_7, currentTrap_7, currentCfDone_7, currentDataDone_6, currentTrap_6, currentCfDone_6, currentDataDone_5, currentTrap_5, currentCfDone_5, currentDataDone_4, currentTrap_4, currentCfDone_4, currentDataDone_3, currentTrap_3, currentCfDone_3, currentDataDone_2, currentTrap_2, currentCfDone_2, currentDataDone_1, currentTrap_1, currentCfDone_1, currentDataDone, hi, currentCfDone} >> ({2'h0, deqReady} * 6'h03); + always @(posedge clock or posedge reset) + if (reset) begin + storeComplete_pipe_v <= 1'h0; + regLastTarget <= 32'h00000000; + regLastAddr <= 32'h00000000; + regLastIsBranch <= 1'h0; + resultBuffer_0_valid <= 1'h0; + resultBuffer_0_bits_trap <= 1'h0; + resultBuffer_0_bits_cfDone <= 1'h0; + resultBuffer_1_valid <= 1'h0; + resultBuffer_1_bits_trap <= 1'h0; + resultBuffer_1_bits_cfDone <= 1'h0; + resultBuffer_2_valid <= 1'h0; + resultBuffer_2_bits_trap <= 1'h0; + resultBuffer_2_bits_cfDone <= 1'h0; + resultBuffer_3_valid <= 1'h0; + resultBuffer_3_bits_trap <= 1'h0; + resultBuffer_3_bits_cfDone <= 1'h0; + resultBuffer_4_valid <= 1'h0; + resultBuffer_4_bits_trap <= 1'h0; + resultBuffer_4_bits_cfDone <= 1'h0; + resultBuffer_5_valid <= 1'h0; + resultBuffer_5_bits_trap <= 1'h0; + resultBuffer_5_bits_cfDone <= 1'h0; + resultBuffer_6_valid <= 1'h0; + resultBuffer_6_bits_trap <= 1'h0; + resultBuffer_6_bits_cfDone <= 1'h0; + resultBuffer_7_valid <= 1'h0; + resultBuffer_7_bits_trap <= 1'h0; + resultBuffer_7_bits_cfDone <= 1'h0; + io_trapPending_REG <= 1'h0; + end + else begin + storeComplete_pipe_v <= io_storeComplete_valid; + if (((instFires_0 | instFires_1) | instFires_2) | instFires_3) begin + regLastTarget <= (instFires_3 ? (io_inst_3_bits_inst[6:0] == 7'h67 ? io_jalrTargets_3 : io_targets_3) : (instFires_2 ? (io_inst_2_bits_inst[6:0] == 7'h67 ? io_jalrTargets_2 : io_targets_2) : (instFires_1 ? (io_inst_1_bits_inst[6:0] == 7'h67 ? io_jalrTargets_1 : io_targets_1) : (io_inst_0_bits_inst[6:0] == 7'h67 ? io_jalrTargets_0 : io_targets_0)))); + regLastAddr <= (instFires_3 ? io_inst_3_bits_addr : (instFires_2 ? io_inst_2_bits_addr : (instFires_1 ? io_inst_1_bits_addr : io_inst_0_bits_addr))); + regLastIsBranch <= (instFires_3 ? io_branch_3 : (instFires_2 ? io_branch_2 : (instFires_1 ? io_branch_1 : io_branch_0))); + end + resultBuffer_0_valid <= ~trapReadyToRetire & shifted[2]; + resultBuffer_0_bits_trap <= ~trapReadyToRetire & shifted[1]; + resultBuffer_0_bits_cfDone <= ~trapReadyToRetire & shifted[0]; + resultBuffer_1_valid <= ~trapReadyToRetire & shifted[5]; + resultBuffer_1_bits_trap <= ~trapReadyToRetire & shifted[4]; + resultBuffer_1_bits_cfDone <= ~trapReadyToRetire & shifted[3]; + resultBuffer_2_valid <= ~trapReadyToRetire & shifted[8]; + resultBuffer_2_bits_trap <= ~trapReadyToRetire & shifted[7]; + resultBuffer_2_bits_cfDone <= ~trapReadyToRetire & shifted[6]; + resultBuffer_3_valid <= ~trapReadyToRetire & shifted[11]; + resultBuffer_3_bits_trap <= ~trapReadyToRetire & shifted[10]; + resultBuffer_3_bits_cfDone <= ~trapReadyToRetire & shifted[9]; + resultBuffer_4_valid <= ~trapReadyToRetire & shifted[14]; + resultBuffer_4_bits_trap <= ~trapReadyToRetire & shifted[13]; + resultBuffer_4_bits_cfDone <= ~trapReadyToRetire & shifted[12]; + resultBuffer_5_valid <= ~trapReadyToRetire & shifted[17]; + resultBuffer_5_bits_trap <= ~trapReadyToRetire & shifted[16]; + resultBuffer_5_bits_cfDone <= ~trapReadyToRetire & shifted[15]; + resultBuffer_6_valid <= ~trapReadyToRetire & shifted[20]; + resultBuffer_6_bits_trap <= ~trapReadyToRetire & shifted[19]; + resultBuffer_6_bits_cfDone <= ~trapReadyToRetire & shifted[18]; + resultBuffer_7_valid <= ~trapReadyToRetire & shifted[23]; + resultBuffer_7_bits_trap <= ~trapReadyToRetire & shifted[22]; + resultBuffer_7_bits_cfDone <= ~trapReadyToRetire & shifted[21]; + io_trapPending_REG <= hasTrap & ~trapReadyToRetire; + end + always @(posedge clock) + if (io_storeComplete_valid) + storeComplete_pipe_b <= io_storeComplete_bits; + CircularBufferMulti_2 instBuffer( + .clock(clock), + .reset(reset), + .io_enqValid({1'h0, {1'h0, {1'h0, instFires_0} + {1'h0, instFires_1}} + {1'h0, {1'h0, instFires_2} + {1'h0, instFires_3}}} + {3'h0, decodeFaultValid | noFire0Fault}), + .io_enqData_0_addr((noFire0Fault ? io_fault_bits_mepc : io_inst_0_bits_addr)), + .io_enqData_0_idx((io_writeAddrFloat_valid ? {2'h0, io_writeAddrFloat_addr} + 7'h20 : (noFire0Fault ? (io_writeAddrScalar_0_valid & |io_writeAddrScalar_0_addr ? _GEN : {6'h3f, ~(((io_inst_0_bits_inst[6:0] == 7'h23) | ((io_inst_0_bits_inst[6:0] == 7'h27) & ((((io_inst_0_bits_inst[14:12] == 3'h1) | (io_inst_0_bits_inst[14:12] == 3'h2)) | (io_inst_0_bits_inst[14:12] == 3'h3)) | (io_inst_0_bits_inst[14:12] == 3'h4)))) | insts_instr_isVector)}) : (io_writeAddrScalar_0_valid & |io_writeAddrScalar_0_addr ? _GEN : {6'h3f, ~(((io_inst_0_bits_inst[6:0] == 7'h23) | ((io_inst_0_bits_inst[6:0] == 7'h27) & ((((io_inst_0_bits_inst[14:12] == 3'h1) | (io_inst_0_bits_inst[14:12] == 3'h2)) | (io_inst_0_bits_inst[14:12] == 3'h3)) | (io_inst_0_bits_inst[14:12] == 3'h4)))) | insts_vectorStore)})))), + .io_enqData_0_trap(noFire0Fault | (decodeFaultValid & (io_fault_bits_mepc == io_inst_0_bits_addr))), + .io_enqData_0_isControlFlow(io_jump_0 | io_branch_0), + .io_enqData_0_isBranch(io_branch_0), + .io_enqData_0_isVector((noFire0Fault ? insts_instr_isVector : insts_vectorStore)), + .io_enqData_0_linkOk((noFire0Fault ? (io_fault_bits_mepc == regLastTarget) | (regLastIsBranch & (io_fault_bits_mepc == _faultLinkOk_T_36)) : _lane0LinkOk_T_35 | (regLastIsBranch & (io_inst_0_bits_addr == _faultLinkOk_T_36)))), + .io_enqData_0_isEcall(io_inst_0_bits_inst == 32'h00000073), + .io_enqData_0_isMpause(io_inst_0_bits_inst == 32'h08000073), + .io_enqData_1_addr(io_inst_1_bits_addr), + .io_enqData_1_idx((io_writeAddrScalar_1_valid & |io_writeAddrScalar_1_addr ? {2'h0, io_writeAddrScalar_1_addr} : {6'h3f, ~(((io_inst_1_bits_inst[6:0] == 7'h23) | ((io_inst_1_bits_inst[6:0] == 7'h27) & ((((io_inst_1_bits_inst[14:12] == 3'h1) | (io_inst_1_bits_inst[14:12] == 3'h2)) | (io_inst_1_bits_inst[14:12] == 3'h3)) | (io_inst_1_bits_inst[14:12] == 3'h4)))) | insts_1_isVector)})), + .io_enqData_1_trap(decodeFaultValid & (io_fault_bits_mepc == io_inst_1_bits_addr)), + .io_enqData_1_isControlFlow(io_jump_1 | io_branch_1), + .io_enqData_1_isBranch(io_branch_1), + .io_enqData_1_isVector(insts_1_isVector), + .io_enqData_1_linkOk((io_inst_1_bits_addr == (io_inst_0_bits_inst[6:0] == 7'h67 ? io_jalrTargets_0 : io_targets_0)) | (io_branch_0 & (io_inst_1_bits_addr == (io_inst_0_bits_addr + 32'h00000004)))), + .io_enqData_1_isEcall(io_inst_1_bits_inst == 32'h00000073), + .io_enqData_1_isMpause(io_inst_1_bits_inst == 32'h08000073), + .io_enqData_2_addr(io_inst_2_bits_addr), + .io_enqData_2_idx((io_writeAddrScalar_2_valid & |io_writeAddrScalar_2_addr ? {2'h0, io_writeAddrScalar_2_addr} : {6'h3f, ~(((io_inst_2_bits_inst[6:0] == 7'h23) | ((io_inst_2_bits_inst[6:0] == 7'h27) & ((((io_inst_2_bits_inst[14:12] == 3'h1) | (io_inst_2_bits_inst[14:12] == 3'h2)) | (io_inst_2_bits_inst[14:12] == 3'h3)) | (io_inst_2_bits_inst[14:12] == 3'h4)))) | insts_2_isVector)})), + .io_enqData_2_trap(decodeFaultValid & (io_fault_bits_mepc == io_inst_2_bits_addr)), + .io_enqData_2_isControlFlow(io_jump_2 | io_branch_2), + .io_enqData_2_isBranch(io_branch_2), + .io_enqData_2_isVector(insts_2_isVector), + .io_enqData_2_linkOk((io_inst_2_bits_addr == (io_inst_1_bits_inst[6:0] == 7'h67 ? io_jalrTargets_1 : io_targets_1)) | (io_branch_1 & (io_inst_2_bits_addr == (io_inst_1_bits_addr + 32'h00000004)))), + .io_enqData_2_isEcall(io_inst_2_bits_inst == 32'h00000073), + .io_enqData_2_isMpause(io_inst_2_bits_inst == 32'h08000073), + .io_enqData_3_addr(io_inst_3_bits_addr), + .io_enqData_3_idx((io_writeAddrScalar_3_valid & |io_writeAddrScalar_3_addr ? {2'h0, io_writeAddrScalar_3_addr} : {6'h3f, ~(((io_inst_3_bits_inst[6:0] == 7'h23) | ((io_inst_3_bits_inst[6:0] == 7'h27) & ((((io_inst_3_bits_inst[14:12] == 3'h1) | (io_inst_3_bits_inst[14:12] == 3'h2)) | (io_inst_3_bits_inst[14:12] == 3'h3)) | (io_inst_3_bits_inst[14:12] == 3'h4)))) | insts_3_isVector)})), + .io_enqData_3_trap(decodeFaultValid & (io_fault_bits_mepc == io_inst_3_bits_addr)), + .io_enqData_3_isControlFlow(io_jump_3 | io_branch_3), + .io_enqData_3_isBranch(io_branch_3), + .io_enqData_3_isVector(insts_3_isVector), + .io_enqData_3_linkOk((io_inst_3_bits_addr == (io_inst_2_bits_inst[6:0] == 7'h67 ? io_jalrTargets_2 : io_targets_2)) | (io_branch_2 & (io_inst_3_bits_addr == (io_inst_2_bits_addr + 32'h00000004)))), + .io_enqData_3_isEcall(io_inst_3_bits_inst == 32'h00000073), + .io_enqData_3_isMpause(io_inst_3_bits_inst == 32'h08000073), + .io_enqData_4_addr(32'h00000000), + .io_enqData_4_idx(7'h00), + .io_enqData_4_trap(1'h0), + .io_enqData_4_isControlFlow(1'h0), + .io_enqData_4_isBranch(1'h0), + .io_enqData_4_isVector(1'h0), + .io_enqData_4_linkOk(1'h0), + .io_enqData_4_isEcall(1'h0), + .io_enqData_4_isMpause(1'h0), + .io_enqData_5_addr(32'h00000000), + .io_enqData_5_idx(7'h00), + .io_enqData_5_trap(1'h0), + .io_enqData_5_isControlFlow(1'h0), + .io_enqData_5_isBranch(1'h0), + .io_enqData_5_isVector(1'h0), + .io_enqData_5_linkOk(1'h0), + .io_enqData_5_isEcall(1'h0), + .io_enqData_5_isMpause(1'h0), + .io_enqData_6_addr(32'h00000000), + .io_enqData_6_idx(7'h00), + .io_enqData_6_trap(1'h0), + .io_enqData_6_isControlFlow(1'h0), + .io_enqData_6_isBranch(1'h0), + .io_enqData_6_isVector(1'h0), + .io_enqData_6_linkOk(1'h0), + .io_enqData_6_isEcall(1'h0), + .io_enqData_6_isMpause(1'h0), + .io_enqData_7_addr(32'h00000000), + .io_enqData_7_idx(7'h00), + .io_enqData_7_trap(1'h0), + .io_enqData_7_isControlFlow(1'h0), + .io_enqData_7_isBranch(1'h0), + .io_enqData_7_isVector(1'h0), + .io_enqData_7_linkOk(1'h0), + .io_enqData_7_isEcall(1'h0), + .io_enqData_7_isMpause(1'h0), + .io_nEnqueued(_instBuffer_io_nEnqueued), + .io_nSpace(_instBuffer_io_nSpace), + .io_dataOut_0_addr(_instBuffer_io_dataOut_0_addr), + .io_dataOut_0_idx(_instBuffer_io_dataOut_0_idx), + .io_dataOut_0_trap(_instBuffer_io_dataOut_0_trap), + .io_dataOut_0_isControlFlow(_instBuffer_io_dataOut_0_isControlFlow), + .io_dataOut_0_isBranch(_instBuffer_io_dataOut_0_isBranch), + .io_dataOut_0_isVector(), + .io_dataOut_0_linkOk(), + .io_dataOut_0_isEcall(_instBuffer_io_dataOut_0_isEcall), + .io_dataOut_0_isMpause(_instBuffer_io_dataOut_0_isMpause), + .io_dataOut_1_addr(_instBuffer_io_dataOut_1_addr), + .io_dataOut_1_idx(_instBuffer_io_dataOut_1_idx), + .io_dataOut_1_trap(_instBuffer_io_dataOut_1_trap), + .io_dataOut_1_isControlFlow(_instBuffer_io_dataOut_1_isControlFlow), + .io_dataOut_1_isBranch(_instBuffer_io_dataOut_1_isBranch), + .io_dataOut_1_isVector(), + .io_dataOut_1_linkOk(_instBuffer_io_dataOut_1_linkOk), + .io_dataOut_1_isEcall(_instBuffer_io_dataOut_1_isEcall), + .io_dataOut_1_isMpause(_instBuffer_io_dataOut_1_isMpause), + .io_dataOut_2_addr(_instBuffer_io_dataOut_2_addr), + .io_dataOut_2_idx(_instBuffer_io_dataOut_2_idx), + .io_dataOut_2_trap(_instBuffer_io_dataOut_2_trap), + .io_dataOut_2_isControlFlow(_instBuffer_io_dataOut_2_isControlFlow), + .io_dataOut_2_isBranch(_instBuffer_io_dataOut_2_isBranch), + .io_dataOut_2_isVector(), + .io_dataOut_2_linkOk(_instBuffer_io_dataOut_2_linkOk), + .io_dataOut_2_isEcall(_instBuffer_io_dataOut_2_isEcall), + .io_dataOut_2_isMpause(_instBuffer_io_dataOut_2_isMpause), + .io_dataOut_3_addr(_instBuffer_io_dataOut_3_addr), + .io_dataOut_3_idx(_instBuffer_io_dataOut_3_idx), + .io_dataOut_3_trap(_instBuffer_io_dataOut_3_trap), + .io_dataOut_3_isControlFlow(_instBuffer_io_dataOut_3_isControlFlow), + .io_dataOut_3_isBranch(_instBuffer_io_dataOut_3_isBranch), + .io_dataOut_3_isVector(), + .io_dataOut_3_linkOk(_instBuffer_io_dataOut_3_linkOk), + .io_dataOut_3_isEcall(_instBuffer_io_dataOut_3_isEcall), + .io_dataOut_3_isMpause(_instBuffer_io_dataOut_3_isMpause), + .io_dataOut_4_addr(_instBuffer_io_dataOut_4_addr), + .io_dataOut_4_idx(_instBuffer_io_dataOut_4_idx), + .io_dataOut_4_trap(_instBuffer_io_dataOut_4_trap), + .io_dataOut_4_isControlFlow(_instBuffer_io_dataOut_4_isControlFlow), + .io_dataOut_4_isBranch(_instBuffer_io_dataOut_4_isBranch), + .io_dataOut_4_isVector(), + .io_dataOut_4_linkOk(_instBuffer_io_dataOut_4_linkOk), + .io_dataOut_4_isEcall(_instBuffer_io_dataOut_4_isEcall), + .io_dataOut_4_isMpause(_instBuffer_io_dataOut_4_isMpause), + .io_dataOut_5_addr(_instBuffer_io_dataOut_5_addr), + .io_dataOut_5_idx(_instBuffer_io_dataOut_5_idx), + .io_dataOut_5_trap(_instBuffer_io_dataOut_5_trap), + .io_dataOut_5_isControlFlow(_instBuffer_io_dataOut_5_isControlFlow), + .io_dataOut_5_isBranch(_instBuffer_io_dataOut_5_isBranch), + .io_dataOut_5_isVector(), + .io_dataOut_5_linkOk(_instBuffer_io_dataOut_5_linkOk), + .io_dataOut_5_isEcall(_instBuffer_io_dataOut_5_isEcall), + .io_dataOut_5_isMpause(_instBuffer_io_dataOut_5_isMpause), + .io_dataOut_6_addr(_instBuffer_io_dataOut_6_addr), + .io_dataOut_6_idx(_instBuffer_io_dataOut_6_idx), + .io_dataOut_6_trap(_instBuffer_io_dataOut_6_trap), + .io_dataOut_6_isControlFlow(_instBuffer_io_dataOut_6_isControlFlow), + .io_dataOut_6_isBranch(_instBuffer_io_dataOut_6_isBranch), + .io_dataOut_6_isVector(), + .io_dataOut_6_linkOk(_instBuffer_io_dataOut_6_linkOk), + .io_dataOut_6_isEcall(_instBuffer_io_dataOut_6_isEcall), + .io_dataOut_6_isMpause(_instBuffer_io_dataOut_6_isMpause), + .io_dataOut_7_addr(_instBuffer_io_dataOut_7_addr), + .io_dataOut_7_idx(_instBuffer_io_dataOut_7_idx), + .io_dataOut_7_trap(_instBuffer_io_dataOut_7_trap), + .io_dataOut_7_isControlFlow(_instBuffer_io_dataOut_7_isControlFlow), + .io_dataOut_7_isBranch(_instBuffer_io_dataOut_7_isBranch), + .io_dataOut_7_isVector(), + .io_dataOut_7_linkOk(_instBuffer_io_dataOut_7_linkOk), + .io_dataOut_7_isEcall(_instBuffer_io_dataOut_7_isEcall), + .io_dataOut_7_isMpause(_instBuffer_io_dataOut_7_isMpause), + .io_deqReady(deqReady), + .io_flush(trapReadyToRetire) + ); + assign io_nSpace = {28'h0000000, _instBuffer_io_nSpace}; + assign io_nRetired = deqReady - ({1'h0, {1'h0, {1'h0, |deqReady & _instBuffer_io_dataOut_0_isEcall} + {1'h0, |deqReady[3:1] & _instBuffer_io_dataOut_1_isEcall}} + {1'h0, {1'h0, (deqReady > 4'h2) & _instBuffer_io_dataOut_2_isEcall} + {1'h0, |deqReady[3:2] & _instBuffer_io_dataOut_3_isEcall}}} + {1'h0, {1'h0, {1'h0, (deqReady > 4'h4) & _instBuffer_io_dataOut_4_isEcall} + {1'h0, (deqReady > 4'h5) & _instBuffer_io_dataOut_5_isEcall}} + {1'h0, {1'h0, (deqReady > 4'h6) & _instBuffer_io_dataOut_6_isEcall} + {1'h0, deqReady[3] & _instBuffer_io_dataOut_7_isEcall}}}); + assign io_empty = _instBuffer_io_nEnqueued == 4'h0; + assign io_trapPending = io_trapPending_REG; +endmodule +module Alu ( + clock, + reset, + io_req_valid, + io_req_bits_addr, + io_req_bits_op, + io_rs1_valid, + io_rs1_data, + io_rs2_valid, + io_rs2_data, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data +); + input clock; + input reset; + input io_req_valid; + input [4:0] io_req_bits_addr; + input [4:0] io_req_bits_op; + input io_rs1_valid; + input [31:0] io_rs1_data; + input io_rs2_valid; + input [31:0] io_rs2_data; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + reg valid; + reg [4:0] addr; + reg [4:0] op; + wire r2IsGreater = $signed(io_rs1_data) < $signed(io_rs2_data); + wire r2IsGreaterU = io_rs1_data < io_rs2_data; + wire [31:0] _io_rd_bits_data_T_19 = io_rs1_data ^ io_rs2_data; + wire [62:0] _io_rd_bits_data_T_7 = {31'h00000000, io_rs1_data} << io_rs2_data[4:0]; + wire [31:0] _GEN = {27'h0000000, io_rs2_data[4:0]}; + wire [31:0] _io_rd_bits_data_T_29 = {16'h0000, io_rs1_data[31:16]} | {io_rs1_data[15:0], 16'h0000}; + wire [31:0] _io_rd_bits_data_T_39 = {8'h00, _io_rd_bits_data_T_29[31:8] & 24'hff00ff} | {_io_rd_bits_data_T_29[23:0] & 24'hff00ff, 8'h00}; + wire [31:0] _io_rd_bits_data_T_49 = {4'h0, _io_rd_bits_data_T_39[31:4] & 28'hf0f0f0f} | {_io_rd_bits_data_T_39[27:0] & 28'hf0f0f0f, 4'h0}; + wire [31:0] _io_rd_bits_data_T_59 = {2'h0, _io_rd_bits_data_T_49[31:2] & 30'h33333333} | {_io_rd_bits_data_T_49[29:0] & 30'h33333333, 2'h0}; + wire [31:0] _io_rd_bits_data_T_69 = {1'h0, _io_rd_bits_data_T_59[31:1] & 31'h55555555} | {_io_rd_bits_data_T_59[30:0] & 31'h55555555, 1'h0}; + wire [31:0] _io_rd_bits_data_T_312 = (io_rs2_data[0] ? {io_rs1_data[30:0], io_rs1_data[31]} : io_rs1_data); + wire [31:0] _io_rd_bits_data_T_316 = (io_rs2_data[1] ? {_io_rd_bits_data_T_312[29:0], _io_rd_bits_data_T_312[31:30]} : _io_rd_bits_data_T_312); + wire [31:0] _io_rd_bits_data_T_320 = (io_rs2_data[2] ? {_io_rd_bits_data_T_316[27:0], _io_rd_bits_data_T_316[31:28]} : _io_rd_bits_data_T_316); + wire [31:0] _io_rd_bits_data_T_324 = (io_rs2_data[3] ? {_io_rd_bits_data_T_320[23:0], _io_rd_bits_data_T_320[31:24]} : _io_rd_bits_data_T_320); + wire [31:0] _io_rd_bits_data_T_337 = (io_rs2_data[0] ? {io_rs1_data[0], io_rs1_data[31:1]} : io_rs1_data); + wire [31:0] _io_rd_bits_data_T_341 = (io_rs2_data[1] ? {_io_rd_bits_data_T_337[1:0], _io_rd_bits_data_T_337[31:2]} : _io_rd_bits_data_T_337); + wire [31:0] _io_rd_bits_data_T_345 = (io_rs2_data[2] ? {_io_rd_bits_data_T_341[3:0], _io_rd_bits_data_T_341[31:4]} : _io_rd_bits_data_T_341); + wire [31:0] _io_rd_bits_data_T_349 = (io_rs2_data[3] ? {_io_rd_bits_data_T_345[7:0], _io_rd_bits_data_T_345[31:8]} : _io_rd_bits_data_T_345); + wire [1023:0] _GEN_0 = {144'h000000000000000000000000000000000000, io_rs1_data[15:0], io_rs1_data[7:0], io_rs1_data[15:8], io_rs1_data[23:16], io_rs1_data[31:24], (io_rs1_data[31:24] == 8'h00 ? 8'h00 : 8'hff), (io_rs1_data[23:16] == 8'h00 ? 8'h00 : 8'hff), (io_rs1_data[15:8] == 8'h00 ? 8'h00 : 8'hff), (io_rs1_data[7:0] == 8'h00 ? 8'h00 : 8'hff), (io_rs2_data[4] ? {_io_rd_bits_data_T_349[15:0], _io_rd_bits_data_T_349[31:16]} : _io_rd_bits_data_T_349), (io_rs2_data[4] ? {_io_rd_bits_data_T_324[15:0], _io_rd_bits_data_T_324[31:16]} : _io_rd_bits_data_T_324), {16 {io_rs1_data[15]}}, io_rs1_data[15:0], {24 {io_rs1_data[7]}}, io_rs1_data[7:0], (r2IsGreaterU ? io_rs1_data : io_rs2_data), (r2IsGreater ? io_rs1_data : io_rs2_data), (r2IsGreaterU ? io_rs2_data : io_rs1_data), (r2IsGreater ? io_rs2_data : io_rs1_data), 26'h0000000, {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, io_rs1_data[0]} + {1'h0, io_rs1_data[1]}} + {1'h0, {1'h0, io_rs1_data[2]} + {1'h0, io_rs1_data[3]}}} + {1'h0, {1'h0, {1'h0, io_rs1_data[4]} + {1'h0, io_rs1_data[5]}} + {1'h0, {1'h0, io_rs1_data[6]} + {1'h0, io_rs1_data[7]}}}} + {1'h0, {1'h0, {1'h0, {1'h0, io_rs1_data[8]} + {1'h0, io_rs1_data[9]}} + {1'h0, {1'h0, io_rs1_data[10]} + {1'h0, io_rs1_data[11]}}} + {1'h0, {1'h0, {1'h0, io_rs1_data[12]} + {1'h0, io_rs1_data[13]}} + {1'h0, {1'h0, io_rs1_data[14]} + {1'h0, io_rs1_data[15]}}}}} + {1'h0, {1'h0, {1'h0, {1'h0, {1'h0, io_rs1_data[16]} + {1'h0, io_rs1_data[17]}} + {1'h0, {1'h0, io_rs1_data[18]} + {1'h0, io_rs1_data[19]}}} + {1'h0, {1'h0, {1'h0, io_rs1_data[20]} + {1'h0, io_rs1_data[21]}} + {1'h0, {1'h0, io_rs1_data[22]} + {1'h0, io_rs1_data[23]}}}} + {1'h0, {1'h0, {1'h0, {1'h0, io_rs1_data[24]} + {1'h0, io_rs1_data[25]}} + {1'h0, {1'h0, io_rs1_data[26]} + {1'h0, io_rs1_data[27]}}} + {1'h0, {1'h0, {1'h0, io_rs1_data[28]} + {1'h0, io_rs1_data[29]}} + {1'h0, {1'h0, io_rs1_data[30]} + {1'h0, io_rs1_data[31]}}}}}, 26'h0000000, (io_rs1_data[0] ? 6'h00 : (io_rs1_data[1] ? 6'h01 : (io_rs1_data[2] ? 6'h02 : (io_rs1_data[3] ? 6'h03 : (io_rs1_data[4] ? 6'h04 : (io_rs1_data[5] ? 6'h05 : (io_rs1_data[6] ? 6'h06 : (io_rs1_data[7] ? 6'h07 : (io_rs1_data[8] ? 6'h08 : (io_rs1_data[9] ? 6'h09 : (io_rs1_data[10] ? 6'h0a : (io_rs1_data[11] ? 6'h0b : (io_rs1_data[12] ? 6'h0c : (io_rs1_data[13] ? 6'h0d : (io_rs1_data[14] ? 6'h0e : (io_rs1_data[15] ? 6'h0f : (io_rs1_data[16] ? 6'h10 : (io_rs1_data[17] ? 6'h11 : (io_rs1_data[18] ? 6'h12 : (io_rs1_data[19] ? 6'h13 : (io_rs1_data[20] ? 6'h14 : (io_rs1_data[21] ? 6'h15 : (io_rs1_data[22] ? 6'h16 : (io_rs1_data[23] ? 6'h17 : (io_rs1_data[24] ? 6'h18 : (io_rs1_data[25] ? 6'h19 : (io_rs1_data[26] ? 6'h1a : (io_rs1_data[27] ? 6'h1b : (io_rs1_data[28] ? 6'h1c : (io_rs1_data[29] ? 6'h1d : (io_rs1_data[30] ? 6'h1e : (io_rs1_data[31] ? 6'h1f : 6'h20)))))))))))))))))))))))))))))))), 26'h0000000, (_io_rd_bits_data_T_69[0] ? 6'h00 : (_io_rd_bits_data_T_69[1] ? 6'h01 : (_io_rd_bits_data_T_69[2] ? 6'h02 : (_io_rd_bits_data_T_69[3] ? 6'h03 : (_io_rd_bits_data_T_69[4] ? 6'h04 : (_io_rd_bits_data_T_69[5] ? 6'h05 : (_io_rd_bits_data_T_69[6] ? 6'h06 : (_io_rd_bits_data_T_69[7] ? 6'h07 : (_io_rd_bits_data_T_69[8] ? 6'h08 : (_io_rd_bits_data_T_69[9] ? 6'h09 : (_io_rd_bits_data_T_69[10] ? 6'h0a : (_io_rd_bits_data_T_69[11] ? 6'h0b : (_io_rd_bits_data_T_69[12] ? 6'h0c : (_io_rd_bits_data_T_69[13] ? 6'h0d : (_io_rd_bits_data_T_69[14] ? 6'h0e : (_io_rd_bits_data_T_69[15] ? 6'h0f : (_io_rd_bits_data_T_69[16] ? 6'h10 : (_io_rd_bits_data_T_69[17] ? 6'h11 : (_io_rd_bits_data_T_69[18] ? 6'h12 : (_io_rd_bits_data_T_69[19] ? 6'h13 : (_io_rd_bits_data_T_69[20] ? 6'h14 : (_io_rd_bits_data_T_69[21] ? 6'h15 : (_io_rd_bits_data_T_69[22] ? 6'h16 : (_io_rd_bits_data_T_69[23] ? 6'h17 : (_io_rd_bits_data_T_69[24] ? 6'h18 : (_io_rd_bits_data_T_69[25] ? 6'h19 : (_io_rd_bits_data_T_69[26] ? 6'h1a : (_io_rd_bits_data_T_69[27] ? 6'h1b : (_io_rd_bits_data_T_69[28] ? 6'h1c : (_io_rd_bits_data_T_69[29] ? 6'h1d : (_io_rd_bits_data_T_69[30] ? 6'h1e : (_io_rd_bits_data_T_69[31] ? 6'h1f : 6'h20)))))))))))))))))))))))))))))))), ~_io_rd_bits_data_T_19, io_rs1_data | ~io_rs2_data, io_rs1_data & ~io_rs2_data, io_rs2_data, $signed($signed(io_rs1_data) >>> _GEN), io_rs1_data >> _GEN, _io_rd_bits_data_T_7[31:0], io_rs1_data & io_rs2_data, io_rs1_data | io_rs2_data, _io_rd_bits_data_T_19, 31'h00000000, r2IsGreaterU, 31'h00000000, r2IsGreater, io_rs1_data - io_rs2_data, io_rs1_data + io_rs2_data}; + always @(posedge clock or posedge reset) + if (reset) begin + valid <= 1'h0; + addr <= 5'h00; + op <= 5'h00; + end + else begin + valid <= io_req_valid; + if (io_req_valid) begin + addr <= io_req_bits_addr; + op <= io_req_bits_op; + end + end + assign io_rd_valid = valid; + assign io_rd_bits_addr = addr; + assign io_rd_bits_data = _GEN_0[op * 32+:32]; +endmodule +module Bru ( + clock, + reset, + io_req_valid, + io_req_bits_fwd, + io_req_bits_op, + io_req_bits_pc, + io_req_bits_target, + io_req_bits_link, + io_csr_in_mode_valid, + io_csr_in_mode_bits, + io_csr_in_mcause_valid, + io_csr_in_mcause_bits, + io_csr_in_mepc_valid, + io_csr_in_mepc_bits, + io_csr_in_mtval_valid, + io_csr_in_mtval_bits, + io_csr_in_halt, + io_csr_in_fault, + io_csr_in_wfi, + io_csr_out_mode, + io_csr_out_mepc, + io_csr_out_mtvec, + io_rs1_valid, + io_rs1_data, + io_rs2_valid, + io_rs2_data, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data, + io_taken_valid, + io_taken_value, + io_target_data, + io_interlock, + io_fault_manager_valid, + io_fault_manager_bits_mepc, + io_fault_manager_bits_mtval, + io_fault_manager_bits_mcause +); + input clock; + input reset; + input io_req_valid; + input io_req_bits_fwd; + input [3:0] io_req_bits_op; + input [31:0] io_req_bits_pc; + input [31:0] io_req_bits_target; + input [4:0] io_req_bits_link; + output wire io_csr_in_mode_valid; + output wire [1:0] io_csr_in_mode_bits; + output wire io_csr_in_mcause_valid; + output wire [31:0] io_csr_in_mcause_bits; + output wire io_csr_in_mepc_valid; + output wire [31:0] io_csr_in_mepc_bits; + output wire io_csr_in_mtval_valid; + output wire [31:0] io_csr_in_mtval_bits; + output wire io_csr_in_halt; + output wire io_csr_in_fault; + output wire io_csr_in_wfi; + input [1:0] io_csr_out_mode; + input [31:0] io_csr_out_mepc; + input [31:0] io_csr_out_mtvec; + input io_rs1_valid; + input [31:0] io_rs1_data; + input io_rs2_valid; + input [31:0] io_rs2_data; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + output wire io_taken_valid; + output wire [31:0] io_taken_value; + input [31:0] io_target_data; + output wire io_interlock; + input io_fault_manager_valid; + input [31:0] io_fault_manager_bits_mepc; + input [31:0] io_fault_manager_bits_mtval; + input [31:0] io_fault_manager_bits_mcause; + wire io_csr_in_fault_0; + reg stateReg_valid; + reg stateReg_bits_fwd; + reg [3:0] stateReg_bits_op; + reg [31:0] stateReg_bits_target; + reg stateReg_bits_linkValid; + reg [4:0] stateReg_bits_linkAddr; + reg [31:0] stateReg_bits_linkData; + reg [31:0] stateReg_bits_pcEx; + wire _io_csr_in_fault_T = io_csr_out_mode == 2'h0; + wire _io_csr_in_mcause_bits_T_4 = io_csr_out_mode == 2'h1; + wire _ignore_T_2 = stateReg_bits_op == 4'h8; + wire _ignore_T_3 = stateReg_bits_op == 4'h9; + wire _ignore_T_4 = stateReg_bits_op == 4'ha; + wire _ignore_T_5 = stateReg_bits_op == 4'hb; + wire _ignore_T_7 = stateReg_bits_op == 4'hd; + wire usageFault = stateReg_valid & (_io_csr_in_mcause_bits_T_4 ? |{_ignore_T_5, _ignore_T_4} : _ignore_T_2); + assign io_csr_in_fault_0 = usageFault & _io_csr_in_fault_T; + wire _ignore_T_6 = stateReg_bits_op == 4'hc; + wire [31:0] nextState_linkData = io_req_bits_pc + 32'h00000004; + wire _nextState_target_T = io_req_bits_op == 4'h1; + wire [31:0] mtvec = {io_csr_out_mtvec[31:2], 2'h0}; + wire _pipeline0Target_call_T = io_req_bits_op == 4'hb; + wire stateRegValid = io_req_valid | io_fault_manager_valid; + always @(posedge clock or posedge reset) + if (reset) begin + stateReg_valid <= 1'h0; + stateReg_bits_fwd <= 1'h0; + stateReg_bits_op <= 4'h0; + stateReg_bits_target <= 32'h00000000; + stateReg_bits_linkValid <= 1'h0; + stateReg_bits_linkAddr <= 5'h00; + stateReg_bits_linkData <= 32'h00000000; + stateReg_bits_pcEx <= 32'h00000000; + end + else begin + stateReg_valid <= stateRegValid; + if (stateRegValid) begin + stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; + stateReg_bits_op <= (io_fault_manager_valid ? 4'hd : io_req_bits_op); + stateReg_bits_target <= (io_fault_manager_valid ? mtvec : (io_req_bits_fwd ? nextState_linkData : (_nextState_target_T ? io_target_data & 32'hfffffffe : (io_req_bits_op == 4'h9 ? mtvec : (|{_pipeline0Target_call_T & _io_csr_in_fault_T, _pipeline0Target_call_T & _io_csr_in_mcause_bits_T_4, io_req_bits_op == 4'ha, io_req_bits_op == 4'h8} ? io_csr_out_mepc : (io_req_bits_op == 4'hc ? nextState_linkData : io_req_bits_target)))))); + stateReg_bits_linkValid <= (io_req_valid & |io_req_bits_link) & |{_nextState_target_T, io_req_bits_op == 4'h0}; + stateReg_bits_linkAddr <= io_req_bits_link; + stateReg_bits_linkData <= nextState_linkData; + stateReg_bits_pcEx <= io_req_bits_pc; + end + end + assign io_csr_in_mode_valid = stateReg_valid & (_io_csr_in_mcause_bits_T_4 ? |{_ignore_T_7, _ignore_T_5, _ignore_T_4, _ignore_T_3, _ignore_T_2} : _ignore_T_5); + assign io_csr_in_mode_bits = {1'h0, ~(_ignore_T_5 & _io_csr_in_fault_T)}; + assign io_csr_in_mcause_valid = (stateReg_valid & ((usageFault | _ignore_T_3) | (_io_csr_in_mcause_bits_T_4 & _ignore_T_2))) | io_fault_manager_valid; + assign io_csr_in_mcause_bits = (io_fault_manager_valid ? io_fault_manager_bits_mcause : {27'h0000000, (_ignore_T_3 & _io_csr_in_fault_T ? 5'h0b : (_ignore_T_3 & _io_csr_in_mcause_bits_T_4 ? 5'h08 : (_ignore_T_2 ? 5'h03 : (usageFault ? 5'h19 : 5'h00))))}); + assign io_csr_in_mepc_valid = (stateReg_valid & _ignore_T_3) | io_fault_manager_valid; + assign io_csr_in_mepc_bits = (io_fault_manager_valid ? io_fault_manager_bits_mepc : stateReg_bits_pcEx); + assign io_csr_in_mtval_valid = usageFault | io_fault_manager_valid; + assign io_csr_in_mtval_bits = (io_fault_manager_valid ? io_fault_manager_bits_mtval : stateReg_bits_pcEx); + assign io_csr_in_halt = ((stateReg_valid & _ignore_T_4) & _io_csr_in_fault_T) | io_csr_in_fault_0; + assign io_csr_in_fault = io_csr_in_fault_0; + assign io_csr_in_wfi = stateReg_valid & _ignore_T_6; + assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; + assign io_rd_bits_addr = stateReg_bits_linkAddr; + assign io_rd_bits_data = stateReg_bits_linkData; + assign io_taken_valid = stateReg_valid & ((stateReg_bits_op == 4'hd) | (stateReg_bits_op == 4'h7 ? (io_rs1_data >= io_rs2_data) != stateReg_bits_fwd : (stateReg_bits_op == 4'h6 ? (io_rs1_data < io_rs2_data) != stateReg_bits_fwd : (stateReg_bits_op == 4'h5 ? ($signed(io_rs1_data) >= $signed(io_rs2_data)) != stateReg_bits_fwd : (stateReg_bits_op == 4'h4 ? ($signed(io_rs1_data) < $signed(io_rs2_data)) != stateReg_bits_fwd : (stateReg_bits_op == 4'h3 ? (io_rs1_data != io_rs2_data) != stateReg_bits_fwd : (stateReg_bits_op == 4'h2 ? (io_rs1_data == io_rs2_data) != stateReg_bits_fwd : ((stateReg_bits_op == 4'h1) | ~(|stateReg_bits_op) ? ~stateReg_bits_fwd : (stateReg_bits_op == 4'hc) | (stateReg_bits_op == 4'hb ? _io_csr_in_fault_T : (stateReg_bits_op == 4'ha ? _io_csr_in_mcause_bits_T_4 : (stateReg_bits_op == 4'h9) | ((stateReg_bits_op == 4'h8) & _io_csr_in_mcause_bits_T_4))))))))))); + assign io_taken_value = stateReg_bits_target; + assign io_interlock = stateReg_valid & |{_ignore_T_7, _ignore_T_5, _ignore_T_4, _ignore_T_3, _ignore_T_2}; +endmodule +module Bru_1 ( + clock, + reset, + io_req_valid, + io_req_bits_fwd, + io_req_bits_op, + io_req_bits_pc, + io_req_bits_target, + io_req_bits_link, + io_rs1_valid, + io_rs1_data, + io_rs2_valid, + io_rs2_data, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data, + io_taken_valid, + io_taken_value, + io_target_data +); + input clock; + input reset; + input io_req_valid; + input io_req_bits_fwd; + input [3:0] io_req_bits_op; + input [31:0] io_req_bits_pc; + input [31:0] io_req_bits_target; + input [4:0] io_req_bits_link; + input io_rs1_valid; + input [31:0] io_rs1_data; + input io_rs2_valid; + input [31:0] io_rs2_data; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + output wire io_taken_valid; + output wire [31:0] io_taken_value; + input [31:0] io_target_data; + reg stateReg_valid; + reg stateReg_bits_fwd; + reg [3:0] stateReg_bits_op; + reg [31:0] stateReg_bits_target; + reg stateReg_bits_linkValid; + reg [4:0] stateReg_bits_linkAddr; + reg [31:0] stateReg_bits_linkData; + wire _ignore_T_2 = stateReg_bits_op == 4'h8; + wire _ignore_T_3 = stateReg_bits_op == 4'h9; + wire _ignore_T_4 = stateReg_bits_op == 4'ha; + wire _ignore_T_5 = stateReg_bits_op == 4'hb; + wire _ignore_T_6 = stateReg_bits_op == 4'hc; + wire [31:0] nextState_linkData = io_req_bits_pc + 32'h00000004; + wire _nextState_target_T = io_req_bits_op == 4'h1; + always @(posedge clock or posedge reset) + if (reset) begin + stateReg_valid <= 1'h0; + stateReg_bits_fwd <= 1'h0; + stateReg_bits_op <= 4'h0; + stateReg_bits_target <= 32'h00000000; + stateReg_bits_linkValid <= 1'h0; + stateReg_bits_linkAddr <= 5'h00; + stateReg_bits_linkData <= 32'h00000000; + end + else begin + stateReg_valid <= io_req_valid; + if (io_req_valid) begin + stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; + stateReg_bits_op <= io_req_bits_op; + stateReg_bits_target <= (io_req_bits_fwd ? nextState_linkData : (_nextState_target_T ? io_target_data & 32'hfffffffe : io_req_bits_target)); + stateReg_bits_linkValid <= (io_req_valid & |io_req_bits_link) & |{_nextState_target_T, io_req_bits_op == 4'h0}; + stateReg_bits_linkAddr <= io_req_bits_link; + stateReg_bits_linkData <= nextState_linkData; + end + end + assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; + assign io_rd_bits_addr = stateReg_bits_linkAddr; + assign io_rd_bits_data = stateReg_bits_linkData; + assign io_taken_valid = stateReg_valid & ((stateReg_bits_op == 4'hd) | (stateReg_bits_op == 4'h7 ? (io_rs1_data >= io_rs2_data) != stateReg_bits_fwd : (stateReg_bits_op == 4'h6 ? (io_rs1_data < io_rs2_data) != stateReg_bits_fwd : (stateReg_bits_op == 4'h5 ? ($signed(io_rs1_data) >= $signed(io_rs2_data)) != stateReg_bits_fwd : (stateReg_bits_op == 4'h4 ? ($signed(io_rs1_data) < $signed(io_rs2_data)) != stateReg_bits_fwd : (stateReg_bits_op == 4'h3 ? (io_rs1_data != io_rs2_data) != stateReg_bits_fwd : (stateReg_bits_op == 4'h2 ? (io_rs1_data == io_rs2_data) != stateReg_bits_fwd : ((stateReg_bits_op == 4'h1) | ~(|stateReg_bits_op)) & ~stateReg_bits_fwd))))))); + assign io_taken_value = stateReg_bits_target; +endmodule +module Arbiter4_MluCmd ( + io_in_0_valid, + io_in_0_bits_addr, + io_in_0_bits_op, + io_in_1_ready, + io_in_1_valid, + io_in_1_bits_addr, + io_in_1_bits_op, + io_in_2_ready, + io_in_2_valid, + io_in_2_bits_addr, + io_in_2_bits_op, + io_in_3_ready, + io_in_3_valid, + io_in_3_bits_addr, + io_in_3_bits_op, + io_out_valid, + io_out_bits_addr, + io_out_bits_op, + io_chosen +); + input io_in_0_valid; + input [4:0] io_in_0_bits_addr; + input [2:0] io_in_0_bits_op; + output wire io_in_1_ready; + input io_in_1_valid; + input [4:0] io_in_1_bits_addr; + input [2:0] io_in_1_bits_op; + output wire io_in_2_ready; + input io_in_2_valid; + input [4:0] io_in_2_bits_addr; + input [2:0] io_in_2_bits_op; + output wire io_in_3_ready; + input io_in_3_valid; + input [4:0] io_in_3_bits_addr; + input [2:0] io_in_3_bits_op; + output wire io_out_valid; + output wire [4:0] io_out_bits_addr; + output wire [2:0] io_out_bits_op; + output wire [1:0] io_chosen; + wire _grant_T = io_in_0_valid | io_in_1_valid; + wire _io_out_valid_T = _grant_T | io_in_2_valid; + assign io_in_1_ready = ~io_in_0_valid; + assign io_in_2_ready = ~_grant_T; + assign io_in_3_ready = ~_io_out_valid_T; + assign io_out_valid = _io_out_valid_T | io_in_3_valid; + assign io_out_bits_addr = (io_in_0_valid ? io_in_0_bits_addr : (io_in_1_valid ? io_in_1_bits_addr : (io_in_2_valid ? io_in_2_bits_addr : io_in_3_bits_addr))); + assign io_out_bits_op = (io_in_0_valid ? io_in_0_bits_op : (io_in_1_valid ? io_in_1_bits_op : (io_in_2_valid ? io_in_2_bits_op : io_in_3_bits_op))); + assign io_chosen = (io_in_0_valid ? 2'h0 : (io_in_1_valid ? 2'h1 : {1'h1, ~io_in_2_valid})); +endmodule +module Queue1_MluStage1 ( + clock, + reset, + io_enq_valid, + io_enq_bits_rd, + io_enq_bits_op, + io_enq_bits_sel, + io_deq_valid, + io_deq_bits_rd, + io_deq_bits_op, + io_deq_bits_sel +); + input clock; + input reset; + input io_enq_valid; + input [4:0] io_enq_bits_rd; + input [2:0] io_enq_bits_op; + input [3:0] io_enq_bits_sel; + output wire io_deq_valid; + output wire [4:0] io_deq_bits_rd; + output wire [2:0] io_deq_bits_op; + output wire [3:0] io_deq_bits_sel; + reg [11:0] ram; + reg full; + always @(posedge clock or posedge reset) + if (reset) + full <= 1'h0; + else if (~(io_enq_valid == full)) + full <= io_enq_valid; + always @(posedge clock) + if (io_enq_valid) + ram <= {io_enq_bits_rd, io_enq_bits_op, io_enq_bits_sel}; + assign io_deq_valid = full; + assign io_deq_bits_rd = ram[11:7]; + assign io_deq_bits_op = ram[6:4]; + assign io_deq_bits_sel = ram[3:0]; +endmodule +module Queue1_MluStage2 ( + clock, + reset, + io_enq_valid, + io_enq_bits_rd, + io_enq_bits_op, + io_enq_bits_prod, + io_deq_valid, + io_deq_bits_rd, + io_deq_bits_op, + io_deq_bits_prod +); + input clock; + input reset; + input io_enq_valid; + input [4:0] io_enq_bits_rd; + input [2:0] io_enq_bits_op; + input [65:0] io_enq_bits_prod; + output wire io_deq_valid; + output wire [4:0] io_deq_bits_rd; + output wire [2:0] io_deq_bits_op; + output wire [65:0] io_deq_bits_prod; + reg [73:0] ram; + reg full; + always @(posedge clock or posedge reset) + if (reset) + full <= 1'h0; + else if (~(io_enq_valid == full)) + full <= io_enq_valid; + always @(posedge clock) + if (io_enq_valid) + ram <= {io_enq_bits_rd, io_enq_bits_op, io_enq_bits_prod}; + assign io_deq_valid = full; + assign io_deq_bits_rd = ram[73:69]; + assign io_deq_bits_op = ram[68:66]; + assign io_deq_bits_prod = ram[65:0]; +endmodule +module Mlu ( + clock, + reset, + io_req_0_valid, + io_req_0_bits_addr, + io_req_0_bits_op, + io_req_1_ready, + io_req_1_valid, + io_req_1_bits_addr, + io_req_1_bits_op, + io_req_2_ready, + io_req_2_valid, + io_req_2_bits_addr, + io_req_2_bits_op, + io_req_3_ready, + io_req_3_valid, + io_req_3_bits_addr, + io_req_3_bits_op, + io_rs1_0_valid, + io_rs1_0_data, + io_rs1_1_valid, + io_rs1_1_data, + io_rs1_2_valid, + io_rs1_2_data, + io_rs1_3_valid, + io_rs1_3_data, + io_rs2_0_valid, + io_rs2_0_data, + io_rs2_1_valid, + io_rs2_1_data, + io_rs2_2_valid, + io_rs2_2_data, + io_rs2_3_valid, + io_rs2_3_data, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data +); + input clock; + input reset; + input io_req_0_valid; + input [4:0] io_req_0_bits_addr; + input [2:0] io_req_0_bits_op; + output wire io_req_1_ready; + input io_req_1_valid; + input [4:0] io_req_1_bits_addr; + input [2:0] io_req_1_bits_op; + output wire io_req_2_ready; + input io_req_2_valid; + input [4:0] io_req_2_bits_addr; + input [2:0] io_req_2_bits_op; + output wire io_req_3_ready; + input io_req_3_valid; + input [4:0] io_req_3_bits_addr; + input [2:0] io_req_3_bits_op; + input io_rs1_0_valid; + input [31:0] io_rs1_0_data; + input io_rs1_1_valid; + input [31:0] io_rs1_1_data; + input io_rs1_2_valid; + input [31:0] io_rs1_2_data; + input io_rs1_3_valid; + input [31:0] io_rs1_3_data; + input io_rs2_0_valid; + input [31:0] io_rs2_0_data; + input io_rs2_1_valid; + input [31:0] io_rs2_1_data; + input io_rs2_2_valid; + input [31:0] io_rs2_2_data; + input io_rs2_3_valid; + input [31:0] io_rs2_3_data; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + wire [2:0] _stage3Input_q_io_deq_bits_op; + wire [65:0] _stage3Input_q_io_deq_bits_prod; + wire _stage2Input_q_io_deq_valid; + wire [4:0] _stage2Input_q_io_deq_bits_rd; + wire [2:0] _stage2Input_q_io_deq_bits_op; + wire [3:0] _stage2Input_q_io_deq_bits_sel; + wire _arb_io_out_valid; + wire [4:0] _arb_io_out_bits_addr; + wire [2:0] _arb_io_out_bits_op; + wire [1:0] _arb_io_chosen; + wire [31:0] rs1 = (((_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[0] ? io_rs1_0_data : 32'h00000000) | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[1] ? io_rs1_1_data : 32'h00000000)) | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[2] ? io_rs1_2_data : 32'h00000000)) | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[3] ? io_rs1_3_data : 32'h00000000); + wire [31:0] rs2 = (((_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[0] ? io_rs2_0_data : 32'h00000000) | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[1] ? io_rs2_1_data : 32'h00000000)) | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[2] ? io_rs2_2_data : 32'h00000000)) | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[3] ? io_rs2_3_data : 32'h00000000); + wire rs2signed = _stage2Input_q_io_deq_bits_op == 3'h1; + Arbiter4_MluCmd arb( + .io_in_0_valid(io_req_0_valid), + .io_in_0_bits_addr(io_req_0_bits_addr), + .io_in_0_bits_op(io_req_0_bits_op), + .io_in_1_ready(io_req_1_ready), + .io_in_1_valid(io_req_1_valid), + .io_in_1_bits_addr(io_req_1_bits_addr), + .io_in_1_bits_op(io_req_1_bits_op), + .io_in_2_ready(io_req_2_ready), + .io_in_2_valid(io_req_2_valid), + .io_in_2_bits_addr(io_req_2_bits_addr), + .io_in_2_bits_op(io_req_2_bits_op), + .io_in_3_ready(io_req_3_ready), + .io_in_3_valid(io_req_3_valid), + .io_in_3_bits_addr(io_req_3_bits_addr), + .io_in_3_bits_op(io_req_3_bits_op), + .io_out_valid(_arb_io_out_valid), + .io_out_bits_addr(_arb_io_out_bits_addr), + .io_out_bits_op(_arb_io_out_bits_op), + .io_chosen(_arb_io_chosen) + ); + Queue1_MluStage1 stage2Input_q( + .clock(clock), + .reset(reset), + .io_enq_valid(_arb_io_out_valid), + .io_enq_bits_rd(_arb_io_out_bits_addr), + .io_enq_bits_op(_arb_io_out_bits_op), + .io_enq_bits_sel(4'h1 << _arb_io_chosen), + .io_deq_valid(_stage2Input_q_io_deq_valid), + .io_deq_bits_rd(_stage2Input_q_io_deq_bits_rd), + .io_deq_bits_op(_stage2Input_q_io_deq_bits_op), + .io_deq_bits_sel(_stage2Input_q_io_deq_bits_sel) + ); + Queue1_MluStage2 stage3Input_q( + .clock(clock), + .reset(reset), + .io_enq_valid(_stage2Input_q_io_deq_valid), + .io_enq_bits_rd(_stage2Input_q_io_deq_bits_rd), + .io_enq_bits_op(_stage2Input_q_io_deq_bits_op), + .io_enq_bits_prod({{34 {((_stage2Input_q_io_deq_bits_op == 3'h2) | rs2signed) & rs1[31]}}, rs1} * {{34 {rs2signed & rs2[31]}}, rs2}), + .io_deq_valid(io_rd_valid), + .io_deq_bits_rd(io_rd_bits_addr), + .io_deq_bits_op(_stage3Input_q_io_deq_bits_op), + .io_deq_bits_prod(_stage3Input_q_io_deq_bits_prod) + ); + assign io_rd_bits_data = (_stage3Input_q_io_deq_bits_op == 3'h0 ? _stage3Input_q_io_deq_bits_prod[31:0] : _stage3Input_q_io_deq_bits_prod[63:32]); +endmodule +module Dvu ( + clock, + reset, + io_req_ready, + io_req_valid, + io_req_bits_addr, + io_req_bits_op, + io_rs1_data, + io_rs2_data, + io_rd_ready, + io_rd_valid, + io_rd_bits_addr, + io_rd_bits_data +); + input clock; + input reset; + output wire io_req_ready; + input io_req_valid; + input [4:0] io_req_bits_addr; + input [1:0] io_req_bits_op; + input [31:0] io_rs1_data; + input [31:0] io_rs2_data; + input io_rd_ready; + output wire io_rd_valid; + output wire [4:0] io_rd_bits_addr; + output wire [31:0] io_rd_bits_data; + reg active; + reg compute; + reg [4:0] addr1; + reg signed1; + reg divide1; + reg [4:0] addr2; + reg signed2d; + reg signed2r; + reg divide2; + reg [5:0] count; + reg [31:0] divide; + reg [31:0] remain; + reg [31:0] denom; + wire io_req_ready_0 = (~active & ~compute) & ~count[5]; + wire _divide1_T_1 = io_req_bits_op == 2'h0; + wire [31:0] inp = (signed1 & io_rs1_data[31] ? ~io_rs1_data + 32'h00000001 : io_rs1_data); + wire [15:0] _clz_T_12 = {8'h00, inp[15:8]} | {inp[7:0], 8'h00}; + wire [15:0] _clz_T_22 = {4'h0, _clz_T_12[15:4] & 12'hf0f} | {_clz_T_12[11:0] & 12'hf0f, 4'h0}; + wire [15:0] _clz_T_32 = {2'h0, _clz_T_22[15:2] & 14'h3333} | {_clz_T_22[13:0] & 14'h3333, 2'h0}; + wire [14:0] _clz_T_42 = (_clz_T_32[15:1] & 15'h5555) | {1'h0, _clz_T_32[12:0] & 13'h1555, 1'h0}; + wire [7:0] _clz_T_53 = {4'h0, inp[23:20]} | {inp[19:16], 4'h0}; + wire [7:0] _clz_T_63 = {2'h0, _clz_T_53[7:2] & 6'h33} | {_clz_T_53[5:0] & 6'h33, 2'h0}; + wire [7:0] _clz_T_73 = {1'h0, _clz_T_63[7:1] & 7'h55} | {_clz_T_63[6:0] & 7'h55, 1'h0}; + wire [4:0] clz = ((~(|io_rs2_data) | inp[31]) | inp[30] ? 5'h00 : (inp[29] ? 5'h01 : (inp[28] ? 5'h02 : (inp[27] ? 5'h03 : (inp[26] ? 5'h04 : (inp[25] ? 5'h05 : (inp[24] ? 5'h06 : (_clz_T_73[0] ? 5'h07 : (_clz_T_73[1] ? 5'h08 : (_clz_T_73[2] ? 5'h09 : (_clz_T_73[3] ? 5'h0a : (_clz_T_73[4] ? 5'h0b : (_clz_T_73[5] ? 5'h0c : (_clz_T_73[6] ? 5'h0d : (_clz_T_73[7] ? 5'h0e : (_clz_T_42[0] ? 5'h0f : (_clz_T_42[1] ? 5'h10 : (_clz_T_42[2] ? 5'h11 : (_clz_T_42[3] ? 5'h12 : (_clz_T_42[4] ? 5'h13 : (_clz_T_42[5] ? 5'h14 : (_clz_T_42[6] ? 5'h15 : (_clz_T_42[7] ? 5'h16 : (_clz_T_42[8] ? 5'h17 : (_clz_T_42[9] ? 5'h18 : (_clz_T_42[10] ? 5'h19 : (_clz_T_42[11] ? 5'h1a : (_clz_T_42[12] ? 5'h1b : (_clz_T_42[13] ? 5'h1c : (_clz_T_42[14] ? 5'h1d : 5'h1e)))))))))))))))))))))))))))))); + wire [62:0] _divide_T = {31'h00000000, inp} << clz; + wire [32:0] subtract = {1'h0, remain[30:0], divide[31]} - {1'h0, denom}; + wire _divide1_T = io_req_valid & io_req_ready_0; + always @(posedge clock or posedge reset) + if (reset) begin + active <= 1'h0; + compute <= 1'h0; + addr1 <= 5'h00; + signed1 <= 1'h0; + divide1 <= 1'h0; + addr2 <= 5'h00; + signed2d <= 1'h0; + signed2r <= 1'h0; + divide2 <= 1'h0; + count <= 6'h00; + divide <= 32'h00000000; + remain <= 32'h00000000; + denom <= 32'h00000000; + end + else begin + active <= _divide1_T | ((count != 6'h1e) & active); + compute <= active; + if (_divide1_T) begin + addr1 <= io_req_bits_addr; + signed1 <= |{io_req_bits_op == 2'h2, _divide1_T_1}; + divide1 <= |{io_req_bits_op == 2'h1, _divide1_T_1}; + end + if (active & ~compute) begin + addr2 <= addr1; + signed2d <= (signed1 & (io_rs1_data[31] != io_rs2_data[31])) & |io_rs2_data; + signed2r <= signed1 & io_rs1_data[31]; + divide2 <= divide1; + count <= {1'h0, clz}; + divide <= _divide_T[31:0]; + remain <= 32'h00000000; + denom <= (signed1 & io_rs2_data[31] ? ~io_rs2_data + 32'h00000001 : io_rs2_data); + end + else if (compute & ~count[5]) begin + count <= count + 6'h01; + divide <= (subtract[32] ? {divide[30:0], 1'h0} : {divide[30:0], 1'h1}); + remain <= (subtract[32] ? {remain[30:0], divide[31]} : subtract[31:0]); + end + else if (count[5] & io_rd_ready) + count <= 6'h00; + end + assign io_req_ready = io_req_ready_0; + assign io_rd_valid = count[5]; + assign io_rd_bits_addr = addr2; + assign io_rd_bits_data = (divide2 ? (signed2d ? ~divide + 32'h00000001 : divide) : (signed2r ? ~remain + 32'h00000001 : remain)); +endmodule +module Queue1_FloatInstruction ( + clock, + reset, + io_enq_valid, + io_enq_bits_opcode, + io_enq_bits_funct5, + io_enq_bits_rs3, + io_enq_bits_rs2, + io_enq_bits_rs1, + io_enq_bits_rm, + io_enq_bits_inst, + io_enq_bits_pc, + io_enq_bits_scalar_rd, + io_enq_bits_scalar_rs1, + io_enq_bits_float_rs1, + io_enq_bits_rd, + io_enq_bits_uses_rs3, + io_enq_bits_uses_rs2, + io_deq_ready, + io_deq_valid, + io_deq_bits_opcode, + io_deq_bits_funct5, + io_deq_bits_rs3, + io_deq_bits_rs2, + io_deq_bits_rs1, + io_deq_bits_rm, + io_deq_bits_scalar_rd, + io_deq_bits_rd, + io_count +); + input clock; + input reset; + input io_enq_valid; + input [2:0] io_enq_bits_opcode; + input [4:0] io_enq_bits_funct5; + input [4:0] io_enq_bits_rs3; + input [4:0] io_enq_bits_rs2; + input [4:0] io_enq_bits_rs1; + input [2:0] io_enq_bits_rm; + input [31:0] io_enq_bits_inst; + input [31:0] io_enq_bits_pc; + input io_enq_bits_scalar_rd; + input io_enq_bits_scalar_rs1; + input io_enq_bits_float_rs1; + input [4:0] io_enq_bits_rd; + input io_enq_bits_uses_rs3; + input io_enq_bits_uses_rs2; + input io_deq_ready; + output wire io_deq_valid; + output wire [2:0] io_deq_bits_opcode; + output wire [4:0] io_deq_bits_funct5; + output wire [4:0] io_deq_bits_rs3; + output wire [4:0] io_deq_bits_rs2; + output wire [4:0] io_deq_bits_rs1; + output wire [2:0] io_deq_bits_rm; + output wire io_deq_bits_scalar_rd; + output wire [4:0] io_deq_bits_rd; + output wire io_count; + reg [99:0] ram; + wire io_enq_ready; + reg full; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = ~full; + always @(posedge clock or posedge reset) + if (reset) + full <= 1'h0; + else if (~(do_enq == (io_deq_ready & full))) + full <= do_enq; + always @(posedge clock) + if (do_enq) + ram <= {io_enq_bits_opcode, io_enq_bits_funct5, io_enq_bits_rs3, io_enq_bits_rs2, io_enq_bits_rs1, io_enq_bits_rm, io_enq_bits_inst, io_enq_bits_pc, io_enq_bits_scalar_rd, io_enq_bits_scalar_rs1, io_enq_bits_float_rs1, io_enq_bits_rd, io_enq_bits_uses_rs3, io_enq_bits_uses_rs2}; + assign io_deq_valid = full; + assign io_deq_bits_opcode = ram[99:97]; + assign io_deq_bits_funct5 = ram[96:92]; + assign io_deq_bits_rs3 = ram[91:87]; + assign io_deq_bits_rs2 = ram[86:82]; + assign io_deq_bits_rs1 = ram[81:77]; + assign io_deq_bits_rm = ram[76:74]; + assign io_deq_bits_scalar_rd = ram[9]; + assign io_deq_bits_rd = ram[6:2]; + assign io_count = full; +endmodule +module ram_2x37 ( + R0_addr, + R0_en, + R0_clk, + R0_data, + W0_addr, + W0_en, + W0_clk, + W0_data +); + input R0_addr; + input R0_en; + input R0_clk; + output wire [36:0] R0_data; + input W0_addr; + input W0_en; + input W0_clk; + input [36:0] W0_data; + reg [36:0] Memory [0:1]; + always @(posedge W0_clk) + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + assign R0_data = (R0_en ? Memory[R0_addr] : 37'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); +endmodule +module Queue2_RegfileWriteDataIO ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_addr, + io_enq_bits_data, + io_deq_ready, + io_deq_valid, + io_deq_bits_addr, + io_deq_bits_data +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [4:0] io_enq_bits_addr; + input [31:0] io_enq_bits_data; + input io_deq_ready; + output wire io_deq_valid; + output wire [4:0] io_deq_bits_addr; + output wire [31:0] io_deq_bits_data; + wire [36:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + ram_2x37 ram_ext( + .R0_addr(wrap_1), + .R0_en(1'h1), + .R0_clk(clock), + .R0_data(_ram_ext_R0_data), + .W0_addr(wrap), + .W0_en(do_enq), + .W0_clk(clock), + .W0_data({io_enq_bits_addr, io_enq_bits_data}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_addr = _ram_ext_R0_data[36:32]; + assign io_deq_bits_data = _ram_ext_R0_data[31:0]; +endmodule +module FloatCore ( + clock, + reset, + io_inst_ready, + io_inst_valid, + io_inst_bits_opcode, + io_inst_bits_funct5, + io_inst_bits_rs3, + io_inst_bits_rs2, + io_inst_bits_rs1, + io_inst_bits_rm, + io_inst_bits_inst, + io_inst_bits_pc, + io_inst_bits_scalar_rd, + io_inst_bits_scalar_rs1, + io_inst_bits_float_rs1, + io_inst_bits_rd, + io_inst_bits_uses_rs3, + io_inst_bits_uses_rs2, + io_read_ports_0_valid, + io_read_ports_0_addr, + io_read_ports_0_data_mantissa, + io_read_ports_0_data_exponent, + io_read_ports_0_data_sign, + io_read_ports_1_valid, + io_read_ports_1_addr, + io_read_ports_1_data_mantissa, + io_read_ports_1_data_exponent, + io_read_ports_1_data_sign, + io_read_ports_2_valid, + io_read_ports_2_addr, + io_read_ports_2_data_mantissa, + io_read_ports_2_data_exponent, + io_read_ports_2_data_sign, + io_write_ports_0_valid, + io_write_ports_0_addr, + io_write_ports_0_data_mantissa, + io_write_ports_0_data_exponent, + io_write_ports_0_data_sign, + io_write_ports_1_valid, + io_write_ports_1_addr, + io_write_ports_1_data_mantissa, + io_write_ports_1_data_exponent, + io_write_ports_1_data_sign, + io_rs1_data, + io_scalar_rd_ready, + io_scalar_rd_valid, + io_scalar_rd_bits_addr, + io_scalar_rd_bits_data, + io_csr_in_fflags_valid, + io_csr_in_fflags_bits, + io_csr_out_frm, + io_lsu_rd_valid, + io_lsu_rd_bits_addr, + io_lsu_rd_bits_data +); + input clock; + input reset; + output wire io_inst_ready; + input io_inst_valid; + input [2:0] io_inst_bits_opcode; + input [4:0] io_inst_bits_funct5; + input [4:0] io_inst_bits_rs3; + input [4:0] io_inst_bits_rs2; + input [4:0] io_inst_bits_rs1; + input [2:0] io_inst_bits_rm; + input [31:0] io_inst_bits_inst; + input [31:0] io_inst_bits_pc; + input io_inst_bits_scalar_rd; + input io_inst_bits_scalar_rs1; + input io_inst_bits_float_rs1; + input [4:0] io_inst_bits_rd; + input io_inst_bits_uses_rs3; + input io_inst_bits_uses_rs2; + output wire io_read_ports_0_valid; + output wire [4:0] io_read_ports_0_addr; + input [22:0] io_read_ports_0_data_mantissa; + input [7:0] io_read_ports_0_data_exponent; + input io_read_ports_0_data_sign; + output wire io_read_ports_1_valid; + output wire [4:0] io_read_ports_1_addr; + input [22:0] io_read_ports_1_data_mantissa; + input [7:0] io_read_ports_1_data_exponent; + input io_read_ports_1_data_sign; + output wire io_read_ports_2_valid; + output wire [4:0] io_read_ports_2_addr; + input [22:0] io_read_ports_2_data_mantissa; + input [7:0] io_read_ports_2_data_exponent; + input io_read_ports_2_data_sign; + output wire io_write_ports_0_valid; + output wire [4:0] io_write_ports_0_addr; + output wire [22:0] io_write_ports_0_data_mantissa; + output wire [7:0] io_write_ports_0_data_exponent; + output wire io_write_ports_0_data_sign; + output wire io_write_ports_1_valid; + output wire [4:0] io_write_ports_1_addr; + output wire [22:0] io_write_ports_1_data_mantissa; + output wire [7:0] io_write_ports_1_data_exponent; + output wire io_write_ports_1_data_sign; + input [31:0] io_rs1_data; + input io_scalar_rd_ready; + output wire io_scalar_rd_valid; + output wire [4:0] io_scalar_rd_bits_addr; + output wire [31:0] io_scalar_rd_bits_data; + output wire io_csr_in_fflags_valid; + output wire [4:0] io_csr_in_fflags_bits; + input [2:0] io_csr_out_frm; + input io_lsu_rd_valid; + input [4:0] io_lsu_rd_bits_addr; + input [31:0] io_lsu_rd_bits_data; + wire instQueue_io_deq_ready; + wire _floatCoreWrapper_io_out_ready_i_T_4; + wire _floatCoreWrapper_io_in_valid_i_T_4; + wire _scalar_rd_pipe_q_io_enq_ready; + wire _floatCoreWrapper_in_ready_o; + wire _floatCoreWrapper_out_valid_o; + wire [31:0] _floatCoreWrapper_result_o; + wire _floatCoreWrapper_status_o_0; + wire _floatCoreWrapper_status_o_1; + wire _floatCoreWrapper_status_o_2; + wire _floatCoreWrapper_status_o_3; + wire _floatCoreWrapper_status_o_4; + wire _instQueue_io_deq_valid; + wire [2:0] _instQueue_io_deq_bits_opcode; + wire [4:0] _instQueue_io_deq_bits_funct5; + wire [4:0] _instQueue_io_deq_bits_rs3; + wire [4:0] _instQueue_io_deq_bits_rs2; + wire [4:0] _instQueue_io_deq_bits_rs1; + wire [2:0] _instQueue_io_deq_bits_rm; + wire _instQueue_io_deq_bits_scalar_rd; + wire [4:0] _instQueue_io_deq_bits_rd; + wire _instQueue_io_count; + wire _opfp_mod_T_6 = _instQueue_io_deq_bits_funct5 == 5'h04; + wire _opfp_mod_T_8 = _instQueue_io_deq_bits_funct5 == 5'h18; + wire _fmv_x_w_T_2 = _instQueue_io_deq_bits_funct5 == 5'h1c; + wire _opfp_mod_T_10 = _instQueue_io_deq_bits_funct5 == 5'h1a; + wire [3:0] opfp_operation = (_opfp_mod_T_10 ? 4'hc : (_fmv_x_w_T_2 ? 4'h9 : (_instQueue_io_deq_bits_funct5 == 5'h14 ? 4'h8 : (_opfp_mod_T_8 ? 4'hb : {1'h0, (_instQueue_io_deq_bits_funct5 == 5'h05 ? 3'h7 : (_opfp_mod_T_6 ? 3'h6 : (_instQueue_io_deq_bits_funct5 == 5'h0b ? 3'h5 : (_instQueue_io_deq_bits_funct5 == 5'h03 ? 3'h4 : {2'h1, _instQueue_io_deq_bits_funct5 == 5'h02}))))})))); + wire [31:0] _GEN = {20'h21100, opfp_operation, 8'hf2}; + wire [3:0] op_i = _GEN[_instQueue_io_deq_bits_opcode * 4+:4]; + wire _read_port_2_valid_T = op_i == 4'h0; + wire _read_port_2_valid_T_1 = op_i == 4'h1; + wire _fmv_w_x_T = _instQueue_io_deq_bits_opcode == 3'h2; + wire _floatCoreWrapper_io_operands_i_0_T_1 = opfp_operation == 4'hc; + wire _fmv_w_x_T_4 = _instQueue_io_deq_bits_rm == 3'h0; + wire fmv_x_w = ((_instQueue_io_deq_valid & _fmv_w_x_T) & _fmv_x_w_T_2) & _fmv_w_x_T_4; + wire fmv_w_x = ((_instQueue_io_deq_valid & _fmv_w_x_T) & (_instQueue_io_deq_bits_funct5 == 5'h1e)) & _fmv_w_x_T_4; + wire fmv = fmv_x_w | fmv_w_x; + wire _op2_addr_T = op_i == 4'h2; + wire inst_rm_valid = (((((_instQueue_io_deq_bits_rm == 3'h0) | (_instQueue_io_deq_bits_rm == 3'h1)) | (_instQueue_io_deq_bits_rm == 3'h2)) | (_instQueue_io_deq_bits_rm == 3'h3)) | (_instQueue_io_deq_bits_rm == 3'h4)) | &_instQueue_io_deq_bits_rm; + wire csr_rm_valid = (((((io_csr_out_frm == 3'h0) | (io_csr_out_frm == 3'h1)) | (io_csr_out_frm == 3'h2)) | (io_csr_out_frm == 3'h3)) | (io_csr_out_frm == 3'h4)) | &io_csr_out_frm; + reg fpuActive; + wire _io_csr_in_fflags_valid_T = instQueue_io_deq_ready & _instQueue_io_deq_valid; + wire _instQueue_io_deq_ready_T = _floatCoreWrapper_io_in_valid_i_T_4 & _floatCoreWrapper_in_ready_o; + assign _floatCoreWrapper_io_in_valid_i_T_4 = (((_instQueue_io_deq_valid & ~fmv) & ~fpuActive) & inst_rm_valid) & (~(&_instQueue_io_deq_bits_rm) | (~(~csr_rm_valid | (csr_rm_valid & (&io_csr_out_frm))) & csr_rm_valid)); + wire [31:0] _io_write_ports_0_data_T = (fmv_w_x ? io_rs1_data : _floatCoreWrapper_result_o); + assign _floatCoreWrapper_io_out_ready_i_T_4 = ((_instQueue_io_deq_valid & _instQueue_io_deq_bits_scalar_rd) & _scalar_rd_pipe_q_io_enq_ready) | (_instQueue_io_deq_valid & ~_instQueue_io_deq_bits_scalar_rd); + assign instQueue_io_deq_ready = (((_instQueue_io_deq_ready_T | fpuActive) & _floatCoreWrapper_io_out_ready_i_T_4) & _floatCoreWrapper_out_valid_o) | fmv; + always @(posedge clock or posedge reset) + if (reset) + fpuActive <= 1'h0; + else + fpuActive <= ~_io_csr_in_fflags_valid_T & (_instQueue_io_deq_ready_T | fpuActive); + Queue1_FloatInstruction instQueue( + .clock(clock), + .reset(reset), + .io_enq_valid(io_inst_valid), + .io_enq_bits_opcode(io_inst_bits_opcode), + .io_enq_bits_funct5(io_inst_bits_funct5), + .io_enq_bits_rs3(io_inst_bits_rs3), + .io_enq_bits_rs2(io_inst_bits_rs2), + .io_enq_bits_rs1(io_inst_bits_rs1), + .io_enq_bits_rm(io_inst_bits_rm), + .io_enq_bits_inst(io_inst_bits_inst), + .io_enq_bits_pc(io_inst_bits_pc), + .io_enq_bits_scalar_rd(io_inst_bits_scalar_rd), + .io_enq_bits_scalar_rs1(io_inst_bits_scalar_rs1), + .io_enq_bits_float_rs1(io_inst_bits_float_rs1), + .io_enq_bits_rd(io_inst_bits_rd), + .io_enq_bits_uses_rs3(io_inst_bits_uses_rs3), + .io_enq_bits_uses_rs2(io_inst_bits_uses_rs2), + .io_deq_ready(instQueue_io_deq_ready), + .io_deq_valid(_instQueue_io_deq_valid), + .io_deq_bits_opcode(_instQueue_io_deq_bits_opcode), + .io_deq_bits_funct5(_instQueue_io_deq_bits_funct5), + .io_deq_bits_rs3(_instQueue_io_deq_bits_rs3), + .io_deq_bits_rs2(_instQueue_io_deq_bits_rs2), + .io_deq_bits_rs1(_instQueue_io_deq_bits_rs1), + .io_deq_bits_rm(_instQueue_io_deq_bits_rm), + .io_deq_bits_scalar_rd(_instQueue_io_deq_bits_scalar_rd), + .io_deq_bits_rd(_instQueue_io_deq_bits_rd), + .io_count(_instQueue_io_count) + ); + FloatCoreWrapper floatCoreWrapper( + .clk_i(clock), + .rst_ni(~reset), + .in_valid_i(_floatCoreWrapper_io_in_valid_i_T_4), + .in_ready_o(_floatCoreWrapper_in_ready_o), + .operands_i_0((_fmv_w_x_T & _floatCoreWrapper_io_operands_i_0_T_1 ? io_rs1_data : {io_read_ports_0_data_sign, io_read_ports_0_data_exponent, io_read_ports_0_data_mantissa})), + .operands_i_1({io_read_ports_1_data_sign, io_read_ports_1_data_exponent, io_read_ports_1_data_mantissa}), + .operands_i_2({io_read_ports_2_data_sign, io_read_ports_2_data_exponent, io_read_ports_2_data_mantissa}), + .op_i(op_i), + .op_mod_i((_instQueue_io_deq_bits_opcode != 3'h6) & (((_instQueue_io_deq_bits_opcode == 3'h5) | (_instQueue_io_deq_bits_opcode == 3'h4)) | (((_instQueue_io_deq_bits_opcode != 3'h3) & (_instQueue_io_deq_bits_opcode == 3'h2)) & (_opfp_mod_T_10 | _opfp_mod_T_8 ? _instQueue_io_deq_bits_rs2[0] : _opfp_mod_T_6 | (_instQueue_io_deq_bits_funct5 == 5'h01))))), + .rnd_mode_i((inst_rm_valid & (&_instQueue_io_deq_bits_rm) ? io_csr_out_frm : _instQueue_io_deq_bits_rm)), + .flush_i(1'h0), + .out_valid_o(_floatCoreWrapper_out_valid_o), + .out_ready_i(_floatCoreWrapper_io_out_ready_i_T_4), + .result_o(_floatCoreWrapper_result_o), + .status_o_0(_floatCoreWrapper_status_o_0), + .status_o_1(_floatCoreWrapper_status_o_1), + .status_o_2(_floatCoreWrapper_status_o_2), + .status_o_3(_floatCoreWrapper_status_o_3), + .status_o_4(_floatCoreWrapper_status_o_4), + .busy_o(), + .early_valid_o() + ); + Queue2_RegfileWriteDataIO scalar_rd_pipe_q( + .clock(clock), + .reset(reset), + .io_enq_ready(_scalar_rd_pipe_q_io_enq_ready), + .io_enq_valid(((((_instQueue_io_deq_ready_T | fpuActive) & _floatCoreWrapper_out_valid_o) & _floatCoreWrapper_io_out_ready_i_T_4) & _instQueue_io_deq_bits_scalar_rd) | fmv_x_w), + .io_enq_bits_addr(_instQueue_io_deq_bits_rd), + .io_enq_bits_data((fmv_x_w ? {io_read_ports_0_data_sign, io_read_ports_0_data_exponent, io_read_ports_0_data_mantissa} : _floatCoreWrapper_result_o)), + .io_deq_ready(io_scalar_rd_ready), + .io_deq_valid(io_scalar_rd_valid), + .io_deq_bits_addr(io_scalar_rd_bits_addr), + .io_deq_bits_data(io_scalar_rd_bits_data) + ); + assign io_inst_ready = ~_instQueue_io_count; + assign io_read_ports_0_valid = (op_i != 4'h2) & _instQueue_io_deq_valid; + assign io_read_ports_0_addr = _instQueue_io_deq_bits_rs1; + assign io_read_ports_1_valid = (|{_read_port_2_valid_T_1, _read_port_2_valid_T} | (_fmv_w_x_T & ({_floatCoreWrapper_io_operands_i_0_T_1, opfp_operation == 4'hb, opfp_operation == 4'h9, opfp_operation == 4'h5} == 4'h0))) & _instQueue_io_deq_valid; + assign io_read_ports_1_addr = (_op2_addr_T ? _instQueue_io_deq_bits_rs1 : _instQueue_io_deq_bits_rs2); + assign io_read_ports_2_valid = (|{_read_port_2_valid_T_1, _read_port_2_valid_T} | (_fmv_w_x_T & (opfp_operation == 4'h2))) & _instQueue_io_deq_valid; + assign io_read_ports_2_addr = (_op2_addr_T ? _instQueue_io_deq_bits_rs2 : _instQueue_io_deq_bits_rs3); + assign io_write_ports_0_valid = (((_floatCoreWrapper_out_valid_o & _io_csr_in_fflags_valid_T) & ~_instQueue_io_deq_bits_scalar_rd) | fmv_w_x) & ~(_instQueue_io_deq_valid & (_instQueue_io_deq_bits_opcode == 3'h1)); + assign io_write_ports_0_addr = _instQueue_io_deq_bits_rd; + assign io_write_ports_0_data_mantissa = _io_write_ports_0_data_T[22:0]; + assign io_write_ports_0_data_exponent = _io_write_ports_0_data_T[30:23]; + assign io_write_ports_0_data_sign = _io_write_ports_0_data_T[31]; + assign io_write_ports_1_valid = io_lsu_rd_valid; + assign io_write_ports_1_addr = io_lsu_rd_bits_addr; + assign io_write_ports_1_data_mantissa = io_lsu_rd_bits_data[22:0]; + assign io_write_ports_1_data_exponent = io_lsu_rd_bits_data[30:23]; + assign io_write_ports_1_data_sign = io_lsu_rd_bits_data[31]; + assign io_csr_in_fflags_valid = (_floatCoreWrapper_out_valid_o & _io_csr_in_fflags_valid_T) & ~fmv; + assign io_csr_in_fflags_bits = {_floatCoreWrapper_status_o_4, _floatCoreWrapper_status_o_3, _floatCoreWrapper_status_o_2, _floatCoreWrapper_status_o_1, _floatCoreWrapper_status_o_0}; +endmodule +module FRegfile ( + clock, + reset, + io_read_ports_0_valid, + io_read_ports_0_addr, + io_read_ports_0_data_mantissa, + io_read_ports_0_data_exponent, + io_read_ports_0_data_sign, + io_read_ports_1_valid, + io_read_ports_1_addr, + io_read_ports_1_data_mantissa, + io_read_ports_1_data_exponent, + io_read_ports_1_data_sign, + io_read_ports_2_valid, + io_read_ports_2_addr, + io_read_ports_2_data_mantissa, + io_read_ports_2_data_exponent, + io_read_ports_2_data_sign, + io_write_ports_0_valid, + io_write_ports_0_addr, + io_write_ports_0_data_mantissa, + io_write_ports_0_data_exponent, + io_write_ports_0_data_sign, + io_write_ports_1_valid, + io_write_ports_1_addr, + io_write_ports_1_data_mantissa, + io_write_ports_1_data_exponent, + io_write_ports_1_data_sign, + io_scoreboard_set, + io_scoreboard, + io_busPort_data_0, + io_busPortAddr +); + input clock; + input reset; + input io_read_ports_0_valid; + input [4:0] io_read_ports_0_addr; + output wire [22:0] io_read_ports_0_data_mantissa; + output wire [7:0] io_read_ports_0_data_exponent; + output wire io_read_ports_0_data_sign; + input io_read_ports_1_valid; + input [4:0] io_read_ports_1_addr; + output wire [22:0] io_read_ports_1_data_mantissa; + output wire [7:0] io_read_ports_1_data_exponent; + output wire io_read_ports_1_data_sign; + input io_read_ports_2_valid; + input [4:0] io_read_ports_2_addr; + output wire [22:0] io_read_ports_2_data_mantissa; + output wire [7:0] io_read_ports_2_data_exponent; + output wire io_read_ports_2_data_sign; + input io_write_ports_0_valid; + input [4:0] io_write_ports_0_addr; + input [22:0] io_write_ports_0_data_mantissa; + input [7:0] io_write_ports_0_data_exponent; + input io_write_ports_0_data_sign; + input io_write_ports_1_valid; + input [4:0] io_write_ports_1_addr; + input [22:0] io_write_ports_1_data_mantissa; + input [7:0] io_write_ports_1_data_exponent; + input io_write_ports_1_data_sign; + input [31:0] io_scoreboard_set; + output wire [31:0] io_scoreboard; + output wire [31:0] io_busPort_data_0; + input [4:0] io_busPortAddr; + reg [22:0] fregfile_0_mantissa; + reg [7:0] fregfile_0_exponent; + reg fregfile_0_sign; + reg [22:0] fregfile_1_mantissa; + reg [7:0] fregfile_1_exponent; + reg fregfile_1_sign; + reg [22:0] fregfile_2_mantissa; + reg [7:0] fregfile_2_exponent; + reg fregfile_2_sign; + reg [22:0] fregfile_3_mantissa; + reg [7:0] fregfile_3_exponent; + reg fregfile_3_sign; + reg [22:0] fregfile_4_mantissa; + reg [7:0] fregfile_4_exponent; + reg fregfile_4_sign; + reg [22:0] fregfile_5_mantissa; + reg [7:0] fregfile_5_exponent; + reg fregfile_5_sign; + reg [22:0] fregfile_6_mantissa; + reg [7:0] fregfile_6_exponent; + reg fregfile_6_sign; + reg [22:0] fregfile_7_mantissa; + reg [7:0] fregfile_7_exponent; + reg fregfile_7_sign; + reg [22:0] fregfile_8_mantissa; + reg [7:0] fregfile_8_exponent; + reg fregfile_8_sign; + reg [22:0] fregfile_9_mantissa; + reg [7:0] fregfile_9_exponent; + reg fregfile_9_sign; + reg [22:0] fregfile_10_mantissa; + reg [7:0] fregfile_10_exponent; + reg fregfile_10_sign; + reg [22:0] fregfile_11_mantissa; + reg [7:0] fregfile_11_exponent; + reg fregfile_11_sign; + reg [22:0] fregfile_12_mantissa; + reg [7:0] fregfile_12_exponent; + reg fregfile_12_sign; + reg [22:0] fregfile_13_mantissa; + reg [7:0] fregfile_13_exponent; + reg fregfile_13_sign; + reg [22:0] fregfile_14_mantissa; + reg [7:0] fregfile_14_exponent; + reg fregfile_14_sign; + reg [22:0] fregfile_15_mantissa; + reg [7:0] fregfile_15_exponent; + reg fregfile_15_sign; + reg [22:0] fregfile_16_mantissa; + reg [7:0] fregfile_16_exponent; + reg fregfile_16_sign; + reg [22:0] fregfile_17_mantissa; + reg [7:0] fregfile_17_exponent; + reg fregfile_17_sign; + reg [22:0] fregfile_18_mantissa; + reg [7:0] fregfile_18_exponent; + reg fregfile_18_sign; + reg [22:0] fregfile_19_mantissa; + reg [7:0] fregfile_19_exponent; + reg fregfile_19_sign; + reg [22:0] fregfile_20_mantissa; + reg [7:0] fregfile_20_exponent; + reg fregfile_20_sign; + reg [22:0] fregfile_21_mantissa; + reg [7:0] fregfile_21_exponent; + reg fregfile_21_sign; + reg [22:0] fregfile_22_mantissa; + reg [7:0] fregfile_22_exponent; + reg fregfile_22_sign; + reg [22:0] fregfile_23_mantissa; + reg [7:0] fregfile_23_exponent; + reg fregfile_23_sign; + reg [22:0] fregfile_24_mantissa; + reg [7:0] fregfile_24_exponent; + reg fregfile_24_sign; + reg [22:0] fregfile_25_mantissa; + reg [7:0] fregfile_25_exponent; + reg fregfile_25_sign; + reg [22:0] fregfile_26_mantissa; + reg [7:0] fregfile_26_exponent; + reg fregfile_26_sign; + reg [22:0] fregfile_27_mantissa; + reg [7:0] fregfile_27_exponent; + reg fregfile_27_sign; + reg [22:0] fregfile_28_mantissa; + reg [7:0] fregfile_28_exponent; + reg fregfile_28_sign; + reg [22:0] fregfile_29_mantissa; + reg [7:0] fregfile_29_exponent; + reg fregfile_29_sign; + reg [22:0] fregfile_30_mantissa; + reg [7:0] fregfile_30_exponent; + reg fregfile_30_sign; + reg [22:0] fregfile_31_mantissa; + reg [7:0] fregfile_31_exponent; + reg fregfile_31_sign; + reg [31:0] scoreboard; + reg scoreboard_error; + wire [735:0] _GEN = {fregfile_31_mantissa, fregfile_30_mantissa, fregfile_29_mantissa, fregfile_28_mantissa, fregfile_27_mantissa, fregfile_26_mantissa, fregfile_25_mantissa, fregfile_24_mantissa, fregfile_23_mantissa, fregfile_22_mantissa, fregfile_21_mantissa, fregfile_20_mantissa, fregfile_19_mantissa, fregfile_18_mantissa, fregfile_17_mantissa, fregfile_16_mantissa, fregfile_15_mantissa, fregfile_14_mantissa, fregfile_13_mantissa, fregfile_12_mantissa, fregfile_11_mantissa, fregfile_10_mantissa, fregfile_9_mantissa, fregfile_8_mantissa, fregfile_7_mantissa, fregfile_6_mantissa, fregfile_5_mantissa, fregfile_4_mantissa, fregfile_3_mantissa, fregfile_2_mantissa, fregfile_1_mantissa, fregfile_0_mantissa}; + wire [255:0] _GEN_0 = {fregfile_31_exponent, fregfile_30_exponent, fregfile_29_exponent, fregfile_28_exponent, fregfile_27_exponent, fregfile_26_exponent, fregfile_25_exponent, fregfile_24_exponent, fregfile_23_exponent, fregfile_22_exponent, fregfile_21_exponent, fregfile_20_exponent, fregfile_19_exponent, fregfile_18_exponent, fregfile_17_exponent, fregfile_16_exponent, fregfile_15_exponent, fregfile_14_exponent, fregfile_13_exponent, fregfile_12_exponent, fregfile_11_exponent, fregfile_10_exponent, fregfile_9_exponent, fregfile_8_exponent, fregfile_7_exponent, fregfile_6_exponent, fregfile_5_exponent, fregfile_4_exponent, fregfile_3_exponent, fregfile_2_exponent, fregfile_1_exponent, fregfile_0_exponent}; + wire [31:0] _GEN_1 = {fregfile_31_sign, fregfile_30_sign, fregfile_29_sign, fregfile_28_sign, fregfile_27_sign, fregfile_26_sign, fregfile_25_sign, fregfile_24_sign, fregfile_23_sign, fregfile_22_sign, fregfile_21_sign, fregfile_20_sign, fregfile_19_sign, fregfile_18_sign, fregfile_17_sign, fregfile_16_sign, fregfile_15_sign, fregfile_14_sign, fregfile_13_sign, fregfile_12_sign, fregfile_11_sign, fregfile_10_sign, fregfile_9_sign, fregfile_8_sign, fregfile_7_sign, fregfile_6_sign, fregfile_5_sign, fregfile_4_sign, fregfile_3_sign, fregfile_2_sign, fregfile_1_sign, fregfile_0_sign}; + wire [31:0] scoreboard_clr = (io_write_ports_0_valid ? 32'h00000001 << io_write_ports_0_addr : 32'h00000000) | (io_write_ports_1_valid ? 32'h00000001 << io_write_ports_1_addr : 32'h00000000); + wire valid_0 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h00); + wire valid_0_1 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h01); + wire valid_0_2 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h02); + wire valid_0_3 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h03); + wire valid_0_4 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h04); + wire valid_0_5 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h05); + wire valid_0_6 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h06); + wire valid_0_7 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h07); + wire valid_0_8 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h08); + wire valid_0_9 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h09); + wire valid_0_10 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h0a); + wire valid_0_11 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h0b); + wire valid_0_12 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h0c); + wire valid_0_13 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h0d); + wire valid_0_14 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h0e); + wire valid_0_15 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h0f); + wire valid_0_16 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h10); + wire valid_0_17 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h11); + wire valid_0_18 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h12); + wire valid_0_19 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h13); + wire valid_0_20 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h14); + wire valid_0_21 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h15); + wire valid_0_22 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h16); + wire valid_0_23 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h17); + wire valid_0_24 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h18); + wire valid_0_25 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h19); + wire valid_0_26 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h1a); + wire valid_0_27 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h1b); + wire valid_0_28 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h1c); + wire valid_0_29 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h1d); + wire valid_0_30 = io_write_ports_0_valid & (io_write_ports_0_addr == 5'h1e); + wire valid_0_31 = io_write_ports_0_valid & (&io_write_ports_0_addr); + always @(posedge clock or posedge reset) + if (reset) begin + fregfile_0_mantissa <= 23'h000000; + fregfile_0_exponent <= 8'h00; + fregfile_0_sign <= 1'h0; + fregfile_1_mantissa <= 23'h000000; + fregfile_1_exponent <= 8'h00; + fregfile_1_sign <= 1'h0; + fregfile_2_mantissa <= 23'h000000; + fregfile_2_exponent <= 8'h00; + fregfile_2_sign <= 1'h0; + fregfile_3_mantissa <= 23'h000000; + fregfile_3_exponent <= 8'h00; + fregfile_3_sign <= 1'h0; + fregfile_4_mantissa <= 23'h000000; + fregfile_4_exponent <= 8'h00; + fregfile_4_sign <= 1'h0; + fregfile_5_mantissa <= 23'h000000; + fregfile_5_exponent <= 8'h00; + fregfile_5_sign <= 1'h0; + fregfile_6_mantissa <= 23'h000000; + fregfile_6_exponent <= 8'h00; + fregfile_6_sign <= 1'h0; + fregfile_7_mantissa <= 23'h000000; + fregfile_7_exponent <= 8'h00; + fregfile_7_sign <= 1'h0; + fregfile_8_mantissa <= 23'h000000; + fregfile_8_exponent <= 8'h00; + fregfile_8_sign <= 1'h0; + fregfile_9_mantissa <= 23'h000000; + fregfile_9_exponent <= 8'h00; + fregfile_9_sign <= 1'h0; + fregfile_10_mantissa <= 23'h000000; + fregfile_10_exponent <= 8'h00; + fregfile_10_sign <= 1'h0; + fregfile_11_mantissa <= 23'h000000; + fregfile_11_exponent <= 8'h00; + fregfile_11_sign <= 1'h0; + fregfile_12_mantissa <= 23'h000000; + fregfile_12_exponent <= 8'h00; + fregfile_12_sign <= 1'h0; + fregfile_13_mantissa <= 23'h000000; + fregfile_13_exponent <= 8'h00; + fregfile_13_sign <= 1'h0; + fregfile_14_mantissa <= 23'h000000; + fregfile_14_exponent <= 8'h00; + fregfile_14_sign <= 1'h0; + fregfile_15_mantissa <= 23'h000000; + fregfile_15_exponent <= 8'h00; + fregfile_15_sign <= 1'h0; + fregfile_16_mantissa <= 23'h000000; + fregfile_16_exponent <= 8'h00; + fregfile_16_sign <= 1'h0; + fregfile_17_mantissa <= 23'h000000; + fregfile_17_exponent <= 8'h00; + fregfile_17_sign <= 1'h0; + fregfile_18_mantissa <= 23'h000000; + fregfile_18_exponent <= 8'h00; + fregfile_18_sign <= 1'h0; + fregfile_19_mantissa <= 23'h000000; + fregfile_19_exponent <= 8'h00; + fregfile_19_sign <= 1'h0; + fregfile_20_mantissa <= 23'h000000; + fregfile_20_exponent <= 8'h00; + fregfile_20_sign <= 1'h0; + fregfile_21_mantissa <= 23'h000000; + fregfile_21_exponent <= 8'h00; + fregfile_21_sign <= 1'h0; + fregfile_22_mantissa <= 23'h000000; + fregfile_22_exponent <= 8'h00; + fregfile_22_sign <= 1'h0; + fregfile_23_mantissa <= 23'h000000; + fregfile_23_exponent <= 8'h00; + fregfile_23_sign <= 1'h0; + fregfile_24_mantissa <= 23'h000000; + fregfile_24_exponent <= 8'h00; + fregfile_24_sign <= 1'h0; + fregfile_25_mantissa <= 23'h000000; + fregfile_25_exponent <= 8'h00; + fregfile_25_sign <= 1'h0; + fregfile_26_mantissa <= 23'h000000; + fregfile_26_exponent <= 8'h00; + fregfile_26_sign <= 1'h0; + fregfile_27_mantissa <= 23'h000000; + fregfile_27_exponent <= 8'h00; + fregfile_27_sign <= 1'h0; + fregfile_28_mantissa <= 23'h000000; + fregfile_28_exponent <= 8'h00; + fregfile_28_sign <= 1'h0; + fregfile_29_mantissa <= 23'h000000; + fregfile_29_exponent <= 8'h00; + fregfile_29_sign <= 1'h0; + fregfile_30_mantissa <= 23'h000000; + fregfile_30_exponent <= 8'h00; + fregfile_30_sign <= 1'h0; + fregfile_31_mantissa <= 23'h000000; + fregfile_31_exponent <= 8'h00; + fregfile_31_sign <= 1'h0; + scoreboard <= 32'h00000000; + scoreboard_error <= 1'h0; + end + else begin + if (valid_0 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h00))) begin + fregfile_0_mantissa <= (valid_0 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_0_exponent <= (valid_0 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_0_sign <= (valid_0 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_1 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h01))) begin + fregfile_1_mantissa <= (valid_0_1 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_1_exponent <= (valid_0_1 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_1_sign <= (valid_0_1 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_2 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h02))) begin + fregfile_2_mantissa <= (valid_0_2 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_2_exponent <= (valid_0_2 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_2_sign <= (valid_0_2 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_3 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h03))) begin + fregfile_3_mantissa <= (valid_0_3 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_3_exponent <= (valid_0_3 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_3_sign <= (valid_0_3 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_4 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h04))) begin + fregfile_4_mantissa <= (valid_0_4 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_4_exponent <= (valid_0_4 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_4_sign <= (valid_0_4 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_5 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h05))) begin + fregfile_5_mantissa <= (valid_0_5 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_5_exponent <= (valid_0_5 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_5_sign <= (valid_0_5 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_6 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h06))) begin + fregfile_6_mantissa <= (valid_0_6 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_6_exponent <= (valid_0_6 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_6_sign <= (valid_0_6 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_7 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h07))) begin + fregfile_7_mantissa <= (valid_0_7 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_7_exponent <= (valid_0_7 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_7_sign <= (valid_0_7 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_8 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h08))) begin + fregfile_8_mantissa <= (valid_0_8 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_8_exponent <= (valid_0_8 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_8_sign <= (valid_0_8 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_9 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h09))) begin + fregfile_9_mantissa <= (valid_0_9 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_9_exponent <= (valid_0_9 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_9_sign <= (valid_0_9 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_10 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h0a))) begin + fregfile_10_mantissa <= (valid_0_10 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_10_exponent <= (valid_0_10 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_10_sign <= (valid_0_10 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_11 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h0b))) begin + fregfile_11_mantissa <= (valid_0_11 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_11_exponent <= (valid_0_11 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_11_sign <= (valid_0_11 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_12 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h0c))) begin + fregfile_12_mantissa <= (valid_0_12 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_12_exponent <= (valid_0_12 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_12_sign <= (valid_0_12 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_13 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h0d))) begin + fregfile_13_mantissa <= (valid_0_13 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_13_exponent <= (valid_0_13 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_13_sign <= (valid_0_13 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_14 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h0e))) begin + fregfile_14_mantissa <= (valid_0_14 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_14_exponent <= (valid_0_14 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_14_sign <= (valid_0_14 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_15 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h0f))) begin + fregfile_15_mantissa <= (valid_0_15 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_15_exponent <= (valid_0_15 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_15_sign <= (valid_0_15 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_16 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h10))) begin + fregfile_16_mantissa <= (valid_0_16 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_16_exponent <= (valid_0_16 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_16_sign <= (valid_0_16 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_17 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h11))) begin + fregfile_17_mantissa <= (valid_0_17 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_17_exponent <= (valid_0_17 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_17_sign <= (valid_0_17 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_18 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h12))) begin + fregfile_18_mantissa <= (valid_0_18 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_18_exponent <= (valid_0_18 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_18_sign <= (valid_0_18 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_19 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h13))) begin + fregfile_19_mantissa <= (valid_0_19 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_19_exponent <= (valid_0_19 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_19_sign <= (valid_0_19 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_20 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h14))) begin + fregfile_20_mantissa <= (valid_0_20 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_20_exponent <= (valid_0_20 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_20_sign <= (valid_0_20 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_21 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h15))) begin + fregfile_21_mantissa <= (valid_0_21 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_21_exponent <= (valid_0_21 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_21_sign <= (valid_0_21 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_22 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h16))) begin + fregfile_22_mantissa <= (valid_0_22 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_22_exponent <= (valid_0_22 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_22_sign <= (valid_0_22 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_23 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h17))) begin + fregfile_23_mantissa <= (valid_0_23 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_23_exponent <= (valid_0_23 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_23_sign <= (valid_0_23 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_24 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h18))) begin + fregfile_24_mantissa <= (valid_0_24 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_24_exponent <= (valid_0_24 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_24_sign <= (valid_0_24 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_25 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h19))) begin + fregfile_25_mantissa <= (valid_0_25 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_25_exponent <= (valid_0_25 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_25_sign <= (valid_0_25 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_26 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h1a))) begin + fregfile_26_mantissa <= (valid_0_26 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_26_exponent <= (valid_0_26 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_26_sign <= (valid_0_26 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_27 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h1b))) begin + fregfile_27_mantissa <= (valid_0_27 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_27_exponent <= (valid_0_27 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_27_sign <= (valid_0_27 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_28 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h1c))) begin + fregfile_28_mantissa <= (valid_0_28 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_28_exponent <= (valid_0_28 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_28_sign <= (valid_0_28 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_29 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h1d))) begin + fregfile_29_mantissa <= (valid_0_29 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_29_exponent <= (valid_0_29 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_29_sign <= (valid_0_29 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_30 | (io_write_ports_1_valid & (io_write_ports_1_addr == 5'h1e))) begin + fregfile_30_mantissa <= (valid_0_30 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_30_exponent <= (valid_0_30 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_30_sign <= (valid_0_30 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + if (valid_0_31 | (io_write_ports_1_valid & (&io_write_ports_1_addr))) begin + fregfile_31_mantissa <= (valid_0_31 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa); + fregfile_31_exponent <= (valid_0_31 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent); + fregfile_31_sign <= (valid_0_31 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign); + end + scoreboard <= (scoreboard & ~scoreboard_clr) | io_scoreboard_set; + scoreboard_error <= (scoreboard & scoreboard_clr) != scoreboard_clr; + end + assign io_read_ports_0_data_mantissa = (io_read_ports_0_valid ? _GEN[io_read_ports_0_addr * 23+:23] : 23'h000000); + assign io_read_ports_0_data_exponent = (io_read_ports_0_valid ? _GEN_0[io_read_ports_0_addr * 8+:8] : 8'h00); + assign io_read_ports_0_data_sign = io_read_ports_0_valid & _GEN_1[io_read_ports_0_addr]; + assign io_read_ports_1_data_mantissa = (io_read_ports_1_valid ? _GEN[io_read_ports_1_addr * 23+:23] : 23'h000000); + assign io_read_ports_1_data_exponent = (io_read_ports_1_valid ? _GEN_0[io_read_ports_1_addr * 8+:8] : 8'h00); + assign io_read_ports_1_data_sign = io_read_ports_1_valid & _GEN_1[io_read_ports_1_addr]; + assign io_read_ports_2_data_mantissa = (io_read_ports_2_valid ? _GEN[io_read_ports_2_addr * 23+:23] : 23'h000000); + assign io_read_ports_2_data_exponent = (io_read_ports_2_valid ? _GEN_0[io_read_ports_2_addr * 8+:8] : 8'h00); + assign io_read_ports_2_data_sign = io_read_ports_2_valid & _GEN_1[io_read_ports_2_addr]; + assign io_scoreboard = scoreboard; + assign io_busPort_data_0 = {_GEN_1[io_busPortAddr], _GEN_0[io_busPortAddr * 8+:8], _GEN[io_busPortAddr * 23+:23]}; +endmodule +module Arbiter3_RegfileWriteDataIO ( + io_in_0_valid, + io_in_0_bits_addr, + io_in_0_bits_data, + io_in_1_ready, + io_in_1_valid, + io_in_1_bits_addr, + io_in_1_bits_data, + io_in_2_ready, + io_in_2_valid, + io_in_2_bits_addr, + io_in_2_bits_data, + io_out_valid, + io_out_bits_addr, + io_out_bits_data +); + input io_in_0_valid; + input [4:0] io_in_0_bits_addr; + input [31:0] io_in_0_bits_data; + output wire io_in_1_ready; + input io_in_1_valid; + input [4:0] io_in_1_bits_addr; + input [31:0] io_in_1_bits_data; + output wire io_in_2_ready; + input io_in_2_valid; + input [4:0] io_in_2_bits_addr; + input [31:0] io_in_2_bits_data; + output wire io_out_valid; + output wire [4:0] io_out_bits_addr; + output wire [31:0] io_out_bits_data; + wire _io_out_valid_T = io_in_0_valid | io_in_1_valid; + assign io_in_1_ready = ~io_in_0_valid; + assign io_in_2_ready = ~_io_out_valid_T; + assign io_out_valid = _io_out_valid_T | io_in_2_valid; + assign io_out_bits_addr = (io_in_0_valid ? io_in_0_bits_addr : (io_in_1_valid ? io_in_1_bits_addr : io_in_2_bits_addr)); + assign io_out_bits_data = (io_in_0_valid ? io_in_0_bits_data : (io_in_1_valid ? io_in_1_bits_data : io_in_2_bits_data)); +endmodule +module SCore ( + clock, + reset, + io_csr_in_value_0, + io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + io_csr_out_value_8, + io_halted, + io_fault, + io_wfi, + io_irq, + io_ibus_valid, + io_ibus_addr, + io_ibus_rdata, + io_ibus_fault_valid, + io_dbus_valid, + io_dbus_write, + io_dbus_addr, + io_dbus_wdata, + io_dbus_wmask, + io_dbus_rdata, + io_ebus_dbus_valid, + io_ebus_dbus_ready, + io_ebus_dbus_write, + io_ebus_dbus_pc, + io_ebus_dbus_addr, + io_ebus_dbus_size, + io_ebus_dbus_wdata, + io_ebus_dbus_wmask, + io_ebus_dbus_rdata, + io_ebus_fault_valid, + io_ebus_fault_bits_write, + io_ebus_fault_bits_addr, + io_ebus_fault_bits_epc, +); + input clock; + input reset; + input [31:0] io_csr_in_value_0; + output wire [31:0] io_csr_out_value_0; + output wire [31:0] io_csr_out_value_1; + output wire [31:0] io_csr_out_value_2; + output wire [31:0] io_csr_out_value_3; + output wire [31:0] io_csr_out_value_4; + output wire [31:0] io_csr_out_value_5; + output wire [31:0] io_csr_out_value_6; + output wire [31:0] io_csr_out_value_7; + output wire [31:0] io_csr_out_value_8; + output wire io_halted; + output wire io_fault; + output wire io_wfi; + input io_irq; + output wire io_ibus_valid; + output wire [31:0] io_ibus_addr; + input [127:0] io_ibus_rdata; + input io_ibus_fault_valid; + output wire io_dbus_valid; + output wire io_dbus_write; + output wire [31:0] io_dbus_addr; + output wire [127:0] io_dbus_wdata; + output wire [15:0] io_dbus_wmask; + input [127:0] io_dbus_rdata; + output wire io_ebus_dbus_valid; + input io_ebus_dbus_ready; + output wire io_ebus_dbus_write; + output wire [31:0] io_ebus_dbus_pc; + output wire [31:0] io_ebus_dbus_addr; + output wire [4:0] io_ebus_dbus_size; + output wire [127:0] io_ebus_dbus_wdata; + output wire [15:0] io_ebus_dbus_wmask; + input [127:0] io_ebus_dbus_rdata; + input io_ebus_fault_valid; + input io_ebus_fault_bits_write; + input [31:0] io_ebus_fault_bits_addr; + input [31:0] io_ebus_fault_bits_epc; + wire _arb_io_in_1_ready; + wire _arb_io_in_2_ready; + wire _arb_io_out_valid; + wire [4:0] _arb_io_out_bits_addr; + wire [31:0] _arb_io_out_bits_data; + wire [22:0] _fRegfile_io_read_ports_0_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_0_data_exponent; + wire _fRegfile_io_read_ports_0_data_sign; + wire [22:0] _fRegfile_io_read_ports_1_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_1_data_exponent; + wire _fRegfile_io_read_ports_1_data_sign; + wire [22:0] _fRegfile_io_read_ports_2_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_2_data_exponent; + wire _fRegfile_io_read_ports_2_data_sign; + wire [31:0] _fRegfile_io_scoreboard; + wire [31:0] _fRegfile_io_busPort_data_0; + wire _floatCore_io_inst_ready; + wire _floatCore_io_read_ports_0_valid; + wire [4:0] _floatCore_io_read_ports_0_addr; + wire _floatCore_io_read_ports_1_valid; + wire [4:0] _floatCore_io_read_ports_1_addr; + wire _floatCore_io_read_ports_2_valid; + wire [4:0] _floatCore_io_read_ports_2_addr; + wire _floatCore_io_write_ports_0_valid; + wire [4:0] _floatCore_io_write_ports_0_addr; + wire [22:0] _floatCore_io_write_ports_0_data_mantissa; + wire [7:0] _floatCore_io_write_ports_0_data_exponent; + wire _floatCore_io_write_ports_0_data_sign; + wire _floatCore_io_write_ports_1_valid; + wire [4:0] _floatCore_io_write_ports_1_addr; + wire [22:0] _floatCore_io_write_ports_1_data_mantissa; + wire [7:0] _floatCore_io_write_ports_1_data_exponent; + wire _floatCore_io_write_ports_1_data_sign; + wire _floatCore_io_scalar_rd_valid; + wire [4:0] _floatCore_io_scalar_rd_bits_addr; + wire [31:0] _floatCore_io_scalar_rd_bits_data; + wire _floatCore_io_csr_in_fflags_valid; + wire [4:0] _floatCore_io_csr_in_fflags_bits; + wire _dvu_io_req_ready; + wire _dvu_io_rd_valid; + wire [4:0] _dvu_io_rd_bits_addr; + wire [31:0] _dvu_io_rd_bits_data; + wire _mlu_io_req_1_ready; + wire _mlu_io_req_2_ready; + wire _mlu_io_req_3_ready; + wire _mlu_io_rd_valid; + wire [4:0] _mlu_io_rd_bits_addr; + wire [31:0] _mlu_io_rd_bits_data; + wire _bru_3_io_rd_valid; + wire [4:0] _bru_3_io_rd_bits_addr; + wire [31:0] _bru_3_io_rd_bits_data; + wire _bru_3_io_taken_valid; + wire [31:0] _bru_3_io_taken_value; + wire _bru_2_io_rd_valid; + wire [4:0] _bru_2_io_rd_bits_addr; + wire [31:0] _bru_2_io_rd_bits_data; + wire _bru_2_io_taken_valid; + wire [31:0] _bru_2_io_taken_value; + wire _bru_1_io_rd_valid; + wire [4:0] _bru_1_io_rd_bits_addr; + wire [31:0] _bru_1_io_rd_bits_data; + wire _bru_1_io_taken_valid; + wire [31:0] _bru_1_io_taken_value; + wire _bru_0_io_csr_in_mode_valid; + wire [1:0] _bru_0_io_csr_in_mode_bits; + wire _bru_0_io_csr_in_mcause_valid; + wire [31:0] _bru_0_io_csr_in_mcause_bits; + wire _bru_0_io_csr_in_mepc_valid; + wire [31:0] _bru_0_io_csr_in_mepc_bits; + wire _bru_0_io_csr_in_mtval_valid; + wire [31:0] _bru_0_io_csr_in_mtval_bits; + wire _bru_0_io_csr_in_halt; + wire _bru_0_io_csr_in_fault; + wire _bru_0_io_csr_in_wfi; + wire _bru_0_io_rd_valid; + wire [4:0] _bru_0_io_rd_bits_addr; + wire [31:0] _bru_0_io_rd_bits_data; + wire _bru_0_io_taken_valid; + wire [31:0] _bru_0_io_taken_value; + wire _bru_0_io_interlock; + wire _alu_3_io_rd_valid; + wire [4:0] _alu_3_io_rd_bits_addr; + wire [31:0] _alu_3_io_rd_bits_data; + wire _alu_2_io_rd_valid; + wire [4:0] _alu_2_io_rd_bits_addr; + wire [31:0] _alu_2_io_rd_bits_data; + wire _alu_1_io_rd_valid; + wire [4:0] _alu_1_io_rd_bits_addr; + wire [31:0] _alu_1_io_rd_bits_data; + wire _alu_0_io_rd_valid; + wire [4:0] _alu_0_io_rd_bits_addr; + wire [31:0] _alu_0_io_rd_bits_data; + wire [31:0] _retirement_buffer_io_nSpace; + wire [3:0] _retirement_buffer_io_nRetired; + wire _retirement_buffer_io_empty; + wire _retirement_buffer_io_trapPending; + wire _fault_manager_io_out_valid; + wire [31:0] _fault_manager_io_out_bits_mepc; + wire [31:0] _fault_manager_io_out_bits_mtval; + wire [31:0] _fault_manager_io_out_bits_mcause; + wire _fault_manager_io_out_bits_decode; + wire _lsu_io_req_0_ready; + wire _lsu_io_req_1_ready; + wire _lsu_io_req_2_ready; + wire _lsu_io_req_3_ready; + wire _lsu_io_rd_valid; + wire [4:0] _lsu_io_rd_bits_addr; + wire [31:0] _lsu_io_rd_bits_data; + wire _lsu_io_rd_flt_valid; + wire [4:0] _lsu_io_rd_flt_bits_addr; + wire [31:0] _lsu_io_rd_flt_bits_data; + wire _lsu_io_ibus_valid; + wire [31:0] _lsu_io_ibus_addr; + wire _lsu_io_dbus_valid; + wire _lsu_io_dbus_write; + wire [31:0] _lsu_io_dbus_addr; + wire [127:0] _lsu_io_dbus_wdata; + wire _lsu_io_flush_valid; + wire _lsu_io_flush_fencei; + wire [31:0] _lsu_io_flush_pcNext; + wire _lsu_io_fault_valid; + wire _lsu_io_fault_bits_write; + wire [31:0] _lsu_io_fault_bits_addr; + wire [31:0] _lsu_io_fault_bits_epc; + wire [2:0] _lsu_io_queueCapacity; + wire _lsu_io_active; + wire _lsu_io_storeComplete_valid; + wire [31:0] _lsu_io_storeComplete_bits; + wire _dispatch_io_csrFault_0; + wire _dispatch_io_jalFault_0; + wire _dispatch_io_jalFault_1; + wire _dispatch_io_jalFault_2; + wire _dispatch_io_jalFault_3; + wire _dispatch_io_jalrFault_0; + wire _dispatch_io_jalrFault_1; + wire _dispatch_io_jalrFault_2; + wire _dispatch_io_jalrFault_3; + wire _dispatch_io_bxxFault_0; + wire _dispatch_io_bxxFault_1; + wire _dispatch_io_bxxFault_2; + wire _dispatch_io_bxxFault_3; + wire _dispatch_io_undefFault_0; + wire [31:0] _dispatch_io_bruTarget_0; + wire [31:0] _dispatch_io_bruTarget_1; + wire [31:0] _dispatch_io_bruTarget_2; + wire [31:0] _dispatch_io_bruTarget_3; + wire _dispatch_io_inst_0_ready; + wire _dispatch_io_inst_1_ready; + wire _dispatch_io_inst_2_ready; + wire _dispatch_io_inst_3_ready; + wire _dispatch_io_rs1Read_0_valid; + wire [4:0] _dispatch_io_rs1Read_0_addr; + wire _dispatch_io_rs1Read_1_valid; + wire [4:0] _dispatch_io_rs1Read_1_addr; + wire _dispatch_io_rs1Read_2_valid; + wire [4:0] _dispatch_io_rs1Read_2_addr; + wire _dispatch_io_rs1Read_3_valid; + wire [4:0] _dispatch_io_rs1Read_3_addr; + wire _dispatch_io_rs1Set_0_valid; + wire [31:0] _dispatch_io_rs1Set_0_value; + wire _dispatch_io_rs1Set_1_valid; + wire [31:0] _dispatch_io_rs1Set_1_value; + wire _dispatch_io_rs1Set_2_valid; + wire [31:0] _dispatch_io_rs1Set_2_value; + wire _dispatch_io_rs1Set_3_valid; + wire [31:0] _dispatch_io_rs1Set_3_value; + wire _dispatch_io_rs2Read_0_valid; + wire [4:0] _dispatch_io_rs2Read_0_addr; + wire _dispatch_io_rs2Read_1_valid; + wire [4:0] _dispatch_io_rs2Read_1_addr; + wire _dispatch_io_rs2Read_2_valid; + wire [4:0] _dispatch_io_rs2Read_2_addr; + wire _dispatch_io_rs2Read_3_valid; + wire [4:0] _dispatch_io_rs2Read_3_addr; + wire _dispatch_io_rs2Set_0_valid; + wire [31:0] _dispatch_io_rs2Set_0_value; + wire _dispatch_io_rs2Set_1_valid; + wire [31:0] _dispatch_io_rs2Set_1_value; + wire _dispatch_io_rs2Set_2_valid; + wire [31:0] _dispatch_io_rs2Set_2_value; + wire _dispatch_io_rs2Set_3_valid; + wire [31:0] _dispatch_io_rs2Set_3_value; + wire _dispatch_io_rdMark_0_valid; + wire [4:0] _dispatch_io_rdMark_0_addr; + wire _dispatch_io_rdMark_1_valid; + wire [4:0] _dispatch_io_rdMark_1_addr; + wire _dispatch_io_rdMark_2_valid; + wire [4:0] _dispatch_io_rdMark_2_addr; + wire _dispatch_io_rdMark_3_valid; + wire [4:0] _dispatch_io_rdMark_3_addr; + wire _dispatch_io_busRead_0_bypass; + wire _dispatch_io_busRead_0_immen; + wire [31:0] _dispatch_io_busRead_0_immed; + wire _dispatch_io_busRead_1_bypass; + wire [31:0] _dispatch_io_busRead_1_immed; + wire _dispatch_io_busRead_2_bypass; + wire [31:0] _dispatch_io_busRead_2_immed; + wire _dispatch_io_busRead_3_bypass; + wire [31:0] _dispatch_io_busRead_3_immed; + wire _dispatch_io_rdMark_flt_valid; + wire [4:0] _dispatch_io_rdMark_flt_addr; + wire _dispatch_io_alu_0_valid; + wire [4:0] _dispatch_io_alu_0_bits_addr; + wire [4:0] _dispatch_io_alu_0_bits_op; + wire _dispatch_io_alu_1_valid; + wire [4:0] _dispatch_io_alu_1_bits_addr; + wire [4:0] _dispatch_io_alu_1_bits_op; + wire _dispatch_io_alu_2_valid; + wire [4:0] _dispatch_io_alu_2_bits_addr; + wire [4:0] _dispatch_io_alu_2_bits_op; + wire _dispatch_io_alu_3_valid; + wire [4:0] _dispatch_io_alu_3_bits_addr; + wire [4:0] _dispatch_io_alu_3_bits_op; + wire _dispatch_io_bru_0_valid; + wire _dispatch_io_bru_0_bits_fwd; + wire [3:0] _dispatch_io_bru_0_bits_op; + wire [31:0] _dispatch_io_bru_0_bits_pc; + wire [31:0] _dispatch_io_bru_0_bits_target; + wire [4:0] _dispatch_io_bru_0_bits_link; + wire _dispatch_io_bru_1_valid; + wire _dispatch_io_bru_1_bits_fwd; + wire [3:0] _dispatch_io_bru_1_bits_op; + wire [31:0] _dispatch_io_bru_1_bits_pc; + wire [31:0] _dispatch_io_bru_1_bits_target; + wire [4:0] _dispatch_io_bru_1_bits_link; + wire _dispatch_io_bru_2_valid; + wire _dispatch_io_bru_2_bits_fwd; + wire [3:0] _dispatch_io_bru_2_bits_op; + wire [31:0] _dispatch_io_bru_2_bits_pc; + wire [31:0] _dispatch_io_bru_2_bits_target; + wire [4:0] _dispatch_io_bru_2_bits_link; + wire _dispatch_io_bru_3_valid; + wire _dispatch_io_bru_3_bits_fwd; + wire [3:0] _dispatch_io_bru_3_bits_op; + wire [31:0] _dispatch_io_bru_3_bits_pc; + wire [31:0] _dispatch_io_bru_3_bits_target; + wire [4:0] _dispatch_io_bru_3_bits_link; + wire _dispatch_io_csr_valid; + wire [4:0] _dispatch_io_csr_bits_addr; + wire [11:0] _dispatch_io_csr_bits_index; + wire [4:0] _dispatch_io_csr_bits_rs1; + wire [1:0] _dispatch_io_csr_bits_op; + wire _dispatch_io_lsu_0_valid; + wire _dispatch_io_lsu_0_bits_store; + wire [4:0] _dispatch_io_lsu_0_bits_addr; + wire [4:0] _dispatch_io_lsu_0_bits_op; + wire [31:0] _dispatch_io_lsu_0_bits_pc; + wire _dispatch_io_lsu_1_valid; + wire _dispatch_io_lsu_1_bits_store; + wire [4:0] _dispatch_io_lsu_1_bits_addr; + wire [4:0] _dispatch_io_lsu_1_bits_op; + wire [31:0] _dispatch_io_lsu_1_bits_pc; + wire _dispatch_io_lsu_2_valid; + wire _dispatch_io_lsu_2_bits_store; + wire [4:0] _dispatch_io_lsu_2_bits_addr; + wire [4:0] _dispatch_io_lsu_2_bits_op; + wire [31:0] _dispatch_io_lsu_2_bits_pc; + wire _dispatch_io_lsu_3_valid; + wire _dispatch_io_lsu_3_bits_store; + wire [4:0] _dispatch_io_lsu_3_bits_addr; + wire [4:0] _dispatch_io_lsu_3_bits_op; + wire [31:0] _dispatch_io_lsu_3_bits_pc; + wire _dispatch_io_mlu_0_valid; + wire [4:0] _dispatch_io_mlu_0_bits_addr; + wire [2:0] _dispatch_io_mlu_0_bits_op; + wire _dispatch_io_mlu_1_valid; + wire [4:0] _dispatch_io_mlu_1_bits_addr; + wire [2:0] _dispatch_io_mlu_1_bits_op; + wire _dispatch_io_mlu_2_valid; + wire [4:0] _dispatch_io_mlu_2_bits_addr; + wire [2:0] _dispatch_io_mlu_2_bits_op; + wire _dispatch_io_mlu_3_valid; + wire [4:0] _dispatch_io_mlu_3_bits_addr; + wire [2:0] _dispatch_io_mlu_3_bits_op; + wire _dispatch_io_dvu_0_valid; + wire [4:0] _dispatch_io_dvu_0_bits_addr; + wire [1:0] _dispatch_io_dvu_0_bits_op; + wire _dispatch_io_float_valid; + wire [2:0] _dispatch_io_float_bits_opcode; + wire [4:0] _dispatch_io_float_bits_funct5; + wire [4:0] _dispatch_io_float_bits_rs3; + wire [4:0] _dispatch_io_float_bits_rs2; + wire [4:0] _dispatch_io_float_bits_rs1; + wire [2:0] _dispatch_io_float_bits_rm; + wire [31:0] _dispatch_io_float_bits_inst; + wire [31:0] _dispatch_io_float_bits_pc; + wire _dispatch_io_float_bits_scalar_rd; + wire _dispatch_io_float_bits_scalar_rs1; + wire _dispatch_io_float_bits_float_rs1; + wire [4:0] _dispatch_io_float_bits_rd; + wire _dispatch_io_float_bits_uses_rs3; + wire _dispatch_io_float_bits_uses_rs2; + wire [4:0] _dispatch_io_fbusPortAddr; + wire _dispatch_io_branch_0; + wire _dispatch_io_branch_1; + wire _dispatch_io_branch_2; + wire _dispatch_io_branch_3; + wire _dispatch_io_jump_0; + wire _dispatch_io_jump_1; + wire _dispatch_io_jump_2; + wire _dispatch_io_jump_3; + wire [31:0] _csr_io_csr_out_value_4; + wire _csr_io_rd_valid; + wire [4:0] _csr_io_rd_bits_addr; + wire [31:0] _csr_io_rd_bits_data; + wire [1:0] _csr_io_bru_out_mode; + wire [31:0] _csr_io_bru_out_mepc; + wire [31:0] _csr_io_bru_out_mtvec; + wire [2:0] _csr_io_float_out_frm; + wire _csr_io_halted; + wire _csr_io_wfi; + wire _fetch_io_ibus_valid; + wire [31:0] _fetch_io_ibus_addr; + wire _fetch_io_inst_lanes_0_valid; + wire [31:0] _fetch_io_inst_lanes_0_bits_addr; + wire [31:0] _fetch_io_inst_lanes_0_bits_inst; + wire _fetch_io_inst_lanes_0_bits_brchFwd; + wire _fetch_io_inst_lanes_1_valid; + wire [31:0] _fetch_io_inst_lanes_1_bits_addr; + wire [31:0] _fetch_io_inst_lanes_1_bits_inst; + wire _fetch_io_inst_lanes_1_bits_brchFwd; + wire _fetch_io_inst_lanes_2_valid; + wire [31:0] _fetch_io_inst_lanes_2_bits_addr; + wire [31:0] _fetch_io_inst_lanes_2_bits_inst; + wire _fetch_io_inst_lanes_2_bits_brchFwd; + wire _fetch_io_inst_lanes_3_valid; + wire [31:0] _fetch_io_inst_lanes_3_bits_addr; + wire [31:0] _fetch_io_inst_lanes_3_bits_inst; + wire _fetch_io_inst_lanes_3_bits_brchFwd; + wire [31:0] _fetch_io_pc; + wire _fetch_io_fault_valid; + wire [31:0] _fetch_io_fault_bits; + wire [31:0] _regfile_io_target_0_data; + wire [31:0] _regfile_io_target_1_data; + wire [31:0] _regfile_io_target_2_data; + wire [31:0] _regfile_io_target_3_data; + wire [31:0] _regfile_io_busPort_addr_0; + wire [31:0] _regfile_io_busPort_addr_1; + wire [31:0] _regfile_io_busPort_addr_2; + wire [31:0] _regfile_io_busPort_addr_3; + wire [31:0] _regfile_io_busPort_data_0; + wire [31:0] _regfile_io_busPort_data_1; + wire [31:0] _regfile_io_busPort_data_2; + wire [31:0] _regfile_io_busPort_data_3; + wire _regfile_io_readData_0_valid; + wire [31:0] _regfile_io_readData_0_data; + wire _regfile_io_readData_1_valid; + wire [31:0] _regfile_io_readData_1_data; + wire _regfile_io_readData_2_valid; + wire [31:0] _regfile_io_readData_2_data; + wire _regfile_io_readData_3_valid; + wire [31:0] _regfile_io_readData_3_data; + wire _regfile_io_readData_4_valid; + wire [31:0] _regfile_io_readData_4_data; + wire _regfile_io_readData_5_valid; + wire [31:0] _regfile_io_readData_5_data; + wire _regfile_io_readData_6_valid; + wire [31:0] _regfile_io_readData_6_data; + wire _regfile_io_readData_7_valid; + wire [31:0] _regfile_io_readData_7_data; + wire [31:0] _regfile_io_scoreboard_regd; + wire [31:0] _regfile_io_scoreboard_comb; + wire _isBranching_T = _bru_0_io_taken_valid | _bru_1_io_taken_valid; + wire branchTaken = (_isBranching_T | _bru_2_io_taken_valid) | _bru_3_io_taken_valid; + wire regfile_io_writeData_0_valid = (_csr_io_rd_valid | _alu_0_io_rd_valid) | _bru_0_io_rd_valid; + wire [4:0] regfile_io_writeData_0_bits_addr = ((_csr_io_rd_valid ? _csr_io_rd_bits_addr : 5'h00) | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_addr : 5'h00)) | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_addr : 5'h00); + wire [31:0] regfile_io_writeData_0_bits_data = ((_csr_io_rd_valid ? _csr_io_rd_bits_data : 32'h00000000) | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_data : 32'h00000000)) | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_data : 32'h00000000); + wire regfile_io_writeData_1_valid = _alu_1_io_rd_valid | _bru_1_io_rd_valid; + wire [4:0] regfile_io_writeData_1_bits_addr = (_alu_1_io_rd_valid ? _alu_1_io_rd_bits_addr : 5'h00) | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_addr : 5'h00); + wire [31:0] regfile_io_writeData_1_bits_data = (_alu_1_io_rd_valid ? _alu_1_io_rd_bits_data : 32'h00000000) | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_data : 32'h00000000); + wire regfile_io_writeData_2_valid = _alu_2_io_rd_valid | _bru_2_io_rd_valid; + wire [4:0] regfile_io_writeData_2_bits_addr = (_alu_2_io_rd_valid ? _alu_2_io_rd_bits_addr : 5'h00) | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_addr : 5'h00); + wire [31:0] regfile_io_writeData_2_bits_data = (_alu_2_io_rd_valid ? _alu_2_io_rd_bits_data : 32'h00000000) | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_data : 32'h00000000); + wire regfile_io_writeData_3_valid = _alu_3_io_rd_valid | _bru_3_io_rd_valid; + wire [4:0] regfile_io_writeData_3_bits_addr = (_alu_3_io_rd_valid ? _alu_3_io_rd_bits_addr : 5'h00) | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_addr : 5'h00); + wire [31:0] regfile_io_writeData_3_bits_data = (_alu_3_io_rd_valid ? _alu_3_io_rd_bits_data : 32'h00000000) | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_data : 32'h00000000); + wire writeMask_2 = _bru_0_io_taken_valid | _bru_1_io_taken_valid; + Regfile regfile( + .clock(clock), + .reset(reset), + .io_readAddr_0_valid(_dispatch_io_rs1Read_0_valid), + .io_readAddr_0_addr(_dispatch_io_rs1Read_0_addr), + .io_readAddr_1_valid(_dispatch_io_rs2Read_0_valid), + .io_readAddr_1_addr(_dispatch_io_rs2Read_0_addr), + .io_readAddr_2_valid(_dispatch_io_rs1Read_1_valid), + .io_readAddr_2_addr(_dispatch_io_rs1Read_1_addr), + .io_readAddr_3_valid(_dispatch_io_rs2Read_1_valid), + .io_readAddr_3_addr(_dispatch_io_rs2Read_1_addr), + .io_readAddr_4_valid(_dispatch_io_rs1Read_2_valid), + .io_readAddr_4_addr(_dispatch_io_rs1Read_2_addr), + .io_readAddr_5_valid(_dispatch_io_rs2Read_2_valid), + .io_readAddr_5_addr(_dispatch_io_rs2Read_2_addr), + .io_readAddr_6_valid(_dispatch_io_rs1Read_3_valid), + .io_readAddr_6_addr(_dispatch_io_rs1Read_3_addr), + .io_readAddr_7_valid(_dispatch_io_rs2Read_3_valid), + .io_readAddr_7_addr(_dispatch_io_rs2Read_3_addr), + .io_readSet_0_valid(_dispatch_io_rs1Set_0_valid), + .io_readSet_0_value(_dispatch_io_rs1Set_0_value), + .io_readSet_1_valid(_dispatch_io_rs2Set_0_valid), + .io_readSet_1_value(_dispatch_io_rs2Set_0_value), + .io_readSet_2_valid(_dispatch_io_rs1Set_1_valid), + .io_readSet_2_value(_dispatch_io_rs1Set_1_value), + .io_readSet_3_valid(_dispatch_io_rs2Set_1_valid), + .io_readSet_3_value(_dispatch_io_rs2Set_1_value), + .io_readSet_4_valid(_dispatch_io_rs1Set_2_valid), + .io_readSet_4_value(_dispatch_io_rs1Set_2_value), + .io_readSet_5_valid(_dispatch_io_rs2Set_2_valid), + .io_readSet_5_value(_dispatch_io_rs2Set_2_value), + .io_readSet_6_valid(_dispatch_io_rs1Set_3_valid), + .io_readSet_6_value(_dispatch_io_rs1Set_3_value), + .io_readSet_7_valid(_dispatch_io_rs2Set_3_valid), + .io_readSet_7_value(_dispatch_io_rs2Set_3_value), + .io_writeAddr_0_valid(_dispatch_io_rdMark_0_valid), + .io_writeAddr_0_addr(_dispatch_io_rdMark_0_addr), + .io_writeAddr_1_valid(_dispatch_io_rdMark_1_valid), + .io_writeAddr_1_addr(_dispatch_io_rdMark_1_addr), + .io_writeAddr_2_valid(_dispatch_io_rdMark_2_valid), + .io_writeAddr_2_addr(_dispatch_io_rdMark_2_addr), + .io_writeAddr_3_valid(_dispatch_io_rdMark_3_valid), + .io_writeAddr_3_addr(_dispatch_io_rdMark_3_addr), + .io_busAddr_0_bypass(_dispatch_io_busRead_0_bypass), + .io_busAddr_0_immen(_dispatch_io_busRead_0_immen), + .io_busAddr_0_immed(_dispatch_io_busRead_0_immed), + .io_busAddr_1_bypass(_dispatch_io_busRead_1_bypass), + .io_busAddr_1_immed(_dispatch_io_busRead_1_immed), + .io_busAddr_2_bypass(_dispatch_io_busRead_2_bypass), + .io_busAddr_2_immed(_dispatch_io_busRead_2_immed), + .io_busAddr_3_bypass(_dispatch_io_busRead_3_bypass), + .io_busAddr_3_immed(_dispatch_io_busRead_3_immed), + .io_target_0_data(_regfile_io_target_0_data), + .io_target_1_data(_regfile_io_target_1_data), + .io_target_2_data(_regfile_io_target_2_data), + .io_target_3_data(_regfile_io_target_3_data), + .io_busPort_addr_0(_regfile_io_busPort_addr_0), + .io_busPort_addr_1(_regfile_io_busPort_addr_1), + .io_busPort_addr_2(_regfile_io_busPort_addr_2), + .io_busPort_addr_3(_regfile_io_busPort_addr_3), + .io_busPort_data_0(_regfile_io_busPort_data_0), + .io_busPort_data_1(_regfile_io_busPort_data_1), + .io_busPort_data_2(_regfile_io_busPort_data_2), + .io_busPort_data_3(_regfile_io_busPort_data_3), + .io_readData_0_valid(_regfile_io_readData_0_valid), + .io_readData_0_data(_regfile_io_readData_0_data), + .io_readData_1_valid(_regfile_io_readData_1_valid), + .io_readData_1_data(_regfile_io_readData_1_data), + .io_readData_2_valid(_regfile_io_readData_2_valid), + .io_readData_2_data(_regfile_io_readData_2_data), + .io_readData_3_valid(_regfile_io_readData_3_valid), + .io_readData_3_data(_regfile_io_readData_3_data), + .io_readData_4_valid(_regfile_io_readData_4_valid), + .io_readData_4_data(_regfile_io_readData_4_data), + .io_readData_5_valid(_regfile_io_readData_5_valid), + .io_readData_5_data(_regfile_io_readData_5_data), + .io_readData_6_valid(_regfile_io_readData_6_valid), + .io_readData_6_data(_regfile_io_readData_6_data), + .io_readData_7_valid(_regfile_io_readData_7_valid), + .io_readData_7_data(_regfile_io_readData_7_data), + .io_writeData_0_valid(regfile_io_writeData_0_valid), + .io_writeData_0_bits_addr(regfile_io_writeData_0_bits_addr), + .io_writeData_0_bits_data(regfile_io_writeData_0_bits_data), + .io_writeData_1_valid(regfile_io_writeData_1_valid), + .io_writeData_1_bits_addr(regfile_io_writeData_1_bits_addr), + .io_writeData_1_bits_data(regfile_io_writeData_1_bits_data), + .io_writeData_2_valid(regfile_io_writeData_2_valid), + .io_writeData_2_bits_addr(regfile_io_writeData_2_bits_addr), + .io_writeData_2_bits_data(regfile_io_writeData_2_bits_data), + .io_writeData_3_valid(regfile_io_writeData_3_valid), + .io_writeData_3_bits_addr(regfile_io_writeData_3_bits_addr), + .io_writeData_3_bits_data(regfile_io_writeData_3_bits_data), + .io_writeData_4_valid(_arb_io_out_valid), + .io_writeData_4_bits_addr(_arb_io_out_bits_addr), + .io_writeData_4_bits_data(_arb_io_out_bits_data), + .io_writeData_5_valid(_lsu_io_rd_valid), + .io_writeData_5_bits_addr(_lsu_io_rd_bits_addr), + .io_writeData_5_bits_data(_lsu_io_rd_bits_data), + .io_writeMask_1_valid(_bru_0_io_taken_valid), + .io_writeMask_2_valid(writeMask_2), + .io_writeMask_3_valid(writeMask_2 | _bru_2_io_taken_valid), + .io_writeMask_5_valid(_lsu_io_fault_valid), + .io_scoreboard_regd(_regfile_io_scoreboard_regd), + .io_scoreboard_comb(_regfile_io_scoreboard_comb) + ); + UncachedFetch fetch( + .clock(clock), + .reset(reset), + .io_csr_value_0(io_csr_in_value_0), + .io_ibus_valid(_fetch_io_ibus_valid), + .io_ibus_ready(~_lsu_io_ibus_valid), + .io_ibus_addr(_fetch_io_ibus_addr), + .io_ibus_rdata(io_ibus_rdata), + .io_ibus_fault_valid(~_lsu_io_ibus_valid & io_ibus_fault_valid), + .io_inst_lanes_0_ready(_dispatch_io_inst_0_ready), + .io_inst_lanes_0_valid(_fetch_io_inst_lanes_0_valid), + .io_inst_lanes_0_bits_addr(_fetch_io_inst_lanes_0_bits_addr), + .io_inst_lanes_0_bits_inst(_fetch_io_inst_lanes_0_bits_inst), + .io_inst_lanes_0_bits_brchFwd(_fetch_io_inst_lanes_0_bits_brchFwd), + .io_inst_lanes_1_ready(_dispatch_io_inst_1_ready), + .io_inst_lanes_1_valid(_fetch_io_inst_lanes_1_valid), + .io_inst_lanes_1_bits_addr(_fetch_io_inst_lanes_1_bits_addr), + .io_inst_lanes_1_bits_inst(_fetch_io_inst_lanes_1_bits_inst), + .io_inst_lanes_1_bits_brchFwd(_fetch_io_inst_lanes_1_bits_brchFwd), + .io_inst_lanes_2_ready(_dispatch_io_inst_2_ready), + .io_inst_lanes_2_valid(_fetch_io_inst_lanes_2_valid), + .io_inst_lanes_2_bits_addr(_fetch_io_inst_lanes_2_bits_addr), + .io_inst_lanes_2_bits_inst(_fetch_io_inst_lanes_2_bits_inst), + .io_inst_lanes_2_bits_brchFwd(_fetch_io_inst_lanes_2_bits_brchFwd), + .io_inst_lanes_3_ready(_dispatch_io_inst_3_ready), + .io_inst_lanes_3_valid(_fetch_io_inst_lanes_3_valid), + .io_inst_lanes_3_bits_addr(_fetch_io_inst_lanes_3_bits_addr), + .io_inst_lanes_3_bits_inst(_fetch_io_inst_lanes_3_bits_inst), + .io_inst_lanes_3_bits_brchFwd(_fetch_io_inst_lanes_3_bits_brchFwd), + .io_branch_0_valid(_bru_0_io_taken_valid), + .io_branch_0_value(_bru_0_io_taken_value), + .io_branch_1_valid(_bru_1_io_taken_valid), + .io_branch_1_value(_bru_1_io_taken_value), + .io_branch_2_valid(_bru_2_io_taken_valid), + .io_branch_2_value(_bru_2_io_taken_value), + .io_branch_3_valid(_bru_3_io_taken_valid), + .io_branch_3_value(_bru_3_io_taken_value), + .io_iflush_valid(_lsu_io_flush_valid & _lsu_io_flush_fencei), + .io_iflush_pcNext(_lsu_io_flush_pcNext), + .io_pc(_fetch_io_pc), + .io_fault_valid(_fetch_io_fault_valid), + .io_fault_bits(_fetch_io_fault_bits) + ); + Csr csr( + .clock(clock), + .reset(reset), + .io_csr_in_value_12(_fetch_io_pc), + .io_csr_out_value_0(io_csr_out_value_0), + .io_csr_out_value_1(io_csr_out_value_1), + .io_csr_out_value_2(io_csr_out_value_2), + .io_csr_out_value_3(io_csr_out_value_3), + .io_csr_out_value_4(_csr_io_csr_out_value_4), + .io_csr_out_value_5(io_csr_out_value_5), + .io_csr_out_value_6(io_csr_out_value_6), + .io_csr_out_value_7(io_csr_out_value_7), + .io_csr_out_value_8(io_csr_out_value_8), + .io_req_valid(_dispatch_io_csr_valid), + .io_req_bits_addr(_dispatch_io_csr_bits_addr), + .io_req_bits_index(_dispatch_io_csr_bits_index), + .io_req_bits_rs1(_dispatch_io_csr_bits_rs1), + .io_req_bits_op(_dispatch_io_csr_bits_op), + .io_rs1_valid(_regfile_io_readData_0_valid), + .io_rs1_data(_regfile_io_readData_0_data), + .io_rd_valid(_csr_io_rd_valid), + .io_rd_bits_addr(_csr_io_rd_bits_addr), + .io_rd_bits_data(_csr_io_rd_bits_data), + .io_bru_in_mode_valid(_bru_0_io_csr_in_mode_valid), + .io_bru_in_mode_bits(_bru_0_io_csr_in_mode_bits), + .io_bru_in_mcause_valid(_bru_0_io_csr_in_mcause_valid), + .io_bru_in_mcause_bits(_bru_0_io_csr_in_mcause_bits), + .io_bru_in_mepc_valid(_bru_0_io_csr_in_mepc_valid), + .io_bru_in_mepc_bits(_bru_0_io_csr_in_mepc_bits), + .io_bru_in_mtval_valid(_bru_0_io_csr_in_mtval_valid), + .io_bru_in_mtval_bits(_bru_0_io_csr_in_mtval_bits), + .io_bru_in_halt(_bru_0_io_csr_in_halt), + .io_bru_in_fault(_bru_0_io_csr_in_fault), + .io_bru_in_wfi(_bru_0_io_csr_in_wfi), + .io_bru_out_mode(_csr_io_bru_out_mode), + .io_bru_out_mepc(_csr_io_bru_out_mepc), + .io_bru_out_mtvec(_csr_io_bru_out_mtvec), + .io_float_in_fflags_valid(_floatCore_io_csr_in_fflags_valid), + .io_float_in_fflags_bits(_floatCore_io_csr_in_fflags_bits), + .io_float_out_frm(_csr_io_float_out_frm), + .io_counters_nRetired(_retirement_buffer_io_nRetired), + .io_halted(_csr_io_halted), + .io_fault(io_fault), + .io_wfi(_csr_io_wfi), + .io_irq(io_irq) + ); + DispatchV2 dispatch( + .clock(clock), + .reset(reset), + .io_halted(_csr_io_halted | _csr_io_wfi), + .io_lsuActive(_lsu_io_active), + .io_scoreboard_regd(_regfile_io_scoreboard_regd), + .io_scoreboard_comb(_regfile_io_scoreboard_comb), + .io_fscoreboard(_fRegfile_io_scoreboard), + .io_branchTaken(branchTaken), + .io_csrFault_0(_dispatch_io_csrFault_0), + .io_jalFault_0(_dispatch_io_jalFault_0), + .io_jalFault_1(_dispatch_io_jalFault_1), + .io_jalFault_2(_dispatch_io_jalFault_2), + .io_jalFault_3(_dispatch_io_jalFault_3), + .io_jalrFault_0(_dispatch_io_jalrFault_0), + .io_jalrFault_1(_dispatch_io_jalrFault_1), + .io_jalrFault_2(_dispatch_io_jalrFault_2), + .io_jalrFault_3(_dispatch_io_jalrFault_3), + .io_bxxFault_0(_dispatch_io_bxxFault_0), + .io_bxxFault_1(_dispatch_io_bxxFault_1), + .io_bxxFault_2(_dispatch_io_bxxFault_2), + .io_bxxFault_3(_dispatch_io_bxxFault_3), + .io_undefFault_0(_dispatch_io_undefFault_0), + .io_bruTarget_0(_dispatch_io_bruTarget_0), + .io_bruTarget_1(_dispatch_io_bruTarget_1), + .io_bruTarget_2(_dispatch_io_bruTarget_2), + .io_bruTarget_3(_dispatch_io_bruTarget_3), + .io_jalrTarget_0_data(_regfile_io_target_0_data), + .io_jalrTarget_1_data(_regfile_io_target_1_data), + .io_jalrTarget_2_data(_regfile_io_target_2_data), + .io_jalrTarget_3_data(_regfile_io_target_3_data), + .io_interlock(_bru_0_io_interlock | _lsu_io_flush_valid), + .io_inst_0_ready(_dispatch_io_inst_0_ready), + .io_inst_0_valid(_fetch_io_inst_lanes_0_valid), + .io_inst_0_bits_addr(_fetch_io_inst_lanes_0_bits_addr), + .io_inst_0_bits_inst(_fetch_io_inst_lanes_0_bits_inst), + .io_inst_0_bits_brchFwd(_fetch_io_inst_lanes_0_bits_brchFwd), + .io_inst_1_ready(_dispatch_io_inst_1_ready), + .io_inst_1_valid(_fetch_io_inst_lanes_1_valid), + .io_inst_1_bits_addr(_fetch_io_inst_lanes_1_bits_addr), + .io_inst_1_bits_inst(_fetch_io_inst_lanes_1_bits_inst), + .io_inst_1_bits_brchFwd(_fetch_io_inst_lanes_1_bits_brchFwd), + .io_inst_2_ready(_dispatch_io_inst_2_ready), + .io_inst_2_valid(_fetch_io_inst_lanes_2_valid), + .io_inst_2_bits_addr(_fetch_io_inst_lanes_2_bits_addr), + .io_inst_2_bits_inst(_fetch_io_inst_lanes_2_bits_inst), + .io_inst_2_bits_brchFwd(_fetch_io_inst_lanes_2_bits_brchFwd), + .io_inst_3_ready(_dispatch_io_inst_3_ready), + .io_inst_3_valid(_fetch_io_inst_lanes_3_valid), + .io_inst_3_bits_addr(_fetch_io_inst_lanes_3_bits_addr), + .io_inst_3_bits_inst(_fetch_io_inst_lanes_3_bits_inst), + .io_inst_3_bits_brchFwd(_fetch_io_inst_lanes_3_bits_brchFwd), + .io_rs1Read_0_valid(_dispatch_io_rs1Read_0_valid), + .io_rs1Read_0_addr(_dispatch_io_rs1Read_0_addr), + .io_rs1Read_1_valid(_dispatch_io_rs1Read_1_valid), + .io_rs1Read_1_addr(_dispatch_io_rs1Read_1_addr), + .io_rs1Read_2_valid(_dispatch_io_rs1Read_2_valid), + .io_rs1Read_2_addr(_dispatch_io_rs1Read_2_addr), + .io_rs1Read_3_valid(_dispatch_io_rs1Read_3_valid), + .io_rs1Read_3_addr(_dispatch_io_rs1Read_3_addr), + .io_rs1Set_0_valid(_dispatch_io_rs1Set_0_valid), + .io_rs1Set_0_value(_dispatch_io_rs1Set_0_value), + .io_rs1Set_1_valid(_dispatch_io_rs1Set_1_valid), + .io_rs1Set_1_value(_dispatch_io_rs1Set_1_value), + .io_rs1Set_2_valid(_dispatch_io_rs1Set_2_valid), + .io_rs1Set_2_value(_dispatch_io_rs1Set_2_value), + .io_rs1Set_3_valid(_dispatch_io_rs1Set_3_valid), + .io_rs1Set_3_value(_dispatch_io_rs1Set_3_value), + .io_rs2Read_0_valid(_dispatch_io_rs2Read_0_valid), + .io_rs2Read_0_addr(_dispatch_io_rs2Read_0_addr), + .io_rs2Read_1_valid(_dispatch_io_rs2Read_1_valid), + .io_rs2Read_1_addr(_dispatch_io_rs2Read_1_addr), + .io_rs2Read_2_valid(_dispatch_io_rs2Read_2_valid), + .io_rs2Read_2_addr(_dispatch_io_rs2Read_2_addr), + .io_rs2Read_3_valid(_dispatch_io_rs2Read_3_valid), + .io_rs2Read_3_addr(_dispatch_io_rs2Read_3_addr), + .io_rs2Set_0_valid(_dispatch_io_rs2Set_0_valid), + .io_rs2Set_0_value(_dispatch_io_rs2Set_0_value), + .io_rs2Set_1_valid(_dispatch_io_rs2Set_1_valid), + .io_rs2Set_1_value(_dispatch_io_rs2Set_1_value), + .io_rs2Set_2_valid(_dispatch_io_rs2Set_2_valid), + .io_rs2Set_2_value(_dispatch_io_rs2Set_2_value), + .io_rs2Set_3_valid(_dispatch_io_rs2Set_3_valid), + .io_rs2Set_3_value(_dispatch_io_rs2Set_3_value), + .io_rdMark_0_valid(_dispatch_io_rdMark_0_valid), + .io_rdMark_0_addr(_dispatch_io_rdMark_0_addr), + .io_rdMark_1_valid(_dispatch_io_rdMark_1_valid), + .io_rdMark_1_addr(_dispatch_io_rdMark_1_addr), + .io_rdMark_2_valid(_dispatch_io_rdMark_2_valid), + .io_rdMark_2_addr(_dispatch_io_rdMark_2_addr), + .io_rdMark_3_valid(_dispatch_io_rdMark_3_valid), + .io_rdMark_3_addr(_dispatch_io_rdMark_3_addr), + .io_busRead_0_bypass(_dispatch_io_busRead_0_bypass), + .io_busRead_0_immen(_dispatch_io_busRead_0_immen), + .io_busRead_0_immed(_dispatch_io_busRead_0_immed), + .io_busRead_1_bypass(_dispatch_io_busRead_1_bypass), + .io_busRead_1_immed(_dispatch_io_busRead_1_immed), + .io_busRead_2_bypass(_dispatch_io_busRead_2_bypass), + .io_busRead_2_immed(_dispatch_io_busRead_2_immed), + .io_busRead_3_bypass(_dispatch_io_busRead_3_bypass), + .io_busRead_3_immed(_dispatch_io_busRead_3_immed), + .io_rdMark_flt_valid(_dispatch_io_rdMark_flt_valid), + .io_rdMark_flt_addr(_dispatch_io_rdMark_flt_addr), + .io_alu_0_valid(_dispatch_io_alu_0_valid), + .io_alu_0_bits_addr(_dispatch_io_alu_0_bits_addr), + .io_alu_0_bits_op(_dispatch_io_alu_0_bits_op), + .io_alu_1_valid(_dispatch_io_alu_1_valid), + .io_alu_1_bits_addr(_dispatch_io_alu_1_bits_addr), + .io_alu_1_bits_op(_dispatch_io_alu_1_bits_op), + .io_alu_2_valid(_dispatch_io_alu_2_valid), + .io_alu_2_bits_addr(_dispatch_io_alu_2_bits_addr), + .io_alu_2_bits_op(_dispatch_io_alu_2_bits_op), + .io_alu_3_valid(_dispatch_io_alu_3_valid), + .io_alu_3_bits_addr(_dispatch_io_alu_3_bits_addr), + .io_alu_3_bits_op(_dispatch_io_alu_3_bits_op), + .io_bru_0_valid(_dispatch_io_bru_0_valid), + .io_bru_0_bits_fwd(_dispatch_io_bru_0_bits_fwd), + .io_bru_0_bits_op(_dispatch_io_bru_0_bits_op), + .io_bru_0_bits_pc(_dispatch_io_bru_0_bits_pc), + .io_bru_0_bits_target(_dispatch_io_bru_0_bits_target), + .io_bru_0_bits_link(_dispatch_io_bru_0_bits_link), + .io_bru_1_valid(_dispatch_io_bru_1_valid), + .io_bru_1_bits_fwd(_dispatch_io_bru_1_bits_fwd), + .io_bru_1_bits_op(_dispatch_io_bru_1_bits_op), + .io_bru_1_bits_pc(_dispatch_io_bru_1_bits_pc), + .io_bru_1_bits_target(_dispatch_io_bru_1_bits_target), + .io_bru_1_bits_link(_dispatch_io_bru_1_bits_link), + .io_bru_2_valid(_dispatch_io_bru_2_valid), + .io_bru_2_bits_fwd(_dispatch_io_bru_2_bits_fwd), + .io_bru_2_bits_op(_dispatch_io_bru_2_bits_op), + .io_bru_2_bits_pc(_dispatch_io_bru_2_bits_pc), + .io_bru_2_bits_target(_dispatch_io_bru_2_bits_target), + .io_bru_2_bits_link(_dispatch_io_bru_2_bits_link), + .io_bru_3_valid(_dispatch_io_bru_3_valid), + .io_bru_3_bits_fwd(_dispatch_io_bru_3_bits_fwd), + .io_bru_3_bits_op(_dispatch_io_bru_3_bits_op), + .io_bru_3_bits_pc(_dispatch_io_bru_3_bits_pc), + .io_bru_3_bits_target(_dispatch_io_bru_3_bits_target), + .io_bru_3_bits_link(_dispatch_io_bru_3_bits_link), + .io_csr_valid(_dispatch_io_csr_valid), + .io_csr_bits_addr(_dispatch_io_csr_bits_addr), + .io_csr_bits_index(_dispatch_io_csr_bits_index), + .io_csr_bits_rs1(_dispatch_io_csr_bits_rs1), + .io_csr_bits_op(_dispatch_io_csr_bits_op), + .io_lsu_0_ready(_lsu_io_req_0_ready), + .io_lsu_0_valid(_dispatch_io_lsu_0_valid), + .io_lsu_0_bits_store(_dispatch_io_lsu_0_bits_store), + .io_lsu_0_bits_addr(_dispatch_io_lsu_0_bits_addr), + .io_lsu_0_bits_op(_dispatch_io_lsu_0_bits_op), + .io_lsu_0_bits_pc(_dispatch_io_lsu_0_bits_pc), + .io_lsu_1_ready(_lsu_io_req_1_ready), + .io_lsu_1_valid(_dispatch_io_lsu_1_valid), + .io_lsu_1_bits_store(_dispatch_io_lsu_1_bits_store), + .io_lsu_1_bits_addr(_dispatch_io_lsu_1_bits_addr), + .io_lsu_1_bits_op(_dispatch_io_lsu_1_bits_op), + .io_lsu_1_bits_pc(_dispatch_io_lsu_1_bits_pc), + .io_lsu_2_ready(_lsu_io_req_2_ready), + .io_lsu_2_valid(_dispatch_io_lsu_2_valid), + .io_lsu_2_bits_store(_dispatch_io_lsu_2_bits_store), + .io_lsu_2_bits_addr(_dispatch_io_lsu_2_bits_addr), + .io_lsu_2_bits_op(_dispatch_io_lsu_2_bits_op), + .io_lsu_2_bits_pc(_dispatch_io_lsu_2_bits_pc), + .io_lsu_3_ready(_lsu_io_req_3_ready), + .io_lsu_3_valid(_dispatch_io_lsu_3_valid), + .io_lsu_3_bits_store(_dispatch_io_lsu_3_bits_store), + .io_lsu_3_bits_addr(_dispatch_io_lsu_3_bits_addr), + .io_lsu_3_bits_op(_dispatch_io_lsu_3_bits_op), + .io_lsu_3_bits_pc(_dispatch_io_lsu_3_bits_pc), + .io_lsuQueueCapacity(_lsu_io_queueCapacity), + .io_mlu_0_valid(_dispatch_io_mlu_0_valid), + .io_mlu_0_bits_addr(_dispatch_io_mlu_0_bits_addr), + .io_mlu_0_bits_op(_dispatch_io_mlu_0_bits_op), + .io_mlu_1_ready(_mlu_io_req_1_ready), + .io_mlu_1_valid(_dispatch_io_mlu_1_valid), + .io_mlu_1_bits_addr(_dispatch_io_mlu_1_bits_addr), + .io_mlu_1_bits_op(_dispatch_io_mlu_1_bits_op), + .io_mlu_2_ready(_mlu_io_req_2_ready), + .io_mlu_2_valid(_dispatch_io_mlu_2_valid), + .io_mlu_2_bits_addr(_dispatch_io_mlu_2_bits_addr), + .io_mlu_2_bits_op(_dispatch_io_mlu_2_bits_op), + .io_mlu_3_ready(_mlu_io_req_3_ready), + .io_mlu_3_valid(_dispatch_io_mlu_3_valid), + .io_mlu_3_bits_addr(_dispatch_io_mlu_3_bits_addr), + .io_mlu_3_bits_op(_dispatch_io_mlu_3_bits_op), + .io_dvu_0_ready(_dvu_io_req_ready), + .io_dvu_0_valid(_dispatch_io_dvu_0_valid), + .io_dvu_0_bits_addr(_dispatch_io_dvu_0_bits_addr), + .io_dvu_0_bits_op(_dispatch_io_dvu_0_bits_op), + .io_float_ready(_floatCore_io_inst_ready), + .io_float_valid(_dispatch_io_float_valid), + .io_float_bits_opcode(_dispatch_io_float_bits_opcode), + .io_float_bits_funct5(_dispatch_io_float_bits_funct5), + .io_float_bits_rs3(_dispatch_io_float_bits_rs3), + .io_float_bits_rs2(_dispatch_io_float_bits_rs2), + .io_float_bits_rs1(_dispatch_io_float_bits_rs1), + .io_float_bits_rm(_dispatch_io_float_bits_rm), + .io_float_bits_inst(_dispatch_io_float_bits_inst), + .io_float_bits_pc(_dispatch_io_float_bits_pc), + .io_float_bits_scalar_rd(_dispatch_io_float_bits_scalar_rd), + .io_float_bits_scalar_rs1(_dispatch_io_float_bits_scalar_rs1), + .io_float_bits_float_rs1(_dispatch_io_float_bits_float_rs1), + .io_float_bits_rd(_dispatch_io_float_bits_rd), + .io_float_bits_uses_rs3(_dispatch_io_float_bits_uses_rs3), + .io_float_bits_uses_rs2(_dispatch_io_float_bits_uses_rs2), + .io_csrFrm(_csr_io_float_out_frm), + .io_fbusPortAddr(_dispatch_io_fbusPortAddr), + .io_retirement_buffer_nSpace(_retirement_buffer_io_nSpace[4:0]), + .io_retirement_buffer_empty(_retirement_buffer_io_empty), + .io_retirement_buffer_trap_pending(_retirement_buffer_io_trapPending), + .io_branch_0(_dispatch_io_branch_0), + .io_branch_1(_dispatch_io_branch_1), + .io_branch_2(_dispatch_io_branch_2), + .io_branch_3(_dispatch_io_branch_3), + .io_jump_0(_dispatch_io_jump_0), + .io_jump_1(_dispatch_io_jump_1), + .io_jump_2(_dispatch_io_jump_2), + .io_jump_3(_dispatch_io_jump_3) + ); + LsuV2 lsu( + .clock(clock), + .reset(reset), + .io_req_0_ready(_lsu_io_req_0_ready), + .io_req_0_valid(_dispatch_io_lsu_0_valid), + .io_req_0_bits_store(_dispatch_io_lsu_0_bits_store), + .io_req_0_bits_addr(_dispatch_io_lsu_0_bits_addr), + .io_req_0_bits_op(_dispatch_io_lsu_0_bits_op), + .io_req_0_bits_pc(_dispatch_io_lsu_0_bits_pc), + .io_req_1_ready(_lsu_io_req_1_ready), + .io_req_1_valid(_dispatch_io_lsu_1_valid), + .io_req_1_bits_store(_dispatch_io_lsu_1_bits_store), + .io_req_1_bits_addr(_dispatch_io_lsu_1_bits_addr), + .io_req_1_bits_op(_dispatch_io_lsu_1_bits_op), + .io_req_1_bits_pc(_dispatch_io_lsu_1_bits_pc), + .io_req_2_ready(_lsu_io_req_2_ready), + .io_req_2_valid(_dispatch_io_lsu_2_valid), + .io_req_2_bits_store(_dispatch_io_lsu_2_bits_store), + .io_req_2_bits_addr(_dispatch_io_lsu_2_bits_addr), + .io_req_2_bits_op(_dispatch_io_lsu_2_bits_op), + .io_req_2_bits_pc(_dispatch_io_lsu_2_bits_pc), + .io_req_3_ready(_lsu_io_req_3_ready), + .io_req_3_valid(_dispatch_io_lsu_3_valid), + .io_req_3_bits_store(_dispatch_io_lsu_3_bits_store), + .io_req_3_bits_addr(_dispatch_io_lsu_3_bits_addr), + .io_req_3_bits_op(_dispatch_io_lsu_3_bits_op), + .io_req_3_bits_pc(_dispatch_io_lsu_3_bits_pc), + .io_busPort_addr_0(_regfile_io_busPort_addr_0), + .io_busPort_addr_1(_regfile_io_busPort_addr_1), + .io_busPort_addr_2(_regfile_io_busPort_addr_2), + .io_busPort_addr_3(_regfile_io_busPort_addr_3), + .io_busPort_data_0(_regfile_io_busPort_data_0), + .io_busPort_data_1(_regfile_io_busPort_data_1), + .io_busPort_data_2(_regfile_io_busPort_data_2), + .io_busPort_data_3(_regfile_io_busPort_data_3), + .io_busPort_flt_data_0(_fRegfile_io_busPort_data_0), + .io_rd_valid(_lsu_io_rd_valid), + .io_rd_bits_addr(_lsu_io_rd_bits_addr), + .io_rd_bits_data(_lsu_io_rd_bits_data), + .io_rd_flt_valid(_lsu_io_rd_flt_valid), + .io_rd_flt_bits_addr(_lsu_io_rd_flt_bits_addr), + .io_rd_flt_bits_data(_lsu_io_rd_flt_bits_data), + .io_ibus_valid(_lsu_io_ibus_valid), + .io_ibus_ready(_lsu_io_ibus_valid), + .io_ibus_addr(_lsu_io_ibus_addr), + .io_ibus_rdata(io_ibus_rdata), + .io_dbus_valid(_lsu_io_dbus_valid), + .io_dbus_write(_lsu_io_dbus_write), + .io_dbus_addr(_lsu_io_dbus_addr), + .io_dbus_wdata(_lsu_io_dbus_wdata), + .io_dbus_wmask(io_dbus_wmask), + .io_dbus_rdata(io_dbus_rdata), + .io_flush_valid(_lsu_io_flush_valid), + .io_flush_ready(_lsu_io_flush_valid), + .io_flush_fencei(_lsu_io_flush_fencei), + .io_flush_pcNext(_lsu_io_flush_pcNext), + .io_fault_valid(_lsu_io_fault_valid), + .io_fault_bits_write(_lsu_io_fault_bits_write), + .io_fault_bits_addr(_lsu_io_fault_bits_addr), + .io_fault_bits_epc(_lsu_io_fault_bits_epc), + .io_ebus_dbus_valid(io_ebus_dbus_valid), + .io_ebus_dbus_ready(io_ebus_dbus_ready), + .io_ebus_dbus_write(io_ebus_dbus_write), + .io_ebus_dbus_pc(io_ebus_dbus_pc), + .io_ebus_dbus_addr(io_ebus_dbus_addr), + .io_ebus_dbus_size(io_ebus_dbus_size), + .io_ebus_dbus_wdata(io_ebus_dbus_wdata), + .io_ebus_dbus_wmask(io_ebus_dbus_wmask), + .io_ebus_dbus_rdata(io_ebus_dbus_rdata), + .io_ebus_fault_valid(io_ebus_fault_valid), + .io_ebus_fault_bits_write(io_ebus_fault_bits_write), + .io_ebus_fault_bits_addr(io_ebus_fault_bits_addr), + .io_ebus_fault_bits_epc(io_ebus_fault_bits_epc), + .io_queueCapacity(_lsu_io_queueCapacity), + .io_active(_lsu_io_active), + .io_storeComplete_valid(_lsu_io_storeComplete_valid), + .io_storeComplete_bits(_lsu_io_storeComplete_bits) + ); + FaultManager fault_manager( + .io_in_fault_0_csr(_dispatch_io_csrFault_0), + .io_in_fault_0_jal(_dispatch_io_jalFault_0), + .io_in_fault_0_jalr(_dispatch_io_jalrFault_0), + .io_in_fault_0_bxx(_dispatch_io_bxxFault_0), + .io_in_fault_0_undef(_dispatch_io_undefFault_0), + .io_in_fault_1_jal(_dispatch_io_jalFault_1), + .io_in_fault_1_jalr(_dispatch_io_jalrFault_1), + .io_in_fault_1_bxx(_dispatch_io_bxxFault_1), + .io_in_fault_2_jal(_dispatch_io_jalFault_2), + .io_in_fault_2_jalr(_dispatch_io_jalrFault_2), + .io_in_fault_2_bxx(_dispatch_io_bxxFault_2), + .io_in_fault_3_jal(_dispatch_io_jalFault_3), + .io_in_fault_3_jalr(_dispatch_io_jalrFault_3), + .io_in_fault_3_bxx(_dispatch_io_bxxFault_3), + .io_in_pc_0_pc(_fetch_io_inst_lanes_0_bits_addr), + .io_in_pc_1_pc(_fetch_io_inst_lanes_1_bits_addr), + .io_in_pc_2_pc(_fetch_io_inst_lanes_2_bits_addr), + .io_in_pc_3_pc(_fetch_io_inst_lanes_3_bits_addr), + .io_in_memory_fault_valid(_lsu_io_fault_valid), + .io_in_memory_fault_bits_write(_lsu_io_fault_bits_write), + .io_in_memory_fault_bits_addr(_lsu_io_fault_bits_addr), + .io_in_memory_fault_bits_epc(_lsu_io_fault_bits_epc), + .io_in_undef_0_inst(_fetch_io_inst_lanes_0_bits_inst), + .io_in_undef_1_inst(_fetch_io_inst_lanes_1_bits_inst), + .io_in_undef_2_inst(_fetch_io_inst_lanes_2_bits_inst), + .io_in_undef_3_inst(_fetch_io_inst_lanes_3_bits_inst), + .io_in_jal_0_target(_dispatch_io_bruTarget_0), + .io_in_jal_1_target(_dispatch_io_bruTarget_1), + .io_in_jal_2_target(_dispatch_io_bruTarget_2), + .io_in_jal_3_target(_dispatch_io_bruTarget_3), + .io_in_jalr_0_target(_regfile_io_target_0_data), + .io_in_jalr_1_target(_regfile_io_target_1_data), + .io_in_jalr_2_target(_regfile_io_target_2_data), + .io_in_jalr_3_target(_regfile_io_target_3_data), + .io_in_fetchFault_valid(((((_fetch_io_fault_valid & ~((_isBranching_T | _bru_2_io_taken_valid) | _bru_3_io_taken_valid)) & (_regfile_io_scoreboard_regd == 32'h00000000)) & (_fRegfile_io_scoreboard == 32'h00000000)) & ~_lsu_io_active) & ~(((_fetch_io_inst_lanes_0_valid | _fetch_io_inst_lanes_1_valid) | _fetch_io_inst_lanes_2_valid) | _fetch_io_inst_lanes_3_valid)), + .io_in_fetchFault_bits(_fetch_io_fault_bits), + .io_out_valid(_fault_manager_io_out_valid), + .io_out_bits_mepc(_fault_manager_io_out_bits_mepc), + .io_out_bits_mtval(_fault_manager_io_out_bits_mtval), + .io_out_bits_mcause(_fault_manager_io_out_bits_mcause), + .io_out_bits_decode(_fault_manager_io_out_bits_decode) + ); + RetirementBuffer retirement_buffer( + .clock(clock), + .reset(reset), + .io_inst_0_ready(_dispatch_io_inst_0_ready), + .io_inst_0_valid(_fetch_io_inst_lanes_0_valid), + .io_inst_0_bits_addr(_fetch_io_inst_lanes_0_bits_addr), + .io_inst_0_bits_inst(_fetch_io_inst_lanes_0_bits_inst), + .io_inst_1_ready(_dispatch_io_inst_1_ready), + .io_inst_1_valid(_fetch_io_inst_lanes_1_valid), + .io_inst_1_bits_addr(_fetch_io_inst_lanes_1_bits_addr), + .io_inst_1_bits_inst(_fetch_io_inst_lanes_1_bits_inst), + .io_inst_2_ready(_dispatch_io_inst_2_ready), + .io_inst_2_valid(_fetch_io_inst_lanes_2_valid), + .io_inst_2_bits_addr(_fetch_io_inst_lanes_2_bits_addr), + .io_inst_2_bits_inst(_fetch_io_inst_lanes_2_bits_inst), + .io_inst_3_ready(_dispatch_io_inst_3_ready), + .io_inst_3_valid(_fetch_io_inst_lanes_3_valid), + .io_inst_3_bits_addr(_fetch_io_inst_lanes_3_bits_addr), + .io_inst_3_bits_inst(_fetch_io_inst_lanes_3_bits_inst), + .io_targets_0(_dispatch_io_bruTarget_0), + .io_targets_1(_dispatch_io_bruTarget_1), + .io_targets_2(_dispatch_io_bruTarget_2), + .io_targets_3(_dispatch_io_bruTarget_3), + .io_jalrTargets_0(_regfile_io_target_0_data), + .io_jalrTargets_1(_regfile_io_target_1_data), + .io_jalrTargets_2(_regfile_io_target_2_data), + .io_jalrTargets_3(_regfile_io_target_3_data), + .io_jump_0(_dispatch_io_jump_0), + .io_jump_1(_dispatch_io_jump_1), + .io_jump_2(_dispatch_io_jump_2), + .io_jump_3(_dispatch_io_jump_3), + .io_branch_0(_dispatch_io_branch_0), + .io_branch_1(_dispatch_io_branch_1), + .io_branch_2(_dispatch_io_branch_2), + .io_branch_3(_dispatch_io_branch_3), + .io_storeComplete_valid(_lsu_io_storeComplete_valid), + .io_storeComplete_bits(_lsu_io_storeComplete_bits), + .io_writeAddrScalar_0_valid(_dispatch_io_rdMark_0_valid), + .io_writeAddrScalar_0_addr(_dispatch_io_rdMark_0_addr), + .io_writeAddrScalar_1_valid(_dispatch_io_rdMark_1_valid), + .io_writeAddrScalar_1_addr(_dispatch_io_rdMark_1_addr), + .io_writeAddrScalar_2_valid(_dispatch_io_rdMark_2_valid), + .io_writeAddrScalar_2_addr(_dispatch_io_rdMark_2_addr), + .io_writeAddrScalar_3_valid(_dispatch_io_rdMark_3_valid), + .io_writeAddrScalar_3_addr(_dispatch_io_rdMark_3_addr), + .io_writeDataScalar_0_valid(regfile_io_writeData_0_valid), + .io_writeDataScalar_0_bits_addr(regfile_io_writeData_0_bits_addr), + .io_writeDataScalar_1_valid(regfile_io_writeData_1_valid), + .io_writeDataScalar_1_bits_addr(regfile_io_writeData_1_bits_addr), + .io_writeDataScalar_2_valid(regfile_io_writeData_2_valid), + .io_writeDataScalar_2_bits_addr(regfile_io_writeData_2_bits_addr), + .io_writeDataScalar_3_valid(regfile_io_writeData_3_valid), + .io_writeDataScalar_3_bits_addr(regfile_io_writeData_3_bits_addr), + .io_writeDataScalar_4_valid(_arb_io_out_valid), + .io_writeDataScalar_4_bits_addr(_arb_io_out_bits_addr), + .io_writeDataScalar_5_valid(_lsu_io_rd_valid), + .io_writeDataScalar_5_bits_addr(_lsu_io_rd_bits_addr), + .io_writeAddrFloat_valid(_dispatch_io_rdMark_flt_valid), + .io_writeAddrFloat_addr(_dispatch_io_rdMark_flt_addr), + .io_writeDataFloat_0_valid(_floatCore_io_write_ports_0_valid), + .io_writeDataFloat_0_bits_addr(_floatCore_io_write_ports_0_addr), + .io_writeDataFloat_1_valid(_floatCore_io_write_ports_1_valid), + .io_writeDataFloat_1_bits_addr(_floatCore_io_write_ports_1_addr), + .io_fault_valid(_fault_manager_io_out_valid), + .io_fault_bits_mepc(_fault_manager_io_out_bits_mepc), + .io_fault_bits_mcause(_fault_manager_io_out_bits_mcause), + .io_fault_bits_decode(_fault_manager_io_out_bits_decode), + .io_nSpace(_retirement_buffer_io_nSpace), + .io_nRetired(_retirement_buffer_io_nRetired), + .io_empty(_retirement_buffer_io_empty), + .io_trapPending(_retirement_buffer_io_trapPending), + ); + Alu alu_0( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_alu_0_valid), + .io_req_bits_addr(_dispatch_io_alu_0_bits_addr), + .io_req_bits_op(_dispatch_io_alu_0_bits_op), + .io_rs1_valid(_regfile_io_readData_0_valid), + .io_rs1_data(_regfile_io_readData_0_data), + .io_rs2_valid(_regfile_io_readData_1_valid), + .io_rs2_data(_regfile_io_readData_1_data), + .io_rd_valid(_alu_0_io_rd_valid), + .io_rd_bits_addr(_alu_0_io_rd_bits_addr), + .io_rd_bits_data(_alu_0_io_rd_bits_data) + ); + Alu alu_1( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_alu_1_valid), + .io_req_bits_addr(_dispatch_io_alu_1_bits_addr), + .io_req_bits_op(_dispatch_io_alu_1_bits_op), + .io_rs1_valid(_regfile_io_readData_2_valid), + .io_rs1_data(_regfile_io_readData_2_data), + .io_rs2_valid(_regfile_io_readData_3_valid), + .io_rs2_data(_regfile_io_readData_3_data), + .io_rd_valid(_alu_1_io_rd_valid), + .io_rd_bits_addr(_alu_1_io_rd_bits_addr), + .io_rd_bits_data(_alu_1_io_rd_bits_data) + ); + Alu alu_2( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_alu_2_valid), + .io_req_bits_addr(_dispatch_io_alu_2_bits_addr), + .io_req_bits_op(_dispatch_io_alu_2_bits_op), + .io_rs1_valid(_regfile_io_readData_4_valid), + .io_rs1_data(_regfile_io_readData_4_data), + .io_rs2_valid(_regfile_io_readData_5_valid), + .io_rs2_data(_regfile_io_readData_5_data), + .io_rd_valid(_alu_2_io_rd_valid), + .io_rd_bits_addr(_alu_2_io_rd_bits_addr), + .io_rd_bits_data(_alu_2_io_rd_bits_data) + ); + Alu alu_3( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_alu_3_valid), + .io_req_bits_addr(_dispatch_io_alu_3_bits_addr), + .io_req_bits_op(_dispatch_io_alu_3_bits_op), + .io_rs1_valid(_regfile_io_readData_6_valid), + .io_rs1_data(_regfile_io_readData_6_data), + .io_rs2_valid(_regfile_io_readData_7_valid), + .io_rs2_data(_regfile_io_readData_7_data), + .io_rd_valid(_alu_3_io_rd_valid), + .io_rd_bits_addr(_alu_3_io_rd_bits_addr), + .io_rd_bits_data(_alu_3_io_rd_bits_data) + ); + Bru bru_0( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_bru_0_valid), + .io_req_bits_fwd(_dispatch_io_bru_0_bits_fwd), + .io_req_bits_op(_dispatch_io_bru_0_bits_op), + .io_req_bits_pc(_dispatch_io_bru_0_bits_pc), + .io_req_bits_target(_dispatch_io_bru_0_bits_target), + .io_req_bits_link(_dispatch_io_bru_0_bits_link), + .io_csr_in_mode_valid(_bru_0_io_csr_in_mode_valid), + .io_csr_in_mode_bits(_bru_0_io_csr_in_mode_bits), + .io_csr_in_mcause_valid(_bru_0_io_csr_in_mcause_valid), + .io_csr_in_mcause_bits(_bru_0_io_csr_in_mcause_bits), + .io_csr_in_mepc_valid(_bru_0_io_csr_in_mepc_valid), + .io_csr_in_mepc_bits(_bru_0_io_csr_in_mepc_bits), + .io_csr_in_mtval_valid(_bru_0_io_csr_in_mtval_valid), + .io_csr_in_mtval_bits(_bru_0_io_csr_in_mtval_bits), + .io_csr_in_halt(_bru_0_io_csr_in_halt), + .io_csr_in_fault(_bru_0_io_csr_in_fault), + .io_csr_in_wfi(_bru_0_io_csr_in_wfi), + .io_csr_out_mode(_csr_io_bru_out_mode), + .io_csr_out_mepc(_csr_io_bru_out_mepc), + .io_csr_out_mtvec(_csr_io_bru_out_mtvec), + .io_rs1_valid(_regfile_io_readData_0_valid), + .io_rs1_data(_regfile_io_readData_0_data), + .io_rs2_valid(_regfile_io_readData_1_valid), + .io_rs2_data(_regfile_io_readData_1_data), + .io_rd_valid(_bru_0_io_rd_valid), + .io_rd_bits_addr(_bru_0_io_rd_bits_addr), + .io_rd_bits_data(_bru_0_io_rd_bits_data), + .io_taken_valid(_bru_0_io_taken_valid), + .io_taken_value(_bru_0_io_taken_value), + .io_target_data(_regfile_io_target_0_data), + .io_interlock(_bru_0_io_interlock), + .io_fault_manager_valid(_fault_manager_io_out_valid), + .io_fault_manager_bits_mepc(_fault_manager_io_out_bits_mepc), + .io_fault_manager_bits_mtval(_fault_manager_io_out_bits_mtval), + .io_fault_manager_bits_mcause(_fault_manager_io_out_bits_mcause) + ); + Bru_1 bru_1( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_bru_1_valid), + .io_req_bits_fwd(_dispatch_io_bru_1_bits_fwd), + .io_req_bits_op(_dispatch_io_bru_1_bits_op), + .io_req_bits_pc(_dispatch_io_bru_1_bits_pc), + .io_req_bits_target(_dispatch_io_bru_1_bits_target), + .io_req_bits_link(_dispatch_io_bru_1_bits_link), + .io_rs1_valid(_regfile_io_readData_2_valid), + .io_rs1_data(_regfile_io_readData_2_data), + .io_rs2_valid(_regfile_io_readData_3_valid), + .io_rs2_data(_regfile_io_readData_3_data), + .io_rd_valid(_bru_1_io_rd_valid), + .io_rd_bits_addr(_bru_1_io_rd_bits_addr), + .io_rd_bits_data(_bru_1_io_rd_bits_data), + .io_taken_valid(_bru_1_io_taken_valid), + .io_taken_value(_bru_1_io_taken_value), + .io_target_data(_regfile_io_target_1_data) + ); + Bru_1 bru_2( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_bru_2_valid), + .io_req_bits_fwd(_dispatch_io_bru_2_bits_fwd), + .io_req_bits_op(_dispatch_io_bru_2_bits_op), + .io_req_bits_pc(_dispatch_io_bru_2_bits_pc), + .io_req_bits_target(_dispatch_io_bru_2_bits_target), + .io_req_bits_link(_dispatch_io_bru_2_bits_link), + .io_rs1_valid(_regfile_io_readData_4_valid), + .io_rs1_data(_regfile_io_readData_4_data), + .io_rs2_valid(_regfile_io_readData_5_valid), + .io_rs2_data(_regfile_io_readData_5_data), + .io_rd_valid(_bru_2_io_rd_valid), + .io_rd_bits_addr(_bru_2_io_rd_bits_addr), + .io_rd_bits_data(_bru_2_io_rd_bits_data), + .io_taken_valid(_bru_2_io_taken_valid), + .io_taken_value(_bru_2_io_taken_value), + .io_target_data(_regfile_io_target_2_data) + ); + Bru_1 bru_3( + .clock(clock), + .reset(reset), + .io_req_valid(_dispatch_io_bru_3_valid), + .io_req_bits_fwd(_dispatch_io_bru_3_bits_fwd), + .io_req_bits_op(_dispatch_io_bru_3_bits_op), + .io_req_bits_pc(_dispatch_io_bru_3_bits_pc), + .io_req_bits_target(_dispatch_io_bru_3_bits_target), + .io_req_bits_link(_dispatch_io_bru_3_bits_link), + .io_rs1_valid(_regfile_io_readData_6_valid), + .io_rs1_data(_regfile_io_readData_6_data), + .io_rs2_valid(_regfile_io_readData_7_valid), + .io_rs2_data(_regfile_io_readData_7_data), + .io_rd_valid(_bru_3_io_rd_valid), + .io_rd_bits_addr(_bru_3_io_rd_bits_addr), + .io_rd_bits_data(_bru_3_io_rd_bits_data), + .io_taken_valid(_bru_3_io_taken_valid), + .io_taken_value(_bru_3_io_taken_value), + .io_target_data(_regfile_io_target_3_data) + ); + Mlu mlu( + .clock(clock), + .reset(reset), + .io_req_0_valid(_dispatch_io_mlu_0_valid), + .io_req_0_bits_addr(_dispatch_io_mlu_0_bits_addr), + .io_req_0_bits_op(_dispatch_io_mlu_0_bits_op), + .io_req_1_ready(_mlu_io_req_1_ready), + .io_req_1_valid(_dispatch_io_mlu_1_valid), + .io_req_1_bits_addr(_dispatch_io_mlu_1_bits_addr), + .io_req_1_bits_op(_dispatch_io_mlu_1_bits_op), + .io_req_2_ready(_mlu_io_req_2_ready), + .io_req_2_valid(_dispatch_io_mlu_2_valid), + .io_req_2_bits_addr(_dispatch_io_mlu_2_bits_addr), + .io_req_2_bits_op(_dispatch_io_mlu_2_bits_op), + .io_req_3_ready(_mlu_io_req_3_ready), + .io_req_3_valid(_dispatch_io_mlu_3_valid), + .io_req_3_bits_addr(_dispatch_io_mlu_3_bits_addr), + .io_req_3_bits_op(_dispatch_io_mlu_3_bits_op), + .io_rs1_0_valid(_regfile_io_readData_0_valid), + .io_rs1_0_data(_regfile_io_readData_0_data), + .io_rs1_1_valid(_regfile_io_readData_2_valid), + .io_rs1_1_data(_regfile_io_readData_2_data), + .io_rs1_2_valid(_regfile_io_readData_4_valid), + .io_rs1_2_data(_regfile_io_readData_4_data), + .io_rs1_3_valid(_regfile_io_readData_6_valid), + .io_rs1_3_data(_regfile_io_readData_6_data), + .io_rs2_0_valid(_regfile_io_readData_1_valid), + .io_rs2_0_data(_regfile_io_readData_1_data), + .io_rs2_1_valid(_regfile_io_readData_3_valid), + .io_rs2_1_data(_regfile_io_readData_3_data), + .io_rs2_2_valid(_regfile_io_readData_5_valid), + .io_rs2_2_data(_regfile_io_readData_5_data), + .io_rs2_3_valid(_regfile_io_readData_7_valid), + .io_rs2_3_data(_regfile_io_readData_7_data), + .io_rd_valid(_mlu_io_rd_valid), + .io_rd_bits_addr(_mlu_io_rd_bits_addr), + .io_rd_bits_data(_mlu_io_rd_bits_data) + ); + Dvu dvu( + .clock(clock), + .reset(reset), + .io_req_ready(_dvu_io_req_ready), + .io_req_valid(_dispatch_io_dvu_0_valid), + .io_req_bits_addr(_dispatch_io_dvu_0_bits_addr), + .io_req_bits_op(_dispatch_io_dvu_0_bits_op), + .io_rs1_data(_regfile_io_readData_0_data), + .io_rs2_data(_regfile_io_readData_1_data), + .io_rd_ready(_arb_io_in_1_ready), + .io_rd_valid(_dvu_io_rd_valid), + .io_rd_bits_addr(_dvu_io_rd_bits_addr), + .io_rd_bits_data(_dvu_io_rd_bits_data) + ); + FloatCore floatCore( + .clock(clock), + .reset(reset), + .io_inst_ready(_floatCore_io_inst_ready), + .io_inst_valid(_dispatch_io_float_valid), + .io_inst_bits_opcode(_dispatch_io_float_bits_opcode), + .io_inst_bits_funct5(_dispatch_io_float_bits_funct5), + .io_inst_bits_rs3(_dispatch_io_float_bits_rs3), + .io_inst_bits_rs2(_dispatch_io_float_bits_rs2), + .io_inst_bits_rs1(_dispatch_io_float_bits_rs1), + .io_inst_bits_rm(_dispatch_io_float_bits_rm), + .io_inst_bits_inst(_dispatch_io_float_bits_inst), + .io_inst_bits_pc(_dispatch_io_float_bits_pc), + .io_inst_bits_scalar_rd(_dispatch_io_float_bits_scalar_rd), + .io_inst_bits_scalar_rs1(_dispatch_io_float_bits_scalar_rs1), + .io_inst_bits_float_rs1(_dispatch_io_float_bits_float_rs1), + .io_inst_bits_rd(_dispatch_io_float_bits_rd), + .io_inst_bits_uses_rs3(_dispatch_io_float_bits_uses_rs3), + .io_inst_bits_uses_rs2(_dispatch_io_float_bits_uses_rs2), + .io_read_ports_0_valid(_floatCore_io_read_ports_0_valid), + .io_read_ports_0_addr(_floatCore_io_read_ports_0_addr), + .io_read_ports_0_data_mantissa(_fRegfile_io_read_ports_0_data_mantissa), + .io_read_ports_0_data_exponent(_fRegfile_io_read_ports_0_data_exponent), + .io_read_ports_0_data_sign(_fRegfile_io_read_ports_0_data_sign), + .io_read_ports_1_valid(_floatCore_io_read_ports_1_valid), + .io_read_ports_1_addr(_floatCore_io_read_ports_1_addr), + .io_read_ports_1_data_mantissa(_fRegfile_io_read_ports_1_data_mantissa), + .io_read_ports_1_data_exponent(_fRegfile_io_read_ports_1_data_exponent), + .io_read_ports_1_data_sign(_fRegfile_io_read_ports_1_data_sign), + .io_read_ports_2_valid(_floatCore_io_read_ports_2_valid), + .io_read_ports_2_addr(_floatCore_io_read_ports_2_addr), + .io_read_ports_2_data_mantissa(_fRegfile_io_read_ports_2_data_mantissa), + .io_read_ports_2_data_exponent(_fRegfile_io_read_ports_2_data_exponent), + .io_read_ports_2_data_sign(_fRegfile_io_read_ports_2_data_sign), + .io_write_ports_0_valid(_floatCore_io_write_ports_0_valid), + .io_write_ports_0_addr(_floatCore_io_write_ports_0_addr), + .io_write_ports_0_data_mantissa(_floatCore_io_write_ports_0_data_mantissa), + .io_write_ports_0_data_exponent(_floatCore_io_write_ports_0_data_exponent), + .io_write_ports_0_data_sign(_floatCore_io_write_ports_0_data_sign), + .io_write_ports_1_valid(_floatCore_io_write_ports_1_valid), + .io_write_ports_1_addr(_floatCore_io_write_ports_1_addr), + .io_write_ports_1_data_mantissa(_floatCore_io_write_ports_1_data_mantissa), + .io_write_ports_1_data_exponent(_floatCore_io_write_ports_1_data_exponent), + .io_write_ports_1_data_sign(_floatCore_io_write_ports_1_data_sign), + .io_rs1_data(_regfile_io_readData_0_data), + .io_scalar_rd_ready(_arb_io_in_2_ready), + .io_scalar_rd_valid(_floatCore_io_scalar_rd_valid), + .io_scalar_rd_bits_addr(_floatCore_io_scalar_rd_bits_addr), + .io_scalar_rd_bits_data(_floatCore_io_scalar_rd_bits_data), + .io_csr_in_fflags_valid(_floatCore_io_csr_in_fflags_valid), + .io_csr_in_fflags_bits(_floatCore_io_csr_in_fflags_bits), + .io_csr_out_frm(_csr_io_float_out_frm), + .io_lsu_rd_valid(_lsu_io_rd_flt_valid), + .io_lsu_rd_bits_addr(_lsu_io_rd_flt_bits_addr), + .io_lsu_rd_bits_data(_lsu_io_rd_flt_bits_data) + ); + FRegfile fRegfile( + .clock(clock), + .reset(reset), + .io_read_ports_0_valid(_floatCore_io_read_ports_0_valid), + .io_read_ports_0_addr(_floatCore_io_read_ports_0_addr), + .io_read_ports_0_data_mantissa(_fRegfile_io_read_ports_0_data_mantissa), + .io_read_ports_0_data_exponent(_fRegfile_io_read_ports_0_data_exponent), + .io_read_ports_0_data_sign(_fRegfile_io_read_ports_0_data_sign), + .io_read_ports_1_valid(_floatCore_io_read_ports_1_valid), + .io_read_ports_1_addr(_floatCore_io_read_ports_1_addr), + .io_read_ports_1_data_mantissa(_fRegfile_io_read_ports_1_data_mantissa), + .io_read_ports_1_data_exponent(_fRegfile_io_read_ports_1_data_exponent), + .io_read_ports_1_data_sign(_fRegfile_io_read_ports_1_data_sign), + .io_read_ports_2_valid(_floatCore_io_read_ports_2_valid), + .io_read_ports_2_addr(_floatCore_io_read_ports_2_addr), + .io_read_ports_2_data_mantissa(_fRegfile_io_read_ports_2_data_mantissa), + .io_read_ports_2_data_exponent(_fRegfile_io_read_ports_2_data_exponent), + .io_read_ports_2_data_sign(_fRegfile_io_read_ports_2_data_sign), + .io_write_ports_0_valid(_floatCore_io_write_ports_0_valid), + .io_write_ports_0_addr(_floatCore_io_write_ports_0_addr), + .io_write_ports_0_data_mantissa(_floatCore_io_write_ports_0_data_mantissa), + .io_write_ports_0_data_exponent(_floatCore_io_write_ports_0_data_exponent), + .io_write_ports_0_data_sign(_floatCore_io_write_ports_0_data_sign), + .io_write_ports_1_valid(_floatCore_io_write_ports_1_valid), + .io_write_ports_1_addr(_floatCore_io_write_ports_1_addr), + .io_write_ports_1_data_mantissa(_floatCore_io_write_ports_1_data_mantissa), + .io_write_ports_1_data_exponent(_floatCore_io_write_ports_1_data_exponent), + .io_write_ports_1_data_sign(_floatCore_io_write_ports_1_data_sign), + .io_scoreboard_set((_dispatch_io_rdMark_flt_valid ? 32'h00000001 << _dispatch_io_rdMark_flt_addr : 32'h00000000)), + .io_scoreboard(_fRegfile_io_scoreboard), + .io_busPort_data_0(_fRegfile_io_busPort_data_0), + .io_busPortAddr(_dispatch_io_fbusPortAddr) + ); + Arbiter3_RegfileWriteDataIO arb( + .io_in_0_valid(_mlu_io_rd_valid), + .io_in_0_bits_addr(_mlu_io_rd_bits_addr), + .io_in_0_bits_data(_mlu_io_rd_bits_data), + .io_in_1_ready(_arb_io_in_1_ready), + .io_in_1_valid(_dvu_io_rd_valid), + .io_in_1_bits_addr(_dvu_io_rd_bits_addr), + .io_in_1_bits_data(_dvu_io_rd_bits_data), + .io_in_2_ready(_arb_io_in_2_ready), + .io_in_2_valid(_floatCore_io_scalar_rd_valid), + .io_in_2_bits_addr(_floatCore_io_scalar_rd_bits_addr), + .io_in_2_bits_data(_floatCore_io_scalar_rd_bits_data), + .io_out_valid(_arb_io_out_valid), + .io_out_bits_addr(_arb_io_out_bits_addr), + .io_out_bits_data(_arb_io_out_bits_data) + ); + assign io_csr_out_value_4 = _csr_io_csr_out_value_4; + assign io_halted = _csr_io_halted; + assign io_wfi = _csr_io_wfi; + assign io_ibus_valid = (_lsu_io_ibus_valid ? _lsu_io_ibus_valid : _fetch_io_ibus_valid); + assign io_ibus_addr = (_lsu_io_ibus_valid ? _lsu_io_ibus_addr : _fetch_io_ibus_addr); + assign io_dbus_valid = _lsu_io_dbus_valid; + assign io_dbus_write = _lsu_io_dbus_write; + assign io_dbus_addr = _lsu_io_dbus_addr; + assign io_dbus_wdata = _lsu_io_dbus_wdata; +endmodule +module CoreMini ( + clock, + reset, + io_csr_in_value_0, + io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + io_csr_out_value_8, + io_halted, + io_fault, + io_wfi, + io_irq, + io_ibus_valid, + io_ibus_addr, + io_ibus_rdata, + io_ibus_fault_valid, + io_dbus_valid, + io_dbus_write, + io_dbus_addr, + io_dbus_wdata, + io_dbus_wmask, + io_dbus_rdata, + io_ebus_dbus_valid, + io_ebus_dbus_ready, + io_ebus_dbus_write, + io_ebus_dbus_pc, + io_ebus_dbus_addr, + io_ebus_dbus_size, + io_ebus_dbus_wdata, + io_ebus_dbus_wmask, + io_ebus_dbus_rdata, + io_ebus_fault_valid, + io_ebus_fault_bits_write, + io_ebus_fault_bits_addr, + io_ebus_fault_bits_epc, +); + input clock; + input reset; + input [31:0] io_csr_in_value_0; + output wire [31:0] io_csr_out_value_0; + output wire [31:0] io_csr_out_value_1; + output wire [31:0] io_csr_out_value_2; + output wire [31:0] io_csr_out_value_3; + output wire [31:0] io_csr_out_value_4; + output wire [31:0] io_csr_out_value_5; + output wire [31:0] io_csr_out_value_6; + output wire [31:0] io_csr_out_value_7; + output wire [31:0] io_csr_out_value_8; + output wire io_halted; + output wire io_fault; + output wire io_wfi; + input io_irq; + output wire io_ibus_valid; + output wire [31:0] io_ibus_addr; + input [127:0] io_ibus_rdata; + input io_ibus_fault_valid; + output wire io_dbus_valid; + output wire io_dbus_write; + output wire [31:0] io_dbus_addr; + output wire [127:0] io_dbus_wdata; + output wire [15:0] io_dbus_wmask; + input [127:0] io_dbus_rdata; + output wire io_ebus_dbus_valid; + input io_ebus_dbus_ready; + output wire io_ebus_dbus_write; + output wire [31:0] io_ebus_dbus_pc; + output wire [31:0] io_ebus_dbus_addr; + output wire [4:0] io_ebus_dbus_size; + output wire [127:0] io_ebus_dbus_wdata; + output wire [15:0] io_ebus_dbus_wmask; + input [127:0] io_ebus_dbus_rdata; + input io_ebus_fault_valid; + input io_ebus_fault_bits_write; + input [31:0] io_ebus_fault_bits_addr; + input [31:0] io_ebus_fault_bits_epc; + SCore score( + .clock(clock), + .reset(reset), + .io_csr_in_value_0(io_csr_in_value_0), + .io_csr_out_value_0(io_csr_out_value_0), + .io_csr_out_value_1(io_csr_out_value_1), + .io_csr_out_value_2(io_csr_out_value_2), + .io_csr_out_value_3(io_csr_out_value_3), + .io_csr_out_value_4(io_csr_out_value_4), + .io_csr_out_value_5(io_csr_out_value_5), + .io_csr_out_value_6(io_csr_out_value_6), + .io_csr_out_value_7(io_csr_out_value_7), + .io_csr_out_value_8(io_csr_out_value_8), + .io_halted(io_halted), + .io_fault(io_fault), + .io_wfi(io_wfi), + .io_irq(io_irq), + .io_ibus_valid(io_ibus_valid), + .io_ibus_addr(io_ibus_addr), + .io_ibus_rdata(io_ibus_rdata), + .io_ibus_fault_valid(io_ibus_fault_valid), + .io_dbus_valid(io_dbus_valid), + .io_dbus_write(io_dbus_write), + .io_dbus_addr(io_dbus_addr), + .io_dbus_wdata(io_dbus_wdata), + .io_dbus_wmask(io_dbus_wmask), + .io_dbus_rdata(io_dbus_rdata), + .io_ebus_dbus_valid(io_ebus_dbus_valid), + .io_ebus_dbus_ready(io_ebus_dbus_ready), + .io_ebus_dbus_write(io_ebus_dbus_write), + .io_ebus_dbus_pc(io_ebus_dbus_pc), + .io_ebus_dbus_addr(io_ebus_dbus_addr), + .io_ebus_dbus_size(io_ebus_dbus_size), + .io_ebus_dbus_wdata(io_ebus_dbus_wdata), + .io_ebus_dbus_wmask(io_ebus_dbus_wmask), + .io_ebus_dbus_rdata(io_ebus_dbus_rdata), + .io_ebus_fault_valid(io_ebus_fault_valid), + .io_ebus_fault_bits_write(io_ebus_fault_bits_write), + .io_ebus_fault_bits_addr(io_ebus_fault_bits_addr), + .io_ebus_fault_bits_epc(io_ebus_fault_bits_epc), + ); +endmodule +module SRAM_512x128 ( + clock, + io_addr, + io_enable, + io_write, + io_wdata, + io_wmask, + io_rdata +); + input clock; + input [8:0] io_addr; + input io_enable; + input io_write; + input [127:0] io_wdata; + input [15:0] io_wmask; + output wire [127:0] io_rdata; + Sram_512x128 sramModules_0( + .clock(clock), + .enable(io_enable), + .write(io_write), + .addr(io_addr), + .wdata(io_wdata), + .wmask(io_wmask), + .rdata(io_rdata) + ); +endmodule +module TCM128 ( + clock, + io_addr, + io_enable, + io_write, + io_wdata_0, + io_wdata_1, + io_wdata_2, + io_wdata_3, + io_wdata_4, + io_wdata_5, + io_wdata_6, + io_wdata_7, + io_wdata_8, + io_wdata_9, + io_wdata_10, + io_wdata_11, + io_wdata_12, + io_wdata_13, + io_wdata_14, + io_wdata_15, + io_wmask_0, + io_wmask_1, + io_wmask_2, + io_wmask_3, + io_wmask_4, + io_wmask_5, + io_wmask_6, + io_wmask_7, + io_wmask_8, + io_wmask_9, + io_wmask_10, + io_wmask_11, + io_wmask_12, + io_wmask_13, + io_wmask_14, + io_wmask_15, + io_rdata_0, + io_rdata_1, + io_rdata_2, + io_rdata_3, + io_rdata_4, + io_rdata_5, + io_rdata_6, + io_rdata_7, + io_rdata_8, + io_rdata_9, + io_rdata_10, + io_rdata_11, + io_rdata_12, + io_rdata_13, + io_rdata_14, + io_rdata_15 +); + input clock; + input [8:0] io_addr; + input io_enable; + input io_write; + input [7:0] io_wdata_0; + input [7:0] io_wdata_1; + input [7:0] io_wdata_2; + input [7:0] io_wdata_3; + input [7:0] io_wdata_4; + input [7:0] io_wdata_5; + input [7:0] io_wdata_6; + input [7:0] io_wdata_7; + input [7:0] io_wdata_8; + input [7:0] io_wdata_9; + input [7:0] io_wdata_10; + input [7:0] io_wdata_11; + input [7:0] io_wdata_12; + input [7:0] io_wdata_13; + input [7:0] io_wdata_14; + input [7:0] io_wdata_15; + input io_wmask_0; + input io_wmask_1; + input io_wmask_2; + input io_wmask_3; + input io_wmask_4; + input io_wmask_5; + input io_wmask_6; + input io_wmask_7; + input io_wmask_8; + input io_wmask_9; + input io_wmask_10; + input io_wmask_11; + input io_wmask_12; + input io_wmask_13; + input io_wmask_14; + input io_wmask_15; + output wire [7:0] io_rdata_0; + output wire [7:0] io_rdata_1; + output wire [7:0] io_rdata_2; + output wire [7:0] io_rdata_3; + output wire [7:0] io_rdata_4; + output wire [7:0] io_rdata_5; + output wire [7:0] io_rdata_6; + output wire [7:0] io_rdata_7; + output wire [7:0] io_rdata_8; + output wire [7:0] io_rdata_9; + output wire [7:0] io_rdata_10; + output wire [7:0] io_rdata_11; + output wire [7:0] io_rdata_12; + output wire [7:0] io_rdata_13; + output wire [7:0] io_rdata_14; + output wire [7:0] io_rdata_15; + wire [127:0] _sram_io_rdata; + SRAM_512x128 sram( + .clock(clock), + .io_addr(io_addr), + .io_enable(io_enable), + .io_write(io_write), + .io_wdata({io_wdata_15, io_wdata_14, io_wdata_13, io_wdata_12, io_wdata_11, io_wdata_10, io_wdata_9, io_wdata_8, io_wdata_7, io_wdata_6, io_wdata_5, io_wdata_4, io_wdata_3, io_wdata_2, io_wdata_1, io_wdata_0}), + .io_wmask({io_wmask_15, io_wmask_14, io_wmask_13, io_wmask_12, io_wmask_11, io_wmask_10, io_wmask_9, io_wmask_8, io_wmask_7, io_wmask_6, io_wmask_5, io_wmask_4, io_wmask_3, io_wmask_2, io_wmask_1, io_wmask_0}), + .io_rdata(_sram_io_rdata) + ); + assign io_rdata_0 = _sram_io_rdata[127:120]; + assign io_rdata_1 = _sram_io_rdata[119:112]; + assign io_rdata_2 = _sram_io_rdata[111:104]; + assign io_rdata_3 = _sram_io_rdata[103:96]; + assign io_rdata_4 = _sram_io_rdata[95:88]; + assign io_rdata_5 = _sram_io_rdata[87:80]; + assign io_rdata_6 = _sram_io_rdata[79:72]; + assign io_rdata_7 = _sram_io_rdata[71:64]; + assign io_rdata_8 = _sram_io_rdata[63:56]; + assign io_rdata_9 = _sram_io_rdata[55:48]; + assign io_rdata_10 = _sram_io_rdata[47:40]; + assign io_rdata_11 = _sram_io_rdata[39:32]; + assign io_rdata_12 = _sram_io_rdata[31:24]; + assign io_rdata_13 = _sram_io_rdata[23:16]; + assign io_rdata_14 = _sram_io_rdata[15:8]; + assign io_rdata_15 = _sram_io_rdata[7:0]; +endmodule +module SRAM ( + clock, + reset, + io_fabric_readDataAddr_valid, + io_fabric_readDataAddr_bits, + io_fabric_readData_valid, + io_fabric_readData_bits, + io_fabric_writeDataAddr_valid, + io_fabric_writeDataAddr_bits, + io_fabric_writeDataBits, + io_fabric_writeDataStrb, + io_sram_address, + io_sram_enable, + io_sram_isWrite, + io_sram_readData_0, + io_sram_readData_1, + io_sram_readData_2, + io_sram_readData_3, + io_sram_readData_4, + io_sram_readData_5, + io_sram_readData_6, + io_sram_readData_7, + io_sram_readData_8, + io_sram_readData_9, + io_sram_readData_10, + io_sram_readData_11, + io_sram_readData_12, + io_sram_readData_13, + io_sram_readData_14, + io_sram_readData_15, + io_sram_writeData_0, + io_sram_writeData_1, + io_sram_writeData_2, + io_sram_writeData_3, + io_sram_writeData_4, + io_sram_writeData_5, + io_sram_writeData_6, + io_sram_writeData_7, + io_sram_writeData_8, + io_sram_writeData_9, + io_sram_writeData_10, + io_sram_writeData_11, + io_sram_writeData_12, + io_sram_writeData_13, + io_sram_writeData_14, + io_sram_writeData_15, + io_sram_mask_0, + io_sram_mask_1, + io_sram_mask_2, + io_sram_mask_3, + io_sram_mask_4, + io_sram_mask_5, + io_sram_mask_6, + io_sram_mask_7, + io_sram_mask_8, + io_sram_mask_9, + io_sram_mask_10, + io_sram_mask_11, + io_sram_mask_12, + io_sram_mask_13, + io_sram_mask_14, + io_sram_mask_15 +); + input clock; + input reset; + input io_fabric_readDataAddr_valid; + input [31:0] io_fabric_readDataAddr_bits; + output wire io_fabric_readData_valid; + output wire [127:0] io_fabric_readData_bits; + input io_fabric_writeDataAddr_valid; + input [31:0] io_fabric_writeDataAddr_bits; + input [127:0] io_fabric_writeDataBits; + input [15:0] io_fabric_writeDataStrb; + output wire [8:0] io_sram_address; + output wire io_sram_enable; + output wire io_sram_isWrite; + input [7:0] io_sram_readData_0; + input [7:0] io_sram_readData_1; + input [7:0] io_sram_readData_2; + input [7:0] io_sram_readData_3; + input [7:0] io_sram_readData_4; + input [7:0] io_sram_readData_5; + input [7:0] io_sram_readData_6; + input [7:0] io_sram_readData_7; + input [7:0] io_sram_readData_8; + input [7:0] io_sram_readData_9; + input [7:0] io_sram_readData_10; + input [7:0] io_sram_readData_11; + input [7:0] io_sram_readData_12; + input [7:0] io_sram_readData_13; + input [7:0] io_sram_readData_14; + input [7:0] io_sram_readData_15; + output wire [7:0] io_sram_writeData_0; + output wire [7:0] io_sram_writeData_1; + output wire [7:0] io_sram_writeData_2; + output wire [7:0] io_sram_writeData_3; + output wire [7:0] io_sram_writeData_4; + output wire [7:0] io_sram_writeData_5; + output wire [7:0] io_sram_writeData_6; + output wire [7:0] io_sram_writeData_7; + output wire [7:0] io_sram_writeData_8; + output wire [7:0] io_sram_writeData_9; + output wire [7:0] io_sram_writeData_10; + output wire [7:0] io_sram_writeData_11; + output wire [7:0] io_sram_writeData_12; + output wire [7:0] io_sram_writeData_13; + output wire [7:0] io_sram_writeData_14; + output wire [7:0] io_sram_writeData_15; + output wire io_sram_mask_0; + output wire io_sram_mask_1; + output wire io_sram_mask_2; + output wire io_sram_mask_3; + output wire io_sram_mask_4; + output wire io_sram_mask_5; + output wire io_sram_mask_6; + output wire io_sram_mask_7; + output wire io_sram_mask_8; + output wire io_sram_mask_9; + output wire io_sram_mask_10; + output wire io_sram_mask_11; + output wire io_sram_mask_12; + output wire io_sram_mask_13; + output wire io_sram_mask_14; + output wire io_sram_mask_15; + reg readIssued; + always @(posedge clock or posedge reset) + if (reset) + readIssued <= 1'h0; + else + readIssued <= io_fabric_readDataAddr_valid & ~io_fabric_writeDataAddr_valid; + assign io_fabric_readData_valid = readIssued; + assign io_fabric_readData_bits = (readIssued ? {io_sram_readData_0, io_sram_readData_1, io_sram_readData_2, io_sram_readData_3, io_sram_readData_4, io_sram_readData_5, io_sram_readData_6, io_sram_readData_7, io_sram_readData_8, io_sram_readData_9, io_sram_readData_10, io_sram_readData_11, io_sram_readData_12, io_sram_readData_13, io_sram_readData_14, io_sram_readData_15} : 128'h00000000000000000000000000000000); + assign io_sram_address = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataAddr_bits[12:4] : 9'h000) | (io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[12:4] : 9'h000); + assign io_sram_enable = io_fabric_writeDataAddr_valid | io_fabric_readDataAddr_valid; + assign io_sram_isWrite = io_fabric_writeDataAddr_valid; + assign io_sram_writeData_0 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[7:0] : 8'h00); + assign io_sram_writeData_1 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[15:8] : 8'h00); + assign io_sram_writeData_2 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[23:16] : 8'h00); + assign io_sram_writeData_3 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[31:24] : 8'h00); + assign io_sram_writeData_4 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[39:32] : 8'h00); + assign io_sram_writeData_5 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[47:40] : 8'h00); + assign io_sram_writeData_6 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[55:48] : 8'h00); + assign io_sram_writeData_7 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[63:56] : 8'h00); + assign io_sram_writeData_8 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[71:64] : 8'h00); + assign io_sram_writeData_9 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[79:72] : 8'h00); + assign io_sram_writeData_10 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[87:80] : 8'h00); + assign io_sram_writeData_11 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[95:88] : 8'h00); + assign io_sram_writeData_12 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[103:96] : 8'h00); + assign io_sram_writeData_13 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[111:104] : 8'h00); + assign io_sram_writeData_14 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[119:112] : 8'h00); + assign io_sram_writeData_15 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[127:120] : 8'h00); + assign io_sram_mask_0 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[0]; + assign io_sram_mask_1 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[1]; + assign io_sram_mask_2 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[2]; + assign io_sram_mask_3 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[3]; + assign io_sram_mask_4 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[4]; + assign io_sram_mask_5 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[5]; + assign io_sram_mask_6 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[6]; + assign io_sram_mask_7 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[7]; + assign io_sram_mask_8 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[8]; + assign io_sram_mask_9 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[9]; + assign io_sram_mask_10 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[10]; + assign io_sram_mask_11 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[11]; + assign io_sram_mask_12 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[12]; + assign io_sram_mask_13 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[13]; + assign io_sram_mask_14 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[14]; + assign io_sram_mask_15 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[15]; +endmodule +module FabricArbiter ( + clock, + reset, + io_source_0_readDataAddr_valid, + io_source_0_readDataAddr_bits, + io_source_0_readData_bits, + io_source_0_writeDataAddr_valid, + io_source_0_writeDataAddr_bits, + io_source_0_writeDataBits, + io_source_0_writeDataStrb, + io_source_1_readDataAddr_valid, + io_source_1_readDataAddr_bits, + io_source_1_readData_valid, + io_source_1_readData_bits, + io_source_1_writeDataAddr_valid, + io_source_1_writeDataAddr_bits, + io_source_1_writeDataBits, + io_source_1_writeDataStrb, + io_fabricBusy_1, + io_port_readDataAddr_valid, + io_port_readDataAddr_bits, + io_port_readData_valid, + io_port_readData_bits, + io_port_writeDataAddr_valid, + io_port_writeDataAddr_bits, + io_port_writeDataBits, + io_port_writeDataStrb +); + input clock; + input reset; + input io_source_0_readDataAddr_valid; + input [31:0] io_source_0_readDataAddr_bits; + output wire [127:0] io_source_0_readData_bits; + input io_source_0_writeDataAddr_valid; + input [31:0] io_source_0_writeDataAddr_bits; + input [127:0] io_source_0_writeDataBits; + input [15:0] io_source_0_writeDataStrb; + input io_source_1_readDataAddr_valid; + input [31:0] io_source_1_readDataAddr_bits; + output wire io_source_1_readData_valid; + output wire [127:0] io_source_1_readData_bits; + input io_source_1_writeDataAddr_valid; + input [31:0] io_source_1_writeDataAddr_bits; + input [127:0] io_source_1_writeDataBits; + input [15:0] io_source_1_writeDataStrb; + output wire io_fabricBusy_1; + output wire io_port_readDataAddr_valid; + output wire [31:0] io_port_readDataAddr_bits; + input io_port_readData_valid; + input [127:0] io_port_readData_bits; + output wire io_port_writeDataAddr_valid; + output wire [31:0] io_port_writeDataAddr_bits; + output wire [127:0] io_port_writeDataBits; + output wire [15:0] io_port_writeDataStrb; + wire sourceValid_0 = io_source_0_readDataAddr_valid | io_source_0_writeDataAddr_valid; + wire sourceValid_1 = io_source_1_readDataAddr_valid | io_source_1_writeDataAddr_valid; + assign io_source_0_readData_bits = io_port_readData_bits; + assign io_source_1_readData_valid = io_port_readData_valid; + assign io_source_1_readData_bits = io_port_readData_bits; + assign io_fabricBusy_1 = sourceValid_0; + assign io_port_readDataAddr_valid = (sourceValid_0 ? io_source_0_readDataAddr_valid : sourceValid_1 & io_source_1_readDataAddr_valid); + assign io_port_readDataAddr_bits = (sourceValid_0 ? io_source_0_readDataAddr_bits : (sourceValid_1 ? io_source_1_readDataAddr_bits : 32'h00000000)); + assign io_port_writeDataAddr_valid = (sourceValid_0 ? io_source_0_writeDataAddr_valid : sourceValid_1 & io_source_1_writeDataAddr_valid); + assign io_port_writeDataAddr_bits = (sourceValid_0 ? io_source_0_writeDataAddr_bits : (sourceValid_1 ? io_source_1_writeDataAddr_bits : 32'h00000000)); + assign io_port_writeDataBits = (sourceValid_0 ? io_source_0_writeDataBits : (sourceValid_1 ? io_source_1_writeDataBits : 128'h00000000000000000000000000000000)); + assign io_port_writeDataStrb = (sourceValid_0 ? io_source_0_writeDataStrb : (sourceValid_1 ? io_source_1_writeDataStrb : 16'h0000)); +endmodule +module SRAM_2048x128 ( + clock, + io_addr, + io_enable, + io_write, + io_wdata, + io_wmask, + io_rdata +); + input clock; + input [10:0] io_addr; + input io_enable; + input io_write; + input [127:0] io_wdata; + input [15:0] io_wmask; + output wire [127:0] io_rdata; + Sram_2048x128 sramModules_0( + .clock(clock), + .enable(io_enable), + .write(io_write), + .addr(io_addr), + .wdata(io_wdata), + .wmask(io_wmask), + .rdata(io_rdata) + ); +endmodule +module TCM128_1 ( + clock, + io_addr, + io_enable, + io_write, + io_wdata_0, + io_wdata_1, + io_wdata_2, + io_wdata_3, + io_wdata_4, + io_wdata_5, + io_wdata_6, + io_wdata_7, + io_wdata_8, + io_wdata_9, + io_wdata_10, + io_wdata_11, + io_wdata_12, + io_wdata_13, + io_wdata_14, + io_wdata_15, + io_wmask_0, + io_wmask_1, + io_wmask_2, + io_wmask_3, + io_wmask_4, + io_wmask_5, + io_wmask_6, + io_wmask_7, + io_wmask_8, + io_wmask_9, + io_wmask_10, + io_wmask_11, + io_wmask_12, + io_wmask_13, + io_wmask_14, + io_wmask_15, + io_rdata_0, + io_rdata_1, + io_rdata_2, + io_rdata_3, + io_rdata_4, + io_rdata_5, + io_rdata_6, + io_rdata_7, + io_rdata_8, + io_rdata_9, + io_rdata_10, + io_rdata_11, + io_rdata_12, + io_rdata_13, + io_rdata_14, + io_rdata_15 +); + input clock; + input [10:0] io_addr; + input io_enable; + input io_write; + input [7:0] io_wdata_0; + input [7:0] io_wdata_1; + input [7:0] io_wdata_2; + input [7:0] io_wdata_3; + input [7:0] io_wdata_4; + input [7:0] io_wdata_5; + input [7:0] io_wdata_6; + input [7:0] io_wdata_7; + input [7:0] io_wdata_8; + input [7:0] io_wdata_9; + input [7:0] io_wdata_10; + input [7:0] io_wdata_11; + input [7:0] io_wdata_12; + input [7:0] io_wdata_13; + input [7:0] io_wdata_14; + input [7:0] io_wdata_15; + input io_wmask_0; + input io_wmask_1; + input io_wmask_2; + input io_wmask_3; + input io_wmask_4; + input io_wmask_5; + input io_wmask_6; + input io_wmask_7; + input io_wmask_8; + input io_wmask_9; + input io_wmask_10; + input io_wmask_11; + input io_wmask_12; + input io_wmask_13; + input io_wmask_14; + input io_wmask_15; + output wire [7:0] io_rdata_0; + output wire [7:0] io_rdata_1; + output wire [7:0] io_rdata_2; + output wire [7:0] io_rdata_3; + output wire [7:0] io_rdata_4; + output wire [7:0] io_rdata_5; + output wire [7:0] io_rdata_6; + output wire [7:0] io_rdata_7; + output wire [7:0] io_rdata_8; + output wire [7:0] io_rdata_9; + output wire [7:0] io_rdata_10; + output wire [7:0] io_rdata_11; + output wire [7:0] io_rdata_12; + output wire [7:0] io_rdata_13; + output wire [7:0] io_rdata_14; + output wire [7:0] io_rdata_15; + wire [127:0] _sram_io_rdata; + SRAM_2048x128 sram( + .clock(clock), + .io_addr(io_addr), + .io_enable(io_enable), + .io_write(io_write), + .io_wdata({io_wdata_15, io_wdata_14, io_wdata_13, io_wdata_12, io_wdata_11, io_wdata_10, io_wdata_9, io_wdata_8, io_wdata_7, io_wdata_6, io_wdata_5, io_wdata_4, io_wdata_3, io_wdata_2, io_wdata_1, io_wdata_0}), + .io_wmask({io_wmask_15, io_wmask_14, io_wmask_13, io_wmask_12, io_wmask_11, io_wmask_10, io_wmask_9, io_wmask_8, io_wmask_7, io_wmask_6, io_wmask_5, io_wmask_4, io_wmask_3, io_wmask_2, io_wmask_1, io_wmask_0}), + .io_rdata(_sram_io_rdata) + ); + assign io_rdata_0 = _sram_io_rdata[127:120]; + assign io_rdata_1 = _sram_io_rdata[119:112]; + assign io_rdata_2 = _sram_io_rdata[111:104]; + assign io_rdata_3 = _sram_io_rdata[103:96]; + assign io_rdata_4 = _sram_io_rdata[95:88]; + assign io_rdata_5 = _sram_io_rdata[87:80]; + assign io_rdata_6 = _sram_io_rdata[79:72]; + assign io_rdata_7 = _sram_io_rdata[71:64]; + assign io_rdata_8 = _sram_io_rdata[63:56]; + assign io_rdata_9 = _sram_io_rdata[55:48]; + assign io_rdata_10 = _sram_io_rdata[47:40]; + assign io_rdata_11 = _sram_io_rdata[39:32]; + assign io_rdata_12 = _sram_io_rdata[31:24]; + assign io_rdata_13 = _sram_io_rdata[23:16]; + assign io_rdata_14 = _sram_io_rdata[15:8]; + assign io_rdata_15 = _sram_io_rdata[7:0]; +endmodule +module SRAM_1 ( + clock, + reset, + io_fabric_readDataAddr_valid, + io_fabric_readDataAddr_bits, + io_fabric_readData_valid, + io_fabric_readData_bits, + io_fabric_writeDataAddr_valid, + io_fabric_writeDataAddr_bits, + io_fabric_writeDataBits, + io_fabric_writeDataStrb, + io_sram_address, + io_sram_enable, + io_sram_isWrite, + io_sram_readData_0, + io_sram_readData_1, + io_sram_readData_2, + io_sram_readData_3, + io_sram_readData_4, + io_sram_readData_5, + io_sram_readData_6, + io_sram_readData_7, + io_sram_readData_8, + io_sram_readData_9, + io_sram_readData_10, + io_sram_readData_11, + io_sram_readData_12, + io_sram_readData_13, + io_sram_readData_14, + io_sram_readData_15, + io_sram_writeData_0, + io_sram_writeData_1, + io_sram_writeData_2, + io_sram_writeData_3, + io_sram_writeData_4, + io_sram_writeData_5, + io_sram_writeData_6, + io_sram_writeData_7, + io_sram_writeData_8, + io_sram_writeData_9, + io_sram_writeData_10, + io_sram_writeData_11, + io_sram_writeData_12, + io_sram_writeData_13, + io_sram_writeData_14, + io_sram_writeData_15, + io_sram_mask_0, + io_sram_mask_1, + io_sram_mask_2, + io_sram_mask_3, + io_sram_mask_4, + io_sram_mask_5, + io_sram_mask_6, + io_sram_mask_7, + io_sram_mask_8, + io_sram_mask_9, + io_sram_mask_10, + io_sram_mask_11, + io_sram_mask_12, + io_sram_mask_13, + io_sram_mask_14, + io_sram_mask_15 +); + input clock; + input reset; + input io_fabric_readDataAddr_valid; + input [31:0] io_fabric_readDataAddr_bits; + output wire io_fabric_readData_valid; + output wire [127:0] io_fabric_readData_bits; + input io_fabric_writeDataAddr_valid; + input [31:0] io_fabric_writeDataAddr_bits; + input [127:0] io_fabric_writeDataBits; + input [15:0] io_fabric_writeDataStrb; + output wire [10:0] io_sram_address; + output wire io_sram_enable; + output wire io_sram_isWrite; + input [7:0] io_sram_readData_0; + input [7:0] io_sram_readData_1; + input [7:0] io_sram_readData_2; + input [7:0] io_sram_readData_3; + input [7:0] io_sram_readData_4; + input [7:0] io_sram_readData_5; + input [7:0] io_sram_readData_6; + input [7:0] io_sram_readData_7; + input [7:0] io_sram_readData_8; + input [7:0] io_sram_readData_9; + input [7:0] io_sram_readData_10; + input [7:0] io_sram_readData_11; + input [7:0] io_sram_readData_12; + input [7:0] io_sram_readData_13; + input [7:0] io_sram_readData_14; + input [7:0] io_sram_readData_15; + output wire [7:0] io_sram_writeData_0; + output wire [7:0] io_sram_writeData_1; + output wire [7:0] io_sram_writeData_2; + output wire [7:0] io_sram_writeData_3; + output wire [7:0] io_sram_writeData_4; + output wire [7:0] io_sram_writeData_5; + output wire [7:0] io_sram_writeData_6; + output wire [7:0] io_sram_writeData_7; + output wire [7:0] io_sram_writeData_8; + output wire [7:0] io_sram_writeData_9; + output wire [7:0] io_sram_writeData_10; + output wire [7:0] io_sram_writeData_11; + output wire [7:0] io_sram_writeData_12; + output wire [7:0] io_sram_writeData_13; + output wire [7:0] io_sram_writeData_14; + output wire [7:0] io_sram_writeData_15; + output wire io_sram_mask_0; + output wire io_sram_mask_1; + output wire io_sram_mask_2; + output wire io_sram_mask_3; + output wire io_sram_mask_4; + output wire io_sram_mask_5; + output wire io_sram_mask_6; + output wire io_sram_mask_7; + output wire io_sram_mask_8; + output wire io_sram_mask_9; + output wire io_sram_mask_10; + output wire io_sram_mask_11; + output wire io_sram_mask_12; + output wire io_sram_mask_13; + output wire io_sram_mask_14; + output wire io_sram_mask_15; + reg readIssued; + always @(posedge clock or posedge reset) + if (reset) + readIssued <= 1'h0; + else + readIssued <= io_fabric_readDataAddr_valid & ~io_fabric_writeDataAddr_valid; + assign io_fabric_readData_valid = readIssued; + assign io_fabric_readData_bits = (readIssued ? {io_sram_readData_0, io_sram_readData_1, io_sram_readData_2, io_sram_readData_3, io_sram_readData_4, io_sram_readData_5, io_sram_readData_6, io_sram_readData_7, io_sram_readData_8, io_sram_readData_9, io_sram_readData_10, io_sram_readData_11, io_sram_readData_12, io_sram_readData_13, io_sram_readData_14, io_sram_readData_15} : 128'h00000000000000000000000000000000); + assign io_sram_address = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataAddr_bits[14:4] : 11'h000) | (io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[14:4] : 11'h000); + assign io_sram_enable = io_fabric_writeDataAddr_valid | io_fabric_readDataAddr_valid; + assign io_sram_isWrite = io_fabric_writeDataAddr_valid; + assign io_sram_writeData_0 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[7:0] : 8'h00); + assign io_sram_writeData_1 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[15:8] : 8'h00); + assign io_sram_writeData_2 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[23:16] : 8'h00); + assign io_sram_writeData_3 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[31:24] : 8'h00); + assign io_sram_writeData_4 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[39:32] : 8'h00); + assign io_sram_writeData_5 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[47:40] : 8'h00); + assign io_sram_writeData_6 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[55:48] : 8'h00); + assign io_sram_writeData_7 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[63:56] : 8'h00); + assign io_sram_writeData_8 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[71:64] : 8'h00); + assign io_sram_writeData_9 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[79:72] : 8'h00); + assign io_sram_writeData_10 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[87:80] : 8'h00); + assign io_sram_writeData_11 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[95:88] : 8'h00); + assign io_sram_writeData_12 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[103:96] : 8'h00); + assign io_sram_writeData_13 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[111:104] : 8'h00); + assign io_sram_writeData_14 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[119:112] : 8'h00); + assign io_sram_writeData_15 = (io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[127:120] : 8'h00); + assign io_sram_mask_0 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[0]; + assign io_sram_mask_1 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[1]; + assign io_sram_mask_2 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[2]; + assign io_sram_mask_3 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[3]; + assign io_sram_mask_4 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[4]; + assign io_sram_mask_5 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[5]; + assign io_sram_mask_6 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[6]; + assign io_sram_mask_7 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[7]; + assign io_sram_mask_8 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[8]; + assign io_sram_mask_9 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[9]; + assign io_sram_mask_10 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[10]; + assign io_sram_mask_11 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[11]; + assign io_sram_mask_12 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[12]; + assign io_sram_mask_13 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[13]; + assign io_sram_mask_14 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[14]; + assign io_sram_mask_15 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[15]; +endmodule +module FabricMux ( + clock, + reset, + io_source_readDataAddr_valid, + io_source_readDataAddr_bits, + io_source_readData_valid, + io_source_readData_bits, + io_source_writeDataAddr_valid, + io_source_writeDataAddr_bits, + io_source_writeDataBits, + io_source_writeDataStrb, + io_source_writeResp, + io_fabricBusy, + io_ports_0_readDataAddr_valid, + io_ports_0_readDataAddr_bits, + io_ports_0_readData_valid, + io_ports_0_readData_bits, + io_ports_0_writeDataAddr_valid, + io_ports_0_writeDataAddr_bits, + io_ports_0_writeDataBits, + io_ports_0_writeDataStrb, + io_ports_1_readDataAddr_valid, + io_ports_1_readDataAddr_bits, + io_ports_1_readData_valid, + io_ports_1_readData_bits, + io_ports_1_writeDataAddr_valid, + io_ports_1_writeDataAddr_bits, + io_ports_1_writeDataBits, + io_ports_1_writeDataStrb, + io_ports_2_readDataAddr_bits, + io_ports_2_readData_valid, + io_ports_2_readData_bits, + io_ports_2_writeDataAddr_valid, + io_ports_2_writeDataAddr_bits, + io_ports_2_writeDataBits, + io_ports_2_writeResp, + io_periBusy_0, + io_periBusy_1 +); + input clock; + input reset; + input io_source_readDataAddr_valid; + input [31:0] io_source_readDataAddr_bits; + output wire io_source_readData_valid; + output wire [127:0] io_source_readData_bits; + input io_source_writeDataAddr_valid; + input [31:0] io_source_writeDataAddr_bits; + input [127:0] io_source_writeDataBits; + input [15:0] io_source_writeDataStrb; + output wire io_source_writeResp; + output wire io_fabricBusy; + output wire io_ports_0_readDataAddr_valid; + output wire [31:0] io_ports_0_readDataAddr_bits; + input io_ports_0_readData_valid; + input [127:0] io_ports_0_readData_bits; + output wire io_ports_0_writeDataAddr_valid; + output wire [31:0] io_ports_0_writeDataAddr_bits; + output wire [127:0] io_ports_0_writeDataBits; + output wire [15:0] io_ports_0_writeDataStrb; + output wire io_ports_1_readDataAddr_valid; + output wire [31:0] io_ports_1_readDataAddr_bits; + input io_ports_1_readData_valid; + input [127:0] io_ports_1_readData_bits; + output wire io_ports_1_writeDataAddr_valid; + output wire [31:0] io_ports_1_writeDataAddr_bits; + output wire [127:0] io_ports_1_writeDataBits; + output wire [15:0] io_ports_1_writeDataStrb; + output wire [31:0] io_ports_2_readDataAddr_bits; + input io_ports_2_readData_valid; + input [127:0] io_ports_2_readData_bits; + output wire io_ports_2_writeDataAddr_valid; + output wire [31:0] io_ports_2_writeDataAddr_bits; + output wire [127:0] io_ports_2_writeDataBits; + input io_ports_2_writeResp; + input io_periBusy_0; + input io_periBusy_1; + wire sourceValid = io_source_readDataAddr_valid | io_source_writeDataAddr_valid; + wire [31:0] addr = (io_source_readDataAddr_valid ? io_source_readDataAddr_bits : 32'h00000000) | (io_source_writeDataAddr_valid ? io_source_writeDataAddr_bits : 32'h00000000); + wire _selected_T_5 = sourceValid & (addr < 32'h00002000); + wire _selected_T_11 = (sourceValid & |addr[31:16]) & (addr < 32'h00018000); + wire _selected_T_18_valid = (sourceValid & (addr > 32'h0002ffff)) & (addr < 32'h00031000); + wire selected_valid = (_selected_T_5 | _selected_T_11) | _selected_T_18_valid; + wire [1:0] selected_bits = (_selected_T_5 ? 2'h0 : (_selected_T_11 ? 2'h1 : {_selected_T_18_valid, 1'h0})); + wire _io_fabricBusy_T = selected_bits == 2'h0; + wire portSelected_0 = (selected_valid & _io_fabricBusy_T) & ~io_periBusy_0; + wire _io_fabricBusy_T_2 = selected_bits == 2'h1; + wire portSelected_1 = (selected_valid & _io_fabricBusy_T_2) & ~io_periBusy_1; + wire _io_fabricBusy_T_4 = selected_bits == 2'h2; + wire _portSelected_T_7 = selected_valid & _io_fabricBusy_T_4; + wire _io_fabricBusy_T_1 = selected_valid & _io_fabricBusy_T; + wire _io_fabricBusy_T_3 = selected_valid & _io_fabricBusy_T_2; + wire io_ports_0_readDataAddr_valid_0 = portSelected_0 & io_source_readDataAddr_valid; + wire io_ports_1_readDataAddr_valid_0 = portSelected_1 & io_source_readDataAddr_valid; + wire _lastReadSelected_T_19 = _portSelected_T_7 & io_source_readDataAddr_valid; + reg lastReadSelected_valid; + reg [1:0] lastReadSelected_bits; + wire _io_source_readData_T_1 = lastReadSelected_valid & (lastReadSelected_bits == 2'h0); + wire _io_source_readData_T_3 = lastReadSelected_valid & (lastReadSelected_bits == 2'h1); + wire _io_source_readData_T_5 = lastReadSelected_valid & (lastReadSelected_bits == 2'h2); + always @(posedge clock or posedge reset) + if (reset) begin + lastReadSelected_valid <= 1'h0; + lastReadSelected_bits <= 2'h0; + end + else begin + lastReadSelected_valid <= (io_ports_0_readDataAddr_valid_0 | io_ports_1_readDataAddr_valid_0) | _lastReadSelected_T_19; + lastReadSelected_bits <= {1'h0, io_ports_1_readDataAddr_valid_0} | {_lastReadSelected_T_19, 1'h0}; + end + assign io_source_readData_valid = ((_io_source_readData_T_1 & io_ports_0_readData_valid) | (_io_source_readData_T_3 & io_ports_1_readData_valid)) | (_io_source_readData_T_5 & io_ports_2_readData_valid); + assign io_source_readData_bits = ((_io_source_readData_T_1 ? io_ports_0_readData_bits : 128'h00000000000000000000000000000000) | (_io_source_readData_T_3 ? io_ports_1_readData_bits : 128'h00000000000000000000000000000000)) | (_io_source_readData_T_5 ? io_ports_2_readData_bits : 128'h00000000000000000000000000000000); + assign io_source_writeResp = (portSelected_0 | portSelected_1) | (_portSelected_T_7 & io_ports_2_writeResp); + assign io_fabricBusy = (_io_fabricBusy_T_1 & io_periBusy_0) | (_io_fabricBusy_T_3 & io_periBusy_1); + assign io_ports_0_readDataAddr_valid = io_ports_0_readDataAddr_valid_0; + assign io_ports_0_readDataAddr_bits = (portSelected_0 ? io_source_readDataAddr_bits : 32'h00000000); + assign io_ports_0_writeDataAddr_valid = portSelected_0 & io_source_writeDataAddr_valid; + assign io_ports_0_writeDataAddr_bits = (portSelected_0 ? io_source_writeDataAddr_bits : 32'h00000000); + assign io_ports_0_writeDataBits = (portSelected_0 ? io_source_writeDataBits : 128'h00000000000000000000000000000000); + assign io_ports_0_writeDataStrb = (portSelected_0 ? io_source_writeDataStrb : 16'h0000); + assign io_ports_1_readDataAddr_valid = io_ports_1_readDataAddr_valid_0; + assign io_ports_1_readDataAddr_bits = (portSelected_1 ? io_source_readDataAddr_bits & 32'hfffeffff : 32'h00000000); + assign io_ports_1_writeDataAddr_valid = portSelected_1 & io_source_writeDataAddr_valid; + assign io_ports_1_writeDataAddr_bits = (portSelected_1 ? io_source_writeDataAddr_bits & 32'hfffeffff : 32'h00000000); + assign io_ports_1_writeDataBits = (portSelected_1 ? io_source_writeDataBits : 128'h00000000000000000000000000000000); + assign io_ports_1_writeDataStrb = (portSelected_1 ? io_source_writeDataStrb : 16'h0000); + assign io_ports_2_readDataAddr_bits = (_portSelected_T_7 ? io_source_readDataAddr_bits & 32'hfffcffff : 32'h00000000); + assign io_ports_2_writeDataAddr_valid = _portSelected_T_7 & io_source_writeDataAddr_valid; + assign io_ports_2_writeDataAddr_bits = (_portSelected_T_7 ? io_source_writeDataAddr_bits & 32'hfffcffff : 32'h00000000); + assign io_ports_2_writeDataBits = (_portSelected_T_7 ? io_source_writeDataBits : 128'h00000000000000000000000000000000); +endmodule +module CoralNPURRArbiter ( + clock, + reset, + io_in_0_ready, + io_in_0_valid, + io_in_0_bits_addr, + io_in_0_bits_prot, + io_in_0_bits_id, + io_in_0_bits_len, + io_in_0_bits_size, + io_in_0_bits_burst, + io_in_0_bits_lock, + io_in_0_bits_cache, + io_in_0_bits_qos, + io_in_0_bits_region, + io_in_1_ready, + io_in_1_valid, + io_in_1_bits_addr, + io_in_1_bits_prot, + io_in_1_bits_id, + io_in_1_bits_len, + io_in_1_bits_size, + io_in_1_bits_burst, + io_in_1_bits_lock, + io_in_1_bits_cache, + io_in_1_bits_qos, + io_in_1_bits_region, + io_out_ready, + io_out_valid, + io_out_bits_addr, + io_out_bits_prot, + io_out_bits_id, + io_out_bits_len, + io_out_bits_size, + io_out_bits_burst, + io_out_bits_lock, + io_out_bits_cache, + io_out_bits_qos, + io_out_bits_region, + io_chosen +); + input clock; + input reset; + output wire io_in_0_ready; + input io_in_0_valid; + input [31:0] io_in_0_bits_addr; + input [2:0] io_in_0_bits_prot; + input [5:0] io_in_0_bits_id; + input [7:0] io_in_0_bits_len; + input [2:0] io_in_0_bits_size; + input [1:0] io_in_0_bits_burst; + input io_in_0_bits_lock; + input [3:0] io_in_0_bits_cache; + input [3:0] io_in_0_bits_qos; + input [3:0] io_in_0_bits_region; + output wire io_in_1_ready; + input io_in_1_valid; + input [31:0] io_in_1_bits_addr; + input [2:0] io_in_1_bits_prot; + input [5:0] io_in_1_bits_id; + input [7:0] io_in_1_bits_len; + input [2:0] io_in_1_bits_size; + input [1:0] io_in_1_bits_burst; + input io_in_1_bits_lock; + input [3:0] io_in_1_bits_cache; + input [3:0] io_in_1_bits_qos; + input [3:0] io_in_1_bits_region; + input io_out_ready; + output wire io_out_valid; + output wire [31:0] io_out_bits_addr; + output wire [2:0] io_out_bits_prot; + output wire [5:0] io_out_bits_id; + output wire [7:0] io_out_bits_len; + output wire [2:0] io_out_bits_size; + output wire [1:0] io_out_bits_burst; + output wire io_out_bits_lock; + output wire [3:0] io_out_bits_cache; + output wire [3:0] io_out_bits_qos; + output wire [3:0] io_out_bits_region; + output wire io_chosen; + wire io_chosen_choice; + wire io_out_valid_0 = (io_chosen_choice ? io_in_1_valid : io_in_0_valid); + reg ctrl_validMask_grantMask_lastGrant; + wire ctrl_validMask_1 = io_in_1_valid & ~ctrl_validMask_grantMask_lastGrant; + assign io_chosen_choice = ctrl_validMask_1 | ~io_in_0_valid; + always @(posedge clock or posedge reset) + if (reset) + ctrl_validMask_grantMask_lastGrant <= 1'h0; + else if (io_out_ready & io_out_valid_0) + ctrl_validMask_grantMask_lastGrant <= io_chosen_choice; + assign io_in_0_ready = ~ctrl_validMask_1 & io_out_ready; + assign io_in_1_ready = (~ctrl_validMask_grantMask_lastGrant | ~(ctrl_validMask_1 | io_in_0_valid)) & io_out_ready; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_addr = (io_chosen_choice ? io_in_1_bits_addr : io_in_0_bits_addr); + assign io_out_bits_prot = (io_chosen_choice ? io_in_1_bits_prot : io_in_0_bits_prot); + assign io_out_bits_id = (io_chosen_choice ? io_in_1_bits_id : io_in_0_bits_id); + assign io_out_bits_len = (io_chosen_choice ? io_in_1_bits_len : io_in_0_bits_len); + assign io_out_bits_size = (io_chosen_choice ? io_in_1_bits_size : io_in_0_bits_size); + assign io_out_bits_burst = (io_chosen_choice ? io_in_1_bits_burst : io_in_0_bits_burst); + assign io_out_bits_lock = (io_chosen_choice ? io_in_1_bits_lock : io_in_0_bits_lock); + assign io_out_bits_cache = (io_chosen_choice ? io_in_1_bits_cache : io_in_0_bits_cache); + assign io_out_bits_qos = (io_chosen_choice ? io_in_1_bits_qos : io_in_0_bits_qos); + assign io_out_bits_region = (io_chosen_choice ? io_in_1_bits_region : io_in_0_bits_region); + assign io_chosen = io_chosen_choice; +endmodule +module ram_2x67 ( + R0_addr, + R0_en, + R0_clk, + R0_data, + W0_addr, + W0_en, + W0_clk, + W0_data +); + input R0_addr; + input R0_en; + input R0_clk; + output wire [66:0] R0_data; + input W0_addr; + input W0_en; + input W0_clk; + input [66:0] W0_data; + reg [66:0] Memory [0:1]; + always @(posedge W0_clk) + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + assign R0_data = (R0_en ? Memory[R0_addr] : 67'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); +endmodule +module Queue2_AxiAddress ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_addr, + io_enq_bits_prot, + io_enq_bits_id, + io_enq_bits_len, + io_enq_bits_size, + io_enq_bits_burst, + io_enq_bits_lock, + io_enq_bits_cache, + io_enq_bits_qos, + io_enq_bits_region, + io_deq_ready, + io_deq_valid, + io_deq_bits_addr, + io_deq_bits_prot, + io_deq_bits_id, + io_deq_bits_len, + io_deq_bits_size, + io_deq_bits_burst, + io_deq_bits_lock, + io_deq_bits_cache, + io_deq_bits_qos, + io_deq_bits_region +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [31:0] io_enq_bits_addr; + input [2:0] io_enq_bits_prot; + input [5:0] io_enq_bits_id; + input [7:0] io_enq_bits_len; + input [2:0] io_enq_bits_size; + input [1:0] io_enq_bits_burst; + input io_enq_bits_lock; + input [3:0] io_enq_bits_cache; + input [3:0] io_enq_bits_qos; + input [3:0] io_enq_bits_region; + input io_deq_ready; + output wire io_deq_valid; + output wire [31:0] io_deq_bits_addr; + output wire [2:0] io_deq_bits_prot; + output wire [5:0] io_deq_bits_id; + output wire [7:0] io_deq_bits_len; + output wire [2:0] io_deq_bits_size; + output wire [1:0] io_deq_bits_burst; + output wire io_deq_bits_lock; + output wire [3:0] io_deq_bits_cache; + output wire [3:0] io_deq_bits_qos; + output wire [3:0] io_deq_bits_region; + wire [66:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + ram_2x67 ram_ext( + .R0_addr(wrap_1), + .R0_en(1'h1), + .R0_clk(clock), + .R0_data(_ram_ext_R0_data), + .W0_addr(wrap), + .W0_en(do_enq), + .W0_clk(clock), + .W0_data({io_enq_bits_addr, io_enq_bits_prot, io_enq_bits_id, io_enq_bits_len, io_enq_bits_size, io_enq_bits_burst, io_enq_bits_lock, io_enq_bits_cache, io_enq_bits_qos, io_enq_bits_region}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_addr = _ram_ext_R0_data[66:35]; + assign io_deq_bits_prot = _ram_ext_R0_data[34:32]; + assign io_deq_bits_id = _ram_ext_R0_data[31:26]; + assign io_deq_bits_len = _ram_ext_R0_data[25:18]; + assign io_deq_bits_size = _ram_ext_R0_data[17:15]; + assign io_deq_bits_burst = _ram_ext_R0_data[14:13]; + assign io_deq_bits_lock = _ram_ext_R0_data[12]; + assign io_deq_bits_cache = _ram_ext_R0_data[11:8]; + assign io_deq_bits_qos = _ram_ext_R0_data[7:4]; + assign io_deq_bits_region = _ram_ext_R0_data[3:0]; +endmodule +module Queue1_RWAxiAddress ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_addr_addr, + io_enq_bits_addr_prot, + io_enq_bits_addr_id, + io_enq_bits_addr_len, + io_enq_bits_addr_size, + io_enq_bits_addr_burst, + io_enq_bits_addr_lock, + io_enq_bits_addr_cache, + io_enq_bits_addr_qos, + io_enq_bits_addr_region, + io_enq_bits_write, + io_deq_ready, + io_deq_valid, + io_deq_bits_addr_addr, + io_deq_bits_addr_id, + io_deq_bits_addr_len, + io_deq_bits_addr_size, + io_deq_bits_addr_burst, + io_deq_bits_write +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [31:0] io_enq_bits_addr_addr; + input [2:0] io_enq_bits_addr_prot; + input [5:0] io_enq_bits_addr_id; + input [7:0] io_enq_bits_addr_len; + input [2:0] io_enq_bits_addr_size; + input [1:0] io_enq_bits_addr_burst; + input io_enq_bits_addr_lock; + input [3:0] io_enq_bits_addr_cache; + input [3:0] io_enq_bits_addr_qos; + input [3:0] io_enq_bits_addr_region; + input io_enq_bits_write; + input io_deq_ready; + output wire io_deq_valid; + output wire [31:0] io_deq_bits_addr_addr; + output wire [5:0] io_deq_bits_addr_id; + output wire [7:0] io_deq_bits_addr_len; + output wire [2:0] io_deq_bits_addr_size; + output wire [1:0] io_deq_bits_addr_burst; + output wire io_deq_bits_write; + reg [67:0] ram; + wire io_enq_ready_0; + reg full; + wire do_enq = io_enq_ready_0 & io_enq_valid; + assign io_enq_ready_0 = io_deq_ready | ~full; + always @(posedge clock or posedge reset) + if (reset) + full <= 1'h0; + else if (~(do_enq == (io_deq_ready & full))) + full <= do_enq; + always @(posedge clock) + if (do_enq) + ram <= {io_enq_bits_addr_addr, io_enq_bits_addr_prot, io_enq_bits_addr_id, io_enq_bits_addr_len, io_enq_bits_addr_size, io_enq_bits_addr_burst, io_enq_bits_addr_lock, io_enq_bits_addr_cache, io_enq_bits_addr_qos, io_enq_bits_addr_region, io_enq_bits_write}; + assign io_enq_ready = io_enq_ready_0; + assign io_deq_valid = full; + assign io_deq_bits_addr_addr = ram[67:36]; + assign io_deq_bits_addr_id = ram[32:27]; + assign io_deq_bits_addr_len = ram[26:19]; + assign io_deq_bits_addr_size = ram[18:16]; + assign io_deq_bits_addr_burst = ram[15:14]; + assign io_deq_bits_write = ram[0]; +endmodule +module ram_3x145 ( + R0_addr, + R0_en, + R0_clk, + R0_data, + W0_addr, + W0_en, + W0_clk, + W0_data +); + input [1:0] R0_addr; + input R0_en; + input R0_clk; + output wire [144:0] R0_data; + input [1:0] W0_addr; + input W0_en; + input W0_clk; + input [144:0] W0_data; + reg [144:0] Memory [0:2]; + always @(posedge W0_clk) + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + assign R0_data = (R0_en ? Memory[R0_addr] : 145'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); +endmodule +module Queue3_AxiWriteData ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_data, + io_enq_bits_last, + io_enq_bits_strb, + io_deq_ready, + io_deq_valid, + io_deq_bits_data, + io_deq_bits_last, + io_deq_bits_strb +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [127:0] io_enq_bits_data; + input io_enq_bits_last; + input [15:0] io_enq_bits_strb; + input io_deq_ready; + output wire io_deq_valid; + output wire [127:0] io_deq_bits_data; + output wire io_deq_bits_last; + output wire [15:0] io_deq_bits_strb; + wire [144:0] _ram_ext_R0_data; + reg [1:0] enq_ptr_value; + reg [1:0] deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) + if (reset) begin + enq_ptr_value <= 2'h0; + deq_ptr_value <= 2'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + enq_ptr_value <= (enq_ptr_value == 2'h2 ? 2'h0 : enq_ptr_value + 2'h1); + if (do_deq) + deq_ptr_value <= (deq_ptr_value == 2'h2 ? 2'h0 : deq_ptr_value + 2'h1); + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + ram_3x145 ram_ext( + .R0_addr(deq_ptr_value), + .R0_en(1'h1), + .R0_clk(clock), + .R0_data(_ram_ext_R0_data), + .W0_addr(enq_ptr_value), + .W0_en(do_enq), + .W0_clk(clock), + .W0_data({io_enq_bits_data, io_enq_bits_last, io_enq_bits_strb}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[144:17]; + assign io_deq_bits_last = _ram_ext_R0_data[16]; + assign io_deq_bits_strb = _ram_ext_R0_data[15:0]; +endmodule +module ram_2x8 ( + R0_addr, + R0_en, + R0_clk, + R0_data, + W0_addr, + W0_en, + W0_clk, + W0_data +); + input R0_addr; + input R0_en; + input R0_clk; + output wire [7:0] R0_data; + input W0_addr; + input W0_en; + input W0_clk; + input [7:0] W0_data; + reg [7:0] Memory [0:1]; + always @(posedge W0_clk) + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + assign R0_data = (R0_en ? Memory[R0_addr] : 8'bxxxxxxxx); +endmodule +module Queue2_AxiWriteResponse ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_id, + io_enq_bits_resp, + io_deq_ready, + io_deq_valid, + io_deq_bits_id, + io_deq_bits_resp +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [5:0] io_enq_bits_id; + input [1:0] io_enq_bits_resp; + input io_deq_ready; + output wire io_deq_valid; + output wire [5:0] io_deq_bits_id; + output wire [1:0] io_deq_bits_resp; + wire [7:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + ram_2x8 ram_ext( + .R0_addr(wrap_1), + .R0_en(1'h1), + .R0_clk(clock), + .R0_data(_ram_ext_R0_data), + .W0_addr(wrap), + .W0_en(do_enq), + .W0_clk(clock), + .W0_data({io_enq_bits_id, io_enq_bits_resp}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_id = _ram_ext_R0_data[7:2]; + assign io_deq_bits_resp = _ram_ext_R0_data[1:0]; +endmodule +module ram_3x137 ( + R0_addr, + R0_en, + R0_clk, + R0_data, + W0_addr, + W0_en, + W0_clk, + W0_data +); + input [1:0] R0_addr; + input R0_en; + input R0_clk; + output wire [136:0] R0_data; + input [1:0] W0_addr; + input W0_en; + input W0_clk; + input [136:0] W0_data; + reg [136:0] Memory [0:2]; + always @(posedge W0_clk) + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + assign R0_data = (R0_en ? Memory[R0_addr] : 137'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); +endmodule +module Queue3_AxiReadData ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_data, + io_enq_bits_id, + io_enq_bits_resp, + io_enq_bits_last, + io_deq_ready, + io_deq_valid, + io_deq_bits_data, + io_deq_bits_id, + io_deq_bits_resp, + io_deq_bits_last, + io_count +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [127:0] io_enq_bits_data; + input [5:0] io_enq_bits_id; + input [1:0] io_enq_bits_resp; + input io_enq_bits_last; + input io_deq_ready; + output wire io_deq_valid; + output wire [127:0] io_deq_bits_data; + output wire [5:0] io_deq_bits_id; + output wire [1:0] io_deq_bits_resp; + output wire io_deq_bits_last; + output wire [1:0] io_count; + wire [136:0] _ram_ext_R0_data; + reg [1:0] enq_ptr_value; + reg [1:0] deq_ptr_value; + reg maybe_full; + wire ptr_match = enq_ptr_value == deq_ptr_value; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire [1:0] _ptr_diff_T = enq_ptr_value - deq_ptr_value; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) + if (reset) begin + enq_ptr_value <= 2'h0; + deq_ptr_value <= 2'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + enq_ptr_value <= (enq_ptr_value == 2'h2 ? 2'h0 : enq_ptr_value + 2'h1); + if (do_deq) + deq_ptr_value <= (deq_ptr_value == 2'h2 ? 2'h0 : deq_ptr_value + 2'h1); + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + ram_3x137 ram_ext( + .R0_addr(deq_ptr_value), + .R0_en(1'h1), + .R0_clk(clock), + .R0_data(_ram_ext_R0_data), + .W0_addr(enq_ptr_value), + .W0_en(do_enq), + .W0_clk(clock), + .W0_data({io_enq_bits_data, io_enq_bits_id, io_enq_bits_resp, io_enq_bits_last}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[136:9]; + assign io_deq_bits_id = _ram_ext_R0_data[8:3]; + assign io_deq_bits_resp = _ram_ext_R0_data[2:1]; + assign io_deq_bits_last = _ram_ext_R0_data[0]; + assign io_count = (ptr_match ? {2 {maybe_full}} : (deq_ptr_value > enq_ptr_value ? _ptr_diff_T - 2'h1 : _ptr_diff_T)); +endmodule +module AxiSlave ( + clock, + reset, + io_axi_write_addr_ready, + io_axi_write_addr_valid, + io_axi_write_addr_bits_addr, + io_axi_write_addr_bits_prot, + io_axi_write_addr_bits_id, + io_axi_write_addr_bits_len, + io_axi_write_addr_bits_size, + io_axi_write_addr_bits_burst, + io_axi_write_addr_bits_lock, + io_axi_write_addr_bits_cache, + io_axi_write_addr_bits_qos, + io_axi_write_addr_bits_region, + io_axi_write_data_ready, + io_axi_write_data_valid, + io_axi_write_data_bits_data, + io_axi_write_data_bits_last, + io_axi_write_data_bits_strb, + io_axi_write_resp_ready, + io_axi_write_resp_valid, + io_axi_write_resp_bits_id, + io_axi_write_resp_bits_resp, + io_axi_read_addr_ready, + io_axi_read_addr_valid, + io_axi_read_addr_bits_addr, + io_axi_read_addr_bits_prot, + io_axi_read_addr_bits_id, + io_axi_read_addr_bits_len, + io_axi_read_addr_bits_size, + io_axi_read_addr_bits_burst, + io_axi_read_addr_bits_lock, + io_axi_read_addr_bits_cache, + io_axi_read_addr_bits_qos, + io_axi_read_addr_bits_region, + io_axi_read_data_ready, + io_axi_read_data_valid, + io_axi_read_data_bits_data, + io_axi_read_data_bits_id, + io_axi_read_data_bits_resp, + io_axi_read_data_bits_last, + io_fabric_readDataAddr_valid, + io_fabric_readDataAddr_bits, + io_fabric_readData_valid, + io_fabric_readData_bits, + io_fabric_writeDataAddr_valid, + io_fabric_writeDataAddr_bits, + io_fabric_writeDataBits, + io_fabric_writeDataStrb, + io_fabric_writeResp, + io_periBusy +); + input clock; + input reset; + output wire io_axi_write_addr_ready; + input io_axi_write_addr_valid; + input [31:0] io_axi_write_addr_bits_addr; + input [2:0] io_axi_write_addr_bits_prot; + input [5:0] io_axi_write_addr_bits_id; + input [7:0] io_axi_write_addr_bits_len; + input [2:0] io_axi_write_addr_bits_size; + input [1:0] io_axi_write_addr_bits_burst; + input io_axi_write_addr_bits_lock; + input [3:0] io_axi_write_addr_bits_cache; + input [3:0] io_axi_write_addr_bits_qos; + input [3:0] io_axi_write_addr_bits_region; + output wire io_axi_write_data_ready; + input io_axi_write_data_valid; + input [127:0] io_axi_write_data_bits_data; + input io_axi_write_data_bits_last; + input [15:0] io_axi_write_data_bits_strb; + input io_axi_write_resp_ready; + output wire io_axi_write_resp_valid; + output wire [5:0] io_axi_write_resp_bits_id; + output wire [1:0] io_axi_write_resp_bits_resp; + output wire io_axi_read_addr_ready; + input io_axi_read_addr_valid; + input [31:0] io_axi_read_addr_bits_addr; + input [2:0] io_axi_read_addr_bits_prot; + input [5:0] io_axi_read_addr_bits_id; + input [7:0] io_axi_read_addr_bits_len; + input [2:0] io_axi_read_addr_bits_size; + input [1:0] io_axi_read_addr_bits_burst; + input io_axi_read_addr_bits_lock; + input [3:0] io_axi_read_addr_bits_cache; + input [3:0] io_axi_read_addr_bits_qos; + input [3:0] io_axi_read_addr_bits_region; + input io_axi_read_data_ready; + output wire io_axi_read_data_valid; + output wire [127:0] io_axi_read_data_bits_data; + output wire [5:0] io_axi_read_data_bits_id; + output wire [1:0] io_axi_read_data_bits_resp; + output wire io_axi_read_data_bits_last; + output wire io_fabric_readDataAddr_valid; + output wire [31:0] io_fabric_readDataAddr_bits; + input io_fabric_readData_valid; + input [127:0] io_fabric_readData_bits; + output wire io_fabric_writeDataAddr_valid; + output wire [31:0] io_fabric_writeDataAddr_bits; + output wire [127:0] io_fabric_writeDataBits; + output wire [15:0] io_fabric_writeDataStrb; + input io_fabric_writeResp; + input io_periBusy; + wire _readDataQueue_io_enq_ready; + wire [1:0] _readDataQueue_io_count; + wire _io_axi_write_resp_q_io_enq_ready; + wire _writeData_q_io_deq_valid; + wire _writeData_q_io_deq_bits_last; + wire _axiAddrCmd_q_io_enq_ready; + wire _axiAddrCmd_q_io_deq_valid; + wire [31:0] _axiAddrCmd_q_io_deq_bits_addr_addr; + wire [5:0] _axiAddrCmd_q_io_deq_bits_addr_id; + wire [7:0] _axiAddrCmd_q_io_deq_bits_addr_len; + wire [2:0] _axiAddrCmd_q_io_deq_bits_addr_size; + wire [1:0] _axiAddrCmd_q_io_deq_bits_addr_burst; + wire _axiAddrCmd_q_io_deq_bits_write; + wire _addrArbiter_io_in_1_q_io_deq_valid; + wire [31:0] _addrArbiter_io_in_1_q_io_deq_bits_addr; + wire [2:0] _addrArbiter_io_in_1_q_io_deq_bits_prot; + wire [5:0] _addrArbiter_io_in_1_q_io_deq_bits_id; + wire [7:0] _addrArbiter_io_in_1_q_io_deq_bits_len; + wire [2:0] _addrArbiter_io_in_1_q_io_deq_bits_size; + wire [1:0] _addrArbiter_io_in_1_q_io_deq_bits_burst; + wire _addrArbiter_io_in_1_q_io_deq_bits_lock; + wire [3:0] _addrArbiter_io_in_1_q_io_deq_bits_cache; + wire [3:0] _addrArbiter_io_in_1_q_io_deq_bits_qos; + wire [3:0] _addrArbiter_io_in_1_q_io_deq_bits_region; + wire _addrArbiter_io_in_0_q_io_deq_valid; + wire [31:0] _addrArbiter_io_in_0_q_io_deq_bits_addr; + wire [2:0] _addrArbiter_io_in_0_q_io_deq_bits_prot; + wire [5:0] _addrArbiter_io_in_0_q_io_deq_bits_id; + wire [7:0] _addrArbiter_io_in_0_q_io_deq_bits_len; + wire [2:0] _addrArbiter_io_in_0_q_io_deq_bits_size; + wire [1:0] _addrArbiter_io_in_0_q_io_deq_bits_burst; + wire _addrArbiter_io_in_0_q_io_deq_bits_lock; + wire [3:0] _addrArbiter_io_in_0_q_io_deq_bits_cache; + wire [3:0] _addrArbiter_io_in_0_q_io_deq_bits_qos; + wire [3:0] _addrArbiter_io_in_0_q_io_deq_bits_region; + wire _addrArbiter_io_in_0_ready; + wire _addrArbiter_io_in_1_ready; + wire _addrArbiter_io_out_valid; + wire [31:0] _addrArbiter_io_out_bits_addr; + wire [2:0] _addrArbiter_io_out_bits_prot; + wire [5:0] _addrArbiter_io_out_bits_id; + wire [7:0] _addrArbiter_io_out_bits_len; + wire [2:0] _addrArbiter_io_out_bits_size; + wire [1:0] _addrArbiter_io_out_bits_burst; + wire _addrArbiter_io_out_bits_lock; + wire [3:0] _addrArbiter_io_out_bits_cache; + wire [3:0] _addrArbiter_io_out_bits_qos; + wire [3:0] _addrArbiter_io_out_bits_region; + wire _addrArbiter_io_chosen; + wire writeActive = _axiAddrCmd_q_io_deq_valid & _axiAddrCmd_q_io_deq_bits_write; + wire readActive = _axiAddrCmd_q_io_deq_valid & ~_axiAddrCmd_q_io_deq_bits_write; + reg [31:0] cmdAddr; + wire maybeWriteData = (writeActive & _writeData_q_io_deq_valid) & _io_axi_write_resp_q_io_enq_ready; + wire writeData_q_io_deq_ready = maybeWriteData & ~io_periBusy; + wire writeResponse_valid = writeData_q_io_deq_ready & _writeData_q_io_deq_bits_last; + reg readIssued_valid; + reg [5:0] readIssued_bits_id; + reg readIssued_bits_last; + reg [8:0] readsIssued; + wire [1:0] _maybeIssueRead_T = 2'h3 - _readDataQueue_io_count; + wire maybeIssueRead = readActive & _maybeIssueRead_T[1]; + wire issueRead = maybeIssueRead & ~io_periBusy; + wire lastRead = readsIssued == {1'h0, _axiAddrCmd_q_io_deq_bits_addr_len}; + wire _addrNext_T = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h0; + wire _addrNext_T_2 = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h1; + wire _addrNext_T_7 = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h2; + wire validBurst = _axiAddrCmd_q_io_deq_valid & ((_addrNext_T | _addrNext_T_2) | _addrNext_T_7); + wire _addrNext_T_1 = validBurst & _addrNext_T; + wire _addrNext_T_3 = validBurst & _addrNext_T_2; + wire _addrNext_T_8 = validBurst & _addrNext_T_7; + wire axiAddrCmd_q_io_deq_ready = (writeActive ? writeResponse_valid : (readActive & issueRead) & lastRead); + wire [31:0] cmdAddrBase = _axiAddrCmd_q_io_deq_bits_addr_addr & {25'h1ffffff, _axiAddrCmd_q_io_deq_bits_addr_size != 3'h7, _axiAddrCmd_q_io_deq_bits_addr_size[2:1] != 2'h3, _axiAddrCmd_q_io_deq_bits_addr_size < 3'h5, ~_axiAddrCmd_q_io_deq_bits_addr_size[2], _axiAddrCmd_q_io_deq_bits_addr_size < 3'h3, _axiAddrCmd_q_io_deq_bits_addr_size < 3'h2, _axiAddrCmd_q_io_deq_bits_addr_size == 3'h0}; + wire [31:0] _GEN = {24'h000000, 8'h01 << _axiAddrCmd_q_io_deq_bits_addr_size}; + wire [31:0] _addrNext_newAddr_T_1 = cmdAddr + _GEN; + always @(posedge clock or posedge reset) + if (reset) begin + cmdAddr <= 32'h00000000; + readIssued_valid <= 1'h0; + readIssued_bits_id <= 6'h00; + readIssued_bits_last <= 1'h0; + readsIssued <= 9'h000; + end + else begin + if (_axiAddrCmd_q_io_enq_ready & _addrArbiter_io_out_valid) + cmdAddr <= _addrArbiter_io_out_bits_addr; + else if ((maybeWriteData & ~io_periBusy) | (maybeIssueRead & ~io_periBusy)) + cmdAddr <= (((_addrNext_T_1 ? cmdAddr : 32'h00000000) | (_addrNext_T_3 ? cmdAddr + _GEN : 32'h00000000)) | (_addrNext_T_8 ? (_addrNext_newAddr_T_1 >= (cmdAddrBase + 32'h00000010) ? cmdAddrBase : _addrNext_newAddr_T_1) : 32'h00000000)) | ((_addrNext_T_1 | _addrNext_T_3) | _addrNext_T_8 ? 32'h00000000 : cmdAddr); + readIssued_valid <= issueRead; + readIssued_bits_id <= _axiAddrCmd_q_io_deq_bits_addr_id; + readIssued_bits_last <= lastRead; + readsIssued <= (axiAddrCmd_q_io_deq_ready & _axiAddrCmd_q_io_deq_valid ? 9'h000 : readsIssued + {8'h00, issueRead}); + end + CoralNPURRArbiter addrArbiter( + .clock(clock), + .reset(reset), + .io_in_0_ready(_addrArbiter_io_in_0_ready), + .io_in_0_valid(_addrArbiter_io_in_0_q_io_deq_valid), + .io_in_0_bits_addr(_addrArbiter_io_in_0_q_io_deq_bits_addr), + .io_in_0_bits_prot(_addrArbiter_io_in_0_q_io_deq_bits_prot), + .io_in_0_bits_id(_addrArbiter_io_in_0_q_io_deq_bits_id), + .io_in_0_bits_len(_addrArbiter_io_in_0_q_io_deq_bits_len), + .io_in_0_bits_size(_addrArbiter_io_in_0_q_io_deq_bits_size), + .io_in_0_bits_burst(_addrArbiter_io_in_0_q_io_deq_bits_burst), + .io_in_0_bits_lock(_addrArbiter_io_in_0_q_io_deq_bits_lock), + .io_in_0_bits_cache(_addrArbiter_io_in_0_q_io_deq_bits_cache), + .io_in_0_bits_qos(_addrArbiter_io_in_0_q_io_deq_bits_qos), + .io_in_0_bits_region(_addrArbiter_io_in_0_q_io_deq_bits_region), + .io_in_1_ready(_addrArbiter_io_in_1_ready), + .io_in_1_valid(_addrArbiter_io_in_1_q_io_deq_valid), + .io_in_1_bits_addr(_addrArbiter_io_in_1_q_io_deq_bits_addr), + .io_in_1_bits_prot(_addrArbiter_io_in_1_q_io_deq_bits_prot), + .io_in_1_bits_id(_addrArbiter_io_in_1_q_io_deq_bits_id), + .io_in_1_bits_len(_addrArbiter_io_in_1_q_io_deq_bits_len), + .io_in_1_bits_size(_addrArbiter_io_in_1_q_io_deq_bits_size), + .io_in_1_bits_burst(_addrArbiter_io_in_1_q_io_deq_bits_burst), + .io_in_1_bits_lock(_addrArbiter_io_in_1_q_io_deq_bits_lock), + .io_in_1_bits_cache(_addrArbiter_io_in_1_q_io_deq_bits_cache), + .io_in_1_bits_qos(_addrArbiter_io_in_1_q_io_deq_bits_qos), + .io_in_1_bits_region(_addrArbiter_io_in_1_q_io_deq_bits_region), + .io_out_ready(_axiAddrCmd_q_io_enq_ready), + .io_out_valid(_addrArbiter_io_out_valid), + .io_out_bits_addr(_addrArbiter_io_out_bits_addr), + .io_out_bits_prot(_addrArbiter_io_out_bits_prot), + .io_out_bits_id(_addrArbiter_io_out_bits_id), + .io_out_bits_len(_addrArbiter_io_out_bits_len), + .io_out_bits_size(_addrArbiter_io_out_bits_size), + .io_out_bits_burst(_addrArbiter_io_out_bits_burst), + .io_out_bits_lock(_addrArbiter_io_out_bits_lock), + .io_out_bits_cache(_addrArbiter_io_out_bits_cache), + .io_out_bits_qos(_addrArbiter_io_out_bits_qos), + .io_out_bits_region(_addrArbiter_io_out_bits_region), + .io_chosen(_addrArbiter_io_chosen) + ); + Queue2_AxiAddress addrArbiter_io_in_0_q( + .clock(clock), + .reset(reset), + .io_enq_ready(io_axi_read_addr_ready), + .io_enq_valid(io_axi_read_addr_valid), + .io_enq_bits_addr(io_axi_read_addr_bits_addr), + .io_enq_bits_prot(io_axi_read_addr_bits_prot), + .io_enq_bits_id(io_axi_read_addr_bits_id), + .io_enq_bits_len(io_axi_read_addr_bits_len), + .io_enq_bits_size(io_axi_read_addr_bits_size), + .io_enq_bits_burst(io_axi_read_addr_bits_burst), + .io_enq_bits_lock(io_axi_read_addr_bits_lock), + .io_enq_bits_cache(io_axi_read_addr_bits_cache), + .io_enq_bits_qos(io_axi_read_addr_bits_qos), + .io_enq_bits_region(io_axi_read_addr_bits_region), + .io_deq_ready(_addrArbiter_io_in_0_ready), + .io_deq_valid(_addrArbiter_io_in_0_q_io_deq_valid), + .io_deq_bits_addr(_addrArbiter_io_in_0_q_io_deq_bits_addr), + .io_deq_bits_prot(_addrArbiter_io_in_0_q_io_deq_bits_prot), + .io_deq_bits_id(_addrArbiter_io_in_0_q_io_deq_bits_id), + .io_deq_bits_len(_addrArbiter_io_in_0_q_io_deq_bits_len), + .io_deq_bits_size(_addrArbiter_io_in_0_q_io_deq_bits_size), + .io_deq_bits_burst(_addrArbiter_io_in_0_q_io_deq_bits_burst), + .io_deq_bits_lock(_addrArbiter_io_in_0_q_io_deq_bits_lock), + .io_deq_bits_cache(_addrArbiter_io_in_0_q_io_deq_bits_cache), + .io_deq_bits_qos(_addrArbiter_io_in_0_q_io_deq_bits_qos), + .io_deq_bits_region(_addrArbiter_io_in_0_q_io_deq_bits_region) + ); + Queue2_AxiAddress addrArbiter_io_in_1_q( + .clock(clock), + .reset(reset), + .io_enq_ready(io_axi_write_addr_ready), + .io_enq_valid(io_axi_write_addr_valid), + .io_enq_bits_addr(io_axi_write_addr_bits_addr), + .io_enq_bits_prot(io_axi_write_addr_bits_prot), + .io_enq_bits_id(io_axi_write_addr_bits_id), + .io_enq_bits_len(io_axi_write_addr_bits_len), + .io_enq_bits_size(io_axi_write_addr_bits_size), + .io_enq_bits_burst(io_axi_write_addr_bits_burst), + .io_enq_bits_lock(io_axi_write_addr_bits_lock), + .io_enq_bits_cache(io_axi_write_addr_bits_cache), + .io_enq_bits_qos(io_axi_write_addr_bits_qos), + .io_enq_bits_region(io_axi_write_addr_bits_region), + .io_deq_ready(_addrArbiter_io_in_1_ready), + .io_deq_valid(_addrArbiter_io_in_1_q_io_deq_valid), + .io_deq_bits_addr(_addrArbiter_io_in_1_q_io_deq_bits_addr), + .io_deq_bits_prot(_addrArbiter_io_in_1_q_io_deq_bits_prot), + .io_deq_bits_id(_addrArbiter_io_in_1_q_io_deq_bits_id), + .io_deq_bits_len(_addrArbiter_io_in_1_q_io_deq_bits_len), + .io_deq_bits_size(_addrArbiter_io_in_1_q_io_deq_bits_size), + .io_deq_bits_burst(_addrArbiter_io_in_1_q_io_deq_bits_burst), + .io_deq_bits_lock(_addrArbiter_io_in_1_q_io_deq_bits_lock), + .io_deq_bits_cache(_addrArbiter_io_in_1_q_io_deq_bits_cache), + .io_deq_bits_qos(_addrArbiter_io_in_1_q_io_deq_bits_qos), + .io_deq_bits_region(_addrArbiter_io_in_1_q_io_deq_bits_region) + ); + Queue1_RWAxiAddress axiAddrCmd_q( + .clock(clock), + .reset(reset), + .io_enq_ready(_axiAddrCmd_q_io_enq_ready), + .io_enq_valid(_addrArbiter_io_out_valid), + .io_enq_bits_addr_addr(_addrArbiter_io_out_bits_addr), + .io_enq_bits_addr_prot(_addrArbiter_io_out_bits_prot), + .io_enq_bits_addr_id(_addrArbiter_io_out_bits_id), + .io_enq_bits_addr_len(_addrArbiter_io_out_bits_len), + .io_enq_bits_addr_size(_addrArbiter_io_out_bits_size), + .io_enq_bits_addr_burst(_addrArbiter_io_out_bits_burst), + .io_enq_bits_addr_lock(_addrArbiter_io_out_bits_lock), + .io_enq_bits_addr_cache(_addrArbiter_io_out_bits_cache), + .io_enq_bits_addr_qos(_addrArbiter_io_out_bits_qos), + .io_enq_bits_addr_region(_addrArbiter_io_out_bits_region), + .io_enq_bits_write(_addrArbiter_io_chosen), + .io_deq_ready(axiAddrCmd_q_io_deq_ready), + .io_deq_valid(_axiAddrCmd_q_io_deq_valid), + .io_deq_bits_addr_addr(_axiAddrCmd_q_io_deq_bits_addr_addr), + .io_deq_bits_addr_id(_axiAddrCmd_q_io_deq_bits_addr_id), + .io_deq_bits_addr_len(_axiAddrCmd_q_io_deq_bits_addr_len), + .io_deq_bits_addr_size(_axiAddrCmd_q_io_deq_bits_addr_size), + .io_deq_bits_addr_burst(_axiAddrCmd_q_io_deq_bits_addr_burst), + .io_deq_bits_write(_axiAddrCmd_q_io_deq_bits_write) + ); + Queue3_AxiWriteData writeData_q( + .clock(clock), + .reset(reset), + .io_enq_ready(io_axi_write_data_ready), + .io_enq_valid(io_axi_write_data_valid), + .io_enq_bits_data(io_axi_write_data_bits_data), + .io_enq_bits_last(io_axi_write_data_bits_last), + .io_enq_bits_strb(io_axi_write_data_bits_strb), + .io_deq_ready(writeData_q_io_deq_ready), + .io_deq_valid(_writeData_q_io_deq_valid), + .io_deq_bits_data(io_fabric_writeDataBits), + .io_deq_bits_last(_writeData_q_io_deq_bits_last), + .io_deq_bits_strb(io_fabric_writeDataStrb) + ); + Queue2_AxiWriteResponse io_axi_write_resp_q( + .clock(clock), + .reset(reset), + .io_enq_ready(_io_axi_write_resp_q_io_enq_ready), + .io_enq_valid(writeResponse_valid), + .io_enq_bits_id(_axiAddrCmd_q_io_deq_bits_addr_id), + .io_enq_bits_resp({~io_fabric_writeResp, 1'h0}), + .io_deq_ready(io_axi_write_resp_ready), + .io_deq_valid(io_axi_write_resp_valid), + .io_deq_bits_id(io_axi_write_resp_bits_id), + .io_deq_bits_resp(io_axi_write_resp_bits_resp) + ); + Queue3_AxiReadData readDataQueue( + .clock(clock), + .reset(reset), + .io_enq_ready(_readDataQueue_io_enq_ready), + .io_enq_valid(readIssued_valid), + .io_enq_bits_data(io_fabric_readData_bits), + .io_enq_bits_id(readIssued_bits_id), + .io_enq_bits_resp({~io_fabric_readData_valid, 1'h0}), + .io_enq_bits_last(readIssued_bits_last), + .io_deq_ready(io_axi_read_data_ready), + .io_deq_valid(io_axi_read_data_valid), + .io_deq_bits_data(io_axi_read_data_bits_data), + .io_deq_bits_id(io_axi_read_data_bits_id), + .io_deq_bits_resp(io_axi_read_data_bits_resp), + .io_deq_bits_last(io_axi_read_data_bits_last), + .io_count(_readDataQueue_io_count) + ); + assign io_fabric_readDataAddr_valid = maybeIssueRead; + assign io_fabric_readDataAddr_bits = cmdAddr; + assign io_fabric_writeDataAddr_valid = maybeWriteData; + assign io_fabric_writeDataAddr_bits = cmdAddr; +endmodule +module ram_2x145 ( + R0_addr, + R0_en, + R0_clk, + R0_data, + W0_addr, + W0_en, + W0_clk, + W0_data +); + input R0_addr; + input R0_en; + input R0_clk; + output wire [144:0] R0_data; + input W0_addr; + input W0_en; + input W0_clk; + input [144:0] W0_data; + reg [144:0] Memory [0:1]; + always @(posedge W0_clk) + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + assign R0_data = (R0_en ? Memory[R0_addr] : 145'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); +endmodule +module Queue2_AxiWriteData ( + clock, + reset, + io_enq_ready, + io_enq_valid, + io_enq_bits_data, + io_enq_bits_strb, + io_deq_ready, + io_deq_valid, + io_deq_bits_data, + io_deq_bits_last, + io_deq_bits_strb +); + input clock; + input reset; + output wire io_enq_ready; + input io_enq_valid; + input [127:0] io_enq_bits_data; + input [15:0] io_enq_bits_strb; + input io_deq_ready; + output wire io_deq_valid; + output wire [127:0] io_deq_bits_data; + output wire io_deq_bits_last; + output wire [15:0] io_deq_bits_strb; + wire [144:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + ram_2x145 ram_ext( + .R0_addr(wrap_1), + .R0_en(1'h1), + .R0_clk(clock), + .R0_data(_ram_ext_R0_data), + .W0_addr(wrap), + .W0_en(do_enq), + .W0_clk(clock), + .W0_data({io_enq_bits_data, 1'h1, io_enq_bits_strb}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[144:17]; + assign io_deq_bits_last = _ram_ext_R0_data[16]; + assign io_deq_bits_strb = _ram_ext_R0_data[15:0]; +endmodule +module DBus2AxiV2 ( + clock, + reset, + io_dbus_valid, + io_dbus_ready, + io_dbus_write, + io_dbus_pc, + io_dbus_addr, + io_dbus_size, + io_dbus_wdata, + io_dbus_wmask, + io_dbus_rdata, + io_axi_write_addr_ready, + io_axi_write_addr_valid, + io_axi_write_addr_bits_addr, + io_axi_write_addr_bits_size, + io_axi_write_data_ready, + io_axi_write_data_valid, + io_axi_write_data_bits_data, + io_axi_write_data_bits_last, + io_axi_write_data_bits_strb, + io_axi_write_resp_ready, + io_axi_write_resp_valid, + io_axi_write_resp_bits_resp, + io_axi_read_addr_ready, + io_axi_read_addr_valid, + io_axi_read_addr_bits_addr, + io_axi_read_addr_bits_size, + io_axi_read_data_ready, + io_axi_read_data_valid, + io_axi_read_data_bits_data, + io_axi_read_data_bits_resp, + io_fault_valid, + io_fault_bits_write, + io_fault_bits_addr, + io_fault_bits_epc +); + input clock; + input reset; + input io_dbus_valid; + output wire io_dbus_ready; + input io_dbus_write; + input [31:0] io_dbus_pc; + input [31:0] io_dbus_addr; + input [4:0] io_dbus_size; + input [127:0] io_dbus_wdata; + input [15:0] io_dbus_wmask; + output wire [127:0] io_dbus_rdata; + input io_axi_write_addr_ready; + output wire io_axi_write_addr_valid; + output wire [31:0] io_axi_write_addr_bits_addr; + output wire [2:0] io_axi_write_addr_bits_size; + input io_axi_write_data_ready; + output wire io_axi_write_data_valid; + output wire [127:0] io_axi_write_data_bits_data; + output wire io_axi_write_data_bits_last; + output wire [15:0] io_axi_write_data_bits_strb; + output wire io_axi_write_resp_ready; + input io_axi_write_resp_valid; + input [1:0] io_axi_write_resp_bits_resp; + input io_axi_read_addr_ready; + output wire io_axi_read_addr_valid; + output wire [31:0] io_axi_read_addr_bits_addr; + output wire [2:0] io_axi_read_addr_bits_size; + output wire io_axi_read_data_ready; + input io_axi_read_data_valid; + input [127:0] io_axi_read_data_bits_data; + input [1:0] io_axi_read_data_bits_resp; + output wire io_fault_valid; + output wire io_fault_bits_write; + output wire [31:0] io_fault_bits_addr; + output wire [31:0] io_fault_bits_epc; + wire _wdataQueue_io_enq_ready; + reg waddrFired; + wire io_axi_write_addr_valid_0 = (~waddrFired & io_dbus_valid) & io_dbus_write; + reg wdataFired; + wire wdataQueue_io_enq_valid = (~wdataFired & io_dbus_valid) & io_dbus_write; + reg wrespReceived; + wire io_axi_write_resp_ready_0 = (~wrespReceived & io_dbus_valid) & io_dbus_write; + wire _waddrFired_T = io_axi_write_addr_ready & io_axi_write_addr_valid_0; + wire _wdataFired_T = _wdataQueue_io_enq_ready & wdataQueue_io_enq_valid; + wire _wrespReceived_T = io_axi_write_resp_ready_0 & io_axi_write_resp_valid; + wire writeFinished = ((_waddrFired_T | waddrFired) & (_wdataFired_T | wdataFired)) & (_wrespReceived_T | wrespReceived); + reg raddrFired; + wire io_axi_read_addr_valid_0 = (~raddrFired & io_dbus_valid) & ~io_dbus_write; + reg rdataReceived_valid; + reg [127:0] rdataReceived_bits; + wire io_axi_read_data_ready_0 = (~rdataReceived_valid & io_dbus_valid) & ~io_dbus_write; + wire _raddrFired_T = io_axi_read_addr_ready & io_axi_read_addr_valid_0; + wire _readNext_T = io_axi_read_data_ready_0 & io_axi_read_data_valid; + wire readFinished = (_raddrFired_T | raddrFired) & (_readNext_T | rdataReceived_valid); + reg [127:0] readNext; + always @(posedge clock or posedge reset) + if (reset) begin + waddrFired <= 1'h0; + wdataFired <= 1'h0; + wrespReceived <= 1'h0; + raddrFired <= 1'h0; + rdataReceived_valid <= 1'h0; + rdataReceived_bits <= 128'h00000000000000000000000000000000; + readNext <= 128'h00000000000000000000000000000000; + end + else begin + waddrFired <= ~writeFinished & (_waddrFired_T | waddrFired); + wdataFired <= ~writeFinished & (_wdataFired_T | wdataFired); + wrespReceived <= ~writeFinished & (_wrespReceived_T | wrespReceived); + raddrFired <= ~readFinished & (_raddrFired_T | raddrFired); + rdataReceived_valid <= ~readFinished & (_readNext_T | rdataReceived_valid); + if (readFinished) begin + rdataReceived_bits <= 128'h00000000000000000000000000000000; + readNext <= (_readNext_T ? io_axi_read_data_bits_data : rdataReceived_bits); + end + else if (_readNext_T) + rdataReceived_bits <= io_axi_read_data_bits_data; + end + Queue2_AxiWriteData wdataQueue( + .clock(clock), + .reset(reset), + .io_enq_ready(_wdataQueue_io_enq_ready), + .io_enq_valid(wdataQueue_io_enq_valid), + .io_enq_bits_data(io_dbus_wdata), + .io_enq_bits_strb(io_dbus_wmask), + .io_deq_ready(io_axi_write_data_ready), + .io_deq_valid(io_axi_write_data_valid), + .io_deq_bits_data(io_axi_write_data_bits_data), + .io_deq_bits_last(io_axi_write_data_bits_last), + .io_deq_bits_strb(io_axi_write_data_bits_strb) + ); + assign io_dbus_ready = (io_dbus_write ? writeFinished : readFinished); + assign io_dbus_rdata = readNext; + assign io_axi_write_addr_valid = io_axi_write_addr_valid_0; + assign io_axi_write_addr_bits_addr = io_dbus_addr; + assign io_axi_write_addr_bits_size = (io_dbus_size[0] ? 3'h0 : (io_dbus_size[1] ? 3'h1 : (io_dbus_size[2] ? 3'h2 : (io_dbus_size[3] ? 3'h3 : {2'h2, ~io_dbus_size[4]})))); + assign io_axi_write_resp_ready = io_axi_write_resp_ready_0; + assign io_axi_read_addr_valid = io_axi_read_addr_valid_0; + assign io_axi_read_addr_bits_addr = io_dbus_addr; + assign io_axi_read_addr_bits_size = (io_dbus_size[0] ? 3'h0 : (io_dbus_size[1] ? 3'h1 : (io_dbus_size[2] ? 3'h2 : (io_dbus_size[3] ? 3'h3 : {2'h2, ~io_dbus_size[4]})))); + assign io_axi_read_data_ready = io_axi_read_data_ready_0; + assign io_fault_valid = io_dbus_valid & (io_dbus_write ? io_axi_write_resp_valid & |io_axi_write_resp_bits_resp : io_axi_read_data_valid & |io_axi_read_data_bits_resp); + assign io_fault_bits_write = io_dbus_write; + assign io_fault_bits_addr = io_dbus_addr; + assign io_fault_bits_epc = io_dbus_pc; +endmodule +module CoreMiniAxi ( + io_aclk, + io_aresetn, + io_axi_slave_write_addr_ready, + io_axi_slave_write_addr_valid, + io_axi_slave_write_addr_bits_addr, + io_axi_slave_write_addr_bits_prot, + io_axi_slave_write_addr_bits_id, + io_axi_slave_write_addr_bits_len, + io_axi_slave_write_addr_bits_size, + io_axi_slave_write_addr_bits_burst, + io_axi_slave_write_addr_bits_lock, + io_axi_slave_write_addr_bits_cache, + io_axi_slave_write_addr_bits_qos, + io_axi_slave_write_addr_bits_region, + io_axi_slave_write_data_ready, + io_axi_slave_write_data_valid, + io_axi_slave_write_data_bits_data, + io_axi_slave_write_data_bits_last, + io_axi_slave_write_data_bits_strb, + io_axi_slave_write_resp_ready, + io_axi_slave_write_resp_valid, + io_axi_slave_write_resp_bits_id, + io_axi_slave_write_resp_bits_resp, + io_axi_slave_read_addr_ready, + io_axi_slave_read_addr_valid, + io_axi_slave_read_addr_bits_addr, + io_axi_slave_read_addr_bits_prot, + io_axi_slave_read_addr_bits_id, + io_axi_slave_read_addr_bits_len, + io_axi_slave_read_addr_bits_size, + io_axi_slave_read_addr_bits_burst, + io_axi_slave_read_addr_bits_lock, + io_axi_slave_read_addr_bits_cache, + io_axi_slave_read_addr_bits_qos, + io_axi_slave_read_addr_bits_region, + io_axi_slave_read_data_ready, + io_axi_slave_read_data_valid, + io_axi_slave_read_data_bits_data, + io_axi_slave_read_data_bits_id, + io_axi_slave_read_data_bits_resp, + io_axi_slave_read_data_bits_last, + io_axi_master_write_addr_ready, + io_axi_master_write_addr_valid, + io_axi_master_write_addr_bits_addr, + io_axi_master_write_addr_bits_prot, + io_axi_master_write_addr_bits_id, + io_axi_master_write_addr_bits_len, + io_axi_master_write_addr_bits_size, + io_axi_master_write_addr_bits_burst, + io_axi_master_write_addr_bits_lock, + io_axi_master_write_addr_bits_cache, + io_axi_master_write_addr_bits_qos, + io_axi_master_write_addr_bits_region, + io_axi_master_write_data_ready, + io_axi_master_write_data_valid, + io_axi_master_write_data_bits_data, + io_axi_master_write_data_bits_last, + io_axi_master_write_data_bits_strb, + io_axi_master_write_resp_ready, + io_axi_master_write_resp_valid, + io_axi_master_write_resp_bits_id, + io_axi_master_write_resp_bits_resp, + io_axi_master_read_addr_ready, + io_axi_master_read_addr_valid, + io_axi_master_read_addr_bits_addr, + io_axi_master_read_addr_bits_prot, + io_axi_master_read_addr_bits_id, + io_axi_master_read_addr_bits_len, + io_axi_master_read_addr_bits_size, + io_axi_master_read_addr_bits_burst, + io_axi_master_read_addr_bits_lock, + io_axi_master_read_addr_bits_cache, + io_axi_master_read_addr_bits_qos, + io_axi_master_read_addr_bits_region, + io_axi_master_read_data_ready, + io_axi_master_read_data_valid, + io_axi_master_read_data_bits_data, + io_axi_master_read_data_bits_id, + io_axi_master_read_data_bits_resp, + io_axi_master_read_data_bits_last, + io_halted, + io_fault, + io_wfi, + io_irq, + io_te +); + input io_aclk; + input io_aresetn; + output wire io_axi_slave_write_addr_ready; + input io_axi_slave_write_addr_valid; + input [31:0] io_axi_slave_write_addr_bits_addr; + input [2:0] io_axi_slave_write_addr_bits_prot; + input [5:0] io_axi_slave_write_addr_bits_id; + input [7:0] io_axi_slave_write_addr_bits_len; + input [2:0] io_axi_slave_write_addr_bits_size; + input [1:0] io_axi_slave_write_addr_bits_burst; + input io_axi_slave_write_addr_bits_lock; + input [3:0] io_axi_slave_write_addr_bits_cache; + input [3:0] io_axi_slave_write_addr_bits_qos; + input [3:0] io_axi_slave_write_addr_bits_region; + output wire io_axi_slave_write_data_ready; + input io_axi_slave_write_data_valid; + input [127:0] io_axi_slave_write_data_bits_data; + input io_axi_slave_write_data_bits_last; + input [15:0] io_axi_slave_write_data_bits_strb; + input io_axi_slave_write_resp_ready; + output wire io_axi_slave_write_resp_valid; + output wire [5:0] io_axi_slave_write_resp_bits_id; + output wire [1:0] io_axi_slave_write_resp_bits_resp; + output wire io_axi_slave_read_addr_ready; + input io_axi_slave_read_addr_valid; + input [31:0] io_axi_slave_read_addr_bits_addr; + input [2:0] io_axi_slave_read_addr_bits_prot; + input [5:0] io_axi_slave_read_addr_bits_id; + input [7:0] io_axi_slave_read_addr_bits_len; + input [2:0] io_axi_slave_read_addr_bits_size; + input [1:0] io_axi_slave_read_addr_bits_burst; + input io_axi_slave_read_addr_bits_lock; + input [3:0] io_axi_slave_read_addr_bits_cache; + input [3:0] io_axi_slave_read_addr_bits_qos; + input [3:0] io_axi_slave_read_addr_bits_region; + input io_axi_slave_read_data_ready; + output wire io_axi_slave_read_data_valid; + output wire [127:0] io_axi_slave_read_data_bits_data; + output wire [5:0] io_axi_slave_read_data_bits_id; + output wire [1:0] io_axi_slave_read_data_bits_resp; + output wire io_axi_slave_read_data_bits_last; + input io_axi_master_write_addr_ready; + output wire io_axi_master_write_addr_valid; + output wire [31:0] io_axi_master_write_addr_bits_addr; + output wire [2:0] io_axi_master_write_addr_bits_prot; + output wire [5:0] io_axi_master_write_addr_bits_id; + output wire [7:0] io_axi_master_write_addr_bits_len; + output wire [2:0] io_axi_master_write_addr_bits_size; + output wire [1:0] io_axi_master_write_addr_bits_burst; + output wire io_axi_master_write_addr_bits_lock; + output wire [3:0] io_axi_master_write_addr_bits_cache; + output wire [3:0] io_axi_master_write_addr_bits_qos; + output wire [3:0] io_axi_master_write_addr_bits_region; + input io_axi_master_write_data_ready; + output wire io_axi_master_write_data_valid; + output wire [127:0] io_axi_master_write_data_bits_data; + output wire io_axi_master_write_data_bits_last; + output wire [15:0] io_axi_master_write_data_bits_strb; + output wire io_axi_master_write_resp_ready; + input io_axi_master_write_resp_valid; + input [5:0] io_axi_master_write_resp_bits_id; + input [1:0] io_axi_master_write_resp_bits_resp; + input io_axi_master_read_addr_ready; + output wire io_axi_master_read_addr_valid; + output wire [31:0] io_axi_master_read_addr_bits_addr; + output wire [2:0] io_axi_master_read_addr_bits_prot; + output wire [5:0] io_axi_master_read_addr_bits_id; + output wire [7:0] io_axi_master_read_addr_bits_len; + output wire [2:0] io_axi_master_read_addr_bits_size; + output wire [1:0] io_axi_master_read_addr_bits_burst; + output wire io_axi_master_read_addr_bits_lock; + output wire [3:0] io_axi_master_read_addr_bits_cache; + output wire [3:0] io_axi_master_read_addr_bits_qos; + output wire [3:0] io_axi_master_read_addr_bits_region; + output wire io_axi_master_read_data_ready; + input io_axi_master_read_data_valid; + input [127:0] io_axi_master_read_data_bits_data; + input [5:0] io_axi_master_read_data_bits_id; + input [1:0] io_axi_master_read_data_bits_resp; + input io_axi_master_read_data_bits_last; + output wire io_halted; + output wire io_fault; + output wire io_wfi; + input io_irq; + input io_te; + wire _ebus2axi_io_dbus_ready; + wire [127:0] _ebus2axi_io_dbus_rdata; + wire _ebus2axi_io_fault_valid; + wire _ebus2axi_io_fault_bits_write; + wire [31:0] _ebus2axi_io_fault_bits_addr; + wire [31:0] _ebus2axi_io_fault_bits_epc; + wire _axiSlave_io_axi_write_addr_ready; + wire _axiSlave_io_axi_write_data_ready; + wire _axiSlave_io_axi_write_resp_valid; + wire _axiSlave_io_axi_read_addr_ready; + wire _axiSlave_io_axi_read_data_valid; + wire _axiSlave_io_fabric_readDataAddr_valid; + wire [31:0] _axiSlave_io_fabric_readDataAddr_bits; + wire _axiSlave_io_fabric_writeDataAddr_valid; + wire [31:0] _axiSlave_io_fabric_writeDataAddr_bits; + wire [127:0] _axiSlave_io_fabric_writeDataBits; + wire [15:0] _axiSlave_io_fabric_writeDataStrb; + wire _fabricMux_io_source_readData_valid; + wire [127:0] _fabricMux_io_source_readData_bits; + wire _fabricMux_io_source_writeResp; + wire _fabricMux_io_fabricBusy; + wire _fabricMux_io_ports_0_readDataAddr_valid; + wire [31:0] _fabricMux_io_ports_0_readDataAddr_bits; + wire _fabricMux_io_ports_0_writeDataAddr_valid; + wire [31:0] _fabricMux_io_ports_0_writeDataAddr_bits; + wire [127:0] _fabricMux_io_ports_0_writeDataBits; + wire [15:0] _fabricMux_io_ports_0_writeDataStrb; + wire _fabricMux_io_ports_1_readDataAddr_valid; + wire [31:0] _fabricMux_io_ports_1_readDataAddr_bits; + wire _fabricMux_io_ports_1_writeDataAddr_valid; + wire [31:0] _fabricMux_io_ports_1_writeDataAddr_bits; + wire [127:0] _fabricMux_io_ports_1_writeDataBits; + wire [15:0] _fabricMux_io_ports_1_writeDataStrb; + wire [31:0] _fabricMux_io_ports_2_readDataAddr_bits; + wire _fabricMux_io_ports_2_writeDataAddr_valid; + wire [31:0] _fabricMux_io_ports_2_writeDataAddr_bits; + wire [127:0] _fabricMux_io_ports_2_writeDataBits; + wire [127:0] _dtcmArbiter_io_source_0_readData_bits; + wire _dtcmArbiter_io_source_1_readData_valid; + wire [127:0] _dtcmArbiter_io_source_1_readData_bits; + wire _dtcmArbiter_io_fabricBusy_1; + wire _dtcmArbiter_io_port_readDataAddr_valid; + wire [31:0] _dtcmArbiter_io_port_readDataAddr_bits; + wire _dtcmArbiter_io_port_writeDataAddr_valid; + wire [31:0] _dtcmArbiter_io_port_writeDataAddr_bits; + wire [127:0] _dtcmArbiter_io_port_writeDataBits; + wire [15:0] _dtcmArbiter_io_port_writeDataStrb; + wire _dtcmWrapper_io_fabric_readData_valid; + wire [127:0] _dtcmWrapper_io_fabric_readData_bits; + wire [10:0] _dtcmWrapper_io_sram_address; + wire _dtcmWrapper_io_sram_enable; + wire _dtcmWrapper_io_sram_isWrite; + wire [7:0] _dtcmWrapper_io_sram_writeData_0; + wire [7:0] _dtcmWrapper_io_sram_writeData_1; + wire [7:0] _dtcmWrapper_io_sram_writeData_2; + wire [7:0] _dtcmWrapper_io_sram_writeData_3; + wire [7:0] _dtcmWrapper_io_sram_writeData_4; + wire [7:0] _dtcmWrapper_io_sram_writeData_5; + wire [7:0] _dtcmWrapper_io_sram_writeData_6; + wire [7:0] _dtcmWrapper_io_sram_writeData_7; + wire [7:0] _dtcmWrapper_io_sram_writeData_8; + wire [7:0] _dtcmWrapper_io_sram_writeData_9; + wire [7:0] _dtcmWrapper_io_sram_writeData_10; + wire [7:0] _dtcmWrapper_io_sram_writeData_11; + wire [7:0] _dtcmWrapper_io_sram_writeData_12; + wire [7:0] _dtcmWrapper_io_sram_writeData_13; + wire [7:0] _dtcmWrapper_io_sram_writeData_14; + wire [7:0] _dtcmWrapper_io_sram_writeData_15; + wire _dtcmWrapper_io_sram_mask_0; + wire _dtcmWrapper_io_sram_mask_1; + wire _dtcmWrapper_io_sram_mask_2; + wire _dtcmWrapper_io_sram_mask_3; + wire _dtcmWrapper_io_sram_mask_4; + wire _dtcmWrapper_io_sram_mask_5; + wire _dtcmWrapper_io_sram_mask_6; + wire _dtcmWrapper_io_sram_mask_7; + wire _dtcmWrapper_io_sram_mask_8; + wire _dtcmWrapper_io_sram_mask_9; + wire _dtcmWrapper_io_sram_mask_10; + wire _dtcmWrapper_io_sram_mask_11; + wire _dtcmWrapper_io_sram_mask_12; + wire _dtcmWrapper_io_sram_mask_13; + wire _dtcmWrapper_io_sram_mask_14; + wire _dtcmWrapper_io_sram_mask_15; + wire [7:0] _dtcm_io_rdata_0; + wire [7:0] _dtcm_io_rdata_1; + wire [7:0] _dtcm_io_rdata_2; + wire [7:0] _dtcm_io_rdata_3; + wire [7:0] _dtcm_io_rdata_4; + wire [7:0] _dtcm_io_rdata_5; + wire [7:0] _dtcm_io_rdata_6; + wire [7:0] _dtcm_io_rdata_7; + wire [7:0] _dtcm_io_rdata_8; + wire [7:0] _dtcm_io_rdata_9; + wire [7:0] _dtcm_io_rdata_10; + wire [7:0] _dtcm_io_rdata_11; + wire [7:0] _dtcm_io_rdata_12; + wire [7:0] _dtcm_io_rdata_13; + wire [7:0] _dtcm_io_rdata_14; + wire [7:0] _dtcm_io_rdata_15; + wire [127:0] _itcmArbiter_io_source_0_readData_bits; + wire _itcmArbiter_io_source_1_readData_valid; + wire [127:0] _itcmArbiter_io_source_1_readData_bits; + wire _itcmArbiter_io_fabricBusy_1; + wire _itcmArbiter_io_port_readDataAddr_valid; + wire [31:0] _itcmArbiter_io_port_readDataAddr_bits; + wire _itcmArbiter_io_port_writeDataAddr_valid; + wire [31:0] _itcmArbiter_io_port_writeDataAddr_bits; + wire [127:0] _itcmArbiter_io_port_writeDataBits; + wire [15:0] _itcmArbiter_io_port_writeDataStrb; + wire _itcmWrapper_io_fabric_readData_valid; + wire [127:0] _itcmWrapper_io_fabric_readData_bits; + wire [8:0] _itcmWrapper_io_sram_address; + wire _itcmWrapper_io_sram_enable; + wire _itcmWrapper_io_sram_isWrite; + wire [7:0] _itcmWrapper_io_sram_writeData_0; + wire [7:0] _itcmWrapper_io_sram_writeData_1; + wire [7:0] _itcmWrapper_io_sram_writeData_2; + wire [7:0] _itcmWrapper_io_sram_writeData_3; + wire [7:0] _itcmWrapper_io_sram_writeData_4; + wire [7:0] _itcmWrapper_io_sram_writeData_5; + wire [7:0] _itcmWrapper_io_sram_writeData_6; + wire [7:0] _itcmWrapper_io_sram_writeData_7; + wire [7:0] _itcmWrapper_io_sram_writeData_8; + wire [7:0] _itcmWrapper_io_sram_writeData_9; + wire [7:0] _itcmWrapper_io_sram_writeData_10; + wire [7:0] _itcmWrapper_io_sram_writeData_11; + wire [7:0] _itcmWrapper_io_sram_writeData_12; + wire [7:0] _itcmWrapper_io_sram_writeData_13; + wire [7:0] _itcmWrapper_io_sram_writeData_14; + wire [7:0] _itcmWrapper_io_sram_writeData_15; + wire _itcmWrapper_io_sram_mask_0; + wire _itcmWrapper_io_sram_mask_1; + wire _itcmWrapper_io_sram_mask_2; + wire _itcmWrapper_io_sram_mask_3; + wire _itcmWrapper_io_sram_mask_4; + wire _itcmWrapper_io_sram_mask_5; + wire _itcmWrapper_io_sram_mask_6; + wire _itcmWrapper_io_sram_mask_7; + wire _itcmWrapper_io_sram_mask_8; + wire _itcmWrapper_io_sram_mask_9; + wire _itcmWrapper_io_sram_mask_10; + wire _itcmWrapper_io_sram_mask_11; + wire _itcmWrapper_io_sram_mask_12; + wire _itcmWrapper_io_sram_mask_13; + wire _itcmWrapper_io_sram_mask_14; + wire _itcmWrapper_io_sram_mask_15; + wire [7:0] _itcm_io_rdata_0; + wire [7:0] _itcm_io_rdata_1; + wire [7:0] _itcm_io_rdata_2; + wire [7:0] _itcm_io_rdata_3; + wire [7:0] _itcm_io_rdata_4; + wire [7:0] _itcm_io_rdata_5; + wire [7:0] _itcm_io_rdata_6; + wire [7:0] _itcm_io_rdata_7; + wire [7:0] _itcm_io_rdata_8; + wire [7:0] _itcm_io_rdata_9; + wire [7:0] _itcm_io_rdata_10; + wire [7:0] _itcm_io_rdata_11; + wire [7:0] _itcm_io_rdata_12; + wire [7:0] _itcm_io_rdata_13; + wire [7:0] _itcm_io_rdata_14; + wire [7:0] _itcm_io_rdata_15; + wire [31:0] _core_io_csr_out_value_0; + wire [31:0] _core_io_csr_out_value_1; + wire [31:0] _core_io_csr_out_value_2; + wire [31:0] _core_io_csr_out_value_3; + wire [31:0] _core_io_csr_out_value_4; + wire [31:0] _core_io_csr_out_value_5; + wire [31:0] _core_io_csr_out_value_6; + wire [31:0] _core_io_csr_out_value_7; + wire [31:0] _core_io_csr_out_value_8; + wire _core_io_halted; + wire _core_io_fault; + wire _core_io_wfi; + wire _core_io_ibus_valid; + wire [31:0] _core_io_ibus_addr; + wire _core_io_dbus_valid; + wire _core_io_dbus_write; + wire [31:0] _core_io_dbus_addr; + wire [127:0] _core_io_dbus_wdata; + wire [15:0] _core_io_dbus_wmask; + wire _core_io_ebus_dbus_valid; + wire _core_io_ebus_dbus_write; + wire [31:0] _core_io_ebus_dbus_pc; + wire [31:0] _core_io_ebus_dbus_addr; + wire [4:0] _core_io_ebus_dbus_size; + wire [127:0] _core_io_ebus_dbus_wdata; + wire [15:0] _core_io_ebus_dbus_wmask; + wire _cg_clk_o; + wire _csr_io_fabric_readData_valid; + wire [127:0] _csr_io_fabric_readData_bits; + wire _csr_io_fabric_writeResp; + wire _csr_io_reset; + wire _csr_io_cg; + wire [31:0] _csr_io_pcStart; + wire _rst_sync_clk_o; + wire _rst_sync_rstn_o; + wire _global_reset_T_2 = ~(io_te ? io_aresetn : _rst_sync_rstn_o); + reg axiSlaveEnable; + always @(posedge _rst_sync_clk_o or posedge _global_reset_T_2) + if (_global_reset_T_2) + axiSlaveEnable <= 1'h0; + else + axiSlaveEnable <= 1'h1; + RstSync rst_sync( + .clk_i(io_aclk), + .rstn_i(io_aresetn), + .clk_en(1'h1), + .te(io_te), + .clk_o(_rst_sync_clk_o), + .rstn_o(_rst_sync_rstn_o) + ); + CoreCSR csr( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_fabric_readDataAddr_bits(_fabricMux_io_ports_2_readDataAddr_bits), + .io_fabric_readData_valid(_csr_io_fabric_readData_valid), + .io_fabric_readData_bits(_csr_io_fabric_readData_bits), + .io_fabric_writeDataAddr_valid(_fabricMux_io_ports_2_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits(_fabricMux_io_ports_2_writeDataAddr_bits), + .io_fabric_writeDataBits(_fabricMux_io_ports_2_writeDataBits), + .io_fabric_writeResp(_csr_io_fabric_writeResp), + .io_reset(_csr_io_reset), + .io_cg(_csr_io_cg), + .io_pcStart(_csr_io_pcStart), + .io_halted(_core_io_halted), + .io_fault(_core_io_fault), + .io_coralnpu_csr_value_0(_core_io_csr_out_value_0), + .io_coralnpu_csr_value_1(_core_io_csr_out_value_1), + .io_coralnpu_csr_value_2(_core_io_csr_out_value_2), + .io_coralnpu_csr_value_3(_core_io_csr_out_value_3), + .io_coralnpu_csr_value_4(_core_io_csr_out_value_4), + .io_coralnpu_csr_value_5(_core_io_csr_out_value_5), + .io_coralnpu_csr_value_6(_core_io_csr_out_value_6), + .io_coralnpu_csr_value_7(_core_io_csr_out_value_7), + .io_coralnpu_csr_value_8(_core_io_csr_out_value_8) + ); + ClockGate cg( + .clk_i(_rst_sync_clk_o), + .enable(io_irq | (~_csr_io_cg & ~_core_io_wfi)), + .te(io_te), + .clk_o(_cg_clk_o) + ); + CoreMini core( + .clock(_cg_clk_o), + .reset((io_te ? ~io_aresetn : _csr_io_reset)), + .io_csr_in_value_0(_csr_io_pcStart), + .io_csr_out_value_0(_core_io_csr_out_value_0), + .io_csr_out_value_1(_core_io_csr_out_value_1), + .io_csr_out_value_2(_core_io_csr_out_value_2), + .io_csr_out_value_3(_core_io_csr_out_value_3), + .io_csr_out_value_4(_core_io_csr_out_value_4), + .io_csr_out_value_5(_core_io_csr_out_value_5), + .io_csr_out_value_6(_core_io_csr_out_value_6), + .io_csr_out_value_7(_core_io_csr_out_value_7), + .io_csr_out_value_8(_core_io_csr_out_value_8), + .io_halted(_core_io_halted), + .io_fault(_core_io_fault), + .io_wfi(_core_io_wfi), + .io_irq(io_irq), + .io_ibus_valid(_core_io_ibus_valid), + .io_ibus_addr(_core_io_ibus_addr), + .io_ibus_rdata(_itcmArbiter_io_source_0_readData_bits), + .io_ibus_fault_valid(_core_io_ibus_valid & |_core_io_ibus_addr[31:13]), + .io_dbus_valid(_core_io_dbus_valid), + .io_dbus_write(_core_io_dbus_write), + .io_dbus_addr(_core_io_dbus_addr), + .io_dbus_wdata(_core_io_dbus_wdata), + .io_dbus_wmask(_core_io_dbus_wmask), + .io_dbus_rdata(_dtcmArbiter_io_source_0_readData_bits), + .io_ebus_dbus_valid(_core_io_ebus_dbus_valid), + .io_ebus_dbus_ready(_ebus2axi_io_dbus_ready), + .io_ebus_dbus_write(_core_io_ebus_dbus_write), + .io_ebus_dbus_pc(_core_io_ebus_dbus_pc), + .io_ebus_dbus_addr(_core_io_ebus_dbus_addr), + .io_ebus_dbus_size(_core_io_ebus_dbus_size), + .io_ebus_dbus_wdata(_core_io_ebus_dbus_wdata), + .io_ebus_dbus_wmask(_core_io_ebus_dbus_wmask), + .io_ebus_dbus_rdata(_ebus2axi_io_dbus_rdata), + .io_ebus_fault_valid(_ebus2axi_io_fault_valid), + .io_ebus_fault_bits_write(_ebus2axi_io_fault_bits_write), + .io_ebus_fault_bits_addr(_ebus2axi_io_fault_bits_addr), + .io_ebus_fault_bits_epc(_ebus2axi_io_fault_bits_epc), + ); + TCM128 itcm( + .clock(_rst_sync_clk_o), + .io_addr(_itcmWrapper_io_sram_address), + .io_enable(_itcmWrapper_io_sram_enable), + .io_write(_itcmWrapper_io_sram_isWrite), + .io_wdata_0(_itcmWrapper_io_sram_writeData_0), + .io_wdata_1(_itcmWrapper_io_sram_writeData_1), + .io_wdata_2(_itcmWrapper_io_sram_writeData_2), + .io_wdata_3(_itcmWrapper_io_sram_writeData_3), + .io_wdata_4(_itcmWrapper_io_sram_writeData_4), + .io_wdata_5(_itcmWrapper_io_sram_writeData_5), + .io_wdata_6(_itcmWrapper_io_sram_writeData_6), + .io_wdata_7(_itcmWrapper_io_sram_writeData_7), + .io_wdata_8(_itcmWrapper_io_sram_writeData_8), + .io_wdata_9(_itcmWrapper_io_sram_writeData_9), + .io_wdata_10(_itcmWrapper_io_sram_writeData_10), + .io_wdata_11(_itcmWrapper_io_sram_writeData_11), + .io_wdata_12(_itcmWrapper_io_sram_writeData_12), + .io_wdata_13(_itcmWrapper_io_sram_writeData_13), + .io_wdata_14(_itcmWrapper_io_sram_writeData_14), + .io_wdata_15(_itcmWrapper_io_sram_writeData_15), + .io_wmask_0(_itcmWrapper_io_sram_mask_0), + .io_wmask_1(_itcmWrapper_io_sram_mask_1), + .io_wmask_2(_itcmWrapper_io_sram_mask_2), + .io_wmask_3(_itcmWrapper_io_sram_mask_3), + .io_wmask_4(_itcmWrapper_io_sram_mask_4), + .io_wmask_5(_itcmWrapper_io_sram_mask_5), + .io_wmask_6(_itcmWrapper_io_sram_mask_6), + .io_wmask_7(_itcmWrapper_io_sram_mask_7), + .io_wmask_8(_itcmWrapper_io_sram_mask_8), + .io_wmask_9(_itcmWrapper_io_sram_mask_9), + .io_wmask_10(_itcmWrapper_io_sram_mask_10), + .io_wmask_11(_itcmWrapper_io_sram_mask_11), + .io_wmask_12(_itcmWrapper_io_sram_mask_12), + .io_wmask_13(_itcmWrapper_io_sram_mask_13), + .io_wmask_14(_itcmWrapper_io_sram_mask_14), + .io_wmask_15(_itcmWrapper_io_sram_mask_15), + .io_rdata_0(_itcm_io_rdata_0), + .io_rdata_1(_itcm_io_rdata_1), + .io_rdata_2(_itcm_io_rdata_2), + .io_rdata_3(_itcm_io_rdata_3), + .io_rdata_4(_itcm_io_rdata_4), + .io_rdata_5(_itcm_io_rdata_5), + .io_rdata_6(_itcm_io_rdata_6), + .io_rdata_7(_itcm_io_rdata_7), + .io_rdata_8(_itcm_io_rdata_8), + .io_rdata_9(_itcm_io_rdata_9), + .io_rdata_10(_itcm_io_rdata_10), + .io_rdata_11(_itcm_io_rdata_11), + .io_rdata_12(_itcm_io_rdata_12), + .io_rdata_13(_itcm_io_rdata_13), + .io_rdata_14(_itcm_io_rdata_14), + .io_rdata_15(_itcm_io_rdata_15) + ); + SRAM itcmWrapper( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_fabric_readDataAddr_valid(_itcmArbiter_io_port_readDataAddr_valid), + .io_fabric_readDataAddr_bits(_itcmArbiter_io_port_readDataAddr_bits), + .io_fabric_readData_valid(_itcmWrapper_io_fabric_readData_valid), + .io_fabric_readData_bits(_itcmWrapper_io_fabric_readData_bits), + .io_fabric_writeDataAddr_valid(_itcmArbiter_io_port_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits(_itcmArbiter_io_port_writeDataAddr_bits), + .io_fabric_writeDataBits(_itcmArbiter_io_port_writeDataBits), + .io_fabric_writeDataStrb(_itcmArbiter_io_port_writeDataStrb), + .io_sram_address(_itcmWrapper_io_sram_address), + .io_sram_enable(_itcmWrapper_io_sram_enable), + .io_sram_isWrite(_itcmWrapper_io_sram_isWrite), + .io_sram_readData_0(_itcm_io_rdata_0), + .io_sram_readData_1(_itcm_io_rdata_1), + .io_sram_readData_2(_itcm_io_rdata_2), + .io_sram_readData_3(_itcm_io_rdata_3), + .io_sram_readData_4(_itcm_io_rdata_4), + .io_sram_readData_5(_itcm_io_rdata_5), + .io_sram_readData_6(_itcm_io_rdata_6), + .io_sram_readData_7(_itcm_io_rdata_7), + .io_sram_readData_8(_itcm_io_rdata_8), + .io_sram_readData_9(_itcm_io_rdata_9), + .io_sram_readData_10(_itcm_io_rdata_10), + .io_sram_readData_11(_itcm_io_rdata_11), + .io_sram_readData_12(_itcm_io_rdata_12), + .io_sram_readData_13(_itcm_io_rdata_13), + .io_sram_readData_14(_itcm_io_rdata_14), + .io_sram_readData_15(_itcm_io_rdata_15), + .io_sram_writeData_0(_itcmWrapper_io_sram_writeData_0), + .io_sram_writeData_1(_itcmWrapper_io_sram_writeData_1), + .io_sram_writeData_2(_itcmWrapper_io_sram_writeData_2), + .io_sram_writeData_3(_itcmWrapper_io_sram_writeData_3), + .io_sram_writeData_4(_itcmWrapper_io_sram_writeData_4), + .io_sram_writeData_5(_itcmWrapper_io_sram_writeData_5), + .io_sram_writeData_6(_itcmWrapper_io_sram_writeData_6), + .io_sram_writeData_7(_itcmWrapper_io_sram_writeData_7), + .io_sram_writeData_8(_itcmWrapper_io_sram_writeData_8), + .io_sram_writeData_9(_itcmWrapper_io_sram_writeData_9), + .io_sram_writeData_10(_itcmWrapper_io_sram_writeData_10), + .io_sram_writeData_11(_itcmWrapper_io_sram_writeData_11), + .io_sram_writeData_12(_itcmWrapper_io_sram_writeData_12), + .io_sram_writeData_13(_itcmWrapper_io_sram_writeData_13), + .io_sram_writeData_14(_itcmWrapper_io_sram_writeData_14), + .io_sram_writeData_15(_itcmWrapper_io_sram_writeData_15), + .io_sram_mask_0(_itcmWrapper_io_sram_mask_0), + .io_sram_mask_1(_itcmWrapper_io_sram_mask_1), + .io_sram_mask_2(_itcmWrapper_io_sram_mask_2), + .io_sram_mask_3(_itcmWrapper_io_sram_mask_3), + .io_sram_mask_4(_itcmWrapper_io_sram_mask_4), + .io_sram_mask_5(_itcmWrapper_io_sram_mask_5), + .io_sram_mask_6(_itcmWrapper_io_sram_mask_6), + .io_sram_mask_7(_itcmWrapper_io_sram_mask_7), + .io_sram_mask_8(_itcmWrapper_io_sram_mask_8), + .io_sram_mask_9(_itcmWrapper_io_sram_mask_9), + .io_sram_mask_10(_itcmWrapper_io_sram_mask_10), + .io_sram_mask_11(_itcmWrapper_io_sram_mask_11), + .io_sram_mask_12(_itcmWrapper_io_sram_mask_12), + .io_sram_mask_13(_itcmWrapper_io_sram_mask_13), + .io_sram_mask_14(_itcmWrapper_io_sram_mask_14), + .io_sram_mask_15(_itcmWrapper_io_sram_mask_15) + ); + FabricArbiter itcmArbiter( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_source_0_readDataAddr_valid(_core_io_ibus_valid), + .io_source_0_readDataAddr_bits(_core_io_ibus_addr), + .io_source_0_readData_bits(_itcmArbiter_io_source_0_readData_bits), + .io_source_0_writeDataAddr_valid(1'h0), + .io_source_0_writeDataAddr_bits(32'h00000000), + .io_source_0_writeDataBits(128'h00000000000000000000000000000000), + .io_source_0_writeDataStrb(16'h0000), + .io_source_1_readDataAddr_valid(_fabricMux_io_ports_0_readDataAddr_valid), + .io_source_1_readDataAddr_bits(_fabricMux_io_ports_0_readDataAddr_bits), + .io_source_1_readData_valid(_itcmArbiter_io_source_1_readData_valid), + .io_source_1_readData_bits(_itcmArbiter_io_source_1_readData_bits), + .io_source_1_writeDataAddr_valid(_fabricMux_io_ports_0_writeDataAddr_valid), + .io_source_1_writeDataAddr_bits(_fabricMux_io_ports_0_writeDataAddr_bits), + .io_source_1_writeDataBits(_fabricMux_io_ports_0_writeDataBits), + .io_source_1_writeDataStrb(_fabricMux_io_ports_0_writeDataStrb), + .io_fabricBusy_1(_itcmArbiter_io_fabricBusy_1), + .io_port_readDataAddr_valid(_itcmArbiter_io_port_readDataAddr_valid), + .io_port_readDataAddr_bits(_itcmArbiter_io_port_readDataAddr_bits), + .io_port_readData_valid(_itcmWrapper_io_fabric_readData_valid), + .io_port_readData_bits(_itcmWrapper_io_fabric_readData_bits), + .io_port_writeDataAddr_valid(_itcmArbiter_io_port_writeDataAddr_valid), + .io_port_writeDataAddr_bits(_itcmArbiter_io_port_writeDataAddr_bits), + .io_port_writeDataBits(_itcmArbiter_io_port_writeDataBits), + .io_port_writeDataStrb(_itcmArbiter_io_port_writeDataStrb) + ); + TCM128_1 dtcm( + .clock(_rst_sync_clk_o), + .io_addr(_dtcmWrapper_io_sram_address), + .io_enable(_dtcmWrapper_io_sram_enable), + .io_write(_dtcmWrapper_io_sram_isWrite), + .io_wdata_0(_dtcmWrapper_io_sram_writeData_0), + .io_wdata_1(_dtcmWrapper_io_sram_writeData_1), + .io_wdata_2(_dtcmWrapper_io_sram_writeData_2), + .io_wdata_3(_dtcmWrapper_io_sram_writeData_3), + .io_wdata_4(_dtcmWrapper_io_sram_writeData_4), + .io_wdata_5(_dtcmWrapper_io_sram_writeData_5), + .io_wdata_6(_dtcmWrapper_io_sram_writeData_6), + .io_wdata_7(_dtcmWrapper_io_sram_writeData_7), + .io_wdata_8(_dtcmWrapper_io_sram_writeData_8), + .io_wdata_9(_dtcmWrapper_io_sram_writeData_9), + .io_wdata_10(_dtcmWrapper_io_sram_writeData_10), + .io_wdata_11(_dtcmWrapper_io_sram_writeData_11), + .io_wdata_12(_dtcmWrapper_io_sram_writeData_12), + .io_wdata_13(_dtcmWrapper_io_sram_writeData_13), + .io_wdata_14(_dtcmWrapper_io_sram_writeData_14), + .io_wdata_15(_dtcmWrapper_io_sram_writeData_15), + .io_wmask_0(_dtcmWrapper_io_sram_mask_0), + .io_wmask_1(_dtcmWrapper_io_sram_mask_1), + .io_wmask_2(_dtcmWrapper_io_sram_mask_2), + .io_wmask_3(_dtcmWrapper_io_sram_mask_3), + .io_wmask_4(_dtcmWrapper_io_sram_mask_4), + .io_wmask_5(_dtcmWrapper_io_sram_mask_5), + .io_wmask_6(_dtcmWrapper_io_sram_mask_6), + .io_wmask_7(_dtcmWrapper_io_sram_mask_7), + .io_wmask_8(_dtcmWrapper_io_sram_mask_8), + .io_wmask_9(_dtcmWrapper_io_sram_mask_9), + .io_wmask_10(_dtcmWrapper_io_sram_mask_10), + .io_wmask_11(_dtcmWrapper_io_sram_mask_11), + .io_wmask_12(_dtcmWrapper_io_sram_mask_12), + .io_wmask_13(_dtcmWrapper_io_sram_mask_13), + .io_wmask_14(_dtcmWrapper_io_sram_mask_14), + .io_wmask_15(_dtcmWrapper_io_sram_mask_15), + .io_rdata_0(_dtcm_io_rdata_0), + .io_rdata_1(_dtcm_io_rdata_1), + .io_rdata_2(_dtcm_io_rdata_2), + .io_rdata_3(_dtcm_io_rdata_3), + .io_rdata_4(_dtcm_io_rdata_4), + .io_rdata_5(_dtcm_io_rdata_5), + .io_rdata_6(_dtcm_io_rdata_6), + .io_rdata_7(_dtcm_io_rdata_7), + .io_rdata_8(_dtcm_io_rdata_8), + .io_rdata_9(_dtcm_io_rdata_9), + .io_rdata_10(_dtcm_io_rdata_10), + .io_rdata_11(_dtcm_io_rdata_11), + .io_rdata_12(_dtcm_io_rdata_12), + .io_rdata_13(_dtcm_io_rdata_13), + .io_rdata_14(_dtcm_io_rdata_14), + .io_rdata_15(_dtcm_io_rdata_15) + ); + SRAM_1 dtcmWrapper( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_fabric_readDataAddr_valid(_dtcmArbiter_io_port_readDataAddr_valid), + .io_fabric_readDataAddr_bits(_dtcmArbiter_io_port_readDataAddr_bits), + .io_fabric_readData_valid(_dtcmWrapper_io_fabric_readData_valid), + .io_fabric_readData_bits(_dtcmWrapper_io_fabric_readData_bits), + .io_fabric_writeDataAddr_valid(_dtcmArbiter_io_port_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits(_dtcmArbiter_io_port_writeDataAddr_bits), + .io_fabric_writeDataBits(_dtcmArbiter_io_port_writeDataBits), + .io_fabric_writeDataStrb(_dtcmArbiter_io_port_writeDataStrb), + .io_sram_address(_dtcmWrapper_io_sram_address), + .io_sram_enable(_dtcmWrapper_io_sram_enable), + .io_sram_isWrite(_dtcmWrapper_io_sram_isWrite), + .io_sram_readData_0(_dtcm_io_rdata_0), + .io_sram_readData_1(_dtcm_io_rdata_1), + .io_sram_readData_2(_dtcm_io_rdata_2), + .io_sram_readData_3(_dtcm_io_rdata_3), + .io_sram_readData_4(_dtcm_io_rdata_4), + .io_sram_readData_5(_dtcm_io_rdata_5), + .io_sram_readData_6(_dtcm_io_rdata_6), + .io_sram_readData_7(_dtcm_io_rdata_7), + .io_sram_readData_8(_dtcm_io_rdata_8), + .io_sram_readData_9(_dtcm_io_rdata_9), + .io_sram_readData_10(_dtcm_io_rdata_10), + .io_sram_readData_11(_dtcm_io_rdata_11), + .io_sram_readData_12(_dtcm_io_rdata_12), + .io_sram_readData_13(_dtcm_io_rdata_13), + .io_sram_readData_14(_dtcm_io_rdata_14), + .io_sram_readData_15(_dtcm_io_rdata_15), + .io_sram_writeData_0(_dtcmWrapper_io_sram_writeData_0), + .io_sram_writeData_1(_dtcmWrapper_io_sram_writeData_1), + .io_sram_writeData_2(_dtcmWrapper_io_sram_writeData_2), + .io_sram_writeData_3(_dtcmWrapper_io_sram_writeData_3), + .io_sram_writeData_4(_dtcmWrapper_io_sram_writeData_4), + .io_sram_writeData_5(_dtcmWrapper_io_sram_writeData_5), + .io_sram_writeData_6(_dtcmWrapper_io_sram_writeData_6), + .io_sram_writeData_7(_dtcmWrapper_io_sram_writeData_7), + .io_sram_writeData_8(_dtcmWrapper_io_sram_writeData_8), + .io_sram_writeData_9(_dtcmWrapper_io_sram_writeData_9), + .io_sram_writeData_10(_dtcmWrapper_io_sram_writeData_10), + .io_sram_writeData_11(_dtcmWrapper_io_sram_writeData_11), + .io_sram_writeData_12(_dtcmWrapper_io_sram_writeData_12), + .io_sram_writeData_13(_dtcmWrapper_io_sram_writeData_13), + .io_sram_writeData_14(_dtcmWrapper_io_sram_writeData_14), + .io_sram_writeData_15(_dtcmWrapper_io_sram_writeData_15), + .io_sram_mask_0(_dtcmWrapper_io_sram_mask_0), + .io_sram_mask_1(_dtcmWrapper_io_sram_mask_1), + .io_sram_mask_2(_dtcmWrapper_io_sram_mask_2), + .io_sram_mask_3(_dtcmWrapper_io_sram_mask_3), + .io_sram_mask_4(_dtcmWrapper_io_sram_mask_4), + .io_sram_mask_5(_dtcmWrapper_io_sram_mask_5), + .io_sram_mask_6(_dtcmWrapper_io_sram_mask_6), + .io_sram_mask_7(_dtcmWrapper_io_sram_mask_7), + .io_sram_mask_8(_dtcmWrapper_io_sram_mask_8), + .io_sram_mask_9(_dtcmWrapper_io_sram_mask_9), + .io_sram_mask_10(_dtcmWrapper_io_sram_mask_10), + .io_sram_mask_11(_dtcmWrapper_io_sram_mask_11), + .io_sram_mask_12(_dtcmWrapper_io_sram_mask_12), + .io_sram_mask_13(_dtcmWrapper_io_sram_mask_13), + .io_sram_mask_14(_dtcmWrapper_io_sram_mask_14), + .io_sram_mask_15(_dtcmWrapper_io_sram_mask_15) + ); + FabricArbiter dtcmArbiter( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_source_0_readDataAddr_valid(_core_io_dbus_valid & ~_core_io_dbus_write), + .io_source_0_readDataAddr_bits(_core_io_dbus_addr), + .io_source_0_readData_bits(_dtcmArbiter_io_source_0_readData_bits), + .io_source_0_writeDataAddr_valid(_core_io_dbus_valid & _core_io_dbus_write), + .io_source_0_writeDataAddr_bits(_core_io_dbus_addr), + .io_source_0_writeDataBits(_core_io_dbus_wdata), + .io_source_0_writeDataStrb(_core_io_dbus_wmask), + .io_source_1_readDataAddr_valid(_fabricMux_io_ports_1_readDataAddr_valid), + .io_source_1_readDataAddr_bits(_fabricMux_io_ports_1_readDataAddr_bits), + .io_source_1_readData_valid(_dtcmArbiter_io_source_1_readData_valid), + .io_source_1_readData_bits(_dtcmArbiter_io_source_1_readData_bits), + .io_source_1_writeDataAddr_valid(_fabricMux_io_ports_1_writeDataAddr_valid), + .io_source_1_writeDataAddr_bits(_fabricMux_io_ports_1_writeDataAddr_bits), + .io_source_1_writeDataBits(_fabricMux_io_ports_1_writeDataBits), + .io_source_1_writeDataStrb(_fabricMux_io_ports_1_writeDataStrb), + .io_fabricBusy_1(_dtcmArbiter_io_fabricBusy_1), + .io_port_readDataAddr_valid(_dtcmArbiter_io_port_readDataAddr_valid), + .io_port_readDataAddr_bits(_dtcmArbiter_io_port_readDataAddr_bits), + .io_port_readData_valid(_dtcmWrapper_io_fabric_readData_valid), + .io_port_readData_bits(_dtcmWrapper_io_fabric_readData_bits), + .io_port_writeDataAddr_valid(_dtcmArbiter_io_port_writeDataAddr_valid), + .io_port_writeDataAddr_bits(_dtcmArbiter_io_port_writeDataAddr_bits), + .io_port_writeDataBits(_dtcmArbiter_io_port_writeDataBits), + .io_port_writeDataStrb(_dtcmArbiter_io_port_writeDataStrb) + ); + FabricMux fabricMux( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_source_readDataAddr_valid(_axiSlave_io_fabric_readDataAddr_valid), + .io_source_readDataAddr_bits(_axiSlave_io_fabric_readDataAddr_bits), + .io_source_readData_valid(_fabricMux_io_source_readData_valid), + .io_source_readData_bits(_fabricMux_io_source_readData_bits), + .io_source_writeDataAddr_valid(_axiSlave_io_fabric_writeDataAddr_valid), + .io_source_writeDataAddr_bits(_axiSlave_io_fabric_writeDataAddr_bits), + .io_source_writeDataBits(_axiSlave_io_fabric_writeDataBits), + .io_source_writeDataStrb(_axiSlave_io_fabric_writeDataStrb), + .io_source_writeResp(_fabricMux_io_source_writeResp), + .io_fabricBusy(_fabricMux_io_fabricBusy), + .io_ports_0_readDataAddr_valid(_fabricMux_io_ports_0_readDataAddr_valid), + .io_ports_0_readDataAddr_bits(_fabricMux_io_ports_0_readDataAddr_bits), + .io_ports_0_readData_valid(_itcmArbiter_io_source_1_readData_valid), + .io_ports_0_readData_bits(_itcmArbiter_io_source_1_readData_bits), + .io_ports_0_writeDataAddr_valid(_fabricMux_io_ports_0_writeDataAddr_valid), + .io_ports_0_writeDataAddr_bits(_fabricMux_io_ports_0_writeDataAddr_bits), + .io_ports_0_writeDataBits(_fabricMux_io_ports_0_writeDataBits), + .io_ports_0_writeDataStrb(_fabricMux_io_ports_0_writeDataStrb), + .io_ports_1_readDataAddr_valid(_fabricMux_io_ports_1_readDataAddr_valid), + .io_ports_1_readDataAddr_bits(_fabricMux_io_ports_1_readDataAddr_bits), + .io_ports_1_readData_valid(_dtcmArbiter_io_source_1_readData_valid), + .io_ports_1_readData_bits(_dtcmArbiter_io_source_1_readData_bits), + .io_ports_1_writeDataAddr_valid(_fabricMux_io_ports_1_writeDataAddr_valid), + .io_ports_1_writeDataAddr_bits(_fabricMux_io_ports_1_writeDataAddr_bits), + .io_ports_1_writeDataBits(_fabricMux_io_ports_1_writeDataBits), + .io_ports_1_writeDataStrb(_fabricMux_io_ports_1_writeDataStrb), + .io_ports_2_readDataAddr_bits(_fabricMux_io_ports_2_readDataAddr_bits), + .io_ports_2_readData_valid(_csr_io_fabric_readData_valid), + .io_ports_2_readData_bits(_csr_io_fabric_readData_bits), + .io_ports_2_writeDataAddr_valid(_fabricMux_io_ports_2_writeDataAddr_valid), + .io_ports_2_writeDataAddr_bits(_fabricMux_io_ports_2_writeDataAddr_bits), + .io_ports_2_writeDataBits(_fabricMux_io_ports_2_writeDataBits), + .io_ports_2_writeResp(_csr_io_fabric_writeResp), + .io_periBusy_0(_itcmArbiter_io_fabricBusy_1), + .io_periBusy_1(_dtcmArbiter_io_fabricBusy_1) + ); + AxiSlave axiSlave( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_axi_write_addr_ready(_axiSlave_io_axi_write_addr_ready), + .io_axi_write_addr_valid(io_axi_slave_write_addr_valid & axiSlaveEnable), + .io_axi_write_addr_bits_addr(io_axi_slave_write_addr_bits_addr), + .io_axi_write_addr_bits_prot(io_axi_slave_write_addr_bits_prot), + .io_axi_write_addr_bits_id(io_axi_slave_write_addr_bits_id), + .io_axi_write_addr_bits_len(io_axi_slave_write_addr_bits_len), + .io_axi_write_addr_bits_size(io_axi_slave_write_addr_bits_size), + .io_axi_write_addr_bits_burst(io_axi_slave_write_addr_bits_burst), + .io_axi_write_addr_bits_lock(io_axi_slave_write_addr_bits_lock), + .io_axi_write_addr_bits_cache(io_axi_slave_write_addr_bits_cache), + .io_axi_write_addr_bits_qos(io_axi_slave_write_addr_bits_qos), + .io_axi_write_addr_bits_region(io_axi_slave_write_addr_bits_region), + .io_axi_write_data_ready(_axiSlave_io_axi_write_data_ready), + .io_axi_write_data_valid(io_axi_slave_write_data_valid & axiSlaveEnable), + .io_axi_write_data_bits_data(io_axi_slave_write_data_bits_data), + .io_axi_write_data_bits_last(io_axi_slave_write_data_bits_last), + .io_axi_write_data_bits_strb(io_axi_slave_write_data_bits_strb), + .io_axi_write_resp_ready(io_axi_slave_write_resp_ready & axiSlaveEnable), + .io_axi_write_resp_valid(_axiSlave_io_axi_write_resp_valid), + .io_axi_write_resp_bits_id(io_axi_slave_write_resp_bits_id), + .io_axi_write_resp_bits_resp(io_axi_slave_write_resp_bits_resp), + .io_axi_read_addr_ready(_axiSlave_io_axi_read_addr_ready), + .io_axi_read_addr_valid(io_axi_slave_read_addr_valid & axiSlaveEnable), + .io_axi_read_addr_bits_addr(io_axi_slave_read_addr_bits_addr), + .io_axi_read_addr_bits_prot(io_axi_slave_read_addr_bits_prot), + .io_axi_read_addr_bits_id(io_axi_slave_read_addr_bits_id), + .io_axi_read_addr_bits_len(io_axi_slave_read_addr_bits_len), + .io_axi_read_addr_bits_size(io_axi_slave_read_addr_bits_size), + .io_axi_read_addr_bits_burst(io_axi_slave_read_addr_bits_burst), + .io_axi_read_addr_bits_lock(io_axi_slave_read_addr_bits_lock), + .io_axi_read_addr_bits_cache(io_axi_slave_read_addr_bits_cache), + .io_axi_read_addr_bits_qos(io_axi_slave_read_addr_bits_qos), + .io_axi_read_addr_bits_region(io_axi_slave_read_addr_bits_region), + .io_axi_read_data_ready(io_axi_slave_read_data_ready & axiSlaveEnable), + .io_axi_read_data_valid(_axiSlave_io_axi_read_data_valid), + .io_axi_read_data_bits_data(io_axi_slave_read_data_bits_data), + .io_axi_read_data_bits_id(io_axi_slave_read_data_bits_id), + .io_axi_read_data_bits_resp(io_axi_slave_read_data_bits_resp), + .io_axi_read_data_bits_last(io_axi_slave_read_data_bits_last), + .io_fabric_readDataAddr_valid(_axiSlave_io_fabric_readDataAddr_valid), + .io_fabric_readDataAddr_bits(_axiSlave_io_fabric_readDataAddr_bits), + .io_fabric_readData_valid(_fabricMux_io_source_readData_valid), + .io_fabric_readData_bits(_fabricMux_io_source_readData_bits), + .io_fabric_writeDataAddr_valid(_axiSlave_io_fabric_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits(_axiSlave_io_fabric_writeDataAddr_bits), + .io_fabric_writeDataBits(_axiSlave_io_fabric_writeDataBits), + .io_fabric_writeDataStrb(_axiSlave_io_fabric_writeDataStrb), + .io_fabric_writeResp(_fabricMux_io_source_writeResp), + .io_periBusy(_fabricMux_io_fabricBusy) + ); + DBus2AxiV2 ebus2axi( + .clock(_rst_sync_clk_o), + .reset(_global_reset_T_2), + .io_dbus_valid(_core_io_ebus_dbus_valid), + .io_dbus_ready(_ebus2axi_io_dbus_ready), + .io_dbus_write(_core_io_ebus_dbus_write), + .io_dbus_pc(_core_io_ebus_dbus_pc), + .io_dbus_addr(_core_io_ebus_dbus_addr), + .io_dbus_size(_core_io_ebus_dbus_size), + .io_dbus_wdata(_core_io_ebus_dbus_wdata), + .io_dbus_wmask(_core_io_ebus_dbus_wmask), + .io_dbus_rdata(_ebus2axi_io_dbus_rdata), + .io_axi_write_addr_ready(io_axi_master_write_addr_ready), + .io_axi_write_addr_valid(io_axi_master_write_addr_valid), + .io_axi_write_addr_bits_addr(io_axi_master_write_addr_bits_addr), + .io_axi_write_addr_bits_size(io_axi_master_write_addr_bits_size), + .io_axi_write_data_ready(io_axi_master_write_data_ready), + .io_axi_write_data_valid(io_axi_master_write_data_valid), + .io_axi_write_data_bits_data(io_axi_master_write_data_bits_data), + .io_axi_write_data_bits_last(io_axi_master_write_data_bits_last), + .io_axi_write_data_bits_strb(io_axi_master_write_data_bits_strb), + .io_axi_write_resp_ready(io_axi_master_write_resp_ready), + .io_axi_write_resp_valid(io_axi_master_write_resp_valid), + .io_axi_write_resp_bits_resp(io_axi_master_write_resp_bits_resp), + .io_axi_read_addr_ready(io_axi_master_read_addr_ready), + .io_axi_read_addr_valid(io_axi_master_read_addr_valid), + .io_axi_read_addr_bits_addr(io_axi_master_read_addr_bits_addr), + .io_axi_read_addr_bits_size(io_axi_master_read_addr_bits_size), + .io_axi_read_data_ready(io_axi_master_read_data_ready), + .io_axi_read_data_valid(io_axi_master_read_data_valid), + .io_axi_read_data_bits_data(io_axi_master_read_data_bits_data), + .io_axi_read_data_bits_resp(io_axi_master_read_data_bits_resp), + .io_fault_valid(_ebus2axi_io_fault_valid), + .io_fault_bits_write(_ebus2axi_io_fault_bits_write), + .io_fault_bits_addr(_ebus2axi_io_fault_bits_addr), + .io_fault_bits_epc(_ebus2axi_io_fault_bits_epc) + ); + assign io_axi_slave_write_addr_ready = _axiSlave_io_axi_write_addr_ready & axiSlaveEnable; + assign io_axi_slave_write_data_ready = _axiSlave_io_axi_write_data_ready & axiSlaveEnable; + assign io_axi_slave_write_resp_valid = _axiSlave_io_axi_write_resp_valid & axiSlaveEnable; + assign io_axi_slave_read_addr_ready = _axiSlave_io_axi_read_addr_ready & axiSlaveEnable; + assign io_axi_slave_read_data_valid = _axiSlave_io_axi_read_data_valid & axiSlaveEnable; + assign io_axi_master_write_addr_bits_prot = 3'h2; + assign io_axi_master_write_addr_bits_id = 6'h00; + assign io_axi_master_write_addr_bits_len = 8'h00; + assign io_axi_master_write_addr_bits_burst = 2'h1; + assign io_axi_master_write_addr_bits_lock = 1'h0; + assign io_axi_master_write_addr_bits_cache = 4'h0; + assign io_axi_master_write_addr_bits_qos = 4'h0; + assign io_axi_master_write_addr_bits_region = 4'h0; + assign io_axi_master_read_addr_bits_prot = 3'h2; + assign io_axi_master_read_addr_bits_id = 6'h00; + assign io_axi_master_read_addr_bits_len = 8'h00; + assign io_axi_master_read_addr_bits_burst = 2'h1; + assign io_axi_master_read_addr_bits_lock = 1'h0; + assign io_axi_master_read_addr_bits_cache = 4'h0; + assign io_axi_master_read_addr_bits_qos = 4'h0; + assign io_axi_master_read_addr_bits_region = 4'h0; + assign io_halted = _core_io_halted; + assign io_fault = _core_io_fault; + assign io_wfi = _core_io_wfi; +endmodule +module Regfile_Verification_Assert ( + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + _GEN_4, + reset, + _GEN_5, + _GEN_6, + _GEN_7, + _GEN_8, + _GEN_9, + _GEN_10, + _GEN_11, + _GEN_12, + _GEN_13, + _GEN_14, + _GEN_15, + _GEN_16, + _GEN_17, + _GEN_18, + _GEN_19, + _GEN_20, + _GEN_21, + _GEN_22, + _GEN_23, + _GEN_24, + _GEN_25, + _GEN_26, + _GEN_27, + _GEN_28, + _GEN_29, + _GEN_30, + _GEN_31, + _GEN_32, + _GEN_33, + _GEN_34, + _GEN_35, + _GEN_36, + _GEN_37, + _GEN_38, + _GEN_39, + _GEN_40, + _GEN_41, + _GEN_42, + _GEN_43, + _GEN_44, + _GEN_45, + _GEN_46, + _GEN_47, + _GEN_48, + _GEN_49, + _GEN_50, + _GEN_51, + _GEN_52, + _GEN_53, + _GEN_54, + _GEN_55, + _GEN_56, + _GEN_57, + _GEN_58, + _GEN_59, + _GEN_60, + _GEN_61, + _GEN_62, + _GEN_63, + _GEN_64, + _GEN_65, + _GEN_66, + _GEN_67, + _GEN_68, + _GEN_69, + _GEN_70, + _GEN_71, + _GEN_72, + _GEN_73, + _GEN_74, + _GEN_75, + _GEN_76, + _GEN_77, + _GEN_78, + _GEN_79, + _GEN_80, + _GEN_81, + _GEN_82, + _GEN_83, + _GEN_84, + _GEN_85, + _GEN_86, + _GEN_87, + _GEN_88, + _GEN_89, + _GEN_90, + _GEN_91, + _GEN_92, + _GEN_93, + _GEN_94, + _GEN_95, + _GEN_96, + _GEN_97, + _GEN_98, + _GEN_99, + _GEN_100, + _GEN_101, + _GEN_102, + _GEN_103, + _GEN_104, + _GEN_105, + _GEN_106, + _GEN_107, + _GEN_108, + _GEN_109, + _GEN_110, + _GEN_111, + _GEN_112, + _GEN_113, + _GEN_114, + _GEN_115, + _GEN_116, + _GEN_117, + _GEN_118, + _GEN_119, + _GEN_120, + _GEN_121, + _GEN_122, + _GEN_123, + _GEN_124, + _GEN_125, + _GEN_126, + _GEN_127, + _GEN_128, + _GEN_129, + _GEN_130, + _GEN_131, + _GEN_132, + _GEN_133, + _GEN_134, + _GEN_135, + _GEN_136, + _GEN_137, + _GEN_138, + _GEN_139, + _GEN_140, + _GEN_141, + _GEN_142, + _GEN_143, + _GEN_144, + _GEN_145, + _GEN_146, + _GEN_147, + _GEN_148, + _GEN_149, + _GEN_150, + _GEN_151, + _GEN_152, + _GEN_153, + _GEN_154, + _GEN_155, + _GEN_156, + _GEN_157, + _GEN_158, + _GEN_159, + _GEN_160, + _GEN_161, + _GEN_162, + _GEN_163, + _GEN_164, + _GEN_165, + _GEN_166, + _GEN_167, + _GEN_168, + _GEN_169, + _GEN_170, + _GEN_171, + _GEN_172, + _GEN_173, + _GEN_174, + _GEN_175, + _GEN_176, + _GEN_177, + _GEN_178, + _GEN_179, + _GEN_180, + _GEN_181, + _GEN_182, + _GEN_183, + _GEN_184, + _GEN_185, + write_fail, + write_fail_1, + write_fail_2, + write_fail_3, + write_fail_4, + write_fail_5, + write_fail_6, + write_fail_7, + write_fail_8, + write_fail_9, + write_fail_10, + write_fail_11, + write_fail_12, + write_fail_13, + write_fail_14, + scoreboard_error, + clock +); + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input _GEN_3; + input _GEN_4; + input reset; + input _GEN_5; + input _GEN_6; + input _GEN_7; + input _GEN_8; + input _GEN_9; + input _GEN_10; + input _GEN_11; + input _GEN_12; + input _GEN_13; + input _GEN_14; + input _GEN_15; + input _GEN_16; + input _GEN_17; + input _GEN_18; + input _GEN_19; + input _GEN_20; + input _GEN_21; + input _GEN_22; + input _GEN_23; + input _GEN_24; + input _GEN_25; + input _GEN_26; + input _GEN_27; + input _GEN_28; + input _GEN_29; + input _GEN_30; + input _GEN_31; + input _GEN_32; + input _GEN_33; + input _GEN_34; + input _GEN_35; + input _GEN_36; + input _GEN_37; + input _GEN_38; + input _GEN_39; + input _GEN_40; + input _GEN_41; + input _GEN_42; + input _GEN_43; + input _GEN_44; + input _GEN_45; + input _GEN_46; + input _GEN_47; + input _GEN_48; + input _GEN_49; + input _GEN_50; + input _GEN_51; + input _GEN_52; + input _GEN_53; + input _GEN_54; + input _GEN_55; + input _GEN_56; + input _GEN_57; + input _GEN_58; + input _GEN_59; + input _GEN_60; + input _GEN_61; + input _GEN_62; + input _GEN_63; + input _GEN_64; + input _GEN_65; + input _GEN_66; + input _GEN_67; + input _GEN_68; + input _GEN_69; + input _GEN_70; + input _GEN_71; + input _GEN_72; + input _GEN_73; + input _GEN_74; + input _GEN_75; + input _GEN_76; + input _GEN_77; + input _GEN_78; + input _GEN_79; + input _GEN_80; + input _GEN_81; + input _GEN_82; + input _GEN_83; + input _GEN_84; + input _GEN_85; + input _GEN_86; + input _GEN_87; + input _GEN_88; + input _GEN_89; + input _GEN_90; + input _GEN_91; + input _GEN_92; + input _GEN_93; + input _GEN_94; + input _GEN_95; + input _GEN_96; + input _GEN_97; + input _GEN_98; + input _GEN_99; + input _GEN_100; + input _GEN_101; + input _GEN_102; + input _GEN_103; + input _GEN_104; + input _GEN_105; + input _GEN_106; + input _GEN_107; + input _GEN_108; + input _GEN_109; + input _GEN_110; + input _GEN_111; + input _GEN_112; + input _GEN_113; + input _GEN_114; + input _GEN_115; + input _GEN_116; + input _GEN_117; + input _GEN_118; + input _GEN_119; + input _GEN_120; + input _GEN_121; + input _GEN_122; + input _GEN_123; + input _GEN_124; + input _GEN_125; + input _GEN_126; + input _GEN_127; + input _GEN_128; + input _GEN_129; + input _GEN_130; + input _GEN_131; + input _GEN_132; + input _GEN_133; + input _GEN_134; + input _GEN_135; + input _GEN_136; + input _GEN_137; + input _GEN_138; + input _GEN_139; + input _GEN_140; + input _GEN_141; + input _GEN_142; + input _GEN_143; + input _GEN_144; + input _GEN_145; + input _GEN_146; + input _GEN_147; + input _GEN_148; + input _GEN_149; + input _GEN_150; + input _GEN_151; + input _GEN_152; + input _GEN_153; + input _GEN_154; + input _GEN_155; + input _GEN_156; + input _GEN_157; + input _GEN_158; + input _GEN_159; + input _GEN_160; + input _GEN_161; + input _GEN_162; + input _GEN_163; + input _GEN_164; + input _GEN_165; + input _GEN_166; + input _GEN_167; + input _GEN_168; + input _GEN_169; + input _GEN_170; + input _GEN_171; + input _GEN_172; + input _GEN_173; + input _GEN_174; + input _GEN_175; + input _GEN_176; + input _GEN_177; + input _GEN_178; + input _GEN_179; + input _GEN_180; + input _GEN_181; + input _GEN_182; + input _GEN_183; + input _GEN_184; + input _GEN_185; + input write_fail; + input write_fail_1; + input write_fail_2; + input write_fail_3; + input write_fail_4; + input write_fail_5; + input write_fail_6; + input write_fail_7; + input write_fail_8; + input write_fail_9; + input write_fail_10; + input write_fail_11; + input write_fail_12; + input write_fail_13; + input write_fail_14; + input scoreboard_error; + input clock; +endmodule +module FetchControl_Verification_Assert ( + predecode_firstJumpOH_2, + predecode_firstJumpOH_3, + predecode_firstJumpOH_0, + predecode_firstJumpOH_1, + reset, + _GEN, + clock +); + input predecode_firstJumpOH_2; + input predecode_firstJumpOH_3; + input predecode_firstJumpOH_0; + input predecode_firstJumpOH_1; + input reset; + input _GEN; + input clock; +endmodule +module CircularBufferMulti_Verification_Assert ( + io_nEnqueued, + io_enqValid, + io_deqReady, + reset, + _GEN, + clock +); + input [3:0] io_nEnqueued; + input [2:0] io_enqValid; + input [2:0] io_deqReady; + input reset; + input [3:0] _GEN; + input clock; +endmodule +module InstructionBuffer_Verification_Assert ( + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + reset, + clock +); + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input reset; + input clock; +endmodule +module Csr_Verification_Assert ( + csr_address, + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + _GEN_4, + _GEN_5, + _GEN_6, + _GEN_7, + _GEN_8, + _GEN_9, + _GEN_10, + _GEN_11, + _GEN_12, + _GEN_13, + _GEN_14, + _GEN_15, + _GEN_16, + _GEN_17, + _GEN_18, + _GEN_19, + _GEN_20, + _GEN_21, + _GEN_22, + _GEN_23, + _GEN_24, + _GEN_25, + _GEN_26, + _GEN_27, + _GEN_28, + _GEN_29, + req_valid, + reset, + io_halted, + io_wfi, + io_fault, + _GEN_30, + io_rs1_valid, + clock +); + input [11:0] csr_address; + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input _GEN_3; + input _GEN_4; + input _GEN_5; + input _GEN_6; + input _GEN_7; + input _GEN_8; + input _GEN_9; + input _GEN_10; + input _GEN_11; + input _GEN_12; + input _GEN_13; + input _GEN_14; + input _GEN_15; + input _GEN_16; + input _GEN_17; + input _GEN_18; + input _GEN_19; + input _GEN_20; + input _GEN_21; + input _GEN_22; + input _GEN_23; + input _GEN_24; + input _GEN_25; + input _GEN_26; + input _GEN_27; + input _GEN_28; + input _GEN_29; + input req_valid; + input reset; + input io_halted; + input io_wfi; + input io_fault; + input _GEN_30; + input io_rs1_valid; + input clock; +endmodule +module DispatchV2_Verification_Assert ( + decodedInsts_0_sub, + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + _GEN_4, + _GEN_5, + _GEN_6, + _GEN_7, + decodedInsts_0_orn, + decodedInsts_0_xnor, + decodedInsts_0_lui, + decodedInsts_0_andn, + decodedInsts_0_ctz, + decodedInsts_0_cpop, + decodedInsts_0_clz, + decodedInsts_0_min, + decodedInsts_0_minu, + decodedInsts_0_max, + decodedInsts_0_maxu, + decodedInsts_0_rol, + decodedInsts_0_ror, + decodedInsts_0_sextb, + decodedInsts_0_sexth, + decodedInsts_0_zexth, + decodedInsts_0_rori, + decodedInsts_0_orcb, + decodedInsts_0_rev8, + reset, + _GEN_8, + decodedInsts_0_jalr, + decodedInsts_0_beq, + decodedInsts_0_jal, + decodedInsts_0_blt, + decodedInsts_0_bge, + decodedInsts_0_bne, + decodedInsts_0_bgeu, + decodedInsts_0_ebreak, + decodedInsts_0_bltu, + decodedInsts_0_mret, + decodedInsts_0_wfi, + decodedInsts_0_ecall, + decodedInsts_0_mpause, + decodedInsts_0_mulhsu, + decodedInsts_0_mulhu, + decodedInsts_0_mul, + decodedInsts_0_mulh, + decodedInsts_0_rem, + decodedInsts_0_remu, + decodedInsts_0_div, + decodedInsts_0_divu, + decodedInsts_0_lh, + decodedInsts_0_lw, + decodedInsts_0_lb, + decodedInsts_0_lhu, + decodedInsts_0_sb, + decodedInsts_0_lbu, + decodedInsts_0_sw, + decodedInsts_0_sh, + decodedInsts_0_flushall, + _GEN_9, + decodedInsts_0_fencei, + decodedInsts_0_flushat, + decodedInsts_0_csrrs, + decodedInsts_0_csrrc, + decodedInsts_0_csrrw, + decodedInsts_1_sub, + _GEN_10, + _GEN_11, + _GEN_12, + _GEN_13, + _GEN_14, + _GEN_15, + _GEN_16, + _GEN_17, + _GEN_18, + decodedInsts_1_orn, + decodedInsts_1_xnor, + decodedInsts_1_lui, + decodedInsts_1_andn, + decodedInsts_1_ctz, + decodedInsts_1_cpop, + decodedInsts_1_clz, + decodedInsts_1_min, + decodedInsts_1_minu, + decodedInsts_1_max, + decodedInsts_1_maxu, + decodedInsts_1_rol, + decodedInsts_1_ror, + decodedInsts_1_sextb, + decodedInsts_1_sexth, + decodedInsts_1_zexth, + decodedInsts_1_rori, + decodedInsts_1_orcb, + decodedInsts_1_rev8, + decodedInsts_1_jalr, + decodedInsts_1_beq, + decodedInsts_1_jal, + decodedInsts_1_blt, + decodedInsts_1_bge, + decodedInsts_1_bne, + decodedInsts_1_bgeu, + decodedInsts_1_bltu, + decodedInsts_1_mulhsu, + decodedInsts_1_mulhu, + decodedInsts_1_mul, + decodedInsts_1_mulh, + decodedInsts_1_lh, + decodedInsts_1_lw, + decodedInsts_1_lb, + decodedInsts_1_lhu, + decodedInsts_1_sb, + decodedInsts_1_lbu, + decodedInsts_1_sw, + decodedInsts_1_sh, + decodedInsts_2_sub, + _GEN_19, + _GEN_20, + _GEN_21, + _GEN_22, + _GEN_23, + _GEN_24, + _GEN_25, + _GEN_26, + _GEN_27, + decodedInsts_2_orn, + decodedInsts_2_xnor, + decodedInsts_2_lui, + decodedInsts_2_andn, + decodedInsts_2_ctz, + decodedInsts_2_cpop, + decodedInsts_2_clz, + decodedInsts_2_min, + decodedInsts_2_minu, + decodedInsts_2_max, + decodedInsts_2_maxu, + decodedInsts_2_rol, + decodedInsts_2_ror, + decodedInsts_2_sextb, + decodedInsts_2_sexth, + decodedInsts_2_zexth, + decodedInsts_2_rori, + decodedInsts_2_orcb, + decodedInsts_2_rev8, + decodedInsts_2_jalr, + decodedInsts_2_beq, + decodedInsts_2_jal, + decodedInsts_2_blt, + decodedInsts_2_bge, + decodedInsts_2_bne, + decodedInsts_2_bgeu, + decodedInsts_2_bltu, + decodedInsts_2_mulhsu, + decodedInsts_2_mulhu, + decodedInsts_2_mul, + decodedInsts_2_mulh, + decodedInsts_2_lh, + decodedInsts_2_lw, + decodedInsts_2_lb, + decodedInsts_2_lhu, + decodedInsts_2_sb, + decodedInsts_2_lbu, + decodedInsts_2_sw, + decodedInsts_2_sh, + decodedInsts_3_sub, + _GEN_28, + _GEN_29, + _GEN_30, + _GEN_31, + _GEN_32, + _GEN_33, + _GEN_34, + _GEN_35, + _GEN_36, + decodedInsts_3_orn, + decodedInsts_3_xnor, + decodedInsts_3_lui, + decodedInsts_3_andn, + decodedInsts_3_ctz, + decodedInsts_3_cpop, + decodedInsts_3_clz, + decodedInsts_3_min, + decodedInsts_3_minu, + decodedInsts_3_max, + decodedInsts_3_maxu, + decodedInsts_3_rol, + decodedInsts_3_ror, + decodedInsts_3_sextb, + decodedInsts_3_sexth, + decodedInsts_3_zexth, + decodedInsts_3_rori, + decodedInsts_3_orcb, + decodedInsts_3_rev8, + decodedInsts_3_jalr, + decodedInsts_3_beq, + decodedInsts_3_jal, + decodedInsts_3_blt, + decodedInsts_3_bge, + decodedInsts_3_bne, + decodedInsts_3_bgeu, + decodedInsts_3_bltu, + decodedInsts_3_mulhsu, + decodedInsts_3_mulhu, + decodedInsts_3_mul, + decodedInsts_3_mulh, + decodedInsts_3_lh, + decodedInsts_3_lw, + decodedInsts_3_lb, + decodedInsts_3_lhu, + decodedInsts_3_sb, + decodedInsts_3_lbu, + decodedInsts_3_sw, + decodedInsts_3_sh, + clock +); + input decodedInsts_0_sub; + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input _GEN_3; + input _GEN_4; + input _GEN_5; + input _GEN_6; + input _GEN_7; + input decodedInsts_0_orn; + input decodedInsts_0_xnor; + input decodedInsts_0_lui; + input decodedInsts_0_andn; + input decodedInsts_0_ctz; + input decodedInsts_0_cpop; + input decodedInsts_0_clz; + input decodedInsts_0_min; + input decodedInsts_0_minu; + input decodedInsts_0_max; + input decodedInsts_0_maxu; + input decodedInsts_0_rol; + input decodedInsts_0_ror; + input decodedInsts_0_sextb; + input decodedInsts_0_sexth; + input decodedInsts_0_zexth; + input decodedInsts_0_rori; + input decodedInsts_0_orcb; + input decodedInsts_0_rev8; + input reset; + input _GEN_8; + input decodedInsts_0_jalr; + input decodedInsts_0_beq; + input decodedInsts_0_jal; + input decodedInsts_0_blt; + input decodedInsts_0_bge; + input decodedInsts_0_bne; + input decodedInsts_0_bgeu; + input decodedInsts_0_ebreak; + input decodedInsts_0_bltu; + input decodedInsts_0_mret; + input decodedInsts_0_wfi; + input decodedInsts_0_ecall; + input decodedInsts_0_mpause; + input decodedInsts_0_mulhsu; + input decodedInsts_0_mulhu; + input decodedInsts_0_mul; + input decodedInsts_0_mulh; + input decodedInsts_0_rem; + input decodedInsts_0_remu; + input decodedInsts_0_div; + input decodedInsts_0_divu; + input decodedInsts_0_lh; + input decodedInsts_0_lw; + input decodedInsts_0_lb; + input decodedInsts_0_lhu; + input decodedInsts_0_sb; + input decodedInsts_0_lbu; + input decodedInsts_0_sw; + input decodedInsts_0_sh; + input decodedInsts_0_flushall; + input _GEN_9; + input decodedInsts_0_fencei; + input decodedInsts_0_flushat; + input decodedInsts_0_csrrs; + input decodedInsts_0_csrrc; + input decodedInsts_0_csrrw; + input decodedInsts_1_sub; + input _GEN_10; + input _GEN_11; + input _GEN_12; + input _GEN_13; + input _GEN_14; + input _GEN_15; + input _GEN_16; + input _GEN_17; + input _GEN_18; + input decodedInsts_1_orn; + input decodedInsts_1_xnor; + input decodedInsts_1_lui; + input decodedInsts_1_andn; + input decodedInsts_1_ctz; + input decodedInsts_1_cpop; + input decodedInsts_1_clz; + input decodedInsts_1_min; + input decodedInsts_1_minu; + input decodedInsts_1_max; + input decodedInsts_1_maxu; + input decodedInsts_1_rol; + input decodedInsts_1_ror; + input decodedInsts_1_sextb; + input decodedInsts_1_sexth; + input decodedInsts_1_zexth; + input decodedInsts_1_rori; + input decodedInsts_1_orcb; + input decodedInsts_1_rev8; + input decodedInsts_1_jalr; + input decodedInsts_1_beq; + input decodedInsts_1_jal; + input decodedInsts_1_blt; + input decodedInsts_1_bge; + input decodedInsts_1_bne; + input decodedInsts_1_bgeu; + input decodedInsts_1_bltu; + input decodedInsts_1_mulhsu; + input decodedInsts_1_mulhu; + input decodedInsts_1_mul; + input decodedInsts_1_mulh; + input decodedInsts_1_lh; + input decodedInsts_1_lw; + input decodedInsts_1_lb; + input decodedInsts_1_lhu; + input decodedInsts_1_sb; + input decodedInsts_1_lbu; + input decodedInsts_1_sw; + input decodedInsts_1_sh; + input decodedInsts_2_sub; + input _GEN_19; + input _GEN_20; + input _GEN_21; + input _GEN_22; + input _GEN_23; + input _GEN_24; + input _GEN_25; + input _GEN_26; + input _GEN_27; + input decodedInsts_2_orn; + input decodedInsts_2_xnor; + input decodedInsts_2_lui; + input decodedInsts_2_andn; + input decodedInsts_2_ctz; + input decodedInsts_2_cpop; + input decodedInsts_2_clz; + input decodedInsts_2_min; + input decodedInsts_2_minu; + input decodedInsts_2_max; + input decodedInsts_2_maxu; + input decodedInsts_2_rol; + input decodedInsts_2_ror; + input decodedInsts_2_sextb; + input decodedInsts_2_sexth; + input decodedInsts_2_zexth; + input decodedInsts_2_rori; + input decodedInsts_2_orcb; + input decodedInsts_2_rev8; + input decodedInsts_2_jalr; + input decodedInsts_2_beq; + input decodedInsts_2_jal; + input decodedInsts_2_blt; + input decodedInsts_2_bge; + input decodedInsts_2_bne; + input decodedInsts_2_bgeu; + input decodedInsts_2_bltu; + input decodedInsts_2_mulhsu; + input decodedInsts_2_mulhu; + input decodedInsts_2_mul; + input decodedInsts_2_mulh; + input decodedInsts_2_lh; + input decodedInsts_2_lw; + input decodedInsts_2_lb; + input decodedInsts_2_lhu; + input decodedInsts_2_sb; + input decodedInsts_2_lbu; + input decodedInsts_2_sw; + input decodedInsts_2_sh; + input decodedInsts_3_sub; + input _GEN_28; + input _GEN_29; + input _GEN_30; + input _GEN_31; + input _GEN_32; + input _GEN_33; + input _GEN_34; + input _GEN_35; + input _GEN_36; + input decodedInsts_3_orn; + input decodedInsts_3_xnor; + input decodedInsts_3_lui; + input decodedInsts_3_andn; + input decodedInsts_3_ctz; + input decodedInsts_3_cpop; + input decodedInsts_3_clz; + input decodedInsts_3_min; + input decodedInsts_3_minu; + input decodedInsts_3_max; + input decodedInsts_3_maxu; + input decodedInsts_3_rol; + input decodedInsts_3_ror; + input decodedInsts_3_sextb; + input decodedInsts_3_sexth; + input decodedInsts_3_zexth; + input decodedInsts_3_rori; + input decodedInsts_3_orcb; + input decodedInsts_3_rev8; + input decodedInsts_3_jalr; + input decodedInsts_3_beq; + input decodedInsts_3_jal; + input decodedInsts_3_blt; + input decodedInsts_3_bge; + input decodedInsts_3_bne; + input decodedInsts_3_bgeu; + input decodedInsts_3_bltu; + input decodedInsts_3_mulhsu; + input decodedInsts_3_mulhu; + input decodedInsts_3_mul; + input decodedInsts_3_mulh; + input decodedInsts_3_lh; + input decodedInsts_3_lw; + input decodedInsts_3_lb; + input decodedInsts_3_lhu; + input decodedInsts_3_sb; + input decodedInsts_3_lbu; + input decodedInsts_3_sw; + input decodedInsts_3_sh; + input clock; +endmodule +module CircularBufferMulti_1_Verification_Assert ( + io_nEnqueued, + io_enqValid, + io_deqReady, + reset, + _GEN, + clock +); + input [2:0] io_nEnqueued; + input [2:0] io_enqValid; + input [2:0] io_deqReady; + input reset; + input [2:0] _GEN; + input clock; +endmodule +module LsuV2_Verification_Assert ( + reset, + opQueue_io_enqValid, + opQueue_io_nSpace, + _nextSlot_active_WIRE_3_5, + _nextSlot_active_WIRE_3_4, + _nextSlot_active_WIRE_3_7, + _nextSlot_active_WIRE_3_6, + _nextSlot_active_WIRE_3_1, + _nextSlot_active_WIRE_3_0, + _nextSlot_active_WIRE_3_3, + _nextSlot_active_WIRE_3_2, + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + lineActive_0, + lineActive_1, + wactive_1, + wactive_0, + lineActive_2, + lineActive_3, + wactive_3, + wactive_2, + lineActive_4, + lineActive_5, + wactive_5, + wactive_4, + lineActive_6, + lineActive_7, + wactive_7, + wactive_6, + lineActive_8, + lineActive_9, + wactive_9, + wactive_8, + lineActive_10, + lineActive_11, + wactive_11, + wactive_10, + lineActive_12, + lineActive_13, + wactive_13, + wactive_12, + lineActive_14, + lineActive_15, + wactive_15, + wactive_14, + _GEN_3, + _GEN_4, + _GEN_5, + _GEN_6, + _GEN_7, + _GEN_8, + _GEN_9, + io_dbus_valid, + _GEN_10, + _GEN_11, + io_rd_valid, + io_rd_flt_valid, + slot_elemWidth, + _GEN_12, + _GEN_13, + _GEN_14, + slot_active_2, + slot_active_3, + slot_active_4, + slot_active_5, + slot_active_6, + slot_active_7, + slot_active_8, + slot_active_9, + slot_active_10, + slot_active_11, + slot_active_12, + slot_active_13, + slot_active_14, + slot_active_15, + slot_vectorLoop_subvector_curr, + slot_vectorLoop_subvector_max, + slot_pendingWriteback, + faultReg_valid, + _GEN_15, + clock +); + input reset; + input [2:0] opQueue_io_enqValid; + input [2:0] opQueue_io_nSpace; + input _nextSlot_active_WIRE_3_5; + input _nextSlot_active_WIRE_3_4; + input _nextSlot_active_WIRE_3_7; + input _nextSlot_active_WIRE_3_6; + input _nextSlot_active_WIRE_3_1; + input _nextSlot_active_WIRE_3_0; + input _nextSlot_active_WIRE_3_3; + input _nextSlot_active_WIRE_3_2; + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input lineActive_0; + input lineActive_1; + input wactive_1; + input wactive_0; + input lineActive_2; + input lineActive_3; + input wactive_3; + input wactive_2; + input lineActive_4; + input lineActive_5; + input wactive_5; + input wactive_4; + input lineActive_6; + input lineActive_7; + input wactive_7; + input wactive_6; + input lineActive_8; + input lineActive_9; + input wactive_9; + input wactive_8; + input lineActive_10; + input lineActive_11; + input wactive_11; + input wactive_10; + input lineActive_12; + input lineActive_13; + input wactive_13; + input wactive_12; + input lineActive_14; + input lineActive_15; + input wactive_15; + input wactive_14; + input _GEN_3; + input _GEN_4; + input _GEN_5; + input _GEN_6; + input _GEN_7; + input _GEN_8; + input _GEN_9; + input io_dbus_valid; + input _GEN_10; + input _GEN_11; + input io_rd_valid; + input io_rd_flt_valid; + input [2:0] slot_elemWidth; + input [2:0] _GEN_12; + input [2:0] _GEN_13; + input _GEN_14; + input slot_active_2; + input slot_active_3; + input slot_active_4; + input slot_active_5; + input slot_active_6; + input slot_active_7; + input slot_active_8; + input slot_active_9; + input slot_active_10; + input slot_active_11; + input slot_active_12; + input slot_active_13; + input slot_active_14; + input slot_active_15; + input [2:0] slot_vectorLoop_subvector_curr; + input [2:0] slot_vectorLoop_subvector_max; + input slot_pendingWriteback; + input faultReg_valid; + input _GEN_15; + input clock; +endmodule +module CircularBufferMulti_2_Verification_Assert ( + io_nEnqueued, + io_enqValid, + io_deqReady, + reset, + _GEN, + clock +); + input [3:0] io_nEnqueued; + input [3:0] io_enqValid; + input [3:0] io_deqReady; + input reset; + input [3:0] _GEN; + input clock; +endmodule +module RetirementBuffer_Verification_Assert ( + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + reset, + clock +); + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input reset; + input clock; +endmodule +module Alu_Verification_Assert ( + io_rs1_valid, + _GEN, + valid, + reset, + io_rs2_valid, + _rs1Only_WIRE_5, + _rs1Only_WIRE_4, + _rs1Only_WIRE_7, + _rs1Only_WIRE_6, + _rs1Only_WIRE_1, + _rs1Only_WIRE_0, + _rs1Only_WIRE_3, + _rs1Only_WIRE_2, + clock +); + input io_rs1_valid; + input _GEN; + input valid; + input reset; + input io_rs2_valid; + input _rs1Only_WIRE_5; + input _rs1Only_WIRE_4; + input _rs1Only_WIRE_7; + input _rs1Only_WIRE_6; + input _rs1Only_WIRE_1; + input _rs1Only_WIRE_0; + input _rs1Only_WIRE_3; + input _rs1Only_WIRE_2; + input clock; +endmodule +module Bru_Verification_Assert ( + io_rs1_valid, + stateReg_valid, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_1, + _ignore_WIRE_0, + _ignore_WIRE_3, + _ignore_WIRE_2, + reset, + io_rs2_valid, + clock +); + input io_rs1_valid; + input stateReg_valid; + input _ignore_WIRE_5; + input _ignore_WIRE_4; + input _ignore_WIRE_7; + input _ignore_WIRE_6; + input _ignore_WIRE_1; + input _ignore_WIRE_0; + input _ignore_WIRE_3; + input _ignore_WIRE_2; + input reset; + input io_rs2_valid; + input clock; +endmodule +module Bru_1_Verification_Assert ( + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + reset, + io_rs1_valid, + stateReg_valid, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_1, + _ignore_WIRE_0, + _ignore_WIRE_3, + _ignore_WIRE_2, + io_rs2_valid, + clock +); + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input _GEN_3; + input reset; + input io_rs1_valid; + input stateReg_valid; + input _ignore_WIRE_5; + input _ignore_WIRE_4; + input _ignore_WIRE_7; + input _ignore_WIRE_6; + input _ignore_WIRE_1; + input _ignore_WIRE_0; + input _ignore_WIRE_3; + input _ignore_WIRE_2; + input io_rs2_valid; + input clock; +endmodule +module Mlu_Verification_Assert ( + io_rs1_0_valid, + stage2Input_q_io_deq_valid, + _GEN, + reset, + io_rs2_0_valid, + io_rs1_1_valid, + _GEN_0, + io_rs2_1_valid, + io_rs1_2_valid, + _GEN_1, + io_rs2_2_valid, + io_rs1_3_valid, + _GEN_2, + io_rs2_3_valid, + clock +); + input io_rs1_0_valid; + input stage2Input_q_io_deq_valid; + input _GEN; + input reset; + input io_rs2_0_valid; + input io_rs1_1_valid; + input _GEN_0; + input io_rs2_1_valid; + input io_rs1_2_valid; + input _GEN_1; + input io_rs2_2_valid; + input io_rs1_3_valid; + input _GEN_2; + input io_rs2_3_valid; + input clock; +endmodule +module FRegfile_Verification_Assert ( + reset, + scoreboard_error, + clock +); + input reset; + input scoreboard_error; + input clock; +endmodule +module SCore_Verification_Assert ( + csr_io_rd_valid, + alu_0_io_rd_valid, + bru_0_io_rd_valid, + reset, + _GEN, + alu_1_io_rd_valid, + bru_1_io_rd_valid, + alu_2_io_rd_valid, + bru_2_io_rd_valid, + alu_3_io_rd_valid, + bru_3_io_rd_valid, + clock +); + input csr_io_rd_valid; + input alu_0_io_rd_valid; + input bru_0_io_rd_valid; + input reset; + input _GEN; + input alu_1_io_rd_valid; + input bru_1_io_rd_valid; + input alu_2_io_rd_valid; + input bru_2_io_rd_valid; + input alu_3_io_rd_valid; + input bru_3_io_rd_valid; + input clock; +endmodule +module SRAM_Verification_Assert ( + io_fabric_writeDataAddr_valid, + io_fabric_readDataAddr_valid, + reset, + _GEN, + clock +); + input io_fabric_writeDataAddr_valid; + input io_fabric_readDataAddr_valid; + input reset; + input _GEN; + input clock; +endmodule +module FabricArbiter_Verification_Assert ( + io_source_1_readDataAddr_valid, + io_source_1_writeDataAddr_valid, + io_source_0_readDataAddr_valid, + io_source_0_writeDataAddr_valid, + reset, + clock +); + input io_source_1_readDataAddr_valid; + input io_source_1_writeDataAddr_valid; + input io_source_0_readDataAddr_valid; + input io_source_0_writeDataAddr_valid; + input reset; + input clock; +endmodule +module SRAM_1_Verification_Assert ( + io_fabric_writeDataAddr_valid, + io_fabric_readDataAddr_valid, + reset, + _GEN, + clock +); + input io_fabric_writeDataAddr_valid; + input io_fabric_readDataAddr_valid; + input reset; + input _GEN; + input clock; +endmodule +module FabricMux_Verification_Assert ( + io_source_readDataAddr_valid, + io_source_writeDataAddr_valid, + reset, + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + _GEN_4, + _GEN_5, + _GEN_6, + _GEN_7, + _GEN_8, + _GEN_9, + _GEN_10, + _GEN_11, + _GEN_12, + _GEN_13, + _GEN_14, + _GEN_15, + clock +); + input io_source_readDataAddr_valid; + input io_source_writeDataAddr_valid; + input reset; + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input _GEN_3; + input _GEN_4; + input _GEN_5; + input _GEN_6; + input _GEN_7; + input _GEN_8; + input _GEN_9; + input _GEN_10; + input _GEN_11; + input _GEN_12; + input _GEN_13; + input _GEN_14; + input _GEN_15; + input clock; +endmodule +module AxiSlave_Verification_Assert ( + readIssued_valid, + reset, + readDataQueue_io_enq_ready, + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + clock +); + input readIssued_valid; + input reset; + input readDataQueue_io_enq_ready; + input _GEN; + input _GEN_0; + input _GEN_1; + input _GEN_2; + input clock; +endmodule +module DBus2AxiV2_Verification_Assert ( + io_dbus_size, + _GEN, + io_dbus_valid, + reset, + clock +); + input [4:0] io_dbus_size; + input _GEN; + input io_dbus_valid; + input reset; + input clock; +endmodule +module RstSync ( + clk_i, + rstn_i, + clk_en, + te, + clk_o, + rstn_o +); + input clk_i; + input rstn_i; + input clk_en; + input te; + output wire clk_o; + output wire rstn_o; + localparam RST_DELAY = 2; + localparam CLK_DELAY = 2; + reg [3:0] rst_delay_reg; + always @(posedge clk_i or negedge rstn_i) + if (~rstn_i) + rst_delay_reg <= 1'sb0; + else + rst_delay_reg <= {rst_delay_reg[2:0], 1'b1}; + assign rstn_o = rst_delay_reg[1]; + wire clk_en_int; + assign clk_en_int = clk_en & rst_delay_reg[3]; + ClockGate icg( + .clk_i(clk_i), + .enable(clk_en_int), + .te(te), + .clk_o(clk_o) + ); +endmodule +module ClockGate ( + clk_i, + enable, + te, + clk_o +); + reg _sv2v_0; + input clk_i; + input enable; + input te; + output wire clk_o; + reg en_latch; + always @(*) begin + if (_sv2v_0) + ; + if (!clk_i) + en_latch = enable | te; + end + assign clk_o = en_latch & clk_i; + initial _sv2v_0 = 0; +endmodule +module Aligner_364EB ( + valid_in, + data_in, + valid_out, + data_out +); + reg _sv2v_0; + parameter N = 8; + input wire [N - 1:0] valid_in; + input wire [(N * 107) - 1:0] data_in; + output reg [N - 1:0] valid_out; + output reg [(N * 107) - 1:0] data_out; + localparam COUNTBITS = $clog2(N); + reg [COUNTBITS - 1:0] valid_count [N - 1:0]; + always @(*) begin + if (_sv2v_0) + ; + valid_count[0] = 0; + begin : sv2v_autoblock_1 + reg signed [31:0] i; + for (i = 0; i < (N - 1); i = i + 1) + valid_count[i + 1] = valid_count[i] + valid_in[i]; + end + end + reg [(N * N) - 1:0] output_valid_map; + reg [COUNTBITS - 1:0] valid_idx [N - 1:0]; + always @(*) begin + if (_sv2v_0) + ; + begin : sv2v_autoblock_2 + reg signed [31:0] o; + for (o = 0; o < N; o = o + 1) + begin + valid_idx[o] = 0; + begin : sv2v_autoblock_3 + reg signed [31:0] i; + for (i = 0; i < N; i = i + 1) + begin + output_valid_map[(o * N) + i] = (valid_count[i] == o) && valid_in[i]; + valid_idx[o] = valid_idx[o] | (output_valid_map[(o * N) + i] ? i : 0); + end + end + valid_out[o] = |output_valid_map[o * N+:N]; + data_out[o * 107+:107] = data_in[valid_idx[o] * 107+:107]; + end + end + end + initial _sv2v_0 = 0; +endmodule +module Aligner_107_4 ( + in_0_valid, + in_1_valid, + in_2_valid, + in_3_valid, + in_0_bits, + in_1_bits, + in_2_bits, + in_3_bits, + out_0_valid, + out_1_valid, + out_2_valid, + out_3_valid, + out_0_bits, + out_1_bits, + out_2_bits, + out_3_bits +); + input wire in_0_valid; + input wire in_1_valid; + input wire in_2_valid; + input wire in_3_valid; + input wire [106:0] in_0_bits; + input wire [106:0] in_1_bits; + input wire [106:0] in_2_bits; + input wire [106:0] in_3_bits; + output wire out_0_valid; + output wire out_1_valid; + output wire out_2_valid; + output wire out_3_valid; + output wire [106:0] out_0_bits; + output wire [106:0] out_1_bits; + output wire [106:0] out_2_bits; + output wire [106:0] out_3_bits; + wire [3:0] valid_in; + assign valid_in[0] = in_0_valid; + assign valid_in[1] = in_1_valid; + assign valid_in[2] = in_2_valid; + assign valid_in[3] = in_3_valid; + wire [427:0] data_in; + assign data_in[0+:107] = in_0_bits; + assign data_in[107+:107] = in_1_bits; + assign data_in[214+:107] = in_2_bits; + assign data_in[321+:107] = in_3_bits; + wire [3:0] valid_out; + assign out_0_valid = valid_out[0]; + assign out_1_valid = valid_out[1]; + assign out_2_valid = valid_out[2]; + assign out_3_valid = valid_out[3]; + wire [427:0] data_out; + assign out_0_bits = data_out[0+:107]; + assign out_1_bits = data_out[107+:107]; + assign out_2_bits = data_out[214+:107]; + assign out_3_bits = data_out[321+:107]; + Aligner_364EB #(.N(4)) aligner( + .valid_in(valid_in), + .data_in(data_in), + .valid_out(valid_out), + .data_out(data_out) + ); +endmodule +module lzc ( + in_i, + cnt_o, + empty_o +); + reg _sv2v_0; + parameter [31:0] WIDTH = 2; + parameter [0:0] MODE = 1'b0; + function automatic [31:0] cf_math_pkg_idx_width; + input reg [31:0] num_idx; + cf_math_pkg_idx_width = (num_idx > 32'd1 ? $unsigned($clog2(num_idx)) : 32'd1); + endfunction + parameter [31:0] CNT_WIDTH = cf_math_pkg_idx_width(WIDTH); + input wire [WIDTH - 1:0] in_i; + output wire [CNT_WIDTH - 1:0] cnt_o; + output wire empty_o; + generate + if (WIDTH == 1) begin : gen_degenerate_lzc + assign cnt_o[0] = !in_i[0]; + assign empty_o = !in_i[0]; + end + else begin : gen_lzc + localparam [31:0] NumLevels = $clog2(WIDTH); + wire [(WIDTH * NumLevels) - 1:0] index_lut; + wire [(2 ** NumLevels) - 1:0] sel_nodes; + wire [((2 ** NumLevels) * NumLevels) - 1:0] index_nodes; + reg [WIDTH - 1:0] in_tmp; + always @(*) begin : flip_vector + if (_sv2v_0) + ; + begin : sv2v_autoblock_1 + reg [31:0] i; + for (i = 0; i < WIDTH; i = i + 1) + in_tmp[i] = (MODE ? in_i[(WIDTH - 1) - i] : in_i[i]); + end + end + genvar _gv_j_1; + for (_gv_j_1 = 0; $unsigned(_gv_j_1) < WIDTH; _gv_j_1 = _gv_j_1 + 1) begin : g_index_lut + localparam j = _gv_j_1; + function automatic [NumLevels - 1:0] sv2v_cast_677FF; + input reg [NumLevels - 1:0] inp; + sv2v_cast_677FF = inp; + endfunction + assign index_lut[j * NumLevels+:NumLevels] = sv2v_cast_677FF($unsigned(j)); + end + genvar _gv_level_1; + for (_gv_level_1 = 0; $unsigned(_gv_level_1) < NumLevels; _gv_level_1 = _gv_level_1 + 1) begin : g_levels + localparam level = _gv_level_1; + if ($unsigned(level) == (NumLevels - 1)) begin : g_last_level + genvar _gv_k_1; + for (_gv_k_1 = 0; _gv_k_1 < (2 ** level); _gv_k_1 = _gv_k_1 + 1) begin : g_level + localparam k = _gv_k_1; + if (($unsigned(k) * 2) < (WIDTH - 1)) begin : g_reduce + assign sel_nodes[((2 ** level) - 1) + k] = in_tmp[k * 2] | in_tmp[(k * 2) + 1]; + assign index_nodes[(((2 ** level) - 1) + k) * NumLevels+:NumLevels] = (in_tmp[k * 2] == 1'b1 ? index_lut[(k * 2) * NumLevels+:NumLevels] : index_lut[((k * 2) + 1) * NumLevels+:NumLevels]); + end + if (($unsigned(k) * 2) == (WIDTH - 1)) begin : g_base + assign sel_nodes[((2 ** level) - 1) + k] = in_tmp[k * 2]; + assign index_nodes[(((2 ** level) - 1) + k) * NumLevels+:NumLevels] = index_lut[(k * 2) * NumLevels+:NumLevels]; + end + if (($unsigned(k) * 2) > (WIDTH - 1)) begin : g_out_of_range + assign sel_nodes[((2 ** level) - 1) + k] = 1'b0; + assign index_nodes[(((2 ** level) - 1) + k) * NumLevels+:NumLevels] = 1'sb0; + end + end + end + else begin : g_not_last_level + genvar _gv_l_1; + for (_gv_l_1 = 0; _gv_l_1 < (2 ** level); _gv_l_1 = _gv_l_1 + 1) begin : g_level + localparam l = _gv_l_1; + assign sel_nodes[((2 ** level) - 1) + l] = sel_nodes[((2 ** (level + 1)) - 1) + (l * 2)] | sel_nodes[(((2 ** (level + 1)) - 1) + (l * 2)) + 1]; + assign index_nodes[(((2 ** level) - 1) + l) * NumLevels+:NumLevels] = (sel_nodes[((2 ** (level + 1)) - 1) + (l * 2)] == 1'b1 ? index_nodes[(((2 ** (level + 1)) - 1) + (l * 2)) * NumLevels+:NumLevels] : index_nodes[((((2 ** (level + 1)) - 1) + (l * 2)) + 1) * NumLevels+:NumLevels]); + end + end + end + assign cnt_o = (NumLevels > $unsigned(0) ? index_nodes[0+:NumLevels] : {$clog2(WIDTH) {1'b0}}); + assign empty_o = (NumLevels > $unsigned(0) ? ~sel_nodes[0] : ~(|in_i)); + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module rr_arb_tree_3ECCC_C4496 ( + clk_i, + rst_ni, + flush_i, + rr_i, + req_i, + gnt_o, + data_i, + req_o, + gnt_i, + data_o, + idx_o +); + parameter [31:0] DataType_Width = 0; + parameter [31:0] NumIn = 64; + parameter [31:0] DataWidth = 32; + parameter [0:0] ExtPrio = 1'b0; + parameter [0:0] AxiVldRdy = 1'b0; + parameter [0:0] LockIn = 1'b0; + parameter [0:0] FairArb = 1'b1; + parameter [31:0] IdxWidth = (NumIn > 32'd1 ? $unsigned($clog2(NumIn)) : 32'd1); + input wire clk_i; + input wire rst_ni; + input wire flush_i; + input wire [IdxWidth - 1:0] rr_i; + input wire [NumIn - 1:0] req_i; + output wire [NumIn - 1:0] gnt_o; + input wire [((DataType_Width + 6) >= 0 ? (NumIn * (DataType_Width + 7)) - 1 : (NumIn * (1 - (DataType_Width + 6))) + (DataType_Width + 5)):((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6)] data_i; + output wire req_o; + input wire gnt_i; + output wire [DataType_Width + 6:0] data_o; + output wire [IdxWidth - 1:0] idx_o; + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + function automatic [((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)) - 1:0] sv2v_cast_5FCB8; + input reg [((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)) - 1:0] inp; + sv2v_cast_5FCB8 = inp; + endfunction + generate + if (NumIn == $unsigned(1)) begin : gen_pass_through + assign req_o = req_i[0]; + assign gnt_o[0] = gnt_i; + assign data_o = data_i[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + 0+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))]; + assign idx_o = 1'sb0; + end + else begin : gen_arbiter + localparam [31:0] NumLevels = $unsigned($clog2(NumIn)); + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * IdxWidth) - 1 : ((3 - (2 ** NumLevels)) * IdxWidth) + ((((2 ** NumLevels) - 2) * IdxWidth) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * IdxWidth)] index_nodes; + wire [(((2 ** NumLevels) - 2) >= 0 ? ((DataType_Width + 6) >= 0 ? (((2 ** NumLevels) - 1) * (DataType_Width + 7)) - 1 : (((2 ** NumLevels) - 1) * (1 - (DataType_Width + 6))) + (DataType_Width + 5)) : ((DataType_Width + 6) >= 0 ? ((3 - (2 ** NumLevels)) * (DataType_Width + 7)) + ((((2 ** NumLevels) - 2) * (DataType_Width + 7)) - 1) : ((3 - (2 ** NumLevels)) * (1 - (DataType_Width + 6))) + (((DataType_Width + 6) + (((2 ** NumLevels) - 2) * (1 - (DataType_Width + 6)))) - 1))):(((2 ** NumLevels) - 2) >= 0 ? ((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) : ((DataType_Width + 6) >= 0 ? ((2 ** NumLevels) - 2) * (DataType_Width + 7) : (DataType_Width + 6) + (((2 ** NumLevels) - 2) * (1 - (DataType_Width + 6)))))] data_nodes; + wire [(2 ** NumLevels) - 2:0] gnt_nodes; + wire [(2 ** NumLevels) - 2:0] req_nodes; + reg [IdxWidth - 1:0] rr_q; + wire [NumIn - 1:0] req_d; + assign req_o = req_nodes[0]; + assign data_o = data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))]; + assign idx_o = index_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * IdxWidth+:IdxWidth]; + if (ExtPrio) begin : gen_ext_rr + wire [IdxWidth:1] sv2v_tmp_0900B; + assign sv2v_tmp_0900B = rr_i; + always @(*) rr_q = sv2v_tmp_0900B; + assign req_d = req_i; + end + else begin : gen_int_rr + wire [IdxWidth - 1:0] rr_d; + if (LockIn) begin : gen_lock + wire lock_d; + reg lock_q; + reg [NumIn - 1:0] req_q; + assign lock_d = req_o & ~gnt_i; + assign req_d = (lock_q ? req_q : req_i); + always @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + if (!rst_ni) + lock_q <= 1'sb0; + else if (flush_i) + lock_q <= 1'sb0; + else + lock_q <= lock_d; + end + always @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) + req_q <= 1'sb0; + else if (flush_i) + req_q <= 1'sb0; + else + req_q <= req_d; + end + end + else begin : gen_no_lock + assign req_d = req_i; + end + if (FairArb) begin : gen_fair_arb + wire [NumIn - 1:0] upper_mask; + wire [NumIn - 1:0] lower_mask; + wire [IdxWidth - 1:0] upper_idx; + wire [IdxWidth - 1:0] lower_idx; + wire [IdxWidth - 1:0] next_idx; + wire upper_empty; + wire lower_empty; + genvar _gv_i_1; + for (_gv_i_1 = 0; _gv_i_1 < NumIn; _gv_i_1 = _gv_i_1 + 1) begin : gen_mask + localparam i = _gv_i_1; + assign upper_mask[i] = (i > rr_q ? req_d[i] : 1'b0); + assign lower_mask[i] = (i <= rr_q ? req_d[i] : 1'b0); + end + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_upper( + .in_i(upper_mask), + .cnt_o(upper_idx), + .empty_o(upper_empty) + ); + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_lower( + .in_i(lower_mask), + .cnt_o(lower_idx), + .empty_o() + ); + assign next_idx = (upper_empty ? lower_idx : upper_idx); + assign rr_d = (gnt_i && req_o ? next_idx : rr_q); + end + else begin : gen_unfair_arb + assign rr_d = (gnt_i && req_o ? (rr_q == sv2v_cast_5FDFE(NumIn - 1) ? {IdxWidth {1'sb0}} : rr_q + 1'b1) : rr_q); + end + always @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + if (!rst_ni) + rr_q <= 1'sb0; + else if (flush_i) + rr_q <= 1'sb0; + else + rr_q <= rr_d; + end + end + assign gnt_nodes[0] = gnt_i; + genvar _gv_level_2; + for (_gv_level_2 = 0; $unsigned(_gv_level_2) < NumLevels; _gv_level_2 = _gv_level_2 + 1) begin : gen_levels + localparam level = _gv_level_2; + genvar _gv_l_2; + for (_gv_l_2 = 0; _gv_l_2 < (2 ** level); _gv_l_2 = _gv_l_2 + 1) begin : gen_level + localparam l = _gv_l_2; + wire sel; + localparam [31:0] Idx0 = ((2 ** level) - 1) + l; + localparam [31:0] Idx1 = ((2 ** (level + 1)) - 1) + (l * 2); + if ($unsigned(level) == (NumLevels - 1)) begin : gen_first_level + if (($unsigned(l) * 2) < (NumIn - 1)) begin : gen_reduce + assign req_nodes[Idx0] = req_d[l * 2] | req_d[(l * 2) + 1]; + assign sel = ~req_d[l * 2] | (req_d[(l * 2) + 1] & rr_q[(NumLevels - 1) - level]); + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(sel); + assign data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))] = (sel ? data_i[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + (((l * 2) + 1) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))] : data_i[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((l * 2) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))]); + assign gnt_o[l * 2] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2])) & ~sel; + assign gnt_o[(l * 2) + 1] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[(l * 2) + 1])) & sel; + end + if (($unsigned(l) * 2) == (NumIn - 1)) begin : gen_first + assign req_nodes[Idx0] = req_d[l * 2]; + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = 1'sb0; + assign data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))] = data_i[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((l * 2) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))]; + assign gnt_o[l * 2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2]); + end + if (($unsigned(l) * 2) > (NumIn - 1)) begin : gen_out_of_range + assign req_nodes[Idx0] = 1'b0; + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(1'sb0); + assign data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))] = sv2v_cast_5FCB8(1'sb0); + end + end + else begin : gen_other_levels + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1 + 1]; + assign sel = ~req_nodes[Idx1] | (req_nodes[Idx1 + 1] & rr_q[(NumLevels - 1) - level]); + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = (sel ? sv2v_cast_5FDFE({1'b1, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]}) : sv2v_cast_5FDFE({1'b0, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]})); + assign data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))] = (sel ? data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))] : data_nodes[((DataType_Width + 6) >= 0 ? 0 : DataType_Width + 6) + ((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * ((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6)))+:((DataType_Width + 6) >= 0 ? DataType_Width + 7 : 1 - (DataType_Width + 6))]); + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + assign gnt_nodes[Idx1 + 1] = gnt_nodes[Idx0] & sel; + end + end + end + end + endgenerate +endmodule +module rr_arb_tree_A5EF3_ED1F7 ( + clk_i, + rst_ni, + flush_i, + rr_i, + req_i, + gnt_o, + data_i, + req_o, + gnt_i, + data_o, + idx_o +); + parameter [31:0] DataType_WIDTH = 0; + parameter [31:0] NumIn = 64; + parameter [31:0] DataWidth = 32; + parameter [0:0] ExtPrio = 1'b0; + parameter [0:0] AxiVldRdy = 1'b0; + parameter [0:0] LockIn = 1'b0; + parameter [0:0] FairArb = 1'b1; + parameter [31:0] IdxWidth = (NumIn > 32'd1 ? $unsigned($clog2(NumIn)) : 32'd1); + input wire clk_i; + input wire rst_ni; + input wire flush_i; + input wire [IdxWidth - 1:0] rr_i; + input wire [NumIn - 1:0] req_i; + output wire [NumIn - 1:0] gnt_o; + input wire [((DataType_WIDTH + 5) >= 0 ? (NumIn * (DataType_WIDTH + 6)) - 1 : (NumIn * (1 - (DataType_WIDTH + 5))) + (DataType_WIDTH + 4)):((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5)] data_i; + output wire req_o; + input wire gnt_i; + output wire [DataType_WIDTH + 5:0] data_o; + output wire [IdxWidth - 1:0] idx_o; + function automatic [IdxWidth - 1:0] sv2v_cast_5FDFE; + input reg [IdxWidth - 1:0] inp; + sv2v_cast_5FDFE = inp; + endfunction + function automatic [((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)) - 1:0] sv2v_cast_7B119; + input reg [((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)) - 1:0] inp; + sv2v_cast_7B119 = inp; + endfunction + generate + if (NumIn == $unsigned(1)) begin : gen_pass_through + assign req_o = req_i[0]; + assign gnt_o[0] = gnt_i; + assign data_o = data_i[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + 0+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))]; + assign idx_o = 1'sb0; + end + else begin : gen_arbiter + localparam [31:0] NumLevels = $unsigned($clog2(NumIn)); + wire [(((2 ** NumLevels) - 2) >= 0 ? (((2 ** NumLevels) - 1) * IdxWidth) - 1 : ((3 - (2 ** NumLevels)) * IdxWidth) + ((((2 ** NumLevels) - 2) * IdxWidth) - 1)):(((2 ** NumLevels) - 2) >= 0 ? 0 : ((2 ** NumLevels) - 2) * IdxWidth)] index_nodes; + wire [(((2 ** NumLevels) - 2) >= 0 ? ((DataType_WIDTH + 5) >= 0 ? (((2 ** NumLevels) - 1) * (DataType_WIDTH + 6)) - 1 : (((2 ** NumLevels) - 1) * (1 - (DataType_WIDTH + 5))) + (DataType_WIDTH + 4)) : ((DataType_WIDTH + 5) >= 0 ? ((3 - (2 ** NumLevels)) * (DataType_WIDTH + 6)) + ((((2 ** NumLevels) - 2) * (DataType_WIDTH + 6)) - 1) : ((3 - (2 ** NumLevels)) * (1 - (DataType_WIDTH + 5))) + (((DataType_WIDTH + 5) + (((2 ** NumLevels) - 2) * (1 - (DataType_WIDTH + 5)))) - 1))):(((2 ** NumLevels) - 2) >= 0 ? ((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) : ((DataType_WIDTH + 5) >= 0 ? ((2 ** NumLevels) - 2) * (DataType_WIDTH + 6) : (DataType_WIDTH + 5) + (((2 ** NumLevels) - 2) * (1 - (DataType_WIDTH + 5)))))] data_nodes; + wire [(2 ** NumLevels) - 2:0] gnt_nodes; + wire [(2 ** NumLevels) - 2:0] req_nodes; + reg [IdxWidth - 1:0] rr_q; + wire [NumIn - 1:0] req_d; + assign req_o = req_nodes[0]; + assign data_o = data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))]; + assign idx_o = index_nodes[(((2 ** NumLevels) - 2) >= 0 ? 0 : (2 ** NumLevels) - 2) * IdxWidth+:IdxWidth]; + if (ExtPrio) begin : gen_ext_rr + wire [IdxWidth:1] sv2v_tmp_0900B; + assign sv2v_tmp_0900B = rr_i; + always @(*) rr_q = sv2v_tmp_0900B; + assign req_d = req_i; + end + else begin : gen_int_rr + wire [IdxWidth - 1:0] rr_d; + if (LockIn) begin : gen_lock + wire lock_d; + reg lock_q; + reg [NumIn - 1:0] req_q; + assign lock_d = req_o & ~gnt_i; + assign req_d = (lock_q ? req_q : req_i); + always @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + if (!rst_ni) + lock_q <= 1'sb0; + else if (flush_i) + lock_q <= 1'sb0; + else + lock_q <= lock_d; + end + always @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) + req_q <= 1'sb0; + else if (flush_i) + req_q <= 1'sb0; + else + req_q <= req_d; + end + end + else begin : gen_no_lock + assign req_d = req_i; + end + if (FairArb) begin : gen_fair_arb + wire [NumIn - 1:0] upper_mask; + wire [NumIn - 1:0] lower_mask; + wire [IdxWidth - 1:0] upper_idx; + wire [IdxWidth - 1:0] lower_idx; + wire [IdxWidth - 1:0] next_idx; + wire upper_empty; + wire lower_empty; + genvar _gv_i_1; + for (_gv_i_1 = 0; _gv_i_1 < NumIn; _gv_i_1 = _gv_i_1 + 1) begin : gen_mask + localparam i = _gv_i_1; + assign upper_mask[i] = (i > rr_q ? req_d[i] : 1'b0); + assign lower_mask[i] = (i <= rr_q ? req_d[i] : 1'b0); + end + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_upper( + .in_i(upper_mask), + .cnt_o(upper_idx), + .empty_o(upper_empty) + ); + lzc #( + .WIDTH(NumIn), + .MODE(1'b0) + ) i_lzc_lower( + .in_i(lower_mask), + .cnt_o(lower_idx), + .empty_o() + ); + assign next_idx = (upper_empty ? lower_idx : upper_idx); + assign rr_d = (gnt_i && req_o ? next_idx : rr_q); + end + else begin : gen_unfair_arb + assign rr_d = (gnt_i && req_o ? (rr_q == sv2v_cast_5FDFE(NumIn - 1) ? {IdxWidth {1'sb0}} : rr_q + 1'b1) : rr_q); + end + always @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + if (!rst_ni) + rr_q <= 1'sb0; + else if (flush_i) + rr_q <= 1'sb0; + else + rr_q <= rr_d; + end + end + assign gnt_nodes[0] = gnt_i; + genvar _gv_level_2; + for (_gv_level_2 = 0; $unsigned(_gv_level_2) < NumLevels; _gv_level_2 = _gv_level_2 + 1) begin : gen_levels + localparam level = _gv_level_2; + genvar _gv_l_2; + for (_gv_l_2 = 0; _gv_l_2 < (2 ** level); _gv_l_2 = _gv_l_2 + 1) begin : gen_level + localparam l = _gv_l_2; + wire sel; + localparam [31:0] Idx0 = ((2 ** level) - 1) + l; + localparam [31:0] Idx1 = ((2 ** (level + 1)) - 1) + (l * 2); + if ($unsigned(level) == (NumLevels - 1)) begin : gen_first_level + if (($unsigned(l) * 2) < (NumIn - 1)) begin : gen_reduce + assign req_nodes[Idx0] = req_d[l * 2] | req_d[(l * 2) + 1]; + assign sel = ~req_d[l * 2] | (req_d[(l * 2) + 1] & rr_q[(NumLevels - 1) - level]); + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(sel); + assign data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))] = (sel ? data_i[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + (((l * 2) + 1) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))] : data_i[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((l * 2) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))]); + assign gnt_o[l * 2] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2])) & ~sel; + assign gnt_o[(l * 2) + 1] = (gnt_nodes[Idx0] & (AxiVldRdy | req_d[(l * 2) + 1])) & sel; + end + if (($unsigned(l) * 2) == (NumIn - 1)) begin : gen_first + assign req_nodes[Idx0] = req_d[l * 2]; + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = 1'sb0; + assign data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))] = data_i[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((l * 2) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))]; + assign gnt_o[l * 2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l * 2]); + end + if (($unsigned(l) * 2) > (NumIn - 1)) begin : gen_out_of_range + assign req_nodes[Idx0] = 1'b0; + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = sv2v_cast_5FDFE(1'sb0); + assign data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))] = sv2v_cast_7B119(1'sb0); + end + end + else begin : gen_other_levels + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1 + 1]; + assign sel = ~req_nodes[Idx1] | (req_nodes[Idx1 + 1] & rr_q[(NumLevels - 1) - level]); + assign index_nodes[(((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * IdxWidth+:IdxWidth] = (sel ? sv2v_cast_5FDFE({1'b1, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]}) : sv2v_cast_5FDFE({1'b0, index_nodes[((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * IdxWidth) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 2 : (((NumLevels - $unsigned(level)) - 2) + (((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))) - 1)-:(((NumLevels - $unsigned(level)) - 2) >= 0 ? (NumLevels - $unsigned(level)) - 1 : 3 - (NumLevels - $unsigned(level)))]})); + assign data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? Idx0 : ((2 ** NumLevels) - 2) - Idx0) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))] = (sel ? data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? Idx1 + 1 : ((2 ** NumLevels) - 2) - (Idx1 + 1)) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))] : data_nodes[((DataType_WIDTH + 5) >= 0 ? 0 : DataType_WIDTH + 5) + ((((2 ** NumLevels) - 2) >= 0 ? Idx1 : ((2 ** NumLevels) - 2) - Idx1) * ((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5)))+:((DataType_WIDTH + 5) >= 0 ? DataType_WIDTH + 6 : 1 - (DataType_WIDTH + 5))]); + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + assign gnt_nodes[Idx1 + 1] = gnt_nodes[Idx0] & sel; + end + end + end + end + endgenerate +endmodule +module fpnew_cast_multi_2E827_67072 ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + src_fmt_i, + dst_fmt_i, + int_fmt_i, + tag_i, + mask_i, + aux_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + mask_o, + aux_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + parameter [31:0] AuxType_AUX_BITS = 0; + reg _sv2v_0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + parameter [0:4] FpFmtConfig = 1'sb1; + localparam [31:0] fpnew_pkg_NUM_INT_FORMATS = 4; + parameter [0:3] IntFmtConfig = 1'sb1; + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + function automatic signed [31:0] fpnew_pkg_maximum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_maximum = (a > b ? a : b); + endfunction + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + function automatic [31:0] fpnew_pkg_max_fp_width; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_1 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) + res = $unsigned(fpnew_pkg_maximum(res, fpnew_pkg_fp_width(sv2v_cast_5D882(i)))); + end + fpnew_pkg_max_fp_width = res; + end + endfunction + localparam [31:0] fpnew_pkg_INT_FORMAT_BITS = 2; + function automatic [1:0] sv2v_cast_CDB06; + input reg [1:0] inp; + sv2v_cast_CDB06 = inp; + endfunction + function automatic [31:0] fpnew_pkg_int_width; + input reg [1:0] ifmt; + (* full_case, parallel_case *) + case (ifmt) + sv2v_cast_CDB06(0): fpnew_pkg_int_width = 8; + sv2v_cast_CDB06(1): fpnew_pkg_int_width = 16; + sv2v_cast_CDB06(2): fpnew_pkg_int_width = 32; + sv2v_cast_CDB06(3): fpnew_pkg_int_width = 64; + default: begin + fpnew_pkg_int_width = sv2v_cast_CDB06(0); + end + endcase + endfunction + function automatic [31:0] fpnew_pkg_max_int_width; + input reg [0:3] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_2 + reg signed [31:0] ifmt; + for (ifmt = 0; ifmt < fpnew_pkg_NUM_INT_FORMATS; ifmt = ifmt + 1) + if (cfg[ifmt]) + res = fpnew_pkg_maximum(res, fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt))); + end + fpnew_pkg_max_int_width = res; + end + endfunction + localparam [31:0] WIDTH = fpnew_pkg_maximum(fpnew_pkg_max_fp_width(FpFmtConfig), fpnew_pkg_max_int_width(IntFmtConfig)); + localparam [31:0] NUM_FORMATS = fpnew_pkg_NUM_FP_FORMATS; + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [WIDTH - 1:0] operands_i; + input wire [4:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire [2:0] src_fmt_i; + input wire [2:0] dst_fmt_i; + input wire [1:0] int_fmt_i; + input wire tag_i; + input wire mask_i; + input wire [AuxType_AUX_BITS - 1:0] aux_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [WIDTH - 1:0] result_o; + output wire [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire mask_o; + output wire [AuxType_AUX_BITS - 1:0] aux_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + localparam [31:0] NUM_INT_FORMATS = fpnew_pkg_NUM_INT_FORMATS; + localparam [31:0] MAX_INT_WIDTH = fpnew_pkg_max_int_width(IntFmtConfig); + function automatic [31:0] fpnew_pkg_exp_bits; + input reg [2:0] fmt; + fpnew_pkg_exp_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32]; + endfunction + function automatic [31:0] fpnew_pkg_man_bits; + input reg [2:0] fmt; + fpnew_pkg_man_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]; + endfunction + function automatic [63:0] fpnew_pkg_super_format; + input reg [0:4] cfg; + reg [63:0] res; + begin + res = 1'sb0; + begin : sv2v_autoblock_3 + reg [31:0] fmt; + for (fmt = 0; fmt < fpnew_pkg_NUM_FP_FORMATS; fmt = fmt + 1) + if (cfg[fmt]) begin + res[63-:32] = $unsigned(fpnew_pkg_maximum(res[63-:32], fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)))); + res[31-:32] = $unsigned(fpnew_pkg_maximum(res[31-:32], fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)))); + end + end + fpnew_pkg_super_format = res; + end + endfunction + localparam [63:0] SUPER_FORMAT = fpnew_pkg_super_format(FpFmtConfig); + localparam [31:0] SUPER_EXP_BITS = SUPER_FORMAT[63-:32]; + localparam [31:0] SUPER_MAN_BITS = SUPER_FORMAT[31-:32]; + localparam [31:0] SUPER_BIAS = (2 ** (SUPER_EXP_BITS - 1)) - 1; + localparam [31:0] INT_MAN_WIDTH = fpnew_pkg_maximum(SUPER_MAN_BITS + 1, MAX_INT_WIDTH); + localparam [31:0] LZC_RESULT_WIDTH = $clog2(INT_MAN_WIDTH); + localparam [31:0] INT_EXP_WIDTH = fpnew_pkg_maximum($clog2(MAX_INT_WIDTH), fpnew_pkg_maximum(SUPER_EXP_BITS, $clog2(SUPER_BIAS + SUPER_MAN_BITS))) + 1; + localparam NUM_INP_REGS = (PipeConfig == 2'd0 ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 1) / 3 : 0)); + localparam NUM_MID_REGS = (PipeConfig == 2'd2 ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 2) / 3 : 0)); + localparam NUM_OUT_REGS = (PipeConfig == 2'd1 ? NumPipeRegs : (PipeConfig == 2'd3 ? NumPipeRegs / 3 : 0)); + wire [WIDTH - 1:0] operands_q; + wire [4:0] is_boxed_q; + wire op_mod_q; + wire [2:0] src_fmt_q; + wire [2:0] dst_fmt_q; + wire [1:0] int_fmt_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * WIDTH) + ((NUM_INP_REGS * WIDTH) - 1) : ((NUM_INP_REGS + 1) * WIDTH) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * WIDTH : 0)] inp_pipe_operands_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0)] inp_pipe_is_boxed_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)] inp_pipe_rnd_mode_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_OP_BITS) + ((NUM_INP_REGS * fpnew_pkg_OP_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_OP_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_OP_BITS : 0)] inp_pipe_op_q; + reg [0:NUM_INP_REGS] inp_pipe_op_mod_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] inp_pipe_src_fmt_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] inp_pipe_dst_fmt_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_INT_FORMAT_BITS) + ((NUM_INP_REGS * fpnew_pkg_INT_FORMAT_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_INT_FORMAT_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_INT_FORMAT_BITS : 0)] inp_pipe_int_fmt_q; + reg [0:NUM_INP_REGS] inp_pipe_tag_q; + reg [0:NUM_INP_REGS] inp_pipe_mask_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * AuxType_AUX_BITS) + ((NUM_INP_REGS * AuxType_AUX_BITS) - 1) : ((NUM_INP_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * AuxType_AUX_BITS : 0)] inp_pipe_aux_q; + reg [0:NUM_INP_REGS] inp_pipe_valid_q; + wire [0:NUM_INP_REGS] inp_pipe_ready; + wire [WIDTH * 1:1] sv2v_tmp_933AE; + assign sv2v_tmp_933AE = operands_i; + always @(*) inp_pipe_operands_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * WIDTH+:WIDTH] = sv2v_tmp_933AE; + wire [5:1] sv2v_tmp_7038A; + assign sv2v_tmp_7038A = is_boxed_i; + always @(*) inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * NUM_FORMATS+:NUM_FORMATS] = sv2v_tmp_7038A; + wire [3:1] sv2v_tmp_AA272; + assign sv2v_tmp_AA272 = rnd_mode_i; + always @(*) inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3+:3] = sv2v_tmp_AA272; + wire [4:1] sv2v_tmp_14A3A; + assign sv2v_tmp_14A3A = op_i; + always @(*) inp_pipe_op_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] = sv2v_tmp_14A3A; + wire [1:1] sv2v_tmp_72E02; + assign sv2v_tmp_72E02 = op_mod_i; + always @(*) inp_pipe_op_mod_q[0] = sv2v_tmp_72E02; + wire [3:1] sv2v_tmp_8EF42; + assign sv2v_tmp_8EF42 = src_fmt_i; + always @(*) inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_8EF42; + wire [3:1] sv2v_tmp_B0F12; + assign sv2v_tmp_B0F12 = dst_fmt_i; + always @(*) inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_B0F12; + wire [2:1] sv2v_tmp_C9BC4; + assign sv2v_tmp_C9BC4 = int_fmt_i; + always @(*) inp_pipe_int_fmt_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] = sv2v_tmp_C9BC4; + wire [1:1] sv2v_tmp_DE624; + assign sv2v_tmp_DE624 = tag_i; + always @(*) inp_pipe_tag_q[0] = sv2v_tmp_DE624; + wire [1:1] sv2v_tmp_AE6A6; + assign sv2v_tmp_AE6A6 = mask_i; + always @(*) inp_pipe_mask_q[0] = sv2v_tmp_AE6A6; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_47FF6; + assign sv2v_tmp_47FF6 = aux_i; + always @(*) inp_pipe_aux_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_47FF6; + wire [1:1] sv2v_tmp_CFC25; + assign sv2v_tmp_CFC25 = in_valid_i; + always @(*) inp_pipe_valid_q[0] = sv2v_tmp_CFC25; + assign in_ready_o = inp_pipe_ready[0]; + genvar _gv_i_2; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + function automatic [AuxType_AUX_BITS - 1:0] sv2v_cast_533F1; + input reg [AuxType_AUX_BITS - 1:0] inp; + sv2v_cast_533F1 = inp; + endfunction + generate + for (_gv_i_2 = 0; _gv_i_2 < NUM_INP_REGS; _gv_i_2 = _gv_i_2 + 1) begin : gen_input_pipeline + localparam i = _gv_i_2; + wire reg_ena; + assign inp_pipe_ready[i] = inp_pipe_ready[i + 1] | ~inp_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_valid_q[i + 1] <= 1'b0; + else + inp_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (inp_pipe_ready[i] ? inp_pipe_valid_q[i] : inp_pipe_valid_q[i + 1])); + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_operands_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * WIDTH+:WIDTH] <= 1'sb0; + else + inp_pipe_operands_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * WIDTH+:WIDTH] <= (reg_ena ? inp_pipe_operands_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * WIDTH+:WIDTH] : inp_pipe_operands_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * WIDTH+:WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS+:NUM_FORMATS] <= 1'sb0; + else + inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS+:NUM_FORMATS] <= (reg_ena ? inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * NUM_FORMATS+:NUM_FORMATS] : inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS+:NUM_FORMATS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= (reg_ena ? inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3+:3] : inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= sv2v_cast_4CD2E(0); + else + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= (reg_ena ? inp_pipe_op_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] : inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_mod_q[i + 1] <= 1'sb0; + else + inp_pipe_op_mod_q[i + 1] <= (reg_ena ? inp_pipe_op_mod_q[i] : inp_pipe_op_mod_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_int_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] <= sv2v_cast_CDB06(0); + else + inp_pipe_int_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] <= (reg_ena ? inp_pipe_int_fmt_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] : inp_pipe_int_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_tag_q[i + 1] <= 1'b0; + else + inp_pipe_tag_q[i + 1] <= (reg_ena ? inp_pipe_tag_q[i] : inp_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_mask_q[i + 1] <= 1'sb0; + else + inp_pipe_mask_q[i + 1] <= (reg_ena ? inp_pipe_mask_q[i] : inp_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign operands_q = inp_pipe_operands_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * WIDTH+:WIDTH]; + assign is_boxed_q = inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * NUM_FORMATS+:NUM_FORMATS]; + assign op_mod_q = inp_pipe_op_mod_q[NUM_INP_REGS]; + assign src_fmt_q = inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign int_fmt_q = inp_pipe_int_fmt_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS]; + wire src_is_int; + wire dst_is_int; + assign src_is_int = inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] == sv2v_cast_4CD2E(12); + assign dst_is_int = inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] == sv2v_cast_4CD2E(11); + wire [INT_MAN_WIDTH - 1:0] encoded_mant; + wire [4:0] fmt_sign; + wire signed [(NUM_FORMATS * INT_EXP_WIDTH) - 1:0] fmt_exponent; + wire [(NUM_FORMATS * INT_MAN_WIDTH) - 1:0] fmt_mantissa; + wire signed [(NUM_FORMATS * INT_EXP_WIDTH) - 1:0] fmt_shift_compensation; + wire [39:0] info; + reg [(NUM_INT_FORMATS * INT_MAN_WIDTH) - 1:0] ifmt_input_val; + wire int_sign; + wire [INT_MAN_WIDTH - 1:0] int_value; + wire [INT_MAN_WIDTH - 1:0] int_mantissa; + genvar _gv_fmt_1; + localparam [0:0] fpnew_pkg_DONT_CARE = 1'b1; + function automatic signed [0:0] sv2v_cast_1_signed; + input reg signed [0:0] inp; + sv2v_cast_1_signed = inp; + endfunction + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + generate + for (_gv_fmt_1 = 0; _gv_fmt_1 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_1 = _gv_fmt_1 + 1) begin : fmt_init_inputs + localparam fmt = _gv_fmt_1; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + if (FpFmtConfig[fmt]) begin : active_format + localparam [2:0] FpFormat = sv2v_cast_5D882(fmt); + fpnew_classifier #( + .FpFormat(FpFormat), + .NumOperands(1) + ) i_fpnew_classifier( + .operands_i(operands_q[FP_WIDTH - 1:0]), + .is_boxed_i(is_boxed_q[fmt]), + .info_o(info[fmt * 8+:8]) + ); + assign fmt_sign[fmt] = operands_q[FP_WIDTH - 1]; + assign fmt_exponent[fmt * INT_EXP_WIDTH+:INT_EXP_WIDTH] = $signed({1'b0, operands_q[MAN_BITS+:EXP_BITS]}); + assign fmt_mantissa[fmt * INT_MAN_WIDTH+:INT_MAN_WIDTH] = {info[(fmt * 8) + 7], operands_q[MAN_BITS - 1:0]}; + assign fmt_shift_compensation[fmt * INT_EXP_WIDTH+:INT_EXP_WIDTH] = $signed((INT_MAN_WIDTH - 1) - MAN_BITS); + end + else begin : inactive_format + assign info[fmt * 8+:8] = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + assign fmt_sign[fmt] = fpnew_pkg_DONT_CARE; + assign fmt_exponent[fmt * INT_EXP_WIDTH+:INT_EXP_WIDTH] = {INT_EXP_WIDTH {sv2v_cast_1_signed(fpnew_pkg_DONT_CARE)}}; + assign fmt_mantissa[fmt * INT_MAN_WIDTH+:INT_MAN_WIDTH] = {INT_MAN_WIDTH {fpnew_pkg_DONT_CARE}}; + assign fmt_shift_compensation[fmt * INT_EXP_WIDTH+:INT_EXP_WIDTH] = {INT_EXP_WIDTH {sv2v_cast_1_signed(fpnew_pkg_DONT_CARE)}}; + end + end + endgenerate + genvar _gv_ifmt_1; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + generate + for (_gv_ifmt_1 = 0; _gv_ifmt_1 < sv2v_cast_32_signed(NUM_INT_FORMATS); _gv_ifmt_1 = _gv_ifmt_1 + 1) begin : gen_sign_extend_int + localparam ifmt = _gv_ifmt_1; + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if (IntFmtConfig[ifmt]) begin : active_format + always @(*) begin : sign_ext_input + if (_sv2v_0) + ; + ifmt_input_val[ifmt * INT_MAN_WIDTH+:INT_MAN_WIDTH] = {INT_MAN_WIDTH {sv2v_cast_1(operands_q[INT_WIDTH - 1] & ~op_mod_q)}}; + ifmt_input_val[(ifmt * INT_MAN_WIDTH) + (INT_WIDTH - 1)-:INT_WIDTH] = operands_q[INT_WIDTH - 1:0]; + end + end + else begin : inactive_format + wire [INT_MAN_WIDTH * 1:1] sv2v_tmp_F208D; + assign sv2v_tmp_F208D = {INT_MAN_WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) ifmt_input_val[ifmt * INT_MAN_WIDTH+:INT_MAN_WIDTH] = sv2v_tmp_F208D; + end + end + endgenerate + assign int_value = ifmt_input_val[int_fmt_q * INT_MAN_WIDTH+:INT_MAN_WIDTH]; + assign int_sign = int_value[INT_MAN_WIDTH - 1] & ~op_mod_q; + assign int_mantissa = (int_sign ? $unsigned(-int_value) : int_value); + assign encoded_mant = (src_is_int ? int_mantissa : fmt_mantissa[src_fmt_q * INT_MAN_WIDTH+:INT_MAN_WIDTH]); + wire signed [INT_EXP_WIDTH - 1:0] src_bias; + wire signed [INT_EXP_WIDTH - 1:0] src_exp; + wire signed [INT_EXP_WIDTH - 1:0] src_subnormal; + wire signed [INT_EXP_WIDTH - 1:0] src_offset; + function automatic [31:0] fpnew_pkg_bias; + input reg [2:0] fmt; + fpnew_pkg_bias = $unsigned((2 ** (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] - 1)) - 1); + endfunction + assign src_bias = $signed(fpnew_pkg_bias(src_fmt_q)); + assign src_exp = fmt_exponent[src_fmt_q * INT_EXP_WIDTH+:INT_EXP_WIDTH]; + assign src_subnormal = $signed({1'b0, info[(src_fmt_q * 8) + 6]}); + assign src_offset = fmt_shift_compensation[src_fmt_q * INT_EXP_WIDTH+:INT_EXP_WIDTH]; + wire input_sign; + wire signed [INT_EXP_WIDTH - 1:0] input_exp; + wire [INT_MAN_WIDTH - 1:0] input_mant; + wire mant_is_zero; + wire signed [INT_EXP_WIDTH - 1:0] fp_input_exp; + wire signed [INT_EXP_WIDTH - 1:0] int_input_exp; + wire [LZC_RESULT_WIDTH - 1:0] renorm_shamt; + wire [LZC_RESULT_WIDTH:0] renorm_shamt_sgn; + lzc #( + .WIDTH(INT_MAN_WIDTH), + .MODE(1) + ) i_lzc( + .in_i(encoded_mant), + .cnt_o(renorm_shamt), + .empty_o(mant_is_zero) + ); + assign renorm_shamt_sgn = $signed({1'b0, renorm_shamt}); + assign input_sign = (src_is_int ? int_sign : fmt_sign[src_fmt_q]); + assign input_mant = encoded_mant << renorm_shamt; + assign fp_input_exp = $signed((((src_exp + src_subnormal) - src_bias) - renorm_shamt_sgn) + src_offset); + assign int_input_exp = $signed((INT_MAN_WIDTH - 1) - renorm_shamt_sgn); + assign input_exp = (src_is_int ? int_input_exp : fp_input_exp); + wire signed [INT_EXP_WIDTH - 1:0] destination_exp; + assign destination_exp = input_exp + $signed(fpnew_pkg_bias(dst_fmt_q)); + wire input_sign_q; + wire signed [INT_EXP_WIDTH - 1:0] input_exp_q; + wire [INT_MAN_WIDTH - 1:0] input_mant_q; + wire signed [INT_EXP_WIDTH - 1:0] destination_exp_q; + wire src_is_int_q; + wire dst_is_int_q; + wire [7:0] info_q; + wire mant_is_zero_q; + wire op_mod_q2; + wire [2:0] rnd_mode_q; + wire [2:0] src_fmt_q2; + wire [2:0] dst_fmt_q2; + wire [1:0] int_fmt_q2; + reg [0:NUM_MID_REGS] mid_pipe_input_sign_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * INT_EXP_WIDTH) + ((NUM_MID_REGS * INT_EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * INT_EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * INT_EXP_WIDTH : 0)] mid_pipe_input_exp_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * INT_MAN_WIDTH) + ((NUM_MID_REGS * INT_MAN_WIDTH) - 1) : ((NUM_MID_REGS + 1) * INT_MAN_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * INT_MAN_WIDTH : 0)] mid_pipe_input_mant_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * INT_EXP_WIDTH) + ((NUM_MID_REGS * INT_EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * INT_EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * INT_EXP_WIDTH : 0)] mid_pipe_dest_exp_q; + reg [0:NUM_MID_REGS] mid_pipe_src_is_int_q; + reg [0:NUM_MID_REGS] mid_pipe_dst_is_int_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * 8) + ((NUM_MID_REGS * 8) - 1) : ((NUM_MID_REGS + 1) * 8) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * 8 : 0)] mid_pipe_info_q; + reg [0:NUM_MID_REGS] mid_pipe_mant_zero_q; + reg [0:NUM_MID_REGS] mid_pipe_op_mod_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * 3) + ((NUM_MID_REGS * 3) - 1) : ((NUM_MID_REGS + 1) * 3) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * 3 : 0)] mid_pipe_rnd_mode_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_MID_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_MID_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] mid_pipe_src_fmt_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_MID_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_MID_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] mid_pipe_dst_fmt_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * fpnew_pkg_INT_FORMAT_BITS) + ((NUM_MID_REGS * fpnew_pkg_INT_FORMAT_BITS) - 1) : ((NUM_MID_REGS + 1) * fpnew_pkg_INT_FORMAT_BITS) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * fpnew_pkg_INT_FORMAT_BITS : 0)] mid_pipe_int_fmt_q; + reg [0:NUM_MID_REGS] mid_pipe_tag_q; + reg [0:NUM_MID_REGS] mid_pipe_mask_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * AuxType_AUX_BITS) + ((NUM_MID_REGS * AuxType_AUX_BITS) - 1) : ((NUM_MID_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * AuxType_AUX_BITS : 0)] mid_pipe_aux_q; + reg [0:NUM_MID_REGS] mid_pipe_valid_q; + wire [0:NUM_MID_REGS] mid_pipe_ready; + wire [1:1] sv2v_tmp_73C39; + assign sv2v_tmp_73C39 = input_sign; + always @(*) mid_pipe_input_sign_q[0] = sv2v_tmp_73C39; + wire [INT_EXP_WIDTH * 1:1] sv2v_tmp_D63AF; + assign sv2v_tmp_D63AF = input_exp; + always @(*) mid_pipe_input_exp_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * INT_EXP_WIDTH+:INT_EXP_WIDTH] = sv2v_tmp_D63AF; + wire [INT_MAN_WIDTH * 1:1] sv2v_tmp_CED01; + assign sv2v_tmp_CED01 = input_mant; + always @(*) mid_pipe_input_mant_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * INT_MAN_WIDTH+:INT_MAN_WIDTH] = sv2v_tmp_CED01; + wire [INT_EXP_WIDTH * 1:1] sv2v_tmp_5026E; + assign sv2v_tmp_5026E = destination_exp; + always @(*) mid_pipe_dest_exp_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * INT_EXP_WIDTH+:INT_EXP_WIDTH] = sv2v_tmp_5026E; + wire [1:1] sv2v_tmp_6F1F9; + assign sv2v_tmp_6F1F9 = src_is_int; + always @(*) mid_pipe_src_is_int_q[0] = sv2v_tmp_6F1F9; + wire [1:1] sv2v_tmp_202B9; + assign sv2v_tmp_202B9 = dst_is_int; + always @(*) mid_pipe_dst_is_int_q[0] = sv2v_tmp_202B9; + wire [8:1] sv2v_tmp_C577A; + assign sv2v_tmp_C577A = info[src_fmt_q * 8+:8]; + always @(*) mid_pipe_info_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * 8+:8] = sv2v_tmp_C577A; + wire [1:1] sv2v_tmp_CCDAF; + assign sv2v_tmp_CCDAF = mant_is_zero; + always @(*) mid_pipe_mant_zero_q[0] = sv2v_tmp_CCDAF; + wire [1:1] sv2v_tmp_0DC3D; + assign sv2v_tmp_0DC3D = op_mod_q; + always @(*) mid_pipe_op_mod_q[0] = sv2v_tmp_0DC3D; + wire [3:1] sv2v_tmp_EC44B; + assign sv2v_tmp_EC44B = inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]; + always @(*) mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * 3+:3] = sv2v_tmp_EC44B; + wire [3:1] sv2v_tmp_8D32D; + assign sv2v_tmp_8D32D = src_fmt_q; + always @(*) mid_pipe_src_fmt_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_8D32D; + wire [3:1] sv2v_tmp_9DD7D; + assign sv2v_tmp_9DD7D = dst_fmt_q; + always @(*) mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_9DD7D; + wire [2:1] sv2v_tmp_5CA4B; + assign sv2v_tmp_5CA4B = int_fmt_q; + always @(*) mid_pipe_int_fmt_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] = sv2v_tmp_5CA4B; + wire [1:1] sv2v_tmp_7259D; + assign sv2v_tmp_7259D = inp_pipe_tag_q[NUM_INP_REGS]; + always @(*) mid_pipe_tag_q[0] = sv2v_tmp_7259D; + wire [1:1] sv2v_tmp_FAFEF; + assign sv2v_tmp_FAFEF = inp_pipe_mask_q[NUM_INP_REGS]; + always @(*) mid_pipe_mask_q[0] = sv2v_tmp_FAFEF; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_E40B9; + assign sv2v_tmp_E40B9 = inp_pipe_aux_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + always @(*) mid_pipe_aux_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_E40B9; + wire [1:1] sv2v_tmp_C7159; + assign sv2v_tmp_C7159 = inp_pipe_valid_q[NUM_INP_REGS]; + always @(*) mid_pipe_valid_q[0] = sv2v_tmp_C7159; + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + genvar _gv_i_3; + generate + for (_gv_i_3 = 0; _gv_i_3 < NUM_MID_REGS; _gv_i_3 = _gv_i_3 + 1) begin : gen_inside_pipeline + localparam i = _gv_i_3; + wire reg_ena; + assign mid_pipe_ready[i] = mid_pipe_ready[i + 1] | ~mid_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_valid_q[i + 1] <= 1'b0; + else + mid_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (mid_pipe_ready[i] ? mid_pipe_valid_q[i] : mid_pipe_valid_q[i + 1])); + assign reg_ena = (mid_pipe_ready[i] & mid_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_input_sign_q[i + 1] <= 1'sb0; + else + mid_pipe_input_sign_q[i + 1] <= (reg_ena ? mid_pipe_input_sign_q[i] : mid_pipe_input_sign_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_input_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_EXP_WIDTH+:INT_EXP_WIDTH] <= 1'sb0; + else + mid_pipe_input_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_EXP_WIDTH+:INT_EXP_WIDTH] <= (reg_ena ? mid_pipe_input_exp_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * INT_EXP_WIDTH+:INT_EXP_WIDTH] : mid_pipe_input_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_EXP_WIDTH+:INT_EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_input_mant_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_MAN_WIDTH+:INT_MAN_WIDTH] <= 1'sb0; + else + mid_pipe_input_mant_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_MAN_WIDTH+:INT_MAN_WIDTH] <= (reg_ena ? mid_pipe_input_mant_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * INT_MAN_WIDTH+:INT_MAN_WIDTH] : mid_pipe_input_mant_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_MAN_WIDTH+:INT_MAN_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_dest_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_EXP_WIDTH+:INT_EXP_WIDTH] <= 1'sb0; + else + mid_pipe_dest_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_EXP_WIDTH+:INT_EXP_WIDTH] <= (reg_ena ? mid_pipe_dest_exp_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * INT_EXP_WIDTH+:INT_EXP_WIDTH] : mid_pipe_dest_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * INT_EXP_WIDTH+:INT_EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_src_is_int_q[i + 1] <= 1'sb0; + else + mid_pipe_src_is_int_q[i + 1] <= (reg_ena ? mid_pipe_src_is_int_q[i] : mid_pipe_src_is_int_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_dst_is_int_q[i + 1] <= 1'sb0; + else + mid_pipe_dst_is_int_q[i + 1] <= (reg_ena ? mid_pipe_dst_is_int_q[i] : mid_pipe_dst_is_int_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_info_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 8+:8] <= 1'sb0; + else + mid_pipe_info_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 8+:8] <= (reg_ena ? mid_pipe_info_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * 8+:8] : mid_pipe_info_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 8+:8]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_mant_zero_q[i + 1] <= 1'sb0; + else + mid_pipe_mant_zero_q[i + 1] <= (reg_ena ? mid_pipe_mant_zero_q[i] : mid_pipe_mant_zero_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_op_mod_q[i + 1] <= 1'sb0; + else + mid_pipe_op_mod_q[i + 1] <= (reg_ena ? mid_pipe_op_mod_q[i] : mid_pipe_op_mod_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3] <= (reg_ena ? mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * 3+:3] : mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_src_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + mid_pipe_src_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? mid_pipe_src_fmt_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : mid_pipe_src_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_int_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] <= sv2v_cast_CDB06(0); + else + mid_pipe_int_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] <= (reg_ena ? mid_pipe_int_fmt_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS] : mid_pipe_int_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_tag_q[i + 1] <= 1'b0; + else + mid_pipe_tag_q[i + 1] <= (reg_ena ? mid_pipe_tag_q[i] : mid_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_mask_q[i + 1] <= 1'sb0; + else + mid_pipe_mask_q[i + 1] <= (reg_ena ? mid_pipe_mask_q[i] : mid_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign input_sign_q = mid_pipe_input_sign_q[NUM_MID_REGS]; + assign input_exp_q = mid_pipe_input_exp_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * INT_EXP_WIDTH+:INT_EXP_WIDTH]; + assign input_mant_q = mid_pipe_input_mant_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * INT_MAN_WIDTH+:INT_MAN_WIDTH]; + assign destination_exp_q = mid_pipe_dest_exp_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * INT_EXP_WIDTH+:INT_EXP_WIDTH]; + assign src_is_int_q = mid_pipe_src_is_int_q[NUM_MID_REGS]; + assign dst_is_int_q = mid_pipe_dst_is_int_q[NUM_MID_REGS]; + assign info_q = mid_pipe_info_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * 8+:8]; + assign mant_is_zero_q = mid_pipe_mant_zero_q[NUM_MID_REGS]; + assign op_mod_q2 = mid_pipe_op_mod_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * 3+:3]; + assign src_fmt_q2 = mid_pipe_src_fmt_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign int_fmt_q2 = mid_pipe_int_fmt_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * fpnew_pkg_INT_FORMAT_BITS+:fpnew_pkg_INT_FORMAT_BITS]; + reg [INT_EXP_WIDTH - 1:0] final_exp; + reg [2 * INT_MAN_WIDTH:0] preshift_mant; + wire [2 * INT_MAN_WIDTH:0] destination_mant; + wire [SUPER_MAN_BITS - 1:0] final_mant; + wire [MAX_INT_WIDTH - 1:0] final_int; + reg [$clog2(INT_MAN_WIDTH + 1) - 1:0] denorm_shamt; + wire [1:0] fp_round_sticky_bits; + wire [1:0] int_round_sticky_bits; + wire [1:0] round_sticky_bits; + reg of_before_round; + reg uf_before_round; + always @(*) begin : cast_value + if (_sv2v_0) + ; + final_exp = $unsigned(destination_exp_q); + preshift_mant = 1'sb0; + denorm_shamt = SUPER_MAN_BITS - fpnew_pkg_man_bits(dst_fmt_q2); + of_before_round = 1'b0; + uf_before_round = 1'b0; + preshift_mant = input_mant_q << (INT_MAN_WIDTH + 1); + if (dst_is_int_q) begin + denorm_shamt = $unsigned((MAX_INT_WIDTH - 1) - input_exp_q); + if ((input_exp_q >= $signed((fpnew_pkg_int_width(int_fmt_q2) - 1) + op_mod_q2)) && !(((!op_mod_q2 && input_sign_q) && (input_exp_q == $signed(fpnew_pkg_int_width(int_fmt_q2) - 1))) && (input_mant_q == {1'b1, {INT_MAN_WIDTH - 1 {1'b0}}}))) begin + denorm_shamt = 1'sb0; + of_before_round = 1'b1; + end + else if (input_exp_q < -1) begin + denorm_shamt = MAX_INT_WIDTH + 1; + uf_before_round = 1'b1; + end + end + else if (~src_is_int_q && info_q[4]) begin + final_exp = $unsigned((2 ** fpnew_pkg_exp_bits(dst_fmt_q2)) - 1); + preshift_mant = 1'sb0; + end + else if (destination_exp_q >= ($signed(2 ** fpnew_pkg_exp_bits(dst_fmt_q2)) - 1)) begin + final_exp = $unsigned((2 ** fpnew_pkg_exp_bits(dst_fmt_q2)) - 2); + preshift_mant = 1'sb1; + of_before_round = 1'b1; + end + else if ((destination_exp_q < 1) && (destination_exp_q >= -$signed(fpnew_pkg_man_bits(dst_fmt_q2)))) begin + final_exp = 1'sb0; + denorm_shamt = $unsigned((denorm_shamt + 1) - destination_exp_q); + uf_before_round = 1'b1; + end + else if (destination_exp_q < -$signed(fpnew_pkg_man_bits(dst_fmt_q2))) begin + final_exp = 1'sb0; + denorm_shamt = $unsigned((denorm_shamt + 2) + fpnew_pkg_man_bits(dst_fmt_q2)); + uf_before_round = 1'b1; + end + end + localparam NUM_FP_STICKY = ((2 * INT_MAN_WIDTH) - SUPER_MAN_BITS) - 1; + localparam NUM_INT_STICKY = (2 * INT_MAN_WIDTH) - MAX_INT_WIDTH; + assign destination_mant = preshift_mant >> denorm_shamt; + assign {final_mant, fp_round_sticky_bits[1]} = destination_mant[(2 * INT_MAN_WIDTH) - 1-:SUPER_MAN_BITS + 1]; + assign {final_int, int_round_sticky_bits[1]} = destination_mant[2 * INT_MAN_WIDTH-:MAX_INT_WIDTH + 1]; + assign fp_round_sticky_bits[0] = |{destination_mant[NUM_FP_STICKY - 1:0]}; + assign int_round_sticky_bits[0] = |{destination_mant[NUM_INT_STICKY - 1:0]}; + assign round_sticky_bits = (dst_is_int_q ? int_round_sticky_bits : fp_round_sticky_bits); + wire [WIDTH - 1:0] pre_round_abs; + wire of_after_round; + wire uf_after_round; + reg [(NUM_FORMATS * WIDTH) - 1:0] fmt_pre_round_abs; + reg [4:0] fmt_of_after_round; + reg [4:0] fmt_uf_after_round; + reg [(NUM_INT_FORMATS * WIDTH) - 1:0] ifmt_pre_round_abs; + reg [(NUM_INT_FORMATS * WIDTH) - 1:0] ifmt_rounded_signed_res; + reg [3:0] ifmt_of_after_round; + wire rounded_sign; + wire [WIDTH - 1:0] rounded_abs; + wire result_true_zero; + wire [WIDTH - 1:0] rounded_uint_res; + wire [WIDTH - 1:0] rounded_int_res; + wire rounded_int_res_zero; + genvar _gv_fmt_2; + generate + for (_gv_fmt_2 = 0; _gv_fmt_2 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_2 = _gv_fmt_2 + 1) begin : gen_res_assemble + localparam fmt = _gv_fmt_2; + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + if (FpFmtConfig[fmt]) begin : active_format + always @(*) begin : assemble_result + if (_sv2v_0) + ; + fmt_pre_round_abs[fmt * WIDTH+:WIDTH] = {final_exp[EXP_BITS - 1:0], final_mant[MAN_BITS - 1:0]}; + end + end + else begin : inactive_format + wire [WIDTH * 1:1] sv2v_tmp_DA55D; + assign sv2v_tmp_DA55D = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) fmt_pre_round_abs[fmt * WIDTH+:WIDTH] = sv2v_tmp_DA55D; + end + end + endgenerate + genvar _gv_ifmt_2; + generate + for (_gv_ifmt_2 = 0; _gv_ifmt_2 < sv2v_cast_32_signed(NUM_INT_FORMATS); _gv_ifmt_2 = _gv_ifmt_2 + 1) begin : gen_int_res_zero_ext + localparam ifmt = _gv_ifmt_2; + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if (IntFmtConfig[ifmt]) begin : active_format + always @(*) begin : assemble_result + if (_sv2v_0) + ; + ifmt_pre_round_abs[ifmt * WIDTH+:WIDTH] = 1'sb0; + ifmt_pre_round_abs[(ifmt * WIDTH) + (INT_WIDTH - 1)-:INT_WIDTH] = final_int[INT_WIDTH - 1:0]; + end + end + else begin : inactive_format + wire [WIDTH * 1:1] sv2v_tmp_7C8AF; + assign sv2v_tmp_7C8AF = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) ifmt_pre_round_abs[ifmt * WIDTH+:WIDTH] = sv2v_tmp_7C8AF; + end + end + endgenerate + assign pre_round_abs = (dst_is_int_q ? ifmt_pre_round_abs[int_fmt_q2 * WIDTH+:WIDTH] : fmt_pre_round_abs[dst_fmt_q2 * WIDTH+:WIDTH]); + fpnew_rounding #(.AbsWidth(WIDTH)) i_fpnew_rounding( + .abs_value_i(pre_round_abs), + .sign_i(input_sign_q), + .round_sticky_bits_i(round_sticky_bits), + .rnd_mode_i(rnd_mode_q), + .effective_subtraction_i(1'b0), + .abs_rounded_o(rounded_abs), + .sign_o(rounded_sign), + .exact_zero_o(result_true_zero) + ); + reg [(NUM_FORMATS * WIDTH) - 1:0] fmt_result; + genvar _gv_fmt_3; + generate + for (_gv_fmt_3 = 0; _gv_fmt_3 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_3 = _gv_fmt_3 + 1) begin : gen_sign_inject + localparam fmt = _gv_fmt_3; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + if (FpFmtConfig[fmt]) begin : active_format + always @(*) begin : post_process + if (_sv2v_0) + ; + fmt_uf_after_round[fmt] = rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb0}}; + fmt_of_after_round[fmt] = rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb1}}; + fmt_result[fmt * WIDTH+:WIDTH] = 1'sb1; + fmt_result[(fmt * WIDTH) + (FP_WIDTH - 1)-:FP_WIDTH] = (src_is_int_q & mant_is_zero_q ? {FP_WIDTH * 1 {1'sb0}} : {rounded_sign, rounded_abs[(EXP_BITS + MAN_BITS) - 1:0]}); + end + end + else begin : inactive_format + wire [1:1] sv2v_tmp_4C394; + assign sv2v_tmp_4C394 = fpnew_pkg_DONT_CARE; + always @(*) fmt_uf_after_round[fmt] = sv2v_tmp_4C394; + wire [1:1] sv2v_tmp_5852E; + assign sv2v_tmp_5852E = fpnew_pkg_DONT_CARE; + always @(*) fmt_of_after_round[fmt] = sv2v_tmp_5852E; + wire [WIDTH * 1:1] sv2v_tmp_F321A; + assign sv2v_tmp_F321A = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) fmt_result[fmt * WIDTH+:WIDTH] = sv2v_tmp_F321A; + end + end + endgenerate + assign rounded_uint_res = (rounded_sign ? $unsigned(-rounded_abs) : rounded_abs); + genvar _gv_ifmt_3; + generate + for (_gv_ifmt_3 = 0; _gv_ifmt_3 < sv2v_cast_32_signed(NUM_INT_FORMATS); _gv_ifmt_3 = _gv_ifmt_3 + 1) begin : gen_int_res_sign_ext + localparam ifmt = _gv_ifmt_3; + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if (IntFmtConfig[ifmt]) begin : active_format + always @(*) begin : assemble_result + if (_sv2v_0) + ; + ifmt_rounded_signed_res[ifmt * WIDTH+:WIDTH] = {WIDTH {rounded_uint_res[INT_WIDTH - 1]}}; + ifmt_rounded_signed_res[(ifmt * WIDTH) + (INT_WIDTH - 1)-:INT_WIDTH] = rounded_uint_res[INT_WIDTH - 1:0]; + end + end + else begin : inactive_format + wire [WIDTH * 1:1] sv2v_tmp_79864; + assign sv2v_tmp_79864 = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) ifmt_rounded_signed_res[ifmt * WIDTH+:WIDTH] = sv2v_tmp_79864; + end + end + endgenerate + assign rounded_int_res = ifmt_rounded_signed_res[int_fmt_q2 * WIDTH+:WIDTH]; + assign rounded_int_res_zero = rounded_int_res == {WIDTH {1'sb0}}; + genvar _gv_ifmt_4; + generate + for (_gv_ifmt_4 = 0; _gv_ifmt_4 < sv2v_cast_32_signed(NUM_INT_FORMATS); _gv_ifmt_4 = _gv_ifmt_4 + 1) begin : gen_int_overflow + localparam ifmt = _gv_ifmt_4; + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if (IntFmtConfig[ifmt]) begin : active_format + always @(*) begin : detect_overflow + if (_sv2v_0) + ; + ifmt_of_after_round[ifmt] = 1'b0; + if (!rounded_sign && (input_exp_q == $signed((INT_WIDTH - 2) + op_mod_q2))) + ifmt_of_after_round[ifmt] = ~rounded_int_res[(INT_WIDTH - 2) + op_mod_q2]; + end + end + else begin : inactive_format + wire [1:1] sv2v_tmp_13A6C; + assign sv2v_tmp_13A6C = fpnew_pkg_DONT_CARE; + always @(*) ifmt_of_after_round[ifmt] = sv2v_tmp_13A6C; + end + end + endgenerate + assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; + assign of_after_round = (dst_is_int_q ? ifmt_of_after_round[int_fmt_q2] : fmt_of_after_round[dst_fmt_q2]); + wire [WIDTH - 1:0] fp_special_result; + wire [4:0] fp_special_status; + wire fp_result_is_special; + reg [(NUM_FORMATS * WIDTH) - 1:0] fmt_special_result; + genvar _gv_fmt_4; + generate + for (_gv_fmt_4 = 0; _gv_fmt_4 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_4 = _gv_fmt_4 + 1) begin : gen_special_results + localparam fmt = _gv_fmt_4; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + localparam [EXP_BITS - 1:0] QNAN_EXPONENT = 1'sb1; + localparam [MAN_BITS - 1:0] QNAN_MANTISSA = 2 ** (MAN_BITS - 1); + if (FpFmtConfig[fmt]) begin : active_format + always @(*) begin : special_results + reg [FP_WIDTH - 1:0] special_res; + if (_sv2v_0) + ; + special_res = (info_q[5] ? input_sign_q << (FP_WIDTH - 1) : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}); + fmt_special_result[fmt * WIDTH+:WIDTH] = 1'sb1; + fmt_special_result[(fmt * WIDTH) + (FP_WIDTH - 1)-:FP_WIDTH] = special_res; + end + end + else begin : inactive_format + wire [WIDTH * 1:1] sv2v_tmp_294DC; + assign sv2v_tmp_294DC = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) fmt_special_result[fmt * WIDTH+:WIDTH] = sv2v_tmp_294DC; + end + end + endgenerate + assign fp_result_is_special = ~src_is_int_q & ((info_q[5] | info_q[3]) | ~info_q[0]); + assign fp_special_status = {info_q[2], 4'b0000}; + assign fp_special_result = fmt_special_result[dst_fmt_q2 * WIDTH+:WIDTH]; + wire [WIDTH - 1:0] int_special_result; + wire [4:0] int_special_status; + wire int_result_is_special; + reg [(NUM_INT_FORMATS * WIDTH) - 1:0] ifmt_special_result; + genvar _gv_ifmt_5; + generate + for (_gv_ifmt_5 = 0; _gv_ifmt_5 < sv2v_cast_32_signed(NUM_INT_FORMATS); _gv_ifmt_5 = _gv_ifmt_5 + 1) begin : gen_special_results_int + localparam ifmt = _gv_ifmt_5; + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if (IntFmtConfig[ifmt]) begin : active_format + always @(*) begin : special_results + reg [INT_WIDTH - 1:0] special_res; + if (_sv2v_0) + ; + special_res[INT_WIDTH - 2:0] = 1'sb1; + special_res[INT_WIDTH - 1] = op_mod_q2; + if (input_sign_q && !info_q[3]) + special_res = ~special_res; + ifmt_special_result[ifmt * WIDTH+:WIDTH] = {WIDTH {special_res[INT_WIDTH - 1]}}; + ifmt_special_result[(ifmt * WIDTH) + (INT_WIDTH - 1)-:INT_WIDTH] = special_res; + end + end + else begin : inactive_format + wire [WIDTH * 1:1] sv2v_tmp_577FA; + assign sv2v_tmp_577FA = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) ifmt_special_result[ifmt * WIDTH+:WIDTH] = sv2v_tmp_577FA; + end + end + endgenerate + assign int_result_is_special = ((((info_q[3] | info_q[4]) | of_before_round) | of_after_round) | ~info_q[0]) | ((input_sign_q & op_mod_q2) & ~rounded_int_res_zero); + assign int_special_status = 5'b10000; + assign int_special_result = ifmt_special_result[int_fmt_q2 * WIDTH+:WIDTH]; + wire [4:0] int_regular_status; + wire [4:0] fp_regular_status; + wire [WIDTH - 1:0] fp_result; + wire [WIDTH - 1:0] int_result; + wire [4:0] fp_status; + wire [4:0] int_status; + assign fp_regular_status[4] = 1'b0; + assign fp_regular_status[3] = 1'b0; + assign fp_regular_status[2] = (src_is_int_q | ~info_q[4]) & (of_before_round | of_after_round); + assign fp_regular_status[1] = uf_after_round & fp_regular_status[0]; + assign fp_regular_status[0] = |fp_round_sticky_bits | ((src_is_int_q | ~info_q[4]) & (of_before_round | of_after_round)); + assign int_regular_status = {of_before_round | of_after_round, 3'b000, |int_round_sticky_bits}; + assign fp_result = (fp_result_is_special ? fp_special_result : fmt_result[dst_fmt_q2 * WIDTH+:WIDTH]); + assign fp_status = (fp_result_is_special ? fp_special_status : fp_regular_status); + assign int_result = (int_result_is_special ? int_special_result : rounded_int_res); + assign int_status = (int_result_is_special ? int_special_status : int_regular_status); + wire [WIDTH - 1:0] result_d; + wire [4:0] status_d; + wire extension_bit; + assign result_d = (dst_is_int_q ? int_result : fp_result); + assign status_d = (dst_is_int_q ? int_status : fp_status); + assign extension_bit = (dst_is_int_q ? int_result[WIDTH - 1] : 1'b1); + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * WIDTH) + ((NUM_OUT_REGS * WIDTH) - 1) : ((NUM_OUT_REGS + 1) * WIDTH) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * WIDTH : 0)] out_pipe_result_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * 5) + ((NUM_OUT_REGS * 5) - 1) : ((NUM_OUT_REGS + 1) * 5) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * 5 : 0)] out_pipe_status_q; + reg [0:NUM_OUT_REGS] out_pipe_ext_bit_q; + reg [0:NUM_OUT_REGS] out_pipe_tag_q; + reg [0:NUM_OUT_REGS] out_pipe_mask_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * AuxType_AUX_BITS) + ((NUM_OUT_REGS * AuxType_AUX_BITS) - 1) : ((NUM_OUT_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * AuxType_AUX_BITS : 0)] out_pipe_aux_q; + reg [0:NUM_OUT_REGS] out_pipe_valid_q; + wire [0:NUM_OUT_REGS] out_pipe_ready; + wire [WIDTH * 1:1] sv2v_tmp_6C5BE; + assign sv2v_tmp_6C5BE = result_d; + always @(*) out_pipe_result_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * WIDTH+:WIDTH] = sv2v_tmp_6C5BE; + wire [5:1] sv2v_tmp_D9FFA; + assign sv2v_tmp_D9FFA = status_d; + always @(*) out_pipe_status_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * 5+:5] = sv2v_tmp_D9FFA; + wire [1:1] sv2v_tmp_F04C7; + assign sv2v_tmp_F04C7 = extension_bit; + always @(*) out_pipe_ext_bit_q[0] = sv2v_tmp_F04C7; + wire [1:1] sv2v_tmp_1CCC3; + assign sv2v_tmp_1CCC3 = mid_pipe_tag_q[NUM_MID_REGS]; + always @(*) out_pipe_tag_q[0] = sv2v_tmp_1CCC3; + wire [1:1] sv2v_tmp_D6E81; + assign sv2v_tmp_D6E81 = mid_pipe_mask_q[NUM_MID_REGS]; + always @(*) out_pipe_mask_q[0] = sv2v_tmp_D6E81; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_77E30; + assign sv2v_tmp_77E30 = mid_pipe_aux_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + always @(*) out_pipe_aux_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_77E30; + wire [1:1] sv2v_tmp_E45E7; + assign sv2v_tmp_E45E7 = mid_pipe_valid_q[NUM_MID_REGS]; + always @(*) out_pipe_valid_q[0] = sv2v_tmp_E45E7; + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + genvar _gv_i_4; + generate + for (_gv_i_4 = 0; _gv_i_4 < NUM_OUT_REGS; _gv_i_4 = _gv_i_4 + 1) begin : gen_output_pipeline + localparam i = _gv_i_4; + wire reg_ena; + assign out_pipe_ready[i] = out_pipe_ready[i + 1] | ~out_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_valid_q[i + 1] <= 1'b0; + else + out_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (out_pipe_ready[i] ? out_pipe_valid_q[i] : out_pipe_valid_q[i + 1])); + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[(NUM_INP_REGS + NUM_MID_REGS) + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH] <= 1'sb0; + else + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH] <= (reg_ena ? out_pipe_result_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * WIDTH+:WIDTH] : out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= (reg_ena ? out_pipe_status_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * 5+:5] : out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_ext_bit_q[i + 1] <= 1'sb0; + else + out_pipe_ext_bit_q[i + 1] <= (reg_ena ? out_pipe_ext_bit_q[i] : out_pipe_ext_bit_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_tag_q[i + 1] <= 1'b0; + else + out_pipe_tag_q[i + 1] <= (reg_ena ? out_pipe_tag_q[i] : out_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_mask_q[i + 1] <= 1'sb0; + else + out_pipe_mask_q[i + 1] <= (reg_ena ? out_pipe_mask_q[i] : out_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + assign result_o = out_pipe_result_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * WIDTH+:WIDTH]; + assign status_o = out_pipe_status_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * 5+:5]; + assign extension_bit_o = out_pipe_ext_bit_q[NUM_OUT_REGS]; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = |{inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}; + generate + if (NUM_OUT_REGS > 0) begin : genblk13 + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], out_pipe_valid_q[NUM_OUT_REGS - 1]}; + end + else if (NUM_MID_REGS > 0) begin : genblk13 + assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS], mid_pipe_valid_q[NUM_MID_REGS - 1]}; + end + else if (NUM_INP_REGS > 0) begin : genblk13 + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], inp_pipe_valid_q[NUM_INP_REGS - 1]}; + end + else begin : genblk13 + assign early_out_valid_o = 1'b0; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module fpnew_classifier ( + operands_i, + is_boxed_i, + info_o +); + reg _sv2v_0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + parameter [2:0] FpFormat = sv2v_cast_5D882(0); + parameter [31:0] NumOperands = 1; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + localparam [31:0] WIDTH = fpnew_pkg_fp_width(FpFormat); + input wire [(NumOperands * WIDTH) - 1:0] operands_i; + input wire [NumOperands - 1:0] is_boxed_i; + output reg [(NumOperands * 8) - 1:0] info_o; + function automatic [31:0] fpnew_pkg_exp_bits; + input reg [2:0] fmt; + fpnew_pkg_exp_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32]; + endfunction + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(FpFormat); + function automatic [31:0] fpnew_pkg_man_bits; + input reg [2:0] fmt; + fpnew_pkg_man_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]; + endfunction + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(FpFormat); + genvar _gv_op_1; + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + generate + for (_gv_op_1 = 0; _gv_op_1 < sv2v_cast_32_signed(NumOperands); _gv_op_1 = _gv_op_1 + 1) begin : gen_num_values + localparam op = _gv_op_1; + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] value; + reg is_boxed; + reg is_normal; + reg is_inf; + reg is_nan; + reg is_signalling; + reg is_quiet; + reg is_zero; + reg is_subnormal; + always @(*) begin : classify_input + if (_sv2v_0) + ; + value = operands_i[op * WIDTH+:WIDTH]; + is_boxed = is_boxed_i[op]; + is_normal = (is_boxed && (value[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)] != {((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1) * 1 {1'sb0}})) && (value[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)] != {((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1) * 1 {1'sb1}}); + is_zero = (is_boxed && (value[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)] == {((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1) * 1 {1'sb0}})) && (value[MAN_BITS - 1-:MAN_BITS] == {MAN_BITS * 1 {1'sb0}}); + is_subnormal = (is_boxed && (value[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)] == {((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1) * 1 {1'sb0}})) && !is_zero; + is_inf = is_boxed && ((value[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)] == {((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1) * 1 {1'sb1}}) && (value[MAN_BITS - 1-:MAN_BITS] == {MAN_BITS * 1 {1'sb0}})); + is_nan = !is_boxed || ((value[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)] == {((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1) * 1 {1'sb1}}) && (value[MAN_BITS - 1-:MAN_BITS] != {MAN_BITS * 1 {1'sb0}})); + is_signalling = (is_boxed && is_nan) && (value[(MAN_BITS - 1) - ((MAN_BITS - 1) - (MAN_BITS - 1))] == 1'b0); + is_quiet = is_nan && !is_signalling; + info_o[(op * 8) + 7] = is_normal; + info_o[(op * 8) + 6] = is_subnormal; + info_o[(op * 8) + 5] = is_zero; + info_o[(op * 8) + 4] = is_inf; + info_o[(op * 8) + 3] = is_nan; + info_o[(op * 8) + 2] = is_signalling; + info_o[(op * 8) + 1] = is_quiet; + info_o[op * 8] = is_boxed; + end + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module gated_clk_cell ( + clk_in, + global_en, + module_en, + local_en, + external_en, + pad_yy_icg_scan_en, + clk_out +); + input clk_in; + input global_en; + input module_en; + input local_en; + input external_en; + input pad_yy_icg_scan_en; + output wire clk_out; + wire clk_en_bf_latch; + wire SE; + assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en; + assign SE = pad_yy_icg_scan_en; + assign clk_out = clk_in; +endmodule +module pa_fdsu_ctrl ( + cp0_fpu_icg_en, + cp0_yy_clk_en, + cpurst_b, + ctrl_fdsu_ex1_sel, + ctrl_xx_ex1_cmplt_dp, + ctrl_xx_ex1_inst_vld, + ctrl_xx_ex1_stall, + ctrl_xx_ex1_warm_up, + ctrl_xx_ex2_warm_up, + ctrl_xx_ex3_warm_up, + ex1_div, + ex1_expnt_adder_op0, + ex1_of_result_lfn, + ex1_op0_id, + ex1_op0_norm, + ex1_op1_id_vld, + ex1_op1_norm, + ex1_op1_sel, + ex1_oper_id_expnt, + ex1_oper_id_expnt_f, + ex1_pipedown, + ex1_pipedown_gate, + ex1_result_sign, + ex1_rm, + ex1_save_op0, + ex1_save_op0_gate, + ex1_sqrt, + ex1_srt_skip, + ex2_expnt_adder_op0, + ex2_of, + ex2_pipe_clk, + ex2_pipedown, + ex2_potnt_of, + ex2_potnt_uf, + ex2_result_inf, + ex2_result_lfn, + ex2_rslt_denorm, + ex2_srt_expnt_rst, + ex2_srt_first_round, + ex2_uf, + ex2_uf_srt_skip, + ex3_expnt_adjust_result, + ex3_pipedown, + ex3_rslt_denorm, + fdsu_ex1_sel, + fdsu_fpu_ex1_cmplt, + fdsu_fpu_ex1_cmplt_dp, + fdsu_fpu_ex1_stall, + fdsu_fpu_no_op, + fdsu_frbus_wb_vld, + fdsu_yy_div, + fdsu_yy_expnt_rst, + fdsu_yy_of, + fdsu_yy_of_rm_lfn, + fdsu_yy_op0_norm, + fdsu_yy_op1_norm, + fdsu_yy_potnt_of, + fdsu_yy_potnt_uf, + fdsu_yy_result_inf, + fdsu_yy_result_lfn, + fdsu_yy_result_sign, + fdsu_yy_rm, + fdsu_yy_rslt_denorm, + fdsu_yy_sqrt, + fdsu_yy_uf, + fdsu_yy_wb_freg, + forever_cpuclk, + frbus_fdsu_wb_grant, + idu_fpu_ex1_dst_freg, + idu_fpu_ex1_eu_sel, + pad_yy_icg_scan_en, + rtu_xx_ex1_cancel, + rtu_xx_ex2_cancel, + rtu_yy_xx_async_flush, + rtu_yy_xx_flush, + srt_remainder_zero, + srt_sm_on +); + input wire cp0_fpu_icg_en; + input wire cp0_yy_clk_en; + input wire cpurst_b; + input wire ctrl_fdsu_ex1_sel; + input wire ctrl_xx_ex1_cmplt_dp; + input wire ctrl_xx_ex1_inst_vld; + input wire ctrl_xx_ex1_stall; + input wire ctrl_xx_ex1_warm_up; + input wire ctrl_xx_ex2_warm_up; + input wire ctrl_xx_ex3_warm_up; + input wire ex1_div; + input wire [12:0] ex1_expnt_adder_op0; + input wire ex1_of_result_lfn; + input wire ex1_op0_id; + input ex1_op0_norm; + input wire ex1_op1_id_vld; + input ex1_op1_norm; + input wire [12:0] ex1_oper_id_expnt; + input wire ex1_result_sign; + input wire [2:0] ex1_rm; + input wire ex1_sqrt; + input wire ex1_srt_skip; + input wire ex2_of; + input wire ex2_potnt_of; + input wire ex2_potnt_uf; + input wire ex2_result_inf; + input wire ex2_result_lfn; + input wire ex2_rslt_denorm; + input wire [9:0] ex2_srt_expnt_rst; + input wire ex2_uf; + input wire ex2_uf_srt_skip; + input wire [9:0] ex3_expnt_adjust_result; + input wire ex3_rslt_denorm; + input wire forever_cpuclk; + input wire frbus_fdsu_wb_grant; + input wire [4:0] idu_fpu_ex1_dst_freg; + input wire [2:0] idu_fpu_ex1_eu_sel; + input wire pad_yy_icg_scan_en; + input wire rtu_xx_ex1_cancel; + input wire rtu_xx_ex2_cancel; + input wire rtu_yy_xx_async_flush; + input wire rtu_yy_xx_flush; + input wire srt_remainder_zero; + output wire ex1_op1_sel; + output wire [12:0] ex1_oper_id_expnt_f; + output wire ex1_pipedown; + output wire ex1_pipedown_gate; + output wire ex1_save_op0; + output wire ex1_save_op0_gate; + output wire [9:0] ex2_expnt_adder_op0; + output wire ex2_pipe_clk; + output wire ex2_pipedown; + output reg ex2_srt_first_round; + output wire ex3_pipedown; + output wire fdsu_ex1_sel; + output wire fdsu_fpu_ex1_cmplt; + output wire fdsu_fpu_ex1_cmplt_dp; + output wire fdsu_fpu_ex1_stall; + output wire fdsu_fpu_no_op; + output wire fdsu_frbus_wb_vld; + output wire fdsu_yy_div; + output wire [9:0] fdsu_yy_expnt_rst; + output wire fdsu_yy_of; + output wire fdsu_yy_of_rm_lfn; + output wire fdsu_yy_op0_norm; + output wire fdsu_yy_op1_norm; + output wire fdsu_yy_potnt_of; + output wire fdsu_yy_potnt_uf; + output wire fdsu_yy_result_inf; + output wire fdsu_yy_result_lfn; + output wire fdsu_yy_result_sign; + output wire [2:0] fdsu_yy_rm; + output reg fdsu_yy_rslt_denorm; + output wire fdsu_yy_sqrt; + output wire fdsu_yy_uf; + output wire [4:0] fdsu_yy_wb_freg; + output wire srt_sm_on; + reg [2:0] fdsu_cur_state; + reg fdsu_div; + reg [9:0] fdsu_expnt_rst; + reg [2:0] fdsu_next_state; + reg fdsu_of; + reg fdsu_of_rm_lfn; + reg fdsu_potnt_of; + reg fdsu_potnt_uf; + reg fdsu_result_inf; + reg fdsu_result_lfn; + reg fdsu_result_sign; + reg [2:0] fdsu_rm; + reg fdsu_sqrt; + reg fdsu_uf; + reg [4:0] fdsu_wb_freg; + reg [4:0] srt_cnt; + reg [1:0] wb_cur_state; + reg [1:0] wb_nxt_state; + wire ctrl_fdsu_ex1_stall; + wire ctrl_fdsu_wb_vld; + wire ctrl_iter_start; + wire ctrl_iter_start_gate; + wire ctrl_pack; + wire ctrl_result_vld; + wire ctrl_round; + wire ctrl_sm_cmplt; + wire ctrl_sm_ex1; + wire ctrl_sm_idle; + wire ctrl_sm_start; + wire ctrl_sm_start_gate; + wire ctrl_srt_idle; + wire ctrl_srt_itering; + wire ctrl_wb_idle; + wire ctrl_wb_sm_cmplt; + wire ctrl_wb_sm_ex2; + wire ctrl_wb_sm_idle; + wire ctrl_wfi2; + wire ctrl_wfwb; + wire ex1_pipe_clk; + wire ex1_pipe_clk_en; + wire [4:0] ex1_wb_freg; + wire ex2_pipe_clk_en; + wire expnt_rst_clk; + wire expnt_rst_clk_en; + wire fdsu_busy; + wire fdsu_clk; + wire fdsu_clk_en; + wire fdsu_dn_stall; + wire fdsu_ex1_inst_vld; + wire fdsu_ex1_res_vld; + wire fdsu_flush; + wire fdsu_op0_norm; + wire fdsu_op1_norm; + wire fdsu_wb_grant; + wire [4:0] srt_cnt_ini; + wire srt_cnt_zero; + wire srt_last_round; + wire srt_skip; + assign ex1_wb_freg[4:0] = idu_fpu_ex1_dst_freg[4:0]; + assign fdsu_ex1_inst_vld = ctrl_xx_ex1_inst_vld && ctrl_fdsu_ex1_sel; + assign fdsu_ex1_sel = idu_fpu_ex1_eu_sel[2]; + assign fdsu_ex1_res_vld = fdsu_ex1_inst_vld && ex1_srt_skip; + assign fdsu_wb_grant = frbus_fdsu_wb_grant; + assign ctrl_iter_start = (ctrl_sm_start && !fdsu_dn_stall) || ctrl_wfi2; + assign ctrl_iter_start_gate = (ctrl_sm_start_gate && !fdsu_dn_stall) || ctrl_wfi2; + assign ctrl_sm_start = (fdsu_ex1_inst_vld && ctrl_srt_idle) && !ex1_srt_skip; + assign ctrl_sm_start_gate = fdsu_ex1_inst_vld && ctrl_srt_idle; + assign srt_last_round = ((srt_skip || srt_remainder_zero) || srt_cnt_zero) && ctrl_srt_itering; + assign srt_skip = ex2_of || ex2_uf_srt_skip; + assign srt_cnt_zero = ~|srt_cnt[4:0]; + assign fdsu_dn_stall = ctrl_sm_start && ex1_op1_id_vld; + parameter IDLE = 3'b000; + parameter WFI2 = 3'b001; + parameter ITER = 3'b010; + parameter RND = 3'b011; + parameter PACK = 3'b100; + parameter WFWB = 3'b101; + always @(posedge fdsu_clk or negedge cpurst_b) + if (!cpurst_b) + fdsu_cur_state[2:0] <= IDLE; + else if (fdsu_flush) + fdsu_cur_state[2:0] <= IDLE; + else + fdsu_cur_state[2:0] <= fdsu_next_state[2:0]; + always @(ctrl_sm_start or fdsu_dn_stall or srt_last_round or fdsu_cur_state[2:0] or fdsu_wb_grant) + case (fdsu_cur_state[2:0]) + IDLE: + if (ctrl_sm_start) begin + if (fdsu_dn_stall) + fdsu_next_state[2:0] = WFI2; + else + fdsu_next_state[2:0] = ITER; + end + else + fdsu_next_state[2:0] = IDLE; + WFI2: fdsu_next_state[2:0] = ITER; + ITER: + if (srt_last_round) + fdsu_next_state[2:0] = RND; + else + fdsu_next_state[2:0] = ITER; + RND: fdsu_next_state[2:0] = PACK; + PACK: + if (fdsu_wb_grant) begin + if (ctrl_sm_start) begin + if (fdsu_dn_stall) + fdsu_next_state[2:0] = WFI2; + else + fdsu_next_state[2:0] = ITER; + end + else + fdsu_next_state[2:0] = IDLE; + end + else + fdsu_next_state[2:0] = WFWB; + WFWB: + if (fdsu_wb_grant) begin + if (ctrl_sm_start) begin + if (fdsu_dn_stall) + fdsu_next_state[2:0] = WFI2; + else + fdsu_next_state[2:0] = ITER; + end + else + fdsu_next_state[2:0] = IDLE; + end + else + fdsu_next_state[2:0] = WFWB; + default: fdsu_next_state[2:0] = IDLE; + endcase + assign ctrl_sm_idle = fdsu_cur_state[2:0] == IDLE; + assign ctrl_wfi2 = fdsu_cur_state[2:0] == WFI2; + assign ctrl_srt_itering = fdsu_cur_state[2:0] == ITER; + assign ctrl_round = fdsu_cur_state[2:0] == RND; + assign ctrl_pack = fdsu_cur_state[2:0] == PACK; + assign ctrl_wfwb = fdsu_cur_state[2:0] == WFWB; + assign ctrl_sm_cmplt = ctrl_pack || ctrl_wfwb; + assign ctrl_srt_idle = ctrl_sm_idle || fdsu_wb_grant; + assign ctrl_sm_ex1 = ctrl_srt_idle || ctrl_wfi2; + always @(posedge fdsu_clk) + if (fdsu_flush) + srt_cnt[4:0] <= 5'b00000; + else if (ctrl_iter_start) + srt_cnt[4:0] <= srt_cnt_ini[4:0]; + else if (ctrl_srt_itering) + srt_cnt[4:0] <= srt_cnt[4:0] - 5'b00001; + else + srt_cnt[4:0] <= srt_cnt[4:0]; + assign srt_cnt_ini[4:0] = 5'b01110; + always @(posedge fdsu_clk or negedge cpurst_b) + if (!cpurst_b) + ex2_srt_first_round <= 1'b0; + else if (fdsu_flush) + ex2_srt_first_round <= 1'b0; + else if (ex1_pipedown) + ex2_srt_first_round <= 1'b1; + else + ex2_srt_first_round <= 1'b0; + parameter WB_IDLE = 2'b00; + parameter WB_EX2 = 2'b10; + parameter WB_CMPLT = 2'b01; + always @(posedge fdsu_clk or negedge cpurst_b) + if (!cpurst_b) + wb_cur_state[1:0] <= WB_IDLE; + else if (fdsu_flush) + wb_cur_state[1:0] <= WB_IDLE; + else + wb_cur_state[1:0] <= wb_nxt_state[1:0]; + always @(ctrl_fdsu_wb_vld or fdsu_dn_stall or ctrl_xx_ex1_stall or fdsu_ex1_inst_vld or ctrl_iter_start or fdsu_ex1_res_vld or wb_cur_state[1:0]) + case (wb_cur_state[1:0]) + WB_IDLE: + if (fdsu_ex1_inst_vld) begin + if ((ctrl_xx_ex1_stall || fdsu_ex1_res_vld) || fdsu_dn_stall) + wb_nxt_state[1:0] = WB_IDLE; + else + wb_nxt_state[1:0] = WB_EX2; + end + else + wb_nxt_state[1:0] = WB_IDLE; + WB_EX2: + if (ctrl_fdsu_wb_vld) begin + if (ctrl_iter_start && !ctrl_xx_ex1_stall) + wb_nxt_state[1:0] = WB_EX2; + else + wb_nxt_state[1:0] = WB_IDLE; + end + else + wb_nxt_state[1:0] = WB_CMPLT; + WB_CMPLT: + if (ctrl_fdsu_wb_vld) begin + if (ctrl_iter_start && !ctrl_xx_ex1_stall) + wb_nxt_state[1:0] = WB_EX2; + else + wb_nxt_state[1:0] = WB_IDLE; + end + else + wb_nxt_state[1:0] = WB_CMPLT; + default: wb_nxt_state[1:0] = WB_IDLE; + endcase + assign ctrl_wb_idle = (wb_cur_state[1:0] == WB_IDLE) || ((wb_cur_state[1:0] == WB_CMPLT) && ctrl_fdsu_wb_vld); + assign ctrl_wb_sm_idle = wb_cur_state[1:0] == WB_IDLE; + assign ctrl_wb_sm_ex2 = wb_cur_state[1:0] == WB_EX2; + assign ctrl_wb_sm_cmplt = (wb_cur_state[1:0] == WB_EX2) || (wb_cur_state[1:0] == WB_CMPLT); + assign ctrl_result_vld = ctrl_sm_cmplt && ctrl_wb_sm_cmplt; + assign ctrl_fdsu_wb_vld = ctrl_result_vld && frbus_fdsu_wb_grant; + assign ctrl_fdsu_ex1_stall = ((fdsu_ex1_inst_vld && !ctrl_sm_ex1) && !ctrl_wb_idle) || (fdsu_ex1_inst_vld && fdsu_dn_stall); + always @(posedge ex1_pipe_clk) + if (ex1_pipedown) begin + fdsu_wb_freg[4:0] <= ex1_wb_freg[4:0]; + fdsu_result_sign <= ex1_result_sign; + fdsu_of_rm_lfn <= ex1_of_result_lfn; + fdsu_div <= ex1_div; + fdsu_sqrt <= ex1_sqrt; + fdsu_rm[2:0] <= ex1_rm[2:0]; + end + else begin + fdsu_wb_freg[4:0] <= fdsu_wb_freg[4:0]; + fdsu_result_sign <= fdsu_result_sign; + fdsu_of_rm_lfn <= fdsu_of_rm_lfn; + fdsu_div <= fdsu_div; + fdsu_sqrt <= fdsu_sqrt; + fdsu_rm[2:0] <= fdsu_rm[2:0]; + end + assign fdsu_op0_norm = 1'b1; + assign fdsu_op1_norm = 1'b1; + always @(posedge expnt_rst_clk) + if (ex1_save_op0) + fdsu_expnt_rst[9:0] <= ex1_oper_id_expnt[9:0]; + else if (ex1_pipedown) + fdsu_expnt_rst[9:0] <= ex1_expnt_adder_op0[9:0]; + else if (ex2_pipedown) + fdsu_expnt_rst[9:0] <= ex2_srt_expnt_rst[9:0]; + else if (ex3_pipedown) + fdsu_expnt_rst[9:0] <= ex3_expnt_adjust_result[9:0]; + else + fdsu_expnt_rst[9:0] <= fdsu_expnt_rst[9:0]; + assign ex1_oper_id_expnt_f[12:0] = {3'b001, fdsu_expnt_rst[9:0]}; + always @(posedge expnt_rst_clk) + if (ex2_pipedown) + fdsu_yy_rslt_denorm <= ex2_rslt_denorm; + else if (ex3_pipedown) + fdsu_yy_rslt_denorm <= ex3_rslt_denorm; + else + fdsu_yy_rslt_denorm <= fdsu_yy_rslt_denorm; + always @(posedge ex2_pipe_clk) + if (ex2_pipedown) begin + fdsu_result_inf <= ex2_result_inf; + fdsu_result_lfn <= ex2_result_lfn; + fdsu_of <= ex2_of; + fdsu_uf <= ex2_uf; + fdsu_potnt_of <= ex2_potnt_of; + fdsu_potnt_uf <= ex2_potnt_uf; + end + else begin + fdsu_result_inf <= fdsu_result_inf; + fdsu_result_lfn <= fdsu_result_lfn; + fdsu_of <= fdsu_of; + fdsu_uf <= fdsu_uf; + fdsu_potnt_of <= fdsu_potnt_of; + fdsu_potnt_uf <= fdsu_potnt_uf; + end + assign fdsu_flush = (((rtu_xx_ex1_cancel && ctrl_wb_idle) || (rtu_xx_ex2_cancel && ctrl_wb_sm_ex2)) || ctrl_xx_ex1_warm_up) || rtu_yy_xx_async_flush; + assign fdsu_busy = (fdsu_ex1_inst_vld || !ctrl_sm_idle) || !ctrl_wb_sm_idle; + assign fdsu_clk_en = (fdsu_busy || !ctrl_sm_idle) || rtu_yy_xx_flush; + gated_clk_cell x_fdsu_clk( + .clk_in(forever_cpuclk), + .clk_out(fdsu_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(fdsu_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign ex1_pipe_clk_en = ex1_pipedown_gate; + gated_clk_cell x_ex1_pipe_clk( + .clk_in(forever_cpuclk), + .clk_out(ex1_pipe_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(ex1_pipe_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign ex2_pipe_clk_en = ex2_pipedown; + gated_clk_cell x_ex2_pipe_clk( + .clk_in(forever_cpuclk), + .clk_out(ex2_pipe_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(ex2_pipe_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign expnt_rst_clk_en = ((ex1_save_op0_gate || ex1_pipedown_gate) || ex2_pipedown) || ex3_pipedown; + gated_clk_cell x_expnt_rst_clk( + .clk_in(forever_cpuclk), + .clk_out(expnt_rst_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(expnt_rst_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign fdsu_yy_wb_freg[4:0] = fdsu_wb_freg[4:0]; + assign fdsu_yy_result_sign = fdsu_result_sign; + assign fdsu_yy_op0_norm = fdsu_op0_norm; + assign fdsu_yy_op1_norm = fdsu_op1_norm; + assign fdsu_yy_of_rm_lfn = fdsu_of_rm_lfn; + assign fdsu_yy_div = fdsu_div; + assign fdsu_yy_sqrt = fdsu_sqrt; + assign fdsu_yy_rm[2:0] = fdsu_rm[2:0]; + assign fdsu_yy_expnt_rst[9:0] = fdsu_expnt_rst[9:0]; + assign ex2_expnt_adder_op0[9:0] = fdsu_expnt_rst[9:0]; + assign fdsu_yy_result_inf = fdsu_result_inf; + assign fdsu_yy_result_lfn = fdsu_result_lfn; + assign fdsu_yy_of = fdsu_of; + assign fdsu_yy_uf = fdsu_uf; + assign fdsu_yy_potnt_of = fdsu_potnt_of; + assign fdsu_yy_potnt_uf = fdsu_potnt_uf; + assign ex1_pipedown = ctrl_iter_start || ctrl_xx_ex1_warm_up; + assign ex1_pipedown_gate = ctrl_iter_start_gate || ctrl_xx_ex1_warm_up; + assign ex2_pipedown = (ctrl_srt_itering && srt_last_round) || ctrl_xx_ex2_warm_up; + assign ex3_pipedown = ctrl_round || ctrl_xx_ex3_warm_up; + assign srt_sm_on = ctrl_srt_itering; + assign fdsu_fpu_ex1_cmplt = fdsu_ex1_inst_vld; + assign fdsu_fpu_ex1_cmplt_dp = ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel[2]; + assign fdsu_fpu_ex1_stall = ctrl_fdsu_ex1_stall; + assign fdsu_frbus_wb_vld = ctrl_result_vld; + assign fdsu_fpu_no_op = !fdsu_busy; + assign ex1_op1_sel = ctrl_wfi2; + assign ex1_save_op0 = (ctrl_sm_start && ex1_op0_id) && ex1_op1_id_vld; + assign ex1_save_op0_gate = (ctrl_sm_start_gate && ex1_op0_id) && ex1_op1_id_vld; +endmodule +module pa_fdsu_ff1 ( + fanc_shift_num, + frac_bin_val, + frac_num +); + input wire [51:0] frac_num; + output reg [51:0] fanc_shift_num; + output reg [12:0] frac_bin_val; + always @(frac_num[51:0]) + casez (frac_num[51:0]) + 52'b1zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h0000; + 52'b01zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fff; + 52'b001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ffe; + 52'b0001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ffd; + 52'b00001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ffc; + 52'b000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ffb; + 52'b0000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ffa; + 52'b00000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff9; + 52'b000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff8; + 52'b0000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff7; + 52'b00000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff6; + 52'b000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff5; + 52'b0000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff4; + 52'b00000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff3; + 52'b000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff2; + 52'b0000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff1; + 52'b00000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1ff0; + 52'b000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fef; + 52'b0000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fee; + 52'b00000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fed; + 52'b000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fec; + 52'b0000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1feb; + 52'b00000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fea; + 52'b000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe9; + 52'b0000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe8; + 52'b00000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe7; + 52'b000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe6; + 52'b0000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe5; + 52'b00000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe4; + 52'b000000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe3; + 52'b0000000000000000000000000000001zzzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe2; + 52'b00000000000000000000000000000001zzzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe1; + 52'b000000000000000000000000000000001zzzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fe0; + 52'b0000000000000000000000000000000001zzzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fdf; + 52'b00000000000000000000000000000000001zzzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fde; + 52'b000000000000000000000000000000000001zzzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fdd; + 52'b0000000000000000000000000000000000001zzzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fdc; + 52'b00000000000000000000000000000000000001zzzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fdb; + 52'b000000000000000000000000000000000000001zzzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fda; + 52'b0000000000000000000000000000000000000001zzzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fd9; + 52'b00000000000000000000000000000000000000001zzzzzzzzzzz: frac_bin_val[12:0] = 13'h1fd8; + 52'b000000000000000000000000000000000000000001zzzzzzzzzz: frac_bin_val[12:0] = 13'h1fd7; + 52'b0000000000000000000000000000000000000000001zzzzzzzzz: frac_bin_val[12:0] = 13'h1fd6; + 52'b00000000000000000000000000000000000000000001zzzzzzzz: frac_bin_val[12:0] = 13'h1fd5; + 52'b000000000000000000000000000000000000000000001zzzzzzz: frac_bin_val[12:0] = 13'h1fd4; + 52'b0000000000000000000000000000000000000000000001zzzzzz: frac_bin_val[12:0] = 13'h1fd3; + 52'b00000000000000000000000000000000000000000000001zzzzz: frac_bin_val[12:0] = 13'h1fd2; + 52'b000000000000000000000000000000000000000000000001zzzz: frac_bin_val[12:0] = 13'h1fd1; + 52'b0000000000000000000000000000000000000000000000001zzz: frac_bin_val[12:0] = 13'h1fd0; + 52'b00000000000000000000000000000000000000000000000001zz: frac_bin_val[12:0] = 13'h1fcf; + 52'b000000000000000000000000000000000000000000000000001z: frac_bin_val[12:0] = 13'h1fce; + 52'b0000000000000000000000000000000000000000000000000001: frac_bin_val[12:0] = 13'h1fcd; + 52'b0000000000000000000000000000000000000000000000000000: frac_bin_val[12:0] = 13'h1fcc; + default: frac_bin_val[12:0] = 13'h0000; + endcase + always @(frac_num[51:0]) + casez (frac_num[51:0]) + 52'b1zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = frac_num[51:0]; + 52'b01zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[50:0], 1'b0}; + 52'b001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[49:0], 2'b00}; + 52'b0001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[48:0], 3'b000}; + 52'b00001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[47:0], 4'b0000}; + 52'b000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[46:0], 5'b00000}; + 52'b0000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[45:0], 6'b000000}; + 52'b00000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[44:0], 7'b0000000}; + 52'b000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[43:0], 8'b00000000}; + 52'b0000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[42:0], 9'b000000000}; + 52'b00000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[41:0], 10'b0000000000}; + 52'b000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[40:0], 11'b00000000000}; + 52'b0000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[39:0], 12'b000000000000}; + 52'b00000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[38:0], 13'b0000000000000}; + 52'b000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[37:0], 14'b00000000000000}; + 52'b0000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[36:0], 15'b000000000000000}; + 52'b00000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[35:0], 16'b0000000000000000}; + 52'b000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[34:0], 17'b00000000000000000}; + 52'b0000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[33:0], 18'b000000000000000000}; + 52'b00000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[32:0], 19'b0000000000000000000}; + 52'b000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[31:0], 20'b00000000000000000000}; + 52'b0000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[30:0], 21'b000000000000000000000}; + 52'b00000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[29:0], 22'b0000000000000000000000}; + 52'b000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[28:0], 23'b00000000000000000000000}; + 52'b0000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[27:0], 24'b000000000000000000000000}; + 52'b00000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[26:0], 25'b0000000000000000000000000}; + 52'b000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[25:0], 26'b00000000000000000000000000}; + 52'b0000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[24:0], 27'b000000000000000000000000000}; + 52'b00000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[23:0], 28'b0000000000000000000000000000}; + 52'b000000000000000000000000000001zzzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[22:0], 29'b00000000000000000000000000000}; + 52'b0000000000000000000000000000001zzzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[21:0], 30'b000000000000000000000000000000}; + 52'b00000000000000000000000000000001zzzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[20:0], 31'b0000000000000000000000000000000}; + 52'b000000000000000000000000000000001zzzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[19:0], 32'b00000000000000000000000000000000}; + 52'b0000000000000000000000000000000001zzzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[18:0], 33'b000000000000000000000000000000000}; + 52'b00000000000000000000000000000000001zzzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[17:0], 34'b0000000000000000000000000000000000}; + 52'b000000000000000000000000000000000001zzzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[16:0], 35'b00000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000001zzzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[15:0], 36'b000000000000000000000000000000000000}; + 52'b00000000000000000000000000000000000001zzzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[14:0], 37'b0000000000000000000000000000000000000}; + 52'b000000000000000000000000000000000000001zzzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[13:0], 38'b00000000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000000001zzzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[12:0], 39'b000000000000000000000000000000000000000}; + 52'b00000000000000000000000000000000000000001zzzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[11:0], 40'b0000000000000000000000000000000000000000}; + 52'b000000000000000000000000000000000000000001zzzzzzzzzz: fanc_shift_num[51:0] = {frac_num[10:0], 41'b00000000000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000000000001zzzzzzzzz: fanc_shift_num[51:0] = {frac_num[9:0], 42'b000000000000000000000000000000000000000000}; + 52'b00000000000000000000000000000000000000000001zzzzzzzz: fanc_shift_num[51:0] = {frac_num[8:0], 43'b0000000000000000000000000000000000000000000}; + 52'b000000000000000000000000000000000000000000001zzzzzzz: fanc_shift_num[51:0] = {frac_num[7:0], 44'b00000000000000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000000000000001zzzzzz: fanc_shift_num[51:0] = {frac_num[6:0], 45'b000000000000000000000000000000000000000000000}; + 52'b00000000000000000000000000000000000000000000001zzzzz: fanc_shift_num[51:0] = {frac_num[5:0], 46'b0000000000000000000000000000000000000000000000}; + 52'b000000000000000000000000000000000000000000000001zzzz: fanc_shift_num[51:0] = {frac_num[4:0], 47'b00000000000000000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000000000000000001zzz: fanc_shift_num[51:0] = {frac_num[3:0], 48'b000000000000000000000000000000000000000000000000}; + 52'b00000000000000000000000000000000000000000000000001zz: fanc_shift_num[51:0] = {frac_num[2:0], 49'b0000000000000000000000000000000000000000000000000}; + 52'b000000000000000000000000000000000000000000000000001z: fanc_shift_num[51:0] = {frac_num[1:0], 50'b00000000000000000000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000000000000000000001: fanc_shift_num[51:0] = {frac_num[0:0], 51'b000000000000000000000000000000000000000000000000000}; + 52'b0000000000000000000000000000000000000000000000000000: fanc_shift_num[51:0] = 52'b0000000000000000000000000000000000000000000000000000; + default: fanc_shift_num[51:0] = 52'b0000000000000000000000000000000000000000000000000000; + endcase +endmodule +module pa_fdsu_pack_single ( + fdsu_ex4_denorm_to_tiny_frac, + fdsu_ex4_frac, + fdsu_ex4_nx, + fdsu_ex4_potnt_norm, + fdsu_ex4_result_nor, + fdsu_frbus_data, + fdsu_frbus_fflags, + fdsu_frbus_freg, + fdsu_yy_expnt_rst, + fdsu_yy_of, + fdsu_yy_of_rm_lfn, + fdsu_yy_potnt_of, + fdsu_yy_potnt_uf, + fdsu_yy_result_inf, + fdsu_yy_result_lfn, + fdsu_yy_result_sign, + fdsu_yy_rslt_denorm, + fdsu_yy_uf, + fdsu_yy_wb_freg +); + input wire fdsu_ex4_denorm_to_tiny_frac; + input wire [25:0] fdsu_ex4_frac; + input wire fdsu_ex4_nx; + input wire [1:0] fdsu_ex4_potnt_norm; + input wire fdsu_ex4_result_nor; + input wire [9:0] fdsu_yy_expnt_rst; + input wire fdsu_yy_of; + input wire fdsu_yy_of_rm_lfn; + input wire fdsu_yy_potnt_of; + input wire fdsu_yy_potnt_uf; + input wire fdsu_yy_result_inf; + input wire fdsu_yy_result_lfn; + input wire fdsu_yy_result_sign; + input wire fdsu_yy_rslt_denorm; + input wire fdsu_yy_uf; + input wire [4:0] fdsu_yy_wb_freg; + output wire [31:0] fdsu_frbus_data; + output wire [4:0] fdsu_frbus_fflags; + output wire [4:0] fdsu_frbus_freg; + reg [22:0] ex4_frac_23; + reg [31:0] ex4_result; + reg [22:0] ex4_single_denorm_frac; + reg [9:0] expnt_add_op1; + wire ex4_cor_nx; + wire ex4_cor_uf; + wire ex4_denorm_potnt_norm; + wire [31:0] ex4_denorm_result; + wire [9:0] ex4_expnt_rst; + wire [4:0] ex4_expt; + wire ex4_final_rst_norm; + wire [25:0] ex4_frac; + wire ex4_of_plus; + wire ex4_result_inf; + wire ex4_result_lfn; + wire ex4_rslt_denorm; + wire [31:0] ex4_rst_inf; + wire [31:0] ex4_rst_lfn; + wire ex4_rst_nor; + wire [31:0] ex4_rst_norm; + wire ex4_uf_plus; + wire fdsu_ex4_dz; + wire [9:0] fdsu_ex4_expnt_rst; + wire fdsu_ex4_nv; + wire fdsu_ex4_of; + wire fdsu_ex4_of_rst_lfn; + wire fdsu_ex4_potnt_of; + wire fdsu_ex4_potnt_uf; + wire fdsu_ex4_result_inf; + wire fdsu_ex4_result_lfn; + wire fdsu_ex4_result_sign; + wire fdsu_ex4_rslt_denorm; + wire fdsu_ex4_uf; + assign fdsu_ex4_result_sign = fdsu_yy_result_sign; + assign fdsu_ex4_of_rst_lfn = fdsu_yy_of_rm_lfn; + assign fdsu_ex4_result_inf = fdsu_yy_result_inf; + assign fdsu_ex4_result_lfn = fdsu_yy_result_lfn; + assign fdsu_ex4_of = fdsu_yy_of; + assign fdsu_ex4_uf = fdsu_yy_uf; + assign fdsu_ex4_potnt_of = fdsu_yy_potnt_of; + assign fdsu_ex4_potnt_uf = fdsu_yy_potnt_uf; + assign fdsu_ex4_nv = 1'b0; + assign fdsu_ex4_dz = 1'b0; + assign fdsu_ex4_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; + assign fdsu_ex4_rslt_denorm = fdsu_yy_rslt_denorm; + assign ex4_frac[25:0] = fdsu_ex4_frac[25:0]; + always @(ex4_frac[25:24]) + casez (ex4_frac[25:24]) + 2'b00: expnt_add_op1[9:0] = 10'h1ff; + 2'b01: expnt_add_op1[9:0] = 10'h000; + 2'b1z: expnt_add_op1[9:0] = 10'h001; + default: expnt_add_op1[9:0] = 10'b0000000000; + endcase + assign ex4_expnt_rst[9:0] = fdsu_ex4_expnt_rst[9:0] + expnt_add_op1[9:0]; + always @(fdsu_ex4_expnt_rst[9:0] or fdsu_ex4_denorm_to_tiny_frac or ex4_frac[25:1]) + case (fdsu_ex4_expnt_rst[9:0]) + 10'h001: ex4_single_denorm_frac[22:0] = {ex4_frac[23:1]}; + 10'h000: ex4_single_denorm_frac[22:0] = {ex4_frac[24:2]}; + 10'h3ff: ex4_single_denorm_frac[22:0] = {ex4_frac[25:3]}; + 10'h3fe: ex4_single_denorm_frac[22:0] = {1'b0, ex4_frac[25:4]}; + 10'h3fd: ex4_single_denorm_frac[22:0] = {2'b00, ex4_frac[25:5]}; + 10'h3fc: ex4_single_denorm_frac[22:0] = {3'b000, ex4_frac[25:6]}; + 10'h3fb: ex4_single_denorm_frac[22:0] = {4'b0000, ex4_frac[25:7]}; + 10'h3fa: ex4_single_denorm_frac[22:0] = {5'b00000, ex4_frac[25:8]}; + 10'h3f9: ex4_single_denorm_frac[22:0] = {6'b000000, ex4_frac[25:9]}; + 10'h3f8: ex4_single_denorm_frac[22:0] = {7'b0000000, ex4_frac[25:10]}; + 10'h3f7: ex4_single_denorm_frac[22:0] = {8'b00000000, ex4_frac[25:11]}; + 10'h3f6: ex4_single_denorm_frac[22:0] = {9'b000000000, ex4_frac[25:12]}; + 10'h3f5: ex4_single_denorm_frac[22:0] = {10'b0000000000, ex4_frac[25:13]}; + 10'h3f4: ex4_single_denorm_frac[22:0] = {11'b00000000000, ex4_frac[25:14]}; + 10'h3f3: ex4_single_denorm_frac[22:0] = {12'b000000000000, ex4_frac[25:15]}; + 10'h3f2: ex4_single_denorm_frac[22:0] = {13'b0000000000000, ex4_frac[25:16]}; + 10'h3f1: ex4_single_denorm_frac[22:0] = {14'b00000000000000, ex4_frac[25:17]}; + 10'h3f0: ex4_single_denorm_frac[22:0] = {15'b000000000000000, ex4_frac[25:18]}; + 10'h3ef: ex4_single_denorm_frac[22:0] = {16'b0000000000000000, ex4_frac[25:19]}; + 10'h3ee: ex4_single_denorm_frac[22:0] = {17'b00000000000000000, ex4_frac[25:20]}; + 10'h3ed: ex4_single_denorm_frac[22:0] = {18'b000000000000000000, ex4_frac[25:21]}; + 10'h3ec: ex4_single_denorm_frac[22:0] = {19'b0000000000000000000, ex4_frac[25:22]}; + 10'h3eb: ex4_single_denorm_frac[22:0] = {20'b00000000000000000000, ex4_frac[25:23]}; + 10'h3ea: ex4_single_denorm_frac[22:0] = {21'b000000000000000000000, ex4_frac[25:24]}; + default: ex4_single_denorm_frac[22:0] = (fdsu_ex4_denorm_to_tiny_frac ? 23'b00000000000000000000001 : 23'b00000000000000000000000); + endcase + assign ex4_denorm_potnt_norm = (fdsu_ex4_potnt_norm[1] && ex4_frac[24]) || (fdsu_ex4_potnt_norm[0] && ex4_frac[25]); + assign ex4_rslt_denorm = fdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm; + assign ex4_denorm_result[31:0] = {fdsu_ex4_result_sign, 8'h00, ex4_single_denorm_frac[22:0]}; + assign ex4_rst_nor = fdsu_ex4_result_nor; + assign ex4_of_plus = (fdsu_ex4_potnt_of && |ex4_frac[25:24]) && ex4_rst_nor; + assign ex4_uf_plus = (fdsu_ex4_potnt_uf && ~|ex4_frac[25:24]) && ex4_rst_nor; + assign ex4_result_lfn = (ex4_of_plus && fdsu_ex4_of_rst_lfn) || fdsu_ex4_result_lfn; + assign ex4_result_inf = (ex4_of_plus && !fdsu_ex4_of_rst_lfn) || fdsu_ex4_result_inf; + assign ex4_rst_lfn[31:0] = {fdsu_ex4_result_sign, 8'hfe, {23 {1'b1}}}; + assign ex4_rst_inf[31:0] = {fdsu_ex4_result_sign, 31'h7f800000}; + always @(ex4_frac[25:0]) + casez (ex4_frac[25:24]) + 2'b00: ex4_frac_23[22:0] = ex4_frac[22:0]; + 2'b01: ex4_frac_23[22:0] = ex4_frac[23:1]; + 2'b1z: ex4_frac_23[22:0] = ex4_frac[24:2]; + default: ex4_frac_23[22:0] = 23'b00000000000000000000000; + endcase + assign ex4_rst_norm[31:0] = {fdsu_ex4_result_sign, ex4_expnt_rst[7:0], ex4_frac_23[22:0]}; + assign ex4_cor_uf = ((fdsu_ex4_uf || ex4_denorm_potnt_norm) || ex4_uf_plus) && fdsu_ex4_nx; + assign ex4_cor_nx = (fdsu_ex4_nx || fdsu_ex4_of) || ex4_of_plus; + assign ex4_expt[4:0] = {fdsu_ex4_nv, fdsu_ex4_dz, fdsu_ex4_of | ex4_of_plus, ex4_cor_uf, ex4_cor_nx}; + assign ex4_final_rst_norm = (!ex4_result_inf && !ex4_result_lfn) && !ex4_rslt_denorm; + always @(ex4_denorm_result[31:0] or ex4_result_lfn or ex4_result_inf or ex4_final_rst_norm or ex4_rst_norm[31:0] or ex4_rst_lfn[31:0] or ex4_rst_inf[31:0] or ex4_rslt_denorm) + case ({ex4_rslt_denorm, ex4_result_inf, ex4_result_lfn, ex4_final_rst_norm}) + 4'b1000: ex4_result[31:0] = ex4_denorm_result[31:0]; + 4'b0100: ex4_result[31:0] = ex4_rst_inf[31:0]; + 4'b0010: ex4_result[31:0] = ex4_rst_lfn[31:0]; + 4'b0001: ex4_result[31:0] = ex4_rst_norm[31:0]; + default: ex4_result[31:0] = 32'b00000000000000000000000000000000; + endcase + assign fdsu_frbus_freg[4:0] = fdsu_yy_wb_freg[4:0]; + assign fdsu_frbus_data[31:0] = ex4_result[31:0]; + assign fdsu_frbus_fflags[4:0] = ex4_expt[4:0]; +endmodule +module pa_fdsu_prepare ( + dp_xx_ex1_rm, + ex1_div, + ex1_divisor, + ex1_expnt_adder_op0, + ex1_expnt_adder_op1, + ex1_of_result_lfn, + ex1_op0_id, + ex1_op0_sign, + ex1_op1_id, + ex1_op1_id_vld, + ex1_op1_sel, + ex1_oper_id_expnt, + ex1_oper_id_expnt_f, + ex1_oper_id_frac, + ex1_oper_id_frac_f, + ex1_remainder, + ex1_result_sign, + ex1_rm, + ex1_sqrt, + fdsu_ex1_sel, + idu_fpu_ex1_func, + idu_fpu_ex1_srcf0, + idu_fpu_ex1_srcf1 +); + input wire [2:0] dp_xx_ex1_rm; + input wire ex1_op0_id; + input wire ex1_op1_id; + input wire ex1_op1_sel; + input wire [12:0] ex1_oper_id_expnt_f; + input wire [51:0] ex1_oper_id_frac_f; + input wire fdsu_ex1_sel; + input wire [9:0] idu_fpu_ex1_func; + input wire [31:0] idu_fpu_ex1_srcf0; + input wire [31:0] idu_fpu_ex1_srcf1; + output wire ex1_div; + output wire [23:0] ex1_divisor; + output wire [12:0] ex1_expnt_adder_op0; + output reg [12:0] ex1_expnt_adder_op1; + output reg ex1_of_result_lfn; + output wire ex1_op0_sign; + output wire ex1_op1_id_vld; + output wire [12:0] ex1_oper_id_expnt; + output wire [51:0] ex1_oper_id_frac; + output wire [31:0] ex1_remainder; + output wire ex1_result_sign; + output wire [2:0] ex1_rm; + output wire ex1_sqrt; + wire div_sign; + wire [52:0] ex1_div_noid_nor_srt_op0; + wire [52:0] ex1_div_noid_nor_srt_op1; + wire [52:0] ex1_div_nor_srt_op0; + wire [52:0] ex1_div_nor_srt_op1; + wire [12:0] ex1_div_op0_expnt; + wire [12:0] ex1_div_op1_expnt; + wire [52:0] ex1_div_srt_op0; + wire [52:0] ex1_div_srt_op1; + wire ex1_double; + wire ex1_op0_id_nor; + wire ex1_op1_id_nor; + wire ex1_op1_sign; + wire [63:0] ex1_oper0; + wire [51:0] ex1_oper0_frac; + wire [12:0] ex1_oper0_id_expnt; + wire [51:0] ex1_oper0_id_frac; + wire [63:0] ex1_oper1; + wire [51:0] ex1_oper1_frac; + wire [12:0] ex1_oper1_id_expnt; + wire [51:0] ex1_oper1_id_frac; + wire [51:0] ex1_oper_frac; + wire ex1_single; + wire ex1_sqrt_expnt_odd; + wire ex1_sqrt_op0_expnt_0; + wire [12:0] ex1_sqrt_op1_expnt; + wire [52:0] ex1_sqrt_srt_op0; + wire [59:0] sqrt_remainder; + wire sqrt_sign; + assign ex1_sqrt = idu_fpu_ex1_func[0]; + assign ex1_div = idu_fpu_ex1_func[1]; + assign ex1_oper0[63:0] = {32'b00000000000000000000000000000000, idu_fpu_ex1_srcf0[31:0] & {32 {fdsu_ex1_sel}}}; + assign ex1_oper1[63:0] = {32'b00000000000000000000000000000000, idu_fpu_ex1_srcf1[31:0] & {32 {fdsu_ex1_sel}}}; + assign ex1_double = 1'b0; + assign ex1_single = 1'b1; + assign ex1_op0_id_nor = ex1_op0_id; + assign ex1_op1_id_nor = ex1_op1_id; + assign ex1_op0_sign = (ex1_double && ex1_oper0[63]) || (ex1_single && ex1_oper0[31]); + assign ex1_op1_sign = (ex1_double && ex1_oper1[63]) || (ex1_single && ex1_oper1[31]); + assign div_sign = ex1_op0_sign ^ ex1_op1_sign; + assign sqrt_sign = ex1_op0_sign; + assign ex1_result_sign = (ex1_div ? div_sign : sqrt_sign); + assign ex1_oper_frac[51:0] = (ex1_op1_sel ? ex1_oper1_frac[51:0] : ex1_oper0_frac[51:0]); + pa_fdsu_ff1 x_frac_expnt( + .fanc_shift_num(ex1_oper_id_frac[51:0]), + .frac_bin_val(ex1_oper_id_expnt[12:0]), + .frac_num(ex1_oper_frac[51:0]) + ); + assign ex1_oper0_id_expnt[12:0] = (ex1_op1_sel ? ex1_oper_id_expnt_f[12:0] : ex1_oper_id_expnt[12:0]); + assign ex1_oper0_id_frac[51:0] = (ex1_op1_sel ? ex1_oper_id_frac_f[51:0] : ex1_oper_id_frac[51:0]); + assign ex1_oper1_id_expnt[12:0] = ex1_oper_id_expnt[12:0]; + assign ex1_oper1_id_frac[51:0] = ex1_oper_id_frac[51:0]; + assign ex1_oper0_frac[51:0] = ({52 {ex1_double}} & ex1_oper0[51:0]) | ({52 {ex1_single}} & {ex1_oper0[22:0], 29'b00000000000000000000000000000}); + assign ex1_oper1_frac[51:0] = ({52 {ex1_double}} & ex1_oper1[51:0]) | ({52 {ex1_single}} & {ex1_oper1[22:0], 29'b00000000000000000000000000000}); + assign ex1_div_op0_expnt[12:0] = ({13 {ex1_double}} & {2'b00, ex1_oper0[62:52]}) | ({13 {ex1_single}} & {5'b00000, ex1_oper0[30:23]}); + assign ex1_expnt_adder_op0[12:0] = (ex1_op0_id_nor ? ex1_oper0_id_expnt[12:0] : ex1_div_op0_expnt[12:0]); + assign ex1_div_op1_expnt[12:0] = ({13 {ex1_double}} & {2'b00, ex1_oper1[62:52]}) | ({13 {ex1_single}} & {5'b00000, ex1_oper1[30:23]}); + assign ex1_sqrt_op1_expnt[12:0] = ({13 {ex1_double}} & {3'b000, {10 {1'b1}}}) | ({13 {ex1_single}} & {6'b000000, {7 {1'b1}}}); + always @(ex1_oper1_id_expnt[12:0] or ex1_div or ex1_op1_id_nor or ex1_sqrt_op1_expnt[12:0] or ex1_sqrt or ex1_div_op1_expnt[12:0]) + case ({ex1_div, ex1_sqrt}) + 2'b10: ex1_expnt_adder_op1[12:0] = (ex1_op1_id_nor ? ex1_oper1_id_expnt[12:0] : ex1_div_op1_expnt[12:0]); + 2'b01: ex1_expnt_adder_op1[12:0] = ex1_sqrt_op1_expnt[12:0]; + default: ex1_expnt_adder_op1[12:0] = 13'b0000000000000; + endcase + assign ex1_sqrt_op0_expnt_0 = (ex1_op0_id_nor ? ex1_oper_id_expnt[0] : ex1_div_op0_expnt[0]); + assign ex1_sqrt_expnt_odd = !ex1_sqrt_op0_expnt_0; + assign ex1_rm[2:0] = dp_xx_ex1_rm[2:0]; + always @(ex1_rm[2:0] or ex1_result_sign) + case (ex1_rm[2:0]) + 3'b000: ex1_of_result_lfn = 1'b0; + 3'b001: ex1_of_result_lfn = 1'b1; + 3'b010: ex1_of_result_lfn = !ex1_result_sign; + 3'b011: ex1_of_result_lfn = ex1_result_sign; + 3'b100: ex1_of_result_lfn = 1'b0; + default: ex1_of_result_lfn = 1'b0; + endcase + assign ex1_remainder[31:0] = ({32 {ex1_div}} & {5'b00000, ex1_div_srt_op0[52:28], 2'b00}) | ({32 {ex1_sqrt}} & sqrt_remainder[59:28]); + assign ex1_divisor[23:0] = ex1_div_srt_op1[52:29]; + assign ex1_div_srt_op0[52:0] = ex1_div_nor_srt_op0[52:0]; + assign ex1_div_srt_op1[52:0] = ex1_div_nor_srt_op1[52:0]; + assign ex1_div_noid_nor_srt_op0[52:0] = ({53 {ex1_double}} & {1'b1, ex1_oper0[51:0]}) | ({53 {ex1_single}} & {1'b1, ex1_oper0[22:0], 29'b00000000000000000000000000000}); + assign ex1_div_nor_srt_op0[52:0] = (ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0], 1'b0} : ex1_div_noid_nor_srt_op0[52:0]); + assign ex1_div_noid_nor_srt_op1[52:0] = ({53 {ex1_double}} & {1'b1, ex1_oper1[51:0]}) | ({53 {ex1_single}} & {1'b1, ex1_oper1[22:0], 29'b00000000000000000000000000000}); + assign ex1_div_nor_srt_op1[52:0] = (ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0], 1'b0} : ex1_div_noid_nor_srt_op1[52:0]); + assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd ? {5'b00000, ex1_sqrt_srt_op0[52:0], 2'b00} : {6'b000000, ex1_sqrt_srt_op0[52:0], 1'b0}); + assign ex1_sqrt_srt_op0[52:0] = ex1_div_srt_op0[52:0]; + assign ex1_op1_id_vld = ex1_op1_id_nor && ex1_div; +endmodule +module pa_fdsu_round_single ( + cp0_fpu_icg_en, + cp0_yy_clk_en, + ex3_expnt_adjust_result, + ex3_frac_final_rst, + ex3_pipedown, + ex3_rslt_denorm, + fdsu_ex3_id_srt_skip, + fdsu_ex3_rem_sign, + fdsu_ex3_rem_zero, + fdsu_ex3_result_denorm_round_add_num, + fdsu_ex4_denorm_to_tiny_frac, + fdsu_ex4_nx, + fdsu_ex4_potnt_norm, + fdsu_ex4_result_nor, + fdsu_yy_expnt_rst, + fdsu_yy_result_inf, + fdsu_yy_result_lfn, + fdsu_yy_result_sign, + fdsu_yy_rm, + fdsu_yy_rslt_denorm, + forever_cpuclk, + pad_yy_icg_scan_en, + total_qt_rt_30 +); + input wire cp0_fpu_icg_en; + input wire cp0_yy_clk_en; + input wire ex3_pipedown; + input wire fdsu_ex3_id_srt_skip; + input wire fdsu_ex3_rem_sign; + input wire fdsu_ex3_rem_zero; + input wire [23:0] fdsu_ex3_result_denorm_round_add_num; + input wire [9:0] fdsu_yy_expnt_rst; + input wire fdsu_yy_result_inf; + input wire fdsu_yy_result_lfn; + input wire fdsu_yy_result_sign; + input wire [2:0] fdsu_yy_rm; + input wire fdsu_yy_rslt_denorm; + input wire forever_cpuclk; + input wire pad_yy_icg_scan_en; + input wire [29:0] total_qt_rt_30; + output wire [9:0] ex3_expnt_adjust_result; + output wire [25:0] ex3_frac_final_rst; + output wire ex3_rslt_denorm; + output reg fdsu_ex4_denorm_to_tiny_frac; + output reg fdsu_ex4_nx; + output reg [1:0] fdsu_ex4_potnt_norm; + output reg fdsu_ex4_result_nor; + reg denorm_to_tiny_frac; + reg [25:0] frac_add1_op1; + reg frac_add_1; + reg frac_orig; + reg [25:0] frac_sub1_op1; + reg frac_sub_1; + reg [27:0] qt_result_single_denorm_for_round; + reg single_denorm_lst_frac; + wire ex3_denorm_eq; + wire ex3_denorm_gr; + wire ex3_denorm_lst_frac; + wire ex3_denorm_nx; + wire ex3_denorm_plus; + wire ex3_denorm_potnt_norm; + wire ex3_denorm_zero; + wire [9:0] ex3_expnt_adjst; + wire ex3_nx; + wire ex3_pipe_clk; + wire ex3_pipe_clk_en; + wire [1:0] ex3_potnt_norm; + wire ex3_qt_eq; + wire ex3_qt_gr; + wire ex3_qt_sing_lo3_not0; + wire ex3_qt_sing_lo4_not0; + wire ex3_qt_zero; + wire ex3_rst_eq_1; + wire ex3_rst_nor; + wire ex3_single_denorm_eq; + wire ex3_single_denorm_gr; + wire ex3_single_denorm_zero; + wire ex3_single_low_not_zero; + wire [9:0] fdsu_ex3_expnt_rst; + wire fdsu_ex3_result_inf; + wire fdsu_ex3_result_lfn; + wire fdsu_ex3_result_sign; + wire [2:0] fdsu_ex3_rm; + wire fdsu_ex3_rslt_denorm; + wire [25:0] frac_add1_op1_with_denorm; + wire [25:0] frac_add1_rst; + wire frac_denorm_rdn_add_1; + wire frac_denorm_rdn_sub_1; + wire frac_denorm_rmm_add_1; + wire frac_denorm_rne_add_1; + wire frac_denorm_rtz_sub_1; + wire frac_denorm_rup_add_1; + wire frac_denorm_rup_sub_1; + wire [25:0] frac_final_rst; + wire frac_rdn_add_1; + wire frac_rdn_sub_1; + wire frac_rmm_add_1; + wire frac_rne_add_1; + wire frac_rtz_sub_1; + wire frac_rup_add_1; + wire frac_rup_sub_1; + wire [25:0] frac_sub1_op1_with_denorm; + wire [25:0] frac_sub1_rst; + assign fdsu_ex3_result_sign = fdsu_yy_result_sign; + assign fdsu_ex3_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; + assign fdsu_ex3_result_inf = fdsu_yy_result_inf; + assign fdsu_ex3_result_lfn = fdsu_yy_result_lfn; + assign fdsu_ex3_rm[2:0] = fdsu_yy_rm[2:0]; + assign fdsu_ex3_rslt_denorm = fdsu_yy_rslt_denorm; + assign ex3_qt_sing_lo4_not0 = |total_qt_rt_30[3:0]; + assign ex3_qt_sing_lo3_not0 = |total_qt_rt_30[2:0]; + assign ex3_qt_gr = (total_qt_rt_30[28] ? total_qt_rt_30[4] && ex3_qt_sing_lo4_not0 : total_qt_rt_30[3] && ex3_qt_sing_lo3_not0); + assign ex3_qt_eq = (total_qt_rt_30[28] ? total_qt_rt_30[4] && !ex3_qt_sing_lo4_not0 : total_qt_rt_30[3] && !ex3_qt_sing_lo3_not0); + assign ex3_qt_zero = (total_qt_rt_30[28] ? ~|total_qt_rt_30[4:0] : ~|total_qt_rt_30[3:0]); + assign ex3_rst_eq_1 = total_qt_rt_30[28] && ~|total_qt_rt_30[27:5]; + assign ex3_denorm_plus = !total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h382); + assign ex3_denorm_potnt_norm = total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h381); + assign ex3_rslt_denorm = ex3_denorm_plus || fdsu_ex3_rslt_denorm; + always @(total_qt_rt_30[28:0] or fdsu_ex3_expnt_rst[9:0]) + case (fdsu_ex3_expnt_rst[9:0]) + 10'h382: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[4:0], 23'b00000000000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[5]; + end + 10'h381: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[5:0], 22'b0000000000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[6]; + end + 10'h380: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[6:0], 21'b000000000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[7]; + end + 10'h37f: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[7:0], 20'b00000000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[8]; + end + 10'h37e: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[8:0], 19'b0000000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[9]; + end + 10'h37d: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[9:0], 18'b000000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[10]; + end + 10'h37c: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[10:0], 17'b00000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[11]; + end + 10'h37b: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[11:0], 16'b0000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[12]; + end + 10'h37a: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[12:0], 15'b000000000000000}; + single_denorm_lst_frac = total_qt_rt_30[13]; + end + 10'h379: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[13:0], 14'b00000000000000}; + single_denorm_lst_frac = total_qt_rt_30[14]; + end + 10'h378: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[14:0], 13'b0000000000000}; + single_denorm_lst_frac = total_qt_rt_30[15]; + end + 10'h377: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[15:0], 12'b000000000000}; + single_denorm_lst_frac = total_qt_rt_30[16]; + end + 10'h376: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[16:0], 11'b00000000000}; + single_denorm_lst_frac = total_qt_rt_30[17]; + end + 10'h375: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[17:0], 10'b0000000000}; + single_denorm_lst_frac = total_qt_rt_30[18]; + end + 10'h374: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[18:0], 9'b000000000}; + single_denorm_lst_frac = total_qt_rt_30[19]; + end + 10'h373: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[19:0], 8'b00000000}; + single_denorm_lst_frac = total_qt_rt_30[20]; + end + 10'h372: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[20:0], 7'b0000000}; + single_denorm_lst_frac = total_qt_rt_30[21]; + end + 10'h371: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[21:0], 6'b000000}; + single_denorm_lst_frac = total_qt_rt_30[22]; + end + 10'h370: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[22:0], 5'b00000}; + single_denorm_lst_frac = total_qt_rt_30[23]; + end + 10'h36f: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[23:0], 4'b0000}; + single_denorm_lst_frac = total_qt_rt_30[24]; + end + 10'h36e: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[24:0], 3'b000}; + single_denorm_lst_frac = total_qt_rt_30[25]; + end + 10'h36d: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[25:0], 2'b00}; + single_denorm_lst_frac = total_qt_rt_30[26]; + end + 10'h36c: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[26:0], 1'b0}; + single_denorm_lst_frac = total_qt_rt_30[27]; + end + 10'h36b: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[27:0]}; + single_denorm_lst_frac = total_qt_rt_30[28]; + end + default: begin + qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[28:1]}; + single_denorm_lst_frac = 1'b0; + end + endcase + assign ex3_single_denorm_eq = qt_result_single_denorm_for_round[27] && !ex3_single_low_not_zero; + assign ex3_single_low_not_zero = |qt_result_single_denorm_for_round[26:0]; + assign ex3_single_denorm_gr = qt_result_single_denorm_for_round[27] && ex3_single_low_not_zero; + assign ex3_single_denorm_zero = !qt_result_single_denorm_for_round[27] && !ex3_single_low_not_zero; + assign ex3_denorm_eq = ex3_single_denorm_eq; + assign ex3_denorm_gr = ex3_single_denorm_gr; + assign ex3_denorm_zero = ex3_single_denorm_zero; + assign ex3_denorm_lst_frac = single_denorm_lst_frac; + assign frac_rne_add_1 = ex3_qt_gr || (ex3_qt_eq && !fdsu_ex3_rem_sign); + assign frac_rtz_sub_1 = ex3_qt_zero && fdsu_ex3_rem_sign; + assign frac_rup_add_1 = !fdsu_ex3_result_sign && (!ex3_qt_zero || (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); + assign frac_rup_sub_1 = fdsu_ex3_result_sign && (ex3_qt_zero && fdsu_ex3_rem_sign); + assign frac_rdn_add_1 = fdsu_ex3_result_sign && (!ex3_qt_zero || (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); + assign frac_rdn_sub_1 = !fdsu_ex3_result_sign && (ex3_qt_zero && fdsu_ex3_rem_sign); + assign frac_rmm_add_1 = ex3_qt_gr || (ex3_qt_eq && !fdsu_ex3_rem_sign); + assign frac_denorm_rne_add_1 = ex3_denorm_gr || (ex3_denorm_eq && ((fdsu_ex3_rem_zero && ex3_denorm_lst_frac) || (!fdsu_ex3_rem_zero && !fdsu_ex3_rem_sign))); + assign frac_denorm_rtz_sub_1 = ex3_denorm_zero && fdsu_ex3_rem_sign; + assign frac_denorm_rup_add_1 = !fdsu_ex3_result_sign && (!ex3_denorm_zero || (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); + assign frac_denorm_rup_sub_1 = fdsu_ex3_result_sign && (ex3_denorm_zero && fdsu_ex3_rem_sign); + assign frac_denorm_rdn_add_1 = fdsu_ex3_result_sign && (!ex3_denorm_zero || (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); + assign frac_denorm_rdn_sub_1 = !fdsu_ex3_result_sign && (ex3_denorm_zero && fdsu_ex3_rem_sign); + assign frac_denorm_rmm_add_1 = ex3_denorm_gr || (ex3_denorm_eq && !fdsu_ex3_rem_sign); + always @(fdsu_ex3_rm[2:0] or frac_denorm_rdn_add_1 or frac_rne_add_1 or frac_denorm_rdn_sub_1 or fdsu_ex3_result_sign or frac_rup_add_1 or frac_denorm_rup_sub_1 or frac_rdn_sub_1 or frac_rtz_sub_1 or frac_rdn_add_1 or fdsu_ex3_id_srt_skip or frac_denorm_rtz_sub_1 or ex3_rslt_denorm or frac_rup_sub_1 or frac_denorm_rmm_add_1 or frac_denorm_rup_add_1 or frac_denorm_rne_add_1 or frac_rmm_add_1) + case (fdsu_ex3_rm[2:0]) + 3'b000: begin + frac_add_1 = (ex3_rslt_denorm ? frac_denorm_rne_add_1 : frac_rne_add_1); + frac_sub_1 = 1'b0; + frac_orig = (ex3_rslt_denorm ? !frac_denorm_rne_add_1 : !frac_rne_add_1); + denorm_to_tiny_frac = (fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rne_add_1); + end + 3'b001: begin + frac_add_1 = 1'b0; + frac_sub_1 = (ex3_rslt_denorm ? frac_denorm_rtz_sub_1 : frac_rtz_sub_1); + frac_orig = (ex3_rslt_denorm ? !frac_denorm_rtz_sub_1 : !frac_rtz_sub_1); + denorm_to_tiny_frac = 1'b0; + end + 3'b010: begin + frac_add_1 = (ex3_rslt_denorm ? frac_denorm_rdn_add_1 : frac_rdn_add_1); + frac_sub_1 = (ex3_rslt_denorm ? frac_denorm_rdn_sub_1 : frac_rdn_sub_1); + frac_orig = (ex3_rslt_denorm ? !frac_denorm_rdn_add_1 && !frac_denorm_rdn_sub_1 : !frac_rdn_add_1 && !frac_rdn_sub_1); + denorm_to_tiny_frac = (fdsu_ex3_id_srt_skip ? fdsu_ex3_result_sign : frac_denorm_rdn_add_1); + end + 3'b011: begin + frac_add_1 = (ex3_rslt_denorm ? frac_denorm_rup_add_1 : frac_rup_add_1); + frac_sub_1 = (ex3_rslt_denorm ? frac_denorm_rup_sub_1 : frac_rup_sub_1); + frac_orig = (ex3_rslt_denorm ? !frac_denorm_rup_add_1 && !frac_denorm_rup_sub_1 : !frac_rup_add_1 && !frac_rup_sub_1); + denorm_to_tiny_frac = (fdsu_ex3_id_srt_skip ? !fdsu_ex3_result_sign : frac_denorm_rup_add_1); + end + 3'b100: begin + frac_add_1 = (ex3_rslt_denorm ? frac_denorm_rmm_add_1 : frac_rmm_add_1); + frac_sub_1 = 1'b0; + frac_orig = (ex3_rslt_denorm ? !frac_denorm_rmm_add_1 : !frac_rmm_add_1); + denorm_to_tiny_frac = (fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rmm_add_1); + end + default: begin + frac_add_1 = 1'b0; + frac_sub_1 = 1'b0; + frac_orig = 1'b0; + denorm_to_tiny_frac = 1'b0; + end + endcase + always @(total_qt_rt_30[28]) + case (total_qt_rt_30[28]) + 1'b0: begin + frac_add1_op1[25:0] = 26'b00000000000000000000000001; + frac_sub1_op1[25:0] = {2'b11, {24 {1'b1}}}; + end + 1'b1: begin + frac_add1_op1[25:0] = 26'b00000000000000000000000010; + frac_sub1_op1[25:0] = {{25 {1'b1}}, 1'b0}; + end + default: begin + frac_add1_op1[25:0] = 26'b00000000000000000000000000; + frac_sub1_op1[25:0] = 26'b00000000000000000000000000; + end + endcase + assign frac_add1_rst[25:0] = {1'b0, total_qt_rt_30[28:4]} + frac_add1_op1_with_denorm[25:0]; + assign frac_add1_op1_with_denorm[25:0] = (ex3_rslt_denorm ? {1'b0, fdsu_ex3_result_denorm_round_add_num[23:0], 1'b0} : frac_add1_op1[25:0]); + assign frac_sub1_rst[25:0] = (ex3_rst_eq_1 ? {3'b000, {23 {1'b1}}} : ({1'b0, total_qt_rt_30[28:4]} + frac_sub1_op1_with_denorm[25:0]) + {25'b0000000000000000000000000, ex3_rslt_denorm}); + assign frac_sub1_op1_with_denorm[25:0] = (ex3_rslt_denorm ? ~{1'b0, fdsu_ex3_result_denorm_round_add_num[23:0], 1'b0} : frac_sub1_op1[25:0]); + assign frac_final_rst[25:0] = ((frac_add1_rst[25:0] & {26 {frac_add_1}}) | (frac_sub1_rst[25:0] & {26 {frac_sub_1}})) | ({1'b0, total_qt_rt_30[28:4]} & {26 {frac_orig}}); + assign ex3_rst_nor = !fdsu_ex3_result_inf && !fdsu_ex3_result_lfn; + assign ex3_nx = ex3_rst_nor && ((!ex3_qt_zero || !fdsu_ex3_rem_zero) || ex3_denorm_nx); + assign ex3_denorm_nx = ex3_rslt_denorm && (!ex3_denorm_zero || !fdsu_ex3_rem_zero); + assign ex3_expnt_adjst[9:0] = 10'h07f; + assign ex3_expnt_adjust_result[9:0] = fdsu_ex3_expnt_rst[9:0] + ex3_expnt_adjst[9:0]; + assign ex3_potnt_norm[1:0] = {ex3_denorm_plus, ex3_denorm_potnt_norm}; + gated_clk_cell x_ex3_pipe_clk( + .clk_in(forever_cpuclk), + .clk_out(ex3_pipe_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(ex3_pipe_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign ex3_pipe_clk_en = ex3_pipedown; + always @(posedge ex3_pipe_clk) + if (ex3_pipedown) begin + fdsu_ex4_result_nor <= ex3_rst_nor; + fdsu_ex4_nx <= ex3_nx; + fdsu_ex4_denorm_to_tiny_frac <= denorm_to_tiny_frac; + fdsu_ex4_potnt_norm[1:0] <= ex3_potnt_norm[1:0]; + end + else begin + fdsu_ex4_result_nor <= fdsu_ex4_result_nor; + fdsu_ex4_nx <= fdsu_ex4_nx; + fdsu_ex4_denorm_to_tiny_frac <= fdsu_ex4_denorm_to_tiny_frac; + fdsu_ex4_potnt_norm[1:0] <= fdsu_ex4_potnt_norm[1:0]; + end + assign ex3_frac_final_rst[25:0] = frac_final_rst[25:0]; +endmodule +module pa_fdsu_special ( + cp0_fpu_xx_dqnan, + dp_xx_ex1_cnan, + dp_xx_ex1_id, + dp_xx_ex1_inf, + dp_xx_ex1_qnan, + dp_xx_ex1_snan, + dp_xx_ex1_zero, + ex1_div, + ex1_op0_id, + ex1_op0_norm, + ex1_op0_sign, + ex1_op1_id, + ex1_op1_norm, + ex1_result_sign, + ex1_sqrt, + ex1_srt_skip, + fdsu_fpu_ex1_fflags, + fdsu_fpu_ex1_special_sel, + fdsu_fpu_ex1_special_sign +); + input wire cp0_fpu_xx_dqnan; + input wire [2:0] dp_xx_ex1_cnan; + input wire [2:0] dp_xx_ex1_id; + input wire [2:0] dp_xx_ex1_inf; + input wire [2:0] dp_xx_ex1_qnan; + input wire [2:0] dp_xx_ex1_snan; + input wire [2:0] dp_xx_ex1_zero; + input wire ex1_div; + input wire ex1_op0_sign; + input wire ex1_result_sign; + input wire ex1_sqrt; + output wire ex1_op0_id; + output wire ex1_op0_norm; + output wire ex1_op1_id; + output wire ex1_op1_norm; + output wire ex1_srt_skip; + output wire [4:0] fdsu_fpu_ex1_fflags; + output wire [7:0] fdsu_fpu_ex1_special_sel; + output wire [3:0] fdsu_fpu_ex1_special_sign; + reg ex1_result_cnan; + reg ex1_result_qnan_op0; + reg ex1_result_qnan_op1; + wire ex1_div_dz; + wire ex1_div_nv; + wire ex1_div_rst_inf; + wire ex1_div_rst_qnan; + wire ex1_div_rst_zero; + wire ex1_dz; + wire [4:0] ex1_fflags; + wire ex1_nv; + wire ex1_op0_cnan; + wire ex1_op0_inf; + wire ex1_op0_is_qnan; + wire ex1_op0_is_snan; + wire ex1_op0_qnan; + wire ex1_op0_snan; + wire ex1_op0_tt_zero; + wire ex1_op0_zero; + wire ex1_op1_cnan; + wire ex1_op1_inf; + wire ex1_op1_is_qnan; + wire ex1_op1_is_snan; + wire ex1_op1_qnan; + wire ex1_op1_snan; + wire ex1_op1_tt_zero; + wire ex1_op1_zero; + wire ex1_result_inf; + wire ex1_result_lfn; + wire ex1_result_qnan; + wire ex1_result_zero; + wire ex1_rst_default_qnan; + wire [7:0] ex1_special_sel; + wire [3:0] ex1_special_sign; + wire ex1_sqrt_nv; + wire ex1_sqrt_rst_inf; + wire ex1_sqrt_rst_qnan; + wire ex1_sqrt_rst_zero; + assign ex1_op0_inf = dp_xx_ex1_inf[0]; + assign ex1_op1_inf = dp_xx_ex1_inf[1]; + assign ex1_op0_zero = dp_xx_ex1_zero[0]; + assign ex1_op1_zero = dp_xx_ex1_zero[1]; + assign ex1_op0_id = dp_xx_ex1_id[0]; + assign ex1_op1_id = dp_xx_ex1_id[1]; + assign ex1_op0_cnan = dp_xx_ex1_cnan[0]; + assign ex1_op1_cnan = dp_xx_ex1_cnan[1]; + assign ex1_op0_snan = dp_xx_ex1_snan[0]; + assign ex1_op1_snan = dp_xx_ex1_snan[1]; + assign ex1_op0_qnan = dp_xx_ex1_qnan[0]; + assign ex1_op1_qnan = dp_xx_ex1_qnan[1]; + assign ex1_nv = (ex1_div && ex1_div_nv) || (ex1_sqrt && ex1_sqrt_nv); + assign ex1_div_nv = ((ex1_op0_snan || ex1_op1_snan) || (ex1_op0_tt_zero && ex1_op1_tt_zero)) || (ex1_op0_inf && ex1_op1_inf); + assign ex1_op0_tt_zero = ex1_op0_zero; + assign ex1_op1_tt_zero = ex1_op1_zero; + assign ex1_sqrt_nv = ex1_op0_snan || (ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf)); + assign ex1_op0_norm = (((!ex1_op0_inf && !ex1_op0_zero) && !ex1_op0_snan) && !ex1_op0_qnan) && !ex1_op0_cnan; + assign ex1_op1_norm = (((!ex1_op1_inf && !ex1_op1_zero) && !ex1_op1_snan) && !ex1_op1_qnan) && !ex1_op1_cnan; + assign ex1_dz = ex1_div && ex1_div_dz; + assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm; + assign ex1_result_zero = (ex1_div_rst_zero && ex1_div) || (ex1_sqrt_rst_zero && ex1_sqrt); + assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm) || ((((!ex1_op0_inf && !ex1_op0_qnan) && !ex1_op0_snan) && !ex1_op0_cnan) && ex1_op1_inf); + assign ex1_sqrt_rst_zero = ex1_op0_tt_zero; + assign ex1_result_qnan = ((ex1_div_rst_qnan && ex1_div) || (ex1_sqrt_rst_qnan && ex1_sqrt)) || ex1_nv; + assign ex1_div_rst_qnan = ex1_op0_qnan || ex1_op1_qnan; + assign ex1_sqrt_rst_qnan = ex1_op0_qnan; + assign ex1_rst_default_qnan = (((ex1_div && ex1_op0_zero) && ex1_op1_zero) || ((ex1_div && ex1_op0_inf) && ex1_op1_inf)) || ((ex1_sqrt && ex1_op0_sign) && (ex1_op0_norm || ex1_op0_inf)); + assign ex1_result_inf = ((ex1_div_rst_inf && ex1_div) || (ex1_sqrt_rst_inf && ex1_sqrt)) || ex1_dz; + assign ex1_div_rst_inf = (((ex1_op0_inf && !ex1_op1_inf) && !ex1_op1_qnan) && !ex1_op1_snan) && !ex1_op1_cnan; + assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign; + assign ex1_result_lfn = 1'b0; + assign ex1_op0_is_snan = ex1_op0_snan; + assign ex1_op1_is_snan = ex1_op1_snan && ex1_div; + assign ex1_op0_is_qnan = ex1_op0_qnan; + assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div; + always @(ex1_op0_is_snan or ex1_op0_cnan or ex1_result_qnan or ex1_op0_is_qnan or ex1_rst_default_qnan or cp0_fpu_xx_dqnan or ex1_op1_cnan or ex1_op1_is_qnan or ex1_op1_is_snan) + if (ex1_rst_default_qnan) begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = ex1_result_qnan; + end + else if (ex1_op0_is_snan && cp0_fpu_xx_dqnan) begin + ex1_result_qnan_op0 = ex1_result_qnan; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = 1'b0; + end + else if (ex1_op1_is_snan && cp0_fpu_xx_dqnan) begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = ex1_result_qnan; + ex1_result_cnan = 1'b0; + end + else if (ex1_op0_is_qnan && cp0_fpu_xx_dqnan) begin + ex1_result_qnan_op0 = ex1_result_qnan && !ex1_op0_cnan; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = ex1_result_qnan && ex1_op0_cnan; + end + else if (ex1_op1_is_qnan && cp0_fpu_xx_dqnan) begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = ex1_result_qnan && !ex1_op1_cnan; + ex1_result_cnan = ex1_result_qnan && ex1_op1_cnan; + end + else begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = ex1_result_qnan; + end + assign ex1_srt_skip = ((ex1_result_zero || ex1_result_qnan) || ex1_result_lfn) || ex1_result_inf; + assign ex1_fflags[4:0] = {ex1_nv, ex1_dz, 3'b000}; + assign ex1_special_sel[7:0] = {1'b0, ex1_result_qnan_op1, ex1_result_qnan_op0, ex1_result_cnan, ex1_result_lfn, ex1_result_inf, ex1_result_zero, 1'b0}; + assign ex1_special_sign[3:0] = {ex1_result_sign, ex1_result_sign, ex1_result_sign, 1'b0}; + assign fdsu_fpu_ex1_fflags[4:0] = ex1_fflags[4:0]; + assign fdsu_fpu_ex1_special_sel[7:0] = ex1_special_sel[7:0]; + assign fdsu_fpu_ex1_special_sign[3:0] = ex1_special_sign[3:0]; +endmodule +module pa_fdsu_srt_single ( + cp0_fpu_icg_en, + cp0_yy_clk_en, + ex1_divisor, + ex1_expnt_adder_op1, + ex1_oper_id_frac, + ex1_oper_id_frac_f, + ex1_pipedown, + ex1_pipedown_gate, + ex1_remainder, + ex1_save_op0, + ex1_save_op0_gate, + ex2_expnt_adder_op0, + ex2_of, + ex2_pipe_clk, + ex2_pipedown, + ex2_potnt_of, + ex2_potnt_uf, + ex2_result_inf, + ex2_result_lfn, + ex2_rslt_denorm, + ex2_srt_expnt_rst, + ex2_srt_first_round, + ex2_uf, + ex2_uf_srt_skip, + ex3_frac_final_rst, + ex3_pipedown, + fdsu_ex3_id_srt_skip, + fdsu_ex3_rem_sign, + fdsu_ex3_rem_zero, + fdsu_ex3_result_denorm_round_add_num, + fdsu_ex4_frac, + fdsu_yy_div, + fdsu_yy_of_rm_lfn, + fdsu_yy_op0_norm, + fdsu_yy_op1_norm, + fdsu_yy_sqrt, + forever_cpuclk, + pad_yy_icg_scan_en, + srt_remainder_zero, + srt_sm_on, + total_qt_rt_30 +); + input wire cp0_fpu_icg_en; + input wire cp0_yy_clk_en; + input wire [23:0] ex1_divisor; + input wire [12:0] ex1_expnt_adder_op1; + input wire [51:0] ex1_oper_id_frac; + input wire ex1_pipedown; + input wire ex1_pipedown_gate; + input wire [31:0] ex1_remainder; + input wire ex1_save_op0; + input wire ex1_save_op0_gate; + input wire [9:0] ex2_expnt_adder_op0; + input wire ex2_pipe_clk; + input wire ex2_pipedown; + input wire ex2_srt_first_round; + input wire [25:0] ex3_frac_final_rst; + input wire ex3_pipedown; + input wire fdsu_yy_div; + input wire fdsu_yy_of_rm_lfn; + input wire fdsu_yy_op0_norm; + input wire fdsu_yy_op1_norm; + input wire fdsu_yy_sqrt; + input wire forever_cpuclk; + input wire pad_yy_icg_scan_en; + input wire srt_sm_on; + output wire [51:0] ex1_oper_id_frac_f; + output wire ex2_of; + output wire ex2_potnt_of; + output wire ex2_potnt_uf; + output wire ex2_result_inf; + output wire ex2_result_lfn; + output wire ex2_rslt_denorm; + output wire [9:0] ex2_srt_expnt_rst; + output wire ex2_uf; + output wire ex2_uf_srt_skip; + output reg fdsu_ex3_id_srt_skip; + output reg fdsu_ex3_rem_sign; + output reg fdsu_ex3_rem_zero; + output reg [23:0] fdsu_ex3_result_denorm_round_add_num; + output wire [25:0] fdsu_ex4_frac; + output wire srt_remainder_zero; + output reg [29:0] total_qt_rt_30; + reg [31:0] cur_rem; + reg [7:0] digit_bound_1; + reg [7:0] digit_bound_2; + reg [23:0] ex2_result_denorm_round_add_num; + reg [29:0] qt_rt_const_shift_std; + reg [7:0] qtrt_sel_rem; + reg [31:0] rem_add1_op1; + reg [31:0] rem_add2_op1; + reg [25:0] srt_divisor; + reg [31:0] srt_remainder; + reg [29:0] total_qt_rt_30_next; + reg [29:0] total_qt_rt_minus_30; + reg [29:0] total_qt_rt_minus_30_next; + wire [7:0] bound1_cmp_result; + wire bound1_cmp_sign; + wire [7:0] bound2_cmp_result; + wire bound2_cmp_sign; + wire [3:0] bound_sel; + wire [31:0] cur_doub_rem_1; + wire [31:0] cur_doub_rem_2; + wire [31:0] cur_rem_1; + wire [31:0] cur_rem_2; + wire [31:0] div_qt_1_rem_add_op1; + wire [31:0] div_qt_2_rem_add_op1; + wire [31:0] div_qt_r1_rem_add_op1; + wire [31:0] div_qt_r2_rem_add_op1; + wire ex1_ex2_pipe_clk; + wire ex1_ex2_pipe_clk_en; + wire ex2_div_of; + wire ex2_div_uf; + wire [9:0] ex2_expnt_adder_op1; + wire ex2_expnt_of; + wire [9:0] ex2_expnt_result; + wire ex2_expnt_uf; + wire ex2_id_nor_srt_skip; + wire ex2_of_plus; + wire ex2_potnt_of_pre; + wire ex2_potnt_uf_pre; + wire [9:0] ex2_sqrt_expnt_result; + wire ex2_uf_plus; + wire fdsu_ex2_div; + wire [9:0] fdsu_ex2_expnt_rst; + wire fdsu_ex2_of_rm_lfn; + wire fdsu_ex2_op0_norm; + wire fdsu_ex2_op1_norm; + wire fdsu_ex2_result_lfn; + wire fdsu_ex2_sqrt; + wire qt_clk; + wire qt_clk_en; + wire [29:0] qt_rt_const_pre_sel_q1; + wire [29:0] qt_rt_const_pre_sel_q2; + wire [29:0] qt_rt_const_q1; + wire [29:0] qt_rt_const_q2; + wire [29:0] qt_rt_const_q3; + wire [29:0] qt_rt_const_shift_std_next; + wire [29:0] qt_rt_mins_const_pre_sel_q1; + wire [29:0] qt_rt_mins_const_pre_sel_q2; + wire rem_sign; + wire [31:0] sqrt_qt_1_rem_add_op1; + wire [31:0] sqrt_qt_2_rem_add_op1; + wire [31:0] sqrt_qt_r1_rem_add_op1; + wire [31:0] sqrt_qt_r2_rem_add_op1; + wire srt_div_clk; + wire srt_div_clk_en; + wire [31:0] srt_remainder_nxt; + wire [31:0] srt_remainder_shift; + wire srt_remainder_sign; + wire [29:0] total_qt_rt_pre_sel; + assign fdsu_ex2_div = fdsu_yy_div; + assign fdsu_ex2_sqrt = fdsu_yy_sqrt; + assign fdsu_ex2_op0_norm = fdsu_yy_op0_norm; + assign fdsu_ex2_op1_norm = fdsu_yy_op1_norm; + assign fdsu_ex2_of_rm_lfn = fdsu_yy_of_rm_lfn; + assign fdsu_ex2_result_lfn = 1'b0; + assign ex2_expnt_result[9:0] = ex2_expnt_adder_op0[9:0] - ex2_expnt_adder_op1[9:0]; + assign ex2_sqrt_expnt_result[9:0] = {ex2_expnt_result[9], ex2_expnt_result[9:1]}; + assign ex2_srt_expnt_rst[9:0] = (fdsu_ex2_sqrt ? ex2_sqrt_expnt_result[9:0] : ex2_expnt_result[9:0]); + assign fdsu_ex2_expnt_rst[9:0] = ex2_srt_expnt_rst[9:0]; + assign ex2_expnt_of = ~fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8] || (fdsu_ex2_expnt_rst[7] && |fdsu_ex2_expnt_rst[6:0])); + assign ex2_potnt_of_pre = ((~fdsu_ex2_expnt_rst[9] && ~fdsu_ex2_expnt_rst[8]) && fdsu_ex2_expnt_rst[7]) && ~|fdsu_ex2_expnt_rst[6:0]; + assign ex2_potnt_of = ((ex2_potnt_of_pre && fdsu_ex2_op0_norm) && fdsu_ex2_op1_norm) && fdsu_ex2_div; + assign ex2_expnt_uf = fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8:0] <= 9'h181); + assign ex2_potnt_uf_pre = ((&fdsu_ex2_expnt_rst[9:7] && ~|fdsu_ex2_expnt_rst[6:2]) && fdsu_ex2_expnt_rst[1]) && !fdsu_ex2_expnt_rst[0]; + assign ex2_potnt_uf = (((ex2_potnt_uf_pre && fdsu_ex2_op0_norm) && fdsu_ex2_op1_norm) && fdsu_ex2_div) || (ex2_potnt_uf_pre && fdsu_ex2_op0_norm); + assign ex2_of = ex2_of_plus; + assign ex2_of_plus = ex2_div_of && fdsu_ex2_div; + assign ex2_div_of = (fdsu_ex2_op0_norm && fdsu_ex2_op1_norm) && ex2_expnt_of; + assign ex2_uf = ex2_uf_plus; + assign ex2_uf_plus = ex2_div_uf && fdsu_ex2_div; + assign ex2_div_uf = (fdsu_ex2_op0_norm && fdsu_ex2_op1_norm) && ex2_expnt_uf; + assign ex2_id_nor_srt_skip = fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8:0] < 9'h16a); + assign ex2_uf_srt_skip = ex2_id_nor_srt_skip; + assign ex2_rslt_denorm = ex2_uf; + always @(fdsu_ex2_expnt_rst[9:0]) + case (fdsu_ex2_expnt_rst[9:0]) + 10'h382: ex2_result_denorm_round_add_num[23:0] = 24'h000001; + 10'h381: ex2_result_denorm_round_add_num[23:0] = 24'h000002; + 10'h380: ex2_result_denorm_round_add_num[23:0] = 24'h000004; + 10'h37f: ex2_result_denorm_round_add_num[23:0] = 24'h000008; + 10'h37e: ex2_result_denorm_round_add_num[23:0] = 24'h000010; + 10'h37d: ex2_result_denorm_round_add_num[23:0] = 24'h000020; + 10'h37c: ex2_result_denorm_round_add_num[23:0] = 24'h000040; + 10'h37b: ex2_result_denorm_round_add_num[23:0] = 24'h000080; + 10'h37a: ex2_result_denorm_round_add_num[23:0] = 24'h000100; + 10'h379: ex2_result_denorm_round_add_num[23:0] = 24'h000200; + 10'h378: ex2_result_denorm_round_add_num[23:0] = 24'h000400; + 10'h377: ex2_result_denorm_round_add_num[23:0] = 24'h000800; + 10'h376: ex2_result_denorm_round_add_num[23:0] = 24'h001000; + 10'h375: ex2_result_denorm_round_add_num[23:0] = 24'h002000; + 10'h374: ex2_result_denorm_round_add_num[23:0] = 24'h004000; + 10'h373: ex2_result_denorm_round_add_num[23:0] = 24'h008000; + 10'h372: ex2_result_denorm_round_add_num[23:0] = 24'h010000; + 10'h371: ex2_result_denorm_round_add_num[23:0] = 24'h020000; + 10'h370: ex2_result_denorm_round_add_num[23:0] = 24'h040000; + 10'h36f: ex2_result_denorm_round_add_num[23:0] = 24'h080000; + 10'h36e: ex2_result_denorm_round_add_num[23:0] = 24'h100000; + 10'h36d: ex2_result_denorm_round_add_num[23:0] = 24'h200000; + 10'h36c: ex2_result_denorm_round_add_num[23:0] = 24'h400000; + 10'h36b: ex2_result_denorm_round_add_num[23:0] = 24'h800000; + default: ex2_result_denorm_round_add_num[23:0] = 24'h000000; + endcase + assign ex2_result_inf = ex2_of_plus && !fdsu_ex2_of_rm_lfn; + assign ex2_result_lfn = fdsu_ex2_result_lfn || (ex2_of_plus && fdsu_ex2_of_rm_lfn); + always @(posedge ex1_ex2_pipe_clk) + if (ex1_pipedown) + fdsu_ex3_result_denorm_round_add_num[23:0] <= {14'b00000000000000, ex1_expnt_adder_op1[9:0]}; + else if (ex2_pipedown) + fdsu_ex3_result_denorm_round_add_num[23:0] <= ex2_result_denorm_round_add_num[23:0]; + else + fdsu_ex3_result_denorm_round_add_num[23:0] <= fdsu_ex3_result_denorm_round_add_num[23:0]; + assign ex2_expnt_adder_op1 = fdsu_ex3_result_denorm_round_add_num[9:0]; + assign ex1_ex2_pipe_clk_en = ex1_pipedown_gate || ex2_pipedown; + gated_clk_cell x_ex1_ex2_pipe_clk( + .clk_in(forever_cpuclk), + .clk_out(ex1_ex2_pipe_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(ex1_ex2_pipe_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + always @(posedge ex2_pipe_clk) + if (ex2_pipedown) begin + fdsu_ex3_rem_sign <= srt_remainder_sign; + fdsu_ex3_rem_zero <= srt_remainder_zero; + fdsu_ex3_id_srt_skip <= ex2_id_nor_srt_skip; + end + else begin + fdsu_ex3_rem_sign <= fdsu_ex3_rem_sign; + fdsu_ex3_rem_zero <= fdsu_ex3_rem_zero; + fdsu_ex3_id_srt_skip <= fdsu_ex3_id_srt_skip; + end + always @(posedge qt_clk) + if (ex1_pipedown) + srt_remainder[31:0] <= ex1_remainder[31:0]; + else if (srt_sm_on) + srt_remainder[31:0] <= srt_remainder_nxt[31:0]; + else + srt_remainder[31:0] <= srt_remainder[31:0]; + gated_clk_cell x_srt_div_clk( + .clk_in(forever_cpuclk), + .clk_out(srt_div_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(srt_div_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign srt_div_clk_en = (ex1_pipedown_gate || ex1_save_op0_gate) || ex3_pipedown; + always @(posedge srt_div_clk) + if (ex1_save_op0) + srt_divisor[25:0] <= {3'b000, ex1_oper_id_frac[51:29]}; + else if (ex1_pipedown) + srt_divisor[25:0] <= {2'b00, ex1_divisor[23:0]}; + else if (ex3_pipedown) + srt_divisor[25:0] <= ex3_frac_final_rst[25:0]; + else + srt_divisor[25:0] <= srt_divisor[25:0]; + assign ex1_oper_id_frac_f[51:0] = {srt_divisor[22:0], 29'b00000000000000000000000000000}; + assign fdsu_ex4_frac[25:0] = srt_divisor[25:0]; + assign bound_sel[3:0] = (fdsu_ex2_div ? srt_divisor[23:20] : (ex2_srt_first_round ? 4'b1010 : total_qt_rt_30[28:25])); + always @(bound_sel[3:0]) + case (bound_sel[3:0]) + 4'b0000: begin + digit_bound_1[7:0] = 8'b11110100; + digit_bound_2[7:0] = 8'b11010001; + end + 4'b1000: begin + digit_bound_1[7:0] = 8'b11111001; + digit_bound_2[7:0] = 8'b11100111; + end + 4'b1001: begin + digit_bound_1[7:0] = 8'b11111001; + digit_bound_2[7:0] = 8'b11100100; + end + 4'b1010: begin + digit_bound_1[7:0] = 8'b11111000; + digit_bound_2[7:0] = 8'b11100001; + end + 4'b1011: begin + digit_bound_1[7:0] = 8'b11110111; + digit_bound_2[7:0] = 8'b11011111; + end + 4'b1100: begin + digit_bound_1[7:0] = 8'b11110111; + digit_bound_2[7:0] = 8'b11011100; + end + 4'b1101: begin + digit_bound_1[7:0] = 8'b11110110; + digit_bound_2[7:0] = 8'b11011001; + end + 4'b1110: begin + digit_bound_1[7:0] = 8'b11110101; + digit_bound_2[7:0] = 8'b11010111; + end + 4'b1111: begin + digit_bound_1[7:0] = 8'b11110100; + digit_bound_2[7:0] = 8'b11010001; + end + default: begin + digit_bound_1[7:0] = 8'b11111001; + digit_bound_2[7:0] = 8'b11100111; + end + endcase + assign bound1_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_1[7:0]; + assign bound2_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_2[7:0]; + assign bound1_cmp_sign = bound1_cmp_result[7]; + assign bound2_cmp_sign = bound2_cmp_result[7]; + assign rem_sign = srt_remainder[29]; + always @(ex2_srt_first_round or fdsu_ex2_sqrt or srt_remainder[29:21]) + if (ex2_srt_first_round && fdsu_ex2_sqrt) + qtrt_sel_rem[7:0] = {srt_remainder[29], srt_remainder[27:21]}; + else + qtrt_sel_rem[7:0] = (srt_remainder[29] ? ~srt_remainder[29:22] : srt_remainder[29:22]); + gated_clk_cell x_qt_clk( + .clk_in(forever_cpuclk), + .clk_out(qt_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(qt_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + assign qt_clk_en = srt_sm_on || ex1_pipedown_gate; + always @(posedge qt_clk) + if (ex1_pipedown) begin + qt_rt_const_shift_std[29:0] <= 30'b010000000000000000000000000000; + total_qt_rt_30[29:0] <= 30'b000000000000000000000000000000; + total_qt_rt_minus_30[29:0] <= 30'b000000000000000000000000000000; + end + else if (srt_sm_on) begin + qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std_next[29:0]; + total_qt_rt_30[29:0] <= total_qt_rt_30_next[29:0]; + total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30_next[29:0]; + end + else begin + qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std[29:0]; + total_qt_rt_30[29:0] <= total_qt_rt_30[29:0]; + total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30[29:0]; + end + assign qt_rt_const_q1[29:0] = qt_rt_const_shift_std[29:0]; + assign qt_rt_const_q2[29:0] = {qt_rt_const_shift_std[28:0], 1'b0}; + assign qt_rt_const_q3[29:0] = qt_rt_const_q1[29:0] | qt_rt_const_q2[29:0]; + assign qt_rt_const_shift_std_next[29:0] = {2'b00, qt_rt_const_shift_std[29:2]}; + assign total_qt_rt_pre_sel[29:0] = (rem_sign ? total_qt_rt_minus_30[29:0] : total_qt_rt_30[29:0]); + assign qt_rt_const_pre_sel_q2[29:0] = qt_rt_const_q2[29:0]; + assign qt_rt_mins_const_pre_sel_q2[29:0] = qt_rt_const_q1[29:0]; + assign qt_rt_const_pre_sel_q1[29:0] = (rem_sign ? qt_rt_const_q3[29:0] : qt_rt_const_q1[29:0]); + assign qt_rt_mins_const_pre_sel_q1[29:0] = (rem_sign ? qt_rt_const_q2[29:0] : 30'b000000000000000000000000000000); + always @(qt_rt_const_q3[29:0] or qt_rt_mins_const_pre_sel_q1[29:0] or bound1_cmp_sign or total_qt_rt_30[29:0] or qt_rt_mins_const_pre_sel_q2[29:0] or total_qt_rt_minus_30[29:0] or bound2_cmp_sign or qt_rt_const_pre_sel_q2[29:0] or qt_rt_const_pre_sel_q1[29:0] or total_qt_rt_pre_sel[29:0]) + casez ({bound1_cmp_sign, bound2_cmp_sign}) + 2'b00: begin + total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] | qt_rt_const_pre_sel_q2[29:0]; + total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] | qt_rt_mins_const_pre_sel_q2[29:0]; + end + 2'b01: begin + total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] | qt_rt_const_pre_sel_q1[29:0]; + total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] | qt_rt_mins_const_pre_sel_q1[29:0]; + end + 2'b1z: begin + total_qt_rt_30_next[29:0] = total_qt_rt_30[29:0]; + total_qt_rt_minus_30_next[29:0] = total_qt_rt_minus_30[29:0] | qt_rt_const_q3[29:0]; + end + default: begin + total_qt_rt_30_next[29:0] = 30'b000000000000000000000000000000; + total_qt_rt_minus_30_next[29:0] = 30'b000000000000000000000000000000; + end + endcase + assign div_qt_1_rem_add_op1[31:0] = ~{3'b000, srt_divisor[23:0], 5'b00000}; + assign div_qt_2_rem_add_op1[31:0] = ~{2'b00, srt_divisor[23:0], 6'b000000}; + assign div_qt_r1_rem_add_op1[31:0] = {3'b000, srt_divisor[23:0], 5'b00000}; + assign div_qt_r2_rem_add_op1[31:0] = {2'b00, srt_divisor[23:0], 6'b000000}; + assign sqrt_qt_1_rem_add_op1[31:0] = ~({2'b00, total_qt_rt_30[29:0]} | {3'b000, qt_rt_const_q1[29:1]}); + assign sqrt_qt_2_rem_add_op1[31:0] = ~({1'b0, total_qt_rt_30[29:0], 1'b0} | {1'b0, qt_rt_const_q1[29:0], 1'b0}); + assign sqrt_qt_r1_rem_add_op1[31:0] = (({2'b00, total_qt_rt_minus_30[29:0]} | {1'b0, qt_rt_const_q1[29:0], 1'b0}) | {2'b00, qt_rt_const_q1[29:0]}) | {3'b000, qt_rt_const_q1[29:1]}; + assign sqrt_qt_r2_rem_add_op1[31:0] = ({1'b0, total_qt_rt_minus_30[29:0], 1'b0} | {qt_rt_const_q1[29:0], 2'b00}) | {1'b0, qt_rt_const_q1[29:0], 1'b0}; + always @(div_qt_2_rem_add_op1[31:0] or sqrt_qt_r2_rem_add_op1[31:0] or sqrt_qt_r1_rem_add_op1[31:0] or rem_sign or div_qt_r2_rem_add_op1[31:0] or div_qt_1_rem_add_op1[31:0] or sqrt_qt_2_rem_add_op1[31:0] or fdsu_ex2_sqrt or div_qt_r1_rem_add_op1[31:0] or sqrt_qt_1_rem_add_op1[31:0]) + case ({rem_sign, fdsu_ex2_sqrt}) + 2'b01: begin + rem_add1_op1[31:0] = sqrt_qt_1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = sqrt_qt_2_rem_add_op1[31:0]; + end + 2'b00: begin + rem_add1_op1[31:0] = div_qt_1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = div_qt_2_rem_add_op1[31:0]; + end + 2'b11: begin + rem_add1_op1[31:0] = sqrt_qt_r1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = sqrt_qt_r2_rem_add_op1[31:0]; + end + 2'b10: begin + rem_add1_op1[31:0] = div_qt_r1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = div_qt_r2_rem_add_op1[31:0]; + end + default: begin + rem_add1_op1[31:0] = 32'b00000000000000000000000000000000; + rem_add2_op1[31:0] = 32'b00000000000000000000000000000000; + end + endcase + assign srt_remainder_shift[31:0] = {srt_remainder[31], srt_remainder[28:0], 2'b00}; + assign cur_doub_rem_1[31:0] = (srt_remainder_shift[31:0] + rem_add1_op1[31:0]) + {31'b0000000000000000000000000000000, ~rem_sign}; + assign cur_doub_rem_2[31:0] = (srt_remainder_shift[31:0] + rem_add2_op1[31:0]) + {31'b0000000000000000000000000000000, ~rem_sign}; + assign cur_rem_1[31:0] = cur_doub_rem_1[31:0]; + assign cur_rem_2[31:0] = cur_doub_rem_2[31:0]; + always @(cur_rem_2[31:0] or bound1_cmp_sign or srt_remainder_shift[31:0] or bound2_cmp_sign or cur_rem_1[31:0]) + case ({bound1_cmp_sign, bound2_cmp_sign}) + 2'b00: cur_rem[31:0] = cur_rem_2[31:0]; + 2'b01: cur_rem[31:0] = cur_rem_1[31:0]; + default: cur_rem[31:0] = srt_remainder_shift[31:0]; + endcase + assign srt_remainder_nxt[31:0] = cur_rem[31:0]; + assign srt_remainder_zero = ~|srt_remainder[31:0]; + assign srt_remainder_sign = srt_remainder[31]; +endmodule +module pa_fdsu_top ( + cp0_fpu_icg_en, + cp0_fpu_xx_dqnan, + cp0_yy_clk_en, + cpurst_b, + ctrl_fdsu_ex1_sel, + ctrl_xx_ex1_cmplt_dp, + ctrl_xx_ex1_inst_vld, + ctrl_xx_ex1_stall, + ctrl_xx_ex1_warm_up, + ctrl_xx_ex2_warm_up, + ctrl_xx_ex3_warm_up, + dp_xx_ex1_cnan, + dp_xx_ex1_id, + dp_xx_ex1_inf, + dp_xx_ex1_qnan, + dp_xx_ex1_rm, + dp_xx_ex1_snan, + dp_xx_ex1_zero, + fdsu_fpu_ex1_cmplt, + fdsu_fpu_ex1_cmplt_dp, + fdsu_fpu_ex1_fflags, + fdsu_fpu_ex1_special_sel, + fdsu_fpu_ex1_special_sign, + fdsu_fpu_ex1_stall, + fdsu_fpu_no_op, + fdsu_frbus_data, + fdsu_frbus_fflags, + fdsu_frbus_freg, + fdsu_frbus_wb_vld, + forever_cpuclk, + frbus_fdsu_wb_grant, + idu_fpu_ex1_dst_freg, + idu_fpu_ex1_eu_sel, + idu_fpu_ex1_func, + idu_fpu_ex1_srcf0, + idu_fpu_ex1_srcf1, + pad_yy_icg_scan_en, + rtu_xx_ex1_cancel, + rtu_xx_ex2_cancel, + rtu_yy_xx_async_flush, + rtu_yy_xx_flush +); + input wire cp0_fpu_icg_en; + input wire cp0_fpu_xx_dqnan; + input wire cp0_yy_clk_en; + input wire cpurst_b; + input wire ctrl_fdsu_ex1_sel; + input wire ctrl_xx_ex1_cmplt_dp; + input wire ctrl_xx_ex1_inst_vld; + input wire ctrl_xx_ex1_stall; + input wire ctrl_xx_ex1_warm_up; + input wire ctrl_xx_ex2_warm_up; + input wire ctrl_xx_ex3_warm_up; + input wire [2:0] dp_xx_ex1_cnan; + input wire [2:0] dp_xx_ex1_id; + input wire [2:0] dp_xx_ex1_inf; + input wire [2:0] dp_xx_ex1_qnan; + input wire [2:0] dp_xx_ex1_rm; + input wire [2:0] dp_xx_ex1_snan; + input wire [2:0] dp_xx_ex1_zero; + input wire forever_cpuclk; + input wire frbus_fdsu_wb_grant; + input wire [4:0] idu_fpu_ex1_dst_freg; + input wire [2:0] idu_fpu_ex1_eu_sel; + input wire [9:0] idu_fpu_ex1_func; + input wire [31:0] idu_fpu_ex1_srcf0; + input wire [31:0] idu_fpu_ex1_srcf1; + input wire pad_yy_icg_scan_en; + input wire rtu_xx_ex1_cancel; + input wire rtu_xx_ex2_cancel; + input wire rtu_yy_xx_async_flush; + input wire rtu_yy_xx_flush; + output wire fdsu_fpu_ex1_cmplt; + output wire fdsu_fpu_ex1_cmplt_dp; + output wire [4:0] fdsu_fpu_ex1_fflags; + output wire [7:0] fdsu_fpu_ex1_special_sel; + output wire [3:0] fdsu_fpu_ex1_special_sign; + output wire fdsu_fpu_ex1_stall; + output wire fdsu_fpu_no_op; + output wire [31:0] fdsu_frbus_data; + output wire [4:0] fdsu_frbus_fflags; + output wire [4:0] fdsu_frbus_freg; + output wire fdsu_frbus_wb_vld; + wire ex1_div; + wire [23:0] ex1_divisor; + wire [12:0] ex1_expnt_adder_op0; + wire [12:0] ex1_expnt_adder_op1; + wire ex1_of_result_lfn; + wire ex1_op0_id; + wire ex1_op0_norm; + wire ex1_op0_sign; + wire ex1_op1_id; + wire ex1_op1_id_vld; + wire ex1_op1_norm; + wire ex1_op1_sel; + wire [12:0] ex1_oper_id_expnt; + wire [12:0] ex1_oper_id_expnt_f; + wire [51:0] ex1_oper_id_frac; + wire [51:0] ex1_oper_id_frac_f; + wire ex1_pipedown; + wire ex1_pipedown_gate; + wire [31:0] ex1_remainder; + wire ex1_result_sign; + wire [2:0] ex1_rm; + wire ex1_save_op0; + wire ex1_save_op0_gate; + wire ex1_sqrt; + wire ex1_srt_skip; + wire [9:0] ex2_expnt_adder_op0; + wire ex2_of; + wire ex2_pipe_clk; + wire ex2_pipedown; + wire ex2_potnt_of; + wire ex2_potnt_uf; + wire ex2_result_inf; + wire ex2_result_lfn; + wire ex2_rslt_denorm; + wire [9:0] ex2_srt_expnt_rst; + wire ex2_srt_first_round; + wire ex2_uf; + wire ex2_uf_srt_skip; + wire [9:0] ex3_expnt_adjust_result; + wire [25:0] ex3_frac_final_rst; + wire ex3_pipedown; + wire ex3_rslt_denorm; + wire fdsu_ex1_sel; + wire fdsu_ex3_id_srt_skip; + wire fdsu_ex3_rem_sign; + wire fdsu_ex3_rem_zero; + wire [23:0] fdsu_ex3_result_denorm_round_add_num; + wire fdsu_ex4_denorm_to_tiny_frac; + wire [25:0] fdsu_ex4_frac; + wire fdsu_ex4_nx; + wire [1:0] fdsu_ex4_potnt_norm; + wire fdsu_ex4_result_nor; + wire fdsu_yy_div; + wire [9:0] fdsu_yy_expnt_rst; + wire fdsu_yy_of; + wire fdsu_yy_of_rm_lfn; + wire fdsu_yy_op0_norm; + wire fdsu_yy_op1_norm; + wire fdsu_yy_potnt_of; + wire fdsu_yy_potnt_uf; + wire fdsu_yy_result_inf; + wire fdsu_yy_result_lfn; + wire fdsu_yy_result_sign; + wire [2:0] fdsu_yy_rm; + wire fdsu_yy_rslt_denorm; + wire fdsu_yy_sqrt; + wire fdsu_yy_uf; + wire [4:0] fdsu_yy_wb_freg; + wire srt_remainder_zero; + wire srt_sm_on; + wire [29:0] total_qt_rt_30; + pa_fdsu_special x_pa_fdsu_special( + .cp0_fpu_xx_dqnan(cp0_fpu_xx_dqnan), + .dp_xx_ex1_cnan(dp_xx_ex1_cnan), + .dp_xx_ex1_id(dp_xx_ex1_id), + .dp_xx_ex1_inf(dp_xx_ex1_inf), + .dp_xx_ex1_qnan(dp_xx_ex1_qnan), + .dp_xx_ex1_snan(dp_xx_ex1_snan), + .dp_xx_ex1_zero(dp_xx_ex1_zero), + .ex1_div(ex1_div), + .ex1_op0_id(ex1_op0_id), + .ex1_op0_norm(ex1_op0_norm), + .ex1_op0_sign(ex1_op0_sign), + .ex1_op1_id(ex1_op1_id), + .ex1_op1_norm(ex1_op1_norm), + .ex1_result_sign(ex1_result_sign), + .ex1_sqrt(ex1_sqrt), + .ex1_srt_skip(ex1_srt_skip), + .fdsu_fpu_ex1_fflags(fdsu_fpu_ex1_fflags), + .fdsu_fpu_ex1_special_sel(fdsu_fpu_ex1_special_sel), + .fdsu_fpu_ex1_special_sign(fdsu_fpu_ex1_special_sign) + ); + pa_fdsu_prepare x_pa_fdsu_prepare( + .dp_xx_ex1_rm(dp_xx_ex1_rm), + .ex1_div(ex1_div), + .ex1_divisor(ex1_divisor), + .ex1_expnt_adder_op0(ex1_expnt_adder_op0), + .ex1_expnt_adder_op1(ex1_expnt_adder_op1), + .ex1_of_result_lfn(ex1_of_result_lfn), + .ex1_op0_id(ex1_op0_id), + .ex1_op0_sign(ex1_op0_sign), + .ex1_op1_id(ex1_op1_id), + .ex1_op1_id_vld(ex1_op1_id_vld), + .ex1_op1_sel(ex1_op1_sel), + .ex1_oper_id_expnt(ex1_oper_id_expnt), + .ex1_oper_id_expnt_f(ex1_oper_id_expnt_f), + .ex1_oper_id_frac(ex1_oper_id_frac), + .ex1_oper_id_frac_f(ex1_oper_id_frac_f), + .ex1_remainder(ex1_remainder), + .ex1_result_sign(ex1_result_sign), + .ex1_rm(ex1_rm), + .ex1_sqrt(ex1_sqrt), + .fdsu_ex1_sel(fdsu_ex1_sel), + .idu_fpu_ex1_func(idu_fpu_ex1_func), + .idu_fpu_ex1_srcf0(idu_fpu_ex1_srcf0), + .idu_fpu_ex1_srcf1(idu_fpu_ex1_srcf1) + ); + pa_fdsu_srt_single x_pa_fdsu_srt( + .cp0_fpu_icg_en(cp0_fpu_icg_en), + .cp0_yy_clk_en(cp0_yy_clk_en), + .ex1_divisor(ex1_divisor), + .ex1_expnt_adder_op1(ex1_expnt_adder_op1), + .ex1_oper_id_frac(ex1_oper_id_frac), + .ex1_oper_id_frac_f(ex1_oper_id_frac_f), + .ex1_pipedown(ex1_pipedown), + .ex1_pipedown_gate(ex1_pipedown_gate), + .ex1_remainder(ex1_remainder), + .ex1_save_op0(ex1_save_op0), + .ex1_save_op0_gate(ex1_save_op0_gate), + .ex2_expnt_adder_op0(ex2_expnt_adder_op0), + .ex2_of(ex2_of), + .ex2_pipe_clk(ex2_pipe_clk), + .ex2_pipedown(ex2_pipedown), + .ex2_potnt_of(ex2_potnt_of), + .ex2_potnt_uf(ex2_potnt_uf), + .ex2_result_inf(ex2_result_inf), + .ex2_result_lfn(ex2_result_lfn), + .ex2_rslt_denorm(ex2_rslt_denorm), + .ex2_srt_expnt_rst(ex2_srt_expnt_rst), + .ex2_srt_first_round(ex2_srt_first_round), + .ex2_uf(ex2_uf), + .ex2_uf_srt_skip(ex2_uf_srt_skip), + .ex3_frac_final_rst(ex3_frac_final_rst), + .ex3_pipedown(ex3_pipedown), + .fdsu_ex3_id_srt_skip(fdsu_ex3_id_srt_skip), + .fdsu_ex3_rem_sign(fdsu_ex3_rem_sign), + .fdsu_ex3_rem_zero(fdsu_ex3_rem_zero), + .fdsu_ex3_result_denorm_round_add_num(fdsu_ex3_result_denorm_round_add_num), + .fdsu_ex4_frac(fdsu_ex4_frac), + .fdsu_yy_div(fdsu_yy_div), + .fdsu_yy_of_rm_lfn(fdsu_yy_of_rm_lfn), + .fdsu_yy_op0_norm(fdsu_yy_op0_norm), + .fdsu_yy_op1_norm(fdsu_yy_op1_norm), + .fdsu_yy_sqrt(fdsu_yy_sqrt), + .forever_cpuclk(forever_cpuclk), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en), + .srt_remainder_zero(srt_remainder_zero), + .srt_sm_on(srt_sm_on), + .total_qt_rt_30(total_qt_rt_30) + ); + pa_fdsu_round_single x_pa_fdsu_round( + .cp0_fpu_icg_en(cp0_fpu_icg_en), + .cp0_yy_clk_en(cp0_yy_clk_en), + .ex3_expnt_adjust_result(ex3_expnt_adjust_result), + .ex3_frac_final_rst(ex3_frac_final_rst), + .ex3_pipedown(ex3_pipedown), + .ex3_rslt_denorm(ex3_rslt_denorm), + .fdsu_ex3_id_srt_skip(fdsu_ex3_id_srt_skip), + .fdsu_ex3_rem_sign(fdsu_ex3_rem_sign), + .fdsu_ex3_rem_zero(fdsu_ex3_rem_zero), + .fdsu_ex3_result_denorm_round_add_num(fdsu_ex3_result_denorm_round_add_num), + .fdsu_ex4_denorm_to_tiny_frac(fdsu_ex4_denorm_to_tiny_frac), + .fdsu_ex4_nx(fdsu_ex4_nx), + .fdsu_ex4_potnt_norm(fdsu_ex4_potnt_norm), + .fdsu_ex4_result_nor(fdsu_ex4_result_nor), + .fdsu_yy_expnt_rst(fdsu_yy_expnt_rst), + .fdsu_yy_result_inf(fdsu_yy_result_inf), + .fdsu_yy_result_lfn(fdsu_yy_result_lfn), + .fdsu_yy_result_sign(fdsu_yy_result_sign), + .fdsu_yy_rm(fdsu_yy_rm), + .fdsu_yy_rslt_denorm(fdsu_yy_rslt_denorm), + .forever_cpuclk(forever_cpuclk), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en), + .total_qt_rt_30(total_qt_rt_30) + ); + pa_fdsu_pack_single x_pa_fdsu_pack( + .fdsu_ex4_denorm_to_tiny_frac(fdsu_ex4_denorm_to_tiny_frac), + .fdsu_ex4_frac(fdsu_ex4_frac), + .fdsu_ex4_nx(fdsu_ex4_nx), + .fdsu_ex4_potnt_norm(fdsu_ex4_potnt_norm), + .fdsu_ex4_result_nor(fdsu_ex4_result_nor), + .fdsu_frbus_data(fdsu_frbus_data), + .fdsu_frbus_fflags(fdsu_frbus_fflags), + .fdsu_frbus_freg(fdsu_frbus_freg), + .fdsu_yy_expnt_rst(fdsu_yy_expnt_rst), + .fdsu_yy_of(fdsu_yy_of), + .fdsu_yy_of_rm_lfn(fdsu_yy_of_rm_lfn), + .fdsu_yy_potnt_of(fdsu_yy_potnt_of), + .fdsu_yy_potnt_uf(fdsu_yy_potnt_uf), + .fdsu_yy_result_inf(fdsu_yy_result_inf), + .fdsu_yy_result_lfn(fdsu_yy_result_lfn), + .fdsu_yy_result_sign(fdsu_yy_result_sign), + .fdsu_yy_rslt_denorm(fdsu_yy_rslt_denorm), + .fdsu_yy_uf(fdsu_yy_uf), + .fdsu_yy_wb_freg(fdsu_yy_wb_freg) + ); + pa_fdsu_ctrl x_pa_fdsu_ctrl( + .cp0_fpu_icg_en(cp0_fpu_icg_en), + .cp0_yy_clk_en(cp0_yy_clk_en), + .cpurst_b(cpurst_b), + .ctrl_fdsu_ex1_sel(ctrl_fdsu_ex1_sel), + .ctrl_xx_ex1_cmplt_dp(ctrl_xx_ex1_cmplt_dp), + .ctrl_xx_ex1_inst_vld(ctrl_xx_ex1_inst_vld), + .ctrl_xx_ex1_stall(ctrl_xx_ex1_stall), + .ctrl_xx_ex1_warm_up(ctrl_xx_ex1_warm_up), + .ctrl_xx_ex2_warm_up(ctrl_xx_ex2_warm_up), + .ctrl_xx_ex3_warm_up(ctrl_xx_ex3_warm_up), + .ex1_div(ex1_div), + .ex1_expnt_adder_op0(ex1_expnt_adder_op0), + .ex1_of_result_lfn(ex1_of_result_lfn), + .ex1_op0_id(ex1_op0_id), + .ex1_op0_norm(ex1_op0_norm), + .ex1_op1_id_vld(ex1_op1_id_vld), + .ex1_op1_norm(ex1_op1_norm), + .ex1_op1_sel(ex1_op1_sel), + .ex1_oper_id_expnt(ex1_oper_id_expnt), + .ex1_oper_id_expnt_f(ex1_oper_id_expnt_f), + .ex1_pipedown(ex1_pipedown), + .ex1_pipedown_gate(ex1_pipedown_gate), + .ex1_result_sign(ex1_result_sign), + .ex1_rm(ex1_rm), + .ex1_save_op0(ex1_save_op0), + .ex1_save_op0_gate(ex1_save_op0_gate), + .ex1_sqrt(ex1_sqrt), + .ex1_srt_skip(ex1_srt_skip), + .ex2_expnt_adder_op0(ex2_expnt_adder_op0), + .ex2_of(ex2_of), + .ex2_pipe_clk(ex2_pipe_clk), + .ex2_pipedown(ex2_pipedown), + .ex2_potnt_of(ex2_potnt_of), + .ex2_potnt_uf(ex2_potnt_uf), + .ex2_result_inf(ex2_result_inf), + .ex2_result_lfn(ex2_result_lfn), + .ex2_rslt_denorm(ex2_rslt_denorm), + .ex2_srt_expnt_rst(ex2_srt_expnt_rst), + .ex2_srt_first_round(ex2_srt_first_round), + .ex2_uf(ex2_uf), + .ex2_uf_srt_skip(ex2_uf_srt_skip), + .ex3_expnt_adjust_result(ex3_expnt_adjust_result), + .ex3_pipedown(ex3_pipedown), + .ex3_rslt_denorm(ex3_rslt_denorm), + .fdsu_ex1_sel(fdsu_ex1_sel), + .fdsu_fpu_ex1_cmplt(fdsu_fpu_ex1_cmplt), + .fdsu_fpu_ex1_cmplt_dp(fdsu_fpu_ex1_cmplt_dp), + .fdsu_fpu_ex1_stall(fdsu_fpu_ex1_stall), + .fdsu_fpu_no_op(fdsu_fpu_no_op), + .fdsu_frbus_wb_vld(fdsu_frbus_wb_vld), + .fdsu_yy_div(fdsu_yy_div), + .fdsu_yy_expnt_rst(fdsu_yy_expnt_rst), + .fdsu_yy_of(fdsu_yy_of), + .fdsu_yy_of_rm_lfn(fdsu_yy_of_rm_lfn), + .fdsu_yy_op0_norm(fdsu_yy_op0_norm), + .fdsu_yy_op1_norm(fdsu_yy_op1_norm), + .fdsu_yy_potnt_of(fdsu_yy_potnt_of), + .fdsu_yy_potnt_uf(fdsu_yy_potnt_uf), + .fdsu_yy_result_inf(fdsu_yy_result_inf), + .fdsu_yy_result_lfn(fdsu_yy_result_lfn), + .fdsu_yy_result_sign(fdsu_yy_result_sign), + .fdsu_yy_rm(fdsu_yy_rm), + .fdsu_yy_rslt_denorm(fdsu_yy_rslt_denorm), + .fdsu_yy_sqrt(fdsu_yy_sqrt), + .fdsu_yy_uf(fdsu_yy_uf), + .fdsu_yy_wb_freg(fdsu_yy_wb_freg), + .forever_cpuclk(forever_cpuclk), + .frbus_fdsu_wb_grant(frbus_fdsu_wb_grant), + .idu_fpu_ex1_dst_freg(idu_fpu_ex1_dst_freg), + .idu_fpu_ex1_eu_sel(idu_fpu_ex1_eu_sel), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en), + .rtu_xx_ex1_cancel(rtu_xx_ex1_cancel), + .rtu_xx_ex2_cancel(rtu_xx_ex2_cancel), + .rtu_yy_xx_async_flush(rtu_yy_xx_async_flush), + .rtu_yy_xx_flush(rtu_yy_xx_flush), + .srt_remainder_zero(srt_remainder_zero), + .srt_sm_on(srt_sm_on) + ); +endmodule +module pa_fpu_dp ( + cp0_fpu_icg_en, + cp0_fpu_xx_rm, + cp0_yy_clk_en, + ctrl_xx_ex1_inst_vld, + ctrl_xx_ex1_stall, + ctrl_xx_ex1_warm_up, + dp_frbus_ex2_data, + dp_frbus_ex2_fflags, + dp_xx_ex1_cnan, + dp_xx_ex1_id, + dp_xx_ex1_inf, + dp_xx_ex1_norm, + dp_xx_ex1_qnan, + dp_xx_ex1_snan, + dp_xx_ex1_zero, + ex2_inst_wb, + fdsu_fpu_ex1_fflags, + fdsu_fpu_ex1_special_sel, + fdsu_fpu_ex1_special_sign, + forever_cpuclk, + idu_fpu_ex1_eu_sel, + idu_fpu_ex1_func, + idu_fpu_ex1_gateclk_vld, + idu_fpu_ex1_rm, + idu_fpu_ex1_srcf0, + idu_fpu_ex1_srcf1, + idu_fpu_ex1_srcf2, + pad_yy_icg_scan_en +); + input wire cp0_fpu_icg_en; + input wire [2:0] cp0_fpu_xx_rm; + input wire cp0_yy_clk_en; + input wire ctrl_xx_ex1_inst_vld; + input wire ctrl_xx_ex1_stall; + input wire ctrl_xx_ex1_warm_up; + input wire [4:0] fdsu_fpu_ex1_fflags; + input wire [7:0] fdsu_fpu_ex1_special_sel; + input wire [3:0] fdsu_fpu_ex1_special_sign; + input wire forever_cpuclk; + input wire [2:0] idu_fpu_ex1_eu_sel; + input wire [9:0] idu_fpu_ex1_func; + input wire idu_fpu_ex1_gateclk_vld; + input wire [2:0] idu_fpu_ex1_rm; + input wire [31:0] idu_fpu_ex1_srcf0; + input wire [31:0] idu_fpu_ex1_srcf1; + input wire [31:0] idu_fpu_ex1_srcf2; + input wire pad_yy_icg_scan_en; + output wire [31:0] dp_frbus_ex2_data; + output wire [4:0] dp_frbus_ex2_fflags; + output wire [2:0] dp_xx_ex1_cnan; + output wire [2:0] dp_xx_ex1_id; + output wire [2:0] dp_xx_ex1_inf; + output wire [2:0] dp_xx_ex1_norm; + output wire [2:0] dp_xx_ex1_qnan; + output wire [2:0] dp_xx_ex1_snan; + output wire [2:0] dp_xx_ex1_zero; + output wire ex2_inst_wb; + reg [4:0] ex1_fflags; + reg [31:0] ex1_special_data; + reg [8:0] ex1_special_sel; + reg [3:0] ex1_special_sign; + reg [4:0] ex2_fflags; + reg [31:0] ex2_result; + reg [31:0] ex2_special_data; + reg [6:0] ex2_special_sel; + reg [3:0] ex2_special_sign; + wire [2:0] ex1_decode_rm; + wire ex1_double; + wire [2:0] ex1_eu_sel; + wire [9:0] ex1_func; + wire [2:0] ex1_global_rm; + wire [2:0] ex1_rm; + wire ex1_single; + wire [31:0] ex1_special_data_final; + wire [63:0] ex1_src0; + wire [63:0] ex1_src1; + wire [63:0] ex1_src2; + wire ex1_src2_vld; + wire [2:0] ex1_src_cnan; + wire [2:0] ex1_src_id; + wire [2:0] ex1_src_inf; + wire [2:0] ex1_src_norm; + wire [2:0] ex1_src_qnan; + wire [2:0] ex1_src_snan; + wire [2:0] ex1_src_zero; + wire ex2_data_clk; + wire ex2_data_clk_en; + parameter DOUBLE_WIDTH = 64; + parameter SINGLE_WIDTH = 32; + parameter FUNC_WIDTH = 10; + assign ex1_eu_sel[2:0] = idu_fpu_ex1_eu_sel[2:0]; + assign ex1_func[FUNC_WIDTH - 1:0] = idu_fpu_ex1_func[FUNC_WIDTH - 1:0]; + assign ex1_global_rm[2:0] = cp0_fpu_xx_rm[2:0]; + assign ex1_decode_rm[2:0] = idu_fpu_ex1_rm[2:0]; + assign ex1_rm[2:0] = (ex1_decode_rm[2:0] == 3'b111 ? ex1_global_rm[2:0] : ex1_decode_rm[2:0]); + assign ex1_src2_vld = idu_fpu_ex1_eu_sel[1] && ex1_func[0]; + assign ex1_src0[DOUBLE_WIDTH - 1:0] = {{SINGLE_WIDTH {1'b1}}, idu_fpu_ex1_srcf0[SINGLE_WIDTH - 1:0]}; + assign ex1_src1[DOUBLE_WIDTH - 1:0] = {{SINGLE_WIDTH {1'b1}}, idu_fpu_ex1_srcf1[SINGLE_WIDTH - 1:0]}; + assign ex1_src2[DOUBLE_WIDTH - 1:0] = (ex1_src2_vld ? {{SINGLE_WIDTH {1'b1}}, idu_fpu_ex1_srcf2[SINGLE_WIDTH - 1:0]} : {{SINGLE_WIDTH {1'b1}}, {SINGLE_WIDTH {1'b0}}}); + assign ex1_double = 1'b0; + assign ex1_single = 1'b1; + pa_fpu_src_type x_pa_fpu_ex1_srcf0_type( + .inst_double(ex1_double), + .inst_single(ex1_single), + .src_cnan(ex1_src_cnan[0]), + .src_id(ex1_src_id[0]), + .src_in(ex1_src0), + .src_inf(ex1_src_inf[0]), + .src_norm(ex1_src_norm[0]), + .src_qnan(ex1_src_qnan[0]), + .src_snan(ex1_src_snan[0]), + .src_zero(ex1_src_zero[0]) + ); + pa_fpu_src_type x_pa_fpu_ex1_srcf1_type( + .inst_double(ex1_double), + .inst_single(ex1_single), + .src_cnan(ex1_src_cnan[1]), + .src_id(ex1_src_id[1]), + .src_in(ex1_src1), + .src_inf(ex1_src_inf[1]), + .src_norm(ex1_src_norm[1]), + .src_qnan(ex1_src_qnan[1]), + .src_snan(ex1_src_snan[1]), + .src_zero(ex1_src_zero[1]) + ); + pa_fpu_src_type x_pa_fpu_ex1_srcf2_type( + .inst_double(ex1_double), + .inst_single(ex1_single), + .src_cnan(ex1_src_cnan[2]), + .src_id(ex1_src_id[2]), + .src_in(ex1_src2), + .src_inf(ex1_src_inf[2]), + .src_norm(ex1_src_norm[2]), + .src_qnan(ex1_src_qnan[2]), + .src_snan(ex1_src_snan[2]), + .src_zero(ex1_src_zero[2]) + ); + assign dp_xx_ex1_cnan[2:0] = ex1_src_cnan[2:0]; + assign dp_xx_ex1_snan[2:0] = ex1_src_snan[2:0]; + assign dp_xx_ex1_qnan[2:0] = ex1_src_qnan[2:0]; + assign dp_xx_ex1_norm[2:0] = ex1_src_norm[2:0]; + assign dp_xx_ex1_zero[2:0] = ex1_src_zero[2:0]; + assign dp_xx_ex1_inf[2:0] = ex1_src_inf[2:0]; + assign dp_xx_ex1_id[2:0] = ex1_src_id[2:0]; + always @(fdsu_fpu_ex1_special_sign[3:0] or fdsu_fpu_ex1_fflags[4:0] or ex1_eu_sel[2:0] or fdsu_fpu_ex1_special_sel[7:0]) + case (ex1_eu_sel[2:0]) + 3'b100: begin + ex1_fflags[4:0] = fdsu_fpu_ex1_fflags[4:0]; + ex1_special_sel[8:0] = {1'b0, fdsu_fpu_ex1_special_sel[7:0]}; + ex1_special_sign[3:0] = fdsu_fpu_ex1_special_sign[3:0]; + end + default: begin + ex1_fflags[4:0] = {5 {1'b0}}; + ex1_special_sel[8:0] = {9 {1'b0}}; + ex1_special_sign[3:0] = {4 {1'b0}}; + end + endcase + always @(ex1_special_sel[8:5] or ex1_src0[31:0] or ex1_src1[31:0] or ex1_src2[31:0]) + case (ex1_special_sel[8:5]) + 4'b0001: ex1_special_data[SINGLE_WIDTH - 1:0] = ex1_src0[SINGLE_WIDTH - 1:0]; + 4'b0010: ex1_special_data[SINGLE_WIDTH - 1:0] = ex1_src1[SINGLE_WIDTH - 1:0]; + 4'b0100: ex1_special_data[SINGLE_WIDTH - 1:0] = ex1_src2[SINGLE_WIDTH - 1:0]; + default: ex1_special_data[SINGLE_WIDTH - 1:0] = ex1_src2[SINGLE_WIDTH - 1:0]; + endcase + assign ex1_special_data_final[SINGLE_WIDTH - 1:0] = ex1_special_data[SINGLE_WIDTH - 1:0]; + assign ex2_data_clk_en = idu_fpu_ex1_gateclk_vld || ctrl_xx_ex1_warm_up; + gated_clk_cell x_fpu_data_ex2_gated_clk( + .clk_in(forever_cpuclk), + .clk_out(ex2_data_clk), + .external_en(1'b0), + .global_en(cp0_yy_clk_en), + .local_en(ex2_data_clk_en), + .module_en(cp0_fpu_icg_en), + .pad_yy_icg_scan_en(pad_yy_icg_scan_en) + ); + always @(posedge ex2_data_clk) + if ((ctrl_xx_ex1_inst_vld && !ctrl_xx_ex1_stall) || ctrl_xx_ex1_warm_up) begin + ex2_fflags[4:0] <= ex1_fflags[4:0]; + ex2_special_sign[3:0] <= ex1_special_sign[3:0]; + ex2_special_sel[6:0] <= {ex1_special_sel[8], |ex1_special_sel[7:5], ex1_special_sel[4:0]}; + ex2_special_data[SINGLE_WIDTH - 1:0] <= ex1_special_data_final[SINGLE_WIDTH - 1:0]; + end + assign ex2_inst_wb = |ex2_special_sel[6:0]; + always @(ex2_special_sel[6:0] or ex2_special_data[31:0] or ex2_special_sign[3:0]) + case (ex2_special_sel[6:0]) + 7'b0000001: ex2_result[SINGLE_WIDTH - 1:0] = {ex2_special_sign[0], ex2_special_data[SINGLE_WIDTH - 2:0]}; + 7'b0000010: ex2_result[SINGLE_WIDTH - 1:0] = {ex2_special_sign[1], {31 {1'b0}}}; + 7'b0000100: ex2_result[SINGLE_WIDTH - 1:0] = {ex2_special_sign[2], {8 {1'b1}}, {23 {1'b0}}}; + 7'b0001000: ex2_result[SINGLE_WIDTH - 1:0] = {ex2_special_sign[3], {7 {1'b1}}, 1'b0, {23 {1'b1}}}; + 7'b0010000: ex2_result[SINGLE_WIDTH - 1:0] = {1'b0, {8 {1'b1}}, 1'b1, {22 {1'b0}}}; + 7'b0100000: ex2_result[SINGLE_WIDTH - 1:0] = {ex2_special_data[31], {8 {1'b1}}, 1'b1, ex2_special_data[21:0]}; + 7'b1000000: ex2_result[SINGLE_WIDTH - 1:0] = ex2_special_data[SINGLE_WIDTH - 1:0]; + default: ex2_result[SINGLE_WIDTH - 1:0] = {SINGLE_WIDTH {1'b0}}; + endcase + assign dp_frbus_ex2_data[SINGLE_WIDTH - 1:0] = ex2_result[SINGLE_WIDTH - 1:0]; + assign dp_frbus_ex2_fflags[4:0] = ex2_fflags[4:0]; +endmodule +module pa_fpu_frbus ( + ctrl_frbus_ex2_wb_req, + dp_frbus_ex2_data, + dp_frbus_ex2_fflags, + fdsu_frbus_data, + fdsu_frbus_fflags, + fdsu_frbus_wb_vld, + fpu_idu_fwd_data, + fpu_idu_fwd_fflags, + fpu_idu_fwd_vld +); + input wire ctrl_frbus_ex2_wb_req; + input [31:0] dp_frbus_ex2_data; + input [4:0] dp_frbus_ex2_fflags; + input wire [31:0] fdsu_frbus_data; + input wire [4:0] fdsu_frbus_fflags; + input wire fdsu_frbus_wb_vld; + output wire [31:0] fpu_idu_fwd_data; + output wire [4:0] fpu_idu_fwd_fflags; + output wire fpu_idu_fwd_vld; + reg [31:0] frbus_wb_data; + reg [4:0] frbus_wb_fflags; + wire frbus_ex2_wb_vld; + wire frbus_fdsu_wb_vld; + wire frbus_wb_vld; + wire [3:0] frbus_source_vld; + assign frbus_fdsu_wb_vld = fdsu_frbus_wb_vld; + assign frbus_ex2_wb_vld = ctrl_frbus_ex2_wb_req; + assign frbus_source_vld[3:0] = {2'b00, frbus_ex2_wb_vld, frbus_fdsu_wb_vld}; + assign frbus_wb_vld = frbus_ex2_wb_vld | frbus_fdsu_wb_vld; + always @(frbus_source_vld[3:0] or fdsu_frbus_data[31:0] or dp_frbus_ex2_data[31:0] or fdsu_frbus_fflags[4:0] or dp_frbus_ex2_fflags[4:0]) + case (frbus_source_vld[3:0]) + 4'b0001: begin + frbus_wb_data[31:0] = fdsu_frbus_data[31:0]; + frbus_wb_fflags[4:0] = fdsu_frbus_fflags[4:0]; + end + 4'b0010: begin + frbus_wb_data[31:0] = dp_frbus_ex2_data[31:0]; + frbus_wb_fflags[4:0] = dp_frbus_ex2_fflags[4:0]; + end + default: begin + frbus_wb_data[31:0] = {31 {1'b0}}; + frbus_wb_fflags[4:0] = 5'b00000; + end + endcase + assign fpu_idu_fwd_vld = frbus_wb_vld; + assign fpu_idu_fwd_fflags[4:0] = frbus_wb_fflags[4:0]; + assign fpu_idu_fwd_data[31:0] = frbus_wb_data[31:0]; +endmodule +module pa_fpu_src_type ( + inst_double, + inst_single, + src_cnan, + src_id, + src_in, + src_inf, + src_norm, + src_qnan, + src_snan, + src_zero +); + input wire inst_double; + input wire inst_single; + input wire [63:0] src_in; + output wire src_cnan; + output wire src_id; + output wire src_inf; + output wire src_norm; + output wire src_qnan; + output wire src_snan; + output wire src_zero; + wire [63:0] src; + wire src_expn_max; + wire src_expn_zero; + wire src_frac_msb; + wire src_frac_zero; + assign src[63:0] = src_in[63:0]; + assign src_cnan = !(&src[63:32]) && inst_single; + assign src_expn_zero = (!(|src[62:52]) && inst_double) || (!(|src[30:23]) && inst_single); + assign src_expn_max = (&src[62:52] && inst_double) || (&src[30:23] && inst_single); + assign src_frac_zero = (!(|src[51:0]) && inst_double) || (!(|src[22:0]) && inst_single); + assign src_frac_msb = (src[51] && inst_double) || (src[22] && inst_single); + assign src_snan = ((src_expn_max && !src_frac_msb) && !src_frac_zero) && !src_cnan; + assign src_qnan = (src_expn_max && src_frac_msb) || src_cnan; + assign src_zero = (src_expn_zero && src_frac_zero) && !src_cnan; + assign src_id = (src_expn_zero && !src_frac_zero) && !src_cnan; + assign src_inf = (src_expn_max && src_frac_zero) && !src_cnan; + assign src_norm = (!(src_expn_zero && src_frac_zero) && !src_expn_max) && !src_cnan; +endmodule +module fpnew_divsqrt_th_32_3DF01_FC8AC ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + tag_i, + mask_i, + aux_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + mask_o, + aux_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + parameter [31:0] AuxType_AUX_BITS = 0; + reg _sv2v_0; + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + localparam [31:0] WIDTH = 32; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + localparam [31:0] NUM_FORMATS = fpnew_pkg_NUM_FP_FORMATS; + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [63:0] operands_i; + input wire [9:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire tag_i; + input wire mask_i; + input wire [AuxType_AUX_BITS - 1:0] aux_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [31:0] result_o; + output wire [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire mask_o; + output wire [AuxType_AUX_BITS - 1:0] aux_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + localparam NUM_INP_REGS = (PipeConfig == 2'd0 ? NumPipeRegs : (PipeConfig == 2'd3 ? NumPipeRegs / 2 : 0)); + localparam NUM_OUT_REGS = ((PipeConfig == 2'd1) || (PipeConfig == 2'd2) ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 1) / 2 : 0)); + wire [63:0] operands_q; + wire [2:0] rnd_mode_q; + wire [3:0] op_q; + wire in_valid_q; + reg [((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) - (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0)) + 1) * 32) + (((0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) * 32) - 1) : ((((0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)) + 1) * 32) + (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) * 32) - 1)):((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) * 32 : (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) * 32)] inp_pipe_operands_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)] inp_pipe_rnd_mode_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_OP_BITS) + ((NUM_INP_REGS * fpnew_pkg_OP_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_OP_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_OP_BITS : 0)] inp_pipe_op_q; + reg [0:NUM_INP_REGS] inp_pipe_tag_q; + reg [0:NUM_INP_REGS] inp_pipe_mask_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * AuxType_AUX_BITS) + ((NUM_INP_REGS * AuxType_AUX_BITS) - 1) : ((NUM_INP_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * AuxType_AUX_BITS : 0)] inp_pipe_aux_q; + reg [0:NUM_INP_REGS] inp_pipe_valid_q; + reg [0:NUM_INP_REGS] inp_pipe_ready; + wire [64:1] sv2v_tmp_D1F38; + assign sv2v_tmp_D1F38 = operands_i; + always @(*) inp_pipe_operands_q[32 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:64] = sv2v_tmp_D1F38; + wire [3:1] sv2v_tmp_A5988; + assign sv2v_tmp_A5988 = rnd_mode_i; + always @(*) inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3+:3] = sv2v_tmp_A5988; + wire [4:1] sv2v_tmp_76106; + assign sv2v_tmp_76106 = op_i; + always @(*) inp_pipe_op_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] = sv2v_tmp_76106; + wire [1:1] sv2v_tmp_DE624; + assign sv2v_tmp_DE624 = tag_i; + always @(*) inp_pipe_tag_q[0] = sv2v_tmp_DE624; + wire [1:1] sv2v_tmp_AE6A6; + assign sv2v_tmp_AE6A6 = mask_i; + always @(*) inp_pipe_mask_q[0] = sv2v_tmp_AE6A6; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_B1FC2; + assign sv2v_tmp_B1FC2 = aux_i; + always @(*) inp_pipe_aux_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_B1FC2; + wire [1:1] sv2v_tmp_CFC25; + assign sv2v_tmp_CFC25 = in_valid_i; + always @(*) inp_pipe_valid_q[0] = sv2v_tmp_CFC25; + assign in_ready_o = inp_pipe_ready[0]; + genvar _gv_i_5; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + function automatic [AuxType_AUX_BITS - 1:0] sv2v_cast_533F1; + input reg [AuxType_AUX_BITS - 1:0] inp; + sv2v_cast_533F1 = inp; + endfunction + generate + for (_gv_i_5 = 0; _gv_i_5 < NUM_INP_REGS; _gv_i_5 = _gv_i_5 + 1) begin : gen_input_pipeline + localparam i = _gv_i_5; + wire reg_ena; + wire [1:1] sv2v_tmp_FF0D2; + assign sv2v_tmp_FF0D2 = inp_pipe_ready[i + 1] | ~inp_pipe_valid_q[i + 1]; + always @(*) inp_pipe_ready[i] = sv2v_tmp_FF0D2; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_valid_q[i + 1] <= 1'b0; + else + inp_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (inp_pipe_ready[i] ? inp_pipe_valid_q[i] : inp_pipe_valid_q[i + 1])); + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_operands_q[32 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:64] <= 1'sb0; + else + inp_pipe_operands_q[32 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:64] <= (reg_ena ? inp_pipe_operands_q[32 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:64] : inp_pipe_operands_q[32 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:64]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= (reg_ena ? inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3+:3] : inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= sv2v_cast_4CD2E(0); + else + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= (reg_ena ? inp_pipe_op_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] : inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_tag_q[i + 1] <= 1'b0; + else + inp_pipe_tag_q[i + 1] <= (reg_ena ? inp_pipe_tag_q[i] : inp_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_mask_q[i + 1] <= 1'sb0; + else + inp_pipe_mask_q[i + 1] <= (reg_ena ? inp_pipe_mask_q[i] : inp_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign operands_q = inp_pipe_operands_q[32 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:64]; + assign rnd_mode_q = inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]; + assign op_q = inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]; + assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS]; + reg in_ready; + wire div_op; + wire sqrt_op; + reg unit_ready_q; + reg unit_done; + wire op_starting; + reg out_valid; + wire out_ready; + reg hold_result; + reg data_is_held; + reg unit_busy; + reg [1:0] state_q; + reg [1:0] state_d; + assign div_op = ((in_valid_q & (op_q == sv2v_cast_4CD2E(4))) & in_ready) & ~flush_i; + assign sqrt_op = ((in_valid_q & (op_q == sv2v_cast_4CD2E(5))) & in_ready) & ~flush_i; + assign op_starting = div_op | sqrt_op; + wire fdsu_fpu_ex1_stall; + reg fdsu_fpu_ex1_stall_q; + wire div_op_d; + reg div_op_q; + wire sqrt_op_d; + reg sqrt_op_q; + assign div_op_d = (fdsu_fpu_ex1_stall ? div_op : 1'b0); + assign sqrt_op_d = (fdsu_fpu_ex1_stall ? sqrt_op : 1'b0); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + fdsu_fpu_ex1_stall_q <= 1'sb0; + else + fdsu_fpu_ex1_stall_q <= fdsu_fpu_ex1_stall; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + div_op_q <= 1'sb0; + else + div_op_q <= div_op_d; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + sqrt_op_q <= 1'sb0; + else + sqrt_op_q <= sqrt_op_d; + always @(*) begin : flag_fsm + if (_sv2v_0) + ; + in_ready = 1'b0; + out_valid = 1'b0; + hold_result = 1'b0; + data_is_held = 1'b0; + unit_busy = 1'b0; + state_d = state_q; + inp_pipe_ready[NUM_INP_REGS] = unit_ready_q; + (* full_case, parallel_case *) + case (state_q) + 2'd0: begin + in_ready = unit_ready_q; + if (in_valid_q && unit_ready_q) begin + inp_pipe_ready[NUM_INP_REGS] = unit_ready_q && !fdsu_fpu_ex1_stall; + state_d = 2'd1; + end + end + 2'd1: begin + inp_pipe_ready[NUM_INP_REGS] = fdsu_fpu_ex1_stall_q; + unit_busy = 1'b1; + if (unit_done) begin + out_valid = 1'b1; + if (out_ready) begin + state_d = 2'd0; + if (in_valid_q && unit_ready_q) begin + in_ready = 1'b1; + state_d = 2'd1; + end + end + else begin + hold_result = 1'b1; + state_d = 2'd2; + end + end + end + 2'd2: begin + unit_busy = 1'b1; + data_is_held = 1'b1; + out_valid = 1'b1; + if (out_ready) begin + state_d = 2'd0; + if (in_valid_q && unit_ready_q) begin + in_ready = 1'b1; + state_d = 2'd1; + end + end + end + default: state_d = 2'd0; + endcase + if (flush_i) begin + unit_busy = 1'b0; + out_valid = 1'b0; + state_d = 2'd0; + end + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + state_q <= 2'd0; + else + state_q <= state_d; + reg result_tag_q; + reg [AuxType_AUX_BITS - 1:0] result_aux_q; + reg result_mask_q; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + result_tag_q <= 1'sb0; + else + result_tag_q <= (op_starting ? inp_pipe_tag_q[NUM_INP_REGS] : result_tag_q); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + result_mask_q <= 1'sb0; + else + result_mask_q <= (op_starting ? inp_pipe_mask_q[NUM_INP_REGS] : result_mask_q); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + result_aux_q <= 1'sb0; + else + result_aux_q <= (op_starting ? inp_pipe_aux_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : result_aux_q); + reg [31:0] unit_result; + reg [31:0] held_result_q; + reg [4:0] unit_status; + reg [4:0] held_status_q; + reg ctrl_fdsu_ex1_sel; + wire fdsu_fpu_ex1_cmplt; + wire [4:0] fdsu_fpu_ex1_fflags; + wire [7:0] fdsu_fpu_ex1_special_sel; + wire [3:0] fdsu_fpu_ex1_special_sign; + wire fdsu_fpu_no_op; + reg [2:0] idu_fpu_ex1_eu_sel; + wire [31:0] fdsu_frbus_data; + wire [4:0] fdsu_frbus_fflags; + wire fdsu_frbus_wb_vld; + wire [31:0] dp_frbus_ex2_data; + wire [4:0] dp_frbus_ex2_fflags; + wire [2:0] dp_xx_ex1_cnan; + wire [2:0] dp_xx_ex1_id; + wire [2:0] dp_xx_ex1_inf; + wire [2:0] dp_xx_ex1_norm; + wire [2:0] dp_xx_ex1_qnan; + wire [2:0] dp_xx_ex1_snan; + wire [2:0] dp_xx_ex1_zero; + wire ex2_inst_wb; + wire ex2_inst_wb_vld_d; + reg ex2_inst_wb_vld_q; + wire [31:0] fpu_idu_fwd_data; + wire [4:0] fpu_idu_fwd_fflags; + wire fpu_idu_fwd_vld; + reg unit_ready_d; + always @(*) begin + if (_sv2v_0) + ; + if (op_starting && unit_ready_q) begin + if (ex2_inst_wb && ex2_inst_wb_vld_q) + unit_ready_d = 1'b1; + else + unit_ready_d = 1'b0; + end + else if (fpu_idu_fwd_vld | flush_i) + unit_ready_d = 1'b1; + else + unit_ready_d = unit_ready_q; + end + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + unit_ready_q <= 1'b1; + else + unit_ready_q <= unit_ready_d; + always @(*) begin + if (_sv2v_0) + ; + ctrl_fdsu_ex1_sel = 1'b0; + idu_fpu_ex1_eu_sel = 3'h0; + if (op_starting) begin + ctrl_fdsu_ex1_sel = 1'b1; + idu_fpu_ex1_eu_sel = 3'h4; + end + else if (fdsu_fpu_ex1_stall_q) begin + ctrl_fdsu_ex1_sel = 1'b1; + idu_fpu_ex1_eu_sel = 3'h4; + end + else begin + ctrl_fdsu_ex1_sel = 1'b0; + idu_fpu_ex1_eu_sel = 3'h0; + end + end + pa_fdsu_top i_divsqrt_thead( + .cp0_fpu_icg_en(1'b0), + .cp0_fpu_xx_dqnan(1'b0), + .cp0_yy_clk_en(1'b1), + .cpurst_b(rst_ni), + .ctrl_fdsu_ex1_sel(ctrl_fdsu_ex1_sel), + .ctrl_xx_ex1_cmplt_dp(ctrl_fdsu_ex1_sel), + .ctrl_xx_ex1_inst_vld(ctrl_fdsu_ex1_sel), + .ctrl_xx_ex1_stall(fdsu_fpu_ex1_stall), + .ctrl_xx_ex1_warm_up(1'b0), + .ctrl_xx_ex2_warm_up(1'b0), + .ctrl_xx_ex3_warm_up(1'b0), + .dp_xx_ex1_cnan(dp_xx_ex1_cnan), + .dp_xx_ex1_id(dp_xx_ex1_id), + .dp_xx_ex1_inf(dp_xx_ex1_inf), + .dp_xx_ex1_qnan(dp_xx_ex1_qnan), + .dp_xx_ex1_rm(rnd_mode_q), + .dp_xx_ex1_snan(dp_xx_ex1_snan), + .dp_xx_ex1_zero(dp_xx_ex1_zero), + .fdsu_fpu_ex1_cmplt(fdsu_fpu_ex1_cmplt), + .fdsu_fpu_ex1_cmplt_dp(), + .fdsu_fpu_ex1_fflags(fdsu_fpu_ex1_fflags), + .fdsu_fpu_ex1_special_sel(fdsu_fpu_ex1_special_sel), + .fdsu_fpu_ex1_special_sign(fdsu_fpu_ex1_special_sign), + .fdsu_fpu_ex1_stall(fdsu_fpu_ex1_stall), + .fdsu_fpu_no_op(fdsu_fpu_no_op), + .fdsu_frbus_data(fdsu_frbus_data), + .fdsu_frbus_fflags(fdsu_frbus_fflags), + .fdsu_frbus_freg(), + .fdsu_frbus_wb_vld(fdsu_frbus_wb_vld), + .forever_cpuclk(clk_i), + .frbus_fdsu_wb_grant(fdsu_frbus_wb_vld), + .idu_fpu_ex1_dst_freg(5'h0f), + .idu_fpu_ex1_eu_sel(idu_fpu_ex1_eu_sel), + .idu_fpu_ex1_func({8'b00000000, div_op | div_op_q, sqrt_op | sqrt_op_q}), + .idu_fpu_ex1_srcf0(operands_q[31-:32]), + .idu_fpu_ex1_srcf1(operands_q[63-:32]), + .pad_yy_icg_scan_en(1'b0), + .rtu_xx_ex1_cancel(1'b0), + .rtu_xx_ex2_cancel(1'b0), + .rtu_yy_xx_async_flush(flush_i), + .rtu_yy_xx_flush(1'b0) + ); + localparam [31:0] sv2v_uu_x_pa_fpu_dp_ext_idu_fpu_ex1_srcf2_0 = 1'sb0; + pa_fpu_dp x_pa_fpu_dp( + .cp0_fpu_icg_en(1'b0), + .cp0_fpu_xx_rm(rnd_mode_q), + .cp0_yy_clk_en(1'b1), + .ctrl_xx_ex1_inst_vld(ctrl_fdsu_ex1_sel), + .ctrl_xx_ex1_stall(1'b0), + .ctrl_xx_ex1_warm_up(1'b0), + .dp_frbus_ex2_data(dp_frbus_ex2_data), + .dp_frbus_ex2_fflags(dp_frbus_ex2_fflags), + .dp_xx_ex1_cnan(dp_xx_ex1_cnan), + .dp_xx_ex1_id(dp_xx_ex1_id), + .dp_xx_ex1_inf(dp_xx_ex1_inf), + .dp_xx_ex1_norm(dp_xx_ex1_norm), + .dp_xx_ex1_qnan(dp_xx_ex1_qnan), + .dp_xx_ex1_snan(dp_xx_ex1_snan), + .dp_xx_ex1_zero(dp_xx_ex1_zero), + .ex2_inst_wb(ex2_inst_wb), + .fdsu_fpu_ex1_fflags(fdsu_fpu_ex1_fflags), + .fdsu_fpu_ex1_special_sel(fdsu_fpu_ex1_special_sel), + .fdsu_fpu_ex1_special_sign(fdsu_fpu_ex1_special_sign), + .forever_cpuclk(clk_i), + .idu_fpu_ex1_eu_sel(idu_fpu_ex1_eu_sel), + .idu_fpu_ex1_func({8'b00000000, div_op, sqrt_op}), + .idu_fpu_ex1_gateclk_vld(fdsu_fpu_ex1_cmplt), + .idu_fpu_ex1_rm(rnd_mode_q), + .idu_fpu_ex1_srcf0(operands_q[31-:32]), + .idu_fpu_ex1_srcf1(operands_q[63-:32]), + .idu_fpu_ex1_srcf2(sv2v_uu_x_pa_fpu_dp_ext_idu_fpu_ex1_srcf2_0), + .pad_yy_icg_scan_en(1'b0) + ); + assign ex2_inst_wb_vld_d = ctrl_fdsu_ex1_sel; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + ex2_inst_wb_vld_q <= 1'sb0; + else + ex2_inst_wb_vld_q <= ex2_inst_wb_vld_d; + pa_fpu_frbus x_pa_fpu_frbus( + .ctrl_frbus_ex2_wb_req(ex2_inst_wb & ex2_inst_wb_vld_q), + .dp_frbus_ex2_data(dp_frbus_ex2_data), + .dp_frbus_ex2_fflags(dp_frbus_ex2_fflags), + .fdsu_frbus_data(fdsu_frbus_data), + .fdsu_frbus_fflags(fdsu_frbus_fflags), + .fdsu_frbus_wb_vld(fdsu_frbus_wb_vld), + .fpu_idu_fwd_data(fpu_idu_fwd_data), + .fpu_idu_fwd_fflags(fpu_idu_fwd_fflags), + .fpu_idu_fwd_vld(fpu_idu_fwd_vld) + ); + always @(*) begin + if (_sv2v_0) + ; + unit_result[31:0] = fpu_idu_fwd_data[31:0]; + unit_status[4:0] = fpu_idu_fwd_fflags[4:0]; + unit_done = fpu_idu_fwd_vld; + end + always @(posedge clk_i) held_result_q <= (hold_result ? unit_result : held_result_q); + always @(posedge clk_i) held_status_q <= (hold_result ? unit_status : held_status_q); + wire [31:0] result_d; + wire [4:0] status_d; + assign result_d = (data_is_held ? held_result_q : unit_result); + assign status_d = (data_is_held ? held_status_q : unit_status); + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * WIDTH) + ((NUM_OUT_REGS * WIDTH) - 1) : ((NUM_OUT_REGS + 1) * WIDTH) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * WIDTH : 0)] out_pipe_result_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * 5) + ((NUM_OUT_REGS * 5) - 1) : ((NUM_OUT_REGS + 1) * 5) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * 5 : 0)] out_pipe_status_q; + reg [0:NUM_OUT_REGS] out_pipe_tag_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * AuxType_AUX_BITS) + ((NUM_OUT_REGS * AuxType_AUX_BITS) - 1) : ((NUM_OUT_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * AuxType_AUX_BITS : 0)] out_pipe_aux_q; + reg [0:NUM_OUT_REGS] out_pipe_mask_q; + reg [0:NUM_OUT_REGS] out_pipe_valid_q; + wire [0:NUM_OUT_REGS] out_pipe_ready; + wire [32:1] sv2v_tmp_F1632; + assign sv2v_tmp_F1632 = result_d; + always @(*) out_pipe_result_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * WIDTH+:WIDTH] = sv2v_tmp_F1632; + wire [5:1] sv2v_tmp_03440; + assign sv2v_tmp_03440 = status_d; + always @(*) out_pipe_status_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * 5+:5] = sv2v_tmp_03440; + wire [1:1] sv2v_tmp_AFEEA; + assign sv2v_tmp_AFEEA = result_tag_q; + always @(*) out_pipe_tag_q[0] = sv2v_tmp_AFEEA; + wire [1:1] sv2v_tmp_0A048; + assign sv2v_tmp_0A048 = result_mask_q; + always @(*) out_pipe_mask_q[0] = sv2v_tmp_0A048; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_EB2CC; + assign sv2v_tmp_EB2CC = result_aux_q; + always @(*) out_pipe_aux_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_EB2CC; + wire [1:1] sv2v_tmp_F96BC; + assign sv2v_tmp_F96BC = out_valid; + always @(*) out_pipe_valid_q[0] = sv2v_tmp_F96BC; + assign out_ready = out_pipe_ready[0]; + genvar _gv_i_6; + generate + for (_gv_i_6 = 0; _gv_i_6 < NUM_OUT_REGS; _gv_i_6 = _gv_i_6 + 1) begin : gen_output_pipeline + localparam i = _gv_i_6; + wire reg_ena; + assign out_pipe_ready[i] = out_pipe_ready[i + 1] | ~out_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_valid_q[i + 1] <= 1'b0; + else + out_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (out_pipe_ready[i] ? out_pipe_valid_q[i] : out_pipe_valid_q[i + 1])); + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH] <= 1'sb0; + else + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH] <= (reg_ena ? out_pipe_result_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * WIDTH+:WIDTH] : out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= (reg_ena ? out_pipe_status_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * 5+:5] : out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_tag_q[i + 1] <= 1'b0; + else + out_pipe_tag_q[i + 1] <= (reg_ena ? out_pipe_tag_q[i] : out_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_mask_q[i + 1] <= 1'sb0; + else + out_pipe_mask_q[i + 1] <= (reg_ena ? out_pipe_mask_q[i] : out_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + assign result_o = out_pipe_result_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * WIDTH+:WIDTH]; + assign status_o = out_pipe_status_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * 5+:5]; + assign extension_bit_o = 1'b1; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = |{inp_pipe_valid_q, unit_busy, out_pipe_valid_q}; + generate + if (NUM_OUT_REGS > 0) begin : genblk3 + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], out_pipe_valid_q[NUM_OUT_REGS - 1]}; + end + else if (NUM_INP_REGS > 0) begin : genblk3 + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], inp_pipe_valid_q[NUM_INP_REGS - 1]}; + end + else begin : genblk3 + assign early_out_valid_o = 1'b0; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module fpnew_fma_EA93F ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + tag_i, + mask_i, + aux_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + mask_o, + aux_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + reg _sv2v_0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + parameter [2:0] FpFormat = sv2v_cast_5D882(0); + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + localparam [31:0] WIDTH = fpnew_pkg_fp_width(FpFormat); + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [(3 * WIDTH) - 1:0] operands_i; + input wire [2:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire tag_i; + input wire mask_i; + input wire aux_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [WIDTH - 1:0] result_o; + output wire [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire mask_o; + output wire aux_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + function automatic [31:0] fpnew_pkg_exp_bits; + input reg [2:0] fmt; + fpnew_pkg_exp_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32]; + endfunction + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(FpFormat); + function automatic [31:0] fpnew_pkg_man_bits; + input reg [2:0] fmt; + fpnew_pkg_man_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]; + endfunction + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(FpFormat); + function automatic [31:0] fpnew_pkg_bias; + input reg [2:0] fmt; + fpnew_pkg_bias = $unsigned((2 ** (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] - 1)) - 1); + endfunction + localparam [31:0] BIAS = fpnew_pkg_bias(FpFormat); + localparam [31:0] PRECISION_BITS = MAN_BITS + 1; + localparam [31:0] LOWER_SUM_WIDTH = (2 * PRECISION_BITS) + 3; + localparam [31:0] LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH); + function automatic signed [31:0] fpnew_pkg_maximum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_maximum = (a > b ? a : b); + endfunction + localparam [31:0] EXP_WIDTH = $unsigned(fpnew_pkg_maximum(EXP_BITS + 2, LZC_RESULT_WIDTH)); + localparam [31:0] SHIFT_AMOUNT_WIDTH = $clog2((3 * PRECISION_BITS) + 5); + localparam NUM_INP_REGS = (PipeConfig == 2'd0 ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 1) / 3 : 0)); + localparam NUM_MID_REGS = (PipeConfig == 2'd2 ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 2) / 3 : 0)); + localparam NUM_OUT_REGS = (PipeConfig == 2'd1 ? NumPipeRegs : (PipeConfig == 2'd3 ? NumPipeRegs / 3 : 0)); + reg [((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) - (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)) + 1) * WIDTH) + (((0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) * WIDTH) - 1) : ((((0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)) + 1) * WIDTH) + (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) * WIDTH) - 1)):((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) * WIDTH : (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) * WIDTH)] inp_pipe_operands_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)] inp_pipe_is_boxed_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)] inp_pipe_rnd_mode_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_OP_BITS) + ((NUM_INP_REGS * fpnew_pkg_OP_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_OP_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_OP_BITS : 0)] inp_pipe_op_q; + reg [0:NUM_INP_REGS] inp_pipe_op_mod_q; + reg [0:NUM_INP_REGS] inp_pipe_tag_q; + reg [0:NUM_INP_REGS] inp_pipe_mask_q; + reg [0:NUM_INP_REGS] inp_pipe_aux_q; + reg [0:NUM_INP_REGS] inp_pipe_valid_q; + wire [0:NUM_INP_REGS] inp_pipe_ready; + wire [3 * WIDTH:1] sv2v_tmp_15914; + assign sv2v_tmp_15914 = operands_i; + always @(*) inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] = sv2v_tmp_15914; + wire [3:1] sv2v_tmp_3D994; + assign sv2v_tmp_3D994 = is_boxed_i; + always @(*) inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3+:3] = sv2v_tmp_3D994; + wire [3:1] sv2v_tmp_85314; + assign sv2v_tmp_85314 = rnd_mode_i; + always @(*) inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3+:3] = sv2v_tmp_85314; + wire [4:1] sv2v_tmp_D905E; + assign sv2v_tmp_D905E = op_i; + always @(*) inp_pipe_op_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] = sv2v_tmp_D905E; + wire [1:1] sv2v_tmp_72E02; + assign sv2v_tmp_72E02 = op_mod_i; + always @(*) inp_pipe_op_mod_q[0] = sv2v_tmp_72E02; + wire [1:1] sv2v_tmp_DE624; + assign sv2v_tmp_DE624 = tag_i; + always @(*) inp_pipe_tag_q[0] = sv2v_tmp_DE624; + wire [1:1] sv2v_tmp_AE6A6; + assign sv2v_tmp_AE6A6 = mask_i; + always @(*) inp_pipe_mask_q[0] = sv2v_tmp_AE6A6; + wire [1:1] sv2v_tmp_683C4; + assign sv2v_tmp_683C4 = aux_i; + always @(*) inp_pipe_aux_q[0] = sv2v_tmp_683C4; + wire [1:1] sv2v_tmp_CFC25; + assign sv2v_tmp_CFC25 = in_valid_i; + always @(*) inp_pipe_valid_q[0] = sv2v_tmp_CFC25; + assign in_ready_o = inp_pipe_ready[0]; + genvar _gv_i_7; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + generate + for (_gv_i_7 = 0; _gv_i_7 < NUM_INP_REGS; _gv_i_7 = _gv_i_7 + 1) begin : gen_input_pipeline + localparam i = _gv_i_7; + wire reg_ena; + assign inp_pipe_ready[i] = inp_pipe_ready[i + 1] | ~inp_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_valid_q[i + 1] <= 1'b0; + else + inp_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (inp_pipe_ready[i] ? inp_pipe_valid_q[i] : inp_pipe_valid_q[i + 1])); + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] <= 1'sb0; + else + inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] <= (reg_ena ? inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] : inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= 1'sb0; + else + inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= (reg_ena ? inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3+:3] : inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= (reg_ena ? inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3+:3] : inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= sv2v_cast_4CD2E(0); + else + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= (reg_ena ? inp_pipe_op_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] : inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_mod_q[i + 1] <= 1'sb0; + else + inp_pipe_op_mod_q[i + 1] <= (reg_ena ? inp_pipe_op_mod_q[i] : inp_pipe_op_mod_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_tag_q[i + 1] <= 1'b0; + else + inp_pipe_tag_q[i + 1] <= (reg_ena ? inp_pipe_tag_q[i] : inp_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_mask_q[i + 1] <= 1'sb0; + else + inp_pipe_mask_q[i + 1] <= (reg_ena ? inp_pipe_mask_q[i] : inp_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_aux_q[i + 1] <= 1'b0; + else + inp_pipe_aux_q[i + 1] <= (reg_ena ? inp_pipe_aux_q[i] : inp_pipe_aux_q[i + 1]); + end + endgenerate + wire [23:0] info_q; + fpnew_classifier #( + .FpFormat(FpFormat), + .NumOperands(3) + ) i_class_inputs( + .operands_i(inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3]), + .is_boxed_i(inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]), + .info_o(info_q) + ); + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] operand_a; + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] operand_b; + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] operand_c; + reg [7:0] info_a; + reg [7:0] info_b; + reg [7:0] info_c; + localparam [0:0] fpnew_pkg_DONT_CARE = 1'b1; + function automatic [EXP_BITS - 1:0] sv2v_cast_51E93; + input reg [EXP_BITS - 1:0] inp; + sv2v_cast_51E93 = inp; + endfunction + function automatic [MAN_BITS - 1:0] sv2v_cast_78D38; + input reg [MAN_BITS - 1:0] inp; + sv2v_cast_78D38 = inp; + endfunction + function automatic [EXP_BITS - 1:0] sv2v_cast_89227; + input reg [EXP_BITS - 1:0] inp; + sv2v_cast_89227 = inp; + endfunction + function automatic [MAN_BITS - 1:0] sv2v_cast_D5F4C; + input reg [MAN_BITS - 1:0] inp; + sv2v_cast_D5F4C = inp; + endfunction + always @(*) begin : op_select + if (_sv2v_0) + ; + operand_a = inp_pipe_operands_q[((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3 : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1))) * WIDTH+:WIDTH]; + operand_b = inp_pipe_operands_q[((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 1 : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - ((((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1))) * WIDTH+:WIDTH]; + operand_c = inp_pipe_operands_q[((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 2 : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - ((((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1))) * WIDTH+:WIDTH]; + info_a = info_q[0+:8]; + info_b = info_q[8+:8]; + info_c = info_q[16+:8]; + operand_c[1 + (EXP_BITS + (MAN_BITS - 1))] = operand_c[1 + (EXP_BITS + (MAN_BITS - 1))] ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + (* full_case, parallel_case *) + case (inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]) + sv2v_cast_4CD2E(0): + ; + sv2v_cast_4CD2E(1): operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] = ~operand_a[1 + (EXP_BITS + (MAN_BITS - 1))]; + sv2v_cast_4CD2E(2), sv2v_cast_4CD2E(15): begin + operand_a = {1'b0, sv2v_cast_51E93(BIAS), sv2v_cast_78D38(1'sb0)}; + info_a = 8'b10000001; + end + sv2v_cast_4CD2E(3): begin + if (inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3] == 3'b010) + operand_c = {1'b0, sv2v_cast_89227(1'sb0), sv2v_cast_78D38(1'sb0)}; + else + operand_c = {1'b1, sv2v_cast_89227(1'sb0), sv2v_cast_78D38(1'sb0)}; + info_c = 8'b00100001; + end + default: begin + operand_a = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + operand_b = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + operand_c = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + info_a = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + info_b = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + info_c = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + end + endcase + end + wire any_operand_inf; + wire any_operand_nan; + wire signalling_nan; + wire effective_subtraction; + wire tentative_sign; + assign any_operand_inf = |{info_a[4], info_b[4], info_c[4]}; + assign any_operand_nan = |{info_a[3], info_b[3], info_c[3]}; + assign signalling_nan = |{info_a[2], info_b[2], info_c[2]}; + assign effective_subtraction = (operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ^ operand_b[1 + (EXP_BITS + (MAN_BITS - 1))]) ^ operand_c[1 + (EXP_BITS + (MAN_BITS - 1))]; + assign tentative_sign = operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ^ operand_b[1 + (EXP_BITS + (MAN_BITS - 1))]; + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] special_result; + reg [4:0] special_status; + reg result_is_special; + always @(*) begin : special_cases + if (_sv2v_0) + ; + special_result = {1'b0, sv2v_cast_89227(1'sb1), sv2v_cast_D5F4C(2 ** (MAN_BITS - 1))}; + special_status = 1'sb0; + result_is_special = 1'b0; + if ((info_a[4] && info_b[5]) || (info_a[5] && info_b[4])) begin + result_is_special = 1'b1; + special_status[4] = 1'b1; + end + else if (any_operand_nan) begin + result_is_special = 1'b1; + special_status[4] = signalling_nan; + end + else if (any_operand_inf) begin + result_is_special = 1'b1; + if (((info_a[4] || info_b[4]) && info_c[4]) && effective_subtraction) + special_status[4] = 1'b1; + else if (info_a[4] || info_b[4]) + special_result = {operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ^ operand_b[1 + (EXP_BITS + (MAN_BITS - 1))], sv2v_cast_89227(1'sb1), sv2v_cast_78D38(1'sb0)}; + else if (info_c[4]) + special_result = {operand_c[1 + (EXP_BITS + (MAN_BITS - 1))], sv2v_cast_89227(1'sb1), sv2v_cast_78D38(1'sb0)}; + end + end + wire signed [EXP_WIDTH - 1:0] exponent_a; + wire signed [EXP_WIDTH - 1:0] exponent_b; + wire signed [EXP_WIDTH - 1:0] exponent_c; + wire signed [EXP_WIDTH - 1:0] exponent_addend; + wire signed [EXP_WIDTH - 1:0] exponent_product; + wire signed [EXP_WIDTH - 1:0] exponent_difference; + wire signed [EXP_WIDTH - 1:0] tentative_exponent; + assign exponent_a = $signed({1'b0, operand_a[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)]}); + assign exponent_b = $signed({1'b0, operand_b[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)]}); + assign exponent_c = $signed({1'b0, operand_c[EXP_BITS + (MAN_BITS - 1)-:((EXP_BITS + (MAN_BITS - 1)) >= (MAN_BITS + 0) ? ((EXP_BITS + (MAN_BITS - 1)) - (MAN_BITS + 0)) + 1 : ((MAN_BITS + 0) - (EXP_BITS + (MAN_BITS - 1))) + 1)]}); + assign exponent_addend = $signed(exponent_c + $signed({1'b0, ~info_c[7]})); + assign exponent_product = (info_a[5] || info_b[5] ? 2 - $signed(BIAS) : $signed((((exponent_a + info_a[6]) + exponent_b) + info_b[6]) - $signed(BIAS))); + assign exponent_difference = exponent_addend - exponent_product; + assign tentative_exponent = (exponent_difference > 0 ? exponent_addend : exponent_product); + reg [SHIFT_AMOUNT_WIDTH - 1:0] addend_shamt; + always @(*) begin : addend_shift_amount + if (_sv2v_0) + ; + if (exponent_difference <= $signed((-2 * PRECISION_BITS) - 1)) + addend_shamt = (3 * PRECISION_BITS) + 4; + else if (exponent_difference <= $signed(PRECISION_BITS + 2)) + addend_shamt = $unsigned(($signed(PRECISION_BITS) + 3) - exponent_difference); + else + addend_shamt = 0; + end + wire [PRECISION_BITS - 1:0] mantissa_a; + wire [PRECISION_BITS - 1:0] mantissa_b; + wire [PRECISION_BITS - 1:0] mantissa_c; + wire [(2 * PRECISION_BITS) - 1:0] product; + wire [(3 * PRECISION_BITS) + 3:0] product_shifted; + assign mantissa_a = {info_a[7], operand_a[MAN_BITS - 1-:MAN_BITS]}; + assign mantissa_b = {info_b[7], operand_b[MAN_BITS - 1-:MAN_BITS]}; + assign mantissa_c = {info_c[7], operand_c[MAN_BITS - 1-:MAN_BITS]}; + assign product = mantissa_a * mantissa_b; + assign product_shifted = product << 2; + wire [(3 * PRECISION_BITS) + 3:0] addend_after_shift; + wire [PRECISION_BITS - 1:0] addend_sticky_bits; + wire sticky_before_add; + wire [(3 * PRECISION_BITS) + 3:0] addend_shifted; + wire inject_carry_in; + assign {addend_after_shift, addend_sticky_bits} = (mantissa_c << ((3 * PRECISION_BITS) + 4)) >> addend_shamt; + assign sticky_before_add = |addend_sticky_bits; + assign addend_shifted = (effective_subtraction ? ~addend_after_shift : addend_after_shift); + assign inject_carry_in = effective_subtraction & ~sticky_before_add; + wire [(3 * PRECISION_BITS) + 4:0] sum_pos; + wire [(3 * PRECISION_BITS) + 4:0] sum_neg; + wire sum_carry; + wire [(3 * PRECISION_BITS) + 3:0] sum; + wire final_sign; + assign sum_pos = (product_shifted + addend_shifted) + inject_carry_in; + assign sum_carry = sum_pos[(3 * PRECISION_BITS) + 4]; + assign sum_neg = addend_after_shift - product_shifted; + assign sum = (effective_subtraction && ~sum_carry ? sum_neg : sum_pos); + assign final_sign = (effective_subtraction && (sum_carry == tentative_sign) ? 1'b1 : (effective_subtraction ? 1'b0 : tentative_sign)); + wire effective_subtraction_q; + wire signed [EXP_WIDTH - 1:0] exponent_product_q; + wire signed [EXP_WIDTH - 1:0] exponent_difference_q; + wire signed [EXP_WIDTH - 1:0] tentative_exponent_q; + wire [SHIFT_AMOUNT_WIDTH - 1:0] addend_shamt_q; + wire sticky_before_add_q; + wire [(3 * PRECISION_BITS) + 3:0] sum_q; + wire final_sign_q; + wire [2:0] rnd_mode_q; + wire result_is_special_q; + wire [((1 + EXP_BITS) + MAN_BITS) - 1:0] special_result_q; + wire [4:0] special_status_q; + reg [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * EXP_WIDTH) + ((NUM_MID_REGS * EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * EXP_WIDTH : 0)] mid_pipe_exp_prod_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * EXP_WIDTH) + ((NUM_MID_REGS * EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * EXP_WIDTH : 0)] mid_pipe_exp_diff_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * EXP_WIDTH) + ((NUM_MID_REGS * EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * EXP_WIDTH : 0)] mid_pipe_tent_exp_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * SHIFT_AMOUNT_WIDTH) + ((NUM_MID_REGS * SHIFT_AMOUNT_WIDTH) - 1) : ((NUM_MID_REGS + 1) * SHIFT_AMOUNT_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * SHIFT_AMOUNT_WIDTH : 0)] mid_pipe_add_shamt_q; + reg [0:NUM_MID_REGS] mid_pipe_sticky_q; + reg [(0 >= NUM_MID_REGS ? (((3 * PRECISION_BITS) + 3) >= 0 ? ((1 - NUM_MID_REGS) * ((3 * PRECISION_BITS) + 4)) + ((NUM_MID_REGS * ((3 * PRECISION_BITS) + 4)) - 1) : ((1 - NUM_MID_REGS) * (1 - ((3 * PRECISION_BITS) + 3))) + ((((3 * PRECISION_BITS) + 3) + (NUM_MID_REGS * (1 - ((3 * PRECISION_BITS) + 3)))) - 1)) : (((3 * PRECISION_BITS) + 3) >= 0 ? ((NUM_MID_REGS + 1) * ((3 * PRECISION_BITS) + 4)) - 1 : ((NUM_MID_REGS + 1) * (1 - ((3 * PRECISION_BITS) + 3))) + ((3 * PRECISION_BITS) + 2))):(0 >= NUM_MID_REGS ? (((3 * PRECISION_BITS) + 3) >= 0 ? NUM_MID_REGS * ((3 * PRECISION_BITS) + 4) : ((3 * PRECISION_BITS) + 3) + (NUM_MID_REGS * (1 - ((3 * PRECISION_BITS) + 3)))) : (((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3))] mid_pipe_sum_q; + reg [0:NUM_MID_REGS] mid_pipe_final_sign_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * 3) + ((NUM_MID_REGS * 3) - 1) : ((NUM_MID_REGS + 1) * 3) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * 3 : 0)] mid_pipe_rnd_mode_q; + reg [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * ((1 + EXP_BITS) + MAN_BITS)) + ((NUM_MID_REGS * ((1 + EXP_BITS) + MAN_BITS)) - 1) : ((NUM_MID_REGS + 1) * ((1 + EXP_BITS) + MAN_BITS)) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * ((1 + EXP_BITS) + MAN_BITS) : 0)] mid_pipe_spec_res_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * 5) + ((NUM_MID_REGS * 5) - 1) : ((NUM_MID_REGS + 1) * 5) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * 5 : 0)] mid_pipe_spec_stat_q; + reg [0:NUM_MID_REGS] mid_pipe_tag_q; + reg [0:NUM_MID_REGS] mid_pipe_mask_q; + reg [0:NUM_MID_REGS] mid_pipe_aux_q; + reg [0:NUM_MID_REGS] mid_pipe_valid_q; + wire [0:NUM_MID_REGS] mid_pipe_ready; + wire [1:1] sv2v_tmp_301F1; + assign sv2v_tmp_301F1 = effective_subtraction; + always @(*) mid_pipe_eff_sub_q[0] = sv2v_tmp_301F1; + wire [EXP_WIDTH * 1:1] sv2v_tmp_27C8D; + assign sv2v_tmp_27C8D = exponent_product; + always @(*) mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH] = sv2v_tmp_27C8D; + wire [EXP_WIDTH * 1:1] sv2v_tmp_DEAE0; + assign sv2v_tmp_DEAE0 = exponent_difference; + always @(*) mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH] = sv2v_tmp_DEAE0; + wire [EXP_WIDTH * 1:1] sv2v_tmp_530A2; + assign sv2v_tmp_530A2 = tentative_exponent; + always @(*) mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH] = sv2v_tmp_530A2; + wire [SHIFT_AMOUNT_WIDTH * 1:1] sv2v_tmp_12F7F; + assign sv2v_tmp_12F7F = addend_shamt; + always @(*) mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] = sv2v_tmp_12F7F; + wire [1:1] sv2v_tmp_6A24C; + assign sv2v_tmp_6A24C = sticky_before_add; + always @(*) mid_pipe_sticky_q[0] = sv2v_tmp_6A24C; + wire [(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)) * 1:1] sv2v_tmp_A48E2; + assign sv2v_tmp_A48E2 = sum; + always @(*) mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] = sv2v_tmp_A48E2; + wire [1:1] sv2v_tmp_9C379; + assign sv2v_tmp_9C379 = final_sign; + always @(*) mid_pipe_final_sign_q[0] = sv2v_tmp_9C379; + wire [3:1] sv2v_tmp_C990F; + assign sv2v_tmp_C990F = inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]; + always @(*) mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * 3+:3] = sv2v_tmp_C990F; + wire [1:1] sv2v_tmp_08378; + assign sv2v_tmp_08378 = result_is_special; + always @(*) mid_pipe_res_is_spec_q[0] = sv2v_tmp_08378; + wire [((1 + EXP_BITS) + MAN_BITS) * 1:1] sv2v_tmp_8913F; + assign sv2v_tmp_8913F = special_result; + always @(*) mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] = sv2v_tmp_8913F; + wire [5:1] sv2v_tmp_9D338; + assign sv2v_tmp_9D338 = special_status; + always @(*) mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * 5+:5] = sv2v_tmp_9D338; + wire [1:1] sv2v_tmp_7259D; + assign sv2v_tmp_7259D = inp_pipe_tag_q[NUM_INP_REGS]; + always @(*) mid_pipe_tag_q[0] = sv2v_tmp_7259D; + wire [1:1] sv2v_tmp_FAFEF; + assign sv2v_tmp_FAFEF = inp_pipe_mask_q[NUM_INP_REGS]; + always @(*) mid_pipe_mask_q[0] = sv2v_tmp_FAFEF; + wire [1:1] sv2v_tmp_8CE3D; + assign sv2v_tmp_8CE3D = inp_pipe_aux_q[NUM_INP_REGS]; + always @(*) mid_pipe_aux_q[0] = sv2v_tmp_8CE3D; + wire [1:1] sv2v_tmp_C7159; + assign sv2v_tmp_C7159 = inp_pipe_valid_q[NUM_INP_REGS]; + always @(*) mid_pipe_valid_q[0] = sv2v_tmp_C7159; + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + genvar _gv_i_8; + generate + for (_gv_i_8 = 0; _gv_i_8 < NUM_MID_REGS; _gv_i_8 = _gv_i_8 + 1) begin : gen_inside_pipeline + localparam i = _gv_i_8; + wire reg_ena; + assign mid_pipe_ready[i] = mid_pipe_ready[i + 1] | ~mid_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_valid_q[i + 1] <= 1'b0; + else + mid_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (mid_pipe_ready[i] ? mid_pipe_valid_q[i] : mid_pipe_valid_q[i + 1])); + assign reg_ena = (mid_pipe_ready[i] & mid_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_eff_sub_q[i + 1] <= 1'sb0; + else + mid_pipe_eff_sub_q[i + 1] <= (reg_ena ? mid_pipe_eff_sub_q[i] : mid_pipe_eff_sub_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= 1'sb0; + else + mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= (reg_ena ? mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * EXP_WIDTH+:EXP_WIDTH] : mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= 1'sb0; + else + mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= (reg_ena ? mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * EXP_WIDTH+:EXP_WIDTH] : mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= 1'sb0; + else + mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= (reg_ena ? mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * EXP_WIDTH+:EXP_WIDTH] : mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] <= 1'sb0; + else + mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] <= (reg_ena ? mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] : mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_sticky_q[i + 1] <= 1'sb0; + else + mid_pipe_sticky_q[i + 1] <= (reg_ena ? mid_pipe_sticky_q[i] : mid_pipe_sticky_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] <= 1'sb0; + else + mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] <= (reg_ena ? mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] : mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_final_sign_q[i + 1] <= 1'sb0; + else + mid_pipe_final_sign_q[i + 1] <= (reg_ena ? mid_pipe_final_sign_q[i] : mid_pipe_final_sign_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3] <= (reg_ena ? mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * 3+:3] : mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_res_is_spec_q[i + 1] <= 1'sb0; + else + mid_pipe_res_is_spec_q[i + 1] <= (reg_ena ? mid_pipe_res_is_spec_q[i] : mid_pipe_res_is_spec_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] <= 1'sb0; + else + mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] <= (reg_ena ? mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] : mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 5+:5] <= (reg_ena ? mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * 5+:5] : mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_tag_q[i + 1] <= 1'b0; + else + mid_pipe_tag_q[i + 1] <= (reg_ena ? mid_pipe_tag_q[i] : mid_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_mask_q[i + 1] <= 1'sb0; + else + mid_pipe_mask_q[i + 1] <= (reg_ena ? mid_pipe_mask_q[i] : mid_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_aux_q[i + 1] <= 1'b0; + else + mid_pipe_aux_q[i + 1] <= (reg_ena ? mid_pipe_aux_q[i] : mid_pipe_aux_q[i + 1]); + end + endgenerate + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH]; + assign exponent_difference_q = mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH]; + assign addend_shamt_q = mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; + assign sum_q = mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * 3+:3]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; + assign special_result_q = mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS]; + assign special_status_q = mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * 5+:5]; + wire [LOWER_SUM_WIDTH - 1:0] sum_lower; + wire [LZC_RESULT_WIDTH - 1:0] leading_zero_count; + wire signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; + wire lzc_zeroes; + reg [SHIFT_AMOUNT_WIDTH - 1:0] norm_shamt; + reg signed [EXP_WIDTH - 1:0] normalized_exponent; + wire [(3 * PRECISION_BITS) + 4:0] sum_shifted; + reg [PRECISION_BITS:0] final_mantissa; + reg [(2 * PRECISION_BITS) + 2:0] sum_sticky_bits; + wire sticky_after_norm; + reg signed [EXP_WIDTH - 1:0] final_exponent; + assign sum_lower = sum_q[LOWER_SUM_WIDTH - 1:0]; + lzc #( + .WIDTH(LOWER_SUM_WIDTH), + .MODE(1) + ) i_lzc( + .in_i(sum_lower), + .cnt_o(leading_zero_count), + .empty_o(lzc_zeroes) + ); + assign leading_zero_count_sgn = $signed({1'b0, leading_zero_count}); + always @(*) begin : norm_shift_amount + if (_sv2v_0) + ; + if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin + if ((((exponent_product_q - leading_zero_count_sgn) + 1) >= 0) && !lzc_zeroes) begin + norm_shamt = (PRECISION_BITS + 2) + leading_zero_count; + normalized_exponent = (exponent_product_q - leading_zero_count_sgn) + 1; + end + else begin + norm_shamt = $unsigned(($signed(PRECISION_BITS) + 2) + exponent_product_q); + normalized_exponent = 0; + end + end + else begin + norm_shamt = addend_shamt_q; + normalized_exponent = tentative_exponent_q; + end + end + assign sum_shifted = sum_q << norm_shamt; + always @(*) begin : small_norm + if (_sv2v_0) + ; + {final_mantissa, sum_sticky_bits} = sum_shifted; + final_exponent = normalized_exponent; + if (sum_shifted[(3 * PRECISION_BITS) + 4]) begin + {final_mantissa, sum_sticky_bits} = sum_shifted >> 1; + final_exponent = normalized_exponent + 1; + end + else if (sum_shifted[(3 * PRECISION_BITS) + 3]) + ; + else if (normalized_exponent > 1) begin + {final_mantissa, sum_sticky_bits} = sum_shifted << 1; + final_exponent = normalized_exponent - 1; + end + else + final_exponent = 1'sb0; + end + assign sticky_after_norm = |{sum_sticky_bits} | sticky_before_add_q; + wire pre_round_sign; + wire [EXP_BITS - 1:0] pre_round_exponent; + wire [MAN_BITS - 1:0] pre_round_mantissa; + wire [(EXP_BITS + MAN_BITS) - 1:0] pre_round_abs; + wire [1:0] round_sticky_bits; + wire of_before_round; + wire of_after_round; + wire uf_before_round; + wire uf_after_round; + wire result_zero; + wire rounded_sign; + wire [(EXP_BITS + MAN_BITS) - 1:0] rounded_abs; + assign of_before_round = final_exponent >= ((2 ** EXP_BITS) - 1); + assign uf_before_round = final_exponent == 0; + assign pre_round_sign = final_sign_q; + assign pre_round_exponent = (of_before_round ? (2 ** EXP_BITS) - 2 : $unsigned(final_exponent[EXP_BITS - 1:0])); + assign pre_round_mantissa = (of_before_round ? {MAN_BITS {1'sb1}} : final_mantissa[MAN_BITS:1]); + assign pre_round_abs = {pre_round_exponent, pre_round_mantissa}; + assign round_sticky_bits = (of_before_round ? 2'b11 : {final_mantissa[0], sticky_after_norm}); + fpnew_rounding #(.AbsWidth(EXP_BITS + MAN_BITS)) i_fpnew_rounding( + .abs_value_i(pre_round_abs), + .sign_i(pre_round_sign), + .round_sticky_bits_i(round_sticky_bits), + .rnd_mode_i(rnd_mode_q), + .effective_subtraction_i(effective_subtraction_q), + .abs_rounded_o(rounded_abs), + .sign_o(rounded_sign), + .exact_zero_o(result_zero) + ); + assign uf_after_round = (rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb0}}) || (((pre_round_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb0}}) && (rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == 1)) && ((round_sticky_bits != 2'b11) || (!sum_sticky_bits[(MAN_BITS * 2) + 4] && ((rnd_mode_q == 3'b000) || (rnd_mode_q == 3'b100))))); + assign of_after_round = rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb1}}; + wire [WIDTH - 1:0] regular_result; + wire [4:0] regular_status; + assign regular_result = {rounded_sign, rounded_abs}; + assign regular_status[4] = 1'b0; + assign regular_status[3] = 1'b0; + assign regular_status[2] = of_before_round | of_after_round; + assign regular_status[1] = uf_after_round & regular_status[0]; + assign regular_status[0] = (|round_sticky_bits | of_before_round) | of_after_round; + wire [((1 + EXP_BITS) + MAN_BITS) - 1:0] result_d; + wire [4:0] status_d; + assign result_d = (result_is_special_q ? special_result_q : regular_result); + assign status_d = (result_is_special_q ? special_status_q : regular_status); + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * ((1 + EXP_BITS) + MAN_BITS)) + ((NUM_OUT_REGS * ((1 + EXP_BITS) + MAN_BITS)) - 1) : ((NUM_OUT_REGS + 1) * ((1 + EXP_BITS) + MAN_BITS)) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * ((1 + EXP_BITS) + MAN_BITS) : 0)] out_pipe_result_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * 5) + ((NUM_OUT_REGS * 5) - 1) : ((NUM_OUT_REGS + 1) * 5) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * 5 : 0)] out_pipe_status_q; + reg [0:NUM_OUT_REGS] out_pipe_tag_q; + reg [0:NUM_OUT_REGS] out_pipe_mask_q; + reg [0:NUM_OUT_REGS] out_pipe_aux_q; + reg [0:NUM_OUT_REGS] out_pipe_valid_q; + wire [0:NUM_OUT_REGS] out_pipe_ready; + wire [((1 + EXP_BITS) + MAN_BITS) * 1:1] sv2v_tmp_4232B; + assign sv2v_tmp_4232B = result_d; + always @(*) out_pipe_result_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] = sv2v_tmp_4232B; + wire [5:1] sv2v_tmp_07934; + assign sv2v_tmp_07934 = status_d; + always @(*) out_pipe_status_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * 5+:5] = sv2v_tmp_07934; + wire [1:1] sv2v_tmp_1CCC3; + assign sv2v_tmp_1CCC3 = mid_pipe_tag_q[NUM_MID_REGS]; + always @(*) out_pipe_tag_q[0] = sv2v_tmp_1CCC3; + wire [1:1] sv2v_tmp_D6E81; + assign sv2v_tmp_D6E81 = mid_pipe_mask_q[NUM_MID_REGS]; + always @(*) out_pipe_mask_q[0] = sv2v_tmp_D6E81; + wire [1:1] sv2v_tmp_F4A83; + assign sv2v_tmp_F4A83 = mid_pipe_aux_q[NUM_MID_REGS]; + always @(*) out_pipe_aux_q[0] = sv2v_tmp_F4A83; + wire [1:1] sv2v_tmp_E45E7; + assign sv2v_tmp_E45E7 = mid_pipe_valid_q[NUM_MID_REGS]; + always @(*) out_pipe_valid_q[0] = sv2v_tmp_E45E7; + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + genvar _gv_i_9; + generate + for (_gv_i_9 = 0; _gv_i_9 < NUM_OUT_REGS; _gv_i_9 = _gv_i_9 + 1) begin : gen_output_pipeline + localparam i = _gv_i_9; + wire reg_ena; + assign out_pipe_ready[i] = out_pipe_ready[i + 1] | ~out_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_valid_q[i + 1] <= 1'b0; + else + out_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (out_pipe_ready[i] ? out_pipe_valid_q[i] : out_pipe_valid_q[i + 1])); + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[(NUM_INP_REGS + NUM_MID_REGS) + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] <= 1'sb0; + else + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] <= (reg_ena ? out_pipe_result_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] : out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= (reg_ena ? out_pipe_status_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * 5+:5] : out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_tag_q[i + 1] <= 1'b0; + else + out_pipe_tag_q[i + 1] <= (reg_ena ? out_pipe_tag_q[i] : out_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_mask_q[i + 1] <= 1'sb0; + else + out_pipe_mask_q[i + 1] <= (reg_ena ? out_pipe_mask_q[i] : out_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_aux_q[i + 1] <= 1'b0; + else + out_pipe_aux_q[i + 1] <= (reg_ena ? out_pipe_aux_q[i] : out_pipe_aux_q[i + 1]); + end + endgenerate + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + assign result_o = out_pipe_result_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS]; + assign status_o = out_pipe_status_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * 5+:5]; + assign extension_bit_o = 1'b1; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = |{inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}; + generate + if (NUM_OUT_REGS > 0) begin : genblk4 + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], out_pipe_valid_q[NUM_OUT_REGS - 1]}; + end + else if (NUM_MID_REGS > 0) begin : genblk4 + assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS], mid_pipe_valid_q[NUM_MID_REGS - 1]}; + end + else if (NUM_INP_REGS > 0) begin : genblk4 + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], inp_pipe_valid_q[NUM_INP_REGS - 1]}; + end + else begin : genblk4 + assign early_out_valid_o = 1'b0; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module fpnew_fma_multi_B5D6B_2D261 ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + src_fmt_i, + src2_fmt_i, + dst_fmt_i, + tag_i, + mask_i, + aux_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + mask_o, + aux_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + parameter [31:0] AuxType_AUX_BITS = 0; + reg _sv2v_0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + parameter [0:4] FpFmtConfig = 1'sb1; + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + function automatic signed [31:0] fpnew_pkg_maximum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_maximum = (a > b ? a : b); + endfunction + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + function automatic [31:0] fpnew_pkg_max_fp_width; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_1 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) + res = $unsigned(fpnew_pkg_maximum(res, fpnew_pkg_fp_width(sv2v_cast_5D882(i)))); + end + fpnew_pkg_max_fp_width = res; + end + endfunction + localparam [31:0] WIDTH = fpnew_pkg_max_fp_width(FpFmtConfig); + localparam [31:0] NUM_FORMATS = fpnew_pkg_NUM_FP_FORMATS; + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [(3 * WIDTH) - 1:0] operands_i; + input wire [14:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire [2:0] src_fmt_i; + input wire [2:0] src2_fmt_i; + input wire [2:0] dst_fmt_i; + input wire tag_i; + input wire mask_i; + input wire [AuxType_AUX_BITS - 1:0] aux_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [WIDTH - 1:0] result_o; + output wire [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire mask_o; + output wire [AuxType_AUX_BITS - 1:0] aux_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + function automatic [31:0] fpnew_pkg_exp_bits; + input reg [2:0] fmt; + fpnew_pkg_exp_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32]; + endfunction + function automatic [31:0] fpnew_pkg_man_bits; + input reg [2:0] fmt; + fpnew_pkg_man_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]; + endfunction + function automatic [63:0] fpnew_pkg_super_format; + input reg [0:4] cfg; + reg [63:0] res; + begin + res = 1'sb0; + begin : sv2v_autoblock_2 + reg [31:0] fmt; + for (fmt = 0; fmt < fpnew_pkg_NUM_FP_FORMATS; fmt = fmt + 1) + if (cfg[fmt]) begin + res[63-:32] = $unsigned(fpnew_pkg_maximum(res[63-:32], fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)))); + res[31-:32] = $unsigned(fpnew_pkg_maximum(res[31-:32], fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)))); + end + end + fpnew_pkg_super_format = res; + end + endfunction + localparam [63:0] SUPER_FORMAT = fpnew_pkg_super_format(FpFmtConfig); + localparam [31:0] SUPER_EXP_BITS = SUPER_FORMAT[63-:32]; + localparam [31:0] SUPER_MAN_BITS = SUPER_FORMAT[31-:32]; + localparam [31:0] PRECISION_BITS = SUPER_MAN_BITS + 1; + localparam [31:0] LOWER_SUM_WIDTH = (2 * PRECISION_BITS) + 3; + localparam [31:0] LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH); + localparam [31:0] EXP_WIDTH = fpnew_pkg_maximum(SUPER_EXP_BITS + 2, LZC_RESULT_WIDTH); + localparam [31:0] SHIFT_AMOUNT_WIDTH = $clog2((3 * PRECISION_BITS) + 5); + localparam NUM_INP_REGS = (PipeConfig == 2'd0 ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 1) / 3 : 0)); + localparam NUM_MID_REGS = (PipeConfig == 2'd2 ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 2) / 3 : 0)); + localparam NUM_OUT_REGS = (PipeConfig == 2'd1 ? NumPipeRegs : (PipeConfig == 2'd3 ? NumPipeRegs / 3 : 0)); + wire [(3 * WIDTH) - 1:0] operands_q; + wire [2:0] src_fmt_q; + wire [2:0] src2_fmt_q; + wire [2:0] dst_fmt_q; + reg [((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) - (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)) + 1) * WIDTH) + (((0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) * WIDTH) - 1) : ((((0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)) + 1) * WIDTH) + (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) * WIDTH) - 1)):((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) * WIDTH : (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) * WIDTH)] inp_pipe_operands_q; + reg [((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) - (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0)) + 1) * 3) + (((0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) * 3) - 1) : ((((0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1)) + 1) * 3) + (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) * 3) - 1)):((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) * 3 : (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) * 3)] inp_pipe_is_boxed_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)] inp_pipe_rnd_mode_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_OP_BITS) + ((NUM_INP_REGS * fpnew_pkg_OP_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_OP_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_OP_BITS : 0)] inp_pipe_op_q; + reg [0:NUM_INP_REGS] inp_pipe_op_mod_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] inp_pipe_src_fmt_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] inp_pipe_src2_fmt_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] inp_pipe_dst_fmt_q; + reg [0:NUM_INP_REGS] inp_pipe_tag_q; + reg [0:NUM_INP_REGS] inp_pipe_mask_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * AuxType_AUX_BITS) + ((NUM_INP_REGS * AuxType_AUX_BITS) - 1) : ((NUM_INP_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * AuxType_AUX_BITS : 0)] inp_pipe_aux_q; + reg [0:NUM_INP_REGS] inp_pipe_valid_q; + wire [0:NUM_INP_REGS] inp_pipe_ready; + wire [3 * WIDTH:1] sv2v_tmp_2F660; + assign sv2v_tmp_2F660 = operands_i; + always @(*) inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] = sv2v_tmp_2F660; + wire [15:1] sv2v_tmp_F6596; + assign sv2v_tmp_F6596 = is_boxed_i; + always @(*) inp_pipe_is_boxed_q[3 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * NUM_FORMATS) + 4) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * NUM_FORMATS) + 4) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1)))+:15] = sv2v_tmp_F6596; + wire [3:1] sv2v_tmp_D6AA0; + assign sv2v_tmp_D6AA0 = rnd_mode_i; + always @(*) inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3+:3] = sv2v_tmp_D6AA0; + wire [4:1] sv2v_tmp_99256; + assign sv2v_tmp_99256 = op_i; + always @(*) inp_pipe_op_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] = sv2v_tmp_99256; + wire [1:1] sv2v_tmp_72E02; + assign sv2v_tmp_72E02 = op_mod_i; + always @(*) inp_pipe_op_mod_q[0] = sv2v_tmp_72E02; + wire [3:1] sv2v_tmp_97D9E; + assign sv2v_tmp_97D9E = src_fmt_i; + always @(*) inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_97D9E; + wire [3:1] sv2v_tmp_64EC0; + assign sv2v_tmp_64EC0 = src2_fmt_i; + always @(*) inp_pipe_src2_fmt_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_64EC0; + wire [3:1] sv2v_tmp_C878E; + assign sv2v_tmp_C878E = dst_fmt_i; + always @(*) inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_C878E; + wire [1:1] sv2v_tmp_DE624; + assign sv2v_tmp_DE624 = tag_i; + always @(*) inp_pipe_tag_q[0] = sv2v_tmp_DE624; + wire [1:1] sv2v_tmp_AE6A6; + assign sv2v_tmp_AE6A6 = mask_i; + always @(*) inp_pipe_mask_q[0] = sv2v_tmp_AE6A6; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_0E322; + assign sv2v_tmp_0E322 = aux_i; + always @(*) inp_pipe_aux_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_0E322; + wire [1:1] sv2v_tmp_CFC25; + assign sv2v_tmp_CFC25 = in_valid_i; + always @(*) inp_pipe_valid_q[0] = sv2v_tmp_CFC25; + assign in_ready_o = inp_pipe_ready[0]; + genvar _gv_i_10; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + function automatic [AuxType_AUX_BITS - 1:0] sv2v_cast_533F1; + input reg [AuxType_AUX_BITS - 1:0] inp; + sv2v_cast_533F1 = inp; + endfunction + generate + for (_gv_i_10 = 0; _gv_i_10 < NUM_INP_REGS; _gv_i_10 = _gv_i_10 + 1) begin : gen_input_pipeline + localparam i = _gv_i_10; + wire reg_ena; + assign inp_pipe_ready[i] = inp_pipe_ready[i + 1] | ~inp_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_valid_q[i + 1] <= 1'b0; + else + inp_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (inp_pipe_ready[i] ? inp_pipe_valid_q[i] : inp_pipe_valid_q[i + 1])); + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] <= 1'sb0; + else + inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] <= (reg_ena ? inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3] : inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_is_boxed_q[3 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS) + 4) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS) + 4) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1)))+:15] <= 1'sb0; + else + inp_pipe_is_boxed_q[3 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS) + 4) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS) + 4) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1)))+:15] <= (reg_ena ? inp_pipe_is_boxed_q[3 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * NUM_FORMATS) + 4) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * NUM_FORMATS) + 4) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1)))+:15] : inp_pipe_is_boxed_q[3 * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS) + 4) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * NUM_FORMATS) + 4) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1)))+:15]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= (reg_ena ? inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3+:3] : inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= sv2v_cast_4CD2E(0); + else + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= (reg_ena ? inp_pipe_op_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] : inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_mod_q[i + 1] <= 1'sb0; + else + inp_pipe_op_mod_q[i + 1] <= (reg_ena ? inp_pipe_op_mod_q[i] : inp_pipe_op_mod_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_src2_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + inp_pipe_src2_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? inp_pipe_src2_fmt_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : inp_pipe_src2_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_tag_q[i + 1] <= 1'b0; + else + inp_pipe_tag_q[i + 1] <= (reg_ena ? inp_pipe_tag_q[i] : inp_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_mask_q[i + 1] <= 1'sb0; + else + inp_pipe_mask_q[i + 1] <= (reg_ena ? inp_pipe_mask_q[i] : inp_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : inp_pipe_aux_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign operands_q = inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 2) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3) + 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1)))+:WIDTH * 3]; + assign src_fmt_q = inp_pipe_src_fmt_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign src2_fmt_q = inp_pipe_src2_fmt_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + wire [14:0] fmt_sign; + wire signed [(15 * SUPER_EXP_BITS) - 1:0] fmt_exponent; + wire [(15 * SUPER_MAN_BITS) - 1:0] fmt_mantissa; + wire [119:0] info_q; + genvar _gv_fmt_5; + localparam [0:0] fpnew_pkg_DONT_CARE = 1'b1; + function automatic [7:0] sv2v_cast_8; + input reg [7:0] inp; + sv2v_cast_8 = inp; + endfunction + function automatic signed [SUPER_EXP_BITS - 1:0] sv2v_cast_994BB_signed; + input reg signed [SUPER_EXP_BITS - 1:0] inp; + sv2v_cast_994BB_signed = inp; + endfunction + function automatic [SUPER_MAN_BITS - 1:0] sv2v_cast_3FC64; + input reg [SUPER_MAN_BITS - 1:0] inp; + sv2v_cast_3FC64 = inp; + endfunction + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + generate + for (_gv_fmt_5 = 0; _gv_fmt_5 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_5 = _gv_fmt_5 + 1) begin : fmt_init_inputs + localparam fmt = _gv_fmt_5; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + if (FpFmtConfig[fmt]) begin : active_format + localparam [2:0] FpFormat = sv2v_cast_5D882(fmt); + wire [(3 * FP_WIDTH) - 1:0] trimmed_ops; + fpnew_classifier #( + .FpFormat(FpFormat), + .NumOperands(3) + ) i_fpnew_classifier( + .operands_i(trimmed_ops), + .is_boxed_i(inp_pipe_is_boxed_q[((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) ? ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * NUM_FORMATS) + fmt : (0 >= NUM_INP_REGS ? NUM_INP_REGS * NUM_FORMATS : 0) - ((((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * NUM_FORMATS) + fmt) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * NUM_FORMATS) + ((NUM_INP_REGS * NUM_FORMATS) - 1) : ((NUM_INP_REGS + 1) * NUM_FORMATS) - 1))) * 3+:3]), + .info_o(info_q[8 * (fmt * 3)+:24]) + ); + genvar _gv_op_2; + for (_gv_op_2 = 0; _gv_op_2 < 3; _gv_op_2 = _gv_op_2 + 1) begin : gen_operands + localparam op = _gv_op_2; + assign trimmed_ops[op * fpnew_pkg_fp_width(sv2v_cast_5D882(_gv_fmt_5))+:fpnew_pkg_fp_width(sv2v_cast_5D882(_gv_fmt_5))] = operands_q[(op * WIDTH) + (FP_WIDTH - 1)-:FP_WIDTH]; + assign fmt_sign[(fmt * 3) + op] = operands_q[(op * WIDTH) + (FP_WIDTH - 1)]; + assign fmt_exponent[((fmt * 3) + op) * SUPER_EXP_BITS+:SUPER_EXP_BITS] = $signed({1'b0, operands_q[(op * WIDTH) + MAN_BITS+:EXP_BITS]}); + assign fmt_mantissa[((fmt * 3) + op) * SUPER_MAN_BITS+:SUPER_MAN_BITS] = {info_q[(((fmt * 3) + op) * 8) + 7], operands_q[(op * WIDTH) + (MAN_BITS - 1)-:MAN_BITS]} << (SUPER_MAN_BITS - MAN_BITS); + end + end + else begin : inactive_format + assign info_q[8 * (fmt * 3)+:24] = {3 {sv2v_cast_8(fpnew_pkg_DONT_CARE)}}; + assign fmt_sign[fmt * 3+:3] = fpnew_pkg_DONT_CARE; + assign fmt_exponent[SUPER_EXP_BITS * (fmt * 3)+:SUPER_EXP_BITS * 3] = {3 {sv2v_cast_994BB_signed(fpnew_pkg_DONT_CARE)}}; + assign fmt_mantissa[SUPER_MAN_BITS * (fmt * 3)+:SUPER_MAN_BITS * 3] = {3 {sv2v_cast_3FC64(fpnew_pkg_DONT_CARE)}}; + end + end + endgenerate + reg [((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS) - 1:0] operand_a; + reg [((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS) - 1:0] operand_b; + reg [((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS) - 1:0] operand_c; + reg [7:0] info_a; + reg [7:0] info_b; + reg [7:0] info_c; + function automatic [31:0] fpnew_pkg_bias; + input reg [2:0] fmt; + fpnew_pkg_bias = $unsigned((2 ** (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] - 1)) - 1); + endfunction + function automatic [SUPER_EXP_BITS - 1:0] sv2v_cast_994BB; + input reg [SUPER_EXP_BITS - 1:0] inp; + sv2v_cast_994BB = inp; + endfunction + function automatic [SUPER_MAN_BITS - 1:0] sv2v_cast_2F96C; + input reg [SUPER_MAN_BITS - 1:0] inp; + sv2v_cast_2F96C = inp; + endfunction + function automatic [SUPER_EXP_BITS - 1:0] sv2v_cast_1FC93; + input reg [SUPER_EXP_BITS - 1:0] inp; + sv2v_cast_1FC93 = inp; + endfunction + always @(*) begin : op_select + if (_sv2v_0) + ; + operand_a = {fmt_sign[src_fmt_q * 3], fmt_exponent[(src_fmt_q * 3) * SUPER_EXP_BITS+:SUPER_EXP_BITS], fmt_mantissa[(src_fmt_q * 3) * SUPER_MAN_BITS+:SUPER_MAN_BITS]}; + operand_b = {fmt_sign[(src_fmt_q * 3) + 1], fmt_exponent[((src_fmt_q * 3) + 1) * SUPER_EXP_BITS+:SUPER_EXP_BITS], fmt_mantissa[((src_fmt_q * 3) + 1) * SUPER_MAN_BITS+:SUPER_MAN_BITS]}; + operand_c = {fmt_sign[(src2_fmt_q * 3) + 2], fmt_exponent[((src2_fmt_q * 3) + 2) * SUPER_EXP_BITS+:SUPER_EXP_BITS], fmt_mantissa[((src2_fmt_q * 3) + 2) * SUPER_MAN_BITS+:SUPER_MAN_BITS]}; + info_a = info_q[(src_fmt_q * 3) * 8+:8]; + info_b = info_q[((src_fmt_q * 3) + 1) * 8+:8]; + info_c = info_q[((src2_fmt_q * 3) + 2) * 8+:8]; + operand_c[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))] = operand_c[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))] ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + (* full_case, parallel_case *) + case (inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]) + sv2v_cast_4CD2E(0): + ; + sv2v_cast_4CD2E(1): operand_a[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))] = ~operand_a[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))]; + sv2v_cast_4CD2E(2), sv2v_cast_4CD2E(15): begin + operand_a = {1'b0, sv2v_cast_994BB(fpnew_pkg_bias(src_fmt_q)), sv2v_cast_2F96C(1'sb0)}; + info_a = 8'b10000001; + end + sv2v_cast_4CD2E(3): begin + if (inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3] == 3'b010) + operand_c = {1'b0, sv2v_cast_1FC93(1'sb0), sv2v_cast_2F96C(1'sb0)}; + else + operand_c = {1'b1, sv2v_cast_1FC93(1'sb0), sv2v_cast_2F96C(1'sb0)}; + info_c = 8'b00100001; + end + default: begin + operand_a = {fpnew_pkg_DONT_CARE, sv2v_cast_994BB(fpnew_pkg_DONT_CARE), sv2v_cast_3FC64(fpnew_pkg_DONT_CARE)}; + operand_b = {fpnew_pkg_DONT_CARE, sv2v_cast_994BB(fpnew_pkg_DONT_CARE), sv2v_cast_3FC64(fpnew_pkg_DONT_CARE)}; + operand_c = {fpnew_pkg_DONT_CARE, sv2v_cast_994BB(fpnew_pkg_DONT_CARE), sv2v_cast_3FC64(fpnew_pkg_DONT_CARE)}; + info_a = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + info_b = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + info_c = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + end + endcase + end + wire any_operand_inf; + wire any_operand_nan; + wire signalling_nan; + wire effective_subtraction; + wire tentative_sign; + assign any_operand_inf = |{info_a[4], info_b[4], info_c[4]}; + assign any_operand_nan = |{info_a[3], info_b[3], info_c[3]}; + assign signalling_nan = |{info_a[2], info_b[2], info_c[2]}; + assign effective_subtraction = (operand_a[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))] ^ operand_b[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))]) ^ operand_c[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))]; + assign tentative_sign = operand_a[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))] ^ operand_b[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))]; + wire [WIDTH - 1:0] special_result; + wire [4:0] special_status; + wire result_is_special; + reg [(NUM_FORMATS * WIDTH) - 1:0] fmt_special_result; + reg [24:0] fmt_special_status; + reg [4:0] fmt_result_is_special; + genvar _gv_fmt_6; + generate + for (_gv_fmt_6 = 0; _gv_fmt_6 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_6 = _gv_fmt_6 + 1) begin : gen_special_results + localparam fmt = _gv_fmt_6; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + localparam [EXP_BITS - 1:0] QNAN_EXPONENT = 1'sb1; + localparam [MAN_BITS - 1:0] QNAN_MANTISSA = 2 ** (MAN_BITS - 1); + localparam [MAN_BITS - 1:0] ZERO_MANTISSA = 1'sb0; + if (FpFmtConfig[fmt]) begin : active_format + always @(*) begin : special_results + reg [FP_WIDTH - 1:0] special_res; + if (_sv2v_0) + ; + special_res = {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; + fmt_special_status[fmt * 5+:5] = 1'sb0; + fmt_result_is_special[fmt] = 1'b0; + if ((info_a[4] && info_b[5]) || (info_a[5] && info_b[4])) begin + fmt_result_is_special[fmt] = 1'b1; + fmt_special_status[(fmt * 5) + 4] = 1'b1; + end + else if (any_operand_nan) begin + fmt_result_is_special[fmt] = 1'b1; + fmt_special_status[(fmt * 5) + 4] = signalling_nan; + end + else if (any_operand_inf) begin + fmt_result_is_special[fmt] = 1'b1; + if (((info_a[4] || info_b[4]) && info_c[4]) && effective_subtraction) + fmt_special_status[(fmt * 5) + 4] = 1'b1; + else if (info_a[4] || info_b[4]) + special_res = {operand_a[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))] ^ operand_b[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))], QNAN_EXPONENT, ZERO_MANTISSA}; + else if (info_c[4]) + special_res = {operand_c[1 + (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))], QNAN_EXPONENT, ZERO_MANTISSA}; + end + fmt_special_result[fmt * WIDTH+:WIDTH] = 1'sb1; + fmt_special_result[(fmt * WIDTH) + (FP_WIDTH - 1)-:FP_WIDTH] = special_res; + end + end + else begin : inactive_format + wire [WIDTH * 1:1] sv2v_tmp_D05EE; + assign sv2v_tmp_D05EE = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) fmt_special_result[fmt * WIDTH+:WIDTH] = sv2v_tmp_D05EE; + wire [5:1] sv2v_tmp_0AFA1; + assign sv2v_tmp_0AFA1 = 1'sb0; + always @(*) fmt_special_status[fmt * 5+:5] = sv2v_tmp_0AFA1; + wire [1:1] sv2v_tmp_EE036; + assign sv2v_tmp_EE036 = 1'b0; + always @(*) fmt_result_is_special[fmt] = sv2v_tmp_EE036; + end + end + endgenerate + assign result_is_special = fmt_result_is_special[dst_fmt_q]; + assign special_status = fmt_special_status[dst_fmt_q * 5+:5]; + assign special_result = fmt_special_result[dst_fmt_q * WIDTH+:WIDTH]; + wire signed [EXP_WIDTH - 1:0] exponent_a; + wire signed [EXP_WIDTH - 1:0] exponent_b; + wire signed [EXP_WIDTH - 1:0] exponent_c; + wire signed [EXP_WIDTH - 1:0] exponent_addend; + wire signed [EXP_WIDTH - 1:0] exponent_product; + wire signed [EXP_WIDTH - 1:0] exponent_difference; + wire signed [EXP_WIDTH - 1:0] tentative_exponent; + assign exponent_a = $signed({1'b0, operand_a[SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)-:((SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)) >= (SUPER_MAN_BITS + 0) ? ((SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)) - (SUPER_MAN_BITS + 0)) + 1 : ((SUPER_MAN_BITS + 0) - (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))) + 1)]}); + assign exponent_b = $signed({1'b0, operand_b[SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)-:((SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)) >= (SUPER_MAN_BITS + 0) ? ((SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)) - (SUPER_MAN_BITS + 0)) + 1 : ((SUPER_MAN_BITS + 0) - (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))) + 1)]}); + assign exponent_c = $signed({1'b0, operand_c[SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)-:((SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)) >= (SUPER_MAN_BITS + 0) ? ((SUPER_EXP_BITS + (SUPER_MAN_BITS - 1)) - (SUPER_MAN_BITS + 0)) + 1 : ((SUPER_MAN_BITS + 0) - (SUPER_EXP_BITS + (SUPER_MAN_BITS - 1))) + 1)]}); + assign exponent_addend = (info_c[5] ? 1 : $signed(((exponent_c + $signed({1'b0, ~info_c[7]})) - $signed(fpnew_pkg_bias(src2_fmt_q))) + $signed(fpnew_pkg_bias(dst_fmt_q)))); + assign exponent_product = (info_a[5] || info_b[5] ? 2 - $signed(fpnew_pkg_bias(dst_fmt_q)) : $signed(((((exponent_a + info_a[6]) + exponent_b) + info_b[6]) - (2 * $signed(fpnew_pkg_bias(src_fmt_q)))) + $signed(fpnew_pkg_bias(dst_fmt_q)))); + assign exponent_difference = exponent_addend - exponent_product; + reg [SHIFT_AMOUNT_WIDTH - 1:0] addend_shamt; + always @(*) begin : addend_shift_amount + if (_sv2v_0) + ; + if (exponent_difference <= $signed((-2 * PRECISION_BITS) - 1)) + addend_shamt = (3 * PRECISION_BITS) + 4; + else if (exponent_difference <= $signed(PRECISION_BITS + 2)) + addend_shamt = $unsigned(($signed(PRECISION_BITS) + 3) - exponent_difference); + else + addend_shamt = 0; + end + wire [$clog2(SUPER_MAN_BITS) - 1:0] addend_lzc_count; + wire [$clog2(SUPER_MAN_BITS):0] addend_lzc_count_sgn; + reg [SHIFT_AMOUNT_WIDTH - 1:0] addend_normalize_shamt; + lzc #( + .WIDTH(SUPER_MAN_BITS), + .MODE(1) + ) i_addend_lzc( + .in_i(operand_c[SUPER_MAN_BITS - 1-:SUPER_MAN_BITS]), + .cnt_o(addend_lzc_count), + .empty_o() + ); + assign addend_lzc_count_sgn = $signed({1'b0, addend_lzc_count}); + always @(*) begin + if (_sv2v_0) + ; + if (info_c[7] || info_c[5]) + addend_normalize_shamt = 0; + else if (exponent_addend <= 1) + addend_normalize_shamt = 0; + else if ((addend_lzc_count_sgn + 1) < exponent_addend) + addend_normalize_shamt = addend_lzc_count + 1; + else + addend_normalize_shamt = exponent_addend - 1; + end + assign tentative_exponent = (exponent_difference > 0 ? exponent_addend - addend_normalize_shamt : exponent_product); + wire [PRECISION_BITS - 1:0] mantissa_a; + wire [PRECISION_BITS - 1:0] mantissa_b; + wire [PRECISION_BITS - 1:0] mantissa_c; + wire [(2 * PRECISION_BITS) - 1:0] product; + wire [(3 * PRECISION_BITS) + 3:0] product_shifted; + assign mantissa_a = {info_a[7], operand_a[SUPER_MAN_BITS - 1-:SUPER_MAN_BITS]}; + assign mantissa_b = {info_b[7], operand_b[SUPER_MAN_BITS - 1-:SUPER_MAN_BITS]}; + assign mantissa_c = {info_c[7], operand_c[SUPER_MAN_BITS - 1-:SUPER_MAN_BITS]}; + assign product = mantissa_a * mantissa_b; + assign product_shifted = product << 2; + wire [(3 * PRECISION_BITS) + 3:0] addend_after_shift; + wire [PRECISION_BITS - 1:0] addend_sticky_bits; + wire sticky_before_add; + wire [(3 * PRECISION_BITS) + 3:0] addend_shifted; + wire inject_carry_in; + assign {addend_after_shift, addend_sticky_bits} = (mantissa_c << ((3 * PRECISION_BITS) + 4)) >> addend_shamt; + assign sticky_before_add = |addend_sticky_bits; + assign addend_shifted = (effective_subtraction ? ~addend_after_shift : addend_after_shift); + assign inject_carry_in = effective_subtraction & ~sticky_before_add; + wire [(3 * PRECISION_BITS) + 4:0] sum_pos; + wire [(3 * PRECISION_BITS) + 4:0] sum_neg; + wire sum_carry; + wire [(3 * PRECISION_BITS) + 3:0] sum; + wire final_sign; + assign sum_pos = (product_shifted + addend_shifted) + inject_carry_in; + assign sum_carry = sum_pos[(3 * PRECISION_BITS) + 4]; + assign sum_neg = addend_after_shift - product_shifted; + assign sum = (effective_subtraction && ~sum_carry ? sum_neg : sum_pos); + assign final_sign = (effective_subtraction && (sum_carry == tentative_sign) ? 1'b1 : (effective_subtraction ? 1'b0 : tentative_sign)); + wire effective_subtraction_q; + wire signed [EXP_WIDTH - 1:0] exponent_product_q; + wire signed [EXP_WIDTH - 1:0] exponent_difference_q; + wire signed [EXP_WIDTH - 1:0] tentative_exponent_q; + wire [SHIFT_AMOUNT_WIDTH - 1:0] addend_shamt_q; + wire sticky_before_add_q; + wire [(3 * PRECISION_BITS) + 3:0] sum_q; + wire final_sign_q; + wire [2:0] dst_fmt_q2; + wire [2:0] rnd_mode_q; + wire result_is_special_q; + wire [((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS) - 1:0] special_result_q; + wire [4:0] special_status_q; + reg [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * EXP_WIDTH) + ((NUM_MID_REGS * EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * EXP_WIDTH : 0)] mid_pipe_exp_prod_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * EXP_WIDTH) + ((NUM_MID_REGS * EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * EXP_WIDTH : 0)] mid_pipe_exp_diff_q; + reg signed [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * EXP_WIDTH) + ((NUM_MID_REGS * EXP_WIDTH) - 1) : ((NUM_MID_REGS + 1) * EXP_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * EXP_WIDTH : 0)] mid_pipe_tent_exp_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * SHIFT_AMOUNT_WIDTH) + ((NUM_MID_REGS * SHIFT_AMOUNT_WIDTH) - 1) : ((NUM_MID_REGS + 1) * SHIFT_AMOUNT_WIDTH) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * SHIFT_AMOUNT_WIDTH : 0)] mid_pipe_add_shamt_q; + reg [0:NUM_MID_REGS] mid_pipe_sticky_q; + reg [(0 >= NUM_MID_REGS ? (((3 * PRECISION_BITS) + 3) >= 0 ? ((1 - NUM_MID_REGS) * ((3 * PRECISION_BITS) + 4)) + ((NUM_MID_REGS * ((3 * PRECISION_BITS) + 4)) - 1) : ((1 - NUM_MID_REGS) * (1 - ((3 * PRECISION_BITS) + 3))) + ((((3 * PRECISION_BITS) + 3) + (NUM_MID_REGS * (1 - ((3 * PRECISION_BITS) + 3)))) - 1)) : (((3 * PRECISION_BITS) + 3) >= 0 ? ((NUM_MID_REGS + 1) * ((3 * PRECISION_BITS) + 4)) - 1 : ((NUM_MID_REGS + 1) * (1 - ((3 * PRECISION_BITS) + 3))) + ((3 * PRECISION_BITS) + 2))):(0 >= NUM_MID_REGS ? (((3 * PRECISION_BITS) + 3) >= 0 ? NUM_MID_REGS * ((3 * PRECISION_BITS) + 4) : ((3 * PRECISION_BITS) + 3) + (NUM_MID_REGS * (1 - ((3 * PRECISION_BITS) + 3)))) : (((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3))] mid_pipe_sum_q; + reg [0:NUM_MID_REGS] mid_pipe_final_sign_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * 3) + ((NUM_MID_REGS * 3) - 1) : ((NUM_MID_REGS + 1) * 3) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * 3 : 0)] mid_pipe_rnd_mode_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS) + ((NUM_MID_REGS * fpnew_pkg_FP_FORMAT_BITS) - 1) : ((NUM_MID_REGS + 1) * fpnew_pkg_FP_FORMAT_BITS) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * fpnew_pkg_FP_FORMAT_BITS : 0)] mid_pipe_dst_fmt_q; + reg [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)) + ((NUM_MID_REGS * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)) - 1) : ((NUM_MID_REGS + 1) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS) : 0)] mid_pipe_spec_res_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * 5) + ((NUM_MID_REGS * 5) - 1) : ((NUM_MID_REGS + 1) * 5) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * 5 : 0)] mid_pipe_spec_stat_q; + reg [0:NUM_MID_REGS] mid_pipe_tag_q; + reg [0:NUM_MID_REGS] mid_pipe_mask_q; + reg [(0 >= NUM_MID_REGS ? ((1 - NUM_MID_REGS) * AuxType_AUX_BITS) + ((NUM_MID_REGS * AuxType_AUX_BITS) - 1) : ((NUM_MID_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_MID_REGS ? NUM_MID_REGS * AuxType_AUX_BITS : 0)] mid_pipe_aux_q; + reg [0:NUM_MID_REGS] mid_pipe_valid_q; + wire [0:NUM_MID_REGS] mid_pipe_ready; + wire [1:1] sv2v_tmp_301F1; + assign sv2v_tmp_301F1 = effective_subtraction; + always @(*) mid_pipe_eff_sub_q[0] = sv2v_tmp_301F1; + wire [EXP_WIDTH * 1:1] sv2v_tmp_C29F5; + assign sv2v_tmp_C29F5 = exponent_product; + always @(*) mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH] = sv2v_tmp_C29F5; + wire [EXP_WIDTH * 1:1] sv2v_tmp_24DD8; + assign sv2v_tmp_24DD8 = exponent_difference; + always @(*) mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH] = sv2v_tmp_24DD8; + wire [EXP_WIDTH * 1:1] sv2v_tmp_6091A; + assign sv2v_tmp_6091A = tentative_exponent; + always @(*) mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH] = sv2v_tmp_6091A; + wire [SHIFT_AMOUNT_WIDTH * 1:1] sv2v_tmp_25D5D; + assign sv2v_tmp_25D5D = addend_shamt + addend_normalize_shamt; + always @(*) mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] = sv2v_tmp_25D5D; + wire [1:1] sv2v_tmp_6A24C; + assign sv2v_tmp_6A24C = sticky_before_add; + always @(*) mid_pipe_sticky_q[0] = sv2v_tmp_6A24C; + wire [(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)) * 1:1] sv2v_tmp_6ABE6; + assign sv2v_tmp_6ABE6 = sum; + always @(*) mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] = sv2v_tmp_6ABE6; + wire [1:1] sv2v_tmp_9C379; + assign sv2v_tmp_9C379 = final_sign; + always @(*) mid_pipe_final_sign_q[0] = sv2v_tmp_9C379; + wire [3:1] sv2v_tmp_68647; + assign sv2v_tmp_68647 = inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]; + always @(*) mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * 3+:3] = sv2v_tmp_68647; + wire [3:1] sv2v_tmp_59791; + assign sv2v_tmp_59791 = dst_fmt_q; + always @(*) mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] = sv2v_tmp_59791; + wire [1:1] sv2v_tmp_08378; + assign sv2v_tmp_08378 = result_is_special; + always @(*) mid_pipe_res_is_spec_q[0] = sv2v_tmp_08378; + wire [((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS) * 1:1] sv2v_tmp_3E0BB; + assign sv2v_tmp_3E0BB = special_result; + always @(*) mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)+:(1 + SUPER_EXP_BITS) + SUPER_MAN_BITS] = sv2v_tmp_3E0BB; + wire [5:1] sv2v_tmp_80D24; + assign sv2v_tmp_80D24 = special_status; + always @(*) mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * 5+:5] = sv2v_tmp_80D24; + wire [1:1] sv2v_tmp_7259D; + assign sv2v_tmp_7259D = inp_pipe_tag_q[NUM_INP_REGS]; + always @(*) mid_pipe_tag_q[0] = sv2v_tmp_7259D; + wire [1:1] sv2v_tmp_FAFEF; + assign sv2v_tmp_FAFEF = inp_pipe_mask_q[NUM_INP_REGS]; + always @(*) mid_pipe_mask_q[0] = sv2v_tmp_FAFEF; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_45511; + assign sv2v_tmp_45511 = inp_pipe_aux_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + always @(*) mid_pipe_aux_q[(0 >= NUM_MID_REGS ? 0 : NUM_MID_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_45511; + wire [1:1] sv2v_tmp_C7159; + assign sv2v_tmp_C7159 = inp_pipe_valid_q[NUM_INP_REGS]; + always @(*) mid_pipe_valid_q[0] = sv2v_tmp_C7159; + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + genvar _gv_i_11; + generate + for (_gv_i_11 = 0; _gv_i_11 < NUM_MID_REGS; _gv_i_11 = _gv_i_11 + 1) begin : gen_inside_pipeline + localparam i = _gv_i_11; + wire reg_ena; + assign mid_pipe_ready[i] = mid_pipe_ready[i + 1] | ~mid_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_valid_q[i + 1] <= 1'b0; + else + mid_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (mid_pipe_ready[i] ? mid_pipe_valid_q[i] : mid_pipe_valid_q[i + 1])); + assign reg_ena = (mid_pipe_ready[i] & mid_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_eff_sub_q[i + 1] <= 1'sb0; + else + mid_pipe_eff_sub_q[i + 1] <= (reg_ena ? mid_pipe_eff_sub_q[i] : mid_pipe_eff_sub_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= 1'sb0; + else + mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= (reg_ena ? mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * EXP_WIDTH+:EXP_WIDTH] : mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= 1'sb0; + else + mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= (reg_ena ? mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * EXP_WIDTH+:EXP_WIDTH] : mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= 1'sb0; + else + mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH] <= (reg_ena ? mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * EXP_WIDTH+:EXP_WIDTH] : mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * EXP_WIDTH+:EXP_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] <= 1'sb0; + else + mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] <= (reg_ena ? mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH] : mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_sticky_q[i + 1] <= 1'sb0; + else + mid_pipe_sticky_q[i + 1] <= (reg_ena ? mid_pipe_sticky_q[i] : mid_pipe_sticky_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] <= 1'sb0; + else + mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] <= (reg_ena ? mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))] : mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_final_sign_q[i + 1] <= 1'sb0; + else + mid_pipe_final_sign_q[i + 1] <= (reg_ena ? mid_pipe_final_sign_q[i] : mid_pipe_final_sign_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3] <= (reg_ena ? mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * 3+:3] : mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= sv2v_cast_5D882(0); + else + mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] <= (reg_ena ? mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS] : mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_res_is_spec_q[i + 1] <= 1'sb0; + else + mid_pipe_res_is_spec_q[i + 1] <= (reg_ena ? mid_pipe_res_is_spec_q[i] : mid_pipe_res_is_spec_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)+:(1 + SUPER_EXP_BITS) + SUPER_MAN_BITS] <= 1'sb0; + else + mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)+:(1 + SUPER_EXP_BITS) + SUPER_MAN_BITS] <= (reg_ena ? mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)+:(1 + SUPER_EXP_BITS) + SUPER_MAN_BITS] : mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)+:(1 + SUPER_EXP_BITS) + SUPER_MAN_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 5+:5] <= (reg_ena ? mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * 5+:5] : mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_tag_q[i + 1] <= 1'b0; + else + mid_pipe_tag_q[i + 1] <= (reg_ena ? mid_pipe_tag_q[i] : mid_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_mask_q[i + 1] <= 1'sb0; + else + mid_pipe_mask_q[i + 1] <= (reg_ena ? mid_pipe_mask_q[i] : mid_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i : NUM_MID_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : mid_pipe_aux_q[(0 >= NUM_MID_REGS ? i + 1 : NUM_MID_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH]; + assign exponent_difference_q = mid_pipe_exp_diff_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * EXP_WIDTH+:EXP_WIDTH]; + assign addend_shamt_q = mid_pipe_add_shamt_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * SHIFT_AMOUNT_WIDTH+:SHIFT_AMOUNT_WIDTH]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; + assign sum_q = mid_pipe_sum_q[(((3 * PRECISION_BITS) + 3) >= 0 ? 0 : (3 * PRECISION_BITS) + 3) + ((0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * (((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3)))+:(((3 * PRECISION_BITS) + 3) >= 0 ? (3 * PRECISION_BITS) + 4 : 1 - ((3 * PRECISION_BITS) + 3))]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * 3+:3]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * fpnew_pkg_FP_FORMAT_BITS+:fpnew_pkg_FP_FORMAT_BITS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; + assign special_result_q = mid_pipe_spec_res_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * ((1 + SUPER_EXP_BITS) + SUPER_MAN_BITS)+:(1 + SUPER_EXP_BITS) + SUPER_MAN_BITS]; + assign special_status_q = mid_pipe_spec_stat_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * 5+:5]; + wire [LOWER_SUM_WIDTH - 1:0] sum_lower; + wire [LZC_RESULT_WIDTH - 1:0] leading_zero_count; + wire signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; + wire lzc_zeroes; + reg [SHIFT_AMOUNT_WIDTH - 1:0] norm_shamt; + reg signed [EXP_WIDTH - 1:0] normalized_exponent; + wire [(3 * PRECISION_BITS) + 4:0] sum_shifted; + reg [PRECISION_BITS:0] final_mantissa; + reg [(2 * PRECISION_BITS) + 2:0] sum_sticky_bits; + wire sticky_after_norm; + reg signed [EXP_WIDTH - 1:0] final_exponent; + assign sum_lower = sum_q[LOWER_SUM_WIDTH - 1:0]; + lzc #( + .WIDTH(LOWER_SUM_WIDTH), + .MODE(1) + ) i_lzc( + .in_i(sum_lower), + .cnt_o(leading_zero_count), + .empty_o(lzc_zeroes) + ); + assign leading_zero_count_sgn = $signed({1'b0, leading_zero_count}); + always @(*) begin : norm_shift_amount + if (_sv2v_0) + ; + if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin + if ((((exponent_product_q - leading_zero_count_sgn) + 1) >= 0) && !lzc_zeroes) begin + norm_shamt = (PRECISION_BITS + 2) + leading_zero_count; + normalized_exponent = (exponent_product_q - leading_zero_count_sgn) + 1; + end + else begin + norm_shamt = $unsigned($signed((PRECISION_BITS + 2) + exponent_product_q)); + normalized_exponent = 0; + end + end + else begin + norm_shamt = addend_shamt_q; + normalized_exponent = tentative_exponent_q; + end + end + assign sum_shifted = sum_q << norm_shamt; + always @(*) begin : small_norm + if (_sv2v_0) + ; + {final_mantissa, sum_sticky_bits} = sum_shifted; + final_exponent = normalized_exponent; + if (sum_shifted[(3 * PRECISION_BITS) + 4]) begin + {final_mantissa, sum_sticky_bits} = sum_shifted >> 1; + final_exponent = normalized_exponent + 1; + end + else if (sum_shifted[(3 * PRECISION_BITS) + 3]) + ; + else if (normalized_exponent > 1) begin + {final_mantissa, sum_sticky_bits} = sum_shifted << 1; + final_exponent = normalized_exponent - 1; + end + else + final_exponent = 1'sb0; + end + assign sticky_after_norm = |{sum_sticky_bits} | sticky_before_add_q; + wire pre_round_sign; + wire [(SUPER_EXP_BITS + SUPER_MAN_BITS) - 1:0] pre_round_abs; + wire [1:0] round_sticky_bits; + wire of_before_round; + wire of_after_round; + wire uf_before_round; + wire uf_after_round; + wire [(NUM_FORMATS * (SUPER_EXP_BITS + SUPER_MAN_BITS)) - 1:0] fmt_pre_round_abs; + wire [9:0] fmt_round_sticky_bits; + reg [4:0] fmt_of_after_round; + reg [4:0] fmt_uf_after_round; + wire rounded_sign; + wire [(SUPER_EXP_BITS + SUPER_MAN_BITS) - 1:0] rounded_abs; + wire result_zero; + assign of_before_round = final_exponent >= ((2 ** fpnew_pkg_exp_bits(dst_fmt_q2)) - 1); + assign uf_before_round = final_exponent == 0; + genvar _gv_fmt_7; + generate + for (_gv_fmt_7 = 0; _gv_fmt_7 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_7 = _gv_fmt_7 + 1) begin : gen_res_assemble + localparam fmt = _gv_fmt_7; + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + wire [EXP_BITS - 1:0] pre_round_exponent; + wire [MAN_BITS - 1:0] pre_round_mantissa; + if (FpFmtConfig[fmt]) begin : active_format + assign pre_round_exponent = (of_before_round ? (2 ** EXP_BITS) - 2 : final_exponent[EXP_BITS - 1:0]); + assign pre_round_mantissa = (of_before_round ? {fpnew_pkg_man_bits(sv2v_cast_5D882(_gv_fmt_7)) {1'sb1}} : final_mantissa[SUPER_MAN_BITS-:MAN_BITS]); + assign fmt_pre_round_abs[fmt * (SUPER_EXP_BITS + SUPER_MAN_BITS)+:SUPER_EXP_BITS + SUPER_MAN_BITS] = {pre_round_exponent, pre_round_mantissa}; + assign fmt_round_sticky_bits[(fmt * 2) + 1] = final_mantissa[SUPER_MAN_BITS - MAN_BITS] | of_before_round; + if (MAN_BITS < SUPER_MAN_BITS) begin : narrow_sticky + assign fmt_round_sticky_bits[fmt * 2] = (|final_mantissa[(SUPER_MAN_BITS - MAN_BITS) - 1:0] | sticky_after_norm) | of_before_round; + end + else begin : normal_sticky + assign fmt_round_sticky_bits[fmt * 2] = sticky_after_norm | of_before_round; + end + end + else begin : inactive_format + assign fmt_pre_round_abs[fmt * (SUPER_EXP_BITS + SUPER_MAN_BITS)+:SUPER_EXP_BITS + SUPER_MAN_BITS] = {SUPER_EXP_BITS + SUPER_MAN_BITS {fpnew_pkg_DONT_CARE}}; + assign fmt_round_sticky_bits[fmt * 2+:2] = {2 {fpnew_pkg_DONT_CARE}}; + end + end + endgenerate + assign pre_round_sign = final_sign_q; + assign pre_round_abs = fmt_pre_round_abs[dst_fmt_q2 * (SUPER_EXP_BITS + SUPER_MAN_BITS)+:SUPER_EXP_BITS + SUPER_MAN_BITS]; + assign round_sticky_bits = fmt_round_sticky_bits[dst_fmt_q2 * 2+:2]; + fpnew_rounding #(.AbsWidth(SUPER_EXP_BITS + SUPER_MAN_BITS)) i_fpnew_rounding( + .abs_value_i(pre_round_abs), + .sign_i(pre_round_sign), + .round_sticky_bits_i(round_sticky_bits), + .rnd_mode_i(rnd_mode_q), + .effective_subtraction_i(effective_subtraction_q), + .abs_rounded_o(rounded_abs), + .sign_o(rounded_sign), + .exact_zero_o(result_zero) + ); + reg [(NUM_FORMATS * WIDTH) - 1:0] fmt_result; + genvar _gv_fmt_8; + generate + for (_gv_fmt_8 = 0; _gv_fmt_8 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_8 = _gv_fmt_8 + 1) begin : gen_sign_inject + localparam fmt = _gv_fmt_8; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(sv2v_cast_5D882(fmt)); + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(sv2v_cast_5D882(fmt)); + if (FpFmtConfig[fmt]) begin : active_format + always @(*) begin : post_process + if (_sv2v_0) + ; + fmt_uf_after_round[fmt] = (rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb0}}) || (((pre_round_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb0}}) && (rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == 1)) && ((round_sticky_bits != 2'b11) || (!sum_sticky_bits[(MAN_BITS * 2) + 4] && ((rnd_mode_q == 3'b000) || (rnd_mode_q == 3'b100))))); + fmt_of_after_round[fmt] = rounded_abs[(EXP_BITS + MAN_BITS) - 1:MAN_BITS] == {(((EXP_BITS + MAN_BITS) - 1) >= MAN_BITS ? (((EXP_BITS + MAN_BITS) - 1) - MAN_BITS) + 1 : (MAN_BITS - ((EXP_BITS + MAN_BITS) - 1)) + 1) * 1 {1'sb1}}; + fmt_result[fmt * WIDTH+:WIDTH] = 1'sb1; + fmt_result[(fmt * WIDTH) + (FP_WIDTH - 1)-:FP_WIDTH] = {rounded_sign, rounded_abs[(EXP_BITS + MAN_BITS) - 1:0]}; + end + end + else begin : inactive_format + wire [1:1] sv2v_tmp_4C394; + assign sv2v_tmp_4C394 = fpnew_pkg_DONT_CARE; + always @(*) fmt_uf_after_round[fmt] = sv2v_tmp_4C394; + wire [1:1] sv2v_tmp_5852E; + assign sv2v_tmp_5852E = fpnew_pkg_DONT_CARE; + always @(*) fmt_of_after_round[fmt] = sv2v_tmp_5852E; + wire [WIDTH * 1:1] sv2v_tmp_49668; + assign sv2v_tmp_49668 = {WIDTH {fpnew_pkg_DONT_CARE}}; + always @(*) fmt_result[fmt * WIDTH+:WIDTH] = sv2v_tmp_49668; + end + end + endgenerate + assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; + assign of_after_round = fmt_of_after_round[dst_fmt_q2]; + wire [WIDTH - 1:0] regular_result; + wire [4:0] regular_status; + assign regular_result = fmt_result[dst_fmt_q2 * WIDTH+:WIDTH]; + assign regular_status[4] = 1'b0; + assign regular_status[3] = 1'b0; + assign regular_status[2] = of_before_round | of_after_round; + assign regular_status[1] = uf_after_round & regular_status[0]; + assign regular_status[0] = (|round_sticky_bits | of_before_round) | of_after_round; + wire [WIDTH - 1:0] result_d; + wire [4:0] status_d; + assign result_d = (result_is_special_q ? special_result_q : regular_result); + assign status_d = (result_is_special_q ? special_status_q : regular_status); + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * WIDTH) + ((NUM_OUT_REGS * WIDTH) - 1) : ((NUM_OUT_REGS + 1) * WIDTH) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * WIDTH : 0)] out_pipe_result_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * 5) + ((NUM_OUT_REGS * 5) - 1) : ((NUM_OUT_REGS + 1) * 5) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * 5 : 0)] out_pipe_status_q; + reg [0:NUM_OUT_REGS] out_pipe_tag_q; + reg [0:NUM_OUT_REGS] out_pipe_mask_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * AuxType_AUX_BITS) + ((NUM_OUT_REGS * AuxType_AUX_BITS) - 1) : ((NUM_OUT_REGS + 1) * AuxType_AUX_BITS) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * AuxType_AUX_BITS : 0)] out_pipe_aux_q; + reg [0:NUM_OUT_REGS] out_pipe_valid_q; + wire [0:NUM_OUT_REGS] out_pipe_ready; + wire [WIDTH * 1:1] sv2v_tmp_469C2; + assign sv2v_tmp_469C2 = result_d; + always @(*) out_pipe_result_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * WIDTH+:WIDTH] = sv2v_tmp_469C2; + wire [5:1] sv2v_tmp_A6238; + assign sv2v_tmp_A6238 = status_d; + always @(*) out_pipe_status_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * 5+:5] = sv2v_tmp_A6238; + wire [1:1] sv2v_tmp_1CCC3; + assign sv2v_tmp_1CCC3 = mid_pipe_tag_q[NUM_MID_REGS]; + always @(*) out_pipe_tag_q[0] = sv2v_tmp_1CCC3; + wire [1:1] sv2v_tmp_D6E81; + assign sv2v_tmp_D6E81 = mid_pipe_mask_q[NUM_MID_REGS]; + always @(*) out_pipe_mask_q[0] = sv2v_tmp_D6E81; + wire [AuxType_AUX_BITS * 1:1] sv2v_tmp_1BC38; + assign sv2v_tmp_1BC38 = mid_pipe_aux_q[(0 >= NUM_MID_REGS ? NUM_MID_REGS : NUM_MID_REGS - NUM_MID_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + always @(*) out_pipe_aux_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS] = sv2v_tmp_1BC38; + wire [1:1] sv2v_tmp_E45E7; + assign sv2v_tmp_E45E7 = mid_pipe_valid_q[NUM_MID_REGS]; + always @(*) out_pipe_valid_q[0] = sv2v_tmp_E45E7; + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + genvar _gv_i_12; + generate + for (_gv_i_12 = 0; _gv_i_12 < NUM_OUT_REGS; _gv_i_12 = _gv_i_12 + 1) begin : gen_output_pipeline + localparam i = _gv_i_12; + wire reg_ena; + assign out_pipe_ready[i] = out_pipe_ready[i + 1] | ~out_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_valid_q[i + 1] <= 1'b0; + else + out_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (out_pipe_ready[i] ? out_pipe_valid_q[i] : out_pipe_valid_q[i + 1])); + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[(NUM_INP_REGS + NUM_MID_REGS) + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH] <= 1'sb0; + else + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH] <= (reg_ena ? out_pipe_result_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * WIDTH+:WIDTH] : out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * WIDTH+:WIDTH]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= (reg_ena ? out_pipe_status_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * 5+:5] : out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_tag_q[i + 1] <= 1'b0; + else + out_pipe_tag_q[i + 1] <= (reg_ena ? out_pipe_tag_q[i] : out_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_mask_q[i + 1] <= 1'sb0; + else + out_pipe_mask_q[i + 1] <= (reg_ena ? out_pipe_mask_q[i] : out_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= sv2v_cast_533F1(1'sb0); + else + out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS] <= (reg_ena ? out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * AuxType_AUX_BITS+:AuxType_AUX_BITS] : out_pipe_aux_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * AuxType_AUX_BITS+:AuxType_AUX_BITS]); + end + endgenerate + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + assign result_o = out_pipe_result_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * WIDTH+:WIDTH]; + assign status_o = out_pipe_status_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * 5+:5]; + assign extension_bit_o = 1'b1; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * AuxType_AUX_BITS+:AuxType_AUX_BITS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = |{inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}; + generate + if (NUM_OUT_REGS > 0) begin : genblk8 + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], out_pipe_valid_q[NUM_OUT_REGS - 1]}; + end + else if (NUM_MID_REGS > 0) begin : genblk8 + assign early_out_valid_o = |{mid_pipe_valid_q[NUM_MID_REGS] & ~mid_pipe_ready[NUM_OUT_REGS], mid_pipe_valid_q[NUM_MID_REGS - 1]}; + end + else if (NUM_INP_REGS > 0) begin : genblk8 + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], inp_pipe_valid_q[NUM_INP_REGS - 1]}; + end + else begin : genblk8 + assign early_out_valid_o = 1'b0; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module fpnew_noncomp_DE16F ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + tag_i, + mask_i, + aux_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + class_mask_o, + is_class_o, + tag_o, + mask_o, + aux_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + reg _sv2v_0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + parameter [2:0] FpFormat = sv2v_cast_5D882(0); + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + localparam [31:0] WIDTH = fpnew_pkg_fp_width(FpFormat); + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [(2 * WIDTH) - 1:0] operands_i; + input wire [1:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire tag_i; + input wire mask_i; + input wire aux_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [WIDTH - 1:0] result_o; + output wire [4:0] status_o; + output wire extension_bit_o; + output wire [9:0] class_mask_o; + output wire is_class_o; + output wire tag_o; + output wire mask_o; + output wire aux_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + function automatic [31:0] fpnew_pkg_exp_bits; + input reg [2:0] fmt; + fpnew_pkg_exp_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32]; + endfunction + localparam [31:0] EXP_BITS = fpnew_pkg_exp_bits(FpFormat); + function automatic [31:0] fpnew_pkg_man_bits; + input reg [2:0] fmt; + fpnew_pkg_man_bits = fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]; + endfunction + localparam [31:0] MAN_BITS = fpnew_pkg_man_bits(FpFormat); + localparam NUM_INP_REGS = ((PipeConfig == 2'd0) || (PipeConfig == 2'd2) ? NumPipeRegs : (PipeConfig == 2'd3 ? (NumPipeRegs + 1) / 2 : 0)); + localparam NUM_OUT_REGS = (PipeConfig == 2'd1 ? NumPipeRegs : (PipeConfig == 2'd3 ? NumPipeRegs / 2 : 0)); + reg [((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) - (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0)) + 1) * WIDTH) + (((0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) * WIDTH) - 1) : ((((0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)) + 1) * WIDTH) + (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) * WIDTH) - 1)):((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) * WIDTH : (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) * WIDTH)] inp_pipe_operands_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0)] inp_pipe_is_boxed_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 3) + ((NUM_INP_REGS * 3) - 1) : ((NUM_INP_REGS + 1) * 3) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * 3 : 0)] inp_pipe_rnd_mode_q; + reg [(0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * fpnew_pkg_OP_BITS) + ((NUM_INP_REGS * fpnew_pkg_OP_BITS) - 1) : ((NUM_INP_REGS + 1) * fpnew_pkg_OP_BITS) - 1):(0 >= NUM_INP_REGS ? NUM_INP_REGS * fpnew_pkg_OP_BITS : 0)] inp_pipe_op_q; + reg [0:NUM_INP_REGS] inp_pipe_op_mod_q; + reg [0:NUM_INP_REGS] inp_pipe_tag_q; + reg [0:NUM_INP_REGS] inp_pipe_mask_q; + reg [0:NUM_INP_REGS] inp_pipe_aux_q; + reg [0:NUM_INP_REGS] inp_pipe_valid_q; + wire [0:NUM_INP_REGS] inp_pipe_ready; + wire [2 * WIDTH:1] sv2v_tmp_E768C; + assign sv2v_tmp_E768C = operands_i; + always @(*) inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:WIDTH * 2] = sv2v_tmp_E768C; + wire [2:1] sv2v_tmp_9866C; + assign sv2v_tmp_9866C = is_boxed_i; + always @(*) inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 2+:2] = sv2v_tmp_9866C; + wire [3:1] sv2v_tmp_B26FC; + assign sv2v_tmp_B26FC = rnd_mode_i; + always @(*) inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * 3+:3] = sv2v_tmp_B26FC; + wire [4:1] sv2v_tmp_6E66E; + assign sv2v_tmp_6E66E = op_i; + always @(*) inp_pipe_op_q[(0 >= NUM_INP_REGS ? 0 : NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] = sv2v_tmp_6E66E; + wire [1:1] sv2v_tmp_72E02; + assign sv2v_tmp_72E02 = op_mod_i; + always @(*) inp_pipe_op_mod_q[0] = sv2v_tmp_72E02; + wire [1:1] sv2v_tmp_DE624; + assign sv2v_tmp_DE624 = tag_i; + always @(*) inp_pipe_tag_q[0] = sv2v_tmp_DE624; + wire [1:1] sv2v_tmp_AE6A6; + assign sv2v_tmp_AE6A6 = mask_i; + always @(*) inp_pipe_mask_q[0] = sv2v_tmp_AE6A6; + wire [1:1] sv2v_tmp_683C4; + assign sv2v_tmp_683C4 = aux_i; + always @(*) inp_pipe_aux_q[0] = sv2v_tmp_683C4; + wire [1:1] sv2v_tmp_CFC25; + assign sv2v_tmp_CFC25 = in_valid_i; + always @(*) inp_pipe_valid_q[0] = sv2v_tmp_CFC25; + assign in_ready_o = inp_pipe_ready[0]; + genvar _gv_i_13; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + generate + for (_gv_i_13 = 0; _gv_i_13 < NUM_INP_REGS; _gv_i_13 = _gv_i_13 + 1) begin : gen_input_pipeline + localparam i = _gv_i_13; + wire reg_ena; + assign inp_pipe_ready[i] = inp_pipe_ready[i + 1] | ~inp_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_valid_q[i + 1] <= 1'b0; + else + inp_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (inp_pipe_ready[i] ? inp_pipe_valid_q[i] : inp_pipe_valid_q[i + 1])); + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:WIDTH * 2] <= 1'sb0; + else + inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:WIDTH * 2] <= (reg_ena ? inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2 : ((0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:WIDTH * 2] : inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2 : ((0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:WIDTH * 2]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2+:2] <= 1'sb0; + else + inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2+:2] <= (reg_ena ? inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 2+:2] : inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 2+:2]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= 3'b000; + else + inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3] <= (reg_ena ? inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * 3+:3] : inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * 3+:3]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= sv2v_cast_4CD2E(0); + else + inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] <= (reg_ena ? inp_pipe_op_q[(0 >= NUM_INP_REGS ? i : NUM_INP_REGS - i) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] : inp_pipe_op_q[(0 >= NUM_INP_REGS ? i + 1 : NUM_INP_REGS - (i + 1)) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_op_mod_q[i + 1] <= 1'sb0; + else + inp_pipe_op_mod_q[i + 1] <= (reg_ena ? inp_pipe_op_mod_q[i] : inp_pipe_op_mod_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_tag_q[i + 1] <= 1'b0; + else + inp_pipe_tag_q[i + 1] <= (reg_ena ? inp_pipe_tag_q[i] : inp_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_mask_q[i + 1] <= 1'sb0; + else + inp_pipe_mask_q[i + 1] <= (reg_ena ? inp_pipe_mask_q[i] : inp_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + inp_pipe_aux_q[i + 1] <= 1'b0; + else + inp_pipe_aux_q[i + 1] <= (reg_ena ? inp_pipe_aux_q[i] : inp_pipe_aux_q[i + 1]); + end + endgenerate + wire [15:0] info_q; + fpnew_classifier #( + .FpFormat(FpFormat), + .NumOperands(2) + ) i_class_a( + .operands_i(inp_pipe_operands_q[WIDTH * ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) + 1) : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2 : ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1)))+:WIDTH * 2]), + .is_boxed_i(inp_pipe_is_boxed_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2+:2]), + .info_o(info_q) + ); + wire [((1 + EXP_BITS) + MAN_BITS) - 1:0] operand_a; + wire [((1 + EXP_BITS) + MAN_BITS) - 1:0] operand_b; + wire [7:0] info_a; + wire [7:0] info_b; + assign operand_a = inp_pipe_operands_q[((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? (0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2 : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - (((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1))) * WIDTH+:WIDTH]; + assign operand_b = inp_pipe_operands_q[((0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1) >= (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) ? ((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) + 1 : (0 >= NUM_INP_REGS ? NUM_INP_REGS * 2 : 0) - ((((0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 2) + 1) - (0 >= NUM_INP_REGS ? ((1 - NUM_INP_REGS) * 2) + ((NUM_INP_REGS * 2) - 1) : ((NUM_INP_REGS + 1) * 2) - 1))) * WIDTH+:WIDTH]; + assign info_a = info_q[0+:8]; + assign info_b = info_q[8+:8]; + wire any_operand_inf; + wire any_operand_nan; + wire signalling_nan; + assign any_operand_inf = |{info_a[4], info_b[4]}; + assign any_operand_nan = |{info_a[3], info_b[3]}; + assign signalling_nan = |{info_a[2], info_b[2]}; + wire operands_equal; + wire operand_a_smaller; + assign operands_equal = (operand_a == operand_b) || (info_a[5] && info_b[5]); + assign operand_a_smaller = (operand_a < operand_b) ^ (operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] || operand_b[1 + (EXP_BITS + (MAN_BITS - 1))]); + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] sgnj_result; + wire [4:0] sgnj_status; + wire sgnj_extension_bit; + localparam [0:0] fpnew_pkg_DONT_CARE = 1'b1; + function automatic [EXP_BITS - 1:0] sv2v_cast_8D8F7; + input reg [EXP_BITS - 1:0] inp; + sv2v_cast_8D8F7 = inp; + endfunction + function automatic [MAN_BITS - 1:0] sv2v_cast_D5F4C; + input reg [MAN_BITS - 1:0] inp; + sv2v_cast_D5F4C = inp; + endfunction + function automatic [EXP_BITS - 1:0] sv2v_cast_51E93; + input reg [EXP_BITS - 1:0] inp; + sv2v_cast_51E93 = inp; + endfunction + always @(*) begin : sign_injections + reg sign_a; + reg sign_b; + if (_sv2v_0) + ; + sgnj_result = operand_a; + if (!info_a[0]) + sgnj_result = {1'b0, sv2v_cast_8D8F7(1'sb1), sv2v_cast_D5F4C(2 ** (MAN_BITS - 1))}; + sign_a = operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] & info_a[0]; + sign_b = operand_b[1 + (EXP_BITS + (MAN_BITS - 1))] & info_b[0]; + (* full_case, parallel_case *) + case (inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]) + 3'b000: sgnj_result[1 + (EXP_BITS + (MAN_BITS - 1))] = sign_b; + 3'b001: sgnj_result[1 + (EXP_BITS + (MAN_BITS - 1))] = ~sign_b; + 3'b010: sgnj_result[1 + (EXP_BITS + (MAN_BITS - 1))] = sign_a ^ sign_b; + 3'b011: sgnj_result = operand_a; + default: sgnj_result = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + endcase + end + assign sgnj_status = 1'sb0; + assign sgnj_extension_bit = (inp_pipe_op_mod_q[NUM_INP_REGS] ? sgnj_result[1 + (EXP_BITS + (MAN_BITS - 1))] : 1'b1); + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] minmax_result; + reg [4:0] minmax_status; + wire minmax_extension_bit; + always @(*) begin : min_max + if (_sv2v_0) + ; + minmax_status = 1'sb0; + minmax_status[4] = signalling_nan; + if (info_a[3] && info_b[3]) + minmax_result = {1'b0, sv2v_cast_8D8F7(1'sb1), sv2v_cast_D5F4C(2 ** (MAN_BITS - 1))}; + else if (info_a[3]) + minmax_result = operand_b; + else if (info_b[3]) + minmax_result = operand_a; + else + (* full_case, parallel_case *) + case (inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]) + 3'b000: minmax_result = (operand_a_smaller ? operand_a : operand_b); + 3'b001: minmax_result = (operand_a_smaller ? operand_b : operand_a); + default: minmax_result = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + endcase + end + assign minmax_extension_bit = 1'b1; + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] cmp_result; + reg [4:0] cmp_status; + wire cmp_extension_bit; + always @(*) begin : comparisons + if (_sv2v_0) + ; + cmp_result = 1'sb0; + cmp_status = 1'sb0; + if (signalling_nan) begin + cmp_status[4] = 1'b1; + cmp_result = (inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3] == 3'b010) && inp_pipe_op_mod_q[NUM_INP_REGS]; + end + else + (* full_case, parallel_case *) + case (inp_pipe_rnd_mode_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * 3+:3]) + 3'b000: + if (any_operand_nan) + cmp_status[4] = 1'b1; + else + cmp_result = (operand_a_smaller | operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + 3'b001: + if (any_operand_nan) + cmp_status[4] = 1'b1; + else + cmp_result = (operand_a_smaller & ~operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + 3'b010: + if (any_operand_nan) + cmp_result = inp_pipe_op_mod_q[NUM_INP_REGS]; + else + cmp_result = operands_equal ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + default: cmp_result = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + endcase + end + assign cmp_extension_bit = 1'b0; + wire [4:0] class_status; + wire class_extension_bit; + reg [9:0] class_mask_d; + always @(*) begin : classify + if (_sv2v_0) + ; + if (info_a[7]) + class_mask_d = (operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ? 10'b0000000010 : 10'b0001000000); + else if (info_a[6]) + class_mask_d = (operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ? 10'b0000000100 : 10'b0000100000); + else if (info_a[5]) + class_mask_d = (operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ? 10'b0000001000 : 10'b0000010000); + else if (info_a[4]) + class_mask_d = (operand_a[1 + (EXP_BITS + (MAN_BITS - 1))] ? 10'b0000000001 : 10'b0010000000); + else if (info_a[3]) + class_mask_d = (info_a[2] ? 10'b0100000000 : 10'b1000000000); + else + class_mask_d = 10'b1000000000; + end + assign class_status = 1'sb0; + assign class_extension_bit = 1'b0; + reg [((1 + EXP_BITS) + MAN_BITS) - 1:0] result_d; + reg [4:0] status_d; + reg extension_bit_d; + wire is_class_d; + always @(*) begin : select_result + if (_sv2v_0) + ; + (* full_case, parallel_case *) + case (inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS]) + sv2v_cast_4CD2E(6): begin + result_d = sgnj_result; + status_d = sgnj_status; + extension_bit_d = sgnj_extension_bit; + end + sv2v_cast_4CD2E(7): begin + result_d = minmax_result; + status_d = minmax_status; + extension_bit_d = minmax_extension_bit; + end + sv2v_cast_4CD2E(8): begin + result_d = cmp_result; + status_d = cmp_status; + extension_bit_d = cmp_extension_bit; + end + sv2v_cast_4CD2E(9): begin + result_d = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + status_d = class_status; + extension_bit_d = class_extension_bit; + end + default: begin + result_d = {fpnew_pkg_DONT_CARE, sv2v_cast_51E93(fpnew_pkg_DONT_CARE), sv2v_cast_D5F4C(fpnew_pkg_DONT_CARE)}; + status_d = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + extension_bit_d = fpnew_pkg_DONT_CARE; + end + endcase + end + assign is_class_d = inp_pipe_op_q[(0 >= NUM_INP_REGS ? NUM_INP_REGS : NUM_INP_REGS - NUM_INP_REGS) * fpnew_pkg_OP_BITS+:fpnew_pkg_OP_BITS] == sv2v_cast_4CD2E(9); + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * ((1 + EXP_BITS) + MAN_BITS)) + ((NUM_OUT_REGS * ((1 + EXP_BITS) + MAN_BITS)) - 1) : ((NUM_OUT_REGS + 1) * ((1 + EXP_BITS) + MAN_BITS)) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * ((1 + EXP_BITS) + MAN_BITS) : 0)] out_pipe_result_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * 5) + ((NUM_OUT_REGS * 5) - 1) : ((NUM_OUT_REGS + 1) * 5) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * 5 : 0)] out_pipe_status_q; + reg [0:NUM_OUT_REGS] out_pipe_extension_bit_q; + reg [(0 >= NUM_OUT_REGS ? ((1 - NUM_OUT_REGS) * 10) + ((NUM_OUT_REGS * 10) - 1) : ((NUM_OUT_REGS + 1) * 10) - 1):(0 >= NUM_OUT_REGS ? NUM_OUT_REGS * 10 : 0)] out_pipe_class_mask_q; + reg [0:NUM_OUT_REGS] out_pipe_is_class_q; + reg [0:NUM_OUT_REGS] out_pipe_tag_q; + reg [0:NUM_OUT_REGS] out_pipe_mask_q; + reg [0:NUM_OUT_REGS] out_pipe_aux_q; + reg [0:NUM_OUT_REGS] out_pipe_valid_q; + wire [0:NUM_OUT_REGS] out_pipe_ready; + wire [((1 + EXP_BITS) + MAN_BITS) * 1:1] sv2v_tmp_35063; + assign sv2v_tmp_35063 = result_d; + always @(*) out_pipe_result_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] = sv2v_tmp_35063; + wire [5:1] sv2v_tmp_036FC; + assign sv2v_tmp_036FC = status_d; + always @(*) out_pipe_status_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * 5+:5] = sv2v_tmp_036FC; + wire [1:1] sv2v_tmp_C9204; + assign sv2v_tmp_C9204 = extension_bit_d; + always @(*) out_pipe_extension_bit_q[0] = sv2v_tmp_C9204; + wire [10:1] sv2v_tmp_0A406; + assign sv2v_tmp_0A406 = class_mask_d; + always @(*) out_pipe_class_mask_q[(0 >= NUM_OUT_REGS ? 0 : NUM_OUT_REGS) * 10+:10] = sv2v_tmp_0A406; + wire [1:1] sv2v_tmp_C899A; + assign sv2v_tmp_C899A = is_class_d; + always @(*) out_pipe_is_class_q[0] = sv2v_tmp_C899A; + wire [1:1] sv2v_tmp_13053; + assign sv2v_tmp_13053 = inp_pipe_tag_q[NUM_INP_REGS]; + always @(*) out_pipe_tag_q[0] = sv2v_tmp_13053; + wire [1:1] sv2v_tmp_CF9A1; + assign sv2v_tmp_CF9A1 = inp_pipe_mask_q[NUM_INP_REGS]; + always @(*) out_pipe_mask_q[0] = sv2v_tmp_CF9A1; + wire [1:1] sv2v_tmp_571F3; + assign sv2v_tmp_571F3 = inp_pipe_aux_q[NUM_INP_REGS]; + always @(*) out_pipe_aux_q[0] = sv2v_tmp_571F3; + wire [1:1] sv2v_tmp_B2A17; + assign sv2v_tmp_B2A17 = inp_pipe_valid_q[NUM_INP_REGS]; + always @(*) out_pipe_valid_q[0] = sv2v_tmp_B2A17; + assign inp_pipe_ready[NUM_INP_REGS] = out_pipe_ready[0]; + genvar _gv_i_14; + generate + for (_gv_i_14 = 0; _gv_i_14 < NUM_OUT_REGS; _gv_i_14 = _gv_i_14 + 1) begin : gen_output_pipeline + localparam i = _gv_i_14; + wire reg_ena; + assign out_pipe_ready[i] = out_pipe_ready[i + 1] | ~out_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_valid_q[i + 1] <= 1'b0; + else + out_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (out_pipe_ready[i] ? out_pipe_valid_q[i] : out_pipe_valid_q[i + 1])); + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] <= 1'sb0; + else + out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] <= (reg_ena ? out_pipe_result_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS] : out_pipe_result_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= 1'sb0; + else + out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5] <= (reg_ena ? out_pipe_status_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * 5+:5] : out_pipe_status_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 5+:5]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_extension_bit_q[i + 1] <= 1'sb0; + else + out_pipe_extension_bit_q[i + 1] <= (reg_ena ? out_pipe_extension_bit_q[i] : out_pipe_extension_bit_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_class_mask_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 10+:10] <= 10'b1000000000; + else + out_pipe_class_mask_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 10+:10] <= (reg_ena ? out_pipe_class_mask_q[(0 >= NUM_OUT_REGS ? i : NUM_OUT_REGS - i) * 10+:10] : out_pipe_class_mask_q[(0 >= NUM_OUT_REGS ? i + 1 : NUM_OUT_REGS - (i + 1)) * 10+:10]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_is_class_q[i + 1] <= 1'sb0; + else + out_pipe_is_class_q[i + 1] <= (reg_ena ? out_pipe_is_class_q[i] : out_pipe_is_class_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_tag_q[i + 1] <= 1'b0; + else + out_pipe_tag_q[i + 1] <= (reg_ena ? out_pipe_tag_q[i] : out_pipe_tag_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_mask_q[i + 1] <= 1'sb0; + else + out_pipe_mask_q[i + 1] <= (reg_ena ? out_pipe_mask_q[i] : out_pipe_mask_q[i + 1]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + out_pipe_aux_q[i + 1] <= 1'b0; + else + out_pipe_aux_q[i + 1] <= (reg_ena ? out_pipe_aux_q[i] : out_pipe_aux_q[i + 1]); + end + endgenerate + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + assign result_o = out_pipe_result_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * ((1 + EXP_BITS) + MAN_BITS)+:(1 + EXP_BITS) + MAN_BITS]; + assign status_o = out_pipe_status_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * 5+:5]; + assign extension_bit_o = out_pipe_extension_bit_q[NUM_OUT_REGS]; + assign class_mask_o = out_pipe_class_mask_q[(0 >= NUM_OUT_REGS ? NUM_OUT_REGS : NUM_OUT_REGS - NUM_OUT_REGS) * 10+:10]; + assign is_class_o = out_pipe_is_class_q[NUM_OUT_REGS]; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = |{inp_pipe_valid_q, out_pipe_valid_q}; + generate + if (NUM_OUT_REGS > 0) begin : genblk3 + assign early_out_valid_o = |{out_pipe_valid_q[NUM_OUT_REGS] & ~out_pipe_ready[NUM_OUT_REGS], out_pipe_valid_q[NUM_OUT_REGS - 1]}; + end + else if (NUM_INP_REGS > 0) begin : genblk3 + assign early_out_valid_o = |{inp_pipe_valid_q[NUM_INP_REGS] & ~inp_pipe_ready[NUM_INP_REGS], inp_pipe_valid_q[NUM_INP_REGS - 1]}; + end + else begin : genblk3 + assign early_out_valid_o = 1'b0; + end + endgenerate + initial _sv2v_0 = 0; +endmodule +module fpnew_opgroup_block_37AAD ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + src_fmt_i, + dst_fmt_i, + int_fmt_i, + vectorial_op_i, + tag_i, + simd_mask_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + out_valid_o, + out_ready_i, + busy_o, + early_valid_o +); + reg _sv2v_0; + parameter [1:0] OpGroup = 2'd0; + parameter [31:0] Width = 32; + parameter [0:0] EnableVectors = 1'b1; + parameter [1:0] DivSqrtSel = 2'd2; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + parameter [0:4] FpFmtMask = 1'sb1; + localparam [31:0] fpnew_pkg_NUM_INT_FORMATS = 4; + parameter [0:3] IntFmtMask = 1'sb1; + parameter [159:0] FmtPipeRegs = {fpnew_pkg_NUM_FP_FORMATS {32'd0}}; + parameter [9:0] FmtUnitTypes = {fpnew_pkg_NUM_FP_FORMATS {2'd1}}; + parameter [1:0] PipeConfig = 2'd0; + parameter [31:0] TrueSIMDClass = 0; + localparam [31:0] NUM_FORMATS = fpnew_pkg_NUM_FP_FORMATS; + function automatic [31:0] fpnew_pkg_num_operands; + input reg [1:0] grp; + (* full_case, parallel_case *) + case (grp) + 2'd0: fpnew_pkg_num_operands = 3; + 2'd1: fpnew_pkg_num_operands = 2; + 2'd2: fpnew_pkg_num_operands = 2; + 2'd3: fpnew_pkg_num_operands = 3; + default: fpnew_pkg_num_operands = 0; + endcase + endfunction + localparam [31:0] NUM_OPERANDS = fpnew_pkg_num_operands(OpGroup); + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + function automatic signed [31:0] fpnew_pkg_maximum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_maximum = (a > b ? a : b); + endfunction + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + function automatic [31:0] fpnew_pkg_max_fp_width; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_1 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) + res = $unsigned(fpnew_pkg_maximum(res, fpnew_pkg_fp_width(sv2v_cast_5D882(i)))); + end + fpnew_pkg_max_fp_width = res; + end + endfunction + function automatic signed [31:0] fpnew_pkg_minimum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_minimum = (a < b ? a : b); + endfunction + function automatic [31:0] fpnew_pkg_max_num_lanes; + input reg [31:0] width; + input reg [0:4] cfg; + input reg vec; + if (vec) begin : sv2v_autoblock_2 + reg [31:0] res; + res = fpnew_pkg_max_fp_width(cfg); + begin : sv2v_autoblock_3 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) begin : sv2v_autoblock_4 + reg [31:0] format_width; + format_width = (fpnew_pkg_FP_ENCODINGS[((4 - i) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - i) * 64) + 31-:32]) + 1; + res = $unsigned(fpnew_pkg_minimum(res, format_width)); + end + end + fpnew_pkg_max_num_lanes = width / res; + end + else + fpnew_pkg_max_num_lanes = 1; + endfunction + localparam [31:0] NUM_LANES = fpnew_pkg_max_num_lanes(Width, FpFmtMask, EnableVectors); + input wire clk_i; + input wire rst_ni; + input wire [(NUM_OPERANDS * Width) - 1:0] operands_i; + input wire [(NUM_FORMATS * NUM_OPERANDS) - 1:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire [2:0] src_fmt_i; + input wire [2:0] dst_fmt_i; + localparam [31:0] fpnew_pkg_INT_FORMAT_BITS = 2; + input wire [1:0] int_fmt_i; + input wire vectorial_op_i; + input wire tag_i; + input wire [NUM_LANES - 1:0] simd_mask_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [Width - 1:0] result_o; + output wire [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + output wire early_valid_o; + wire [4:0] fmt_in_ready; + wire [4:0] fmt_out_valid; + wire [4:0] fmt_out_ready; + wire [4:0] fmt_busy; + wire [4:0] early_valid; + wire [((Width + 6) >= 0 ? (5 * (Width + 7)) - 1 : (5 * (1 - (Width + 6))) + (Width + 5)):((Width + 6) >= 0 ? 0 : Width + 6)] fmt_outputs; + assign in_ready_o = in_valid_i & fmt_in_ready[dst_fmt_i]; + genvar _gv_fmt_9; + localparam [0:0] fpnew_pkg_DONT_CARE = 1'b1; + function automatic fpnew_pkg_any_enabled_multi; + input reg [9:0] types; + input reg [0:4] cfg; + reg [0:1] _sv2v_jump; + begin + _sv2v_jump = 2'b00; + begin : sv2v_autoblock_5 + reg [31:0] i; + begin : sv2v_autoblock_6 + reg [31:0] _sv2v_value_on_break; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (_sv2v_jump < 2'b10) begin + _sv2v_jump = 2'b00; + if (cfg[i] && (types[(4 - i) * 2+:2] == 2'd2)) begin + fpnew_pkg_any_enabled_multi = 1'b1; + _sv2v_jump = 2'b11; + end + _sv2v_value_on_break = i; + end + if (!(_sv2v_jump < 2'b10)) + i = _sv2v_value_on_break; + if (_sv2v_jump != 2'b11) + _sv2v_jump = 2'b00; + end + end + if (_sv2v_jump == 2'b00) begin + fpnew_pkg_any_enabled_multi = 1'b0; + _sv2v_jump = 2'b11; + end + end + endfunction + function automatic [2:0] fpnew_pkg_get_first_enabled_multi; + input reg [9:0] types; + input reg [0:4] cfg; + reg [0:1] _sv2v_jump; + begin + _sv2v_jump = 2'b00; + begin : sv2v_autoblock_7 + reg [31:0] i; + begin : sv2v_autoblock_8 + reg [31:0] _sv2v_value_on_break; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (_sv2v_jump < 2'b10) begin + _sv2v_jump = 2'b00; + if (cfg[i] && (types[(4 - i) * 2+:2] == 2'd2)) begin + fpnew_pkg_get_first_enabled_multi = sv2v_cast_5D882(i); + _sv2v_jump = 2'b11; + end + _sv2v_value_on_break = i; + end + if (!(_sv2v_jump < 2'b10)) + i = _sv2v_value_on_break; + if (_sv2v_jump != 2'b11) + _sv2v_jump = 2'b00; + end + end + if (_sv2v_jump == 2'b00) begin + fpnew_pkg_get_first_enabled_multi = sv2v_cast_5D882(0); + _sv2v_jump = 2'b11; + end + end + endfunction + function automatic fpnew_pkg_is_first_enabled_multi; + input reg [2:0] fmt; + input reg [9:0] types; + input reg [0:4] cfg; + reg [0:1] _sv2v_jump; + begin + _sv2v_jump = 2'b00; + begin : sv2v_autoblock_9 + reg [31:0] i; + begin : sv2v_autoblock_10 + reg [31:0] _sv2v_value_on_break; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (_sv2v_jump < 2'b10) begin + _sv2v_jump = 2'b00; + if (cfg[i] && (types[(4 - i) * 2+:2] == 2'd2)) begin + fpnew_pkg_is_first_enabled_multi = sv2v_cast_5D882(i) == fmt; + _sv2v_jump = 2'b11; + end + _sv2v_value_on_break = i; + end + if (!(_sv2v_jump < 2'b10)) + i = _sv2v_value_on_break; + if (_sv2v_jump != 2'b11) + _sv2v_jump = 2'b00; + end + end + if (_sv2v_jump == 2'b00) begin + fpnew_pkg_is_first_enabled_multi = 1'b0; + _sv2v_jump = 2'b11; + end + end + endfunction + function automatic [31:0] fpnew_pkg_num_lanes; + input reg [31:0] width; + input reg [2:0] fmt; + input reg vec; + fpnew_pkg_num_lanes = (vec ? width / fpnew_pkg_fp_width(fmt) : 1); + endfunction + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + generate + for (_gv_fmt_9 = 0; _gv_fmt_9 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_9 = _gv_fmt_9 + 1) begin : gen_parallel_slices + localparam fmt = _gv_fmt_9; + localparam [0:0] ANY_MERGED = fpnew_pkg_any_enabled_multi(FmtUnitTypes, FpFmtMask); + localparam [0:0] IS_FIRST_MERGED = fpnew_pkg_is_first_enabled_multi(sv2v_cast_5D882(fmt), FmtUnitTypes, FpFmtMask); + if (FpFmtMask[fmt] && (FmtUnitTypes[(4 - fmt) * 2+:2] == 2'd1)) begin : active_format + localparam [2:0] FpFormat = sv2v_cast_5D882(fmt); + wire in_valid; + assign in_valid = in_valid_i & (dst_fmt_i == fmt); + localparam [31:0] INTERNAL_LANES = fpnew_pkg_num_lanes(Width, sv2v_cast_5D882(fmt), EnableVectors); + reg [INTERNAL_LANES - 1:0] mask_slice; + always @(*) begin : sv2v_autoblock_11 + reg signed [31:0] b; + if (_sv2v_0) + ; + for (b = 0; b < INTERNAL_LANES; b = b + 1) + mask_slice[b] = simd_mask_i[(NUM_LANES / INTERNAL_LANES) * b]; + end + localparam [31:0] sv2v_uu_i_fmt_slice_NumPipeRegs = FmtPipeRegs[(4 - fmt) * 32+:32]; + localparam [31:0] sv2v_uu_i_fmt_slice_ExtRegEnaWidth = (sv2v_uu_i_fmt_slice_NumPipeRegs == 0 ? 1 : sv2v_uu_i_fmt_slice_NumPipeRegs); + localparam [sv2v_cast_32((sv2v_cast_32(FmtPipeRegs[(4 - _gv_fmt_9) * 32+:32]) == 0 ? 1 : sv2v_cast_32(FmtPipeRegs[(4 - _gv_fmt_9) * 32+:32]))) - 1:0] sv2v_uu_i_fmt_slice_ext_reg_ena_i_0 = 1'sb0; + fpnew_opgroup_fmt_slice_07650 #( + .OpGroup(OpGroup), + .FpFormat(FpFormat), + .Width(Width), + .EnableVectors(EnableVectors), + .NumPipeRegs(FmtPipeRegs[(4 - fmt) * 32+:32]), + .PipeConfig(PipeConfig), + .TrueSIMDClass(TrueSIMDClass) + ) i_fmt_slice( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(operands_i), + .is_boxed_i(is_boxed_i[fmt * NUM_OPERANDS+:NUM_OPERANDS]), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .vectorial_op_i(vectorial_op_i), + .tag_i(tag_i), + .simd_mask_i(mask_slice), + .in_valid_i(in_valid), + .in_ready_o(fmt_in_ready[fmt]), + .flush_i(flush_i), + .result_o(fmt_outputs[((Width + 6) >= 0 ? (fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6)) : (((fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6))) + ((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))) - 1)-:((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))]), + .status_o(fmt_outputs[((Width + 6) >= 0 ? (fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0) : ((fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0)) + 4)-:5]), + .extension_bit_o(fmt_outputs[(fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 1 : Width + 5)]), + .tag_o(fmt_outputs[(fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 0 : Width + 6)]), + .out_valid_o(fmt_out_valid[fmt]), + .out_ready_i(fmt_out_ready[fmt]), + .busy_o(fmt_busy[fmt]), + .reg_ena_i(sv2v_uu_i_fmt_slice_ext_reg_ena_i_0), + .early_out_valid_o(early_valid[fmt]) + ); + end + else if ((FpFmtMask[fmt] && ANY_MERGED) && !IS_FIRST_MERGED) begin : merged_unused + localparam FMT = fpnew_pkg_get_first_enabled_multi(FmtUnitTypes, FpFmtMask); + assign fmt_in_ready[fmt] = fmt_in_ready[sv2v_cast_32_signed(FMT)]; + assign fmt_out_valid[fmt] = 1'b0; + assign fmt_busy[fmt] = 1'b0; + assign fmt_outputs[((Width + 6) >= 0 ? (fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6)) : (((fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6))) + ((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))) - 1)-:((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))] = {Width {fpnew_pkg_DONT_CARE}}; + assign fmt_outputs[((Width + 6) >= 0 ? (fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0) : ((fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0)) + 4)-:5] = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + assign fmt_outputs[(fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 1 : Width + 5)] = fpnew_pkg_DONT_CARE; + assign fmt_outputs[(fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 0 : Width + 6)] = fpnew_pkg_DONT_CARE; + assign early_valid[fmt] = 1'b0; + end + else if (!FpFmtMask[fmt] || (FmtUnitTypes[(4 - fmt) * 2+:2] == 2'd0)) begin : disable_fmt + assign fmt_in_ready[fmt] = 1'b0; + assign fmt_out_valid[fmt] = 1'b0; + assign fmt_busy[fmt] = 1'b0; + assign fmt_outputs[((Width + 6) >= 0 ? (fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6)) : (((fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6))) + ((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))) - 1)-:((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))] = {Width {fpnew_pkg_DONT_CARE}}; + assign fmt_outputs[((Width + 6) >= 0 ? (fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0) : ((fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0)) + 4)-:5] = {fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE, fpnew_pkg_DONT_CARE}; + assign fmt_outputs[(fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 1 : Width + 5)] = fpnew_pkg_DONT_CARE; + assign fmt_outputs[(fmt * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 0 : Width + 6)] = fpnew_pkg_DONT_CARE; + assign early_valid[fmt] = 1'b0; + end + end + endgenerate + function automatic [31:0] fpnew_pkg_get_num_regs_multi; + input reg [159:0] regs; + input reg [9:0] types; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_12 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i] && (types[(4 - i) * 2+:2] == 2'd2)) + res = fpnew_pkg_maximum(res, regs[(4 - i) * 32+:32]); + end + fpnew_pkg_get_num_regs_multi = res; + end + endfunction + generate + if (fpnew_pkg_any_enabled_multi(FmtUnitTypes, FpFmtMask)) begin : gen_merged_slice + localparam FMT = fpnew_pkg_get_first_enabled_multi(FmtUnitTypes, FpFmtMask); + localparam REG = fpnew_pkg_get_num_regs_multi(FmtPipeRegs, FmtUnitTypes, FpFmtMask); + wire in_valid; + assign in_valid = in_valid_i & (FmtUnitTypes[(4 - dst_fmt_i) * 2+:2] == 2'd2); + localparam [31:0] sv2v_uu_i_multifmt_slice_NumPipeRegs = REG; + localparam [31:0] sv2v_uu_i_multifmt_slice_ExtRegEnaWidth = (sv2v_uu_i_multifmt_slice_NumPipeRegs == 0 ? 1 : sv2v_uu_i_multifmt_slice_NumPipeRegs); + localparam [sv2v_uu_i_multifmt_slice_ExtRegEnaWidth - 1:0] sv2v_uu_i_multifmt_slice_ext_reg_ena_i_0 = 1'sb0; + fpnew_opgroup_multifmt_slice_23084 #( + .OpGroup(OpGroup), + .Width(Width), + .FpFmtConfig(FpFmtMask), + .IntFmtConfig(IntFmtMask), + .EnableVectors(EnableVectors), + .DivSqrtSel(DivSqrtSel), + .NumPipeRegs(REG), + .PipeConfig(PipeConfig) + ) i_multifmt_slice( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(operands_i), + .is_boxed_i(is_boxed_i), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .src_fmt_i(src_fmt_i), + .dst_fmt_i(dst_fmt_i), + .int_fmt_i(int_fmt_i), + .vectorial_op_i(vectorial_op_i), + .tag_i(tag_i), + .simd_mask_i(simd_mask_i), + .in_valid_i(in_valid), + .in_ready_o(fmt_in_ready[FMT]), + .flush_i(flush_i), + .result_o(fmt_outputs[((Width + 6) >= 0 ? (FMT * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6)) : (((FMT * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? Width + 6 : (Width + 6) - (Width + 6))) + ((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))) - 1)-:((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))]), + .status_o(fmt_outputs[((Width + 6) >= 0 ? (FMT * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0) : ((FMT * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 6 : Width + 0)) + 4)-:5]), + .extension_bit_o(fmt_outputs[(FMT * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 1 : Width + 5)]), + .tag_o(fmt_outputs[(FMT * ((Width + 6) >= 0 ? Width + 7 : 1 - (Width + 6))) + ((Width + 6) >= 0 ? 0 : Width + 6)]), + .out_valid_o(fmt_out_valid[FMT]), + .out_ready_i(fmt_out_ready[FMT]), + .busy_o(fmt_busy[FMT]), + .reg_ena_i(sv2v_uu_i_multifmt_slice_ext_reg_ena_i_0), + .early_out_valid_o(early_valid[FMT]) + ); + end + endgenerate + wire [Width + 6:0] arbiter_output; + localparam [31:0] sv2v_uu_i_arbiter_NumIn = NUM_FORMATS; + localparam [31:0] sv2v_uu_i_arbiter_IdxWidth = $unsigned(3); + localparam [sv2v_uu_i_arbiter_IdxWidth - 1:0] sv2v_uu_i_arbiter_ext_rr_i_0 = 1'sb0; + rr_arb_tree_3ECCC_C4496 #( + .DataType_Width(Width), + .NumIn(NUM_FORMATS), + .AxiVldRdy(1'b1) + ) i_arbiter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(flush_i), + .rr_i(sv2v_uu_i_arbiter_ext_rr_i_0), + .req_i(fmt_out_valid), + .gnt_o(fmt_out_ready), + .data_i(fmt_outputs), + .gnt_i(out_ready_i), + .req_o(out_valid_o), + .data_o(arbiter_output), + .idx_o() + ); + assign result_o = arbiter_output[Width + 6-:((Width + 6) >= 7 ? Width + 0 : 8 - (Width + 6))]; + assign status_o = arbiter_output[6-:5]; + assign extension_bit_o = arbiter_output[1]; + assign tag_o = arbiter_output[0]; + assign early_valid_o = |early_valid; + assign busy_o = |fmt_busy; + initial _sv2v_0 = 0; +endmodule +module fpnew_opgroup_fmt_slice_07650 ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + vectorial_op_i, + tag_i, + simd_mask_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + reg _sv2v_0; + parameter [1:0] OpGroup = 2'd0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + parameter [2:0] FpFormat = sv2v_cast_5D882(0); + parameter [31:0] Width = 32; + parameter [0:0] EnableVectors = 1'b1; + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + parameter [0:0] ExtRegEna = 1'b0; + parameter [31:0] TrueSIMDClass = 0; + function automatic [31:0] fpnew_pkg_num_operands; + input reg [1:0] grp; + (* full_case, parallel_case *) + case (grp) + 2'd0: fpnew_pkg_num_operands = 3; + 2'd1: fpnew_pkg_num_operands = 2; + 2'd2: fpnew_pkg_num_operands = 2; + 2'd3: fpnew_pkg_num_operands = 3; + default: fpnew_pkg_num_operands = 0; + endcase + endfunction + localparam [31:0] NUM_OPERANDS = fpnew_pkg_num_operands(OpGroup); + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + function automatic [31:0] fpnew_pkg_num_lanes; + input reg [31:0] width; + input reg [2:0] fmt; + input reg vec; + fpnew_pkg_num_lanes = (vec ? width / fpnew_pkg_fp_width(fmt) : 1); + endfunction + localparam [31:0] NUM_LANES = fpnew_pkg_num_lanes(Width, FpFormat, EnableVectors); + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [(NUM_OPERANDS * Width) - 1:0] operands_i; + input wire [NUM_OPERANDS - 1:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire vectorial_op_i; + input wire tag_i; + input wire [NUM_LANES - 1:0] simd_mask_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [Width - 1:0] result_o; + output reg [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(FpFormat); + localparam [31:0] SIMD_WIDTH = $unsigned(Width / NUM_LANES); + wire [NUM_LANES - 1:0] lane_in_ready; + wire [NUM_LANES - 1:0] lane_out_valid; + wire vectorial_op; + wire [(NUM_LANES * FP_WIDTH) - 1:0] slice_result; + wire [Width - 1:0] slice_regular_result; + wire [Width - 1:0] slice_class_result; + wire [Width - 1:0] slice_vec_class_result; + wire [(NUM_LANES * 5) - 1:0] lane_status; + wire [NUM_LANES - 1:0] lane_ext_bit; + wire [(NUM_LANES * 10) - 1:0] lane_class_mask; + wire [NUM_LANES - 1:0] lane_tags; + wire [NUM_LANES - 1:0] lane_masks; + wire [NUM_LANES - 1:0] lane_vectorial; + wire [NUM_LANES - 1:0] lane_busy; + wire [NUM_LANES - 1:0] lane_is_class; + wire [NUM_LANES - 1:0] lane_early_out_valid; + wire result_is_vector; + wire result_is_class; + assign in_ready_o = lane_in_ready[0]; + assign vectorial_op = vectorial_op_i & EnableVectors; + genvar _gv_lane_1; + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + generate + for (_gv_lane_1 = 0; _gv_lane_1 < sv2v_cast_32_signed(NUM_LANES); _gv_lane_1 = _gv_lane_1 + 1) begin : gen_num_lanes + localparam lane = _gv_lane_1; + wire [FP_WIDTH - 1:0] local_result; + wire local_sign; + if ((lane == 0) || EnableVectors) begin : active_lane + wire in_valid; + wire out_valid; + wire out_ready; + reg [(NUM_OPERANDS * FP_WIDTH) - 1:0] local_operands; + wire [FP_WIDTH - 1:0] op_result; + wire [4:0] op_status; + assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); + always @(*) begin : prepare_input + if (_sv2v_0) + ; + begin : sv2v_autoblock_1 + reg signed [31:0] i; + for (i = 0; i < sv2v_cast_32_signed(NUM_OPERANDS); i = i + 1) + local_operands[i * FP_WIDTH+:FP_WIDTH] = operands_i[(i * Width) + (((($unsigned(lane) + 1) * FP_WIDTH) - 1) >= ($unsigned(lane) * FP_WIDTH) ? (($unsigned(lane) + 1) * FP_WIDTH) - 1 : (((($unsigned(lane) + 1) * FP_WIDTH) - 1) + (((($unsigned(lane) + 1) * FP_WIDTH) - 1) >= ($unsigned(lane) * FP_WIDTH) ? (((($unsigned(lane) + 1) * FP_WIDTH) - 1) - ($unsigned(lane) * FP_WIDTH)) + 1 : (($unsigned(lane) * FP_WIDTH) - ((($unsigned(lane) + 1) * FP_WIDTH) - 1)) + 1)) - 1)-:(((($unsigned(lane) + 1) * FP_WIDTH) - 1) >= ($unsigned(lane) * FP_WIDTH) ? (((($unsigned(lane) + 1) * FP_WIDTH) - 1) - ($unsigned(lane) * FP_WIDTH)) + 1 : (($unsigned(lane) * FP_WIDTH) - ((($unsigned(lane) + 1) * FP_WIDTH) - 1)) + 1)]; + end + end + if (OpGroup == 2'd0) begin : lane_instance + fpnew_fma_EA93F #( + .FpFormat(FpFormat), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_fma( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands), + .is_boxed_i(is_boxed_i[NUM_OPERANDS - 1:0]), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(vectorial_op), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_vectorial[lane]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + assign lane_is_class[lane] = 1'b0; + assign lane_class_mask[lane * 10+:10] = 10'b0000000001; + end + else if (OpGroup == 2'd1) begin + ; + end + else if (OpGroup == 2'd2) begin : lane_instance + fpnew_noncomp_DE16F #( + .FpFormat(FpFormat), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_noncomp( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands), + .is_boxed_i(is_boxed_i[NUM_OPERANDS - 1:0]), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(vectorial_op), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .class_mask_o(lane_class_mask[lane * 10+:10]), + .is_class_o(lane_is_class[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_vectorial[lane]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + end + assign out_ready = out_ready_i & ((lane == 0) | result_is_vector); + assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector); + assign local_result = (lane_out_valid[lane] | ExtRegEna ? op_result : {FP_WIDTH {lane_ext_bit[0]}}); + assign lane_status[lane * 5+:5] = (lane_out_valid[lane] | ExtRegEna ? op_status : {5 {1'sb0}}); + end + else begin : genblk1 + assign lane_out_valid[lane] = 1'b0; + assign lane_in_ready[lane] = 1'b0; + assign local_result = {FP_WIDTH {lane_ext_bit[0]}}; + assign lane_status[lane * 5+:5] = 1'sb0; + assign lane_busy[lane] = 1'b0; + assign lane_is_class[lane] = 1'b0; + end + assign slice_result[(($unsigned(lane) + 1) * FP_WIDTH) - 1:$unsigned(lane) * FP_WIDTH] = local_result; + if (TrueSIMDClass && (SIMD_WIDTH >= 10)) begin : vectorial_true_class + assign slice_vec_class_result[lane * SIMD_WIDTH+:10] = lane_class_mask[lane * 10+:10]; + assign slice_vec_class_result[((lane + 1) * SIMD_WIDTH) - 1-:SIMD_WIDTH - 10] = 1'sb0; + end + else if (((lane + 1) * 8) <= Width) begin : vectorial_class + assign local_sign = (((lane_class_mask[lane * 10+:10] == 10'b0000000001) || (lane_class_mask[lane * 10+:10] == 10'b0000000010)) || (lane_class_mask[lane * 10+:10] == 10'b0000000100)) || (lane_class_mask[lane * 10+:10] == 10'b0000001000); + assign slice_vec_class_result[((lane + 1) * 8) - 1:lane * 8] = {local_sign, ~local_sign, lane_class_mask[lane * 10+:10] == 10'b1000000000, lane_class_mask[lane * 10+:10] == 10'b0100000000, (lane_class_mask[lane * 10+:10] == 10'b0000010000) || (lane_class_mask[lane * 10+:10] == 10'b0000001000), (lane_class_mask[lane * 10+:10] == 10'b0000100000) || (lane_class_mask[lane * 10+:10] == 10'b0000000100), (lane_class_mask[lane * 10+:10] == 10'b0001000000) || (lane_class_mask[lane * 10+:10] == 10'b0000000010), (lane_class_mask[lane * 10+:10] == 10'b0010000000) || (lane_class_mask[lane * 10+:10] == 10'b0000000001)}; + end + end + endgenerate + assign result_is_vector = lane_vectorial[0]; + assign result_is_class = lane_is_class[0]; + assign slice_regular_result = $signed({extension_bit_o, slice_result}); + localparam [31:0] CLASS_VEC_BITS = ((NUM_LANES * 8) > Width ? 8 * (Width / 8) : NUM_LANES * 8); + generate + if (!(TrueSIMDClass && (SIMD_WIDTH >= 10))) begin : genblk2 + if (CLASS_VEC_BITS < Width) begin : pad_vectorial_class + assign slice_vec_class_result[Width - 1:CLASS_VEC_BITS] = 1'sb0; + end + end + endgenerate + assign slice_class_result = (result_is_vector ? slice_vec_class_result : lane_class_mask[0+:10]); + assign result_o = (result_is_class ? slice_class_result : slice_regular_result); + assign extension_bit_o = lane_ext_bit[0]; + assign tag_o = lane_tags[0]; + assign busy_o = |lane_busy; + assign out_valid_o = lane_out_valid[0]; + assign early_out_valid_o = |lane_early_out_valid; + always @(*) begin : output_processing + reg [4:0] temp_status; + if (_sv2v_0) + ; + temp_status = 1'sb0; + begin : sv2v_autoblock_2 + reg signed [31:0] i; + for (i = 0; i < sv2v_cast_32_signed(NUM_LANES); i = i + 1) + temp_status = temp_status | (lane_status[i * 5+:5] & {5 {lane_masks[i]}}); + end + status_o = temp_status; + end + initial _sv2v_0 = 0; +endmodule +module fpnew_opgroup_multifmt_slice_23084 ( + clk_i, + rst_ni, + operands_i, + is_boxed_i, + rnd_mode_i, + op_i, + op_mod_i, + src_fmt_i, + dst_fmt_i, + int_fmt_i, + vectorial_op_i, + tag_i, + simd_mask_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + extension_bit_o, + tag_o, + out_valid_o, + out_ready_i, + busy_o, + reg_ena_i, + early_out_valid_o +); + reg _sv2v_0; + parameter [1:0] OpGroup = 2'd3; + parameter [31:0] Width = 64; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + parameter [0:4] FpFmtConfig = 1'sb1; + localparam [31:0] fpnew_pkg_NUM_INT_FORMATS = 4; + parameter [0:3] IntFmtConfig = 1'sb1; + parameter [0:0] EnableVectors = 1'b1; + parameter [1:0] DivSqrtSel = 2'd2; + parameter [31:0] NumPipeRegs = 0; + parameter [1:0] PipeConfig = 2'd0; + parameter [0:0] ExtRegEna = 1'b0; + function automatic [31:0] fpnew_pkg_num_operands; + input reg [1:0] grp; + (* full_case, parallel_case *) + case (grp) + 2'd0: fpnew_pkg_num_operands = 3; + 2'd1: fpnew_pkg_num_operands = 2; + 2'd2: fpnew_pkg_num_operands = 2; + 2'd3: fpnew_pkg_num_operands = 3; + default: fpnew_pkg_num_operands = 0; + endcase + endfunction + localparam [31:0] NUM_OPERANDS = fpnew_pkg_num_operands(OpGroup); + localparam [31:0] NUM_FORMATS = fpnew_pkg_NUM_FP_FORMATS; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + function automatic signed [31:0] fpnew_pkg_maximum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_maximum = (a > b ? a : b); + endfunction + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + function automatic [31:0] fpnew_pkg_max_fp_width; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_1 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) + res = $unsigned(fpnew_pkg_maximum(res, fpnew_pkg_fp_width(sv2v_cast_5D882(i)))); + end + fpnew_pkg_max_fp_width = res; + end + endfunction + function automatic signed [31:0] fpnew_pkg_minimum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_minimum = (a < b ? a : b); + endfunction + function automatic [31:0] fpnew_pkg_max_num_lanes; + input reg [31:0] width; + input reg [0:4] cfg; + input reg vec; + if (vec) begin : sv2v_autoblock_2 + reg [31:0] res; + res = fpnew_pkg_max_fp_width(cfg); + begin : sv2v_autoblock_3 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) begin : sv2v_autoblock_4 + reg [31:0] format_width; + format_width = (fpnew_pkg_FP_ENCODINGS[((4 - i) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - i) * 64) + 31-:32]) + 1; + res = $unsigned(fpnew_pkg_minimum(res, format_width)); + end + end + fpnew_pkg_max_num_lanes = width / res; + end + else + fpnew_pkg_max_num_lanes = 1; + endfunction + localparam [31:0] NUM_SIMD_LANES = fpnew_pkg_max_num_lanes(Width, FpFmtConfig, EnableVectors); + localparam [31:0] ExtRegEnaWidth = (NumPipeRegs == 0 ? 1 : NumPipeRegs); + input wire clk_i; + input wire rst_ni; + input wire [(NUM_OPERANDS * Width) - 1:0] operands_i; + input wire [(NUM_FORMATS * NUM_OPERANDS) - 1:0] is_boxed_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire [2:0] src_fmt_i; + input wire [2:0] dst_fmt_i; + localparam [31:0] fpnew_pkg_INT_FORMAT_BITS = 2; + input wire [1:0] int_fmt_i; + input wire vectorial_op_i; + input wire tag_i; + input wire [NUM_SIMD_LANES - 1:0] simd_mask_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [Width - 1:0] result_o; + output reg [4:0] status_o; + output wire extension_bit_o; + output wire tag_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + input wire [ExtRegEnaWidth - 1:0] reg_ena_i; + output wire early_out_valid_o; + generate + if (OpGroup == 2'd1) begin : genblk1 + if ((DivSqrtSel == 2'd1) && !((FpFmtConfig[0] == 1) && (FpFmtConfig[1:4] == {4 {1'sb0}}))) begin : genblk1 + initial begin + end + end + else if ((DivSqrtSel == 2'd2) && (FpFmtConfig[3] == 1'b1)) begin : genblk1 + initial $display("Warning [elaboration] /OpenROAD-flow-scripts/HighTide/designs/src/coralnpu/dev/repo/bazel-bin/hdl/chisel/src/coralnpu/CoreMiniAxi.sv:31271:7 - fpnew_opgroup_multifmt_slice.genblk1.genblk1\n msg: ", "The DivSqrt unit of C910 (instantiated by DivSqrtSel = THMULTI) does not support FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8."); + end + end + endgenerate + localparam [31:0] MAX_FP_WIDTH = fpnew_pkg_max_fp_width(FpFmtConfig); + function automatic [1:0] sv2v_cast_CDB06; + input reg [1:0] inp; + sv2v_cast_CDB06 = inp; + endfunction + function automatic [31:0] fpnew_pkg_int_width; + input reg [1:0] ifmt; + (* full_case, parallel_case *) + case (ifmt) + sv2v_cast_CDB06(0): fpnew_pkg_int_width = 8; + sv2v_cast_CDB06(1): fpnew_pkg_int_width = 16; + sv2v_cast_CDB06(2): fpnew_pkg_int_width = 32; + sv2v_cast_CDB06(3): fpnew_pkg_int_width = 64; + default: begin + fpnew_pkg_int_width = sv2v_cast_CDB06(0); + end + endcase + endfunction + function automatic [31:0] fpnew_pkg_max_int_width; + input reg [0:3] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_5 + reg signed [31:0] ifmt; + for (ifmt = 0; ifmt < fpnew_pkg_NUM_INT_FORMATS; ifmt = ifmt + 1) + if (cfg[ifmt]) + res = fpnew_pkg_maximum(res, fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt))); + end + fpnew_pkg_max_int_width = res; + end + endfunction + localparam [31:0] MAX_INT_WIDTH = fpnew_pkg_max_int_width(IntFmtConfig); + localparam [31:0] NUM_LANES = fpnew_pkg_max_num_lanes(Width, FpFmtConfig, 1'b1); + function automatic [31:0] fpnew_pkg_min_fp_width; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = fpnew_pkg_max_fp_width(cfg); + begin : sv2v_autoblock_6 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) + res = $unsigned(fpnew_pkg_minimum(res, fpnew_pkg_fp_width(sv2v_cast_5D882(i)))); + end + fpnew_pkg_min_fp_width = res; + end + endfunction + function automatic [31:0] fpnew_pkg_num_divsqrt_lanes; + input reg [31:0] width; + input reg [0:4] cfg; + input reg vec; + input reg [1:0] DivSqrtSel; + reg [0:4] cfg_tmp; + begin + cfg_tmp = (DivSqrtSel == 2'd2 ? cfg & 5'b11101 : cfg); + fpnew_pkg_num_divsqrt_lanes = (vec ? width / fpnew_pkg_min_fp_width(cfg_tmp) : 1); + end + endfunction + localparam [31:0] NUM_DIVSQRT_LANES = fpnew_pkg_num_divsqrt_lanes(Width, FpFmtConfig, 1'b1, DivSqrtSel); + localparam [31:0] NUM_INT_FORMATS = fpnew_pkg_NUM_INT_FORMATS; + localparam [31:0] FMT_BITS = fpnew_pkg_maximum(3, 2); + localparam [31:0] AUX_BITS = FMT_BITS + 2; + wire [NUM_LANES - 1:0] lane_in_ready; + wire [NUM_LANES - 1:0] lane_out_valid; + wire [NUM_LANES - 1:0] divsqrt_done; + wire [NUM_LANES - 1:0] divsqrt_ready; + wire vectorial_op; + wire [FMT_BITS - 1:0] dst_fmt; + wire [AUX_BITS - 1:0] aux_data; + wire dst_fmt_is_int; + wire dst_is_cpk; + wire [1:0] dst_vec_op; + wire [2:0] target_aux_d; + wire is_up_cast; + wire is_down_cast; + wire [(NUM_FORMATS * Width) - 1:0] fmt_slice_result; + wire [(NUM_INT_FORMATS * Width) - 1:0] ifmt_slice_result; + wire [Width - 1:0] conv_target_d; + wire [Width - 1:0] conv_target_q; + wire [(NUM_LANES * 5) - 1:0] lane_status; + wire [NUM_LANES - 1:0] lane_ext_bit; + wire [NUM_LANES - 1:0] lane_tags; + wire [NUM_LANES - 1:0] lane_masks; + wire [(NUM_LANES * AUX_BITS) - 1:0] lane_aux; + wire [NUM_LANES - 1:0] lane_busy; + wire [NUM_LANES - 1:0] lane_early_out_valid; + wire result_is_vector; + wire [FMT_BITS - 1:0] result_fmt; + wire result_fmt_is_int; + wire result_is_cpk; + wire [1:0] result_vec_op; + wire simd_synch_rdy; + wire simd_synch_done; + assign in_ready_o = lane_in_ready[0]; + assign vectorial_op = vectorial_op_i & EnableVectors; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + assign dst_fmt_is_int = (OpGroup == 2'd3) & (op_i == sv2v_cast_4CD2E(11)); + assign dst_is_cpk = (OpGroup == 2'd3) & ((op_i == sv2v_cast_4CD2E(13)) || (op_i == sv2v_cast_4CD2E(14))); + assign dst_vec_op = (OpGroup == 2'd3) & {op_i == sv2v_cast_4CD2E(14), op_mod_i}; + assign is_up_cast = fpnew_pkg_fp_width(dst_fmt_i) > fpnew_pkg_fp_width(src_fmt_i); + assign is_down_cast = fpnew_pkg_fp_width(dst_fmt_i) < fpnew_pkg_fp_width(src_fmt_i); + assign dst_fmt = (dst_fmt_is_int ? int_fmt_i : dst_fmt_i); + assign aux_data = {dst_fmt_is_int, vectorial_op, dst_fmt}; + assign target_aux_d = {dst_vec_op, dst_is_cpk}; + generate + if (OpGroup == 2'd3) begin : conv_target + assign conv_target_d = (dst_is_cpk ? operands_i[2 * Width+:Width] : operands_i[Width+:Width]); + end + else begin : not_conv_target + assign conv_target_d = 1'sb0; + end + endgenerate + reg [4:0] is_boxed_1op; + reg [9:0] is_boxed_2op; + always @(*) begin : boxed_2op + if (_sv2v_0) + ; + begin : sv2v_autoblock_7 + reg signed [31:0] fmt; + for (fmt = 0; fmt < NUM_FORMATS; fmt = fmt + 1) + begin + is_boxed_1op[fmt] = is_boxed_i[fmt * NUM_OPERANDS]; + is_boxed_2op[fmt * 2+:2] = is_boxed_i[(fmt * NUM_OPERANDS) + 1-:2]; + end + end + end + genvar _gv_lane_2; + localparam [0:4] fpnew_pkg_CPK_FORMATS = 5'b11000; + function automatic [0:4] fpnew_pkg_get_conv_lane_formats; + input reg [31:0] width; + input reg [0:4] cfg; + input reg [31:0] lane_no; + reg [0:4] res; + begin + begin : sv2v_autoblock_8 + reg [31:0] fmt; + for (fmt = 0; fmt < fpnew_pkg_NUM_FP_FORMATS; fmt = fmt + 1) + res[fmt] = cfg[fmt] && (((width / fpnew_pkg_fp_width(sv2v_cast_5D882(fmt))) > lane_no) || (fpnew_pkg_CPK_FORMATS[fmt] && (lane_no < 2))); + end + fpnew_pkg_get_conv_lane_formats = res; + end + endfunction + function automatic [0:3] fpnew_pkg_get_conv_lane_int_formats; + input reg [31:0] width; + input reg [0:4] cfg; + input reg [0:3] icfg; + input reg [31:0] lane_no; + reg [0:3] res; + reg [0:4] lanefmts; + begin + res = 1'sb0; + lanefmts = fpnew_pkg_get_conv_lane_formats(width, cfg, lane_no); + begin : sv2v_autoblock_9 + reg [31:0] ifmt; + for (ifmt = 0; ifmt < fpnew_pkg_NUM_INT_FORMATS; ifmt = ifmt + 1) + begin : sv2v_autoblock_10 + reg [31:0] fmt; + for (fmt = 0; fmt < fpnew_pkg_NUM_FP_FORMATS; fmt = fmt + 1) + res[ifmt] = res[ifmt] | ((icfg[ifmt] && lanefmts[fmt]) && (fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)) == fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)))); + end + end + fpnew_pkg_get_conv_lane_int_formats = res; + end + endfunction + function automatic [0:4] fpnew_pkg_get_lane_formats; + input reg [31:0] width; + input reg [0:4] cfg; + input reg [31:0] lane_no; + reg [0:4] res; + begin + begin : sv2v_autoblock_11 + reg [31:0] fmt; + for (fmt = 0; fmt < fpnew_pkg_NUM_FP_FORMATS; fmt = fmt + 1) + res[fmt] = cfg[fmt] & ((width / fpnew_pkg_fp_width(sv2v_cast_5D882(fmt))) > lane_no); + end + fpnew_pkg_get_lane_formats = res; + end + endfunction + function automatic [0:3] fpnew_pkg_get_lane_int_formats; + input reg [31:0] width; + input reg [0:4] cfg; + input reg [0:3] icfg; + input reg [31:0] lane_no; + reg [0:3] res; + reg [0:4] lanefmts; + begin + res = 1'sb0; + lanefmts = fpnew_pkg_get_lane_formats(width, cfg, lane_no); + begin : sv2v_autoblock_12 + reg [31:0] ifmt; + for (ifmt = 0; ifmt < fpnew_pkg_NUM_INT_FORMATS; ifmt = ifmt + 1) + begin : sv2v_autoblock_13 + reg [31:0] fmt; + for (fmt = 0; fmt < fpnew_pkg_NUM_FP_FORMATS; fmt = fmt + 1) + if (fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)) == fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt))) + res[ifmt] = res[ifmt] | (icfg[ifmt] && lanefmts[fmt]); + end + end + fpnew_pkg_get_lane_int_formats = res; + end + endfunction + function automatic [31:0] sv2v_cast_32; + input reg [31:0] inp; + sv2v_cast_32 = inp; + endfunction + function automatic [4:0] sv2v_cast_F930B; + input reg [4:0] inp; + sv2v_cast_F930B = inp; + endfunction + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + generate + for (_gv_lane_2 = 0; _gv_lane_2 < sv2v_cast_32_signed(NUM_LANES); _gv_lane_2 = _gv_lane_2 + 1) begin : gen_num_lanes + localparam lane = _gv_lane_2; + localparam [31:0] LANE = $unsigned(lane); + localparam [0:4] ACTIVE_FORMATS = fpnew_pkg_get_lane_formats(Width, FpFmtConfig, LANE); + localparam [0:3] ACTIVE_INT_FORMATS = fpnew_pkg_get_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE); + localparam [31:0] MAX_WIDTH = fpnew_pkg_max_fp_width(ACTIVE_FORMATS); + localparam [0:4] CONV_FORMATS = fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, LANE); + localparam [0:3] CONV_INT_FORMATS = fpnew_pkg_get_conv_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE); + localparam [31:0] CONV_WIDTH = fpnew_pkg_max_fp_width(CONV_FORMATS); + localparam [0:4] LANE_FORMATS = (OpGroup == 2'd3 ? CONV_FORMATS : ACTIVE_FORMATS); + localparam [31:0] LANE_WIDTH = (OpGroup == 2'd3 ? CONV_WIDTH : MAX_WIDTH); + wire [LANE_WIDTH - 1:0] local_result; + if ((lane == 0) || (EnableVectors & !((OpGroup == 2'd1) && (lane >= NUM_DIVSQRT_LANES)))) begin : active_lane + wire in_valid; + wire out_valid; + wire out_ready; + reg [(NUM_OPERANDS * LANE_WIDTH) - 1:0] local_operands; + wire [LANE_WIDTH - 1:0] op_result; + wire [4:0] op_status; + assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); + always @(*) begin : prepare_input + if (_sv2v_0) + ; + begin : sv2v_autoblock_14 + reg [31:0] i; + for (i = 0; i < NUM_OPERANDS; i = i + 1) + if (i == 2) + local_operands[i * (OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))] = operands_i[i * Width+:Width] >> (LANE * fpnew_pkg_fp_width((op_i == sv2v_cast_4CD2E(15) ? src_fmt_i : dst_fmt_i))); + else + local_operands[i * (OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))] = operands_i[i * Width+:Width] >> (LANE * fpnew_pkg_fp_width(src_fmt_i)); + end + if (OpGroup == 2'd3) begin + if (op_i == sv2v_cast_4CD2E(12)) + local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))] = operands_i[0+:Width] >> (LANE * fpnew_pkg_int_width(int_fmt_i)); + else if (op_i == sv2v_cast_4CD2E(10)) begin + if ((vectorial_op && op_mod_i) && is_up_cast) + local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))] = operands_i[0+:Width] >> ((LANE * fpnew_pkg_fp_width(src_fmt_i)) + (MAX_FP_WIDTH / 2)); + end + else if (dst_is_cpk) begin + if (lane == 1) + local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))] = operands_i[Width + (LANE_WIDTH - 1)-:LANE_WIDTH]; + end + end + end + if (OpGroup == 2'd0) begin : lane_instance + fpnew_fma_multi_B5D6B_2D261 #( + .AuxType_AUX_BITS(AUX_BITS), + .FpFmtConfig(LANE_FORMATS), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_fpnew_fma_multi( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands), + .is_boxed_i(is_boxed_i), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .src_fmt_i(src_fmt_i), + .src2_fmt_i((op_i == sv2v_cast_4CD2E(15) ? src_fmt_i : dst_fmt_i)), + .dst_fmt_i(dst_fmt_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(aux_data), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_aux[lane * AUX_BITS+:AUX_BITS]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + end + else if (OpGroup == 2'd1) begin : lane_instance + if (((DivSqrtSel == 2'd1) && LANE_FORMATS[0]) && (LANE_FORMATS[1:4] == {4 {1'sb0}})) begin : gen_th32_e906_divsqrt + fpnew_divsqrt_th_32_3DF01_FC8AC #( + .AuxType_AUX_BITS(AUX_BITS), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_fpnew_divsqrt_multi_th( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2))))) * 2]), + .is_boxed_i(is_boxed_2op), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(aux_data), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_aux[lane * AUX_BITS+:AUX_BITS]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + end + else if (DivSqrtSel == 2'd2) begin : gen_thmulti_c910_divsqrt + fpnew_divsqrt_th_64_multi_6575A_19233 #( + .AuxType_AUX_BITS(AUX_BITS), + .FpFmtConfig(LANE_FORMATS), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_fpnew_divsqrt_th_64_c910( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2))))) * 2]), + .is_boxed_i(is_boxed_2op), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .dst_fmt_i(dst_fmt_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(aux_data), + .vectorial_op_i(vectorial_op), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .divsqrt_done_o(divsqrt_done[lane]), + .simd_synch_done_i(simd_synch_done), + .divsqrt_ready_o(divsqrt_ready[lane]), + .simd_synch_rdy_i(simd_synch_rdy), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_aux[lane * AUX_BITS+:AUX_BITS]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + end + else begin : gen_pulp_divsqrt + fpnew_divsqrt_multi_E225A_B8CF6 #( + .AuxType_AUX_BITS(AUX_BITS), + .FpFmtConfig(LANE_FORMATS), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_fpnew_divsqrt_multi( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2))))) * 2]), + .is_boxed_i(is_boxed_2op), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .dst_fmt_i(dst_fmt_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(aux_data), + .vectorial_op_i(vectorial_op), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .divsqrt_done_o(divsqrt_done[lane]), + .simd_synch_done_i(simd_synch_done), + .divsqrt_ready_o(divsqrt_ready[lane]), + .simd_synch_rdy_i(simd_synch_rdy), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_aux[lane * AUX_BITS+:AUX_BITS]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + end + end + else if (OpGroup == 2'd2) begin + ; + end + else if (OpGroup == 2'd3) begin : lane_instance + fpnew_cast_multi_2E827_67072 #( + .AuxType_AUX_BITS(AUX_BITS), + .FpFmtConfig(LANE_FORMATS), + .IntFmtConfig(CONV_INT_FORMATS), + .NumPipeRegs(NumPipeRegs), + .PipeConfig(PipeConfig) + ) i_fpnew_cast_multi( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(local_operands[0+:(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))) : fpnew_pkg_max_fp_width(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))]), + .is_boxed_i(is_boxed_1op), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .src_fmt_i(src_fmt_i), + .dst_fmt_i(dst_fmt_i), + .int_fmt_i(int_fmt_i), + .tag_i(tag_i), + .mask_i(simd_mask_i[lane]), + .aux_i(aux_data), + .in_valid_i(in_valid), + .in_ready_o(lane_in_ready[lane]), + .flush_i(flush_i), + .result_o(op_result), + .status_o(op_status), + .extension_bit_o(lane_ext_bit[lane]), + .tag_o(lane_tags[lane]), + .mask_o(lane_masks[lane]), + .aux_o(lane_aux[lane * AUX_BITS+:AUX_BITS]), + .out_valid_o(out_valid), + .out_ready_i(out_ready), + .busy_o(lane_busy[lane]), + .reg_ena_i(reg_ena_i), + .early_out_valid_o(lane_early_out_valid[lane]) + ); + end + assign out_ready = out_ready_i & ((lane == 0) | result_is_vector); + assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector); + assign local_result = (lane_out_valid[lane] | ExtRegEna ? op_result : {(OpGroup == 2'd3 ? fpnew_pkg_max_fp_width(sv2v_cast_F930B(fpnew_pkg_get_conv_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2))))) : fpnew_pkg_max_fp_width(sv2v_cast_F930B(fpnew_pkg_get_lane_formats(Width, FpFmtConfig, sv2v_cast_32($unsigned(_gv_lane_2)))))) {lane_ext_bit[0]}}); + assign lane_status[lane * 5+:5] = (lane_out_valid[lane] | ExtRegEna ? op_status : {5 {1'sb0}}); + end + else begin : inactive_lane + assign lane_out_valid[lane] = 1'b0; + assign lane_in_ready[lane] = 1'b0; + assign lane_aux[lane * AUX_BITS+:AUX_BITS] = 1'b0; + assign lane_masks[lane] = 1'b1; + assign lane_tags[lane] = 1'b0; + assign divsqrt_done[lane] = 1'b0; + assign divsqrt_ready[lane] = 1'b0; + assign lane_ext_bit[lane] = 1'b1; + assign local_result = {LANE_WIDTH {lane_ext_bit[0]}}; + assign lane_status[lane * 5+:5] = 1'sb0; + assign lane_busy[lane] = 1'b0; + end + genvar _gv_fmt_10; + for (_gv_fmt_10 = 0; _gv_fmt_10 < NUM_FORMATS; _gv_fmt_10 = _gv_fmt_10 + 1) begin : pack_fp_result + localparam fmt = _gv_fmt_10; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + if (ACTIVE_FORMATS[fmt]) begin : genblk1 + assign fmt_slice_result[(fmt * Width) + ((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((LANE + 1) * FP_WIDTH) - 1 : ((((LANE + 1) * FP_WIDTH) - 1) + ((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((((LANE + 1) * FP_WIDTH) - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (((LANE + 1) * FP_WIDTH) - 1)) + 1)) - 1)-:((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((((LANE + 1) * FP_WIDTH) - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (((LANE + 1) * FP_WIDTH) - 1)) + 1)] = local_result[FP_WIDTH - 1:0]; + end + else if (((LANE + 1) * FP_WIDTH) <= Width) begin : genblk1 + assign fmt_slice_result[(fmt * Width) + ((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((LANE + 1) * FP_WIDTH) - 1 : ((((LANE + 1) * FP_WIDTH) - 1) + ((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((((LANE + 1) * FP_WIDTH) - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (((LANE + 1) * FP_WIDTH) - 1)) + 1)) - 1)-:((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((((LANE + 1) * FP_WIDTH) - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (((LANE + 1) * FP_WIDTH) - 1)) + 1)] = {((((LANE + 1) * FP_WIDTH) - 1) >= (LANE * FP_WIDTH) ? ((((LANE + 1) * FP_WIDTH) - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (((LANE + 1) * FP_WIDTH) - 1)) + 1) {lane_ext_bit[LANE]}}; + end + else if ((LANE * FP_WIDTH) < Width) begin : genblk1 + assign fmt_slice_result[(fmt * Width) + ((Width - 1) >= (LANE * FP_WIDTH) ? Width - 1 : ((Width - 1) + ((Width - 1) >= (LANE * FP_WIDTH) ? ((Width - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (Width - 1)) + 1)) - 1)-:((Width - 1) >= (LANE * FP_WIDTH) ? ((Width - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (Width - 1)) + 1)] = {((Width - 1) >= (LANE * FP_WIDTH) ? ((Width - 1) - (LANE * FP_WIDTH)) + 1 : ((LANE * FP_WIDTH) - (Width - 1)) + 1) {lane_ext_bit[LANE]}}; + end + end + if (OpGroup == 2'd3) begin : int_results_enabled + genvar _gv_ifmt_6; + for (_gv_ifmt_6 = 0; _gv_ifmt_6 < NUM_INT_FORMATS; _gv_ifmt_6 = _gv_ifmt_6 + 1) begin : pack_int_result + localparam ifmt = _gv_ifmt_6; + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if (ACTIVE_INT_FORMATS[ifmt]) begin : genblk1 + assign ifmt_slice_result[(ifmt * Width) + ((((LANE + 1) * INT_WIDTH) - 1) >= (LANE * INT_WIDTH) ? ((LANE + 1) * INT_WIDTH) - 1 : ((((LANE + 1) * INT_WIDTH) - 1) + ((((LANE + 1) * INT_WIDTH) - 1) >= (LANE * INT_WIDTH) ? ((((LANE + 1) * INT_WIDTH) - 1) - (LANE * INT_WIDTH)) + 1 : ((LANE * INT_WIDTH) - (((LANE + 1) * INT_WIDTH) - 1)) + 1)) - 1)-:((((LANE + 1) * INT_WIDTH) - 1) >= (LANE * INT_WIDTH) ? ((((LANE + 1) * INT_WIDTH) - 1) - (LANE * INT_WIDTH)) + 1 : ((LANE * INT_WIDTH) - (((LANE + 1) * INT_WIDTH) - 1)) + 1)] = local_result[INT_WIDTH - 1:0]; + end + else if (((LANE + 1) * INT_WIDTH) <= Width) begin : genblk1 + assign ifmt_slice_result[(ifmt * Width) + ((((LANE + 1) * INT_WIDTH) - 1) >= (LANE * INT_WIDTH) ? ((LANE + 1) * INT_WIDTH) - 1 : ((((LANE + 1) * INT_WIDTH) - 1) + ((((LANE + 1) * INT_WIDTH) - 1) >= (LANE * INT_WIDTH) ? ((((LANE + 1) * INT_WIDTH) - 1) - (LANE * INT_WIDTH)) + 1 : ((LANE * INT_WIDTH) - (((LANE + 1) * INT_WIDTH) - 1)) + 1)) - 1)-:((((LANE + 1) * INT_WIDTH) - 1) >= (LANE * INT_WIDTH) ? ((((LANE + 1) * INT_WIDTH) - 1) - (LANE * INT_WIDTH)) + 1 : ((LANE * INT_WIDTH) - (((LANE + 1) * INT_WIDTH) - 1)) + 1)] = 1'sb0; + end + else if ((LANE * INT_WIDTH) < Width) begin : genblk1 + assign ifmt_slice_result[(ifmt * Width) + ((Width - 1) >= (LANE * INT_WIDTH) ? Width - 1 : ((Width - 1) + ((Width - 1) >= (LANE * INT_WIDTH) ? ((Width - 1) - (LANE * INT_WIDTH)) + 1 : ((LANE * INT_WIDTH) - (Width - 1)) + 1)) - 1)-:((Width - 1) >= (LANE * INT_WIDTH) ? ((Width - 1) - (LANE * INT_WIDTH)) + 1 : ((LANE * INT_WIDTH) - (Width - 1)) + 1)] = 1'sb0; + end + end + end + end + endgenerate + genvar _gv_fmt_11; + generate + for (_gv_fmt_11 = 0; _gv_fmt_11 < NUM_FORMATS; _gv_fmt_11 = _gv_fmt_11 + 1) begin : extend_fp_result + localparam fmt = _gv_fmt_11; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + if ((NUM_LANES * FP_WIDTH) < Width) begin : genblk1 + assign fmt_slice_result[(fmt * Width) + ((Width - 1) >= (NUM_LANES * FP_WIDTH) ? Width - 1 : ((Width - 1) + ((Width - 1) >= (NUM_LANES * FP_WIDTH) ? ((Width - 1) - (NUM_LANES * FP_WIDTH)) + 1 : ((NUM_LANES * FP_WIDTH) - (Width - 1)) + 1)) - 1)-:((Width - 1) >= (NUM_LANES * FP_WIDTH) ? ((Width - 1) - (NUM_LANES * FP_WIDTH)) + 1 : ((NUM_LANES * FP_WIDTH) - (Width - 1)) + 1)] = {((Width - 1) >= (NUM_LANES * FP_WIDTH) ? ((Width - 1) - (NUM_LANES * FP_WIDTH)) + 1 : ((NUM_LANES * FP_WIDTH) - (Width - 1)) + 1) {lane_ext_bit[0]}}; + end + end + endgenerate + genvar _gv_ifmt_7; + generate + for (_gv_ifmt_7 = 0; _gv_ifmt_7 < NUM_INT_FORMATS; _gv_ifmt_7 = _gv_ifmt_7 + 1) begin : extend_or_mute_int_result + localparam ifmt = _gv_ifmt_7; + if (OpGroup != 2'd3) begin : mute_int_result + assign ifmt_slice_result[ifmt * Width+:Width] = 1'sb0; + end + else begin : extend_int_result + localparam [31:0] INT_WIDTH = fpnew_pkg_int_width(sv2v_cast_CDB06(ifmt)); + if ((NUM_LANES * INT_WIDTH) < Width) begin : genblk1 + assign ifmt_slice_result[(ifmt * Width) + ((Width - 1) >= (NUM_LANES * INT_WIDTH) ? Width - 1 : ((Width - 1) + ((Width - 1) >= (NUM_LANES * INT_WIDTH) ? ((Width - 1) - (NUM_LANES * INT_WIDTH)) + 1 : ((NUM_LANES * INT_WIDTH) - (Width - 1)) + 1)) - 1)-:((Width - 1) >= (NUM_LANES * INT_WIDTH) ? ((Width - 1) - (NUM_LANES * INT_WIDTH)) + 1 : ((NUM_LANES * INT_WIDTH) - (Width - 1)) + 1)] = 1'sb0; + end + end + end + if (OpGroup == 2'd3) begin : target_regs + reg [(0 >= NumPipeRegs ? ((1 - NumPipeRegs) * Width) + ((NumPipeRegs * Width) - 1) : ((NumPipeRegs + 1) * Width) - 1):(0 >= NumPipeRegs ? NumPipeRegs * Width : 0)] byp_pipe_target_q; + reg [(0 >= NumPipeRegs ? ((1 - NumPipeRegs) * 3) + ((NumPipeRegs * 3) - 1) : ((NumPipeRegs + 1) * 3) - 1):(0 >= NumPipeRegs ? NumPipeRegs * 3 : 0)] byp_pipe_aux_q; + reg [0:NumPipeRegs] byp_pipe_valid_q; + wire [0:NumPipeRegs] byp_pipe_ready; + wire [Width * 1:1] sv2v_tmp_341F5; + assign sv2v_tmp_341F5 = conv_target_d; + always @(*) byp_pipe_target_q[(0 >= NumPipeRegs ? 0 : NumPipeRegs) * Width+:Width] = sv2v_tmp_341F5; + wire [3:1] sv2v_tmp_5E9D8; + assign sv2v_tmp_5E9D8 = target_aux_d; + always @(*) byp_pipe_aux_q[(0 >= NumPipeRegs ? 0 : NumPipeRegs) * 3+:3] = sv2v_tmp_5E9D8; + wire [1:1] sv2v_tmp_967FD; + assign sv2v_tmp_967FD = in_valid_i & vectorial_op; + always @(*) byp_pipe_valid_q[0] = sv2v_tmp_967FD; + genvar _gv_i_15; + for (_gv_i_15 = 0; _gv_i_15 < NumPipeRegs; _gv_i_15 = _gv_i_15 + 1) begin : gen_bypass_pipeline + localparam i = _gv_i_15; + wire reg_ena; + assign byp_pipe_ready[i] = byp_pipe_ready[i + 1] | ~byp_pipe_valid_q[i + 1]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + byp_pipe_valid_q[i + 1] <= 1'b0; + else + byp_pipe_valid_q[i + 1] <= (flush_i ? 1'b0 : (byp_pipe_ready[i] ? byp_pipe_valid_q[i] : byp_pipe_valid_q[i + 1])); + assign reg_ena = (byp_pipe_ready[i] & byp_pipe_valid_q[i]) | reg_ena_i[i]; + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + byp_pipe_target_q[(0 >= NumPipeRegs ? i + 1 : NumPipeRegs - (i + 1)) * Width+:Width] <= 1'sb0; + else + byp_pipe_target_q[(0 >= NumPipeRegs ? i + 1 : NumPipeRegs - (i + 1)) * Width+:Width] <= (reg_ena ? byp_pipe_target_q[(0 >= NumPipeRegs ? i : NumPipeRegs - i) * Width+:Width] : byp_pipe_target_q[(0 >= NumPipeRegs ? i + 1 : NumPipeRegs - (i + 1)) * Width+:Width]); + always @(posedge clk_i or negedge rst_ni) + if (!rst_ni) + byp_pipe_aux_q[(0 >= NumPipeRegs ? i + 1 : NumPipeRegs - (i + 1)) * 3+:3] <= 1'sb0; + else + byp_pipe_aux_q[(0 >= NumPipeRegs ? i + 1 : NumPipeRegs - (i + 1)) * 3+:3] <= (reg_ena ? byp_pipe_aux_q[(0 >= NumPipeRegs ? i : NumPipeRegs - i) * 3+:3] : byp_pipe_aux_q[(0 >= NumPipeRegs ? i + 1 : NumPipeRegs - (i + 1)) * 3+:3]); + end + assign byp_pipe_ready[NumPipeRegs] = out_ready_i & result_is_vector; + assign conv_target_q = byp_pipe_target_q[(0 >= NumPipeRegs ? NumPipeRegs : NumPipeRegs - NumPipeRegs) * Width+:Width]; + assign {result_vec_op, result_is_cpk} = byp_pipe_aux_q[(0 >= NumPipeRegs ? NumPipeRegs : NumPipeRegs - NumPipeRegs) * 3+:3]; + end + else begin : no_conv + assign {result_vec_op, result_is_cpk} = 1'sb0; + assign conv_target_q = 1'sb0; + end + if ((DivSqrtSel != 2'd1) && !ExtRegEna) begin : genblk7 + assign simd_synch_rdy = (EnableVectors ? &divsqrt_ready[NUM_DIVSQRT_LANES - 1:0] : divsqrt_ready[0]); + assign simd_synch_done = (EnableVectors ? &divsqrt_done[NUM_DIVSQRT_LANES - 1:0] : divsqrt_done[0]); + end + else begin : genblk7 + assign simd_synch_rdy = 1'sb0; + assign simd_synch_done = 1'sb0; + end + endgenerate + assign {result_fmt_is_int, result_is_vector, result_fmt} = lane_aux[0+:AUX_BITS]; + assign result_o = (result_fmt_is_int ? ifmt_slice_result[result_fmt * Width+:Width] : fmt_slice_result[result_fmt * Width+:Width]); + assign extension_bit_o = lane_ext_bit[0]; + assign tag_o = lane_tags[0]; + assign busy_o = |lane_busy; + assign early_out_valid_o = |lane_early_out_valid; + assign out_valid_o = lane_out_valid[0]; + always @(*) begin : output_processing + reg [4:0] temp_status; + if (_sv2v_0) + ; + temp_status = 1'sb0; + begin : sv2v_autoblock_15 + reg signed [31:0] i; + for (i = 0; i < sv2v_cast_32_signed(NUM_LANES); i = i + 1) + temp_status = temp_status | (lane_status[i * 5+:5] & {5 {lane_masks[i]}}); + end + status_o = temp_status; + end + initial _sv2v_0 = 0; +endmodule +module fpnew_rounding ( + abs_value_i, + sign_i, + round_sticky_bits_i, + rnd_mode_i, + effective_subtraction_i, + abs_rounded_o, + sign_o, + exact_zero_o +); + reg _sv2v_0; + parameter [31:0] AbsWidth = 2; + input wire [AbsWidth - 1:0] abs_value_i; + input wire sign_i; + input wire [1:0] round_sticky_bits_i; + input wire [2:0] rnd_mode_i; + input wire effective_subtraction_i; + output wire [AbsWidth - 1:0] abs_rounded_o; + output wire sign_o; + output wire exact_zero_o; + reg round_up; + localparam [0:0] fpnew_pkg_DONT_CARE = 1'b1; + always @(*) begin : rounding_decision + if (_sv2v_0) + ; + (* full_case, parallel_case *) + case (rnd_mode_i) + 3'b000: + (* full_case, parallel_case *) + case (round_sticky_bits_i) + 2'b00, 2'b01: round_up = 1'b0; + 2'b10: round_up = abs_value_i[0]; + 2'b11: round_up = 1'b1; + default: round_up = fpnew_pkg_DONT_CARE; + endcase + 3'b001: round_up = 1'b0; + 3'b010: round_up = (|round_sticky_bits_i ? sign_i : 1'b0); + 3'b011: round_up = (|round_sticky_bits_i ? ~sign_i : 1'b0); + 3'b100: round_up = round_sticky_bits_i[1]; + 3'b101: round_up = ~abs_value_i[0] & |round_sticky_bits_i; + default: round_up = fpnew_pkg_DONT_CARE; + endcase + end + assign abs_rounded_o = abs_value_i + round_up; + assign exact_zero_o = (abs_value_i == {AbsWidth {1'sb0}}) && (round_sticky_bits_i == {2 {1'sb0}}); + assign sign_o = (exact_zero_o && effective_subtraction_i ? rnd_mode_i == 3'b010 : sign_i); + initial _sv2v_0 = 0; +endmodule +module fpnew_top ( + clk_i, + rst_ni, + operands_i, + rnd_mode_i, + op_i, + op_mod_i, + src_fmt_i, + dst_fmt_i, + int_fmt_i, + vectorial_op_i, + tag_i, + simd_mask_i, + in_valid_i, + in_ready_o, + flush_i, + result_o, + status_o, + tag_o, + out_valid_o, + out_ready_i, + busy_o, + early_valid_o +); + reg _sv2v_0; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + localparam [31:0] fpnew_pkg_NUM_INT_FORMATS = 4; + localparam [42:0] fpnew_pkg_RV64D_Xsflt = 43'h000000207ff; + parameter [42:0] Features = fpnew_pkg_RV64D_Xsflt; + localparam [31:0] fpnew_pkg_NUM_OPGROUPS = 4; + function automatic [159:0] sv2v_cast_C3475; + input reg [159:0] inp; + sv2v_cast_C3475 = inp; + endfunction + function automatic [((32'd4 * 32'd5) * 32) - 1:0] sv2v_cast_52F10; + input reg [((32'd4 * 32'd5) * 32) - 1:0] inp; + sv2v_cast_52F10 = inp; + endfunction + function automatic [((32'd4 * 32'd5) * 2) - 1:0] sv2v_cast_18D94; + input reg [((32'd4 * 32'd5) * 2) - 1:0] inp; + sv2v_cast_18D94 = inp; + endfunction + localparam [(((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 32) + ((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 2)) + 1:0] fpnew_pkg_DEFAULT_NOREGS = {sv2v_cast_52F10({fpnew_pkg_NUM_OPGROUPS {sv2v_cast_C3475(0)}}), sv2v_cast_18D94({{fpnew_pkg_NUM_FP_FORMATS {2'd1}}, {fpnew_pkg_NUM_FP_FORMATS {2'd2}}, {fpnew_pkg_NUM_FP_FORMATS {2'd1}}, {fpnew_pkg_NUM_FP_FORMATS {2'd2}}}), 2'd0}; + parameter [(((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 32) + ((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 2)) + 1:0] Implementation = fpnew_pkg_DEFAULT_NOREGS; + parameter [1:0] DivSqrtSel = 2'd2; + parameter [31:0] TrueSIMDClass = 0; + parameter [31:0] EnableSIMDMask = 0; + localparam [319:0] fpnew_pkg_FP_ENCODINGS = 320'h8000000170000000b00000034000000050000000a00000005000000020000000800000007; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + function automatic [31:0] fpnew_pkg_fp_width; + input reg [2:0] fmt; + fpnew_pkg_fp_width = (fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - fmt) * 64) + 31-:32]) + 1; + endfunction + function automatic signed [31:0] fpnew_pkg_maximum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_maximum = (a > b ? a : b); + endfunction + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + function automatic [31:0] fpnew_pkg_max_fp_width; + input reg [0:4] cfg; + reg [31:0] res; + begin + res = 0; + begin : sv2v_autoblock_1 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) + res = $unsigned(fpnew_pkg_maximum(res, fpnew_pkg_fp_width(sv2v_cast_5D882(i)))); + end + fpnew_pkg_max_fp_width = res; + end + endfunction + function automatic signed [31:0] fpnew_pkg_minimum; + input reg signed [31:0] a; + input reg signed [31:0] b; + fpnew_pkg_minimum = (a < b ? a : b); + endfunction + function automatic [31:0] fpnew_pkg_max_num_lanes; + input reg [31:0] width; + input reg [0:4] cfg; + input reg vec; + if (vec) begin : sv2v_autoblock_2 + reg [31:0] res; + res = fpnew_pkg_max_fp_width(cfg); + begin : sv2v_autoblock_3 + reg [31:0] i; + for (i = 0; i < fpnew_pkg_NUM_FP_FORMATS; i = i + 1) + if (cfg[i]) begin : sv2v_autoblock_4 + reg [31:0] format_width; + format_width = (fpnew_pkg_FP_ENCODINGS[((4 - i) * 64) + 63-:32] + fpnew_pkg_FP_ENCODINGS[((4 - i) * 64) + 31-:32]) + 1; + res = $unsigned(fpnew_pkg_minimum(res, format_width)); + end + end + fpnew_pkg_max_num_lanes = width / res; + end + else + fpnew_pkg_max_num_lanes = 1; + endfunction + localparam [31:0] NumLanes = fpnew_pkg_max_num_lanes(Features[42-:32], Features[8-:5], Features[10]); + localparam [31:0] WIDTH = Features[42-:32]; + localparam [31:0] NUM_OPERANDS = 3; + input wire clk_i; + input wire rst_ni; + input wire [(NUM_OPERANDS * WIDTH) - 1:0] operands_i; + input wire [2:0] rnd_mode_i; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + input wire [3:0] op_i; + input wire op_mod_i; + input wire [2:0] src_fmt_i; + input wire [2:0] dst_fmt_i; + localparam [31:0] fpnew_pkg_INT_FORMAT_BITS = 2; + input wire [1:0] int_fmt_i; + input wire vectorial_op_i; + input wire tag_i; + input wire [NumLanes - 1:0] simd_mask_i; + input wire in_valid_i; + output wire in_ready_o; + input wire flush_i; + output wire [WIDTH - 1:0] result_o; + output wire [4:0] status_o; + output wire tag_o; + output wire out_valid_o; + input wire out_ready_i; + output wire busy_o; + output wire early_valid_o; + localparam [31:0] NUM_OPGROUPS = fpnew_pkg_NUM_OPGROUPS; + localparam [31:0] NUM_FORMATS = fpnew_pkg_NUM_FP_FORMATS; + wire [3:0] opgrp_in_ready; + wire [3:0] opgrp_out_valid; + wire [3:0] opgrp_out_ready; + wire [3:0] opgrp_ext; + wire [3:0] opgrp_busy; + wire [3:0] opgrp_early_valid; + wire [((WIDTH + 5) >= 0 ? (4 * (WIDTH + 6)) - 1 : (4 * (1 - (WIDTH + 5))) + (WIDTH + 4)):((WIDTH + 5) >= 0 ? 0 : WIDTH + 5)] opgrp_outputs; + wire [(NUM_FORMATS * NUM_OPERANDS) - 1:0] is_boxed; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + function automatic [1:0] fpnew_pkg_get_opgroup; + input reg [3:0] op; + (* full_case, parallel_case *) + case (op) + sv2v_cast_4CD2E(0), sv2v_cast_4CD2E(1), sv2v_cast_4CD2E(2), sv2v_cast_4CD2E(15), sv2v_cast_4CD2E(3): fpnew_pkg_get_opgroup = 2'd0; + sv2v_cast_4CD2E(4), sv2v_cast_4CD2E(5): fpnew_pkg_get_opgroup = 2'd1; + sv2v_cast_4CD2E(6), sv2v_cast_4CD2E(7), sv2v_cast_4CD2E(8), sv2v_cast_4CD2E(9): fpnew_pkg_get_opgroup = 2'd2; + sv2v_cast_4CD2E(10), sv2v_cast_4CD2E(11), sv2v_cast_4CD2E(12), sv2v_cast_4CD2E(13), sv2v_cast_4CD2E(14): fpnew_pkg_get_opgroup = 2'd3; + default: fpnew_pkg_get_opgroup = 2'd2; + endcase + endfunction + assign in_ready_o = in_valid_i & opgrp_in_ready[fpnew_pkg_get_opgroup(op_i)]; + genvar _gv_fmt_12; + function automatic signed [31:0] sv2v_cast_32_signed; + input reg signed [31:0] inp; + sv2v_cast_32_signed = inp; + endfunction + generate + for (_gv_fmt_12 = 0; _gv_fmt_12 < sv2v_cast_32_signed(NUM_FORMATS); _gv_fmt_12 = _gv_fmt_12 + 1) begin : gen_nanbox_check + localparam fmt = _gv_fmt_12; + localparam [31:0] FP_WIDTH = fpnew_pkg_fp_width(sv2v_cast_5D882(fmt)); + if (Features[9] && (FP_WIDTH < WIDTH)) begin : check + genvar _gv_op_3; + for (_gv_op_3 = 0; _gv_op_3 < sv2v_cast_32_signed(NUM_OPERANDS); _gv_op_3 = _gv_op_3 + 1) begin : operands + localparam op = _gv_op_3; + assign is_boxed[(fmt * NUM_OPERANDS) + op] = (!vectorial_op_i ? operands_i[(op * WIDTH) + ((WIDTH - 1) >= FP_WIDTH ? WIDTH - 1 : ((WIDTH - 1) + ((WIDTH - 1) >= FP_WIDTH ? ((WIDTH - 1) - FP_WIDTH) + 1 : (FP_WIDTH - (WIDTH - 1)) + 1)) - 1)-:((WIDTH - 1) >= FP_WIDTH ? ((WIDTH - 1) - FP_WIDTH) + 1 : (FP_WIDTH - (WIDTH - 1)) + 1)] == {((WIDTH - 1) >= FP_WIDTH ? ((WIDTH - 1) - FP_WIDTH) + 1 : (FP_WIDTH - (WIDTH - 1)) + 1) * 1 {1'sb1}} : 1'b1); + end + end + else begin : no_check + assign is_boxed[fmt * NUM_OPERANDS+:NUM_OPERANDS] = 1'sb1; + end + end + endgenerate + wire [NumLanes - 1:0] simd_mask; + function automatic [0:0] sv2v_cast_1; + input reg [0:0] inp; + sv2v_cast_1 = inp; + endfunction + assign simd_mask = simd_mask_i | ~{NumLanes {sv2v_cast_1(EnableSIMDMask)}}; + genvar _gv_opgrp_1; + function automatic [31:0] fpnew_pkg_num_operands; + input reg [1:0] grp; + (* full_case, parallel_case *) + case (grp) + 2'd0: fpnew_pkg_num_operands = 3; + 2'd1: fpnew_pkg_num_operands = 2; + 2'd2: fpnew_pkg_num_operands = 2; + 2'd3: fpnew_pkg_num_operands = 3; + default: fpnew_pkg_num_operands = 0; + endcase + endfunction + function automatic [1:0] sv2v_cast_2; + input reg [1:0] inp; + sv2v_cast_2 = inp; + endfunction + generate + for (_gv_opgrp_1 = 0; _gv_opgrp_1 < sv2v_cast_32_signed(NUM_OPGROUPS); _gv_opgrp_1 = _gv_opgrp_1 + 1) begin : gen_operation_groups + localparam opgrp = _gv_opgrp_1; + localparam [31:0] NUM_OPS = fpnew_pkg_num_operands(sv2v_cast_2(opgrp)); + localparam [1:0] OpGroup = sv2v_cast_2(opgrp); + localparam [0:0] EnableVectors = Features[10]; + localparam [0:4] FpFmtMask = Features[8-:5]; + localparam [0:3] IntFmtMask = Features[3-:fpnew_pkg_NUM_INT_FORMATS]; + localparam [159:0] FmtPipeRegs = Implementation[(((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 32) + (((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 2) + 1)) - ((((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 32) - 1) - (32 * ((3 - opgrp) * fpnew_pkg_NUM_FP_FORMATS)))+:160]; + localparam [9:0] FmtUnitTypes = Implementation[(((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 2) + 1) - ((((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 2) - 1) - (2 * ((3 - opgrp) * fpnew_pkg_NUM_FP_FORMATS)))+:10]; + localparam [1:0] PipeConfig = Implementation[1-:2]; + wire in_valid; + reg [(NUM_FORMATS * NUM_OPS) - 1:0] input_boxed; + assign in_valid = in_valid_i & (fpnew_pkg_get_opgroup(op_i) == sv2v_cast_2(opgrp)); + always @(*) begin : slice_inputs + if (_sv2v_0) + ; + begin : sv2v_autoblock_5 + reg [31:0] fmt; + for (fmt = 0; fmt < NUM_FORMATS; fmt = fmt + 1) + input_boxed[fmt * fpnew_pkg_num_operands(sv2v_cast_2(_gv_opgrp_1))+:fpnew_pkg_num_operands(sv2v_cast_2(_gv_opgrp_1))] = is_boxed[(fmt * NUM_OPERANDS) + (NUM_OPS - 1)-:NUM_OPS]; + end + end + fpnew_opgroup_block_37AAD #( + .OpGroup(OpGroup), + .Width(WIDTH), + .EnableVectors(EnableVectors), + .DivSqrtSel(DivSqrtSel), + .FpFmtMask(FpFmtMask), + .IntFmtMask(IntFmtMask), + .FmtPipeRegs(FmtPipeRegs), + .FmtUnitTypes(FmtUnitTypes), + .PipeConfig(PipeConfig), + .TrueSIMDClass(TrueSIMDClass) + ) i_opgroup_block( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(operands_i[WIDTH * ((NUM_OPS - 1) - (NUM_OPS - 1))+:WIDTH * NUM_OPS]), + .is_boxed_i(input_boxed), + .rnd_mode_i(rnd_mode_i), + .op_i(op_i), + .op_mod_i(op_mod_i), + .src_fmt_i(src_fmt_i), + .dst_fmt_i(dst_fmt_i), + .int_fmt_i(int_fmt_i), + .vectorial_op_i(vectorial_op_i), + .tag_i(tag_i), + .simd_mask_i(simd_mask), + .in_valid_i(in_valid), + .in_ready_o(opgrp_in_ready[opgrp]), + .flush_i(flush_i), + .result_o(opgrp_outputs[((WIDTH + 5) >= 0 ? (opgrp * ((WIDTH + 5) >= 0 ? WIDTH + 6 : 1 - (WIDTH + 5))) + ((WIDTH + 5) >= 0 ? WIDTH + 5 : (WIDTH + 5) - (WIDTH + 5)) : (((opgrp * ((WIDTH + 5) >= 0 ? WIDTH + 6 : 1 - (WIDTH + 5))) + ((WIDTH + 5) >= 0 ? WIDTH + 5 : (WIDTH + 5) - (WIDTH + 5))) + ((WIDTH + 5) >= 6 ? WIDTH + 0 : 7 - (WIDTH + 5))) - 1)-:((WIDTH + 5) >= 6 ? WIDTH + 0 : 7 - (WIDTH + 5))]), + .status_o(opgrp_outputs[((WIDTH + 5) >= 0 ? (opgrp * ((WIDTH + 5) >= 0 ? WIDTH + 6 : 1 - (WIDTH + 5))) + ((WIDTH + 5) >= 0 ? 5 : WIDTH + 0) : ((opgrp * ((WIDTH + 5) >= 0 ? WIDTH + 6 : 1 - (WIDTH + 5))) + ((WIDTH + 5) >= 0 ? 5 : WIDTH + 0)) + 4)-:5]), + .extension_bit_o(opgrp_ext[opgrp]), + .tag_o(opgrp_outputs[(opgrp * ((WIDTH + 5) >= 0 ? WIDTH + 6 : 1 - (WIDTH + 5))) + ((WIDTH + 5) >= 0 ? 0 : WIDTH + 5)]), + .out_valid_o(opgrp_out_valid[opgrp]), + .out_ready_i(opgrp_out_ready[opgrp]), + .busy_o(opgrp_busy[opgrp]), + .early_valid_o(opgrp_early_valid[opgrp]) + ); + end + endgenerate + wire [WIDTH + 5:0] arbiter_output; + localparam [31:0] sv2v_uu_i_arbiter_NumIn = NUM_OPGROUPS; + localparam [31:0] sv2v_uu_i_arbiter_IdxWidth = $unsigned(2); + localparam [sv2v_uu_i_arbiter_IdxWidth - 1:0] sv2v_uu_i_arbiter_ext_rr_i_0 = 1'sb0; + rr_arb_tree_A5EF3_ED1F7 #( + .DataType_WIDTH(WIDTH), + .NumIn(NUM_OPGROUPS), + .AxiVldRdy(1'b1) + ) i_arbiter( + .clk_i(clk_i), + .rst_ni(rst_ni), + .flush_i(flush_i), + .rr_i(sv2v_uu_i_arbiter_ext_rr_i_0), + .req_i(opgrp_out_valid), + .gnt_o(opgrp_out_ready), + .data_i(opgrp_outputs), + .gnt_i(out_ready_i), + .req_o(out_valid_o), + .data_o(arbiter_output), + .idx_o() + ); + assign result_o = arbiter_output[WIDTH + 5-:((WIDTH + 5) >= 6 ? WIDTH + 0 : 7 - (WIDTH + 5))]; + assign status_o = arbiter_output[5-:5]; + assign tag_o = arbiter_output[0]; + assign early_valid_o = |opgrp_early_valid; + assign busy_o = |opgrp_busy; + initial _sv2v_0 = 0; +endmodule +module FloatCoreWrapper ( + clk_i, + rst_ni, + in_valid_i, + in_ready_o, + operands_i_0, + operands_i_1, + operands_i_2, + op_i, + op_mod_i, + rnd_mode_i, + flush_i, + out_valid_o, + out_ready_i, + result_o, + status_o_0, + status_o_1, + status_o_2, + status_o_3, + status_o_4, + busy_o, + early_valid_o +); + input wire clk_i; + input wire rst_ni; + input wire in_valid_i; + output wire in_ready_o; + input wire [31:0] operands_i_0; + input wire [31:0] operands_i_1; + input wire [31:0] operands_i_2; + input wire [3:0] op_i; + input wire op_mod_i; + input wire [2:0] rnd_mode_i; + input wire flush_i; + output wire out_valid_o; + input wire out_ready_i; + output wire [31:0] result_o; + output wire status_o_0; + output wire status_o_1; + output wire status_o_2; + output wire status_o_3; + output wire status_o_4; + output wire busy_o; + output wire early_valid_o; + wire [95:0] operands_i; + assign operands_i[0+:32] = operands_i_0; + assign operands_i[32+:32] = operands_i_1; + assign operands_i[64+:32] = operands_i_2; + wire [4:0] status_o_pkg; + assign status_o_0 = status_o_pkg[0]; + assign status_o_1 = status_o_pkg[1]; + assign status_o_2 = status_o_pkg[2]; + assign status_o_3 = status_o_pkg[3]; + assign status_o_4 = status_o_pkg[4]; + localparam [31:0] fpnew_pkg_NUM_OPGROUPS = 4; + localparam [31:0] fpnew_pkg_NUM_FP_FORMATS = 5; + function automatic [159:0] sv2v_cast_C3475; + input reg [159:0] inp; + sv2v_cast_C3475 = inp; + endfunction + function automatic [((32'd4 * 32'd5) * 32) - 1:0] sv2v_cast_52F10; + input reg [((32'd4 * 32'd5) * 32) - 1:0] inp; + sv2v_cast_52F10 = inp; + endfunction + function automatic [((32'd4 * 32'd5) * 2) - 1:0] sv2v_cast_18D94; + input reg [((32'd4 * 32'd5) * 2) - 1:0] inp; + sv2v_cast_18D94 = inp; + endfunction + localparam [(((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 32) + ((fpnew_pkg_NUM_OPGROUPS * fpnew_pkg_NUM_FP_FORMATS) * 2)) + 1:0] impl = {sv2v_cast_52F10({fpnew_pkg_NUM_OPGROUPS {sv2v_cast_C3475('d3)}}), sv2v_cast_18D94({{fpnew_pkg_NUM_FP_FORMATS {2'd1}}, {fpnew_pkg_NUM_FP_FORMATS {2'd2}}, {fpnew_pkg_NUM_FP_FORMATS {2'd1}}, {fpnew_pkg_NUM_FP_FORMATS {2'd2}}}), 2'd3}; + localparam [31:0] fpnew_pkg_FP_FORMAT_BITS = 3; + localparam [31:0] fpnew_pkg_NUM_INT_FORMATS = 4; + localparam [31:0] fpnew_pkg_INT_FORMAT_BITS = 2; + localparam [42:0] fpnew_pkg_RV32F = 43'h00000010302; + localparam [31:0] fpnew_pkg_OP_BITS = 4; + function automatic [3:0] sv2v_cast_4CD2E; + input reg [3:0] inp; + sv2v_cast_4CD2E = inp; + endfunction + function automatic [2:0] sv2v_cast_5D882; + input reg [2:0] inp; + sv2v_cast_5D882 = inp; + endfunction + function automatic [1:0] sv2v_cast_CDB06; + input reg [1:0] inp; + sv2v_cast_CDB06 = inp; + endfunction + fpnew_top #( + .Features(fpnew_pkg_RV32F), + .Implementation(impl), + .DivSqrtSel(2'd1) + ) core( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(operands_i), + .rnd_mode_i(rnd_mode_i), + .op_i(sv2v_cast_4CD2E(op_i)), + .op_mod_i(op_mod_i), + .src_fmt_i(sv2v_cast_5D882('d0)), + .dst_fmt_i(sv2v_cast_5D882('d0)), + .int_fmt_i(sv2v_cast_CDB06(2)), + .vectorial_op_i(1'b0), + .tag_i(1'b0), + .simd_mask_i(1'b0), + .in_valid_i(in_valid_i), + .flush_i(flush_i), + .out_ready_i(out_ready_i), + .in_ready_o(in_ready_o), + .result_o(result_o), + .status_o(status_o_pkg), + .tag_o(), + .out_valid_o(out_valid_o), + .busy_o(busy_o), + .early_valid_o(early_valid_o) + ); +endmodule +module Sram_512x128 ( + clock, + enable, + write, + addr, + wdata, + wmask, + rdata +); + input clock; + input enable; + input write; + input [8:0] addr; + input [127:0] wdata; + input [15:0] wmask; + output wire [127:0] rdata; + fakeram_512x128 sramModules_0( + .clock(clock), + .enable(enable), + .write(write), + .addr(addr), + .wdata(wdata), + .wmask(wmask), + .rdata(rdata) + ); +endmodule +module Sram_2048x128 ( + clock, + enable, + write, + addr, + wdata, + wmask, + rdata +); + input clock; + input enable; + input write; + input [10:0] addr; + input [127:0] wdata; + input [15:0] wmask; + output wire [127:0] rdata; + fakeram_512x128 sramModules_0( + .clock(clock), + .enable(enable), + .write(write), + .addr(addr), + .wdata(wdata), + .wmask(wmask), + .rdata(rdata) + ); +endmodule diff --git a/designs/src/NyuziProcessor/LICENSE b/designs/src/coralnpu/LICENSE similarity index 89% rename from designs/src/NyuziProcessor/LICENSE rename to designs/src/coralnpu/LICENSE index 68c771a..7a4a3ea 100644 --- a/designs/src/NyuziProcessor/LICENSE +++ b/designs/src/coralnpu/LICENSE @@ -174,3 +174,29 @@ incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. + END OF TERMS AND CONDITIONS + + APPENDIX: How to apply the Apache License to your work. + + To apply the Apache License to your work, attach the following + boilerplate notice, with the fields enclosed by brackets "[]" + replaced with your own identifying information. (Don't include + the brackets!) The text should be enclosed in the appropriate + comment syntax for the file format. We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/designs/src/coralnpu/dev/Sram_2048x128_REPLACE.v b/designs/src/coralnpu/dev/Sram_2048x128_REPLACE.v new file mode 100644 index 0000000..64498d8 --- /dev/null +++ b/designs/src/coralnpu/dev/Sram_2048x128_REPLACE.v @@ -0,0 +1,19 @@ +module Sram_2048x128( + input clock, + input enable, + input write, + input [10:0] addr, + input [127:0] wdata, + input [15:0] wmask, + output [127:0] rdata +); + fakeram_512x128 sramModules_0( + .clock(clock), + .enable(enable), + .write(write), + .addr(addr), + .wdata(wdata), + .wmask(wmask), + .rdata(rdata) + ); +endmodule diff --git a/designs/src/coralnpu/dev/Sram_512x128_REPLACE.v b/designs/src/coralnpu/dev/Sram_512x128_REPLACE.v new file mode 100644 index 0000000..cd38229 --- /dev/null +++ b/designs/src/coralnpu/dev/Sram_512x128_REPLACE.v @@ -0,0 +1,19 @@ +module Sram_512x128( + input clock, + input enable, + input write, + input [8:0] addr, + input [127:0] wdata, + input [15:0] wmask, + output [127:0] rdata +); + fakeram_512x128 sramModules_0( + .clock(clock), + .enable(enable), + .write(write), + .addr(addr), + .wdata(wdata), + .wmask(wmask), + .rdata(rdata) + ); +endmodule \ No newline at end of file diff --git a/designs/src/coralnpu/dev/install/install_bazel_7_4_1.sh b/designs/src/coralnpu/dev/install/install_bazel_7_4_1.sh new file mode 100644 index 0000000..41092b6 --- /dev/null +++ b/designs/src/coralnpu/dev/install/install_bazel_7_4_1.sh @@ -0,0 +1,81 @@ +#!/usr/bin/env bash +# ============================================================ +# setup_bazel.sh — Install Bazel 7.4.1 locally +# Supports: Linux (x86_64 / arm64) and macOS (x86_64 / arm64) +# ============================================================ + +set -euo pipefail + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" +cd .. +# Set specific bazel version, install dir, and binary location +BAZEL_VERSION="7.4.1" +INSTALL_DIR="$(pwd)/packages" +BAZEL_BIN="${INSTALL_DIR}/bazel" + +# Check for aarch64 or x86_64 architectures (mac/linux) +OS="$(uname -s)" +ARCH="$(uname -m)" + +case "${OS}" in + Linux) + case "${ARCH}" in + x86_64) PLATFORM="linux-x86_64" ;; + aarch64) PLATFORM="linux-arm64" ;; + *) echo "Unsupported Linux arch: ${ARCH}"; exit 1 ;; + esac + ;; + Darwin) + case "${ARCH}" in + x86_64) PLATFORM="darwin-x86_64" ;; + arm64) PLATFORM="darwin-arm64" ;; + *) echo "Unsupported macOS arch: ${ARCH}"; exit 1 ;; + esac + ;; + *) + echo "Unsupported OS: ${OS}" + exit 1 + ;; +esac + +# Set download to download bazel version +DOWNLOAD_URL="https://github.com/bazelbuild/bazel/releases/download/${BAZEL_VERSION}/bazel-${BAZEL_VERSION}-${PLATFORM}" + +echo "============================================" +echo " Bazel ${BAZEL_VERSION} Setup" +echo " Platform : ${PLATFORM}" +echo " Install : ${BAZEL_BIN}" +echo "============================================" + +# Check to see if bazel has already been installed +# check to see if needed bazel version is already being used +# Check if python version is already installed +if [[ -x "${BAZEL_BIN}" ]]; then + echo "Bazel ${BAZEL_VERSION} is already installed at ${BAZEL_BIN}" + exit 0 +fi + + +# Download +echo "" +echo "Downloading ${DOWNLOAD_URL}" +echo "" + + + +if command -v curl &>/dev/null; then + curl -fsSL --progress-bar "${DOWNLOAD_URL}" -o "${BAZEL_BIN}" +elif command -v wget &>/dev/null; then + wget -q --show-progress "${DOWNLOAD_URL}" -O "${BAZEL_BIN}" +else + echo "Neither curl nor wget found. Please install one and retry." + exit 1 +fi + +# make the bin an executable +chmod +x "${BAZEL_BIN}" + +# ensure that download was succesful +echo "" +echo "Done! Run '${INSTALL_DIR}/bazel --version' in the working directory to confirm." diff --git a/designs/src/coralnpu/dev/install/install_py_3_10_9.sh b/designs/src/coralnpu/dev/install/install_py_3_10_9.sh new file mode 100644 index 0000000..508a74f --- /dev/null +++ b/designs/src/coralnpu/dev/install/install_py_3_10_9.sh @@ -0,0 +1,111 @@ +#!/usr/bin/env bash +# ============================================================ +# setup_python.sh — Build & install Python 3.10.9 locally +# Installs into ./python-3.10.9 relative to where you run it +# Supports: Linux (x86_64 / arm64) and macOS (x86_64 / arm64) +# ============================================================ + +set -euo pipefail + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" + +cd .. + +PYTHON_VERSION="3.10.9" +INSTALL_DIR="$(pwd)/packages/python-${PYTHON_VERSION}" +PYTHON_BIN="${INSTALL_DIR}/bin/python3" + +SOURCE_URL="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tgz" +BUILD_DIR="/tmp/python-${PYTHON_VERSION}-build" + +echo "============================================" +echo " Python ${PYTHON_VERSION} Setup" +echo " Install : ${INSTALL_DIR}" +echo "============================================" + +# Check if python version is already installed +if [[ -x "${PYTHON_BIN}" ]]; then + echo "Python ${PYTHON_VERSION} is already installed at ${PYTHON_BIN}" + exit 0 +fi + +# Ensure gcc/make/tar exist for build +echo "" +echo "Checking build dependencies..." + +MISSING=() +for dep in gcc make tar; do + command -v "${dep}" &>/dev/null || MISSING+=("${dep}") +done + +if [[ ${#MISSING[@]} -gt 0 ]]; then + echo "Missing required tools: ${MISSING[*]}" + exit 1 +fi + +# Download py3.10.9 from source +echo "" +echo "Downloading Python ${PYTHON_VERSION} source from ${SOURCE_URL}" +echo "" + +mkdir -p "${BUILD_DIR}" +TARBALL="${BUILD_DIR}/Python-${PYTHON_VERSION}.tgz" + +if command -v curl &>/dev/null; then + curl -fsSL --progress-bar "${SOURCE_URL}" -o "${TARBALL}" +elif command -v wget &>/dev/null; then + wget -q --show-progress "${SOURCE_URL}" -O "${TARBALL}" +else + echo "Neither curl nor wget found (one of these tools is needed for installation)" + echo "Please install and retry" + exit 1 +fi + +# Extract stage +echo "" +echo "Extracting..." +tar -xzf "${TARBALL}" -C "${BUILD_DIR}" + +# Config stage +echo "" +echo "Configuring (this may take a moment)..." +cd "${BUILD_DIR}/Python-${PYTHON_VERSION}" + +./configure \ + --prefix="${INSTALL_DIR}" \ + --enable-optimizations \ + --with-ensurepip=install \ + --quiet + +# Build for py_3.10.9 +echo "" +echo "Building Python ${PYTHON_VERSION}..." +echo "" + +unset MAKEFLAGS MFLAGS MAKELEVEL + +JOBS="$(getconf _NPROCESSORS_ONLN 2>/dev/null || echo 2)" +make -j"${JOBS}" LDFLAGS="-lgcov" --quiet + +echo "" +echo "Installing to ${INSTALL_DIR}..." +make install --quiet + +# Verify that we've correctly installed py_3.10.9 +echo "" +echo "Verifying installation..." +INSTALLED_VERSION="$("${PYTHON_BIN}" --version 2>&1 | awk '{print $2}')" +if [[ "${INSTALLED_VERSION}" == "${PYTHON_VERSION}" ]]; then + echo "Python ${INSTALLED_VERSION} installed successfully!" +else + echo "Version mismatch — expected ${PYTHON_VERSION}, got ${INSTALLED_VERSION}" + exit 1 +fi + +# Remove build directory +echo "" +echo "Cleaning up build files..." +rm -rf "${BUILD_DIR}" + +echo "Done! Run '${INSTALL_DIR}/bin/python3 --version' to confirm." diff --git a/designs/src/coralnpu/dev/install/install_srecord.sh b/designs/src/coralnpu/dev/install/install_srecord.sh new file mode 100644 index 0000000..e3a7864 --- /dev/null +++ b/designs/src/coralnpu/dev/install/install_srecord.sh @@ -0,0 +1,152 @@ +#!/usr/bin/env bash +# ============================================================ +# setup_srecord.sh — Build & install SRecord 1.65 locally +# Installs into ./srecord relative to where you run it +# Supports: Linux (x86_64 / arm64) and macOS (x86_64 / arm64) +# ============================================================ + +set -euo pipefail + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" + +cd .. + +SRECORD_VERSION="1.65" +SRECORD_NAME="1.65.0-Linux" +INSTALL_DIR="$(pwd)/packages/srecord" +BUILD_DIR="$(pwd)/srecord-build" + +SOURCE_URL="https://sourceforge.net/projects/srecord/files/srecord/${SRECORD_VERSION}/srecord-${SRECORD_NAME}.tar.gz/download" +TARBALL_NAME="srecord-${SRECORD_VERSION}.tar.gz" + +echo "============================================" +echo " SRecord ${SRECORD_VERSION} Setup" +echo " Install : ${INSTALL_DIR}" +echo "============================================" + +# Check if install already exists +if [[ -x "${INSTALL_DIR}/bin/srec_cat" ]]; then + echo "SRecord already installed at ${INSTALL_DIR}/bin/" + exit 0 +fi + +# Check OS +OS="$(uname -s)" + +# Ensure required dependencies exist +echo "" +echo "Checking build dependencies..." + +MISSING=() +for dep in cmake g++ make tar; do + command -v "${dep}" &>/dev/null || MISSING+=("${dep}") +done + +if [[ ${#MISSING[@]} -gt 0 ]]; then + echo "Missing required tools: ${MISSING[*]}" + exit 1 +fi + +echo "Done." + +# Source Download +echo "" +echo "Downloading SRecord (${SRECORD_VERSION}) from ${SOURCE_URL}" +echo "" + +mkdir -p "${BUILD_DIR}" +TARBALL="${BUILD_DIR}/${TARBALL_NAME}" + +if command -v curl &>/dev/null; then + curl -fsSL --progress-bar -L "${SOURCE_URL}" -o "${TARBALL}" +elif command -v wget &>/dev/null; then + wget -q --show-progress "${SOURCE_URL}" -O "${TARBALL}" +else + echo "Neither curl nor wget found." + exit 1 +fi + +# Extract tarball +echo "Extracting..." +tar -xzf "${TARBALL}" -C "${BUILD_DIR}" + +SOURCE_DIR="$(find "${BUILD_DIR}" -maxdepth 1 -mindepth 1 -type d | head -n 1)" +if [[ -z "${SOURCE_DIR}" ]]; then + echo "Could not find extracted source directory in ${BUILD_DIR}" + exit 1 +fi +echo " Source dir: ${SOURCE_DIR}" + +# Config/Build/Install stage +if [[ -f "${SOURCE_DIR}/CMakeLists.txt" ]]; then + + CMAKE_BUILD_DIR="${BUILD_DIR}/cmake-build" + mkdir -p "${CMAKE_BUILD_DIR}" + + # Config + echo "" + echo "Configuring with CMake..." + cmake -S "${SOURCE_DIR}" \ + -B "${CMAKE_BUILD_DIR}" \ + -DCMAKE_INSTALL_PREFIX="${INSTALL_DIR}" \ + -DCMAKE_BUILD_TYPE=Release \ + -Wno-dev \ + --no-warn-unused-cli \ + -DCMAKE_INSTALL_RPATH_USE_LINK_PATH=ON \ + -DCMAKE_POSITION_INDEPENDENT_CODE=ON + + # Build + echo "" + echo "Building SRecord ${SRECORD_VERSION}..." + echo "" + JOBS="$(getconf _NPROCESSORS_ONLN 2>/dev/null || echo 2)" + cmake --build "${CMAKE_BUILD_DIR}" --parallel "${JOBS}" + + # Install + echo "" + echo "Installing to ${INSTALL_DIR}..." + cmake --install "${CMAKE_BUILD_DIR}" + +else + # Pre-built binary tarball, only file install needed + echo "" + echo "Pre-built binary detected, copying files to ${INSTALL_DIR}..." + mkdir -p "${INSTALL_DIR}" + cp -r "${SOURCE_DIR}/." "${INSTALL_DIR}/" + # Ensure binaries are executable + find "${INSTALL_DIR}/bin" -type f -exec chmod +x {} \; 2>/dev/null || \ + find "${INSTALL_DIR}" -maxdepth 1 -type f -name "srec_*" -exec chmod +x {} \; +fi + +# Verify installation was succesful +echo "" +echo "Verifying installation..." + +BINS=("srec_cat" "srec_cmp" "srec_info") +ALL_OK=true + +for bin in "${BINS[@]}"; do + # Check both ./bin/ and ./ + if [[ -x "${INSTALL_DIR}/bin/${bin}" ]]; then + echo " ${bin} → ${INSTALL_DIR}/bin/${bin}" + elif [[ -x "${INSTALL_DIR}/${bin}" ]]; then + echo " ${bin} → ${INSTALL_DIR}/${bin}" + else + echo " ${bin} not found under ${INSTALL_DIR}" + ALL_OK=false + fi +done + +if [[ "${ALL_OK}" != "true" ]]; then + echo "" + echo "Binaries are missing, the build failed." + exit 1 +fi + +# Clean SRecord build files +echo "" +echo "Cleaning up build files..." +rm -rf "${BUILD_DIR}" + +echo "Done! SRecord bin files have been installed to ${INSTALL_DIR}/bin." diff --git a/designs/src/NyuziProcessor/dev/setup.sh b/designs/src/coralnpu/dev/install/install_sv2v.sh similarity index 78% rename from designs/src/NyuziProcessor/dev/setup.sh rename to designs/src/coralnpu/dev/install/install_sv2v.sh index f929bcb..28e8052 100644 --- a/designs/src/NyuziProcessor/dev/setup.sh +++ b/designs/src/coralnpu/dev/install/install_sv2v.sh @@ -1,14 +1,14 @@ #!/usr/bin/bash # Using OpenROAD-flow-scripts/build_openroad.sh as a template -set -eu +set -euo pipefail DIR="$(dirname $(readlink -f $0))" cd "$DIR" +cd .. -INSTALL_PATH="$(pwd)" - +INSTALL_PATH="$(pwd)/packages/" PROC=-1 @@ -76,7 +76,7 @@ if [[ "$PROC" == "-1" ]]; then PROC=$(sysctl -n hw.ncpu) else cat << EOF -[WARNING FLW-0025] Unsupported OSTYPE: cannot determine number of host CPUs" +Unsupported OS: cannot determine number of host CPUs" Defaulting to 2 threads. Use --threads N to use N threads" EOF PROC=2 @@ -102,22 +102,16 @@ if [ ! -z "${CLEAN_BEFORE+x}" ]; then fi # Check if sv2v exists already (and set up if not) -if [ ! -f "./sv2v" ]; then - echo "A local sv2v installation doesn't exist. Cloning and building..." - rm -rf sv2v_main - git clone https://github.com/zachjs/sv2v.git sv2v_main - # Download haskell stack locally - curl -sSL https://get.haskellstack.org/ | sh -s - -d $(pwd)/sv2v_main - cd sv2v_main - # Change default STACK_ROOT dir from ~/.stack to the current dir - export STACK_ROOT=$(pwd)/sv2v_main - ./stack setup - ./stack build - cp "$(./stack path --local-install-root)/bin/sv2v" ../sv2v - cd .. - rm -rf sv2v_main - echo "Local sv2v build completed!" +if [ ! -f "${INSTALL_PATH}/sv2v" ]; then + echo "sv2v not found. Downloading prebuilt binary..." + SV2V_ZIP="sv2v-Linux.zip" + curl -sSL -o "$SV2V_ZIP" \ + "https://github.com/zachjs/sv2v/releases/download/v0.0.13/sv2v-Linux.zip" + unzip -o "$SV2V_ZIP" -d sv2v_extract + cp sv2v_extract/sv2v-Linux/sv2v "${INSTALL_PATH}/sv2v" + chmod +x "${INSTALL_PATH}/sv2v" + rm -rf "$SV2V_ZIP" sv2v_extract + echo "sv2v binary downloaded successfully!" else echo "sv2v already present in directory" fi - diff --git a/designs/src/coralnpu/dev/repo b/designs/src/coralnpu/dev/repo new file mode 160000 index 0000000..7731fd6 --- /dev/null +++ b/designs/src/coralnpu/dev/repo @@ -0,0 +1 @@ +Subproject commit 7731fd6e70ac9a288097dcdad2253c4974deff88 diff --git a/designs/src/coralnpu/dev/setup.sh b/designs/src/coralnpu/dev/setup.sh new file mode 100644 index 0000000..31bb3d8 --- /dev/null +++ b/designs/src/coralnpu/dev/setup.sh @@ -0,0 +1,124 @@ +#!/usr/bin/env bash + +set -euo pipefail + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" + +mkdir -p packages + +# Prerequisite Setup +bash "$(pwd)/install/install_bazel_7_4_1.sh" +bash "$(pwd)/install/install_py_3_10_9.sh" +bash "$(pwd)/install/install_srecord.sh" +bash "$(pwd)/install/install_sv2v.sh" + +# Copy black-boxed SRAM to replace existing memories before chisel generation +cp "$(pwd)/Sram_512x128_REPLACE.v" "$(pwd)/repo/hdl/verilog/Sram_512x128.v" +cp "$(pwd)/Sram_2048x128_REPLACE.v" "$(pwd)/repo/hdl/verilog/Sram_2048x128.v" + +# Generate Source SystemVerilog from chisel +cd "$(pwd)/repo/" + +# Bazel requires a user for its state +export USER=${USER:-no_user} +if [ "$HOME" = "/" ]; then + HOME=/tmp/ +fi + + +"./../packages/bazel" \ + --output_base=/tmp/bazel_root \ + --install_base=/tmp/bazel_install \ + build \ + --action_env=JAVA_TOOL_OPTIONS="-Duser.home=/tmp" \ + //hdl/chisel/src/coralnpu:core_mini_axi_cc_library_emit_verilog + +cd .. + +# Generate Verilog from generated SV +"$(pwd)/packages/sv2v" -D SYNTHESIS -D layers_CoreMiniAxi_Verification_Assert -D VERILATOR "$(pwd)/repo/bazel-bin/hdl/chisel/src/coralnpu/CoreMiniAxi.sv" > "$(pwd)/../CoreMiniAxi.v" + + +# Remove debug/slog logic and any conditions that they belong in (not necessary for non-validation silicon) +perl -i -0777 -pe ' +sub body_is_debug_slog_only { + my ($body) = @_; + + # strip comments + $body =~ s{/\*.*?\*/}{}gs; + $body =~ s{//[^\n]*}{}g; + + for my $line (split /\n/, $body) { + $line =~ s/^\s+|\s+$//g; + next if $line eq ""; + return 0 unless $line =~ /(debug|slog)/; # substring match + } + return 1; +} + +sub strip_blocks { + my ($s, $hdr_re) = @_; + my $out = ""; + pos($s) = 0; + + while ($s =~ /\G(.*?)(($hdr_re))/sgc) { + $out .= $1; + + my $hdr = $2; + my $start = pos($s) - length($hdr); + my $i = pos($s); + + # header ends with "begin" so we are inside a begin/end region + my $depth = 1; + while ($depth > 0 && $s =~ /\G(.*?)(\bbegin\b|\bend\b)/sgc) { + $depth++ if $2 eq "begin"; + $depth-- if $2 eq "end"; + $i = pos($s); + } + + my $blk = substr($s, $start, $i - $start); + my $body = $blk; + $body =~ s/^.*?\bbegin\b//s; + $body =~ s/\bend\b\s*$//s; + + if (body_is_debug_slog_only($body)) { + # drop whole block (including optional leading "initial") + } else { + $out .= $blk; + } + + pos($s) = $i; + } + + $out .= substr($s, pos($s) // 0); + return $out; +} + +# optional "initial" before if/else +my $PFX = qr/(?:\binitial\b\s*)?/s; + +$_ = strip_blocks($_, qr/${PFX}\bif\s*\(.*?\)\s*begin\b/s); +$_ = strip_blocks($_, qr/${PFX}\belse\s*begin\b/s); +' "$(pwd)/../CoreMiniAxi.v" + +# Parse empty always blocks after removing debug logic +perl -i -0777 -pe ' + 1 while s{ + ^([ \t]*)always\s*@\s*\([^)]*\)\s*\r?\n + (?: + [ \t]*\r?\n + | [ \t]*//[^\n]*\r?\n + | [ \t]*/\*.*?\*/[ \t]*\r?\n + )+ + (?=^[ \t]*\S|\z) + }{}gmsx; +' "$(pwd)/../CoreMiniAxi.v" + +# Remove display/finish tasks +perl -i -0777 -pe ' + s/^[ \t]*\$(?:display|finish)\b.*?\);\s*\r?\n//gms; +' "$(pwd)/../CoreMiniAxi.v" + +sed -i '/debug/d' "$(pwd)/../CoreMiniAxi.v" +sed -i '/slog/d' "$(pwd)/../CoreMiniAxi.v" diff --git a/designs/src/coralnpu/macros.v b/designs/src/coralnpu/macros.v new file mode 100644 index 0000000..f0bb649 --- /dev/null +++ b/designs/src/coralnpu/macros.v @@ -0,0 +1,60 @@ +module fakeram_2048x128( + clock, + enable, + addr, + rdata, + write, + wdata, + wmask +); + parameter DATA_WIDTH = 2048; + parameter SIZE = 128; + parameter READ_DURING_WRITE = "NEW_DATA"; + parameter ADDR_WIDTH = $clog2(SIZE); + input clock; + input enable; + input [ADDR_WIDTH - 1:0] addr; + input [15:0] wmask; + output reg [DATA_WIDTH - 1:0] rdata; + input write; + input [DATA_WIDTH - 1:0] wdata; + fakeram_2048x128_1rw sram ( + .rw0_clk (clock), + .rw0_rd_out (rdata), + .rw0_addr_in (addr), + .rw0_we_in (write), + .rw0_wd_in (wdata), + .rw0_ce_in (enable), + .rw0_wmask_in (wmask) + ); +endmodule +module fakeram_512x128( + clock, + enable, + addr, + rdata, + write, + wdata, + wmask +); + parameter DATA_WIDTH = 512; + parameter SIZE = 128; + parameter READ_DURING_WRITE = "NEW_DATA"; + parameter ADDR_WIDTH = $clog2(SIZE); + input clock; + input enable; + input [ADDR_WIDTH - 1:0] addr; + input [15:0] wmask; + output reg [DATA_WIDTH - 1:0] rdata; + input write; + input [DATA_WIDTH - 1:0] wdata; + fakeram_512x128_1rw sram ( + .rw0_clk (clock), + .rw0_rd_out (rdata), + .rw0_addr_in (addr), + .rw0_we_in (write), + .rw0_wd_in (wdata), + .rw0_ce_in (enable), + .rw0_wmask_in (wmask) + ); +endmodule \ No newline at end of file diff --git a/designs/src/coralnpu/verilog.mk b/designs/src/coralnpu/verilog.mk new file mode 100644 index 0000000..6a62ed4 --- /dev/null +++ b/designs/src/coralnpu/verilog.mk @@ -0,0 +1,8 @@ +export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/coralnpu/CoreMiniAxi.v \ + $(BENCH_DESIGN_HOME)/src/coralnpu/macros.v + +export ADDITIONAL_LEFS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/coralnpu/sram/lef/fakeram_512x128_1rw.lef \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/coralnpu/sram/lef/fakeram_2048x128_1rw.lef + +export ADDITIONAL_LIBS = $(BENCH_DESIGN_HOME)/$(PLATFORM)/coralnpu/sram/lib/fakeram_512x128_1rw.lib \ + $(BENCH_DESIGN_HOME)/$(PLATFORM)/coralnpu/sram/lib/fakeram_2048x128_1rw.lib \ No newline at end of file diff --git a/designs/src/gemmini/verilog.mk b/designs/src/gemmini/verilog.mk index bda6d89..66936a2 100644 --- a/designs/src/gemmini/verilog.mk +++ b/designs/src/gemmini/verilog.mk @@ -6,11 +6,7 @@ GEMMINI_RELEASE_RTL := $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v # Allow clean_design to prune dev-generated artifacts when desired. export DEV_SRC := $(GEMMINI_DEV_DIR)/generated -ifneq ($(wildcard $(DEV_FLAG)),) -$(GEMMINI_DEV_RTL): $(GEMMINI_DEV_DIR)/setup.sh - @echo "Generating Gemmini RTL via setup.sh" - @cd $(GEMMINI_DEV_DIR) && bash setup.sh - +ifeq ($(DO_UPDATE),1) export VERILOG_FILES = $(GEMMINI_DEV_RTL) else # Prefer checked-in RTL; fall back to dev output if it has not been promoted yet. diff --git a/designs/src/lfsr_prbs_gen/LICENSE b/designs/src/lfsr_prbs_gen/LICENSE deleted file mode 100644 index 1b8f1ce..0000000 --- a/designs/src/lfsr_prbs_gen/LICENSE +++ /dev/null @@ -1,19 +0,0 @@ -Copyright (c) 2016 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. diff --git a/designs/src/lfsr_prbs_gen/dev/repo b/designs/src/lfsr_prbs_gen/dev/repo deleted file mode 160000 index c1f86d0..0000000 --- a/designs/src/lfsr_prbs_gen/dev/repo +++ /dev/null @@ -1 +0,0 @@ -Subproject commit c1f86d036745935f3812ec6ddc7821c70ef4c9de diff --git a/designs/src/lfsr_prbs_gen/dev/setup.sh b/designs/src/lfsr_prbs_gen/dev/setup.sh deleted file mode 100644 index 3e2aea0..0000000 --- a/designs/src/lfsr_prbs_gen/dev/setup.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/bash - -# Add any customization of the design submodule here. diff --git a/designs/src/lfsr_prbs_gen/lfsr.v b/designs/src/lfsr_prbs_gen/lfsr.v deleted file mode 100644 index e3a472e..0000000 --- a/designs/src/lfsr_prbs_gen/lfsr.v +++ /dev/null @@ -1,447 +0,0 @@ -/* - -Copyright (c) 2016-2023 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Parametrizable combinatorial parallel LFSR/CRC - */ -module lfsr # -( - // width of LFSR - parameter LFSR_WIDTH = 31, - // LFSR polynomial - parameter LFSR_POLY = 31'h10000001, - // LFSR configuration: "GALOIS", "FIBONACCI" - parameter LFSR_CONFIG = "FIBONACCI", - // LFSR feed forward enable - parameter LFSR_FEED_FORWARD = 0, - // bit-reverse input and output - parameter REVERSE = 0, - // width of data input - parameter DATA_WIDTH = 8, - // implementation style: "AUTO", "LOOP", "REDUCTION" - parameter STYLE = "AUTO" -) -( - input wire [DATA_WIDTH-1:0] data_in, - input wire [LFSR_WIDTH-1:0] state_in, - output wire [DATA_WIDTH-1:0] data_out, - output wire [LFSR_WIDTH-1:0] state_out -); - -/* - -Fully parametrizable combinatorial parallel LFSR/CRC module. Implements an unrolled LFSR -next state computation, shifting DATA_WIDTH bits per pass through the module. Input data -is XORed with LFSR feedback path, tie data_in to zero if this is not required. - -Works in two parts: statically computes a set of bit masks, then uses these bit masks to -select bits for XORing to compute the next state. - -Ports: - -data_in - -Data bits to be shifted through the LFSR (DATA_WIDTH bits) - -state_in - -LFSR/CRC current state input (LFSR_WIDTH bits) - -data_out - -Data bits shifted out of LFSR (DATA_WIDTH bits) - -state_out - -LFSR/CRC next state output (LFSR_WIDTH bits) - -Parameters: - -LFSR_WIDTH - -Specify width of LFSR/CRC register - -LFSR_POLY - -Specify the LFSR/CRC polynomial in hex format. For example, the polynomial - -x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 - -would be represented as - -32'h04c11db7 - -Note that the largest term (x^32) is suppressed. This term is generated automatically based -on LFSR_WIDTH. - -LFSR_CONFIG - -Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used -for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators, -scramblers, and descrambers, while Galois is generally used for cyclic redundancy check -generators and checkers. - -Fibonacci style (example for 64b66b scrambler, 0x8000000001) - - DIN (LSB first) - | - V - (+)<---------------------------(+)<-----------------------------. - | ^ | - | .----. .----. .----. | .----. .----. .----. | - +->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--' - | '----' '----' '----' '----' '----' '----' - V - DOUT - -Galois style (example for CRC16, 0x8005) - - ,-------------------+-------------------------+----------(+)<-- DIN (MSB first) - | | | ^ - | .----. .----. V .----. .----. V .----. | - `->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT - '----' '----' '----' '----' '----' - -LFSR_FEED_FORWARD - -Generate feed forward instead of feed back LFSR. Enable this for PRBS checking and self- -synchronous descrambling. - -Fibonacci feed-forward style (example for 64b66b descrambler, 0x8000000001) - - DIN (LSB first) - | - | .----. .----. .----. .----. .----. .----. - +->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--. - | '----' '----' '----' | '----' '----' '----' | - | V | - (+)<---------------------------(+)------------------------------' - | - V - DOUT - -Galois feed-forward style - - ,-------------------+-------------------------+------------+--- DIN (MSB first) - | | | | - | .----. .----. V .----. .----. V .----. V - `->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |->(+)-> DOUT - '----' '----' '----' '----' '----' - -REVERSE - -Bit-reverse LFSR input and output. Shifts MSB first by default, set REVERSE for LSB first. - -DATA_WIDTH - -Specify width of input and output data bus. The module will perform one shift per input -data bit, so if the input data bus is not required tie data_in to zero and set DATA_WIDTH -to the required number of shifts per clock cycle. - -STYLE - -Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO" -is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate -directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate -and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog -reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction -operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in -Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing -problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO" -will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey -synthesis translate directives. - -Settings for common LFSR/CRC implementations: - -Name Configuration Length Polynomial Initial value Notes -CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff -CRC16-CCITT Galois 16 16'h1021 16'h1d0f -CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output -CRC32C Galois, bit-reverse 32 32'h1edc6f41 32'hffffffff iSCSI, Intel CRC32 instruction; invert final output -PRBS6 Fibonacci 6 6'h21 any -PRBS7 Fibonacci 7 7'h41 any -PRBS9 Fibonacci 9 9'h021 any ITU V.52 -PRBS10 Fibonacci 10 10'h081 any ITU -PRBS11 Fibonacci 11 11'h201 any ITU O.152 -PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152 -PRBS17 Fibonacci 17 17'h04001 any -PRBS20 Fibonacci 20 20'h00009 any ITU V.57 -PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151 -PRBS29 Fibonacci, inverted 29 29'h08000001 any -PRBS31 Fibonacci, inverted 31 31'h10000001 any -64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet -128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3 - -*/ - -function [LFSR_WIDTH+DATA_WIDTH-1:0] lfsr_mask(input [31:0] index); - reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0]; - reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0]; - reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0]; - reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0]; - - reg [LFSR_WIDTH-1:0] state_val; - reg [DATA_WIDTH-1:0] data_val; - - reg [DATA_WIDTH-1:0] data_mask; - - integer i, j; - - begin - // init bit masks - for (i = 0; i < LFSR_WIDTH; i = i + 1) begin - lfsr_mask_state[i] = 0; - lfsr_mask_state[i][i] = 1'b1; - lfsr_mask_data[i] = 0; - end - for (i = 0; i < DATA_WIDTH; i = i + 1) begin - output_mask_state[i] = 0; - if (i < LFSR_WIDTH) begin - output_mask_state[i][i] = 1'b1; - end - output_mask_data[i] = 0; - end - - // simulate shift register - if (LFSR_CONFIG == "FIBONACCI") begin - // Fibonacci configuration - for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin - // determine shift in value - // current value in last FF, XOR with input data bit (MSB first) - state_val = lfsr_mask_state[LFSR_WIDTH-1]; - data_val = lfsr_mask_data[LFSR_WIDTH-1]; - data_val = data_val ^ data_mask; - - // add XOR inputs from correct indicies - for (j = 1; j < LFSR_WIDTH; j = j + 1) begin - if ((LFSR_POLY >> j) & 1) begin - state_val = lfsr_mask_state[j-1] ^ state_val; - data_val = lfsr_mask_data[j-1] ^ data_val; - end - end - - // shift - for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin - lfsr_mask_state[j] = lfsr_mask_state[j-1]; - lfsr_mask_data[j] = lfsr_mask_data[j-1]; - end - for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin - output_mask_state[j] = output_mask_state[j-1]; - output_mask_data[j] = output_mask_data[j-1]; - end - output_mask_state[0] = state_val; - output_mask_data[0] = data_val; - if (LFSR_FEED_FORWARD) begin - // only shift in new input data - state_val = {LFSR_WIDTH{1'b0}}; - data_val = data_mask; - end - lfsr_mask_state[0] = state_val; - lfsr_mask_data[0] = data_val; - end - end else if (LFSR_CONFIG == "GALOIS") begin - // Galois configuration - for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin - // determine shift in value - // current value in last FF, XOR with input data bit (MSB first) - state_val = lfsr_mask_state[LFSR_WIDTH-1]; - data_val = lfsr_mask_data[LFSR_WIDTH-1]; - data_val = data_val ^ data_mask; - - // shift - for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin - lfsr_mask_state[j] = lfsr_mask_state[j-1]; - lfsr_mask_data[j] = lfsr_mask_data[j-1]; - end - for (j = DATA_WIDTH-1; j > 0; j = j - 1) begin - output_mask_state[j] = output_mask_state[j-1]; - output_mask_data[j] = output_mask_data[j-1]; - end - output_mask_state[0] = state_val; - output_mask_data[0] = data_val; - if (LFSR_FEED_FORWARD) begin - // only shift in new input data - state_val = {LFSR_WIDTH{1'b0}}; - data_val = data_mask; - end - lfsr_mask_state[0] = state_val; - lfsr_mask_data[0] = data_val; - - // add XOR inputs at correct indicies - for (j = 1; j < LFSR_WIDTH; j = j + 1) begin - if ((LFSR_POLY >> j) & 1) begin - lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val; - lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val; - end - end - end - end else begin - $error("Error: unknown configuration setting!"); - $finish; - end - - // reverse bits if selected - if (REVERSE) begin - if (index < LFSR_WIDTH) begin - state_val = 0; - for (i = 0; i < LFSR_WIDTH; i = i + 1) begin - state_val[i] = lfsr_mask_state[LFSR_WIDTH-index-1][LFSR_WIDTH-i-1]; - end - - data_val = 0; - for (i = 0; i < DATA_WIDTH; i = i + 1) begin - data_val[i] = lfsr_mask_data[LFSR_WIDTH-index-1][DATA_WIDTH-i-1]; - end - end else begin - state_val = 0; - for (i = 0; i < LFSR_WIDTH; i = i + 1) begin - state_val[i] = output_mask_state[DATA_WIDTH-(index-LFSR_WIDTH)-1][LFSR_WIDTH-i-1]; - end - - data_val = 0; - for (i = 0; i < DATA_WIDTH; i = i + 1) begin - data_val[i] = output_mask_data[DATA_WIDTH-(index-LFSR_WIDTH)-1][DATA_WIDTH-i-1]; - end - end - end else begin - if (index < LFSR_WIDTH) begin - state_val = lfsr_mask_state[index]; - data_val = lfsr_mask_data[index]; - end else begin - state_val = output_mask_state[index-LFSR_WIDTH]; - data_val = output_mask_data[index-LFSR_WIDTH]; - end - end - lfsr_mask = {data_val, state_val}; - end -endfunction - -// synthesis translate_off -`define SIMULATION -// synthesis translate_on - -`ifdef SIMULATION -// "AUTO" style is "REDUCTION" for faster simulation -parameter STYLE_INT = (STYLE == "AUTO") ? "REDUCTION" : STYLE; -`else -// "AUTO" style is "LOOP" for better synthesis result -parameter STYLE_INT = (STYLE == "AUTO") ? "LOOP" : STYLE; -`endif - -genvar n; - -generate - -if (STYLE_INT == "REDUCTION") begin - - // use Verilog reduction operator - // fast in iverilog - // significantly larger than generated code with ISE (inferred wide XORs may be tripping up optimizer) - // slightly smaller than generated code with Quartus - // --> better for simulation - - for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state - wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n); - assign state_out[n] = ^({data_in, state_in} & mask); - end - for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data - wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH); - assign data_out[n] = ^({data_in, state_in} & mask); - end - -end else if (STYLE_INT == "LOOP") begin - - // use nested loops - // very slow in iverilog - // slightly smaller than generated code with ISE - // same size as generated code with Quartus - // --> better for synthesis - - for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state - wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n); - - reg state_reg; - - assign state_out[n] = state_reg; - - integer i; - - always @* begin - state_reg = 1'b0; - for (i = 0; i < LFSR_WIDTH; i = i + 1) begin - if (mask[i]) begin - state_reg = state_reg ^ state_in[i]; - end - end - for (i = 0; i < DATA_WIDTH; i = i + 1) begin - if (mask[i+LFSR_WIDTH]) begin - state_reg = state_reg ^ data_in[i]; - end - end - end - end - for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data - wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH); - - reg data_reg; - - assign data_out[n] = data_reg; - - integer i; - - always @* begin - data_reg = 1'b0; - for (i = 0; i < LFSR_WIDTH; i = i + 1) begin - if (mask[i]) begin - data_reg = data_reg ^ state_in[i]; - end - end - for (i = 0; i < DATA_WIDTH; i = i + 1) begin - if (mask[i+LFSR_WIDTH]) begin - data_reg = data_reg ^ data_in[i]; - end - end - end - end - -end else begin - - initial begin - $error("Error: unknown style setting!"); - $finish; - end - -end - -endgenerate - -endmodule - -`resetall diff --git a/designs/src/lfsr_prbs_gen/lfsr_prbs_check.v b/designs/src/lfsr_prbs_gen/lfsr_prbs_check.v deleted file mode 100644 index c48a293..0000000 --- a/designs/src/lfsr_prbs_gen/lfsr_prbs_check.v +++ /dev/null @@ -1,222 +0,0 @@ -/* - -Copyright (c) 2016 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * LFSR PRBS checker - */ -module lfsr_prbs_check # -( - // width of LFSR - parameter LFSR_WIDTH = 31, - // LFSR polynomial - parameter LFSR_POLY = 31'h10000001, - // Initial state - parameter LFSR_INIT = {LFSR_WIDTH{1'b1}}, - // LFSR configuration: "GALOIS", "FIBONACCI" - parameter LFSR_CONFIG = "FIBONACCI", - // bit-reverse input and output - parameter REVERSE = 0, - // invert input - parameter INVERT = 1, - // width of data input and output - parameter DATA_WIDTH = 8, - // implementation style: "AUTO", "LOOP", "REDUCTION" - parameter STYLE = "AUTO" -) -( - input wire clk, - input wire rst, - input wire [DATA_WIDTH-1:0] data_in, - input wire data_in_valid, - output wire [DATA_WIDTH-1:0] data_out -); - -/* - -Fully parametrizable combinatorial parallel LFSR PRBS checker. Implements an unrolled LFSR -PRBS checker. - -Ports: - -clk - -Clock input - -rst - -Reset input, set state to LFSR_INIT - -data_in - -PRBS data input (DATA_WIDTH bits) - -data_in_valid - -Shift input data through LFSR when asserted - -data_out - -Error output (DATA_WIDTH bits) - -Parameters: - -LFSR_WIDTH - -Specify width of LFSR/CRC register - -LFSR_POLY - -Specify the LFSR/CRC polynomial in hex format. For example, the polynomial - -x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 - -would be represented as - -32'h04c11db7 - -Note that the largest term (x^32) is suppressed. This term is generated automatically based -on LFSR_WIDTH. - -LFSR_INIT - -Initial state of LFSR. Defaults to all 1s. - -LFSR_CONFIG - -Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used -for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators, -scramblers, and descrambers, while Galois is generally used for cyclic redundancy check -generators and checkers. - -Fibonacci style (example for 64b66b scrambler, 0x8000000001) - - DIN (LSB first) - | - V - (+)<---------------------------(+)<-----------------------------. - | ^ | - | .----. .----. .----. | .----. .----. .----. | - +->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--' - | '----' '----' '----' '----' '----' '----' - V - DOUT - -Galois style (example for CRC16, 0x8005) - - ,-------------------+-------------------------+----------(+)<-- DIN (MSB first) - | | | ^ - | .----. .----. V .----. .----. V .----. | - `->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT - '----' '----' '----' '----' '----' - -REVERSE - -Bit-reverse LFSR output. Shifts MSB first by default, set REVERSE for LSB first. - -INVERT - -Bitwise invert PRBS input. - -DATA_WIDTH - -Specify width of output data bus. - -STYLE - -Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO" -is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate -directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate -and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog -reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction -operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in -Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing -problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO" -will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey -synthesis translate directives. - -Settings for common LFSR/CRC implementations: - -Name Configuration Length Polynomial Initial value Notes -CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output -PRBS6 Fibonacci 6 6'h21 any -PRBS7 Fibonacci 7 7'h41 any -PRBS9 Fibonacci 9 9'h021 any ITU V.52 -PRBS10 Fibonacci 10 10'h081 any ITU -PRBS11 Fibonacci 11 11'h201 any ITU O.152 -PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152 -PRBS17 Fibonacci 17 17'h04001 any -PRBS20 Fibonacci 20 20'h00009 any ITU V.57 -PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151 -PRBS29 Fibonacci, inverted 29 29'h08000001 any -PRBS31 Fibonacci, inverted 31 31'h10000001 any -64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet -128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3 - -*/ - -reg [LFSR_WIDTH-1:0] state_reg = LFSR_INIT; -reg [DATA_WIDTH-1:0] output_reg = 0; - -wire [DATA_WIDTH-1:0] lfsr_data; -wire [LFSR_WIDTH-1:0] lfsr_state; - -assign data_out = output_reg; - -lfsr #( - .LFSR_WIDTH(LFSR_WIDTH), - .LFSR_POLY(LFSR_POLY), - .LFSR_CONFIG(LFSR_CONFIG), - .LFSR_FEED_FORWARD(1), - .REVERSE(REVERSE), - .DATA_WIDTH(DATA_WIDTH), - .STYLE(STYLE) -) -lfsr_inst ( - .data_in(INVERT ? ~data_in : data_in), - .state_in(state_reg), - .data_out(lfsr_data), - .state_out(lfsr_state) -); - -always @(posedge clk) begin - if (rst) begin - state_reg <= LFSR_INIT; - output_reg <= 0; - end else begin - if (data_in_valid) begin - state_reg <= lfsr_state; - output_reg <= lfsr_data; - end - end -end - -endmodule - -`resetall diff --git a/designs/src/lfsr_prbs_gen/lfsr_prbs_gen.v b/designs/src/lfsr_prbs_gen/lfsr_prbs_gen.v deleted file mode 100644 index 89d273c..0000000 --- a/designs/src/lfsr_prbs_gen/lfsr_prbs_gen.v +++ /dev/null @@ -1,223 +0,0 @@ -/* - -Copyright (c) 2016 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * LFSR PRBS generator - */ -module lfsr_prbs_gen # -( - // width of LFSR - parameter LFSR_WIDTH = 31, - // LFSR polynomial - parameter LFSR_POLY = 31'h10000001, - // Initial state - parameter LFSR_INIT = {LFSR_WIDTH{1'b1}}, - // LFSR configuration: "GALOIS", "FIBONACCI" - parameter LFSR_CONFIG = "FIBONACCI", - // bit-reverse input and output - parameter REVERSE = 0, - // invert output - parameter INVERT = 1, - // width of data output - parameter DATA_WIDTH = 8, - // implementation style: "AUTO", "LOOP", "REDUCTION" - parameter STYLE = "AUTO" -) -( - input wire clk, - input wire rst, - input wire enable, - output wire [DATA_WIDTH-1:0] data_out -); - -/* - -Fully parametrizable combinatorial parallel LFSR PRBS module. Implements an unrolled LFSR -next state computation. - -Ports: - -clk - -Clock input - -rst - -Reset input, set state to LFSR_INIT - -enable - -Generate new output data - -data_out - -LFSR output (DATA_WIDTH bits) - -Parameters: - -LFSR_WIDTH - -Specify width of LFSR/CRC register - -LFSR_POLY - -Specify the LFSR/CRC polynomial in hex format. For example, the polynomial - -x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1 - -would be represented as - -32'h04c11db7 - -Note that the largest term (x^32) is suppressed. This term is generated automatically based -on LFSR_WIDTH. - -LFSR_INIT - -Initial state of LFSR. Defaults to all 1s. - -LFSR_CONFIG - -Specify the LFSR configuration, either Fibonacci or Galois. Fibonacci is generally used -for linear-feedback shift registers (LFSR) for pseudorandom binary sequence (PRBS) generators, -scramblers, and descrambers, while Galois is generally used for cyclic redundancy check -generators and checkers. - -Fibonacci style (example for 64b66b scrambler, 0x8000000001) - - DIN (LSB first) - | - V - (+)<---------------------------(+)<-----------------------------. - | ^ | - | .----. .----. .----. | .----. .----. .----. | - +->| 0 |->| 1 |->...->| 38 |-+->| 39 |->...->| 56 |->| 57 |--' - | '----' '----' '----' '----' '----' '----' - V - DOUT - -Galois style (example for CRC16, 0x8005) - - ,-------------------+-------------------------+----------(+)<-- DIN (MSB first) - | | | ^ - | .----. .----. V .----. .----. V .----. | - `->| 0 |->| 1 |->(+)->| 2 |->...->| 14 |->(+)->| 15 |--+---> DOUT - '----' '----' '----' '----' '----' - -REVERSE - -Bit-reverse LFSR output. Shifts MSB first by default, set REVERSE for LSB first. - -INVERT - -Bitwise invert PRBS output. - -DATA_WIDTH - -Specify width of output data bus. - -STYLE - -Specify implementation style. Can be "AUTO", "LOOP", or "REDUCTION". When "AUTO" -is selected, implemenation will be "LOOP" or "REDUCTION" based on synthesis translate -directives. "REDUCTION" and "LOOP" are functionally identical, however they simulate -and synthesize differently. "REDUCTION" is implemented with a loop over a Verilog -reduction operator. "LOOP" is implemented as a doubly-nested loop with no reduction -operator. "REDUCTION" is very fast for simulation in iverilog and synthesizes well in -Quartus but synthesizes poorly in ISE, likely due to large inferred XOR gates causing -problems with the optimizer. "LOOP" synthesizes will in both ISE and Quartus. "AUTO" -will default to "REDUCTION" when simulating and "LOOP" for synthesizers that obey -synthesis translate directives. - -Settings for common LFSR/CRC implementations: - -Name Configuration Length Polynomial Initial value Notes -CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output -PRBS6 Fibonacci 6 6'h21 any -PRBS7 Fibonacci 7 7'h41 any -PRBS9 Fibonacci 9 9'h021 any ITU V.52 -PRBS10 Fibonacci 10 10'h081 any ITU -PRBS11 Fibonacci 11 11'h201 any ITU O.152 -PRBS15 Fibonacci, inverted 15 15'h4001 any ITU O.152 -PRBS17 Fibonacci 17 17'h04001 any -PRBS20 Fibonacci 20 20'h00009 any ITU V.57 -PRBS23 Fibonacci, inverted 23 23'h040001 any ITU O.151 -PRBS29 Fibonacci, inverted 29 29'h08000001 any -PRBS31 Fibonacci, inverted 31 31'h10000001 any -64b66b Fibonacci, bit-reverse 58 58'h8000000001 any 10G Ethernet -128b130b Galois, bit-reverse 23 23'h210125 any PCIe gen 3 - -*/ - -reg [LFSR_WIDTH-1:0] state_reg = LFSR_INIT; -reg [DATA_WIDTH-1:0] output_reg = 0; - -wire [DATA_WIDTH-1:0] lfsr_data; -wire [LFSR_WIDTH-1:0] lfsr_state; - -assign data_out = output_reg; - -lfsr #( - .LFSR_WIDTH(LFSR_WIDTH), - .LFSR_POLY(LFSR_POLY), - .LFSR_CONFIG(LFSR_CONFIG), - .LFSR_FEED_FORWARD(0), - .REVERSE(REVERSE), - .DATA_WIDTH(DATA_WIDTH), - .STYLE(STYLE) -) -lfsr_inst ( - .data_in({DATA_WIDTH{1'b0}}), - .state_in(state_reg), - .data_out(lfsr_data), - .state_out(lfsr_state) -); - -always @* begin - if (INVERT) begin - output_reg <= ~lfsr_data; - end else begin - output_reg <= lfsr_data; - end -end - -always @(posedge clk) begin - if (rst) begin - state_reg <= LFSR_INIT; - end else begin - if (enable) begin - state_reg <= lfsr_state; - end - end -end - -endmodule - -`resetall diff --git a/designs/src/lfsr_prbs_gen/verilog.mk b/designs/src/lfsr_prbs_gen/verilog.mk deleted file mode 100644 index 3d88517..0000000 --- a/designs/src/lfsr_prbs_gen/verilog.mk +++ /dev/null @@ -1,6 +0,0 @@ -ifneq ($(wildcard $(DEV_FLAG)),) -export VERILOG_FILES = \ - $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo/rtl/*.v) -else -export VERILOG_FILES = $(wildcard $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/*.v) -endif \ No newline at end of file diff --git a/designs/src/liteeth/macros.v b/designs/src/liteeth/macros.v index 52cf172..e3a3b23 100644 Binary files a/designs/src/liteeth/macros.v and b/designs/src/liteeth/macros.v differ diff --git a/designs/src/liteeth/verilog.mk b/designs/src/liteeth/verilog.mk index 12ab81a..3c150f7 100644 --- a/designs/src/liteeth/verilog.mk +++ b/designs/src/liteeth/verilog.mk @@ -27,7 +27,7 @@ endif VERILOG_FILES += $(TARGET_FILE) $(LITEETH_DIR)/macros.v ifeq ($(MAKELEVEL),1) -ifneq ($(wildcard $(DEV_FLAG)),) +ifeq ($(DO_UPDATE),1) ifeq ($(DESIGN_NAME),liteeth_mac_axi_mii) YAML_FILE = axi-lite-mii.yml PATCH_FILE = mac_axi_mii.patch diff --git a/designs/src/minimax/verilog.mk b/designs/src/minimax/verilog.mk index 12e5755..d14cba4 100644 --- a/designs/src/minimax/verilog.mk +++ b/designs/src/minimax/verilog.mk @@ -1,12 +1,10 @@ -ifneq ($(wildcard $(DEV_FLAG)),) +export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v +ifeq ($(DO_UPDATE),1) REPO_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/repo/rtl/$(DESIGN_NAME).v -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/$(DESIGN_NAME).v $(VERILOG_FILES): $(REPO_FILES) @echo "Translating $(REPO_FILES) -> $@" $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/dev/sv2v -w $@ $(REPO_FILES) @echo "Done." -else -export VERILOG_FILES = $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v endif \ No newline at end of file diff --git a/designs/src/sha3/dev/generated/sha3.v b/designs/src/sha3/sha3.v similarity index 100% rename from designs/src/sha3/dev/generated/sha3.v rename to designs/src/sha3/sha3.v diff --git a/designs/src/sha3/verilog.mk b/designs/src/sha3/verilog.mk index a7cae83..340bf4c 100644 --- a/designs/src/sha3/verilog.mk +++ b/designs/src/sha3/verilog.mk @@ -3,11 +3,7 @@ SHA3_DEV_RTL := $(SHA3_DEV_DIR)/generated/$(DESIGN_NAME).v SHA3_RELEASE_RTL := $(BENCH_DESIGN_HOME)/src/$(DESIGN_NAME)/$(DESIGN_NAME).v -ifneq ($(wildcard $(DEV_FLAG)),) -$(SHA3_DEV_RTL): $(SHA3_DEV_DIR)/setup.sh - @echo "Generating SHA3 RTL via setup.sh" - @cd $(SHA3_DEV_DIR) && bash setup.sh - +ifeq ($(DO_UPDATE),1) export VERILOG_FILES = $(SHA3_DEV_RTL) else # Prefer checked-in RTL; fall back to dev output if it has not been promoted yet. diff --git a/designs/src/vortex/LICENSE b/designs/src/vortex/LICENSE new file mode 100644 index 0000000..261eeb9 --- /dev/null +++ b/designs/src/vortex/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright [yyyy] [name of copyright owner] + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/designs/src/vortex/dev/VX_dp_ram_REPLACE.sv b/designs/src/vortex/dev/VX_dp_ram_REPLACE.sv new file mode 100644 index 0000000..28a1758 --- /dev/null +++ b/designs/src/vortex/dev/VX_dp_ram_REPLACE.sv @@ -0,0 +1,498 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// Modifications: +// - Added FakeRAM conditionals (for memories exceeding 1000 bits) +`include "VX_platform.vh" + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE != 0) begin : g_init \ + if (INIT_FILE != "") begin : g_file \ + initial $readmemh(INIT_FILE, ram); \ + end else begin : g_value \ + initial begin \ + for (integer i = 0; i < SIZE; ++i) begin : g_i \ + ram[i] = INIT_VALUE; \ + end \ + end \ + end \ + end + +`ifdef SIMULATION + `define RAM_RESET_BLOCK if (RESET_RAM && reset) begin \ + for (integer i = 0; i < SIZE; ++i) begin \ + ram[i] <= DATAW'(INIT_VALUE); \ + end \ + end else +`else + `define RAM_RESET_BLOCK +`endif + +`define RAM_WRITE_ALL `RAM_RESET_BLOCK \ + if (write) begin \ + ram[waddr] <= wdata; \ + end + +`ifdef QUARTUS + `define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`else + `define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`endif + +`TRACING_OFF +module VX_dp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter WRENW = 1, + parameter OUT_REG = 0, + parameter LUTRAM = 0, + parameter `STRING RDW_MODE = "W", // W: write-first, R: read-first + parameter RADDR_REG = 0, // read address registered hint + parameter RADDR_RESET = 0, // read address has reset + parameter RDW_ASSERT = 0, + parameter RESET_RAM = 0, + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, + input wire [ADDRW-1:0] waddr, + input wire [DATAW-1:0] wdata, + input wire [ADDRW-1:0] raddr, + output wire [DATAW-1:0] rdata +); + localparam WSELW = DATAW / WRENW; + `UNUSED_PARAM (LUTRAM) + `UNUSED_PARAM (RADDR_REG) + `UNUSED_PARAM (RADDR_RESET) + + `STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter")) + `STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W"), ("invalid parameter")) + `UNUSED_PARAM (RDW_ASSERT) + +`ifdef SYNTHESIS + localparam FORCE_BRAM = !LUTRAM && `FORCE_BRAM(SIZE, DATAW); + if (DATAW == 128 && SIZE == 64) begin : g_fakeram + fakeram_128x64_1r1w fakeram_128x64 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 193 && SIZE == 16) begin : g_fakeram + fakeram_193x16_1r1w fakeram_193x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 654 && SIZE == 4) begin : g_fakeram + fakeram_654x4_1r1w fakeram_654x4 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 560 && SIZE == 4) begin : g_fakeram + fakeram_560x4_1r1w fakeram_560x4 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 21 && SIZE == 256) begin : g_fakeram + fakeram_21x256_1r1w fakeram_21x256 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 192 && SIZE == 16) begin : g_fakeram + fakeram_192x16_1r1w fakeram_192x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 85 && SIZE == 16) begin : g_fakeram + fakeram_85x16_1r1w fakeram_85x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 21 && SIZE == 64) begin : g_fakeram + fakeram_21x64_1r1w fakeram_21x64 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 87 && SIZE == 16) begin : g_fakeram + fakeram_87x16_1r1w fakeram_87x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (OUT_REG) begin : g_sync + if (FORCE_BRAM) begin : g_bram + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end else begin : g_no_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end + end + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end else begin : g_no_wren + `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end + end + end + end else begin : g_async + `UNUSED_VAR (read) + if (FORCE_BRAM) begin : g_bram + `ifdef ASYNC_BRAM_PATCH + VX_async_ram_patch #( + .DATAW (DATAW), + .SIZE (SIZE), + .WRENW (WRENW), + .DUAL_PORT (1), + .FORCE_BRAM (FORCE_BRAM), + .RADDR_REG (RADDR_REG), + .RADDR_RESET(RADDR_RESET), + .WRITE_FIRST(RDW_MODE == "W"), + .INIT_ENABLE(INIT_ENABLE), + .INIT_FILE (INIT_FILE), + .INIT_VALUE (INIT_VALUE) + ) async_ram_patch ( + .clk (clk), + .reset (reset), + .read (read), + .write (write), + .wren (wren), + .waddr (waddr), + .wdata (wdata), + .raddr (raddr), + .rdata (rdata) + ); + `else + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end + `endif + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end + end + end +`else + // simulation + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + + if (WRENW != 1) begin : g_wren + reg [DATAW-1:0] wdata_n; + always @(*) begin + wdata_n = ram[waddr]; + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) begin + wdata_n[i * WSELW +: WSELW] = wdata[i * WSELW +: WSELW]; + end + end + end + always @(posedge clk) begin + `RAM_RESET_BLOCK + if (write) begin + ram[waddr] <= wdata_n; + end + end + end else begin : g_no_wren + `UNUSED_VAR (wren) + always @(posedge clk) begin + `RAM_WRITE_ALL + end + end + + if (OUT_REG) begin : g_sync + if (RDW_MODE == "W") begin : g_write_first + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end else if (RDW_MODE == "R") begin : g_read_first + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end + end else begin : g_async + `UNUSED_VAR (read) + if (RDW_MODE == "W") begin : g_write_first + assign rdata = ram[raddr]; + end else begin : g_read_first + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + + always @(posedge clk) begin + if (reset) begin + prev_write <= 0; + prev_data <= '0; + prev_waddr <= '0; + end else begin + prev_write <= write; + prev_data <= ram[waddr]; + prev_waddr <= waddr; + end + end + + assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; + if (RDW_ASSERT) begin : g_rw_asert + `RUNTIME_ASSERT(~read || (rdata == ram[raddr]), ("%t: read after write hazard", $time)) + end + end + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/dev/VX_fpu_div_REPLACE.sv b/designs/src/vortex/dev/VX_fpu_div_REPLACE.sv new file mode 100644 index 0000000..5eefd55 --- /dev/null +++ b/designs/src/vortex/dev/VX_fpu_div_REPLACE.sv @@ -0,0 +1,185 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_div import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES / `FDIV_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + output wire valid_out, + input wire ready_out +); + localparam DATAW = 2 * 32 + INST_FRM_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = dataa[i]; + assign data_in[i][32 +: 32] = datab[i]; + assign data_in[i][64 +: INST_FRM_BITS] = frm; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FDIV), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + acl_fdiv fdiv ( + .clk (clk), + .areset (1'b0), + .en (pe_enable), + .a (pe_data_in[i][0 +: 32]), + .b (pe_data_in[i][32 +: 32]), + .q (pe_data_out[i][0 +: 32]) + ); + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x; + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + `UNUSED_VAR (fflags_out) + +`elsif VIVADO + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + wire [3:0] tuser; + xil_fdiv fdiv ( + .aclk (clk), + .aclken (pe_enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (pe_data_in[i][0 +: 32]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (pe_data_in[i][32 +: 32]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (pe_data_out[i][0 +: 32]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = {tuser[2], tuser[3], tuser[1], tuser[0], 1'b0}; + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`else + `ifndef SYNTHESIS + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + reg [63:0] r; + `UNUSED_VAR (r) + fflags_t f; + + always @(*) begin + dpi_fdiv ( + pe_enable, + int'(0), + {32'hffffffff, pe_data_in[i][0 +: 32]}, // a + {32'hffffffff, pe_data_in[i][32 +: 32]}, // b + pe_data_in[0][64 +: INST_FRM_BITS], // frm + r, + f + ); + end + + VX_shift_register #( + .DATAW (`FP_FLAGS_BITS + 32), + .DEPTH (`LATENCY_FDIV) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (pe_enable), + .data_in ({f, r[31:0]}), + .data_out (pe_data_out[i]) + ); + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + `else + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + assign pe_data_out[i] = '0; + end + assign has_fflags = 0; + assign per_lane_fflags = '0; + `endif +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/dev/VX_fpu_fma_REPLACE.sv b/designs/src/vortex/dev/VX_fpu_fma_REPLACE.sv new file mode 100644 index 0000000..7fd760f --- /dev/null +++ b/designs/src/vortex/dev/VX_fpu_fma_REPLACE.sv @@ -0,0 +1,221 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_fma import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES / `FMA_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire is_madd, + input wire is_sub, + input wire is_neg, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + input wire [NUM_LANES-1:0][31:0] datac, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam DATAW = 3 * 32 + INST_FRM_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + reg [NUM_LANES-1:0][31:0] a, b, c; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_select + always @(*) begin + if (is_madd) begin + // MADD / MSUB / NMADD / NMSUB + a[i] = {is_neg ^ dataa[i][31], dataa[i][30:0]}; + b[i] = datab[i]; + c[i] = {is_neg ^ is_sub ^ datac[i][31], datac[i][30:0]}; + end else begin + if (is_neg) begin + // MUL + a[i] = dataa[i]; + b[i] = datab[i]; + c[i] = '0; + end else begin + // ADD / SUB + a[i] = dataa[i]; + b[i] = 32'h3f800000; // 1.0f + c[i] = {is_sub ^ datab[i][31], datab[i][30:0]}; + end + end + end + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = a[i]; + assign data_in[i][32 +: 32] = b[i]; + assign data_in[i][64 +: 32] = c[i]; + assign data_in[i][96 +: INST_FRM_BITS] = frm; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FMA), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas + acl_fmadd fmadd ( + .clk (clk), + .areset (1'b0), + .en (pe_enable), + .a (pe_data_in[i][0 +: 32]), + .b (pe_data_in[i][32 +: 32]), + .c (pe_data_in[i][64 +: 32]), + .q (pe_data_out[i][0 +: 32]) + ); + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x; + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + +`elsif VIVADO + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas + wire [2:0] tuser; + + xil_fma fma ( + .aclk (clk), + .aclken (pe_enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (pe_data_in[i][0 +: 32]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (pe_data_in[i][32 +: 32]), + .s_axis_c_tvalid (1'b1), + .s_axis_c_tdata (pe_data_in[i][64 +: 32]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (pe_data_out[i][0 +: 32]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = {tuser[2], 1'b0, tuser[1], tuser[0], 1'b0}; + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`else + `ifndef SYNTHESIS + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas + reg [63:0] r; + `UNUSED_VAR (r) + fflags_t f; + + always @(*) begin + dpi_fmadd ( + pe_enable, + int'(0), + {32'hffffffff, pe_data_in[i][0 +: 32]}, // a + {32'hffffffff, pe_data_in[i][32 +: 32]}, // b + {32'hffffffff, pe_data_in[i][64 +: 32]}, // c + pe_data_in[0][96 +: INST_FRM_BITS], // frm + r, + f + ); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FMA) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (pe_enable), + .data_in ({f, r[31:0]}), + .data_out (pe_data_out[i]) + ); + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + `else + for (genvar i = 0; i < NUM_PES; ++i) begin : g_ffma + assign pe_data_out[i] = '0; + end + assign has_fflags = 0; + assign per_lane_fflags = '0; + `endif + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/dev/VX_fpu_sqrt_REPLACE.sv b/designs/src/vortex/dev/VX_fpu_sqrt_REPLACE.sv new file mode 100644 index 0000000..f29470a --- /dev/null +++ b/designs/src/vortex/dev/VX_fpu_sqrt_REPLACE.sv @@ -0,0 +1,181 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_sqrt import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES /`FSQRT_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam DATAW = 32 + INST_FRM_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = dataa[i]; + assign data_in[i][32 +: INST_FRM_BITS] = frm; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FSQRT), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts + acl_fsqrt fsqrt ( + .clk (clk), + .areset (1'b0), + .en (pe_enable), + .a (pe_data_in[i][0 +: 32]), + .q (pe_data_out[i][0 +: 32]) + ); + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x; + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + `UNUSED_VAR (fflags_out) + +`elsif VIVADO + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts + wire tuser; + + xil_fsqrt fsqrt ( + .aclk (clk), + .aclken (pe_enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (pe_data_in[i][0 +: 32]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (pe_data_out[i][0 +: 32]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = {tuser, 1'b0, 1'b0, 1'b0, 1'b0}; + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`else + `ifndef SYNTHESIS + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts + reg [63:0] r; + `UNUSED_VAR (r) + fflags_t f; + + always @(*) begin + dpi_fsqrt ( + pe_enable, + int'(0), + {32'hffffffff, pe_data_in[i][0 +: 32]}, // a + pe_data_in[0][32 +: INST_FRM_BITS], // frm + r, + f + ); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FSQRT) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (pe_enable), + .data_in ({f, r[31:0]}), + .data_out (pe_data_out[i]) + ); + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + `else + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + assign pe_data_out[i] = '0; + end + assign has_fflags = 0; + assign per_lane_fflags = '0; + `endif + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/dev/VX_sp_ram_REPLACE.sv b/designs/src/vortex/dev/VX_sp_ram_REPLACE.sv new file mode 100644 index 0000000..7fa6ea6 --- /dev/null +++ b/designs/src/vortex/dev/VX_sp_ram_REPLACE.sv @@ -0,0 +1,473 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// Modifications: +// - Added FakeRAM conditionals (for memories exceeding 2000 bits) + +`include "VX_platform.vh" + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE != 0) begin : g_init \ + if (INIT_FILE != "") begin : g_file \ + initial $readmemh(INIT_FILE, ram); \ + end else begin : g_value \ + initial begin \ + for (integer i = 0; i < SIZE; ++i) begin : g_i \ + ram[i] = INIT_VALUE; \ + end \ + end \ + end \ + end + +`ifdef SIMULATION + `define RAM_RESET_BLOCK if (RESET_RAM && reset) begin \ + for (integer i = 0; i < SIZE; ++i) begin \ + ram[i] <= DATAW'(INIT_VALUE); \ + end \ + end else +`else + `define RAM_RESET_BLOCK +`endif + +`define RAM_WRITE_ALL `RAM_RESET_BLOCK \ + if (write) begin \ + ram[addr] <= wdata; \ + end + +`ifdef QUARTUS + `define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[addr][i] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`else + `define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`endif + +`TRACING_OFF +module VX_sp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter WRENW = 1, + parameter OUT_REG = 0, + parameter LUTRAM = 0, + parameter `STRING RDW_MODE = "W", // W: write-first, R: read-first, N: no-change + parameter RADDR_REG = 0, // read address registered hint + parameter RADDR_RESET = 0, // read address has reset + parameter RDW_ASSERT = 0, + parameter RESET_RAM = 0, + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, + input wire [ADDRW-1:0] addr, + input wire [DATAW-1:0] wdata, + output wire [DATAW-1:0] rdata +); + localparam WSELW = DATAW / WRENW; + `UNUSED_PARAM (LUTRAM) + `UNUSED_PARAM (RADDR_REG) + `UNUSED_PARAM (RADDR_RESET) + + `STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter")) + `STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W" || RDW_MODE == "N"), ("invalid parameter")) + `UNUSED_PARAM (RDW_ASSERT) + +`ifdef SYNTHESIS + localparam FORCE_BRAM = !LUTRAM && `FORCE_BRAM(SIZE, DATAW); + if (DATAW == 32 && SIZE == 1024) begin : g_fakeram + fakeram_32x1024_1rw fakeram_32x1024 ( + .rw0_clk (clk), + .rw0_ce_in (read || write), + .rw0_we_in (write), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_wmask_in(wren), + .rw0_rd_out (rdata) + ); + end else if (DATAW == 512 && SIZE == 64) begin : g_fakeram + fakeram_512x64_1rw fakeram_512x64 ( + .rw0_clk (clk), + .rw0_ce_in (read || write), + .rw0_we_in (write), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_wmask_in(wren), + .rw0_rd_out (rdata) + ); + end else if (DATAW == 128 && SIZE == 256) begin : g_fakeram + fakeram_128x256_1rw fakeram_128x256 ( + .rw0_clk (clk), + .rw0_ce_in (read || write), + .rw0_we_in (write), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_wmask_in(wren), + .rw0_rd_out (rdata) + ); + end else if (OUT_REG) begin : g_sync + if (FORCE_BRAM) begin : g_bram + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] addr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + addr_r <= addr; + end + end + assign rdata = ram[addr_r]; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + if (write) begin + rdata_r <= wdata; + end else begin + rdata_r <= ram[addr]; + end + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "N") begin : g_no_change + if (WRENW != 1) begin : g_wren + `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] addr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + addr_r <= addr; + end + end + assign rdata = ram[addr_r]; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + if (write) begin + rdata_r <= wdata; + end else begin + rdata_r <= ram[addr]; + end + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "N") begin : g_no_change + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end + end + end else begin : g_async + `UNUSED_VAR (read) + if (FORCE_BRAM) begin : g_bram + `ifdef ASYNC_BRAM_PATCH + VX_async_ram_patch #( + .DATAW (DATAW), + .SIZE (SIZE), + .WRENW (WRENW), + .DUAL_PORT (0), + .FORCE_BRAM (FORCE_BRAM), + .RADDR_REG (RADDR_REG), + .RADDR_RESET(RADDR_RESET), + .WRITE_FIRST(RDW_MODE == "W"), + .INIT_ENABLE(INIT_ENABLE), + .INIT_FILE (INIT_FILE), + .INIT_VALUE (INIT_VALUE) + ) async_ram_patch ( + .clk (clk), + .reset (reset), + .read (read), + .write (write), + .wren (wren), + .waddr (addr), + .wdata (wdata), + .raddr (addr), + .rdata (rdata) + ); + `else + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end + `endif + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end + end + end +`else + // simulation + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + + if (WRENW != 1) begin : g_wren + reg [DATAW-1:0] wdata_n; + always @(*) begin + wdata_n = ram[addr]; + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) begin + wdata_n[i * WSELW +: WSELW] = wdata[i * WSELW +: WSELW]; + end + end + end + always @(posedge clk) begin + `RAM_RESET_BLOCK + if (write) begin + ram[addr] <= wdata_n; + end + end + end else begin : g_no_wren + `UNUSED_VAR (wren) + always @(posedge clk) begin + `RAM_WRITE_ALL + end + end + + if (OUT_REG) begin : g_sync + if (RDW_MODE == "W") begin : g_write_first + reg [ADDRW-1:0] addr_r; + always @(posedge clk) begin + if (read) begin + addr_r <= addr; + end + end + assign rdata = ram[addr_r]; + end else if (RDW_MODE == "R") begin : g_read_first + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else if (RDW_MODE == "N") begin : g_no_change + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (read && ~write) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end else begin : g_async + `UNUSED_VAR (read) + if (RDW_MODE == "W") begin : g_write_first + assign rdata = ram[addr]; + end else begin : g_read_first + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + always @(posedge clk) begin + if (reset) begin + prev_write <= 0; + prev_data <= '0; + prev_waddr <= '0; + end else begin + prev_write <= write; + prev_data <= ram[addr]; + prev_waddr <= addr; + end + end + assign rdata = (prev_write && (prev_waddr == addr)) ? prev_data : ram[addr]; + if (RDW_ASSERT) begin : g_rw_asert + `RUNTIME_ASSERT(~read || (rdata == ram[addr]), ("%t: read after write hazard", $time)) + end + end + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/dev/install/install_sv2v.sh b/designs/src/vortex/dev/install/install_sv2v.sh new file mode 100644 index 0000000..3030dd6 --- /dev/null +++ b/designs/src/vortex/dev/install/install_sv2v.sh @@ -0,0 +1,117 @@ +#!/usr/bin/bash +# Using OpenROAD-flow-scripts/build_openroad.sh as a template + +set -euo pipefail + +DIR="$(dirname $(readlink -f $0))" +cd "$DIR" + +cd .. +mkdir -p packages +INSTALL_PATH="$(pwd)/packages/" + +PROC=-1 + +function usage() { + cat << EOF + +Usage: $0 [-h|--help] [-o|--local] [-t|--threads N] [--clean] [--clean-force] + +Options: + -h, --help Print this help message. + + -o, --local Build locally instead of building a Docker image. + + -t, --threads N Use N cpus when compiling software. + + --install-path PATH Path to install tools. Default is ${INSTALL_PATH}. + + --clean Call git clean interactively before compile. + Also removes any files native to nyuzi. + + --clean-force Call clean before compile. WARNING: this option + will not ask for confirmation. +EOF +} + +# Parse arguments +__CMD="$0 $@" +while (( "$#" )); do + case "$1" in + -h|--help) + usage 2> /dev/null + exit + ;; + -o|--local) + LOCAL_BUILD=1 + ;; + -t|--threads) + PROC="$2" + shift + ;; + --install-path) + INSTALL_PATH="$2" + shift + ;; + --clean) + CLEAN_BEFORE=1 + ;; + --clean-force) + CLEAN_BEFORE=1 + CLEAN_FORCE=1 + ;; + -*|--*) # unsupported flags + echo "[ERROR FLW-0005] Unsupported flag $1." >&2 + usage 2> /dev/null + exit 1 + ;; + esac + shift +done + +if [[ "$PROC" == "-1" ]]; then + if [[ "$OSTYPE" == "linux-gnu"* ]]; then + PROC=$(nproc --all) + elif [[ "$OSTYPE" == "darwin"* ]]; then + PROC=$(sysctl -n hw.ncpu) + else + cat << EOF +Unsupported OS: cannot determine number of host CPUs" +Defaulting to 2 threads. Use --threads N to use N threads" +EOF + PROC=2 + fi +fi + + +__cleanup() +{ + if [ ! -z "${CLEAN_FORCE+x}" ]; then + CLEAN_CMD="-x -d --force" + else + CLEAN_CMD="-x -d --interactive" + fi + echo "Cleaning up binaries and build files." + git clean ${CLEAN_CMD} tools + git submodule foreach --recursive git clean ${CLEAN_CMD} + rm sv2v +} + +if [ ! -z "${CLEAN_BEFORE+x}" ]; then + __cleanup +fi + +# Check if sv2v exists already (and set up if not) +if [ ! -f "${INSTALL_PATH}/sv2v" ]; then + echo "sv2v not found. Downloading prebuilt binary..." + SV2V_ZIP="sv2v-Linux.zip" + curl -sSL -o "$SV2V_ZIP" \ + "https://github.com/zachjs/sv2v/releases/download/v0.0.13/sv2v-Linux.zip" + unzip -o "$SV2V_ZIP" -d sv2v_extract + cp sv2v_extract/sv2v-Linux/sv2v "${INSTALL_PATH}/sv2v" + chmod +x "${INSTALL_PATH}/sv2v" + rm -rf "$SV2V_ZIP" sv2v_extract + echo "sv2v binary downloaded successfully!" +else + echo "sv2v already present in directory" +fi diff --git a/designs/src/vortex/dev/repo b/designs/src/vortex/dev/repo new file mode 160000 index 0000000..31e4765 --- /dev/null +++ b/designs/src/vortex/dev/repo @@ -0,0 +1 @@ +Subproject commit 31e4765d0d09d7686c1299e5baf7bbb6102245ae diff --git a/designs/src/vortex/dev/setup.sh b/designs/src/vortex/dev/setup.sh new file mode 100755 index 0000000..ce8e111 --- /dev/null +++ b/designs/src/vortex/dev/setup.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +set -euo pipefail + +DEV_DIR="$(dirname $(readlink -f $0))" +cd "$DEV_DIR" + +cd .. +VORTEX_DIR="$DEV_DIR/repo" +OUT_FILE="vortex.v" +HW="${VORTEX_DIR}/hw/rtl" + +cp -r "$HW" "$(pwd)" +cp "${VORTEX_DIR}/hw/dpi/float_dpi.vh" "${VORTEX_DIR}/hw/dpi/util_dpi.vh" "$(pwd)/rtl/" +cp "$DEV_DIR/VX_dp_ram_REPLACE.sv" "$(pwd)/rtl/libs/VX_dp_ram.sv" +cp "$DEV_DIR/VX_sp_ram_REPLACE.sv" "$(pwd)/rtl/libs/VX_sp_ram.sv" +# cp "$DEV_DIR/VX_fpu_div_REPLACE.sv" "$(pwd)/rtl/fpu/VX_fpu_div.sv" +# cp "$DEV_DIR/VX_fpu_sqrt_REPLACE.sv" "$(pwd)/rtl/fpu/VX_fpu_sqrt.sv" +# cp "$DEV_DIR/VX_fpu_fma_REPLACE.sv" "$(pwd)/rtl/fpu/VX_fpu_fma.sv" \ No newline at end of file diff --git a/designs/src/vortex/rtl/.DS_Store b/designs/src/vortex/rtl/.DS_Store new file mode 100644 index 0000000..9e68d61 Binary files /dev/null and b/designs/src/vortex/rtl/.DS_Store differ diff --git a/designs/src/vortex/rtl/VX_cluster.sv b/designs/src/vortex/rtl/VX_cluster.sv new file mode 100644 index 0000000..896e91c --- /dev/null +++ b/designs/src/vortex/rtl/VX_cluster.sv @@ -0,0 +1,158 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_cluster import VX_gpu_pkg::*; #( + parameter CLUSTER_ID = 0, + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, +`endif + + // DCRs + VX_dcr_bus_if.slave dcr_bus_if, + + // Memory + VX_mem_bus_if.master mem_bus_if [`L2_MEM_PORTS], + + // Status + output wire busy +); + +`ifdef SCOPE + localparam scope_socket = 0; + `SCOPE_IO_SWITCH (NUM_SOCKETS); +`endif + +`ifdef PERF_ENABLE + cache_perf_t l2_perf; + sysmem_perf_t sysmem_perf_tmp; + always @(*) begin + sysmem_perf_tmp = sysmem_perf; + sysmem_perf_tmp.l2cache = l2_perf; + end +`endif + +`ifdef GBAR_ENABLE + + VX_gbar_bus_if per_socket_gbar_bus_if[NUM_SOCKETS](); + VX_gbar_bus_if gbar_bus_if(); + + VX_gbar_arb #( + .NUM_REQS (NUM_SOCKETS), + .OUT_BUF ((NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure + ) gbar_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (per_socket_gbar_bus_if), + .bus_out_if (gbar_bus_if) + ); + + VX_gbar_unit #( + .INSTANCE_ID (`SFORMATF(("gbar%0d", CLUSTER_ID))) + ) gbar_unit ( + .clk (clk), + .reset (reset), + .gbar_bus_if (gbar_bus_if) + ); + +`endif + + VX_mem_bus_if #( + .DATA_SIZE (`L1_LINE_SIZE), + .TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH) + ) per_socket_mem_bus_if[NUM_SOCKETS * `L1_MEM_PORTS](); + + `RESET_RELAY (l2_reset, reset); + + VX_cache_wrap #( + .INSTANCE_ID (`SFORMATF(("%s-l2cache", INSTANCE_ID))), + .CACHE_SIZE (`L2_CACHE_SIZE), + .LINE_SIZE (`L2_LINE_SIZE), + .NUM_BANKS (`L2_NUM_BANKS), + .NUM_WAYS (`L2_NUM_WAYS), + .WORD_SIZE (L2_WORD_SIZE), + .NUM_REQS (L2_NUM_REQS), + .MEM_PORTS (`L2_MEM_PORTS), + .CRSQ_SIZE (`L2_CRSQ_SIZE), + .MSHR_SIZE (`L2_MSHR_SIZE), + .MRSQ_SIZE (`L2_MRSQ_SIZE), + .MREQ_SIZE (`L2_WRITEBACK ? `L2_MSHR_SIZE : `L2_MREQ_SIZE), + .TAG_WIDTH (L2_TAG_WIDTH), + .WRITE_ENABLE (1), + .WRITEBACK (`L2_WRITEBACK), + .DIRTY_BYTES (`L2_DIRTYBYTES), + .REPL_POLICY (`L2_REPL_POLICY), + .CORE_OUT_BUF (3), + .MEM_OUT_BUF (3), + .NC_ENABLE (1), + .PASSTHRU (!`L2_ENABLED) + ) l2cache ( + .clk (clk), + .reset (l2_reset), + `ifdef PERF_ENABLE + .cache_perf (l2_perf), + `endif + .core_bus_if (per_socket_mem_bus_if), + .mem_bus_if (mem_bus_if) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_SOCKETS-1:0] per_socket_busy; + + // Generate all sockets + for (genvar socket_id = 0; socket_id < NUM_SOCKETS; ++socket_id) begin : g_sockets + + `RESET_RELAY (socket_reset, reset); + + VX_dcr_bus_if socket_dcr_bus_if(); + wire is_base_dcr_addr = (dcr_bus_if.write_addr >= `VX_DCR_BASE_STATE_BEGIN && dcr_bus_if.write_addr < `VX_DCR_BASE_STATE_END); + `BUFFER_DCR_BUS_IF (socket_dcr_bus_if, dcr_bus_if, is_base_dcr_addr, (NUM_SOCKETS > 1)) + + VX_socket #( + .SOCKET_ID ((CLUSTER_ID * NUM_SOCKETS) + socket_id), + .INSTANCE_ID (`SFORMATF(("%s-socket%0d", INSTANCE_ID, socket_id))) + ) socket ( + `SCOPE_IO_BIND (scope_socket+socket_id) + + .clk (clk), + .reset (socket_reset), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf_tmp), + `endif + + .dcr_bus_if (socket_dcr_bus_if), + + .mem_bus_if (per_socket_mem_bus_if[socket_id * `L1_MEM_PORTS +: `L1_MEM_PORTS]), + + `ifdef GBAR_ENABLE + .gbar_bus_if (per_socket_gbar_bus_if[socket_id]), + `endif + + .busy (per_socket_busy[socket_id]) + ); + end + + `BUFFER_EX(busy, (| per_socket_busy), 1'b1, 1, (NUM_SOCKETS > 1)); + +endmodule diff --git a/designs/src/vortex/rtl/VX_config.vh b/designs/src/vortex/rtl/VX_config.vh new file mode 100644 index 0000000..eef7bed --- /dev/null +++ b/designs/src/vortex/rtl/VX_config.vh @@ -0,0 +1,966 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_CONFIG_VH +`define VX_CONFIG_VH + +`ifndef MIN +`define MIN(x, y) (((x) < (y)) ? (x) : (y)) +`endif + +`ifndef MAX +`define MAX(x, y) (((x) > (y)) ? (x) : (y)) +`endif + +`ifndef CLAMP +`define CLAMP(x, lo, hi) (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x))) +`endif + +`ifndef UP +`define UP(x) (((x) != 0) ? (x) : 1) +`endif + +/////////////////////////////////////////////////////////////////////////////// + +`ifndef EXT_M_DISABLE +`define EXT_M_ENABLE +`endif + +`ifndef EXT_F_DISABLE +`define EXT_F_ENABLE +`endif + +`ifdef XLEN_64 +`ifndef FPU_DSP +`ifndef EXT_D_DISABLE +`define EXT_D_ENABLE +`endif +`endif +`endif + +`ifndef EXT_ZICOND_DISABLE +`define EXT_ZICOND_ENABLE +`endif + +`ifndef XLEN_32 +`ifndef XLEN_64 +`define XLEN_32 +`endif +`endif + +`ifdef XLEN_64 +`define XLEN 64 +`endif + +`ifdef XLEN_32 +`define XLEN 32 +`endif + +`ifdef EXT_D_ENABLE +`define FLEN_64 +`else +`define FLEN_32 +`endif + +`ifdef FLEN_64 +`define FLEN 64 +`endif + +`ifdef FLEN_32 +`define FLEN 32 +`endif + +`ifdef XLEN_64 +`ifdef FLEN_32 + `define FPU_RV64F +`endif +`endif + +`ifndef VLEN +`define VLEN (4 * `XLEN) +`endif + +`ifndef NUM_CLUSTERS +`define NUM_CLUSTERS 1 +`endif + +`ifndef NUM_CORES +`define NUM_CORES 1 +`endif + +`ifndef NUM_WARPS +`define NUM_WARPS 4 +`endif + +`ifndef NUM_THREADS +`define NUM_THREADS 4 +`endif + +`ifndef NUM_BARRIERS +`define NUM_BARRIERS `UP(`NUM_WARPS/2) +`endif + +`ifndef SOCKET_SIZE +`define SOCKET_SIZE `MIN(4, `NUM_CORES) +`endif + +`ifdef L1_DISABLE + `define ICACHE_DISABLE + `define DCACHE_DISABLE +`endif + +`ifndef MEM_BLOCK_SIZE +`define MEM_BLOCK_SIZE 64 +`endif + +`ifndef MEM_ADDR_WIDTH +`ifdef XLEN_64 +`define MEM_ADDR_WIDTH 48 +`else +`define MEM_ADDR_WIDTH 32 +`endif +`endif + +`ifndef L1_LINE_SIZE +`define L1_LINE_SIZE `MEM_BLOCK_SIZE +`endif + +`ifndef L2_LINE_SIZE +`define L2_LINE_SIZE `MEM_BLOCK_SIZE +`endif + +`ifndef L3_LINE_SIZE +`define L3_LINE_SIZE `MEM_BLOCK_SIZE +`endif + +// Platform memory parameters + +`ifndef PLATFORM_MEMORY_NUM_BANKS +`define PLATFORM_MEMORY_NUM_BANKS 2 +`endif + +`ifndef PLATFORM_MEMORY_ADDR_WIDTH +`ifdef XLEN_64 + `define PLATFORM_MEMORY_ADDR_WIDTH 48 +`else + `define PLATFORM_MEMORY_ADDR_WIDTH 32 +`endif +`endif + +`ifndef PLATFORM_MEMORY_DATA_SIZE +`define PLATFORM_MEMORY_DATA_SIZE 64 +`endif + +`ifndef PLATFORM_MEMORY_INTERLEAVE +`define PLATFORM_MEMORY_INTERLEAVE 1 +`endif + +`ifdef XLEN_64 + +`ifndef STACK_BASE_ADDR +`define STACK_BASE_ADDR 64'h1FFFF0000 +`endif + +`ifndef STARTUP_ADDR +`define STARTUP_ADDR 64'h080000000 +`endif + +`ifndef USER_BASE_ADDR +`define USER_BASE_ADDR 64'h000010000 +`endif + +`ifndef IO_BASE_ADDR +`define IO_BASE_ADDR 64'h000000040 +`endif + +`ifdef VM_ENABLE +`ifndef PAGE_TABLE_BASE_ADDR +`define PAGE_TABLE_BASE_ADDR 64'h0F0000000 +`endif + +`endif + +`else // XLEN_32 + +`ifndef STACK_BASE_ADDR +`define STACK_BASE_ADDR 32'hFFFF0000 +`endif + +`ifndef STARTUP_ADDR +`define STARTUP_ADDR 32'h80000000 +`endif + +`ifndef USER_BASE_ADDR +`define USER_BASE_ADDR 32'h00010000 +`endif + +`ifndef IO_BASE_ADDR +`define IO_BASE_ADDR 32'h00000040 +`endif + +`ifdef VM_ENABLE +`ifndef PAGE_TABLE_BASE_ADDR +`define PAGE_TABLE_BASE_ADDR 32'hF0000000 +`endif + +`endif + +`endif + +`define IO_END_ADDR `USER_BASE_ADDR + +`ifndef LMEM_LOG_SIZE +`define LMEM_LOG_SIZE 14 +`endif + +`ifndef LMEM_BASE_ADDR +`define LMEM_BASE_ADDR `STACK_BASE_ADDR +`endif + +`ifndef IO_COUT_ADDR +`define IO_COUT_ADDR `IO_BASE_ADDR +`endif +`define IO_COUT_SIZE 64 + +`ifndef IO_MPM_ADDR +`define IO_MPM_ADDR (`IO_COUT_ADDR + `IO_COUT_SIZE) +`endif + +`ifndef STACK_LOG2_SIZE +`define STACK_LOG2_SIZE 13 +`endif + +`define RESET_DELAY 8 + +`ifndef STALL_TIMEOUT +`define STALL_TIMEOUT (100000 * (1 ** (`L2_ENABLED + `L3_ENABLED))) +`endif + +`ifndef SV_DPI +`ifndef DPI_DISABLE +`define DPI_DISABLE +`endif +`endif + +`ifndef FPU_FPNEW +`ifndef FPU_DSP +`ifndef FPU_DPI +`ifndef SYNTHESIS +`ifndef DPI_DISABLE +`define FPU_DPI +`else +`define FPU_DSP +`endif +`else +`define FPU_DSP +`endif +`endif +`endif +`endif + +`ifndef SYNTHESIS +`ifndef DPI_DISABLE +`define IMUL_DPI +`define IDIV_DPI +`endif +`endif + +`ifndef DEBUG_LEVEL +`define DEBUG_LEVEL 3 +`endif + +`ifndef MEM_PAGE_SIZE +`define MEM_PAGE_SIZE (4096) +`endif + +`ifndef MEM_PAGE_LOG2_SIZE +`define MEM_PAGE_LOG2_SIZE (12) +`endif + +// Virtual Memory Configuration /////////////////////////////////////////////// +`ifdef VM_ENABLE + `ifdef XLEN_32 + `ifndef VM_ADDR_MODE + `define VM_ADDR_MODE SV32 //or BARE + `endif + `ifndef PT_LEVEL + `define PT_LEVEL (2) + `endif + `ifndef PTE_SIZE + `define PTE_SIZE (4) + `endif + `ifndef NUM_PTE_ENTRY + `define NUM_PTE_ENTRY (1024) + `endif + `ifndef PT_SIZE_LIMIT + `define PT_SIZE_LIMIT (1<<23) + `endif + `else + `ifndef VM_ADDR_MODE + `define VM_ADDR_MODE SV39 //or BARE + `endif + `ifndef PT_LEVEL + `define PT_LEVEL (3) + `endif + `ifndef PTE_SIZE + `define PTE_SIZE (8) + `endif + `ifndef NUM_PTE_ENTRY + `define NUM_PTE_ENTRY (512) + `endif + `ifndef PT_SIZE_LIMIT + `define PT_SIZE_LIMIT (1<<25) + `endif + `endif + + `ifndef PT_SIZE + `define PT_SIZE MEM_PAGE_SIZE + `endif + + `ifndef TLB_SIZE + `define TLB_SIZE (32) + `endif + +`endif + +// Pipeline Configuration ///////////////////////////////////////////////////// + +`ifndef SIMD_WIDTH +`define SIMD_WIDTH `NUM_THREADS +`endif + +// Issue width +`ifndef ISSUE_WIDTH +`define ISSUE_WIDTH `UP(`NUM_WARPS / 16) +`endif + +// Operand collectors +`ifndef NUM_OPCS +`define NUM_OPCS `UP(`NUM_WARPS / (4 * `ISSUE_WIDTH)) +`endif + +// Register File Banks +`ifndef NUM_GPR_BANKS +`define NUM_GPR_BANKS 4 +`endif +`ifndef NUM_VGPR_BANKS +`define NUM_VGPR_BANKS 2 +`endif + +// Number of ALU units +`ifndef NUM_ALU_LANES +`define NUM_ALU_LANES `SIMD_WIDTH +`endif +`ifndef NUM_ALU_BLOCKS +`define NUM_ALU_BLOCKS `ISSUE_WIDTH +`endif + +// Number of FPU units +`ifndef NUM_FPU_LANES +`define NUM_FPU_LANES `SIMD_WIDTH +`endif +`ifndef NUM_FPU_BLOCKS +`define NUM_FPU_BLOCKS `ISSUE_WIDTH +`endif + +// Number of LSU units +`ifndef NUM_LSU_LANES +`define NUM_LSU_LANES `SIMD_WIDTH +`endif +`ifndef NUM_LSU_BLOCKS +`define NUM_LSU_BLOCKS 1 +`endif + +// Number of SFU units +`ifndef NUM_SFU_LANES +`define NUM_SFU_LANES `SIMD_WIDTH +`endif +`define NUM_SFU_BLOCKS 1 + +// Number of VPU units +`ifndef NUM_VPU_LANES +`define NUM_VPU_LANES `SIMD_WIDTH +`endif +`ifndef NUM_VPU_BLOCKS +`define NUM_VPU_BLOCKS `ISSUE_WIDTH +`endif + +// Number of TCU units +`define NUM_TCU_LANES `NUM_THREADS +`ifndef NUM_TCU_BLOCKS +`define NUM_TCU_BLOCKS `ISSUE_WIDTH +`endif + +// Size of Instruction Buffer +`ifndef IBUF_SIZE +`define IBUF_SIZE 4 +`endif + +// LSU line size +`ifndef LSU_LINE_SIZE +`define LSU_LINE_SIZE `MIN(`NUM_LSU_LANES * (`XLEN / 8), `L1_LINE_SIZE) +`endif + +// Size of LSU Core Request Queue +`ifndef LSUQ_IN_SIZE +`define LSUQ_IN_SIZE (2 * (`SIMD_WIDTH / `NUM_LSU_LANES)) +`endif + +// Size of LSU Memory Request Queue +`ifndef LSUQ_OUT_SIZE +`define LSUQ_OUT_SIZE `MAX(`LSUQ_IN_SIZE, `LSU_LINE_SIZE / (`XLEN / 8)) +`endif + +// Floating-Point Units /////////////////////////////////////////////////////// + +// Size of FPU Request Queue +`ifndef FPUQ_SIZE +`define FPUQ_SIZE (2 * (`SIMD_WIDTH / `NUM_FPU_LANES)) +`endif + +// FNCP Latency +`ifndef LATENCY_FNCP +`define LATENCY_FNCP 2 +`endif + +// FMA Latency +`ifndef LATENCY_FMA +`ifdef FPU_DPI +`define LATENCY_FMA 4 +`endif +`ifdef FPU_FPNEW +`define LATENCY_FMA 4 +`endif +`ifdef FPU_DSP +`ifdef QUARTUS +`define LATENCY_FMA 4 +`endif +`ifdef VIVADO +`define LATENCY_FMA 16 +`endif +`ifndef LATENCY_FMA +`define LATENCY_FMA 4 +`endif +`endif +`endif + +// FDIV Latency +`ifndef LATENCY_FDIV +`ifdef FPU_DPI +`define LATENCY_FDIV 15 +`endif +`ifdef FPU_FPNEW +`define LATENCY_FDIV 16 +`endif +`ifdef FPU_DSP +`ifdef QUARTUS +`define LATENCY_FDIV 15 +`endif +`ifdef VIVADO +`define LATENCY_FDIV 28 +`endif +`ifndef LATENCY_FDIV +`define LATENCY_FDIV 16 +`endif +`endif +`endif + +// FSQRT Latency +`ifndef LATENCY_FSQRT +`ifdef FPU_DPI +`define LATENCY_FSQRT 10 +`endif +`ifdef FPU_FPNEW +`define LATENCY_FSQRT 16 +`endif +`ifdef FPU_DSP +`ifdef QUARTUS +`define LATENCY_FSQRT 10 +`endif +`ifdef VIVADO +`define LATENCY_FSQRT 28 +`endif +`ifndef LATENCY_FSQRT +`define LATENCY_FSQRT 16 +`endif +`endif +`endif + +// FCVT Latency +`ifndef LATENCY_FCVT +`define LATENCY_FCVT 5 +`endif + +// FMA Bandwidth ratio +`ifndef FMA_PE_RATIO +`define FMA_PE_RATIO 1 +`endif + +// FDIV Bandwidth ratio +`ifndef FDIV_PE_RATIO +`define FDIV_PE_RATIO 8 +`endif + +// FSQRT Bandwidth ratio +`ifndef FSQRT_PE_RATIO +`define FSQRT_PE_RATIO 8 +`endif + +// FCVT Bandwidth ratio +`ifndef FCVT_PE_RATIO +`define FCVT_PE_RATIO 8 +`endif + +// FNCP Bandwidth ratio +`ifndef FNCP_PE_RATIO +`define FNCP_PE_RATIO 2 +`endif + +// Icache Configurable Knobs ////////////////////////////////////////////////// + +// Cache Enable +`ifndef ICACHE_DISABLE +`define ICACHE_ENABLE +`endif + +`ifndef ICACHE_ENABLE + `define NUM_ICACHES 0 +`endif + +// Number of Cache Units +`ifndef NUM_ICACHES +`define NUM_ICACHES `UP(`SOCKET_SIZE / 4) +`endif + +// Cache Size +`ifndef ICACHE_SIZE +`define ICACHE_SIZE 16384 +`endif + +// Core Response Queue Size +`ifndef ICACHE_CRSQ_SIZE +`define ICACHE_CRSQ_SIZE 2 +`endif + +// Miss Handling Register Size +`ifndef ICACHE_MSHR_SIZE +`define ICACHE_MSHR_SIZE 16 +`endif + +// Memory Request Queue Size +`ifndef ICACHE_MREQ_SIZE +`define ICACHE_MREQ_SIZE 4 +`endif + +// Memory Response Queue Size +`ifndef ICACHE_MRSQ_SIZE +`define ICACHE_MRSQ_SIZE 0 +`endif + +// Number of Associative Ways +`ifndef ICACHE_NUM_WAYS +`define ICACHE_NUM_WAYS 4 +`endif + +// Replacement Policy +`ifndef ICACHE_REPL_POLICY +`define ICACHE_REPL_POLICY 1 +`endif + +`ifndef ICACHE_MEM_PORTS +`define ICACHE_MEM_PORTS 1 +`endif + +// Dcache Configurable Knobs ////////////////////////////////////////////////// + +// Cache Enable +`ifndef DCACHE_DISABLE +`define DCACHE_ENABLE +`endif + +`ifndef DCACHE_ENABLE + `define NUM_DCACHES 0 + `define DCACHE_NUM_BANKS 1 +`endif + +// Number of Cache Units +`ifndef NUM_DCACHES +`define NUM_DCACHES `UP(`SOCKET_SIZE / 4) +`endif + +// Cache Size +`ifndef DCACHE_SIZE +`define DCACHE_SIZE 16384 +`endif + +// Number of Banks +`ifndef DCACHE_NUM_BANKS +`define DCACHE_NUM_BANKS `MIN(DCACHE_NUM_REQS, 16) +`endif + +// Core Response Queue Size +`ifndef DCACHE_CRSQ_SIZE +`define DCACHE_CRSQ_SIZE 2 +`endif + +// Miss Handling Register Size +`ifndef DCACHE_MSHR_SIZE +`define DCACHE_MSHR_SIZE 16 +`endif + +// Memory Request Queue Size +`ifndef DCACHE_MREQ_SIZE +`define DCACHE_MREQ_SIZE 4 +`endif + +// Memory Response Queue Size +`ifndef DCACHE_MRSQ_SIZE +`define DCACHE_MRSQ_SIZE 4 +`endif + +// Number of Associative Ways +`ifndef DCACHE_NUM_WAYS +`define DCACHE_NUM_WAYS 4 +`endif + +// Enable Cache Writeback +`ifndef DCACHE_WRITEBACK +`define DCACHE_WRITEBACK 0 +`endif + +// Enable Cache Dirty bytes +`ifndef DCACHE_DIRTYBYTES +`define DCACHE_DIRTYBYTES `DCACHE_WRITEBACK +`endif + +// Replacement Policy +`ifndef DCACHE_REPL_POLICY +`define DCACHE_REPL_POLICY 1 +`endif + +// Number of Memory Ports +`ifndef L1_MEM_PORTS +`ifdef L1_DISABLE +`define L1_MEM_PORTS `MIN(DCACHE_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS) +`else +`define L1_MEM_PORTS `MIN(`DCACHE_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS) +`endif +`endif + +// LMEM Configurable Knobs //////////////////////////////////////////////////// + +`ifndef LMEM_DISABLE +`define LMEM_ENABLE +`endif + +`ifndef LMEM_ENABLE + `define LMEM_NUM_BANKS 1 +`endif + +// Number of Banks +`ifndef LMEM_NUM_BANKS +`define LMEM_NUM_BANKS `NUM_LSU_LANES +`endif + +// L2cache Configurable Knobs ///////////////////////////////////////////////// + +// Cache Size +`ifndef L2_CACHE_SIZE +`define L2_CACHE_SIZE 1048576 +`endif + +// Number of Banks +`ifndef L2_NUM_BANKS +`define L2_NUM_BANKS `MIN(L2_NUM_REQS, 16) +`endif + +// Core Response Queue Size +`ifndef L2_CRSQ_SIZE +`define L2_CRSQ_SIZE 2 +`endif + +// Miss Handling Register Size +`ifndef L2_MSHR_SIZE +`define L2_MSHR_SIZE 16 +`endif + +// Memory Request Queue Size +`ifndef L2_MREQ_SIZE +`define L2_MREQ_SIZE 4 +`endif + +// Memory Response Queue Size +`ifndef L2_MRSQ_SIZE +`define L2_MRSQ_SIZE 4 +`endif + +// Number of Associative Ways +`ifndef L2_NUM_WAYS +`define L2_NUM_WAYS 8 +`endif + +// Enable Cache Writeback +`ifndef L2_WRITEBACK +`define L2_WRITEBACK 0 +`endif + +// Enable Cache Dirty bytes +`ifndef L2_DIRTYBYTES +`define L2_DIRTYBYTES `L2_WRITEBACK +`endif + +// Replacement Policy +`ifndef L2_REPL_POLICY +`define L2_REPL_POLICY 1 +`endif + +// Number of Memory Ports +`ifndef L2_MEM_PORTS +`ifdef L2_ENABLE +`define L2_MEM_PORTS `MIN(`L2_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS) +`else +`define L2_MEM_PORTS `MIN(L2_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS) +`endif +`endif + +// L3cache Configurable Knobs ///////////////////////////////////////////////// + +// Cache Size +`ifndef L3_CACHE_SIZE +`define L3_CACHE_SIZE 2097152 +`endif + +// Number of Banks +`ifndef L3_NUM_BANKS +`define L3_NUM_BANKS `MIN(L3_NUM_REQS, 16) +`endif + +// Core Response Queue Size +`ifndef L3_CRSQ_SIZE +`define L3_CRSQ_SIZE 2 +`endif + +// Miss Handling Register Size +`ifndef L3_MSHR_SIZE +`define L3_MSHR_SIZE 16 +`endif + +// Memory Request Queue Size +`ifndef L3_MREQ_SIZE +`define L3_MREQ_SIZE 4 +`endif + +// Memory Response Queue Size +`ifndef L3_MRSQ_SIZE +`define L3_MRSQ_SIZE 4 +`endif + +// Number of Associative Ways +`ifndef L3_NUM_WAYS +`define L3_NUM_WAYS 8 +`endif + +// Enable Cache Writeback +`ifndef L3_WRITEBACK +`define L3_WRITEBACK 0 +`endif + +// Enable Cache Dirty bytes +`ifndef L3_DIRTYBYTES +`define L3_DIRTYBYTES `L3_WRITEBACK +`endif + +// Replacement Policy +`ifndef L3_REPL_POLICY +`define L3_REPL_POLICY 1 +`endif + +// Number of Memory Ports +`ifndef L3_MEM_PORTS +`ifdef L3_ENABLE +`define L3_MEM_PORTS `MIN(`L3_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS) +`else +`define L3_MEM_PORTS `MIN(L3_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS) +`endif +`endif + +// TCU Configurable Knobs ///////////////////////////////////////////////////// + +`ifndef TCU_DRL +`ifndef TCU_BHF +`ifndef TCU_DSP +`ifndef TCU_DPI + +`ifndef SYNTHESIS +`ifndef DPI_DISABLE +`define TCU_DPI +`else +`define TCU_BHF +`endif +`else +`define TCU_DSP +`endif + +`endif +`endif +`endif +`endif + +// ISA Extensions ///////////////////////////////////////////////////////////// + +`ifdef ICACHE_ENABLE + `define ICACHE_ENABLED 1 +`else + `define ICACHE_ENABLED 0 +`endif + +`ifdef DCACHE_ENABLE + `define DCACHE_ENABLED 1 +`else + `define DCACHE_ENABLED 0 +`endif + +`ifdef LMEM_ENABLE + `define LMEM_ENABLED 1 +`else + `define LMEM_ENABLED 0 +`endif + +`ifdef GBAR_ENABLE + `define GBAR_ENABLED 1 +`else + `define GBAR_ENABLED 0 +`endif + +`ifdef L2_ENABLE + `define L2_ENABLED 1 +`else + `define L2_ENABLED 0 +`endif + +`ifdef L3_ENABLE + `define L3_ENABLED 1 +`else + `define L3_ENABLED 0 +`endif + +`ifdef EXT_A_ENABLE + `define EXT_A_ENABLED 1 +`else + `define EXT_A_ENABLED 0 +`endif + +`ifdef EXT_C_ENABLE + `define EXT_C_ENABLED 1 +`else + `define EXT_C_ENABLED 0 +`endif + +`ifdef EXT_D_ENABLE + `define EXT_D_ENABLED 1 +`else + `define EXT_D_ENABLED 0 +`endif + +`ifdef EXT_F_ENABLE + `define EXT_F_ENABLED 1 +`else + `define EXT_F_ENABLED 0 +`endif + +`ifdef EXT_M_ENABLE + `define EXT_M_ENABLED 1 +`else + `define EXT_M_ENABLED 0 +`endif + +`ifdef EXT_V_ENABLE + `define EXT_V_ENABLED 1 +`else + `define EXT_V_ENABLED 0 +`endif + +`ifdef EXT_ZICOND_ENABLE + `define EXT_ZICOND_ENABLED 1 +`else + `define EXT_ZICOND_ENABLED 0 +`endif + +`ifdef EXT_TCU_ENABLE + `define EXT_TCU_ENABLED 1 +`else + `define EXT_TCU_ENABLED 0 +`endif + +`define ISA_STD_A 0 +`define ISA_STD_C 2 +`define ISA_STD_D 3 +`define ISA_STD_E 4 +`define ISA_STD_F 5 +`define ISA_STD_H 7 +`define ISA_STD_I 8 +`define ISA_STD_N 13 +`define ISA_STD_Q 16 +`define ISA_STD_S 18 +`define ISA_STD_V 21 + +`define ISA_EXT_ICACHE 0 +`define ISA_EXT_DCACHE 1 +`define ISA_EXT_L2CACHE 2 +`define ISA_EXT_L3CACHE 3 +`define ISA_EXT_LMEM 4 +`define ISA_EXT_ZICOND 5 +`define ISA_EXT_TCU 6 + +`define MISA_EXT (`ICACHE_ENABLED << `ISA_EXT_ICACHE) \ + | (`DCACHE_ENABLED << `ISA_EXT_DCACHE) \ + | (`L2_ENABLED << `ISA_EXT_L2CACHE) \ + | (`L3_ENABLED << `ISA_EXT_L3CACHE) \ + | (`LMEM_ENABLED << `ISA_EXT_LMEM) \ + | (`EXT_ZICOND_ENABLED << `ISA_EXT_ZICOND) \ + | (`EXT_TCU_ENABLED << `ISA_EXT_TCU) \ + +`define MISA_STD (`EXT_A_ENABLED << 0) /* A - Atomic Instructions extension */ \ + | (0 << 1) /* B - Tentatively reserved for Bit operations extension */ \ + | (`EXT_C_ENABLED << 2) /* C - Compressed extension */ \ + | (`EXT_D_ENABLED << 3) /* D - Double precsision floating-point extension */ \ + | (0 << 4) /* E - RV32E base ISA */ \ + | (`EXT_F_ENABLED << 5) /* F - Single precsision floating-point extension */ \ + | (0 << 6) /* G - Additional standard extensions present */ \ + | (0 << 7) /* H - Hypervisor mode implemented */ \ + | (1 << 8) /* I - RV32I/64I/128I base ISA */ \ + | (0 << 9) /* J - Reserved */ \ + | (0 << 10) /* K - Reserved */ \ + | (0 << 11) /* L - Tentatively reserved for Bit operations extension */ \ + | (`EXT_M_ENABLED << 12) /* M - Integer Multiply/Divide extension */ \ + | (0 << 13) /* N - User level interrupts supported */ \ + | (0 << 14) /* O - Reserved */ \ + | (0 << 15) /* P - Tentatively reserved for Packed-SIMD extension */ \ + | (0 << 16) /* Q - Quad-precision floating-point extension */ \ + | (0 << 17) /* R - Reserved */ \ + | (0 << 18) /* S - Supervisor mode implemented */ \ + | (0 << 19) /* T - Tentatively reserved for Transactional Memory extension */ \ + | (1 << 20) /* U - User mode implemented */ \ + | (`EXT_V_ENABLED << 21) /* V - Tentatively reserved for Vector extension */ \ + | (0 << 22) /* W - Reserved */ \ + | (1 << 23) /* X - Non-standard extensions present */ \ + | (0 << 24) /* Y - Reserved */ \ + | (0 << 25) /* Z - Reserved */ + +// Device identification ////////////////////////////////////////////////////// + +`define VENDOR_ID 0 +`define ARCHITECTURE_ID 0 +`define IMPLEMENTATION_ID 0 + +`endif // VX_CONFIG_VH diff --git a/designs/src/vortex/rtl/VX_define.vh b/designs/src/vortex/rtl/VX_define.vh new file mode 100644 index 0000000..4ef53b0 --- /dev/null +++ b/designs/src/vortex/rtl/VX_define.vh @@ -0,0 +1,470 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_DEFINE_VH +`define VX_DEFINE_VH + +`include "VX_platform.vh" +`include "VX_config.vh" +`include "VX_types.vh" + +`ifdef ICACHE_ENABLE + `define L1_ENABLE +`endif + +`ifdef DCACHE_ENABLE + `define L1_ENABLE +`endif + +`ifndef NDEBUG +`define UUID_ENABLE +`else +`ifdef SCOPE +`define UUID_ENABLE +`endif +`endif + +/////////////////////////////////////////////////////////////////////////////// + +`define ITF_TO_AOS(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + wire [(count)-1:0] prefix``_ready; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign prefix``_valid[i] = itf[i].valid; \ + assign prefix``_data[i] = itf[i].data; \ + assign itf[i].ready = prefix``_ready[i]; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define AOS_TO_ITF(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + wire [(count)-1:0] prefix``_ready; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign itf[i].valid = prefix``_valid[i]; \ + assign itf[i].data = prefix``_data[i]; \ + assign prefix``_ready[i] = itf[i].ready; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define ITF_TO_AOS_V(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign prefix``_valid[i] = itf[i].valid; \ + assign prefix``_data[i] = itf[i].data; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define AOS_TO_ITF_V(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign itf[i].valid = prefix``_valid[i]; \ + assign itf[i].data = prefix``_data[i]; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define ITF_TO_AOS_REQ(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + wire [(count)-1:0] prefix``_ready; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign prefix``_valid[i] = itf[i].req_valid; \ + assign prefix``_data[i] = itf[i].req_data; \ + assign itf[i].req_ready = prefix``_ready[i]; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define AOS_TO_ITF_REQ(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + wire [(count)-1:0] prefix``_ready; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign itf[i].req_valid = prefix``_valid[i]; \ + assign itf[i].req_data = prefix``_data[i]; \ + assign prefix``_ready[i] = itf[i].req_ready; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define ITF_TO_AOS_REQ_V(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign prefix``_valid[i] = itf[i].req_valid; \ + assign prefix``_data[i] = itf[i].req_data; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define AOS_TO_ITF_REQ_V(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign itf[i].req_valid = prefix``_valid[i]; \ + assign itf[i].req_data = prefix``_data[i]; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define ITF_TO_AOS_RSP(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + wire [(count)-1:0] prefix``_ready; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign prefix``_valid[i] = itf[i].rsp_valid; \ + assign prefix``_data[i] = itf[i].rsp_data; \ + assign itf[i].rsp_ready = prefix``_ready[i]; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define AOS_TO_ITF_RSP(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + wire [(count)-1:0] prefix``_vready; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign itf[i].rsp_valid = prefix``_valid[i]; \ + assign itf[i].rsp_data = prefix``_data[i]; \ + assign prefix``_ready[i] = itf[i].rsp_ready; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define ITF_TO_AOS_RSP_V(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign prefix``_valid[i] = itf[i].rsp_valid; \ + assign prefix``_data[i] = itf[i].rsp_data; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define AOS_TO_ITF_RSP_V(prefix, itf, count, dataw) \ + wire [(count)-1:0] prefix``_valid; \ + wire [(count)-1:0][(dataw)-1:0] prefix``_data; \ + /* verilator lint_off GENUNNAMED */ \ + for (genvar i = 0; i < (count); ++i) begin \ + assign itf[i].rsp_valid = prefix``_valid[i]; \ + assign itf[i].rsp_data = prefix``_data[i]; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define REDUCE(__op, __out, __in, __n, __outw) \ + /* verilator lint_off GENUNNAMED */ \ + if (__n > 1) begin \ + reg [(__outw)-1:0] result; \ + always @(*) begin \ + result = (__outw)'(__in[0]); \ + for (integer __i = 1; __i < __n; __i++) begin \ + result = result __op (__outw)'(__in[__i]); \ + end \ + end \ + assign __out = result; \ + end else begin \ + assign __out = (__outw)'(__in[0]); \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define REDUCE_TREE(__op, __out, __in, __n, __outw, __inw) \ + VX_reduce_tree #( \ + .IN_W (__inw), \ + .OUT_W (__outw), \ + .N (__n), \ + .OP ("__op") \ + ) reduce`__LINE__ ( \ + .data_in(__in), \ + .data_out(__out) \ + ) + +`define POP_COUNT_EX(out, in, model) \ + VX_popcount #( \ + .N ($bits(in)), \ + .MODEL (model) \ + ) __pop_count_ex`__LINE__ ( \ + .data_in (in), \ + .data_out (out) \ + ) + +`define POP_COUNT(out, in) `POP_COUNT_EX(out, in, 1) + +`define CONCAT(out, left_in, right_in, L, R) \ + /* verilator lint_off GENUNNAMED */ \ + if ((L) != 0 && (R) == 0) begin \ + assign out = left_in; \ + end else if ((L) == 0 && (R) != 0) begin \ + assign out = right_in; \ + end else if ((L) != 0 && (R) != 0) begin \ + assign out = {left_in, right_in}; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define BUFFER_EX(dst, src, ena, resetw, latency) \ + VX_pipe_register #( \ + .DATAW ($bits(dst)), \ + .RESETW (resetw), \ + .DEPTH (latency) \ + ) __buffer_ex`__LINE__ ( \ + .clk (clk), \ + .reset (reset), \ + .enable (ena), \ + .data_in (src), \ + .data_out (dst) \ + ) + +`define BUFFER(dst, src) `BUFFER_EX(dst, src, 1'b1, $bits(dst), 1) + +`define NEG_EDGE(dst, src) \ + VX_edge_trigger #( \ + .POS (0), \ + .INIT (0) \ + ) __neg_edge`__LINE__ ( \ + .clk (clk), \ + .reset (1'b0), \ + .data_in (src), \ + .data_out (dst) \ + ) + +/////////////////////////////////////////////////////////////////////////////// + +`define ARB_SEL_BITS(I, O) ((I > O) ? `CLOG2(`CDIV(I, O)) : 0) + +/////////////////////////////////////////////////////////////////////////////// + +`define CACHE_MEM_TAG_WIDTH(mshr_size, num_banks, mem_ports, uuid_width) \ + (uuid_width + `CLOG2(mshr_size) + `CLOG2(`CDIV(num_banks, mem_ports))) + +`define CACHE_BYPASS_TAG_WIDTH(num_reqs, mem_ports, line_size, word_size, tag_width) \ + (`CLOG2(`CDIV(num_reqs, mem_ports)) + `CLOG2(line_size / word_size) + tag_width) + +`define CACHE_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, mem_ports, line_size, word_size, tag_width, uuid_width) \ + (`MAX(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks, mem_ports, uuid_width), `CACHE_BYPASS_TAG_WIDTH(num_reqs, mem_ports, line_size, word_size, tag_width)) + 1) + +/////////////////////////////////////////////////////////////////////////////// + +`define CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches) \ + (tag_width + `ARB_SEL_BITS(num_inputs, `UP(num_caches))) + +`define CACHE_CLUSTER_MEM_ARB_TAG(tag_width, num_caches) \ + (tag_width + `ARB_SEL_BITS(`UP(num_caches), 1)) + +`define CACHE_CLUSTER_MEM_TAG_WIDTH(mshr_size, num_banks, mem_ports, num_caches, uuid_width) \ + `CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_MEM_TAG_WIDTH(mshr_size, num_banks, mem_ports, uuid_width), num_caches) + +`define CACHE_CLUSTER_BYPASS_MEM_TAG_WIDTH(num_reqs, mem_ports, line_size, word_size, tag_width, num_inputs, num_caches) \ + `CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_BYPASS_TAG_WIDTH(num_reqs, mem_ports, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches)), num_caches) + +`define CACHE_CLUSTER_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, mem_ports, line_size, word_size, tag_width, num_inputs, num_caches, uuid_width) \ + `CACHE_CLUSTER_MEM_ARB_TAG(`CACHE_NC_MEM_TAG_WIDTH(mshr_size, num_banks, num_reqs, mem_ports, line_size, word_size, `CACHE_CLUSTER_CORE_ARB_TAG(tag_width, num_inputs, num_caches), uuid_width), num_caches) + +`define TO_FULL_ADDR(x) {x, (`MEM_ADDR_WIDTH-$bits(x))'(0)} + +/////////////////////////////////////////////////////////////////////////////// + +`define ASSIGN_VX_IF(dst, src) \ + assign dst.valid = src.valid; \ + assign dst.data = src.data; \ + assign src.ready = dst.ready + +`define ASSIGN_VX_MEM_BUS_IF(dst, src) \ + assign dst.req_valid = src.req_valid; \ + assign dst.req_data = src.req_data; \ + assign src.req_ready = dst.req_ready; \ + assign src.rsp_valid = dst.rsp_valid; \ + assign src.rsp_data = dst.rsp_data; \ + assign dst.rsp_ready = src.rsp_ready + +`define ASSIGN_VX_MEM_BUS_RO_IF(dst, src) \ + assign dst.req_valid = src.req_valid; \ + assign dst.req_data.rw = 0; \ + assign dst.req_data.addr = src.req_data.addr; \ + assign dst.req_data.data = '0; \ + assign dst.req_data.byteen = '1; \ + assign dst.req_data.flags = src.req_data.flags; \ + assign dst.req_data.tag = src.req_data.tag; \ + assign src.req_ready = dst.req_ready; \ + assign src.rsp_valid = dst.rsp_valid; \ + assign src.rsp_data.data = dst.rsp_data.data; \ + assign src.rsp_data.tag = dst.rsp_data.tag; \ + assign dst.rsp_ready = src.rsp_ready + +`define ASSIGN_VX_MEM_BUS_IF_EX(dst, src, TD, TS, UUID) \ + /* verilator lint_off GENUNNAMED */ \ + assign dst.req_valid = src.req_valid; \ + assign dst.req_data.rw = src.req_data.rw; \ + assign dst.req_data.addr = src.req_data.addr; \ + assign dst.req_data.data = src.req_data.data; \ + assign dst.req_data.byteen = src.req_data.byteen; \ + assign dst.req_data.flags = src.req_data.flags; \ + if (TD != TS) begin \ + if (UUID != 0) begin \ + if (TD > TS) begin \ + assign dst.req_data.tag = {src.req_data.tag.uuid, {(TD-TS){1'b0}}, src.req_data.tag.value}; \ + end else begin \ + assign dst.req_data.tag = {src.req_data.tag.uuid, src.req_data.tag.value[TD-UUID-1:0]}; \ + end \ + end else begin \ + if (TD > TS) begin \ + assign dst.req_data.tag = {{(TD-TS){1'b0}}, src.req_data.tag}; \ + end else begin \ + assign dst.req_data.tag = src.req_data.tag[TD-1:0]; \ + end \ + end \ + end else begin \ + assign dst.req_data.tag = src.req_data.tag; \ + end \ + assign src.req_ready = dst.req_ready; \ + assign src.rsp_valid = dst.rsp_valid; \ + assign src.rsp_data.data = dst.rsp_data.data; \ + if (TD != TS) begin \ + if (UUID != 0) begin \ + if (TD > TS) begin \ + assign src.rsp_data.tag = {dst.rsp_data.tag.uuid, dst.rsp_data.tag.value[TS-UUID-1:0]}; \ + end else begin \ + assign src.rsp_data.tag = {dst.rsp_data.tag.uuid, {(TS-TD){1'b0}}, dst.rsp_data.tag.value}; \ + end \ + end else begin \ + if (TD > TS) begin \ + assign src.rsp_data.tag = dst.rsp_data.tag[TS-1:0]; \ + end else begin \ + assign src.rsp_data.tag = {{(TS-TD){1'b0}}, dst.rsp_data.tag}; \ + end \ + end \ + end else begin \ + assign src.rsp_data.tag = dst.rsp_data.tag; \ + end \ + assign dst.rsp_ready = src.rsp_ready \ + /* verilator lint_off GENUNNAMED */ + +`define INIT_VX_MEM_BUS_IF(itf) \ + assign itf.req_valid = 0; \ + assign itf.req_data = '0; \ + `UNUSED_VAR (itf.req_ready) \ + `UNUSED_VAR (itf.rsp_valid) \ + `UNUSED_VAR (itf.rsp_data) \ + assign itf.rsp_ready = 0; + +`define UNUSED_VX_MEM_BUS_IF(itf) \ + `UNUSED_VAR (itf.req_valid) \ + `UNUSED_VAR (itf.req_data) \ + assign itf.req_ready = 0; \ + assign itf.rsp_valid = 0; \ + assign itf.rsp_data = '0; \ + `UNUSED_VAR (itf.rsp_ready) + +`define BUFFER_DCR_BUS_IF(dst, src, ena, latency) \ + /* verilator lint_off GENUNNAMED */ \ + if (latency != 0) begin \ + VX_pipe_register #( \ + .DATAW (1 + VX_DCR_ADDR_WIDTH + VX_DCR_DATA_WIDTH), \ + .DEPTH (latency) \ + ) pipe_reg ( \ + .clk (clk), \ + .reset (1'b0), \ + .enable (1'b1), \ + .data_in ({src.write_valid && ena, src.write_addr, src.write_data}), \ + .data_out ({dst.write_valid, dst.write_addr, dst.write_data}) \ + ); \ + end else begin \ + assign {dst.write_valid, dst.write_addr, dst.write_data} = {src.write_valid && ena, src.write_addr, src.write_data}; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define PERF_COUNTER_ADD(dst, src, field, width, count, reg_enable) \ + /* verilator lint_off GENUNNAMED */ \ + if ((count) > 1) begin \ + wire [(count)-1:0][(width)-1:0] __reduce_add_i_field; \ + wire [(width)-1:0] __reduce_add_o_field; \ + for (genvar __i = 0; __i < (count); ++__i) begin \ + assign __reduce_add_i_field[__i] = src[__i].``field; \ + end \ + VX_reduce_tree #( \ + .IN_W (width), \ + .N (count), \ + .OP ("+") \ + ) __reduce_add_field ( \ + __reduce_add_i_field, \ + __reduce_add_o_field \ + ); \ + if (reg_enable) begin \ + reg [(width)-1:0] __reduce_add_r_field; \ + always @(posedge clk) begin \ + if (reset) begin \ + __reduce_add_r_field <= '0; \ + end else begin \ + __reduce_add_r_field <= __reduce_add_o_field; \ + end \ + end \ + assign dst.``field = __reduce_add_r_field; \ + end else begin \ + assign dst.``field = __reduce_add_o_field; \ + end \ + end else begin \ + assign dst.``field = src[0].``field; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define ASSIGN_BLOCKED_WID(dst, src, block_idx, block_size) \ + /* verilator lint_off GENUNNAMED */ \ + if (block_size != 1) begin \ + if (block_size != `NUM_WARPS) begin \ + assign dst = {src[NW_WIDTH-1:`CLOG2(block_size)], `CLOG2(block_size)'(block_idx)}; \ + end else begin \ + assign dst = NW_WIDTH'(block_idx); \ + end \ + end else begin \ + assign dst = src; \ + end \ + /* verilator lint_off GENUNNAMED */ + +`define DECL_EXECUTE_T(__name__, __lanes__) \ + typedef struct packed { \ + logic [UUID_WIDTH-1:0] uuid; \ + logic [NW_WIDTH-1:0] wid; \ + logic [__lanes__-1:0] tmask; \ + logic [PC_BITS-1:0] PC; \ + logic [INST_ALU_BITS-1:0] op_type; \ + op_args_t op_args; \ + logic wb; \ + logic [NUM_REGS_BITS-1:0] rd; \ + logic [__lanes__-1:0][`XLEN-1:0] rs1_data; \ + logic [__lanes__-1:0][`XLEN-1:0] rs2_data; \ + logic [__lanes__-1:0][`XLEN-1:0] rs3_data; \ + logic [`LOG2UP(`NUM_THREADS / __lanes__)-1:0] pid; \ + logic sop; \ + logic eop; \ + } __name__ + +`define DECL_RESULT_T(__name__, __lanes__) \ + typedef struct packed { \ + logic [UUID_WIDTH-1:0] uuid; \ + logic [NW_WIDTH-1:0] wid; \ + logic [__lanes__-1:0] tmask; \ + logic [PC_BITS-1:0] PC; \ + logic wb; \ + logic [NUM_REGS_BITS-1:0] rd; \ + logic [__lanes__-1:0][`XLEN-1:0] data; \ + logic [`LOG2UP(`NUM_THREADS / __lanes__)-1:0] pid; \ + logic sop; \ + logic eop; \ + } __name__ + +`endif // VX_DEFINE_VH diff --git a/designs/src/vortex/rtl/VX_gpu_pkg.sv b/designs/src/vortex/rtl/VX_gpu_pkg.sv new file mode 100644 index 0000000..f2f00ed --- /dev/null +++ b/designs/src/vortex/rtl/VX_gpu_pkg.sv @@ -0,0 +1,907 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_GPU_PKG_VH +`define VX_GPU_PKG_VH + +`include "VX_define.vh" + +`IGNORE_UNUSED_BEGIN + +package VX_gpu_pkg; + + localparam NC_BITS = `CLOG2(`NUM_CORES); + localparam NW_BITS = `CLOG2(`NUM_WARPS); + localparam NT_BITS = `CLOG2(`NUM_THREADS); + localparam NB_BITS = `CLOG2(`NUM_BARRIERS); + + localparam NC_WIDTH = `UP(NC_BITS); + localparam NW_WIDTH = `UP(NW_BITS); + localparam NT_WIDTH = `UP(NT_BITS); + localparam NB_WIDTH = `UP(NB_BITS); + + localparam XLENB = `XLEN / 8; + + localparam RV_REGS = 32; + localparam RV_REGS_BITS = 5; + + localparam REG_TYPE_I = 0; + localparam REG_TYPE_F = 1; + +`ifdef EXT_F_ENABLE + localparam REG_TYPES = 2; +`else + localparam REG_TYPES = 1; +`endif + + localparam NUM_REGS = (REG_TYPES * RV_REGS); + + localparam REG_TYPE_BITS = `LOG2UP(REG_TYPES); + + localparam NUM_REGS_BITS = `CLOG2(NUM_REGS); + + localparam DV_STACK_SIZE = `UP(`NUM_THREADS-1); + localparam DV_STACK_SIZEW = `UP(`CLOG2(DV_STACK_SIZE)); + + localparam PERF_CTR_BITS = 44; + + localparam SIMD_COUNT = `NUM_THREADS / `SIMD_WIDTH; + localparam SIMD_IDX_BITS = `CLOG2(SIMD_COUNT); + localparam SIMD_IDX_W = `UP(SIMD_IDX_BITS); + + localparam NUM_OPCS_BITS = `CLOG2(`NUM_OPCS); + localparam NUM_OPCS_W = `UP(NUM_OPCS_BITS); + +`ifndef NDEBUG + localparam UUID_WIDTH = 44; +`else +`ifdef SCOPE + localparam UUID_WIDTH = 44; +`else + localparam UUID_WIDTH = 1; +`endif +`endif + +`ifndef NDEBUG + localparam PC_BITS = `XLEN; + function automatic logic [`XLEN-1:0] to_fullPC(input logic[PC_BITS-1:0] pc); + to_fullPC = pc; + endfunction + function automatic logic [PC_BITS-1:0] from_fullPC(input logic[`XLEN-1:0] pc); + from_fullPC = pc; + endfunction +`else + localparam PC_BITS = (`XLEN-2); + function automatic logic [`XLEN-1:0] to_fullPC(input logic[PC_BITS-1:0] pc); + to_fullPC = {pc, 2'b0}; + endfunction + function automatic logic [PC_BITS-1:0] from_fullPC(input logic[`XLEN-1:0] pc); + from_fullPC = PC_BITS'(pc >> 2); + endfunction +`endif + + localparam OFFSET_BITS = 12; + + localparam NUM_SRC_OPDS = 3; + localparam SRC_OPD_BITS = `CLOG2(NUM_SRC_OPDS); + localparam SRC_OPD_WIDTH = `UP(SRC_OPD_BITS); + + localparam NUM_SOCKETS = `UP(`NUM_CORES / `SOCKET_SIZE); + + localparam MEM_REQ_FLAG_FLUSH = 0; + localparam MEM_REQ_FLAG_IO = 1; + localparam MEM_REQ_FLAG_LOCAL = 2; // shoud be last since optional + localparam MEM_FLAGS_WIDTH = (MEM_REQ_FLAG_LOCAL + `LMEM_ENABLED); + + localparam VX_DCR_ADDR_WIDTH = `VX_DCR_ADDR_BITS; + localparam VX_DCR_DATA_WIDTH = 32; + + localparam STALL_TIMEOUT = (100000 * (1 ** (`L2_ENABLED + `L3_ENABLED))); + + /////////////////////////////////////////////////////////////////////////// + + localparam EX_ALU = 0; + localparam EX_LSU = 1; + localparam EX_SFU = 2; + localparam EX_FPU = (EX_SFU + `EXT_F_ENABLED); + localparam EX_TCU = (EX_FPU + `EXT_TCU_ENABLED); + + localparam NUM_EX_UNITS = EX_TCU + 1; + localparam EX_BITS = `CLOG2(NUM_EX_UNITS); + localparam EX_WIDTH = `UP(EX_BITS); + + localparam SFU_CSRS = 0; + localparam SFU_WCTL = 1; + + localparam NUM_SFU_UNITS = (2); + localparam SFU_BITS = `CLOG2(NUM_SFU_UNITS); + localparam SFU_WIDTH = `UP(SFU_BITS); + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_LUI = 7'b0110111; + localparam INST_AUIPC = 7'b0010111; + localparam INST_JAL = 7'b1101111; + localparam INST_JALR = 7'b1100111; + localparam INST_B = 7'b1100011; // branch instructions + localparam INST_L = 7'b0000011; // load instructions + localparam INST_S = 7'b0100011; // store instructions + localparam INST_I = 7'b0010011; // immediate instructions + localparam INST_R = 7'b0110011; // register instructions + localparam INST_V = 7'b1010111; // vector instructions + localparam INST_FENCE = 7'b0001111; // Fence instructions + localparam INST_SYS = 7'b1110011; // system instructions + + // RV64I instruction specific opcodes (for any W instruction) + localparam INST_I_W = 7'b0011011; // W type immediate instructions + localparam INST_R_W = 7'b0111011; // W type register instructions + + localparam INST_FL = 7'b0000111; // float load instruction + localparam INST_FS = 7'b0100111; // float store instruction + localparam INST_FMADD = 7'b1000011; + localparam INST_FMSUB = 7'b1000111; + localparam INST_FNMSUB = 7'b1001011; + localparam INST_FNMADD = 7'b1001111; + localparam INST_FCI = 7'b1010011; // float common instructions + + // Custom extension opcodes + localparam INST_EXT1 = 7'b0001011; // 0x0B + localparam INST_EXT2 = 7'b0101011; // 0x2B + localparam INST_EXT3 = 7'b1011011; // 0x5B + localparam INST_EXT4 = 7'b1111011; // 0x7B + + // Opcode extensions + localparam INST_R_F7_MUL = 7'b0000001; + localparam INST_R_F7_ZICOND= 7'b0000111; + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_FRM_RNE = 3'b000; // round to nearest even + localparam INST_FRM_RTZ = 3'b001; // round to zero + localparam INST_FRM_RDN = 3'b010; // round to -inf + localparam INST_FRM_RUP = 3'b011; // round to +inf + localparam INST_FRM_RMM = 3'b100; // round to nearest max magnitude + localparam INST_FRM_DYN = 3'b111; // dynamic mode + localparam INST_FRM_BITS = 3; + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_OP_BITS = 4; + localparam INST_FMT_BITS = 2; + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_ALU_ADD = 4'b0000; + //localparam INST_ALU_UNUSED=4'b0001; + localparam INST_ALU_LUI = 4'b0010; + localparam INST_ALU_AUIPC = 4'b0011; + localparam INST_ALU_SLTU = 4'b0100; + localparam INST_ALU_SLT = 4'b0101; + //localparam INST_ALU_UNUSED=4'b0110; + localparam INST_ALU_SUB = 4'b0111; + localparam INST_ALU_SRL = 4'b1000; + localparam INST_ALU_SRA = 4'b1001; + localparam INST_ALU_CZEQ = 4'b1010; + localparam INST_ALU_CZNE = 4'b1011; + localparam INST_ALU_AND = 4'b1100; + localparam INST_ALU_OR = 4'b1101; + localparam INST_ALU_XOR = 4'b1110; + localparam INST_ALU_SLL = 4'b1111; + localparam INST_ALU_BITS = 4; + + localparam ALU_TYPE_BITS = 2; + localparam ALU_TYPE_ARITH = 0; + localparam ALU_TYPE_BRANCH = 1; + localparam ALU_TYPE_MULDIV = 2; + localparam ALU_TYPE_OTHER = 3; + + function automatic logic [1:0] inst_alu_class(input logic [INST_ALU_BITS-1:0] op); + return op[3:2]; + endfunction + + function automatic logic inst_alu_signed(input logic [INST_ALU_BITS-1:0] op); + return op[0]; + endfunction + + function automatic logic inst_alu_is_sub(input logic [INST_ALU_BITS-1:0] op); + return op[1]; + endfunction + + function automatic logic inst_alu_is_czero(input logic [INST_ALU_BITS-1:0] op); + return (op[3:1] == 3'b101); + endfunction + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_BR_BEQ = 4'b0000; + localparam INST_BR_BNE = 4'b0010; + localparam INST_BR_BLTU = 4'b0100; + localparam INST_BR_BGEU = 4'b0110; + localparam INST_BR_BLT = 4'b0101; + localparam INST_BR_BGE = 4'b0111; + localparam INST_BR_JAL = 4'b1000; + localparam INST_BR_JALR = 4'b1001; + localparam INST_BR_ECALL = 4'b1010; + localparam INST_BR_EBREAK = 4'b1011; + localparam INST_BR_URET = 4'b1100; + localparam INST_BR_SRET = 4'b1101; + localparam INST_BR_MRET = 4'b1110; + localparam INST_BR_OTHER = 4'b1111; + localparam INST_BR_BITS = 4; + + function automatic logic [1:0] inst_br_class(input logic [INST_BR_BITS-1:0] op); + return {1'b0, ~op[3]}; + endfunction + + function automatic logic inst_br_is_neg(input logic [INST_BR_BITS-1:0] op); + return op[1]; + endfunction + + function automatic logic inst_br_is_less(input logic [INST_BR_BITS-1:0] op); + return op[2]; + endfunction + + function automatic logic inst_br_is_static(input logic [INST_BR_BITS-1:0] op); + return op[3]; + endfunction + + /////////////////////////////////////////////////////////////////////////// + + // Shuffle & Vote Extension + + localparam INST_VOTE_ALL = 2'b00; + localparam INST_VOTE_ANY = 2'b01; + localparam INST_VOTE_UNI = 2'b10; + localparam INST_VOTE_BAL = 2'b11; + + localparam INST_SHFL_UP = 2'b00; + localparam INST_SHFL_DOWN = 2'b01; + localparam INST_SHFL_BFLY = 2'b10; + localparam INST_SHFL_IDX = 2'b11; + + localparam INST_VOTE_BITS = 2; + localparam INST_SHFL_BITS = 2; + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_M_MUL = 3'b000; + localparam INST_M_MULHU = 3'b001; + localparam INST_M_MULH = 3'b010; + localparam INST_M_MULHSU = 3'b011; + localparam INST_M_DIV = 3'b100; + localparam INST_M_DIVU = 3'b101; + localparam INST_M_REM = 3'b110; + localparam INST_M_REMU = 3'b111; + localparam INST_M_BITS = 3; + + function automatic logic inst_m_signed(input logic [INST_M_BITS-1:0] op); + return (~op[0]); + endfunction + + function automatic logic inst_m_is_mulx(input logic [INST_M_BITS-1:0] op); + return (~op[2]); + endfunction + + function automatic logic inst_m_is_mulh(input logic [INST_M_BITS-1:0] op); + return (op[1:0] != 0); + endfunction + + function automatic logic inst_m_signed_a(input logic [INST_M_BITS-1:0] op); + return (op[1:0] != 1); + endfunction + + function automatic logic inst_m_is_rem(input logic [INST_M_BITS-1:0] op); + return op[1]; + endfunction + + /////////////////////////////////////////////////////////////////////////// + + localparam LSU_FMT_B = 3'b000; + localparam LSU_FMT_H = 3'b001; + localparam LSU_FMT_W = 3'b010; + localparam LSU_FMT_D = 3'b011; + localparam LSU_FMT_BU = 3'b100; + localparam LSU_FMT_HU = 3'b101; + localparam LSU_FMT_WU = 3'b110; + + localparam INST_LSU_LB = 4'b0000; + localparam INST_LSU_LH = 4'b0001; + localparam INST_LSU_LW = 4'b0010; + localparam INST_LSU_LD = 4'b0011; // new for RV64I LD + localparam INST_LSU_LBU = 4'b0100; + localparam INST_LSU_LHU = 4'b0101; + localparam INST_LSU_LWU = 4'b0110; // new for RV64I LWU + localparam INST_LSU_SB = 4'b1000; + localparam INST_LSU_SH = 4'b1001; + localparam INST_LSU_SW = 4'b1010; + localparam INST_LSU_SD = 4'b1011; // new for RV64I SD + localparam INST_LSU_FENCE = 4'b1111; + localparam INST_LSU_BITS = 4; + + localparam INST_FENCE_BITS = 1; + localparam INST_FENCE_D = 1'h0; + localparam INST_FENCE_I = 1'h1; + + function automatic logic [2:0] inst_lsu_fmt(input logic [INST_LSU_BITS-1:0] op); + return op[2:0]; + endfunction + + function automatic logic [1:0] inst_lsu_wsize(input logic [INST_LSU_BITS-1:0] op); + return op[1:0]; + endfunction + + function automatic logic inst_lsu_is_fence(input logic [INST_LSU_BITS-1:0] op); + return (op[3:2] == 3); + endfunction + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_FPU_ADD = 4'b0000; // SUB=fmt[1] + localparam INST_FPU_MUL = 4'b0001; + localparam INST_FPU_MADD = 4'b0010; // SUB=fmt[1] + localparam INST_FPU_NMADD = 4'b0011; // SUB=fmt[1] + localparam INST_FPU_DIV = 4'b0100; + localparam INST_FPU_SQRT = 4'b0101; + localparam INST_FPU_F2I = 4'b1000; // fmt[0]: F32=0, F64=1, fmt[1]: I32=0, I64=1 + localparam INST_FPU_F2U = 4'b1001; // fmt[0]: F32=0, F64=1, fmt[1]: I32=0, I64=1 + localparam INST_FPU_I2F = 4'b1010; // fmt[0]: F32=0, F64=1, fmt[1]: I32=0, I64=1 + localparam INST_FPU_U2F = 4'b1011; // fmt[0]: F32=0, F64=1, fmt[1]: I32=0, I64=1 + localparam INST_FPU_CMP = 4'b1100; // frm: LE=0, LT=1, EQ=2 + localparam INST_FPU_F2F = 4'b1101; // fmt[0]: F32=0, F64=1 + localparam INST_FPU_MISC = 4'b1110; // frm: SGNJ=0, SGNJN=1, SGNJX=2, CLASS=3, MVXW=4, MVWX=5, FMIN=6, FMAX=7 + localparam INST_FPU_BITS = 4; + + function automatic logic inst_fpu_is_class(input logic [INST_FPU_BITS-1:0] op, input logic [INST_FRM_BITS-1:0] frm); + return (op == INST_FPU_MISC && frm == 3); + endfunction + + function automatic logic inst_fpu_is_mvxw(input logic [INST_FPU_BITS-1:0] op, input logic [INST_FRM_BITS-1:0] frm); + return (op == INST_FPU_MISC && frm == 4); + endfunction + + /////////////////////////////////////////////////////////////////////////// + + localparam INST_SFU_TMC = 4'h0; + localparam INST_SFU_WSPAWN = 4'h1; + localparam INST_SFU_SPLIT = 4'h2; + localparam INST_SFU_JOIN = 4'h3; + localparam INST_SFU_BAR = 4'h4; + localparam INST_SFU_PRED = 4'h5; + localparam INST_SFU_CSRRW = 4'h6; + localparam INST_SFU_CSRRS = 4'h7; + localparam INST_SFU_CSRRC = 4'h8; + localparam INST_SFU_BITS = 4; + + function automatic logic [3:0] inst_sfu_csr(input logic [2:0] funct3); + return (4'h6 + 4'(funct3[1:0]) - 4'h1); + endfunction + + function automatic logic inst_sfu_is_wctl(input logic [INST_SFU_BITS-1:0] op); + return (op <= 5); + endfunction + + function automatic logic inst_sfu_is_csr(input logic [INST_SFU_BITS-1:0] op); + return (op >= 6 && op <= 8); + endfunction + + /////////////////////////////// Issue parameters ////////////////////////// + + localparam ISSUE_ISW_BITS = `CLOG2(`ISSUE_WIDTH); + localparam ISSUE_ISW_W = `UP(ISSUE_ISW_BITS); + localparam PER_ISSUE_WARPS = `NUM_WARPS / `ISSUE_WIDTH; + localparam ISSUE_WIS_BITS = `CLOG2(PER_ISSUE_WARPS); + localparam ISSUE_WIS_W = `UP(ISSUE_WIS_BITS); + + function automatic logic [NW_WIDTH-1:0] wis_to_wid( + input logic [ISSUE_WIS_W-1:0] wis, + input logic [ISSUE_ISW_W-1:0] isw + ); + if (ISSUE_WIS_BITS == 0) begin + wis_to_wid = NW_WIDTH'(isw); + end else if (ISSUE_ISW_BITS == 0) begin + wis_to_wid = NW_WIDTH'(wis); + end else begin + wis_to_wid = NW_WIDTH'({wis, isw}); + end + endfunction + + function automatic logic [ISSUE_ISW_W-1:0] wid_to_isw( + input logic [NW_WIDTH-1:0] wid + ); + if (ISSUE_ISW_BITS != 0) begin + wid_to_isw = wid[ISSUE_ISW_W-1:0]; + end else begin + wid_to_isw = 0; + end + endfunction + + function automatic logic [ISSUE_WIS_W-1:0] wid_to_wis( + input logic [NW_WIDTH-1:0] wid + ); + if (ISSUE_WIS_BITS != 0) begin + wid_to_wis = ISSUE_WIS_W'(wid >> ISSUE_ISW_BITS); + end else begin + wid_to_wis = 0; + end + endfunction + + /////////////////////////////// TENSOR UNIT /////////////////////////////// + +`ifdef EXT_TCU_ENABLE + + localparam INST_TCU_WMMA = 4'h0; + localparam INST_TCU_BITS = 4; + +`endif + + /////////////////////////////////////////////////////////////////////////// + + typedef struct packed { + logic valid; + logic [`NUM_THREADS-1:0] tmask; + } tmc_t; + + typedef struct packed { + logic valid; + logic [`NUM_WARPS-1:0] wmask; + logic [PC_BITS-1:0] pc; + } wspawn_t; + + typedef struct packed { + logic valid; + logic is_dvg; + logic [`NUM_THREADS-1:0] then_tmask; + logic [`NUM_THREADS-1:0] else_tmask; + logic [PC_BITS-1:0] next_pc; + } split_t; + + typedef struct packed { + logic valid; + logic [DV_STACK_SIZEW-1:0] stack_ptr; + } join_t; + + typedef struct packed { + logic valid; + logic [NB_WIDTH-1:0] id; + logic is_global; + `ifdef GBAR_ENABLE + logic [`MAX(NW_WIDTH, NC_WIDTH)-1:0] size_m1; + `else + logic [NW_WIDTH-1:0] size_m1; + `endif + logic is_noop; + } barrier_t; + + typedef struct packed { + logic [`XLEN-1:0] startup_addr; + logic [`XLEN-1:0] startup_arg; + logic [7:0] mpm_class; + } base_dcrs_t; + + //////////////////////// instruction arguments //////////////////////////// + + localparam INST_ARGS_BITS = ALU_TYPE_BITS + `XLEN + 3; + + typedef struct packed { + logic use_PC; + logic use_imm; + logic is_w; + logic [ALU_TYPE_BITS-1:0] xtype; + logic [`XLEN-1:0] imm; + } alu_args_t; + `PACKAGE_ASSERT($bits(alu_args_t) == INST_ARGS_BITS) + + typedef struct packed { + logic [(INST_ARGS_BITS-INST_FRM_BITS-INST_FMT_BITS)-1:0] __padding; + logic [INST_FRM_BITS-1:0] frm; + logic [INST_FMT_BITS-1:0] fmt; + } fpu_args_t; + `PACKAGE_ASSERT($bits(fpu_args_t) == INST_ARGS_BITS) + + typedef struct packed { + logic [(INST_ARGS_BITS-1-1-OFFSET_BITS)-1:0] __padding; + logic is_store; + logic is_float; + logic [OFFSET_BITS-1:0] offset; + } lsu_args_t; + `PACKAGE_ASSERT($bits(lsu_args_t) == INST_ARGS_BITS) + + typedef struct packed { + logic [(INST_ARGS_BITS-1-`VX_CSR_ADDR_BITS-5)-1:0] __padding; + logic use_imm; + logic [`VX_CSR_ADDR_BITS-1:0] addr; + logic [4:0] imm; + } csr_args_t; + `PACKAGE_ASSERT($bits(csr_args_t) == INST_ARGS_BITS) + + typedef struct packed { + logic [(INST_ARGS_BITS-1)-1:0] __padding; + logic is_neg; + } wctl_args_t; + `PACKAGE_ASSERT($bits(wctl_args_t) == INST_ARGS_BITS) + +`ifdef EXT_TCU_ENABLE + typedef struct packed { + logic [(INST_ARGS_BITS-16)-1:0] __padding; + logic [3:0] fmt_d; + logic [3:0] fmt_s; + logic [3:0] step_n; + logic [3:0] step_m; + } tcu_args_t; + `PACKAGE_ASSERT($bits(tcu_args_t) == INST_ARGS_BITS) +`endif + + typedef union packed { + alu_args_t alu; + fpu_args_t fpu; + lsu_args_t lsu; + csr_args_t csr; + wctl_args_t wctl; + `ifdef EXT_TCU_ENABLE + tcu_args_t tcu; + `endif + } op_args_t; + `PACKAGE_ASSERT($bits(op_args_t) == INST_ARGS_BITS) + + //////////////////////////// Pipeline Data Types ////////////////////////// + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [NW_WIDTH-1:0] wid; + logic [`NUM_THREADS-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [31:0] instr; + } fetch_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [NW_WIDTH-1:0] wid; + logic [`NUM_THREADS-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [EX_BITS-1:0] ex_type; + logic [INST_OP_BITS-1:0] op_type; + op_args_t op_args; + logic wb; + logic [NUM_SRC_OPDS-1:0] used_rs; + logic [NUM_REGS_BITS-1:0] rd; + logic [NUM_REGS_BITS-1:0] rs1; + logic [NUM_REGS_BITS-1:0] rs2; + logic [NUM_REGS_BITS-1:0] rs3; + } decode_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [`NUM_THREADS-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [EX_BITS-1:0] ex_type; + logic [INST_OP_BITS-1:0] op_type; + op_args_t op_args; + logic wb; + logic [NUM_SRC_OPDS-1:0] used_rs; + logic [NUM_REGS_BITS-1:0] rd; + logic [NUM_REGS_BITS-1:0] rs1; + logic [NUM_REGS_BITS-1:0] rs2; + logic [NUM_REGS_BITS-1:0] rs3; + } ibuffer_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [`NUM_THREADS-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [EX_BITS-1:0] ex_type; + logic [INST_OP_BITS-1:0] op_type; + op_args_t op_args; + logic wb; + logic [NUM_SRC_OPDS-1:0] used_rs; + logic [NUM_REGS_BITS-1:0] rd; + logic [NUM_REGS_BITS-1:0] rs1; + logic [NUM_REGS_BITS-1:0] rs2; + logic [NUM_REGS_BITS-1:0] rs3; + } scoreboard_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [SIMD_IDX_W-1:0] sid; + logic [`SIMD_WIDTH-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [EX_BITS-1:0] ex_type; + logic [INST_OP_BITS-1:0] op_type; + op_args_t op_args; + logic wb; + logic [NUM_REGS_BITS-1:0] rd; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] rs1_data; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] rs2_data; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] rs3_data; + logic sop; + logic eop; + } operands_t; + + // warning: this layout should not be modified without updating VX_dispatch_unit!!! + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [SIMD_IDX_W-1:0] sid; + logic [`SIMD_WIDTH-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [INST_ALU_BITS-1:0] op_type; + op_args_t op_args; + logic wb; + logic [NUM_REGS_BITS-1:0] rd; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] rs1_data; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] rs2_data; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] rs3_data; + logic sop; + logic eop; + } dispatch_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [NW_WIDTH-1:0] wid; + logic [SIMD_IDX_W-1:0] sid; + logic [`SIMD_WIDTH-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic wb; + logic [NUM_REGS_BITS-1:0] rd; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] data; + logic sop; + logic eop; + } commit_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [ISSUE_WIS_W-1:0] wis; + logic [SIMD_IDX_W-1:0] sid; + logic [`SIMD_WIDTH-1:0] tmask; + logic [PC_BITS-1:0] PC; + logic [NUM_REGS_BITS-1:0] rd; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] data; + logic sop; + logic eop; + } writeback_t; + + typedef struct packed { + logic [UUID_WIDTH-1:0] uuid; + logic [NW_WIDTH-1:0] wid; + logic [`NUM_THREADS-1:0] tmask; + logic [PC_BITS-1:0] PC; + } schedule_t; + + `DECL_EXECUTE_T (alu_exe_t, `NUM_ALU_LANES); + `DECL_RESULT_T (alu_res_t, `NUM_ALU_LANES); + + `DECL_EXECUTE_T (lsu_exe_t, `NUM_LSU_LANES); + `DECL_RESULT_T (lsu_res_t, `NUM_LSU_LANES); + + `DECL_EXECUTE_T (sfu_exe_t, `NUM_SFU_LANES); + `DECL_RESULT_T (sfu_res_t, `NUM_SFU_LANES); + + //////////////////////////// Perf counter types /////////////////////////// + + typedef struct packed { + logic [PERF_CTR_BITS-1:0] reads; + logic [PERF_CTR_BITS-1:0] writes; + logic [PERF_CTR_BITS-1:0] read_misses; + logic [PERF_CTR_BITS-1:0] write_misses; + logic [PERF_CTR_BITS-1:0] bank_stalls; + logic [PERF_CTR_BITS-1:0] mshr_stalls; + logic [PERF_CTR_BITS-1:0] mem_stalls; + logic [PERF_CTR_BITS-1:0] crsp_stalls; + } cache_perf_t; + + typedef struct packed { + logic [PERF_CTR_BITS-1:0] reads; + logic [PERF_CTR_BITS-1:0] writes; + logic [PERF_CTR_BITS-1:0] bank_stalls; + logic [PERF_CTR_BITS-1:0] crsp_stalls; + } lmem_perf_t; + + typedef struct packed { + logic [PERF_CTR_BITS-1:0] misses; + } coalescer_perf_t; + + typedef struct packed { + logic [PERF_CTR_BITS-1:0] reads; + logic [PERF_CTR_BITS-1:0] writes; + logic [PERF_CTR_BITS-1:0] latency; + } mem_perf_t; + + typedef struct packed { + logic [PERF_CTR_BITS-1:0] idles; + logic [PERF_CTR_BITS-1:0] stalls; + } sched_perf_t; + + typedef struct packed { + logic [PERF_CTR_BITS-1:0] ibf_stalls; + logic [PERF_CTR_BITS-1:0] scb_stalls; + logic [PERF_CTR_BITS-1:0] opd_stalls; + logic [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] units_uses; + logic [NUM_SFU_UNITS-1:0][PERF_CTR_BITS-1:0] sfu_uses; + } issue_perf_t; + + typedef struct packed { + cache_perf_t icache; + cache_perf_t dcache; + cache_perf_t l2cache; + cache_perf_t l3cache; + lmem_perf_t lmem; + coalescer_perf_t coalescer; + mem_perf_t mem; + } sysmem_perf_t; + + typedef struct packed { + sched_perf_t sched; + issue_perf_t issue; + logic [PERF_CTR_BITS-1:0] ifetches; + logic [PERF_CTR_BITS-1:0] loads; + logic [PERF_CTR_BITS-1:0] stores; + logic [PERF_CTR_BITS-1:0] ifetch_latency; + logic [PERF_CTR_BITS-1:0] load_latency; + } pipeline_perf_t; + + ///////////////////////// LSU memory Parameters /////////////////////////// + + localparam LSU_WORD_SIZE = XLENB; + localparam LSU_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(LSU_WORD_SIZE)); + localparam LSU_MEM_BATCHES = 1; + localparam LSU_TAG_ID_BITS = (`CLOG2(`LSUQ_IN_SIZE) + `CLOG2(LSU_MEM_BATCHES)); + localparam LSU_TAG_WIDTH = (UUID_WIDTH + LSU_TAG_ID_BITS); + localparam LSU_NUM_REQS = `NUM_LSU_BLOCKS * `NUM_LSU_LANES; + localparam LMEM_TAG_WIDTH = LSU_TAG_WIDTH + `CLOG2(`NUM_LSU_BLOCKS); + + ////////////////////////// Icache Parameters ////////////////////////////// + + // Word size in bytes + localparam ICACHE_WORD_SIZE = 4; + localparam ICACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(ICACHE_WORD_SIZE)); + + // Block size in bytes + localparam ICACHE_LINE_SIZE = `L1_LINE_SIZE; + + // Core request tag Id bits + localparam ICACHE_TAG_ID_BITS = NW_WIDTH; + + // Core request tag bits + localparam ICACHE_TAG_WIDTH = (UUID_WIDTH + ICACHE_TAG_ID_BITS); + + // Memory request data bits + localparam ICACHE_MEM_DATA_WIDTH = (ICACHE_LINE_SIZE * 8); + + // Memory request tag bits +`ifdef ICACHE_ENABLE + localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_MEM_TAG_WIDTH(`ICACHE_MSHR_SIZE, 1, 1, `NUM_ICACHES, UUID_WIDTH); +`else + localparam ICACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_MEM_TAG_WIDTH(1, 1, ICACHE_LINE_SIZE, ICACHE_WORD_SIZE, ICACHE_TAG_WIDTH, `SOCKET_SIZE, `NUM_ICACHES); +`endif + + ////////////////////////// Dcache Parameters ////////////////////////////// + + // Word size in bytes + localparam DCACHE_WORD_SIZE = `LSU_LINE_SIZE; + localparam DCACHE_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(DCACHE_WORD_SIZE)); + + // Block size in bytes + localparam DCACHE_LINE_SIZE = `L1_LINE_SIZE; + + // Input request size (using coalesced memory blocks) + localparam DCACHE_CHANNELS = `UP((`NUM_LSU_LANES * LSU_WORD_SIZE) / DCACHE_WORD_SIZE); + localparam DCACHE_NUM_REQS = `NUM_LSU_BLOCKS * DCACHE_CHANNELS; + + // Core request tag Id bits + localparam DCACHE_MERGED_REQS = (`NUM_LSU_LANES * LSU_WORD_SIZE) / DCACHE_WORD_SIZE; + localparam DCACHE_MEM_BATCHES = `CDIV(DCACHE_MERGED_REQS, DCACHE_CHANNELS); + localparam DCACHE_TAG_ID_BITS = (`CLOG2(`LSUQ_OUT_SIZE) + `CLOG2(DCACHE_MEM_BATCHES)); + + // Core request tag bits + localparam DCACHE_TAG_WIDTH = (UUID_WIDTH + DCACHE_TAG_ID_BITS); + + // Memory request data bits + localparam DCACHE_MEM_DATA_WIDTH = (DCACHE_LINE_SIZE * 8); + + // Memory request tag bits +`ifdef DCACHE_ENABLE + localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_NC_MEM_TAG_WIDTH(`DCACHE_MSHR_SIZE, `DCACHE_NUM_BANKS, DCACHE_NUM_REQS, `L1_MEM_PORTS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_TAG_WIDTH, `SOCKET_SIZE, `NUM_DCACHES, UUID_WIDTH); +`else + localparam DCACHE_MEM_TAG_WIDTH = `CACHE_CLUSTER_BYPASS_MEM_TAG_WIDTH(DCACHE_NUM_REQS, `L1_MEM_PORTS, DCACHE_LINE_SIZE, DCACHE_WORD_SIZE, DCACHE_TAG_WIDTH, `SOCKET_SIZE, `NUM_DCACHES); +`endif + + /////////////////////////////// L1 Parameters ///////////////////////////// + + // arbitrate between icache and dcache + localparam L1_MEM_TAG_WIDTH = `MAX(ICACHE_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH); + localparam L1_MEM_ARB_TAG_WIDTH = (L1_MEM_TAG_WIDTH + `CLOG2(2)); + + /////////////////////////////// L2 Parameters ///////////////////////////// + + localparam ICACHE_MEM_ARB_IDX = 0; + localparam DCACHE_MEM_ARB_IDX = ICACHE_MEM_ARB_IDX + 1; + + // Word size in bytes + localparam L2_WORD_SIZE = `L1_LINE_SIZE; + + // Input request size + localparam L2_NUM_REQS = NUM_SOCKETS * `L1_MEM_PORTS; + + // Core request tag bits + localparam L2_TAG_WIDTH = L1_MEM_ARB_TAG_WIDTH; + + // Memory request data bits + localparam L2_MEM_DATA_WIDTH = (`L2_LINE_SIZE * 8); + + // Memory request tag bits +`ifdef L2_ENABLE + localparam L2_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L2_MSHR_SIZE, `L2_NUM_BANKS, L2_NUM_REQS, `L2_MEM_PORTS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH, UUID_WIDTH); +`else + localparam L2_MEM_TAG_WIDTH = `CACHE_BYPASS_TAG_WIDTH(L2_NUM_REQS, `L2_MEM_PORTS, `L2_LINE_SIZE, L2_WORD_SIZE, L2_TAG_WIDTH); +`endif + + /////////////////////////////// L3 Parameters ///////////////////////////// + + // Word size in bytes + localparam L3_WORD_SIZE = `L2_LINE_SIZE; + + // Input request size + localparam L3_NUM_REQS = `NUM_CLUSTERS * `L2_MEM_PORTS; + + // Core request tag bits + localparam L3_TAG_WIDTH = L2_MEM_TAG_WIDTH; + + // Memory request data bits + localparam L3_MEM_DATA_WIDTH = (`L3_LINE_SIZE * 8); + + // Memory request tag bits +`ifdef L3_ENABLE + localparam L3_MEM_TAG_WIDTH = `CACHE_NC_MEM_TAG_WIDTH(`L3_MSHR_SIZE, `L3_NUM_BANKS, L3_NUM_REQS, `L3_MEM_PORTS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH, UUID_WIDTH); +`else + localparam L3_MEM_TAG_WIDTH = `CACHE_BYPASS_TAG_WIDTH(L3_NUM_REQS, `L3_MEM_PORTS, `L3_LINE_SIZE, L3_WORD_SIZE, L3_TAG_WIDTH); +`endif + + /////////////////////////////////////////////////////////////////////////// + + localparam VX_MEM_PORTS = `L3_MEM_PORTS; + localparam VX_MEM_BYTEEN_WIDTH = `L3_LINE_SIZE; + localparam VX_MEM_ADDR_WIDTH = (`MEM_ADDR_WIDTH - `CLOG2(`L3_LINE_SIZE)); + localparam VX_MEM_DATA_WIDTH = (`L3_LINE_SIZE * 8); + localparam VX_MEM_TAG_WIDTH = L3_MEM_TAG_WIDTH; + + ///////////////////////// Miscaellaneous functions //////////////////////// + + function automatic logic [SFU_WIDTH-1:0] op_to_sfu_type( + input logic [INST_OP_BITS-1:0] op_type + ); + case (op_type) + INST_SFU_CSRRW, + INST_SFU_CSRRS, + INST_SFU_CSRRC: op_to_sfu_type = SFU_CSRS; + default: op_to_sfu_type = SFU_WCTL; + endcase + endfunction + + function automatic logic [NUM_REGS_BITS-1:0] make_reg_num(input logic [REG_TYPE_BITS-1:0] rtype, logic [RV_REGS_BITS-1:0] idx); + return (NUM_REGS_BITS'(rtype) << RV_REGS_BITS) | NUM_REGS_BITS'(idx); + endfunction + + function automatic logic [REG_TYPE_BITS-1:0] get_reg_type(input logic [NUM_REGS_BITS-1:0] reg_num); + return REG_TYPE_BITS'(reg_num >> RV_REGS_BITS); + endfunction + + function automatic logic [RV_REGS_BITS-1:0] get_reg_idx(input logic [NUM_REGS_BITS-1:0] reg_num); + return reg_num[RV_REGS_BITS-1:0]; + endfunction + +endpackage + +`IGNORE_UNUSED_END + +`endif // VX_GPU_PKG_VH diff --git a/designs/src/vortex/rtl/VX_platform.vh b/designs/src/vortex/rtl/VX_platform.vh new file mode 100644 index 0000000..f8e7017 --- /dev/null +++ b/designs/src/vortex/rtl/VX_platform.vh @@ -0,0 +1,327 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_PLATFORM_VH +`define VX_PLATFORM_VH + +`ifdef SV_DPI +`include "util_dpi.vh" +`endif + +`include "VX_scope.vh" + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef SIMULATION + +`define STATIC_ASSERT(cond, msg) \ + /* verilator lint_off GENUNNAMED */ \ + initial if (!(cond)) begin \ + $error msg; \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define PACKAGE_ASSERT(cond) \ + /* verilator lint_on UNUSED */ \ + typedef bit [((cond) ? 0 : -1) : 0] static_assertion_at_line_`__LINE__; \ + /* verilator lint_off UNUSED */ + +`define ERROR(msg) \ + $error msg + +`define ASSERT(cond, msg) \ + assert(cond) else $error msg + +`define RUNTIME_ASSERT(cond, msg) \ + always @(posedge clk) begin \ + if (!reset) begin \ + `ASSERT(cond, msg); \ + end \ + end + +`ifndef TRACING_ALL +`define TRACING_ON /* verilator tracing_on */ +`define TRACING_OFF /* verilator tracing_off */ +`else +`define TRACING_ON +`define TRACING_OFF +`endif + +`ifndef NDEBUG + `define DEBUG_BLOCK(x) /* verilator lint_off UNUSED */ \ + x \ + /* verilator lint_on UNUSED */ +`else + `define DEBUG_BLOCK(x) +`endif + +`define IGNORE_UNOPTFLAT_BEGIN /* verilator lint_off UNOPTFLAT */ + +`define IGNORE_UNOPTFLAT_END /* verilator lint_off UNOPTFLAT */ + +`define IGNORE_UNUSED_BEGIN /* verilator lint_off UNUSED */ + +`define IGNORE_UNUSED_END /* verilator lint_on UNUSED */ + +`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \ + /* verilator lint_off PINCONNECTEMPTY */ \ + /* verilator lint_off WIDTH */ \ + /* verilator lint_off UNOPTFLAT */ \ + /* verilator lint_off UNDRIVEN */ \ + /* verilator lint_off DECLFILENAME */ \ + /* verilator lint_off IMPLICIT */ \ + /* verilator lint_off PINMISSING */ \ + /* verilator lint_off IMPORTSTAR */ \ + /* verilator lint_off UNSIGNED */ \ + /* verilator lint_off CMPCONST */ \ + /* verilator lint_off SYMRSVDWORD */ + +`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \ + /* verilator lint_on PINCONNECTEMPTY */ \ + /* verilator lint_on WIDTH */ \ + /* verilator lint_on UNOPTFLAT */ \ + /* verilator lint_on UNDRIVEN */ \ + /* verilator lint_on DECLFILENAME */ \ + /* verilator lint_on IMPLICIT */ \ + /* verilator lint_off PINMISSING */ \ + /* verilator lint_on IMPORTSTAR */ \ + /* verilator lint_on UNSIGNED */ \ + /* verilator lint_on CMPCONST */ \ + /* verilator lint_on SYMRSVDWORD */ + +`define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \ + localparam __``x = x; \ + /* verilator lint_on UNUSED */ + +`define UNUSED_SPARAM(x) /* verilator lint_off UNUSED */ \ + localparam `STRING __``x = x; \ + /* verilator lint_on UNUSED */ + +`define UNUSED_VAR(x) /* verilator lint_off GENUNNAMED */ \ + if (1) begin \ + /* verilator lint_off UNUSED */ \ + wire [$bits(x)-1:0] __unused = x; \ + /* verilator lint_on UNUSED */ \ + end \ + /* verilator lint_on GENUNNAMED */ + +`define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ + . x () \ + /* verilator lint_on PINCONNECTEMPTY */ + +`define UNUSED_ARG(x) /* verilator lint_off UNUSED */ \ + x \ + /* verilator lint_on UNUSED */ + +`ifdef SV_DPI +`define TRACE(level, args) \ + dpi_trace(level, $sformatf args); +`else +`define TRACE(level, args) \ + if (level <= `DEBUG_LEVEL) begin \ + $write args; \ + end +`endif + +`define SFORMATF(x) $sformatf x + +`else // SYNTHESIS + +`define STATIC_ASSERT(cond, msg) +`define PACKAGE_ASSERT(cond) +`define ERROR(msg) // +`define ASSERT(cond, msg) // +`define RUNTIME_ASSERT(cond, msg) + +`define DEBUG_BLOCK(x) +`define TRACE(level, args) \ + if (level <= `DEBUG_LEVEL) begin \ + end +`define SFORMATF(x) "" + +`define TRACING_ON +`define TRACING_OFF + +`define IGNORE_UNOPTFLAT_BEGIN +`define IGNORE_UNOPTFLAT_END +`define IGNORE_UNUSED_BEGIN +`define IGNORE_UNUSED_END +`define IGNORE_WARNINGS_BEGIN +`define IGNORE_WARNINGS_END +`define UNUSED_PARAM(x) +`define UNUSED_SPARAM(x) +`define UNUSED_VAR(x) +`define UNUSED_PIN(x) . x () +`define UNUSED_ARG(x) x + +`endif + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef QUARTUS +`define MAX_FANOUT 8 +`define LATENCY_IMUL 3 +`define FORCE_BRAM(d,w) (((d) >= 64 || (w) >= 16 || ((d) * (w)) >= 512) && ((d) * (w)) >= 64) +`define USE_BLOCK_BRAM (* ramstyle = "block" *) +`define USE_FAST_BRAM (* ramstyle = "MLAB, no_rw_check" *) +`define NO_RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams off" *) +`define RW_RAM_CHECK (* altera_attribute = "-name add_pass_through_logic_to_inferred_rams on" *) +`define DISABLE_BRAM (* ramstyle = "logic" *) +`define PRESERVE_NET (* preserve *) +`define BLACKBOX_CELL (* black_box *) +`define STRING string +`elsif VIVADO +`define MAX_FANOUT 8 +`define LATENCY_IMUL 3 +`define FORCE_BRAM(d,w) (((d) >= 64 || (w) >= 16 || ((d) * (w)) >= 512) && ((d) * (w)) >= 64) +`define USE_BLOCK_BRAM (* ram_style = "block" *) +`define USE_FAST_BRAM (* ram_style = "distributed" *) +`define NO_RW_RAM_CHECK (* rw_addr_collision = "no" *) +`define RW_RAM_CHECK (* rw_addr_collision = "yes" *) +`define DISABLE_BRAM (* ram_style = "registers" *) +`define PRESERVE_NET (* keep = "true" *) +`define BLACKBOX_CELL (* black_box *) +`define STRING +`ifndef SIMULATION + `define ASYNC_BRAM_PATCH +`endif +`else +`define MAX_FANOUT 8 +`define LATENCY_IMUL 3 +`define FORCE_BRAM(d,w) (((d) >= 64 || (w) >= 16 || ((d) * (w)) >= 512) && ((d) * (w)) >= 64) +`define USE_BLOCK_BRAM +`define USE_FAST_BRAM +`define NO_RW_RAM_CHECK +`define RW_RAM_CHECK +`define DISABLE_BRAM +`define PRESERVE_NET +`define BLACKBOX_CELL +`define STRING string +`endif + +/////////////////////////////////////////////////////////////////////////////// + +`define STRINGIFY(x) `"x`" + +`define CLOG2(x) $clog2(x) +`define FLOG2(x) ($clog2(x) - (((1 << $clog2(x)) > (x)) ? 1 : 0)) +`define LOG2UP(x) (((x) > 1) ? $clog2(x) : 1) +`define IS_POW2(x) (((x) != 0) && (0 == ((x) & ((x) - 1)))) +`define IS_DIVISBLE(n, d) (((n) % (d)) == 0) + +`define ABS(x) (((x) < 0) ? (-(x)) : (x)); + +`ifndef MIN +`define MIN(x, y) (((x) < (y)) ? (x) : (y)) +`endif + +`ifndef MAX +`define MAX(x, y) (((x) > (y)) ? (x) : (y)) +`endif + +`define CLAMP(x, lo, hi) (((x) > (hi)) ? (hi) : (((x) < (lo)) ? (lo) : (x))) + +`define UP(x) (((x) > 0) ? (x) : 1) + +`define CDIV(n,d) ((n + d - 1) / (d)) + + +`define RTRIM(x, s) x[$bits(x)-1:($bits(x)-s)] + +`define LTRIM(x, s) x[s-1:0] + +`define SEXT(len, x) {{(len-$bits(x)+1){x[$bits(x)-1]}}, x[$bits(x)-2:0]} + +`define TRACE_ARRAY1D(lvl, fmt, arr, n) \ + `TRACE(lvl, ("{")) \ + for (integer __i = (n-1); __i >= 0; --__i) begin \ + if (__i != (n-1)) `TRACE(lvl, (", ")) \ + `TRACE(lvl, (fmt, arr[__i])) \ + end \ + `TRACE(lvl, ("}")) + +`define TRACE_ARRAY2D(lvl, fmt, arr, m, n) \ + `TRACE(lvl, ("{")) \ + for (integer __i = n-1; __i >= 0; --__i) begin \ + if (__i != (n-1)) `TRACE(lvl, (", ")) \ + `TRACE(lvl, ("{")) \ + for (integer __j = (m-1); __j >= 0; --__j) begin \ + if (__j != (m-1)) `TRACE(lvl, (", "))\ + `TRACE(lvl, (fmt, arr[__i][__j])) \ + end \ + `TRACE(lvl, ("}")) \ + end \ + `TRACE(lvl, ("}")) + +`define RESET_RELAY_EX(dst, src, size, fanout) \ + wire [size-1:0] dst; \ + VX_reset_relay #(.N(size), .MAX_FANOUT(fanout)) __``dst ( \ + .clk (clk), \ + .reset (src), \ + .reset_o (dst) \ + ) + +`define RESET_RELAY_EN(dst, src, enable) \ + `RESET_RELAY_EX (dst, src, 1, ((enable) ? 0 : -1)) + +`define RESET_RELAY(dst, src) \ + `RESET_RELAY_EX (dst, src, 1, 0) + +// size(x): 0 -> 0, 1 -> 1, 2 -> 2, 3 -> 2, 4-> 2, 5 -> 2 +`define TO_OUT_BUF_SIZE(s) `MIN(s & 7, 2) + +// reg(x): 0 -> 0, 1 -> 1, 2 -> 0, 3 -> 1, 4 -> 2, 5 > 3 +`define TO_OUT_BUF_REG(s) (((s & 7) < 2) ? (s & 7) : ((s & 7) - 2)) + +// lut(x): (x & 8) != 0 +`define TO_OUT_BUF_LUTRAM(s) ((s & 8) != 0) + +`define REPEAT(n,f,s) `_REPEAT_``n(f,s) +`define _REPEAT_0(f,s) +`define _REPEAT_1(f,s) `f(0) +`define _REPEAT_2(f,s) `f(1) `s `_REPEAT_1(f,s) +`define _REPEAT_3(f,s) `f(2) `s `_REPEAT_2(f,s) +`define _REPEAT_4(f,s) `f(3) `s `_REPEAT_3(f,s) +`define _REPEAT_5(f,s) `f(4) `s `_REPEAT_4(f,s) +`define _REPEAT_6(f,s) `f(5) `s `_REPEAT_5(f,s) +`define _REPEAT_7(f,s) `f(6) `s `_REPEAT_6(f,s) +`define _REPEAT_8(f,s) `f(7) `s `_REPEAT_7(f,s) +`define _REPEAT_9(f,s) `f(8) `s `_REPEAT_8(f,s) +`define _REPEAT_10(f,s) `f(9) `s `_REPEAT_9(f,s) +`define _REPEAT_11(f,s) `f(10) `s `_REPEAT_10(f,s) +`define _REPEAT_12(f,s) `f(11) `s `_REPEAT_11(f,s) +`define _REPEAT_13(f,s) `f(12) `s `_REPEAT_12(f,s) +`define _REPEAT_14(f,s) `f(13) `s `_REPEAT_13(f,s) +`define _REPEAT_15(f,s) `f(14) `s `_REPEAT_14(f,s) +`define _REPEAT_16(f,s) `f(15) `s `_REPEAT_15(f,s) +`define _REPEAT_17(f,s) `f(16) `s `_REPEAT_16(f,s) +`define _REPEAT_18(f,s) `f(17) `s `_REPEAT_17(f,s) +`define _REPEAT_19(f,s) `f(18) `s `_REPEAT_18(f,s) +`define _REPEAT_20(f,s) `f(19) `s `_REPEAT_19(f,s) +`define _REPEAT_21(f,s) `f(20) `s `_REPEAT_20(f,s) +`define _REPEAT_22(f,s) `f(21) `s `_REPEAT_21(f,s) +`define _REPEAT_23(f,s) `f(22) `s `_REPEAT_22(f,s) +`define _REPEAT_24(f,s) `f(23) `s `_REPEAT_23(f,s) +`define _REPEAT_25(f,s) `f(24) `s `_REPEAT_24(f,s) +`define _REPEAT_26(f,s) `f(25) `s `_REPEAT_25(f,s) +`define _REPEAT_27(f,s) `f(26) `s `_REPEAT_26(f,s) +`define _REPEAT_28(f,s) `f(27) `s `_REPEAT_27(f,s) +`define _REPEAT_29(f,s) `f(28) `s `_REPEAT_28(f,s) +`define _REPEAT_30(f,s) `f(29) `s `_REPEAT_29(f,s) +`define _REPEAT_31(f,s) `f(30) `s `_REPEAT_30(f,s) +`define _REPEAT_32(f,s) `f(31) `s `_REPEAT_31(f,s) + +`define REPEAT_COMMA , +`define REPEAT_SEMICOLON ; + +`endif // VX_PLATFORM_VH diff --git a/designs/src/vortex/rtl/VX_scope.vh b/designs/src/vortex/rtl/VX_scope.vh new file mode 100644 index 0000000..b3d427e --- /dev/null +++ b/designs/src/vortex/rtl/VX_scope.vh @@ -0,0 +1,87 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_SCOPE_VH +`define VX_SCOPE_VH + +`ifdef SCOPE + +`define SCOPE_IO_DECL \ + input wire scope_reset, \ + input wire scope_bus_in, \ + output wire scope_bus_out, + +`define SCOPE_IO_BIND(__i) \ + .scope_reset (scope_reset_w[__i]), \ + .scope_bus_in (scope_bus_in_w[__i]), \ + .scope_bus_out (scope_bus_out_w[__i]), + +`define SCOPE_IO_UNUSED(__i) \ + `UNUSED_VAR (scope_reset_w[__i]); \ + `UNUSED_VAR (scope_bus_in_w[__i]); \ + assign scope_bus_out_w[__i] = 0; + +`define SCOPE_IO_SWITCH(__count) \ + wire [__count-1:0] scope_bus_in_w; \ + wire [__count-1:0] scope_bus_out_w; \ + wire [__count-1:0] scope_reset_w = {__count{scope_reset}}; \ + VX_scope_switch #( \ + .N (__count) \ + ) scope_switch ( \ + .clk (clk), \ + .reset (scope_reset), \ + .req_in (scope_bus_in), \ + .rsp_out (scope_bus_out), \ + .req_out (scope_bus_in_w), \ + .rsp_in (scope_bus_out_w) \ + ) + +`define SCOPE_TAP_EX(__idx, __id, __xtriggers_w, __htriggers_w, __probes_w, __xtriggers, __htriggers, __probes, __start, __stop, __depth) \ + VX_scope_tap #( \ + .SCOPE_ID (__id), \ + .XTRIGGERW(__xtriggers_w), \ + .HTRIGGERW(__htriggers_w), \ + .PROBEW (__probes_w), \ + .DEPTH (__depth) \ + ) scope_tap_``idx ( \ + .clk (clk), \ + .reset (scope_reset_w[__idx]), \ + .start (__start), \ + .stop (__stop), \ + .xtriggers(__xtriggers), \ + .htriggers(__htriggers), \ + .probes (__probes), \ + .bus_in (scope_bus_in_w[__idx]), \ + .bus_out(scope_bus_out_w[__idx]) \ + ) + +`define SCOPE_TAP(__idx, __id, __xtriggers, __htriggers, __probes, __start, __stop, __depth) \ + `SCOPE_TAP_EX(__idx, __id, $bits(__xtriggers), $bits(__htriggers), $bits(__probes), __xtriggers, __htriggers, __probes, __start, __stop, __depth) + +`else + +`define SCOPE_IO_DECL + +`define SCOPE_IO_BIND(__i) + +`define SCOPE_IO_UNUSED(__i) + +`define SCOPE_IO_SWITCH(__count) + +`define SCOPE_TAP(__idx, __id, __xtriggers, __probes, __depth) + +`define SCOPE_TAP_EX(__idx, __id, __xtriggers_w, __probes_w, __xtriggers, __probes, __depth) + +`endif + +`endif // VX_SCOPE_VH diff --git a/designs/src/vortex/rtl/VX_socket.sv b/designs/src/vortex/rtl/VX_socket.sv new file mode 100644 index 0000000..54bdca3 --- /dev/null +++ b/designs/src/vortex/rtl/VX_socket.sv @@ -0,0 +1,255 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_socket import VX_gpu_pkg::*; #( + parameter SOCKET_ID = 0, + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, +`endif + + // DCRs + VX_dcr_bus_if.slave dcr_bus_if, + + // Memory + VX_mem_bus_if.master mem_bus_if [`L1_MEM_PORTS], + +`ifdef GBAR_ENABLE + // Barrier + VX_gbar_bus_if.master gbar_bus_if, +`endif + // Status + output wire busy +); + +`ifdef SCOPE + localparam scope_core = 0; + `SCOPE_IO_SWITCH (`SOCKET_SIZE); +`endif + +`ifdef GBAR_ENABLE + VX_gbar_bus_if per_core_gbar_bus_if[`SOCKET_SIZE](); + + VX_gbar_arb #( + .NUM_REQS (`SOCKET_SIZE), + .OUT_BUF ((`SOCKET_SIZE > 1) ? 2 : 0) + ) gbar_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (per_core_gbar_bus_if), + .bus_out_if (gbar_bus_if) + ); +`endif + + /////////////////////////////////////////////////////////////////////////// + +`ifdef PERF_ENABLE + cache_perf_t icache_perf, dcache_perf; + sysmem_perf_t sysmem_perf_tmp; + always @(*) begin + sysmem_perf_tmp = sysmem_perf; + sysmem_perf_tmp.icache = icache_perf; + sysmem_perf_tmp.dcache = dcache_perf; + end +`endif + + /////////////////////////////////////////////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_TAG_WIDTH) + ) per_core_icache_bus_if[`SOCKET_SIZE](); + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_LINE_SIZE), + .TAG_WIDTH (ICACHE_MEM_TAG_WIDTH) + ) icache_mem_bus_if[1](); + + `RESET_RELAY (icache_reset, reset); + + VX_cache_cluster #( + .INSTANCE_ID (`SFORMATF(("%s-icache", INSTANCE_ID))), + .NUM_UNITS (`NUM_ICACHES), + .NUM_INPUTS (`SOCKET_SIZE), + .TAG_SEL_IDX (0), + .CACHE_SIZE (`ICACHE_SIZE), + .LINE_SIZE (ICACHE_LINE_SIZE), + .NUM_BANKS (1), + .NUM_WAYS (`ICACHE_NUM_WAYS), + .WORD_SIZE (ICACHE_WORD_SIZE), + .NUM_REQS (1), + .MEM_PORTS (1), + .CRSQ_SIZE (`ICACHE_CRSQ_SIZE), + .MSHR_SIZE (`ICACHE_MSHR_SIZE), + .MRSQ_SIZE (`ICACHE_MRSQ_SIZE), + .MREQ_SIZE (`ICACHE_MREQ_SIZE), + .TAG_WIDTH (ICACHE_TAG_WIDTH), + .WRITE_ENABLE (0), + .REPL_POLICY (`ICACHE_REPL_POLICY), + .NC_ENABLE (0), + .CORE_OUT_BUF (3), + .MEM_OUT_BUF (2) + ) icache ( + `ifdef PERF_ENABLE + .cache_perf (icache_perf), + `endif + .clk (clk), + .reset (icache_reset), + .core_bus_if (per_core_icache_bus_if), + .mem_bus_if (icache_mem_bus_if) + ); + + /////////////////////////////////////////////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH) + ) per_core_dcache_bus_if[`SOCKET_SIZE * DCACHE_NUM_REQS](); + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_LINE_SIZE), + .TAG_WIDTH (DCACHE_MEM_TAG_WIDTH) + ) dcache_mem_bus_if[`L1_MEM_PORTS](); + + `RESET_RELAY (dcache_reset, reset); + + VX_cache_cluster #( + .INSTANCE_ID (`SFORMATF(("%s-dcache", INSTANCE_ID))), + .NUM_UNITS (`NUM_DCACHES), + .NUM_INPUTS (`SOCKET_SIZE), + .TAG_SEL_IDX (0), + .CACHE_SIZE (`DCACHE_SIZE), + .LINE_SIZE (DCACHE_LINE_SIZE), + .NUM_BANKS (`DCACHE_NUM_BANKS), + .NUM_WAYS (`DCACHE_NUM_WAYS), + .WORD_SIZE (DCACHE_WORD_SIZE), + .NUM_REQS (DCACHE_NUM_REQS), + .MEM_PORTS (`L1_MEM_PORTS), + .CRSQ_SIZE (`DCACHE_CRSQ_SIZE), + .MSHR_SIZE (`DCACHE_MSHR_SIZE), + .MRSQ_SIZE (`DCACHE_MRSQ_SIZE), + .MREQ_SIZE (`DCACHE_WRITEBACK ? `DCACHE_MSHR_SIZE : `DCACHE_MREQ_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH), + .WRITE_ENABLE (1), + .WRITEBACK (`DCACHE_WRITEBACK), + .DIRTY_BYTES (`DCACHE_DIRTYBYTES), + .REPL_POLICY (`DCACHE_REPL_POLICY), + .NC_ENABLE (1), + .CORE_OUT_BUF (3), + .MEM_OUT_BUF (2) + ) dcache ( + `ifdef PERF_ENABLE + .cache_perf (dcache_perf), + `endif + .clk (clk), + .reset (dcache_reset), + .core_bus_if (per_core_dcache_bus_if), + .mem_bus_if (dcache_mem_bus_if) + ); + + /////////////////////////////////////////////////////////////////////////// + + for (genvar i = 0; i < `L1_MEM_PORTS; ++i) begin : g_mem_bus_if + if (i == 0) begin : g_i0 + VX_mem_bus_if #( + .DATA_SIZE (`L1_LINE_SIZE), + .TAG_WIDTH (L1_MEM_TAG_WIDTH) + ) l1_mem_bus_if[2](); + + VX_mem_bus_if #( + .DATA_SIZE (`L1_LINE_SIZE), + .TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH) + ) l1_mem_arb_bus_if[1](); + + `ASSIGN_VX_MEM_BUS_IF_EX (l1_mem_bus_if[0], icache_mem_bus_if[0], L1_MEM_TAG_WIDTH, ICACHE_MEM_TAG_WIDTH, UUID_WIDTH); + `ASSIGN_VX_MEM_BUS_IF_EX (l1_mem_bus_if[1], dcache_mem_bus_if[0], L1_MEM_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH, UUID_WIDTH); + + VX_mem_arb #( + .NUM_INPUTS (2), + .NUM_OUTPUTS(1), + .DATA_SIZE (`L1_LINE_SIZE), + .TAG_WIDTH (L1_MEM_TAG_WIDTH), + .TAG_SEL_IDX(0), + .ARBITER ("P"), // prioritize the icache + .REQ_OUT_BUF(3), + .RSP_OUT_BUF(3) + ) mem_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (l1_mem_bus_if), + .bus_out_if (l1_mem_arb_bus_if) + ); + + `ASSIGN_VX_MEM_BUS_IF (mem_bus_if[0], l1_mem_arb_bus_if[0]); + end else begin : g_i + VX_mem_bus_if #( + .DATA_SIZE (`L1_LINE_SIZE), + .TAG_WIDTH (L1_MEM_ARB_TAG_WIDTH) + ) l1_mem_arb_bus_if(); + + `ASSIGN_VX_MEM_BUS_IF_EX (l1_mem_arb_bus_if, dcache_mem_bus_if[i], L1_MEM_ARB_TAG_WIDTH, DCACHE_MEM_TAG_WIDTH, UUID_WIDTH); + `ASSIGN_VX_MEM_BUS_IF (mem_bus_if[i], l1_mem_arb_bus_if); + end + end + + /////////////////////////////////////////////////////////////////////////// + + wire [`SOCKET_SIZE-1:0] per_core_busy; + + // Generate all cores + for (genvar core_id = 0; core_id < `SOCKET_SIZE; ++core_id) begin : g_cores + + `RESET_RELAY (core_reset, reset); + + VX_dcr_bus_if core_dcr_bus_if(); + `BUFFER_DCR_BUS_IF (core_dcr_bus_if, dcr_bus_if, 1'b1, (`SOCKET_SIZE > 1)) + + VX_core #( + .CORE_ID ((SOCKET_ID * `SOCKET_SIZE) + core_id), + .INSTANCE_ID (`SFORMATF(("%s-core%0d", INSTANCE_ID, core_id))) + ) core ( + `SCOPE_IO_BIND (scope_core + core_id) + + .clk (clk), + .reset (core_reset), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf_tmp), + `endif + + .dcr_bus_if (core_dcr_bus_if), + + .dcache_bus_if (per_core_dcache_bus_if[core_id * DCACHE_NUM_REQS +: DCACHE_NUM_REQS]), + + .icache_bus_if (per_core_icache_bus_if[core_id]), + + `ifdef GBAR_ENABLE + .gbar_bus_if (per_core_gbar_bus_if[core_id]), + `endif + + .busy (per_core_busy[core_id]) + ); + end + + `BUFFER_EX(busy, (| per_core_busy), 1'b1, 1, (`SOCKET_SIZE > 1)); + +endmodule diff --git a/designs/src/vortex/rtl/VX_trace_pkg.sv b/designs/src/vortex/rtl/VX_trace_pkg.sv new file mode 100644 index 0000000..cfc12d6 --- /dev/null +++ b/designs/src/vortex/rtl/VX_trace_pkg.sv @@ -0,0 +1,450 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_TRACE_PKG_VH +`define VX_TRACE_PKG_VH + +`include "VX_define.vh" + +package VX_trace_pkg; + +`ifdef SIMULATION + + import VX_gpu_pkg::*; + +`ifdef SV_DPI + import "DPI-C" function void dpi_trace(input int level, input string format /*verilator sformat*/); +`endif + + task trace_reg_idx(input int level, input logic [NUM_REGS_BITS-1:0] reg_id); + `TRACE(level, ("%0d", reg_id)); + endtask + + task trace_ex_type(input int level, input [EX_BITS-1:0] ex_type); + case (ex_type) + EX_ALU: `TRACE(level, ("ALU")) + EX_LSU: `TRACE(level, ("LSU")) + EX_SFU: `TRACE(level, ("SFU")) + `ifdef EXT_F_ENABLE + EX_FPU: `TRACE(level, ("FPU")) + `endif + `ifdef EXT_TCU_ENABLE + EX_TCU: `TRACE(level, ("TCU")) + `endif + default: `TRACE(level, ("?")) + endcase + endtask + + task trace_ex_op(input int level, + input [EX_BITS-1:0] ex_type, + input [INST_OP_BITS-1:0] op_type, + input op_args_t op_args + ); + case (ex_type) + EX_ALU: begin + case (op_args.alu.xtype) + ALU_TYPE_ARITH: begin + if (op_args.alu.is_w) begin + if (op_args.alu.use_imm) begin + case (INST_ALU_BITS'(op_type)) + INST_ALU_ADD: `TRACE(level, ("ADDIW")) + INST_ALU_SLL: `TRACE(level, ("SLLIW")) + INST_ALU_SRL: `TRACE(level, ("SRLIW")) + INST_ALU_SRA: `TRACE(level, ("SRAIW")) + default: `TRACE(level, ("?")) + endcase + end else begin + case (INST_ALU_BITS'(op_type)) + INST_ALU_ADD: `TRACE(level, ("ADDW")) + INST_ALU_SUB: `TRACE(level, ("SUBW")) + INST_ALU_SLL: `TRACE(level, ("SLLW")) + INST_ALU_SRL: `TRACE(level, ("SRLW")) + INST_ALU_SRA: `TRACE(level, ("SRAW")) + default: `TRACE(level, ("?")) + endcase + end + end else begin + if (op_args.alu.use_imm) begin + case (INST_ALU_BITS'(op_type)) + INST_ALU_ADD: `TRACE(level, ("ADDI")) + INST_ALU_SLL: `TRACE(level, ("SLLI")) + INST_ALU_SRL: `TRACE(level, ("SRLI")) + INST_ALU_SRA: `TRACE(level, ("SRAI")) + INST_ALU_SLT: `TRACE(level, ("SLTI")) + INST_ALU_SLTU: `TRACE(level, ("SLTIU")) + INST_ALU_XOR: `TRACE(level, ("XORI")) + INST_ALU_OR: `TRACE(level, ("ORI")) + INST_ALU_AND: `TRACE(level, ("ANDI")) + INST_ALU_LUI: `TRACE(level, ("LUI")) + INST_ALU_AUIPC: `TRACE(level, ("AUIPC")) + default: `TRACE(level, ("?")) + endcase + end else begin + case (INST_ALU_BITS'(op_type)) + INST_ALU_ADD: `TRACE(level, ("ADD")) + INST_ALU_SUB: `TRACE(level, ("SUB")) + INST_ALU_SLL: `TRACE(level, ("SLL")) + INST_ALU_SRL: `TRACE(level, ("SRL")) + INST_ALU_SRA: `TRACE(level, ("SRA")) + INST_ALU_SLT: `TRACE(level, ("SLT")) + INST_ALU_SLTU: `TRACE(level, ("SLTU")) + INST_ALU_XOR: `TRACE(level, ("XOR")) + INST_ALU_OR: `TRACE(level, ("OR")) + INST_ALU_AND: `TRACE(level, ("AND")) + INST_ALU_CZEQ: `TRACE(level, ("CZERO.EQZ")) + INST_ALU_CZNE: `TRACE(level, ("CZERO.NEZ")) + default: `TRACE(level, ("?")) + endcase + end + end + end + ALU_TYPE_OTHER: begin + if (op_type[2]) begin + case (INST_SHFL_BITS'(op_type)) + INST_SHFL_UP: `TRACE(level, ("SHFL.UP")) + INST_SHFL_DOWN:`TRACE(level, ("SHFL.DOWN")) + INST_SHFL_BFLY:`TRACE(level, ("SHFL.BFLY")) + INST_SHFL_IDX: `TRACE(level, ("SHFL.IDX")) + default: `TRACE(level, ("?")) + endcase + end else begin + case (INST_VOTE_BITS'(op_type)) + INST_VOTE_ALL: `TRACE(level, ("VOTE.ALL")) + INST_VOTE_ANY: `TRACE(level, ("VOTE.ANY")) + INST_VOTE_UNI: `TRACE(level, ("VOTE.UNI")) + INST_VOTE_BAL: `TRACE(level, ("VOTE.BAL")) + default: `TRACE(level, ("?")) + endcase + end + end + ALU_TYPE_BRANCH: begin + case (INST_BR_BITS'(op_type)) + INST_BR_BEQ: `TRACE(level, ("BEQ")) + INST_BR_BNE: `TRACE(level, ("BNE")) + INST_BR_BLT: `TRACE(level, ("BLT")) + INST_BR_BGE: `TRACE(level, ("BGE")) + INST_BR_BLTU: `TRACE(level, ("BLTU")) + INST_BR_BGEU: `TRACE(level, ("BGEU")) + INST_BR_JAL: `TRACE(level, ("JAL")) + INST_BR_JALR: `TRACE(level, ("JALR")) + INST_BR_ECALL: `TRACE(level, ("ECALL")) + INST_BR_EBREAK:`TRACE(level, ("EBREAK")) + INST_BR_URET: `TRACE(level, ("URET")) + INST_BR_SRET: `TRACE(level, ("SRET")) + INST_BR_MRET: `TRACE(level, ("MRET")) + default: `TRACE(level, ("?")) + endcase + end + ALU_TYPE_MULDIV: begin + if (op_args.alu.is_w) begin + case (INST_M_BITS'(op_type)) + INST_M_MUL: `TRACE(level, ("MULW")) + INST_M_DIV: `TRACE(level, ("DIVW")) + INST_M_DIVU: `TRACE(level, ("DIVUW")) + INST_M_REM: `TRACE(level, ("REMW")) + INST_M_REMU: `TRACE(level, ("REMUW")) + default: `TRACE(level, ("?")) + endcase + end else begin + case (INST_M_BITS'(op_type)) + INST_M_MUL: `TRACE(level, ("MUL")) + INST_M_MULH: `TRACE(level, ("MULH")) + INST_M_MULHSU:`TRACE(level, ("MULHSU")) + INST_M_MULHU: `TRACE(level, ("MULHU")) + INST_M_DIV: `TRACE(level, ("DIV")) + INST_M_DIVU: `TRACE(level, ("DIVU")) + INST_M_REM: `TRACE(level, ("REM")) + INST_M_REMU: `TRACE(level, ("REMU")) + default: `TRACE(level, ("?")) + endcase + end + end + default: `TRACE(level, ("?")) + endcase + end + EX_LSU: begin + if (op_args.lsu.is_float) begin + case (INST_LSU_BITS'(op_type)) + INST_LSU_LW: `TRACE(level, ("FLW")) + INST_LSU_LD: `TRACE(level, ("FLD")) + INST_LSU_SW: `TRACE(level, ("FSW")) + INST_LSU_SD: `TRACE(level, ("FSD")) + default: `TRACE(level, ("?")) + endcase + end else begin + case (INST_LSU_BITS'(op_type)) + INST_LSU_LB: `TRACE(level, ("LB")) + INST_LSU_LH: `TRACE(level, ("LH")) + INST_LSU_LW: `TRACE(level, ("LW")) + INST_LSU_LD: `TRACE(level, ("LD")) + INST_LSU_LBU:`TRACE(level, ("LBU")) + INST_LSU_LHU:`TRACE(level, ("LHU")) + INST_LSU_LWU:`TRACE(level, ("LWU")) + INST_LSU_SB: `TRACE(level, ("SB")) + INST_LSU_SH: `TRACE(level, ("SH")) + INST_LSU_SW: `TRACE(level, ("SW")) + INST_LSU_SD: `TRACE(level, ("SD")) + INST_LSU_FENCE:`TRACE(level,("FENCE")) + default: `TRACE(level, ("?")) + endcase + end + end + EX_SFU: begin + case (INST_SFU_BITS'(op_type)) + INST_SFU_TMC: `TRACE(level, ("TMC")) + INST_SFU_WSPAWN:`TRACE(level, ("WSPAWN")) + INST_SFU_SPLIT: begin + if (op_args.wctl.is_neg) begin + `TRACE(level, ("SPLIT.N")) + end else begin + `TRACE(level, ("SPLIT")) + end + end + INST_SFU_JOIN: `TRACE(level, ("JOIN")) + INST_SFU_BAR: `TRACE(level, ("BAR")) + INST_SFU_PRED: begin + if (op_args.wctl.is_neg) begin + `TRACE(level, ("PRED.N")) + end else begin + `TRACE(level, ("PRED")) + end + end + INST_SFU_CSRRW: begin + if (op_args.csr.use_imm) begin + `TRACE(level, ("CSRRWI")) + end else begin + `TRACE(level, ("CSRRW")) + end + end + INST_SFU_CSRRS: begin + if (op_args.csr.use_imm) begin + `TRACE(level, ("CSRRSI")) + end else begin + `TRACE(level, ("CSRRS")) + end + end + INST_SFU_CSRRC: begin + if (op_args.csr.use_imm) begin + `TRACE(level, ("CSRRCI")) + end else begin + `TRACE(level, ("CSRRC")) + end + end + default: `TRACE(level, ("?")) + endcase + end + `ifdef EXT_F_ENABLE + EX_FPU: begin + case (INST_FPU_BITS'(op_type)) + INST_FPU_ADD: begin + if (op_args.fpu.fmt[1]) begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FSUB.D")) + end else begin + `TRACE(level, ("FSUB.S")) + end + end else begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FADD.D")) + end else begin + `TRACE(level, ("FADD.S")) + end + end + end + INST_FPU_MADD: begin + if (op_args.fpu.fmt[1]) begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FMSUB.D")) + end else begin + `TRACE(level, ("FMSUB.S")) + end + end else begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FMADD.D")) + end else begin + `TRACE(level, ("FMADD.S")) + end + end + end + INST_FPU_NMADD: begin + if (op_args.fpu.fmt[1]) begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FNMSUB.D")) + end else begin + `TRACE(level, ("FNMSUB.S")) + end + end else begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FNMADD.D")) + end else begin + `TRACE(level, ("FNMADD.S")) + end + end + end + INST_FPU_MUL: begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FMUL.D")) + end else begin + `TRACE(level, ("FMUL.S")) + end + end + INST_FPU_DIV: begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FDIV.D")) + end else begin + `TRACE(level, ("FDIV.S")) + end + end + INST_FPU_SQRT: begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FSQRT.D")) + end else begin + `TRACE(level, ("FSQRT.S")) + end + end + INST_FPU_CMP: begin + if (op_args.fpu.fmt[0]) begin + case (op_args.fpu.frm[1:0]) + 0: `TRACE(level, ("FLE.D")) + 1: `TRACE(level, ("FLT.D")) + 2: `TRACE(level, ("FEQ.D")) + default: `TRACE(level, ("?")) + endcase + end else begin + case (op_args.fpu.frm[1:0]) + 0: `TRACE(level, ("FLE.S")) + 1: `TRACE(level, ("FLT.S")) + 2: `TRACE(level, ("FEQ.S")) + default: `TRACE(level, ("?")) + endcase + end + end + INST_FPU_F2F: begin + if (op_args.fpu.fmt[0]) begin + `TRACE(level, ("FCVT.D.S")) + end else begin + `TRACE(level, ("FCVT.S.D")) + end + end + INST_FPU_F2I: begin + case (op_args.fpu.fmt) + 2'b00: `TRACE(level, ("FCVT.W.S")) + 2'b01: `TRACE(level, ("FCVT.W.D")) + 2'b10: `TRACE(level, ("FCVT.L.S")) + 2'b11: `TRACE(level, ("FCVT.L.D")) + endcase + end + INST_FPU_F2U: begin + case (op_args.fpu.fmt) + 2'b00: `TRACE(level, ("FCVT.WU.S")) + 2'b01: `TRACE(level, ("FCVT.WU.D")) + 2'b10: `TRACE(level, ("FCVT.LU.S")) + 2'b11: `TRACE(level, ("FCVT.LU.D")) + endcase + end + INST_FPU_I2F: begin + case (op_args.fpu.fmt) + 2'b00: `TRACE(level, ("FCVT.S.W")) + 2'b01: `TRACE(level, ("FCVT.D.W")) + 2'b10: `TRACE(level, ("FCVT.S.L")) + 2'b11: `TRACE(level, ("FCVT.D.L")) + endcase + end + INST_FPU_U2F: begin + case (op_args.fpu.fmt) + 2'b00: `TRACE(level, ("FCVT.S.WU")) + 2'b01: `TRACE(level, ("FCVT.D.WU")) + 2'b10: `TRACE(level, ("FCVT.S.LU")) + 2'b11: `TRACE(level, ("FCVT.D.LU")) + endcase + end + INST_FPU_MISC: begin + if (op_args.fpu.fmt[0]) begin + case (op_args.fpu.frm) + 0: `TRACE(level, ("FSGNJ.D")) + 1: `TRACE(level, ("FSGNJN.D")) + 2: `TRACE(level, ("FSGNJX.D")) + 3: `TRACE(level, ("FCLASS.D")) + 4: `TRACE(level, ("FMV.X.D")) + 5: `TRACE(level, ("FMV.D.X")) + 6: `TRACE(level, ("FMIN.D")) + 7: `TRACE(level, ("FMAX.D")) + endcase + end else begin + case (op_args.fpu.frm) + 0: `TRACE(level, ("FSGNJ.S")) + 1: `TRACE(level, ("FSGNJN.S")) + 2: `TRACE(level, ("FSGNJX.S")) + 3: `TRACE(level, ("FCLASS.S")) + 4: `TRACE(level, ("FMV.X.S")) + 5: `TRACE(level, ("FMV.S.X")) + 6: `TRACE(level, ("FMIN.S")) + 7: `TRACE(level, ("FMAX.S")) + endcase + end + end + default: `TRACE(level, ("?")) + endcase + end + `endif + `ifdef EXT_TCU_ENABLE + EX_TCU: begin + VX_tcu_pkg::trace_ex_op(level, op_type, op_args); + end + `endif + default: `TRACE(level, ("?")) + endcase + endtask + + task trace_op_args(input int level, + input [EX_BITS-1:0] ex_type, + input [INST_OP_BITS-1:0] op_type, + input op_args_t op_args + ); + case (ex_type) + EX_ALU: begin + `TRACE(level, ("use_PC=%b, use_imm=%b, imm=0x%0h", op_args.alu.use_PC, op_args.alu.use_imm, op_args.alu.imm)) + end + EX_LSU: begin + `TRACE(level, ("offset=0x%0h", op_args.lsu.offset)) + end + EX_SFU: begin + if (inst_sfu_is_csr(op_type)) begin + `TRACE(level, ("addr=0x%0h, use_imm=%b, imm=0x%0h", op_args.csr.addr, op_args.csr.use_imm, op_args.csr.imm)) + end + end + `ifdef EXT_F_ENABLE + EX_FPU: begin + `TRACE(level, ("fmt=0x%0h, frm=0x%0h", op_args.fpu.fmt, op_args.fpu.frm)) + end + `endif + default:; + endcase + endtask + + task trace_base_dcr(input int level, input [VX_DCR_ADDR_WIDTH-1:0] addr); + case (addr) + `VX_DCR_BASE_STARTUP_ADDR0: `TRACE(level, ("STARTUP_ADDR0")) + `VX_DCR_BASE_STARTUP_ADDR1: `TRACE(level, ("STARTUP_ADDR1")) + `VX_DCR_BASE_STARTUP_ARG0: `TRACE(level, ("STARTUP_ARG0")) + `VX_DCR_BASE_STARTUP_ARG1: `TRACE(level, ("STARTUP_ARG1")) + `VX_DCR_BASE_MPM_CLASS: `TRACE(level, ("MPM_CLASS")) + default: `TRACE(level, ("?")) + endcase + endtask + +`endif + +endpackage + +`endif // VX_TRACE_PKG_VH diff --git a/designs/src/vortex/rtl/VX_types.vh b/designs/src/vortex/rtl/VX_types.vh new file mode 100644 index 0000000..7ff3326 --- /dev/null +++ b/designs/src/vortex/rtl/VX_types.vh @@ -0,0 +1,218 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_TYPES_VH +`define VX_TYPES_VH + +// Device configuration registers ///////////////////////////////////////////// + +`define VX_CSR_ADDR_BITS 12 +`define VX_DCR_ADDR_BITS 12 + +`define VX_DCR_BASE_STATE_BEGIN 12'h001 +`define VX_DCR_BASE_STARTUP_ADDR0 12'h001 +`define VX_DCR_BASE_STARTUP_ADDR1 12'h002 +`define VX_DCR_BASE_STARTUP_ARG0 12'h003 +`define VX_DCR_BASE_STARTUP_ARG1 12'h004 +`define VX_DCR_BASE_MPM_CLASS 12'h005 +`define VX_DCR_BASE_STATE_END 12'h006 + +`define VX_DCR_BASE_STATE(addr) ((addr) - `VX_DCR_BASE_STATE_BEGIN) +`define VX_DCR_BASE_STATE_COUNT (`VX_DCR_BASE_STATE_END-`VX_DCR_BASE_STATE_BEGIN) + +// Machine Performance-monitoring counters classes //////////////////////////// + +`define VX_DCR_MPM_CLASS_NONE 0 +`define VX_DCR_MPM_CLASS_CORE 1 +`define VX_DCR_MPM_CLASS_MEM 2 + +// User Floating-Point CSRs /////////////////////////////////////////////////// + +`define VX_CSR_FFLAGS 12'h001 +`define VX_CSR_FRM 12'h002 +`define VX_CSR_FCSR 12'h003 + +`define VX_CSR_SATP 12'h180 + +`define VX_CSR_PMPCFG0 12'h3A0 +`define VX_CSR_PMPADDR0 12'h3B0 + +`define VX_CSR_MSTATUS 12'h300 +`define VX_CSR_MISA 12'h301 +`define VX_CSR_MEDELEG 12'h302 +`define VX_CSR_MIDELEG 12'h303 +`define VX_CSR_MIE 12'h304 +`define VX_CSR_MTVEC 12'h305 + +`define VX_CSR_MSCRATCH 12'h340 +`define VX_CSR_MEPC 12'h341 +`define VX_CSR_MCAUSE 12'h342 + +`define VX_CSR_MNSTATUS 12'h744 + +`define VX_CSR_MPM_BASE 12'hB00 +`define VX_CSR_MPM_BASE_H 12'hB80 +`define VX_CSR_MPM_USER 12'hB03 +`define VX_CSR_MPM_USER_H 12'hB83 + +// Machine Performance-monitoring core counters (Standard) //////////////////// + +`define VX_CSR_MCYCLE 12'hB00 +`define VX_CSR_MCYCLE_H 12'hB80 +`define VX_CSR_MPM_RESERVED 12'hB01 +`define VX_CSR_MPM_RESERVED_H 12'hB81 +`define VX_CSR_MINSTRET 12'hB02 +`define VX_CSR_MINSTRET_H 12'hB82 + +// Machine Performance-monitoring core counters (class 1) ///////////////////// + +// PERF: pipeline +`define VX_CSR_MPM_SCHED_ID 12'hB03 +`define VX_CSR_MPM_SCHED_ID_H 12'hB83 +`define VX_CSR_MPM_SCHED_ST 12'hB04 +`define VX_CSR_MPM_SCHED_ST_H 12'hB84 +`define VX_CSR_MPM_IBUF_ST 12'hB05 +`define VX_CSR_MPM_IBUF_ST_H 12'hB85 +`define VX_CSR_MPM_SCRB_ST 12'hB06 +`define VX_CSR_MPM_SCRB_ST_H 12'hB86 +`define VX_CSR_MPM_OPDS_ST 12'hB07 +`define VX_CSR_MPM_OPDS_ST_H 12'hB87 +`define VX_CSR_MPM_SCRB_ALU 12'hB08 +`define VX_CSR_MPM_SCRB_ALU_H 12'hB88 +`define VX_CSR_MPM_SCRB_FPU 12'hB09 +`define VX_CSR_MPM_SCRB_FPU_H 12'hB89 +`define VX_CSR_MPM_SCRB_LSU 12'hB0A +`define VX_CSR_MPM_SCRB_LSU_H 12'hB8A +`define VX_CSR_MPM_SCRB_SFU 12'hB0B +`define VX_CSR_MPM_SCRB_SFU_H 12'hB8B +`define VX_CSR_MPM_SCRB_CSRS 12'hB0C +`define VX_CSR_MPM_SCRB_CSRS_H 12'hB8C +`define VX_CSR_MPM_SCRB_WCTL 12'hB0D +`define VX_CSR_MPM_SCRB_WCTL_H 12'hB8D +`define VX_CSR_MPM_SCRB_VPU 12'hB13 +`define VX_CSR_MPM_SCRB_VPU_H 12'hB93 +`define VX_CSR_MPM_SCRB_TCU 12'hB14 +`define VX_CSR_MPM_SCRB_TCU_H 12'hB94 +// PERF: memory +`define VX_CSR_MPM_IFETCHES 12'hB0E +`define VX_CSR_MPM_IFETCHES_H 12'hB8E +`define VX_CSR_MPM_LOADS 12'hB0F +`define VX_CSR_MPM_LOADS_H 12'hB8F +`define VX_CSR_MPM_STORES 12'hB10 +`define VX_CSR_MPM_STORES_H 12'hB90 +`define VX_CSR_MPM_IFETCH_LT 12'hB11 +`define VX_CSR_MPM_IFETCH_LT_H 12'hB91 +`define VX_CSR_MPM_LOAD_LT 12'hB12 +`define VX_CSR_MPM_LOAD_LT_H 12'hB92 + +// Machine Performance-monitoring memory counters (class 2) /////////////////// + +// PERF: icache +`define VX_CSR_MPM_ICACHE_READS 12'hB03 // total reads +`define VX_CSR_MPM_ICACHE_READS_H 12'hB83 +`define VX_CSR_MPM_ICACHE_MISS_R 12'hB04 // read misses +`define VX_CSR_MPM_ICACHE_MISS_R_H 12'hB84 +`define VX_CSR_MPM_ICACHE_MSHR_ST 12'hB05 // MSHR stalls +`define VX_CSR_MPM_ICACHE_MSHR_ST_H 12'hB85 +// PERF: dcache +`define VX_CSR_MPM_DCACHE_READS 12'hB06 // total reads +`define VX_CSR_MPM_DCACHE_READS_H 12'hB86 +`define VX_CSR_MPM_DCACHE_WRITES 12'hB07 // total writes +`define VX_CSR_MPM_DCACHE_WRITES_H 12'hB87 +`define VX_CSR_MPM_DCACHE_MISS_R 12'hB08 // read misses +`define VX_CSR_MPM_DCACHE_MISS_R_H 12'hB88 +`define VX_CSR_MPM_DCACHE_MISS_W 12'hB09 // write misses +`define VX_CSR_MPM_DCACHE_MISS_W_H 12'hB89 +`define VX_CSR_MPM_DCACHE_BANK_ST 12'hB0A // bank conflicts +`define VX_CSR_MPM_DCACHE_BANK_ST_H 12'hB8A +`define VX_CSR_MPM_DCACHE_MSHR_ST 12'hB0B // MSHR stalls +`define VX_CSR_MPM_DCACHE_MSHR_ST_H 12'hB8B +// PERF: l2cache +`define VX_CSR_MPM_L2CACHE_READS 12'hB0C // total reads +`define VX_CSR_MPM_L2CACHE_READS_H 12'hB8C +`define VX_CSR_MPM_L2CACHE_WRITES 12'hB0D // total writes +`define VX_CSR_MPM_L2CACHE_WRITES_H 12'hB8D +`define VX_CSR_MPM_L2CACHE_MISS_R 12'hB0E // read misses +`define VX_CSR_MPM_L2CACHE_MISS_R_H 12'hB8E +`define VX_CSR_MPM_L2CACHE_MISS_W 12'hB0F // write misses +`define VX_CSR_MPM_L2CACHE_MISS_W_H 12'hB8F +`define VX_CSR_MPM_L2CACHE_BANK_ST 12'hB10 // bank conflicts +`define VX_CSR_MPM_L2CACHE_BANK_ST_H 12'hB90 +`define VX_CSR_MPM_L2CACHE_MSHR_ST 12'hB11 // MSHR stalls +`define VX_CSR_MPM_L2CACHE_MSHR_ST_H 12'hB91 +// PERF: l3cache +`define VX_CSR_MPM_L3CACHE_READS 12'hB12 // total reads +`define VX_CSR_MPM_L3CACHE_READS_H 12'hB92 +`define VX_CSR_MPM_L3CACHE_WRITES 12'hB13 // total writes +`define VX_CSR_MPM_L3CACHE_WRITES_H 12'hB93 +`define VX_CSR_MPM_L3CACHE_MISS_R 12'hB14 // read misses +`define VX_CSR_MPM_L3CACHE_MISS_R_H 12'hB94 +`define VX_CSR_MPM_L3CACHE_MISS_W 12'hB15 // write misses +`define VX_CSR_MPM_L3CACHE_MISS_W_H 12'hB95 +`define VX_CSR_MPM_L3CACHE_BANK_ST 12'hB16 // bank conflicts +`define VX_CSR_MPM_L3CACHE_BANK_ST_H 12'hB96 +`define VX_CSR_MPM_L3CACHE_MSHR_ST 12'hB17 // MSHR stalls +`define VX_CSR_MPM_L3CACHE_MSHR_ST_H 12'hB97 +// PERF: memory +`define VX_CSR_MPM_MEM_READS 12'hB18 // total reads +`define VX_CSR_MPM_MEM_READS_H 12'hB98 +`define VX_CSR_MPM_MEM_WRITES 12'hB19 // total writes +`define VX_CSR_MPM_MEM_WRITES_H 12'hB99 +`define VX_CSR_MPM_MEM_LT 12'hB1A // memory latency +`define VX_CSR_MPM_MEM_LT_H 12'hB9A +`define VX_CSR_MPM_MEM_BANK_ST 12'hB1E // bank conflicts +`define VX_CSR_MPM_MEM_BANK_ST_H 12'hB9E +// PERF: lmem +`define VX_CSR_MPM_LMEM_READS 12'hB1B // memory reads +`define VX_CSR_MPM_LMEM_READS_H 12'hB9B +`define VX_CSR_MPM_LMEM_WRITES 12'hB1C // memory writes +`define VX_CSR_MPM_LMEM_WRITES_H 12'hB9C +`define VX_CSR_MPM_LMEM_BANK_ST 12'hB1D // bank conflicts +`define VX_CSR_MPM_LMEM_BANK_ST_H 12'hB9D +// PERF: coalescer +`define VX_CSR_MPM_COALESCER_MISS 12'hB1F // coalescer misses +`define VX_CSR_MPM_COALESCER_MISS_H 12'hB9F + +// + +// Machine Information Registers ////////////////////////////////////////////// + +`define VX_CSR_MVENDORID 12'hF11 +`define VX_CSR_MARCHID 12'hF12 +`define VX_CSR_MIMPID 12'hF13 +`define VX_CSR_MHARTID 12'hF14 + +// Vector CSRs + +`define VX_CSR_VSTART 12'h008 +`define VX_CSR_VXSAT 12'h009 +`define VX_CSR_VXRM 12'h00A +`define VX_CSR_VCSR 12'h00F +`define VX_CSR_VL 12'hC20 +`define VX_CSR_VTYPE 12'hC21 +`define VX_CSR_VLENB 12'hC22 + +// GPGU CSRs + +`define VX_CSR_THREAD_ID 12'hCC0 +`define VX_CSR_WARP_ID 12'hCC1 +`define VX_CSR_CORE_ID 12'hCC2 +`define VX_CSR_ACTIVE_WARPS 12'hCC3 +`define VX_CSR_ACTIVE_THREADS 12'hCC4 // warning! this value is also used in LLVM + +`define VX_CSR_NUM_THREADS 12'hFC0 +`define VX_CSR_NUM_WARPS 12'hFC1 +`define VX_CSR_NUM_CORES 12'hFC2 +`define VX_CSR_LOCAL_MEM_BASE 12'hFC3 + +`endif // VX_TYPES_VH diff --git a/designs/src/vortex/rtl/Vortex.sv b/designs/src/vortex/rtl/Vortex.sv new file mode 100644 index 0000000..eee08c7 --- /dev/null +++ b/designs/src/vortex/rtl/Vortex.sv @@ -0,0 +1,237 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module Vortex import VX_gpu_pkg::*; ( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + + // Memory request + output wire mem_req_valid [VX_MEM_PORTS], + output wire mem_req_rw [VX_MEM_PORTS], + output wire [VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen [VX_MEM_PORTS], + output wire [VX_MEM_ADDR_WIDTH-1:0] mem_req_addr [VX_MEM_PORTS], + output wire [VX_MEM_DATA_WIDTH-1:0] mem_req_data [VX_MEM_PORTS], + output wire [VX_MEM_TAG_WIDTH-1:0] mem_req_tag [VX_MEM_PORTS], + input wire mem_req_ready [VX_MEM_PORTS], + + // Memory response + input wire mem_rsp_valid [VX_MEM_PORTS], + input wire [VX_MEM_DATA_WIDTH-1:0] mem_rsp_data [VX_MEM_PORTS], + input wire [VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag [VX_MEM_PORTS], + output wire mem_rsp_ready [VX_MEM_PORTS], + + // DCR write request + input wire dcr_wr_valid, + input wire [VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + input wire [VX_DCR_DATA_WIDTH-1:0] dcr_wr_data, + + // Status + output wire busy +); + +`ifdef SCOPE + localparam scope_cluster = 0; + `SCOPE_IO_SWITCH (`NUM_CLUSTERS); +`endif + +`ifdef PERF_ENABLE + cache_perf_t l3_perf; + mem_perf_t mem_perf; + sysmem_perf_t sysmem_perf; + always @(*) begin + sysmem_perf = '0; + sysmem_perf.l3cache = l3_perf; + sysmem_perf.mem = mem_perf; + end +`endif + + VX_mem_bus_if #( + .DATA_SIZE (`L2_LINE_SIZE), + .TAG_WIDTH (L2_MEM_TAG_WIDTH) + ) per_cluster_mem_bus_if[`NUM_CLUSTERS * `L2_MEM_PORTS](); + + VX_mem_bus_if #( + .DATA_SIZE (`L3_LINE_SIZE), + .TAG_WIDTH (L3_MEM_TAG_WIDTH) + ) mem_bus_if[`L3_MEM_PORTS](); + + `RESET_RELAY (l3_reset, reset); + + VX_cache_wrap #( + .INSTANCE_ID ("l3cache"), + .CACHE_SIZE (`L3_CACHE_SIZE), + .LINE_SIZE (`L3_LINE_SIZE), + .NUM_BANKS (`L3_NUM_BANKS), + .NUM_WAYS (`L3_NUM_WAYS), + .WORD_SIZE (L3_WORD_SIZE), + .NUM_REQS (L3_NUM_REQS), + .MEM_PORTS (`L3_MEM_PORTS), + .CRSQ_SIZE (`L3_CRSQ_SIZE), + .MSHR_SIZE (`L3_MSHR_SIZE), + .MRSQ_SIZE (`L3_MRSQ_SIZE), + .MREQ_SIZE (`L3_WRITEBACK ? `L3_MSHR_SIZE : `L3_MREQ_SIZE), + .TAG_WIDTH (L2_MEM_TAG_WIDTH), + .WRITE_ENABLE (1), + .WRITEBACK (`L3_WRITEBACK), + .DIRTY_BYTES (`L3_DIRTYBYTES), + .REPL_POLICY (`L3_REPL_POLICY), + .CORE_OUT_BUF (3), + .MEM_OUT_BUF (3), + .NC_ENABLE (1), + .PASSTHRU (!`L3_ENABLED) + ) l3cache ( + .clk (clk), + .reset (l3_reset), + + `ifdef PERF_ENABLE + .cache_perf (l3_perf), + `endif + + .core_bus_if (per_cluster_mem_bus_if), + .mem_bus_if (mem_bus_if) + ); + + for (genvar i = 0; i < `L3_MEM_PORTS; ++i) begin : g_mem_bus_if + assign mem_req_valid[i] = mem_bus_if[i].req_valid; + assign mem_req_rw[i] = mem_bus_if[i].req_data.rw; + assign mem_req_byteen[i] = mem_bus_if[i].req_data.byteen; + assign mem_req_addr[i] = mem_bus_if[i].req_data.addr; + assign mem_req_data[i] = mem_bus_if[i].req_data.data; + assign mem_req_tag[i] = mem_bus_if[i].req_data.tag; + `UNUSED_VAR (mem_bus_if[i].req_data.flags) + assign mem_bus_if[i].req_ready = mem_req_ready[i]; + + assign mem_bus_if[i].rsp_valid = mem_rsp_valid[i]; + assign mem_bus_if[i].rsp_data.data = mem_rsp_data[i]; + assign mem_bus_if[i].rsp_data.tag = mem_rsp_tag[i]; + assign mem_rsp_ready[i] = mem_bus_if[i].rsp_ready; + end + + VX_dcr_bus_if dcr_bus_if(); + assign dcr_bus_if.write_valid = dcr_wr_valid; + assign dcr_bus_if.write_addr = dcr_wr_addr; + assign dcr_bus_if.write_data = dcr_wr_data; + + wire [`NUM_CLUSTERS-1:0] per_cluster_busy; + + // Generate all clusters + for (genvar cluster_id = 0; cluster_id < `NUM_CLUSTERS; ++cluster_id) begin : g_clusters + + `RESET_RELAY (cluster_reset, reset); + + VX_dcr_bus_if cluster_dcr_bus_if(); + `BUFFER_DCR_BUS_IF (cluster_dcr_bus_if, dcr_bus_if, 1'b1, (`NUM_CLUSTERS > 1)) + + VX_cluster #( + .CLUSTER_ID (cluster_id), + .INSTANCE_ID (`SFORMATF(("cluster%0d", cluster_id))) + ) cluster ( + `SCOPE_IO_BIND (scope_cluster + cluster_id) + + .clk (clk), + .reset (cluster_reset), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf), + `endif + + .dcr_bus_if (cluster_dcr_bus_if), + + .mem_bus_if (per_cluster_mem_bus_if[cluster_id * `L2_MEM_PORTS +: `L2_MEM_PORTS]), + + .busy (per_cluster_busy[cluster_id]) + ); + end + + `BUFFER_EX(busy, (| per_cluster_busy), 1'b1, 1, (`NUM_CLUSTERS > 1)); + +`ifdef PERF_ENABLE + + localparam MEM_PORTS_CTR_W = `CLOG2(VX_MEM_PORTS+1); + + wire [VX_MEM_PORTS-1:0] mem_req_fire, mem_rsp_fire; + wire [VX_MEM_PORTS-1:0] mem_rd_req_fire, mem_wr_req_fire; + + for (genvar i = 0; i < VX_MEM_PORTS; ++i) begin : g_perf_ctrs + assign mem_req_fire[i] = mem_req_valid[i] & mem_req_ready[i]; + assign mem_rsp_fire[i] = mem_rsp_valid[i] & mem_rsp_ready[i]; + assign mem_rd_req_fire[i] = mem_req_fire[i] & ~mem_req_rw[i]; + assign mem_wr_req_fire[i] = mem_req_fire[i] & mem_req_rw[i]; + end + + wire [MEM_PORTS_CTR_W-1:0] perf_mem_reads_per_cycle; + wire [MEM_PORTS_CTR_W-1:0] perf_mem_writes_per_cycle; + wire [MEM_PORTS_CTR_W-1:0] perf_mem_rsps_per_cycle; + + `POP_COUNT(perf_mem_reads_per_cycle, mem_rd_req_fire); + `POP_COUNT(perf_mem_writes_per_cycle, mem_wr_req_fire); + `POP_COUNT(perf_mem_rsps_per_cycle, mem_rsp_fire); + + reg [PERF_CTR_BITS-1:0] perf_mem_pending_reads; + + always @(posedge clk) begin + if (reset) begin + perf_mem_pending_reads <= '0; + end else begin + perf_mem_pending_reads <= $signed(perf_mem_pending_reads) + + PERF_CTR_BITS'($signed((MEM_PORTS_CTR_W+1)'(perf_mem_reads_per_cycle) - (MEM_PORTS_CTR_W+1)'(perf_mem_rsps_per_cycle))); + end + end + + always @(posedge clk) begin + if (reset) begin + mem_perf <= '0; + end else begin + mem_perf.reads <= mem_perf.reads + PERF_CTR_BITS'(perf_mem_reads_per_cycle); + mem_perf.writes <= mem_perf.writes + PERF_CTR_BITS'(perf_mem_writes_per_cycle); + mem_perf.latency <= mem_perf.latency + perf_mem_pending_reads; + end + end + +`endif + + // dump device configuration + initial begin + `TRACE(0, ("CONFIGS: num_threads=%0d, num_warps=%0d, num_cores=%0d, num_clusters=%0d, socket_size=%0d, local_mem_base=0x%0h, num_barriers=%0d\n", + `NUM_THREADS, `NUM_WARPS, `NUM_CORES, `NUM_CLUSTERS, `SOCKET_SIZE, `LMEM_BASE_ADDR, `NUM_BARRIERS)) + end + +`ifdef DBG_TRACE_MEM + for (genvar i = 0; i < VX_MEM_PORTS; ++i) begin : g_trace + always @(posedge clk) begin + if (mem_bus_if[i].req_valid && mem_bus_if[i].req_ready) begin + if (mem_bus_if[i].req_data.rw) begin + `TRACE(2, ("%t: MEM Wr Req[%0d]: addr=0x%0h, byteen=0x%h data=0x%h, tag=0x%0h (#%0d)\n", $time, i, `TO_FULL_ADDR(mem_bus_if[i].req_data.addr), mem_bus_if[i].req_data.byteen, mem_bus_if[i].req_data.data, mem_bus_if[i].req_data.tag.value, mem_bus_if[i].req_data.tag.uuid)) + end else begin + `TRACE(2, ("%t: MEM Rd Req[%0d]: addr=0x%0h, byteen=0x%h, tag=0x%0h (#%0d)\n", $time, i, `TO_FULL_ADDR(mem_bus_if[i].req_data.addr), mem_bus_if[i].req_data.byteen, mem_bus_if[i].req_data.tag.value, mem_bus_if[i].req_data.tag.uuid)) + end + end + if (mem_bus_if[i].rsp_valid && mem_bus_if[i].rsp_ready) begin + `TRACE(2, ("%t: MEM Rd Rsp[%0d]: data=0x%h, tag=0x%0h (#%0d)\n", $time, i, mem_bus_if[i].rsp_data.data, mem_bus_if[i].rsp_data.tag.value, mem_bus_if[i].rsp_data.tag.uuid)) + end + end + end +`endif + +`ifdef SIMULATION + always @(posedge clk) begin + $fflush(); // flush stdout buffer + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/Vortex_axi.sv b/designs/src/vortex/rtl/Vortex_axi.sv new file mode 100644 index 0000000..a7fb8ab --- /dev/null +++ b/designs/src/vortex/rtl/Vortex_axi.sv @@ -0,0 +1,261 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module Vortex_axi import VX_gpu_pkg::*; #( + parameter AXI_DATA_WIDTH = VX_MEM_DATA_WIDTH, + parameter AXI_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter AXI_TID_WIDTH = VX_MEM_TAG_WIDTH, + parameter AXI_NUM_BANKS = 1 +)( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + + // AXI write request address channel + output wire m_axi_awvalid [AXI_NUM_BANKS], + input wire m_axi_awready [AXI_NUM_BANKS], + output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr [AXI_NUM_BANKS], + output wire [AXI_TID_WIDTH-1:0] m_axi_awid [AXI_NUM_BANKS], + output wire [7:0] m_axi_awlen [AXI_NUM_BANKS], + output wire [2:0] m_axi_awsize [AXI_NUM_BANKS], + output wire [1:0] m_axi_awburst [AXI_NUM_BANKS], + output wire [1:0] m_axi_awlock [AXI_NUM_BANKS], + output wire [3:0] m_axi_awcache [AXI_NUM_BANKS], + output wire [2:0] m_axi_awprot [AXI_NUM_BANKS], + output wire [3:0] m_axi_awqos [AXI_NUM_BANKS], + output wire [3:0] m_axi_awregion [AXI_NUM_BANKS], + + // AXI write request data channel + output wire m_axi_wvalid [AXI_NUM_BANKS], + input wire m_axi_wready [AXI_NUM_BANKS], + output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata [AXI_NUM_BANKS], + output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb [AXI_NUM_BANKS], + output wire m_axi_wlast [AXI_NUM_BANKS], + + // AXI write response channel + input wire m_axi_bvalid [AXI_NUM_BANKS], + output wire m_axi_bready [AXI_NUM_BANKS], + input wire [AXI_TID_WIDTH-1:0] m_axi_bid [AXI_NUM_BANKS], + input wire [1:0] m_axi_bresp [AXI_NUM_BANKS], + + // AXI read request channel + output wire m_axi_arvalid [AXI_NUM_BANKS], + input wire m_axi_arready [AXI_NUM_BANKS], + output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr [AXI_NUM_BANKS], + output wire [AXI_TID_WIDTH-1:0] m_axi_arid [AXI_NUM_BANKS], + output wire [7:0] m_axi_arlen [AXI_NUM_BANKS], + output wire [2:0] m_axi_arsize [AXI_NUM_BANKS], + output wire [1:0] m_axi_arburst [AXI_NUM_BANKS], + output wire [1:0] m_axi_arlock [AXI_NUM_BANKS], + output wire [3:0] m_axi_arcache [AXI_NUM_BANKS], + output wire [2:0] m_axi_arprot [AXI_NUM_BANKS], + output wire [3:0] m_axi_arqos [AXI_NUM_BANKS], + output wire [3:0] m_axi_arregion [AXI_NUM_BANKS], + + // AXI read response channel + input wire m_axi_rvalid [AXI_NUM_BANKS], + output wire m_axi_rready [AXI_NUM_BANKS], + input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata [AXI_NUM_BANKS], + input wire m_axi_rlast [AXI_NUM_BANKS], + input wire [AXI_TID_WIDTH-1:0] m_axi_rid [AXI_NUM_BANKS], + input wire [1:0] m_axi_rresp [AXI_NUM_BANKS], + + // DCR write request + input wire dcr_wr_valid, + input wire [VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + input wire [VX_DCR_DATA_WIDTH-1:0] dcr_wr_data, + + // Status + output wire busy +); + localparam DST_LDATAW = `CLOG2(AXI_DATA_WIDTH); + localparam SRC_LDATAW = `CLOG2(VX_MEM_DATA_WIDTH); + localparam SUB_LDATAW = DST_LDATAW - SRC_LDATAW; + localparam VX_MEM_TAG_A_WIDTH = VX_MEM_TAG_WIDTH + `MAX(SUB_LDATAW, 0); + localparam VX_MEM_ADDR_A_WIDTH = VX_MEM_ADDR_WIDTH - SUB_LDATAW; + + wire mem_req_valid [VX_MEM_PORTS]; + wire mem_req_rw [VX_MEM_PORTS]; + wire [VX_MEM_BYTEEN_WIDTH-1:0] mem_req_byteen [VX_MEM_PORTS]; + wire [VX_MEM_ADDR_WIDTH-1:0] mem_req_addr [VX_MEM_PORTS]; + wire [VX_MEM_DATA_WIDTH-1:0] mem_req_data [VX_MEM_PORTS]; + wire [VX_MEM_TAG_WIDTH-1:0] mem_req_tag [VX_MEM_PORTS]; + wire mem_req_ready [VX_MEM_PORTS]; + + wire mem_rsp_valid [VX_MEM_PORTS]; + wire [VX_MEM_DATA_WIDTH-1:0] mem_rsp_data [VX_MEM_PORTS]; + wire [VX_MEM_TAG_WIDTH-1:0] mem_rsp_tag [VX_MEM_PORTS]; + wire mem_rsp_ready [VX_MEM_PORTS]; + + `SCOPE_IO_SWITCH (1); + + Vortex vortex ( + `SCOPE_IO_BIND (0) + + .clk (clk), + .reset (reset), + + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), + + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready), + + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data), + + .busy (busy) + ); + + wire mem_req_valid_a [VX_MEM_PORTS]; + wire mem_req_rw_a [VX_MEM_PORTS]; + wire [(AXI_DATA_WIDTH/8)-1:0] mem_req_byteen_a [VX_MEM_PORTS]; + wire [VX_MEM_ADDR_A_WIDTH-1:0] mem_req_addr_a [VX_MEM_PORTS]; + wire [AXI_DATA_WIDTH-1:0] mem_req_data_a [VX_MEM_PORTS]; + wire [VX_MEM_TAG_A_WIDTH-1:0] mem_req_tag_a [VX_MEM_PORTS]; + wire mem_req_ready_a [VX_MEM_PORTS]; + + wire mem_rsp_valid_a [VX_MEM_PORTS]; + wire [AXI_DATA_WIDTH-1:0] mem_rsp_data_a [VX_MEM_PORTS]; + wire [VX_MEM_TAG_A_WIDTH-1:0] mem_rsp_tag_a [VX_MEM_PORTS]; + wire mem_rsp_ready_a [VX_MEM_PORTS]; + + // Adjust memory data width to match AXI interface + for (genvar i = 0; i < VX_MEM_PORTS; i++) begin : g_mem_adapter + VX_mem_data_adapter #( + .SRC_DATA_WIDTH (VX_MEM_DATA_WIDTH), + .DST_DATA_WIDTH (AXI_DATA_WIDTH), + .SRC_ADDR_WIDTH (VX_MEM_ADDR_WIDTH), + .DST_ADDR_WIDTH (VX_MEM_ADDR_A_WIDTH), + .SRC_TAG_WIDTH (VX_MEM_TAG_WIDTH), + .DST_TAG_WIDTH (VX_MEM_TAG_A_WIDTH), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (0) + ) mem_data_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (mem_req_valid[i]), + .mem_req_addr_in (mem_req_addr[i]), + .mem_req_rw_in (mem_req_rw[i]), + .mem_req_byteen_in (mem_req_byteen[i]), + .mem_req_data_in (mem_req_data[i]), + .mem_req_tag_in (mem_req_tag[i]), + .mem_req_ready_in (mem_req_ready[i]), + + .mem_rsp_valid_in (mem_rsp_valid[i]), + .mem_rsp_data_in (mem_rsp_data[i]), + .mem_rsp_tag_in (mem_rsp_tag[i]), + .mem_rsp_ready_in (mem_rsp_ready[i]), + + .mem_req_valid_out (mem_req_valid_a[i]), + .mem_req_addr_out (mem_req_addr_a[i]), + .mem_req_rw_out (mem_req_rw_a[i]), + .mem_req_byteen_out (mem_req_byteen_a[i]), + .mem_req_data_out (mem_req_data_a[i]), + .mem_req_tag_out (mem_req_tag_a[i]), + .mem_req_ready_out (mem_req_ready_a[i]), + + .mem_rsp_valid_out (mem_rsp_valid_a[i]), + .mem_rsp_data_out (mem_rsp_data_a[i]), + .mem_rsp_tag_out (mem_rsp_tag_a[i]), + .mem_rsp_ready_out (mem_rsp_ready_a[i]) + ); + end + + VX_axi_adapter #( + .DATA_WIDTH (AXI_DATA_WIDTH), + .ADDR_WIDTH_IN (VX_MEM_ADDR_A_WIDTH), + .ADDR_WIDTH_OUT (AXI_ADDR_WIDTH), + .TAG_WIDTH_IN (VX_MEM_TAG_A_WIDTH), + .TAG_WIDTH_OUT (AXI_TID_WIDTH), + .NUM_PORTS_IN (VX_MEM_PORTS), + .NUM_BANKS_OUT (AXI_NUM_BANKS), + .INTERLEAVE (`PLATFORM_MEMORY_INTERLEAVE), + .REQ_OUT_BUF ((VX_MEM_PORTS > 1) ? 2 : 0), + .RSP_OUT_BUF ((VX_MEM_PORTS > 1 || AXI_NUM_BANKS > 1) ? 2 : 0) + ) axi_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid (mem_req_valid_a), + .mem_req_rw (mem_req_rw_a), + .mem_req_byteen (mem_req_byteen_a), + .mem_req_addr (mem_req_addr_a), + .mem_req_data (mem_req_data_a), + .mem_req_tag (mem_req_tag_a), + .mem_req_ready (mem_req_ready_a), + + .mem_rsp_valid (mem_rsp_valid_a), + .mem_rsp_data (mem_rsp_data_a), + .mem_rsp_tag (mem_rsp_tag_a), + .mem_rsp_ready (mem_rsp_ready_a), + + .m_axi_awvalid (m_axi_awvalid), + .m_axi_awready (m_axi_awready), + .m_axi_awaddr (m_axi_awaddr), + .m_axi_awid (m_axi_awid), + .m_axi_awlen (m_axi_awlen), + .m_axi_awsize (m_axi_awsize), + .m_axi_awburst (m_axi_awburst), + .m_axi_awlock (m_axi_awlock), + .m_axi_awcache (m_axi_awcache), + .m_axi_awprot (m_axi_awprot), + .m_axi_awqos (m_axi_awqos), + .m_axi_awregion (m_axi_awregion), + + .m_axi_wvalid (m_axi_wvalid), + .m_axi_wready (m_axi_wready), + .m_axi_wdata (m_axi_wdata), + .m_axi_wstrb (m_axi_wstrb), + .m_axi_wlast (m_axi_wlast), + + .m_axi_bvalid (m_axi_bvalid), + .m_axi_bready (m_axi_bready), + .m_axi_bid (m_axi_bid), + .m_axi_bresp (m_axi_bresp), + + .m_axi_arvalid (m_axi_arvalid), + .m_axi_arready (m_axi_arready), + .m_axi_araddr (m_axi_araddr), + .m_axi_arid (m_axi_arid), + .m_axi_arlen (m_axi_arlen), + .m_axi_arsize (m_axi_arsize), + .m_axi_arburst (m_axi_arburst), + .m_axi_arlock (m_axi_arlock), + .m_axi_arcache (m_axi_arcache), + .m_axi_arprot (m_axi_arprot), + .m_axi_arqos (m_axi_arqos), + .m_axi_arregion (m_axi_arregion), + + .m_axi_rvalid (m_axi_rvalid), + .m_axi_rready (m_axi_rready), + .m_axi_rdata (m_axi_rdata), + .m_axi_rlast (m_axi_rlast), + .m_axi_rid (m_axi_rid), + .m_axi_rresp (m_axi_rresp) + ); + +endmodule diff --git a/designs/src/vortex/rtl/afu/opae/ccip/ccip_if_pkg.sv b/designs/src/vortex/rtl/afu/opae/ccip/ccip_if_pkg.sv new file mode 100644 index 0000000..ba399b7 --- /dev/null +++ b/designs/src/vortex/rtl/afu/opae/ccip/ccip_if_pkg.sv @@ -0,0 +1,244 @@ +// Date: 02/2/2016 +// Compliant with CCI-P spec v0.71 +package ccip_if_pkg; + +//===================================================================== +// CCI-P interface defines +//===================================================================== +parameter CCIP_VERSION_NUMBER = 12'h071; + +parameter CCIP_CLADDR_WIDTH = 42; +parameter CCIP_CLDATA_WIDTH = 512; + +parameter CCIP_MMIOADDR_WIDTH = 16; +parameter CCIP_MMIODATA_WIDTH = 64; +parameter CCIP_TID_WIDTH = 9; + +parameter CCIP_MDATA_WIDTH = 16; + + +// Number of requests that can be accepted after almost full is asserted. +parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8; + +parameter CCIP_MMIO_RD_TIMEOUT = 512; + +parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset + +// Base types +//---------------------------------------------------------------------- +typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr; +typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData; + + +typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr; +typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData; +typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid; + + +typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata; +typedef logic [1:0] t_ccip_clNum; +typedef logic [2:0] t_ccip_qwIdx; + + +// Request Type Encodings +//---------------------------------------------------------------------- +// Channel 0 +typedef enum logic [3:0] { + eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid + eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared +} t_ccip_c0_req; + +// Channel 1 +typedef enum logic [3:0] { + eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid + eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified + eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY ** + eREQ_WRFENCE = 4'h4, // Memory Write Fence +// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY ** + eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY ** +} t_ccip_c1_req; + +// Response Type Encodings +//---------------------------------------------------------------------- +// Channel 0 +typedef enum logic [3:0] { + eRSP_RDLINE = 4'h0, // Memory Read + eRSP_UMSG = 4'h4 // UMsg received +// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr +} t_ccip_c0_rsp; + +// Channel 1 +typedef enum logic [3:0] { + eRSP_WRLINE = 4'h0, // Memory Write + eRSP_WRFENCE = 4'h4, // Memory Write Fence + eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY ** +} t_ccip_c1_rsp; + +// +// Virtual Channel Select +//---------------------------------------------------------------------- +typedef enum logic [1:0] { + eVC_VA = 2'b00, + eVC_VL0 = 2'b01, + eVC_VH0 = 2'b10, + eVC_VH1 = 2'b11 +} t_ccip_vc; + +// Multi-CL Memory Request +//---------------------------------------------------------------------- +typedef enum logic [1:0] { + eCL_LEN_1 = 2'b00, + eCL_LEN_2 = 2'b01, + eCL_LEN_4 = 2'b11 +} t_ccip_clLen; + +// +// Structures for Request and Response headers +//---------------------------------------------------------------------- +typedef struct packed { + t_ccip_vc vc_sel; + logic [1:0] rsvd1; // reserved, drive 0 + t_ccip_clLen cl_len; + t_ccip_c0_req req_type; + logic [5:0] rsvd0; // reserved, drive 0 + t_ccip_clAddr address; + t_ccip_mdata mdata; +} t_ccip_c0_ReqMemHdr; +parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr); + +typedef struct packed { + logic [5:0] rsvd2; + t_ccip_vc vc_sel; + logic sop; + logic rsvd1; // reserved, drive 0 + t_ccip_clLen cl_len; + t_ccip_c1_req req_type; + logic [5:0] rsvd0; // reserved, drive 0 + t_ccip_clAddr address; + t_ccip_mdata mdata; +} t_ccip_c1_ReqMemHdr; +parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr); + +typedef struct packed { + logic [5:0] rsvd2; // reserved, drive 0 + t_ccip_vc vc_sel; + logic [3:0] rsvd1; // reserved, drive 0 + t_ccip_c1_req req_type; + logic [47:0] rsvd0; // reserved, drive 0 + t_ccip_mdata mdata; +}t_ccip_c1_ReqFenceHdr; + +typedef struct packed { + t_ccip_vc vc_used; + logic rsvd1; // reserved, don't care + logic hit_miss; + logic [1:0] rsvd0; // reserved, don't care + t_ccip_clNum cl_num; + t_ccip_c0_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c0_RspMemHdr; +parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr); + +typedef struct packed { + t_ccip_vc vc_used; + logic rsvd1; // reserved, don't care + logic hit_miss; + logic format; + logic rsvd0; // reserved, don't care + t_ccip_clNum cl_num; + t_ccip_c1_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c1_RspMemHdr; +parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr); + +typedef struct packed { + logic [7:0] rsvd0; // reserved, don't care + t_ccip_c1_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c1_RspFenceHdr; + +// Alternate Channel 0 MMIO request from host : +// MMIO requests arrive on the same channel as read responses, sharing +// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set +// the message is an MMIO request and should be processed by casting +// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr. +typedef struct packed { + t_ccip_mmioAddr address; // 4B aligned Mmio address + logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B + logic rsvd; // reserved, don't care + t_ccip_tid tid; +} t_ccip_c0_ReqMmioHdr; + +typedef struct packed { + t_ccip_tid tid; // Returned back from ReqMmioHdr +} t_ccip_c2_RspMmioHdr; +parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr); + +//------------------------------------------------------------------------ +// CCI-P Input & Output bus structures +// +// Users are encouraged to use these for AFU development +//------------------------------------------------------------------------ +// Channel 0 : Memory Reads +typedef struct packed { + t_ccip_c0_ReqMemHdr hdr; // Request Header + logic valid; // Request Valid +} t_if_ccip_c0_Tx; + + +// Channel 1 : Memory Writes, Interrupts, CmpXchg +typedef struct packed { + t_ccip_c1_ReqMemHdr hdr; // Request Header + t_ccip_clData data; // Request Data + logic valid; // Request Wr Valid +} t_if_ccip_c1_Tx; + +// Channel 2 : MMIO Read response +typedef struct packed { + t_ccip_c2_RspMmioHdr hdr; // Response Header + logic mmioRdValid; // Response Read Valid + t_ccip_mmioData data; // Response Data +} t_if_ccip_c2_Tx; + +// Wrap all Tx channels +typedef struct packed { + t_if_ccip_c0_Tx c0; + t_if_ccip_c1_Tx c1; + t_if_ccip_c2_Tx c2; +} t_if_ccip_Tx; + +// Channel 0: Memory Read response, MMIO Request +typedef struct packed { + t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header + t_ccip_clData data; // Rd Data / MMIO req Data + // Only one of valid, mmioRdValid and mmioWrValid may be set + // in a cycle. When either mmioRdValid or mmioWrValid are true + // the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr + // above. + logic rspValid; // Rd Response Valid + logic mmioRdValid; // MMIO Read Valid + logic mmioWrValid; // MMIO Write Valid +} t_if_ccip_c0_Rx; + +// Channel 1: Memory Writes +typedef struct packed { + t_ccip_c1_RspMemHdr hdr; // Response Header + logic rspValid; // Response Valid +} t_if_ccip_c1_Rx; + +// Wrap all channels +typedef struct packed { + logic c0TxAlmFull; // C0 Request Channel Almost Full + logic c1TxAlmFull; // C1 Request Channel Almost Full + + t_if_ccip_c0_Rx c0; + t_if_ccip_c1_Rx c1; +} t_if_ccip_Rx; + + +typedef union packed { + t_ccip_c0_RspMemHdr rspMemHdr; + t_ccip_c0_ReqMmioHdr reqMmioHdr; +} t_if_ccip_c0_RxHdr; + +endpackage diff --git a/designs/src/vortex/rtl/afu/opae/ccip_interface_reg.sv b/designs/src/vortex/rtl/afu/opae/ccip_interface_reg.sv new file mode 100644 index 0000000..47e29e6 --- /dev/null +++ b/designs/src/vortex/rtl/afu/opae/ccip_interface_reg.sv @@ -0,0 +1,48 @@ +// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex + +// Register all interface signals + +import ccip_if_pkg::*; +module ccip_interface_reg( + // CCI-P Clocks and Resets + input logic pClk, // 400MHz - CC-P clock domain. Primary Clock + input logic pck_cp2af_softReset_T0, // CCI-P ACTIVE HIGH Soft Reset + input logic [1:0] pck_cp2af_pwrState_T0, // CCI-P AFU Power State + input logic pck_cp2af_error_T0, // CCI-P Protocol Error Detected + // Interface structures + input t_if_ccip_Rx pck_cp2af_sRx_T0, // CCI-P Rx Port + input t_if_ccip_Tx pck_af2cp_sTx_T0, // CCI-P Tx Port + + output logic pck_cp2af_softReset_T1, + output logic [1:0] pck_cp2af_pwrState_T1, + output logic pck_cp2af_error_T1, + + output t_if_ccip_Rx pck_cp2af_sRx_T1, + output t_if_ccip_Tx pck_af2cp_sTx_T1 + +); +(* preserve *) logic pck_cp2af_softReset_T0_q; +(* preserve *) logic [1:0] pck_cp2af_pwrState_T0_q; +(* preserve *) logic pck_cp2af_error_T0_q; +(* preserve *) t_if_ccip_Rx pck_cp2af_sRx_T0_q; +(* preserve *) t_if_ccip_Tx pck_af2cp_sTx_T0_q; + +always@(posedge pClk) +begin + pck_cp2af_softReset_T0_q <= pck_cp2af_softReset_T0; + pck_cp2af_pwrState_T0_q <= pck_cp2af_pwrState_T0; + pck_cp2af_error_T0_q <= pck_cp2af_error_T0; + pck_cp2af_sRx_T0_q <= pck_cp2af_sRx_T0; + pck_af2cp_sTx_T0_q <= pck_af2cp_sTx_T0; +end + +always_comb +begin + pck_cp2af_softReset_T1 = pck_cp2af_softReset_T0_q; + pck_cp2af_pwrState_T1 = pck_cp2af_pwrState_T0_q; + pck_cp2af_error_T1 = pck_cp2af_error_T0_q; + pck_cp2af_sRx_T1 = pck_cp2af_sRx_T0_q; + pck_af2cp_sTx_T1 = pck_af2cp_sTx_T0_q; +end + +endmodule diff --git a/designs/src/vortex/rtl/afu/opae/ccip_std_afu.sv b/designs/src/vortex/rtl/afu/opae/ccip_std_afu.sv new file mode 100644 index 0000000..b042ba6 --- /dev/null +++ b/designs/src/vortex/rtl/afu/opae/ccip_std_afu.sv @@ -0,0 +1,126 @@ +// Code reused from Intel OPAE's 04_local_memory sample program with changes made to fit Vortex + +// Top Level Vortex Driver + +// To be done: +// Check how to run this with OPAE. Looks like setup issue + +`ifndef NOPAE + +`include "platform_if.vh" + +import local_mem_cfg_pkg::*; + +module ccip_std_afu #( + parameter NUM_LOCAL_MEM_BANKS = 2 +) ( + // CCI-P Clocks and Resets + input logic pClk, // Primary CCI-P interface clock. + input logic pClkDiv2, // Aligned, pClk divided by 2. + input logic pClkDiv4, // Aligned, pClk divided by 4. + input logic uClk_usr, // User clock domain. Refer to clock programming guide. + input logic uClk_usrDiv2, // Aligned, user clock divided by 2. + input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset + + input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State + input logic pck_cp2af_error, // CCI-P Protocol Error Detected + + // CCI-P structures + input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port + output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port + + // Local memory interface + avalon_mem_if.to_fiu local_mem[NUM_LOCAL_MEM_BANKS] +); + + // ==================================================================== + // Pick the proper clk and reset, as chosen by the AFU's JSON file + // ==================================================================== + + // The platform may transform the CCI-P clock from pClk to a clock + // chosen in the AFU's JSON file. + logic clk; + assign clk = `PLATFORM_PARAM_CCI_P_CLOCK; + + logic reset; + assign reset = `PLATFORM_PARAM_CCI_P_RESET; + + + // ==================================================================== + // Register signals at interface before consuming them + // ==================================================================== + + (* noprune *) logic [1:0] cp2af_pwrState_T1; + (* noprune *) logic cp2af_error_T1; + + logic reset_T1; + t_if_ccip_Rx cp2af_sRx_T1; + t_if_ccip_Tx af2cp_sTx_T0; + + ccip_interface_reg inst_green_ccip_interface_reg + ( + .pClk (clk), + .pck_cp2af_softReset_T0 (reset), + .pck_cp2af_pwrState_T0 (pck_cp2af_pwrState), + .pck_cp2af_error_T0 (pck_cp2af_error), + .pck_cp2af_sRx_T0 (pck_cp2af_sRx), + .pck_af2cp_sTx_T0 (af2cp_sTx_T0), + + .pck_cp2af_softReset_T1 (reset_T1), + .pck_cp2af_pwrState_T1 (cp2af_pwrState_T1), + .pck_cp2af_error_T1 (cp2af_error_T1), + .pck_cp2af_sRx_T1 (cp2af_sRx_T1), + .pck_af2cp_sTx_T1 (pck_af2cp_sTx) + ); + + + // ==================================================================== + // User AFU goes here + // ==================================================================== + + t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS]; + logic avs_waitrequest [NUM_LOCAL_MEM_BANKS]; + t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS]; + logic avs_readdatavalid [NUM_LOCAL_MEM_BANKS]; + t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS]; + t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS]; + t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS]; + logic avs_write [NUM_LOCAL_MEM_BANKS]; + logic avs_read [NUM_LOCAL_MEM_BANKS]; + + for (genvar b = 0; b < NUM_LOCAL_MEM_BANKS; b++) begin + assign local_mem[b].burstcount = avs_burstcount[b]; + assign local_mem[b].writedata = avs_writedata[b]; + assign local_mem[b].address = avs_address[b]; + assign local_mem[b].byteenable = avs_byteenable[b]; + assign local_mem[b].write = avs_write[b]; + assign local_mem[b].read = avs_read[b]; + + assign avs_waitrequest[b] = local_mem[b].waitrequest; + assign avs_readdata[b] = local_mem[b].readdata; + assign avs_readdatavalid[b] = local_mem[b].readdatavalid; + end + + vortex_afu #( + .NUM_LOCAL_MEM_BANKS(NUM_LOCAL_MEM_BANKS) + ) afu ( + .clk (clk), + .reset (reset_T1), + + .cp2af_sRxPort (cp2af_sRx_T1), + .af2cp_sTxPort (af2cp_sTx_T0), + + .avs_writedata (avs_writedata), + .avs_readdata (avs_readdata), + .avs_address (avs_address), + .avs_waitrequest (avs_waitrequest), + .avs_write (avs_write), + .avs_read (avs_read), + .avs_byteenable (avs_byteenable), + .avs_burstcount (avs_burstcount), + .avs_readdatavalid (avs_readdatavalid) + ); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/afu/opae/local_mem_cfg_pkg.sv b/designs/src/vortex/rtl/afu/opae/local_mem_cfg_pkg.sv new file mode 100644 index 0000000..87b3290 --- /dev/null +++ b/designs/src/vortex/rtl/afu/opae/local_mem_cfg_pkg.sv @@ -0,0 +1,69 @@ +// +// Copyright (c) 2017, Intel Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +`include "VX_define.vh" + +`ifndef PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH +`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH ((`PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_NUM_BANKS)) - $clog2(`PLATFORM_MEMORY_DATA_SIZE)) +`endif + +`ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH +`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH (`PLATFORM_MEMORY_DATA_SIZE * 8) +`endif + +`ifndef PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH +`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4 +`endif + +package local_mem_cfg_pkg; + + parameter LOCAL_MEM_VERSION_NUMBER = 1; + + parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH; + parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH; + + parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH; + + // Number of bytes in a data line + parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8; + + + // Base types + // -------------------------------------------------------------------- + + typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr; + typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data; + + typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt; + + // Byte-level mask of a data line + typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask; + +endpackage // local_mem_cfg_pkg diff --git a/designs/src/vortex/rtl/afu/opae/vortex_afu.sv b/designs/src/vortex/rtl/afu/opae/vortex_afu.sv new file mode 100644 index 0000000..b8f981e --- /dev/null +++ b/designs/src/vortex/rtl/afu/opae/vortex_afu.sv @@ -0,0 +1,1179 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifndef NOPAE +`include "afu_json_info.vh" +`else +`include "vortex_afu.vh" +`endif + +module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_gpu_pkg::*; #( + parameter NUM_LOCAL_MEM_BANKS = 2 +) ( + // global signals + input wire clk, + input wire reset, + + // IF signals between CCI and AFU + input t_if_ccip_Rx cp2af_sRxPort, + output t_if_ccip_Tx af2cp_sTxPort, + + // Avalon signals for local memory access + output t_local_mem_data avs_writedata [NUM_LOCAL_MEM_BANKS], + input t_local_mem_data avs_readdata [NUM_LOCAL_MEM_BANKS], + output t_local_mem_addr avs_address [NUM_LOCAL_MEM_BANKS], + input wire avs_waitrequest [NUM_LOCAL_MEM_BANKS], + output wire avs_write [NUM_LOCAL_MEM_BANKS], + output wire avs_read [NUM_LOCAL_MEM_BANKS], + output t_local_mem_byte_mask avs_byteenable [NUM_LOCAL_MEM_BANKS], + output t_local_mem_burst_cnt avs_burstcount [NUM_LOCAL_MEM_BANKS], + input wire avs_readdatavalid [NUM_LOCAL_MEM_BANKS] +); + localparam LMEM_DATA_WIDTH = $bits(t_local_mem_data); + localparam LMEM_DATA_SIZE = LMEM_DATA_WIDTH / 8; + localparam LMEM_ADDR_WIDTH = $bits(t_local_mem_addr); + + localparam LMEM_BYTE_ADDR_WIDTH = LMEM_ADDR_WIDTH + $clog2(LMEM_DATA_SIZE); + localparam CCI_VX_ADDR_WIDTH = VX_MEM_ADDR_WIDTH + ($clog2(VX_MEM_DATA_WIDTH) - $clog2(LMEM_DATA_WIDTH)); + + localparam LMEM_BURST_CTRW = $bits(t_local_mem_burst_cnt); + + localparam MEM_PORTS_BITS = `CLOG2(VX_MEM_PORTS); + localparam MEM_PORTS_WIDTH = `UP(MEM_PORTS_BITS); + + localparam CCI_DATA_WIDTH = $bits(t_ccip_clData); + localparam CCI_DATA_SIZE = CCI_DATA_WIDTH / 8; + localparam CCI_ADDR_WIDTH = $bits(t_ccip_clAddr); + + localparam RESET_CTR_WIDTH = `CLOG2(`RESET_DELAY+1); + + localparam AVS_RD_QUEUE_SIZE = 32; + localparam VX_AVS_REQ_TAGW = VX_MEM_TAG_WIDTH + `CLOG2(LMEM_DATA_WIDTH) - `CLOG2(VX_MEM_DATA_WIDTH); + localparam CCI_AVS_REQ_TAGW = CCI_ADDR_WIDTH + `CLOG2(LMEM_DATA_WIDTH) - `CLOG2(CCI_DATA_WIDTH); + localparam VX_AVS_REQ_TAGW2 = `MAX(VX_MEM_TAG_WIDTH, VX_AVS_REQ_TAGW); + localparam CCI_AVS_REQ_TAGW2 = `MAX(CCI_ADDR_WIDTH, CCI_AVS_REQ_TAGW); + localparam CCI_VX_TAG_WIDTH = `MAX(VX_AVS_REQ_TAGW2, CCI_AVS_REQ_TAGW2); + localparam AVS_TAG_WIDTH = CCI_VX_TAG_WIDTH + 1; // adding the arbiter bit + + localparam CCI_RD_WINDOW_SIZE = 8; + localparam CCI_RW_PENDING_SIZE= 256; + + localparam AFU_ID_L = 16'h0002; // AFU ID Lower + localparam AFU_ID_H = 16'h0004; // AFU ID Higher + + localparam CMD_IDLE = 0; + localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ; + localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE; + localparam CMD_DCR_WRITE = `AFU_IMAGE_CMD_DCR_WRITE; + localparam CMD_RUN = `AFU_IMAGE_CMD_RUN; + localparam CMD_TYPE_WIDTH = `CLOG2(`AFU_IMAGE_CMD_MAX_VALUE+1); + + localparam MMIO_CMD_TYPE = `AFU_IMAGE_MMIO_CMD_TYPE; + localparam MMIO_CMD_ARG0 = `AFU_IMAGE_MMIO_CMD_ARG0; + localparam MMIO_CMD_ARG1 = `AFU_IMAGE_MMIO_CMD_ARG1; + localparam MMIO_CMD_ARG2 = `AFU_IMAGE_MMIO_CMD_ARG2; + localparam MMIO_STATUS = `AFU_IMAGE_MMIO_STATUS; + + localparam COUT_TID_WIDTH = `CLOG2(VX_MEM_BYTEEN_WIDTH); + localparam COUT_QUEUE_DATAW = COUT_TID_WIDTH + 8; + localparam COUT_QUEUE_SIZE = 1024; + + localparam MMIO_DEV_CAPS = `AFU_IMAGE_MMIO_DEV_CAPS; + localparam MMIO_ISA_CAPS = `AFU_IMAGE_MMIO_ISA_CAPS; + + localparam CCI_RD_QUEUE_SIZE = 2 * CCI_RD_WINDOW_SIZE; + localparam CCI_RD_QUEUE_TAGW = `CLOG2(CCI_RD_WINDOW_SIZE); + localparam CCI_RD_QUEUE_DATAW = CCI_DATA_WIDTH + CCI_ADDR_WIDTH; + + localparam STATE_IDLE = 0; + localparam STATE_MEM_WRITE = 1; + localparam STATE_MEM_READ = 2; + localparam STATE_RUN = 3; + localparam STATE_DCR_WRITE = 4; + localparam STATE_WIDTH = `CLOG2(STATE_DCR_WRITE+1); + + wire [127:0] afu_id = `AFU_ACCEL_UUID; + + wire [63:0] dev_caps = {8'b0, + 5'(LMEM_BYTE_ADDR_WIDTH-20), + 3'(`CLOG2(NUM_LOCAL_MEM_BANKS)), + 8'(`LMEM_ENABLED ? `LMEM_LOG_SIZE : 0), + 16'(`NUM_CORES * `NUM_CLUSTERS), + 8'(`NUM_WARPS), + 8'(`NUM_THREADS), + 8'(`IMPLEMENTATION_ID)}; + + wire [63:0] isa_caps = {32'(`MISA_EXT), + 2'(`CLOG2(`XLEN)-4), + 30'(`MISA_STD)}; + + reg [STATE_WIDTH-1:0] state; + + // Vortex ports /////////////////////////////////////////////////////////// + + wire vx_mem_req_valid [VX_MEM_PORTS]; + wire vx_mem_req_rw [VX_MEM_PORTS]; + wire [VX_MEM_BYTEEN_WIDTH-1:0] vx_mem_req_byteen [VX_MEM_PORTS]; + wire [VX_MEM_ADDR_WIDTH-1:0] vx_mem_req_addr [VX_MEM_PORTS]; + wire [VX_MEM_DATA_WIDTH-1:0] vx_mem_req_data [VX_MEM_PORTS]; + wire [VX_MEM_TAG_WIDTH-1:0] vx_mem_req_tag [VX_MEM_PORTS]; + wire vx_mem_req_ready [VX_MEM_PORTS]; + + wire vx_mem_rsp_valid [VX_MEM_PORTS]; + wire [VX_MEM_DATA_WIDTH-1:0] vx_mem_rsp_data [VX_MEM_PORTS]; + wire [VX_MEM_TAG_WIDTH-1:0] vx_mem_rsp_tag [VX_MEM_PORTS]; + wire vx_mem_rsp_ready [VX_MEM_PORTS]; + + // CMD variables ////////////////////////////////////////////////////////// + + reg [2:0][63:0] cmd_args; + + t_ccip_clAddr cmd_io_addr; + assign cmd_io_addr = t_ccip_clAddr'(cmd_args[0]); + + wire [CCI_ADDR_WIDTH-1:0] cmd_mem_addr = CCI_ADDR_WIDTH'(cmd_args[1]); + wire [CCI_ADDR_WIDTH-1:0] cmd_data_size = CCI_ADDR_WIDTH'(cmd_args[2]); + + wire [VX_DCR_ADDR_WIDTH-1:0] cmd_dcr_addr = VX_DCR_ADDR_WIDTH'(cmd_args[0]); + wire [VX_DCR_DATA_WIDTH-1:0] cmd_dcr_data = VX_DCR_DATA_WIDTH'(cmd_args[1]); + + // MMIO controller //////////////////////////////////////////////////////// + + t_ccip_c0_ReqMmioHdr mmio_req_hdr; + assign mmio_req_hdr = t_ccip_c0_ReqMmioHdr'(cp2af_sRxPort.c0.hdr[$bits(t_ccip_c0_ReqMmioHdr)-1:0]); + `UNUSED_VAR (mmio_req_hdr) + + t_if_ccip_c2_Tx mmio_rsp; + assign af2cp_sTxPort.c2 = mmio_rsp; + +`ifdef SCOPE + + localparam MMIO_SCOPE_READ = `AFU_IMAGE_MMIO_SCOPE_READ; + localparam MMIO_SCOPE_WRITE = `AFU_IMAGE_MMIO_SCOPE_WRITE; + + reg [63:0] cmd_scope_rdata; + reg [63:0] cmd_scope_wdata; + + reg cmd_scope_reading; + reg cmd_scope_writing; + + reg scope_bus_in; + wire scope_bus_out; + + reg [5:0] scope_bus_ctr; + + wire scope_reset = reset; + + always @(posedge clk) begin + if (reset) begin + cmd_scope_reading <= 0; + cmd_scope_writing <= 0; + scope_bus_in <= 0; + end else begin + scope_bus_in <= 0; + if (scope_bus_out) begin + cmd_scope_reading <= 1; + scope_bus_ctr <= 63; + end + if (cp2af_sRxPort.c0.mmioWrValid + && (MMIO_SCOPE_WRITE == mmio_req_hdr.address)) begin + cmd_scope_wdata <= 64'(cp2af_sRxPort.c0.data); + cmd_scope_writing <= 1; + scope_bus_ctr <= 63; + scope_bus_in <= 1; + end + if (cmd_scope_writing) begin + scope_bus_in <= cmd_scope_wdata[scope_bus_ctr]; + scope_bus_ctr <= scope_bus_ctr - 6'd1; + if (scope_bus_ctr == 0) begin + cmd_scope_writing <= 0; + scope_bus_ctr <= 0; + end + end + if (cmd_scope_reading) begin + cmd_scope_rdata <= {cmd_scope_rdata[62:0], scope_bus_out}; + scope_bus_ctr <= scope_bus_ctr - 6'd1; + if (scope_bus_ctr == 0) begin + cmd_scope_reading <= 0; + scope_bus_ctr <= 0; + end + end + end + end + +`endif + + // Console output queue read ////////////////////////////////////////////// + + wire [VX_MEM_PORTS-1:0][COUT_QUEUE_DATAW-1:0] cout_q_dout; + wire [VX_MEM_PORTS-1:0] cout_q_full, cout_q_empty, cout_q_pop; + + reg [MEM_PORTS_WIDTH-1:0] cout_q_id; + + always @(posedge clk) begin + if (reset) begin + cout_q_id <= 0; + end else begin + if (cp2af_sRxPort.c0.mmioRdValid && mmio_req_hdr.address == MMIO_STATUS) begin + cout_q_id <= cout_q_id + 1; + end + end + end + + for (genvar i = 0; i < VX_MEM_PORTS; ++i) begin : g_cout_q_pop + assign cout_q_pop[i] = (cp2af_sRxPort.c0.mmioRdValid && mmio_req_hdr.address == MMIO_STATUS) + && (cout_q_id == i) + && ~cout_q_empty[i]; + end + + wire [COUT_QUEUE_DATAW-1:0] cout_q_dout_s = cout_q_dout[cout_q_id] & {COUT_QUEUE_DATAW{!cout_q_empty[cout_q_id]}}; + wire cout_q_empty_all = & cout_q_empty; + +`ifdef SIMULATION +`ifndef VERILATOR + // disable assertions until full reset + reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr; + initial begin + $assertoff; + end + always @(posedge clk) begin + if (reset) begin + assert_delay_ctr <= '0; + end else begin + assert_delay_ctr <= assert_delay_ctr + $bits(assert_delay_ctr)'(1); + if (assert_delay_ctr == (`RESET_DELAY-1)) begin + $asserton; // enable assertions + end + end + end +`endif +`endif + + // MMIO controller //////////////////////////////////////////////////////// + + // Handle MMIO read requests + always @(posedge clk) begin + if (reset) begin + mmio_rsp.mmioRdValid <= 0; + cout_q_id <= 0; + end else begin + mmio_rsp.mmioRdValid <= cp2af_sRxPort.c0.mmioRdValid; + end + + mmio_rsp.hdr.tid <= mmio_req_hdr.tid; + + if (cp2af_sRxPort.c0.mmioRdValid) begin + case (mmio_req_hdr.address) + // AFU header + 16'h0000: mmio_rsp.data <= { + 4'b0001, // Feature type = AFU + 8'b0, // reserved + 4'b0, // afu minor revision = 0 + 7'b0, // reserved + 1'b1, // end of DFH list = 1 + 24'b0, // next DFH offset = 0 + 4'b0, // afu major revision = 0 + 12'b0 // feature ID = 0 + }; + AFU_ID_L: mmio_rsp.data <= afu_id[63:0]; // afu id low + AFU_ID_H: mmio_rsp.data <= afu_id[127:64]; // afu id hi + 16'h0006: mmio_rsp.data <= 64'h0; // next AFU + 16'h0008: mmio_rsp.data <= 64'h0; // reserved + MMIO_STATUS: begin + mmio_rsp.data <= 64'({cout_q_dout_s, ~cout_q_empty_all, 8'(state)}); + `ifdef DBG_TRACE_AFU + if (state != STATE_WIDTH'(mmio_rsp.data)) begin + `TRACE(2, ("%t: AFU: MMIO_STATUS: addr=0x%0h, state=%0d\n", $time, mmio_req_hdr.address, state)) + end + `endif + end + `ifdef SCOPE + MMIO_SCOPE_READ: begin + mmio_rsp.data <= cmd_scope_rdata; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_SCOPE_READ: data=0x%h\n", $time, cmd_scope_rdata)) + `endif + end + `endif + MMIO_DEV_CAPS: begin + mmio_rsp.data <= dev_caps; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_DEV_CAPS: data=0x%h\n", $time, dev_caps)) + `endif + end + MMIO_ISA_CAPS: begin + mmio_rsp.data <= isa_caps; + `ifdef DBG_TRACE_AFU + if (state != STATE_WIDTH'(mmio_rsp.data)) begin + `TRACE(2, ("%t: AFU: MMIO_ISA_CAPS: data=%0d\n", $time, isa_caps)) + end + `endif + end + default: begin + mmio_rsp.data <= 64'h0; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Unknown MMIO Rd: addr=0x%0h\n", $time, mmio_req_hdr.address)) + `endif + end + endcase + end + end + + // Handle MMIO write requests + always @(posedge clk) begin + if (cp2af_sRxPort.c0.mmioWrValid) begin + case (mmio_req_hdr.address) + MMIO_CMD_ARG0: begin + cmd_args[0] <= 64'(cp2af_sRxPort.c0.data); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_CMD_ARG0: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data))) + `endif + end + MMIO_CMD_ARG1: begin + cmd_args[1] <= 64'(cp2af_sRxPort.c0.data); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_CMD_ARG1: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data))) + `endif + end + MMIO_CMD_ARG2: begin + cmd_args[2] <= 64'(cp2af_sRxPort.c0.data); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_CMD_ARG2: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data))) + `endif + end + MMIO_CMD_TYPE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_CMD_TYPE: data=%0d\n", $time, 64'(cp2af_sRxPort.c0.data))) + `endif + end + `ifdef SCOPE + MMIO_SCOPE_WRITE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: MMIO_SCOPE_WRITE: data=0x%h\n", $time, 64'(cp2af_sRxPort.c0.data))) + `endif + end + `endif + default: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: Unknown MMIO Wr: addr=0x%0h, data=0x%h\n", $time, mmio_req_hdr.address, 64'(cp2af_sRxPort.c0.data))) + `endif + end + endcase + end + end + + // COMMAND FSM //////////////////////////////////////////////////////////// + + wire cmd_mem_rd_done; + reg cmd_mem_wr_done; + + reg [RESET_CTR_WIDTH-1:0] vx_reset_ctr; + reg vx_busy_wait; + reg vx_reset = 1; // asserted at initialization + wire vx_busy; + + wire is_mmio_wr_cmd = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CMD_TYPE == mmio_req_hdr.address); + wire [CMD_TYPE_WIDTH-1:0] cmd_type = is_mmio_wr_cmd ? CMD_TYPE_WIDTH'(cp2af_sRxPort.c0.data) : CMD_TYPE_WIDTH'(CMD_IDLE); + + always @(posedge clk) begin + if (reset) begin + state <= STATE_IDLE; + vx_reset <= 1; + end else begin + case (state) + STATE_IDLE: begin + case (cmd_type) + CMD_MEM_READ: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Goto STATE MEM_READ: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size)) + `endif + state <= STATE_MEM_READ; + end + CMD_MEM_WRITE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Goto STATE MEM_WRITE: ia=0x%0h addr=0x%0h size=%0d\n", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size)) + `endif + state <= STATE_MEM_WRITE; + end + CMD_DCR_WRITE: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Goto STATE DCR_WRITE: addr=0x%0h data=%0d\n", $time, cmd_dcr_addr, cmd_dcr_data)) + `endif + state <= STATE_DCR_WRITE; + end + CMD_RUN: begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Goto STATE RUN\n", $time)) + `endif + state <= STATE_RUN; + vx_reset_ctr <= RESET_CTR_WIDTH'(`RESET_DELAY-1); + vx_reset <= 1; + end + default: begin + state <= state; + end + endcase + end + STATE_MEM_READ: begin + if (cmd_mem_rd_done) begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Goto STATE IDLE\n", $time)) + `endif + end + end + STATE_MEM_WRITE: begin + if (cmd_mem_wr_done) begin + state <= STATE_IDLE; + end + end + STATE_DCR_WRITE: begin + state <= STATE_IDLE; + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Goto STATE IDLE\n", $time)) + `endif + end + STATE_RUN: begin + if (vx_reset) begin + // wait until the reset network is ready + if (vx_reset_ctr == RESET_CTR_WIDTH'(0)) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Begin execution\n", $time)) + `endif + vx_busy_wait <= 1; + vx_reset <= 0; + end + end else begin + if (vx_busy_wait) begin + // wait until processor goes busy + if (vx_busy) begin + vx_busy_wait <= 0; + end + end else begin + // wait until the processor is not busy + if (~vx_busy) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: End execution\n", $time)) + `TRACE(2, ("%t: AFU: Goto STATE IDLE\n", $time)) + `endif + state <= STATE_IDLE; + end + end + end + end + default:; + endcase + + // ensure reset network initialization + if (vx_reset_ctr != RESET_CTR_WIDTH'(0)) begin + vx_reset_ctr <= vx_reset_ctr - RESET_CTR_WIDTH'(1); + end + end + end + + // AVS Controller ///////////////////////////////////////////////////////// + + wire cci_mem_rd_req_valid; + wire cci_mem_wr_req_valid; + wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_dout; + + wire cci_mem_req_valid; + wire cci_mem_req_rw; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_addr; + wire [CCI_DATA_WIDTH-1:0] cci_mem_req_data; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_req_tag; + wire cci_mem_req_ready; + + wire cci_mem_rsp_valid; + wire [CCI_DATA_WIDTH-1:0] cci_mem_rsp_data; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_rsp_tag; + wire cci_mem_rsp_ready; + + // adjust VX mnemory interface to be compatible with CCI + + VX_mem_bus_if #( + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (CCI_VX_ADDR_WIDTH), + .TAG_WIDTH (CCI_VX_TAG_WIDTH) + ) vx_mem_bus_if[VX_MEM_PORTS](); + + wire [VX_MEM_PORTS-1:0] vx_mem_req_valid_qual; + wire [VX_MEM_PORTS-1:0] vx_mem_req_ready_qual; + + for (genvar i = 0; i < VX_MEM_PORTS; ++i) begin : g_vx_mem_adapter + VX_mem_data_adapter #( + .SRC_DATA_WIDTH (VX_MEM_DATA_WIDTH), + .DST_DATA_WIDTH (LMEM_DATA_WIDTH), + .SRC_ADDR_WIDTH (VX_MEM_ADDR_WIDTH), + .DST_ADDR_WIDTH (CCI_VX_ADDR_WIDTH), + .SRC_TAG_WIDTH (VX_MEM_TAG_WIDTH), + .DST_TAG_WIDTH (CCI_VX_TAG_WIDTH), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (2) + ) vx_mem_data_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (vx_mem_req_valid_qual[i]), + .mem_req_addr_in (vx_mem_req_addr[i]), + .mem_req_rw_in (vx_mem_req_rw[i]), + .mem_req_byteen_in (vx_mem_req_byteen[i]), + .mem_req_data_in (vx_mem_req_data[i]), + .mem_req_tag_in (vx_mem_req_tag[i]), + .mem_req_ready_in (vx_mem_req_ready_qual[i]), + + .mem_rsp_valid_in (vx_mem_rsp_valid[i]), + .mem_rsp_data_in (vx_mem_rsp_data[i]), + .mem_rsp_tag_in (vx_mem_rsp_tag[i]), + .mem_rsp_ready_in (vx_mem_rsp_ready[i]), + + .mem_req_valid_out (vx_mem_bus_if[i].req_valid), + .mem_req_addr_out (vx_mem_bus_if[i].req_data.addr), + .mem_req_rw_out (vx_mem_bus_if[i].req_data.rw), + .mem_req_byteen_out (vx_mem_bus_if[i].req_data.byteen), + .mem_req_data_out (vx_mem_bus_if[i].req_data.data), + .mem_req_tag_out (vx_mem_bus_if[i].req_data.tag), + .mem_req_ready_out (vx_mem_bus_if[i].req_ready), + + .mem_rsp_valid_out (vx_mem_bus_if[i].rsp_valid), + .mem_rsp_data_out (vx_mem_bus_if[i].rsp_data.data), + .mem_rsp_tag_out (vx_mem_bus_if[i].rsp_data.tag), + .mem_rsp_ready_out (vx_mem_bus_if[i].rsp_ready) + ); + assign vx_mem_bus_if[i].req_data.flags = '0; + end + + // adjust CCI mnemory interface to be compatible with VX + + VX_mem_bus_if #( + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (CCI_VX_ADDR_WIDTH), + .TAG_WIDTH (CCI_VX_TAG_WIDTH) + ) cci_vx_mem_arb_in_if[2](); + + VX_mem_data_adapter #( + .SRC_DATA_WIDTH (CCI_DATA_WIDTH), + .DST_DATA_WIDTH (LMEM_DATA_WIDTH), + .SRC_ADDR_WIDTH (CCI_ADDR_WIDTH), + .DST_ADDR_WIDTH (CCI_VX_ADDR_WIDTH), + .SRC_TAG_WIDTH (CCI_ADDR_WIDTH), + .DST_TAG_WIDTH (CCI_VX_TAG_WIDTH), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (0) + ) cci_mem_data_adapter ( + .clk (clk), + .reset (reset), + + .mem_req_valid_in (cci_mem_req_valid), + .mem_req_addr_in (cci_mem_req_addr), + .mem_req_rw_in (cci_mem_req_rw), + .mem_req_byteen_in ({CCI_DATA_SIZE{1'b1}}), + .mem_req_data_in (cci_mem_req_data), + .mem_req_tag_in (cci_mem_req_tag), + .mem_req_ready_in (cci_mem_req_ready), + + .mem_rsp_valid_in (cci_mem_rsp_valid), + .mem_rsp_data_in (cci_mem_rsp_data), + .mem_rsp_tag_in (cci_mem_rsp_tag), + .mem_rsp_ready_in (cci_mem_rsp_ready), + + .mem_req_valid_out (cci_vx_mem_arb_in_if[1].req_valid), + .mem_req_addr_out (cci_vx_mem_arb_in_if[1].req_data.addr), + .mem_req_rw_out (cci_vx_mem_arb_in_if[1].req_data.rw), + .mem_req_byteen_out (cci_vx_mem_arb_in_if[1].req_data.byteen), + .mem_req_data_out (cci_vx_mem_arb_in_if[1].req_data.data), + .mem_req_tag_out (cci_vx_mem_arb_in_if[1].req_data.tag), + .mem_req_ready_out (cci_vx_mem_arb_in_if[1].req_ready), + + .mem_rsp_valid_out (cci_vx_mem_arb_in_if[1].rsp_valid), + .mem_rsp_data_out (cci_vx_mem_arb_in_if[1].rsp_data.data), + .mem_rsp_tag_out (cci_vx_mem_arb_in_if[1].rsp_data.tag), + .mem_rsp_ready_out (cci_vx_mem_arb_in_if[1].rsp_ready) + ); + assign cci_vx_mem_arb_in_if[1].req_data.flags = '0; + + // arbitrate between CCI and VX memory interfaces + + `ASSIGN_VX_MEM_BUS_IF(cci_vx_mem_arb_in_if[0], vx_mem_bus_if[0]); + + VX_mem_bus_if #( + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (CCI_VX_ADDR_WIDTH), + .TAG_WIDTH (AVS_TAG_WIDTH) + ) cci_vx_mem_arb_out_if[1](); + + VX_mem_arb #( + .NUM_INPUTS (2), + .NUM_OUTPUTS (1), + .DATA_SIZE (LMEM_DATA_SIZE), + .ADDR_WIDTH (CCI_VX_ADDR_WIDTH), + .TAG_WIDTH (CCI_VX_TAG_WIDTH), + .ARBITER ("P"), // prioritize VX requests + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (0) + ) mem_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (cci_vx_mem_arb_in_if), + .bus_out_if (cci_vx_mem_arb_out_if) + ); + `UNUSED_VAR (cci_vx_mem_arb_out_if[0].req_data.flags) + + // final merged memory interface + wire mem_req_valid [VX_MEM_PORTS]; + wire mem_req_rw [VX_MEM_PORTS]; + wire [CCI_VX_ADDR_WIDTH-1:0] mem_req_addr [VX_MEM_PORTS]; + wire [LMEM_DATA_SIZE-1:0] mem_req_byteen [VX_MEM_PORTS]; + wire [LMEM_DATA_WIDTH-1:0] mem_req_data [VX_MEM_PORTS]; + wire [AVS_TAG_WIDTH-1:0] mem_req_tag [VX_MEM_PORTS]; + wire mem_req_ready [VX_MEM_PORTS]; + + wire mem_rsp_valid [VX_MEM_PORTS]; + wire [LMEM_DATA_WIDTH-1:0] mem_rsp_data [VX_MEM_PORTS]; + wire [AVS_TAG_WIDTH-1:0] mem_rsp_tag [VX_MEM_PORTS]; + wire mem_rsp_ready [VX_MEM_PORTS]; + + for (genvar i = 0; i < VX_MEM_PORTS; ++i) begin : g_mem_bus_if + if (i == 0) begin : g_i0 + // assign port0 to CCI/VX arbiter + assign mem_req_valid[i] = cci_vx_mem_arb_out_if[i].req_valid; + assign mem_req_rw[i] = cci_vx_mem_arb_out_if[i].req_data.rw; + assign mem_req_addr[i] = cci_vx_mem_arb_out_if[i].req_data.addr; + assign mem_req_byteen[i]= cci_vx_mem_arb_out_if[i].req_data.byteen; + assign mem_req_data[i] = cci_vx_mem_arb_out_if[i].req_data.data; + assign mem_req_tag[i] = cci_vx_mem_arb_out_if[i].req_data.tag; + assign cci_vx_mem_arb_out_if[i].req_ready = mem_req_ready[i]; + + assign cci_vx_mem_arb_out_if[i].rsp_valid = mem_rsp_valid[i]; + assign cci_vx_mem_arb_out_if[i].rsp_data.data = mem_rsp_data[i]; + assign cci_vx_mem_arb_out_if[i].rsp_data.tag = mem_rsp_tag[i]; + assign mem_rsp_ready[i] = cci_vx_mem_arb_out_if[i].rsp_ready; + end else begin : g_i + // assign other ports to VX memory bus + assign mem_req_valid[i] = vx_mem_bus_if[i].req_valid; + assign mem_req_rw[i] = vx_mem_bus_if[i].req_data.rw; + assign mem_req_addr[i] = vx_mem_bus_if[i].req_data.addr; + assign mem_req_byteen[i]= vx_mem_bus_if[i].req_data.byteen; + assign mem_req_data[i] = vx_mem_bus_if[i].req_data.data; + assign mem_req_tag[i] = AVS_TAG_WIDTH'(vx_mem_bus_if[i].req_data.tag); + assign vx_mem_bus_if[i].req_ready = mem_req_ready[i]; + + assign vx_mem_bus_if[i].rsp_valid = mem_rsp_valid[i]; + assign vx_mem_bus_if[i].rsp_data.data = mem_rsp_data[i]; + assign vx_mem_bus_if[i].rsp_data.tag = CCI_VX_TAG_WIDTH'(mem_rsp_tag[i]); + assign mem_rsp_ready[i] = vx_mem_bus_if[i].rsp_ready; + end + end + + // convert merged memory interface to AVS + VX_avs_adapter #( + .DATA_WIDTH (LMEM_DATA_WIDTH), + .ADDR_WIDTH_IN (CCI_VX_ADDR_WIDTH), + .ADDR_WIDTH_OUT(LMEM_ADDR_WIDTH), + .BURST_WIDTH (LMEM_BURST_CTRW), + .NUM_PORTS_IN (VX_MEM_PORTS), + .NUM_BANKS_OUT (NUM_LOCAL_MEM_BANKS), + .TAG_WIDTH (AVS_TAG_WIDTH), + .RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE), + .INTERLEAVE (`PLATFORM_MEMORY_INTERLEAVE), + .REQ_OUT_BUF (2), // always needed due to CCI/VX arbiter + .RSP_OUT_BUF ((VX_MEM_PORTS > 1 || NUM_LOCAL_MEM_BANKS > 1) ? 2 : 0) + ) avs_adapter ( + .clk (clk), + .reset (reset), + + // Memory request + .mem_req_valid (mem_req_valid), + .mem_req_rw (mem_req_rw), + .mem_req_byteen (mem_req_byteen), + .mem_req_addr (mem_req_addr), + .mem_req_data (mem_req_data), + .mem_req_tag (mem_req_tag), + .mem_req_ready (mem_req_ready), + + // Memory response + .mem_rsp_valid (mem_rsp_valid), + .mem_rsp_data (mem_rsp_data), + .mem_rsp_tag (mem_rsp_tag), + .mem_rsp_ready (mem_rsp_ready), + + // AVS bus + .avs_writedata (avs_writedata), + .avs_readdata (avs_readdata), + .avs_address (avs_address), + .avs_waitrequest (avs_waitrequest), + .avs_write (avs_write), + .avs_read (avs_read), + .avs_byteenable (avs_byteenable), + .avs_burstcount (avs_burstcount), + .avs_readdatavalid(avs_readdatavalid) + ); + + // CCI-P Read Request ///////////////////////////////////////////////////// + + reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_ctr; + wire [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr; + reg [CCI_ADDR_WIDTH-1:0] cci_mem_wr_req_addr_base; + + wire cci_rd_req_fire; + t_ccip_clAddr cci_rd_req_addr; + reg cci_rd_req_valid, cci_rd_req_wait; + reg [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr; + wire [CCI_ADDR_WIDTH-1:0] cci_rd_req_ctr_next; + wire [CCI_RD_QUEUE_TAGW-1:0] cci_rd_req_tag; + + wire [CCI_RD_QUEUE_TAGW-1:0] cci_rd_rsp_tag; + reg [CCI_RD_QUEUE_TAGW-1:0] cci_rd_rsp_ctr; + + wire cci_rdq_push, cci_rdq_pop; + wire [CCI_RD_QUEUE_DATAW-1:0] cci_rdq_din; + wire cci_rdq_empty; + + always @(*) begin + af2cp_sTxPort.c0.valid = cci_rd_req_fire; + af2cp_sTxPort.c0.hdr = t_ccip_c0_ReqMemHdr'(0); + af2cp_sTxPort.c0.hdr.address = cci_rd_req_addr; + af2cp_sTxPort.c0.hdr.mdata = t_ccip_mdata'(cci_rd_req_tag); + end + + wire cci_mem_wr_req_fire = cci_mem_wr_req_valid && cci_mem_req_ready; + + wire cci_rd_rsp_fire = cp2af_sRxPort.c0.rspValid + && (cp2af_sRxPort.c0.hdr.resp_type == eRSP_RDLINE); + + assign cci_rd_req_tag = CCI_RD_QUEUE_TAGW'(cci_rd_req_ctr); + assign cci_rd_rsp_tag = CCI_RD_QUEUE_TAGW'(cp2af_sRxPort.c0.hdr.mdata); + + assign cci_rdq_push = cci_rd_rsp_fire; + assign cci_rdq_pop = cci_mem_wr_req_fire; + assign cci_rdq_din = {cp2af_sRxPort.c0.data, cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(cci_rd_rsp_tag)}; + + wire [`CLOG2(CCI_RD_QUEUE_SIZE+1)-1:0] cci_pending_reads; + wire cci_pending_reads_full; + VX_pending_size #( + .SIZE (CCI_RD_QUEUE_SIZE) + ) cci_rd_pending_size ( + .clk (clk), + .reset (reset), + .incr (cci_rd_req_fire), + .decr (cci_rdq_pop), + `UNUSED_PIN (empty), + `UNUSED_PIN (alm_empty), + .full (cci_pending_reads_full), + `UNUSED_PIN (alm_full), + .size (cci_pending_reads) + ); + + `UNUSED_VAR (cci_pending_reads) + + assign cci_rd_req_ctr_next = cci_rd_req_ctr + CCI_ADDR_WIDTH'(cci_rd_req_fire ? 1 : 0); + + assign cci_rd_req_fire = cci_rd_req_valid && !(cci_rd_req_wait || cci_pending_reads_full); + + assign cci_mem_wr_req_valid = !cci_rdq_empty; + + assign cci_mem_wr_req_addr = cci_rdq_dout[CCI_ADDR_WIDTH-1:0]; + + // Send read requests to CCI + always @(posedge clk) begin + if (reset) begin + cci_rd_req_valid <= 0; + cci_rd_req_wait <= 0; + end else begin + if ((STATE_IDLE == state) + && (CMD_MEM_WRITE == cmd_type)) begin + cci_rd_req_valid <= (cmd_data_size != 0); + cci_rd_req_wait <= 0; + end + + cci_rd_req_valid <= (STATE_MEM_WRITE == state) + && (cci_rd_req_ctr_next != cmd_data_size) + && !cp2af_sRxPort.c0TxAlmFull; + + if (cci_rd_req_fire + && (cci_rd_req_tag == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1))) begin + cci_rd_req_wait <= 1; // end current request batch + end + + if (cci_rd_rsp_fire + && (cci_rd_rsp_ctr == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1))) begin + cci_rd_req_wait <= 0; // begin new request batch + end + end + + if ((STATE_IDLE == state) + && (CMD_MEM_WRITE == cmd_type)) begin + cci_rd_req_addr <= cmd_io_addr; + cci_rd_req_ctr <= '0; + cci_rd_rsp_ctr <= '0; + cci_mem_wr_req_ctr <= '0; + cci_mem_wr_req_addr_base <= cmd_mem_addr; + cmd_mem_wr_done <= 0; + end + + if (cci_rd_req_fire) begin + cci_rd_req_addr <= cci_rd_req_addr + 1; + cci_rd_req_ctr <= cci_rd_req_ctr + $bits(cci_rd_req_ctr)'(1); + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: CCI Rd Req: addr=0x%0h, tag=0x%0h, rem=%0d, pending=%0d\n", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr - 1), cci_pending_reads)) + `endif + end + + if (cci_rd_rsp_fire) begin + cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_QUEUE_TAGW'(1); + if (CCI_RD_QUEUE_TAGW'(cci_rd_rsp_ctr) == CCI_RD_QUEUE_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin + cci_mem_wr_req_addr_base <= cci_mem_wr_req_addr_base + CCI_ADDR_WIDTH'(CCI_RD_WINDOW_SIZE); + end + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: CCI Rd Rsp: idx=%0d, ctr=%0d, data=0x%h\n", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, cp2af_sRxPort.c0.data)) + `endif + end + + if (cci_rdq_pop) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: CCI Rd Queue Pop: pending=%0d\n", $time, cci_pending_reads)) + `endif + end + + if (cci_mem_wr_req_fire) begin + cci_mem_wr_req_ctr <= cci_mem_wr_req_ctr + CCI_ADDR_WIDTH'(1); + if (cci_mem_wr_req_ctr == (cmd_data_size-1)) begin + cmd_mem_wr_done <= 1; + end + end + end + + VX_fifo_queue #( + .DATAW (CCI_RD_QUEUE_DATAW), + .DEPTH (CCI_RD_QUEUE_SIZE) + ) cci_rd_req_queue ( + .clk (clk), + .reset (reset), + .push (cci_rdq_push), + .pop (cci_rdq_pop), + .data_in (cci_rdq_din), + .data_out (cci_rdq_dout), + .empty (cci_rdq_empty), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + +`DEBUG_BLOCK( + reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask; + always @(posedge clk) begin + if (reset) begin + dbg_cci_rd_rsp_mask <= '0; + end else begin + if (cci_rd_rsp_fire) begin + if (cci_rd_rsp_ctr == 0) begin + dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag); + end else begin + assert(!dbg_cci_rd_rsp_mask[cci_rd_rsp_tag]); + dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1; + end + end + end + end +) + + // CCI-P Write Request //////////////////////////////////////////////////// + + reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_ctr; + reg [CCI_ADDR_WIDTH-1:0] cci_mem_rd_req_addr; + reg cci_mem_rd_req_done; + + reg [CCI_ADDR_WIDTH-1:0] cci_wr_req_ctr; + reg cci_wr_req_fire; + t_ccip_clAddr cci_wr_req_addr; + t_ccip_clData cci_wr_req_data; + reg cci_wr_req_done; + + always @(*) begin + af2cp_sTxPort.c1.valid = cci_wr_req_fire; + af2cp_sTxPort.c1.hdr = t_ccip_c1_ReqMemHdr'(0); + af2cp_sTxPort.c1.hdr.sop = 1; // single line write mode + af2cp_sTxPort.c1.hdr.address = cci_wr_req_addr; + af2cp_sTxPort.c1.data = cci_wr_req_data; + end + + wire cci_mem_rd_req_fire = cci_mem_rd_req_valid && cci_mem_req_ready; + wire cci_mem_rd_rsp_fire = cci_mem_rsp_valid && cci_mem_rsp_ready; + + wire cci_wr_rsp_fire = (STATE_MEM_READ == state) + && cp2af_sRxPort.c1.rspValid + && (cp2af_sRxPort.c1.hdr.resp_type == eRSP_WRLINE); + + wire [`CLOG2(CCI_RW_PENDING_SIZE+1)-1:0] cci_pending_writes; + wire cci_pending_writes_empty; + wire cci_pending_writes_full; + + VX_pending_size #( + .SIZE (CCI_RW_PENDING_SIZE) + ) cci_wr_pending_size ( + .clk (clk), + .reset (reset), + .incr (cci_mem_rd_rsp_fire), + .decr (cci_wr_rsp_fire), + .empty (cci_pending_writes_empty), + `UNUSED_PIN (alm_empty), + .full (cci_pending_writes_full), + `UNUSED_PIN (alm_full), + .size (cci_pending_writes) + ); + + `UNUSED_VAR (cci_pending_writes) + + assign cci_mem_rd_req_valid = (STATE_MEM_READ == state) && ~cci_mem_rd_req_done; + + assign cci_mem_rsp_ready = ~cp2af_sRxPort.c1TxAlmFull && ~cci_pending_writes_full; + + assign cmd_mem_rd_done = cci_wr_req_done && cci_pending_writes_empty; + + // Send write requests to CCI + always @(posedge clk) begin + if (reset) begin + cci_wr_req_fire <= 0; + end else begin + cci_wr_req_fire <= cci_mem_rd_rsp_fire; + end + + if ((STATE_IDLE == state) + && (CMD_MEM_READ == cmd_type)) begin + cci_mem_rd_req_ctr <= '0; + cci_mem_rd_req_addr <= cmd_mem_addr; + cci_mem_rd_req_done <= 0; + cci_wr_req_ctr <= cmd_data_size; + cci_wr_req_done <= 0; + end + + if (cci_mem_rd_req_fire) begin + cci_mem_rd_req_addr <= cci_mem_rd_req_addr + CCI_ADDR_WIDTH'(1); + cci_mem_rd_req_ctr <= cci_mem_rd_req_ctr + CCI_ADDR_WIDTH'(1); + if (cci_mem_rd_req_ctr == (cmd_data_size-1)) begin + cci_mem_rd_req_done <= 1; + end + end + + cci_wr_req_addr <= cmd_io_addr + t_ccip_clAddr'(cci_mem_rsp_tag); + cci_wr_req_data <= t_ccip_clData'(cci_mem_rsp_data); + + if (cci_wr_req_fire) begin + `ASSERT(cci_wr_req_ctr != 0, ("runtime error")); + cci_wr_req_ctr <= cci_wr_req_ctr - CCI_ADDR_WIDTH'(1); + if (cci_wr_req_ctr == CCI_ADDR_WIDTH'(1)) begin + cci_wr_req_done <= 1; + end + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: CCI Wr Req: addr=0x%0h, rem=%0d, pending=%0d, data=0x%h\n", $time, cci_wr_req_addr, (cci_wr_req_ctr - 1), cci_pending_writes, af2cp_sTxPort.c1.data)) + `endif + end + + if (cci_wr_rsp_fire) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: CCI Wr Rsp: pending=%0d\n", $time, cci_pending_writes)) + `endif + end + end + + //-- + + assign cci_mem_req_rw = state[0]; + `STATIC_ASSERT(STATE_MEM_WRITE == 1, ("invalid value")); // 01 + `STATIC_ASSERT(STATE_MEM_READ == 2, ("invalid value")); // 10 + + assign cci_mem_req_valid = cci_mem_req_rw ? cci_mem_wr_req_valid : cci_mem_rd_req_valid; + assign cci_mem_req_addr = cci_mem_req_rw ? cci_mem_wr_req_addr : cci_mem_rd_req_addr; + assign cci_mem_req_data = cci_rdq_dout[CCI_RD_QUEUE_DATAW-1:CCI_ADDR_WIDTH]; + assign cci_mem_req_tag = cci_mem_req_rw ? cci_mem_wr_req_ctr : cci_mem_rd_req_ctr; + + // Vortex ///////////////////////////////////////////////////////////////// + + wire vx_dcr_wr_valid = (STATE_DCR_WRITE == state); + wire [VX_DCR_ADDR_WIDTH-1:0] vx_dcr_wr_addr = cmd_dcr_addr; + wire [VX_DCR_DATA_WIDTH-1:0] vx_dcr_wr_data = cmd_dcr_data; + + `SCOPE_IO_SWITCH (2); + + Vortex vortex ( + `SCOPE_IO_BIND (1) + + .clk (clk), + .reset (vx_reset), + + // Memory request + .mem_req_valid (vx_mem_req_valid), + .mem_req_rw (vx_mem_req_rw), + .mem_req_byteen (vx_mem_req_byteen), + .mem_req_addr (vx_mem_req_addr), + .mem_req_data (vx_mem_req_data), + .mem_req_tag (vx_mem_req_tag), + .mem_req_ready (vx_mem_req_ready), + + // Memory response + .mem_rsp_valid (vx_mem_rsp_valid), + .mem_rsp_data (vx_mem_rsp_data), + .mem_rsp_tag (vx_mem_rsp_tag), + .mem_rsp_ready (vx_mem_rsp_ready), + + // DCR write request + .dcr_wr_valid (vx_dcr_wr_valid), + .dcr_wr_addr (vx_dcr_wr_addr), + .dcr_wr_data (vx_dcr_wr_data), + + // Status + .busy (vx_busy) + ); + + // COUT HANDLING ////////////////////////////////////////////////////////// + + for (genvar i = 0; i < VX_MEM_PORTS; ++i) begin : g_cout + + wire [COUT_TID_WIDTH-1:0] cout_tid; + + VX_onehot_encoder #( + .N (VX_MEM_BYTEEN_WIDTH) + ) cout_tid_enc ( + .data_in (vx_mem_req_byteen[i]), + .data_out (cout_tid), + `UNUSED_PIN (valid_out) + ); + + wire [VX_MEM_BYTEEN_WIDTH-1:0][7:0] vx_mem_req_data_m = vx_mem_req_data[i]; + + wire [7:0] cout_char = vx_mem_req_data_m[cout_tid]; + + wire [VX_MEM_ADDR_WIDTH-1:0] io_cout_addr_b = VX_MEM_ADDR_WIDTH'(`IO_COUT_ADDR >> `CLOG2(`MEM_BLOCK_SIZE)); + + wire vx_mem_is_cout = (vx_mem_req_addr[i] == io_cout_addr_b); + + assign vx_mem_req_valid_qual[i] = vx_mem_req_valid[i] && ~vx_mem_is_cout; + assign vx_mem_req_ready[i] = vx_mem_is_cout ? ~cout_q_full[i] : vx_mem_req_ready_qual[i]; + + wire cout_q_push = vx_mem_req_valid[i] && vx_mem_is_cout && ~cout_q_full[i]; + + VX_fifo_queue #( + .DATAW (COUT_QUEUE_DATAW), + .DEPTH (COUT_QUEUE_SIZE) + ) cout_queue ( + .clk (clk), + .reset (reset), + .push (cout_q_push), + .pop (cout_q_pop[i]), + .data_in ({cout_tid, cout_char}), + .data_out (cout_q_dout[i]), + .empty (cout_q_empty[i]), + .full (cout_q_full[i]), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + end + + // SCOPE ////////////////////////////////////////////////////////////////// + +`ifdef DBG_SCOPE_AFU + reg [STATE_WIDTH-1:0] state_prev; + always @(posedge clk) begin + state_prev <= state; + end + wire state_changed = (state != state_prev); + wire vx_mem_req_fire = vx_mem_req_valid[0] && vx_mem_req_ready[0]; + wire vx_mem_rsp_fire = vx_mem_rsp_valid[0] && vx_mem_rsp_ready[0]; + wire avs_req_fire = (avs_write[0] || avs_read[0]) && ~avs_waitrequest[0]; + wire reset_negedge; + `NEG_EDGE (reset_negedge, reset); + `SCOPE_TAP (0, 0, { + vx_reset, + vx_busy, + vx_mem_req_valid[0], + vx_mem_req_ready[0], + vx_mem_rsp_valid[0], + vx_mem_rsp_ready[0], + avs_read[0], + avs_write[0], + avs_waitrequest[0], + cp2af_sRxPort.c0.rspValid, + cp2af_sRxPort.c1.rspValid, + af2cp_sTxPort.c0.valid, + af2cp_sTxPort.c1.valid, + cp2af_sRxPort.c0TxAlmFull, + cp2af_sRxPort.c1TxAlmFull + },{ + state_changed, + vx_dcr_wr_valid, // ack-free + avs_readdatavalid[0], // ack-free + cp2af_sRxPort.c0.mmioRdValid, // ack-free + cp2af_sRxPort.c0.mmioWrValid, // ack-free + af2cp_sTxPort.c2.mmioRdValid, // ack-free + cp2af_sRxPort.c0.rspValid, // ack-free + cp2af_sRxPort.c1.rspValid, // ack-free + cci_rd_req_fire, + cci_wr_req_fire, + avs_req_fire, + vx_mem_req_fire, + vx_mem_rsp_fire + },{ + cmd_type, + state, + vx_mem_req_rw[0], + vx_mem_req_byteen[0], + vx_mem_req_addr[0], + vx_mem_req_data[0], + vx_mem_req_tag[0], + vx_mem_rsp_data[0], + vx_mem_rsp_tag[0], + vx_dcr_wr_addr, + vx_dcr_wr_data, + mmio_req_hdr.address, + cp2af_sRxPort.c0.hdr.mdata, + af2cp_sTxPort.c0.hdr.address, + af2cp_sTxPort.c0.hdr.mdata, + af2cp_sTxPort.c1.hdr.address, + avs_address[0], + avs_byteenable[0], + avs_burstcount[0], + cci_mem_rd_req_ctr, + cci_mem_wr_req_ctr, + cci_rd_req_ctr, + cci_rd_rsp_ctr, + cci_wr_req_ctr + }, + reset_negedge, 1'b0, 4096 + ); +`else + `SCOPE_IO_UNUSED(0) +`endif + + /////////////////////////////////////////////////////////////////////////// + +`ifdef DBG_TRACE_AFU + always @(posedge clk) begin + for (integer i = 0; i < NUM_LOCAL_MEM_BANKS; ++i) begin + if (avs_write[i] && ~avs_waitrequest[i]) begin + `TRACE(2, ("%t: AVS Wr Req[%0d]: addr=0x%0h, byteen=0x%0h, burst=0x%0h, data=0x%h\n", $time, i, `TO_FULL_ADDR(avs_address[i]), avs_byteenable[i], avs_burstcount[i], avs_writedata[i])) + end + if (avs_read[i] && ~avs_waitrequest[i]) begin + `TRACE(2, ("%t: AVS Rd Req[%0d]: addr=0x%0h, byteen=0x%0h, burst=0x%0h\n", $time, i, `TO_FULL_ADDR(avs_address[i]), avs_byteenable[i], avs_burstcount[i])) + end + if (avs_readdatavalid[i]) begin + `TRACE(2, ("%t: AVS Rd Rsp[%0d]: data=0x%h\n", $time, i, avs_readdata[i])) + end + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/afu/opae/vortex_afu.vh b/designs/src/vortex/rtl/afu/opae/vortex_afu.vh new file mode 100644 index 0000000..31f09ae --- /dev/null +++ b/designs/src/vortex/rtl/afu/opae/vortex_afu.vh @@ -0,0 +1,39 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VORTEX_AFU_VH +`define VORTEX_AFU_VH + +`define AFU_ACCEL_NAME "vortex_afu" +`define AFU_ACCEL_UUID 128'h35F9452B_25C2_434C_93D5_6F8C60DB361C + +`define AFU_IMAGE_CMD_MEM_READ 1 +`define AFU_IMAGE_CMD_MEM_WRITE 2 +`define AFU_IMAGE_CMD_RUN 3 +`define AFU_IMAGE_CMD_DCR_WRITE 4 +`define AFU_IMAGE_CMD_MAX_VALUE 4 + +`define AFU_IMAGE_MMIO_CMD_TYPE 10 +`define AFU_IMAGE_MMIO_CMD_ARG0 12 +`define AFU_IMAGE_MMIO_CMD_ARG1 14 +`define AFU_IMAGE_MMIO_CMD_ARG2 16 +`define AFU_IMAGE_MMIO_STATUS 18 +`define AFU_IMAGE_MMIO_SCOPE_READ 20 +`define AFU_IMAGE_MMIO_SCOPE_WRITE 22 +`define AFU_IMAGE_MMIO_DEV_CAPS 24 +`define AFU_IMAGE_MMIO_ISA_CAPS 26 + +`define AFU_IMAGE_POWER 0 +`define AFU_TOP_IFC "ccip_std_afu_avalon_mm" + +`endif // VORTEX_AFU_VH diff --git a/designs/src/vortex/rtl/afu/xrt/VX_afu_ctrl.sv b/designs/src/vortex/rtl/afu/xrt/VX_afu_ctrl.sv new file mode 100644 index 0000000..82e2cec --- /dev/null +++ b/designs/src/vortex/rtl/afu/xrt/VX_afu_ctrl.sv @@ -0,0 +1,443 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "vortex_afu.vh" + +module VX_afu_ctrl import VX_gpu_pkg::*; #( + parameter S_AXI_ADDR_WIDTH = 8, + parameter S_AXI_DATA_WIDTH = 32 +) ( + // axi4 lite slave signals + input wire clk, + input wire reset, + + input wire s_axi_awvalid, + input wire [S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + output wire s_axi_awready, + + input wire s_axi_wvalid, + input wire [S_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [S_AXI_DATA_WIDTH/8-1:0]s_axi_wstrb, + output wire s_axi_wready, + + output wire s_axi_bvalid, + output wire [1:0] s_axi_bresp, + input wire s_axi_bready, + + input wire s_axi_arvalid, + input wire [S_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + output wire s_axi_arready, + + output wire s_axi_rvalid, + output wire [S_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [1:0] s_axi_rresp, + input wire s_axi_rready, + + output wire ap_reset, + output wire ap_start, + input wire ap_done, + input wire ap_ready, + input wire ap_idle, + output wire interrupt, + + output wire ap_ctrl_read, + +`ifdef SCOPE + input wire scope_bus_in, + output wire scope_bus_out, +`endif + + output wire dcr_wr_valid, + output wire [VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr, + output wire [VX_DCR_DATA_WIDTH-1:0] dcr_wr_data +); + + // Address Info + // 0x00 : Control signals + // bit 0 - ap_start (Read/Write/COH) + // bit 1 - ap_done (Read/COR) + // bit 2 - ap_idle (Read) + // bit 3 - ap_ready (Read) + // bit 4 - ap_reset (Write) + // bit 7 - auto_restart (Read/Write) + // others - reserved + // 0x04 : Global Interrupt Enable Register + // bit 0 - Global Interrupt Enable (Read/Write) + // others - reserved + // 0x08 : IP Interrupt Enable Register (Read/Write) + // bit 0 - Channel 0 (ap_done) + // bit 1 - Channel 1 (ap_ready) + // others - reserved + // 0x0c : IP Interrupt Status Register (Read/TOW) + // bit 0 - Channel 0 (ap_done) + // bit 1 - Channel 1 (ap_ready) + // others - reserved + // 0x10 : Low 32-bit Data signal of DEV_CAPS + // 0x14 : High 32-bit Data signal of DEV_CAPS + // 0x18 : Control signal of DEV_CAPS + // 0x1C : Low 32-bit Data signal of ISA_CAPS + // 0x20 : High 32-bit Data signal of ISA_CAPS + // 0x24 : Control signal of ISA_CAPS + // 0x28 : Low 32-bit Data signal of DCR + // 0x2C : High 32-bit Data signal of DCR + // 0x30 : Control signal of DCR + // 0x34 : Low 32-bit Data signal of SCP + // 0x38 : High 32-bit Data signal of SCP + // 0x3C : Control signal of SCP + // 0x40 : Low 32-bit Data signal of MEM + // 0x44 : High 32-bit Data signal of MEM + // 0x48 : Control signal of MEM + // (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + + // Parameters + localparam + ADDR_AP_CTRL = 8'h00, + ADDR_GIE = 8'h04, + ADDR_IER = 8'h08, + ADDR_ISR = 8'h0C, + + ADDR_DEV_0 = 8'h10, + ADDR_DEV_1 = 8'h14, + + ADDR_ISA_0 = 8'h18, + ADDR_ISA_1 = 8'h1C, + + ADDR_DCR_0 = 8'h20, + ADDR_DCR_1 = 8'h24, + + `ifdef SCOPE + ADDR_SCP_0 = 8'h28, + ADDR_SCP_1 = 8'h2C, + `endif + + ADDR_BITS = 8; + + localparam + WSTATE_ADDR = 2'd0, + WSTATE_DATA = 2'd1, + WSTATE_RESP = 2'd2, + WSTATE_WIDTH = 2; + + localparam + RSTATE_ADDR = 2'd0, + RSTATE_DATA = 2'd1, + RSTATE_RESP = 2'd2, + RSTATE_WIDTH = 2; + + localparam MEMORY_BANK_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH - `CLOG2(`PLATFORM_MEMORY_NUM_BANKS); + + // device caps + wire [63:0] dev_caps = {8'b0, + 5'(MEMORY_BANK_ADDR_WIDTH-20), + 3'(`CLOG2(`PLATFORM_MEMORY_NUM_BANKS)), + 8'(`LMEM_ENABLED ? `LMEM_LOG_SIZE : 0), + 16'(`NUM_CORES * `NUM_CLUSTERS), + 8'(`NUM_WARPS), + 8'(`NUM_THREADS), + 8'(`IMPLEMENTATION_ID)}; + + wire [63:0] isa_caps = {32'(`MISA_EXT), + 2'(`CLOG2(`XLEN)-4), + 30'(`MISA_STD)}; + + reg [WSTATE_WIDTH-1:0] wstate; + reg [ADDR_BITS-1:0] waddr; + wire [31:0] wmask; + wire s_axi_aw_fire; + wire s_axi_w_fire; + wire s_axi_b_fire; + + logic [RSTATE_WIDTH-1:0] rstate; + reg [31:0] rdata; + reg [ADDR_BITS-1:0] raddr; + wire s_axi_ar_fire; + wire s_axi_r_fire; + + reg ap_reset_r; + reg ap_start_r; + reg auto_restart_r; + reg gie_r; + reg [1:0] ier_r; + reg [1:0] isr_r; + reg [31:0] dcra_r; + reg [31:0] dcrv_r; + reg dcr_wr_valid_r; + + logic wready_stall; + logic rvalid_stall; + +`ifdef SCOPE + + reg [63:0] scope_bus_wdata, scope_bus_rdata; + reg [5:0] scope_bus_ctr; + + reg cmd_scope_writing, cmd_scope_reading; + reg scope_bus_out_r; + reg scope_rdata_valid; + + reg is_scope_waddr, is_scope_raddr; + + always @(posedge clk) begin + if (reset) begin + cmd_scope_reading <= 0; + cmd_scope_writing <= 0; + scope_bus_ctr <= '0; + scope_bus_out_r <= 0; + is_scope_waddr <= 0; + is_scope_raddr <= 0; + scope_bus_rdata <= '0; + scope_rdata_valid <= 0; + end else begin + scope_bus_out_r <= 0; + if (s_axi_aw_fire) begin + is_scope_waddr <= (s_axi_awaddr[ADDR_BITS-1:0] == ADDR_SCP_0) + || (s_axi_awaddr[ADDR_BITS-1:0] == ADDR_SCP_1); + end + if (s_axi_ar_fire) begin + is_scope_raddr <= (s_axi_araddr[ADDR_BITS-1:0] == ADDR_SCP_0) + || (s_axi_araddr[ADDR_BITS-1:0] == ADDR_SCP_1); + end + if (s_axi_w_fire && waddr == ADDR_SCP_0) begin + scope_bus_wdata[31:0] <= (s_axi_wdata & wmask) | (scope_bus_wdata[31:0] & ~wmask); + end + if (s_axi_w_fire && waddr == ADDR_SCP_1) begin + scope_bus_wdata[63:32] <= (s_axi_wdata & wmask) | (scope_bus_wdata[63:32] & ~wmask); + cmd_scope_writing <= 1; + scope_rdata_valid <= 0; + scope_bus_out_r <= 1; + scope_bus_ctr <= 63; + end + if (scope_bus_in) begin + cmd_scope_reading <= 1; + scope_bus_rdata <= '0; + scope_bus_ctr <= 63; + end + if (cmd_scope_reading) begin + scope_bus_rdata <= {scope_bus_rdata[62:0], scope_bus_in}; + scope_bus_ctr <= scope_bus_ctr - 1; + if (scope_bus_ctr == 0) begin + cmd_scope_reading <= 0; + scope_rdata_valid <= 1; + scope_bus_ctr <= 0; + end + end + if (cmd_scope_writing) begin + scope_bus_out_r <= scope_bus_wdata[scope_bus_ctr]; + scope_bus_ctr <= scope_bus_ctr - 1; + if (scope_bus_ctr == 0) begin + cmd_scope_writing <= 0; + scope_bus_ctr <= 0; + end + end + end + end + + assign scope_bus_out = scope_bus_out_r; + + assign wready_stall = is_scope_waddr && cmd_scope_writing; + assign rvalid_stall = is_scope_raddr && ~scope_rdata_valid; + +`else + + assign wready_stall = 0; + assign rvalid_stall = 0; + +`endif + + // AXI Write Request + assign s_axi_awready = (wstate == WSTATE_ADDR); + assign s_axi_wready = (wstate == WSTATE_DATA) && ~wready_stall; + + // AXI Write Response + assign s_axi_bvalid = (wstate == WSTATE_RESP); + assign s_axi_bresp = 2'b00; // OKAY + + for (genvar i = 0; i < 4; ++i) begin : g_wmask + assign wmask[8 * i +: 8] = {8{s_axi_wstrb[i]}}; + end + + assign s_axi_aw_fire = s_axi_awvalid && s_axi_awready; + assign s_axi_w_fire = s_axi_wvalid && s_axi_wready; + assign s_axi_b_fire = s_axi_bvalid && s_axi_bready; + + // wstate + always @(posedge clk) begin + if (reset) begin + wstate <= WSTATE_ADDR; + end else begin + case (wstate) + WSTATE_ADDR: wstate <= s_axi_aw_fire ? WSTATE_DATA : WSTATE_ADDR; + WSTATE_DATA: wstate <= s_axi_w_fire ? WSTATE_RESP : WSTATE_DATA; + WSTATE_RESP: wstate <= s_axi_b_fire ? WSTATE_ADDR : WSTATE_RESP; + default: wstate <= WSTATE_ADDR; + endcase + end + end + + // waddr + always @(posedge clk) begin + if (s_axi_aw_fire) begin + waddr <= s_axi_awaddr[ADDR_BITS-1:0]; + end + end + + // wdata + always @(posedge clk) begin + if (reset) begin + ap_start_r <= 0; + ap_reset_r <= 0; + auto_restart_r <= 0; + + gie_r <= 0; + ier_r <= '0; + isr_r <= '0; + + dcra_r <= '0; + dcrv_r <= '0; + dcr_wr_valid_r <= 0; + end else begin + dcr_wr_valid_r <= 0; + ap_reset_r <= 0; + + if (ap_ready) + ap_start_r <= auto_restart_r; + + if (s_axi_w_fire) begin + case (waddr) + ADDR_AP_CTRL: begin + if (s_axi_wstrb[0]) begin + if (s_axi_wdata[0]) + ap_start_r <= 1; + if (s_axi_wdata[4]) + ap_reset_r <= 1; + if (s_axi_wdata[7]) + auto_restart_r <= 1; + end + end + ADDR_GIE: begin + if (s_axi_wstrb[0]) + gie_r <= s_axi_wdata[0]; + end + ADDR_IER: begin + if (s_axi_wstrb[0]) + ier_r <= s_axi_wdata[1:0]; + end + ADDR_ISR: begin + if (s_axi_wstrb[0]) + isr_r <= isr_r ^ s_axi_wdata[1:0]; + end + ADDR_DCR_0: begin + dcra_r <= (s_axi_wdata & wmask) | (dcra_r & ~wmask); + end + ADDR_DCR_1: begin + dcrv_r <= (s_axi_wdata & wmask) | (dcrv_r & ~wmask); + dcr_wr_valid_r <= 1; + end + default:; + endcase + + if (ier_r[0] & ap_done) + isr_r[0] <= 1'b1; + if (ier_r[1] & ap_ready) + isr_r[1] <= 1'b1; + end + end + end + + // AXI Read Request + assign s_axi_arready = (rstate == RSTATE_ADDR); + + // AXI Read Response + assign s_axi_rvalid = (rstate == RSTATE_RESP); + assign s_axi_rdata = rdata; + assign s_axi_rresp = 2'b00; // OKAY + + assign s_axi_ar_fire = s_axi_arvalid && s_axi_arready; + assign s_axi_r_fire = s_axi_rvalid && s_axi_rready; + + // rstate + always @(posedge clk) begin + if (reset) begin + rstate <= RSTATE_ADDR; + end else begin + case (rstate) + RSTATE_ADDR: rstate <= s_axi_ar_fire ? RSTATE_DATA : RSTATE_ADDR; + RSTATE_DATA: rstate <= rvalid_stall ? RSTATE_DATA : RSTATE_RESP; + RSTATE_RESP: rstate <= s_axi_r_fire ? RSTATE_ADDR : RSTATE_RESP; + default: rstate <= RSTATE_ADDR; + endcase + end + end + + // raddr + always @(posedge clk) begin + if (s_axi_ar_fire) begin + raddr <= s_axi_araddr[ADDR_BITS-1:0]; + end + end + + // rdata + always @(posedge clk) begin + rdata <= '0; + case (raddr) + ADDR_AP_CTRL: begin + rdata[0] <= ap_start_r; + rdata[1] <= ap_done; + rdata[2] <= ap_idle; + rdata[3] <= ap_ready; + rdata[7] <= auto_restart_r; + end + ADDR_GIE: begin + rdata <= 32'(gie_r); + end + ADDR_IER: begin + rdata <= 32'(ier_r); + end + ADDR_ISR: begin + rdata <= 32'(isr_r); + end + ADDR_DEV_0: begin + rdata <= dev_caps[31:0]; + end + ADDR_DEV_1: begin + rdata <= dev_caps[63:32]; + end + ADDR_ISA_0: begin + rdata <= isa_caps[31:0]; + end + ADDR_ISA_1: begin + rdata <= isa_caps[63:32]; + end + `ifdef SCOPE + ADDR_SCP_0: begin + rdata <= scope_bus_rdata[31:0]; + end + ADDR_SCP_1: begin + rdata <= scope_bus_rdata[63:32]; + end + `endif + default:; + endcase + end + + assign ap_reset = ap_reset_r; + assign ap_start = ap_start_r; + assign interrupt = gie_r & (| isr_r); + + assign ap_ctrl_read = s_axi_r_fire && (raddr == ADDR_AP_CTRL); + + assign dcr_wr_valid = dcr_wr_valid_r; + assign dcr_wr_addr = VX_DCR_ADDR_WIDTH'(dcra_r); + assign dcr_wr_data = VX_DCR_DATA_WIDTH'(dcrv_r); + +endmodule diff --git a/designs/src/vortex/rtl/afu/xrt/VX_afu_wrap.sv b/designs/src/vortex/rtl/afu/xrt/VX_afu_wrap.sv new file mode 100644 index 0000000..f2c220f --- /dev/null +++ b/designs/src/vortex/rtl/afu/xrt/VX_afu_wrap.sv @@ -0,0 +1,483 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Reference: https://www.xilinx.com/developer/articles/porting-rtl-designs-to-vitis-rtl-kernels.html + +`include "vortex_afu.vh" + +module VX_afu_wrap import VX_gpu_pkg::*; #( + parameter C_S_AXI_CTRL_ADDR_WIDTH = 8, + parameter C_S_AXI_CTRL_DATA_WIDTH = 32, + parameter C_M_AXI_MEM_ID_WIDTH = `PLATFORM_MEMORY_ID_WIDTH, + parameter C_M_AXI_MEM_DATA_WIDTH = `PLATFORM_MEMORY_DATA_SIZE * 8, + parameter C_M_AXI_MEM_ADDR_WIDTH = 64, +`ifdef PLATFORM_MERGED_MEMORY_INTERFACE + parameter C_M_AXI_MEM_NUM_BANKS = 1 +`else + parameter C_M_AXI_MEM_NUM_BANKS = `PLATFORM_MEMORY_NUM_BANKS +`endif +) ( + // System signals + input wire clk, + input wire reset, + + // AXI4 master interface +`ifdef PLATFORM_MERGED_MEMORY_INTERFACE + `REPEAT (1, GEN_AXI_MEM, REPEAT_COMMA), +`else + `REPEAT (`PLATFORM_MEMORY_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA), +`endif + // AXI4-Lite slave interface + input wire s_axi_ctrl_awvalid, + output wire s_axi_ctrl_awready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr, + + input wire s_axi_ctrl_wvalid, + output wire s_axi_ctrl_wready, + input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata, + input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb, + + input wire s_axi_ctrl_arvalid, + output wire s_axi_ctrl_arready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr, + + output wire s_axi_ctrl_rvalid, + input wire s_axi_ctrl_rready, + output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata, + output wire [1:0] s_axi_ctrl_rresp, + + output wire s_axi_ctrl_bvalid, + input wire s_axi_ctrl_bready, + output wire [1:0] s_axi_ctrl_bresp, + + output wire interrupt +); + localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH; + + typedef enum logic [1:0] { + STATE_IDLE = 0, + STATE_INIT = 1, + STATE_RUN = 2, + STATE_DONE = 3 + } state_e; + + localparam PENDING_WR_SIZEW = 12; // max outstanding requests size + localparam NUM_MEM_BANKS_SIZEW = `CLOG2(C_M_AXI_MEM_NUM_BANKS+1); + + wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_awid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [7:0] m_axi_mem_awlen_a [C_M_AXI_MEM_NUM_BANKS]; + + wire m_axi_mem_wvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_wdata_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_wstrb_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_wlast_a [C_M_AXI_MEM_NUM_BANKS]; + + wire m_axi_mem_bvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_bready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_bid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_bresp_a [C_M_AXI_MEM_NUM_BANKS]; + + wire m_axi_mem_arvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_arready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_arid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [7:0] m_axi_mem_arlen_a [C_M_AXI_MEM_NUM_BANKS]; + + wire m_axi_mem_rvalid_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rready_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_rdata_a [C_M_AXI_MEM_NUM_BANKS]; + wire m_axi_mem_rlast_a [C_M_AXI_MEM_NUM_BANKS]; + wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_rid_a [C_M_AXI_MEM_NUM_BANKS]; + wire [1:0] m_axi_mem_rresp_a [C_M_AXI_MEM_NUM_BANKS]; + + // convert memory interface to array +`ifdef PLATFORM_MERGED_MEMORY_INTERFACE + `REPEAT (1, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON); +`else + `REPEAT (`PLATFORM_MEMORY_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON); +`endif + + reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr; + reg [PENDING_WR_SIZEW-1:0] vx_pending_writes; + reg vx_reset = 1; // asserted at initialization + wire vx_busy; + + wire dcr_wr_valid; + wire [VX_DCR_ADDR_WIDTH-1:0] dcr_wr_addr; + wire [VX_DCR_DATA_WIDTH-1:0] dcr_wr_data; + + state_e state; + + wire ap_reset; + wire ap_start; + wire ap_ctrl_read; + wire ap_idle = (state == STATE_IDLE); + wire ap_done = (state == STATE_DONE) && (vx_pending_writes == '0); + wire ap_ready = ap_done; + + wire ap_done_ack = ap_done && ap_ctrl_read; + +`ifdef SCOPE + wire scope_bus_in; + wire scope_bus_out; + wire scope_reset = reset; +`endif + + always @(posedge clk) begin + if (reset || ap_reset) begin + state <= STATE_IDLE; + vx_reset <= 1; + end else begin + case (state) + STATE_IDLE: begin + if (ap_start) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Begin initialization\n", $time)) + `endif + state <= STATE_INIT; + vx_reset_ctr <= (`RESET_DELAY-1); + vx_reset <= 1; + end + end + STATE_INIT: begin + if (vx_reset) begin + // wait for reset to complete + if (vx_reset_ctr == 0) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Initialization completed\n", $time)) + `endif + vx_reset <= 0; + end + end else begin + // wait until processor goes busy + if (vx_busy) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Begin execution\n", $time)) + `endif + state <= STATE_RUN; + end + end + end + STATE_RUN: begin + // wait until the processor is not busy + if (~vx_busy) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Execution completed\n", $time)) + `endif + state <= STATE_DONE; + end + end + STATE_DONE: begin + // wait for host's done acknowledgement + if (ap_done_ack) begin + `ifdef DBG_TRACE_AFU + `TRACE(2, ("%t: AFU: Processor idle\n", $time)) + `endif + state <= STATE_IDLE; + end + end + endcase + + // ensure reset network initialization + if (vx_reset_ctr != '0) begin + vx_reset_ctr <= vx_reset_ctr - 1; + end + end + end + + wire [C_M_AXI_MEM_NUM_BANKS-1:0] m_axi_wr_req_fire, m_axi_wr_rsp_fire; + wire [NUM_MEM_BANKS_SIZEW-1:0] cur_wr_reqs, cur_wr_rsps; + + for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_m_axi_wr_req_fire + VX_axi_write_ack axi_write_ack ( + .clk (clk), + .reset (reset), + .awvalid(m_axi_mem_awvalid_a[i]), + .awready(m_axi_mem_awready_a[i]), + .wvalid (m_axi_mem_wvalid_a[i]), + .wready (m_axi_mem_wready_a[i]), + .tx_ack (m_axi_wr_req_fire[i]), + `UNUSED_PIN (aw_ack), + `UNUSED_PIN (w_ack), + `UNUSED_PIN (tx_rdy) + ); + end + + for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_m_axi_wr_rsp_fire + assign m_axi_wr_rsp_fire[i] = m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i]; + end + + `POP_COUNT(cur_wr_reqs, m_axi_wr_req_fire); + `POP_COUNT(cur_wr_rsps, m_axi_wr_rsp_fire); + + wire signed [NUM_MEM_BANKS_SIZEW:0] reqs_sub = (NUM_MEM_BANKS_SIZEW+1)'(cur_wr_reqs) - + (NUM_MEM_BANKS_SIZEW+1)'(cur_wr_rsps); + + always @(posedge clk) begin + if (reset) begin + vx_pending_writes <= '0; + end else begin + vx_pending_writes <= vx_pending_writes + PENDING_WR_SIZEW'(reqs_sub); + end + end + + VX_afu_ctrl #( + .S_AXI_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH), + .S_AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) + ) afu_ctrl ( + .clk (clk), + .reset (reset), + + .s_axi_awvalid (s_axi_ctrl_awvalid), + .s_axi_awready (s_axi_ctrl_awready), + .s_axi_awaddr (s_axi_ctrl_awaddr), + + .s_axi_wvalid (s_axi_ctrl_wvalid), + .s_axi_wready (s_axi_ctrl_wready), + .s_axi_wdata (s_axi_ctrl_wdata), + .s_axi_wstrb (s_axi_ctrl_wstrb), + + .s_axi_arvalid (s_axi_ctrl_arvalid), + .s_axi_arready (s_axi_ctrl_arready), + .s_axi_araddr (s_axi_ctrl_araddr), + + .s_axi_rvalid (s_axi_ctrl_rvalid), + .s_axi_rready (s_axi_ctrl_rready), + .s_axi_rdata (s_axi_ctrl_rdata), + .s_axi_rresp (s_axi_ctrl_rresp), + + .s_axi_bvalid (s_axi_ctrl_bvalid), + .s_axi_bready (s_axi_ctrl_bready), + .s_axi_bresp (s_axi_ctrl_bresp), + + .ap_reset (ap_reset), + .ap_start (ap_start), + .ap_done (ap_done), + .ap_ready (ap_ready), + .ap_idle (ap_idle), + .interrupt (interrupt), + + .ap_ctrl_read (ap_ctrl_read), + + `ifdef SCOPE + .scope_bus_in (scope_bus_out), + .scope_bus_out (scope_bus_in), + `endif + + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data) + ); + + wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_awaddr_u [C_M_AXI_MEM_NUM_BANKS]; + wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_u [C_M_AXI_MEM_NUM_BANKS]; + + for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_addressing + assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET); + assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET); + end + + `SCOPE_IO_SWITCH (2); + + Vortex_axi #( + .AXI_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH), + .AXI_ADDR_WIDTH (M_AXI_MEM_ADDR_WIDTH), + .AXI_TID_WIDTH (C_M_AXI_MEM_ID_WIDTH), + .AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS) + ) vortex_axi ( + `SCOPE_IO_BIND (1) + + .clk (clk), + .reset (vx_reset), + + .m_axi_awvalid (m_axi_mem_awvalid_a), + .m_axi_awready (m_axi_mem_awready_a), + .m_axi_awaddr (m_axi_mem_awaddr_u), + .m_axi_awid (m_axi_mem_awid_a), + .m_axi_awlen (m_axi_mem_awlen_a), + `UNUSED_PIN (m_axi_awsize), + `UNUSED_PIN (m_axi_awburst), + `UNUSED_PIN (m_axi_awlock), + `UNUSED_PIN (m_axi_awcache), + `UNUSED_PIN (m_axi_awprot), + `UNUSED_PIN (m_axi_awqos), + `UNUSED_PIN (m_axi_awregion), + + .m_axi_wvalid (m_axi_mem_wvalid_a), + .m_axi_wready (m_axi_mem_wready_a), + .m_axi_wdata (m_axi_mem_wdata_a), + .m_axi_wstrb (m_axi_mem_wstrb_a), + .m_axi_wlast (m_axi_mem_wlast_a), + + .m_axi_bvalid (m_axi_mem_bvalid_a), + .m_axi_bready (m_axi_mem_bready_a), + .m_axi_bid (m_axi_mem_bid_a), + .m_axi_bresp (m_axi_mem_bresp_a), + + .m_axi_arvalid (m_axi_mem_arvalid_a), + .m_axi_arready (m_axi_mem_arready_a), + .m_axi_araddr (m_axi_mem_araddr_u), + .m_axi_arid (m_axi_mem_arid_a), + .m_axi_arlen (m_axi_mem_arlen_a), + `UNUSED_PIN (m_axi_arsize), + `UNUSED_PIN (m_axi_arburst), + `UNUSED_PIN (m_axi_arlock), + `UNUSED_PIN (m_axi_arcache), + `UNUSED_PIN (m_axi_arprot), + `UNUSED_PIN (m_axi_arqos), + `UNUSED_PIN (m_axi_arregion), + + .m_axi_rvalid (m_axi_mem_rvalid_a), + .m_axi_rready (m_axi_mem_rready_a), + .m_axi_rdata (m_axi_mem_rdata_a), + .m_axi_rlast (m_axi_mem_rlast_a), + .m_axi_rid (m_axi_mem_rid_a), + .m_axi_rresp (m_axi_mem_rresp_a), + + .dcr_wr_valid (dcr_wr_valid), + .dcr_wr_addr (dcr_wr_addr), + .dcr_wr_data (dcr_wr_data), + + .busy (vx_busy) + ); + + // SCOPE ////////////////////////////////////////////////////////////////////// + +`ifdef SCOPE +`ifdef DBG_SCOPE_AFU + wire m_axi_mem_awfire_0 = m_axi_mem_awvalid_a[0] & m_axi_mem_awready_a[0]; + wire m_axi_mem_arfire_0 = m_axi_mem_arvalid_a[0] & m_axi_mem_arready_a[0]; + wire m_axi_mem_wfire_0 = m_axi_mem_wvalid_a[0] & m_axi_mem_wready_a[0]; + wire m_axi_mem_bfire_0 = m_axi_mem_bvalid_a[0] & m_axi_mem_bready_a[0]; + wire reset_negedge; + `NEG_EDGE (reset_negedge, reset); + `SCOPE_TAP (0, 0, { + ap_reset, + ap_start, + ap_done, + ap_idle, + interrupt, + vx_reset, + vx_busy, + state, + m_axi_mem_awvalid_a[0], + m_axi_mem_awready_a[0], + m_axi_mem_wvalid_a[0], + m_axi_mem_wready_a[0], + m_axi_mem_bvalid_a[0], + m_axi_mem_bready_a[0], + m_axi_mem_arvalid_a[0], + m_axi_mem_arready_a[0], + m_axi_mem_rvalid_a[0], + m_axi_mem_rready_a[0] + }, { + dcr_wr_valid, + m_axi_mem_awfire_0, + m_axi_mem_arfire_0, + m_axi_mem_wfire_0, + m_axi_mem_bfire_0 + }, { + dcr_wr_addr, + dcr_wr_data, + vx_pending_writes, + m_axi_mem_awaddr_u[0], + m_axi_mem_awid_a[0], + m_axi_mem_bid_a[0], + m_axi_mem_araddr_u[0], + m_axi_mem_arid_a[0], + m_axi_mem_rid_a[0] + }, + reset_negedge, 1'b0, 4096 + ); +`else + `SCOPE_IO_UNUSED(0) +`endif +`endif + +`ifdef CHIPSCOPE +`ifdef DBG_SCOPE_AFU + ila_afu ila_afu_inst ( + .clk (clk), + .probe0 ({ + ap_reset, + ap_start, + ap_done, + ap_idle, + state, + interrupt + }), + .probe1 ({ + vx_pending_writes, + vx_busy, + vx_reset, + dcr_wr_valid, + dcr_wr_addr, + dcr_wr_data + }) + ); +`endif +`endif + +`ifdef SIMULATION +`ifndef VERILATOR + // disable assertions until full reset + reg [`CLOG2(`RESET_DELAY+1)-1:0] assert_delay_ctr; + reg assert_enabled; + initial begin + $assertoff(0, vortex_axi); + end + always @(posedge clk) begin + if (reset) begin + assert_delay_ctr <= '0; + assert_enabled <= 0; + end else begin + if (~assert_enabled) begin + if (assert_delay_ctr == (`RESET_DELAY-1)) begin + assert_enabled <= 1; + $asserton(0, vortex_axi); // enable assertions + end else begin + assert_delay_ctr <= assert_delay_ctr + 1; + end + end + end + end +`endif +`endif + +`ifdef DBG_TRACE_AFU + always @(posedge clk) begin + for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin + if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin + `TRACE(2, ("%t: AXI Wr Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i])) + end + if (m_axi_mem_wvalid_a[i] && m_axi_mem_wready_a[i]) begin + `TRACE(2, ("%t: AXI Wr Req [%0d]: strb=0x%h, data=0x%h\n", $time, i, m_axi_mem_wstrb_a[i], m_axi_mem_wdata_a[i])) + end + if (m_axi_mem_bvalid_a[i] && m_axi_mem_bready_a[i]) begin + `TRACE(2, ("%t: AXI Wr Rsp [%0d]: id=0x%0h\n", $time, i, m_axi_mem_bid_a[i])) + end + if (m_axi_mem_arvalid_a[i] && m_axi_mem_arready_a[i]) begin + `TRACE(2, ("%t: AXI Rd Req [%0d]: addr=0x%0h, id=0x%0h\n", $time, i, m_axi_mem_araddr_a[i], m_axi_mem_arid_a[i])) + end + if (m_axi_mem_rvalid_a[i] && m_axi_mem_rready_a[i]) begin + `TRACE(2, ("%t: AXI Rd Rsp [%0d]: data=0x%h, id=0x%0h\n", $time, i, m_axi_mem_rdata_a[i], m_axi_mem_rid_a[i])) + end + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/afu/xrt/vortex_afu.v b/designs/src/vortex/rtl/afu/xrt/vortex_afu.v new file mode 100644 index 0000000..bfae112 --- /dev/null +++ b/designs/src/vortex/rtl/afu/xrt/vortex_afu.v @@ -0,0 +1,105 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "vortex_afu.vh" + +module vortex_afu #( + parameter C_S_AXI_CTRL_ADDR_WIDTH = 8, + parameter C_S_AXI_CTRL_DATA_WIDTH = 32, + parameter C_M_AXI_MEM_ID_WIDTH = `PLATFORM_MEMORY_ID_WIDTH, + parameter C_M_AXI_MEM_DATA_WIDTH = (`PLATFORM_MEMORY_DATA_SIZE * 8), + parameter C_M_AXI_MEM_ADDR_WIDTH = 64, +`ifdef PLATFORM_MERGED_MEMORY_INTERFACE + parameter C_M_AXI_MEM_NUM_BANKS = 1 +`else + parameter C_M_AXI_MEM_NUM_BANKS = `PLATFORM_MEMORY_NUM_BANKS +`endif +) ( + // System signals + input wire ap_clk, + input wire ap_rst_n, + + // AXI4 master interface +`ifdef PLATFORM_MERGED_MEMORY_INTERFACE + `REPEAT (1, GEN_AXI_MEM, REPEAT_COMMA), +`else + `REPEAT (`PLATFORM_MEMORY_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA), +`endif + + // AXI4-Lite slave interface + input wire s_axi_ctrl_awvalid, + output wire s_axi_ctrl_awready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr, + + input wire s_axi_ctrl_wvalid, + output wire s_axi_ctrl_wready, + input wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata, + input wire [C_S_AXI_CTRL_DATA_WIDTH/8-1:0] s_axi_ctrl_wstrb, + + input wire s_axi_ctrl_arvalid, + output wire s_axi_ctrl_arready, + input wire [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr, + + output wire s_axi_ctrl_rvalid, + input wire s_axi_ctrl_rready, + output wire [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata, + output wire [1:0] s_axi_ctrl_rresp, + + output wire s_axi_ctrl_bvalid, + input wire s_axi_ctrl_bready, + output wire [1:0] s_axi_ctrl_bresp, + + output wire interrupt +); + + VX_afu_wrap #( + .C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH), + .C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH), + .C_M_AXI_MEM_ID_WIDTH (C_M_AXI_MEM_ID_WIDTH), + .C_M_AXI_MEM_ADDR_WIDTH (C_M_AXI_MEM_ADDR_WIDTH), + .C_M_AXI_MEM_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH), + .C_M_AXI_MEM_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS) + ) afu_wrap ( + .clk (ap_clk), + .reset (~ap_rst_n), + `ifdef PLATFORM_MERGED_MEMORY_INTERFACE + `REPEAT (1, AXI_MEM_ARGS, REPEAT_COMMA), + `else + `REPEAT (`PLATFORM_MEMORY_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA), + `endif + .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid), + .s_axi_ctrl_awready (s_axi_ctrl_awready), + .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr), + + .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid), + .s_axi_ctrl_wready (s_axi_ctrl_wready), + .s_axi_ctrl_wdata (s_axi_ctrl_wdata), + .s_axi_ctrl_wstrb (s_axi_ctrl_wstrb), + + .s_axi_ctrl_arvalid (s_axi_ctrl_arvalid), + .s_axi_ctrl_arready (s_axi_ctrl_arready), + .s_axi_ctrl_araddr (s_axi_ctrl_araddr), + + .s_axi_ctrl_rvalid (s_axi_ctrl_rvalid), + .s_axi_ctrl_rready (s_axi_ctrl_rready), + .s_axi_ctrl_rdata (s_axi_ctrl_rdata), + .s_axi_ctrl_rresp (s_axi_ctrl_rresp), + + .s_axi_ctrl_bvalid (s_axi_ctrl_bvalid), + .s_axi_ctrl_bready (s_axi_ctrl_bready), + .s_axi_ctrl_bresp (s_axi_ctrl_bresp), + + .interrupt (interrupt) + ); + +endmodule diff --git a/designs/src/vortex/rtl/afu/xrt/vortex_afu.vh b/designs/src/vortex/rtl/afu/xrt/vortex_afu.vh new file mode 100644 index 0000000..c66ede2 --- /dev/null +++ b/designs/src/vortex/rtl/afu/xrt/vortex_afu.vh @@ -0,0 +1,108 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VORTEX_AFU_VH +`define VORTEX_AFU_VH + +`ifndef PLATFORM_MEMORY_OFFSET +`define PLATFORM_MEMORY_OFFSET 0 +`endif + +`ifndef PLATFORM_MEMORY_ID_WIDTH +`define PLATFORM_MEMORY_ID_WIDTH 32 +`endif + +`define GEN_AXI_MEM(i) \ + output wire m_axi_mem_``i``_awvalid, \ + input wire m_axi_mem_``i``_awready, \ + output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_awaddr, \ + output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_awid, \ + output wire [7:0] m_axi_mem_``i``_awlen, \ + output wire m_axi_mem_``i``_wvalid, \ + input wire m_axi_mem_``i``_wready, \ + output wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_wdata, \ + output wire [C_M_AXI_MEM_DATA_WIDTH/8-1:0] m_axi_mem_``i``_wstrb, \ + output wire m_axi_mem_``i``_wlast, \ + output wire m_axi_mem_``i``_arvalid, \ + input wire m_axi_mem_``i``_arready, \ + output wire [C_M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_``i``_araddr, \ + output wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_arid, \ + output wire [7:0] m_axi_mem_``i``_arlen, \ + input wire m_axi_mem_``i``_rvalid, \ + output wire m_axi_mem_``i``_rready, \ + input wire [C_M_AXI_MEM_DATA_WIDTH-1:0] m_axi_mem_``i``_rdata, \ + input wire m_axi_mem_``i``_rlast, \ + input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_rid, \ + input wire [1:0] m_axi_mem_``i``_rresp, \ + input wire m_axi_mem_``i``_bvalid, \ + output wire m_axi_mem_``i``_bready, \ + input wire [1:0] m_axi_mem_``i``_bresp, \ + input wire [C_M_AXI_MEM_ID_WIDTH-1:0] m_axi_mem_``i``_bid + +`define AXI_MEM_ARGS(i) \ + .m_axi_mem_``i``_awvalid(m_axi_mem_``i``_awvalid), \ + .m_axi_mem_``i``_awready(m_axi_mem_``i``_awready), \ + .m_axi_mem_``i``_awaddr(m_axi_mem_``i``_awaddr), \ + .m_axi_mem_``i``_awid(m_axi_mem_``i``_awid), \ + .m_axi_mem_``i``_awlen(m_axi_mem_``i``_awlen), \ + .m_axi_mem_``i``_wvalid(m_axi_mem_``i``_wvalid), \ + .m_axi_mem_``i``_wready(m_axi_mem_``i``_wready), \ + .m_axi_mem_``i``_wdata(m_axi_mem_``i``_wdata), \ + .m_axi_mem_``i``_wstrb(m_axi_mem_``i``_wstrb), \ + .m_axi_mem_``i``_wlast(m_axi_mem_``i``_wlast), \ + .m_axi_mem_``i``_arvalid(m_axi_mem_``i``_arvalid), \ + .m_axi_mem_``i``_arready(m_axi_mem_``i``_arready), \ + .m_axi_mem_``i``_araddr(m_axi_mem_``i``_araddr), \ + .m_axi_mem_``i``_arid(m_axi_mem_``i``_arid), \ + .m_axi_mem_``i``_arlen(m_axi_mem_``i``_arlen), \ + .m_axi_mem_``i``_rvalid(m_axi_mem_``i``_rvalid), \ + .m_axi_mem_``i``_rready(m_axi_mem_``i``_rready), \ + .m_axi_mem_``i``_rdata(m_axi_mem_``i``_rdata), \ + .m_axi_mem_``i``_rlast(m_axi_mem_``i``_rlast), \ + .m_axi_mem_``i``_rid(m_axi_mem_``i``_rid), \ + .m_axi_mem_``i``_rresp(m_axi_mem_``i``_rresp), \ + .m_axi_mem_``i``_bvalid(m_axi_mem_``i``_bvalid), \ + .m_axi_mem_``i``_bready(m_axi_mem_``i``_bready), \ + .m_axi_mem_``i``_bresp(m_axi_mem_``i``_bresp), \ + .m_axi_mem_``i``_bid(m_axi_mem_``i``_bid) + +`define AXI_MEM_TO_ARRAY(i) \ + assign m_axi_mem_``i``_awvalid = m_axi_mem_awvalid_a[i]; \ + assign m_axi_mem_awready_a[i] = m_axi_mem_``i``_awready; \ + assign m_axi_mem_``i``_awaddr = m_axi_mem_awaddr_a[i]; \ + assign m_axi_mem_``i``_awid = m_axi_mem_awid_a[i]; \ + assign m_axi_mem_``i``_awlen = m_axi_mem_awlen_a[i]; \ + assign m_axi_mem_``i``_wvalid = m_axi_mem_wvalid_a[i]; \ + assign m_axi_mem_wready_a[i] = m_axi_mem_``i``_wready; \ + assign m_axi_mem_``i``_wdata = m_axi_mem_wdata_a[i]; \ + assign m_axi_mem_``i``_wstrb = m_axi_mem_wstrb_a[i]; \ + assign m_axi_mem_``i``_wlast = m_axi_mem_wlast_a[i]; \ + assign m_axi_mem_``i``_arvalid = m_axi_mem_arvalid_a[i]; \ + assign m_axi_mem_arready_a[i] = m_axi_mem_``i``_arready; \ + assign m_axi_mem_``i``_araddr = m_axi_mem_araddr_a[i]; \ + assign m_axi_mem_``i``_arid = m_axi_mem_arid_a[i]; \ + assign m_axi_mem_``i``_arlen = m_axi_mem_arlen_a[i]; \ + assign m_axi_mem_rvalid_a[i] = m_axi_mem_``i``_rvalid; \ + assign m_axi_mem_``i``_rready = m_axi_mem_rready_a[i]; \ + assign m_axi_mem_rdata_a[i] = m_axi_mem_``i``_rdata; \ + assign m_axi_mem_rlast_a[i] = m_axi_mem_``i``_rlast; \ + assign m_axi_mem_rid_a[i] = m_axi_mem_``i``_rid; \ + assign m_axi_mem_rresp_a[i] = m_axi_mem_``i``_rresp; \ + assign m_axi_mem_bvalid_a[i] = m_axi_mem_``i``_bvalid; \ + assign m_axi_mem_``i``_bready = m_axi_mem_bready_a[i]; \ + assign m_axi_mem_bresp_a[i] = m_axi_mem_``i``_bresp; \ + assign m_axi_mem_bid_a[i] = m_axi_mem_``i``_bid + +`include "VX_define.vh" + +`endif // VORTEX_AFU_VH diff --git a/designs/src/vortex/rtl/cache/VX_cache.sv b/designs/src/vortex/rtl/cache/VX_cache.sv new file mode 100644 index 0000000..4925772 --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache.sv @@ -0,0 +1,670 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + + // Number of memory ports + parameter MEM_PORTS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 32768, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 4, + // Number of associative ways + parameter NUM_WAYS = 4, + // Size of a word in bytes + parameter WORD_SIZE = 16, + + // Core Response Queue Size + parameter CRSQ_SIZE = 4, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 16, + // Memory Response Queue Size + parameter MRSQ_SIZE = 4, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Enable cache writeback + parameter WRITEBACK = 0, + + // Enable dirty bytes on writeback + parameter DIRTY_BYTES = 0, + + // Replacement policy + parameter REPL_POLICY = `CS_REPL_FIFO, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // Core response output register + parameter CORE_OUT_BUF = 3, + + // Memory request output register + parameter MEM_OUT_BUF = 3 + ) ( + // PERF +`ifdef PERF_ENABLE + output cache_perf_t cache_perf, +`endif + + input wire clk, + input wire reset, + + VX_mem_bus_if.slave core_bus_if [NUM_REQS], + VX_mem_bus_if.master mem_bus_if [MEM_PORTS] +); + + `STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter: number of banks must be power of 2")) + `STATIC_ASSERT(WRITE_ENABLE || !WRITEBACK, ("invalid parameter: writeback requires write enable")) + `STATIC_ASSERT(WRITEBACK || !DIRTY_BYTES, ("invalid parameter: dirty bytes require writeback")) + `STATIC_ASSERT(NUM_BANKS >= MEM_PORTS, ("invalid parameter: number of banks must be greater or equal to number of memory ports")) + + localparam REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS); + localparam WORD_SEL_WIDTH = `UP(`CS_WORD_SEL_BITS); + localparam MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE); + localparam MEM_TAG_WIDTH = `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, MEM_PORTS, UUID_WIDTH); + localparam WORDS_PER_LINE = LINE_SIZE / WORD_SIZE; + localparam WORD_WIDTH = WORD_SIZE * 8; + localparam WORD_SEL_BITS = `CLOG2(WORDS_PER_LINE); + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam LINE_ADDR_WIDTH = (`CS_WORD_ADDR_WIDTH - BANK_SEL_BITS - WORD_SEL_BITS); + localparam CORE_REQ_DATAW = LINE_ADDR_WIDTH + 1 + WORD_SEL_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH + `UP(MEM_FLAGS_WIDTH); + localparam CORE_RSP_DATAW = WORD_WIDTH + TAG_WIDTH; + localparam BANK_MEM_TAG_WIDTH = UUID_WIDTH + MSHR_ADDR_WIDTH; + localparam MEM_REQ_DATAW = (`CS_LINE_ADDR_WIDTH + 1 + LINE_SIZE + `CS_LINE_WIDTH + BANK_MEM_TAG_WIDTH + `UP(MEM_FLAGS_WIDTH)); + localparam MEM_RSP_DATAW = `CS_LINE_WIDTH + MEM_TAG_WIDTH; + localparam MEM_PORTS_SEL_BITS = `CLOG2(MEM_PORTS); + localparam MEM_PORTS_SEL_WIDTH = `UP(MEM_PORTS_SEL_BITS); + localparam MEM_ARB_SEL_BITS = `CLOG2(`CDIV(NUM_BANKS, MEM_PORTS)); + localparam MEM_ARB_SEL_WIDTH = `UP(MEM_ARB_SEL_BITS); + + localparam REQ_XBAR_BUF = (NUM_REQS > 2) ? 2 : 0; + localparam CORE_RSP_BUF_ENABLE = (NUM_BANKS != 1) || (NUM_REQS != 1); + localparam MEM_REQ_BUF_ENABLE = (NUM_BANKS != 1); + +`ifdef PERF_ENABLE + wire [NUM_BANKS-1:0] perf_read_miss_per_bank; + wire [NUM_BANKS-1:0] perf_write_miss_per_bank; + wire [NUM_BANKS-1:0] perf_mshr_stall_per_bank; +`endif + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH) + ) core_bus2_if[NUM_REQS](); + + wire [NUM_BANKS-1:0] per_bank_flush_begin; + wire [`UP(UUID_WIDTH)-1:0] flush_uuid; + wire [NUM_BANKS-1:0] per_bank_flush_end; + + wire [NUM_BANKS-1:0] per_bank_core_req_fire; + + VX_cache_init #( + .NUM_REQS (NUM_REQS), + .NUM_BANKS (NUM_BANKS), + .TAG_WIDTH (TAG_WIDTH), + .BANK_SEL_LATENCY (`TO_OUT_BUF_REG(REQ_XBAR_BUF)) // request xbar latency + ) cache_init ( + .clk (clk), + .reset (reset), + .core_bus_in_if (core_bus_if), + .core_bus_out_if (core_bus2_if), + .bank_req_fire (per_bank_core_req_fire), + .flush_begin (per_bank_flush_begin), + .flush_uuid (flush_uuid), + .flush_end (per_bank_flush_end) + ); + + // Memory response gather ///////////////////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) mem_bus_tmp_if[MEM_PORTS](); + + wire [MEM_PORTS-1:0] mem_rsp_queue_valid; + wire [MEM_PORTS-1:0][MEM_RSP_DATAW-1:0] mem_rsp_queue_data; + wire [MEM_PORTS-1:0] mem_rsp_queue_ready; + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_rsp_queue + VX_elastic_buffer #( + .DATAW (MEM_RSP_DATAW), + .SIZE (MRSQ_SIZE), + .OUT_REG (MRSQ_SIZE > 2) + ) mem_rsp_queue ( + .clk (clk), + .reset (reset), + .valid_in (mem_bus_tmp_if[i].rsp_valid), + .data_in (mem_bus_tmp_if[i].rsp_data), + .ready_in (mem_bus_tmp_if[i].rsp_ready), + .valid_out (mem_rsp_queue_valid[i]), + .data_out (mem_rsp_queue_data[i]), + .ready_out (mem_rsp_queue_ready[i]) + ); + end + + wire [MEM_PORTS-1:0][MEM_RSP_DATAW-MEM_ARB_SEL_BITS-1:0] mem_rsp_queue_data_s; + wire [MEM_PORTS-1:0][BANK_SEL_WIDTH-1:0] mem_rsp_queue_sel; + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_rsp_queue_data_s + wire [BANK_MEM_TAG_WIDTH-1:0] mem_rsp_tag_s = mem_rsp_queue_data[i][MEM_TAG_WIDTH-1:MEM_ARB_SEL_BITS]; + wire [`CS_LINE_WIDTH-1:0] mem_rsp_data_s = mem_rsp_queue_data[i][MEM_RSP_DATAW-1:MEM_TAG_WIDTH]; + assign mem_rsp_queue_data_s[i] = {mem_rsp_data_s, mem_rsp_tag_s}; + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_rsp_queue_sel + if (NUM_BANKS > 1) begin : g_multibanks + if (NUM_BANKS != MEM_PORTS) begin : g_arb_sel + VX_bits_concat #( + .L (MEM_ARB_SEL_BITS), + .R (MEM_PORTS_SEL_BITS) + ) mem_rsp_sel_concat ( + .left_in (mem_rsp_queue_data[i][MEM_ARB_SEL_BITS-1:0]), + .right_in (MEM_PORTS_SEL_WIDTH'(i)), + .data_out (mem_rsp_queue_sel[i]) + ); + end else begin : g_no_arb_sel + assign mem_rsp_queue_sel[i] = MEM_PORTS_SEL_WIDTH'(i); + end + end else begin : g_singlebank + assign mem_rsp_queue_sel[i] = 0; + end + end + + wire [NUM_BANKS-1:0] per_bank_mem_rsp_valid; + wire [NUM_BANKS-1:0][MEM_RSP_DATAW-MEM_ARB_SEL_BITS-1:0] per_bank_mem_rsp_pdata; + wire [NUM_BANKS-1:0] per_bank_mem_rsp_ready; + + VX_stream_omega #( + .NUM_INPUTS (MEM_PORTS), + .NUM_OUTPUTS (NUM_BANKS), + .DATAW (MEM_RSP_DATAW-MEM_ARB_SEL_BITS), + .ARBITER ("R"), + .OUT_BUF (3) + ) mem_rsp_xbar ( + .clk (clk), + .reset (reset), + .valid_in (mem_rsp_queue_valid), + .data_in (mem_rsp_queue_data_s), + .sel_in (mem_rsp_queue_sel), + .ready_in (mem_rsp_queue_ready), + .valid_out (per_bank_mem_rsp_valid), + .data_out (per_bank_mem_rsp_pdata), + `UNUSED_PIN (sel_out), + .ready_out (per_bank_mem_rsp_ready), + `UNUSED_PIN (collisions) + ); + + wire [NUM_BANKS-1:0][`CS_LINE_WIDTH-1:0] per_bank_mem_rsp_data; + wire [NUM_BANKS-1:0][BANK_MEM_TAG_WIDTH-1:0] per_bank_mem_rsp_tag; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_per_bank_mem_rsp_data + assign { + per_bank_mem_rsp_data[i], + per_bank_mem_rsp_tag[i] + } = per_bank_mem_rsp_pdata[i]; + end + + // Core requests dispatch ///////////////////////////////////////////////// + + wire [NUM_BANKS-1:0] per_bank_core_req_valid; + wire [NUM_BANKS-1:0][`CS_LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr; + wire [NUM_BANKS-1:0] per_bank_core_req_rw; + wire [NUM_BANKS-1:0][WORD_SEL_WIDTH-1:0] per_bank_core_req_wsel; + wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen; + wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_core_req_data; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_core_req_tag; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_core_req_idx; + wire [NUM_BANKS-1:0][`UP(MEM_FLAGS_WIDTH)-1:0] per_bank_core_req_flags; + wire [NUM_BANKS-1:0] per_bank_core_req_ready; + + wire [NUM_BANKS-1:0] per_bank_core_rsp_valid; + wire [NUM_BANKS-1:0][`CS_WORD_WIDTH-1:0] per_bank_core_rsp_data; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_core_rsp_tag; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_core_rsp_idx; + wire [NUM_BANKS-1:0] per_bank_core_rsp_ready; + + wire [NUM_BANKS-1:0] per_bank_mem_req_valid; + wire [NUM_BANKS-1:0][`CS_LINE_ADDR_WIDTH-1:0] per_bank_mem_req_addr; + wire [NUM_BANKS-1:0] per_bank_mem_req_rw; + wire [NUM_BANKS-1:0][LINE_SIZE-1:0] per_bank_mem_req_byteen; + wire [NUM_BANKS-1:0][`CS_LINE_WIDTH-1:0] per_bank_mem_req_data; + wire [NUM_BANKS-1:0][BANK_MEM_TAG_WIDTH-1:0] per_bank_mem_req_tag; + wire [NUM_BANKS-1:0][`UP(MEM_FLAGS_WIDTH)-1:0] per_bank_mem_req_flags; + wire [NUM_BANKS-1:0] per_bank_mem_req_ready; + + wire [NUM_REQS-1:0] core_req_valid; + wire [NUM_REQS-1:0][`CS_WORD_ADDR_WIDTH-1:0] core_req_addr; + wire [NUM_REQS-1:0] core_req_rw; + wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_req_data; + wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_req_tag; + wire [NUM_REQS-1:0][`UP(MEM_FLAGS_WIDTH)-1:0] core_req_flags; + wire [NUM_REQS-1:0] core_req_ready; + + wire [NUM_REQS-1:0][LINE_ADDR_WIDTH-1:0] core_req_line_addr; + wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] core_req_bid; + wire [NUM_REQS-1:0][WORD_SEL_WIDTH-1:0] core_req_wsel; + + wire [NUM_REQS-1:0][CORE_REQ_DATAW-1:0] core_req_data_in; + wire [NUM_BANKS-1:0][CORE_REQ_DATAW-1:0] core_req_data_out; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req + assign core_req_valid[i] = core_bus2_if[i].req_valid; + assign core_req_rw[i] = core_bus2_if[i].req_data.rw; + assign core_req_byteen[i] = core_bus2_if[i].req_data.byteen; + assign core_req_addr[i] = core_bus2_if[i].req_data.addr; + assign core_req_data[i] = core_bus2_if[i].req_data.data; + assign core_req_tag[i] = core_bus2_if[i].req_data.tag; + assign core_req_flags[i] = `UP(MEM_FLAGS_WIDTH)'(core_bus2_if[i].req_data.flags); + assign core_bus2_if[i].req_ready = core_req_ready[i]; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_wsel + if (WORDS_PER_LINE > 1) begin : g_wsel + assign core_req_wsel[i] = core_req_addr[i][0 +: WORD_SEL_BITS]; + end else begin : g_no_wsel + assign core_req_wsel[i] = '0; + end + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_line_addr + assign core_req_line_addr[i] = core_req_addr[i][(BANK_SEL_BITS + WORD_SEL_BITS) +: LINE_ADDR_WIDTH]; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_bid + if (NUM_BANKS > 1) begin : g_multibanks + assign core_req_bid[i] = core_req_addr[i][WORD_SEL_BITS +: BANK_SEL_BITS]; + end else begin : g_singlebank + assign core_req_bid[i] = '0; + end + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_data_in + assign core_req_data_in[i] = { + core_req_line_addr[i], + core_req_rw[i], + core_req_wsel[i], + core_req_byteen[i], + core_req_data[i], + core_req_tag[i], + core_req_flags[i] + }; + end + + assign per_bank_core_req_fire = per_bank_core_req_valid & per_bank_mem_req_ready; + +`ifdef PERF_ENABLE + wire [PERF_CTR_BITS-1:0] perf_collisions; +`endif + + VX_stream_xbar #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS (NUM_BANKS), + .DATAW (CORE_REQ_DATAW), + .PERF_CTR_BITS (PERF_CTR_BITS), + .ARBITER ("R"), + .OUT_BUF (REQ_XBAR_BUF) + ) core_req_xbar ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .collisions(perf_collisions), + `else + `UNUSED_PIN(collisions), + `endif + .valid_in (core_req_valid), + .data_in (core_req_data_in), + .sel_in (core_req_bid), + .ready_in (core_req_ready), + .valid_out (per_bank_core_req_valid), + .data_out (core_req_data_out), + .sel_out (per_bank_core_req_idx), + .ready_out (per_bank_core_req_ready) + ); + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_core_req_data_out + assign { + per_bank_core_req_addr[i], + per_bank_core_req_rw[i], + per_bank_core_req_wsel[i], + per_bank_core_req_byteen[i], + per_bank_core_req_data[i], + per_bank_core_req_tag[i], + per_bank_core_req_flags[i] + } = core_req_data_out[i]; + end + + // Banks access /////////////////////////////////////////////////////////// + + for (genvar bank_id = 0; bank_id < NUM_BANKS; ++bank_id) begin : g_banks + VX_cache_bank #( + .BANK_ID (bank_id), + .INSTANCE_ID (`SFORMATF(("%s-bank%0d", INSTANCE_ID, bank_id))), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .WRITE_ENABLE (WRITE_ENABLE), + .WRITEBACK (WRITEBACK), + .DIRTY_BYTES (DIRTY_BYTES), + .REPL_POLICY (REPL_POLICY), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .CORE_OUT_REG (CORE_RSP_BUF_ENABLE ? 0 : `TO_OUT_BUF_REG(CORE_OUT_BUF)), + .MEM_OUT_REG (MEM_REQ_BUF_ENABLE ? 0 : `TO_OUT_BUF_REG(MEM_OUT_BUF)) + ) bank ( + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .perf_read_miss (perf_read_miss_per_bank[bank_id]), + .perf_write_miss (perf_write_miss_per_bank[bank_id]), + .perf_mshr_stall (perf_mshr_stall_per_bank[bank_id]), + `endif + + // Core request + .core_req_valid (per_bank_core_req_valid[bank_id]), + .core_req_addr (per_bank_core_req_addr[bank_id]), + .core_req_rw (per_bank_core_req_rw[bank_id]), + .core_req_wsel (per_bank_core_req_wsel[bank_id]), + .core_req_byteen (per_bank_core_req_byteen[bank_id]), + .core_req_data (per_bank_core_req_data[bank_id]), + .core_req_tag (per_bank_core_req_tag[bank_id]), + .core_req_idx (per_bank_core_req_idx[bank_id]), + .core_req_flags (per_bank_core_req_flags[bank_id]), + .core_req_ready (per_bank_core_req_ready[bank_id]), + + // Core response + .core_rsp_valid (per_bank_core_rsp_valid[bank_id]), + .core_rsp_data (per_bank_core_rsp_data[bank_id]), + .core_rsp_tag (per_bank_core_rsp_tag[bank_id]), + .core_rsp_idx (per_bank_core_rsp_idx[bank_id]), + .core_rsp_ready (per_bank_core_rsp_ready[bank_id]), + + // Memory request + .mem_req_valid (per_bank_mem_req_valid[bank_id]), + .mem_req_addr (per_bank_mem_req_addr[bank_id]), + .mem_req_rw (per_bank_mem_req_rw[bank_id]), + .mem_req_byteen (per_bank_mem_req_byteen[bank_id]), + .mem_req_data (per_bank_mem_req_data[bank_id]), + .mem_req_tag (per_bank_mem_req_tag[bank_id]), + .mem_req_flags (per_bank_mem_req_flags[bank_id]), + .mem_req_ready (per_bank_mem_req_ready[bank_id]), + + // Memory response + .mem_rsp_valid (per_bank_mem_rsp_valid[bank_id]), + .mem_rsp_data (per_bank_mem_rsp_data[bank_id]), + .mem_rsp_tag (per_bank_mem_rsp_tag[bank_id]), + .mem_rsp_ready (per_bank_mem_rsp_ready[bank_id]), + + // Flush request + .flush_begin (per_bank_flush_begin[bank_id]), + .flush_uuid (flush_uuid), + .flush_end (per_bank_flush_end[bank_id]) + ); + end + + // Core responses gather ////////////////////////////////////////////////// + + wire [NUM_BANKS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_in; + wire [NUM_REQS-1:0][CORE_RSP_DATAW-1:0] core_rsp_data_out; + + wire [NUM_REQS-1:0] core_rsp_valid_s; + wire [NUM_REQS-1:0][`CS_WORD_WIDTH-1:0] core_rsp_data_s; + wire [NUM_REQS-1:0][TAG_WIDTH-1:0] core_rsp_tag_s; + wire [NUM_REQS-1:0] core_rsp_ready_s; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_core_rsp_data_in + assign core_rsp_data_in[i] = {per_bank_core_rsp_data[i], per_bank_core_rsp_tag[i]}; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS), + .NUM_OUTPUTS (NUM_REQS), + .DATAW (CORE_RSP_DATAW), + .ARBITER ("R") + ) core_rsp_xbar ( + .clk (clk), + .reset (reset), + `UNUSED_PIN (collisions), + .valid_in (per_bank_core_rsp_valid), + .data_in (core_rsp_data_in), + .sel_in (per_bank_core_rsp_idx), + .ready_in (per_bank_core_rsp_ready), + .valid_out (core_rsp_valid_s), + .data_out (core_rsp_data_out), + .ready_out (core_rsp_ready_s), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_data_s + assign {core_rsp_data_s[i], core_rsp_tag_s[i]} = core_rsp_data_out[i]; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_rsp_buf + VX_elastic_buffer #( + .DATAW (`CS_WORD_WIDTH + TAG_WIDTH), + .SIZE (CORE_RSP_BUF_ENABLE ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0), + .OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF)) + ) core_rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (core_rsp_valid_s[i]), + .ready_in (core_rsp_ready_s[i]), + .data_in ({core_rsp_data_s[i], core_rsp_tag_s[i]}), + .data_out ({core_bus2_if[i].rsp_data.data, core_bus2_if[i].rsp_data.tag}), + .valid_out (core_bus2_if[i].rsp_valid), + .ready_out (core_bus2_if[i].rsp_ready) + ); + end + + // Memory request arbitration ///////////////////////////////////////////// + + wire [NUM_BANKS-1:0][MEM_REQ_DATAW-1:0] per_bank_mem_req_pdata; + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_per_bank_mem_req_pdata + assign per_bank_mem_req_pdata[i] = { + per_bank_mem_req_rw[i], + per_bank_mem_req_addr[i], + per_bank_mem_req_data[i], + per_bank_mem_req_byteen[i], + per_bank_mem_req_flags[i], + per_bank_mem_req_tag[i] + }; + end + + wire [MEM_PORTS-1:0] mem_req_valid; + wire [MEM_PORTS-1:0][MEM_REQ_DATAW-1:0] mem_req_pdata; + wire [MEM_PORTS-1:0] mem_req_ready; + wire [MEM_PORTS-1:0][MEM_ARB_SEL_WIDTH-1:0] mem_req_sel_out; + + VX_stream_arb #( + .NUM_INPUTS (NUM_BANKS), + .NUM_OUTPUTS(MEM_PORTS), + .DATAW (MEM_REQ_DATAW), + .ARBITER ("R") + ) mem_req_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_bank_mem_req_valid), + .data_in (per_bank_mem_req_pdata), + .ready_in (per_bank_mem_req_ready), + .valid_out (mem_req_valid), + .data_out (mem_req_pdata), + .ready_out (mem_req_ready), + .sel_out (mem_req_sel_out) + ); + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_req_buf + wire mem_req_rw; + wire [`CS_LINE_ADDR_WIDTH-1:0] mem_req_addr; + wire [`CS_LINE_WIDTH-1:0] mem_req_data; + wire [LINE_SIZE-1:0] mem_req_byteen; + wire [`UP(MEM_FLAGS_WIDTH)-1:0] mem_req_flags; + wire [BANK_MEM_TAG_WIDTH-1:0] mem_req_tag; + + assign { + mem_req_rw, + mem_req_addr, + mem_req_data, + mem_req_byteen, + mem_req_flags, + mem_req_tag + } = mem_req_pdata[i]; + + wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr_w; + wire [MEM_TAG_WIDTH-1:0] mem_req_tag_w; + wire [`UP(MEM_FLAGS_WIDTH)-1:0] mem_req_flags_w; + + if (NUM_BANKS > 1) begin : g_mem_req_tag_multibanks + if (NUM_BANKS != MEM_PORTS) begin : g_arb_sel + wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id; + VX_bits_concat #( + .L (MEM_ARB_SEL_BITS), + .R (MEM_PORTS_SEL_BITS) + ) bank_id_concat ( + .left_in (mem_req_sel_out[i]), + .right_in (MEM_PORTS_SEL_WIDTH'(i)), + .data_out (mem_req_bank_id) + ); + assign mem_req_addr_w = `CS_MEM_ADDR_WIDTH'({mem_req_addr, mem_req_bank_id}); + assign mem_req_tag_w = {mem_req_tag, mem_req_sel_out[i]}; + end else begin : g_no_arb_sel + `UNUSED_VAR (mem_req_sel_out) + assign mem_req_addr_w = `CS_MEM_ADDR_WIDTH'({mem_req_addr, MEM_PORTS_SEL_WIDTH'(i)}); + assign mem_req_tag_w = MEM_TAG_WIDTH'(mem_req_tag); + end + end else begin : g_mem_req_tag + `UNUSED_VAR (mem_req_sel_out) + assign mem_req_addr_w = `CS_MEM_ADDR_WIDTH'(mem_req_addr); + assign mem_req_tag_w = MEM_TAG_WIDTH'(mem_req_tag); + end + + VX_elastic_buffer #( + .DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH + `UP(MEM_FLAGS_WIDTH)), + .SIZE (MEM_REQ_BUF_ENABLE ? `TO_OUT_BUF_SIZE(MEM_OUT_BUF) : 0), + .OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF)) + ) mem_req_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid[i]), + .ready_in (mem_req_ready[i]), + .data_in ({mem_req_rw, mem_req_byteen, mem_req_addr_w, mem_req_data, mem_req_tag_w, mem_req_flags}), + .data_out ({mem_bus_tmp_if[i].req_data.rw, mem_bus_tmp_if[i].req_data.byteen, mem_bus_tmp_if[i].req_data.addr, mem_bus_tmp_if[i].req_data.data, mem_bus_tmp_if[i].req_data.tag, mem_req_flags_w}), + .valid_out (mem_bus_tmp_if[i].req_valid), + .ready_out (mem_bus_tmp_if[i].req_ready) + ); + + if (MEM_FLAGS_WIDTH != 0) begin : g_mem_req_flags + assign mem_bus_tmp_if[i].req_data.flags = mem_req_flags_w; + end else begin : g_no_mem_req_flags + assign mem_bus_tmp_if[i].req_data.flags = '0; + `UNUSED_VAR (mem_req_flags_w) + end + + if (WRITE_ENABLE) begin : g_mem_bus_if + `ASSIGN_VX_MEM_BUS_IF (mem_bus_if[i], mem_bus_tmp_if[i]); + end else begin : g_mem_bus_if_ro + `ASSIGN_VX_MEM_BUS_RO_IF (mem_bus_if[i], mem_bus_tmp_if[i]); + end + end + +`ifdef PERF_ENABLE + wire [NUM_REQS-1:0] perf_core_reads_per_req; + wire [NUM_REQS-1:0] perf_core_writes_per_req; + wire [NUM_REQS-1:0] perf_crsp_stall_per_req; + wire [MEM_PORTS-1:0] perf_mem_stall_per_port; + + `BUFFER(perf_core_reads_per_req, core_req_valid & core_req_ready & ~core_req_rw); + `BUFFER(perf_core_writes_per_req, core_req_valid & core_req_ready & core_req_rw); + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_perf_crsp_stall_per_req + assign perf_crsp_stall_per_req[i] = core_bus_if[i].rsp_valid && ~core_bus_if[i].rsp_ready; + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_perf_mem_stall_per_port + assign perf_mem_stall_per_port[i] = mem_bus_if[i].req_valid && ~mem_bus_if[i].req_ready; + end + + // per cycle: read misses, write misses, msrq stalls, pipeline stalls + wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_read_miss_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_write_miss_per_cycle; + wire [`CLOG2(NUM_BANKS+1)-1:0] perf_mshr_stall_per_cycle; + wire [`CLOG2(MEM_PORTS+1)-1:0] perf_mem_stall_per_cycle; + + `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_req); + `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_req); + `POP_COUNT(perf_read_miss_per_cycle, perf_read_miss_per_bank); + `POP_COUNT(perf_write_miss_per_cycle, perf_write_miss_per_bank); + `POP_COUNT(perf_mshr_stall_per_cycle, perf_mshr_stall_per_bank); + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req); + `POP_COUNT(perf_mem_stall_per_cycle, perf_mem_stall_per_port); + + reg [PERF_CTR_BITS-1:0] perf_core_reads; + reg [PERF_CTR_BITS-1:0] perf_core_writes; + reg [PERF_CTR_BITS-1:0] perf_read_misses; + reg [PERF_CTR_BITS-1:0] perf_write_misses; + reg [PERF_CTR_BITS-1:0] perf_mshr_stalls; + reg [PERF_CTR_BITS-1:0] perf_mem_stalls; + reg [PERF_CTR_BITS-1:0] perf_crsp_stalls; + + always @(posedge clk) begin + if (reset) begin + perf_core_reads <= '0; + perf_core_writes <= '0; + perf_read_misses <= '0; + perf_write_misses <= '0; + perf_mshr_stalls <= '0; + perf_mem_stalls <= '0; + perf_crsp_stalls <= '0; + end else begin + perf_core_reads <= perf_core_reads + PERF_CTR_BITS'(perf_core_reads_per_cycle); + perf_core_writes <= perf_core_writes + PERF_CTR_BITS'(perf_core_writes_per_cycle); + perf_read_misses <= perf_read_misses + PERF_CTR_BITS'(perf_read_miss_per_cycle); + perf_write_misses <= perf_write_misses + PERF_CTR_BITS'(perf_write_miss_per_cycle); + perf_mshr_stalls <= perf_mshr_stalls + PERF_CTR_BITS'(perf_mshr_stall_per_cycle); + perf_mem_stalls <= perf_mem_stalls + PERF_CTR_BITS'(perf_mem_stall_per_cycle); + perf_crsp_stalls <= perf_crsp_stalls + PERF_CTR_BITS'(perf_crsp_stall_per_cycle); + end + end + + assign cache_perf.reads = perf_core_reads; + assign cache_perf.writes = perf_core_writes; + assign cache_perf.read_misses = perf_read_misses; + assign cache_perf.write_misses = perf_write_misses; + assign cache_perf.bank_stalls = perf_collisions; + assign cache_perf.mshr_stalls = perf_mshr_stalls; + assign cache_perf.mem_stalls = perf_mem_stalls; + assign cache_perf.crsp_stalls = perf_crsp_stalls; +`endif + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_bank.sv b/designs/src/vortex/rtl/cache/VX_cache_bank.sv new file mode 100644 index 0000000..2875724 --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_bank.sv @@ -0,0 +1,776 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_bank import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID= "", + parameter BANK_ID = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 4, + + // Core Response Queue Size + parameter CRSQ_SIZE = 1, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 1, + // Memory Request Queue Size + parameter MREQ_SIZE = 1, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Enable cache writeback + parameter WRITEBACK = 0, + + // Enable dirty bytes on writeback + parameter DIRTY_BYTES = 0, + + // Replacement policy + parameter REPL_POLICY = `CS_REPL_FIFO, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // Core response output register + parameter CORE_OUT_REG = 0, + + // Memory request output register + parameter MEM_OUT_REG = 0, + + parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE), + parameter MEM_TAG_WIDTH = UUID_WIDTH + MSHR_ADDR_WIDTH, + parameter REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS), + parameter WORD_SEL_WIDTH = `UP(`CS_WORD_SEL_BITS) +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire perf_read_miss, + output wire perf_write_miss, + output wire perf_mshr_stall, +`endif + + // Core Request + input wire core_req_valid, + input wire [`CS_LINE_ADDR_WIDTH-1:0] core_req_addr, + input wire core_req_rw, // write enable + input wire [WORD_SEL_WIDTH-1:0] core_req_wsel, // select the word in a cacheline, e.g. word size = 4 bytes, cacheline size = 64 bytes, it should have log(64/4)= 4 bits + input wire [WORD_SIZE-1:0] core_req_byteen,// which bytes in data to write + input wire [`CS_WORD_WIDTH-1:0] core_req_data, // data to be written + input wire [TAG_WIDTH-1:0] core_req_tag, // identifier of the request (request id) + input wire [REQ_SEL_WIDTH-1:0] core_req_idx, // index of the request in the core request array + input wire [`UP(MEM_FLAGS_WIDTH)-1:0] core_req_flags, + output wire core_req_ready, + + // Core Response + output wire core_rsp_valid, + output wire [`CS_WORD_WIDTH-1:0] core_rsp_data, + output wire [TAG_WIDTH-1:0] core_rsp_tag, + output wire [REQ_SEL_WIDTH-1:0] core_rsp_idx, + input wire core_rsp_ready, + + // Memory request + output wire mem_req_valid, + output wire [`CS_LINE_ADDR_WIDTH-1:0] mem_req_addr, + output wire mem_req_rw, + output wire [LINE_SIZE-1:0] mem_req_byteen, + output wire [`CS_LINE_WIDTH-1:0] mem_req_data, + output wire [MEM_TAG_WIDTH-1:0] mem_req_tag, + output wire [`UP(MEM_FLAGS_WIDTH)-1:0] mem_req_flags, + input wire mem_req_ready, + + // Memory response + input wire mem_rsp_valid, + input wire [`CS_LINE_WIDTH-1:0] mem_rsp_data, + input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready, + + // flush + input wire flush_begin, + input wire [`UP(UUID_WIDTH)-1:0] flush_uuid, + output wire flush_end +); + + localparam PIPELINE_STAGES = 2; + +`IGNORE_UNUSED_BEGIN + wire [`UP(UUID_WIDTH)-1:0] req_uuid_sel, req_uuid_st0, req_uuid_st1; +`IGNORE_UNUSED_END + + wire crsp_queue_stall; + wire mshr_alm_full; + wire mreq_queue_empty; + wire mreq_queue_alm_full; + + wire [`CS_LINE_ADDR_WIDTH-1:0] mem_rsp_addr; + + wire replay_valid; + wire [`CS_LINE_ADDR_WIDTH-1:0] replay_addr; + wire replay_rw; + wire [WORD_SEL_WIDTH-1:0] replay_wsel; + wire [WORD_SIZE-1:0] replay_byteen; + wire [`CS_WORD_WIDTH-1:0] replay_data; + wire [TAG_WIDTH-1:0] replay_tag; + wire [REQ_SEL_WIDTH-1:0] replay_idx; + wire [MSHR_ADDR_WIDTH-1:0] replay_id; + wire replay_ready; + + + wire valid_sel, valid_st0, valid_st1; + wire is_init_st0; + wire is_creq_st0, is_creq_st1; + wire is_fill_st0, is_fill_st1; + wire is_flush_st0, is_flush_st1; + wire [`CS_WAY_SEL_WIDTH-1:0] flush_way_st0, evict_way_st0; + wire [`CS_WAY_SEL_WIDTH-1:0] way_idx_st0, way_idx_st1; + + wire [`CS_LINE_ADDR_WIDTH-1:0] addr_sel, addr_st0, addr_st1; + wire [`CS_LINE_SEL_BITS-1:0] line_idx_sel, line_idx_st0, line_idx_st1; + wire [`CS_TAG_SEL_BITS-1:0] line_tag_st0, line_tag_st1; + wire [`CS_TAG_SEL_BITS-1:0] evict_tag_st0, evict_tag_st1; + wire rw_sel, rw_st0, rw_st1; + wire [WORD_SEL_WIDTH-1:0] word_idx_sel, word_idx_st0, word_idx_st1; + wire [WORD_SIZE-1:0] byteen_sel, byteen_st0, byteen_st1; + wire [REQ_SEL_WIDTH-1:0] req_idx_sel, req_idx_st0, req_idx_st1; + wire [TAG_WIDTH-1:0] tag_sel, tag_st0, tag_st1; + wire [`CS_WORD_WIDTH-1:0] write_word_st0, write_word_st1; + wire [`CS_LINE_WIDTH-1:0] data_sel, data_st0, data_st1; + wire [MSHR_ADDR_WIDTH-1:0] mshr_id_st0, mshr_id_st1; + wire [MSHR_ADDR_WIDTH-1:0] replay_id_st0; + wire is_dirty_st0, is_dirty_st1; + wire is_replay_st0, is_replay_st1; + wire is_hit_st0, is_hit_st1; + wire [`UP(MEM_FLAGS_WIDTH)-1:0] flags_sel, flags_st0, flags_st1; + wire mshr_pending_st0, mshr_pending_st1; + wire [MSHR_ADDR_WIDTH-1:0] mshr_previd_st0, mshr_previd_st1; + wire mshr_empty; + + wire flush_valid; + wire init_valid; + wire [`CS_LINE_SEL_BITS-1:0] flush_sel; + wire [`CS_WAY_SEL_WIDTH-1:0] flush_way; + wire flush_ready; + + // ensure we have no pending memory request in the bank + wire no_pending_req = ~valid_st0 && ~valid_st1 && mreq_queue_empty; + + VX_cache_flush #( + .BANK_ID (BANK_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WRITEBACK (WRITEBACK) + ) cache_flush ( + .clk (clk), + .reset (reset), + .flush_begin (flush_begin), + .flush_end (flush_end), + .flush_init (init_valid), + .flush_valid (flush_valid), + .flush_line (flush_sel), + .flush_way (flush_way), + .flush_ready (flush_ready), + .mshr_empty (mshr_empty), + .bank_empty (no_pending_req) + ); + + wire pipe_stall = crsp_queue_stall; + + // inputs arbitration: + // mshr replay has highest priority to maximize utilization since there is no miss. + // handle memory responses next to prevent deadlock with potential memory request from a miss. + // flush has precedence over core requests to ensure that the cache is in a consistent state. + wire replay_grant = ~init_valid; + wire replay_enable = replay_grant && replay_valid; + + wire fill_grant = ~init_valid && ~replay_enable; + wire fill_enable = fill_grant && mem_rsp_valid; + + wire flush_grant = ~init_valid && ~replay_enable && ~fill_enable; + wire flush_enable = flush_grant && flush_valid; + + wire creq_grant = ~init_valid && ~replay_enable && ~fill_enable && ~flush_enable; + wire creq_enable = creq_grant && core_req_valid; + + assign replay_ready = replay_grant + && ~(!WRITEBACK && replay_rw && mreq_queue_alm_full) // needed for writethrough + && ~pipe_stall; + + assign mem_rsp_ready = fill_grant + && ~(WRITEBACK && mreq_queue_alm_full) // needed for writeback + && ~pipe_stall; + + assign flush_ready = flush_grant + && ~(WRITEBACK && mreq_queue_alm_full) // needed for writeback + && ~pipe_stall; + + assign core_req_ready = creq_grant + && ~mreq_queue_alm_full // needed for fill requests + && ~mshr_alm_full // needed for mshr allocation + && ~pipe_stall; + + wire init_fire = init_valid; + wire replay_fire = replay_valid && replay_ready; + wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; + wire flush_fire = flush_valid && flush_ready; + wire core_req_fire = core_req_valid && core_req_ready; + + wire [MSHR_ADDR_WIDTH-1:0] mem_rsp_id = mem_rsp_tag[MSHR_ADDR_WIDTH-1:0]; + + wire [TAG_WIDTH-1:0] mem_rsp_tag_s; + if (TAG_WIDTH > MEM_TAG_WIDTH) begin : g_mem_rsp_tag_s_pad + assign mem_rsp_tag_s = {mem_rsp_tag, (TAG_WIDTH-MEM_TAG_WIDTH)'(1'b0)}; + end else begin : g_mem_rsp_tag_s_cut + assign mem_rsp_tag_s = mem_rsp_tag[MEM_TAG_WIDTH-1 -: TAG_WIDTH]; + `UNUSED_VAR (mem_rsp_tag) + end + + wire [TAG_WIDTH-1:0] flush_tag; + if (UUID_WIDTH != 0) begin : g_flush_tag_uuid + assign flush_tag = {flush_uuid, (TAG_WIDTH-UUID_WIDTH)'(1'b0)}; + end else begin : g_flush_tag_0 + `UNUSED_VAR (flush_uuid) + assign flush_tag = '0; + end + + assign valid_sel = init_fire || replay_fire || mem_rsp_fire || flush_fire || core_req_fire; + assign rw_sel = replay_valid ? replay_rw : core_req_rw; + assign byteen_sel = replay_valid ? replay_byteen : core_req_byteen; + assign addr_sel = (init_valid | flush_valid) ? `CS_LINE_ADDR_WIDTH'(flush_sel) : + (replay_valid ? replay_addr : (mem_rsp_valid ? mem_rsp_addr : core_req_addr)); + assign word_idx_sel= replay_valid ? replay_wsel : core_req_wsel; + assign req_idx_sel = replay_valid ? replay_idx : core_req_idx; + assign tag_sel = (init_valid | flush_valid) ? (flush_valid ? flush_tag : '0) : + (replay_valid ? replay_tag : (mem_rsp_valid ? mem_rsp_tag_s : core_req_tag)); + assign flags_sel = core_req_valid ? core_req_flags : '0; + + if (WRITE_ENABLE) begin : g_data_sel + for (genvar i = 0; i < `CS_LINE_WIDTH; ++i) begin : g_i + if (i < `CS_WORD_WIDTH) begin : g_lo + assign data_sel[i] = replay_valid ? replay_data[i] : (mem_rsp_valid ? mem_rsp_data[i] : core_req_data[i]); + end else begin : g_hi + assign data_sel[i] = mem_rsp_data[i]; // only the memory response fills the upper words of data_sel + end + end + end else begin : g_data_sel_ro + assign data_sel = mem_rsp_data; + `UNUSED_VAR (core_req_data) + `UNUSED_VAR (replay_data) + end + + if (UUID_WIDTH != 0) begin : g_req_uuid_sel + assign req_uuid_sel = tag_sel[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_req_uuid_sel_0 + assign req_uuid_sel = '0; + end + + wire is_init_sel = init_valid; + wire is_creq_sel = creq_enable || replay_enable; + wire is_fill_sel = fill_enable; + wire is_flush_sel = flush_enable; + wire is_replay_sel = replay_enable; + + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + `UP(MEM_FLAGS_WIDTH) + `CS_WAY_SEL_WIDTH + `CS_LINE_ADDR_WIDTH + `CS_LINE_WIDTH + 1 + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH), + .RESETW (1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (~pipe_stall), + .data_in ({valid_sel, is_init_sel, is_fill_sel, is_flush_sel, is_creq_sel, is_replay_sel, flags_sel, flush_way, addr_sel, data_sel, rw_sel, byteen_sel, word_idx_sel, req_idx_sel, tag_sel, replay_id}), + .data_out ({valid_st0, is_init_st0, is_fill_st0, is_flush_st0, is_creq_st0, is_replay_st0, flags_st0, flush_way_st0, addr_st0, data_st0, rw_st0, byteen_st0, word_idx_st0, req_idx_st0, tag_st0, replay_id_st0}) + ); + + if (UUID_WIDTH != 0) begin : g_req_uuid_st0 + assign req_uuid_st0 = tag_st0[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_req_uuid_st0_0 + assign req_uuid_st0 = '0; + end + + wire is_read_st0 = is_creq_st0 && ~rw_st0; + wire is_write_st0 = is_creq_st0 && rw_st0; + + wire do_init_st0 = valid_st0 && is_init_st0; + wire do_flush_st0 = valid_st0 && is_flush_st0; + wire do_read_st0 = valid_st0 && is_read_st0; + wire do_write_st0 = valid_st0 && is_write_st0; + wire do_fill_st0 = valid_st0 && is_fill_st0; + + wire is_read_st1 = is_creq_st1 && ~rw_st1; + wire is_write_st1 = is_creq_st1 && rw_st1; + + wire do_read_st1 = valid_st1 && is_read_st1; + wire do_write_st1 = valid_st1 && is_write_st1; + + assign line_idx_sel = addr_sel[`CS_LINE_SEL_BITS-1:0]; + assign line_idx_st0 = addr_st0[`CS_LINE_SEL_BITS-1:0]; + assign line_tag_st0 = `CS_LINE_ADDR_TAG(addr_st0); + + assign write_word_st0 = data_st0[`CS_WORD_WIDTH-1:0]; + + wire do_lookup_st0 = do_read_st0 || do_write_st0; + wire do_lookup_st1 = do_read_st1 || do_write_st1; + + wire [`CS_WAY_SEL_WIDTH-1:0] victim_way_st0; + wire [NUM_WAYS-1:0] tag_matches_st0; + + VX_cache_repl #( + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .REPL_POLICY (REPL_POLICY) + ) cache_repl ( + .clk (clk), + .reset (reset), + .stall (pipe_stall), + .init (do_init_st0), + .lookup_valid(do_lookup_st1 && ~pipe_stall), + .lookup_hit (is_hit_st1), + .lookup_line(line_idx_st1), + .lookup_way (way_idx_st1), + .repl_valid (do_fill_st0 && ~pipe_stall), + .repl_line (line_idx_st0), + .repl_way (victim_way_st0) + ); + + assign evict_way_st0 = is_fill_st0 ? victim_way_st0 : flush_way_st0; + + VX_cache_tags #( + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .WRITEBACK (WRITEBACK) + ) cache_tags ( + .clk (clk), + .reset (reset), + // inputs + .stall (pipe_stall), + .init (do_init_st0), + .flush (do_flush_st0 && ~pipe_stall), + .fill (do_fill_st0 && ~pipe_stall), + .read (do_read_st0 && ~pipe_stall), + .write (do_write_st0 && ~pipe_stall), + .line_idx (line_idx_st0), + .line_idx_n (line_idx_sel), + .line_tag (line_tag_st0), + .evict_way (evict_way_st0), + // outputs + .tag_matches(tag_matches_st0), + .evict_dirty(is_dirty_st0), + .evict_tag (evict_tag_st0) + ); + + wire [`CS_WAY_SEL_WIDTH-1:0] hit_idx_st0; + VX_onehot_encoder #( + .N (NUM_WAYS) + ) way_idx_enc ( + .data_in (tag_matches_st0), + .data_out (hit_idx_st0), + `UNUSED_PIN (valid_out) + ); + + assign way_idx_st0 = is_creq_st0 ? hit_idx_st0 : evict_way_st0; + assign is_hit_st0 = (| tag_matches_st0); + + wire [MSHR_ADDR_WIDTH-1:0] mshr_alloc_id_st0; + assign mshr_id_st0 = is_replay_st0 ? replay_id_st0 : mshr_alloc_id_st0; + + VX_pipe_register #( + .DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `UP(MEM_FLAGS_WIDTH) + `CS_WAY_SEL_WIDTH + `CS_TAG_SEL_BITS + `CS_TAG_SEL_BITS + `CS_LINE_SEL_BITS + `CS_LINE_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + REQ_SEL_WIDTH + TAG_WIDTH + MSHR_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1), + .RESETW (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (~pipe_stall), + .data_in ({valid_st0, is_fill_st0, is_flush_st0, is_creq_st0, is_replay_st0, is_dirty_st0, is_hit_st0, rw_st0, flags_st0, way_idx_st0, evict_tag_st0, line_tag_st0, line_idx_st0, data_st0, byteen_st0, word_idx_st0, req_idx_st0, tag_st0, mshr_id_st0, mshr_previd_st0, mshr_pending_st0}), + .data_out ({valid_st1, is_fill_st1, is_flush_st1, is_creq_st1, is_replay_st1, is_dirty_st1, is_hit_st1, rw_st1, flags_st1, way_idx_st1, evict_tag_st1, line_tag_st1, line_idx_st1, data_st1, byteen_st1, word_idx_st1, req_idx_st1, tag_st1, mshr_id_st1, mshr_previd_st1, mshr_pending_st1}) + ); + + if (UUID_WIDTH != 0) begin : g_req_uuid_st1 + assign req_uuid_st1 = tag_st1[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_req_uuid_st1_0 + assign req_uuid_st1 = '0; + end + + assign addr_st1 = {line_tag_st1, line_idx_st1}; + + // ensure mshr replay always get a hit + `RUNTIME_ASSERT (~(valid_st1 && is_replay_st1 && ~is_hit_st1), ("%t: missed mshr replay", $time)) + + assign write_word_st1 = data_st1[`CS_WORD_WIDTH-1:0]; + `UNUSED_VAR (data_st1) + + wire[`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] read_data_st1; + wire [LINE_SIZE-1:0] evict_byteen_st1; + + VX_cache_data #( + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .WRITE_ENABLE (WRITE_ENABLE), + .WRITEBACK (WRITEBACK), + .DIRTY_BYTES (DIRTY_BYTES) + ) cache_data ( + .clk (clk), + .reset (reset), + // inputs + .init (do_init_st0), + .fill (do_fill_st0 && ~pipe_stall), + .flush (do_flush_st0 && ~pipe_stall), + .read (do_read_st0 && ~pipe_stall), + .write (do_write_st0 && ~pipe_stall), + .evict_way (evict_way_st0), + .tag_matches(tag_matches_st0), + .line_idx (line_idx_st0), + .fill_data (data_st0), + .write_word (write_word_st0), + .word_idx (word_idx_st0), + .write_byteen(byteen_st0), + .way_idx_r (way_idx_st1), + // outputs + .read_data (read_data_st1), + .evict_byteen(evict_byteen_st1) + ); + + // only allocate MSHR entries for non-replay core requests + wire mshr_allocate_st0 = valid_st0 && is_creq_st0 && ~is_replay_st0; + wire mshr_finalize_st1 = valid_st1 && is_creq_st1 && ~is_replay_st1; + + // release allocated mshr entry if we had a hit + wire mshr_release_st1; + if (WRITEBACK) begin : g_mshr_release + assign mshr_release_st1 = is_hit_st1; + end else begin : g_mshr_release_ro + // we need to keep missed write requests in MSHR if there is already a pending entry to the same address. + // this ensures that missed write requests are replayed locally in case a pending fill arrives without the write content. + // this can happen when writes are sent to memory late, when a related fill was already in flight. + assign mshr_release_st1 = is_hit_st1 || (rw_st1 && ~mshr_pending_st1); + end + + wire mshr_release_fire = mshr_finalize_st1 && mshr_release_st1 && ~pipe_stall; + + wire [1:0] mshr_dequeue; + `POP_COUNT(mshr_dequeue, {replay_fire, mshr_release_fire}); + + VX_pending_size #( + .SIZE (MSHR_SIZE), + .DECRW (2) + ) mshr_pending_size ( + .clk (clk), + .reset (reset), + .incr (core_req_fire), + .decr (mshr_dequeue), + .empty (mshr_empty), + `UNUSED_PIN (alm_empty), + .full (mshr_alm_full), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + VX_cache_mshr #( + .INSTANCE_ID (`SFORMATF(("%s-mshr", INSTANCE_ID))), + .BANK_ID (BANK_ID), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .MSHR_SIZE (MSHR_SIZE), + .WRITEBACK (WRITEBACK), + .DATA_WIDTH (WORD_SEL_WIDTH + WORD_SIZE + `CS_WORD_WIDTH + TAG_WIDTH + REQ_SEL_WIDTH) + ) cache_mshr ( + .clk (clk), + .reset (reset), + + .deq_req_uuid (req_uuid_sel), + .alc_req_uuid (req_uuid_st0), + .fin_req_uuid (req_uuid_st1), + + // memory fill + .fill_valid (mem_rsp_fire), + .fill_id (mem_rsp_id), + .fill_addr (mem_rsp_addr), + + // dequeue + .dequeue_valid (replay_valid), + .dequeue_addr (replay_addr), + .dequeue_rw (replay_rw), + .dequeue_data ({replay_wsel, replay_byteen, replay_data, replay_tag, replay_idx}), + .dequeue_id (replay_id), + .dequeue_ready (replay_ready), + + // allocate + .allocate_valid (mshr_allocate_st0 && ~pipe_stall), + .allocate_addr (addr_st0), + .allocate_rw (rw_st0), + .allocate_data ({word_idx_st0, byteen_st0, write_word_st0, tag_st0, req_idx_st0}), + .allocate_id (mshr_alloc_id_st0), + .allocate_pending(mshr_pending_st0), + .allocate_previd(mshr_previd_st0), + `UNUSED_PIN (allocate_ready), + + // finalize + .finalize_valid (mshr_finalize_st1 && ~pipe_stall), + .finalize_is_release(mshr_release_st1), + .finalize_is_pending(mshr_pending_st1), + .finalize_id (mshr_id_st1), + .finalize_previd(mshr_previd_st1) + ); + + // schedule core response + + wire crsp_queue_valid, crsp_queue_ready; + wire [`CS_WORD_WIDTH-1:0] crsp_queue_data; + wire [REQ_SEL_WIDTH-1:0] crsp_queue_idx; + wire [TAG_WIDTH-1:0] crsp_queue_tag; + + assign crsp_queue_valid = do_read_st1 && is_hit_st1; + assign crsp_queue_idx = req_idx_st1; + assign crsp_queue_data = read_data_st1[word_idx_st1]; + assign crsp_queue_tag = tag_st1; + + VX_elastic_buffer #( + .DATAW (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH), + .SIZE (CRSQ_SIZE), + .OUT_REG (CORE_OUT_REG) + ) core_rsp_queue ( + .clk (clk), + .reset (reset), + .valid_in (crsp_queue_valid), + .ready_in (crsp_queue_ready), + .data_in ({crsp_queue_tag, crsp_queue_data, crsp_queue_idx}), + .data_out ({core_rsp_tag, core_rsp_data, core_rsp_idx}), + .valid_out (core_rsp_valid), + .ready_out (core_rsp_ready) + ); + + assign crsp_queue_stall = crsp_queue_valid && ~crsp_queue_ready; + + // schedule memory request + + wire mreq_queue_push, mreq_queue_pop; + wire [`CS_LINE_WIDTH-1:0] mreq_queue_data; + wire [LINE_SIZE-1:0] mreq_queue_byteen; + wire [`CS_LINE_ADDR_WIDTH-1:0] mreq_queue_addr; + wire [MEM_TAG_WIDTH-1:0] mreq_queue_tag; + wire mreq_queue_rw; + wire [`UP(MEM_FLAGS_WIDTH)-1:0] mreq_queue_flags; + + wire is_fill_or_flush_st1 = is_fill_st1 || (is_flush_st1 && WRITEBACK); + wire do_fill_or_flush_st1 = valid_st1 && is_fill_or_flush_st1; + wire do_writeback_st1 = do_fill_or_flush_st1 && is_dirty_st1; + wire [`CS_LINE_ADDR_WIDTH-1:0] evict_addr_st1 = {evict_tag_st1, line_idx_st1}; + + if (WRITE_ENABLE) begin : g_mreq_queue + if (WRITEBACK) begin : g_wb + if (DIRTY_BYTES) begin : g_dirty_bytes + // ensure dirty bytes match the tag info + wire has_dirty_bytes = (| evict_byteen_st1); + `RUNTIME_ASSERT (~do_fill_or_flush_st1 || (is_dirty_st1 == has_dirty_bytes), ("%t: missmatch dirty bytes: dirty_line=%b, dirty_bytes=%b, addr=0x%0h", $time, is_dirty_st1, has_dirty_bytes, `CS_BANK_TO_FULL_ADDR(addr_st1, BANK_ID))) + end + // issue a fill request on a read/write miss + // issue a writeback on a dirty line eviction + assign mreq_queue_push = ((do_lookup_st1 && ~is_hit_st1 && ~mshr_pending_st1) + || do_writeback_st1) + && ~pipe_stall; + assign mreq_queue_addr = is_fill_or_flush_st1 ? evict_addr_st1 : addr_st1; + assign mreq_queue_rw = is_fill_or_flush_st1; + assign mreq_queue_data = read_data_st1; + assign mreq_queue_byteen = is_fill_or_flush_st1 ? evict_byteen_st1 : '1; + `UNUSED_VAR (write_word_st1) + `UNUSED_VAR (byteen_st1) + end else begin : g_wt + wire [LINE_SIZE-1:0] line_byteen; + VX_demux #( + .DATAW (WORD_SIZE), + .N (`CS_WORDS_PER_LINE) + ) byteen_demux ( + .sel_in (word_idx_st1), + .data_in (byteen_st1), + .data_out (line_byteen) + ); + // issue a fill request on a read miss + // issue a memory write on a write request + assign mreq_queue_push = ((do_read_st1 && ~is_hit_st1 && ~mshr_pending_st1) + || do_write_st1) + && ~pipe_stall; + assign mreq_queue_addr = addr_st1; + assign mreq_queue_rw = rw_st1; + assign mreq_queue_data = {`CS_WORDS_PER_LINE{write_word_st1}}; + assign mreq_queue_byteen = rw_st1 ? line_byteen : '1; + `UNUSED_VAR (is_fill_or_flush_st1) + `UNUSED_VAR (do_writeback_st1) + `UNUSED_VAR (evict_addr_st1) + `UNUSED_VAR (evict_byteen_st1) + end + end else begin : g_mreq_queue_ro + // issue a fill request on a read miss + assign mreq_queue_push = (do_read_st1 && ~is_hit_st1 && ~mshr_pending_st1) + && ~pipe_stall; + assign mreq_queue_addr = addr_st1; + assign mreq_queue_rw = 0; + assign mreq_queue_data = '0; + assign mreq_queue_byteen = '1; + `UNUSED_VAR (do_writeback_st1) + `UNUSED_VAR (evict_addr_st1) + `UNUSED_VAR (evict_byteen_st1) + `UNUSED_VAR (write_word_st1) + `UNUSED_VAR (byteen_st1) + end + + if (UUID_WIDTH != 0) begin : g_mreq_queue_tag_uuid + assign mreq_queue_tag = {req_uuid_st1, mshr_id_st1}; + end else begin : g_mreq_queue_tag + assign mreq_queue_tag = mshr_id_st1; + end + + assign mreq_queue_pop = mem_req_valid && mem_req_ready; + assign mreq_queue_flags = flags_st1; + + VX_fifo_queue #( + .DATAW (1 + `CS_LINE_ADDR_WIDTH + LINE_SIZE + `CS_LINE_WIDTH + MEM_TAG_WIDTH + `UP(MEM_FLAGS_WIDTH)), + .DEPTH (MREQ_SIZE), + .ALM_FULL (MREQ_SIZE - PIPELINE_STAGES), + .OUT_REG (MEM_OUT_REG) + ) mem_req_queue ( + .clk (clk), + .reset (reset), + .push (mreq_queue_push), + .pop (mreq_queue_pop), + .data_in ({mreq_queue_rw, mreq_queue_addr, mreq_queue_byteen, mreq_queue_data, mreq_queue_tag, mreq_queue_flags}), + .data_out ({mem_req_rw, mem_req_addr, mem_req_byteen, mem_req_data, mem_req_tag, mem_req_flags}), + .empty (mreq_queue_empty), + .alm_full (mreq_queue_alm_full), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (size) + ); + + assign mem_req_valid = ~mreq_queue_empty; + + `UNUSED_VAR (do_lookup_st0) + +/////////////////////////////////////////////////////////////////////////////// + +`ifdef PERF_ENABLE + assign perf_read_miss = do_read_st1 && ~is_hit_st1; + assign perf_write_miss = do_write_st1 && ~is_hit_st1; + assign perf_mshr_stall = mshr_alm_full; +`endif + +`ifdef DBG_TRACE_CACHE + wire crsp_queue_fire = crsp_queue_valid && crsp_queue_ready; + wire input_stall = (replay_valid || mem_rsp_valid || core_req_valid || flush_valid) + && ~(replay_fire || mem_rsp_fire || core_req_fire || flush_fire); + + wire [`XLEN-1:0] mem_rsp_full_addr = `CS_BANK_TO_FULL_ADDR(mem_rsp_addr, BANK_ID); + wire [`XLEN-1:0] replay_full_addr = `CS_BANK_TO_FULL_ADDR(replay_addr, BANK_ID); + wire [`XLEN-1:0] core_req_full_addr = `CS_BANK_TO_FULL_ADDR(core_req_addr, BANK_ID); + wire [`XLEN-1:0] full_addr_st0 = `CS_BANK_TO_FULL_ADDR(addr_st0, BANK_ID); + wire [`XLEN-1:0] full_addr_st1 = `CS_BANK_TO_FULL_ADDR(addr_st1, BANK_ID); + wire [`XLEN-1:0] mreq_queue_full_addr = `CS_BANK_TO_FULL_ADDR(mreq_queue_addr, BANK_ID); + + always @(posedge clk) begin + if (input_stall || pipe_stall) begin + `TRACE(4, ("%t: *** %s stall: crsq=%b, mreq=%b, mshr=%b\n", $time, INSTANCE_ID, + crsp_queue_stall, mreq_queue_alm_full, mshr_alm_full)) + end + if (mem_rsp_fire) begin + `TRACE(2, ("%t: %s fill-rsp: addr=0x%0h, mshr_id=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + mem_rsp_full_addr, mem_rsp_id, mem_rsp_data, req_uuid_sel)) + end + if (replay_fire) begin + `TRACE(2, ("%t: %s mshr-pop: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, + replay_full_addr, replay_tag, replay_idx, req_uuid_sel)) + end + if (core_req_fire) begin + if (core_req_rw) begin + `TRACE(2, ("%t: %s core-wr-req: addr=0x%0h, tag=0x%0h, req_idx=%0d, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + core_req_full_addr, core_req_tag, core_req_idx, core_req_byteen, core_req_data, req_uuid_sel)) + end else begin + `TRACE(2, ("%t: %s core-rd-req: addr=0x%0h, tag=0x%0h, req_idx=%0d (#%0d)\n", $time, INSTANCE_ID, + core_req_full_addr, core_req_tag, core_req_idx, req_uuid_sel)) + end + end + if (do_init_st0) begin + `TRACE(3, ("%t: %s tags-init: addr=0x%0h, line=%0d\n", $time, INSTANCE_ID, full_addr_st0, line_idx_st0)) + end + if (do_fill_st0 && ~pipe_stall) begin + `TRACE(3, ("%t: %s tags-fill: addr=0x%0h, way=%0d, line=%0d, dirty=%b (#%0d)\n", $time, INSTANCE_ID, + full_addr_st0, evict_way_st0, line_idx_st0, is_dirty_st0, req_uuid_st0)) + end + if (do_flush_st0 && ~pipe_stall) begin + `TRACE(3, ("%t: %s tags-flush: addr=0x%0h, way=%0d, line=%0d, dirty=%b (#%0d)\n", $time, INSTANCE_ID, + full_addr_st0, evict_way_st0, line_idx_st0, is_dirty_st0, req_uuid_st0)) + end + if (do_lookup_st0 && ~pipe_stall) begin + if (is_hit_st0) begin + `TRACE(3, ("%t: %s tags-hit: addr=0x%0h, rw=%b, way=%0d, line=%0d, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, + full_addr_st0, rw_st0, way_idx_st0, line_idx_st0, line_tag_st0, req_uuid_st0)) + end else begin + `TRACE(3, ("%t: %s tags-miss: addr=0x%0h, rw=%b, way=%0d, line=%0d, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, + full_addr_st0, rw_st0, way_idx_st0, line_idx_st0, line_tag_st0, req_uuid_st0)) + end + end + if (do_fill_st0 && ~pipe_stall) begin + `TRACE(3, ("%t: %s data-fill: addr=0x%0h, way=%0d, line=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + full_addr_st0, way_idx_st0, line_idx_st0, data_st0, req_uuid_st0)) + end + if (do_flush_st0 && ~pipe_stall) begin + `TRACE(3, ("%t: %s data-flush: addr=0x%0h, way=%0d, line=%0d (#%0d)\n", $time, INSTANCE_ID, + full_addr_st0, way_idx_st0, line_idx_st0, req_uuid_st0)) + end + if (do_read_st1 && is_hit_st1 && ~pipe_stall) begin + `TRACE(3, ("%t: %s data-read: addr=0x%0h, way=%0d, line=%0d, wsel=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + full_addr_st1, way_idx_st1, line_idx_st1, word_idx_st1, crsp_queue_data, req_uuid_st1)) + end + if (do_write_st1 && is_hit_st1 && ~pipe_stall) begin + `TRACE(3, ("%t: %s data-write: addr=0x%0h, way=%0d, line=%0d, wsel=%0d, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + full_addr_st1, way_idx_st1, line_idx_st1, word_idx_st1, byteen_st1, write_word_st1, req_uuid_st1)) + end + if (crsp_queue_fire) begin + `TRACE(2, ("%t: %s core-rd-rsp: addr=0x%0h, tag=0x%0h, req_idx=%0d, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + full_addr_st1, crsp_queue_tag, crsp_queue_idx, crsp_queue_data, req_uuid_st1)) + end + if (mreq_queue_push) begin + if (!WRITEBACK && do_write_st1) begin + `TRACE(2, ("%t: %s writethrough: addr=0x%0h, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + mreq_queue_full_addr, mreq_queue_byteen, mreq_queue_data, req_uuid_st1)) + end else if (WRITEBACK && do_writeback_st1) begin + `TRACE(2, ("%t: %s writeback: addr=0x%0h, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, + mreq_queue_full_addr, mreq_queue_byteen, mreq_queue_data, req_uuid_st1)) + end else begin + `TRACE(2, ("%t: %s fill-req: addr=0x%0h, mshr_id=%0d (#%0d)\n", $time, INSTANCE_ID, + mreq_queue_full_addr, mshr_id_st1, req_uuid_st1)) + end + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_bypass.sv b/designs/src/vortex/rtl/cache/VX_cache_bypass.sv new file mode 100644 index 0000000..43646ff --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_bypass.sv @@ -0,0 +1,264 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_bypass import VX_gpu_pkg::*; #( + parameter NUM_REQS = 1, + parameter MEM_PORTS = 1, + parameter TAG_SEL_IDX = 0, + + parameter CACHE_ENABLE = 0, + + parameter WORD_SIZE = 1, + parameter LINE_SIZE = 1, + + parameter CORE_ADDR_WIDTH = 1, + + parameter CORE_TAG_WIDTH = 1, + + parameter MEM_ADDR_WIDTH = 1, + parameter MEM_TAG_IN_WIDTH = 1, + + parameter CORE_OUT_BUF = 0, + parameter MEM_OUT_BUF = 0 + ) ( + input wire clk, + input wire reset, + + // Core request in + VX_mem_bus_if.slave core_bus_in_if [NUM_REQS], + + // Core request out + VX_mem_bus_if.master core_bus_out_if [NUM_REQS], + + // Memory request in + VX_mem_bus_if.slave mem_bus_in_if [MEM_PORTS], + + // Memory request out + VX_mem_bus_if.master mem_bus_out_if [MEM_PORTS] +); + localparam DIRECT_PASSTHRU = !CACHE_ENABLE && (`CS_WORD_SEL_BITS == 0) && (NUM_REQS == MEM_PORTS); + localparam CORE_DATA_WIDTH = WORD_SIZE * 8; + localparam WORDS_PER_LINE = LINE_SIZE / WORD_SIZE; + localparam WSEL_BITS = `CLOG2(WORDS_PER_LINE); + + localparam CORE_TAG_ID_WIDTH = CORE_TAG_WIDTH - UUID_WIDTH; + localparam MEM_TAG_ID_WIDTH = `CLOG2(`CDIV(NUM_REQS, MEM_PORTS)) + CORE_TAG_ID_WIDTH; + localparam MEM_TAG_NC1_WIDTH = UUID_WIDTH + MEM_TAG_ID_WIDTH; + localparam MEM_TAG_NC2_WIDTH = MEM_TAG_NC1_WIDTH + WSEL_BITS; + localparam MEM_TAG_OUT_WIDTH = CACHE_ENABLE ? `MAX(MEM_TAG_IN_WIDTH, MEM_TAG_NC2_WIDTH) : MEM_TAG_NC2_WIDTH; + + `STATIC_ASSERT(0 == (`IO_BASE_ADDR % `MEM_BLOCK_SIZE), ("invalid parameter")) + + // hanlde non-cacheable core request switch /////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (CORE_TAG_WIDTH) + ) core_bus_nc_switch_if[(CACHE_ENABLE ? 2 : 1) * NUM_REQS](); + + wire [NUM_REQS-1:0] core_req_nc_sel; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_req_is_nc + if (CACHE_ENABLE) begin : g_cache + assign core_req_nc_sel[i] = ~core_bus_in_if[i].req_data.flags[MEM_REQ_FLAG_IO]; + end else begin : g_no_cache + assign core_req_nc_sel[i] = 1'b0; + end + end + + VX_mem_switch #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS ((CACHE_ENABLE ? 2 : 1) * NUM_REQS), + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (CORE_TAG_WIDTH), + .ARBITER ("R"), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (DIRECT_PASSTHRU ? 0 : `TO_OUT_BUF_SIZE(CORE_OUT_BUF)) + ) core_bus_nc_switch ( + .clk (clk), + .reset (reset), + .bus_sel (core_req_nc_sel), + .bus_in_if (core_bus_in_if), + .bus_out_if(core_bus_nc_switch_if) + ); + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (CORE_TAG_WIDTH) + ) core_bus_in_nc_if[NUM_REQS](); + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_nc_switch_if + + assign core_bus_in_nc_if[i].req_valid = core_bus_nc_switch_if[0 * NUM_REQS + i].req_valid; + assign core_bus_in_nc_if[i].req_data = core_bus_nc_switch_if[0 * NUM_REQS + i].req_data; + assign core_bus_nc_switch_if[0 * NUM_REQS + i].req_ready = core_bus_in_nc_if[i].req_ready; + + assign core_bus_nc_switch_if[0 * NUM_REQS + i].rsp_valid = core_bus_in_nc_if[i].rsp_valid; + assign core_bus_nc_switch_if[0 * NUM_REQS + i].rsp_data = core_bus_in_nc_if[i].rsp_data; + assign core_bus_in_nc_if[i].rsp_ready = core_bus_nc_switch_if[0 * NUM_REQS + i].rsp_ready; + + if (CACHE_ENABLE) begin : g_cache + assign core_bus_out_if[i].req_valid = core_bus_nc_switch_if[1 * NUM_REQS + i].req_valid; + assign core_bus_out_if[i].req_data = core_bus_nc_switch_if[1 * NUM_REQS + i].req_data; + assign core_bus_nc_switch_if[1 * NUM_REQS + i].req_ready = core_bus_out_if[i].req_ready; + + assign core_bus_nc_switch_if[1 * NUM_REQS + i].rsp_valid = core_bus_out_if[i].rsp_valid; + assign core_bus_nc_switch_if[1 * NUM_REQS + i].rsp_data = core_bus_out_if[i].rsp_data; + assign core_bus_out_if[i].rsp_ready = core_bus_nc_switch_if[1 * NUM_REQS + i].rsp_ready; + end else begin : g_no_cache + `INIT_VX_MEM_BUS_IF (core_bus_out_if[i]) + end + end + + // handle memory requests ///////////////////////////////////////////////// + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (MEM_TAG_NC1_WIDTH) + ) core_bus_nc_arb_if[MEM_PORTS](); + + VX_mem_arb #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS(MEM_PORTS), + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (CORE_TAG_WIDTH), + .TAG_SEL_IDX(TAG_SEL_IDX), + .ARBITER (CACHE_ENABLE ? "P" : "R"), + .REQ_OUT_BUF(0), + .RSP_OUT_BUF(0) + ) core_bus_nc_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (core_bus_in_nc_if), + .bus_out_if (core_bus_nc_arb_if) + ); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_NC2_WIDTH) + ) mem_bus_out_nc_if[MEM_PORTS](); + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_bus_out_nc + wire core_req_nc_arb_rw; + wire [WORD_SIZE-1:0] core_req_nc_arb_byteen; + wire [CORE_ADDR_WIDTH-1:0] core_req_nc_arb_addr; + wire [MEM_FLAGS_WIDTH-1:0] core_req_nc_arb_flags; + wire [CORE_DATA_WIDTH-1:0] core_req_nc_arb_data; + wire [MEM_TAG_NC1_WIDTH-1:0] core_req_nc_arb_tag; + + assign { + core_req_nc_arb_rw, + core_req_nc_arb_addr, + core_req_nc_arb_data, + core_req_nc_arb_byteen, + core_req_nc_arb_flags, + core_req_nc_arb_tag + } = core_bus_nc_arb_if[i].req_data; + + logic [MEM_ADDR_WIDTH-1:0] core_req_nc_arb_addr_w; + logic [WORDS_PER_LINE-1:0][WORD_SIZE-1:0] core_req_nc_arb_byteen_w; + logic [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] core_req_nc_arb_data_w; + logic [CORE_DATA_WIDTH-1:0] core_rsp_nc_arb_data_w; + wire [MEM_TAG_NC2_WIDTH-1:0] core_req_nc_arb_tag_w; + wire [MEM_TAG_NC1_WIDTH-1:0] core_rsp_nc_arb_tag_w; + + if (WORDS_PER_LINE > 1) begin : g_multi_word_line + wire [WSEL_BITS-1:0] rsp_wsel; + wire [WSEL_BITS-1:0] req_wsel = core_req_nc_arb_addr[WSEL_BITS-1:0]; + always @(*) begin + core_req_nc_arb_byteen_w = '0; + core_req_nc_arb_byteen_w[req_wsel] = core_req_nc_arb_byteen; + core_req_nc_arb_data_w = 'x; + core_req_nc_arb_data_w[req_wsel] = core_req_nc_arb_data; + end + VX_bits_insert #( + .N (MEM_TAG_NC1_WIDTH), + .S (WSEL_BITS), + .POS (TAG_SEL_IDX) + ) wsel_insert ( + .data_in (core_req_nc_arb_tag), + .ins_in (req_wsel), + .data_out (core_req_nc_arb_tag_w) + ); + VX_bits_remove #( + .N (MEM_TAG_NC2_WIDTH), + .S (WSEL_BITS), + .POS (TAG_SEL_IDX) + ) wsel_remove ( + .data_in (mem_bus_out_nc_if[i].rsp_data.tag), + .sel_out (rsp_wsel), + .data_out (core_rsp_nc_arb_tag_w) + ); + assign core_req_nc_arb_addr_w = core_req_nc_arb_addr[WSEL_BITS +: MEM_ADDR_WIDTH]; + assign core_rsp_nc_arb_data_w = mem_bus_out_nc_if[i].rsp_data.data[rsp_wsel * CORE_DATA_WIDTH +: CORE_DATA_WIDTH]; + end else begin : g_single_word_line + assign core_req_nc_arb_addr_w = core_req_nc_arb_addr; + assign core_req_nc_arb_byteen_w = core_req_nc_arb_byteen; + assign core_req_nc_arb_data_w = core_req_nc_arb_data; + assign core_req_nc_arb_tag_w = MEM_TAG_NC2_WIDTH'(core_req_nc_arb_tag); + + assign core_rsp_nc_arb_data_w = mem_bus_out_nc_if[i].rsp_data.data; + assign core_rsp_nc_arb_tag_w = MEM_TAG_NC1_WIDTH'(mem_bus_out_nc_if[i].rsp_data.tag); + end + + assign mem_bus_out_nc_if[i].req_valid = core_bus_nc_arb_if[i].req_valid; + assign mem_bus_out_nc_if[i].req_data = { + core_req_nc_arb_rw, + core_req_nc_arb_addr_w, + core_req_nc_arb_data_w, + core_req_nc_arb_byteen_w, + core_req_nc_arb_flags, + core_req_nc_arb_tag_w + }; + assign core_bus_nc_arb_if[i].req_ready = mem_bus_out_nc_if[i].req_ready; + + assign core_bus_nc_arb_if[i].rsp_valid = mem_bus_out_nc_if[i].rsp_valid; + assign core_bus_nc_arb_if[i].rsp_data = { + core_rsp_nc_arb_data_w, + core_rsp_nc_arb_tag_w + }; + assign mem_bus_out_nc_if[i].rsp_ready = core_bus_nc_arb_if[i].rsp_ready; + end + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_OUT_WIDTH) + ) mem_bus_out_src_if[(CACHE_ENABLE ? 2 : 1) * MEM_PORTS](); + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_bus_out_src + `ASSIGN_VX_MEM_BUS_IF_EX(mem_bus_out_src_if[0 * MEM_PORTS + i], mem_bus_out_nc_if[i], MEM_TAG_OUT_WIDTH, MEM_TAG_NC2_WIDTH, UUID_WIDTH); + if (CACHE_ENABLE) begin : g_cache + `ASSIGN_VX_MEM_BUS_IF_EX(mem_bus_out_src_if[1 * MEM_PORTS + i], mem_bus_in_if[i], MEM_TAG_OUT_WIDTH, MEM_TAG_IN_WIDTH, UUID_WIDTH); + end else begin : g_no_cache + `UNUSED_VX_MEM_BUS_IF(mem_bus_in_if[i]) + end + end + + VX_mem_arb #( + .NUM_INPUTS ((CACHE_ENABLE ? 2 : 1) * MEM_PORTS), + .NUM_OUTPUTS(MEM_PORTS), + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_OUT_WIDTH), + .ARBITER ("R"), + .REQ_OUT_BUF(DIRECT_PASSTHRU ? 0 : `TO_OUT_BUF_SIZE(MEM_OUT_BUF)), + .RSP_OUT_BUF(0) + ) mem_bus_out_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (mem_bus_out_src_if), + .bus_out_if (mem_bus_out_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_cluster.sv b/designs/src/vortex/rtl/cache/VX_cache_cluster.sv new file mode 100644 index 0000000..ba1f20e --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_cluster.sv @@ -0,0 +1,219 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_cluster import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + + parameter NUM_UNITS = 1, + parameter NUM_INPUTS = 1, + parameter TAG_SEL_IDX = 0, + + // Number of requests per cycle + parameter NUM_REQS = 4, + + // Number of memory ports + parameter MEM_PORTS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 32768, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 4, + // Number of associative ways + parameter NUM_WAYS = 4, + // Size of a word in bytes + parameter WORD_SIZE = 16, + + // Core Response Queue Size + parameter CRSQ_SIZE = 4, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 16, + // Memory Response Queue Size + parameter MRSQ_SIZE = 4, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Enable cache writeback + parameter WRITEBACK = 0, + + // Enable dirty bytes on writeback + parameter DIRTY_BYTES = 0, + + // Replacement policy + parameter REPL_POLICY = `CS_REPL_FIFO, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // enable bypass for non-cacheable addresses + parameter NC_ENABLE = 0, + + // Core response output buffer + parameter CORE_OUT_BUF = 3, + + // Memory request output buffer + parameter MEM_OUT_BUF = 3 + ) ( + input wire clk, + input wire reset, + + // PERF +`ifdef PERF_ENABLE + output cache_perf_t cache_perf, +`endif + + VX_mem_bus_if.slave core_bus_if [NUM_INPUTS * NUM_REQS], + VX_mem_bus_if.master mem_bus_if [MEM_PORTS] +); + localparam NUM_CACHES = `UP(NUM_UNITS); + localparam PASSTHRU = (NUM_UNITS == 0); + localparam ARB_TAG_WIDTH = TAG_WIDTH + `ARB_SEL_BITS(NUM_INPUTS, NUM_CACHES); + + localparam CACHE_MEM_TAG_WIDTH = `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, MEM_PORTS, UUID_WIDTH); + localparam BYPASS_TAG_WIDTH = `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, MEM_PORTS, LINE_SIZE, WORD_SIZE, ARB_TAG_WIDTH); + localparam NC_TAG_WIDTH = `MAX(CACHE_MEM_TAG_WIDTH, BYPASS_TAG_WIDTH) + 1; + localparam MEM_TAG_WIDTH = PASSTHRU ? BYPASS_TAG_WIDTH : (NC_ENABLE ? NC_TAG_WIDTH : CACHE_MEM_TAG_WIDTH); + + `STATIC_ASSERT(NUM_INPUTS >= NUM_CACHES, ("invalid parameter")) + +`ifdef PERF_ENABLE + cache_perf_t perf_cache_unit[NUM_CACHES]; + `PERF_CACHE_ADD (cache_perf, perf_cache_unit, NUM_CACHES) +`endif + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) cache_mem_bus_if[NUM_CACHES * MEM_PORTS](); + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (ARB_TAG_WIDTH) + ) arb_core_bus_if[NUM_CACHES * NUM_REQS](); + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_arb + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH) + ) core_bus_tmp_if[NUM_INPUTS](); + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (ARB_TAG_WIDTH) + ) arb_core_bus_tmp_if[NUM_CACHES](); + + for (genvar j = 0; j < NUM_INPUTS; ++j) begin : g_core_bus_tmp_if + `ASSIGN_VX_MEM_BUS_IF (core_bus_tmp_if[j], core_bus_if[j * NUM_REQS + i]); + end + + VX_mem_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_CACHES), + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .TAG_SEL_IDX (TAG_SEL_IDX), + .ARBITER ("R"), + .REQ_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? 2 : 0), + .RSP_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? CORE_OUT_BUF : 0) + ) core_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (core_bus_tmp_if), + .bus_out_if (arb_core_bus_tmp_if) + ); + + for (genvar k = 0; k < NUM_CACHES; ++k) begin : g_arb_core_bus_if + `ASSIGN_VX_MEM_BUS_IF (arb_core_bus_if[k * NUM_REQS + i], arb_core_bus_tmp_if[k]); + end + end + + for (genvar i = 0; i < NUM_CACHES; ++i) begin : g_cache_wrap + VX_cache_wrap #( + .INSTANCE_ID (`SFORMATF(("%s%0d", INSTANCE_ID, i))), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .MEM_PORTS (MEM_PORTS), + .WRITE_ENABLE (WRITE_ENABLE), + .WRITEBACK (WRITEBACK), + .DIRTY_BYTES (DIRTY_BYTES), + .REPL_POLICY (REPL_POLICY), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MRSQ_SIZE (MRSQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .TAG_WIDTH (ARB_TAG_WIDTH), + .TAG_SEL_IDX (TAG_SEL_IDX), + .CORE_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? 2 : CORE_OUT_BUF), + .MEM_OUT_BUF ((NUM_CACHES > 1) ? 2 : MEM_OUT_BUF), + .NC_ENABLE (NC_ENABLE), + .PASSTHRU (PASSTHRU) + ) cache_wrap ( + `ifdef PERF_ENABLE + .cache_perf (perf_cache_unit[i]), + `endif + .clk (clk), + .reset (reset), + .core_bus_if (arb_core_bus_if[i * NUM_REQS +: NUM_REQS]), + .mem_bus_if (cache_mem_bus_if[i * MEM_PORTS +: MEM_PORTS]) + ); + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_bus_if + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) arb_core_bus_tmp_if[NUM_CACHES](); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH + `ARB_SEL_BITS(NUM_CACHES, 1)) + ) mem_bus_tmp_if[1](); + + for (genvar j = 0; j < NUM_CACHES; ++j) begin : g_arb_core_bus_tmp_if + `ASSIGN_VX_MEM_BUS_IF (arb_core_bus_tmp_if[j], cache_mem_bus_if[j * MEM_PORTS + i]); + end + + VX_mem_arb #( + .NUM_INPUTS (NUM_CACHES), + .NUM_OUTPUTS (1), + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH), + .TAG_SEL_IDX (TAG_SEL_IDX), + .ARBITER ("R"), + .REQ_OUT_BUF ((NUM_CACHES > 1) ? MEM_OUT_BUF : 0), + .RSP_OUT_BUF ((NUM_CACHES > 1) ? 2 : 0) + ) mem_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (arb_core_bus_tmp_if), + .bus_out_if (mem_bus_tmp_if) + ); + + if (WRITE_ENABLE) begin : g_we + `ASSIGN_VX_MEM_BUS_IF (mem_bus_if[i], mem_bus_tmp_if[0]); + end else begin : g_ro + `ASSIGN_VX_MEM_BUS_RO_IF (mem_bus_if[i], mem_bus_tmp_if[0]); + end + end + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_data.sv b/designs/src/vortex/rtl/cache/VX_cache_data.sv new file mode 100644 index 0000000..5fa9f9d --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_data.sv @@ -0,0 +1,144 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_data import VX_gpu_pkg::*; #( + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // Enable cache writeable + parameter WRITE_ENABLE = 1, + // Enable cache writeback + parameter WRITEBACK = 0, + // Enable dirty bytes on writeback + parameter DIRTY_BYTES = 0 +) ( + input wire clk, + input wire reset, + // inputs + input wire init, + input wire fill, + input wire flush, + input wire read, + input wire write, + input wire [`CS_LINE_SEL_BITS-1:0] line_idx, + input wire [`CS_WAY_SEL_WIDTH-1:0] evict_way, + input wire [NUM_WAYS-1:0] tag_matches, + input wire [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] fill_data, + input wire [`CS_WORD_WIDTH-1:0] write_word, + input wire [WORD_SIZE-1:0] write_byteen, + input wire [`UP(`CS_WORD_SEL_BITS)-1:0] word_idx, + input wire [`CS_WAY_SEL_WIDTH-1:0] way_idx_r, + // outputs + output wire [`CS_LINE_WIDTH-1:0] read_data, + output wire [LINE_SIZE-1:0] evict_byteen +); + `UNUSED_PARAM (WORD_SIZE) + + wire [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_mask; + for (genvar i = 0; i < `CS_WORDS_PER_LINE; ++i) begin : g_write_mask + wire word_en = (`CS_WORDS_PER_LINE == 1) || (word_idx == i); + assign write_mask[i] = write_byteen & {WORD_SIZE{word_en}}; + end + + if (DIRTY_BYTES != 0) begin : g_dirty_bytes + + wire [NUM_WAYS-1:0][LINE_SIZE-1:0] byteen_rdata; + + for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_byteen_store + wire [LINE_SIZE-1:0] byteen_wdata = {LINE_SIZE{write}}; // only asserted on writes + wire [LINE_SIZE-1:0] byteen_wren = {LINE_SIZE{init || fill || flush}} | write_mask; + wire byteen_write = ((fill || flush) && ((NUM_WAYS == 1) || (evict_way == i))) + || (write && tag_matches[i]) + || init; + wire byteen_read = fill || flush; + + VX_sp_ram #( + .DATAW (LINE_SIZE), + .WRENW (LINE_SIZE), + .SIZE (`CS_LINES_PER_BANK), + .OUT_REG (1), + .RDW_MODE ("R") + ) byteen_store ( + .clk (clk), + .reset (reset), + .read (byteen_read), + .write (byteen_write), + .wren (byteen_wren), + .addr (line_idx), + .wdata (byteen_wdata), + .rdata (byteen_rdata[i]) + ); + end + + assign evict_byteen = byteen_rdata[way_idx_r]; + + end else begin : g_no_dirty_bytes + `UNUSED_VAR (init) + `UNUSED_VAR (flush) + assign evict_byteen = '1; // update whole line + end + + wire [NUM_WAYS-1:0][`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] line_rdata; + + for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_data_store + + localparam WRENW = WRITE_ENABLE ? LINE_SIZE : 1; + + wire [`CS_WORDS_PER_LINE-1:0][`CS_WORD_WIDTH-1:0] line_wdata; + wire [WRENW-1:0] line_wren; + + if (WRITE_ENABLE) begin : g_wren + assign line_wdata = fill ? fill_data : {`CS_WORDS_PER_LINE{write_word}}; + assign line_wren = {LINE_SIZE{fill}} | write_mask; + end else begin : g_no_wren + `UNUSED_VAR (write_word) + `UNUSED_VAR (write_mask) + assign line_wdata = fill_data; + assign line_wren = 1'b1; + end + + wire line_write = (fill && ((NUM_WAYS == 1) || (evict_way == i))) + || (write && tag_matches[i] && WRITE_ENABLE); + + wire line_read = read || ((fill || flush) && WRITEBACK); + + VX_sp_ram #( + .DATAW (`CS_LINE_WIDTH), + .SIZE (`CS_LINES_PER_BANK), + .WRENW (WRENW), + .OUT_REG (1), + .RDW_MODE ("R") + ) data_store ( + .clk (clk), + .reset (reset), + .read (line_read), + .write (line_write), + .wren (line_wren), + .addr (line_idx), + .wdata (line_wdata), + .rdata (line_rdata[i]) + ); + end + + assign read_data = line_rdata[way_idx_r]; + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_define.vh b/designs/src/vortex/rtl/cache/VX_cache_define.vh new file mode 100644 index 0000000..10e888a --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_define.vh @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_CACHE_DEFINE_VH +`define VX_CACHE_DEFINE_VH + +`include "VX_define.vh" + +`define CS_REQ_SEL_BITS `CLOG2(NUM_REQS) + +`define CS_WORD_WIDTH (8 * WORD_SIZE) +`define CS_LINE_WIDTH (8 * LINE_SIZE) +`define CS_BANK_SIZE (CACHE_SIZE / NUM_BANKS) +`define CS_WAY_SEL_BITS `CLOG2(NUM_WAYS) +`define CS_WAY_SEL_WIDTH `UP(`CS_WAY_SEL_BITS) + +`define CS_LINES_PER_BANK (`CS_BANK_SIZE / (LINE_SIZE * NUM_WAYS)) +`define CS_WORDS_PER_LINE (LINE_SIZE / WORD_SIZE) + +`define CS_WORD_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(WORD_SIZE)) +`define CS_MEM_ADDR_WIDTH (`MEM_ADDR_WIDTH-`CLOG2(LINE_SIZE)) +`define CS_LINE_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH-`CLOG2(NUM_BANKS)) + +// Word select +`define CS_WORD_SEL_BITS `CLOG2(`CS_WORDS_PER_LINE) +`define CS_WORD_SEL_ADDR_START 0 +`define CS_WORD_SEL_ADDR_END (`CS_WORD_SEL_ADDR_START+`CS_WORD_SEL_BITS-1) + +// Bank select +`define CS_BANK_SEL_BITS `CLOG2(NUM_BANKS) +`define CS_BANK_SEL_ADDR_START (1+`CS_WORD_SEL_ADDR_END) +`define CS_BANK_SEL_ADDR_END (`CS_BANK_SEL_ADDR_START+`CS_BANK_SEL_BITS-1) + +// Line select +`define CS_LINE_SEL_BITS `CLOG2(`CS_LINES_PER_BANK) +`define CS_LINE_SEL_ADDR_START (1+`CS_BANK_SEL_ADDR_END) +`define CS_LINE_SEL_ADDR_END (`CS_LINE_SEL_ADDR_START+`CS_LINE_SEL_BITS-1) + +// Tag select +`define CS_TAG_SEL_BITS (`CS_WORD_ADDR_WIDTH-1-`CS_LINE_SEL_ADDR_END) +`define CS_TAG_SEL_ADDR_START (1+`CS_LINE_SEL_ADDR_END) +`define CS_TAG_SEL_ADDR_END (`CS_WORD_ADDR_WIDTH-1) + +`define CS_LINE_ADDR_TAG(x) x[`CS_LINE_ADDR_WIDTH-1 : `CS_LINE_SEL_BITS] + +/////////////////////////////////////////////////////////////////////////////// + +`define CS_BANK_TO_FULL_ADDR(x, b) {x, (`XLEN-$bits(x))'(b << (`XLEN-$bits(x)-`CS_BANK_SEL_BITS))} +`define CS_MEM_TO_FULL_ADDR(x) {x, (`XLEN-$bits(x))'(0)} + +/////////////////////////////////////////////////////////////////////////////// + +`define PERF_CACHE_ADD(dst, src, count) \ + `PERF_COUNTER_ADD (dst, src, reads, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, writes, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, read_misses, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, write_misses, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, bank_stalls, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, mshr_stalls, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, mem_stalls, PERF_CTR_BITS, count, (count > 1)) \ + `PERF_COUNTER_ADD (dst, src, crsp_stalls, PERF_CTR_BITS, count, (count > 1)) + +/////////////////////////////////////////////////////////////////////////////// + +`define CS_REPL_RANDOM 0 +`define CS_REPL_FIFO 1 +`define CS_REPL_PLRU 2 + +`endif // VX_CACHE_DEFINE_VH diff --git a/designs/src/vortex/rtl/cache/VX_cache_flush.sv b/designs/src/vortex/rtl/cache/VX_cache_flush.sv new file mode 100644 index 0000000..24eb31d --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_flush.sv @@ -0,0 +1,123 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_flush import VX_gpu_pkg::*; #( + parameter BANK_ID = 0, + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Enable cache writeback + parameter WRITEBACK = 0 +) ( + input wire clk, + input wire reset, + input wire flush_begin, + output wire flush_end, + output wire flush_init, + output wire flush_valid, + output wire [`CS_LINE_SEL_BITS-1:0] flush_line, + output wire [`CS_WAY_SEL_WIDTH-1:0] flush_way, + input wire flush_ready, + input wire mshr_empty, + input wire bank_empty +); + // ways interation is only needed when eviction is enabled + localparam CTR_WIDTH = `CS_LINE_SEL_BITS + (WRITEBACK ? `CS_WAY_SEL_BITS : 0); + + localparam STATE_IDLE = 0; + localparam STATE_INIT = 1; + localparam STATE_WAIT1 = 2; + localparam STATE_FLUSH = 3; + localparam STATE_WAIT2 = 4; + localparam STATE_DONE = 5; + + reg [2:0] state, state_n; + + reg [CTR_WIDTH-1:0] counter; + + always @(*) begin + state_n = state; + case (state) + // STATE_IDLE: + default : begin + if (flush_begin) begin + state_n = STATE_WAIT1; + end + end + STATE_INIT: begin + if (counter == ((2 ** `CS_LINE_SEL_BITS)-1)) begin + state_n = STATE_IDLE; + end + end + STATE_WAIT1: begin + // wait for pending requests to complete + if (mshr_empty) begin + state_n = STATE_FLUSH; + end + end + STATE_FLUSH: begin + if (counter == ((2 ** CTR_WIDTH)-1) && flush_ready) begin + state_n = (BANK_ID == 0) ? STATE_DONE : STATE_WAIT2; + end + end + STATE_WAIT2: begin + // ensure the bank is empty before notifying the cache flush unit, + // because the flush request to lower caches only goes through bank0 + // and it is important that request gets send out last. + if (bank_empty) begin + state_n = STATE_DONE; + end + end + STATE_DONE: begin + // generate a completion pulse + state_n = STATE_IDLE; + end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= STATE_INIT; + counter <= '0; + end else begin + state <= state_n; + if (state != STATE_IDLE) begin + if ((state == STATE_INIT) + || ((state == STATE_FLUSH) && flush_ready)) begin + counter <= counter + CTR_WIDTH'(1); + end + end else begin + counter <= '0; + end + end + end + + assign flush_end = (state == STATE_DONE); + assign flush_init = (state == STATE_INIT); + assign flush_valid = (state == STATE_FLUSH); + assign flush_line = counter[`CS_LINE_SEL_BITS-1:0]; + + if (WRITEBACK && (NUM_WAYS > 1)) begin : g_flush_way + assign flush_way = counter[`CS_LINE_SEL_BITS +: `CS_WAY_SEL_BITS]; + end else begin : g_flush_way_all + assign flush_way = '0; + end + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_init.sv b/designs/src/vortex/rtl/cache/VX_cache_init.sv new file mode 100644 index 0000000..fd39c31 --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_init.sv @@ -0,0 +1,189 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_init import VX_gpu_pkg::*; #( + // Number of Word requests per cycle + parameter NUM_REQS = 4, + // Number of banks + parameter NUM_BANKS = 1, + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + // Bank select latency + parameter BANK_SEL_LATENCY = 1 +) ( + input wire clk, + input wire reset, + VX_mem_bus_if.slave core_bus_in_if [NUM_REQS], + VX_mem_bus_if.master core_bus_out_if [NUM_REQS], + input wire [NUM_BANKS-1:0] bank_req_fire, + output wire [NUM_BANKS-1:0] flush_begin, + output wire [`UP(UUID_WIDTH)-1:0] flush_uuid, + input wire [NUM_BANKS-1:0] flush_end +); + `UNUSED_PARAM (TAG_WIDTH) + + localparam STATE_IDLE = 0; + localparam STATE_WAIT1 = 1; + localparam STATE_FLUSH = 2; + localparam STATE_WAIT2 = 3; + localparam STATE_DONE = 4; + + reg [2:0] state, state_n; + + // track in-flight core requests + + wire no_inflight_reqs; + + if (BANK_SEL_LATENCY != 0) begin : g_bank_sel_latency + + localparam NUM_REQS_W = `CLOG2(NUM_REQS+1); + localparam NUM_BANKS_W = `CLOG2(NUM_BANKS+1); + + wire [NUM_REQS-1:0] core_bus_out_fire; + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_fire + assign core_bus_out_fire[i] = core_bus_out_if[i].req_valid && core_bus_out_if[i].req_ready; + end + + wire [NUM_REQS_W-1:0] core_bus_out_cnt; + wire [NUM_BANKS_W-1:0] bank_req_cnt; + + `POP_COUNT(core_bus_out_cnt, core_bus_out_fire); + `POP_COUNT(bank_req_cnt, bank_req_fire); + `UNUSED_VAR (core_bus_out_cnt) + + VX_pending_size #( + .SIZE (BANK_SEL_LATENCY * NUM_BANKS), + .INCRW (NUM_BANKS_W), + .DECRW (NUM_BANKS_W) + ) pending_size ( + .clk (clk), + .reset (reset), + .incr (NUM_BANKS_W'(core_bus_out_cnt)), + .decr (bank_req_cnt), + .empty (no_inflight_reqs), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + end else begin : g_no_bank_sel_latency + assign no_inflight_reqs = 0; + `UNUSED_VAR (bank_req_fire) + end + + reg [NUM_BANKS-1:0] flush_done, flush_done_n; + + wire [NUM_REQS-1:0] flush_req_mask; + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_flush_req_mask + assign flush_req_mask[i] = core_bus_in_if[i].req_valid && core_bus_in_if[i].req_data.flags[MEM_REQ_FLAG_FLUSH]; + end + wire flush_req_enable = (| flush_req_mask); + + reg [NUM_REQS-1:0] lock_released, lock_released_n; + reg [`UP(UUID_WIDTH)-1:0] flush_uuid_r, flush_uuid_n; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_req + wire input_enable = ~flush_req_enable || lock_released[i]; + assign core_bus_out_if[i].req_valid = core_bus_in_if[i].req_valid && input_enable; + assign core_bus_out_if[i].req_data = core_bus_in_if[i].req_data; + assign core_bus_in_if[i].req_ready = core_bus_out_if[i].req_ready && input_enable; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_in_rsp + assign core_bus_in_if[i].rsp_valid = core_bus_out_if[i].rsp_valid; + assign core_bus_in_if[i].rsp_data = core_bus_out_if[i].rsp_data; + assign core_bus_out_if[i].rsp_ready = core_bus_in_if[i].rsp_ready; + end + + reg [NUM_REQS-1:0][`UP(UUID_WIDTH)-1:0] core_bus_out_uuid; + wire [NUM_REQS-1:0] core_bus_out_ready; + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_uuid + if (UUID_WIDTH != 0) begin : g_uuid + assign core_bus_out_uuid[i] = core_bus_in_if[i].req_data.tag.uuid; + end else begin : g_no_uuid + assign core_bus_out_uuid[i] = 0; + end + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_out_ready + assign core_bus_out_ready[i] = core_bus_out_if[i].req_ready; + end + + always @(*) begin + state_n = state; + flush_done_n = flush_done; + lock_released_n = lock_released; + flush_uuid_n = flush_uuid_r; + case (state) + // STATE_IDLE: + default: begin + if (flush_req_enable) begin + state_n = (BANK_SEL_LATENCY != 0) ? STATE_WAIT1 : STATE_FLUSH; + for (integer i = NUM_REQS-1; i >= 0; --i) begin + if (flush_req_mask[i]) begin + flush_uuid_n = core_bus_out_uuid[i]; + end + end + end + end + STATE_WAIT1: begin + if (no_inflight_reqs) begin + state_n = STATE_FLUSH; + end + end + STATE_FLUSH: begin + // generate a flush request pulse + state_n = STATE_WAIT2; + end + STATE_WAIT2: begin + // wait for all banks to finish flushing + flush_done_n = flush_done | flush_end; + if (flush_done_n == {NUM_BANKS{1'b1}}) begin + state_n = STATE_DONE; + flush_done_n = '0; + // only release current flush requests + // and keep normal requests locked + lock_released_n = flush_req_mask; + end + end + STATE_DONE: begin + // wait until released flush requests are issued + // when returning to IDLE state other requests will unlock + lock_released_n = lock_released & ~core_bus_out_ready; + if (lock_released_n == 0) begin + state_n = STATE_IDLE; + end + end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= STATE_IDLE; + flush_done <= '0; + lock_released <= '0; + end else begin + state <= state_n; + flush_done <= flush_done_n; + lock_released <= lock_released_n; + end + flush_uuid_r <= flush_uuid_n; + end + + assign flush_begin = {NUM_BANKS{state == STATE_FLUSH}}; + assign flush_uuid = flush_uuid_r; + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_mshr.sv b/designs/src/vortex/rtl/cache/VX_cache_mshr.sv new file mode 100644 index 0000000..d9a01d5 --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_mshr.sv @@ -0,0 +1,300 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +// This is an implementation of a MSHR for pipelined multi-banked cache. +// We allocate a free slot from the MSHR before processing a core request +// and release the slot when we get a cache hit. This ensure that we do not +// enter the cache bank pipeline when the MSHR is full. +// During a memory fill response, we initiate the replay sequence +// and dequeue all pending entries for the given cache line. +// +// Pending core requests stored in the MSHR are sorted by the order of +// arrival and are dequeued in the same order. +// Each entry has a next pointer to the next entry pending for the same cache line. +// +// During the fill request, the MSHR will dequue the MSHR entry at the fill_id location +// which represents the first request in the pending list that initiated the memory fill. +// +// The dequeue response directly follows the fill request and will release +// all the subsequent entries linked to fill_id (pending the same cache line). +// +// During the allocation request, the MSHR will allocate the next free slot +// for the incoming core request. We return the allocated slot id as well as +// the slot id of the previous entry for the same cache line. This is used to +// link the new entry to the pending list. +// +// The finalize request is used to persit or release the currently allocated MSHR entry +// if we had a cache miss or a hit, respectively. +// +// Warning: This MSHR implementation is strongly coupled with the bank pipeline +// and as such changes to either module requires careful evaluation. +// + +module VX_cache_mshr import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID= "", + parameter BANK_ID = 0, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 4, + // MSHR parameters + parameter DATA_WIDTH = 1, + // Enable cache writeback + parameter WRITEBACK = 0, + + parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE) +) ( + input wire clk, + input wire reset, + +`IGNORE_UNUSED_BEGIN + input wire[`UP(UUID_WIDTH)-1:0] deq_req_uuid, + input wire[`UP(UUID_WIDTH)-1:0] alc_req_uuid, + input wire[`UP(UUID_WIDTH)-1:0] fin_req_uuid, +`IGNORE_UNUSED_END + + // memory fill + input wire fill_valid, + input wire [MSHR_ADDR_WIDTH-1:0] fill_id, + output wire [`CS_LINE_ADDR_WIDTH-1:0] fill_addr, + + // dequeue + output wire dequeue_valid, + output wire [`CS_LINE_ADDR_WIDTH-1:0] dequeue_addr, + output wire dequeue_rw, + output wire [DATA_WIDTH-1:0] dequeue_data, + output wire [MSHR_ADDR_WIDTH-1:0] dequeue_id, + input wire dequeue_ready, + + // allocate + input wire allocate_valid, + input wire [`CS_LINE_ADDR_WIDTH-1:0] allocate_addr, + input wire allocate_rw, + input wire [DATA_WIDTH-1:0] allocate_data, + output wire [MSHR_ADDR_WIDTH-1:0] allocate_id, + output wire allocate_pending, + output wire [MSHR_ADDR_WIDTH-1:0] allocate_previd, + output wire allocate_ready, + + // finalize + input wire finalize_valid, + input wire finalize_is_release, + input wire finalize_is_pending, + input wire [MSHR_ADDR_WIDTH-1:0] finalize_previd, + input wire [MSHR_ADDR_WIDTH-1:0] finalize_id +); + `UNUSED_PARAM (BANK_ID) + + reg [`CS_LINE_ADDR_WIDTH-1:0] addr_table [0:MSHR_SIZE-1]; + reg [MSHR_ADDR_WIDTH-1:0] next_index [0:MSHR_SIZE-1]; + + reg [MSHR_SIZE-1:0] valid_table, valid_table_n; + reg [MSHR_SIZE-1:0] next_table, next_table_x, next_table_n; + reg [MSHR_SIZE-1:0] write_table; + + reg allocate_rdy, allocate_rdy_n; + reg [MSHR_ADDR_WIDTH-1:0] allocate_id_r, allocate_id_n; + + reg dequeue_val, dequeue_val_n; + reg [MSHR_ADDR_WIDTH-1:0] dequeue_id_r, dequeue_id_n; + + wire [MSHR_ADDR_WIDTH-1:0] prev_idx; + + wire allocate_fire = allocate_valid && allocate_ready; + wire dequeue_fire = dequeue_valid && dequeue_ready; + + wire [MSHR_SIZE-1:0] addr_matches; + for (genvar i = 0; i < MSHR_SIZE; ++i) begin : g_addr_matches + assign addr_matches[i] = valid_table[i] && (addr_table[i] == allocate_addr); + end + + VX_priority_encoder #( + .N (MSHR_SIZE) + ) allocate_sel ( + .data_in (~valid_table_n), + .index_out (allocate_id_n), + .valid_out (allocate_rdy_n), + `UNUSED_PIN (onehot_out) + ); + + // find matching tail-entry + VX_priority_encoder #( + .N (MSHR_SIZE) + ) prev_sel ( + .data_in (addr_matches & ~next_table_x), + .index_out (prev_idx), + `UNUSED_PIN (valid_out), + `UNUSED_PIN (onehot_out) + ); + + always @(*) begin + valid_table_n = valid_table; + next_table_x = next_table; + dequeue_val_n = dequeue_val; + dequeue_id_n = dequeue_id; + + if (fill_valid) begin + dequeue_val_n = 1; + dequeue_id_n = fill_id; + end + + if (dequeue_fire) begin + valid_table_n[dequeue_id] = 0; + if (next_table[dequeue_id]) begin + dequeue_id_n = next_index[dequeue_id]; + end else if (finalize_valid && finalize_is_pending && (finalize_previd == dequeue_id)) begin + dequeue_id_n = finalize_id; + end else begin + dequeue_val_n = 0; + end + end + + if (finalize_valid) begin + if (finalize_is_release) begin + valid_table_n[finalize_id] = 0; + end + // warning: This code allows 'finalize_is_pending' to be asserted regardless of hit/miss + // to reduce the its propagation delay into the MSHR. this is safe because wrong updates + // to 'next_table_n' will be cleared during 'allocate_fire' below. + if (finalize_is_pending) begin + next_table_x[finalize_previd] = 1; + end + end + + next_table_n = next_table_x; + if (allocate_fire) begin + valid_table_n[allocate_id] = 1; + next_table_n[allocate_id] = 0; + end + end + + always @(posedge clk) begin + if (reset) begin + valid_table <= '0; + allocate_rdy <= 0; + dequeue_val <= 0; + end else begin + valid_table <= valid_table_n; + allocate_rdy <= allocate_rdy_n; + dequeue_val <= dequeue_val_n; + end + + if (allocate_fire) begin + addr_table[allocate_id] <= allocate_addr; + write_table[allocate_id] <= allocate_rw; + end + + if (finalize_valid && finalize_is_pending) begin + next_index[finalize_previd] <= finalize_id; + end + + dequeue_id_r <= dequeue_id_n; + allocate_id_r <= allocate_id_n; + next_table <= next_table_n; + end + + `RUNTIME_ASSERT(~(allocate_fire && valid_table[allocate_id_r]), ("%t: *** %s inuse allocation: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, + `CS_BANK_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id_r, alc_req_uuid)) + + `RUNTIME_ASSERT(~(finalize_valid && ~valid_table[finalize_id]), ("%t: *** %s invalid release: addr=0x%0h, id=%0d (#%0d)", $time, INSTANCE_ID, + `CS_BANK_TO_FULL_ADDR(addr_table[finalize_id], BANK_ID), finalize_id, fin_req_uuid)) + + `RUNTIME_ASSERT(~(fill_valid && ~valid_table[fill_id]), ("%t: *** %s invalid fill: addr=0x%0h, id=%0d", $time, INSTANCE_ID, + `CS_BANK_TO_FULL_ADDR(addr_table[fill_id], BANK_ID), fill_id)) + + VX_dp_ram #( + .DATAW (DATA_WIDTH), + .SIZE (MSHR_SIZE), + .RDW_MODE ("R"), + .RADDR_REG (1) + ) mshr_store ( + .clk (clk), + .reset (reset), + .read (1'b1), + .write (allocate_valid), + .wren (1'b1), + .waddr (allocate_id_r), + .wdata (allocate_data), + .raddr (dequeue_id_r), + .rdata (dequeue_data) + ); + + assign fill_addr = addr_table[fill_id]; + + assign allocate_ready = allocate_rdy; + assign allocate_id = allocate_id_r; + assign allocate_previd = prev_idx; + + if (WRITEBACK) begin : g_pending_wb + assign allocate_pending = |addr_matches; + end else begin : g_pending_wt + // exclude write requests if writethrough + assign allocate_pending = |(addr_matches & ~write_table); + end + + assign dequeue_valid = dequeue_val; + assign dequeue_addr = addr_table[dequeue_id_r]; + assign dequeue_rw = write_table[dequeue_id_r]; + assign dequeue_id = dequeue_id_r; + +`ifdef DBG_TRACE_CACHE + reg show_table; + always @(posedge clk) begin + if (reset) begin + show_table <= 0; + end else begin + show_table <= allocate_fire || finalize_valid || fill_valid || dequeue_fire; + end + if (allocate_fire) begin + `TRACE(3, ("%t: %s allocate: addr=0x%0h, id=%0d, pending=%b, prev=%0d (#%0d)\n", $time, INSTANCE_ID, + `CS_BANK_TO_FULL_ADDR(allocate_addr, BANK_ID), allocate_id, allocate_pending, prev_idx, alc_req_uuid)) + end + if (finalize_valid && finalize_is_release) begin + `TRACE(3, ("%t: %s release: id=%0d (#%0d)\n", $time, INSTANCE_ID, finalize_id, fin_req_uuid)) + end + if (finalize_valid && finalize_is_pending) begin + `TRACE(3, ("%t: %s finalize: id=%0d (#%0d)\n", $time, INSTANCE_ID, finalize_id, fin_req_uuid)) + end + if (fill_valid) begin + `TRACE(3, ("%t: %s fill: addr=0x%0h, id=%0d\n", $time, INSTANCE_ID, + `CS_BANK_TO_FULL_ADDR(fill_addr, BANK_ID), fill_id)) + end + if (dequeue_fire) begin + `TRACE(3, ("%t: %s dequeue: addr=0x%0h, id=%0d (#%0d)\n", $time, INSTANCE_ID, + `CS_BANK_TO_FULL_ADDR(dequeue_addr, BANK_ID), dequeue_id_r, deq_req_uuid)) + end + if (show_table) begin + `TRACE(3, ("%t: %s table", $time, INSTANCE_ID)) + for (integer i = 0; i < MSHR_SIZE; ++i) begin + if (valid_table[i]) begin + `TRACE(3, (" %0d=0x%0h", i, `CS_BANK_TO_FULL_ADDR(addr_table[i], BANK_ID))) + if (write_table[i]) begin + `TRACE(3, ("(w)")) + end else begin + `TRACE(3, ("(r)")) + end + if (next_table[i]) begin + `TRACE(3, ("->%0d", next_index[i])) + end + end + end + `TRACE(3, ("\n")) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_repl.sv b/designs/src/vortex/rtl/cache/VX_cache_repl.sv new file mode 100644 index 0000000..7cba692 --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_repl.sv @@ -0,0 +1,210 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +// Fast PLRU encoder and decoder utility +// Adapted from BaseJump STL: http://bjump.org/data_out.html + +module plru_decoder import VX_gpu_pkg::*; #( + parameter NUM_WAYS = 1, + parameter WAY_IDX_BITS = $clog2(NUM_WAYS), + parameter WAY_IDX_WIDTH = `UP(WAY_IDX_BITS) +) ( + input wire [WAY_IDX_WIDTH-1:0] way_idx, + output wire [`UP(NUM_WAYS-1)-1:0] lru_data, + output wire [`UP(NUM_WAYS-1)-1:0] lru_mask +); + if (NUM_WAYS > 1) begin : g_dec + wire [`UP(NUM_WAYS-1)-1:0] data; + `IGNORE_UNOPTFLAT_BEGIN + wire [`UP(NUM_WAYS-1)-1:0] mask; + `IGNORE_UNOPTFLAT_END + for (genvar i = 0; i < NUM_WAYS-1; ++i) begin : g_i + if (i == 0) begin : g_i_0 + assign mask[i] = 1'b1; + end else if (i % 2 == 1) begin : g_i_odd + assign mask[i] = mask[(i-1)/2] & ~way_idx[WAY_IDX_BITS-$clog2(i+2)+1]; + end else begin : g_i_even + assign mask[i] = mask[(i-2)/2] & way_idx[WAY_IDX_BITS-$clog2(i+2)+1]; + end + assign data[i] = ~way_idx[WAY_IDX_BITS-$clog2(i+2)]; + end + assign lru_data = data; + assign lru_mask = mask; + end else begin : g_no_dec + `UNUSED_VAR (way_idx) + assign lru_data = '0; + assign lru_mask = '0; + end + +endmodule + +module plru_encoder #( + parameter NUM_WAYS = 1, + parameter WAY_IDX_BITS = $clog2(NUM_WAYS), + parameter WAY_IDX_WIDTH = `UP(WAY_IDX_BITS) +) ( + input wire [`UP(NUM_WAYS-1)-1:0] lru_in, + output wire [WAY_IDX_WIDTH-1:0] way_idx +); + if (NUM_WAYS > 1) begin : g_enc + wire [WAY_IDX_BITS-1:0] tmp; + for (genvar i = 0; i < WAY_IDX_BITS; ++i) begin : g_i + if (i == 0) begin : g_i_0 + assign tmp[WAY_IDX_WIDTH-1] = lru_in[0]; + end else begin : g_i_n + VX_mux #( + .N (2**i) + ) mux ( + .data_in (lru_in[((2**i)-1)+:(2**i)]), + .sel_in (tmp[WAY_IDX_BITS-1-:i]), + .data_out (tmp[WAY_IDX_BITS-1-i]) + ); + end + end + assign way_idx = tmp; + end else begin : g_no_enc + `UNUSED_VAR (lru_in) + assign way_idx = '0; + end + +endmodule + +module VX_cache_repl #( + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // replacement policy + parameter REPL_POLICY = `CS_REPL_FIFO +) ( + input wire clk, + input wire reset, + input wire stall, + input wire init, + input wire lookup_valid, + input wire lookup_hit, + input wire [`CS_LINE_SEL_BITS-1:0] lookup_line, + input wire [`CS_WAY_SEL_WIDTH-1:0] lookup_way, + input wire repl_valid, + input wire [`CS_LINE_SEL_BITS-1:0] repl_line, + output wire [`CS_WAY_SEL_WIDTH-1:0] repl_way +); + localparam WAY_SEL_WIDTH = `CS_WAY_SEL_WIDTH; + `UNUSED_VAR (reset) + `UNUSED_VAR (init) + `UNUSED_VAR (stall) + + if (NUM_WAYS > 1) begin : g_enable + if (REPL_POLICY == `CS_REPL_PLRU) begin : g_plru + // Pseudo Least Recently Used replacement policy + localparam LRU_WIDTH = `UP(NUM_WAYS-1); + + wire [LRU_WIDTH-1:0] plru_rdata; + wire [LRU_WIDTH-1:0] plru_wdata; + wire [LRU_WIDTH-1:0] plru_wmask; + + VX_dp_ram #( + .DATAW (LRU_WIDTH), + .SIZE (`CS_LINES_PER_BANK), + .WRENW (LRU_WIDTH), + .RDW_MODE ("R"), + .RADDR_REG (1) + ) plru_store ( + .clk (clk), + .reset (1'b0), + .read (repl_valid), + .write (init || (lookup_valid && lookup_hit)), + .wren (init ? '1 : plru_wmask), + .waddr (lookup_line), + .raddr (repl_line), + .wdata (init ? '0 : plru_wdata), + .rdata (plru_rdata) + ); + + plru_decoder #( + .NUM_WAYS (NUM_WAYS) + ) plru_dec ( + .way_idx (lookup_way), + .lru_data (plru_wdata), + .lru_mask (plru_wmask) + ); + + plru_encoder #( + .NUM_WAYS (NUM_WAYS) + ) plru_enc ( + .lru_in (plru_rdata), + .way_idx (repl_way) + ); + + end else if (REPL_POLICY == `CS_REPL_FIFO) begin : g_fifo + // Fifo replacement policy + `UNUSED_VAR (lookup_valid) + `UNUSED_VAR (lookup_hit) + `UNUSED_VAR (lookup_line) + `UNUSED_VAR (lookup_way) + + wire [WAY_SEL_WIDTH-1:0] fifo_rdata; + wire [WAY_SEL_WIDTH-1:0] fifo_wdata = fifo_rdata + 1; + + VX_sp_ram #( + .DATAW (WAY_SEL_WIDTH), + .SIZE (`CS_LINES_PER_BANK), + .RDW_MODE ("R"), + .RADDR_REG (1) + ) fifo_store ( + .clk (clk), + .reset (1'b0), + .read (repl_valid), + .write (init || repl_valid), + .wren (1'b1), + .addr (repl_line), + .wdata (init ? '0 : fifo_wdata), + .rdata (fifo_rdata) + ); + + assign repl_way = fifo_rdata; + end else begin : g_random + // Random replacement policy + `UNUSED_VAR (lookup_valid) + `UNUSED_VAR (lookup_hit) + `UNUSED_VAR (lookup_line) + `UNUSED_VAR (lookup_way) + `UNUSED_VAR (repl_valid) + `UNUSED_VAR (repl_line) + reg [WAY_SEL_WIDTH-1:0] victim_idx; + always @(posedge clk) begin + if (reset) begin + victim_idx <= 0; + end else if (~stall) begin + victim_idx <= victim_idx + 1; + end + end + assign repl_way = victim_idx; + end + end else begin : g_disable + `UNUSED_VAR (clk) + `UNUSED_VAR (lookup_valid) + `UNUSED_VAR (lookup_hit) + `UNUSED_VAR (lookup_line) + `UNUSED_VAR (lookup_way) + `UNUSED_VAR (repl_valid) + `UNUSED_VAR (repl_line) + assign repl_way = 1'b0; + end + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_tags.sv b/designs/src/vortex/rtl/cache/VX_cache_tags.sv new file mode 100644 index 0000000..7eeaffe --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_tags.sv @@ -0,0 +1,119 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_tags import VX_gpu_pkg::*; #( + // Size of cache in bytes + parameter CACHE_SIZE = 1024, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 16, + // Number of banks + parameter NUM_BANKS = 1, + // Number of associative ways + parameter NUM_WAYS = 1, + // Size of a word in bytes + parameter WORD_SIZE = 1, + // Enable cache writeback + parameter WRITEBACK = 0 +) ( + input wire clk, + input wire reset, + + // inputs + input wire stall, + input wire init, + input wire flush, + input wire fill, + input wire read, + input wire write, + input wire [`CS_LINE_SEL_BITS-1:0] line_idx, + input wire [`CS_LINE_SEL_BITS-1:0] line_idx_n, + input wire [`CS_TAG_SEL_BITS-1:0] line_tag, + input wire [`CS_WAY_SEL_WIDTH-1:0] evict_way, + + // outputs + output wire [NUM_WAYS-1:0] tag_matches, + output wire evict_dirty, + output wire [`CS_TAG_SEL_BITS-1:0] evict_tag +); + // valid, dirty, tag + localparam TAG_WIDTH = 1 + WRITEBACK + `CS_TAG_SEL_BITS; + + wire [NUM_WAYS-1:0][`CS_TAG_SEL_BITS-1:0] read_tag; + wire [NUM_WAYS-1:0] read_valid; + wire [NUM_WAYS-1:0] read_dirty; + `UNUSED_VAR (read) + + if (WRITEBACK) begin : g_evict_tag_wb + assign evict_dirty = read_dirty[evict_way]; + assign evict_tag = read_tag[evict_way]; + end else begin : g_evict_tag_wt + `UNUSED_VAR (read_dirty) + assign evict_dirty = 1'b0; + assign evict_tag = '0; + end + + for (genvar i = 0; i < NUM_WAYS; ++i) begin : g_tag_store + wire way_en = (NUM_WAYS == 1) || (evict_way == i); + wire do_init = init; // init all ways + wire do_fill = fill && way_en; + wire do_flush = flush && (!WRITEBACK || way_en); // flush all ways in writethrough mode + wire do_write = WRITEBACK && write && tag_matches[i]; // only write on tag hit + + //wire line_read = read || write || (WRITEBACK && (fill || flush)); + wire line_write = do_init || do_fill || do_flush || do_write; + wire line_valid = fill || write; + + wire [TAG_WIDTH-1:0] line_wdata, line_rdata; + + // This module uses a Read-First block RAM with Read-During-Write hazard not supported. + // Fill requests are always followed by MSHR replays that hit the cache. + // In Writeback mode, writes requests can be followed by Fill/flush requests reading the dirty bit. + wire rdw_fill, rdw_write; + `BUFFER(rdw_fill, do_fill); + `BUFFER(rdw_write, do_write && (line_idx == line_idx_n)); + + if (WRITEBACK) begin : g_wdata + assign line_wdata = {line_valid, write, line_tag}; + assign read_tag[i] = line_rdata[0 +: `CS_TAG_SEL_BITS]; + assign read_dirty[i] = line_rdata[`CS_TAG_SEL_BITS] || rdw_write; + assign read_valid[i] = line_rdata[`CS_TAG_SEL_BITS+1]; + end else begin : g_wdata + `UNUSED_VAR (rdw_write) + assign line_wdata = {line_valid, line_tag}; + assign {read_valid[i], read_tag[i]} = line_rdata; + assign read_dirty[i] = 1'b0; + end + + VX_dp_ram #( + .DATAW (TAG_WIDTH), + .SIZE (`CS_LINES_PER_BANK), + .OUT_REG (1), + .RDW_MODE ("R") + ) tag_store ( + .clk (clk), + .reset (reset), + .read (~stall), + .write (line_write), + .wren (1'b1), + .waddr (line_idx), + .raddr (line_idx_n), + .wdata (line_wdata), + .rdata (line_rdata) + ); + + assign tag_matches[i] = (read_valid[i] && (line_tag == read_tag[i])) || rdw_fill; + end + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_top.sv b/designs/src/vortex/rtl/cache/VX_cache_top.sv new file mode 100644 index 0000000..f637306 --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_top.sv @@ -0,0 +1,182 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_top import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + + // Number of memory ports + parameter MEM_PORTS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 65536, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 4, + // Number of associative ways + parameter NUM_WAYS = 4, + // Size of a word in bytes + parameter WORD_SIZE = 16, + + // Core Response Queue Size + parameter CRSQ_SIZE = 8, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 16, + // Memory Response Queue Size + parameter MRSQ_SIZE = 8, + // Memory Request Queue Size + parameter MREQ_SIZE = 8, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Enable cache writeback + parameter WRITEBACK = 1, + + // Enable dirty bytes on writeback + parameter DIRTY_BYTES = 1, + + // core request tag size + parameter TAG_WIDTH = 32, + + // Core response output buffer + parameter CORE_OUT_BUF = 3, + + // Memory request output buffer + parameter MEM_OUT_BUF = 3, + + parameter MEM_TAG_WIDTH = `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, MEM_PORTS, UUID_WIDTH) + ) ( + input wire clk, + input wire reset, + +// PERF +`ifdef PERF_ENABLE + output cache_perf_t cache_perf, +`endif + + // Core request + input wire core_req_valid [NUM_REQS], + input wire core_req_rw [NUM_REQS], + input wire[WORD_SIZE-1:0] core_req_byteen [NUM_REQS], + input wire[`CS_WORD_ADDR_WIDTH-1:0] core_req_addr [NUM_REQS], + input wire[MEM_FLAGS_WIDTH-1:0] core_req_flags [NUM_REQS], + input wire[`CS_WORD_WIDTH-1:0] core_req_data [NUM_REQS], + input wire[TAG_WIDTH-1:0] core_req_tag [NUM_REQS], + output wire core_req_ready [NUM_REQS], + + // Core response + output wire core_rsp_valid [NUM_REQS], + output wire[`CS_WORD_WIDTH-1:0] core_rsp_data [NUM_REQS], + output wire[TAG_WIDTH-1:0] core_rsp_tag [NUM_REQS], + input wire core_rsp_ready [NUM_REQS], + + // Memory request + output wire mem_req_valid [MEM_PORTS], + output wire mem_req_rw [MEM_PORTS], + output wire [LINE_SIZE-1:0] mem_req_byteen [MEM_PORTS], + output wire [`CS_MEM_ADDR_WIDTH-1:0] mem_req_addr [MEM_PORTS], + output wire [`CS_LINE_WIDTH-1:0] mem_req_data [MEM_PORTS], + output wire [MEM_TAG_WIDTH-1:0] mem_req_tag [MEM_PORTS], + input wire mem_req_ready [MEM_PORTS], + + // Memory response + input wire mem_rsp_valid [MEM_PORTS], + input wire [`CS_LINE_WIDTH-1:0] mem_rsp_data [MEM_PORTS], + input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag [MEM_PORTS], + output wire mem_rsp_ready [MEM_PORTS] +); + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH) + ) core_bus_if[NUM_REQS](); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) mem_bus_if[MEM_PORTS](); + + // Core request + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_bus_if[i].req_valid = core_req_valid[i]; + assign core_bus_if[i].req_data.rw = core_req_rw[i]; + assign core_bus_if[i].req_data.byteen = core_req_byteen[i]; + assign core_bus_if[i].req_data.addr = core_req_addr[i]; + assign core_bus_if[i].req_data.flags = core_req_flags[i]; + assign core_bus_if[i].req_data.data = core_req_data[i]; + assign core_bus_if[i].req_data.tag = core_req_tag[i]; + assign core_req_ready[i] = core_bus_if[i].req_ready; + end + + // Core response + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign core_rsp_valid[i]= core_bus_if[i].rsp_valid; + assign core_rsp_data[i] = core_bus_if[i].rsp_data.data; + assign core_rsp_tag[i] = core_bus_if[i].rsp_data.tag; + assign core_bus_if[i].rsp_ready = core_rsp_ready[i]; + end + + // Memory request + for (genvar i = 0; i < MEM_PORTS; ++i) begin + assign mem_req_valid[i] = mem_bus_if[i].req_valid; + assign mem_req_rw[i] = mem_bus_if[i].req_data.rw; + assign mem_req_byteen[i]= mem_bus_if[i].req_data.byteen; + assign mem_req_addr[i] = mem_bus_if[i].req_data.addr; + assign mem_req_data[i] = mem_bus_if[i].req_data.data; + assign mem_req_tag[i] = mem_bus_if[i].req_data.tag; + assign mem_bus_if[i].req_ready = mem_req_ready[i]; + end + + // Memory response + for (genvar i = 0; i < MEM_PORTS; ++i) begin + assign mem_bus_if[i].rsp_valid = mem_rsp_valid[i]; + assign mem_bus_if[i].rsp_data.data = mem_rsp_data[i]; + assign mem_bus_if[i].rsp_data.tag = mem_rsp_tag[i]; + assign mem_rsp_ready[i] = mem_bus_if[i].rsp_ready; + end + + VX_cache_wrap #( + .INSTANCE_ID (INSTANCE_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .MEM_PORTS (MEM_PORTS), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MRSQ_SIZE (MRSQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .WRITE_ENABLE (WRITE_ENABLE), + .WRITEBACK (WRITEBACK), + .DIRTY_BYTES (DIRTY_BYTES), + .CORE_OUT_BUF (CORE_OUT_BUF), + .MEM_OUT_BUF (MEM_OUT_BUF) + ) cache ( + `ifdef PERF_ENABLE + .cache_perf (cache_perf), + `endif + .clk (clk), + .reset (reset), + .core_bus_if (core_bus_if), + .mem_bus_if (mem_bus_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/cache/VX_cache_wrap.sv b/designs/src/vortex/rtl/cache/VX_cache_wrap.sv new file mode 100644 index 0000000..b48abaf --- /dev/null +++ b/designs/src/vortex/rtl/cache/VX_cache_wrap.sv @@ -0,0 +1,295 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_cache_define.vh" + +module VX_cache_wrap import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + + parameter TAG_SEL_IDX = 0, + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + + // Number of memory ports + parameter MEM_PORTS = 1, + + // Size of cache in bytes + parameter CACHE_SIZE = 4096, + // Size of line inside a bank in bytes + parameter LINE_SIZE = 64, + // Number of banks + parameter NUM_BANKS = 4, + // Number of associative ways + parameter NUM_WAYS = 4, + // Size of a word in bytes + parameter WORD_SIZE = 16, + + // Core Response Queue Size + parameter CRSQ_SIZE = 4, + // Miss Reserv Queue Knob + parameter MSHR_SIZE = 16, + // Memory Response Queue Size + parameter MRSQ_SIZE = 4, + // Memory Request Queue Size + parameter MREQ_SIZE = 4, + + // Enable cache writeable + parameter WRITE_ENABLE = 1, + + // Enable cache writeback + parameter WRITEBACK = 0, + + // Enable dirty bytes on writeback + parameter DIRTY_BYTES = 0, + + // Replacement policy + parameter REPL_POLICY = `CS_REPL_FIFO, + + // core request tag size + parameter TAG_WIDTH = UUID_WIDTH + 1, + + // enable bypass for non-cacheable addresses + parameter NC_ENABLE = 0, + + // Force bypass for all requests + parameter PASSTHRU = 0, + + // Core response output buffer + parameter CORE_OUT_BUF = 3, + + // Memory request output buffer + parameter MEM_OUT_BUF = 3 + ) ( + + input wire clk, + input wire reset, + + // PERF +`ifdef PERF_ENABLE + output cache_perf_t cache_perf, +`endif + + VX_mem_bus_if.slave core_bus_if [NUM_REQS], + VX_mem_bus_if.master mem_bus_if [MEM_PORTS] +); + + `STATIC_ASSERT(NUM_BANKS == (1 << `CLOG2(NUM_BANKS)), ("invalid parameter")) + + localparam CACHE_MEM_TAG_WIDTH = `CACHE_MEM_TAG_WIDTH(MSHR_SIZE, NUM_BANKS, MEM_PORTS, UUID_WIDTH); + localparam BYPASS_TAG_WIDTH = `CACHE_BYPASS_TAG_WIDTH(NUM_REQS, MEM_PORTS, LINE_SIZE, WORD_SIZE, TAG_WIDTH); + localparam NC_TAG_WIDTH = `MAX(CACHE_MEM_TAG_WIDTH, BYPASS_TAG_WIDTH) + 1; + localparam MEM_TAG_WIDTH = PASSTHRU ? BYPASS_TAG_WIDTH : (NC_ENABLE ? NC_TAG_WIDTH : CACHE_MEM_TAG_WIDTH); + localparam BYPASS_ENABLE = (NC_ENABLE || PASSTHRU); + + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH) + ) core_bus_cache_if[NUM_REQS](); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (CACHE_MEM_TAG_WIDTH) + ) mem_bus_cache_if[MEM_PORTS](); + + VX_mem_bus_if #( + .DATA_SIZE (LINE_SIZE), + .TAG_WIDTH (MEM_TAG_WIDTH) + ) mem_bus_tmp_if[MEM_PORTS](); + + if (BYPASS_ENABLE) begin : g_bypass + + VX_cache_bypass #( + .NUM_REQS (NUM_REQS), + .MEM_PORTS (MEM_PORTS), + .TAG_SEL_IDX (TAG_SEL_IDX), + + .CACHE_ENABLE (!PASSTHRU), + + .WORD_SIZE (WORD_SIZE), + .LINE_SIZE (LINE_SIZE), + + .CORE_ADDR_WIDTH (`CS_WORD_ADDR_WIDTH), + .CORE_TAG_WIDTH (TAG_WIDTH), + + .MEM_ADDR_WIDTH (`CS_MEM_ADDR_WIDTH), + .MEM_TAG_IN_WIDTH (CACHE_MEM_TAG_WIDTH), + + .CORE_OUT_BUF (CORE_OUT_BUF), + .MEM_OUT_BUF (MEM_OUT_BUF) + ) cache_bypass ( + .clk (clk), + .reset (reset), + + .core_bus_in_if (core_bus_if), + .core_bus_out_if(core_bus_cache_if), + + .mem_bus_in_if (mem_bus_cache_if), + .mem_bus_out_if (mem_bus_tmp_if) + ); + + end else begin : g_no_bypass + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_cache_if + `ASSIGN_VX_MEM_BUS_IF (core_bus_cache_if[i], core_bus_if[i]); + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_bus_tmp_if + `ASSIGN_VX_MEM_BUS_IF (mem_bus_tmp_if[i], mem_bus_cache_if[i]); + end + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_bus_if + if (WRITE_ENABLE) begin : g_we + `ASSIGN_VX_MEM_BUS_IF (mem_bus_if[i], mem_bus_tmp_if[i]); + end else begin : g_ro + `ASSIGN_VX_MEM_BUS_RO_IF (mem_bus_if[i], mem_bus_tmp_if[i]); + end + end + + if (PASSTHRU == 0) begin : g_cache + + VX_cache #( + .INSTANCE_ID (INSTANCE_ID), + .CACHE_SIZE (CACHE_SIZE), + .LINE_SIZE (LINE_SIZE), + .NUM_BANKS (NUM_BANKS), + .NUM_WAYS (NUM_WAYS), + .WORD_SIZE (WORD_SIZE), + .NUM_REQS (NUM_REQS), + .MEM_PORTS (MEM_PORTS), + .WRITE_ENABLE (WRITE_ENABLE), + .WRITEBACK (WRITEBACK), + .DIRTY_BYTES (DIRTY_BYTES), + .REPL_POLICY (REPL_POLICY), + .CRSQ_SIZE (CRSQ_SIZE), + .MSHR_SIZE (MSHR_SIZE), + .MRSQ_SIZE (MRSQ_SIZE), + .MREQ_SIZE (MREQ_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .CORE_OUT_BUF (BYPASS_ENABLE ? 1 : CORE_OUT_BUF), + .MEM_OUT_BUF (BYPASS_ENABLE ? 1 : MEM_OUT_BUF) + ) cache ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .cache_perf (cache_perf), + `endif + .core_bus_if (core_bus_cache_if), + .mem_bus_if (mem_bus_cache_if) + ); + + end else begin : g_passthru + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_core_bus_cache_if + `UNUSED_VX_MEM_BUS_IF (core_bus_cache_if[i]) + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_mem_bus_cache_if + `INIT_VX_MEM_BUS_IF (mem_bus_cache_if[i]) + end + + `ifdef PERF_ENABLE + wire [NUM_REQS-1:0] perf_core_reads_per_req; + wire [NUM_REQS-1:0] perf_core_writes_per_req; + wire [NUM_REQS-1:0] perf_crsp_stall_per_req; + wire [MEM_PORTS-1:0] perf_mem_stall_per_port; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_perf_crsp_stall_per_req + assign perf_core_reads_per_req[i] = core_bus_if[i].req_valid && core_bus_if[i].req_ready && ~core_bus_if[i].req_data.rw; + assign perf_core_writes_per_req[i] = core_bus_if[i].req_valid && core_bus_if[i].req_ready && core_bus_if[i].req_data.rw; + assign perf_crsp_stall_per_req[i] = core_bus_if[i].rsp_valid && ~core_bus_if[i].rsp_ready; + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_perf_mem_stall_per_port + assign perf_mem_stall_per_port[i] = mem_bus_if[i].req_valid && ~mem_bus_if[i].req_ready; + end + + // per cycle: read misses, write misses, msrq stalls, pipeline stalls + wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_reads_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_core_writes_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; + wire [`CLOG2(MEM_PORTS+1)-1:0] perf_mem_stall_per_cycle; + + `POP_COUNT(perf_core_reads_per_cycle, perf_core_reads_per_req); + `POP_COUNT(perf_core_writes_per_cycle, perf_core_writes_per_req); + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req); + `POP_COUNT(perf_mem_stall_per_cycle, perf_mem_stall_per_port); + + reg [PERF_CTR_BITS-1:0] perf_core_reads; + reg [PERF_CTR_BITS-1:0] perf_core_writes; + reg [PERF_CTR_BITS-1:0] perf_mem_stalls; + reg [PERF_CTR_BITS-1:0] perf_crsp_stalls; + + always @(posedge clk) begin + if (reset) begin + perf_core_reads <= '0; + perf_core_writes <= '0; + perf_mem_stalls <= '0; + perf_crsp_stalls <= '0; + end else begin + perf_core_reads <= perf_core_reads + PERF_CTR_BITS'(perf_core_reads_per_cycle); + perf_core_writes <= perf_core_writes + PERF_CTR_BITS'(perf_core_writes_per_cycle); + perf_mem_stalls <= perf_mem_stalls + PERF_CTR_BITS'(perf_mem_stall_per_cycle); + perf_crsp_stalls <= perf_crsp_stalls + PERF_CTR_BITS'(perf_crsp_stall_per_cycle); + end + end + + assign cache_perf.reads = perf_core_reads; + assign cache_perf.writes = perf_core_writes; + assign cache_perf.read_misses = '0; + assign cache_perf.write_misses = '0; + assign cache_perf.bank_stalls = '0; + assign cache_perf.mshr_stalls = '0; + assign cache_perf.mem_stalls = perf_mem_stalls; + assign cache_perf.crsp_stalls = perf_crsp_stalls; + `endif + + end + +`ifdef DBG_TRACE_CACHE + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_trace_core + always @(posedge clk) begin + if (core_bus_if[i].req_valid && core_bus_if[i].req_ready) begin + if (core_bus_if[i].req_data.rw) begin + `TRACE(2, ("%t: %s core-wr-req[%0d]: addr=0x%0h, tag=0x%0h, byteen=0x%h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, i, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag.value, core_bus_if[i].req_data.byteen, core_bus_if[i].req_data.data, core_bus_if[i].req_data.tag.uuid)) + end else begin + `TRACE(2, ("%t: %s core-rd-req[%0d]: addr=0x%0h, tag=0x%0h (#%0d)\n", $time, INSTANCE_ID, i, `TO_FULL_ADDR(core_bus_if[i].req_data.addr), core_bus_if[i].req_data.tag.value, core_bus_if[i].req_data.tag.uuid)) + end + end + if (core_bus_if[i].rsp_valid && core_bus_if[i].rsp_ready) begin + `TRACE(2, ("%t: %s core-rd-rsp[%0d]: tag=0x%0h, data=0x%h (#%0d)\n", $time, INSTANCE_ID, i, core_bus_if[i].rsp_data.tag.value, core_bus_if[i].rsp_data.data, core_bus_if[i].rsp_data.tag.uuid)) + end + end + end + + for (genvar i = 0; i < MEM_PORTS; ++i) begin : g_trace_mem + always @(posedge clk) begin + if (mem_bus_if[i].req_valid && mem_bus_if[i].req_ready) begin + if (mem_bus_if[i].req_data.rw) begin + `TRACE(2, ("%t: %s mem-wr-req[%0d]: addr=0x%0h, tag=0x%0h, byteen=0x%h, data=0x%h (#%0d)\n", + $time, INSTANCE_ID, i, `TO_FULL_ADDR(mem_bus_if[i].req_data.addr), mem_bus_if[i].req_data.tag.value, mem_bus_if[i].req_data.byteen, mem_bus_if[i].req_data.data, mem_bus_if[i].req_data.tag.uuid)) + end else begin + `TRACE(2, ("%t: %s mem-rd-req[%0d]: addr=0x%0h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, `TO_FULL_ADDR(mem_bus_if[i].req_data.addr), mem_bus_if[i].req_data.tag.value, mem_bus_if[i].req_data.tag.uuid)) + end + end + if (mem_bus_if[i].rsp_valid && mem_bus_if[i].rsp_ready) begin + `TRACE(2, ("%t: %s mem-rd-rsp[%0d]: data=0x%h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, mem_bus_if[i].rsp_data.data, mem_bus_if[i].rsp_data.tag.value, mem_bus_if[i].rsp_data.tag.uuid)) + end + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_alu_int.sv b/designs/src/vortex/rtl/core/VX_alu_int.sv new file mode 100644 index 0000000..88602d0 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_alu_int.sv @@ -0,0 +1,294 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_alu_int import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter BLOCK_IDX = 0, + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_result_if.master result_if, + VX_branch_ctl_if.master branch_ctl_if +); + + `UNUSED_SPARAM (INSTANCE_ID) + localparam LANE_BITS = `CLOG2(NUM_LANES); + localparam LANE_WIDTH = `UP(LANE_BITS); + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam SHIFT_IMM_BITS = `CLOG2(`XLEN); + + `UNUSED_VAR (execute_if.data.rs3_data) + + wire [NUM_LANES-1:0][`XLEN-1:0] add_result; + wire [NUM_LANES-1:0][`XLEN:0] sub_result; // +1 bit for branch compare + reg [NUM_LANES-1:0][`XLEN-1:0] shr_zic_result; + reg [NUM_LANES-1:0][`XLEN-1:0] msc_result; + + wire [NUM_LANES-1:0][`XLEN-1:0] add_result_w; + wire [NUM_LANES-1:0][`XLEN-1:0] sub_result_w; + wire [NUM_LANES-1:0][`XLEN-1:0] shr_result_w; + reg [NUM_LANES-1:0][`XLEN-1:0] msc_result_w; + reg [NUM_LANES-1:0][`XLEN-1:0] vote_result; + wire [NUM_LANES-1:0][`XLEN-1:0] shfl_result; + + reg [NUM_LANES-1:0][`XLEN-1:0] alu_result; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_result_r; + +`ifdef XLEN_64 + wire is_alu_w = execute_if.data.op_args.alu.is_w; +`else + wire is_alu_w = 0; +`endif + + wire [INST_ALU_BITS-1:0] alu_op = INST_ALU_BITS'(execute_if.data.op_type); + wire [INST_BR_BITS-1:0] br_op = INST_BR_BITS'(execute_if.data.op_type); + wire is_br_op = (execute_if.data.op_args.alu.xtype == ALU_TYPE_BRANCH); + wire is_sub_op = inst_alu_is_sub(alu_op); + wire is_signed = inst_alu_signed(alu_op); + wire [1:0] op_class = is_br_op ? inst_br_class(alu_op) : inst_alu_class(alu_op); + + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1 = execute_if.data.rs1_data; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2 = execute_if.data.rs2_data; + + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in1_PC = execute_if.data.op_args.alu.use_PC ? {NUM_LANES{to_fullPC(execute_if.data.PC)}} : alu_in1; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_imm = execute_if.data.op_args.alu.use_imm ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_args.alu.imm)}} : alu_in2; + wire [NUM_LANES-1:0][`XLEN-1:0] alu_in2_br = (execute_if.data.op_args.alu.use_imm && ~is_br_op) ? {NUM_LANES{`SEXT(`XLEN, execute_if.data.op_args.alu.imm)}} : alu_in2; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_add_result + assign add_result[i] = alu_in1_PC[i] + alu_in2_imm[i]; + assign add_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] + alu_in2_imm[i][31:0])); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_sub_result + wire [`XLEN:0] sub_in1 = {is_signed & alu_in1[i][`XLEN-1], alu_in1[i]}; + wire [`XLEN:0] sub_in2 = {is_signed & alu_in2_br[i][`XLEN-1], alu_in2_br[i]}; + assign sub_result[i] = sub_in1 - sub_in2; + assign sub_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] - alu_in2_imm[i][31:0])); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_shr_result + wire [`XLEN:0] shr_in1 = {is_signed && alu_in1[i][`XLEN-1], alu_in1[i]}; + always @(*) begin + case (alu_op[1:0]) + `ifdef EXT_ZICOND_ENABLE + 2'b10, 2'b11: begin // CZERO + shr_zic_result[i] = alu_in1[i] & {`XLEN{alu_op[0] ^ (| alu_in2[i])}}; + end + `endif + default: begin // SRL, SRA, SRLI, SRAI + shr_zic_result[i] = `XLEN'($signed(shr_in1) >>> alu_in2_imm[i][SHIFT_IMM_BITS-1:0]); + end + endcase + end + wire [32:0] shr_in1_w = {is_signed && alu_in1[i][31], alu_in1[i][31:0]}; + wire [31:0] shr_res_w = 32'($signed(shr_in1_w) >>> alu_in2_imm[i][4:0]); + assign shr_result_w[i] = `XLEN'($signed(shr_res_w)); + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_msc_result + always @(*) begin + case (alu_op[1:0]) + 2'b00: msc_result[i] = alu_in1[i] & alu_in2_imm[i]; // AND + 2'b01: msc_result[i] = alu_in1[i] | alu_in2_imm[i]; // OR + 2'b10: msc_result[i] = alu_in1[i] ^ alu_in2_imm[i]; // XOR + 2'b11: msc_result[i] = alu_in1[i] << alu_in2_imm[i][SHIFT_IMM_BITS-1:0]; // SLL + endcase + end + assign msc_result_w[i] = `XLEN'($signed(alu_in1[i][31:0] << alu_in2_imm[i][4:0])); // SLLW + end + + // VOTE + wire [NUM_LANES-1:0] vote_true, vote_false; + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_vote_calc + wire pred = alu_in1[i][0]; + assign vote_true[i] = execute_if.data.tmask[i] && pred; + assign vote_false[i] = execute_if.data.tmask[i] && ~pred; + end + wire has_vote_true = (| vote_true); + wire has_vote_false = (| vote_false); + wire vote_all = ~has_vote_false; + wire vote_any = has_vote_true; + wire vote_none = ~has_vote_true; + wire vote_uni = vote_all || vote_none; + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_vote_result + always @(*) begin + case (alu_op[1:0]) + INST_VOTE_ALL: vote_result[i] = `XLEN'(vote_all); + INST_VOTE_ANY: vote_result[i] = `XLEN'(vote_any); + INST_VOTE_UNI: vote_result[i] = `XLEN'(vote_uni); + INST_VOTE_BAL: vote_result[i] = `XLEN'(vote_true); + endcase + end + end + + // SHFL + if (NUM_LANES > 1) begin : g_shfl + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_i + wire [LANE_BITS-1:0] bval = alu_in2[i][0 +: LANE_BITS]; + wire [LANE_BITS-1:0] cval = alu_in2[i][6 +: LANE_BITS]; + wire [LANE_BITS-1:0] mask = alu_in2[i][12 +: LANE_BITS]; + wire [LANE_BITS-1:0] minLane = (LANE_BITS'(i) & mask); + wire [LANE_BITS-1:0] maxLane = minLane | (cval & ~(mask)); + + wire [LANE_BITS:0] lane_up = LANE_BITS'(i) - bval; + wire [LANE_BITS:0] lane_down = LANE_BITS'(i) + bval; + wire [LANE_BITS-1:0] lane_bfly = LANE_BITS'(i) ^ bval; + wire [LANE_BITS-1:0] lane_idx = minLane | (bval & ~mask); + + reg [LANE_BITS-1:0] lane; + always @(*) begin + lane = LANE_BITS'(i); + case (alu_op[1:0]) + INST_SHFL_UP: begin + if ($signed(lane_up) >= $signed({1'b0, minLane})) begin + lane = lane_up[LANE_BITS-1:0]; + end + end + INST_SHFL_DOWN: begin + if (lane_down <= {1'b0, maxLane}) begin + lane = lane_down[LANE_BITS-1:0]; + end + end + INST_SHFL_BFLY: begin + if (lane_bfly <= maxLane) begin + lane = lane_bfly; + end + end + INST_SHFL_IDX: begin + if (lane_idx <= maxLane) begin + lane = lane_idx; + end + end + endcase + end + assign shfl_result[i] = execute_if.data.tmask[lane] ? alu_in1[lane] : alu_in1[i]; + end + end else begin : g_shfl_0 + assign shfl_result[0] = alu_in1[0]; + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_alu_result + wire [`XLEN-1:0] slt_br_result = `XLEN'({is_br_op && ~(| sub_result[i][`XLEN-1:0]), sub_result[i][`XLEN]}); + wire [`XLEN-1:0] sub_slt_br_result = (is_sub_op && ~is_br_op) ? sub_result[i][`XLEN-1:0] : slt_br_result; + always @(*) begin + if (execute_if.data.op_args.alu.xtype == ALU_TYPE_OTHER) begin + case (alu_op[2]) + 1'b0: alu_result[i] = vote_result[i]; + 1'b1: alu_result[i] = shfl_result[i]; + default:; + endcase + end else begin + case ({is_alu_w, op_class}) + 3'b000: alu_result[i] = add_result[i]; // ADD, LUI, AUIPC + 3'b001: alu_result[i] = sub_slt_br_result; // SUB, SLTU, SLTI, BR* + 3'b010: alu_result[i] = shr_zic_result[i]; // SRL, SRA, SRLI, SRAI, CZERO* + 3'b011: alu_result[i] = msc_result[i]; // AND, OR, XOR, SLL, SLLI + 3'b100: alu_result[i] = add_result_w[i]; // ADDIW, ADDW + 3'b101: alu_result[i] = sub_result_w[i]; // SUBW + 3'b110: alu_result[i] = shr_result_w[i]; // SRLW, SRAW, SRLIW, SRAIW + 3'b111: alu_result[i] = msc_result_w[i]; // SLLW + endcase + end + end + end + + // branch + + wire [PC_BITS-1:0] PC_r; + wire [INST_BR_BITS-1:0] br_op_r; + wire [PC_BITS-1:0] cbr_dest, cbr_dest_r; + wire [LANE_WIDTH-1:0] last_tid, last_tid_r; + wire is_br_op_r; + + assign cbr_dest = from_fullPC(add_result[0]); + + if (LANE_BITS != 0) begin : g_last_tid + VX_priority_encoder #( + .N (NUM_LANES), + .REVERSE (1) + ) last_tid_sel ( + .data_in (execute_if.data.tmask), + .index_out (last_tid), + `UNUSED_PIN (onehot_out), + `UNUSED_PIN (valid_out) + ); + end else begin : g_tid_0 + assign last_tid = 0; + end + + VX_elastic_buffer #( + .DATAW (UUID_WIDTH + NW_WIDTH + NUM_LANES + NUM_REGS_BITS + 1 + PID_WIDTH + 1 + 1 + (NUM_LANES * `XLEN) + PC_BITS + PC_BITS + 1 + INST_BR_BITS + LANE_WIDTH) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (execute_if.valid), + .ready_in (execute_if.ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, alu_result, execute_if.data.PC, cbr_dest, is_br_op, br_op, last_tid}), + .data_out ({result_if.data.uuid, result_if.data.wid, result_if.data.tmask, result_if.data.rd, result_if.data.wb, result_if.data.pid, result_if.data.sop, result_if.data.eop, alu_result_r, PC_r, cbr_dest_r, is_br_op_r, br_op_r, last_tid_r}), + .valid_out (result_if.valid), + .ready_out (result_if.ready) + ); + + `UNUSED_VAR (br_op_r) + wire is_br_neg = inst_br_is_neg(br_op_r); + wire is_br_less = inst_br_is_less(br_op_r); + wire is_br_static = inst_br_is_static(br_op_r); + + wire [`XLEN-1:0] br_result = alu_result_r[last_tid_r]; + wire is_less = br_result[0]; + wire is_equal = br_result[1]; + + wire result_fire = result_if.valid && result_if.ready; + wire br_enable = result_fire && is_br_op_r && result_if.data.eop; + wire br_taken = ((is_br_less ? is_less : is_equal) ^ is_br_neg) | is_br_static; + wire [PC_BITS-1:0] br_dest = is_br_static ? from_fullPC(br_result) : cbr_dest_r; + wire [NW_WIDTH-1:0] br_wid; + `ASSIGN_BLOCKED_WID (br_wid, result_if.data.wid, BLOCK_IDX, `NUM_ALU_BLOCKS) + + VX_pipe_register #( + .DATAW (1 + NW_WIDTH + 1 + PC_BITS), + .RESETW (1) + ) branch_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({br_enable, br_wid, br_taken, br_dest}), + .data_out ({branch_ctl_if.valid, branch_ctl_if.wid, branch_ctl_if.taken, branch_ctl_if.dest}) + ); + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + wire [`XLEN-1:0] PC_next = to_fullPC(PC_r) + `XLEN'(4); + assign result_if.data.data[i] = (is_br_op_r && is_br_static) ? PC_next : alu_result_r[i]; + end + + assign result_if.data.PC = PC_r; + +`ifdef DBG_TRACE_PIPELINE + always @(posedge clk) begin + if (br_enable) begin + `TRACE(2, ("%t: %s branch: wid=%0d, PC=0x%0h, taken=%b, dest=0x%0h (#%0d)\n", + $time, INSTANCE_ID, br_wid, to_fullPC(result_if.data.PC), br_taken, to_fullPC(br_dest), result_if.data.uuid)) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_alu_muldiv.sv b/designs/src/vortex/rtl/core/VX_alu_muldiv.sv new file mode 100644 index 0000000..00d2359 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_alu_muldiv.sv @@ -0,0 +1,342 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_alu_muldiv import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_result_if.master result_if +); + `UNUSED_SPARAM (INSTANCE_ID) + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam TAG_WIDTH = UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + NUM_REGS_BITS + 1 + PID_WIDTH + 1 + 1; + + `UNUSED_VAR (execute_if.data.rs3_data) + + wire [INST_M_BITS-1:0] muldiv_op = INST_M_BITS'(execute_if.data.op_type); + + wire is_mulx_op = inst_m_is_mulx(muldiv_op); + wire is_signed_op = inst_m_signed(muldiv_op); +`ifdef XLEN_64 + wire is_alu_w = execute_if.data.op_args.alu.is_w; +`else + wire is_alu_w = 0; +`endif + + wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_out; + wire [UUID_WIDTH-1:0] mul_uuid_out; + wire [NW_WIDTH-1:0] mul_wid_out; + wire [NUM_LANES-1:0] mul_tmask_out; + wire [PC_BITS-1:0] mul_PC_out; + wire [NUM_REGS_BITS-1:0] mul_rd_out; + wire mul_wb_out; + wire [PID_WIDTH-1:0] mul_pid_out; + wire mul_sop_out, mul_eop_out; + + wire mul_valid_in = execute_if.valid && is_mulx_op; + wire mul_ready_in; + wire mul_valid_out; + wire mul_ready_out; + + wire is_mulh_in = inst_m_is_mulh(muldiv_op); + wire is_signed_mul_a = inst_m_signed_a(muldiv_op); + wire is_signed_mul_b = is_signed_op; + +`ifdef IMUL_DPI + + wire [NUM_LANES-1:0][`XLEN-1:0] mul_result_tmp; + + wire mul_fire_in = mul_valid_in && mul_ready_in; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mul_result_tmp + reg [`XLEN-1:0] mul_resultl, mul_resulth; + wire [`XLEN-1:0] mul_in1 = is_alu_w ? (execute_if.data.rs1_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs1_data[i]; + wire [`XLEN-1:0] mul_in2 = is_alu_w ? (execute_if.data.rs2_data[i] & `XLEN'hFFFFFFFF) : execute_if.data.rs2_data[i]; + always @(*) begin + dpi_imul (mul_fire_in, is_signed_mul_a, is_signed_mul_b, mul_in1, mul_in2, mul_resultl, mul_resulth); + end + assign mul_result_tmp[i] = is_mulh_in ? mul_resulth : (is_alu_w ? `XLEN'($signed(mul_resultl[31:0])) : mul_resultl); + end + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + (NUM_LANES * `XLEN)), + .DEPTH (`LATENCY_IMUL), + .RESETW (1) + ) mul_shift_reg ( + .clk (clk), + .reset (reset), + .enable (mul_ready_in), + .data_in ({mul_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, mul_result_tmp}), + .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, mul_result_out}) + ); + + assign mul_ready_in = mul_ready_out || ~mul_valid_out; + +`else + + wire [NUM_LANES-1:0][2*(`XLEN+1)-1:0] mul_result_tmp; + wire is_mulh_out; + wire is_mul_w_out; + +`ifdef XLEN_64 + + wire [NUM_LANES-1:0][`XLEN:0] mul_in1; + wire [NUM_LANES-1:0][`XLEN:0] mul_in2; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mul_in + assign mul_in1[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]} : {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]}; + assign mul_in2[i] = is_alu_w ? {{(`XLEN-31){execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]} : {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]}; + end + + wire mul_strode; + wire mul_busy; + + VX_elastic_adapter mul_elastic_adapter ( + .clk (clk), + .reset (reset), + .valid_in (mul_valid_in), + .ready_in (mul_ready_in), + .valid_out (mul_valid_out), + .ready_out (mul_ready_out), + .strobe (mul_strode), + .busy (mul_busy) + ); + + VX_serial_mul #( + .A_WIDTH (`XLEN+1), + .LANES (NUM_LANES), + .SIGNED (1) + ) serial_mul ( + .clk (clk), + .reset (reset), + + .strobe (mul_strode), + .busy (mul_busy), + + .dataa (mul_in1), + .datab (mul_in2), + .result (mul_result_tmp) + ); + + reg [TAG_WIDTH+2-1:0] mul_tag_r; + always @(posedge clk) begin + if (mul_valid_in && mul_ready_in) begin + mul_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_mulh_in, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}; + end + end + + assign {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, is_mulh_out, is_mul_w_out, mul_pid_out, mul_sop_out, mul_eop_out} = mul_tag_r; + +`else + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_multiplier + wire [`XLEN:0] mul_in1 = {is_signed_mul_a && execute_if.data.rs1_data[i][`XLEN-1], execute_if.data.rs1_data[i]}; + wire [`XLEN:0] mul_in2 = {is_signed_mul_b && execute_if.data.rs2_data[i][`XLEN-1], execute_if.data.rs2_data[i]}; + + VX_multiplier #( + .A_WIDTH (`XLEN+1), + .B_WIDTH (`XLEN+1), + .R_WIDTH (2*(`XLEN+1)), + .SIGNED (1), + .LATENCY (`LATENCY_IMUL) + ) multiplier ( + .clk (clk), + .enable (mul_ready_in), + .dataa (mul_in1), + .datab (mul_in2), + .result (mul_result_tmp[i]) + ); + end + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + 1 + 1), + .DEPTH (`LATENCY_IMUL), + .RESETW (1) + ) mul_shift_reg ( + .clk (clk), + .reset (reset), + .enable (mul_ready_in), + .data_in ({mul_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, is_mulh_in, is_alu_w}), + .data_out ({mul_valid_out, mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, is_mulh_out, is_mul_w_out}) + ); + + assign mul_ready_in = mul_ready_out || ~mul_valid_out; + +`endif + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mul_result_out + `ifdef XLEN_64 + assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : + (is_mul_w_out ? `XLEN'($signed(mul_result_tmp[i][31:0])) : + mul_result_tmp[i][`XLEN-1:0]); + `else + assign mul_result_out[i] = is_mulh_out ? mul_result_tmp[i][2*(`XLEN)-1:`XLEN] : mul_result_tmp[i][`XLEN-1:0]; + `UNUSED_VAR (is_mul_w_out) + `endif + end + +`endif + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_LANES-1:0][`XLEN-1:0] div_result_out; + wire [UUID_WIDTH-1:0] div_uuid_out; + wire [NW_WIDTH-1:0] div_wid_out; + wire [NUM_LANES-1:0] div_tmask_out; + wire [PC_BITS-1:0] div_PC_out; + wire [NUM_REGS_BITS-1:0] div_rd_out; + wire div_wb_out; + wire [PID_WIDTH-1:0] div_pid_out; + wire div_sop_out, div_eop_out; + + wire is_rem_op = inst_m_is_rem(muldiv_op); + + wire div_valid_in = execute_if.valid && ~is_mulx_op; + wire div_ready_in; + wire div_valid_out; + wire div_ready_out; + + wire [NUM_LANES-1:0][`XLEN-1:0] div_in1; + wire [NUM_LANES-1:0][`XLEN-1:0] div_in2; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_div_in + `ifdef XLEN_64 + assign div_in1[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs1_data[i][31]}}, execute_if.data.rs1_data[i][31:0]}: execute_if.data.rs1_data[i]; + assign div_in2[i] = is_alu_w ? {{(`XLEN-32){is_signed_op && execute_if.data.rs2_data[i][31]}}, execute_if.data.rs2_data[i][31:0]}: execute_if.data.rs2_data[i]; + `else + assign div_in1[i] = execute_if.data.rs1_data[i]; + assign div_in2[i] = execute_if.data.rs2_data[i]; + `endif + end + +`ifdef IDIV_DPI + + wire [NUM_LANES-1:0][`XLEN-1:0] div_result_in; + wire div_fire_in = div_valid_in && div_ready_in; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_div_result_in + reg [`XLEN-1:0] div_quotient, div_remainder; + always @(*) begin + dpi_idiv (div_fire_in, is_signed_op, div_in1[i], div_in2[i], div_quotient, div_remainder); + end + assign div_result_in[i] = is_rem_op ? (is_alu_w ? `XLEN'($signed(div_remainder[31:0])) : div_remainder) : + (is_alu_w ? `XLEN'($signed(div_quotient[31:0])) : div_quotient); + end + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + (NUM_LANES * `XLEN)), + .DEPTH (`LATENCY_IMUL), + .RESETW (1) + ) div_shift_reg ( + .clk(clk), + .reset (reset), + .enable (div_ready_in), + .data_in ({div_valid_in, execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, div_result_in}), + .data_out ({div_valid_out, div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_pid_out, div_sop_out, div_eop_out, div_result_out}) + ); + + assign div_ready_in = div_ready_out || ~div_valid_out; + +`else + + wire [NUM_LANES-1:0][`XLEN-1:0] div_quotient, div_remainder; + wire is_rem_op_out; + wire is_div_w_out; + wire div_strode; + wire div_busy; + + VX_elastic_adapter div_elastic_adapter ( + .clk (clk), + .reset (reset), + .valid_in (div_valid_in), + .ready_in (div_ready_in), + .valid_out (div_valid_out), + .ready_out (div_ready_out), + .strobe (div_strode), + .busy (div_busy) + ); + + VX_serial_div #( + .WIDTHN (`XLEN), + .WIDTHD (`XLEN), + .WIDTHQ (`XLEN), + .WIDTHR (`XLEN), + .LANES (NUM_LANES) + ) serial_div ( + .clk (clk), + .reset (reset), + + .strobe (div_strode), + .busy (div_busy), + + .is_signed (is_signed_op), + .numer (div_in1), + .denom (div_in2), + + .quotient (div_quotient), + .remainder (div_remainder) + ); + + reg [TAG_WIDTH+2-1:0] div_tag_r; + always @(posedge clk) begin + if (div_valid_in && div_ready_in) begin + div_tag_r <= {execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, is_rem_op, is_alu_w, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}; + end + end + + assign {div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, is_rem_op_out, is_div_w_out, div_pid_out, div_sop_out, div_eop_out} = div_tag_r; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_div_result_out + `ifdef XLEN_64 + assign div_result_out[i] = is_rem_op_out ? (is_div_w_out ? `XLEN'($signed(div_remainder[i][31:0])) : div_remainder[i]) : + (is_div_w_out ? `XLEN'($signed(div_quotient[i][31:0])) : div_quotient[i]); + `else + assign div_result_out[i] = is_rem_op_out ? div_remainder[i] : div_quotient[i]; + `UNUSED_VAR (is_div_w_out) + `endif + end + +`endif + + // can accept new request? + assign execute_if.ready = is_mulx_op ? mul_ready_in : div_ready_in; + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (TAG_WIDTH + (NUM_LANES * `XLEN)), + .ARBITER ("P"), + .OUT_BUF (2) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in ({div_valid_out, mul_valid_out}), + .ready_in ({div_ready_out, mul_ready_out}), + .data_in ({{div_uuid_out, div_wid_out, div_tmask_out, div_PC_out, div_rd_out, div_wb_out, div_pid_out, div_sop_out, div_eop_out, div_result_out}, + {mul_uuid_out, mul_wid_out, mul_tmask_out, mul_PC_out, mul_rd_out, mul_wb_out, mul_pid_out, mul_sop_out, mul_eop_out, mul_result_out}}), + .data_out ({result_if.data.uuid, result_if.data.wid, result_if.data.tmask, result_if.data.PC, result_if.data.rd, result_if.data.wb, result_if.data.pid, result_if.data.sop, result_if.data.eop, result_if.data.data}), + .valid_out (result_if.valid), + .ready_out (result_if.ready), + `UNUSED_PIN (sel_out) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_alu_unit.sv b/designs/src/vortex/rtl/core/VX_alu_unit.sv new file mode 100644 index 0000000..1b7f9b6 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_alu_unit.sv @@ -0,0 +1,127 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_alu_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH], + VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS] +); + + `UNUSED_SPARAM (INSTANCE_ID) + localparam BLOCK_SIZE = `NUM_ALU_BLOCKS; + localparam NUM_LANES = `NUM_ALU_LANES; + localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `SIMD_WIDTH); + localparam PE_COUNT = 1 + `EXT_M_ENABLED; + localparam PE_SEL_BITS = `CLOG2(PE_COUNT); + localparam PE_IDX_INT = 0; + localparam PE_IDX_MDV = PE_IDX_INT + `EXT_M_ENABLED; + + VX_execute_if #( + .data_t (alu_exe_t) + ) per_block_execute_if[BLOCK_SIZE](); + + VX_result_if #( + .data_t (alu_res_t) + ) per_block_result_if[BLOCK_SIZE](); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (PARTIAL_BW ? 3 : 0) + ) dispatch_unit ( + .clk (clk), + .reset (reset), + .dispatch_if(dispatch_if), + .execute_if (per_block_execute_if) + ); + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_blocks + + VX_execute_if #( + .data_t (alu_exe_t) + ) pe_execute_if[PE_COUNT](); + + VX_result_if#( + .data_t (alu_res_t) + ) pe_result_if[PE_COUNT](); + + reg [`UP(PE_SEL_BITS)-1:0] pe_select; + always @(*) begin + pe_select = PE_IDX_INT; + if (`EXT_M_ENABLED && (per_block_execute_if[block_idx].data.op_args.alu.xtype == ALU_TYPE_MULDIV)) + pe_select = PE_IDX_MDV; + end + + VX_pe_switch #( + .PE_COUNT (PE_COUNT), + .NUM_LANES (NUM_LANES), + .ARBITER ("R"), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (PARTIAL_BW ? 1 : 3) + ) pe_switch ( + .clk (clk), + .reset (reset), + .pe_sel (pe_select), + .execute_in_if (per_block_execute_if[block_idx]), + .result_out_if (per_block_result_if[block_idx]), + .execute_out_if (pe_execute_if), + .result_in_if (pe_result_if) + ); + + VX_alu_int #( + .INSTANCE_ID (`SFORMATF(("%s-int%0d", INSTANCE_ID, block_idx))), + .BLOCK_IDX (block_idx), + .NUM_LANES (NUM_LANES) + ) alu_int ( + .clk (clk), + .reset (reset), + .execute_if (pe_execute_if[PE_IDX_INT]), + .branch_ctl_if (branch_ctl_if[block_idx]), + .result_if (pe_result_if[PE_IDX_INT]) + ); + + `ifdef EXT_M_ENABLE + VX_alu_muldiv #( + .INSTANCE_ID (`SFORMATF(("%s-muldiv%0d", INSTANCE_ID, block_idx))), + .NUM_LANES (NUM_LANES) + ) muldiv_unit ( + .clk (clk), + .reset (reset), + .execute_if (pe_execute_if[PE_IDX_MDV]), + .result_if (pe_result_if[PE_IDX_MDV]) + ); + `endif + end + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (PARTIAL_BW ? 3 : 0) + ) gather_unit ( + .clk (clk), + .reset (reset), + .result_if (per_block_result_if), + .commit_if (commit_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_commit.sv b/designs/src/vortex/rtl/core/VX_commit.sv new file mode 100644 index 0000000..d54da6a --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_commit.sv @@ -0,0 +1,193 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_commit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + + // inputs + VX_commit_if.slave commit_if [NUM_EX_UNITS * `ISSUE_WIDTH], + + // outputs + VX_writeback_if.master writeback_if [`ISSUE_WIDTH], + VX_commit_csr_if.master commit_csr_if, + VX_commit_sched_if.master commit_sched_if +); + `UNUSED_SPARAM (INSTANCE_ID) + localparam OUT_DATAW = $bits(commit_t); + localparam COMMIT_SIZEW = `CLOG2(`SIMD_WIDTH + 1); + localparam COMMIT_ALL_SIZEW = COMMIT_SIZEW + `ISSUE_WIDTH - 1; + + // commit arbitration + + VX_commit_if commit_arb_if[`ISSUE_WIDTH](); + + wire [`ISSUE_WIDTH-1:0] per_issue_commit_fire; + wire [`ISSUE_WIDTH-1:0][NW_WIDTH-1:0] per_issue_commit_wid; + wire [`ISSUE_WIDTH-1:0][`SIMD_WIDTH-1:0] per_issue_commit_tmask; + wire [`ISSUE_WIDTH-1:0] per_issue_commit_eop; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_commit_arbs + + wire [NUM_EX_UNITS-1:0] valid_in; + wire [NUM_EX_UNITS-1:0][OUT_DATAW-1:0] data_in; + wire [NUM_EX_UNITS-1:0] ready_in; + + for (genvar j = 0; j < NUM_EX_UNITS; ++j) begin : g_data_in + assign valid_in[j] = commit_if[j * `ISSUE_WIDTH + i].valid; + assign data_in[j] = commit_if[j * `ISSUE_WIDTH + i].data; + assign commit_if[j * `ISSUE_WIDTH + i].ready = ready_in[j]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_EX_UNITS), + .DATAW (OUT_DATAW), + .ARBITER ("P"), + .OUT_BUF (1) + ) commit_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in (data_in), + .data_out (commit_arb_if[i].data), + .valid_out (commit_arb_if[i].valid), + .ready_out (commit_arb_if[i].ready), + `UNUSED_PIN (sel_out) + ); + + assign per_issue_commit_fire[i] = commit_arb_if[i].valid && commit_arb_if[i].ready; + assign per_issue_commit_tmask[i]= {`SIMD_WIDTH{per_issue_commit_fire[i]}} & commit_arb_if[i].data.tmask; + assign per_issue_commit_wid[i] = commit_arb_if[i].data.wid; + assign per_issue_commit_eop[i] = commit_arb_if[i].data.eop; + end + + // CSRs update + + wire [`ISSUE_WIDTH-1:0][COMMIT_SIZEW-1:0] commit_size, commit_size_r; + wire [COMMIT_ALL_SIZEW-1:0] commit_size_all_r, commit_size_all_rr; + wire commit_fire_any, commit_fire_any_r, commit_fire_any_rr; + + assign commit_fire_any = (| per_issue_commit_fire); + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_commit_size + wire [COMMIT_SIZEW-1:0] count; + `POP_COUNT(count, per_issue_commit_tmask[i]); + assign commit_size[i] = count; + end + + VX_pipe_register #( + .DATAW (1 + `ISSUE_WIDTH * COMMIT_SIZEW), + .RESETW (1) + ) commit_size_reg1 ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({commit_fire_any, commit_size}), + .data_out ({commit_fire_any_r, commit_size_r}) + ); + + VX_reduce_tree #( + .IN_W (COMMIT_SIZEW), + .OUT_W (COMMIT_ALL_SIZEW), + .N (`ISSUE_WIDTH), + .OP ("+") + ) commit_size_reduce ( + .data_in (commit_size_r), + .data_out (commit_size_all_r) + ); + + VX_pipe_register #( + .DATAW (1 + COMMIT_ALL_SIZEW), + .RESETW (1) + ) commit_size_reg2 ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({commit_fire_any_r, commit_size_all_r}), + .data_out ({commit_fire_any_rr, commit_size_all_rr}) + ); + + reg [PERF_CTR_BITS-1:0] instret; + always @(posedge clk) begin + if (reset) begin + instret <= '0; + end else begin + if (commit_fire_any_rr) begin + instret <= instret + PERF_CTR_BITS'(commit_size_all_rr); + end + end + end + assign commit_csr_if.instret = instret; + + // Track committed instructions + + reg [`NUM_WARPS-1:0] committed_warps; + + always @(*) begin + committed_warps = 0; + for (integer i = 0; i < `ISSUE_WIDTH; ++i) begin + if (per_issue_commit_fire[i] && per_issue_commit_eop[i]) begin + committed_warps[per_issue_commit_wid[i]] = 1; + end + end + end + + VX_pipe_register #( + .DATAW (`NUM_WARPS), + .RESETW (`NUM_WARPS) + ) committed_pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in (committed_warps), + .data_out ({commit_sched_if.committed_warps}) + ); + + // Writeback + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_writeback + assign writeback_if[i].valid = commit_arb_if[i].valid && commit_arb_if[i].data.wb; + assign writeback_if[i].data.uuid = commit_arb_if[i].data.uuid; + assign writeback_if[i].data.wis = wid_to_wis(commit_arb_if[i].data.wid); + assign writeback_if[i].data.sid = commit_arb_if[i].data.sid; + assign writeback_if[i].data.PC = commit_arb_if[i].data.PC; + assign writeback_if[i].data.tmask= commit_arb_if[i].data.tmask; + assign writeback_if[i].data.rd = commit_arb_if[i].data.rd; + assign writeback_if[i].data.data = commit_arb_if[i].data.data; + assign writeback_if[i].data.sop = commit_arb_if[i].data.sop; + assign writeback_if[i].data.eop = commit_arb_if[i].data.eop; + assign commit_arb_if[i].ready = 1; + end + +`ifdef DBG_TRACE_PIPELINE + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_trace + for (genvar j = 0; j < NUM_EX_UNITS; ++j) begin : g_j + always @(posedge clk) begin + if (commit_if[j * `ISSUE_WIDTH + i].valid && commit_if[j * `ISSUE_WIDTH + i].ready) begin + `TRACE(1, ("%t: %s: wid=%0d, sid=%0d, PC=0x%0h, ex=", $time, INSTANCE_ID, commit_if[j * `ISSUE_WIDTH + i].data.wid, commit_if[j * `ISSUE_WIDTH + i].data.sid, to_fullPC(commit_if[j * `ISSUE_WIDTH + i].data.PC))) + VX_trace_pkg::trace_ex_type(1, j); + `TRACE(1, (", tmask=%b, wb=%0d, rd=%0d, sop=%b, eop=%b, data=", commit_if[j * `ISSUE_WIDTH + i].data.tmask, commit_if[j * `ISSUE_WIDTH + i].data.wb, commit_if[j * `ISSUE_WIDTH + i].data.rd, commit_if[j * `ISSUE_WIDTH + i].data.sop, commit_if[j * `ISSUE_WIDTH + i].data.eop)) + `TRACE_ARRAY1D(1, "0x%0h", commit_if[j * `ISSUE_WIDTH + i].data.data, `SIMD_WIDTH) + `TRACE(1, (" (#%0d)\n", commit_if[j * `ISSUE_WIDTH + i].data.uuid)) + end + end + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_core.sv b/designs/src/vortex/rtl/core/VX_core.sv new file mode 100644 index 0000000..0e41934 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_core.sv @@ -0,0 +1,292 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifdef EXT_F_ENABLE +`include "VX_fpu_define.vh" +`endif + +module VX_core import VX_gpu_pkg::*; #( + parameter CORE_ID = 0, + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + // Clock + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, +`endif + + VX_dcr_bus_if.slave dcr_bus_if, + + VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS], + + VX_mem_bus_if.master icache_bus_if, + +`ifdef GBAR_ENABLE + VX_gbar_bus_if.master gbar_bus_if, +`endif + + // Status + output wire busy +); + VX_schedule_if schedule_if(); + VX_fetch_if fetch_if(); + VX_decode_if decode_if(); + VX_sched_csr_if sched_csr_if(); + VX_decode_sched_if decode_sched_if(); + VX_issue_sched_if issue_sched_if[`ISSUE_WIDTH](); + VX_commit_sched_if commit_sched_if(); + VX_commit_csr_if commit_csr_if(); + VX_branch_ctl_if branch_ctl_if[`NUM_ALU_BLOCKS](); + VX_warp_ctl_if warp_ctl_if(); + + VX_dispatch_if dispatch_if[NUM_EX_UNITS * `ISSUE_WIDTH](); + VX_commit_if commit_if[NUM_EX_UNITS * `ISSUE_WIDTH](); + VX_writeback_if writeback_if[`ISSUE_WIDTH](); + + VX_lsu_mem_if #( + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LSU_TAG_WIDTH) + ) lsu_mem_if[`NUM_LSU_BLOCKS](); + +`ifdef PERF_ENABLE + lmem_perf_t lmem_perf; + coalescer_perf_t coalescer_perf; + pipeline_perf_t pipeline_perf; + sysmem_perf_t sysmem_perf_tmp; + always @(*) begin + sysmem_perf_tmp = sysmem_perf; + sysmem_perf_tmp.lmem = lmem_perf; + sysmem_perf_tmp.coalescer = coalescer_perf; + end +`endif + + base_dcrs_t base_dcrs; + + VX_dcr_data dcr_data ( + .clk (clk), + .reset (reset), + .dcr_bus_if (dcr_bus_if), + .base_dcrs (base_dcrs) + ); + + `SCOPE_IO_SWITCH (3); + + VX_schedule #( + .INSTANCE_ID (`SFORMATF(("%s-schedule", INSTANCE_ID))), + .CORE_ID (CORE_ID) + ) schedule ( + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .sched_perf (pipeline_perf.sched), + `endif + + .base_dcrs (base_dcrs), + + .warp_ctl_if (warp_ctl_if), + .branch_ctl_if (branch_ctl_if), + + .decode_sched_if(decode_sched_if), + .issue_sched_if (issue_sched_if), + .commit_sched_if(commit_sched_if), + + .schedule_if (schedule_if), + `ifdef GBAR_ENABLE + .gbar_bus_if (gbar_bus_if), + `endif + .sched_csr_if (sched_csr_if), + + .busy (busy) + ); + + VX_fetch #( + .INSTANCE_ID (`SFORMATF(("%s-fetch", INSTANCE_ID))) + ) fetch ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (reset), + .icache_bus_if (icache_bus_if), + .schedule_if (schedule_if), + .fetch_if (fetch_if) + ); + + VX_decode #( + .INSTANCE_ID (`SFORMATF(("%s-decode", INSTANCE_ID))) + ) decode ( + .clk (clk), + .reset (reset), + .fetch_if (fetch_if), + .decode_if (decode_if), + .decode_sched_if(decode_sched_if) + ); + + VX_issue #( + .INSTANCE_ID (`SFORMATF(("%s-issue", INSTANCE_ID))) + ) issue ( + `SCOPE_IO_BIND (1) + + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .issue_perf (pipeline_perf.issue), + `endif + + .decode_if (decode_if), + .writeback_if (writeback_if), + .dispatch_if (dispatch_if), + .issue_sched_if (issue_sched_if) + ); + + VX_execute #( + .INSTANCE_ID (`SFORMATF(("%s-execute", INSTANCE_ID))), + .CORE_ID (CORE_ID) + ) execute ( + `SCOPE_IO_BIND (2) + + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf_tmp), + .pipeline_perf (pipeline_perf), + `endif + + .base_dcrs (base_dcrs), + + .lsu_mem_if (lsu_mem_if), + + .dispatch_if (dispatch_if), + .commit_if (commit_if), + + .commit_csr_if (commit_csr_if), + .sched_csr_if (sched_csr_if), + + .warp_ctl_if (warp_ctl_if), + .branch_ctl_if (branch_ctl_if) + ); + + VX_commit #( + .INSTANCE_ID (`SFORMATF(("%s-commit", INSTANCE_ID))) + ) commit ( + .clk (clk), + .reset (reset), + + .commit_if (commit_if), + + .writeback_if (writeback_if), + + .commit_csr_if (commit_csr_if), + .commit_sched_if(commit_sched_if) + ); + + VX_mem_unit #( + .INSTANCE_ID (INSTANCE_ID) + ) mem_unit ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .lmem_perf (lmem_perf), + .coalescer_perf(coalescer_perf), + `endif + .lsu_mem_if (lsu_mem_if), + .dcache_bus_if (dcache_bus_if) + ); + +`ifdef PERF_ENABLE + + wire [`CLOG2(LSU_NUM_REQS+1)-1:0] perf_dcache_rd_req_per_cycle; + wire [`CLOG2(LSU_NUM_REQS+1)-1:0] perf_dcache_wr_req_per_cycle; + wire [`CLOG2(LSU_NUM_REQS+1)-1:0] perf_dcache_rsp_per_cycle; + + wire [1:0] perf_icache_pending_read_cycle; + wire [`CLOG2(LSU_NUM_REQS+1)+1-1:0] perf_dcache_pending_read_cycle; + + reg [PERF_CTR_BITS-1:0] perf_icache_pending_reads; + reg [PERF_CTR_BITS-1:0] perf_dcache_pending_reads; + + reg [PERF_CTR_BITS-1:0] perf_ifetches; + reg [PERF_CTR_BITS-1:0] perf_loads; + reg [PERF_CTR_BITS-1:0] perf_stores; + + wire perf_icache_req_fire = icache_bus_if.req_valid && icache_bus_if.req_ready; + wire perf_icache_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready; + + wire [LSU_NUM_REQS-1:0] perf_dcache_rd_req_fire, perf_dcache_rd_req_fire_r; + wire [LSU_NUM_REQS-1:0] perf_dcache_wr_req_fire, perf_dcache_wr_req_fire_r; + wire [LSU_NUM_REQS-1:0] perf_dcache_rsp_fire; + + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_perf_dcache + for (genvar j = 0; j < `NUM_LSU_LANES; ++j) begin : g_j + assign perf_dcache_rd_req_fire[i * `NUM_LSU_LANES + j] = lsu_mem_if[i].req_valid && lsu_mem_if[i].req_data.mask[j] && lsu_mem_if[i].req_ready && ~lsu_mem_if[i].req_data.rw; + assign perf_dcache_wr_req_fire[i * `NUM_LSU_LANES + j] = lsu_mem_if[i].req_valid && lsu_mem_if[i].req_data.mask[j] && lsu_mem_if[i].req_ready && lsu_mem_if[i].req_data.rw; + assign perf_dcache_rsp_fire[i * `NUM_LSU_LANES + j] = lsu_mem_if[i].rsp_valid && lsu_mem_if[i].rsp_data.mask[j] && lsu_mem_if[i].rsp_ready; + end + end + + `BUFFER(perf_dcache_rd_req_fire_r, perf_dcache_rd_req_fire); + `BUFFER(perf_dcache_wr_req_fire_r, perf_dcache_wr_req_fire); + + `POP_COUNT(perf_dcache_rd_req_per_cycle, perf_dcache_rd_req_fire_r); + `POP_COUNT(perf_dcache_wr_req_per_cycle, perf_dcache_wr_req_fire_r); + `POP_COUNT(perf_dcache_rsp_per_cycle, perf_dcache_rsp_fire); + + assign perf_icache_pending_read_cycle = perf_icache_req_fire - perf_icache_rsp_fire; + assign perf_dcache_pending_read_cycle = perf_dcache_rd_req_per_cycle - perf_dcache_rsp_per_cycle; + + always @(posedge clk) begin + if (reset) begin + perf_icache_pending_reads <= '0; + perf_dcache_pending_reads <= '0; + end else begin + perf_icache_pending_reads <= $signed(perf_icache_pending_reads) + PERF_CTR_BITS'($signed(perf_icache_pending_read_cycle)); + perf_dcache_pending_reads <= $signed(perf_dcache_pending_reads) + PERF_CTR_BITS'($signed(perf_dcache_pending_read_cycle)); + end + end + + reg [PERF_CTR_BITS-1:0] perf_icache_lat; + reg [PERF_CTR_BITS-1:0] perf_dcache_lat; + + always @(posedge clk) begin + if (reset) begin + perf_ifetches <= '0; + perf_loads <= '0; + perf_stores <= '0; + perf_icache_lat <= '0; + perf_dcache_lat <= '0; + end else begin + perf_ifetches <= perf_ifetches + PERF_CTR_BITS'(perf_icache_req_fire); + perf_loads <= perf_loads + PERF_CTR_BITS'(perf_dcache_rd_req_per_cycle); + perf_stores <= perf_stores + PERF_CTR_BITS'(perf_dcache_wr_req_per_cycle); + perf_icache_lat <= perf_icache_lat + perf_icache_pending_reads; + perf_dcache_lat <= perf_dcache_lat + perf_dcache_pending_reads; + end + end + + assign pipeline_perf.ifetches = perf_ifetches; + assign pipeline_perf.loads = perf_loads; + assign pipeline_perf.stores = perf_stores; + assign pipeline_perf.ifetch_latency = perf_icache_lat; + assign pipeline_perf.load_latency = perf_dcache_lat; + +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_core_top.sv b/designs/src/vortex/rtl/core/VX_core_top.sv new file mode 100644 index 0000000..6b68c99 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_core_top.sv @@ -0,0 +1,171 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifdef EXT_F_ENABLE +`include "VX_fpu_define.vh" +`endif + +module VX_core_top import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + // Clock + input wire clk, + input wire reset, + + input wire dcr_write_valid, + input wire [VX_DCR_ADDR_WIDTH-1:0] dcr_write_addr, + input wire [VX_DCR_DATA_WIDTH-1:0] dcr_write_data, + + output wire [DCACHE_NUM_REQS-1:0] dcache_req_valid, + output wire [DCACHE_NUM_REQS-1:0] dcache_req_rw, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] dcache_req_byteen, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] dcache_req_addr, + output wire [DCACHE_NUM_REQS-1:0][MEM_FLAGS_WIDTH-1:0] dcache_req_flags, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_req_data, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_TAG_WIDTH-1:0] dcache_req_tag, + input wire [DCACHE_NUM_REQS-1:0] dcache_req_ready, + + input wire [DCACHE_NUM_REQS-1:0] dcache_rsp_valid, + input wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] dcache_rsp_data, + input wire [DCACHE_NUM_REQS-1:0][DCACHE_TAG_WIDTH-1:0] dcache_rsp_tag, + output wire [DCACHE_NUM_REQS-1:0] dcache_rsp_ready, + + output wire icache_req_valid, + output wire icache_req_rw, + output wire [ICACHE_WORD_SIZE-1:0] icache_req_byteen, + output wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr, + output wire [ICACHE_WORD_SIZE*8-1:0] icache_req_data, + output wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag, + input wire icache_req_ready, + + input wire icache_rsp_valid, + input wire [ICACHE_WORD_SIZE*8-1:0] icache_rsp_data, + input wire [ICACHE_TAG_WIDTH-1:0] icache_rsp_tag, + output wire icache_rsp_ready, + +`ifdef GBAR_ENABLE + output wire gbar_req_valid, + output wire [NB_WIDTH-1:0] gbar_req_id, + output wire [NC_WIDTH-1:0] gbar_req_size_m1, + output wire [NC_WIDTH-1:0] gbar_req_core_id, + input wire gbar_req_ready, + input wire gbar_rsp_valid, + input wire [NB_WIDTH-1:0] gbar_rsp_id, +`endif + // Status + output wire busy +); + +`ifdef GBAR_ENABLE + VX_gbar_bus_if gbar_bus_if(); + + assign gbar_req_valid = gbar_bus_if.req_valid; + assign gbar_req_id = gbar_bus_if.req_id; + assign gbar_req_size_m1 = gbar_bus_if.req_size_m1; + assign gbar_req_core_id = gbar_bus_if.req_core_id; + assign gbar_bus_if.req_ready = gbar_req_ready; + assign gbar_bus_if.rsp_valid = gbar_rsp_valid; + assign gbar_bus_if.rsp_id = gbar_rsp_id; +`endif + + VX_dcr_bus_if dcr_bus_if(); + + assign dcr_bus_if.write_valid = dcr_write_valid; + assign dcr_bus_if.write_addr = dcr_write_addr; + assign dcr_bus_if.write_data = dcr_write_data; + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH) + ) dcache_bus_if[DCACHE_NUM_REQS](); + + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin + assign dcache_req_valid[i] = dcache_bus_if[i].req_valid; + assign dcache_req_rw[i] = dcache_bus_if[i].req_data.rw; + assign dcache_req_byteen[i] = dcache_bus_if[i].req_data.byteen; + assign dcache_req_addr[i] = dcache_bus_if[i].req_data.addr; + assign dcache_req_flags[i] = dcache_bus_if[i].req_data.flags; + assign dcache_req_data[i] = dcache_bus_if[i].req_data.data; + assign dcache_req_tag[i] = dcache_bus_if[i].req_data.tag; + assign dcache_bus_if[i].req_ready = dcache_req_ready[i]; + + assign dcache_bus_if[i].rsp_valid = dcache_rsp_valid[i]; + assign dcache_bus_if[i].rsp_data.tag = dcache_rsp_tag[i]; + assign dcache_bus_if[i].rsp_data.data = dcache_rsp_data[i]; + assign dcache_rsp_ready[i] = dcache_bus_if[i].rsp_ready; + end + + VX_mem_bus_if #( + .DATA_SIZE (ICACHE_WORD_SIZE), + .TAG_WIDTH (ICACHE_TAG_WIDTH) + ) icache_bus_if(); + + assign icache_req_valid = icache_bus_if.req_valid; + assign icache_req_rw = icache_bus_if.req_data.rw; + assign icache_req_byteen = icache_bus_if.req_data.byteen; + assign icache_req_addr = icache_bus_if.req_data.addr; + assign icache_req_data = icache_bus_if.req_data.data; + assign icache_req_tag = icache_bus_if.req_data.tag; + assign icache_bus_if.req_ready = icache_req_ready; + `UNUSED_VAR (icache_bus_if.req_data.flags) + + assign icache_bus_if.rsp_valid = icache_rsp_valid; + assign icache_bus_if.rsp_data.tag = icache_rsp_tag; + assign icache_bus_if.rsp_data.data = icache_rsp_data; + assign icache_rsp_ready = icache_bus_if.rsp_ready; + +`ifdef PERF_ENABLE + sysmem_perf_t mem_perf; + assign mem_perf.icache = '0; + assign mem_perf.dcache = '0; + assign mem_perf.l2cache = '0; + assign mem_perf.l3cache = '0; + assign mem_perf.lmem = '0; + assign mem_perf.mem = '0; +`endif + +`ifdef SCOPE + wire [0:0] scope_reset_w = 1'b0; + wire [0:0] scope_bus_in_w = 1'b0; + wire [0:0] scope_bus_out_w; + `UNUSED_VAR (scope_bus_out_w) +`endif + + VX_core #( + .INSTANCE_ID (`SFORMATF(("core"))), + .CORE_ID (CORE_ID) + ) core ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf), + `endif + + .dcr_bus_if (dcr_bus_if), + + .dcache_bus_if (dcache_bus_if), + + .icache_bus_if (icache_bus_if), + + `ifdef GBAR_ENABLE + .gbar_bus_if (gbar_bus_if), + `endif + + .busy (busy) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_csr_data.sv b/designs/src/vortex/rtl/core/VX_csr_data.sv new file mode 100644 index 0000000..96c2973 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_csr_data.sv @@ -0,0 +1,300 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifdef EXT_F_ENABLE +`include "VX_fpu_define.vh" +`endif + +`ifdef XLEN_64 + `define CSR_READ_64(addr, dst, src) \ + addr : dst = `XLEN'(src) +`else + `define CSR_READ_64(addr, dst, src) \ + addr : dst = src[31:0]; \ + addr+12'h80 : dst = 32'(src[$bits(src)-1:32]) +`endif + +module VX_csr_data +import VX_gpu_pkg::*; +`ifdef EXT_F_ENABLE +import VX_fpu_pkg::*; +`endif +#( + parameter `STRING INSTANCE_ID = "", + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + + input base_dcrs_t base_dcrs, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, + input pipeline_perf_t pipeline_perf, +`endif + + VX_commit_csr_if.slave commit_csr_if, + +`ifdef EXT_F_ENABLE + VX_fpu_csr_if.slave fpu_csr_if [`NUM_FPU_BLOCKS], +`endif + + input wire [PERF_CTR_BITS-1:0] cycles, + input wire [`NUM_WARPS-1:0] active_warps, + input wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, + + input wire read_enable, + input wire [UUID_WIDTH-1:0] read_uuid, + input wire [NW_WIDTH-1:0] read_wid, + input wire [`VX_CSR_ADDR_BITS-1:0] read_addr, + output wire [`XLEN-1:0] read_data_ro, + output wire [`XLEN-1:0] read_data_rw, + + input wire write_enable, + input wire [UUID_WIDTH-1:0] write_uuid, + input wire [NW_WIDTH-1:0] write_wid, + input wire [`VX_CSR_ADDR_BITS-1:0] write_addr, + input wire [`XLEN-1:0] write_data +); + + `UNUSED_VAR (reset) + `UNUSED_VAR (write_wid) + `UNUSED_VAR (write_data) + + // CSRs Write ///////////////////////////////////////////////////////////// + + reg [`XLEN-1:0] mscratch; + +`ifdef EXT_F_ENABLE + reg [`NUM_WARPS-1:0][INST_FRM_BITS+`FP_FLAGS_BITS-1:0] fcsr, fcsr_n; + wire [`NUM_FPU_BLOCKS-1:0] fpu_write_enable; + wire [`NUM_FPU_BLOCKS-1:0][NW_WIDTH-1:0] fpu_write_wid; + fflags_t [`NUM_FPU_BLOCKS-1:0] fpu_write_fflags; + + for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin : g_fpu_write + assign fpu_write_enable[i] = fpu_csr_if[i].write_enable; + assign fpu_write_wid[i] = fpu_csr_if[i].write_wid; + assign fpu_write_fflags[i] = fpu_csr_if[i].write_fflags; + end + + always @(*) begin + fcsr_n = fcsr; + for (integer i = 0; i < `NUM_FPU_BLOCKS; ++i) begin + if (fpu_write_enable[i]) begin + fcsr_n[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] = fcsr[fpu_write_wid[i]][`FP_FLAGS_BITS-1:0] + | fpu_write_fflags[i]; + end + end + if (write_enable) begin + case (write_addr) + `VX_CSR_FFLAGS: fcsr_n[write_wid][`FP_FLAGS_BITS-1:0] = write_data[`FP_FLAGS_BITS-1:0]; + `VX_CSR_FRM: fcsr_n[write_wid][INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS] = write_data[INST_FRM_BITS-1:0]; + `VX_CSR_FCSR: fcsr_n[write_wid] = write_data[`FP_FLAGS_BITS+INST_FRM_BITS-1:0]; + default:; + endcase + end + end + + for (genvar i = 0; i < `NUM_FPU_BLOCKS; ++i) begin : g_fpu_csr_read_frm + assign fpu_csr_if[i].read_frm = fcsr[fpu_csr_if[i].read_wid][INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]; + end + + always @(posedge clk) begin + if (reset) begin + fcsr <= '0; + end else begin + fcsr <= fcsr_n; + end + end +`endif + + always @(posedge clk) begin + if (reset) begin + mscratch <= base_dcrs.startup_arg; + end + if (write_enable) begin + case (write_addr) + `ifdef EXT_F_ENABLE + `VX_CSR_FFLAGS, + `VX_CSR_FRM, + `VX_CSR_FCSR, + `endif + `VX_CSR_SATP, + `VX_CSR_MSTATUS, + `VX_CSR_MNSTATUS, + `VX_CSR_MEDELEG, + `VX_CSR_MIDELEG, + `VX_CSR_MIE, + `VX_CSR_MTVEC, + `VX_CSR_MEPC, + `VX_CSR_PMPCFG0, + `VX_CSR_PMPADDR0: begin + // do nothing! + end + `VX_CSR_MSCRATCH: begin + mscratch <= write_data; + end + default: begin + `ASSERT(0, ("%t: *** %s invalid CSR write address: %0h (#%0d)", $time, INSTANCE_ID, write_addr, write_uuid)); + end + endcase + end + end + + // CSRs read ////////////////////////////////////////////////////////////// + + reg [`XLEN-1:0] read_data_ro_w; + reg [`XLEN-1:0] read_data_rw_w; + reg read_addr_valid_w; + + always @(*) begin + read_data_ro_w = '0; + read_data_rw_w = '0; + read_addr_valid_w = 1; + case (read_addr) + `VX_CSR_MVENDORID : read_data_ro_w = `XLEN'(`VENDOR_ID); + `VX_CSR_MARCHID : read_data_ro_w = `XLEN'(`ARCHITECTURE_ID); + `VX_CSR_MIMPID : read_data_ro_w = `XLEN'(`IMPLEMENTATION_ID); + `VX_CSR_MISA : read_data_ro_w = `XLEN'({2'(`CLOG2(`XLEN/16)), 30'(`MISA_STD)}); + `ifdef EXT_F_ENABLE + `VX_CSR_FFLAGS : read_data_rw_w = `XLEN'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]); + `VX_CSR_FRM : read_data_rw_w = `XLEN'(fcsr[read_wid][INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]); + `VX_CSR_FCSR : read_data_rw_w = `XLEN'(fcsr[read_wid]); + `endif + `VX_CSR_MSCRATCH : read_data_rw_w = mscratch; + + `VX_CSR_WARP_ID : read_data_ro_w = `XLEN'(read_wid); + `VX_CSR_CORE_ID : read_data_ro_w = `XLEN'(CORE_ID); + `VX_CSR_ACTIVE_THREADS: read_data_ro_w = `XLEN'(thread_masks[read_wid]); + `VX_CSR_ACTIVE_WARPS: read_data_ro_w = `XLEN'(active_warps); + `VX_CSR_NUM_THREADS: read_data_ro_w = `XLEN'(`NUM_THREADS); + `VX_CSR_NUM_WARPS : read_data_ro_w = `XLEN'(`NUM_WARPS); + `VX_CSR_NUM_CORES : read_data_ro_w = `XLEN'(`NUM_CORES * `NUM_CLUSTERS); + `VX_CSR_LOCAL_MEM_BASE: read_data_ro_w = `XLEN'(`LMEM_BASE_ADDR); + + `CSR_READ_64(`VX_CSR_MCYCLE, read_data_ro_w, cycles); + + `VX_CSR_MPM_RESERVED : read_data_ro_w = 'x; + `VX_CSR_MPM_RESERVED_H : read_data_ro_w = 'x; + + `CSR_READ_64(`VX_CSR_MINSTRET, read_data_ro_w, commit_csr_if.instret); + + `VX_CSR_SATP, + `VX_CSR_MSTATUS, + `VX_CSR_MNSTATUS, + `VX_CSR_MEDELEG, + `VX_CSR_MIDELEG, + `VX_CSR_MIE, + `VX_CSR_MTVEC, + `VX_CSR_MEPC, + `VX_CSR_PMPCFG0, + `VX_CSR_PMPADDR0 : read_data_ro_w = `XLEN'(0); + + default: begin + read_addr_valid_w = 0; + if ((read_addr >= `VX_CSR_MPM_USER && read_addr < (`VX_CSR_MPM_USER + 32)) + || (read_addr >= `VX_CSR_MPM_USER_H && read_addr < (`VX_CSR_MPM_USER_H + 32))) begin + read_addr_valid_w = 1; + `ifdef PERF_ENABLE + case (base_dcrs.mpm_class) + `VX_DCR_MPM_CLASS_CORE: begin + case (read_addr) + // PERF: pipeline + `CSR_READ_64(`VX_CSR_MPM_SCHED_ID, read_data_ro_w, pipeline_perf.sched.idles); + `CSR_READ_64(`VX_CSR_MPM_SCHED_ST, read_data_ro_w, pipeline_perf.sched.stalls); + `CSR_READ_64(`VX_CSR_MPM_IBUF_ST, read_data_ro_w, pipeline_perf.issue.ibf_stalls); + `CSR_READ_64(`VX_CSR_MPM_SCRB_ST, read_data_ro_w, pipeline_perf.issue.scb_stalls); + `CSR_READ_64(`VX_CSR_MPM_OPDS_ST, read_data_ro_w, pipeline_perf.issue.opd_stalls); + `CSR_READ_64(`VX_CSR_MPM_SCRB_ALU, read_data_ro_w, pipeline_perf.issue.units_uses[EX_ALU]); + `CSR_READ_64(`VX_CSR_MPM_SCRB_LSU, read_data_ro_w, pipeline_perf.issue.units_uses[EX_LSU]); + `CSR_READ_64(`VX_CSR_MPM_SCRB_SFU, read_data_ro_w, pipeline_perf.issue.units_uses[EX_SFU]); + `ifdef EXT_F_ENABLE + `CSR_READ_64(`VX_CSR_MPM_SCRB_FPU, read_data_ro_w, pipeline_perf.issue.units_uses[EX_FPU]); + `endif + `ifdef EXT_TCU_ENABLE + `CSR_READ_64(`VX_CSR_MPM_SCRB_TCU, read_data_ro_w, pipeline_perf.issue.units_uses[EX_TCU]); + `endif + `CSR_READ_64(`VX_CSR_MPM_SCRB_CSRS, read_data_ro_w, pipeline_perf.issue.sfu_uses[SFU_CSRS]); + `CSR_READ_64(`VX_CSR_MPM_SCRB_WCTL, read_data_ro_w, pipeline_perf.issue.sfu_uses[SFU_WCTL]); + // PERF: memory + `CSR_READ_64(`VX_CSR_MPM_IFETCHES, read_data_ro_w, pipeline_perf.ifetches); + `CSR_READ_64(`VX_CSR_MPM_LOADS, read_data_ro_w, pipeline_perf.loads); + `CSR_READ_64(`VX_CSR_MPM_STORES, read_data_ro_w, pipeline_perf.stores); + `CSR_READ_64(`VX_CSR_MPM_IFETCH_LT, read_data_ro_w, pipeline_perf.ifetch_latency); + `CSR_READ_64(`VX_CSR_MPM_LOAD_LT, read_data_ro_w, pipeline_perf.load_latency); + default:; + endcase + end + `VX_DCR_MPM_CLASS_MEM: begin + case (read_addr) + // PERF: icache + `CSR_READ_64(`VX_CSR_MPM_ICACHE_READS, read_data_ro_w, sysmem_perf.icache.reads); + `CSR_READ_64(`VX_CSR_MPM_ICACHE_MISS_R, read_data_ro_w, sysmem_perf.icache.read_misses); + `CSR_READ_64(`VX_CSR_MPM_ICACHE_MSHR_ST, read_data_ro_w, sysmem_perf.icache.mshr_stalls); + // PERF: dcache + `CSR_READ_64(`VX_CSR_MPM_DCACHE_READS, read_data_ro_w, sysmem_perf.dcache.reads); + `CSR_READ_64(`VX_CSR_MPM_DCACHE_WRITES, read_data_ro_w, sysmem_perf.dcache.writes); + `CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_R, read_data_ro_w, sysmem_perf.dcache.read_misses); + `CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_W, read_data_ro_w, sysmem_perf.dcache.write_misses); + `CSR_READ_64(`VX_CSR_MPM_DCACHE_BANK_ST, read_data_ro_w, sysmem_perf.dcache.bank_stalls); + `CSR_READ_64(`VX_CSR_MPM_DCACHE_MSHR_ST, read_data_ro_w, sysmem_perf.dcache.mshr_stalls); + // PERF: lmem + `CSR_READ_64(`VX_CSR_MPM_LMEM_READS, read_data_ro_w, sysmem_perf.lmem.reads); + `CSR_READ_64(`VX_CSR_MPM_LMEM_WRITES, read_data_ro_w, sysmem_perf.lmem.writes); + `CSR_READ_64(`VX_CSR_MPM_LMEM_BANK_ST, read_data_ro_w, sysmem_perf.lmem.bank_stalls); + // PERF: l2cache + `CSR_READ_64(`VX_CSR_MPM_L2CACHE_READS, read_data_ro_w, sysmem_perf.l2cache.reads); + `CSR_READ_64(`VX_CSR_MPM_L2CACHE_WRITES, read_data_ro_w, sysmem_perf.l2cache.writes); + `CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_R, read_data_ro_w, sysmem_perf.l2cache.read_misses); + `CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_W, read_data_ro_w, sysmem_perf.l2cache.write_misses); + `CSR_READ_64(`VX_CSR_MPM_L2CACHE_BANK_ST, read_data_ro_w, sysmem_perf.l2cache.bank_stalls); + `CSR_READ_64(`VX_CSR_MPM_L2CACHE_MSHR_ST, read_data_ro_w, sysmem_perf.l2cache.mshr_stalls); + // PERF: l3cache + `CSR_READ_64(`VX_CSR_MPM_L3CACHE_READS, read_data_ro_w, sysmem_perf.l3cache.reads); + `CSR_READ_64(`VX_CSR_MPM_L3CACHE_WRITES, read_data_ro_w, sysmem_perf.l3cache.writes); + `CSR_READ_64(`VX_CSR_MPM_L3CACHE_MISS_R, read_data_ro_w, sysmem_perf.l3cache.read_misses); + `CSR_READ_64(`VX_CSR_MPM_L3CACHE_MISS_W, read_data_ro_w, sysmem_perf.l3cache.write_misses); + `CSR_READ_64(`VX_CSR_MPM_L3CACHE_BANK_ST, read_data_ro_w, sysmem_perf.l3cache.bank_stalls); + `CSR_READ_64(`VX_CSR_MPM_L3CACHE_MSHR_ST, read_data_ro_w, sysmem_perf.l3cache.mshr_stalls); + // PERF: memory + `CSR_READ_64(`VX_CSR_MPM_MEM_READS, read_data_ro_w, sysmem_perf.mem.reads); + `CSR_READ_64(`VX_CSR_MPM_MEM_WRITES, read_data_ro_w, sysmem_perf.mem.writes); + `CSR_READ_64(`VX_CSR_MPM_MEM_LT, read_data_ro_w, sysmem_perf.mem.latency); + // PERF: coalescer + `CSR_READ_64(`VX_CSR_MPM_COALESCER_MISS, read_data_ro_w, sysmem_perf.coalescer.misses); + default:; + endcase + end + default:; + endcase + `endif + end + end + endcase + end + + assign read_data_ro = read_data_ro_w; + assign read_data_rw = read_data_rw_w; + + `UNUSED_VAR (base_dcrs) + + `RUNTIME_ASSERT(~read_enable || read_addr_valid_w, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid)) + +`ifdef PERF_ENABLE + `UNUSED_VAR (sysmem_perf.icache); + `UNUSED_VAR (sysmem_perf.lmem); +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_csr_unit.sv b/designs/src/vortex/rtl/core/VX_csr_unit.sv new file mode 100644 index 0000000..b395071 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_csr_unit.sv @@ -0,0 +1,178 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_csr_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter CORE_ID = 0, + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + input base_dcrs_t base_dcrs, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, + input pipeline_perf_t pipeline_perf, +`endif + +`ifdef EXT_F_ENABLE + VX_fpu_csr_if.slave fpu_csr_if [`NUM_FPU_BLOCKS], +`endif + + VX_commit_csr_if.slave commit_csr_if, + VX_sched_csr_if.slave sched_csr_if, + VX_execute_if.slave execute_if, + VX_result_if.master result_if +); + `UNUSED_SPARAM (INSTANCE_ID) + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam DATAW = UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + NUM_REGS_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1; + + `UNUSED_VAR (execute_if.data.rs3_data) + + reg [NUM_LANES-1:0][`XLEN-1:0] csr_read_data; + reg [`XLEN-1:0] csr_write_data; + wire [`XLEN-1:0] csr_read_data_ro, csr_read_data_rw; + wire [`XLEN-1:0] csr_req_data; + reg csr_rd_enable; + wire csr_wr_enable; + wire csr_req_ready; + + wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.op_args.csr.addr; + wire [RV_REGS_BITS-1:0] csr_imm = execute_if.data.op_args.csr.imm; + + wire is_fpu_csr = (csr_addr <= `VX_CSR_FCSR); + + // wait for all pending instructions for current warp to complete + assign sched_csr_if.alm_empty_wid = execute_if.data.wid; + wire no_pending_instr = sched_csr_if.alm_empty || ~is_fpu_csr; + + wire csr_req_valid = execute_if.valid && no_pending_instr; + assign execute_if.ready = csr_req_ready && no_pending_instr; + + wire [NUM_LANES-1:0][`XLEN-1:0] rs1_data; + `UNUSED_VAR (rs1_data) + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_rs1_data + assign rs1_data[i] = execute_if.data.rs1_data[i]; + end + + wire csr_write_enable = (execute_if.data.op_type == INST_SFU_CSRRW); + + VX_csr_data #( + .INSTANCE_ID (INSTANCE_ID), + .CORE_ID (CORE_ID) + ) csr_data ( + .clk (clk), + .reset (reset), + + .base_dcrs (base_dcrs), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf), + .pipeline_perf (pipeline_perf), + `endif + + .commit_csr_if (commit_csr_if), + .cycles (sched_csr_if.cycles), + .active_warps (sched_csr_if.active_warps), + .thread_masks (sched_csr_if.thread_masks), + + `ifdef EXT_F_ENABLE + .fpu_csr_if (fpu_csr_if), + `endif + + .read_enable (csr_req_valid && csr_rd_enable), + .read_uuid (execute_if.data.uuid), + .read_wid (execute_if.data.wid), + .read_addr (csr_addr), + .read_data_ro (csr_read_data_ro), + .read_data_rw (csr_read_data_rw), + + .write_enable (csr_req_valid && csr_wr_enable), + .write_uuid (execute_if.data.uuid), + .write_wid (execute_if.data.wid), + .write_addr (csr_addr), + .write_data (csr_write_data) + ); + + // CSR read + + wire [NUM_LANES-1:0][`XLEN-1:0] wtid, gtid; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_wtid + if (PID_BITS != 0) begin : g_pid + assign wtid[i] = `XLEN'(execute_if.data.pid * NUM_LANES + i); + end else begin : g_no_pid + assign wtid[i] = `XLEN'(i); + end + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_gtid + assign gtid[i] = (`XLEN'(CORE_ID) << (NW_BITS + NT_BITS)) + (`XLEN'(execute_if.data.wid) << NT_BITS) + wtid[i]; + end + + always @(*) begin + csr_rd_enable = 0; + case (csr_addr) + `VX_CSR_THREAD_ID : csr_read_data = wtid; + `VX_CSR_MHARTID : csr_read_data = gtid; + default : begin + csr_read_data = {NUM_LANES{csr_read_data_ro | csr_read_data_rw}}; + csr_rd_enable = 1; + end + endcase + end + + // CSR write + + assign csr_req_data = execute_if.data.op_args.csr.use_imm ? `XLEN'(csr_imm) : rs1_data[0]; + assign csr_wr_enable = csr_write_enable || (| csr_req_data); + + always @(*) begin + case (execute_if.data.op_type) + INST_SFU_CSRRW: begin + csr_write_data = csr_req_data; + end + INST_SFU_CSRRS: begin + csr_write_data = csr_read_data_rw | csr_req_data; + end + //INST_SFU_CSRRC + default: begin + csr_write_data = csr_read_data_rw & ~csr_req_data; + end + endcase + end + + // unlock the warp + assign sched_csr_if.unlock_warp = csr_req_valid && csr_req_ready && execute_if.data.eop && is_fpu_csr; + assign sched_csr_if.unlock_wid = execute_if.data.wid; + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (csr_req_valid), + .ready_in (csr_req_ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, csr_read_data, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}), + .data_out ({result_if.data.uuid, result_if.data.wid, result_if.data.tmask, result_if.data.PC, result_if.data.rd, result_if.data.wb, result_if.data.data, result_if.data.pid, result_if.data.sop, result_if.data.eop}), + .valid_out (result_if.valid), + .ready_out (result_if.ready) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_dcr_data.sv b/designs/src/vortex/rtl/core/VX_dcr_data.sv new file mode 100644 index 0000000..7a566b0 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_dcr_data.sv @@ -0,0 +1,60 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_dcr_data import VX_gpu_pkg::*; ( + input wire clk, + input wire reset, + + // Inputs + VX_dcr_bus_if.slave dcr_bus_if, + + // Outputs + output base_dcrs_t base_dcrs +); + + `UNUSED_VAR (reset) + + base_dcrs_t dcrs; + + always @(posedge clk) begin + if (dcr_bus_if.write_valid) begin + case (dcr_bus_if.write_addr) + `VX_DCR_BASE_STARTUP_ADDR0 : dcrs.startup_addr[31:0] <= dcr_bus_if.write_data; + `ifdef XLEN_64 + `VX_DCR_BASE_STARTUP_ADDR1 : dcrs.startup_addr[63:32] <= dcr_bus_if.write_data; + `endif + `VX_DCR_BASE_STARTUP_ARG0 : dcrs.startup_arg[31:0] <= dcr_bus_if.write_data; + `ifdef XLEN_64 + `VX_DCR_BASE_STARTUP_ARG1 : dcrs.startup_arg[63:32] <= dcr_bus_if.write_data; + `endif + `VX_DCR_BASE_MPM_CLASS : dcrs.mpm_class <= dcr_bus_if.write_data[7:0]; + default:; + endcase + end + end + + assign base_dcrs = dcrs; + +`ifdef DBG_TRACE_PIPELINE + always @(posedge clk) begin + if (dcr_bus_if.write_valid) begin + `TRACE(2, ("%t: base-dcr: state=", $time)) + VX_trace_pkg::trace_base_dcr(1, dcr_bus_if.write_addr); + `TRACE(2, (", data=0x%h\n", dcr_bus_if.write_data)) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_decode.sv b/designs/src/vortex/rtl/core/VX_decode.sv new file mode 100644 index 0000000..6669f26 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_decode.sv @@ -0,0 +1,575 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`define USED_REG(t, x) \ + x``_v = make_reg_num(t, ``x); \ + use_``x = 1 + +`define USED_IREG(x) \ + `USED_REG(REG_TYPE_I, ``x) + +`define USED_FREG(x) \ + `USED_REG(REG_TYPE_F, ``x) + +module VX_decode import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + + // inputs + VX_fetch_if.slave fetch_if, + + // outputs + VX_decode_if.master decode_if, + VX_decode_sched_if.master decode_sched_if +); + + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + localparam OUT_DATAW = $bits(decode_t); + + reg [EX_BITS-1:0] ex_type; + reg [INST_OP_BITS-1:0] op_type; + op_args_t op_args; + reg [NUM_REGS_BITS-1:0] rd_v, rs1_v, rs2_v, rs3_v; + reg use_rd, use_rs1, use_rs2, use_rs3; + reg is_wstall; + + wire [31:0] instr = fetch_if.data.instr; + wire [6:0] opcode = instr[6:0]; + wire [1:0] funct2 = instr[26:25]; + wire [2:0] funct3 = instr[14:12]; + wire [4:0] funct5 = instr[31:27]; + wire [6:0] funct7 = instr[31:25]; + wire [11:0] u_12 = instr[31:20]; + + wire [4:0] rd = instr[11:7]; + wire [4:0] rs1 = instr[19:15]; + wire [4:0] rs2 = instr[24:20]; + wire [4:0] rs3 = instr[31:27]; + + `UNUSED_VAR (funct2) + `UNUSED_VAR (funct5) + `UNUSED_VAR (rs3) + `UNUSED_VAR (use_rd) + `UNUSED_VAR (use_rs1) + `UNUSED_VAR (use_rs2) + `UNUSED_VAR (use_rs3) + + wire is_itype_sh = funct3[0] && ~funct3[1]; + wire is_fpu_csr = (u_12 <= `VX_CSR_FCSR); + + wire [19:0] ui_imm = instr[31:12]; +`ifdef XLEN_64 + wire [11:0] i_imm = is_itype_sh ? {6'b0, instr[25:20]} : u_12; + wire [11:0] iw_imm = is_itype_sh ? {7'b0, instr[24:20]} : u_12; +`else + wire [11:0] i_imm = is_itype_sh ? {7'b0, instr[24:20]} : u_12; +`endif + wire [11:0] s_imm = {funct7, rd}; + wire [12:0] b_imm = {instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; + wire [20:0] jal_imm = {instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; + + reg [INST_ALU_BITS-1:0] r_type; + always @(*) begin + case (funct3) + 3'h0: r_type = (opcode[5] && funct7[5]) ? INST_ALU_SUB : INST_ALU_ADD; + 3'h1: r_type = INST_ALU_SLL; + 3'h2: r_type = INST_ALU_SLT; + 3'h3: r_type = INST_ALU_SLTU; + 3'h4: r_type = INST_ALU_XOR; + 3'h5: r_type = funct7[5] ? INST_ALU_SRA : INST_ALU_SRL; + 3'h6: r_type = INST_ALU_OR; + 3'h7: r_type = INST_ALU_AND; + endcase + end + + reg [INST_BR_BITS-1:0] b_type; + always @(*) begin + case (funct3) + 3'h0: b_type = INST_BR_BEQ; + 3'h1: b_type = INST_BR_BNE; + 3'h4: b_type = INST_BR_BLT; + 3'h5: b_type = INST_BR_BGE; + 3'h6: b_type = INST_BR_BLTU; + 3'h7: b_type = INST_BR_BGEU; + default: b_type = 'x; + endcase + end + + reg [INST_BR_BITS-1:0] s_type; + always @(*) begin + case (u_12) + 12'h000: s_type = INST_OP_BITS'(INST_BR_ECALL); + 12'h001: s_type = INST_OP_BITS'(INST_BR_EBREAK); + 12'h002: s_type = INST_OP_BITS'(INST_BR_URET); + 12'h102: s_type = INST_OP_BITS'(INST_BR_SRET); + 12'h302: s_type = INST_OP_BITS'(INST_BR_MRET); + default: s_type = 'x; + endcase + end + +`ifdef EXT_M_ENABLE + reg [INST_M_BITS-1:0] m_type; + always @(*) begin + case (funct3) + 3'h0: m_type = INST_M_MUL; + 3'h1: m_type = INST_M_MULH; + 3'h2: m_type = INST_M_MULHSU; + 3'h3: m_type = INST_M_MULHU; + 3'h4: m_type = INST_M_DIV; + 3'h5: m_type = INST_M_DIVU; + 3'h6: m_type = INST_M_REM; + 3'h7: m_type = INST_M_REMU; + endcase + end +`endif + + always @(*) begin + + ex_type = 'x; + op_type = 'x; + op_args = 'x; + rd_v = 'x; + rs1_v = 'x; + rs2_v = 'x; + rs3_v = 'x; + use_rd = 0; + use_rs1 = 0; + use_rs2 = 0; + use_rs3 = 0; + is_wstall = 0; + + case (opcode) + INST_I: begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(r_type); + op_args.alu.xtype = ALU_TYPE_ARITH; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 0; + op_args.alu.use_imm = 1; + op_args.alu.imm = `SEXT(`XLEN, i_imm); + `USED_IREG (rd); + `USED_IREG (rs1); + end + INST_R: begin + ex_type = EX_ALU; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 0; + op_args.alu.use_imm = 0; + `USED_IREG (rd); + `USED_IREG (rs1); + `USED_IREG (rs2); + case (funct7) + `ifdef EXT_M_ENABLE + INST_R_F7_MUL: begin + // MUL, MULH, MULHSU, MULHU + op_type = INST_OP_BITS'(m_type); + op_args.alu.xtype = ALU_TYPE_MULDIV; + end + `endif + `ifdef EXT_ZICOND_ENABLE + INST_R_F7_ZICOND: begin + // CZERO-EQZ, CZERO-NEZ + op_type = funct3[1] ? INST_OP_BITS'(INST_ALU_CZNE) : INST_OP_BITS'(INST_ALU_CZEQ); + op_args.alu.xtype = ALU_TYPE_ARITH; + end + `endif + default: begin + op_type = INST_OP_BITS'(r_type); + op_args.alu.xtype = ALU_TYPE_ARITH; + end + endcase + end + `ifdef XLEN_64 + INST_I_W: begin + // ADDIW, SLLIW, SRLIW, SRAIW + ex_type = EX_ALU; + op_type = INST_OP_BITS'(r_type); + op_args.alu.xtype = ALU_TYPE_ARITH; + op_args.alu.is_w = 1; + op_args.alu.use_PC = 0; + op_args.alu.use_imm = 1; + op_args.alu.imm = `SEXT(`XLEN, iw_imm); + `USED_IREG (rd); + `USED_IREG (rs1); + end + INST_R_W: begin + ex_type = EX_ALU; + op_args.alu.is_w = 1; + op_args.alu.use_PC = 0; + op_args.alu.use_imm = 0; + `USED_IREG (rd); + `USED_IREG (rs1); + `USED_IREG (rs2); + case (funct7) + `ifdef EXT_M_ENABLE + INST_R_F7_MUL: begin + // MULW, DIVW, DIVUW, REMW, REMUW + op_type = INST_OP_BITS'(m_type); + op_args.alu.xtype = ALU_TYPE_MULDIV; + end + `endif + default: begin + // ADDW, SUBW, SLLW, SRLW, SRAW + op_type = INST_OP_BITS'(r_type); + op_args.alu.xtype = ALU_TYPE_ARITH; + end + endcase + end + `endif + INST_LUI: begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(INST_ALU_LUI); + op_args.alu.xtype = ALU_TYPE_ARITH; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 0; + op_args.alu.use_imm = 1; + op_args.alu.imm = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)}; + `USED_IREG (rd); + end + INST_AUIPC: begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(INST_ALU_AUIPC); + op_args.alu.xtype = ALU_TYPE_ARITH; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 1; + op_args.alu.use_imm = 1; + op_args.alu.imm = {{`XLEN-31{ui_imm[19]}}, ui_imm[18:0], 12'(0)}; + `USED_IREG (rd); + end + INST_JAL: begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(INST_BR_JAL); + op_args.alu.xtype = ALU_TYPE_BRANCH; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 1; + op_args.alu.use_imm = 1; + op_args.alu.imm = `SEXT(`XLEN, jal_imm); + is_wstall = 1; + `USED_IREG (rd); + end + INST_JALR: begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(INST_BR_JALR); + op_args.alu.xtype = ALU_TYPE_BRANCH; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 0; + op_args.alu.use_imm = 1; + op_args.alu.imm = `SEXT(`XLEN, u_12); + is_wstall = 1; + `USED_IREG (rd); + `USED_IREG (rs1); + end + INST_B: begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(b_type); + op_args.alu.xtype = ALU_TYPE_BRANCH; + op_args.alu.is_w = 0; + op_args.alu.use_PC = 1; + op_args.alu.use_imm = 1; + op_args.alu.imm = `SEXT(`XLEN, b_imm); + is_wstall = 1; + `USED_IREG (rs1); + `USED_IREG (rs2); + end + INST_FENCE: begin + ex_type = EX_LSU; + op_type = INST_LSU_FENCE; + op_args.lsu.is_store = 0; + op_args.lsu.is_float = 0; + op_args.lsu.offset = 0; + end + INST_SYS : begin + if (funct3[1:0] != 0) begin + ex_type = EX_SFU; + op_type = INST_OP_BITS'(inst_sfu_csr(funct3)); + op_args.csr.addr = u_12; + op_args.csr.use_imm = funct3[2]; + is_wstall = is_fpu_csr; // only stall for FPU CSRs + `USED_IREG (rd); + if (funct3[2]) begin + op_args.csr.imm = rs1; + end else begin + `USED_IREG (rs1); + end + end else begin + ex_type = EX_ALU; + op_type = INST_OP_BITS'(s_type); + op_args.alu.xtype = ALU_TYPE_BRANCH; + op_args.alu.is_w = 0; + op_args.alu.use_imm = 1; + op_args.alu.use_PC = 1; + op_args.alu.imm = `XLEN'd4; + is_wstall = 1; + `USED_IREG (rd); + end + end + `ifdef EXT_F_ENABLE + INST_FL, + `endif + INST_L: begin + ex_type = EX_LSU; + op_type = INST_OP_BITS'({1'b0, funct3}); + op_args.lsu.is_store = 0; + op_args.lsu.is_float = opcode[2]; + op_args.lsu.offset = u_12; + `USED_IREG (rs1); + `ifdef EXT_F_ENABLE + `USED_REG (opcode[2], rd); + `else + `USED_IREG (rd); + `endif + end + `ifdef EXT_F_ENABLE + INST_FS, + `endif + INST_S: begin + ex_type = EX_LSU; + op_type = INST_OP_BITS'({1'b1, funct3}); + op_args.lsu.is_store = 1; + op_args.lsu.is_float = opcode[2]; + op_args.lsu.offset = s_imm; + `USED_IREG (rs1); + `ifdef EXT_F_ENABLE + `USED_REG (opcode[2], rs2); + `else + `USED_IREG (rs2); + `endif + end + `ifdef EXT_F_ENABLE + INST_FMADD, // 7'b1000011 + INST_FMSUB, // 7'b1000111 + INST_FNMSUB, // 7'b1001011 + INST_FNMADD: // 7'b1001111 + begin + ex_type = EX_FPU; + op_type = INST_OP_BITS'({2'b00, 1'b1, opcode[3]}); + op_args.fpu.frm = funct3; + op_args.fpu.fmt[0] = funct2[0]; // float/double + op_args.fpu.fmt[1] = opcode[3] ^ opcode[2]; // SUB + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + `USED_FREG (rs3); + end + INST_FCI: begin + ex_type = EX_FPU; + op_args.fpu.frm = funct3; + op_args.fpu.fmt[0] = funct2[0]; // float/double + op_args.fpu.fmt[1] = rs2[1]; // CVT W/L + + case (funct5) + 5'b00000, // FADD + 5'b00001, // FSUB + 5'b00010: // FMUL + begin + op_type = INST_OP_BITS'({2'b00, 1'b0, funct5[1]}); + op_args.fpu.fmt[1] = funct5[0]; // SUB + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b00100: begin + // NCP: FSGNJ=0, FSGNJN=1, FSGNJX=2 + op_type = INST_OP_BITS'(INST_FPU_MISC); + op_args.fpu.frm = INST_FRM_BITS'(funct3[1:0]); + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b00101: begin + // NCP: FMIN=6, FMAX=7 + op_type = INST_OP_BITS'(INST_FPU_MISC); + op_args.fpu.frm = INST_FRM_BITS'(funct3[0] ? 7 : 6); + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + `ifdef FLEN_64 + 5'b01000: begin + // FCVT.S.D, FCVT.D.S + op_type = INST_OP_BITS'(INST_FPU_F2F); + `USED_FREG (rd); + `USED_FREG (rs1); + end + `endif + 5'b00011: begin + // FDIV + op_type = INST_OP_BITS'(INST_FPU_DIV); + `USED_FREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b01011: begin + // FSQRT + op_type = INST_OP_BITS'(INST_FPU_SQRT); + `USED_FREG (rd); + `USED_FREG (rs1); + end + 5'b10100: begin + // FCMP + op_type = INST_OP_BITS'(INST_FPU_CMP); + `USED_IREG (rd); + `USED_FREG (rs1); + `USED_FREG (rs2); + end + 5'b11000: begin + // FCVT.W.X, FCVT.WU.X + op_type = (rs2[0]) ? INST_OP_BITS'(INST_FPU_F2U) : INST_OP_BITS'(INST_FPU_F2I); + `USED_IREG (rd); + `USED_FREG (rs1); + end + 5'b11010: begin + // FCVT.X.W, FCVT.X.WU + op_type = (rs2[0]) ? INST_OP_BITS'(INST_FPU_U2F) : INST_OP_BITS'(INST_FPU_I2F); + `USED_FREG (rd); + `USED_IREG (rs1); + end + 5'b11100: begin + if (funct3[0]) begin + // NCP: FCLASS=3 + op_type = INST_OP_BITS'(INST_FPU_MISC); + op_args.fpu.frm = INST_FRM_BITS'(3); + end else begin + // NCP: FMV.X.W=4 + op_type = INST_OP_BITS'(INST_FPU_MISC); + op_args.fpu.frm = INST_FRM_BITS'(4); + end + `USED_IREG (rd); + `USED_FREG (rs1); + end + 5'b11110: begin + // NCP: FMV.W.X=5 + op_type = INST_OP_BITS'(INST_FPU_MISC); + op_args.fpu.frm = INST_FRM_BITS'(5); + `USED_FREG (rd); + `USED_IREG (rs1); + end + default:; + endcase + end + `endif + INST_EXT1: begin + case (funct7) + 7'h00: begin + ex_type = EX_SFU; + is_wstall = 1; + case (funct3) + 3'h0: begin // TMC + op_type = INST_OP_BITS'(INST_SFU_TMC); + `USED_IREG (rs1); + end + 3'h1: begin // WSPAWN + op_type = INST_OP_BITS'(INST_SFU_WSPAWN); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + 3'h2: begin // SPLIT + op_type = INST_OP_BITS'(INST_SFU_SPLIT); + op_args.wctl.is_neg = rs2[0]; + `USED_IREG (rs1); + `USED_IREG (rd); + end + 3'h3: begin // JOIN + op_type = INST_OP_BITS'(INST_SFU_JOIN); + `USED_IREG (rs1); + end + 3'h4: begin // BAR + op_type = INST_OP_BITS'(INST_SFU_BAR); + `USED_IREG (rs1); + `USED_IREG (rs2); + end + 3'h5: begin // PRED + op_type = INST_OP_BITS'(INST_SFU_PRED); + op_args.wctl.is_neg = rd[0]; + `USED_IREG (rs1); + `USED_IREG (rs2); + end + default:; + endcase + end + 7'h01: begin // VOTE, SHFL + ex_type = EX_ALU; + op_args.alu.xtype = ALU_TYPE_OTHER; + use_rd = 1; + `USED_IREG (rd); + `USED_IREG (rs1); + if (funct3[2]) begin + `USED_IREG (rs2); + end + op_type = INST_OP_BITS'(funct3); + end + `ifdef EXT_TCU_ENABLE + 7'h02: begin + case (funct3) + 3'h0: begin // WMMA + ex_type = EX_TCU; + op_type = INST_OP_BITS'(INST_TCU_WMMA); + op_args.tcu.fmt_s = rs1[3:0]; + op_args.tcu.fmt_d = rd[3:0]; + op_args.tcu.step_m = '0; + op_args.tcu.step_n = '0; + `USED_IREG (rd); + `USED_IREG (rs1); + `USED_IREG (rs2); + `USED_IREG (rs3); + end + default:; + endcase + end + `endif + default:; + endcase + end + default:; + endcase + end + + // disable write to integer register r0 + wire wb = use_rd && (rd_v != 0); + + wire [2:0] used_rs = {use_rs3, use_rs2, use_rs1}; + + VX_elastic_buffer #( + .DATAW (OUT_DATAW), + .SIZE (0) + ) req_buf ( + .clk (clk), + .reset (reset), + .valid_in (fetch_if.valid), + .ready_in (fetch_if.ready), + .data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_args, wb, used_rs, rd_v, rs1_v, rs2_v, rs3_v}), + .data_out ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_args, decode_if.data.wb, decode_if.data.used_rs, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}), + .valid_out (decode_if.valid), + .ready_out (decode_if.ready) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire fetch_fire = fetch_if.valid && fetch_if.ready; + + assign decode_sched_if.valid = fetch_fire; + assign decode_sched_if.wid = fetch_if.data.wid; + assign decode_sched_if.unlock = ~is_wstall; + +`ifndef L1_ENABLE + assign fetch_if.ibuf_pop = decode_if.ibuf_pop; +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_dispatch.sv b/designs/src/vortex/rtl/core/VX_dispatch.sv new file mode 100644 index 0000000..68a64b6 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_dispatch.sv @@ -0,0 +1,89 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_dispatch import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter ISSUE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire [PERF_CTR_BITS-1:0] perf_stalls [NUM_EX_UNITS], +`endif + // inputs + VX_operands_if.slave operands_if, + + // outputs + VX_dispatch_if.master dispatch_if [NUM_EX_UNITS] +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (ISSUE_ID) + + localparam OUT_DATAW = $bits(dispatch_t); + + wire [NUM_EX_UNITS-1:0] operands_ready_in; + assign operands_if.ready = operands_ready_in[operands_if.data.ex_type]; + + for (genvar i = 0; i < NUM_EX_UNITS; ++i) begin : g_buffers + VX_elastic_buffer #( + .DATAW (OUT_DATAW), + .SIZE (2), + .OUT_REG (1) + ) buffer ( + .clk (clk), + .reset (reset), + .valid_in (operands_if.valid && (operands_if.data.ex_type == EX_BITS'(i))), + .ready_in (operands_ready_in[i]), + .data_in ({ + operands_if.data.uuid, + operands_if.data.wis, + operands_if.data.sid, + operands_if.data.tmask, + operands_if.data.PC, + operands_if.data.op_type, + operands_if.data.op_args, + operands_if.data.wb, + operands_if.data.rd, + operands_if.data.rs1_data, + operands_if.data.rs2_data, + operands_if.data.rs3_data, + operands_if.data.sop, + operands_if.data.eop + }), + .data_out (dispatch_if[i].data), + .valid_out (dispatch_if[i].valid), + .ready_out (dispatch_if[i].ready) + ); + end + +`ifdef PERF_ENABLE + reg [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] perf_stalls_r; + + wire operands_if_stall = operands_if.valid && ~operands_if.ready; + + for (genvar i = 0; i < NUM_EX_UNITS; ++i) begin : g_perf_stalls + always @(posedge clk) begin + if (reset) begin + perf_stalls_r[i] <= '0; + end else begin + perf_stalls_r[i] <= perf_stalls_r[i] + PERF_CTR_BITS'(operands_if_stall && operands_if.data.ex_type == EX_BITS'(i)); + end + end + assign perf_stalls[i] = perf_stalls_r[i]; + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_dispatch_unit.sv b/designs/src/vortex/rtl/core/VX_dispatch_unit.sv new file mode 100644 index 0000000..59a84ea --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_dispatch_unit.sv @@ -0,0 +1,242 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_dispatch_unit import VX_gpu_pkg::*; #( + parameter BLOCK_SIZE = 1, + parameter NUM_LANES = 1, + parameter OUT_BUF = 0, + parameter MAX_FANOUT = `MAX_FANOUT +) ( + input wire clk, + input wire reset, + + // inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // outputs + VX_execute_if.master execute_if [BLOCK_SIZE] +); + `STATIC_ASSERT (`IS_DIVISBLE(`ISSUE_WIDTH, BLOCK_SIZE), ("invalid parameter")) + `STATIC_ASSERT (`IS_DIVISBLE(`SIMD_WIDTH, NUM_LANES), ("invalid parameter")) + localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE); + localparam NUM_PACKETS = `SIMD_WIDTH / NUM_LANES; + localparam LPID_BITS = `CLOG2(NUM_PACKETS); + localparam LPID_WIDTH = `UP(LPID_BITS); + localparam GPID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam GPID_WIDTH = `UP(GPID_BITS); + localparam BATCH_COUNT = `ISSUE_WIDTH / BLOCK_SIZE; + localparam BATCH_COUNT_W= `LOG2UP(BATCH_COUNT); + localparam ISSUE_W = `LOG2UP(`ISSUE_WIDTH); + localparam IN_DATAW = UUID_WIDTH + ISSUE_WIS_W + SIMD_IDX_W + `SIMD_WIDTH + INST_OP_BITS + INST_ARGS_BITS + 1 + PC_BITS + NUM_REGS_BITS + (NUM_SRC_OPDS * `SIMD_WIDTH * `XLEN) + 1 + 1; + localparam OUT_DATAW = UUID_WIDTH + NW_WIDTH + NUM_LANES + INST_OP_BITS + INST_ARGS_BITS + 1 + PC_BITS + NUM_REGS_BITS + (NUM_SRC_OPDS * NUM_LANES * `XLEN) + GPID_WIDTH + 1 + 1; + localparam FANOUT_ENABLE= (`SIMD_WIDTH > (MAX_FANOUT + MAX_FANOUT /2)); + + localparam DATA_TMASK_OFF = IN_DATAW - (UUID_WIDTH + ISSUE_WIS_W + SIMD_IDX_W + `SIMD_WIDTH); + localparam DATA_REGS_OFF = 1 + 1; + + typedef struct packed { + logic [2:0][NUM_LANES-1:0][`XLEN-1:0] rsdata; + logic [NUM_LANES-1:0] tmask; + } packet_t; + + wire [`ISSUE_WIDTH-1:0] dispatch_valid; + wire [`ISSUE_WIDTH-1:0][IN_DATAW-1:0] dispatch_data; + wire [`ISSUE_WIDTH-1:0] dispatch_ready; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_dispatch_data + assign dispatch_valid[i] = dispatch_if[i].valid; + assign dispatch_data[i] = dispatch_if[i].data; + assign dispatch_if[i].ready = dispatch_ready[i]; + end + + wire [BLOCK_SIZE-1:0] block_ready; + wire [BLOCK_SIZE-1:0][NUM_LANES-1:0] block_tmask; + wire [BLOCK_SIZE-1:0][2:0][NUM_LANES-1:0][`XLEN-1:0] block_rsdata; + wire [BLOCK_SIZE-1:0][LPID_WIDTH-1:0] block_pid; + wire [BLOCK_SIZE-1:0] block_sop; + wire [BLOCK_SIZE-1:0] block_eop; + wire [BLOCK_SIZE-1:0] block_done; + + wire batch_done = (& block_done); + + // batch select logic + + logic [BATCH_COUNT_W-1:0] batch_idx; + + if (BATCH_COUNT != 1) begin : g_batch_idx + wire [BATCH_COUNT_W-1:0] batch_idx_n; + wire [BATCH_COUNT-1:0] valid_batches; + for (genvar i = 0; i < BATCH_COUNT; ++i) begin : g_valid_batches + assign valid_batches[i] = | dispatch_valid[i * BLOCK_SIZE +: BLOCK_SIZE]; + end + + VX_generic_arbiter #( + .NUM_REQS (BATCH_COUNT), + .TYPE ("P") + ) batch_sel ( + .clk (clk), + .reset (reset), + .requests (valid_batches), + .grant_index (batch_idx_n), + `UNUSED_PIN (grant_onehot), + `UNUSED_PIN (grant_valid), + .grant_ready (batch_done) + ); + + always @(posedge clk) begin + if (reset) begin + batch_idx <= '0; + end else if (batch_done) begin + batch_idx <= batch_idx_n; + end + end + end else begin : g_batch_idx_0 + assign batch_idx = 0; + `UNUSED_VAR (batch_done) + end + + wire [BLOCK_SIZE-1:0][ISSUE_W-1:0] issue_indices; + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_issue_indices + assign issue_indices[block_idx] = ISSUE_W'(batch_idx * BLOCK_SIZE) + ISSUE_W'(block_idx); + end + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_blocks + + wire [ISSUE_W-1:0] issue_idx = issue_indices[block_idx]; + wire [ISSUE_WIS_W-1:0] dispatch_wis = dispatch_data[issue_idx][DATA_TMASK_OFF + `SIMD_WIDTH + SIMD_IDX_W +: ISSUE_WIS_W]; + wire [SIMD_IDX_W-1:0] dispatch_sid = dispatch_data[issue_idx][DATA_TMASK_OFF + `SIMD_WIDTH +: SIMD_IDX_W]; + wire dispatch_sop = dispatch_data[issue_idx][1]; + wire dispatch_eop = dispatch_data[issue_idx][0]; + + wire [`SIMD_WIDTH-1:0] dispatch_tmask; + wire [2:0][`SIMD_WIDTH-1:0][`XLEN-1:0] dispatch_rsdata; + + assign dispatch_tmask = dispatch_data[issue_idx][DATA_TMASK_OFF +: `SIMD_WIDTH]; + assign dispatch_rsdata[0] = dispatch_data[issue_idx][DATA_REGS_OFF + 2 * `SIMD_WIDTH * `XLEN +: `SIMD_WIDTH * `XLEN]; + assign dispatch_rsdata[1] = dispatch_data[issue_idx][DATA_REGS_OFF + 1 * `SIMD_WIDTH * `XLEN +: `SIMD_WIDTH * `XLEN]; + assign dispatch_rsdata[2] = dispatch_data[issue_idx][DATA_REGS_OFF + 0 * `SIMD_WIDTH * `XLEN +: `SIMD_WIDTH * `XLEN]; + + wire valid_p, ready_p; + + if (`SIMD_WIDTH != NUM_LANES) begin : g_partial_simd + + packet_t [NUM_PACKETS-1:0] packets; + + for (genvar i = 0; i < NUM_PACKETS; ++i) begin : g_per_packet_data + for (genvar j = 0; j < NUM_LANES; ++j) begin : g_j + localparam k = i * NUM_LANES + j; + assign packets[i].tmask[j] = dispatch_tmask[k]; + assign packets[i].rsdata[0][j] = dispatch_rsdata[0][k]; + assign packets[i].rsdata[1][j] = dispatch_rsdata[1][k]; + assign packets[i].rsdata[2][j] = dispatch_rsdata[2][k]; + end + end + + wire [LPID_WIDTH-1:0] start_p; + wire is_first_p, is_last_p; + packet_t block_packet; + + wire fire_p = valid_p && ready_p; + + VX_nz_iterator #( + .DATAW ($bits(packet_t)), + .KEYW (NUM_LANES), + .N (NUM_PACKETS), + .OUT_REG (FANOUT_ENABLE) + ) packet_iter ( + .clk (clk), + .reset (reset), + .valid_in(dispatch_valid[issue_idx]), + .data_in (packets), + .next (fire_p), + .valid_out(valid_p), + .data_out(block_packet), + .pid (start_p), + .sop (is_first_p), + .eop (is_last_p) + ); + + assign block_tmask[block_idx] = block_packet.tmask; + assign block_rsdata[block_idx] = block_packet.rsdata; + assign block_pid[block_idx] = start_p; + assign block_sop[block_idx] = is_first_p; + assign block_eop[block_idx] = is_last_p; + assign block_ready[block_idx] = ready_p; + assign block_done[block_idx] = (fire_p && is_last_p) || ~dispatch_valid[issue_idx]; + end else begin : g_full_simd + assign valid_p = dispatch_valid[issue_idx]; + assign block_tmask[block_idx] = dispatch_tmask; + assign block_rsdata[block_idx] = dispatch_rsdata; + assign block_pid[block_idx] = 0; + assign block_sop[block_idx] = 1; + assign block_eop[block_idx] = 1; + assign block_ready[block_idx] = ready_p; + assign block_done[block_idx] = ready_p || ~valid_p; + end + + wire [ISSUE_ISW_W-1:0] isw; + if (BATCH_COUNT != 1) begin : g_isw_batch + if (BLOCK_SIZE != 1) begin : g_block + assign isw = {batch_idx, BLOCK_SIZE_W'(block_idx)}; + end else begin : g_no_block + assign isw = batch_idx; + end + end else begin : g_isw + assign isw = block_idx; + end + + wire [NW_WIDTH-1:0] block_wid = wis_to_wid(dispatch_wis, isw); + wire [GPID_WIDTH-1:0] warp_pid = GPID_WIDTH'(block_pid[block_idx]) + GPID_WIDTH'(dispatch_sid * NUM_PACKETS); + + wire warp_sop = block_sop[block_idx] && dispatch_sop; + wire warp_eop = block_eop[block_idx] && dispatch_eop; + + VX_elastic_buffer #( + .DATAW (OUT_DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) buf_out ( + .clk (clk), + .reset (reset), + .valid_in (valid_p), + .ready_in (ready_p), + .data_in ({ + dispatch_data[issue_idx][IN_DATAW-1 -: UUID_WIDTH], + block_wid, + block_tmask[block_idx], + dispatch_data[issue_idx][DATA_TMASK_OFF-1 : (DATA_REGS_OFF + NUM_SRC_OPDS * `SIMD_WIDTH * `XLEN)], + block_rsdata[block_idx][0], + block_rsdata[block_idx][1], + block_rsdata[block_idx][2], + warp_pid, + warp_sop, + warp_eop}), + .data_out (execute_if[block_idx].data), + .valid_out (execute_if[block_idx].valid), + .ready_out (execute_if[block_idx].ready) + ); + end + + // release the dispatch interface when all packets are sent + reg [`ISSUE_WIDTH-1:0] ready_in; + always @(*) begin + ready_in = 0; + for (integer block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin + ready_in[issue_indices[block_idx]] = block_ready[block_idx] && block_eop[block_idx]; + end + end + assign dispatch_ready = ready_in; + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_execute.sv b/designs/src/vortex/rtl/core/VX_execute.sv new file mode 100644 index 0000000..3cce1d5 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_execute.sv @@ -0,0 +1,121 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_execute import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter CORE_ID = 0 +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, + input pipeline_perf_t pipeline_perf, +`endif + + input base_dcrs_t base_dcrs, + + // Dcache interface + VX_lsu_mem_if.master lsu_mem_if [`NUM_LSU_BLOCKS], + + // dispatch interface + VX_dispatch_if.slave dispatch_if [NUM_EX_UNITS * `ISSUE_WIDTH], + + // commit interface + VX_commit_if.master commit_if [NUM_EX_UNITS * `ISSUE_WIDTH], + + // scheduler interfaces + VX_sched_csr_if.slave sched_csr_if, + VX_branch_ctl_if.master branch_ctl_if [`NUM_ALU_BLOCKS], + VX_warp_ctl_if.master warp_ctl_if, + + // commit interface + VX_commit_csr_if.slave commit_csr_if +); + +`ifdef EXT_F_ENABLE + VX_fpu_csr_if fpu_csr_if[`NUM_FPU_BLOCKS](); +`endif + + VX_alu_unit #( + .INSTANCE_ID (`SFORMATF(("%s-alu", INSTANCE_ID))) + ) alu_unit ( + .clk (clk), + .reset (reset), + .dispatch_if (dispatch_if[EX_ALU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .commit_if (commit_if[EX_ALU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .branch_ctl_if (branch_ctl_if) + ); + + `SCOPE_IO_SWITCH (1); + + VX_lsu_unit #( + .INSTANCE_ID (`SFORMATF(("%s-lsu", INSTANCE_ID))) + ) lsu_unit ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (reset), + .dispatch_if (dispatch_if[EX_LSU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .commit_if (commit_if[EX_LSU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .lsu_mem_if (lsu_mem_if) + ); + +`ifdef EXT_F_ENABLE + VX_fpu_unit #( + .INSTANCE_ID (`SFORMATF(("%s-fpu", INSTANCE_ID))) + ) fpu_unit ( + .clk (clk), + .reset (reset), + .dispatch_if (dispatch_if[EX_FPU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .commit_if (commit_if[EX_FPU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .fpu_csr_if (fpu_csr_if) + ); +`endif + +`ifdef EXT_TCU_ENABLE + VX_tcu_unit #( + .INSTANCE_ID (`SFORMATF(("%s-tcu", INSTANCE_ID))) + ) tcu_unit ( + .clk (clk), + .reset (reset), + .dispatch_if (dispatch_if[EX_TCU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .commit_if (commit_if[EX_TCU * `ISSUE_WIDTH +: `ISSUE_WIDTH]) + ); +`endif + + VX_sfu_unit #( + .INSTANCE_ID (`SFORMATF(("%s-sfu", INSTANCE_ID))), + .CORE_ID (CORE_ID) + ) sfu_unit ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf), + .pipeline_perf (pipeline_perf), + `endif + .base_dcrs (base_dcrs), + .dispatch_if (dispatch_if[EX_SFU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + .commit_if (commit_if[EX_SFU * `ISSUE_WIDTH +: `ISSUE_WIDTH]), + `ifdef EXT_F_ENABLE + .fpu_csr_if (fpu_csr_if), + `endif + .commit_csr_if (commit_csr_if), + .sched_csr_if (sched_csr_if), + .warp_ctl_if (warp_ctl_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_fetch.sv b/designs/src/vortex/rtl/core/VX_fetch.sv new file mode 100644 index 0000000..60a310c --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_fetch.sv @@ -0,0 +1,192 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_fetch import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Icache interface + VX_mem_bus_if.master icache_bus_if, + + // inputs + VX_schedule_if.slave schedule_if, + + // outputs + VX_fetch_if.master fetch_if +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_VAR (reset) + + wire icache_req_valid; + wire [ICACHE_ADDR_WIDTH-1:0] icache_req_addr; + wire [ICACHE_TAG_WIDTH-1:0] icache_req_tag; + wire icache_req_ready; + + wire [UUID_WIDTH-1:0] rsp_uuid; + wire [NW_WIDTH-1:0] req_tag, rsp_tag; + + wire icache_req_fire = icache_req_valid && icache_req_ready; + + assign req_tag = schedule_if.data.wid; + + assign {rsp_uuid, rsp_tag} = icache_bus_if.rsp_data.tag; + + wire [PC_BITS-1:0] rsp_PC; + wire [`NUM_THREADS-1:0] rsp_tmask; + + VX_dp_ram #( + .DATAW (PC_BITS + `NUM_THREADS), + .SIZE (`NUM_WARPS), + .RDW_MODE ("R"), + .LUTRAM (1) + ) tag_store ( + .clk (clk), + .reset (reset), + .read (1'b1), + .write (icache_req_fire), + .wren (1'b1), + .waddr (req_tag), + .wdata ({schedule_if.data.PC, schedule_if.data.tmask}), + .raddr (rsp_tag), + .rdata ({rsp_PC, rsp_tmask}) + ); + +`ifndef L1_ENABLE + // Ensure that the ibuffer doesn't fill up. + // This resolves potential deadlock if ibuffer fills and the LSU stalls the execute stage due to pending dcache requests. + // This issue is particularly prevalent when the icache and dcache are disabled and both requests share the same bus. + wire [`NUM_WARPS-1:0] pending_ibuf_full; + for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_pending_reads + VX_pending_size #( + .SIZE (`IBUF_SIZE) + ) pending_reads ( + .clk (clk), + .reset (reset), + .incr (icache_req_fire && schedule_if.data.wid == i), + .decr (fetch_if.ibuf_pop[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (alm_empty), + .full (pending_ibuf_full[i]), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + end + wire ibuf_ready = ~pending_ibuf_full[schedule_if.data.wid]; +`else + wire ibuf_ready = 1'b1; +`endif + + `RUNTIME_ASSERT((!schedule_if.valid || schedule_if.data.PC != 0), + ("%t: *** %s invalid PC=0x%0h, wid=%0d, tmask=%b (#%0d)", $time, INSTANCE_ID, to_fullPC(schedule_if.data.PC), schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.uuid)) + + // Icache Request + + assign icache_req_valid = schedule_if.valid && ibuf_ready; + assign icache_req_addr = schedule_if.data.PC[2-(`XLEN-PC_BITS) +: ICACHE_ADDR_WIDTH]; // 4-byte aligned addresses + assign icache_req_tag = {schedule_if.data.uuid, req_tag}; + assign schedule_if.ready = icache_req_ready && ibuf_ready; + + VX_elastic_buffer #( + .DATAW (ICACHE_ADDR_WIDTH + ICACHE_TAG_WIDTH), + .SIZE (2), + .OUT_REG (1) // external bus should be registered + ) req_buf ( + .clk (clk), + .reset (reset), + .valid_in (icache_req_valid), + .ready_in (icache_req_ready), + .data_in ({icache_req_addr, icache_req_tag}), + .data_out ({icache_bus_if.req_data.addr, icache_bus_if.req_data.tag}), + .valid_out (icache_bus_if.req_valid), + .ready_out (icache_bus_if.req_ready) + ); + + assign icache_bus_if.req_data.flags = '0; + assign icache_bus_if.req_data.rw = 0; + assign icache_bus_if.req_data.byteen = '1; + assign icache_bus_if.req_data.data = '0; + + // Icache Response + + assign fetch_if.valid = icache_bus_if.rsp_valid; + assign fetch_if.data.tmask = rsp_tmask; + assign fetch_if.data.wid = rsp_tag; + assign fetch_if.data.PC = rsp_PC; + assign fetch_if.data.instr = icache_bus_if.rsp_data.data; + assign fetch_if.data.uuid = rsp_uuid; + assign icache_bus_if.rsp_ready = fetch_if.ready; + +`ifdef SCOPE +`ifdef DBG_SCOPE_FETCH + `SCOPE_IO_SWITCH (1); + wire schedule_fire = schedule_if.valid && schedule_if.ready; + wire icache_bus_req_fire = icache_bus_if.req_valid && icache_bus_if.req_ready; + wire icache_bus_rsp_fire = icache_bus_if.rsp_valid && icache_bus_if.rsp_ready; + wire reset_negedge; + `NEG_EDGE (reset_negedge, reset); + `SCOPE_TAP_EX (0, 1, 6, 3, ( + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + PC_BITS + + UUID_WIDTH + ICACHE_WORD_SIZE + ICACHE_ADDR_WIDTH + + UUID_WIDTH + (ICACHE_WORD_SIZE * 8) + ), { + schedule_if.valid, + schedule_if.ready, + icache_bus_if.req_valid, + icache_bus_if.req_ready, + icache_bus_if.rsp_valid, + icache_bus_if.rsp_ready + }, { + schedule_fire, + icache_bus_req_fire, + icache_bus_rsp_fire + },{ + schedule_if.data.uuid, schedule_if.data.wid, schedule_if.data.tmask, schedule_if.data.PC, + icache_bus_if.req_data.tag.uuid, icache_bus_if.req_data.byteen, icache_bus_if.req_data.addr, + icache_bus_if.rsp_data.tag.uuid, icache_bus_if.rsp_data.data + }, + reset_negedge, 1'b0, 4096 + ); +`else + `SCOPE_IO_UNUSED(0) +`endif +`endif + +`ifdef CHIPSCOPE +`ifdef DBG_SCOPE_FETCH + ila_fetch ila_fetch_inst ( + .clk (clk), + .probe0 ({schedule_if.valid, schedule_if.data, schedule_if.ready}), + .probe1 ({icache_bus_if.req_valid, icache_bus_if.req_data, icache_bus_if.req_ready}), + .probe2 ({icache_bus_if.rsp_valid, icache_bus_if.rsp_data, icache_bus_if.rsp_ready}) + ); +`endif +`endif + +`ifdef DBG_TRACE_MEM + always @(posedge clk) begin + if (schedule_if.valid && schedule_if.ready) begin + `TRACE(1, ("%t: %s req: wid=%0d, PC=0x%0h, tmask=%b (#%0d)\n", $time, INSTANCE_ID, schedule_if.data.wid, to_fullPC(schedule_if.data.PC), schedule_if.data.tmask, schedule_if.data.uuid)) + end + if (fetch_if.valid && fetch_if.ready) begin + `TRACE(1, ("%t: %s rsp: wid=%0d, PC=0x%0h, tmask=%b, instr=0x%0h (#%0d)\n", $time, INSTANCE_ID, fetch_if.data.wid, to_fullPC(fetch_if.data.PC), fetch_if.data.tmask, fetch_if.data.instr, fetch_if.data.uuid)) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_gather_unit.sv b/designs/src/vortex/rtl/core/VX_gather_unit.sv new file mode 100644 index 0000000..fedca5b --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_gather_unit.sv @@ -0,0 +1,144 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_gather_unit import VX_gpu_pkg::*; #( + parameter BLOCK_SIZE = 1, + parameter NUM_LANES = 1, + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + // inputs + VX_result_if.slave result_if [BLOCK_SIZE], + + // outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH] +); + `STATIC_ASSERT (`IS_DIVISBLE(`ISSUE_WIDTH, BLOCK_SIZE), ("invalid parameter")) + `STATIC_ASSERT (`IS_DIVISBLE(`SIMD_WIDTH, NUM_LANES), ("invalid parameter")) + localparam BLOCK_SIZE_W = `LOG2UP(BLOCK_SIZE); + localparam NUM_PACKETS = `SIMD_WIDTH / NUM_LANES; + localparam LPID_BITS = `CLOG2(NUM_PACKETS); + localparam LPID_WIDTH = `UP(LPID_BITS); + localparam GPID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam GPID_WIDTH = `UP(GPID_BITS); + localparam DATAW = UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + 1 + NUM_REGS_BITS + NUM_LANES * `XLEN + GPID_WIDTH + 1 + 1; + localparam DATA_WIS_OFF = DATAW - (UUID_WIDTH + NW_WIDTH); + + `DECL_RESULT_T (result_t, NUM_LANES); + + wire [BLOCK_SIZE-1:0] result_in_valid; + wire [BLOCK_SIZE-1:0][DATAW-1:0] result_in_data; + wire [BLOCK_SIZE-1:0] result_in_ready; + wire [BLOCK_SIZE-1:0][ISSUE_ISW_W-1:0] result_in_isw; + + for (genvar i = 0; i < BLOCK_SIZE; ++i) begin : g_commit_in + assign result_in_valid[i] = result_if[i].valid; + assign result_in_data[i] = result_if[i].data; + assign result_if[i].ready = result_in_ready[i]; + if (BLOCK_SIZE != `ISSUE_WIDTH) begin : g_result_in_isw_partial + if (BLOCK_SIZE != 1) begin : g_block + assign result_in_isw[i] = {result_in_data[i][DATA_WIS_OFF+BLOCK_SIZE_W +: (ISSUE_ISW_W-BLOCK_SIZE_W)], BLOCK_SIZE_W'(i)}; + end else begin : g_no_block + assign result_in_isw[i] = result_in_data[i][DATA_WIS_OFF +: ISSUE_ISW_W]; + end + end else begin : g_result_in_isw_full + assign result_in_isw[i] = BLOCK_SIZE_W'(i); + end + end + + reg [`ISSUE_WIDTH-1:0] result_out_valid; + reg [`ISSUE_WIDTH-1:0][DATAW-1:0] result_out_data; + wire [`ISSUE_WIDTH-1:0] result_out_ready; + + always @(*) begin + result_out_valid = '0; + for (integer i = 0; i < `ISSUE_WIDTH; ++i) begin + result_out_data[i] = 'x; + end + for (integer i = 0; i < BLOCK_SIZE; ++i) begin + result_out_valid[result_in_isw[i]] = result_in_valid[i]; + result_out_data[result_in_isw[i]] = result_in_data[i]; + end + end + + for (genvar i = 0; i < BLOCK_SIZE; ++i) begin : g_result_in_ready + assign result_in_ready[i] = result_out_ready[result_in_isw[i]]; + end + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin: g_out_bufs + VX_result_if #( + .data_t (result_t) + ) result_tmp_if(); + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (result_out_valid[i]), + .ready_in (result_out_ready[i]), + .data_in (result_out_data[i]), + .data_out (result_tmp_if.data), + .valid_out (result_tmp_if.valid), + .ready_out (result_tmp_if.ready) + ); + + logic [SIMD_IDX_W-1:0] commit_sid_w; + logic [`SIMD_WIDTH-1:0] commit_tmask_w; + logic [`SIMD_WIDTH-1:0][`XLEN-1:0] commit_data_w; + + if (LPID_BITS != 0) begin : g_lpid + logic [LPID_WIDTH-1:0] lpid; + if (SIMD_COUNT != 1) begin : g_simd + assign {commit_sid_w, lpid} = result_tmp_if.data.pid; + end else begin : g_no_simd + assign commit_sid_w = 0; + assign lpid = result_tmp_if.data.pid; + end + always @(*) begin + commit_tmask_w = '0; + commit_data_w = 'x; + for (integer j = 0; j < NUM_LANES; ++j) begin + commit_tmask_w[lpid * NUM_LANES + j] = result_tmp_if.data.tmask[j]; + commit_data_w[lpid * NUM_LANES + j] = result_tmp_if.data.data[j]; + end + end + end else begin : g_no_lpid + assign commit_sid_w = result_tmp_if.data.pid; + assign commit_tmask_w = result_tmp_if.data.tmask; + assign commit_data_w = result_tmp_if.data.data; + end + + assign commit_if[i].valid = result_tmp_if.valid; + assign commit_if[i].data = { + result_tmp_if.data.uuid, + result_tmp_if.data.wid, + commit_sid_w, + commit_tmask_w, + result_tmp_if.data.PC, + result_tmp_if.data.wb, + result_tmp_if.data.rd, + commit_data_w, + result_tmp_if.data.sop, + result_tmp_if.data.eop + }; + assign result_tmp_if.ready = commit_if[i].ready; + end + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_ibuffer.sv b/designs/src/vortex/rtl/core/VX_ibuffer.sv new file mode 100644 index 0000000..793c393 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_ibuffer.sv @@ -0,0 +1,100 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_ibuffer import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter ISSUE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire [PERF_CTR_BITS-1:0] perf_stalls, +`endif + + // inputs + VX_decode_if.slave decode_if, + + // outputs + VX_ibuffer_if.master ibuffer_if [PER_ISSUE_WARPS] +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (ISSUE_ID) + + localparam OUT_DATAW = $bits(ibuffer_t); + + wire [ISSUE_WIS_W-1:0] decode_wis = wid_to_wis(decode_if.data.wid); + + wire [PER_ISSUE_WARPS-1:0] ibuf_ready_in; + assign decode_if.ready = ibuf_ready_in[decode_wis]; + + for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_instr_bufs + VX_ibuffer_if uop_sequencer_if(); + VX_elastic_buffer #( + .DATAW (OUT_DATAW), + .SIZE (`IBUF_SIZE), + .OUT_REG (1) + ) instr_buf ( + .clk (clk), + .reset (reset), + .valid_in (decode_if.valid && decode_wis == ISSUE_WIS_W'(w)), + .data_in ({ + decode_if.data.uuid, + decode_if.data.tmask, + decode_if.data.PC, + decode_if.data.ex_type, + decode_if.data.op_type, + decode_if.data.op_args, + decode_if.data.wb, + decode_if.data.used_rs, + decode_if.data.rd, + decode_if.data.rs1, + decode_if.data.rs2, + decode_if.data.rs3 + }), + .ready_in (ibuf_ready_in[w]), + .valid_out(uop_sequencer_if.valid), + .data_out (uop_sequencer_if.data), + .ready_out(uop_sequencer_if.ready) + ); + `ifndef L1_ENABLE + assign decode_if.ibuf_pop[w] = uop_sequencer_if.valid && uop_sequencer_if.ready; + `endif + + VX_uop_sequencer uop_sequencer ( + .clk (clk), + .reset (reset), + .input_if (uop_sequencer_if), + .output_if (ibuffer_if[w]) + ); + end + +`ifdef PERF_ENABLE + reg [PERF_CTR_BITS-1:0] perf_ibf_stalls; + + wire decode_if_stall = decode_if.valid && ~decode_if.ready; + + always @(posedge clk) begin + if (reset) begin + perf_ibf_stalls <= '0; + end else begin + perf_ibf_stalls <= perf_ibf_stalls + PERF_CTR_BITS'(decode_if_stall); + end + end + + assign perf_stalls = perf_ibf_stalls; +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_ipdom_stack.sv b/designs/src/vortex/rtl/core/VX_ipdom_stack.sv new file mode 100644 index 0000000..b716597 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_ipdom_stack.sv @@ -0,0 +1,123 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_ipdom_stack import VX_gpu_pkg::*; #( + parameter WIDTH = 1, + parameter DEPTH = 1, + parameter ADDRW = `LOG2UP(DEPTH) +) ( + input wire clk, + input wire reset, + input wire [NW_WIDTH-1:0] wid, + input wire [WIDTH-1:0] d0, + input wire [WIDTH-1:0] d1, + input wire [ADDRW-1:0] rd_ptr, + input wire push, + input wire pop, + output wire [WIDTH-1:0] q_val, + output wire q_idx, + output wire [`NUM_WARPS-1:0][ADDRW-1:0] wr_ptr, + output wire empty, + output wire full +); + localparam BRAM_DATAW = 1 + WIDTH * 2; + localparam BRAM_SIZE = DEPTH * `NUM_WARPS; + localparam BRAW_ADDRW = `LOG2UP(BRAM_SIZE); + + wire [`NUM_WARPS-1:0][ADDRW-1:0] wr_ptr_w; + wire [`NUM_WARPS-1:0] empty_w, full_w; + + for (genvar i = 0; i < `NUM_WARPS; i++) begin : g_addressing + + reg [ADDRW-1:0] wr_ptr_r; + reg empty_r, full_r; + + wire push_s = push && (wid == i); + wire pop_s = pop && (wid == i); + + `RUNTIME_ASSERT(~(push_s && full_r), ("%t: runtime error: writing to a full stack!", $time)); + `RUNTIME_ASSERT(~(pop_s && empty_r), ("%t: runtime error: reading an empty stack!", $time)); + `RUNTIME_ASSERT(~(push_s && pop_s), ("%t: runtime error: push and pop in same cycle not supported!", $time)); + + always @(posedge clk) begin + if (reset) begin + wr_ptr_r <= '0; + empty_r <= 1; + full_r <= 0; + end else begin + if (push_s) begin + wr_ptr_r <= wr_ptr_r + ADDRW'(1); + empty_r <= 0; + full_r <= (ADDRW'(DEPTH-1) == wr_ptr_r); + end else if (pop_s) begin + wr_ptr_r <= wr_ptr_r - ADDRW'(q_idx); + empty_r <= (rd_ptr == 0) && q_idx; + full_r <= 0; + end + end + end + + assign wr_ptr_w[i] = wr_ptr_r; + assign empty_w[i] = empty_r; + assign full_w[i] = full_r; + end + + wire [BRAW_ADDRW-1:0] raddr, waddr; + + if (DEPTH > 1 && `NUM_WARPS > 1) begin : g_DW + assign waddr = push ? {wr_ptr_w[wid], wid} : {rd_ptr, wid}; + assign raddr = {rd_ptr, wid}; + end else if (DEPTH > 1) begin : g_D + `UNUSED_VAR (wid) + assign waddr = push ? wr_ptr_w : rd_ptr; + assign raddr = rd_ptr; + end else if (`NUM_WARPS > 1) begin : g_W + `UNUSED_VAR (rd_ptr) + `UNUSED_VAR (wr_ptr_w) + assign waddr = push ? wid : wid; + assign raddr = 0; + end else begin : g_none + `UNUSED_VAR (rd_ptr) + `UNUSED_VAR (wr_ptr_w) + `UNUSED_VAR (wid) + assign waddr = 0; + assign raddr = 0; + end + + wire [WIDTH-1:0] q0, q1; + + VX_dp_ram #( + .DATAW (BRAM_DATAW), + .SIZE (BRAM_SIZE), + .RDW_MODE ("R"), + .RADDR_REG(1) + ) ipdom_store ( + .clk (clk), + .reset (reset), + .read (pop), + .write (push || pop), + .wren (1'b1), + .waddr (waddr), + .raddr (raddr), + .wdata (push ? {1'b0, d1, d0} : {1'b1, q1, q0}), + .rdata ({q_idx, q1, q0}) + ); + + assign q_val = q_idx ? q0 : q1; + assign wr_ptr = wr_ptr_w; + assign empty = empty_w[wid]; + assign full = full_w[wid]; + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_issue.sv b/designs/src/vortex/rtl/core/VX_issue.sv new file mode 100644 index 0000000..19b3a4b --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_issue.sv @@ -0,0 +1,90 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_issue import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output issue_perf_t issue_perf, +`endif + + VX_decode_if.slave decode_if, + VX_writeback_if.slave writeback_if [`ISSUE_WIDTH], + VX_dispatch_if.master dispatch_if [NUM_EX_UNITS * `ISSUE_WIDTH], + VX_issue_sched_if.master issue_sched_if[`ISSUE_WIDTH] +); + `STATIC_ASSERT ((`ISSUE_WIDTH <= `NUM_WARPS), ("invalid parameter")) + +`ifdef PERF_ENABLE + issue_perf_t per_issue_perf [`ISSUE_WIDTH]; + `PERF_COUNTER_ADD (issue_perf, per_issue_perf, ibf_stalls, PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2)) + `PERF_COUNTER_ADD (issue_perf, per_issue_perf, scb_stalls, PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2)) + `PERF_COUNTER_ADD (issue_perf, per_issue_perf, opd_stalls, PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2)) + for (genvar i = 0; i < NUM_EX_UNITS; ++i) begin : g_issue_perf_units_uses + `PERF_COUNTER_ADD (issue_perf, per_issue_perf, units_uses[i], PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2)) + end + for (genvar i = 0; i < NUM_SFU_UNITS; ++i) begin : g_issue_perf_sfu_uses + `PERF_COUNTER_ADD (issue_perf, per_issue_perf, sfu_uses[i], PERF_CTR_BITS, `ISSUE_WIDTH, (`ISSUE_WIDTH > 2)) + end +`endif + + wire [ISSUE_ISW_W-1:0] decode_isw = wid_to_isw(decode_if.data.wid); + + wire [`ISSUE_WIDTH-1:0] decode_ready_in; + assign decode_if.ready = decode_ready_in[decode_isw]; + + `SCOPE_IO_SWITCH (`ISSUE_WIDTH); + + for (genvar issue_id = 0; issue_id < `ISSUE_WIDTH; ++issue_id) begin : g_slices + VX_decode_if slice_decode_if(); + + VX_dispatch_if per_issue_dispatch_if[NUM_EX_UNITS](); + + assign slice_decode_if.valid = decode_if.valid && (decode_isw == issue_id); + assign slice_decode_if.data = decode_if.data; + assign decode_ready_in[issue_id] = slice_decode_if.ready; + + `ifndef L1_ENABLE + assign decode_if.ibuf_pop[issue_id * PER_ISSUE_WARPS +: PER_ISSUE_WARPS] = slice_decode_if.ibuf_pop; + `endif + + VX_issue_slice #( + .INSTANCE_ID (`SFORMATF(("%s%0d", INSTANCE_ID, issue_id))), + .ISSUE_ID (issue_id) + ) issue_slice ( + `SCOPE_IO_BIND(issue_id) + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .issue_perf (per_issue_perf[issue_id]), + `endif + .decode_if (slice_decode_if), + .writeback_if (writeback_if[issue_id]), + .dispatch_if (per_issue_dispatch_if), + .issue_sched_if(issue_sched_if[issue_id]) + ); + + // Assign transposed dispatch_if + for (genvar ex_id = 0; ex_id < NUM_EX_UNITS; ++ex_id) begin : g_dispatch_if + `ASSIGN_VX_IF(dispatch_if[ex_id * `ISSUE_WIDTH + issue_id], per_issue_dispatch_if[ex_id]); + end + end + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_issue_slice.sv b/designs/src/vortex/rtl/core/VX_issue_slice.sv new file mode 100644 index 0000000..2417212 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_issue_slice.sv @@ -0,0 +1,212 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_issue_slice import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter ISSUE_ID = 0 +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output issue_perf_t issue_perf, +`endif + + VX_decode_if.slave decode_if, + VX_writeback_if.slave writeback_if, + VX_dispatch_if.master dispatch_if [NUM_EX_UNITS], + VX_issue_sched_if.master issue_sched_if +); + `UNUSED_PARAM (ISSUE_ID) + + VX_ibuffer_if ibuffer_if [PER_ISSUE_WARPS](); + VX_scoreboard_if scoreboard_if(); + VX_operands_if operands_if(); + + VX_ibuffer #( + .INSTANCE_ID (`SFORMATF(("%s-ibuffer", INSTANCE_ID))), + .ISSUE_ID (ISSUE_ID) + ) ibuffer ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .perf_stalls (issue_perf.ibf_stalls), + `endif + .decode_if (decode_if), + .ibuffer_if (ibuffer_if) + ); + + VX_scoreboard #( + .INSTANCE_ID (`SFORMATF(("%s-scoreboard", INSTANCE_ID))), + .ISSUE_ID (ISSUE_ID) + ) scoreboard ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .perf_stalls (issue_perf.scb_stalls), + .perf_units_uses(issue_perf.units_uses), + .perf_sfu_uses (issue_perf.sfu_uses), + `endif + .writeback_if (writeback_if), + .ibuffer_if (ibuffer_if), + .scoreboard_if (scoreboard_if) + ); + + VX_operands #( + .INSTANCE_ID (`SFORMATF(("%s-operands", INSTANCE_ID))), + .ISSUE_ID (ISSUE_ID) + ) operands ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .perf_stalls (issue_perf.opd_stalls), + `endif + .writeback_if (writeback_if), + .scoreboard_if (scoreboard_if), + .operands_if (operands_if) + ); + + VX_dispatch #( + .INSTANCE_ID (`SFORMATF(("%s-dispatch", INSTANCE_ID))), + .ISSUE_ID (ISSUE_ID) + ) dispatch ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + `UNUSED_PIN (perf_stalls), + `endif + .operands_if (operands_if), + .dispatch_if (dispatch_if) + ); + + // notify scheduler + assign issue_sched_if.valid = operands_if.valid && operands_if.ready && operands_if.data.sop; + assign issue_sched_if.wis = operands_if.data.wis; + +`ifdef SCOPE +`ifdef DBG_SCOPE_ISSUE + `SCOPE_IO_SWITCH (1); + wire decode_fire = decode_if.valid && decode_if.ready; + wire operands_fire = operands_if.valid && operands_if.ready; + wire reset_negedge; + `NEG_EDGE (reset_negedge, reset); + `SCOPE_TAP_EX (0, 2, 4, 3, ( + UUID_WIDTH + NW_WIDTH + `NUM_THREADS + PC_BITS + EX_BITS + INST_OP_BITS + 1 + NUM_REGS_BITS * 4 + + UUID_WIDTH + ISSUE_WIS_W + `SIMD_WIDTH + PC_BITS + EX_BITS + INST_OP_BITS + 1 + NUM_REGS_BITS + (3 * `XLEN) + + UUID_WIDTH + ISSUE_WIS_W + `SIMD_WIDTH + NUM_REGS_BITS + (`SIMD_WIDTH * `XLEN) + 1 + ), { + decode_if.valid, + decode_if.ready, + operands_if.valid, + operands_if.ready + }, { + decode_fire, + operands_fire, + writeback_if.valid // ack-free + }, { + decode_if.data.uuid, + decode_if.data.wid, + decode_if.data.tmask, + decode_if.data.PC, + decode_if.data.ex_type, + decode_if.data.op_type, + decode_if.data.wb, + decode_if.data.rd, + decode_if.data.rs1, + decode_if.data.rs2, + decode_if.data.rs3, + operands_if.data.uuid, + operands_if.data.wis, + operands_if.data.tmask, + operands_if.data.PC, + operands_if.data.ex_type, + operands_if.data.op_type, + operands_if.data.wb, + operands_if.data.rd, + operands_if.data.rs1_data[0], + operands_if.data.rs2_data[0], + operands_if.data.rs3_data[0], + writeback_if.data.uuid, + writeback_if.data.wis, + writeback_if.data.tmask, + writeback_if.data.rd, + writeback_if.data.data, + writeback_if.data.eop + }, + reset_negedge, 1'b0, 4096 + ); +`else + `SCOPE_IO_UNUSED(0) +`endif +`endif + +`ifdef CHIPSCOPE +`ifdef DBG_SCOPE_ISSUE + ila_issue ila_issue_inst ( + .clk (clk), + .probe0 ({decode_if.valid, decode_if.data, decode_if.ready}), + .probe1 ({scoreboard_if.valid, scoreboard_if.data, scoreboard_if.ready}), + .probe2 ({operands_if.valid, operands_if.data, operands_if.ready}), + .probe3 ({writeback_if.valid, writeback_if.data}) + ); +`endif +`endif + +`ifdef DBG_TRACE_PIPELINE + for (genvar i = 0; i < PER_ISSUE_WARPS; ++i) begin : g_ibuffer_trace + localparam wid = wis_to_wid(ISSUE_WIS_W'(i), ISSUE_ID); + always @(posedge clk) begin + if (ibuffer_if[i].valid && ibuffer_if[i].ready) begin + `TRACE(1, ("%t: %s-ibuffer: wid=%0d, PC=0x%0h, ex=", $time, INSTANCE_ID, wid, to_fullPC(ibuffer_if[i].data.PC))) + VX_trace_pkg::trace_ex_type(1, ibuffer_if[i].data.ex_type); + `TRACE(1, (", op=")) + VX_trace_pkg::trace_ex_op(1, ibuffer_if[i].data.ex_type, ibuffer_if[i].data.op_type, ibuffer_if[i].data.op_args); + `TRACE(1, (", tmask=%b, wb=%b, used_rs=%b, rd=", ibuffer_if[i].data.tmask, ibuffer_if[i].data.wb, ibuffer_if[i].data.used_rs)) + VX_trace_pkg::trace_reg_idx(1, ibuffer_if[i].data.rd); + `TRACE(1, (", rs1=")) + VX_trace_pkg::trace_reg_idx(1, ibuffer_if[i].data.rs1); + `TRACE(1, (", rs2=")) + VX_trace_pkg::trace_reg_idx(1, ibuffer_if[i].data.rs2); + `TRACE(1, (", rs3=")) + VX_trace_pkg::trace_reg_idx(1, ibuffer_if[i].data.rs3); + `TRACE(1, (", ")) + VX_trace_pkg::trace_op_args(1, ibuffer_if[i].data.ex_type, ibuffer_if[i].data.op_type, ibuffer_if[i].data.op_args); + `TRACE(1, (" (#%0d)\n", ibuffer_if[i].data.uuid)) + end + end + end + + always @(posedge clk) begin + if (operands_if.valid && operands_if.ready) begin + `TRACE(1, ("%t: %s-dispatch: wid=%0d, sid=%0d, PC=0x%0h, ex=", $time, INSTANCE_ID, wis_to_wid(operands_if.data.wis, ISSUE_ID), operands_if.data.sid, to_fullPC(operands_if.data.PC))) + VX_trace_pkg::trace_ex_type(1, operands_if.data.ex_type); + `TRACE(1, (", op=")) + VX_trace_pkg::trace_ex_op(1, operands_if.data.ex_type, operands_if.data.op_type, operands_if.data.op_args); + `TRACE(1, (", tmask=%b, wb=%b, rd=%0d, rs1_data=", operands_if.data.tmask, operands_if.data.wb, operands_if.data.rd)) + `TRACE_ARRAY1D(1, "0x%0h", operands_if.data.rs1_data, `SIMD_WIDTH) + `TRACE(1, (", rs2_data=")) + `TRACE_ARRAY1D(1, "0x%0h", operands_if.data.rs2_data, `SIMD_WIDTH) + `TRACE(1, (", rs3_data=")) + `TRACE_ARRAY1D(1, "0x%0h", operands_if.data.rs3_data, `SIMD_WIDTH) + `TRACE(1, (", ")) + VX_trace_pkg::trace_op_args(1, operands_if.data.ex_type, operands_if.data.op_type, operands_if.data.op_args); + `TRACE(1, (", sop=%b, eop=%b (#%0d)\n", operands_if.data.sop, operands_if.data.eop, operands_if.data.uuid)) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_issue_top.sv b/designs/src/vortex/rtl/core/VX_issue_top.sv new file mode 100644 index 0000000..36728bc --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_issue_top.sv @@ -0,0 +1,156 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_issue_top import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "issue" +) ( + // Clock + input wire clk, + input wire reset, + + input wire decode_valid, + input wire [UUID_WIDTH-1:0] decode_uuid, + input wire [NW_WIDTH-1:0] decode_wid, + input wire [`NUM_THREADS-1:0] decode_tmask, + input wire [PC_BITS-1:0] decode_PC, + input wire [EX_BITS-1:0] decode_ex_type, + input wire [INST_OP_BITS-1:0] decode_op_type, + input op_args_t decode_op_args, + input wire decode_wb, + input wire [NUM_SRC_OPDS-1:0] decode_used_rs, + input wire [NUM_REGS_BITS-1:0] decode_rd, + input wire [NUM_REGS_BITS-1:0] decode_rs1, + input wire [NUM_REGS_BITS-1:0] decode_rs2, + input wire [NUM_REGS_BITS-1:0] decode_rs3, + output wire decode_ready, + + input wire writeback_valid[`ISSUE_WIDTH], + input wire [UUID_WIDTH-1:0] writeback_uuid[`ISSUE_WIDTH], + input wire [ISSUE_WIS_W-1:0] writeback_wis[`ISSUE_WIDTH], + input wire [SIMD_IDX_W-1:0] writeback_sid[`ISSUE_WIDTH], + input wire [`SIMD_WIDTH-1:0] writeback_tmask[`ISSUE_WIDTH], + input wire [PC_BITS-1:0] writeback_PC[`ISSUE_WIDTH], + input wire [NUM_REGS_BITS-1:0] writeback_rd[`ISSUE_WIDTH], + input wire [`SIMD_WIDTH-1:0][`XLEN-1:0] writeback_data[`ISSUE_WIDTH], + input wire writeback_sop[`ISSUE_WIDTH], + input wire writeback_eop[`ISSUE_WIDTH], + + output wire dispatch_valid[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [UUID_WIDTH-1:0] dispatch_uuid[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [ISSUE_WIS_W-1:0] dispatch_wis[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [SIMD_IDX_W-1:0] dispatch_sid[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [`SIMD_WIDTH-1:0] dispatch_tmask[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [PC_BITS-1:0] dispatch_PC[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [INST_ALU_BITS-1:0] dispatch_op_type[NUM_EX_UNITS * `ISSUE_WIDTH], + output op_args_t dispatch_op_args[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire dispatch_wb[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [NUM_REGS_BITS-1:0] dispatch_rd[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [`SIMD_WIDTH-1:0][`XLEN-1:0] dispatch_rs1_data[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [`SIMD_WIDTH-1:0][`XLEN-1:0] dispatch_rs2_data[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire [`SIMD_WIDTH-1:0][`XLEN-1:0] dispatch_rs3_data[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire dispatch_sop[NUM_EX_UNITS * `ISSUE_WIDTH], + output wire dispatch_eop[NUM_EX_UNITS * `ISSUE_WIDTH], + input wire dispatch_ready[NUM_EX_UNITS * `ISSUE_WIDTH], + + output wire [ISSUE_WIS_W-1:0] issue_sched_wis[`ISSUE_WIDTH], + output wire issue_sched_valid[`ISSUE_WIDTH] +); + VX_decode_if decode_if(); + VX_dispatch_if dispatch_if[NUM_EX_UNITS * `ISSUE_WIDTH](); + VX_writeback_if writeback_if[`ISSUE_WIDTH](); + VX_issue_sched_if issue_sched_if[`ISSUE_WIDTH](); + + assign decode_if.valid = decode_valid; + assign decode_if.data.uuid = decode_uuid; + assign decode_if.data.wid = decode_wid; + assign decode_if.data.tmask = decode_tmask; + assign decode_if.data.PC = decode_PC; + assign decode_if.data.ex_type = decode_ex_type; + assign decode_if.data.op_type = decode_op_type; + assign decode_if.data.op_args = decode_op_args; + assign decode_if.data.wb = decode_wb; + assign decode_if.data.used_rs = decode_used_rs; + assign decode_if.data.rd = decode_rd; + assign decode_if.data.rs1 = decode_rs1; + assign decode_if.data.rs2 = decode_rs2; + assign decode_if.data.rs3 = decode_rs3; + assign decode_ready = decode_if.ready; + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_writeback_if + assign writeback_if[i].valid = writeback_valid[i]; + assign writeback_if[i].data.uuid = writeback_uuid[i]; + assign writeback_if[i].data.wis = writeback_wis[i]; + assign writeback_if[i].data.sid = writeback_sid[i]; + assign writeback_if[i].data.tmask = writeback_tmask[i]; + assign writeback_if[i].data.PC = writeback_PC[i]; + assign writeback_if[i].data.rd = writeback_rd[i]; + assign writeback_if[i].data.data = writeback_data[i]; + assign writeback_if[i].data.sop = writeback_sop[i]; + assign writeback_if[i].data.eop = writeback_eop[i]; + end + + for (genvar i = 0; i < NUM_EX_UNITS * `ISSUE_WIDTH; ++i) begin : g_dispatch_if + assign dispatch_valid[i] = dispatch_if[i].valid; + assign dispatch_uuid[i] = dispatch_if[i].data.uuid; + assign dispatch_wis[i] = dispatch_if[i].data.wis; + assign dispatch_sid[i] = dispatch_if[i].data.sid; + assign dispatch_tmask[i] = dispatch_if[i].data.tmask; + assign dispatch_PC[i] = dispatch_if[i].data.PC; + assign dispatch_op_type[i] = dispatch_if[i].data.op_type; + assign dispatch_op_args[i] = dispatch_if[i].data.op_args; + assign dispatch_wb[i] = dispatch_if[i].data.wb; + assign dispatch_rd[i] = dispatch_if[i].data.rd; + assign dispatch_rs1_data[i] = dispatch_if[i].data.rs1_data; + assign dispatch_rs2_data[i] = dispatch_if[i].data.rs2_data; + assign dispatch_rs3_data[i] = dispatch_if[i].data.rs3_data; + assign dispatch_sop[i] = dispatch_if[i].data.sop; + assign dispatch_eop[i] = dispatch_if[i].data.eop; + assign dispatch_if[i].ready = dispatch_ready[i]; + end + + for (genvar i = 0; i < `ISSUE_WIDTH; ++i) begin : g_issue_sched_if + assign issue_sched_wis[i] = issue_sched_if[i].wis; + assign issue_sched_valid[i] = issue_sched_if[i].valid; + end + +`ifdef PERF_ENABLE + issue_perf_t issue_perf = '0; +`endif + +`ifdef SCOPE + wire [0:0] scope_reset_w = 1'b0; + wire [0:0] scope_bus_in_w = 1'b0; + wire [0:0] scope_bus_out_w; + `UNUSED_VAR (scope_bus_out_w) +`endif + + VX_issue #( + .INSTANCE_ID (INSTANCE_ID) + ) issue ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .issue_perf (issue_perf), + `endif + + .decode_if (decode_if), + .writeback_if (writeback_if), + .dispatch_if (dispatch_if), + .issue_sched_if (issue_sched_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_lsu_slice.sv b/designs/src/vortex/rtl/core/VX_lsu_slice.sv new file mode 100644 index 0000000..1fad7d8 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_lsu_slice.sv @@ -0,0 +1,580 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_lsu_slice import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_result_if.master result_if, + VX_lsu_mem_if.master lsu_mem_if +); + localparam NUM_LANES = `NUM_LSU_LANES; + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam RSP_ARB_DATAW= UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + 1 + NUM_REGS_BITS + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1; + localparam LSUQ_SIZEW = `LOG2UP(`LSUQ_IN_SIZE); + localparam REQ_ASHIFT = `CLOG2(LSU_WORD_SIZE); + localparam MEM_ASHIFT = `CLOG2(`MEM_BLOCK_SIZE); + localparam MEM_ADDRW = `MEM_ADDR_WIDTH - MEM_ASHIFT; + + // tag_id = wid + PC + wb + rd + op_type + align + pid + pkt_addr + fence + localparam TAG_ID_WIDTH = NW_WIDTH + PC_BITS + 1 + NUM_REGS_BITS + INST_LSU_BITS + (NUM_LANES * REQ_ASHIFT) + PID_WIDTH + LSUQ_SIZEW + 1; + + // tag = uuid + tag_id + localparam TAG_WIDTH = UUID_WIDTH + TAG_ID_WIDTH; + + VX_result_if #( + .data_t (lsu_res_t) + ) result_rsp_if(); + + VX_result_if #( + .data_t (lsu_res_t) + ) result_no_rsp_if(); + + `UNUSED_VAR (execute_if.data.rs3_data) + + // full address calculation + + wire req_is_fence, rsp_is_fence; + + wire [NUM_LANES-1:0][`XLEN-1:0] full_addr; + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_full_addr + assign full_addr[i] = execute_if.data.rs1_data[i] + `SEXT(`XLEN, execute_if.data.op_args.lsu.offset); + end + + // address type calculation + + wire [NUM_LANES-1:0][MEM_FLAGS_WIDTH-1:0] mem_req_flags; + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_flags + wire [MEM_ADDRW-1:0] block_addr = full_addr[i][MEM_ASHIFT +: MEM_ADDRW]; + // is I/O address + wire [MEM_ADDRW-1:0] io_addr_start = MEM_ADDRW'(`XLEN'(`IO_BASE_ADDR) >> MEM_ASHIFT); + wire [MEM_ADDRW-1:0] io_addr_end = MEM_ADDRW'(`XLEN'(`IO_END_ADDR) >> MEM_ASHIFT); + assign mem_req_flags[i][MEM_REQ_FLAG_FLUSH] = req_is_fence; + assign mem_req_flags[i][MEM_REQ_FLAG_IO] = (block_addr >= io_addr_start) && (block_addr < io_addr_end); + `ifdef LMEM_ENABLE + // is local memory address + wire [MEM_ADDRW-1:0] lmem_addr_start = MEM_ADDRW'(`XLEN'(`LMEM_BASE_ADDR) >> MEM_ASHIFT); + wire [MEM_ADDRW-1:0] lmem_addr_end = MEM_ADDRW'((`XLEN'(`LMEM_BASE_ADDR) + `XLEN'(1 << `LMEM_LOG_SIZE)) >> MEM_ASHIFT); + assign mem_req_flags[i][MEM_REQ_FLAG_LOCAL] = (block_addr >= lmem_addr_start) && (block_addr < lmem_addr_end); + `endif + end + + // schedule memory request + + wire mem_req_valid; + wire [NUM_LANES-1:0] mem_req_mask; + wire mem_req_rw; + wire [NUM_LANES-1:0][LSU_ADDR_WIDTH-1:0] mem_req_addr; + wire [NUM_LANES-1:0][LSU_WORD_SIZE-1:0] mem_req_byteen; + reg [NUM_LANES-1:0][LSU_WORD_SIZE*8-1:0] mem_req_data; + wire [TAG_WIDTH-1:0] mem_req_tag; + wire mem_req_ready; + + wire mem_rsp_valid; + wire [NUM_LANES-1:0] mem_rsp_mask; + wire [NUM_LANES-1:0][LSU_WORD_SIZE*8-1:0] mem_rsp_data; + wire [TAG_WIDTH-1:0] mem_rsp_tag; + wire mem_rsp_sop; + wire mem_rsp_eop; + wire mem_rsp_ready; + + wire mem_req_fire = mem_req_valid && mem_req_ready; + wire mem_rsp_fire = mem_rsp_valid && mem_rsp_ready; + + wire mem_rsp_sop_pkt, mem_rsp_eop_pkt; + wire no_rsp_buf_valid, no_rsp_buf_ready; + + wire [LSUQ_SIZEW-1:0] pkt_waddr, pkt_raddr; + + // fence handling + + reg fence_lock; + + assign req_is_fence = inst_lsu_is_fence(execute_if.data.op_type); + + always @(posedge clk) begin + if (reset) begin + fence_lock <= 0; + end else begin + if (mem_req_fire && req_is_fence && execute_if.data.eop) begin + fence_lock <= 1; + end + if (mem_rsp_fire && rsp_is_fence && mem_rsp_eop_pkt) begin + fence_lock <= 0; + end + end + end + + wire req_skip = req_is_fence && ~execute_if.data.eop; + wire no_rsp_buf_enable = (mem_req_rw && ~execute_if.data.wb) || req_skip; + + assign mem_req_valid = execute_if.valid + && ~req_skip + && ~(no_rsp_buf_enable && ~no_rsp_buf_ready) + && ~fence_lock; + + assign no_rsp_buf_valid = execute_if.valid + && no_rsp_buf_enable + && (req_skip || mem_req_ready) + && ~fence_lock; + + assign execute_if.ready = (mem_req_ready || req_skip) + && ~(no_rsp_buf_enable && ~no_rsp_buf_ready) + && ~fence_lock; + + assign mem_req_mask = execute_if.data.tmask; + assign mem_req_rw = execute_if.data.op_args.lsu.is_store; + + // address formatting + + wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] req_align; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_addr + assign req_align[i] = full_addr[i][REQ_ASHIFT-1:0]; + assign mem_req_addr[i] = full_addr[i][`MEM_ADDR_WIDTH-1:REQ_ASHIFT]; + end + + // byte enable formatting + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_byteen_w + reg [LSU_WORD_SIZE-1:0] mem_req_byteen_w; + always @(*) begin + mem_req_byteen_w = '0; + case (inst_lsu_wsize(execute_if.data.op_type)) + 0: begin // 8-bit + mem_req_byteen_w[req_align[i]] = 1'b1; + end + 1: begin // 16 bit + mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1; + mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1; + end + `ifdef XLEN_64 + 2: begin // 32 bit + mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1; + mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1; + mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1; + mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1; + end + `endif + // 3: 64 bit + default : mem_req_byteen_w = {LSU_WORD_SIZE{1'b1}}; + endcase + end + assign mem_req_byteen[i] = mem_req_byteen_w; + end + + // memory misalignment not supported! + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_missalign + wire lsu_req_fire = execute_if.valid && execute_if.ready; + `RUNTIME_ASSERT((~lsu_req_fire || ~execute_if.data.tmask[i] || req_is_fence || (full_addr[i] % (1 << inst_lsu_wsize(execute_if.data.op_type))) == 0), + ("%t: misaligned memory access, wid=%0d, PC=0x%0h, addr=0x%0h, wsize=%0d! (#%0d)", + $time, execute_if.data.wid, to_fullPC(execute_if.data.PC), full_addr[i], inst_lsu_wsize(execute_if.data.op_type), execute_if.data.uuid)) + end + + // store data formatting + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_req_data + always @(*) begin + mem_req_data[i] = execute_if.data.rs2_data[i]; + case (req_align[i]) + 1: mem_req_data[i][`XLEN-1:8] = execute_if.data.rs2_data[i][`XLEN-9:0]; + 2: mem_req_data[i][`XLEN-1:16] = execute_if.data.rs2_data[i][`XLEN-17:0]; + 3: mem_req_data[i][`XLEN-1:24] = execute_if.data.rs2_data[i][`XLEN-25:0]; + `ifdef XLEN_64 + 4: mem_req_data[i][`XLEN-1:32] = execute_if.data.rs2_data[i][`XLEN-33:0]; + 5: mem_req_data[i][`XLEN-1:40] = execute_if.data.rs2_data[i][`XLEN-41:0]; + 6: mem_req_data[i][`XLEN-1:48] = execute_if.data.rs2_data[i][`XLEN-49:0]; + 7: mem_req_data[i][`XLEN-1:56] = execute_if.data.rs2_data[i][`XLEN-57:0]; + `endif + default:; + endcase + end + end + + // multi-packet load responses could return out-of-order. + // we should track and flag SOP and EOP responses. + + if (PID_BITS != 0) begin : g_pid + reg [`LSUQ_IN_SIZE-1:0][PID_BITS:0] pkt_ctr; + reg [`LSUQ_IN_SIZE-1:0] pkt_sop, pkt_eop; + + wire mem_req_rd_fire = mem_req_fire && ~mem_req_rw; + wire mem_req_rd_sop_fire = mem_req_rd_fire && execute_if.data.sop; + wire mem_req_rd_eop_fire = mem_req_rd_fire && execute_if.data.eop; + wire mem_rsp_eop_fire = mem_rsp_fire && mem_rsp_eop; + wire mem_rsp_eop_pkt_fire= mem_rsp_fire && mem_rsp_eop_pkt; + wire full; + + VX_allocator #( + .SIZE (`LSUQ_IN_SIZE) + ) pkt_allocator ( + .clk (clk), + .reset (reset), + .acquire_en (mem_req_rd_eop_fire), + .acquire_addr(pkt_waddr), + .release_en (mem_rsp_eop_pkt_fire), + .release_addr(pkt_raddr), + `UNUSED_PIN (empty), + .full (full) + ); + + wire rw_collision = mem_req_rd_fire && mem_rsp_eop_fire && (pkt_raddr == pkt_waddr); + + always @(posedge clk) begin + if (reset) begin + pkt_ctr <= '0; + pkt_sop <= '0; + pkt_eop <= '0; + end else begin + if (mem_req_rd_sop_fire) begin + pkt_sop[pkt_waddr] <= 1; + end + if (mem_req_rd_eop_fire) begin + pkt_eop[pkt_waddr] <= 1; + end + if (mem_rsp_fire) begin + pkt_sop[pkt_raddr] <= 0; + end + if (mem_rsp_eop_pkt_fire) begin + pkt_eop[pkt_raddr] <= 0; + end + if (~rw_collision) begin + if (mem_req_rd_fire) begin + pkt_ctr[pkt_waddr] <= pkt_ctr[pkt_waddr] + PID_BITS'(1); + end + if (mem_rsp_eop_fire) begin + pkt_ctr[pkt_raddr] <= pkt_ctr[pkt_raddr] - PID_BITS'(1); + end + end + end + end + + assign mem_rsp_sop_pkt = pkt_sop[pkt_raddr]; + assign mem_rsp_eop_pkt = mem_rsp_eop && pkt_eop[pkt_raddr] && (pkt_ctr[pkt_raddr] == 1); + `RUNTIME_ASSERT(~(mem_req_rd_fire && full), ("%t: allocator full!", $time)) + `RUNTIME_ASSERT(~(mem_req_rd_sop_fire && pkt_ctr[pkt_waddr] != 0), ("%t: oops! broken sop request!", $time)) + `UNUSED_VAR (mem_rsp_sop) + end else begin : g_no_pid + assign pkt_waddr = 0; + assign mem_rsp_sop_pkt = mem_rsp_sop; + assign mem_rsp_eop_pkt = mem_rsp_eop; + `UNUSED_VAR (pkt_raddr) + end + + // pack memory request tag + assign mem_req_tag = { + execute_if.data.uuid, + execute_if.data.wid, + execute_if.data.PC, + execute_if.data.wb, + execute_if.data.rd, + execute_if.data.op_type, + req_align, + execute_if.data.pid, + pkt_waddr, + req_is_fence + }; + + wire lsu_mem_req_valid; + wire lsu_mem_req_rw; + wire [NUM_LANES-1:0] lsu_mem_req_mask; + wire [NUM_LANES-1:0][LSU_WORD_SIZE-1:0] lsu_mem_req_byteen; + wire [NUM_LANES-1:0][LSU_ADDR_WIDTH-1:0] lsu_mem_req_addr; + wire [NUM_LANES-1:0][MEM_FLAGS_WIDTH-1:0] lsu_mem_req_flags; + wire [NUM_LANES-1:0][(LSU_WORD_SIZE*8)-1:0] lsu_mem_req_data; + wire [LSU_TAG_WIDTH-1:0] lsu_mem_req_tag; + wire lsu_mem_req_ready; + + wire lsu_mem_rsp_valid; + wire [NUM_LANES-1:0] lsu_mem_rsp_mask; + wire [NUM_LANES-1:0][(LSU_WORD_SIZE*8)-1:0] lsu_mem_rsp_data; + wire [LSU_TAG_WIDTH-1:0] lsu_mem_rsp_tag; + wire lsu_mem_rsp_ready; + + VX_mem_scheduler #( + .INSTANCE_ID (`SFORMATF(("%s-memsched", INSTANCE_ID))), + .CORE_REQS (NUM_LANES), + .MEM_CHANNELS(NUM_LANES), + .WORD_SIZE (LSU_WORD_SIZE), + .LINE_SIZE (LSU_WORD_SIZE), + .ADDR_WIDTH (LSU_ADDR_WIDTH), + .FLAGS_WIDTH (MEM_FLAGS_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .CORE_QUEUE_SIZE (`LSUQ_IN_SIZE), + .MEM_QUEUE_SIZE (`LSUQ_OUT_SIZE), + .UUID_WIDTH (UUID_WIDTH), + .RSP_PARTIAL (1), + .MEM_OUT_BUF (0), + .CORE_OUT_BUF(0) + ) mem_scheduler ( + .clk (clk), + .reset (reset), + + // Input request + .core_req_valid (mem_req_valid), + .core_req_rw (mem_req_rw), + .core_req_mask (mem_req_mask), + .core_req_byteen(mem_req_byteen), + .core_req_addr (mem_req_addr), + .core_req_flags (mem_req_flags), + .core_req_data (mem_req_data), + .core_req_tag (mem_req_tag), + .core_req_ready (mem_req_ready), + + // request queue info + `UNUSED_PIN (req_queue_empty), + `UNUSED_PIN (req_queue_rw_notify), + + // Output response + .core_rsp_valid (mem_rsp_valid), + .core_rsp_mask (mem_rsp_mask), + .core_rsp_data (mem_rsp_data), + .core_rsp_tag (mem_rsp_tag), + .core_rsp_sop (mem_rsp_sop), + .core_rsp_eop (mem_rsp_eop), + .core_rsp_ready (mem_rsp_ready), + + // Memory request + .mem_req_valid (lsu_mem_req_valid), + .mem_req_rw (lsu_mem_req_rw), + .mem_req_mask (lsu_mem_req_mask), + .mem_req_byteen (lsu_mem_req_byteen), + .mem_req_addr (lsu_mem_req_addr), + .mem_req_flags (lsu_mem_req_flags), + .mem_req_data (lsu_mem_req_data), + .mem_req_tag (lsu_mem_req_tag), + .mem_req_ready (lsu_mem_req_ready), + + // Memory response + .mem_rsp_valid (lsu_mem_rsp_valid), + .mem_rsp_mask (lsu_mem_rsp_mask), + .mem_rsp_data (lsu_mem_rsp_data), + .mem_rsp_tag (lsu_mem_rsp_tag), + .mem_rsp_ready (lsu_mem_rsp_ready) + ); + + assign lsu_mem_if.req_valid = lsu_mem_req_valid; + assign lsu_mem_if.req_data.mask = lsu_mem_req_mask; + assign lsu_mem_if.req_data.rw = lsu_mem_req_rw; + assign lsu_mem_if.req_data.byteen = lsu_mem_req_byteen; + assign lsu_mem_if.req_data.addr = lsu_mem_req_addr; + assign lsu_mem_if.req_data.flags = lsu_mem_req_flags; + assign lsu_mem_if.req_data.data = lsu_mem_req_data; + assign lsu_mem_if.req_data.tag = lsu_mem_req_tag; + assign lsu_mem_req_ready = lsu_mem_if.req_ready; + + assign lsu_mem_rsp_valid = lsu_mem_if.rsp_valid; + assign lsu_mem_rsp_mask = lsu_mem_if.rsp_data.mask; + assign lsu_mem_rsp_data = lsu_mem_if.rsp_data.data; + assign lsu_mem_rsp_tag = lsu_mem_if.rsp_data.tag; + assign lsu_mem_if.rsp_ready = lsu_mem_rsp_ready; + + wire [UUID_WIDTH-1:0] rsp_uuid; + wire [NW_WIDTH-1:0] rsp_wid; + wire [PC_BITS-1:0] rsp_pc; + wire rsp_wb; + wire [NUM_REGS_BITS-1:0] rsp_rd; + wire [INST_LSU_BITS-1:0] rsp_op_type; + wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] rsp_align; + wire [PID_WIDTH-1:0] rsp_pid; + `UNUSED_VAR (rsp_op_type) + + // unpack memory response tag + assign { + rsp_uuid, + rsp_wid, + rsp_pc, + rsp_wb, + rsp_rd, + rsp_op_type, + rsp_align, + rsp_pid, + pkt_raddr, + rsp_is_fence + } = mem_rsp_tag; + + // load response formatting + + reg [NUM_LANES-1:0][`XLEN-1:0] rsp_data; + +`ifdef XLEN_64 +`ifdef EXT_F_ENABLE + // apply nan-boxing to flw outputs + wire rsp_is_float = rsp_rd[5]; +`else + wire rsp_is_float = 0; +`endif +`endif + + for (genvar i = 0; i < NUM_LANES; i++) begin : g_rsp_data + `ifdef XLEN_64 + wire [63:0] rsp_data64 = mem_rsp_data[i]; + wire [31:0] rsp_data32 = (rsp_align[i][2] ? mem_rsp_data[i][63:32] : mem_rsp_data[i][31:0]); + `else + wire [31:0] rsp_data32 = mem_rsp_data[i]; + `endif + wire [15:0] rsp_data16 = rsp_align[i][1] ? rsp_data32[31:16] : rsp_data32[15:0]; + wire [7:0] rsp_data8 = rsp_align[i][0] ? rsp_data16[15:8] : rsp_data16[7:0]; + + always @(*) begin + case (inst_lsu_fmt(rsp_op_type)) + LSU_FMT_B: rsp_data[i] = `XLEN'(signed'(rsp_data8)); + LSU_FMT_H: rsp_data[i] = `XLEN'(signed'(rsp_data16)); + LSU_FMT_BU: rsp_data[i] = `XLEN'(unsigned'(rsp_data8)); + LSU_FMT_HU: rsp_data[i] = `XLEN'(unsigned'(rsp_data16)); + `ifdef XLEN_64 + LSU_FMT_W: rsp_data[i] = rsp_is_float ? (`XLEN'(rsp_data32) | 64'hffffffff00000000) : `XLEN'(signed'(rsp_data32)); + LSU_FMT_WU: rsp_data[i] = `XLEN'(unsigned'(rsp_data32)); + LSU_FMT_D: rsp_data[i] = `XLEN'(signed'(rsp_data64)); + `else + LSU_FMT_W: rsp_data[i] = `XLEN'(signed'(rsp_data32)); + `endif + default: rsp_data[i] = 'x; + endcase + end + end + + // result + + VX_elastic_buffer #( + .DATAW (UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + 1 + NUM_REGS_BITS + (NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1), + .SIZE (2) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_rsp_valid), + .ready_in (mem_rsp_ready), + .data_in ({rsp_uuid, rsp_wid, mem_rsp_mask, rsp_pc, rsp_wb, rsp_rd, rsp_data, rsp_pid, mem_rsp_sop_pkt, mem_rsp_eop_pkt}), + .data_out ({result_rsp_if.data.uuid, result_rsp_if.data.wid, result_rsp_if.data.tmask, result_rsp_if.data.PC, result_rsp_if.data.wb, result_rsp_if.data.rd, result_rsp_if.data.data, result_rsp_if.data.pid, result_rsp_if.data.sop, result_rsp_if.data.eop}), + .valid_out (result_rsp_if.valid), + .ready_out (result_rsp_if.ready) + ); + + VX_elastic_buffer #( + .DATAW (UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + PID_WIDTH + 1 + 1), + .SIZE (2) + ) no_rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (no_rsp_buf_valid), + .ready_in (no_rsp_buf_ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop}), + .data_out ({result_no_rsp_if.data.uuid, result_no_rsp_if.data.wid, result_no_rsp_if.data.tmask, result_no_rsp_if.data.PC, result_no_rsp_if.data.pid, result_no_rsp_if.data.sop, result_no_rsp_if.data.eop}), + .valid_out (result_no_rsp_if.valid), + .ready_out (result_no_rsp_if.ready) + ); + + assign result_no_rsp_if.data.rd = '0; + assign result_no_rsp_if.data.wb = 1'b0; + assign result_no_rsp_if.data.data = result_rsp_if.data.data; // arbiter MUX optimization + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_ARB_DATAW), + .ARBITER ("P"), // prioritize result_rsp_if + .OUT_BUF (3) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in ({result_no_rsp_if.valid, result_rsp_if.valid}), + .ready_in ({result_no_rsp_if.ready, result_rsp_if.ready}), + .data_in ({result_no_rsp_if.data, result_rsp_if.data}), + .data_out (result_if.data), + .valid_out (result_if.valid), + .ready_out (result_if.ready), + `UNUSED_PIN (sel_out) + ); + +`ifdef DBG_TRACE_MEM + always @(posedge clk) begin + if (execute_if.valid && fence_lock) begin + `TRACE(2, ("%t: *** %s fence wait\n", $time, INSTANCE_ID)) + end + if (mem_req_fire) begin + if (mem_req_rw) begin + `TRACE(2, ("%t: %s Wr Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, INSTANCE_ID, execute_if.data.wid, to_fullPC(execute_if.data.PC), mem_req_mask)) + `TRACE_ARRAY1D(2, "0x%h", full_addr, NUM_LANES) + `TRACE(2, (", flags=")) + `TRACE_ARRAY1D(2, "%b", mem_req_flags, NUM_LANES) + `TRACE(2, (", byteen=0x%0h, data=", mem_req_byteen)) + `TRACE_ARRAY1D(2, "0x%0h", mem_req_data, NUM_LANES) + `TRACE(2, (", sop=%b, pid=%0d, eop=%b, tag=0x%0h (#%0d)\n", execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, mem_req_tag, execute_if.data.uuid)) + end else begin + `TRACE(2, ("%t: %s Rd Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, INSTANCE_ID, execute_if.data.wid, to_fullPC(execute_if.data.PC), mem_req_mask)) + `TRACE_ARRAY1D(2, "0x%h", full_addr, NUM_LANES) + `TRACE(2, (", flags=")) + `TRACE_ARRAY1D(2, "%b", mem_req_flags, NUM_LANES) + `TRACE(2, (", byteen=0x%0h, rd=%0d, pid=%0d, sop=%b, eop=%b, tag=0x%0h (#%0d)\n", mem_req_byteen, execute_if.data.rd, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, mem_req_tag, execute_if.data.uuid)) + end + end + if (mem_rsp_fire) begin + `TRACE(2, ("%t: %s Rsp: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d, pid=%0d, sop=%b, eop=%b, data=", + $time, INSTANCE_ID, rsp_wid, to_fullPC(rsp_pc), mem_rsp_mask, rsp_rd, rsp_pid, mem_rsp_sop_pkt, mem_rsp_eop_pkt)) + `TRACE_ARRAY1D(2, "0x%0h", mem_rsp_data, NUM_LANES) + `TRACE(2, (", tag=0x%0h (#%0d)\n", mem_rsp_tag, rsp_uuid)) + end + end +`endif + +`ifdef SCOPE +`ifdef DBG_SCOPE_LSU + `SCOPE_IO_SWITCH (1); + wire reset_negedge; + `NEG_EDGE (reset_negedge, reset); + `SCOPE_TAP_EX (0, 3, 4, 2, ( + 1 + NUM_LANES * (`XLEN + LSU_WORD_SIZE + LSU_WORD_SIZE * 8) + UUID_WIDTH + NUM_LANES * LSU_WORD_SIZE * 8 + UUID_WIDTH + ), { + mem_req_valid, + mem_req_ready, + mem_rsp_valid, + mem_rsp_ready + }, { + mem_req_fire, + mem_rsp_fire + }, { + mem_req_rw, + full_addr, + mem_req_byteen, + mem_req_data, + execute_if.data.uuid, + rsp_data, + rsp_uuid + }, + reset_negedge, 1'b0, 4096 + ); +`else + `SCOPE_IO_UNUSED(0) +`endif +`endif + +`ifdef CHIPSCOPE +`ifdef DBG_SCOPE_LSU + ila_lsu ila_lsu_inst ( + .clk (clk), + .probe0 ({execute_if.valid, execute_if.data, execute_if.ready}), + .probe1 ({lsu_mem_if.req_valid, lsu_mem_if.req_data, lsu_mem_if.req_ready}), + .probe2 ({lsu_mem_if.rsp_valid, lsu_mem_if.rsp_data, lsu_mem_if.rsp_ready}) + ); +`endif +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_lsu_unit.sv b/designs/src/vortex/rtl/core/VX_lsu_unit.sv new file mode 100644 index 0000000..b3962c1 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_lsu_unit.sv @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_lsu_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH], + VX_lsu_mem_if.master lsu_mem_if [`NUM_LSU_BLOCKS] +); + localparam BLOCK_SIZE = `NUM_LSU_BLOCKS; + localparam NUM_LANES = `NUM_LSU_LANES; + + `SCOPE_IO_SWITCH (BLOCK_SIZE); + + VX_execute_if #( + .data_t (lsu_exe_t) + ) per_block_execute_if[BLOCK_SIZE](); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (3) + ) dispatch_unit ( + .clk (clk), + .reset (reset), + .dispatch_if(dispatch_if), + .execute_if (per_block_execute_if) + ); + + VX_result_if #( + .data_t (lsu_res_t) + ) per_block_result_if[BLOCK_SIZE](); + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_blocks + VX_lsu_slice #( + .INSTANCE_ID (`SFORMATF(("%s%0d", INSTANCE_ID, block_idx))) + ) lsu_slice( + `SCOPE_IO_BIND (block_idx) + .clk (clk), + .reset (reset), + .execute_if (per_block_execute_if[block_idx]), + .result_if (per_block_result_if[block_idx]), + .lsu_mem_if (lsu_mem_if[block_idx]) + ); + end + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (3) + ) gather_unit ( + .clk (clk), + .reset (reset), + .result_if (per_block_result_if), + .commit_if (commit_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_mem_unit.sv b/designs/src/vortex/rtl/core/VX_mem_unit.sv new file mode 100644 index 0000000..dbae0c4 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_mem_unit.sv @@ -0,0 +1,258 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_mem_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output lmem_perf_t lmem_perf, + output coalescer_perf_t coalescer_perf, +`endif + + VX_lsu_mem_if.slave lsu_mem_if [`NUM_LSU_BLOCKS], + VX_mem_bus_if.master dcache_bus_if [DCACHE_NUM_REQS] +); + VX_lsu_mem_if #( + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LSU_TAG_WIDTH) + ) lsu_dcache_if[`NUM_LSU_BLOCKS](); + +`ifdef LMEM_ENABLE + + `STATIC_ASSERT(`IS_DIVISBLE((1 << `LMEM_LOG_SIZE), `MEM_BLOCK_SIZE), ("invalid parameter")) + `STATIC_ASSERT(0 == (`LMEM_BASE_ADDR % (1 << `LMEM_LOG_SIZE)), ("invalid parameter")) + + localparam LMEM_ADDR_WIDTH = `LMEM_LOG_SIZE - `CLOG2(LSU_WORD_SIZE); + + VX_lsu_mem_if #( + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LSU_TAG_WIDTH) + ) lsu_lmem_if[`NUM_LSU_BLOCKS](); + + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lmem_switches + VX_lmem_switch #( + .GLOBAL_OUT_BUF(1), + .LOCAL_OUT_BUF(1), + .RSP_OUT_BUF (1), + .ARBITER ("P") + ) lmem_switch ( + .clk (clk), + .reset (reset), + .lsu_in_if (lsu_mem_if[i]), + .global_out_if(lsu_dcache_if[i]), + .local_out_if (lsu_lmem_if[i]) + ); + end + + VX_lsu_mem_if #( + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LMEM_TAG_WIDTH) + ) lmem_arb_if[1](); + + VX_lsu_mem_arb #( + .NUM_INPUTS (`NUM_LSU_BLOCKS), + .NUM_OUTPUTS(1), + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LSU_TAG_WIDTH), + .TAG_SEL_IDX(0), + .ARBITER ("R"), + .REQ_OUT_BUF(0), + .RSP_OUT_BUF(2) + ) lmem_arb ( + .clk (clk), + .reset (reset), + .bus_in_if (lsu_lmem_if), + .bus_out_if (lmem_arb_if) + ); + + VX_mem_bus_if #( + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LMEM_TAG_WIDTH) + ) lmem_adapt_if[`NUM_LSU_LANES](); + + VX_lsu_adapter #( + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LMEM_TAG_WIDTH), + .TAG_SEL_BITS (LMEM_TAG_WIDTH - UUID_WIDTH), + .ARBITER ("P"), + .REQ_OUT_BUF (3), + .RSP_OUT_BUF (0) + ) lmem_adapter ( + .clk (clk), + .reset (reset), + .lsu_mem_if (lmem_arb_if[0]), + .mem_bus_if (lmem_adapt_if) + ); + + VX_local_mem #( + .INSTANCE_ID(`SFORMATF(("%s-lmem", INSTANCE_ID))), + .SIZE (1 << `LMEM_LOG_SIZE), + .NUM_REQS (`NUM_LSU_LANES), + .NUM_BANKS (`LMEM_NUM_BANKS), + .WORD_SIZE (LSU_WORD_SIZE), + .ADDR_WIDTH (LMEM_ADDR_WIDTH), + .TAG_WIDTH (LMEM_TAG_WIDTH), + .OUT_BUF (3) + ) local_mem ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .lmem_perf (lmem_perf), + `endif + .mem_bus_if (lmem_adapt_if) + ); + +`else + +`ifdef PERF_ENABLE + assign lmem_perf = '0; +`endif + + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lsu_dcache_if + `ASSIGN_VX_MEM_BUS_IF (lsu_dcache_if[i], lsu_mem_if[i]); + end + +`endif + + VX_lsu_mem_if #( + .NUM_LANES (DCACHE_CHANNELS), + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH) + ) dcache_coalesced_if[`NUM_LSU_BLOCKS](); + +`ifdef PERF_ENABLE + wire [`NUM_LSU_BLOCKS-1:0][PERF_CTR_BITS-1:0] per_block_coalescer_misses; + wire [PERF_CTR_BITS-1:0] coalescer_misses; + VX_reduce_tree #( + .IN_W (PERF_CTR_BITS), + .N (`NUM_LSU_BLOCKS), + .OP ("+") + ) coalescer_reduce ( + .data_in (per_block_coalescer_misses), + .data_out (coalescer_misses) + ); + `BUFFER(coalescer_perf.misses, coalescer_misses); +`endif + + if ((`NUM_LSU_LANES > 1) && (LSU_WORD_SIZE != DCACHE_WORD_SIZE)) begin : g_enabled + + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_coalescers + VX_mem_coalescer #( + .INSTANCE_ID (`SFORMATF(("%s-coalescer%0d", INSTANCE_ID, i))), + .NUM_REQS (`NUM_LSU_LANES), + .DATA_IN_SIZE (LSU_WORD_SIZE), + .DATA_OUT_SIZE (DCACHE_WORD_SIZE), + .ADDR_WIDTH (LSU_ADDR_WIDTH), + .FLAGS_WIDTH (MEM_FLAGS_WIDTH), + .TAG_WIDTH (LSU_TAG_WIDTH), + .UUID_WIDTH (UUID_WIDTH), + .QUEUE_SIZE (`LSUQ_OUT_SIZE), + .PERF_CTR_BITS (PERF_CTR_BITS) + ) mem_coalescer ( + .clk (clk), + .reset (reset), + + `ifdef PERF_ENABLE + .misses (per_block_coalescer_misses[i]), + `else + `UNUSED_PIN (misses), + `endif + + // Input request + .in_req_valid (lsu_dcache_if[i].req_valid), + .in_req_mask (lsu_dcache_if[i].req_data.mask), + .in_req_rw (lsu_dcache_if[i].req_data.rw), + .in_req_byteen (lsu_dcache_if[i].req_data.byteen), + .in_req_addr (lsu_dcache_if[i].req_data.addr), + .in_req_flags (lsu_dcache_if[i].req_data.flags), + .in_req_data (lsu_dcache_if[i].req_data.data), + .in_req_tag (lsu_dcache_if[i].req_data.tag), + .in_req_ready (lsu_dcache_if[i].req_ready), + + // Input response + .in_rsp_valid (lsu_dcache_if[i].rsp_valid), + .in_rsp_mask (lsu_dcache_if[i].rsp_data.mask), + .in_rsp_data (lsu_dcache_if[i].rsp_data.data), + .in_rsp_tag (lsu_dcache_if[i].rsp_data.tag), + .in_rsp_ready (lsu_dcache_if[i].rsp_ready), + + // Output request + .out_req_valid (dcache_coalesced_if[i].req_valid), + .out_req_mask (dcache_coalesced_if[i].req_data.mask), + .out_req_rw (dcache_coalesced_if[i].req_data.rw), + .out_req_byteen (dcache_coalesced_if[i].req_data.byteen), + .out_req_addr (dcache_coalesced_if[i].req_data.addr), + .out_req_flags (dcache_coalesced_if[i].req_data.flags), + .out_req_data (dcache_coalesced_if[i].req_data.data), + .out_req_tag (dcache_coalesced_if[i].req_data.tag), + .out_req_ready (dcache_coalesced_if[i].req_ready), + + // Output response + .out_rsp_valid (dcache_coalesced_if[i].rsp_valid), + .out_rsp_mask (dcache_coalesced_if[i].rsp_data.mask), + .out_rsp_data (dcache_coalesced_if[i].rsp_data.data), + .out_rsp_tag (dcache_coalesced_if[i].rsp_data.tag), + .out_rsp_ready (dcache_coalesced_if[i].rsp_ready) + ); + end + + end else begin : g_passthru + + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_dcache_coalesced_if + `ASSIGN_VX_MEM_BUS_IF (dcache_coalesced_if[i], lsu_dcache_if[i]); + `ifdef PERF_ENABLE + assign per_block_coalescer_misses[i] = '0; + `endif + end + + end + + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_dcache_adapters + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH) + ) dcache_bus_tmp_if[DCACHE_CHANNELS](); + + VX_lsu_adapter #( + .NUM_LANES (DCACHE_CHANNELS), + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH), + .TAG_SEL_BITS (DCACHE_TAG_WIDTH - UUID_WIDTH), + .ARBITER ("P"), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (0) + ) dcache_adapter ( + .clk (clk), + .reset (reset), + .lsu_mem_if (dcache_coalesced_if[i]), + .mem_bus_if (dcache_bus_tmp_if) + ); + + for (genvar j = 0; j < DCACHE_CHANNELS; ++j) begin : g_dcache_bus_if + `ASSIGN_VX_MEM_BUS_IF (dcache_bus_if[i * DCACHE_CHANNELS + j], dcache_bus_tmp_if[j]); + end + + end + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_mem_unit_top.sv b/designs/src/vortex/rtl/core/VX_mem_unit_top.sv new file mode 100644 index 0000000..6a322f8 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_mem_unit_top.sv @@ -0,0 +1,127 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_mem_unit_top import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter LSU_WORD_WIDTH = LSU_WORD_SIZE * 8 +) ( + // Clock + input wire clk, + input wire reset, + + // LSU memory request + input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_valid, + input wire [`NUM_LSU_BLOCKS-1:0] lsu_req_rw, + input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0] lsu_req_mask, + input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_SIZE-1:0] lsu_req_byteen, + input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_ADDR_WIDTH-1:0] lsu_req_addr, + input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][MEM_FLAGS_WIDTH-1:0] lsu_req_flags, + input wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_WIDTH-1:0] lsu_req_data, + input wire [`NUM_LSU_BLOCKS-1:0][LSU_TAG_WIDTH-1:0] lsu_req_tag, + output wire [`NUM_LSU_BLOCKS-1:0] lsu_req_ready, + + // LSU memory response + output wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_valid, + output wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0] lsu_rsp_mask, + output wire [`NUM_LSU_BLOCKS-1:0][`NUM_LSU_LANES-1:0][LSU_WORD_WIDTH-1:0] lsu_rsp_data, + output wire [`NUM_LSU_BLOCKS-1:0][LSU_TAG_WIDTH-1:0] lsu_rsp_tag, + input wire [`NUM_LSU_BLOCKS-1:0] lsu_rsp_ready, + + // Memory request + output wire [DCACHE_NUM_REQS-1:0] mem_req_valid, + output wire [DCACHE_NUM_REQS-1:0] mem_req_rw, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE-1:0] mem_req_byteen, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_ADDR_WIDTH-1:0] mem_req_addr, + output wire [DCACHE_NUM_REQS-1:0][MEM_FLAGS_WIDTH-1:0] mem_req_flags, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] mem_req_data, + output wire [DCACHE_NUM_REQS-1:0][DCACHE_TAG_WIDTH-1:0] mem_req_tag, + input wire [DCACHE_NUM_REQS-1:0] mem_req_ready, + + // Memory response + input wire [DCACHE_NUM_REQS-1:0] mem_rsp_valid, + input wire [DCACHE_NUM_REQS-1:0][DCACHE_WORD_SIZE*8-1:0] mem_rsp_data, + input wire [DCACHE_NUM_REQS-1:0][DCACHE_TAG_WIDTH-1:0] mem_rsp_tag, + output wire [DCACHE_NUM_REQS-1:0] mem_rsp_ready +); + VX_lsu_mem_if #( + .NUM_LANES (`NUM_LSU_LANES), + .DATA_SIZE (LSU_WORD_SIZE), + .TAG_WIDTH (LSU_TAG_WIDTH) + ) lsu_mem_if[`NUM_LSU_BLOCKS](); + + // LSU memory request + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lsu_mem_req + assign lsu_mem_if[i].req_valid = lsu_req_valid[i]; + assign lsu_mem_if[i].req_data.rw = lsu_req_rw[i]; + assign lsu_mem_if[i].req_data.mask = lsu_req_mask[i]; + assign lsu_mem_if[i].req_data.byteen = lsu_req_byteen[i]; + assign lsu_mem_if[i].req_data.addr = lsu_req_addr[i]; + assign lsu_mem_if[i].req_data.flags = lsu_req_flags[i]; + assign lsu_mem_if[i].req_data.data = lsu_req_data[i]; + assign lsu_mem_if[i].req_data.tag = lsu_req_tag[i]; + assign lsu_req_ready[i] = lsu_mem_if[i].req_ready; + end + + // LSU memory response + for (genvar i = 0; i < `NUM_LSU_BLOCKS; ++i) begin : g_lsu_rsp + assign lsu_rsp_valid[i] = lsu_mem_if[i].rsp_valid; + assign lsu_rsp_mask[i] = lsu_mem_if[i].rsp_data.mask; + assign lsu_rsp_data[i] = lsu_mem_if[i].rsp_data.data; + assign lsu_rsp_tag[i] = lsu_mem_if[i].rsp_data.tag; + assign lsu_mem_if[i].rsp_ready = lsu_rsp_ready[i]; + end + + VX_mem_bus_if #( + .DATA_SIZE (DCACHE_WORD_SIZE), + .TAG_WIDTH (DCACHE_TAG_WIDTH) + ) mem_bus_if[DCACHE_NUM_REQS](); + + // memory request + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin : g_mem_req + assign mem_req_valid[i] = mem_bus_if[i].req_valid; + assign mem_req_rw[i] = mem_bus_if[i].req_data.rw; + assign mem_req_byteen[i] = mem_bus_if[i].req_data.byteen; + assign mem_req_addr[i] = mem_bus_if[i].req_data.addr; + assign mem_req_flags[i] = mem_bus_if[i].req_data.flags; + assign mem_req_data[i] = mem_bus_if[i].req_data.data; + assign mem_req_tag[i] = mem_bus_if[i].req_data.tag; + assign mem_bus_if[i].req_ready = mem_req_ready[i]; + end + + // memory response + for (genvar i = 0; i < DCACHE_NUM_REQS; ++i) begin : g_mem_bus_rsp + assign mem_bus_if[i].rsp_valid = mem_rsp_valid[i]; + assign mem_bus_if[i].rsp_data.tag = mem_rsp_tag[i]; + assign mem_bus_if[i].rsp_data.data = mem_rsp_data[i]; + assign mem_rsp_ready[i] = mem_bus_if[i].rsp_ready; + end + +`ifdef PERF_ENABLE + VX_cache_pkg::cache_perf_t lmem_perf = '0; +`endif + + VX_mem_unit #( + .INSTANCE_ID (INSTANCE_ID) + ) mem_unit ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .lmem_perf (lmem_perf), + `endif + .lsu_mem_if (lsu_mem_if), + .dcache_bus_if (mem_bus_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_opc_unit.sv b/designs/src/vortex/rtl/core/VX_opc_unit.sv new file mode 100644 index 0000000..d0821b0 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_opc_unit.sv @@ -0,0 +1,347 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +// reset all GPRs in debug mode +`ifdef SIMULATION +`ifndef NDEBUG +`define GPR_RESET +`endif +`endif + +module VX_opc_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter NUM_BANKS = 4, + parameter OUT_BUF = 3 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire [PERF_CTR_BITS-1:0] perf_stalls, +`endif + + VX_writeback_if.slave writeback_if, + VX_scoreboard_if.slave scoreboard_if, + VX_operands_if.master operands_if +); + `UNUSED_SPARAM (INSTANCE_ID) + + localparam REQ_SEL_WIDTH = SRC_OPD_WIDTH; + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam BANK_DATA_WIDTH = `XLEN * `SIMD_WIDTH; + localparam BANK_DATA_SIZE = BANK_DATA_WIDTH / 8; + + localparam PER_OPC_WARPS = PER_ISSUE_WARPS / `NUM_OPCS; + localparam PER_OPC_NW_BITS = `CLOG2(PER_OPC_WARPS); + localparam BANK_SIZE = (NUM_REGS * SIMD_COUNT * PER_OPC_WARPS) / NUM_BANKS; + localparam BANK_ADDR_WIDTH = `CLOG2(BANK_SIZE); + + localparam REG_REM_BITS = NUM_REGS_BITS - BANK_SEL_BITS; + + localparam META_DATAW = UUID_WIDTH + ISSUE_WIS_W + SIMD_IDX_W + `SIMD_WIDTH + PC_BITS + 1 + EX_BITS + INST_OP_BITS + INST_ARGS_BITS + NUM_REGS_BITS + 1 + 1; + localparam OUT_DATAW = $bits(operands_t); + + `UNUSED_VAR (writeback_if.data.sop) + + wire [NUM_SRC_OPDS-1:0] src_valid; + wire [NUM_SRC_OPDS-1:0] req_valid_in, req_ready_in; + wire [NUM_SRC_OPDS-1:0][REG_REM_BITS-1:0] req_addr_in; + wire [NUM_SRC_OPDS-1:0][BANK_SEL_WIDTH-1:0] req_bank_idx; + + wire [NUM_BANKS-1:0] gpr_rd_valid, gpr_rd_ready; + wire [NUM_BANKS-1:0] gpr_rd_valid_st1, gpr_rd_valid_st2; + wire [NUM_BANKS-1:0][REG_REM_BITS-1:0] gpr_rd_reg, gpr_rd_reg_st1; + wire [NUM_BANKS-1:0][`SIMD_WIDTH-1:0][`XLEN-1:0] gpr_rd_data_st2; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rd_opd, gpr_rd_opd_st1, gpr_rd_opd_st2; + + wire [`SIMD_WIDTH-1:0] simd_out; + wire [SIMD_IDX_W-1:0] simd_pid; + wire simd_sop, simd_eop; + + wire pipe_ready_in; + wire pipe_valid_st1, pipe_ready_st1; + wire pipe_valid_st2, pipe_ready_st2; + wire [META_DATAW-1:0] pipe_mdata, pipe_mdata_st1, pipe_mdata_st2; + + reg [NUM_SRC_OPDS-1:0][(`SIMD_WIDTH * `XLEN)-1:0] opd_buffer_st2, opd_buffer_n_st2; + + reg [NUM_SRC_OPDS-1:0] opd_fetched_st1; + + reg has_collision; + wire has_collision_st1; + + wire [NUM_SRC_OPDS-1:0][NUM_REGS_BITS-1:0] src_regs; + assign src_regs = {scoreboard_if.data.rs3, scoreboard_if.data.rs2, scoreboard_if.data.rs1}; + + for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_gpr_rd_reg + assign req_addr_in[i] = src_regs[i][NUM_REGS_BITS-1 -: REG_REM_BITS]; + end + + for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_req_bank_idx + if (NUM_BANKS != 1) begin : g_bn + assign req_bank_idx[i] = src_regs[i][BANK_SEL_BITS-1:0]; + end else begin : g_b1 + assign req_bank_idx[i] = '0; + end + end + + for (genvar i = 0; i < NUM_SRC_OPDS; ++i) begin : g_src_valid + assign src_valid[i] = scoreboard_if.data.used_rs[i] && (src_regs[i] != 0) && ~opd_fetched_st1[i]; + end + + assign req_valid_in = {NUM_SRC_OPDS{scoreboard_if.valid}} & src_valid; + + VX_stream_xbar #( + .NUM_INPUTS (NUM_SRC_OPDS), + .NUM_OUTPUTS (NUM_BANKS), + .DATAW (REG_REM_BITS), + .ARBITER ("P"), // use priority arbiter + .OUT_BUF (0) // no output buffering + ) req_xbar ( + .clk (clk), + .reset (reset), + `UNUSED_PIN(collisions), + .valid_in (req_valid_in), + .data_in (req_addr_in), + .sel_in (req_bank_idx), + .ready_in (req_ready_in), + .valid_out (gpr_rd_valid), + .data_out (gpr_rd_reg), + .sel_out (gpr_rd_opd), + .ready_out (gpr_rd_ready) + ); + + assign gpr_rd_ready = {NUM_BANKS{pipe_ready_in}}; + + always @(*) begin + has_collision = 0; + for (integer i = 0; i < NUM_SRC_OPDS; ++i) begin + for (integer j = 1; j < (NUM_SRC_OPDS-i); ++j) begin + has_collision |= src_valid[i] + && src_valid[j+i] + && (req_bank_idx[i] == req_bank_idx[j+i]); + end + end + end + + wire opd_last_fetch = pipe_ready_in && ~has_collision; + + // simd iterator (skip requests with inactive threads) + VX_nz_iterator #( + .DATAW (`SIMD_WIDTH), + .N (SIMD_COUNT) + ) simd_iter ( + .clk (clk), + .reset (reset), + .valid_in(scoreboard_if.valid), + .data_in (scoreboard_if.data.tmask), + .next (opd_last_fetch), + `UNUSED_PIN (valid_out), + .data_out(simd_out), + .pid (simd_pid), + .sop (simd_sop), + .eop (simd_eop) + ); + + assign pipe_mdata = { + scoreboard_if.data.uuid, + scoreboard_if.data.wis, + simd_pid, + simd_out, + scoreboard_if.data.PC, + scoreboard_if.data.wb, + scoreboard_if.data.ex_type, + scoreboard_if.data.op_type, + scoreboard_if.data.op_args, + scoreboard_if.data.rd, + simd_sop, + simd_eop + }; + + assign scoreboard_if.ready = opd_last_fetch && simd_eop; + + wire pipe_fire_st1 = pipe_valid_st1 && pipe_ready_st1; + wire pipe_fire_st2 = pipe_valid_st2 && pipe_ready_st2; + + VX_pipe_buffer #( + .DATAW (NUM_BANKS + META_DATAW + 1 + NUM_BANKS * (REG_REM_BITS + REQ_SEL_WIDTH)), + .RESETW (1) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .valid_in (scoreboard_if.valid), + .ready_in (pipe_ready_in), + .data_in ({gpr_rd_valid, pipe_mdata, has_collision, gpr_rd_reg, gpr_rd_opd}), + .data_out ({gpr_rd_valid_st1, pipe_mdata_st1, has_collision_st1, gpr_rd_reg_st1, gpr_rd_opd_st1}), + .valid_out(pipe_valid_st1), + .ready_out(pipe_ready_st1) + ); + + wire [NUM_SRC_OPDS-1:0] req_fire_in = req_valid_in & req_ready_in; + + always @(posedge clk) begin + if (reset || opd_last_fetch) begin + opd_fetched_st1 <= '0; + end else begin + opd_fetched_st1 <= opd_fetched_st1 | req_fire_in; + end + end + + wire pipe_valid2_st1 = pipe_valid_st1 && ~has_collision_st1; + + VX_pipe_buffer #( + .DATAW (NUM_BANKS * (1 + REQ_SEL_WIDTH) + META_DATAW), + .RESETW (1) + ) pipe_reg2 ( + .clk (clk), + .reset (reset), + .valid_in (pipe_valid2_st1), + .ready_in (pipe_ready_st1), + .data_in ({gpr_rd_valid_st1, gpr_rd_opd_st1, pipe_mdata_st1}), + .data_out ({gpr_rd_valid_st2, gpr_rd_opd_st2, pipe_mdata_st2}), + .valid_out(pipe_valid_st2), + .ready_out(pipe_ready_st2) + ); + + always @(*) begin + opd_buffer_n_st2 = opd_buffer_st2; + for (integer b = 0; b < NUM_BANKS; ++b) begin + if (gpr_rd_valid_st2[b]) begin + opd_buffer_n_st2[gpr_rd_opd_st2[b]] = gpr_rd_data_st2[b]; + end + end + end + + always @(posedge clk) begin + if (reset || pipe_fire_st2) begin + opd_buffer_st2 <= '0; // clear on reset or when data is sent out + end else begin + opd_buffer_st2 <= opd_buffer_n_st2; + end + end + + wire [BANK_ADDR_WIDTH-1:0] gpr_wr_addr; + if (SIMD_COUNT != 1) begin : g_gpr_wr_addr_sid + wire [PER_OPC_NW_BITS + REG_REM_BITS-1:0] tmp; + `CONCAT(tmp, writeback_if.data.wis[ISSUE_WIS_W-1 -: PER_OPC_NW_BITS], + writeback_if.data.rd[NUM_REGS_BITS-1 -: REG_REM_BITS], PER_OPC_NW_BITS, REG_REM_BITS) + assign gpr_wr_addr = {writeback_if.data.sid, tmp}; + end else begin : g_gpr_wr_addr + `CONCAT(gpr_wr_addr, writeback_if.data.wis[ISSUE_WIS_W-1 -: PER_OPC_NW_BITS], + writeback_if.data.rd[NUM_REGS_BITS-1 -: REG_REM_BITS], PER_OPC_NW_BITS, REG_REM_BITS) + end + + wire [BANK_SEL_WIDTH-1:0] gpr_wr_bank_idx; + if (NUM_BANKS != 1) begin : g_gpr_wr_bank_idx_bn + assign gpr_wr_bank_idx = writeback_if.data.rd[BANK_SEL_BITS-1:0]; + end else begin : g_gpr_wr_bank_idx_b1 + assign gpr_wr_bank_idx = '0; + end + + wire [BANK_DATA_SIZE-1:0] gpr_wr_byteen; + for (genvar i = 0; i < `SIMD_WIDTH; ++i) begin : g_gpr_wr_byteen + assign gpr_wr_byteen[i*XLENB+:XLENB] = {XLENB{writeback_if.data.tmask[i]}}; + end + + // GPR banks + for (genvar b = 0; b < NUM_BANKS; ++b) begin : g_gpr_rams + wire gpr_wr_enabled; + if (BANK_SEL_BITS != 0) begin : g_gpr_wr_enabled_bn + assign gpr_wr_enabled = writeback_if.valid && (gpr_wr_bank_idx == BANK_SEL_BITS'(b)); + end else begin : g_gpr_wr_enabled_b1 + assign gpr_wr_enabled = writeback_if.valid; + end + + wire [BANK_ADDR_WIDTH-1:0] gpr_rd_addr; + if (SIMD_COUNT != 1) begin : g_gpr_rd_addr_sid + wire [PER_OPC_NW_BITS + REG_REM_BITS-1:0] tmp; + `CONCAT(tmp, pipe_mdata_st1[META_DATAW-UUID_WIDTH-1 -: PER_OPC_NW_BITS], + gpr_rd_reg_st1[b], PER_OPC_NW_BITS, REG_REM_BITS) + assign gpr_rd_addr = {pipe_mdata_st1[META_DATAW-UUID_WIDTH-ISSUE_WIS_W-1 -: SIMD_IDX_W], tmp}; + end else begin : g_gpr_rd_addr + `CONCAT(gpr_rd_addr, pipe_mdata_st1[META_DATAW-UUID_WIDTH-1 -: PER_OPC_NW_BITS], + gpr_rd_reg_st1[b], PER_OPC_NW_BITS, REG_REM_BITS) + end + + VX_dp_ram #( + .DATAW (BANK_DATA_WIDTH), + .SIZE (BANK_SIZE), + .WRENW (BANK_DATA_SIZE), + `ifdef GPR_RESET + .RESET_RAM (1), + `endif + .OUT_REG (1), + .RDW_MODE ("R") + ) gpr_ram ( + .clk (clk), + .reset (reset), + .read (pipe_fire_st1), + .wren (gpr_wr_byteen), + .write (gpr_wr_enabled), + .waddr (gpr_wr_addr), + .wdata (writeback_if.data.data), + .raddr (gpr_rd_addr), + .rdata (gpr_rd_data_st2[b]) + ); + end + + // output buffer + VX_elastic_buffer #( + .DATAW (OUT_DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (pipe_valid_st2), + .ready_in (pipe_ready_st2), + .data_in ({pipe_mdata_st2[META_DATAW-1:2], // remove sop/eop + opd_buffer_n_st2, // operand data + pipe_mdata_st2[1:0]}), // sop/eop + .data_out ({ + operands_if.data.uuid, + operands_if.data.wis, + operands_if.data.sid, + operands_if.data.tmask, + operands_if.data.PC, + operands_if.data.wb, + operands_if.data.ex_type, + operands_if.data.op_type, + operands_if.data.op_args, + operands_if.data.rd, + operands_if.data.rs3_data, + operands_if.data.rs2_data, + operands_if.data.rs1_data, + operands_if.data.sop, + operands_if.data.eop + }), + .valid_out(operands_if.valid), + .ready_out(operands_if.ready) + ); + +`ifdef PERF_ENABLE + reg [PERF_CTR_BITS-1:0] collisions_r; + always @(posedge clk) begin + if (reset) begin + collisions_r <= '0; + end else begin + collisions_r <= collisions_r + PERF_CTR_BITS'(scoreboard_if.valid && pipe_ready_in && has_collision); + end + end + assign perf_stalls = collisions_r; +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_operands.sv b/designs/src/vortex/rtl/core/VX_operands.sv new file mode 100644 index 0000000..4d70e05 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_operands.sv @@ -0,0 +1,119 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_operands import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter ISSUE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output wire [PERF_CTR_BITS-1:0] perf_stalls, +`endif + + VX_writeback_if.slave writeback_if, + VX_scoreboard_if.slave scoreboard_if, + VX_operands_if.master operands_if +); + `UNUSED_SPARAM (ISSUE_ID) + + localparam OUT_DATAW = $bits(operands_t); + + // LSU cannot handle partial requests from multiple warps at the same time + // this ensure that OPCs are dispatched atomically + localparam OUT_ARB_STICKY = (`NUM_OPCS != 1) && (SIMD_COUNT != 1); + +`ifdef PERF_ENABLE + wire [`NUM_OPCS-1:0][PERF_CTR_BITS-1:0] per_opc_perf_stalls; +`endif + + VX_operands_if per_opc_operands_if[`NUM_OPCS](); + + wire [NUM_OPCS_W-1:0] sb_opc, wb_opc; + if (`NUM_OPCS != 1) begin : g_wis_opc + assign sb_opc = scoreboard_if.data.wis[NUM_OPCS_W-1:0]; + assign wb_opc = writeback_if.data.wis[NUM_OPCS_W-1:0]; + end else begin : g_wis_opc + assign sb_opc = 0; + assign wb_opc = 0; + end + + wire [`NUM_OPCS-1:0] scoreboard_ready_in; + assign scoreboard_if.ready = scoreboard_ready_in[sb_opc]; + + for (genvar i = 0; i < `NUM_OPCS; i++) begin : g_collectors + // select scoreboard interface + VX_scoreboard_if opc_scoreboard_if(); + assign opc_scoreboard_if.valid = scoreboard_if.valid && (sb_opc == i); + assign opc_scoreboard_if.data = scoreboard_if.data; + assign scoreboard_ready_in[i] = opc_scoreboard_if.ready; + + // select writeback interface + VX_writeback_if opc_writeback_if(); + assign opc_writeback_if.valid = writeback_if.valid && (wb_opc == i); + assign opc_writeback_if.data = writeback_if.data; + + VX_opc_unit #( + .INSTANCE_ID (`SFORMATF(("%s-collector%0d", INSTANCE_ID, i))), + .NUM_BANKS (`NUM_GPR_BANKS), + .OUT_BUF (3) + ) opc_unit ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .perf_stalls (per_opc_perf_stalls[i]), + `endif + .writeback_if (opc_writeback_if), + .scoreboard_if(opc_scoreboard_if), + .operands_if (per_opc_operands_if[i]) + ); + end + + `ITF_TO_AOS (per_opc_operands, per_opc_operands_if, `NUM_OPCS, OUT_DATAW) + + VX_stream_arb #( + .NUM_INPUTS (`NUM_OPCS), + .NUM_OUTPUTS (1), + .DATAW (OUT_DATAW), + .ARBITER ("P"), + .STICKY (OUT_ARB_STICKY), + .OUT_BUF ((`NUM_OPCS > 1) ? 3 : 0) + ) output_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_opc_operands_valid), + .data_in (per_opc_operands_data), + .ready_in (per_opc_operands_ready), + .valid_out (operands_if.valid), + .data_out (operands_if.data), + .ready_out (operands_if.ready), + `UNUSED_PIN (sel_out) + ); + +`ifdef PERF_ENABLE + wire [PERF_CTR_BITS-1:0] perf_stalls_w; + VX_reduce_tree #( + .IN_W (PERF_CTR_BITS), + .N (`NUM_OPCS), + .OP ("+") + ) perf_stalls_reduce ( + .data_in (per_opc_perf_stalls), + .data_out (perf_stalls_w) + ); + `BUFFER(perf_stalls, perf_stalls_w); +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_pe_switch.sv b/designs/src/vortex/rtl/core/VX_pe_switch.sv new file mode 100644 index 0000000..b6c3aaa --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_pe_switch.sv @@ -0,0 +1,93 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_pe_switch import VX_gpu_pkg::*; #( + parameter PE_COUNT = 0, + parameter NUM_LANES = 0, + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0, + parameter `STRING ARBITER = "R", + parameter PE_SEL_BITS = `CLOG2(PE_COUNT) +) ( + input wire clk, + input wire reset, + input wire [`UP(PE_SEL_BITS)-1:0] pe_sel, + VX_execute_if.slave execute_in_if, + VX_result_if.master result_out_if, + VX_execute_if.master execute_out_if[PE_COUNT], + VX_result_if .slave result_in_if[PE_COUNT] +); + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam REQ_DATAW = UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + INST_ALU_BITS + $bits(op_args_t) + 1 + NUM_REGS_BITS + (3 * NUM_LANES * `XLEN) + PID_WIDTH + 1 + 1; + localparam RSP_DATAW = UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + NUM_REGS_BITS + 1 + NUM_LANES * `XLEN + PID_WIDTH + 1 + 1; + + wire [PE_COUNT-1:0] pe_req_valid; + wire [PE_COUNT-1:0][REQ_DATAW-1:0] pe_req_data; + wire [PE_COUNT-1:0] pe_req_ready; + + VX_stream_switch #( + .DATAW (REQ_DATAW), + .NUM_INPUTS (1), + .NUM_OUTPUTS (PE_COUNT), + .OUT_BUF (REQ_OUT_BUF) + ) req_switch ( + .clk (clk), + .reset (reset), + .sel_in (pe_sel), + .valid_in (execute_in_if.valid), + .ready_in (execute_in_if.ready), + .data_in (execute_in_if.data), + .data_out (pe_req_data), + .valid_out (pe_req_valid), + .ready_out (pe_req_ready) + ); + + for (genvar i = 0; i < PE_COUNT; ++i) begin : g_execute_out_if + assign execute_out_if[i].valid = pe_req_valid[i]; + assign execute_out_if[i].data = pe_req_data[i]; + assign pe_req_ready[i] = execute_out_if[i].ready; + end + + /////////////////////////////////////////////////////////////////////////// + + wire [PE_COUNT-1:0] pe_rsp_valid; + wire [PE_COUNT-1:0][RSP_DATAW-1:0] pe_rsp_data; + wire [PE_COUNT-1:0] pe_rsp_ready; + + for (genvar i = 0; i < PE_COUNT; ++i) begin : g_result_in_if + assign pe_rsp_valid[i] = result_in_if[i].valid; + assign pe_rsp_data[i] = result_in_if[i].data; + assign result_in_if[i].ready = pe_rsp_ready[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (PE_COUNT), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (pe_rsp_valid), + .ready_in (pe_rsp_ready), + .data_in (pe_rsp_data), + .data_out (result_out_if.data), + .valid_out (result_out_if.valid), + .ready_out (result_out_if.ready), + `UNUSED_PIN (sel_out) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_schedule.sv b/designs/src/vortex/rtl/core/VX_schedule.sv new file mode 100644 index 0000000..a89a0b4 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_schedule.sv @@ -0,0 +1,446 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_schedule import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output sched_perf_t sched_perf, +`endif + + // configuration + input base_dcrs_t base_dcrs, + + // inputsdecode_if + VX_warp_ctl_if.slave warp_ctl_if, + VX_branch_ctl_if.slave branch_ctl_if [`NUM_ALU_BLOCKS], + VX_decode_sched_if.slave decode_sched_if, + VX_issue_sched_if.slave issue_sched_if[`ISSUE_WIDTH], + VX_commit_sched_if.slave commit_sched_if, + + // outputs + VX_schedule_if.master schedule_if, +`ifdef GBAR_ENABLE + VX_gbar_bus_if.master gbar_bus_if, +`endif + VX_sched_csr_if.master sched_csr_if, + + // status + output wire busy +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (CORE_ID) + + reg [`NUM_WARPS-1:0] active_warps, active_warps_n; // updated when a warp is activated or disabled + reg [`NUM_WARPS-1:0] stalled_warps, stalled_warps_n; // set when branch/gpgpu instructions are issued + + reg [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks, thread_masks_n; + reg [`NUM_WARPS-1:0][PC_BITS-1:0] warp_pcs, warp_pcs_n; + + wire [NW_WIDTH-1:0] schedule_wid; + wire [`NUM_THREADS-1:0] schedule_tmask; + wire [PC_BITS-1:0] schedule_pc; + wire schedule_valid; + wire schedule_ready; + + // split/join + wire join_valid; + wire join_is_dvg; + wire join_is_else; + wire [NW_WIDTH-1:0] join_wid; + wire [`NUM_THREADS-1:0] join_tmask; + wire [PC_BITS-1:0] join_pc; + + reg [PERF_CTR_BITS-1:0] cycles; + + wire schedule_fire = schedule_valid && schedule_ready; + wire schedule_if_fire = schedule_if.valid && schedule_if.ready; + + // branch + wire [`NUM_ALU_BLOCKS-1:0] branch_valid; + wire [`NUM_ALU_BLOCKS-1:0][NW_WIDTH-1:0] branch_wid; + wire [`NUM_ALU_BLOCKS-1:0] branch_taken; + wire [`NUM_ALU_BLOCKS-1:0][PC_BITS-1:0] branch_dest; + for (genvar i = 0; i < `NUM_ALU_BLOCKS; ++i) begin : g_branch_init + assign branch_valid[i] = branch_ctl_if[i].valid; + assign branch_wid[i] = branch_ctl_if[i].wid; + assign branch_taken[i] = branch_ctl_if[i].taken; + assign branch_dest[i] = branch_ctl_if[i].dest; + end + + // barriers + reg [`NUM_BARRIERS-1:0][`NUM_WARPS-1:0] barrier_masks, barrier_masks_n; + reg [`NUM_BARRIERS-1:0][NW_WIDTH-1:0] barrier_ctrs, barrier_ctrs_n; + reg [`NUM_WARPS-1:0] barrier_stalls, barrier_stalls_n; + reg [`NUM_WARPS-1:0] curr_barrier_mask_p1; +`ifdef GBAR_ENABLE + reg gbar_req_valid; + reg [NB_WIDTH-1:0] gbar_req_id; + reg [NC_WIDTH-1:0] gbar_req_size_m1; +`endif + + // wspawn + wspawn_t wspawn; + reg [NW_WIDTH-1:0] wspawn_wid; + reg is_single_warp; + + wire [`CLOG2(`NUM_WARPS+1)-1:0] active_warps_cnt; + `POP_COUNT(active_warps_cnt, active_warps); + + always @(*) begin + active_warps_n = active_warps; + stalled_warps_n = stalled_warps; + thread_masks_n = thread_masks; + barrier_masks_n = barrier_masks; + barrier_ctrs_n = barrier_ctrs; + barrier_stalls_n= barrier_stalls; + warp_pcs_n = warp_pcs; + + // decode unlock + if (decode_sched_if.valid && decode_sched_if.unlock) begin + stalled_warps_n[decode_sched_if.wid] = 0; + end + + // CSR unlock + if (sched_csr_if.unlock_warp) begin + stalled_warps_n[sched_csr_if.unlock_wid] = 0; + end + + // wspawn handling + if (wspawn.valid && is_single_warp) begin + active_warps_n |= wspawn.wmask; + for (integer i = 0; i < `NUM_WARPS; ++i) begin + if (wspawn.wmask[i]) begin + thread_masks_n[i][0] = 1; + warp_pcs_n[i] = wspawn.pc; + end + end + stalled_warps_n[wspawn_wid] = 0; // unlock warp + end + + // TMC handling + if (warp_ctl_if.valid && warp_ctl_if.tmc.valid) begin + active_warps_n[warp_ctl_if.wid] = (warp_ctl_if.tmc.tmask != 0); + thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.tmc.tmask; + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + + // split handling + if (warp_ctl_if.valid && warp_ctl_if.split.valid) begin + if (warp_ctl_if.split.is_dvg) begin + thread_masks_n[warp_ctl_if.wid] = warp_ctl_if.split.then_tmask; + end + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + + // join handling + if (join_valid) begin + if (join_is_dvg) begin + if (join_is_else) begin + warp_pcs_n[join_wid] = join_pc; + end + thread_masks_n[join_wid] = join_tmask; + end + stalled_warps_n[join_wid] = 0; // unlock warp + end + + // barrier handling + curr_barrier_mask_p1 = barrier_masks[warp_ctl_if.barrier.id]; + curr_barrier_mask_p1[warp_ctl_if.wid] = 1; + if (warp_ctl_if.valid && warp_ctl_if.barrier.valid) begin + if (~warp_ctl_if.barrier.is_noop) begin + if (~warp_ctl_if.barrier.is_global + && (barrier_ctrs[warp_ctl_if.barrier.id] == NW_WIDTH'(warp_ctl_if.barrier.size_m1))) begin + barrier_ctrs_n[warp_ctl_if.barrier.id] = '0; // reset barrier counter + barrier_masks_n[warp_ctl_if.barrier.id] = '0; // reset barrier mask + stalled_warps_n &= ~barrier_masks[warp_ctl_if.barrier.id]; // unlock warps + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end else begin + barrier_ctrs_n[warp_ctl_if.barrier.id] = barrier_ctrs[warp_ctl_if.barrier.id] + NW_WIDTH'(1); + barrier_masks_n[warp_ctl_if.barrier.id] = curr_barrier_mask_p1; + end + end else begin + stalled_warps_n[warp_ctl_if.wid] = 0; // unlock warp + end + end + + `ifdef GBAR_ENABLE + if (gbar_bus_if.rsp_valid && (gbar_req_id == gbar_bus_if.rsp_data.id)) begin + barrier_ctrs_n[warp_ctl_if.barrier.id] = '0; // reset barrier counter + barrier_masks_n[gbar_bus_if.rsp_data.id] = '0; // reset barrier mask + stalled_warps_n = '0; // unlock all warps + end + `endif + + // Branch handling + for (integer i = 0; i < `NUM_ALU_BLOCKS; ++i) begin + if (branch_valid[i]) begin + if (branch_taken[i]) begin + warp_pcs_n[branch_wid[i]] = branch_dest[i]; + end + stalled_warps_n[branch_wid[i]] = 0; // unlock warp + end + end + + // stall the warp until decode stage + if (schedule_fire) begin + stalled_warps_n[schedule_wid] = 1; + end + + // advance PC + if (schedule_if_fire) begin + warp_pcs_n[schedule_if.data.wid] = schedule_if.data.PC + from_fullPC(`XLEN'(4)); + end + end + + `UNUSED_VAR (base_dcrs) + + always @(posedge clk) begin + if (reset) begin + barrier_masks <= '0; + barrier_ctrs <= '0; + `ifdef GBAR_ENABLE + gbar_req_valid <= 0; + `endif + stalled_warps <= '0; + warp_pcs <= '0; + active_warps <= '0; + thread_masks <= '0; + barrier_stalls <= '0; + cycles <= '0; + wspawn.valid <= 0; + + // activate first warp + warp_pcs[0] <= from_fullPC(base_dcrs.startup_addr); + active_warps[0] <= 1; + thread_masks[0][0] <= 1; + is_single_warp <= 1; + end else begin + active_warps <= active_warps_n; + stalled_warps <= stalled_warps_n; + thread_masks <= thread_masks_n; + warp_pcs <= warp_pcs_n; + barrier_masks <= barrier_masks_n; + barrier_ctrs <= barrier_ctrs_n; + barrier_stalls <= barrier_stalls_n; + is_single_warp <= (active_warps_cnt == $bits(active_warps_cnt)'(1)); + + // wspawn handling + if (warp_ctl_if.valid && warp_ctl_if.wspawn.valid) begin + wspawn.valid <= 1; + wspawn.wmask <= warp_ctl_if.wspawn.wmask; + wspawn.pc <= warp_ctl_if.wspawn.pc; + wspawn_wid <= warp_ctl_if.wid; + end + if (wspawn.valid && is_single_warp) begin + wspawn.valid <= 0; + end + + // global barrier scheduling + `ifdef GBAR_ENABLE + if (warp_ctl_if.valid && warp_ctl_if.barrier.valid + && warp_ctl_if.barrier.is_global + && !warp_ctl_if.barrier.is_noop + && (curr_barrier_mask_p1 == active_warps)) begin + gbar_req_valid <= 1; + gbar_req_id <= warp_ctl_if.barrier.id; + gbar_req_size_m1 <= NC_WIDTH'(warp_ctl_if.barrier.size_m1); + end + if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin + gbar_req_valid <= 0; + end + `endif + + if (busy) begin + cycles <= cycles + 1; + end + end + end + + // barrier handling + +`ifdef GBAR_ENABLE + assign gbar_bus_if.req_valid = gbar_req_valid; + assign gbar_bus_if.req_data.id = gbar_req_id; + assign gbar_bus_if.req_data.size_m1 = gbar_req_size_m1; + assign gbar_bus_if.req_data.core_id = NC_WIDTH'(CORE_ID % `NUM_CORES); +`endif + + // split/join handling + + VX_split_join #( + .INSTANCE_ID (`SFORMATF(("%s-splitjoin", INSTANCE_ID))), + .OUT_REG (1) + ) split_join ( + .clk (clk), + .reset (reset), + .valid (warp_ctl_if.valid), + .wid (warp_ctl_if.wid), + .split (warp_ctl_if.split), + .sjoin (warp_ctl_if.sjoin), + .join_valid (join_valid), + .join_is_dvg(join_is_dvg), + .join_is_else(join_is_else), + .join_wid (join_wid), + .join_tmask (join_tmask), + .join_pc (join_pc), + .stack_wid (warp_ctl_if.dvstack_wid), + .stack_ptr (warp_ctl_if.dvstack_ptr) + ); + + // schedule the next ready warp + + wire [`NUM_WARPS-1:0] ready_warps = active_warps & ~stalled_warps; + + VX_priority_encoder #( + .N (`NUM_WARPS) + ) wid_select ( + .data_in (ready_warps), + .index_out (schedule_wid), + .valid_out (schedule_valid), + `UNUSED_PIN (onehot_out) + ); + + wire [`NUM_WARPS-1:0][(`NUM_THREADS + PC_BITS)-1:0] schedule_data; + for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_schedule_data + assign schedule_data[i] = {thread_masks[i], warp_pcs[i]}; + end + + assign {schedule_tmask, schedule_pc} = { + schedule_data[schedule_wid][(`NUM_THREADS + PC_BITS)-1:(`NUM_THREADS + PC_BITS)-4], + schedule_data[schedule_wid][(`NUM_THREADS + PC_BITS)-5:0] + }; + + wire [UUID_WIDTH-1:0] instr_uuid; +`ifdef UUID_ENABLE + VX_uuid_gen #( + .CORE_ID (CORE_ID) + ) uuid_gen ( + .clk (clk), + .reset (reset), + .incr (schedule_fire), + .wid (schedule_wid), + .uuid (instr_uuid) + ); +`else + assign instr_uuid = '0; +`endif + + VX_elastic_buffer #( + .DATAW (`NUM_THREADS + PC_BITS + NW_WIDTH + UUID_WIDTH), + .SIZE (2), // need to buffer out ready_in + .OUT_REG (1) // should be registered for BRAM acces in fetch unit + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (schedule_valid), + .ready_in (schedule_ready), + .data_in ({schedule_tmask, schedule_pc, schedule_wid, instr_uuid}), + .data_out ({schedule_if.data.tmask, schedule_if.data.PC, schedule_if.data.wid, schedule_if.data.uuid}), + .valid_out (schedule_if.valid), + .ready_out (schedule_if.ready) + ); + + // Track pending instructions per warp + + wire [`NUM_WARPS-1:0] pending_warp_empty; + wire [`NUM_WARPS-1:0] pending_warp_alm_empty; + + for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_pending_sizes + + localparam isw = wid_to_isw(i); + localparam wis = wid_to_wis(i); + + VX_pending_size #( + .SIZE (4096), + .ALM_EMPTY (1) + ) counter ( + .clk (clk), + .reset (reset), + .incr (issue_sched_if[isw].valid && (issue_sched_if[isw].wis == wis)), + .decr (commit_sched_if.committed_warps[i]), + .empty (pending_warp_empty[i]), + .alm_empty (pending_warp_alm_empty[i]), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + end + + assign sched_csr_if.alm_empty = pending_warp_alm_empty[sched_csr_if.alm_empty_wid]; + + wire no_pending_instr = (& pending_warp_empty); + + `BUFFER_EX(busy, (active_warps != 0 || ~no_pending_instr), 1'b1, 1, 1); + + // export CSRs + assign sched_csr_if.cycles = cycles; + assign sched_csr_if.active_warps = active_warps; + assign sched_csr_if.thread_masks = thread_masks; + + // timeout handling + reg [31:0] timeout_ctr; + reg timeout_enable; + always @(posedge clk) begin + if (reset) begin + timeout_ctr <= '0; + timeout_enable <= 0; + end else begin + if (decode_sched_if.valid && decode_sched_if.unlock) begin + timeout_enable <= 1; + end + if (timeout_enable && active_warps !=0 && active_warps == stalled_warps) begin + timeout_ctr <= timeout_ctr + 1; + end else if (active_warps == 0 || active_warps != stalled_warps) begin + timeout_ctr <= '0; + end + end + end + `RUNTIME_ASSERT(timeout_ctr < STALL_TIMEOUT, ("%t: *** %s timeout: stalled_warps=%b", $time, INSTANCE_ID, stalled_warps)) + +`ifdef PERF_ENABLE + reg [PERF_CTR_BITS-1:0] perf_sched_idles; + reg [PERF_CTR_BITS-1:0] perf_sched_stalls; + + wire schedule_idle = ~schedule_valid; + wire schedule_stall = schedule_if.valid && ~schedule_if.ready; + + always @(posedge clk) begin + if (reset) begin + perf_sched_idles <= '0; + perf_sched_stalls <= '0; + end else begin + perf_sched_idles <= perf_sched_idles + PERF_CTR_BITS'(schedule_idle); + perf_sched_stalls <= perf_sched_stalls + PERF_CTR_BITS'(schedule_stall); + end + end + + assign sched_perf.idles = perf_sched_idles; + assign sched_perf.stalls = perf_sched_stalls; +`endif + +`ifdef DBG_TRACE_PIPELINE + always @(posedge clk) begin + if (schedule_fire) begin + `TRACE(1, ("%t: %s: wid=%0d, PC=0x%0h, tmask=%b (#%0d)\n", $time, INSTANCE_ID, schedule_wid, to_fullPC(schedule_pc), schedule_tmask, instr_uuid)) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_scoreboard.sv b/designs/src/vortex/rtl/core/VX_scoreboard.sv new file mode 100644 index 0000000..251cc25 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_scoreboard.sv @@ -0,0 +1,288 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_scoreboard import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter ISSUE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + output reg [PERF_CTR_BITS-1:0] perf_stalls, + output reg [NUM_EX_UNITS-1:0][PERF_CTR_BITS-1:0] perf_units_uses, + output reg [NUM_SFU_UNITS-1:0][PERF_CTR_BITS-1:0] perf_sfu_uses, +`endif + + VX_writeback_if.slave writeback_if, + VX_ibuffer_if.slave ibuffer_if [PER_ISSUE_WARPS], + VX_scoreboard_if.master scoreboard_if +); + `UNUSED_SPARAM (INSTANCE_ID) + `UNUSED_PARAM (ISSUE_ID) + `UNUSED_VAR (writeback_if.data.sop) + + localparam NUM_OPDS = NUM_SRC_OPDS + 1; + localparam IN_DATAW = $bits(ibuffer_t); + + VX_ibuffer_if staging_if [PER_ISSUE_WARPS](); + wire [PER_ISSUE_WARPS-1:0] operands_ready; + +`ifdef PERF_ENABLE + reg [PER_ISSUE_WARPS-1:0][NUM_EX_UNITS-1:0] perf_inuse_units_per_cycle; + wire [NUM_EX_UNITS-1:0] perf_units_per_cycle, perf_units_per_cycle_r; + + reg [PER_ISSUE_WARPS-1:0][NUM_SFU_UNITS-1:0] perf_inuse_sfu_per_cycle; + wire [NUM_SFU_UNITS-1:0] perf_sfu_per_cycle, perf_sfu_per_cycle_r; + + VX_reduce_tree #( + .IN_W (NUM_EX_UNITS), + .N (PER_ISSUE_WARPS), + .OP ("|") + ) perf_units_reduce ( + .data_in (perf_inuse_units_per_cycle), + .data_out (perf_units_per_cycle) + ); + + VX_reduce_tree #( + .IN_W (NUM_SFU_UNITS), + .N (PER_ISSUE_WARPS), + .OP ("|") + ) perf_sfu_reduce ( + .data_in (perf_inuse_sfu_per_cycle), + .data_out (perf_sfu_per_cycle) + ); + + `BUFFER_EX(perf_units_per_cycle_r, perf_units_per_cycle, 1'b1, 0, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT)); + `BUFFER_EX(perf_sfu_per_cycle_r, perf_sfu_per_cycle, 1'b1, 0, `CDIV(PER_ISSUE_WARPS, `MAX_FANOUT)); + + wire [PER_ISSUE_WARPS-1:0] stg_valid_in; + for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_stg_valid_in + assign stg_valid_in[w] = staging_if[w].valid; + end + + wire perf_stall_per_cycle = (|stg_valid_in) && ~(|(stg_valid_in & operands_ready)); + + always @(posedge clk) begin : g_perf_stalls + if (reset) begin + perf_stalls <= '0; + end else begin + perf_stalls <= perf_stalls + PERF_CTR_BITS'(perf_stall_per_cycle); + end + end + + for (genvar i = 0; i < NUM_EX_UNITS; ++i) begin : g_perf_units_uses + always @(posedge clk) begin + if (reset) begin + perf_units_uses[i] <= '0; + end else begin + perf_units_uses[i] <= perf_units_uses[i] + PERF_CTR_BITS'(perf_units_per_cycle_r[i]); + end + end + end + + for (genvar i = 0; i < NUM_SFU_UNITS; ++i) begin : g_perf_sfu_uses + always @(posedge clk) begin + if (reset) begin + perf_sfu_uses[i] <= '0; + end else begin + perf_sfu_uses[i] <= perf_sfu_uses[i] + PERF_CTR_BITS'(perf_sfu_per_cycle_r[i]); + end + end + end +`endif + + for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_stanging_bufs + VX_pipe_buffer #( + .DATAW (IN_DATAW) + ) stanging_buf ( + .clk (clk), + .reset (reset), + .valid_in (ibuffer_if[w].valid), + .data_in (ibuffer_if[w].data), + .ready_in (ibuffer_if[w].ready), + .valid_out(staging_if[w].valid), + .data_out (staging_if[w].data), + .ready_out(staging_if[w].ready) + ); + end + + for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_scoreboard + reg [NUM_REGS-1:0] inuse_regs, inuse_regs_n; + wire [NUM_OPDS-1:0] operands_busy; + + wire ibuffer_fire = ibuffer_if[w].valid && ibuffer_if[w].ready; + wire staging_fire = staging_if[w].valid && staging_if[w].ready; + + wire writeback_fire = writeback_if.valid + && (writeback_if.data.wis == ISSUE_WIS_W'(w)) + && writeback_if.data.eop; + + wire [NUM_OPDS-1:0] [NUM_REGS_BITS-1:0] ibf_opds, stg_opds; + assign ibf_opds = {ibuffer_if[w].data.rs3, ibuffer_if[w].data.rs2, ibuffer_if[w].data.rs1, ibuffer_if[w].data.rd}; + assign stg_opds = {staging_if[w].data.rs3, staging_if[w].data.rs2, staging_if[w].data.rs1, staging_if[w].data.rd}; + + wire [NUM_OPDS-1:0] ibf_used_rs = {ibuffer_if[w].data.used_rs, ibuffer_if[w].data.wb}; + wire [NUM_OPDS-1:0] stg_used_rs = {staging_if[w].data.used_rs, staging_if[w].data.wb}; + + wire [NUM_OPDS-1:0][REG_TYPES-1:0][RV_REGS-1:0] ibf_opd_mask, stg_opd_mask; + + for (genvar i = 0; i < NUM_OPDS; ++i) begin : g_opd_masks + for (genvar j = 0; j < REG_TYPES; ++j) begin : g_j + assign ibf_opd_mask[i][j] = (1 << get_reg_idx(ibf_opds[i])) & {RV_REGS{ibf_used_rs[i] && get_reg_type(ibf_opds[i]) == j}}; + assign stg_opd_mask[i][j] = (1 << get_reg_idx(stg_opds[i])) & {RV_REGS{stg_used_rs[i] && get_reg_type(stg_opds[i]) == j}}; + end + end + + always @(*) begin + inuse_regs_n = inuse_regs; + if (writeback_fire) begin + inuse_regs_n[writeback_if.data.rd] = 0; // release rd + end + if (staging_fire && staging_if[w].data.wb) begin + inuse_regs_n |= stg_opd_mask[0]; // reserve rd + end + end + + wire [REG_TYPES-1:0][RV_REGS-1:0] in_use_mask; + for (genvar i = 0; i < REG_TYPES; ++i) begin : g_in_use_mask + wire [RV_REGS-1:0] ibf_reg_mask = ibf_opd_mask[0][i] | ibf_opd_mask[1][i] | ibf_opd_mask[2][i] | ibf_opd_mask[3][i]; + wire [RV_REGS-1:0] stg_reg_mask = stg_opd_mask[0][i] | stg_opd_mask[1][i] | stg_opd_mask[2][i] | stg_opd_mask[3][i]; + wire [RV_REGS-1:0] regs_mask = ibuffer_fire ? ibf_reg_mask : stg_reg_mask; + assign in_use_mask[i] = inuse_regs_n[i * RV_REGS +: RV_REGS] & regs_mask; + end + + wire [REG_TYPES-1:0] regs_busy; + for (genvar i = 0; i < REG_TYPES; ++i) begin : g_regs_busy + assign regs_busy[i] = (in_use_mask[i] != 0); + end + + for (genvar i = 0; i < NUM_OPDS; ++i) begin : g_operands_busy + wire [REG_TYPE_BITS-1:0] rtype = get_reg_type(stg_opds[i]); + assign operands_busy[i] = (in_use_mask[rtype] & stg_opd_mask[i][rtype]) != 0; + end + + reg operands_ready_r; + + always @(posedge clk) begin + if (reset) begin + inuse_regs <= '0; + end else begin + inuse_regs <= inuse_regs_n; + end + operands_ready_r <= ~(| regs_busy); + end + + assign operands_ready[w] = operands_ready_r; + + `ifdef PERF_ENABLE + reg [NUM_REGS-1:0][EX_WIDTH-1:0] inuse_units; + reg [NUM_REGS-1:0][SFU_WIDTH-1:0] inuse_sfu; + + always @(*) begin + perf_inuse_units_per_cycle[w] = '0; + perf_inuse_sfu_per_cycle[w] = '0; + for (integer i = 0; i < NUM_OPDS; ++i) begin + if (staging_if[w].valid && operands_busy[i]) begin + perf_inuse_units_per_cycle[w][inuse_units[stg_opds[i]]] = 1; + if (inuse_units[stg_opds[i]] == EX_SFU) begin + perf_inuse_sfu_per_cycle[w][inuse_sfu[stg_opds[i]]] = 1; + end + end + end + end + always @(posedge clk) begin + if (staging_fire && staging_if[w].data.wb) begin + inuse_units[staging_if[w].data.rd] <= staging_if[w].data.ex_type; + if (staging_if[w].data.ex_type == EX_SFU) begin + inuse_sfu[staging_if[w].data.rd] <= op_to_sfu_type(staging_if[w].data.op_type); + end + end + end + `endif + + `ifdef SIMULATION + reg [31:0] timeout_ctr; + + always @(posedge clk) begin + if (reset) begin + timeout_ctr <= '0; + end else begin + if (staging_if[w].valid && ~staging_if[w].ready) begin + `ifdef DBG_TRACE_PIPELINE + `TRACE(4, ("%t: *** %s-stall: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)\n", + $time, INSTANCE_ID, w, to_fullPC(staging_if[w].data.PC), staging_if[w].data.tmask, timeout_ctr, + operands_busy, staging_if[w].data.uuid)) + `endif + timeout_ctr <= timeout_ctr + 1; + end else if (ibuffer_fire) begin + timeout_ctr <= '0; + end + end + end + + `RUNTIME_ASSERT((timeout_ctr < STALL_TIMEOUT), + ("%t: *** %s timeout: wid=%0d, PC=0x%0h, tmask=%b, cycles=%0d, inuse=%b (#%0d)", + $time, INSTANCE_ID, w, to_fullPC(staging_if[w].data.PC), staging_if[w].data.tmask, timeout_ctr, + operands_busy, staging_if[w].data.uuid)) + + `RUNTIME_ASSERT(~writeback_fire || inuse_regs[writeback_if.data.rd] != 0, + ("%t: *** %s invalid writeback register: wid=%0d, PC=0x%0h, tmask=%b, rd=%0d (#%0d)", + $time, INSTANCE_ID, w, to_fullPC(writeback_if.data.PC), writeback_if.data.tmask, writeback_if.data.rd, writeback_if.data.uuid)) + `endif + + end + + wire [PER_ISSUE_WARPS-1:0] arb_valid_in; + wire [PER_ISSUE_WARPS-1:0][IN_DATAW-1:0] arb_data_in; + wire [PER_ISSUE_WARPS-1:0] arb_ready_in; + + for (genvar w = 0; w < PER_ISSUE_WARPS; ++w) begin : g_arb_data_in + assign arb_valid_in[w] = staging_if[w].valid && operands_ready[w]; + assign arb_data_in[w] = staging_if[w].data; + assign staging_if[w].ready = arb_ready_in[w] && operands_ready[w]; + end + + VX_stream_arb #( + .NUM_INPUTS (PER_ISSUE_WARPS), + .DATAW (IN_DATAW), + .ARBITER ("C"), + .OUT_BUF (3) + ) out_arb ( + .clk (clk), + .reset (reset), + .valid_in (arb_valid_in), + .ready_in (arb_ready_in), + .data_in (arb_data_in), + .data_out ({ + scoreboard_if.data.uuid, + scoreboard_if.data.tmask, + scoreboard_if.data.PC, + scoreboard_if.data.ex_type, + scoreboard_if.data.op_type, + scoreboard_if.data.op_args, + scoreboard_if.data.wb, + scoreboard_if.data.used_rs, + scoreboard_if.data.rd, + scoreboard_if.data.rs1, + scoreboard_if.data.rs2, + scoreboard_if.data.rs3 + }), + .valid_out (scoreboard_if.valid), + .ready_out (scoreboard_if.ready), + .sel_out (scoreboard_if.data.wis) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_sfu_unit.sv b/designs/src/vortex/rtl/core/VX_sfu_unit.sv new file mode 100644 index 0000000..6e43519 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_sfu_unit.sv @@ -0,0 +1,150 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_sfu_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + +`ifdef PERF_ENABLE + input sysmem_perf_t sysmem_perf, + input pipeline_perf_t pipeline_perf, +`endif + + input base_dcrs_t base_dcrs, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + +`ifdef EXT_F_ENABLE + VX_fpu_csr_if.slave fpu_csr_if [`NUM_FPU_BLOCKS], +`endif + + VX_commit_csr_if.slave commit_csr_if, + VX_sched_csr_if.slave sched_csr_if, + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH], + VX_warp_ctl_if.master warp_ctl_if +); + `UNUSED_SPARAM (INSTANCE_ID) + localparam BLOCK_SIZE = 1; + localparam NUM_LANES = `NUM_SFU_LANES; + localparam PE_COUNT = 2; + localparam PE_SEL_BITS = `CLOG2(PE_COUNT); + localparam PE_IDX_WCTL = 0; + localparam PE_IDX_CSRS = 1; + + VX_execute_if #( + .data_t (sfu_exe_t) + ) per_block_execute_if[BLOCK_SIZE](); + + VX_result_if #( + .data_t (sfu_res_t) + ) per_block_result_if[BLOCK_SIZE](); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (3) + ) dispatch_unit ( + .clk (clk), + .reset (reset), + .dispatch_if(dispatch_if), + .execute_if (per_block_execute_if) + ); + + VX_execute_if #( + .data_t (sfu_exe_t) + ) pe_execute_if[PE_COUNT](); + + VX_result_if#( + .data_t (sfu_res_t) + ) pe_result_if[PE_COUNT](); + + reg [PE_SEL_BITS-1:0] pe_select; + always @(*) begin + pe_select = PE_IDX_WCTL; + if (inst_sfu_is_csr(per_block_execute_if[0].data.op_type)) begin + pe_select = PE_IDX_CSRS; + end + end + + VX_pe_switch #( + .PE_COUNT (PE_COUNT), + .NUM_LANES (NUM_LANES), + .ARBITER ("R"), + .REQ_OUT_BUF(0), + .RSP_OUT_BUF(3) + ) pe_switch ( + .clk (clk), + .reset (reset), + .pe_sel (pe_select), + .execute_in_if (per_block_execute_if[0]), + .result_out_if (per_block_result_if[0]), + .execute_out_if (pe_execute_if), + .result_in_if (pe_result_if) + ); + + VX_wctl_unit #( + .INSTANCE_ID (`SFORMATF(("%s-wctl", INSTANCE_ID))), + .NUM_LANES (NUM_LANES) + ) wctl_unit ( + .clk (clk), + .reset (reset), + .execute_if (pe_execute_if[PE_IDX_WCTL]), + .warp_ctl_if(warp_ctl_if), + .result_if (pe_result_if[PE_IDX_WCTL]) + ); + + VX_csr_unit #( + .INSTANCE_ID (`SFORMATF(("%s-csr", INSTANCE_ID))), + .CORE_ID (CORE_ID), + .NUM_LANES (NUM_LANES) + ) csr_unit ( + .clk (clk), + .reset (reset), + + .base_dcrs (base_dcrs), + .execute_if (pe_execute_if[PE_IDX_CSRS]), + + `ifdef PERF_ENABLE + .sysmem_perf (sysmem_perf), + .pipeline_perf (pipeline_perf), + `endif + + `ifdef EXT_F_ENABLE + .fpu_csr_if (fpu_csr_if), + `endif + + .sched_csr_if (sched_csr_if), + .commit_csr_if (commit_csr_if), + .result_if (pe_result_if[PE_IDX_CSRS]) + ); + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (3) + ) gather_unit ( + .clk (clk), + .reset (reset), + .result_if (per_block_result_if), + .commit_if (commit_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_split_join.sv b/designs/src/vortex/rtl/core/VX_split_join.sv new file mode 100644 index 0000000..f1e7db8 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_split_join.sv @@ -0,0 +1,106 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_split_join import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + input wire valid, + input wire [NW_WIDTH-1:0] wid, + input split_t split, + input join_t sjoin, + input wire [NW_WIDTH-1:0] stack_wid, + output wire join_valid, + output wire join_is_dvg, + output wire join_is_else, + output wire [NW_WIDTH-1:0] join_wid, + output wire [`NUM_THREADS-1:0] join_tmask, + output wire [PC_BITS-1:0] join_pc, + output wire [DV_STACK_SIZEW-1:0] stack_ptr +); + `UNUSED_SPARAM (INSTANCE_ID) + + wire split_valid = valid && split.valid; + wire sjoin_valid = valid && sjoin.valid; + + if (NT_BITS != 0) begin : g_enable + wire [`NUM_WARPS-1:0][DV_STACK_SIZEW-1:0] ipdom_wr_ptr; + wire [`NUM_THREADS-1:0] ipdom_tmask; + wire [PC_BITS-1:0] ipdom_pc; + wire ipdom_idx; + + wire [(`NUM_THREADS + PC_BITS)-1:0] ipdom_d0 = {split.then_tmask | split.else_tmask, PC_BITS'(0)}; + wire [(`NUM_THREADS + PC_BITS)-1:0] ipdom_d1 = {split.else_tmask, split.next_pc}; + + wire sjoin_is_dvg = (sjoin.stack_ptr != ipdom_wr_ptr[wid]); + + wire ipdom_push = split_valid && split.is_dvg; + wire ipdom_pop = sjoin_valid && sjoin_is_dvg; + + VX_ipdom_stack #( + .WIDTH (`NUM_THREADS + PC_BITS), + .DEPTH (DV_STACK_SIZE) + ) ipdom_stack ( + .clk (clk), + .reset (reset), + .wid (wid), + .d0 (ipdom_d0), + .d1 (ipdom_d1), + .push (ipdom_push), + .pop (ipdom_pop), + .rd_ptr(sjoin.stack_ptr), + .q_val ({ipdom_tmask, ipdom_pc}), + .q_idx (ipdom_idx), + .wr_ptr(ipdom_wr_ptr), + `UNUSED_PIN (empty), + `UNUSED_PIN (full) + ); + + VX_pipe_register #( + .DATAW (1 + NW_WIDTH + 1 + 1 + `NUM_THREADS + PC_BITS), + .RESETW (1), + .DEPTH (OUT_REG) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({sjoin_valid, wid, sjoin_is_dvg, ~ipdom_idx, ipdom_tmask, ipdom_pc}), + .data_out ({join_valid, join_wid, join_is_dvg, join_is_else, join_tmask, join_pc}) + ); + + assign stack_ptr = ipdom_wr_ptr[stack_wid]; + + end else begin : g_disable + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (split) + `UNUSED_VAR (sjoin) + `UNUSED_VAR (wid) + `UNUSED_VAR (stack_wid) + `UNUSED_VAR (split_valid) + assign join_valid = sjoin_valid; + assign join_wid = wid; + assign join_is_dvg = 0; + assign join_is_else = 0; + assign join_tmask = 1'b1; + assign join_pc = '0; + assign stack_ptr = '0; + + end + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_uop_sequencer.sv b/designs/src/vortex/rtl/core/VX_uop_sequencer.sv new file mode 100644 index 0000000..57ef237 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_uop_sequencer.sv @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_uop_sequencer import +`ifdef EXT_TCU_ENABLE + VX_tcu_pkg::*, +`endif + VX_gpu_pkg::*; ( + input clk, + input reset, + + VX_ibuffer_if.slave input_if, + VX_ibuffer_if.master output_if +); + ibuffer_t uop_data; + + wire is_uop_input; + wire uop_start = input_if.valid && is_uop_input; + wire uop_next = output_if.ready; + wire uop_done; + +`ifdef EXT_TCU_ENABLE + + assign is_uop_input = (input_if.data.ex_type == EX_TCU && input_if.data.op_type == INST_TCU_WMMA); + + VX_tcu_uops tcu_uops ( + .clk (clk), + .reset (reset), + .ibuf_in (input_if.data), + .ibuf_out(uop_data), + .start (uop_start), + .next (uop_next), + .done (uop_done) + ); + +`else + + assign is_uop_input = 0; + assign uop_done = 0; + assign uop_data = '0; + +`endif + + reg uop_active; + + always_ff @(posedge clk) begin + if (reset) begin + uop_active <= 0; + end else begin + if (uop_active) begin + if (uop_next && uop_done) begin + uop_active <= 0; + end + end + else if (uop_start) begin + uop_active <= 1; + end + end + end + + // output assignments + wire uop_hold = ~uop_active && is_uop_input; // hold transition cycles to uop_active + assign output_if.valid = uop_active ? 1'b1 : (input_if.valid && ~uop_hold); + assign output_if.data = uop_active ? uop_data : input_if.data; + assign input_if.ready = uop_active ? (output_if.ready && uop_done) : (output_if.ready && ~uop_hold); + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_uuid_gen.sv b/designs/src/vortex/rtl/core/VX_uuid_gen.sv new file mode 100644 index 0000000..1e9ffb2 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_uuid_gen.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_uuid_gen import VX_gpu_pkg::*; #( + parameter CORE_ID = 0 +) ( + input wire clk, + input wire reset, + input wire incr, + input wire [NW_WIDTH-1:0] wid, + output wire [UUID_WIDTH-1:0] uuid +); + localparam GNW_WIDTH = UUID_WIDTH - 32; + reg [31:0] uuid_cntrs [0:`NUM_WARPS-1]; + reg [`NUM_WARPS-1:0] has_uuid_cntrs; + + always @(posedge clk) begin + if (reset) begin + has_uuid_cntrs <= '0; + end else if (incr) begin + has_uuid_cntrs[wid] <= 1; + end + if (incr) begin + uuid_cntrs[wid] <= has_uuid_cntrs[wid] ? (uuid_cntrs[wid] + 1) : 1; + end + end + + wire [GNW_WIDTH-1:0] g_wid = (GNW_WIDTH'(CORE_ID) << NW_BITS) + GNW_WIDTH'(wid); + assign uuid = {g_wid, (has_uuid_cntrs[wid] ? uuid_cntrs[wid] : 0)}; + +endmodule diff --git a/designs/src/vortex/rtl/core/VX_wctl_unit.sv b/designs/src/vortex/rtl/core/VX_wctl_unit.sv new file mode 100644 index 0000000..80131b2 --- /dev/null +++ b/designs/src/vortex/rtl/core/VX_wctl_unit.sv @@ -0,0 +1,190 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_wctl_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + parameter NUM_LANES = 1 +) ( + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_warp_ctl_if.master warp_ctl_if, + VX_result_if.master result_if +); + `UNUSED_SPARAM (INSTANCE_ID) + localparam LANE_BITS = `CLOG2(NUM_LANES); + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam WCTL_WIDTH = $bits(tmc_t) + $bits(wspawn_t) + $bits(split_t) + $bits(join_t) + $bits(barrier_t); + localparam DATAW = UUID_WIDTH + NW_WIDTH+ NUM_LANES + PC_BITS + NUM_REGS_BITS + 1 + PID_WIDTH + 1 + 1 + DV_STACK_SIZEW; + + `UNUSED_VAR (execute_if.data.rs3_data) + + tmc_t tmc; + wspawn_t wspawn; + split_t split; + join_t sjoin; + barrier_t barrier; + + wire is_wspawn = (execute_if.data.op_type == INST_SFU_WSPAWN); + wire is_tmc = (execute_if.data.op_type == INST_SFU_TMC); + wire is_pred = (execute_if.data.op_type == INST_SFU_PRED); + wire is_split = (execute_if.data.op_type == INST_SFU_SPLIT); + wire is_join = (execute_if.data.op_type == INST_SFU_JOIN); + wire is_bar = (execute_if.data.op_type == INST_SFU_BAR); + + wire [`UP(LANE_BITS)-1:0] last_tid; + if (LANE_BITS != 0) begin : g_last_tid + VX_priority_encoder #( + .N (NUM_LANES), + .REVERSE (1) + ) last_tid_select ( + .data_in (execute_if.data.tmask), + .index_out (last_tid), + `UNUSED_PIN (onehot_out), + `UNUSED_PIN (valid_out) + ); + end else begin : g_no_tid + assign last_tid = 0; + end + + wire [`XLEN-1:0] rs1_data = execute_if.data.rs1_data[last_tid]; + wire [`XLEN-1:0] rs2_data = execute_if.data.rs2_data[last_tid]; + `UNUSED_VAR (rs1_data) + + wire not_pred = execute_if.data.op_args.wctl.is_neg; + + wire [NUM_LANES-1:0] taken; + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_taken + assign taken[i] = (execute_if.data.rs1_data[i][0] ^ not_pred); + end + + logic [`NUM_THREADS-1:0] then_tmask; + logic [`NUM_THREADS-1:0] else_tmask; + + if (PID_BITS != 0) begin : g_pid + reg [`NUM_WARPS-1:0][2*`NUM_THREADS-1:0] tmask_table; + + wire [2*`NUM_THREADS-1:0] tmask_r = tmask_table[execute_if.data.wid]; + + always @(*) begin + {else_tmask, then_tmask} = execute_if.data.sop ? '0 : tmask_r; + then_tmask[execute_if.data.pid * NUM_LANES +: NUM_LANES] = taken & execute_if.data.tmask; + else_tmask[execute_if.data.pid * NUM_LANES +: NUM_LANES] = ~taken & execute_if.data.tmask; + end + + always @(posedge clk) begin + if (execute_if.valid) begin + tmask_table[execute_if.data.wid] <= {else_tmask, then_tmask}; + end + end + end else begin : g_no_pid + assign then_tmask = taken & execute_if.data.tmask; + assign else_tmask = ~taken & execute_if.data.tmask; + end + + wire has_then = (then_tmask != 0); + wire has_else = (else_tmask != 0); + + // tmc / pred + + wire [`NUM_THREADS-1:0] pred_mask = has_then ? then_tmask : rs2_data[`NUM_THREADS-1:0]; + assign tmc.valid = (is_tmc || is_pred); + assign tmc.tmask = is_pred ? pred_mask : rs1_data[`NUM_THREADS-1:0]; + + // split + + wire [`CLOG2(`NUM_THREADS+1)-1:0] then_tmask_cnt, else_tmask_cnt; + `POP_COUNT(then_tmask_cnt, then_tmask); + `POP_COUNT(else_tmask_cnt, else_tmask); + wire then_first = (then_tmask_cnt >= else_tmask_cnt); + wire [`NUM_THREADS-1:0] taken_tmask = then_first ? then_tmask : else_tmask; + wire [`NUM_THREADS-1:0] ntaken_tmask = then_first ? else_tmask : then_tmask; + + assign split.valid = is_split; + assign split.is_dvg = has_then && has_else; + assign split.then_tmask = taken_tmask; + assign split.else_tmask = ntaken_tmask; + assign split.next_pc = execute_if.data.PC + from_fullPC(`XLEN'(4)); + + // join + + assign sjoin.valid = is_join; + assign sjoin.stack_ptr = rs1_data[DV_STACK_SIZEW-1:0]; + + // barrier + + assign barrier.valid = is_bar; + assign barrier.id = rs1_data[NB_WIDTH-1:0]; +`ifdef GBAR_ENABLE + assign barrier.is_global= rs1_data[31]; +`else + assign barrier.is_global= 1'b0; +`endif + assign barrier.size_m1 = rs2_data[$bits(barrier.size_m1)-1:0] - $bits(barrier.size_m1)'(1); + assign barrier.is_noop = (rs2_data[$bits(barrier.size_m1)-1:0] == $bits(barrier.size_m1)'(1)); + + // wspawn + + wire [`NUM_WARPS-1:0] wspawn_wmask; + for (genvar i = 0; i < `NUM_WARPS; ++i) begin : g_wspawn_wmask + assign wspawn_wmask[i] = (i < rs1_data[NW_BITS:0]) && (i != execute_if.data.wid); + end + assign wspawn.valid = is_wspawn; + assign wspawn.wmask = wspawn_wmask; + assign wspawn.pc = from_fullPC(rs2_data); + + // response + + assign warp_ctl_if.dvstack_wid = execute_if.data.wid; + wire [DV_STACK_SIZEW-1:0] dvstack_ptr; + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (2) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (execute_if.valid), + .ready_in (execute_if.ready), + .data_in ({execute_if.data.uuid, execute_if.data.wid, execute_if.data.tmask, execute_if.data.PC, execute_if.data.rd, execute_if.data.wb, execute_if.data.pid, execute_if.data.sop, execute_if.data.eop, warp_ctl_if.dvstack_ptr}), + .data_out ({result_if.data.uuid, result_if.data.wid, result_if.data.tmask, result_if.data.PC, result_if.data.rd, result_if.data.wb, result_if.data.pid, result_if.data.sop, result_if.data.eop, dvstack_ptr}), + .valid_out (result_if.valid), + .ready_out (result_if.ready) + ); + + wire execute_fire = execute_if.valid && execute_if.ready; + wire wctl_valid = execute_fire && execute_if.data.eop; + + VX_pipe_register #( + .DATAW (1 + NW_WIDTH + WCTL_WIDTH), + .RESETW (1) + ) wctl_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({wctl_valid, execute_if.data.wid, tmc, wspawn, split, sjoin, barrier}), + .data_out ({warp_ctl_if.valid, warp_ctl_if.wid, warp_ctl_if.tmc, warp_ctl_if.wspawn, warp_ctl_if.split, warp_ctl_if.sjoin, warp_ctl_if.barrier}) + ); + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result_if + assign result_if.data.data[i] = `XLEN'(dvstack_ptr); + end + +endmodule diff --git a/designs/src/vortex/rtl/float_dpi.vh b/designs/src/vortex/rtl/float_dpi.vh new file mode 100644 index 0000000..5dc91eb --- /dev/null +++ b/designs/src/vortex/rtl/float_dpi.vh @@ -0,0 +1,45 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef FLOAT_DPI_VH +`define FLOAT_DPI_VH + +import "DPI-C" function void dpi_fadd(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fsub(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmul(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmadd(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmsub(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fnmadd(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fnmsub(input logic enable, input int dst_fmt, input longint a, input longint b, input longint c, input bit[2:0] frm, output longint result, output bit[4:0] fflags); + +import "DPI-C" function void dpi_fdiv(input logic enable, input int dst_fmt, input longint a, input longint b, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fsqrt(input logic enable, input int dst_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); + +import "DPI-C" function void dpi_ftoi(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_ftou(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_itof(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_utof(input logic enable, input int dst_fmt, input int src_fmt, input longint a, input bit[2:0] frm, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_f2f(input logic enable, input int dst_fmt, input int src_fmt, input longint a, output longint result); + +import "DPI-C" function void dpi_fclss(input logic enable, input int dst_fmt, input longint a, output longint result); +import "DPI-C" function void dpi_fsgnj(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result); +import "DPI-C" function void dpi_fsgnjn(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result); +import "DPI-C" function void dpi_fsgnjx(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result); + +import "DPI-C" function void dpi_flt(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fle(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_feq(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmin(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); +import "DPI-C" function void dpi_fmax(input logic enable, input int dst_fmt, input longint a, input longint b, output longint result, output bit[4:0] fflags); + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fcvt_unit.sv b/designs/src/vortex/rtl/fpu/VX_fcvt_unit.sv new file mode 100644 index 0000000..c362b29 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fcvt_unit.sv @@ -0,0 +1,321 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Modified port of cast module from fpnew Libray +// reference: https://github.com/pulp-platform/fpnew + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fcvt_unit import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter LATENCY = 1, + parameter INT_WIDTH = 32, + parameter MAN_BITS = 23, + parameter EXP_BITS = 8, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + input wire enable, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire is_itof, + input wire is_signed, + + input wire [31:0] dataa, + output wire [31:0] result, + + output wire [`FP_FLAGS_BITS-1:0] fflags +); + // Constants + localparam EXP_BIAS = 2**(EXP_BITS-1)-1; + + // The internal mantissa includes normal bit or an entire integer + localparam S_MAN_WIDTH = `MAX(1+MAN_BITS, INT_WIDTH); + + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam LZC_RESULT_WIDTH = `CLOG2(S_MAN_WIDTH); + + // The internal exponent must be able to represent the smallest denormal input value as signed + // or the number of bits in an integer + localparam S_EXP_WIDTH = `MAX(`CLOG2(INT_WIDTH), `MAX(EXP_BITS, `CLOG2(EXP_BIAS + MAN_BITS))) + 1; + + localparam FMT_SHIFT_COMPENSATION = S_MAN_WIDTH - 1 - MAN_BITS; + localparam NUM_FP_STICKY = 2 * S_MAN_WIDTH - MAN_BITS - 1; // removed mantissa, 1. and R + localparam NUM_INT_STICKY = 2 * S_MAN_WIDTH - INT_WIDTH; // removed int and R + + // Input processing + + fclass_t fclass; + VX_fp_classifier #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_classifier ( + .exp_i (dataa[INT_WIDTH-2:MAN_BITS]), + .man_i (dataa[MAN_BITS-1:0]), + .clss_o (fclass) + ); + + wire [S_MAN_WIDTH-1:0] input_mant; + wire [S_EXP_WIDTH-1:0] input_exp; + wire input_sign; + + wire i2f_sign = dataa[INT_WIDTH-1]; + wire f2i_sign = dataa[INT_WIDTH-1] && is_signed; + wire [S_MAN_WIDTH-1:0] f2i_mantissa = f2i_sign ? (-dataa) : dataa; + wire [S_MAN_WIDTH-1:0] i2f_mantissa = S_MAN_WIDTH'({fclass.is_normal, dataa[MAN_BITS-1:0]}); + assign input_exp = {1'b0, dataa[MAN_BITS +: EXP_BITS]} + S_EXP_WIDTH'({1'b0, fclass.is_subnormal}); + assign input_mant = is_itof ? f2i_mantissa : i2f_mantissa; + assign input_sign = is_itof ? f2i_sign : i2f_sign; + + // Pipeline stage0 + + wire is_itof_s0; + wire is_signed_s0; + wire [2:0] rnd_mode_s0; + fclass_t fclass_s0; + wire input_sign_s0; + wire [S_EXP_WIDTH-1:0] fmt_exponent_s0; + wire [S_MAN_WIDTH-1:0] encoded_mant_s0; + + VX_pipe_register #( + .DATAW (1 + INST_FRM_BITS + 1 + $bits(fclass_t) + 1 + S_EXP_WIDTH + S_MAN_WIDTH), + .DEPTH (LATENCY > 1) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({is_itof, is_signed, frm, fclass, input_sign, input_exp, input_mant}), + .data_out ({is_itof_s0, is_signed_s0, rnd_mode_s0, fclass_s0, input_sign_s0, fmt_exponent_s0, encoded_mant_s0}) + ); + + // Normalization + + wire [LZC_RESULT_WIDTH-1:0] renorm_shamt_s0; // renormalization shift amount + wire mant_is_nonzero_s0; + + VX_lzc #( + .N (S_MAN_WIDTH) + ) lzc ( + .data_in (encoded_mant_s0), + .data_out (renorm_shamt_s0), + .valid_out (mant_is_nonzero_s0) + ); + + wire mant_is_zero_s0 = ~mant_is_nonzero_s0; + + wire [S_MAN_WIDTH-1:0] input_mant_n_s0; // normalized input mantissa + wire [S_EXP_WIDTH-1:0] input_exp_n_s0; // unbiased true exponent + + // Realign input mantissa, append zeroes if destination is wider + assign input_mant_n_s0 = encoded_mant_s0 << renorm_shamt_s0; + + // Unbias exponent and compensate for shift + wire [S_EXP_WIDTH-1:0] i2f_input_exp_s0 = fmt_exponent_s0 + S_EXP_WIDTH'(FMT_SHIFT_COMPENSATION - EXP_BIAS) - S_EXP_WIDTH'({1'b0, renorm_shamt_s0}); + wire [S_EXP_WIDTH-1:0] f2i_input_exp_s0 = S_EXP_WIDTH'(S_MAN_WIDTH-1) - S_EXP_WIDTH'({1'b0, renorm_shamt_s0}); + assign input_exp_n_s0 = is_itof_s0 ? f2i_input_exp_s0 : i2f_input_exp_s0; + + // Pipeline stage1 + + wire is_itof_s1; + wire is_signed_s1; + wire [2:0] rnd_mode_s1; + fclass_t fclass_s1; + wire input_sign_s1; + wire mant_is_zero_s1; + wire [S_MAN_WIDTH-1:0] input_mant_s1; + wire [S_EXP_WIDTH-1:0] input_exp_s1; + + VX_pipe_register #( + .DATAW (1 + INST_FRM_BITS + 1 + $bits(fclass_t) + 1 + 1 + S_MAN_WIDTH + S_EXP_WIDTH), + .DEPTH (LATENCY > 2) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({is_itof_s0, is_signed_s0, rnd_mode_s0, fclass_s0, input_sign_s0, mant_is_zero_s0, input_mant_n_s0, input_exp_n_s0}), + .data_out ({is_itof_s1, is_signed_s1, rnd_mode_s1, fclass_s1, input_sign_s1, mant_is_zero_s1, input_mant_s1, input_exp_s1}) + ); + + // Perform adjustments to mantissa and exponent + + wire [S_EXP_WIDTH-1:0] denorm_shamt = S_EXP_WIDTH'(INT_WIDTH-1) - input_exp_s1; + wire overflow = ($signed(denorm_shamt) <= -$signed(S_EXP_WIDTH'(!is_signed_s1))); + wire underflow = ($signed(input_exp_s1) < S_EXP_WIDTH'($signed(-1))); + reg [S_EXP_WIDTH-1:0] denorm_shamt_q; + always @(*) begin + if (overflow) begin + denorm_shamt_q = '0; + end else if (underflow) begin + denorm_shamt_q = INT_WIDTH+1; + end else begin + denorm_shamt_q = denorm_shamt; + end + end + wire [2*S_MAN_WIDTH:0] destination_mant_s1 = is_itof_s1 ? {input_mant_s1, 33'b0} : ({input_mant_s1, 33'b0} >> denorm_shamt_q); + wire [EXP_BITS-1:0] final_exp_s1 = input_exp_s1[EXP_BITS-1:0] + EXP_BITS'(EXP_BIAS); + wire of_before_round_s1 = overflow; + + // Pipeline stage2 + + wire is_itof_s2; + wire is_signed_s2; + wire [2:0] rnd_mode_s2; + fclass_t fclass_s2; + wire mant_is_zero_s2; + wire input_sign_s2; + wire [2*S_MAN_WIDTH:0] destination_mant_s2; + wire [EXP_BITS-1:0] final_exp_s2; + wire of_before_round_s2; + + VX_pipe_register #( + .DATAW (1 + 1 + INST_FRM_BITS + $bits(fclass_t) + 1 + 1 + (2*S_MAN_WIDTH+1) + EXP_BITS + 1), + .DEPTH (LATENCY > 0) + ) pipe_reg2 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({is_itof_s1, is_signed_s1, rnd_mode_s1, fclass_s1, mant_is_zero_s1, input_sign_s1, destination_mant_s1, final_exp_s1, of_before_round_s1}), + .data_out ({is_itof_s2, is_signed_s2, rnd_mode_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, destination_mant_s2, final_exp_s2, of_before_round_s2}) + ); + + // Rouding and classification + + wire [MAN_BITS-1:0] final_mant_s2; // mantissa after adjustments + wire [INT_WIDTH-1:0] final_int_s2; // integer shifted in position + wire [1:0] f2i_round_sticky_bits_s2, i2f_round_sticky_bits_s2; + + // Extract final mantissa and round bit, discard the normal bit (for FP) + assign {final_mant_s2, i2f_round_sticky_bits_s2[1]} = destination_mant_s2[2*S_MAN_WIDTH-1 : 2*S_MAN_WIDTH-1 - (MAN_BITS+1) + 1]; + assign {final_int_s2, f2i_round_sticky_bits_s2[1]} = destination_mant_s2[2*S_MAN_WIDTH : 2*S_MAN_WIDTH - (INT_WIDTH+1) + 1]; + + // Collapse sticky bits + assign i2f_round_sticky_bits_s2[0] = (| destination_mant_s2[NUM_FP_STICKY-1:0]); + assign f2i_round_sticky_bits_s2[0] = (| destination_mant_s2[NUM_INT_STICKY-1:0]); + wire i2f_round_has_sticky_s2 = (| i2f_round_sticky_bits_s2); + wire f2i_round_has_sticky_s2 = (| f2i_round_sticky_bits_s2); + + // select RS bits for destination operation + wire [1:0] round_sticky_bits_s2 = is_itof_s2 ? i2f_round_sticky_bits_s2 : f2i_round_sticky_bits_s2; + + // Pack exponent and mantissa into proper rounding form + wire [INT_WIDTH-1:0] fmt_pre_round_abs_s2 = {1'b0, final_exp_s2, final_mant_s2[MAN_BITS-1:0]}; + + // Select output with destination format and operation + wire [INT_WIDTH-1:0] pre_round_abs_s2 = is_itof_s2 ? fmt_pre_round_abs_s2 : final_int_s2; + + wire [INT_WIDTH-1:0] rounded_abs_s2; + wire rounded_sign_s2; + + // Perform the rounding + VX_fp_rounding #( + .DAT_WIDTH (32) + ) fp_rounding ( + .abs_value_i (pre_round_abs_s2), + .sign_i (input_sign_s2), + .round_sticky_bits_i (round_sticky_bits_s2), + .rnd_mode_i (rnd_mode_s2), + .effective_subtraction_i (1'b0), + .abs_rounded_o (rounded_abs_s2), + .sign_o (rounded_sign_s2), + `UNUSED_PIN (exact_zero_o) + ); + + // Pipeline stage3 + + wire is_itof_s3; + wire is_signed_s3; + fclass_t fclass_s3; + wire mant_is_zero_s3; + wire input_sign_s3; + wire rounded_sign_s3; + wire [INT_WIDTH-1:0] rounded_abs_s3; + wire of_before_round_s3; + wire f2i_round_has_sticky_s3; + wire i2f_round_has_sticky_s3; + + `UNUSED_VAR (fclass_s3) + + VX_pipe_register #( + .DATAW (1 + 1 + $bits(fclass_t) + 1 + 1 + 32 + 1 + 1 + 1 + 1), + .DEPTH (LATENCY > 3) + ) pipe_reg3 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({is_itof_s2, is_signed_s2, fclass_s2, mant_is_zero_s2, input_sign_s2, rounded_abs_s2, rounded_sign_s2, of_before_round_s2, f2i_round_has_sticky_s2, i2f_round_has_sticky_s2}), + .data_out ({is_itof_s3, is_signed_s3, fclass_s3, mant_is_zero_s3, input_sign_s3, rounded_abs_s3, rounded_sign_s3, of_before_round_s3, f2i_round_has_sticky_s3, i2f_round_has_sticky_s3}) + ); + + // Assemble regular result, nan box short ones. Int zeroes need to be detected + wire [INT_WIDTH-1:0] fmt_result_s3 = mant_is_zero_s3 ? 0 : {rounded_sign_s3, rounded_abs_s3[EXP_BITS+MAN_BITS-1:0]}; + + // Negative integer result needs to be brought into two's complement + wire [INT_WIDTH-1:0] rounded_int_res_s3 = rounded_sign_s3 ? (-rounded_abs_s3) : rounded_abs_s3; + wire rounded_int_res_zero_s3 = (rounded_int_res_s3 == 0); + + // F2I Special case handling + + // Assemble result according to destination format + reg [INT_WIDTH-1:0] f2i_special_result_s3; + always @(*) begin + if (input_sign_s3 && !fclass_s3.is_nan) begin + f2i_special_result_s3[INT_WIDTH-2:0] = '0; // alone yields 2**(31)-1 + f2i_special_result_s3[INT_WIDTH-1] = is_signed_s3; // for unsigned casts yields 2**31 + end else begin + f2i_special_result_s3[INT_WIDTH-2:0] = 2**(INT_WIDTH-1) - 1; // alone yields 2**(31)-1 + f2i_special_result_s3[INT_WIDTH-1] = ~is_signed_s3; // for unsigned casts yields 2**31 + end + end + + // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) + wire f2i_result_is_special_s3 = fclass_s3.is_nan + | fclass_s3.is_inf + | of_before_round_s3 + | (input_sign_s3 & ~is_signed_s3 & ~rounded_int_res_zero_s3); + + fflags_t f2i_special_status_s3; + fflags_t i2f_status_s3, f2i_status_s3; + fflags_t tmp_fflags_s3; + + // All integer special cases are invalid + assign f2i_special_status_s3 = {1'b1, 4'h0}; + + // Result selection and output + + assign i2f_status_s3 = {4'h0, i2f_round_has_sticky_s3}; + assign f2i_status_s3 = f2i_result_is_special_s3 ? f2i_special_status_s3 : {4'h0, f2i_round_has_sticky_s3}; + + wire [INT_WIDTH-1:0] i2f_result_s3 = fmt_result_s3; + wire [INT_WIDTH-1:0] f2i_result_s3 = f2i_result_is_special_s3 ? f2i_special_result_s3 : rounded_int_res_s3; + + wire [INT_WIDTH-1:0] tmp_result_s3 = is_itof_s3 ? i2f_result_s3 : f2i_result_s3; + assign tmp_fflags_s3 = is_itof_s3 ? i2f_status_s3 : f2i_status_s3; + + VX_pipe_register #( + .DATAW (32 + `FP_FLAGS_BITS), + .DEPTH (OUT_REG) + ) pipe_reg4 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({tmp_result_s3, tmp_fflags_s3}), + .data_out ({result, fflags}) + ); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fncp_unit.sv b/designs/src/vortex/rtl/fpu/VX_fncp_unit.sv new file mode 100644 index 0000000..dc1d0b6 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fncp_unit.sv @@ -0,0 +1,246 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Modified port of noncomp module from fpnew Libray +// reference: https://github.com/pulp-platform/fpnew + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fncp_unit import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter LATENCY = 1, + parameter EXP_BITS = 8, + parameter MAN_BITS = 23, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + input wire enable, + + input wire [INST_FPU_BITS-1:0] op_type, + input wire [INST_FRM_BITS-1:0] frm, + + input wire [31:0] dataa, + input wire [31:0] datab, + output wire [31:0] result, + + output wire [`FP_FLAGS_BITS-1:0] fflags +); + localparam NEG_INF = 32'h00000001, + NEG_NORM = 32'h00000002, + NEG_SUBNORM = 32'h00000004, + NEG_ZERO = 32'h00000008, + POS_ZERO = 32'h00000010, + POS_SUBNORM = 32'h00000020, + POS_NORM = 32'h00000040, + POS_INF = 32'h00000080, + //SIG_NAN = 32'h00000100, + QUT_NAN = 32'h00000200; + + wire a_sign, b_sign; + wire [7:0] a_exponent, b_exponent; + wire [22:0] a_mantissa, b_mantissa; + fclass_t a_fclass, b_fclass; + wire a_smaller, ab_equal; + + // Setup + assign a_sign = dataa[31]; + assign a_exponent = dataa[30:23]; + assign a_mantissa = dataa[22:0]; + + assign b_sign = datab[31]; + assign b_exponent = datab[30:23]; + assign b_mantissa = datab[22:0]; + + VX_fp_classifier #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class_a ( + .exp_i (a_exponent), + .man_i (a_mantissa), + .clss_o (a_fclass) + ); + + VX_fp_classifier #( + .EXP_BITS (EXP_BITS), + .MAN_BITS (MAN_BITS) + ) fp_class_b ( + .exp_i (b_exponent), + .man_i (b_mantissa), + .clss_o (b_fclass) + ); + + assign a_smaller = (dataa < datab) ^ (a_sign || b_sign); + assign ab_equal = (dataa == datab) + || (a_fclass.is_zero && b_fclass.is_zero); // +0 == -0 + + // Pipeline stage0 + + wire [3:0] op_mod_s0; + wire [31:0] dataa_s0, datab_s0; + wire a_sign_s0, b_sign_s0; + wire [7:0] a_exponent_s0; + wire [22:0] a_mantissa_s0; + fclass_t a_fclass_s0, b_fclass_s0; + wire a_smaller_s0, ab_equal_s0; + + `UNUSED_VAR (b_fclass_s0) + + wire [3:0] op_mod = {(op_type == INST_FPU_CMP), frm}; + + VX_pipe_register #( + .DATAW (4 + 2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fclass_t) + 1 + 1), + .DEPTH (LATENCY > 0) + ) pipe_reg0 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({op_mod, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_fclass, b_fclass, a_smaller, ab_equal}), + .data_out ({op_mod_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_fclass_s0, b_fclass_s0, a_smaller_s0, ab_equal_s0}) + ); + + // FCLASS + reg [31:0] fclass_mask_s0; // generate a 10-bit mask for integer reg + always @(*) begin + if (a_fclass_s0.is_normal) begin + fclass_mask_s0 = a_sign_s0 ? NEG_NORM : POS_NORM; + end + else if (a_fclass_s0.is_inf) begin + fclass_mask_s0 = a_sign_s0 ? NEG_INF : POS_INF; + end + else if (a_fclass_s0.is_zero) begin + fclass_mask_s0 = a_sign_s0 ? NEG_ZERO : POS_ZERO; + end + else if (a_fclass_s0.is_subnormal) begin + fclass_mask_s0 = a_sign_s0 ? NEG_SUBNORM : POS_SUBNORM; + end + else if (a_fclass_s0.is_nan) begin + fclass_mask_s0 = {22'h0, a_fclass_s0.is_quiet, a_fclass_s0.is_signaling, 8'h0}; + end + else begin + fclass_mask_s0 = QUT_NAN; + end + end + + // Min/Max + reg [31:0] fminmax_res_s0; + always @(*) begin + if (a_fclass_s0.is_nan && b_fclass_s0.is_nan) + fminmax_res_s0 = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN + else if (a_fclass_s0.is_nan) + fminmax_res_s0 = datab_s0; + else if (b_fclass_s0.is_nan) + fminmax_res_s0 = dataa_s0; + else begin + // FMIN, FMAX + fminmax_res_s0 = (op_mod_s0[0] ^ a_smaller_s0) ? dataa_s0 : datab_s0; + end + end + + // Sign injection + reg [31:0] fsgnj_res_s0; // result of sign injection + always @(*) begin + case (op_mod_s0[1:0]) + 0: fsgnj_res_s0 = { b_sign_s0, a_exponent_s0, a_mantissa_s0}; + 1: fsgnj_res_s0 = {~b_sign_s0, a_exponent_s0, a_mantissa_s0}; + default: fsgnj_res_s0 = { a_sign_s0 ^ b_sign_s0, a_exponent_s0, a_mantissa_s0}; + endcase + end + + // Comparison + reg fcmp_res_s0; // result of comparison + reg fcmp_fflags_NV_s0; // comparison fflags + always @(*) begin + case (op_mod_s0[1:0]) + 0: begin // LE + if (a_fclass_s0.is_nan || b_fclass_s0.is_nan) begin + fcmp_res_s0 = 0; + fcmp_fflags_NV_s0 = 1; + end else begin + fcmp_res_s0 = (a_smaller_s0 | ab_equal_s0); + fcmp_fflags_NV_s0 = 0; + end + end + 1: begin // LT + if (a_fclass_s0.is_nan || b_fclass_s0.is_nan) begin + fcmp_res_s0 = 0; + fcmp_fflags_NV_s0 = 1; + end else begin + fcmp_res_s0 = (a_smaller_s0 & ~ab_equal_s0); + fcmp_fflags_NV_s0 = 0; + end + end + 2: begin // EQ + if (a_fclass_s0.is_nan || b_fclass_s0.is_nan) begin + fcmp_res_s0 = 0; + fcmp_fflags_NV_s0 = a_fclass_s0.is_signaling | b_fclass_s0.is_signaling; + end else begin + fcmp_res_s0 = ab_equal_s0; + fcmp_fflags_NV_s0 = 0; + end + end + default: begin + fcmp_res_s0 = 'x; + fcmp_fflags_NV_s0 = 'x; + end + endcase + end + + // outputs + reg [31:0] result_s0; + reg fflags_NV_s0; + always @(*) begin + case (op_mod_s0[2:0]) + 0,1,2: begin + // SGNJ, CMP + result_s0 = op_mod_s0[3] ? 32'(fcmp_res_s0) : fsgnj_res_s0; + fflags_NV_s0 = fcmp_fflags_NV_s0; + end + 3: begin + // CLASS + result_s0 = fclass_mask_s0; + fflags_NV_s0 = 0; + end + 4,5: begin + // FMV + result_s0 = dataa_s0; + fflags_NV_s0 = 0; + end + 6,7: begin + // MIN/MAX + result_s0 = fminmax_res_s0; + fflags_NV_s0 = a_fclass_s0.is_signaling | b_fclass_s0.is_signaling; + end + endcase + end + + wire fflags_NV; + + VX_pipe_register #( + .DATAW (32 + 1), + .DEPTH (OUT_REG) + ) pipe_reg1 ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({result_s0, fflags_NV_s0}), + .data_out ({result, fflags_NV}) + ); + // NV, DZ, OF, UF, NX + assign fflags = {fflags_NV, 1'b0, 1'b0, 1'b0, 1'b0}; + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fp_classifier.sv b/designs/src/vortex/rtl/fpu/VX_fp_classifier.sv new file mode 100644 index 0000000..bde0383 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fp_classifier.sv @@ -0,0 +1,44 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fp_classifier import VX_fpu_pkg::*; #( + parameter MAN_BITS = 23, + parameter EXP_BITS = 8 +) ( + input [EXP_BITS-1:0] exp_i, + input [MAN_BITS-1:0] man_i, + output fclass_t clss_o +); + wire is_normal = (exp_i != '0) && (exp_i != '1); + wire is_zero = (exp_i == '0) && (man_i == '0); + wire is_subnormal = (exp_i == '0) && (man_i != '0); + wire is_inf = (exp_i == '1) && (man_i == '0); + wire is_nan = (exp_i == '1) && (man_i != '0); + wire is_signaling = is_nan && ~man_i[MAN_BITS-1]; + wire is_quiet = is_nan && ~is_signaling; + + assign clss_o.is_normal = is_normal; + assign clss_o.is_zero = is_zero; + assign clss_o.is_subnormal = is_subnormal; + assign clss_o.is_inf = is_inf; + assign clss_o.is_nan = is_nan; + assign clss_o.is_quiet = is_quiet; + assign clss_o.is_signaling = is_signaling; + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fp_rounding.sv b/designs/src/vortex/rtl/fpu/VX_fp_rounding.sv new file mode 100644 index 0000000..8314849 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fp_rounding.sv @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Modified port of rouding module from fpnew Libray +// reference: https://github.com/pulp-platform/fpnew + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fp_rounding import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter DAT_WIDTH = 2 // Width of the abolute value, without sign bit +) ( + // inputs + input wire [DAT_WIDTH-1:0] abs_value_i, // absolute value without sign + input wire sign_i, + // rounding information + input wire [1:0] round_sticky_bits_i, // round and sticky bits {RS} + input wire [2:0] rnd_mode_i, + input wire effective_subtraction_i, // sign of inputs affects rounding of zeroes + // outputs + output wire [DAT_WIDTH-1:0] abs_rounded_o, // absolute value without sign + output wire sign_o, + output wire exact_zero_o // output is an exact zero +); + + reg round_up; // Rounding decision + + // Take the rounding decision according to RISC-V spec + // RoundMode | Mnemonic | Meaning + // :--------:|:--------:|:------- + // 000 | RNE | Round to Nearest, ties to Even + // 001 | RTZ | Round towards Zero + // 010 | RDN | Round Down (towards -\infty) + // 011 | RUP | Round Up (towards \infty) + // 100 | RMM | Round to Nearest, ties to Max Magnitude + // others | | *invalid* + + always @(*) begin + case (rnd_mode_i) + INST_FRM_RNE: // Decide accoring to round/sticky bits + case (round_sticky_bits_i) + 2'b00, + 2'b01: round_up = 1'b0; // < ulp/2 away, round down + 2'b10: round_up = abs_value_i[0]; // = ulp/2 away, round towards even result + 2'b11: round_up = 1'b1; // > ulp/2 away, round up + endcase + INST_FRM_RTZ: round_up = 1'b0; // always round down + INST_FRM_RDN: round_up = (| round_sticky_bits_i) & sign_i; // to 0 if +, away if - + INST_FRM_RUP: round_up = (| round_sticky_bits_i) & ~sign_i; // to 0 if -, away if + + INST_FRM_RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up + default: round_up = 1'bx; // propagate x + endcase + end + + // Perform the rounding, exponent change and overflow to inf happens automagically + assign abs_rounded_o = abs_value_i + DAT_WIDTH'(round_up); + + // True zero result is a zero result without dirty round/sticky bits + assign exact_zero_o = (abs_value_i == 0) && (round_sticky_bits_i == 0); + + // In case of effective subtraction (thus signs of addition operands must have differed) and a + // true zero result, the result sign is '-' in case of RDN and '+' for other modes. + assign sign_o = (exact_zero_o && effective_subtraction_i) ? (rnd_mode_i == INST_FRM_RDN) + : sign_i; + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_csr_if.sv b/designs/src/vortex/rtl/fpu/VX_fpu_csr_if.sv new file mode 100644 index 0000000..c20d052 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_csr_if.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +interface VX_fpu_csr_if import VX_gpu_pkg::*, VX_fpu_pkg::*; (); + + wire write_enable; + wire [NW_WIDTH-1:0] write_wid; + fflags_t write_fflags; + + wire [NW_WIDTH-1:0] read_wid; + wire [INST_FRM_BITS-1:0] read_frm; + + modport master ( + output write_enable, + output write_wid, + output write_fflags, + + output read_wid, + input read_frm + ); + + modport slave ( + input write_enable, + input write_wid, + input write_fflags, + + input read_wid, + output read_frm + ); + +endinterface diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_cvt.sv b/designs/src/vortex/rtl/fpu/VX_fpu_cvt.sv new file mode 100644 index 0000000..cd7e8b0 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_cvt.sv @@ -0,0 +1,123 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_cvt import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 5, + parameter NUM_PES = `UP(NUM_LANES / `FCVT_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire is_itof, + input wire is_signed, + + input wire [NUM_LANES-1:0][31:0] dataa, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam DATAW = 32 + INST_FRM_BITS + 1 + 1; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + fflags_t [NUM_LANES-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = dataa[i]; + assign data_in[i][32 +: INST_FRM_BITS] = frm; + assign data_in[i][32 + INST_FRM_BITS +: 1] = is_itof; + assign data_in[i][32 + INST_FRM_BITS + 1 +: 1] = is_signed; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FCVT), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fcvt_units + VX_fcvt_unit #( + .LATENCY (`LATENCY_FCVT), + .OUT_REG (1) + ) fcvt_unit ( + .clk (clk), + .reset (reset), + .enable (pe_enable), + .frm (pe_data_in[0][32 +: INST_FRM_BITS]), + .is_itof (pe_data_in[0][32 + INST_FRM_BITS +: 1]), + .is_signed (pe_data_in[0][32 + INST_FRM_BITS + 1 +: 1]), + .dataa (pe_data_in[i][0 +: 32]), + .result (pe_data_out[i][0 +: 32]), + .fflags (pe_data_out[i][32 +: `FP_FLAGS_BITS]) + ); + end + + assign has_fflags = 1; + + `FPU_MERGE_FFLAGS(fflags, fflags_out, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_define.vh b/designs/src/vortex/rtl/fpu/VX_fpu_define.vh new file mode 100644 index 0000000..596db92 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_define.vh @@ -0,0 +1,42 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_FPU_DEFINE_VH +`define VX_FPU_DEFINE_VH + +`include "VX_define.vh" + +`ifdef SV_DPI +`include "float_dpi.vh" +`endif + +`define FPU_MERGE_FFLAGS(out, in, mask, lanes) \ + fflags_t __``out; \ + always @(*) begin \ + __``out = '0; \ + for (integer __i = 0; __i < lanes; ++__i) begin \ + if (mask[__i]) begin \ + __``out.NX |= in[__i].NX; \ + __``out.UF |= in[__i].UF; \ + __``out.OF |= in[__i].OF; \ + __``out.DZ |= in[__i].DZ; \ + __``out.NV |= in[__i].NV; \ + end \ + end \ + end \ + assign out = __``out + +`define FP_CLASS_BITS $bits(VX_fpu_pkg::fclass_t) +`define FP_FLAGS_BITS $bits(VX_fpu_pkg::fflags_t) + +`endif // VX_FPU_DEFINE_VH diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_div.sv b/designs/src/vortex/rtl/fpu/VX_fpu_div.sv new file mode 100644 index 0000000..b5eb717 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_div.sv @@ -0,0 +1,179 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_div import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES / `FDIV_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + output wire valid_out, + input wire ready_out +); + localparam DATAW = 2 * 32 + INST_FRM_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = dataa[i]; + assign data_in[i][32 +: 32] = datab[i]; + assign data_in[i][64 +: INST_FRM_BITS] = frm; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FDIV), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + acl_fdiv fdiv ( + .clk (clk), + .areset (1'b0), + .en (pe_enable), + .a (pe_data_in[i][0 +: 32]), + .b (pe_data_in[i][32 +: 32]), + .q (pe_data_out[i][0 +: 32]) + ); + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x; + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + `UNUSED_VAR (fflags_out) + +`elsif VIVADO + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + wire [3:0] tuser; + xil_fdiv fdiv ( + .aclk (clk), + .aclken (pe_enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (pe_data_in[i][0 +: 32]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (pe_data_in[i][32 +: 32]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (pe_data_out[i][0 +: 32]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = {tuser[2], tuser[3], tuser[1], tuser[0], 1'b0}; + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`else + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fdivs + reg [63:0] r; + `UNUSED_VAR (r) + fflags_t f; + + always @(*) begin + dpi_fdiv ( + pe_enable, + int'(0), + {32'hffffffff, pe_data_in[i][0 +: 32]}, // a + {32'hffffffff, pe_data_in[i][32 +: 32]}, // b + pe_data_in[0][64 +: INST_FRM_BITS], // frm + r, + f + ); + end + + VX_shift_register #( + .DATAW (`FP_FLAGS_BITS + 32), + .DEPTH (`LATENCY_FDIV) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (pe_enable), + .data_in ({f, r[31:0]}), + .data_out (pe_data_out[i]) + ); + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_dpi.sv b/designs/src/vortex/rtl/fpu/VX_fpu_dpi.sv new file mode 100644 index 0000000..0796e4d --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_dpi.sv @@ -0,0 +1,477 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DPI + +module VX_fpu_dpi import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter TAG_WIDTH = 1, + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FPU_BITS-1:0] op_type, + input wire [INST_FMT_BITS-1:0] fmt, + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][`XLEN-1:0] dataa, + input wire [NUM_LANES-1:0][`XLEN-1:0] datab, + input wire [NUM_LANES-1:0][`XLEN-1:0] datac, + output wire [NUM_LANES-1:0][`XLEN-1:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam FPU_FMA = 0; + localparam FPU_DIVSQRT = 1; + localparam FPU_CVT = 2; + localparam FPU_NCP = 3; + localparam NUM_FPC = 4; + localparam FPC_BITS = `LOG2UP(NUM_FPC); + + localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAG_WIDTH; + + wire [NUM_FPC-1:0] per_core_ready_in; + wire [NUM_FPC-1:0][NUM_LANES-1:0][`XLEN-1:0] per_core_result; + wire [NUM_FPC-1:0][TAG_WIDTH-1:0] per_core_tag_out; + reg [NUM_FPC-1:0] per_core_ready_out; + wire [NUM_FPC-1:0] per_core_valid_out; + wire [NUM_FPC-1:0] per_core_has_fflags; + fflags_t [NUM_FPC-1:0] per_core_fflags; + + wire div_ready_in, sqrt_ready_in; + wire [NUM_LANES-1:0][`XLEN-1:0] div_result, sqrt_result; + wire [TAG_WIDTH-1:0] div_tag_out, sqrt_tag_out; + wire div_ready_out, sqrt_ready_out; + wire div_valid_out, sqrt_valid_out; + wire div_has_fflags, sqrt_has_fflags; + fflags_t div_fflags, sqrt_fflags; + + reg [FPC_BITS-1:0] core_select; + + reg is_fadd, is_fsub, is_fmul, is_fmadd, is_fmsub, is_fnmadd, is_fnmsub; + reg is_div, is_fcmp, is_itof, is_utof, is_ftoi, is_ftou, is_f2f; + + reg [NUM_LANES-1:0][63:0] operands [3]; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + operands[0][i] = 64'(dataa[i]); + operands[1][i] = 64'(datab[i]); + operands[2][i] = 64'(datac[i]); + end + end + + wire f_fmt = fmt[0]; // S/D format + wire i_fmt = fmt[1]; // W/L format + + always @(*) begin + is_fadd = 0; + is_fsub = 0; + is_fmul = 0; + is_fmadd = 0; + is_fmsub = 0; + is_fnmadd = 0; + is_fnmsub = 0; + is_div = 0; + is_fcmp = 0; + is_itof = 0; + is_utof = 0; + is_ftoi = 0; + is_ftou = 0; + is_f2f = 0; + + case (op_type) + INST_FPU_ADD: begin core_select = FPU_FMA; is_fadd = ~i_fmt; is_fsub = i_fmt; end + INST_FPU_MADD: begin core_select = FPU_FMA; is_fmadd = ~i_fmt; is_fmsub = i_fmt; end + INST_FPU_NMADD: begin core_select = FPU_FMA; is_fnmadd = ~i_fmt; is_fnmsub = i_fmt; end + INST_FPU_MUL: begin core_select = FPU_FMA; is_fmul = 1; end + INST_FPU_DIV: begin core_select = FPU_DIVSQRT; is_div = 1; end + INST_FPU_SQRT: begin core_select = FPU_DIVSQRT; end + INST_FPU_CMP: begin core_select = FPU_NCP; is_fcmp = 1; end + INST_FPU_F2I: begin core_select = FPU_CVT; is_ftoi = 1; end + INST_FPU_F2U: begin core_select = FPU_CVT; is_ftou = 1; end + INST_FPU_I2F: begin core_select = FPU_CVT; is_itof = 1; end + INST_FPU_U2F: begin core_select = FPU_CVT; is_utof = 1; end + INST_FPU_F2F: begin core_select = FPU_CVT; is_f2f = 1; end + default: begin core_select = FPU_NCP; end + endcase + end + + generate + begin : g_fma + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fma; + reg [NUM_LANES-1:0][63:0] result_fadd; + reg [NUM_LANES-1:0][63:0] result_fsub; + reg [NUM_LANES-1:0][63:0] result_fmul; + reg [NUM_LANES-1:0][63:0] result_fmadd; + reg [NUM_LANES-1:0][63:0] result_fmsub; + reg [NUM_LANES-1:0][63:0] result_fnmadd; + reg [NUM_LANES-1:0][63:0] result_fnmsub; + + fflags_t [NUM_LANES-1:0] fflags_fma; + fflags_t [NUM_LANES-1:0] fflags_fadd; + fflags_t [NUM_LANES-1:0] fflags_fsub; + fflags_t [NUM_LANES-1:0] fflags_fmul; + fflags_t [NUM_LANES-1:0] fflags_fmadd; + fflags_t [NUM_LANES-1:0] fflags_fmsub; + fflags_t [NUM_LANES-1:0] fflags_fnmadd; + fflags_t [NUM_LANES-1:0] fflags_fnmsub; + + wire fma_valid = (valid_in && core_select == FPU_FMA); + wire fma_ready = per_core_ready_out[FPU_FMA] || ~per_core_valid_out[FPU_FMA]; + wire fma_fire = fma_valid && fma_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fadd (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], frm, result_fadd[i], fflags_fadd[i]); + dpi_fsub (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], frm, result_fsub[i], fflags_fsub[i]); + dpi_fmul (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], frm, result_fmul[i], fflags_fmul[i]); + dpi_fmadd (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmadd[i], fflags_fmadd[i]); + dpi_fmsub (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fmsub[i], fflags_fmsub[i]); + dpi_fnmadd (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmadd[i], fflags_fnmadd[i]); + dpi_fnmsub (fma_fire, int'(f_fmt), operands[0][i], operands[1][i], operands[2][i], frm, result_fnmsub[i], fflags_fnmsub[i]); + + result_fma[i] = is_fadd ? result_fadd[i][`XLEN-1:0] : + is_fsub ? result_fsub[i][`XLEN-1:0] : + is_fmul ? result_fmul[i][`XLEN-1:0] : + is_fmadd ? result_fmadd[i][`XLEN-1:0] : + is_fmsub ? result_fmsub[i][`XLEN-1:0] : + is_fnmadd ? result_fnmadd[i][`XLEN-1:0] : + is_fnmsub ? result_fnmsub[i][`XLEN-1:0] : + '0; + + fflags_fma[i] = is_fadd ? fflags_fadd[i] : + is_fsub ? fflags_fsub[i] : + is_fmul ? fflags_fmul[i] : + is_fmadd ? fflags_fmadd[i] : + is_fmsub ? fflags_fmsub[i] : + is_fnmadd ? fflags_fnmadd[i] : + is_fnmsub ? fflags_fnmsub[i] : + '0; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fma, mask_in, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FMA), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fma_ready), + .data_in ({fma_valid, tag_in, result_fma, fflags_merged}), + .data_out ({per_core_valid_out[FPU_FMA], per_core_tag_out[FPU_FMA], per_core_result[FPU_FMA], per_core_fflags[FPU_FMA]}) + ); + + assign per_core_has_fflags[FPU_FMA] = 1; + assign per_core_ready_in[FPU_FMA] = fma_ready; + + end + endgenerate + + generate + begin : g_fdiv + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fdiv_r; + reg [NUM_LANES-1:0][63:0] result_fdiv; + fflags_t [NUM_LANES-1:0] fflags_fdiv; + + wire fdiv_valid = (valid_in && core_select == FPU_DIVSQRT) && is_div; + wire fdiv_ready = div_ready_out || ~div_valid_out; + wire fdiv_fire = fdiv_valid && fdiv_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fdiv (fdiv_fire, int'(f_fmt), operands[0][i], operands[1][i], frm, result_fdiv[i], fflags_fdiv[i]); + result_fdiv_r[i] = result_fdiv[i][`XLEN-1:0]; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fdiv, mask_in, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FDIV), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fdiv_ready), + .data_in ({fdiv_valid, tag_in, result_fdiv_r, fflags_merged}), + .data_out ({div_valid_out, div_tag_out, div_result, div_fflags}) + ); + + assign div_has_fflags = 1; + assign div_ready_in = fdiv_ready; + + end + endgenerate + + generate + begin : g_fsqrt + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fsqrt_r; + reg [NUM_LANES-1:0][63:0] result_fsqrt; + fflags_t [NUM_LANES-1:0] fflags_fsqrt; + + wire fsqrt_valid = (valid_in && core_select == FPU_DIVSQRT) && ~is_div; + wire fsqrt_ready = sqrt_ready_out || ~sqrt_valid_out; + wire fsqrt_fire = fsqrt_valid && fsqrt_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fsqrt (fsqrt_fire, int'(f_fmt), operands[0][i], frm, result_fsqrt[i], fflags_fsqrt[i]); + result_fsqrt_r[i] = result_fsqrt[i][`XLEN-1:0]; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fsqrt, mask_in, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FSQRT), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fsqrt_ready), + .data_in ({fsqrt_valid, tag_in, result_fsqrt_r, fflags_merged}), + .data_out ({sqrt_valid_out, sqrt_tag_out, sqrt_result, sqrt_fflags}) + ); + + assign sqrt_has_fflags = 1; + assign sqrt_ready_in = fsqrt_ready; + + end + endgenerate + + generate + begin : g_fcvt + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fcvt; + reg [NUM_LANES-1:0][63:0] result_itof; + reg [NUM_LANES-1:0][63:0] result_utof; + reg [NUM_LANES-1:0][63:0] result_ftoi; + reg [NUM_LANES-1:0][63:0] result_ftou; + reg [NUM_LANES-1:0][63:0] result_f2f; + + fflags_t [NUM_LANES-1:0] fflags_fcvt; + fflags_t [NUM_LANES-1:0] fflags_itof; + fflags_t [NUM_LANES-1:0] fflags_utof; + fflags_t [NUM_LANES-1:0] fflags_ftoi; + fflags_t [NUM_LANES-1:0] fflags_ftou; + + wire fcvt_valid = (valid_in && core_select == FPU_CVT); + wire fcvt_ready = per_core_ready_out[FPU_CVT] || ~per_core_valid_out[FPU_CVT]; + wire fcvt_fire = fcvt_valid && fcvt_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_itof (fcvt_fire, int'(f_fmt), int'(i_fmt), operands[0][i], frm, result_itof[i], fflags_itof[i]); + dpi_utof (fcvt_fire, int'(f_fmt), int'(i_fmt), operands[0][i], frm, result_utof[i], fflags_utof[i]); + dpi_ftoi (fcvt_fire, int'(i_fmt), int'(f_fmt), operands[0][i], frm, result_ftoi[i], fflags_ftoi[i]); + dpi_ftou (fcvt_fire, int'(i_fmt), int'(f_fmt), operands[0][i], frm, result_ftou[i], fflags_ftou[i]); + dpi_f2f (fcvt_fire, int'(f_fmt?1:0), int'(f_fmt?0:1), operands[0][i], result_f2f[i]); + + result_fcvt[i] = is_itof ? result_itof[i][`XLEN-1:0] : + is_utof ? result_utof[i][`XLEN-1:0] : + is_ftoi ? result_ftoi[i][`XLEN-1:0] : + is_ftou ? result_ftou[i][`XLEN-1:0] : + is_f2f ? result_f2f[i][`XLEN-1:0] : + '0; + + fflags_fcvt[i] = is_itof ? fflags_itof[i] : + is_utof ? fflags_utof[i] : + is_ftoi ? fflags_ftoi[i] : + is_ftou ? fflags_ftou[i] : + '0; + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fcvt, mask_in, NUM_LANES); + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FCVT), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fcvt_ready), + .data_in ({fcvt_valid, tag_in, result_fcvt, fflags_merged}), + .data_out ({per_core_valid_out[FPU_CVT], per_core_tag_out[FPU_CVT], per_core_result[FPU_CVT], per_core_fflags[FPU_CVT]}) + ); + + assign per_core_has_fflags[FPU_CVT] = 1; + assign per_core_ready_in[FPU_CVT] = fcvt_ready; + + end + endgenerate + + generate + begin : g_fncp + + reg [NUM_LANES-1:0][`XLEN-1:0] result_fncp; + reg [NUM_LANES-1:0][63:0] result_fclss; + reg [NUM_LANES-1:0][63:0] result_flt; + reg [NUM_LANES-1:0][63:0] result_fle; + reg [NUM_LANES-1:0][63:0] result_feq; + reg [NUM_LANES-1:0][63:0] result_fmin; + reg [NUM_LANES-1:0][63:0] result_fmax; + reg [NUM_LANES-1:0][63:0] result_fsgnj; + reg [NUM_LANES-1:0][63:0] result_fsgnjn; + reg [NUM_LANES-1:0][63:0] result_fsgnjx; + reg [NUM_LANES-1:0][63:0] result_fmvx; + reg [NUM_LANES-1:0][63:0] result_fmvf; + + fflags_t [NUM_LANES-1:0] fflags_fncp; + fflags_t [NUM_LANES-1:0] fflags_flt; + fflags_t [NUM_LANES-1:0] fflags_fle; + fflags_t [NUM_LANES-1:0] fflags_feq; + fflags_t [NUM_LANES-1:0] fflags_fmin; + fflags_t [NUM_LANES-1:0] fflags_fmax; + + wire fncp_valid = (valid_in && core_select == FPU_NCP); + wire fncp_ready = per_core_ready_out[FPU_NCP] || ~per_core_valid_out[FPU_NCP]; + wire fncp_fire = fncp_valid && fncp_ready; + + always @(*) begin + for (integer i = 0; i < NUM_LANES; ++i) begin + dpi_fclss (fncp_fire, int'(f_fmt), operands[0][i], result_fclss[i]); + dpi_fle (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_fle[i], fflags_fle[i]); + dpi_flt (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_flt[i], fflags_flt[i]); + dpi_feq (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_feq[i], fflags_feq[i]); + dpi_fmin (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_fmin[i], fflags_fmin[i]); + dpi_fmax (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_fmax[i], fflags_fmax[i]); + dpi_fsgnj (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_fsgnj[i]); + dpi_fsgnjn (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_fsgnjn[i]); + dpi_fsgnjx (fncp_fire, int'(f_fmt), operands[0][i], operands[1][i], result_fsgnjx[i]); + result_fmvx[i] = f_fmt ? operands[0][i] : 64'($signed(operands[0][i][31:0])); // sign-extension + result_fmvf[i] = f_fmt ? operands[0][i] : (operands[0][i] | 64'hffffffff00000000); // nan-boxing + end + end + + always @(*) begin + result_fncp = 'x; + fflags_fncp = 'x; + for (integer i = 0; i < NUM_LANES; ++i) begin + case (frm) + 0: begin result_fncp[i] = is_fcmp ? result_fle[i][`XLEN-1:0] : result_fsgnj[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fle[i]; end + 1: begin result_fncp[i] = is_fcmp ? result_flt[i][`XLEN-1:0] : result_fsgnjn[i][`XLEN-1:0]; fflags_fncp[i] = fflags_flt[i]; end + 2: begin result_fncp[i] = is_fcmp ? result_feq[i][`XLEN-1:0] : result_fsgnjx[i][`XLEN-1:0]; fflags_fncp[i] = fflags_feq[i]; end + 3: begin result_fncp[i] = result_fclss[i][`XLEN-1:0]; end + 4: begin result_fncp[i] = result_fmvx[i][`XLEN-1:0]; end + 5: begin result_fncp[i] = result_fmvf[i][`XLEN-1:0]; end + 6: begin result_fncp[i] = result_fmin[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmin[i]; end + 7: begin result_fncp[i] = result_fmax[i][`XLEN-1:0]; fflags_fncp[i] = fflags_fmax[i]; end + endcase + end + end + + fflags_t fflags_merged; + `FPU_MERGE_FFLAGS(fflags_merged, fflags_fncp, mask_in, NUM_LANES); + + wire has_fflags_fncp = (frm >= 6) || is_fcmp; + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH + 1 + NUM_LANES * `XLEN + $bits(fflags_t)), + .DEPTH (`LATENCY_FNCP), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (fncp_ready), + .data_in ({fncp_valid, tag_in, has_fflags_fncp, result_fncp, fflags_merged}), + .data_out ({per_core_valid_out[FPU_NCP], per_core_tag_out[FPU_NCP], per_core_has_fflags[FPU_NCP], per_core_result[FPU_NCP], per_core_fflags[FPU_NCP]}) + ); + + assign per_core_ready_in[FPU_NCP] = fncp_ready; + + end + endgenerate + + /////////////////////////////////////////////////////////////////////////// + + assign per_core_ready_in[FPU_DIVSQRT] = is_div ? div_ready_in : sqrt_ready_in; + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_DATAW), + .ARBITER ("P"), + .OUT_BUF (0) + ) div_sqrt_arb ( + .clk (clk), + .reset (reset), + .valid_in ({sqrt_valid_out, div_valid_out}), + .ready_in ({sqrt_ready_out, div_ready_out}), + .data_in ({{sqrt_result, sqrt_has_fflags, sqrt_fflags, sqrt_tag_out}, + {div_result, div_has_fflags, div_fflags, div_tag_out}}), + .data_out ({per_core_result[FPU_DIVSQRT], per_core_has_fflags[FPU_DIVSQRT], per_core_fflags[FPU_DIVSQRT], per_core_tag_out[FPU_DIVSQRT]}), + .valid_out (per_core_valid_out[FPU_DIVSQRT]), + .ready_out (per_core_ready_out[FPU_DIVSQRT]), + `UNUSED_PIN (sel_out) + ); + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_FPC-1:0][RSP_DATAW-1:0] per_core_data_out; + + for (genvar i = 0; i < NUM_FPC; ++i) begin : g_per_core_data_out + assign per_core_data_out[i] = {per_core_result[i], per_core_has_fflags[i], per_core_fflags[i], per_core_tag_out[i]}; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_FPC), + .DATAW (RSP_DATAW), + .ARBITER ("R"), + .OUT_BUF (OUT_BUF) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_out), + .ready_in (per_core_ready_out), + .data_in (per_core_data_out), + .data_out ({result, has_fflags, fflags, tag_out}), + .valid_out (valid_out), + .ready_out (ready_out), + `UNUSED_PIN (sel_out) + ); + + assign ready_in = per_core_ready_in[core_select]; + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_dsp.sv b/designs/src/vortex/rtl/fpu/VX_fpu_dsp.sv new file mode 100644 index 0000000..e8db12c --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_dsp.sv @@ -0,0 +1,426 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_dsp import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 4, + parameter TAG_WIDTH = 4, + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FPU_BITS-1:0] op_type, + input wire [INST_FMT_BITS-1:0] fmt, + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][`XLEN-1:0] dataa, + input wire [NUM_LANES-1:0][`XLEN-1:0] datab, + input wire [NUM_LANES-1:0][`XLEN-1:0] datac, + output wire [NUM_LANES-1:0][`XLEN-1:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam FPU_FMA = 0; + localparam FPU_DIVSQRT = 1; + localparam FPU_CVT = 2; + localparam FPU_NCP = 3; + localparam NUM_FPCORES = 4; + localparam FPCORES_BITS = `LOG2UP(NUM_FPCORES); + + localparam REQ_DATAW = NUM_LANES + TAG_WIDTH + INST_FPU_BITS + INST_FMT_BITS + INST_FRM_BITS + 3 * (NUM_LANES * 32); + localparam RSP_DATAW = (NUM_LANES * 32) + 1 + $bits(fflags_t) + TAG_WIDTH; + + `UNUSED_VAR (fmt) + + wire [NUM_FPCORES-1:0] per_core_valid_in; + wire [NUM_FPCORES-1:0][REQ_DATAW-1:0] per_core_data_in; + wire [NUM_FPCORES-1:0] per_core_ready_in; + + wire [NUM_FPCORES-1:0][NUM_LANES-1:0] per_core_mask_in; + wire [NUM_FPCORES-1:0][TAG_WIDTH-1:0] per_core_tag_in; + wire [NUM_FPCORES-1:0][INST_FPU_BITS-1:0] per_core_op_type; + wire [NUM_FPCORES-1:0][INST_FMT_BITS-1:0] per_core_fmt; + wire [NUM_FPCORES-1:0][INST_FRM_BITS-1:0] per_core_frm; + wire [NUM_FPCORES-1:0][NUM_LANES-1:0][31:0] per_core_dataa; + wire [NUM_FPCORES-1:0][NUM_LANES-1:0][31:0] per_core_datab; + wire [NUM_FPCORES-1:0][NUM_LANES-1:0][31:0] per_core_datac; + + wire [NUM_FPCORES-1:0] per_core_valid_out; + wire [NUM_FPCORES-1:0][NUM_LANES-1:0][31:0] per_core_result; + wire [NUM_FPCORES-1:0][TAG_WIDTH-1:0] per_core_tag_out; + wire [NUM_FPCORES-1:0] per_core_has_fflags; + fflags_t [NUM_FPCORES-1:0] per_core_fflags; + wire [NUM_FPCORES-1:0] per_core_ready_out; + + wire [NUM_LANES-1:0][31:0] dataa_s; + wire [NUM_LANES-1:0][31:0] datab_s; + wire [NUM_LANES-1:0][31:0] datac_s; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data + assign dataa_s[i] = dataa[i][31:0]; + assign datab_s[i] = datab[i][31:0]; + assign datac_s[i] = datac[i][31:0]; + end + + `UNUSED_VAR (dataa) + `UNUSED_VAR (datab) + `UNUSED_VAR (datac) + + // Decode fpu core type + wire [FPCORES_BITS-1:0] core_select = op_type[3:2]; + + VX_stream_switch #( + .DATAW (REQ_DATAW), + .NUM_INPUTS (1), + .NUM_OUTPUTS (NUM_FPCORES) + ) req_switch ( + .clk (clk), + .reset (reset), + .sel_in (core_select), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in ({mask_in, tag_in, fmt, frm, dataa_s, datab_s, datac_s, op_type}), + .data_out (per_core_data_in), + .valid_out (per_core_valid_in), + .ready_out (per_core_ready_in) + ); + + for (genvar i = 0; i < NUM_FPCORES; ++i) begin : g_per_core_data_in + assign { + per_core_mask_in[i], + per_core_tag_in[i], + per_core_fmt[i], + per_core_frm[i], + per_core_dataa[i], + per_core_datab[i], + per_core_datac[i], + per_core_op_type[i] + } = per_core_data_in[i]; + end + + // FMA core /////////////////////////////////////////////////////////////// + + wire is_madd = per_core_op_type[FPU_FMA][1]; + wire is_neg = per_core_op_type[FPU_FMA][0]; + wire is_sub = per_core_fmt[FPU_FMA][1]; + + VX_fpu_fma #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH) + ) fpu_fma ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_in[FPU_FMA]), + .ready_in (per_core_ready_in[FPU_FMA]), + .mask_in (per_core_mask_in[FPU_FMA]), + .tag_in (per_core_tag_in[FPU_FMA]), + .frm (per_core_frm[FPU_FMA]), + .is_madd (is_madd), + .is_sub (is_sub), + .is_neg (is_neg), + .dataa (per_core_dataa[FPU_FMA]), + .datab (per_core_datab[FPU_FMA]), + .datac (per_core_datac[FPU_FMA]), + .has_fflags (per_core_has_fflags[FPU_FMA]), + .fflags (per_core_fflags[FPU_FMA]), + .result (per_core_result[FPU_FMA]), + .tag_out (per_core_tag_out[FPU_FMA]), + .ready_out (per_core_ready_out[FPU_FMA]), + .valid_out (per_core_valid_out[FPU_FMA]) + ); + + // Div/Sqrt cores ///////////////////////////////////////////////////////// + + wire [1:0] div_sqrt_valid_in; + wire [1:0][REQ_DATAW-1:0] div_sqrt_data_in; + wire [1:0] div_sqrt_ready_in; + + wire [1:0][NUM_LANES-1:0] div_sqrt_mask_in; + wire [1:0][TAG_WIDTH-1:0] div_sqrt_tag_in; + wire [1:0][INST_FPU_BITS-1:0] div_sqrt_op_type; + wire [1:0][INST_FMT_BITS-1:0] div_sqrt_fmt; + wire [1:0][INST_FRM_BITS-1:0] div_sqrt_frm; + wire [1:0][NUM_LANES-1:0][31:0] div_sqrt_dataa; + wire [1:0][NUM_LANES-1:0][31:0] div_sqrt_datab; + wire [1:0][NUM_LANES-1:0][31:0] div_sqrt_datac; + + wire [1:0] div_sqrt_valid_out; + wire [1:0][NUM_LANES-1:0][31:0] div_sqrt_result; + wire [1:0][TAG_WIDTH-1:0] div_sqrt_tag_out; + wire [1:0] div_sqrt_has_fflags; + fflags_t [1:0] div_sqrt_fflags; + wire [1:0] div_sqrt_ready_out; + + wire div_sqrt_valid_tmp_in; + wire [REQ_DATAW-1:0] div_sqrt_data_tmp_in; + wire div_sqrt_ready_tmp_in; + + VX_elastic_buffer #( + .DATAW (REQ_DATAW) + ) div_sqrt_req_buffer ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_in[FPU_DIVSQRT]), + .ready_in (per_core_ready_in[FPU_DIVSQRT]), + .data_in (per_core_data_in[FPU_DIVSQRT]), + .data_out (div_sqrt_data_tmp_in), + .valid_out (div_sqrt_valid_tmp_in), + .ready_out (div_sqrt_ready_tmp_in) + ); + + wire is_sqrt = div_sqrt_data_tmp_in[0]; // op_type[0] + + VX_stream_switch #( + .DATAW (REQ_DATAW), + .NUM_INPUTS (1), + .NUM_OUTPUTS (2) + ) div_sqrt_req_switch ( + .clk (clk), + .reset (reset), + .sel_in (is_sqrt), + .valid_in (div_sqrt_valid_tmp_in), + .ready_in (div_sqrt_ready_tmp_in), + .data_in (div_sqrt_data_tmp_in), + .data_out (div_sqrt_data_in), + .valid_out (div_sqrt_valid_in), + .ready_out (div_sqrt_ready_in) + ); + + for (genvar i = 0; i < 2; ++i) begin : g_div_sqrt_data_in + assign { + div_sqrt_mask_in[i], + div_sqrt_tag_in[i], + div_sqrt_fmt[i], + div_sqrt_frm[i], + div_sqrt_dataa[i], + div_sqrt_datab[i], + div_sqrt_datac[i], + div_sqrt_op_type[i] + } = div_sqrt_data_in[i]; + end + + `UNUSED_VAR (div_sqrt_op_type) + `UNUSED_VAR (div_sqrt_fmt) + `UNUSED_VAR (div_sqrt_datab) + `UNUSED_VAR (div_sqrt_datac) + + VX_fpu_div #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH) + ) fpu_div ( + .clk (clk), + .reset (reset), + .valid_in (div_sqrt_valid_in[0]), + .ready_in (div_sqrt_ready_in[0]), + .mask_in (div_sqrt_mask_in[0]), + .tag_in (div_sqrt_tag_in[0]), + .frm (div_sqrt_frm[0]), + .dataa (div_sqrt_dataa[0]), + .datab (div_sqrt_datab[0]), + .has_fflags (div_sqrt_has_fflags[0]), + .fflags (div_sqrt_fflags[0]), + .result (div_sqrt_result[0]), + .tag_out (div_sqrt_tag_out[0]), + .valid_out (div_sqrt_valid_out[0]), + .ready_out (div_sqrt_ready_out[0]) + ); + + VX_fpu_sqrt #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH) + ) fpu_sqrt ( + .clk (clk), + .reset (reset), + .valid_in (div_sqrt_valid_in[1]), + .ready_in (div_sqrt_ready_in[1]), + .mask_in (div_sqrt_mask_in[1]), + .tag_in (div_sqrt_tag_in[1]), + .frm (div_sqrt_frm[1]), + .dataa (div_sqrt_dataa[1]), + .has_fflags (div_sqrt_has_fflags[1]), + .fflags (div_sqrt_fflags[1]), + .result (div_sqrt_result[1]), + .tag_out (div_sqrt_tag_out[1]), + .valid_out (div_sqrt_valid_out[1]), + .ready_out (div_sqrt_ready_out[1]) + ); + + wire [1:0][RSP_DATAW-1:0] div_sqrt_arb_data_in; + for (genvar i = 0; i < 2; ++i) begin : g_div_sqrt_arb_data_in + assign div_sqrt_arb_data_in[i] = { + div_sqrt_result[i], + div_sqrt_has_fflags[i], + div_sqrt_fflags[i], + div_sqrt_tag_out[i] + }; + end + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_DATAW), + .ARBITER ("P"), + .OUT_BUF (0) + ) div_sqrt_rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (div_sqrt_valid_out), + .ready_in (div_sqrt_ready_out), + .data_in (div_sqrt_arb_data_in), + .data_out ({ + per_core_result[FPU_DIVSQRT], + per_core_has_fflags[FPU_DIVSQRT], + per_core_fflags[FPU_DIVSQRT], + per_core_tag_out[FPU_DIVSQRT] + }), + .valid_out (per_core_valid_out[FPU_DIVSQRT]), + .ready_out (per_core_ready_out[FPU_DIVSQRT]), + `UNUSED_PIN (sel_out) + ); + + // CVT core /////////////////////////////////////////////////////////////// + + wire is_itof = per_core_op_type[FPU_CVT][1]; + wire is_signed = ~per_core_op_type[FPU_CVT][0]; + wire cvt_ret_int_in = ~is_itof; + wire cvt_ret_int_out; + + VX_fpu_cvt #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (1+TAG_WIDTH) + ) fpu_cvt ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_in[FPU_CVT]), + .ready_in (per_core_ready_in[FPU_CVT]), + .mask_in (per_core_mask_in[FPU_CVT]), + .tag_in ({cvt_ret_int_in, per_core_tag_in[FPU_CVT]}), + .frm (per_core_frm[FPU_CVT]), + .is_itof (is_itof), + .is_signed (is_signed), + .dataa (per_core_dataa[FPU_CVT]), + .has_fflags (per_core_has_fflags[FPU_CVT]), + .fflags (per_core_fflags[FPU_CVT]), + .result (per_core_result[FPU_CVT]), + .tag_out ({cvt_ret_int_out, per_core_tag_out[FPU_CVT]}), + .valid_out (per_core_valid_out[FPU_CVT]), + .ready_out (per_core_ready_out[FPU_CVT]) + ); + + // NCP core /////////////////////////////////////////////////////////////// + + wire ncp_ret_int_in = (per_core_op_type[FPU_NCP] == INST_FPU_CMP) + || inst_fpu_is_class(per_core_op_type[FPU_NCP], per_core_frm[FPU_NCP]) + || inst_fpu_is_mvxw(per_core_op_type[FPU_NCP], per_core_frm[FPU_NCP]); + wire ncp_ret_int_out; + + wire ncp_ret_sext_in = inst_fpu_is_mvxw(per_core_op_type[FPU_NCP], per_core_frm[FPU_NCP]); + wire ncp_ret_sext_out; + + VX_fpu_ncp #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH+2) + ) fpu_ncp ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_in[FPU_NCP]), + .ready_in (per_core_ready_in[FPU_NCP]), + .mask_in (per_core_mask_in[FPU_NCP]), + .tag_in ({ncp_ret_sext_in, ncp_ret_int_in, per_core_tag_in[FPU_NCP]}), + .op_type (per_core_op_type[FPU_NCP]), + .frm (per_core_frm[FPU_NCP]), + .dataa (per_core_dataa[FPU_NCP]), + .datab (per_core_datab[FPU_NCP]), + .result (per_core_result[FPU_NCP]), + .has_fflags (per_core_has_fflags[FPU_NCP]), + .fflags (per_core_fflags[FPU_NCP]), + .tag_out ({ncp_ret_sext_out, ncp_ret_int_out, per_core_tag_out[FPU_NCP]}), + .valid_out (per_core_valid_out[FPU_NCP]), + .ready_out (per_core_ready_out[FPU_NCP]) + ); + + /////////////////////////////////////////////////////////////////////////// + + reg [NUM_FPCORES-1:0][RSP_DATAW+2-1:0] per_core_data_out; + + always @(*) begin + for (integer i = 0; i < NUM_FPCORES; ++i) begin + per_core_data_out[i][RSP_DATAW+1:2] = { + per_core_result[i], + per_core_has_fflags[i], + per_core_fflags[i], + per_core_tag_out[i] + }; + per_core_data_out[i][1:0] = '0; + end + per_core_data_out[FPU_CVT][1:0] = {1'b1, cvt_ret_int_out}; + per_core_data_out[FPU_NCP][1:0] = {ncp_ret_sext_out, ncp_ret_int_out}; + end + + wire [NUM_LANES-1:0][31:0] result_s; + + wire [1:0] op_ret_int_out; + `UNUSED_VAR (op_ret_int_out) + + VX_stream_arb #( + .NUM_INPUTS (NUM_FPCORES), + .DATAW (RSP_DATAW + 2), + .ARBITER ("R"), + .OUT_BUF (OUT_BUF) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_core_valid_out), + .ready_in (per_core_ready_out), + .data_in (per_core_data_out), + .data_out ({result_s, has_fflags, fflags, tag_out, op_ret_int_out}), + .valid_out (valid_out), + .ready_out (ready_out), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + `ifdef FPU_RV64F + reg [`XLEN-1:0] result_w; + always @(*) begin + case (op_ret_int_out) + 2'b11: result_w = `XLEN'($signed(result_s[i])); + 2'b01: result_w = {32'h00000000, result_s[i]}; + default: result_w = {32'hffffffff, result_s[i]}; + endcase + end + assign result[i] = result_w; + `else + assign result[i] = result_s[i]; + `endif + end + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_fma.sv b/designs/src/vortex/rtl/fpu/VX_fpu_fma.sv new file mode 100644 index 0000000..d1ca9ef --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_fma.sv @@ -0,0 +1,214 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_fma import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES / `FMA_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire is_madd, + input wire is_sub, + input wire is_neg, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + input wire [NUM_LANES-1:0][31:0] datac, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam DATAW = 3 * 32 + INST_FRM_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + reg [NUM_LANES-1:0][31:0] a, b, c; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_select + always @(*) begin + if (is_madd) begin + // MADD / MSUB / NMADD / NMSUB + a[i] = {is_neg ^ dataa[i][31], dataa[i][30:0]}; + b[i] = datab[i]; + c[i] = {is_neg ^ is_sub ^ datac[i][31], datac[i][30:0]}; + end else begin + if (is_neg) begin + // MUL + a[i] = dataa[i]; + b[i] = datab[i]; + c[i] = '0; + end else begin + // ADD / SUB + a[i] = dataa[i]; + b[i] = 32'h3f800000; // 1.0f + c[i] = {is_sub ^ datab[i][31], datab[i][30:0]}; + end + end + end + end + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = a[i]; + assign data_in[i][32 +: 32] = b[i]; + assign data_in[i][64 +: 32] = c[i]; + assign data_in[i][96 +: INST_FRM_BITS] = frm; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FMA), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas + acl_fmadd fmadd ( + .clk (clk), + .areset (1'b0), + .en (pe_enable), + .a (pe_data_in[i][0 +: 32]), + .b (pe_data_in[i][32 +: 32]), + .c (pe_data_in[i][64 +: 32]), + .q (pe_data_out[i][0 +: 32]) + ); + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x; + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + +`elsif VIVADO + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas + wire [2:0] tuser; + + xil_fma fma ( + .aclk (clk), + .aclken (pe_enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (pe_data_in[i][0 +: 32]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (pe_data_in[i][32 +: 32]), + .s_axis_c_tvalid (1'b1), + .s_axis_c_tdata (pe_data_in[i][64 +: 32]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (pe_data_out[i][0 +: 32]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = {tuser[2], 1'b0, tuser[1], tuser[0], 1'b0}; + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`else + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fmas + reg [63:0] r; + `UNUSED_VAR (r) + fflags_t f; + + always @(*) begin + dpi_fmadd ( + pe_enable, + int'(0), + {32'hffffffff, pe_data_in[i][0 +: 32]}, // a + {32'hffffffff, pe_data_in[i][32 +: 32]}, // b + {32'hffffffff, pe_data_in[i][64 +: 32]}, // c + pe_data_in[0][96 +: INST_FRM_BITS], // frm + r, + f + ); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FMA) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (pe_enable), + .data_in ({f, r[31:0]}), + .data_out (pe_data_out[i]) + ); + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_fpnew.sv b/designs/src/vortex/rtl/fpu/VX_fpu_fpnew.sv new file mode 100644 index 0000000..da565c4 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_fpnew.sv @@ -0,0 +1,234 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_FPNEW + +module VX_fpu_fpnew + import VX_gpu_pkg::*; + import VX_fpu_pkg::*; + import fpnew_pkg::*; + import cf_math_pkg::*; + import defs_div_sqrt_mvp::*; +#( + parameter NUM_LANES = 1, + parameter TAG_WIDTH = 1, + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FPU_BITS-1:0] op_type, + input wire [INST_FMT_BITS-1:0] fmt, + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][`XLEN-1:0] dataa, + input wire [NUM_LANES-1:0][`XLEN-1:0] datab, + input wire [NUM_LANES-1:0][`XLEN-1:0] datac, + output wire [NUM_LANES-1:0][`XLEN-1:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam LATENCY_FDIVSQRT = `MAX(`LATENCY_FDIV, `LATENCY_FSQRT); + localparam RSP_DATAW = (NUM_LANES * `XLEN) + 1 + $bits(fflags_t) + TAG_WIDTH; + + localparam fpnew_pkg::fpu_features_t FPU_FEATURES = '{ + Width: unsigned'(`XLEN), + EnableVectors: 1'b0, + `ifdef XLEN_64 + EnableNanBox: 1'b1, + `ifdef FLEN_64 + FpFmtMask: 5'b11000, + `else + FpFmtMask: 5'b11000, // TODO: adding FP64 to fix CVT bug in FpNew + `endif + IntFmtMask: 4'b0011 + `else + EnableNanBox: 1'b0, + FpFmtMask: 5'b10000, + IntFmtMask: 4'b0010 + `endif + }; + + localparam fpnew_pkg::fpu_implementation_t FPU_IMPLEMENTATION = '{ + PipeRegs:'{'{`LATENCY_FMA, 0, 0, 0, 0}, // ADDMUL + '{default: unsigned'(LATENCY_FDIVSQRT)}, // DIVSQRT + '{default: `LATENCY_FNCP}, // NONCOMP + '{default: `LATENCY_FCVT}}, // CONV + UnitTypes:'{'{default: fpnew_pkg::PARALLEL}, // ADDMUL + '{default: fpnew_pkg::MERGED}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED}}, // CONV + PipeConfig: fpnew_pkg::DISTRIBUTED + }; + + wire fpu_ready_in, fpu_valid_in; + wire fpu_ready_out, fpu_valid_out; + + reg [TAG_WIDTH-1:0] fpu_tag_in, fpu_tag_out; + + logic [2:0][NUM_LANES-1:0][`XLEN-1:0] fpu_operands; + + wire [NUM_LANES-1:0][`XLEN-1:0] fpu_result; + fpnew_pkg::status_t fpu_status; + + fpnew_pkg::operation_e fpu_op; + reg [INST_FRM_BITS-1:0] fpu_rnd; + reg fpu_op_mod; + reg fpu_has_fflags, fpu_has_fflags_out; + fpnew_pkg::fp_format_e fpu_src_fmt, fpu_dst_fmt; + fpnew_pkg::int_format_e fpu_int_fmt; + + `UNUSED_VAR (fmt) + + always @(*) begin + fpu_op = fpnew_pkg::operation_e'('x); + fpu_rnd = frm; + fpu_op_mod = 0; + fpu_has_fflags = 1; + fpu_operands[0] = dataa; + fpu_operands[1] = datab; + fpu_operands[2] = datac; + fpu_dst_fmt = fpnew_pkg::FP32; + fpu_int_fmt = fpnew_pkg::INT32; + + `ifdef FLEN_64 + if (fmt[0]) begin + fpu_dst_fmt = fpnew_pkg::FP64; + end + `endif + + `ifdef XLEN_64 + if (fmt[1]) begin + fpu_int_fmt = fpnew_pkg::INT64; + end + `endif + + fpu_src_fmt = fpu_dst_fmt; + + case (op_type) + INST_FPU_ADD: begin + fpu_op = fpnew_pkg::ADD; + fpu_operands[1] = dataa; + fpu_operands[2] = datab; + fpu_op_mod = fmt[1]; // FADD or FSUB + end + INST_FPU_MUL: begin fpu_op = fpnew_pkg::MUL; end + INST_FPU_MADD: begin fpu_op = fpnew_pkg::FMADD; fpu_op_mod = fmt[1]; end + INST_FPU_NMADD: begin fpu_op = fpnew_pkg::FNMSUB; fpu_op_mod = ~fmt[1]; end + INST_FPU_DIV: begin fpu_op = fpnew_pkg::DIV; end + INST_FPU_SQRT: begin fpu_op = fpnew_pkg::SQRT; end + `ifdef FLEN_64 + INST_FPU_F2F: begin fpu_op = fpnew_pkg::F2F; fpu_src_fmt = fmt[0] ? fpnew_pkg::FP32 : fpnew_pkg::FP64; end + `endif + INST_FPU_F2I, + INST_FPU_F2U: begin fpu_op = fpnew_pkg::F2I; fpu_op_mod = op_type[0]; end + INST_FPU_I2F, + INST_FPU_U2F: begin fpu_op = fpnew_pkg::I2F; fpu_op_mod = op_type[0]; end + INST_FPU_CMP: begin fpu_op = fpnew_pkg::CMP; end + INST_FPU_MISC:begin + case (frm) + 0,1,2: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = {1'b0, frm[1:0]}; fpu_has_fflags = 0; end // FSGNJ + 3: begin fpu_op = fpnew_pkg::CLASSIFY; fpu_has_fflags = 0; end // CLASS + 4,5: begin fpu_op = fpnew_pkg::SGNJ; fpu_rnd = 3'b011; fpu_op_mod = ~frm[0]; fpu_has_fflags = 0; end // FMV.X.W, FMV.W.X + 6,7: begin fpu_op = fpnew_pkg::MINMAX; fpu_rnd = {2'b00, frm[0]}; end // MIN, MAX + endcase + end + default:; + endcase + end + + `UNUSED_VAR (mask_in) + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_fpnew_coreses + wire [(TAG_WIDTH+1)-1:0] fpu_tag; + wire fpu_valid_out_uq; + wire fpu_ready_in_uq; + fpnew_pkg::status_t fpu_status_uq; + `UNUSED_VAR (fpu_tag) + `UNUSED_VAR (fpu_valid_out_uq) + `UNUSED_VAR (fpu_ready_in_uq) + `UNUSED_VAR (fpu_status_uq) + + fpnew_top #( + .Features (FPU_FEATURES), + .Implementation (FPU_IMPLEMENTATION), + .TagType (logic[(TAG_WIDTH+1)-1:0]), + .DivSqrtSel (fpnew_pkg::PULP) + ) fpnew_core ( + .clk_i (clk), + .rst_ni (~reset), + .operands_i ({fpu_operands[2][i], fpu_operands[1][i], fpu_operands[0][i]}), + .rnd_mode_i (fpnew_pkg::roundmode_e'(fpu_rnd)), + .op_i (fpu_op), + .op_mod_i (fpu_op_mod), + .src_fmt_i (fpu_src_fmt), + .dst_fmt_i (fpu_dst_fmt), + .int_fmt_i (fpu_int_fmt), + .vectorial_op_i (1'b0), + .simd_mask_i (1'b1), + .tag_i ({fpu_tag_in, fpu_has_fflags}), + .in_valid_i (fpu_valid_in), + .in_ready_o (fpu_ready_in_uq), + .flush_i (1'b0), + .result_o (fpu_result[i]), + .status_o (fpu_status_uq), + .tag_o (fpu_tag), + .out_valid_o (fpu_valid_out_uq), + .out_ready_i (fpu_ready_out), + `UNUSED_PIN (busy_o) + ); + + if (i == 0) begin : g_output_0 + assign {fpu_tag_out, fpu_has_fflags_out} = fpu_tag; + assign fpu_valid_out = fpu_valid_out_uq; + assign fpu_ready_in = fpu_ready_in_uq; + assign fpu_status = fpu_status_uq; + end + end + + assign fpu_valid_in = valid_in; + assign ready_in = fpu_ready_in; + assign fpu_tag_in = tag_in; + + VX_elastic_buffer #( + .DATAW (RSP_DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (fpu_valid_out), + .ready_in (fpu_ready_out), + .data_in ({fpu_result, fpu_has_fflags_out, fpu_status, fpu_tag_out}), + .data_out ({result, has_fflags, fflags, tag_out}), + .valid_out (valid_out), + .ready_out (ready_out) + ); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_ncp.sv b/designs/src/vortex/rtl/fpu/VX_fpu_ncp.sv new file mode 100644 index 0000000..fae23db --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_ncp.sv @@ -0,0 +1,122 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_ncp import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES / `FNCP_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FPU_BITS-1:0] op_type, + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + input wire [NUM_LANES-1:0][31:0] datab, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam DATAW = 2 * 32 + INST_FRM_BITS + INST_FPU_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + fflags_t [NUM_LANES-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = dataa[i]; + assign data_in[i][32 +: 32] = datab[i]; + assign data_in[i][64 +: INST_FRM_BITS] = frm; + assign data_in[i][64 + INST_FRM_BITS +: INST_FPU_BITS] = op_type; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FNCP), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fncp_units + VX_fncp_unit #( + .LATENCY (`LATENCY_FNCP), + .OUT_REG (1) + ) fncp_unit ( + .clk (clk), + .reset (reset), + .enable (pe_enable), + .frm (pe_data_in[0][64 +: INST_FRM_BITS]), + .op_type (pe_data_in[0][64 + INST_FRM_BITS +: INST_FPU_BITS]), + .dataa (pe_data_in[i][0 +: 32]), + .datab (pe_data_in[i][32 +: 32]), + .result (pe_data_out[i][0 +: 32]), + .fflags (pe_data_out[i][32 +: `FP_FLAGS_BITS]) + ); + end + + assign has_fflags = 1; + + `FPU_MERGE_FFLAGS(fflags, fflags_out, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_pkg.sv b/designs/src/vortex/rtl/fpu/VX_fpu_pkg.sv new file mode 100644 index 0000000..be2dd66 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_pkg.sv @@ -0,0 +1,46 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_FPU_PKG_VH +`define VX_FPU_PKG_VH + +`include "VX_define.vh" + +package VX_fpu_pkg; + + import VX_gpu_pkg::*; + + typedef struct packed { + logic is_normal; + logic is_zero; + logic is_subnormal; + logic is_inf; + logic is_nan; + logic is_quiet; + logic is_signaling; + } fclass_t; + + typedef struct packed { + logic NV; // 4-Invalid + logic DZ; // 3-Divide by zero + logic OF; // 2-Overflow + logic UF; // 1-Underflow + logic NX; // 0-Inexact + } fflags_t; + + `DECL_EXECUTE_T (fpu_exe_t, `NUM_FPU_LANES); + `DECL_RESULT_T (fpu_res_t, `NUM_FPU_LANES); + +endpackage + +`endif // VX_FPU_PKG_VH diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_sqrt.sv b/designs/src/vortex/rtl/fpu/VX_fpu_sqrt.sv new file mode 100644 index 0000000..631790f --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_sqrt.sv @@ -0,0 +1,174 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +`ifdef FPU_DSP + +module VX_fpu_sqrt import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter NUM_PES = `UP(NUM_LANES /`FSQRT_PE_RATIO), + parameter TAG_WIDTH = 1 +) ( + input wire clk, + input wire reset, + + output wire ready_in, + input wire valid_in, + + input wire [NUM_LANES-1:0] mask_in, + + input wire [TAG_WIDTH-1:0] tag_in, + + input wire [INST_FRM_BITS-1:0] frm, + + input wire [NUM_LANES-1:0][31:0] dataa, + output wire [NUM_LANES-1:0][31:0] result, + + output wire has_fflags, + output wire [`FP_FLAGS_BITS-1:0] fflags, + + output wire [TAG_WIDTH-1:0] tag_out, + + input wire ready_out, + output wire valid_out +); + localparam DATAW = 32 + INST_FRM_BITS; + + wire [NUM_LANES-1:0][DATAW-1:0] data_in; + + wire [NUM_LANES-1:0] mask_out; + wire [NUM_LANES-1:0][(`FP_FLAGS_BITS+32)-1:0] data_out; + wire [NUM_LANES-1:0][`FP_FLAGS_BITS-1:0] fflags_out; + + wire pe_enable; + wire [NUM_PES-1:0][DATAW-1:0] pe_data_in; + wire [NUM_PES-1:0][(`FP_FLAGS_BITS+32)-1:0] pe_data_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_data_in + assign data_in[i][0 +: 32] = dataa[i]; + assign data_in[i][32 +: INST_FRM_BITS] = frm; + end + + VX_pe_serializer #( + .NUM_LANES (NUM_LANES), + .NUM_PES (NUM_PES), + .LATENCY (`LATENCY_FSQRT), + .DATA_IN_WIDTH (DATAW), + .DATA_OUT_WIDTH (`FP_FLAGS_BITS + 32), + .TAG_WIDTH (NUM_LANES + TAG_WIDTH), + .PE_REG (0), + .OUT_BUF (2) + ) pe_serializer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .tag_in ({mask_in, tag_in}), + .ready_in (ready_in), + .pe_enable (pe_enable), + .pe_data_out(pe_data_in), + .pe_data_in (pe_data_out), + .valid_out (valid_out), + .data_out (data_out), + .tag_out ({mask_out, tag_out}), + .ready_out (ready_out) + ); + + `UNUSED_VAR (pe_data_in) + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_result + assign result[i] = data_out[i][0 +: 32]; + assign fflags_out[i] = data_out[i][32 +: `FP_FLAGS_BITS]; + end + + fflags_t [NUM_LANES-1:0] per_lane_fflags; + +`ifdef QUARTUS + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts + acl_fsqrt fsqrt ( + .clk (clk), + .areset (1'b0), + .en (pe_enable), + .a (pe_data_in[i][0 +: 32]), + .q (pe_data_out[i][0 +: 32]) + ); + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = 'x; + end + + assign has_fflags = 0; + assign per_lane_fflags = 'x; + `UNUSED_VAR (fflags_out) + +`elsif VIVADO + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts + wire tuser; + + xil_fsqrt fsqrt ( + .aclk (clk), + .aclken (pe_enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (pe_data_in[i][0 +: 32]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (pe_data_out[i][0 +: 32]), + .m_axis_result_tuser (tuser) + ); + // NV, DZ, OF, UF, NX + assign pe_data_out[i][32 +: `FP_FLAGS_BITS] = {tuser, 1'b0, 1'b0, 1'b0, 1'b0}; + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`else + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_fsqrts + reg [63:0] r; + `UNUSED_VAR (r) + fflags_t f; + + always @(*) begin + dpi_fsqrt ( + pe_enable, + int'(0), + {32'hffffffff, pe_data_in[i][0 +: 32]}, // a + pe_data_in[0][32 +: INST_FRM_BITS], // frm + r, + f + ); + end + + VX_shift_register #( + .DATAW (32 + $bits(fflags_t)), + .DEPTH (`LATENCY_FSQRT) + ) shift_req_dpi ( + .clk (clk), + `UNUSED_PIN (reset), + .enable (pe_enable), + .data_in ({f, r[31:0]}), + .data_out (pe_data_out[i]) + ); + end + + assign has_fflags = 1; + assign per_lane_fflags = fflags_out; + +`endif + +`FPU_MERGE_FFLAGS(fflags, per_lane_fflags, mask_out, NUM_LANES); + +endmodule + +`endif diff --git a/designs/src/vortex/rtl/fpu/VX_fpu_unit.sv b/designs/src/vortex/rtl/fpu/VX_fpu_unit.sv new file mode 100644 index 0000000..3c30f93 --- /dev/null +++ b/designs/src/vortex/rtl/fpu/VX_fpu_unit.sv @@ -0,0 +1,276 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_fpu_define.vh" + +module VX_fpu_unit import VX_gpu_pkg::*, VX_fpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH], + VX_fpu_csr_if.master fpu_csr_if[`NUM_FPU_BLOCKS] +); + `UNUSED_SPARAM (INSTANCE_ID) + localparam BLOCK_SIZE = `NUM_FPU_BLOCKS; + localparam NUM_LANES = `NUM_FPU_LANES; + localparam PID_BITS = `CLOG2(`NUM_THREADS / NUM_LANES); + localparam PID_WIDTH = `UP(PID_BITS); + localparam TAG_WIDTH = `LOG2UP(`FPUQ_SIZE); + localparam IBUF_DATAW = UUID_WIDTH + NW_WIDTH + NUM_LANES + PC_BITS + NUM_REGS_BITS + PID_WIDTH + 1 + 1; + localparam PARTIAL_BW = (BLOCK_SIZE != `ISSUE_WIDTH) || (NUM_LANES != `SIMD_WIDTH); + + VX_execute_if #( + .data_t (fpu_exe_t) + ) per_block_execute_if[BLOCK_SIZE](); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (PARTIAL_BW ? 3 : 0) + ) dispatch_unit ( + .clk (clk), + .reset (reset), + .dispatch_if(dispatch_if), + .execute_if (per_block_execute_if) + ); + + VX_result_if #( + .data_t (fpu_res_t) + ) per_block_result_if[BLOCK_SIZE](); + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_blocks + `UNUSED_VAR (per_block_execute_if[block_idx].data.wb) + + // Store request info + wire fpu_req_valid, fpu_req_ready; + wire fpu_rsp_valid, fpu_rsp_ready; + wire [NUM_LANES-1:0][`XLEN-1:0] fpu_rsp_result; + fflags_t fpu_rsp_fflags; + wire fpu_rsp_has_fflags; + + wire [UUID_WIDTH-1:0] fpu_rsp_uuid; + wire [NW_WIDTH-1:0] fpu_rsp_wid; + wire [NUM_LANES-1:0] fpu_rsp_tmask; + wire [PC_BITS-1:0] fpu_rsp_PC; + wire [NUM_REGS_BITS-1:0] fpu_rsp_rd; + wire [PID_WIDTH-1:0] fpu_rsp_pid, fpu_rsp_pid_u; + wire fpu_rsp_sop, fpu_rsp_sop_u; + wire fpu_rsp_eop, fpu_rsp_eop_u; + + wire [TAG_WIDTH-1:0] fpu_req_tag, fpu_rsp_tag; + wire mdata_full; + + wire [INST_FMT_BITS-1:0] fpu_fmt = per_block_execute_if[block_idx].data.op_args.fpu.fmt; + wire [INST_FRM_BITS-1:0] fpu_frm = per_block_execute_if[block_idx].data.op_args.fpu.frm; + + wire execute_fire = per_block_execute_if[block_idx].valid && per_block_execute_if[block_idx].ready; + wire fpu_rsp_fire = fpu_rsp_valid && fpu_rsp_ready; + + VX_index_buffer #( + .DATAW (IBUF_DATAW), + .SIZE (`FPUQ_SIZE) + ) tag_store ( + .clk (clk), + .reset (reset), + .acquire_en (execute_fire), + .write_addr (fpu_req_tag), + .write_data ({per_block_execute_if[block_idx].data.uuid, per_block_execute_if[block_idx].data.wid, per_block_execute_if[block_idx].data.tmask, per_block_execute_if[block_idx].data.PC, per_block_execute_if[block_idx].data.rd, per_block_execute_if[block_idx].data.pid, per_block_execute_if[block_idx].data.sop, per_block_execute_if[block_idx].data.eop}), + .read_data ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_pid_u, fpu_rsp_sop_u, fpu_rsp_eop_u}), + .read_addr (fpu_rsp_tag), + .release_en (fpu_rsp_fire), + .full (mdata_full), + `UNUSED_PIN (empty) + ); + + if (PID_BITS != 0) begin : g_fpu_rsp_pid + assign fpu_rsp_pid = fpu_rsp_pid_u; + assign fpu_rsp_sop = fpu_rsp_sop_u; + assign fpu_rsp_eop = fpu_rsp_eop_u; + end else begin : g_fpu_rsp_no_pid + `UNUSED_VAR (fpu_rsp_pid_u) + `UNUSED_VAR (fpu_rsp_sop_u) + `UNUSED_VAR (fpu_rsp_eop_u) + assign fpu_rsp_pid = 0; + assign fpu_rsp_sop = 1; + assign fpu_rsp_eop = 1; + end + + // resolve dynamic FRM from CSR + wire [INST_FRM_BITS-1:0] fpu_req_frm; + `ASSIGN_BLOCKED_WID (fpu_csr_if[block_idx].read_wid, per_block_execute_if[block_idx].data.wid, block_idx, `NUM_FPU_BLOCKS) + assign fpu_req_frm = (per_block_execute_if[block_idx].data.op_type != INST_FPU_MISC + && fpu_frm == INST_FRM_DYN) ? fpu_csr_if[block_idx].read_frm : fpu_frm; + + // submit FPU request + + assign fpu_req_valid = per_block_execute_if[block_idx].valid && ~mdata_full; + assign per_block_execute_if[block_idx].ready = fpu_req_ready && ~mdata_full; + + `ifdef FPU_DPI + + VX_fpu_dpi #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH), + .OUT_BUF (PARTIAL_BW ? 1 : 3) + ) fpu_dpi ( + .clk (clk), + .reset (reset), + + .valid_in (fpu_req_valid), + .mask_in (per_block_execute_if[block_idx].data.tmask), + .op_type (per_block_execute_if[block_idx].data.op_type), + .fmt (fpu_fmt), + .frm (fpu_req_frm), + .dataa (per_block_execute_if[block_idx].data.rs1_data), + .datab (per_block_execute_if[block_idx].data.rs2_data), + .datac (per_block_execute_if[block_idx].data.rs3_data), + .tag_in (fpu_req_tag), + .ready_in (fpu_req_ready), + + .valid_out (fpu_rsp_valid), + .result (fpu_rsp_result), + .has_fflags (fpu_rsp_has_fflags), + .fflags (fpu_rsp_fflags), + .tag_out (fpu_rsp_tag), + .ready_out (fpu_rsp_ready) + ); + + `elsif FPU_FPNEW + + VX_fpu_fpnew #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH), + .OUT_BUF (PARTIAL_BW ? 1 : 3) + ) fpu_fpnew ( + .clk (clk), + .reset (reset), + + .valid_in (fpu_req_valid), + .mask_in (per_block_execute_if[block_idx].data.tmask), + .op_type (per_block_execute_if[block_idx].data.op_type), + .fmt (fpu_fmt), + .frm (fpu_req_frm), + .dataa (per_block_execute_if[block_idx].data.rs1_data), + .datab (per_block_execute_if[block_idx].data.rs2_data), + .datac (per_block_execute_if[block_idx].data.rs3_data), + .tag_in (fpu_req_tag), + .ready_in (fpu_req_ready), + + .valid_out (fpu_rsp_valid), + .result (fpu_rsp_result), + .has_fflags (fpu_rsp_has_fflags), + .fflags (fpu_rsp_fflags), + .tag_out (fpu_rsp_tag), + .ready_out (fpu_rsp_ready) + ); + + `elsif FPU_DSP + + VX_fpu_dsp #( + .NUM_LANES (NUM_LANES), + .TAG_WIDTH (TAG_WIDTH), + .OUT_BUF (PARTIAL_BW ? 1 : 3) + ) fpu_dsp ( + .clk (clk), + .reset (reset), + + .valid_in (fpu_req_valid), + .mask_in (per_block_execute_if[block_idx].data.tmask), + .op_type (per_block_execute_if[block_idx].data.op_type), + .fmt (fpu_fmt), + .frm (fpu_req_frm), + .dataa (per_block_execute_if[block_idx].data.rs1_data), + .datab (per_block_execute_if[block_idx].data.rs2_data), + .datac (per_block_execute_if[block_idx].data.rs3_data), + .tag_in (fpu_req_tag), + .ready_in (fpu_req_ready), + + .valid_out (fpu_rsp_valid), + .result (fpu_rsp_result), + .has_fflags (fpu_rsp_has_fflags), + .fflags (fpu_rsp_fflags), + .tag_out (fpu_rsp_tag), + .ready_out (fpu_rsp_ready) + ); + + `endif + + // handle CSR update + fflags_t fpu_rsp_fflags_q; + + if (PID_BITS != 0) begin : g_fflags_pid + fflags_t fpu_rsp_fflags_r; + always @(posedge clk) begin + if (reset) begin + fpu_rsp_fflags_r <= '0; + end else if (fpu_rsp_fire) begin + fpu_rsp_fflags_r <= fpu_rsp_eop ? '0 : (fpu_rsp_fflags_r | fpu_rsp_fflags); + end + end + assign fpu_rsp_fflags_q = fpu_rsp_fflags_r | fpu_rsp_fflags; + end else begin : g_fflags_no_pid + assign fpu_rsp_fflags_q = fpu_rsp_fflags; + end + + VX_fpu_csr_if fpu_csr_tmp_if(); + assign fpu_csr_tmp_if.write_enable = fpu_rsp_fire && fpu_rsp_eop && fpu_rsp_has_fflags; + `ASSIGN_BLOCKED_WID (fpu_csr_tmp_if.write_wid, fpu_rsp_wid, block_idx, `NUM_FPU_BLOCKS) + assign fpu_csr_tmp_if.write_fflags = fpu_rsp_fflags_q; + + VX_pipe_register #( + .DATAW (1 + NW_WIDTH + $bits(fflags_t)), + .RESETW (1) + ) fpu_csr_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({fpu_csr_tmp_if.write_enable, fpu_csr_tmp_if.write_wid, fpu_csr_tmp_if.write_fflags}), + .data_out ({fpu_csr_if[block_idx].write_enable, fpu_csr_if[block_idx].write_wid, fpu_csr_if[block_idx].write_fflags}) + ); + + // send response + + VX_elastic_buffer #( + .DATAW (IBUF_DATAW + (NUM_LANES * `XLEN)), + .SIZE (0) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (fpu_rsp_valid), + .ready_in (fpu_rsp_ready), + .data_in ({fpu_rsp_uuid, fpu_rsp_wid, fpu_rsp_tmask, fpu_rsp_PC, fpu_rsp_rd, fpu_rsp_pid, fpu_rsp_sop, fpu_rsp_eop, fpu_rsp_result}), + .data_out ({per_block_result_if[block_idx].data.uuid, per_block_result_if[block_idx].data.wid, per_block_result_if[block_idx].data.tmask, per_block_result_if[block_idx].data.PC, per_block_result_if[block_idx].data.rd, per_block_result_if[block_idx].data.pid, per_block_result_if[block_idx].data.sop, per_block_result_if[block_idx].data.eop, per_block_result_if[block_idx].data.data}), + .valid_out (per_block_result_if[block_idx].valid), + .ready_out (per_block_result_if[block_idx].ready) + ); + assign per_block_result_if[block_idx].data.wb = 1'b1; + end + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (PARTIAL_BW ? 3 : 0) + ) gather_unit ( + .clk (clk), + .reset (reset), + .result_if (per_block_result_if), + .commit_if (commit_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/interfaces/VX_branch_ctl_if.sv b/designs/src/vortex/rtl/interfaces/VX_branch_ctl_if.sv new file mode 100644 index 0000000..c52af73 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_branch_ctl_if.sv @@ -0,0 +1,37 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_branch_ctl_if import VX_gpu_pkg::*; (); + + wire valid; + wire [NW_WIDTH-1:0] wid; + wire taken; + wire [PC_BITS-1:0] dest; + + modport master ( + output valid, + output wid, + output taken, + output dest + ); + + modport slave ( + input valid, + input wid, + input taken, + input dest + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_commit_csr_if.sv b/designs/src/vortex/rtl/interfaces/VX_commit_csr_if.sv new file mode 100644 index 0000000..f896437 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_commit_csr_if.sv @@ -0,0 +1,28 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_commit_csr_if import VX_gpu_pkg::*; (); + + wire [PERF_CTR_BITS-1:0] instret; + + modport master ( + output instret + ); + + modport slave ( + input instret + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_commit_if.sv b/designs/src/vortex/rtl/interfaces/VX_commit_if.sv new file mode 100644 index 0000000..d0a98d2 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_commit_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_commit_if import VX_gpu_pkg::*; (); + + logic valid; + commit_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_commit_sched_if.sv b/designs/src/vortex/rtl/interfaces/VX_commit_sched_if.sv new file mode 100644 index 0000000..eab794c --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_commit_sched_if.sv @@ -0,0 +1,28 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_commit_sched_if (); + + wire [`NUM_WARPS-1:0] committed_warps; + + modport master ( + output committed_warps + ); + + modport slave ( + input committed_warps + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_dcr_bus_if.sv b/designs/src/vortex/rtl/interfaces/VX_dcr_bus_if.sv new file mode 100644 index 0000000..9640861 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_dcr_bus_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_dcr_bus_if import VX_gpu_pkg::*; (); + + wire write_valid; + wire [VX_DCR_ADDR_WIDTH-1:0] write_addr; + wire [VX_DCR_DATA_WIDTH-1:0] write_data; + + modport master ( + output write_valid, + output write_addr, + output write_data + ); + + modport slave ( + input write_valid, + input write_addr, + input write_data + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_decode_if.sv b/designs/src/vortex/rtl/interfaces/VX_decode_if.sv new file mode 100644 index 0000000..c0827a1 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_decode_if.sv @@ -0,0 +1,42 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_decode_if import VX_gpu_pkg::*; (); + logic valid; + decode_t data; + logic ready; +`ifndef L1_ENABLE + wire [`NUM_WARPS-1:0] ibuf_pop; +`endif + + modport master ( + output valid, + output data, + input ready + `ifndef L1_ENABLE + , input ibuf_pop + `endif + ); + + modport slave ( + input valid, + input data, + output ready + `ifndef L1_ENABLE + , output ibuf_pop + `endif + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_decode_sched_if.sv b/designs/src/vortex/rtl/interfaces/VX_decode_sched_if.sv new file mode 100644 index 0000000..0dc1dcb --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_decode_sched_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_decode_sched_if import VX_gpu_pkg::*; (); + + wire valid; + wire unlock; + wire [NW_WIDTH-1:0] wid; + + modport master ( + output valid, + output unlock, + output wid + ); + + modport slave ( + input valid, + input unlock, + input wid + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_dispatch_if.sv b/designs/src/vortex/rtl/interfaces/VX_dispatch_if.sv new file mode 100644 index 0000000..d4aa388 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_dispatch_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_dispatch_if import VX_gpu_pkg::*; (); + + logic valid; + dispatch_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_execute_if.sv b/designs/src/vortex/rtl/interfaces/VX_execute_if.sv new file mode 100644 index 0000000..55e0aef --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_execute_if.sv @@ -0,0 +1,35 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_execute_if import VX_gpu_pkg::*; #( + parameter type data_t = logic +); + logic valid; + data_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_fetch_if.sv b/designs/src/vortex/rtl/interfaces/VX_fetch_if.sv new file mode 100644 index 0000000..e4c84b2 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_fetch_if.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_fetch_if import VX_gpu_pkg::*; (); + + logic valid; + fetch_t data; + logic ready; +`ifndef L1_ENABLE + logic [`NUM_WARPS-1:0] ibuf_pop; +`endif + + modport master ( + output valid, + output data, + input ready + `ifndef L1_ENABLE + , input ibuf_pop + `endif + ); + + modport slave ( + input valid, + input data, + output ready + `ifndef L1_ENABLE + , output ibuf_pop + `endif + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_ibuffer_if.sv b/designs/src/vortex/rtl/interfaces/VX_ibuffer_if.sv new file mode 100644 index 0000000..4da4234 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_ibuffer_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_ibuffer_if import VX_gpu_pkg::*; (); + + logic valid; + ibuffer_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_issue_sched_if.sv b/designs/src/vortex/rtl/interfaces/VX_issue_sched_if.sv new file mode 100644 index 0000000..20b2e40 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_issue_sched_if.sv @@ -0,0 +1,31 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_issue_sched_if import VX_gpu_pkg::*; (); + + wire [ISSUE_WIS_W-1:0] wis; + wire valid; + + modport master ( + output valid, + output wis + ); + + modport slave ( + input valid, + input wis + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_operands_if.sv b/designs/src/vortex/rtl/interfaces/VX_operands_if.sv new file mode 100644 index 0000000..8bc97ab --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_operands_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_operands_if import VX_gpu_pkg::*; (); + + logic valid; + operands_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_result_if.sv b/designs/src/vortex/rtl/interfaces/VX_result_if.sv new file mode 100644 index 0000000..3a8dd66 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_result_if.sv @@ -0,0 +1,36 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_result_if import VX_gpu_pkg::*; #( + parameter type data_t = logic +) (); + + logic valid; + data_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_sched_csr_if.sv b/designs/src/vortex/rtl/interfaces/VX_sched_csr_if.sv new file mode 100644 index 0000000..a31e00c --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_sched_csr_if.sv @@ -0,0 +1,46 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_sched_csr_if import VX_gpu_pkg::*; (); + + wire [PERF_CTR_BITS-1:0] cycles; + wire [`NUM_WARPS-1:0] active_warps; + wire [`NUM_WARPS-1:0][`NUM_THREADS-1:0] thread_masks; + wire alm_empty; + wire [NW_WIDTH-1:0] alm_empty_wid; + wire unlock_warp; + wire [NW_WIDTH-1:0] unlock_wid; + + modport master ( + output cycles, + output active_warps, + output thread_masks, + input alm_empty_wid, + output alm_empty, + input unlock_wid, + input unlock_warp + ); + + modport slave ( + input cycles, + input active_warps, + input thread_masks, + output alm_empty_wid, + input alm_empty, + output unlock_wid, + output unlock_warp + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_schedule_if.sv b/designs/src/vortex/rtl/interfaces/VX_schedule_if.sv new file mode 100644 index 0000000..2d4587e --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_schedule_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_schedule_if import VX_gpu_pkg::*; (); + + logic valid; + schedule_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_scoreboard_if.sv b/designs/src/vortex/rtl/interfaces/VX_scoreboard_if.sv new file mode 100644 index 0000000..bf77083 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_scoreboard_if.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_scoreboard_if import VX_gpu_pkg::*; (); + + logic valid; + scoreboard_t data; + logic ready; + + modport master ( + output valid, + output data, + input ready + ); + + modport slave ( + input valid, + input data, + output ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_warp_ctl_if.sv b/designs/src/vortex/rtl/interfaces/VX_warp_ctl_if.sv new file mode 100644 index 0000000..5bc3019 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_warp_ctl_if.sv @@ -0,0 +1,55 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_warp_ctl_if import VX_gpu_pkg::*; (); + + wire valid; + wire [NW_WIDTH-1:0] wid; + tmc_t tmc; + wspawn_t wspawn; + split_t split; + join_t sjoin; + barrier_t barrier; + + wire [NW_WIDTH-1:0] dvstack_wid; + wire [DV_STACK_SIZEW-1:0] dvstack_ptr; + + modport master ( + output valid, + output wid, + output wspawn, + output tmc, + output split, + output sjoin, + output barrier, + + output dvstack_wid, + input dvstack_ptr + ); + + modport slave ( + input valid, + input wid, + input wspawn, + input tmc, + input split, + input sjoin, + input barrier, + + input dvstack_wid, + output dvstack_ptr + ); + +endinterface diff --git a/designs/src/vortex/rtl/interfaces/VX_writeback_if.sv b/designs/src/vortex/rtl/interfaces/VX_writeback_if.sv new file mode 100644 index 0000000..3ea5c72 --- /dev/null +++ b/designs/src/vortex/rtl/interfaces/VX_writeback_if.sv @@ -0,0 +1,31 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_writeback_if import VX_gpu_pkg::*; (); + + logic valid; + writeback_t data; + + modport master ( + output valid, + output data + ); + + modport slave ( + input valid, + input data + ); + +endinterface diff --git a/designs/src/vortex/rtl/libs/VX_allocator.sv b/designs/src/vortex/rtl/libs/VX_allocator.sv new file mode 100644 index 0000000..67a8fc8 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_allocator.sv @@ -0,0 +1,87 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_allocator #( + parameter SIZE = 1, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + + input wire acquire_en, + output wire [ADDRW-1:0] acquire_addr, + + input wire release_en, + input wire [ADDRW-1:0] release_addr, + + output wire empty, + output wire full +); + reg [SIZE-1:0] free_slots, free_slots_n; + reg [ADDRW-1:0] acquire_addr_r; + reg empty_r, full_r; + wire [ADDRW-1:0] free_index; + wire free_valid; + + always @(*) begin + free_slots_n = free_slots; + if (release_en) begin + free_slots_n[release_addr] = 1; + end + if (acquire_en) begin + free_slots_n[acquire_addr_r] = 0; + end + end + + VX_priority_encoder #( + .N (SIZE) + ) free_slots_sel ( + .data_in (free_slots_n), + .index_out (free_index), + .valid_out (free_valid), + `UNUSED_PIN (onehot_out) + ); + + always @(posedge clk) begin + if (reset) begin + acquire_addr_r <= ADDRW'(1'b0); + free_slots <= {SIZE{1'b1}}; + empty_r <= 1'b1; + full_r <= 1'b0; + end else begin + if (release_en) begin + `ASSERT(0 == free_slots[release_addr], ("%t: releasing invalid addr %d", $time, release_addr)); + end + if (acquire_en) begin + `ASSERT(~full_r, ("%t: allocator is full", $time)); + end + + if (acquire_en || (release_en && full_r)) begin + acquire_addr_r <= free_index; + end + + free_slots <= free_slots_n; + empty_r <= (& free_slots_n); + full_r <= ~free_valid; + end + end + + assign acquire_addr = acquire_addr_r; + assign empty = empty_r; + assign full = full_r; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_async_ram_patch.sv b/designs/src/vortex/rtl/libs/VX_async_ram_patch.sv new file mode 100644 index 0000000..dd4d2b4 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_async_ram_patch.sv @@ -0,0 +1,277 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE != 0) begin : g_init \ + if (INIT_FILE != "") begin : g_file \ + initial $readmemh(INIT_FILE, ram); \ + end else begin : g_value \ + initial begin \ + for (integer i = 0; i < SIZE; ++i) begin : g_i \ + ram[i] = INIT_VALUE; \ + end \ + end \ + end \ + end + +`define SYNC_RAM_WF_BLOCK(__d, __re, __we, __ra, __wa) \ + `RAM_ATTRIBUTES `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; \ + `RAM_INITIALIZATION \ + reg [ADDRW-1:0] raddr_r; \ + always @(posedge clk) begin \ + if (__we) begin \ + ram[__wa] <= wdata; \ + end \ + if (__re) begin \ + raddr_r <= __ra; \ + end \ + end \ + assign __d = ram[raddr_r] + +`define SYNC_RAM_WF_WREN_BLOCK(__d, __re, __we, __ra, __wa) \ + `RAM_ATTRIBUTES `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; \ + `RAM_INITIALIZATION \ + reg [ADDRW-1:0] raddr_r; \ + always @(posedge clk) begin \ + if (__we) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end \ + if (__re) begin \ + raddr_r <= __ra; \ + end \ + end \ + assign __d = ram[raddr_r] + +`define SYNC_RAM_RF_BLOCK(__d, __re, __we, __ra, __wa) \ + `RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \ + `RAM_INITIALIZATION \ + reg [DATAW-1:0] rdata_r; \ + always @(posedge clk) begin \ + if (__we) begin \ + ram[__wa] <= wdata; \ + end \ + if (__re) begin \ + rdata_r <= ram[__ra]; \ + end \ + end \ + assign __d = rdata_r + +`define SYNC_RAM_RF_WREN_BLOCK(__d, __re, __we, __ra, __wa) \ + `RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \ + `RAM_INITIALIZATION \ + reg [DATAW-1:0] rdata_r; \ + always @(posedge clk) begin \ + if (__we) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end \ + if (__re) begin \ + rdata_r <= ram[__ra]; \ + end \ + end \ + assign __d = rdata_r + +`define ASYNC_RAM_BLOCK(__d, __we, __ra, __wa) \ + `RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \ + `RAM_INITIALIZATION \ + always @(posedge clk) begin \ + if (__we) begin \ + ram[__wa] <= wdata; \ + end \ + end \ + assign __d = ram[__ra] + +`define ASYNC_RAM_BLOCK_WREN(__d, __we, __ra, __wa) \ + `RAM_ATTRIBUTES reg [DATAW-1:0] ram [0:SIZE-1]; \ + `RAM_INITIALIZATION \ + always @(posedge clk) begin \ + if (__we) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[__wa][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end \ + end \ + assign __d = ram[__ra] + +`TRACING_OFF +module VX_async_ram_patch #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter WRENW = 1, + parameter DUAL_PORT = 0, + parameter FORCE_BRAM = 0, + parameter RADDR_REG = 0, // read address registered hint + parameter RADDR_RESET = 0, // read address has reset + parameter WRITE_FIRST = 0, + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, + input wire [ADDRW-1:0] waddr, + input wire [DATAW-1:0] wdata, + input wire [ADDRW-1:0] raddr, + output wire [DATAW-1:0] rdata +); + localparam WSELW = DATAW / WRENW; + + `UNUSED_VAR (reset) + + (* keep = "true" *) wire [ADDRW-1:0] raddr_w, raddr_s; + (* keep = "true" *) wire read_s; + assign raddr_w = raddr; + + wire raddr_reset_w; + if (RADDR_RESET) begin : g_raddr_reset + (* keep = "true" *) wire raddr_reset; + assign raddr_reset = 0; + assign raddr_reset_w = raddr_reset; + end else begin : g_no_raddr_reset + assign raddr_reset_w = 0; + end + + VX_placeholder #( + .I (ADDRW + 1), + .O (ADDRW + 1) + ) placeholder1 ( + .in ({raddr_w, raddr_reset_w}), + .out ({raddr_s, read_s}) + ); + + wire [DATAW-1:0] rdata_s; + + if (1) begin : g_sync_ram + if (WRENW != 1) begin : g_wren + if (FORCE_BRAM) begin : g_bram + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES `USE_BLOCK_BRAM + `SYNC_RAM_WF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES `USE_BLOCK_BRAM + `SYNC_RAM_RF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end + end else begin : g_lutram + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES + `SYNC_RAM_WF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES + `SYNC_RAM_RF_WREN_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end + end + end else begin : g_no_wren + if (FORCE_BRAM) begin : g_bram + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES `USE_BLOCK_BRAM + `SYNC_RAM_WF_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES `USE_BLOCK_BRAM + `SYNC_RAM_RF_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end + end else begin : g_lutram + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES + `SYNC_RAM_WF_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES + `SYNC_RAM_RF_BLOCK(rdata_s, read_s, write, raddr_s, waddr); + `undef RAM_ATTRIBUTES + end + end + end + end + + if (RADDR_REG) begin : g_raddr_reg + assign rdata = rdata_s; + end else begin : g_async_ram + (* keep = "true" *) wire is_raddr_reg; + VX_placeholder #( + .O (1) + ) placeholder2 ( + .in (1'b0), + .out (is_raddr_reg) + ); + wire [DATAW-1:0] rdata_a; + if (DUAL_PORT) begin : g_dp + if (WRENW != 1) begin : g_wren + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES `RW_RAM_CHECK + `ASYNC_RAM_BLOCK_WREN(rdata_a, write, raddr, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES `NO_RW_RAM_CHECK + `ASYNC_RAM_BLOCK_WREN(rdata_a, write, raddr, waddr); + `undef RAM_ATTRIBUTES + end + end else begin : g_no_wren + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES `RW_RAM_CHECK + `ASYNC_RAM_BLOCK(rdata_a, write, raddr, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES `NO_RW_RAM_CHECK + `ASYNC_RAM_BLOCK(rdata_a, write, raddr, waddr); + `undef RAM_ATTRIBUTES + end + end + end else begin : g_sp + if (WRENW != 1) begin : g_wren + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES `RW_RAM_CHECK + `ASYNC_RAM_BLOCK_WREN(rdata_a, write, waddr, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES `NO_RW_RAM_CHECK + `ASYNC_RAM_BLOCK_WREN(rdata_a, write, waddr, waddr); + `undef RAM_ATTRIBUTES + end + end else begin : g_no_wren + if (WRITE_FIRST) begin : g_write_first + `define RAM_ATTRIBUTES `RW_RAM_CHECK + `ASYNC_RAM_BLOCK(rdata_a, write, waddr, waddr); + `undef RAM_ATTRIBUTES + end else begin : g_read_first + `define RAM_ATTRIBUTES `NO_RW_RAM_CHECK + `ASYNC_RAM_BLOCK(rdata_a, write, waddr, waddr); + `undef RAM_ATTRIBUTES + end + end + end + assign rdata = is_raddr_reg ? rdata_s : rdata_a; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_avs_adapter.sv b/designs/src/vortex/rtl/libs/VX_avs_adapter.sv new file mode 100644 index 0000000..48810db --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_avs_adapter.sv @@ -0,0 +1,275 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`TRACING_OFF +module VX_avs_adapter #( + parameter DATA_WIDTH = 1, + parameter ADDR_WIDTH_IN = 1, + parameter ADDR_WIDTH_OUT= 32, + parameter BURST_WIDTH = 1, + parameter NUM_PORTS_IN = 1, + parameter NUM_BANKS_OUT = 1, + parameter TAG_WIDTH = 1, + parameter RD_QUEUE_SIZE = 1, + parameter INTERLEAVE = 0, + parameter ARBITER = "R", + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + // Memory request + input wire mem_req_valid [NUM_PORTS_IN], + input wire mem_req_rw [NUM_PORTS_IN], + input wire [DATA_WIDTH/8-1:0] mem_req_byteen [NUM_PORTS_IN], + input wire [ADDR_WIDTH_IN-1:0] mem_req_addr [NUM_PORTS_IN], + input wire [DATA_WIDTH-1:0] mem_req_data [NUM_PORTS_IN], + input wire [TAG_WIDTH-1:0] mem_req_tag [NUM_PORTS_IN], + output wire mem_req_ready [NUM_PORTS_IN], + + // Memory response + output wire mem_rsp_valid [NUM_PORTS_IN], + output wire [DATA_WIDTH-1:0] mem_rsp_data [NUM_PORTS_IN], + output wire [TAG_WIDTH-1:0] mem_rsp_tag [NUM_PORTS_IN], + input wire mem_rsp_ready [NUM_PORTS_IN], + + // AVS bus + output wire [DATA_WIDTH-1:0] avs_writedata [NUM_BANKS_OUT], + input wire [DATA_WIDTH-1:0] avs_readdata [NUM_BANKS_OUT], + output wire [ADDR_WIDTH_OUT-1:0] avs_address [NUM_BANKS_OUT], + input wire avs_waitrequest [NUM_BANKS_OUT], + output wire avs_write [NUM_BANKS_OUT], + output wire avs_read [NUM_BANKS_OUT], + output wire [DATA_WIDTH/8-1:0] avs_byteenable [NUM_BANKS_OUT], + output wire [BURST_WIDTH-1:0] avs_burstcount [NUM_BANKS_OUT], + input wire avs_readdatavalid [NUM_BANKS_OUT] +); + localparam DATA_SIZE = DATA_WIDTH/8; + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS_OUT); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam DST_ADDR_WDITH = ADDR_WIDTH_OUT + BANK_SEL_BITS; // convert output addresss to input space + localparam BANK_ADDR_WIDTH = DST_ADDR_WDITH - BANK_SEL_BITS; + localparam NUM_PORTS_IN_BITS = `CLOG2(NUM_PORTS_IN); + localparam NUM_PORTS_IN_WIDTH = `UP(NUM_PORTS_IN_BITS); + localparam REQ_QUEUE_DATAW = TAG_WIDTH + NUM_PORTS_IN_BITS; + localparam REQ_XBAR_DATAW = 1 + BANK_ADDR_WIDTH + DATA_WIDTH + DATA_SIZE + TAG_WIDTH; + localparam RSP_XBAR_DATAW = DATA_WIDTH + TAG_WIDTH; + + `STATIC_ASSERT ((DST_ADDR_WDITH >= ADDR_WIDTH_IN), ("invalid address width: current=%0d, expected=%0d", DST_ADDR_WDITH, ADDR_WIDTH_IN)) + + // Bank selection + + wire [NUM_PORTS_IN-1:0][BANK_SEL_WIDTH-1:0] req_bank_sel; + wire [NUM_PORTS_IN-1:0][BANK_ADDR_WIDTH-1:0] req_bank_addr; + + if (NUM_BANKS_OUT > 1) begin : g_bank_sel + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_i + wire [DST_ADDR_WDITH-1:0] mem_req_addr_dst = DST_ADDR_WDITH'(mem_req_addr[i]); + if (INTERLEAVE) begin : g_interleave + assign req_bank_sel[i] = mem_req_addr_dst[BANK_SEL_BITS-1:0]; + assign req_bank_addr[i] = mem_req_addr_dst[BANK_SEL_BITS +: BANK_ADDR_WIDTH]; + end else begin : g_no_interleave + assign req_bank_sel[i] = mem_req_addr_dst[BANK_ADDR_WIDTH +: BANK_SEL_BITS]; + assign req_bank_addr[i] = mem_req_addr_dst[BANK_ADDR_WIDTH-1:0]; + end + end + end else begin : g_no_bank_sel + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_i + assign req_bank_sel[i] = '0; + assign req_bank_addr[i] = DST_ADDR_WDITH'(mem_req_addr[i]); + end + end + + // Requests handling + + wire [NUM_PORTS_IN-1:0] req_xbar_valid_in; + wire [NUM_PORTS_IN-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_in; + wire [NUM_PORTS_IN-1:0] req_xbar_ready_in; + + wire [NUM_BANKS_OUT-1:0] req_xbar_valid_out; + wire [NUM_BANKS_OUT-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_out; + wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] req_xbar_sel_out; + wire [NUM_BANKS_OUT-1:0] req_xbar_ready_out; + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_req_xbar_data_in + assign req_xbar_valid_in[i] = mem_req_valid[i]; + assign req_xbar_data_in[i] = {mem_req_rw[i], req_bank_addr[i], mem_req_byteen[i], mem_req_data[i], mem_req_tag[i]}; + assign mem_req_ready[i] = req_xbar_ready_in[i]; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_PORTS_IN), + .NUM_OUTPUTS(NUM_BANKS_OUT), + .DATAW (REQ_XBAR_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (REQ_OUT_BUF) + ) req_xbar ( + .clk (clk), + .reset (reset), + .sel_in (req_bank_sel), + .valid_in (req_xbar_valid_in), + .data_in (req_xbar_data_in), + .ready_in (req_xbar_ready_in), + .valid_out (req_xbar_valid_out), + .data_out (req_xbar_data_out), + .ready_out (req_xbar_ready_out), + .sel_out (req_xbar_sel_out), + `UNUSED_PIN (collisions) + ); + + wire [NUM_BANKS_OUT-1:0][REQ_QUEUE_DATAW-1:0] rd_req_queue_data_out; + wire [NUM_BANKS_OUT-1:0] rd_req_queue_pop; + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_req_xbar_data_out + + wire ready_out; + wire rw_out; + wire [BANK_ADDR_WIDTH-1:0] addr_out; + wire [TAG_WIDTH-1:0] tag_out; + wire [DATA_WIDTH-1:0] data_out; + wire [DATA_SIZE-1:0] byteen_out; + wire valid_out; + + assign {rw_out, addr_out, byteen_out, data_out, tag_out} = req_xbar_data_out[i]; + + wire rd_req_queue_going_full; + wire rd_req_queue_push; + + // stall pipeline if the request queue is needed and going full + wire rd_req_queue_ready = rw_out || ~rd_req_queue_going_full; + assign valid_out = req_xbar_valid_out[i] && rd_req_queue_ready; + assign ready_out = ~avs_waitrequest[i] && rd_req_queue_ready; + assign rd_req_queue_push = valid_out && ready_out && ~rw_out; + + VX_pending_size #( + .SIZE (RD_QUEUE_SIZE) + ) pending_size ( + .clk (clk), + .reset (reset), + .incr (rd_req_queue_push), + .decr (rd_req_queue_pop[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (alm_empty), + .full (rd_req_queue_going_full), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + wire [REQ_QUEUE_DATAW-1:0] rd_req_queue_data_in; + if (NUM_PORTS_IN > 1) begin : g_input_sel + assign rd_req_queue_data_in = {tag_out, req_xbar_sel_out[i]}; + end else begin : g_no_input_sel + `UNUSED_VAR (req_xbar_sel_out[i]) + assign rd_req_queue_data_in = tag_out; + end + + VX_fifo_queue #( + .DATAW (REQ_QUEUE_DATAW), + .DEPTH (RD_QUEUE_SIZE) + ) rd_req_queue ( + .clk (clk), + .reset (reset), + .push (rd_req_queue_push), + .pop (rd_req_queue_pop[i]), + .data_in (rd_req_queue_data_in), + .data_out (rd_req_queue_data_out[i]), + `UNUSED_PIN (empty), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + assign avs_read[i] = valid_out && ~rw_out; + assign avs_write[i] = valid_out && rw_out; + assign avs_address[i] = ADDR_WIDTH_OUT'(addr_out); + assign avs_byteenable[i] = byteen_out; + assign avs_writedata[i] = data_out; + assign avs_burstcount[i] = BURST_WIDTH'(1); + assign req_xbar_ready_out[i] = ready_out; + end + + // Responses handling + + wire [NUM_BANKS_OUT-1:0] rsp_xbar_valid_in; + wire [NUM_BANKS_OUT-1:0][RSP_XBAR_DATAW-1:0] rsp_xbar_data_in; + wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] rsp_xbar_sel_in; + wire [NUM_BANKS_OUT-1:0] rsp_xbar_ready_in; + + wire [NUM_PORTS_IN-1:0] rsp_xbar_valid_out; + wire [NUM_PORTS_IN-1:0][RSP_XBAR_DATAW-1:0] rsp_xbar_data_out; + wire [NUM_PORTS_IN-1:0] rsp_xbar_ready_out; + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_rsp_xbar_data_in + + wire [DATA_WIDTH-1:0] rsp_queue_data_out; + wire rsp_queue_empty; + + VX_fifo_queue #( + .DATAW (DATA_WIDTH), + .DEPTH (RD_QUEUE_SIZE) + ) rsp_queue ( + .clk (clk), + .reset (reset), + .push (avs_readdatavalid[i]), + .pop (rd_req_queue_pop[i]), + .data_in (avs_readdata[i]), + .data_out (rsp_queue_data_out), + .empty (rsp_queue_empty), + `UNUSED_PIN (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + assign rsp_xbar_valid_in[i] = ~rsp_queue_empty; + assign rsp_xbar_data_in[i] = {rsp_queue_data_out, rd_req_queue_data_out[i][NUM_PORTS_IN_BITS +: TAG_WIDTH]}; + if (NUM_PORTS_IN > 1) begin : g_input_sel + assign rsp_xbar_sel_in[i] = rd_req_queue_data_out[i][0 +: NUM_PORTS_IN_BITS]; + end else begin : g_no_input_sel + assign rsp_xbar_sel_in[i] = 0; + end + assign rd_req_queue_pop[i] = rsp_xbar_valid_in[i] && rsp_xbar_ready_in[i]; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS_OUT), + .NUM_OUTPUTS(NUM_PORTS_IN), + .DATAW (RSP_XBAR_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_xbar ( + .clk (clk), + .reset (reset), + .valid_in (rsp_xbar_valid_in), + .data_in (rsp_xbar_data_in), + .ready_in (rsp_xbar_ready_in), + .sel_in (rsp_xbar_sel_in), + .data_out (rsp_xbar_data_out), + .valid_out (rsp_xbar_valid_out), + .ready_out (rsp_xbar_ready_out), + `UNUSED_PIN (collisions), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_rsp_xbar_data_out + assign mem_rsp_valid[i] = rsp_xbar_valid_out[i]; + assign {mem_rsp_data[i], mem_rsp_tag[i]} = rsp_xbar_data_out[i]; + assign rsp_xbar_ready_out[i] = mem_rsp_ready[i]; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_axi_adapter.sv b/designs/src/vortex/rtl/libs/VX_axi_adapter.sv new file mode 100644 index 0000000..8ea6585 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_axi_adapter.sv @@ -0,0 +1,368 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_axi_adapter #( + parameter DATA_WIDTH = 512, + parameter ADDR_WIDTH_IN = 26, // word-addressable + parameter ADDR_WIDTH_OUT = 32, // byte-addressable + parameter TAG_WIDTH_IN = 8, + parameter TAG_WIDTH_OUT = 8, + parameter NUM_PORTS_IN = 1, + parameter NUM_BANKS_OUT = 1, + parameter INTERLEAVE = 0, + parameter TAG_BUFFER_SIZE= 16, + parameter ARBITER = "R", + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0, + parameter DATA_SIZE = DATA_WIDTH/8 + ) ( + input wire clk, + input wire reset, + + // Vortex request + input wire mem_req_valid [NUM_PORTS_IN], + input wire mem_req_rw [NUM_PORTS_IN], + input wire [DATA_SIZE-1:0] mem_req_byteen [NUM_PORTS_IN], + input wire [ADDR_WIDTH_IN-1:0] mem_req_addr [NUM_PORTS_IN], + input wire [DATA_WIDTH-1:0] mem_req_data [NUM_PORTS_IN], + input wire [TAG_WIDTH_IN-1:0] mem_req_tag [NUM_PORTS_IN], + output wire mem_req_ready [NUM_PORTS_IN], + + // Vortex response + output wire mem_rsp_valid [NUM_PORTS_IN], + output wire [DATA_WIDTH-1:0] mem_rsp_data [NUM_PORTS_IN], + output wire [TAG_WIDTH_IN-1:0] mem_rsp_tag [NUM_PORTS_IN], + input wire mem_rsp_ready [NUM_PORTS_IN], + + // AXI write request address channel + output wire m_axi_awvalid [NUM_BANKS_OUT], + input wire m_axi_awready [NUM_BANKS_OUT], + output wire [ADDR_WIDTH_OUT-1:0] m_axi_awaddr [NUM_BANKS_OUT], + output wire [TAG_WIDTH_OUT-1:0] m_axi_awid [NUM_BANKS_OUT], + output wire [7:0] m_axi_awlen [NUM_BANKS_OUT], + output wire [2:0] m_axi_awsize [NUM_BANKS_OUT], + output wire [1:0] m_axi_awburst [NUM_BANKS_OUT], + output wire [1:0] m_axi_awlock [NUM_BANKS_OUT], + output wire [3:0] m_axi_awcache [NUM_BANKS_OUT], + output wire [2:0] m_axi_awprot [NUM_BANKS_OUT], + output wire [3:0] m_axi_awqos [NUM_BANKS_OUT], + output wire [3:0] m_axi_awregion [NUM_BANKS_OUT], + + // AXI write request data channel + output wire m_axi_wvalid [NUM_BANKS_OUT], + input wire m_axi_wready [NUM_BANKS_OUT], + output wire [DATA_WIDTH-1:0] m_axi_wdata [NUM_BANKS_OUT], + output wire [DATA_SIZE-1:0] m_axi_wstrb [NUM_BANKS_OUT], + output wire m_axi_wlast [NUM_BANKS_OUT], + + // AXI write response channel + input wire m_axi_bvalid [NUM_BANKS_OUT], + output wire m_axi_bready [NUM_BANKS_OUT], + input wire [TAG_WIDTH_OUT-1:0] m_axi_bid [NUM_BANKS_OUT], + input wire [1:0] m_axi_bresp [NUM_BANKS_OUT], + + // AXI read address channel + output wire m_axi_arvalid [NUM_BANKS_OUT], + input wire m_axi_arready [NUM_BANKS_OUT], + output wire [ADDR_WIDTH_OUT-1:0] m_axi_araddr [NUM_BANKS_OUT], + output wire [TAG_WIDTH_OUT-1:0] m_axi_arid [NUM_BANKS_OUT], + output wire [7:0] m_axi_arlen [NUM_BANKS_OUT], + output wire [2:0] m_axi_arsize [NUM_BANKS_OUT], + output wire [1:0] m_axi_arburst [NUM_BANKS_OUT], + output wire [1:0] m_axi_arlock [NUM_BANKS_OUT], + output wire [3:0] m_axi_arcache [NUM_BANKS_OUT], + output wire [2:0] m_axi_arprot [NUM_BANKS_OUT], + output wire [3:0] m_axi_arqos [NUM_BANKS_OUT], + output wire [3:0] m_axi_arregion [NUM_BANKS_OUT], + + // AXI read response channel + input wire m_axi_rvalid [NUM_BANKS_OUT], + output wire m_axi_rready [NUM_BANKS_OUT], + input wire [DATA_WIDTH-1:0] m_axi_rdata [NUM_BANKS_OUT], + input wire m_axi_rlast [NUM_BANKS_OUT], + input wire [TAG_WIDTH_OUT-1:0] m_axi_rid [NUM_BANKS_OUT], + input wire [1:0] m_axi_rresp [NUM_BANKS_OUT] +); + localparam LOG2_DATA_SIZE = `CLOG2(DATA_SIZE); + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS_OUT); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam DST_ADDR_WDITH = (ADDR_WIDTH_OUT - LOG2_DATA_SIZE) + BANK_SEL_BITS; // convert byte-addressable output addresss to block-addressable input space + localparam BANK_ADDR_WIDTH = DST_ADDR_WDITH - BANK_SEL_BITS; + localparam NUM_PORTS_IN_BITS = `CLOG2(NUM_PORTS_IN); + localparam NUM_PORTS_IN_WIDTH = `UP(NUM_PORTS_IN_BITS); + localparam TAG_BUFFER_ADDRW = `CLOG2(TAG_BUFFER_SIZE); + localparam NEEDED_TAG_WIDTH = TAG_WIDTH_IN + NUM_PORTS_IN_BITS; + localparam READ_TAG_WIDTH = (NEEDED_TAG_WIDTH > TAG_WIDTH_OUT) ? TAG_BUFFER_ADDRW : TAG_WIDTH_IN; + localparam READ_FULL_TAG_WIDTH = READ_TAG_WIDTH + NUM_PORTS_IN_BITS; + localparam WRITE_TAG_WIDTH = `MIN(TAG_WIDTH_IN, TAG_WIDTH_OUT); + localparam DST_TAG_WIDTH = `MAX(READ_FULL_TAG_WIDTH, WRITE_TAG_WIDTH); + localparam XBAR_TAG_WIDTH = `MAX(READ_TAG_WIDTH, WRITE_TAG_WIDTH); + localparam REQ_XBAR_DATAW = 1 + BANK_ADDR_WIDTH + DATA_SIZE + DATA_WIDTH + XBAR_TAG_WIDTH; + localparam RSP_XBAR_DATAW = DATA_WIDTH + READ_TAG_WIDTH; + + `STATIC_ASSERT ((DST_ADDR_WDITH >= ADDR_WIDTH_IN), ("invalid address width: current=%0d, expected=%0d", DST_ADDR_WDITH, ADDR_WIDTH_IN)) + `STATIC_ASSERT ((TAG_WIDTH_OUT >= DST_TAG_WIDTH), ("invalid output tag width: current=%0d, expected=%0d", TAG_WIDTH_OUT, DST_TAG_WIDTH)) + + // Bank selection + + wire [NUM_PORTS_IN-1:0][BANK_SEL_WIDTH-1:0] req_bank_sel; + wire [NUM_PORTS_IN-1:0][BANK_ADDR_WIDTH-1:0] req_bank_addr; + + if (NUM_BANKS_OUT > 1) begin : g_bank_sel + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_i + wire [DST_ADDR_WDITH-1:0] mem_req_addr_dst = DST_ADDR_WDITH'(mem_req_addr[i]); + if (INTERLEAVE) begin : g_interleave + assign req_bank_sel[i] = mem_req_addr_dst[BANK_SEL_BITS-1:0]; + assign req_bank_addr[i] = mem_req_addr_dst[BANK_SEL_BITS +: BANK_ADDR_WIDTH]; + end else begin : g_no_interleave + assign req_bank_sel[i] = mem_req_addr_dst[BANK_ADDR_WIDTH +: BANK_SEL_BITS]; + assign req_bank_addr[i] = mem_req_addr_dst[BANK_ADDR_WIDTH-1:0]; + end + end + end else begin : g_no_bank_sel + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_i + assign req_bank_sel[i] = '0; + assign req_bank_addr[i] = DST_ADDR_WDITH'(mem_req_addr[i]); + end + end + + // Tag handling logic + + wire [NUM_PORTS_IN-1:0] mem_rd_req_tag_ready; + wire [NUM_PORTS_IN-1:0][READ_TAG_WIDTH-1:0] mem_rd_req_tag; + wire [NUM_PORTS_IN-1:0][READ_TAG_WIDTH-1:0] mem_rd_rsp_tag; + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_tag_buf + if (NEEDED_TAG_WIDTH > TAG_WIDTH_OUT) begin : g_enabled + wire [TAG_BUFFER_ADDRW-1:0] tbuf_waddr, tbuf_raddr; + wire tbuf_full; + VX_index_buffer #( + .DATAW (TAG_WIDTH_IN), + .SIZE (TAG_BUFFER_SIZE) + ) tag_buf ( + .clk (clk), + .reset (reset), + .acquire_en (mem_req_valid[i] && ~mem_req_rw[i] && mem_req_ready[i]), + .write_addr (tbuf_waddr), + .write_data (mem_req_tag[i]), + .read_data (mem_rsp_tag[i]), + .read_addr (tbuf_raddr), + .release_en (mem_rsp_valid[i] && mem_rsp_ready[i]), + .full (tbuf_full), + `UNUSED_PIN (empty) + ); + assign mem_rd_req_tag_ready[i] = ~tbuf_full; + assign mem_rd_req_tag[i] = tbuf_waddr; + assign tbuf_raddr = mem_rd_rsp_tag[i]; + end else begin : g_none + assign mem_rd_req_tag_ready[i] = 1; + assign mem_rd_req_tag[i] = mem_req_tag[i]; + assign mem_rsp_tag[i] = mem_rd_rsp_tag[i]; + end + end + + // AXI request handling + + wire [NUM_PORTS_IN-1:0] req_xbar_valid_in; + wire [NUM_PORTS_IN-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_in; + wire [NUM_PORTS_IN-1:0] req_xbar_ready_in; + + wire [NUM_BANKS_OUT-1:0] req_xbar_valid_out; + wire [NUM_BANKS_OUT-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_out; + wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] req_xbar_sel_out; + wire [NUM_BANKS_OUT-1:0] req_xbar_ready_out; + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_req_xbar_data_in + wire tag_ready = mem_req_rw[i] || mem_rd_req_tag_ready[i]; + wire [XBAR_TAG_WIDTH-1:0] tag_value = mem_req_rw[i] ? XBAR_TAG_WIDTH'(mem_req_tag[i]) : XBAR_TAG_WIDTH'(mem_rd_req_tag[i]); + assign req_xbar_valid_in[i] = mem_req_valid[i] && tag_ready; + assign req_xbar_data_in[i] = {mem_req_rw[i], req_bank_addr[i], mem_req_byteen[i], mem_req_data[i], tag_value}; + assign mem_req_ready[i] = req_xbar_ready_in[i] && tag_ready; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_PORTS_IN), + .NUM_OUTPUTS(NUM_BANKS_OUT), + .DATAW (REQ_XBAR_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (REQ_OUT_BUF) + ) req_xbar ( + .clk (clk), + .reset (reset), + .sel_in (req_bank_sel), + .valid_in (req_xbar_valid_in), + .data_in (req_xbar_data_in), + .ready_in (req_xbar_ready_in), + .valid_out (req_xbar_valid_out), + .data_out (req_xbar_data_out), + .ready_out (req_xbar_ready_out), + .sel_out (req_xbar_sel_out), + `UNUSED_PIN (collisions) + ); + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_reqs + + wire xbar_rw_out; + wire [BANK_ADDR_WIDTH-1:0] xbar_addr_out; + wire [XBAR_TAG_WIDTH-1:0] xbar_tag_out; + wire [DATA_WIDTH-1:0] xbar_data_out; + wire [DATA_SIZE-1:0] xbar_byteen_out; + + assign { + xbar_rw_out, + xbar_addr_out, + xbar_byteen_out, + xbar_data_out, + xbar_tag_out + } = req_xbar_data_out[i]; + + // AXi request handshake + + wire m_axi_aw_ack, m_axi_w_ack, axi_write_ready; + + VX_axi_write_ack axi_write_ack ( + .clk (clk), + .reset (reset), + .awvalid(m_axi_awvalid[i]), + .awready(m_axi_awready[i]), + .wvalid (m_axi_wvalid[i]), + .wready (m_axi_wready[i]), + .aw_ack (m_axi_aw_ack), + .w_ack (m_axi_w_ack), + .tx_rdy (axi_write_ready), + `UNUSED_PIN (tx_ack) + ); + + assign req_xbar_ready_out[i] = xbar_rw_out ? axi_write_ready : m_axi_arready[i]; + + // AXI write address channel + + assign m_axi_awvalid[i] = req_xbar_valid_out[i] && xbar_rw_out && ~m_axi_aw_ack; + + if (INTERLEAVE) begin : g_m_axi_awaddr_i + assign m_axi_awaddr[i] = (ADDR_WIDTH_OUT'(xbar_addr_out) << (BANK_SEL_BITS + LOG2_DATA_SIZE)) | (ADDR_WIDTH_OUT'(i) << LOG2_DATA_SIZE); + end else begin : g_m_axi_awaddr_ni + assign m_axi_awaddr[i] = (ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE) | (ADDR_WIDTH_OUT'(i) << (BANK_ADDR_WIDTH + LOG2_DATA_SIZE)); + end + + assign m_axi_awid[i] = TAG_WIDTH_OUT'(xbar_tag_out); + assign m_axi_awlen[i] = 8'b00000000; + assign m_axi_awsize[i] = 3'(LOG2_DATA_SIZE); + assign m_axi_awburst[i] = 2'b00; + assign m_axi_awlock[i] = 2'b00; + assign m_axi_awcache[i] = 4'b0000; + assign m_axi_awprot[i] = 3'b000; + assign m_axi_awqos[i] = 4'b0000; + assign m_axi_awregion[i]= 4'b0000; + + // AXI write data channel + + assign m_axi_wvalid[i] = req_xbar_valid_out[i] && xbar_rw_out && ~m_axi_w_ack; + assign m_axi_wstrb[i] = xbar_byteen_out; + assign m_axi_wdata[i] = xbar_data_out; + assign m_axi_wlast[i] = 1'b1; + + // AXI read address channel + + wire [READ_FULL_TAG_WIDTH-1:0] xbar_tag_r_out; + if (NUM_PORTS_IN > 1) begin : g_xbar_tag_r_out + assign xbar_tag_r_out = READ_FULL_TAG_WIDTH'({xbar_tag_out, req_xbar_sel_out[i]}); + end else begin : g_no_input_sel + `UNUSED_VAR (req_xbar_sel_out) + assign xbar_tag_r_out = READ_TAG_WIDTH'(xbar_tag_out); + end + + assign m_axi_arvalid[i] = req_xbar_valid_out[i] && ~xbar_rw_out; + + // convert address to byte-addressable space + if (INTERLEAVE) begin : g_m_axi_araddr_i + assign m_axi_araddr[i] = (ADDR_WIDTH_OUT'(xbar_addr_out) << (BANK_SEL_BITS + LOG2_DATA_SIZE)) | (ADDR_WIDTH_OUT'(i) << LOG2_DATA_SIZE); + end else begin : g_m_axi_araddr_ni + assign m_axi_araddr[i] = (ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE) | (ADDR_WIDTH_OUT'(i) << (BANK_ADDR_WIDTH + LOG2_DATA_SIZE)); + end + assign m_axi_arid[i] = TAG_WIDTH_OUT'(xbar_tag_r_out); + assign m_axi_arlen[i] = 8'b00000000; + assign m_axi_arsize[i] = 3'(LOG2_DATA_SIZE); + assign m_axi_arburst[i] = 2'b00; + assign m_axi_arlock[i] = 2'b00; + assign m_axi_arcache[i] = 4'b0000; + assign m_axi_arprot[i] = 3'b000; + assign m_axi_arqos[i] = 4'b0000; + assign m_axi_arregion[i]= 4'b0000; + end + + // AXI write response channel (ignore) + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_axi_write_rsp + `UNUSED_VAR (m_axi_bvalid[i]) + `UNUSED_VAR (m_axi_bid[i]) + `UNUSED_VAR (m_axi_bresp[i]) + assign m_axi_bready[i] = 1'b1; + `RUNTIME_ASSERT(~m_axi_bvalid[i] || m_axi_bresp[i] == 0, ("%t: *** AXI response error", $time)) + end + + // AXI read response channel + + wire [NUM_BANKS_OUT-1:0] rsp_xbar_valid_in; + wire [NUM_BANKS_OUT-1:0][RSP_XBAR_DATAW-1:0] rsp_xbar_data_in; + wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] rsp_xbar_sel_in; + wire [NUM_BANKS_OUT-1:0] rsp_xbar_ready_in; + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_rsp_xbar_data_in + assign rsp_xbar_valid_in[i] = m_axi_rvalid[i]; + assign rsp_xbar_data_in[i] = {m_axi_rdata[i], m_axi_rid[i][NUM_PORTS_IN_BITS +: READ_TAG_WIDTH]}; + if (NUM_PORTS_IN > 1) begin : g_input_sel + assign rsp_xbar_sel_in[i] = m_axi_rid[i][0 +: NUM_PORTS_IN_BITS]; + end else begin : g_no_input_sel + assign rsp_xbar_sel_in[i] = 0; + end + assign m_axi_rready[i] = rsp_xbar_ready_in[i]; + `RUNTIME_ASSERT(~(m_axi_rvalid[i] && m_axi_rlast[i] == 0), ("%t: *** AXI response error", $time)) + `RUNTIME_ASSERT(~(m_axi_rvalid[i] && m_axi_rresp[i] != 0), ("%t: *** AXI response error", $time)) + end + + wire [NUM_PORTS_IN-1:0] rsp_xbar_valid_out; + wire [NUM_PORTS_IN-1:0][DATA_WIDTH+READ_TAG_WIDTH-1:0] rsp_xbar_data_out; + wire [NUM_PORTS_IN-1:0] rsp_xbar_ready_out; + + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS_OUT), + .NUM_OUTPUTS(NUM_PORTS_IN), + .DATAW (RSP_XBAR_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_xbar ( + .clk (clk), + .reset (reset), + .valid_in (rsp_xbar_valid_in), + .data_in (rsp_xbar_data_in), + .ready_in (rsp_xbar_ready_in), + .sel_in (rsp_xbar_sel_in), + .data_out (rsp_xbar_data_out), + .valid_out (rsp_xbar_valid_out), + .ready_out (rsp_xbar_ready_out), + `UNUSED_PIN (collisions), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_rsp_xbar_data_out + assign mem_rsp_valid[i] = rsp_xbar_valid_out[i]; + assign {mem_rsp_data[i], mem_rd_rsp_tag[i]} = rsp_xbar_data_out[i]; + assign rsp_xbar_ready_out[i] = mem_rsp_ready[i]; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_axi_write_ack.sv b/designs/src/vortex/rtl/libs/VX_axi_write_ack.sv new file mode 100644 index 0000000..faf4fc8 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_axi_write_ack.sv @@ -0,0 +1,60 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_axi_write_ack ( + input wire clk, + input wire reset, + input wire awvalid, + input wire awready, + input wire wvalid, + input wire wready, + output wire aw_ack, + output wire w_ack, + output wire tx_ack, + output wire tx_rdy +); + reg aw_fired; + reg w_fired; + + wire aw_fire = awvalid && awready; + wire w_fire = wvalid && wready; + + always @(posedge clk) begin + if (reset) begin + aw_fired <= 0; + w_fired <= 0; + end else begin + if (aw_fire) begin + aw_fired <= 1; + end + if (w_fire) begin + w_fired <= 1; + end + if (tx_ack) begin + aw_fired <= 0; + w_fired <= 0; + end + end + end + + assign aw_ack = aw_fired; + assign w_ack = w_fired; + + assign tx_ack = (aw_fire || aw_fired) && (w_fire || w_fired); + assign tx_rdy = (awready || aw_fired) && (wready || w_fired); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_bits_concat.sv b/designs/src/vortex/rtl/libs/VX_bits_concat.sv new file mode 100644 index 0000000..cb3cec4 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_bits_concat.sv @@ -0,0 +1,36 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_bits_concat #( + parameter L = 1, + parameter R = 1 +) ( + input wire [`UP(L)-1:0] left_in, + input wire [`UP(R)-1:0] right_in, + output wire [(L+R)-1:0] data_out +); + if (L == 0) begin : g_right_only + `UNUSED_VAR (left_in) + assign data_out = right_in; + end else if (R == 0) begin : g_left_only + `UNUSED_VAR (right_in) + assign data_out = left_in; + end else begin : g_concat + assign data_out = {left_in, right_in}; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_bits_insert.sv b/designs/src/vortex/rtl/libs/VX_bits_insert.sv new file mode 100644 index 0000000..dee8141 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_bits_insert.sv @@ -0,0 +1,40 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_bits_insert #( + parameter N = 1, + parameter S = 1, + parameter POS = 0 +) ( + input wire [N-1:0] data_in, + input wire [`UP(S)-1:0] ins_in, + output wire [N+S-1:0] data_out +); + if (S == 0) begin : g_passthru + `UNUSED_VAR (ins_in) + assign data_out = data_in; + end else begin : g_insert + if (POS == 0) begin : g_pos_0 + assign data_out = {data_in, ins_in}; + end else if (POS == N) begin : g_pos_N + assign data_out = {ins_in, data_in}; + end else begin : g_pos + assign data_out = {data_in[N-1:POS], ins_in, data_in[POS-1:0]}; + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_bits_remove.sv b/designs/src/vortex/rtl/libs/VX_bits_remove.sv new file mode 100644 index 0000000..fae7d47 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_bits_remove.sv @@ -0,0 +1,45 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_bits_remove #( + parameter N = 2, + parameter S = 1, + parameter POS = 0 +) ( + input wire [N-1:0] data_in, + output wire [`UP(S)-1:0] sel_out, + output wire [N-S-1:0] data_out +); + `STATIC_ASSERT (((0 == S) || ((POS + S) <= N)), ("invalid parameter")) + + if (S == 0) begin : g_passthru + assign sel_out = 0; + assign data_out = data_in; + end else if (POS == 0) begin : g_pos_0 + assign sel_out = data_in[0 +: S]; + assign data_out = data_in[N-1:S]; + end else if ((POS + S) == N) begin : g_pos_N + assign sel_out = data_in[POS +: S]; + assign data_out = data_in[POS-1:0]; + end else begin : g_pos + assign sel_out = data_in[POS +: S]; + assign data_out = {data_in[N-1:(POS+S)], data_in[POS-1:0]}; + end + + `UNUSED_VAR (data_in) + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_bypass_buffer.sv b/designs/src/vortex/rtl/libs/VX_bypass_buffer.sv new file mode 100644 index 0000000..7378a4f --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_bypass_buffer.sv @@ -0,0 +1,73 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A bypass elastic buffer operates at full bandwidth where pop can happen if the buffer is empty but is going full +// It has the following benefits: +// + Full-bandwidth throughput +// + use only one register for storage +// It has the following limitations: +// + data_out is not registered +// + ready_in and ready_out are coupled + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_bypass_buffer #( + parameter DATAW = 1, + parameter PASSTHRU = 0 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (PASSTHRU != 0) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + assign ready_in = ready_out; + assign valid_out = valid_in; + assign data_out = data_in; + + end else begin : g_buffer + + reg [DATAW-1:0] buffer; + reg has_data; + + always @(posedge clk) begin + if (reset) begin + has_data <= 0; + end else begin + if (ready_out) begin + has_data <= 0; + end else if (~has_data) begin + has_data <= valid_in; + end + end + if (~has_data) begin + buffer <= data_in; + end + end + + assign ready_in = ready_out || ~has_data; + assign data_out = has_data ? buffer : data_in; + assign valid_out = valid_in || has_data; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_cyclic_arbiter.sv b/designs/src/vortex/rtl/libs/VX_cyclic_arbiter.sv new file mode 100644 index 0000000..394df4f --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_cyclic_arbiter.sv @@ -0,0 +1,104 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_cyclic_arbiter #( + parameter NUM_REQS = 1, + parameter STICKY = 0, // hold the grant until its request is deasserted + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) +) ( + input wire clk, + input wire reset, + input wire [NUM_REQS-1:0] requests, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid, + input wire grant_ready +); + if (NUM_REQS == 1) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (grant_ready) + `UNUSED_PARAM (STICKY) + + assign grant_index = '0; + assign grant_onehot = requests; + assign grant_valid = requests[0]; + + end else begin : g_arbiter + + localparam IS_POW2 = (1 << LOG_NUM_REQS) == NUM_REQS; + + wire [LOG_NUM_REQS-1:0] grant_index_um; + wire [NUM_REQS-1:0] grant_onehot_w, grant_onehot_um; + reg [LOG_NUM_REQS-1:0] grant_index_r; + + reg [NUM_REQS-1:0] prev_grant; + + always @(posedge clk) begin + if (reset) begin + prev_grant <= '0; + end else if (grant_valid && grant_ready) begin + prev_grant <= grant_onehot; + end + end + + wire retain_grant = (STICKY != 0) && (|(prev_grant & requests)); + + wire [NUM_REQS-1:0] requests_w = retain_grant ? prev_grant : requests; + + always @(posedge clk) begin + if (reset) begin + grant_index_r <= '0; + end else if (grant_valid && grant_ready && ~retain_grant) begin + if (!IS_POW2 && grant_index == LOG_NUM_REQS'(NUM_REQS-1)) begin + grant_index_r <= '0; + end else begin + grant_index_r <= grant_index + LOG_NUM_REQS'(1); + end + end + end + + wire grant_valid_w; + + VX_priority_encoder #( + .N (NUM_REQS) + ) grant_sel ( + .data_in (requests_w), + .onehot_out (grant_onehot_um), + .index_out (grant_index_um), + .valid_out (grant_valid_w) + ); + + VX_demux #( + .DATAW (1), + .N (NUM_REQS) + ) grant_decoder ( + .sel_in (grant_index_r), + .data_in (1'b1), + .data_out (grant_onehot_w) + ); + + wire is_hit = requests[grant_index_r] && ~retain_grant; + + assign grant_index = is_hit ? grant_index_r : grant_index_um; + assign grant_onehot = is_hit ? grant_onehot_w : grant_onehot_um; + assign grant_valid = (STICKY != 0) ? (| requests) : grant_valid_w; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_demux.sv b/designs/src/vortex/rtl/libs/VX_demux.sv new file mode 100644 index 0000000..6a1ddc8 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_demux.sv @@ -0,0 +1,47 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +// Fast encoder using parallel prefix computation +// Adapted from BaseJump STL: http://bjump.org/data_out.html + +`TRACING_OFF +module VX_demux #( + parameter DATAW = 1, + parameter N = 0, + parameter MODEL = 0, + parameter LN = `LOG2UP(N) +) ( + input wire [LN-1:0] sel_in, + input wire [DATAW-1:0] data_in, + output wire [N-1:0][DATAW-1:0] data_out +); + if (N > 1) begin : g_demux + logic [N-1:0][DATAW-1:0] shift; + if (MODEL == 1) begin : g_model1 + always @(*) begin + shift = '0; + shift[sel_in] = {DATAW{1'b1}}; + end + end else begin : g_model0 + assign shift = ((N*DATAW)'({DATAW{1'b1}})) << (sel_in * DATAW); + end + assign data_out = {N{data_in}} & shift; + end else begin : g_passthru + `UNUSED_VAR (sel_in) + assign data_out = data_in; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_divider.sv b/designs/src/vortex/rtl/libs/VX_divider.sv new file mode 100644 index 0000000..b842484 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_divider.sv @@ -0,0 +1,109 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_divider #( + parameter N_WIDTH = 1, + parameter D_WIDTH = 1, + parameter Q_WIDTH = 1, + parameter R_WIDTH = 1, + parameter N_SIGNED = 0, + parameter D_SIGNED = 0, + parameter LATENCY = 0 +) ( + input wire clk, + input wire enable, + input wire [N_WIDTH-1:0] numer, + input wire [D_WIDTH-1:0] denom, + output wire [Q_WIDTH-1:0] quotient, + output wire [R_WIDTH-1:0] remainder +); + +`ifdef QUARTUS + + wire [N_WIDTH-1:0] quotient_unqual; + wire [D_WIDTH-1:0] remainder_unqual; + + lpm_divide divide ( + .clock (clk), + .clken (enable), + .numer (numer), + .denom (denom), + .quotient (quotient_unqual), + .remain (remainder_unqual) + ); + + defparam + divide.lpm_type = "LPM_DIVIDE", + divide.lpm_widthn = N_WIDTH, + divide.lpm_widthd = D_WIDTH, + divide.lpm_nrepresentation = N_SIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_drepresentation = D_SIGNED ? "SIGNED" : "UNSIGNED", + divide.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", + divide.lpm_pipeline = LATENCY; + + assign quotient = quotient_unqual [Q_WIDTH-1:0]; + assign remainder = remainder_unqual [R_WIDTH-1:0]; + +`else + + reg [N_WIDTH-1:0] quotient_unqual; + reg [D_WIDTH-1:0] remainder_unqual; + + always @(*) begin + begin + if (N_SIGNED && D_SIGNED) begin + quotient_unqual = $signed(numer) / $signed(denom); + remainder_unqual = $signed(numer) % $signed(denom); + end + else if (N_SIGNED && !D_SIGNED) begin + quotient_unqual = $signed(numer) / denom; + remainder_unqual = $signed(numer) % denom; + end + else if (!N_SIGNED && D_SIGNED) begin + quotient_unqual = numer / $signed(denom); + remainder_unqual = numer % $signed(denom); + end + else begin + quotient_unqual = numer / denom; + remainder_unqual = numer % denom; + end + end + end + + if (LATENCY == 0) begin : g_comb + assign quotient = quotient_unqual [Q_WIDTH-1:0]; + assign remainder = remainder_unqual [R_WIDTH-1:0]; + end else begin : g_pipe + reg [N_WIDTH-1:0] quotient_pipe [LATENCY-1:0]; + reg [D_WIDTH-1:0] remainder_pipe [LATENCY-1:0]; + + for (genvar i = 0; i < LATENCY; ++i) begin : g_reg + always @(posedge clk) begin + if (enable) begin + quotient_pipe[i] <= (0 == i) ? quotient_unqual : quotient_pipe[i-1]; + remainder_pipe[i] <= (0 == i) ? remainder_unqual : remainder_pipe[i-1]; + end + end + end + + assign quotient = quotient_pipe[LATENCY-1][Q_WIDTH-1:0]; + assign remainder = remainder_pipe[LATENCY-1][R_WIDTH-1:0]; + end + +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_dp_ram.sv b/designs/src/vortex/rtl/libs/VX_dp_ram.sv new file mode 100644 index 0000000..28a1758 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_dp_ram.sv @@ -0,0 +1,498 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// Modifications: +// - Added FakeRAM conditionals (for memories exceeding 1000 bits) +`include "VX_platform.vh" + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE != 0) begin : g_init \ + if (INIT_FILE != "") begin : g_file \ + initial $readmemh(INIT_FILE, ram); \ + end else begin : g_value \ + initial begin \ + for (integer i = 0; i < SIZE; ++i) begin : g_i \ + ram[i] = INIT_VALUE; \ + end \ + end \ + end \ + end + +`ifdef SIMULATION + `define RAM_RESET_BLOCK if (RESET_RAM && reset) begin \ + for (integer i = 0; i < SIZE; ++i) begin \ + ram[i] <= DATAW'(INIT_VALUE); \ + end \ + end else +`else + `define RAM_RESET_BLOCK +`endif + +`define RAM_WRITE_ALL `RAM_RESET_BLOCK \ + if (write) begin \ + ram[waddr] <= wdata; \ + end + +`ifdef QUARTUS + `define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[waddr][i] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`else + `define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`endif + +`TRACING_OFF +module VX_dp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter WRENW = 1, + parameter OUT_REG = 0, + parameter LUTRAM = 0, + parameter `STRING RDW_MODE = "W", // W: write-first, R: read-first + parameter RADDR_REG = 0, // read address registered hint + parameter RADDR_RESET = 0, // read address has reset + parameter RDW_ASSERT = 0, + parameter RESET_RAM = 0, + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, + input wire [ADDRW-1:0] waddr, + input wire [DATAW-1:0] wdata, + input wire [ADDRW-1:0] raddr, + output wire [DATAW-1:0] rdata +); + localparam WSELW = DATAW / WRENW; + `UNUSED_PARAM (LUTRAM) + `UNUSED_PARAM (RADDR_REG) + `UNUSED_PARAM (RADDR_RESET) + + `STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter")) + `STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W"), ("invalid parameter")) + `UNUSED_PARAM (RDW_ASSERT) + +`ifdef SYNTHESIS + localparam FORCE_BRAM = !LUTRAM && `FORCE_BRAM(SIZE, DATAW); + if (DATAW == 128 && SIZE == 64) begin : g_fakeram + fakeram_128x64_1r1w fakeram_128x64 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 193 && SIZE == 16) begin : g_fakeram + fakeram_193x16_1r1w fakeram_193x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 654 && SIZE == 4) begin : g_fakeram + fakeram_654x4_1r1w fakeram_654x4 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 560 && SIZE == 4) begin : g_fakeram + fakeram_560x4_1r1w fakeram_560x4 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 21 && SIZE == 256) begin : g_fakeram + fakeram_21x256_1r1w fakeram_21x256 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 192 && SIZE == 16) begin : g_fakeram + fakeram_192x16_1r1w fakeram_192x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 85 && SIZE == 16) begin : g_fakeram + fakeram_85x16_1r1w fakeram_85x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 21 && SIZE == 64) begin : g_fakeram + fakeram_21x64_1r1w fakeram_21x64 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (DATAW == 87 && SIZE == 16) begin : g_fakeram + fakeram_87x16_1r1w fakeram_87x16 ( + .w0_clk (clk), + .r0_clk (clk), + .w0_ce_in (write), + .r0_ce_in (read), + .w0_we_in (write), + .w0_addr_in(waddr), + .w0_wd_in (wdata), + .w0_wmask_in(wren), + .r0_addr_in(raddr), + .r0_rd_out (rdata) + ); + end else if (OUT_REG) begin : g_sync + if (FORCE_BRAM) begin : g_bram + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end else begin : g_no_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end + end + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end else begin : g_no_wren + `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end + end + end + end else begin : g_async + `UNUSED_VAR (read) + if (FORCE_BRAM) begin : g_bram + `ifdef ASYNC_BRAM_PATCH + VX_async_ram_patch #( + .DATAW (DATAW), + .SIZE (SIZE), + .WRENW (WRENW), + .DUAL_PORT (1), + .FORCE_BRAM (FORCE_BRAM), + .RADDR_REG (RADDR_REG), + .RADDR_RESET(RADDR_RESET), + .WRITE_FIRST(RDW_MODE == "W"), + .INIT_ENABLE(INIT_ENABLE), + .INIT_FILE (INIT_FILE), + .INIT_VALUE (INIT_VALUE) + ) async_ram_patch ( + .clk (clk), + .reset (reset), + .read (read), + .write (write), + .wren (wren), + .waddr (waddr), + .wdata (wdata), + .raddr (raddr), + .rdata (rdata) + ); + `else + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end + `endif + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[raddr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[raddr]; + end + end + end + end +`else + // simulation + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + + if (WRENW != 1) begin : g_wren + reg [DATAW-1:0] wdata_n; + always @(*) begin + wdata_n = ram[waddr]; + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) begin + wdata_n[i * WSELW +: WSELW] = wdata[i * WSELW +: WSELW]; + end + end + end + always @(posedge clk) begin + `RAM_RESET_BLOCK + if (write) begin + ram[waddr] <= wdata_n; + end + end + end else begin : g_no_wren + `UNUSED_VAR (wren) + always @(posedge clk) begin + `RAM_WRITE_ALL + end + end + + if (OUT_REG) begin : g_sync + if (RDW_MODE == "W") begin : g_write_first + reg [ADDRW-1:0] raddr_r; + always @(posedge clk) begin + if (read) begin + raddr_r <= raddr; + end + end + assign rdata = ram[raddr_r]; + end else if (RDW_MODE == "R") begin : g_read_first + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (read) begin + rdata_r <= ram[raddr]; + end + end + assign rdata = rdata_r; + end + end else begin : g_async + `UNUSED_VAR (read) + if (RDW_MODE == "W") begin : g_write_first + assign rdata = ram[raddr]; + end else begin : g_read_first + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + + always @(posedge clk) begin + if (reset) begin + prev_write <= 0; + prev_data <= '0; + prev_waddr <= '0; + end else begin + prev_write <= write; + prev_data <= ram[waddr]; + prev_waddr <= waddr; + end + end + + assign rdata = (prev_write && (prev_waddr == raddr)) ? prev_data : ram[raddr]; + if (RDW_ASSERT) begin : g_rw_asert + `RUNTIME_ASSERT(~read || (rdata == ram[raddr]), ("%t: read after write hazard", $time)) + end + end + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_edge_trigger.sv b/designs/src/vortex/rtl/libs/VX_edge_trigger.sv new file mode 100644 index 0000000..9e87698 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_edge_trigger.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_edge_trigger #( + parameter POS = 0, + parameter INIT = 0 +) ( + input wire clk, + input wire reset, + input wire data_in, + output wire data_out +); + reg prev; + + always @(posedge clk) begin + if (reset) begin + prev <= INIT; + end else begin + prev <= data_in; + end + end + + if (POS != 0) begin : g_pos + assign data_out = data_in & ~prev; + end else begin : g_neg + assign data_out = ~data_in & prev; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_elastic_adapter.sv b/designs/src/vortex/rtl/libs/VX_elastic_adapter.sv new file mode 100644 index 0000000..8a24a80 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_elastic_adapter.sv @@ -0,0 +1,53 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_elastic_adapter ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + + input wire ready_out, + output wire valid_out, + + input wire busy, + output wire strobe +); + wire push = valid_in && ready_in; + wire pop = valid_out && ready_out; + + reg loaded; + + always @(posedge clk) begin + if (reset) begin + loaded <= 0; + end else begin + if (push) begin + loaded <= 1; + end + if (pop) begin + loaded <= 0; + end + end + end + + assign ready_in = ~loaded; + assign valid_out = loaded && ~busy; + assign strobe = push; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_elastic_buffer.sv b/designs/src/vortex/rtl/libs/VX_elastic_buffer.sv new file mode 100644 index 0000000..c90aa06 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_elastic_buffer.sv @@ -0,0 +1,143 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_elastic_buffer #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter OUT_REG = 0, + parameter LUTRAM = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (SIZE == 0) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign valid_out = valid_in; + assign data_out = data_in; + assign ready_in = ready_out; + + end else if (SIZE == 1) begin : g_eb1 + + VX_pipe_buffer #( + .DATAW (DATAW), + .DEPTH (`MAX(OUT_REG, 1)) + ) pipe_buffer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .ready_in (ready_in), + .valid_out (valid_out), + .data_out (data_out), + .ready_out (ready_out) + ); + + end else if (SIZE == 2 && LUTRAM == 0) begin : g_eb2 + + wire valid_out_t; + wire [DATAW-1:0] data_out_t; + wire ready_out_t; + + VX_stream_buffer #( + .DATAW (DATAW), + .OUT_REG (OUT_REG == 1) + ) stream_buffer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .ready_in (ready_in), + .valid_out (valid_out_t), + .data_out (data_out_t), + .ready_out (ready_out_t) + ); + + VX_pipe_buffer #( + .DATAW (DATAW), + .DEPTH ((OUT_REG > 1) ? (OUT_REG-1) : 0) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_t), + .data_in (data_out_t), + .ready_in (ready_out_t), + .valid_out (valid_out), + .data_out (data_out), + .ready_out (ready_out) + ); + + end else begin : g_ebN + + wire empty, full; + + wire [DATAW-1:0] data_out_t; + wire ready_out_t; + + wire valid_out_t = ~empty; + + wire push = valid_in && ready_in; + wire pop = valid_out_t && ready_out_t; + + VX_fifo_queue #( + .DATAW (DATAW), + .DEPTH (SIZE), + .OUT_REG (OUT_REG == 1), + .LUTRAM (LUTRAM) + ) fifo_queue ( + .clk (clk), + .reset (reset), + .push (push), + .pop (pop), + .data_in(data_in), + .data_out(data_out_t), + .empty (empty), + .full (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + assign ready_in = ~full; + + VX_pipe_buffer #( + .DATAW (DATAW), + .DEPTH ((OUT_REG > 1) ? (OUT_REG-1) : 0) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_t), + .data_in (data_out_t), + .ready_in (ready_out_t), + .valid_out (valid_out), + .data_out (data_out), + .ready_out (ready_out) + ); + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_fifo_queue.sv b/designs/src/vortex/rtl/libs/VX_fifo_queue.sv new file mode 100644 index 0000000..615484a --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_fifo_queue.sv @@ -0,0 +1,133 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_fifo_queue #( + parameter DATAW = 32, + parameter DEPTH = 32, + parameter ALM_FULL = (DEPTH - 1), + parameter ALM_EMPTY = 1, + parameter OUT_REG = 0, + parameter LUTRAM = 0, + parameter SIZEW = `CLOG2(DEPTH+1) +) ( + input wire clk, + input wire reset, + input wire push, + input wire pop, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + output wire empty, + output wire alm_empty, + output wire full, + output wire alm_full, + output wire [SIZEW-1:0] size +); + + `STATIC_ASSERT(ALM_FULL > 0, ("alm_full must be greater than 0!")) + `STATIC_ASSERT(ALM_FULL < DEPTH, ("alm_full must be smaller than size!")) + `STATIC_ASSERT(ALM_EMPTY > 0, ("alm_empty must be greater than 0!")) + `STATIC_ASSERT(ALM_EMPTY < DEPTH, ("alm_empty must be smaller than size!")) + `STATIC_ASSERT(`IS_POW2(DEPTH), ("depth must be a power of 2!")) + + VX_pending_size #( + .SIZE (DEPTH), + .ALM_EMPTY (ALM_EMPTY), + .ALM_FULL (ALM_FULL) + ) pending_size ( + .clk (clk), + .reset (reset), + .incr (push), + .decr (pop), + .empty (empty), + .full (full), + .alm_empty(alm_empty), + .alm_full(alm_full), + .size (size) + ); + + if (DEPTH == 1) begin : g_depth_1 + `UNUSED_PARAM (OUT_REG) + `UNUSED_PARAM (LUTRAM) + + reg [DATAW-1:0] head_r; + + always @(posedge clk) begin + if (push) begin + head_r <= data_in; + end + end + + assign data_out = head_r; + + end else begin : g_depth_n + + localparam ADDRW = `CLOG2(DEPTH); + + wire [DATAW-1:0] data_out_w; + reg [ADDRW-1:0] rd_ptr_r; + reg [ADDRW-1:0] wr_ptr_r; + + always @(posedge clk) begin + if (reset) begin + wr_ptr_r <= '0; + rd_ptr_r <= (OUT_REG != 0) ? 1 : 0; + end else begin + wr_ptr_r <= wr_ptr_r + ADDRW'(push); + rd_ptr_r <= rd_ptr_r + ADDRW'(pop); + end + end + + VX_dp_ram #( + .DATAW (DATAW), + .SIZE (DEPTH), + .LUTRAM (LUTRAM), + .RDW_MODE ("W"), + .RADDR_REG (1), + .RADDR_RESET (1) + ) dp_ram ( + .clk (clk), + .reset (reset), + .read (1'b1), + .write (push), + .wren (1'b1), + .raddr (rd_ptr_r), + .waddr (wr_ptr_r), + .wdata (data_in), + .rdata (data_out_w) + ); + + if (OUT_REG != 0) begin : g_out_reg + reg [DATAW-1:0] data_out_r; + wire going_empty = (ALM_EMPTY == 1) ? alm_empty : (size[ADDRW-1:0] == ADDRW'(1)); + wire bypass = push && (empty || (going_empty && pop)); + always @(posedge clk) begin + if (bypass) begin + data_out_r <= data_in; + end else if (pop) begin + data_out_r <= data_out_w; + end + end + assign data_out = data_out_r; + end else begin : g_no_out_reg + assign data_out = data_out_w; + end + end + + `RUNTIME_ASSERT(~(push && ~pop) || ~full, ("%t: runtime error: incrementing full queue", $time)) + `RUNTIME_ASSERT(~(pop && ~push) || ~empty, ("%t: runtime error: decrementing empty queue", $time)) + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_find_first.sv b/designs/src/vortex/rtl/libs/VX_find_first.sv new file mode 100644 index 0000000..b497fd1 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_find_first.sv @@ -0,0 +1,61 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_find_first #( + parameter N = 1, + parameter DATAW = 1, + parameter REVERSE = 0 // 0 -> first valid, 1 -> last valid +) ( + input wire [N-1:0][DATAW-1:0] data_in, + input wire [N-1:0] valid_in, + output wire [DATAW-1:0] data_out, + output wire valid_out +); + localparam LOGN = `CLOG2(N); + localparam TL = (1 << LOGN) - 1; + localparam TN = (1 << (LOGN+1)) - 1; + +`IGNORE_UNOPTFLAT_BEGIN + wire s_n [TN]; + wire [DATAW-1:0] d_n [TN]; +`IGNORE_UNOPTFLAT_END + + for (genvar i = 0; i < N; ++i) begin : g_fill + assign s_n[TL+i] = REVERSE ? valid_in[N-1-i] : valid_in[i]; + assign d_n[TL+i] = REVERSE ? data_in[N-1-i] : data_in[i]; + end + + if (TL < (TN-N)) begin : g_padding + for (genvar i = TL+N; i < TN; ++i) begin : g_i + assign s_n[i] = 0; + assign d_n[i] = '0; + end + end + + for (genvar j = 0; j < LOGN; ++j) begin : g_scan + localparam I = 1 << j; + for (genvar i = 0; i < I; ++i) begin : g_i + localparam K = I+i-1; + assign s_n[K] = s_n[2*K+2] | s_n[2*K+1]; + assign d_n[K] = s_n[2*K+1] ? d_n[2*K+1] : d_n[2*K+2]; + end + end + + assign valid_out = s_n[0]; + assign data_out = d_n[0]; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_generic_arbiter.sv b/designs/src/vortex/rtl/libs/VX_generic_arbiter.sv new file mode 100644 index 0000000..a79448e --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_generic_arbiter.sv @@ -0,0 +1,102 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_generic_arbiter #( + parameter NUM_REQS = 1, + parameter `STRING TYPE = "P", // P: priority, R: round-robin, M: matrix, C: cyclic + parameter STICKY = 0, // hold the grant until its request is deasserted + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) +) ( + input wire clk, + input wire reset, + input wire [NUM_REQS-1:0] requests, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid, + input wire grant_ready +); + `STATIC_ASSERT((TYPE == "P" || TYPE == "R" || TYPE == "M" || TYPE == "C"), ("invalid parameter")) + + if (TYPE == "P") begin : g_priority + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (grant_ready) + + VX_priority_arbiter #( + .NUM_REQS (NUM_REQS), + .STICKY (STICKY) + ) priority_arbiter ( + .clk (clk), + .reset (reset), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot), + .grant_ready (grant_ready) + ); + + end else if (TYPE == "R") begin : g_round_robin + + VX_rr_arbiter #( + .NUM_REQS (NUM_REQS), + .STICKY (STICKY) + ) rr_arbiter ( + .clk (clk), + .reset (reset), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot), + .grant_ready (grant_ready) + ); + + end else if (TYPE == "M") begin : g_matrix + + VX_matrix_arbiter #( + .NUM_REQS (NUM_REQS), + .STICKY (STICKY) + ) matrix_arbiter ( + .clk (clk), + .reset (reset), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot), + .grant_ready (grant_ready) + ); + + end else if (TYPE == "C") begin : g_cyclic + + VX_cyclic_arbiter #( + .NUM_REQS (NUM_REQS), + .STICKY (STICKY) + ) cyclic_arbiter ( + .clk (clk), + .reset (reset), + .requests (requests), + .grant_valid (grant_valid), + .grant_index (grant_index), + .grant_onehot (grant_onehot), + .grant_ready (grant_ready) + ); + + end + + `RUNTIME_ASSERT (((~(| requests) != 1) || (grant_valid && (requests[grant_index] != 0) && (grant_onehot == (NUM_REQS'(1) << grant_index)))), ("%t: invalid arbiter grant!", $time)) + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_index_buffer.sv b/designs/src/vortex/rtl/libs/VX_index_buffer.sv new file mode 100644 index 0000000..8d0320c --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_index_buffer.sv @@ -0,0 +1,69 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_index_buffer #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter LUTRAM = 0, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + + output wire [ADDRW-1:0] write_addr, + input wire [DATAW-1:0] write_data, + input wire acquire_en, + + input wire [ADDRW-1:0] read_addr, + output wire [DATAW-1:0] read_data, + input wire release_en, + + output wire empty, + output wire full +); + + VX_allocator #( + .SIZE (SIZE) + ) allocator ( + .clk (clk), + .reset (reset), + .acquire_en (acquire_en), + .acquire_addr (write_addr), + .release_en (release_en), + .release_addr (read_addr), + .empty (empty), + .full (full) + ); + + VX_dp_ram #( + .DATAW (DATAW), + .SIZE (SIZE), + .LUTRAM (LUTRAM), + .RDW_MODE ("W") + ) data_table ( + .clk (clk), + .reset (reset), + .read (1'b1), + .write (acquire_en), + .wren (1'b1), + .waddr (write_addr), + .wdata (write_data), + .raddr (read_addr), + .rdata (read_data) + ); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_index_queue.sv b/designs/src/vortex/rtl/libs/VX_index_queue.sv new file mode 100644 index 0000000..e73db0f --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_index_queue.sv @@ -0,0 +1,77 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_index_queue #( + parameter DATAW = 1, + parameter SIZE = 1 +) ( + input wire clk, + input wire reset, + input wire [DATAW-1:0] write_data, + output wire [`LOG2UP(SIZE)-1:0] write_addr, + input wire push, + input wire pop, + output wire full, + output wire empty, + input wire [`LOG2UP(SIZE)-1:0] read_addr, + output wire [DATAW-1:0] read_data +); + reg [DATAW-1:0] entries [SIZE-1:0]; + reg [SIZE-1:0] valid; + reg [`LOG2UP(SIZE):0] rd_ptr, wr_ptr; + + wire [`LOG2UP(SIZE)-1:0] rd_a, wr_a; + wire enqueue, dequeue; + + assign rd_a = rd_ptr[`LOG2UP(SIZE)-1:0]; + assign wr_a = wr_ptr[`LOG2UP(SIZE)-1:0]; + + assign empty = (wr_ptr == rd_ptr); + assign full = (wr_a == rd_a) && (wr_ptr[`LOG2UP(SIZE)] != rd_ptr[`LOG2UP(SIZE)]); + + assign enqueue = push; + assign dequeue = !empty && !valid[rd_a]; // auto-remove when head is invalid + + `RUNTIME_ASSERT(!push || !full, ("%t: *** invalid inputs", $time)) + + always @(posedge clk) begin + if (reset) begin + rd_ptr <= '0; + wr_ptr <= '0; + valid <= '0; + end else begin + if (enqueue) begin + valid[wr_a] <= 1; + wr_ptr <= wr_ptr + 1; + end + if (dequeue) begin + rd_ptr <= rd_ptr + 1; + end + if (pop) begin + valid[read_addr] <= 0; + end + end + + if (enqueue) begin + entries[wr_a] <= write_data; + end + end + + assign write_addr = wr_a; + assign read_data = entries[read_addr]; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_lzc.sv b/designs/src/vortex/rtl/libs/VX_lzc.sv new file mode 100644 index 0000000..d595e0b --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_lzc.sv @@ -0,0 +1,54 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_lzc #( + parameter N = 2, + parameter REVERSE = 0, // 0 -> leading zero, 1 -> trailing zero, + parameter LOGN = `LOG2UP(N) +) ( + input wire [N-1:0] data_in, + output wire [LOGN-1:0] data_out, + output wire valid_out +); + if (N == 1) begin : g_passthru + + `UNUSED_PARAM (REVERSE) + + assign data_out = '0; + assign valid_out = data_in; + + end else begin : g_lzc + + wire [N-1:0][LOGN-1:0] indices; + for (genvar i = 0; i < N; ++i) begin : g_indices + assign indices[i] = REVERSE ? LOGN'(i) : LOGN'(N-1-i); + end + + VX_find_first #( + .N (N), + .DATAW (LOGN), + .REVERSE (!REVERSE) + ) find_first ( + .valid_in (data_in), + .data_in (indices), + .data_out (data_out), + .valid_out (valid_out) + ); + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_matrix_arbiter.sv b/designs/src/vortex/rtl/libs/VX_matrix_arbiter.sv new file mode 100644 index 0000000..2c804f1 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_matrix_arbiter.sv @@ -0,0 +1,105 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_matrix_arbiter #( + parameter NUM_REQS = 1, + parameter STICKY = 0, // hold the grant until its request is deasserted + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) +) ( + input wire clk, + input wire reset, + input wire [NUM_REQS-1:0] requests, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid, + input wire grant_ready +); + if (NUM_REQS == 1) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (grant_ready) + `UNUSED_PARAM (STICKY) + + assign grant_index = '0; + assign grant_onehot = requests; + assign grant_valid = requests[0]; + + end else begin : g_arbiter + + reg [NUM_REQS-1:1] state [NUM_REQS-1:0]; + wire [NUM_REQS-1:0] pri [NUM_REQS-1:0]; + wire [NUM_REQS-1:0] grant; + + reg [NUM_REQS-1:0] prev_grant; + + always @(posedge clk) begin + if (reset) begin + prev_grant <= '0; + end else if (grant_valid && grant_ready) begin + prev_grant <= grant_onehot; + end + end + + wire retain_grant = (STICKY != 0) && (|(prev_grant & requests)); + + wire [NUM_REQS-1:0] grant_w = retain_grant ? prev_grant : grant; + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_pri_r + for (genvar c = 0; c < NUM_REQS; ++c) begin : g_pri_c + if (r > c) begin : g_row + assign pri[r][c] = requests[c] && state[c][r]; + end else if (r < c) begin : g_col + assign pri[r][c] = requests[c] && !state[r][c]; + end else begin : g_equal + assign pri[r][c] = 0; + end + end + end + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_grant + assign grant[r] = requests[r] && ~(| pri[r]); + end + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_state_r + for (genvar c = r + 1; c < NUM_REQS; ++c) begin : g_state_c + always @(posedge clk) begin + if (reset) begin + state[r][c] <= '0; + end else if (grant_valid && grant_ready && ~retain_grant) begin + state[r][c] <= (state[r][c] || grant[c]) && ~grant[r]; + end + end + end + end + + assign grant_onehot = grant_w; + + wire grant_valid_w; + + VX_onehot_encoder #( + .N (NUM_REQS) + ) encoder ( + .data_in (grant_w), + .data_out (grant_index), + .valid_out (grant_valid_w) + ); + + assign grant_valid = (STICKY != 0) ? (| requests) : grant_valid_w; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_mem_bank_adapter.sv b/designs/src/vortex/rtl/libs/VX_mem_bank_adapter.sv new file mode 100644 index 0000000..252a37a --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_mem_bank_adapter.sv @@ -0,0 +1,261 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_bank_adapter #( + parameter DATA_WIDTH = 512, + parameter ADDR_WIDTH_IN = 26, // word-addressable + parameter ADDR_WIDTH_OUT = 32, // byte-addressable + parameter TAG_WIDTH_IN = 8, + parameter TAG_WIDTH_OUT = 8, + parameter NUM_PORTS_IN = 1, + parameter NUM_BANKS_OUT = 1, + parameter INTERLEAVE = 0, + parameter TAG_BUFFER_SIZE= 32, + parameter ARBITER = "R", + parameter REQ_OUT_BUF = 1, + parameter RSP_OUT_BUF = 1, + parameter DATA_SIZE = DATA_WIDTH/8 + ) ( + input wire clk, + input wire reset, + + // Input request + input wire mem_req_valid_in [NUM_PORTS_IN], + input wire mem_req_rw_in [NUM_PORTS_IN], + input wire [DATA_SIZE-1:0] mem_req_byteen_in [NUM_PORTS_IN], + input wire [ADDR_WIDTH_IN-1:0] mem_req_addr_in [NUM_PORTS_IN], + input wire [DATA_WIDTH-1:0] mem_req_data_in [NUM_PORTS_IN], + input wire [TAG_WIDTH_IN-1:0] mem_req_tag_in [NUM_PORTS_IN], + output wire mem_req_ready_in [NUM_PORTS_IN], + + // Input response + output wire mem_rsp_valid_in [NUM_PORTS_IN], + output wire [DATA_WIDTH-1:0] mem_rsp_data_in [NUM_PORTS_IN], + output wire [TAG_WIDTH_IN-1:0] mem_rsp_tag_in [NUM_PORTS_IN], + input wire mem_rsp_ready_in [NUM_PORTS_IN], + + // Output request + output wire mem_req_valid_out [NUM_BANKS_OUT], + output wire mem_req_rw_out [NUM_BANKS_OUT], + output wire [DATA_SIZE-1:0] mem_req_byteen_out [NUM_BANKS_OUT], + output wire [ADDR_WIDTH_OUT-1:0] mem_req_addr_out [NUM_BANKS_OUT], + output wire [DATA_WIDTH-1:0] mem_req_data_out [NUM_BANKS_OUT], + output wire [TAG_WIDTH_OUT-1:0] mem_req_tag_out [NUM_BANKS_OUT], + input wire mem_req_ready_out [NUM_BANKS_OUT], + + // Output response + input wire mem_rsp_valid_out [NUM_BANKS_OUT], + input wire [DATA_WIDTH-1:0] mem_rsp_data_out [NUM_BANKS_OUT], + input wire [TAG_WIDTH_OUT-1:0] mem_rsp_tag_out [NUM_BANKS_OUT], + output wire mem_rsp_ready_out [NUM_BANKS_OUT] +); + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS_OUT); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam DST_ADDR_WDITH = ADDR_WIDTH_OUT + BANK_SEL_BITS; // convert output addresss to input space + localparam BANK_ADDR_WIDTH = DST_ADDR_WDITH - BANK_SEL_BITS; + localparam NUM_PORTS_IN_BITS = `CLOG2(NUM_PORTS_IN); + localparam NUM_PORTS_IN_WIDTH = `UP(NUM_PORTS_IN_BITS); + localparam TAG_BUFFER_ADDRW = `CLOG2(TAG_BUFFER_SIZE); + localparam NEEDED_TAG_WIDTH = TAG_WIDTH_IN + NUM_PORTS_IN_BITS; + localparam READ_TAG_WIDTH = (NEEDED_TAG_WIDTH > TAG_WIDTH_OUT) ? TAG_BUFFER_ADDRW : TAG_WIDTH_IN; + localparam WRITE_TAG_WIDTH = TAG_WIDTH_IN; + localparam XBAR_TAG_WIDTH = `MAX(READ_TAG_WIDTH, WRITE_TAG_WIDTH); + localparam DST_TAG_WIDTH = XBAR_TAG_WIDTH + NUM_PORTS_IN_BITS; + localparam REQ_XBAR_DATAW = 1 + BANK_ADDR_WIDTH + DATA_SIZE + DATA_WIDTH + XBAR_TAG_WIDTH; + localparam RSP_XBAR_DATAW = DATA_WIDTH + READ_TAG_WIDTH; + + `STATIC_ASSERT ((DST_ADDR_WDITH >= ADDR_WIDTH_IN), ("invalid address width: current=%0d, expected=%0d", DST_ADDR_WDITH, ADDR_WIDTH_IN)) + `STATIC_ASSERT ((TAG_WIDTH_OUT >= DST_TAG_WIDTH), ("invalid output tag width: current=%0d, expected=%0d", TAG_WIDTH_OUT, DST_TAG_WIDTH)) + + // Bank selection + + wire [NUM_PORTS_IN-1:0][BANK_SEL_WIDTH-1:0] req_bank_sel; + wire [NUM_PORTS_IN-1:0][BANK_ADDR_WIDTH-1:0] req_bank_addr; + + if (NUM_BANKS_OUT > 1) begin : g_bank_sel + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_i + wire [DST_ADDR_WDITH-1:0] mem_req_addr_dst = DST_ADDR_WDITH'(mem_req_addr_in[i]); + if (INTERLEAVE) begin : g_interleave + assign req_bank_sel[i] = mem_req_addr_dst[BANK_SEL_BITS-1:0]; + assign req_bank_addr[i] = mem_req_addr_dst[BANK_SEL_BITS +: BANK_ADDR_WIDTH]; + end else begin : g_no_interleave + assign req_bank_sel[i] = mem_req_addr_dst[BANK_ADDR_WIDTH +: BANK_SEL_BITS]; + assign req_bank_addr[i] = mem_req_addr_dst[BANK_ADDR_WIDTH-1:0]; + end + end + end else begin : g_no_bank_sel + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_i + assign req_bank_sel[i] = '0; + assign req_bank_addr[i] = DST_ADDR_WDITH'(mem_req_addr_in[i]); + end + end + + // Tag handling logic + + wire [NUM_PORTS_IN-1:0] mem_rd_req_tag_in_ready; + wire [NUM_PORTS_IN-1:0][READ_TAG_WIDTH-1:0] mem_rd_req_tag_in; + wire [NUM_PORTS_IN-1:0][READ_TAG_WIDTH-1:0] mem_rd_rsp_tag_in; + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_tag_buf + if (NEEDED_TAG_WIDTH > TAG_WIDTH_OUT) begin : g_enabled + wire [TAG_BUFFER_ADDRW-1:0] tbuf_waddr, tbuf_raddr; + wire tbuf_full; + VX_index_buffer #( + .DATAW (TAG_WIDTH_IN), + .SIZE (TAG_BUFFER_SIZE) + ) tag_buf ( + .clk (clk), + .reset (reset), + .acquire_en (mem_req_valid_in[i] && ~mem_req_rw_in[i] && mem_req_ready_in[i]), + .write_addr (tbuf_waddr), + .write_data (mem_req_tag_in[i]), + .read_data (mem_rsp_tag_in[i]), + .read_addr (tbuf_raddr), + .release_en (mem_rsp_valid_in[i] && mem_rsp_ready_in[i]), + .full (tbuf_full), + `UNUSED_PIN (empty) + ); + assign mem_rd_req_tag_in_ready[i] = ~tbuf_full; + assign mem_rd_req_tag_in[i] = tbuf_waddr; + assign tbuf_raddr = mem_rd_rsp_tag_in[i]; + end else begin : g_none + assign mem_rd_req_tag_in_ready[i] = 1; + assign mem_rd_req_tag_in[i] = mem_req_tag_in[i]; + assign mem_rsp_tag_in[i] = mem_rd_rsp_tag_in[i]; + end + end + + // Requests handling + + wire [NUM_PORTS_IN-1:0] req_xbar_valid_in; + wire [NUM_PORTS_IN-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_in; + wire [NUM_PORTS_IN-1:0] req_xbar_ready_in; + + wire [NUM_BANKS_OUT-1:0] req_xbar_valid_out; + wire [NUM_BANKS_OUT-1:0][REQ_XBAR_DATAW-1:0] req_xbar_data_out; + wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] req_xbar_sel_out; + wire [NUM_BANKS_OUT-1:0] req_xbar_ready_out; + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_req_xbar_data_in + wire tag_ready = mem_req_rw_in[i] || mem_rd_req_tag_in_ready[i]; + wire [XBAR_TAG_WIDTH-1:0] tag_value = mem_req_rw_in[i] ? XBAR_TAG_WIDTH'(mem_req_tag_in[i]) : XBAR_TAG_WIDTH'(mem_rd_req_tag_in[i]); + assign req_xbar_valid_in[i] = mem_req_valid_in[i] && tag_ready; + assign req_xbar_data_in[i] = {mem_req_rw_in[i], req_bank_addr[i], mem_req_byteen_in[i], mem_req_data_in[i], tag_value}; + assign mem_req_ready_in[i] = req_xbar_ready_in[i] && tag_ready; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_PORTS_IN), + .NUM_OUTPUTS(NUM_BANKS_OUT), + .DATAW (REQ_XBAR_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (REQ_OUT_BUF) + ) req_xbar ( + .clk (clk), + .reset (reset), + .sel_in (req_bank_sel), + .valid_in (req_xbar_valid_in), + .data_in (req_xbar_data_in), + .ready_in (req_xbar_ready_in), + .valid_out (req_xbar_valid_out), + .data_out (req_xbar_data_out), + .ready_out (req_xbar_ready_out), + .sel_out (req_xbar_sel_out), + `UNUSED_PIN (collisions) + ); + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_req_xbar_data_out + + wire xbar_rw_out; + wire [BANK_ADDR_WIDTH-1:0] xbar_addr_out; + wire [XBAR_TAG_WIDTH-1:0] xbar_tag_out; + wire [DATA_WIDTH-1:0] xbar_data_out; + wire [DATA_SIZE-1:0] xbar_byteen_out; + + assign { + xbar_rw_out, + xbar_addr_out, + xbar_byteen_out, + xbar_data_out, + xbar_tag_out + } = req_xbar_data_out[i]; + + assign mem_req_valid_out[i] = req_xbar_valid_out[i]; + assign mem_req_rw_out[i] = xbar_rw_out; + assign mem_req_addr_out[i] = ADDR_WIDTH_OUT'(xbar_addr_out); + assign mem_req_byteen_out[i] = xbar_byteen_out; + assign mem_req_data_out[i] = xbar_data_out; + + if (NUM_PORTS_IN > 1) begin : g_input_sel + assign mem_req_tag_out[i] = TAG_WIDTH_OUT'({xbar_tag_out, req_xbar_sel_out[i]}); + end else begin : g_no_input_sel + `UNUSED_VAR (req_xbar_sel_out[i]) + assign mem_req_tag_out[i] = TAG_WIDTH_OUT'(xbar_tag_out); + end + + assign req_xbar_ready_out[i] = mem_req_ready_out[i]; + end + + // Responses handling + + wire [NUM_BANKS_OUT-1:0] rsp_xbar_valid_in; + wire [NUM_BANKS_OUT-1:0][RSP_XBAR_DATAW-1:0] rsp_xbar_data_in; + wire [NUM_BANKS_OUT-1:0][NUM_PORTS_IN_WIDTH-1:0] rsp_xbar_sel_in; + wire [NUM_BANKS_OUT-1:0] rsp_xbar_ready_in; + + for (genvar i = 0; i < NUM_BANKS_OUT; ++i) begin : g_rsp_xbar_data_in + assign rsp_xbar_valid_in[i] = mem_rsp_valid_out[i]; + assign rsp_xbar_data_in[i] = {mem_rsp_data_out[i], mem_rsp_tag_out[i][NUM_PORTS_IN_BITS +: READ_TAG_WIDTH]}; + if (NUM_PORTS_IN > 1) begin : g_input_sel + assign rsp_xbar_sel_in[i] = mem_rsp_tag_out[i][0 +: NUM_PORTS_IN_BITS]; + end else begin : g_no_input_sel + assign rsp_xbar_sel_in[i] = 0; + end + assign mem_rsp_ready_out[i] = rsp_xbar_ready_in[i]; + end + + wire [NUM_PORTS_IN-1:0] rsp_xbar_valid_out; + wire [NUM_PORTS_IN-1:0][DATA_WIDTH+READ_TAG_WIDTH-1:0] rsp_xbar_data_out; + wire [NUM_PORTS_IN-1:0] rsp_xbar_ready_out; + + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS_OUT), + .NUM_OUTPUTS(NUM_PORTS_IN), + .DATAW (RSP_XBAR_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_xbar ( + .clk (clk), + .reset (reset), + .valid_in (rsp_xbar_valid_in), + .data_in (rsp_xbar_data_in), + .ready_in (rsp_xbar_ready_in), + .sel_in (rsp_xbar_sel_in), + .data_out (rsp_xbar_data_out), + .valid_out (rsp_xbar_valid_out), + .ready_out (rsp_xbar_ready_out), + `UNUSED_PIN (collisions), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_PORTS_IN; ++i) begin : g_rsp_xbar_data_out + assign mem_rsp_valid_in[i] = rsp_xbar_valid_out[i]; + assign {mem_rsp_data_in[i], mem_rd_rsp_tag_in[i]} = rsp_xbar_data_out[i]; + assign rsp_xbar_ready_out[i] = mem_rsp_ready_in[i]; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_mem_coalescer.sv b/designs/src/vortex/rtl/libs/VX_mem_coalescer.sv new file mode 100644 index 0000000..9f0f948 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_mem_coalescer.sv @@ -0,0 +1,404 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_coalescer #( + parameter `STRING INSTANCE_ID = "", + parameter NUM_REQS = 1, + parameter ADDR_WIDTH = 32, + parameter FLAGS_WIDTH = 0, + parameter DATA_IN_SIZE = 4, + parameter DATA_OUT_SIZE = 64, + parameter TAG_WIDTH = 8, + parameter UUID_WIDTH = 0, // upper section of the request tag contains the UUID + parameter QUEUE_SIZE = 8, + parameter PERF_CTR_BITS = `CLOG2(NUM_REQS+1), + + parameter DATA_IN_WIDTH = DATA_IN_SIZE * 8, + parameter DATA_OUT_WIDTH= DATA_OUT_SIZE * 8, + parameter DATA_RATIO = DATA_OUT_SIZE / DATA_IN_SIZE, + parameter DATA_RATIO_W = `LOG2UP(DATA_RATIO), + parameter OUT_REQS = NUM_REQS / DATA_RATIO, + parameter OUT_ADDR_WIDTH= ADDR_WIDTH - DATA_RATIO_W, + parameter QUEUE_ADDRW = `CLOG2(QUEUE_SIZE), + parameter OUT_TAG_WIDTH = UUID_WIDTH + QUEUE_ADDRW +) ( + input wire clk, + input wire reset, + + output wire [PERF_CTR_BITS-1:0] misses, + + // Input request + input wire in_req_valid, + input wire in_req_rw, + input wire [NUM_REQS-1:0] in_req_mask, + input wire [NUM_REQS-1:0][DATA_IN_SIZE-1:0] in_req_byteen, + input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] in_req_addr, + input wire [NUM_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] in_req_flags, + input wire [NUM_REQS-1:0][DATA_IN_WIDTH-1:0] in_req_data, + input wire [TAG_WIDTH-1:0] in_req_tag, + output wire in_req_ready, + + // Input response + output wire in_rsp_valid, + output wire [NUM_REQS-1:0] in_rsp_mask, + output wire [NUM_REQS-1:0][DATA_IN_WIDTH-1:0] in_rsp_data, + output wire [TAG_WIDTH-1:0] in_rsp_tag, + input wire in_rsp_ready, + + // Output request + output wire out_req_valid, + output wire out_req_rw, + output wire [OUT_REQS-1:0] out_req_mask, + output wire [OUT_REQS-1:0][DATA_OUT_SIZE-1:0] out_req_byteen, + output wire [OUT_REQS-1:0][OUT_ADDR_WIDTH-1:0] out_req_addr, + output wire [OUT_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] out_req_flags, + output wire [OUT_REQS-1:0][DATA_OUT_WIDTH-1:0] out_req_data, + output wire [OUT_TAG_WIDTH-1:0] out_req_tag, + input wire out_req_ready, + + // Output response + input wire out_rsp_valid, + input wire [OUT_REQS-1:0] out_rsp_mask, + input wire [OUT_REQS-1:0][DATA_OUT_WIDTH-1:0] out_rsp_data, + input wire [OUT_TAG_WIDTH-1:0] out_rsp_tag, + output wire out_rsp_ready +); + `UNUSED_SPARAM (INSTANCE_ID) + `STATIC_ASSERT ((NUM_REQS > 1), ("invalid parameter")) + `STATIC_ASSERT (`IS_DIVISBLE(NUM_REQS * DATA_IN_WIDTH, DATA_OUT_WIDTH), ("invalid parameter")) + `STATIC_ASSERT ((NUM_REQS * DATA_IN_WIDTH >= DATA_OUT_WIDTH), ("invalid parameter")) + `RUNTIME_ASSERT ((~in_req_valid || in_req_mask != 0), ("%t: invalid request mask", $time)) + `RUNTIME_ASSERT ((~out_rsp_valid || out_rsp_mask != 0), ("%t: invalid request mask", $time)) + + localparam TAG_ID_WIDTH = TAG_WIDTH - UUID_WIDTH; + // tag + mask + offest + localparam IBUF_DATA_WIDTH = TAG_ID_WIDTH + NUM_REQS + (NUM_REQS * DATA_RATIO_W); + + localparam STATE_WAIT = 0; + localparam STATE_SEND = 1; + + logic state_r, state_n; + + logic out_req_valid_r, out_req_valid_n; + logic out_req_rw_r, out_req_rw_n; + logic [OUT_REQS-1:0] out_req_mask_r, out_req_mask_n; + logic [OUT_REQS-1:0][OUT_ADDR_WIDTH-1:0] out_req_addr_r, out_req_addr_n; + logic [OUT_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] out_req_flags_r, out_req_flags_n; + logic [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_SIZE-1:0] out_req_byteen_r, out_req_byteen_n; + logic [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_WIDTH-1:0] out_req_data_r, out_req_data_n; + logic [OUT_TAG_WIDTH-1:0] out_req_tag_r, out_req_tag_n; + + reg in_req_ready_n; + + wire ibuf_push; + wire ibuf_pop; + wire [QUEUE_ADDRW-1:0] ibuf_waddr; + wire [QUEUE_ADDRW-1:0] ibuf_raddr; + wire ibuf_full; + wire ibuf_empty; + wire [IBUF_DATA_WIDTH-1:0] ibuf_din; + wire [IBUF_DATA_WIDTH-1:0] ibuf_dout; + + logic [OUT_REQS-1:0] batch_valid_r, batch_valid_n; + logic [OUT_REQS-1:0][OUT_ADDR_WIDTH-1:0] seed_addr_r, seed_addr_n; + logic [OUT_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] seed_flags_r, seed_flags_n; + logic [NUM_REQS-1:0] addr_matches_r, addr_matches_n; + logic [NUM_REQS-1:0] req_rem_mask_r, req_rem_mask_n; + + wire [NUM_REQS-1:0][DATA_RATIO_W-1:0] in_addr_offset; + for (genvar i = 0; i < NUM_REQS; i++) begin : g_in_addr_offset + assign in_addr_offset[i] = in_req_addr[i][DATA_RATIO_W-1:0]; + end + + for (genvar i = 0; i < OUT_REQS; ++i) begin : g_seed_gen + wire [DATA_RATIO-1:0] batch_mask; + wire [DATA_RATIO_W-1:0] batch_idx; + + assign batch_mask = in_req_mask[i * DATA_RATIO +: DATA_RATIO] & req_rem_mask_r[i * DATA_RATIO +: DATA_RATIO]; + + VX_priority_encoder #( + .N (DATA_RATIO) + ) batch_sel ( + .data_in (batch_mask), + .index_out (batch_idx), + .valid_out (batch_valid_n[i]), + `UNUSED_PIN (onehot_out) + ); + + wire [DATA_RATIO-1:0][OUT_ADDR_WIDTH-1:0] addr_base; + for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_addr_base + assign addr_base[j] = in_req_addr[DATA_RATIO * i + j][ADDR_WIDTH-1:DATA_RATIO_W]; + end + + wire [DATA_RATIO-1:0][`UP(FLAGS_WIDTH)-1:0] req_flags; + for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_req_flags + assign req_flags[j] = in_req_flags[DATA_RATIO * i + j]; + end + + assign seed_addr_n[i] = addr_base[batch_idx]; + assign seed_flags_n[i] = req_flags[batch_idx]; + + for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_addr_matches_n + assign addr_matches_n[i * DATA_RATIO + j] = (addr_base[j] == seed_addr_n[i]); + end + end + + wire [NUM_REQS-1:0] current_pmask = in_req_mask & addr_matches_r; + + wire [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_SIZE-1:0] req_byteen_merged; + wire [OUT_REQS-1:0][DATA_RATIO-1:0][DATA_IN_WIDTH-1:0] req_data_merged; + + for (genvar i = 0; i < OUT_REQS; ++i) begin : g_data_merged + reg [DATA_RATIO-1:0][DATA_IN_SIZE-1:0] byteen_merged; + reg [DATA_RATIO-1:0][DATA_IN_WIDTH-1:0] data_merged; + always @(*) begin + byteen_merged = '0; + data_merged = 'x; + for (integer j = 0; j < DATA_RATIO; ++j) begin + for (integer k = 0; k < DATA_IN_SIZE; ++k) begin + // perform byte-level merge since each thread may have different bytes enabled + if (current_pmask[i * DATA_RATIO + j] && in_req_byteen[DATA_RATIO * i + j][k]) begin + byteen_merged[in_addr_offset[DATA_RATIO * i + j]][k] = 1'b1; + data_merged[in_addr_offset[DATA_RATIO * i + j]][k * 8 +: 8] = in_req_data[DATA_RATIO * i + j][k * 8 +: 8]; + end + end + end + end + assign req_byteen_merged[i] = byteen_merged; + assign req_data_merged[i] = data_merged; + end + + wire is_last_batch = ~(| (in_req_mask & ~addr_matches_r & req_rem_mask_r)); + + wire out_req_fire = out_req_valid && out_req_ready; + + always @(*) begin + state_n = state_r; + out_req_valid_n = out_req_valid_r; + out_req_mask_n = out_req_mask_r; + out_req_rw_n = out_req_rw_r; + out_req_addr_n = out_req_addr_r; + out_req_flags_n = out_req_flags_r; + out_req_byteen_n = out_req_byteen_r; + out_req_data_n = out_req_data_r; + out_req_tag_n = out_req_tag_r; + req_rem_mask_n = req_rem_mask_r; + in_req_ready_n = 0; + + case (state_r) + STATE_WAIT: begin + // wait for pending outgoing request to submit + if (out_req_fire) begin + out_req_valid_n = 0; + end + if (in_req_valid && ~out_req_valid_n && ~ibuf_full) begin + state_n = STATE_SEND; + end + end + default/*STATE_SEND*/: begin + state_n = STATE_WAIT; + out_req_valid_n = 1; + out_req_mask_n = batch_valid_r; + out_req_rw_n = in_req_rw; + out_req_addr_n = seed_addr_r; + out_req_flags_n = seed_flags_r; + out_req_byteen_n= req_byteen_merged; + out_req_data_n = req_data_merged; + out_req_tag_n = {in_req_tag[TAG_WIDTH-1 -: UUID_WIDTH], ibuf_waddr}; + req_rem_mask_n = is_last_batch ? '1 : (req_rem_mask_r & ~current_pmask); + in_req_ready_n = is_last_batch; + end + endcase + end + + VX_pipe_register #( + .DATAW (1 + NUM_REQS + 1 + 1 + NUM_REQS + OUT_REQS * (1 + 1 + OUT_ADDR_WIDTH + `UP(FLAGS_WIDTH) + OUT_ADDR_WIDTH + `UP(FLAGS_WIDTH) + DATA_OUT_SIZE + DATA_OUT_WIDTH) + OUT_TAG_WIDTH), + .RESETW (1 + NUM_REQS + 1), + .INIT_VALUE ({1'b0, {NUM_REQS{1'b1}}, 1'b0}) + ) pipe_reg ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({state_n, req_rem_mask_n, out_req_valid_n, out_req_rw_n, addr_matches_n, batch_valid_n, out_req_mask_n, seed_addr_n, seed_flags_n, out_req_addr_n, out_req_flags_n, out_req_byteen_n, out_req_data_n, out_req_tag_n}), + .data_out ({state_r, req_rem_mask_r, out_req_valid_r, out_req_rw_r, addr_matches_r, batch_valid_r, out_req_mask_r, seed_addr_r, seed_flags_r, out_req_addr_r, out_req_flags_r, out_req_byteen_r, out_req_data_r, out_req_tag_r}) + ); + + wire out_rsp_fire = out_rsp_valid && out_rsp_ready; + + wire out_rsp_eop; + + wire req_sent = (state_r == STATE_SEND); + + assign ibuf_push = req_sent && ~in_req_rw; + assign ibuf_pop = out_rsp_fire && out_rsp_eop; + assign ibuf_raddr = out_rsp_tag[QUEUE_ADDRW-1:0]; + + wire [TAG_ID_WIDTH-1:0] ibuf_din_tag = in_req_tag[TAG_ID_WIDTH-1:0]; + wire [NUM_REQS-1:0][DATA_RATIO_W-1:0] ibuf_din_offset = in_addr_offset; + wire [NUM_REQS-1:0] ibuf_din_pmask = current_pmask; + + assign ibuf_din = {ibuf_din_tag, ibuf_din_pmask, ibuf_din_offset}; + + VX_index_buffer #( + .DATAW (IBUF_DATA_WIDTH), + .SIZE (QUEUE_SIZE) + ) req_ibuf ( + .clk (clk), + .reset (reset), + .acquire_en (ibuf_push), + .write_addr (ibuf_waddr), + .write_data (ibuf_din), + .read_data (ibuf_dout), + .read_addr (ibuf_raddr), + .release_en (ibuf_pop), + .full (ibuf_full), + .empty (ibuf_empty) + ); + `UNUSED_VAR (ibuf_empty) + + assign out_req_valid = out_req_valid_r; + assign out_req_rw = out_req_rw_r; + assign out_req_mask = out_req_mask_r; + assign out_req_byteen = out_req_byteen_r; + assign out_req_addr = out_req_addr_r; + if (FLAGS_WIDTH != 0) begin : g_out_req_flags + assign out_req_flags = out_req_flags_r; + end else begin : g_out_req_flags_0 + `UNUSED_VAR (out_req_flags_r) + assign out_req_flags = '0; + end + assign out_req_data = out_req_data_r; + assign out_req_tag = out_req_tag_r; + + assign in_req_ready = in_req_ready_n; + + // unmerge responses + + reg [QUEUE_SIZE-1:0][OUT_REQS-1:0] rsp_rem_mask; + wire [OUT_REQS-1:0] rsp_rem_mask_n = rsp_rem_mask[ibuf_raddr] & ~out_rsp_mask; + assign out_rsp_eop = ~(| rsp_rem_mask_n); + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_rem_mask[ibuf_waddr] <= batch_valid_r; + end + if (out_rsp_fire) begin + rsp_rem_mask[ibuf_raddr] <= rsp_rem_mask_n; + end + end + + wire [NUM_REQS-1:0][DATA_RATIO_W-1:0] ibuf_dout_offset; + wire [NUM_REQS-1:0] ibuf_dout_pmask; + wire [TAG_ID_WIDTH-1:0] ibuf_dout_tag; + + assign {ibuf_dout_tag, ibuf_dout_pmask, ibuf_dout_offset} = ibuf_dout; + + wire [NUM_REQS-1:0][DATA_IN_WIDTH-1:0] in_rsp_data_n; + for (genvar i = 0; i < OUT_REQS; ++i) begin : g_in_rsp_data_n + for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_j + assign in_rsp_data_n[i * DATA_RATIO + j] = out_rsp_data[i][ibuf_dout_offset[i * DATA_RATIO + j] * DATA_IN_WIDTH +: DATA_IN_WIDTH]; + end + end + + wire [NUM_REQS-1:0] in_rsp_mask_n; + for (genvar i = 0; i < OUT_REQS; ++i) begin : g_in_rsp_mask_n + for (genvar j = 0; j < DATA_RATIO; ++j) begin : g_j + assign in_rsp_mask_n[i * DATA_RATIO + j] = out_rsp_mask[i] && ibuf_dout_pmask[i * DATA_RATIO + j]; + end + end + + assign in_rsp_valid = out_rsp_valid; + assign in_rsp_mask = in_rsp_mask_n; + assign in_rsp_data = in_rsp_data_n; + assign in_rsp_tag = {out_rsp_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH], ibuf_dout_tag}; + assign out_rsp_ready = in_rsp_ready; + + // compute coalescing misses + // misses are partial transfers (not fuly coalesced) + + reg [PERF_CTR_BITS-1:0] misses_r; + + wire partial_transfer = (out_req_fire && req_rem_mask_r != '1); + + always @(posedge clk) begin + if (reset) begin + misses_r <= '0; + end else begin + misses_r <= misses_r + PERF_CTR_BITS'(partial_transfer); + end + end + + assign misses = misses_r; + +`ifdef DBG_TRACE_MEM + wire [`UP(UUID_WIDTH)-1:0] out_req_uuid; + wire [`UP(UUID_WIDTH)-1:0] out_rsp_uuid; + + if (UUID_WIDTH != 0) begin : g_out_req_uuid + assign out_req_uuid = out_req_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_out_req_uuid_0 + assign out_req_uuid = '0; + end + + if (UUID_WIDTH != 0) begin : g_out_rsp_uuid + assign out_rsp_uuid = out_rsp_tag[OUT_TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_out_rsp_uuid_0 + assign out_rsp_uuid = '0; + end + + reg [NUM_REQS-1:0][DATA_RATIO_W-1:0] out_req_offset; + reg [NUM_REQS-1:0] out_req_pmask; + + always @(posedge clk) begin + if (req_sent) begin + out_req_offset <= ibuf_din_offset; + out_req_pmask <= ibuf_din_pmask; + end + end + + always @(posedge clk) begin + if (out_req_fire) begin + if (out_req_rw) begin + `TRACE(2, ("%t: %s out-req-wr: valid=%b, addr=", $time, INSTANCE_ID, out_req_mask)) + `TRACE_ARRAY1D(2, "0x%h", out_req_addr, OUT_REQS) + `TRACE(2, (", flags=")) + `TRACE_ARRAY1D(2, "%b", out_req_flags, OUT_REQS) + `TRACE(2, (", byteen=")) + `TRACE_ARRAY1D(2, "0x%h", out_req_byteen, OUT_REQS) + `TRACE(2, (", data=")) + `TRACE_ARRAY1D(2, "0x%0h", out_req_data, OUT_REQS) + end else begin + `TRACE(2, ("%d: %s out-req-rd: valid=%b, addr=", $time, INSTANCE_ID, out_req_mask)) + `TRACE_ARRAY1D(2, "0x%h", out_req_addr, OUT_REQS) + `TRACE(2, (", flags=")) + `TRACE_ARRAY1D(2, "%b", out_req_flags, OUT_REQS) + end + `TRACE(2, (", offset=")) + `TRACE_ARRAY1D(2, "%0d", out_req_offset, NUM_REQS) + `TRACE(2, (", pmask=%b, coalesced=%0d, tag=0x%0h (#%0d)\n", out_req_pmask, $countones(out_req_pmask), out_req_tag, out_req_uuid)) + end + if (out_rsp_fire) begin + `TRACE(2, ("%t: %s out-rsp: valid=%b, data=", $time, INSTANCE_ID, out_rsp_mask)) + `TRACE_ARRAY1D(2, "0x%0h", out_rsp_data, OUT_REQS) + `TRACE(2, (", offset=")) + `TRACE_ARRAY1D(2, "%0d", ibuf_dout_offset, NUM_REQS) + `TRACE(2, (", eop=%b, pmask=%b, tag=0x%0h (#%0d)\n", out_rsp_eop, ibuf_dout_pmask, out_rsp_tag, out_rsp_uuid)) + end + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_mem_data_adapter.sv b/designs/src/vortex/rtl/libs/VX_mem_data_adapter.sv new file mode 100644 index 0000000..653c81e --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_mem_data_adapter.sv @@ -0,0 +1,259 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_data_adapter #( + parameter SRC_DATA_WIDTH = 1, + parameter SRC_ADDR_WIDTH = 1, + parameter DST_DATA_WIDTH = 1, + parameter DST_ADDR_WIDTH = 1, + parameter SRC_TAG_WIDTH = 1, + parameter DST_TAG_WIDTH = 1, + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + input wire mem_req_valid_in, + input wire [SRC_ADDR_WIDTH-1:0] mem_req_addr_in, + input wire mem_req_rw_in, + input wire [SRC_DATA_WIDTH/8-1:0] mem_req_byteen_in, + input wire [SRC_DATA_WIDTH-1:0] mem_req_data_in, + input wire [SRC_TAG_WIDTH-1:0] mem_req_tag_in, + output wire mem_req_ready_in, + + output wire mem_rsp_valid_in, + output wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_in, + output wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_in, + input wire mem_rsp_ready_in, + + output wire mem_req_valid_out, + output wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out, + output wire mem_req_rw_out, + output wire [DST_DATA_WIDTH/8-1:0] mem_req_byteen_out, + output wire [DST_DATA_WIDTH-1:0] mem_req_data_out, + output wire [DST_TAG_WIDTH-1:0] mem_req_tag_out, + input wire mem_req_ready_out, + + input wire mem_rsp_valid_out, + input wire [DST_DATA_WIDTH-1:0] mem_rsp_data_out, + input wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_out, + output wire mem_rsp_ready_out +); + localparam DST_DATA_SIZE = (DST_DATA_WIDTH / 8); + localparam DST_LDATAW = `CLOG2(DST_DATA_WIDTH); + localparam SRC_LDATAW = `CLOG2(SRC_DATA_WIDTH); + localparam D = `ABS(DST_LDATAW - SRC_LDATAW); + localparam P = 2**D; + + localparam EXPECTED_TAG_WIDTH = SRC_TAG_WIDTH + ((DST_LDATAW > SRC_LDATAW) ? D : 0); + + `STATIC_ASSERT(DST_TAG_WIDTH >= EXPECTED_TAG_WIDTH, ("invalid DST_TAG_WIDTH parameter, current=%0d, expected=%0d", DST_TAG_WIDTH, EXPECTED_TAG_WIDTH)) + + wire mem_req_valid_out_w; + wire [DST_ADDR_WIDTH-1:0] mem_req_addr_out_w; + wire mem_req_rw_out_w; + wire [DST_DATA_WIDTH/8-1:0] mem_req_byteen_out_w; + wire [DST_DATA_WIDTH-1:0] mem_req_data_out_w; + wire [DST_TAG_WIDTH-1:0] mem_req_tag_out_w; + wire mem_req_ready_out_w; + + wire mem_rsp_valid_in_w; + wire [SRC_DATA_WIDTH-1:0] mem_rsp_data_in_w; + wire [SRC_TAG_WIDTH-1:0] mem_rsp_tag_in_w; + wire mem_rsp_ready_in_w; + + `UNUSED_VAR (mem_req_tag_in) + `UNUSED_VAR (mem_rsp_tag_out) + + if (DST_LDATAW > SRC_LDATAW) begin : g_wider_dst_data + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + wire [D-1:0] req_idx = mem_req_addr_in[D-1:0]; + wire [D-1:0] rsp_idx = mem_rsp_tag_out[D-1:0]; + + wire [SRC_ADDR_WIDTH-D-1:0] mem_req_addr_in_qual = mem_req_addr_in[SRC_ADDR_WIDTH-1:D]; + + wire [P-1:0][SRC_DATA_WIDTH-1:0] mem_rsp_data_out_w = mem_rsp_data_out; + + if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH - D)) begin : g_mem_req_addr_out_w_src + `UNUSED_VAR (mem_req_addr_in_qual) + assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0]; + end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH - D)) begin : g_mem_req_addr_out_w_dst + assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual); + end else begin : g_mem_req_addr_out_w + assign mem_req_addr_out_w = mem_req_addr_in_qual; + end + + VX_demux #( + .DATAW (SRC_DATA_WIDTH/8), + .N (P) + ) req_be_demux ( + .sel_in (req_idx), + .data_in (mem_req_byteen_in), + .data_out (mem_req_byteen_out_w) + ); + + VX_demux #( + .DATAW (SRC_DATA_WIDTH), + .N (P) + ) req_data_demux ( + .sel_in (req_idx), + .data_in (mem_req_data_in), + .data_out (mem_req_data_out_w) + ); + + assign mem_req_valid_out_w = mem_req_valid_in; + assign mem_req_rw_out_w = mem_req_rw_in; + assign mem_req_tag_out_w = DST_TAG_WIDTH'({mem_req_tag_in, req_idx}); + assign mem_req_ready_in = mem_req_ready_out_w; + + assign mem_rsp_valid_in_w = mem_rsp_valid_out; + assign mem_rsp_data_in_w = mem_rsp_data_out_w[rsp_idx]; + assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out[DST_TAG_WIDTH-1:D]); + assign mem_rsp_ready_out = mem_rsp_ready_in_w; + + end else if (DST_LDATAW < SRC_LDATAW) begin : g_wider_src_data + + reg [D-1:0] req_ctr, rsp_ctr; + + reg [P-1:0][DST_DATA_WIDTH-1:0] mem_rsp_data_out_r, mem_rsp_data_out_n; + + wire mem_req_out_fire = mem_req_valid_out && mem_req_ready_out; + wire mem_rsp_in_fire = mem_rsp_valid_out && mem_rsp_ready_out; + + wire [P-1:0][DST_DATA_WIDTH-1:0] mem_req_data_in_w = mem_req_data_in; + wire [P-1:0][DST_DATA_SIZE-1:0] mem_req_byteen_in_w = mem_req_byteen_in; + + always @(*) begin + mem_rsp_data_out_n = mem_rsp_data_out_r; + if (mem_rsp_in_fire) begin + mem_rsp_data_out_n[rsp_ctr] = mem_rsp_data_out; + end + end + + always @(posedge clk) begin + if (reset) begin + req_ctr <= '0; + rsp_ctr <= '0; + end else begin + if (mem_req_out_fire) begin + req_ctr <= req_ctr + 1; + end + if (mem_rsp_in_fire) begin + rsp_ctr <= rsp_ctr + 1; + end + end + mem_rsp_data_out_r <= mem_rsp_data_out_n; + end + + reg [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_r; + wire [DST_TAG_WIDTH-1:0] mem_rsp_tag_in_x; + + always @(posedge clk) begin + if (mem_rsp_in_fire) begin + mem_rsp_tag_in_r <= mem_rsp_tag_out; + end + end + assign mem_rsp_tag_in_x = (rsp_ctr != 0) ? mem_rsp_tag_in_r : mem_rsp_tag_out; + `RUNTIME_ASSERT(!mem_rsp_in_fire || (mem_rsp_tag_in_x == mem_rsp_tag_out), + ("%t: *** out-of-order memory reponse! cur=0x%0h, expected=0x%0h", $time, mem_rsp_tag_in_x, mem_rsp_tag_out)) + + wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr}; + + if (DST_ADDR_WIDTH < (SRC_ADDR_WIDTH + D)) begin : g_mem_req_addr_out_w_src + `UNUSED_VAR (mem_req_addr_in_qual) + assign mem_req_addr_out_w = mem_req_addr_in_qual[DST_ADDR_WIDTH-1:0]; + end else if (DST_ADDR_WIDTH > (SRC_ADDR_WIDTH + D)) begin : g_mem_req_addr_out_w_dst + assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in_qual); + end else begin : g_mem_req_addr_out_w + assign mem_req_addr_out_w = mem_req_addr_in_qual; + end + + assign mem_req_valid_out_w = mem_req_valid_in; + assign mem_req_rw_out_w = mem_req_rw_in; + assign mem_req_byteen_out_w = mem_req_byteen_in_w[req_ctr]; + assign mem_req_data_out_w = mem_req_data_in_w[req_ctr]; + assign mem_req_tag_out_w = DST_TAG_WIDTH'(mem_req_tag_in); + assign mem_req_ready_in = mem_req_ready_out_w && (req_ctr == (P-1)); + + assign mem_rsp_valid_in_w = mem_rsp_valid_out && (rsp_ctr == (P-1)); + assign mem_rsp_data_in_w = mem_rsp_data_out_n; + assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out); + assign mem_rsp_ready_out = mem_rsp_ready_in_w; + + end else begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + if (DST_ADDR_WIDTH < SRC_ADDR_WIDTH) begin : g_mem_req_addr_out_w_src + `UNUSED_VAR (mem_req_addr_in) + assign mem_req_addr_out_w = mem_req_addr_in[DST_ADDR_WIDTH-1:0]; + end else if (DST_ADDR_WIDTH > SRC_ADDR_WIDTH) begin : g_mem_req_addr_out_w_dst + assign mem_req_addr_out_w = DST_ADDR_WIDTH'(mem_req_addr_in); + end else begin : g_mem_req_addr_out_w + assign mem_req_addr_out_w = mem_req_addr_in; + end + + assign mem_req_valid_out_w = mem_req_valid_in; + assign mem_req_rw_out_w = mem_req_rw_in; + assign mem_req_byteen_out_w = mem_req_byteen_in; + assign mem_req_data_out_w = mem_req_data_in; + assign mem_req_tag_out_w = DST_TAG_WIDTH'(mem_req_tag_in); + assign mem_req_ready_in = mem_req_ready_out_w; + + assign mem_rsp_valid_in_w = mem_rsp_valid_out; + assign mem_rsp_data_in_w = mem_rsp_data_out; + assign mem_rsp_tag_in_w = SRC_TAG_WIDTH'(mem_rsp_tag_out); + assign mem_rsp_ready_out = mem_rsp_ready_in_w; + + end + + VX_elastic_buffer #( + .DATAW (1 + DST_DATA_SIZE + DST_ADDR_WIDTH + DST_DATA_WIDTH + DST_TAG_WIDTH), + .SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF)) + ) req_out_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid_out_w), + .ready_in (mem_req_ready_out_w), + .data_in ({mem_req_rw_out_w, mem_req_byteen_out_w, mem_req_addr_out_w, mem_req_data_out_w, mem_req_tag_out_w}), + .data_out ({mem_req_rw_out, mem_req_byteen_out, mem_req_addr_out, mem_req_data_out, mem_req_tag_out}), + .valid_out (mem_req_valid_out), + .ready_out (mem_req_ready_out) + ); + + VX_elastic_buffer #( + .DATAW (SRC_DATA_WIDTH + SRC_TAG_WIDTH), + .SIZE (`TO_OUT_BUF_SIZE(RSP_OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(RSP_OUT_BUF)) + ) rsp_in_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_rsp_valid_in_w), + .ready_in (mem_rsp_ready_in_w), + .data_in ({mem_rsp_data_in_w, mem_rsp_tag_in_w}), + .data_out ({mem_rsp_data_in, mem_rsp_tag_in}), + .valid_out (mem_rsp_valid_in), + .ready_out (mem_rsp_ready_in) + ); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_mem_scheduler.sv b/designs/src/vortex/rtl/libs/VX_mem_scheduler.sv new file mode 100644 index 0000000..a0fc915 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_mem_scheduler.sv @@ -0,0 +1,652 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mem_scheduler #( + parameter `STRING INSTANCE_ID = "", + parameter CORE_REQS = 1, + parameter MEM_CHANNELS = 1, + parameter WORD_SIZE = 4, + parameter LINE_SIZE = WORD_SIZE, + parameter ADDR_WIDTH = 32 - `CLOG2(WORD_SIZE), + parameter FLAGS_WIDTH = 0, + parameter TAG_WIDTH = 8, + parameter UUID_WIDTH = 0, // upper section of the request tag contains the UUID + parameter CORE_QUEUE_SIZE= 8, + parameter MEM_QUEUE_SIZE= CORE_QUEUE_SIZE, + parameter RSP_PARTIAL = 0, + parameter CORE_OUT_BUF = 0, + parameter MEM_OUT_BUF = 0, + + parameter WORD_WIDTH = WORD_SIZE * 8, + parameter LINE_WIDTH = LINE_SIZE * 8, + parameter COALESCE_ENABLE = (CORE_REQS > 1) && (LINE_SIZE != WORD_SIZE), + parameter PER_LINE_REQS = LINE_SIZE / WORD_SIZE, + parameter MERGED_REQS = CORE_REQS / PER_LINE_REQS, + parameter MEM_BATCHES = `CDIV(MERGED_REQS, MEM_CHANNELS), + parameter MEM_BATCH_BITS= `CLOG2(MEM_BATCHES), + parameter MEM_QUEUE_ADDRW= `CLOG2(COALESCE_ENABLE ? MEM_QUEUE_SIZE : CORE_QUEUE_SIZE), + parameter MEM_ADDR_WIDTH= ADDR_WIDTH - `CLOG2(PER_LINE_REQS), + parameter MEM_TAG_WIDTH = UUID_WIDTH + MEM_QUEUE_ADDRW + MEM_BATCH_BITS, + parameter CORE_QUEUE_ADDRW = `CLOG2(CORE_QUEUE_SIZE) +) ( + input wire clk, + input wire reset, + + // Core request + input wire core_req_valid, + input wire core_req_rw, + input wire [CORE_REQS-1:0] core_req_mask, + input wire [CORE_REQS-1:0][WORD_SIZE-1:0] core_req_byteen, + input wire [CORE_REQS-1:0][ADDR_WIDTH-1:0] core_req_addr, + input wire [CORE_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] core_req_flags, + input wire [CORE_REQS-1:0][WORD_WIDTH-1:0] core_req_data, + input wire [TAG_WIDTH-1:0] core_req_tag, + output wire core_req_ready, + + // Core request queue + output wire req_queue_empty, + output wire req_queue_rw_notify, + + // Core response + output wire core_rsp_valid, + output wire [CORE_REQS-1:0] core_rsp_mask, + output wire [CORE_REQS-1:0][WORD_WIDTH-1:0] core_rsp_data, + output wire [TAG_WIDTH-1:0] core_rsp_tag, + output wire core_rsp_sop, + output wire core_rsp_eop, + input wire core_rsp_ready, + + // Memory request + output wire mem_req_valid, + output wire mem_req_rw, + output wire [MEM_CHANNELS-1:0] mem_req_mask, + output wire [MEM_CHANNELS-1:0][LINE_SIZE-1:0] mem_req_byteen, + output wire [MEM_CHANNELS-1:0][MEM_ADDR_WIDTH-1:0] mem_req_addr, + output wire [MEM_CHANNELS-1:0][`UP(FLAGS_WIDTH)-1:0] mem_req_flags, + output wire [MEM_CHANNELS-1:0][LINE_WIDTH-1:0] mem_req_data, + output wire [MEM_TAG_WIDTH-1:0] mem_req_tag, + input wire mem_req_ready, + + // Memory response + input wire mem_rsp_valid, + input wire [MEM_CHANNELS-1:0] mem_rsp_mask, + input wire [MEM_CHANNELS-1:0][LINE_WIDTH-1:0] mem_rsp_data, + input wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag, + output wire mem_rsp_ready +); + localparam BATCH_SEL_WIDTH = `UP(MEM_BATCH_BITS); + localparam STALL_TIMEOUT = 10000000; + localparam TAG_ID_WIDTH = TAG_WIDTH - UUID_WIDTH; + localparam REQQ_TAG_WIDTH = UUID_WIDTH + CORE_QUEUE_ADDRW; + localparam MERGED_TAG_WIDTH= UUID_WIDTH + MEM_QUEUE_ADDRW; + localparam CORE_CHANNELS = COALESCE_ENABLE ? CORE_REQS : MEM_CHANNELS; + localparam CORE_BATCHES = COALESCE_ENABLE ? 1 : MEM_BATCHES; + localparam CORE_BATCH_BITS = `CLOG2(CORE_BATCHES); + + `STATIC_ASSERT ((MEM_CHANNELS <= CORE_REQS), ("invalid parameter")) + `STATIC_ASSERT (`IS_DIVISBLE(CORE_REQS * WORD_SIZE, LINE_SIZE), ("invalid parameter")) + `STATIC_ASSERT ((TAG_WIDTH >= UUID_WIDTH), ("invalid parameter")) + `RUNTIME_ASSERT((~core_req_valid || core_req_mask != 0), ("%t: invalid request mask", $time)) + + wire ibuf_push; + wire ibuf_pop; + wire [CORE_QUEUE_ADDRW-1:0] ibuf_waddr; + wire [CORE_QUEUE_ADDRW-1:0] ibuf_raddr; + wire ibuf_full; + wire ibuf_empty; + wire [TAG_ID_WIDTH-1:0] ibuf_din; + wire [TAG_ID_WIDTH-1:0] ibuf_dout; + + wire reqq_valid; + wire [CORE_REQS-1:0] reqq_mask; + wire reqq_rw; + wire [CORE_REQS-1:0][WORD_SIZE-1:0] reqq_byteen; + wire [CORE_REQS-1:0][ADDR_WIDTH-1:0] reqq_addr; + wire [CORE_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] reqq_flags; + wire [CORE_REQS-1:0][WORD_WIDTH-1:0] reqq_data; + wire [REQQ_TAG_WIDTH-1:0] reqq_tag; + wire reqq_ready; + + wire reqq_valid_s; + wire [MERGED_REQS-1:0] reqq_mask_s; + wire reqq_rw_s; + wire [MERGED_REQS-1:0][LINE_SIZE-1:0] reqq_byteen_s; + wire [MERGED_REQS-1:0][MEM_ADDR_WIDTH-1:0] reqq_addr_s; + wire [MERGED_REQS-1:0][`UP(FLAGS_WIDTH)-1:0] reqq_flags_s; + wire [MERGED_REQS-1:0][LINE_WIDTH-1:0] reqq_data_s; + wire [MERGED_TAG_WIDTH-1:0] reqq_tag_s; + wire reqq_ready_s; + + wire mem_req_valid_s; + wire [MEM_CHANNELS-1:0] mem_req_mask_s; + wire mem_req_rw_s; + wire [MEM_CHANNELS-1:0][LINE_SIZE-1:0] mem_req_byteen_s; + wire [MEM_CHANNELS-1:0][MEM_ADDR_WIDTH-1:0] mem_req_addr_s; + wire [MEM_CHANNELS-1:0][`UP(FLAGS_WIDTH)-1:0] mem_req_flags_s; + wire [MEM_CHANNELS-1:0][LINE_WIDTH-1:0] mem_req_data_s; + wire [MEM_TAG_WIDTH-1:0] mem_req_tag_s; + wire mem_req_ready_s; + + wire mem_rsp_valid_s; + wire [CORE_CHANNELS-1:0] mem_rsp_mask_s; + wire [CORE_CHANNELS-1:0][WORD_WIDTH-1:0] mem_rsp_data_s; + wire [MEM_TAG_WIDTH-1:0] mem_rsp_tag_s; + wire mem_rsp_ready_s; + + wire crsp_valid; + wire [CORE_REQS-1:0] crsp_mask; + wire [CORE_REQS-1:0][WORD_WIDTH-1:0] crsp_data; + wire [TAG_WIDTH-1:0] crsp_tag; + wire crsp_sop; + wire crsp_eop; + wire crsp_ready; + + // Request queue ////////////////////////////////////////////////////////// + + wire req_sent_all; + + wire ibuf_ready = (core_req_rw || ~ibuf_full); + wire reqq_valid_in = core_req_valid && ibuf_ready; + wire reqq_ready_in; + + wire [REQQ_TAG_WIDTH-1:0] reqq_tag_u; + if (UUID_WIDTH != 0) begin : g_reqq_tag_u_uuid + assign reqq_tag_u = {core_req_tag[TAG_WIDTH-1 -: UUID_WIDTH], ibuf_waddr}; + end else begin : g_reqq_tag_u + assign reqq_tag_u = ibuf_waddr; + end + + VX_elastic_buffer #( + .DATAW (1 + CORE_REQS * (1 + WORD_SIZE + ADDR_WIDTH + `UP(FLAGS_WIDTH) + WORD_WIDTH) + REQQ_TAG_WIDTH), + .SIZE (CORE_QUEUE_SIZE), + .OUT_REG (1) + ) req_queue ( + .clk (clk), + .reset (reset), + .valid_in (reqq_valid_in), + .ready_in (reqq_ready_in), + .data_in ({core_req_rw, core_req_mask, core_req_byteen, core_req_addr, core_req_flags, core_req_data, reqq_tag_u}), + .data_out ({reqq_rw, reqq_mask, reqq_byteen, reqq_addr, reqq_flags, reqq_data, reqq_tag}), + .valid_out(reqq_valid), + .ready_out(reqq_ready) + ); + + // can accept another request? + assign core_req_ready = reqq_ready_in && ibuf_ready; + + // request queue status + assign req_queue_rw_notify = reqq_valid && reqq_ready && reqq_rw; + assign req_queue_empty = !reqq_valid && ibuf_empty; + + // Index buffer /////////////////////////////////////////////////////////// + + wire core_req_fire = core_req_valid && core_req_ready; + wire crsp_fire = crsp_valid && crsp_ready; + + assign ibuf_push = core_req_fire && ~core_req_rw; + assign ibuf_pop = crsp_fire && crsp_eop; + assign ibuf_raddr = mem_rsp_tag_s[CORE_BATCH_BITS +: CORE_QUEUE_ADDRW]; + assign ibuf_din = core_req_tag[TAG_ID_WIDTH-1:0]; + + VX_index_buffer #( + .DATAW (TAG_ID_WIDTH), + .SIZE (CORE_QUEUE_SIZE) + ) req_ibuf ( + .clk (clk), + .reset (reset), + .acquire_en (ibuf_push), + .write_addr (ibuf_waddr), + .write_data (ibuf_din), + .read_data (ibuf_dout), + .read_addr (ibuf_raddr), + .release_en (ibuf_pop), + .full (ibuf_full), + .empty (ibuf_empty) + ); + + `UNUSED_VAR (ibuf_empty) + + // Handle memory coalescing /////////////////////////////////////////////// + + if (COALESCE_ENABLE) begin : g_coalescer + + VX_mem_coalescer #( + .INSTANCE_ID (`SFORMATF(("%s-coalescer", INSTANCE_ID))), + .NUM_REQS (CORE_REQS), + .DATA_IN_SIZE (WORD_SIZE), + .DATA_OUT_SIZE (LINE_SIZE), + .ADDR_WIDTH (ADDR_WIDTH), + .FLAGS_WIDTH (FLAGS_WIDTH), + .TAG_WIDTH (REQQ_TAG_WIDTH), + .UUID_WIDTH (UUID_WIDTH), + .QUEUE_SIZE (MEM_QUEUE_SIZE) + ) coalescer ( + .clk (clk), + .reset (reset), + + `UNUSED_PIN (misses), + + // Input request + .in_req_valid (reqq_valid), + .in_req_mask (reqq_mask), + .in_req_rw (reqq_rw), + .in_req_byteen (reqq_byteen), + .in_req_addr (reqq_addr), + .in_req_flags (reqq_flags), + .in_req_data (reqq_data), + .in_req_tag (reqq_tag), + .in_req_ready (reqq_ready), + + // Input response + .in_rsp_valid (mem_rsp_valid_s), + .in_rsp_mask (mem_rsp_mask_s), + .in_rsp_data (mem_rsp_data_s), + .in_rsp_tag (mem_rsp_tag_s), + .in_rsp_ready (mem_rsp_ready_s), + + // Output request + .out_req_valid (reqq_valid_s), + .out_req_mask (reqq_mask_s), + .out_req_rw (reqq_rw_s), + .out_req_byteen (reqq_byteen_s), + .out_req_addr (reqq_addr_s), + .out_req_flags (reqq_flags_s), + .out_req_data (reqq_data_s), + .out_req_tag (reqq_tag_s), + .out_req_ready (reqq_ready_s), + + // Output response + .out_rsp_valid (mem_rsp_valid), + .out_rsp_mask (mem_rsp_mask), + .out_rsp_data (mem_rsp_data), + .out_rsp_tag (mem_rsp_tag), + .out_rsp_ready (mem_rsp_ready) + ); + + end else begin : g_no_coalescer + assign reqq_valid_s = reqq_valid; + assign reqq_mask_s = reqq_mask; + assign reqq_rw_s = reqq_rw; + assign reqq_byteen_s= reqq_byteen; + assign reqq_addr_s = reqq_addr; + assign reqq_flags_s = reqq_flags; + assign reqq_data_s = reqq_data; + assign reqq_tag_s = reqq_tag; + assign reqq_ready = reqq_ready_s; + + assign mem_rsp_valid_s = mem_rsp_valid; + assign mem_rsp_mask_s = mem_rsp_mask; + assign mem_rsp_data_s = mem_rsp_data; + assign mem_rsp_tag_s = mem_rsp_tag; + assign mem_rsp_ready = mem_rsp_ready_s; + + end + + // Handle memory requests ///////////////////////////////////////////////// + + wire [MEM_BATCHES-1:0][MEM_CHANNELS-1:0] mem_req_mask_b; + wire [MEM_BATCHES-1:0][MEM_CHANNELS-1:0][LINE_SIZE-1:0] mem_req_byteen_b; + wire [MEM_BATCHES-1:0][MEM_CHANNELS-1:0][MEM_ADDR_WIDTH-1:0] mem_req_addr_b; + wire [MEM_BATCHES-1:0][MEM_CHANNELS-1:0][`UP(FLAGS_WIDTH)-1:0] mem_req_flags_b; + wire [MEM_BATCHES-1:0][MEM_CHANNELS-1:0][LINE_WIDTH-1:0] mem_req_data_b; + + wire [BATCH_SEL_WIDTH-1:0] req_batch_idx; + + for (genvar i = 0; i < MEM_BATCHES; ++i) begin : g_mem_req_data_b + for (genvar j = 0; j < MEM_CHANNELS; ++j) begin : g_j + localparam r = i * MEM_CHANNELS + j; + if (r < MERGED_REQS) begin : g_valid + assign mem_req_mask_b[i][j] = reqq_mask_s[r]; + assign mem_req_byteen_b[i][j] = reqq_byteen_s[r]; + assign mem_req_addr_b[i][j] = reqq_addr_s[r]; + assign mem_req_flags_b[i][j] = reqq_flags_s[r]; + assign mem_req_data_b[i][j] = reqq_data_s[r]; + end else begin : g_padding + assign mem_req_mask_b[i][j] = 0; + assign mem_req_byteen_b[i][j] = '0; + assign mem_req_addr_b[i][j] = '0; + assign mem_req_flags_b[i][j] = '0; + assign mem_req_data_b[i][j] = '0; + end + end + end + + assign mem_req_mask_s = mem_req_mask_b[req_batch_idx]; + assign mem_req_rw_s = reqq_rw_s; + assign mem_req_byteen_s = mem_req_byteen_b[req_batch_idx]; + assign mem_req_addr_s = mem_req_addr_b[req_batch_idx]; + assign mem_req_flags_s = mem_req_flags_b[req_batch_idx]; + assign mem_req_data_s = mem_req_data_b[req_batch_idx]; + + if (MEM_BATCHES != 1) begin : g_batch + reg [MEM_BATCH_BITS-1:0] req_batch_idx_r; + + wire is_degenerate_batch = ~(| mem_req_mask_s); + wire mem_req_valid_b = reqq_valid_s && ~is_degenerate_batch; + wire mem_req_ready_b = mem_req_ready_s || is_degenerate_batch; + + always @(posedge clk) begin + if (reset) begin + req_batch_idx_r <= '0; + end else begin + if (reqq_valid_s && mem_req_ready_b) begin + if (req_sent_all) begin + req_batch_idx_r <= '0; + end else begin + req_batch_idx_r <= req_batch_idx_r + MEM_BATCH_BITS'(1); + end + end + end + end + + wire [MEM_BATCHES-1:0] req_batch_valids; + wire [MEM_BATCHES-1:0][MEM_BATCH_BITS-1:0] req_batch_idxs; + wire [MEM_BATCH_BITS-1:0] req_batch_idx_last; + + for (genvar i = 0; i < MEM_BATCHES; ++i) begin : g_req_batch + assign req_batch_valids[i] = (| mem_req_mask_b[i]); + assign req_batch_idxs[i] = MEM_BATCH_BITS'(i); + end + + VX_find_first #( + .N (MEM_BATCHES), + .DATAW (MEM_BATCH_BITS), + .REVERSE (1) + ) find_last ( + .valid_in (req_batch_valids), + .data_in (req_batch_idxs), + .data_out (req_batch_idx_last), + `UNUSED_PIN (valid_out) + ); + + assign mem_req_valid_s = mem_req_valid_b; + assign req_batch_idx = req_batch_idx_r; + assign req_sent_all = mem_req_ready_b && (req_batch_idx_r == req_batch_idx_last); + assign mem_req_tag_s = {reqq_tag_s, req_batch_idx}; + + end else begin : g_no_batch + + assign mem_req_valid_s = reqq_valid_s; + assign req_batch_idx = '0; + assign req_sent_all = mem_req_ready_s; + assign mem_req_tag_s = reqq_tag_s; + + end + + assign reqq_ready_s = req_sent_all; + + wire [MEM_CHANNELS-1:0][`UP(FLAGS_WIDTH)-1:0] mem_req_flags_u; + + VX_elastic_buffer #( + .DATAW (MEM_CHANNELS + 1 + MEM_CHANNELS * (LINE_SIZE + MEM_ADDR_WIDTH + `UP(FLAGS_WIDTH) + LINE_WIDTH) + MEM_TAG_WIDTH), + .SIZE (`TO_OUT_BUF_SIZE(MEM_OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF)) + ) mem_req_buf ( + .clk (clk), + .reset (reset), + .valid_in (mem_req_valid_s), + .ready_in (mem_req_ready_s), + .data_in ({mem_req_mask_s, mem_req_rw_s, mem_req_byteen_s, mem_req_addr_s, mem_req_flags_s, mem_req_data_s, mem_req_tag_s}), + .data_out ({mem_req_mask, mem_req_rw, mem_req_byteen, mem_req_addr, mem_req_flags_u, mem_req_data, mem_req_tag}), + .valid_out (mem_req_valid), + .ready_out (mem_req_ready) + ); + + if (FLAGS_WIDTH != 0) begin : g_mem_req_flags + assign mem_req_flags = mem_req_flags_u; + end else begin : g_mem_req_flags_0 + `UNUSED_VAR (mem_req_flags_u) + assign mem_req_flags = '0; + end + + // Handle memory responses //////////////////////////////////////////////// + + wire [BATCH_SEL_WIDTH-1:0] rsp_batch_idx; + if (CORE_BATCHES > 1) begin : g_rsp_batch_idx + assign rsp_batch_idx = mem_rsp_tag_s[CORE_BATCH_BITS-1:0]; + end else begin : g_rsp_batch_idx_0 + assign rsp_batch_idx = '0; + end + + if (CORE_REQS == 1) begin : g_rsp_1 + `UNUSED_VAR (rsp_batch_idx) + + assign crsp_valid = mem_rsp_valid_s; + assign crsp_mask = mem_rsp_mask_s; + assign crsp_sop = 1'b1; + assign crsp_eop = 1'b1; + assign crsp_data = mem_rsp_data_s; + + assign mem_rsp_ready_s = crsp_ready; + + end else begin : g_rsp_N + + reg [CORE_QUEUE_SIZE-1:0][CORE_REQS-1:0] rsp_rem_mask; + wire [CORE_REQS-1:0] rsp_rem_mask_n, curr_mask; + + for (genvar r = 0; r < CORE_REQS; ++r) begin : g_curr_mask + localparam i = r / CORE_CHANNELS; + localparam j = r % CORE_CHANNELS; + assign curr_mask[r] = (BATCH_SEL_WIDTH'(i) == rsp_batch_idx) && mem_rsp_mask_s[j]; + end + + assign rsp_rem_mask_n = rsp_rem_mask[ibuf_raddr] & ~curr_mask; + + wire mem_rsp_fire_s = mem_rsp_valid_s && mem_rsp_ready_s; + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_rem_mask[ibuf_waddr] <= core_req_mask; + end + if (mem_rsp_fire_s) begin + rsp_rem_mask[ibuf_raddr] <= rsp_rem_mask_n; + end + end + + wire rsp_complete = ~(| rsp_rem_mask_n) || (CORE_REQS == 1); + + if (RSP_PARTIAL != 0) begin : g_rsp_partial + + reg [CORE_QUEUE_SIZE-1:0] rsp_sop_r; + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_sop_r[ibuf_waddr] <= 1; + end + if (mem_rsp_fire_s) begin + rsp_sop_r[ibuf_raddr] <= 0; + end + end + + assign crsp_valid = mem_rsp_valid_s; + assign crsp_mask = curr_mask; + assign crsp_sop = rsp_sop_r[ibuf_raddr]; + + for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data + localparam j = r % CORE_CHANNELS; + assign crsp_data[r] = mem_rsp_data_s[j]; + end + + assign mem_rsp_ready_s = crsp_ready; + + end else begin : g_rsp_full + + wire [CORE_CHANNELS-1:0][CORE_BATCHES-1:0][WORD_WIDTH-1:0] rsp_store_n; + reg [CORE_REQS-1:0] rsp_orig_mask [CORE_QUEUE_SIZE-1:0]; + + for (genvar i = 0; i < CORE_CHANNELS; ++i) begin : g_rsp_store + for (genvar j = 0; j < CORE_BATCHES; ++j) begin : g_j + reg [WORD_WIDTH-1:0] rsp_store [0:CORE_QUEUE_SIZE-1]; + wire rsp_wren = mem_rsp_fire_s + && (BATCH_SEL_WIDTH'(j) == rsp_batch_idx) + && ((CORE_CHANNELS == 1) || mem_rsp_mask_s[i]); + always @(posedge clk) begin + if (rsp_wren) begin + rsp_store[ibuf_raddr] <= mem_rsp_data_s[i]; + end + end + assign rsp_store_n[i][j] = rsp_wren ? mem_rsp_data_s[i] : rsp_store[ibuf_raddr]; + end + end + + always @(posedge clk) begin + if (ibuf_push) begin + rsp_orig_mask[ibuf_waddr] <= core_req_mask; + end + end + + assign crsp_valid = mem_rsp_valid_s && rsp_complete; + assign crsp_mask = rsp_orig_mask[ibuf_raddr]; + assign crsp_sop = 1'b1; + + for (genvar r = 0; r < CORE_REQS; ++r) begin : g_crsp_data + localparam i = r / CORE_CHANNELS; + localparam j = r % CORE_CHANNELS; + assign crsp_data[r] = rsp_store_n[j][i]; + end + + assign mem_rsp_ready_s = crsp_ready || ~rsp_complete; + end + + assign crsp_eop = rsp_complete; + end + + if (UUID_WIDTH != 0) begin : g_crsp_tag + assign crsp_tag = {mem_rsp_tag_s[MEM_TAG_WIDTH-1 -: UUID_WIDTH], ibuf_dout}; + end else begin : g_crsp_tag_0 + assign crsp_tag = ibuf_dout; + end + + // Send response to caller + + VX_elastic_buffer #( + .DATAW (CORE_REQS + 1 + 1 + (CORE_REQS * WORD_WIDTH) + TAG_WIDTH), + .SIZE (`TO_OUT_BUF_SIZE(CORE_OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF)) + ) rsp_buf ( + .clk (clk), + .reset (reset), + .valid_in (crsp_valid), + .ready_in (crsp_ready), + .data_in ({crsp_mask, crsp_sop, crsp_eop, crsp_data, crsp_tag}), + .data_out ({core_rsp_mask, core_rsp_sop, core_rsp_eop, core_rsp_data, core_rsp_tag}), + .valid_out (core_rsp_valid), + .ready_out (core_rsp_ready) + ); + +`ifdef SIMULATION + wire [`UP(UUID_WIDTH)-1:0] req_dbg_uuid; + + if (UUID_WIDTH != 0) begin : g_req_dbg_uuid + assign req_dbg_uuid = core_req_tag[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_req_dbg_uuid_0 + assign req_dbg_uuid = '0; + end + + reg [(`UP(UUID_WIDTH) + TAG_ID_WIDTH + 64)-1:0] pending_reqs_time [CORE_QUEUE_SIZE-1:0]; + reg [CORE_QUEUE_SIZE-1:0] pending_reqs_valid; + + always @(posedge clk) begin + if (reset) begin + pending_reqs_valid <= '0; + end else begin + if (ibuf_push) begin + pending_reqs_valid[ibuf_waddr] <= 1'b1; + end + if (ibuf_pop) begin + pending_reqs_valid[ibuf_raddr] <= 1'b0; + end + end + + if (ibuf_push) begin + pending_reqs_time[ibuf_waddr] <= {req_dbg_uuid, ibuf_din, $time}; + end + + for (integer i = 0; i < CORE_QUEUE_SIZE; ++i) begin + if (pending_reqs_valid[i]) begin + `ASSERT(($time - pending_reqs_time[i][63:0]) < STALL_TIMEOUT, + ("%t: *** %s response timeout: tag=0x%0h (#%0d)", + $time, INSTANCE_ID, pending_reqs_time[i][64 +: TAG_ID_WIDTH], pending_reqs_time[i][64+TAG_ID_WIDTH +: `UP(UUID_WIDTH)])); + end + end + end +`endif + + /////////////////////////////////////////////////////////////////////////// + +`ifdef DBG_TRACE_MEM + wire [`UP(UUID_WIDTH)-1:0] mem_req_dbg_uuid; + wire [`UP(UUID_WIDTH)-1:0] mem_rsp_dbg_uuid; + wire [`UP(UUID_WIDTH)-1:0] rsp_dbg_uuid; + + if (UUID_WIDTH != 0) begin : g_dbg_uuid + assign mem_req_dbg_uuid = mem_req_tag_s[MEM_TAG_WIDTH-1 -: UUID_WIDTH]; + assign mem_rsp_dbg_uuid = mem_rsp_tag_s[MEM_TAG_WIDTH-1 -: UUID_WIDTH]; + assign rsp_dbg_uuid = core_rsp_tag[TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_dbg_uuid_0 + assign mem_req_dbg_uuid = '0; + assign mem_rsp_dbg_uuid = '0; + assign rsp_dbg_uuid = '0; + end + + wire [CORE_QUEUE_ADDRW-1:0] ibuf_waddr_s = mem_req_tag_s[MEM_BATCH_BITS +: CORE_QUEUE_ADDRW]; + + wire mem_req_fire_s = mem_req_valid_s && mem_req_ready_s; + + always @(posedge clk) begin + if (core_req_fire) begin + if (core_req_rw) begin + `TRACE(2, ("%t: %s core-req-wr: valid=%b, addr=", $time, INSTANCE_ID, core_req_mask)) + `TRACE_ARRAY1D(2, "0x%h", core_req_addr, CORE_REQS) + `TRACE(2, (", byteen=")) + `TRACE_ARRAY1D(2, "0x%h", core_req_byteen, CORE_REQS) + `TRACE(2, (", data=")) + `TRACE_ARRAY1D(2, "0x%0h", core_req_data, CORE_REQS) + end else begin + `TRACE(2, ("%t: %s core-req-rd: valid=%b, addr=", $time, INSTANCE_ID, core_req_mask)) + `TRACE_ARRAY1D(2, "0x%h", core_req_addr, CORE_REQS) + end + `TRACE(2, (", tag=0x%0h (#%0d)\n", core_req_tag, req_dbg_uuid)) + end + if (core_rsp_valid && core_rsp_ready) begin + `TRACE(2, ("%t: %s core-rsp: valid=%b, sop=%b, eop=%b, data=", $time, INSTANCE_ID, core_rsp_mask, core_rsp_sop, core_rsp_eop)) + `TRACE_ARRAY1D(2, "0x%0h", core_rsp_data, CORE_REQS) + `TRACE(2, (", tag=0x%0h (#%0d)\n", core_rsp_tag, rsp_dbg_uuid)) + end + if (| mem_req_fire_s) begin + if (| mem_req_rw_s) begin + `TRACE(2, ("%t: %s mem-req-wr: valid=%b, addr=", $time, INSTANCE_ID, mem_req_mask_s)) + `TRACE_ARRAY1D(2, "0x%h", mem_req_addr_s, CORE_CHANNELS) + `TRACE(2, (", byteen=")) + `TRACE_ARRAY1D(2, "0x%h", mem_req_byteen_s, CORE_CHANNELS) + `TRACE(2, (", data=")) + `TRACE_ARRAY1D(2, "0x%0h", mem_req_data_s, CORE_CHANNELS) + end else begin + `TRACE(2, ("%t: %s mem-req-rd: valid=%b, addr=", $time, INSTANCE_ID, mem_req_mask_s)) + `TRACE_ARRAY1D(2, "0x%h", mem_req_addr_s, CORE_CHANNELS) + end + `TRACE(2, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_waddr_s, req_batch_idx, mem_req_dbg_uuid)) + end + if (mem_rsp_valid_s && mem_rsp_ready_s) begin + `TRACE(2, ("%t: %s mem-rsp: valid=%b, data=", $time, INSTANCE_ID, mem_rsp_mask_s)) + `TRACE_ARRAY1D(2, "0x%0h", mem_rsp_data_s, CORE_CHANNELS) + `TRACE(2, (", ibuf_idx=%0d, batch_idx=%0d (#%0d)\n", ibuf_raddr, rsp_batch_idx, mem_rsp_dbg_uuid)) + end + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_multiplier.sv b/designs/src/vortex/rtl/libs/VX_multiplier.sv new file mode 100644 index 0000000..6b525ce --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_multiplier.sv @@ -0,0 +1,50 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_multiplier #( + parameter A_WIDTH = 1, + parameter B_WIDTH = A_WIDTH, + parameter R_WIDTH = A_WIDTH + B_WIDTH, + parameter SIGNED = 0, + parameter LATENCY = 0 +) ( + input wire clk, + input wire enable, + input wire [A_WIDTH-1:0] dataa, + input wire [B_WIDTH-1:0] datab, + output wire [R_WIDTH-1:0] result +); + wire [R_WIDTH-1:0] prod_w; + + if (SIGNED != 0) begin : g_prod_s + assign prod_w = R_WIDTH'($signed(dataa) * $signed(datab)); + end else begin : g_prod_u + assign prod_w = R_WIDTH'(dataa * datab); + end + + VX_pipe_register #( + .DATAW (R_WIDTH), + .DEPTH (LATENCY) + ) pipe_reg ( + .clk (clk), + .enable (enable), + .reset (1'b0), + .data_in (prod_w), + .data_out(result) + ); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_mux.sv b/designs/src/vortex/rtl/libs/VX_mux.sv new file mode 100644 index 0000000..19a0660 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_mux.sv @@ -0,0 +1,34 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_mux #( + parameter DATAW = 1, + parameter N = 1, + parameter LN = `LOG2UP(N) +) ( + input wire [N-1:0][DATAW-1:0] data_in, + input wire [LN-1:0] sel_in, + output wire [DATAW-1:0] data_out +); + if (N > 1) begin : g_mux + assign data_out = data_in[sel_in]; + end else begin : g_passthru + `UNUSED_VAR (sel_in) + assign data_out = data_in; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_nz_iterator.sv b/designs/src/vortex/rtl/libs/VX_nz_iterator.sv new file mode 100644 index 0000000..5a364b7 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_nz_iterator.sv @@ -0,0 +1,114 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_nz_iterator #( + parameter DATAW = 8, // Bit-width of each data element + parameter KEYW = DATAW, // Bit-width of the key + parameter N = 4, // Number of elements in the stream + parameter OUT_REG = 0, // Output register + parameter LPID_WIDTH = `LOG2UP(N) +) ( + input wire clk, + input wire reset, + input wire valid_in, // Stream input valid + input wire [N-1:0][DATAW-1:0] data_in, // Stream input data + input wire next, // Advance iterator + output wire valid_out, // Current output valid + output reg [DATAW-1:0] data_out, // Current output data + output reg [LPID_WIDTH-1:0] pid, // Index of the current element + output reg sop, // Start of valid stream + output reg eop // End of valid stream +); + if (N > 1) begin : g_iterator + + reg [N-1:0] sent_mask_p; + wire [LPID_WIDTH-1:0] start_p, end_p; + + wire [N-1:0] packet_valids; + for (genvar i = 0; i < N; ++i) begin : g_packet_valids + assign packet_valids[i] = (| data_in[i][KEYW-1:0]); + end + + wire [N-1:0][LPID_WIDTH-1:0] packet_ids; + for (genvar i = 0; i < N; ++i) begin : g_packet_ids + assign packet_ids[i] = LPID_WIDTH'(i); + end + + VX_find_first #( + .N (N), + .DATAW (LPID_WIDTH), + .REVERSE (0) + ) find_first ( + .valid_in (packet_valids & ~sent_mask_p), + .data_in (packet_ids), + .data_out (start_p), + `UNUSED_PIN (valid_out) + ); + + VX_find_first #( + .N (N), + .DATAW (LPID_WIDTH), + .REVERSE (1) + ) find_last ( + .valid_in (packet_valids), + .data_in (packet_ids), + .data_out (end_p), + `UNUSED_PIN (valid_out) + ); + + reg is_first_p; + wire is_last_p = (start_p == end_p); + + wire enable = valid_in && (~valid_out || next); + + always @(posedge clk) begin + if (reset || (enable && (is_last_p || eop))) begin + sent_mask_p <= '0; + is_first_p <= 1; + end else if (enable) begin + sent_mask_p[start_p] <= 1; + is_first_p <= 0; + end + end + + VX_pipe_register #( + .DATAW (1 + DATAW + LPID_WIDTH + 1 + 1), + .RESETW (1), + .DEPTH (OUT_REG) + ) pipe_reg ( + .clk (clk), + .reset (reset || (enable && eop)), + .enable (enable), + .data_in ({valid_in, data_in[start_p], start_p, is_first_p, is_last_p}), + .data_out ({valid_out, data_out, pid, sop, eop}) + ); + + end else begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (next) + + assign valid_out = valid_in; + assign data_out = data_in[0]; + assign pid = 0; + assign sop = 1; + assign eop = 1; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_onehot_encoder.sv b/designs/src/vortex/rtl/libs/VX_onehot_encoder.sv new file mode 100644 index 0000000..08198e4 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_onehot_encoder.sv @@ -0,0 +1,113 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +// Fast one-hot encoder using parallel prefix computation +// Adapted from BaseJump STL: http://bjump.org/data_out.html + +`TRACING_OFF +module VX_onehot_encoder #( + parameter N = 1, + parameter REVERSE = 0, + parameter MODEL = 1, + parameter LN = `LOG2UP(N) +) ( + input wire [N-1:0] data_in, + output wire [LN-1:0] data_out, + output wire valid_out +); + if (N == 1) begin : g_n1 + + assign data_out = 0; + assign valid_out = data_in; + + end else if (N == 2) begin : g_n2 + + assign data_out = data_in[!REVERSE]; + assign valid_out = (| data_in); + + end else if (MODEL == 1) begin : g_model1 + localparam M = 1 << LN; + `IGNORE_UNOPTFLAT_BEGIN + wire [M-1:0] addr [LN]; + wire [M-1:0] v [LN+1]; + `IGNORE_UNOPTFLAT_END + + // base case, also handle padding for non-power of two inputs + assign v[0] = REVERSE ? (M'(data_in) << (M - N)) : M'(data_in); + + for (genvar lvl = 1; lvl < (LN+1); ++lvl) begin : g_scan_l + localparam SN = 1 << (LN - lvl); + localparam SI = M / SN; + for (genvar s = 0; s < SN; ++s) begin : g_scan_s + `IGNORE_UNOPTFLAT_BEGIN + wire [1:0] vs = {v[lvl-1][s*SI+(SI>>1)], v[lvl-1][s*SI]}; + `IGNORE_UNOPTFLAT_END + assign v[lvl][s*SI] = (| vs); + if (lvl == 1) begin : g_lvl_1 + assign addr[lvl-1][s*SI +: lvl] = vs[!REVERSE]; + end else begin : g_lvl_n + assign addr[lvl-1][s*SI +: lvl] = { + vs[!REVERSE], + addr[lvl-2][s*SI +: lvl-1] | addr[lvl-2][s*SI+(SI>>1) +: lvl-1] + }; + end + end + end + + assign data_out = addr[LN-1][LN-1:0]; + assign valid_out = v[LN][0]; + + end else if (MODEL == 2 && REVERSE == 0) begin : g_model2 + + for (genvar j = 0; j < LN; ++j) begin : g_data_out + wire [N-1:0] mask; + for (genvar i = 0; i < N; ++i) begin : g_mask + assign mask[i] = i[j]; + end + assign data_out[j] = | (mask & data_in); + end + + assign valid_out = (| data_in); + + end else begin : g_model0 + + reg [LN-1:0] index_w; + + if (REVERSE != 0) begin : g_msb + always @(*) begin + index_w = 'x; + for (integer i = N-1; i >= 0; --i) begin + if (data_in[i]) begin + index_w = LN'(N-1-i); + end + end + end + end else begin : g_lsb + always @(*) begin + index_w = 'x; + for (integer i = 0; i < N; ++i) begin + if (data_in[i]) begin + index_w = LN'(i); + end + end + end + end + + assign data_out = index_w; + assign valid_out = (| data_in); + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_onehot_mux.sv b/designs/src/vortex/rtl/libs/VX_onehot_mux.sv new file mode 100644 index 0000000..8b97692 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_onehot_mux.sv @@ -0,0 +1,150 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_onehot_mux #( + parameter DATAW = 1, + parameter N = 1, + parameter MODEL = 1, + parameter LUT_OPT = 0 +) ( + input wire [N-1:0][DATAW-1:0] data_in, + input wire [N-1:0] sel_in, + output wire [DATAW-1:0] data_out +); + if (N == 1) begin : g_passthru + `UNUSED_VAR (sel_in) + assign data_out = data_in; + end else if (LUT_OPT && N == 2) begin : g_lut2 + `UNUSED_VAR (sel_in) + assign data_out = sel_in[0] ? data_in[0] : data_in[1]; + end else if (LUT_OPT && N == 3) begin : g_lut3 + reg [DATAW-1:0] data_out_w; + always @(*) begin + case (sel_in) + 3'b001: data_out_w = data_in[0]; + 3'b010: data_out_w = data_in[1]; + 3'b100: data_out_w = data_in[2]; + default: data_out_w = 'x; + endcase + end + assign data_out = data_out_w; + end else if (LUT_OPT && N == 4) begin : g_lut4 + reg [DATAW-1:0] data_out_w; + always @(*) begin + case (sel_in) + 4'b0001: data_out_w = data_in[0]; + 4'b0010: data_out_w = data_in[1]; + 4'b0100: data_out_w = data_in[2]; + 4'b1000: data_out_w = data_in[3]; + default: data_out_w = 'x; + endcase + end + assign data_out = data_out_w; + end else if (LUT_OPT && N == 5) begin : g_lut5 + reg [DATAW-1:0] data_out_w; + always @(*) begin + case (sel_in) + 5'b00001: data_out_w = data_in[0]; + 5'b00010: data_out_w = data_in[1]; + 5'b00100: data_out_w = data_in[2]; + 5'b01000: data_out_w = data_in[3]; + 5'b10000: data_out_w = data_in[4]; + default: data_out_w = 'x; + endcase + end + assign data_out = data_out_w; + end else if (LUT_OPT && N == 6) begin : g_lut6 + reg [DATAW-1:0] data_out_w; + always @(*) begin + case (sel_in) + 6'b000001: data_out_w = data_in[0]; + 6'b000010: data_out_w = data_in[1]; + 6'b000100: data_out_w = data_in[2]; + 6'b001000: data_out_w = data_in[3]; + 6'b010000: data_out_w = data_in[4]; + 6'b100000: data_out_w = data_in[5]; + default: data_out_w = 'x; + endcase + end + assign data_out = data_out_w; + end else if (LUT_OPT && N == 7) begin : g_lut7 + reg [DATAW-1:0] data_out_w; + always @(*) begin + case (sel_in) + 7'b0000001: data_out_w = data_in[0]; + 7'b0000010: data_out_w = data_in[1]; + 7'b0000100: data_out_w = data_in[2]; + 7'b0001000: data_out_w = data_in[3]; + 7'b0010000: data_out_w = data_in[4]; + 7'b0100000: data_out_w = data_in[5]; + 7'b1000000: data_out_w = data_in[6]; + default: data_out_w = 'x; + endcase + end + assign data_out = data_out_w; + end else if (LUT_OPT && N == 8) begin : g_lut8 + reg [DATAW-1:0] data_out_w; + always @(*) begin + case (sel_in) + 8'b00000001: data_out_w = data_in[0]; + 8'b00000010: data_out_w = data_in[1]; + 8'b00000100: data_out_w = data_in[2]; + 8'b00001000: data_out_w = data_in[3]; + 8'b00010000: data_out_w = data_in[4]; + 8'b00100000: data_out_w = data_in[5]; + 8'b01000000: data_out_w = data_in[6]; + 8'b10000000: data_out_w = data_in[7]; + default: data_out_w = 'x; + endcase + end + assign data_out = data_out_w; + end else if (MODEL == 1) begin : g_model1 + wire [N-1:0][DATAW-1:0] mask; + for (genvar i = 0; i < N; ++i) begin : g_mask + assign mask[i] = {DATAW{sel_in[i]}} & data_in[i]; + end + for (genvar i = 0; i < DATAW; ++i) begin : g_data_out + wire [N-1:0] gather; + for (genvar j = 0; j < N; ++j) begin : g_gather + assign gather[j] = mask[j][i]; + end + assign data_out[i] = (| gather); + end + end else if (MODEL == 2) begin : g_model2 + VX_find_first #( + .N (N), + .DATAW (DATAW) + ) find_first ( + .valid_in (sel_in), + .data_in (data_in), + .data_out (data_out), + `UNUSED_PIN (valid_out) + ); + end else if (MODEL == 3) begin : g_model3 + reg [DATAW-1:0] data_out_w; + always @(*) begin + data_out_w = 'x; + for (integer i = 0; i < N; ++i) begin + if (sel_in[i]) begin + data_out_w = data_in[i]; + end + end + end + assign data_out = data_out_w; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_onehot_shift.sv b/designs/src/vortex/rtl/libs/VX_onehot_shift.sv new file mode 100644 index 0000000..3222e30 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_onehot_shift.sv @@ -0,0 +1,32 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_onehot_shift #( + parameter N = 1, + parameter M = 1 +) ( + input wire [N-1:0] data_in0, + input wire [M-1:0] data_in1, + output wire [N*M-1:0] data_out +); + for (genvar i = 0; i < M; ++i) begin : g_i + for (genvar j = 0; j < N; ++j) begin : g_j + assign data_out[i*N + j] = data_in1[i] & data_in0[j]; + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_pe_serializer.sv b/designs/src/vortex/rtl/libs/VX_pe_serializer.sv new file mode 100644 index 0000000..4a66a63 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_pe_serializer.sv @@ -0,0 +1,157 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_pe_serializer #( + parameter NUM_LANES = 1, + parameter NUM_PES = 1, + parameter LATENCY = 1, + parameter DATA_IN_WIDTH = 1, + parameter DATA_OUT_WIDTH = 1, + parameter TAG_WIDTH = 0, + parameter PE_REG = 0, + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + // input + input wire valid_in, + input wire [NUM_LANES-1:0][DATA_IN_WIDTH-1:0] data_in, + input wire [TAG_WIDTH-1:0] tag_in, + output wire ready_in, + + // PE + output wire pe_enable, + output wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_out, + input wire [NUM_PES-1:0][DATA_OUT_WIDTH-1:0] pe_data_in, + + // output + output wire valid_out, + output wire [NUM_LANES-1:0][DATA_OUT_WIDTH-1:0] data_out, + output wire [TAG_WIDTH-1:0] tag_out, + input wire ready_out +); + wire valid_out_u; + wire [NUM_LANES-1:0][DATA_OUT_WIDTH-1:0] data_out_u; + wire [TAG_WIDTH-1:0] tag_out_u; + wire ready_out_u; + + wire [NUM_PES-1:0][DATA_IN_WIDTH-1:0] pe_data_out_w; + wire pe_valid_in; + wire [TAG_WIDTH-1:0] pe_tag_in; + wire enable; + + VX_shift_register #( + .DATAW (1 + TAG_WIDTH), + .DEPTH (PE_REG + LATENCY), + .RESETW (1) + ) shift_reg ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({valid_in, tag_in}), + .data_out ({pe_valid_in, pe_tag_in}) + ); + + VX_pipe_register #( + .DATAW (NUM_PES * DATA_IN_WIDTH), + .DEPTH (PE_REG) + ) pe_data_reg ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (pe_data_out_w), + .data_out (pe_data_out) + ); + + assign pe_enable = enable; + + if (NUM_LANES != NUM_PES) begin : g_serialize + + localparam BATCH_SIZE = NUM_LANES / NUM_PES; + localparam BATCH_SIZEW = `LOG2UP(BATCH_SIZE); + + reg [BATCH_SIZEW-1:0] batch_in_idx, batch_out_idx; + reg batch_in_done, batch_out_done; + + for (genvar i = 0; i < NUM_PES; ++i) begin : g_pe_data_out_w + assign pe_data_out_w[i] = data_in[batch_in_idx * NUM_PES + i]; + end + + always @(posedge clk) begin + if (reset) begin + batch_in_idx <= '0; + batch_out_idx <= '0; + batch_in_done <= 0; + batch_out_done <= 0; + end else if (enable) begin + batch_in_idx <= batch_in_idx + BATCH_SIZEW'(valid_in); + batch_out_idx <= batch_out_idx + BATCH_SIZEW'(pe_valid_in); + batch_in_done <= valid_in && (batch_in_idx == BATCH_SIZEW'(BATCH_SIZE-2)); + batch_out_done <= pe_valid_in && (batch_out_idx == BATCH_SIZEW'(BATCH_SIZE-2)); + end + end + + reg [BATCH_SIZE-1:0][(NUM_PES * DATA_OUT_WIDTH)-1:0] data_out_r, data_out_n; + + always @(*) begin + data_out_n = data_out_r; + if (pe_valid_in) begin + data_out_n[batch_out_idx] = pe_data_in; + end + end + + always @(posedge clk) begin + data_out_r <= data_out_n; + end + + assign enable = ready_out_u || ~valid_out_u; + assign ready_in = enable && batch_in_done; + + assign valid_out_u = batch_out_done; + assign data_out_u = data_out_n; + assign tag_out_u = pe_tag_in; + + end else begin : g_passthru + + assign pe_data_out_w = data_in; + + assign enable = ready_out_u || ~pe_valid_in; + assign ready_in = enable; + + assign valid_out_u = pe_valid_in; + assign data_out_u = pe_data_in; + assign tag_out_u = pe_tag_in; + + end + + VX_elastic_buffer #( + .DATAW (NUM_LANES * DATA_OUT_WIDTH + TAG_WIDTH), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_u), + .ready_in (ready_out_u), + .data_in ({data_out_u, tag_out_u}), + .data_out ({data_out, tag_out}), + .valid_out (valid_out), + .ready_out (ready_out) + ); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_pending_size.sv b/designs/src/vortex/rtl/libs/VX_pending_size.sv new file mode 100644 index 0000000..b94889e --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_pending_size.sv @@ -0,0 +1,192 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_pending_size #( + parameter SIZE = 1, + parameter INCRW = 1, + parameter DECRW = 1, + parameter ALM_FULL = (SIZE - 1), + parameter ALM_EMPTY = 1, + parameter SIZEW = `CLOG2(SIZE+1) +) ( + input wire clk, + input wire reset, + input wire [INCRW-1:0] incr, + input wire [DECRW-1:0] decr, + output wire empty, + output wire alm_empty, + output wire full, + output wire alm_full, + output wire [SIZEW-1:0] size +); + `STATIC_ASSERT(INCRW <= SIZEW, ("invalid parameter: %d vs %d", INCRW, SIZEW)) + `STATIC_ASSERT(DECRW <= SIZEW, ("invalid parameter: %d vs %d", DECRW, SIZEW)) + + if (SIZE == 1) begin : g_size_eq1 + + reg size_r; + + always @(posedge clk) begin + if (reset) begin + size_r <= '0; + end else begin + if (incr) begin + if (~decr) begin + size_r <= 1; + end + end else if (decr) begin + size_r <= '0; + end + end + end + + assign empty = (size_r == 0); + assign full = (size_r != 0); + assign alm_empty = 1'b1; + assign alm_full = 1'b1; + assign size = size_r; + + end else begin : g_size_gt1 + + reg empty_r, alm_empty_r; + reg full_r, alm_full_r; + + if (INCRW != 1 || DECRW != 1) begin : g_wide_step + + localparam DELTAW = `MIN(SIZEW, `MAX(INCRW, DECRW)+1); + + logic [SIZEW-1:0] size_n, size_r; + + wire [DELTAW-1:0] delta = DELTAW'(incr) - DELTAW'(decr); + + assign size_n = $signed(size_r) + SIZEW'($signed(delta)); + + always @(posedge clk) begin + if (reset) begin + empty_r <= 1; + full_r <= 0; + alm_empty_r <= 1; + alm_full_r <= 0; + size_r <= '0; + end else begin + `ASSERT((DELTAW'(incr) <= DELTAW'(decr)) || (size_n >= size_r), ("runtime error: counter overflow")); + `ASSERT((DELTAW'(incr) >= DELTAW'(decr)) || (size_n <= size_r), ("runtime error: counter underflow")); + empty_r <= (size_n == SIZEW'(0)); + full_r <= (size_n == SIZEW'(SIZE)); + alm_empty_r <= (size_n <= SIZEW'(ALM_EMPTY)); + alm_full_r <= (size_n >= SIZEW'(ALM_FULL)); + size_r <= size_n; + end + end + + assign size = size_r; + + end else begin : g_single_step + + localparam ADDRW = `LOG2UP(SIZE); + + reg [ADDRW-1:0] used_r; + + wire is_alm_empty = (used_r == ADDRW'(ALM_EMPTY)); + wire is_alm_empty_n = (used_r == ADDRW'(ALM_EMPTY+1)); + wire is_alm_full = (used_r == ADDRW'(ALM_FULL)); + wire is_alm_full_n = (used_r == ADDRW'(ALM_FULL-1)); + + always @(posedge clk) begin + if (reset) begin + alm_empty_r <= 1; + alm_full_r <= 0; + end else begin + if (incr) begin + if (~decr) begin + if (is_alm_empty) + alm_empty_r <= 0; + if (is_alm_full_n) + alm_full_r <= 1; + end + end else if (decr) begin + if (is_alm_full) + alm_full_r <= 0; + if (is_alm_empty_n) + alm_empty_r <= 1; + end + end + end + + if (SIZE > 2) begin : g_size_gt2 + + wire is_empty_n = (used_r == ADDRW'(1)); + wire is_full_n = (used_r == ADDRW'(SIZE-1)); + + wire [1:0] delta = {~incr & decr, incr ^ decr}; + + always @(posedge clk) begin + if (reset) begin + empty_r <= 1; + full_r <= 0; + used_r <= '0; + end else begin + if (incr) begin + if (~decr) begin + empty_r <= 0; + if (is_full_n) + full_r <= 1; + end + end else if (decr) begin + full_r <= 0; + if (is_empty_n) + empty_r <= 1; + end + used_r <= $signed(used_r) + ADDRW'($signed(delta)); + end + end + + end else begin : g_size_eq2 + + always @(posedge clk) begin + if (reset) begin + empty_r <= 1; + full_r <= 0; + used_r <= '0; + end else begin + empty_r <= (empty_r & ~incr) | (~full_r & decr & ~incr); + full_r <= (~empty_r & incr & ~decr) | (full_r & ~(decr ^ incr)); + used_r <= used_r ^ (incr ^ decr); + end + end + end + + if (SIZE > 1) begin : g_sizeN + if (SIZEW > ADDRW) begin : g_not_log2 + assign size = {full_r, used_r}; + end else begin : g_log2 + assign size = used_r; + end + end else begin : g_size1 + assign size = full_r; + end + + end + + assign empty = empty_r; + assign full = full_r; + assign alm_empty = alm_empty_r; + assign alm_full = alm_full_r; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_pipe_buffer.sv b/designs/src/vortex/rtl/libs/VX_pipe_buffer.sv new file mode 100644 index 0000000..5ba23bc --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_pipe_buffer.sv @@ -0,0 +1,77 @@ +// Copyright 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A pipelined elastic buffer operates at full bandwidth where push can happen if the buffer is not empty but is going empty +// It has the following benefits: +// + Full-bandwidth throughput +// + use only one register for storage +// + data_out is fully registered +// It has the following limitations: +// + ready_in and ready_out are coupled + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_pipe_buffer #( + parameter DATAW = 1, + parameter RESETW = 0, + parameter DEPTH = 1 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (DEPTH == 0) begin : g_passthru + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + assign ready_in = ready_out; + assign valid_out = valid_in; + assign data_out = data_in; + end else begin : g_register + wire [DEPTH:0] valid; + `IGNORE_UNOPTFLAT_BEGIN + wire ready [DEPTH+1]; + `IGNORE_UNOPTFLAT_END + wire [DEPTH:0][DATAW-1:0] data; + + assign valid[0] = valid_in; + assign data[0] = data_in; + assign ready_in = ready[0]; + + for (genvar i = 0; i < DEPTH; ++i) begin : g_pipe_regs + assign ready[i] = (ready[i+1] || ~valid[i+1]); + VX_pipe_register #( + .DATAW (1 + DATAW), + .RESETW (1 + RESETW) + ) pipe_register ( + .clk (clk), + .reset (reset), + .enable (ready[i]), + .data_in ({valid[i], data[i]}), + .data_out ({valid[i+1], data[i+1]}) + ); + end + + assign valid_out = valid[DEPTH]; + assign data_out = data[DEPTH]; + assign ready[DEPTH] = ready_out; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_pipe_register.sv b/designs/src/vortex/rtl/libs/VX_pipe_register.sv new file mode 100644 index 0000000..74abfa9 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_pipe_register.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_pipe_register #( + parameter DATAW = 1, + parameter RESETW = 0, + parameter DEPTH = 1, + parameter [`UP(RESETW)-1:0] INIT_VALUE = {`UP(RESETW){1'b0}} +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out +); + VX_shift_register #( + .DATAW (DATAW), + .RESETW (RESETW), + .DEPTH (DEPTH), + .INIT_VALUE (INIT_VALUE) + ) g_shift_register ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (data_in), + .data_out (data_out) + ); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_placeholder.sv b/designs/src/vortex/rtl/libs/VX_placeholder.sv new file mode 100644 index 0000000..738da61 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_placeholder.sv @@ -0,0 +1,27 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +`BLACKBOX_CELL module VX_placeholder #( + parameter I = 0, + parameter O = 0 +) ( + input wire [`UP(I)-1:0] in, + output wire [`UP(O)-1:0] out +); + // empty module + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_popcount.sv b/designs/src/vortex/rtl/libs/VX_popcount.sv new file mode 100644 index 0000000..fa8c490 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_popcount.sv @@ -0,0 +1,224 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_popcount63( + input wire [5:0] data_in, + output wire [2:0] data_out +); + reg [2:0] sum; + always @(*) begin + case (data_in) + 6'd0: sum=3'd0; 6'd1: sum=3'd1; 6'd2: sum=3'd1; 6'd3: sum=3'd2; + 6'd4: sum=3'd1; 6'd5: sum=3'd2; 6'd6: sum=3'd2; 6'd7: sum=3'd3; + 6'd8: sum=3'd1; 6'd9: sum=3'd2; 6'd10: sum=3'd2; 6'd11: sum=3'd3; + 6'd12: sum=3'd2; 6'd13: sum=3'd3; 6'd14: sum=3'd3; 6'd15: sum=3'd4; + 6'd16: sum=3'd1; 6'd17: sum=3'd2; 6'd18: sum=3'd2; 6'd19: sum=3'd3; + 6'd20: sum=3'd2; 6'd21: sum=3'd3; 6'd22: sum=3'd3; 6'd23: sum=3'd4; + 6'd24: sum=3'd2; 6'd25: sum=3'd3; 6'd26: sum=3'd3; 6'd27: sum=3'd4; + 6'd28: sum=3'd3; 6'd29: sum=3'd4; 6'd30: sum=3'd4; 6'd31: sum=3'd5; + 6'd32: sum=3'd1; 6'd33: sum=3'd2; 6'd34: sum=3'd2; 6'd35: sum=3'd3; + 6'd36: sum=3'd2; 6'd37: sum=3'd3; 6'd38: sum=3'd3; 6'd39: sum=3'd4; + 6'd40: sum=3'd2; 6'd41: sum=3'd3; 6'd42: sum=3'd3; 6'd43: sum=3'd4; + 6'd44: sum=3'd3; 6'd45: sum=3'd4; 6'd46: sum=3'd4; 6'd47: sum=3'd5; + 6'd48: sum=3'd2; 6'd49: sum=3'd3; 6'd50: sum=3'd3; 6'd51: sum=3'd4; + 6'd52: sum=3'd3; 6'd53: sum=3'd4; 6'd54: sum=3'd4; 6'd55: sum=3'd5; + 6'd56: sum=3'd3; 6'd57: sum=3'd4; 6'd58: sum=3'd4; 6'd59: sum=3'd5; + 6'd60: sum=3'd4; 6'd61: sum=3'd5; 6'd62: sum=3'd5; 6'd63: sum=3'd6; + endcase + end + assign data_out = sum; +endmodule + +module VX_popcount32( + input wire [2:0] data_in, + output wire [1:0] data_out +); + reg [1:0] sum; + always @(*) begin + case (data_in) + 3'd0: sum=2'd0; 3'd1: sum=2'd1; 3'd2: sum=2'd1; 3'd3: sum=2'd2; + 3'd4: sum=2'd1; 3'd5: sum=2'd2; 3'd6: sum=2'd2; 3'd7: sum=2'd3; + endcase + end + assign data_out = sum; +endmodule + +module VX_sum33( + input wire [2:0] data_in1, + input wire [2:0] data_in2, + output wire [3:0] data_out +); + reg [3:0] sum; + always @(*) begin + case ({data_in1, data_in2}) + 6'd0: sum=4'd0; 6'd1: sum=4'd1; 6'd2: sum=4'd2; 6'd3: sum=4'd3; + 6'd4: sum=4'd4; 6'd5: sum=4'd5; 6'd6: sum=4'd6; 6'd7: sum=4'd7; + 6'd8: sum=4'd1; 6'd9: sum=4'd2; 6'd10: sum=4'd3; 6'd11: sum=4'd4; + 6'd12: sum=4'd5; 6'd13: sum=4'd6; 6'd14: sum=4'd7; 6'd15: sum=4'd8; + 6'd16: sum=4'd2; 6'd17: sum=4'd3; 6'd18: sum=4'd4; 6'd19: sum=4'd5; + 6'd20: sum=4'd6; 6'd21: sum=4'd7; 6'd22: sum=4'd8; 6'd23: sum=4'd9; + 6'd24: sum=4'd3; 6'd25: sum=4'd4; 6'd26: sum=4'd5; 6'd27: sum=4'd6; + 6'd28: sum=4'd7; 6'd29: sum=4'd8; 6'd30: sum=4'd9; 6'd31: sum=4'd10; + 6'd32: sum=4'd4; 6'd33: sum=4'd5; 6'd34: sum=4'd6; 6'd35: sum=4'd7; + 6'd36: sum=4'd8; 6'd37: sum=4'd9; 6'd38: sum=4'd10; 6'd39: sum=4'd11; + 6'd40: sum=4'd5; 6'd41: sum=4'd6; 6'd42: sum=4'd7; 6'd43: sum=4'd8; + 6'd44: sum=4'd9; 6'd45: sum=4'd10; 6'd46: sum=4'd11; 6'd47: sum=4'd12; + 6'd48: sum=4'd6; 6'd49: sum=4'd7; 6'd50: sum=4'd8; 6'd51: sum=4'd9; + 6'd52: sum=4'd10; 6'd53: sum=4'd11; 6'd54: sum=4'd12; 6'd55: sum=4'd13; + 6'd56: sum=4'd7; 6'd57: sum=4'd8; 6'd58: sum=4'd9; 6'd59: sum=4'd10; + 6'd60: sum=4'd11; 6'd61: sum=4'd12; 6'd62: sum=4'd13; 6'd63: sum=4'd14; + endcase + end + assign data_out = sum; +endmodule + +module VX_popcount #( + parameter MODEL = 1, + parameter N = 1, + parameter M = `CLOG2(N+1) +) ( + input wire [N-1:0] data_in, + output wire [M-1:0] data_out +); + `UNUSED_PARAM (MODEL) + +`ifndef SYNTHESIS + assign data_out = $countones(data_in); +`elsif QUARTUS + assign data_out = $countones(data_in); +`else + if (N == 1) begin : g_passthru + + assign data_out = data_in; + + end else if (N <= 3) begin : g_popcount3 + + reg [2:0] t_in; + wire [1:0] t_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount32 pc32(t_in, t_out); + assign data_out = t_out[M-1:0]; + + end else if (N <= 6) begin : g_popcount6 + + reg [5:0] t_in; + wire [2:0] t_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63(t_in, t_out); + assign data_out = t_out[M-1:0]; + + end else if (N <= 9) begin : g_popcount9 + + reg [8:0] t_in; + wire [4:0] t1_out; + wire [3:0] t2_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63(t_in[5:0], t1_out[2:0]); + VX_popcount32 pc32(t_in[8:6], t1_out[4:3]); + VX_sum33 sum33(t1_out[2:0], {1'b0, t1_out[4:3]}, t2_out); + assign data_out = t2_out[M-1:0]; + + end else if (N <= 12) begin : g_popcount12 + + reg [11:0] t_in; + wire [5:0] t1_out; + wire [3:0] t2_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]); + VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]); + VX_sum33 sum33(t1_out[2:0], t1_out[5:3], t2_out); + assign data_out = t2_out[M-1:0]; + + end else if (N <= 18) begin : g_popcount18 + + reg [17:0] t_in; + wire [8:0] t1_out; + wire [5:0] t2_out; + always @(*) begin + t_in = '0; + t_in[N-1:0] = data_in; + end + VX_popcount63 pc63a(t_in[5:0], t1_out[2:0]); + VX_popcount63 pc63b(t_in[11:6], t1_out[5:3]); + VX_popcount63 pc63c(t_in[17:12], t1_out[8:6]); + VX_popcount32 pc32a({t1_out[0], t1_out[3], t1_out[6]}, t2_out[1:0]); + VX_popcount32 pc32b({t1_out[1], t1_out[4], t1_out[7]}, t2_out[3:2]); + VX_popcount32 pc32c({t1_out[2], t1_out[5], t1_out[8]}, t2_out[5:4]); + assign data_out = {2'b0,t2_out[1:0]} + {1'b0,t2_out[3:2],1'b0} + {t2_out[5:4],2'b0}; + + end else if (MODEL == 1) begin : g_model1 + + localparam PN = 1 << `CLOG2(N); + localparam LOGPN = `CLOG2(PN); + + `IGNORE_UNOPTFLAT_BEGIN + wire [M-1:0] tmp [LOGPN-1:0][PN-1:0]; + `IGNORE_UNOPTFLAT_END + + for (genvar j = 0; j < LOGPN; ++j) begin + localparam D = j + 1; + localparam Q = (D < LOGPN) ? (D + 1) : M; + for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin + localparam l = i * 2; + localparam r = i * 2 + 1; + wire [Q-1:0] res; + if (j == 0) begin + if (r < N) begin + assign res = data_in[l] + data_in[r]; + end else if (l < N) begin + assign res = 2'(data_in[l]); + end else begin + assign res = 2'b0; + end + end else begin + assign res = D'(tmp[j-1][l]) + D'(tmp[j-1][r]); + end + assign tmp[j][i] = M'(res); + end + end + + assign data_out = tmp[LOGPN-1][0]; + + end else begin : g_model2 + + reg [M-1:0] cnt_w; + + always @(*) begin + cnt_w = '0; + for (integer i = 0; i < N; ++i) begin + cnt_w = cnt_w + M'(data_in[i]); + end + end + + assign data_out = cnt_w; + + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_priority_arbiter.sv b/designs/src/vortex/rtl/libs/VX_priority_arbiter.sv new file mode 100644 index 0000000..df7b34f --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_priority_arbiter.sv @@ -0,0 +1,73 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_priority_arbiter #( + parameter NUM_REQS = 1, + parameter STICKY = 0, // hold the grant until its request is deasserted + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS) +) ( + input wire clk, + input wire reset, + input wire [NUM_REQS-1:0] requests, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid, + input wire grant_ready +); + if (NUM_REQS == 1) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (grant_ready) + `UNUSED_PARAM (STICKY) + + assign grant_index = '0; + assign grant_onehot = requests; + assign grant_valid = requests[0]; + + end else begin : g_encoder + + reg [NUM_REQS-1:0] prev_grant; + + always @(posedge clk) begin + if (reset) begin + prev_grant <= '0; + end else if (grant_valid && grant_ready) begin + prev_grant <= grant_onehot; + end + end + + wire retain_grant = (STICKY != 0) && (|(prev_grant & requests)); + + wire [NUM_REQS-1:0] requests_w = retain_grant ? prev_grant : requests; + + wire grant_valid_w; + + VX_priority_encoder #( + .N (NUM_REQS) + ) grant_sel ( + .data_in (requests_w), + .index_out (grant_index), + .onehot_out (grant_onehot), + .valid_out (grant_valid_w) + ); + + assign grant_valid = (STICKY != 0) ? (| requests) : grant_valid_w; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_priority_encoder.sv b/designs/src/vortex/rtl/libs/VX_priority_encoder.sv new file mode 100644 index 0000000..ded1fdc --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_priority_encoder.sv @@ -0,0 +1,187 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_priority_encoder #( + parameter N = 1, + parameter REVERSE = 0, // 0 -> LSB, 1 -> MSB + parameter MODEL = 1, + parameter LN = `LOG2UP(N) +) ( + input wire [N-1:0] data_in, + output wire [N-1:0] onehot_out, + output wire [LN-1:0] index_out, + output wire valid_out +); + if (REVERSE) begin : g_msb + + if (N == 1) begin : g_n1 + + assign onehot_out = data_in; + assign index_out = '0; + assign valid_out = data_in; + + end else if (N == 2) begin : g_n2 + + assign onehot_out = {data_in[1], data_in[0] & ~data_in[1]}; + assign index_out = data_in[1]; + assign valid_out = (| data_in); + + end else if (MODEL != 0) begin : g_model1 + + `IGNORE_UNOPTFLAT_BEGIN + wire [N-1:0] higher_pri_regs; + `IGNORE_UNOPTFLAT_END + + assign higher_pri_regs[N-1] = 1'b0; + for (genvar i = N-2; i >= 0; --i) begin : g_higher_pri_regs + assign higher_pri_regs[i] = higher_pri_regs[i+1] | data_in[i+1]; + end + assign onehot_out = data_in & ~higher_pri_regs; + + wire [N-1:0][LN-1:0] indices; + for (genvar i = 0; i < N; ++i) begin : g_indices + assign indices[i] = LN'(i); + end + + VX_find_first #( + .N (N), + .DATAW (LN), + .REVERSE (1) + ) find_first ( + .valid_in (data_in), + .data_in (indices), + .data_out (index_out), + .valid_out (valid_out) + ); + + end else begin : g_model0 + + reg [LN-1:0] index_w; + reg [N-1:0] onehot_w; + + always @(*) begin + index_w = 'x; + onehot_w = 'x; + for (integer i = 0; i < N-1; ++i) begin + if (data_in[i]) begin + index_w = LN'(i); + onehot_w = N'(1) << i; + end + end + end + + assign index_out = index_w; + assign onehot_out = onehot_w; + assign valid_out = (| data_in); + + end + + end else begin: g_lsb + + if (N == 1) begin : g_n1 + + assign onehot_out = data_in; + assign index_out = '0; + assign valid_out = data_in; + + end else if (N == 2) begin : g_n2 + + assign onehot_out = {data_in[1] && ~data_in[0], data_in[0]}; + assign index_out = ~data_in[0]; + assign valid_out = (| data_in); + + end else if (MODEL == 1) begin : g_model1 + + `IGNORE_UNOPTFLAT_BEGIN + wire [N-1:0] higher_pri_regs; + `IGNORE_UNOPTFLAT_END + + assign higher_pri_regs[0] = 1'b0; + for (genvar i = 1; i < N; ++i) begin : g_higher_pri_regs + assign higher_pri_regs[i] = higher_pri_regs[i-1] | data_in[i-1]; + end + assign onehot_out[N-1:0] = data_in[N-1:0] & ~higher_pri_regs[N-1:0]; + + VX_lzc #( + .N (N), + .REVERSE (1) + ) lzc ( + .data_in (data_in), + .data_out (index_out), + .valid_out (valid_out) + ); + + end else if (MODEL == 2) begin : g_model2 + + wire [N-1:0] scan_lo; + + VX_scan #( + .N (N), + .OP ("|") + ) scan ( + .data_in (data_in), + .data_out (scan_lo) + ); + + assign onehot_out = scan_lo & {(~scan_lo[N-2:0]), 1'b1}; + + VX_lzc #( + .N (N), + .REVERSE (1) + ) lzc ( + .data_in (data_in), + .data_out (index_out), + .valid_out(valid_out) + ); + + end else if (MODEL == 3) begin : g_model3 + + assign onehot_out = data_in & -data_in; + + VX_lzc #( + .N (N), + .REVERSE (1) + ) lzc ( + .data_in (data_in), + .data_out (index_out), + .valid_out (valid_out) + ); + + end else begin : g_model0 + + reg [LN-1:0] index_w; + reg [N-1:0] onehot_w; + + always @(*) begin + index_w = 'x; + onehot_w = 'x; + for (integer i = N-1; i >= 0; --i) begin + if (data_in[i]) begin + index_w = LN'(i); + onehot_w = N'(1) << i; + end + end + end + + assign index_out = index_w; + assign onehot_out = onehot_w; + assign valid_out = (| data_in); + + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_reduce_tree.sv b/designs/src/vortex/rtl/libs/VX_reduce_tree.sv new file mode 100644 index 0000000..d342bf8 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_reduce_tree.sv @@ -0,0 +1,78 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_reduce_tree #( + parameter IN_W = 1, + parameter OUT_W = IN_W, + parameter N = 1, + parameter `STRING OP = "+" +) ( + input wire [N-1:0][IN_W-1:0] data_in, + output wire [OUT_W-1:0] data_out +); + if (N == 1) begin : g_passthru + assign data_out = OUT_W'(data_in[0]); + end else begin : g_reduce + localparam int N_A = N / 2; + localparam int N_B = N - N_A; + + wire [N_A-1:0][IN_W-1:0] in_A; + wire [N_B-1:0][IN_W-1:0] in_B; + wire [OUT_W-1:0] out_A, out_B; + + for (genvar i = 0; i < N_A; i++) begin : g_in_A + assign in_A[i] = data_in[i]; + end + + for (genvar i = 0; i < N_B; i++) begin : g_in_B + assign in_B[i] = data_in[N_A + i]; + end + + VX_reduce_tree #( + .IN_W (IN_W), + .OUT_W (OUT_W), + .N (N_A), + .OP (OP) + ) reduce_A ( + .data_in (in_A), + .data_out (out_A) + ); + + VX_reduce_tree #( + .IN_W (IN_W), + .OUT_W (OUT_W), + .N (N_B), + .OP (OP) + ) reduce_B ( + .data_in (in_B), + .data_out (out_B) + ); + + if (OP == "+") begin : g_plus + assign data_out = out_A + out_B; + end else if (OP == "^") begin : g_xor + assign data_out = out_A ^ out_B; + end else if (OP == "&") begin : g_and + assign data_out = out_A & out_B; + end else if (OP == "|") begin : g_or + assign data_out = out_A | out_B; + end else begin : g_error + `ERROR(("invalid parameter")); + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_reset_relay.sv b/designs/src/vortex/rtl/libs/VX_reset_relay.sv new file mode 100644 index 0000000..0e2a7f4 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_reset_relay.sv @@ -0,0 +1,43 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_reset_relay #( + parameter N = 1, + parameter MAX_FANOUT = 0 +) ( + input wire clk, + input wire reset, + output wire [N-1:0] reset_o +); + if (MAX_FANOUT >= 0 && N > (MAX_FANOUT + MAX_FANOUT/2)) begin : g_relay + localparam F = `UP(MAX_FANOUT); + localparam R = N / F; + `PRESERVE_NET reg [R-1:0] reset_r; + for (genvar i = 0; i < R; ++i) begin : g_reset_r + always @(posedge clk) begin + reset_r[i] <= reset; + end + end + for (genvar i = 0; i < N; ++i) begin : g_reset_o + assign reset_o[i] = reset_r[i / F]; + end + end else begin : g_passthru + `UNUSED_VAR (clk) + assign reset_o = {N{reset}}; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_rr_arbiter.sv b/designs/src/vortex/rtl/libs/VX_rr_arbiter.sv new file mode 100644 index 0000000..d74d50d --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_rr_arbiter.sv @@ -0,0 +1,538 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_rr_arbiter #( + parameter NUM_REQS = 1, + parameter MODEL = 1, + parameter LOG_NUM_REQS = `LOG2UP(NUM_REQS), + parameter STICKY = 0, // hold the grant until its request is deasserted + parameter LUT_OPT = 0 +) ( + input wire clk, + input wire reset, + input wire [NUM_REQS-1:0] requests, + output wire [LOG_NUM_REQS-1:0] grant_index, + output wire [NUM_REQS-1:0] grant_onehot, + output wire grant_valid, + input wire grant_ready +); + `STATIC_ASSERT ((STICKY == 0) || (MODEL == 1 && LUT_OPT == 0), ("Sticky is only supported in model 1")) + + if (NUM_REQS == 1) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (grant_ready) + `UNUSED_PARAM (STICKY) + + assign grant_index = '0; + assign grant_onehot = requests; + assign grant_valid = requests[0]; + + end else if (LUT_OPT && NUM_REQS == 2) begin : g_lut2 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 3'b0_01, + 3'b1_?1: begin grant_onehot_w = 2'b01; grant_index_w = LOG_NUM_REQS'(0); end + 3'b0_1?, + 3'b1_10: begin grant_onehot_w = 2'b10; grant_index_w = LOG_NUM_REQS'(1); end + default: begin grant_onehot_w = 2'b00; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (LUT_OPT && NUM_REQS == 3) begin : g_lut3 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 5'b00_001, + 5'b01_0?1, + 5'b10_??1: begin grant_onehot_w = 3'b001; grant_index_w = LOG_NUM_REQS'(0); end + 5'b00_?1?, + 5'b01_010, + 5'b10_?10: begin grant_onehot_w = 3'b010; grant_index_w = LOG_NUM_REQS'(1); end + 5'b00_10?, + 5'b01_1??, + 5'b10_100: begin grant_onehot_w = 3'b100; grant_index_w = LOG_NUM_REQS'(2); end + default: begin grant_onehot_w = 3'b000; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (LUT_OPT && NUM_REQS == 4) begin : g_lut4 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 6'b00_0001, + 6'b01_00?1, + 6'b10_0??1, + 6'b11_???1: begin grant_onehot_w = 4'b0001; grant_index_w = LOG_NUM_REQS'(0); end + 6'b00_??1?, + 6'b01_0010, + 6'b10_0?10, + 6'b11_??10: begin grant_onehot_w = 4'b0010; grant_index_w = LOG_NUM_REQS'(1); end + 6'b00_?10?, + 6'b01_?1??, + 6'b10_0100, + 6'b11_?100: begin grant_onehot_w = 4'b0100; grant_index_w = LOG_NUM_REQS'(2); end + 6'b00_100?, + 6'b01_10??, + 6'b10_1???, + 6'b11_1000: begin grant_onehot_w = 4'b1000; grant_index_w = LOG_NUM_REQS'(3); end + default: begin grant_onehot_w = 4'b0000; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (LUT_OPT && NUM_REQS == 5) begin : g_lut5 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 8'b000_00001, + 8'b001_000?1, + 8'b010_00??1, + 8'b011_0???1, + 8'b100_????1: begin grant_onehot_w = 5'b00001; grant_index_w = LOG_NUM_REQS'(0); end + 8'b000_???1?, + 8'b001_00010, + 8'b010_00?10, + 8'b011_0??10, + 8'b100_???10: begin grant_onehot_w = 5'b00010; grant_index_w = LOG_NUM_REQS'(1); end + 8'b000_??10?, + 8'b001_??1??, + 8'b010_00100, + 8'b011_0?100, + 8'b100_??100: begin grant_onehot_w = 5'b00100; grant_index_w = LOG_NUM_REQS'(2); end + 8'b000_?100?, + 8'b001_?10??, + 8'b010_?1???, + 8'b011_01000, + 8'b100_?1000: begin grant_onehot_w = 5'b01000; grant_index_w = LOG_NUM_REQS'(3); end + 8'b000_1000?, + 8'b001_100??, + 8'b010_10???, + 8'b011_1????, + 8'b100_10000: begin grant_onehot_w = 5'b10000; grant_index_w = LOG_NUM_REQS'(4); end + default: begin grant_onehot_w = 5'b00000; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (LUT_OPT && NUM_REQS == 6) begin : g_lut6 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 9'b000_000001, + 9'b001_0000?1, + 9'b010_000??1, + 9'b011_00???1, + 9'b100_0????1, + 9'b101_?????1: begin grant_onehot_w = 6'b000001; grant_index_w = LOG_NUM_REQS'(0); end + 9'b000_????1?, + 9'b001_000010, + 9'b010_000?10, + 9'b011_00??10, + 9'b100_0???10, + 9'b101_????10: begin grant_onehot_w = 6'b000010; grant_index_w = LOG_NUM_REQS'(1); end + 9'b000_???10?, + 9'b001_???1??, + 9'b010_000100, + 9'b011_00?100, + 9'b100_0??100, + 9'b101_???100: begin grant_onehot_w = 6'b000100; grant_index_w = LOG_NUM_REQS'(2); end + 9'b000_??100?, + 9'b001_??10??, + 9'b010_??1???, + 9'b011_001000, + 9'b100_0?1000, + 9'b101_??1000: begin grant_onehot_w = 6'b001000; grant_index_w = LOG_NUM_REQS'(3); end + 9'b000_?1000?, + 9'b001_?100??, + 9'b010_?10???, + 9'b011_?1????, + 9'b100_010000, + 9'b101_?10000: begin grant_onehot_w = 6'b010000; grant_index_w = LOG_NUM_REQS'(4); end + 9'b000_10000?, + 9'b001_1000??, + 9'b010_100???, + 9'b011_10????, + 9'b100_1?????, + 9'b101_100000: begin grant_onehot_w = 6'b100000; grant_index_w = LOG_NUM_REQS'(5); end + default: begin grant_onehot_w = 6'b000000; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (LUT_OPT && NUM_REQS == 7) begin : g_lut7 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 10'b000_0000001, + 10'b001_00000?1, + 10'b010_0000??1, + 10'b011_000???1, + 10'b100_000???1, + 10'b101_00????1, + 10'b110_??????1: begin grant_onehot_w = 7'b0000001; grant_index_w = LOG_NUM_REQS'(0); end + 10'b000_?????1?, + 10'b001_0000010, + 10'b010_0000?10, + 10'b011_000??10, + 10'b100_00???10, + 10'b101_0????10, + 10'b110_?????10: begin grant_onehot_w = 7'b0000010; grant_index_w = LOG_NUM_REQS'(1); end + 10'b000_????10?, + 10'b001_????1??, + 10'b010_0000100, + 10'b011_000?100, + 10'b100_00??100, + 10'b101_0???100, + 10'b110_????100: begin grant_onehot_w = 7'b0000100; grant_index_w = LOG_NUM_REQS'(2); end + 10'b000_???100?, + 10'b001_???10??, + 10'b010_???1???, + 10'b011_0001000, + 10'b100_00?1000, + 10'b101_0??1000, + 10'b110_???1000: begin grant_onehot_w = 7'b0001000; grant_index_w = LOG_NUM_REQS'(3); end + 10'b000_??1000?, + 10'b001_??100??, + 10'b010_??10???, + 10'b011_??1????, + 10'b100_0010000, + 10'b101_0?10000, + 10'b110_??10000: begin grant_onehot_w = 7'b0010000; grant_index_w = LOG_NUM_REQS'(4); end + 10'b000_?10000?, + 10'b001_?1000??, + 10'b010_?100???, + 10'b011_?10????, + 10'b100_?1?????, + 10'b101_0100000, + 10'b110_?100000: begin grant_onehot_w = 7'b0100000; grant_index_w = LOG_NUM_REQS'(5); end + 10'b000_100000?, + 10'b001_10000??, + 10'b010_1000???, + 10'b011_100????, + 10'b100_10?????, + 10'b101_1??????, + 10'b110_1000000: begin grant_onehot_w = 7'b1000000; grant_index_w = LOG_NUM_REQS'(6); end + default: begin grant_onehot_w = 7'b0000000; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (LUT_OPT && NUM_REQS == 8) begin : g_lut8 + + `UNUSED_PARAM (STICKY) + + reg [LOG_NUM_REQS-1:0] grant_index_w; + reg [NUM_REQS-1:0] grant_onehot_w; + reg [LOG_NUM_REQS-1:0] state; + + always @(*) begin + casez ({state, requests}) + 11'b000_00000001, + 11'b001_000000?1, + 11'b010_00000??1, + 11'b011_0000???1, + 11'b100_000????1, + 11'b101_00?????1, + 11'b110_0??????1, + 11'b111_???????1: begin grant_onehot_w = 8'b00000001; grant_index_w = LOG_NUM_REQS'(0); end + 11'b000_??????1?, + 11'b001_00000010, + 11'b010_00000?10, + 11'b011_0000??10, + 11'b100_000???10, + 11'b101_00????10, + 11'b110_0?????10, + 11'b111_??????10: begin grant_onehot_w = 8'b00000010; grant_index_w = LOG_NUM_REQS'(1); end + 11'b000_?????10?, + 11'b001_?????1??, + 11'b010_00000100, + 11'b011_0000?100, + 11'b100_000??100, + 11'b101_00???100, + 11'b110_0????100, + 11'b111_?????100: begin grant_onehot_w = 8'b00000100; grant_index_w = LOG_NUM_REQS'(2); end + 11'b000_????100?, + 11'b001_????10??, + 11'b010_????1???, + 11'b011_00001000, + 11'b100_000?1000, + 11'b101_00??1000, + 11'b110_0???1000, + 11'b111_????1000: begin grant_onehot_w = 8'b00001000; grant_index_w = LOG_NUM_REQS'(3); end + 11'b000_???1000?, + 11'b001_???100??, + 11'b010_???10???, + 11'b011_???1????, + 11'b100_00010000, + 11'b101_00?10000, + 11'b110_0??10000, + 11'b111_???10000: begin grant_onehot_w = 8'b00010000; grant_index_w = LOG_NUM_REQS'(4); end + 11'b000_??10000?, + 11'b001_??1000??, + 11'b010_??100???, + 11'b011_??10????, + 11'b100_??1?????, + 11'b101_00100000, + 11'b110_0?100000, + 11'b111_??100000: begin grant_onehot_w = 8'b00100000; grant_index_w = LOG_NUM_REQS'(5); end + 11'b000_?100000?, + 11'b001_?10000??, + 11'b010_?1000???, + 11'b011_?100????, + 11'b100_?10?????, + 11'b101_?1??????, + 11'b110_01000000, + 11'b111_?1000000: begin grant_onehot_w = 8'b01000000; grant_index_w = LOG_NUM_REQS'(6); end + 11'b000_1000000?, + 11'b001_100000??, + 11'b010_10000???, + 11'b011_1000????, + 11'b100_100?????, + 11'b101_10??????, + 11'b110_1???????, + 11'b111_10000000: begin grant_onehot_w = 8'b10000000; grant_index_w = LOG_NUM_REQS'(7); end + default: begin grant_onehot_w = 8'b00000000; grant_index_w = 'x; end + endcase + end + + always @(posedge clk) begin + if (reset) begin + state <= '0; + end else if (grant_valid && grant_ready) begin + state <= grant_index_w; + end + end + + assign grant_index = grant_index_w; + assign grant_onehot = grant_onehot_w; + assign grant_valid = (| requests); + + end else if (MODEL == 1) begin : g_model1 + + `IGNORE_UNOPTFLAT_BEGIN + wire [NUM_REQS-1:0] masked_pri_reqs, unmasked_pri_reqs; + `IGNORE_UNOPTFLAT_END + reg [NUM_REQS-1:0] reqs_mask; + + wire [NUM_REQS-1:0] masked_reqs = requests & reqs_mask; + + assign masked_pri_reqs[0] = 1'b0; + for (genvar i = 1; i < NUM_REQS; ++i) begin : g_masked_pri_reqs + assign masked_pri_reqs[i] = masked_pri_reqs[i-1] | masked_reqs[i-1]; + end + + assign unmasked_pri_reqs[0] = 1'b0; + for (genvar i = 1; i < NUM_REQS; ++i) begin : g_unmasked_pri_reqs + assign unmasked_pri_reqs[i] = unmasked_pri_reqs[i-1] | requests[i-1]; + end + + wire [NUM_REQS-1:0] grant_masked = masked_reqs & ~masked_pri_reqs; + wire [NUM_REQS-1:0] grant_unmasked = requests & ~unmasked_pri_reqs; + + wire has_masked_reqs = (| masked_reqs); + wire has_unmasked_reqs = (| requests); + + reg [NUM_REQS-1:0] prev_grant; + + always @(posedge clk) begin + if (reset) begin + prev_grant <= '0; + end else if (grant_valid && grant_ready) begin + prev_grant <= grant_onehot; + end + end + + wire retain_grant = (STICKY != 0) && (|(prev_grant & requests)); + + wire [NUM_REQS-1:0] grant = has_masked_reqs ? grant_masked : grant_unmasked; + + wire [NUM_REQS-1:0] grant_w = retain_grant ? prev_grant : grant; + + assign grant_onehot = grant_w; + + always @(posedge clk) begin + if (reset) begin + reqs_mask <= {NUM_REQS{1'b1}}; + end else if (grant_valid && grant_ready && ~retain_grant) begin + if (has_masked_reqs) begin + reqs_mask <= masked_pri_reqs; + end else if (has_unmasked_reqs) begin + reqs_mask <= unmasked_pri_reqs; + end + end + end + + wire grant_valid_w; + + VX_onehot_encoder #( + .N (NUM_REQS) + ) onehot_encoder ( + .data_in (grant_w), + .data_out (grant_index), + .valid_out(grant_valid_w) + ); + + assign grant_valid = (STICKY != 0) ? (| requests) : grant_valid_w; + + end else if (MODEL == 2) begin : g_model2 + + `UNUSED_PARAM (STICKY) + + reg [NUM_REQS-1:0][LOG_NUM_REQS-1:0] grant_table; + reg [LOG_NUM_REQS-1:0] state; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_grant_table + always @(*) begin + grant_table[i] = 'x; + for (integer j = NUM_REQS-1; j >= 0; --j) begin + if (requests[(i+j+1) % NUM_REQS]) begin + grant_table[i] = LOG_NUM_REQS'((i+j+1) % NUM_REQS); + end + end + end + end + + always @(posedge clk) begin + if (reset) begin + state <= 0; + end else if (grant_valid && grant_ready) begin + state <= grant_index; + end + end + + VX_demux #( + .DATAW (1), + .N (NUM_REQS) + ) grant_decoder ( + .sel_in (grant_index), + .data_in (grant_valid), + .data_out (grant_onehot) + ); + + assign grant_index = grant_table[state]; + assign grant_valid = (| requests); + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_scan.sv b/designs/src/vortex/rtl/libs/VX_scan.sv new file mode 100644 index 0000000..6effd58 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_scan.sv @@ -0,0 +1,76 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +// Fast Paralllel scan using Kogge-Stone style prefix tree with configurable operator +// Adapted from BaseJump STL: http://bjump.org/index.html + +`TRACING_OFF +module VX_scan #( + parameter N = 1, + parameter `STRING OP = "^", // ^: XOR, &: AND, |: OR + parameter REVERSE = 0 // 0: LO->HI, 1: HI->LO +) ( + input wire [N-1:0] data_in, + output wire [N-1:0] data_out +); + localparam LOGN = `CLOG2(N); + +`IGNORE_UNOPTFLAT_BEGIN + wire [LOGN:0][N-1:0] t; +`IGNORE_UNOPTFLAT_END + + // reverses bits + if (REVERSE != 0) begin : g_data_in_reverse + assign t[0] = data_in; + end else begin : g_data_in_no_reverse + assign t[0] = {<<{data_in}}; + end + + // optimize for the common case of small and-scans + if ((N == 2) && (OP == "&")) begin : g_scan_n2_and + assign t[LOGN] = {t[0][1], &t[0][1:0]}; + end else if ((N == 3) && (OP == "&")) begin : g_scan_n3_and + assign t[LOGN] = {t[0][2], &t[0][2:1], &t[0][2:0]}; + end else if ((N == 4) && (OP == "&")) begin : g_scan_n4_and + assign t[LOGN] = {t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0]}; + end else begin : g_scan + // general case + wire [N-1:0] fill; + for (genvar i = 0; i < LOGN; ++i) begin : g_i + wire [N-1:0] shifted = N'({fill, t[i]} >> (1< 1) begin : g_switch + reg req_out_r [N]; + reg rsp_out_r; + + always @(posedge clk) begin + if (reset) begin + for (integer i = 0; i < N; ++i) begin + req_out_r[i] <= 0; + end + rsp_out_r <= 0; + end else begin + for (integer i = 0; i < N; ++i) begin + req_out_r[i] <= req_in; + end + rsp_out_r <= 0; + for (integer i = 0; i < N; ++i) begin + if (rsp_in[i]) + rsp_out_r <= 1; + end + end + end + + for (genvar i = 0; i < N; ++i) begin : g_req_out + assign req_out[i] = req_out_r[i]; + end + + assign rsp_out = rsp_out_r; + + end else begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign req_out[0] = req_in; + assign rsp_out = rsp_in[0]; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_scope_tap.sv b/designs/src/vortex/rtl/libs/VX_scope_tap.sv new file mode 100644 index 0000000..86e117c --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_scope_tap.sv @@ -0,0 +1,418 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_scope_tap #( + parameter SCOPE_ID = 0, // scope identifier + parameter SCOPE_IDW = 8, // scope identifier width + parameter XTRIGGERW = 0, // changed trigger signals width + parameter HTRIGGERW = 0, // high trigger signals width + parameter PROBEW = 1, // probe signal width + parameter DEPTH = 256, // trace buffer depth + parameter IDLE_CTRW = 32, // idle time between triggers counter width + parameter TX_DATAW = 64 // transfer data width +) ( + input wire clk, + input wire reset, + input wire start, + input wire stop, + input wire [`UP(XTRIGGERW)-1:0] xtriggers, + input wire [`UP(HTRIGGERW)-1:0] htriggers, + input wire [PROBEW-1:0] probes, + input wire bus_in, + output wire bus_out +); + localparam HAS_TRIGGERS = XTRIGGERW != 0 || HTRIGGERW != 0; + localparam CTR_WIDTH = 64; + localparam SER_CTR_WIDTH = `LOG2UP(TX_DATAW); + localparam DATAW = PROBEW + XTRIGGERW + HTRIGGERW; + localparam ADDRW = `CLOG2(DEPTH); + localparam SIZEW = `CLOG2(DEPTH+1); + localparam MAX_IDLE_CTR = (2 ** IDLE_CTRW) - 1; + localparam DATA_BLOCKS = `CDIV(DATAW, TX_DATAW); + localparam BLOCK_IDX_WIDTH = `LOG2UP(DATA_BLOCKS); + + localparam CTRL_STATE_IDLE = 2'd0; + localparam CTRL_STATE_RECV = 2'd1; + localparam CTRL_STATE_CMD = 2'd2; + localparam CTRL_STATE_SEND = 2'd3; + localparam CTRL_STATE_BITS = 2; + + localparam TAP_STATE_IDLE = 2'd0; + localparam TAP_STATE_RUN = 2'd1; + localparam TAP_STATE_DONE = 2'd2; + localparam TAP_STATE_BITS = 2; + + localparam CMD_GET_WIDTH = 3'd0; + localparam CMD_GET_COUNT = 3'd1; + localparam CMD_GET_START = 3'd2; + localparam CMD_GET_DATA = 3'd3; + localparam CMD_SET_START = 3'd4; + localparam CMD_SET_STOP = 3'd5; + localparam CMD_SET_DEPTH = 3'd6; + localparam CMD_TYPE_BITS = 3; + + localparam SEND_TYPE_WIDTH = 2'd0; + localparam SEND_TYPE_COUNT = 2'd1; + localparam SEND_TYPE_START = 2'd2; + localparam SEND_TYPE_DATA = 2'd3; + localparam SEND_TYPE_BITS = 2; + + `STATIC_ASSERT ((IDLE_CTRW <= TX_DATAW), ("invalid parameter")) + `STATIC_ASSERT(`IS_POW2(DEPTH), ("depth must be a power of 2!")) + + reg [TAP_STATE_BITS-1:0] tap_state; + reg [CTRL_STATE_BITS-1:0] ctrl_state; + reg [SEND_TYPE_BITS-1:0] send_type; + + reg [CTR_WIDTH-1:0] timestamp, start_time; + reg [CTR_WIDTH-1:0] start_delay, stop_delay; + reg [`UP(XTRIGGERW)-1:0] prev_xtrig; + reg [`UP(HTRIGGERW)-1:0] prev_htrig; + reg [IDLE_CTRW-1:0] delta; + reg cmd_start, cmd_stop; + reg dflush; + + reg [SIZEW-1:0] waddr, waddr_end; + wire [DATAW-1:0] data_in; + + wire [DATAW-1:0] data_value; + wire [IDLE_CTRW-1:0] delta_value; + reg [ADDRW-1:0] raddr; + + // + // trace capture + // + + wire do_capture; + + wire write_en = (tap_state == TAP_STATE_RUN) && do_capture; + + if (HAS_TRIGGERS) begin : g_delta_store + if (XTRIGGERW != 0 && HTRIGGERW != 0) begin : g_data_in_pxh + assign data_in = {probes, xtriggers, htriggers}; + end else if (XTRIGGERW != 0) begin : g_data_in_px + assign data_in = {probes, xtriggers}; + end else begin : g_data_in_ph + assign data_in = {probes, htriggers}; + end + assign do_capture = dflush || (xtriggers != prev_xtrig) || (htriggers != prev_htrig) || (htriggers != '0); + VX_dp_ram #( + .DATAW (IDLE_CTRW), + .SIZE (DEPTH), + .OUT_REG (1), + .RDW_MODE ("R") + ) delta_store ( + .clk (clk), + .reset (reset), + .read (1'b1), + .wren (1'b1), + .write (write_en), + .waddr (waddr[ADDRW-1:0]), + .wdata (delta), + .raddr (raddr), + .rdata (delta_value) + ); + end else begin : g_no_delta_store + assign data_in = probes; + assign delta_value = '0; + assign do_capture = 1; + end + + VX_dp_ram #( + .DATAW (DATAW), + .SIZE (DEPTH), + .OUT_REG (1), + .RDW_MODE ("R") + ) data_store ( + .clk (clk), + .reset (reset), + .read (1'b1), + .wren (1'b1), + .write (write_en), + .waddr (waddr[ADDRW-1:0]), + .wdata (data_in), + .raddr (raddr), + .rdata (data_value) + ); + + always @(posedge clk) begin + if (reset) begin + timestamp <= '0; + end else begin + timestamp <= timestamp + CTR_WIDTH'(1); + end + end + + always @(posedge clk) begin + if (reset) begin + tap_state <= TAP_STATE_IDLE; + delta <= '0; + dflush <= 0; + prev_xtrig <= '0; + prev_htrig <= '0; + waddr <= '0; + end else begin + case (tap_state) + TAP_STATE_IDLE: begin + if (start || cmd_start) begin + dflush <= 1; + tap_state <= TAP_STATE_RUN; + start_time <= timestamp; + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%t: scope_tap%0d: recording start - time=%0d\n", $time, SCOPE_ID, timestamp)) + `endif + end + end + TAP_STATE_RUN: begin + dflush <= 0; + if (!(stop || cmd_stop) && (waddr < waddr_end)) begin + if (do_capture) begin + waddr <= waddr + SIZEW'(1); + end + if (HAS_TRIGGERS) begin + if (do_capture) begin + delta <= '0; + end else begin + delta <= delta + IDLE_CTRW'(1); + dflush <= (delta == IDLE_CTRW'(MAX_IDLE_CTR-1)); + end + prev_xtrig <= xtriggers; + prev_htrig <= htriggers; + end + end else begin + tap_state <= TAP_STATE_DONE; + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%t: scope_tap%0d: recording stop - waddr=(%0d, %0d)\n", $time, SCOPE_ID, waddr, waddr_end)) + `endif + end + end + default:; + endcase + end + end + + // + // trace controller + // + + reg bus_out_r; + + reg [TX_DATAW-1:0] ser_buf_in; + wire [TX_DATAW-1:0] ser_buf_in_n = {ser_buf_in[TX_DATAW-2:0], bus_in}; + `UNUSED_VAR (ser_buf_in) + + wire [DATA_BLOCKS-1:0][TX_DATAW-1:0] data_blocks; + logic [BLOCK_IDX_WIDTH-1:0] data_block_idx; + reg [SER_CTR_WIDTH-1:0] ser_tx_ctr; + reg is_read_data; + reg is_get_data; + + wire [CMD_TYPE_BITS-1:0] cmd_type = ser_buf_in[CMD_TYPE_BITS-1:0]; + wire [SCOPE_IDW-1:0] cmd_scope_id = ser_buf_in_n[CMD_TYPE_BITS +: SCOPE_IDW]; + wire [TX_DATAW-CMD_TYPE_BITS-SCOPE_IDW-1:0] cmd_data = ser_buf_in[TX_DATAW-1:CMD_TYPE_BITS+SCOPE_IDW]; + + for (genvar i = 0; i < DATA_BLOCKS; ++i) begin : g_data_blocks + for (genvar j = 0; j < TX_DATAW; ++j) begin : g_j + localparam k = i * TX_DATAW + j; + if (k < DATAW) begin : g_valid + assign data_blocks[i][j] = data_value[k]; + end else begin : g_padding + assign data_blocks[i][j] = '0; + end + end + end + + if (DATA_BLOCKS > 1) begin : g_data_block_idx + always @(posedge clk) begin + if (reset) begin + data_block_idx <= '0; + end else if ((ctrl_state == CTRL_STATE_SEND) + && (send_type == SEND_TYPE_DATA) + && (ser_tx_ctr == 0) + && is_read_data) begin + if (data_block_idx < BLOCK_IDX_WIDTH'(DATA_BLOCKS-1)) begin + data_block_idx <= data_block_idx + BLOCK_IDX_WIDTH'(1); + end else begin + data_block_idx <= '0; + end + end + end + end else begin : g_data_block_idx_0 + assign data_block_idx = 0; + end + + always @(posedge clk) begin + if (reset) begin + ctrl_state <= CTRL_STATE_IDLE; + send_type <= SEND_TYPE_BITS'(SEND_TYPE_WIDTH); + waddr_end <= SIZEW'(DEPTH); + cmd_start <= 0; + cmd_stop <= 0; + start_delay <= '0; + stop_delay <= '0; + bus_out_r <= 0; + raddr <= '0; + is_read_data<= 0; + ser_tx_ctr <= '0; + is_get_data <= 0; + end else begin + bus_out_r <= 0; + is_get_data <= 0; + + if (start_delay != 0) begin + start_delay <= start_delay - CTR_WIDTH'(1); + end + + if (stop_delay != 0) begin + stop_delay <= stop_delay - CTR_WIDTH'(1); + end + + cmd_start <= (start_delay == CTR_WIDTH'(1)); + cmd_stop <= (stop_delay == CTR_WIDTH'(1)); + + case (ctrl_state) + CTRL_STATE_IDLE: begin + if (bus_in) begin + ser_tx_ctr <= SER_CTR_WIDTH'(TX_DATAW-1); + ctrl_state <= CTRL_STATE_RECV; + end + end + CTRL_STATE_RECV: begin + ser_tx_ctr <= ser_tx_ctr - SER_CTR_WIDTH'(1); + ser_buf_in <= ser_buf_in_n; + if (ser_tx_ctr == 0) begin + // check if command is for this scope + ctrl_state <= (cmd_scope_id == SCOPE_ID) ? CTRL_STATE_CMD : CTRL_STATE_IDLE; + end + end + CTRL_STATE_CMD: begin + ctrl_state <= CTRL_STATE_IDLE; + case (cmd_type) + CMD_SET_START: begin + start_delay <= CTR_WIDTH'(cmd_data); + cmd_start <= (cmd_data == 0); + end + CMD_SET_STOP: begin + stop_delay <= CTR_WIDTH'(cmd_data); + cmd_stop <= (cmd_data == 0); + end + CMD_SET_DEPTH: begin + waddr_end <= SIZEW'(cmd_data); + end + CMD_GET_WIDTH, + CMD_GET_START, + CMD_GET_COUNT, + CMD_GET_DATA: begin + send_type <= SEND_TYPE_BITS'(cmd_type); + ser_tx_ctr <= SER_CTR_WIDTH'(TX_DATAW-1); + ctrl_state <= CTRL_STATE_SEND; + bus_out_r <= 1; + end + default:; + endcase + `ifdef DBG_TRACE_SCOPE + `TRACE(2, ("%t: scope_tap%0d: CMD: type=%0d\n", $time, SCOPE_ID, cmd_type)) + `endif + end + CTRL_STATE_SEND: begin + case (send_type) + SEND_TYPE_WIDTH: begin + bus_out_r <= 1'(DATAW >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%t: scope_tap%0d: SEND width=%0d\n", $time, SCOPE_ID, DATAW)) + end + `endif + end + SEND_TYPE_COUNT: begin + bus_out_r <= 1'(waddr >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%t: scope_tap%0d: SEND count=%0d\n", $time, SCOPE_ID, waddr)) + end + `endif + end + SEND_TYPE_START: begin + bus_out_r <= 1'(start_time >> ser_tx_ctr); + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + `TRACE(2, ("%t: scope_tap%0d: SEND start=%0d\n", $time, SCOPE_ID, start_time)) + end + `endif + end + SEND_TYPE_DATA: begin + is_get_data <= 1; + if (ser_tx_ctr == 0) begin + if (is_read_data) begin + if (data_block_idx == BLOCK_IDX_WIDTH'(DATA_BLOCKS-1)) begin + raddr <= raddr + ADDRW'(1); + is_read_data <= 0; // switch to delta mode + end + end else begin + is_read_data <= 1; // switch to data mode + end + end + `ifdef DBG_TRACE_SCOPE + if (ser_tx_ctr == 0) begin + if (is_read_data) begin + `TRACE(2, ("%t: scope_tap%0d: SEND data=0x%0h\n", $time, SCOPE_ID, get_data)) + end else begin + `TRACE(2, ("%t: scope_tap%0d: SEND delta=0x%0h\n", $time, SCOPE_ID, get_data)) + end + end + `endif + end + default:; + endcase + ser_tx_ctr <= ser_tx_ctr - SER_CTR_WIDTH'(1); + if (ser_tx_ctr == 0) begin + ctrl_state <= CTRL_STATE_IDLE; + end + end + default:; + endcase + end + end + + wire [BLOCK_IDX_WIDTH-1:0] data_block_idx_r; + wire [SER_CTR_WIDTH-1:0] ser_tx_ctr_r; + wire is_read_data_r; + + VX_pipe_register #( + .DATAW (1 + SER_CTR_WIDTH + BLOCK_IDX_WIDTH) + ) data_sel_buf ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in ({is_read_data, ser_tx_ctr, data_block_idx}), + .data_out ({is_read_data_r, ser_tx_ctr_r, data_block_idx_r}) + ); + + wire [TX_DATAW-1:0] get_data = is_read_data_r ? data_blocks[data_block_idx_r] : TX_DATAW'(delta_value); + wire bus_out_w = is_get_data ? get_data[ser_tx_ctr_r] : bus_out_r; + + VX_pipe_register #( + .DATAW (1) + ) buf_out ( + .clk (clk), + .reset (reset), + .enable (1'b1), + .data_in (bus_out_w), + .data_out (bus_out) + ); + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_serial_div.sv b/designs/src/vortex/rtl/libs/VX_serial_div.sv new file mode 100644 index 0000000..593be2d --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_serial_div.sv @@ -0,0 +1,101 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_serial_div #( + parameter WIDTHN = 32, + parameter WIDTHD = 32, + parameter WIDTHQ = 32, + parameter WIDTHR = 32, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + input wire strobe, + output wire busy, + + input wire is_signed, + input wire [LANES-1:0][WIDTHN-1:0] numer, + input wire [LANES-1:0][WIDTHD-1:0] denom, + + output wire [LANES-1:0][WIDTHQ-1:0] quotient, + output wire [LANES-1:0][WIDTHR-1:0] remainder +); + localparam MIN_ND = (WIDTHN < WIDTHD) ? WIDTHN : WIDTHD; + localparam CNTRW = `CLOG2(WIDTHN); + + reg [LANES-1:0][WIDTHN + MIN_ND:0] working; + reg [LANES-1:0][WIDTHD-1:0] denom_r; + + wire [LANES-1:0][WIDTHN-1:0] numer_qual; + wire [LANES-1:0][WIDTHD-1:0] denom_qual; + wire [LANES-1:0][WIDTHD:0] sub_result; + + reg [LANES-1:0] inv_quot, inv_rem; + + reg [CNTRW-1:0] cntr; + reg busy_r; + + for (genvar i = 0; i < LANES; ++i) begin : g_setup + wire negate_numer = is_signed && numer[i][WIDTHN-1]; + wire negate_denom = is_signed && denom[i][WIDTHD-1]; + assign numer_qual[i] = negate_numer ? -$signed(numer[i]) : numer[i]; + assign denom_qual[i] = negate_denom ? -$signed(denom[i]) : denom[i]; + assign sub_result[i] = working[i][WIDTHN + MIN_ND : WIDTHN] - denom_r[i]; + end + + always @(posedge clk) begin + if (reset) begin + busy_r <= 0; + end else begin + if (strobe) begin + busy_r <= 1; + end + if (busy && cntr == 0) begin + busy_r <= 0; + end + end + cntr <= cntr - CNTRW'(1); + if (strobe) begin + cntr <= CNTRW'(WIDTHN-1); + end + end + + for (genvar i = 0; i < LANES; ++i) begin : g_div + always @(posedge clk) begin + if (strobe) begin + working[i] <= {{WIDTHD{1'b0}}, numer_qual[i], 1'b0}; + denom_r[i] <= denom_qual[i]; + inv_quot[i] <= (denom[i] != 0) && is_signed && (numer[i][31] ^ denom[i][31]); + inv_rem[i] <= is_signed && numer[i][31]; + end else if (busy_r) begin + working[i] <= sub_result[i][WIDTHD] ? {working[i][WIDTHN+MIN_ND-1:0], 1'b0} : + {sub_result[i][WIDTHD-1:0], working[i][WIDTHN-1:0], 1'b1}; + end + end + end + + for (genvar i = 0; i < LANES; ++i) begin : g_output + wire [WIDTHQ-1:0] q = working[i][WIDTHQ-1:0]; + wire [WIDTHR-1:0] r = working[i][WIDTHN+WIDTHR:WIDTHN+1]; + assign quotient[i] = inv_quot[i] ? -$signed(q) : q; + assign remainder[i] = inv_rem[i] ? -$signed(r) : r; + end + + assign busy = busy_r; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_serial_mul.sv b/designs/src/vortex/rtl/libs/VX_serial_mul.sv new file mode 100644 index 0000000..d847b71 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_serial_mul.sv @@ -0,0 +1,107 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +// Iterative integer multiplier +// An adaptation of ZipCPU algorithm for a multi-lane elastic architecture. +// https://zipcpu.com/zipcpu/2021/07/03/slowmpy.html + +`TRACING_OFF +module VX_serial_mul #( + parameter A_WIDTH = 32, + parameter B_WIDTH = A_WIDTH, + parameter R_WIDTH = A_WIDTH + B_WIDTH, + parameter SIGNED = 0, + parameter LANES = 1 +) ( + input wire clk, + input wire reset, + + input wire strobe, + output wire busy, + + input wire [LANES-1:0][A_WIDTH-1:0] dataa, + input wire [LANES-1:0][B_WIDTH-1:0] datab, + output wire [LANES-1:0][R_WIDTH-1:0] result +); + localparam X_WIDTH = SIGNED ? `MAX(A_WIDTH, B_WIDTH) : A_WIDTH; + localparam Y_WIDTH = SIGNED ? `MAX(A_WIDTH, B_WIDTH) : B_WIDTH; + localparam P_WIDTH = X_WIDTH + Y_WIDTH; + + localparam CNTRW = `CLOG2(X_WIDTH); + + reg [LANES-1:0][X_WIDTH-1:0] a; + reg [LANES-1:0][Y_WIDTH-1:0] b; + reg [LANES-1:0][P_WIDTH-1:0] p; + + reg [CNTRW-1:0] cntr; + reg busy_r; + + always @(posedge clk) begin + if (reset) begin + busy_r <= 0; + end else begin + if (strobe) begin + busy_r <= 1; + end + if (busy_r && cntr == 0) begin + busy_r <= 0; + end + end + cntr <= cntr - CNTRW'(1); + if (strobe) begin + cntr <= CNTRW'(X_WIDTH-1); + end + end + + for (genvar i = 0; i < LANES; ++i) begin : g_mul + wire [X_WIDTH-1:0] axb = b[i][0] ? a[i] : '0; + + always @(posedge clk) begin + if (strobe) begin + if (SIGNED) begin + a[i] <= X_WIDTH'($signed(dataa[i])); + b[i] <= Y_WIDTH'($signed(datab[i])); + end else begin + a[i] <= dataa[i]; + b[i] <= datab[i]; + end + p[i] <= 0; + end else if (busy_r) begin + b[i] <= (b[i] >> 1); + p[i][Y_WIDTH-2:0] <= p[i][Y_WIDTH-1:1]; + if (SIGNED) begin + if (cntr == 0) begin + p[i][P_WIDTH-1:Y_WIDTH-1] <= {1'b0, p[i][P_WIDTH-1:Y_WIDTH]} + {1'b0, axb[X_WIDTH-1], ~axb[X_WIDTH-2:0]}; + end else begin + p[i][P_WIDTH-1:Y_WIDTH-1] <= {1'b0, p[i][P_WIDTH-1:Y_WIDTH]} + {1'b0, ~axb[X_WIDTH-1], axb[X_WIDTH-2:0]}; + end + end else begin + p[i][P_WIDTH-1:Y_WIDTH-1] <= {1'b0, p[i][P_WIDTH-1:Y_WIDTH]} + ((b[i][0]) ? {1'b0, a[i]} : 0); + end + end + end + + if (SIGNED) begin : g_signed + assign result[i] = R_WIDTH'(p[i][P_WIDTH-1:0] + {1'b1, {(X_WIDTH-2){1'b0}}, 1'b1, {(Y_WIDTH){1'b0}}}); + end else begin : g_unsigned + assign result[i] = R_WIDTH'(p[i]); + end + end + `UNUSED_VAR (p) + + assign busy = busy_r; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_shift_register.sv b/designs/src/vortex/rtl/libs/VX_shift_register.sv new file mode 100644 index 0000000..027616b --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_shift_register.sv @@ -0,0 +1,89 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_shift_register #( + parameter DATAW = 1, + parameter RESETW = 0, + parameter DEPTH = 1, + parameter NUM_TAPS = 1, + parameter TAP_START = (DEPTH-1), + parameter TAP_STRIDE = 1, + parameter [`UP(RESETW)-1:0] INIT_VALUE = {`UP(RESETW){1'b0}} +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [DATAW-1:0] data_in, + output wire [NUM_TAPS-1:0][DATAW-1:0] data_out +); + `STATIC_ASSERT (RESETW <= DATAW, ("invalid parameter")); + if (DEPTH == 0) begin : g_passthru + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (enable) + `UNUSED_PARAM (RESETW) + `UNUSED_PARAM (INIT_VALUE) + `UNUSED_PARAM (NUM_TAPS) + `UNUSED_PARAM (TAP_START) + `UNUSED_PARAM (TAP_STRIDE) + assign data_out = data_in; + end else begin : g_shift + logic [DEPTH-1:0][DATAW-1:0] pipe; + + if (RESETW == DATAW) begin : g_full_reset + for (genvar i = 0; i < DEPTH; ++i) begin : g_stages + always_ff @(posedge clk) begin + if (reset) begin + pipe[i] <= INIT_VALUE; + end else if (enable) begin + pipe[i] <= (i == 0) ? data_in : pipe[i-1]; + end + end + end + end else if (RESETW != 0) begin : g_partial_reset + for (genvar i = 0; i < DEPTH; ++i) begin : g_stages + always_ff @(posedge clk) begin + if (reset) begin + pipe[i][DATAW-1 : DATAW-RESETW] <= INIT_VALUE; + end else if (enable) begin + pipe[i][DATAW-1 : DATAW-RESETW] <= (i == 0) ? data_in[DATAW-1 : DATAW-RESETW] : pipe[i-1][DATAW-1 : DATAW-RESETW]; + end + end + always_ff @(posedge clk) begin + if (enable) begin + pipe[i][DATAW-RESETW-1 : 0] <= (i == 0) ? data_in[DATAW-RESETW-1 : 0] : pipe[i-1][DATAW-RESETW-1 : 0]; + end + end + end + end else begin : g_no_reset + `UNUSED_VAR (reset) + `UNUSED_PARAM (INIT_VALUE) + for (genvar i = 0; i < DEPTH; ++i) begin : g_stages + always_ff @(posedge clk) begin + if (enable) begin + pipe[i] <= (i == 0) ? data_in : pipe[i-1]; + end + end + end + end + + for (genvar i = 0; i < NUM_TAPS; ++i) begin : g_taps + assign data_out[i] = pipe[i * TAP_STRIDE + TAP_START]; + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_skid_buffer.sv b/designs/src/vortex/rtl/libs/VX_skid_buffer.sv new file mode 100644 index 0000000..b77cce2 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_skid_buffer.sv @@ -0,0 +1,77 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_skid_buffer #( + parameter DATAW = 32, + parameter PASSTHRU = 0, + parameter HALF_BW = 0, + parameter OUT_REG = 0 +) ( + input wire clk, + input wire reset, + + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (PASSTHRU != 0) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign valid_out = valid_in; + assign data_out = data_in; + assign ready_in = ready_out; + + end else if (HALF_BW != 0) begin : g_half_bw + + VX_toggle_buffer #( + .DATAW (DATAW) + ) toggle_buffer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .ready_in (ready_in), + .valid_out (valid_out), + .data_out (data_out), + .ready_out (ready_out) + ); + + end else begin : g_full_bw + + VX_stream_buffer #( + .DATAW (DATAW), + .OUT_REG (OUT_REG) + ) stream_buffer ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .ready_in (ready_in), + .valid_out (valid_out), + .data_out (data_out), + .ready_out (ready_out) + ); + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_sp_ram.sv b/designs/src/vortex/rtl/libs/VX_sp_ram.sv new file mode 100644 index 0000000..7fa6ea6 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_sp_ram.sv @@ -0,0 +1,473 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// Modifications: +// - Added FakeRAM conditionals (for memories exceeding 2000 bits) + +`include "VX_platform.vh" + +`define RAM_INITIALIZATION \ + if (INIT_ENABLE != 0) begin : g_init \ + if (INIT_FILE != "") begin : g_file \ + initial $readmemh(INIT_FILE, ram); \ + end else begin : g_value \ + initial begin \ + for (integer i = 0; i < SIZE; ++i) begin : g_i \ + ram[i] = INIT_VALUE; \ + end \ + end \ + end \ + end + +`ifdef SIMULATION + `define RAM_RESET_BLOCK if (RESET_RAM && reset) begin \ + for (integer i = 0; i < SIZE; ++i) begin \ + ram[i] <= DATAW'(INIT_VALUE); \ + end \ + end else +`else + `define RAM_RESET_BLOCK +`endif + +`define RAM_WRITE_ALL `RAM_RESET_BLOCK \ + if (write) begin \ + ram[addr] <= wdata; \ + end + +`ifdef QUARTUS + `define RAM_ARRAY_WREN reg [WRENW-1:0][WSELW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[addr][i] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`else + `define RAM_ARRAY_WREN reg [DATAW-1:0] ram [0:SIZE-1]; + `define RAM_WRITE_WREN `RAM_RESET_BLOCK \ + if (write) begin \ + for (integer i = 0; i < WRENW; ++i) begin \ + if (wren[i]) begin \ + ram[addr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW]; \ + end \ + end \ + end +`endif + +`TRACING_OFF +module VX_sp_ram #( + parameter DATAW = 1, + parameter SIZE = 1, + parameter WRENW = 1, + parameter OUT_REG = 0, + parameter LUTRAM = 0, + parameter `STRING RDW_MODE = "W", // W: write-first, R: read-first, N: no-change + parameter RADDR_REG = 0, // read address registered hint + parameter RADDR_RESET = 0, // read address has reset + parameter RDW_ASSERT = 0, + parameter RESET_RAM = 0, + parameter INIT_ENABLE = 0, + parameter INIT_FILE = "", + parameter [DATAW-1:0] INIT_VALUE = 0, + parameter ADDRW = `LOG2UP(SIZE) +) ( + input wire clk, + input wire reset, + input wire read, + input wire write, + input wire [WRENW-1:0] wren, + input wire [ADDRW-1:0] addr, + input wire [DATAW-1:0] wdata, + output wire [DATAW-1:0] rdata +); + localparam WSELW = DATAW / WRENW; + `UNUSED_PARAM (LUTRAM) + `UNUSED_PARAM (RADDR_REG) + `UNUSED_PARAM (RADDR_RESET) + + `STATIC_ASSERT(!(WRENW * WSELW != DATAW), ("invalid parameter")) + `STATIC_ASSERT((RDW_MODE == "R" || RDW_MODE == "W" || RDW_MODE == "N"), ("invalid parameter")) + `UNUSED_PARAM (RDW_ASSERT) + +`ifdef SYNTHESIS + localparam FORCE_BRAM = !LUTRAM && `FORCE_BRAM(SIZE, DATAW); + if (DATAW == 32 && SIZE == 1024) begin : g_fakeram + fakeram_32x1024_1rw fakeram_32x1024 ( + .rw0_clk (clk), + .rw0_ce_in (read || write), + .rw0_we_in (write), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_wmask_in(wren), + .rw0_rd_out (rdata) + ); + end else if (DATAW == 512 && SIZE == 64) begin : g_fakeram + fakeram_512x64_1rw fakeram_512x64 ( + .rw0_clk (clk), + .rw0_ce_in (read || write), + .rw0_we_in (write), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_wmask_in(wren), + .rw0_rd_out (rdata) + ); + end else if (DATAW == 128 && SIZE == 256) begin : g_fakeram + fakeram_128x256_1rw fakeram_128x256 ( + .rw0_clk (clk), + .rw0_ce_in (read || write), + .rw0_we_in (write), + .rw0_addr_in (addr), + .rw0_wd_in (wdata), + .rw0_wmask_in(wren), + .rw0_rd_out (rdata) + ); + end else if (OUT_REG) begin : g_sync + if (FORCE_BRAM) begin : g_bram + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] addr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + addr_r <= addr; + end + end + assign rdata = ram[addr_r]; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + if (write) begin + rdata_r <= wdata; + end else begin + rdata_r <= ram[addr]; + end + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "N") begin : g_no_change + if (WRENW != 1) begin : g_wren + `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [ADDRW-1:0] addr_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + addr_r <= addr; + end + end + assign rdata = ram[addr_r]; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + if (write) begin + rdata_r <= wdata; + end else begin + rdata_r <= ram[addr]; + end + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "R") begin : g_read_first + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end else if (RDW_MODE == "N") begin : g_no_change + if (WRENW != 1) begin : g_wren + `RAM_ARRAY_WREN + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_WREN + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else begin : g_no_wren + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + `RAM_WRITE_ALL + else if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end + end + end else begin : g_async + `UNUSED_VAR (read) + if (FORCE_BRAM) begin : g_bram + `ifdef ASYNC_BRAM_PATCH + VX_async_ram_patch #( + .DATAW (DATAW), + .SIZE (SIZE), + .WRENW (WRENW), + .DUAL_PORT (0), + .FORCE_BRAM (FORCE_BRAM), + .RADDR_REG (RADDR_REG), + .RADDR_RESET(RADDR_RESET), + .WRITE_FIRST(RDW_MODE == "W"), + .INIT_ENABLE(INIT_ENABLE), + .INIT_FILE (INIT_FILE), + .INIT_VALUE (INIT_VALUE) + ) async_ram_patch ( + .clk (clk), + .reset (reset), + .read (read), + .write (write), + .wren (wren), + .waddr (addr), + .wdata (wdata), + .raddr (addr), + .rdata (rdata) + ); + `else + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK `USE_BLOCK_BRAM reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end + `endif + end else begin : g_auto + if (RDW_MODE == "W") begin : g_write_first + if (WRENW != 1) begin : g_wren + `RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end else begin : g_read_first + if (WRENW != 1) begin : g_wren + `NO_RW_RAM_CHECK `RAM_ARRAY_WREN + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_WREN + end + assign rdata = ram[addr]; + end else begin : g_no_wren + `NO_RW_RAM_CHECK reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + always @(posedge clk) begin + `RAM_WRITE_ALL + end + assign rdata = ram[addr]; + end + end + end + end +`else + // simulation + reg [DATAW-1:0] ram [0:SIZE-1]; + `RAM_INITIALIZATION + + if (WRENW != 1) begin : g_wren + reg [DATAW-1:0] wdata_n; + always @(*) begin + wdata_n = ram[addr]; + for (integer i = 0; i < WRENW; ++i) begin + if (wren[i]) begin + wdata_n[i * WSELW +: WSELW] = wdata[i * WSELW +: WSELW]; + end + end + end + always @(posedge clk) begin + `RAM_RESET_BLOCK + if (write) begin + ram[addr] <= wdata_n; + end + end + end else begin : g_no_wren + `UNUSED_VAR (wren) + always @(posedge clk) begin + `RAM_WRITE_ALL + end + end + + if (OUT_REG) begin : g_sync + if (RDW_MODE == "W") begin : g_write_first + reg [ADDRW-1:0] addr_r; + always @(posedge clk) begin + if (read) begin + addr_r <= addr; + end + end + assign rdata = ram[addr_r]; + end else if (RDW_MODE == "R") begin : g_read_first + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (read) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end else if (RDW_MODE == "N") begin : g_no_change + reg [DATAW-1:0] rdata_r; + always @(posedge clk) begin + if (read && ~write) begin + rdata_r <= ram[addr]; + end + end + assign rdata = rdata_r; + end + end else begin : g_async + `UNUSED_VAR (read) + if (RDW_MODE == "W") begin : g_write_first + assign rdata = ram[addr]; + end else begin : g_read_first + reg [DATAW-1:0] prev_data; + reg [ADDRW-1:0] prev_waddr; + reg prev_write; + always @(posedge clk) begin + if (reset) begin + prev_write <= 0; + prev_data <= '0; + prev_waddr <= '0; + end else begin + prev_write <= write; + prev_data <= ram[addr]; + prev_waddr <= addr; + end + end + assign rdata = (prev_write && (prev_waddr == addr)) ? prev_data : ram[addr]; + if (RDW_ASSERT) begin : g_rw_asert + `RUNTIME_ASSERT(~read || (rdata == ram[addr]), ("%t: read after write hazard", $time)) + end + end + end +`endif + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_arb.sv b/designs/src/vortex/rtl/libs/VX_stream_arb.sv new file mode 100644 index 0000000..a99e5fb --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_arb.sv @@ -0,0 +1,372 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_arb #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATAW = 1, + parameter STICKY = 0, // hold the grant until its request is deasserted + parameter `STRING ARBITER = "R", + parameter MAX_FANOUT = `MAX_FANOUT, + parameter OUT_BUF = 0, + parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? `CDIV(NUM_INPUTS, NUM_OUTPUTS) : `CDIV(NUM_OUTPUTS, NUM_INPUTS), + parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS), + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS), + parameter NUM_REQS_W = `UP(LOG_NUM_REQS) +) ( + input wire clk, + input wire reset, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + input wire [NUM_OUTPUTS-1:0] ready_out, + + output wire [SEL_COUNT-1:0][NUM_REQS_W-1:0] sel_out +); + if (NUM_INPUTS > NUM_OUTPUTS) begin : g_input_select + + // #Inputs > #Outputs + + if (MAX_FANOUT != 0 && (NUM_REQS > (MAX_FANOUT + MAX_FANOUT /2))) begin : g_fanout + + localparam NUM_SLICES = `CDIV(NUM_REQS, MAX_FANOUT); + localparam LOG_NUM_REQS2 = `CLOG2(MAX_FANOUT); + localparam LOG_NUM_REQS3 = `CLOG2(NUM_SLICES); + localparam DATAW2 = DATAW + LOG_NUM_REQS2; + + wire [NUM_SLICES-1:0][NUM_OUTPUTS-1:0] valid_tmp; + wire [NUM_SLICES-1:0][NUM_OUTPUTS-1:0][DATAW2-1:0] data_tmp; + wire [NUM_SLICES-1:0][NUM_OUTPUTS-1:0] ready_tmp; + + for (genvar s = 0; s < NUM_SLICES; ++s) begin : g_slice_arbs + + localparam SLICE_STRIDE= MAX_FANOUT * NUM_OUTPUTS; + localparam SLICE_BEGIN = s * SLICE_STRIDE; + localparam SLICE_END = `MIN(SLICE_BEGIN + SLICE_STRIDE, NUM_INPUTS); + localparam SLICE_SIZE = SLICE_END - SLICE_BEGIN; + + wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_tmp_u; + wire [NUM_OUTPUTS-1:0][LOG_NUM_REQS2-1:0] sel_tmp_u; + + VX_stream_arb #( + .NUM_INPUTS (SLICE_SIZE), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (DATAW), + .ARBITER (ARBITER), + .STICKY (STICKY), + .MAX_FANOUT (MAX_FANOUT), + .OUT_BUF (3) + ) fanout_slice_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_in[SLICE_END-1: SLICE_BEGIN]), + .data_in (data_in[SLICE_END-1: SLICE_BEGIN]), + .ready_in (ready_in[SLICE_END-1: SLICE_BEGIN]), + .valid_out (valid_tmp[s]), + .data_out (data_tmp_u), + .ready_out (ready_tmp[s]), + .sel_out (sel_tmp_u) + ); + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_data_tmp + assign data_tmp[s][o] = {data_tmp_u[o], sel_tmp_u[o]}; + end + end + + wire [NUM_OUTPUTS-1:0][DATAW2-1:0] data_out_u; + wire [NUM_OUTPUTS-1:0][LOG_NUM_REQS3-1:0] sel_out_u; + + VX_stream_arb #( + .NUM_INPUTS (NUM_SLICES * NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (DATAW2), + .ARBITER (ARBITER), + .STICKY (STICKY), + .MAX_FANOUT (MAX_FANOUT), + .OUT_BUF (OUT_BUF) + ) fanout_join_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_tmp), + .ready_in (ready_tmp), + .data_in (data_tmp), + .data_out (data_out_u), + .sel_out (sel_out_u), + .valid_out (valid_out), + .ready_out (ready_out) + ); + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_data_out + assign sel_out[o] = {sel_out_u[o], data_out_u[o][LOG_NUM_REQS2-1:0]}; + assign data_out[o] = data_out_u[o][DATAW2-1:LOG_NUM_REQS2]; + end + + end else begin : g_arbiter + + wire [NUM_REQS-1:0] arb_requests; + wire arb_valid; + wire [NUM_REQS_W-1:0] arb_index; + wire [NUM_REQS-1:0] arb_onehot; + wire arb_ready; + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_requests + wire [NUM_OUTPUTS-1:0] requests; + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_o + localparam i = r * NUM_OUTPUTS + o; + assign requests[o] = valid_in[i]; + end + assign arb_requests[r] = (| requests); + end + + VX_generic_arbiter #( + .NUM_REQS (NUM_REQS), + .TYPE (ARBITER), + .STICKY (STICKY) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (arb_requests), + .grant_valid (arb_valid), + .grant_index (arb_index), + .grant_onehot (arb_onehot), + .grant_ready (arb_ready) + ); + + wire [NUM_OUTPUTS-1:0] valid_out_w; + wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_w; + wire [NUM_OUTPUTS-1:0] ready_out_w; + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_data_out_w + wire [NUM_REQS-1:0] valid_in_w; + wire [NUM_REQS-1:0][DATAW-1:0] data_in_w; + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_r + localparam i = r * NUM_OUTPUTS + o; + if (r < NUM_INPUTS) begin : g_valid + assign valid_in_w[r] = valid_in[i]; + assign data_in_w[r] = data_in[i]; + end else begin : g_padding + assign valid_in_w[r] = 0; + assign data_in_w[r] = '0; + end + end + assign valid_out_w[o] = (NUM_OUTPUTS == 1) ? arb_valid : (| (valid_in_w & arb_onehot)); + assign data_out_w[o] = data_in_w[arb_index]; + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_ready_in + localparam o = i % NUM_OUTPUTS; + localparam r = i / NUM_OUTPUTS; + assign ready_in[i] = ready_out_w[o] && arb_onehot[r]; + end + + assign arb_ready = (| ready_out_w); + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + VX_elastic_buffer #( + .DATAW (LOG_NUM_REQS + DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)), + .LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_w[o]), + .ready_in (ready_out_w[o]), + .data_in ({arb_index, data_out_w[o]}), + .data_out ({sel_out[o], data_out[o]}), + .valid_out (valid_out[o]), + .ready_out (ready_out[o]) + ); + end + end + + end else if (NUM_INPUTS < NUM_OUTPUTS) begin : g_output_select + + // #Inputs < #Outputs + + if (MAX_FANOUT != 0 && (NUM_REQS > (MAX_FANOUT + MAX_FANOUT /2))) begin : g_fanout + + localparam NUM_SLICES = `CDIV(NUM_REQS, MAX_FANOUT); + localparam LOG_NUM_REQS2 = `CLOG2(MAX_FANOUT); + localparam LOG_NUM_REQS3 = `CLOG2(NUM_SLICES); + + wire [NUM_SLICES-1:0][NUM_INPUTS-1:0] valid_tmp; + wire [NUM_SLICES-1:0][NUM_INPUTS-1:0][DATAW-1:0] data_tmp; + wire [NUM_SLICES-1:0][NUM_INPUTS-1:0] ready_tmp; + wire [NUM_INPUTS-1:0][LOG_NUM_REQS3-1:0] sel_tmp; + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_SLICES * NUM_INPUTS), + .DATAW (DATAW), + .ARBITER (ARBITER), + .STICKY (STICKY), + .MAX_FANOUT (MAX_FANOUT), + .OUT_BUF (3) + ) fanout_fork_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in (data_in), + .data_out (data_tmp), + .valid_out (valid_tmp), + .ready_out (ready_tmp), + .sel_out (sel_tmp) + ); + + wire [NUM_SLICES-1:0][NUM_INPUTS-1:0][LOG_NUM_REQS2-1:0] sel_out_w; + + for (genvar s = 0; s < NUM_SLICES; ++s) begin : g_slice_arbs + + localparam SLICE_STRIDE= MAX_FANOUT * NUM_INPUTS; + localparam SLICE_BEGIN = s * SLICE_STRIDE; + localparam SLICE_END = `MIN(SLICE_BEGIN + SLICE_STRIDE, NUM_OUTPUTS); + localparam SLICE_SIZE = SLICE_END - SLICE_BEGIN; + + wire [NUM_INPUTS-1:0][LOG_NUM_REQS2-1:0] sel_out_u; + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (SLICE_SIZE), + .DATAW (DATAW), + .ARBITER (ARBITER), + .STICKY (STICKY), + .MAX_FANOUT (MAX_FANOUT), + .OUT_BUF (OUT_BUF) + ) fanout_slice_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_tmp[s]), + .ready_in (ready_tmp[s]), + .data_in (data_tmp[s]), + .data_out (data_out[SLICE_END-1: SLICE_BEGIN]), + .valid_out (valid_out[SLICE_END-1: SLICE_BEGIN]), + .ready_out (ready_out[SLICE_END-1: SLICE_BEGIN]), + .sel_out (sel_out_w[s]) + ); + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_sel_out + assign sel_out[i] = {sel_tmp[i], sel_out_w[sel_tmp[i]][i]}; + end + + end else begin : g_arbiter + + wire [NUM_REQS-1:0] arb_requests; + wire arb_valid; + wire [NUM_REQS_W-1:0] arb_index; + wire [NUM_REQS-1:0] arb_onehot; + wire arb_ready; + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_requests + wire [NUM_INPUTS-1:0] requests; + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_i + localparam o = r * NUM_INPUTS + i; + assign requests[i] = ready_out[o]; + end + assign arb_requests[r] = (| requests); + end + + VX_generic_arbiter #( + .NUM_REQS (NUM_REQS), + .TYPE (ARBITER), + .STICKY (STICKY) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (arb_requests), + .grant_valid (arb_valid), + .grant_index (arb_index), + .grant_onehot (arb_onehot), + .grant_ready (arb_ready) + ); + + wire [NUM_OUTPUTS-1:0] valid_out_w; + wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_w; + wire [NUM_OUTPUTS-1:0] ready_out_w; + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_data_out_w + localparam i = o % NUM_INPUTS; + localparam r = o / NUM_INPUTS; + assign valid_out_w[o] = valid_in[i] && arb_onehot[r]; + assign data_out_w[o] = data_in[i]; + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_ready_in + wire [NUM_REQS-1:0] ready_out_s; + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_r + localparam o = r * NUM_INPUTS + i; + assign ready_out_s[r] = ready_out_w[o]; + end + assign ready_in[i] = (NUM_INPUTS == 1) ? arb_valid : (| (ready_out_s & arb_onehot)); + end + + assign arb_ready = (| valid_in); + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)), + .LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_w[o]), + .ready_in (ready_out_w[o]), + .data_in (data_out_w[o]), + .data_out (data_out[o]), + .valid_out (valid_out[o]), + .ready_out (ready_out[o]) + ); + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_sel_out + assign sel_out[i] = arb_index; + end + end + + end else begin : g_passthru + + // #Inputs == #Outputs + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)), + .LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_in[o]), + .ready_in (ready_in[o]), + .data_in (data_in[o]), + .data_out (data_out[o]), + .valid_out (valid_out[o]), + .ready_out (ready_out[o]) + ); + assign sel_out[o] = NUM_REQS_W'(0); + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_buffer.sv b/designs/src/vortex/rtl/libs/VX_stream_buffer.sv new file mode 100644 index 0000000..ea4467c --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_buffer.sv @@ -0,0 +1,112 @@ +// Copyright 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A stream elastic buffer_r operates at full-bandwidth where fire_in and fire_out can happen simultaneously +// It has the following benefits: +// + full-bandwidth throughput +// + ready_in and ready_out are decoupled +// + data_out can be fully registered +// It has the following limitations: +// - requires two registers for storage + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_buffer #( + parameter DATAW = 1, + parameter OUT_REG = 0, + parameter PASSTHRU = 0 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (PASSTHRU != 0) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + assign ready_in = ready_out; + assign valid_out = valid_in; + assign data_out = data_in; + + end else begin : g_buffer + + reg [DATAW-1:0] data_out_r, buffer_r; + reg valid_out_r, valid_in_r; + + wire fire_in = valid_in && ready_in; + wire flow_out = ready_out || ~valid_out; + + always @(posedge clk) begin + if (reset) begin + valid_in_r <= 1'b1; + end else if (valid_in || flow_out) begin + valid_in_r <= flow_out; + end + end + + always @(posedge clk) begin + if (reset) begin + valid_out_r <= 1'b0; + end else if (flow_out) begin + valid_out_r <= valid_in || ~valid_in_r; + end + end + + if (OUT_REG != 0) begin : g_out_reg + + always @(posedge clk) begin + if (fire_in) begin + buffer_r <= data_in; + end + end + + always @(posedge clk) begin + if (flow_out) begin + data_out_r <= valid_in_r ? data_in : buffer_r; + end + end + + assign data_out = data_out_r; + + end else begin : g_no_out_reg + + always @(posedge clk) begin + if (fire_in) begin + data_out_r <= data_in; + end + end + + always @(posedge clk) begin + if (fire_in) begin + buffer_r <= data_out_r; + end + end + + assign data_out = valid_in_r ? data_out_r : buffer_r; + + end + + assign valid_out = valid_out_r; + assign ready_in = valid_in_r; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_omega.sv b/designs/src/vortex/rtl/libs/VX_stream_omega.sv new file mode 100644 index 0000000..fd0d84d --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_omega.sv @@ -0,0 +1,215 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`TRACING_OFF +module VX_stream_omega #( + parameter NUM_INPUTS = 4, + parameter NUM_OUTPUTS = 4, + parameter RADIX = 2, + parameter DATAW = 4, + parameter ARBITER = "R", + parameter OUT_BUF = 0, + parameter MAX_FANOUT = `MAX_FANOUT, + parameter PERF_CTR_BITS = 32, + parameter IN_WIDTH = `LOG2UP(NUM_INPUTS), + parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS) +) ( + input wire clk, + input wire reset, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + input wire [NUM_INPUTS-1:0][OUT_WIDTH-1:0] sel_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + output wire [NUM_OUTPUTS-1:0][IN_WIDTH-1:0] sel_out, + input wire [NUM_OUTPUTS-1:0] ready_out, + + output wire [PERF_CTR_BITS-1:0] collisions +); + `STATIC_ASSERT (`IS_POW2(RADIX), ("inavlid parameters")) + + // If network size smaller than radix, simply use a crossbar. + if (NUM_INPUTS <= RADIX && NUM_OUTPUTS <= RADIX) begin : g_fallback + VX_stream_xbar #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (DATAW), + .ARBITER (ARBITER), + .OUT_BUF (OUT_BUF), + .MAX_FANOUT (MAX_FANOUT), + .PERF_CTR_BITS (PERF_CTR_BITS) + ) xbar_switch ( + .clk, + .reset, + .valid_in, + .data_in, + .sel_in, + .ready_in, + .valid_out, + .data_out, + .sel_out, + .ready_out, + .collisions + ); + end else begin : g_omega + localparam RADIX_LG = `LOG2UP(RADIX); + localparam N_INPUTS_M = `MAX(NUM_INPUTS, NUM_OUTPUTS); + localparam N_INPUTS_LG = `CDIV(`CLOG2(N_INPUTS_M), RADIX_LG); + localparam N_INPUTS = RADIX ** N_INPUTS_LG; + localparam NUM_STAGES = `LOG2UP(N_INPUTS) / RADIX_LG; + localparam NUM_SWITCHES = N_INPUTS / RADIX; + + typedef struct packed { + logic [N_INPUTS_LG-1:0] sel_in; + logic [DATAW-1:0] data; + logic [IN_WIDTH-1:0] sel_out; + } omega_t; + + // Wires for internal connections between stages + wire [NUM_STAGES-1:0][NUM_SWITCHES-1:0][RADIX-1:0] switch_valid_in, switch_valid_out; + omega_t [NUM_STAGES-1:0][NUM_SWITCHES-1:0][RADIX-1:0] switch_data_in, switch_data_out; + wire [NUM_STAGES-1:0][NUM_SWITCHES-1:0][RADIX-1:0][RADIX_LG-1:0] switch_sel_in; + wire [NUM_STAGES-1:0][NUM_SWITCHES-1:0][RADIX-1:0] switch_ready_in, switch_ready_out; + + // Connect inputs to first stage + for (genvar i = 0; i < N_INPUTS; ++i) begin : g_tie_inputs + localparam DST_IDX = ((i << 1) | (i >> (N_INPUTS_LG-1))) & (N_INPUTS-1); + localparam switch = DST_IDX / RADIX; + localparam port = DST_IDX % RADIX; + if (i < NUM_INPUTS) begin : g_valid + assign switch_valid_in[0][switch][port] = valid_in[i]; + assign switch_data_in[0][switch][port] = '{ + sel_in: N_INPUTS_LG'(sel_in[i]), + data: data_in[i], + sel_out: IN_WIDTH'(i) + }; + assign ready_in[i] = switch_ready_in[0][switch][port]; + end else begin : g_padding + assign switch_valid_in[0][switch][port] = 0; + assign switch_data_in[0][switch][port] = 'x; + `UNUSED_VAR (switch_ready_in[0][switch][port]) + end + end + + // Connect switch sel_in + for (genvar stage = 0; stage < NUM_STAGES; ++stage) begin : g_sel_in + for (genvar switch = 0; switch < NUM_SWITCHES; ++switch) begin : g_switches + for (genvar port = 0; port < RADIX; ++port) begin : g_ports + assign switch_sel_in[stage][switch][port] = switch_data_in[stage][switch][port].sel_in[(NUM_STAGES-1-stage) * RADIX_LG +: RADIX_LG]; + end + end + end + + // Connect internal stages + for (genvar stage = 0; stage < NUM_STAGES-1; ++stage) begin : g_stages + for (genvar switch = 0; switch < NUM_SWITCHES; ++switch) begin : g_switches + for (genvar port = 0; port < RADIX; port++) begin : g_ports + localparam lane = switch * RADIX + port; + localparam dst_lane = ((lane << 1) | (lane >> (N_INPUTS_LG-1))) & (N_INPUTS-1); + localparam dst_switch = dst_lane / RADIX; + localparam dst_port = dst_lane % RADIX; + assign switch_valid_in[stage+1][dst_switch][dst_port] = switch_valid_out[stage][switch][port]; + assign switch_data_in[stage+1][dst_switch][dst_port] = switch_data_out[stage][switch][port]; + assign switch_ready_out[stage][switch][port] = switch_ready_in[stage+1][dst_switch][dst_port]; + end + end + end + + // Connect network switches + for (genvar switch = 0; switch < NUM_SWITCHES; ++switch) begin : g_switches + for (genvar stage = 0; stage < NUM_STAGES; ++stage) begin : g_stages + VX_stream_xbar #( + .NUM_INPUTS (RADIX), + .NUM_OUTPUTS (RADIX), + .DATAW ($bits(omega_t)), + .ARBITER (ARBITER), + .OUT_BUF (OUT_BUF), + .MAX_FANOUT (MAX_FANOUT), + .PERF_CTR_BITS(PERF_CTR_BITS) + ) xbar_switch ( + .clk (clk), + .reset (reset), + .valid_in (switch_valid_in[stage][switch]), + .data_in (switch_data_in[stage][switch]), + .sel_in (switch_sel_in[stage][switch]), + .ready_in (switch_ready_in[stage][switch]), + .valid_out (switch_valid_out[stage][switch]), + .data_out (switch_data_out[stage][switch]), + `UNUSED_PIN (sel_out), + .ready_out (switch_ready_out[stage][switch]), + `UNUSED_PIN (collisions) + ); + end + end + + // Connect outputs to last stage + for (genvar i = 0; i < N_INPUTS; ++i) begin : g_tie_outputs + localparam switch = i / RADIX; + localparam port = i % RADIX; + if (i < NUM_OUTPUTS) begin : g_valid + assign valid_out[i] = switch_valid_out[NUM_STAGES-1][switch][port]; + assign data_out[i] = switch_data_out[NUM_STAGES-1][switch][port].data; + assign sel_out[i] = switch_data_out[NUM_STAGES-1][switch][port].sel_out; + assign switch_ready_out[NUM_STAGES-1][switch][port] = ready_out[i]; + end else begin : g_padding + `UNUSED_VAR (switch_valid_out[NUM_STAGES-1][switch][port]) + `UNUSED_VAR (switch_data_out[NUM_STAGES-1][switch][port]) + assign switch_ready_out[NUM_STAGES-1][switch][port] = 0; + end + end + + // compute inputs collision + // we have a collision when there exists a valid transfer with multiple input candicates + // we count the unique duplicates each cycle. + + reg [NUM_STAGES-1:0][NUM_SWITCHES-1:0][RADIX-1:0] per_cycle_collision, per_cycle_collision_r; + wire [`CLOG2(NUM_STAGES*NUM_SWITCHES*RADIX+1)-1:0] collision_count; + reg [PERF_CTR_BITS-1:0] collisions_r; + + always @(*) begin + per_cycle_collision = 0; + for (integer stage = 0; stage < NUM_STAGES; ++stage) begin + for (integer switch = 0; switch < NUM_SWITCHES; ++switch) begin + for (integer port_a = 0; port_a < RADIX; ++port_a) begin + for (integer port_b = port_a + 1; port_b < RADIX; ++port_b) begin + per_cycle_collision[stage][switch][port_a] |= switch_valid_in[stage][switch][port_a] + && switch_valid_in[stage][switch][port_b] + && (switch_sel_in[stage][switch][port_a] == switch_sel_in[stage][switch][port_b]) + && (switch_ready_in[stage][switch][port_a] | switch_ready_in[stage][switch][port_b]); + end + end + end + end + end + + `BUFFER(per_cycle_collision_r, per_cycle_collision); + `POP_COUNT(collision_count, per_cycle_collision_r); + + always @(posedge clk) begin + if (reset) begin + collisions_r <= '0; + end else begin + collisions_r <= collisions_r + PERF_CTR_BITS'(collision_count); + end + end + + assign collisions = collisions_r; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_pack.sv b/designs/src/vortex/rtl/libs/VX_stream_pack.sv new file mode 100644 index 0000000..944b120 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_pack.sv @@ -0,0 +1,104 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_pack #( + parameter NUM_REQS = 1, + parameter DATA_WIDTH = 1, + parameter TAG_WIDTH = 1, + parameter TAG_SEL_BITS = 0, + parameter `STRING ARBITER = "P", + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + // input + input wire [NUM_REQS-1:0] valid_in, + input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] data_in, + input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag_in, + output wire [NUM_REQS-1:0] ready_in, + + // output + output wire valid_out, + output wire [NUM_REQS-1:0] mask_out, + output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] data_out, + output wire [TAG_WIDTH-1:0] tag_out, + input wire ready_out +); + if (NUM_REQS > 1) begin : g_pack + + localparam LOG_NUM_REQS = `CLOG2(NUM_REQS); + + wire [LOG_NUM_REQS-1:0] grant_index; + wire grant_valid; + wire grant_ready; + + VX_generic_arbiter #( + .NUM_REQS (NUM_REQS), + .TYPE (ARBITER) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (valid_in), + .grant_valid (grant_valid), + .grant_index (grant_index), + `UNUSED_PIN (grant_onehot), + .grant_ready (grant_ready) + ); + + wire [TAG_WIDTH-1:0] tag_sel = tag_in[grant_index]; + + wire [NUM_REQS-1:0] tag_matches; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_tag_matches + assign tag_matches[i] = (tag_in[i][TAG_SEL_BITS-1:0] == tag_sel[TAG_SEL_BITS-1:0]); + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_ready_in + assign ready_in[i] = grant_ready & tag_matches[i]; + end + + wire [NUM_REQS-1:0] mask_sel = valid_in & tag_matches; + + VX_elastic_buffer #( + .DATAW (NUM_REQS + TAG_WIDTH + (NUM_REQS * DATA_WIDTH)), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (grant_valid), + .data_in ({mask_sel, tag_sel, data_in}), + .ready_in (grant_ready), + .valid_out (valid_out), + .data_out ({mask_out, tag_out, data_out}), + .ready_out (ready_out) + ); + + end else begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + assign valid_out = valid_in; + assign mask_out = 1'b1; + assign data_out = data_in; + assign tag_out = tag_in; + assign ready_in = ready_out; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_switch.sv b/designs/src/vortex/rtl/libs/VX_stream_switch.sv new file mode 100644 index 0000000..fb263fd --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_switch.sv @@ -0,0 +1,128 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_switch #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATAW = 1, + parameter OUT_BUF = 0, + parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? `CDIV(NUM_INPUTS, NUM_OUTPUTS) : `CDIV(NUM_OUTPUTS, NUM_INPUTS), + parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS), + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS) +) ( + input wire clk, + input wire reset, + + input wire [SEL_COUNT-1:0][`UP(LOG_NUM_REQS)-1:0] sel_in, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + input wire [NUM_OUTPUTS-1:0] ready_out +); + logic [NUM_OUTPUTS-1:0] valid_out_w; + logic [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_w; + logic [NUM_OUTPUTS-1:0] ready_out_w; + + if (NUM_INPUTS > NUM_OUTPUTS) begin : g_input_select + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + + logic [NUM_REQS-1:0] valid_in_w; + logic [NUM_REQS-1:0][DATAW-1:0] data_in_w; + logic [NUM_REQS-1:0] ready_in_w; + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_r + localparam i = r * NUM_OUTPUTS + o; + if (i < NUM_INPUTS) begin : g_valid + assign valid_in_w[r] = valid_in[i]; + assign data_in_w[r] = data_in[i]; + assign ready_in[i] = ready_in_w[r]; + end else begin : g_padding + assign valid_in_w[r] = 0; + assign data_in_w[r] = '0; + `UNUSED_VAR (ready_in_w[r]) + end + end + + assign valid_out_w[o] = valid_in_w[sel_in[o]]; + assign data_out_w[o] = data_in_w[sel_in[o]]; + + always @(*) begin + ready_in_w = '0; + for (integer o = 0; o < NUM_OUTPUTS; ++o) begin + ready_in_w[sel_in[o]] = ready_out_w[o]; + end + end + end + + end else if (NUM_OUTPUTS > NUM_INPUTS) begin : g_output_select + + // Inputs < Outputs + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_out_buf + + logic [NUM_REQS-1:0] ready_out_s; + + for (genvar r = 0; r < NUM_REQS; ++r) begin : g_r + localparam o = r * NUM_INPUTS + i; + if (o < NUM_OUTPUTS) begin : g_valid + assign valid_out_w[o] = valid_in[i] && (sel_in[i] == LOG_NUM_REQS'(r)); + assign data_out_w[o] = data_in[i]; + assign ready_out_s[r] = ready_out_w[o]; + end else begin : g_padding + assign ready_out_s[r] = '0; + end + end + + assign ready_in[i] = ready_out_s[sel_in[i]]; + end + + end else begin : g_passthru + + // #Inputs == #Outputs + + `UNUSED_VAR (sel_in) + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf + assign valid_out_w[i] = valid_in[i]; + assign data_out_w[i] = data_in[i]; + assign ready_in[i] = ready_out_w[i]; + end + end + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_w[o]), + .data_in (data_out_w[o]), + .ready_in (ready_out_w[o]), + .valid_out (valid_out[o]), + .data_out (data_out[o]), + .ready_out (ready_out[o]) + ); + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_unpack.sv b/designs/src/vortex/rtl/libs/VX_stream_unpack.sv new file mode 100644 index 0000000..b0cca96 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_unpack.sv @@ -0,0 +1,89 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_unpack #( + parameter NUM_REQS = 1, + parameter DATA_WIDTH = 1, + parameter TAG_WIDTH = 1, + parameter OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + // input + input wire valid_in, + input wire [NUM_REQS-1:0] mask_in, + input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] data_in, + input wire [TAG_WIDTH-1:0] tag_in, + output wire ready_in, + + // output + output wire [NUM_REQS-1:0] valid_out, + output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] data_out, + output wire [NUM_REQS-1:0][TAG_WIDTH-1:0] tag_out, + input wire [NUM_REQS-1:0] ready_out +); + if (NUM_REQS > 1) begin : g_unpack + + reg [NUM_REQS-1:0] rem_mask_r; + wire [NUM_REQS-1:0] ready_out_w; + + wire [NUM_REQS-1:0] rem_mask_n = rem_mask_r & ~ready_out_w; + wire sent_all = ~(| (mask_in & rem_mask_n)); + + always @(posedge clk) begin + if (reset) begin + rem_mask_r <= '1; + end else begin + if (valid_in) begin + rem_mask_r <= sent_all ? '1 : rem_mask_n; + end + end + end + + assign ready_in = sent_all; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_outbuf + VX_elastic_buffer #( + .DATAW (DATA_WIDTH + TAG_WIDTH), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_in && mask_in[i] && rem_mask_r[i]), + .ready_in (ready_out_w[i]), + .data_in ({data_in[i], tag_in}), + .data_out ({data_out[i], tag_out[i]}), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + + end else begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + `UNUSED_VAR (mask_in) + assign valid_out = valid_in; + assign data_out = data_in; + assign tag_out = tag_in; + assign ready_in = ready_out; + + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_xbar.sv b/designs/src/vortex/rtl/libs/VX_stream_xbar.sv new file mode 100644 index 0000000..34972b8 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_xbar.sv @@ -0,0 +1,234 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`TRACING_OFF +module VX_stream_xbar #( + parameter NUM_INPUTS = 4, + parameter NUM_OUTPUTS = 4, + parameter DATAW = 4, + parameter ARBITER = "R", + parameter OUT_BUF = 0, + parameter MAX_FANOUT = `MAX_FANOUT, + parameter PERF_CTR_BITS = `CLOG2(NUM_INPUTS+1), + parameter IN_WIDTH = `LOG2UP(NUM_INPUTS), + parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS) +) ( + input wire clk, + input wire reset, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + input wire [NUM_INPUTS-1:0][OUT_WIDTH-1:0] sel_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + output wire [NUM_OUTPUTS-1:0][IN_WIDTH-1:0] sel_out, + input wire [NUM_OUTPUTS-1:0] ready_out, + + output wire [PERF_CTR_BITS-1:0] collisions +); + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + if (NUM_INPUTS != 1) begin : g_multi_inputs + + if (NUM_OUTPUTS != 1) begin : g_multiple_outputs + + // (#inputs > 1) and (#outputs > 1) + + wire [NUM_INPUTS-1:0][NUM_OUTPUTS-1:0] per_output_valid_in; + wire [NUM_OUTPUTS-1:0][NUM_INPUTS-1:0] per_output_valid_in_w; + + wire [NUM_OUTPUTS-1:0][NUM_INPUTS-1:0] per_output_ready_in; + wire [NUM_INPUTS-1:0][NUM_OUTPUTS-1:0] per_output_ready_in_w; + + VX_transpose #( + .N (NUM_OUTPUTS), + .M (NUM_INPUTS) + ) rdy_in_transpose ( + .data_in (per_output_ready_in), + .data_out (per_output_ready_in_w) + ); + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_ready_in + assign ready_in[i] = | per_output_ready_in_w[i]; + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_sel_in_demux + VX_demux #( + .DATAW (1), + .N (NUM_OUTPUTS) + ) sel_in_demux ( + .sel_in (sel_in[i]), + .data_in (valid_in[i]), + .data_out (per_output_valid_in[i]) + ); + end + + VX_transpose #( + .N (NUM_INPUTS), + .M (NUM_OUTPUTS) + ) val_in_transpose ( + .data_in (per_output_valid_in), + .data_out (per_output_valid_in_w) + ); + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_xbar_arbs + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (1), + .DATAW (DATAW), + .ARBITER (ARBITER), + .MAX_FANOUT (MAX_FANOUT), + .OUT_BUF (OUT_BUF) + ) xbar_arb ( + .clk (clk), + .reset (reset), + .valid_in (per_output_valid_in_w[i]), + .data_in (data_in), + .ready_in (per_output_ready_in[i]), + .valid_out (valid_out[i]), + .data_out (data_out[i]), + .sel_out (sel_out[i]), + .ready_out (ready_out[i]) + ); + end + + end else begin : g_one_output + + // (#inputs >= 1) and (#outputs == 1) + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (1), + .DATAW (DATAW), + .ARBITER (ARBITER), + .MAX_FANOUT (MAX_FANOUT), + .OUT_BUF (OUT_BUF) + ) xbar_arb ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .data_in (data_in), + .ready_in (ready_in), + .valid_out (valid_out), + .data_out (data_out), + .sel_out (sel_out), + .ready_out (ready_out) + ); + + `UNUSED_VAR (sel_in) + end + + end else if (NUM_OUTPUTS != 1) begin : g_single_input + + // (#inputs == 1) and (#outputs > 1) + + wire [NUM_OUTPUTS-1:0] valid_out_w, ready_out_w; + wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_w; + + VX_demux #( + .DATAW (1), + .N (NUM_OUTPUTS) + ) sel_in_demux ( + .sel_in (sel_in[0]), + .data_in (valid_in[0]), + .data_out (valid_out_w) + ); + + assign ready_in[0] = ready_out_w[sel_in[0]]; + assign data_out_w = {NUM_OUTPUTS{data_in[0]}}; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_out_buf + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)), + .LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_w[i]), + .ready_in (ready_out_w[i]), + .data_in (data_out_w[i]), + .data_out (data_out[i]), + .valid_out (valid_out[i]), + .ready_out (ready_out[i]) + ); + end + + assign sel_out = 0; + + end else begin : g_passthru + + // (#inputs == 1) and (#outputs == 1) + + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)), + .LUTRAM (`TO_OUT_BUF_LUTRAM(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_in), + .ready_in (ready_in), + .data_in (data_in), + .data_out (data_out), + .valid_out (valid_out), + .ready_out (ready_out) + ); + + `UNUSED_VAR (sel_in) + assign sel_out = 0; + + end + + // compute inputs collision + // we have a collision when there exists a valid transfer with multiple input candicates + // we count the unique duplicates each cycle. + + reg [NUM_INPUTS-1:0] per_cycle_collision, per_cycle_collision_r; + wire [`CLOG2(NUM_INPUTS+1)-1:0] collision_count; + reg [PERF_CTR_BITS-1:0] collisions_r; + + always @(*) begin + per_cycle_collision = '0; + for (integer i = 0; i < NUM_INPUTS; ++i) begin + for (integer j = i + 1; j < NUM_INPUTS; ++j) begin + per_cycle_collision[i] |= valid_in[i] + && valid_in[j] + && (sel_in[i] == sel_in[j]) + && (ready_in[i] | ready_in[j]); + end + end + end + + `BUFFER(per_cycle_collision_r, per_cycle_collision); + `POP_COUNT(collision_count, per_cycle_collision_r); + + always @(posedge clk) begin + if (reset) begin + collisions_r <= '0; + end else begin + collisions_r <= collisions_r + PERF_CTR_BITS'(collision_count); + end + end + + assign collisions = collisions_r; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_stream_xpoint.sv b/designs/src/vortex/rtl/libs/VX_stream_xpoint.sv new file mode 100644 index 0000000..a4a6fd1 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_stream_xpoint.sv @@ -0,0 +1,95 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_stream_xpoint #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATAW = 1, + parameter OUT_DRIVEN = 0, + parameter OUT_BUF = 0, + parameter SEL_SRC = OUT_DRIVEN ? NUM_OUTPUTS : NUM_INPUTS, + parameter SEL_DST = OUT_DRIVEN ? NUM_INPUTS : NUM_OUTPUTS +) ( + input wire clk, + input wire reset, + + input wire [SEL_SRC-1:0][`LOG2UP(SEL_DST)-1:0] sel_in, + + input wire [NUM_INPUTS-1:0] valid_in, + input wire [NUM_INPUTS-1:0][DATAW-1:0] data_in, + output wire [NUM_INPUTS-1:0] ready_in, + + output wire [NUM_OUTPUTS-1:0] valid_out, + output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out, + input wire [NUM_OUTPUTS-1:0] ready_out +); + logic [NUM_OUTPUTS-1:0] valid_out_w; + logic [NUM_OUTPUTS-1:0][DATAW-1:0] data_out_w; + logic [NUM_OUTPUTS-1:0] ready_out_w; + + if (OUT_DRIVEN) begin : g_output_driven + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + assign valid_out_w[o] = valid_in[sel_in[o]]; + assign data_out_w[o] = data_in[sel_in[o]]; + end + + logic [NUM_INPUTS-1:0] ready_in_w; + always @(*) begin + ready_in_w = '0; + for (integer o = 0; o < NUM_OUTPUTS; ++o) begin + ready_in_w[sel_in[o]] = ready_out_w[o]; + end + end + assign ready_in = ready_in_w; + + end else begin: g_input_driven + + always @(*) begin + valid_out_w = '0; + data_out_w = 'x; + for (integer i = 0; i < NUM_INPUTS; ++i) begin + if (valid_in[i]) begin + valid_out_w[sel_in[i]] = 1; + data_out_w[sel_in[i]] = data_in[i]; + end + end + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_ready_in + assign ready_in[i] = ready_out_w[sel_in[i]]; + end + end + + for (genvar o = 0; o < NUM_OUTPUTS; ++o) begin : g_out_buf + VX_elastic_buffer #( + .DATAW (DATAW), + .SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)) + ) out_buf ( + .clk (clk), + .reset (reset), + .valid_in (valid_out_w[o]), + .data_in (data_out_w[o]), + .ready_in (ready_out_w[o]), + .valid_out (valid_out[o]), + .data_out (data_out[o]), + .ready_out (ready_out[o]) + ); + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_ticket_lock.sv b/designs/src/vortex/rtl/libs/VX_ticket_lock.sv new file mode 100644 index 0000000..c0b7782 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_ticket_lock.sv @@ -0,0 +1,66 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_ticket_lock #( + parameter N = 2, + parameter LOGN = `LOG2UP(N) +) ( + input wire clk, + input wire reset, + input wire aquire_en, + input wire release_en, + output wire [LOGN-1:0] acquire_id, + output wire [LOGN-1:0] release_id, + output wire full, + output wire empty +); + reg [LOGN-1:0] rd_ctr_r, wr_ctr_r; + + always @(posedge clk) begin + if (reset) begin + rd_ctr_r <= '0; + wr_ctr_r <= '0; + end else begin + if (aquire_en && !full) begin + wr_ctr_r <= wr_ctr_r + 1; + end + if (release_en && !empty) begin + rd_ctr_r <= rd_ctr_r + 1; + end + end + end + + VX_pending_size #( + .SIZE (N), + .INCRW (1), + .DECRW (1) + ) pending_size ( + .clk (clk), + .reset (reset), + .incr (aquire_en), + .decr (release_en), + .empty (empty), + .full (full), + `UNUSED_PIN (alm_empty), + `UNUSED_PIN (alm_full), + `UNUSED_PIN (size) + ); + + assign acquire_id = wr_ctr_r; + assign release_id = rd_ctr_r; + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_toggle_buffer.sv b/designs/src/vortex/rtl/libs/VX_toggle_buffer.sv new file mode 100644 index 0000000..9d6b427 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_toggle_buffer.sv @@ -0,0 +1,73 @@ +// Copyright 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A toggle elastic buffer operates at half-bandwidth where push can only trigger after pop +// It has the following benefits: +// + use only one register for storage +// + ready_in and ready_out are decoupled +// + data_out is fully registered +// It has the following limitations: +// - Half-bandwidth throughput + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_toggle_buffer #( + parameter DATAW = 1, + parameter PASSTHRU = 0 +) ( + input wire clk, + input wire reset, + input wire valid_in, + output wire ready_in, + input wire [DATAW-1:0] data_in, + output wire [DATAW-1:0] data_out, + input wire ready_out, + output wire valid_out +); + if (PASSTHRU != 0) begin : g_passthru + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + assign ready_in = ready_out; + assign valid_out = valid_in; + assign data_out = data_in; + + end else begin : g_buffer + + reg [DATAW-1:0] buffer; + reg has_data; + + always @(posedge clk) begin + if (reset) begin + has_data <= 0; + end else begin + if (~has_data) begin + has_data <= valid_in; + end else if (ready_out) begin + has_data <= 0; + end + end + if (~has_data) begin + buffer <= data_in; + end + end + + assign ready_in = ~has_data; + assign valid_out = has_data; + assign data_out = buffer; + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/libs/VX_transpose.sv b/designs/src/vortex/rtl/libs/VX_transpose.sv new file mode 100644 index 0000000..2fc0bd6 --- /dev/null +++ b/designs/src/vortex/rtl/libs/VX_transpose.sv @@ -0,0 +1,32 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_platform.vh" + +`TRACING_OFF +module VX_transpose #( + parameter DATAW = 1, + parameter N = 1, + parameter M = 1 +) ( + input wire [N-1:0][M-1:0][DATAW-1:0] data_in, + output wire [M-1:0][N-1:0][DATAW-1:0] data_out +); + for (genvar i = 0; i < N; ++i) begin : g_i + for (genvar j = 0; j < M; ++j) begin : g_j + assign data_out[j][i] = data_in[i][j]; + end + end + +endmodule +`TRACING_ON diff --git a/designs/src/vortex/rtl/mem/VX_gbar_arb.sv b/designs/src/vortex/rtl/mem/VX_gbar_arb.sv new file mode 100644 index 0000000..08e6dab --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_gbar_arb.sv @@ -0,0 +1,79 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_gbar_arb import VX_gpu_pkg::*; #( + parameter NUM_REQS = 1, + parameter OUT_BUF = 0, + parameter `STRING ARBITER = "R" +) ( + input wire clk, + input wire reset, + + VX_gbar_bus_if.slave bus_in_if [NUM_REQS], + VX_gbar_bus_if.master bus_out_if +); + + localparam REQ_DATAW = NB_WIDTH + NC_WIDTH + NC_WIDTH; + + // arbitrate request + + wire [NUM_REQS-1:0] req_valid_in; + wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_REQS-1:0] req_ready_in; + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_data_in + assign req_valid_in[i] = bus_in_if[i].req_valid; + assign req_data_in[i] = bus_in_if[i].req_data; + assign bus_in_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS (1), + .DATAW (REQ_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (OUT_BUF) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (req_valid_in), + .ready_in (req_ready_in), + .data_in (req_data_in), + .data_out (bus_out_if.req_data), + .valid_out (bus_out_if.req_valid), + .ready_out (bus_out_if.req_ready), + `UNUSED_PIN (sel_out) + ); + + // broadcast response + + reg rsp_valid; + reg [NB_WIDTH-1:0] rsp_data; + + always @(posedge clk) begin + if (reset) begin + rsp_valid <= 0; + end else begin + rsp_valid <= bus_out_if.rsp_valid; + end + rsp_data <= bus_out_if.rsp_data; + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_bus_in_if + assign bus_in_if[i].rsp_valid = rsp_valid; + assign bus_in_if[i].rsp_data = rsp_data; + end + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_gbar_bus_if.sv b/designs/src/vortex/rtl/mem/VX_gbar_bus_if.sv new file mode 100644 index 0000000..744f430 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_gbar_bus_if.sv @@ -0,0 +1,53 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_gbar_bus_if import VX_gpu_pkg::*; (); + + typedef struct packed { + logic [NB_WIDTH-1:0] id; + logic [NC_WIDTH-1:0] size_m1; + logic [NC_WIDTH-1:0] core_id; + } req_data_t; + + typedef struct packed { + logic [NB_WIDTH-1:0] id; + } rsp_data_t; + + logic req_valid; + req_data_t req_data; + logic req_ready; + + logic rsp_valid; + rsp_data_t rsp_data; + + modport master ( + output req_valid, + output req_data, + input req_ready, + + input rsp_valid, + input rsp_data + ); + + modport slave ( + input req_valid, + input req_data, + output req_ready, + + output rsp_valid, + output rsp_data + ); + +endinterface diff --git a/designs/src/vortex/rtl/mem/VX_gbar_unit.sv b/designs/src/vortex/rtl/mem/VX_gbar_unit.sv new file mode 100644 index 0000000..abac792 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_gbar_unit.sv @@ -0,0 +1,72 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_gbar_unit import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + input wire clk, + input wire reset, + + VX_gbar_bus_if.slave gbar_bus_if +); + `UNUSED_SPARAM (INSTANCE_ID) + + reg [NB_WIDTH-1:0][`NUM_CORES-1:0] barrier_masks; + wire [`CLOG2(`NUM_CORES+1)-1:0] active_barrier_count; + wire [`NUM_CORES-1:0] curr_barrier_mask = barrier_masks[gbar_bus_if.req_data.id]; + + `POP_COUNT(active_barrier_count, curr_barrier_mask); + `UNUSED_VAR (active_barrier_count) + + reg rsp_valid; + reg [NB_WIDTH-1:0] rsp_bar_id; + + always @(posedge clk) begin + if (reset) begin + barrier_masks <= '0; + rsp_valid <= 0; + end else begin + if (rsp_valid) begin + rsp_valid <= 0; + end + if (gbar_bus_if.req_valid) begin + if (active_barrier_count[NC_WIDTH-1:0] == gbar_bus_if.req_data.size_m1) begin + barrier_masks[gbar_bus_if.req_data.id] <= '0; + rsp_bar_id <= gbar_bus_if.req_data.id; + rsp_valid <= 1; + end else begin + barrier_masks[gbar_bus_if.req_data.id][gbar_bus_if.req_data.core_id] <= 1; + end + end + end + end + + assign gbar_bus_if.rsp_valid = rsp_valid; + assign gbar_bus_if.rsp_data.id = rsp_bar_id; + assign gbar_bus_if.req_ready = 1; // global barrier unit is always ready (no dependencies) + +`ifdef DBG_TRACE_GBAR + always @(posedge clk) begin + if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin + `TRACE(2, ("%t: %s acquire: bar_id=%0d, size=%0d, core_id=%0d\n", + $time, INSTANCE_ID, gbar_bus_if.req_data.id, gbar_bus_if.req_data.size_m1, gbar_bus_if.req_data.core_id)) + end + if (gbar_bus_if.rsp_valid) begin + `TRACE(2, ("%t: %s release: bar_id=%0d\n", $time, INSTANCE_ID, gbar_bus_if.rsp_data.id)) + end + end +`endif + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_lmem_switch.sv b/designs/src/vortex/rtl/mem/VX_lmem_switch.sv new file mode 100644 index 0000000..c8a4ee6 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_lmem_switch.sv @@ -0,0 +1,117 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_lmem_switch import VX_gpu_pkg::*; #( + parameter GLOBAL_OUT_BUF = 0, + parameter LOCAL_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0, + parameter `STRING ARBITER = "R" +) ( + input wire clk, + input wire reset, + VX_lsu_mem_if.slave lsu_in_if, + VX_lsu_mem_if.master global_out_if, + VX_lsu_mem_if.master local_out_if +); + localparam REQ_DATAW = `NUM_LSU_LANES + 1 + `NUM_LSU_LANES * (LSU_WORD_SIZE + LSU_ADDR_WIDTH + MEM_FLAGS_WIDTH + LSU_WORD_SIZE * 8) + LSU_TAG_WIDTH; + localparam RSP_DATAW = `NUM_LSU_LANES + `NUM_LSU_LANES * (LSU_WORD_SIZE * 8) + LSU_TAG_WIDTH; + + wire [`NUM_LSU_LANES-1:0] is_addr_local_mask; + wire req_global_ready; + wire req_local_ready; + + for (genvar i = 0; i < `NUM_LSU_LANES; ++i) begin : g_is_addr_local_mask + assign is_addr_local_mask[i] = lsu_in_if.req_data.flags[i][MEM_REQ_FLAG_LOCAL]; + end + + wire is_addr_global = | (lsu_in_if.req_data.mask & ~is_addr_local_mask); + wire is_addr_local = | (lsu_in_if.req_data.mask & is_addr_local_mask); + + assign lsu_in_if.req_ready = (req_global_ready && is_addr_global) + || (req_local_ready && is_addr_local); + + VX_elastic_buffer #( + .DATAW (REQ_DATAW), + .SIZE (`TO_OUT_BUF_SIZE(GLOBAL_OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(GLOBAL_OUT_BUF)) + ) req_global_buf ( + .clk (clk), + .reset (reset), + .valid_in (lsu_in_if.req_valid && is_addr_global), + .data_in ({ + lsu_in_if.req_data.mask & ~is_addr_local_mask, + lsu_in_if.req_data.rw, + lsu_in_if.req_data.addr, + lsu_in_if.req_data.data, + lsu_in_if.req_data.byteen, + lsu_in_if.req_data.flags, + lsu_in_if.req_data.tag + }), + .ready_in (req_global_ready), + .valid_out (global_out_if.req_valid), + .data_out (global_out_if.req_data), + .ready_out (global_out_if.req_ready) + ); + + VX_elastic_buffer #( + .DATAW (REQ_DATAW), + .SIZE (`TO_OUT_BUF_SIZE(LOCAL_OUT_BUF)), + .OUT_REG (`TO_OUT_BUF_REG(LOCAL_OUT_BUF)) + ) req_local_buf ( + .clk (clk), + .reset (reset), + .valid_in (lsu_in_if.req_valid && is_addr_local), + .data_in ({ + lsu_in_if.req_data.mask & is_addr_local_mask, + lsu_in_if.req_data.rw, + lsu_in_if.req_data.addr, + lsu_in_if.req_data.data, + lsu_in_if.req_data.byteen, + lsu_in_if.req_data.flags, + lsu_in_if.req_data.tag + }), + .ready_in (req_local_ready), + .valid_out (local_out_if.req_valid), + .data_out (local_out_if.req_data), + .ready_out (local_out_if.req_ready) + ); + + VX_stream_arb #( + .NUM_INPUTS (2), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in ({ + local_out_if.rsp_valid, + global_out_if.rsp_valid + }), + .ready_in ({ + local_out_if.rsp_ready, + global_out_if.rsp_ready + }), + .data_in ({ + local_out_if.rsp_data, + global_out_if.rsp_data + }), + .data_out (lsu_in_if.rsp_data), + .valid_out (lsu_in_if.rsp_valid), + .ready_out (lsu_in_if.rsp_ready), + `UNUSED_PIN (sel_out) + ); + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_local_mem.sv b/designs/src/vortex/rtl/mem/VX_local_mem.sv new file mode 100644 index 0000000..3510d31 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_local_mem.sv @@ -0,0 +1,350 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_local_mem import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + + // Size of cache in bytes + parameter SIZE = (1024*16*8), + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + // Number of banks + parameter NUM_BANKS = 4, + + // Address width + parameter ADDR_WIDTH = `CLOG2(SIZE), + // Size of a word in bytes + parameter WORD_SIZE = `XLEN/8, + + // Request tag size + parameter TAG_WIDTH = 16, + + // Response buffer + parameter OUT_BUF = 0 + ) ( + input wire clk, + input wire reset, + + // PERF +`ifdef PERF_ENABLE + output lmem_perf_t lmem_perf, +`endif + + VX_mem_bus_if.slave mem_bus_if [NUM_REQS] +); + `UNUSED_SPARAM (INSTANCE_ID) + + localparam REQ_SEL_BITS = `CLOG2(NUM_REQS); + localparam REQ_SEL_WIDTH = `UP(REQ_SEL_BITS); + localparam WORD_WIDTH = WORD_SIZE * 8; + localparam NUM_WORDS = SIZE / WORD_SIZE; + localparam WORDS_PER_BANK = NUM_WORDS / NUM_BANKS; + localparam BANK_ADDR_WIDTH = `CLOG2(WORDS_PER_BANK); + localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS); + localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS); + localparam REQ_DATAW = 1 + BANK_ADDR_WIDTH + WORD_SIZE + WORD_WIDTH + TAG_WIDTH; + localparam RSP_DATAW = WORD_WIDTH + TAG_WIDTH; + + `STATIC_ASSERT(ADDR_WIDTH == (BANK_ADDR_WIDTH + `CLOG2(NUM_BANKS)), ("invalid parameter")) + + // bank selection + + wire [NUM_REQS-1:0][BANK_SEL_WIDTH-1:0] req_bank_idx; + if (NUM_BANKS > 1) begin : g_req_bank_idx + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_bank_idxs + assign req_bank_idx[i] = mem_bus_if[i].req_data.addr[0 +: BANK_SEL_BITS]; + end + end else begin : g_req_bank_idx_0 + assign req_bank_idx = 0; + end + + // bank addressing + + wire [NUM_REQS-1:0][BANK_ADDR_WIDTH-1:0] req_bank_addr; + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_bank_addr + assign req_bank_addr[i] = mem_bus_if[i].req_data.addr[BANK_SEL_BITS +: BANK_ADDR_WIDTH]; + `UNUSED_VAR (mem_bus_if[i].req_data.flags) + end + + // bank requests dispatch + + wire [NUM_BANKS-1:0] per_bank_req_valid; + wire [NUM_BANKS-1:0] per_bank_req_rw; + wire [NUM_BANKS-1:0][BANK_ADDR_WIDTH-1:0] per_bank_req_addr; + wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_req_byteen; + wire [NUM_BANKS-1:0][WORD_WIDTH-1:0] per_bank_req_data; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_req_tag; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_req_idx; + wire [NUM_BANKS-1:0] per_bank_req_ready; + + wire [NUM_BANKS-1:0][REQ_DATAW-1:0] per_bank_req_data_aos; + + wire [NUM_REQS-1:0] req_valid_in; + wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_REQS-1:0] req_ready_in; + +`ifdef PERF_ENABLE + wire [PERF_CTR_BITS-1:0] perf_collisions; +`endif + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_data_in + assign req_valid_in[i] = mem_bus_if[i].req_valid; + assign req_data_in[i] = { + mem_bus_if[i].req_data.rw, + req_bank_addr[i], + mem_bus_if[i].req_data.data, + mem_bus_if[i].req_data.byteen, + mem_bus_if[i].req_data.tag + }; + assign mem_bus_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_xbar #( + .NUM_INPUTS (NUM_REQS), + .NUM_OUTPUTS (NUM_BANKS), + .DATAW (REQ_DATAW), + .PERF_CTR_BITS (PERF_CTR_BITS), + .ARBITER ("P"), + .OUT_BUF (3) // output should be registered for the data_store addressing + ) req_xbar ( + .clk (clk), + .reset (reset), + `ifdef PERF_ENABLE + .collisions (perf_collisions), + `else + `UNUSED_PIN (collisions), + `endif + .valid_in (req_valid_in), + .data_in (req_data_in), + .sel_in (req_bank_idx), + .ready_in (req_ready_in), + .valid_out (per_bank_req_valid), + .data_out (per_bank_req_data_aos), + .sel_out (per_bank_req_idx), + .ready_out (per_bank_req_ready) + ); + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_per_bank_req_data_soa + assign { + per_bank_req_rw[i], + per_bank_req_addr[i], + per_bank_req_data[i], + per_bank_req_byteen[i], + per_bank_req_tag[i] + } = per_bank_req_data_aos[i]; + end + + // banks access + + wire [NUM_BANKS-1:0] per_bank_rsp_valid; + wire [NUM_BANKS-1:0][WORD_WIDTH-1:0] per_bank_rsp_data; + wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] per_bank_rsp_idx; + wire [NUM_BANKS-1:0][TAG_WIDTH-1:0] per_bank_rsp_tag; + wire [NUM_BANKS-1:0] per_bank_rsp_ready; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_data_store + wire bank_rsp_valid, bank_rsp_ready; + + VX_sp_ram #( + .DATAW (WORD_WIDTH), + .SIZE (WORDS_PER_BANK), + .WRENW (WORD_SIZE), + .OUT_REG (1), + .RDW_MODE ("R") + ) lmem_store ( + .clk (clk), + .reset (reset), + .read (per_bank_req_valid[i] && per_bank_req_ready[i] && ~per_bank_req_rw[i]), + .write (per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]), + .wren (per_bank_req_byteen[i]), + .addr (per_bank_req_addr[i]), + .wdata (per_bank_req_data[i]), + .rdata (per_bank_rsp_data[i]) + ); + + // read-during-write hazard detection + reg [BANK_ADDR_WIDTH-1:0] last_wr_addr; + reg last_wr_valid; + always @(posedge clk) begin + if (reset) begin + last_wr_valid <= 0; + end else begin + last_wr_valid <= per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]; + end + last_wr_addr <= per_bank_req_addr[i]; + end + wire is_rdw_hazard = last_wr_valid && ~per_bank_req_rw[i] && (per_bank_req_addr[i] == last_wr_addr); + + // drop write response + assign bank_rsp_valid = per_bank_req_valid[i] && ~per_bank_req_rw[i] && ~is_rdw_hazard; + assign per_bank_req_ready[i] = (bank_rsp_ready || per_bank_req_rw[i]) && ~is_rdw_hazard; + + // register BRAM output + VX_pipe_buffer #( + .DATAW (REQ_SEL_WIDTH + TAG_WIDTH) + ) bram_buf ( + .clk (clk), + .reset (reset), + .valid_in (bank_rsp_valid), + .ready_in (bank_rsp_ready), + .data_in ({per_bank_req_idx[i], per_bank_req_tag[i]}), + .data_out ({per_bank_rsp_idx[i], per_bank_rsp_tag[i]}), + .valid_out (per_bank_rsp_valid[i]), + .ready_out (per_bank_rsp_ready[i]) + ); + end + + // bank responses gather + + wire [NUM_BANKS-1:0][RSP_DATAW-1:0] per_bank_rsp_data_aos; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_per_bank_rsp_data_aos + assign per_bank_rsp_data_aos[i] = {per_bank_rsp_data[i], per_bank_rsp_tag[i]}; + end + + wire [NUM_REQS-1:0] rsp_valid_out; + wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_data_out; + wire [NUM_REQS-1:0] rsp_ready_out; + + VX_stream_xbar #( + .NUM_INPUTS (NUM_BANKS), + .NUM_OUTPUTS (NUM_REQS), + .DATAW (RSP_DATAW), + .ARBITER ("P"), // this priority arbiter has negligeable impact om performance + .OUT_BUF (OUT_BUF) + ) rsp_xbar ( + .clk (clk), + .reset (reset), + `UNUSED_PIN (collisions), + .sel_in (per_bank_rsp_idx), + .valid_in (per_bank_rsp_valid), + .data_in (per_bank_rsp_data_aos), + .ready_in (per_bank_rsp_ready), + .valid_out (rsp_valid_out), + .data_out (rsp_data_out), + .ready_out (rsp_ready_out), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_mem_bus_if + assign mem_bus_if[i].rsp_valid = rsp_valid_out[i]; + assign mem_bus_if[i].rsp_data = rsp_data_out[i]; + assign rsp_ready_out[i] = mem_bus_if[i].rsp_ready; + end + +`ifdef PERF_ENABLE + // per cycle: reads, writes + wire [`CLOG2(NUM_REQS+1)-1:0] perf_reads_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_writes_per_cycle; + wire [`CLOG2(NUM_REQS+1)-1:0] perf_crsp_stall_per_cycle; + + wire [NUM_REQS-1:0] req_rw; + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_rw + assign req_rw[i] = mem_bus_if[i].req_data.rw; + end + + wire [NUM_REQS-1:0] perf_reads_per_req, perf_writes_per_req; + wire [NUM_REQS-1:0] perf_crsp_stall_per_req = rsp_valid_out & ~rsp_ready_out; + + `BUFFER(perf_reads_per_req, req_valid_in & req_ready_in & ~req_rw); + `BUFFER(perf_writes_per_req, req_valid_in & req_ready_in & req_rw); + + `POP_COUNT(perf_reads_per_cycle, perf_reads_per_req); + `POP_COUNT(perf_writes_per_cycle, perf_writes_per_req); + `POP_COUNT(perf_crsp_stall_per_cycle, perf_crsp_stall_per_req); + + reg [PERF_CTR_BITS-1:0] perf_reads; + reg [PERF_CTR_BITS-1:0] perf_writes; + reg [PERF_CTR_BITS-1:0] perf_crsp_stalls; + + always @(posedge clk) begin + if (reset) begin + perf_reads <= '0; + perf_writes <= '0; + perf_crsp_stalls <= '0; + end else begin + perf_reads <= perf_reads + PERF_CTR_BITS'(perf_reads_per_cycle); + perf_writes <= perf_writes + PERF_CTR_BITS'(perf_writes_per_cycle); + perf_crsp_stalls <= perf_crsp_stalls + PERF_CTR_BITS'(perf_crsp_stall_per_cycle); + end + end + + assign lmem_perf.reads = perf_reads; + assign lmem_perf.writes = perf_writes; + assign lmem_perf.bank_stalls = perf_collisions; + assign lmem_perf.crsp_stalls = perf_crsp_stalls; + +`endif + +`ifdef DBG_TRACE_MEM + + wire [NUM_BANKS-1:0][TAG_WIDTH-UUID_WIDTH-1:0] per_bank_req_tag_value; + wire [NUM_BANKS-1:0][`UP(UUID_WIDTH)-1:0] per_bank_req_uuid; + + wire [NUM_BANKS-1:0][TAG_WIDTH-UUID_WIDTH-1:0] per_bank_rsp_tag_value; + wire [NUM_BANKS-1:0][`UP(UUID_WIDTH)-1:0] per_bank_rsp_uuid; + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_per_bank_req_uuid + assign per_bank_req_tag_value[i] = per_bank_req_tag[i][TAG_WIDTH-UUID_WIDTH-1:0]; + assign per_bank_rsp_tag_value[i] = per_bank_rsp_tag[i][TAG_WIDTH-UUID_WIDTH-1:0]; + if (UUID_WIDTH != 0) begin : g_uuid + assign per_bank_req_uuid[i] = per_bank_req_tag[i][TAG_WIDTH-1 -: UUID_WIDTH]; + assign per_bank_rsp_uuid[i] = per_bank_rsp_tag[i][TAG_WIDTH-1 -: UUID_WIDTH]; + end else begin : g_no_uuid + assign per_bank_req_uuid[i] = 0; + assign per_bank_rsp_uuid[i] = 0; + end + end + + for (genvar i = 0; i < NUM_REQS; ++i) begin : g_req_trace + always @(posedge clk) begin + if (mem_bus_if[i].req_valid && mem_bus_if[i].req_ready) begin + if (mem_bus_if[i].req_data.rw) begin + `TRACE(2, ("%t: %s core-wr-req[%0d]: addr=0x%0h, byteen=0x%h, data=0x%h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, mem_bus_if[i].req_data.addr, mem_bus_if[i].req_data.byteen, mem_bus_if[i].req_data.data, mem_bus_if[i].req_data.tag.value, mem_bus_if[i].req_data.tag.uuid)) + end else begin + `TRACE(2, ("%t: %s core-rd-req[%0d]: addr=0x%0h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, mem_bus_if[i].req_data.addr, mem_bus_if[i].req_data.tag.value, mem_bus_if[i].req_data.tag.uuid)) + end + end + if (mem_bus_if[i].rsp_valid && mem_bus_if[i].rsp_ready) begin + `TRACE(2, ("%t: %s core-rd-rsp[%0d]: data=0x%h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, mem_bus_if[i].rsp_data.data, mem_bus_if[i].rsp_data.tag.value, mem_bus_if[i].rsp_data.tag.uuid)) + end + end + end + + for (genvar i = 0; i < NUM_BANKS; ++i) begin : g_bank_trace + always @(posedge clk) begin + if (per_bank_req_valid[i] && per_bank_req_ready[i]) begin + if (per_bank_req_rw[i]) begin + `TRACE(2, ("%t: %s bank-wr-req[%0d]: addr=0x%0h, byteen=0x%h, data=0x%h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, per_bank_req_addr[i], per_bank_req_byteen[i], per_bank_req_data[i], per_bank_req_tag_value[i], per_bank_req_uuid[i])) + end else begin + `TRACE(2, ("%t: %s bank-rd-req[%0d]: addr=0x%0h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, per_bank_req_addr[i], per_bank_req_tag_value[i], per_bank_req_uuid[i])) + end + end + if (per_bank_rsp_valid[i] && per_bank_rsp_ready[i]) begin + `TRACE(2, ("%t: %s bank-rd-rsp[%0d]: data=0x%h, tag=0x%0h (#%0d)\n", + $time, INSTANCE_ID, i, per_bank_rsp_data[i], per_bank_rsp_tag_value[i], per_bank_rsp_uuid[i])) + end + end + end + +`endif + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_local_mem_top.sv b/designs/src/vortex/rtl/mem/VX_local_mem_top.sv new file mode 100644 index 0000000..f45e470 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_local_mem_top.sv @@ -0,0 +1,99 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_local_mem_top import VX_gpu_pkg::*; #( + parameter `STRING INSTANCE_ID = "", + + // Size of cache in bytes + parameter SIZE = (1024*16*8), + + // Number of Word requests per cycle + parameter NUM_REQS = 4, + // Number of banks + parameter NUM_BANKS = 4, + + // Size of a word in bytes + parameter WORD_SIZE = `XLEN/8, + + // Request tag size + parameter TAG_WIDTH = 16, + + // Address width + parameter NUM_WORDS = SIZE / WORD_SIZE, + parameter WORDS_PER_BANK = NUM_WORDS / NUM_BANKS, + parameter BANK_ADDR_WIDTH = `CLOG2(WORDS_PER_BANK), + parameter ADDR_WIDTH = BANK_ADDR_WIDTH + `CLOG2(NUM_BANKS) + ) ( + input wire clk, + input wire reset, + + // Core request + input wire [NUM_REQS-1:0] mem_req_valid, + input wire [NUM_REQS-1:0] mem_req_rw, + input wire [NUM_REQS-1:0][WORD_SIZE-1:0] mem_req_byteen, + input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] mem_req_addr, + input wire [NUM_REQS-1:0][MEM_FLAGS_WIDTH-1:0] mem_req_flags, + input wire [NUM_REQS-1:0][WORD_SIZE*8-1:0] mem_req_data, + input wire [NUM_REQS-1:0][TAG_WIDTH-1:0] mem_req_tag, + output wire [NUM_REQS-1:0] mem_req_ready, + + // Core response + output wire [NUM_REQS-1:0] mem_rsp_valid, + output wire [NUM_REQS-1:0][WORD_SIZE*8-1:0] mem_rsp_data, + output wire [NUM_REQS-1:0][TAG_WIDTH-1:0] mem_rsp_tag, + input wire [NUM_REQS-1:0] mem_rsp_ready +); + VX_mem_bus_if #( + .DATA_SIZE (WORD_SIZE), + .TAG_WIDTH (TAG_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH) + ) mem_bus_if[NUM_REQS](); + + // memory request + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign mem_bus_if[i].req_valid = mem_req_valid[i]; + assign mem_bus_if[i].req_data.rw = mem_req_rw[i]; + assign mem_bus_if[i].req_data.byteen = mem_req_byteen[i]; + assign mem_bus_if[i].req_data.addr = mem_req_addr[i]; + assign mem_bus_if[i].req_data.flags = mem_req_flags[i]; + assign mem_bus_if[i].req_data.data = mem_req_data[i]; + assign mem_bus_if[i].req_data.tag = mem_req_tag[i]; + assign mem_req_ready[i] = mem_bus_if[i].req_ready; + end + + // memory response + for (genvar i = 0; i < NUM_REQS; ++i) begin + assign mem_rsp_valid[i] = mem_bus_if[i].rsp_valid; + assign mem_rsp_data[i] = mem_bus_if[i].rsp_data.data; + assign mem_rsp_tag[i] = mem_bus_if[i].rsp_data.tag; + assign mem_bus_if[i].rsp_ready = mem_rsp_ready[i]; + end + + VX_local_mem #( + .INSTANCE_ID(INSTANCE_ID), + .SIZE (SIZE), + .NUM_REQS (NUM_REQS), + .NUM_BANKS (NUM_BANKS), + .WORD_SIZE (WORD_SIZE), + .ADDR_WIDTH (ADDR_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .OUT_BUF (3) + ) local_mem ( + .clk (clk), + .reset (reset), + .mem_bus_if (mem_bus_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_lsu_adapter.sv b/designs/src/vortex/rtl/mem/VX_lsu_adapter.sv new file mode 100644 index 0000000..788f8ac --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_lsu_adapter.sv @@ -0,0 +1,121 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_lsu_adapter import VX_gpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter DATA_SIZE = 1, + parameter TAG_WIDTH = 1, + parameter TAG_SEL_BITS = 0, + parameter `STRING ARBITER = "P", + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0 +) ( + input wire clk, + input wire reset, + + VX_lsu_mem_if.slave lsu_mem_if, + VX_mem_bus_if.master mem_bus_if [NUM_LANES] +); + localparam REQ_ADDR_WIDTH = `MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE); + localparam REQ_DATA_WIDTH = 1 + DATA_SIZE + REQ_ADDR_WIDTH + MEM_FLAGS_WIDTH + DATA_SIZE * 8; + localparam RSP_DATA_WIDTH = DATA_SIZE * 8; + + // handle request unpacking + + wire [NUM_LANES-1:0][REQ_DATA_WIDTH-1:0] req_data_in; + + wire [NUM_LANES-1:0] req_valid_out; + wire [NUM_LANES-1:0][REQ_DATA_WIDTH-1:0] req_data_out; + wire [NUM_LANES-1:0][TAG_WIDTH-1:0] req_tag_out; + wire [NUM_LANES-1:0] req_ready_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_req_data_in + assign req_data_in[i] = { + lsu_mem_if.req_data.rw, + lsu_mem_if.req_data.addr[i], + lsu_mem_if.req_data.data[i], + lsu_mem_if.req_data.byteen[i], + lsu_mem_if.req_data.flags[i] + }; + end + + VX_stream_unpack #( + .NUM_REQS (NUM_LANES), + .DATA_WIDTH (REQ_DATA_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .OUT_BUF (REQ_OUT_BUF) + ) stream_unpack ( + .clk (clk), + .reset (reset), + .valid_in (lsu_mem_if.req_valid), + .mask_in (lsu_mem_if.req_data.mask), + .data_in (req_data_in), + .tag_in (lsu_mem_if.req_data.tag), + .ready_in (lsu_mem_if.req_ready), + .valid_out (req_valid_out), + .data_out (req_data_out), + .tag_out (req_tag_out), + .ready_out (req_ready_out) + ); + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_bus_req + assign mem_bus_if[i].req_valid = req_valid_out[i]; + assign { + mem_bus_if[i].req_data.rw, + mem_bus_if[i].req_data.addr, + mem_bus_if[i].req_data.data, + mem_bus_if[i].req_data.byteen, + mem_bus_if[i].req_data.flags + } = req_data_out[i]; + assign mem_bus_if[i].req_data.tag = req_tag_out[i]; + assign req_ready_out[i] = mem_bus_if[i].req_ready; + end + + // handle response packing + + wire [NUM_LANES-1:0] rsp_valid_out; + wire [NUM_LANES-1:0][RSP_DATA_WIDTH-1:0] rsp_data_out; + wire [NUM_LANES-1:0][TAG_WIDTH-1:0] rsp_tag_out; + wire [NUM_LANES-1:0] rsp_ready_out; + + for (genvar i = 0; i < NUM_LANES; ++i) begin : g_mem_bus_rsp + assign rsp_valid_out[i] = mem_bus_if[i].rsp_valid; + assign rsp_data_out[i] = mem_bus_if[i].rsp_data.data; + assign rsp_tag_out[i] = mem_bus_if[i].rsp_data.tag; + assign mem_bus_if[i].rsp_ready = rsp_ready_out[i]; + end + + VX_stream_pack #( + .NUM_REQS (NUM_LANES), + .DATA_WIDTH (RSP_DATA_WIDTH), + .TAG_WIDTH (TAG_WIDTH), + .TAG_SEL_BITS (TAG_SEL_BITS), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) stream_pack ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid_out), + .data_in (rsp_data_out), + .tag_in (rsp_tag_out), + .ready_in (rsp_ready_out), + .valid_out (lsu_mem_if.rsp_valid), + .mask_out (lsu_mem_if.rsp_data.mask), + .data_out (lsu_mem_if.rsp_data.data), + .tag_out (lsu_mem_if.rsp_data.tag), + .ready_out (lsu_mem_if.rsp_ready) + ); + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_lsu_mem_arb.sv b/designs/src/vortex/rtl/mem/VX_lsu_mem_arb.sv new file mode 100644 index 0000000..3b77ac1 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_lsu_mem_arb.sv @@ -0,0 +1,191 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_lsu_mem_arb import VX_gpu_pkg::*; #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter NUM_LANES = 1, + parameter DATA_SIZE = 1, + parameter TAG_WIDTH = 1, + parameter TAG_SEL_IDX = 0, + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0, + parameter `STRING ARBITER = "R", + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)), + parameter FLAGS_WIDTH = MEM_FLAGS_WIDTH +) ( + input wire clk, + input wire reset, + + VX_lsu_mem_if.slave bus_in_if [NUM_INPUTS], + VX_lsu_mem_if.master bus_out_if [NUM_OUTPUTS] +); + localparam DATA_WIDTH = (8 * DATA_SIZE); + localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS); + localparam REQ_DATAW = 1 + NUM_LANES * (1 + ADDR_WIDTH + DATA_WIDTH + DATA_SIZE + FLAGS_WIDTH) + TAG_WIDTH; + localparam RSP_DATAW = NUM_LANES * (1 + DATA_WIDTH) + TAG_WIDTH; + + //`STATIC_ASSERT ((NUM_INPUTS >= NUM_OUTPUTS), ("invalid parameter: NUM_INPUTS=%0d, NUM_OUTPUTS=%0d", NUM_INPUTS, NUM_OUTPUTS)); + + wire [NUM_OUTPUTS-1:0] req_valid_out; + wire [NUM_OUTPUTS-1:0][REQ_DATAW-1:0] req_data_out; + wire [NUM_OUTPUTS-1:0] req_ready_out; + wire [NUM_OUTPUTS-1:0][`UP(LOG_NUM_REQS)-1:0] req_sel_out; + + wire [NUM_INPUTS-1:0] req_valid_in; + wire [NUM_INPUTS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_INPUTS-1:0] req_ready_in; + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_req_data_in + assign req_valid_in[i] = bus_in_if[i].req_valid; + assign req_data_in[i] = bus_in_if[i].req_data; + assign bus_in_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (REQ_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (REQ_OUT_BUF) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (req_valid_in), + .ready_in (req_ready_in), + .data_in (req_data_in), + .data_out (req_data_out), + .sel_out (req_sel_out), + .valid_out (req_valid_out), + .ready_out (req_ready_out) + ); + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_bus_out_if + wire [TAG_WIDTH-1:0] req_tag_out; + assign bus_out_if[i].req_valid = req_valid_out[i]; + assign { + bus_out_if[i].req_data.mask, + bus_out_if[i].req_data.rw, + bus_out_if[i].req_data.addr, + bus_out_if[i].req_data.data, + bus_out_if[i].req_data.byteen, + bus_out_if[i].req_data.flags, + req_tag_out + } = req_data_out[i]; + assign req_ready_out[i] = bus_out_if[i].req_ready; + + if (NUM_INPUTS > NUM_OUTPUTS) begin : g_req_tag_sel_out + VX_bits_insert #( + .N (TAG_WIDTH), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_insert ( + .data_in (req_tag_out), + .ins_in (req_sel_out[i]), + .data_out (bus_out_if[i].req_data.tag) + ); + end else begin : g_req_tag_out + `UNUSED_VAR (req_sel_out) + assign bus_out_if[i].req_data.tag = req_tag_out; + end + end + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_INPUTS-1:0] rsp_valid_out; + wire [NUM_INPUTS-1:0][RSP_DATAW-1:0] rsp_data_out; + wire [NUM_INPUTS-1:0] rsp_ready_out; + + wire [NUM_OUTPUTS-1:0] rsp_valid_in; + wire [NUM_OUTPUTS-1:0][RSP_DATAW-1:0] rsp_data_in; + wire [NUM_OUTPUTS-1:0] rsp_ready_in; + + if (NUM_INPUTS > NUM_OUTPUTS) begin : g_rsp_select + + wire [NUM_OUTPUTS-1:0][LOG_NUM_REQS-1:0] rsp_sel_in; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_rsp_data_in + wire [TAG_WIDTH-1:0] rsp_tag_out; + VX_bits_remove #( + .N (TAG_WIDTH + LOG_NUM_REQS), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_remove ( + .data_in (bus_out_if[i].rsp_data.tag), + .sel_out (rsp_sel_in[i]), + .data_out (rsp_tag_out) + ); + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = { + bus_out_if[i].rsp_data.mask, + bus_out_if[i].rsp_data.data, + rsp_tag_out + }; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + end + + VX_stream_switch #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_INPUTS), + .DATAW (RSP_DATAW), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_switch ( + .clk (clk), + .reset (reset), + .sel_in (rsp_sel_in), + .valid_in (rsp_valid_in), + .ready_in (rsp_ready_in), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid_out), + .ready_out (rsp_ready_out) + ); + + end else begin : g_rsp_arb + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_rsp_data_in + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = bus_out_if[i].rsp_data; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_INPUTS), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid_in), + .ready_in (rsp_ready_in), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid_out), + .ready_out (rsp_ready_out), + `UNUSED_PIN (sel_out) + ); + + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_output + assign bus_in_if[i].rsp_valid = rsp_valid_out[i]; + assign bus_in_if[i].rsp_data = rsp_data_out[i]; + assign rsp_ready_out[i] = bus_in_if[i].rsp_ready; + end + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_lsu_mem_if.sv b/designs/src/vortex/rtl/mem/VX_lsu_mem_if.sv new file mode 100644 index 0000000..f8e5629 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_lsu_mem_if.sv @@ -0,0 +1,74 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_lsu_mem_if import VX_gpu_pkg::*; #( + parameter NUM_LANES = 1, + parameter DATA_SIZE = 1, + parameter TAG_WIDTH = 1, + parameter FLAGS_WIDTH = MEM_FLAGS_WIDTH, + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE) +) (); + + typedef struct packed { + logic [`UP(UUID_WIDTH)-1:0] uuid; + logic [TAG_WIDTH-`UP(UUID_WIDTH)-1:0] value; + } tag_t; + + typedef struct packed { + logic [NUM_LANES-1:0] mask; + logic rw; + logic [NUM_LANES-1:0][ADDR_WIDTH-1:0] addr; + logic [NUM_LANES-1:0][DATA_SIZE*8-1:0] data; + logic [NUM_LANES-1:0][DATA_SIZE-1:0] byteen; + logic [NUM_LANES-1:0][FLAGS_WIDTH-1:0] flags; + tag_t tag; + } req_data_t; + + typedef struct packed { + logic [NUM_LANES-1:0] mask; + logic [NUM_LANES-1:0][DATA_SIZE*8-1:0] data; + tag_t tag; + } rsp_data_t; + + logic req_valid; + req_data_t req_data; + logic req_ready; + + logic rsp_valid; + rsp_data_t rsp_data; + logic rsp_ready; + + modport master ( + output req_valid, + output req_data, + input req_ready, + + input rsp_valid, + input rsp_data, + output rsp_ready + ); + + modport slave ( + input req_valid, + input req_data, + output req_ready, + + output rsp_valid, + output rsp_data, + input rsp_ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/mem/VX_mem_arb.sv b/designs/src/vortex/rtl/mem/VX_mem_arb.sv new file mode 100644 index 0000000..5548cf2 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_mem_arb.sv @@ -0,0 +1,184 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_mem_arb import VX_gpu_pkg::*; #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATA_SIZE = 1, + parameter TAG_WIDTH = 1, + parameter TAG_SEL_IDX = 0, + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0, + parameter `STRING ARBITER = "R", + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)), + parameter FLAGS_WIDTH = MEM_FLAGS_WIDTH +) ( + input wire clk, + input wire reset, + + VX_mem_bus_if.slave bus_in_if [NUM_INPUTS], + VX_mem_bus_if.master bus_out_if [NUM_OUTPUTS] +); + localparam DATA_WIDTH = (8 * DATA_SIZE); + localparam LOG_NUM_REQS = `ARB_SEL_BITS(NUM_INPUTS, NUM_OUTPUTS); + localparam REQ_DATAW = 1 + ADDR_WIDTH + DATA_WIDTH + DATA_SIZE + FLAGS_WIDTH + TAG_WIDTH; + localparam RSP_DATAW = DATA_WIDTH + TAG_WIDTH; + localparam SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS); + + wire [NUM_INPUTS-1:0] req_valid_in; + wire [NUM_INPUTS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_INPUTS-1:0] req_ready_in; + + wire [NUM_OUTPUTS-1:0] req_valid_out; + wire [NUM_OUTPUTS-1:0][REQ_DATAW-1:0] req_data_out; + wire [SEL_COUNT-1:0][`UP(LOG_NUM_REQS)-1:0] req_sel_out; + wire [NUM_OUTPUTS-1:0] req_ready_out; + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_req_data_in + assign req_valid_in[i] = bus_in_if[i].req_valid; + assign req_data_in[i] = bus_in_if[i].req_data; + assign bus_in_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (REQ_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (REQ_OUT_BUF) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (req_valid_in), + .ready_in (req_ready_in), + .data_in (req_data_in), + .data_out (req_data_out), + .sel_out (req_sel_out), + .valid_out (req_valid_out), + .ready_out (req_ready_out) + ); + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_bus_out_if + wire [TAG_WIDTH-1:0] req_tag_out; + assign bus_out_if[i].req_valid = req_valid_out[i]; + assign { + bus_out_if[i].req_data.rw, + bus_out_if[i].req_data.addr, + bus_out_if[i].req_data.data, + bus_out_if[i].req_data.byteen, + bus_out_if[i].req_data.flags, + req_tag_out + } = req_data_out[i]; + assign req_ready_out[i] = bus_out_if[i].req_ready; + + if (NUM_INPUTS > NUM_OUTPUTS) begin : g_req_tag_sel_out + VX_bits_insert #( + .N (TAG_WIDTH), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_insert ( + .data_in (req_tag_out), + .ins_in (req_sel_out[i]), + .data_out (bus_out_if[i].req_data.tag) + ); + end else begin : g_req_tag_out + `UNUSED_VAR (req_sel_out) + assign bus_out_if[i].req_data.tag = req_tag_out; + end + end + + /////////////////////////////////////////////////////////////////////////// + + wire [NUM_INPUTS-1:0] rsp_valid_out; + wire [NUM_INPUTS-1:0][RSP_DATAW-1:0] rsp_data_out; + wire [NUM_INPUTS-1:0] rsp_ready_out; + + wire [NUM_OUTPUTS-1:0] rsp_valid_in; + wire [NUM_OUTPUTS-1:0][RSP_DATAW-1:0] rsp_data_in; + wire [NUM_OUTPUTS-1:0] rsp_ready_in; + + if (NUM_INPUTS > NUM_OUTPUTS) begin : g_rsp_select + + wire [NUM_OUTPUTS-1:0][LOG_NUM_REQS-1:0] rsp_sel_in; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_rsp_data_in + wire [TAG_WIDTH-1:0] rsp_tag_out; + VX_bits_remove #( + .N (TAG_WIDTH + LOG_NUM_REQS), + .S (LOG_NUM_REQS), + .POS (TAG_SEL_IDX) + ) bits_remove ( + .data_in (bus_out_if[i].rsp_data.tag), + .sel_out (rsp_sel_in[i]), + .data_out (rsp_tag_out) + ); + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = {bus_out_if[i].rsp_data.data, rsp_tag_out}; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + end + + VX_stream_switch #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_INPUTS), + .DATAW (RSP_DATAW), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_switch ( + .clk (clk), + .reset (reset), + .sel_in (rsp_sel_in), + .valid_in (rsp_valid_in), + .ready_in (rsp_ready_in), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid_out), + .ready_out (rsp_ready_out) + ); + + end else begin : g_rsp_arb + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_rsp_data_in + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = bus_out_if[i].rsp_data; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS (NUM_INPUTS), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid_in), + .ready_in (rsp_ready_in), + .data_in (rsp_data_in), + .data_out (rsp_data_out), + .valid_out (rsp_valid_out), + .ready_out (rsp_ready_out), + `UNUSED_PIN (sel_out) + ); + + end + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_output + assign bus_in_if[i].rsp_valid = rsp_valid_out[i]; + assign bus_in_if[i].rsp_data = rsp_data_out[i]; + assign rsp_ready_out[i] = bus_in_if[i].rsp_ready; + end + +endmodule diff --git a/designs/src/vortex/rtl/mem/VX_mem_bus_if.sv b/designs/src/vortex/rtl/mem/VX_mem_bus_if.sv new file mode 100644 index 0000000..1a1b281 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_mem_bus_if.sv @@ -0,0 +1,71 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +interface VX_mem_bus_if import VX_gpu_pkg::*; #( + parameter DATA_SIZE = 1, + parameter FLAGS_WIDTH = MEM_FLAGS_WIDTH, + parameter TAG_WIDTH = 1, + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE) +) (); + + typedef struct packed { + logic [`UP(UUID_WIDTH)-1:0] uuid; + logic [TAG_WIDTH-`UP(UUID_WIDTH)-1:0] value; + } tag_t; + + typedef struct packed { + logic rw; + logic [ADDR_WIDTH-1:0] addr; + logic [DATA_SIZE*8-1:0] data; + logic [DATA_SIZE-1:0] byteen; + logic [FLAGS_WIDTH-1:0] flags; + tag_t tag; + } req_data_t; + + typedef struct packed { + logic [DATA_SIZE*8-1:0] data; + tag_t tag; + } rsp_data_t; + + logic req_valid; + req_data_t req_data; + logic req_ready; + + logic rsp_valid; + rsp_data_t rsp_data; + logic rsp_ready; + + modport master ( + output req_valid, + output req_data, + input req_ready, + + input rsp_valid, + input rsp_data, + output rsp_ready + ); + + modport slave ( + input req_valid, + input req_data, + output req_ready, + + output rsp_valid, + output rsp_data, + input rsp_ready + ); + +endinterface diff --git a/designs/src/vortex/rtl/mem/VX_mem_switch.sv b/designs/src/vortex/rtl/mem/VX_mem_switch.sv new file mode 100644 index 0000000..6f68a55 --- /dev/null +++ b/designs/src/vortex/rtl/mem/VX_mem_switch.sv @@ -0,0 +1,120 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_mem_switch import VX_gpu_pkg::*; #( + parameter NUM_INPUTS = 1, + parameter NUM_OUTPUTS = 1, + parameter DATA_SIZE = 1, + parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH, + parameter ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)), + parameter TAG_WIDTH = 1, + parameter REQ_OUT_BUF = 0, + parameter RSP_OUT_BUF = 0, + parameter `STRING ARBITER = "R", + parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? `CDIV(NUM_INPUTS, NUM_OUTPUTS) : `CDIV(NUM_OUTPUTS, NUM_INPUTS), + parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS), + parameter LOG_NUM_REQS = `CLOG2(NUM_REQS) +) ( + input wire clk, + input wire reset, + + input wire [SEL_COUNT-1:0][`UP(LOG_NUM_REQS)-1:0] bus_sel, + VX_mem_bus_if.slave bus_in_if [NUM_INPUTS], + VX_mem_bus_if.master bus_out_if [NUM_OUTPUTS] +); + localparam DATA_WIDTH = (8 * DATA_SIZE); + localparam REQ_DATAW = TAG_WIDTH + ADDR_WIDTH + MEM_FLAGS_WIDTH + 1 + DATA_SIZE + DATA_WIDTH; + localparam RSP_DATAW = TAG_WIDTH + DATA_WIDTH; + + // handle requests //////////////////////////////////////////////////////// + + wire [NUM_INPUTS-1:0] req_valid_in; + wire [NUM_INPUTS-1:0][REQ_DATAW-1:0] req_data_in; + wire [NUM_INPUTS-1:0] req_ready_in; + + wire [NUM_OUTPUTS-1:0] req_valid_out; + wire [NUM_OUTPUTS-1:0][REQ_DATAW-1:0] req_data_out; + wire [NUM_OUTPUTS-1:0] req_ready_out; + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_req_data_in + assign req_valid_in[i] = bus_in_if[i].req_valid; + assign req_data_in[i] = bus_in_if[i].req_data; + assign bus_in_if[i].req_ready = req_ready_in[i]; + end + + VX_stream_switch #( + .NUM_INPUTS (NUM_INPUTS), + .NUM_OUTPUTS (NUM_OUTPUTS), + .DATAW (REQ_DATAW), + .OUT_BUF (REQ_OUT_BUF) + ) req_switch ( + .clk (clk), + .reset (reset), + .sel_in (bus_sel), + .valid_in (req_valid_in), + .data_in (req_data_in), + .ready_in (req_ready_in), + .valid_out (req_valid_out), + .data_out (req_data_out), + .ready_out (req_ready_out) + ); + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_req_data_out + assign bus_out_if[i].req_valid = req_valid_out[i]; + assign bus_out_if[i].req_data = req_data_out[i]; + assign req_ready_out[i] = bus_out_if[i].req_ready; + end + + // handle responses /////////////////////////////////////////////////////// + + wire [NUM_OUTPUTS-1:0] rsp_valid_in; + wire [NUM_OUTPUTS-1:0][RSP_DATAW-1:0] rsp_data_in; + wire [NUM_OUTPUTS-1:0] rsp_ready_in; + + wire [NUM_INPUTS-1:0] rsp_valid_out; + wire [NUM_INPUTS-1:0][RSP_DATAW-1:0] rsp_data_out; + wire [NUM_INPUTS-1:0] rsp_ready_out; + + for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin : g_rsp_data_in + assign rsp_valid_in[i] = bus_out_if[i].rsp_valid; + assign rsp_data_in[i] = bus_out_if[i].rsp_data; + assign bus_out_if[i].rsp_ready = rsp_ready_in[i]; + end + + VX_stream_arb #( + .NUM_INPUTS (NUM_OUTPUTS), + .NUM_OUTPUTS(NUM_INPUTS), + .DATAW (RSP_DATAW), + .ARBITER (ARBITER), + .OUT_BUF (RSP_OUT_BUF) + ) rsp_arb ( + .clk (clk), + .reset (reset), + .valid_in (rsp_valid_in), + .data_in (rsp_data_in), + .ready_in (rsp_ready_in), + .valid_out (rsp_valid_out), + .data_out (rsp_data_out), + .ready_out (rsp_ready_out), + `UNUSED_PIN (sel_out) + ); + + for (genvar i = 0; i < NUM_INPUTS; ++i) begin : g_rsp_data_out + assign bus_in_if[i].rsp_valid = rsp_valid_out[i]; + assign bus_in_if[i].rsp_data = rsp_data_out[i]; + assign rsp_ready_out[i] = bus_in_if[i].rsp_ready; + end + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_fedp_bhf.sv b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_bhf.sv new file mode 100644 index 0000000..d11cfc0 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_bhf.sv @@ -0,0 +1,219 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_fedp_bhf #( + parameter LATENCY = 1, + parameter N = 1 +) ( + input wire clk, + input wire reset, + input wire enable, + + input wire[2:0] fmt_s, + input wire[2:0] fmt_d, + + input wire [N-1:0][`XLEN-1:0] a_row, + input wire [N-1:0][`XLEN-1:0] b_col, + input wire [`XLEN-1:0] c_val, + output wire [`XLEN-1:0] d_val +); + localparam TCK = 2 * N; + localparam LEVELS = $clog2(TCK); + localparam FMUL_LATENCY = 2; + localparam FADD_LATENCY = 2; + localparam FRND_LATENCY = 1; + localparam FRED_LATENCY = LEVELS * (FADD_LATENCY + FRND_LATENCY); + localparam TOTAL_LATENCY= (FMUL_LATENCY + FRND_LATENCY) + 1 + FRED_LATENCY + (FADD_LATENCY + FRND_LATENCY); + `STATIC_ASSERT (LATENCY == 0 || LATENCY == TOTAL_LATENCY, ("invalid latency! expected=%0d, actual=%0d", TOTAL_LATENCY, LATENCY)); + + localparam FMT_DELAY = FMUL_LATENCY + FRND_LATENCY; + localparam C_DELAY = (FMUL_LATENCY + FRND_LATENCY) + 1 + FRED_LATENCY; + + `UNUSED_VAR ({fmt_d, c_val}); + + wire [2:0] frm = '0; // RNE rounding mode + + wire [TCK-1:0][15:0] a_row16; + wire [TCK-1:0][15:0] b_col16; + + for (genvar i = 0; i < N; i++) begin : g_unpack + assign a_row16[2*i] = a_row[i][15:0]; + assign a_row16[2*i+1] = a_row[i][31:16]; + assign b_col16[2*i] = b_col[i][15:0]; + assign b_col16[2*i+1] = b_col[i][31:16]; + end + + // Transprecision Multiply + + wire [2:0] fmt_s_delayed; + + VX_pipe_register #( + .DATAW (3), + .DEPTH (FMT_DELAY) + ) pipe_fmt_s ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (fmt_s), + .data_out(fmt_s_delayed) + ); + + wire [32:0] mult_result [TCK]; + + for (genvar i = 0; i < TCK; i++) begin : g_prod + wire [32:0] mult_result_fp16; + wire [32:0] mult_result_bf16; + + // FP16 multiplication + VX_tcu_bhf_fmul #( + .IN_EXPW (5), + .IN_SIGW (10+1), + .OUT_EXPW(8), + .OUT_SIGW(24), + .IN_REC (0), // input in IEEE format + .OUT_REC (1), // output in recoded format + .MUL_LATENCY (FMUL_LATENCY), + .RND_LATENCY (FRND_LATENCY) + ) fp16_mul ( + .clk (clk), + .reset (reset), + .enable (enable), + .frm (frm), + .a (a_row16[i]), + .b (b_col16[i]), + .y (mult_result_fp16), + `UNUSED_PIN(fflags) + ); + + // BF16 multiplication + VX_tcu_bhf_fmul #( + .IN_EXPW (8), + .IN_SIGW (7+1), + .OUT_EXPW(8), + .OUT_SIGW(24), + .IN_REC (0), // input in IEEE format + .OUT_REC (1), // output in recoded format + .MUL_LATENCY (FMUL_LATENCY), + .RND_LATENCY (FRND_LATENCY) + ) bf16_mul ( + .clk (clk), + .reset (reset), + .enable (enable), + .frm (frm), + .a (a_row16[i]), + .b (b_col16[i]), + .y (mult_result_bf16), + `UNUSED_PIN(fflags) + ); + + logic [32:0] mult_result_mux; + always_comb begin + case(fmt_s_delayed) + 3'd1: mult_result_mux = mult_result_fp16; + 3'd2: mult_result_mux = mult_result_bf16; + default: mult_result_mux = 'x; + endcase + end + + VX_pipe_register #( + .DATAW (33), + .DEPTH (1) // select latency + ) pipe_mult ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (mult_result_mux), + .data_out (mult_result[i]) + ); + end + + wire [32:0] red_in [0:LEVELS] [TCK]; + + for (genvar i = 0; i < TCK; i++) begin : g_red_inputs + assign red_in[0][i] = mult_result[i]; + end + + // Accumulate reduction tree + for (genvar lvl = 0; lvl < LEVELS; lvl++) begin : g_red_tree + localparam CURSZ = TCK >> lvl; + localparam OUTSZ = CURSZ >> 1; + + for (genvar i = 0; i < OUTSZ; i++) begin : g_add + VX_tcu_bhf_fadd #( + .IN_EXPW (8), + .IN_SIGW (23+1), + .IN_REC (1), // input in recoded format + .OUT_REC (1), // output in recoded format + .ADD_LATENCY (FADD_LATENCY), + .RND_LATENCY (FRND_LATENCY) + ) reduce_add ( + .clk (clk), + .reset (reset), + .enable (enable), + .frm (frm), + .a (red_in[lvl][2*i+0]), + .b (red_in[lvl][2*i+1]), + .y (red_in[lvl+1][i]), + `UNUSED_PIN(fflags) + ); + end + end + + // Accumulation input C recoding and delay handling + + wire [32:0] c_rec, c_delayed; + wire [31:0] result; + + fNToRecFN #( + .expWidth (8), + .sigWidth (24) + ) conv_c ( + .in (c_val[31:0]), + .out (c_rec) + ); + + VX_pipe_register #( + .DATAW (33), + .DEPTH (C_DELAY) + ) pipe_c ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (c_rec), + .data_out(c_delayed) + ); + + // Final accumulation + VX_tcu_bhf_fadd #( + .IN_EXPW (8), + .IN_SIGW (23+1), + .IN_REC (1), // input in recoded format + .OUT_REC (0), // output in IEEE format + .ADD_LATENCY (FADD_LATENCY), + .RND_LATENCY (FRND_LATENCY) + ) final_add ( + .clk (clk), + .reset (reset), + .enable (enable), + .frm (frm), + .a (red_in[LEVELS][0]), + .b (c_delayed), + .y (result), + `UNUSED_PIN(fflags) + ); + + assign d_val = `XLEN'(result); + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_fedp_dpi.sv b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_dpi.sv new file mode 100644 index 0000000..df783d9 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_dpi.sv @@ -0,0 +1,124 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_fedp_dpi #( + parameter LATENCY = 1, + parameter N = 1 +) ( + input wire clk, + input wire reset, + input wire enable, + + input wire[2:0] fmt_s, + input wire[2:0] fmt_d, + + input wire [N-1:0][`XLEN-1:0] a_row, + input wire [N-1:0][`XLEN-1:0] b_col, + input wire [`XLEN-1:0] c_val, + output wire [`XLEN-1:0] d_val +); + localparam FMUL_LATENCY = 2; + localparam FACC_LATENCY = 2; + localparam TOTAL_LATENCY= FMUL_LATENCY + FACC_LATENCY; + `STATIC_ASSERT (LATENCY == 0 || LATENCY == TOTAL_LATENCY, ("invalid latency! expected=%0d, actual=%0d", TOTAL_LATENCY, LATENCY)); + + `UNUSED_VAR ({fmt_d, c_val}); + + wire [31:0] nult_result [N]; + + // multiplication stage + for (genvar i = 0; i < N; i++) begin : g_prod + reg [63:0] a_f, b_f; + reg [63:0] xprod; + reg [4:0] fflags; + + `UNUSED_VAR({fflags, xprod[63:32]}); + + always @(*) begin + case (fmt_s) + 3'd1: begin // fp16 + xprod = 64'hffffffff00000000; + for (int j = 0; j < 2; j++) begin + dpi_f2f(enable, int'(0), int'(2), {48'hffffffffffff, a_row[i][j * 16 +: 16]}, a_f); + dpi_f2f(enable, int'(0), int'(2), {48'hffffffffffff, b_col[i][j * 16 +: 16]}, b_f); + dpi_fmadd(enable, int'(0), a_f, b_f, xprod, 3'b0, xprod, fflags); + end + end + 3'd2: begin // bf16 + xprod = 64'hffffffff00000000; + for (int j = 0; j < 2; j++) begin + dpi_f2f(enable, int'(0), int'(3), {48'hffffffffffff, a_row[i][j * 16 +: 16]}, a_f); + dpi_f2f(enable, int'(0), int'(3), {48'hffffffffffff, b_col[i][j * 16 +: 16]}, b_f); + dpi_fmadd(enable, int'(0), a_f, b_f, xprod, 3'b0, xprod, fflags); + end + end + default: begin + xprod = 'x; + end + endcase + end + + VX_pipe_register #( + .DATAW (32), + .DEPTH (FMUL_LATENCY) + ) pipe_mult ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (xprod[31:0]), + .data_out (nult_result[i]) + ); + end + + wire [31:0] delayed_c; + + VX_pipe_register #( + .DATAW (32), + .DEPTH (FMUL_LATENCY) + ) pipe_c ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (c_val[31:0]), + .data_out(delayed_c) + ); + + reg [63:0] xacc; + reg [4:0] fflags; + `UNUSED_VAR(fflags); + + always_comb begin + xacc = 64'hffffffff00000000; + for (int i = 0; i < N; ++i) begin + dpi_fadd(enable, int'(0), {32'hffffffff, nult_result[i]}, xacc, 3'b0, xacc, fflags); + end + dpi_fadd(enable, int'(0), {32'hffffffff, delayed_c}, xacc, 3'b0, xacc, fflags); + end + + wire [31:0] result; + VX_pipe_register #( + .DATAW (32), + .DEPTH (FACC_LATENCY) + ) pipe_acc ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (xacc[31:0]), + .data_out(result) + ); + + assign d_val = `XLEN'(result); + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_fedp_dsp.sv b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_dsp.sv new file mode 100644 index 0000000..37ecd24 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_dsp.sv @@ -0,0 +1,309 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +`ifndef SYNTHESIS +`define DSP_TEST +`endif + +// Function to convert IEEE-754 half precision (16-bit) to single precision (32-bit) +module fp16_to_fp32 ( + input wire [15:0] fp16_in, // FP16: 1 sign, 5 exponent, 10 fraction + output wire [31:0] fp32_out // FP32: 1 sign, 8 exponent, 23 fraction +); + // Extract FP16 components + wire sign = fp16_in[15]; + wire [4:0] exponent = fp16_in[14:10]; + wire [9:0] fraction = fp16_in[9:0]; + + // Special case detection + wire is_zero = (exponent == 5'b0) && (fraction == 10'b0); + wire is_denormal = (exponent == 5'b0) && (fraction != 10'b0); + wire is_infinity = (exponent == 5'b11111) && (fraction == 10'b0); + wire is_nan = (exponent == 5'b11111) && (fraction != 10'b0); + + // Denormal handling - normalization and leading zero count + wire [4:0] leading_zeros; + wire [9:0] normalized_frac; + `UNUSED_VAR (normalized_frac[9]); + + // Priority encoder for leading zero count (10-bit) + assign leading_zeros = + fraction[9] ? 5'd0 : + fraction[8] ? 5'd1 : + fraction[7] ? 5'd2 : + fraction[6] ? 5'd3 : + fraction[5] ? 5'd4 : + fraction[4] ? 5'd5 : + fraction[3] ? 5'd6 : + fraction[2] ? 5'd7 : + fraction[1] ? 5'd8 : + fraction[0] ? 5'd9 : 5'd10; + + // Normalize denormal fraction + assign normalized_frac = fraction << leading_zeros; + + // Calculate FP32 exponent + wire [7:0] exp32 = + is_denormal ? 8'd127 - 8'd14 - {3'b0, leading_zeros} + 8'd1 : // 2^(-14 - (10 - leading_zeros)) + is_zero ? 8'b0 : + is_infinity ? 8'b11111111 : + is_nan ? 8'b11111111 : + {3'b0, exponent} + 8'd112; // Normalized: exp16 - 15 + 127 = exp16 + 112 + + // Calculate FP32 fraction + wire [22:0] frac32 = + is_denormal ? {normalized_frac[8:0], 14'b0} : // Use bits after leading one + is_zero ? 23'b0 : + is_infinity ? 23'b0 : + is_nan ? {1'b1, fraction, 12'b0} : // Preserve NaN payload + {fraction, 13'b0}; // Normalized + + // Final FP32 output + assign fp32_out = {sign, exp32, frac32}; + +endmodule + +// Module to convert BF16 (Brain Floating Point) to IEEE-754 FP32 (single precision) +module bf16_to_fp32 ( + input wire [15:0] bf16_in, // BF16: 1 sign, 8 exponent, 7 fraction + output wire [31:0] fp32_out // FP32: 1 sign, 8 exponent, 23 fraction +); + // Extract BF16 components + wire sign = bf16_in[15]; + wire [7:0] exponent = bf16_in[14:7]; + wire [6:0] fraction = bf16_in[6:0]; + + // We simply need to extend the fraction with zeros + wire [7:0] fp32_exponent = exponent; + wire [22:0] fp32_fraction = {fraction, 16'b0}; + + // Final FP32 output + assign fp32_out = {sign, fp32_exponent, fp32_fraction}; + +endmodule + +module VX_tcu_fedp_dsp #( + parameter LATENCY = 1, + parameter N = 1 +) ( + input wire clk, + input wire reset, + input wire enable, + + input wire[2:0] fmt_s, + input wire[2:0] fmt_d, + + input wire [N-1:0][`XLEN-1:0] a_row, + input wire [N-1:0][`XLEN-1:0] b_col, + input wire [`XLEN-1:0] c_val, + output wire [`XLEN-1:0] d_val +); + localparam TCK = 2 * N; + localparam LEVELS = $clog2(TCK); + + localparam FCVT_LATENCY = 1; + localparam FMUL_LATENCY = 8; + localparam FADD_LATENCY = 11; + localparam FRED_LATENCY = LEVELS * FADD_LATENCY; + localparam TOTAL_LATENCY= FCVT_LATENCY + FMUL_LATENCY + FRED_LATENCY + FADD_LATENCY; + `STATIC_ASSERT (LATENCY == 0 || LATENCY == TOTAL_LATENCY, ("invalid latency! expected=%0d, actual=%0d", TOTAL_LATENCY, LATENCY)); + + localparam C_DELAY = FCVT_LATENCY + FMUL_LATENCY + FRED_LATENCY; + + `UNUSED_VAR ({fmt_d, c_val}); + + wire [TCK-1:0][15:0] a_row16, b_col16; + + for (genvar i = 0; i < N; i++) begin : g_unpack + assign a_row16[2*i] = a_row[i][15:0]; + assign a_row16[2*i+1] = a_row[i][31:16]; + assign b_col16[2*i] = b_col[i][15:0]; + assign b_col16[2*i+1] = b_col[i][31:16]; + end + + wire [TCK-1:0][31:0] a_row32, b_col32; + + // convert to fp32 + + for (genvar i = 0; i < TCK; i++) begin : g_cvt + wire [31:0] a_row_fp16, b_col_fp16; + wire [31:0] a_row_bf16, b_col_bf16; + + fp16_to_fp32 cvt_row_fp16 ( + .fp16_in (a_row16[i]), + .fp32_out (a_row_fp16) + ); + + fp16_to_fp32 cvt_col_fp16 ( + .fp16_in (b_col16[i]), + .fp32_out (b_col_fp16) + ); + + bf16_to_fp32 cvt_row_bf16 ( + .bf16_in (a_row16[i]), + .fp32_out (a_row_bf16) + ); + + bf16_to_fp32 cvt_col_bf16 ( + .bf16_in (b_col16[i]), + .fp32_out (b_col_bf16) + ); + + reg [31:0] a_row_sel, a_col_sel; + + always @(*) begin + case (fmt_s) + 3'd1: begin // fp16 + a_row_sel = a_row_fp16; + a_col_sel = b_col_fp16; + end + 3'd2: begin // bf16 + a_row_sel = a_row_bf16; + a_col_sel = b_col_bf16; + end + default: begin + a_row_sel = 'x; + a_col_sel = 'x; + end + endcase + end + + VX_pipe_register #( + .DATAW (32+32), + .DEPTH (FCVT_LATENCY) + ) pipe_cvt ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({a_row_sel, a_col_sel}), + .data_out({a_row32[i], b_col32[i]}) + ); + end + + wire [31:0] mult_result [TCK]; + + // multiplication stage + for (genvar i = 0; i < TCK; i++) begin : g_prod + `ifdef DSP_TEST + wire [63:0] a_h = {32'hffffffff, a_row32[i]}; + wire [63:0] b_h = {32'hffffffff, b_col32[i]}; + reg [63:0] c_h; + reg [4:0] fflags; + `UNUSED_VAR({c_h[63:32], fflags}); + always @(*) begin + dpi_fmul(enable, int'(0), a_h, b_h, 3'b0, c_h, fflags); + end + `BUFFER_EX(mult_result[i], c_h[31:0], enable, 0, FMUL_LATENCY); + `else + xil_fmul fmul ( + .aclk (clk), + .aclken (enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (a_row32[i]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (b_col32[i]), + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (mult_result[i]) + ); + `endif + end + + wire [31:0] red_in [LEVELS+1][TCK]; + + for (genvar i = 0; i < TCK; i++) begin : g_red_inputs + assign red_in[0][i] = mult_result[i]; + end + + // accumulate reduction tree + for (genvar lvl = 0; lvl < LEVELS; lvl++) begin : g_red_tree + localparam integer CURSZ = TCK >> lvl; + localparam integer OUTSZ = CURSZ >> 1; + for (genvar i = 0; i < OUTSZ; i++) begin : g_add + `ifdef DSP_TEST + wire [63:0] a_h = {32'hffffffff, red_in[lvl][2*i+0]}; + wire [63:0] b_h = {32'hffffffff, red_in[lvl][2*i+1]}; + reg [63:0] c_h; + reg [4:0] fflags; + `UNUSED_VAR({c_h[63:32], fflags}); + always @(*) begin + dpi_fadd(enable, int'(0), a_h, b_h, 3'b0, c_h, fflags); + end + `BUFFER_EX(red_in[lvl+1][i], c_h[31:0], enable, 0, FADD_LATENCY); + `else + xil_fadd fadd_red ( + .aclk (clk), + .aclken (enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (red_in[lvl][2*i+0]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (red_in[lvl][2*i+1]), + .s_axis_operation_tvalid (1'b1), + .s_axis_operation_tdata (8'b0), // 0=add + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (red_in[lvl+1][i]) + ); + `endif + end + end + + wire [31:0] delayed_c; + + VX_pipe_register #( + .DATAW (32), + .DEPTH (C_DELAY) + ) pipe_c ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (c_val[31:0]), + .data_out(delayed_c) + ); + + wire [31:0] result; + + // final accumulation +`ifdef DSP_TEST + wire [63:0] a_h = {32'hffffffff, red_in[LEVELS][0]}; + wire [63:0] b_h = {32'hffffffff, delayed_c}; + reg [63:0] c_h; + reg [4:0] fflags; + `UNUSED_VAR({c_h[63:32], fflags}); + always @(*) begin + dpi_fadd(enable, int'(0), a_h, b_h, 3'b0, c_h, fflags); + end + `BUFFER_EX(result, c_h[31:0], enable, 0, FADD_LATENCY); +`else + xil_fadd fadd_acc ( + .aclk (clk), + .aclken (enable), + .s_axis_a_tvalid (1'b1), + .s_axis_a_tdata (red_in[LEVELS][0]), + .s_axis_b_tvalid (1'b1), + .s_axis_b_tdata (delayed_c), + .s_axis_operation_tvalid (1'b1), + .s_axis_operation_tdata (8'b0), // 0=add + `UNUSED_PIN (m_axis_result_tvalid), + .m_axis_result_tdata (result) + ); +`endif + +`ifdef XLEN_64 + // should nan-box when writing to FP registers + assign d_val = {32'hffffffff, result}; +`else + assign d_val = result; +`endif + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_fedp_int.sv b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_int.sv new file mode 100644 index 0000000..49af6c0 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_fedp_int.sv @@ -0,0 +1,189 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_fedp_int #( + parameter LATENCY = 1, + parameter N = 1 +) ( + input wire clk, + input wire reset, + input wire enable, + + input wire[2:0] fmt_s, + input wire[2:0] fmt_d, + + input wire [N-1:0][`XLEN-1:0] a_row, + input wire [N-1:0][`XLEN-1:0] b_col, + input wire [`XLEN-1:0] c_val, + output wire [`XLEN-1:0] d_val +); + localparam LEVELS = $clog2(N); + localparam PRODW = 18; + localparam PSELW = PRODW + 1; // add unsinged guard bit + localparam REDW = `MAX(PRODW + LEVELS, PSELW); + localparam MUL_LATENCY = 2; + localparam ADD_LATENCY = 1; + localparam RED_LATENCY = LEVELS * ADD_LATENCY; + localparam ACC_LATENCY = RED_LATENCY + ADD_LATENCY; + `STATIC_ASSERT (LATENCY == (MUL_LATENCY+ACC_LATENCY), ("invalid parameter!")); + + `UNUSED_VAR ({a_row, b_col, c_val}); + `UNUSED_VAR (fmt_d); + + wire [2:0] delayed_fmt_s; + VX_pipe_register #( + .DATAW (3), + .DEPTH (MUL_LATENCY-1) // remove select stage + ) pipe_fmt_s ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (fmt_s), + .data_out(delayed_fmt_s) + ); + + wire [PSELW-1:0] mult_result [N]; + + // multiplication stage + for (genvar i = 0; i < N; i++) begin : g_prod + reg [16:0] prod_i8_1a, prod_i8_1b; + reg [16:0] prod_u8_1a, prod_u8_1b; + reg [9:0] prod_i4_1a, prod_i4_1b; + reg [9:0] prod_u4_1a, prod_u4_1b; + + always @(posedge clk) begin + if (enable) begin + prod_i8_1a <= ($signed(a_row[i][7:0]) * $signed(b_col[i][7:0])) + + ($signed(a_row[i][15:8]) * $signed(b_col[i][15:8])); + prod_i8_1b <= ($signed(a_row[i][23:16]) * $signed(b_col[i][23:16])) + + ($signed(a_row[i][31:24]) * $signed(b_col[i][31:24])); + end + end + + always @(posedge clk) begin + if (enable) begin + prod_u8_1a <= (a_row[i][7:0] * b_col[i][7:0]) + + (a_row[i][15:8] * b_col[i][15:8]); + prod_u8_1b <= (a_row[i][23:16] * b_col[i][23:16]) + + (a_row[i][31:24] * b_col[i][31:24]); + end + end + + always @(posedge clk) begin + if (enable) begin + prod_i4_1a <= (($signed(a_row[i][3:0]) * $signed(b_col[i][3:0])) + ($signed(a_row[i][7:4]) * $signed(b_col[i][7:4]))) + + (($signed(a_row[i][11:8]) * $signed(b_col[i][11:8])) + ($signed(a_row[i][15:12]) * $signed(b_col[i][15:12]))); + prod_i4_1b <= (($signed(a_row[i][19:16]) * $signed(b_col[i][19:16])) + ($signed(a_row[i][23:20]) * $signed(b_col[i][23:20]))) + + (($signed(a_row[i][27:24]) * $signed(b_col[i][27:24])) + ($signed(a_row[i][31:28]) * $signed(b_col[i][31:28]))); + end + end + + always @(posedge clk) begin + if (enable) begin + prod_u4_1a <= ((a_row[i][3:0] * b_col[i][3:0]) + (a_row[i][7:4] * b_col[i][7:4])) + + ((a_row[i][11:8] * b_col[i][11:8]) + (a_row[i][15:12] * b_col[i][15:12])); + prod_u4_1b <= ((a_row[i][19:16] * b_col[i][19:16]) + (a_row[i][23:20] * b_col[i][23:20])) + + ((a_row[i][27:24] * b_col[i][27:24]) + (a_row[i][31:28] * b_col[i][31:28])); + end + end + + wire [17:0] sum_i8 = $signed(prod_i8_1a) + $signed(prod_i8_1b); + wire [17:0] sum_u8 = prod_u8_1a + prod_u8_1b; + wire [10:0] sum_i4 = $signed(prod_i4_1a) + $signed(prod_i4_1b); + wire [10:0] sum_u4 = prod_u4_1a + prod_u4_1b; + + reg [PSELW-1:0] mult_sel; + always @(*) begin + case (delayed_fmt_s) + 3'd1: mult_sel = PSELW'($signed(sum_i8)); + 3'd2: mult_sel = PSELW'(sum_u8); + 3'd3: mult_sel = PSELW'($signed(sum_i4)); + 3'd4: mult_sel = PSELW'(sum_u4); + default: mult_sel = 'x; + endcase + end + + VX_pipe_register #( + .DATAW (PSELW), + .DEPTH (1) + ) pipe_sel ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (mult_sel), + .data_out (mult_result[i]) + ); + end + + wire [REDW-1:0] red_in [LEVELS+1][N]; + for (genvar i = 0; i < N; i++) begin : g_red_inputs + assign red_in[0][i] = REDW'($signed(mult_result[i])); + end + + // accumulate reduction tree + for (genvar lvl = 0; lvl < LEVELS; lvl++) begin : g_red_tree + localparam integer CURSZ = N >> lvl; + localparam integer OUTSZ = CURSZ >> 1; + for (genvar i = 0; i < OUTSZ; i++) begin : g_add + wire [REDW-1:0] sum = red_in[lvl][2*i+0] + red_in[lvl][2*i+1]; + VX_pipe_register #( + .DATAW (REDW), + .DEPTH (1) + ) pipe_red ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (sum), + .data_out (red_in[lvl+1][i]) + ); + end + end + + wire [31:0] delayed_c; + + VX_pipe_register #( + .DATAW (32), + .DEPTH (MUL_LATENCY + RED_LATENCY) + ) pipe_c ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (c_val[31:0]), + .data_out(delayed_c) + ); + + wire [31:0] result; + + // final accumulation + wire [31:0] acc = 32'($signed(red_in[LEVELS][0])) + delayed_c; + VX_pipe_register #( + .DATAW (32), + .DEPTH (1) + ) pipe_acc ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in (acc), + .data_out(result) + ); + + `ifdef XLEN_64 + // should nan-box when writing to FP registers + assign d_val = {32'hffffffff, result}; + `else + assign d_val = result; + `endif + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_fp.sv b/designs/src/vortex/rtl/tcu/VX_tcu_fp.sv new file mode 100644 index 0000000..77a1a07 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_fp.sv @@ -0,0 +1,221 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_fp import VX_gpu_pkg::*, VX_tcu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_result_if.master result_if +); + `UNUSED_SPARAM (INSTANCE_ID); + + localparam MDATA_WIDTH = UUID_WIDTH + NW_WIDTH + PC_BITS + NUM_REGS_BITS; + +`ifdef TCU_DSP + localparam FCVT_LATENCY = 1; + localparam FMUL_LATENCY = 8; + localparam FADD_LATENCY = 11; + localparam FACC_LATENCY = $clog2(2 * TCU_TC_K + 1) * FADD_LATENCY; + localparam FEDP_LATENCY = FCVT_LATENCY + FMUL_LATENCY + FACC_LATENCY; +`elsif TCU_DPI + localparam FMUL_LATENCY = 2; + localparam FACC_LATENCY = 2; + localparam FEDP_LATENCY = FMUL_LATENCY + FACC_LATENCY; +`elsif TCU_BHF + localparam FMUL_LATENCY = 2; + localparam FADD_LATENCY = 2; + localparam FRND_LATENCY = 1; + localparam FACC_LATENCY = $clog2(2 * TCU_TC_K + 1) * (FADD_LATENCY + FRND_LATENCY); + localparam FEDP_LATENCY = (FMUL_LATENCY + FRND_LATENCY) + 1 + FACC_LATENCY; +`endif + + localparam PIPE_LATENCY = FEDP_LATENCY + 1; + localparam MDATA_QUEUE_DEPTH = 1 << $clog2(PIPE_LATENCY); + + localparam LG_A_BS = $clog2(TCU_A_BLOCK_SIZE); + localparam LG_B_BS = $clog2(TCU_B_BLOCK_SIZE); + localparam OFF_W = $clog2(TCU_BLOCK_CAP); + + wire [3:0] step_m = execute_if.data.op_args.tcu.step_m; + wire [3:0] step_n = execute_if.data.op_args.tcu.step_n; + + wire [3:0] fmt_s = execute_if.data.op_args.tcu.fmt_s; + wire [3:0] fmt_d = execute_if.data.op_args.tcu.fmt_d; + + `UNUSED_VAR ({step_m, step_n, fmt_s, fmt_d}); + + wire [MDATA_WIDTH-1:0] mdata_queue_din, mdata_queue_dout; + wire mdata_queue_full; + + assign mdata_queue_din = { + execute_if.data.uuid, + execute_if.data.wid, + execute_if.data.PC, + execute_if.data.rd + }; + + wire execute_fire = execute_if.valid && execute_if.ready; + wire result_fire = result_if.valid && result_if.ready; + wire fedp_enable, fedp_done; + + // FEDP delay handling + reg [PIPE_LATENCY-1:0] fedp_delay_pipe; + always @(posedge clk) begin + if (reset) begin + fedp_delay_pipe <= '0; + end else begin + if (fedp_enable) begin + fedp_delay_pipe <= fedp_delay_pipe >> 1; + end + if (execute_fire) begin + fedp_delay_pipe[PIPE_LATENCY-1] <= 1; + end + end + end + assign fedp_done = fedp_delay_pipe[0]; + + assign result_if.valid = fedp_done; + assign fedp_enable = ~result_if.valid || result_if.ready; + assign execute_if.ready = ~mdata_queue_full && fedp_enable; + + VX_fifo_queue #( + .DATAW (MDATA_WIDTH), + .DEPTH (MDATA_QUEUE_DEPTH), + .OUT_REG (1) + ) mdata_queue ( + .clk (clk), + .reset (reset), + .push (execute_fire), + .pop (result_fire), + .data_in(mdata_queue_din), + .data_out(mdata_queue_dout), + `UNUSED_PIN(empty), + `UNUSED_PIN(alm_empty), + .full (mdata_queue_full), + `UNUSED_PIN(alm_full), + `UNUSED_PIN(size) + ); + + wire [OFF_W-1:0] a_off = (OFF_W'(step_m) & OFF_W'(TCU_A_SUB_BLOCKS-1)) << LG_A_BS; + wire [OFF_W-1:0] b_off = (OFF_W'(step_n) & OFF_W'(TCU_B_SUB_BLOCKS-1)) << LG_B_BS; + + wire [TCU_TC_M-1:0][TCU_TC_N-1:0][`XLEN-1:0] d_val; + + for (genvar i = 0; i < TCU_TC_M; ++i) begin : g_i + for (genvar j = 0; j < TCU_TC_N; ++j) begin : g_j + + wire [TCU_TC_K-1:0][`XLEN-1:0] a_row = execute_if.data.rs1_data[a_off + i * TCU_TC_K +: TCU_TC_K]; + wire [TCU_TC_K-1:0][`XLEN-1:0] b_col = execute_if.data.rs2_data[b_off + j * TCU_TC_K +: TCU_TC_K]; + wire [`XLEN-1:0] c_val = execute_if.data.rs3_data[i * TCU_TC_N + j]; + + wire [2:0] fmt_s_r, fmt_d_r; + wire [TCU_TC_K-1:0][`XLEN-1:0] a_row_r, b_col_r; + wire [`XLEN-1:0] c_val_r; + + `BUFFER_EX ( + {a_row_r, b_col_r, c_val_r, fmt_s_r, fmt_d_r}, + {a_row, b_col, c_val, fmt_s[2:0], fmt_d[2:0]}, + fedp_enable, + 0, // resetw + 1 // depth + ); + + `ifdef TCU_DPI + VX_tcu_fedp_dpi #( + .LATENCY (FEDP_LATENCY), + .N (TCU_TC_K) + ) fedp ( + .clk (clk), + .reset (reset), + .enable(fedp_enable), + .fmt_s (fmt_s_r), + .fmt_d (fmt_d_r), + .a_row (a_row_r), + .b_col (b_col_r), + .c_val (c_val_r), + .d_val (d_val[i][j]) + ); + `elsif TCU_BHF + VX_tcu_fedp_bhf #( + .LATENCY (FEDP_LATENCY), + .N (TCU_TC_K) + ) fedp ( + .clk (clk), + .reset (reset), + .enable(fedp_enable), + .fmt_s (fmt_s_r), + .fmt_d (fmt_d_r), + .a_row (a_row_r), + .b_col (b_col_r), + .c_val (c_val_r), + .d_val (d_val[i][j]) + ); + `elsif TCU_DSP + VX_tcu_fedp_dsp #( + .LATENCY (FEDP_LATENCY), + .N (TCU_TC_K) + ) fedp ( + .clk (clk), + .reset (reset), + .enable(fedp_enable), + .fmt_s (fmt_s_r), + .fmt_d (fmt_d_r), + .a_row (a_row_r), + .b_col (b_col_r), + .c_val (c_val_r), + .d_val (d_val[i][j]) + ); + `endif + + `ifdef DBG_TRACE_TCU + always @(posedge clk) begin + if (execute_if.valid && execute_if.ready) begin + `TRACE(3, ("%t: %s FEDP-enq: wid=%0d, i=%0d, j=%0d, m=%0d, n=%0d, a_row=", $time, INSTANCE_ID, execute_if.data.wid, i, j, step_m, step_n)) + `TRACE_ARRAY1D(2, "0x%0h", a_row, TCU_TC_K) + `TRACE(3, (", b_col=")); + `TRACE_ARRAY1D(2, "0x%0h", b_col, TCU_TC_K) + `TRACE(3, (", c_val=0x%0h (#%0d)\n", c_val, execute_if.data.uuid)); + end + if (result_if.valid && result_if.ready) begin + `TRACE(3, ("%t: %s FEDP-deq: wid=%0d, i=%0d, j=%0d, d_val=0x%0h (#%0d)\n", $time, INSTANCE_ID, result_if.data.wid, i, j, d_val[i][j], result_if.data.uuid)); + end + end + `endif // DBG_TRACE_TCU + end + end + + assign result_if.data.wb = 1; + assign result_if.data.tmask = {`NUM_THREADS{1'b1}}; + assign result_if.data.data = d_val; + assign result_if.data.pid = 0; + assign result_if.data.sop = 1; + assign result_if.data.eop = 1; + + assign { + result_if.data.uuid, + result_if.data.wid, + result_if.data.PC, + result_if.data.rd + } = mdata_queue_dout; + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_int.sv b/designs/src/vortex/rtl/tcu/VX_tcu_int.sv new file mode 100644 index 0000000..a9ad5f9 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_int.sv @@ -0,0 +1,174 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_int import VX_gpu_pkg::*, VX_tcu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Inputs + VX_execute_if.slave execute_if, + + // Outputs + VX_result_if.master result_if +); + `UNUSED_SPARAM (INSTANCE_ID); + + localparam MDATA_WIDTH = UUID_WIDTH + NW_WIDTH + PC_BITS + NUM_REGS_BITS; + localparam MUL_LATENCY = 2; + localparam ADD_LATENCY = 1; + localparam ACC_LATENCY = $clog2(TCU_TC_K) * ADD_LATENCY + ADD_LATENCY; + localparam FEDP_LATENCY = MUL_LATENCY + ACC_LATENCY; + localparam PIPE_LATENCY = FEDP_LATENCY + 1; + localparam MDATA_QUEUE_DEPTH = 1 << $clog2(PIPE_LATENCY); + + localparam LG_A_BS = $clog2(TCU_A_BLOCK_SIZE); + localparam LG_B_BS = $clog2(TCU_B_BLOCK_SIZE); + localparam OFF_W = $clog2(TCU_BLOCK_CAP); + + wire [3:0] step_m = execute_if.data.op_args.tcu.step_m; + wire [3:0] step_n = execute_if.data.op_args.tcu.step_n; + + wire [3:0] fmt_s = execute_if.data.op_args.tcu.fmt_s; + wire [3:0] fmt_d = execute_if.data.op_args.tcu.fmt_d; + + `UNUSED_VAR ({step_m, step_n, fmt_s, fmt_d}); + + wire [MDATA_WIDTH-1:0] mdata_queue_din, mdata_queue_dout; + wire mdata_queue_full; + + assign mdata_queue_din = { + execute_if.data.uuid, + execute_if.data.wid, + execute_if.data.PC, + execute_if.data.rd + }; + + wire execute_fire = execute_if.valid && execute_if.ready; + wire result_fire = result_if.valid && result_if.ready; + wire fedp_enable, fedp_done; + + // FEDP delay handling + reg [PIPE_LATENCY-1:0] fedp_delay_pipe; + always @(posedge clk) begin + if (reset) begin + fedp_delay_pipe <= '0; + end else begin + if (fedp_enable) begin + fedp_delay_pipe <= fedp_delay_pipe >> 1; + end + if (execute_fire) begin + fedp_delay_pipe[PIPE_LATENCY-1] <= 1; + end + end + end + assign fedp_done = fedp_delay_pipe[0]; + + assign result_if.valid = fedp_done; + assign fedp_enable = ~result_if.valid || result_if.ready; + assign execute_if.ready = ~mdata_queue_full && fedp_enable; + + VX_fifo_queue #( + .DATAW (MDATA_WIDTH), + .DEPTH (MDATA_QUEUE_DEPTH), + .OUT_REG (1) + ) mdata_queue ( + .clk (clk), + .reset (reset), + .push (execute_fire), + .pop (result_fire), + .data_in(mdata_queue_din), + .data_out(mdata_queue_dout), + `UNUSED_PIN(empty), + `UNUSED_PIN(alm_empty), + .full (mdata_queue_full), + `UNUSED_PIN(alm_full), + `UNUSED_PIN(size) + ); + + wire [OFF_W-1:0] a_off = (OFF_W'(step_m) & OFF_W'(TCU_A_SUB_BLOCKS-1)) << LG_A_BS; + wire [OFF_W-1:0] b_off = (OFF_W'(step_n) & OFF_W'(TCU_B_SUB_BLOCKS-1)) << LG_B_BS; + + wire [TCU_TC_M-1:0][TCU_TC_N-1:0][`XLEN-1:0] d_val; + + for (genvar i = 0; i < TCU_TC_M; ++i) begin : g_i + for (genvar j = 0; j < TCU_TC_N; ++j) begin : g_j + + wire [TCU_TC_K-1:0][`XLEN-1:0] a_row = execute_if.data.rs1_data[a_off + i * TCU_TC_K +: TCU_TC_K]; + wire [TCU_TC_K-1:0][`XLEN-1:0] b_col = execute_if.data.rs2_data[b_off + j * TCU_TC_K +: TCU_TC_K]; + wire [`XLEN-1:0] c_val = execute_if.data.rs3_data[i * TCU_TC_N + j]; + + wire [2:0] fmt_s_r, fmt_d_r; + wire [TCU_TC_K-1:0][`XLEN-1:0] a_row_r, b_col_r; + wire [`XLEN-1:0] c_val_r; + + `BUFFER_EX ( + {a_row_r, b_col_r, c_val_r, fmt_s_r, fmt_d_r}, + {a_row, b_col, c_val, fmt_s[2:0], fmt_d[2:0]}, + fedp_enable, + 0, // resetw + 1 // depth + ); + + VX_tcu_fedp_int #( + .LATENCY (FEDP_LATENCY), + .N (TCU_TC_K) + ) fedp ( + .clk (clk), + .reset (reset), + .enable(fedp_enable), + .fmt_s (fmt_s_r), + .fmt_d (fmt_d_r), + .a_row (a_row_r), + .b_col (b_col_r), + .c_val (c_val_r), + .d_val (d_val[i][j]) + ); + + `ifdef DBG_TRACE_TCU + always @(posedge clk) begin + if (execute_if.valid && execute_if.ready) begin + `TRACE(3, ("%t: %s FEDP-enq: wid=%0d, i=%0d, j=%0d, m=%0d, n=%0d, a_row=", $time, INSTANCE_ID, execute_if.data.wid, i, j, step_m, step_n)) + `TRACE_ARRAY1D(2, "0x%0h", a_row, TCU_TC_K) + `TRACE(3, (", b_col=")); + `TRACE_ARRAY1D(2, "0x%0h", b_col, TCU_TC_K) + `TRACE(3, (", c_val=0x%0h (#%0d)\n", c_val, execute_if.data.uuid)); + end + if (result_if.valid && result_if.ready) begin + `TRACE(3, ("%t: %s FEDP-deq: wid=%0d, i=%0d, j=%0d, d_val=0x%0h (#%0d)\n", $time, INSTANCE_ID, result_if.data.wid, i, j, d_val[i][j], result_if.data.uuid)); + end + end + `endif // DBG_TRACE_TCU + end + end + + assign result_if.data.wb = 1; + assign result_if.data.tmask = {`NUM_THREADS{1'b1}}; + assign result_if.data.data = d_val; + assign result_if.data.pid = 0; + assign result_if.data.sop = 1; + assign result_if.data.eop = 1; + + assign { + result_if.data.uuid, + result_if.data.wid, + result_if.data.PC, + result_if.data.rd + } = mdata_queue_dout; + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_pkg.sv b/designs/src/vortex/rtl/tcu/VX_tcu_pkg.sv new file mode 100644 index 0000000..bd82aaa --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_pkg.sv @@ -0,0 +1,121 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VX_TCU_PKG_VH +`define VX_TCU_PKG_VH + +`include "VX_define.vh" + +package VX_tcu_pkg; + + import VX_gpu_pkg::*; + + // Set configuration parameters + localparam TCU_NT = `NUM_THREADS; + localparam TCU_NR = 8; + localparam TCU_DP = 0; + + // Supported data types + localparam TCU_FP32_ID = 0; + localparam TCU_FP16_ID = 1; + localparam TCU_BF16_ID = 2; + localparam TCU_I32_ID = 8; + localparam TCU_I8_ID = 9; + localparam TCU_U8_ID = 10; + localparam TCU_I4_ID = 11; + localparam TCU_U4_ID = 12; + + // Tile dimensions + localparam TCU_TILE_CAP = TCU_NT * TCU_NR; + localparam TCU_LG_TILE_CAP = $clog2(TCU_TILE_CAP); + localparam TCU_TILE_EN = TCU_LG_TILE_CAP / 2; + localparam TCU_TILE_EM = TCU_LG_TILE_CAP - TCU_TILE_EN; + + localparam TCU_TILE_M = 1 << TCU_TILE_EM; + localparam TCU_TILE_N = 1 << TCU_TILE_EN; + localparam TCU_TILE_K = TCU_TILE_CAP / ((TCU_TILE_M > TCU_TILE_N) ? TCU_TILE_M : TCU_TILE_N); + + // Block dimensions + localparam TCU_BLOCK_CAP = TCU_NT; + localparam TCU_LG_BLOCK_CAP = $clog2(TCU_BLOCK_CAP); + localparam TCU_BLOCK_EN = TCU_LG_BLOCK_CAP / 2; + localparam TCU_BLOCK_EM = TCU_LG_BLOCK_CAP - TCU_BLOCK_EN; + + localparam TCU_TC_M = 1 << TCU_BLOCK_EM; + localparam TCU_TC_N = 1 << TCU_BLOCK_EN; + localparam TCU_TC_K = (TCU_DP != 0) ? TCU_DP : (TCU_BLOCK_CAP / ((TCU_TC_M > TCU_TC_N) ? TCU_TC_M : TCU_TC_N)); + + // Step counts + localparam TCU_M_STEPS = TCU_TILE_M / TCU_TC_M; + localparam TCU_N_STEPS = TCU_TILE_N / TCU_TC_N; + localparam TCU_K_STEPS = TCU_TILE_K / TCU_TC_K; + + // A micro-tiling + localparam TCU_A_BLOCK_SIZE = TCU_TC_M * TCU_TC_K; + localparam TCU_A_SUB_BLOCKS = TCU_BLOCK_CAP / TCU_A_BLOCK_SIZE; + + // B micro-tiling + localparam TCU_B_BLOCK_SIZE = TCU_TC_K * TCU_TC_N; + localparam TCU_B_SUB_BLOCKS = TCU_BLOCK_CAP / TCU_B_BLOCK_SIZE; + + // Register counts + //localparam TCU_NRA = (TCU_TILE_M * TCU_TILE_K) / TCU_NT; + localparam TCU_NRB = (TCU_TILE_N * TCU_TILE_K) / TCU_NT; + //localparam TCU_NRC = (TCU_TILE_M * TCU_TILE_N) / TCU_NT; + + // Register base addresses + localparam TCU_RA = 0; + localparam TCU_RB = (TCU_NRB == 4) ? 28 : 10; + localparam TCU_RC = (TCU_NRB == 4) ? 10 : 24; + + localparam TCU_UOPS = TCU_M_STEPS * TCU_N_STEPS * TCU_K_STEPS; + + // Tracing info +`ifdef SIMULATION + task trace_fmt(input int level, input [3:0] fmt); + case (fmt) + TCU_FP32_ID: `TRACE(level, ("fp32")) + TCU_FP16_ID: `TRACE(level, ("fp16")) + TCU_BF16_ID: `TRACE(level, ("bf16")) + TCU_I32_ID: `TRACE(level, ("i32")) + TCU_I8_ID: `TRACE(level, ("i8")) + TCU_U8_ID: `TRACE(level, ("u8")) + TCU_I4_ID: `TRACE(level, ("i4")) + TCU_U4_ID: `TRACE(level, ("u4")) + default: `TRACE(level, ("?")) + endcase + endtask + + task trace_ex_op(input int level, + input [INST_OP_BITS-1:0] op_type, + input op_args_t op_args + ); + case (INST_TCU_BITS'(op_type)) + INST_TCU_WMMA: begin + `TRACE(level, ("WMMA.")); + trace_fmt(level, op_args.tcu.fmt_s); + `TRACE(level, (".")); + trace_fmt(level, op_args.tcu.fmt_d); + `TRACE(level, (".%0d.%0d", op_args.tcu.step_m, op_args.tcu.step_n)); + end + default: `TRACE(level, ("?")) + endcase + endtask +`endif + + `DECL_EXECUTE_T (tcu_exe_t, `NUM_TCU_LANES); + `DECL_RESULT_T (tcu_res_t, `NUM_TCU_LANES); + +endpackage + +`endif // VX_TCU_PKG_VH diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_top.sv b/designs/src/vortex/rtl/tcu/VX_tcu_top.sv new file mode 100644 index 0000000..6d3aff0 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_top.sv @@ -0,0 +1,60 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_top import VX_gpu_pkg::*, VX_tcu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Dispatch Interface + input wire execute_valid, + input tcu_exe_t execute_data, + output wire execute_ready, + + // Commit Interface + output wire result_valid, + output tcu_res_t result_data, + input wire result_ready +); + VX_execute_if #( + .data_t (tcu_exe_t) + ) VX_execute_if(); + + VX_result_if #( + .data_t (tcu_res_t) + ) result_if(); + + assign execute_if.valid = execute_valid; + assign execute_if.data = execute_data; + assign execute_ready = execute_if.ready; + + VX_tcu_fp #( + .INSTANCE_ID (INSTANCE_ID) + ) tcu_unit ( + `SCOPE_IO_BIND (0) + .clk (clk), + .reset (reset), + .execute_if (execute_if), + .result_if (result_if) + ); + + assign result_valid = result_if.valid; + assign result_data = result_if.data; + assign result_if.ready = result_ready; + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_unit.sv b/designs/src/vortex/rtl/tcu/VX_tcu_unit.sv new file mode 100644 index 0000000..79b8f0e --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_unit.sv @@ -0,0 +1,115 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_unit import VX_gpu_pkg::*, VX_tcu_pkg::*; #( + parameter `STRING INSTANCE_ID = "" +) ( + `SCOPE_IO_DECL + + input wire clk, + input wire reset, + + // Inputs + VX_dispatch_if.slave dispatch_if [`ISSUE_WIDTH], + + // Outputs + VX_commit_if.master commit_if [`ISSUE_WIDTH] +); + localparam BLOCK_SIZE = `NUM_TCU_BLOCKS; + localparam NUM_LANES = `NUM_TCU_LANES; + localparam PE_COUNT = 2; + + `STATIC_ASSERT (BLOCK_SIZE == `ISSUE_WIDTH, ("must be full issue execution")); + `STATIC_ASSERT (NUM_LANES == `NUM_THREADS, ("must be full warp execution")); + `SCOPE_IO_SWITCH (BLOCK_SIZE); + + VX_execute_if #( + .data_t (tcu_exe_t) + ) per_block_execute_if[BLOCK_SIZE](); + + VX_dispatch_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (3) + ) dispatch_unit ( + .clk (clk), + .reset (reset), + .dispatch_if(dispatch_if), + .execute_if (per_block_execute_if) + ); + + VX_result_if #( + .data_t (tcu_res_t) + ) per_block_result_if[BLOCK_SIZE](); + + for (genvar block_idx = 0; block_idx < BLOCK_SIZE; ++block_idx) begin : g_blocks + + VX_execute_if #( + .data_t (tcu_exe_t) + ) pe_execute_if[PE_COUNT](); + + VX_result_if #( + .data_t (tcu_res_t) + ) pe_result_if[PE_COUNT](); + + VX_pe_switch #( + .PE_COUNT (PE_COUNT), + .NUM_LANES (NUM_LANES), + .ARBITER ("R"), + .REQ_OUT_BUF (0), + .RSP_OUT_BUF (3) + ) pe_switch ( + .clk (clk), + .reset (reset), + .pe_sel (per_block_execute_if[block_idx].data.op_args.tcu.fmt_s[3]), + .execute_in_if (per_block_execute_if[block_idx]), + .result_out_if (per_block_result_if[block_idx]), + .execute_out_if (pe_execute_if), + .result_in_if (pe_result_if) + ); + + VX_tcu_fp #( + .INSTANCE_ID (`SFORMATF(("%s-fp%0d", INSTANCE_ID, block_idx))) + ) tcu_fp ( + `SCOPE_IO_BIND (block_idx) + .clk (clk), + .reset (reset), + .execute_if (pe_execute_if[0]), + .result_if (pe_result_if[0]) + ); + + VX_tcu_int #( + .INSTANCE_ID (`SFORMATF(("%s-int%0d", INSTANCE_ID, block_idx))) + ) tcu_int ( + `SCOPE_IO_BIND (block_idx) + .clk (clk), + .reset (reset), + .execute_if (pe_execute_if[1]), + .result_if (pe_result_if[1]) + ); + end + + VX_gather_unit #( + .BLOCK_SIZE (BLOCK_SIZE), + .NUM_LANES (NUM_LANES), + .OUT_BUF (3) + ) gather_unit ( + .clk (clk), + .reset (reset), + .result_if (per_block_result_if), + .commit_if (commit_if) + ); + +endmodule diff --git a/designs/src/vortex/rtl/tcu/VX_tcu_uops.sv b/designs/src/vortex/rtl/tcu/VX_tcu_uops.sv new file mode 100644 index 0000000..101c3d8 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/VX_tcu_uops.sv @@ -0,0 +1,122 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_uops import +`ifdef EXT_TCU_ENABLE + VX_tcu_pkg::*, +`endif + VX_gpu_pkg::*; ( + input clk, + input reset, + + input ibuffer_t ibuf_in, + output ibuffer_t ibuf_out, + input wire start, + input wire next, + output reg done +); + localparam CTR_W = $clog2(TCU_UOPS); + + localparam LG_N = $clog2(TCU_N_STEPS); + localparam LG_M = $clog2(TCU_M_STEPS); + localparam LG_K = $clog2(TCU_K_STEPS); + + localparam LG_A_SB = $clog2(TCU_A_SUB_BLOCKS); + localparam LG_B_SB = $clog2(TCU_B_SUB_BLOCKS); + + // uop counter + reg [CTR_W-1:0] counter; + + logic [`UP(LG_N)-1:0] n_index; + logic [`UP(LG_M)-1:0] m_index; + logic [`UP(LG_K)-1:0] k_index; + + if (LG_N != 0) begin : g_n_idx + assign n_index = counter[0 +: LG_N]; + end else begin : g_n_idx0 + assign n_index = 0; + end + + if (LG_M != 0) begin : g_m_idx + assign m_index = counter[LG_N +: LG_M]; + end else begin : g_m_idx0 + assign m_index = 0; + end + + if (LG_K != 0) begin : g_k_idx + assign k_index = counter[LG_N + LG_M +: LG_K]; + end else begin : g_k_idx0 + assign k_index = 0; + end + + // Register offsets + wire [CTR_W-1:0] rs1_offset = ((CTR_W'(m_index) >> LG_A_SB) << LG_K) | CTR_W'(k_index); + wire [CTR_W-1:0] rs2_offset = ((CTR_W'(k_index) << LG_N) | CTR_W'(n_index)) >> LG_B_SB; + wire [CTR_W-1:0] rs3_offset = (CTR_W'(m_index) << LG_N) | CTR_W'(n_index); + + // Register calculations + wire [4:0] rs1 = TCU_RA + 5'(rs1_offset); + wire [4:0] rs2 = TCU_RB + 5'(rs2_offset); + wire [4:0] rs3 = TCU_RC + 5'(rs3_offset); + +`ifdef UUID_ENABLE + wire [31:0] uuid_lo = {counter, ibuf_in.uuid[0 +: (32-CTR_W)]}; + wire [UUID_WIDTH-1:0] uuid = {ibuf_in.uuid[UUID_WIDTH-1:32], uuid_lo}; +`else + wire [UUID_WIDTH-1:0] uuid = ibuf_in.uuid; +`endif + + // Output uop generation + assign ibuf_out.uuid = uuid; + assign ibuf_out.tmask = ibuf_in.tmask; + assign ibuf_out.PC = ibuf_in.PC; + assign ibuf_out.ex_type = ibuf_in.ex_type; + assign ibuf_out.op_type = ibuf_in.op_type; + assign ibuf_out.op_args.tcu.fmt_s = ibuf_in.op_args.tcu.fmt_s; + assign ibuf_out.op_args.tcu.fmt_d = ibuf_in.op_args.tcu.fmt_d; + assign ibuf_out.op_args.tcu.step_m = 4'(m_index); + assign ibuf_out.op_args.tcu.step_n = 4'(n_index); + assign ibuf_out.wb = 1; + assign ibuf_out.used_rs = ibuf_in.used_rs; + assign ibuf_out.rs1 = make_reg_num(REG_TYPE_F, rs1); + assign ibuf_out.rs2 = make_reg_num(REG_TYPE_F, rs2); + assign ibuf_out.rs3 = make_reg_num(REG_TYPE_F, rs3); + assign ibuf_out.rd = make_reg_num(REG_TYPE_F, rs3); + `UNUSED_VAR (ibuf_in.wb) + `UNUSED_VAR (ibuf_in.rd) + `UNUSED_VAR (ibuf_in.rs1) + `UNUSED_VAR (ibuf_in.rs2) + `UNUSED_VAR (ibuf_in.rs3) + + reg busy; + + always_ff @(posedge clk) begin + if (reset) begin + counter <= 0; + busy <= 0; + done <= 0; + end else begin + if (~busy && start) begin + busy <= 1; + done <= (TCU_UOPS == 1); + end else if (busy && next) begin + counter <= counter + ((TCU_UOPS > 1) ? 1 : 0); + done <= (counter == CTR_W'(TCU_UOPS-2)); + busy <= ~done; + end + end + end + +endmodule diff --git a/designs/src/vortex/rtl/tcu/bhf/HardFloat_consts.vi b/designs/src/vortex/rtl/tcu/bhf/HardFloat_consts.vi new file mode 100644 index 0000000..2ab8162 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/bhf/HardFloat_consts.vi @@ -0,0 +1,57 @@ + +/*============================================================================ + +This Verilog include file is part of the Berkeley HardFloat IEEE Floating- +Point Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define round_near_even 3'b000 +`define round_minMag 3'b001 +`define round_min 3'b010 +`define round_max 3'b011 +`define round_near_maxMag 3'b100 +`define round_odd 3'b110 + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define floatControlWidth 1 +`define flControl_tininessBeforeRounding 1'b0 +`define flControl_tininessAfterRounding 1'b1 + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +`define flRoundOpt_sigMSBitAlwaysZero 1 +`define flRoundOpt_subnormsAlwaysExact 2 +`define flRoundOpt_neverUnderflows 4 +`define flRoundOpt_neverOverflows 8 diff --git a/designs/src/vortex/rtl/tcu/bhf/HardFloat_localFuncs.vi b/designs/src/vortex/rtl/tcu/bhf/HardFloat_localFuncs.vi new file mode 100644 index 0000000..79606a5 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/bhf/HardFloat_localFuncs.vi @@ -0,0 +1,46 @@ + +/*============================================================================ + +This Verilog include file is part of the Berkeley HardFloat IEEE Floating- +Point Arithmetic Package, Release 1, by John R. Hauser. + +Copyright 2019 The Regents of the University of California. All rights +reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions, and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions, and the following disclaimer in the documentation + and/or other materials provided with the distribution. + + 3. Neither the name of the University nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=============================================================================*/ + +/*---------------------------------------------------------------------------- +*----------------------------------------------------------------------------*/ +// BSG: automatic qualifier allows reuse of local variable storage +// TODO: for systemverilog, should we just use builtin $clog? +function automatic integer clog2; + input integer fa; + + clog2 = $clog2(fa); + +endfunction diff --git a/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_bf16mul.sv b/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_bf16mul.sv new file mode 100644 index 0000000..2b631fc --- /dev/null +++ b/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_bf16mul.sv @@ -0,0 +1,131 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module VX_tcu_bhf_bf16mul ( + input wire enable, + input wire [15:0] a, //BF16 input a + input wire [15:0] b, //BF16 input b + output logic [32:0] y //FP32 Recoded output y +); + + `UNUSED_VAR(enable); + + //BF16 format constants + localparam BF16_EXP_WIDTH = 8; + localparam BF16_SIG_WIDTH = 8; + + //FP32 format constants + localparam FP32_EXP_WIDTH = 8; + localparam FP32_SIG_WIDTH = 24; + + //Control and rounding mode + localparam CONTROL = 1'b1; //Default (tininess after rounding) + localparam [2:0] RNE = 3'b000; //Round Near Even mode + + //Recoded format widths + localparam BF16_REC_WIDTH = BF16_EXP_WIDTH + BF16_SIG_WIDTH + 1; //17-bit + localparam FP32_REC_WIDTH = FP32_EXP_WIDTH + FP32_SIG_WIDTH + 1; //33-bit + + //Recoded input signals + wire [BF16_REC_WIDTH-1:0] a_recoded; + wire [BF16_REC_WIDTH-1:0] b_recoded; + + //Convert BF16 inputs from standard to recoded format + fNToRecFN #( + .expWidth(BF16_EXP_WIDTH), + .sigWidth(BF16_SIG_WIDTH) + ) conv_a ( + .in(a), + .out(a_recoded) + ); + fNToRecFN #( + .expWidth(BF16_EXP_WIDTH), + .sigWidth(BF16_SIG_WIDTH) + ) conv_b ( + .in(b), + .out(b_recoded) + ); + + //Raw multiplication outputs + wire raw_invalidExc; + wire raw_out_isNaN; + wire raw_out_isInf; + wire raw_out_isZero; + wire raw_out_sign; + wire signed [BF16_EXP_WIDTH+1:0] raw_out_sExp; + wire [(BF16_SIG_WIDTH*2 -1):0] raw_out_sig; //16-bits + + //Mul BF16 inputs to BF16 raw (double width sig) + mulRecFNToFullRaw #( + .expWidth(BF16_EXP_WIDTH), + .sigWidth(BF16_SIG_WIDTH) + ) multiplier ( + .control(CONTROL), + .a(a_recoded), + .b(b_recoded), + .invalidExc(raw_invalidExc), + .out_isNaN(raw_out_isNaN), + .out_isInf(raw_out_isInf), + .out_isZero(raw_out_isZero), + .out_sign(raw_out_sign), + .out_sExp(raw_out_sExp), + .out_sig(raw_out_sig) + ); + + wire [FP32_REC_WIDTH-1:0] fp32_recoded; + wire [4:0] fp32_exception_flags; + `UNUSED_VAR(fp32_exception_flags) + + //Round raw BF16 result to recoded FP32 format (Required for feeding into addRecFN) + roundAnyRawFNToRecFN #( + .inExpWidth(BF16_EXP_WIDTH), + .inSigWidth(BF16_SIG_WIDTH*2-1), //15-bits (for 15:0 in_sig instantiation) + .outExpWidth(FP32_EXP_WIDTH), + .outSigWidth(FP32_SIG_WIDTH), + .options(0) + ) bf16_32rounder ( + .control(CONTROL), + .invalidExc(raw_invalidExc), + .infiniteExc(1'b0), + .in_isNaN(raw_out_isNaN), + .in_isInf(raw_out_isInf), + .in_isZero(raw_out_isZero), + .in_sign(raw_out_sign), + .in_sExp(raw_out_sExp), + .in_sig(raw_out_sig), + .roundingMode(RNE), + .out(fp32_recoded), + .exceptionFlags(fp32_exception_flags) + ); + + assign y = fp32_recoded; + + /* + //Final result exception handling (combine flags from both rounding stages) + wire [4:0] combined_flags = bf16_exception_flags | fp32_exception_flags; + `UNUSED_VAR(combined_flags) + wire result_is_inf = 1'b0; //combined_flags[3]; + wire result_is_nan = 1'b0; //combined_flags[4] | (|combined_flags[2:0]); + + always_comb begin + casez({result_is_nan, result_is_inf}) + 2'b1?: y = 33'h07FC00000; //Canonical FP32 quiet NaN + 2'b01: y = y_wo_exp[32] ? 32'hFF800000 : 32'h7F800000; //Signed FP32 infinity + default: y = fp32_recoded; + endcase + end + */ + +endmodule diff --git a/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_fadd.sv b/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_fadd.sv new file mode 100644 index 0000000..a128d24 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_fadd.sv @@ -0,0 +1,159 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" +`include "HardFloat_consts.vi" + +module VX_tcu_bhf_fadd #( + parameter IN_EXPW = 8, + parameter IN_SIGW = 24, // Includes implicit bit + parameter OUT_EXPW = IN_EXPW, + parameter OUT_SIGW = IN_SIGW, // Includes implicit bit + parameter ADD_LATENCY = 1, + parameter RND_LATENCY = 1, + parameter IN_REC = 0, // 0: IEEE754, 1: recoded + parameter OUT_REC = 0, // 0: IEEE754, 1: recoded + parameter IN_FECW = IN_EXPW + IN_SIGW + IN_REC, + parameter OUT_FECW = OUT_EXPW + OUT_SIGW + OUT_REC +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [2:0] frm, + input wire [IN_FECW-1:0] a, + input wire [IN_FECW-1:0] b, + output wire [OUT_FECW-1:0] y, + output wire [4:0] fflags +); + localparam IN_RECW = IN_EXPW + IN_SIGW + 1; + localparam OUT_RECW = OUT_EXPW + OUT_SIGW + 1; + localparam ADD_EXPW = IN_EXPW + 2; + localparam ADD_SIGW = IN_SIGW + 3; + + // Control signals + wire control = `flControl_tininessAfterRounding; /// IEEE 754-2008 + wire subOp = 1'b0; // addition + + wire [IN_RECW-1:0] a_rec, b_rec; + wire s1_invalidExc, s1_isNaN, s1_isInf, s1_isZero, s1_sign; + wire s2_invalidExc, s2_isNaN, s2_isInf, s2_isZero, s2_sign; + wire signed [ADD_EXPW-1:0] s1_sExp, s2_sExp; + wire [ADD_SIGW-1:0] s1_sig, s2_sig; + wire [2:0] s2_frm; + wire [OUT_RECW-1:0] s2_y_rec; + wire [OUT_FECW-1:0] s2_y; + wire [4:0] s2_fflags; + + // Conversion to recoded format + + if (IN_REC) begin : g_in_rec + assign a_rec = a; + assign b_rec = b; + end else begin : g_in_ieee + fNToRecFN #( + .expWidth (IN_EXPW), + .sigWidth (IN_SIGW) + ) from_ieee_a ( + .in (a[IN_RECW-2:0]), + .out (a_rec) + ); + + fNToRecFN #( + .expWidth (IN_EXPW), + .sigWidth (IN_SIGW) + ) from_ieee_b ( + .in (b[IN_RECW-2:0]), + .out (b_rec) + ); + end + + // Raw addition + + addRecFNToRaw #( + .expWidth (IN_EXPW), + .sigWidth (IN_SIGW) + ) adder ( + .control (control), + .subOp (subOp), + .a (a_rec), + .b (b_rec), + .roundingMode (frm), + .invalidExc (s1_invalidExc), + .out_isNaN (s1_isNaN), + .out_isInf (s1_isInf), + .out_isZero (s1_isZero), + .out_sign (s1_sign), + .out_sExp (s1_sExp), + .out_sig (s1_sig) + ); + + VX_pipe_register #( + .DATAW (5 + ADD_EXPW + ADD_SIGW + 3), + .DEPTH (ADD_LATENCY) + ) pipe_add ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({s1_invalidExc, s1_isNaN, s1_isInf, s1_isZero, s1_sign, s1_sExp, s1_sig, frm}), + .data_out({s2_invalidExc, s2_isNaN, s2_isInf, s2_isZero, s2_sign, s2_sExp, s2_sig, s2_frm}) + ); + + // Rounding + + roundAnyRawFNToRecFN #( + .inExpWidth (ADD_EXPW-2), + .inSigWidth (ADD_SIGW-1), + .outExpWidth (OUT_EXPW), + .outSigWidth (OUT_SIGW), + .options (0) + ) rounding ( + .control (control), + .invalidExc (s2_invalidExc), + .infiniteExc (1'b0), + .in_isNaN (s2_isNaN), + .in_isInf (s2_isInf), + .in_isZero (s2_isZero), + .in_sign (s2_sign), + .in_sExp (s2_sExp), + .in_sig (s2_sig), + .roundingMode (s2_frm), + .out (s2_y_rec), + .exceptionFlags(s2_fflags) + ); + + // Conversion from recoded format + + if (OUT_REC) begin : g_out_rec + assign s2_y = s2_y_rec; + end else begin : g_out_ieee + recFNToFN #( + .expWidth (OUT_EXPW), + .sigWidth (OUT_SIGW) + ) to_ieee ( + .in (s2_y_rec), + .out (s2_y) + ); + end + + VX_pipe_register #( + .DATAW (OUT_FECW + 5), + .DEPTH (RND_LATENCY) + ) pipe_rnd ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({s2_y, s2_fflags}), + .data_out({y, fflags}) + ); + +endmodule diff --git a/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_fmul.sv b/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_fmul.sv new file mode 100644 index 0000000..3454671 --- /dev/null +++ b/designs/src/vortex/rtl/tcu/bhf/VX_tcu_bhf_fmul.sv @@ -0,0 +1,156 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" +`include "HardFloat_consts.vi" + +module VX_tcu_bhf_fmul #( + parameter IN_EXPW = 8, + parameter IN_SIGW = 24, // Includes implicit bit + parameter OUT_EXPW = IN_EXPW, + parameter OUT_SIGW = IN_SIGW, // Includes implicit bit + parameter MUL_LATENCY = 1, + parameter RND_LATENCY = 1, + parameter IN_REC = 0, // 0: IEEE754, 1: recoded + parameter OUT_REC = 0, // 0: IEEE754, 1: recoded + parameter IN_FECW = IN_EXPW + IN_SIGW + IN_REC, + parameter OUT_FECW = OUT_EXPW + OUT_SIGW + OUT_REC +) ( + input wire clk, + input wire reset, + input wire enable, + input wire [2:0] frm, + input wire [IN_FECW-1:0] a, + input wire [IN_FECW-1:0] b, + output wire [OUT_FECW-1:0] y, + output wire [4:0] fflags +); + localparam IN_RECW = IN_EXPW + IN_SIGW + 1; + localparam OUT_RECW = OUT_EXPW + OUT_SIGW + 1; + localparam MUL_EXPW = IN_EXPW + 2; + localparam MUL_SIGW = IN_SIGW * 2; + + // Control signals + wire control = `flControl_tininessAfterRounding; /// IEEE 754-2008 + + wire [IN_RECW-1:0] a_rec, b_rec; + wire s1_invalidExc, s1_isNaN, s1_isInf, s1_isZero, s1_sign; + wire s2_invalidExc, s2_isNaN, s2_isInf, s2_isZero, s2_sign; + wire signed [MUL_EXPW-1:0] s1_sExp, s2_sExp; + wire [MUL_SIGW-1:0] s1_sig, s2_sig; + wire [2:0] s2_frm; + wire [OUT_RECW-1:0] s2_y_rec; + wire [OUT_FECW-1:0] s2_y; + wire [4:0] s2_fflags; + + // Conversion to recoded format + + if (IN_REC) begin : g_in_rec + assign a_rec = a; + assign b_rec = b; + end else begin : g_in_ieee + fNToRecFN #( + .expWidth (IN_EXPW), + .sigWidth (IN_SIGW) + ) from_ieee_a ( + .in (a[IN_RECW-2:0]), + .out (a_rec) + ); + + fNToRecFN #( + .expWidth (IN_EXPW), + .sigWidth (IN_SIGW) + ) from_ieee_b ( + .in (b[IN_RECW-2:0]), + .out (b_rec) + ); + end + + // Raw multiplication + + mulRecFNToFullRaw #( + .expWidth (IN_EXPW), + .sigWidth (IN_SIGW) + ) multiplier ( + .control (control), + .a (a_rec), + .b (b_rec), + .invalidExc(s1_invalidExc), + .out_isNaN (s1_isNaN), + .out_isInf (s1_isInf), + .out_isZero(s1_isZero), + .out_sign (s1_sign), + .out_sExp (s1_sExp), + .out_sig (s1_sig) + ); + + VX_pipe_register #( + .DATAW (5 + MUL_EXPW + MUL_SIGW + 3), + .DEPTH (MUL_LATENCY) + ) pipe_add ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({s1_invalidExc, s1_isNaN, s1_isInf, s1_isZero, s1_sign, s1_sExp, s1_sig, frm}), + .data_out({s2_invalidExc, s2_isNaN, s2_isInf, s2_isZero, s2_sign, s2_sExp, s2_sig, s2_frm}) + ); + + // Rounding + + roundAnyRawFNToRecFN #( + .inExpWidth (MUL_EXPW-2), + .inSigWidth (MUL_SIGW-1), + .outExpWidth (OUT_EXPW), + .outSigWidth (OUT_SIGW), + .options (0) + ) rounding ( + .control (control), + .invalidExc (s2_invalidExc), + .infiniteExc (1'b0), + .in_isNaN (s2_isNaN), + .in_isInf (s2_isInf), + .in_isZero (s2_isZero), + .in_sign (s2_sign), + .in_sExp (s2_sExp), + .in_sig (s2_sig), + .roundingMode (s2_frm), + .out (s2_y_rec), + .exceptionFlags(s2_fflags) + ); + + // Conversion from recoded format + + if (OUT_REC) begin : g_out_rec + assign s2_y = s2_y_rec; + end else begin : g_out_ieee + recFNToFN #( + .expWidth (OUT_EXPW), + .sigWidth (OUT_SIGW) + ) to_ieee ( + .in (s2_y_rec), + .out (s2_y) + ); + end + + VX_pipe_register #( + .DATAW (OUT_FECW + 5), + .DEPTH (RND_LATENCY) + ) pipe_rnd ( + .clk (clk), + .reset (reset), + .enable (enable), + .data_in ({s2_y, s2_fflags}), + .data_out({y, fflags}) + ); + +endmodule diff --git a/designs/src/vortex/rtl/tcu/bhf/bsg_counting_leading_zeros.sv b/designs/src/vortex/rtl/tcu/bhf/bsg_counting_leading_zeros.sv new file mode 100644 index 0000000..714329c --- /dev/null +++ b/designs/src/vortex/rtl/tcu/bhf/bsg_counting_leading_zeros.sv @@ -0,0 +1,31 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "VX_define.vh" + +module bsg_counting_leading_zeros #( + parameter width_p = 1, + parameter lg_width_p = `LOG2UP(width_p) +) ( + input wire [width_p-1:0] a_i, + output wire [lg_width_p-1:0] num_zero_o +); + VX_lzc #( + .N (width_p) + ) lzc ( + .data_in (a_i), + .data_out (num_zero_o), + `UNUSED_PIN(valid_out) + ); + +endmodule diff --git a/designs/src/vortex/rtl/util_dpi.vh b/designs/src/vortex/rtl/util_dpi.vh new file mode 100644 index 0000000..74b095a --- /dev/null +++ b/designs/src/vortex/rtl/util_dpi.vh @@ -0,0 +1,33 @@ +// Copyright © 2019-2023 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef UTIL_DPI_VH +`define UTIL_DPI_VH + +`ifdef XLEN_64 +`define INT_TYPE longint +`else +`define INT_TYPE int +`endif + +import "DPI-C" function void dpi_imul(input logic enable, input logic is_signed_a, input logic is_signed_b, input `INT_TYPE a, input `INT_TYPE b, output `INT_TYPE resultl, output `INT_TYPE resulth); +import "DPI-C" function void dpi_idiv(input logic enable, input logic is_signed, input `INT_TYPE a, input `INT_TYPE b, output `INT_TYPE quotient, output `INT_TYPE remainder); + +import "DPI-C" function int dpi_register(); +import "DPI-C" function void dpi_assert(int inst, input logic cond, input int delay); + +import "DPI-C" function void dpi_trace(input int level, input string format /*verilator sformat*/); +import "DPI-C" function void dpi_trace_start(); +import "DPI-C" function void dpi_trace_stop(); + +`endif diff --git a/designs/src/vortex/verilog.mk b/designs/src/vortex/verilog.mk new file mode 100644 index 0000000..aec4911 --- /dev/null +++ b/designs/src/vortex/verilog.mk @@ -0,0 +1,88 @@ + + +# Write file list to disk, don't expand into env +export HW = $(BENCH_DESIGN_HOME)/src/vortex/rtl +export SYNTH_HDL_FRONTEND = slang +export VERILOG_INCLUDE_DIRS = \ + $(HW) \ + $(HW)/cache \ + $(HW)/core \ + $(HW)/fpu \ + $(HW)/interfaces \ + $(HW)/libs \ + $(HW)/mem +export VERILOG_DEFINES = -DSYNTHESIS -DSV_DPI -DMEM_BLOCK_SIZE=16 -DMAX_FANOUT=32 -DLATENCY_IMUL=5 +# Ordering: packages → interfaces → libs → design modules → top +# +# Excluded directories: +# afu/ — vendor AFU wrappers (OPAE/XRT), need external headers +# tcu/ — optional tensor core extension (needs EXT_TCU_ENABLE) +# +# Excluded files: +# Vortex_axi.sv — AXI wrapper around Vortex, not needed for this top +# VX_avs_adapter.sv — Avalon adapter, only used by OPAE AFU +# VX_axi_adapter.sv — AXI adapter, only used by Vortex_axi.sv +# VX_axi_write_ack.sv — AXI helper, only used by VX_axi_adapter +# VX_mem_bank_adapter.sv — not instantiated in Vortex hierarchy +# VX_mem_data_adapter.sv — only used by AFU / Vortex_axi + +# 1) Packages +_PKG_FILES = \ + $(HW)/VX_gpu_pkg.sv \ + $(HW)/VX_trace_pkg.sv \ + $(HW)/fpu/VX_fpu_pkg.sv + +# 2) Interfaces (rtl/interfaces/ + scattered _if.sv in fpu/ and mem/) +_INTF_FILES = \ + $(wildcard $(HW)/interfaces/*.sv) \ + $(HW)/fpu/VX_fpu_csr_if.sv \ + $(HW)/mem/VX_gbar_bus_if.sv \ + $(HW)/mem/VX_lsu_mem_if.sv \ + $(HW)/mem/VX_mem_bus_if.sv + +# 3) Library modules (excluding adapter files not in our hierarchy) +_LIB_FILES = $(filter-out \ + $(HW)/libs/VX_avs_adapter.sv \ + $(HW)/libs/VX_axi_adapter.sv \ + $(HW)/libs/VX_axi_write_ack.sv \ + $(HW)/libs/VX_mem_bank_adapter.sv \ + $(HW)/libs/VX_mem_data_adapter.sv, \ + $(wildcard $(HW)/libs/*.sv)) + +# 4) Cache +_CACHE_FILES = $(wildcard $(HW)/cache/*.sv) + +# 5) FPU (VX_fpu_dpi.sv and VX_fpu_fpnew.sv are ifdef-gated out by SYNTHESIS) +_FPU_FILES = $(filter-out \ + $(HW)/fpu/VX_fpu_csr_if.sv \ + $(HW)/fpu/VX_fpu_pkg.sv, \ + $(wildcard $(HW)/fpu/*.sv)) + +# 6) Memory subsystem (excluding interface files already listed) +_MEM_FILES = $(filter-out \ + $(HW)/mem/VX_gbar_bus_if.sv \ + $(HW)/mem/VX_lsu_mem_if.sv \ + $(HW)/mem/VX_mem_bus_if.sv, \ + $(wildcard $(HW)/mem/*.sv)) + +# 7) Core +_CORE_FILES = $(wildcard $(HW)/core/*.sv) + +# 8) Top-level +_TOP_FILES = \ + $(HW)/VX_cluster.sv \ + $(HW)/VX_socket.sv \ + $(HW)/Vortex.sv + +export VERILOG_FILES = \ + $(_PKG_FILES) \ + $(_INTF_FILES) \ + $(_LIB_FILES) \ + $(_CACHE_FILES) \ + $(_FPU_FILES) \ + $(_MEM_FILES) \ + $(_CORE_FILES) \ + $(_TOP_FILES) + +#export VERILOG_INCLUDE_DIRS := $(sort $(shell find $(VMOD) -type f -name "*.vh" -printf "%h\n" | sort -u)) + diff --git a/runorfs.sh b/runorfs.sh index 45ce8d9..e7f7b16 100755 --- a/runorfs.sh +++ b/runorfs.sh @@ -1,20 +1,21 @@ #!/bin/bash cd OpenROAD-flow-scripts -tag=$(git describe --tags --abbrev=8 2>/dev/null) -if [ -z "$tag" ]; then - echo "Warning: Commit is not on an exact tag." - tag="v3.0-3201-gf53fbce7" # fallback tag or handle error +ORFS_TAG="26Q1-380-g9a13bc567" +LOCAL_TAG=$(git describe --tags --abbrev=9 2>/dev/null) +if [[ "$LOCAL_TAG" != "$ORFS_TAG" ]]; then + echo "Warning: Commit is not on correct tag. Local tag is $LOCAL_TAG" + LOCAL_TAG=$ORFS_TAG # fallback tag or handle error fi -echo "Running OpenROAD flow with tag: ${tag}" +echo "Running OpenROAD flow with tag: ${LOCAL_TAG}" docker run --rm -it \ -u $(id -u ${USER}):$(id -g ${USER}) \ -v $(pwd)/flow:/OpenROAD-flow-scripts/flow \ - -v $(pwd)/..:/OpenROAD-flow-scripts/UCSC_ML_suite \ - -w /OpenROAD-flow-scripts/UCSC_ML_suite \ + -v $(pwd)/..:/OpenROAD-flow-scripts/HighTide \ + -w /OpenROAD-flow-scripts/HighTide \ -e DISPLAY=${DISPLAY} \ -v /tmp/.X11-unix:/tmp/.X11-unix \ -v ${HOME}/.Xauthority:/.Xauthority \ --network host \ --security-opt seccomp=unconfined \ - openroad/orfs:${tag} \ + openroad/orfs:${LOCAL_TAG} "$@" diff --git a/settings.mk b/settings.mk index 1d142b3..27e8986 100644 --- a/settings.mk +++ b/settings.mk @@ -1,6 +1,6 @@ +# Suite specific Variables export BENCH_DESIGN_HOME = $(abspath $(dir $(firstword $(MAKEFILE_LIST)))/designs) -export DEV_FLAG = $(abspath $(dir $(firstword $(MAKEFILE_LIST)))/.dev-run-$(DESIGN_NAME)-$(DEV_RUN_TAG)) -export DEV_DESIGN_HOME ?= $(DESIGN_NICKNAME)/dev +export DEV_DESIGN_HOME := $(DESIGN_NICKNAME)/dev export DESIGN_RESULTS_NAME ?= $(DESIGN_NICKNAME) # Override log, object, reports, and results subdir names (since OpenROAD bases it off of DESIGN_NICKNAME alone) @@ -9,4 +9,7 @@ override OBJECTS_DIR = $(WORK_HOME)/objects/$(PLATFORM)/$(DESIGN_RESULTS_NAME)/$ override REPORTS_DIR = $(WORK_HOME)/reports/$(PLATFORM)/$(DESIGN_RESULTS_NAME)/$(FLOW_VARIANT) override RESULTS_DIR = $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_RESULTS_NAME)/$(FLOW_VARIANT) -export GDS_ALLOW_EMPTY := fakeram.* \ No newline at end of file +# Add fakeram under GDS_ALLOW_EMPTY +ifeq ($(filter fakeram.*,$(GDS_ALLOW_EMPTY)),) +export GDS_ALLOW_EMPTY := $(strip $(GDS_ALLOW_EMPTY) fakeram.*) +endif